diff --git a/.gitignore b/.gitignore index c92d035..47d4afc 100644 --- a/.gitignore +++ b/.gitignore @@ -396,4 +396,4 @@ FodyWeavers.xsd *.msp # JetBrains Rider -*.sln.iml \ No newline at end of file +*.sln.iml diff --git a/thirdparty/.gitignore b/thirdparty/.gitignore new file mode 100644 index 0000000..cdb5169 --- /dev/null +++ b/thirdparty/.gitignore @@ -0,0 +1,8 @@ +!* + +# Visual Studio 2015/2017 cache/options directory +.vs/ +# The packages folder can be ignored because of Package Restore +**/[Pp]ackages/* +# except build/, which is used as an MSBuild target. +!**/[Pp]ackages/build/ diff --git a/thirdparty/capstone/arch/ARM/ARMAddressingModes.h b/thirdparty/capstone/arch/ARM/ARMAddressingModes.h new file mode 100644 index 0000000..16d4b14 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMAddressingModes.h @@ -0,0 +1,784 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + +//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains the ARM addressing mode implementation stuff. +// +//===----------------------------------------------------------------------===// + +#ifndef CS_ARM_ADDRESSINGMODES_H +#define CS_ARM_ADDRESSINGMODES_H + +#include +#include +#include +#include + +#include "../../MathExtras.h" +#include + +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b + +/// ARM_AM - ARM Addressing Mode Stuff +typedef enum ShiftOpc { + ARM_AM_no_shift = 0, + ARM_AM_asr, + ARM_AM_lsl, + ARM_AM_lsr, + ARM_AM_ror, + ARM_AM_rrx, + ARM_AM_uxtw +} ARM_AM_ShiftOpc; + +typedef enum AddrOpc { ARM_AM_sub = 0, ARM_AM_add } ARM_AM_AddrOpc; + +static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op) +{ + return Op == ARM_AM_sub ? "-" : ""; +} + +static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op) +{ + switch (Op) { + default: + assert(0 && "Unknown shift opc!"); + case ARM_AM_asr: + return "asr"; + case ARM_AM_lsl: + return "lsl"; + case ARM_AM_lsr: + return "lsr"; + case ARM_AM_ror: + return "ror"; + case ARM_AM_rrx: + return "rrx"; + case ARM_AM_uxtw: + return "uxtw"; + } +} + +static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op) +{ + switch (Op) { + default: + assert(0 && "Unknown shift opc!"); + case ARM_AM_asr: + return 2; + case ARM_AM_lsl: + return 0; + case ARM_AM_lsr: + return 1; + case ARM_AM_ror: + return 3; + } +} + +typedef enum AMSubMode { + ARM_AM_bad_am_submode = 0, + ARM_AM_ia, + ARM_AM_ib, + ARM_AM_da, + ARM_AM_db +} ARM_AM_SubMode; + +static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_SubMode Mode) +{ + switch (Mode) { + default: + assert(0 && "Unknown addressing sub-mode!"); + case ARM_AM_ia: + return "ia"; + case ARM_AM_ib: + return "ib"; + case ARM_AM_da: + return "da"; + case ARM_AM_db: + return "db"; + } +} + +/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. +/// +static inline unsigned ARM_AM_rotr32(unsigned Val, unsigned Amt) +{ + return (Val >> Amt) | (Val << ((32 - Amt) & 31)); +} + +/// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. +/// +static inline unsigned ARM_AM_rotl32(unsigned Val, unsigned Amt) +{ + return (Val << Amt) | (Val >> ((32 - Amt) & 31)); +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #1: shift_operand with registers +//===--------------------------------------------------------------------===// +// +// This 'addressing mode' is used for arithmetic instructions. It can +// represent things like: +// reg +// reg [asr|lsl|lsr|ror|rrx] reg +// reg [asr|lsl|lsr|ror|rrx] imm +// +// This is stored three operands [rega, regb, opc]. The first is the base +// reg, the second is the shift amount (or reg0 if not present or imm). The +// third operand encodes the shift opcode and the imm if a reg isn't present. +// +static inline unsigned ARM_AM_getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm) +{ + return ShOp | (Imm << 3); +} + +static inline unsigned ARM_AM_getSORegOffset(unsigned Op) +{ + return Op >> 3; +} + +static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op) +{ + return (ARM_AM_ShiftOpc)(Op & 7); +} + +/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return +/// the 8-bit imm value. +static inline unsigned ARM_AM_getSOImmValImm(unsigned Imm) +{ + return Imm & 0xFF; +} + +/// getSOImmValRot - Given an encoded imm field for the reg/imm form, return +/// the rotate amount. +static inline unsigned ARM_AM_getSOImmValRot(unsigned Imm) +{ + return (Imm >> 8) * 2; +} + +/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, +/// computing the rotate amount to use. If this immediate value cannot be +/// handled with a single shifter-op, determine a good rotate amount that will +/// take a maximal chunk of bits out of the immediate. +static inline unsigned ARM_AM_getSOImmValRotate(unsigned Imm) +{ + // 8-bit (or less) immediates are trivially shifter_operands with a rotate + // of zero. + if ((Imm & ~255U) == 0) + return 0; + + // Use CTZ to compute the rotate amount. + unsigned TZ = CountTrailingZeros_32(Imm); + + // Rotate amount must be even. Something like 0x200 must be rotated 8 bits, + // not 9. + unsigned RotAmt = TZ & ~1; + + // If we can handle this spread, return it. + if ((ARM_AM_rotr32(Imm, RotAmt) & ~255U) == 0) + return (32 - RotAmt) & 31; // HW rotates right, not left. + + // For values like 0xF000000F, we should ignore the low 6 bits, then + // retry the hunt. + if (Imm & 63U) { + unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U); + unsigned RotAmt2 = TZ2 & ~1; + if ((ARM_AM_rotr32(Imm, RotAmt2) & ~255U) == 0) + return (32 - RotAmt2) & + 31; // HW rotates right, not left. + } + + // Otherwise, we have no way to cover this span of bits with a single + // shifter_op immediate. Return a chunk of bits that will be useful to + // handle. + return (32 - RotAmt) & 31; // HW rotates right, not left. +} + +/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit +/// into an shifter_operand immediate operand, return the 12-bit encoding for +/// it. If not, return -1. +static inline int ARM_AM_getSOImmVal(unsigned Arg) +{ + // 8-bit (or less) immediates are trivially shifter_operands with a rotate + // of zero. + if ((Arg & ~255U) == 0) + return Arg; + + unsigned RotAmt = ARM_AM_getSOImmValRotate(Arg); + + // If this cannot be handled with a single shifter_op, bail out. + if (ARM_AM_rotr32(~255U, RotAmt) & Arg) + return -1; + + // Encode this correctly. + return ARM_AM_rotl32(Arg, RotAmt) | ((RotAmt >> 1) << 8); +} + +/// isSOImmTwoPartVal - Return true if the specified value can be obtained by +/// or'ing together two SOImmVal's. +static inline bool ARM_AM_isSOImmTwoPartVal(unsigned V) +{ + // If this can be handled with a single shifter_op, bail out. + V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V; + if (V == 0) + return false; + + // If this can be handled with two shifter_op's, accept. + V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V; + return V == 0; +} + +/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, +/// return the first chunk of it. +static inline unsigned ARM_AM_getSOImmTwoPartFirst(unsigned V) +{ + return ARM_AM_rotr32(255U, ARM_AM_getSOImmValRotate(V)) & V; +} + +/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, +/// return the second chunk of it. +static inline unsigned ARM_AM_getSOImmTwoPartSecond(unsigned V) +{ + // Mask out the first hunk. + V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V; + + // Take what's left. + + return V; +} + +/// isSOImmTwoPartValNeg - Return true if the specified value can be obtained +/// by two SOImmVal, that -V = First + Second. +/// "R+V" can be optimized to (sub (sub R, First), Second). +/// "R=V" can be optimized to (sub (mvn R, ~(-First)), Second). +static inline bool ARM_AM_isSOImmTwoPartValNeg(unsigned V) +{ + unsigned First; + if (!ARM_AM_isSOImmTwoPartVal(-V)) + return false; + // Return false if ~(-First) is not a SoImmval. + First = ARM_AM_getSOImmTwoPartFirst(-V); + First = ~(-First); + return !(ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(First)) & First); +} + +/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed +/// by a left shift. Returns the shift amount to use. +static inline unsigned ARM_AM_getThumbImmValShift(unsigned Imm) +{ + // 8-bit (or less) immediates are trivially immediate operand with a shift + // of zero. + if ((Imm & ~255U) == 0) + return 0; + + // Use CTZ to compute the shift amount. + return CountTrailingZeros_32(Imm); +} + +/// isThumbImmShiftedVal - Return true if the specified value can be obtained +/// by left shifting a 8-bit immediate. +static inline bool ARM_AM_isThumbImmShiftedVal(unsigned V) +{ + // If this can be handled with + V = (~255U << ARM_AM_getThumbImmValShift(V)) & V; + return V == 0; +} + +/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed +/// by a left shift. Returns the shift amount to use. +static inline unsigned ARM_AM_getThumbImm16ValShift(unsigned Imm) +{ + // 16-bit (or less) immediates are trivially immediate operand with a shift + // of zero. + if ((Imm & ~65535U) == 0) + return 0; + + // Use CTZ to compute the shift amount. + return CountTrailingZeros_32(Imm); +} + +/// isThumbImm16ShiftedVal - Return true if the specified value can be +/// obtained by left shifting a 16-bit immediate. +static inline bool ARM_AM_isThumbImm16ShiftedVal(unsigned V) +{ + // If this can be handled with + V = (~65535U << ARM_AM_getThumbImm16ValShift(V)) & V; + return V == 0; +} + +/// getThumbImmNonShiftedVal - If V is a value that satisfies +/// isThumbImmShiftedVal, return the non-shiftd value. +static inline unsigned ARM_AM_getThumbImmNonShiftedVal(unsigned V) +{ + return V >> ARM_AM_getThumbImmValShift(V); +} + +/// getT2SOImmValSplat - Return the 12-bit encoded representation +/// if the specified value can be obtained by splatting the low 8 bits +/// into every other byte or every byte of a 32-bit value. i.e., +/// 00000000 00000000 00000000 abcdefgh control = 0 +/// 00000000 abcdefgh 00000000 abcdefgh control = 1 +/// abcdefgh 00000000 abcdefgh 00000000 control = 2 +/// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 +/// Return -1 if none of the above apply. +/// See ARM Reference Manual A6.3.2. +static inline int ARM_AM_getT2SOImmValSplatVal(unsigned V) +{ + unsigned u, Vs, Imm; + // control = 0 + if ((V & 0xffffff00) == 0) + return V; + + // If the value is zeroes in the first byte, just shift those off + Vs = ((V & 0xff) == 0) ? V >> 8 : V; + // Any passing value only has 8 bits of payload, splatted across the word + Imm = Vs & 0xff; + // Likewise, any passing values have the payload splatted into the 3rd byte + u = Imm | (Imm << 16); + + // control = 1 or 2 + if (Vs == u) + return (((Vs == V) ? 1 : 2) << 8) | Imm; + + // control = 3 + if (Vs == (u | (u << 8))) + return (3 << 8) | Imm; + + return -1; +} + +/// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the +/// specified value is a rotated 8-bit value. Return -1 if no rotation +/// encoding is possible. +/// See ARM Reference Manual A6.3.2. +static inline int ARM_AM_getT2SOImmValRotateVal(unsigned V) +{ + unsigned RotAmt = CountLeadingZeros_32(V); + if (RotAmt >= 24) + return -1; + + // If 'Arg' can be handled with a single shifter_op return the value. + if ((ARM_AM_rotr32(0xff000000U, RotAmt) & V) == V) + return (ARM_AM_rotr32(V, 24 - RotAmt) & 0x7f) | + ((RotAmt + 8) << 7); + + return -1; +} + +/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit +/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit +/// encoding for it. If not, return -1. +/// See ARM Reference Manual A6.3.2. +static inline int ARM_AM_getT2SOImmVal(unsigned Arg) +{ + // If 'Arg' is an 8-bit splat, then get the encoded value. + int Splat = ARM_AM_getT2SOImmValSplatVal(Arg); + if (Splat != -1) + return Splat; + + // If 'Arg' can be handled with a single shifter_op return the value. + int Rot = ARM_AM_getT2SOImmValRotateVal(Arg); + if (Rot != -1) + return Rot; + + return -1; +} + +static inline unsigned ARM_AM_getT2SOImmValRotate(unsigned V) +{ + if ((V & ~255U) == 0) + return 0; + // Use CTZ to compute the rotate amount. + unsigned RotAmt = CountTrailingZeros_32(V); + return (32 - RotAmt) & 31; +} + +static inline bool ARM_AM_isT2SOImmTwoPartVal(unsigned Imm) +{ + unsigned V = Imm; + // Passing values can be any combination of splat values and shifter + // values. If this can be handled with a single shifter or splat, bail + // out. Those should be handled directly, not with a two-part val. + if (ARM_AM_getT2SOImmValSplatVal(V) != -1) + return false; + V = ARM_AM_rotr32(~255U, ARM_AM_getT2SOImmValRotate(V)) & V; + if (V == 0) + return false; + + // If this can be handled as an immediate, accept. + if (ARM_AM_getT2SOImmVal(V) != -1) + return true; + + // Likewise, try masking out a splat value first. + V = Imm; + if (ARM_AM_getT2SOImmValSplatVal(V & 0xff00ff00U) != -1) + V &= ~0xff00ff00U; + else if (ARM_AM_getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1) + V &= ~0x00ff00ffU; + // If what's left can be handled as an immediate, accept. + if (ARM_AM_getT2SOImmVal(V) != -1) + return true; + + // Otherwise, do not accept. + return false; +} + +static inline unsigned ARM_AM_getT2SOImmTwoPartFirst(unsigned Imm) +{ + // Try a shifter operand as one part + unsigned V = ARM_AM_rotr32(~255, ARM_AM_getT2SOImmValRotate(Imm)) & Imm; + // If the rest is encodable as an immediate, then return it. + if (ARM_AM_getT2SOImmVal(V) != -1) + return V; + + // Try masking out a splat value first. + if (ARM_AM_getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1) + return Imm & 0xff00ff00U; + + // The other splat is all that's left as an option. + + return Imm & 0x00ff00ffU; +} + +static inline unsigned ARM_AM_getT2SOImmTwoPartSecond(unsigned Imm) +{ + // Mask out the first hunk + Imm ^= ARM_AM_getT2SOImmTwoPartFirst(Imm); + // Return what's left + + return Imm; +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #2 +//===--------------------------------------------------------------------===// +// +// This is used for most simple load/store instructions. +// +// addrmode2 := reg +/- reg shop imm +// addrmode2 := reg +/- imm12 +// +// The first operand is always a Reg. The second operand is a reg if in +// reg/reg form, otherwise it's reg#0. The third field encodes the operation +// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The +// fourth operand 16-17 encodes the index mode. +// +// If this addressing mode is a frame index (before prolog/epilog insertion +// and code rewriting), this operand will have the form: FI#, reg0, +// with no shift amount for the frame offset. +// +static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, + ARM_AM_ShiftOpc SO, unsigned IdxMode) +{ + bool isSub = Opc == ARM_AM_sub; + return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16); +} + +static inline unsigned ARM_AM_getAM2Offset(unsigned AM2Opc) +{ + return AM2Opc & ((1 << 12) - 1); +} + +static inline ARM_AM_AddrOpc ARM_AM_getAM2Op(unsigned AM2Opc) +{ + return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add; +} + +static inline ARM_AM_ShiftOpc ARM_AM_getAM2ShiftOpc(unsigned AM2Opc) +{ + return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7); +} + +static inline unsigned ARM_AM_getAM2IdxMode(unsigned AM2Opc) +{ + return (AM2Opc >> 16); +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #3 +//===--------------------------------------------------------------------===// +// +// This is used for sign-extending loads, and load/store-pair instructions. +// +// addrmode3 := reg +/- reg +// addrmode3 := reg +/- imm8 +// +// The first operand is always a Reg. The second operand is a reg if in +// reg/reg form, otherwise it's reg#0. The third field encodes the operation +// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the +// index mode. +/// getAM3Opc - This function encodes the addrmode3 opc field. +static inline unsigned ARM_AM_getAM3Opc(ARM_AM_AddrOpc Opc, + unsigned char Offset, unsigned IdxMode) +{ + bool isSub = Opc == ARM_AM_sub; + return ((int)isSub << 8) | Offset | (IdxMode << 9); +} + +static inline unsigned char ARM_AM_getAM3Offset(unsigned AM3Opc) +{ + return AM3Opc & 0xFF; +} + +static inline ARM_AM_AddrOpc ARM_AM_getAM3Op(unsigned AM3Opc) +{ + return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; +} + +static inline unsigned ARM_AM_getAM3IdxMode(unsigned AM3Opc) +{ + return (AM3Opc >> 9); +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #4 +//===--------------------------------------------------------------------===// +// +// This is used for load / store multiple instructions. +// +// addrmode4 := reg, +// +// The four modes are: +// IA - Increment after +// IB - Increment before +// DA - Decrement after +// DB - Decrement before +// For VFP instructions, only the IA and DB modes are valid. +static inline ARM_AM_SubMode ARM_AM_getAM4SubMode(unsigned Mode) +{ + return (ARM_AM_SubMode)(Mode & 0x7); +} + +static inline unsigned ARM_AM_getAM4ModeImm(ARM_AM_SubMode SubMode) +{ + return (int)SubMode; +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #5 +//===--------------------------------------------------------------------===// +// +// This is used for coprocessor instructions, such as FP load/stores. +// +// addrmode5 := reg +/- imm8*4 +// +// The first operand is always a Reg. The second operand encodes the +// operation (add or subtract) in bit 8 and the immediate in bits 0-7. +/// getAM5Opc - This function encodes the addrmode5 opc field. +static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, + unsigned char Offset) +{ + bool isSub = Opc == ARM_AM_sub; + return ((int)isSub << 8) | Offset; +} + +static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc) +{ + return AM5Opc & 0xFF; +} + +static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc) +{ + return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #5 FP16 +//===--------------------------------------------------------------------===// +// +// This is used for coprocessor instructions, such as 16-bit FP load/stores. +// +// addrmode5fp16 := reg +/- imm8*2 +// +// The first operand is always a Reg. The second operand encodes the +// operation (add or subtract) in bit 8 and the immediate in bits 0-7. +/// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field. +static inline unsigned ARM_AM_getAM5FP16Opc(ARM_AM_AddrOpc Opc, + unsigned char Offset) +{ + bool isSub = Opc == ARM_AM_sub; + return ((int)isSub << 8) | Offset; +} + +static inline unsigned char ARM_AM_getAM5FP16Offset(unsigned AM5Opc) +{ + return AM5Opc & 0xFF; +} + +static inline ARM_AM_AddrOpc ARM_AM_getAM5FP16Op(unsigned AM5Opc) +{ + return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #6 +//===--------------------------------------------------------------------===// +// +// This is used for NEON load / store instructions. +// +// addrmode6 := reg with optional alignment +// +// This is stored in two operands [regaddr, align]. The first is the +// address register. The second operand is the value of the alignment +// specifier in bytes or zero if no explicit alignment. +// Valid alignments depend on the specific instruction. +//===--------------------------------------------------------------------===// +// NEON/MVE Modified Immediates +//===--------------------------------------------------------------------===// +// +// Several NEON and MVE instructions (e.g., VMOV) take a "modified immediate" +// vector operand, where a small immediate encoded in the instruction +// specifies a full NEON vector value. These modified immediates are +// represented here as encoded integers. The low 8 bits hold the immediate +// value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold +// the "Cmode" field of the instruction. The interfaces below treat the +// Op and Cmode values as a single 5-bit value. +static inline unsigned ARM_AM_createVMOVModImm(unsigned OpCmode, unsigned Val) +{ + return (OpCmode << 8) | Val; +} + +static inline unsigned ARM_AM_getVMOVModImmOpCmode(unsigned ModImm) +{ + return (ModImm >> 8) & 0x1f; +} + +static inline unsigned ARM_AM_getVMOVModImmVal(unsigned ModImm) +{ + return ModImm & 0xff; +} + +/// decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the +/// element value and the element size in bits. (If the element size is +/// smaller than the vector, it is splatted into all the elements.) +static inline uint64_t ARM_AM_decodeVMOVModImm(unsigned ModImm, + unsigned *EltBits) +{ + unsigned OpCmode = ARM_AM_getVMOVModImmOpCmode(ModImm); + unsigned Imm8 = ARM_AM_getVMOVModImmVal(ModImm); + uint64_t Val = 0; + + if (OpCmode == 0xe) { + // 8-bit vector elements + Val = Imm8; + *EltBits = 8; + } else if ((OpCmode & 0xc) == 0x8) { + // 16-bit vector elements + unsigned ByteNum = (OpCmode & 0x6) >> 1; + Val = Imm8 << (8 * ByteNum); + *EltBits = 16; + } else if ((OpCmode & 0x8) == 0) { + // 32-bit vector elements, zero with one byte set + unsigned ByteNum = (OpCmode & 0x6) >> 1; + Val = Imm8 << (8 * ByteNum); + *EltBits = 32; + } else if ((OpCmode & 0xe) == 0xc) { + // 32-bit vector elements, one byte with low bits set + unsigned ByteNum = 1 + (OpCmode & 0x1); + Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); + *EltBits = 32; + } else if (OpCmode == 0x1e) { + // 64-bit vector elements + for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) { + if ((ModImm >> ByteNum) & 1) + Val |= (uint64_t)0xff << (8 * ByteNum); + } + *EltBits = 64; + } else { + assert(0 && "Unsupported VMOV immediate"); + } + return Val; +} + +// Generic validation for single-byte immediate (0X00, 00X0, etc). +static inline bool ARM_AM_isNEONBytesplat(unsigned Value, unsigned Size) +{ + unsigned count = 0; + for (unsigned i = 0; i < Size; ++i) { + if (Value & 0xff) + count++; + Value >>= 8; + } + return count == 1; +} + +/// Checks if Value is a correct immediate for instructions like VBIC/VORR. +static inline bool ARM_AM_isNEONi16splat(unsigned Value) +{ + if (Value > 0xffff) + return false; + // i16 value with set bits only in one byte X0 or 0X. + return Value == 0 || ARM_AM_isNEONBytesplat(Value, 2); +} + +// Encode NEON 16 bits Splat immediate for instructions like VBIC/VORR +static inline unsigned ARM_AM_encodeNEONi16splat(unsigned Value) +{ + if (Value >= 0x100) + Value = (Value >> 8) | 0xa00; + else + Value |= 0x800; + return Value; +} + +/// Checks if Value is a correct immediate for instructions like VBIC/VORR. +static inline bool ARM_AM_isNEONi32splat(unsigned Value) +{ + // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. + return Value == 0 || ARM_AM_isNEONBytesplat(Value, 4); +} + +/// Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR. +static inline unsigned ARM_AM_encodeNEONi32splat(unsigned Value) +{ + if (Value >= 0x100 && Value <= 0xff00) + Value = (Value >> 8) | 0x200; + else if (Value > 0xffff && Value <= 0xff0000) + Value = (Value >> 16) | 0x400; + else if (Value > 0xffffff) + Value = (Value >> 24) | 0x600; + return Value; +} + +//===--------------------------------------------------------------------===// +// Floating-point Immediates +// +static inline float ARM_AM_getFPImmFloat(unsigned Imm) +{ + // We expect an 8-bit binary encoding of a floating-point number here. + + uint8_t Sign = (Imm >> 7) & 0x1; + uint8_t Exp = (Imm >> 4) & 0x7; + uint8_t Mantissa = Imm & 0xf; + + // 8-bit FP IEEE Float Encoding + // abcd efgh aBbbbbbc defgh000 00000000 00000000 + // + // where B = NOT(b); + uint32_t I = 0; + I |= Sign << 31; + I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; + I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; + I |= (Exp & 0x3) << 23; + I |= Mantissa << 19; + return BitsToFloat(I); +} + +#endif // CS_ARM_ADDRESSINGMODES_H diff --git a/thirdparty/capstone/arch/ARM/ARMBaseInfo.c b/thirdparty/capstone/arch/ARM/ARMBaseInfo.c new file mode 100644 index 0000000..fc15921 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMBaseInfo.c @@ -0,0 +1,101 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + +//===-- ARMBaseInfo.cpp - ARM Base encoding information------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file provides basic encoding and assembly information for ARM. +// +//===----------------------------------------------------------------------===// +#include +#include +#include +#include + +#include "ARMBaseInfo.h" +#include "ARMMapping.h" + +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b + +const char *get_pred_mask(ARM_PredBlockMask pred_mask) +{ + switch (pred_mask) { + default: + assert(0 && "pred_mask not handled."); + case ARM_T: + return "T"; + case ARM_TT: + return "TT"; + case ARM_TE: + return "TE"; + case ARM_TTT: + return "TTT"; + case ARM_TTE: + return "TTE"; + case ARM_TEE: + return "TEE"; + case ARM_TET: + return "TET"; + case ARM_TTTT: + return "TTTT"; + case ARM_TTTE: + return "TTTE"; + case ARM_TTEE: + return "TTEE"; + case ARM_TTET: + return "TTET"; + case ARM_TEEE: + return "TEEE"; + case ARM_TEET: + return "TEET"; + case ARM_TETT: + return "TETT"; + case ARM_TETE: + return "TETE"; + } +} + +#define GET_MCLASSSYSREG_IMPL +#include "ARMGenSystemRegister.inc" + +// lookup system register using 12-bit SYSm value. +// Note: the search is uniqued using M1 mask +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) +{ + return ARMSysReg_lookupMClassSysRegByM1Encoding12(SYSm); +} + +// returns APSR with _ qualifier. +// Note: ARMv7-M deprecates using MSR APSR without a _ qualifier +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) +{ + return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 9) | + (SYSm & 0xFF)); +} + +// lookup system registers using 8-bit SYSm value +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) +{ + return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 8) | + (SYSm & 0xFF)); +} diff --git a/thirdparty/capstone/arch/ARM/ARMBaseInfo.h b/thirdparty/capstone/arch/ARM/ARMBaseInfo.h new file mode 100644 index 0000000..02f7a81 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMBaseInfo.h @@ -0,0 +1,573 @@ +//===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains small standalone helper functions and enum definitions for +// the ARM target useful for the compiler back-end and the MC libraries. +// As such, it deliberately does not include references to LLVM core +// code gen types, passes, etc.. +// +//===----------------------------------------------------------------------===// + +#ifndef CS_ARM_BASEINFO_H +#define CS_ARM_BASEINFO_H + +#include +#include +#include +#include + +#include "../../MCInstPrinter.h" +#include "capstone/arm.h" + +#define GET_INSTRINFO_ENUM +#include "ARMGenInstrInfo.inc" + +// System Registers +typedef struct MClassSysReg { + const char *Name; + arm_sysop_reg sysreg; + uint16_t M1Encoding12; + uint16_t M2M3Encoding8; + uint16_t Encoding; + int FeaturesRequired[2]; +} ARMSysReg_MClassSysReg; + +// return true if FeaturesRequired are all present in ActiveFeatures +static inline bool hasRequiredFeatures(const ARMSysReg_MClassSysReg *TheReg, + int ActiveFeatures) +{ + return (TheReg->FeaturesRequired[0] == ActiveFeatures || + TheReg->FeaturesRequired[1] == ActiveFeatures); +} + +// returns true if TestFeatures are all present in FeaturesRequired +static inline bool +MClassSysReg_isInRequiredFeatures(const ARMSysReg_MClassSysReg *TheReg, + int TestFeatures) +{ + return (TheReg->FeaturesRequired[0] == TestFeatures || + TheReg->FeaturesRequired[1] == TestFeatures); +} + +#define GET_SUBTARGETINFO_ENUM +#include "ARMGenSubtargetInfo.inc" + +// lookup system register using 12-bit SYSm value. +// Note: the search is uniqued using M1 mask +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm); +// returns APSR with _ qualifier. +// Note: ARMv7-M deprecates using MSR APSR without a _ qualifier +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm); +// lookup system registers using 8-bit SYSm value +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm); +// end namespace ARMSysReg + +// Banked Registers +typedef struct BankedReg { + const char *Name; + arm_sysop_reg sysreg; + uint16_t Encoding; +} ARMBankedReg_BankedReg; + +#define GET_BANKEDREG_DECL +#define GET_MCLASSSYSREG_DECL +#include "ARMGenSystemRegister.inc" + +typedef enum IMod { ARM_PROC_IE = 2, ARM_PROC_ID = 3 } ARM_PROC_IMod; + +typedef enum IFlags { + ARM_PROC_F = 1, + ARM_PROC_I = 2, + ARM_PROC_A = 4 +} ARM_PROC_IFlags; + +inline static const char *ARM_PROC_IFlagsToString(unsigned val) +{ + switch (val) { + default: + // llvm_unreachable("Unknown iflags operand"); + case ARM_PROC_F: + return "f"; + case ARM_PROC_I: + return "i"; + case ARM_PROC_A: + return "a"; + } +} + +inline static const char *ARM_PROC_IModToString(unsigned val) +{ + switch (val) { + default: + // llvm_unreachable("Unknown imod operand"); + assert(0); + case ARM_PROC_IE: + return "ie"; + case ARM_PROC_ID: + return "id"; + } +} + +inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8) +{ + switch (val) { + default: + // llvm_unreachable("Unknown memory operation"); + assert(0); + case ARM_MB_SY: + return "sy"; + case ARM_MB_ST: + return "st"; + case ARM_MB_LD: + return HasV8 ? "ld" : "#0xd"; + case ARM_MB_RESERVED_12: + return "#0xc"; + case ARM_MB_ISH: + return "ish"; + case ARM_MB_ISHST: + return "ishst"; + case ARM_MB_ISHLD: + return HasV8 ? "ishld" : "#0x9"; + case ARM_MB_RESERVED_8: + return "#0x8"; + case ARM_MB_NSH: + return "nsh"; + case ARM_MB_NSHST: + return "nshst"; + case ARM_MB_NSHLD: + return HasV8 ? "nshld" : "#0x5"; + case ARM_MB_RESERVED_4: + return "#0x4"; + case ARM_MB_OSH: + return "osh"; + case ARM_MB_OSHST: + return "oshst"; + case ARM_MB_OSHLD: + return HasV8 ? "oshld" : "#0x1"; + case ARM_MB_RESERVED_0: + return "#0x0"; + } +} + +typedef enum TraceSyncBOpt { ARM_TSB_CSYNC = 0 } ARM_TSB_TraceSyncBOpt; + +inline static const char *ARM_TSB_TraceSyncBOptToString(unsigned val) +{ + switch (val) { + default: + // llvm_unreachable("Unknown trace synchronization barrier operation"); + assert(0); + case ARM_TSB_CSYNC: + return "csync"; + } +} + +typedef enum InstSyncBOpt { + ARM_ISB_RESERVED_0 = 0, + ARM_ISB_RESERVED_1 = 1, + ARM_ISB_RESERVED_2 = 2, + ARM_ISB_RESERVED_3 = 3, + ARM_ISB_RESERVED_4 = 4, + ARM_ISB_RESERVED_5 = 5, + ARM_ISB_RESERVED_6 = 6, + ARM_ISB_RESERVED_7 = 7, + ARM_ISB_RESERVED_8 = 8, + ARM_ISB_RESERVED_9 = 9, + ARM_ISB_RESERVED_10 = 10, + ARM_ISB_RESERVED_11 = 11, + ARM_ISB_RESERVED_12 = 12, + ARM_ISB_RESERVED_13 = 13, + ARM_ISB_RESERVED_14 = 14, + ARM_ISB_SY = 15 +} ARM_ISB_InstSyncBOpt; + +inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val) +{ + switch (val) { + default: + // llvm_unreachable("Unknown memory operation"); + assert(0); + case ARM_ISB_RESERVED_0: + return "#0x0"; + case ARM_ISB_RESERVED_1: + return "#0x1"; + case ARM_ISB_RESERVED_2: + return "#0x2"; + case ARM_ISB_RESERVED_3: + return "#0x3"; + case ARM_ISB_RESERVED_4: + return "#0x4"; + case ARM_ISB_RESERVED_5: + return "#0x5"; + case ARM_ISB_RESERVED_6: + return "#0x6"; + case ARM_ISB_RESERVED_7: + return "#0x7"; + case ARM_ISB_RESERVED_8: + return "#0x8"; + case ARM_ISB_RESERVED_9: + return "#0x9"; + case ARM_ISB_RESERVED_10: + return "#0xa"; + case ARM_ISB_RESERVED_11: + return "#0xb"; + case ARM_ISB_RESERVED_12: + return "#0xc"; + case ARM_ISB_RESERVED_13: + return "#0xd"; + case ARM_ISB_RESERVED_14: + return "#0xe"; + case ARM_ISB_SY: + return "sy"; + } +} + +#define GET_REGINFO_ENUM +#include "ARMGenRegisterInfo.inc" + +/// isARMLowRegister - Returns true if the register is a low register (r0-r7). +/// +static inline bool isARMLowRegister(unsigned Reg) +{ + switch (Reg) { + case ARM_R0: + case ARM_R1: + case ARM_R2: + case ARM_R3: + case ARM_R4: + case ARM_R5: + case ARM_R6: + case ARM_R7: + return true; + default: + return false; + } +} + +/// ARMII - This namespace holds all of the target specific flags that +/// instruction info tracks. +/// +/// ARM Index Modes +typedef enum IndexMode { + ARMII_IndexModeNone = 0, + ARMII_IndexModePre = 1, + ARMII_IndexModePost = 2, + ARMII_IndexModeUpd = 3 +} ARMII_IndexMode; + +/// ARM Addressing Modes +typedef enum AddrMode { + ARMII_AddrModeNone = 0, + ARMII_AddrMode1 = 1, + ARMII_AddrMode2 = 2, + ARMII_AddrMode3 = 3, + ARMII_AddrMode4 = 4, + ARMII_AddrMode5 = 5, + ARMII_AddrMode6 = 6, + ARMII_AddrModeT1_1 = 7, + ARMII_AddrModeT1_2 = 8, + ARMII_AddrModeT1_4 = 9, + ARMII_AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data + ARMII_AddrModeT2_i12 = 11, + ARMII_AddrModeT2_i8 = 12, // +/- i8 + ARMII_AddrModeT2_i8pos = 13, // + i8 + ARMII_AddrModeT2_i8neg = 14, // - i8 + ARMII_AddrModeT2_so = 15, + ARMII_AddrModeT2_pc = 16, // +/- i12 for pc relative data + ARMII_AddrModeT2_i8s4 = 17, // i8 * 4 + ARMII_AddrMode_i12 = 18, + ARMII_AddrMode5FP16 = 19, // i8 * 2 + ARMII_AddrModeT2_ldrex = 20, // i8 * 4, with unscaled offset in MCInst + ARMII_AddrModeT2_i7s4 = 21, // i7 * 4 + ARMII_AddrModeT2_i7s2 = 22, // i7 * 2 + ARMII_AddrModeT2_i7 = 23, // i7 * 1 +} ARMII_AddrMode; + +inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode) +{ + switch (addrmode) { + case ARMII_AddrModeNone: + return "AddrModeNone"; + case ARMII_AddrMode1: + return "AddrMode1"; + case ARMII_AddrMode2: + return "AddrMode2"; + case ARMII_AddrMode3: + return "AddrMode3"; + case ARMII_AddrMode4: + return "AddrMode4"; + case ARMII_AddrMode5: + return "AddrMode5"; + case ARMII_AddrMode5FP16: + return "AddrMode5FP16"; + case ARMII_AddrMode6: + return "AddrMode6"; + case ARMII_AddrModeT1_1: + return "AddrModeT1_1"; + case ARMII_AddrModeT1_2: + return "AddrModeT1_2"; + case ARMII_AddrModeT1_4: + return "AddrModeT1_4"; + case ARMII_AddrModeT1_s: + return "AddrModeT1_s"; + case ARMII_AddrModeT2_i12: + return "AddrModeT2_i12"; + case ARMII_AddrModeT2_i8: + return "AddrModeT2_i8"; + case ARMII_AddrModeT2_i8pos: + return "AddrModeT2_i8pos"; + case ARMII_AddrModeT2_i8neg: + return "AddrModeT2_i8neg"; + case ARMII_AddrModeT2_so: + return "AddrModeT2_so"; + case ARMII_AddrModeT2_pc: + return "AddrModeT2_pc"; + case ARMII_AddrModeT2_i8s4: + return "AddrModeT2_i8s4"; + case ARMII_AddrMode_i12: + return "AddrMode_i12"; + case ARMII_AddrModeT2_ldrex: + return "AddrModeT2_ldrex"; + case ARMII_AddrModeT2_i7s4: + return "AddrModeT2_i7s4"; + case ARMII_AddrModeT2_i7s2: + return "AddrModeT2_i7s2"; + case ARMII_AddrModeT2_i7: + return "AddrModeT2_i7"; + } +} + +/// Target Operand Flag enum. +typedef enum TOF { + //===------------------------------------------------------------------===// + // ARM Specific MachineOperand flags. + + ARMII_MO_NO_FLAG = 0, + + /// MO_LO16 - On a symbol operand, this represents a relocation containing + /// lower 16 bit of the address. Used only via movw instruction. + ARMII_MO_LO16 = 0x1, + + /// MO_HI16 - On a symbol operand, this represents a relocation containing + /// higher 16 bit of the address. Used only via movt instruction. + ARMII_MO_HI16 = 0x2, + + /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects + /// just that part of the flag set. + ARMII_MO_OPTION_MASK = 0x3, + + /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the + /// reference is actually to the ".refptr.FOO" symbol. This is used for + /// stub symbols on windows. + ARMII_MO_COFFSTUB = 0x4, + + /// MO_GOT - On a symbol operand, this represents a GOT relative relocation. + ARMII_MO_GOT = 0x8, + + /// MO_SBREL - On a symbol operand, this represents a static base relative + /// relocation. Used in movw and movt instructions. + ARMII_MO_SBREL = 0x10, + + /// MO_DLLIMPORT - On a symbol operand, this represents that the reference + /// to the symbol is for an import stub. This is used for DLL import + /// storage class indication on Windows. + ARMII_MO_DLLIMPORT = 0x20, + + /// MO_SECREL - On a symbol operand this indicates that the immediate is + /// the offset from beginning of section. + /// + /// This is the TLS offset for the COFF/Windows TLS mechanism. + ARMII_MO_SECREL = 0x40, + + /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it + /// represents a symbol which, if indirect, will get special Darwin mangling + /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be + /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for + /// example). + ARMII_MO_NONLAZY = 0x80, + + // It's undefined behaviour if an enum overflows the range between its + // smallest and largest values, but since these are |ed together, it can + // happen. Put a sentinel in (values of this enum are stored as "unsigned + // char"). + ARMII_MO_UNUSED_MAXIMUM = 0xff +} ARMII_TOF; + +enum { + //===------------------------------------------------------------------===// + // Instruction Flags. + + //===------------------------------------------------------------------===// + // This four-bit field describes the addressing mode used. + ARMII_AddrModeMask = + 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h + + // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load + // and store ops only. Generic "updating" flag is used for ld/st multiple. + // The index mode enums are declared in ARMBaseInfo.h + ARMII_IndexModeShift = 5, + ARMII_IndexModeMask = 3 << ARMII_IndexModeShift, + + //===------------------------------------------------------------------===// + // Instruction encoding formats. + // + ARMII_FormShift = 7, + ARMII_FormMask = 0x3f << ARMII_FormShift, + + // Pseudo instructions + ARMII_Pseudo = 0 << ARMII_FormShift, + + // Multiply instructions + ARMII_MulFrm = 1 << ARMII_FormShift, + + // Branch instructions + ARMII_BrFrm = 2 << ARMII_FormShift, + ARMII_BrMiscFrm = 3 << ARMII_FormShift, + + // Data Processing instructions + ARMII_DPFrm = 4 << ARMII_FormShift, + ARMII_DPSoRegFrm = 5 << ARMII_FormShift, + + // Load and Store + ARMII_LdFrm = 6 << ARMII_FormShift, + ARMII_StFrm = 7 << ARMII_FormShift, + ARMII_LdMiscFrm = 8 << ARMII_FormShift, + ARMII_StMiscFrm = 9 << ARMII_FormShift, + ARMII_LdStMulFrm = 10 << ARMII_FormShift, + + ARMII_LdStExFrm = 11 << ARMII_FormShift, + + // Miscellaneous arithmetic instructions + ARMII_ArithMiscFrm = 12 << ARMII_FormShift, + ARMII_SatFrm = 13 << ARMII_FormShift, + + // Extend instructions + ARMII_ExtFrm = 14 << ARMII_FormShift, + + // VFP formats + ARMII_VFPUnaryFrm = 15 << ARMII_FormShift, + ARMII_VFPBinaryFrm = 16 << ARMII_FormShift, + ARMII_VFPConv1Frm = 17 << ARMII_FormShift, + ARMII_VFPConv2Frm = 18 << ARMII_FormShift, + ARMII_VFPConv3Frm = 19 << ARMII_FormShift, + ARMII_VFPConv4Frm = 20 << ARMII_FormShift, + ARMII_VFPConv5Frm = 21 << ARMII_FormShift, + ARMII_VFPLdStFrm = 22 << ARMII_FormShift, + ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift, + ARMII_VFPMiscFrm = 24 << ARMII_FormShift, + + // Thumb format + ARMII_ThumbFrm = 25 << ARMII_FormShift, + + // Miscelleaneous format + ARMII_MiscFrm = 26 << ARMII_FormShift, + + // NEON formats + ARMII_NGetLnFrm = 27 << ARMII_FormShift, + ARMII_NSetLnFrm = 28 << ARMII_FormShift, + ARMII_NDupFrm = 29 << ARMII_FormShift, + ARMII_NLdStFrm = 30 << ARMII_FormShift, + ARMII_N1RegModImmFrm = 31 << ARMII_FormShift, + ARMII_N2RegFrm = 32 << ARMII_FormShift, + ARMII_NVCVTFrm = 33 << ARMII_FormShift, + ARMII_NVDupLnFrm = 34 << ARMII_FormShift, + ARMII_N2RegVShLFrm = 35 << ARMII_FormShift, + ARMII_N2RegVShRFrm = 36 << ARMII_FormShift, + ARMII_N3RegFrm = 37 << ARMII_FormShift, + ARMII_N3RegVShFrm = 38 << ARMII_FormShift, + ARMII_NVExtFrm = 39 << ARMII_FormShift, + ARMII_NVMulSLFrm = 40 << ARMII_FormShift, + ARMII_NVTBLFrm = 41 << ARMII_FormShift, + ARMII_N3RegCplxFrm = 43 << ARMII_FormShift, + + //===------------------------------------------------------------------===// + // Misc flags. + + // UnaryDP - Indicates this is a unary data processing instruction, i.e. + // it doesn't have a Rn operand. + ARMII_UnaryDP = 1 << 13, + + // Xform16Bit - Indicates this Thumb2 instruction may be transformed into + // a 16-bit Thumb instruction if certain conditions are met. + ARMII_Xform16Bit = 1 << 14, + + // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb + // instruction. Used by the parser to determine whether to require the 'S' + // suffix on the mnemonic (when not in an IT block) or preclude it (when + // in an IT block). + ARMII_ThumbArithFlagSetting = 1 << 19, + + // Whether an instruction can be included in an MVE tail-predicated loop, + // though extra validity checks may need to be performed too. + ARMII_ValidForTailPredication = 1 << 20, + + // Whether an instruction writes to the top/bottom half of a vector element + // and leaves the other half untouched. + ARMII_RetainsPreviousHalfElement = 1 << 21, + + // Whether the instruction produces a scalar result from vector operands. + ARMII_HorizontalReduction = 1 << 22, + + // Whether this instruction produces a vector result that is larger than + // its input, typically reading from the top/bottom halves of the input(s). + ARMII_DoubleWidthResult = 1 << 23, + + // The vector element size for MVE instructions. 00 = i8, 01 = i16, 10 = i32 + // and 11 = i64. This is the largest type if multiple are present, so a + // MVE_VMOVLs8bh is ize 01=i16, as it extends from a i8 to a i16. There are + // some caveats so cannot be used blindly, such as exchanging VMLADAVA's and + // complex instructions, which may use different input lanes. + ARMII_VecSizeShift = 24, + ARMII_VecSize = 3 << ARMII_VecSizeShift, + + //===------------------------------------------------------------------===// + // Code domain. + ARMII_DomainShift = 15, + ARMII_DomainMask = 15 << ARMII_DomainShift, + ARMII_DomainGeneral = 0 << ARMII_DomainShift, + ARMII_DomainVFP = 1 << ARMII_DomainShift, + ARMII_DomainNEON = 2 << ARMII_DomainShift, + ARMII_DomainNEONA8 = 4 << ARMII_DomainShift, + ARMII_DomainMVE = 8 << ARMII_DomainShift, + + //===------------------------------------------------------------------===// + // Field shifts - such shifts are used to set field while generating + // machine instructions. + // + // FIXME: This list will need adjusting/fixing as the MC code emitter + // takes shape and the ARMCodeEmitter.cpp bits go away. + ARMII_ShiftTypeShift = 4, + + ARMII_M_BitShift = 5, + ARMII_ShiftImmShift = 5, + ARMII_ShiftShift = 7, + ARMII_N_BitShift = 7, + ARMII_ImmHiShift = 8, + ARMII_SoRotImmShift = 8, + ARMII_RegRsShift = 8, + ARMII_ExtRotImmShift = 10, + ARMII_RegRdLoShift = 12, + ARMII_RegRdShift = 12, + ARMII_RegRdHiShift = 16, + ARMII_RegRnShift = 16, + ARMII_S_BitShift = 20, + ARMII_W_BitShift = 21, + ARMII_AM3_I_BitShift = 22, + ARMII_D_BitShift = 22, + ARMII_U_BitShift = 23, + ARMII_P_BitShift = 24, + ARMII_I_BitShift = 25, + ARMII_CondShift = 28 +}; + +const char *get_pred_mask(ARM_PredBlockMask pred_mask); + +#endif // CS_ARM_BASEINFO_H diff --git a/thirdparty/capstone/arch/ARM/ARMDisassembler.c b/thirdparty/capstone/arch/ARM/ARMDisassembler.c new file mode 100644 index 0000000..1618af9 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMDisassembler.c @@ -0,0 +1,7346 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + +//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include +#include +#include + +#include "../../LEB128.h" +#include "../../MCDisassembler.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../MCInst.h" +#include "../../MCInstrDesc.h" +#include "../../MCRegisterInfo.h" +#include "../../MathExtras.h" +#include "../../cs_priv.h" +#include "../../utils.h" +#include "ARMLinkage.h" +#include "ARMAddressingModes.h" +#include "ARMBaseInfo.h" +#include "ARMDisassemblerExtension.h" +#include "ARMMapping.h" + +#define GET_INSTRINFO_MC_DESC +#include "ARMGenInstrInfo.inc" + +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b + +#define DEBUG_TYPE "arm-disassembler" + +// Handles the condition code status of instructions in IT blocks +; + +; + +/// ARM disassembler for all ARM platforms.; +static DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t ByteLen, + MCInst *MI, uint16_t *Size, uint64_t Address, + void *Info); +DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes, size_t ByteLen, + MCInst *MI, uint16_t *Size, uint64_t Address, + void *Info); +DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t ByteLen, + MCInst *MI, uint16_t *Size, uint64_t Address, + void *Info); +DecodeStatus AddThumbPredicate(MCInst *); +void UpdateThumbVFPPredicate(DecodeStatus, MCInst *); +; + +// end anonymous namespace + +// Forward declare these because the autogenerated code will reference them. +// Definitions are further down. +static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodetGPROddRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodetGPREvenRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus +DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeGPRnospRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeGPRspRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeSPR_8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeMQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeMQQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeTSBInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst, + unsigned Insn, + uint64_t Adddress, + const void *Decoder); +static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2HintSpaceInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVMOVModImmInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeMVEModImmInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeMVEVADCInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMveAddrModeRQ(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +#define DECLARE_DecodeMveAddrModeQ(shift) \ + static DecodeStatus CONCAT(DecodeMveAddrModeQ, shift)( \ + MCInst * Inst, unsigned Insn, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeMveAddrModeQ(2) DECLARE_DecodeMveAddrModeQ(3) + + static DecodeStatus + DecodeCoprocessor(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVCVTImmOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, + unsigned Val, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2Imm7S4(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2AddrModeImm7s4(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder); +#define DECLARE_DecodeT2Imm7(shift) \ + static DecodeStatus CONCAT(DecodeT2Imm7, shift)(MCInst * Inst, \ + unsigned Val, \ + uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeT2Imm7(0) DECLARE_DecodeT2Imm7(1) DECLARE_DecodeT2Imm7(2) + + static DecodeStatus + DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder); +#define DECLARE_DecodeTAddrModeImm7(shift) \ + static DecodeStatus CONCAT(DecodeTAddrModeImm7, shift)( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeTAddrModeImm7(0) DECLARE_DecodeTAddrModeImm7(1) + +#define DECLARE_DecodeT2AddrModeImm7(shift, WriteBack) \ + static DecodeStatus CONCAT(DecodeT2AddrModeImm7, \ + CONCAT(shift, WriteBack))( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder); + DECLARE_DecodeT2AddrModeImm7(0, 0) DECLARE_DecodeT2AddrModeImm7(1, 0) + DECLARE_DecodeT2AddrModeImm7(2, 0) + DECLARE_DecodeT2AddrModeImm7(0, 1) + DECLARE_DecodeT2AddrModeImm7(1, 1) + DECLARE_DecodeT2AddrModeImm7(2, 1) + + static DecodeStatus + DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2Adr(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder); +static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); + +#define DECLARE_DecodeBFLabelOperand(isSigned, isNeg, zeroPermitted, size) \ + static DecodeStatus CONCAT( \ + DecodeBFLabelOperand, \ + CONCAT(isSigned, CONCAT(isNeg, CONCAT(zeroPermitted, size))))( \ + MCInst * Inst, unsigned val, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeBFLabelOperand(false, false, false, + 4) DECLARE_DecodeBFLabelOperand(true, false, true, + 18) + DECLARE_DecodeBFLabelOperand(true, false, true, 12) + DECLARE_DecodeBFLabelOperand(true, false, true, 16) + DECLARE_DecodeBFLabelOperand(false, true, true, 11) + DECLARE_DecodeBFLabelOperand(false, false, true, + 11) + + static DecodeStatus + DecodeBFAfterTargetOperand(MCInst *Inst, unsigned val, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodePredNoALOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeLOLoop(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeLongShiftOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVSCCLRM(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVPTMaskOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVpredROperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + const void *Decoder); +#define DECLARE_DecodeVSTRVLDR_SYSREG(Writeback) \ + static DecodeStatus CONCAT(DecodeVSTRVLDR_SYSREG, Writeback)( \ + MCInst * Inst, unsigned Insn, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeVSTRVLDR_SYSREG(false) DECLARE_DecodeVSTRVLDR_SYSREG(true) + +#define DECLARE_DecodeMVE_MEM_1_pre(shift) \ + static DecodeStatus CONCAT(DecodeMVE_MEM_1_pre, shift)( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder); + DECLARE_DecodeMVE_MEM_1_pre(0) DECLARE_DecodeMVE_MEM_1_pre(1) + +#define DECLARE_DecodeMVE_MEM_2_pre(shift) \ + static DecodeStatus CONCAT(DecodeMVE_MEM_2_pre, shift)( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder); + DECLARE_DecodeMVE_MEM_2_pre(0) DECLARE_DecodeMVE_MEM_2_pre( + 1) DECLARE_DecodeMVE_MEM_2_pre(2) + +#define DECLARE_DecodeMVE_MEM_3_pre(shift) \ + static DecodeStatus CONCAT(DecodeMVE_MEM_3_pre, shift)( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder); + DECLARE_DecodeMVE_MEM_3_pre( + 2) DECLARE_DecodeMVE_MEM_3_pre(3) + +#define DECLARE_DecodePowerTwoOperand(MinLog, MaxLog) \ + static DecodeStatus CONCAT(DecodePowerTwoOperand, \ + CONCAT(MinLog, MaxLog))( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder); + DECLARE_DecodePowerTwoOperand(0, 3) + +#define DECLARE_DecodeMVEPairVectorIndexOperand(start) \ + static DecodeStatus CONCAT(DecodeMVEPairVectorIndexOperand, start)( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder); + DECLARE_DecodeMVEPairVectorIndexOperand( + 2) + DECLARE_DecodeMVEPairVectorIndexOperand( + 0) + + static DecodeStatus + DecodeMVEVMOVQtoDReg(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMVEVCVTt1fp(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +typedef DecodeStatus OperandDecoder(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +#define DECLARE_DecodeMVEVCMP(scalar, predicate_decoder) \ + static DecodeStatus CONCAT(DecodeMVEVCMP, \ + CONCAT(scalar, predicate_decoder))( \ + MCInst * Inst, unsigned Insn, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeMVEVCMP(false, DecodeRestrictedIPredicateOperand) DECLARE_DecodeMVEVCMP( + false, DecodeRestrictedUPredicateOperand) + DECLARE_DecodeMVEVCMP(false, DecodeRestrictedSPredicateOperand) + DECLARE_DecodeMVEVCMP(true, DecodeRestrictedIPredicateOperand) + DECLARE_DecodeMVEVCMP(true, + DecodeRestrictedUPredicateOperand) + DECLARE_DecodeMVEVCMP( + true, DecodeRestrictedSPredicateOperand) + DECLARE_DecodeMVEVCMP( + false, + DecodeRestrictedFPPredicateOperand) + DECLARE_DecodeMVEVCMP( + true, + DecodeRestrictedFPPredicateOperand) + + static DecodeStatus + DecodeMveVCTP(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeMVEVPNOT(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMVEOverlappingLongShift(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeT2AddSubSPImm(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +#include "ARMGenDisassemblerTables.inc" + +// Post-decoding checks +static DecodeStatus checkDecodedInstruction(MCInst *MI, uint32_t Insn, + DecodeStatus Result) +{ + switch (MCInst_getOpcode(MI)) { + case ARM_HVC: { + // HVC is undefined if condition = 0xf otherwise upredictable + // if condition != 0xe + uint32_t Cond = (Insn >> 28) & 0xF; + if (Cond == 0xF) + return MCDisassembler_Fail; + if (Cond != 0xE) + return MCDisassembler_SoftFail; + return Result; + } + case ARM_t2ADDri: + case ARM_t2ADDri12: + case ARM_t2ADDrr: + case ARM_t2ADDrs: + case ARM_t2SUBri: + case ARM_t2SUBri12: + case ARM_t2SUBrr: + case ARM_t2SUBrs: + if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP && + MCOperand_getReg(MCInst_getOperand(MI, (1))) != ARM_SP) + return MCDisassembler_SoftFail; + return Result; + default: + return Result; + } +} + +static DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, + size_t BytesLen, MCInst *MI, uint16_t *Size, + uint64_t Address, void *Info) +{ + DecodeStatus Result = MCDisassembler_Fail; + if (MI->csh->mode & CS_MODE_THUMB) + Result = getThumbInstruction(ud, Bytes, BytesLen, MI, Size, + Address, Info); + else + Result = getARMInstruction(ud, Bytes, BytesLen, MI, Size, + Address, Info); + MCInst_handleWriteback(MI, ARMInsts, ARR_SIZE(ARMInsts)); + return Result; +} + +static inline uint32_t endianSensitiveOpcode32(MCInst *MI, const uint8_t *Bytes) +{ + uint32_t Insn; + if (MODE_IS_BIG_ENDIAN(MI->csh->mode)) + Insn = (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | + ((uint32_t)Bytes[0] << 24); + else + Insn = ((uint32_t)Bytes[3] << 24) | (Bytes[2] << 16) | + (Bytes[1] << 8) | (Bytes[0] << 0); + return Insn; +} + +static inline uint16_t endianSensitiveOpcode16(MCInst *MI, const uint8_t *Bytes) +{ + uint16_t Insn; + if (MODE_IS_BIG_ENDIAN(MI->csh->mode)) + Insn = (Bytes[0] << 8) | Bytes[1]; + else + Insn = (Bytes[1] << 8) | Bytes[0]; + + return Insn; +} + +DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen, + MCInst *MI, uint16_t *Size, uint64_t Address, + void *Info) +{ + // We want to read exactly 4 bytes of data. + if (BytesLen < 4) { + *Size = 0; + return MCDisassembler_Fail; + } + + // Encoded as a 32-bit word in the stream. + uint32_t Insn = endianSensitiveOpcode32(MI, Bytes); + + // Calling the auto-generated decoder function. + DecodeStatus Result = + decodeInstruction_4(DecoderTableARM32, MI, Insn, Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return checkDecodedInstruction(MI, Insn, Result); + } + + typedef struct DecodeTable { + const uint8_t *P; + bool DecodePred; + } DecodeTable; + + const DecodeTable Tables[] = { + { DecoderTableVFP32, false }, + { DecoderTableVFPV832, false }, + { DecoderTableNEONData32, true }, + { DecoderTableNEONLoadStore32, true }, + { DecoderTableNEONDup32, true }, + { DecoderTablev8NEON32, false }, + { DecoderTablev8Crypto32, false }, + }; + + for (int i = 0; i < (sizeof(Tables) / sizeof(Tables[0])); ++i) { + MCInst_clear(MI); + DecodeTable Table = Tables[i]; + Result = decodeInstruction_4(Table.P, MI, Insn, Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + // Add a fake predicate operand, because we share these instruction + // definitions with Thumb2 where these instructions are predicable. + if (Table.DecodePred && + !DecodePredicateOperand(MI, 0xE, Address, Table.P)) + return MCDisassembler_Fail; + return Result; + } + } + + Result = decodeInstruction_4(DecoderTableCoProc32, MI, Insn, Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return checkDecodedInstruction(MI, Insn, Result); + } + + *Size = 4; + return MCDisassembler_Fail; +} + +extern const MCInstrDesc ARMInsts[]; + +/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the +/// immediate Value in the MCInst. The immediate Value has had any PC +/// adjustment made by the caller. If the instruction is a branch instruction +/// then isBranch is true, else false. If the getOpInfo() function was set as +/// part of the setupForSymbolicDisassembly() call then that function is called +/// to get any symbolic information at the Address for this instruction. If +/// that returns non-zero then the symbolic information it returns is used to +/// create an MCExpr and that is added as an operand to the MCInst. If +/// getOpInfo() returns zero and isBranch is true then a symbol look up for +/// Value is done and if a symbol is found an MCExpr is created with that, else +/// an MCExpr with Value is created. This function returns true if it adds an +/// operand to the MCInst and false otherwise. +static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, + bool isBranch, uint64_t InstSize, + MCInst *MI, const void *Decoder) +{ + // FIXME: Does it make sense for value to be negative? + // return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, + // isBranch, /*Offset=*/0, /*OpSize=*/0, + // InstSize); + return false; +} + +/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being +/// referenced by a load instruction with the base register that is the Pc. +/// These can often be values in a literal pool near the Address of the +/// instruction. The Address of the instruction and its immediate Value are +/// used as a possible literal pool entry. The SymbolLookUp call back will +/// return the name of a symbol referenced by the literal pool's entry if +/// the referenced address is that of a symbol. Or it will return a pointer to +/// a literal 'C' string if the referenced address of the literal pool's entry +/// is an address into a section with 'C' string literals. +static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, + const void *Decoder) +{ + // Decoder->tryAddingPcLoadReferenceComment(Value, Address); +} + +// Thumb1 instructions don't have explicit S bits. Rather, they +// implicitly set CPSR. Since it's not represented in the encoding, the +// auto-generated decoder won't inject the CPSR operand. We need to fix +// that as a post-pass. +static void AddThumb1SBit(MCInst *MI, bool InITBlock) +{ + const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; + unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; + unsigned i; + + for (i = 0; i < NumOps; ++i) { + if (i == MCInst_getNumOperands(MI)) + break; + if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && + OpInfo[i].RegClass == ARM_CCRRegClassID) { + if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i - 1])) + continue; + MCInst_insert0(MI, i, + MCOperand_CreateReg1( + MI, (InITBlock ? 0 : ARM_CPSR))); + return; + } + } + + MCInst_insert0(MI, i, + MCOperand_CreateReg1(MI, (InITBlock ? 0 : ARM_CPSR))); +} + +static bool isVectorPredicable(unsigned Opcode) +{ + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + unsigned short NumOps = ARMInsts[Opcode].NumOperands; + for (unsigned i = 0; i < NumOps; ++i) { + if (ARM_isVpred(OpInfo[i].OperandType)) + return true; + } + return false; +} + +// Most Thumb instructions don't have explicit predicates in the +// encoding, but rather get their predicates from IT context. We need +// to fix up the predicate operands using this context information as a +// post-pass. +DecodeStatus AddThumbPredicate(MCInst *MI) +{ + DecodeStatus S = MCDisassembler_Success; + + // A few instructions actually have predicates encoded in them. Don't + // try to overwrite it if we're seeing one of those. + switch (MCInst_getOpcode(MI)) { + case ARM_tBcc: + case ARM_t2Bcc: + case ARM_tCBZ: + case ARM_tCBNZ: + case ARM_tCPS: + case ARM_t2CPS3p: + case ARM_t2CPS2p: + case ARM_t2CPS1p: + case ARM_t2CSEL: + case ARM_t2CSINC: + case ARM_t2CSINV: + case ARM_t2CSNEG: + case ARM_tMOVSr: + case ARM_tSETEND: + // Some instructions (mostly conditional branches) are not + // allowed in IT blocks. + if (ITBlock_instrInITBlock(&(MI->csh->ITBlock))) + S = MCDisassembler_SoftFail; + else + return MCDisassembler_Success; + break; + case ARM_t2HINT: + if (MCOperand_getImm(MCInst_getOperand(MI, (0))) == 0x10 && + (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureRAS)) != 0) + S = MCDisassembler_SoftFail; + break; + case ARM_tB: + case ARM_t2B: + case ARM_t2TBB: + case ARM_t2TBH: + // Some instructions (mostly unconditional branches) can + // only appears at the end of, or outside of, an IT. + if (ITBlock_instrInITBlock(&(MI->csh->ITBlock)) && + !ITBlock_instrLastInITBlock(&(MI->csh->ITBlock))) + S = MCDisassembler_SoftFail; + break; + default: + break; + } + + // Warn on non-VPT predicable instruction in a VPT block and a VPT + // predicable instruction in an IT block + if ((!isVectorPredicable(MCInst_getOpcode(MI)) && + VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock))) || + (isVectorPredicable(MCInst_getOpcode(MI)) && + ITBlock_instrInITBlock(&(MI->csh->ITBlock)))) + S = MCDisassembler_SoftFail; + + // If we're in an IT/VPT block, base the predicate on that. Otherwise, + // assume a predicate of AL. + unsigned CC = ARMCC_AL; + unsigned VCC = ARMVCC_None; + if (ITBlock_instrInITBlock(&(MI->csh->ITBlock))) { + CC = ITBlock_getITCC(&(MI->csh->ITBlock)); + ITBlock_advanceITState(&(MI->csh->ITBlock)); + } else if (VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock))) { + VCC = VPTBlock_getVPTPred(&(MI->csh->VPTBlock)); + VPTBlock_advanceVPTState(&(MI->csh->VPTBlock)); + } + + const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; + unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; + + unsigned i; + for (i = 0; i < NumOps; ++i) { + if (MCOperandInfo_isPredicate(&OpInfo[i]) || + i == MCInst_getNumOperands(MI)) + break; + } + + if (MCInst_isPredicable(&ARMInsts[MCInst_getOpcode(MI)])) { + MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, (CC))); + + if (CC == ARMCC_AL) + MCInst_insert0(MI, i + 1, + MCOperand_CreateReg1(MI, (0))); + else + MCInst_insert0(MI, i + 1, + MCOperand_CreateReg1(MI, (ARM_CPSR))); + } else if (CC != ARMCC_AL) { + Check(&S, MCDisassembler_SoftFail); + } + + unsigned VCCPos; + for (VCCPos = 0; VCCPos < NumOps; ++VCCPos) { + if (ARM_isVpred(OpInfo[VCCPos].OperandType) || + VCCPos == MCInst_getNumOperands(MI)) + break; + } + + if (isVectorPredicable(MCInst_getOpcode(MI))) { + MCInst_insert0(MI, VCCPos, MCOperand_CreateImm1(MI, (VCC))); + + if (VCC == ARMVCC_None) + MCInst_insert0(MI, VCCPos + 1, + MCOperand_CreateReg1(MI, (0))); + else + MCInst_insert0(MI, VCCPos + 1, + MCOperand_CreateReg1(MI, (ARM_P0))); + MCInst_insert0(MI, VCCPos + 2, MCOperand_CreateReg1(MI, (0))); + if (OpInfo[VCCPos].OperandType == ARM_OP_VPRED_R) { + int TiedOp = MCOperandInfo_getOperandConstraint( + &ARMInsts[MCInst_getOpcode(MI)], VCCPos + 3, + MCOI_TIED_TO); + assert(TiedOp >= 0 && + "Inactive register in vpred_r is not tied to an output!"); + // Copy the operand to ensure it's not invalidated when MI grows. + MCOperand Op = *MCInst_getOperand(MI, TiedOp); + MCInst_insert0(MI, VCCPos + 3, &Op); + } + } else if (VCC != ARMVCC_None) { + Check(&S, MCDisassembler_SoftFail); + } + + return S; +} + +// Thumb VFP instructions are a special case. Because we share their +// encodings between ARM and Thumb modes, and they are predicable in ARM +// mode, the auto-generated decoder will give them an (incorrect) +// predicate operand. We need to rewrite these operands based on the IT +// context as a post-pass. +void UpdateThumbVFPPredicate(DecodeStatus S, MCInst *MI) +{ + unsigned CC; + CC = ITBlock_getITCC(&(MI->csh->ITBlock)); + if (CC == 0xF) + CC = ARMCC_AL; + if (ITBlock_instrInITBlock(&(MI->csh->ITBlock))) + ITBlock_advanceITState(&(MI->csh->ITBlock)); + else if (VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock))) { + CC = VPTBlock_getVPTPred(&(MI->csh->VPTBlock)); + VPTBlock_advanceVPTState(&(MI->csh->VPTBlock)); + } + + const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; + unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; + for (unsigned i = 0; i < NumOps; ++i) { + if (MCOperandInfo_isPredicate(&OpInfo[i])) { + if (CC != ARMCC_AL && + !MCInst_isPredicable( + &ARMInsts[MCInst_getOpcode(MI)])) + Check(&S, MCDisassembler_SoftFail); + MCOperand_setImm(MCInst_getOperand(MI, i), CC); + + if (CC == ARMCC_AL) + MCOperand_setReg(MCInst_getOperand(MI, i + 1), + 0); + else + MCOperand_setReg(MCInst_getOperand(MI, i + 1), + ARM_CPSR); + + return; + } + } +} + +DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen, + MCInst *MI, uint16_t *Size, uint64_t Address, + void *Info) +{ + // We want to read exactly 2 bytes of data. + if (BytesLen < 2) { + *Size = 0; + return MCDisassembler_Fail; + } + + uint16_t Insn16 = endianSensitiveOpcode16(MI, Bytes); + DecodeStatus Result = + decodeInstruction_2(DecoderTableThumb16, MI, Insn16, Address); + if (Result != MCDisassembler_Fail) { + *Size = 2; + Check(&Result, AddThumbPredicate(MI)); + return Result; + } + + Result = decodeInstruction_2(DecoderTableThumbSBit16, MI, Insn16, + Address); + if (Result) { + *Size = 2; + bool InITBlock = ITBlock_instrInITBlock(&(MI->csh->ITBlock)); + Check(&Result, AddThumbPredicate(MI)); + AddThumb1SBit(MI, InITBlock); + return Result; + } + + Result = decodeInstruction_2(DecoderTableThumb216, MI, Insn16, Address); + if (Result != MCDisassembler_Fail) { + *Size = 2; + + // Nested IT blocks are UNPREDICTABLE. Must be checked before we add + // the Thumb predicate. + if (MCInst_getOpcode(MI) == ARM_t2IT && + ITBlock_instrInITBlock(&(MI->csh->ITBlock))) + Result = MCDisassembler_SoftFail; + + Check(&Result, AddThumbPredicate(MI)); + + // If we find an IT instruction, we need to parse its condition + // code and mask operands so that we can apply them correctly + // to the subsequent instructions. + if (MCInst_getOpcode(MI) == ARM_t2IT) { + unsigned Firstcond = + MCOperand_getImm(MCInst_getOperand(MI, (0))); + unsigned Mask = + MCOperand_getImm(MCInst_getOperand(MI, (1))); + ITBlock_setITState(&(MI->csh->ITBlock), (char)Firstcond, + (char)Mask); + + // An IT instruction that would give a 'NV' predicate is + // unpredictable. if (Firstcond == ARMCC_AL && !isPowerOf2_32(Mask)) + // SStream_concat0(CS, "unpredictable IT predicate sequence"); + } + + return Result; + } + + // We want to read exactly 4 bytes of data. + if (BytesLen < 4) { + *Size = 0; + return MCDisassembler_Fail; + } + uint32_t Insn32 = (uint32_t)Insn16 << 16 | + endianSensitiveOpcode16(MI, Bytes + 2); + + Result = decodeInstruction_4(DecoderTableMVE32, MI, Insn32, Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + + // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add + // the VPT predicate. + if (isVPTOpcode(MCInst_getOpcode(MI)) && + VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock))) + Result = MCDisassembler_SoftFail; + + Check(&Result, AddThumbPredicate(MI)); + + if (isVPTOpcode(MCInst_getOpcode(MI))) { + unsigned Mask = + MCOperand_getImm(MCInst_getOperand(MI, (0))); + VPTBlock_setVPTState(&(MI->csh->VPTBlock), Mask); + } + + return Result; + } + + Result = decodeInstruction_4(DecoderTableThumb32, MI, Insn32, Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + bool InITBlock = ITBlock_instrInITBlock(&(MI->csh->ITBlock)); + Check(&Result, AddThumbPredicate(MI)); + AddThumb1SBit(MI, InITBlock); + return Result; + } + + Result = decodeInstruction_4(DecoderTableThumb232, MI, Insn32, Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + Check(&Result, AddThumbPredicate(MI)); + return checkDecodedInstruction(MI, Insn32, Result); + } + + if (fieldFromInstruction_4(Insn32, 28, 4) == 0xE) { + Result = decodeInstruction_4(DecoderTableVFP32, MI, Insn32, + Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + UpdateThumbVFPPredicate(Result, MI); + return Result; + } + } + + Result = decodeInstruction_4(DecoderTableVFPV832, MI, Insn32, Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + + if (fieldFromInstruction_4(Insn32, 28, 4) == 0xE) { + Result = decodeInstruction_4(DecoderTableNEONDup32, MI, Insn32, + Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + Check(&Result, AddThumbPredicate(MI)); + return Result; + } + } + + if (fieldFromInstruction_4(Insn32, 24, 8) == 0xF9) { + uint32_t NEONLdStInsn = Insn32; + NEONLdStInsn &= 0xF0FFFFFF; + NEONLdStInsn |= 0x04000000; + Result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, + NEONLdStInsn, Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + Check(&Result, AddThumbPredicate(MI)); + return Result; + } + } + + if (fieldFromInstruction_4(Insn32, 24, 4) == 0xF) { + uint32_t NEONDataInsn = Insn32; + NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 + NEONDataInsn |= (NEONDataInsn & 0x10000000) >> + 4; // Move bit 28 to bit 24 + NEONDataInsn |= 0x12000000; // Set bits 28 and 25 + Result = decodeInstruction_4(DecoderTableNEONData32, MI, + NEONDataInsn, Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + Check(&Result, AddThumbPredicate(MI)); + return Result; + } + + uint32_t NEONCryptoInsn = Insn32; + NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 + NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> + 4; // Move bit 28 to bit 24 + NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 + Result = decodeInstruction_4(DecoderTablev8Crypto32, MI, + NEONCryptoInsn, Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + + uint32_t NEONv8Insn = Insn32; + NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 + Result = decodeInstruction_4(DecoderTablev8NEON32, MI, + NEONv8Insn, Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + uint32_t Coproc = fieldFromInstruction_4(Insn32, 8, 4); + const uint8_t *DecoderTable = ARM_isCDECoproc(Coproc, MI) ? + DecoderTableThumb2CDE32 : + DecoderTableThumb2CoProc32; + Result = decodeInstruction_4(DecoderTable, MI, Insn32, Address); + if (Result != MCDisassembler_Fail) { + *Size = 4; + Check(&Result, AddThumbPredicate(MI)); + return Result; + } + + *Size = 0; + return MCDisassembler_Fail; +} + +static const uint16_t GPRDecoderTable[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, + ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, + ARM_R12, ARM_SP, ARM_LR, ARM_PC }; + +static const uint16_t CLRMGPRDecoderTable[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, 0, ARM_LR, ARM_APSR +}; + +static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 15) + return MCDisassembler_Fail; + + unsigned Register = GPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 15) + return MCDisassembler_Fail; + + unsigned Register = CLRMGPRDecoderTable[RegNo]; + if (Register == 0) + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if (RegNo == 15) + S = MCDisassembler_SoftFail; + + Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + + return S; +} + +static DecodeStatus DecodeGPRnospRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if (RegNo == 13) + S = MCDisassembler_SoftFail; + + Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + + return S; +} + +static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if (RegNo == 15) { + MCOperand_CreateReg0(Inst, (ARM_APSR_NZCV)); + return MCDisassembler_Success; + } + + Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + return S; +} + +static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if (RegNo == 15) { + MCOperand_CreateReg0(Inst, (ARM_ZR)); + return MCDisassembler_Success; + } + + if (RegNo == 13) + Check(&S, MCDisassembler_SoftFail); + + Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + return S; +} + +static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + if (RegNo == 13) + return MCDisassembler_Fail; + Check(&S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); + return S; +} + +static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 7) + return MCDisassembler_Fail; + return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static const uint16_t GPRPairDecoderTable[] = { ARM_R0_R1, ARM_R2_R3, + ARM_R4_R5, ARM_R6_R7, + ARM_R8_R9, ARM_R10_R11, + ARM_R12_SP }; + +static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + // According to the Arm ARM RegNo = 14 is undefined, but we return fail + // rather than SoftFail as there is no GPRPair table entry for index 7. + if (RegNo > 13) + return MCDisassembler_Fail; + + if (RegNo & 1) + S = MCDisassembler_SoftFail; + + unsigned RegisterPair = GPRPairDecoderTable[RegNo / 2]; + MCOperand_CreateReg0(Inst, (RegisterPair)); + return S; +} + +static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 13) + return MCDisassembler_Fail; + + unsigned RegisterPair = GPRPairDecoderTable[RegNo / 2]; + MCOperand_CreateReg0(Inst, (RegisterPair)); + + if ((RegNo & 1) || RegNo > 10) + return MCDisassembler_SoftFail; + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRspRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo != 13) + return MCDisassembler_Fail; + + unsigned Register = GPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + unsigned Register = 0; + switch (RegNo) { + case 0: + Register = ARM_R0; + break; + case 1: + Register = ARM_R1; + break; + case 2: + Register = ARM_R2; + break; + case 3: + Register = ARM_R3; + break; + case 9: + Register = ARM_R9; + break; + case 12: + Register = ARM_R12; + break; + default: + return MCDisassembler_Fail; + } + + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if ((RegNo == 13 && + !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) || + RegNo == 15) + S = MCDisassembler_SoftFail; + + Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + return S; +} + +static const uint16_t SPRDecoderTable[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, + ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, + ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, + ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31 +}; + +static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Register = SPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static const uint16_t DPRDecoderTable[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, + ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, + ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, + ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31 +}; + +static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + bool hasD32 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureD32); + + if (RegNo > 31 || (!hasD32 && RegNo > 15)) + return MCDisassembler_Fail; + + unsigned Register = DPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 7) + return MCDisassembler_Fail; + return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeSPR_8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 15) + return MCDisassembler_Fail; + return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 15) + return MCDisassembler_Fail; + return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static const uint16_t QPRDecoderTable[] = { + ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, + ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15 +}; + +static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31 || (RegNo & 1) != 0) + return MCDisassembler_Fail; + RegNo >>= 1; + + unsigned Register = QPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static const uint16_t DPairDecoderTable[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, + ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, + ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, + ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, + ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, + ARM_Q15 +}; + +static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 30) + return MCDisassembler_Fail; + + unsigned Register = DPairDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static const uint16_t DPairSpacedDecoderTable[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, + ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, + ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, + ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, + ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, + ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31 +}; + +static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 29) + return MCDisassembler_Fail; + + unsigned Register = DPairSpacedDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + if (Val == 0xF) + return MCDisassembler_Fail; + // AL predicate is not allowed on Thumb1 branches. + if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE) + return MCDisassembler_Fail; + if (Val != ARMCC_AL && + !MCInst_isPredicable(&ARMInsts[MCInst_getOpcode(Inst)])) + Check(&S, MCDisassembler_SoftFail); + MCOperand_CreateImm0(Inst, (Val)); + if (Val == ARMCC_AL) { + MCOperand_CreateReg0(Inst, (0)); + } else + MCOperand_CreateReg0(Inst, (ARM_CPSR)); + return S; +} + +static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + if (Val) + MCOperand_CreateReg0(Inst, (ARM_CPSR)); + else + MCOperand_CreateReg0(Inst, (0)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + unsigned type = fieldFromInstruction_4(Val, 5, 2); + unsigned imm = fieldFromInstruction_4(Val, 7, 5); + + // Register-immediate + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + ARM_AM_ShiftOpc Shift = ARM_AM_lsl; + switch (type) { + case 0: + Shift = ARM_AM_lsl; + break; + case 1: + Shift = ARM_AM_lsr; + break; + case 2: + Shift = ARM_AM_asr; + break; + case 3: + Shift = ARM_AM_ror; + break; + } + + if (Shift == ARM_AM_ror && imm == 0) + Shift = ARM_AM_rrx; + + unsigned Op = Shift | (imm << 3); + MCOperand_CreateImm0(Inst, (Op)); + + return S; +} + +static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + unsigned type = fieldFromInstruction_4(Val, 5, 2); + unsigned Rs = fieldFromInstruction_4(Val, 8, 4); + + // Register-register + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) + return MCDisassembler_Fail; + + ARM_AM_ShiftOpc Shift = ARM_AM_lsl; + switch (type) { + case 0: + Shift = ARM_AM_lsl; + break; + case 1: + Shift = ARM_AM_lsr; + break; + case 2: + Shift = ARM_AM_asr; + break; + case 3: + Shift = ARM_AM_ror; + break; + } + + MCOperand_CreateImm0(Inst, (Shift)); + + return S; +} + +static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + bool NeedDisjointWriteback = false; + unsigned WritebackReg = 0; + bool CLRM = false; + switch (MCInst_getOpcode(Inst)) { + default: + break; + case ARM_LDMIA_UPD: + case ARM_LDMDB_UPD: + case ARM_LDMIB_UPD: + case ARM_LDMDA_UPD: + case ARM_t2LDMIA_UPD: + case ARM_t2LDMDB_UPD: + case ARM_t2STMIA_UPD: + case ARM_t2STMDB_UPD: + NeedDisjointWriteback = true; + WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, (0))); + break; + case ARM_t2CLRM: + CLRM = true; + break; + } + + // Empty register lists are not allowed. + if (Val == 0) + return MCDisassembler_Fail; + for (unsigned i = 0; i < 16; ++i) { + if (Val & (1 << i)) { + if (CLRM) { + if (!Check(&S, DecodeCLRMGPRRegisterClass( + Inst, i, Address, + Decoder))) { + return MCDisassembler_Fail; + } + } else { + if (!Check(&S, DecodeGPRRegisterClass(Inst, i, + Address, + Decoder))) + return MCDisassembler_Fail; + // Writeback not allowed if Rn is in the target list. + if (NeedDisjointWriteback && + WritebackReg == + MCOperand_getReg(&( + Inst->Operands[Inst->size - + 1]))) + Check(&S, MCDisassembler_SoftFail); + } + } + } + + return S; +} + +static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Vd = fieldFromInstruction_4(Val, 8, 5); + unsigned regs = fieldFromInstruction_4(Val, 0, 8); + + // In case of unpredictable encoding, tweak the operands. + if (regs == 0 || (Vd + regs) > 32) { + regs = Vd + regs > 32 ? 32 - Vd : regs; + regs = regs > 1u ? regs : 1u; + S = MCDisassembler_SoftFail; + } + + if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + for (unsigned i = 0; i < (regs - 1); ++i) { + if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, + Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Vd = fieldFromInstruction_4(Val, 8, 5); + unsigned regs = fieldFromInstruction_4(Val, 1, 7); + + // In case of unpredictable encoding, tweak the operands. + if (regs == 0 || regs > 16 || (Vd + regs) > 32) { + regs = Vd + regs > 32 ? 32 - Vd : regs; + regs = regs > 1u ? regs : 1u; + regs = regs < 16u ? regs : 16u; + S = MCDisassembler_SoftFail; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + for (unsigned i = 0; i < (regs - 1); ++i) { + if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, + Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + // This operand encodes a mask of contiguous zeros between a specified MSB + // and LSB. To decode it, we create the mask of all bits MSB-and-lower, + // the mask of all bits LSB-and-lower, and then xor them to create + // the mask of that's all ones on [msb, lsb]. Finally we not it to + // create the final mask. + unsigned msb = fieldFromInstruction_4(Val, 5, 5); + unsigned lsb = fieldFromInstruction_4(Val, 0, 5); + + DecodeStatus S = MCDisassembler_Success; + if (lsb > msb) { + Check(&S, MCDisassembler_SoftFail); + // The check above will cause the warning for the "potentially undefined + // instruction encoding" but we can't build a bad MCOperand value here + // with a lsb > msb or else printing the MCInst will cause a crash. + lsb = msb; + } + + uint32_t msb_mask = 0xFFFFFFFF; + if (msb != 31) + msb_mask = (1U << (msb + 1)) - 1; + uint32_t lsb_mask = (1U << lsb) - 1; + + MCOperand_CreateImm0(Inst, (~(msb_mask ^ lsb_mask))); + return S; +} + +static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned CRd = fieldFromInstruction_4(Insn, 12, 4); + unsigned coproc = fieldFromInstruction_4(Insn, 8, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 8); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned U = fieldFromInstruction_4(Insn, 23, 1); + + // Pre-Indexed implies writeback to Rn + bool IsPreIndexed = (P == 1) && (W == 1); + + switch (MCInst_getOpcode(Inst)) { + case ARM_LDC_OFFSET: + case ARM_LDC_PRE: + case ARM_LDC_POST: + case ARM_LDC_OPTION: + case ARM_LDCL_OFFSET: + case ARM_LDCL_PRE: + case ARM_LDCL_POST: + case ARM_LDCL_OPTION: + case ARM_STC_OFFSET: + case ARM_STC_PRE: + case ARM_STC_POST: + case ARM_STC_OPTION: + case ARM_STCL_OFFSET: + case ARM_STCL_PRE: + case ARM_STCL_POST: + case ARM_STCL_OPTION: + case ARM_t2LDC_OFFSET: + case ARM_t2LDC_PRE: + case ARM_t2LDC_POST: + case ARM_t2LDC_OPTION: + case ARM_t2LDCL_OFFSET: + case ARM_t2LDCL_PRE: + case ARM_t2LDCL_POST: + case ARM_t2LDCL_OPTION: + case ARM_t2STC_OFFSET: + case ARM_t2STC_PRE: + case ARM_t2STC_POST: + case ARM_t2STC_OPTION: + case ARM_t2STCL_OFFSET: + case ARM_t2STCL_PRE: + case ARM_t2STCL_POST: + case ARM_t2STCL_OPTION: + case ARM_t2LDC2_OFFSET: + case ARM_t2LDC2L_OFFSET: + case ARM_t2LDC2_PRE: + case ARM_t2LDC2L_PRE: + case ARM_t2STC2_OFFSET: + case ARM_t2STC2L_OFFSET: + case ARM_t2STC2_PRE: + case ARM_t2STC2L_PRE: + case ARM_LDC2_OFFSET: + case ARM_LDC2L_OFFSET: + case ARM_LDC2_PRE: + case ARM_LDC2L_PRE: + case ARM_STC2_OFFSET: + case ARM_STC2L_OFFSET: + case ARM_STC2_PRE: + case ARM_STC2L_PRE: + case ARM_t2LDC2_OPTION: + case ARM_t2STC2_OPTION: + case ARM_t2LDC2_POST: + case ARM_t2LDC2L_POST: + case ARM_t2STC2_POST: + case ARM_t2STC2L_POST: + case ARM_LDC2_POST: + case ARM_LDC2L_POST: + case ARM_STC2_POST: + case ARM_STC2L_POST: + if (coproc == 0xA || coproc == 0xB || + (ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV8_1MMainlineOps) && + (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || + coproc == 0xB || coproc == 0xE || coproc == 0xF))) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && (coproc != 14)) + return MCDisassembler_Fail; + + if (IsPreIndexed) + // Dummy operand for Rn_wb. + MCOperand_CreateImm0(Inst, (0)); + + MCOperand_CreateImm0(Inst, (coproc)); + MCOperand_CreateImm0(Inst, (CRd)); + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDC2_OFFSET: + case ARM_t2LDC2L_OFFSET: + case ARM_t2LDC2_PRE: + case ARM_t2LDC2L_PRE: + case ARM_t2STC2_OFFSET: + case ARM_t2STC2L_OFFSET: + case ARM_t2STC2_PRE: + case ARM_t2STC2L_PRE: + case ARM_LDC2_OFFSET: + case ARM_LDC2L_OFFSET: + case ARM_LDC2_PRE: + case ARM_LDC2L_PRE: + case ARM_STC2_OFFSET: + case ARM_STC2L_OFFSET: + case ARM_STC2_PRE: + case ARM_STC2L_PRE: + case ARM_t2LDC_OFFSET: + case ARM_t2LDCL_OFFSET: + case ARM_t2LDC_PRE: + case ARM_t2LDCL_PRE: + case ARM_t2STC_OFFSET: + case ARM_t2STCL_OFFSET: + case ARM_t2STC_PRE: + case ARM_t2STCL_PRE: + case ARM_LDC_OFFSET: + case ARM_LDCL_OFFSET: + case ARM_LDC_PRE: + case ARM_LDCL_PRE: + case ARM_STC_OFFSET: + case ARM_STCL_OFFSET: + case ARM_STC_PRE: + case ARM_STCL_PRE: + imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, imm); + MCOperand_CreateImm0(Inst, (imm)); + break; + case ARM_t2LDC2_POST: + case ARM_t2LDC2L_POST: + case ARM_t2STC2_POST: + case ARM_t2STC2L_POST: + case ARM_LDC2_POST: + case ARM_LDC2L_POST: + case ARM_STC2_POST: + case ARM_STC2L_POST: + case ARM_t2LDC_POST: + case ARM_t2LDCL_POST: + case ARM_t2STC_POST: + case ARM_t2STCL_POST: + case ARM_LDC_POST: + case ARM_LDCL_POST: + case ARM_STC_POST: + case ARM_STCL_POST: + imm |= U << 8; + // fall through + default: + // The 'option' variant doesn't encode 'U' in the immediate since + // the immediate is unsigned [0,255]. + MCOperand_CreateImm0(Inst, (imm)); + break; + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_LDC_OFFSET: + case ARM_LDC_PRE: + case ARM_LDC_POST: + case ARM_LDC_OPTION: + case ARM_LDCL_OFFSET: + case ARM_LDCL_PRE: + case ARM_LDCL_POST: + case ARM_LDCL_OPTION: + case ARM_STC_OFFSET: + case ARM_STC_PRE: + case ARM_STC_POST: + case ARM_STC_OPTION: + case ARM_STCL_OFFSET: + case ARM_STCL_PRE: + case ARM_STCL_POST: + case ARM_STCL_OPTION: + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, + Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + return S; +} + +static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned reg = fieldFromInstruction_4(Insn, 25, 1); + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + + // On stores, the writeback operand precedes Rt. + switch (MCInst_getOpcode(Inst)) { + case ARM_STR_POST_IMM: + case ARM_STR_POST_REG: + case ARM_STRB_POST_IMM: + case ARM_STRB_POST_REG: + case ARM_STRT_POST_REG: + case ARM_STRT_POST_IMM: + case ARM_STRBT_POST_REG: + case ARM_STRBT_POST_IMM: + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + // On loads, the writeback operand comes after Rt. + switch (MCInst_getOpcode(Inst)) { + case ARM_LDR_POST_IMM: + case ARM_LDR_POST_REG: + case ARM_LDRB_POST_IMM: + case ARM_LDRB_POST_REG: + case ARM_LDRBT_POST_REG: + case ARM_LDRBT_POST_IMM: + case ARM_LDRT_POST_REG: + case ARM_LDRT_POST_IMM: + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + ARM_AM_AddrOpc Op = ARM_AM_add; + if (!fieldFromInstruction_4(Insn, 23, 1)) + Op = ARM_AM_sub; + + bool writeback = (P == 0) || (W == 1); + unsigned idx_mode = 0; + if (P && writeback) + idx_mode = ARMII_IndexModePre; + else if (!P && writeback) + idx_mode = ARMII_IndexModePost; + + if (writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler_SoftFail; // UNPREDICTABLE + + if (reg) { + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, + Decoder))) + return MCDisassembler_Fail; + ARM_AM_ShiftOpc Opc = ARM_AM_lsl; + switch (fieldFromInstruction_4(Insn, 5, 2)) { + case 0: + Opc = ARM_AM_lsl; + break; + case 1: + Opc = ARM_AM_lsr; + break; + case 2: + Opc = ARM_AM_asr; + break; + case 3: + Opc = ARM_AM_ror; + break; + default: + return MCDisassembler_Fail; + } + unsigned amt = fieldFromInstruction_4(Insn, 7, 5); + if (Opc == ARM_AM_ror && amt == 0) + Opc = ARM_AM_rrx; + imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode); + + MCOperand_CreateImm0(Inst, (imm)); + } else { + MCOperand_CreateReg0(Inst, (0)); + unsigned tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode); + MCOperand_CreateImm0(Inst, (tmp)); + } + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 13, 4); + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + unsigned type = fieldFromInstruction_4(Val, 5, 2); + unsigned imm = fieldFromInstruction_4(Val, 7, 5); + unsigned U = fieldFromInstruction_4(Val, 12, 1); + + ARM_AM_ShiftOpc ShOp = ARM_AM_lsl; + switch (type) { + case 0: + ShOp = ARM_AM_lsl; + break; + case 1: + ShOp = ARM_AM_lsr; + break; + case 2: + ShOp = ARM_AM_asr; + break; + case 3: + ShOp = ARM_AM_ror; + break; + } + + if (ShOp == ARM_AM_ror && imm == 0) + ShOp = ARM_AM_rrx; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + unsigned shift; + if (U) + shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); + else + shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); + MCOperand_CreateImm0(Inst, (shift)); + + return S; +} + +static DecodeStatus DecodeTSBInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + if (MCInst_getOpcode(Inst) != ARM_TSB && + MCInst_getOpcode(Inst) != ARM_t2TSB) + return MCDisassembler_Fail; + + // The "csync" operand is not encoded into the "tsb" instruction (as this is + // the only available operand), but LLVM expects the instruction to have one + // operand, so we need to add the csync when decoding. + MCOperand_CreateImm0(Inst, (ARM_TSB_CSYNC)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned type = fieldFromInstruction_4(Insn, 22, 1); + unsigned imm = fieldFromInstruction_4(Insn, 8, 4); + unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8; + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + unsigned Rt2 = Rt + 1; + + bool writeback = (W == 1) | (P == 0); + + // For {LD,ST}RD, Rt must be even, else undefined. + switch (MCInst_getOpcode(Inst)) { + case ARM_STRD: + case ARM_STRD_PRE: + case ARM_STRD_POST: + case ARM_LDRD: + case ARM_LDRD_PRE: + case ARM_LDRD_POST: + if (Rt & 0x1) + S = MCDisassembler_SoftFail; + break; + default: + break; + } + switch (MCInst_getOpcode(Inst)) { + case ARM_STRD: + case ARM_STRD_PRE: + case ARM_STRD_POST: + if (P == 0 && W == 1) + S = MCDisassembler_SoftFail; + + if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) + S = MCDisassembler_SoftFail; + if (type && Rm == 15) + S = MCDisassembler_SoftFail; + if (Rt2 == 15) + S = MCDisassembler_SoftFail; + if (!type && fieldFromInstruction_4(Insn, 8, 4)) + S = MCDisassembler_SoftFail; + break; + case ARM_STRH: + case ARM_STRH_PRE: + case ARM_STRH_POST: + if (Rt == 15) + S = MCDisassembler_SoftFail; + if (writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler_SoftFail; + if (!type && Rm == 15) + S = MCDisassembler_SoftFail; + break; + case ARM_LDRD: + case ARM_LDRD_PRE: + case ARM_LDRD_POST: + if (type && Rn == 15) { + if (Rt2 == 15) + S = MCDisassembler_SoftFail; + break; + } + if (P == 0 && W == 1) + S = MCDisassembler_SoftFail; + if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) + S = MCDisassembler_SoftFail; + if (!type && writeback && Rn == 15) + S = MCDisassembler_SoftFail; + if (writeback && (Rn == Rt || Rn == Rt2)) + S = MCDisassembler_SoftFail; + break; + case ARM_LDRH: + case ARM_LDRH_PRE: + case ARM_LDRH_POST: + if (type && Rn == 15) { + if (Rt == 15) + S = MCDisassembler_SoftFail; + break; + } + if (Rt == 15) + S = MCDisassembler_SoftFail; + if (!type && Rm == 15) + S = MCDisassembler_SoftFail; + if (!type && writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler_SoftFail; + break; + case ARM_LDRSH: + case ARM_LDRSH_PRE: + case ARM_LDRSH_POST: + case ARM_LDRSB: + case ARM_LDRSB_PRE: + case ARM_LDRSB_POST: + if (type && Rn == 15) { + if (Rt == 15) + S = MCDisassembler_SoftFail; + break; + } + if (type && (Rt == 15 || (writeback && Rn == Rt))) + S = MCDisassembler_SoftFail; + if (!type && (Rt == 15 || Rm == 15)) + S = MCDisassembler_SoftFail; + if (!type && writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler_SoftFail; + break; + default: + break; + } + + if (writeback) { // Writeback + if (P) + U |= ARMII_IndexModePre << 9; + else + U |= ARMII_IndexModePost << 9; + + // On stores, the writeback operand precedes Rt. + switch (MCInst_getOpcode(Inst)) { + case ARM_STRD: + case ARM_STRD_PRE: + case ARM_STRD_POST: + case ARM_STRH: + case ARM_STRH_PRE: + case ARM_STRH_POST: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, + Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + switch (MCInst_getOpcode(Inst)) { + case ARM_STRD: + case ARM_STRD_PRE: + case ARM_STRD_POST: + case ARM_LDRD: + case ARM_LDRD_PRE: + case ARM_LDRD_POST: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt + 1, Address, + Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (writeback) { + // On loads, the writeback operand comes after Rt. + switch (MCInst_getOpcode(Inst)) { + case ARM_LDRD: + case ARM_LDRD_PRE: + case ARM_LDRD_POST: + case ARM_LDRH: + case ARM_LDRH_PRE: + case ARM_LDRH_POST: + case ARM_LDRSH: + case ARM_LDRSH_PRE: + case ARM_LDRSH_POST: + case ARM_LDRSB: + case ARM_LDRSB_PRE: + case ARM_LDRSB_POST: + case ARM_LDRHTr: + case ARM_LDRSBTr: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, + Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (type) { + MCOperand_CreateReg0(Inst, (0)); + MCOperand_CreateImm0(Inst, (U | (imm << 4) | Rm)); + } else { + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (U)); + } + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned mode = fieldFromInstruction_4(Insn, 23, 2); + + switch (mode) { + case 0: + mode = ARM_AM_da; + break; + case 1: + mode = ARM_AM_ia; + break; + case 2: + mode = ARM_AM_db; + break; + case 3: + mode = ARM_AM_ib; + break; + } + + MCOperand_CreateImm0(Inst, (mode)); + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (pred == 0xF) + return DecodeCPSInstruction(Inst, Insn, Address, Decoder); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + return S; +} + +static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned reglist = fieldFromInstruction_4(Insn, 0, 16); + + if (pred == 0xF) { + // Ambiguous with RFE and SRS + switch (MCInst_getOpcode(Inst)) { + case ARM_LDMDA: + MCInst_setOpcode(Inst, (ARM_RFEDA)); + break; + case ARM_LDMDA_UPD: + MCInst_setOpcode(Inst, (ARM_RFEDA_UPD)); + break; + case ARM_LDMDB: + MCInst_setOpcode(Inst, (ARM_RFEDB)); + break; + case ARM_LDMDB_UPD: + MCInst_setOpcode(Inst, (ARM_RFEDB_UPD)); + break; + case ARM_LDMIA: + MCInst_setOpcode(Inst, (ARM_RFEIA)); + break; + case ARM_LDMIA_UPD: + MCInst_setOpcode(Inst, (ARM_RFEIA_UPD)); + break; + case ARM_LDMIB: + MCInst_setOpcode(Inst, (ARM_RFEIB)); + break; + case ARM_LDMIB_UPD: + MCInst_setOpcode(Inst, (ARM_RFEIB_UPD)); + break; + case ARM_STMDA: + MCInst_setOpcode(Inst, (ARM_SRSDA)); + break; + case ARM_STMDA_UPD: + MCInst_setOpcode(Inst, (ARM_SRSDA_UPD)); + break; + case ARM_STMDB: + MCInst_setOpcode(Inst, (ARM_SRSDB)); + break; + case ARM_STMDB_UPD: + MCInst_setOpcode(Inst, (ARM_SRSDB_UPD)); + break; + case ARM_STMIA: + MCInst_setOpcode(Inst, (ARM_SRSIA)); + break; + case ARM_STMIA_UPD: + MCInst_setOpcode(Inst, (ARM_SRSIA_UPD)); + break; + case ARM_STMIB: + MCInst_setOpcode(Inst, (ARM_SRSIB)); + break; + case ARM_STMIB_UPD: + MCInst_setOpcode(Inst, (ARM_SRSIB_UPD)); + break; + default: + return MCDisassembler_Fail; + } + + // For stores (which become SRS's, the only operand is the mode. + if (fieldFromInstruction_4(Insn, 20, 1) == 0) { + // Check SRS encoding constraints + if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 && + fieldFromInstruction_4(Insn, 20, 1) == 0)) + return MCDisassembler_Fail; + + MCOperand_CreateImm0( + Inst, (fieldFromInstruction_4(Insn, 0, 4))); + return S; + } + + return DecodeRFEInstruction(Inst, Insn, Address, Decoder); + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; // Tied + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +// Check for UNPREDICTABLE predicated ESB instruction +static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned imm8 = fieldFromInstruction_4(Insn, 0, 8); + + DecodeStatus S = MCDisassembler_Success; + + MCOperand_CreateImm0(Inst, (imm8)); + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + // ESB is unpredictable if pred != AL. Without the RAS extension, it is a + // NOP, so all predicates should be allowed. + if (imm8 == 0x10 && pred != 0xe && + ((ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureRAS)) != 0)) + S = MCDisassembler_SoftFail; + + return S; +} + +static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + unsigned imod = fieldFromInstruction_4(Insn, 18, 2); + unsigned M = fieldFromInstruction_4(Insn, 17, 1); + unsigned iflags = fieldFromInstruction_4(Insn, 6, 3); + unsigned mode = fieldFromInstruction_4(Insn, 0, 5); + + DecodeStatus S = MCDisassembler_Success; + + // This decoder is called from multiple location that do not check + // the full encoding is valid before they do. + if (fieldFromInstruction_4(Insn, 5, 1) != 0 || + fieldFromInstruction_4(Insn, 16, 1) != 0 || + fieldFromInstruction_4(Insn, 20, 8) != 0x10) + return MCDisassembler_Fail; + + // imod == '01' --> UNPREDICTABLE + // NOTE: Even though this is technically UNPREDICTABLE, we choose to + // return failure here. The '01' imod value is unprintable, so there's + // nothing useful we could do even if we returned UNPREDICTABLE. + + if (imod == 1) + return MCDisassembler_Fail; + + if (imod && M) { + MCInst_setOpcode(Inst, (ARM_CPS3p)); + MCOperand_CreateImm0(Inst, (imod)); + MCOperand_CreateImm0(Inst, (iflags)); + MCOperand_CreateImm0(Inst, (mode)); + } else if (imod && !M) { + MCInst_setOpcode(Inst, (ARM_CPS2p)); + MCOperand_CreateImm0(Inst, (imod)); + MCOperand_CreateImm0(Inst, (iflags)); + if (mode) + S = MCDisassembler_SoftFail; + } else if (!imod && M) { + MCInst_setOpcode(Inst, (ARM_CPS1p)); + MCOperand_CreateImm0(Inst, (mode)); + if (iflags) + S = MCDisassembler_SoftFail; + } else { + // imod == '00' && M == '0' --> UNPREDICTABLE + MCInst_setOpcode(Inst, (ARM_CPS1p)); + MCOperand_CreateImm0(Inst, (mode)); + S = MCDisassembler_SoftFail; + } + + return S; +} + +static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + unsigned imod = fieldFromInstruction_4(Insn, 9, 2); + unsigned M = fieldFromInstruction_4(Insn, 8, 1); + unsigned iflags = fieldFromInstruction_4(Insn, 5, 3); + unsigned mode = fieldFromInstruction_4(Insn, 0, 5); + + DecodeStatus S = MCDisassembler_Success; + + // imod == '01' --> UNPREDICTABLE + // NOTE: Even though this is technically UNPREDICTABLE, we choose to + // return failure here. The '01' imod value is unprintable, so there's + // nothing useful we could do even if we returned UNPREDICTABLE. + + if (imod == 1) + return MCDisassembler_Fail; + + if (imod && M) { + MCInst_setOpcode(Inst, (ARM_t2CPS3p)); + MCOperand_CreateImm0(Inst, (imod)); + MCOperand_CreateImm0(Inst, (iflags)); + MCOperand_CreateImm0(Inst, (mode)); + } else if (imod && !M) { + MCInst_setOpcode(Inst, (ARM_t2CPS2p)); + MCOperand_CreateImm0(Inst, (imod)); + MCOperand_CreateImm0(Inst, (iflags)); + if (mode) + S = MCDisassembler_SoftFail; + } else if (!imod && M) { + MCInst_setOpcode(Inst, (ARM_t2CPS1p)); + MCOperand_CreateImm0(Inst, (mode)); + if (iflags) + S = MCDisassembler_SoftFail; + } else { + // imod == '00' && M == '0' --> this is a HINT instruction + int imm = fieldFromInstruction_4(Insn, 0, 8); + // HINT are defined only for immediate in [0..4] + if (imm > 4) + return MCDisassembler_Fail; + MCInst_setOpcode(Inst, (ARM_t2HINT)); + MCOperand_CreateImm0(Inst, (imm)); + } + + return S; +} + +static DecodeStatus DecodeT2HintSpaceInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + unsigned imm = fieldFromInstruction_4(Insn, 0, 8); + + unsigned Opcode = ARM_t2HINT; + + if (imm == 0x0D) { + Opcode = ARM_t2PACBTI; + } else if (imm == 0x1D) { + Opcode = ARM_t2PAC; + } else if (imm == 0x2D) { + Opcode = ARM_t2AUT; + } else if (imm == 0x0F) { + Opcode = ARM_t2BTI; + } + + MCInst_setOpcode(Inst, (Opcode)); + if (Opcode == ARM_t2HINT) { + MCOperand_CreateImm0(Inst, (imm)); + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); + unsigned imm = 0; + + imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0); + imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8); + imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); + imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11); + + if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16) + if (!Check(&S, + DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, (imm)); + + return S; +} + +static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned imm = 0; + + imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0); + imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); + + if (MCInst_getOpcode(Inst) == ARM_MOVTi16) + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, + Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, (imm)); + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 8, 4); + unsigned Ra = fieldFromInstruction_4(Insn, 12, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (pred == 0xF) + return DecodeCPSInstruction(Inst, Insn, Address, Decoder); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + + if (Pred == 0xF) + return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Imm = fieldFromInstruction_4(Insn, 9, 1); + + if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps) || + !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) + return MCDisassembler_Fail; + + // Decoder can be called from DecodeTST, which does not check the full + // encoding is valid. + if (fieldFromInstruction_4(Insn, 20, 12) != 0xf11 || + fieldFromInstruction_4(Insn, 4, 4) != 0) + return MCDisassembler_Fail; + if (fieldFromInstruction_4(Insn, 10, 10) != 0 || + fieldFromInstruction_4(Insn, 0, 4) != 0) + S = MCDisassembler_SoftFail; + + MCInst_setOpcode(Inst, (ARM_SETPAN)); + MCOperand_CreateImm0(Inst, (Imm)); + + return S; +} + +static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned add = fieldFromInstruction_4(Val, 12, 1); + unsigned imm = fieldFromInstruction_4(Val, 0, 12); + unsigned Rn = fieldFromInstruction_4(Val, 13, 4); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!add) + imm *= -1; + if (imm == 0 && !add) + imm = INT32_MIN; + MCOperand_CreateImm0(Inst, (imm)); + if (Rn == 15) + tryAddingPcLoadReferenceComment(Address, Address + imm + 8, + Decoder); + + return S; +} + +static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 9, 4); + // U == 1 to add imm, 0 to subtract it. + unsigned U = fieldFromInstruction_4(Val, 8, 1); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (U) + MCOperand_CreateImm0(Inst, (ARM_AM_getAM5Opc(ARM_AM_add, imm))); + else + MCOperand_CreateImm0(Inst, (ARM_AM_getAM5Opc(ARM_AM_sub, imm))); + + return S; +} + +static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 9, 4); + // U == 1 to add imm, 0 to subtract it. + unsigned U = fieldFromInstruction_4(Val, 8, 1); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (U) + MCOperand_CreateImm0(Inst, + (ARM_AM_getAM5FP16Opc(ARM_AM_add, imm))); + else + MCOperand_CreateImm0(Inst, + (ARM_AM_getAM5FP16Opc(ARM_AM_sub, imm))); + + return S; +} + +static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); +} + +static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus Status = MCDisassembler_Success; + + // Note the J1 and J2 values are from the encoded instruction. So here + // change them to I1 and I2 values via as documented: + // I1 = NOT(J1 EOR S); + // I2 = NOT(J2 EOR S); + // and build the imm32 with one trailing zero as documented: + // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); + unsigned S = fieldFromInstruction_4(Insn, 26, 1); + unsigned J1 = fieldFromInstruction_4(Insn, 13, 1); + unsigned J2 = fieldFromInstruction_4(Insn, 11, 1); + unsigned I1 = !(J1 ^ S); + unsigned I2 = !(J2 ^ S); + unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10); + unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11); + unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | + imm11; + int imm32 = SignExtend32((tmp << 1), 25); + if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, true, 4, + Inst, Decoder)) + MCOperand_CreateImm0(Inst, (imm32)); + + return Status; +} + +static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2; + + if (pred == 0xF) { + MCInst_setOpcode(Inst, (ARM_BLXi)); + imm |= fieldFromInstruction_4(Insn, 24, 1) << 1; + if (!tryAddingSymbolicOperand( + Address, Address + SignExtend32((imm), 26) + 8, + true, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, (SignExtend32((imm), 26))); + return S; + } + + if (!tryAddingSymbolicOperand(Address, + Address + SignExtend32((imm), 26) + 8, + true, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, (SignExtend32((imm), 26))); + + // We already have BL_pred for BL w/ predicate, no need to add addition + // predicate opreands for BL + if (MCInst_getOpcode(Inst) != ARM_BL) + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, + Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + unsigned align = fieldFromInstruction_4(Val, 4, 2); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!align) + MCOperand_CreateImm0(Inst, (0)); + else + MCOperand_CreateImm0(Inst, (4 << align)); + + return S; +} + +static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned wb = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + + // First output register + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD1q16: + case ARM_VLD1q32: + case ARM_VLD1q64: + case ARM_VLD1q8: + case ARM_VLD1q16wb_fixed: + case ARM_VLD1q16wb_register: + case ARM_VLD1q32wb_fixed: + case ARM_VLD1q32wb_register: + case ARM_VLD1q64wb_fixed: + case ARM_VLD1q64wb_register: + case ARM_VLD1q8wb_fixed: + case ARM_VLD1q8wb_register: + case ARM_VLD2d16: + case ARM_VLD2d32: + case ARM_VLD2d8: + case ARM_VLD2d16wb_fixed: + case ARM_VLD2d16wb_register: + case ARM_VLD2d32wb_fixed: + case ARM_VLD2d32wb_register: + case ARM_VLD2d8wb_fixed: + case ARM_VLD2d8wb_register: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, + Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD2b16: + case ARM_VLD2b32: + case ARM_VLD2b8: + case ARM_VLD2b16wb_fixed: + case ARM_VLD2b16wb_register: + case ARM_VLD2b32wb_fixed: + case ARM_VLD2b32wb_register: + case ARM_VLD2b8wb_fixed: + case ARM_VLD2b8wb_register: + if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, + Decoder))) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + } + + // Second output register + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD3d8: + case ARM_VLD3d16: + case ARM_VLD3d32: + case ARM_VLD3d8_UPD: + case ARM_VLD3d16_UPD: + case ARM_VLD3d32_UPD: + case ARM_VLD4d8: + case ARM_VLD4d16: + case ARM_VLD4d32: + case ARM_VLD4d8_UPD: + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD3q8: + case ARM_VLD3q16: + case ARM_VLD3q32: + case ARM_VLD3q8_UPD: + case ARM_VLD3q16_UPD: + case ARM_VLD3q32_UPD: + case ARM_VLD4q8: + case ARM_VLD4q16: + case ARM_VLD4q32: + case ARM_VLD4q8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Third output register + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD3d8: + case ARM_VLD3d16: + case ARM_VLD3d32: + case ARM_VLD3d8_UPD: + case ARM_VLD3d16_UPD: + case ARM_VLD3d32_UPD: + case ARM_VLD4d8: + case ARM_VLD4d16: + case ARM_VLD4d32: + case ARM_VLD4d8_UPD: + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD3q8: + case ARM_VLD3q16: + case ARM_VLD3q32: + case ARM_VLD3q8_UPD: + case ARM_VLD3q16_UPD: + case ARM_VLD3q32_UPD: + case ARM_VLD4q8: + case ARM_VLD4q16: + case ARM_VLD4q32: + case ARM_VLD4q8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Fourth output register + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD4d8: + case ARM_VLD4d16: + case ARM_VLD4d32: + case ARM_VLD4d8_UPD: + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD4q8: + case ARM_VLD4q16: + case ARM_VLD4q32: + case ARM_VLD4q8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Writeback operand + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD1d8wb_fixed: + case ARM_VLD1d16wb_fixed: + case ARM_VLD1d32wb_fixed: + case ARM_VLD1d64wb_fixed: + case ARM_VLD1d8wb_register: + case ARM_VLD1d16wb_register: + case ARM_VLD1d32wb_register: + case ARM_VLD1d64wb_register: + case ARM_VLD1q8wb_fixed: + case ARM_VLD1q16wb_fixed: + case ARM_VLD1q32wb_fixed: + case ARM_VLD1q64wb_fixed: + case ARM_VLD1q8wb_register: + case ARM_VLD1q16wb_register: + case ARM_VLD1q32wb_register: + case ARM_VLD1q64wb_register: + case ARM_VLD1d8Twb_fixed: + case ARM_VLD1d8Twb_register: + case ARM_VLD1d16Twb_fixed: + case ARM_VLD1d16Twb_register: + case ARM_VLD1d32Twb_fixed: + case ARM_VLD1d32Twb_register: + case ARM_VLD1d64Twb_fixed: + case ARM_VLD1d64Twb_register: + case ARM_VLD1d8Qwb_fixed: + case ARM_VLD1d8Qwb_register: + case ARM_VLD1d16Qwb_fixed: + case ARM_VLD1d16Qwb_register: + case ARM_VLD1d32Qwb_fixed: + case ARM_VLD1d32Qwb_register: + case ARM_VLD1d64Qwb_fixed: + case ARM_VLD1d64Qwb_register: + case ARM_VLD2d8wb_fixed: + case ARM_VLD2d16wb_fixed: + case ARM_VLD2d32wb_fixed: + case ARM_VLD2q8wb_fixed: + case ARM_VLD2q16wb_fixed: + case ARM_VLD2q32wb_fixed: + case ARM_VLD2d8wb_register: + case ARM_VLD2d16wb_register: + case ARM_VLD2d32wb_register: + case ARM_VLD2q8wb_register: + case ARM_VLD2q16wb_register: + case ARM_VLD2q32wb_register: + case ARM_VLD2b8wb_fixed: + case ARM_VLD2b16wb_fixed: + case ARM_VLD2b32wb_fixed: + case ARM_VLD2b8wb_register: + case ARM_VLD2b16wb_register: + case ARM_VLD2b32wb_register: + MCOperand_CreateImm0(Inst, (0)); + break; + case ARM_VLD3d8_UPD: + case ARM_VLD3d16_UPD: + case ARM_VLD3d32_UPD: + case ARM_VLD3q8_UPD: + case ARM_VLD3q16_UPD: + case ARM_VLD3q32_UPD: + case ARM_VLD4d8_UPD: + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + case ARM_VLD4q8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + if (!Check(&S, + DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // AddrMode6 Base (register+alignment) + if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + // AddrMode6 Offset (register) + switch (MCInst_getOpcode(Inst)) { + default: + // The below have been updated to have explicit am6offset split + // between fixed and register offset. For those instructions not + // yet updated, we need to add an additional reg0 operand for the + // fixed variant. + // + // The fixed offset encodes as Rm == 0xd, so we check for that. + if (Rm == 0xd) { + MCOperand_CreateReg0(Inst, (0)); + break; + } + // Fall through to handle the register offset variant. + // fall through + case ARM_VLD1d8wb_fixed: + case ARM_VLD1d16wb_fixed: + case ARM_VLD1d32wb_fixed: + case ARM_VLD1d64wb_fixed: + case ARM_VLD1d8Twb_fixed: + case ARM_VLD1d16Twb_fixed: + case ARM_VLD1d32Twb_fixed: + case ARM_VLD1d64Twb_fixed: + case ARM_VLD1d8Qwb_fixed: + case ARM_VLD1d16Qwb_fixed: + case ARM_VLD1d32Qwb_fixed: + case ARM_VLD1d64Qwb_fixed: + case ARM_VLD1d8wb_register: + case ARM_VLD1d16wb_register: + case ARM_VLD1d32wb_register: + case ARM_VLD1d64wb_register: + case ARM_VLD1q8wb_fixed: + case ARM_VLD1q16wb_fixed: + case ARM_VLD1q32wb_fixed: + case ARM_VLD1q64wb_fixed: + case ARM_VLD1q8wb_register: + case ARM_VLD1q16wb_register: + case ARM_VLD1q32wb_register: + case ARM_VLD1q64wb_register: + // The fixed offset post-increment encodes Rm == 0xd. The no-writeback + // variant encodes Rm == 0xf. Anything else is a register offset post- + // increment and we need to add the register operand to the instruction. + if (Rm != 0xD && Rm != 0xF && + !Check(&S, + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD2d8wb_fixed: + case ARM_VLD2d16wb_fixed: + case ARM_VLD2d32wb_fixed: + case ARM_VLD2b8wb_fixed: + case ARM_VLD2b16wb_fixed: + case ARM_VLD2b32wb_fixed: + case ARM_VLD2q8wb_fixed: + case ARM_VLD2q16wb_fixed: + case ARM_VLD2q32wb_fixed: + break; + } + + return S; +} + +static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + unsigned type = fieldFromInstruction_4(Insn, 8, 4); + unsigned align = fieldFromInstruction_4(Insn, 4, 2); + if (type == 6 && (align & 2)) + return MCDisassembler_Fail; + if (type == 7 && (align & 2)) + return MCDisassembler_Fail; + if (type == 10 && align == 3) + return MCDisassembler_Fail; + + unsigned load = fieldFromInstruction_4(Insn, 21, 1); + return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) : + DecodeVSTInstruction(Inst, Insn, Address, Decoder); +} + +static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + if (size == 3) + return MCDisassembler_Fail; + + unsigned type = fieldFromInstruction_4(Insn, 8, 4); + unsigned align = fieldFromInstruction_4(Insn, 4, 2); + if (type == 8 && align == 3) + return MCDisassembler_Fail; + if (type == 9 && align == 3) + return MCDisassembler_Fail; + + unsigned load = fieldFromInstruction_4(Insn, 21, 1); + return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) : + DecodeVSTInstruction(Inst, Insn, Address, Decoder); +} + +static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + if (size == 3) + return MCDisassembler_Fail; + + unsigned align = fieldFromInstruction_4(Insn, 4, 2); + if (align & 2) + return MCDisassembler_Fail; + + unsigned load = fieldFromInstruction_4(Insn, 21, 1); + return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) : + DecodeVSTInstruction(Inst, Insn, Address, Decoder); +} + +static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + if (size == 3) + return MCDisassembler_Fail; + + unsigned load = fieldFromInstruction_4(Insn, 21, 1); + return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) : + DecodeVSTInstruction(Inst, Insn, Address, Decoder); +} + +static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned wb = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + + // Writeback Operand + switch (MCInst_getOpcode(Inst)) { + case ARM_VST1d8wb_fixed: + case ARM_VST1d16wb_fixed: + case ARM_VST1d32wb_fixed: + case ARM_VST1d64wb_fixed: + case ARM_VST1d8wb_register: + case ARM_VST1d16wb_register: + case ARM_VST1d32wb_register: + case ARM_VST1d64wb_register: + case ARM_VST1q8wb_fixed: + case ARM_VST1q16wb_fixed: + case ARM_VST1q32wb_fixed: + case ARM_VST1q64wb_fixed: + case ARM_VST1q8wb_register: + case ARM_VST1q16wb_register: + case ARM_VST1q32wb_register: + case ARM_VST1q64wb_register: + case ARM_VST1d8Twb_fixed: + case ARM_VST1d16Twb_fixed: + case ARM_VST1d32Twb_fixed: + case ARM_VST1d64Twb_fixed: + case ARM_VST1d8Twb_register: + case ARM_VST1d16Twb_register: + case ARM_VST1d32Twb_register: + case ARM_VST1d64Twb_register: + case ARM_VST1d8Qwb_fixed: + case ARM_VST1d16Qwb_fixed: + case ARM_VST1d32Qwb_fixed: + case ARM_VST1d64Qwb_fixed: + case ARM_VST1d8Qwb_register: + case ARM_VST1d16Qwb_register: + case ARM_VST1d32Qwb_register: + case ARM_VST1d64Qwb_register: + case ARM_VST2d8wb_fixed: + case ARM_VST2d16wb_fixed: + case ARM_VST2d32wb_fixed: + case ARM_VST2d8wb_register: + case ARM_VST2d16wb_register: + case ARM_VST2d32wb_register: + case ARM_VST2q8wb_fixed: + case ARM_VST2q16wb_fixed: + case ARM_VST2q32wb_fixed: + case ARM_VST2q8wb_register: + case ARM_VST2q16wb_register: + case ARM_VST2q32wb_register: + case ARM_VST2b8wb_fixed: + case ARM_VST2b16wb_fixed: + case ARM_VST2b32wb_fixed: + case ARM_VST2b8wb_register: + case ARM_VST2b16wb_register: + case ARM_VST2b32wb_register: + if (Rm == 0xF) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (0)); + break; + case ARM_VST3d8_UPD: + case ARM_VST3d16_UPD: + case ARM_VST3d32_UPD: + case ARM_VST3q8_UPD: + case ARM_VST3q16_UPD: + case ARM_VST3q32_UPD: + case ARM_VST4d8_UPD: + case ARM_VST4d16_UPD: + case ARM_VST4d32_UPD: + case ARM_VST4q8_UPD: + case ARM_VST4q16_UPD: + case ARM_VST4q32_UPD: + if (!Check(&S, + DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // AddrMode6 Base (register+alignment) + if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + // AddrMode6 Offset (register) + switch (MCInst_getOpcode(Inst)) { + default: + if (Rm == 0xD) + MCOperand_CreateReg0(Inst, (0)); + else if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, + Decoder))) + return MCDisassembler_Fail; + } + break; + case ARM_VST1d8wb_fixed: + case ARM_VST1d16wb_fixed: + case ARM_VST1d32wb_fixed: + case ARM_VST1d64wb_fixed: + case ARM_VST1q8wb_fixed: + case ARM_VST1q16wb_fixed: + case ARM_VST1q32wb_fixed: + case ARM_VST1q64wb_fixed: + case ARM_VST1d8Twb_fixed: + case ARM_VST1d16Twb_fixed: + case ARM_VST1d32Twb_fixed: + case ARM_VST1d64Twb_fixed: + case ARM_VST1d8Qwb_fixed: + case ARM_VST1d16Qwb_fixed: + case ARM_VST1d32Qwb_fixed: + case ARM_VST1d64Qwb_fixed: + case ARM_VST2d8wb_fixed: + case ARM_VST2d16wb_fixed: + case ARM_VST2d32wb_fixed: + case ARM_VST2q8wb_fixed: + case ARM_VST2q16wb_fixed: + case ARM_VST2q32wb_fixed: + case ARM_VST2b8wb_fixed: + case ARM_VST2b16wb_fixed: + case ARM_VST2b32wb_fixed: + break; + } + + // First input register + switch (MCInst_getOpcode(Inst)) { + case ARM_VST1q16: + case ARM_VST1q32: + case ARM_VST1q64: + case ARM_VST1q8: + case ARM_VST1q16wb_fixed: + case ARM_VST1q16wb_register: + case ARM_VST1q32wb_fixed: + case ARM_VST1q32wb_register: + case ARM_VST1q64wb_fixed: + case ARM_VST1q64wb_register: + case ARM_VST1q8wb_fixed: + case ARM_VST1q8wb_register: + case ARM_VST2d16: + case ARM_VST2d32: + case ARM_VST2d8: + case ARM_VST2d16wb_fixed: + case ARM_VST2d16wb_register: + case ARM_VST2d32wb_fixed: + case ARM_VST2d32wb_register: + case ARM_VST2d8wb_fixed: + case ARM_VST2d8wb_register: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, + Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VST2b16: + case ARM_VST2b32: + case ARM_VST2b8: + case ARM_VST2b16wb_fixed: + case ARM_VST2b16wb_register: + case ARM_VST2b32wb_fixed: + case ARM_VST2b32wb_register: + case ARM_VST2b8wb_fixed: + case ARM_VST2b8wb_register: + if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, + Decoder))) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + } + + // Second input register + switch (MCInst_getOpcode(Inst)) { + case ARM_VST3d8: + case ARM_VST3d16: + case ARM_VST3d32: + case ARM_VST3d8_UPD: + case ARM_VST3d16_UPD: + case ARM_VST3d32_UPD: + case ARM_VST4d8: + case ARM_VST4d16: + case ARM_VST4d32: + case ARM_VST4d8_UPD: + case ARM_VST4d16_UPD: + case ARM_VST4d32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VST3q8: + case ARM_VST3q16: + case ARM_VST3q32: + case ARM_VST3q8_UPD: + case ARM_VST3q16_UPD: + case ARM_VST3q32_UPD: + case ARM_VST4q8: + case ARM_VST4q16: + case ARM_VST4q32: + case ARM_VST4q8_UPD: + case ARM_VST4q16_UPD: + case ARM_VST4q32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Third input register + switch (MCInst_getOpcode(Inst)) { + case ARM_VST3d8: + case ARM_VST3d16: + case ARM_VST3d32: + case ARM_VST3d8_UPD: + case ARM_VST3d16_UPD: + case ARM_VST3d32_UPD: + case ARM_VST4d8: + case ARM_VST4d16: + case ARM_VST4d32: + case ARM_VST4d8_UPD: + case ARM_VST4d16_UPD: + case ARM_VST4d32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VST3q8: + case ARM_VST3q16: + case ARM_VST3q32: + case ARM_VST3q8_UPD: + case ARM_VST3q16_UPD: + case ARM_VST3q32_UPD: + case ARM_VST4q8: + case ARM_VST4q16: + case ARM_VST4q32: + case ARM_VST4q8_UPD: + case ARM_VST4q16_UPD: + case ARM_VST4q32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Fourth input register + switch (MCInst_getOpcode(Inst)) { + case ARM_VST4d8: + case ARM_VST4d16: + case ARM_VST4d32: + case ARM_VST4d8_UPD: + case ARM_VST4d16_UPD: + case ARM_VST4d32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VST4q8: + case ARM_VST4q16: + case ARM_VST4q32: + case ARM_VST4q8_UPD: + case ARM_VST4q16_UPD: + case ARM_VST4q32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + return S; +} + +static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned align = fieldFromInstruction_4(Insn, 4, 1); + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + + if (size == 0 && align == 1) + return MCDisassembler_Fail; + align *= (1 << size); + + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD1DUPq16: + case ARM_VLD1DUPq32: + case ARM_VLD1DUPq8: + case ARM_VLD1DUPq16wb_fixed: + case ARM_VLD1DUPq16wb_register: + case ARM_VLD1DUPq32wb_fixed: + case ARM_VLD1DUPq32wb_register: + case ARM_VLD1DUPq8wb_fixed: + case ARM_VLD1DUPq8wb_register: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, + Decoder))) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + } + if (Rm != 0xF) { + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (align)); + + // The fixed offset post-increment encodes Rm == 0xd. The no-writeback + // variant encodes Rm == 0xf. Anything else is a register offset post- + // increment and we need to add the register operand to the instruction. + if (Rm != 0xD && Rm != 0xF && + !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned align = fieldFromInstruction_4(Insn, 4, 1); + unsigned size = 1 << fieldFromInstruction_4(Insn, 6, 2); + align *= 2 * size; + + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD2DUPd16: + case ARM_VLD2DUPd32: + case ARM_VLD2DUPd8: + case ARM_VLD2DUPd16wb_fixed: + case ARM_VLD2DUPd16wb_register: + case ARM_VLD2DUPd32wb_fixed: + case ARM_VLD2DUPd32wb_register: + case ARM_VLD2DUPd8wb_fixed: + case ARM_VLD2DUPd8wb_register: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, + Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD2DUPd16x2: + case ARM_VLD2DUPd32x2: + case ARM_VLD2DUPd8x2: + case ARM_VLD2DUPd16x2wb_fixed: + case ARM_VLD2DUPd16x2wb_register: + case ARM_VLD2DUPd32x2wb_fixed: + case ARM_VLD2DUPd32x2wb_register: + case ARM_VLD2DUPd8x2wb_fixed: + case ARM_VLD2DUPd8x2wb_register: + if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, + Decoder))) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + } + + if (Rm != 0xF) + MCOperand_CreateImm0(Inst, (0)); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (align)); + + if (Rm != 0xD && Rm != 0xF) { + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned inc = fieldFromInstruction_4(Insn, 5, 1) + 1; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, + Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2 * inc) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + if (Rm != 0xF) { + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (0)); + + if (Rm == 0xD) + MCOperand_CreateReg0(Inst, (0)); + else if (Rm != 0xF) { + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + unsigned inc = fieldFromInstruction_4(Insn, 5, 1) + 1; + unsigned align = fieldFromInstruction_4(Insn, 4, 1); + + if (size == 0x3) { + if (align == 0) + return MCDisassembler_Fail; + align = 16; + } else { + if (size == 2) { + align *= 8; + } else { + size = 1 << size; + align *= 4 * size; + } + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, + Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2 * inc) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3 * inc) % 32, + Address, Decoder))) + return MCDisassembler_Fail; + if (Rm != 0xF) { + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (align)); + + if (Rm == 0xD) + MCOperand_CreateReg0(Inst, (0)); + else if (Rm != 0xF) { + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeVMOVModImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned imm = fieldFromInstruction_4(Insn, 0, 4); + imm |= fieldFromInstruction_4(Insn, 16, 3) << 4; + imm |= fieldFromInstruction_4(Insn, 24, 1) << 7; + imm |= fieldFromInstruction_4(Insn, 8, 4) << 8; + imm |= fieldFromInstruction_4(Insn, 5, 1) << 12; + unsigned Q = fieldFromInstruction_4(Insn, 6, 1); + + if (Q) { + if (!Check(&S, + DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + } else { + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + } + + MCOperand_CreateImm0(Inst, (imm)); + + switch (MCInst_getOpcode(Inst)) { + case ARM_VORRiv4i16: + case ARM_VORRiv2i32: + case ARM_VBICiv4i16: + case ARM_VBICiv2i32: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VORRiv8i16: + case ARM_VORRiv4i32: + case ARM_VBICiv8i16: + case ARM_VBICiv4i32: + if (!Check(&S, + DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + return S; +} + +static DecodeStatus DecodeMVEModImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) | + fieldFromInstruction_4(Insn, 13, 3)); + unsigned cmode = fieldFromInstruction_4(Insn, 8, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 4); + imm |= fieldFromInstruction_4(Insn, 16, 3) << 4; + imm |= fieldFromInstruction_4(Insn, 28, 1) << 7; + imm |= cmode << 8; + imm |= fieldFromInstruction_4(Insn, 5, 1) << 12; + + if (cmode == 0xF && MCInst_getOpcode(Inst) == ARM_MVE_VMVNimmi32) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, (imm)); + + MCOperand_CreateImm0(Inst, (ARMVCC_None)); + MCOperand_CreateReg0(Inst, (0)); + MCOperand_CreateImm0(Inst, (0)); + + return S; +} + +static DecodeStatus DecodeMVEVADCInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Qd = fieldFromInstruction_4(Insn, 13, 3); + Qd |= fieldFromInstruction_4(Insn, 22, 1) << 3; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, (ARM_FPSCR_NZCV)); + + unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); + Qn |= fieldFromInstruction_4(Insn, 7, 1) << 3; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) + return MCDisassembler_Fail; + unsigned Qm = fieldFromInstruction_4(Insn, 1, 3); + Qm |= fieldFromInstruction_4(Insn, 5, 1) << 3; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + return MCDisassembler_Fail; + if (!fieldFromInstruction_4(Insn, 12, + 1)) // I bit clear => need input FPSCR + MCOperand_CreateReg0(Inst, (ARM_FPSCR_NZCV)); + MCOperand_CreateImm0(Inst, (Qd)); + + return S; +} + +static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 18, 2); + + if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (8 << size)); + + return S; +} + +static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, (8 - Val)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, (16 - Val)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, (32 - Val)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, (64 - Val)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4; + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; + unsigned op = fieldFromInstruction_4(Insn, 6, 1); + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (op) { + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; // Writeback + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_VTBL2: + case ARM_VTBX2: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, + Decoder))) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned dst = fieldFromInstruction_2(Insn, 8, 3); + unsigned imm = fieldFromInstruction_2(Insn, 0, 8); + + if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) + return MCDisassembler_Fail; + + switch (MCInst_getOpcode(Inst)) { + default: + return MCDisassembler_Fail; + case ARM_tADR: + break; // tADR does not explicitly represent the PC as an operand. + case ARM_tADDrSPi: + MCOperand_CreateReg0(Inst, (ARM_SP)); + break; + } + + MCOperand_CreateImm0(Inst, (imm)); + return S; +} + +static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + if (!tryAddingSymbolicOperand( + Address, Address + SignExtend32((Val << 1), 12) + 4, true, + 2, Inst, Decoder)) + MCOperand_CreateImm0(Inst, (SignExtend32((Val << 1), 12))); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + if (!tryAddingSymbolicOperand(Address, + Address + SignExtend32((Val), 21) + 4, + true, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, (SignExtend32((Val), 21))); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + if (!tryAddingSymbolicOperand(Address, Address + (Val << 1) + 4, true, + 2, Inst, Decoder)) + MCOperand_CreateImm0(Inst, (Val << 1)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 0, 3); + unsigned Rm = fieldFromInstruction_4(Val, 3, 3); + + if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 0, 3); + unsigned imm = fieldFromInstruction_4(Val, 3, 5); + + if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (imm)); + + return S; +} + +static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + unsigned imm = Val << 2; + + MCOperand_CreateImm0(Inst, (imm)); + tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, + Decoder); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateReg0(Inst, (ARM_SP)); + MCOperand_CreateImm0(Inst, (Val)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 6, 4); + unsigned Rm = fieldFromInstruction_4(Val, 2, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 2); + + // Thumb stores cannot use PC as dest register. + switch (MCInst_getOpcode(Inst)) { + case ARM_t2STRHs: + case ARM_t2STRBs: + case ARM_t2STRs: + if (Rn == 15) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (imm)); + + return S; +} + +static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + + bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); + bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRBs: + MCInst_setOpcode(Inst, (ARM_t2LDRBpci)); + break; + case ARM_t2LDRHs: + MCInst_setOpcode(Inst, (ARM_t2LDRHpci)); + break; + case ARM_t2LDRSHs: + MCInst_setOpcode(Inst, (ARM_t2LDRSHpci)); + break; + case ARM_t2LDRSBs: + MCInst_setOpcode(Inst, (ARM_t2LDRSBpci)); + break; + case ARM_t2LDRs: + MCInst_setOpcode(Inst, (ARM_t2LDRpci)); + break; + case ARM_t2PLDs: + MCInst_setOpcode(Inst, (ARM_t2PLDpci)); + break; + case ARM_t2PLIs: + MCInst_setOpcode(Inst, (ARM_t2PLIpci)); + break; + default: + return MCDisassembler_Fail; + } + + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (Rt == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRSHs: + return MCDisassembler_Fail; + case ARM_t2LDRHs: + MCInst_setOpcode(Inst, (ARM_t2PLDWs)); + break; + case ARM_t2LDRSBs: + MCInst_setOpcode(Inst, (ARM_t2PLIs)); + break; + default: + break; + } + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2PLDs: + break; + case ARM_t2PLIs: + if (!hasV7Ops) + return MCDisassembler_Fail; + break; + case ARM_t2PLDWs: + if (!hasV7Ops || !hasMP) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + } + + unsigned addrmode = fieldFromInstruction_4(Insn, 4, 2); + addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2; + addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6; + if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned U = fieldFromInstruction_4(Insn, 9, 1); + unsigned imm = fieldFromInstruction_4(Insn, 0, 8); + imm |= (U << 8); + imm |= (Rn << 9); + unsigned add = fieldFromInstruction_4(Insn, 9, 1); + + bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); + bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRi8: + MCInst_setOpcode(Inst, (ARM_t2LDRpci)); + break; + case ARM_t2LDRBi8: + MCInst_setOpcode(Inst, (ARM_t2LDRBpci)); + break; + case ARM_t2LDRSBi8: + MCInst_setOpcode(Inst, (ARM_t2LDRSBpci)); + break; + case ARM_t2LDRHi8: + MCInst_setOpcode(Inst, (ARM_t2LDRHpci)); + break; + case ARM_t2LDRSHi8: + MCInst_setOpcode(Inst, (ARM_t2LDRSHpci)); + break; + case ARM_t2PLDi8: + MCInst_setOpcode(Inst, (ARM_t2PLDpci)); + break; + case ARM_t2PLIi8: + MCInst_setOpcode(Inst, (ARM_t2PLIpci)); + break; + default: + return MCDisassembler_Fail; + } + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (Rt == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRSHi8: + return MCDisassembler_Fail; + case ARM_t2LDRHi8: + if (!add) + MCInst_setOpcode(Inst, (ARM_t2PLDWi8)); + break; + case ARM_t2LDRSBi8: + MCInst_setOpcode(Inst, (ARM_t2PLIi8)); + break; + default: + break; + } + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2PLDi8: + break; + case ARM_t2PLIi8: + if (!hasV7Ops) + return MCDisassembler_Fail; + break; + case ARM_t2PLDWi8: + if (!hasV7Ops || !hasMP) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + return S; +} + +static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= (Rn << 13); + + bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); + bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRi12: + MCInst_setOpcode(Inst, (ARM_t2LDRpci)); + break; + case ARM_t2LDRHi12: + MCInst_setOpcode(Inst, (ARM_t2LDRHpci)); + break; + case ARM_t2LDRSHi12: + MCInst_setOpcode(Inst, (ARM_t2LDRSHpci)); + break; + case ARM_t2LDRBi12: + MCInst_setOpcode(Inst, (ARM_t2LDRBpci)); + break; + case ARM_t2LDRSBi12: + MCInst_setOpcode(Inst, (ARM_t2LDRSBpci)); + break; + case ARM_t2PLDi12: + MCInst_setOpcode(Inst, (ARM_t2PLDpci)); + break; + case ARM_t2PLIi12: + MCInst_setOpcode(Inst, (ARM_t2PLIpci)); + break; + default: + return MCDisassembler_Fail; + } + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (Rt == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRSHi12: + return MCDisassembler_Fail; + case ARM_t2LDRHi12: + MCInst_setOpcode(Inst, (ARM_t2PLDWi12)); + break; + case ARM_t2LDRSBi12: + MCInst_setOpcode(Inst, (ARM_t2PLIi12)); + break; + default: + break; + } + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2PLDi12: + break; + case ARM_t2PLIi12: + if (!hasV7Ops) + return MCDisassembler_Fail; + break; + case ARM_t2PLDWi12: + if (!hasV7Ops || !hasMP) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + return S; +} + +static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 8); + imm |= (Rn << 9); + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRT: + MCInst_setOpcode(Inst, (ARM_t2LDRpci)); + break; + case ARM_t2LDRBT: + MCInst_setOpcode(Inst, (ARM_t2LDRBpci)); + break; + case ARM_t2LDRHT: + MCInst_setOpcode(Inst, (ARM_t2LDRHpci)); + break; + case ARM_t2LDRSBT: + MCInst_setOpcode(Inst, (ARM_t2LDRSBpci)); + break; + case ARM_t2LDRSHT: + MCInst_setOpcode(Inst, (ARM_t2LDRSHpci)); + break; + default: + return MCDisassembler_Fail; + } + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + return S; +} + +static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned U = fieldFromInstruction_4(Insn, 23, 1); + int imm = fieldFromInstruction_4(Insn, 0, 12); + + bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); + + if (Rt == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRBpci: + case ARM_t2LDRHpci: + MCInst_setOpcode(Inst, (ARM_t2PLDpci)); + break; + case ARM_t2LDRSBpci: + MCInst_setOpcode(Inst, (ARM_t2PLIpci)); + break; + case ARM_t2LDRSHpci: + return MCDisassembler_Fail; + default: + break; + } + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2PLDpci: + break; + case ARM_t2PLIpci: + if (!hasV7Ops) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!U) { + // Special case for #-0. + if (imm == 0) + imm = INT32_MIN; + else + imm = -imm; + } + MCOperand_CreateImm0(Inst, (imm)); + + return S; +} + +static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder) +{ + if (Val == 0) + MCOperand_CreateImm0(Inst, (INT32_MIN)); + else { + int imm = Val & 0xFF; + + if (!(Val & 0x100)) + imm *= -1; + MCOperand_CreateImm0(Inst, (imm * 4)); + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2Imm7S4(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder) +{ + if (Val == 0) + MCOperand_CreateImm0(Inst, (INT32_MIN)); + else { + int imm = Val & 0x7F; + + if (!(Val & 0x80)) + imm *= -1; + MCOperand_CreateImm0(Inst, (imm * 4)); + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 9, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 9); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2AddrModeImm7s4(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 8, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 8, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, (imm)); + + return S; +} + +static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder) +{ + int imm = Val & 0xFF; + if (Val == 0) + imm = INT32_MIN; + else if (!(Val & 0x100)) + imm *= -1; + MCOperand_CreateImm0(Inst, (imm)); + + return MCDisassembler_Success; +} + +#define DEFINE_DecodeT2Imm7(shift) \ + static DecodeStatus CONCAT(DecodeT2Imm7, shift)(MCInst * Inst, \ + unsigned Val, \ + uint64_t Address, \ + const void *Decoder) \ + { \ + int imm = Val & 0x7F; \ + if (Val == 0) \ + imm = INT32_MIN; \ + else if (!(Val & 0x80)) \ + imm *= -1; \ + if (imm != INT32_MIN) \ + imm *= (1U << shift); \ + MCOperand_CreateImm0(Inst, (imm)); \ +\ + return MCDisassembler_Success; \ + } +DEFINE_DecodeT2Imm7(0) DEFINE_DecodeT2Imm7(1) DEFINE_DecodeT2Imm7(2) + + static DecodeStatus + DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 9, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 9); + + // Thumb stores cannot use PC as dest register. + switch (MCInst_getOpcode(Inst)) { + case ARM_t2STRT: + case ARM_t2STRBT: + case ARM_t2STRHT: + case ARM_t2STRi8: + case ARM_t2STRHi8: + case ARM_t2STRBi8: + if (Rn == 15) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Some instructions always use an additive offset. + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRT: + case ARM_t2LDRBT: + case ARM_t2LDRHT: + case ARM_t2LDRSBT: + case ARM_t2LDRSHT: + case ARM_t2STRT: + case ARM_t2STRBT: + case ARM_t2STRHT: + imm |= 0x100; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +#define DEFINE_DecodeTAddrModeImm7(shift) \ + static DecodeStatus CONCAT(DecodeTAddrModeImm7, shift)( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder) \ + { \ + DecodeStatus S = MCDisassembler_Success; \ +\ + unsigned Rn = fieldFromInstruction_4(Val, 8, 3); \ + unsigned imm = fieldFromInstruction_4(Val, 0, 8); \ +\ + if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, \ + Decoder))) \ + return MCDisassembler_Fail; \ + if (!Check(&S, CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, \ + Decoder))) \ + return MCDisassembler_Fail; \ +\ + return S; \ + } +DEFINE_DecodeTAddrModeImm7(0) DEFINE_DecodeTAddrModeImm7(1) + +#define DEFINE_DecodeT2AddrModeImm7(shift, WriteBack) \ + static DecodeStatus CONCAT(DecodeT2AddrModeImm7, \ + CONCAT(shift, WriteBack))( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder) \ + { \ + DecodeStatus S = MCDisassembler_Success; \ +\ + unsigned Rn = fieldFromInstruction_4(Val, 8, 4); \ + unsigned imm = fieldFromInstruction_4(Val, 0, 8); \ + if (WriteBack) { \ + if (!Check(&S, DecoderGPRRegisterClass( \ + Inst, Rn, Address, Decoder))) \ + return MCDisassembler_Fail; \ + } else if (!Check(&S, DecodeGPRnopcRegisterClass( \ + Inst, Rn, Address, Decoder))) \ + return MCDisassembler_Fail; \ + if (!Check(&S, CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, \ + Decoder))) \ + return MCDisassembler_Fail; \ +\ + return S; \ + } + DEFINE_DecodeT2AddrModeImm7(0, 0) DEFINE_DecodeT2AddrModeImm7(1, 0) + DEFINE_DecodeT2AddrModeImm7(2, 0) + DEFINE_DecodeT2AddrModeImm7(0, 1) + DEFINE_DecodeT2AddrModeImm7(1, 1) + DEFINE_DecodeT2AddrModeImm7(2, 1) + + static DecodeStatus + DecodeT2LdStPre(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned addr = fieldFromInstruction_4(Insn, 0, 8); + addr |= fieldFromInstruction_4(Insn, 9, 1) << 8; + addr |= Rn << 9; + unsigned load = fieldFromInstruction_4(Insn, 20, 1); + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDR_PRE: + case ARM_t2LDR_POST: + MCInst_setOpcode(Inst, (ARM_t2LDRpci)); + break; + case ARM_t2LDRB_PRE: + case ARM_t2LDRB_POST: + MCInst_setOpcode(Inst, (ARM_t2LDRBpci)); + break; + case ARM_t2LDRH_PRE: + case ARM_t2LDRH_POST: + MCInst_setOpcode(Inst, (ARM_t2LDRHpci)); + break; + case ARM_t2LDRSB_PRE: + case ARM_t2LDRSB_POST: + if (Rt == 15) + MCInst_setOpcode(Inst, (ARM_t2PLIpci)); + else + MCInst_setOpcode(Inst, (ARM_t2LDRSBpci)); + break; + case ARM_t2LDRSH_PRE: + case ARM_t2LDRSH_POST: + MCInst_setOpcode(Inst, (ARM_t2LDRSHpci)); + break; + default: + return MCDisassembler_Fail; + } + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (!load) { + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (load) { + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 13, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 12); + + // Thumb stores cannot use PC as dest register. + switch (MCInst_getOpcode(Inst)) { + case ARM_t2STRi12: + case ARM_t2STRBi12: + case ARM_t2STRHi12: + if (Rn == 15) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (imm)); + + return S; +} + +static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn, + uint64_t Address, const void *Decoder) +{ + unsigned imm = fieldFromInstruction_2(Insn, 0, 7); + + MCOperand_CreateReg0(Inst, (ARM_SP)); + MCOperand_CreateReg0(Inst, (ARM_SP)); + MCOperand_CreateImm0(Inst, (imm)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if (MCInst_getOpcode(Inst) == ARM_tADDrSP) { + unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3); + Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3; + + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, (ARM_SP)); + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) + return MCDisassembler_Fail; + } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) { + unsigned Rm = fieldFromInstruction_2(Insn, 3, 4); + + MCOperand_CreateReg0(Inst, (ARM_SP)); + MCOperand_CreateReg0(Inst, (ARM_SP)); + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, + uint64_t Address, const void *Decoder) +{ + unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2; + unsigned flags = fieldFromInstruction_2(Insn, 0, 3); + + MCOperand_CreateImm0(Inst, (imod)); + MCOperand_CreateImm0(Inst, (flags)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned add = fieldFromInstruction_4(Insn, 4, 1); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (add)); + + return S; +} + +static DecodeStatus DecodeMveAddrModeRQ(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Insn, 3, 4); + unsigned Qm = fieldFromInstruction_4(Insn, 0, 3); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +#define DEFINE_DecodeMveAddrModeQ(shift) \ + static DecodeStatus CONCAT(DecodeMveAddrModeQ, shift)( \ + MCInst * Inst, unsigned Insn, uint64_t Address, \ + const void *Decoder) \ + { \ + DecodeStatus S = MCDisassembler_Success; \ + unsigned Qm = fieldFromInstruction_4(Insn, 8, 3); \ + int imm = fieldFromInstruction_4(Insn, 0, 7); \ +\ + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, \ + Decoder))) \ + return MCDisassembler_Fail; \ +\ + if (!fieldFromInstruction_4(Insn, 7, 1)) { \ + if (imm == 0) \ + imm = INT32_MIN; \ + else \ + imm *= -1; \ + } \ + if (imm != INT32_MIN) \ + imm *= (1U << shift); \ + MCOperand_CreateImm0(Inst, (imm)); \ +\ + return S; \ + } +DEFINE_DecodeMveAddrModeQ(2) DEFINE_DecodeMveAddrModeQ(3) + + static DecodeStatus + DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder) +{ + // Val is passed in as S:J1:J2:imm10H:imm10L:'0' + // Note only one trailing zero not two. Also the J1 and J2 values are from + // the encoded instruction. So here change to I1 and I2 values via: + // I1 = NOT(J1 EOR S); + // I2 = NOT(J2 EOR S); + // and build the imm32 with two trailing zeros as documented: + // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); + unsigned S = (Val >> 23) & 1; + unsigned J1 = (Val >> 22) & 1; + unsigned J2 = (Val >> 21) & 1; + unsigned I1 = !(J1 ^ S); + unsigned I2 = !(J2 ^ S); + unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); + int imm32 = SignExtend32((tmp << 1), 25); + + if (!tryAddingSymbolicOperand(Address, (Address & ~2u) + imm32 + 4, + true, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, (imm32)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + if (Val == 0xA || Val == 0xB) + return MCDisassembler_Fail; + + if (!isValidCoprocessorNumber(Inst, Val)) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, (Val)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + + if (Rn == 13 && !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) + S = MCDisassembler_SoftFail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + return S; +} + +static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned pred = fieldFromInstruction_4(Insn, 22, 4); + if (pred == 0xE || pred == 0xF) { + unsigned opc = fieldFromInstruction_4(Insn, 4, 28); + switch (opc) { + default: + return MCDisassembler_Fail; + case 0xf3bf8f4: + MCInst_setOpcode(Inst, (ARM_t2DSB)); + break; + case 0xf3bf8f5: + MCInst_setOpcode(Inst, (ARM_t2DMB)); + break; + case 0xf3bf8f6: + MCInst_setOpcode(Inst, (ARM_t2ISB)); + break; + } + + unsigned imm = fieldFromInstruction_4(Insn, 0, 4); + return DecodeMemBarrierOption(Inst, imm, Address, Decoder); + } + + unsigned brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1; + brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19; + brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18; + brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12; + brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20; + + if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +// Decode a shifted immediate operand. These basically consist +// of an 8-bit value, and a 4-bit directive that specifies either +// a splat operation or a rotation. +static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder) +{ + unsigned ctrl = fieldFromInstruction_4(Val, 10, 2); + if (ctrl == 0) { + unsigned byte = fieldFromInstruction_4(Val, 8, 2); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + switch (byte) { + case 0: + MCOperand_CreateImm0(Inst, (imm)); + break; + case 1: + MCOperand_CreateImm0(Inst, ((imm << 16) | imm)); + break; + case 2: + MCOperand_CreateImm0(Inst, ((imm << 24) | (imm << 8))); + break; + case 3: + MCOperand_CreateImm0(Inst, ((imm << 24) | (imm << 16) | + (imm << 8) | imm)); + break; + } + } else { + unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80; + unsigned rot = fieldFromInstruction_4(Val, 7, 5); + unsigned imm = (unrot >> rot) | (unrot << ((32 - rot) & 31)); + MCOperand_CreateImm0(Inst, (imm)); + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + if (!tryAddingSymbolicOperand(Address, + Address + SignExtend32((Val << 1), 9) + 4, + true, 2, Inst, Decoder)) + MCOperand_CreateImm0(Inst, (SignExtend32((Val << 1), 9))); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + // Val is passed in as S:J1:J2:imm10:imm11 + // Note no trailing zero after imm11. Also the J1 and J2 values are from + // the encoded instruction. So here change to I1 and I2 values via: + // I1 = NOT(J1 EOR S); + // I2 = NOT(J2 EOR S); + // and build the imm32 with one trailing zero as documented: + // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); + unsigned S = (Val >> 23) & 1; + unsigned J1 = (Val >> 22) & 1; + unsigned J2 = (Val >> 21) & 1; + unsigned I1 = !(J1 ^ S); + unsigned I2 = !(J2 ^ S); + unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); + int imm32 = SignExtend32((tmp << 1), 25); + + if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, true, 4, + Inst, Decoder)) + MCOperand_CreateImm0(Inst, (imm32)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + if (Val & ~0xf) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, (Val)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + if (Val & ~0xf) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, (Val)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass)) { + unsigned ValLow = Val & 0xff; + + // Validate the SYSm value first. + switch (ValLow) { + case 0: // apsr + case 1: // iapsr + case 2: // eapsr + case 3: // xpsr + case 5: // ipsr + case 6: // epsr + case 7: // iepsr + case 8: // msp + case 9: // psp + case 16: // primask + case 20: // control + break; + case 17: // basepri + case 18: // basepri_max + case 19: // faultmask + if (!(ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV7Ops))) + // Values basepri, basepri_max and faultmask are only valid for + // v7m. + return MCDisassembler_Fail; + break; + case 0x8a: // msplim_ns + case 0x8b: // psplim_ns + case 0x91: // basepri_ns + case 0x93: // faultmask_ns + if (!(ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV8MMainlineOps))) + return MCDisassembler_Fail; + // fall through + case 10: // msplim + case 11: // psplim + case 0x88: // msp_ns + case 0x89: // psp_ns + case 0x90: // primask_ns + case 0x94: // control_ns + case 0x98: // sp_ns + if (!(ARM_getFeatureBits(Inst->csh->mode, + ARM_Feature8MSecExt))) + return MCDisassembler_Fail; + break; + case 0x20: // pac_key_p_0 + case 0x21: // pac_key_p_1 + case 0x22: // pac_key_p_2 + case 0x23: // pac_key_p_3 + case 0x24: // pac_key_u_0 + case 0x25: // pac_key_u_1 + case 0x26: // pac_key_u_2 + case 0x27: // pac_key_u_3 + case 0xa0: // pac_key_p_0_ns + case 0xa1: // pac_key_p_1_ns + case 0xa2: // pac_key_p_2_ns + case 0xa3: // pac_key_p_3_ns + case 0xa4: // pac_key_u_0_ns + case 0xa5: // pac_key_u_1_ns + case 0xa6: // pac_key_u_2_ns + case 0xa7: // pac_key_u_3_ns + if (!(ARM_getFeatureBits(Inst->csh->mode, + ARM_FeaturePACBTI))) + return MCDisassembler_Fail; + break; + default: + // Architecturally defined as unpredictable + S = MCDisassembler_SoftFail; + break; + } + + if (MCInst_getOpcode(Inst) == ARM_t2MSR_M) { + unsigned Mask = fieldFromInstruction_4(Val, 10, 2); + if (!(ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV7Ops))) { + // The ARMv6-M MSR bits {11-10} can be only 0b10, other values + // are unpredictable. + if (Mask != 2) + S = MCDisassembler_SoftFail; + } else { + // The ARMv7-M architecture stores an additional 2-bit mask + // value in MSR bits {11-10}. The mask is used only with apsr, + // iapsr, eapsr and xpsr, it has to be 0b10 in other cases. Bit + // mask{1} indicates if the NZCVQ bits should be moved by the + // instruction. Bit mask{0} indicates the move for the GE{3:0} + // bits, the mask{0} bit can be set only if the processor + // includes the DSP extension. + if (Mask == 0 || (Mask != 2 && ValLow > 3) || + (!(ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureDSP)) && + (Mask & 1))) + S = MCDisassembler_SoftFail; + } + } + } else { + // A/R class + if (Val == 0) + return MCDisassembler_Fail; + } + MCOperand_CreateImm0(Inst, (Val)); + return S; +} + +static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + unsigned R = fieldFromInstruction_4(Val, 5, 1); + unsigned SysM = fieldFromInstruction_4(Val, 0, 5); + + // The table of encodings for these banked registers comes from B9.2.3 of + // the ARM ARM. There are patterns, but nothing regular enough to make this + // logic neater. So by fiat, these values are UNPREDICTABLE: + if (!ARMBankedReg_lookupBankedRegByEncoding((R << 5) | SysM)) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, (Val)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (Rn == 0xF) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt + 1) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; + imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (Rn == 0xF || Rn == Rt) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; + imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + + if (Rn == 0xF || Rn == Rt) + S = MCDisassembler_SoftFail; + if (Rm == 0xF) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; + imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (Rn == 0xF || Rn == Rt) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; + imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (Rn == 0xF || Rn == Rt) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 5, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 6, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + + switch (fieldFromInstruction_4(Insn, 4, 2)) { + case 0: + align = 0; + break; + case 3: + align = 4; + break; + default: + return MCDisassembler_Fail; + } + break; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (Rm != 0xF) { // Writeback + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, + Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, (0)); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (index)); + + return S; +} + +static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 5, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 6, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + + switch (fieldFromInstruction_4(Insn, 4, 2)) { + case 0: + align = 0; + break; + case 3: + align = 4; + break; + default: + return MCDisassembler_Fail; + } + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, + Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, (0)); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (index)); + + return S; +} + +static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + index = fieldFromInstruction_4(Insn, 5, 3); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 2; + break; + case 1: + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 4; + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 5, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 4, 1) != 0) + align = 8; + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (Rm != 0xF) { // Writeback + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, + Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, (0)); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (index)); + + return S; +} + +static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + index = fieldFromInstruction_4(Insn, 5, 3); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 2; + break; + case 1: + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 4; + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 5, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 4, 1) != 0) + align = 8; + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, + Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, (0)); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (index)); + + return S; +} + +static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 4, 2)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, + Decoder))) + return MCDisassembler_Fail; + + if (Rm != 0xF) { // Writeback + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, + Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, (0)); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, + Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (index)); + + return S; +} + +static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 4, 2)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, + Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, (0)); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, + Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (index)); + + return S; +} + +static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 4; + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 8; + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + switch (fieldFromInstruction_4(Insn, 4, 2)) { + case 0: + align = 0; + break; + case 3: + return MCDisassembler_Fail; + default: + align = 4 << fieldFromInstruction_4(Insn, 4, 2); + break; + } + + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, + Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, + Decoder))) + return MCDisassembler_Fail; + + if (Rm != 0xF) { // Writeback + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, + Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, (0)); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, + Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, + Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (index)); + + return S; +} + +static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 4; + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 8; + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + switch (fieldFromInstruction_4(Insn, 4, 2)) { + case 0: + align = 0; + break; + case 3: + return MCDisassembler_Fail; + default: + align = 4 << fieldFromInstruction_4(Insn, 4, 2); + break; + } + + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(&S, + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, + Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, (0)); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, + Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, + Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (index)); + + return S; +} + +static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; + + if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; + + if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned pred = fieldFromInstruction_4(Insn, 4, 4); + unsigned mask = fieldFromInstruction_4(Insn, 0, 4); + + if (pred == 0xF) { + pred = 0xE; + S = MCDisassembler_SoftFail; + } + + if (mask == 0x0) + return MCDisassembler_Fail; + + // IT masks are encoded as a sequence of replacement low-order bits + // for the condition code. So if the low bit of the starting + // condition code is 1, then we have to flip all the bits above the + // terminating bit (which is the lowest 1 bit). + if (pred & 1) { + unsigned LowBit = mask & -mask; + unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); + mask ^= BitsAboveLowBit; + } + + MCOperand_CreateImm0(Inst, (pred)); + MCOperand_CreateImm0(Inst, (mask)); + return S; +} + +static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned addr = fieldFromInstruction_4(Insn, 0, 8); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + unsigned U = fieldFromInstruction_4(Insn, 23, 1); + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + bool writeback = (W == 1) | (P == 0); + + addr |= (U << 8) | (Rn << 9); + + if (writeback && (Rn == Rt || Rn == Rt2)) + Check(&S, MCDisassembler_SoftFail); + if (Rt == Rt2) + Check(&S, MCDisassembler_SoftFail); + + // Rt + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + // Rt2 + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + // Writeback operand + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + // addr + if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned addr = fieldFromInstruction_4(Insn, 0, 8); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + unsigned U = fieldFromInstruction_4(Insn, 23, 1); + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + bool writeback = (W == 1) | (P == 0); + + addr |= (U << 8) | (Rn << 9); + + if (writeback && (Rn == Rt || Rn == Rt2)) + Check(&S, MCDisassembler_SoftFail); + + // Writeback operand + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + // Rt + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + // Rt2 + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + // addr + if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1); + unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1); + if (sign1 != sign2) + return MCDisassembler_Fail; + const unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); + + DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); + + unsigned Val = fieldFromInstruction_4(Insn, 0, 8); + Val |= fieldFromInstruction_4(Insn, 12, 3) << 8; + Val |= fieldFromInstruction_4(Insn, 26, 1) << 11; + // If sign, then it is decreasing the address. + if (sign1) { + // Following ARMv7 Architecture Manual, when the offset + // is zero, it is decoded as a subw, not as a adr.w + if (!Val) { + MCInst_setOpcode(Inst, (ARM_t2SUBri12)); + MCOperand_CreateReg0(Inst, (ARM_PC)); + } else + Val = -Val; + } + MCOperand_CreateImm0(Inst, (Val)); + return S; +} + +static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + // Shift of "asr #32" is not allowed in Thumb2 mode. + if (Val == 0x20) + S = MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (Val)); + return S; +} + +static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (pred == 0xF) + return DecodeCPSInstruction(Inst, Insn, Address, Decoder); + + DecodeStatus S = MCDisassembler_Success; + + if (Rt == Rn || Rn == Rt2) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + bool hasFullFP16 = + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16); + + unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); + Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); + unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); + Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); + unsigned imm = fieldFromInstruction_4(Insn, 16, 6); + unsigned cmode = fieldFromInstruction_4(Insn, 8, 4); + unsigned op = fieldFromInstruction_4(Insn, 5, 1); + + DecodeStatus S = MCDisassembler_Success; + + // If the top 3 bits of imm are clear, this is a VMOV (immediate) + if (!(imm & 0x38)) { + if (cmode == 0xF) { + if (op == 1) + return MCDisassembler_Fail; + MCInst_setOpcode(Inst, (ARM_VMOVv2f32)); + } + if (hasFullFP16) { + if (cmode == 0xE) { + if (op == 1) { + MCInst_setOpcode(Inst, (ARM_VMOVv1i64)); + } else { + MCInst_setOpcode(Inst, (ARM_VMOVv8i8)); + } + } + if (cmode == 0xD) { + if (op == 1) { + MCInst_setOpcode(Inst, (ARM_VMVNv2i32)); + } else { + MCInst_setOpcode(Inst, (ARM_VMOVv2i32)); + } + } + if (cmode == 0xC) { + if (op == 1) { + MCInst_setOpcode(Inst, (ARM_VMVNv2i32)); + } else { + MCInst_setOpcode(Inst, (ARM_VMOVv2i32)); + } + } + } + return DecodeVMOVModImmInstruction(Inst, Insn, Address, + Decoder); + } + + if (!(imm & 0x20)) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (64 - imm)); + + return S; +} + +static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + bool hasFullFP16 = + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16); + + unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); + Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); + unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); + Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); + unsigned imm = fieldFromInstruction_4(Insn, 16, 6); + unsigned cmode = fieldFromInstruction_4(Insn, 8, 4); + unsigned op = fieldFromInstruction_4(Insn, 5, 1); + + DecodeStatus S = MCDisassembler_Success; + + // If the top 3 bits of imm are clear, this is a VMOV (immediate) + if (!(imm & 0x38)) { + if (cmode == 0xF) { + if (op == 1) + return MCDisassembler_Fail; + MCInst_setOpcode(Inst, (ARM_VMOVv4f32)); + } + if (hasFullFP16) { + if (cmode == 0xE) { + if (op == 1) { + MCInst_setOpcode(Inst, (ARM_VMOVv2i64)); + } else { + MCInst_setOpcode(Inst, (ARM_VMOVv16i8)); + } + } + if (cmode == 0xD) { + if (op == 1) { + MCInst_setOpcode(Inst, (ARM_VMVNv4i32)); + } else { + MCInst_setOpcode(Inst, (ARM_VMOVv4i32)); + } + } + if (cmode == 0xC) { + if (op == 1) { + MCInst_setOpcode(Inst, (ARM_VMVNv4i32)); + } else { + MCInst_setOpcode(Inst, (ARM_VMOVv4i32)); + } + } + } + return DecodeVMOVModImmInstruction(Inst, Insn, Address, + Decoder); + } + + if (!(imm & 0x20)) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (64 - imm)); + + return S; +} + +static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); + Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); + unsigned Vn = (fieldFromInstruction_4(Insn, 16, 4) << 0); + Vn |= (fieldFromInstruction_4(Insn, 7, 1) << 4); + unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); + Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); + unsigned q = (fieldFromInstruction_4(Insn, 6, 1) << 0); + unsigned rotate = (fieldFromInstruction_4(Insn, 20, 2) << 0); + + DecodeStatus S = MCDisassembler_Success; + + typedef DecodeStatus (*DecoderFunction)(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + + DecoderFunction DestRegDecoder = q ? DecodeQPRRegisterClass : + DecodeDPRRegisterClass; + + if (!Check(&S, DestRegDecoder(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DestRegDecoder(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DestRegDecoder(Inst, Vn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) + return MCDisassembler_Fail; + // The lane index does not have any bits in the encoding, because it can + // only be 0. + MCOperand_CreateImm0(Inst, (0)); + MCOperand_CreateImm0(Inst, (rotate)); + + return S; +} + +static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 16, 4); + unsigned Rt = fieldFromInstruction_4(Val, 12, 4); + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4); + unsigned Cond = fieldFromInstruction_4(Val, 28, 4); + + if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned CRm = fieldFromInstruction_4(Val, 0, 4); + unsigned opc1 = fieldFromInstruction_4(Val, 4, 4); + unsigned cop = fieldFromInstruction_4(Val, 8, 4); + unsigned Rt = fieldFromInstruction_4(Val, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4); + + if ((cop & ~0x1) == 0xa) + return MCDisassembler_Fail; + + if (Rt == Rt2) + S = MCDisassembler_SoftFail; + + // We have to check if the instruction is MRRC2 + // or MCRR2 when constructing the operands for + // Inst. Reason is because MRRC2 stores to two + // registers so its tablegen desc has two + // outputs whereas MCRR doesn't store to any + // registers so all of its operands are listed + // as inputs, therefore the operand order for + // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] + // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] + + if (MCInst_getOpcode(Inst) == ARM_MRRC2) { + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, + Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, + Decoder))) + return MCDisassembler_Fail; + } + MCOperand_CreateImm0(Inst, (cop)); + MCOperand_CreateImm0(Inst, (opc1)); + if (MCInst_getOpcode(Inst) == ARM_MCRR2) { + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, + Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, + Decoder))) + return MCDisassembler_Fail; + } + MCOperand_CreateImm0(Inst, (CRm)); + + return S; +} + +static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + // Add explicit operand for the destination sysreg, for cases where + // we have to model it for code generation purposes. + switch (MCInst_getOpcode(Inst)) { + case ARM_VMSR_FPSCR_NZCVQC: + MCOperand_CreateReg0(Inst, (ARM_FPSCR_NZCV)); + break; + case ARM_VMSR_P0: + MCOperand_CreateReg0(Inst, (ARM_VPR)); + break; + } + + if (MCInst_getOpcode(Inst) != ARM_FMSTAT) { + unsigned Rt = fieldFromInstruction_4(Val, 12, 4); + + if (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) { + if (Rt == 13 || Rt == 15) + S = MCDisassembler_SoftFail; + Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, + Decoder)); + } else + Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, + Decoder)); + } + + // Add explicit operand for the source sysreg, similarly to above. + switch (MCInst_getOpcode(Inst)) { + case ARM_VMRS_FPSCR_NZCVQC: + MCOperand_CreateReg0(Inst, (ARM_FPSCR_NZCV)); + break; + case ARM_VMRS_P0: + MCOperand_CreateReg0(Inst, (ARM_VPR)); + break; + } + + if (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb)) { + MCOperand_CreateImm0(Inst, (ARMCC_AL)); + MCOperand_CreateReg0(Inst, (0)); + } else { + unsigned pred = fieldFromInstruction_4(Val, 28, 4); + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, + Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +#define DEFINE_DecodeBFLabelOperand(isSigned, isNeg, zeroPermitted, size) \ + static DecodeStatus CONCAT( \ + DecodeBFLabelOperand, \ + CONCAT(isSigned, CONCAT(isNeg, CONCAT(zeroPermitted, size))))( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder) \ + { \ + DecodeStatus S = MCDisassembler_Success; \ + if (Val == 0 && !zeroPermitted) \ + S = MCDisassembler_Fail; \ +\ + uint64_t DecVal; \ + if (isSigned) \ + DecVal = SignExtend32((Val << 1), size + 1); \ + else \ + DecVal = (Val << 1); \ +\ + if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, \ + true, 4, Inst, Decoder)) \ + MCOperand_CreateImm0(Inst, \ + (isNeg ? -DecVal : DecVal)); \ + return S; \ + } +DEFINE_DecodeBFLabelOperand(false, false, false, 4) + DEFINE_DecodeBFLabelOperand(true, false, true, + 18) DEFINE_DecodeBFLabelOperand(true, false, + true, 12) + DEFINE_DecodeBFLabelOperand(true, false, true, 16) + DEFINE_DecodeBFLabelOperand(false, true, true, 11) + DEFINE_DecodeBFLabelOperand(false, false, true, + 11) + + static DecodeStatus + DecodeBFAfterTargetOperand(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder) +{ + uint64_t LocImm = MCOperand_getImm(MCInst_getOperand(Inst, (0))); + Val = LocImm + (2 << Val); + if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, + Decoder)) + MCOperand_CreateImm0(Inst, (Val)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodePredNoALOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + if (Val >= ARMCC_AL) // also exclude the non-condition NV + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (Val)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLOLoop(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if (MCInst_getOpcode(Inst) == ARM_MVE_LCTP) + return S; + + unsigned Imm = fieldFromInstruction_4(Insn, 11, 1) | + fieldFromInstruction_4(Insn, 1, 10) << 1; + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LEUpdate: + case ARM_MVE_LETP: + MCOperand_CreateReg0(Inst, (ARM_LR)); + MCOperand_CreateReg0(Inst, (ARM_LR)); + // fall through + case ARM_t2LE: + if (!Check(&S, CONCAT(DecodeBFLabelOperand, + CONCAT(false, + CONCAT(true, CONCAT(true, 11))))( + Inst, Imm, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_t2WLS: + case ARM_MVE_WLSTP_8: + case ARM_MVE_WLSTP_16: + case ARM_MVE_WLSTP_32: + case ARM_MVE_WLSTP_64: + MCOperand_CreateReg0(Inst, (ARM_LR)); + if (!Check(&S, + DecoderGPRRegisterClass( + Inst, fieldFromInstruction_4(Insn, 16, 4), + Address, Decoder)) || + !Check(&S, CONCAT(DecodeBFLabelOperand, + CONCAT(false, + CONCAT(false, CONCAT(true, 11))))( + Inst, Imm, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_t2DLS: + case ARM_MVE_DLSTP_8: + case ARM_MVE_DLSTP_16: + case ARM_MVE_DLSTP_32: + case ARM_MVE_DLSTP_64: { + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + if (Rn == 0xF) { + // Enforce all the rest of the instruction bits in LCTP, which + // won't have been reliably checked based on LCTP's own tablegen + // record, because we came to this decode by a roundabout route. + uint32_t CanonicalLCTP = 0xF00FE001, + SBZMask = 0x00300FFE; + if ((Insn & ~SBZMask) != CanonicalLCTP) + return MCDisassembler_Fail; // a mandatory bit is wrong: hard + // fail + if (Insn != CanonicalLCTP) + Check(&S, + MCDisassembler_SoftFail); // an SBZ bit is wrong: soft fail + + MCInst_setOpcode(Inst, (ARM_MVE_LCTP)); + } else { + MCOperand_CreateReg0(Inst, (ARM_LR)); + if (!Check(&S, + DecoderGPRRegisterClass( + Inst, + fieldFromInstruction_4(Insn, 16, 4), + Address, Decoder))) + return MCDisassembler_Fail; + } + break; + } + } + return S; +} + +static DecodeStatus DecodeLongShiftOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if (Val == 0) + Val = 32; + + MCOperand_CreateImm0(Inst, (Val)); + + return S; +} + +static DecodeStatus DecodetGPROddRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if ((RegNo) + 1 > 11) + return MCDisassembler_Fail; + + unsigned Register = GPRDecoderTable[(RegNo) + 1]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodetGPREvenRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if ((RegNo) > 14) + return MCDisassembler_Fail; + + unsigned Register = GPRDecoderTable[(RegNo)]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo == 15) { + MCOperand_CreateReg0(Inst, (ARM_APSR_NZCV)); + return MCDisassembler_Success; + } + + unsigned Register = GPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + + if (RegNo == 13) + return MCDisassembler_SoftFail; + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeVSCCLRM(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + MCOperand_CreateImm0(Inst, (ARMCC_AL)); + MCOperand_CreateReg0(Inst, (0)); + if (MCInst_getOpcode(Inst) == ARM_VSCCLRMD) { + unsigned reglist = (fieldFromInstruction_4(Insn, 1, 7) << 1) | + (fieldFromInstruction_4(Insn, 12, 4) << 8) | + (fieldFromInstruction_4(Insn, 22, 1) << 12); + if (!Check(&S, DecodeDPRRegListOperand(Inst, reglist, Address, + Decoder))) { + return MCDisassembler_Fail; + } + } else { + unsigned reglist = fieldFromInstruction_4(Insn, 0, 8) | + (fieldFromInstruction_4(Insn, 22, 1) << 8) | + (fieldFromInstruction_4(Insn, 12, 4) << 9); + if (!Check(&S, DecodeSPRRegListOperand(Inst, reglist, Address, + Decoder))) { + return MCDisassembler_Fail; + } + } + MCOperand_CreateReg0(Inst, (ARM_VPR)); + + return S; +} + +static DecodeStatus DecodeMQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 7) + return MCDisassembler_Fail; + + unsigned Register = QPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static const uint16_t QQPRDecoderTable[] = { ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, + ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, + ARM_Q6_Q7 }; + +static DecodeStatus DecodeMQQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 6) + return MCDisassembler_Fail; + + unsigned Register = QQPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static const uint16_t QQQQPRDecoderTable[] = { ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, + ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, + ARM_Q4_Q5_Q6_Q7 }; + +static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 4) + return MCDisassembler_Fail; + + unsigned Register = QQQQPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeVPTMaskOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + // Parse VPT mask and encode it in the MCInst as an immediate with the same + // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 + // and 't' as 0 and finish with a 1. + unsigned Imm = 0; + // We always start with a 't'. + unsigned CurBit = 0; + for (int i = 3; i >= 0; --i) { + // If the bit we are looking at is not the same as last one, invert the + // CurBit, if it is the same leave it as is. + CurBit ^= (Val >> i) & 1U; + + // Encode the CurBit at the right place in the immediate. + Imm |= (CurBit << i); + + // If we are done, finish the encoding with a 1. + if ((Val & ~(~0U << i)) == 0) { + Imm |= 1U << i; + break; + } + } + + MCOperand_CreateImm0(Inst, (Imm)); + + return S; +} + +static DecodeStatus DecodeVpredROperand(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + // The vpred_r operand type includes an MQPR register field derived + // from the encoding. But we don't actually want to add an operand + // to the MCInst at this stage, because AddThumbPredicate will do it + // later, and will infer the register number from the TIED_TO + // constraint. So this is a deliberately empty decoder method that + // will inhibit the auto-generated disassembly code from adding an + // operand at all. + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + const void *Decoder) +{ + MCOperand_CreateImm0(Inst, ((Val & 0x1) == 0 ? ARMCC_EQ : ARMCC_NE)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + const void *Decoder) +{ + unsigned Code; + switch (Val & 0x3) { + case 0: + Code = ARMCC_GE; + break; + case 1: + Code = ARMCC_LT; + break; + case 2: + Code = ARMCC_GT; + break; + case 3: + Code = ARMCC_LE; + break; + } + MCOperand_CreateImm0(Inst, (Code)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + const void *Decoder) +{ + MCOperand_CreateImm0(Inst, ((Val & 0x1) == 0 ? ARMCC_HS : ARMCC_HI)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + const void *Decoder) +{ + unsigned Code; + switch (Val) { + default: + return MCDisassembler_Fail; + case 0: + Code = ARMCC_EQ; + break; + case 1: + Code = ARMCC_NE; + break; + case 4: + Code = ARMCC_GE; + break; + case 5: + Code = ARMCC_LT; + break; + case 6: + Code = ARMCC_GT; + break; + case 7: + Code = ARMCC_LE; + break; + } + + MCOperand_CreateImm0(Inst, (Code)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeVCVTImmOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned DecodedVal = 64 - Val; + + switch (MCInst_getOpcode(Inst)) { + case ARM_MVE_VCVTf16s16_fix: + case ARM_MVE_VCVTs16f16_fix: + case ARM_MVE_VCVTf16u16_fix: + case ARM_MVE_VCVTu16f16_fix: + if (DecodedVal > 16) + return MCDisassembler_Fail; + break; + case ARM_MVE_VCVTf32s32_fix: + case ARM_MVE_VCVTs32f32_fix: + case ARM_MVE_VCVTf32u32_fix: + case ARM_MVE_VCVTu32f32_fix: + if (DecodedVal > 32) + return MCDisassembler_Fail; + break; + } + + MCOperand_CreateImm0(Inst, (64 - Val)); + + return S; +} + +static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) +{ + switch (Opcode) { + case ARM_VSTR_P0_off: + case ARM_VSTR_P0_pre: + case ARM_VSTR_P0_post: + case ARM_VLDR_P0_off: + case ARM_VLDR_P0_pre: + case ARM_VLDR_P0_post: + return ARM_P0; + default: + return 0; + } +} + +#define DEFINE_DecodeVSTRVLDR_SYSREG(Writeback) \ + static DecodeStatus CONCAT(DecodeVSTRVLDR_SYSREG, Writeback)( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder) \ + { \ + switch (MCInst_getOpcode(Inst)) { \ + case ARM_VSTR_FPSCR_pre: \ + case ARM_VSTR_FPSCR_NZCVQC_pre: \ + case ARM_VLDR_FPSCR_pre: \ + case ARM_VLDR_FPSCR_NZCVQC_pre: \ + case ARM_VSTR_FPSCR_off: \ + case ARM_VSTR_FPSCR_NZCVQC_off: \ + case ARM_VLDR_FPSCR_off: \ + case ARM_VLDR_FPSCR_NZCVQC_off: \ + case ARM_VSTR_FPSCR_post: \ + case ARM_VSTR_FPSCR_NZCVQC_post: \ + case ARM_VLDR_FPSCR_post: \ + case ARM_VLDR_FPSCR_NZCVQC_post: \ +\ + if (!ARM_getFeatureBits(Inst->csh->mode, \ + ARM_HasMVEIntegerOps) && \ + !ARM_getFeatureBits(Inst->csh->mode, \ + ARM_FeatureVFP2)) \ + return MCDisassembler_Fail; \ + } \ +\ + DecodeStatus S = MCDisassembler_Success; \ + unsigned Sysreg = \ + FixedRegForVSTRVLDR_SYSREG(MCInst_getOpcode(Inst)); \ + if (Sysreg) \ + MCOperand_CreateReg0(Inst, (Sysreg)); \ + unsigned Rn = fieldFromInstruction_4(Val, 16, 4); \ + unsigned addr = fieldFromInstruction_4(Val, 0, 7) | \ + (fieldFromInstruction_4(Val, 23, 1) << 7) | \ + (Rn << 8); \ +\ + if (Writeback) { \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + Inst, Rn, Address, Decoder))) \ + return MCDisassembler_Fail; \ + } \ + if (!Check(&S, DecodeT2AddrModeImm7s4(Inst, addr, Address, \ + Decoder))) \ + return MCDisassembler_Fail; \ +\ + MCOperand_CreateImm0(Inst, (ARMCC_AL)); \ + MCOperand_CreateReg0(Inst, (0)); \ +\ + return S; \ + } +DEFINE_DecodeVSTRVLDR_SYSREG(false) DEFINE_DecodeVSTRVLDR_SYSREG(true) + + static inline DecodeStatus + DecodeMVE_MEM_pre(MCInst *Inst, unsigned Val, uint64_t Address, + const void *Decoder, unsigned Rn, + OperandDecoder RnDecoder, OperandDecoder AddrDecoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Qd = fieldFromInstruction_4(Val, 13, 3); + unsigned addr = fieldFromInstruction_4(Val, 0, 7) | + (fieldFromInstruction_4(Val, 23, 1) << 7) | (Rn << 8); + + if (!Check(&S, RnDecoder(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, AddrDecoder(Inst, addr, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +#define DEFINE_DecodeMVE_MEM_1_pre(shift) \ + static DecodeStatus CONCAT(DecodeMVE_MEM_1_pre, shift)( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder) \ + { \ + return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \ + fieldFromInstruction_4(Val, 16, 3), \ + DecodetGPRRegisterClass, \ + CONCAT(DecodeTAddrModeImm7, shift)); \ + } +DEFINE_DecodeMVE_MEM_1_pre(0) DEFINE_DecodeMVE_MEM_1_pre(1) + +#define DEFINE_DecodeMVE_MEM_2_pre(shift) \ + static DecodeStatus CONCAT(DecodeMVE_MEM_2_pre, shift)( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder) \ + { \ + return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \ + fieldFromInstruction_4(Val, 16, 4), \ + DecoderGPRRegisterClass, \ + CONCAT(DecodeT2AddrModeImm7, \ + CONCAT(shift, 1))); \ + } + DEFINE_DecodeMVE_MEM_2_pre(0) DEFINE_DecodeMVE_MEM_2_pre( + 1) DEFINE_DecodeMVE_MEM_2_pre(2) + +#define DEFINE_DecodeMVE_MEM_3_pre(shift) \ + static DecodeStatus CONCAT(DecodeMVE_MEM_3_pre, shift)( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder) \ + { \ + return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \ + fieldFromInstruction_4(Val, 17, 3), \ + DecodeMQPRRegisterClass, \ + CONCAT(DecodeMveAddrModeQ, shift)); \ + } + DEFINE_DecodeMVE_MEM_3_pre(2) DEFINE_DecodeMVE_MEM_3_pre(3) + +#define DEFINE_DecodePowerTwoOperand(MinLog, MaxLog) \ + static DecodeStatus CONCAT(DecodePowerTwoOperand, \ + CONCAT(MinLog, MaxLog))( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder) \ + { \ + DecodeStatus S = MCDisassembler_Success; \ +\ + if (Val < MinLog || Val > MaxLog) \ + return MCDisassembler_Fail; \ +\ + MCOperand_CreateImm0(Inst, (1LL << Val)); \ + return S; \ + } + DEFINE_DecodePowerTwoOperand(0, 3) + +#define DEFINE_DecodeMVEPairVectorIndexOperand(start) \ + static DecodeStatus CONCAT(DecodeMVEPairVectorIndexOperand, start)( \ + MCInst * Inst, unsigned Val, uint64_t Address, \ + const void *Decoder) \ + { \ + DecodeStatus S = MCDisassembler_Success; \ +\ + MCOperand_CreateImm0(Inst, (start + Val)); \ +\ + return S; \ + } + DEFINE_DecodeMVEPairVectorIndexOperand(2) + DEFINE_DecodeMVEPairVectorIndexOperand(0) + + static DecodeStatus + DecodeMVEVMOVQtoDReg(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); + unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) | + fieldFromInstruction_4(Insn, 13, 3)); + unsigned index = fieldFromInstruction_4(Insn, 4, 1); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, CONCAT(DecodeMVEPairVectorIndexOperand, + 2)(Inst, index, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, CONCAT(DecodeMVEPairVectorIndexOperand, + 0)(Inst, index, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); + unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) | + fieldFromInstruction_4(Insn, 13, 3)); + unsigned index = fieldFromInstruction_4(Insn, 4, 1); + + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, CONCAT(DecodeMVEPairVectorIndexOperand, + 2)(Inst, index, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, CONCAT(DecodeMVEPairVectorIndexOperand, + 0)(Inst, index, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeMVEOverlappingLongShift(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned RdaLo = fieldFromInstruction_4(Insn, 17, 3) << 1; + unsigned RdaHi = fieldFromInstruction_4(Insn, 9, 3) << 1; + unsigned Rm = fieldFromInstruction_4(Insn, 12, 4); + + if (RdaHi == 14) { + // This value of RdaHi (really indicating pc, because RdaHi has to + // be an odd-numbered register, so the low bit will be set by the + // decode function below) indicates that we must decode as SQRSHR + // or UQRSHL, which both have a single Rda register field with all + // four bits. + unsigned Rda = fieldFromInstruction_4(Insn, 16, 4); + + switch (MCInst_getOpcode(Inst)) { + case ARM_MVE_ASRLr: + case ARM_MVE_SQRSHRL: + MCInst_setOpcode(Inst, (ARM_MVE_SQRSHR)); + break; + case ARM_MVE_LSLLr: + case ARM_MVE_UQRSHLL: + MCInst_setOpcode(Inst, (ARM_MVE_UQRSHL)); + break; + default: + // llvm_unreachable("Unexpected starting opcode!"); + break; + } + + // Rda as output parameter + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rda, Address, + Decoder))) + return MCDisassembler_Fail; + + // Rda again as input parameter + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rda, Address, + Decoder))) + return MCDisassembler_Fail; + + // Rm, the amount to shift by + if (!Check(&S, + DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + if (fieldFromInstruction_4(Insn, 6, 3) != 4) + return MCDisassembler_SoftFail; + + if (Rda == Rm) + return MCDisassembler_SoftFail; + + return S; + } + + // Otherwise, we decode as whichever opcode our caller has already + // put into Inst. Those all look the same: + + // RdaLo,RdaHi as output parameters + if (!Check(&S, + DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) + return MCDisassembler_Fail; + + // RdaLo,RdaHi again as input parameters + if (!Check(&S, + DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) + return MCDisassembler_Fail; + + // Rm, the amount to shift by + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + if (MCInst_getOpcode(Inst) == ARM_MVE_SQRSHRL || + MCInst_getOpcode(Inst) == ARM_MVE_UQRSHLL) { + unsigned Saturate = fieldFromInstruction_4(Insn, 7, 1); + // Saturate, the bit position for saturation + MCOperand_CreateImm0(Inst, (Saturate)); + } + + return S; +} + +static DecodeStatus DecodeMVEVCVTt1fp(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) | + fieldFromInstruction_4(Insn, 13, 3)); + unsigned Qm = ((fieldFromInstruction_4(Insn, 5, 1) << 3) | + fieldFromInstruction_4(Insn, 1, 3)); + unsigned imm6 = fieldFromInstruction_4(Insn, 16, 6); + + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +#define DEFINE_DecodeMVEVCMP(scalar, predicate_decoder) \ + static DecodeStatus CONCAT(DecodeMVEVCMP, \ + CONCAT(scalar, predicate_decoder))( \ + MCInst * Inst, unsigned Insn, uint64_t Address, \ + const void *Decoder) \ + { \ + DecodeStatus S = MCDisassembler_Success; \ + MCOperand_CreateReg0(Inst, (ARM_VPR)); \ + unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, \ + Decoder))) \ + return MCDisassembler_Fail; \ +\ + unsigned fc; \ +\ + if (scalar) { \ + fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \ + fieldFromInstruction_4(Insn, 7, 1) | \ + fieldFromInstruction_4(Insn, 5, 1) << 1; \ + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); \ + if (!Check(&S, DecodeGPRwithZRRegisterClass( \ + Inst, Rm, Address, Decoder))) \ + return MCDisassembler_Fail; \ + } else { \ + fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \ + fieldFromInstruction_4(Insn, 7, 1) | \ + fieldFromInstruction_4(Insn, 0, 1) << 1; \ + unsigned Qm = fieldFromInstruction_4(Insn, 5, 1) \ + << 4 | \ + fieldFromInstruction_4(Insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + Inst, Qm, Address, Decoder))) \ + return MCDisassembler_Fail; \ + } \ +\ + if (!Check(&S, predicate_decoder(Inst, fc, Address, Decoder))) \ + return MCDisassembler_Fail; \ +\ + MCOperand_CreateImm0(Inst, (ARMVCC_None)); \ + MCOperand_CreateReg0(Inst, (0)); \ + MCOperand_CreateImm0(Inst, (0)); \ +\ + return S; \ + } +DEFINE_DecodeMVEVCMP(false, DecodeRestrictedIPredicateOperand) DEFINE_DecodeMVEVCMP( + false, DecodeRestrictedUPredicateOperand) + DEFINE_DecodeMVEVCMP(false, DecodeRestrictedSPredicateOperand) + DEFINE_DecodeMVEVCMP(true, DecodeRestrictedIPredicateOperand) + DEFINE_DecodeMVEVCMP(true, + DecodeRestrictedUPredicateOperand) + DEFINE_DecodeMVEVCMP( + true, DecodeRestrictedSPredicateOperand) + DEFINE_DecodeMVEVCMP( + false, + DecodeRestrictedFPPredicateOperand) + DEFINE_DecodeMVEVCMP( + true, + DecodeRestrictedFPPredicateOperand) + + static DecodeStatus + DecodeMveVCTP(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + MCOperand_CreateReg0(Inst, (ARM_VPR)); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + return S; +} + +static DecodeStatus DecodeMVEVPNOT(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + MCOperand_CreateReg0(Inst, (ARM_VPR)); + MCOperand_CreateReg0(Inst, (ARM_VPR)); + return S; +} + +static DecodeStatus DecodeT2AddSubSPImm(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + const unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); + const unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + const unsigned Imm12 = fieldFromInstruction_4(Insn, 26, 1) << 11 | + fieldFromInstruction_4(Insn, 12, 3) << 8 | + fieldFromInstruction_4(Insn, 0, 8); + const unsigned TypeT3 = fieldFromInstruction_4(Insn, 25, 1); + unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1); + unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1); + unsigned S = fieldFromInstruction_4(Insn, 20, 1); + if (sign1 != sign2) + return MCDisassembler_Fail; + + // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) + DecodeStatus DS = MCDisassembler_Success; + if ((!Check(&DS, DecodeGPRspRegisterClass(Inst, Rd, Address, + Decoder))) || // dst + (!Check(&DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) + return MCDisassembler_Fail; + if (TypeT3) { + MCInst_setOpcode(Inst, + (sign1 ? ARM_t2SUBspImm12 : ARM_t2ADDspImm12)); + MCOperand_CreateImm0(Inst, (Imm12)); // zext imm12 + } else { + MCInst_setOpcode(Inst, + (sign1 ? ARM_t2SUBspImm : ARM_t2ADDspImm)); + if (!Check(&DS, DecodeT2SOImm(Inst, Imm12, Address, + Decoder))) // imm12 + return MCDisassembler_Fail; + if (!Check(&DS, DecodeCCOutOperand(Inst, S, Address, + Decoder))) // cc_out + return MCDisassembler_Fail; + } + + return DS; +} + +DecodeStatus ARM_LLVM_getInstruction(csh handle, const uint8_t *code, + size_t code_len, MCInst *instr, + uint16_t *size, uint64_t address, + void *info) +{ + return getInstruction(handle, code, code_len, instr, size, address, + info); +} diff --git a/thirdparty/capstone/arch/ARM/ARMDisassemblerExtension.c b/thirdparty/capstone/arch/ARM/ARMDisassemblerExtension.c new file mode 100644 index 0000000..2d3ad4e --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMDisassemblerExtension.c @@ -0,0 +1,238 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ +/* Rot127 , 2022-2023 */ + +#include "ARMDisassemblerExtension.h" +#include "ARMBaseInfo.h" + +bool ITBlock_push_back(ARM_ITBlock *it, char v) +{ + if (it->size >= sizeof(it->ITStates)) { + // TODO: consider warning user. + it->size = 0; + } + it->ITStates[it->size] = v; + it->size++; + + return true; +} + +// Returns true if the current instruction is in an IT block +bool ITBlock_instrInITBlock(ARM_ITBlock *it) +{ + return (it->size > 0); +} + +// Returns true if current instruction is the last instruction in an IT block +bool ITBlock_instrLastInITBlock(ARM_ITBlock *it) +{ + return (it->size == 1); +} + +// Returns the condition code for instruction in IT block +unsigned ITBlock_getITCC(ARM_ITBlock *it) +{ + unsigned CC = ARMCC_AL; + + if (ITBlock_instrInITBlock(it)) + CC = it->ITStates[it->size - 1]; + + return CC; +} + +// Advances the IT block state to the next T or E +void ITBlock_advanceITState(ARM_ITBlock *it) +{ + it->size--; +} + +// Called when decoding an IT instruction. Sets the IT state for the following +// instructions that for the IT block. Firstcond and Mask correspond to the +// fields in the IT instruction encoding. +void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask) +{ + // (3 - the number of trailing zeros) is the number of then / else. + unsigned NumTZ = CountTrailingZeros_8(Mask); + unsigned char CCBits = (unsigned char)(Firstcond & 0xf); + assert(NumTZ <= 3 && "Invalid IT mask!"); + // push condition codes onto the stack the correct order for the pops + for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) { + unsigned Else = (Mask >> Pos) & 1; + ITBlock_push_back(it, CCBits ^ Else); + } + ITBlock_push_back(it, CCBits); +} + +bool VPTBlock_push_back(ARM_VPTBlock *it, char v) +{ + if (it->size >= sizeof(it->VPTStates)) { + // TODO: consider warning user. + it->size = 0; + } + it->VPTStates[it->size] = v; + it->size++; + + return true; +} + +bool VPTBlock_instrInVPTBlock(ARM_VPTBlock *VPT) +{ + return VPT->size > 0; +} + +unsigned VPTBlock_getVPTPred(ARM_VPTBlock *VPT) +{ + unsigned Pred = ARMVCC_None; + if (VPTBlock_instrInVPTBlock(VPT)) + Pred = VPT->VPTStates[VPT->size - 1]; + return Pred; +} + +void VPTBlock_advanceVPTState(ARM_VPTBlock *VPT) +{ + VPT->size--; +} + +void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask) +{ + // (3 - the number of trailing zeros) is the number of then / else. + unsigned NumTZ = CountTrailingZeros_8(Mask); + assert(NumTZ <= 3 && "Invalid VPT mask!"); + // push predicates onto the stack the correct order for the pops + for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) { + bool T = ((Mask >> Pos) & 1) == 0; + if (T) + VPTBlock_push_back(VPT, ARMVCC_Then); + else + VPTBlock_push_back(VPT, ARMVCC_Else); + } + VPTBlock_push_back(VPT, ARMVCC_Then); +} + +/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. + +bool Check(DecodeStatus *Out, DecodeStatus In) +{ + switch (In) { + case MCDisassembler_Success: + // Out stays the same. + return true; + case MCDisassembler_SoftFail: + *Out = In; + return true; + case MCDisassembler_Fail: + *Out = In; + return false; + default: // never reached + return false; + } +} + +// Imported from ARMBaseInstrInfo.h +// +/// isValidCoprocessorNumber - decide whether an explicit coprocessor +/// number is legal in generic instructions like CDP. The answer can +/// vary with the subtarget. +bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num) +{ + // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the + // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is + // useful for code which is shared with older architectures which do not + // know the new VFP/NEON mnemonics. + + // Armv8-A disallows everything *other* than 111x (CP14 and CP15). + if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && + (Num & 0xE) != 0xE) + return false; + + // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15) + // which clash with MVE. + if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps) && + ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE)) + return false; + + return true; +} + +// Imported from ARMMCTargetDesc.h +bool ARM_isVpred(arm_op_type op) +{ + return op == ARM_OP_VPRED_R || op == ARM_OP_VPRED_N; +} + +// Imported from ARMBaseInstrInfo.h +// +// This table shows the VPT instruction variants, i.e. the different +// mask field encodings, see also B5.6. Predication/conditional execution in +// the ArmARM. +bool isVPTOpcode(int Opc) +{ + return Opc == ARM_MVE_VPTv16i8 || Opc == ARM_MVE_VPTv16u8 || + Opc == ARM_MVE_VPTv16s8 || Opc == ARM_MVE_VPTv8i16 || + Opc == ARM_MVE_VPTv8u16 || Opc == ARM_MVE_VPTv8s16 || + Opc == ARM_MVE_VPTv4i32 || Opc == ARM_MVE_VPTv4u32 || + Opc == ARM_MVE_VPTv4s32 || Opc == ARM_MVE_VPTv4f32 || + Opc == ARM_MVE_VPTv8f16 || Opc == ARM_MVE_VPTv16i8r || + Opc == ARM_MVE_VPTv16u8r || Opc == ARM_MVE_VPTv16s8r || + Opc == ARM_MVE_VPTv8i16r || Opc == ARM_MVE_VPTv8u16r || + Opc == ARM_MVE_VPTv8s16r || Opc == ARM_MVE_VPTv4i32r || + Opc == ARM_MVE_VPTv4u32r || Opc == ARM_MVE_VPTv4s32r || + Opc == ARM_MVE_VPTv4f32r || Opc == ARM_MVE_VPTv8f16r || + Opc == ARM_MVE_VPST; +} + +// Imported from ARMMCTargetDesc.cpp +bool ARM_isCDECoproc(size_t Coproc, const MCInst *MI) +{ + // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have + // to rely on feature bits. + if (Coproc >= 8) + return false; + + return ARM_getFeatureBits(MI->csh->mode, + ARM_FeatureCoprocCDE0 + Coproc); +} + +// Hacky: enable all features for disassembler +bool ARM_getFeatureBits(unsigned int mode, unsigned int feature) +{ + if (feature == ARM_ModeThumb) { + if (mode & CS_MODE_THUMB) + return true; + return false; + } + + if (feature == ARM_FeatureDFB) + return false; + + if (feature == ARM_FeatureRAS) + return false; + + if (feature == ARM_FeatureMClass && (mode & CS_MODE_MCLASS) == 0) + return false; + + if ((feature == ARM_HasMVEIntegerOps || feature == ARM_HasMVEFloatOps || + feature == ARM_FeatureMVEVectorCostFactor1 || + feature == ARM_FeatureMVEVectorCostFactor2 || + feature == ARM_FeatureMVEVectorCostFactor4) && + (mode & CS_MODE_MCLASS) == 0) + return false; + + if ((feature == ARM_HasV8Ops || feature == ARM_HasV8_1MMainlineOps || + feature == ARM_HasV8_1aOps || feature == ARM_HasV8_2aOps || + feature == ARM_HasV8_3aOps || feature == ARM_HasV8_4aOps || + feature == ARM_HasV8_5aOps || feature == ARM_HasV8_6aOps || + feature == ARM_HasV8_7aOps || feature == ARM_HasV8_8aOps || + feature == ARM_HasV8_9aOps) && + (mode & CS_MODE_V8) == 0) + return false; + + if (feature >= ARM_FeatureCoprocCDE0 && + feature <= ARM_FeatureCoprocCDE7) + // We currently have no way to detect CDE (Custom-Datapath-Extension) + // coprocessors. + return false; + + // we support everything + return true; +} diff --git a/thirdparty/capstone/arch/ARM/ARMDisassemblerExtension.h b/thirdparty/capstone/arch/ARM/ARMDisassemblerExtension.h new file mode 100644 index 0000000..6d1be46 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMDisassemblerExtension.h @@ -0,0 +1,51 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ +/* Rot127 , 2022-2023 */ + +#ifndef CS_ARM_DISASSEMBLER_EXTENSION_H +#define CS_ARM_DISASSEMBLER_EXTENSION_H + +#include "../../MCDisassembler.h" +#include "../../MCRegisterInfo.h" +#include "../../MathExtras.h" +#include "../../cs_priv.h" +#include "ARMAddressingModes.h" +#include "capstone/capstone.h" + +unsigned ARM_AM_getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset); + +bool ITBlock_push_back(ARM_ITBlock *it, char v); + +bool ITBlock_instrInITBlock(ARM_ITBlock *it); + +bool ITBlock_instrLastInITBlock(ARM_ITBlock *it); + +unsigned ITBlock_getITCC(ARM_ITBlock *it); + +void ITBlock_advanceITState(ARM_ITBlock *it); + +void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask); + +bool Check(DecodeStatus *Out, DecodeStatus In); + +bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num); + +bool ARM_isVpred(arm_op_type op); + +bool isVPTOpcode(int Opc); + +bool ARM_isCDECoproc(size_t Coproc, const MCInst *MI); + +bool VPTBlock_push_back(ARM_VPTBlock *it, char v); + +bool VPTBlock_instrInVPTBlock(ARM_VPTBlock *VPT); + +unsigned VPTBlock_getVPTPred(ARM_VPTBlock *VPT); + +void VPTBlock_advanceVPTState(ARM_VPTBlock *VPT); + +void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask); + +bool ARM_getFeatureBits(unsigned int mode, unsigned int feature); + +#endif // CS_ARM_DISASSEMBLER_EXTENSION_H diff --git a/thirdparty/capstone/arch/ARM/ARMFeatureEnum.inc b/thirdparty/capstone/arch/ARM/ARMFeatureEnum.inc new file mode 100644 index 0000000..d054c3d --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMFeatureEnum.inc @@ -0,0 +1,22 @@ +ARM_FEATURE_IsThumb = 128, ARM_FEATURE_IsARM, ARM_FEATURE_UseNegativeImmediates, + ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasAES, + ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, ARM_FEATURE_HasV7, + ARM_FEATURE_IsMClass, ARM_FEATURE_HasPACBTI, ARM_FEATURE_HasV8MBaseline, + ARM_FEATURE_HasLOB, ARM_FEATURE_HasV6T2, ARM_FEATURE_HasV5T, + ARM_FEATURE_IsNotMClass, ARM_FEATURE_Has8MSecExt, ARM_FEATURE_HasV4T, + ARM_FEATURE_PreV8, ARM_FEATURE_HasCLRBHB, ARM_FEATURE_HasV6K, + ARM_FEATURE_HasV7Clrex, ARM_FEATURE_HasCRC, ARM_FEATURE_HasCDE, + ARM_FEATURE_HasDFB, ARM_FEATURE_HasDB, ARM_FEATURE_HasVirtualization, + ARM_FEATURE_HasRAS, ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, + ARM_FEATURE_HasVFP3, ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV6M, + ARM_FEATURE_HasV6, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV5TE, + ARM_FEATURE_HasDSP, ARM_FEATURE_HasMP, ARM_FEATURE_HasSB, + ARM_FEATURE_HasDivideInThumb, ARM_FEATURE_HasDivideInARM, + ARM_FEATURE_HasV8_1a, ARM_FEATURE_HasSHA2, ARM_FEATURE_HasTrustZone, + ARM_FEATURE_UseNaClTrap, ARM_FEATURE_HasV8_4a, ARM_FEATURE_HasNEON, + ARM_FEATURE_HasFullFP16, ARM_FEATURE_HasMVEFloat, ARM_FEATURE_HasV8_3a, + ARM_FEATURE_HasFP16, ARM_FEATURE_HasBF16, ARM_FEATURE_HasFPARMv8, + ARM_FEATURE_HasVFP4, ARM_FEATURE_HasFP16FML, ARM_FEATURE_HasFPRegs16, + ARM_FEATURE_HasV8MMainline, ARM_FEATURE_HasFPRegs64, + ARM_FEATURE_HasFPRegsV8_1M, ARM_FEATURE_HasDotProd, + ARM_FEATURE_HasMatMulInt8, diff --git a/thirdparty/capstone/arch/ARM/ARMGenAsmWriter.inc b/thirdparty/capstone/arch/ARM/ARMGenAsmWriter.inc new file mode 100644 index 0000000..453e96b --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMGenAsmWriter.inc @@ -0,0 +1,13360 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#include +#include + +/// getMnemonic - This method is automatically generated by tablegen +/// from the instruction set description. +static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) +{ +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ "vcx1\t\0" + /* 6 */ "vld20.32\t\0" + /* 16 */ "vst20.32\t\0" + /* 26 */ "vld40.32\t\0" + /* 36 */ "vst40.32\t\0" + /* 46 */ "sha1su0.32\t\0" + /* 58 */ "sha256su0.32\t\0" + /* 72 */ "vld21.32\t\0" + /* 82 */ "vst21.32\t\0" + /* 92 */ "vld41.32\t\0" + /* 102 */ "vst41.32\t\0" + /* 112 */ "sha1su1.32\t\0" + /* 124 */ "sha256su1.32\t\0" + /* 138 */ "vld42.32\t\0" + /* 148 */ "vst42.32\t\0" + /* 158 */ "sha256h2.32\t\0" + /* 171 */ "vld43.32\t\0" + /* 181 */ "vst43.32\t\0" + /* 191 */ "sha1c.32\t\0" + /* 201 */ "sha1h.32\t\0" + /* 211 */ "sha256h.32\t\0" + /* 223 */ "sha1m.32\t\0" + /* 233 */ "sha1p.32\t\0" + /* 243 */ "dlstp.32\t\0" + /* 253 */ "wlstp.32\t\0" + /* 263 */ "vcvta.s32.f32\t\0" + /* 278 */ "vcvtm.s32.f32\t\0" + /* 293 */ "vcvtn.s32.f32\t\0" + /* 308 */ "vcvtp.s32.f32\t\0" + /* 323 */ "vcvta.u32.f32\t\0" + /* 338 */ "vcvtm.u32.f32\t\0" + /* 353 */ "vcvtn.u32.f32\t\0" + /* 368 */ "vcvtp.u32.f32\t\0" + /* 383 */ "vcmla.f32\t\0" + /* 394 */ "vrinta.f32\t\0" + /* 406 */ "vcadd.f32\t\0" + /* 417 */ "vselge.f32\t\0" + /* 429 */ "vminnm.f32\t\0" + /* 441 */ "vmaxnm.f32\t\0" + /* 453 */ "vrintm.f32\t\0" + /* 465 */ "vrintn.f32\t\0" + /* 477 */ "vrintp.f32\t\0" + /* 489 */ "vseleq.f32\t\0" + /* 501 */ "vselvs.f32\t\0" + /* 513 */ "vselgt.f32\t\0" + /* 525 */ "vrintx.f32\t\0" + /* 537 */ "vrintz.f32\t\0" + /* 549 */ "ldc2\t\0" + /* 555 */ "mrc2\t\0" + /* 561 */ "mrrc2\t\0" + /* 568 */ "stc2\t\0" + /* 574 */ "cdp2\t\0" + /* 580 */ "mcr2\t\0" + /* 586 */ "mcrr2\t\0" + /* 593 */ "vcx2\t\0" + /* 599 */ "vcx3\t\0" + /* 605 */ "dlstp.64\t\0" + /* 615 */ "wlstp.64\t\0" + /* 625 */ "vcvta.s32.f64\t\0" + /* 640 */ "vcvtm.s32.f64\t\0" + /* 655 */ "vcvtn.s32.f64\t\0" + /* 670 */ "vcvtp.s32.f64\t\0" + /* 685 */ "vcvta.u32.f64\t\0" + /* 700 */ "vcvtm.u32.f64\t\0" + /* 715 */ "vcvtn.u32.f64\t\0" + /* 730 */ "vcvtp.u32.f64\t\0" + /* 745 */ "vrinta.f64\t\0" + /* 757 */ "vselge.f64\t\0" + /* 769 */ "vminnm.f64\t\0" + /* 781 */ "vmaxnm.f64\t\0" + /* 793 */ "vrintm.f64\t\0" + /* 805 */ "vrintn.f64\t\0" + /* 817 */ "vrintp.f64\t\0" + /* 829 */ "vseleq.f64\t\0" + /* 841 */ "vselvs.f64\t\0" + /* 853 */ "vselgt.f64\t\0" + /* 865 */ "vmull.p64\t\0" + /* 876 */ "vld20.16\t\0" + /* 886 */ "vst20.16\t\0" + /* 896 */ "vld40.16\t\0" + /* 906 */ "vst40.16\t\0" + /* 916 */ "vld21.16\t\0" + /* 926 */ "vst21.16\t\0" + /* 936 */ "vld41.16\t\0" + /* 946 */ "vst41.16\t\0" + /* 956 */ "vld42.16\t\0" + /* 966 */ "vst42.16\t\0" + /* 976 */ "vld43.16\t\0" + /* 986 */ "vst43.16\t\0" + /* 996 */ "dlstp.16\t\0" + /* 1006 */ "wlstp.16\t\0" + /* 1016 */ "vcvta.s32.f16\t\0" + /* 1031 */ "vcvtm.s32.f16\t\0" + /* 1046 */ "vcvtn.s32.f16\t\0" + /* 1061 */ "vcvtp.s32.f16\t\0" + /* 1076 */ "vcvta.u32.f16\t\0" + /* 1091 */ "vcvtm.u32.f16\t\0" + /* 1106 */ "vcvtn.u32.f16\t\0" + /* 1121 */ "vcvtp.u32.f16\t\0" + /* 1136 */ "vcvta.s16.f16\t\0" + /* 1151 */ "vcvtm.s16.f16\t\0" + /* 1166 */ "vcvtn.s16.f16\t\0" + /* 1181 */ "vcvtp.s16.f16\t\0" + /* 1196 */ "vcvta.u16.f16\t\0" + /* 1211 */ "vcvtm.u16.f16\t\0" + /* 1226 */ "vcvtn.u16.f16\t\0" + /* 1241 */ "vcvtp.u16.f16\t\0" + /* 1256 */ "vcmla.f16\t\0" + /* 1267 */ "vrinta.f16\t\0" + /* 1279 */ "vcadd.f16\t\0" + /* 1290 */ "vselge.f16\t\0" + /* 1302 */ "vfmal.f16\t\0" + /* 1313 */ "vfmsl.f16\t\0" + /* 1324 */ "vminnm.f16\t\0" + /* 1336 */ "vmaxnm.f16\t\0" + /* 1348 */ "vrintm.f16\t\0" + /* 1360 */ "vrintn.f16\t\0" + /* 1372 */ "vrintp.f16\t\0" + /* 1384 */ "vseleq.f16\t\0" + /* 1396 */ "vins.f16\t\0" + /* 1406 */ "vselvs.f16\t\0" + /* 1418 */ "vselgt.f16\t\0" + /* 1430 */ "vrintx.f16\t\0" + /* 1442 */ "vmovx.f16\t\0" + /* 1453 */ "vrintz.f16\t\0" + /* 1465 */ "vmmla.bf16\t\0" + /* 1477 */ "vfmab.bf16\t\0" + /* 1489 */ "vfmat.bf16\t\0" + /* 1501 */ "vdot.bf16\t\0" + /* 1512 */ "vld20.8\t\0" + /* 1521 */ "vst20.8\t\0" + /* 1530 */ "vld40.8\t\0" + /* 1539 */ "vst40.8\t\0" + /* 1548 */ "vld21.8\t\0" + /* 1557 */ "vst21.8\t\0" + /* 1566 */ "vld41.8\t\0" + /* 1575 */ "vst41.8\t\0" + /* 1584 */ "vld42.8\t\0" + /* 1593 */ "vst42.8\t\0" + /* 1602 */ "vld43.8\t\0" + /* 1611 */ "vst43.8\t\0" + /* 1620 */ "aesimc.8\t\0" + /* 1630 */ "aesmc.8\t\0" + /* 1639 */ "aesd.8\t\0" + /* 1647 */ "aese.8\t\0" + /* 1655 */ "dlstp.8\t\0" + /* 1664 */ "wlstp.8\t\0" + /* 1673 */ "vusmmla.s8\t\0" + /* 1685 */ "vsmmla.s8\t\0" + /* 1696 */ "vusdot.s8\t\0" + /* 1707 */ "vsdot.s8\t\0" + /* 1717 */ "vummla.u8\t\0" + /* 1728 */ "vsudot.u8\t\0" + /* 1739 */ "vudot.u8\t\0" + /* 1749 */ "vcx1a\t\0" + /* 1756 */ "vcx2a\t\0" + /* 1763 */ "vcx3a\t\0" + /* 1770 */ "rfeda\t\0" + /* 1777 */ "rfeia\t\0" + /* 1784 */ "crc32b\t\0" + /* 1792 */ "crc32cb\t\0" + /* 1801 */ "rfedb\t\0" + /* 1808 */ "rfeib\t\0" + /* 1815 */ "dmb\t\0" + /* 1820 */ "dsb\t\0" + /* 1825 */ "isb\t\0" + /* 1830 */ "tsb\t\0" + /* 1835 */ "csinc\t\0" + /* 1842 */ "hvc\t\0" + /* 1847 */ "cx1d\t\0" + /* 1853 */ "cx2d\t\0" + /* 1859 */ "cx3d\t\0" + /* 1865 */ "pld\t\0" + /* 1870 */ "setend\t\0" + /* 1878 */ "le\t\0" + /* 1882 */ "udf\t\0" + /* 1887 */ "csneg\t\0" + /* 1894 */ "crc32h\t\0" + /* 1902 */ "crc32ch\t\0" + /* 1911 */ "pli\t\0" + /* 1916 */ "bti\t\0" + /* 1921 */ "ldc2l\t\0" + /* 1928 */ "stc2l\t\0" + /* 1935 */ "bl\t\0" + /* 1939 */ "bfcsel\t\0" + /* 1947 */ "setpan\t\0" + /* 1955 */ "letp\t\0" + /* 1961 */ "dls\t\0" + /* 1966 */ "wls\t\0" + /* 1971 */ "cps\t\0" + /* 1976 */ "movs\t\0" + /* 1982 */ "hlt\t\0" + /* 1987 */ "bkpt\t\0" + /* 1993 */ "csinv\t\0" + /* 2000 */ "hvc.w\t\0" + /* 2007 */ "udf.w\t\0" + /* 2014 */ "crc32w\t\0" + /* 2022 */ "crc32cw\t\0" + /* 2031 */ "pldw\t\0" + /* 2037 */ "bx\t\0" + /* 2041 */ "blx\t\0" + /* 2046 */ "cbz\t\0" + /* 2051 */ "cbnz\t\0" + /* 2057 */ "srsda\tsp!, \0" + /* 2069 */ "srsia\tsp!, \0" + /* 2081 */ "srsdb\tsp!, \0" + /* 2093 */ "srsib\tsp!, \0" + /* 2105 */ "srsda\tsp, \0" + /* 2116 */ "srsia\tsp, \0" + /* 2127 */ "srsdb\tsp, \0" + /* 2138 */ "srsib\tsp, \0" + /* 2149 */ "# XRay Function Patchable RET.\0" + /* 2180 */ "# XRay Typed Event Log.\0" + /* 2204 */ "# XRay Custom Event Log.\0" + /* 2229 */ "# XRay Function Enter.\0" + /* 2252 */ "# XRay Tail Call Exit.\0" + /* 2275 */ "# XRay Function Exit.\0" + /* 2297 */ "__brkdiv0\0" + /* 2307 */ "vld1\0" + /* 2312 */ "dcps1\0" + /* 2318 */ "vst1\0" + /* 2323 */ "vcx1\0" + /* 2328 */ "vrev32\0" + /* 2335 */ "ldc2\0" + /* 2340 */ "mrc2\0" + /* 2345 */ "mrrc2\0" + /* 2351 */ "stc2\0" + /* 2356 */ "vld2\0" + /* 2361 */ "cdp2\0" + /* 2366 */ "mcr2\0" + /* 2371 */ "mcrr2\0" + /* 2377 */ "dcps2\0" + /* 2383 */ "vst2\0" + /* 2388 */ "vcx2\0" + /* 2393 */ "vld3\0" + /* 2398 */ "dcps3\0" + /* 2404 */ "vst3\0" + /* 2409 */ "vcx3\0" + /* 2414 */ "vrev64\0" + /* 2421 */ "vld4\0" + /* 2426 */ "vst4\0" + /* 2431 */ "sxtab16\0" + /* 2439 */ "uxtab16\0" + /* 2447 */ "sxtb16\0" + /* 2454 */ "uxtb16\0" + /* 2461 */ "shsub16\0" + /* 2469 */ "uhsub16\0" + /* 2477 */ "uqsub16\0" + /* 2485 */ "ssub16\0" + /* 2492 */ "usub16\0" + /* 2499 */ "shadd16\0" + /* 2507 */ "uhadd16\0" + /* 2515 */ "uqadd16\0" + /* 2523 */ "sadd16\0" + /* 2530 */ "uadd16\0" + /* 2537 */ "ssat16\0" + /* 2544 */ "usat16\0" + /* 2551 */ "vrev16\0" + /* 2558 */ "usada8\0" + /* 2565 */ "shsub8\0" + /* 2572 */ "uhsub8\0" + /* 2579 */ "uqsub8\0" + /* 2586 */ "ssub8\0" + /* 2592 */ "usub8\0" + /* 2598 */ "usad8\0" + /* 2604 */ "shadd8\0" + /* 2611 */ "uhadd8\0" + /* 2618 */ "uqadd8\0" + /* 2625 */ "sadd8\0" + /* 2631 */ "uadd8\0" + /* 2637 */ "LIFETIME_END\0" + /* 2650 */ "PSEUDO_PROBE\0" + /* 2663 */ "BUNDLE\0" + /* 2670 */ "DBG_VALUE\0" + /* 2680 */ "DBG_INSTR_REF\0" + /* 2694 */ "DBG_PHI\0" + /* 2702 */ "DBG_LABEL\0" + /* 2712 */ "LIFETIME_START\0" + /* 2727 */ "DBG_VALUE_LIST\0" + /* 2742 */ "vcx1a\0" + /* 2748 */ "vcx2a\0" + /* 2754 */ "vcx3a\0" + /* 2760 */ "vaba\0" + /* 2765 */ "cx1da\0" + /* 2771 */ "cx2da\0" + /* 2777 */ "cx3da\0" + /* 2783 */ "lda\0" + /* 2787 */ "ldmda\0" + /* 2793 */ "stmda\0" + /* 2799 */ "vrmlaldavha\0" + /* 2811 */ "vrmlsldavha\0" + /* 2823 */ "rfeia\0" + /* 2829 */ "vldmia\0" + /* 2836 */ "vstmia\0" + /* 2843 */ "srsia\0" + /* 2849 */ "vcmla\0" + /* 2855 */ "smmla\0" + /* 2861 */ "vnmla\0" + /* 2867 */ "vmla\0" + /* 2872 */ "vfma\0" + /* 2877 */ "vfnma\0" + /* 2883 */ "vminnma\0" + /* 2891 */ "vmaxnma\0" + /* 2899 */ "vmina\0" + /* 2905 */ "vrsra\0" + /* 2911 */ "vsra\0" + /* 2916 */ "vrinta\0" + /* 2923 */ "tta\0" + /* 2927 */ "vcvta\0" + /* 2933 */ "vmladava\0" + /* 2942 */ "vmlaldava\0" + /* 2952 */ "vmlsldava\0" + /* 2962 */ "vmlsdava\0" + /* 2971 */ "vaddva\0" + /* 2978 */ "vaddlva\0" + /* 2986 */ "vmaxa\0" + /* 2992 */ "ldab\0" + /* 2997 */ "sxtab\0" + /* 3003 */ "uxtab\0" + /* 3009 */ "smlabb\0" + /* 3016 */ "smlalbb\0" + /* 3024 */ "smulbb\0" + /* 3031 */ "tbb\0" + /* 3035 */ "rfedb\0" + /* 3041 */ "vldmdb\0" + /* 3048 */ "vstmdb\0" + /* 3055 */ "srsdb\0" + /* 3061 */ "ldmib\0" + /* 3067 */ "stmib\0" + /* 3073 */ "vshllb\0" + /* 3080 */ "vqdmullb\0" + /* 3089 */ "vmullb\0" + /* 3096 */ "stlb\0" + /* 3101 */ "vmovlb\0" + /* 3108 */ "dmb\0" + /* 3112 */ "vqshrnb\0" + /* 3120 */ "vqrshrnb\0" + /* 3129 */ "vrshrnb\0" + /* 3137 */ "vshrnb\0" + /* 3144 */ "vqshrunb\0" + /* 3153 */ "vqrshrunb\0" + /* 3163 */ "vqmovunb\0" + /* 3172 */ "vqmovnb\0" + /* 3180 */ "vmovnb\0" + /* 3187 */ "swpb\0" + /* 3192 */ "vldrb\0" + /* 3198 */ "vstrb\0" + /* 3204 */ "dsb\0" + /* 3208 */ "isb\0" + /* 3212 */ "ldrsb\0" + /* 3218 */ "tsb\0" + /* 3222 */ "smlatb\0" + /* 3229 */ "pkhtb\0" + /* 3235 */ "smlaltb\0" + /* 3243 */ "smultb\0" + /* 3250 */ "vcvtb\0" + /* 3256 */ "sxtb\0" + /* 3261 */ "uxtb\0" + /* 3266 */ "qdsub\0" + /* 3272 */ "vhsub\0" + /* 3278 */ "vqsub\0" + /* 3284 */ "vsub\0" + /* 3289 */ "smlawb\0" + /* 3296 */ "smulwb\0" + /* 3303 */ "ldaexb\0" + /* 3310 */ "stlexb\0" + /* 3317 */ "ldrexb\0" + /* 3324 */ "strexb\0" + /* 3331 */ "vsbc\0" + /* 3336 */ "vadc\0" + /* 3341 */ "ldc\0" + /* 3345 */ "bfc\0" + /* 3349 */ "vbic\0" + /* 3354 */ "vshlc\0" + /* 3360 */ "smc\0" + /* 3364 */ "mrc\0" + /* 3368 */ "mrrc\0" + /* 3373 */ "rsc\0" + /* 3377 */ "stc\0" + /* 3381 */ "svc\0" + /* 3385 */ "smlad\0" + /* 3391 */ "smuad\0" + /* 3397 */ "vabd\0" + /* 3402 */ "vhcadd\0" + /* 3409 */ "vcadd\0" + /* 3415 */ "qdadd\0" + /* 3421 */ "vrhadd\0" + /* 3428 */ "vhadd\0" + /* 3434 */ "vpadd\0" + /* 3440 */ "vqadd\0" + /* 3446 */ "vadd\0" + /* 3451 */ "smlald\0" + /* 3458 */ "pld\0" + /* 3462 */ "smlsld\0" + /* 3469 */ "vand\0" + /* 3474 */ "vldrd\0" + /* 3480 */ "vstrd\0" + /* 3486 */ "smlsd\0" + /* 3492 */ "smusd\0" + /* 3498 */ "ldaexd\0" + /* 3505 */ "stlexd\0" + /* 3512 */ "ldrexd\0" + /* 3519 */ "strexd\0" + /* 3526 */ "vacge\0" + /* 3532 */ "vcge\0" + /* 3537 */ "vcle\0" + /* 3542 */ "vrecpe\0" + /* 3549 */ "vcmpe\0" + /* 3555 */ "vrsqrte\0" + /* 3563 */ "bf\0" + /* 3566 */ "vbif\0" + /* 3571 */ "dbg\0" + /* 3575 */ "pacg\0" + /* 3580 */ "vqneg\0" + /* 3586 */ "vneg\0" + /* 3591 */ "sg\0" + /* 3594 */ "autg\0" + /* 3599 */ "ldah\0" + /* 3604 */ "vqdmlah\0" + /* 3612 */ "vqrdmlah\0" + /* 3621 */ "sxtah\0" + /* 3627 */ "uxtah\0" + /* 3633 */ "tbh\0" + /* 3637 */ "vqdmladh\0" + /* 3646 */ "vqrdmladh\0" + /* 3656 */ "vqdmlsdh\0" + /* 3665 */ "vqrdmlsdh\0" + /* 3675 */ "stlh\0" + /* 3680 */ "vqdmulh\0" + /* 3688 */ "vqrdmulh\0" + /* 3697 */ "vrmulh\0" + /* 3704 */ "vmulh\0" + /* 3710 */ "vldrh\0" + /* 3716 */ "vstrh\0" + /* 3722 */ "vqdmlash\0" + /* 3731 */ "vqrdmlash\0" + /* 3741 */ "vqrdmlsh\0" + /* 3750 */ "ldrsh\0" + /* 3756 */ "push\0" + /* 3761 */ "revsh\0" + /* 3767 */ "sxth\0" + /* 3772 */ "uxth\0" + /* 3777 */ "vrmlaldavh\0" + /* 3788 */ "vrmlsldavh\0" + /* 3799 */ "ldaexh\0" + /* 3806 */ "stlexh\0" + /* 3813 */ "ldrexh\0" + /* 3820 */ "strexh\0" + /* 3827 */ "vsbci\0" + /* 3833 */ "vadci\0" + /* 3839 */ "bfi\0" + /* 3843 */ "pli\0" + /* 3847 */ "vsli\0" + /* 3852 */ "vsri\0" + /* 3857 */ "bxj\0" + /* 3861 */ "ldc2l\0" + /* 3867 */ "stc2l\0" + /* 3873 */ "umaal\0" + /* 3879 */ "vabal\0" + /* 3885 */ "vpadal\0" + /* 3892 */ "vqdmlal\0" + /* 3900 */ "smlal\0" + /* 3906 */ "umlal\0" + /* 3912 */ "vmlal\0" + /* 3918 */ "vtbl\0" + /* 3923 */ "vsubl\0" + /* 3929 */ "ldcl\0" + /* 3934 */ "stcl\0" + /* 3939 */ "vabdl\0" + /* 3945 */ "vpaddl\0" + /* 3952 */ "vaddl\0" + /* 3958 */ "vpsel\0" + /* 3964 */ "bfl\0" + /* 3968 */ "sqshl\0" + /* 3974 */ "uqshl\0" + /* 3980 */ "vqshl\0" + /* 3986 */ "uqrshl\0" + /* 3993 */ "vqrshl\0" + /* 4000 */ "vrshl\0" + /* 4006 */ "vshl\0" + /* 4011 */ "# FEntry call\0" + /* 4025 */ "sqshll\0" + /* 4032 */ "uqshll\0" + /* 4039 */ "uqrshll\0" + /* 4047 */ "vshll\0" + /* 4053 */ "lsll\0" + /* 4058 */ "vqdmull\0" + /* 4066 */ "smull\0" + /* 4072 */ "umull\0" + /* 4078 */ "vmull\0" + /* 4084 */ "sqrshrl\0" + /* 4092 */ "srshrl\0" + /* 4099 */ "urshrl\0" + /* 4106 */ "asrl\0" + /* 4111 */ "lsrl\0" + /* 4116 */ "vbsl\0" + /* 4121 */ "vqdmlsl\0" + /* 4129 */ "vmlsl\0" + /* 4135 */ "stl\0" + /* 4139 */ "vcmul\0" + /* 4145 */ "smmul\0" + /* 4151 */ "vnmul\0" + /* 4157 */ "vmul\0" + /* 4162 */ "vmovl\0" + /* 4168 */ "vlldm\0" + /* 4174 */ "vminnm\0" + /* 4181 */ "vmaxnm\0" + /* 4188 */ "vscclrm\0" + /* 4196 */ "vrintm\0" + /* 4203 */ "vlstm\0" + /* 4209 */ "vcvtm\0" + /* 4215 */ "vrsubhn\0" + /* 4223 */ "vsubhn\0" + /* 4230 */ "vraddhn\0" + /* 4238 */ "vaddhn\0" + /* 4245 */ "vpmin\0" + /* 4251 */ "vmin\0" + /* 4256 */ "cmn\0" + /* 4260 */ "vqshrn\0" + /* 4267 */ "vqrshrn\0" + /* 4275 */ "vrshrn\0" + /* 4282 */ "vshrn\0" + /* 4288 */ "vorn\0" + /* 4293 */ "vtrn\0" + /* 4298 */ "vrintn\0" + /* 4305 */ "vcvtn\0" + /* 4311 */ "vqshrun\0" + /* 4319 */ "vqrshrun\0" + /* 4328 */ "vqmovun\0" + /* 4336 */ "vmvn\0" + /* 4341 */ "vqmovn\0" + /* 4348 */ "vmovn\0" + /* 4354 */ "trap\0" + /* 4359 */ "cdp\0" + /* 4363 */ "vzip\0" + /* 4368 */ "vcmp\0" + /* 4373 */ "pop\0" + /* 4377 */ "pac\tr12, lr, sp\0" + /* 4393 */ "pacbti\tr12, lr, sp\0" + /* 4412 */ "aut\tr12, lr, sp\0" + /* 4428 */ "lctp\0" + /* 4433 */ "vctp\0" + /* 4438 */ "vrintp\0" + /* 4445 */ "vcvtp\0" + /* 4451 */ "vddup\0" + /* 4457 */ "vidup\0" + /* 4463 */ "vdup\0" + /* 4468 */ "vdwdup\0" + /* 4475 */ "viwdup\0" + /* 4482 */ "vswp\0" + /* 4487 */ "vuzp\0" + /* 4492 */ "vceq\0" + /* 4497 */ "teq\0" + /* 4501 */ "smmlar\0" + /* 4508 */ "mcr\0" + /* 4512 */ "adr\0" + /* 4516 */ "vldr\0" + /* 4521 */ "sqrshr\0" + /* 4528 */ "srshr\0" + /* 4534 */ "urshr\0" + /* 4540 */ "vrshr\0" + /* 4546 */ "vshr\0" + /* 4551 */ "smmulr\0" + /* 4558 */ "veor\0" + /* 4563 */ "ror\0" + /* 4567 */ "mcrr\0" + /* 4572 */ "vorr\0" + /* 4577 */ "asr\0" + /* 4581 */ "smmlsr\0" + /* 4588 */ "vmsr\0" + /* 4593 */ "vbrsr\0" + /* 4599 */ "vrintr\0" + /* 4606 */ "vstr\0" + /* 4611 */ "vcvtr\0" + /* 4617 */ "vmlas\0" + /* 4623 */ "vfmas\0" + /* 4629 */ "vqabs\0" + /* 4635 */ "vabs\0" + /* 4640 */ "subs\0" + /* 4645 */ "vcls\0" + /* 4650 */ "smmls\0" + /* 4656 */ "vnmls\0" + /* 4662 */ "vmls\0" + /* 4667 */ "vfms\0" + /* 4672 */ "vfnms\0" + /* 4678 */ "bxns\0" + /* 4683 */ "blxns\0" + /* 4689 */ "vrecps\0" + /* 4696 */ "vmrs\0" + /* 4701 */ "asrs\0" + /* 4706 */ "lsrs\0" + /* 4711 */ "vrsqrts\0" + /* 4719 */ "movs\0" + /* 4724 */ "ssat\0" + /* 4729 */ "usat\0" + /* 4734 */ "ttat\0" + /* 4739 */ "smlabt\0" + /* 4746 */ "pkhbt\0" + /* 4752 */ "smlalbt\0" + /* 4760 */ "smulbt\0" + /* 4767 */ "ldrbt\0" + /* 4773 */ "strbt\0" + /* 4779 */ "ldrsbt\0" + /* 4786 */ "eret\0" + /* 4791 */ "vacgt\0" + /* 4797 */ "vcgt\0" + /* 4802 */ "ldrht\0" + /* 4808 */ "strht\0" + /* 4814 */ "ldrsht\0" + /* 4821 */ "rbit\0" + /* 4826 */ "vbit\0" + /* 4831 */ "vclt\0" + /* 4836 */ "vshllt\0" + /* 4843 */ "vqdmullt\0" + /* 4852 */ "vmullt\0" + /* 4859 */ "vmovlt\0" + /* 4866 */ "vcnt\0" + /* 4871 */ "hint\0" + /* 4876 */ "vqshrnt\0" + /* 4884 */ "vqrshrnt\0" + /* 4893 */ "vrshrnt\0" + /* 4901 */ "vshrnt\0" + /* 4908 */ "vqshrunt\0" + /* 4917 */ "vqrshrunt\0" + /* 4927 */ "vqmovunt\0" + /* 4936 */ "vqmovnt\0" + /* 4944 */ "vmovnt\0" + /* 4951 */ "vpnot\0" + /* 4957 */ "vpt\0" + /* 4961 */ "ldrt\0" + /* 4966 */ "vsqrt\0" + /* 4972 */ "strt\0" + /* 4977 */ "vpst\0" + /* 4982 */ "vtst\0" + /* 4987 */ "smlatt\0" + /* 4994 */ "smlaltt\0" + /* 5002 */ "smultt\0" + /* 5009 */ "ttt\0" + /* 5013 */ "vcvtt\0" + /* 5019 */ "bxaut\0" + /* 5025 */ "vjcvt\0" + /* 5031 */ "vcvt\0" + /* 5036 */ "movt\0" + /* 5041 */ "smlawt\0" + /* 5048 */ "smulwt\0" + /* 5055 */ "vext\0" + /* 5060 */ "vqshlu\0" + /* 5067 */ "vabav\0" + /* 5073 */ "vmladav\0" + /* 5081 */ "vmlaldav\0" + /* 5090 */ "vmlsldav\0" + /* 5099 */ "vmlsdav\0" + /* 5107 */ "vminnmav\0" + /* 5116 */ "vmaxnmav\0" + /* 5125 */ "vminav\0" + /* 5132 */ "vmaxav\0" + /* 5139 */ "vaddv\0" + /* 5145 */ "rev\0" + /* 5149 */ "sdiv\0" + /* 5154 */ "udiv\0" + /* 5159 */ "vdiv\0" + /* 5164 */ "vaddlv\0" + /* 5171 */ "vminnmv\0" + /* 5179 */ "vmaxnmv\0" + /* 5187 */ "vminv\0" + /* 5193 */ "vmov\0" + /* 5198 */ "vmaxv\0" + /* 5204 */ "vsubw\0" + /* 5210 */ "vaddw\0" + /* 5216 */ "pldw\0" + /* 5221 */ "vldrw\0" + /* 5227 */ "vstrw\0" + /* 5233 */ "movw\0" + /* 5238 */ "vrmlaldavhax\0" + /* 5251 */ "vrmlsldavhax\0" + /* 5264 */ "fldmiax\0" + /* 5272 */ "fstmiax\0" + /* 5280 */ "vpmax\0" + /* 5286 */ "vmax\0" + /* 5291 */ "shsax\0" + /* 5297 */ "uhsax\0" + /* 5303 */ "uqsax\0" + /* 5309 */ "ssax\0" + /* 5314 */ "usax\0" + /* 5319 */ "vmladavax\0" + /* 5329 */ "vmlaldavax\0" + /* 5340 */ "vmlsldavax\0" + /* 5351 */ "vmlsdavax\0" + /* 5361 */ "fldmdbx\0" + /* 5369 */ "fstmdbx\0" + /* 5377 */ "vtbx\0" + /* 5382 */ "smladx\0" + /* 5389 */ "smuadx\0" + /* 5396 */ "smlaldx\0" + /* 5404 */ "smlsldx\0" + /* 5412 */ "smlsdx\0" + /* 5419 */ "smusdx\0" + /* 5426 */ "ldaex\0" + /* 5432 */ "stlex\0" + /* 5438 */ "ldrex\0" + /* 5444 */ "clrex\0" + /* 5450 */ "strex\0" + /* 5456 */ "sbfx\0" + /* 5461 */ "ubfx\0" + /* 5466 */ "vqdmladhx\0" + /* 5476 */ "vqrdmladhx\0" + /* 5487 */ "vqdmlsdhx\0" + /* 5497 */ "vqrdmlsdhx\0" + /* 5508 */ "vrmlaldavhx\0" + /* 5520 */ "vrmlsldavhx\0" + /* 5532 */ "blx\0" + /* 5536 */ "bflx\0" + /* 5541 */ "rrx\0" + /* 5545 */ "shasx\0" + /* 5551 */ "uhasx\0" + /* 5557 */ "uqasx\0" + /* 5563 */ "sasx\0" + /* 5568 */ "uasx\0" + /* 5573 */ "vrintx\0" + /* 5580 */ "vmladavx\0" + /* 5589 */ "vmlaldavx\0" + /* 5599 */ "vmlsldavx\0" + /* 5609 */ "vmlsdavx\0" + /* 5618 */ "vclz\0" + /* 5623 */ "vrintz\0" + }; +#endif // CAPSTONE_DIET + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 2671U, // DBG_VALUE + 2728U, // DBG_VALUE_LIST + 2681U, // DBG_INSTR_REF + 2695U, // DBG_PHI + 2703U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 2664U, // BUNDLE + 2713U, // LIFETIME_START + 2638U, // LIFETIME_END + 2651U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 4012U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 2230U, // PATCHABLE_FUNCTION_ENTER + 2150U, // PATCHABLE_RET + 2276U, // PATCHABLE_FUNCTION_EXIT + 2253U, // PATCHABLE_TAIL_CALL + 2205U, // PATCHABLE_EVENT_CALL + 2181U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // MEMBARRIER + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ASSERT_ALIGN + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_FPTRUNC_ROUND + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_ATOMICRMW_FMAX + 0U, // G_ATOMICRMW_FMIN + 0U, // G_ATOMICRMW_UINC_WRAP + 0U, // G_ATOMICRMW_UDEC_WRAP + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INVOKE_REGION_START + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_IS_FPCLASS + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ABS + 0U, // ADDSri + 0U, // ADDSrr + 0U, // ADDSrsi + 0U, // ADDSrsr + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 12770U, // ASRi + 12770U, // ASRr + 0U, // B + 0U, // BCCZi64 + 0U, // BCCi64 + 0U, // BLX_noip + 0U, // BLX_pred_noip + 0U, // BL_PUSHLR + 0U, // BMOVPCB_CALL + 0U, // BMOVPCRX_CALL + 0U, // BR_JTadd + 0U, // BR_JTm_i12 + 0U, // BR_JTm_rs + 0U, // BR_JTr + 0U, // BX_CALL + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_STRUCT_BYVAL_I32 + 67130072U, // ITasm + 0U, // Int_eh_sjlj_dispatchsetup + 0U, // Int_eh_sjlj_longjmp + 0U, // Int_eh_sjlj_setjmp + 0U, // Int_eh_sjlj_setjmp_nofp + 0U, // Int_eh_sjlj_setup_dispatch + 0U, // JUMPTABLE_ADDRS + 0U, // JUMPTABLE_INSTS + 0U, // JUMPTABLE_TBB + 0U, // JUMPTABLE_TBH + 0U, // LDMIA_RET + 29344U, // LDRBT_POST + 29094U, // LDRConstPool + 29379U, // LDRHTii + 0U, // LDRLIT_ga_abs + 0U, // LDRLIT_ga_pcrel + 0U, // LDRLIT_ga_pcrel_ldr + 29356U, // LDRSBTii + 29391U, // LDRSHTii + 29538U, // LDRT_POST + 0U, // LEApcrel + 0U, // LEApcrelJT + 0U, // LOADDUAL + 12318U, // LSLi + 12318U, // LSLr + 12777U, // LSRi + 12777U, // LSRr + 0U, // MEMCPY + 0U, // MLAv5 + 0U, // MOVCCi + 0U, // MOVCCi16 + 0U, // MOVCCi32imm + 0U, // MOVCCr + 0U, // MOVCCsi + 0U, // MOVCCsr + 0U, // MOVPCRX + 0U, // MOVTi16_ga_pcrel + 0U, // MOV_ga_pcrel + 0U, // MOV_ga_pcrel_ldr + 0U, // MOVi16_ga_pcrel + 0U, // MOVi32imm + 0U, // MOVsra_flag + 0U, // MOVsrl_flag + 0U, // MQPRCopy + 0U, // MQQPRLoad + 0U, // MQQPRStore + 0U, // MQQQQPRLoad + 0U, // MQQQQPRStore + 0U, // MULv5 + 0U, // MVE_MEMCPYLOOPINST + 0U, // MVE_MEMSETLOOPINST + 0U, // MVNCCi + 0U, // PICADD + 0U, // PICLDR + 0U, // PICLDRB + 0U, // PICLDRH + 0U, // PICLDRSB + 0U, // PICLDRSH + 0U, // PICSTR + 0U, // PICSTRB + 0U, // PICSTRH + 12756U, // RORi + 12756U, // RORr + 0U, // RRX + 38310U, // RRXi + 0U, // RSBSri + 0U, // RSBSrsi + 0U, // RSBSrsr + 0U, // SEH_EpilogEnd + 0U, // SEH_EpilogStart + 0U, // SEH_Nop + 0U, // SEH_Nop_Ret + 0U, // SEH_PrologEnd + 0U, // SEH_SaveFRegs + 0U, // SEH_SaveLR + 0U, // SEH_SaveRegs + 0U, // SEH_SaveRegs_Ret + 0U, // SEH_SaveSP + 0U, // SEH_StackAlloc + 0U, // SMLALv5 + 0U, // SMULLv5 + 0U, // SPACE + 0U, // STOREDUAL + 29350U, // STRBT_POST + 0U, // STRBi_preidx + 0U, // STRBr_preidx + 0U, // STRH_preidx + 29549U, // STRT_POST + 0U, // STRi_preidx + 0U, // STRr_preidx + 0U, // SUBS_PC_LR + 0U, // SUBSri + 0U, // SUBSrr + 0U, // SUBSrsi + 0U, // SUBSrsr + 0U, // SpeculationBarrierISBDSBEndBB + 0U, // SpeculationBarrierSBEndBB + 0U, // TAILJMPd + 0U, // TAILJMPr + 0U, // TAILJMPr4 + 0U, // TCRETURNdi + 0U, // TCRETURNri + 0U, // TPsoft + 0U, // UMLALv5 + 0U, // UMULLv5 + 567556U, // VLD1LNdAsm_16 + 1091844U, // VLD1LNdAsm_32 + 1616132U, // VLD1LNdAsm_8 + 567556U, // VLD1LNdWB_fixed_Asm_16 + 1091844U, // VLD1LNdWB_fixed_Asm_32 + 1616132U, // VLD1LNdWB_fixed_Asm_8 + 575748U, // VLD1LNdWB_register_Asm_16 + 1100036U, // VLD1LNdWB_register_Asm_32 + 1624324U, // VLD1LNdWB_register_Asm_8 + 567605U, // VLD2LNdAsm_16 + 1091893U, // VLD2LNdAsm_32 + 1616181U, // VLD2LNdAsm_8 + 567605U, // VLD2LNdWB_fixed_Asm_16 + 1091893U, // VLD2LNdWB_fixed_Asm_32 + 1616181U, // VLD2LNdWB_fixed_Asm_8 + 575797U, // VLD2LNdWB_register_Asm_16 + 1100085U, // VLD2LNdWB_register_Asm_32 + 1624373U, // VLD2LNdWB_register_Asm_8 + 567605U, // VLD2LNqAsm_16 + 1091893U, // VLD2LNqAsm_32 + 567605U, // VLD2LNqWB_fixed_Asm_16 + 1091893U, // VLD2LNqWB_fixed_Asm_32 + 575797U, // VLD2LNqWB_register_Asm_16 + 1100085U, // VLD2LNqWB_register_Asm_32 + 134801754U, // VLD3DUPdAsm_16 + 135326042U, // VLD3DUPdAsm_32 + 135850330U, // VLD3DUPdAsm_8 + 134801754U, // VLD3DUPdWB_fixed_Asm_16 + 135326042U, // VLD3DUPdWB_fixed_Asm_32 + 135850330U, // VLD3DUPdWB_fixed_Asm_8 + 134785370U, // VLD3DUPdWB_register_Asm_16 + 135309658U, // VLD3DUPdWB_register_Asm_32 + 135833946U, // VLD3DUPdWB_register_Asm_8 + 201910618U, // VLD3DUPqAsm_16 + 202434906U, // VLD3DUPqAsm_32 + 202959194U, // VLD3DUPqAsm_8 + 201910618U, // VLD3DUPqWB_fixed_Asm_16 + 202434906U, // VLD3DUPqWB_fixed_Asm_32 + 202959194U, // VLD3DUPqWB_fixed_Asm_8 + 201894234U, // VLD3DUPqWB_register_Asm_16 + 202418522U, // VLD3DUPqWB_register_Asm_32 + 202942810U, // VLD3DUPqWB_register_Asm_8 + 567642U, // VLD3LNdAsm_16 + 1091930U, // VLD3LNdAsm_32 + 1616218U, // VLD3LNdAsm_8 + 567642U, // VLD3LNdWB_fixed_Asm_16 + 1091930U, // VLD3LNdWB_fixed_Asm_32 + 1616218U, // VLD3LNdWB_fixed_Asm_8 + 575834U, // VLD3LNdWB_register_Asm_16 + 1100122U, // VLD3LNdWB_register_Asm_32 + 1624410U, // VLD3LNdWB_register_Asm_8 + 567642U, // VLD3LNqAsm_16 + 1091930U, // VLD3LNqAsm_32 + 567642U, // VLD3LNqWB_fixed_Asm_16 + 1091930U, // VLD3LNqWB_fixed_Asm_32 + 575834U, // VLD3LNqWB_register_Asm_16 + 1100122U, // VLD3LNqWB_register_Asm_32 + 269019482U, // VLD3dAsm_16 + 269543770U, // VLD3dAsm_32 + 270068058U, // VLD3dAsm_8 + 269019482U, // VLD3dWB_fixed_Asm_16 + 269543770U, // VLD3dWB_fixed_Asm_32 + 270068058U, // VLD3dWB_fixed_Asm_8 + 269003098U, // VLD3dWB_register_Asm_16 + 269527386U, // VLD3dWB_register_Asm_32 + 270051674U, // VLD3dWB_register_Asm_8 + 336128346U, // VLD3qAsm_16 + 336652634U, // VLD3qAsm_32 + 337176922U, // VLD3qAsm_8 + 336128346U, // VLD3qWB_fixed_Asm_16 + 336652634U, // VLD3qWB_fixed_Asm_32 + 337176922U, // VLD3qWB_fixed_Asm_8 + 336111962U, // VLD3qWB_register_Asm_16 + 336636250U, // VLD3qWB_register_Asm_32 + 337160538U, // VLD3qWB_register_Asm_8 + 403237238U, // VLD4DUPdAsm_16 + 403761526U, // VLD4DUPdAsm_32 + 404285814U, // VLD4DUPdAsm_8 + 403237238U, // VLD4DUPdWB_fixed_Asm_16 + 403761526U, // VLD4DUPdWB_fixed_Asm_32 + 404285814U, // VLD4DUPdWB_fixed_Asm_8 + 403220854U, // VLD4DUPdWB_register_Asm_16 + 403745142U, // VLD4DUPdWB_register_Asm_32 + 404269430U, // VLD4DUPdWB_register_Asm_8 + 470346102U, // VLD4DUPqAsm_16 + 470870390U, // VLD4DUPqAsm_32 + 471394678U, // VLD4DUPqAsm_8 + 470346102U, // VLD4DUPqWB_fixed_Asm_16 + 470870390U, // VLD4DUPqWB_fixed_Asm_32 + 471394678U, // VLD4DUPqWB_fixed_Asm_8 + 470329718U, // VLD4DUPqWB_register_Asm_16 + 470854006U, // VLD4DUPqWB_register_Asm_32 + 471378294U, // VLD4DUPqWB_register_Asm_8 + 567670U, // VLD4LNdAsm_16 + 1091958U, // VLD4LNdAsm_32 + 1616246U, // VLD4LNdAsm_8 + 567670U, // VLD4LNdWB_fixed_Asm_16 + 1091958U, // VLD4LNdWB_fixed_Asm_32 + 1616246U, // VLD4LNdWB_fixed_Asm_8 + 575862U, // VLD4LNdWB_register_Asm_16 + 1100150U, // VLD4LNdWB_register_Asm_32 + 1624438U, // VLD4LNdWB_register_Asm_8 + 567670U, // VLD4LNqAsm_16 + 1091958U, // VLD4LNqAsm_32 + 567670U, // VLD4LNqWB_fixed_Asm_16 + 1091958U, // VLD4LNqWB_fixed_Asm_32 + 575862U, // VLD4LNqWB_register_Asm_16 + 1100150U, // VLD4LNqWB_register_Asm_32 + 537454966U, // VLD4dAsm_16 + 537979254U, // VLD4dAsm_32 + 538503542U, // VLD4dAsm_8 + 537454966U, // VLD4dWB_fixed_Asm_16 + 537979254U, // VLD4dWB_fixed_Asm_32 + 538503542U, // VLD4dWB_fixed_Asm_8 + 537438582U, // VLD4dWB_register_Asm_16 + 537962870U, // VLD4dWB_register_Asm_32 + 538487158U, // VLD4dWB_register_Asm_8 + 604563830U, // VLD4qAsm_16 + 605088118U, // VLD4qAsm_32 + 605612406U, // VLD4qAsm_8 + 604563830U, // VLD4qWB_fixed_Asm_16 + 605088118U, // VLD4qWB_fixed_Asm_32 + 605612406U, // VLD4qWB_fixed_Asm_8 + 604547446U, // VLD4qWB_register_Asm_16 + 605071734U, // VLD4qWB_register_Asm_32 + 605596022U, // VLD4qWB_register_Asm_8 + 0U, // VMOVD0 + 0U, // VMOVDcc + 0U, // VMOVHcc + 0U, // VMOVQ0 + 0U, // VMOVScc + 567567U, // VST1LNdAsm_16 + 1091855U, // VST1LNdAsm_32 + 1616143U, // VST1LNdAsm_8 + 567567U, // VST1LNdWB_fixed_Asm_16 + 1091855U, // VST1LNdWB_fixed_Asm_32 + 1616143U, // VST1LNdWB_fixed_Asm_8 + 575759U, // VST1LNdWB_register_Asm_16 + 1100047U, // VST1LNdWB_register_Asm_32 + 1624335U, // VST1LNdWB_register_Asm_8 + 567632U, // VST2LNdAsm_16 + 1091920U, // VST2LNdAsm_32 + 1616208U, // VST2LNdAsm_8 + 567632U, // VST2LNdWB_fixed_Asm_16 + 1091920U, // VST2LNdWB_fixed_Asm_32 + 1616208U, // VST2LNdWB_fixed_Asm_8 + 575824U, // VST2LNdWB_register_Asm_16 + 1100112U, // VST2LNdWB_register_Asm_32 + 1624400U, // VST2LNdWB_register_Asm_8 + 567632U, // VST2LNqAsm_16 + 1091920U, // VST2LNqAsm_32 + 567632U, // VST2LNqWB_fixed_Asm_16 + 1091920U, // VST2LNqWB_fixed_Asm_32 + 575824U, // VST2LNqWB_register_Asm_16 + 1100112U, // VST2LNqWB_register_Asm_32 + 567653U, // VST3LNdAsm_16 + 1091941U, // VST3LNdAsm_32 + 1616229U, // VST3LNdAsm_8 + 567653U, // VST3LNdWB_fixed_Asm_16 + 1091941U, // VST3LNdWB_fixed_Asm_32 + 1616229U, // VST3LNdWB_fixed_Asm_8 + 575845U, // VST3LNdWB_register_Asm_16 + 1100133U, // VST3LNdWB_register_Asm_32 + 1624421U, // VST3LNdWB_register_Asm_8 + 567653U, // VST3LNqAsm_16 + 1091941U, // VST3LNqAsm_32 + 567653U, // VST3LNqWB_fixed_Asm_16 + 1091941U, // VST3LNqWB_fixed_Asm_32 + 575845U, // VST3LNqWB_register_Asm_16 + 1100133U, // VST3LNqWB_register_Asm_32 + 269019493U, // VST3dAsm_16 + 269543781U, // VST3dAsm_32 + 270068069U, // VST3dAsm_8 + 269019493U, // VST3dWB_fixed_Asm_16 + 269543781U, // VST3dWB_fixed_Asm_32 + 270068069U, // VST3dWB_fixed_Asm_8 + 269003109U, // VST3dWB_register_Asm_16 + 269527397U, // VST3dWB_register_Asm_32 + 270051685U, // VST3dWB_register_Asm_8 + 336128357U, // VST3qAsm_16 + 336652645U, // VST3qAsm_32 + 337176933U, // VST3qAsm_8 + 336128357U, // VST3qWB_fixed_Asm_16 + 336652645U, // VST3qWB_fixed_Asm_32 + 337176933U, // VST3qWB_fixed_Asm_8 + 336111973U, // VST3qWB_register_Asm_16 + 336636261U, // VST3qWB_register_Asm_32 + 337160549U, // VST3qWB_register_Asm_8 + 567675U, // VST4LNdAsm_16 + 1091963U, // VST4LNdAsm_32 + 1616251U, // VST4LNdAsm_8 + 567675U, // VST4LNdWB_fixed_Asm_16 + 1091963U, // VST4LNdWB_fixed_Asm_32 + 1616251U, // VST4LNdWB_fixed_Asm_8 + 575867U, // VST4LNdWB_register_Asm_16 + 1100155U, // VST4LNdWB_register_Asm_32 + 1624443U, // VST4LNdWB_register_Asm_8 + 567675U, // VST4LNqAsm_16 + 1091963U, // VST4LNqAsm_32 + 567675U, // VST4LNqWB_fixed_Asm_16 + 1091963U, // VST4LNqWB_fixed_Asm_32 + 575867U, // VST4LNqWB_register_Asm_16 + 1100155U, // VST4LNqWB_register_Asm_32 + 537454971U, // VST4dAsm_16 + 537979259U, // VST4dAsm_32 + 538503547U, // VST4dAsm_8 + 537454971U, // VST4dWB_fixed_Asm_16 + 537979259U, // VST4dWB_fixed_Asm_32 + 538503547U, // VST4dWB_fixed_Asm_8 + 537438587U, // VST4dWB_register_Asm_16 + 537962875U, // VST4dWB_register_Asm_32 + 538487163U, // VST4dWB_register_Asm_8 + 604563835U, // VST4qAsm_16 + 605088123U, // VST4qAsm_32 + 605612411U, // VST4qAsm_8 + 604563835U, // VST4qWB_fixed_Asm_16 + 605088123U, // VST4qWB_fixed_Asm_32 + 605612411U, // VST4qWB_fixed_Asm_8 + 604547451U, // VST4qWB_register_Asm_16 + 605071739U, // VST4qWB_register_Asm_32 + 605596027U, // VST4qWB_register_Asm_8 + 0U, // WIN__CHKSTK + 0U, // WIN__DBZCHK + 0U, // t2ABS + 0U, // t2ADDSri + 0U, // t2ADDSrr + 0U, // t2ADDSrs + 0U, // t2BF_LabelPseudo + 0U, // t2BR_JT + 0U, // t2CALL_BTI + 0U, // t2DoLoopStart + 0U, // t2DoLoopStartTP + 0U, // t2LDMIA_RET + 27770U, // t2LDRBpcrel + 29094U, // t2LDRConstPool + 28288U, // t2LDRHpcrel + 0U, // t2LDRLIT_ga_pcrel + 27789U, // t2LDRSBpcrel + 28327U, // t2LDRSHpcrel + 673247654U, // t2LDR_POST_imm + 740356518U, // t2LDR_PRE_imm + 0U, // t2LDRpci_pic + 29094U, // t2LDRpcrel + 0U, // t2LEApcrel + 0U, // t2LEApcrelJT + 0U, // t2LoopDec + 0U, // t2LoopEnd + 0U, // t2LoopEndDec + 0U, // t2MOVCCasr + 0U, // t2MOVCCi + 0U, // t2MOVCCi16 + 0U, // t2MOVCCi32imm + 0U, // t2MOVCClsl + 0U, // t2MOVCClsr + 0U, // t2MOVCCr + 0U, // t2MOVCCror + 62064U, // t2MOVSsi + 45680U, // t2MOVSsr + 0U, // t2MOVTi16_ga_pcrel + 0U, // t2MOV_ga_pcrel + 0U, // t2MOVi16_ga_pcrel + 0U, // t2MOVi32imm + 62539U, // t2MOVsi + 46155U, // t2MOVsr + 0U, // t2MVNCCi + 0U, // t2RSBSri + 0U, // t2RSBSrs + 0U, // t2STRB_preidx + 0U, // t2STRH_preidx + 673247744U, // t2STR_POST_imm + 740356608U, // t2STR_PRE_imm + 0U, // t2STR_preidx + 0U, // t2SUBSri + 0U, // t2SUBSrr + 0U, // t2SUBSrs + 0U, // t2SpeculationBarrierISBDSBEndBB + 0U, // t2SpeculationBarrierSBEndBB + 0U, // t2TBB_JT + 0U, // t2TBH_JT + 0U, // t2WhileLoopSetup + 0U, // t2WhileLoopStart + 0U, // t2WhileLoopStartLR + 0U, // t2WhileLoopStartTP + 0U, // tADCS + 0U, // tADDSi3 + 0U, // tADDSi8 + 0U, // tADDSrr + 0U, // tADDframe + 0U, // tADJCALLSTACKDOWN + 0U, // tADJCALLSTACKUP + 0U, // tBLXNS_CALL + 0U, // tBLXr_noip + 0U, // tBL_PUSHLR + 0U, // tBRIND + 0U, // tBR_JTr + 0U, // tBXNS_RET + 0U, // tBX_CALL + 0U, // tBX_RET + 0U, // tBX_RET_vararg + 0U, // tBfar + 0U, // tCMP_SWAP_16 + 0U, // tCMP_SWAP_32 + 0U, // tCMP_SWAP_8 + 0U, // tLDMIA_UPD + 29094U, // tLDRConstPool + 0U, // tLDRLIT_ga_abs + 0U, // tLDRLIT_ga_pcrel + 0U, // tLDR_postidx + 0U, // tLDRpci_pic + 0U, // tLEApcrel + 0U, // tLEApcrelJT + 0U, // tLSLSri + 0U, // tMOVCCr_pseudo + 0U, // tPOP_RET + 0U, // tRSBS + 0U, // tSBCS + 0U, // tSUBSi3 + 0U, // tSUBSi8 + 0U, // tSUBSrr + 0U, // tTAILJMPd + 0U, // tTAILJMPdND + 0U, // tTAILJMPr + 0U, // tTBB_JT + 0U, // tTBH_JT + 0U, // tTPsoft + 2632970U, // ADCri + 2632970U, // ADCrr + 2690314U, // ADCrsi + 77066U, // ADCrsr + 2633038U, // ADDri + 2633038U, // ADDrr + 2690382U, // ADDrsi + 77134U, // ADDrsr + 2650529U, // ADR + 808535656U, // AESD + 808535664U, // AESE + 875644501U, // AESIMC + 875644511U, // AESMC + 2633103U, // ANDri + 2633103U, // ANDrr + 2690447U, // ANDrsi + 77199U, // ANDrsr + 808543710U, // BF16VDOTI_VDOTD + 808543710U, // BF16VDOTI_VDOTQ + 808543710U, // BF16VDOTS_VDOTD + 808543710U, // BF16VDOTS_VDOTQ + 876114856U, // BF16_VCVT + 809036979U, // BF16_VCVTB + 809038742U, // BF16_VCVTT + 2682130U, // BFC + 2666240U, // BFI + 2632983U, // BICri + 2632983U, // BICrr + 2690327U, // BICrsi + 77079U, // BICrsr + 4278212U, // BKPT + 4294544U, // BL + 4278266U, // BLX + 2733469U, // BLX_pred + 4294650U, // BLXi + 942255953U, // BL_pred + 4278262U, // BX + 2731794U, // BXJ + 4838647U, // BX_RET + 2733303U, // BX_pred + 942255028U, // Bcc + 810672130U, // CDE_CX1 + 1009298104U, // CDE_CX1A + 1079633720U, // CDE_CX1D + 1009298126U, // CDE_CX1DA + 810672723U, // CDE_CX2 + 1009306302U, // CDE_CX2A + 1146742590U, // CDE_CX2D + 1009306324U, // CDE_CX2DA + 810672729U, // CDE_CX3 + 1009388228U, // CDE_CX3A + 1146742596U, // CDE_CX3D + 1009388250U, // CDE_CX3DA + 1213327062U, // CDE_VCX1A_fpdp + 1213327062U, // CDE_VCX1A_fpsp + 1009396407U, // CDE_VCX1A_vec + 810672129U, // CDE_VCX1_fpdp + 810672129U, // CDE_VCX1_fpsp + 1009404180U, // CDE_VCX1_vec + 1213327069U, // CDE_VCX2A_fpdp + 1213327069U, // CDE_VCX2A_fpsp + 1009412797U, // CDE_VCX2A_vec + 810672722U, // CDE_VCX2_fpdp + 810672722U, // CDE_VCX2_fpsp + 1009396053U, // CDE_VCX2_vec + 1213327076U, // CDE_VCX3A_fpdp + 1213327076U, // CDE_VCX3A_fpsp + 1009420995U, // CDE_VCX3A_vec + 810672728U, // CDE_VCX3_fpdp + 810672728U, // CDE_VCX3_fpsp + 1009412458U, // CDE_VCX3_vec + 1277825288U, // CDP + 1348641343U, // CDP2 + 5445U, // CLREX + 2651636U, // CLZ + 2650273U, // CMNri + 2650273U, // CMNzrr + 2683041U, // CMNzrsi + 2666657U, // CMNzrsr + 2650386U, // CMPri + 2650386U, // CMPrr + 2683154U, // CMPrsi + 2666770U, // CMPrsr + 4278196U, // CPS1p + 1412092501U, // CPS2p + 1412092501U, // CPS3p + 875644665U, // CRC32B + 875644673U, // CRC32CB + 875644783U, // CRC32CH + 875644903U, // CRC32CW + 875644775U, // CRC32H + 875644895U, // CRC32W + 2731508U, // DBG + 190232U, // DMB + 190237U, // DSB + 2634192U, // EORri + 2634192U, // EORrr + 2691536U, // EORrsi + 78288U, // EORrsr + 4313779U, // ERET + 1147696202U, // FCONSTD + 7369802U, // FCONSTH + 7894090U, // FCONSTS + 875066610U, // FLDMXDB_UPD + 2733201U, // FLDMXIA + 875066513U, // FLDMXIA_UPD + 8507993U, // FMSTAT + 875066618U, // FSTMXDB_UPD + 2733209U, // FSTMXIA + 875066521U, // FSTMXIA_UPD + 2732808U, // HINT + 4278207U, // HLT + 4278067U, // HVC + 198434U, // ISB + 2648800U, // LDA + 2649009U, // LDAB + 2651443U, // LDAEX + 2649320U, // LDAEXB + 1479044523U, // LDAEXD + 2649816U, // LDAEXH + 2649616U, // LDAH + 1552590722U, // LDC2L_OFFSET + 1619699586U, // LDC2L_OPTION + 1619699586U, // LDC2L_POST + 9561986U, // LDC2L_PRE + 1552589350U, // LDC2_OFFSET + 1619698214U, // LDC2_OPTION + 1619698214U, // LDC2_POST + 9560614U, // LDC2_PRE + 1277734746U, // LDCL_OFFSET + 1277734746U, // LDCL_OPTION + 1277734746U, // LDCL_POST + 1009307482U, // LDCL_PRE + 1277734158U, // LDC_OFFSET + 1277734158U, // LDC_OPTION + 1277734158U, // LDC_POST + 1009306894U, // LDC_PRE + 2730724U, // LDMDA + 875064036U, // LDMDA_UPD + 2730979U, // LDMDB + 875064291U, // LDMDB_UPD + 2732107U, // LDMIA + 875065419U, // LDMIA_UPD + 2730998U, // LDMIB + 875064310U, // LDMIB_UPD + 2675360U, // LDRBT_POST_IMM + 2675360U, // LDRBT_POST_REG + 2673786U, // LDRB_POST_IMM + 2673786U, // LDRB_POST_REG + 2665594U, // LDRB_PRE_IMM + 2673786U, // LDRB_PRE_REG + 2681978U, // LDRBi12 + 2665594U, // LDRBrs + 2674068U, // LDRD + 2755988U, // LDRD_POST + 2755988U, // LDRD_PRE + 2651455U, // LDREX + 2649334U, // LDREXB + 1479044537U, // LDREXD + 2649830U, // LDREXH + 2666112U, // LDRH + 2667203U, // LDRHTi + 2675395U, // LDRHTr + 2674304U, // LDRH_POST + 2674304U, // LDRH_PRE + 2665613U, // LDRSB + 2667180U, // LDRSBTi + 2675372U, // LDRSBTr + 2673805U, // LDRSB_POST + 2673805U, // LDRSB_PRE + 2666151U, // LDRSH + 2667215U, // LDRSHTi + 2675407U, // LDRSHTr + 2674343U, // LDRSH_POST + 2674343U, // LDRSH_PRE + 2675554U, // LDRT_POST_IMM + 2675554U, // LDRT_POST_REG + 2675110U, // LDR_POST_IMM + 2675110U, // LDR_POST_REG + 2666918U, // LDR_PRE_IMM + 2675110U, // LDR_PRE_REG + 2683302U, // LDRcp + 2683302U, // LDRi12 + 2666918U, // LDRrs + 1277825437U, // MCR + 811770437U, // MCR2 + 1277743576U, // MCRR + 811770443U, // MCRR2 + 2689828U, // MLA + 2667053U, // MLS + 10081355U, // MOVPCLR + 2683821U, // MOVTi16 + 2659403U, // MOVi + 2651250U, // MOVi16 + 2659403U, // MOVr + 2659403U, // MOVr_TC + 2634827U, // MOVsi + 2692171U, // MOVsr + 1009388837U, // MRC + 10609196U, // MRC2 + 1680395561U, // MRRC + 205362U, // MRRC2 + 2732634U, // MRS + 2650714U, // MRSbanked + 2732634U, // MRSsys + 1747481070U, // MSR + 1814589934U, // MSRbanked + 1747481070U, // MSRi + 2633774U, // MUL + 2674699U, // MVE_ASRLi + 2674699U, // MVE_ASRLr + 875643877U, // MVE_DLSTP_16 + 875643124U, // MVE_DLSTP_32 + 875643486U, // MVE_DLSTP_64 + 875644536U, // MVE_DLSTP_8 + 1076482381U, // MVE_LCTP + 1882285988U, // MVE_LETP + 2674646U, // MVE_LSLLi + 2674646U, // MVE_LSLLr + 2674704U, // MVE_LSRL + 875098538U, // MVE_SQRSHR + 2756597U, // MVE_SQRSHRL + 875097985U, // MVE_SQSHL + 2674618U, // MVE_SQSHLL + 875098545U, // MVE_SRSHR + 2674685U, // MVE_SRSHRL + 875098003U, // MVE_UQRSHL + 2756552U, // MVE_UQRSHLL + 875097991U, // MVE_UQSHL + 2674625U, // MVE_UQSHLL + 875098551U, // MVE_URSHR + 2674692U, // MVE_URSHRL + 11154380U, // MVE_VABAVs16 + 11678668U, // MVE_VABAVs32 + 12202956U, // MVE_VABAVs8 + 12727244U, // MVE_VABAVu16 + 13251532U, // MVE_VABAVu32 + 13775820U, // MVE_VABAVu8 + 7490886U, // MVE_VABDf16 + 8015174U, // MVE_VABDf32 + 11160902U, // MVE_VABDs16 + 11685190U, // MVE_VABDs32 + 12209478U, // MVE_VABDs8 + 12733766U, // MVE_VABDu16 + 13258054U, // MVE_VABDu32 + 13782342U, // MVE_VABDu8 + 7557660U, // MVE_VABSf16 + 8081948U, // MVE_VABSf32 + 11227676U, // MVE_VABSs16 + 11751964U, // MVE_VABSs32 + 12276252U, // MVE_VABSs8 + 14314761U, // MVE_VADC + 14298874U, // MVE_VADCI + 11692963U, // MVE_VADDLVs32acc + 11686957U, // MVE_VADDLVs32no_acc + 13265827U, // MVE_VADDLVu32acc + 13259821U, // MVE_VADDLVu32no_acc + 11160476U, // MVE_VADDVs16acc + 11228180U, // MVE_VADDVs16no_acc + 11684764U, // MVE_VADDVs32acc + 11752468U, // MVE_VADDVs32no_acc + 12209052U, // MVE_VADDVs8acc + 12276756U, // MVE_VADDVs8no_acc + 12733340U, // MVE_VADDVu16acc + 12801044U, // MVE_VADDVu16no_acc + 13257628U, // MVE_VADDVu32acc + 13325332U, // MVE_VADDVu32no_acc + 13781916U, // MVE_VADDVu8acc + 13849620U, // MVE_VADDVu8no_acc + 7490935U, // MVE_VADD_qr_f16 + 8015223U, // MVE_VADD_qr_f32 + 14830967U, // MVE_VADD_qr_i16 + 14306679U, // MVE_VADD_qr_i32 + 15355255U, // MVE_VADD_qr_i8 + 7490935U, // MVE_VADDf16 + 8015223U, // MVE_VADDf32 + 14830967U, // MVE_VADDi16 + 14306679U, // MVE_VADDi32 + 15355255U, // MVE_VADDi8 + 2772366U, // MVE_VAND + 2772246U, // MVE_VBIC + 14830870U, // MVE_VBICimmi16 + 14306582U, // MVE_VBICimmi32 + 676338U, // MVE_VBRSR16 + 1200626U, // MVE_VBRSR32 + 1724914U, // MVE_VBRSR8 + 7482706U, // MVE_VCADDf16 + 8006994U, // MVE_VCADDf32 + 14822738U, // MVE_VCADDi16 + 14298450U, // MVE_VCADDi32 + 15347026U, // MVE_VCADDi8 + 11227686U, // MVE_VCLSs16 + 11751974U, // MVE_VCLSs32 + 12276262U, // MVE_VCLSs8 + 14898675U, // MVE_VCLZs16 + 14374387U, // MVE_VCLZs32 + 15422963U, // MVE_VCLZs8 + 7498530U, // MVE_VCMLAf16 + 8022818U, // MVE_VCMLAf32 + 1953640721U, // MVE_VCMPf16 + 1953640721U, // MVE_VCMPf16r + 1954165009U, // MVE_VCMPf32 + 1954165009U, // MVE_VCMPf32r + 1960980753U, // MVE_VCMPi16 + 1960980753U, // MVE_VCMPi16r + 1960456465U, // MVE_VCMPi32 + 1960456465U, // MVE_VCMPi32r + 1961505041U, // MVE_VCMPi8 + 1961505041U, // MVE_VCMPi8r + 1957310737U, // MVE_VCMPs16 + 1957310737U, // MVE_VCMPs16r + 1957835025U, // MVE_VCMPs32 + 1957835025U, // MVE_VCMPs32r + 1958359313U, // MVE_VCMPs8 + 1958359313U, // MVE_VCMPs8r + 1958883601U, // MVE_VCMPu16 + 1958883601U, // MVE_VCMPu16r + 1959407889U, // MVE_VCMPu32 + 1959407889U, // MVE_VCMPu32r + 1959932177U, // MVE_VCMPu8 + 1959932177U, // MVE_VCMPu8r + 7483436U, // MVE_VCMULf16 + 8007724U, // MVE_VCMULf32 + 873156946U, // MVE_VCTP16 + 873681234U, // MVE_VCTP32 + 888361298U, // MVE_VCTP64 + 874205522U, // MVE_VCTP8 + 821710003U, // MVE_VCVTf16f32bh + 821711766U, // MVE_VCVTf16f32th + 1157780392U, // MVE_VCVTf16s16_fix + 1090737064U, // MVE_VCVTf16s16n + 1158304680U, // MVE_VCVTf16u16_fix + 1091261352U, // MVE_VCVTf16u16n + 18042035U, // MVE_VCVTf32f16bh + 18043798U, // MVE_VCVTf32f16th + 1159353256U, // MVE_VCVTf32s32_fix + 1092309928U, // MVE_VCVTf32s32n + 1159877544U, // MVE_VCVTf32u32_fix + 1092834216U, // MVE_VCVTf32u32n + 1160401832U, // MVE_VCVTs16f16_fix + 1093356400U, // MVE_VCVTs16f16a + 1093357682U, // MVE_VCVTs16f16m + 1093357778U, // MVE_VCVTs16f16n + 1093357918U, // MVE_VCVTs16f16p + 1093358504U, // MVE_VCVTs16f16z + 1160926120U, // MVE_VCVTs32f32_fix + 1093880688U, // MVE_VCVTs32f32a + 1093881970U, // MVE_VCVTs32f32m + 1093882066U, // MVE_VCVTs32f32n + 1093882206U, // MVE_VCVTs32f32p + 1093882792U, // MVE_VCVTs32f32z + 1161450408U, // MVE_VCVTu16f16_fix + 1094404976U, // MVE_VCVTu16f16a + 1094406258U, // MVE_VCVTu16f16m + 1094406354U, // MVE_VCVTu16f16n + 1094406494U, // MVE_VCVTu16f16p + 1094407080U, // MVE_VCVTu16f16z + 1161974696U, // MVE_VCVTu32f32_fix + 1094929264U, // MVE_VCVTu32f32a + 1094930546U, // MVE_VCVTu32f32m + 1094930642U, // MVE_VCVTu32f32n + 1094930782U, // MVE_VCVTu32f32p + 1094931368U, // MVE_VCVTu32f32z + 12726628U, // MVE_VDDUPu16 + 13250916U, // MVE_VDDUPu32 + 13775204U, // MVE_VDDUPu8 + 741744U, // MVE_VDUP16 + 1266032U, // MVE_VDUP32 + 1790320U, // MVE_VDUP8 + 12743029U, // MVE_VDWDUPu16 + 13267317U, // MVE_VDWDUPu32 + 13791605U, // MVE_VDWDUPu8 + 2773455U, // MVE_VEOR + 7483920U, // MVE_VFMA_qr_Sf16 + 8008208U, // MVE_VFMA_qr_Sf32 + 7482169U, // MVE_VFMA_qr_f16 + 8006457U, // MVE_VFMA_qr_f32 + 7482169U, // MVE_VFMAf16 + 8006457U, // MVE_VFMAf32 + 7483964U, // MVE_VFMSf16 + 8008252U, // MVE_VFMSf32 + 11160933U, // MVE_VHADD_qr_s16 + 11685221U, // MVE_VHADD_qr_s32 + 12209509U, // MVE_VHADD_qr_s8 + 12733797U, // MVE_VHADD_qr_u16 + 13258085U, // MVE_VHADD_qr_u32 + 13782373U, // MVE_VHADD_qr_u8 + 11160933U, // MVE_VHADDs16 + 11685221U, // MVE_VHADDs32 + 12209509U, // MVE_VHADDs8 + 12733797U, // MVE_VHADDu16 + 13258085U, // MVE_VHADDu32 + 13782373U, // MVE_VHADDu8 + 11152715U, // MVE_VHCADDs16 + 11677003U, // MVE_VHCADDs32 + 12201291U, // MVE_VHCADDs8 + 11160777U, // MVE_VHSUB_qr_s16 + 11685065U, // MVE_VHSUB_qr_s32 + 12209353U, // MVE_VHSUB_qr_s8 + 12733641U, // MVE_VHSUB_qr_u16 + 13257929U, // MVE_VHSUB_qr_u32 + 13782217U, // MVE_VHSUB_qr_u8 + 11160777U, // MVE_VHSUBs16 + 11685065U, // MVE_VHSUBs32 + 12209353U, // MVE_VHSUBs8 + 12733641U, // MVE_VHSUBu16 + 13257929U, // MVE_VHSUBu32 + 13782217U, // MVE_VHSUBu8 + 12726634U, // MVE_VIDUPu16 + 13250922U, // MVE_VIDUPu32 + 13775210U, // MVE_VIDUPu8 + 12743036U, // MVE_VIWDUPu16 + 13267324U, // MVE_VIWDUPu32 + 13791612U, // MVE_VIWDUPu8 + 21717869U, // MVE_VLD20_16 + 22242157U, // MVE_VLD20_16_wb + 21716999U, // MVE_VLD20_32 + 22241287U, // MVE_VLD20_32_wb + 21718505U, // MVE_VLD20_8 + 22242793U, // MVE_VLD20_8_wb + 21717909U, // MVE_VLD21_16 + 22242197U, // MVE_VLD21_16_wb + 21717065U, // MVE_VLD21_32 + 22241353U, // MVE_VLD21_32_wb + 21718541U, // MVE_VLD21_8 + 22242829U, // MVE_VLD21_8_wb + 21726081U, // MVE_VLD40_16 + 22250369U, // MVE_VLD40_16_wb + 21725211U, // MVE_VLD40_32 + 22249499U, // MVE_VLD40_32_wb + 21726715U, // MVE_VLD40_8 + 22251003U, // MVE_VLD40_8_wb + 21726121U, // MVE_VLD41_16 + 22250409U, // MVE_VLD41_16_wb + 21725277U, // MVE_VLD41_32 + 22249565U, // MVE_VLD41_32_wb + 21726751U, // MVE_VLD41_8 + 22251039U, // MVE_VLD41_8_wb + 21726141U, // MVE_VLD42_16 + 22250429U, // MVE_VLD42_16_wb + 21725323U, // MVE_VLD42_32 + 22249611U, // MVE_VLD42_32_wb + 21726769U, // MVE_VLD42_8 + 22251057U, // MVE_VLD42_8_wb + 21726161U, // MVE_VLD43_16 + 22250449U, // MVE_VLD43_16_wb + 21725356U, // MVE_VLD43_32 + 22249644U, // MVE_VLD43_32_wb + 21726787U, // MVE_VLD43_8 + 22251075U, // MVE_VLD43_8_wb + 11160697U, // MVE_VLDRBS16 + 883567737U, // MVE_VLDRBS16_post + 883567737U, // MVE_VLDRBS16_pre + 11160697U, // MVE_VLDRBS16_rq + 11684985U, // MVE_VLDRBS32 + 884092025U, // MVE_VLDRBS32_post + 884092025U, // MVE_VLDRBS32_pre + 11684985U, // MVE_VLDRBS32_rq + 12733561U, // MVE_VLDRBU16 + 885140601U, // MVE_VLDRBU16_post + 885140601U, // MVE_VLDRBU16_pre + 12733561U, // MVE_VLDRBU16_rq + 13257849U, // MVE_VLDRBU32 + 885664889U, // MVE_VLDRBU32_post + 885664889U, // MVE_VLDRBU32_pre + 13257849U, // MVE_VLDRBU32_rq + 13782137U, // MVE_VLDRBU8 + 886189177U, // MVE_VLDRBU8_post + 886189177U, // MVE_VLDRBU8_pre + 13782137U, // MVE_VLDRBU8_rq + 22695315U, // MVE_VLDRDU64_qi + 895102355U, // MVE_VLDRDU64_qi_pre + 22695315U, // MVE_VLDRDU64_rq + 22695315U, // MVE_VLDRDU64_rq_u + 11685503U, // MVE_VLDRHS32 + 884092543U, // MVE_VLDRHS32_post + 884092543U, // MVE_VLDRHS32_pre + 11685503U, // MVE_VLDRHS32_rq + 11685503U, // MVE_VLDRHS32_rq_u + 12734079U, // MVE_VLDRHU16 + 885141119U, // MVE_VLDRHU16_post + 885141119U, // MVE_VLDRHU16_pre + 12734079U, // MVE_VLDRHU16_rq + 12734079U, // MVE_VLDRHU16_rq_u + 13258367U, // MVE_VLDRHU32 + 885665407U, // MVE_VLDRHU32_post + 885665407U, // MVE_VLDRHU32_pre + 13258367U, // MVE_VLDRHU32_rq + 13258367U, // MVE_VLDRHU32_rq_u + 13259878U, // MVE_VLDRWU32 + 885666918U, // MVE_VLDRWU32_post + 885666918U, // MVE_VLDRWU32_pre + 13259878U, // MVE_VLDRWU32_qi + 885666918U, // MVE_VLDRWU32_qi_pre + 13259878U, // MVE_VLDRWU32_rq + 13259878U, // MVE_VLDRWU32_rq_u + 883577869U, // MVE_VMAXAVs16 + 884102157U, // MVE_VMAXAVs32 + 884626445U, // MVE_VMAXAVs8 + 11160491U, // MVE_VMAXAs16 + 11684779U, // MVE_VMAXAs32 + 12209067U, // MVE_VMAXAs8 + 879907837U, // MVE_VMAXNMAVf16 + 880432125U, // MVE_VMAXNMAVf32 + 7490380U, // MVE_VMAXNMAf16 + 8014668U, // MVE_VMAXNMAf32 + 879907900U, // MVE_VMAXNMVf16 + 880432188U, // MVE_VMAXNMVf32 + 7491670U, // MVE_VMAXNMf16 + 8015958U, // MVE_VMAXNMf32 + 883577935U, // MVE_VMAXVs16 + 884102223U, // MVE_VMAXVs32 + 884626511U, // MVE_VMAXVs8 + 885150799U, // MVE_VMAXVu16 + 885675087U, // MVE_VMAXVu32 + 886199375U, // MVE_VMAXVu8 + 11162791U, // MVE_VMAXs16 + 11687079U, // MVE_VMAXs32 + 12211367U, // MVE_VMAXs8 + 12735655U, // MVE_VMAXu16 + 13259943U, // MVE_VMAXu32 + 13784231U, // MVE_VMAXu8 + 883577862U, // MVE_VMINAVs16 + 884102150U, // MVE_VMINAVs32 + 884626438U, // MVE_VMINAVs8 + 11160404U, // MVE_VMINAs16 + 11684692U, // MVE_VMINAs32 + 12208980U, // MVE_VMINAs8 + 879907828U, // MVE_VMINNMAVf16 + 880432116U, // MVE_VMINNMAVf32 + 7490372U, // MVE_VMINNMAf16 + 8014660U, // MVE_VMINNMAf32 + 879907892U, // MVE_VMINNMVf16 + 880432180U, // MVE_VMINNMVf32 + 7491663U, // MVE_VMINNMf16 + 8015951U, // MVE_VMINNMf32 + 883577924U, // MVE_VMINVs16 + 884102212U, // MVE_VMINVs32 + 884626500U, // MVE_VMINVs8 + 885150788U, // MVE_VMINVu16 + 885675076U, // MVE_VMINVu32 + 886199364U, // MVE_VMINVu8 + 11161756U, // MVE_VMINs16 + 11686044U, // MVE_VMINs32 + 12210332U, // MVE_VMINs8 + 12734620U, // MVE_VMINu16 + 13258908U, // MVE_VMINu32 + 13783196U, // MVE_VMINu8 + 11152246U, // MVE_VMLADAVas16 + 11676534U, // MVE_VMLADAVas32 + 12200822U, // MVE_VMLADAVas8 + 12725110U, // MVE_VMLADAVau16 + 13249398U, // MVE_VMLADAVau32 + 13773686U, // MVE_VMLADAVau8 + 11154632U, // MVE_VMLADAVaxs16 + 11678920U, // MVE_VMLADAVaxs32 + 12203208U, // MVE_VMLADAVaxs8 + 11162578U, // MVE_VMLADAVs16 + 11686866U, // MVE_VMLADAVs32 + 12211154U, // MVE_VMLADAVs8 + 12735442U, // MVE_VMLADAVu16 + 13259730U, // MVE_VMLADAVu32 + 13784018U, // MVE_VMLADAVu8 + 11163085U, // MVE_VMLADAVxs16 + 11687373U, // MVE_VMLADAVxs32 + 12211661U, // MVE_VMLADAVxs8 + 11176831U, // MVE_VMLALDAVas16 + 11701119U, // MVE_VMLALDAVas32 + 12749695U, // MVE_VMLALDAVau16 + 13273983U, // MVE_VMLALDAVau32 + 11179218U, // MVE_VMLALDAVaxs16 + 11703506U, // MVE_VMLALDAVaxs32 + 11154394U, // MVE_VMLALDAVs16 + 11678682U, // MVE_VMLALDAVs32 + 12727258U, // MVE_VMLALDAVu16 + 13251546U, // MVE_VMLALDAVu32 + 11154902U, // MVE_VMLALDAVxs16 + 11679190U, // MVE_VMLALDAVxs32 + 14823946U, // MVE_VMLAS_qr_i16 + 14299658U, // MVE_VMLAS_qr_i32 + 15348234U, // MVE_VMLAS_qr_i8 + 14822196U, // MVE_VMLA_qr_i16 + 14297908U, // MVE_VMLA_qr_i32 + 15346484U, // MVE_VMLA_qr_i8 + 11152275U, // MVE_VMLSDAVas16 + 11676563U, // MVE_VMLSDAVas32 + 12200851U, // MVE_VMLSDAVas8 + 11154664U, // MVE_VMLSDAVaxs16 + 11678952U, // MVE_VMLSDAVaxs32 + 12203240U, // MVE_VMLSDAVaxs8 + 11162604U, // MVE_VMLSDAVs16 + 11686892U, // MVE_VMLSDAVs32 + 12211180U, // MVE_VMLSDAVs8 + 11163114U, // MVE_VMLSDAVxs16 + 11687402U, // MVE_VMLSDAVxs32 + 12211690U, // MVE_VMLSDAVxs8 + 11176841U, // MVE_VMLSLDAVas16 + 11701129U, // MVE_VMLSLDAVas32 + 11179229U, // MVE_VMLSLDAVaxs16 + 11703517U, // MVE_VMLSLDAVaxs32 + 11154403U, // MVE_VMLSLDAVs16 + 11678691U, // MVE_VMLSLDAVs32 + 11154912U, // MVE_VMLSLDAVxs16 + 11679200U, // MVE_VMLSLDAVxs32 + 11226142U, // MVE_VMOVLs16bh + 11227900U, // MVE_VMOVLs16th + 12274718U, // MVE_VMOVLs8bh + 12276476U, // MVE_VMOVLs8th + 12799006U, // MVE_VMOVLu16bh + 12800764U, // MVE_VMOVLu16th + 13847582U, // MVE_VMOVLu8bh + 13849340U, // MVE_VMOVLu8th + 14830701U, // MVE_VMOVNi16bh + 14832465U, // MVE_VMOVNi16th + 14306413U, // MVE_VMOVNi32bh + 14308177U, // MVE_VMOVNi32th + 1111114U, // MVE_VMOV_from_lane_32 + 11072586U, // MVE_VMOV_from_lane_s16 + 12121162U, // MVE_VMOV_from_lane_s8 + 12645450U, // MVE_VMOV_from_lane_u16 + 13694026U, // MVE_VMOV_from_lane_u8 + 2757706U, // MVE_VMOV_q_rr + 2675786U, // MVE_VMOV_rr_q + 570442U, // MVE_VMOV_to_lane_16 + 1094730U, // MVE_VMOV_to_lane_32 + 1619018U, // MVE_VMOV_to_lane_8 + 8082506U, // MVE_VMOVimmf32 + 14898250U, // MVE_VMOVimmi16 + 14373962U, // MVE_VMOVimmi32 + 2036552778U, // MVE_VMOVimmi64 + 15422538U, // MVE_VMOVimmi8 + 11161209U, // MVE_VMULHs16 + 11685497U, // MVE_VMULHs32 + 12209785U, // MVE_VMULHs8 + 12734073U, // MVE_VMULHu16 + 13258361U, // MVE_VMULHu32 + 13782649U, // MVE_VMULHu8 + 23743506U, // MVE_VMULLBp16 + 24267794U, // MVE_VMULLBp8 + 11160594U, // MVE_VMULLBs16 + 11684882U, // MVE_VMULLBs32 + 12209170U, // MVE_VMULLBs8 + 12733458U, // MVE_VMULLBu16 + 13257746U, // MVE_VMULLBu32 + 13782034U, // MVE_VMULLBu8 + 23745269U, // MVE_VMULLTp16 + 24269557U, // MVE_VMULLTp8 + 11162357U, // MVE_VMULLTs16 + 11686645U, // MVE_VMULLTs32 + 12210933U, // MVE_VMULLTs8 + 12735221U, // MVE_VMULLTu16 + 13259509U, // MVE_VMULLTu32 + 13783797U, // MVE_VMULLTu8 + 7491646U, // MVE_VMUL_qr_f16 + 8015934U, // MVE_VMUL_qr_f32 + 14831678U, // MVE_VMUL_qr_i16 + 14307390U, // MVE_VMUL_qr_i32 + 15355966U, // MVE_VMUL_qr_i8 + 7491646U, // MVE_VMULf16 + 8015934U, // MVE_VMULf32 + 14831678U, // MVE_VMULi16 + 14307390U, // MVE_VMULi32 + 15355966U, // MVE_VMULi8 + 2838769U, // MVE_VMVN + 14897393U, // MVE_VMVNimmi16 + 14373105U, // MVE_VMVNimmi32 + 7556611U, // MVE_VNEGf16 + 8080899U, // MVE_VNEGf32 + 11226627U, // MVE_VNEGs16 + 11750915U, // MVE_VNEGs32 + 12275203U, // MVE_VNEGs8 + 2773185U, // MVE_VORN + 2773469U, // MVE_VORR + 14832093U, // MVE_VORRimmi16 + 14307805U, // MVE_VORRimmi32 + 1076581208U, // MVE_VPNOT + 2772855U, // MVE_VPSEL + 1076605810U, // MVE_VPST + 1961603934U, // MVE_VPTv16i8 + 1961603934U, // MVE_VPTv16i8r + 1958458206U, // MVE_VPTv16s8 + 1958458206U, // MVE_VPTv16s8r + 1960031070U, // MVE_VPTv16u8 + 1960031070U, // MVE_VPTv16u8r + 1954263902U, // MVE_VPTv4f32 + 1954263902U, // MVE_VPTv4f32r + 1960555358U, // MVE_VPTv4i32 + 1960555358U, // MVE_VPTv4i32r + 1957933918U, // MVE_VPTv4s32 + 1957933918U, // MVE_VPTv4s32r + 1959506782U, // MVE_VPTv4u32 + 1959506782U, // MVE_VPTv4u32r + 1953739614U, // MVE_VPTv8f16 + 1953739614U, // MVE_VPTv8f16r + 1961079646U, // MVE_VPTv8i16 + 1961079646U, // MVE_VPTv8i16r + 1957409630U, // MVE_VPTv8s16 + 1957409630U, // MVE_VPTv8s16r + 1958982494U, // MVE_VPTv8u16 + 1958982494U, // MVE_VPTv8u16r + 11227670U, // MVE_VQABSs16 + 11751958U, // MVE_VQABSs32 + 12276246U, // MVE_VQABSs8 + 11160945U, // MVE_VQADD_qr_s16 + 11685233U, // MVE_VQADD_qr_s32 + 12209521U, // MVE_VQADD_qr_s8 + 12733809U, // MVE_VQADD_qr_u16 + 13258097U, // MVE_VQADD_qr_u32 + 13782385U, // MVE_VQADD_qr_u8 + 11160945U, // MVE_VQADDs16 + 11685233U, // MVE_VQADDs32 + 12209521U, // MVE_VQADDs8 + 12733809U, // MVE_VQADDu16 + 13258097U, // MVE_VQADDu32 + 13782385U, // MVE_VQADDu8 + 11154779U, // MVE_VQDMLADHXs16 + 11679067U, // MVE_VQDMLADHXs32 + 12203355U, // MVE_VQDMLADHXs8 + 11152950U, // MVE_VQDMLADHs16 + 11677238U, // MVE_VQDMLADHs32 + 12201526U, // MVE_VQDMLADHs8 + 11152917U, // MVE_VQDMLAH_qrs16 + 11677205U, // MVE_VQDMLAH_qrs32 + 12201493U, // MVE_VQDMLAH_qrs8 + 11153035U, // MVE_VQDMLASH_qrs16 + 11677323U, // MVE_VQDMLASH_qrs32 + 12201611U, // MVE_VQDMLASH_qrs8 + 11154800U, // MVE_VQDMLSDHXs16 + 11679088U, // MVE_VQDMLSDHXs32 + 12203376U, // MVE_VQDMLSDHXs8 + 11152969U, // MVE_VQDMLSDHs16 + 11677257U, // MVE_VQDMLSDHs32 + 12201545U, // MVE_VQDMLSDHs8 + 11161185U, // MVE_VQDMULH_qr_s16 + 11685473U, // MVE_VQDMULH_qr_s32 + 12209761U, // MVE_VQDMULH_qr_s8 + 11161185U, // MVE_VQDMULHi16 + 11685473U, // MVE_VQDMULHi32 + 12209761U, // MVE_VQDMULHi8 + 11160585U, // MVE_VQDMULL_qr_s16bh + 11162348U, // MVE_VQDMULL_qr_s16th + 11684873U, // MVE_VQDMULL_qr_s32bh + 11686636U, // MVE_VQDMULL_qr_s32th + 11160585U, // MVE_VQDMULLs16bh + 11162348U, // MVE_VQDMULLs16th + 11684873U, // MVE_VQDMULLs32bh + 11686636U, // MVE_VQDMULLs32th + 11160677U, // MVE_VQMOVNs16bh + 11162441U, // MVE_VQMOVNs16th + 11684965U, // MVE_VQMOVNs32bh + 11686729U, // MVE_VQMOVNs32th + 12733541U, // MVE_VQMOVNu16bh + 12735305U, // MVE_VQMOVNu16th + 13257829U, // MVE_VQMOVNu32bh + 13259593U, // MVE_VQMOVNu32th + 11160668U, // MVE_VQMOVUNs16bh + 11162432U, // MVE_VQMOVUNs16th + 11684956U, // MVE_VQMOVUNs32bh + 11686720U, // MVE_VQMOVUNs32th + 11226621U, // MVE_VQNEGs16 + 11750909U, // MVE_VQNEGs32 + 12275197U, // MVE_VQNEGs8 + 11154789U, // MVE_VQRDMLADHXs16 + 11679077U, // MVE_VQRDMLADHXs32 + 12203365U, // MVE_VQRDMLADHXs8 + 11152959U, // MVE_VQRDMLADHs16 + 11677247U, // MVE_VQRDMLADHs32 + 12201535U, // MVE_VQRDMLADHs8 + 11152925U, // MVE_VQRDMLAH_qrs16 + 11677213U, // MVE_VQRDMLAH_qrs32 + 12201501U, // MVE_VQRDMLAH_qrs8 + 11153044U, // MVE_VQRDMLASH_qrs16 + 11677332U, // MVE_VQRDMLASH_qrs32 + 12201620U, // MVE_VQRDMLASH_qrs8 + 11154810U, // MVE_VQRDMLSDHXs16 + 11679098U, // MVE_VQRDMLSDHXs32 + 12203386U, // MVE_VQRDMLSDHXs8 + 11152978U, // MVE_VQRDMLSDHs16 + 11677266U, // MVE_VQRDMLSDHs32 + 12201554U, // MVE_VQRDMLSDHs8 + 11161193U, // MVE_VQRDMULH_qr_s16 + 11685481U, // MVE_VQRDMULH_qr_s32 + 12209769U, // MVE_VQRDMULH_qr_s8 + 11161193U, // MVE_VQRDMULHi16 + 11685481U, // MVE_VQRDMULHi32 + 12209769U, // MVE_VQRDMULHi8 + 11161498U, // MVE_VQRSHL_by_vecs16 + 11685786U, // MVE_VQRSHL_by_vecs32 + 12210074U, // MVE_VQRSHL_by_vecs8 + 12734362U, // MVE_VQRSHL_by_vecu16 + 13258650U, // MVE_VQRSHL_by_vecu32 + 13782938U, // MVE_VQRSHL_by_vecu8 + 11161498U, // MVE_VQRSHL_qrs16 + 11685786U, // MVE_VQRSHL_qrs32 + 12210074U, // MVE_VQRSHL_qrs8 + 12734362U, // MVE_VQRSHL_qru16 + 13258650U, // MVE_VQRSHL_qru32 + 13782938U, // MVE_VQRSHL_qru8 + 11152433U, // MVE_VQRSHRNbhs16 + 11676721U, // MVE_VQRSHRNbhs32 + 12725297U, // MVE_VQRSHRNbhu16 + 13249585U, // MVE_VQRSHRNbhu32 + 11154197U, // MVE_VQRSHRNths16 + 11678485U, // MVE_VQRSHRNths32 + 12727061U, // MVE_VQRSHRNthu16 + 13251349U, // MVE_VQRSHRNthu32 + 11152466U, // MVE_VQRSHRUNs16bh + 11154230U, // MVE_VQRSHRUNs16th + 11676754U, // MVE_VQRSHRUNs32bh + 11678518U, // MVE_VQRSHRUNs32th + 11162565U, // MVE_VQSHLU_imms16 + 11686853U, // MVE_VQSHLU_imms32 + 12211141U, // MVE_VQSHLU_imms8 + 11161485U, // MVE_VQSHL_by_vecs16 + 11685773U, // MVE_VQSHL_by_vecs32 + 12210061U, // MVE_VQSHL_by_vecs8 + 12734349U, // MVE_VQSHL_by_vecu16 + 13258637U, // MVE_VQSHL_by_vecu32 + 13782925U, // MVE_VQSHL_by_vecu8 + 11161485U, // MVE_VQSHL_qrs16 + 11685773U, // MVE_VQSHL_qrs32 + 12210061U, // MVE_VQSHL_qrs8 + 12734349U, // MVE_VQSHL_qru16 + 13258637U, // MVE_VQSHL_qru32 + 13782925U, // MVE_VQSHL_qru8 + 11161485U, // MVE_VQSHLimms16 + 11685773U, // MVE_VQSHLimms32 + 12210061U, // MVE_VQSHLimms8 + 12734349U, // MVE_VQSHLimmu16 + 13258637U, // MVE_VQSHLimmu32 + 13782925U, // MVE_VQSHLimmu8 + 11152425U, // MVE_VQSHRNbhs16 + 11676713U, // MVE_VQSHRNbhs32 + 12725289U, // MVE_VQSHRNbhu16 + 13249577U, // MVE_VQSHRNbhu32 + 11154189U, // MVE_VQSHRNths16 + 11678477U, // MVE_VQSHRNths32 + 12727053U, // MVE_VQSHRNthu16 + 13251341U, // MVE_VQSHRNthu32 + 11152457U, // MVE_VQSHRUNs16bh + 11154221U, // MVE_VQSHRUNs16th + 11676745U, // MVE_VQSHRUNs32bh + 11678509U, // MVE_VQSHRUNs32th + 11160783U, // MVE_VQSUB_qr_s16 + 11685071U, // MVE_VQSUB_qr_s32 + 12209359U, // MVE_VQSUB_qr_s8 + 12733647U, // MVE_VQSUB_qr_u16 + 13257935U, // MVE_VQSUB_qr_u32 + 13782223U, // MVE_VQSUB_qr_u8 + 11160783U, // MVE_VQSUBs16 + 11685071U, // MVE_VQSUBs32 + 12209359U, // MVE_VQSUBs8 + 12733647U, // MVE_VQSUBu16 + 13257935U, // MVE_VQSUBu32 + 13782223U, // MVE_VQSUBu8 + 1788408U, // MVE_VREV16_8 + 739609U, // MVE_VREV32_16 + 1788185U, // MVE_VREV32_8 + 739695U, // MVE_VREV64_16 + 1263983U, // MVE_VREV64_32 + 1788271U, // MVE_VREV64_8 + 11160926U, // MVE_VRHADDs16 + 11685214U, // MVE_VRHADDs32 + 12209502U, // MVE_VRHADDs8 + 12733790U, // MVE_VRHADDu16 + 13258078U, // MVE_VRHADDu32 + 13782366U, // MVE_VRHADDu8 + 7555941U, // MVE_VRINTf16A + 7557221U, // MVE_VRINTf16M + 7557323U, // MVE_VRINTf16N + 7557463U, // MVE_VRINTf16P + 7558598U, // MVE_VRINTf16X + 7558648U, // MVE_VRINTf16Z + 8080229U, // MVE_VRINTf32A + 8081509U, // MVE_VRINTf32M + 8081611U, // MVE_VRINTf32N + 8081751U, // MVE_VRINTf32P + 8082886U, // MVE_VRINTf32X + 8082936U, // MVE_VRINTf32Z + 11700976U, // MVE_VRMLALDAVHas32 + 13273840U, // MVE_VRMLALDAVHau32 + 11703415U, // MVE_VRMLALDAVHaxs32 + 11677378U, // MVE_VRMLALDAVHs32 + 13250242U, // MVE_VRMLALDAVHu32 + 11679109U, // MVE_VRMLALDAVHxs32 + 11700988U, // MVE_VRMLSLDAVHas32 + 11703428U, // MVE_VRMLSLDAVHaxs32 + 11677389U, // MVE_VRMLSLDAVHs32 + 11679121U, // MVE_VRMLSLDAVHxs32 + 11161202U, // MVE_VRMULHs16 + 11685490U, // MVE_VRMULHs32 + 12209778U, // MVE_VRMULHs8 + 12734066U, // MVE_VRMULHu16 + 13258354U, // MVE_VRMULHu32 + 13782642U, // MVE_VRMULHu8 + 11161505U, // MVE_VRSHL_by_vecs16 + 11685793U, // MVE_VRSHL_by_vecs32 + 12210081U, // MVE_VRSHL_by_vecs8 + 12734369U, // MVE_VRSHL_by_vecu16 + 13258657U, // MVE_VRSHL_by_vecu32 + 13782945U, // MVE_VRSHL_by_vecu8 + 11161505U, // MVE_VRSHL_qrs16 + 11685793U, // MVE_VRSHL_qrs32 + 12210081U, // MVE_VRSHL_qrs8 + 12734369U, // MVE_VRSHL_qru16 + 13258657U, // MVE_VRSHL_qru32 + 13782945U, // MVE_VRSHL_qru8 + 14822458U, // MVE_VRSHRNi16bh + 14824222U, // MVE_VRSHRNi16th + 14298170U, // MVE_VRSHRNi32bh + 14299934U, // MVE_VRSHRNi32th + 11162045U, // MVE_VRSHR_imms16 + 11686333U, // MVE_VRSHR_imms32 + 12210621U, // MVE_VRSHR_imms8 + 12734909U, // MVE_VRSHR_immu16 + 13259197U, // MVE_VRSHR_immu32 + 13783485U, // MVE_VRSHR_immu8 + 14314756U, // MVE_VSBC + 14298868U, // MVE_VSBCI + 808086811U, // MVE_VSHLC + 11160578U, // MVE_VSHLL_imms16bh + 11162341U, // MVE_VSHLL_imms16th + 12209154U, // MVE_VSHLL_imms8bh + 12210917U, // MVE_VSHLL_imms8th + 12733442U, // MVE_VSHLL_immu16bh + 12735205U, // MVE_VSHLL_immu16th + 13782018U, // MVE_VSHLL_immu8bh + 13783781U, // MVE_VSHLL_immu8th + 11226114U, // MVE_VSHLL_lws16bh + 11227877U, // MVE_VSHLL_lws16th + 12274690U, // MVE_VSHLL_lws8bh + 12276453U, // MVE_VSHLL_lws8th + 12798978U, // MVE_VSHLL_lwu16bh + 12800741U, // MVE_VSHLL_lwu16th + 13847554U, // MVE_VSHLL_lwu8bh + 13849317U, // MVE_VSHLL_lwu8th + 11161511U, // MVE_VSHL_by_vecs16 + 11685799U, // MVE_VSHL_by_vecs32 + 12210087U, // MVE_VSHL_by_vecs8 + 12734375U, // MVE_VSHL_by_vecu16 + 13258663U, // MVE_VSHL_by_vecu32 + 13782951U, // MVE_VSHL_by_vecu8 + 14831527U, // MVE_VSHL_immi16 + 14307239U, // MVE_VSHL_immi32 + 15355815U, // MVE_VSHL_immi8 + 11161511U, // MVE_VSHL_qrs16 + 11685799U, // MVE_VSHL_qrs32 + 12210087U, // MVE_VSHL_qrs8 + 12734375U, // MVE_VSHL_qru16 + 13258663U, // MVE_VSHL_qru32 + 13782951U, // MVE_VSHL_qru8 + 14822466U, // MVE_VSHRNi16bh + 14824230U, // MVE_VSHRNi16th + 14298178U, // MVE_VSHRNi32bh + 14299942U, // MVE_VSHRNi32th + 11162051U, // MVE_VSHR_imms16 + 11686339U, // MVE_VSHR_imms32 + 12210627U, // MVE_VSHR_imms8 + 12734915U, // MVE_VSHR_immu16 + 13259203U, // MVE_VSHR_immu32 + 13783491U, // MVE_VSHR_immu8 + 667400U, // MVE_VSLIimm16 + 1191688U, // MVE_VSLIimm32 + 1715976U, // MVE_VSLIimm8 + 667405U, // MVE_VSRIimm16 + 1191693U, // MVE_VSRIimm32 + 1715981U, // MVE_VSRIimm8 + 24863607U, // MVE_VST20_16 + 246647U, // MVE_VST20_16_wb + 24862737U, // MVE_VST20_32 + 245777U, // MVE_VST20_32_wb + 24864242U, // MVE_VST20_8 + 247282U, // MVE_VST20_8_wb + 24863647U, // MVE_VST21_16 + 246687U, // MVE_VST21_16_wb + 24862803U, // MVE_VST21_32 + 245843U, // MVE_VST21_32_wb + 24864278U, // MVE_VST21_8 + 247318U, // MVE_VST21_8_wb + 24871819U, // MVE_VST40_16 + 254859U, // MVE_VST40_16_wb + 24870949U, // MVE_VST40_32 + 253989U, // MVE_VST40_32_wb + 24872452U, // MVE_VST40_8 + 255492U, // MVE_VST40_8_wb + 24871859U, // MVE_VST41_16 + 254899U, // MVE_VST41_16_wb + 24871015U, // MVE_VST41_32 + 254055U, // MVE_VST41_32_wb + 24872488U, // MVE_VST41_8 + 255528U, // MVE_VST41_8_wb + 24871879U, // MVE_VST42_16 + 254919U, // MVE_VST42_16_wb + 24871061U, // MVE_VST42_32 + 254101U, // MVE_VST42_32_wb + 24872506U, // MVE_VST42_8 + 255546U, // MVE_VST42_8_wb + 24871899U, // MVE_VST43_16 + 254939U, // MVE_VST43_16_wb + 24871094U, // MVE_VST43_32 + 254134U, // MVE_VST43_32_wb + 24872524U, // MVE_VST43_8 + 255564U, // MVE_VST43_8_wb + 674943U, // MVE_VSTRB16 + 873081983U, // MVE_VSTRB16_post + 873081983U, // MVE_VSTRB16_pre + 674943U, // MVE_VSTRB16_rq + 1199231U, // MVE_VSTRB32 + 873606271U, // MVE_VSTRB32_post + 873606271U, // MVE_VSTRB32_pre + 1199231U, // MVE_VSTRB32_rq + 1723519U, // MVE_VSTRB8_rq + 1723519U, // MVE_VSTRBU8 + 874130559U, // MVE_VSTRBU8_post + 874130559U, // MVE_VSTRBU8_pre + 15879577U, // MVE_VSTRD64_qi + 888286617U, // MVE_VSTRD64_qi_pre + 15879577U, // MVE_VSTRD64_rq + 15879577U, // MVE_VSTRD64_rq_u + 675461U, // MVE_VSTRH16_rq + 675461U, // MVE_VSTRH16_rq_u + 1199749U, // MVE_VSTRH32 + 873606789U, // MVE_VSTRH32_post + 873606789U, // MVE_VSTRH32_pre + 1199749U, // MVE_VSTRH32_rq + 1199749U, // MVE_VSTRH32_rq_u + 675461U, // MVE_VSTRHU16 + 873082501U, // MVE_VSTRHU16_post + 873082501U, // MVE_VSTRHU16_pre + 1201260U, // MVE_VSTRW32_qi + 873608300U, // MVE_VSTRW32_qi_pre + 1201260U, // MVE_VSTRW32_rq + 1201260U, // MVE_VSTRW32_rq_u + 1201260U, // MVE_VSTRWU32 + 873608300U, // MVE_VSTRWU32_post + 873608300U, // MVE_VSTRWU32_pre + 7490773U, // MVE_VSUB_qr_f16 + 8015061U, // MVE_VSUB_qr_f32 + 14830805U, // MVE_VSUB_qr_i16 + 14306517U, // MVE_VSUB_qr_i32 + 15355093U, // MVE_VSUB_qr_i8 + 7490773U, // MVE_VSUBf16 + 8015061U, // MVE_VSUBf32 + 14830805U, // MVE_VSUBi16 + 14306517U, // MVE_VSUBi32 + 15355093U, // MVE_VSUBi8 + 875643887U, // MVE_WLSTP_16 + 875643134U, // MVE_WLSTP_32 + 875643496U, // MVE_WLSTP_64 + 875644545U, // MVE_WLSTP_8 + 2658546U, // MVNi + 2658546U, // MVNr + 2633970U, // MVNsi + 2691314U, // MVNsr + 875643322U, // NEON_VMAXNMNDf + 875644217U, // NEON_VMAXNMNDh + 875643322U, // NEON_VMAXNMNQf + 875644217U, // NEON_VMAXNMNQh + 875643310U, // NEON_VMINNMNDf + 875644205U, // NEON_VMINNMNDh + 875643310U, // NEON_VMINNMNQf + 875644205U, // NEON_VMINNMNQh + 2634206U, // ORRri + 2634206U, // ORRrr + 2691550U, // ORRrsi + 78302U, // ORRrsr + 2667147U, // PKHBT + 2665630U, // PKHTB + 264176U, // PLDWi12 + 272368U, // PLDWrs + 264010U, // PLDi12 + 272202U, // PLDrs + 264056U, // PLIi12 + 272248U, // PLIrs + 2682226U, // QADD + 2681301U, // QADD16 + 2681404U, // QADD8 + 2684343U, // QASX + 2682200U, // QDADD + 2682051U, // QDSUB + 2684089U, // QSAX + 2682064U, // QSUB + 2681263U, // QSUB16 + 2681365U, // QSUB8 + 2650838U, // RBIT + 2651162U, // REV + 2648569U, // REV16 + 2649778U, // REVSH + 4277995U, // RFEDA + 25257707U, // RFEDA_UPD + 4278026U, // RFEDB + 25257738U, // RFEDB_UPD + 4278002U, // RFEIA + 25257714U, // RFEIA_UPD + 4278033U, // RFEIB + 25257745U, // RFEIB_UPD + 2632847U, // RSBri + 2632847U, // RSBrr + 2690191U, // RSBrsi + 76943U, // RSBrsr + 2633006U, // RSCri + 2633006U, // RSCrr + 2690350U, // RSCrsi + 77102U, // RSCrsr + 2681308U, // SADD16 + 2681410U, // SADD8 + 2684348U, // SASX + 3206U, // SB + 2632965U, // SBCri + 2632965U, // SBCrr + 2690309U, // SBCrsi + 77061U, // SBCrsr + 2667857U, // SBFX + 2683934U, // SDIV + 2682745U, // SEL + 280399U, // SETEND + 4278172U, // SETPAN + 808534208U, // SHA1C + 875643082U, // SHA1H + 808534240U, // SHA1M + 808534250U, // SHA1P + 808534063U, // SHA1SU0 + 808534129U, // SHA1SU1 + 808534228U, // SHA256H + 808534175U, // SHA256H2 + 808534075U, // SHA256SU0 + 808534141U, // SHA256SU1 + 2681284U, // SHADD16 + 2681389U, // SHADD8 + 2684330U, // SHASX + 2684076U, // SHSAX + 2681246U, // SHSUB16 + 2681350U, // SHSUB8 + 2731297U, // SMC + 2665410U, // SMLABB + 2667140U, // SMLABT + 2665786U, // SMLAD + 2667783U, // SMLADX + 290621U, // SMLAL + 2755529U, // SMLALBB + 2757265U, // SMLALBT + 2755964U, // SMLALD + 2757909U, // SMLALDX + 2755748U, // SMLALTB + 2757507U, // SMLALTT + 2665623U, // SMLATB + 2667388U, // SMLATT + 2665690U, // SMLAWB + 2667442U, // SMLAWT + 2665887U, // SMLSD + 2667813U, // SMLSDX + 2755975U, // SMLSLD + 2757917U, // SMLSLDX + 2665256U, // SMMLA + 2666902U, // SMMLAR + 2667051U, // SMMLS + 2666982U, // SMMLSR + 2682930U, // SMMUL + 2683336U, // SMMULR + 2682176U, // SMUAD + 2684174U, // SMUADX + 2681809U, // SMULBB + 2683545U, // SMULBT + 2691043U, // SMULL + 2682028U, // SMULTB + 2683787U, // SMULTT + 2682081U, // SMULWB + 2683833U, // SMULWT + 2682277U, // SMUSD + 2684204U, // SMUSDX + 4278330U, // SRSDA + 4278282U, // SRSDA_UPD + 4278352U, // SRSDB + 4278306U, // SRSDB_UPD + 4278341U, // SRSIA + 4278294U, // SRSIA_UPD + 4278363U, // SRSIB + 4278318U, // SRSIB_UPD + 2667125U, // SSAT + 2681322U, // SSAT16 + 2684094U, // SSAX + 2681270U, // SSUB16 + 2681371U, // SSUB8 + 1552590729U, // STC2L_OFFSET + 1619699593U, // STC2L_OPTION + 1619699593U, // STC2L_POST + 9561993U, // STC2L_PRE + 1552589369U, // STC2_OFFSET + 1619698233U, // STC2_OPTION + 1619698233U, // STC2_POST + 9560633U, // STC2_PRE + 1277734751U, // STCL_OFFSET + 1277734751U, // STCL_OPTION + 1277734751U, // STCL_POST + 1009307487U, // STCL_PRE + 1277734194U, // STC_OFFSET + 1277734194U, // STC_OPTION + 1277734194U, // STC_POST + 1009306930U, // STC_PRE + 2650152U, // STL + 2649113U, // STLB + 2684217U, // STLEX + 2682095U, // STLEXB + 2682290U, // STLEXD + 2682591U, // STLEXH + 2649692U, // STLH + 2730730U, // STMDA + 875064042U, // STMDA_UPD + 2730986U, // STMDB + 875064298U, // STMDB_UPD + 2732142U, // STMIA + 875065454U, // STMIA_UPD + 2731004U, // STMIB + 875064316U, // STMIB_UPD + 875090598U, // STRBT_POST_IMM + 875090598U, // STRBT_POST_REG + 875089024U, // STRB_POST_IMM + 875089024U, // STRB_POST_REG + 875080832U, // STRB_PRE_IMM + 875089024U, // STRB_PRE_REG + 2681984U, // STRBi12 + 2665600U, // STRBrs + 2674074U, // STRD + 875171226U, // STRD_POST + 875171226U, // STRD_PRE + 2684235U, // STREX + 2682109U, // STREXB + 2682304U, // STREXD + 2682605U, // STREXH + 2666118U, // STRH + 875082441U, // STRHTi + 875090633U, // STRHTr + 875089542U, // STRH_POST + 875089542U, // STRH_PRE + 875090797U, // STRT_POST_IMM + 875090797U, // STRT_POST_REG + 875090432U, // STR_POST_IMM + 875090432U, // STR_POST_REG + 875082240U, // STR_PRE_IMM + 875090432U, // STR_PRE_REG + 2683392U, // STRi12 + 2667008U, // STRrs + 2632901U, // SUBri + 2632901U, // SUBrr + 2690245U, // SUBrsi + 76997U, // SUBrsr + 2731318U, // SVC + 2683268U, // SWP + 2681972U, // SWPB + 2665398U, // SXTAB + 2664832U, // SXTAB16 + 2666022U, // SXTAH + 2682041U, // SXTB + 2681232U, // SXTB16 + 2682552U, // SXTH + 2650514U, // TEQri + 2650514U, // TEQrr + 2683282U, // TEQrsi + 2666898U, // TEQrsr + 4355U, // TRAP + 4355U, // TRAPNaCl + 296743U, // TSB + 2651000U, // TSTri + 2651000U, // TSTrr + 2683768U, // TSTrsi + 2667384U, // TSTrsr + 2681315U, // UADD16 + 2681416U, // UADD8 + 2684353U, // UASX + 2667862U, // UBFX + 4278107U, // UDF + 2683939U, // UDIV + 2681292U, // UHADD16 + 2681396U, // UHADD8 + 2684336U, // UHASX + 2684082U, // UHSAX + 2681254U, // UHSUB16 + 2681357U, // UHSUB8 + 2756386U, // UMAAL + 290627U, // UMLAL + 2691049U, // UMULL + 2681300U, // UQADD16 + 2681403U, // UQADD8 + 2684342U, // UQASX + 2684088U, // UQSAX + 2681262U, // UQSUB16 + 2681364U, // UQSUB8 + 2681383U, // USAD8 + 2664959U, // USADA8 + 2667130U, // USAT + 2681329U, // USAT16 + 2684099U, // USAX + 2681277U, // USUB16 + 2681377U, // USUB8 + 2665404U, // UXTAB + 2664840U, // UXTAB16 + 2666028U, // UXTAH + 2682046U, // UXTB + 2681239U, // UXTB16 + 2682557U, // UXTH + 11579176U, // VABALsv2i64 + 11054888U, // VABALsv4i32 + 12103464U, // VABALsv8i16 + 13152040U, // VABALuv2i64 + 12627752U, // VABALuv4i32 + 13676328U, // VABALuv8i16 + 12102345U, // VABAsv16i8 + 11578057U, // VABAsv2i32 + 11053769U, // VABAsv4i16 + 11578057U, // VABAsv4i32 + 11053769U, // VABAsv8i16 + 12102345U, // VABAsv8i8 + 13675209U, // VABAuv16i8 + 13150921U, // VABAuv2i32 + 12626633U, // VABAuv4i16 + 13150921U, // VABAuv4i32 + 12626633U, // VABAuv8i16 + 13675209U, // VABAuv8i8 + 11595620U, // VABDLsv2i64 + 11071332U, // VABDLsv4i32 + 12119908U, // VABDLsv8i16 + 13168484U, // VABDLuv2i64 + 12644196U, // VABDLuv4i32 + 13692772U, // VABDLuv8i16 + 7925062U, // VABDfd + 7925062U, // VABDfq + 7400774U, // VABDhd + 7400774U, // VABDhq + 12119366U, // VABDsv16i8 + 11595078U, // VABDsv2i32 + 11070790U, // VABDsv4i16 + 11595078U, // VABDsv4i32 + 11070790U, // VABDsv8i16 + 12119366U, // VABDsv8i8 + 13692230U, // VABDuv16i8 + 13167942U, // VABDuv2i32 + 12643654U, // VABDuv4i16 + 13167942U, // VABDuv4i32 + 12643654U, // VABDuv8i16 + 13692230U, // VABDuv8i8 + 1147695644U, // VABSD + 7369244U, // VABSH + 7893532U, // VABSS + 7893532U, // VABSfd + 7893532U, // VABSfq + 7369244U, // VABShd + 7369244U, // VABShq + 12087836U, // VABSv16i8 + 11563548U, // VABSv2i32 + 11039260U, // VABSv4i16 + 11563548U, // VABSv4i32 + 11039260U, // VABSv8i16 + 12087836U, // VABSv8i8 + 7925191U, // VACGEfd + 7925191U, // VACGEfq + 7400903U, // VACGEhd + 7400903U, // VACGEhq + 7926456U, // VACGTfd + 7926456U, // VACGTfq + 7402168U, // VACGThd + 7402168U, // VACGThq + 1147727223U, // VADDD + 7400823U, // VADDH + 895545487U, // VADDHNv2i32 + 14217359U, // VADDHNv4i16 + 14741647U, // VADDHNv8i8 + 11595633U, // VADDLsv2i64 + 11071345U, // VADDLsv4i32 + 12119921U, // VADDLsv8i16 + 13168497U, // VADDLuv2i64 + 12644209U, // VADDLuv4i32 + 13692785U, // VADDLuv8i16 + 7925111U, // VADDS + 11596891U, // VADDWsv2i64 + 11072603U, // VADDWsv4i32 + 12121179U, // VADDWsv8i16 + 13169755U, // VADDWuv2i64 + 12645467U, // VADDWuv4i32 + 13694043U, // VADDWuv8i16 + 7925111U, // VADDfd + 7925111U, // VADDfq + 7400823U, // VADDhd + 7400823U, // VADDhq + 15265143U, // VADDv16i8 + 895544695U, // VADDv1i64 + 14216567U, // VADDv2i32 + 895544695U, // VADDv2i64 + 14740855U, // VADDv4i16 + 14216567U, // VADDv4i32 + 14740855U, // VADDv8i16 + 15265143U, // VADDv8i8 + 2682254U, // VANDd + 2682254U, // VANDq + 808543686U, // VBF16MALBQ + 808543686U, // VBF16MALBQI + 808543698U, // VBF16MALTQ + 808543698U, // VBF16MALTQI + 2682134U, // VBICd + 14216470U, // VBICiv2i32 + 14740758U, // VBICiv4i16 + 14216470U, // VBICiv4i32 + 14740758U, // VBICiv8i16 + 2682134U, // VBICq + 2665967U, // VBIFd + 2665967U, // VBIFq + 2667227U, // VBITd + 2667227U, // VBITq + 2666517U, // VBSLd + 2666517U, // VBSLq + 0U, // VBSPd + 0U, // VBSPq + 875643287U, // VCADDv2f32 + 875644160U, // VCADDv4f16 + 875643287U, // VCADDv4f32 + 875644160U, // VCADDv8f16 + 7926157U, // VCEQfd + 7926157U, // VCEQfq + 7401869U, // VCEQhd + 7401869U, // VCEQhq + 15266189U, // VCEQv16i8 + 14217613U, // VCEQv2i32 + 14741901U, // VCEQv4i16 + 14217613U, // VCEQv4i32 + 14741901U, // VCEQv8i16 + 15266189U, // VCEQv8i8 + 15233421U, // VCEQzv16i8 + 7893389U, // VCEQzv2f32 + 14184845U, // VCEQzv2i32 + 7369101U, // VCEQzv4f16 + 7893389U, // VCEQzv4f32 + 14709133U, // VCEQzv4i16 + 14184845U, // VCEQzv4i32 + 7369101U, // VCEQzv8f16 + 14709133U, // VCEQzv8i16 + 15233421U, // VCEQzv8i8 + 7925197U, // VCGEfd + 7925197U, // VCGEfq + 7400909U, // VCGEhd + 7400909U, // VCGEhq + 12119501U, // VCGEsv16i8 + 11595213U, // VCGEsv2i32 + 11070925U, // VCGEsv4i16 + 11595213U, // VCGEsv4i32 + 11070925U, // VCGEsv8i16 + 12119501U, // VCGEsv8i8 + 13692365U, // VCGEuv16i8 + 13168077U, // VCGEuv2i32 + 12643789U, // VCGEuv4i16 + 13168077U, // VCGEuv4i32 + 12643789U, // VCGEuv8i16 + 13692365U, // VCGEuv8i8 + 12086733U, // VCGEzv16i8 + 7892429U, // VCGEzv2f32 + 11562445U, // VCGEzv2i32 + 7368141U, // VCGEzv4f16 + 7892429U, // VCGEzv4f32 + 11038157U, // VCGEzv4i16 + 11562445U, // VCGEzv4i32 + 7368141U, // VCGEzv8f16 + 11038157U, // VCGEzv8i16 + 12086733U, // VCGEzv8i8 + 7926462U, // VCGTfd + 7926462U, // VCGTfq + 7402174U, // VCGThd + 7402174U, // VCGThq + 12120766U, // VCGTsv16i8 + 11596478U, // VCGTsv2i32 + 11072190U, // VCGTsv4i16 + 11596478U, // VCGTsv4i32 + 11072190U, // VCGTsv8i16 + 12120766U, // VCGTsv8i8 + 13693630U, // VCGTuv16i8 + 13169342U, // VCGTuv2i32 + 12645054U, // VCGTuv4i16 + 13169342U, // VCGTuv4i32 + 12645054U, // VCGTuv8i16 + 13693630U, // VCGTuv8i8 + 12087998U, // VCGTzv16i8 + 7893694U, // VCGTzv2f32 + 11563710U, // VCGTzv2i32 + 7369406U, // VCGTzv4f16 + 7893694U, // VCGTzv4f32 + 11039422U, // VCGTzv4i16 + 11563710U, // VCGTzv4i32 + 7369406U, // VCGTzv8f16 + 11039422U, // VCGTzv8i16 + 12087998U, // VCGTzv8i8 + 12086738U, // VCLEzv16i8 + 7892434U, // VCLEzv2f32 + 11562450U, // VCLEzv2i32 + 7368146U, // VCLEzv4f16 + 7892434U, // VCLEzv4f32 + 11038162U, // VCLEzv4i16 + 11562450U, // VCLEzv4i32 + 7368146U, // VCLEzv8f16 + 11038162U, // VCLEzv8i16 + 12086738U, // VCLEzv8i8 + 12087846U, // VCLSv16i8 + 11563558U, // VCLSv2i32 + 11039270U, // VCLSv4i16 + 11563558U, // VCLSv4i32 + 11039270U, // VCLSv8i16 + 12087846U, // VCLSv8i8 + 12088032U, // VCLTzv16i8 + 7893728U, // VCLTzv2f32 + 11563744U, // VCLTzv2i32 + 7369440U, // VCLTzv4f16 + 7893728U, // VCLTzv4f32 + 11039456U, // VCLTzv4i16 + 11563744U, // VCLTzv4i32 + 7369440U, // VCLTzv8f16 + 11039456U, // VCLTzv8i16 + 12088032U, // VCLTzv8i8 + 15234547U, // VCLZv16i8 + 14185971U, // VCLZv2i32 + 14710259U, // VCLZv4i16 + 14185971U, // VCLZv4i32 + 14710259U, // VCLZv8i16 + 15234547U, // VCLZv8i8 + 808534400U, // VCMLAv2f32 + 808534400U, // VCMLAv2f32_indexed + 808535273U, // VCMLAv4f16 + 808535273U, // VCMLAv4f16_indexed + 808534400U, // VCMLAv4f32 + 808534400U, // VCMLAv4f32_indexed + 808535273U, // VCMLAv8f16 + 808535273U, // VCMLAv8f16_indexed + 1147695377U, // VCMPD + 1147694558U, // VCMPED + 7368158U, // VCMPEH + 7892446U, // VCMPES + 2087300574U, // VCMPEZD + 7450078U, // VCMPEZH + 7974366U, // VCMPEZS + 7368977U, // VCMPH + 7893265U, // VCMPS + 2087301393U, // VCMPZD + 7450897U, // VCMPZH + 7975185U, // VCMPZS + 1602307U, // VCNTd + 1602307U, // VCNTq + 875643144U, // VCVTANSDf + 875644017U, // VCVTANSDh + 875643144U, // VCVTANSQf + 875644017U, // VCVTANSQh + 875643204U, // VCVTANUDf + 875644077U, // VCVTANUDh + 875643204U, // VCVTANUQf + 875644077U, // VCVTANUQh + 875643506U, // VCVTASD + 875643897U, // VCVTASH + 875643144U, // VCVTASS + 875643566U, // VCVTAUD + 875643957U, // VCVTAUH + 875643204U, // VCVTAUS + 25750707U, // VCVTBDH + 26242227U, // VCVTBHD + 17853619U, // VCVTBHS + 821619891U, // VCVTBSH + 26768296U, // VCVTDS + 875643159U, // VCVTMNSDf + 875644032U, // VCVTMNSDh + 875643159U, // VCVTMNSQf + 875644032U, // VCVTMNSQh + 875643219U, // VCVTMNUDf + 875644092U, // VCVTMNUDh + 875643219U, // VCVTMNUQf + 875644092U, // VCVTMNUQh + 875643521U, // VCVTMSD + 875643912U, // VCVTMSH + 875643159U, // VCVTMSS + 875643581U, // VCVTMUD + 875643972U, // VCVTMUH + 875643219U, // VCVTMUS + 875643174U, // VCVTNNSDf + 875644047U, // VCVTNNSDh + 875643174U, // VCVTNNSQf + 875644047U, // VCVTNNSQh + 875643234U, // VCVTNNUDf + 875644107U, // VCVTNNUDh + 875643234U, // VCVTNNUQf + 875644107U, // VCVTNNUQh + 875643536U, // VCVTNSD + 875643927U, // VCVTNSH + 875643174U, // VCVTNSS + 875643596U, // VCVTNUD + 875643987U, // VCVTNUH + 875643234U, // VCVTNUS + 875643189U, // VCVTPNSDf + 875644062U, // VCVTPNSDh + 875643189U, // VCVTPNSQf + 875644062U, // VCVTPNSQh + 875643249U, // VCVTPNUDf + 875644122U, // VCVTPNUDh + 875643249U, // VCVTPNUQf + 875644122U, // VCVTPNUQh + 875643551U, // VCVTPSD + 875643942U, // VCVTPSH + 875643189U, // VCVTPSS + 875643611U, // VCVTPUD + 875644002U, // VCVTPUH + 875643249U, // VCVTPUS + 27292584U, // VCVTSD + 25752470U, // VCVTTDH + 26243990U, // VCVTTHD + 17855382U, // VCVTTHS + 821621654U, // VCVTTSH + 888697768U, // VCVTf2h + 1093694376U, // VCVTf2sd + 1093694376U, // VCVTf2sq + 1094742952U, // VCVTf2ud + 1094742952U, // VCVTf2uq + 1160836008U, // VCVTf2xsd + 1160836008U, // VCVTf2xsq + 1161884584U, // VCVTf2xud + 1161884584U, // VCVTf2xuq + 17855400U, // VCVTh2f + 1093170088U, // VCVTh2sd + 1093170088U, // VCVTh2sq + 1094218664U, // VCVTh2ud + 1094218664U, // VCVTh2uq + 1160311720U, // VCVTh2xsd + 1160311720U, // VCVTh2xsq + 1161360296U, // VCVTh2xud + 1161360296U, // VCVTh2xuq + 1092121512U, // VCVTs2fd + 1092121512U, // VCVTs2fq + 1090548648U, // VCVTs2hd + 1090548648U, // VCVTs2hq + 1092645800U, // VCVTu2fd + 1092645800U, // VCVTu2fq + 1091072936U, // VCVTu2hd + 1091072936U, // VCVTu2hq + 1159263144U, // VCVTxs2fd + 1159263144U, // VCVTxs2fq + 1157690280U, // VCVTxs2hd + 1157690280U, // VCVTxs2hq + 1159787432U, // VCVTxu2fd + 1159787432U, // VCVTxu2fq + 1158214568U, // VCVTxu2hd + 1158214568U, // VCVTxu2hq + 1147728936U, // VDIVD + 7402536U, // VDIVH + 7926824U, // VDIVS + 553328U, // VDUP16d + 553328U, // VDUP16q + 1077616U, // VDUP32d + 1077616U, // VDUP32q + 1601904U, // VDUP8d + 1601904U, // VDUP8q + 586096U, // VDUPLN16d + 586096U, // VDUPLN16q + 1110384U, // VDUPLN32d + 1110384U, // VDUPLN32q + 1634672U, // VDUPLN8d + 1634672U, // VDUPLN8q + 2683343U, // VEORd + 2683343U, // VEORq + 570304U, // VEXTd16 + 1094592U, // VEXTd32 + 1618880U, // VEXTd8 + 570304U, // VEXTq16 + 1094592U, // VEXTq32 + 15774656U, // VEXTq64 + 1618880U, // VEXTq8 + 1147710265U, // VFMAD + 7383865U, // VFMAH + 875644183U, // VFMALD + 875644183U, // VFMALDI + 875644183U, // VFMALQ + 875644183U, // VFMALQI + 7908153U, // VFMAS + 7908153U, // VFMAfd + 7908153U, // VFMAfq + 7383865U, // VFMAhd + 7383865U, // VFMAhq + 1147712060U, // VFMSD + 7385660U, // VFMSH + 875644194U, // VFMSLD + 875644194U, // VFMSLDI + 875644194U, // VFMSLQ + 875644194U, // VFMSLQI + 7909948U, // VFMSS + 7909948U, // VFMSfd + 7909948U, // VFMSfq + 7385660U, // VFMShd + 7385660U, // VFMShq + 1147710270U, // VFNMAD + 7383870U, // VFNMAH + 7908158U, // VFNMAS + 1147712065U, // VFNMSD + 7385665U, // VFNMSH + 7909953U, // VFNMSS + 875643662U, // VFP_VMAXNMD + 875644217U, // VFP_VMAXNMH + 875643322U, // VFP_VMAXNMS + 875643650U, // VFP_VMINNMD + 875644205U, // VFP_VMINNMH + 875643310U, // VFP_VMINNMS + 1111114U, // VGETLNi32 + 11072586U, // VGETLNs16 + 12121162U, // VGETLNs8 + 12645450U, // VGETLNu16 + 13694026U, // VGETLNu8 + 12119397U, // VHADDsv16i8 + 11595109U, // VHADDsv2i32 + 11070821U, // VHADDsv4i16 + 11595109U, // VHADDsv4i32 + 11070821U, // VHADDsv8i16 + 12119397U, // VHADDsv8i8 + 13692261U, // VHADDuv16i8 + 13167973U, // VHADDuv2i32 + 12643685U, // VHADDuv4i16 + 13167973U, // VHADDuv4i32 + 12643685U, // VHADDuv8i16 + 13692261U, // VHADDuv8i8 + 12119241U, // VHSUBsv16i8 + 11594953U, // VHSUBsv2i32 + 11070665U, // VHSUBsv4i16 + 11594953U, // VHSUBsv4i32 + 11070665U, // VHSUBsv8i16 + 12119241U, // VHSUBsv8i8 + 13692105U, // VHSUBuv16i8 + 13167817U, // VHSUBuv2i32 + 12643529U, // VHSUBuv4i16 + 13167817U, // VHSUBuv4i32 + 12643529U, // VHSUBuv8i16 + 13692105U, // VHSUBuv8i8 + 808535413U, // VINSH + 1101558690U, // VJCVT + 2148067588U, // VLD1DUPd16 + 2148051204U, // VLD1DUPd16wb_fixed + 2148059396U, // VLD1DUPd16wb_register + 2148591876U, // VLD1DUPd32 + 2148575492U, // VLD1DUPd32wb_fixed + 2148583684U, // VLD1DUPd32wb_register + 2149116164U, // VLD1DUPd8 + 2149099780U, // VLD1DUPd8wb_fixed + 2149107972U, // VLD1DUPd8wb_register + 2215176452U, // VLD1DUPq16 + 2215160068U, // VLD1DUPq16wb_fixed + 2215168260U, // VLD1DUPq16wb_register + 2215700740U, // VLD1DUPq32 + 2215684356U, // VLD1DUPq32wb_fixed + 2215692548U, // VLD1DUPq32wb_register + 2216225028U, // VLD1DUPq8 + 2216208644U, // VLD1DUPq8wb_fixed + 2216216836U, // VLD1DUPq8wb_register + 28363012U, // VLD1LNd16 + 28616964U, // VLD1LNd16_UPD + 28887300U, // VLD1LNd32 + 29141252U, // VLD1LNd32_UPD + 29411588U, // VLD1LNd8 + 29665540U, // VLD1LNd8_UPD + 0U, // VLD1LNq16Pseudo + 0U, // VLD1LNq16Pseudo_UPD + 0U, // VLD1LNq32Pseudo + 0U, // VLD1LNq32Pseudo_UPD + 0U, // VLD1LNq8Pseudo + 0U, // VLD1LNq8Pseudo_UPD + 2282285316U, // VLD1d16 + 537454852U, // VLD1d16Q + 0U, // VLD1d16QPseudo + 0U, // VLD1d16QPseudoWB_fixed + 0U, // VLD1d16QPseudoWB_register + 537438468U, // VLD1d16Qwb_fixed + 537446660U, // VLD1d16Qwb_register + 269019396U, // VLD1d16T + 0U, // VLD1d16TPseudo + 0U, // VLD1d16TPseudoWB_fixed + 0U, // VLD1d16TPseudoWB_register + 269003012U, // VLD1d16Twb_fixed + 269011204U, // VLD1d16Twb_register + 2282268932U, // VLD1d16wb_fixed + 2282277124U, // VLD1d16wb_register + 2282809604U, // VLD1d32 + 537979140U, // VLD1d32Q + 0U, // VLD1d32QPseudo + 0U, // VLD1d32QPseudoWB_fixed + 0U, // VLD1d32QPseudoWB_register + 537962756U, // VLD1d32Qwb_fixed + 537970948U, // VLD1d32Qwb_register + 269543684U, // VLD1d32T + 0U, // VLD1d32TPseudo + 0U, // VLD1d32TPseudoWB_fixed + 0U, // VLD1d32TPseudoWB_register + 269527300U, // VLD1d32Twb_fixed + 269535492U, // VLD1d32Twb_register + 2282793220U, // VLD1d32wb_fixed + 2282801412U, // VLD1d32wb_register + 2297489668U, // VLD1d64 + 552659204U, // VLD1d64Q + 0U, // VLD1d64QPseudo + 0U, // VLD1d64QPseudoWB_fixed + 0U, // VLD1d64QPseudoWB_register + 552642820U, // VLD1d64Qwb_fixed + 552651012U, // VLD1d64Qwb_register + 284223748U, // VLD1d64T + 0U, // VLD1d64TPseudo + 0U, // VLD1d64TPseudoWB_fixed + 0U, // VLD1d64TPseudoWB_register + 284207364U, // VLD1d64Twb_fixed + 284215556U, // VLD1d64Twb_register + 2297473284U, // VLD1d64wb_fixed + 2297481476U, // VLD1d64wb_register + 2283333892U, // VLD1d8 + 538503428U, // VLD1d8Q + 0U, // VLD1d8QPseudo + 0U, // VLD1d8QPseudoWB_fixed + 0U, // VLD1d8QPseudoWB_register + 538487044U, // VLD1d8Qwb_fixed + 538495236U, // VLD1d8Qwb_register + 270067972U, // VLD1d8T + 0U, // VLD1d8TPseudo + 0U, // VLD1d8TPseudoWB_fixed + 0U, // VLD1d8TPseudoWB_register + 270051588U, // VLD1d8Twb_fixed + 270059780U, // VLD1d8Twb_register + 2283317508U, // VLD1d8wb_fixed + 2283325700U, // VLD1d8wb_register + 2349394180U, // VLD1q16 + 0U, // VLD1q16HighQPseudo + 0U, // VLD1q16HighQPseudo_UPD + 0U, // VLD1q16HighTPseudo + 0U, // VLD1q16HighTPseudo_UPD + 0U, // VLD1q16LowQPseudo_UPD + 0U, // VLD1q16LowTPseudo_UPD + 2349377796U, // VLD1q16wb_fixed + 2349385988U, // VLD1q16wb_register + 2349918468U, // VLD1q32 + 0U, // VLD1q32HighQPseudo + 0U, // VLD1q32HighQPseudo_UPD + 0U, // VLD1q32HighTPseudo + 0U, // VLD1q32HighTPseudo_UPD + 0U, // VLD1q32LowQPseudo_UPD + 0U, // VLD1q32LowTPseudo_UPD + 2349902084U, // VLD1q32wb_fixed + 2349910276U, // VLD1q32wb_register + 2364598532U, // VLD1q64 + 0U, // VLD1q64HighQPseudo + 0U, // VLD1q64HighQPseudo_UPD + 0U, // VLD1q64HighTPseudo + 0U, // VLD1q64HighTPseudo_UPD + 0U, // VLD1q64LowQPseudo_UPD + 0U, // VLD1q64LowTPseudo_UPD + 2364582148U, // VLD1q64wb_fixed + 2364590340U, // VLD1q64wb_register + 2350442756U, // VLD1q8 + 0U, // VLD1q8HighQPseudo + 0U, // VLD1q8HighQPseudo_UPD + 0U, // VLD1q8HighTPseudo + 0U, // VLD1q8HighTPseudo_UPD + 0U, // VLD1q8LowQPseudo_UPD + 0U, // VLD1q8LowTPseudo_UPD + 2350426372U, // VLD1q8wb_fixed + 2350434564U, // VLD1q8wb_register + 2215176501U, // VLD2DUPd16 + 2215160117U, // VLD2DUPd16wb_fixed + 2215168309U, // VLD2DUPd16wb_register + 2416503093U, // VLD2DUPd16x2 + 2416486709U, // VLD2DUPd16x2wb_fixed + 2416494901U, // VLD2DUPd16x2wb_register + 2215700789U, // VLD2DUPd32 + 2215684405U, // VLD2DUPd32wb_fixed + 2215692597U, // VLD2DUPd32wb_register + 2417027381U, // VLD2DUPd32x2 + 2417010997U, // VLD2DUPd32x2wb_fixed + 2417019189U, // VLD2DUPd32x2wb_register + 2216225077U, // VLD2DUPd8 + 2216208693U, // VLD2DUPd8wb_fixed + 2216216885U, // VLD2DUPd8wb_register + 2417551669U, // VLD2DUPd8x2 + 2417535285U, // VLD2DUPd8x2wb_fixed + 2417543477U, // VLD2DUPd8x2wb_register + 0U, // VLD2DUPq16EvenPseudo + 0U, // VLD2DUPq16OddPseudo + 0U, // VLD2DUPq16OddPseudoWB_fixed + 0U, // VLD2DUPq16OddPseudoWB_register + 0U, // VLD2DUPq32EvenPseudo + 0U, // VLD2DUPq32OddPseudo + 0U, // VLD2DUPq32OddPseudoWB_fixed + 0U, // VLD2DUPq32OddPseudoWB_register + 0U, // VLD2DUPq8EvenPseudo + 0U, // VLD2DUPq8OddPseudo + 0U, // VLD2DUPq8OddPseudoWB_fixed + 0U, // VLD2DUPq8OddPseudoWB_register + 28617013U, // VLD2LNd16 + 0U, // VLD2LNd16Pseudo + 0U, // VLD2LNd16Pseudo_UPD + 28625205U, // VLD2LNd16_UPD + 29141301U, // VLD2LNd32 + 0U, // VLD2LNd32Pseudo + 0U, // VLD2LNd32Pseudo_UPD + 29149493U, // VLD2LNd32_UPD + 29665589U, // VLD2LNd8 + 0U, // VLD2LNd8Pseudo + 0U, // VLD2LNd8Pseudo_UPD + 29673781U, // VLD2LNd8_UPD + 28617013U, // VLD2LNq16 + 0U, // VLD2LNq16Pseudo + 0U, // VLD2LNq16Pseudo_UPD + 28625205U, // VLD2LNq16_UPD + 29141301U, // VLD2LNq32 + 0U, // VLD2LNq32Pseudo + 0U, // VLD2LNq32Pseudo_UPD + 29149493U, // VLD2LNq32_UPD + 2483611957U, // VLD2b16 + 2483595573U, // VLD2b16wb_fixed + 2483603765U, // VLD2b16wb_register + 2484136245U, // VLD2b32 + 2484119861U, // VLD2b32wb_fixed + 2484128053U, // VLD2b32wb_register + 2484660533U, // VLD2b8 + 2484644149U, // VLD2b8wb_fixed + 2484652341U, // VLD2b8wb_register + 2349394229U, // VLD2d16 + 2349377845U, // VLD2d16wb_fixed + 2349386037U, // VLD2d16wb_register + 2349918517U, // VLD2d32 + 2349902133U, // VLD2d32wb_fixed + 2349910325U, // VLD2d32wb_register + 2350442805U, // VLD2d8 + 2350426421U, // VLD2d8wb_fixed + 2350434613U, // VLD2d8wb_register + 537454901U, // VLD2q16 + 0U, // VLD2q16Pseudo + 0U, // VLD2q16PseudoWB_fixed + 0U, // VLD2q16PseudoWB_register + 537438517U, // VLD2q16wb_fixed + 537446709U, // VLD2q16wb_register + 537979189U, // VLD2q32 + 0U, // VLD2q32Pseudo + 0U, // VLD2q32PseudoWB_fixed + 0U, // VLD2q32PseudoWB_register + 537962805U, // VLD2q32wb_fixed + 537970997U, // VLD2q32wb_register + 538503477U, // VLD2q8 + 0U, // VLD2q8Pseudo + 0U, // VLD2q8PseudoWB_fixed + 0U, // VLD2q8PseudoWB_register + 538487093U, // VLD2q8wb_fixed + 538495285U, // VLD2q8wb_register + 28363098U, // VLD3DUPd16 + 0U, // VLD3DUPd16Pseudo + 0U, // VLD3DUPd16Pseudo_UPD + 28617050U, // VLD3DUPd16_UPD + 28887386U, // VLD3DUPd32 + 0U, // VLD3DUPd32Pseudo + 0U, // VLD3DUPd32Pseudo_UPD + 29141338U, // VLD3DUPd32_UPD + 29411674U, // VLD3DUPd8 + 0U, // VLD3DUPd8Pseudo + 0U, // VLD3DUPd8Pseudo_UPD + 29665626U, // VLD3DUPd8_UPD + 28363098U, // VLD3DUPq16 + 0U, // VLD3DUPq16EvenPseudo + 0U, // VLD3DUPq16OddPseudo + 0U, // VLD3DUPq16OddPseudo_UPD + 28617050U, // VLD3DUPq16_UPD + 28887386U, // VLD3DUPq32 + 0U, // VLD3DUPq32EvenPseudo + 0U, // VLD3DUPq32OddPseudo + 0U, // VLD3DUPq32OddPseudo_UPD + 29141338U, // VLD3DUPq32_UPD + 29411674U, // VLD3DUPq8 + 0U, // VLD3DUPq8EvenPseudo + 0U, // VLD3DUPq8OddPseudo + 0U, // VLD3DUPq8OddPseudo_UPD + 29665626U, // VLD3DUPq8_UPD + 28625242U, // VLD3LNd16 + 0U, // VLD3LNd16Pseudo + 0U, // VLD3LNd16Pseudo_UPD + 28633434U, // VLD3LNd16_UPD + 29149530U, // VLD3LNd32 + 0U, // VLD3LNd32Pseudo + 0U, // VLD3LNd32Pseudo_UPD + 29157722U, // VLD3LNd32_UPD + 29673818U, // VLD3LNd8 + 0U, // VLD3LNd8Pseudo + 0U, // VLD3LNd8Pseudo_UPD + 29682010U, // VLD3LNd8_UPD + 28625242U, // VLD3LNq16 + 0U, // VLD3LNq16Pseudo + 0U, // VLD3LNq16Pseudo_UPD + 28633434U, // VLD3LNq16_UPD + 29149530U, // VLD3LNq32 + 0U, // VLD3LNq32Pseudo + 0U, // VLD3LNq32Pseudo_UPD + 29157722U, // VLD3LNq32_UPD + 28363098U, // VLD3d16 + 0U, // VLD3d16Pseudo + 0U, // VLD3d16Pseudo_UPD + 28617050U, // VLD3d16_UPD + 28887386U, // VLD3d32 + 0U, // VLD3d32Pseudo + 0U, // VLD3d32Pseudo_UPD + 29141338U, // VLD3d32_UPD + 29411674U, // VLD3d8 + 0U, // VLD3d8Pseudo + 0U, // VLD3d8Pseudo_UPD + 29665626U, // VLD3d8_UPD + 28363098U, // VLD3q16 + 0U, // VLD3q16Pseudo_UPD + 28617050U, // VLD3q16_UPD + 0U, // VLD3q16oddPseudo + 0U, // VLD3q16oddPseudo_UPD + 28887386U, // VLD3q32 + 0U, // VLD3q32Pseudo_UPD + 29141338U, // VLD3q32_UPD + 0U, // VLD3q32oddPseudo + 0U, // VLD3q32oddPseudo_UPD + 29411674U, // VLD3q8 + 0U, // VLD3q8Pseudo_UPD + 29665626U, // VLD3q8_UPD + 0U, // VLD3q8oddPseudo + 0U, // VLD3q8oddPseudo_UPD + 28445046U, // VLD4DUPd16 + 0U, // VLD4DUPd16Pseudo + 0U, // VLD4DUPd16Pseudo_UPD + 28641654U, // VLD4DUPd16_UPD + 28969334U, // VLD4DUPd32 + 0U, // VLD4DUPd32Pseudo + 0U, // VLD4DUPd32Pseudo_UPD + 29165942U, // VLD4DUPd32_UPD + 29493622U, // VLD4DUPd8 + 0U, // VLD4DUPd8Pseudo + 0U, // VLD4DUPd8Pseudo_UPD + 29690230U, // VLD4DUPd8_UPD + 28445046U, // VLD4DUPq16 + 0U, // VLD4DUPq16EvenPseudo + 0U, // VLD4DUPq16OddPseudo + 0U, // VLD4DUPq16OddPseudo_UPD + 28641654U, // VLD4DUPq16_UPD + 28969334U, // VLD4DUPq32 + 0U, // VLD4DUPq32EvenPseudo + 0U, // VLD4DUPq32OddPseudo + 0U, // VLD4DUPq32OddPseudo_UPD + 29165942U, // VLD4DUPq32_UPD + 29493622U, // VLD4DUPq8 + 0U, // VLD4DUPq8EvenPseudo + 0U, // VLD4DUPq8OddPseudo + 0U, // VLD4DUPq8OddPseudo_UPD + 29690230U, // VLD4DUPq8_UPD + 28633462U, // VLD4LNd16 + 0U, // VLD4LNd16Pseudo + 0U, // VLD4LNd16Pseudo_UPD + 28649846U, // VLD4LNd16_UPD + 29157750U, // VLD4LNd32 + 0U, // VLD4LNd32Pseudo + 0U, // VLD4LNd32Pseudo_UPD + 29174134U, // VLD4LNd32_UPD + 29682038U, // VLD4LNd8 + 0U, // VLD4LNd8Pseudo + 0U, // VLD4LNd8Pseudo_UPD + 29698422U, // VLD4LNd8_UPD + 28633462U, // VLD4LNq16 + 0U, // VLD4LNq16Pseudo + 0U, // VLD4LNq16Pseudo_UPD + 28649846U, // VLD4LNq16_UPD + 29157750U, // VLD4LNq32 + 0U, // VLD4LNq32Pseudo + 0U, // VLD4LNq32Pseudo_UPD + 29174134U, // VLD4LNq32_UPD + 28445046U, // VLD4d16 + 0U, // VLD4d16Pseudo + 0U, // VLD4d16Pseudo_UPD + 28641654U, // VLD4d16_UPD + 28969334U, // VLD4d32 + 0U, // VLD4d32Pseudo + 0U, // VLD4d32Pseudo_UPD + 29165942U, // VLD4d32_UPD + 29493622U, // VLD4d8 + 0U, // VLD4d8Pseudo + 0U, // VLD4d8Pseudo_UPD + 29690230U, // VLD4d8_UPD + 28445046U, // VLD4q16 + 0U, // VLD4q16Pseudo_UPD + 28641654U, // VLD4q16_UPD + 0U, // VLD4q16oddPseudo + 0U, // VLD4q16oddPseudo_UPD + 28969334U, // VLD4q32 + 0U, // VLD4q32Pseudo_UPD + 29165942U, // VLD4q32_UPD + 0U, // VLD4q32oddPseudo + 0U, // VLD4q32oddPseudo_UPD + 29493622U, // VLD4q8 + 0U, // VLD4q8Pseudo_UPD + 29690230U, // VLD4q8_UPD + 0U, // VLD4q8oddPseudo + 0U, // VLD4q8oddPseudo_UPD + 875064290U, // VLDMDDB_UPD + 2730766U, // VLDMDIA + 875064078U, // VLDMDIA_UPD + 0U, // VLDMQIA + 875064290U, // VLDMSDB_UPD + 2730766U, // VLDMSIA + 875064078U, // VLDMSIA_UPD + 2683301U, // VLDRD + 586149U, // VLDRH + 2683301U, // VLDRS + 2580050341U, // VLDR_FPCXTNS_off + 701034917U, // VLDR_FPCXTNS_post + 2647191973U, // VLDR_FPCXTNS_pre + 2580574629U, // VLDR_FPCXTS_off + 701559205U, // VLDR_FPCXTS_post + 2647716261U, // VLDR_FPCXTS_pre + 2581098917U, // VLDR_FPSCR_NZCVQC_off + 702083493U, // VLDR_FPSCR_NZCVQC_post + 2648240549U, // VLDR_FPSCR_NZCVQC_pre + 2581623205U, // VLDR_FPSCR_off + 702607781U, // VLDR_FPSCR_post + 2648764837U, // VLDR_FPSCR_pre + 2716397989U, // VLDR_P0_off + 1642639781U, // VLDR_P0_post + 2783490469U, // VLDR_P0_pre + 2582671781U, // VLDR_VPR_off + 703656357U, // VLDR_VPR_post + 2649813413U, // VLDR_VPR_pre + 2732105U, // VLLDM + 2732140U, // VLSTM + 7926951U, // VMAXfd + 7926951U, // VMAXfq + 7402663U, // VMAXhd + 7402663U, // VMAXhq + 12121255U, // VMAXsv16i8 + 11596967U, // VMAXsv2i32 + 11072679U, // VMAXsv4i16 + 11596967U, // VMAXsv4i32 + 11072679U, // VMAXsv8i16 + 12121255U, // VMAXsv8i8 + 13694119U, // VMAXuv16i8 + 13169831U, // VMAXuv2i32 + 12645543U, // VMAXuv4i16 + 13169831U, // VMAXuv4i32 + 12645543U, // VMAXuv8i16 + 13694119U, // VMAXuv8i8 + 7925916U, // VMINfd + 7925916U, // VMINfq + 7401628U, // VMINhd + 7401628U, // VMINhq + 12120220U, // VMINsv16i8 + 11595932U, // VMINsv2i32 + 11071644U, // VMINsv4i16 + 11595932U, // VMINsv4i32 + 11071644U, // VMINsv8i16 + 12120220U, // VMINsv8i8 + 13693084U, // VMINuv16i8 + 13168796U, // VMINuv2i32 + 12644508U, // VMINuv4i16 + 13168796U, // VMINuv4i32 + 12644508U, // VMINuv8i16 + 13693084U, // VMINuv8i8 + 1147710260U, // VMLAD + 7383860U, // VMLAH + 11587401U, // VMLALslsv2i32 + 11063113U, // VMLALslsv4i16 + 13160265U, // VMLALsluv2i32 + 12635977U, // VMLALsluv4i16 + 11579209U, // VMLALsv2i64 + 11054921U, // VMLALsv4i32 + 12103497U, // VMLALsv8i16 + 13152073U, // VMLALuv2i64 + 12627785U, // VMLALuv4i32 + 13676361U, // VMLALuv8i16 + 7908148U, // VMLAS + 7908148U, // VMLAfd + 7908148U, // VMLAfq + 7383860U, // VMLAhd + 7383860U, // VMLAhq + 7916340U, // VMLAslfd + 7916340U, // VMLAslfq + 7392052U, // VMLAslhd + 7392052U, // VMLAslhq + 14207796U, // VMLAslv2i32 + 14732084U, // VMLAslv4i16 + 14207796U, // VMLAslv4i32 + 14732084U, // VMLAslv8i16 + 15248180U, // VMLAv16i8 + 14199604U, // VMLAv2i32 + 14723892U, // VMLAv4i16 + 14199604U, // VMLAv4i32 + 14723892U, // VMLAv8i16 + 15248180U, // VMLAv8i8 + 1147712055U, // VMLSD + 7385655U, // VMLSH + 11587618U, // VMLSLslsv2i32 + 11063330U, // VMLSLslsv4i16 + 13160482U, // VMLSLsluv2i32 + 12636194U, // VMLSLsluv4i16 + 11579426U, // VMLSLsv2i64 + 11055138U, // VMLSLsv4i32 + 12103714U, // VMLSLsv8i16 + 13152290U, // VMLSLuv2i64 + 12628002U, // VMLSLuv4i32 + 13676578U, // VMLSLuv8i16 + 7909943U, // VMLSS + 7909943U, // VMLSfd + 7909943U, // VMLSfq + 7385655U, // VMLShd + 7385655U, // VMLShq + 7918135U, // VMLSslfd + 7918135U, // VMLSslfq + 7393847U, // VMLSslhd + 7393847U, // VMLSslhq + 14209591U, // VMLSslv2i32 + 14733879U, // VMLSslv4i16 + 14209591U, // VMLSslv4i32 + 14733879U, // VMLSslv8i16 + 15249975U, // VMLSv16i8 + 14201399U, // VMLSv2i32 + 14725687U, // VMLSv4i16 + 14201399U, // VMLSv4i32 + 14725687U, // VMLSv8i16 + 15249975U, // VMLSv8i8 + 808543674U, // VMMLA + 1147696202U, // VMOVD + 2683978U, // VMOVDRR + 875644323U, // VMOVH + 7369802U, // VMOVHR + 11563075U, // VMOVLsv2i64 + 11038787U, // VMOVLsv4i32 + 12087363U, // VMOVLsv8i16 + 13135939U, // VMOVLuv2i64 + 12611651U, // VMOVLuv4i32 + 13660227U, // VMOVLuv8i16 + 895512829U, // VMOVNv2i32 + 14184701U, // VMOVNv4i16 + 14708989U, // VMOVNv8i8 + 7369802U, // VMOVRH + 2683978U, // VMOVRRD + 2667594U, // VMOVRRS + 2651210U, // VMOVRS + 7894090U, // VMOVS + 2651210U, // VMOVSR + 2667594U, // VMOVSRR + 15234122U, // VMOVv16i8 + 2036364362U, // VMOVv1i64 + 7894090U, // VMOVv2f32 + 14185546U, // VMOVv2i32 + 2036364362U, // VMOVv2i64 + 7894090U, // VMOVv4f32 + 14709834U, // VMOVv4i16 + 14185546U, // VMOVv4i32 + 14709834U, // VMOVv8i16 + 15234122U, // VMOVv8i8 + 2732633U, // VMRS + 2732633U, // VMRS_FPCXTNS + 2732633U, // VMRS_FPCXTS + 2732633U, // VMRS_FPEXC + 2732633U, // VMRS_FPINST + 2732633U, // VMRS_FPINST2 + 2650713U, // VMRS_FPSCR_NZCVQC + 2732633U, // VMRS_FPSID + 2732633U, // VMRS_MVFR0 + 2732633U, // VMRS_MVFR1 + 2732633U, // VMRS_MVFR2 + 2650713U, // VMRS_P0 + 2732633U, // VMRS_VPR + 31568365U, // VMSR + 29995501U, // VMSR_FPCXTNS + 30519789U, // VMSR_FPCXTS + 33141229U, // VMSR_FPEXC + 33665517U, // VMSR_FPINST + 34189805U, // VMSR_FPINST2 + 903377389U, // VMSR_FPSCR_NZCVQC + 34714093U, // VMSR_FPSID + 904425965U, // VMSR_P0 + 32616941U, // VMSR_VPR + 1147727934U, // VMULD + 7401534U, // VMULH + 875643746U, // VMULLp64 + 24178671U, // VMULLp8 + 11579375U, // VMULLslsv2i32 + 11055087U, // VMULLslsv4i16 + 13152239U, // VMULLsluv2i32 + 12627951U, // VMULLsluv4i16 + 11595759U, // VMULLsv2i64 + 11071471U, // VMULLsv4i32 + 12120047U, // VMULLsv8i16 + 13168623U, // VMULLuv2i64 + 12644335U, // VMULLuv4i32 + 13692911U, // VMULLuv8i16 + 7925822U, // VMULS + 7925822U, // VMULfd + 7925822U, // VMULfq + 7401534U, // VMULhd + 7401534U, // VMULhq + 24178750U, // VMULpd + 24178750U, // VMULpq + 7909438U, // VMULslfd + 7909438U, // VMULslfq + 7385150U, // VMULslhd + 7385150U, // VMULslhq + 14200894U, // VMULslv2i32 + 14725182U, // VMULslv4i16 + 14200894U, // VMULslv4i32 + 14725182U, // VMULslv8i16 + 15265854U, // VMULv16i8 + 14217278U, // VMULv2i32 + 14741566U, // VMULv4i16 + 14217278U, // VMULv4i32 + 14741566U, // VMULv8i16 + 15265854U, // VMULv8i8 + 2650353U, // VMVNd + 2650353U, // VMVNq + 14184689U, // VMVNv2i32 + 14708977U, // VMVNv4i16 + 14184689U, // VMVNv4i32 + 14708977U, // VMVNv8i16 + 1147694595U, // VNEGD + 7368195U, // VNEGH + 7892483U, // VNEGS + 7892483U, // VNEGf32q + 7892483U, // VNEGfd + 7368195U, // VNEGhd + 7368195U, // VNEGhq + 11038211U, // VNEGs16d + 11038211U, // VNEGs16q + 11562499U, // VNEGs32d + 11562499U, // VNEGs32q + 12086787U, // VNEGs8d + 12086787U, // VNEGs8q + 1147710254U, // VNMLAD + 7383854U, // VNMLAH + 7908142U, // VNMLAS + 1147712049U, // VNMLSD + 7385649U, // VNMLSH + 7909937U, // VNMLSS + 1147727928U, // VNMULD + 7401528U, // VNMULH + 7925816U, // VNMULS + 2683073U, // VORNd + 2683073U, // VORNq + 2683357U, // VORRd + 14217693U, // VORRiv2i32 + 14741981U, // VORRiv4i16 + 14217693U, // VORRiv4i32 + 14741981U, // VORRiv8i16 + 2683357U, // VORRq + 12119854U, // VPADALsv16i8 + 11595566U, // VPADALsv2i32 + 11071278U, // VPADALsv4i16 + 11595566U, // VPADALsv4i32 + 11071278U, // VPADALsv8i16 + 12119854U, // VPADALsv8i8 + 13692718U, // VPADALuv16i8 + 13168430U, // VPADALuv2i32 + 12644142U, // VPADALuv4i16 + 13168430U, // VPADALuv4i32 + 12644142U, // VPADALuv8i16 + 13692718U, // VPADALuv8i8 + 12087146U, // VPADDLsv16i8 + 11562858U, // VPADDLsv2i32 + 11038570U, // VPADDLsv4i16 + 11562858U, // VPADDLsv4i32 + 11038570U, // VPADDLsv8i16 + 12087146U, // VPADDLsv8i8 + 13660010U, // VPADDLuv16i8 + 13135722U, // VPADDLuv2i32 + 12611434U, // VPADDLuv4i16 + 13135722U, // VPADDLuv4i32 + 12611434U, // VPADDLuv8i16 + 13660010U, // VPADDLuv8i8 + 7925099U, // VPADDf + 7400811U, // VPADDh + 14740843U, // VPADDi16 + 14216555U, // VPADDi32 + 15265131U, // VPADDi8 + 7926945U, // VPMAXf + 7402657U, // VPMAXh + 11072673U, // VPMAXs16 + 11596961U, // VPMAXs32 + 12121249U, // VPMAXs8 + 12645537U, // VPMAXu16 + 13169825U, // VPMAXu32 + 13694113U, // VPMAXu8 + 7925910U, // VPMINf + 7401622U, // VPMINh + 11071638U, // VPMINs16 + 11595926U, // VPMINs32 + 12120214U, // VPMINs8 + 12644502U, // VPMINu16 + 13168790U, // VPMINu32 + 13693078U, // VPMINu8 + 12087830U, // VQABSv16i8 + 11563542U, // VQABSv2i32 + 11039254U, // VQABSv4i16 + 11563542U, // VQABSv4i32 + 11039254U, // VQABSv8i16 + 12087830U, // VQABSv8i8 + 12119409U, // VQADDsv16i8 + 907603313U, // VQADDsv1i64 + 11595121U, // VQADDsv2i32 + 907603313U, // VQADDsv2i64 + 11070833U, // VQADDsv4i16 + 11595121U, // VQADDsv4i32 + 11070833U, // VQADDsv8i16 + 12119409U, // VQADDsv8i8 + 13692273U, // VQADDuv16i8 + 22605169U, // VQADDuv1i64 + 13167985U, // VQADDuv2i32 + 22605169U, // VQADDuv2i64 + 12643697U, // VQADDuv4i16 + 13167985U, // VQADDuv4i32 + 12643697U, // VQADDuv8i16 + 13692273U, // VQADDuv8i8 + 11587381U, // VQDMLALslv2i32 + 11063093U, // VQDMLALslv4i16 + 11579189U, // VQDMLALv2i64 + 11054901U, // VQDMLALv4i32 + 11587610U, // VQDMLSLslv2i32 + 11063322U, // VQDMLSLslv4i16 + 11579418U, // VQDMLSLv2i64 + 11055130U, // VQDMLSLv4i32 + 11578977U, // VQDMULHslv2i32 + 11054689U, // VQDMULHslv4i16 + 11578977U, // VQDMULHslv4i32 + 11054689U, // VQDMULHslv8i16 + 11595361U, // VQDMULHv2i32 + 11071073U, // VQDMULHv4i16 + 11595361U, // VQDMULHv4i32 + 11071073U, // VQDMULHv8i16 + 11579355U, // VQDMULLslv2i32 + 11055067U, // VQDMULLslv4i16 + 11595739U, // VQDMULLv2i64 + 11071451U, // VQDMULLv4i32 + 907571433U, // VQMOVNsuv2i32 + 11563241U, // VQMOVNsuv4i16 + 11038953U, // VQMOVNsuv8i8 + 907571446U, // VQMOVNsv2i32 + 11563254U, // VQMOVNsv4i16 + 11038966U, // VQMOVNsv8i8 + 22573302U, // VQMOVNuv2i32 + 13136118U, // VQMOVNuv4i16 + 12611830U, // VQMOVNuv8i8 + 12086781U, // VQNEGv16i8 + 11562493U, // VQNEGv2i32 + 11038205U, // VQNEGv4i16 + 11562493U, // VQNEGv4i32 + 11038205U, // VQNEGv8i16 + 12086781U, // VQNEGv8i8 + 11587101U, // VQRDMLAHslv2i32 + 11062813U, // VQRDMLAHslv4i16 + 11587101U, // VQRDMLAHslv4i32 + 11062813U, // VQRDMLAHslv8i16 + 11578909U, // VQRDMLAHv2i32 + 11054621U, // VQRDMLAHv4i16 + 11578909U, // VQRDMLAHv4i32 + 11054621U, // VQRDMLAHv8i16 + 11587230U, // VQRDMLSHslv2i32 + 11062942U, // VQRDMLSHslv4i16 + 11587230U, // VQRDMLSHslv4i32 + 11062942U, // VQRDMLSHslv8i16 + 11579038U, // VQRDMLSHv2i32 + 11054750U, // VQRDMLSHv4i16 + 11579038U, // VQRDMLSHv4i32 + 11054750U, // VQRDMLSHv8i16 + 11578985U, // VQRDMULHslv2i32 + 11054697U, // VQRDMULHslv4i16 + 11578985U, // VQRDMULHslv4i32 + 11054697U, // VQRDMULHslv8i16 + 11595369U, // VQRDMULHv2i32 + 11071081U, // VQRDMULHv4i16 + 11595369U, // VQRDMULHv4i32 + 11071081U, // VQRDMULHv8i16 + 12119962U, // VQRSHLsv16i8 + 907603866U, // VQRSHLsv1i64 + 11595674U, // VQRSHLsv2i32 + 907603866U, // VQRSHLsv2i64 + 11071386U, // VQRSHLsv4i16 + 11595674U, // VQRSHLsv4i32 + 11071386U, // VQRSHLsv8i16 + 12119962U, // VQRSHLsv8i8 + 13692826U, // VQRSHLuv16i8 + 22605722U, // VQRSHLuv1i64 + 13168538U, // VQRSHLuv2i32 + 22605722U, // VQRSHLuv2i64 + 12644250U, // VQRSHLuv4i16 + 13168538U, // VQRSHLuv4i32 + 12644250U, // VQRSHLuv8i16 + 13692826U, // VQRSHLuv8i8 + 907604140U, // VQRSHRNsv2i32 + 11595948U, // VQRSHRNsv4i16 + 11071660U, // VQRSHRNsv8i8 + 22605996U, // VQRSHRNuv2i32 + 13168812U, // VQRSHRNuv4i16 + 12644524U, // VQRSHRNuv8i8 + 907604192U, // VQRSHRUNv2i32 + 11596000U, // VQRSHRUNv4i16 + 11071712U, // VQRSHRUNv8i8 + 12119949U, // VQSHLsiv16i8 + 907603853U, // VQSHLsiv1i64 + 11595661U, // VQSHLsiv2i32 + 907603853U, // VQSHLsiv2i64 + 11071373U, // VQSHLsiv4i16 + 11595661U, // VQSHLsiv4i32 + 11071373U, // VQSHLsiv8i16 + 12119949U, // VQSHLsiv8i8 + 12121029U, // VQSHLsuv16i8 + 907604933U, // VQSHLsuv1i64 + 11596741U, // VQSHLsuv2i32 + 907604933U, // VQSHLsuv2i64 + 11072453U, // VQSHLsuv4i16 + 11596741U, // VQSHLsuv4i32 + 11072453U, // VQSHLsuv8i16 + 12121029U, // VQSHLsuv8i8 + 12119949U, // VQSHLsv16i8 + 907603853U, // VQSHLsv1i64 + 11595661U, // VQSHLsv2i32 + 907603853U, // VQSHLsv2i64 + 11071373U, // VQSHLsv4i16 + 11595661U, // VQSHLsv4i32 + 11071373U, // VQSHLsv8i16 + 12119949U, // VQSHLsv8i8 + 13692813U, // VQSHLuiv16i8 + 22605709U, // VQSHLuiv1i64 + 13168525U, // VQSHLuiv2i32 + 22605709U, // VQSHLuiv2i64 + 12644237U, // VQSHLuiv4i16 + 13168525U, // VQSHLuiv4i32 + 12644237U, // VQSHLuiv8i16 + 13692813U, // VQSHLuiv8i8 + 13692813U, // VQSHLuv16i8 + 22605709U, // VQSHLuv1i64 + 13168525U, // VQSHLuv2i32 + 22605709U, // VQSHLuv2i64 + 12644237U, // VQSHLuv4i16 + 13168525U, // VQSHLuv4i32 + 12644237U, // VQSHLuv8i16 + 13692813U, // VQSHLuv8i8 + 907604133U, // VQSHRNsv2i32 + 11595941U, // VQSHRNsv4i16 + 11071653U, // VQSHRNsv8i8 + 22605989U, // VQSHRNuv2i32 + 13168805U, // VQSHRNuv4i16 + 12644517U, // VQSHRNuv8i8 + 907604184U, // VQSHRUNv2i32 + 11595992U, // VQSHRUNv4i16 + 11071704U, // VQSHRUNv8i8 + 12119247U, // VQSUBsv16i8 + 907603151U, // VQSUBsv1i64 + 11594959U, // VQSUBsv2i32 + 907603151U, // VQSUBsv2i64 + 11070671U, // VQSUBsv4i16 + 11594959U, // VQSUBsv4i32 + 11070671U, // VQSUBsv8i16 + 12119247U, // VQSUBsv8i8 + 13692111U, // VQSUBuv16i8 + 22605007U, // VQSUBuv1i64 + 13167823U, // VQSUBuv2i32 + 22605007U, // VQSUBuv2i64 + 12643535U, // VQSUBuv4i16 + 13167823U, // VQSUBuv4i32 + 12643535U, // VQSUBuv8i16 + 13692111U, // VQSUBuv8i8 + 895545479U, // VRADDHNv2i32 + 14217351U, // VRADDHNv4i16 + 14741639U, // VRADDHNv8i8 + 13135319U, // VRECPEd + 7892439U, // VRECPEfd + 7892439U, // VRECPEfq + 7368151U, // VRECPEhd + 7368151U, // VRECPEhq + 13135319U, // VRECPEq + 7926354U, // VRECPSfd + 7926354U, // VRECPSfq + 7402066U, // VRECPShd + 7402066U, // VRECPShq + 1599992U, // VREV16d8 + 1599992U, // VREV16q8 + 551193U, // VREV32d16 + 1599769U, // VREV32d8 + 551193U, // VREV32q16 + 1599769U, // VREV32q8 + 551279U, // VREV64d16 + 1075567U, // VREV64d32 + 1599855U, // VREV64d8 + 551279U, // VREV64q16 + 1075567U, // VREV64q32 + 1599855U, // VREV64q8 + 12119390U, // VRHADDsv16i8 + 11595102U, // VRHADDsv2i32 + 11070814U, // VRHADDsv4i16 + 11595102U, // VRHADDsv4i32 + 11070814U, // VRHADDsv8i16 + 12119390U, // VRHADDsv8i8 + 13692254U, // VRHADDuv16i8 + 13167966U, // VRHADDuv2i32 + 12643678U, // VRHADDuv4i16 + 13167966U, // VRHADDuv4i32 + 12643678U, // VRHADDuv8i16 + 13692254U, // VRHADDuv8i8 + 875643626U, // VRINTAD + 875644148U, // VRINTAH + 875643275U, // VRINTANDf + 875644148U, // VRINTANDh + 875643275U, // VRINTANQf + 875644148U, // VRINTANQh + 875643275U, // VRINTAS + 875643674U, // VRINTMD + 875644229U, // VRINTMH + 875643334U, // VRINTMNDf + 875644229U, // VRINTMNDh + 875643334U, // VRINTMNQf + 875644229U, // VRINTMNQh + 875643334U, // VRINTMS + 875643686U, // VRINTND + 875644241U, // VRINTNH + 875643346U, // VRINTNNDf + 875644241U, // VRINTNNDh + 875643346U, // VRINTNNQf + 875644241U, // VRINTNNQh + 875643346U, // VRINTNS + 875643698U, // VRINTPD + 875644253U, // VRINTPH + 875643358U, // VRINTPNDf + 875644253U, // VRINTPNDh + 875643358U, // VRINTPNQf + 875644253U, // VRINTPNQh + 875643358U, // VRINTPS + 1147695608U, // VRINTRD + 7369208U, // VRINTRH + 7893496U, // VRINTRS + 1147696582U, // VRINTXD + 7370182U, // VRINTXH + 875643406U, // VRINTXNDf + 875644311U, // VRINTXNDh + 875643406U, // VRINTXNQf + 875644311U, // VRINTXNQh + 7894470U, // VRINTXS + 1147696632U, // VRINTZD + 7370232U, // VRINTZH + 875643418U, // VRINTZNDf + 875644334U, // VRINTZNDh + 875643418U, // VRINTZNQf + 875644334U, // VRINTZNQh + 7894520U, // VRINTZS + 12119969U, // VRSHLsv16i8 + 907603873U, // VRSHLsv1i64 + 11595681U, // VRSHLsv2i32 + 907603873U, // VRSHLsv2i64 + 11071393U, // VRSHLsv4i16 + 11595681U, // VRSHLsv4i32 + 11071393U, // VRSHLsv8i16 + 12119969U, // VRSHLsv8i8 + 13692833U, // VRSHLuv16i8 + 22605729U, // VRSHLuv1i64 + 13168545U, // VRSHLuv2i32 + 22605729U, // VRSHLuv2i64 + 12644257U, // VRSHLuv4i16 + 13168545U, // VRSHLuv4i32 + 12644257U, // VRSHLuv8i16 + 13692833U, // VRSHLuv8i8 + 895545524U, // VRSHRNv2i32 + 14217396U, // VRSHRNv4i16 + 14741684U, // VRSHRNv8i8 + 12120509U, // VRSHRsv16i8 + 907604413U, // VRSHRsv1i64 + 11596221U, // VRSHRsv2i32 + 907604413U, // VRSHRsv2i64 + 11071933U, // VRSHRsv4i16 + 11596221U, // VRSHRsv4i32 + 11071933U, // VRSHRsv8i16 + 12120509U, // VRSHRsv8i8 + 13693373U, // VRSHRuv16i8 + 22606269U, // VRSHRuv1i64 + 13169085U, // VRSHRuv2i32 + 22606269U, // VRSHRuv2i64 + 12644797U, // VRSHRuv4i16 + 13169085U, // VRSHRuv4i32 + 12644797U, // VRSHRuv8i16 + 13693373U, // VRSHRuv8i8 + 13135332U, // VRSQRTEd + 7892452U, // VRSQRTEfd + 7892452U, // VRSQRTEfq + 7368164U, // VRSQRTEhd + 7368164U, // VRSQRTEhq + 13135332U, // VRSQRTEq + 7926376U, // VRSQRTSfd + 7926376U, // VRSQRTSfq + 7402088U, // VRSQRTShd + 7402088U, // VRSQRTShq + 12102490U, // VRSRAsv16i8 + 840477530U, // VRSRAsv1i64 + 11578202U, // VRSRAsv2i32 + 840477530U, // VRSRAsv2i64 + 11053914U, // VRSRAsv4i16 + 11578202U, // VRSRAsv4i32 + 11053914U, // VRSRAsv8i16 + 12102490U, // VRSRAsv8i8 + 13675354U, // VRSRAuv16i8 + 22588250U, // VRSRAuv1i64 + 13151066U, // VRSRAuv2i32 + 22588250U, // VRSRAuv2i64 + 12626778U, // VRSRAuv4i16 + 13151066U, // VRSRAuv4i32 + 12626778U, // VRSRAuv8i16 + 13675354U, // VRSRAuv8i8 + 895545464U, // VRSUBHNv2i32 + 14217336U, // VRSUBHNv4i16 + 14741624U, // VRSUBHNv8i8 + 2821312605U, // VSCCLRMD + 2821312605U, // VSCCLRMS + 808543916U, // VSDOTD + 808543916U, // VSDOTDI + 808543916U, // VSDOTQ + 808543916U, // VSDOTQI + 875643710U, // VSELEQD + 875644265U, // VSELEQH + 875643370U, // VSELEQS + 875643638U, // VSELGED + 875644171U, // VSELGEH + 875643298U, // VSELGES + 875643734U, // VSELGTD + 875644299U, // VSELGTH + 875643394U, // VSELGTS + 875643722U, // VSELVSD + 875644287U, // VSELVSH + 875643382U, // VSELVSS + 570442U, // VSETLNi16 + 1094730U, // VSETLNi32 + 1619018U, // VSETLNi8 + 14741456U, // VSHLLi16 + 14217168U, // VSHLLi32 + 15265744U, // VSHLLi8 + 11595728U, // VSHLLsv2i64 + 11071440U, // VSHLLsv4i32 + 12120016U, // VSHLLsv8i16 + 13168592U, // VSHLLuv2i64 + 12644304U, // VSHLLuv4i32 + 13692880U, // VSHLLuv8i16 + 15265703U, // VSHLiv16i8 + 895545255U, // VSHLiv1i64 + 14217127U, // VSHLiv2i32 + 895545255U, // VSHLiv2i64 + 14741415U, // VSHLiv4i16 + 14217127U, // VSHLiv4i32 + 14741415U, // VSHLiv8i16 + 15265703U, // VSHLiv8i8 + 12119975U, // VSHLsv16i8 + 907603879U, // VSHLsv1i64 + 11595687U, // VSHLsv2i32 + 907603879U, // VSHLsv2i64 + 11071399U, // VSHLsv4i16 + 11595687U, // VSHLsv4i32 + 11071399U, // VSHLsv8i16 + 12119975U, // VSHLsv8i8 + 13692839U, // VSHLuv16i8 + 22605735U, // VSHLuv1i64 + 13168551U, // VSHLuv2i32 + 22605735U, // VSHLuv2i64 + 12644263U, // VSHLuv4i16 + 13168551U, // VSHLuv4i32 + 12644263U, // VSHLuv8i16 + 13692839U, // VSHLuv8i8 + 895545531U, // VSHRNv2i32 + 14217403U, // VSHRNv4i16 + 14741691U, // VSHRNv8i8 + 12120515U, // VSHRsv16i8 + 907604419U, // VSHRsv1i64 + 11596227U, // VSHRsv2i32 + 907604419U, // VSHRsv2i64 + 11071939U, // VSHRsv4i16 + 11596227U, // VSHRsv4i32 + 11071939U, // VSHRsv8i16 + 12120515U, // VSHRsv8i8 + 13693379U, // VSHRuv16i8 + 22606275U, // VSHRuv1i64 + 13169091U, // VSHRuv2i32 + 22606275U, // VSHRuv2i64 + 12644803U, // VSHRuv4i16 + 13169091U, // VSHRuv4i32 + 12644803U, // VSHRuv8i16 + 13693379U, // VSHRuv8i8 + 35713960U, // VSHTOD + 1157690280U, // VSHTOH + 36238248U, // VSHTOS + 1110471592U, // VSITOD + 1110995880U, // VSITOH + 1092121512U, // VSITOS + 1617672U, // VSLIv16i8 + 15773448U, // VSLIv1i64 + 1093384U, // VSLIv2i32 + 15773448U, // VSLIv2i64 + 569096U, // VSLIv4i16 + 1093384U, // VSLIv4i32 + 569096U, // VSLIv8i16 + 1617672U, // VSLIv8i8 + 1177613224U, // VSLTOD + 1178137512U, // VSLTOH + 1159263144U, // VSLTOS + 808543894U, // VSMMLA + 1147695975U, // VSQRTD + 7369575U, // VSQRTH + 7893863U, // VSQRTS + 12102496U, // VSRAsv16i8 + 840477536U, // VSRAsv1i64 + 11578208U, // VSRAsv2i32 + 840477536U, // VSRAsv2i64 + 11053920U, // VSRAsv4i16 + 11578208U, // VSRAsv4i32 + 11053920U, // VSRAsv8i16 + 12102496U, // VSRAsv8i8 + 13675360U, // VSRAuv16i8 + 22588256U, // VSRAuv1i64 + 13151072U, // VSRAuv2i32 + 22588256U, // VSRAuv2i64 + 12626784U, // VSRAuv4i16 + 13151072U, // VSRAuv4i32 + 12626784U, // VSRAuv8i16 + 13675360U, // VSRAuv8i8 + 1617677U, // VSRIv16i8 + 15773453U, // VSRIv1i64 + 1093389U, // VSRIv2i32 + 15773453U, // VSRIv2i64 + 569101U, // VSRIv4i16 + 1093389U, // VSRIv4i32 + 569101U, // VSRIv8i16 + 1617677U, // VSRIv8i8 + 833661199U, // VST1LNd16 + 2914126095U, // VST1LNd16_UPD + 834185487U, // VST1LNd32 + 2914650383U, // VST1LNd32_UPD + 834709775U, // VST1LNd8 + 2915174671U, // VST1LNd8_UPD + 0U, // VST1LNq16Pseudo + 0U, // VST1LNq16Pseudo_UPD + 0U, // VST1LNq32Pseudo + 0U, // VST1LNq32Pseudo_UPD + 0U, // VST1LNq8Pseudo + 0U, // VST1LNq8Pseudo_UPD + 2953373967U, // VST1d16 + 3020482831U, // VST1d16Q + 0U, // VST1d16QPseudo + 0U, // VST1d16QPseudoWB_fixed + 0U, // VST1d16QPseudoWB_register + 3087575311U, // VST1d16Qwb_fixed + 3154692367U, // VST1d16Qwb_register + 3221809423U, // VST1d16T + 0U, // VST1d16TPseudo + 0U, // VST1d16TPseudoWB_fixed + 0U, // VST1d16TPseudoWB_register + 3288901903U, // VST1d16Twb_fixed + 3356018959U, // VST1d16Twb_register + 3423119631U, // VST1d16wb_fixed + 3490236687U, // VST1d16wb_register + 2953898255U, // VST1d32 + 3021007119U, // VST1d32Q + 0U, // VST1d32QPseudo + 0U, // VST1d32QPseudoWB_fixed + 0U, // VST1d32QPseudoWB_register + 3088099599U, // VST1d32Qwb_fixed + 3155216655U, // VST1d32Qwb_register + 3222333711U, // VST1d32T + 0U, // VST1d32TPseudo + 0U, // VST1d32TPseudoWB_fixed + 0U, // VST1d32TPseudoWB_register + 3289426191U, // VST1d32Twb_fixed + 3356543247U, // VST1d32Twb_register + 3423643919U, // VST1d32wb_fixed + 3490760975U, // VST1d32wb_register + 2968578319U, // VST1d64 + 3035687183U, // VST1d64Q + 0U, // VST1d64QPseudo + 0U, // VST1d64QPseudoWB_fixed + 0U, // VST1d64QPseudoWB_register + 3102779663U, // VST1d64Qwb_fixed + 3169896719U, // VST1d64Qwb_register + 3237013775U, // VST1d64T + 0U, // VST1d64TPseudo + 0U, // VST1d64TPseudoWB_fixed + 0U, // VST1d64TPseudoWB_register + 3304106255U, // VST1d64Twb_fixed + 3371223311U, // VST1d64Twb_register + 3438323983U, // VST1d64wb_fixed + 3505441039U, // VST1d64wb_register + 2954422543U, // VST1d8 + 3021531407U, // VST1d8Q + 0U, // VST1d8QPseudo + 0U, // VST1d8QPseudoWB_fixed + 0U, // VST1d8QPseudoWB_register + 3088623887U, // VST1d8Qwb_fixed + 3155740943U, // VST1d8Qwb_register + 3222857999U, // VST1d8T + 0U, // VST1d8TPseudo + 0U, // VST1d8TPseudoWB_fixed + 0U, // VST1d8TPseudoWB_register + 3289950479U, // VST1d8Twb_fixed + 3357067535U, // VST1d8Twb_register + 3424168207U, // VST1d8wb_fixed + 3491285263U, // VST1d8wb_register + 3557353743U, // VST1q16 + 0U, // VST1q16HighQPseudo + 0U, // VST1q16HighQPseudo_UPD + 0U, // VST1q16HighTPseudo + 0U, // VST1q16HighTPseudo_UPD + 0U, // VST1q16LowQPseudo_UPD + 0U, // VST1q16LowTPseudo_UPD + 3624446223U, // VST1q16wb_fixed + 3691563279U, // VST1q16wb_register + 3557878031U, // VST1q32 + 0U, // VST1q32HighQPseudo + 0U, // VST1q32HighQPseudo_UPD + 0U, // VST1q32HighTPseudo + 0U, // VST1q32HighTPseudo_UPD + 0U, // VST1q32LowQPseudo_UPD + 0U, // VST1q32LowTPseudo_UPD + 3624970511U, // VST1q32wb_fixed + 3692087567U, // VST1q32wb_register + 3572558095U, // VST1q64 + 0U, // VST1q64HighQPseudo + 0U, // VST1q64HighQPseudo_UPD + 0U, // VST1q64HighTPseudo + 0U, // VST1q64HighTPseudo_UPD + 0U, // VST1q64LowQPseudo_UPD + 0U, // VST1q64LowTPseudo_UPD + 3639650575U, // VST1q64wb_fixed + 3706767631U, // VST1q64wb_register + 3558402319U, // VST1q8 + 0U, // VST1q8HighQPseudo + 0U, // VST1q8HighQPseudo_UPD + 0U, // VST1q8HighTPseudo + 0U, // VST1q8HighTPseudo_UPD + 0U, // VST1q8LowQPseudo_UPD + 0U, // VST1q8LowTPseudo_UPD + 3625494799U, // VST1q8wb_fixed + 3692611855U, // VST1q8wb_register + 833669456U, // VST2LNd16 + 0U, // VST2LNd16Pseudo + 0U, // VST2LNd16Pseudo_UPD + 2914298192U, // VST2LNd16_UPD + 834193744U, // VST2LNd32 + 0U, // VST2LNd32Pseudo + 0U, // VST2LNd32Pseudo_UPD + 2914822480U, // VST2LNd32_UPD + 834718032U, // VST2LNd8 + 0U, // VST2LNd8Pseudo + 0U, // VST2LNd8Pseudo_UPD + 2915346768U, // VST2LNd8_UPD + 833669456U, // VST2LNq16 + 0U, // VST2LNq16Pseudo + 0U, // VST2LNq16Pseudo_UPD + 2914298192U, // VST2LNq16_UPD + 834193744U, // VST2LNq32 + 0U, // VST2LNq32Pseudo + 0U, // VST2LNq32Pseudo_UPD + 2914822480U, // VST2LNq32_UPD + 3758680400U, // VST2b16 + 3825772880U, // VST2b16wb_fixed + 3892889936U, // VST2b16wb_register + 3759204688U, // VST2b32 + 3826297168U, // VST2b32wb_fixed + 3893414224U, // VST2b32wb_register + 3759728976U, // VST2b8 + 3826821456U, // VST2b8wb_fixed + 3893938512U, // VST2b8wb_register + 3557353808U, // VST2d16 + 3624446288U, // VST2d16wb_fixed + 3691563344U, // VST2d16wb_register + 3557878096U, // VST2d32 + 3624970576U, // VST2d32wb_fixed + 3692087632U, // VST2d32wb_register + 3558402384U, // VST2d8 + 3625494864U, // VST2d8wb_fixed + 3692611920U, // VST2d8wb_register + 3020482896U, // VST2q16 + 0U, // VST2q16Pseudo + 0U, // VST2q16PseudoWB_fixed + 0U, // VST2q16PseudoWB_register + 3087575376U, // VST2q16wb_fixed + 3154692432U, // VST2q16wb_register + 3021007184U, // VST2q32 + 0U, // VST2q32Pseudo + 0U, // VST2q32PseudoWB_fixed + 0U, // VST2q32PseudoWB_register + 3088099664U, // VST2q32wb_fixed + 3155216720U, // VST2q32wb_register + 3021531472U, // VST2q8 + 0U, // VST2q8Pseudo + 0U, // VST2q8PseudoWB_fixed + 0U, // VST2q8PseudoWB_register + 3088623952U, // VST2q8wb_fixed + 3155741008U, // VST2q8wb_register + 833751397U, // VST3LNd16 + 0U, // VST3LNd16Pseudo + 0U, // VST3LNd16Pseudo_UPD + 2914322789U, // VST3LNd16_UPD + 834275685U, // VST3LNd32 + 0U, // VST3LNd32Pseudo + 0U, // VST3LNd32Pseudo_UPD + 2914847077U, // VST3LNd32_UPD + 834799973U, // VST3LNd8 + 0U, // VST3LNd8Pseudo + 0U, // VST3LNd8Pseudo_UPD + 2915371365U, // VST3LNd8_UPD + 833751397U, // VST3LNq16 + 0U, // VST3LNq16Pseudo + 0U, // VST3LNq16Pseudo_UPD + 2914322789U, // VST3LNq16_UPD + 834275685U, // VST3LNq32 + 0U, // VST3LNq32Pseudo + 0U, // VST3LNq32Pseudo_UPD + 2914847077U, // VST3LNq32_UPD + 833669477U, // VST3d16 + 0U, // VST3d16Pseudo + 0U, // VST3d16Pseudo_UPD + 2914298213U, // VST3d16_UPD + 834193765U, // VST3d32 + 0U, // VST3d32Pseudo + 0U, // VST3d32Pseudo_UPD + 2914822501U, // VST3d32_UPD + 834718053U, // VST3d8 + 0U, // VST3d8Pseudo + 0U, // VST3d8Pseudo_UPD + 2915346789U, // VST3d8_UPD + 833669477U, // VST3q16 + 0U, // VST3q16Pseudo_UPD + 2914298213U, // VST3q16_UPD + 0U, // VST3q16oddPseudo + 0U, // VST3q16oddPseudo_UPD + 834193765U, // VST3q32 + 0U, // VST3q32Pseudo_UPD + 2914822501U, // VST3q32_UPD + 0U, // VST3q32oddPseudo + 0U, // VST3q32oddPseudo_UPD + 834718053U, // VST3q8 + 0U, // VST3q8Pseudo_UPD + 2915346789U, // VST3q8_UPD + 0U, // VST3q8oddPseudo + 0U, // VST3q8oddPseudo_UPD + 833923451U, // VST4LNd16 + 0U, // VST4LNd16Pseudo + 0U, // VST4LNd16Pseudo_UPD + 2914306427U, // VST4LNd16_UPD + 834447739U, // VST4LNd32 + 0U, // VST4LNd32Pseudo + 0U, // VST4LNd32Pseudo_UPD + 2914830715U, // VST4LNd32_UPD + 834972027U, // VST4LNd8 + 0U, // VST4LNd8Pseudo + 0U, // VST4LNd8Pseudo_UPD + 2915355003U, // VST4LNd8_UPD + 833923451U, // VST4LNq16 + 0U, // VST4LNq16Pseudo + 0U, // VST4LNq16Pseudo_UPD + 2914306427U, // VST4LNq16_UPD + 834447739U, // VST4LNq32 + 0U, // VST4LNq32Pseudo + 0U, // VST4LNq32Pseudo_UPD + 2914830715U, // VST4LNq32_UPD + 833751419U, // VST4d16 + 0U, // VST4d16Pseudo + 0U, // VST4d16Pseudo_UPD + 2914322811U, // VST4d16_UPD + 834275707U, // VST4d32 + 0U, // VST4d32Pseudo + 0U, // VST4d32Pseudo_UPD + 2914847099U, // VST4d32_UPD + 834799995U, // VST4d8 + 0U, // VST4d8Pseudo + 0U, // VST4d8Pseudo_UPD + 2915371387U, // VST4d8_UPD + 833751419U, // VST4q16 + 0U, // VST4q16Pseudo_UPD + 2914322811U, // VST4q16_UPD + 0U, // VST4q16oddPseudo + 0U, // VST4q16oddPseudo_UPD + 834275707U, // VST4q32 + 0U, // VST4q32Pseudo_UPD + 2914847099U, // VST4q32_UPD + 0U, // VST4q32oddPseudo + 0U, // VST4q32oddPseudo_UPD + 834799995U, // VST4q8 + 0U, // VST4q8Pseudo_UPD + 2915371387U, // VST4q8_UPD + 0U, // VST4q8oddPseudo + 0U, // VST4q8oddPseudo_UPD + 875064297U, // VSTMDDB_UPD + 2730773U, // VSTMDIA + 875064085U, // VSTMDIA_UPD + 0U, // VSTMQIA + 875064297U, // VSTMSDB_UPD + 2730773U, // VSTMSIA + 875064085U, // VSTMSIA_UPD + 2683391U, // VSTRD + 586239U, // VSTRH + 2683391U, // VSTRS + 2580050431U, // VSTR_FPCXTNS_off + 701035007U, // VSTR_FPCXTNS_post + 2647192063U, // VSTR_FPCXTNS_pre + 2580574719U, // VSTR_FPCXTS_off + 701559295U, // VSTR_FPCXTS_post + 2647716351U, // VSTR_FPCXTS_pre + 2581099007U, // VSTR_FPSCR_NZCVQC_off + 702083583U, // VSTR_FPSCR_NZCVQC_post + 2648240639U, // VSTR_FPSCR_NZCVQC_pre + 2581623295U, // VSTR_FPSCR_off + 702607871U, // VSTR_FPSCR_post + 2648764927U, // VSTR_FPSCR_pre + 2716398079U, // VSTR_P0_off + 1642639871U, // VSTR_P0_post + 2783490559U, // VSTR_P0_pre + 2582671871U, // VSTR_VPR_off + 703656447U, // VSTR_VPR_post + 2649813503U, // VSTR_VPR_pre + 1147727061U, // VSUBD + 7400661U, // VSUBH + 895545472U, // VSUBHNv2i32 + 14217344U, // VSUBHNv4i16 + 14741632U, // VSUBHNv8i8 + 11595604U, // VSUBLsv2i64 + 11071316U, // VSUBLsv4i32 + 12119892U, // VSUBLsv8i16 + 13168468U, // VSUBLuv2i64 + 12644180U, // VSUBLuv4i32 + 13692756U, // VSUBLuv8i16 + 7924949U, // VSUBS + 11596885U, // VSUBWsv2i64 + 11072597U, // VSUBWsv4i32 + 12121173U, // VSUBWsv8i16 + 13169749U, // VSUBWuv2i64 + 12645461U, // VSUBWuv4i32 + 13694037U, // VSUBWuv8i16 + 7924949U, // VSUBfd + 7924949U, // VSUBfq + 7400661U, // VSUBhd + 7400661U, // VSUBhq + 15264981U, // VSUBv16i8 + 895544533U, // VSUBv1i64 + 14216405U, // VSUBv2i32 + 895544533U, // VSUBv2i64 + 14740693U, // VSUBv4i16 + 14216405U, // VSUBv4i32 + 14740693U, // VSUBv8i16 + 15264981U, // VSUBv8i8 + 808543937U, // VSUDOTDI + 808543937U, // VSUDOTQI + 2666883U, // VSWPd + 2666883U, // VSWPq + 1634127U, // VTBL1 + 1634127U, // VTBL2 + 1634127U, // VTBL3 + 0U, // VTBL3Pseudo + 1634127U, // VTBL4 + 0U, // VTBL4Pseudo + 1619202U, // VTBX1 + 1619202U, // VTBX2 + 1619202U, // VTBX3 + 0U, // VTBX3Pseudo + 1619202U, // VTBX4 + 0U, // VTBX4Pseudo + 37811112U, // VTOSHD + 1160311720U, // VTOSHH + 38335400U, // VTOSHS + 1101558276U, // VTOSIRD + 1112568324U, // VTOSIRH + 1093693956U, // VTOSIRS + 1101558696U, // VTOSIZD + 1112568744U, // VTOSIZH + 1093694376U, // VTOSIZS + 1168700328U, // VTOSLD + 1179710376U, // VTOSLH + 1160836008U, // VTOSLS + 39383976U, // VTOUHD + 1161360296U, // VTOUHH + 39908264U, // VTOUHS + 1114141188U, // VTOUIRD + 1114665476U, // VTOUIRH + 1094742532U, // VTOUIRS + 1114141608U, // VTOUIZD + 1114665896U, // VTOUIZH + 1094742952U, // VTOUIZS + 1181283240U, // VTOULD + 1181807528U, // VTOULH + 1161884584U, // VTOULS + 569542U, // VTRNd16 + 1093830U, // VTRNd32 + 1618118U, // VTRNd8 + 569542U, // VTRNq16 + 1093830U, // VTRNq32 + 1618118U, // VTRNq8 + 1635191U, // VTSTv16i8 + 1110903U, // VTSTv2i32 + 586615U, // VTSTv4i16 + 1110903U, // VTSTv4i32 + 586615U, // VTSTv8i16 + 1635191U, // VTSTv8i8 + 808543948U, // VUDOTD + 808543948U, // VUDOTDI + 808543948U, // VUDOTQ + 808543948U, // VUDOTQI + 41481128U, // VUHTOD + 1158214568U, // VUHTOH + 42005416U, // VUHTOS + 1116238760U, // VUITOD + 1116763048U, // VUITOH + 1092645800U, // VUITOS + 1183380392U, // VULTOD + 1183904680U, // VULTOH + 1159787432U, // VULTOS + 808543926U, // VUMMLA + 808543905U, // VUSDOTD + 808543905U, // VUSDOTDI + 808543905U, // VUSDOTQ + 808543905U, // VUSDOTQI + 808543882U, // VUSMMLA + 569736U, // VUZPd16 + 1618312U, // VUZPd8 + 569736U, // VUZPq16 + 1094024U, // VUZPq32 + 1618312U, // VUZPq8 + 569612U, // VZIPd16 + 1618188U, // VZIPd8 + 569612U, // VZIPq16 + 1093900U, // VZIPq32 + 1618188U, // VZIPq8 + 2730724U, // sysLDMDA + 875064036U, // sysLDMDA_UPD + 2730979U, // sysLDMDB + 875064291U, // sysLDMDB_UPD + 2732107U, // sysLDMIA + 875065419U, // sysLDMIA_UPD + 2730998U, // sysLDMIB + 875064310U, // sysLDMIB_UPD + 2730730U, // sysSTMDA + 875064042U, // sysSTMDA_UPD + 2730986U, // sysSTMDB + 875064298U, // sysSTMDB_UPD + 2732142U, // sysSTMIA + 875065454U, // sysSTMIA_UPD + 2731004U, // sysSTMIB + 875064316U, // sysSTMIB_UPD + 2632970U, // t2ADCri + 43527434U, // t2ADCrr + 43584778U, // t2ADCrs + 43527502U, // t2ADDri + 2683996U, // t2ADDri12 + 43527502U, // t2ADDrr + 43584846U, // t2ADDrs + 43527502U, // t2ADDspImm + 2683996U, // t2ADDspImm12 + 43544993U, // t2ADR + 2633103U, // t2ANDri + 43527567U, // t2ANDrr + 43584911U, // t2ANDrs + 43528674U, // t2ASRri + 43528674U, // t2ASRrr + 4413U, // t2AUT + 808046091U, // t2AUTG + 983149492U, // t2B + 2682130U, // t2BFC + 2666240U, // t2BFI + 942174077U, // t2BFLi + 942175649U, // t2BFLr + 942173676U, // t2BFi + 3962668948U, // t2BFic + 942175570U, // t2BFr + 2632983U, // t2BICri + 43527447U, // t2BICrr + 43584791U, // t2BICrs + 1917U, // t2BTI + 808047516U, // t2BXAUT + 2731794U, // t2BXJ + 983149492U, // t2Bcc + 1277825288U, // t2CDP + 1277823290U, // t2CDP2 + 4314437U, // t2CLREX + 2821312608U, // t2CLRM + 2651636U, // t2CLZ + 43544737U, // t2CMNri + 43544737U, // t2CMNzrr + 43577505U, // t2CMNzrs + 43544850U, // t2CMPri + 43544850U, // t2CMPrr + 43577618U, // t2CMPrs + 4278196U, // t2CPS1p + 1452986965U, // t2CPS2p + 1412092501U, // t2CPS3p + 875644665U, // t2CRC32B + 875644673U, // t2CRC32CB + 875644783U, // t2CRC32CH + 875644903U, // t2CRC32CW + 875644775U, // t2CRC32H + 875644895U, // t2CRC32W + 875644822U, // t2CSEL + 875644716U, // t2CSINC + 875644874U, // t2CSINV + 875644768U, // t2CSNEG + 2731508U, // t2DBG + 4311305U, // t2DCPS1 + 4311370U, // t2DCPS2 + 4311391U, // t2DCPS3 + 875644842U, // t2DLS + 4029262885U, // t2DMB + 4029262981U, // t2DSB + 2634192U, // t2EORri + 43528656U, // t2EORrr + 43586000U, // t2EORrs + 43627272U, // t2HINT + 4278225U, // t2HVC + 4096371849U, // t2ISB + 69751512U, // t2IT + 0U, // t2Int_eh_sjlj_setjmp + 0U, // t2Int_eh_sjlj_setjmp_nofp + 2648800U, // t2LDA + 2649009U, // t2LDAB + 2651443U, // t2LDAEX + 2649320U, // t2LDAEXB + 2682283U, // t2LDAEXD + 2649816U, // t2LDAEXH + 2649616U, // t2LDAH + 1277734678U, // t2LDC2L_OFFSET + 1277734678U, // t2LDC2L_OPTION + 1277734678U, // t2LDC2L_POST + 1009307414U, // t2LDC2L_PRE + 1277733152U, // t2LDC2_OFFSET + 1277733152U, // t2LDC2_OPTION + 1277733152U, // t2LDC2_POST + 1009305888U, // t2LDC2_PRE + 1277734746U, // t2LDCL_OFFSET + 1277734746U, // t2LDCL_OPTION + 1277734746U, // t2LDCL_POST + 1009307482U, // t2LDCL_PRE + 1277734158U, // t2LDC_OFFSET + 1277734158U, // t2LDC_OPTION + 1277734158U, // t2LDC_POST + 1009306894U, // t2LDC_PRE + 2730979U, // t2LDMDB + 875064291U, // t2LDMDB_UPD + 43626571U, // t2LDMIA + 915959883U, // t2LDMIA_UPD + 2683552U, // t2LDRBT + 2665594U, // t2LDRB_POST + 2665594U, // t2LDRB_PRE + 43576442U, // t2LDRBi12 + 2681978U, // t2LDRBi8 + 43543674U, // t2LDRBpci + 43560058U, // t2LDRBs + 2674068U, // t2LDRD_POST + 2674068U, // t2LDRD_PRE + 2665876U, // t2LDRDi8 + 2684223U, // t2LDREX + 2649334U, // t2LDREXB + 2682297U, // t2LDREXD + 2649830U, // t2LDREXH + 2683587U, // t2LDRHT + 2666112U, // t2LDRH_POST + 2666112U, // t2LDRH_PRE + 43576960U, // t2LDRHi12 + 2682496U, // t2LDRHi8 + 43544192U, // t2LDRHpci + 43560576U, // t2LDRHs + 2683564U, // t2LDRSBT + 2665613U, // t2LDRSB_POST + 2665613U, // t2LDRSB_PRE + 43576461U, // t2LDRSBi12 + 2681997U, // t2LDRSBi8 + 43543693U, // t2LDRSBpci + 43560077U, // t2LDRSBs + 2683599U, // t2LDRSHT + 2666151U, // t2LDRSH_POST + 2666151U, // t2LDRSH_PRE + 43576999U, // t2LDRSHi12 + 2682535U, // t2LDRSHi8 + 43544231U, // t2LDRSHpci + 43560615U, // t2LDRSHs + 2683746U, // t2LDRT + 2666918U, // t2LDR_POST + 2666918U, // t2LDR_PRE + 43577766U, // t2LDRi12 + 2683302U, // t2LDRi8 + 43544998U, // t2LDRpci + 43561382U, // t2LDRs + 4294487U, // t2LE + 1882285911U, // t2LEUpdate + 43528222U, // t2LSLri + 43528222U, // t2LSLrr + 43528681U, // t2LSRri + 43528681U, // t2LSRrr + 1277825437U, // t2MCR + 1277823295U, // t2MCR2 + 1277743576U, // t2MCRR + 1277741380U, // t2MCRR2 + 2665252U, // t2MLA + 2667053U, // t2MLS + 2683821U, // t2MOVTi16 + 43553867U, // t2MOVi + 2651250U, // t2MOVi16 + 43553867U, // t2MOVr + 43545182U, // t2MOVsra_flag + 43545187U, // t2MOVsrl_flag + 1009388837U, // t2MRC + 1009387813U, // t2MRC2 + 1680395561U, // t2MRRC + 1680394538U, // t2MRRC2 + 2732634U, // t2MRS_AR + 2650714U, // t2MRS_M + 2650714U, // t2MRSbanked + 2732634U, // t2MRSsys_AR + 1747481070U, // t2MSR_AR + 1747481070U, // t2MSR_M + 1814589934U, // t2MSRbanked + 2682926U, // t2MUL + 2658546U, // t2MVNi + 43553010U, // t2MVNr + 43528434U, // t2MVNs + 2633922U, // t2ORNri + 2633922U, // t2ORNrr + 2691266U, // t2ORNrs + 2634206U, // t2ORRri + 43528670U, // t2ORRrr + 43586014U, // t2ORRrs + 4378U, // t2PAC + 4394U, // t2PACBTI + 2731512U, // t2PACG + 2667147U, // t2PKHBT + 2665630U, // t2PKHTB + 4163400801U, // t2PLDWi12 + 4230509665U, // t2PLDWi8 + 2684001U, // t2PLDWs + 4163399043U, // t2PLDi12 + 4230507907U, // t2PLDi8 + 69840259U, // t2PLDpci + 2682243U, // t2PLDs + 4163399428U, // t2PLIi12 + 4230508292U, // t2PLIi8 + 69840644U, // t2PLIpci + 2682628U, // t2PLIs + 2682226U, // t2QADD + 2681301U, // t2QADD16 + 2681404U, // t2QADD8 + 2684343U, // t2QASX + 2682200U, // t2QDADD + 2682051U, // t2QDSUB + 2684089U, // t2QSAX + 2682064U, // t2QSUB + 2681263U, // t2QSUB16 + 2681365U, // t2QSUB8 + 2650838U, // t2RBIT + 43545626U, // t2REV + 43543033U, // t2REV16 + 43544242U, // t2REVSH + 2730972U, // t2RFEDB + 2730972U, // t2RFEDBW + 2730760U, // t2RFEIA + 2730760U, // t2RFEIAW + 43528660U, // t2RORri + 43528660U, // t2RORrr + 2659750U, // t2RRX + 43527311U, // t2RSBri + 2632847U, // t2RSBrr + 2690191U, // t2RSBrs + 2681308U, // t2SADD16 + 2681410U, // t2SADD8 + 2684348U, // t2SASX + 3206U, // t2SB + 2632965U, // t2SBCri + 43527429U, // t2SBCrr + 43584773U, // t2SBCrs + 2667857U, // t2SBFX + 2683934U, // t2SDIV + 2682745U, // t2SEL + 4278172U, // t2SETPAN + 4312584U, // t2SG + 2681284U, // t2SHADD16 + 2681389U, // t2SHADD8 + 2684330U, // t2SHASX + 2684076U, // t2SHSAX + 2681246U, // t2SHSUB16 + 2681350U, // t2SHSUB8 + 2731297U, // t2SMC + 2665410U, // t2SMLABB + 2667140U, // t2SMLABT + 2665786U, // t2SMLAD + 2667783U, // t2SMLADX + 2756413U, // t2SMLAL + 2755529U, // t2SMLALBB + 2757265U, // t2SMLALBT + 2755964U, // t2SMLALD + 2757909U, // t2SMLALDX + 2755748U, // t2SMLALTB + 2757507U, // t2SMLALTT + 2665623U, // t2SMLATB + 2667388U, // t2SMLATT + 2665690U, // t2SMLAWB + 2667442U, // t2SMLAWT + 2665887U, // t2SMLSD + 2667813U, // t2SMLSDX + 2755975U, // t2SMLSLD + 2757917U, // t2SMLSLDX + 2665256U, // t2SMMLA + 2666902U, // t2SMMLAR + 2667051U, // t2SMMLS + 2666982U, // t2SMMLSR + 2682930U, // t2SMMUL + 2683336U, // t2SMMULR + 2682176U, // t2SMUAD + 2684174U, // t2SMUADX + 2681809U, // t2SMULBB + 2683545U, // t2SMULBT + 2666467U, // t2SMULL + 2682028U, // t2SMULTB + 2683787U, // t2SMULTT + 2682081U, // t2SMULWB + 2683833U, // t2SMULWT + 2682277U, // t2SMUSD + 2684204U, // t2SMUSDX + 44149744U, // t2SRSDB + 44674032U, // t2SRSDB_UPD + 44149532U, // t2SRSIA + 44673820U, // t2SRSIA_UPD + 2667125U, // t2SSAT + 2681322U, // t2SSAT16 + 2684094U, // t2SSAX + 2681270U, // t2SSUB16 + 2681371U, // t2SSUB8 + 1277734684U, // t2STC2L_OFFSET + 1277734684U, // t2STC2L_OPTION + 1277734684U, // t2STC2L_POST + 1009307420U, // t2STC2L_PRE + 1277733168U, // t2STC2_OFFSET + 1277733168U, // t2STC2_OPTION + 1277733168U, // t2STC2_POST + 1009305904U, // t2STC2_PRE + 1277734751U, // t2STCL_OFFSET + 1277734751U, // t2STCL_OPTION + 1277734751U, // t2STCL_POST + 1009307487U, // t2STCL_PRE + 1277734194U, // t2STC_OFFSET + 1277734194U, // t2STC_OPTION + 1277734194U, // t2STC_POST + 1009306930U, // t2STC_PRE + 2650152U, // t2STL + 2649113U, // t2STLB + 2684217U, // t2STLEX + 2682095U, // t2STLEXB + 2665906U, // t2STLEXD + 2682591U, // t2STLEXH + 2649692U, // t2STLH + 2730986U, // t2STMDB + 875064298U, // t2STMDB_UPD + 43626606U, // t2STMIA + 915959918U, // t2STMIA_UPD + 2683558U, // t2STRBT + 875080832U, // t2STRB_POST + 875080832U, // t2STRB_PRE + 43576448U, // t2STRBi12 + 2681984U, // t2STRBi8 + 43560064U, // t2STRBs + 875089306U, // t2STRD_POST + 875089306U, // t2STRD_PRE + 2665882U, // t2STRDi8 + 2667851U, // t2STREX + 2682109U, // t2STREXB + 2665920U, // t2STREXD + 2682605U, // t2STREXH + 2683593U, // t2STRHT + 875081350U, // t2STRH_POST + 875081350U, // t2STRH_PRE + 43576966U, // t2STRHi12 + 2682502U, // t2STRHi8 + 43560582U, // t2STRHs + 2683757U, // t2STRT + 875082240U, // t2STR_POST + 875082240U, // t2STR_PRE + 43577856U, // t2STRi12 + 2683392U, // t2STRi8 + 43561472U, // t2STRs + 45199905U, // t2SUBS_PC_LR + 43527365U, // t2SUBri + 2683990U, // t2SUBri12 + 43527365U, // t2SUBrr + 43584709U, // t2SUBrs + 43527365U, // t2SUBspImm + 2683990U, // t2SUBspImm12 + 2665398U, // t2SXTAB + 2664832U, // t2SXTAB16 + 2666022U, // t2SXTAH + 43576505U, // t2SXTB + 2681232U, // t2SXTB16 + 43577016U, // t2SXTH + 136866776U, // t2TBB + 203976242U, // t2TBH + 43544978U, // t2TEQri + 43544978U, // t2TEQrr + 43577746U, // t2TEQrs + 271166611U, // t2TSB + 43545464U, // t2TSTri + 43545464U, // t2TSTrr + 43578232U, // t2TSTrs + 2651008U, // t2TT + 2648940U, // t2TTA + 2650751U, // t2TTAT + 2651026U, // t2TTT + 2681315U, // t2UADD16 + 2681416U, // t2UADD8 + 2684353U, // t2UASX + 2667862U, // t2UBFX + 4278232U, // t2UDF + 2683939U, // t2UDIV + 2681292U, // t2UHADD16 + 2681396U, // t2UHADD8 + 2684336U, // t2UHASX + 2684082U, // t2UHSAX + 2681254U, // t2UHSUB16 + 2681357U, // t2UHSUB8 + 2756386U, // t2UMAAL + 2756419U, // t2UMLAL + 2666473U, // t2UMULL + 2681300U, // t2UQADD16 + 2681403U, // t2UQADD8 + 2684342U, // t2UQASX + 2684088U, // t2UQSAX + 2681262U, // t2UQSUB16 + 2681364U, // t2UQSUB8 + 2681383U, // t2USAD8 + 2664959U, // t2USADA8 + 2667130U, // t2USAT + 2681329U, // t2USAT16 + 2684099U, // t2USAX + 2681277U, // t2USUB16 + 2681377U, // t2USUB8 + 2665404U, // t2UXTAB + 2664840U, // t2UXTAB16 + 2666028U, // t2UXTAH + 43576510U, // t2UXTB + 2681239U, // t2UXTB16 + 43577021U, // t2UXTH + 875644847U, // t2WLS + 1253920010U, // tADC + 2682190U, // tADDhirr + 851266894U, // tADDi3 + 1253920078U, // tADDi8 + 2682190U, // tADDrSP + 2682190U, // tADDrSPi + 851266894U, // tADDrr + 2682190U, // tADDspi + 2682190U, // tADDspr + 2650529U, // tADR + 1253920143U, // tAND + 851268066U, // tASRri + 1253921250U, // tASRrr + 942255028U, // tB + 1253920023U, // tBIC + 4278212U, // tBKPT + 1881788241U, // tBL + 808047180U, // tBLXNSr + 1881789853U, // tBLXi + 808048029U, // tBLXr + 2733303U, // tBX + 2732615U, // tBXNS + 942255028U, // tBcc + 3962652676U, // tCBNZ + 3962652671U, // tCBZ + 2650273U, // tCMNz + 2650386U, // tCMPhir + 2650386U, // tCMPi8 + 2650386U, // tCMPr + 1409471061U, // tCPS + 1253921232U, // tEOR + 2732808U, // tHINT + 4278207U, // tHLT + 0U, // tInt_WIN_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_setjmp + 2732107U, // tLDMIA + 2681978U, // tLDRBi + 2681978U, // tLDRBr + 2682496U, // tLDRHi + 2682496U, // tLDRHr + 2681997U, // tLDRSB + 2682535U, // tLDRSH + 2683302U, // tLDRi + 2650534U, // tLDRpci + 2683302U, // tLDRr + 2683302U, // tLDRspi + 851267614U, // tLSLri + 1253920798U, // tLSLrr + 851268073U, // tLSRri + 1253921257U, // tLSRrr + 875644857U, // tMOVSr + 1120228427U, // tMOVi8 + 2651211U, // tMOVr + 851267630U, // tMUL + 1120227570U, // tMVN + 1253921246U, // tORR + 0U, // tPICADD + 2821312790U, // tPOP + 2821312173U, // tPUSH + 2651162U, // tREV + 2648569U, // tREV16 + 2649778U, // tREVSH + 1253921236U, // tROR + 2126859407U, // tRSB + 1253920005U, // tSBC + 280399U, // tSETEND + 875065454U, // tSTMIA_UPD + 2681984U, // tSTRBi + 2681984U, // tSTRBr + 2682502U, // tSTRHi + 2682502U, // tSTRHr + 2683392U, // tSTRi + 2683392U, // tSTRr + 2683392U, // tSTRspi + 851266757U, // tSUBi3 + 1253919941U, // tSUBi8 + 851266757U, // tSUBrr + 2682053U, // tSUBspi + 2731318U, // tSVC + 2649273U, // tSXTB + 2649784U, // tSXTH + 4355U, // tTRAP + 2651000U, // tTST + 4278107U, // tUDF + 2649278U, // tUXTB + 2649789U, // tUXTH + 2298U, // t__brkdiv0 + }; + + static const uint32_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // MEMBARRIER + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ASSERT_ALIGN + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_FPTRUNC_ROUND + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_ATOMICRMW_FMAX + 0U, // G_ATOMICRMW_FMIN + 0U, // G_ATOMICRMW_UINC_WRAP + 0U, // G_ATOMICRMW_UDEC_WRAP + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INVOKE_REGION_START + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_IS_FPCLASS + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ABS + 0U, // ADDSri + 0U, // ADDSrr + 0U, // ADDSrsi + 0U, // ADDSrsr + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ASRi + 0U, // ASRr + 0U, // B + 0U, // BCCZi64 + 0U, // BCCi64 + 0U, // BLX_noip + 0U, // BLX_pred_noip + 0U, // BL_PUSHLR + 0U, // BMOVPCB_CALL + 0U, // BMOVPCRX_CALL + 0U, // BR_JTadd + 0U, // BR_JTm_i12 + 0U, // BR_JTm_rs + 0U, // BR_JTr + 0U, // BX_CALL + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_STRUCT_BYVAL_I32 + 0U, // ITasm + 0U, // Int_eh_sjlj_dispatchsetup + 0U, // Int_eh_sjlj_longjmp + 0U, // Int_eh_sjlj_setjmp + 0U, // Int_eh_sjlj_setjmp_nofp + 0U, // Int_eh_sjlj_setup_dispatch + 0U, // JUMPTABLE_ADDRS + 0U, // JUMPTABLE_INSTS + 0U, // JUMPTABLE_TBB + 0U, // JUMPTABLE_TBH + 0U, // LDMIA_RET + 128U, // LDRBT_POST + 16384U, // LDRConstPool + 128U, // LDRHTii + 0U, // LDRLIT_ga_abs + 0U, // LDRLIT_ga_pcrel + 0U, // LDRLIT_ga_pcrel_ldr + 128U, // LDRSBTii + 128U, // LDRSHTii + 128U, // LDRT_POST + 0U, // LEApcrel + 0U, // LEApcrelJT + 0U, // LOADDUAL + 0U, // LSLi + 0U, // LSLr + 0U, // LSRi + 0U, // LSRr + 0U, // MEMCPY + 0U, // MLAv5 + 0U, // MOVCCi + 0U, // MOVCCi16 + 0U, // MOVCCi32imm + 0U, // MOVCCr + 0U, // MOVCCsi + 0U, // MOVCCsr + 0U, // MOVPCRX + 0U, // MOVTi16_ga_pcrel + 0U, // MOV_ga_pcrel + 0U, // MOV_ga_pcrel_ldr + 0U, // MOVi16_ga_pcrel + 0U, // MOVi32imm + 0U, // MOVsra_flag + 0U, // MOVsrl_flag + 0U, // MQPRCopy + 0U, // MQQPRLoad + 0U, // MQQPRStore + 0U, // MQQQQPRLoad + 0U, // MQQQQPRStore + 0U, // MULv5 + 0U, // MVE_MEMCPYLOOPINST + 0U, // MVE_MEMSETLOOPINST + 0U, // MVNCCi + 0U, // PICADD + 0U, // PICLDR + 0U, // PICLDRB + 0U, // PICLDRH + 0U, // PICLDRSB + 0U, // PICLDRSH + 0U, // PICSTR + 0U, // PICSTRB + 0U, // PICSTRH + 0U, // RORi + 0U, // RORr + 0U, // RRX + 16384U, // RRXi + 0U, // RSBSri + 0U, // RSBSrsi + 0U, // RSBSrsr + 0U, // SEH_EpilogEnd + 0U, // SEH_EpilogStart + 0U, // SEH_Nop + 0U, // SEH_Nop_Ret + 0U, // SEH_PrologEnd + 0U, // SEH_SaveFRegs + 0U, // SEH_SaveLR + 0U, // SEH_SaveRegs + 0U, // SEH_SaveRegs_Ret + 0U, // SEH_SaveSP + 0U, // SEH_StackAlloc + 0U, // SMLALv5 + 0U, // SMULLv5 + 0U, // SPACE + 0U, // STOREDUAL + 128U, // STRBT_POST + 0U, // STRBi_preidx + 0U, // STRBr_preidx + 0U, // STRH_preidx + 128U, // STRT_POST + 0U, // STRi_preidx + 0U, // STRr_preidx + 0U, // SUBS_PC_LR + 0U, // SUBSri + 0U, // SUBSrr + 0U, // SUBSrsi + 0U, // SUBSrsr + 0U, // SpeculationBarrierISBDSBEndBB + 0U, // SpeculationBarrierSBEndBB + 0U, // TAILJMPd + 0U, // TAILJMPr + 0U, // TAILJMPr4 + 0U, // TCRETURNdi + 0U, // TCRETURNri + 0U, // TPsoft + 0U, // UMLALv5 + 0U, // UMULLv5 + 16640U, // VLD1LNdAsm_16 + 16640U, // VLD1LNdAsm_32 + 16640U, // VLD1LNdAsm_8 + 33024U, // VLD1LNdWB_fixed_Asm_16 + 33024U, // VLD1LNdWB_fixed_Asm_32 + 33024U, // VLD1LNdWB_fixed_Asm_8 + 524544U, // VLD1LNdWB_register_Asm_16 + 524544U, // VLD1LNdWB_register_Asm_32 + 524544U, // VLD1LNdWB_register_Asm_8 + 16640U, // VLD2LNdAsm_16 + 16640U, // VLD2LNdAsm_32 + 16640U, // VLD2LNdAsm_8 + 33024U, // VLD2LNdWB_fixed_Asm_16 + 33024U, // VLD2LNdWB_fixed_Asm_32 + 33024U, // VLD2LNdWB_fixed_Asm_8 + 524544U, // VLD2LNdWB_register_Asm_16 + 524544U, // VLD2LNdWB_register_Asm_32 + 524544U, // VLD2LNdWB_register_Asm_8 + 16640U, // VLD2LNqAsm_16 + 16640U, // VLD2LNqAsm_32 + 33024U, // VLD2LNqWB_fixed_Asm_16 + 33024U, // VLD2LNqWB_fixed_Asm_32 + 524544U, // VLD2LNqWB_register_Asm_16 + 524544U, // VLD2LNqWB_register_Asm_32 + 2U, // VLD3DUPdAsm_16 + 2U, // VLD3DUPdAsm_32 + 2U, // VLD3DUPdAsm_8 + 4U, // VLD3DUPdWB_fixed_Asm_16 + 4U, // VLD3DUPdWB_fixed_Asm_32 + 4U, // VLD3DUPdWB_fixed_Asm_8 + 16768U, // VLD3DUPdWB_register_Asm_16 + 16768U, // VLD3DUPdWB_register_Asm_32 + 16768U, // VLD3DUPdWB_register_Asm_8 + 2U, // VLD3DUPqAsm_16 + 2U, // VLD3DUPqAsm_32 + 2U, // VLD3DUPqAsm_8 + 4U, // VLD3DUPqWB_fixed_Asm_16 + 4U, // VLD3DUPqWB_fixed_Asm_32 + 4U, // VLD3DUPqWB_fixed_Asm_8 + 16768U, // VLD3DUPqWB_register_Asm_16 + 16768U, // VLD3DUPqWB_register_Asm_32 + 16768U, // VLD3DUPqWB_register_Asm_8 + 16640U, // VLD3LNdAsm_16 + 16640U, // VLD3LNdAsm_32 + 16640U, // VLD3LNdAsm_8 + 33024U, // VLD3LNdWB_fixed_Asm_16 + 33024U, // VLD3LNdWB_fixed_Asm_32 + 33024U, // VLD3LNdWB_fixed_Asm_8 + 524544U, // VLD3LNdWB_register_Asm_16 + 524544U, // VLD3LNdWB_register_Asm_32 + 524544U, // VLD3LNdWB_register_Asm_8 + 16640U, // VLD3LNqAsm_16 + 16640U, // VLD3LNqAsm_32 + 33024U, // VLD3LNqWB_fixed_Asm_16 + 33024U, // VLD3LNqWB_fixed_Asm_32 + 524544U, // VLD3LNqWB_register_Asm_16 + 524544U, // VLD3LNqWB_register_Asm_32 + 518U, // VLD3dAsm_16 + 518U, // VLD3dAsm_32 + 518U, // VLD3dAsm_8 + 646U, // VLD3dWB_fixed_Asm_16 + 646U, // VLD3dWB_fixed_Asm_32 + 646U, // VLD3dWB_fixed_Asm_8 + 49926U, // VLD3dWB_register_Asm_16 + 49926U, // VLD3dWB_register_Asm_32 + 49926U, // VLD3dWB_register_Asm_8 + 2U, // VLD3qAsm_16 + 2U, // VLD3qAsm_32 + 2U, // VLD3qAsm_8 + 4U, // VLD3qWB_fixed_Asm_16 + 4U, // VLD3qWB_fixed_Asm_32 + 4U, // VLD3qWB_fixed_Asm_8 + 16768U, // VLD3qWB_register_Asm_16 + 16768U, // VLD3qWB_register_Asm_32 + 16768U, // VLD3qWB_register_Asm_8 + 2U, // VLD4DUPdAsm_16 + 2U, // VLD4DUPdAsm_32 + 2U, // VLD4DUPdAsm_8 + 4U, // VLD4DUPdWB_fixed_Asm_16 + 4U, // VLD4DUPdWB_fixed_Asm_32 + 4U, // VLD4DUPdWB_fixed_Asm_8 + 16768U, // VLD4DUPdWB_register_Asm_16 + 16768U, // VLD4DUPdWB_register_Asm_32 + 16768U, // VLD4DUPdWB_register_Asm_8 + 2U, // VLD4DUPqAsm_16 + 2U, // VLD4DUPqAsm_32 + 2U, // VLD4DUPqAsm_8 + 4U, // VLD4DUPqWB_fixed_Asm_16 + 4U, // VLD4DUPqWB_fixed_Asm_32 + 4U, // VLD4DUPqWB_fixed_Asm_8 + 16768U, // VLD4DUPqWB_register_Asm_16 + 16768U, // VLD4DUPqWB_register_Asm_32 + 16768U, // VLD4DUPqWB_register_Asm_8 + 16640U, // VLD4LNdAsm_16 + 16640U, // VLD4LNdAsm_32 + 16640U, // VLD4LNdAsm_8 + 33024U, // VLD4LNdWB_fixed_Asm_16 + 33024U, // VLD4LNdWB_fixed_Asm_32 + 33024U, // VLD4LNdWB_fixed_Asm_8 + 524544U, // VLD4LNdWB_register_Asm_16 + 524544U, // VLD4LNdWB_register_Asm_32 + 524544U, // VLD4LNdWB_register_Asm_8 + 16640U, // VLD4LNqAsm_16 + 16640U, // VLD4LNqAsm_32 + 33024U, // VLD4LNqWB_fixed_Asm_16 + 33024U, // VLD4LNqWB_fixed_Asm_32 + 524544U, // VLD4LNqWB_register_Asm_16 + 524544U, // VLD4LNqWB_register_Asm_32 + 518U, // VLD4dAsm_16 + 518U, // VLD4dAsm_32 + 518U, // VLD4dAsm_8 + 646U, // VLD4dWB_fixed_Asm_16 + 646U, // VLD4dWB_fixed_Asm_32 + 646U, // VLD4dWB_fixed_Asm_8 + 49926U, // VLD4dWB_register_Asm_16 + 49926U, // VLD4dWB_register_Asm_32 + 49926U, // VLD4dWB_register_Asm_8 + 2U, // VLD4qAsm_16 + 2U, // VLD4qAsm_32 + 2U, // VLD4qAsm_8 + 4U, // VLD4qWB_fixed_Asm_16 + 4U, // VLD4qWB_fixed_Asm_32 + 4U, // VLD4qWB_fixed_Asm_8 + 16768U, // VLD4qWB_register_Asm_16 + 16768U, // VLD4qWB_register_Asm_32 + 16768U, // VLD4qWB_register_Asm_8 + 0U, // VMOVD0 + 0U, // VMOVDcc + 0U, // VMOVHcc + 0U, // VMOVQ0 + 0U, // VMOVScc + 16640U, // VST1LNdAsm_16 + 16640U, // VST1LNdAsm_32 + 16640U, // VST1LNdAsm_8 + 33024U, // VST1LNdWB_fixed_Asm_16 + 33024U, // VST1LNdWB_fixed_Asm_32 + 33024U, // VST1LNdWB_fixed_Asm_8 + 524544U, // VST1LNdWB_register_Asm_16 + 524544U, // VST1LNdWB_register_Asm_32 + 524544U, // VST1LNdWB_register_Asm_8 + 16640U, // VST2LNdAsm_16 + 16640U, // VST2LNdAsm_32 + 16640U, // VST2LNdAsm_8 + 33024U, // VST2LNdWB_fixed_Asm_16 + 33024U, // VST2LNdWB_fixed_Asm_32 + 33024U, // VST2LNdWB_fixed_Asm_8 + 524544U, // VST2LNdWB_register_Asm_16 + 524544U, // VST2LNdWB_register_Asm_32 + 524544U, // VST2LNdWB_register_Asm_8 + 16640U, // VST2LNqAsm_16 + 16640U, // VST2LNqAsm_32 + 33024U, // VST2LNqWB_fixed_Asm_16 + 33024U, // VST2LNqWB_fixed_Asm_32 + 524544U, // VST2LNqWB_register_Asm_16 + 524544U, // VST2LNqWB_register_Asm_32 + 16640U, // VST3LNdAsm_16 + 16640U, // VST3LNdAsm_32 + 16640U, // VST3LNdAsm_8 + 33024U, // VST3LNdWB_fixed_Asm_16 + 33024U, // VST3LNdWB_fixed_Asm_32 + 33024U, // VST3LNdWB_fixed_Asm_8 + 524544U, // VST3LNdWB_register_Asm_16 + 524544U, // VST3LNdWB_register_Asm_32 + 524544U, // VST3LNdWB_register_Asm_8 + 16640U, // VST3LNqAsm_16 + 16640U, // VST3LNqAsm_32 + 33024U, // VST3LNqWB_fixed_Asm_16 + 33024U, // VST3LNqWB_fixed_Asm_32 + 524544U, // VST3LNqWB_register_Asm_16 + 524544U, // VST3LNqWB_register_Asm_32 + 518U, // VST3dAsm_16 + 518U, // VST3dAsm_32 + 518U, // VST3dAsm_8 + 646U, // VST3dWB_fixed_Asm_16 + 646U, // VST3dWB_fixed_Asm_32 + 646U, // VST3dWB_fixed_Asm_8 + 49926U, // VST3dWB_register_Asm_16 + 49926U, // VST3dWB_register_Asm_32 + 49926U, // VST3dWB_register_Asm_8 + 2U, // VST3qAsm_16 + 2U, // VST3qAsm_32 + 2U, // VST3qAsm_8 + 4U, // VST3qWB_fixed_Asm_16 + 4U, // VST3qWB_fixed_Asm_32 + 4U, // VST3qWB_fixed_Asm_8 + 16768U, // VST3qWB_register_Asm_16 + 16768U, // VST3qWB_register_Asm_32 + 16768U, // VST3qWB_register_Asm_8 + 16640U, // VST4LNdAsm_16 + 16640U, // VST4LNdAsm_32 + 16640U, // VST4LNdAsm_8 + 33024U, // VST4LNdWB_fixed_Asm_16 + 33024U, // VST4LNdWB_fixed_Asm_32 + 33024U, // VST4LNdWB_fixed_Asm_8 + 524544U, // VST4LNdWB_register_Asm_16 + 524544U, // VST4LNdWB_register_Asm_32 + 524544U, // VST4LNdWB_register_Asm_8 + 16640U, // VST4LNqAsm_16 + 16640U, // VST4LNqAsm_32 + 33024U, // VST4LNqWB_fixed_Asm_16 + 33024U, // VST4LNqWB_fixed_Asm_32 + 524544U, // VST4LNqWB_register_Asm_16 + 524544U, // VST4LNqWB_register_Asm_32 + 518U, // VST4dAsm_16 + 518U, // VST4dAsm_32 + 518U, // VST4dAsm_8 + 646U, // VST4dWB_fixed_Asm_16 + 646U, // VST4dWB_fixed_Asm_32 + 646U, // VST4dWB_fixed_Asm_8 + 49926U, // VST4dWB_register_Asm_16 + 49926U, // VST4dWB_register_Asm_32 + 49926U, // VST4dWB_register_Asm_8 + 2U, // VST4qAsm_16 + 2U, // VST4qAsm_32 + 2U, // VST4qAsm_8 + 4U, // VST4qWB_fixed_Asm_16 + 4U, // VST4qWB_fixed_Asm_32 + 4U, // VST4qWB_fixed_Asm_8 + 16768U, // VST4qWB_register_Asm_16 + 16768U, // VST4qWB_register_Asm_32 + 16768U, // VST4qWB_register_Asm_8 + 0U, // WIN__CHKSTK + 0U, // WIN__DBZCHK + 0U, // t2ABS + 0U, // t2ADDSri + 0U, // t2ADDSrr + 0U, // t2ADDSrs + 0U, // t2BF_LabelPseudo + 0U, // t2BR_JT + 0U, // t2CALL_BTI + 0U, // t2DoLoopStart + 0U, // t2DoLoopStartTP + 0U, // t2LDMIA_RET + 16384U, // t2LDRBpcrel + 16384U, // t2LDRConstPool + 16384U, // t2LDRHpcrel + 0U, // t2LDRLIT_ga_pcrel + 16384U, // t2LDRSBpcrel + 16384U, // t2LDRSHpcrel + 896U, // t2LDR_POST_imm + 0U, // t2LDR_PRE_imm + 0U, // t2LDRpci_pic + 16384U, // t2LDRpcrel + 0U, // t2LEApcrel + 0U, // t2LEApcrelJT + 0U, // t2LoopDec + 0U, // t2LoopEnd + 0U, // t2LoopEndDec + 0U, // t2MOVCCasr + 0U, // t2MOVCCi + 0U, // t2MOVCCi16 + 0U, // t2MOVCCi32imm + 0U, // t2MOVCClsl + 0U, // t2MOVCClsr + 0U, // t2MOVCCr + 0U, // t2MOVCCror + 1024U, // t2MOVSsi + 1152U, // t2MOVSsr + 0U, // t2MOVTi16_ga_pcrel + 0U, // t2MOV_ga_pcrel + 0U, // t2MOVi16_ga_pcrel + 0U, // t2MOVi32imm + 1024U, // t2MOVsi + 1152U, // t2MOVsr + 0U, // t2MVNCCi + 0U, // t2RSBSri + 0U, // t2RSBSrs + 0U, // t2STRB_preidx + 0U, // t2STRH_preidx + 896U, // t2STR_POST_imm + 0U, // t2STR_PRE_imm + 0U, // t2STR_preidx + 0U, // t2SUBSri + 0U, // t2SUBSrr + 0U, // t2SUBSrs + 0U, // t2SpeculationBarrierISBDSBEndBB + 0U, // t2SpeculationBarrierSBEndBB + 0U, // t2TBB_JT + 0U, // t2TBH_JT + 0U, // t2WhileLoopSetup + 0U, // t2WhileLoopStart + 0U, // t2WhileLoopStartLR + 0U, // t2WhileLoopStartTP + 0U, // tADCS + 0U, // tADDSi3 + 0U, // tADDSi8 + 0U, // tADDSrr + 0U, // tADDframe + 0U, // tADJCALLSTACKDOWN + 0U, // tADJCALLSTACKUP + 0U, // tBLXNS_CALL + 0U, // tBLXr_noip + 0U, // tBL_PUSHLR + 0U, // tBRIND + 0U, // tBR_JTr + 0U, // tBXNS_RET + 0U, // tBX_CALL + 0U, // tBX_RET + 0U, // tBX_RET_vararg + 0U, // tBfar + 0U, // tCMP_SWAP_16 + 0U, // tCMP_SWAP_32 + 0U, // tCMP_SWAP_8 + 0U, // tLDMIA_UPD + 16384U, // tLDRConstPool + 0U, // tLDRLIT_ga_abs + 0U, // tLDRLIT_ga_pcrel + 0U, // tLDR_postidx + 0U, // tLDRpci_pic + 0U, // tLEApcrel + 0U, // tLEApcrelJT + 0U, // tLSLSri + 0U, // tMOVCCr_pseudo + 0U, // tPOP_RET + 0U, // tRSBS + 0U, // tSBCS + 0U, // tSUBSi3 + 0U, // tSUBSi8 + 0U, // tSUBSrr + 0U, // tTAILJMPd + 0U, // tTAILJMPdND + 0U, // tTAILJMPr + 0U, // tTBB_JT + 0U, // tTBH_JT + 0U, // tTPsoft + 1048576U, // ADCri + 0U, // ADCrr + 1572864U, // ADCrsi + 0U, // ADCrsr + 1048576U, // ADDri + 0U, // ADDrr + 1572864U, // ADDrsi + 0U, // ADDrsr + 1280U, // ADR + 2U, // AESD + 2U, // AESE + 2U, // AESIMC + 2U, // AESMC + 1048576U, // ANDri + 0U, // ANDrr + 1572864U, // ANDrsi + 0U, // ANDrsr + 2163072U, // BF16VDOTI_VDOTD + 2163072U, // BF16VDOTI_VDOTQ + 16768U, // BF16VDOTS_VDOTD + 16768U, // BF16VDOTS_VDOTQ + 2U, // BF16_VCVT + 2U, // BF16_VCVTB + 2U, // BF16_VCVTT + 1408U, // BFC + 2622976U, // BFI + 1048576U, // BICri + 0U, // BICrr + 1572864U, // BICrsi + 0U, // BICrsr + 0U, // BKPT + 0U, // BL + 0U, // BLX + 2U, // BLX_pred + 0U, // BLXi + 2U, // BL_pred + 0U, // BX + 2U, // BXJ + 0U, // BX_RET + 2U, // BX_pred + 2U, // Bcc + 2U, // CDE_CX1 + 16776U, // CDE_CX1A + 0U, // CDE_CX1D + 522U, // CDE_CX1DA + 16768U, // CDE_CX2 + 524680U, // CDE_CX2A + 524U, // CDE_CX2D + 2179850U, // CDE_CX2DA + 524672U, // CDE_CX3 + 34079112U, // CDE_CX3A + 2179852U, // CDE_CX3D + 70337290U, // CDE_CX3DA + 2U, // CDE_VCX1A_fpdp + 2U, // CDE_VCX1A_fpsp + 16776U, // CDE_VCX1A_vec + 2U, // CDE_VCX1_fpdp + 2U, // CDE_VCX1_fpsp + 17928U, // CDE_VCX1_vec + 18048U, // CDE_VCX2A_fpdp + 18048U, // CDE_VCX2A_fpsp + 524680U, // CDE_VCX2A_vec + 16768U, // CDE_VCX2_fpdp + 16768U, // CDE_VCX2_fpsp + 3671560U, // CDE_VCX2_vec + 4195968U, // CDE_VCX3A_fpdp + 4195968U, // CDE_VCX3A_fpsp + 34079112U, // CDE_VCX3A_vec + 524672U, // CDE_VCX3_fpdp + 524672U, // CDE_VCX3_fpsp + 37225992U, // CDE_VCX3_vec + 99086U, // CDP + 0U, // CDP2 + 0U, // CLREX + 16384U, // CLZ + 1792U, // CMNri + 16384U, // CMNzrr + 1920U, // CMNzrsi + 1152U, // CMNzrsr + 1792U, // CMPri + 16384U, // CMPrr + 1920U, // CMPrsi + 1152U, // CMPrsr + 0U, // CPS1p + 2U, // CPS2p + 17920U, // CPS3p + 17920U, // CRC32B + 17920U, // CRC32CB + 17920U, // CRC32CH + 17920U, // CRC32CW + 17920U, // CRC32H + 17920U, // CRC32W + 2U, // DBG + 0U, // DMB + 0U, // DSB + 1048576U, // EORri + 0U, // EORrr + 1572864U, // EORrsi + 0U, // EORrsr + 0U, // ERET + 16U, // FCONSTD + 2048U, // FCONSTH + 2048U, // FCONSTS + 530U, // FLDMXDB_UPD + 18560U, // FLDMXIA + 530U, // FLDMXIA_UPD + 0U, // FMSTAT + 530U, // FSTMXDB_UPD + 18560U, // FSTMXIA + 530U, // FSTMXIA_UPD + 2U, // HINT + 0U, // HLT + 0U, // HVC + 0U, // ISB + 128U, // LDA + 128U, // LDAB + 128U, // LDAEX + 128U, // LDAEXB + 0U, // LDAEXD + 128U, // LDAEXH + 128U, // LDAH + 0U, // LDC2L_OFFSET + 2304U, // LDC2L_OPTION + 2432U, // LDC2L_POST + 0U, // LDC2L_PRE + 0U, // LDC2_OFFSET + 2304U, // LDC2_OPTION + 2432U, // LDC2_POST + 0U, // LDC2_PRE + 2580U, // LDCL_OFFSET + 4721300U, // LDCL_OPTION + 5245588U, // LDCL_POST + 22U, // LDCL_PRE + 2580U, // LDC_OFFSET + 4721300U, // LDC_OPTION + 5245588U, // LDC_POST + 22U, // LDC_PRE + 18560U, // LDMDA + 530U, // LDMDA_UPD + 18560U, // LDMDB + 530U, // LDMDB_UPD + 18560U, // LDMIA + 530U, // LDMIA_UPD + 18560U, // LDMIB + 530U, // LDMIB_UPD + 5769856U, // LDRBT_POST_IMM + 5769856U, // LDRBT_POST_REG + 5769856U, // LDRB_POST_IMM + 5769856U, // LDRB_POST_REG + 2816U, // LDRB_PRE_IMM + 2944U, // LDRB_PRE_REG + 3072U, // LDRBi12 + 3200U, // LDRBrs + 6291456U, // LDRD + 40370176U, // LDRD_POST + 7340032U, // LDRD_PRE + 128U, // LDREX + 128U, // LDREXB + 0U, // LDREXD + 128U, // LDREXH + 3328U, // LDRH + 7867008U, // LDRHTi + 8391296U, // LDRHTr + 8915584U, // LDRH_POST + 3456U, // LDRH_PRE + 3328U, // LDRSB + 7867008U, // LDRSBTi + 8391296U, // LDRSBTr + 8915584U, // LDRSB_POST + 3456U, // LDRSB_PRE + 3328U, // LDRSH + 7867008U, // LDRSHTi + 8391296U, // LDRSHTr + 8915584U, // LDRSH_POST + 3456U, // LDRSH_PRE + 5769856U, // LDRT_POST_IMM + 5769856U, // LDRT_POST_REG + 5769856U, // LDR_POST_IMM + 5769856U, // LDR_POST_REG + 2816U, // LDR_PRE_IMM + 2944U, // LDR_PRE_REG + 3072U, // LDRcp + 3072U, // LDRi12 + 3200U, // LDRrs + 103924494U, // MCR + 3584U, // MCR2 + 137478926U, // MCRR + 9437568U, // MCRR2 + 33554432U, // MLA + 33554432U, // MLS + 0U, // MOVPCLR + 17920U, // MOVTi16 + 1792U, // MOVi + 16384U, // MOVi16 + 16384U, // MOVr + 16384U, // MOVr_TC + 1920U, // MOVsi + 1152U, // MOVsr + 131864U, // MRC + 0U, // MRC2 + 0U, // MRRC + 0U, // MRRC2 + 26U, // MRS + 3712U, // MRSbanked + 28U, // MRSsys + 526U, // MSR + 0U, // MSRbanked + 30U, // MSRi + 0U, // MUL + 524288U, // MVE_ASRLi + 524288U, // MVE_ASRLr + 2U, // MVE_DLSTP_16 + 2U, // MVE_DLSTP_32 + 2U, // MVE_DLSTP_64 + 2U, // MVE_DLSTP_8 + 0U, // MVE_LCTP + 0U, // MVE_LETP + 524288U, // MVE_LSLLi + 524288U, // MVE_LSLLr + 524288U, // MVE_LSRL + 17920U, // MVE_SQRSHR + 9961472U, // MVE_SQRSHRL + 17920U, // MVE_SQSHL + 524288U, // MVE_SQSHLL + 17920U, // MVE_SRSHR + 524288U, // MVE_SRSHRL + 17920U, // MVE_UQRSHL + 9961472U, // MVE_UQRSHLL + 17920U, // MVE_UQSHL + 524288U, // MVE_UQSHLL + 17920U, // MVE_URSHR + 524288U, // MVE_URSHRL + 3671552U, // MVE_VABAVs16 + 3671552U, // MVE_VABAVs32 + 3671552U, // MVE_VABAVs8 + 3671552U, // MVE_VABAVu16 + 3671552U, // MVE_VABAVu32 + 3671552U, // MVE_VABAVu8 + 0U, // MVE_VABDf16 + 0U, // MVE_VABDf32 + 0U, // MVE_VABDs16 + 0U, // MVE_VABDs32 + 0U, // MVE_VABDs8 + 0U, // MVE_VABDu16 + 0U, // MVE_VABDu32 + 0U, // MVE_VABDu8 + 16384U, // MVE_VABSf16 + 16384U, // MVE_VABSf32 + 16384U, // MVE_VABSs16 + 16384U, // MVE_VABSs32 + 16384U, // MVE_VABSs8 + 3671552U, // MVE_VADC + 3671552U, // MVE_VADCI + 524288U, // MVE_VADDLVs32acc + 0U, // MVE_VADDLVs32no_acc + 524288U, // MVE_VADDLVu32acc + 0U, // MVE_VADDLVu32no_acc + 17920U, // MVE_VADDVs16acc + 16384U, // MVE_VADDVs16no_acc + 17920U, // MVE_VADDVs32acc + 16384U, // MVE_VADDVs32no_acc + 17920U, // MVE_VADDVs8acc + 16384U, // MVE_VADDVs8no_acc + 17920U, // MVE_VADDVu16acc + 16384U, // MVE_VADDVu16no_acc + 17920U, // MVE_VADDVu32acc + 16384U, // MVE_VADDVu32no_acc + 17920U, // MVE_VADDVu8acc + 16384U, // MVE_VADDVu8no_acc + 0U, // MVE_VADD_qr_f16 + 0U, // MVE_VADD_qr_f32 + 0U, // MVE_VADD_qr_i16 + 0U, // MVE_VADD_qr_i32 + 0U, // MVE_VADD_qr_i8 + 0U, // MVE_VADDf16 + 0U, // MVE_VADDf32 + 0U, // MVE_VADDi16 + 0U, // MVE_VADDi32 + 0U, // MVE_VADDi8 + 0U, // MVE_VAND + 0U, // MVE_VBIC + 3840U, // MVE_VBICimmi16 + 3840U, // MVE_VBICimmi32 + 0U, // MVE_VBRSR16 + 0U, // MVE_VBRSR32 + 0U, // MVE_VBRSR8 + 33554432U, // MVE_VCADDf16 + 33554432U, // MVE_VCADDf32 + 33554432U, // MVE_VCADDi16 + 33554432U, // MVE_VCADDi32 + 33554432U, // MVE_VCADDi8 + 16384U, // MVE_VCLSs16 + 16384U, // MVE_VCLSs32 + 16384U, // MVE_VCLSs8 + 16384U, // MVE_VCLZs16 + 16384U, // MVE_VCLZs32 + 16384U, // MVE_VCLZs8 + 37225984U, // MVE_VCMLAf16 + 37225984U, // MVE_VCMLAf32 + 0U, // MVE_VCMPf16 + 0U, // MVE_VCMPf16r + 0U, // MVE_VCMPf32 + 0U, // MVE_VCMPf32r + 0U, // MVE_VCMPi16 + 0U, // MVE_VCMPi16r + 0U, // MVE_VCMPi32 + 0U, // MVE_VCMPi32r + 0U, // MVE_VCMPi8 + 0U, // MVE_VCMPi8r + 0U, // MVE_VCMPs16 + 0U, // MVE_VCMPs16r + 0U, // MVE_VCMPs32 + 0U, // MVE_VCMPs32r + 0U, // MVE_VCMPs8 + 0U, // MVE_VCMPs8r + 0U, // MVE_VCMPu16 + 0U, // MVE_VCMPu16r + 0U, // MVE_VCMPu32 + 0U, // MVE_VCMPu32r + 0U, // MVE_VCMPu8 + 0U, // MVE_VCMPu8r + 33554432U, // MVE_VCMULf16 + 33554432U, // MVE_VCMULf32 + 2U, // MVE_VCTP16 + 2U, // MVE_VCTP32 + 2U, // MVE_VCTP64 + 2U, // MVE_VCTP8 + 2U, // MVE_VCVTf16f32bh + 2U, // MVE_VCVTf16f32th + 536U, // MVE_VCVTf16s16_fix + 0U, // MVE_VCVTf16s16n + 536U, // MVE_VCVTf16u16_fix + 0U, // MVE_VCVTf16u16n + 0U, // MVE_VCVTf32f16bh + 0U, // MVE_VCVTf32f16th + 536U, // MVE_VCVTf32s32_fix + 0U, // MVE_VCVTf32s32n + 536U, // MVE_VCVTf32u32_fix + 0U, // MVE_VCVTf32u32n + 536U, // MVE_VCVTs16f16_fix + 0U, // MVE_VCVTs16f16a + 0U, // MVE_VCVTs16f16m + 0U, // MVE_VCVTs16f16n + 0U, // MVE_VCVTs16f16p + 0U, // MVE_VCVTs16f16z + 536U, // MVE_VCVTs32f32_fix + 0U, // MVE_VCVTs32f32a + 0U, // MVE_VCVTs32f32m + 0U, // MVE_VCVTs32f32n + 0U, // MVE_VCVTs32f32p + 0U, // MVE_VCVTs32f32z + 536U, // MVE_VCVTu16f16_fix + 0U, // MVE_VCVTu16f16a + 0U, // MVE_VCVTu16f16m + 0U, // MVE_VCVTu16f16n + 0U, // MVE_VCVTu16f16p + 0U, // MVE_VCVTu16f16z + 536U, // MVE_VCVTu32f32_fix + 0U, // MVE_VCVTu32f32a + 0U, // MVE_VCVTu32f32m + 0U, // MVE_VCVTu32f32n + 0U, // MVE_VCVTu32f32p + 0U, // MVE_VCVTu32f32z + 3670016U, // MVE_VDDUPu16 + 3670016U, // MVE_VDDUPu32 + 3670016U, // MVE_VDDUPu8 + 16384U, // MVE_VDUP16 + 16384U, // MVE_VDUP32 + 16384U, // MVE_VDUP8 + 37224448U, // MVE_VDWDUPu16 + 37224448U, // MVE_VDWDUPu32 + 37224448U, // MVE_VDWDUPu8 + 0U, // MVE_VEOR + 3671552U, // MVE_VFMA_qr_Sf16 + 3671552U, // MVE_VFMA_qr_Sf32 + 3671552U, // MVE_VFMA_qr_f16 + 3671552U, // MVE_VFMA_qr_f32 + 3671552U, // MVE_VFMAf16 + 3671552U, // MVE_VFMAf32 + 3671552U, // MVE_VFMSf16 + 3671552U, // MVE_VFMSf32 + 0U, // MVE_VHADD_qr_s16 + 0U, // MVE_VHADD_qr_s32 + 0U, // MVE_VHADD_qr_s8 + 0U, // MVE_VHADD_qr_u16 + 0U, // MVE_VHADD_qr_u32 + 0U, // MVE_VHADD_qr_u8 + 0U, // MVE_VHADDs16 + 0U, // MVE_VHADDs32 + 0U, // MVE_VHADDs8 + 0U, // MVE_VHADDu16 + 0U, // MVE_VHADDu32 + 0U, // MVE_VHADDu8 + 33554432U, // MVE_VHCADDs16 + 33554432U, // MVE_VHCADDs32 + 33554432U, // MVE_VHCADDs8 + 0U, // MVE_VHSUB_qr_s16 + 0U, // MVE_VHSUB_qr_s32 + 0U, // MVE_VHSUB_qr_s8 + 0U, // MVE_VHSUB_qr_u16 + 0U, // MVE_VHSUB_qr_u32 + 0U, // MVE_VHSUB_qr_u8 + 0U, // MVE_VHSUBs16 + 0U, // MVE_VHSUBs32 + 0U, // MVE_VHSUBs8 + 0U, // MVE_VHSUBu16 + 0U, // MVE_VHSUBu32 + 0U, // MVE_VHSUBu8 + 3670016U, // MVE_VIDUPu16 + 3670016U, // MVE_VIDUPu32 + 3670016U, // MVE_VIDUPu8 + 37224448U, // MVE_VIWDUPu16 + 37224448U, // MVE_VIWDUPu32 + 37224448U, // MVE_VIWDUPu8 + 0U, // MVE_VLD20_16 + 0U, // MVE_VLD20_16_wb + 0U, // MVE_VLD20_32 + 0U, // MVE_VLD20_32_wb + 0U, // MVE_VLD20_8 + 0U, // MVE_VLD20_8_wb + 0U, // MVE_VLD21_16 + 0U, // MVE_VLD21_16_wb + 0U, // MVE_VLD21_32 + 0U, // MVE_VLD21_32_wb + 0U, // MVE_VLD21_8 + 0U, // MVE_VLD21_8_wb + 0U, // MVE_VLD40_16 + 0U, // MVE_VLD40_16_wb + 0U, // MVE_VLD40_32 + 0U, // MVE_VLD40_32_wb + 0U, // MVE_VLD40_8 + 0U, // MVE_VLD40_8_wb + 0U, // MVE_VLD41_16 + 0U, // MVE_VLD41_16_wb + 0U, // MVE_VLD41_32 + 0U, // MVE_VLD41_32_wb + 0U, // MVE_VLD41_8 + 0U, // MVE_VLD41_8_wb + 0U, // MVE_VLD42_16 + 0U, // MVE_VLD42_16_wb + 0U, // MVE_VLD42_32 + 0U, // MVE_VLD42_32_wb + 0U, // MVE_VLD42_8 + 0U, // MVE_VLD42_8_wb + 0U, // MVE_VLD43_16 + 0U, // MVE_VLD43_16_wb + 0U, // MVE_VLD43_32 + 0U, // MVE_VLD43_32_wb + 0U, // MVE_VLD43_8 + 0U, // MVE_VLD43_8_wb + 3968U, // MVE_VLDRBS16 + 150144U, // MVE_VLDRBS16_post + 4096U, // MVE_VLDRBS16_pre + 4224U, // MVE_VLDRBS16_rq + 3968U, // MVE_VLDRBS32 + 150144U, // MVE_VLDRBS32_post + 4096U, // MVE_VLDRBS32_pre + 4224U, // MVE_VLDRBS32_rq + 3968U, // MVE_VLDRBU16 + 150144U, // MVE_VLDRBU16_post + 4096U, // MVE_VLDRBU16_pre + 4224U, // MVE_VLDRBU16_rq + 3968U, // MVE_VLDRBU32 + 150144U, // MVE_VLDRBU32_post + 4096U, // MVE_VLDRBU32_pre + 4224U, // MVE_VLDRBU32_rq + 3968U, // MVE_VLDRBU8 + 150144U, // MVE_VLDRBU8_post + 4352U, // MVE_VLDRBU8_pre + 4224U, // MVE_VLDRBU8_rq + 3968U, // MVE_VLDRDU64_qi + 4096U, // MVE_VLDRDU64_qi_pre + 4480U, // MVE_VLDRDU64_rq + 4224U, // MVE_VLDRDU64_rq_u + 3968U, // MVE_VLDRHS32 + 150144U, // MVE_VLDRHS32_post + 4096U, // MVE_VLDRHS32_pre + 4608U, // MVE_VLDRHS32_rq + 4224U, // MVE_VLDRHS32_rq_u + 3968U, // MVE_VLDRHU16 + 150144U, // MVE_VLDRHU16_post + 4352U, // MVE_VLDRHU16_pre + 4608U, // MVE_VLDRHU16_rq + 4224U, // MVE_VLDRHU16_rq_u + 3968U, // MVE_VLDRHU32 + 150144U, // MVE_VLDRHU32_post + 4096U, // MVE_VLDRHU32_pre + 4608U, // MVE_VLDRHU32_rq + 4224U, // MVE_VLDRHU32_rq_u + 3968U, // MVE_VLDRWU32 + 150144U, // MVE_VLDRWU32_post + 4352U, // MVE_VLDRWU32_pre + 3968U, // MVE_VLDRWU32_qi + 4096U, // MVE_VLDRWU32_qi_pre + 4736U, // MVE_VLDRWU32_rq + 4224U, // MVE_VLDRWU32_rq_u + 17920U, // MVE_VMAXAVs16 + 17920U, // MVE_VMAXAVs32 + 17920U, // MVE_VMAXAVs8 + 17920U, // MVE_VMAXAs16 + 17920U, // MVE_VMAXAs32 + 17920U, // MVE_VMAXAs8 + 17920U, // MVE_VMAXNMAVf16 + 17920U, // MVE_VMAXNMAVf32 + 17920U, // MVE_VMAXNMAf16 + 17920U, // MVE_VMAXNMAf32 + 17920U, // MVE_VMAXNMVf16 + 17920U, // MVE_VMAXNMVf32 + 0U, // MVE_VMAXNMf16 + 0U, // MVE_VMAXNMf32 + 17920U, // MVE_VMAXVs16 + 17920U, // MVE_VMAXVs32 + 17920U, // MVE_VMAXVs8 + 17920U, // MVE_VMAXVu16 + 17920U, // MVE_VMAXVu32 + 17920U, // MVE_VMAXVu8 + 0U, // MVE_VMAXs16 + 0U, // MVE_VMAXs32 + 0U, // MVE_VMAXs8 + 0U, // MVE_VMAXu16 + 0U, // MVE_VMAXu32 + 0U, // MVE_VMAXu8 + 17920U, // MVE_VMINAVs16 + 17920U, // MVE_VMINAVs32 + 17920U, // MVE_VMINAVs8 + 17920U, // MVE_VMINAs16 + 17920U, // MVE_VMINAs32 + 17920U, // MVE_VMINAs8 + 17920U, // MVE_VMINNMAVf16 + 17920U, // MVE_VMINNMAVf32 + 17920U, // MVE_VMINNMAf16 + 17920U, // MVE_VMINNMAf32 + 17920U, // MVE_VMINNMVf16 + 17920U, // MVE_VMINNMVf32 + 0U, // MVE_VMINNMf16 + 0U, // MVE_VMINNMf32 + 17920U, // MVE_VMINVs16 + 17920U, // MVE_VMINVs32 + 17920U, // MVE_VMINVs8 + 17920U, // MVE_VMINVu16 + 17920U, // MVE_VMINVu32 + 17920U, // MVE_VMINVu8 + 0U, // MVE_VMINs16 + 0U, // MVE_VMINs32 + 0U, // MVE_VMINs8 + 0U, // MVE_VMINu16 + 0U, // MVE_VMINu32 + 0U, // MVE_VMINu8 + 3671552U, // MVE_VMLADAVas16 + 3671552U, // MVE_VMLADAVas32 + 3671552U, // MVE_VMLADAVas8 + 3671552U, // MVE_VMLADAVau16 + 3671552U, // MVE_VMLADAVau32 + 3671552U, // MVE_VMLADAVau8 + 3671552U, // MVE_VMLADAVaxs16 + 3671552U, // MVE_VMLADAVaxs32 + 3671552U, // MVE_VMLADAVaxs8 + 0U, // MVE_VMLADAVs16 + 0U, // MVE_VMLADAVs32 + 0U, // MVE_VMLADAVs8 + 0U, // MVE_VMLADAVu16 + 0U, // MVE_VMLADAVu32 + 0U, // MVE_VMLADAVu8 + 0U, // MVE_VMLADAVxs16 + 0U, // MVE_VMLADAVxs32 + 0U, // MVE_VMLADAVxs8 + 34078720U, // MVE_VMLALDAVas16 + 34078720U, // MVE_VMLALDAVas32 + 34078720U, // MVE_VMLALDAVau16 + 34078720U, // MVE_VMLALDAVau32 + 34078720U, // MVE_VMLALDAVaxs16 + 34078720U, // MVE_VMLALDAVaxs32 + 33554432U, // MVE_VMLALDAVs16 + 33554432U, // MVE_VMLALDAVs32 + 33554432U, // MVE_VMLALDAVu16 + 33554432U, // MVE_VMLALDAVu32 + 33554432U, // MVE_VMLALDAVxs16 + 33554432U, // MVE_VMLALDAVxs32 + 3671552U, // MVE_VMLAS_qr_i16 + 3671552U, // MVE_VMLAS_qr_i32 + 3671552U, // MVE_VMLAS_qr_i8 + 3671552U, // MVE_VMLA_qr_i16 + 3671552U, // MVE_VMLA_qr_i32 + 3671552U, // MVE_VMLA_qr_i8 + 3671552U, // MVE_VMLSDAVas16 + 3671552U, // MVE_VMLSDAVas32 + 3671552U, // MVE_VMLSDAVas8 + 3671552U, // MVE_VMLSDAVaxs16 + 3671552U, // MVE_VMLSDAVaxs32 + 3671552U, // MVE_VMLSDAVaxs8 + 0U, // MVE_VMLSDAVs16 + 0U, // MVE_VMLSDAVs32 + 0U, // MVE_VMLSDAVs8 + 0U, // MVE_VMLSDAVxs16 + 0U, // MVE_VMLSDAVxs32 + 0U, // MVE_VMLSDAVxs8 + 34078720U, // MVE_VMLSLDAVas16 + 34078720U, // MVE_VMLSLDAVas32 + 34078720U, // MVE_VMLSLDAVaxs16 + 34078720U, // MVE_VMLSLDAVaxs32 + 33554432U, // MVE_VMLSLDAVs16 + 33554432U, // MVE_VMLSLDAVs32 + 33554432U, // MVE_VMLSLDAVxs16 + 33554432U, // MVE_VMLSLDAVxs32 + 16384U, // MVE_VMOVLs16bh + 16384U, // MVE_VMOVLs16th + 16384U, // MVE_VMOVLs8bh + 16384U, // MVE_VMOVLs8th + 16384U, // MVE_VMOVLu16bh + 16384U, // MVE_VMOVLu16th + 16384U, // MVE_VMOVLu8bh + 16384U, // MVE_VMOVLu8th + 17920U, // MVE_VMOVNi16bh + 17920U, // MVE_VMOVNi16th + 17920U, // MVE_VMOVNi32bh + 17920U, // MVE_VMOVNi32th + 163840U, // MVE_VMOV_from_lane_32 + 163840U, // MVE_VMOV_from_lane_s16 + 163840U, // MVE_VMOV_from_lane_s8 + 163840U, // MVE_VMOV_from_lane_u16 + 163840U, // MVE_VMOV_from_lane_u8 + 32U, // MVE_VMOV_q_rr + 167772160U, // MVE_VMOV_rr_q + 34U, // MVE_VMOV_to_lane_16 + 34U, // MVE_VMOV_to_lane_32 + 34U, // MVE_VMOV_to_lane_8 + 2048U, // MVE_VMOVimmf32 + 4864U, // MVE_VMOVimmi16 + 4864U, // MVE_VMOVimmi32 + 0U, // MVE_VMOVimmi64 + 4864U, // MVE_VMOVimmi8 + 0U, // MVE_VMULHs16 + 0U, // MVE_VMULHs32 + 0U, // MVE_VMULHs8 + 0U, // MVE_VMULHu16 + 0U, // MVE_VMULHu32 + 0U, // MVE_VMULHu8 + 0U, // MVE_VMULLBp16 + 0U, // MVE_VMULLBp8 + 0U, // MVE_VMULLBs16 + 0U, // MVE_VMULLBs32 + 0U, // MVE_VMULLBs8 + 0U, // MVE_VMULLBu16 + 0U, // MVE_VMULLBu32 + 0U, // MVE_VMULLBu8 + 0U, // MVE_VMULLTp16 + 0U, // MVE_VMULLTp8 + 0U, // MVE_VMULLTs16 + 0U, // MVE_VMULLTs32 + 0U, // MVE_VMULLTs8 + 0U, // MVE_VMULLTu16 + 0U, // MVE_VMULLTu32 + 0U, // MVE_VMULLTu8 + 0U, // MVE_VMUL_qr_f16 + 0U, // MVE_VMUL_qr_f32 + 0U, // MVE_VMUL_qr_i16 + 0U, // MVE_VMUL_qr_i32 + 0U, // MVE_VMUL_qr_i8 + 0U, // MVE_VMULf16 + 0U, // MVE_VMULf32 + 0U, // MVE_VMULi16 + 0U, // MVE_VMULi32 + 0U, // MVE_VMULi8 + 16384U, // MVE_VMVN + 4864U, // MVE_VMVNimmi16 + 4864U, // MVE_VMVNimmi32 + 16384U, // MVE_VNEGf16 + 16384U, // MVE_VNEGf32 + 16384U, // MVE_VNEGs16 + 16384U, // MVE_VNEGs32 + 16384U, // MVE_VNEGs8 + 0U, // MVE_VORN + 0U, // MVE_VORR + 3840U, // MVE_VORRimmi16 + 3840U, // MVE_VORRimmi32 + 0U, // MVE_VPNOT + 0U, // MVE_VPSEL + 0U, // MVE_VPST + 0U, // MVE_VPTv16i8 + 0U, // MVE_VPTv16i8r + 0U, // MVE_VPTv16s8 + 0U, // MVE_VPTv16s8r + 0U, // MVE_VPTv16u8 + 0U, // MVE_VPTv16u8r + 0U, // MVE_VPTv4f32 + 0U, // MVE_VPTv4f32r + 0U, // MVE_VPTv4i32 + 0U, // MVE_VPTv4i32r + 0U, // MVE_VPTv4s32 + 0U, // MVE_VPTv4s32r + 0U, // MVE_VPTv4u32 + 0U, // MVE_VPTv4u32r + 0U, // MVE_VPTv8f16 + 0U, // MVE_VPTv8f16r + 0U, // MVE_VPTv8i16 + 0U, // MVE_VPTv8i16r + 0U, // MVE_VPTv8s16 + 0U, // MVE_VPTv8s16r + 0U, // MVE_VPTv8u16 + 0U, // MVE_VPTv8u16r + 16384U, // MVE_VQABSs16 + 16384U, // MVE_VQABSs32 + 16384U, // MVE_VQABSs8 + 0U, // MVE_VQADD_qr_s16 + 0U, // MVE_VQADD_qr_s32 + 0U, // MVE_VQADD_qr_s8 + 0U, // MVE_VQADD_qr_u16 + 0U, // MVE_VQADD_qr_u32 + 0U, // MVE_VQADD_qr_u8 + 0U, // MVE_VQADDs16 + 0U, // MVE_VQADDs32 + 0U, // MVE_VQADDs8 + 0U, // MVE_VQADDu16 + 0U, // MVE_VQADDu32 + 0U, // MVE_VQADDu8 + 3671552U, // MVE_VQDMLADHXs16 + 3671552U, // MVE_VQDMLADHXs32 + 3671552U, // MVE_VQDMLADHXs8 + 3671552U, // MVE_VQDMLADHs16 + 3671552U, // MVE_VQDMLADHs32 + 3671552U, // MVE_VQDMLADHs8 + 3671552U, // MVE_VQDMLAH_qrs16 + 3671552U, // MVE_VQDMLAH_qrs32 + 3671552U, // MVE_VQDMLAH_qrs8 + 3671552U, // MVE_VQDMLASH_qrs16 + 3671552U, // MVE_VQDMLASH_qrs32 + 3671552U, // MVE_VQDMLASH_qrs8 + 3671552U, // MVE_VQDMLSDHXs16 + 3671552U, // MVE_VQDMLSDHXs32 + 3671552U, // MVE_VQDMLSDHXs8 + 3671552U, // MVE_VQDMLSDHs16 + 3671552U, // MVE_VQDMLSDHs32 + 3671552U, // MVE_VQDMLSDHs8 + 0U, // MVE_VQDMULH_qr_s16 + 0U, // MVE_VQDMULH_qr_s32 + 0U, // MVE_VQDMULH_qr_s8 + 0U, // MVE_VQDMULHi16 + 0U, // MVE_VQDMULHi32 + 0U, // MVE_VQDMULHi8 + 0U, // MVE_VQDMULL_qr_s16bh + 0U, // MVE_VQDMULL_qr_s16th + 0U, // MVE_VQDMULL_qr_s32bh + 0U, // MVE_VQDMULL_qr_s32th + 0U, // MVE_VQDMULLs16bh + 0U, // MVE_VQDMULLs16th + 0U, // MVE_VQDMULLs32bh + 0U, // MVE_VQDMULLs32th + 17920U, // MVE_VQMOVNs16bh + 17920U, // MVE_VQMOVNs16th + 17920U, // MVE_VQMOVNs32bh + 17920U, // MVE_VQMOVNs32th + 17920U, // MVE_VQMOVNu16bh + 17920U, // MVE_VQMOVNu16th + 17920U, // MVE_VQMOVNu32bh + 17920U, // MVE_VQMOVNu32th + 17920U, // MVE_VQMOVUNs16bh + 17920U, // MVE_VQMOVUNs16th + 17920U, // MVE_VQMOVUNs32bh + 17920U, // MVE_VQMOVUNs32th + 16384U, // MVE_VQNEGs16 + 16384U, // MVE_VQNEGs32 + 16384U, // MVE_VQNEGs8 + 3671552U, // MVE_VQRDMLADHXs16 + 3671552U, // MVE_VQRDMLADHXs32 + 3671552U, // MVE_VQRDMLADHXs8 + 3671552U, // MVE_VQRDMLADHs16 + 3671552U, // MVE_VQRDMLADHs32 + 3671552U, // MVE_VQRDMLADHs8 + 3671552U, // MVE_VQRDMLAH_qrs16 + 3671552U, // MVE_VQRDMLAH_qrs32 + 3671552U, // MVE_VQRDMLAH_qrs8 + 3671552U, // MVE_VQRDMLASH_qrs16 + 3671552U, // MVE_VQRDMLASH_qrs32 + 3671552U, // MVE_VQRDMLASH_qrs8 + 3671552U, // MVE_VQRDMLSDHXs16 + 3671552U, // MVE_VQRDMLSDHXs32 + 3671552U, // MVE_VQRDMLSDHXs8 + 3671552U, // MVE_VQRDMLSDHs16 + 3671552U, // MVE_VQRDMLSDHs32 + 3671552U, // MVE_VQRDMLSDHs8 + 0U, // MVE_VQRDMULH_qr_s16 + 0U, // MVE_VQRDMULH_qr_s32 + 0U, // MVE_VQRDMULH_qr_s8 + 0U, // MVE_VQRDMULHi16 + 0U, // MVE_VQRDMULHi32 + 0U, // MVE_VQRDMULHi8 + 0U, // MVE_VQRSHL_by_vecs16 + 0U, // MVE_VQRSHL_by_vecs32 + 0U, // MVE_VQRSHL_by_vecs8 + 0U, // MVE_VQRSHL_by_vecu16 + 0U, // MVE_VQRSHL_by_vecu32 + 0U, // MVE_VQRSHL_by_vecu8 + 17920U, // MVE_VQRSHL_qrs16 + 17920U, // MVE_VQRSHL_qrs32 + 17920U, // MVE_VQRSHL_qrs8 + 17920U, // MVE_VQRSHL_qru16 + 17920U, // MVE_VQRSHL_qru32 + 17920U, // MVE_VQRSHL_qru8 + 3671552U, // MVE_VQRSHRNbhs16 + 3671552U, // MVE_VQRSHRNbhs32 + 3671552U, // MVE_VQRSHRNbhu16 + 3671552U, // MVE_VQRSHRNbhu32 + 3671552U, // MVE_VQRSHRNths16 + 3671552U, // MVE_VQRSHRNths32 + 3671552U, // MVE_VQRSHRNthu16 + 3671552U, // MVE_VQRSHRNthu32 + 3671552U, // MVE_VQRSHRUNs16bh + 3671552U, // MVE_VQRSHRUNs16th + 3671552U, // MVE_VQRSHRUNs32bh + 3671552U, // MVE_VQRSHRUNs32th + 0U, // MVE_VQSHLU_imms16 + 0U, // MVE_VQSHLU_imms32 + 0U, // MVE_VQSHLU_imms8 + 0U, // MVE_VQSHL_by_vecs16 + 0U, // MVE_VQSHL_by_vecs32 + 0U, // MVE_VQSHL_by_vecs8 + 0U, // MVE_VQSHL_by_vecu16 + 0U, // MVE_VQSHL_by_vecu32 + 0U, // MVE_VQSHL_by_vecu8 + 17920U, // MVE_VQSHL_qrs16 + 17920U, // MVE_VQSHL_qrs32 + 17920U, // MVE_VQSHL_qrs8 + 17920U, // MVE_VQSHL_qru16 + 17920U, // MVE_VQSHL_qru32 + 17920U, // MVE_VQSHL_qru8 + 0U, // MVE_VQSHLimms16 + 0U, // MVE_VQSHLimms32 + 0U, // MVE_VQSHLimms8 + 0U, // MVE_VQSHLimmu16 + 0U, // MVE_VQSHLimmu32 + 0U, // MVE_VQSHLimmu8 + 3671552U, // MVE_VQSHRNbhs16 + 3671552U, // MVE_VQSHRNbhs32 + 3671552U, // MVE_VQSHRNbhu16 + 3671552U, // MVE_VQSHRNbhu32 + 3671552U, // MVE_VQSHRNths16 + 3671552U, // MVE_VQSHRNths32 + 3671552U, // MVE_VQSHRNthu16 + 3671552U, // MVE_VQSHRNthu32 + 3671552U, // MVE_VQSHRUNs16bh + 3671552U, // MVE_VQSHRUNs16th + 3671552U, // MVE_VQSHRUNs32bh + 3671552U, // MVE_VQSHRUNs32th + 0U, // MVE_VQSUB_qr_s16 + 0U, // MVE_VQSUB_qr_s32 + 0U, // MVE_VQSUB_qr_s8 + 0U, // MVE_VQSUB_qr_u16 + 0U, // MVE_VQSUB_qr_u32 + 0U, // MVE_VQSUB_qr_u8 + 0U, // MVE_VQSUBs16 + 0U, // MVE_VQSUBs32 + 0U, // MVE_VQSUBs8 + 0U, // MVE_VQSUBu16 + 0U, // MVE_VQSUBu32 + 0U, // MVE_VQSUBu8 + 16384U, // MVE_VREV16_8 + 16384U, // MVE_VREV32_16 + 16384U, // MVE_VREV32_8 + 16384U, // MVE_VREV64_16 + 16384U, // MVE_VREV64_32 + 16384U, // MVE_VREV64_8 + 0U, // MVE_VRHADDs16 + 0U, // MVE_VRHADDs32 + 0U, // MVE_VRHADDs8 + 0U, // MVE_VRHADDu16 + 0U, // MVE_VRHADDu32 + 0U, // MVE_VRHADDu8 + 16384U, // MVE_VRINTf16A + 16384U, // MVE_VRINTf16M + 16384U, // MVE_VRINTf16N + 16384U, // MVE_VRINTf16P + 16384U, // MVE_VRINTf16X + 16384U, // MVE_VRINTf16Z + 16384U, // MVE_VRINTf32A + 16384U, // MVE_VRINTf32M + 16384U, // MVE_VRINTf32N + 16384U, // MVE_VRINTf32P + 16384U, // MVE_VRINTf32X + 16384U, // MVE_VRINTf32Z + 34078720U, // MVE_VRMLALDAVHas32 + 34078720U, // MVE_VRMLALDAVHau32 + 34078720U, // MVE_VRMLALDAVHaxs32 + 33554432U, // MVE_VRMLALDAVHs32 + 33554432U, // MVE_VRMLALDAVHu32 + 33554432U, // MVE_VRMLALDAVHxs32 + 34078720U, // MVE_VRMLSLDAVHas32 + 34078720U, // MVE_VRMLSLDAVHaxs32 + 33554432U, // MVE_VRMLSLDAVHs32 + 33554432U, // MVE_VRMLSLDAVHxs32 + 0U, // MVE_VRMULHs16 + 0U, // MVE_VRMULHs32 + 0U, // MVE_VRMULHs8 + 0U, // MVE_VRMULHu16 + 0U, // MVE_VRMULHu32 + 0U, // MVE_VRMULHu8 + 0U, // MVE_VRSHL_by_vecs16 + 0U, // MVE_VRSHL_by_vecs32 + 0U, // MVE_VRSHL_by_vecs8 + 0U, // MVE_VRSHL_by_vecu16 + 0U, // MVE_VRSHL_by_vecu32 + 0U, // MVE_VRSHL_by_vecu8 + 17920U, // MVE_VRSHL_qrs16 + 17920U, // MVE_VRSHL_qrs32 + 17920U, // MVE_VRSHL_qrs8 + 17920U, // MVE_VRSHL_qru16 + 17920U, // MVE_VRSHL_qru32 + 17920U, // MVE_VRSHL_qru8 + 3671552U, // MVE_VRSHRNi16bh + 3671552U, // MVE_VRSHRNi16th + 3671552U, // MVE_VRSHRNi32bh + 3671552U, // MVE_VRSHRNi32th + 0U, // MVE_VRSHR_imms16 + 0U, // MVE_VRSHR_imms32 + 0U, // MVE_VRSHR_imms8 + 0U, // MVE_VRSHR_immu16 + 0U, // MVE_VRSHR_immu32 + 0U, // MVE_VRSHR_immu8 + 3671552U, // MVE_VSBC + 3671552U, // MVE_VSBCI + 524672U, // MVE_VSHLC + 0U, // MVE_VSHLL_imms16bh + 0U, // MVE_VSHLL_imms16th + 0U, // MVE_VSHLL_imms8bh + 0U, // MVE_VSHLL_imms8th + 0U, // MVE_VSHLL_immu16bh + 0U, // MVE_VSHLL_immu16th + 0U, // MVE_VSHLL_immu8bh + 0U, // MVE_VSHLL_immu8th + 180224U, // MVE_VSHLL_lws16bh + 180224U, // MVE_VSHLL_lws16th + 196608U, // MVE_VSHLL_lws8bh + 196608U, // MVE_VSHLL_lws8th + 180224U, // MVE_VSHLL_lwu16bh + 180224U, // MVE_VSHLL_lwu16th + 196608U, // MVE_VSHLL_lwu8bh + 196608U, // MVE_VSHLL_lwu8th + 0U, // MVE_VSHL_by_vecs16 + 0U, // MVE_VSHL_by_vecs32 + 0U, // MVE_VSHL_by_vecs8 + 0U, // MVE_VSHL_by_vecu16 + 0U, // MVE_VSHL_by_vecu32 + 0U, // MVE_VSHL_by_vecu8 + 0U, // MVE_VSHL_immi16 + 0U, // MVE_VSHL_immi32 + 0U, // MVE_VSHL_immi8 + 17920U, // MVE_VSHL_qrs16 + 17920U, // MVE_VSHL_qrs32 + 17920U, // MVE_VSHL_qrs8 + 17920U, // MVE_VSHL_qru16 + 17920U, // MVE_VSHL_qru32 + 17920U, // MVE_VSHL_qru8 + 3671552U, // MVE_VSHRNi16bh + 3671552U, // MVE_VSHRNi16th + 3671552U, // MVE_VSHRNi32bh + 3671552U, // MVE_VSHRNi32th + 0U, // MVE_VSHR_imms16 + 0U, // MVE_VSHR_imms32 + 0U, // MVE_VSHR_imms8 + 0U, // MVE_VSHR_immu16 + 0U, // MVE_VSHR_immu32 + 0U, // MVE_VSHR_immu8 + 3671552U, // MVE_VSLIimm16 + 3671552U, // MVE_VSLIimm32 + 3671552U, // MVE_VSLIimm8 + 3671552U, // MVE_VSRIimm16 + 3671552U, // MVE_VSRIimm32 + 3671552U, // MVE_VSRIimm8 + 0U, // MVE_VST20_16 + 0U, // MVE_VST20_16_wb + 0U, // MVE_VST20_32 + 0U, // MVE_VST20_32_wb + 0U, // MVE_VST20_8 + 0U, // MVE_VST20_8_wb + 0U, // MVE_VST21_16 + 0U, // MVE_VST21_16_wb + 0U, // MVE_VST21_32 + 0U, // MVE_VST21_32_wb + 0U, // MVE_VST21_8 + 0U, // MVE_VST21_8_wb + 0U, // MVE_VST40_16 + 0U, // MVE_VST40_16_wb + 0U, // MVE_VST40_32 + 0U, // MVE_VST40_32_wb + 0U, // MVE_VST40_8 + 0U, // MVE_VST40_8_wb + 0U, // MVE_VST41_16 + 0U, // MVE_VST41_16_wb + 0U, // MVE_VST41_32 + 0U, // MVE_VST41_32_wb + 0U, // MVE_VST41_8 + 0U, // MVE_VST41_8_wb + 0U, // MVE_VST42_16 + 0U, // MVE_VST42_16_wb + 0U, // MVE_VST42_32 + 0U, // MVE_VST42_32_wb + 0U, // MVE_VST42_8 + 0U, // MVE_VST42_8_wb + 0U, // MVE_VST43_16 + 0U, // MVE_VST43_16_wb + 0U, // MVE_VST43_32 + 0U, // MVE_VST43_32_wb + 0U, // MVE_VST43_8 + 0U, // MVE_VST43_8_wb + 3968U, // MVE_VSTRB16 + 150144U, // MVE_VSTRB16_post + 4096U, // MVE_VSTRB16_pre + 4224U, // MVE_VSTRB16_rq + 3968U, // MVE_VSTRB32 + 150144U, // MVE_VSTRB32_post + 4096U, // MVE_VSTRB32_pre + 4224U, // MVE_VSTRB32_rq + 4224U, // MVE_VSTRB8_rq + 3968U, // MVE_VSTRBU8 + 150144U, // MVE_VSTRBU8_post + 4352U, // MVE_VSTRBU8_pre + 3968U, // MVE_VSTRD64_qi + 4096U, // MVE_VSTRD64_qi_pre + 4480U, // MVE_VSTRD64_rq + 4224U, // MVE_VSTRD64_rq_u + 4608U, // MVE_VSTRH16_rq + 4224U, // MVE_VSTRH16_rq_u + 3968U, // MVE_VSTRH32 + 150144U, // MVE_VSTRH32_post + 4096U, // MVE_VSTRH32_pre + 4608U, // MVE_VSTRH32_rq + 4224U, // MVE_VSTRH32_rq_u + 3968U, // MVE_VSTRHU16 + 150144U, // MVE_VSTRHU16_post + 4352U, // MVE_VSTRHU16_pre + 3968U, // MVE_VSTRW32_qi + 4096U, // MVE_VSTRW32_qi_pre + 4736U, // MVE_VSTRW32_rq + 4224U, // MVE_VSTRW32_rq_u + 3968U, // MVE_VSTRWU32 + 150144U, // MVE_VSTRWU32_post + 4352U, // MVE_VSTRWU32_pre + 0U, // MVE_VSUB_qr_f16 + 0U, // MVE_VSUB_qr_f32 + 0U, // MVE_VSUB_qr_i16 + 0U, // MVE_VSUB_qr_i32 + 0U, // MVE_VSUB_qr_i8 + 0U, // MVE_VSUBf16 + 0U, // MVE_VSUBf32 + 0U, // MVE_VSUBi16 + 0U, // MVE_VSUBi32 + 0U, // MVE_VSUBi8 + 21376U, // MVE_WLSTP_16 + 21376U, // MVE_WLSTP_32 + 21376U, // MVE_WLSTP_64 + 21376U, // MVE_WLSTP_8 + 1792U, // MVNi + 16384U, // MVNr + 1920U, // MVNsi + 1152U, // MVNsr + 17920U, // NEON_VMAXNMNDf + 17920U, // NEON_VMAXNMNDh + 17920U, // NEON_VMAXNMNQf + 17920U, // NEON_VMAXNMNQh + 17920U, // NEON_VMINNMNDf + 17920U, // NEON_VMINNMNDh + 17920U, // NEON_VMINNMNQf + 17920U, // NEON_VMINNMNQh + 1048576U, // ORRri + 0U, // ORRrr + 1572864U, // ORRrsi + 0U, // ORRrsr + 201326592U, // PKHBT + 234881024U, // PKHTB + 0U, // PLDWi12 + 0U, // PLDWrs + 0U, // PLDi12 + 0U, // PLDrs + 0U, // PLIi12 + 0U, // PLIrs + 0U, // QADD + 0U, // QADD16 + 0U, // QADD8 + 0U, // QASX + 0U, // QDADD + 0U, // QDSUB + 0U, // QSAX + 0U, // QSUB + 0U, // QSUB16 + 0U, // QSUB8 + 16384U, // RBIT + 16384U, // REV + 16384U, // REV16 + 16384U, // REVSH + 0U, // RFEDA + 0U, // RFEDA_UPD + 0U, // RFEDB + 0U, // RFEDB_UPD + 0U, // RFEIA + 0U, // RFEIA_UPD + 0U, // RFEIB + 0U, // RFEIB_UPD + 1048576U, // RSBri + 0U, // RSBrr + 1572864U, // RSBrsi + 0U, // RSBrsr + 1048576U, // RSCri + 0U, // RSCrr + 1572864U, // RSCrsi + 0U, // RSCrsr + 0U, // SADD16 + 0U, // SADD8 + 0U, // SASX + 0U, // SB + 1048576U, // SBCri + 0U, // SBCrr + 1572864U, // SBCrsi + 0U, // SBCrsr + 33554432U, // SBFX + 0U, // SDIV + 0U, // SEL + 0U, // SETEND + 0U, // SETPAN + 16768U, // SHA1C + 2U, // SHA1H + 16768U, // SHA1M + 16768U, // SHA1P + 16768U, // SHA1SU0 + 2U, // SHA1SU1 + 16768U, // SHA256H + 16768U, // SHA256H2 + 2U, // SHA256SU0 + 16768U, // SHA256SU1 + 0U, // SHADD16 + 0U, // SHADD8 + 0U, // SHASX + 0U, // SHSAX + 0U, // SHSUB16 + 0U, // SHSUB8 + 2U, // SMC + 33554432U, // SMLABB + 33554432U, // SMLABT + 33554432U, // SMLAD + 33554432U, // SMLADX + 0U, // SMLAL + 33554432U, // SMLALBB + 33554432U, // SMLALBT + 33554432U, // SMLALD + 33554432U, // SMLALDX + 33554432U, // SMLALTB + 33554432U, // SMLALTT + 33554432U, // SMLATB + 33554432U, // SMLATT + 33554432U, // SMLAWB + 33554432U, // SMLAWT + 33554432U, // SMLSD + 33554432U, // SMLSDX + 33554432U, // SMLSLD + 33554432U, // SMLSLDX + 33554432U, // SMMLA + 33554432U, // SMMLAR + 33554432U, // SMMLS + 33554432U, // SMMLSR + 0U, // SMMUL + 0U, // SMMULR + 0U, // SMUAD + 0U, // SMUADX + 0U, // SMULBB + 0U, // SMULBT + 33554432U, // SMULL + 0U, // SMULTB + 0U, // SMULTT + 0U, // SMULWB + 0U, // SMULWT + 0U, // SMUSD + 0U, // SMUSDX + 0U, // SRSDA + 0U, // SRSDA_UPD + 0U, // SRSDB + 0U, // SRSDB_UPD + 0U, // SRSIA + 0U, // SRSIA_UPD + 0U, // SRSIB + 0U, // SRSIB_UPD + 218112U, // SSAT + 21504U, // SSAT16 + 0U, // SSAX + 0U, // SSUB16 + 0U, // SSUB8 + 0U, // STC2L_OFFSET + 2304U, // STC2L_OPTION + 2432U, // STC2L_POST + 0U, // STC2L_PRE + 0U, // STC2_OFFSET + 2304U, // STC2_OPTION + 2432U, // STC2_POST + 0U, // STC2_PRE + 2580U, // STCL_OFFSET + 4721300U, // STCL_OPTION + 5245588U, // STCL_POST + 22U, // STCL_PRE + 2580U, // STC_OFFSET + 4721300U, // STC_OPTION + 5245588U, // STC_POST + 22U, // STC_PRE + 128U, // STL + 128U, // STLB + 10485760U, // STLEX + 10485760U, // STLEXB + 5248U, // STLEXD + 10485760U, // STLEXH + 128U, // STLH + 18560U, // STMDA + 530U, // STMDA_UPD + 18560U, // STMDB + 530U, // STMDB_UPD + 18560U, // STMIA + 530U, // STMIA_UPD + 18560U, // STMIB + 530U, // STMIB_UPD + 5769856U, // STRBT_POST_IMM + 5769856U, // STRBT_POST_REG + 5769856U, // STRB_POST_IMM + 5769856U, // STRB_POST_REG + 2816U, // STRB_PRE_IMM + 2944U, // STRB_PRE_REG + 3072U, // STRBi12 + 3200U, // STRBrs + 6291456U, // STRD + 40371712U, // STRD_POST + 7341568U, // STRD_PRE + 10485760U, // STREX + 10485760U, // STREXB + 5248U, // STREXD + 10485760U, // STREXH + 3328U, // STRH + 7867008U, // STRHTi + 8391296U, // STRHTr + 8915584U, // STRH_POST + 3456U, // STRH_PRE + 5769856U, // STRT_POST_IMM + 5769856U, // STRT_POST_REG + 5769856U, // STR_POST_IMM + 5769856U, // STR_POST_REG + 2816U, // STR_PRE_IMM + 2944U, // STR_PRE_REG + 3072U, // STRi12 + 3200U, // STRrs + 1048576U, // SUBri + 0U, // SUBrr + 1572864U, // SUBrsi + 0U, // SUBrsr + 2U, // SVC + 10485760U, // SWP + 10485760U, // SWPB + 268435456U, // SXTAB + 268435456U, // SXTAB16 + 268435456U, // SXTAH + 229376U, // SXTB + 229376U, // SXTB16 + 229376U, // SXTH + 1792U, // TEQri + 16384U, // TEQrr + 1920U, // TEQrsi + 1152U, // TEQrsr + 0U, // TRAP + 0U, // TRAPNaCl + 0U, // TSB + 1792U, // TSTri + 16384U, // TSTrr + 1920U, // TSTrsi + 1152U, // TSTrsr + 0U, // UADD16 + 0U, // UADD8 + 0U, // UASX + 33554432U, // UBFX + 0U, // UDF + 0U, // UDIV + 0U, // UHADD16 + 0U, // UHADD8 + 0U, // UHASX + 0U, // UHSAX + 0U, // UHSUB16 + 0U, // UHSUB8 + 33554432U, // UMAAL + 0U, // UMLAL + 33554432U, // UMULL + 0U, // UQADD16 + 0U, // UQADD8 + 0U, // UQASX + 0U, // UQSAX + 0U, // UQSUB16 + 0U, // UQSUB8 + 0U, // USAD8 + 33554432U, // USADA8 + 301989888U, // USAT + 0U, // USAT16 + 0U, // USAX + 0U, // USUB16 + 0U, // USUB8 + 268435456U, // UXTAB + 268435456U, // UXTAB16 + 268435456U, // UXTAH + 229376U, // UXTB + 229376U, // UXTB16 + 229376U, // UXTH + 3671552U, // VABALsv2i64 + 3671552U, // VABALsv4i32 + 3671552U, // VABALsv8i16 + 3671552U, // VABALuv2i64 + 3671552U, // VABALuv4i32 + 3671552U, // VABALuv8i16 + 3671552U, // VABAsv16i8 + 3671552U, // VABAsv2i32 + 3671552U, // VABAsv4i16 + 3671552U, // VABAsv4i32 + 3671552U, // VABAsv8i16 + 3671552U, // VABAsv8i8 + 3671552U, // VABAuv16i8 + 3671552U, // VABAuv2i32 + 3671552U, // VABAuv4i16 + 3671552U, // VABAuv4i32 + 3671552U, // VABAuv8i16 + 3671552U, // VABAuv8i8 + 0U, // VABDLsv2i64 + 0U, // VABDLsv4i32 + 0U, // VABDLsv8i16 + 0U, // VABDLuv2i64 + 0U, // VABDLuv4i32 + 0U, // VABDLuv8i16 + 0U, // VABDfd + 0U, // VABDfq + 0U, // VABDhd + 0U, // VABDhq + 0U, // VABDsv16i8 + 0U, // VABDsv2i32 + 0U, // VABDsv4i16 + 0U, // VABDsv4i32 + 0U, // VABDsv8i16 + 0U, // VABDsv8i8 + 0U, // VABDuv16i8 + 0U, // VABDuv2i32 + 0U, // VABDuv4i16 + 0U, // VABDuv4i32 + 0U, // VABDuv8i16 + 0U, // VABDuv8i8 + 526U, // VABSD + 16384U, // VABSH + 16384U, // VABSS + 16384U, // VABSfd + 16384U, // VABSfq + 16384U, // VABShd + 16384U, // VABShq + 16384U, // VABSv16i8 + 16384U, // VABSv2i32 + 16384U, // VABSv4i16 + 16384U, // VABSv4i32 + 16384U, // VABSv8i16 + 16384U, // VABSv8i8 + 0U, // VACGEfd + 0U, // VACGEfq + 0U, // VACGEhd + 0U, // VACGEhq + 0U, // VACGTfd + 0U, // VACGTfq + 0U, // VACGThd + 0U, // VACGThq + 2212622U, // VADDD + 0U, // VADDH + 17920U, // VADDHNv2i32 + 0U, // VADDHNv4i16 + 0U, // VADDHNv8i8 + 0U, // VADDLsv2i64 + 0U, // VADDLsv4i32 + 0U, // VADDLsv8i16 + 0U, // VADDLuv2i64 + 0U, // VADDLuv4i32 + 0U, // VADDLuv8i16 + 0U, // VADDS + 0U, // VADDWsv2i64 + 0U, // VADDWsv4i32 + 0U, // VADDWsv8i16 + 0U, // VADDWuv2i64 + 0U, // VADDWuv4i32 + 0U, // VADDWuv8i16 + 0U, // VADDfd + 0U, // VADDfq + 0U, // VADDhd + 0U, // VADDhq + 0U, // VADDv16i8 + 17920U, // VADDv1i64 + 0U, // VADDv2i32 + 17920U, // VADDv2i64 + 0U, // VADDv4i16 + 0U, // VADDv4i32 + 0U, // VADDv8i16 + 0U, // VADDv8i8 + 0U, // VANDd + 0U, // VANDq + 16768U, // VBF16MALBQ + 2163072U, // VBF16MALBQI + 16768U, // VBF16MALTQ + 2163072U, // VBF16MALTQI + 0U, // VBICd + 4864U, // VBICiv2i32 + 4864U, // VBICiv4i16 + 4864U, // VBICiv4i32 + 4864U, // VBICiv8i16 + 0U, // VBICq + 3671552U, // VBIFd + 3671552U, // VBIFq + 3671552U, // VBITd + 3671552U, // VBITq + 3671552U, // VBSLd + 3671552U, // VBSLq + 0U, // VBSPd + 0U, // VBSPq + 11011584U, // VCADDv2f32 + 11011584U, // VCADDv4f16 + 11011584U, // VCADDv4f32 + 11011584U, // VCADDv8f16 + 0U, // VCEQfd + 0U, // VCEQfq + 0U, // VCEQhd + 0U, // VCEQhq + 0U, // VCEQv16i8 + 0U, // VCEQv2i32 + 0U, // VCEQv4i16 + 0U, // VCEQv4i32 + 0U, // VCEQv8i16 + 0U, // VCEQv8i8 + 245760U, // VCEQzv16i8 + 245760U, // VCEQzv2f32 + 245760U, // VCEQzv2i32 + 245760U, // VCEQzv4f16 + 245760U, // VCEQzv4f32 + 245760U, // VCEQzv4i16 + 245760U, // VCEQzv4i32 + 245760U, // VCEQzv8f16 + 245760U, // VCEQzv8i16 + 245760U, // VCEQzv8i8 + 0U, // VCGEfd + 0U, // VCGEfq + 0U, // VCGEhd + 0U, // VCGEhq + 0U, // VCGEsv16i8 + 0U, // VCGEsv2i32 + 0U, // VCGEsv4i16 + 0U, // VCGEsv4i32 + 0U, // VCGEsv8i16 + 0U, // VCGEsv8i8 + 0U, // VCGEuv16i8 + 0U, // VCGEuv2i32 + 0U, // VCGEuv4i16 + 0U, // VCGEuv4i32 + 0U, // VCGEuv8i16 + 0U, // VCGEuv8i8 + 245760U, // VCGEzv16i8 + 245760U, // VCGEzv2f32 + 245760U, // VCGEzv2i32 + 245760U, // VCGEzv4f16 + 245760U, // VCGEzv4f32 + 245760U, // VCGEzv4i16 + 245760U, // VCGEzv4i32 + 245760U, // VCGEzv8f16 + 245760U, // VCGEzv8i16 + 245760U, // VCGEzv8i8 + 0U, // VCGTfd + 0U, // VCGTfq + 0U, // VCGThd + 0U, // VCGThq + 0U, // VCGTsv16i8 + 0U, // VCGTsv2i32 + 0U, // VCGTsv4i16 + 0U, // VCGTsv4i32 + 0U, // VCGTsv8i16 + 0U, // VCGTsv8i8 + 0U, // VCGTuv16i8 + 0U, // VCGTuv2i32 + 0U, // VCGTuv4i16 + 0U, // VCGTuv4i32 + 0U, // VCGTuv8i16 + 0U, // VCGTuv8i8 + 245760U, // VCGTzv16i8 + 245760U, // VCGTzv2f32 + 245760U, // VCGTzv2i32 + 245760U, // VCGTzv4f16 + 245760U, // VCGTzv4f32 + 245760U, // VCGTzv4i16 + 245760U, // VCGTzv4i32 + 245760U, // VCGTzv8f16 + 245760U, // VCGTzv8i16 + 245760U, // VCGTzv8i8 + 245760U, // VCLEzv16i8 + 245760U, // VCLEzv2f32 + 245760U, // VCLEzv2i32 + 245760U, // VCLEzv4f16 + 245760U, // VCLEzv4f32 + 245760U, // VCLEzv4i16 + 245760U, // VCLEzv4i32 + 245760U, // VCLEzv8f16 + 245760U, // VCLEzv8i16 + 245760U, // VCLEzv8i8 + 16384U, // VCLSv16i8 + 16384U, // VCLSv2i32 + 16384U, // VCLSv4i16 + 16384U, // VCLSv4i32 + 16384U, // VCLSv8i16 + 16384U, // VCLSv8i8 + 245760U, // VCLTzv16i8 + 245760U, // VCLTzv2f32 + 245760U, // VCLTzv2i32 + 245760U, // VCLTzv4f16 + 245760U, // VCLTzv4f32 + 245760U, // VCLTzv4i16 + 245760U, // VCLTzv4i32 + 245760U, // VCLTzv8f16 + 245760U, // VCLTzv8i16 + 245760U, // VCLTzv8i8 + 16384U, // VCLZv16i8 + 16384U, // VCLZv2i32 + 16384U, // VCLZv4i16 + 16384U, // VCLZv4i32 + 16384U, // VCLZv8i16 + 16384U, // VCLZv8i8 + 11534720U, // VCMLAv2f32 + 338755968U, // VCMLAv2f32_indexed + 11534720U, // VCMLAv4f16 + 338755968U, // VCMLAv4f16_indexed + 11534720U, // VCMLAv4f32 + 338755968U, // VCMLAv4f32_indexed + 11534720U, // VCMLAv8f16 + 338755968U, // VCMLAv8f16_indexed + 526U, // VCMPD + 526U, // VCMPED + 16384U, // VCMPEH + 16384U, // VCMPES + 0U, // VCMPEZD + 36U, // VCMPEZH + 36U, // VCMPEZS + 16384U, // VCMPH + 16384U, // VCMPS + 0U, // VCMPZD + 36U, // VCMPZH + 36U, // VCMPZS + 16384U, // VCNTd + 16384U, // VCNTq + 2U, // VCVTANSDf + 2U, // VCVTANSDh + 2U, // VCVTANSQf + 2U, // VCVTANSQh + 2U, // VCVTANUDf + 2U, // VCVTANUDh + 2U, // VCVTANUQf + 2U, // VCVTANUQh + 2U, // VCVTASD + 2U, // VCVTASH + 2U, // VCVTASS + 2U, // VCVTAUD + 2U, // VCVTAUH + 2U, // VCVTAUS + 0U, // VCVTBDH + 0U, // VCVTBHD + 0U, // VCVTBHS + 2U, // VCVTBSH + 0U, // VCVTDS + 2U, // VCVTMNSDf + 2U, // VCVTMNSDh + 2U, // VCVTMNSQf + 2U, // VCVTMNSQh + 2U, // VCVTMNUDf + 2U, // VCVTMNUDh + 2U, // VCVTMNUQf + 2U, // VCVTMNUQh + 2U, // VCVTMSD + 2U, // VCVTMSH + 2U, // VCVTMSS + 2U, // VCVTMUD + 2U, // VCVTMUH + 2U, // VCVTMUS + 2U, // VCVTNNSDf + 2U, // VCVTNNSDh + 2U, // VCVTNNSQf + 2U, // VCVTNNSQh + 2U, // VCVTNNUDf + 2U, // VCVTNNUDh + 2U, // VCVTNNUQf + 2U, // VCVTNNUQh + 2U, // VCVTNSD + 2U, // VCVTNSH + 2U, // VCVTNSS + 2U, // VCVTNUD + 2U, // VCVTNUH + 2U, // VCVTNUS + 2U, // VCVTPNSDf + 2U, // VCVTPNSDh + 2U, // VCVTPNSQf + 2U, // VCVTPNSQh + 2U, // VCVTPNUDf + 2U, // VCVTPNUDh + 2U, // VCVTPNUQf + 2U, // VCVTPNUQh + 2U, // VCVTPSD + 2U, // VCVTPSH + 2U, // VCVTPSS + 2U, // VCVTPUD + 2U, // VCVTPUH + 2U, // VCVTPUS + 0U, // VCVTSD + 0U, // VCVTTDH + 0U, // VCVTTHD + 0U, // VCVTTHS + 2U, // VCVTTSH + 2U, // VCVTf2h + 0U, // VCVTf2sd + 0U, // VCVTf2sq + 0U, // VCVTf2ud + 0U, // VCVTf2uq + 536U, // VCVTf2xsd + 536U, // VCVTf2xsq + 536U, // VCVTf2xud + 536U, // VCVTf2xuq + 0U, // VCVTh2f + 0U, // VCVTh2sd + 0U, // VCVTh2sq + 0U, // VCVTh2ud + 0U, // VCVTh2uq + 536U, // VCVTh2xsd + 536U, // VCVTh2xsq + 536U, // VCVTh2xud + 536U, // VCVTh2xuq + 0U, // VCVTs2fd + 0U, // VCVTs2fq + 0U, // VCVTs2hd + 0U, // VCVTs2hq + 0U, // VCVTu2fd + 0U, // VCVTu2fq + 0U, // VCVTu2hd + 0U, // VCVTu2hq + 536U, // VCVTxs2fd + 536U, // VCVTxs2fq + 536U, // VCVTxs2hd + 536U, // VCVTxs2hq + 536U, // VCVTxu2fd + 536U, // VCVTxu2fq + 536U, // VCVTxu2hd + 536U, // VCVTxu2hq + 2212622U, // VDIVD + 0U, // VDIVH + 0U, // VDIVS + 16384U, // VDUP16d + 16384U, // VDUP16q + 16384U, // VDUP32d + 16384U, // VDUP32q + 16384U, // VDUP8d + 16384U, // VDUP8q + 163840U, // VDUPLN16d + 163840U, // VDUPLN16q + 163840U, // VDUPLN32d + 163840U, // VDUPLN32q + 163840U, // VDUPLN8d + 163840U, // VDUPLN8q + 0U, // VEORd + 0U, // VEORq + 33554432U, // VEXTd16 + 33554432U, // VEXTd32 + 33554432U, // VEXTd8 + 33554432U, // VEXTq16 + 33554432U, // VEXTq32 + 33554432U, // VEXTq64 + 33554432U, // VEXTq8 + 49944U, // VFMAD + 3671552U, // VFMAH + 17920U, // VFMALD + 263680U, // VFMALDI + 17920U, // VFMALQ + 263680U, // VFMALQI + 3671552U, // VFMAS + 3671552U, // VFMAfd + 3671552U, // VFMAfq + 3671552U, // VFMAhd + 3671552U, // VFMAhq + 49944U, // VFMSD + 3671552U, // VFMSH + 17920U, // VFMSLD + 263680U, // VFMSLDI + 17920U, // VFMSLQ + 263680U, // VFMSLQI + 3671552U, // VFMSS + 3671552U, // VFMSfd + 3671552U, // VFMSfq + 3671552U, // VFMShd + 3671552U, // VFMShq + 49944U, // VFNMAD + 3671552U, // VFNMAH + 3671552U, // VFNMAS + 49944U, // VFNMSD + 3671552U, // VFNMSH + 3671552U, // VFNMSS + 17920U, // VFP_VMAXNMD + 17920U, // VFP_VMAXNMH + 17920U, // VFP_VMAXNMS + 17920U, // VFP_VMINNMD + 17920U, // VFP_VMINNMH + 17920U, // VFP_VMINNMS + 163840U, // VGETLNi32 + 163840U, // VGETLNs16 + 163840U, // VGETLNs8 + 163840U, // VGETLNu16 + 163840U, // VGETLNu8 + 0U, // VHADDsv16i8 + 0U, // VHADDsv2i32 + 0U, // VHADDsv4i16 + 0U, // VHADDsv4i32 + 0U, // VHADDsv8i16 + 0U, // VHADDsv8i8 + 0U, // VHADDuv16i8 + 0U, // VHADDuv2i32 + 0U, // VHADDuv4i16 + 0U, // VHADDuv4i32 + 0U, // VHADDuv8i16 + 0U, // VHADDuv8i8 + 0U, // VHSUBsv16i8 + 0U, // VHSUBsv2i32 + 0U, // VHSUBsv4i16 + 0U, // VHSUBsv4i32 + 0U, // VHSUBsv8i16 + 0U, // VHSUBsv8i8 + 0U, // VHSUBuv16i8 + 0U, // VHSUBuv2i32 + 0U, // VHSUBuv4i16 + 0U, // VHSUBuv4i32 + 0U, // VHSUBuv8i16 + 0U, // VHSUBuv8i8 + 2U, // VINSH + 0U, // VJCVT + 518U, // VLD1DUPd16 + 678U, // VLD1DUPd16wb_fixed + 2179878U, // VLD1DUPd16wb_register + 518U, // VLD1DUPd32 + 678U, // VLD1DUPd32wb_fixed + 2179878U, // VLD1DUPd32wb_register + 518U, // VLD1DUPd8 + 678U, // VLD1DUPd8wb_fixed + 2179878U, // VLD1DUPd8wb_register + 518U, // VLD1DUPq16 + 678U, // VLD1DUPq16wb_fixed + 2179878U, // VLD1DUPq16wb_register + 518U, // VLD1DUPq32 + 678U, // VLD1DUPq32wb_fixed + 2179878U, // VLD1DUPq32wb_register + 518U, // VLD1DUPq8 + 678U, // VLD1DUPq8wb_fixed + 2179878U, // VLD1DUPq8wb_register + 12342568U, // VLD1LNd16 + 12866984U, // VLD1LNd16_UPD + 12342568U, // VLD1LNd32 + 12866984U, // VLD1LNd32_UPD + 12342568U, // VLD1LNd8 + 12866984U, // VLD1LNd8_UPD + 0U, // VLD1LNq16Pseudo + 0U, // VLD1LNq16Pseudo_UPD + 0U, // VLD1LNq32Pseudo + 0U, // VLD1LNq32Pseudo_UPD + 0U, // VLD1LNq8Pseudo + 0U, // VLD1LNq8Pseudo_UPD + 518U, // VLD1d16 + 518U, // VLD1d16Q + 0U, // VLD1d16QPseudo + 0U, // VLD1d16QPseudoWB_fixed + 0U, // VLD1d16QPseudoWB_register + 678U, // VLD1d16Qwb_fixed + 2179878U, // VLD1d16Qwb_register + 518U, // VLD1d16T + 0U, // VLD1d16TPseudo + 0U, // VLD1d16TPseudoWB_fixed + 0U, // VLD1d16TPseudoWB_register + 678U, // VLD1d16Twb_fixed + 2179878U, // VLD1d16Twb_register + 678U, // VLD1d16wb_fixed + 2179878U, // VLD1d16wb_register + 518U, // VLD1d32 + 518U, // VLD1d32Q + 0U, // VLD1d32QPseudo + 0U, // VLD1d32QPseudoWB_fixed + 0U, // VLD1d32QPseudoWB_register + 678U, // VLD1d32Qwb_fixed + 2179878U, // VLD1d32Qwb_register + 518U, // VLD1d32T + 0U, // VLD1d32TPseudo + 0U, // VLD1d32TPseudoWB_fixed + 0U, // VLD1d32TPseudoWB_register + 678U, // VLD1d32Twb_fixed + 2179878U, // VLD1d32Twb_register + 678U, // VLD1d32wb_fixed + 2179878U, // VLD1d32wb_register + 518U, // VLD1d64 + 518U, // VLD1d64Q + 0U, // VLD1d64QPseudo + 0U, // VLD1d64QPseudoWB_fixed + 0U, // VLD1d64QPseudoWB_register + 678U, // VLD1d64Qwb_fixed + 2179878U, // VLD1d64Qwb_register + 518U, // VLD1d64T + 0U, // VLD1d64TPseudo + 0U, // VLD1d64TPseudoWB_fixed + 0U, // VLD1d64TPseudoWB_register + 678U, // VLD1d64Twb_fixed + 2179878U, // VLD1d64Twb_register + 678U, // VLD1d64wb_fixed + 2179878U, // VLD1d64wb_register + 518U, // VLD1d8 + 518U, // VLD1d8Q + 0U, // VLD1d8QPseudo + 0U, // VLD1d8QPseudoWB_fixed + 0U, // VLD1d8QPseudoWB_register + 678U, // VLD1d8Qwb_fixed + 2179878U, // VLD1d8Qwb_register + 518U, // VLD1d8T + 0U, // VLD1d8TPseudo + 0U, // VLD1d8TPseudoWB_fixed + 0U, // VLD1d8TPseudoWB_register + 678U, // VLD1d8Twb_fixed + 2179878U, // VLD1d8Twb_register + 678U, // VLD1d8wb_fixed + 2179878U, // VLD1d8wb_register + 518U, // VLD1q16 + 0U, // VLD1q16HighQPseudo + 0U, // VLD1q16HighQPseudo_UPD + 0U, // VLD1q16HighTPseudo + 0U, // VLD1q16HighTPseudo_UPD + 0U, // VLD1q16LowQPseudo_UPD + 0U, // VLD1q16LowTPseudo_UPD + 678U, // VLD1q16wb_fixed + 2179878U, // VLD1q16wb_register + 518U, // VLD1q32 + 0U, // VLD1q32HighQPseudo + 0U, // VLD1q32HighQPseudo_UPD + 0U, // VLD1q32HighTPseudo + 0U, // VLD1q32HighTPseudo_UPD + 0U, // VLD1q32LowQPseudo_UPD + 0U, // VLD1q32LowTPseudo_UPD + 678U, // VLD1q32wb_fixed + 2179878U, // VLD1q32wb_register + 518U, // VLD1q64 + 0U, // VLD1q64HighQPseudo + 0U, // VLD1q64HighQPseudo_UPD + 0U, // VLD1q64HighTPseudo + 0U, // VLD1q64HighTPseudo_UPD + 0U, // VLD1q64LowQPseudo_UPD + 0U, // VLD1q64LowTPseudo_UPD + 678U, // VLD1q64wb_fixed + 2179878U, // VLD1q64wb_register + 518U, // VLD1q8 + 0U, // VLD1q8HighQPseudo + 0U, // VLD1q8HighQPseudo_UPD + 0U, // VLD1q8HighTPseudo + 0U, // VLD1q8HighTPseudo_UPD + 0U, // VLD1q8LowQPseudo_UPD + 0U, // VLD1q8LowTPseudo_UPD + 678U, // VLD1q8wb_fixed + 2179878U, // VLD1q8wb_register + 518U, // VLD2DUPd16 + 678U, // VLD2DUPd16wb_fixed + 2179878U, // VLD2DUPd16wb_register + 518U, // VLD2DUPd16x2 + 678U, // VLD2DUPd16x2wb_fixed + 2179878U, // VLD2DUPd16x2wb_register + 518U, // VLD2DUPd32 + 678U, // VLD2DUPd32wb_fixed + 2179878U, // VLD2DUPd32wb_register + 518U, // VLD2DUPd32x2 + 678U, // VLD2DUPd32x2wb_fixed + 2179878U, // VLD2DUPd32x2wb_register + 518U, // VLD2DUPd8 + 678U, // VLD2DUPd8wb_fixed + 2179878U, // VLD2DUPd8wb_register + 518U, // VLD2DUPd8x2 + 678U, // VLD2DUPd8x2wb_fixed + 2179878U, // VLD2DUPd8x2wb_register + 0U, // VLD2DUPq16EvenPseudo + 0U, // VLD2DUPq16OddPseudo + 0U, // VLD2DUPq16OddPseudoWB_fixed + 0U, // VLD2DUPq16OddPseudoWB_register + 0U, // VLD2DUPq32EvenPseudo + 0U, // VLD2DUPq32OddPseudo + 0U, // VLD2DUPq32OddPseudoWB_fixed + 0U, // VLD2DUPq32OddPseudoWB_register + 0U, // VLD2DUPq8EvenPseudo + 0U, // VLD2DUPq8OddPseudo + 0U, // VLD2DUPq8OddPseudoWB_fixed + 0U, // VLD2DUPq8OddPseudoWB_register + 13407656U, // VLD2LNd16 + 0U, // VLD2LNd16Pseudo + 0U, // VLD2LNd16Pseudo_UPD + 13948456U, // VLD2LNd16_UPD + 13407656U, // VLD2LNd32 + 0U, // VLD2LNd32Pseudo + 0U, // VLD2LNd32Pseudo_UPD + 13948456U, // VLD2LNd32_UPD + 13407656U, // VLD2LNd8 + 0U, // VLD2LNd8Pseudo + 0U, // VLD2LNd8Pseudo_UPD + 13948456U, // VLD2LNd8_UPD + 13407656U, // VLD2LNq16 + 0U, // VLD2LNq16Pseudo + 0U, // VLD2LNq16Pseudo_UPD + 13948456U, // VLD2LNq16_UPD + 13407656U, // VLD2LNq32 + 0U, // VLD2LNq32Pseudo + 0U, // VLD2LNq32Pseudo_UPD + 13948456U, // VLD2LNq32_UPD + 518U, // VLD2b16 + 678U, // VLD2b16wb_fixed + 2179878U, // VLD2b16wb_register + 518U, // VLD2b32 + 678U, // VLD2b32wb_fixed + 2179878U, // VLD2b32wb_register + 518U, // VLD2b8 + 678U, // VLD2b8wb_fixed + 2179878U, // VLD2b8wb_register + 518U, // VLD2d16 + 678U, // VLD2d16wb_fixed + 2179878U, // VLD2d16wb_register + 518U, // VLD2d32 + 678U, // VLD2d32wb_fixed + 2179878U, // VLD2d32wb_register + 518U, // VLD2d8 + 678U, // VLD2d8wb_fixed + 2179878U, // VLD2d8wb_register + 518U, // VLD2q16 + 0U, // VLD2q16Pseudo + 0U, // VLD2q16PseudoWB_fixed + 0U, // VLD2q16PseudoWB_register + 678U, // VLD2q16wb_fixed + 2179878U, // VLD2q16wb_register + 518U, // VLD2q32 + 0U, // VLD2q32Pseudo + 0U, // VLD2q32PseudoWB_fixed + 0U, // VLD2q32PseudoWB_register + 678U, // VLD2q32wb_fixed + 2179878U, // VLD2q32wb_register + 518U, // VLD2q8 + 0U, // VLD2q8Pseudo + 0U, // VLD2q8PseudoWB_fixed + 0U, // VLD2q8PseudoWB_register + 678U, // VLD2q8wb_fixed + 2179878U, // VLD2q8wb_register + 333482U, // VLD3DUPd16 + 0U, // VLD3DUPd16Pseudo + 0U, // VLD3DUPd16Pseudo_UPD + 14505642U, // VLD3DUPd16_UPD + 333482U, // VLD3DUPd32 + 0U, // VLD3DUPd32Pseudo + 0U, // VLD3DUPd32Pseudo_UPD + 14505642U, // VLD3DUPd32_UPD + 333482U, // VLD3DUPd8 + 0U, // VLD3DUPd8Pseudo + 0U, // VLD3DUPd8Pseudo_UPD + 14505642U, // VLD3DUPd8_UPD + 333482U, // VLD3DUPq16 + 0U, // VLD3DUPq16EvenPseudo + 0U, // VLD3DUPq16OddPseudo + 0U, // VLD3DUPq16OddPseudo_UPD + 14505642U, // VLD3DUPq16_UPD + 333482U, // VLD3DUPq32 + 0U, // VLD3DUPq32EvenPseudo + 0U, // VLD3DUPq32OddPseudo + 0U, // VLD3DUPq32OddPseudo_UPD + 14505642U, // VLD3DUPq32_UPD + 333482U, // VLD3DUPq8 + 0U, // VLD3DUPq8EvenPseudo + 0U, // VLD3DUPq8OddPseudo + 0U, // VLD3DUPq8OddPseudo_UPD + 14505642U, // VLD3DUPq8_UPD + 14997032U, // VLD3LNd16 + 0U, // VLD3LNd16Pseudo + 0U, // VLD3LNd16Pseudo_UPD + 15488808U, // VLD3LNd16_UPD + 14997032U, // VLD3LNd32 + 0U, // VLD3LNd32Pseudo + 0U, // VLD3LNd32Pseudo_UPD + 15488808U, // VLD3LNd32_UPD + 14997032U, // VLD3LNd8 + 0U, // VLD3LNd8Pseudo + 0U, // VLD3LNd8Pseudo_UPD + 15488808U, // VLD3LNd8_UPD + 14997032U, // VLD3LNq16 + 0U, // VLD3LNq16Pseudo + 0U, // VLD3LNq16Pseudo_UPD + 15488808U, // VLD3LNq16_UPD + 14997032U, // VLD3LNq32 + 0U, // VLD3LNq32Pseudo + 0U, // VLD3LNq32Pseudo_UPD + 15488808U, // VLD3LNq32_UPD + 369098752U, // VLD3d16 + 0U, // VLD3d16Pseudo + 0U, // VLD3d16Pseudo_UPD + 369098752U, // VLD3d16_UPD + 369098752U, // VLD3d32 + 0U, // VLD3d32Pseudo + 0U, // VLD3d32Pseudo_UPD + 369098752U, // VLD3d32_UPD + 369098752U, // VLD3d8 + 0U, // VLD3d8Pseudo + 0U, // VLD3d8Pseudo_UPD + 369098752U, // VLD3d8_UPD + 369098752U, // VLD3q16 + 0U, // VLD3q16Pseudo_UPD + 369098752U, // VLD3q16_UPD + 0U, // VLD3q16oddPseudo + 0U, // VLD3q16oddPseudo_UPD + 369098752U, // VLD3q32 + 0U, // VLD3q32Pseudo_UPD + 369098752U, // VLD3q32_UPD + 0U, // VLD3q32oddPseudo + 0U, // VLD3q32oddPseudo_UPD + 369098752U, // VLD3q8 + 0U, // VLD3q8Pseudo_UPD + 369098752U, // VLD3q8_UPD + 0U, // VLD3q8oddPseudo + 0U, // VLD3q8oddPseudo_UPD + 2447274U, // VLD4DUPd16 + 0U, // VLD4DUPd16Pseudo + 0U, // VLD4DUPd16Pseudo_UPD + 366506U, // VLD4DUPd16_UPD + 2447274U, // VLD4DUPd32 + 0U, // VLD4DUPd32Pseudo + 0U, // VLD4DUPd32Pseudo_UPD + 366506U, // VLD4DUPd32_UPD + 2447274U, // VLD4DUPd8 + 0U, // VLD4DUPd8Pseudo + 0U, // VLD4DUPd8Pseudo_UPD + 366506U, // VLD4DUPd8_UPD + 2447274U, // VLD4DUPq16 + 0U, // VLD4DUPq16EvenPseudo + 0U, // VLD4DUPq16OddPseudo + 0U, // VLD4DUPq16OddPseudo_UPD + 366506U, // VLD4DUPq16_UPD + 2447274U, // VLD4DUPq32 + 0U, // VLD4DUPq32EvenPseudo + 0U, // VLD4DUPq32OddPseudo + 0U, // VLD4DUPq32OddPseudo_UPD + 366506U, // VLD4DUPq32_UPD + 2447274U, // VLD4DUPq8 + 0U, // VLD4DUPq8EvenPseudo + 0U, // VLD4DUPq8OddPseudo + 0U, // VLD4DUPq8OddPseudo_UPD + 366506U, // VLD4DUPq8_UPD + 406624040U, // VLD4LNd16 + 0U, // VLD4LNd16Pseudo + 0U, // VLD4LNd16Pseudo_UPD + 6184U, // VLD4LNd16_UPD + 406624040U, // VLD4LNd32 + 0U, // VLD4LNd32Pseudo + 0U, // VLD4LNd32Pseudo_UPD + 6184U, // VLD4LNd32_UPD + 406624040U, // VLD4LNd8 + 0U, // VLD4LNd8Pseudo + 0U, // VLD4LNd8Pseudo_UPD + 6184U, // VLD4LNd8_UPD + 406624040U, // VLD4LNq16 + 0U, // VLD4LNq16Pseudo + 0U, // VLD4LNq16Pseudo_UPD + 6184U, // VLD4LNq16_UPD + 406624040U, // VLD4LNq32 + 0U, // VLD4LNq32Pseudo + 0U, // VLD4LNq32Pseudo_UPD + 6184U, // VLD4LNq32_UPD + 33554432U, // VLD4d16 + 0U, // VLD4d16Pseudo + 0U, // VLD4d16Pseudo_UPD + 33554432U, // VLD4d16_UPD + 33554432U, // VLD4d32 + 0U, // VLD4d32Pseudo + 0U, // VLD4d32Pseudo_UPD + 33554432U, // VLD4d32_UPD + 33554432U, // VLD4d8 + 0U, // VLD4d8Pseudo + 0U, // VLD4d8Pseudo_UPD + 33554432U, // VLD4d8_UPD + 33554432U, // VLD4q16 + 0U, // VLD4q16Pseudo_UPD + 33554432U, // VLD4q16_UPD + 0U, // VLD4q16oddPseudo + 0U, // VLD4q16oddPseudo_UPD + 33554432U, // VLD4q32 + 0U, // VLD4q32Pseudo_UPD + 33554432U, // VLD4q32_UPD + 0U, // VLD4q32oddPseudo + 0U, // VLD4q32oddPseudo_UPD + 33554432U, // VLD4q8 + 0U, // VLD4q8Pseudo_UPD + 33554432U, // VLD4q8_UPD + 0U, // VLD4q8oddPseudo + 0U, // VLD4q8oddPseudo_UPD + 530U, // VLDMDDB_UPD + 18560U, // VLDMDIA + 530U, // VLDMDIA_UPD + 0U, // VLDMQIA + 530U, // VLDMSDB_UPD + 18560U, // VLDMSIA + 530U, // VLDMSIA_UPD + 6272U, // VLDRD + 6400U, // VLDRH + 6272U, // VLDRS + 0U, // VLDR_FPCXTNS_off + 44U, // VLDR_FPCXTNS_post + 0U, // VLDR_FPCXTNS_pre + 0U, // VLDR_FPCXTS_off + 44U, // VLDR_FPCXTS_post + 0U, // VLDR_FPCXTS_pre + 0U, // VLDR_FPSCR_NZCVQC_off + 44U, // VLDR_FPSCR_NZCVQC_post + 0U, // VLDR_FPSCR_NZCVQC_pre + 0U, // VLDR_FPSCR_off + 44U, // VLDR_FPSCR_post + 0U, // VLDR_FPSCR_pre + 0U, // VLDR_P0_off + 46U, // VLDR_P0_post + 0U, // VLDR_P0_pre + 0U, // VLDR_VPR_off + 44U, // VLDR_VPR_post + 0U, // VLDR_VPR_pre + 2U, // VLLDM + 2U, // VLSTM + 0U, // VMAXfd + 0U, // VMAXfq + 0U, // VMAXhd + 0U, // VMAXhq + 0U, // VMAXsv16i8 + 0U, // VMAXsv2i32 + 0U, // VMAXsv4i16 + 0U, // VMAXsv4i32 + 0U, // VMAXsv8i16 + 0U, // VMAXsv8i8 + 0U, // VMAXuv16i8 + 0U, // VMAXuv2i32 + 0U, // VMAXuv4i16 + 0U, // VMAXuv4i32 + 0U, // VMAXuv8i16 + 0U, // VMAXuv8i8 + 0U, // VMINfd + 0U, // VMINfq + 0U, // VMINhd + 0U, // VMINhq + 0U, // VMINsv16i8 + 0U, // VMINsv2i32 + 0U, // VMINsv4i16 + 0U, // VMINsv4i32 + 0U, // VMINsv8i16 + 0U, // VMINsv8i8 + 0U, // VMINuv16i8 + 0U, // VMINuv2i32 + 0U, // VMINuv4i16 + 0U, // VMINuv4i32 + 0U, // VMINuv8i16 + 0U, // VMINuv8i8 + 49944U, // VMLAD + 3671552U, // VMLAH + 439879168U, // VMLALslsv2i32 + 439879168U, // VMLALslsv4i16 + 439879168U, // VMLALsluv2i32 + 439879168U, // VMLALsluv4i16 + 3671552U, // VMLALsv2i64 + 3671552U, // VMLALsv4i32 + 3671552U, // VMLALsv8i16 + 3671552U, // VMLALuv2i64 + 3671552U, // VMLALuv4i32 + 3671552U, // VMLALuv8i16 + 3671552U, // VMLAS + 3671552U, // VMLAfd + 3671552U, // VMLAfq + 3671552U, // VMLAhd + 3671552U, // VMLAhq + 439879168U, // VMLAslfd + 439879168U, // VMLAslfq + 439879168U, // VMLAslhd + 439879168U, // VMLAslhq + 439879168U, // VMLAslv2i32 + 439879168U, // VMLAslv4i16 + 439879168U, // VMLAslv4i32 + 439879168U, // VMLAslv8i16 + 3671552U, // VMLAv16i8 + 3671552U, // VMLAv2i32 + 3671552U, // VMLAv4i16 + 3671552U, // VMLAv4i32 + 3671552U, // VMLAv8i16 + 3671552U, // VMLAv8i8 + 49944U, // VMLSD + 3671552U, // VMLSH + 439879168U, // VMLSLslsv2i32 + 439879168U, // VMLSLslsv4i16 + 439879168U, // VMLSLsluv2i32 + 439879168U, // VMLSLsluv4i16 + 3671552U, // VMLSLsv2i64 + 3671552U, // VMLSLsv4i32 + 3671552U, // VMLSLsv8i16 + 3671552U, // VMLSLuv2i64 + 3671552U, // VMLSLuv4i32 + 3671552U, // VMLSLuv8i16 + 3671552U, // VMLSS + 3671552U, // VMLSfd + 3671552U, // VMLSfq + 3671552U, // VMLShd + 3671552U, // VMLShq + 439879168U, // VMLSslfd + 439879168U, // VMLSslfq + 439879168U, // VMLSslhd + 439879168U, // VMLSslhq + 439879168U, // VMLSslv2i32 + 439879168U, // VMLSslv4i16 + 439879168U, // VMLSslv4i32 + 439879168U, // VMLSslv8i16 + 3671552U, // VMLSv16i8 + 3671552U, // VMLSv2i32 + 3671552U, // VMLSv4i16 + 3671552U, // VMLSv4i32 + 3671552U, // VMLSv8i16 + 3671552U, // VMLSv8i8 + 16768U, // VMMLA + 526U, // VMOVD + 0U, // VMOVDRR + 2U, // VMOVH + 16384U, // VMOVHR + 16384U, // VMOVLsv2i64 + 16384U, // VMOVLsv4i32 + 16384U, // VMOVLsv8i16 + 16384U, // VMOVLuv2i64 + 16384U, // VMOVLuv4i32 + 16384U, // VMOVLuv8i16 + 2U, // VMOVNv2i32 + 16384U, // VMOVNv4i16 + 16384U, // VMOVNv8i8 + 16384U, // VMOVRH + 0U, // VMOVRRD + 33554432U, // VMOVRRS + 16384U, // VMOVRS + 16384U, // VMOVS + 16384U, // VMOVSR + 33554432U, // VMOVSRR + 4864U, // VMOVv16i8 + 0U, // VMOVv1i64 + 2048U, // VMOVv2f32 + 4864U, // VMOVv2i32 + 0U, // VMOVv2i64 + 2048U, // VMOVv4f32 + 4864U, // VMOVv4i16 + 4864U, // VMOVv4i32 + 4864U, // VMOVv8i16 + 4864U, // VMOVv8i8 + 48U, // VMRS + 50U, // VMRS_FPCXTNS + 52U, // VMRS_FPCXTS + 54U, // VMRS_FPEXC + 56U, // VMRS_FPINST + 58U, // VMRS_FPINST2 + 60U, // VMRS_FPSCR_NZCVQC + 62U, // VMRS_FPSID + 64U, // VMRS_MVFR0 + 66U, // VMRS_MVFR1 + 68U, // VMRS_MVFR2 + 70U, // VMRS_P0 + 72U, // VMRS_VPR + 2U, // VMSR + 2U, // VMSR_FPCXTNS + 2U, // VMSR_FPCXTS + 0U, // VMSR_FPEXC + 0U, // VMSR_FPINST + 0U, // VMSR_FPINST2 + 2U, // VMSR_FPSCR_NZCVQC + 0U, // VMSR_FPSID + 2U, // VMSR_P0 + 2U, // VMSR_VPR + 2212622U, // VMULD + 0U, // VMULH + 17920U, // VMULLp64 + 0U, // VMULLp8 + 167772160U, // VMULLslsv2i32 + 167772160U, // VMULLslsv4i16 + 167772160U, // VMULLsluv2i32 + 167772160U, // VMULLsluv4i16 + 0U, // VMULLsv2i64 + 0U, // VMULLsv4i32 + 0U, // VMULLsv8i16 + 0U, // VMULLuv2i64 + 0U, // VMULLuv4i32 + 0U, // VMULLuv8i16 + 0U, // VMULS + 0U, // VMULfd + 0U, // VMULfq + 0U, // VMULhd + 0U, // VMULhq + 0U, // VMULpd + 0U, // VMULpq + 167772160U, // VMULslfd + 167772160U, // VMULslfq + 167772160U, // VMULslhd + 167772160U, // VMULslhq + 167772160U, // VMULslv2i32 + 167772160U, // VMULslv4i16 + 167772160U, // VMULslv4i32 + 167772160U, // VMULslv8i16 + 0U, // VMULv16i8 + 0U, // VMULv2i32 + 0U, // VMULv4i16 + 0U, // VMULv4i32 + 0U, // VMULv8i16 + 0U, // VMULv8i8 + 16384U, // VMVNd + 16384U, // VMVNq + 4864U, // VMVNv2i32 + 4864U, // VMVNv4i16 + 4864U, // VMVNv4i32 + 4864U, // VMVNv8i16 + 526U, // VNEGD + 16384U, // VNEGH + 16384U, // VNEGS + 16384U, // VNEGf32q + 16384U, // VNEGfd + 16384U, // VNEGhd + 16384U, // VNEGhq + 16384U, // VNEGs16d + 16384U, // VNEGs16q + 16384U, // VNEGs32d + 16384U, // VNEGs32q + 16384U, // VNEGs8d + 16384U, // VNEGs8q + 49944U, // VNMLAD + 3671552U, // VNMLAH + 3671552U, // VNMLAS + 49944U, // VNMLSD + 3671552U, // VNMLSH + 3671552U, // VNMLSS + 2212622U, // VNMULD + 0U, // VNMULH + 0U, // VNMULS + 0U, // VORNd + 0U, // VORNq + 0U, // VORRd + 4864U, // VORRiv2i32 + 4864U, // VORRiv4i16 + 4864U, // VORRiv4i32 + 4864U, // VORRiv8i16 + 0U, // VORRq + 17920U, // VPADALsv16i8 + 17920U, // VPADALsv2i32 + 17920U, // VPADALsv4i16 + 17920U, // VPADALsv4i32 + 17920U, // VPADALsv8i16 + 17920U, // VPADALsv8i8 + 17920U, // VPADALuv16i8 + 17920U, // VPADALuv2i32 + 17920U, // VPADALuv4i16 + 17920U, // VPADALuv4i32 + 17920U, // VPADALuv8i16 + 17920U, // VPADALuv8i8 + 16384U, // VPADDLsv16i8 + 16384U, // VPADDLsv2i32 + 16384U, // VPADDLsv4i16 + 16384U, // VPADDLsv4i32 + 16384U, // VPADDLsv8i16 + 16384U, // VPADDLsv8i8 + 16384U, // VPADDLuv16i8 + 16384U, // VPADDLuv2i32 + 16384U, // VPADDLuv4i16 + 16384U, // VPADDLuv4i32 + 16384U, // VPADDLuv8i16 + 16384U, // VPADDLuv8i8 + 0U, // VPADDf + 0U, // VPADDh + 0U, // VPADDi16 + 0U, // VPADDi32 + 0U, // VPADDi8 + 0U, // VPMAXf + 0U, // VPMAXh + 0U, // VPMAXs16 + 0U, // VPMAXs32 + 0U, // VPMAXs8 + 0U, // VPMAXu16 + 0U, // VPMAXu32 + 0U, // VPMAXu8 + 0U, // VPMINf + 0U, // VPMINh + 0U, // VPMINs16 + 0U, // VPMINs32 + 0U, // VPMINs8 + 0U, // VPMINu16 + 0U, // VPMINu32 + 0U, // VPMINu8 + 16384U, // VQABSv16i8 + 16384U, // VQABSv2i32 + 16384U, // VQABSv4i16 + 16384U, // VQABSv4i32 + 16384U, // VQABSv8i16 + 16384U, // VQABSv8i8 + 0U, // VQADDsv16i8 + 17920U, // VQADDsv1i64 + 0U, // VQADDsv2i32 + 17920U, // VQADDsv2i64 + 0U, // VQADDsv4i16 + 0U, // VQADDsv4i32 + 0U, // VQADDsv8i16 + 0U, // VQADDsv8i8 + 0U, // VQADDuv16i8 + 0U, // VQADDuv1i64 + 0U, // VQADDuv2i32 + 0U, // VQADDuv2i64 + 0U, // VQADDuv4i16 + 0U, // VQADDuv4i32 + 0U, // VQADDuv8i16 + 0U, // VQADDuv8i8 + 439879168U, // VQDMLALslv2i32 + 439879168U, // VQDMLALslv4i16 + 3671552U, // VQDMLALv2i64 + 3671552U, // VQDMLALv4i32 + 439879168U, // VQDMLSLslv2i32 + 439879168U, // VQDMLSLslv4i16 + 3671552U, // VQDMLSLv2i64 + 3671552U, // VQDMLSLv4i32 + 167772160U, // VQDMULHslv2i32 + 167772160U, // VQDMULHslv4i16 + 167772160U, // VQDMULHslv4i32 + 167772160U, // VQDMULHslv8i16 + 0U, // VQDMULHv2i32 + 0U, // VQDMULHv4i16 + 0U, // VQDMULHv4i32 + 0U, // VQDMULHv8i16 + 167772160U, // VQDMULLslv2i32 + 167772160U, // VQDMULLslv4i16 + 0U, // VQDMULLv2i64 + 0U, // VQDMULLv4i32 + 2U, // VQMOVNsuv2i32 + 16384U, // VQMOVNsuv4i16 + 16384U, // VQMOVNsuv8i8 + 2U, // VQMOVNsv2i32 + 16384U, // VQMOVNsv4i16 + 16384U, // VQMOVNsv8i8 + 16384U, // VQMOVNuv2i32 + 16384U, // VQMOVNuv4i16 + 16384U, // VQMOVNuv8i8 + 16384U, // VQNEGv16i8 + 16384U, // VQNEGv2i32 + 16384U, // VQNEGv4i16 + 16384U, // VQNEGv4i32 + 16384U, // VQNEGv8i16 + 16384U, // VQNEGv8i8 + 439879168U, // VQRDMLAHslv2i32 + 439879168U, // VQRDMLAHslv4i16 + 439879168U, // VQRDMLAHslv4i32 + 439879168U, // VQRDMLAHslv8i16 + 3671552U, // VQRDMLAHv2i32 + 3671552U, // VQRDMLAHv4i16 + 3671552U, // VQRDMLAHv4i32 + 3671552U, // VQRDMLAHv8i16 + 439879168U, // VQRDMLSHslv2i32 + 439879168U, // VQRDMLSHslv4i16 + 439879168U, // VQRDMLSHslv4i32 + 439879168U, // VQRDMLSHslv8i16 + 3671552U, // VQRDMLSHv2i32 + 3671552U, // VQRDMLSHv4i16 + 3671552U, // VQRDMLSHv4i32 + 3671552U, // VQRDMLSHv8i16 + 167772160U, // VQRDMULHslv2i32 + 167772160U, // VQRDMULHslv4i16 + 167772160U, // VQRDMULHslv4i32 + 167772160U, // VQRDMULHslv8i16 + 0U, // VQRDMULHv2i32 + 0U, // VQRDMULHv4i16 + 0U, // VQRDMULHv4i32 + 0U, // VQRDMULHv8i16 + 0U, // VQRSHLsv16i8 + 17920U, // VQRSHLsv1i64 + 0U, // VQRSHLsv2i32 + 17920U, // VQRSHLsv2i64 + 0U, // VQRSHLsv4i16 + 0U, // VQRSHLsv4i32 + 0U, // VQRSHLsv8i16 + 0U, // VQRSHLsv8i8 + 0U, // VQRSHLuv16i8 + 0U, // VQRSHLuv1i64 + 0U, // VQRSHLuv2i32 + 0U, // VQRSHLuv2i64 + 0U, // VQRSHLuv4i16 + 0U, // VQRSHLuv4i32 + 0U, // VQRSHLuv8i16 + 0U, // VQRSHLuv8i8 + 17920U, // VQRSHRNsv2i32 + 0U, // VQRSHRNsv4i16 + 0U, // VQRSHRNsv8i8 + 0U, // VQRSHRNuv2i32 + 0U, // VQRSHRNuv4i16 + 0U, // VQRSHRNuv8i8 + 17920U, // VQRSHRUNv2i32 + 0U, // VQRSHRUNv4i16 + 0U, // VQRSHRUNv8i8 + 0U, // VQSHLsiv16i8 + 17920U, // VQSHLsiv1i64 + 0U, // VQSHLsiv2i32 + 17920U, // VQSHLsiv2i64 + 0U, // VQSHLsiv4i16 + 0U, // VQSHLsiv4i32 + 0U, // VQSHLsiv8i16 + 0U, // VQSHLsiv8i8 + 0U, // VQSHLsuv16i8 + 17920U, // VQSHLsuv1i64 + 0U, // VQSHLsuv2i32 + 17920U, // VQSHLsuv2i64 + 0U, // VQSHLsuv4i16 + 0U, // VQSHLsuv4i32 + 0U, // VQSHLsuv8i16 + 0U, // VQSHLsuv8i8 + 0U, // VQSHLsv16i8 + 17920U, // VQSHLsv1i64 + 0U, // VQSHLsv2i32 + 17920U, // VQSHLsv2i64 + 0U, // VQSHLsv4i16 + 0U, // VQSHLsv4i32 + 0U, // VQSHLsv8i16 + 0U, // VQSHLsv8i8 + 0U, // VQSHLuiv16i8 + 0U, // VQSHLuiv1i64 + 0U, // VQSHLuiv2i32 + 0U, // VQSHLuiv2i64 + 0U, // VQSHLuiv4i16 + 0U, // VQSHLuiv4i32 + 0U, // VQSHLuiv8i16 + 0U, // VQSHLuiv8i8 + 0U, // VQSHLuv16i8 + 0U, // VQSHLuv1i64 + 0U, // VQSHLuv2i32 + 0U, // VQSHLuv2i64 + 0U, // VQSHLuv4i16 + 0U, // VQSHLuv4i32 + 0U, // VQSHLuv8i16 + 0U, // VQSHLuv8i8 + 17920U, // VQSHRNsv2i32 + 0U, // VQSHRNsv4i16 + 0U, // VQSHRNsv8i8 + 0U, // VQSHRNuv2i32 + 0U, // VQSHRNuv4i16 + 0U, // VQSHRNuv8i8 + 17920U, // VQSHRUNv2i32 + 0U, // VQSHRUNv4i16 + 0U, // VQSHRUNv8i8 + 0U, // VQSUBsv16i8 + 17920U, // VQSUBsv1i64 + 0U, // VQSUBsv2i32 + 17920U, // VQSUBsv2i64 + 0U, // VQSUBsv4i16 + 0U, // VQSUBsv4i32 + 0U, // VQSUBsv8i16 + 0U, // VQSUBsv8i8 + 0U, // VQSUBuv16i8 + 0U, // VQSUBuv1i64 + 0U, // VQSUBuv2i32 + 0U, // VQSUBuv2i64 + 0U, // VQSUBuv4i16 + 0U, // VQSUBuv4i32 + 0U, // VQSUBuv8i16 + 0U, // VQSUBuv8i8 + 17920U, // VRADDHNv2i32 + 0U, // VRADDHNv4i16 + 0U, // VRADDHNv8i8 + 16384U, // VRECPEd + 16384U, // VRECPEfd + 16384U, // VRECPEfq + 16384U, // VRECPEhd + 16384U, // VRECPEhq + 16384U, // VRECPEq + 0U, // VRECPSfd + 0U, // VRECPSfq + 0U, // VRECPShd + 0U, // VRECPShq + 16384U, // VREV16d8 + 16384U, // VREV16q8 + 16384U, // VREV32d16 + 16384U, // VREV32d8 + 16384U, // VREV32q16 + 16384U, // VREV32q8 + 16384U, // VREV64d16 + 16384U, // VREV64d32 + 16384U, // VREV64d8 + 16384U, // VREV64q16 + 16384U, // VREV64q32 + 16384U, // VREV64q8 + 0U, // VRHADDsv16i8 + 0U, // VRHADDsv2i32 + 0U, // VRHADDsv4i16 + 0U, // VRHADDsv4i32 + 0U, // VRHADDsv8i16 + 0U, // VRHADDsv8i8 + 0U, // VRHADDuv16i8 + 0U, // VRHADDuv2i32 + 0U, // VRHADDuv4i16 + 0U, // VRHADDuv4i32 + 0U, // VRHADDuv8i16 + 0U, // VRHADDuv8i8 + 2U, // VRINTAD + 2U, // VRINTAH + 2U, // VRINTANDf + 2U, // VRINTANDh + 2U, // VRINTANQf + 2U, // VRINTANQh + 2U, // VRINTAS + 2U, // VRINTMD + 2U, // VRINTMH + 2U, // VRINTMNDf + 2U, // VRINTMNDh + 2U, // VRINTMNQf + 2U, // VRINTMNQh + 2U, // VRINTMS + 2U, // VRINTND + 2U, // VRINTNH + 2U, // VRINTNNDf + 2U, // VRINTNNDh + 2U, // VRINTNNQf + 2U, // VRINTNNQh + 2U, // VRINTNS + 2U, // VRINTPD + 2U, // VRINTPH + 2U, // VRINTPNDf + 2U, // VRINTPNDh + 2U, // VRINTPNQf + 2U, // VRINTPNQh + 2U, // VRINTPS + 526U, // VRINTRD + 16384U, // VRINTRH + 16384U, // VRINTRS + 526U, // VRINTXD + 16384U, // VRINTXH + 2U, // VRINTXNDf + 2U, // VRINTXNDh + 2U, // VRINTXNQf + 2U, // VRINTXNQh + 16384U, // VRINTXS + 526U, // VRINTZD + 16384U, // VRINTZH + 2U, // VRINTZNDf + 2U, // VRINTZNDh + 2U, // VRINTZNQf + 2U, // VRINTZNQh + 16384U, // VRINTZS + 0U, // VRSHLsv16i8 + 17920U, // VRSHLsv1i64 + 0U, // VRSHLsv2i32 + 17920U, // VRSHLsv2i64 + 0U, // VRSHLsv4i16 + 0U, // VRSHLsv4i32 + 0U, // VRSHLsv8i16 + 0U, // VRSHLsv8i8 + 0U, // VRSHLuv16i8 + 0U, // VRSHLuv1i64 + 0U, // VRSHLuv2i32 + 0U, // VRSHLuv2i64 + 0U, // VRSHLuv4i16 + 0U, // VRSHLuv4i32 + 0U, // VRSHLuv8i16 + 0U, // VRSHLuv8i8 + 17920U, // VRSHRNv2i32 + 0U, // VRSHRNv4i16 + 0U, // VRSHRNv8i8 + 0U, // VRSHRsv16i8 + 17920U, // VRSHRsv1i64 + 0U, // VRSHRsv2i32 + 17920U, // VRSHRsv2i64 + 0U, // VRSHRsv4i16 + 0U, // VRSHRsv4i32 + 0U, // VRSHRsv8i16 + 0U, // VRSHRsv8i8 + 0U, // VRSHRuv16i8 + 0U, // VRSHRuv1i64 + 0U, // VRSHRuv2i32 + 0U, // VRSHRuv2i64 + 0U, // VRSHRuv4i16 + 0U, // VRSHRuv4i32 + 0U, // VRSHRuv8i16 + 0U, // VRSHRuv8i8 + 16384U, // VRSQRTEd + 16384U, // VRSQRTEfd + 16384U, // VRSQRTEfq + 16384U, // VRSQRTEhd + 16384U, // VRSQRTEhq + 16384U, // VRSQRTEq + 0U, // VRSQRTSfd + 0U, // VRSQRTSfq + 0U, // VRSQRTShd + 0U, // VRSQRTShq + 3671552U, // VRSRAsv16i8 + 16768U, // VRSRAsv1i64 + 3671552U, // VRSRAsv2i32 + 16768U, // VRSRAsv2i64 + 3671552U, // VRSRAsv4i16 + 3671552U, // VRSRAsv4i32 + 3671552U, // VRSRAsv8i16 + 3671552U, // VRSRAsv8i8 + 3671552U, // VRSRAuv16i8 + 3671552U, // VRSRAuv1i64 + 3671552U, // VRSRAuv2i32 + 3671552U, // VRSRAuv2i64 + 3671552U, // VRSRAuv4i16 + 3671552U, // VRSRAuv4i32 + 3671552U, // VRSRAuv8i16 + 3671552U, // VRSRAuv8i8 + 17920U, // VRSUBHNv2i32 + 0U, // VRSUBHNv4i16 + 0U, // VRSUBHNv8i8 + 0U, // VSCCLRMD + 0U, // VSCCLRMS + 16768U, // VSDOTD + 2163072U, // VSDOTDI + 16768U, // VSDOTQ + 2163072U, // VSDOTQI + 17920U, // VSELEQD + 17920U, // VSELEQH + 17920U, // VSELEQS + 17920U, // VSELGED + 17920U, // VSELGEH + 17920U, // VSELGES + 17920U, // VSELGTD + 17920U, // VSELGTH + 17920U, // VSELGTS + 17920U, // VSELVSD + 17920U, // VSELVSH + 17920U, // VSELVSS + 34U, // VSETLNi16 + 34U, // VSETLNi32 + 34U, // VSETLNi8 + 0U, // VSHLLi16 + 0U, // VSHLLi32 + 0U, // VSHLLi8 + 0U, // VSHLLsv2i64 + 0U, // VSHLLsv4i32 + 0U, // VSHLLsv8i16 + 0U, // VSHLLuv2i64 + 0U, // VSHLLuv4i32 + 0U, // VSHLLuv8i16 + 0U, // VSHLiv16i8 + 17920U, // VSHLiv1i64 + 0U, // VSHLiv2i32 + 17920U, // VSHLiv2i64 + 0U, // VSHLiv4i16 + 0U, // VSHLiv4i32 + 0U, // VSHLiv8i16 + 0U, // VSHLiv8i8 + 0U, // VSHLsv16i8 + 17920U, // VSHLsv1i64 + 0U, // VSHLsv2i32 + 17920U, // VSHLsv2i64 + 0U, // VSHLsv4i16 + 0U, // VSHLsv4i32 + 0U, // VSHLsv8i16 + 0U, // VSHLsv8i8 + 0U, // VSHLuv16i8 + 0U, // VSHLuv1i64 + 0U, // VSHLuv2i32 + 0U, // VSHLuv2i64 + 0U, // VSHLuv4i16 + 0U, // VSHLuv4i32 + 0U, // VSHLuv8i16 + 0U, // VSHLuv8i8 + 17920U, // VSHRNv2i32 + 0U, // VSHRNv4i16 + 0U, // VSHRNv8i8 + 0U, // VSHRsv16i8 + 17920U, // VSHRsv1i64 + 0U, // VSHRsv2i32 + 17920U, // VSHRsv2i64 + 0U, // VSHRsv4i16 + 0U, // VSHRsv4i32 + 0U, // VSHRsv8i16 + 0U, // VSHRsv8i8 + 0U, // VSHRuv16i8 + 0U, // VSHRuv1i64 + 0U, // VSHRuv2i32 + 0U, // VSHRuv2i64 + 0U, // VSHRuv4i16 + 0U, // VSHRuv4i32 + 0U, // VSHRuv8i16 + 0U, // VSHRuv8i8 + 0U, // VSHTOD + 74U, // VSHTOH + 0U, // VSHTOS + 0U, // VSITOD + 0U, // VSITOH + 0U, // VSITOS + 3671552U, // VSLIv16i8 + 3671552U, // VSLIv1i64 + 3671552U, // VSLIv2i32 + 3671552U, // VSLIv2i64 + 3671552U, // VSLIv4i16 + 3671552U, // VSLIv4i32 + 3671552U, // VSLIv8i16 + 3671552U, // VSLIv8i8 + 76U, // VSLTOD + 76U, // VSLTOH + 76U, // VSLTOS + 16768U, // VSMMLA + 526U, // VSQRTD + 16384U, // VSQRTH + 16384U, // VSQRTS + 3671552U, // VSRAsv16i8 + 16768U, // VSRAsv1i64 + 3671552U, // VSRAsv2i32 + 16768U, // VSRAsv2i64 + 3671552U, // VSRAsv4i16 + 3671552U, // VSRAsv4i32 + 3671552U, // VSRAsv8i16 + 3671552U, // VSRAsv8i8 + 3671552U, // VSRAuv16i8 + 3671552U, // VSRAuv1i64 + 3671552U, // VSRAuv2i32 + 3671552U, // VSRAuv2i64 + 3671552U, // VSRAuv4i16 + 3671552U, // VSRAuv4i32 + 3671552U, // VSRAuv8i16 + 3671552U, // VSRAuv8i8 + 3671552U, // VSRIv16i8 + 3671552U, // VSRIv1i64 + 3671552U, // VSRIv2i32 + 3671552U, // VSRIv2i64 + 3671552U, // VSRIv4i16 + 3671552U, // VSRIv4i32 + 3671552U, // VSRIv8i16 + 3671552U, // VSRIv8i8 + 6568U, // VST1LNd16 + 482105896U, // VST1LNd16_UPD + 6568U, // VST1LNd32 + 482105896U, // VST1LNd32_UPD + 6568U, // VST1LNd8 + 482105896U, // VST1LNd8_UPD + 0U, // VST1LNq16Pseudo + 0U, // VST1LNq16Pseudo_UPD + 0U, // VST1LNq32Pseudo + 0U, // VST1LNq32Pseudo_UPD + 0U, // VST1LNq8Pseudo + 0U, // VST1LNq8Pseudo_UPD + 0U, // VST1d16 + 0U, // VST1d16Q + 0U, // VST1d16QPseudo + 0U, // VST1d16QPseudoWB_fixed + 0U, // VST1d16QPseudoWB_register + 0U, // VST1d16Qwb_fixed + 0U, // VST1d16Qwb_register + 0U, // VST1d16T + 0U, // VST1d16TPseudo + 0U, // VST1d16TPseudoWB_fixed + 0U, // VST1d16TPseudoWB_register + 0U, // VST1d16Twb_fixed + 0U, // VST1d16Twb_register + 0U, // VST1d16wb_fixed + 0U, // VST1d16wb_register + 0U, // VST1d32 + 0U, // VST1d32Q + 0U, // VST1d32QPseudo + 0U, // VST1d32QPseudoWB_fixed + 0U, // VST1d32QPseudoWB_register + 0U, // VST1d32Qwb_fixed + 0U, // VST1d32Qwb_register + 0U, // VST1d32T + 0U, // VST1d32TPseudo + 0U, // VST1d32TPseudoWB_fixed + 0U, // VST1d32TPseudoWB_register + 0U, // VST1d32Twb_fixed + 0U, // VST1d32Twb_register + 0U, // VST1d32wb_fixed + 0U, // VST1d32wb_register + 0U, // VST1d64 + 0U, // VST1d64Q + 0U, // VST1d64QPseudo + 0U, // VST1d64QPseudoWB_fixed + 0U, // VST1d64QPseudoWB_register + 0U, // VST1d64Qwb_fixed + 0U, // VST1d64Qwb_register + 0U, // VST1d64T + 0U, // VST1d64TPseudo + 0U, // VST1d64TPseudoWB_fixed + 0U, // VST1d64TPseudoWB_register + 0U, // VST1d64Twb_fixed + 0U, // VST1d64Twb_register + 0U, // VST1d64wb_fixed + 0U, // VST1d64wb_register + 0U, // VST1d8 + 0U, // VST1d8Q + 0U, // VST1d8QPseudo + 0U, // VST1d8QPseudoWB_fixed + 0U, // VST1d8QPseudoWB_register + 0U, // VST1d8Qwb_fixed + 0U, // VST1d8Qwb_register + 0U, // VST1d8T + 0U, // VST1d8TPseudo + 0U, // VST1d8TPseudoWB_fixed + 0U, // VST1d8TPseudoWB_register + 0U, // VST1d8Twb_fixed + 0U, // VST1d8Twb_register + 0U, // VST1d8wb_fixed + 0U, // VST1d8wb_register + 0U, // VST1q16 + 0U, // VST1q16HighQPseudo + 0U, // VST1q16HighQPseudo_UPD + 0U, // VST1q16HighTPseudo + 0U, // VST1q16HighTPseudo_UPD + 0U, // VST1q16LowQPseudo_UPD + 0U, // VST1q16LowTPseudo_UPD + 0U, // VST1q16wb_fixed + 0U, // VST1q16wb_register + 0U, // VST1q32 + 0U, // VST1q32HighQPseudo + 0U, // VST1q32HighQPseudo_UPD + 0U, // VST1q32HighTPseudo + 0U, // VST1q32HighTPseudo_UPD + 0U, // VST1q32LowQPseudo_UPD + 0U, // VST1q32LowTPseudo_UPD + 0U, // VST1q32wb_fixed + 0U, // VST1q32wb_register + 0U, // VST1q64 + 0U, // VST1q64HighQPseudo + 0U, // VST1q64HighQPseudo_UPD + 0U, // VST1q64HighTPseudo + 0U, // VST1q64HighTPseudo_UPD + 0U, // VST1q64LowQPseudo_UPD + 0U, // VST1q64LowTPseudo_UPD + 0U, // VST1q64wb_fixed + 0U, // VST1q64wb_register + 0U, // VST1q8 + 0U, // VST1q8HighQPseudo + 0U, // VST1q8HighQPseudo_UPD + 0U, // VST1q8HighTPseudo + 0U, // VST1q8HighTPseudo_UPD + 0U, // VST1q8LowQPseudo_UPD + 0U, // VST1q8LowTPseudo_UPD + 0U, // VST1q8wb_fixed + 0U, // VST1q8wb_register + 406623528U, // VST2LNd16 + 0U, // VST2LNd16Pseudo + 0U, // VST2LNd16Pseudo_UPD + 407147944U, // VST2LNd16_UPD + 406623528U, // VST2LNd32 + 0U, // VST2LNd32Pseudo + 0U, // VST2LNd32Pseudo_UPD + 407147944U, // VST2LNd32_UPD + 406623528U, // VST2LNd8 + 0U, // VST2LNd8Pseudo + 0U, // VST2LNd8Pseudo_UPD + 407147944U, // VST2LNd8_UPD + 406623528U, // VST2LNq16 + 0U, // VST2LNq16Pseudo + 0U, // VST2LNq16Pseudo_UPD + 407147944U, // VST2LNq16_UPD + 406623528U, // VST2LNq32 + 0U, // VST2LNq32Pseudo + 0U, // VST2LNq32Pseudo_UPD + 407147944U, // VST2LNq32_UPD + 0U, // VST2b16 + 0U, // VST2b16wb_fixed + 0U, // VST2b16wb_register + 0U, // VST2b32 + 0U, // VST2b32wb_fixed + 0U, // VST2b32wb_register + 0U, // VST2b8 + 0U, // VST2b8wb_fixed + 0U, // VST2b8wb_register + 0U, // VST2d16 + 0U, // VST2d16wb_fixed + 0U, // VST2d16wb_register + 0U, // VST2d32 + 0U, // VST2d32wb_fixed + 0U, // VST2d32wb_register + 0U, // VST2d8 + 0U, // VST2d8wb_fixed + 0U, // VST2d8wb_register + 0U, // VST2q16 + 0U, // VST2q16Pseudo + 0U, // VST2q16PseudoWB_fixed + 0U, // VST2q16PseudoWB_register + 0U, // VST2q16wb_fixed + 0U, // VST2q16wb_register + 0U, // VST2q32 + 0U, // VST2q32Pseudo + 0U, // VST2q32PseudoWB_fixed + 0U, // VST2q32PseudoWB_register + 0U, // VST2q32wb_fixed + 0U, // VST2q32wb_register + 0U, // VST2q8 + 0U, // VST2q8Pseudo + 0U, // VST2q8PseudoWB_fixed + 0U, // VST2q8PseudoWB_register + 0U, // VST2q8wb_fixed + 0U, // VST2q8wb_register + 406624808U, // VST3LNd16 + 0U, // VST3LNd16Pseudo + 0U, // VST3LNd16Pseudo_UPD + 6824U, // VST3LNd16_UPD + 406624808U, // VST3LNd32 + 0U, // VST3LNd32Pseudo + 0U, // VST3LNd32Pseudo_UPD + 6824U, // VST3LNd32_UPD + 406624808U, // VST3LNd8 + 0U, // VST3LNd8Pseudo + 0U, // VST3LNd8Pseudo_UPD + 6824U, // VST3LNd8_UPD + 406624808U, // VST3LNq16 + 0U, // VST3LNq16Pseudo + 0U, // VST3LNq16Pseudo_UPD + 6824U, // VST3LNq16_UPD + 406624808U, // VST3LNq32 + 0U, // VST3LNq32Pseudo + 0U, // VST3LNq32Pseudo_UPD + 6824U, // VST3LNq32_UPD + 369623424U, // VST3d16 + 0U, // VST3d16Pseudo + 0U, // VST3d16Pseudo_UPD + 383744U, // VST3d16_UPD + 369623424U, // VST3d32 + 0U, // VST3d32Pseudo + 0U, // VST3d32Pseudo_UPD + 383744U, // VST3d32_UPD + 369623424U, // VST3d8 + 0U, // VST3d8Pseudo + 0U, // VST3d8Pseudo_UPD + 383744U, // VST3d8_UPD + 369623424U, // VST3q16 + 0U, // VST3q16Pseudo_UPD + 383744U, // VST3q16_UPD + 0U, // VST3q16oddPseudo + 0U, // VST3q16oddPseudo_UPD + 369623424U, // VST3q32 + 0U, // VST3q32Pseudo_UPD + 383744U, // VST3q32_UPD + 0U, // VST3q32oddPseudo + 0U, // VST3q32oddPseudo_UPD + 369623424U, // VST3q8 + 0U, // VST3q8Pseudo_UPD + 383744U, // VST3q8_UPD + 0U, // VST3q8oddPseudo + 0U, // VST3q8oddPseudo_UPD + 406623656U, // VST4LNd16 + 0U, // VST4LNd16Pseudo + 0U, // VST4LNd16Pseudo_UPD + 398888U, // VST4LNd16_UPD + 406623656U, // VST4LNd32 + 0U, // VST4LNd32Pseudo + 0U, // VST4LNd32Pseudo_UPD + 398888U, // VST4LNd32_UPD + 406623656U, // VST4LNd8 + 0U, // VST4LNd8Pseudo + 0U, // VST4LNd8Pseudo_UPD + 398888U, // VST4LNd8_UPD + 406623656U, // VST4LNq16 + 0U, // VST4LNq16Pseudo + 0U, // VST4LNq16Pseudo_UPD + 398888U, // VST4LNq16_UPD + 406623656U, // VST4LNq32 + 0U, // VST4LNq32Pseudo + 0U, // VST4LNq32Pseudo_UPD + 398888U, // VST4LNq32_UPD + 34079104U, // VST4d16 + 0U, // VST4d16Pseudo + 0U, // VST4d16Pseudo_UPD + 15735552U, // VST4d16_UPD + 34079104U, // VST4d32 + 0U, // VST4d32Pseudo + 0U, // VST4d32Pseudo_UPD + 15735552U, // VST4d32_UPD + 34079104U, // VST4d8 + 0U, // VST4d8Pseudo + 0U, // VST4d8Pseudo_UPD + 15735552U, // VST4d8_UPD + 34079104U, // VST4q16 + 0U, // VST4q16Pseudo_UPD + 15735552U, // VST4q16_UPD + 0U, // VST4q16oddPseudo + 0U, // VST4q16oddPseudo_UPD + 34079104U, // VST4q32 + 0U, // VST4q32Pseudo_UPD + 15735552U, // VST4q32_UPD + 0U, // VST4q32oddPseudo + 0U, // VST4q32oddPseudo_UPD + 34079104U, // VST4q8 + 0U, // VST4q8Pseudo_UPD + 15735552U, // VST4q8_UPD + 0U, // VST4q8oddPseudo + 0U, // VST4q8oddPseudo_UPD + 530U, // VSTMDDB_UPD + 18560U, // VSTMDIA + 530U, // VSTMDIA_UPD + 0U, // VSTMQIA + 530U, // VSTMSDB_UPD + 18560U, // VSTMSIA + 530U, // VSTMSIA_UPD + 6272U, // VSTRD + 6400U, // VSTRH + 6272U, // VSTRS + 0U, // VSTR_FPCXTNS_off + 44U, // VSTR_FPCXTNS_post + 0U, // VSTR_FPCXTNS_pre + 0U, // VSTR_FPCXTS_off + 44U, // VSTR_FPCXTS_post + 0U, // VSTR_FPCXTS_pre + 0U, // VSTR_FPSCR_NZCVQC_off + 44U, // VSTR_FPSCR_NZCVQC_post + 0U, // VSTR_FPSCR_NZCVQC_pre + 0U, // VSTR_FPSCR_off + 44U, // VSTR_FPSCR_post + 0U, // VSTR_FPSCR_pre + 0U, // VSTR_P0_off + 46U, // VSTR_P0_post + 0U, // VSTR_P0_pre + 0U, // VSTR_VPR_off + 44U, // VSTR_VPR_post + 0U, // VSTR_VPR_pre + 2212622U, // VSUBD + 0U, // VSUBH + 17920U, // VSUBHNv2i32 + 0U, // VSUBHNv4i16 + 0U, // VSUBHNv8i8 + 0U, // VSUBLsv2i64 + 0U, // VSUBLsv4i32 + 0U, // VSUBLsv8i16 + 0U, // VSUBLuv2i64 + 0U, // VSUBLuv4i32 + 0U, // VSUBLuv8i16 + 0U, // VSUBS + 0U, // VSUBWsv2i64 + 0U, // VSUBWsv4i32 + 0U, // VSUBWsv8i16 + 0U, // VSUBWuv2i64 + 0U, // VSUBWuv4i32 + 0U, // VSUBWuv8i16 + 0U, // VSUBfd + 0U, // VSUBfq + 0U, // VSUBhd + 0U, // VSUBhq + 0U, // VSUBv16i8 + 17920U, // VSUBv1i64 + 0U, // VSUBv2i32 + 17920U, // VSUBv2i64 + 0U, // VSUBv4i16 + 0U, // VSUBv4i32 + 0U, // VSUBv8i16 + 0U, // VSUBv8i8 + 2163072U, // VSUDOTDI + 2163072U, // VSUDOTQI + 16384U, // VSWPd + 16384U, // VSWPq + 7040U, // VTBL1 + 7168U, // VTBL2 + 7296U, // VTBL3 + 0U, // VTBL3Pseudo + 7424U, // VTBL4 + 0U, // VTBL4Pseudo + 7552U, // VTBX1 + 7680U, // VTBX2 + 7808U, // VTBX3 + 0U, // VTBX3Pseudo + 7936U, // VTBX4 + 0U, // VTBX4Pseudo + 0U, // VTOSHD + 74U, // VTOSHH + 0U, // VTOSHS + 0U, // VTOSIRD + 0U, // VTOSIRH + 0U, // VTOSIRS + 0U, // VTOSIZD + 0U, // VTOSIZH + 0U, // VTOSIZS + 76U, // VTOSLD + 76U, // VTOSLH + 76U, // VTOSLS + 0U, // VTOUHD + 74U, // VTOUHH + 0U, // VTOUHS + 0U, // VTOUIRD + 0U, // VTOUIRH + 0U, // VTOUIRS + 0U, // VTOUIZD + 0U, // VTOUIZH + 0U, // VTOUIZS + 76U, // VTOULD + 76U, // VTOULH + 76U, // VTOULS + 16384U, // VTRNd16 + 16384U, // VTRNd32 + 16384U, // VTRNd8 + 16384U, // VTRNq16 + 16384U, // VTRNq32 + 16384U, // VTRNq8 + 0U, // VTSTv16i8 + 0U, // VTSTv2i32 + 0U, // VTSTv4i16 + 0U, // VTSTv4i32 + 0U, // VTSTv8i16 + 0U, // VTSTv8i8 + 16768U, // VUDOTD + 2163072U, // VUDOTDI + 16768U, // VUDOTQ + 2163072U, // VUDOTQI + 0U, // VUHTOD + 74U, // VUHTOH + 0U, // VUHTOS + 0U, // VUITOD + 0U, // VUITOH + 0U, // VUITOS + 76U, // VULTOD + 76U, // VULTOH + 76U, // VULTOS + 16768U, // VUMMLA + 16768U, // VUSDOTD + 2163072U, // VUSDOTDI + 16768U, // VUSDOTQ + 2163072U, // VUSDOTQI + 16768U, // VUSMMLA + 16384U, // VUZPd16 + 16384U, // VUZPd8 + 16384U, // VUZPq16 + 16384U, // VUZPq32 + 16384U, // VUZPq8 + 16384U, // VZIPd16 + 16384U, // VZIPd8 + 16384U, // VZIPq16 + 16384U, // VZIPq32 + 16384U, // VZIPq8 + 411776U, // sysLDMDA + 8082U, // sysLDMDA_UPD + 411776U, // sysLDMDB + 8082U, // sysLDMDB_UPD + 411776U, // sysLDMIA + 8082U, // sysLDMIA_UPD + 411776U, // sysLDMIB + 8082U, // sysLDMIB_UPD + 411776U, // sysSTMDA + 8082U, // sysSTMDA_UPD + 411776U, // sysSTMDB + 8082U, // sysSTMDB_UPD + 411776U, // sysSTMIA + 8082U, // sysSTMIA_UPD + 411776U, // sysSTMIB + 8082U, // sysSTMIB_UPD + 0U, // t2ADCri + 0U, // t2ADCrr + 16252928U, // t2ADCrs + 0U, // t2ADDri + 0U, // t2ADDri12 + 0U, // t2ADDrr + 16252928U, // t2ADDrs + 0U, // t2ADDspImm + 0U, // t2ADDspImm12 + 1280U, // t2ADR + 0U, // t2ANDri + 0U, // t2ANDrr + 16252928U, // t2ANDrs + 16777216U, // t2ASRri + 0U, // t2ASRrr + 0U, // t2AUT + 524672U, // t2AUTG + 2U, // t2B + 1408U, // t2BFC + 2622976U, // t2BFI + 8192U, // t2BFLi + 16384U, // t2BFLr + 8192U, // t2BFi + 17306496U, // t2BFic + 16384U, // t2BFr + 0U, // t2BICri + 0U, // t2BICrr + 16252928U, // t2BICrs + 0U, // t2BTI + 524672U, // t2BXAUT + 2U, // t2BXJ + 2U, // t2Bcc + 99086U, // t2CDP + 99086U, // t2CDP2 + 0U, // t2CLREX + 0U, // t2CLRM + 16384U, // t2CLZ + 16384U, // t2CMNri + 16384U, // t2CMNzrr + 1024U, // t2CMNzrs + 16384U, // t2CMPri + 16384U, // t2CMPrr + 1024U, // t2CMPrs + 0U, // t2CPS1p + 2U, // t2CPS2p + 17920U, // t2CPS3p + 17920U, // t2CRC32B + 17920U, // t2CRC32CB + 17920U, // t2CRC32CH + 17920U, // t2CRC32CW + 17920U, // t2CRC32H + 17920U, // t2CRC32W + 17303040U, // t2CSEL + 17303040U, // t2CSINC + 17303040U, // t2CSINV + 17303040U, // t2CSNEG + 2U, // t2DBG + 0U, // t2DCPS1 + 0U, // t2DCPS2 + 0U, // t2DCPS3 + 2U, // t2DLS + 0U, // t2DMB + 0U, // t2DSB + 0U, // t2EORri + 0U, // t2EORrr + 16252928U, // t2EORrs + 2U, // t2HINT + 0U, // t2HVC + 0U, // t2ISB + 0U, // t2IT + 0U, // t2Int_eh_sjlj_setjmp + 0U, // t2Int_eh_sjlj_setjmp_nofp + 128U, // t2LDA + 128U, // t2LDAB + 128U, // t2LDAEX + 128U, // t2LDAEXB + 10485760U, // t2LDAEXD + 128U, // t2LDAEXH + 128U, // t2LDAH + 2580U, // t2LDC2L_OFFSET + 4721300U, // t2LDC2L_OPTION + 5245588U, // t2LDC2L_POST + 22U, // t2LDC2L_PRE + 2580U, // t2LDC2_OFFSET + 4721300U, // t2LDC2_OPTION + 5245588U, // t2LDC2_POST + 22U, // t2LDC2_PRE + 2580U, // t2LDCL_OFFSET + 4721300U, // t2LDCL_OPTION + 5245588U, // t2LDCL_POST + 22U, // t2LDCL_PRE + 2580U, // t2LDC_OFFSET + 4721300U, // t2LDC_OPTION + 5245588U, // t2LDC_POST + 22U, // t2LDC_PRE + 18560U, // t2LDMDB + 530U, // t2LDMDB_UPD + 18560U, // t2LDMIA + 530U, // t2LDMIA_UPD + 3968U, // t2LDRBT + 150144U, // t2LDRB_POST + 4352U, // t2LDRB_PRE + 3072U, // t2LDRBi12 + 3968U, // t2LDRBi8 + 8320U, // t2LDRBpci + 8448U, // t2LDRBs + 510132224U, // t2LDRD_POST + 17825792U, // t2LDRD_PRE + 18350080U, // t2LDRDi8 + 8576U, // t2LDREX + 128U, // t2LDREXB + 10485760U, // t2LDREXD + 128U, // t2LDREXH + 3968U, // t2LDRHT + 150144U, // t2LDRH_POST + 4352U, // t2LDRH_PRE + 3072U, // t2LDRHi12 + 3968U, // t2LDRHi8 + 8320U, // t2LDRHpci + 8448U, // t2LDRHs + 3968U, // t2LDRSBT + 150144U, // t2LDRSB_POST + 4352U, // t2LDRSB_PRE + 3072U, // t2LDRSBi12 + 3968U, // t2LDRSBi8 + 8320U, // t2LDRSBpci + 8448U, // t2LDRSBs + 3968U, // t2LDRSHT + 150144U, // t2LDRSH_POST + 4352U, // t2LDRSH_PRE + 3072U, // t2LDRSHi12 + 3968U, // t2LDRSHi8 + 8320U, // t2LDRSHpci + 8448U, // t2LDRSHs + 3968U, // t2LDRT + 150144U, // t2LDR_POST + 4352U, // t2LDR_PRE + 3072U, // t2LDRi12 + 3968U, // t2LDRi8 + 8320U, // t2LDRpci + 8448U, // t2LDRs + 0U, // t2LE + 0U, // t2LEUpdate + 0U, // t2LSLri + 0U, // t2LSLrr + 16777216U, // t2LSRri + 0U, // t2LSRrr + 103924494U, // t2MCR + 103924494U, // t2MCR2 + 137478926U, // t2MCRR + 137478926U, // t2MCRR2 + 33554432U, // t2MLA + 33554432U, // t2MLS + 17920U, // t2MOVTi16 + 16384U, // t2MOVi + 16384U, // t2MOVi16 + 16384U, // t2MOVr + 425984U, // t2MOVsra_flag + 425984U, // t2MOVsrl_flag + 131864U, // t2MRC + 131864U, // t2MRC2 + 0U, // t2MRRC + 0U, // t2MRRC2 + 26U, // t2MRS_AR + 8704U, // t2MRS_M + 3712U, // t2MRSbanked + 28U, // t2MRSsys_AR + 526U, // t2MSR_AR + 526U, // t2MSR_M + 0U, // t2MSRbanked + 0U, // t2MUL + 16384U, // t2MVNi + 16384U, // t2MVNr + 1024U, // t2MVNs + 0U, // t2ORNri + 0U, // t2ORNrr + 16252928U, // t2ORNrs + 0U, // t2ORRri + 0U, // t2ORRrr + 16252928U, // t2ORRrs + 0U, // t2PAC + 0U, // t2PACBTI + 524672U, // t2PACG + 201326592U, // t2PKHBT + 234881024U, // t2PKHTB + 0U, // t2PLDWi12 + 0U, // t2PLDWi8 + 1U, // t2PLDWs + 0U, // t2PLDi12 + 0U, // t2PLDi8 + 1U, // t2PLDpci + 1U, // t2PLDs + 0U, // t2PLIi12 + 0U, // t2PLIi8 + 1U, // t2PLIpci + 1U, // t2PLIs + 0U, // t2QADD + 0U, // t2QADD16 + 0U, // t2QADD8 + 0U, // t2QASX + 0U, // t2QDADD + 0U, // t2QDSUB + 0U, // t2QSAX + 0U, // t2QSUB + 0U, // t2QSUB16 + 0U, // t2QSUB8 + 16384U, // t2RBIT + 16384U, // t2REV + 16384U, // t2REV16 + 16384U, // t2REVSH + 2U, // t2RFEDB + 4U, // t2RFEDBW + 2U, // t2RFEIA + 4U, // t2RFEIAW + 0U, // t2RORri + 0U, // t2RORrr + 16384U, // t2RRX + 0U, // t2RSBri + 0U, // t2RSBrr + 16252928U, // t2RSBrs + 0U, // t2SADD16 + 0U, // t2SADD8 + 0U, // t2SASX + 0U, // t2SB + 0U, // t2SBCri + 0U, // t2SBCrr + 16252928U, // t2SBCrs + 33554432U, // t2SBFX + 0U, // t2SDIV + 0U, // t2SEL + 0U, // t2SETPAN + 0U, // t2SG + 0U, // t2SHADD16 + 0U, // t2SHADD8 + 0U, // t2SHASX + 0U, // t2SHSAX + 0U, // t2SHSUB16 + 0U, // t2SHSUB8 + 2U, // t2SMC + 33554432U, // t2SMLABB + 33554432U, // t2SMLABT + 33554432U, // t2SMLAD + 33554432U, // t2SMLADX + 33554432U, // t2SMLAL + 33554432U, // t2SMLALBB + 33554432U, // t2SMLALBT + 33554432U, // t2SMLALD + 33554432U, // t2SMLALDX + 33554432U, // t2SMLALTB + 33554432U, // t2SMLALTT + 33554432U, // t2SMLATB + 33554432U, // t2SMLATT + 33554432U, // t2SMLAWB + 33554432U, // t2SMLAWT + 33554432U, // t2SMLSD + 33554432U, // t2SMLSDX + 33554432U, // t2SMLSLD + 33554432U, // t2SMLSLDX + 33554432U, // t2SMMLA + 33554432U, // t2SMMLAR + 33554432U, // t2SMMLS + 33554432U, // t2SMMLSR + 0U, // t2SMMUL + 0U, // t2SMMULR + 0U, // t2SMUAD + 0U, // t2SMUADX + 0U, // t2SMULBB + 0U, // t2SMULBT + 33554432U, // t2SMULL + 0U, // t2SMULTB + 0U, // t2SMULTT + 0U, // t2SMULWB + 0U, // t2SMULWT + 0U, // t2SMUSD + 0U, // t2SMUSDX + 0U, // t2SRSDB + 0U, // t2SRSDB_UPD + 0U, // t2SRSIA + 0U, // t2SRSIA_UPD + 218112U, // t2SSAT + 21504U, // t2SSAT16 + 0U, // t2SSAX + 0U, // t2SSUB16 + 0U, // t2SSUB8 + 2580U, // t2STC2L_OFFSET + 4721300U, // t2STC2L_OPTION + 5245588U, // t2STC2L_POST + 22U, // t2STC2L_PRE + 2580U, // t2STC2_OFFSET + 4721300U, // t2STC2_OPTION + 5245588U, // t2STC2_POST + 22U, // t2STC2_PRE + 2580U, // t2STCL_OFFSET + 4721300U, // t2STCL_OPTION + 5245588U, // t2STCL_POST + 22U, // t2STCL_PRE + 2580U, // t2STC_OFFSET + 4721300U, // t2STC_OPTION + 5245588U, // t2STC_POST + 22U, // t2STC_PRE + 128U, // t2STL + 128U, // t2STLB + 10485760U, // t2STLEX + 10485760U, // t2STLEXB + 33554432U, // t2STLEXD + 10485760U, // t2STLEXH + 128U, // t2STLH + 18560U, // t2STMDB + 530U, // t2STMDB_UPD + 18560U, // t2STMIA + 530U, // t2STMIA_UPD + 3968U, // t2STRBT + 150144U, // t2STRB_POST + 4352U, // t2STRB_PRE + 3072U, // t2STRBi12 + 3968U, // t2STRBi8 + 8448U, // t2STRBs + 510133760U, // t2STRD_POST + 17827328U, // t2STRD_PRE + 18350080U, // t2STRDi8 + 18874368U, // t2STREX + 10485760U, // t2STREXB + 33554432U, // t2STREXD + 10485760U, // t2STREXH + 3968U, // t2STRHT + 150144U, // t2STRH_POST + 4352U, // t2STRH_PRE + 3072U, // t2STRHi12 + 3968U, // t2STRHi8 + 8448U, // t2STRHs + 3968U, // t2STRT + 150144U, // t2STR_POST + 4352U, // t2STR_PRE + 3072U, // t2STRi12 + 3968U, // t2STRi8 + 8448U, // t2STRs + 0U, // t2SUBS_PC_LR + 0U, // t2SUBri + 0U, // t2SUBri12 + 0U, // t2SUBrr + 16252928U, // t2SUBrs + 0U, // t2SUBspImm + 0U, // t2SUBspImm12 + 268435456U, // t2SXTAB + 268435456U, // t2SXTAB16 + 268435456U, // t2SXTAH + 229376U, // t2SXTB + 229376U, // t2SXTB16 + 229376U, // t2SXTH + 1U, // t2TBB + 1U, // t2TBH + 16384U, // t2TEQri + 16384U, // t2TEQrr + 1024U, // t2TEQrs + 1U, // t2TSB + 16384U, // t2TSTri + 16384U, // t2TSTrr + 1024U, // t2TSTrs + 16384U, // t2TT + 16384U, // t2TTA + 16384U, // t2TTAT + 16384U, // t2TTT + 0U, // t2UADD16 + 0U, // t2UADD8 + 0U, // t2UASX + 33554432U, // t2UBFX + 0U, // t2UDF + 0U, // t2UDIV + 0U, // t2UHADD16 + 0U, // t2UHADD8 + 0U, // t2UHASX + 0U, // t2UHSAX + 0U, // t2UHSUB16 + 0U, // t2UHSUB8 + 33554432U, // t2UMAAL + 33554432U, // t2UMLAL + 33554432U, // t2UMULL + 0U, // t2UQADD16 + 0U, // t2UQADD8 + 0U, // t2UQASX + 0U, // t2UQSAX + 0U, // t2UQSUB16 + 0U, // t2UQSUB8 + 0U, // t2USAD8 + 33554432U, // t2USADA8 + 301989888U, // t2USAT + 0U, // t2USAT16 + 0U, // t2USAX + 0U, // t2USUB16 + 0U, // t2USUB8 + 268435456U, // t2UXTAB + 268435456U, // t2UXTAB16 + 268435456U, // t2UXTAH + 229376U, // t2UXTB + 229376U, // t2UXTB16 + 229376U, // t2UXTH + 21376U, // t2WLS + 2U, // tADC + 17920U, // tADDhirr + 16768U, // tADDi3 + 2U, // tADDi8 + 0U, // tADDrSP + 19398656U, // tADDrSPi + 16768U, // tADDrr + 8832U, // tADDspi + 17920U, // tADDspr + 8960U, // tADR + 2U, // tAND + 9088U, // tASRri + 2U, // tASRrr + 2U, // tB + 2U, // tBIC + 0U, // tBKPT + 0U, // tBL + 2U, // tBLXNSr + 0U, // tBLXi + 2U, // tBLXr + 2U, // tBX + 2U, // tBXNS + 2U, // tBcc + 2U, // tCBNZ + 2U, // tCBZ + 16384U, // tCMNz + 16384U, // tCMPhir + 16384U, // tCMPi8 + 16384U, // tCMPr + 2U, // tCPS + 2U, // tEOR + 2U, // tHINT + 0U, // tHLT + 0U, // tInt_WIN_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_setjmp + 18560U, // tLDMIA + 9216U, // tLDRBi + 9344U, // tLDRBr + 9472U, // tLDRHi + 9344U, // tLDRHr + 9344U, // tLDRSB + 9344U, // tLDRSH + 9600U, // tLDRi + 8320U, // tLDRpci + 9344U, // tLDRr + 9728U, // tLDRspi + 16768U, // tLSLri + 2U, // tLSLrr + 9088U, // tLSRri + 2U, // tLSRrr + 2U, // tMOVSr + 0U, // tMOVi8 + 16384U, // tMOVr + 16768U, // tMUL + 0U, // tMVN + 2U, // tORR + 0U, // tPICADD + 0U, // tPOP + 0U, // tPUSH + 16384U, // tREV + 16384U, // tREV16 + 16384U, // tREVSH + 2U, // tROR + 0U, // tRSB + 2U, // tSBC + 0U, // tSETEND + 530U, // tSTMIA_UPD + 9216U, // tSTRBi + 9344U, // tSTRBr + 9472U, // tSTRHi + 9344U, // tSTRHr + 9600U, // tSTRi + 9344U, // tSTRr + 9728U, // tSTRspi + 16768U, // tSUBi3 + 2U, // tSUBi8 + 16768U, // tSUBrr + 8832U, // tSUBspi + 2U, // tSVC + 16384U, // tSXTB + 16384U, // tSXTH + 0U, // tTRAP + 16384U, // tTST + 0U, // tUDF + 16384U, // tUXTB + 16384U, // tUXTH + 0U, // t__brkdiv0 + }; + + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; + MnemonicBitsInfo MBI = { +#ifndef CAPSTONE_DIET + AsmStrs + (Bits & 8191) - 1, +#else + NULL, +#endif // CAPSTONE_DIET + Bits + }; + return MBI; +} + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +void printInstruction(MCInst *MI, uint64_t Address, SStream *O) +{ + SStream_concat0(O, ""); + MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O); + + SStream_concat0(O, MnemonicInfo.first); + + uint64_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 6 bits for 43 unique commands. + switch ((uint32_t)((Bits >> 13) & 63)) { + default: + assert(0 && "Invalid command number."); + case 0: + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... + return; + break; + case 1: + // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCri, ADCrr, ADDri, A... + printSBitModifierOperand(MI, 5, O); + printPredicateOperand(MI, 3, O); + break; + case 2: + // ITasm, t2IT + printThumbITMask(MI, 1, O); + break; + case 3: + // LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDRT_POST, STRB... + printPredicateOperand(MI, 2, O); + break; + case 4: + // RRXi, MOVi, MOVr, MOVr_TC, MVNi, MVNr, t2MOVi, t2MOVr, t2MVNi, t2MVNr,... + printSBitModifierOperand(MI, 4, O); + printPredicateOperand(MI, 2, O); + break; + case 5: + // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... + printPredicateOperand(MI, 4, O); + break; + case 6: + // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... + printPredicateOperand(MI, 5, O); + break; + case 7: + // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... + printPredicateOperand(MI, 3, O); + break; + case 8: + // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, MLA, MOVsr, MVNsr, ORRrsi, RSB... + printSBitModifierOperand(MI, 6, O); + printPredicateOperand(MI, 4, O); + break; + case 9: + // ADCrsr, ADDrsr, ANDrsr, BICrsr, EORrsr, ORRrsr, RSBrsr, RSCrsr, SBCrsr... + printSBitModifierOperand(MI, 7, O); + printPredicateOperand(MI, 5, O); + SStream_concat0(O, "\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printSORegRegOperand(MI, 2, O); + return; + break; + case 10: + // AESD, AESE, AESIMC, AESMC, BKPT, BLX, BX, CPS1p, CRC32B, CRC32CB, CRC3... + printOperand(MI, 0, O); + break; + case 11: + // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDOTS_VDOTQ, MV... + printOperand(MI, 1, O); + break; + case 12: + // BL, BLXi, t2BFic, t2LE + printOperandAddr(MI, Address, 0, O); + break; + case 13: + // BLX_pred, BL_pred, BXJ, BX_pred, Bcc, DBG, FLDMXIA, FSTMXIA, HINT, LDM... + printPredicateOperand(MI, 1, O); + break; + case 14: + // BX_RET, ERET, FMSTAT, MOVPCLR, MVE_LCTP, VSCCLRMD, VSCCLRMS, t2AUTG, t... + printPredicateOperand(MI, 0, O); + break; + case 15: + // CDE_CX1, CDE_CX1D, CDE_CX2, CDE_CX2D, CDE_CX3, CDE_CX3D, CDE_VCX1A_fpd... + printPImmediate(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 16: + // CDE_CX3A, CDE_CX3DA, CDP, LDRD_POST, LDRD_PRE, MCR, MRC, MVE_SQRSHRL, ... + printPredicateOperand(MI, 6, O); + break; + case 17: + // CDE_VCX1A_vec, CDE_VCX2_vec, MVE_VABAVs16, MVE_VABAVs32, MVE_VABAVs8, ... + printVPTPredicateOperand(MI, 4, O); + break; + case 18: + // CDE_VCX1_vec, MVE_VABDf16, MVE_VABDf32, MVE_VABDs16, MVE_VABDs32, MVE_... + printVPTPredicateOperand(MI, 3, O); + break; + case 19: + // CDE_VCX2A_vec, CDE_VCX3_vec, MVE_VADC, MVE_VADDLVs32acc, MVE_VADDLVu32... + printVPTPredicateOperand(MI, 5, O); + break; + case 20: + // CDE_VCX3A_vec, MVE_VMLALDAVas16, MVE_VMLALDAVas32, MVE_VMLALDAVau16, M... + printVPTPredicateOperand(MI, 6, O); + break; + case 21: + // CDP2, LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2_OFFSET, LDC2_OPTION... + printPImmediate(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 22: + // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS + printCPSIMod(MI, 0, O); + break; + case 23: + // DMB, DSB + printMemBOption(MI, 0, O); + return; + break; + case 24: + // ISB + printInstSyncBOption(MI, 0, O); + return; + break; + case 25: + // MRRC2 + printPImmediate(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + return; + break; + case 26: + // MVE_VABSf16, MVE_VABSf32, MVE_VABSs16, MVE_VABSs32, MVE_VABSs8, MVE_VA... + printVPTPredicateOperand(MI, 2, O); + break; + case 27: + // MVE_VLD20_16, MVE_VLD20_16_wb, MVE_VLD20_32, MVE_VLD20_32_wb, MVE_VLD2... + printMVEVectorList_2(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 28: + // MVE_VLD40_16, MVE_VLD40_16_wb, MVE_VLD40_32, MVE_VLD40_32_wb, MVE_VLD4... + printMVEVectorList_4(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 29: + // MVE_VPST, MVE_VPTv16i8, MVE_VPTv16i8r, MVE_VPTv16s8, MVE_VPTv16s8r, MV... + printVPTMask(MI, 0, O); + break; + case 30: + // MVE_VST20_16_wb, MVE_VST20_32_wb, MVE_VST20_8_wb, MVE_VST21_16_wb, MVE... + printMVEVectorList_2(MI, 1, O); + SStream_concat0(O, ", "); + printAddrMode7Operand(MI, 2, O); + SStream_concat1(O, '!'); + return; + break; + case 31: + // MVE_VST40_16_wb, MVE_VST40_32_wb, MVE_VST40_8_wb, MVE_VST41_16_wb, MVE... + printMVEVectorList_4(MI, 1, O); + SStream_concat0(O, ", "); + printAddrMode7Operand(MI, 2, O); + SStream_concat1(O, '!'); + return; + break; + case 32: + // PLDWi12, PLDi12, PLIi12 + printAddrModeImm12Operand_0(MI, 0, O); + return; + break; + case 33: + // PLDWrs, PLDrs, PLIrs + printAddrMode2Operand(MI, 0, O); + return; + break; + case 34: + // SETEND, tSETEND + printSetendOperand(MI, 0, O); + return; + break; + case 35: + // SMLAL, UMLAL + printSBitModifierOperand(MI, 8, O); + printPredicateOperand(MI, 6, O); + SStream_concat0(O, "\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 36: + // TSB + printTraceSyncBOption(MI, 0, O); + return; + break; + case 37: + // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... + printPredicateOperand(MI, 7, O); + break; + case 38: + // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... + printPredicateOperand(MI, 9, O); + break; + case 39: + // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... + printPredicateOperand(MI, 11, O); + break; + case 40: + // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... + printPredicateOperand(MI, 8, O); + break; + case 41: + // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... + printPredicateOperand(MI, 13, O); + break; + case 42: + // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... + printSBitModifierOperand(MI, 1, O); + break; + } + + // Fragment 1 encoded into 7 bits for 89 unique commands. + switch ((uint32_t)((Bits >> 19) & 127)) { + default: + assert(0 && "Invalid command number."); + case 0: + // ASRi, ASRr, ITasm, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHT... + SStream_concat1(O, ' '); + break; + case 1: + // VLD1LNdAsm_16, VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_register_Asm_16, VLD2... + SStream_concat0(O, ".16\t"); + ARM_add_vector_size(MI, 16); + break; + case 2: + // VLD1LNdAsm_32, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_register_Asm_32, VLD2... + SStream_concat0(O, ".32\t"); + ARM_add_vector_size(MI, 32); + break; + case 3: + // VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_8, VLD1LNdWB_register_Asm_8, VLD2LNd... + SStream_concat0(O, ".8\t"); + ARM_add_vector_size(MI, 8); + break; + case 4: + // t2LDR_POST_imm, t2LDR_PRE_imm, t2STR_POST_imm, t2STR_PRE_imm + SStream_concat0(O, ".w "); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 5: + // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,... + SStream_concat0(O, "\t"); + break; + case 6: + // AESD, AESE, AESIMC, AESMC, BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS... + SStream_concat0(O, ", "); + break; + case 7: + // BF16_VCVT, BF16_VCVTB, BF16_VCVTT + SStream_concat0(O, ".bf16.f32\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 8: + // BKPT, BL, BLX, BLXi, BX, CPS1p, ERET, HLT, HVC, RFEDA, RFEDB, RFEIA, R... + return; + break; + case 9: + // BX_RET + SStream_concat0(O, "\tlr"); + return; + break; + case 10: + // CDE_CX1, CDE_CX2, CDE_CX3, CDE_VCX1A_fpdp, CDE_VCX1A_fpsp, CDE_VCX1_fp... + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 11: + // CDE_CX1D, CDE_CX2D, CDE_CX3D + printGPRPairOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + break; + case 12: + // CDP2, MCR2, MCRR2 + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 13: + // FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VFMAD, V... + SStream_concat0(O, ".f64\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F64); + printOperand(MI, 0, O); + break; + case 14: + // FCONSTH, MVE_VABDf16, MVE_VABSf16, MVE_VADD_qr_f16, MVE_VADDf16, MVE_V... + SStream_concat0(O, ".f16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F16); + break; + case 15: + // FCONSTS, MVE_VABDf32, MVE_VABSf32, MVE_VADD_qr_f32, MVE_VADDf32, MVE_V... + SStream_concat0(O, ".f32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F32); + break; + case 16: + // FMSTAT + SStream_concat0(O, "\tAPSR_nzcv, fpscr"); + return; + break; + case 17: + // LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2_OFFSET, LDC2_OPTION, LDC2... + printCImmediate(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 18: + // LDC2L_PRE, LDC2_PRE, STC2L_PRE, STC2_PRE + printCImmediate(MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode5Operand_1(MI, 3, O); + SStream_concat1(O, '!'); + return; + break; + case 19: + // MOVPCLR + SStream_concat0(O, "\tpc, lr"); + return; + break; + case 20: + // MRC2 + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 21: + // MVE_VABAVs16, MVE_VABDs16, MVE_VABSs16, MVE_VADDVs16acc, MVE_VADDVs16n... + SStream_concat0(O, ".s16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_S16); + break; + case 22: + // MVE_VABAVs32, MVE_VABDs32, MVE_VABSs32, MVE_VADDLVs32acc, MVE_VADDLVs3... + SStream_concat0(O, ".s32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_S32); + break; + case 23: + // MVE_VABAVs8, MVE_VABDs8, MVE_VABSs8, MVE_VADDVs8acc, MVE_VADDVs8no_acc... + SStream_concat0(O, ".s8\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_S8); + break; + case 24: + // MVE_VABAVu16, MVE_VABDu16, MVE_VADDVu16acc, MVE_VADDVu16no_acc, MVE_VC... + SStream_concat0(O, ".u16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_U16); + break; + case 25: + // MVE_VABAVu32, MVE_VABDu32, MVE_VADDLVu32acc, MVE_VADDLVu32no_acc, MVE_... + SStream_concat0(O, ".u32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_U32); + break; + case 26: + // MVE_VABAVu8, MVE_VABDu8, MVE_VADDVu8acc, MVE_VADDVu8no_acc, MVE_VCMPu8... + SStream_concat0(O, ".u8\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_U8); + break; + case 27: + // MVE_VADC, MVE_VADCI, MVE_VADD_qr_i32, MVE_VADDi32, MVE_VBICimmi32, MVE... + SStream_concat0(O, ".i32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_I32); + break; + case 28: + // MVE_VADD_qr_i16, MVE_VADDi16, MVE_VBICimmi16, MVE_VCADDi16, MVE_VCLZs1... + SStream_concat0(O, ".i16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_I16); + break; + case 29: + // MVE_VADD_qr_i8, MVE_VADDi8, MVE_VCADDi8, MVE_VCLZs8, MVE_VCMPi8, MVE_V... + SStream_concat0(O, ".i8\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_I8); + break; + case 30: + // MVE_VCTP64, MVE_VSTRD64_qi, MVE_VSTRD64_qi_pre, MVE_VSTRD64_rq, MVE_VS... + SStream_concat0(O, ".64\t"); + ARM_add_vector_size(MI, 64); + break; + case 31: + // MVE_VCVTf16f32bh, MVE_VCVTf16f32th, VCVTBSH, VCVTTSH, VCVTf2h + SStream_concat0(O, ".f16.f32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F16F32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 32: + // MVE_VCVTf16s16_fix, MVE_VCVTf16s16n, VCVTs2hd, VCVTs2hq, VCVTxs2hd, VC... + SStream_concat0(O, ".f16.s16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F16S16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 33: + // MVE_VCVTf16u16_fix, MVE_VCVTf16u16n, VCVTu2hd, VCVTu2hq, VCVTxu2hd, VC... + SStream_concat0(O, ".f16.u16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F16U16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 34: + // MVE_VCVTf32f16bh, MVE_VCVTf32f16th, VCVTBHS, VCVTTHS, VCVTh2f + SStream_concat0(O, ".f32.f16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F32F16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 35: + // MVE_VCVTf32s32_fix, MVE_VCVTf32s32n, VCVTs2fd, VCVTs2fq, VCVTxs2fd, VC... + SStream_concat0(O, ".f32.s32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F32S32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 36: + // MVE_VCVTf32u32_fix, MVE_VCVTf32u32n, VCVTu2fd, VCVTu2fq, VCVTxu2fd, VC... + SStream_concat0(O, ".f32.u32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F32U32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 37: + // MVE_VCVTs16f16_fix, MVE_VCVTs16f16a, MVE_VCVTs16f16m, MVE_VCVTs16f16n,... + SStream_concat0(O, ".s16.f16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_S16F16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 38: + // MVE_VCVTs32f32_fix, MVE_VCVTs32f32a, MVE_VCVTs32f32m, MVE_VCVTs32f32n,... + SStream_concat0(O, ".s32.f32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_S32F32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 39: + // MVE_VCVTu16f16_fix, MVE_VCVTu16f16a, MVE_VCVTu16f16m, MVE_VCVTu16f16n,... + SStream_concat0(O, ".u16.f16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_U16F16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 40: + // MVE_VCVTu32f32_fix, MVE_VCVTu32f32a, MVE_VCVTu32f32m, MVE_VCVTu32f32n,... + SStream_concat0(O, ".u32.f32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_U32F32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 41: + // MVE_VLD20_16, MVE_VLD20_32, MVE_VLD20_8, MVE_VLD21_16, MVE_VLD21_32, M... + printAddrMode7Operand(MI, 2, O); + return; + break; + case 42: + // MVE_VLD20_16_wb, MVE_VLD20_32_wb, MVE_VLD20_8_wb, MVE_VLD21_16_wb, MVE... + printAddrMode7Operand(MI, 3, O); + SStream_concat1(O, '!'); + return; + break; + case 43: + // MVE_VLDRDU64_qi, MVE_VLDRDU64_qi_pre, MVE_VLDRDU64_rq, MVE_VLDRDU64_rq... + SStream_concat0(O, ".u64\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_U64); + break; + case 44: + // MVE_VMOVimmi64, VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i... + SStream_concat0(O, ".i64\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_I64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 45: + // MVE_VMULLBp16, MVE_VMULLTp16 + SStream_concat0(O, ".p16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_P16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 46: + // MVE_VMULLBp8, MVE_VMULLTp8, VMULLp8, VMULpd, VMULpq + SStream_concat0(O, ".p8\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_P8); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 47: + // MVE_VST20_16, MVE_VST20_32, MVE_VST20_8, MVE_VST21_16, MVE_VST21_32, M... + printAddrMode7Operand(MI, 1, O); + return; + break; + case 48: + // RFEDA_UPD, RFEDB_UPD, RFEIA_UPD, RFEIB_UPD + SStream_concat1(O, '!'); + return; + break; + case 49: + // VCVTBDH, VCVTTDH + SStream_concat0(O, ".f16.f64\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F16F64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 50: + // VCVTBHD, VCVTTHD + SStream_concat0(O, ".f64.f16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F64F16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 51: + // VCVTDS + SStream_concat0(O, ".f64.f32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F64F32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 52: + // VCVTSD + SStream_concat0(O, ".f32.f64\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F32F64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 53: + // VJCVT, VTOSIRD, VTOSIZD, VTOSLD + SStream_concat0(O, ".s32.f64\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_S32F64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 54: + // VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq... + SStream_concat0(O, ".16\t{"); + ARM_add_vector_size(MI, 16); + break; + case 55: + // VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq... + SStream_concat0(O, ".32\t{"); + ARM_add_vector_size(MI, 32); + break; + case 56: + // VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U... + SStream_concat0(O, ".8\t{"); + ARM_add_vector_size(MI, 8); + break; + case 57: + // VLDR_FPCXTNS_off, VLDR_FPCXTNS_post, VLDR_FPCXTNS_pre, VMSR_FPCXTNS, V... + SStream_concat0(O, "\tfpcxtns, "); + break; + case 58: + // VLDR_FPCXTS_off, VLDR_FPCXTS_post, VLDR_FPCXTS_pre, VMSR_FPCXTS, VSTR_... + SStream_concat0(O, "\tfpcxts, "); + break; + case 59: + // VLDR_FPSCR_NZCVQC_off, VLDR_FPSCR_NZCVQC_post, VLDR_FPSCR_NZCVQC_pre, ... + SStream_concat0(O, "\tfpscr_nzcvqc, "); + break; + case 60: + // VLDR_FPSCR_off, VLDR_FPSCR_post, VLDR_FPSCR_pre, VMSR, VSTR_FPSCR_off,... + SStream_concat0(O, "\tfpscr, "); + break; + case 61: + // VLDR_P0_off, VLDR_P0_post, VLDR_P0_pre, VMSR_P0, VSTR_P0_off, VSTR_P0_... + SStream_concat0(O, "\tp0, "); + break; + case 62: + // VLDR_VPR_off, VLDR_VPR_post, VLDR_VPR_pre, VMSR_VPR, VSTR_VPR_off, VST... + SStream_concat0(O, "\tvpr, "); + break; + case 63: + // VMSR_FPEXC + SStream_concat0(O, "\tfpexc, "); + printOperand(MI, 0, O); + return; + break; + case 64: + // VMSR_FPINST + SStream_concat0(O, "\tfpinst, "); + printOperand(MI, 0, O); + return; + break; + case 65: + // VMSR_FPINST2 + SStream_concat0(O, "\tfpinst2, "); + printOperand(MI, 0, O); + return; + break; + case 66: + // VMSR_FPSID + SStream_concat0(O, "\tfpsid, "); + printOperand(MI, 0, O); + return; + break; + case 67: + // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V... + SStream_concat0(O, ".s64\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_S64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 68: + // VSHTOD + SStream_concat0(O, ".f64.s16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F64S16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 69: + // VSHTOS + SStream_concat0(O, ".f32.s16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F32S16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 70: + // VSITOD, VSLTOD + SStream_concat0(O, ".f64.s32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F64S32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 71: + // VSITOH, VSLTOH + SStream_concat0(O, ".f16.s32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F16S32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 72: + // VTOSHD + SStream_concat0(O, ".s16.f64\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_S16F64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 73: + // VTOSHS + SStream_concat0(O, ".s16.f32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_S16F32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 74: + // VTOSIRH, VTOSIZH, VTOSLH + SStream_concat0(O, ".s32.f16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_S32F16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 75: + // VTOUHD + SStream_concat0(O, ".u16.f64\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_U16F64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 76: + // VTOUHS + SStream_concat0(O, ".u16.f32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_U16F32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 77: + // VTOUIRD, VTOUIZD, VTOULD + SStream_concat0(O, ".u32.f64\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_U32F64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 78: + // VTOUIRH, VTOUIZH, VTOULH + SStream_concat0(O, ".u32.f16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_U32F16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 79: + // VUHTOD + SStream_concat0(O, ".f64.u16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F64U16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 80: + // VUHTOS + SStream_concat0(O, ".f32.u16\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F32U16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 81: + // VUITOD, VULTOD + SStream_concat0(O, ".f64.u32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F64U32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 82: + // VUITOH, VULTOH + SStream_concat0(O, ".f16.u32\t"); + ARM_add_vector_data(MI, ARM_VECTORDATA_F16U32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 83: + // t2ADCrr, t2ADCrs, t2ADDri, t2ADDrr, t2ADDrs, t2ADDspImm, t2ADR, t2ANDr... + SStream_concat0(O, ".w\t"); + break; + case 84: + // t2SRSDB, t2SRSIA + SStream_concat0(O, "\tsp, "); + printOperand(MI, 0, O); + return; + break; + case 85: + // t2SRSDB_UPD, t2SRSIA_UPD + SStream_concat0(O, "\tsp!, "); + printOperand(MI, 0, O); + return; + break; + case 86: + // t2SUBS_PC_LR + SStream_concat0(O, "\tpc, lr, "); + printOperand(MI, 0, O); + return; + break; + case 87: + // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... + printPredicateOperand(MI, 4, O); + SStream_concat0(O, "\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 88: + // tMOVi8, tMVN, tRSB + printPredicateOperand(MI, 3, O); + SStream_concat0(O, "\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + break; + } + + // Fragment 2 encoded into 7 bits for 69 unique commands. + switch ((uint32_t)((Bits >> 26) & 127)) { + default: + assert(0 && "Invalid command number."); + case 0: + // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDR... + printOperand(MI, 0, O); + break; + case 1: + // ITasm, t2IT + printMandatoryPredicateOperand(MI, 0, O); + return; + break; + case 2: + // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... + printVectorListThreeAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + break; + case 3: + // VLD3DUPqAsm_16, VLD3DUPqAsm_32, VLD3DUPqAsm_8, VLD3DUPqWB_fixed_Asm_16... + printVectorListThreeSpacedAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + break; + case 4: + // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi... + printVectorListThree(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 5: + // VLD3qAsm_16, VLD3qAsm_32, VLD3qAsm_8, VLD3qWB_fixed_Asm_16, VLD3qWB_fi... + printVectorListThreeSpaced(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + break; + case 6: + // VLD4DUPdAsm_16, VLD4DUPdAsm_32, VLD4DUPdAsm_8, VLD4DUPdWB_fixed_Asm_16... + printVectorListFourAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + break; + case 7: + // VLD4DUPqAsm_16, VLD4DUPqAsm_32, VLD4DUPqAsm_8, VLD4DUPqWB_fixed_Asm_16... + printVectorListFourSpacedAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + break; + case 8: + // VLD4dAsm_16, VLD4dAsm_32, VLD4dAsm_8, VLD4dWB_fixed_Asm_16, VLD4dWB_fi... + printVectorListFour(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 9: + // VLD4qAsm_16, VLD4qAsm_32, VLD4qAsm_8, VLD4qWB_fixed_Asm_16, VLD4qWB_fi... + printVectorListFourSpaced(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + break; + case 10: + // t2LDR_POST_imm, t2STR_POST_imm, VLDR_FPCXTNS_post, VLDR_FPCXTS_post, V... + printAddrMode7Operand(MI, 1, O); + break; + case 11: + // t2LDR_PRE_imm, t2STR_PRE_imm + printT2AddrModeImm8Operand_1(MI, 1, O); + SStream_concat1(O, '!'); + return; + break; + case 12: + // AESD, AESE, BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDO... + printOperand(MI, 2, O); + break; + case 13: + // AESIMC, AESMC, BF16_VCVT, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, C... + printOperand(MI, 1, O); + break; + case 14: + // BL_pred, Bcc, t2B, t2BFLi, t2BFLr, t2BFi, t2BFr, t2Bcc, tB, tBcc + printOperandAddr(MI, Address, 0, O); + break; + case 15: + // CDE_CX1A, CDE_CX1DA, CDE_CX2A, CDE_CX2DA, CDE_CX3A, CDE_CX3DA, CDE_VCX... + printPImmediate(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 16: + // CDE_CX1D, MVE_LCTP, MVE_VCVTf16s16n, MVE_VCVTf16u16n, MVE_VCVTf32s32n,... + return; + break; + case 17: + // CDE_CX2D, CDE_CX3D, FCONSTD, MVE_VCVTf16s16_fix, MVE_VCVTf16u16_fix, M... + SStream_concat0(O, ", "); + break; + case 18: + // CDE_VCX1A_fpdp, CDE_VCX1A_fpsp, CDE_VCX2A_fpdp, CDE_VCX2A_fpsp, CDE_VC... + printOperand(MI, 3, O); + break; + case 19: + // CDP, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDC_OFFSET, LDC_OPTION, LDC_... + printPImmediate(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 20: + // CDP2 + printCImmediate(MI, 2, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 21: + // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS + printCPSIFlag(MI, 1, O); + break; + case 22: + // LDAEXD, LDREXD + printGPRPairOperand(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode7Operand(MI, 1, O); + return; + break; + case 23: + // LDC2L_OFFSET, LDC2_OFFSET, STC2L_OFFSET, STC2_OFFSET + printAddrMode5Operand_0(MI, 2, O); + return; + break; + case 24: + // LDC2L_OPTION, LDC2L_POST, LDC2_OPTION, LDC2_POST, STC2L_OPTION, STC2L_... + printAddrMode7Operand(MI, 2, O); + break; + case 25: + // MRRC, t2MRRC, t2MRRC2 + printPImmediate(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + return; + break; + case 26: + // MSR, MSRi, t2MSR_AR, t2MSR_M + printMSRMaskOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 27: + // MSRbanked, t2MSRbanked + printBankedRegOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 28: + // MVE_LETP, t2LEUpdate, tBL, tBLXi + printOperandAddr(MI, Address, 2, O); + return; + break; + case 29: + // MVE_VCMPf16, MVE_VCMPf16r, MVE_VCMPf32, MVE_VCMPf32r, MVE_VCMPi16, MVE... + printMandatoryRestrictedPredicateOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 30: + // MVE_VMOVimmi64, VMOVv1i64, VMOVv2i64 + printVMOVModImmOperand(MI, 1, O); + return; + break; + case 31: + // VCMPEZD, VCMPZD, tRSB + SStream_concat0(O, ", #0"); + return; + break; + case 32: + // VLD1DUPd16, VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32, VLD... + printVectorListOneAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 33: + // VLD1DUPq16, VLD1DUPq16wb_fixed, VLD1DUPq16wb_register, VLD1DUPq32, VLD... + printVectorListTwoAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 34: + // VLD1d16, VLD1d16wb_fixed, VLD1d16wb_register, VLD1d32, VLD1d32wb_fixed... + printVectorListOne(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 35: + // VLD1q16, VLD1q16wb_fixed, VLD1q16wb_register, VLD1q32, VLD1q32wb_fixed... + printVectorListTwo(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 36: + // VLD2DUPd16x2, VLD2DUPd16x2wb_fixed, VLD2DUPd16x2wb_register, VLD2DUPd3... + printVectorListTwoSpacedAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 37: + // VLD2b16, VLD2b16wb_fixed, VLD2b16wb_register, VLD2b32, VLD2b32wb_fixed... + printVectorListTwoSpaced(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 38: + // VLDR_FPCXTNS_off, VLDR_FPCXTS_off, VLDR_FPSCR_NZCVQC_off, VLDR_FPSCR_o... + printT2AddrModeImm8s4Operand_0(MI, 0, O); + return; + break; + case 39: + // VLDR_FPCXTNS_pre, VLDR_FPCXTS_pre, VLDR_FPSCR_NZCVQC_pre, VLDR_FPSCR_p... + printT2AddrModeImm8s4Operand_1(MI, 1, O); + SStream_concat1(O, '!'); + return; + break; + case 40: + // VLDR_P0_off, VSTR_P0_off + printT2AddrModeImm8s4Operand_0(MI, 1, O); + return; + break; + case 41: + // VLDR_P0_pre, VSTR_P0_pre + printT2AddrModeImm8s4Operand_1(MI, 2, O); + SStream_concat1(O, '!'); + return; + break; + case 42: + // VSCCLRMD, VSCCLRMS, t2CLRM, tPOP, tPUSH + printRegisterList(MI, 2, O); + return; + break; + case 43: + // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST2LNd16_UPD, VST2LNd32_U... + printOperand(MI, 4, O); + break; + case 44: + // VST1d16, VST1d32, VST1d64, VST1d8 + printVectorListOne(MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 45: + // VST1d16Q, VST1d32Q, VST1d64Q, VST1d8Q, VST2q16, VST2q32, VST2q8 + printVectorListFour(MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 46: + // VST1d16Qwb_fixed, VST1d32Qwb_fixed, VST1d64Qwb_fixed, VST1d8Qwb_fixed,... + printVectorListFour(MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat1(O, '!'); + return; + break; + case 47: + // VST1d16Qwb_register, VST1d32Qwb_register, VST1d64Qwb_register, VST1d8Q... + printVectorListFour(MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 48: + // VST1d16T, VST1d32T, VST1d64T, VST1d8T + printVectorListThree(MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 49: + // VST1d16Twb_fixed, VST1d32Twb_fixed, VST1d64Twb_fixed, VST1d8Twb_fixed + printVectorListThree(MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat1(O, '!'); + return; + break; + case 50: + // VST1d16Twb_register, VST1d32Twb_register, VST1d64Twb_register, VST1d8T... + printVectorListThree(MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 51: + // VST1d16wb_fixed, VST1d32wb_fixed, VST1d64wb_fixed, VST1d8wb_fixed + printVectorListOne(MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat1(O, '!'); + return; + break; + case 52: + // VST1d16wb_register, VST1d32wb_register, VST1d64wb_register, VST1d8wb_r... + printVectorListOne(MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 53: + // VST1q16, VST1q32, VST1q64, VST1q8, VST2d16, VST2d32, VST2d8 + printVectorListTwo(MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 54: + // VST1q16wb_fixed, VST1q32wb_fixed, VST1q64wb_fixed, VST1q8wb_fixed, VST... + printVectorListTwo(MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat1(O, '!'); + return; + break; + case 55: + // VST1q16wb_register, VST1q32wb_register, VST1q64wb_register, VST1q8wb_r... + printVectorListTwo(MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 56: + // VST2b16, VST2b32, VST2b8 + printVectorListTwoSpaced(MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 57: + // VST2b16wb_fixed, VST2b32wb_fixed, VST2b8wb_fixed + printVectorListTwoSpaced(MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat1(O, '!'); + return; + break; + case 58: + // VST2b16wb_register, VST2b32wb_register, VST2b8wb_register + printVectorListTwoSpaced(MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 59: + // t2BFic, tCBNZ, tCBZ + printOperandAddr(MI, Address, 1, O); + break; + case 60: + // t2DMB, t2DSB + printMemBOption(MI, 0, O); + return; + break; + case 61: + // t2ISB + printInstSyncBOption(MI, 0, O); + return; + break; + case 62: + // t2PLDWi12, t2PLDi12, t2PLIi12 + printAddrModeImm12Operand_0(MI, 0, O); + return; + break; + case 63: + // t2PLDWi8, t2PLDi8, t2PLIi8 + printT2AddrModeImm8Operand_0(MI, 0, O); + return; + break; + case 64: + // t2PLDWs, t2PLDs, t2PLIs + printT2AddrModeSoRegOperand(MI, 0, O); + return; + break; + case 65: + // t2PLDpci, t2PLIpci + printThumbLdrLabelOperand(MI, 0, O); + return; + break; + case 66: + // t2TBB + printAddrModeTBB(MI, 0, O); + return; + break; + case 67: + // t2TBH + printAddrModeTBH(MI, 0, O); + return; + break; + case 68: + // t2TSB + printTraceSyncBOption(MI, 0, O); + return; + break; + } + + // Fragment 3 encoded into 6 bits for 39 unique commands. + switch ((uint32_t)((Bits >> 33) & 63)) { + default: + assert(0 && "Invalid command number."); + case 0: + // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDR... + SStream_concat0(O, ", "); + break; + case 1: + // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPqAsm_16, VLD3DUP... + return; + break; + case 2: + // VLD3DUPdWB_fixed_Asm_16, VLD3DUPdWB_fixed_Asm_32, VLD3DUPdWB_fixed_Asm... + SStream_concat1(O, '!'); + return; + break; + case 3: + // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi... + printAddrMode6Operand(MI, 1, O); + break; + case 4: + // CDE_CX1A, CDE_CX2A, CDE_CX3A, CDE_VCX1A_vec, CDE_VCX1_vec, CDE_VCX2A_v... + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 5: + // CDE_CX1DA, CDE_CX2DA, CDE_CX3DA + printGPRPairOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + break; + case 6: + // CDE_CX2D, CDE_CX3D + printOperand(MI, 3, O); + break; + case 7: + // CDP, MCR, MCRR, MSR, VABSD, VADDD, VCMPD, VCMPED, VDIVD, VMOVD, VMULD,... + printOperand(MI, 1, O); + break; + case 8: + // FCONSTD + printFPImmOperand(MI, 1, O); + return; + break; + case 9: + // FLDMXDB_UPD, FLDMXIA_UPD, FSTMXDB_UPD, FSTMXIA_UPD, LDMDA_UPD, LDMDB_U... + SStream_concat0(O, "!, "); + printRegisterList(MI, 4, O); + break; + case 10: + // LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDC_OFFSET, LDC_OPTION, LDC_POST,... + printCImmediate(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 11: + // LDCL_PRE, LDC_PRE, STCL_PRE, STC_PRE, t2LDC2L_PRE, t2LDC2_PRE, t2LDCL_... + printCImmediate(MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode5Operand_1(MI, 3, O); + SStream_concat1(O, '!'); + return; + break; + case 12: + // MRC, MVE_VCVTf16s16_fix, MVE_VCVTf16u16_fix, MVE_VCVTf32s32_fix, MVE_V... + printOperand(MI, 2, O); + break; + case 13: + // MRS, t2MRS_AR + SStream_concat0(O, ", apsr"); + return; + break; + case 14: + // MRSsys, t2MRSsys_AR + SStream_concat0(O, ", spsr"); + return; + break; + case 15: + // MSRi + printModImmOperand(MI, 1, O); + return; + break; + case 16: + // MVE_VMOV_q_rr + printVectorIndex(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + printVectorIndex(MI, 5, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 17: + // MVE_VMOV_to_lane_16, MVE_VMOV_to_lane_32, MVE_VMOV_to_lane_8, VSETLNi1... + printVectorIndex(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 18: + // VCMPEZH, VCMPEZS, VCMPZH, VCMPZS + SStream_concat0(O, ", #0"); + return; + break; + case 19: + // VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32wb_fixed, VLD1DUP... + printAddrMode6Operand(MI, 2, O); + break; + case 20: + // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... + SStream_concat1(O, '['); + break; + case 21: + // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... + SStream_concat0(O, "[], "); + printOperand(MI, 1, O); + SStream_concat0(O, "[], "); + printOperand(MI, 2, O); + break; + case 22: + // VLDR_FPCXTNS_post, VLDR_FPCXTS_post, VLDR_FPSCR_NZCVQC_post, VLDR_FPSC... + printT2AddrModeImm8s4OffsetOperand(MI, 2, O); + return; + break; + case 23: + // VLDR_P0_post, VSTR_P0_post + printT2AddrModeImm8s4OffsetOperand(MI, 3, O); + return; + break; + case 24: + // VMRS + SStream_concat0(O, ", fpscr"); + return; + break; + case 25: + // VMRS_FPCXTNS + SStream_concat0(O, ", fpcxtns"); + return; + break; + case 26: + // VMRS_FPCXTS + SStream_concat0(O, ", fpcxts"); + return; + break; + case 27: + // VMRS_FPEXC + SStream_concat0(O, ", fpexc"); + return; + break; + case 28: + // VMRS_FPINST + SStream_concat0(O, ", fpinst"); + return; + break; + case 29: + // VMRS_FPINST2 + SStream_concat0(O, ", fpinst2"); + return; + break; + case 30: + // VMRS_FPSCR_NZCVQC + SStream_concat0(O, ", fpscr_nzcvqc"); + return; + break; + case 31: + // VMRS_FPSID + SStream_concat0(O, ", fpsid"); + return; + break; + case 32: + // VMRS_MVFR0 + SStream_concat0(O, ", mvfr0"); + return; + break; + case 33: + // VMRS_MVFR1 + SStream_concat0(O, ", mvfr1"); + return; + break; + case 34: + // VMRS_MVFR2 + SStream_concat0(O, ", mvfr2"); + return; + break; + case 35: + // VMRS_P0 + SStream_concat0(O, ", p0"); + return; + break; + case 36: + // VMRS_VPR + SStream_concat0(O, ", vpr"); + return; + break; + case 37: + // VSHTOH, VTOSHH, VTOUHH, VUHTOH + printFBits16(MI, 2, O); + return; + break; + case 38: + // VSLTOD, VSLTOH, VSLTOS, VTOSLD, VTOSLH, VTOSLS, VTOULD, VTOULH, VTOULS... + printFBits32(MI, 2, O); + return; + break; + } + + // Fragment 4 encoded into 7 bits for 77 unique commands. + switch ((uint32_t)((Bits >> 39) & 127)) { + default: + assert(0 && "Invalid command number."); + case 0: + // ASRi, ASRr, LDRConstPool, LSLi, LSLr, LSRi, LSRr, RORi, RORr, RRXi, t2... + printOperand(MI, 1, O); + break; + case 1: + // LDRBT_POST, LDRHTii, LDRSBTii, LDRSHTii, LDRT_POST, STRBT_POST, STRT_P... + printAddrMode7Operand(MI, 1, O); + return; + break; + case 2: + // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... + printAddrMode6Operand(MI, 2, O); + break; + case 3: + // VLD3DUPdWB_register_Asm_16, VLD3DUPdWB_register_Asm_32, VLD3DUPdWB_reg... + printOperand(MI, 3, O); + break; + case 4: + // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD4dAsm_16, VLD4dAsm_32, VLD4dA... + return; + break; + case 5: + // VLD3dWB_fixed_Asm_16, VLD3dWB_fixed_Asm_32, VLD3dWB_fixed_Asm_8, VLD4d... + SStream_concat1(O, '!'); + return; + break; + case 6: + // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... + SStream_concat0(O, ", "); + break; + case 7: + // t2LDR_POST_imm, t2STR_POST_imm + printT2AddrModeImm8OffsetOperand(MI, 2, O); + return; + break; + case 8: + // t2MOVSsi, t2MOVsi, t2CMNzrs, t2CMPrs, t2MVNs, t2TEQrs, t2TSTrs + printT2SOOperand(MI, 1, O); + return; + break; + case 9: + // t2MOVSsr, t2MOVsr, CMNzrsr, CMPrsr, MOVsr, MVNsr, TEQrsr, TSTrsr + printSORegRegOperand(MI, 1, O); + return; + break; + case 10: + // ADR, t2ADR + printAdrLabelOperand_0(MI, 1, O); + return; + break; + case 11: + // BFC, t2BFC + printBitfieldInvMaskImmOperand(MI, 2, O); + return; + break; + case 12: + // BFI, CDE_VCX1_vec, CDE_VCX2_vec, CDE_VCX3_vec, CPS3p, CRC32B, CRC32CB,... + printOperand(MI, 2, O); + break; + case 13: + // CDE_VCX2A_fpdp, CDE_VCX2A_fpsp, CDE_VCX3A_fpdp, CDE_VCX3A_fpsp + printOperand(MI, 4, O); + break; + case 14: + // CMNri, CMPri, MOVi, MVNi, TEQri, TSTri + printModImmOperand(MI, 1, O); + return; + break; + case 15: + // CMNzrsi, CMPrsi, MOVsi, MVNsi, TEQrsi, TSTrsi + printSORegImmOperand(MI, 1, O); + return; + break; + case 16: + // FCONSTH, FCONSTS, MVE_VMOVimmf32, VMOVv2f32, VMOVv4f32 + printFPImmOperand(MI, 1, O); + return; + break; + case 17: + // FLDMXIA, FSTMXIA, LDMDA, LDMDB, LDMIA, LDMIB, STMDA, STMDB, STMIA, STM... + printRegisterList(MI, 3, O); + break; + case 18: + // LDC2L_OPTION, LDC2_OPTION, STC2L_OPTION, STC2_OPTION + printCoprocOptionImm(MI, 3, O); + return; + break; + case 19: + // LDC2L_POST, LDC2_POST, STC2L_POST, STC2_POST + printPostIdxImm8s4Operand(MI, 3, O); + return; + break; + case 20: + // LDCL_OFFSET, LDC_OFFSET, STCL_OFFSET, STC_OFFSET, t2LDC2L_OFFSET, t2LD... + printAddrMode5Operand_0(MI, 2, O); + return; + break; + case 21: + // LDCL_OPTION, LDCL_POST, LDC_OPTION, LDC_POST, LDRBT_POST_IMM, LDRBT_PO... + printAddrMode7Operand(MI, 2, O); + break; + case 22: + // LDRB_PRE_IMM, LDR_PRE_IMM, STRB_PRE_IMM, STR_PRE_IMM + printAddrModeImm12Operand_1(MI, 2, O); + SStream_concat1(O, '!'); + return; + break; + case 23: + // LDRB_PRE_REG, LDR_PRE_REG, STRB_PRE_REG, STR_PRE_REG + printAddrMode2Operand(MI, 2, O); + SStream_concat1(O, '!'); + return; + break; + case 24: + // LDRBi12, LDRcp, LDRi12, STRBi12, STRi12, t2LDRBi12, t2LDRHi12, t2LDRSB... + printAddrModeImm12Operand_0(MI, 1, O); + return; + break; + case 25: + // LDRBrs, LDRrs, STRBrs, STRrs + printAddrMode2Operand(MI, 1, O); + return; + break; + case 26: + // LDRH, LDRSB, LDRSH, STRH + printAddrMode3Operand_0(MI, 1, O); + return; + break; + case 27: + // LDRH_PRE, LDRSB_PRE, LDRSH_PRE, STRH_PRE + printAddrMode3Operand_1(MI, 2, O); + SStream_concat1(O, '!'); + return; + break; + case 28: + // MCR2 + printCImmediate(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 29: + // MRSbanked, t2MRSbanked + printBankedRegOperand(MI, 1, O); + return; + break; + case 30: + // MVE_VBICimmi16, MVE_VBICimmi32, MVE_VORRimmi16, MVE_VORRimmi32 + printVMOVModImmOperand(MI, 2, O); + return; + break; + case 31: + // MVE_VLDRBS16, MVE_VLDRBS32, MVE_VLDRBU16, MVE_VLDRBU32, MVE_VLDRBU8, M... + printT2AddrModeImm8Operand_0(MI, 1, O); + return; + break; + case 32: + // MVE_VLDRBS16_pre, MVE_VLDRBS32_pre, MVE_VLDRBU16_pre, MVE_VLDRBU32_pre... + printT2AddrModeImm8Operand_0(MI, 2, O); + SStream_concat1(O, '!'); + return; + break; + case 33: + // MVE_VLDRBS16_rq, MVE_VLDRBS32_rq, MVE_VLDRBU16_rq, MVE_VLDRBU32_rq, MV... + printMveAddrModeRQOperand_0(MI, 1, O); + return; + break; + case 34: + // MVE_VLDRBU8_pre, MVE_VLDRHU16_pre, MVE_VLDRWU32_pre, MVE_VSTRBU8_pre, ... + printT2AddrModeImm8Operand_1(MI, 2, O); + SStream_concat1(O, '!'); + return; + break; + case 35: + // MVE_VLDRDU64_rq, MVE_VSTRD64_rq + printMveAddrModeRQOperand_3(MI, 1, O); + return; + break; + case 36: + // MVE_VLDRHS32_rq, MVE_VLDRHU16_rq, MVE_VLDRHU32_rq, MVE_VSTRH16_rq, MVE... + printMveAddrModeRQOperand_1(MI, 1, O); + return; + break; + case 37: + // MVE_VLDRWU32_rq, MVE_VSTRW32_rq + printMveAddrModeRQOperand_2(MI, 1, O); + return; + break; + case 38: + // MVE_VMOVimmi16, MVE_VMOVimmi32, MVE_VMOVimmi8, MVE_VMVNimmi16, MVE_VMV... + printVMOVModImmOperand(MI, 1, O); + return; + break; + case 39: + // MVE_WLSTP_16, MVE_WLSTP_32, MVE_WLSTP_64, MVE_WLSTP_8, t2BFic, t2WLS + printOperandAddr(MI, Address, 2, O); + break; + case 40: + // SSAT, SSAT16, t2SSAT, t2SSAT16 + printImmPlusOneOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + break; + case 41: + // STLEXD, STREXD + printGPRPairOperand(MI, 1, O); + SStream_concat0(O, ", "); + printAddrMode7Operand(MI, 2, O); + return; + break; + case 42: + // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST2LNd16, VST2LNd32, VST2LNd8, VST2LN... + printNoHashImmediate(MI, 4, O); + break; + case 43: + // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... + printNoHashImmediate(MI, 6, O); + break; + case 44: + // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... + printNoHashImmediate(MI, 8, O); + SStream_concat0(O, "], "); + break; + case 45: + // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... + SStream_concat0(O, "[]}, "); + break; + case 46: + // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... + printNoHashImmediate(MI, 10, O); + SStream_concat0(O, "], "); + printOperand(MI, 1, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 10, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 10, O); + break; + case 47: + // VLD4DUPd16, VLD4DUPd16_UPD, VLD4DUPd32, VLD4DUPd32_UPD, VLD4DUPd8, VLD... + SStream_concat0(O, "[], "); + printOperand(MI, 3, O); + SStream_concat0(O, "[]}, "); + break; + case 48: + // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... + printNoHashImmediate(MI, 12, O); + SStream_concat0(O, "], "); + printOperand(MI, 1, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 12, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 12, O); + SStream_concat0(O, "], "); + printOperand(MI, 3, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 12, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand(MI, 5, O); + printAddrMode6OffsetOperand(MI, 7, O); + return; + break; + case 49: + // VLDRD, VLDRS, VSTRD, VSTRS + printAddrMode5Operand_0(MI, 1, O); + return; + break; + case 50: + // VLDRH, VSTRH + printAddrMode5FP16Operand_0(MI, 1, O); + return; + break; + case 51: + // VST1LNd16, VST1LNd32, VST1LNd8 + printNoHashImmediate(MI, 3, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 52: + // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST3LNd16, VST3LNd32, VST3... + printNoHashImmediate(MI, 5, O); + break; + case 53: + // VST3LNd16_UPD, VST3LNd32_UPD, VST3LNd8_UPD, VST3LNq16_UPD, VST3LNq32_U... + printNoHashImmediate(MI, 7, O); + SStream_concat0(O, "], "); + printOperand(MI, 5, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 7, O); + SStream_concat0(O, "], "); + printOperand(MI, 6, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 7, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand(MI, 1, O); + printAddrMode6OffsetOperand(MI, 3, O); + return; + break; + case 54: + // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... + printOperand(MI, 5, O); + SStream_concat0(O, ", "); + printOperand(MI, 6, O); + break; + case 55: + // VTBL1 + printVectorListOne(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 56: + // VTBL2 + printVectorListTwo(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 57: + // VTBL3 + printVectorListThree(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 58: + // VTBL4 + printVectorListFour(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 59: + // VTBX1 + printVectorListOne(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 60: + // VTBX2 + printVectorListTwo(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 61: + // VTBX3 + printVectorListThree(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 62: + // VTBX4 + printVectorListFour(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 63: + // sysLDMDA_UPD, sysLDMDB_UPD, sysLDMIA_UPD, sysLDMIB_UPD, sysSTMDA_UPD, ... + SStream_concat0(O, " ^"); + return; + break; + case 64: + // t2BFLi, t2BFi + printOperandAddr(MI, Address, 1, O); + return; + break; + case 65: + // t2LDRBpci, t2LDRHpci, t2LDRSBpci, t2LDRSHpci, t2LDRpci, tLDRpci + printThumbLdrLabelOperand(MI, 1, O); + return; + break; + case 66: + // t2LDRBs, t2LDRHs, t2LDRSBs, t2LDRSHs, t2LDRs, t2STRBs, t2STRHs, t2STRs + printT2AddrModeSoRegOperand(MI, 1, O); + return; + break; + case 67: + // t2LDREX + printT2AddrModeImm0_1020s4Operand(MI, 1, O); + return; + break; + case 68: + // t2MRS_M + printMSRMaskOperand(MI, 1, O); + return; + break; + case 69: + // tADDspi, tSUBspi + printThumbS4ImmOperand(MI, 2, O); + return; + break; + case 70: + // tADR + printAdrLabelOperandAddr_2(MI, Address, 1, O); + return; + break; + case 71: + // tASRri, tLSRri + printThumbSRImm(MI, 3, O); + return; + break; + case 72: + // tLDRBi, tSTRBi + printThumbAddrModeImm5S1Operand(MI, 1, O); + return; + break; + case 73: + // tLDRBr, tLDRHr, tLDRSB, tLDRSH, tLDRr, tSTRBr, tSTRHr, tSTRr + printThumbAddrModeRROperand(MI, 1, O); + return; + break; + case 74: + // tLDRHi, tSTRHi + printThumbAddrModeImm5S2Operand(MI, 1, O); + return; + break; + case 75: + // tLDRi, tSTRi + printThumbAddrModeImm5S4Operand(MI, 1, O); + return; + break; + case 76: + // tLDRspi, tSTRspi + printThumbAddrModeSPOperand(MI, 1, O); + return; + break; + } + + // Fragment 5 encoded into 5 bits for 27 unique commands. + switch ((uint32_t)((Bits >> 46) & 31)) { + default: + assert(0 && "Invalid command number."); + case 0: + // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm... + SStream_concat0(O, ", "); + break; + case 1: + // LDRConstPool, RRXi, VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD2LN... + return; + break; + case 2: + // VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_fixed_Asm_8,... + SStream_concat1(O, '!'); + return; + break; + case 3: + // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... + printOperand(MI, 3, O); + return; + break; + case 4: + // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, VBF16MALBQI, VBF16MALTQI, VCMLAv2f32... + printVectorIndex(MI, 4, O); + break; + case 5: + // CDE_CX2DA, CDE_CX3D, CDE_CX3DA, VLD1DUPd16wb_register, VLD1DUPd32wb_re... + printOperand(MI, 4, O); + break; + case 6: + // CDP, t2CDP, t2CDP2 + printCImmediate(MI, 2, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 7: + // MCR, MCRR, VADDD, VDIVD, VMULD, VNMULD, VSUBD, t2MCR, t2MCR2, t2MCRR, ... + printOperand(MI, 2, O); + break; + case 8: + // MRC, t2MRC, t2MRC2 + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 9: + // MVE_VLDRBS16_post, MVE_VLDRBS32_post, MVE_VLDRBU16_post, MVE_VLDRBU32_... + printT2AddrModeImm8OffsetOperand(MI, 3, O); + return; + break; + case 10: + // MVE_VMOV_from_lane_32, MVE_VMOV_from_lane_s16, MVE_VMOV_from_lane_s8, ... + printVectorIndex(MI, 2, O); + return; + break; + case 11: + // MVE_VSHLL_lws16bh, MVE_VSHLL_lws16th, MVE_VSHLL_lwu16bh, MVE_VSHLL_lwu... + SStream_concat0(O, ", #16"); + return; + break; + case 12: + // MVE_VSHLL_lws8bh, MVE_VSHLL_lws8th, MVE_VSHLL_lwu8bh, MVE_VSHLL_lwu8th + SStream_concat0(O, ", #8"); + return; + break; + case 13: + // SSAT, t2SSAT + printShiftImmOperand(MI, 3, O); + return; + break; + case 14: + // SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH, t2SXTB, t2SXTB16, t2SXTH, t2UX... + printRotImmOperand(MI, 2, O); + return; + break; + case 15: + // VCEQzv16i8, VCEQzv2f32, VCEQzv2i32, VCEQzv4f16, VCEQzv4f32, VCEQzv4i16... + SStream_concat0(O, ", #0"); + return; + break; + case 16: + // VFMALDI, VFMALQI, VFMSLDI, VFMSLQI + printVectorIndex(MI, 3, O); + return; + break; + case 17: + // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... + SStream_concat0(O, "]}, "); + break; + case 18: + // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32, VLD4LNd16, VLD4L... + SStream_concat0(O, "], "); + break; + case 19: + // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... + printOperand(MI, 1, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 8, O); + break; + case 20: + // VLD3DUPd16, VLD3DUPd32, VLD3DUPd8, VLD3DUPq16, VLD3DUPq32, VLD3DUPq8 + printAddrMode6Operand(MI, 3, O); + return; + break; + case 21: + // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... + printAddrMode6Operand(MI, 4, O); + break; + case 22: + // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... + printAddrMode6Operand(MI, 5, O); + printAddrMode6OffsetOperand(MI, 7, O); + return; + break; + case 23: + // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... + SStream_concat0(O, "}, "); + printAddrMode6Operand(MI, 1, O); + printAddrMode6OffsetOperand(MI, 3, O); + return; + break; + case 24: + // VST4LNd16_UPD, VST4LNd32_UPD, VST4LNd8_UPD, VST4LNq16_UPD, VST4LNq32_U... + printOperand(MI, 5, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 8, O); + SStream_concat0(O, "], "); + printOperand(MI, 6, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 8, O); + SStream_concat0(O, "], "); + printOperand(MI, 7, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 8, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand(MI, 1, O); + printAddrMode6OffsetOperand(MI, 3, O); + return; + break; + case 25: + // sysLDMDA, sysLDMDB, sysLDMIA, sysLDMIB, sysSTMDA, sysSTMDB, sysSTMIA, ... + SStream_concat0(O, " ^"); + return; + break; + case 26: + // t2MOVsra_flag, t2MOVsrl_flag + SStream_concat0(O, ", #1"); + return; + break; + } + + // Fragment 6 encoded into 6 bits for 38 unique commands. + switch ((uint32_t)((Bits >> 51) & 63)) { + default: + assert(0 && "Invalid command number."); + case 0: + // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCrr, ADDrr, ANDrr, B... + printOperand(MI, 2, O); + break; + case 1: + // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... + printOperand(MI, 4, O); + break; + case 2: + // ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri + printModImmOperand(MI, 2, O); + return; + break; + case 3: + // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, ORRrsi, RSBrsi, RSCrsi, SBCrsi... + printSORegImmOperand(MI, 2, O); + return; + break; + case 4: + // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, CDE_CX2DA, CDE_CX3D, VADDD, VBF16MAL... + return; + break; + case 5: + // BFI, t2BFI + printBitfieldInvMaskImmOperand(MI, 3, O); + return; + break; + case 6: + // CDE_CX3DA, MCR, MCRR, VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f... + SStream_concat0(O, ", "); + break; + case 7: + // CDE_VCX2_vec, CDE_VCX3_vec, MVE_VABAVs16, MVE_VABAVs32, MVE_VABAVs8, M... + printOperand(MI, 3, O); + break; + case 8: + // CDE_VCX3A_fpdp, CDE_VCX3A_fpsp, VST2LNd16_UPD, VST2LNd32_UPD, VST2LNd8... + printOperand(MI, 5, O); + break; + case 9: + // LDCL_OPTION, LDC_OPTION, STCL_OPTION, STC_OPTION, t2LDC2L_OPTION, t2LD... + printCoprocOptionImm(MI, 3, O); + return; + break; + case 10: + // LDCL_POST, LDC_POST, STCL_POST, STC_POST, t2LDC2L_POST, t2LDC2_POST, t... + printPostIdxImm8s4Operand(MI, 3, O); + return; + break; + case 11: + // LDRBT_POST_IMM, LDRBT_POST_REG, LDRB_POST_IMM, LDRB_POST_REG, LDRT_POS... + printAddrMode2OffsetOperand(MI, 3, O); + return; + break; + case 12: + // LDRD, STRD + printAddrMode3Operand_0(MI, 2, O); + return; + break; + case 13: + // LDRD_POST, STRD_POST, t2LDRD_POST, t2STRD_POST + printAddrMode7Operand(MI, 3, O); + break; + case 14: + // LDRD_PRE, STRD_PRE + printAddrMode3Operand_1(MI, 3, O); + SStream_concat1(O, '!'); + return; + break; + case 15: + // LDRHTi, LDRSBTi, LDRSHTi, STRHTi + printPostIdxImm8Operand(MI, 3, O); + return; + break; + case 16: + // LDRHTr, LDRSBTr, LDRSHTr, STRHTr + printPostIdxRegOperand(MI, 3, O); + return; + break; + case 17: + // LDRH_POST, LDRSB_POST, LDRSH_POST, STRH_POST + printAddrMode3OffsetOperand(MI, 3, O); + return; + break; + case 18: + // MCRR2 + printCImmediate(MI, 4, O); + return; + break; + case 19: + // MVE_SQRSHRL, MVE_UQRSHLL + printMveSaturateOp(MI, 5, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + return; + break; + case 20: + // STLEX, STLEXB, STLEXH, STREX, STREXB, STREXH, SWP, SWPB, t2LDAEXD, t2L... + printAddrMode7Operand(MI, 2, O); + return; + break; + case 21: + // VCADDv2f32, VCADDv4f16, VCADDv4f32, VCADDv8f16 + printComplexRotationOp_180_90(MI, 3, O); + return; + break; + case 22: + // VCMLAv2f32, VCMLAv4f16, VCMLAv4f32, VCMLAv8f16 + printComplexRotationOp_90_0(MI, 4, O); + return; + break; + case 23: + // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8... + printAddrMode6Operand(MI, 1, O); + break; + case 24: + // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD + printAddrMode6Operand(MI, 2, O); + printAddrMode6OffsetOperand(MI, 4, O); + return; + break; + case 25: + // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32 + printOperand(MI, 1, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 6, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand(MI, 2, O); + return; + break; + case 26: + // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... + SStream_concat0(O, "]}, "); + printAddrMode6Operand(MI, 3, O); + printAddrMode6OffsetOperand(MI, 5, O); + return; + break; + case 27: + // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... + printAddrMode6OffsetOperand(MI, 6, O); + return; + break; + case 28: + // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16, VLD3LNq32 + SStream_concat0(O, "], "); + printOperand(MI, 2, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 8, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand(MI, 3, O); + return; + break; + case 29: + // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... + printAddrMode6Operand(MI, 4, O); + printAddrMode6OffsetOperand(MI, 6, O); + return; + break; + case 30: + // VST4d16_UPD, VST4d32_UPD, VST4d8_UPD, VST4q16_UPD, VST4q32_UPD, VST4q8... + printOperand(MI, 7, O); + SStream_concat0(O, "}, "); + printAddrMode6Operand(MI, 1, O); + printAddrMode6OffsetOperand(MI, 3, O); + return; + break; + case 31: + // t2ADCrs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORRrs, t2RSBrs... + printT2SOOperand(MI, 2, O); + return; + break; + case 32: + // t2ASRri, t2LSRri + printThumbSRImm(MI, 2, O); + return; + break; + case 33: + // t2BFic, t2CSEL, t2CSINC, t2CSINV, t2CSNEG + printMandatoryPredicateOperand(MI, 3, O); + return; + break; + case 34: + // t2LDRD_PRE, t2STRD_PRE + printT2AddrModeImm8s4Operand_1(MI, 3, O); + SStream_concat1(O, '!'); + return; + break; + case 35: + // t2LDRDi8, t2STRDi8 + printT2AddrModeImm8s4Operand_0(MI, 2, O); + return; + break; + case 36: + // t2STREX + printT2AddrModeImm0_1020s4Operand(MI, 2, O); + return; + break; + case 37: + // tADDrSPi + printThumbS4ImmOperand(MI, 2, O); + return; + break; + } + + // Fragment 7 encoded into 4 bits for 16 unique commands. + switch ((uint32_t)((Bits >> 57) & 15)) { + default: + assert(0 && "Invalid command number."); + case 0: + // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm... + return; + break; + case 1: + // CDE_CX3A, CDE_VCX3A_vec, CDE_VCX3_vec, LDRD_POST, MLA, MLS, MVE_VCADDf... + SStream_concat0(O, ", "); + break; + case 2: + // CDE_CX3DA + printOperand(MI, 5, O); + return; + break; + case 3: + // MCR, t2MCR, t2MCR2 + printCImmediate(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 4: + // MCRR, t2MCRR, t2MCRR2 + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + return; + break; + case 5: + // MVE_VMOV_rr_q, VMULLslsv2i32, VMULLslsv4i16, VMULLsluv2i32, VMULLsluv4... + printVectorIndex(MI, 3, O); + break; + case 6: + // PKHBT, t2PKHBT + printPKHLSLShiftImm(MI, 3, O); + return; + break; + case 7: + // PKHTB, t2PKHTB + printPKHASRShiftImm(MI, 3, O); + return; + break; + case 8: + // SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH, t2SXTAB, t2SXTAB16, t2SX... + printRotImmOperand(MI, 3, O); + return; + break; + case 9: + // USAT, t2USAT + printShiftImmOperand(MI, 3, O); + return; + break; + case 10: + // VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed, VCMLAv8f16... + printComplexRotationOp_90_0(MI, 5, O); + return; + break; + case 11: + // VLD3d16, VLD3d16_UPD, VLD3d32, VLD3d32_UPD, VLD3d8, VLD3d8_UPD, VLD3q1... + SStream_concat0(O, "}, "); + break; + case 12: + // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32, VST2LNd16, VST2L... + SStream_concat1(O, '['); + break; + case 13: + // VMLALslsv2i32, VMLALslsv4i16, VMLALsluv2i32, VMLALsluv4i16, VMLAslfd, ... + printVectorIndex(MI, 4, O); + return; + break; + case 14: + // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD + printAddrMode6OffsetOperand(MI, 3, O); + return; + break; + case 15: + // t2LDRD_POST, t2STRD_POST + printT2AddrModeImm8s4OffsetOperand(MI, 4, O); + return; + break; + } + + switch (MCInst_getOpcode(MI)) { + default: + assert(0 && "Unexpected opcode."); + case ARM_CDE_CX3A: + case ARM_CDE_VCX3A_vec: + case ARM_CDE_VCX3_vec: + case ARM_LDRD_POST: + case ARM_MLA: + case ARM_MLS: + case ARM_MVE_VCADDf16: + case ARM_MVE_VCADDf32: + case ARM_MVE_VCADDi16: + case ARM_MVE_VCADDi32: + case ARM_MVE_VCADDi8: + case ARM_MVE_VCMLAf16: + case ARM_MVE_VCMLAf32: + case ARM_MVE_VCMULf16: + case ARM_MVE_VCMULf32: + case ARM_MVE_VDWDUPu16: + case ARM_MVE_VDWDUPu32: + case ARM_MVE_VDWDUPu8: + case ARM_MVE_VHCADDs16: + case ARM_MVE_VHCADDs32: + case ARM_MVE_VHCADDs8: + case ARM_MVE_VIWDUPu16: + case ARM_MVE_VIWDUPu32: + case ARM_MVE_VIWDUPu8: + case ARM_MVE_VMLALDAVas16: + case ARM_MVE_VMLALDAVas32: + case ARM_MVE_VMLALDAVau16: + case ARM_MVE_VMLALDAVau32: + case ARM_MVE_VMLALDAVaxs16: + case ARM_MVE_VMLALDAVaxs32: + case ARM_MVE_VMLALDAVs16: + case ARM_MVE_VMLALDAVs32: + case ARM_MVE_VMLALDAVu16: + case ARM_MVE_VMLALDAVu32: + case ARM_MVE_VMLALDAVxs16: + case ARM_MVE_VMLALDAVxs32: + case ARM_MVE_VMLSLDAVas16: + case ARM_MVE_VMLSLDAVas32: + case ARM_MVE_VMLSLDAVaxs16: + case ARM_MVE_VMLSLDAVaxs32: + case ARM_MVE_VMLSLDAVs16: + case ARM_MVE_VMLSLDAVs32: + case ARM_MVE_VMLSLDAVxs16: + case ARM_MVE_VMLSLDAVxs32: + case ARM_MVE_VRMLALDAVHas32: + case ARM_MVE_VRMLALDAVHau32: + case ARM_MVE_VRMLALDAVHaxs32: + case ARM_MVE_VRMLALDAVHs32: + case ARM_MVE_VRMLALDAVHu32: + case ARM_MVE_VRMLALDAVHxs32: + case ARM_MVE_VRMLSLDAVHas32: + case ARM_MVE_VRMLSLDAVHaxs32: + case ARM_MVE_VRMLSLDAVHs32: + case ARM_MVE_VRMLSLDAVHxs32: + case ARM_SBFX: + case ARM_SMLABB: + case ARM_SMLABT: + case ARM_SMLAD: + case ARM_SMLADX: + case ARM_SMLALBB: + case ARM_SMLALBT: + case ARM_SMLALD: + case ARM_SMLALDX: + case ARM_SMLALTB: + case ARM_SMLALTT: + case ARM_SMLATB: + case ARM_SMLATT: + case ARM_SMLAWB: + case ARM_SMLAWT: + case ARM_SMLSD: + case ARM_SMLSDX: + case ARM_SMLSLD: + case ARM_SMLSLDX: + case ARM_SMMLA: + case ARM_SMMLAR: + case ARM_SMMLS: + case ARM_SMMLSR: + case ARM_SMULL: + case ARM_STRD_POST: + case ARM_UBFX: + case ARM_UMAAL: + case ARM_UMULL: + case ARM_USADA8: + case ARM_VEXTd16: + case ARM_VEXTd32: + case ARM_VEXTd8: + case ARM_VEXTq16: + case ARM_VEXTq32: + case ARM_VEXTq64: + case ARM_VEXTq8: + case ARM_VLD3d16: + case ARM_VLD3d32: + case ARM_VLD3d8: + case ARM_VLD3q16: + case ARM_VLD3q32: + case ARM_VLD3q8: + case ARM_VMOVRRS: + case ARM_VMOVSRR: + case ARM_VST3d16: + case ARM_VST3d32: + case ARM_VST3d8: + case ARM_VST3q16: + case ARM_VST3q32: + case ARM_VST3q8: + case ARM_t2MLA: + case ARM_t2MLS: + case ARM_t2SBFX: + case ARM_t2SMLABB: + case ARM_t2SMLABT: + case ARM_t2SMLAD: + case ARM_t2SMLADX: + case ARM_t2SMLAL: + case ARM_t2SMLALBB: + case ARM_t2SMLALBT: + case ARM_t2SMLALD: + case ARM_t2SMLALDX: + case ARM_t2SMLALTB: + case ARM_t2SMLALTT: + case ARM_t2SMLATB: + case ARM_t2SMLATT: + case ARM_t2SMLAWB: + case ARM_t2SMLAWT: + case ARM_t2SMLSD: + case ARM_t2SMLSDX: + case ARM_t2SMLSLD: + case ARM_t2SMLSLDX: + case ARM_t2SMMLA: + case ARM_t2SMMLAR: + case ARM_t2SMMLS: + case ARM_t2SMMLSR: + case ARM_t2SMULL: + case ARM_t2STLEXD: + case ARM_t2STREXD: + case ARM_t2UBFX: + case ARM_t2UMAAL: + case ARM_t2UMLAL: + case ARM_t2UMULL: + case ARM_t2USADA8: + switch (MCInst_getOpcode(MI)) { + default: + assert(0 && "Unexpected opcode."); + case ARM_CDE_CX3A: + case ARM_CDE_VCX3A_vec: + case ARM_MVE_VMLALDAVas16: + case ARM_MVE_VMLALDAVas32: + case ARM_MVE_VMLALDAVau16: + case ARM_MVE_VMLALDAVau32: + case ARM_MVE_VMLALDAVaxs16: + case ARM_MVE_VMLALDAVaxs32: + case ARM_MVE_VMLSLDAVas16: + case ARM_MVE_VMLSLDAVas32: + case ARM_MVE_VMLSLDAVaxs16: + case ARM_MVE_VMLSLDAVaxs32: + case ARM_MVE_VRMLALDAVHas32: + case ARM_MVE_VRMLALDAVHau32: + case ARM_MVE_VRMLALDAVHaxs32: + case ARM_MVE_VRMLSLDAVHas32: + case ARM_MVE_VRMLSLDAVHaxs32: + printOperand(MI, 5, O); + break; + case ARM_CDE_VCX3_vec: + case ARM_MVE_VDWDUPu16: + case ARM_MVE_VDWDUPu32: + case ARM_MVE_VDWDUPu8: + case ARM_MVE_VIWDUPu16: + case ARM_MVE_VIWDUPu32: + case ARM_MVE_VIWDUPu8: + printOperand(MI, 4, O); + break; + case ARM_LDRD_POST: + case ARM_STRD_POST: + printAddrMode3OffsetOperand(MI, 4, O); + break; + case ARM_MLA: + case ARM_MLS: + case ARM_MVE_VMLALDAVs16: + case ARM_MVE_VMLALDAVs32: + case ARM_MVE_VMLALDAVu16: + case ARM_MVE_VMLALDAVu32: + case ARM_MVE_VMLALDAVxs16: + case ARM_MVE_VMLALDAVxs32: + case ARM_MVE_VMLSLDAVs16: + case ARM_MVE_VMLSLDAVs32: + case ARM_MVE_VMLSLDAVxs16: + case ARM_MVE_VMLSLDAVxs32: + case ARM_MVE_VRMLALDAVHs32: + case ARM_MVE_VRMLALDAVHu32: + case ARM_MVE_VRMLALDAVHxs32: + case ARM_MVE_VRMLSLDAVHs32: + case ARM_MVE_VRMLSLDAVHxs32: + case ARM_SMLABB: + case ARM_SMLABT: + case ARM_SMLAD: + case ARM_SMLADX: + case ARM_SMLALBB: + case ARM_SMLALBT: + case ARM_SMLALD: + case ARM_SMLALDX: + case ARM_SMLALTB: + case ARM_SMLALTT: + case ARM_SMLATB: + case ARM_SMLATT: + case ARM_SMLAWB: + case ARM_SMLAWT: + case ARM_SMLSD: + case ARM_SMLSDX: + case ARM_SMLSLD: + case ARM_SMLSLDX: + case ARM_SMMLA: + case ARM_SMMLAR: + case ARM_SMMLS: + case ARM_SMMLSR: + case ARM_SMULL: + case ARM_UMAAL: + case ARM_UMULL: + case ARM_USADA8: + case ARM_VEXTd16: + case ARM_VEXTd32: + case ARM_VEXTd8: + case ARM_VEXTq16: + case ARM_VEXTq32: + case ARM_VEXTq64: + case ARM_VEXTq8: + case ARM_VMOVRRS: + case ARM_VMOVSRR: + case ARM_t2MLA: + case ARM_t2MLS: + case ARM_t2SMLABB: + case ARM_t2SMLABT: + case ARM_t2SMLAD: + case ARM_t2SMLADX: + case ARM_t2SMLAL: + case ARM_t2SMLALBB: + case ARM_t2SMLALBT: + case ARM_t2SMLALD: + case ARM_t2SMLALDX: + case ARM_t2SMLALTB: + case ARM_t2SMLALTT: + case ARM_t2SMLATB: + case ARM_t2SMLATT: + case ARM_t2SMLAWB: + case ARM_t2SMLAWT: + case ARM_t2SMLSD: + case ARM_t2SMLSDX: + case ARM_t2SMLSLD: + case ARM_t2SMLSLDX: + case ARM_t2SMMLA: + case ARM_t2SMMLAR: + case ARM_t2SMMLS: + case ARM_t2SMMLSR: + case ARM_t2SMULL: + case ARM_t2UMAAL: + case ARM_t2UMLAL: + case ARM_t2UMULL: + case ARM_t2USADA8: + printOperand(MI, 3, O); + break; + case ARM_MVE_VCADDf16: + case ARM_MVE_VCADDf32: + case ARM_MVE_VCADDi16: + case ARM_MVE_VCADDi32: + case ARM_MVE_VCADDi8: + case ARM_MVE_VHCADDs16: + case ARM_MVE_VHCADDs32: + case ARM_MVE_VHCADDs8: + printComplexRotationOp_180_90(MI, 3, O); + break; + case ARM_MVE_VCMLAf16: + case ARM_MVE_VCMLAf32: + printComplexRotationOp_90_0(MI, 4, O); + break; + case ARM_MVE_VCMULf16: + case ARM_MVE_VCMULf32: + printComplexRotationOp_90_0(MI, 3, O); + break; + case ARM_SBFX: + case ARM_UBFX: + case ARM_t2SBFX: + case ARM_t2UBFX: + printImmPlusOneOperand(MI, 3, O); + break; + case ARM_VLD3d16: + case ARM_VLD3d32: + case ARM_VLD3d8: + case ARM_VLD3q16: + case ARM_VLD3q32: + case ARM_VLD3q8: + printAddrMode6Operand(MI, 3, O); + break; + case ARM_VST3d16: + case ARM_VST3d32: + case ARM_VST3d8: + case ARM_VST3q16: + case ARM_VST3q32: + case ARM_VST3q8: + printAddrMode6Operand(MI, 0, O); + break; + case ARM_t2STLEXD: + case ARM_t2STREXD: + printAddrMode7Operand(MI, 3, O); + break; + } + return; + break; + case ARM_MVE_VMOV_rr_q: + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + printVectorIndex(MI, 4, O); + return; + break; + case ARM_VLD3d16_UPD: + case ARM_VLD3d32_UPD: + case ARM_VLD3d8_UPD: + case ARM_VLD3q16_UPD: + case ARM_VLD3q32_UPD: + case ARM_VLD3q8_UPD: + printAddrMode6Operand(MI, 4, O); + printAddrMode6OffsetOperand(MI, 6, O); + return; + break; + case ARM_VLD4LNd16: + case ARM_VLD4LNd32: + case ARM_VLD4LNd8: + case ARM_VLD4LNq16: + case ARM_VLD4LNq32: + printNoHashImmediate(MI, 10, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand(MI, 4, O); + return; + break; + case ARM_VLD4d16: + case ARM_VLD4d32: + case ARM_VLD4d8: + case ARM_VLD4q16: + case ARM_VLD4q32: + case ARM_VLD4q8: + printOperand(MI, 3, O); + SStream_concat0(O, "}, "); + printAddrMode6Operand(MI, 4, O); + return; + break; + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + case ARM_VLD4d8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + case ARM_VLD4q8_UPD: + printOperand(MI, 3, O); + SStream_concat0(O, "}, "); + printAddrMode6Operand(MI, 5, O); + printAddrMode6OffsetOperand(MI, 7, O); + return; + break; + case ARM_VMULLslsv2i32: + case ARM_VMULLslsv4i16: + case ARM_VMULLsluv2i32: + case ARM_VMULLsluv4i16: + case ARM_VMULslfd: + case ARM_VMULslfq: + case ARM_VMULslhd: + case ARM_VMULslhq: + case ARM_VMULslv2i32: + case ARM_VMULslv4i16: + case ARM_VMULslv4i32: + case ARM_VMULslv8i16: + case ARM_VQDMULHslv2i32: + case ARM_VQDMULHslv4i16: + case ARM_VQDMULHslv4i32: + case ARM_VQDMULHslv8i16: + case ARM_VQDMULLslv2i32: + case ARM_VQDMULLslv4i16: + case ARM_VQRDMULHslv2i32: + case ARM_VQRDMULHslv4i16: + case ARM_VQRDMULHslv4i32: + case ARM_VQRDMULHslv8i16: + return; + break; + case ARM_VST2LNd16: + case ARM_VST2LNd32: + case ARM_VST2LNd8: + case ARM_VST2LNq16: + case ARM_VST2LNq32: + printNoHashImmediate(MI, 4, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case ARM_VST2LNd16_UPD: + case ARM_VST2LNd32_UPD: + case ARM_VST2LNd8_UPD: + case ARM_VST2LNq16_UPD: + case ARM_VST2LNq32_UPD: + printNoHashImmediate(MI, 6, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand(MI, 1, O); + printAddrMode6OffsetOperand(MI, 3, O); + return; + break; + case ARM_VST3LNd16: + case ARM_VST3LNd32: + case ARM_VST3LNd8: + case ARM_VST3LNq16: + case ARM_VST3LNq32: + printNoHashImmediate(MI, 5, O); + SStream_concat0(O, "], "); + printOperand(MI, 4, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 5, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case ARM_VST4LNd16: + case ARM_VST4LNd32: + case ARM_VST4LNd8: + case ARM_VST4LNq16: + case ARM_VST4LNq32: + printNoHashImmediate(MI, 6, O); + SStream_concat0(O, "], "); + printOperand(MI, 4, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 6, O); + SStream_concat0(O, "], "); + printOperand(MI, 5, O); + SStream_concat1(O, '['); + printNoHashImmediate(MI, 6, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case ARM_VST4d16: + case ARM_VST4d32: + case ARM_VST4d8: + case ARM_VST4q16: + case ARM_VST4q32: + case ARM_VST4q8: + printOperand(MI, 5, O); + SStream_concat0(O, "}, "); + printAddrMode6Operand(MI, 0, O); + return; + break; + } +} + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +const char *getRegisterName(unsigned RegNo, unsigned AltIdx) +{ +#ifndef CAPSTONE_DIET + assert(RegNo && RegNo < 296 && "Invalid register number!"); + + static const char AsmStrsNoRegAltName[] = { + /* 0 */ "D4_D6_D8_D10\0" + /* 13 */ "D7_D8_D9_D10\0" + /* 26 */ "Q7_Q8_Q9_Q10\0" + /* 39 */ "d10\0" + /* 43 */ "q10\0" + /* 47 */ "r10\0" + /* 51 */ "s10\0" + /* 55 */ "D14_D16_D18_D20\0" + /* 71 */ "D17_D18_D19_D20\0" + /* 87 */ "d20\0" + /* 91 */ "s20\0" + /* 95 */ "D24_D26_D28_D30\0" + /* 111 */ "D27_D28_D29_D30\0" + /* 127 */ "d30\0" + /* 131 */ "s30\0" + /* 135 */ "d0\0" + /* 138 */ "p0\0" + /* 141 */ "q0\0" + /* 144 */ "mvfr0\0" + /* 150 */ "s0\0" + /* 153 */ "D9_D10_D11\0" + /* 164 */ "D5_D7_D9_D11\0" + /* 177 */ "Q8_Q9_Q10_Q11\0" + /* 191 */ "R10_R11\0" + /* 199 */ "d11\0" + /* 203 */ "q11\0" + /* 207 */ "r11\0" + /* 211 */ "s11\0" + /* 215 */ "D19_D20_D21\0" + /* 227 */ "D15_D17_D19_D21\0" + /* 243 */ "d21\0" + /* 247 */ "s21\0" + /* 251 */ "D29_D30_D31\0" + /* 263 */ "D25_D27_D29_D31\0" + /* 279 */ "d31\0" + /* 283 */ "s31\0" + /* 287 */ "Q0_Q1\0" + /* 293 */ "R0_R1\0" + /* 299 */ "d1\0" + /* 302 */ "q1\0" + /* 305 */ "mvfr1\0" + /* 311 */ "s1\0" + /* 314 */ "D6_D8_D10_D12\0" + /* 328 */ "D9_D10_D11_D12\0" + /* 343 */ "Q9_Q10_Q11_Q12\0" + /* 358 */ "d12\0" + /* 362 */ "q12\0" + /* 366 */ "r12\0" + /* 370 */ "s12\0" + /* 374 */ "D16_D18_D20_D22\0" + /* 390 */ "D19_D20_D21_D22\0" + /* 406 */ "d22\0" + /* 410 */ "s22\0" + /* 414 */ "D0_D2\0" + /* 420 */ "D0_D1_D2\0" + /* 429 */ "Q1_Q2\0" + /* 435 */ "d2\0" + /* 438 */ "q2\0" + /* 441 */ "mvfr2\0" + /* 447 */ "s2\0" + /* 450 */ "fpinst2\0" + /* 458 */ "D7_D9_D11_D13\0" + /* 472 */ "D11_D12_D13\0" + /* 484 */ "Q10_Q11_Q12_Q13\0" + /* 500 */ "d13\0" + /* 504 */ "q13\0" + /* 508 */ "s13\0" + /* 512 */ "D17_D19_D21_D23\0" + /* 528 */ "D21_D22_D23\0" + /* 540 */ "d23\0" + /* 544 */ "s23\0" + /* 548 */ "D1_D3\0" + /* 554 */ "D1_D2_D3\0" + /* 563 */ "Q0_Q1_Q2_Q3\0" + /* 575 */ "R2_R3\0" + /* 581 */ "d3\0" + /* 584 */ "q3\0" + /* 587 */ "r3\0" + /* 590 */ "s3\0" + /* 593 */ "D8_D10_D12_D14\0" + /* 608 */ "D11_D12_D13_D14\0" + /* 624 */ "Q11_Q12_Q13_Q14\0" + /* 640 */ "d14\0" + /* 644 */ "q14\0" + /* 648 */ "s14\0" + /* 652 */ "D18_D20_D22_D24\0" + /* 668 */ "D21_D22_D23_D24\0" + /* 684 */ "d24\0" + /* 688 */ "s24\0" + /* 692 */ "D0_D2_D4\0" + /* 701 */ "D1_D2_D3_D4\0" + /* 713 */ "Q1_Q2_Q3_Q4\0" + /* 725 */ "d4\0" + /* 728 */ "q4\0" + /* 731 */ "r4\0" + /* 734 */ "s4\0" + /* 737 */ "D9_D11_D13_D15\0" + /* 752 */ "D13_D14_D15\0" + /* 764 */ "Q12_Q13_Q14_Q15\0" + /* 780 */ "d15\0" + /* 784 */ "q15\0" + /* 788 */ "s15\0" + /* 792 */ "D19_D21_D23_D25\0" + /* 808 */ "D23_D24_D25\0" + /* 820 */ "d25\0" + /* 824 */ "s25\0" + /* 828 */ "D1_D3_D5\0" + /* 837 */ "D3_D4_D5\0" + /* 846 */ "Q2_Q3_Q4_Q5\0" + /* 858 */ "R4_R5\0" + /* 864 */ "d5\0" + /* 867 */ "q5\0" + /* 870 */ "r5\0" + /* 873 */ "s5\0" + /* 876 */ "D10_D12_D14_D16\0" + /* 892 */ "D13_D14_D15_D16\0" + /* 908 */ "d16\0" + /* 912 */ "s16\0" + /* 916 */ "D20_D22_D24_D26\0" + /* 932 */ "D23_D24_D25_D26\0" + /* 948 */ "d26\0" + /* 952 */ "s26\0" + /* 956 */ "D0_D2_D4_D6\0" + /* 968 */ "D3_D4_D5_D6\0" + /* 980 */ "Q3_Q4_Q5_Q6\0" + /* 992 */ "d6\0" + /* 995 */ "q6\0" + /* 998 */ "r6\0" + /* 1001 */ "s6\0" + /* 1004 */ "D11_D13_D15_D17\0" + /* 1020 */ "D15_D16_D17\0" + /* 1032 */ "d17\0" + /* 1036 */ "s17\0" + /* 1040 */ "D21_D23_D25_D27\0" + /* 1056 */ "D25_D26_D27\0" + /* 1068 */ "d27\0" + /* 1072 */ "s27\0" + /* 1076 */ "D1_D3_D5_D7\0" + /* 1088 */ "D5_D6_D7\0" + /* 1097 */ "Q4_Q5_Q6_Q7\0" + /* 1109 */ "R6_R7\0" + /* 1115 */ "d7\0" + /* 1118 */ "q7\0" + /* 1121 */ "r7\0" + /* 1124 */ "s7\0" + /* 1127 */ "D12_D14_D16_D18\0" + /* 1143 */ "D15_D16_D17_D18\0" + /* 1159 */ "d18\0" + /* 1163 */ "s18\0" + /* 1167 */ "D22_D24_D26_D28\0" + /* 1183 */ "D25_D26_D27_D28\0" + /* 1199 */ "d28\0" + /* 1203 */ "s28\0" + /* 1207 */ "D2_D4_D6_D8\0" + /* 1219 */ "D5_D6_D7_D8\0" + /* 1231 */ "Q5_Q6_Q7_Q8\0" + /* 1243 */ "d8\0" + /* 1246 */ "q8\0" + /* 1249 */ "r8\0" + /* 1252 */ "s8\0" + /* 1255 */ "D13_D15_D17_D19\0" + /* 1271 */ "D17_D18_D19\0" + /* 1283 */ "d19\0" + /* 1287 */ "s19\0" + /* 1291 */ "D23_D25_D27_D29\0" + /* 1307 */ "D27_D28_D29\0" + /* 1319 */ "d29\0" + /* 1323 */ "s29\0" + /* 1327 */ "D3_D5_D7_D9\0" + /* 1339 */ "D7_D8_D9\0" + /* 1348 */ "Q6_Q7_Q8_Q9\0" + /* 1360 */ "R8_R9\0" + /* 1366 */ "d9\0" + /* 1369 */ "q9\0" + /* 1372 */ "r9\0" + /* 1375 */ "s9\0" + /* 1378 */ "R12_SP\0" + /* 1385 */ "pc\0" + /* 1388 */ "fpscr_nzcvqc\0" + /* 1401 */ "fpexc\0" + /* 1407 */ "fpsid\0" + /* 1413 */ "ra_auth_code\0" + /* 1426 */ "itstate\0" + /* 1434 */ "sp\0" + /* 1437 */ "fpscr\0" + /* 1443 */ "lr\0" + /* 1446 */ "vpr\0" + /* 1450 */ "apsr\0" + /* 1455 */ "cpsr\0" + /* 1460 */ "spsr\0" + /* 1465 */ "zr\0" + /* 1468 */ "fpcxtns\0" + /* 1476 */ "fpcxts\0" + /* 1483 */ "fpinst\0" + /* 1490 */ "fpscr_nzcv\0" + /* 1501 */ "apsr_nzcv\0" + }; + static const uint16_t RegAsmOffsetNoRegAltName[] = { + 1450, 1501, 1455, 1468, 1476, 1401, 1483, 1437, 1490, 1388, + 1407, 1426, 1443, 1385, 1413, 1434, 1460, 1446, 1465, 135, + 299, 435, 581, 725, 864, 992, 1115, 1243, 1366, 39, + 199, 358, 500, 640, 780, 908, 1032, 1159, 1283, 87, + 243, 406, 540, 684, 820, 948, 1068, 1199, 1319, 127, + 279, 450, 144, 305, 441, 138, 141, 302, 438, 584, + 728, 867, 995, 1118, 1246, 1369, 43, 203, 362, 504, + 644, 784, 147, 308, 444, 587, 731, 870, 998, 1121, + 1249, 1372, 47, 207, 366, 150, 311, 447, 590, 734, + 873, 1001, 1124, 1252, 1375, 51, 211, 370, 508, 648, + 788, 912, 1036, 1163, 1287, 91, 247, 410, 544, 688, + 824, 952, 1072, 1203, 1323, 131, 283, 414, 548, 695, + 831, 962, 1082, 1213, 1333, 6, 170, 320, 464, 600, + 744, 884, 1012, 1135, 1263, 63, 235, 382, 520, 660, + 800, 924, 1048, 1175, 1299, 103, 271, 287, 429, 569, + 719, 852, 986, 1103, 1237, 1354, 32, 183, 350, 492, + 632, 772, 563, 713, 846, 980, 1097, 1231, 1348, 26, + 177, 343, 484, 624, 764, 293, 575, 858, 1109, 1360, + 191, 1378, 420, 554, 704, 837, 971, 1088, 1222, 1339, + 16, 153, 331, 472, 612, 752, 896, 1020, 1147, 1271, + 75, 215, 394, 528, 672, 808, 936, 1056, 1187, 1307, + 115, 251, 692, 828, 959, 1079, 1210, 1330, 3, 167, + 317, 461, 596, 740, 880, 1008, 1131, 1259, 59, 231, + 378, 516, 656, 796, 920, 1044, 1171, 1295, 99, 267, + 956, 1076, 1207, 1327, 0, 164, 314, 458, 593, 737, + 876, 1004, 1127, 1255, 55, 227, 374, 512, 652, 792, + 916, 1040, 1167, 1291, 95, 263, 423, 707, 974, 1225, + 19, 335, 616, 900, 1151, 79, 398, 676, 940, 1191, + 119, 701, 968, 1219, 13, 328, 608, 892, 1143, 71, + 390, 668, 932, 1183, 111, + }; + + static const char AsmStrsRegNamesRaw[] = { /* 0 */ "r13\0" + /* 4 */ "r14\0" + /* 8 */ "r15\0" }; + static const uint8_t RegAsmOffsetRegNamesRaw[] = { + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 8, 3, 0, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + }; + + switch (AltIdx) { + default: + assert(0 && "Invalid register alt name index!"); + case ARM_NoRegAltName: + assert(*(AsmStrsNoRegAltName + + RegAsmOffsetNoRegAltName[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrsNoRegAltName + + RegAsmOffsetNoRegAltName[RegNo - 1]; + case ARM_RegNamesRaw: + if (!*(AsmStrsRegNamesRaw + RegAsmOffsetRegNamesRaw[RegNo - 1])) + return getRegisterName(RegNo, ARM_NoRegAltName); + return AsmStrsRegNamesRaw + RegAsmOffsetRegNamesRaw[RegNo - 1]; + } +#else + return NULL; +#endif // CAPSTONE_DIET +} +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) +{ +#ifndef CAPSTONE_DIET + static const PatternsForOpcode OpToPatterns[] = { + { ARM_DSB, 0, 3 }, + { ARM_HINT, 3, 9 }, + { ARM_MVE_VMLADAVas16, 12, 1 }, + { ARM_MVE_VMLADAVas32, 13, 1 }, + { ARM_MVE_VMLADAVas8, 14, 1 }, + { ARM_MVE_VMLADAVau16, 15, 1 }, + { ARM_MVE_VMLADAVau32, 16, 1 }, + { ARM_MVE_VMLADAVau8, 17, 1 }, + { ARM_MVE_VMLADAVs16, 18, 1 }, + { ARM_MVE_VMLADAVs32, 19, 1 }, + { ARM_MVE_VMLADAVs8, 20, 1 }, + { ARM_MVE_VMLADAVu16, 21, 1 }, + { ARM_MVE_VMLADAVu32, 22, 1 }, + { ARM_MVE_VMLADAVu8, 23, 1 }, + { ARM_MVE_VMLALDAVas16, 24, 1 }, + { ARM_MVE_VMLALDAVas32, 25, 1 }, + { ARM_MVE_VMLALDAVau16, 26, 1 }, + { ARM_MVE_VMLALDAVau32, 27, 1 }, + { ARM_MVE_VMLALDAVs16, 28, 1 }, + { ARM_MVE_VMLALDAVs32, 29, 1 }, + { ARM_MVE_VMLALDAVu16, 30, 1 }, + { ARM_MVE_VMLALDAVu32, 31, 1 }, + { ARM_MVE_VORR, 32, 1 }, + { ARM_MVE_VRMLALDAVHas32, 33, 1 }, + { ARM_MVE_VRMLALDAVHau32, 34, 1 }, + { ARM_MVE_VRMLALDAVHs32, 35, 1 }, + { ARM_MVE_VRMLALDAVHu32, 36, 1 }, + { ARM_t2CSINC, 37, 2 }, + { ARM_t2CSINV, 39, 2 }, + { ARM_t2CSNEG, 41, 1 }, + { ARM_t2DSB, 42, 3 }, + { ARM_t2HINT, 45, 13 }, + { ARM_t2SUBS_PC_LR, 58, 1 }, + { ARM_tHINT, 59, 6 }, + { 0 }, + }; + + static const AliasPattern Patterns[] = { + // ARM_DSB - 0 + { 0, 0, 1, 3 }, + { 5, 3, 1, 3 }, + { 11, 6, 1, 3 }, + // ARM_HINT - 3 + { 15, 9, 3, 3 }, + { 23, 12, 3, 3 }, + { 33, 15, 3, 3 }, + { 41, 18, 3, 3 }, + { 49, 21, 3, 3 }, + { 57, 24, 3, 3 }, + { 66, 27, 3, 3 }, + { 74, 30, 3, 3 }, + { 83, 33, 3, 4 }, + // ARM_MVE_VMLADAVas16 - 12 + { 94, 37, 7, 6 }, + // ARM_MVE_VMLADAVas32 - 13 + { 120, 43, 7, 6 }, + // ARM_MVE_VMLADAVas8 - 14 + { 146, 49, 7, 6 }, + // ARM_MVE_VMLADAVau16 - 15 + { 171, 55, 7, 6 }, + // ARM_MVE_VMLADAVau32 - 16 + { 197, 61, 7, 6 }, + // ARM_MVE_VMLADAVau8 - 17 + { 223, 67, 7, 6 }, + // ARM_MVE_VMLADAVs16 - 18 + { 248, 73, 6, 5 }, + // ARM_MVE_VMLADAVs32 - 19 + { 273, 78, 6, 5 }, + // ARM_MVE_VMLADAVs8 - 20 + { 298, 83, 6, 5 }, + // ARM_MVE_VMLADAVu16 - 21 + { 322, 88, 6, 5 }, + // ARM_MVE_VMLADAVu32 - 22 + { 347, 93, 6, 5 }, + // ARM_MVE_VMLADAVu8 - 23 + { 372, 98, 6, 5 }, + // ARM_MVE_VMLALDAVas16 - 24 + { 396, 103, 9, 8 }, + // ARM_MVE_VMLALDAVas32 - 25 + { 427, 111, 9, 8 }, + // ARM_MVE_VMLALDAVau16 - 26 + { 458, 119, 9, 8 }, + // ARM_MVE_VMLALDAVau32 - 27 + { 489, 127, 9, 8 }, + // ARM_MVE_VMLALDAVs16 - 28 + { 520, 135, 7, 6 }, + // ARM_MVE_VMLALDAVs32 - 29 + { 550, 141, 7, 6 }, + // ARM_MVE_VMLALDAVu16 - 30 + { 580, 147, 7, 6 }, + // ARM_MVE_VMLALDAVu32 - 31 + { 610, 153, 7, 6 }, + // ARM_MVE_VORR - 32 + { 640, 159, 7, 5 }, + // ARM_MVE_VRMLALDAVHas32 - 33 + { 656, 164, 9, 8 }, + // ARM_MVE_VRMLALDAVHau32 - 34 + { 689, 172, 9, 8 }, + // ARM_MVE_VRMLALDAVHs32 - 35 + { 722, 180, 7, 6 }, + // ARM_MVE_VRMLALDAVHu32 - 36 + { 754, 186, 7, 6 }, + // ARM_t2CSINC - 37 + { 786, 192, 4, 4 }, + { 800, 196, 4, 4 }, + // ARM_t2CSINV - 39 + { 818, 200, 4, 4 }, + { 833, 204, 4, 4 }, + // ARM_t2CSNEG - 41 + { 851, 208, 4, 4 }, + // ARM_t2DSB - 42 + { 0, 212, 3, 6 }, + { 5, 218, 3, 6 }, + { 869, 224, 3, 2 }, + // ARM_t2HINT - 45 + { 877, 226, 3, 3 }, + { 887, 229, 3, 3 }, + { 899, 232, 3, 3 }, + { 909, 235, 3, 3 }, + { 919, 238, 3, 3 }, + { 929, 241, 3, 4 }, + { 940, 245, 3, 4 }, + { 74, 249, 3, 3 }, + { 950, 252, 3, 3 }, + { 971, 255, 3, 3 }, + { 979, 258, 3, 3 }, + { 997, 261, 3, 3 }, + { 83, 264, 3, 5 }, + // ARM_t2SUBS_PC_LR - 58 + { 1015, 269, 3, 4 }, + // ARM_tHINT - 59 + { 15, 273, 3, 3 }, + { 23, 276, 3, 3 }, + { 33, 279, 3, 3 }, + { 41, 282, 3, 3 }, + { 49, 285, 3, 3 }, + { 57, 288, 3, 4 }, + { 0 }, + }; + + static const AliasPatternCond Conds[] = { + // (DSB 0) - 0 + { AliasPatternCond_K_Imm, (uint32_t)0 }, + { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureDB }, + // (DSB 4) - 3 + { AliasPatternCond_K_Imm, (uint32_t)4 }, + { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureDB }, + // (DSB 12) - 6 + { AliasPatternCond_K_Imm, (uint32_t)12 }, + { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureDFB }, + // (HINT 0, pred:$p) - 9 + { AliasPatternCond_K_Imm, (uint32_t)0 }, + { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV6KOps }, + // (HINT 1, pred:$p) - 12 + { AliasPatternCond_K_Imm, (uint32_t)1 }, + { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV6KOps }, + // (HINT 2, pred:$p) - 15 + { AliasPatternCond_K_Imm, (uint32_t)2 }, + { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV6KOps }, + // (HINT 3, pred:$p) - 18 + { AliasPatternCond_K_Imm, (uint32_t)3 }, + { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV6KOps }, + // (HINT 4, pred:$p) - 21 + { AliasPatternCond_K_Imm, (uint32_t)4 }, + { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV6KOps }, + // (HINT 5, pred:$p) - 24 + { AliasPatternCond_K_Imm, (uint32_t)5 }, + { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV8Ops }, + // (HINT 16, pred:$p) - 27 + { AliasPatternCond_K_Imm, (uint32_t)16 }, + { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureRAS }, + // (HINT 20, pred:$p) - 30 + { AliasPatternCond_K_Imm, (uint32_t)20 }, + { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV6KOps }, + // (HINT 22, pred:$p) - 33 + { AliasPatternCond_K_Imm, (uint32_t)22 }, + { AliasPatternCond_K_NegFeature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV8Ops }, + { AliasPatternCond_K_Feature, ARM_FeatureCLRBHB }, + // (MVE_VMLADAVas16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 37 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLADAVas32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 43 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLADAVas8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 49 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLADAVau16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 55 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLADAVau32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 61 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLADAVau8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 67 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLADAVs16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 73 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLADAVs32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 78 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLADAVs8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 83 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLADAVu16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 88 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLADAVu32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 93 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLADAVu8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 98 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLALDAVas16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 103 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLALDAVas32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 111 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLALDAVau16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 119 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLALDAVau32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 127 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLALDAVs16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 135 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLALDAVs32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 141 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLALDAVu16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 147 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VMLALDAVu32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 153 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VORR MQPR:$Qd, MQPR:$Qm, MQPR:$Qm, vpred_r:$vp) - 159 + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_TiedReg, 1 }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VRMLALDAVHas32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 164 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VRMLALDAVHau32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 172 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_Ignore, 0 }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VRMLALDAVHs32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 180 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (MVE_VRMLALDAVHu32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 186 + { AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID }, + { AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_MQPRRegClassID }, + { AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + // (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond) - 192 + { AliasPatternCond_K_RegClass, ARM_rGPRRegClassID }, + { AliasPatternCond_K_Reg, ARM_ZR }, + { AliasPatternCond_K_Reg, ARM_ZR }, + { AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps }, + // (t2CSINC rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond) - 196 + { AliasPatternCond_K_RegClass, ARM_rGPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID }, + { AliasPatternCond_K_TiedReg, 1 }, + { AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps }, + // (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond) - 200 + { AliasPatternCond_K_RegClass, ARM_rGPRRegClassID }, + { AliasPatternCond_K_Reg, ARM_ZR }, + { AliasPatternCond_K_Reg, ARM_ZR }, + { AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps }, + // (t2CSINV rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond) - 204 + { AliasPatternCond_K_RegClass, ARM_rGPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID }, + { AliasPatternCond_K_TiedReg, 1 }, + { AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps }, + // (t2CSNEG rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond) - 208 + { AliasPatternCond_K_RegClass, ARM_rGPRRegClassID }, + { AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID }, + { AliasPatternCond_K_TiedReg, 1 }, + { AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps }, + // (t2DSB 0, 14, 0) - 212 + { AliasPatternCond_K_Imm, (uint32_t)0 }, + { AliasPatternCond_K_Imm, (uint32_t)14 }, + { AliasPatternCond_K_Imm, (uint32_t)0 }, + { AliasPatternCond_K_Feature, ARM_FeatureDB }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + // (t2DSB 4, 14, 0) - 218 + { AliasPatternCond_K_Imm, (uint32_t)4 }, + { AliasPatternCond_K_Imm, (uint32_t)14 }, + { AliasPatternCond_K_Imm, (uint32_t)0 }, + { AliasPatternCond_K_Feature, ARM_FeatureDB }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + // (t2DSB 12, pred:$p) - 224 + { AliasPatternCond_K_Imm, (uint32_t)12 }, + { AliasPatternCond_K_Feature, ARM_FeatureDFB }, + // (t2HINT 0, pred:$p) - 226 + { AliasPatternCond_K_Imm, (uint32_t)0 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + // (t2HINT 1, pred:$p) - 229 + { AliasPatternCond_K_Imm, (uint32_t)1 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + // (t2HINT 2, pred:$p) - 232 + { AliasPatternCond_K_Imm, (uint32_t)2 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + // (t2HINT 3, pred:$p) - 235 + { AliasPatternCond_K_Imm, (uint32_t)3 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + // (t2HINT 4, pred:$p) - 238 + { AliasPatternCond_K_Imm, (uint32_t)4 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + // (t2HINT 5, pred:$p) - 241 + { AliasPatternCond_K_Imm, (uint32_t)5 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + { AliasPatternCond_K_Feature, ARM_HasV8Ops }, + // (t2HINT 16, pred:$p) - 245 + { AliasPatternCond_K_Imm, (uint32_t)16 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + { AliasPatternCond_K_Feature, ARM_FeatureRAS }, + // (t2HINT 20, pred:$p) - 249 + { AliasPatternCond_K_Imm, (uint32_t)20 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + // (t2HINT 13, pred:$p) - 252 + { AliasPatternCond_K_Imm, (uint32_t)13 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + // (t2HINT 15, pred:$p) - 255 + { AliasPatternCond_K_Imm, (uint32_t)15 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + // (t2HINT 29, pred:$p) - 258 + { AliasPatternCond_K_Imm, (uint32_t)29 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + // (t2HINT 45, pred:$p) - 261 + { AliasPatternCond_K_Imm, (uint32_t)45 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + // (t2HINT 22, pred:$p) - 264 + { AliasPatternCond_K_Imm, (uint32_t)22 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + { AliasPatternCond_K_Feature, ARM_HasV8Ops }, + { AliasPatternCond_K_Feature, ARM_FeatureCLRBHB }, + // (t2SUBS_PC_LR 0, pred:$p) - 269 + { AliasPatternCond_K_Imm, (uint32_t)0 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + { AliasPatternCond_K_Feature, ARM_FeatureVirtualization }, + // (tHINT 0, pred:$p) - 273 + { AliasPatternCond_K_Imm, (uint32_t)0 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV6MOps }, + // (tHINT 1, pred:$p) - 276 + { AliasPatternCond_K_Imm, (uint32_t)1 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV6MOps }, + // (tHINT 2, pred:$p) - 279 + { AliasPatternCond_K_Imm, (uint32_t)2 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV6MOps }, + // (tHINT 3, pred:$p) - 282 + { AliasPatternCond_K_Imm, (uint32_t)3 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV6MOps }, + // (tHINT 4, pred:$p) - 285 + { AliasPatternCond_K_Imm, (uint32_t)4 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_HasV6MOps }, + // (tHINT 5, pred:$p) - 288 + { AliasPatternCond_K_Imm, (uint32_t)5 }, + { AliasPatternCond_K_Feature, ARM_ModeThumb }, + { AliasPatternCond_K_Feature, ARM_FeatureThumb2 }, + { AliasPatternCond_K_Feature, ARM_HasV8Ops }, + { 0 }, + }; + + static const char AsmStrings[] = + /* 0 */ + "ssbb\0" + /* 5 */ "pssbb\0" + /* 11 */ "dfb\0" + /* 15 */ "nop$\xFF\x02\x01\0" + /* 23 */ "yield$\xFF\x02\x01\0" + /* 33 */ "wfe$\xFF\x02\x01\0" + /* 41 */ "wfi$\xFF\x02\x01\0" + /* 49 */ "sev$\xFF\x02\x01\0" + /* 57 */ "sevl$\xFF\x02\x01\0" + /* 66 */ "esb$\xFF\x02\x01\0" + /* 74 */ "csdb$\xFF\x02\x01\0" + /* 83 */ "clrbhb$\xFF\x02\x01\0" + /* 94 */ "vmlava$\xFF\x05\x02.s16 $\x01, $\x03, $\x04\0" + /* 120 */ "vmlava$\xFF\x05\x02.s32 $\x01, $\x03, $\x04\0" + /* 146 */ "vmlava$\xFF\x05\x02.s8 $\x01, $\x03, $\x04\0" + /* 171 */ "vmlava$\xFF\x05\x02.u16 $\x01, $\x03, $\x04\0" + /* 197 */ "vmlava$\xFF\x05\x02.u32 $\x01, $\x03, $\x04\0" + /* 223 */ "vmlava$\xFF\x05\x02.u8 $\x01, $\x03, $\x04\0" + /* 248 */ "vmlav$\xFF\x04\x02.s16 $\x01, $\x02, $\x03\0" + /* 273 */ "vmlav$\xFF\x04\x02.s32 $\x01, $\x02, $\x03\0" + /* 298 */ "vmlav$\xFF\x04\x02.s8 $\x01, $\x02, $\x03\0" + /* 322 */ "vmlav$\xFF\x04\x02.u16 $\x01, $\x02, $\x03\0" + /* 347 */ "vmlav$\xFF\x04\x02.u32 $\x01, $\x02, $\x03\0" + /* 372 */ "vmlav$\xFF\x04\x02.u8 $\x01, $\x02, $\x03\0" + /* 396 */ "vmlalva$\xFF\x07\x02.s16 $\x01, $\x02, $\x05, $\x06\0" + /* 427 */ "vmlalva$\xFF\x07\x02.s32 $\x01, $\x02, $\x05, $\x06\0" + /* 458 */ "vmlalva$\xFF\x07\x02.u16 $\x01, $\x02, $\x05, $\x06\0" + /* 489 */ "vmlalva$\xFF\x07\x02.u32 $\x01, $\x02, $\x05, $\x06\0" + /* 520 */ "vmlalv$\xFF\x05\x02.s16 $\x01, $\x02, $\x03, $\x04\0" + /* 550 */ "vmlalv$\xFF\x05\x02.s32 $\x01, $\x02, $\x03, $\x04\0" + /* 580 */ "vmlalv$\xFF\x05\x02.u16 $\x01, $\x02, $\x03, $\x04\0" + /* 610 */ "vmlalv$\xFF\x05\x02.u32 $\x01, $\x02, $\x03, $\x04\0" + /* 640 */ "vmov$\xFF\x04\x02 $\x01, $\x02\0" + /* 656 */ "vrmlalvha$\xFF\x07\x02.s32 $\x01, $\x02, $\x05, $\x06\0" + /* 689 */ "vrmlalvha$\xFF\x07\x02.u32 $\x01, $\x02, $\x05, $\x06\0" + /* 722 */ "vrmlalvh$\xFF\x05\x02.s32 $\x01, $\x02, $\x03, $\x04\0" + /* 754 */ "vrmlalvh$\xFF\x05\x02.u32 $\x01, $\x02, $\x03, $\x04\0" + /* 786 */ "cset $\x01, $\xFF\x04\x03\0" + /* 800 */ "cinc $\x01, $\x02, $\xFF\x04\x03\0" + /* 818 */ "csetm $\x01, $\xFF\x04\x03\0" + /* 833 */ "cinv $\x01, $\x02, $\xFF\x04\x03\0" + /* 851 */ "cneg $\x01, $\x02, $\xFF\x04\x03\0" + /* 869 */ "dfb$\xFF\x02\x01\0" + /* 877 */ "nop$\xFF\x02\x01.w\0" + /* 887 */ "yield$\xFF\x02\x01.w\0" + /* 899 */ "wfe$\xFF\x02\x01.w\0" + /* 909 */ "wfi$\xFF\x02\x01.w\0" + /* 919 */ "sev$\xFF\x02\x01.w\0" + /* 929 */ "sevl$\xFF\x02\x01.w\0" + /* 940 */ "esb$\xFF\x02\x01.w\0" + /* 950 */ "pacbti$\xFF\x02\x01 r12,lr,sp\0" + /* 971 */ "bti$\xFF\x02\x01\0" + /* 979 */ "pac$\xFF\x02\x01 r12,lr,sp\0" + /* 997 */ "aut$\xFF\x02\x01 r12,lr,sp\0" + /* 1015 */ "eret$\xFF\x02\x01\0"; + +#ifndef NDEBUG + //static struct SortCheck { + // SortCheck(ArrayRef OpToPatterns) { + // assert(std::is_sorted( + // OpToPatterns.begin(), OpToPatterns.end(), + // [](const PatternsForOpcode &L, const //PatternsForOpcode &R) { + // return L.Opcode < R.Opcode; + // }) && + // "tablegen failed to sort opcode patterns"); + // } + //} sortCheckVar(OpToPatterns); +#endif + + AliasMatchingData M = { + OpToPatterns, Patterns, Conds, AsmStrings, NULL, + }; + const char *AsmString = matchAliasPatterns(MI, &M); + if (!AsmString) + return false; + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && + AsmString[I] != '$' && AsmString[I] != '\0') + ++I; + char *substr = cs_mem_malloc(I + 1); + memcpy(substr, AsmString, I); + substr[I] = '\0'; + SStream_concat0(OS, substr); + cs_mem_free(substr); + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat1(OS, ' '); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, Address, + OpIdx, + PrintMethodIdx, + OS); + } else + printOperand( + MI, + ((unsigned)AsmString[I++]) - 1, + OS); + } else { + SStream_concat1(OS, AsmString[I++]); + } + } while (AsmString[I] != '\0'); + } + + return true; +#else + return false; +#endif // CAPSTONE_DIET +} + +#ifndef CAPSTONE_DIET +void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) +{ + switch (PrintMethodIdx) { + default: + assert(0 && "Unknown PrintMethod kind"); + break; + case 0: + printPredicateOperand(MI, OpIdx, OS); + break; + case 1: + printVPTPredicateOperand(MI, OpIdx, OS); + break; + case 2: + printMandatoryInvertedPredicateOperand(MI, OpIdx, OS); + break; + } +} +#endif // CAPSTONE_DIET + +#endif // PRINT_ALIAS_INSTR diff --git a/thirdparty/capstone/arch/ARM/ARMGenCSAliasMnemMap.inc b/thirdparty/capstone/arch/ARM/ARMGenCSAliasMnemMap.inc new file mode 100644 index 0000000..628deb6 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMGenCSAliasMnemMap.inc @@ -0,0 +1,48 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + { ARM_INS_ALIAS_VMOV, "vmov" }, + { ARM_INS_ALIAS_NOP, "nop" }, + { ARM_INS_ALIAS_YIELD, "yield" }, + { ARM_INS_ALIAS_WFE, "wfe" }, + { ARM_INS_ALIAS_WFI, "wfi" }, + { ARM_INS_ALIAS_SEV, "sev" }, + { ARM_INS_ALIAS_SEVL, "sevl" }, + { ARM_INS_ALIAS_ESB, "esb" }, + { ARM_INS_ALIAS_CSDB, "csdb" }, + { ARM_INS_ALIAS_CLRBHB, "clrbhb" }, + { ARM_INS_ALIAS_PACBTI, "pacbti" }, + { ARM_INS_ALIAS_BTI, "bti" }, + { ARM_INS_ALIAS_PAC, "pac" }, + { ARM_INS_ALIAS_AUT, "aut" }, + { ARM_INS_ALIAS_SSBB, "ssbb" }, + { ARM_INS_ALIAS_PSSBB, "pssbb" }, + { ARM_INS_ALIAS_DFB, "dfb" }, + { ARM_INS_ALIAS_CSETM, "csetm" }, + { ARM_INS_ALIAS_CSET, "cset" }, + { ARM_INS_ALIAS_CINC, "cinc" }, + { ARM_INS_ALIAS_CINV, "cinv" }, + { ARM_INS_ALIAS_CNEG, "cneg" }, + { ARM_INS_ALIAS_VMLAV, "vmlav" }, + { ARM_INS_ALIAS_VMLAVA, "vmlava" }, + { ARM_INS_ALIAS_VRMLALVH, "vrmlalvh" }, + { ARM_INS_ALIAS_VRMLALVHA, "vrmlalvha" }, + { ARM_INS_ALIAS_VMLALV, "vmlalv" }, + { ARM_INS_ALIAS_VMLALVA, "vmlalva" }, + { ARM_INS_ALIAS_VBIC, "vbic" }, + { ARM_INS_ALIAS_VEOR, "veor" }, + { ARM_INS_ALIAS_VORN, "vorn" }, + { ARM_INS_ALIAS_VORR, "vorr" }, + { ARM_INS_ALIAS_VAND, "vand" }, + { ARM_INS_ALIAS_VPSEL, "vpsel" }, + { ARM_INS_ALIAS_ERET, "eret" }, diff --git a/thirdparty/capstone/arch/ARM/ARMGenCSFeatureName.inc b/thirdparty/capstone/arch/ARM/ARMGenCSFeatureName.inc new file mode 100644 index 0000000..3cbc37a --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMGenCSFeatureName.inc @@ -0,0 +1,60 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{ ARM_FEATURE_IsARM, "IsARM" }, { ARM_FEATURE_HasV5T, "HasV5T" }, + { ARM_FEATURE_HasV4T, "HasV4T" }, { ARM_FEATURE_HasVFP2, "HasVFP2" }, + { ARM_FEATURE_HasV5TE, "HasV5TE" }, { ARM_FEATURE_HasV6T2, "HasV6T2" }, + { ARM_FEATURE_HasMVEInt, "HasMVEInt" }, + { ARM_FEATURE_HasNEON, "HasNEON" }, + { ARM_FEATURE_HasFPRegs64, "HasFPRegs64" }, + { ARM_FEATURE_HasFPRegs, "HasFPRegs" }, + { ARM_FEATURE_IsThumb2, "IsThumb2" }, + { ARM_FEATURE_HasV8_1MMainline, "HasV8_1MMainline" }, + { ARM_FEATURE_HasLOB, "HasLOB" }, { ARM_FEATURE_IsThumb, "IsThumb" }, + { ARM_FEATURE_HasV8MBaseline, "HasV8MBaseline" }, + { ARM_FEATURE_Has8MSecExt, "Has8MSecExt" }, + { ARM_FEATURE_HasV8, "HasV8" }, { ARM_FEATURE_HasAES, "HasAES" }, + { ARM_FEATURE_HasBF16, "HasBF16" }, { ARM_FEATURE_HasCDE, "HasCDE" }, + { ARM_FEATURE_PreV8, "PreV8" }, { ARM_FEATURE_HasV6K, "HasV6K" }, + { ARM_FEATURE_HasCRC, "HasCRC" }, { ARM_FEATURE_HasV7, "HasV7" }, + { ARM_FEATURE_HasDB, "HasDB" }, + { ARM_FEATURE_HasVirtualization, "HasVirtualization" }, + { ARM_FEATURE_HasVFP3, "HasVFP3" }, + { ARM_FEATURE_HasDPVFP, "HasDPVFP" }, + { ARM_FEATURE_HasFullFP16, "HasFullFP16" }, + { ARM_FEATURE_HasV6, "HasV6" }, + { ARM_FEATURE_HasAcquireRelease, "HasAcquireRelease" }, + { ARM_FEATURE_HasV7Clrex, "HasV7Clrex" }, + { ARM_FEATURE_HasMVEFloat, "HasMVEFloat" }, + { ARM_FEATURE_HasFPRegsV8_1M, "HasFPRegsV8_1M" }, + { ARM_FEATURE_HasMP, "HasMP" }, { ARM_FEATURE_HasSB, "HasSB" }, + { ARM_FEATURE_HasDivideInARM, "HasDivideInARM" }, + { ARM_FEATURE_HasV8_1a, "HasV8_1a" }, + { ARM_FEATURE_HasSHA2, "HasSHA2" }, + { ARM_FEATURE_HasTrustZone, "HasTrustZone" }, + { ARM_FEATURE_UseNaClTrap, "UseNaClTrap" }, + { ARM_FEATURE_HasV8_4a, "HasV8_4a" }, + { ARM_FEATURE_HasV8_3a, "HasV8_3a" }, + { ARM_FEATURE_HasFPARMv8, "HasFPARMv8" }, + { ARM_FEATURE_HasFP16, "HasFP16" }, { ARM_FEATURE_HasVFP4, "HasVFP4" }, + { ARM_FEATURE_HasFP16FML, "HasFP16FML" }, + { ARM_FEATURE_HasFPRegs16, "HasFPRegs16" }, + { ARM_FEATURE_HasV8MMainline, "HasV8MMainline" }, + { ARM_FEATURE_HasDotProd, "HasDotProd" }, + { ARM_FEATURE_HasMatMulInt8, "HasMatMulInt8" }, + { ARM_FEATURE_IsMClass, "IsMClass" }, + { ARM_FEATURE_HasPACBTI, "HasPACBTI" }, + { ARM_FEATURE_IsNotMClass, "IsNotMClass" }, + { ARM_FEATURE_HasDSP, "HasDSP" }, + { ARM_FEATURE_HasDivideInThumb, "HasDivideInThumb" }, + { ARM_FEATURE_HasV6M, "HasV6M" }, diff --git a/thirdparty/capstone/arch/ARM/ARMGenCSMappingInsn.inc b/thirdparty/capstone/arch/ARM/ARMGenCSMappingInsn.inc new file mode 100644 index 0000000..a631d74 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMGenCSMappingInsn.inc @@ -0,0 +1,30995 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{ + /* PHINODE */ + ARM_PHI /* 0 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_INLINEASM /* 1 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_INLINEASM_BR /* 2 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_CFI_INSTRUCTION /* 3 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_EH_LABEL /* 4 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_GC_LABEL /* 5 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_ANNOTATION_LABEL /* 6 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_KILL /* 7 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_EXTRACT_SUBREG /* 8 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_INSERT_SUBREG /* 9 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_IMPLICIT_DEF /* 10 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SUBREG_TO_REG /* 11 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_COPY_TO_REGCLASS /* 12 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* DBG_VALUE */ + ARM_DBG_VALUE /* 13 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* DBG_VALUE_LIST */ + ARM_DBG_VALUE_LIST /* 14 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* DBG_INSTR_REF */ + ARM_DBG_INSTR_REF /* 15 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* DBG_PHI */ + ARM_DBG_PHI /* 16 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* DBG_LABEL */ + ARM_DBG_LABEL /* 17 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_REG_SEQUENCE /* 18 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_COPY /* 19 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* BUNDLE */ + ARM_BUNDLE /* 20 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* LIFETIME_START */ + ARM_LIFETIME_START /* 21 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* LIFETIME_END */ + ARM_LIFETIME_END /* 22 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* PSEUDO_PROBE */ + ARM_PSEUDO_PROBE /* 23 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_ARITH_FENCE /* 24 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_STACKMAP /* 25 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* # FEntry call */ + ARM_FENTRY_CALL /* 26 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PATCHPOINT /* 27 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_LOAD_STACK_GUARD /* 28 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PREALLOCATED_SETUP /* 29 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PREALLOCATED_ARG /* 30 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_STATEPOINT /* 31 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_LOCAL_ESCAPE /* 32 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_FAULTING_OP /* 33 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PATCHABLE_OP /* 34 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* # XRay Function Enter. */ + ARM_PATCHABLE_FUNCTION_ENTER /* 35 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* # XRay Function Patchable RET. */ + ARM_PATCHABLE_RET /* 36 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* # XRay Function Exit. */ + ARM_PATCHABLE_FUNCTION_EXIT /* 37 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* # XRay Tail Call Exit. */ + ARM_PATCHABLE_TAIL_CALL /* 38 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* # XRay Custom Event Log. */ + ARM_PATCHABLE_EVENT_CALL /* 39 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* # XRay Typed Event Log. */ + ARM_PATCHABLE_TYPED_EVENT_CALL /* 40 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_ICALL_BRANCH_FUNNEL /* 41 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MEMBARRIER /* 42 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ASSERT_SEXT /* 43 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ASSERT_ZEXT /* 44 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ASSERT_ALIGN /* 45 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ADD /* 46 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SUB /* 47 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_MUL /* 48 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SDIV /* 49 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UDIV /* 50 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SREM /* 51 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UREM /* 52 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SDIVREM /* 53 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UDIVREM /* 54 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_AND /* 55 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_OR /* 56 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_XOR /* 57 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_IMPLICIT_DEF /* 58 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_PHI /* 59 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FRAME_INDEX /* 60 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_GLOBAL_VALUE /* 61 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_EXTRACT /* 62 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UNMERGE_VALUES /* 63 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INSERT /* 64 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_MERGE_VALUES /* 65 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_BUILD_VECTOR /* 66 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_BUILD_VECTOR_TRUNC /* 67 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_CONCAT_VECTORS /* 68 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_PTRTOINT /* 69 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INTTOPTR /* 70 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_BITCAST /* 71 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FREEZE /* 72 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INTRINSIC_FPTRUNC_ROUND /* 73 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INTRINSIC_TRUNC /* 74 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INTRINSIC_ROUND /* 75 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INTRINSIC_LRINT /* 76 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INTRINSIC_ROUNDEVEN /* 77 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_READCYCLECOUNTER /* 78 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_LOAD /* 79 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SEXTLOAD /* 80 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ZEXTLOAD /* 81 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INDEXED_LOAD /* 82 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INDEXED_SEXTLOAD /* 83 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INDEXED_ZEXTLOAD /* 84 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_STORE /* 85 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INDEXED_STORE /* 86 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS /* 87 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMIC_CMPXCHG /* 88 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_XCHG /* 89 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_ADD /* 90 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_SUB /* 91 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_AND /* 92 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_NAND /* 93 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_OR /* 94 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_XOR /* 95 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_MAX /* 96 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_MIN /* 97 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_UMAX /* 98 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_UMIN /* 99 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_FADD /* 100 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_FSUB /* 101 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_FMAX /* 102 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_FMIN /* 103 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_UINC_WRAP /* 104 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ATOMICRMW_UDEC_WRAP /* 105 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FENCE /* 106 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_BRCOND /* 107 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_BRINDIRECT /* 108 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INVOKE_REGION_START /* 109 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INTRINSIC /* 110 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INTRINSIC_W_SIDE_EFFECTS /* 111 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ANYEXT /* 112 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_TRUNC /* 113 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_CONSTANT /* 114 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FCONSTANT /* 115 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VASTART /* 116 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VAARG /* 117 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SEXT /* 118 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SEXT_INREG /* 119 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ZEXT /* 120 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SHL /* 121 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_LSHR /* 122 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ASHR /* 123 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FSHL /* 124 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FSHR /* 125 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ROTR /* 126 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ROTL /* 127 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ICMP /* 128 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FCMP /* 129 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SELECT /* 130 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UADDO /* 131 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UADDE /* 132 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_USUBO /* 133 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_USUBE /* 134 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SADDO /* 135 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SADDE /* 136 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SSUBO /* 137 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SSUBE /* 138 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UMULO /* 139 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SMULO /* 140 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UMULH /* 141 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SMULH /* 142 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UADDSAT /* 143 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SADDSAT /* 144 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_USUBSAT /* 145 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SSUBSAT /* 146 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_USHLSAT /* 147 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SSHLSAT /* 148 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SMULFIX /* 149 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UMULFIX /* 150 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SMULFIXSAT /* 151 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UMULFIXSAT /* 152 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SDIVFIX /* 153 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UDIVFIX /* 154 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SDIVFIXSAT /* 155 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UDIVFIXSAT /* 156 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FADD /* 157 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FSUB /* 158 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FMUL /* 159 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FMA /* 160 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FMAD /* 161 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FDIV /* 162 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FREM /* 163 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FPOW /* 164 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FPOWI /* 165 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FEXP /* 166 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FEXP2 /* 167 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FLOG /* 168 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FLOG2 /* 169 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FLOG10 /* 170 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FNEG /* 171 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FPEXT /* 172 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FPTRUNC /* 173 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FPTOSI /* 174 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FPTOUI /* 175 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SITOFP /* 176 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UITOFP /* 177 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FABS /* 178 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FCOPYSIGN /* 179 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_IS_FPCLASS /* 180 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FCANONICALIZE /* 181 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FMINNUM /* 182 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FMAXNUM /* 183 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FMINNUM_IEEE /* 184 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FMAXNUM_IEEE /* 185 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FMINIMUM /* 186 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FMAXIMUM /* 187 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_PTR_ADD /* 188 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_PTRMASK /* 189 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SMIN /* 190 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SMAX /* 191 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UMIN /* 192 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UMAX /* 193 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ABS /* 194 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_LROUND /* 195 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_LLROUND /* 196 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_BR /* 197 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_BRJT /* 198 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_INSERT_VECTOR_ELT /* 199 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_EXTRACT_VECTOR_ELT /* 200 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SHUFFLE_VECTOR /* 201 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_CTTZ /* 202 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_CTTZ_ZERO_UNDEF /* 203 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_CTLZ /* 204 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_CTLZ_ZERO_UNDEF /* 205 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_CTPOP /* 206 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_BSWAP /* 207 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_BITREVERSE /* 208 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FCEIL /* 209 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FCOS /* 210 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FSIN /* 211 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FSQRT /* 212 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FFLOOR /* 213 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FRINT /* 214 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_FNEARBYINT /* 215 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_ADDRSPACE_CAST /* 216 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_BLOCK_ADDR /* 217 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_JUMP_TABLE /* 218 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_DYN_STACKALLOC /* 219 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_STRICT_FADD /* 220 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_STRICT_FSUB /* 221 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_STRICT_FMUL /* 222 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_STRICT_FDIV /* 223 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_STRICT_FREM /* 224 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_STRICT_FMA /* 225 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_STRICT_FSQRT /* 226 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_READ_REGISTER /* 227 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_WRITE_REGISTER /* 228 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_MEMCPY /* 229 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_MEMCPY_INLINE /* 230 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_MEMMOVE /* 231 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_MEMSET /* 232 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_BZERO /* 233 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_SEQ_FADD /* 234 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_SEQ_FMUL /* 235 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_FADD /* 236 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_FMUL /* 237 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_FMAX /* 238 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_FMIN /* 239 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_ADD /* 240 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_MUL /* 241 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_AND /* 242 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_OR /* 243 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_XOR /* 244 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_SMAX /* 245 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_SMIN /* 246 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_UMAX /* 247 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_VECREDUCE_UMIN /* 248 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_SBFX /* 249 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_G_UBFX /* 250 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_ABS /* 251 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_ADDSri /* 252 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_ADDSrr /* 253 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_ADDSrsi /* 254 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_ADDSrsr /* 255 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_ADJCALLSTACKDOWN /* 256 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_ADJCALLSTACKUP /* 257 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* asr${s}${p} $Rd, $Rm, $imm */ + ARM_ASRi /* 258 */, ARM_INS_ASR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* asr${s}${p} $Rd, $Rn, $Rm */ + ARM_ASRr /* 259 */, ARM_INS_ASR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_B /* 260 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_BCCZi64 /* 261 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_BCCi64 /* 262 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_BLX_noip /* 263 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_BLX_pred_noip /* 264 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_BL_PUSHLR /* 265 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_BMOVPCB_CALL /* 266 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_BMOVPCRX_CALL /* 267 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_BR_JTadd /* 268 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_BR_JTm_i12 /* 269 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_BR_JTm_rs /* 270 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_BR_JTr /* 271 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_BX_CALL /* 272 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_CMP_SWAP_16 /* 273 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_CMP_SWAP_32 /* 274 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_CMP_SWAP_64 /* 275 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_CMP_SWAP_8 /* 276 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_CONSTPOOL_ENTRY /* 277 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_COPY_STRUCT_BYVAL_I32 /* 278 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* it$mask $cc */ + ARM_ITasm /* 279 */, ARM_INS_IT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_Int_eh_sjlj_dispatchsetup /* 280 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_Int_eh_sjlj_longjmp /* 281 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_Int_eh_sjlj_setjmp /* 282 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_Int_eh_sjlj_setjmp_nofp /* 283 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_Int_eh_sjlj_setup_dispatch /* 284 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_JUMPTABLE_ADDRS /* 285 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_JUMPTABLE_INSTS /* 286 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_JUMPTABLE_TBB /* 287 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_JUMPTABLE_TBH /* 288 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_LDMIA_RET /* 289 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* ldrbt${q} $Rt, $addr */ + ARM_LDRBT_POST /* 290 */, ARM_INS_LDRBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldr${q} $Rt, $immediate */ + ARM_LDRConstPool /* 291 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrht${p} $Rt, $addr */ + ARM_LDRHTii /* 292 */, ARM_INS_LDRHT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_LDRLIT_ga_abs /* 293 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_LDRLIT_ga_pcrel /* 294 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_LDRLIT_ga_pcrel_ldr /* 295 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* ldrsbt${p} $Rt, $addr */ + ARM_LDRSBTii /* 296 */, ARM_INS_LDRSBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrsht${p} $Rt, $addr */ + ARM_LDRSHTii /* 297 */, ARM_INS_LDRSHT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrt${q} $Rt, $addr */ + ARM_LDRT_POST /* 298 */, ARM_INS_LDRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_LEApcrel /* 299 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_LEApcrelJT /* 300 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_LOADDUAL /* 301 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* lsl${s}${p} $Rd, $Rm, $imm */ + ARM_LSLi /* 302 */, ARM_INS_LSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* lsl${s}${p} $Rd, $Rn, $Rm */ + ARM_LSLr /* 303 */, ARM_INS_LSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* lsr${s}${p} $Rd, $Rm, $imm */ + ARM_LSRi /* 304 */, ARM_INS_LSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* lsr${s}${p} $Rd, $Rn, $Rm */ + ARM_LSRr /* 305 */, ARM_INS_LSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MEMCPY /* 306 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MLAv5 /* 307 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOVCCi /* 308 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOVCCi16 /* 309 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOVCCi32imm /* 310 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOVCCr /* 311 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOVCCsi /* 312 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOVCCsr /* 313 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOVPCRX /* 314 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOVTi16_ga_pcrel /* 315 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOV_ga_pcrel /* 316 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOV_ga_pcrel_ldr /* 317 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOVi16_ga_pcrel /* 318 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOVi32imm /* 319 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOVsra_flag /* 320 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MOVsrl_flag /* 321 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MQPRCopy /* 322 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MQQPRLoad /* 323 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MQQPRStore /* 324 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MQQQQPRLoad /* 325 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MQQQQPRStore /* 326 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MULv5 /* 327 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MVE_MEMCPYLOOPINST /* 328 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MVE_MEMSETLOOPINST /* 329 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_MVNCCi /* 330 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PICADD /* 331 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PICLDR /* 332 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PICLDRB /* 333 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PICLDRH /* 334 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PICLDRSB /* 335 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PICLDRSH /* 336 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PICSTR /* 337 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PICSTRB /* 338 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_PICSTRH /* 339 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* ror${s}${p} $Rd, $Rm, $imm */ + ARM_RORi /* 340 */, ARM_INS_ROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ror${s}${p} $Rd, $Rn, $Rm */ + ARM_RORr /* 341 */, ARM_INS_ROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_RRX /* 342 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* rrx${s}${p} $Rd, $Rm */ + ARM_RRXi /* 343 */, ARM_INS_RRX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_RSBSri /* 344 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_RSBSrsi /* 345 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_RSBSrsr /* 346 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SEH_EpilogEnd /* 347 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SEH_EpilogStart /* 348 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SEH_Nop /* 349 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SEH_Nop_Ret /* 350 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SEH_PrologEnd /* 351 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SEH_SaveFRegs /* 352 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SEH_SaveLR /* 353 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SEH_SaveRegs /* 354 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SEH_SaveRegs_Ret /* 355 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SEH_SaveSP /* 356 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SEH_StackAlloc /* 357 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SMLALv5 /* 358 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SMULLv5 /* 359 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SPACE /* 360 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_STOREDUAL /* 361 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* strbt${q} $Rt, $addr */ + ARM_STRBT_POST /* 362 */, ARM_INS_STRBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_STRBi_preidx /* 363 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_STRBr_preidx /* 364 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_STRH_preidx /* 365 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* strt${q} $Rt, $addr */ + ARM_STRT_POST /* 366 */, ARM_INS_STRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_STRi_preidx /* 367 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_STRr_preidx /* 368 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SUBS_PC_LR /* 369 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SUBSri /* 370 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SUBSrr /* 371 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SUBSrsi /* 372 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SUBSrsr /* 373 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SpeculationBarrierISBDSBEndBB /* 374 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_SpeculationBarrierSBEndBB /* 375 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_TAILJMPd /* 376 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_TAILJMPr /* 377 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_TAILJMPr4 /* 378 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_TCRETURNdi /* 379 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_TCRETURNri /* 380 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_TPsoft /* 381 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_UMLALv5 /* 382 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_UMULLv5 /* 383 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $list, $addr */ + ARM_VLD1LNdAsm_16 /* 384 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $list, $addr */ + ARM_VLD1LNdAsm_32 /* 385 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $list, $addr */ + ARM_VLD1LNdAsm_8 /* 386 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $list, $addr! */ + ARM_VLD1LNdWB_fixed_Asm_16 /* 387 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $list, $addr! */ + ARM_VLD1LNdWB_fixed_Asm_32 /* 388 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $list, $addr! */ + ARM_VLD1LNdWB_fixed_Asm_8 /* 389 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $list, $addr, $Rm */ + ARM_VLD1LNdWB_register_Asm_16 /* 390 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $list, $addr, $Rm */ + ARM_VLD1LNdWB_register_Asm_32 /* 391 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $list, $addr, $Rm */ + ARM_VLD1LNdWB_register_Asm_8 /* 392 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $list, $addr */ + ARM_VLD2LNdAsm_16 /* 393 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $list, $addr */ + ARM_VLD2LNdAsm_32 /* 394 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $list, $addr */ + ARM_VLD2LNdAsm_8 /* 395 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $list, $addr! */ + ARM_VLD2LNdWB_fixed_Asm_16 /* 396 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $list, $addr! */ + ARM_VLD2LNdWB_fixed_Asm_32 /* 397 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $list, $addr! */ + ARM_VLD2LNdWB_fixed_Asm_8 /* 398 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $list, $addr, $Rm */ + ARM_VLD2LNdWB_register_Asm_16 /* 399 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $list, $addr, $Rm */ + ARM_VLD2LNdWB_register_Asm_32 /* 400 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $list, $addr, $Rm */ + ARM_VLD2LNdWB_register_Asm_8 /* 401 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $list, $addr */ + ARM_VLD2LNqAsm_16 /* 402 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $list, $addr */ + ARM_VLD2LNqAsm_32 /* 403 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $list, $addr! */ + ARM_VLD2LNqWB_fixed_Asm_16 /* 404 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $list, $addr! */ + ARM_VLD2LNqWB_fixed_Asm_32 /* 405 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $list, $addr, $Rm */ + ARM_VLD2LNqWB_register_Asm_16 /* 406 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $list, $addr, $Rm */ + ARM_VLD2LNqWB_register_Asm_32 /* 407 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr */ + ARM_VLD3DUPdAsm_16 /* 408 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr */ + ARM_VLD3DUPdAsm_32 /* 409 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr */ + ARM_VLD3DUPdAsm_8 /* 410 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr! */ + ARM_VLD3DUPdWB_fixed_Asm_16 /* 411 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr! */ + ARM_VLD3DUPdWB_fixed_Asm_32 /* 412 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr! */ + ARM_VLD3DUPdWB_fixed_Asm_8 /* 413 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr, $Rm */ + ARM_VLD3DUPdWB_register_Asm_16 /* 414 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr, $Rm */ + ARM_VLD3DUPdWB_register_Asm_32 /* 415 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr, $Rm */ + ARM_VLD3DUPdWB_register_Asm_8 /* 416 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr */ + ARM_VLD3DUPqAsm_16 /* 417 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr */ + ARM_VLD3DUPqAsm_32 /* 418 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr */ + ARM_VLD3DUPqAsm_8 /* 419 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr! */ + ARM_VLD3DUPqWB_fixed_Asm_16 /* 420 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr! */ + ARM_VLD3DUPqWB_fixed_Asm_32 /* 421 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr! */ + ARM_VLD3DUPqWB_fixed_Asm_8 /* 422 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr, $Rm */ + ARM_VLD3DUPqWB_register_Asm_16 /* 423 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr, $Rm */ + ARM_VLD3DUPqWB_register_Asm_32 /* 424 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr, $Rm */ + ARM_VLD3DUPqWB_register_Asm_8 /* 425 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr */ + ARM_VLD3LNdAsm_16 /* 426 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr */ + ARM_VLD3LNdAsm_32 /* 427 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr */ + ARM_VLD3LNdAsm_8 /* 428 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr! */ + ARM_VLD3LNdWB_fixed_Asm_16 /* 429 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr! */ + ARM_VLD3LNdWB_fixed_Asm_32 /* 430 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr! */ + ARM_VLD3LNdWB_fixed_Asm_8 /* 431 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr, $Rm */ + ARM_VLD3LNdWB_register_Asm_16 /* 432 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr, $Rm */ + ARM_VLD3LNdWB_register_Asm_32 /* 433 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr, $Rm */ + ARM_VLD3LNdWB_register_Asm_8 /* 434 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr */ + ARM_VLD3LNqAsm_16 /* 435 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr */ + ARM_VLD3LNqAsm_32 /* 436 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr! */ + ARM_VLD3LNqWB_fixed_Asm_16 /* 437 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr! */ + ARM_VLD3LNqWB_fixed_Asm_32 /* 438 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr, $Rm */ + ARM_VLD3LNqWB_register_Asm_16 /* 439 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr, $Rm */ + ARM_VLD3LNqWB_register_Asm_32 /* 440 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr */ + ARM_VLD3dAsm_16 /* 441 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr */ + ARM_VLD3dAsm_32 /* 442 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr */ + ARM_VLD3dAsm_8 /* 443 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr! */ + ARM_VLD3dWB_fixed_Asm_16 /* 444 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr! */ + ARM_VLD3dWB_fixed_Asm_32 /* 445 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr! */ + ARM_VLD3dWB_fixed_Asm_8 /* 446 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr, $Rm */ + ARM_VLD3dWB_register_Asm_16 /* 447 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr, $Rm */ + ARM_VLD3dWB_register_Asm_32 /* 448 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr, $Rm */ + ARM_VLD3dWB_register_Asm_8 /* 449 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr */ + ARM_VLD3qAsm_16 /* 450 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr */ + ARM_VLD3qAsm_32 /* 451 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr */ + ARM_VLD3qAsm_8 /* 452 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr! */ + ARM_VLD3qWB_fixed_Asm_16 /* 453 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr! */ + ARM_VLD3qWB_fixed_Asm_32 /* 454 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr! */ + ARM_VLD3qWB_fixed_Asm_8 /* 455 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 $list, $addr, $Rm */ + ARM_VLD3qWB_register_Asm_16 /* 456 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 $list, $addr, $Rm */ + ARM_VLD3qWB_register_Asm_32 /* 457 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 $list, $addr, $Rm */ + ARM_VLD3qWB_register_Asm_8 /* 458 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr */ + ARM_VLD4DUPdAsm_16 /* 459 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr */ + ARM_VLD4DUPdAsm_32 /* 460 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr */ + ARM_VLD4DUPdAsm_8 /* 461 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr! */ + ARM_VLD4DUPdWB_fixed_Asm_16 /* 462 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr! */ + ARM_VLD4DUPdWB_fixed_Asm_32 /* 463 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr! */ + ARM_VLD4DUPdWB_fixed_Asm_8 /* 464 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr, $Rm */ + ARM_VLD4DUPdWB_register_Asm_16 /* 465 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr, $Rm */ + ARM_VLD4DUPdWB_register_Asm_32 /* 466 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr, $Rm */ + ARM_VLD4DUPdWB_register_Asm_8 /* 467 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr */ + ARM_VLD4DUPqAsm_16 /* 468 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr */ + ARM_VLD4DUPqAsm_32 /* 469 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr */ + ARM_VLD4DUPqAsm_8 /* 470 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr! */ + ARM_VLD4DUPqWB_fixed_Asm_16 /* 471 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr! */ + ARM_VLD4DUPqWB_fixed_Asm_32 /* 472 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr! */ + ARM_VLD4DUPqWB_fixed_Asm_8 /* 473 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr, $Rm */ + ARM_VLD4DUPqWB_register_Asm_16 /* 474 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr, $Rm */ + ARM_VLD4DUPqWB_register_Asm_32 /* 475 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr, $Rm */ + ARM_VLD4DUPqWB_register_Asm_8 /* 476 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr */ + ARM_VLD4LNdAsm_16 /* 477 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr */ + ARM_VLD4LNdAsm_32 /* 478 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr */ + ARM_VLD4LNdAsm_8 /* 479 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr! */ + ARM_VLD4LNdWB_fixed_Asm_16 /* 480 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr! */ + ARM_VLD4LNdWB_fixed_Asm_32 /* 481 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr! */ + ARM_VLD4LNdWB_fixed_Asm_8 /* 482 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr, $Rm */ + ARM_VLD4LNdWB_register_Asm_16 /* 483 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr, $Rm */ + ARM_VLD4LNdWB_register_Asm_32 /* 484 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr, $Rm */ + ARM_VLD4LNdWB_register_Asm_8 /* 485 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr */ + ARM_VLD4LNqAsm_16 /* 486 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr */ + ARM_VLD4LNqAsm_32 /* 487 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr! */ + ARM_VLD4LNqWB_fixed_Asm_16 /* 488 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr! */ + ARM_VLD4LNqWB_fixed_Asm_32 /* 489 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr, $Rm */ + ARM_VLD4LNqWB_register_Asm_16 /* 490 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr, $Rm */ + ARM_VLD4LNqWB_register_Asm_32 /* 491 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr */ + ARM_VLD4dAsm_16 /* 492 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr */ + ARM_VLD4dAsm_32 /* 493 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr */ + ARM_VLD4dAsm_8 /* 494 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr! */ + ARM_VLD4dWB_fixed_Asm_16 /* 495 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr! */ + ARM_VLD4dWB_fixed_Asm_32 /* 496 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr! */ + ARM_VLD4dWB_fixed_Asm_8 /* 497 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr, $Rm */ + ARM_VLD4dWB_register_Asm_16 /* 498 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr, $Rm */ + ARM_VLD4dWB_register_Asm_32 /* 499 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr, $Rm */ + ARM_VLD4dWB_register_Asm_8 /* 500 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr */ + ARM_VLD4qAsm_16 /* 501 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr */ + ARM_VLD4qAsm_32 /* 502 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr */ + ARM_VLD4qAsm_8 /* 503 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr! */ + ARM_VLD4qWB_fixed_Asm_16 /* 504 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr! */ + ARM_VLD4qWB_fixed_Asm_32 /* 505 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr! */ + ARM_VLD4qWB_fixed_Asm_8 /* 506 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 $list, $addr, $Rm */ + ARM_VLD4qWB_register_Asm_16 /* 507 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 $list, $addr, $Rm */ + ARM_VLD4qWB_register_Asm_32 /* 508 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 $list, $addr, $Rm */ + ARM_VLD4qWB_register_Asm_8 /* 509 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VMOVD0 /* 510 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VMOVDcc /* 511 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VMOVHcc /* 512 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VMOVQ0 /* 513 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VMOVScc /* 514 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $list, $addr */ + ARM_VST1LNdAsm_16 /* 515 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $list, $addr */ + ARM_VST1LNdAsm_32 /* 516 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $list, $addr */ + ARM_VST1LNdAsm_8 /* 517 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $list, $addr! */ + ARM_VST1LNdWB_fixed_Asm_16 /* 518 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $list, $addr! */ + ARM_VST1LNdWB_fixed_Asm_32 /* 519 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $list, $addr! */ + ARM_VST1LNdWB_fixed_Asm_8 /* 520 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $list, $addr, $Rm */ + ARM_VST1LNdWB_register_Asm_16 /* 521 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $list, $addr, $Rm */ + ARM_VST1LNdWB_register_Asm_32 /* 522 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $list, $addr, $Rm */ + ARM_VST1LNdWB_register_Asm_8 /* 523 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $list, $addr */ + ARM_VST2LNdAsm_16 /* 524 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $list, $addr */ + ARM_VST2LNdAsm_32 /* 525 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 $list, $addr */ + ARM_VST2LNdAsm_8 /* 526 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $list, $addr! */ + ARM_VST2LNdWB_fixed_Asm_16 /* 527 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $list, $addr! */ + ARM_VST2LNdWB_fixed_Asm_32 /* 528 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 $list, $addr! */ + ARM_VST2LNdWB_fixed_Asm_8 /* 529 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $list, $addr, $Rm */ + ARM_VST2LNdWB_register_Asm_16 /* 530 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $list, $addr, $Rm */ + ARM_VST2LNdWB_register_Asm_32 /* 531 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 $list, $addr, $Rm */ + ARM_VST2LNdWB_register_Asm_8 /* 532 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $list, $addr */ + ARM_VST2LNqAsm_16 /* 533 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $list, $addr */ + ARM_VST2LNqAsm_32 /* 534 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $list, $addr! */ + ARM_VST2LNqWB_fixed_Asm_16 /* 535 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $list, $addr! */ + ARM_VST2LNqWB_fixed_Asm_32 /* 536 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $list, $addr, $Rm */ + ARM_VST2LNqWB_register_Asm_16 /* 537 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $list, $addr, $Rm */ + ARM_VST2LNqWB_register_Asm_32 /* 538 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 $list, $addr */ + ARM_VST3LNdAsm_16 /* 539 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 $list, $addr */ + ARM_VST3LNdAsm_32 /* 540 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 $list, $addr */ + ARM_VST3LNdAsm_8 /* 541 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 $list, $addr! */ + ARM_VST3LNdWB_fixed_Asm_16 /* 542 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 $list, $addr! */ + ARM_VST3LNdWB_fixed_Asm_32 /* 543 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 $list, $addr! */ + ARM_VST3LNdWB_fixed_Asm_8 /* 544 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 $list, $addr, $Rm */ + ARM_VST3LNdWB_register_Asm_16 /* 545 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 $list, $addr, $Rm */ + ARM_VST3LNdWB_register_Asm_32 /* 546 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 $list, $addr, $Rm */ + ARM_VST3LNdWB_register_Asm_8 /* 547 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 $list, $addr */ + ARM_VST3LNqAsm_16 /* 548 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 $list, $addr */ + ARM_VST3LNqAsm_32 /* 549 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 $list, $addr! */ + ARM_VST3LNqWB_fixed_Asm_16 /* 550 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 $list, $addr! */ + ARM_VST3LNqWB_fixed_Asm_32 /* 551 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 $list, $addr, $Rm */ + ARM_VST3LNqWB_register_Asm_16 /* 552 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 $list, $addr, $Rm */ + ARM_VST3LNqWB_register_Asm_32 /* 553 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 $list, $addr */ + ARM_VST3dAsm_16 /* 554 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 $list, $addr */ + ARM_VST3dAsm_32 /* 555 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 $list, $addr */ + ARM_VST3dAsm_8 /* 556 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 $list, $addr! */ + ARM_VST3dWB_fixed_Asm_16 /* 557 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 $list, $addr! */ + ARM_VST3dWB_fixed_Asm_32 /* 558 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 $list, $addr! */ + ARM_VST3dWB_fixed_Asm_8 /* 559 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 $list, $addr, $Rm */ + ARM_VST3dWB_register_Asm_16 /* 560 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 $list, $addr, $Rm */ + ARM_VST3dWB_register_Asm_32 /* 561 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 $list, $addr, $Rm */ + ARM_VST3dWB_register_Asm_8 /* 562 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 $list, $addr */ + ARM_VST3qAsm_16 /* 563 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 $list, $addr */ + ARM_VST3qAsm_32 /* 564 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 $list, $addr */ + ARM_VST3qAsm_8 /* 565 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 $list, $addr! */ + ARM_VST3qWB_fixed_Asm_16 /* 566 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 $list, $addr! */ + ARM_VST3qWB_fixed_Asm_32 /* 567 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 $list, $addr! */ + ARM_VST3qWB_fixed_Asm_8 /* 568 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 $list, $addr, $Rm */ + ARM_VST3qWB_register_Asm_16 /* 569 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 $list, $addr, $Rm */ + ARM_VST3qWB_register_Asm_32 /* 570 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 $list, $addr, $Rm */ + ARM_VST3qWB_register_Asm_8 /* 571 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 $list, $addr */ + ARM_VST4LNdAsm_16 /* 572 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 $list, $addr */ + ARM_VST4LNdAsm_32 /* 573 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 $list, $addr */ + ARM_VST4LNdAsm_8 /* 574 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 $list, $addr! */ + ARM_VST4LNdWB_fixed_Asm_16 /* 575 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 $list, $addr! */ + ARM_VST4LNdWB_fixed_Asm_32 /* 576 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 $list, $addr! */ + ARM_VST4LNdWB_fixed_Asm_8 /* 577 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 $list, $addr, $Rm */ + ARM_VST4LNdWB_register_Asm_16 /* 578 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 $list, $addr, $Rm */ + ARM_VST4LNdWB_register_Asm_32 /* 579 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 $list, $addr, $Rm */ + ARM_VST4LNdWB_register_Asm_8 /* 580 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 $list, $addr */ + ARM_VST4LNqAsm_16 /* 581 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 $list, $addr */ + ARM_VST4LNqAsm_32 /* 582 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 $list, $addr! */ + ARM_VST4LNqWB_fixed_Asm_16 /* 583 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 $list, $addr! */ + ARM_VST4LNqWB_fixed_Asm_32 /* 584 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 $list, $addr, $Rm */ + ARM_VST4LNqWB_register_Asm_16 /* 585 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 $list, $addr, $Rm */ + ARM_VST4LNqWB_register_Asm_32 /* 586 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 $list, $addr */ + ARM_VST4dAsm_16 /* 587 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 $list, $addr */ + ARM_VST4dAsm_32 /* 588 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 $list, $addr */ + ARM_VST4dAsm_8 /* 589 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 $list, $addr! */ + ARM_VST4dWB_fixed_Asm_16 /* 590 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 $list, $addr! */ + ARM_VST4dWB_fixed_Asm_32 /* 591 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 $list, $addr! */ + ARM_VST4dWB_fixed_Asm_8 /* 592 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 $list, $addr, $Rm */ + ARM_VST4dWB_register_Asm_16 /* 593 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 $list, $addr, $Rm */ + ARM_VST4dWB_register_Asm_32 /* 594 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 $list, $addr, $Rm */ + ARM_VST4dWB_register_Asm_8 /* 595 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 $list, $addr */ + ARM_VST4qAsm_16 /* 596 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 $list, $addr */ + ARM_VST4qAsm_32 /* 597 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 $list, $addr */ + ARM_VST4qAsm_8 /* 598 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 $list, $addr! */ + ARM_VST4qWB_fixed_Asm_16 /* 599 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 $list, $addr! */ + ARM_VST4qWB_fixed_Asm_32 /* 600 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 $list, $addr! */ + ARM_VST4qWB_fixed_Asm_8 /* 601 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 $list, $addr, $Rm */ + ARM_VST4qWB_register_Asm_16 /* 602 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 $list, $addr, $Rm */ + ARM_VST4qWB_register_Asm_32 /* 603 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 $list, $addr, $Rm */ + ARM_VST4qWB_register_Asm_8 /* 604 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_WIN__CHKSTK /* 605 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_WIN__DBZCHK /* 606 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2ABS /* 607 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2ADDSri /* 608 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2ADDSrr /* 609 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2ADDSrs /* 610 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2BF_LabelPseudo /* 611 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2BR_JT /* 612 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2CALL_BTI /* 613 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2DoLoopStart /* 614 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2DoLoopStartTP /* 615 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2LDMIA_RET /* 616 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p} $Rt, $addr */ + ARM_t2LDRBpcrel /* 617 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $immediate */ + ARM_t2LDRConstPool /* 618 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrh${p} $Rt, $addr */ + ARM_t2LDRHpcrel /* 619 */, ARM_INS_LDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2LDRLIT_ga_pcrel /* 620 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* ldrsb${p} $Rt, $addr */ + ARM_t2LDRSBpcrel /* 621 */, ARM_INS_LDRSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsh${p} $Rt, $addr */ + ARM_t2LDRSHpcrel /* 622 */, ARM_INS_LDRSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p}.w $Rt, $Rn, $imm */ + ARM_t2LDR_POST_imm /* 623 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p}.w $Rt, $addr! */ + ARM_t2LDR_PRE_imm /* 624 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2LDRpci_pic /* 625 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr */ + ARM_t2LDRpcrel /* 626 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2LEApcrel /* 627 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2LEApcrelJT /* 628 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2LoopDec /* 629 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2LoopEnd /* 630 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2LoopEndDec /* 631 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MOVCCasr /* 632 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MOVCCi /* 633 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MOVCCi16 /* 634 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MOVCCi32imm /* 635 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MOVCClsl /* 636 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MOVCClsr /* 637 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MOVCCr /* 638 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MOVCCror /* 639 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* movs${p} $Rd, $shift */ + ARM_t2MOVSsi /* 640 */, ARM_INS_MOVS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* movs${p} $Rd, $shift */ + ARM_t2MOVSsr /* 641 */, ARM_INS_MOVS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MOVTi16_ga_pcrel /* 642 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MOV_ga_pcrel /* 643 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MOVi16_ga_pcrel /* 644 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MOVi32imm /* 645 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* mov${p} $Rd, $shift */ + ARM_t2MOVsi /* 646 */, ARM_INS_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* mov${p} $Rd, $shift */ + ARM_t2MOVsr /* 647 */, ARM_INS_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2MVNCCi /* 648 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2RSBSri /* 649 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2RSBSrs /* 650 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2STRB_preidx /* 651 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2STRH_preidx /* 652 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* str${p}.w $Rt, $Rn, $imm */ + ARM_t2STR_POST_imm /* 653 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* str${p}.w $Rt, $addr! */ + ARM_t2STR_PRE_imm /* 654 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2STR_preidx /* 655 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2SUBSri /* 656 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2SUBSrr /* 657 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2SUBSrs /* 658 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2SpeculationBarrierISBDSBEndBB /* 659 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2SpeculationBarrierSBEndBB /* 660 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2TBB_JT /* 661 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2TBH_JT /* 662 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2WhileLoopSetup /* 663 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2WhileLoopStart /* 664 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2WhileLoopStartLR /* 665 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2WhileLoopStartTP /* 666 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tADCS /* 667 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tADDSi3 /* 668 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tADDSi8 /* 669 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tADDSrr /* 670 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tADDframe /* 671 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tADJCALLSTACKDOWN /* 672 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tADJCALLSTACKUP /* 673 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tBLXNS_CALL /* 674 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tBLXr_noip /* 675 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tBL_PUSHLR /* 676 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tBRIND /* 677 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tBR_JTr /* 678 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tBXNS_RET /* 679 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tBX_CALL /* 680 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tBX_RET /* 681 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tBX_RET_vararg /* 682 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tBfar /* 683 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tCMP_SWAP_16 /* 684 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tCMP_SWAP_32 /* 685 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tCMP_SWAP_8 /* 686 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tLDMIA_UPD /* 687 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $immediate */ + ARM_tLDRConstPool /* 688 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tLDRLIT_ga_abs /* 689 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tLDRLIT_ga_pcrel /* 690 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tLDR_postidx /* 691 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tLDRpci_pic /* 692 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tLEApcrel /* 693 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tLEApcrelJT /* 694 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tLSLSri /* 695 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tMOVCCr_pseudo /* 696 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tPOP_RET /* 697 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tRSBS /* 698 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tSBCS /* 699 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tSUBSi3 /* 700 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tSUBSi8 /* 701 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tSUBSrr /* 702 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tTAILJMPd /* 703 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tTAILJMPdND /* 704 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tTAILJMPr /* 705 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tTBB_JT /* 706 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tTBH_JT /* 707 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tTPsoft /* 708 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* adc${s}${p} $Rd, $Rn, $imm */ + ARM_ADCri /* 709 */, ARM_INS_ADC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* adc${s}${p} $Rd, $Rn, $Rm */ + ARM_ADCrr /* 710 */, ARM_INS_ADC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* adc${s}${p} $Rd, $Rn, $shift */ + ARM_ADCrsi /* 711 */, ARM_INS_ADC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* adc${s}${p} $Rd, $Rn, $shift */ + ARM_ADCrsr /* 712 */, ARM_INS_ADC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* add${s}${p} $Rd, $Rn, $imm */ + ARM_ADDri /* 713 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* add${s}${p} $Rd, $Rn, $Rm */ + ARM_ADDrr /* 714 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* add${s}${p} $Rd, $Rn, $shift */ + ARM_ADDrsi /* 715 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* add${s}${p} $Rd, $Rn, $shift */ + ARM_ADDrsr /* 716 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* adr${p} $Rd, $label */ + ARM_ADR /* 717 */, ARM_INS_ADR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* aesd.8 $Vd, $Vm */ + ARM_AESD /* 718 */, ARM_INS_AESD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasAES, 0 }, 0, 0 + #endif +}, +{ + /* aese.8 $Vd, $Vm */ + ARM_AESE /* 719 */, ARM_INS_AESE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasAES, 0 }, 0, 0 + #endif +}, +{ + /* aesimc.8 $Vd, $Vm */ + ARM_AESIMC /* 720 */, ARM_INS_AESIMC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasAES, 0 }, 0, 0 + #endif +}, +{ + /* aesmc.8 $Vd, $Vm */ + ARM_AESMC /* 721 */, ARM_INS_AESMC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasAES, 0 }, 0, 0 + #endif +}, +{ + /* and${s}${p} $Rd, $Rn, $imm */ + ARM_ANDri /* 722 */, ARM_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* and${s}${p} $Rd, $Rn, $Rm */ + ARM_ANDrr /* 723 */, ARM_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* and${s}${p} $Rd, $Rn, $shift */ + ARM_ANDrsi /* 724 */, ARM_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* and${s}${p} $Rd, $Rn, $shift */ + ARM_ANDrsr /* 725 */, ARM_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* vdot.bf16 $Vd, $Vn, $Vm$lane */ + ARM_BF16VDOTI_VDOTD /* 726 */, ARM_INS_VDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdot.bf16 $Vd, $Vn, $Vm$lane */ + ARM_BF16VDOTI_VDOTQ /* 727 */, ARM_INS_VDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdot.bf16 $Vd, $Vn, $Vm */ + ARM_BF16VDOTS_VDOTD /* 728 */, ARM_INS_VDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdot.bf16 $Vd, $Vn, $Vm */ + ARM_BF16VDOTS_VDOTQ /* 729 */, ARM_INS_VDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.bf16.f32 $Vd, $Vm */ + ARM_BF16_VCVT /* 730 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtb${p}.bf16.f32 $Sd, $Sm */ + ARM_BF16_VCVTB /* 731 */, ARM_INS_VCVTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasBF16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtt${p}.bf16.f32 $Sd, $Sm */ + ARM_BF16_VCVTT /* 732 */, ARM_INS_VCVTT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasBF16, 0 }, 0, 0 + #endif +}, +{ + /* bfc${p} $Rd, $imm */ + ARM_BFC /* 733 */, ARM_INS_BFC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0 + #endif +}, +{ + /* bfi${p} $Rd, $Rn, $imm */ + ARM_BFI /* 734 */, ARM_INS_BFI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0 + #endif +}, +{ + /* bic${s}${p} $Rd, $Rn, $imm */ + ARM_BICri /* 735 */, ARM_INS_BIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* bic${s}${p} $Rd, $Rn, $Rm */ + ARM_BICrr /* 736 */, ARM_INS_BIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* bic${s}${p} $Rd, $Rn, $shift */ + ARM_BICrsi /* 737 */, ARM_INS_BIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* bic${s}${p} $Rd, $Rn, $shift */ + ARM_BICrsr /* 738 */, ARM_INS_BIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* bkpt $val */ + ARM_BKPT /* 739 */, ARM_INS_BKPT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* bl $func */ + ARM_BL /* 740 */, ARM_INS_BL, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* blx $func */ + ARM_BLX /* 741 */, ARM_INS_BLX, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsARM, ARM_FEATURE_HasV5T, 0 }, 0, 0 + #endif +}, +{ + /* blx${p} $func */ + ARM_BLX_pred /* 742 */, ARM_INS_BLX, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsARM, ARM_FEATURE_HasV5T, 0 }, 0, 0 + #endif +}, +{ + /* blx $target */ + ARM_BLXi /* 743 */, ARM_INS_BLX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsARM, ARM_FEATURE_HasV5T, 0 }, 0, 0 + #endif +}, +{ + /* bl${p} $func */ + ARM_BL_pred /* 744 */, ARM_INS_BL, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* bx $dst */ + ARM_BX /* 745 */, ARM_INS_BX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsARM, ARM_FEATURE_HasV4T, 0 }, 1, 1 + #endif +}, +{ + /* bxj${p} $func */ + ARM_BXJ /* 746 */, ARM_INS_BXJ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsARM, 0 }, 1, 1 + #endif +}, +{ + /* bx${p} lr */ + ARM_BX_RET /* 747 */, ARM_INS_BX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_RET, ARM_FEATURE_IsARM, ARM_FEATURE_HasV4T, 0 }, 1, 0 + #endif +}, +{ + /* bx${p} $dst */ + ARM_BX_pred /* 748 */, ARM_INS_BX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsARM, ARM_FEATURE_HasV4T, 0 }, 1, 1 + #endif +}, +{ + /* b${p} $target */ + ARM_Bcc /* 749 */, ARM_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsARM, 0 }, 1, 0 + #endif +}, +{ + /* cx1 $coproc, $Rd, $imm */ + ARM_CDE_CX1 /* 750 */, ARM_INS_CX1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0 + #endif +}, +{ + /* cx1a${p} $coproc, $Rd, $imm */ + ARM_CDE_CX1A /* 751 */, ARM_INS_CX1A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0 + #endif +}, +{ + /* cx1d $coproc, $Rd, $imm */ + ARM_CDE_CX1D /* 752 */, ARM_INS_CX1D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0 + #endif +}, +{ + /* cx1da${p} $coproc, $Rd, $imm */ + ARM_CDE_CX1DA /* 753 */, ARM_INS_CX1DA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0 + #endif +}, +{ + /* cx2 $coproc, $Rd, $Rn, $imm */ + ARM_CDE_CX2 /* 754 */, ARM_INS_CX2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0 + #endif +}, +{ + /* cx2a${p} $coproc, $Rd, $Rn, $imm */ + ARM_CDE_CX2A /* 755 */, ARM_INS_CX2A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0 + #endif +}, +{ + /* cx2d $coproc, $Rd, $Rn, $imm */ + ARM_CDE_CX2D /* 756 */, ARM_INS_CX2D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0 + #endif +}, +{ + /* cx2da${p} $coproc, $Rd, $Rn, $imm */ + ARM_CDE_CX2DA /* 757 */, ARM_INS_CX2DA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0 + #endif +}, +{ + /* cx3 $coproc, $Rd, $Rn, $Rm, $imm */ + ARM_CDE_CX3 /* 758 */, ARM_INS_CX3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0 + #endif +}, +{ + /* cx3a${p} $coproc, $Rd, $Rn, $Rm, $imm */ + ARM_CDE_CX3A /* 759 */, ARM_INS_CX3A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0 + #endif +}, +{ + /* cx3d $coproc, $Rd, $Rn, $Rm, $imm */ + ARM_CDE_CX3D /* 760 */, ARM_INS_CX3D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0 + #endif +}, +{ + /* cx3da${p} $coproc, $Rd, $Rn, $Rm, $imm */ + ARM_CDE_CX3DA /* 761 */, ARM_INS_CX3DA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0 + #endif +}, +{ + /* vcx1a $coproc, $Vd, $imm */ + ARM_CDE_VCX1A_fpdp /* 762 */, ARM_INS_VCX1A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vcx1a $coproc, $Vd, $imm */ + ARM_CDE_VCX1A_fpsp /* 763 */, ARM_INS_VCX1A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vcx1a${vp} $coproc, $Qd, $imm */ + ARM_CDE_VCX1A_vec /* 764 */, ARM_INS_VCX1A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcx1 $coproc, $Vd, $imm */ + ARM_CDE_VCX1_fpdp /* 765 */, ARM_INS_VCX1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vcx1 $coproc, $Vd, $imm */ + ARM_CDE_VCX1_fpsp /* 766 */, ARM_INS_VCX1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vcx1${vp} $coproc, $Qd, $imm */ + ARM_CDE_VCX1_vec /* 767 */, ARM_INS_VCX1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcx2a $coproc, $Vd, $Vm, $imm */ + ARM_CDE_VCX2A_fpdp /* 768 */, ARM_INS_VCX2A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vcx2a $coproc, $Vd, $Vm, $imm */ + ARM_CDE_VCX2A_fpsp /* 769 */, ARM_INS_VCX2A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vcx2a${vp} $coproc, $Qd, $Qm, $imm */ + ARM_CDE_VCX2A_vec /* 770 */, ARM_INS_VCX2A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcx2 $coproc, $Vd, $Vm, $imm */ + ARM_CDE_VCX2_fpdp /* 771 */, ARM_INS_VCX2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vcx2 $coproc, $Vd, $Vm, $imm */ + ARM_CDE_VCX2_fpsp /* 772 */, ARM_INS_VCX2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vcx2${vp} $coproc, $Qd, $Qm, $imm */ + ARM_CDE_VCX2_vec /* 773 */, ARM_INS_VCX2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcx3a $coproc, $Vd, $Vn, $Vm, $imm */ + ARM_CDE_VCX3A_fpdp /* 774 */, ARM_INS_VCX3A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vcx3a $coproc, $Vd, $Vn, $Vm, $imm */ + ARM_CDE_VCX3A_fpsp /* 775 */, ARM_INS_VCX3A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vcx3a${vp} $coproc, $Qd, $Qn, $Qm, $imm */ + ARM_CDE_VCX3A_vec /* 776 */, ARM_INS_VCX3A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcx3 $coproc, $Vd, $Vn, $Vm, $imm */ + ARM_CDE_VCX3_fpdp /* 777 */, ARM_INS_VCX3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vcx3 $coproc, $Vd, $Vn, $Vm, $imm */ + ARM_CDE_VCX3_fpsp /* 778 */, ARM_INS_VCX3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vcx3${vp} $coproc, $Qd, $Qn, $Qm, $imm */ + ARM_CDE_VCX3_vec /* 779 */, ARM_INS_VCX3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* cdp${p} $cop, $opc1, $CRd, $CRn, $CRm, $opc2 */ + ARM_CDP /* 780 */, ARM_INS_CDP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* cdp2 $cop, $opc1, $CRd, $CRn, $CRm, $opc2 */ + ARM_CDP2 /* 781 */, ARM_INS_CDP2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* clrex */ + ARM_CLREX /* 782 */, ARM_INS_CLREX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6K, 0 }, 0, 0 + #endif +}, +{ + /* clz${p} $Rd, $Rm */ + ARM_CLZ /* 783 */, ARM_INS_CLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5T, 0 }, 0, 0 + #endif +}, +{ + /* cmn${p} $Rn, $imm */ + ARM_CMNri /* 784 */, ARM_INS_CMN, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* cmn${p} $Rn, $Rm */ + ARM_CMNzrr /* 785 */, ARM_INS_CMN, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* cmn${p} $Rn, $shift */ + ARM_CMNzrsi /* 786 */, ARM_INS_CMN, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* cmn${p} $Rn, $shift */ + ARM_CMNzrsr /* 787 */, ARM_INS_CMN, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* cmp${p} $Rn, $imm */ + ARM_CMPri /* 788 */, ARM_INS_CMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* cmp${p} $Rn, $Rm */ + ARM_CMPrr /* 789 */, ARM_INS_CMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* cmp${p} $Rn, $shift */ + ARM_CMPrsi /* 790 */, ARM_INS_CMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* cmp${p} $Rn, $shift */ + ARM_CMPrsr /* 791 */, ARM_INS_CMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* cps $mode */ + ARM_CPS1p /* 792 */, ARM_INS_CPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* cps$imod $iflags */ + ARM_CPS2p /* 793 */, ARM_INS_CPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* cps$imod $iflags, $mode */ + ARM_CPS3p /* 794 */, ARM_INS_CPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* crc32b $Rd, $Rn, $Rm */ + ARM_CRC32B /* 795 */, ARM_INS_CRC32B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0 + #endif +}, +{ + /* crc32cb $Rd, $Rn, $Rm */ + ARM_CRC32CB /* 796 */, ARM_INS_CRC32CB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0 + #endif +}, +{ + /* crc32ch $Rd, $Rn, $Rm */ + ARM_CRC32CH /* 797 */, ARM_INS_CRC32CH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0 + #endif +}, +{ + /* crc32cw $Rd, $Rn, $Rm */ + ARM_CRC32CW /* 798 */, ARM_INS_CRC32CW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0 + #endif +}, +{ + /* crc32h $Rd, $Rn, $Rm */ + ARM_CRC32H /* 799 */, ARM_INS_CRC32H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0 + #endif +}, +{ + /* crc32w $Rd, $Rn, $Rm */ + ARM_CRC32W /* 800 */, ARM_INS_CRC32W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0 + #endif +}, +{ + /* dbg${p} $opt */ + ARM_DBG /* 801 */, ARM_INS_DBG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV7, 0 }, 0, 0 + #endif +}, +{ + /* dmb $opt */ + ARM_DMB /* 802 */, ARM_INS_DMB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasDB, 0 }, 0, 0 + #endif +}, +{ + /* dsb $opt */ + ARM_DSB /* 803 */, ARM_INS_DSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasDB, 0 }, 0, 0 + #endif +}, +{ + /* eor${s}${p} $Rd, $Rn, $imm */ + ARM_EORri /* 804 */, ARM_INS_EOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* eor${s}${p} $Rd, $Rn, $Rm */ + ARM_EORrr /* 805 */, ARM_INS_EOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* eor${s}${p} $Rd, $Rn, $shift */ + ARM_EORrsi /* 806 */, ARM_INS_EOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* eor${s}${p} $Rd, $Rn, $shift */ + ARM_EORrsr /* 807 */, ARM_INS_EOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* eret${p} */ + ARM_ERET /* 808 */, ARM_INS_ERET, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_JUMP, ARM_GRP_RET, ARM_FEATURE_IsARM, ARM_FEATURE_HasVirtualization, 0 }, 1, 0 + #endif +}, +{ + /* vmov${p}.f64 $Dd, $imm */ + ARM_FCONSTD /* 809 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP3, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.f16 $Sd, $imm */ + ARM_FCONSTH /* 810 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.f32 $Sd, $imm */ + ARM_FCONSTS /* 811 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP3, 0 }, 0, 0 + #endif +}, +{ + /* fldmdbx${p} $Rn!, $regs */ + ARM_FLDMXDB_UPD /* 812 */, ARM_INS_FLDMDBX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* fldmiax${p} $Rn, $regs */ + ARM_FLDMXIA /* 813 */, ARM_INS_FLDMIAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* fldmiax${p} $Rn!, $regs */ + ARM_FLDMXIA_UPD /* 814 */, ARM_INS_FLDMIAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} APSR_nzcv, fpscr */ + ARM_FMSTAT /* 815 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR_NZCV, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* fstmdbx${p} $Rn!, $regs */ + ARM_FSTMXDB_UPD /* 816 */, ARM_INS_FSTMDBX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* fstmiax${p} $Rn, $regs */ + ARM_FSTMXIA /* 817 */, ARM_INS_FSTMIAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* fstmiax${p} $Rn!, $regs */ + ARM_FSTMXIA_UPD /* 818 */, ARM_INS_FSTMIAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* hint${p} $imm */ + ARM_HINT /* 819 */, ARM_INS_HINT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* hlt $val */ + ARM_HLT /* 820 */, ARM_INS_HLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, 0 }, 0, 0 + #endif +}, +{ + /* hvc $imm */ + ARM_HVC /* 821 */, ARM_INS_HVC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsARM, ARM_FEATURE_HasVirtualization, 0 }, 0, 0 + #endif +}, +{ + /* isb $opt */ + ARM_ISB /* 822 */, ARM_INS_ISB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasDB, 0 }, 0, 0 + #endif +}, +{ + /* lda${p} $Rt, $addr */ + ARM_LDA /* 823 */, ARM_INS_LDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0 + #endif +}, +{ + /* ldab${p} $Rt, $addr */ + ARM_LDAB /* 824 */, ARM_INS_LDAB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0 + #endif +}, +{ + /* ldaex${p} $Rt, $addr */ + ARM_LDAEX /* 825 */, ARM_INS_LDAEX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* ldaexb${p} $Rt, $addr */ + ARM_LDAEXB /* 826 */, ARM_INS_LDAEXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* ldaexd${p} $Rt, $addr */ + ARM_LDAEXD /* 827 */, ARM_INS_LDAEXD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* ldaexh${p} $Rt, $addr */ + ARM_LDAEXH /* 828 */, ARM_INS_LDAEXH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* ldah${p} $Rt, $addr */ + ARM_LDAH /* 829 */, ARM_INS_LDAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0 + #endif +}, +{ + /* ldc2l $cop, $CRd, $addr */ + ARM_LDC2L_OFFSET /* 830 */, ARM_INS_LDC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* ldc2l $cop, $CRd, $addr, $option */ + ARM_LDC2L_OPTION /* 831 */, ARM_INS_LDC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* ldc2l $cop, $CRd, $addr, $offset */ + ARM_LDC2L_POST /* 832 */, ARM_INS_LDC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* ldc2l $cop, $CRd, $addr! */ + ARM_LDC2L_PRE /* 833 */, ARM_INS_LDC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* ldc2 $cop, $CRd, $addr */ + ARM_LDC2_OFFSET /* 834 */, ARM_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* ldc2 $cop, $CRd, $addr, $option */ + ARM_LDC2_OPTION /* 835 */, ARM_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* ldc2 $cop, $CRd, $addr, $offset */ + ARM_LDC2_POST /* 836 */, ARM_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* ldc2 $cop, $CRd, $addr! */ + ARM_LDC2_PRE /* 837 */, ARM_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* ldcl${p} $cop, $CRd, $addr */ + ARM_LDCL_OFFSET /* 838 */, ARM_INS_LDCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldcl${p} $cop, $CRd, $addr, $option */ + ARM_LDCL_OPTION /* 839 */, ARM_INS_LDCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldcl${p} $cop, $CRd, $addr, $offset */ + ARM_LDCL_POST /* 840 */, ARM_INS_LDCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldcl${p} $cop, $CRd, $addr! */ + ARM_LDCL_PRE /* 841 */, ARM_INS_LDCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldc${p} $cop, $CRd, $addr */ + ARM_LDC_OFFSET /* 842 */, ARM_INS_LDC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldc${p} $cop, $CRd, $addr, $option */ + ARM_LDC_OPTION /* 843 */, ARM_INS_LDC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldc${p} $cop, $CRd, $addr, $offset */ + ARM_LDC_POST /* 844 */, ARM_INS_LDC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldc${p} $cop, $CRd, $addr! */ + ARM_LDC_PRE /* 845 */, ARM_INS_LDC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldmda${p} $Rn, $regs */ + ARM_LDMDA /* 846 */, ARM_INS_LDMDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldmda${p} $Rn!, $regs */ + ARM_LDMDA_UPD /* 847 */, ARM_INS_LDMDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldmdb${p} $Rn, $regs */ + ARM_LDMDB /* 848 */, ARM_INS_LDMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldmdb${p} $Rn!, $regs */ + ARM_LDMDB_UPD /* 849 */, ARM_INS_LDMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldm${p} $Rn, $regs */ + ARM_LDMIA /* 850 */, ARM_INS_LDM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldm${p} $Rn!, $regs */ + ARM_LDMIA_UPD /* 851 */, ARM_INS_LDM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldmib${p} $Rn, $regs */ + ARM_LDMIB /* 852 */, ARM_INS_LDMIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldmib${p} $Rn!, $regs */ + ARM_LDMIB_UPD /* 853 */, ARM_INS_LDMIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrbt${p} $Rt, $addr, $offset */ + ARM_LDRBT_POST_IMM /* 854 */, ARM_INS_LDRBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrbt${p} $Rt, $addr, $offset */ + ARM_LDRBT_POST_REG /* 855 */, ARM_INS_LDRBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p} $Rt, $addr, $offset */ + ARM_LDRB_POST_IMM /* 856 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p} $Rt, $addr, $offset */ + ARM_LDRB_POST_REG /* 857 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p} $Rt, $addr! */ + ARM_LDRB_PRE_IMM /* 858 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p} $Rt, $addr! */ + ARM_LDRB_PRE_REG /* 859 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p} $Rt, $addr */ + ARM_LDRBi12 /* 860 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p} $Rt, $shift */ + ARM_LDRBrs /* 861 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrd${p} $Rt, $Rt2, $addr */ + ARM_LDRD /* 862 */, ARM_INS_LDRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* ldrd${p} $Rt, $Rt2, $addr, $offset */ + ARM_LDRD_POST /* 863 */, ARM_INS_LDRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrd${p} $Rt, $Rt2, $addr! */ + ARM_LDRD_PRE /* 864 */, ARM_INS_LDRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrex${p} $Rt, $addr */ + ARM_LDREX /* 865 */, ARM_INS_LDREX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrexb${p} $Rt, $addr */ + ARM_LDREXB /* 866 */, ARM_INS_LDREXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrexd${p} $Rt, $addr */ + ARM_LDREXD /* 867 */, ARM_INS_LDREXD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrexh${p} $Rt, $addr */ + ARM_LDREXH /* 868 */, ARM_INS_LDREXH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrh${p} $Rt, $addr */ + ARM_LDRH /* 869 */, ARM_INS_LDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrht${p} $Rt, $addr, $offset */ + ARM_LDRHTi /* 870 */, ARM_INS_LDRHT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrht${p} $Rt, $addr, $Rm */ + ARM_LDRHTr /* 871 */, ARM_INS_LDRHT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrh${p} $Rt, $addr, $offset */ + ARM_LDRH_POST /* 872 */, ARM_INS_LDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrh${p} $Rt, $addr! */ + ARM_LDRH_PRE /* 873 */, ARM_INS_LDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrsb${p} $Rt, $addr */ + ARM_LDRSB /* 874 */, ARM_INS_LDRSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrsbt${p} $Rt, $addr, $offset */ + ARM_LDRSBTi /* 875 */, ARM_INS_LDRSBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrsbt${p} $Rt, $addr, $Rm */ + ARM_LDRSBTr /* 876 */, ARM_INS_LDRSBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrsb${p} $Rt, $addr, $offset */ + ARM_LDRSB_POST /* 877 */, ARM_INS_LDRSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrsb${p} $Rt, $addr! */ + ARM_LDRSB_PRE /* 878 */, ARM_INS_LDRSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrsh${p} $Rt, $addr */ + ARM_LDRSH /* 879 */, ARM_INS_LDRSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrsht${p} $Rt, $addr, $offset */ + ARM_LDRSHTi /* 880 */, ARM_INS_LDRSHT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrsht${p} $Rt, $addr, $Rm */ + ARM_LDRSHTr /* 881 */, ARM_INS_LDRSHT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrsh${p} $Rt, $addr, $offset */ + ARM_LDRSH_POST /* 882 */, ARM_INS_LDRSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrsh${p} $Rt, $addr! */ + ARM_LDRSH_PRE /* 883 */, ARM_INS_LDRSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrt${p} $Rt, $addr, $offset */ + ARM_LDRT_POST_IMM /* 884 */, ARM_INS_LDRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldrt${p} $Rt, $addr, $offset */ + ARM_LDRT_POST_REG /* 885 */, ARM_INS_LDRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr, $offset */ + ARM_LDR_POST_IMM /* 886 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr, $offset */ + ARM_LDR_POST_REG /* 887 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr! */ + ARM_LDR_PRE_IMM /* 888 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr! */ + ARM_LDR_PRE_REG /* 889 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr */ + ARM_LDRcp /* 890 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr */ + ARM_LDRi12 /* 891 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $shift */ + ARM_LDRrs /* 892 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mcr${p} $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + ARM_MCR /* 893 */, ARM_INS_MCR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mcr2 $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + ARM_MCR2 /* 894 */, ARM_INS_MCR2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* mcrr${p} $cop, $opc1, $Rt, $Rt2, $CRm */ + ARM_MCRR /* 895 */, ARM_INS_MCRR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mcrr2 $cop, $opc1, $Rt, $Rt2, $CRm */ + ARM_MCRR2 /* 896 */, ARM_INS_MCRR2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* mla${s}${p} $Rd, $Rn, $Rm, $Ra */ + ARM_MLA /* 897 */, ARM_INS_MLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* mls${p} $Rd, $Rn, $Rm, $Ra */ + ARM_MLS /* 898 */, ARM_INS_MLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0 + #endif +}, +{ + /* mov${p} pc, lr */ + ARM_MOVPCLR /* 899 */, ARM_INS_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_RET, ARM_FEATURE_IsARM, 0 }, 1, 0 + #endif +}, +{ + /* movt${p} $Rd, $imm */ + ARM_MOVTi16 /* 900 */, ARM_INS_MOVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0 + #endif +}, +{ + /* mov${s}${p} $Rd, $imm */ + ARM_MOVi /* 901 */, ARM_INS_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* movw${p} $Rd, $imm */ + ARM_MOVi16 /* 902 */, ARM_INS_MOVW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0 + #endif +}, +{ + /* mov${s}${p} $Rd, $Rm */ + ARM_MOVr /* 903 */, ARM_INS_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mov${s}${p} $Rd, $Rm */ + ARM_MOVr_TC /* 904 */, ARM_INS_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mov${s}${p} $Rd, $src */ + ARM_MOVsi /* 905 */, ARM_INS_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mov${s}${p} $Rd, $src */ + ARM_MOVsr /* 906 */, ARM_INS_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mrc${p} $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + ARM_MRC /* 907 */, ARM_INS_MRC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mrc2 $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + ARM_MRC2 /* 908 */, ARM_INS_MRC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* mrrc${p} $cop, $opc1, $Rt, $Rt2, $CRm */ + ARM_MRRC /* 909 */, ARM_INS_MRRC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mrrc2 $cop, $opc1, $Rt, $Rt2, $CRm */ + ARM_MRRC2 /* 910 */, ARM_INS_MRRC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* mrs${p} $Rd, apsr */ + ARM_MRS /* 911 */, ARM_INS_MRS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mrs${p} $Rd, $banked */ + ARM_MRSbanked /* 912 */, ARM_INS_MRS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasVirtualization, 0 }, 0, 0 + #endif +}, +{ + /* mrs${p} $Rd, spsr */ + ARM_MRSsys /* 913 */, ARM_INS_MRS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* msr${p} $mask, $Rn */ + ARM_MSR /* 914 */, ARM_INS_MSR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* msr${p} $banked, $Rn */ + ARM_MSRbanked /* 915 */, ARM_INS_MSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasVirtualization, 0 }, 0, 0 + #endif +}, +{ + /* msr${p} $mask, $imm */ + ARM_MSRi /* 916 */, ARM_INS_MSR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mul${s}${p} $Rd, $Rn, $Rm */ + ARM_MUL /* 917 */, ARM_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* asrl${p} $RdaLo, $RdaHi, $imm */ + ARM_MVE_ASRLi /* 918 */, ARM_INS_ASRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* asrl${p} $RdaLo, $RdaHi, $Rm */ + ARM_MVE_ASRLr /* 919 */, ARM_INS_ASRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* dlstp.16 $LR, $Rn */ + ARM_MVE_DLSTP_16 /* 920 */, ARM_INS_DLSTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* dlstp.32 $LR, $Rn */ + ARM_MVE_DLSTP_32 /* 921 */, ARM_INS_DLSTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* dlstp.64 $LR, $Rn */ + ARM_MVE_DLSTP_64 /* 922 */, ARM_INS_DLSTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* dlstp.8 $LR, $Rn */ + ARM_MVE_DLSTP_8 /* 923 */, ARM_INS_DLSTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* lctp${p} */ + ARM_MVE_LCTP /* 924 */, ARM_INS_LCTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* letp $LRin, $label */ + ARM_MVE_LETP /* 925 */, ARM_INS_LETP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_HasMVEInt, 0 }, 1, 0 + #endif +}, +{ + /* lsll${p} $RdaLo, $RdaHi, $imm */ + ARM_MVE_LSLLi /* 926 */, ARM_INS_LSLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* lsll${p} $RdaLo, $RdaHi, $Rm */ + ARM_MVE_LSLLr /* 927 */, ARM_INS_LSLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* lsrl${p} $RdaLo, $RdaHi, $imm */ + ARM_MVE_LSRL /* 928 */, ARM_INS_LSRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* sqrshr${p} $RdaSrc, $Rm */ + ARM_MVE_SQRSHR /* 929 */, ARM_INS_SQRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* sqrshrl${p} $RdaLo, $RdaHi, $sat, $Rm */ + ARM_MVE_SQRSHRL /* 930 */, ARM_INS_SQRSHRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* sqshl${p} $RdaSrc, $imm */ + ARM_MVE_SQSHL /* 931 */, ARM_INS_SQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* sqshll${p} $RdaLo, $RdaHi, $imm */ + ARM_MVE_SQSHLL /* 932 */, ARM_INS_SQSHLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* srshr${p} $RdaSrc, $imm */ + ARM_MVE_SRSHR /* 933 */, ARM_INS_SRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* srshrl${p} $RdaLo, $RdaHi, $imm */ + ARM_MVE_SRSHRL /* 934 */, ARM_INS_SRSHRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* uqrshl${p} $RdaSrc, $Rm */ + ARM_MVE_UQRSHL /* 935 */, ARM_INS_UQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* uqrshll${p} $RdaLo, $RdaHi, $sat, $Rm */ + ARM_MVE_UQRSHLL /* 936 */, ARM_INS_UQRSHLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* uqshl${p} $RdaSrc, $imm */ + ARM_MVE_UQSHL /* 937 */, ARM_INS_UQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* uqshll${p} $RdaLo, $RdaHi, $imm */ + ARM_MVE_UQSHLL /* 938 */, ARM_INS_UQSHLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* urshr${p} $RdaSrc, $imm */ + ARM_MVE_URSHR /* 939 */, ARM_INS_URSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* urshrl${p} $RdaLo, $RdaHi, $imm */ + ARM_MVE_URSHRL /* 940 */, ARM_INS_URSHRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabav${vp}.s16 $Rda, $Qn, $Qm */ + ARM_MVE_VABAVs16 /* 941 */, ARM_INS_VABAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabav${vp}.s32 $Rda, $Qn, $Qm */ + ARM_MVE_VABAVs32 /* 942 */, ARM_INS_VABAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabav${vp}.s8 $Rda, $Qn, $Qm */ + ARM_MVE_VABAVs8 /* 943 */, ARM_INS_VABAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabav${vp}.u16 $Rda, $Qn, $Qm */ + ARM_MVE_VABAVu16 /* 944 */, ARM_INS_VABAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabav${vp}.u32 $Rda, $Qn, $Qm */ + ARM_MVE_VABAVu32 /* 945 */, ARM_INS_VABAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabav${vp}.u8 $Rda, $Qn, $Qm */ + ARM_MVE_VABAVu8 /* 946 */, ARM_INS_VABAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabd${vp}.f16 $Qd, $Qn, $Qm */ + ARM_MVE_VABDf16 /* 947 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vabd${vp}.f32 $Qd, $Qn, $Qm */ + ARM_MVE_VABDf32 /* 948 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vabd${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VABDs16 /* 949 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabd${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VABDs32 /* 950 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabd${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VABDs8 /* 951 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabd${vp}.u16 $Qd, $Qn, $Qm */ + ARM_MVE_VABDu16 /* 952 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabd${vp}.u32 $Qd, $Qn, $Qm */ + ARM_MVE_VABDu32 /* 953 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabd${vp}.u8 $Qd, $Qn, $Qm */ + ARM_MVE_VABDu8 /* 954 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabs${vp}.f16 $Qd, $Qm */ + ARM_MVE_VABSf16 /* 955 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vabs${vp}.f32 $Qd, $Qm */ + ARM_MVE_VABSf32 /* 956 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vabs${vp}.s16 $Qd, $Qm */ + ARM_MVE_VABSs16 /* 957 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabs${vp}.s32 $Qd, $Qm */ + ARM_MVE_VABSs32 /* 958 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vabs${vp}.s8 $Qd, $Qm */ + ARM_MVE_VABSs8 /* 959 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vadc${vp}.i32 $Qd, $Qn, $Qm */ + ARM_MVE_VADC /* 960 */, ARM_INS_VADC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vadci${vp}.i32 $Qd, $Qn, $Qm */ + ARM_MVE_VADCI /* 961 */, ARM_INS_VADCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddlva${vp}.s32 $RdaLo, $RdaHi, $Qm */ + ARM_MVE_VADDLVs32acc /* 962 */, ARM_INS_VADDLVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddlv${vp}.s32 $RdaLo, $RdaHi, $Qm */ + ARM_MVE_VADDLVs32no_acc /* 963 */, ARM_INS_VADDLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddlva${vp}.u32 $RdaLo, $RdaHi, $Qm */ + ARM_MVE_VADDLVu32acc /* 964 */, ARM_INS_VADDLVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddlv${vp}.u32 $RdaLo, $RdaHi, $Qm */ + ARM_MVE_VADDLVu32no_acc /* 965 */, ARM_INS_VADDLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddva${vp}.s16 $Rda, $Qm */ + ARM_MVE_VADDVs16acc /* 966 */, ARM_INS_VADDVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddv${vp}.s16 $Rda, $Qm */ + ARM_MVE_VADDVs16no_acc /* 967 */, ARM_INS_VADDV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddva${vp}.s32 $Rda, $Qm */ + ARM_MVE_VADDVs32acc /* 968 */, ARM_INS_VADDVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddv${vp}.s32 $Rda, $Qm */ + ARM_MVE_VADDVs32no_acc /* 969 */, ARM_INS_VADDV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddva${vp}.s8 $Rda, $Qm */ + ARM_MVE_VADDVs8acc /* 970 */, ARM_INS_VADDVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddv${vp}.s8 $Rda, $Qm */ + ARM_MVE_VADDVs8no_acc /* 971 */, ARM_INS_VADDV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddva${vp}.u16 $Rda, $Qm */ + ARM_MVE_VADDVu16acc /* 972 */, ARM_INS_VADDVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddv${vp}.u16 $Rda, $Qm */ + ARM_MVE_VADDVu16no_acc /* 973 */, ARM_INS_VADDV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddva${vp}.u32 $Rda, $Qm */ + ARM_MVE_VADDVu32acc /* 974 */, ARM_INS_VADDVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddv${vp}.u32 $Rda, $Qm */ + ARM_MVE_VADDVu32no_acc /* 975 */, ARM_INS_VADDV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddva${vp}.u8 $Rda, $Qm */ + ARM_MVE_VADDVu8acc /* 976 */, ARM_INS_VADDVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vaddv${vp}.u8 $Rda, $Qm */ + ARM_MVE_VADDVu8no_acc /* 977 */, ARM_INS_VADDV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vadd${vp}.f16 $Qd, $Qn, $Rm */ + ARM_MVE_VADD_qr_f16 /* 978 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vadd${vp}.f32 $Qd, $Qn, $Rm */ + ARM_MVE_VADD_qr_f32 /* 979 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vadd${vp}.i16 $Qd, $Qn, $Rm */ + ARM_MVE_VADD_qr_i16 /* 980 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vadd${vp}.i32 $Qd, $Qn, $Rm */ + ARM_MVE_VADD_qr_i32 /* 981 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vadd${vp}.i8 $Qd, $Qn, $Rm */ + ARM_MVE_VADD_qr_i8 /* 982 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vadd${vp}.f16 $Qd, $Qn, $Qm */ + ARM_MVE_VADDf16 /* 983 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vadd${vp}.f32 $Qd, $Qn, $Qm */ + ARM_MVE_VADDf32 /* 984 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vadd${vp}.i16 $Qd, $Qn, $Qm */ + ARM_MVE_VADDi16 /* 985 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vadd${vp}.i32 $Qd, $Qn, $Qm */ + ARM_MVE_VADDi32 /* 986 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vadd${vp}.i8 $Qd, $Qn, $Qm */ + ARM_MVE_VADDi8 /* 987 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vand${vp} $Qd, $Qn, $Qm */ + ARM_MVE_VAND /* 988 */, ARM_INS_VAND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vbic${vp} $Qd, $Qn, $Qm */ + ARM_MVE_VBIC /* 989 */, ARM_INS_VBIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vbic${vp}.i16 $Qd, $imm */ + ARM_MVE_VBICimmi16 /* 990 */, ARM_INS_VBIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vbic${vp}.i32 $Qd, $imm */ + ARM_MVE_VBICimmi32 /* 991 */, ARM_INS_VBIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vbrsr${vp}.16 $Qd, $Qn, $Rm */ + ARM_MVE_VBRSR16 /* 992 */, ARM_INS_VBRSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vbrsr${vp}.32 $Qd, $Qn, $Rm */ + ARM_MVE_VBRSR32 /* 993 */, ARM_INS_VBRSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vbrsr${vp}.8 $Qd, $Qn, $Rm */ + ARM_MVE_VBRSR8 /* 994 */, ARM_INS_VBRSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcadd${vp}.f16 $Qd, $Qn, $Qm, $rot */ + ARM_MVE_VCADDf16 /* 995 */, ARM_INS_VCADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcadd${vp}.f32 $Qd, $Qn, $Qm, $rot */ + ARM_MVE_VCADDf32 /* 996 */, ARM_INS_VCADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcadd${vp}.i16 $Qd, $Qn, $Qm, $rot */ + ARM_MVE_VCADDi16 /* 997 */, ARM_INS_VCADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcadd${vp}.i32 $Qd, $Qn, $Qm, $rot */ + ARM_MVE_VCADDi32 /* 998 */, ARM_INS_VCADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcadd${vp}.i8 $Qd, $Qn, $Qm, $rot */ + ARM_MVE_VCADDi8 /* 999 */, ARM_INS_VCADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcls${vp}.s16 $Qd, $Qm */ + ARM_MVE_VCLSs16 /* 1000 */, ARM_INS_VCLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcls${vp}.s32 $Qd, $Qm */ + ARM_MVE_VCLSs32 /* 1001 */, ARM_INS_VCLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcls${vp}.s8 $Qd, $Qm */ + ARM_MVE_VCLSs8 /* 1002 */, ARM_INS_VCLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vclz${vp}.i16 $Qd, $Qm */ + ARM_MVE_VCLZs16 /* 1003 */, ARM_INS_VCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vclz${vp}.i32 $Qd, $Qm */ + ARM_MVE_VCLZs32 /* 1004 */, ARM_INS_VCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vclz${vp}.i8 $Qd, $Qm */ + ARM_MVE_VCLZs8 /* 1005 */, ARM_INS_VCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmla${vp}.f16 $Qd, $Qn, $Qm, $rot */ + ARM_MVE_VCMLAf16 /* 1006 */, ARM_INS_VCMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcmla${vp}.f32 $Qd, $Qn, $Qm, $rot */ + ARM_MVE_VCMLAf32 /* 1007 */, ARM_INS_VCMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.f16 $fc, $Qn, $Qm */ + ARM_MVE_VCMPf16 /* 1008 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.f16 $fc, $Qn, $Rm */ + ARM_MVE_VCMPf16r /* 1009 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.f32 $fc, $Qn, $Qm */ + ARM_MVE_VCMPf32 /* 1010 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.f32 $fc, $Qn, $Rm */ + ARM_MVE_VCMPf32r /* 1011 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.i16 $fc, $Qn, $Qm */ + ARM_MVE_VCMPi16 /* 1012 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.i16 $fc, $Qn, $Rm */ + ARM_MVE_VCMPi16r /* 1013 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.i32 $fc, $Qn, $Qm */ + ARM_MVE_VCMPi32 /* 1014 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.i32 $fc, $Qn, $Rm */ + ARM_MVE_VCMPi32r /* 1015 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.i8 $fc, $Qn, $Qm */ + ARM_MVE_VCMPi8 /* 1016 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.i8 $fc, $Qn, $Rm */ + ARM_MVE_VCMPi8r /* 1017 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.s16 $fc, $Qn, $Qm */ + ARM_MVE_VCMPs16 /* 1018 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.s16 $fc, $Qn, $Rm */ + ARM_MVE_VCMPs16r /* 1019 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.s32 $fc, $Qn, $Qm */ + ARM_MVE_VCMPs32 /* 1020 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.s32 $fc, $Qn, $Rm */ + ARM_MVE_VCMPs32r /* 1021 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.s8 $fc, $Qn, $Qm */ + ARM_MVE_VCMPs8 /* 1022 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.s8 $fc, $Qn, $Rm */ + ARM_MVE_VCMPs8r /* 1023 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.u16 $fc, $Qn, $Qm */ + ARM_MVE_VCMPu16 /* 1024 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.u16 $fc, $Qn, $Rm */ + ARM_MVE_VCMPu16r /* 1025 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.u32 $fc, $Qn, $Qm */ + ARM_MVE_VCMPu32 /* 1026 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.u32 $fc, $Qn, $Rm */ + ARM_MVE_VCMPu32r /* 1027 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.u8 $fc, $Qn, $Qm */ + ARM_MVE_VCMPu8 /* 1028 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${vp}.u8 $fc, $Qn, $Rm */ + ARM_MVE_VCMPu8r /* 1029 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcmul${vp}.f16 $Qd, $Qn, $Qm, $rot */ + ARM_MVE_VCMULf16 /* 1030 */, ARM_INS_VCMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcmul${vp}.f32 $Qd, $Qn, $Qm, $rot */ + ARM_MVE_VCMULf32 /* 1031 */, ARM_INS_VCMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vctp${vp}.16 $Rn */ + ARM_MVE_VCTP16 /* 1032 */, ARM_INS_VCTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vctp${vp}.32 $Rn */ + ARM_MVE_VCTP32 /* 1033 */, ARM_INS_VCTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vctp${vp}.64 $Rn */ + ARM_MVE_VCTP64 /* 1034 */, ARM_INS_VCTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vctp${vp}.8 $Rn */ + ARM_MVE_VCTP8 /* 1035 */, ARM_INS_VCTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vcvtb${vp}.f16.f32 $Qd, $Qm */ + ARM_MVE_VCVTf16f32bh /* 1036 */, ARM_INS_VCVTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtt${vp}.f16.f32 $Qd, $Qm */ + ARM_MVE_VCVTf16f32th /* 1037 */, ARM_INS_VCVTT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.f16.s16 $Qd, $Qm, $imm6 */ + ARM_MVE_VCVTf16s16_fix /* 1038 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.f16.s16 $Qd, $Qm */ + ARM_MVE_VCVTf16s16n /* 1039 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.f16.u16 $Qd, $Qm, $imm6 */ + ARM_MVE_VCVTf16u16_fix /* 1040 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.f16.u16 $Qd, $Qm */ + ARM_MVE_VCVTf16u16n /* 1041 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtb${vp}.f32.f16 $Qd, $Qm */ + ARM_MVE_VCVTf32f16bh /* 1042 */, ARM_INS_VCVTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtt${vp}.f32.f16 $Qd, $Qm */ + ARM_MVE_VCVTf32f16th /* 1043 */, ARM_INS_VCVTT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.f32.s32 $Qd, $Qm, $imm6 */ + ARM_MVE_VCVTf32s32_fix /* 1044 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.f32.s32 $Qd, $Qm */ + ARM_MVE_VCVTf32s32n /* 1045 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.f32.u32 $Qd, $Qm, $imm6 */ + ARM_MVE_VCVTf32u32_fix /* 1046 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.f32.u32 $Qd, $Qm */ + ARM_MVE_VCVTf32u32n /* 1047 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.s16.f16 $Qd, $Qm, $imm6 */ + ARM_MVE_VCVTs16f16_fix /* 1048 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvta${vp}.s16.f16 $Qd, $Qm */ + ARM_MVE_VCVTs16f16a /* 1049 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm${vp}.s16.f16 $Qd, $Qm */ + ARM_MVE_VCVTs16f16m /* 1050 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn${vp}.s16.f16 $Qd, $Qm */ + ARM_MVE_VCVTs16f16n /* 1051 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp${vp}.s16.f16 $Qd, $Qm */ + ARM_MVE_VCVTs16f16p /* 1052 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.s16.f16 $Qd, $Qm */ + ARM_MVE_VCVTs16f16z /* 1053 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.s32.f32 $Qd, $Qm, $imm6 */ + ARM_MVE_VCVTs32f32_fix /* 1054 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvta${vp}.s32.f32 $Qd, $Qm */ + ARM_MVE_VCVTs32f32a /* 1055 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm${vp}.s32.f32 $Qd, $Qm */ + ARM_MVE_VCVTs32f32m /* 1056 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn${vp}.s32.f32 $Qd, $Qm */ + ARM_MVE_VCVTs32f32n /* 1057 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp${vp}.s32.f32 $Qd, $Qm */ + ARM_MVE_VCVTs32f32p /* 1058 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.s32.f32 $Qd, $Qm */ + ARM_MVE_VCVTs32f32z /* 1059 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.u16.f16 $Qd, $Qm, $imm6 */ + ARM_MVE_VCVTu16f16_fix /* 1060 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvta${vp}.u16.f16 $Qd, $Qm */ + ARM_MVE_VCVTu16f16a /* 1061 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm${vp}.u16.f16 $Qd, $Qm */ + ARM_MVE_VCVTu16f16m /* 1062 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn${vp}.u16.f16 $Qd, $Qm */ + ARM_MVE_VCVTu16f16n /* 1063 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp${vp}.u16.f16 $Qd, $Qm */ + ARM_MVE_VCVTu16f16p /* 1064 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.u16.f16 $Qd, $Qm */ + ARM_MVE_VCVTu16f16z /* 1065 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.u32.f32 $Qd, $Qm, $imm6 */ + ARM_MVE_VCVTu32f32_fix /* 1066 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvta${vp}.u32.f32 $Qd, $Qm */ + ARM_MVE_VCVTu32f32a /* 1067 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm${vp}.u32.f32 $Qd, $Qm */ + ARM_MVE_VCVTu32f32m /* 1068 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn${vp}.u32.f32 $Qd, $Qm */ + ARM_MVE_VCVTu32f32n /* 1069 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp${vp}.u32.f32 $Qd, $Qm */ + ARM_MVE_VCVTu32f32p /* 1070 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${vp}.u32.f32 $Qd, $Qm */ + ARM_MVE_VCVTu32f32z /* 1071 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vddup${vp}.u16 $Qd, $Rn, $imm */ + ARM_MVE_VDDUPu16 /* 1072 */, ARM_INS_VDDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vddup${vp}.u32 $Qd, $Rn, $imm */ + ARM_MVE_VDDUPu32 /* 1073 */, ARM_INS_VDDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vddup${vp}.u8 $Qd, $Rn, $imm */ + ARM_MVE_VDDUPu8 /* 1074 */, ARM_INS_VDDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vdup${vp}.16 $Qd, $Rt */ + ARM_MVE_VDUP16 /* 1075 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vdup${vp}.32 $Qd, $Rt */ + ARM_MVE_VDUP32 /* 1076 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vdup${vp}.8 $Qd, $Rt */ + ARM_MVE_VDUP8 /* 1077 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vdwdup${vp}.u16 $Qd, $Rn, $Rm, $imm */ + ARM_MVE_VDWDUPu16 /* 1078 */, ARM_INS_VDWDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vdwdup${vp}.u32 $Qd, $Rn, $Rm, $imm */ + ARM_MVE_VDWDUPu32 /* 1079 */, ARM_INS_VDWDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vdwdup${vp}.u8 $Qd, $Rn, $Rm, $imm */ + ARM_MVE_VDWDUPu8 /* 1080 */, ARM_INS_VDWDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* veor${vp} $Qd, $Qn, $Qm */ + ARM_MVE_VEOR /* 1081 */, ARM_INS_VEOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vfmas${vp}.f16 $Qd, $Qn, $Rm */ + ARM_MVE_VFMA_qr_Sf16 /* 1082 */, ARM_INS_VFMAS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vfmas${vp}.f32 $Qd, $Qn, $Rm */ + ARM_MVE_VFMA_qr_Sf32 /* 1083 */, ARM_INS_VFMAS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vfma${vp}.f16 $Qd, $Qn, $Rm */ + ARM_MVE_VFMA_qr_f16 /* 1084 */, ARM_INS_VFMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vfma${vp}.f32 $Qd, $Qn, $Rm */ + ARM_MVE_VFMA_qr_f32 /* 1085 */, ARM_INS_VFMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vfma${vp}.f16 $Qd, $Qn, $Qm */ + ARM_MVE_VFMAf16 /* 1086 */, ARM_INS_VFMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vfma${vp}.f32 $Qd, $Qn, $Qm */ + ARM_MVE_VFMAf32 /* 1087 */, ARM_INS_VFMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vfms${vp}.f16 $Qd, $Qn, $Qm */ + ARM_MVE_VFMSf16 /* 1088 */, ARM_INS_VFMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vfms${vp}.f32 $Qd, $Qn, $Qm */ + ARM_MVE_VFMSf32 /* 1089 */, ARM_INS_VFMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${vp}.s16 $Qd, $Qn, $Rm */ + ARM_MVE_VHADD_qr_s16 /* 1090 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${vp}.s32 $Qd, $Qn, $Rm */ + ARM_MVE_VHADD_qr_s32 /* 1091 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${vp}.s8 $Qd, $Qn, $Rm */ + ARM_MVE_VHADD_qr_s8 /* 1092 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${vp}.u16 $Qd, $Qn, $Rm */ + ARM_MVE_VHADD_qr_u16 /* 1093 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${vp}.u32 $Qd, $Qn, $Rm */ + ARM_MVE_VHADD_qr_u32 /* 1094 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${vp}.u8 $Qd, $Qn, $Rm */ + ARM_MVE_VHADD_qr_u8 /* 1095 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VHADDs16 /* 1096 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VHADDs32 /* 1097 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VHADDs8 /* 1098 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${vp}.u16 $Qd, $Qn, $Qm */ + ARM_MVE_VHADDu16 /* 1099 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${vp}.u32 $Qd, $Qn, $Qm */ + ARM_MVE_VHADDu32 /* 1100 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${vp}.u8 $Qd, $Qn, $Qm */ + ARM_MVE_VHADDu8 /* 1101 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhcadd${vp}.s16 $Qd, $Qn, $Qm, $rot */ + ARM_MVE_VHCADDs16 /* 1102 */, ARM_INS_VHCADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhcadd${vp}.s32 $Qd, $Qn, $Qm, $rot */ + ARM_MVE_VHCADDs32 /* 1103 */, ARM_INS_VHCADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhcadd${vp}.s8 $Qd, $Qn, $Qm, $rot */ + ARM_MVE_VHCADDs8 /* 1104 */, ARM_INS_VHCADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${vp}.s16 $Qd, $Qn, $Rm */ + ARM_MVE_VHSUB_qr_s16 /* 1105 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${vp}.s32 $Qd, $Qn, $Rm */ + ARM_MVE_VHSUB_qr_s32 /* 1106 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${vp}.s8 $Qd, $Qn, $Rm */ + ARM_MVE_VHSUB_qr_s8 /* 1107 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${vp}.u16 $Qd, $Qn, $Rm */ + ARM_MVE_VHSUB_qr_u16 /* 1108 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${vp}.u32 $Qd, $Qn, $Rm */ + ARM_MVE_VHSUB_qr_u32 /* 1109 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${vp}.u8 $Qd, $Qn, $Rm */ + ARM_MVE_VHSUB_qr_u8 /* 1110 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VHSUBs16 /* 1111 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VHSUBs32 /* 1112 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VHSUBs8 /* 1113 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${vp}.u16 $Qd, $Qn, $Qm */ + ARM_MVE_VHSUBu16 /* 1114 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${vp}.u32 $Qd, $Qn, $Qm */ + ARM_MVE_VHSUBu32 /* 1115 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${vp}.u8 $Qd, $Qn, $Qm */ + ARM_MVE_VHSUBu8 /* 1116 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vidup${vp}.u16 $Qd, $Rn, $imm */ + ARM_MVE_VIDUPu16 /* 1117 */, ARM_INS_VIDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vidup${vp}.u32 $Qd, $Rn, $imm */ + ARM_MVE_VIDUPu32 /* 1118 */, ARM_INS_VIDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vidup${vp}.u8 $Qd, $Rn, $imm */ + ARM_MVE_VIDUPu8 /* 1119 */, ARM_INS_VIDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* viwdup${vp}.u16 $Qd, $Rn, $Rm, $imm */ + ARM_MVE_VIWDUPu16 /* 1120 */, ARM_INS_VIWDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* viwdup${vp}.u32 $Qd, $Rn, $Rm, $imm */ + ARM_MVE_VIWDUPu32 /* 1121 */, ARM_INS_VIWDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* viwdup${vp}.u8 $Qd, $Rn, $Rm, $imm */ + ARM_MVE_VIWDUPu8 /* 1122 */, ARM_INS_VIWDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld20.16 $VQd, $Rn */ + ARM_MVE_VLD20_16 /* 1123 */, ARM_INS_VLD20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld20.16 $VQd, $Rn! */ + ARM_MVE_VLD20_16_wb /* 1124 */, ARM_INS_VLD20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld20.32 $VQd, $Rn */ + ARM_MVE_VLD20_32 /* 1125 */, ARM_INS_VLD20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld20.32 $VQd, $Rn! */ + ARM_MVE_VLD20_32_wb /* 1126 */, ARM_INS_VLD20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld20.8 $VQd, $Rn */ + ARM_MVE_VLD20_8 /* 1127 */, ARM_INS_VLD20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld20.8 $VQd, $Rn! */ + ARM_MVE_VLD20_8_wb /* 1128 */, ARM_INS_VLD20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld21.16 $VQd, $Rn */ + ARM_MVE_VLD21_16 /* 1129 */, ARM_INS_VLD21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld21.16 $VQd, $Rn! */ + ARM_MVE_VLD21_16_wb /* 1130 */, ARM_INS_VLD21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld21.32 $VQd, $Rn */ + ARM_MVE_VLD21_32 /* 1131 */, ARM_INS_VLD21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld21.32 $VQd, $Rn! */ + ARM_MVE_VLD21_32_wb /* 1132 */, ARM_INS_VLD21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld21.8 $VQd, $Rn */ + ARM_MVE_VLD21_8 /* 1133 */, ARM_INS_VLD21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld21.8 $VQd, $Rn! */ + ARM_MVE_VLD21_8_wb /* 1134 */, ARM_INS_VLD21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld40.16 $VQd, $Rn */ + ARM_MVE_VLD40_16 /* 1135 */, ARM_INS_VLD40, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld40.16 $VQd, $Rn! */ + ARM_MVE_VLD40_16_wb /* 1136 */, ARM_INS_VLD40, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld40.32 $VQd, $Rn */ + ARM_MVE_VLD40_32 /* 1137 */, ARM_INS_VLD40, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld40.32 $VQd, $Rn! */ + ARM_MVE_VLD40_32_wb /* 1138 */, ARM_INS_VLD40, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld40.8 $VQd, $Rn */ + ARM_MVE_VLD40_8 /* 1139 */, ARM_INS_VLD40, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld40.8 $VQd, $Rn! */ + ARM_MVE_VLD40_8_wb /* 1140 */, ARM_INS_VLD40, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld41.16 $VQd, $Rn */ + ARM_MVE_VLD41_16 /* 1141 */, ARM_INS_VLD41, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld41.16 $VQd, $Rn! */ + ARM_MVE_VLD41_16_wb /* 1142 */, ARM_INS_VLD41, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld41.32 $VQd, $Rn */ + ARM_MVE_VLD41_32 /* 1143 */, ARM_INS_VLD41, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld41.32 $VQd, $Rn! */ + ARM_MVE_VLD41_32_wb /* 1144 */, ARM_INS_VLD41, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld41.8 $VQd, $Rn */ + ARM_MVE_VLD41_8 /* 1145 */, ARM_INS_VLD41, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld41.8 $VQd, $Rn! */ + ARM_MVE_VLD41_8_wb /* 1146 */, ARM_INS_VLD41, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld42.16 $VQd, $Rn */ + ARM_MVE_VLD42_16 /* 1147 */, ARM_INS_VLD42, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld42.16 $VQd, $Rn! */ + ARM_MVE_VLD42_16_wb /* 1148 */, ARM_INS_VLD42, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld42.32 $VQd, $Rn */ + ARM_MVE_VLD42_32 /* 1149 */, ARM_INS_VLD42, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld42.32 $VQd, $Rn! */ + ARM_MVE_VLD42_32_wb /* 1150 */, ARM_INS_VLD42, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld42.8 $VQd, $Rn */ + ARM_MVE_VLD42_8 /* 1151 */, ARM_INS_VLD42, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld42.8 $VQd, $Rn! */ + ARM_MVE_VLD42_8_wb /* 1152 */, ARM_INS_VLD42, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld43.16 $VQd, $Rn */ + ARM_MVE_VLD43_16 /* 1153 */, ARM_INS_VLD43, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld43.16 $VQd, $Rn! */ + ARM_MVE_VLD43_16_wb /* 1154 */, ARM_INS_VLD43, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld43.32 $VQd, $Rn */ + ARM_MVE_VLD43_32 /* 1155 */, ARM_INS_VLD43, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld43.32 $VQd, $Rn! */ + ARM_MVE_VLD43_32_wb /* 1156 */, ARM_INS_VLD43, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld43.8 $VQd, $Rn */ + ARM_MVE_VLD43_8 /* 1157 */, ARM_INS_VLD43, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vld43.8 $VQd, $Rn! */ + ARM_MVE_VLD43_8_wb /* 1158 */, ARM_INS_VLD43, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.s16 $Qd, $addr */ + ARM_MVE_VLDRBS16 /* 1159 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.s16 $Qd, $Rn$addr */ + ARM_MVE_VLDRBS16_post /* 1160 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.s16 $Qd, $addr! */ + ARM_MVE_VLDRBS16_pre /* 1161 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.s16 $Qd, $addr */ + ARM_MVE_VLDRBS16_rq /* 1162 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.s32 $Qd, $addr */ + ARM_MVE_VLDRBS32 /* 1163 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.s32 $Qd, $Rn$addr */ + ARM_MVE_VLDRBS32_post /* 1164 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.s32 $Qd, $addr! */ + ARM_MVE_VLDRBS32_pre /* 1165 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.s32 $Qd, $addr */ + ARM_MVE_VLDRBS32_rq /* 1166 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.u16 $Qd, $addr */ + ARM_MVE_VLDRBU16 /* 1167 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.u16 $Qd, $Rn$addr */ + ARM_MVE_VLDRBU16_post /* 1168 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.u16 $Qd, $addr! */ + ARM_MVE_VLDRBU16_pre /* 1169 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.u16 $Qd, $addr */ + ARM_MVE_VLDRBU16_rq /* 1170 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.u32 $Qd, $addr */ + ARM_MVE_VLDRBU32 /* 1171 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.u32 $Qd, $Rn$addr */ + ARM_MVE_VLDRBU32_post /* 1172 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.u32 $Qd, $addr! */ + ARM_MVE_VLDRBU32_pre /* 1173 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.u32 $Qd, $addr */ + ARM_MVE_VLDRBU32_rq /* 1174 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.u8 $Qd, $addr */ + ARM_MVE_VLDRBU8 /* 1175 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.u8 $Qd, $Rn$addr */ + ARM_MVE_VLDRBU8_post /* 1176 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.u8 $Qd, $addr! */ + ARM_MVE_VLDRBU8_pre /* 1177 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrb${vp}.u8 $Qd, $addr */ + ARM_MVE_VLDRBU8_rq /* 1178 */, ARM_INS_VLDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrd${vp}.u64 $Qd, $addr */ + ARM_MVE_VLDRDU64_qi /* 1179 */, ARM_INS_VLDRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrd${vp}.u64 $Qd, $addr! */ + ARM_MVE_VLDRDU64_qi_pre /* 1180 */, ARM_INS_VLDRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrd${vp}.u64 $Qd, $addr */ + ARM_MVE_VLDRDU64_rq /* 1181 */, ARM_INS_VLDRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrd${vp}.u64 $Qd, $addr */ + ARM_MVE_VLDRDU64_rq_u /* 1182 */, ARM_INS_VLDRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.s32 $Qd, $addr */ + ARM_MVE_VLDRHS32 /* 1183 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.s32 $Qd, $Rn$addr */ + ARM_MVE_VLDRHS32_post /* 1184 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.s32 $Qd, $addr! */ + ARM_MVE_VLDRHS32_pre /* 1185 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.s32 $Qd, $addr */ + ARM_MVE_VLDRHS32_rq /* 1186 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.s32 $Qd, $addr */ + ARM_MVE_VLDRHS32_rq_u /* 1187 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.u16 $Qd, $addr */ + ARM_MVE_VLDRHU16 /* 1188 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.u16 $Qd, $Rn$addr */ + ARM_MVE_VLDRHU16_post /* 1189 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.u16 $Qd, $addr! */ + ARM_MVE_VLDRHU16_pre /* 1190 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.u16 $Qd, $addr */ + ARM_MVE_VLDRHU16_rq /* 1191 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.u16 $Qd, $addr */ + ARM_MVE_VLDRHU16_rq_u /* 1192 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.u32 $Qd, $addr */ + ARM_MVE_VLDRHU32 /* 1193 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.u32 $Qd, $Rn$addr */ + ARM_MVE_VLDRHU32_post /* 1194 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.u32 $Qd, $addr! */ + ARM_MVE_VLDRHU32_pre /* 1195 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.u32 $Qd, $addr */ + ARM_MVE_VLDRHU32_rq /* 1196 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrh${vp}.u32 $Qd, $addr */ + ARM_MVE_VLDRHU32_rq_u /* 1197 */, ARM_INS_VLDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrw${vp}.u32 $Qd, $addr */ + ARM_MVE_VLDRWU32 /* 1198 */, ARM_INS_VLDRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrw${vp}.u32 $Qd, $Rn$addr */ + ARM_MVE_VLDRWU32_post /* 1199 */, ARM_INS_VLDRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrw${vp}.u32 $Qd, $addr! */ + ARM_MVE_VLDRWU32_pre /* 1200 */, ARM_INS_VLDRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrw${vp}.u32 $Qd, $addr */ + ARM_MVE_VLDRWU32_qi /* 1201 */, ARM_INS_VLDRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrw${vp}.u32 $Qd, $addr! */ + ARM_MVE_VLDRWU32_qi_pre /* 1202 */, ARM_INS_VLDRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrw${vp}.u32 $Qd, $addr */ + ARM_MVE_VLDRWU32_rq /* 1203 */, ARM_INS_VLDRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldrw${vp}.u32 $Qd, $addr */ + ARM_MVE_VLDRWU32_rq_u /* 1204 */, ARM_INS_VLDRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmaxav${vp}.s16 $RdaSrc, $Qm */ + ARM_MVE_VMAXAVs16 /* 1205 */, ARM_INS_VMAXAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmaxav${vp}.s32 $RdaSrc, $Qm */ + ARM_MVE_VMAXAVs32 /* 1206 */, ARM_INS_VMAXAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmaxav${vp}.s8 $RdaSrc, $Qm */ + ARM_MVE_VMAXAVs8 /* 1207 */, ARM_INS_VMAXAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmaxa${vp}.s16 $Qd, $Qm */ + ARM_MVE_VMAXAs16 /* 1208 */, ARM_INS_VMAXA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmaxa${vp}.s32 $Qd, $Qm */ + ARM_MVE_VMAXAs32 /* 1209 */, ARM_INS_VMAXA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmaxa${vp}.s8 $Qd, $Qm */ + ARM_MVE_VMAXAs8 /* 1210 */, ARM_INS_VMAXA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnmav${vp}.f16 $RdaSrc, $Qm */ + ARM_MVE_VMAXNMAVf16 /* 1211 */, ARM_INS_VMAXNMAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnmav${vp}.f32 $RdaSrc, $Qm */ + ARM_MVE_VMAXNMAVf32 /* 1212 */, ARM_INS_VMAXNMAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnma${vp}.f16 $Qd, $Qm */ + ARM_MVE_VMAXNMAf16 /* 1213 */, ARM_INS_VMAXNMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnma${vp}.f32 $Qd, $Qm */ + ARM_MVE_VMAXNMAf32 /* 1214 */, ARM_INS_VMAXNMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnmv${vp}.f16 $RdaSrc, $Qm */ + ARM_MVE_VMAXNMVf16 /* 1215 */, ARM_INS_VMAXNMV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnmv${vp}.f32 $RdaSrc, $Qm */ + ARM_MVE_VMAXNMVf32 /* 1216 */, ARM_INS_VMAXNMV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnm${vp}.f16 $Qd, $Qn, $Qm */ + ARM_MVE_VMAXNMf16 /* 1217 */, ARM_INS_VMAXNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnm${vp}.f32 $Qd, $Qn, $Qm */ + ARM_MVE_VMAXNMf32 /* 1218 */, ARM_INS_VMAXNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vmaxv${vp}.s16 $RdaSrc, $Qm */ + ARM_MVE_VMAXVs16 /* 1219 */, ARM_INS_VMAXV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmaxv${vp}.s32 $RdaSrc, $Qm */ + ARM_MVE_VMAXVs32 /* 1220 */, ARM_INS_VMAXV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmaxv${vp}.s8 $RdaSrc, $Qm */ + ARM_MVE_VMAXVs8 /* 1221 */, ARM_INS_VMAXV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmaxv${vp}.u16 $RdaSrc, $Qm */ + ARM_MVE_VMAXVu16 /* 1222 */, ARM_INS_VMAXV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmaxv${vp}.u32 $RdaSrc, $Qm */ + ARM_MVE_VMAXVu32 /* 1223 */, ARM_INS_VMAXV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmaxv${vp}.u8 $RdaSrc, $Qm */ + ARM_MVE_VMAXVu8 /* 1224 */, ARM_INS_VMAXV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmax${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VMAXs16 /* 1225 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmax${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VMAXs32 /* 1226 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmax${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VMAXs8 /* 1227 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmax${vp}.u16 $Qd, $Qn, $Qm */ + ARM_MVE_VMAXu16 /* 1228 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmax${vp}.u32 $Qd, $Qn, $Qm */ + ARM_MVE_VMAXu32 /* 1229 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmax${vp}.u8 $Qd, $Qn, $Qm */ + ARM_MVE_VMAXu8 /* 1230 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vminav${vp}.s16 $RdaSrc, $Qm */ + ARM_MVE_VMINAVs16 /* 1231 */, ARM_INS_VMINAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vminav${vp}.s32 $RdaSrc, $Qm */ + ARM_MVE_VMINAVs32 /* 1232 */, ARM_INS_VMINAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vminav${vp}.s8 $RdaSrc, $Qm */ + ARM_MVE_VMINAVs8 /* 1233 */, ARM_INS_VMINAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmina${vp}.s16 $Qd, $Qm */ + ARM_MVE_VMINAs16 /* 1234 */, ARM_INS_VMINA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmina${vp}.s32 $Qd, $Qm */ + ARM_MVE_VMINAs32 /* 1235 */, ARM_INS_VMINA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmina${vp}.s8 $Qd, $Qm */ + ARM_MVE_VMINAs8 /* 1236 */, ARM_INS_VMINA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vminnmav${vp}.f16 $RdaSrc, $Qm */ + ARM_MVE_VMINNMAVf16 /* 1237 */, ARM_INS_VMINNMAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vminnmav${vp}.f32 $RdaSrc, $Qm */ + ARM_MVE_VMINNMAVf32 /* 1238 */, ARM_INS_VMINNMAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vminnma${vp}.f16 $Qd, $Qm */ + ARM_MVE_VMINNMAf16 /* 1239 */, ARM_INS_VMINNMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vminnma${vp}.f32 $Qd, $Qm */ + ARM_MVE_VMINNMAf32 /* 1240 */, ARM_INS_VMINNMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vminnmv${vp}.f16 $RdaSrc, $Qm */ + ARM_MVE_VMINNMVf16 /* 1241 */, ARM_INS_VMINNMV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vminnmv${vp}.f32 $RdaSrc, $Qm */ + ARM_MVE_VMINNMVf32 /* 1242 */, ARM_INS_VMINNMV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vminnm${vp}.f16 $Qd, $Qn, $Qm */ + ARM_MVE_VMINNMf16 /* 1243 */, ARM_INS_VMINNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vminnm${vp}.f32 $Qd, $Qn, $Qm */ + ARM_MVE_VMINNMf32 /* 1244 */, ARM_INS_VMINNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vminv${vp}.s16 $RdaSrc, $Qm */ + ARM_MVE_VMINVs16 /* 1245 */, ARM_INS_VMINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vminv${vp}.s32 $RdaSrc, $Qm */ + ARM_MVE_VMINVs32 /* 1246 */, ARM_INS_VMINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vminv${vp}.s8 $RdaSrc, $Qm */ + ARM_MVE_VMINVs8 /* 1247 */, ARM_INS_VMINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vminv${vp}.u16 $RdaSrc, $Qm */ + ARM_MVE_VMINVu16 /* 1248 */, ARM_INS_VMINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vminv${vp}.u32 $RdaSrc, $Qm */ + ARM_MVE_VMINVu32 /* 1249 */, ARM_INS_VMINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vminv${vp}.u8 $RdaSrc, $Qm */ + ARM_MVE_VMINVu8 /* 1250 */, ARM_INS_VMINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmin${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VMINs16 /* 1251 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmin${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VMINs32 /* 1252 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmin${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VMINs8 /* 1253 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmin${vp}.u16 $Qd, $Qn, $Qm */ + ARM_MVE_VMINu16 /* 1254 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmin${vp}.u32 $Qd, $Qn, $Qm */ + ARM_MVE_VMINu32 /* 1255 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmin${vp}.u8 $Qd, $Qn, $Qm */ + ARM_MVE_VMINu8 /* 1256 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladava${vp}.s16 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVas16 /* 1257 */, ARM_INS_VMLADAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladava${vp}.s32 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVas32 /* 1258 */, ARM_INS_VMLADAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladava${vp}.s8 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVas8 /* 1259 */, ARM_INS_VMLADAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladava${vp}.u16 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVau16 /* 1260 */, ARM_INS_VMLADAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladava${vp}.u32 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVau32 /* 1261 */, ARM_INS_VMLADAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladava${vp}.u8 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVau8 /* 1262 */, ARM_INS_VMLADAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladavax${vp}.s16 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVaxs16 /* 1263 */, ARM_INS_VMLADAVAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladavax${vp}.s32 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVaxs32 /* 1264 */, ARM_INS_VMLADAVAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladavax${vp}.s8 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVaxs8 /* 1265 */, ARM_INS_VMLADAVAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladav${vp}.s16 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVs16 /* 1266 */, ARM_INS_VMLADAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladav${vp}.s32 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVs32 /* 1267 */, ARM_INS_VMLADAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladav${vp}.s8 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVs8 /* 1268 */, ARM_INS_VMLADAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladav${vp}.u16 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVu16 /* 1269 */, ARM_INS_VMLADAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladav${vp}.u32 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVu32 /* 1270 */, ARM_INS_VMLADAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladav${vp}.u8 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVu8 /* 1271 */, ARM_INS_VMLADAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladavx${vp}.s16 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVxs16 /* 1272 */, ARM_INS_VMLADAVX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladavx${vp}.s32 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVxs32 /* 1273 */, ARM_INS_VMLADAVX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmladavx${vp}.s8 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLADAVxs8 /* 1274 */, ARM_INS_VMLADAVX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlaldava${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLALDAVas16 /* 1275 */, ARM_INS_VMLALDAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlaldava${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLALDAVas32 /* 1276 */, ARM_INS_VMLALDAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlaldava${vp}.u16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLALDAVau16 /* 1277 */, ARM_INS_VMLALDAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlaldava${vp}.u32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLALDAVau32 /* 1278 */, ARM_INS_VMLALDAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlaldavax${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLALDAVaxs16 /* 1279 */, ARM_INS_VMLALDAVAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlaldavax${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLALDAVaxs32 /* 1280 */, ARM_INS_VMLALDAVAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlaldav${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLALDAVs16 /* 1281 */, ARM_INS_VMLALDAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlaldav${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLALDAVs32 /* 1282 */, ARM_INS_VMLALDAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlaldav${vp}.u16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLALDAVu16 /* 1283 */, ARM_INS_VMLALDAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlaldav${vp}.u32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLALDAVu32 /* 1284 */, ARM_INS_VMLALDAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlaldavx${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLALDAVxs16 /* 1285 */, ARM_INS_VMLALDAVX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlaldavx${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLALDAVxs32 /* 1286 */, ARM_INS_VMLALDAVX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlas${vp}.i16 $Qd, $Qn, $Rm */ + ARM_MVE_VMLAS_qr_i16 /* 1287 */, ARM_INS_VMLAS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlas${vp}.i32 $Qd, $Qn, $Rm */ + ARM_MVE_VMLAS_qr_i32 /* 1288 */, ARM_INS_VMLAS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlas${vp}.i8 $Qd, $Qn, $Rm */ + ARM_MVE_VMLAS_qr_i8 /* 1289 */, ARM_INS_VMLAS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmla${vp}.i16 $Qd, $Qn, $Rm */ + ARM_MVE_VMLA_qr_i16 /* 1290 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmla${vp}.i32 $Qd, $Qn, $Rm */ + ARM_MVE_VMLA_qr_i32 /* 1291 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmla${vp}.i8 $Qd, $Qn, $Rm */ + ARM_MVE_VMLA_qr_i8 /* 1292 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsdava${vp}.s16 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLSDAVas16 /* 1293 */, ARM_INS_VMLSDAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsdava${vp}.s32 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLSDAVas32 /* 1294 */, ARM_INS_VMLSDAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsdava${vp}.s8 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLSDAVas8 /* 1295 */, ARM_INS_VMLSDAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsdavax${vp}.s16 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLSDAVaxs16 /* 1296 */, ARM_INS_VMLSDAVAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsdavax${vp}.s32 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLSDAVaxs32 /* 1297 */, ARM_INS_VMLSDAVAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsdavax${vp}.s8 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLSDAVaxs8 /* 1298 */, ARM_INS_VMLSDAVAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsdav${vp}.s16 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLSDAVs16 /* 1299 */, ARM_INS_VMLSDAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsdav${vp}.s32 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLSDAVs32 /* 1300 */, ARM_INS_VMLSDAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsdav${vp}.s8 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLSDAVs8 /* 1301 */, ARM_INS_VMLSDAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsdavx${vp}.s16 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLSDAVxs16 /* 1302 */, ARM_INS_VMLSDAVX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsdavx${vp}.s32 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLSDAVxs32 /* 1303 */, ARM_INS_VMLSDAVX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsdavx${vp}.s8 $RdaDest, $Qn, $Qm */ + ARM_MVE_VMLSDAVxs8 /* 1304 */, ARM_INS_VMLSDAVX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsldava${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLSLDAVas16 /* 1305 */, ARM_INS_VMLSLDAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsldava${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLSLDAVas32 /* 1306 */, ARM_INS_VMLSLDAVA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsldavax${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLSLDAVaxs16 /* 1307 */, ARM_INS_VMLSLDAVAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsldavax${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLSLDAVaxs32 /* 1308 */, ARM_INS_VMLSLDAVAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsldav${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLSLDAVs16 /* 1309 */, ARM_INS_VMLSLDAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsldav${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLSLDAVs32 /* 1310 */, ARM_INS_VMLSLDAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsldavx${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLSLDAVxs16 /* 1311 */, ARM_INS_VMLSLDAVX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmlsldavx${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VMLSLDAVxs32 /* 1312 */, ARM_INS_VMLSLDAVX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmovlb${vp}.s16 $Qd, $Qm */ + ARM_MVE_VMOVLs16bh /* 1313 */, ARM_INS_VMOVLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmovlt${vp}.s16 $Qd, $Qm */ + ARM_MVE_VMOVLs16th /* 1314 */, ARM_INS_VMOVLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmovlb${vp}.s8 $Qd, $Qm */ + ARM_MVE_VMOVLs8bh /* 1315 */, ARM_INS_VMOVLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmovlt${vp}.s8 $Qd, $Qm */ + ARM_MVE_VMOVLs8th /* 1316 */, ARM_INS_VMOVLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmovlb${vp}.u16 $Qd, $Qm */ + ARM_MVE_VMOVLu16bh /* 1317 */, ARM_INS_VMOVLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmovlt${vp}.u16 $Qd, $Qm */ + ARM_MVE_VMOVLu16th /* 1318 */, ARM_INS_VMOVLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmovlb${vp}.u8 $Qd, $Qm */ + ARM_MVE_VMOVLu8bh /* 1319 */, ARM_INS_VMOVLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmovlt${vp}.u8 $Qd, $Qm */ + ARM_MVE_VMOVLu8th /* 1320 */, ARM_INS_VMOVLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmovnb${vp}.i16 $Qd, $Qm */ + ARM_MVE_VMOVNi16bh /* 1321 */, ARM_INS_VMOVNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmovnt${vp}.i16 $Qd, $Qm */ + ARM_MVE_VMOVNi16th /* 1322 */, ARM_INS_VMOVNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmovnb${vp}.i32 $Qd, $Qm */ + ARM_MVE_VMOVNi32bh /* 1323 */, ARM_INS_VMOVNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmovnt${vp}.i32 $Qd, $Qm */ + ARM_MVE_VMOVNi32th /* 1324 */, ARM_INS_VMOVNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.32 $Rt, $Qd$Idx */ + ARM_MVE_VMOV_from_lane_32 /* 1325 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegsV8_1M, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.s16 $Rt, $Qd$Idx */ + ARM_MVE_VMOV_from_lane_s16 /* 1326 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.s8 $Rt, $Qd$Idx */ + ARM_MVE_VMOV_from_lane_s8 /* 1327 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.u16 $Rt, $Qd$Idx */ + ARM_MVE_VMOV_from_lane_u16 /* 1328 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.u8 $Rt, $Qd$Idx */ + ARM_MVE_VMOV_from_lane_u8 /* 1329 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p} $Qd$idx, $QdSrc$idx2, $Rt, $Rt2 */ + ARM_MVE_VMOV_q_rr /* 1330 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p} $Rt, $Rt2, $Qd$idx, $Qd$idx2 */ + ARM_MVE_VMOV_rr_q /* 1331 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.16 $Qd$Idx, $Rt */ + ARM_MVE_VMOV_to_lane_16 /* 1332 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.32 $Qd$Idx, $Rt */ + ARM_MVE_VMOV_to_lane_32 /* 1333 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegsV8_1M, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.8 $Qd$Idx, $Rt */ + ARM_MVE_VMOV_to_lane_8 /* 1334 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${vp}.f32 $Qd, $imm */ + ARM_MVE_VMOVimmf32 /* 1335 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${vp}.i16 $Qd, $imm */ + ARM_MVE_VMOVimmi16 /* 1336 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${vp}.i32 $Qd, $imm */ + ARM_MVE_VMOVimmi32 /* 1337 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${vp}.i64 $Qd, $imm */ + ARM_MVE_VMOVimmi64 /* 1338 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmov${vp}.i8 $Qd, $imm */ + ARM_MVE_VMOVimmi8 /* 1339 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmulh${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VMULHs16 /* 1340 */, ARM_INS_VMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmulh${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VMULHs32 /* 1341 */, ARM_INS_VMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmulh${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VMULHs8 /* 1342 */, ARM_INS_VMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmulh${vp}.u16 $Qd, $Qn, $Qm */ + ARM_MVE_VMULHu16 /* 1343 */, ARM_INS_VMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmulh${vp}.u32 $Qd, $Qn, $Qm */ + ARM_MVE_VMULHu32 /* 1344 */, ARM_INS_VMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmulh${vp}.u8 $Qd, $Qn, $Qm */ + ARM_MVE_VMULHu8 /* 1345 */, ARM_INS_VMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullb${vp}.p16 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLBp16 /* 1346 */, ARM_INS_VMULLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullb${vp}.p8 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLBp8 /* 1347 */, ARM_INS_VMULLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullb${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLBs16 /* 1348 */, ARM_INS_VMULLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullb${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLBs32 /* 1349 */, ARM_INS_VMULLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullb${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLBs8 /* 1350 */, ARM_INS_VMULLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullb${vp}.u16 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLBu16 /* 1351 */, ARM_INS_VMULLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullb${vp}.u32 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLBu32 /* 1352 */, ARM_INS_VMULLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullb${vp}.u8 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLBu8 /* 1353 */, ARM_INS_VMULLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullt${vp}.p16 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLTp16 /* 1354 */, ARM_INS_VMULLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullt${vp}.p8 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLTp8 /* 1355 */, ARM_INS_VMULLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullt${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLTs16 /* 1356 */, ARM_INS_VMULLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullt${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLTs32 /* 1357 */, ARM_INS_VMULLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullt${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLTs8 /* 1358 */, ARM_INS_VMULLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullt${vp}.u16 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLTu16 /* 1359 */, ARM_INS_VMULLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullt${vp}.u32 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLTu32 /* 1360 */, ARM_INS_VMULLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmullt${vp}.u8 $Qd, $Qn, $Qm */ + ARM_MVE_VMULLTu8 /* 1361 */, ARM_INS_VMULLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmul${vp}.f16 $Qd, $Qn, $Rm */ + ARM_MVE_VMUL_qr_f16 /* 1362 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vmul${vp}.f32 $Qd, $Qn, $Rm */ + ARM_MVE_VMUL_qr_f32 /* 1363 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vmul${vp}.i16 $Qd, $Qn, $Rm */ + ARM_MVE_VMUL_qr_i16 /* 1364 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmul${vp}.i32 $Qd, $Qn, $Rm */ + ARM_MVE_VMUL_qr_i32 /* 1365 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmul${vp}.i8 $Qd, $Qn, $Rm */ + ARM_MVE_VMUL_qr_i8 /* 1366 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmul${vp}.f16 $Qd, $Qn, $Qm */ + ARM_MVE_VMULf16 /* 1367 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vmul${vp}.f32 $Qd, $Qn, $Qm */ + ARM_MVE_VMULf32 /* 1368 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vmul${vp}.i16 $Qd, $Qn, $Qm */ + ARM_MVE_VMULi16 /* 1369 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmul${vp}.i32 $Qd, $Qn, $Qm */ + ARM_MVE_VMULi32 /* 1370 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmul${vp}.i8 $Qd, $Qn, $Qm */ + ARM_MVE_VMULi8 /* 1371 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmvn${vp} $Qd, $Qm */ + ARM_MVE_VMVN /* 1372 */, ARM_INS_VMVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmvn${vp}.i16 $Qd, $imm */ + ARM_MVE_VMVNimmi16 /* 1373 */, ARM_INS_VMVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmvn${vp}.i32 $Qd, $imm */ + ARM_MVE_VMVNimmi32 /* 1374 */, ARM_INS_VMVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vneg${vp}.f16 $Qd, $Qm */ + ARM_MVE_VNEGf16 /* 1375 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vneg${vp}.f32 $Qd, $Qm */ + ARM_MVE_VNEGf32 /* 1376 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vneg${vp}.s16 $Qd, $Qm */ + ARM_MVE_VNEGs16 /* 1377 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vneg${vp}.s32 $Qd, $Qm */ + ARM_MVE_VNEGs32 /* 1378 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vneg${vp}.s8 $Qd, $Qm */ + ARM_MVE_VNEGs8 /* 1379 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vorn${vp} $Qd, $Qn, $Qm */ + ARM_MVE_VORN /* 1380 */, ARM_INS_VORN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vorr${vp} $Qd, $Qn, $Qm */ + ARM_MVE_VORR /* 1381 */, ARM_INS_VORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vorr${vp}.i16 $Qd, $imm */ + ARM_MVE_VORRimmi16 /* 1382 */, ARM_INS_VORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vorr${vp}.i32 $Qd, $imm */ + ARM_MVE_VORRimmi32 /* 1383 */, ARM_INS_VORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpnot${vp} */ + ARM_MVE_VPNOT /* 1384 */, ARM_INS_VPNOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpsel${vp} $Qd, $Qn, $Qm */ + ARM_MVE_VPSEL /* 1385 */, ARM_INS_VPSEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpst${Mk} */ + ARM_MVE_VPST /* 1386 */, ARM_INS_VPST, + #ifndef CAPSTONE_DIET + { ARM_REG_VPR, 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.i8 $fc, $Qn, $Qm */ + ARM_MVE_VPTv16i8 /* 1387 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.i8 $fc, $Qn, $Rm */ + ARM_MVE_VPTv16i8r /* 1388 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.s8 $fc, $Qn, $Qm */ + ARM_MVE_VPTv16s8 /* 1389 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.s8 $fc, $Qn, $Rm */ + ARM_MVE_VPTv16s8r /* 1390 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.u8 $fc, $Qn, $Qm */ + ARM_MVE_VPTv16u8 /* 1391 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.u8 $fc, $Qn, $Rm */ + ARM_MVE_VPTv16u8r /* 1392 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.f32 $fc, $Qn, $Qm */ + ARM_MVE_VPTv4f32 /* 1393 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.f32 $fc, $Qn, $Rm */ + ARM_MVE_VPTv4f32r /* 1394 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.i32 $fc, $Qn, $Qm */ + ARM_MVE_VPTv4i32 /* 1395 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.i32 $fc, $Qn, $Rm */ + ARM_MVE_VPTv4i32r /* 1396 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.s32 $fc, $Qn, $Qm */ + ARM_MVE_VPTv4s32 /* 1397 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.s32 $fc, $Qn, $Rm */ + ARM_MVE_VPTv4s32r /* 1398 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.u32 $fc, $Qn, $Qm */ + ARM_MVE_VPTv4u32 /* 1399 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.u32 $fc, $Qn, $Rm */ + ARM_MVE_VPTv4u32r /* 1400 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.f16 $fc, $Qn, $Qm */ + ARM_MVE_VPTv8f16 /* 1401 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.f16 $fc, $Qn, $Rm */ + ARM_MVE_VPTv8f16r /* 1402 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.i16 $fc, $Qn, $Qm */ + ARM_MVE_VPTv8i16 /* 1403 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.i16 $fc, $Qn, $Rm */ + ARM_MVE_VPTv8i16r /* 1404 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.s16 $fc, $Qn, $Qm */ + ARM_MVE_VPTv8s16 /* 1405 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.s16 $fc, $Qn, $Rm */ + ARM_MVE_VPTv8s16r /* 1406 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.u16 $fc, $Qn, $Qm */ + ARM_MVE_VPTv8u16 /* 1407 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vpt${Mk}.u16 $fc, $Qn, $Rm */ + ARM_MVE_VPTv8u16r /* 1408 */, ARM_INS_VPT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqabs${vp}.s16 $Qd, $Qm */ + ARM_MVE_VQABSs16 /* 1409 */, ARM_INS_VQABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqabs${vp}.s32 $Qd, $Qm */ + ARM_MVE_VQABSs32 /* 1410 */, ARM_INS_VQABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqabs${vp}.s8 $Qd, $Qm */ + ARM_MVE_VQABSs8 /* 1411 */, ARM_INS_VQABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${vp}.s16 $Qd, $Qn, $Rm */ + ARM_MVE_VQADD_qr_s16 /* 1412 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${vp}.s32 $Qd, $Qn, $Rm */ + ARM_MVE_VQADD_qr_s32 /* 1413 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${vp}.s8 $Qd, $Qn, $Rm */ + ARM_MVE_VQADD_qr_s8 /* 1414 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${vp}.u16 $Qd, $Qn, $Rm */ + ARM_MVE_VQADD_qr_u16 /* 1415 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${vp}.u32 $Qd, $Qn, $Rm */ + ARM_MVE_VQADD_qr_u32 /* 1416 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${vp}.u8 $Qd, $Qn, $Rm */ + ARM_MVE_VQADD_qr_u8 /* 1417 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQADDs16 /* 1418 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQADDs32 /* 1419 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VQADDs8 /* 1420 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${vp}.u16 $Qd, $Qn, $Qm */ + ARM_MVE_VQADDu16 /* 1421 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${vp}.u32 $Qd, $Qn, $Qm */ + ARM_MVE_VQADDu32 /* 1422 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${vp}.u8 $Qd, $Qn, $Qm */ + ARM_MVE_VQADDu8 /* 1423 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmladhx${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMLADHXs16 /* 1424 */, ARM_INS_VQDMLADHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmladhx${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMLADHXs32 /* 1425 */, ARM_INS_VQDMLADHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmladhx${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMLADHXs8 /* 1426 */, ARM_INS_VQDMLADHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmladh${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMLADHs16 /* 1427 */, ARM_INS_VQDMLADH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmladh${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMLADHs32 /* 1428 */, ARM_INS_VQDMLADH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmladh${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMLADHs8 /* 1429 */, ARM_INS_VQDMLADH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlah${vp}.s16 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMLAH_qrs16 /* 1430 */, ARM_INS_VQDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlah${vp}.s32 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMLAH_qrs32 /* 1431 */, ARM_INS_VQDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlah${vp}.s8 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMLAH_qrs8 /* 1432 */, ARM_INS_VQDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlash${vp}.s16 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMLASH_qrs16 /* 1433 */, ARM_INS_VQDMLASH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlash${vp}.s32 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMLASH_qrs32 /* 1434 */, ARM_INS_VQDMLASH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlash${vp}.s8 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMLASH_qrs8 /* 1435 */, ARM_INS_VQDMLASH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlsdhx${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMLSDHXs16 /* 1436 */, ARM_INS_VQDMLSDHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlsdhx${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMLSDHXs32 /* 1437 */, ARM_INS_VQDMLSDHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlsdhx${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMLSDHXs8 /* 1438 */, ARM_INS_VQDMLSDHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlsdh${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMLSDHs16 /* 1439 */, ARM_INS_VQDMLSDH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlsdh${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMLSDHs32 /* 1440 */, ARM_INS_VQDMLSDH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlsdh${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMLSDHs8 /* 1441 */, ARM_INS_VQDMLSDH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${vp}.s16 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMULH_qr_s16 /* 1442 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${vp}.s32 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMULH_qr_s32 /* 1443 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${vp}.s8 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMULH_qr_s8 /* 1444 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMULHi16 /* 1445 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMULHi32 /* 1446 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMULHi8 /* 1447 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmullb${vp}.s16 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMULL_qr_s16bh /* 1448 */, ARM_INS_VQDMULLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmullt${vp}.s16 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMULL_qr_s16th /* 1449 */, ARM_INS_VQDMULLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmullb${vp}.s32 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMULL_qr_s32bh /* 1450 */, ARM_INS_VQDMULLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmullt${vp}.s32 $Qd, $Qn, $Rm */ + ARM_MVE_VQDMULL_qr_s32th /* 1451 */, ARM_INS_VQDMULLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmullb${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMULLs16bh /* 1452 */, ARM_INS_VQDMULLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmullt${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMULLs16th /* 1453 */, ARM_INS_VQDMULLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmullb${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMULLs32bh /* 1454 */, ARM_INS_VQDMULLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqdmullt${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQDMULLs32th /* 1455 */, ARM_INS_VQDMULLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqmovnb${vp}.s16 $Qd, $Qm */ + ARM_MVE_VQMOVNs16bh /* 1456 */, ARM_INS_VQMOVNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqmovnt${vp}.s16 $Qd, $Qm */ + ARM_MVE_VQMOVNs16th /* 1457 */, ARM_INS_VQMOVNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqmovnb${vp}.s32 $Qd, $Qm */ + ARM_MVE_VQMOVNs32bh /* 1458 */, ARM_INS_VQMOVNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqmovnt${vp}.s32 $Qd, $Qm */ + ARM_MVE_VQMOVNs32th /* 1459 */, ARM_INS_VQMOVNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqmovnb${vp}.u16 $Qd, $Qm */ + ARM_MVE_VQMOVNu16bh /* 1460 */, ARM_INS_VQMOVNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqmovnt${vp}.u16 $Qd, $Qm */ + ARM_MVE_VQMOVNu16th /* 1461 */, ARM_INS_VQMOVNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqmovnb${vp}.u32 $Qd, $Qm */ + ARM_MVE_VQMOVNu32bh /* 1462 */, ARM_INS_VQMOVNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqmovnt${vp}.u32 $Qd, $Qm */ + ARM_MVE_VQMOVNu32th /* 1463 */, ARM_INS_VQMOVNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqmovunb${vp}.s16 $Qd, $Qm */ + ARM_MVE_VQMOVUNs16bh /* 1464 */, ARM_INS_VQMOVUNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqmovunt${vp}.s16 $Qd, $Qm */ + ARM_MVE_VQMOVUNs16th /* 1465 */, ARM_INS_VQMOVUNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqmovunb${vp}.s32 $Qd, $Qm */ + ARM_MVE_VQMOVUNs32bh /* 1466 */, ARM_INS_VQMOVUNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqmovunt${vp}.s32 $Qd, $Qm */ + ARM_MVE_VQMOVUNs32th /* 1467 */, ARM_INS_VQMOVUNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqneg${vp}.s16 $Qd, $Qm */ + ARM_MVE_VQNEGs16 /* 1468 */, ARM_INS_VQNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqneg${vp}.s32 $Qd, $Qm */ + ARM_MVE_VQNEGs32 /* 1469 */, ARM_INS_VQNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqneg${vp}.s8 $Qd, $Qm */ + ARM_MVE_VQNEGs8 /* 1470 */, ARM_INS_VQNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmladhx${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMLADHXs16 /* 1471 */, ARM_INS_VQRDMLADHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmladhx${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMLADHXs32 /* 1472 */, ARM_INS_VQRDMLADHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmladhx${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMLADHXs8 /* 1473 */, ARM_INS_VQRDMLADHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmladh${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMLADHs16 /* 1474 */, ARM_INS_VQRDMLADH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmladh${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMLADHs32 /* 1475 */, ARM_INS_VQRDMLADH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmladh${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMLADHs8 /* 1476 */, ARM_INS_VQRDMLADH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlah${vp}.s16 $Qd, $Qn, $Rm */ + ARM_MVE_VQRDMLAH_qrs16 /* 1477 */, ARM_INS_VQRDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlah${vp}.s32 $Qd, $Qn, $Rm */ + ARM_MVE_VQRDMLAH_qrs32 /* 1478 */, ARM_INS_VQRDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlah${vp}.s8 $Qd, $Qn, $Rm */ + ARM_MVE_VQRDMLAH_qrs8 /* 1479 */, ARM_INS_VQRDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlash${vp}.s16 $Qd, $Qn, $Rm */ + ARM_MVE_VQRDMLASH_qrs16 /* 1480 */, ARM_INS_VQRDMLASH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlash${vp}.s32 $Qd, $Qn, $Rm */ + ARM_MVE_VQRDMLASH_qrs32 /* 1481 */, ARM_INS_VQRDMLASH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlash${vp}.s8 $Qd, $Qn, $Rm */ + ARM_MVE_VQRDMLASH_qrs8 /* 1482 */, ARM_INS_VQRDMLASH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsdhx${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMLSDHXs16 /* 1483 */, ARM_INS_VQRDMLSDHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsdhx${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMLSDHXs32 /* 1484 */, ARM_INS_VQRDMLSDHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsdhx${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMLSDHXs8 /* 1485 */, ARM_INS_VQRDMLSDHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsdh${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMLSDHs16 /* 1486 */, ARM_INS_VQRDMLSDH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsdh${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMLSDHs32 /* 1487 */, ARM_INS_VQRDMLSDH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsdh${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMLSDHs8 /* 1488 */, ARM_INS_VQRDMLSDH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${vp}.s16 $Qd, $Qn, $Rm */ + ARM_MVE_VQRDMULH_qr_s16 /* 1489 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${vp}.s32 $Qd, $Qn, $Rm */ + ARM_MVE_VQRDMULH_qr_s32 /* 1490 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${vp}.s8 $Qd, $Qn, $Rm */ + ARM_MVE_VQRDMULH_qr_s8 /* 1491 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMULHi16 /* 1492 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMULHi32 /* 1493 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VQRDMULHi8 /* 1494 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${vp}.s16 $Qd, $Qm, $Qn */ + ARM_MVE_VQRSHL_by_vecs16 /* 1495 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${vp}.s32 $Qd, $Qm, $Qn */ + ARM_MVE_VQRSHL_by_vecs32 /* 1496 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${vp}.s8 $Qd, $Qm, $Qn */ + ARM_MVE_VQRSHL_by_vecs8 /* 1497 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${vp}.u16 $Qd, $Qm, $Qn */ + ARM_MVE_VQRSHL_by_vecu16 /* 1498 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${vp}.u32 $Qd, $Qm, $Qn */ + ARM_MVE_VQRSHL_by_vecu32 /* 1499 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${vp}.u8 $Qd, $Qm, $Qn */ + ARM_MVE_VQRSHL_by_vecu8 /* 1500 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${vp}.s16 $Qd, $Rm */ + ARM_MVE_VQRSHL_qrs16 /* 1501 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${vp}.s32 $Qd, $Rm */ + ARM_MVE_VQRSHL_qrs32 /* 1502 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${vp}.s8 $Qd, $Rm */ + ARM_MVE_VQRSHL_qrs8 /* 1503 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${vp}.u16 $Qd, $Rm */ + ARM_MVE_VQRSHL_qru16 /* 1504 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${vp}.u32 $Qd, $Rm */ + ARM_MVE_VQRSHL_qru32 /* 1505 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${vp}.u8 $Qd, $Rm */ + ARM_MVE_VQRSHL_qru8 /* 1506 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrnb${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VQRSHRNbhs16 /* 1507 */, ARM_INS_VQRSHRNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrnb${vp}.s32 $Qd, $Qm, $imm */ + ARM_MVE_VQRSHRNbhs32 /* 1508 */, ARM_INS_VQRSHRNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrnb${vp}.u16 $Qd, $Qm, $imm */ + ARM_MVE_VQRSHRNbhu16 /* 1509 */, ARM_INS_VQRSHRNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrnb${vp}.u32 $Qd, $Qm, $imm */ + ARM_MVE_VQRSHRNbhu32 /* 1510 */, ARM_INS_VQRSHRNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrnt${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VQRSHRNths16 /* 1511 */, ARM_INS_VQRSHRNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrnt${vp}.s32 $Qd, $Qm, $imm */ + ARM_MVE_VQRSHRNths32 /* 1512 */, ARM_INS_VQRSHRNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrnt${vp}.u16 $Qd, $Qm, $imm */ + ARM_MVE_VQRSHRNthu16 /* 1513 */, ARM_INS_VQRSHRNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrnt${vp}.u32 $Qd, $Qm, $imm */ + ARM_MVE_VQRSHRNthu32 /* 1514 */, ARM_INS_VQRSHRNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrunb${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VQRSHRUNs16bh /* 1515 */, ARM_INS_VQRSHRUNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrunt${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VQRSHRUNs16th /* 1516 */, ARM_INS_VQRSHRUNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrunb${vp}.s32 $Qd, $Qm, $imm */ + ARM_MVE_VQRSHRUNs32bh /* 1517 */, ARM_INS_VQRSHRUNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrunt${vp}.s32 $Qd, $Qm, $imm */ + ARM_MVE_VQRSHRUNs32th /* 1518 */, ARM_INS_VQRSHRUNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshlu${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VQSHLU_imms16 /* 1519 */, ARM_INS_VQSHLU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshlu${vp}.s32 $Qd, $Qm, $imm */ + ARM_MVE_VQSHLU_imms32 /* 1520 */, ARM_INS_VQSHLU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshlu${vp}.s8 $Qd, $Qm, $imm */ + ARM_MVE_VQSHLU_imms8 /* 1521 */, ARM_INS_VQSHLU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.s16 $Qd, $Qm, $Qn */ + ARM_MVE_VQSHL_by_vecs16 /* 1522 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.s32 $Qd, $Qm, $Qn */ + ARM_MVE_VQSHL_by_vecs32 /* 1523 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.s8 $Qd, $Qm, $Qn */ + ARM_MVE_VQSHL_by_vecs8 /* 1524 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.u16 $Qd, $Qm, $Qn */ + ARM_MVE_VQSHL_by_vecu16 /* 1525 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.u32 $Qd, $Qm, $Qn */ + ARM_MVE_VQSHL_by_vecu32 /* 1526 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.u8 $Qd, $Qm, $Qn */ + ARM_MVE_VQSHL_by_vecu8 /* 1527 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.s16 $Qd, $Rm */ + ARM_MVE_VQSHL_qrs16 /* 1528 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.s32 $Qd, $Rm */ + ARM_MVE_VQSHL_qrs32 /* 1529 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.s8 $Qd, $Rm */ + ARM_MVE_VQSHL_qrs8 /* 1530 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.u16 $Qd, $Rm */ + ARM_MVE_VQSHL_qru16 /* 1531 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.u32 $Qd, $Rm */ + ARM_MVE_VQSHL_qru32 /* 1532 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.u8 $Qd, $Rm */ + ARM_MVE_VQSHL_qru8 /* 1533 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VQSHLimms16 /* 1534 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.s32 $Qd, $Qm, $imm */ + ARM_MVE_VQSHLimms32 /* 1535 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.s8 $Qd, $Qm, $imm */ + ARM_MVE_VQSHLimms8 /* 1536 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.u16 $Qd, $Qm, $imm */ + ARM_MVE_VQSHLimmu16 /* 1537 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.u32 $Qd, $Qm, $imm */ + ARM_MVE_VQSHLimmu32 /* 1538 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${vp}.u8 $Qd, $Qm, $imm */ + ARM_MVE_VQSHLimmu8 /* 1539 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshrnb${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VQSHRNbhs16 /* 1540 */, ARM_INS_VQSHRNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshrnb${vp}.s32 $Qd, $Qm, $imm */ + ARM_MVE_VQSHRNbhs32 /* 1541 */, ARM_INS_VQSHRNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshrnb${vp}.u16 $Qd, $Qm, $imm */ + ARM_MVE_VQSHRNbhu16 /* 1542 */, ARM_INS_VQSHRNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshrnb${vp}.u32 $Qd, $Qm, $imm */ + ARM_MVE_VQSHRNbhu32 /* 1543 */, ARM_INS_VQSHRNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshrnt${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VQSHRNths16 /* 1544 */, ARM_INS_VQSHRNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshrnt${vp}.s32 $Qd, $Qm, $imm */ + ARM_MVE_VQSHRNths32 /* 1545 */, ARM_INS_VQSHRNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshrnt${vp}.u16 $Qd, $Qm, $imm */ + ARM_MVE_VQSHRNthu16 /* 1546 */, ARM_INS_VQSHRNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshrnt${vp}.u32 $Qd, $Qm, $imm */ + ARM_MVE_VQSHRNthu32 /* 1547 */, ARM_INS_VQSHRNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshrunb${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VQSHRUNs16bh /* 1548 */, ARM_INS_VQSHRUNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshrunt${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VQSHRUNs16th /* 1549 */, ARM_INS_VQSHRUNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshrunb${vp}.s32 $Qd, $Qm, $imm */ + ARM_MVE_VQSHRUNs32bh /* 1550 */, ARM_INS_VQSHRUNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqshrunt${vp}.s32 $Qd, $Qm, $imm */ + ARM_MVE_VQSHRUNs32th /* 1551 */, ARM_INS_VQSHRUNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${vp}.s16 $Qd, $Qn, $Rm */ + ARM_MVE_VQSUB_qr_s16 /* 1552 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${vp}.s32 $Qd, $Qn, $Rm */ + ARM_MVE_VQSUB_qr_s32 /* 1553 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${vp}.s8 $Qd, $Qn, $Rm */ + ARM_MVE_VQSUB_qr_s8 /* 1554 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${vp}.u16 $Qd, $Qn, $Rm */ + ARM_MVE_VQSUB_qr_u16 /* 1555 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${vp}.u32 $Qd, $Qn, $Rm */ + ARM_MVE_VQSUB_qr_u32 /* 1556 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${vp}.u8 $Qd, $Qn, $Rm */ + ARM_MVE_VQSUB_qr_u8 /* 1557 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VQSUBs16 /* 1558 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VQSUBs32 /* 1559 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VQSUBs8 /* 1560 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${vp}.u16 $Qd, $Qn, $Qm */ + ARM_MVE_VQSUBu16 /* 1561 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${vp}.u32 $Qd, $Qn, $Qm */ + ARM_MVE_VQSUBu32 /* 1562 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${vp}.u8 $Qd, $Qn, $Qm */ + ARM_MVE_VQSUBu8 /* 1563 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrev16${vp}.8 $Qd, $Qm */ + ARM_MVE_VREV16_8 /* 1564 */, ARM_INS_VREV16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrev32${vp}.16 $Qd, $Qm */ + ARM_MVE_VREV32_16 /* 1565 */, ARM_INS_VREV32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrev32${vp}.8 $Qd, $Qm */ + ARM_MVE_VREV32_8 /* 1566 */, ARM_INS_VREV32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrev64${vp}.16 $Qd, $Qm */ + ARM_MVE_VREV64_16 /* 1567 */, ARM_INS_VREV64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrev64${vp}.32 $Qd, $Qm */ + ARM_MVE_VREV64_32 /* 1568 */, ARM_INS_VREV64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrev64${vp}.8 $Qd, $Qm */ + ARM_MVE_VREV64_8 /* 1569 */, ARM_INS_VREV64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VRHADDs16 /* 1570 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VRHADDs32 /* 1571 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VRHADDs8 /* 1572 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${vp}.u16 $Qd, $Qn, $Qm */ + ARM_MVE_VRHADDu16 /* 1573 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${vp}.u32 $Qd, $Qn, $Qm */ + ARM_MVE_VRHADDu32 /* 1574 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${vp}.u8 $Qd, $Qn, $Qm */ + ARM_MVE_VRHADDu8 /* 1575 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrinta${vp}.f16 $Qd, $Qm */ + ARM_MVE_VRINTf16A /* 1576 */, ARM_INS_VRINTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vrintm${vp}.f16 $Qd, $Qm */ + ARM_MVE_VRINTf16M /* 1577 */, ARM_INS_VRINTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vrintn${vp}.f16 $Qd, $Qm */ + ARM_MVE_VRINTf16N /* 1578 */, ARM_INS_VRINTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vrintp${vp}.f16 $Qd, $Qm */ + ARM_MVE_VRINTf16P /* 1579 */, ARM_INS_VRINTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vrintx${vp}.f16 $Qd, $Qm */ + ARM_MVE_VRINTf16X /* 1580 */, ARM_INS_VRINTX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vrintz${vp}.f16 $Qd, $Qm */ + ARM_MVE_VRINTf16Z /* 1581 */, ARM_INS_VRINTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vrinta${vp}.f32 $Qd, $Qm */ + ARM_MVE_VRINTf32A /* 1582 */, ARM_INS_VRINTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vrintm${vp}.f32 $Qd, $Qm */ + ARM_MVE_VRINTf32M /* 1583 */, ARM_INS_VRINTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vrintn${vp}.f32 $Qd, $Qm */ + ARM_MVE_VRINTf32N /* 1584 */, ARM_INS_VRINTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vrintp${vp}.f32 $Qd, $Qm */ + ARM_MVE_VRINTf32P /* 1585 */, ARM_INS_VRINTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vrintx${vp}.f32 $Qd, $Qm */ + ARM_MVE_VRINTf32X /* 1586 */, ARM_INS_VRINTX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vrintz${vp}.f32 $Qd, $Qm */ + ARM_MVE_VRINTf32Z /* 1587 */, ARM_INS_VRINTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vrmlaldavha${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VRMLALDAVHas32 /* 1588 */, ARM_INS_VRMLALDAVHA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmlaldavha${vp}.u32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VRMLALDAVHau32 /* 1589 */, ARM_INS_VRMLALDAVHA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmlaldavhax${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VRMLALDAVHaxs32 /* 1590 */, ARM_INS_VRMLALDAVHAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmlaldavh${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VRMLALDAVHs32 /* 1591 */, ARM_INS_VRMLALDAVH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmlaldavh${vp}.u32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VRMLALDAVHu32 /* 1592 */, ARM_INS_VRMLALDAVH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmlaldavhx${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VRMLALDAVHxs32 /* 1593 */, ARM_INS_VRMLALDAVHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmlsldavha${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VRMLSLDAVHas32 /* 1594 */, ARM_INS_VRMLSLDAVHA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmlsldavhax${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VRMLSLDAVHaxs32 /* 1595 */, ARM_INS_VRMLSLDAVHAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmlsldavh${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VRMLSLDAVHs32 /* 1596 */, ARM_INS_VRMLSLDAVH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmlsldavhx${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + ARM_MVE_VRMLSLDAVHxs32 /* 1597 */, ARM_INS_VRMLSLDAVHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmulh${vp}.s16 $Qd, $Qn, $Qm */ + ARM_MVE_VRMULHs16 /* 1598 */, ARM_INS_VRMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmulh${vp}.s32 $Qd, $Qn, $Qm */ + ARM_MVE_VRMULHs32 /* 1599 */, ARM_INS_VRMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmulh${vp}.s8 $Qd, $Qn, $Qm */ + ARM_MVE_VRMULHs8 /* 1600 */, ARM_INS_VRMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmulh${vp}.u16 $Qd, $Qn, $Qm */ + ARM_MVE_VRMULHu16 /* 1601 */, ARM_INS_VRMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmulh${vp}.u32 $Qd, $Qn, $Qm */ + ARM_MVE_VRMULHu32 /* 1602 */, ARM_INS_VRMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrmulh${vp}.u8 $Qd, $Qn, $Qm */ + ARM_MVE_VRMULHu8 /* 1603 */, ARM_INS_VRMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${vp}.s16 $Qd, $Qm, $Qn */ + ARM_MVE_VRSHL_by_vecs16 /* 1604 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${vp}.s32 $Qd, $Qm, $Qn */ + ARM_MVE_VRSHL_by_vecs32 /* 1605 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${vp}.s8 $Qd, $Qm, $Qn */ + ARM_MVE_VRSHL_by_vecs8 /* 1606 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${vp}.u16 $Qd, $Qm, $Qn */ + ARM_MVE_VRSHL_by_vecu16 /* 1607 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${vp}.u32 $Qd, $Qm, $Qn */ + ARM_MVE_VRSHL_by_vecu32 /* 1608 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${vp}.u8 $Qd, $Qm, $Qn */ + ARM_MVE_VRSHL_by_vecu8 /* 1609 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${vp}.s16 $Qd, $Rm */ + ARM_MVE_VRSHL_qrs16 /* 1610 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${vp}.s32 $Qd, $Rm */ + ARM_MVE_VRSHL_qrs32 /* 1611 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${vp}.s8 $Qd, $Rm */ + ARM_MVE_VRSHL_qrs8 /* 1612 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${vp}.u16 $Qd, $Rm */ + ARM_MVE_VRSHL_qru16 /* 1613 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${vp}.u32 $Qd, $Rm */ + ARM_MVE_VRSHL_qru32 /* 1614 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${vp}.u8 $Qd, $Rm */ + ARM_MVE_VRSHL_qru8 /* 1615 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshrnb${vp}.i16 $Qd, $Qm, $imm */ + ARM_MVE_VRSHRNi16bh /* 1616 */, ARM_INS_VRSHRNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshrnt${vp}.i16 $Qd, $Qm, $imm */ + ARM_MVE_VRSHRNi16th /* 1617 */, ARM_INS_VRSHRNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshrnb${vp}.i32 $Qd, $Qm, $imm */ + ARM_MVE_VRSHRNi32bh /* 1618 */, ARM_INS_VRSHRNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshrnt${vp}.i32 $Qd, $Qm, $imm */ + ARM_MVE_VRSHRNi32th /* 1619 */, ARM_INS_VRSHRNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VRSHR_imms16 /* 1620 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${vp}.s32 $Qd, $Qm, $imm */ + ARM_MVE_VRSHR_imms32 /* 1621 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${vp}.s8 $Qd, $Qm, $imm */ + ARM_MVE_VRSHR_imms8 /* 1622 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${vp}.u16 $Qd, $Qm, $imm */ + ARM_MVE_VRSHR_immu16 /* 1623 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${vp}.u32 $Qd, $Qm, $imm */ + ARM_MVE_VRSHR_immu32 /* 1624 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${vp}.u8 $Qd, $Qm, $imm */ + ARM_MVE_VRSHR_immu8 /* 1625 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsbc${vp}.i32 $Qd, $Qn, $Qm */ + ARM_MVE_VSBC /* 1626 */, ARM_INS_VSBC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsbci${vp}.i32 $Qd, $Qn, $Qm */ + ARM_MVE_VSBCI /* 1627 */, ARM_INS_VSBCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshlc${vp} $QdSrc, $RdmSrc, $imm */ + ARM_MVE_VSHLC /* 1628 */, ARM_INS_VSHLC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllb${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VSHLL_imms16bh /* 1629 */, ARM_INS_VSHLLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllt${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VSHLL_imms16th /* 1630 */, ARM_INS_VSHLLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllb${vp}.s8 $Qd, $Qm, $imm */ + ARM_MVE_VSHLL_imms8bh /* 1631 */, ARM_INS_VSHLLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllt${vp}.s8 $Qd, $Qm, $imm */ + ARM_MVE_VSHLL_imms8th /* 1632 */, ARM_INS_VSHLLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllb${vp}.u16 $Qd, $Qm, $imm */ + ARM_MVE_VSHLL_immu16bh /* 1633 */, ARM_INS_VSHLLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllt${vp}.u16 $Qd, $Qm, $imm */ + ARM_MVE_VSHLL_immu16th /* 1634 */, ARM_INS_VSHLLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllb${vp}.u8 $Qd, $Qm, $imm */ + ARM_MVE_VSHLL_immu8bh /* 1635 */, ARM_INS_VSHLLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllt${vp}.u8 $Qd, $Qm, $imm */ + ARM_MVE_VSHLL_immu8th /* 1636 */, ARM_INS_VSHLLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllb${vp}.s16 $Qd, $Qm, #16 */ + ARM_MVE_VSHLL_lws16bh /* 1637 */, ARM_INS_VSHLLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllt${vp}.s16 $Qd, $Qm, #16 */ + ARM_MVE_VSHLL_lws16th /* 1638 */, ARM_INS_VSHLLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllb${vp}.s8 $Qd, $Qm, #8 */ + ARM_MVE_VSHLL_lws8bh /* 1639 */, ARM_INS_VSHLLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllt${vp}.s8 $Qd, $Qm, #8 */ + ARM_MVE_VSHLL_lws8th /* 1640 */, ARM_INS_VSHLLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllb${vp}.u16 $Qd, $Qm, #16 */ + ARM_MVE_VSHLL_lwu16bh /* 1641 */, ARM_INS_VSHLLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllt${vp}.u16 $Qd, $Qm, #16 */ + ARM_MVE_VSHLL_lwu16th /* 1642 */, ARM_INS_VSHLLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllb${vp}.u8 $Qd, $Qm, #8 */ + ARM_MVE_VSHLL_lwu8bh /* 1643 */, ARM_INS_VSHLLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshllt${vp}.u8 $Qd, $Qm, #8 */ + ARM_MVE_VSHLL_lwu8th /* 1644 */, ARM_INS_VSHLLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.s16 $Qd, $Qm, $Qn */ + ARM_MVE_VSHL_by_vecs16 /* 1645 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.s32 $Qd, $Qm, $Qn */ + ARM_MVE_VSHL_by_vecs32 /* 1646 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.s8 $Qd, $Qm, $Qn */ + ARM_MVE_VSHL_by_vecs8 /* 1647 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.u16 $Qd, $Qm, $Qn */ + ARM_MVE_VSHL_by_vecu16 /* 1648 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.u32 $Qd, $Qm, $Qn */ + ARM_MVE_VSHL_by_vecu32 /* 1649 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.u8 $Qd, $Qm, $Qn */ + ARM_MVE_VSHL_by_vecu8 /* 1650 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.i16 $Qd, $Qm, $imm */ + ARM_MVE_VSHL_immi16 /* 1651 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.i32 $Qd, $Qm, $imm */ + ARM_MVE_VSHL_immi32 /* 1652 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.i8 $Qd, $Qm, $imm */ + ARM_MVE_VSHL_immi8 /* 1653 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.s16 $Qd, $Rm */ + ARM_MVE_VSHL_qrs16 /* 1654 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.s32 $Qd, $Rm */ + ARM_MVE_VSHL_qrs32 /* 1655 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.s8 $Qd, $Rm */ + ARM_MVE_VSHL_qrs8 /* 1656 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.u16 $Qd, $Rm */ + ARM_MVE_VSHL_qru16 /* 1657 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.u32 $Qd, $Rm */ + ARM_MVE_VSHL_qru32 /* 1658 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshl${vp}.u8 $Qd, $Rm */ + ARM_MVE_VSHL_qru8 /* 1659 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshrnb${vp}.i16 $Qd, $Qm, $imm */ + ARM_MVE_VSHRNi16bh /* 1660 */, ARM_INS_VSHRNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshrnt${vp}.i16 $Qd, $Qm, $imm */ + ARM_MVE_VSHRNi16th /* 1661 */, ARM_INS_VSHRNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshrnb${vp}.i32 $Qd, $Qm, $imm */ + ARM_MVE_VSHRNi32bh /* 1662 */, ARM_INS_VSHRNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshrnt${vp}.i32 $Qd, $Qm, $imm */ + ARM_MVE_VSHRNi32th /* 1663 */, ARM_INS_VSHRNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshr${vp}.s16 $Qd, $Qm, $imm */ + ARM_MVE_VSHR_imms16 /* 1664 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshr${vp}.s32 $Qd, $Qm, $imm */ + ARM_MVE_VSHR_imms32 /* 1665 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshr${vp}.s8 $Qd, $Qm, $imm */ + ARM_MVE_VSHR_imms8 /* 1666 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshr${vp}.u16 $Qd, $Qm, $imm */ + ARM_MVE_VSHR_immu16 /* 1667 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshr${vp}.u32 $Qd, $Qm, $imm */ + ARM_MVE_VSHR_immu32 /* 1668 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vshr${vp}.u8 $Qd, $Qm, $imm */ + ARM_MVE_VSHR_immu8 /* 1669 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsli${vp}.16 $Qd, $Qm, $imm */ + ARM_MVE_VSLIimm16 /* 1670 */, ARM_INS_VSLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsli${vp}.32 $Qd, $Qm, $imm */ + ARM_MVE_VSLIimm32 /* 1671 */, ARM_INS_VSLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsli${vp}.8 $Qd, $Qm, $imm */ + ARM_MVE_VSLIimm8 /* 1672 */, ARM_INS_VSLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsri${vp}.16 $Qd, $Qm, $imm */ + ARM_MVE_VSRIimm16 /* 1673 */, ARM_INS_VSRI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsri${vp}.32 $Qd, $Qm, $imm */ + ARM_MVE_VSRIimm32 /* 1674 */, ARM_INS_VSRI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsri${vp}.8 $Qd, $Qm, $imm */ + ARM_MVE_VSRIimm8 /* 1675 */, ARM_INS_VSRI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst20.16 $VQd, $Rn */ + ARM_MVE_VST20_16 /* 1676 */, ARM_INS_VST20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst20.16 $VQd, $Rn! */ + ARM_MVE_VST20_16_wb /* 1677 */, ARM_INS_VST20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst20.32 $VQd, $Rn */ + ARM_MVE_VST20_32 /* 1678 */, ARM_INS_VST20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst20.32 $VQd, $Rn! */ + ARM_MVE_VST20_32_wb /* 1679 */, ARM_INS_VST20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst20.8 $VQd, $Rn */ + ARM_MVE_VST20_8 /* 1680 */, ARM_INS_VST20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst20.8 $VQd, $Rn! */ + ARM_MVE_VST20_8_wb /* 1681 */, ARM_INS_VST20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst21.16 $VQd, $Rn */ + ARM_MVE_VST21_16 /* 1682 */, ARM_INS_VST21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst21.16 $VQd, $Rn! */ + ARM_MVE_VST21_16_wb /* 1683 */, ARM_INS_VST21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst21.32 $VQd, $Rn */ + ARM_MVE_VST21_32 /* 1684 */, ARM_INS_VST21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst21.32 $VQd, $Rn! */ + ARM_MVE_VST21_32_wb /* 1685 */, ARM_INS_VST21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst21.8 $VQd, $Rn */ + ARM_MVE_VST21_8 /* 1686 */, ARM_INS_VST21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst21.8 $VQd, $Rn! */ + ARM_MVE_VST21_8_wb /* 1687 */, ARM_INS_VST21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst40.16 $VQd, $Rn */ + ARM_MVE_VST40_16 /* 1688 */, ARM_INS_VST40, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst40.16 $VQd, $Rn! */ + ARM_MVE_VST40_16_wb /* 1689 */, ARM_INS_VST40, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst40.32 $VQd, $Rn */ + ARM_MVE_VST40_32 /* 1690 */, ARM_INS_VST40, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst40.32 $VQd, $Rn! */ + ARM_MVE_VST40_32_wb /* 1691 */, ARM_INS_VST40, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst40.8 $VQd, $Rn */ + ARM_MVE_VST40_8 /* 1692 */, ARM_INS_VST40, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst40.8 $VQd, $Rn! */ + ARM_MVE_VST40_8_wb /* 1693 */, ARM_INS_VST40, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst41.16 $VQd, $Rn */ + ARM_MVE_VST41_16 /* 1694 */, ARM_INS_VST41, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst41.16 $VQd, $Rn! */ + ARM_MVE_VST41_16_wb /* 1695 */, ARM_INS_VST41, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst41.32 $VQd, $Rn */ + ARM_MVE_VST41_32 /* 1696 */, ARM_INS_VST41, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst41.32 $VQd, $Rn! */ + ARM_MVE_VST41_32_wb /* 1697 */, ARM_INS_VST41, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst41.8 $VQd, $Rn */ + ARM_MVE_VST41_8 /* 1698 */, ARM_INS_VST41, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst41.8 $VQd, $Rn! */ + ARM_MVE_VST41_8_wb /* 1699 */, ARM_INS_VST41, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst42.16 $VQd, $Rn */ + ARM_MVE_VST42_16 /* 1700 */, ARM_INS_VST42, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst42.16 $VQd, $Rn! */ + ARM_MVE_VST42_16_wb /* 1701 */, ARM_INS_VST42, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst42.32 $VQd, $Rn */ + ARM_MVE_VST42_32 /* 1702 */, ARM_INS_VST42, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst42.32 $VQd, $Rn! */ + ARM_MVE_VST42_32_wb /* 1703 */, ARM_INS_VST42, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst42.8 $VQd, $Rn */ + ARM_MVE_VST42_8 /* 1704 */, ARM_INS_VST42, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst42.8 $VQd, $Rn! */ + ARM_MVE_VST42_8_wb /* 1705 */, ARM_INS_VST42, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst43.16 $VQd, $Rn */ + ARM_MVE_VST43_16 /* 1706 */, ARM_INS_VST43, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst43.16 $VQd, $Rn! */ + ARM_MVE_VST43_16_wb /* 1707 */, ARM_INS_VST43, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst43.32 $VQd, $Rn */ + ARM_MVE_VST43_32 /* 1708 */, ARM_INS_VST43, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst43.32 $VQd, $Rn! */ + ARM_MVE_VST43_32_wb /* 1709 */, ARM_INS_VST43, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst43.8 $VQd, $Rn */ + ARM_MVE_VST43_8 /* 1710 */, ARM_INS_VST43, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vst43.8 $VQd, $Rn! */ + ARM_MVE_VST43_8_wb /* 1711 */, ARM_INS_VST43, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrb${vp}.16 $Qd, $addr */ + ARM_MVE_VSTRB16 /* 1712 */, ARM_INS_VSTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrb${vp}.16 $Qd, $Rn$addr */ + ARM_MVE_VSTRB16_post /* 1713 */, ARM_INS_VSTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrb${vp}.16 $Qd, $addr! */ + ARM_MVE_VSTRB16_pre /* 1714 */, ARM_INS_VSTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrb${vp}.16 $Qd, $addr */ + ARM_MVE_VSTRB16_rq /* 1715 */, ARM_INS_VSTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrb${vp}.32 $Qd, $addr */ + ARM_MVE_VSTRB32 /* 1716 */, ARM_INS_VSTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrb${vp}.32 $Qd, $Rn$addr */ + ARM_MVE_VSTRB32_post /* 1717 */, ARM_INS_VSTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrb${vp}.32 $Qd, $addr! */ + ARM_MVE_VSTRB32_pre /* 1718 */, ARM_INS_VSTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrb${vp}.32 $Qd, $addr */ + ARM_MVE_VSTRB32_rq /* 1719 */, ARM_INS_VSTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrb${vp}.8 $Qd, $addr */ + ARM_MVE_VSTRB8_rq /* 1720 */, ARM_INS_VSTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrb${vp}.8 $Qd, $addr */ + ARM_MVE_VSTRBU8 /* 1721 */, ARM_INS_VSTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrb${vp}.8 $Qd, $Rn$addr */ + ARM_MVE_VSTRBU8_post /* 1722 */, ARM_INS_VSTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrb${vp}.8 $Qd, $addr! */ + ARM_MVE_VSTRBU8_pre /* 1723 */, ARM_INS_VSTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrd${vp}.64 $Qd, $addr */ + ARM_MVE_VSTRD64_qi /* 1724 */, ARM_INS_VSTRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrd${vp}.64 $Qd, $addr! */ + ARM_MVE_VSTRD64_qi_pre /* 1725 */, ARM_INS_VSTRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrd${vp}.64 $Qd, $addr */ + ARM_MVE_VSTRD64_rq /* 1726 */, ARM_INS_VSTRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrd${vp}.64 $Qd, $addr */ + ARM_MVE_VSTRD64_rq_u /* 1727 */, ARM_INS_VSTRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrh${vp}.16 $Qd, $addr */ + ARM_MVE_VSTRH16_rq /* 1728 */, ARM_INS_VSTRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrh${vp}.16 $Qd, $addr */ + ARM_MVE_VSTRH16_rq_u /* 1729 */, ARM_INS_VSTRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrh${vp}.32 $Qd, $addr */ + ARM_MVE_VSTRH32 /* 1730 */, ARM_INS_VSTRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrh${vp}.32 $Qd, $Rn$addr */ + ARM_MVE_VSTRH32_post /* 1731 */, ARM_INS_VSTRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrh${vp}.32 $Qd, $addr! */ + ARM_MVE_VSTRH32_pre /* 1732 */, ARM_INS_VSTRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrh${vp}.32 $Qd, $addr */ + ARM_MVE_VSTRH32_rq /* 1733 */, ARM_INS_VSTRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrh${vp}.32 $Qd, $addr */ + ARM_MVE_VSTRH32_rq_u /* 1734 */, ARM_INS_VSTRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrh${vp}.16 $Qd, $addr */ + ARM_MVE_VSTRHU16 /* 1735 */, ARM_INS_VSTRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrh${vp}.16 $Qd, $Rn$addr */ + ARM_MVE_VSTRHU16_post /* 1736 */, ARM_INS_VSTRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrh${vp}.16 $Qd, $addr! */ + ARM_MVE_VSTRHU16_pre /* 1737 */, ARM_INS_VSTRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrw${vp}.32 $Qd, $addr */ + ARM_MVE_VSTRW32_qi /* 1738 */, ARM_INS_VSTRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrw${vp}.32 $Qd, $addr! */ + ARM_MVE_VSTRW32_qi_pre /* 1739 */, ARM_INS_VSTRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrw${vp}.32 $Qd, $addr */ + ARM_MVE_VSTRW32_rq /* 1740 */, ARM_INS_VSTRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrw${vp}.32 $Qd, $addr */ + ARM_MVE_VSTRW32_rq_u /* 1741 */, ARM_INS_VSTRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrw${vp}.32 $Qd, $addr */ + ARM_MVE_VSTRWU32 /* 1742 */, ARM_INS_VSTRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrw${vp}.32 $Qd, $Rn$addr */ + ARM_MVE_VSTRWU32_post /* 1743 */, ARM_INS_VSTRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstrw${vp}.32 $Qd, $addr! */ + ARM_MVE_VSTRWU32_pre /* 1744 */, ARM_INS_VSTRW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsub${vp}.f16 $Qd, $Qn, $Rm */ + ARM_MVE_VSUB_qr_f16 /* 1745 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vsub${vp}.f32 $Qd, $Qn, $Rm */ + ARM_MVE_VSUB_qr_f32 /* 1746 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vsub${vp}.i16 $Qd, $Qn, $Rm */ + ARM_MVE_VSUB_qr_i16 /* 1747 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsub${vp}.i32 $Qd, $Qn, $Rm */ + ARM_MVE_VSUB_qr_i32 /* 1748 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsub${vp}.i8 $Qd, $Qn, $Rm */ + ARM_MVE_VSUB_qr_i8 /* 1749 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsub${vp}.f16 $Qd, $Qn, $Qm */ + ARM_MVE_VSUBf16 /* 1750 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vsub${vp}.f32 $Qd, $Qn, $Qm */ + ARM_MVE_VSUBf32 /* 1751 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0 + #endif +}, +{ + /* vsub${vp}.i16 $Qd, $Qn, $Qm */ + ARM_MVE_VSUBi16 /* 1752 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsub${vp}.i32 $Qd, $Qn, $Qm */ + ARM_MVE_VSUBi32 /* 1753 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsub${vp}.i8 $Qd, $Qn, $Qm */ + ARM_MVE_VSUBi8 /* 1754 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* wlstp.16 $LR, $Rn, $label */ + ARM_MVE_WLSTP_16 /* 1755 */, ARM_INS_WLSTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_HasMVEInt, 0 }, 1, 0 + #endif +}, +{ + /* wlstp.32 $LR, $Rn, $label */ + ARM_MVE_WLSTP_32 /* 1756 */, ARM_INS_WLSTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_HasMVEInt, 0 }, 1, 0 + #endif +}, +{ + /* wlstp.64 $LR, $Rn, $label */ + ARM_MVE_WLSTP_64 /* 1757 */, ARM_INS_WLSTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_HasMVEInt, 0 }, 1, 0 + #endif +}, +{ + /* wlstp.8 $LR, $Rn, $label */ + ARM_MVE_WLSTP_8 /* 1758 */, ARM_INS_WLSTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_HasMVEInt, 0 }, 1, 0 + #endif +}, +{ + /* mvn${s}${p} $Rd, $imm */ + ARM_MVNi /* 1759 */, ARM_INS_MVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mvn${s}${p} $Rd, $Rm */ + ARM_MVNr /* 1760 */, ARM_INS_MVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mvn${s}${p} $Rd, $shift */ + ARM_MVNsi /* 1761 */, ARM_INS_MVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* mvn${s}${p} $Rd, $shift */ + ARM_MVNsr /* 1762 */, ARM_INS_MVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnm.f32 $Vd, $Vn, $Vm */ + ARM_NEON_VMAXNMNDf /* 1763 */, ARM_INS_VMAXNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnm.f16 $Vd, $Vn, $Vm */ + ARM_NEON_VMAXNMNDh /* 1764 */, ARM_INS_VMAXNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnm.f32 $Vd, $Vn, $Vm */ + ARM_NEON_VMAXNMNQf /* 1765 */, ARM_INS_VMAXNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnm.f16 $Vd, $Vn, $Vm */ + ARM_NEON_VMAXNMNQh /* 1766 */, ARM_INS_VMAXNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vminnm.f32 $Vd, $Vn, $Vm */ + ARM_NEON_VMINNMNDf /* 1767 */, ARM_INS_VMINNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vminnm.f16 $Vd, $Vn, $Vm */ + ARM_NEON_VMINNMNDh /* 1768 */, ARM_INS_VMINNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vminnm.f32 $Vd, $Vn, $Vm */ + ARM_NEON_VMINNMNQf /* 1769 */, ARM_INS_VMINNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vminnm.f16 $Vd, $Vn, $Vm */ + ARM_NEON_VMINNMNQh /* 1770 */, ARM_INS_VMINNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* orr${s}${p} $Rd, $Rn, $imm */ + ARM_ORRri /* 1771 */, ARM_INS_ORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* orr${s}${p} $Rd, $Rn, $Rm */ + ARM_ORRrr /* 1772 */, ARM_INS_ORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* orr${s}${p} $Rd, $Rn, $shift */ + ARM_ORRrsi /* 1773 */, ARM_INS_ORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* orr${s}${p} $Rd, $Rn, $shift */ + ARM_ORRrsr /* 1774 */, ARM_INS_ORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* pkhbt${p} $Rd, $Rn, $Rm$sh */ + ARM_PKHBT /* 1775 */, ARM_INS_PKHBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* pkhtb${p} $Rd, $Rn, $Rm$sh */ + ARM_PKHTB /* 1776 */, ARM_INS_PKHTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* pldw $addr */ + ARM_PLDWi12 /* 1777 */, ARM_INS_PLDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV7, ARM_FEATURE_HasMP, 0 }, 0, 0 + #endif +}, +{ + /* pldw $shift */ + ARM_PLDWrs /* 1778 */, ARM_INS_PLDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV7, ARM_FEATURE_HasMP, 0 }, 0, 0 + #endif +}, +{ + /* pld $addr */ + ARM_PLDi12 /* 1779 */, ARM_INS_PLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* pld $shift */ + ARM_PLDrs /* 1780 */, ARM_INS_PLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* pli $addr */ + ARM_PLIi12 /* 1781 */, ARM_INS_PLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV7, 0 }, 0, 0 + #endif +}, +{ + /* pli $shift */ + ARM_PLIrs /* 1782 */, ARM_INS_PLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV7, 0 }, 0, 0 + #endif +}, +{ + /* qadd${p} $Rd, $Rm, $Rn */ + ARM_QADD /* 1783 */, ARM_INS_QADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* qadd16${p} $Rd, $Rn, $Rm */ + ARM_QADD16 /* 1784 */, ARM_INS_QADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* qadd8${p} $Rd, $Rn, $Rm */ + ARM_QADD8 /* 1785 */, ARM_INS_QADD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* qasx${p} $Rd, $Rn, $Rm */ + ARM_QASX /* 1786 */, ARM_INS_QASX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* qdadd${p} $Rd, $Rm, $Rn */ + ARM_QDADD /* 1787 */, ARM_INS_QDADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* qdsub${p} $Rd, $Rm, $Rn */ + ARM_QDSUB /* 1788 */, ARM_INS_QDSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* qsax${p} $Rd, $Rn, $Rm */ + ARM_QSAX /* 1789 */, ARM_INS_QSAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* qsub${p} $Rd, $Rm, $Rn */ + ARM_QSUB /* 1790 */, ARM_INS_QSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* qsub16${p} $Rd, $Rn, $Rm */ + ARM_QSUB16 /* 1791 */, ARM_INS_QSUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* qsub8${p} $Rd, $Rn, $Rm */ + ARM_QSUB8 /* 1792 */, ARM_INS_QSUB8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rbit${p} $Rd, $Rm */ + ARM_RBIT /* 1793 */, ARM_INS_RBIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0 + #endif +}, +{ + /* rev${p} $Rd, $Rm */ + ARM_REV /* 1794 */, ARM_INS_REV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* rev16${p} $Rd, $Rm */ + ARM_REV16 /* 1795 */, ARM_INS_REV16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* revsh${p} $Rd, $Rm */ + ARM_REVSH /* 1796 */, ARM_INS_REVSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* rfeda $Rn */ + ARM_RFEDA /* 1797 */, ARM_INS_RFEDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rfeda $Rn! */ + ARM_RFEDA_UPD /* 1798 */, ARM_INS_RFEDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rfedb $Rn */ + ARM_RFEDB /* 1799 */, ARM_INS_RFEDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rfedb $Rn! */ + ARM_RFEDB_UPD /* 1800 */, ARM_INS_RFEDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rfeia $Rn */ + ARM_RFEIA /* 1801 */, ARM_INS_RFEIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rfeia $Rn! */ + ARM_RFEIA_UPD /* 1802 */, ARM_INS_RFEIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rfeib $Rn */ + ARM_RFEIB /* 1803 */, ARM_INS_RFEIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rfeib $Rn! */ + ARM_RFEIB_UPD /* 1804 */, ARM_INS_RFEIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rsb${s}${p} $Rd, $Rn, $imm */ + ARM_RSBri /* 1805 */, ARM_INS_RSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rsb${s}${p} $Rd, $Rn, $Rm */ + ARM_RSBrr /* 1806 */, ARM_INS_RSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rsb${s}${p} $Rd, $Rn, $shift */ + ARM_RSBrsi /* 1807 */, ARM_INS_RSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rsb${s}${p} $Rd, $Rn, $shift */ + ARM_RSBrsr /* 1808 */, ARM_INS_RSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rsc${s}${p} $Rd, $Rn, $imm */ + ARM_RSCri /* 1809 */, ARM_INS_RSC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rsc${s}${p} $Rd, $Rn, $Rm */ + ARM_RSCrr /* 1810 */, ARM_INS_RSC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rsc${s}${p} $Rd, $Rn, $shift */ + ARM_RSCrsi /* 1811 */, ARM_INS_RSC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* rsc${s}${p} $Rd, $Rn, $shift */ + ARM_RSCrsr /* 1812 */, ARM_INS_RSC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* sadd16${p} $Rd, $Rn, $Rm */ + ARM_SADD16 /* 1813 */, ARM_INS_SADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* sadd8${p} $Rd, $Rn, $Rm */ + ARM_SADD8 /* 1814 */, ARM_INS_SADD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* sasx${p} $Rd, $Rn, $Rm */ + ARM_SASX /* 1815 */, ARM_INS_SASX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* sb */ + ARM_SB /* 1816 */, ARM_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasSB, 0 }, 0, 0 + #endif +}, +{ + /* sbc${s}${p} $Rd, $Rn, $imm */ + ARM_SBCri /* 1817 */, ARM_INS_SBC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* sbc${s}${p} $Rd, $Rn, $Rm */ + ARM_SBCrr /* 1818 */, ARM_INS_SBC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* sbc${s}${p} $Rd, $Rn, $shift */ + ARM_SBCrsi /* 1819 */, ARM_INS_SBC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* sbc${s}${p} $Rd, $Rn, $shift */ + ARM_SBCrsr /* 1820 */, ARM_INS_SBC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* sbfx${p} $Rd, $Rn, $lsb, $width */ + ARM_SBFX /* 1821 */, ARM_INS_SBFX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0 + #endif +}, +{ + /* sdiv${p} $Rd, $Rn, $Rm */ + ARM_SDIV /* 1822 */, ARM_INS_SDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasDivideInARM, 0 }, 0, 0 + #endif +}, +{ + /* sel${p} $Rd, $Rn, $Rm */ + ARM_SEL /* 1823 */, ARM_INS_SEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* setend $end */ + ARM_SETEND /* 1824 */, ARM_INS_SETEND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* setpan $imm */ + ARM_SETPAN /* 1825 */, ARM_INS_SETPAN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* sha1c.32 $Vd, $Vn, $Vm */ + ARM_SHA1C /* 1826 */, ARM_INS_SHA1C, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0 + #endif +}, +{ + /* sha1h.32 $Vd, $Vm */ + ARM_SHA1H /* 1827 */, ARM_INS_SHA1H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0 + #endif +}, +{ + /* sha1m.32 $Vd, $Vn, $Vm */ + ARM_SHA1M /* 1828 */, ARM_INS_SHA1M, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0 + #endif +}, +{ + /* sha1p.32 $Vd, $Vn, $Vm */ + ARM_SHA1P /* 1829 */, ARM_INS_SHA1P, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0 + #endif +}, +{ + /* sha1su0.32 $Vd, $Vn, $Vm */ + ARM_SHA1SU0 /* 1830 */, ARM_INS_SHA1SU0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0 + #endif +}, +{ + /* sha1su1.32 $Vd, $Vm */ + ARM_SHA1SU1 /* 1831 */, ARM_INS_SHA1SU1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0 + #endif +}, +{ + /* sha256h.32 $Vd, $Vn, $Vm */ + ARM_SHA256H /* 1832 */, ARM_INS_SHA256H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0 + #endif +}, +{ + /* sha256h2.32 $Vd, $Vn, $Vm */ + ARM_SHA256H2 /* 1833 */, ARM_INS_SHA256H2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0 + #endif +}, +{ + /* sha256su0.32 $Vd, $Vm */ + ARM_SHA256SU0 /* 1834 */, ARM_INS_SHA256SU0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0 + #endif +}, +{ + /* sha256su1.32 $Vd, $Vn, $Vm */ + ARM_SHA256SU1 /* 1835 */, ARM_INS_SHA256SU1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0 + #endif +}, +{ + /* shadd16${p} $Rd, $Rn, $Rm */ + ARM_SHADD16 /* 1836 */, ARM_INS_SHADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* shadd8${p} $Rd, $Rn, $Rm */ + ARM_SHADD8 /* 1837 */, ARM_INS_SHADD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* shasx${p} $Rd, $Rn, $Rm */ + ARM_SHASX /* 1838 */, ARM_INS_SHASX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* shsax${p} $Rd, $Rn, $Rm */ + ARM_SHSAX /* 1839 */, ARM_INS_SHSAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* shsub16${p} $Rd, $Rn, $Rm */ + ARM_SHSUB16 /* 1840 */, ARM_INS_SHSUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* shsub8${p} $Rd, $Rn, $Rm */ + ARM_SHSUB8 /* 1841 */, ARM_INS_SHSUB8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* smc${p} $opt */ + ARM_SMC /* 1842 */, ARM_INS_SMC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasTrustZone, 0 }, 0, 0 + #endif +}, +{ + /* smlabb${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMLABB /* 1843 */, ARM_INS_SMLABB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smlabt${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMLABT /* 1844 */, ARM_INS_SMLABT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smlad${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMLAD /* 1845 */, ARM_INS_SMLAD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smladx${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMLADX /* 1846 */, ARM_INS_SMLADX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_SMLAL /* 1847 */, ARM_INS_SMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smlalbb${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_SMLALBB /* 1848 */, ARM_INS_SMLALBB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smlalbt${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_SMLALBT /* 1849 */, ARM_INS_SMLALBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smlald${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_SMLALD /* 1850 */, ARM_INS_SMLALD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smlaldx${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_SMLALDX /* 1851 */, ARM_INS_SMLALDX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smlaltb${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_SMLALTB /* 1852 */, ARM_INS_SMLALTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smlaltt${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_SMLALTT /* 1853 */, ARM_INS_SMLALTT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smlatb${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMLATB /* 1854 */, ARM_INS_SMLATB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smlatt${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMLATT /* 1855 */, ARM_INS_SMLATT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smlawb${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMLAWB /* 1856 */, ARM_INS_SMLAWB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smlawt${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMLAWT /* 1857 */, ARM_INS_SMLAWT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smlsd${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMLSD /* 1858 */, ARM_INS_SMLSD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smlsdx${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMLSDX /* 1859 */, ARM_INS_SMLSDX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smlsld${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_SMLSLD /* 1860 */, ARM_INS_SMLSLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smlsldx${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_SMLSLDX /* 1861 */, ARM_INS_SMLSLDX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smmla${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMMLA /* 1862 */, ARM_INS_SMMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smmlar${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMMLAR /* 1863 */, ARM_INS_SMMLAR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smmls${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMMLS /* 1864 */, ARM_INS_SMMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smmlsr${p} $Rd, $Rn, $Rm, $Ra */ + ARM_SMMLSR /* 1865 */, ARM_INS_SMMLSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smmul${p} $Rd, $Rn, $Rm */ + ARM_SMMUL /* 1866 */, ARM_INS_SMMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smmulr${p} $Rd, $Rn, $Rm */ + ARM_SMMULR /* 1867 */, ARM_INS_SMMULR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smuad${p} $Rd, $Rn, $Rm */ + ARM_SMUAD /* 1868 */, ARM_INS_SMUAD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smuadx${p} $Rd, $Rn, $Rm */ + ARM_SMUADX /* 1869 */, ARM_INS_SMUADX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smulbb${p} $Rd, $Rn, $Rm */ + ARM_SMULBB /* 1870 */, ARM_INS_SMULBB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smulbt${p} $Rd, $Rn, $Rm */ + ARM_SMULBT /* 1871 */, ARM_INS_SMULBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smull${s}${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_SMULL /* 1872 */, ARM_INS_SMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smultb${p} $Rd, $Rn, $Rm */ + ARM_SMULTB /* 1873 */, ARM_INS_SMULTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smultt${p} $Rd, $Rn, $Rm */ + ARM_SMULTT /* 1874 */, ARM_INS_SMULTT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smulwb${p} $Rd, $Rn, $Rm */ + ARM_SMULWB /* 1875 */, ARM_INS_SMULWB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smulwt${p} $Rd, $Rn, $Rm */ + ARM_SMULWT /* 1876 */, ARM_INS_SMULWT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* smusd${p} $Rd, $Rn, $Rm */ + ARM_SMUSD /* 1877 */, ARM_INS_SMUSD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* smusdx${p} $Rd, $Rn, $Rm */ + ARM_SMUSDX /* 1878 */, ARM_INS_SMUSDX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* srsda sp, $mode */ + ARM_SRSDA /* 1879 */, ARM_INS_SRSDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* srsda sp!, $mode */ + ARM_SRSDA_UPD /* 1880 */, ARM_INS_SRSDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* srsdb sp, $mode */ + ARM_SRSDB /* 1881 */, ARM_INS_SRSDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* srsdb sp!, $mode */ + ARM_SRSDB_UPD /* 1882 */, ARM_INS_SRSDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* srsia sp, $mode */ + ARM_SRSIA /* 1883 */, ARM_INS_SRSIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* srsia sp!, $mode */ + ARM_SRSIA_UPD /* 1884 */, ARM_INS_SRSIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* srsib sp, $mode */ + ARM_SRSIB /* 1885 */, ARM_INS_SRSIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* srsib sp!, $mode */ + ARM_SRSIB_UPD /* 1886 */, ARM_INS_SRSIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ssat${p} $Rd, $sat_imm, $Rn$sh */ + ARM_SSAT /* 1887 */, ARM_INS_SSAT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* ssat16${p} $Rd, $sat_imm, $Rn */ + ARM_SSAT16 /* 1888 */, ARM_INS_SSAT16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* ssax${p} $Rd, $Rn, $Rm */ + ARM_SSAX /* 1889 */, ARM_INS_SSAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ssub16${p} $Rd, $Rn, $Rm */ + ARM_SSUB16 /* 1890 */, ARM_INS_SSUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ssub8${p} $Rd, $Rn, $Rm */ + ARM_SSUB8 /* 1891 */, ARM_INS_SSUB8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stc2l $cop, $CRd, $addr */ + ARM_STC2L_OFFSET /* 1892 */, ARM_INS_STC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* stc2l $cop, $CRd, $addr, $option */ + ARM_STC2L_OPTION /* 1893 */, ARM_INS_STC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* stc2l $cop, $CRd, $addr, $offset */ + ARM_STC2L_POST /* 1894 */, ARM_INS_STC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* stc2l $cop, $CRd, $addr! */ + ARM_STC2L_PRE /* 1895 */, ARM_INS_STC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* stc2 $cop, $CRd, $addr */ + ARM_STC2_OFFSET /* 1896 */, ARM_INS_STC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* stc2 $cop, $CRd, $addr, $option */ + ARM_STC2_OPTION /* 1897 */, ARM_INS_STC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* stc2 $cop, $CRd, $addr, $offset */ + ARM_STC2_POST /* 1898 */, ARM_INS_STC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* stc2 $cop, $CRd, $addr! */ + ARM_STC2_PRE /* 1899 */, ARM_INS_STC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* stcl${p} $cop, $CRd, $addr */ + ARM_STCL_OFFSET /* 1900 */, ARM_INS_STCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stcl${p} $cop, $CRd, $addr, $option */ + ARM_STCL_OPTION /* 1901 */, ARM_INS_STCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stcl${p} $cop, $CRd, $addr, $offset */ + ARM_STCL_POST /* 1902 */, ARM_INS_STCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stcl${p} $cop, $CRd, $addr! */ + ARM_STCL_PRE /* 1903 */, ARM_INS_STCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stc${p} $cop, $CRd, $addr */ + ARM_STC_OFFSET /* 1904 */, ARM_INS_STC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stc${p} $cop, $CRd, $addr, $option */ + ARM_STC_OPTION /* 1905 */, ARM_INS_STC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stc${p} $cop, $CRd, $addr, $offset */ + ARM_STC_POST /* 1906 */, ARM_INS_STC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stc${p} $cop, $CRd, $addr! */ + ARM_STC_PRE /* 1907 */, ARM_INS_STC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stl${p} $Rt, $addr */ + ARM_STL /* 1908 */, ARM_INS_STL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0 + #endif +}, +{ + /* stlb${p} $Rt, $addr */ + ARM_STLB /* 1909 */, ARM_INS_STLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0 + #endif +}, +{ + /* stlex${p} $Rd, $Rt, $addr */ + ARM_STLEX /* 1910 */, ARM_INS_STLEX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* stlexb${p} $Rd, $Rt, $addr */ + ARM_STLEXB /* 1911 */, ARM_INS_STLEXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* stlexd${p} $Rd, $Rt, $addr */ + ARM_STLEXD /* 1912 */, ARM_INS_STLEXD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* stlexh${p} $Rd, $Rt, $addr */ + ARM_STLEXH /* 1913 */, ARM_INS_STLEXH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* stlh${p} $Rt, $addr */ + ARM_STLH /* 1914 */, ARM_INS_STLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0 + #endif +}, +{ + /* stmda${p} $Rn, $regs */ + ARM_STMDA /* 1915 */, ARM_INS_STMDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stmda${p} $Rn!, $regs */ + ARM_STMDA_UPD /* 1916 */, ARM_INS_STMDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stmdb${p} $Rn, $regs */ + ARM_STMDB /* 1917 */, ARM_INS_STMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stmdb${p} $Rn!, $regs */ + ARM_STMDB_UPD /* 1918 */, ARM_INS_STMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stm${p} $Rn, $regs */ + ARM_STMIA /* 1919 */, ARM_INS_STM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stm${p} $Rn!, $regs */ + ARM_STMIA_UPD /* 1920 */, ARM_INS_STM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stmib${p} $Rn, $regs */ + ARM_STMIB /* 1921 */, ARM_INS_STMIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stmib${p} $Rn!, $regs */ + ARM_STMIB_UPD /* 1922 */, ARM_INS_STMIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strbt${p} $Rt, $addr, $offset */ + ARM_STRBT_POST_IMM /* 1923 */, ARM_INS_STRBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strbt${p} $Rt, $addr, $offset */ + ARM_STRBT_POST_REG /* 1924 */, ARM_INS_STRBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strb${p} $Rt, $addr, $offset */ + ARM_STRB_POST_IMM /* 1925 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strb${p} $Rt, $addr, $offset */ + ARM_STRB_POST_REG /* 1926 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strb${p} $Rt, $addr! */ + ARM_STRB_PRE_IMM /* 1927 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strb${p} $Rt, $addr! */ + ARM_STRB_PRE_REG /* 1928 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strb${p} $Rt, $addr */ + ARM_STRBi12 /* 1929 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strb${p} $Rt, $shift */ + ARM_STRBrs /* 1930 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strd${p} $Rt, $Rt2, $addr */ + ARM_STRD /* 1931 */, ARM_INS_STRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0 + #endif +}, +{ + /* strd${p} $Rt, $Rt2, $addr, $offset */ + ARM_STRD_POST /* 1932 */, ARM_INS_STRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strd${p} $Rt, $Rt2, $addr! */ + ARM_STRD_PRE /* 1933 */, ARM_INS_STRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strex${p} $Rd, $Rt, $addr */ + ARM_STREX /* 1934 */, ARM_INS_STREX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strexb${p} $Rd, $Rt, $addr */ + ARM_STREXB /* 1935 */, ARM_INS_STREXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strexd${p} $Rd, $Rt, $addr */ + ARM_STREXD /* 1936 */, ARM_INS_STREXD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strexh${p} $Rd, $Rt, $addr */ + ARM_STREXH /* 1937 */, ARM_INS_STREXH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strh${p} $Rt, $addr */ + ARM_STRH /* 1938 */, ARM_INS_STRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strht${p} $Rt, $addr, $offset */ + ARM_STRHTi /* 1939 */, ARM_INS_STRHT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strht${p} $Rt, $addr, $Rm */ + ARM_STRHTr /* 1940 */, ARM_INS_STRHT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strh${p} $Rt, $addr, $offset */ + ARM_STRH_POST /* 1941 */, ARM_INS_STRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strh${p} $Rt, $addr! */ + ARM_STRH_PRE /* 1942 */, ARM_INS_STRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strt${p} $Rt, $addr, $offset */ + ARM_STRT_POST_IMM /* 1943 */, ARM_INS_STRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* strt${p} $Rt, $addr, $offset */ + ARM_STRT_POST_REG /* 1944 */, ARM_INS_STRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* str${p} $Rt, $addr, $offset */ + ARM_STR_POST_IMM /* 1945 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* str${p} $Rt, $addr, $offset */ + ARM_STR_POST_REG /* 1946 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* str${p} $Rt, $addr! */ + ARM_STR_PRE_IMM /* 1947 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* str${p} $Rt, $addr! */ + ARM_STR_PRE_REG /* 1948 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* str${p} $Rt, $addr */ + ARM_STRi12 /* 1949 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* str${p} $Rt, $shift */ + ARM_STRrs /* 1950 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* sub${s}${p} $Rd, $Rn, $imm */ + ARM_SUBri /* 1951 */, ARM_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* sub${s}${p} $Rd, $Rn, $Rm */ + ARM_SUBrr /* 1952 */, ARM_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* sub${s}${p} $Rd, $Rn, $shift */ + ARM_SUBrsi /* 1953 */, ARM_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* sub${s}${p} $Rd, $Rn, $shift */ + ARM_SUBrsr /* 1954 */, ARM_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* svc${p} $svc */ + ARM_SVC /* 1955 */, ARM_INS_SVC, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* swp${p} $Rt, $Rt2, $addr */ + ARM_SWP /* 1956 */, ARM_INS_SWP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* swpb${p} $Rt, $Rt2, $addr */ + ARM_SWPB /* 1957 */, ARM_INS_SWPB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* sxtab${p} $Rd, $Rn, $Rm$rot */ + ARM_SXTAB /* 1958 */, ARM_INS_SXTAB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* sxtab16${p} $Rd, $Rn, $Rm$rot */ + ARM_SXTAB16 /* 1959 */, ARM_INS_SXTAB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* sxtah${p} $Rd, $Rn, $Rm$rot */ + ARM_SXTAH /* 1960 */, ARM_INS_SXTAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* sxtb${p} $Rd, $Rm$rot */ + ARM_SXTB /* 1961 */, ARM_INS_SXTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* sxtb16${p} $Rd, $Rm$rot */ + ARM_SXTB16 /* 1962 */, ARM_INS_SXTB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* sxth${p} $Rd, $Rm$rot */ + ARM_SXTH /* 1963 */, ARM_INS_SXTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* teq${p} $Rn, $imm */ + ARM_TEQri /* 1964 */, ARM_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* teq${p} $Rn, $Rm */ + ARM_TEQrr /* 1965 */, ARM_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* teq${p} $Rn, $shift */ + ARM_TEQrsi /* 1966 */, ARM_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* teq${p} $Rn, $shift */ + ARM_TEQrsr /* 1967 */, ARM_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* trap */ + ARM_TRAP /* 1968 */, ARM_INS_TRAP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* trap */ + ARM_TRAPNaCl /* 1969 */, ARM_INS_TRAP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_UseNaClTrap, 0 }, 0, 0 + #endif +}, +{ + /* tsb $opt */ + ARM_TSB /* 1970 */, ARM_INS_TSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8_4a, 0 }, 0, 0 + #endif +}, +{ + /* tst${p} $Rn, $imm */ + ARM_TSTri /* 1971 */, ARM_INS_TST, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* tst${p} $Rn, $Rm */ + ARM_TSTrr /* 1972 */, ARM_INS_TST, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* tst${p} $Rn, $shift */ + ARM_TSTrsi /* 1973 */, ARM_INS_TST, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* tst${p} $Rn, $shift */ + ARM_TSTrsr /* 1974 */, ARM_INS_TST, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uadd16${p} $Rd, $Rn, $Rm */ + ARM_UADD16 /* 1975 */, ARM_INS_UADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uadd8${p} $Rd, $Rn, $Rm */ + ARM_UADD8 /* 1976 */, ARM_INS_UADD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uasx${p} $Rd, $Rn, $Rm */ + ARM_UASX /* 1977 */, ARM_INS_UASX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ubfx${p} $Rd, $Rn, $lsb, $width */ + ARM_UBFX /* 1978 */, ARM_INS_UBFX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0 + #endif +}, +{ + /* udf $imm16 */ + ARM_UDF /* 1979 */, ARM_INS_UDF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* udiv${p} $Rd, $Rn, $Rm */ + ARM_UDIV /* 1980 */, ARM_INS_UDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasDivideInARM, 0 }, 0, 0 + #endif +}, +{ + /* uhadd16${p} $Rd, $Rn, $Rm */ + ARM_UHADD16 /* 1981 */, ARM_INS_UHADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uhadd8${p} $Rd, $Rn, $Rm */ + ARM_UHADD8 /* 1982 */, ARM_INS_UHADD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uhasx${p} $Rd, $Rn, $Rm */ + ARM_UHASX /* 1983 */, ARM_INS_UHASX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uhsax${p} $Rd, $Rn, $Rm */ + ARM_UHSAX /* 1984 */, ARM_INS_UHSAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uhsub16${p} $Rd, $Rn, $Rm */ + ARM_UHSUB16 /* 1985 */, ARM_INS_UHSUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uhsub8${p} $Rd, $Rn, $Rm */ + ARM_UHSUB8 /* 1986 */, ARM_INS_UHSUB8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* umaal${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_UMAAL /* 1987 */, ARM_INS_UMAAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_UMLAL /* 1988 */, ARM_INS_UMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* umull${s}${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_UMULL /* 1989 */, ARM_INS_UMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* uqadd16${p} $Rd, $Rn, $Rm */ + ARM_UQADD16 /* 1990 */, ARM_INS_UQADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uqadd8${p} $Rd, $Rn, $Rm */ + ARM_UQADD8 /* 1991 */, ARM_INS_UQADD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uqasx${p} $Rd, $Rn, $Rm */ + ARM_UQASX /* 1992 */, ARM_INS_UQASX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uqsax${p} $Rd, $Rn, $Rm */ + ARM_UQSAX /* 1993 */, ARM_INS_UQSAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uqsub16${p} $Rd, $Rn, $Rm */ + ARM_UQSUB16 /* 1994 */, ARM_INS_UQSUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uqsub8${p} $Rd, $Rn, $Rm */ + ARM_UQSUB8 /* 1995 */, ARM_INS_UQSUB8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* usad8${p} $Rd, $Rn, $Rm */ + ARM_USAD8 /* 1996 */, ARM_INS_USAD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* usada8${p} $Rd, $Rn, $Rm, $Ra */ + ARM_USADA8 /* 1997 */, ARM_INS_USADA8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* usat${p} $Rd, $sat_imm, $Rn$sh */ + ARM_USAT /* 1998 */, ARM_INS_USAT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* usat16${p} $Rd, $sat_imm, $Rn */ + ARM_USAT16 /* 1999 */, ARM_INS_USAT16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* usax${p} $Rd, $Rn, $Rm */ + ARM_USAX /* 2000 */, ARM_INS_USAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* usub16${p} $Rd, $Rn, $Rm */ + ARM_USUB16 /* 2001 */, ARM_INS_USUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* usub8${p} $Rd, $Rn, $Rm */ + ARM_USUB8 /* 2002 */, ARM_INS_USUB8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* uxtab${p} $Rd, $Rn, $Rm$rot */ + ARM_UXTAB /* 2003 */, ARM_INS_UXTAB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* uxtab16${p} $Rd, $Rn, $Rm$rot */ + ARM_UXTAB16 /* 2004 */, ARM_INS_UXTAB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* uxtah${p} $Rd, $Rn, $Rm$rot */ + ARM_UXTAH /* 2005 */, ARM_INS_UXTAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* uxtb${p} $Rd, $Rm$rot */ + ARM_UXTB /* 2006 */, ARM_INS_UXTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* uxtb16${p} $Rd, $Rm$rot */ + ARM_UXTB16 /* 2007 */, ARM_INS_UXTB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* uxth${p} $Rd, $Rm$rot */ + ARM_UXTH /* 2008 */, ARM_INS_UXTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* vabal${p}.s32 $Vd, $Vn, $Vm */ + ARM_VABALsv2i64 /* 2009 */, ARM_INS_VABAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabal${p}.s16 $Vd, $Vn, $Vm */ + ARM_VABALsv4i32 /* 2010 */, ARM_INS_VABAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabal${p}.s8 $Vd, $Vn, $Vm */ + ARM_VABALsv8i16 /* 2011 */, ARM_INS_VABAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabal${p}.u32 $Vd, $Vn, $Vm */ + ARM_VABALuv2i64 /* 2012 */, ARM_INS_VABAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabal${p}.u16 $Vd, $Vn, $Vm */ + ARM_VABALuv4i32 /* 2013 */, ARM_INS_VABAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabal${p}.u8 $Vd, $Vn, $Vm */ + ARM_VABALuv8i16 /* 2014 */, ARM_INS_VABAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaba${p}.s8 $Vd, $Vn, $Vm */ + ARM_VABAsv16i8 /* 2015 */, ARM_INS_VABA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaba${p}.s32 $Vd, $Vn, $Vm */ + ARM_VABAsv2i32 /* 2016 */, ARM_INS_VABA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaba${p}.s16 $Vd, $Vn, $Vm */ + ARM_VABAsv4i16 /* 2017 */, ARM_INS_VABA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaba${p}.s32 $Vd, $Vn, $Vm */ + ARM_VABAsv4i32 /* 2018 */, ARM_INS_VABA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaba${p}.s16 $Vd, $Vn, $Vm */ + ARM_VABAsv8i16 /* 2019 */, ARM_INS_VABA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaba${p}.s8 $Vd, $Vn, $Vm */ + ARM_VABAsv8i8 /* 2020 */, ARM_INS_VABA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaba${p}.u8 $Vd, $Vn, $Vm */ + ARM_VABAuv16i8 /* 2021 */, ARM_INS_VABA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaba${p}.u32 $Vd, $Vn, $Vm */ + ARM_VABAuv2i32 /* 2022 */, ARM_INS_VABA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaba${p}.u16 $Vd, $Vn, $Vm */ + ARM_VABAuv4i16 /* 2023 */, ARM_INS_VABA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaba${p}.u32 $Vd, $Vn, $Vm */ + ARM_VABAuv4i32 /* 2024 */, ARM_INS_VABA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaba${p}.u16 $Vd, $Vn, $Vm */ + ARM_VABAuv8i16 /* 2025 */, ARM_INS_VABA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaba${p}.u8 $Vd, $Vn, $Vm */ + ARM_VABAuv8i8 /* 2026 */, ARM_INS_VABA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabdl${p}.s32 $Vd, $Vn, $Vm */ + ARM_VABDLsv2i64 /* 2027 */, ARM_INS_VABDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabdl${p}.s16 $Vd, $Vn, $Vm */ + ARM_VABDLsv4i32 /* 2028 */, ARM_INS_VABDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabdl${p}.s8 $Vd, $Vn, $Vm */ + ARM_VABDLsv8i16 /* 2029 */, ARM_INS_VABDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabdl${p}.u32 $Vd, $Vn, $Vm */ + ARM_VABDLuv2i64 /* 2030 */, ARM_INS_VABDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabdl${p}.u16 $Vd, $Vn, $Vm */ + ARM_VABDLuv4i32 /* 2031 */, ARM_INS_VABDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabdl${p}.u8 $Vd, $Vn, $Vm */ + ARM_VABDLuv8i16 /* 2032 */, ARM_INS_VABDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.f32 $Vd, $Vn, $Vm */ + ARM_VABDfd /* 2033 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.f32 $Vd, $Vn, $Vm */ + ARM_VABDfq /* 2034 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.f16 $Vd, $Vn, $Vm */ + ARM_VABDhd /* 2035 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.f16 $Vd, $Vn, $Vm */ + ARM_VABDhq /* 2036 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.s8 $Vd, $Vn, $Vm */ + ARM_VABDsv16i8 /* 2037 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.s32 $Vd, $Vn, $Vm */ + ARM_VABDsv2i32 /* 2038 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.s16 $Vd, $Vn, $Vm */ + ARM_VABDsv4i16 /* 2039 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.s32 $Vd, $Vn, $Vm */ + ARM_VABDsv4i32 /* 2040 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.s16 $Vd, $Vn, $Vm */ + ARM_VABDsv8i16 /* 2041 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.s8 $Vd, $Vn, $Vm */ + ARM_VABDsv8i8 /* 2042 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.u8 $Vd, $Vn, $Vm */ + ARM_VABDuv16i8 /* 2043 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.u32 $Vd, $Vn, $Vm */ + ARM_VABDuv2i32 /* 2044 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.u16 $Vd, $Vn, $Vm */ + ARM_VABDuv4i16 /* 2045 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.u32 $Vd, $Vn, $Vm */ + ARM_VABDuv4i32 /* 2046 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.u16 $Vd, $Vn, $Vm */ + ARM_VABDuv8i16 /* 2047 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabd${p}.u8 $Vd, $Vn, $Vm */ + ARM_VABDuv8i8 /* 2048 */, ARM_INS_VABD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.f64 $Dd, $Dm */ + ARM_VABSD /* 2049 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.f16 $Sd, $Sm */ + ARM_VABSH /* 2050 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.f32 $Sd, $Sm */ + ARM_VABSS /* 2051 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.f32 $Vd, $Vm */ + ARM_VABSfd /* 2052 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.f32 $Vd, $Vm */ + ARM_VABSfq /* 2053 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.f16 $Vd, $Vm */ + ARM_VABShd /* 2054 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.f16 $Vd, $Vm */ + ARM_VABShq /* 2055 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.s8 $Vd, $Vm */ + ARM_VABSv16i8 /* 2056 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.s32 $Vd, $Vm */ + ARM_VABSv2i32 /* 2057 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.s16 $Vd, $Vm */ + ARM_VABSv4i16 /* 2058 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.s32 $Vd, $Vm */ + ARM_VABSv4i32 /* 2059 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.s16 $Vd, $Vm */ + ARM_VABSv8i16 /* 2060 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vabs${p}.s8 $Vd, $Vm */ + ARM_VABSv8i8 /* 2061 */, ARM_INS_VABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vacge${p}.f32 $Vd, $Vn, $Vm */ + ARM_VACGEfd /* 2062 */, ARM_INS_VACGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vacge${p}.f32 $Vd, $Vn, $Vm */ + ARM_VACGEfq /* 2063 */, ARM_INS_VACGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vacge${p}.f16 $Vd, $Vn, $Vm */ + ARM_VACGEhd /* 2064 */, ARM_INS_VACGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vacge${p}.f16 $Vd, $Vn, $Vm */ + ARM_VACGEhq /* 2065 */, ARM_INS_VACGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vacgt${p}.f32 $Vd, $Vn, $Vm */ + ARM_VACGTfd /* 2066 */, ARM_INS_VACGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vacgt${p}.f32 $Vd, $Vn, $Vm */ + ARM_VACGTfq /* 2067 */, ARM_INS_VACGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vacgt${p}.f16 $Vd, $Vn, $Vm */ + ARM_VACGThd /* 2068 */, ARM_INS_VACGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vacgt${p}.f16 $Vd, $Vn, $Vm */ + ARM_VACGThq /* 2069 */, ARM_INS_VACGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.f64 $Dd, $Dn, $Dm */ + ARM_VADDD /* 2070 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.f16 $Sd, $Sn, $Sm */ + ARM_VADDH /* 2071 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vaddhn${p}.i64 $Vd, $Vn, $Vm */ + ARM_VADDHNv2i32 /* 2072 */, ARM_INS_VADDHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddhn${p}.i32 $Vd, $Vn, $Vm */ + ARM_VADDHNv4i16 /* 2073 */, ARM_INS_VADDHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddhn${p}.i16 $Vd, $Vn, $Vm */ + ARM_VADDHNv8i8 /* 2074 */, ARM_INS_VADDHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddl${p}.s32 $Vd, $Vn, $Vm */ + ARM_VADDLsv2i64 /* 2075 */, ARM_INS_VADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddl${p}.s16 $Vd, $Vn, $Vm */ + ARM_VADDLsv4i32 /* 2076 */, ARM_INS_VADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddl${p}.s8 $Vd, $Vn, $Vm */ + ARM_VADDLsv8i16 /* 2077 */, ARM_INS_VADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddl${p}.u32 $Vd, $Vn, $Vm */ + ARM_VADDLuv2i64 /* 2078 */, ARM_INS_VADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddl${p}.u16 $Vd, $Vn, $Vm */ + ARM_VADDLuv4i32 /* 2079 */, ARM_INS_VADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddl${p}.u8 $Vd, $Vn, $Vm */ + ARM_VADDLuv8i16 /* 2080 */, ARM_INS_VADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.f32 $Sd, $Sn, $Sm */ + ARM_VADDS /* 2081 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vaddw${p}.s32 $Vd, $Vn, $Vm */ + ARM_VADDWsv2i64 /* 2082 */, ARM_INS_VADDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddw${p}.s16 $Vd, $Vn, $Vm */ + ARM_VADDWsv4i32 /* 2083 */, ARM_INS_VADDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddw${p}.s8 $Vd, $Vn, $Vm */ + ARM_VADDWsv8i16 /* 2084 */, ARM_INS_VADDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddw${p}.u32 $Vd, $Vn, $Vm */ + ARM_VADDWuv2i64 /* 2085 */, ARM_INS_VADDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddw${p}.u16 $Vd, $Vn, $Vm */ + ARM_VADDWuv4i32 /* 2086 */, ARM_INS_VADDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vaddw${p}.u8 $Vd, $Vn, $Vm */ + ARM_VADDWuv8i16 /* 2087 */, ARM_INS_VADDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.f32 $Vd, $Vn, $Vm */ + ARM_VADDfd /* 2088 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.f32 $Vd, $Vn, $Vm */ + ARM_VADDfq /* 2089 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.f16 $Vd, $Vn, $Vm */ + ARM_VADDhd /* 2090 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.f16 $Vd, $Vn, $Vm */ + ARM_VADDhq /* 2091 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.i8 $Vd, $Vn, $Vm */ + ARM_VADDv16i8 /* 2092 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.i64 $Vd, $Vn, $Vm */ + ARM_VADDv1i64 /* 2093 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.i32 $Vd, $Vn, $Vm */ + ARM_VADDv2i32 /* 2094 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.i64 $Vd, $Vn, $Vm */ + ARM_VADDv2i64 /* 2095 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.i16 $Vd, $Vn, $Vm */ + ARM_VADDv4i16 /* 2096 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.i32 $Vd, $Vn, $Vm */ + ARM_VADDv4i32 /* 2097 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.i16 $Vd, $Vn, $Vm */ + ARM_VADDv8i16 /* 2098 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vadd${p}.i8 $Vd, $Vn, $Vm */ + ARM_VADDv8i8 /* 2099 */, ARM_INS_VADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vand${p} $Vd, $Vn, $Vm */ + ARM_VANDd /* 2100 */, ARM_INS_VAND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vand${p} $Vd, $Vn, $Vm */ + ARM_VANDq /* 2101 */, ARM_INS_VAND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vfmab.bf16 $Vd, $Vn, $Vm */ + ARM_VBF16MALBQ /* 2102 */, ARM_INS_VFMAB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vfmab.bf16 $Vd, $Vn, $Vm$idx */ + ARM_VBF16MALBQI /* 2103 */, ARM_INS_VFMAB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vfmat.bf16 $Vd, $Vn, $Vm */ + ARM_VBF16MALTQ /* 2104 */, ARM_INS_VFMAT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vfmat.bf16 $Vd, $Vn, $Vm$idx */ + ARM_VBF16MALTQI /* 2105 */, ARM_INS_VFMAT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vbic${p} $Vd, $Vn, $Vm */ + ARM_VBICd /* 2106 */, ARM_INS_VBIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vbic${p}.i32 $Vd, $SIMM */ + ARM_VBICiv2i32 /* 2107 */, ARM_INS_VBIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vbic${p}.i16 $Vd, $SIMM */ + ARM_VBICiv4i16 /* 2108 */, ARM_INS_VBIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vbic${p}.i32 $Vd, $SIMM */ + ARM_VBICiv4i32 /* 2109 */, ARM_INS_VBIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vbic${p}.i16 $Vd, $SIMM */ + ARM_VBICiv8i16 /* 2110 */, ARM_INS_VBIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vbic${p} $Vd, $Vn, $Vm */ + ARM_VBICq /* 2111 */, ARM_INS_VBIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vbif${p} $Vd, $Vn, $Vm */ + ARM_VBIFd /* 2112 */, ARM_INS_VBIF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vbif${p} $Vd, $Vn, $Vm */ + ARM_VBIFq /* 2113 */, ARM_INS_VBIF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vbit${p} $Vd, $Vn, $Vm */ + ARM_VBITd /* 2114 */, ARM_INS_VBIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vbit${p} $Vd, $Vn, $Vm */ + ARM_VBITq /* 2115 */, ARM_INS_VBIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vbsl${p} $Vd, $Vn, $Vm */ + ARM_VBSLd /* 2116 */, ARM_INS_VBSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vbsl${p} $Vd, $Vn, $Vm */ + ARM_VBSLq /* 2117 */, ARM_INS_VBSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VBSPd /* 2118 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VBSPq /* 2119 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vcadd.f32 $Vd, $Vn, $Vm, $rot */ + ARM_VCADDv2f32 /* 2120 */, ARM_INS_VCADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, 0 }, 0, 0 + #endif +}, +{ + /* vcadd.f16 $Vd, $Vn, $Vm, $rot */ + ARM_VCADDv4f16 /* 2121 */, ARM_INS_VCADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcadd.f32 $Vd, $Vn, $Vm, $rot */ + ARM_VCADDv4f32 /* 2122 */, ARM_INS_VCADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, 0 }, 0, 0 + #endif +}, +{ + /* vcadd.f16 $Vd, $Vn, $Vm, $rot */ + ARM_VCADDv8f16 /* 2123 */, ARM_INS_VCADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.f32 $Vd, $Vn, $Vm */ + ARM_VCEQfd /* 2124 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.f32 $Vd, $Vn, $Vm */ + ARM_VCEQfq /* 2125 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.f16 $Vd, $Vn, $Vm */ + ARM_VCEQhd /* 2126 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.f16 $Vd, $Vn, $Vm */ + ARM_VCEQhq /* 2127 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.i8 $Vd, $Vn, $Vm */ + ARM_VCEQv16i8 /* 2128 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.i32 $Vd, $Vn, $Vm */ + ARM_VCEQv2i32 /* 2129 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.i16 $Vd, $Vn, $Vm */ + ARM_VCEQv4i16 /* 2130 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.i32 $Vd, $Vn, $Vm */ + ARM_VCEQv4i32 /* 2131 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.i16 $Vd, $Vn, $Vm */ + ARM_VCEQv8i16 /* 2132 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.i8 $Vd, $Vn, $Vm */ + ARM_VCEQv8i8 /* 2133 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.i8 $Vd, $Vm, #0 */ + ARM_VCEQzv16i8 /* 2134 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.f32 $Vd, $Vm, #0 */ + ARM_VCEQzv2f32 /* 2135 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.i32 $Vd, $Vm, #0 */ + ARM_VCEQzv2i32 /* 2136 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.f16 $Vd, $Vm, #0 */ + ARM_VCEQzv4f16 /* 2137 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.f32 $Vd, $Vm, #0 */ + ARM_VCEQzv4f32 /* 2138 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.i16 $Vd, $Vm, #0 */ + ARM_VCEQzv4i16 /* 2139 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.i32 $Vd, $Vm, #0 */ + ARM_VCEQzv4i32 /* 2140 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.f16 $Vd, $Vm, #0 */ + ARM_VCEQzv8f16 /* 2141 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.i16 $Vd, $Vm, #0 */ + ARM_VCEQzv8i16 /* 2142 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vceq${p}.i8 $Vd, $Vm, #0 */ + ARM_VCEQzv8i8 /* 2143 */, ARM_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.f32 $Vd, $Vn, $Vm */ + ARM_VCGEfd /* 2144 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.f32 $Vd, $Vn, $Vm */ + ARM_VCGEfq /* 2145 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.f16 $Vd, $Vn, $Vm */ + ARM_VCGEhd /* 2146 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.f16 $Vd, $Vn, $Vm */ + ARM_VCGEhq /* 2147 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.s8 $Vd, $Vn, $Vm */ + ARM_VCGEsv16i8 /* 2148 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.s32 $Vd, $Vn, $Vm */ + ARM_VCGEsv2i32 /* 2149 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.s16 $Vd, $Vn, $Vm */ + ARM_VCGEsv4i16 /* 2150 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.s32 $Vd, $Vn, $Vm */ + ARM_VCGEsv4i32 /* 2151 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.s16 $Vd, $Vn, $Vm */ + ARM_VCGEsv8i16 /* 2152 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.s8 $Vd, $Vn, $Vm */ + ARM_VCGEsv8i8 /* 2153 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.u8 $Vd, $Vn, $Vm */ + ARM_VCGEuv16i8 /* 2154 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.u32 $Vd, $Vn, $Vm */ + ARM_VCGEuv2i32 /* 2155 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.u16 $Vd, $Vn, $Vm */ + ARM_VCGEuv4i16 /* 2156 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.u32 $Vd, $Vn, $Vm */ + ARM_VCGEuv4i32 /* 2157 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.u16 $Vd, $Vn, $Vm */ + ARM_VCGEuv8i16 /* 2158 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.u8 $Vd, $Vn, $Vm */ + ARM_VCGEuv8i8 /* 2159 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.s8 $Vd, $Vm, #0 */ + ARM_VCGEzv16i8 /* 2160 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.f32 $Vd, $Vm, #0 */ + ARM_VCGEzv2f32 /* 2161 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.s32 $Vd, $Vm, #0 */ + ARM_VCGEzv2i32 /* 2162 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.f16 $Vd, $Vm, #0 */ + ARM_VCGEzv4f16 /* 2163 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.f32 $Vd, $Vm, #0 */ + ARM_VCGEzv4f32 /* 2164 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.s16 $Vd, $Vm, #0 */ + ARM_VCGEzv4i16 /* 2165 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.s32 $Vd, $Vm, #0 */ + ARM_VCGEzv4i32 /* 2166 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.f16 $Vd, $Vm, #0 */ + ARM_VCGEzv8f16 /* 2167 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.s16 $Vd, $Vm, #0 */ + ARM_VCGEzv8i16 /* 2168 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcge${p}.s8 $Vd, $Vm, #0 */ + ARM_VCGEzv8i8 /* 2169 */, ARM_INS_VCGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.f32 $Vd, $Vn, $Vm */ + ARM_VCGTfd /* 2170 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.f32 $Vd, $Vn, $Vm */ + ARM_VCGTfq /* 2171 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.f16 $Vd, $Vn, $Vm */ + ARM_VCGThd /* 2172 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.f16 $Vd, $Vn, $Vm */ + ARM_VCGThq /* 2173 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.s8 $Vd, $Vn, $Vm */ + ARM_VCGTsv16i8 /* 2174 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.s32 $Vd, $Vn, $Vm */ + ARM_VCGTsv2i32 /* 2175 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.s16 $Vd, $Vn, $Vm */ + ARM_VCGTsv4i16 /* 2176 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.s32 $Vd, $Vn, $Vm */ + ARM_VCGTsv4i32 /* 2177 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.s16 $Vd, $Vn, $Vm */ + ARM_VCGTsv8i16 /* 2178 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.s8 $Vd, $Vn, $Vm */ + ARM_VCGTsv8i8 /* 2179 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.u8 $Vd, $Vn, $Vm */ + ARM_VCGTuv16i8 /* 2180 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.u32 $Vd, $Vn, $Vm */ + ARM_VCGTuv2i32 /* 2181 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.u16 $Vd, $Vn, $Vm */ + ARM_VCGTuv4i16 /* 2182 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.u32 $Vd, $Vn, $Vm */ + ARM_VCGTuv4i32 /* 2183 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.u16 $Vd, $Vn, $Vm */ + ARM_VCGTuv8i16 /* 2184 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.u8 $Vd, $Vn, $Vm */ + ARM_VCGTuv8i8 /* 2185 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.s8 $Vd, $Vm, #0 */ + ARM_VCGTzv16i8 /* 2186 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.f32 $Vd, $Vm, #0 */ + ARM_VCGTzv2f32 /* 2187 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.s32 $Vd, $Vm, #0 */ + ARM_VCGTzv2i32 /* 2188 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.f16 $Vd, $Vm, #0 */ + ARM_VCGTzv4f16 /* 2189 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.f32 $Vd, $Vm, #0 */ + ARM_VCGTzv4f32 /* 2190 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.s16 $Vd, $Vm, #0 */ + ARM_VCGTzv4i16 /* 2191 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.s32 $Vd, $Vm, #0 */ + ARM_VCGTzv4i32 /* 2192 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.f16 $Vd, $Vm, #0 */ + ARM_VCGTzv8f16 /* 2193 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.s16 $Vd, $Vm, #0 */ + ARM_VCGTzv8i16 /* 2194 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcgt${p}.s8 $Vd, $Vm, #0 */ + ARM_VCGTzv8i8 /* 2195 */, ARM_INS_VCGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcle${p}.s8 $Vd, $Vm, #0 */ + ARM_VCLEzv16i8 /* 2196 */, ARM_INS_VCLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcle${p}.f32 $Vd, $Vm, #0 */ + ARM_VCLEzv2f32 /* 2197 */, ARM_INS_VCLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcle${p}.s32 $Vd, $Vm, #0 */ + ARM_VCLEzv2i32 /* 2198 */, ARM_INS_VCLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcle${p}.f16 $Vd, $Vm, #0 */ + ARM_VCLEzv4f16 /* 2199 */, ARM_INS_VCLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcle${p}.f32 $Vd, $Vm, #0 */ + ARM_VCLEzv4f32 /* 2200 */, ARM_INS_VCLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcle${p}.s16 $Vd, $Vm, #0 */ + ARM_VCLEzv4i16 /* 2201 */, ARM_INS_VCLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcle${p}.s32 $Vd, $Vm, #0 */ + ARM_VCLEzv4i32 /* 2202 */, ARM_INS_VCLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcle${p}.f16 $Vd, $Vm, #0 */ + ARM_VCLEzv8f16 /* 2203 */, ARM_INS_VCLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcle${p}.s16 $Vd, $Vm, #0 */ + ARM_VCLEzv8i16 /* 2204 */, ARM_INS_VCLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcle${p}.s8 $Vd, $Vm, #0 */ + ARM_VCLEzv8i8 /* 2205 */, ARM_INS_VCLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcls${p}.s8 $Vd, $Vm */ + ARM_VCLSv16i8 /* 2206 */, ARM_INS_VCLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcls${p}.s32 $Vd, $Vm */ + ARM_VCLSv2i32 /* 2207 */, ARM_INS_VCLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcls${p}.s16 $Vd, $Vm */ + ARM_VCLSv4i16 /* 2208 */, ARM_INS_VCLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcls${p}.s32 $Vd, $Vm */ + ARM_VCLSv4i32 /* 2209 */, ARM_INS_VCLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcls${p}.s16 $Vd, $Vm */ + ARM_VCLSv8i16 /* 2210 */, ARM_INS_VCLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcls${p}.s8 $Vd, $Vm */ + ARM_VCLSv8i8 /* 2211 */, ARM_INS_VCLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclt${p}.s8 $Vd, $Vm, #0 */ + ARM_VCLTzv16i8 /* 2212 */, ARM_INS_VCLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclt${p}.f32 $Vd, $Vm, #0 */ + ARM_VCLTzv2f32 /* 2213 */, ARM_INS_VCLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclt${p}.s32 $Vd, $Vm, #0 */ + ARM_VCLTzv2i32 /* 2214 */, ARM_INS_VCLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclt${p}.f16 $Vd, $Vm, #0 */ + ARM_VCLTzv4f16 /* 2215 */, ARM_INS_VCLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vclt${p}.f32 $Vd, $Vm, #0 */ + ARM_VCLTzv4f32 /* 2216 */, ARM_INS_VCLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclt${p}.s16 $Vd, $Vm, #0 */ + ARM_VCLTzv4i16 /* 2217 */, ARM_INS_VCLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclt${p}.s32 $Vd, $Vm, #0 */ + ARM_VCLTzv4i32 /* 2218 */, ARM_INS_VCLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclt${p}.f16 $Vd, $Vm, #0 */ + ARM_VCLTzv8f16 /* 2219 */, ARM_INS_VCLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vclt${p}.s16 $Vd, $Vm, #0 */ + ARM_VCLTzv8i16 /* 2220 */, ARM_INS_VCLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclt${p}.s8 $Vd, $Vm, #0 */ + ARM_VCLTzv8i8 /* 2221 */, ARM_INS_VCLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclz${p}.i8 $Vd, $Vm */ + ARM_VCLZv16i8 /* 2222 */, ARM_INS_VCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclz${p}.i32 $Vd, $Vm */ + ARM_VCLZv2i32 /* 2223 */, ARM_INS_VCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclz${p}.i16 $Vd, $Vm */ + ARM_VCLZv4i16 /* 2224 */, ARM_INS_VCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclz${p}.i32 $Vd, $Vm */ + ARM_VCLZv4i32 /* 2225 */, ARM_INS_VCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclz${p}.i16 $Vd, $Vm */ + ARM_VCLZv8i16 /* 2226 */, ARM_INS_VCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vclz${p}.i8 $Vd, $Vm */ + ARM_VCLZv8i8 /* 2227 */, ARM_INS_VCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcmla.f32 $Vd, $Vn, $Vm, $rot */ + ARM_VCMLAv2f32 /* 2228 */, ARM_INS_VCMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, 0 }, 0, 0 + #endif +}, +{ + /* vcmla.f32 $Vd, $Vn, $Vm$lane, $rot */ + ARM_VCMLAv2f32_indexed /* 2229 */, ARM_INS_VCMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, 0 }, 0, 0 + #endif +}, +{ + /* vcmla.f16 $Vd, $Vn, $Vm, $rot */ + ARM_VCMLAv4f16 /* 2230 */, ARM_INS_VCMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcmla.f16 $Vd, $Vn, $Vm$lane, $rot */ + ARM_VCMLAv4f16_indexed /* 2231 */, ARM_INS_VCMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcmla.f32 $Vd, $Vn, $Vm, $rot */ + ARM_VCMLAv4f32 /* 2232 */, ARM_INS_VCMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, 0 }, 0, 0 + #endif +}, +{ + /* vcmla.f32 $Vd, $Vn, $Vm$lane, $rot */ + ARM_VCMLAv4f32_indexed /* 2233 */, ARM_INS_VCMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, 0 }, 0, 0 + #endif +}, +{ + /* vcmla.f16 $Vd, $Vn, $Vm, $rot */ + ARM_VCMLAv8f16 /* 2234 */, ARM_INS_VCMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcmla.f16 $Vd, $Vn, $Vm$lane, $rot */ + ARM_VCMLAv8f16_indexed /* 2235 */, ARM_INS_VCMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${p}.f64 $Dd, $Dm */ + ARM_VCMPD /* 2236 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcmpe${p}.f64 $Dd, $Dm */ + ARM_VCMPED /* 2237 */, ARM_INS_VCMPE, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcmpe${p}.f16 $Sd, $Sm */ + ARM_VCMPEH /* 2238 */, ARM_INS_VCMPE, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcmpe${p}.f32 $Sd, $Sm */ + ARM_VCMPES /* 2239 */, ARM_INS_VCMPE, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcmpe${p}.f64 $Dd, #0 */ + ARM_VCMPEZD /* 2240 */, ARM_INS_VCMPE, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcmpe${p}.f16 $Sd, #0 */ + ARM_VCMPEZH /* 2241 */, ARM_INS_VCMPE, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcmpe${p}.f32 $Sd, #0 */ + ARM_VCMPEZS /* 2242 */, ARM_INS_VCMPE, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${p}.f16 $Sd, $Sm */ + ARM_VCMPH /* 2243 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${p}.f32 $Sd, $Sm */ + ARM_VCMPS /* 2244 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${p}.f64 $Dd, #0 */ + ARM_VCMPZD /* 2245 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${p}.f16 $Sd, #0 */ + ARM_VCMPZH /* 2246 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcmp${p}.f32 $Sd, #0 */ + ARM_VCMPZS /* 2247 */, ARM_INS_VCMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcnt${p}.8 $Vd, $Vm */ + ARM_VCNTd /* 2248 */, ARM_INS_VCNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcnt${p}.8 $Vd, $Vm */ + ARM_VCNTq /* 2249 */, ARM_INS_VCNT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.s32.f32 $Vd, $Vm */ + ARM_VCVTANSDf /* 2250 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.s16.f16 $Vd, $Vm */ + ARM_VCVTANSDh /* 2251 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.s32.f32 $Vd, $Vm */ + ARM_VCVTANSQf /* 2252 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.s16.f16 $Vd, $Vm */ + ARM_VCVTANSQh /* 2253 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.u32.f32 $Vd, $Vm */ + ARM_VCVTANUDf /* 2254 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.u16.f16 $Vd, $Vm */ + ARM_VCVTANUDh /* 2255 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.u32.f32 $Vd, $Vm */ + ARM_VCVTANUQf /* 2256 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.u16.f16 $Vd, $Vm */ + ARM_VCVTANUQh /* 2257 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.s32.f64 $Sd, $Dm */ + ARM_VCVTASD /* 2258 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.s32.f16 $Sd, $Sm */ + ARM_VCVTASH /* 2259 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.s32.f32 $Sd, $Sm */ + ARM_VCVTASS /* 2260 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.u32.f64 $Sd, $Dm */ + ARM_VCVTAUD /* 2261 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.u32.f16 $Sd, $Sm */ + ARM_VCVTAUH /* 2262 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvta.u32.f32 $Sd, $Sm */ + ARM_VCVTAUS /* 2263 */, ARM_INS_VCVTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vcvtb${p}.f16.f64 $Sd, $Dm */ + ARM_VCVTBDH /* 2264 */, ARM_INS_VCVTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtb${p}.f64.f16 $Dd, $Sm */ + ARM_VCVTBHD /* 2265 */, ARM_INS_VCVTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtb${p}.f32.f16 $Sd, $Sm */ + ARM_VCVTBHS /* 2266 */, ARM_INS_VCVTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtb${p}.f16.f32 $Sd, $Sm */ + ARM_VCVTBSH /* 2267 */, ARM_INS_VCVTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f64.f32 $Dd, $Sm */ + ARM_VCVTDS /* 2268 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.s32.f32 $Vd, $Vm */ + ARM_VCVTMNSDf /* 2269 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.s16.f16 $Vd, $Vm */ + ARM_VCVTMNSDh /* 2270 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.s32.f32 $Vd, $Vm */ + ARM_VCVTMNSQf /* 2271 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.s16.f16 $Vd, $Vm */ + ARM_VCVTMNSQh /* 2272 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.u32.f32 $Vd, $Vm */ + ARM_VCVTMNUDf /* 2273 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.u16.f16 $Vd, $Vm */ + ARM_VCVTMNUDh /* 2274 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.u32.f32 $Vd, $Vm */ + ARM_VCVTMNUQf /* 2275 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.u16.f16 $Vd, $Vm */ + ARM_VCVTMNUQh /* 2276 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.s32.f64 $Sd, $Dm */ + ARM_VCVTMSD /* 2277 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.s32.f16 $Sd, $Sm */ + ARM_VCVTMSH /* 2278 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.s32.f32 $Sd, $Sm */ + ARM_VCVTMSS /* 2279 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.u32.f64 $Sd, $Dm */ + ARM_VCVTMUD /* 2280 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.u32.f16 $Sd, $Sm */ + ARM_VCVTMUH /* 2281 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtm.u32.f32 $Sd, $Sm */ + ARM_VCVTMUS /* 2282 */, ARM_INS_VCVTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.s32.f32 $Vd, $Vm */ + ARM_VCVTNNSDf /* 2283 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.s16.f16 $Vd, $Vm */ + ARM_VCVTNNSDh /* 2284 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.s32.f32 $Vd, $Vm */ + ARM_VCVTNNSQf /* 2285 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.s16.f16 $Vd, $Vm */ + ARM_VCVTNNSQh /* 2286 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.u32.f32 $Vd, $Vm */ + ARM_VCVTNNUDf /* 2287 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.u16.f16 $Vd, $Vm */ + ARM_VCVTNNUDh /* 2288 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.u32.f32 $Vd, $Vm */ + ARM_VCVTNNUQf /* 2289 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.u16.f16 $Vd, $Vm */ + ARM_VCVTNNUQh /* 2290 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.s32.f64 $Sd, $Dm */ + ARM_VCVTNSD /* 2291 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.s32.f16 $Sd, $Sm */ + ARM_VCVTNSH /* 2292 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.s32.f32 $Sd, $Sm */ + ARM_VCVTNSS /* 2293 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.u32.f64 $Sd, $Dm */ + ARM_VCVTNUD /* 2294 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.u32.f16 $Sd, $Sm */ + ARM_VCVTNUH /* 2295 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtn.u32.f32 $Sd, $Sm */ + ARM_VCVTNUS /* 2296 */, ARM_INS_VCVTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.s32.f32 $Vd, $Vm */ + ARM_VCVTPNSDf /* 2297 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.s16.f16 $Vd, $Vm */ + ARM_VCVTPNSDh /* 2298 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.s32.f32 $Vd, $Vm */ + ARM_VCVTPNSQf /* 2299 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.s16.f16 $Vd, $Vm */ + ARM_VCVTPNSQh /* 2300 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.u32.f32 $Vd, $Vm */ + ARM_VCVTPNUDf /* 2301 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.u16.f16 $Vd, $Vm */ + ARM_VCVTPNUDh /* 2302 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.u32.f32 $Vd, $Vm */ + ARM_VCVTPNUQf /* 2303 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.u16.f16 $Vd, $Vm */ + ARM_VCVTPNUQh /* 2304 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.s32.f64 $Sd, $Dm */ + ARM_VCVTPSD /* 2305 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.s32.f16 $Sd, $Sm */ + ARM_VCVTPSH /* 2306 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.s32.f32 $Sd, $Sm */ + ARM_VCVTPSS /* 2307 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.u32.f64 $Sd, $Dm */ + ARM_VCVTPUD /* 2308 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.u32.f16 $Sd, $Sm */ + ARM_VCVTPUH /* 2309 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtp.u32.f32 $Sd, $Sm */ + ARM_VCVTPUS /* 2310 */, ARM_INS_VCVTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.f64 $Sd, $Dm */ + ARM_VCVTSD /* 2311 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtt${p}.f16.f64 $Sd, $Dm */ + ARM_VCVTTDH /* 2312 */, ARM_INS_VCVTT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtt${p}.f64.f16 $Dd, $Sm */ + ARM_VCVTTHD /* 2313 */, ARM_INS_VCVTT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtt${p}.f32.f16 $Sd, $Sm */ + ARM_VCVTTHS /* 2314 */, ARM_INS_VCVTT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtt${p}.f16.f32 $Sd, $Sm */ + ARM_VCVTTSH /* 2315 */, ARM_INS_VCVTT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.f32 $Vd, $Vm */ + ARM_VCVTf2h /* 2316 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s32.f32 $Vd, $Vm */ + ARM_VCVTf2sd /* 2317 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s32.f32 $Vd, $Vm */ + ARM_VCVTf2sq /* 2318 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u32.f32 $Vd, $Vm */ + ARM_VCVTf2ud /* 2319 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u32.f32 $Vd, $Vm */ + ARM_VCVTf2uq /* 2320 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s32.f32 $Vd, $Vm, $SIMM */ + ARM_VCVTf2xsd /* 2321 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s32.f32 $Vd, $Vm, $SIMM */ + ARM_VCVTf2xsq /* 2322 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u32.f32 $Vd, $Vm, $SIMM */ + ARM_VCVTf2xud /* 2323 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u32.f32 $Vd, $Vm, $SIMM */ + ARM_VCVTf2xuq /* 2324 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.f16 $Vd, $Vm */ + ARM_VCVTh2f /* 2325 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s16.f16 $Vd, $Vm */ + ARM_VCVTh2sd /* 2326 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s16.f16 $Vd, $Vm */ + ARM_VCVTh2sq /* 2327 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u16.f16 $Vd, $Vm */ + ARM_VCVTh2ud /* 2328 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u16.f16 $Vd, $Vm */ + ARM_VCVTh2uq /* 2329 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s16.f16 $Vd, $Vm, $SIMM */ + ARM_VCVTh2xsd /* 2330 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s16.f16 $Vd, $Vm, $SIMM */ + ARM_VCVTh2xsq /* 2331 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u16.f16 $Vd, $Vm, $SIMM */ + ARM_VCVTh2xud /* 2332 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u16.f16 $Vd, $Vm, $SIMM */ + ARM_VCVTh2xuq /* 2333 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.s32 $Vd, $Vm */ + ARM_VCVTs2fd /* 2334 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.s32 $Vd, $Vm */ + ARM_VCVTs2fq /* 2335 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.s16 $Vd, $Vm */ + ARM_VCVTs2hd /* 2336 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.s16 $Vd, $Vm */ + ARM_VCVTs2hq /* 2337 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.u32 $Vd, $Vm */ + ARM_VCVTu2fd /* 2338 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.u32 $Vd, $Vm */ + ARM_VCVTu2fq /* 2339 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.u16 $Vd, $Vm */ + ARM_VCVTu2hd /* 2340 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.u16 $Vd, $Vm */ + ARM_VCVTu2hq /* 2341 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.s32 $Vd, $Vm, $SIMM */ + ARM_VCVTxs2fd /* 2342 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.s32 $Vd, $Vm, $SIMM */ + ARM_VCVTxs2fq /* 2343 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.s16 $Vd, $Vm, $SIMM */ + ARM_VCVTxs2hd /* 2344 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.s16 $Vd, $Vm, $SIMM */ + ARM_VCVTxs2hq /* 2345 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.u32 $Vd, $Vm, $SIMM */ + ARM_VCVTxu2fd /* 2346 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.u32 $Vd, $Vm, $SIMM */ + ARM_VCVTxu2fq /* 2347 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.u16 $Vd, $Vm, $SIMM */ + ARM_VCVTxu2hd /* 2348 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.u16 $Vd, $Vm, $SIMM */ + ARM_VCVTxu2hq /* 2349 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vdiv${p}.f64 $Dd, $Dn, $Dm */ + ARM_VDIVD /* 2350 */, ARM_INS_VDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vdiv${p}.f16 $Sd, $Sn, $Sm */ + ARM_VDIVH /* 2351 */, ARM_INS_VDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vdiv${p}.f32 $Sd, $Sn, $Sm */ + ARM_VDIVS /* 2352 */, ARM_INS_VDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vdup${p}.16 $V, $R */ + ARM_VDUP16d /* 2353 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdup${p}.16 $V, $R */ + ARM_VDUP16q /* 2354 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdup${p}.32 $V, $R */ + ARM_VDUP32d /* 2355 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdup${p}.32 $V, $R */ + ARM_VDUP32q /* 2356 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdup${p}.8 $V, $R */ + ARM_VDUP8d /* 2357 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdup${p}.8 $V, $R */ + ARM_VDUP8q /* 2358 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdup${p}.16 $Vd, $Vm$lane */ + ARM_VDUPLN16d /* 2359 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdup${p}.16 $Vd, $Vm$lane */ + ARM_VDUPLN16q /* 2360 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdup${p}.32 $Vd, $Vm$lane */ + ARM_VDUPLN32d /* 2361 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdup${p}.32 $Vd, $Vm$lane */ + ARM_VDUPLN32q /* 2362 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdup${p}.8 $Vd, $Vm$lane */ + ARM_VDUPLN8d /* 2363 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vdup${p}.8 $Vd, $Vm$lane */ + ARM_VDUPLN8q /* 2364 */, ARM_INS_VDUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* veor${p} $Vd, $Vn, $Vm */ + ARM_VEORd /* 2365 */, ARM_INS_VEOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* veor${p} $Vd, $Vn, $Vm */ + ARM_VEORq /* 2366 */, ARM_INS_VEOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vext${p}.16 $Vd, $Vn, $Vm, $index */ + ARM_VEXTd16 /* 2367 */, ARM_INS_VEXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vext${p}.32 $Vd, $Vn, $Vm, $index */ + ARM_VEXTd32 /* 2368 */, ARM_INS_VEXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vext${p}.8 $Vd, $Vn, $Vm, $index */ + ARM_VEXTd8 /* 2369 */, ARM_INS_VEXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vext${p}.16 $Vd, $Vn, $Vm, $index */ + ARM_VEXTq16 /* 2370 */, ARM_INS_VEXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vext${p}.32 $Vd, $Vn, $Vm, $index */ + ARM_VEXTq32 /* 2371 */, ARM_INS_VEXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vext${p}.64 $Vd, $Vn, $Vm, $index */ + ARM_VEXTq64 /* 2372 */, ARM_INS_VEXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vext${p}.8 $Vd, $Vn, $Vm, $index */ + ARM_VEXTq8 /* 2373 */, ARM_INS_VEXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vfma${p}.f64 $Dd, $Dn, $Dm */ + ARM_VFMAD /* 2374 */, ARM_INS_VFMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vfma${p}.f16 $Sd, $Sn, $Sm */ + ARM_VFMAH /* 2375 */, ARM_INS_VFMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vfmal.f16 $Vd, $Vn, $Vm */ + ARM_VFMALD /* 2376 */, ARM_INS_VFMAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0 + #endif +}, +{ + /* vfmal.f16 $Vd, $Vn, $Vm$idx */ + ARM_VFMALDI /* 2377 */, ARM_INS_VFMAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0 + #endif +}, +{ + /* vfmal.f16 $Vd, $Vn, $Vm */ + ARM_VFMALQ /* 2378 */, ARM_INS_VFMAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0 + #endif +}, +{ + /* vfmal.f16 $Vd, $Vn, $Vm$idx */ + ARM_VFMALQI /* 2379 */, ARM_INS_VFMAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0 + #endif +}, +{ + /* vfma${p}.f32 $Sd, $Sn, $Sm */ + ARM_VFMAS /* 2380 */, ARM_INS_VFMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, 0 }, 0, 0 + #endif +}, +{ + /* vfma${p}.f32 $Vd, $Vn, $Vm */ + ARM_VFMAfd /* 2381 */, ARM_INS_VFMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasVFP4, 0 }, 0, 0 + #endif +}, +{ + /* vfma${p}.f32 $Vd, $Vn, $Vm */ + ARM_VFMAfq /* 2382 */, ARM_INS_VFMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasVFP4, 0 }, 0, 0 + #endif +}, +{ + /* vfma${p}.f16 $Vd, $Vn, $Vm */ + ARM_VFMAhd /* 2383 */, ARM_INS_VFMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vfma${p}.f16 $Vd, $Vn, $Vm */ + ARM_VFMAhq /* 2384 */, ARM_INS_VFMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vfms${p}.f64 $Dd, $Dn, $Dm */ + ARM_VFMSD /* 2385 */, ARM_INS_VFMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vfms${p}.f16 $Sd, $Sn, $Sm */ + ARM_VFMSH /* 2386 */, ARM_INS_VFMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vfmsl.f16 $Vd, $Vn, $Vm */ + ARM_VFMSLD /* 2387 */, ARM_INS_VFMSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0 + #endif +}, +{ + /* vfmsl.f16 $Vd, $Vn, $Vm$idx */ + ARM_VFMSLDI /* 2388 */, ARM_INS_VFMSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0 + #endif +}, +{ + /* vfmsl.f16 $Vd, $Vn, $Vm */ + ARM_VFMSLQ /* 2389 */, ARM_INS_VFMSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0 + #endif +}, +{ + /* vfmsl.f16 $Vd, $Vn, $Vm$idx */ + ARM_VFMSLQI /* 2390 */, ARM_INS_VFMSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0 + #endif +}, +{ + /* vfms${p}.f32 $Sd, $Sn, $Sm */ + ARM_VFMSS /* 2391 */, ARM_INS_VFMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, 0 }, 0, 0 + #endif +}, +{ + /* vfms${p}.f32 $Vd, $Vn, $Vm */ + ARM_VFMSfd /* 2392 */, ARM_INS_VFMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasVFP4, 0 }, 0, 0 + #endif +}, +{ + /* vfms${p}.f32 $Vd, $Vn, $Vm */ + ARM_VFMSfq /* 2393 */, ARM_INS_VFMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasVFP4, 0 }, 0, 0 + #endif +}, +{ + /* vfms${p}.f16 $Vd, $Vn, $Vm */ + ARM_VFMShd /* 2394 */, ARM_INS_VFMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vfms${p}.f16 $Vd, $Vn, $Vm */ + ARM_VFMShq /* 2395 */, ARM_INS_VFMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vfnma${p}.f64 $Dd, $Dn, $Dm */ + ARM_VFNMAD /* 2396 */, ARM_INS_VFNMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vfnma${p}.f16 $Sd, $Sn, $Sm */ + ARM_VFNMAH /* 2397 */, ARM_INS_VFNMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vfnma${p}.f32 $Sd, $Sn, $Sm */ + ARM_VFNMAS /* 2398 */, ARM_INS_VFNMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, 0 }, 0, 0 + #endif +}, +{ + /* vfnms${p}.f64 $Dd, $Dn, $Dm */ + ARM_VFNMSD /* 2399 */, ARM_INS_VFNMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vfnms${p}.f16 $Sd, $Sn, $Sm */ + ARM_VFNMSH /* 2400 */, ARM_INS_VFNMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vfnms${p}.f32 $Sd, $Sn, $Sm */ + ARM_VFNMSS /* 2401 */, ARM_INS_VFNMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnm.f64 $Dd, $Dn, $Dm */ + ARM_VFP_VMAXNMD /* 2402 */, ARM_INS_VMAXNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnm.f16 $Sd, $Sn, $Sm */ + ARM_VFP_VMAXNMH /* 2403 */, ARM_INS_VMAXNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmaxnm.f32 $Sd, $Sn, $Sm */ + ARM_VFP_VMAXNMS /* 2404 */, ARM_INS_VMAXNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vminnm.f64 $Dd, $Dn, $Dm */ + ARM_VFP_VMINNMD /* 2405 */, ARM_INS_VMINNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vminnm.f16 $Sd, $Sn, $Sm */ + ARM_VFP_VMINNMH /* 2406 */, ARM_INS_VMINNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vminnm.f32 $Sd, $Sn, $Sm */ + ARM_VFP_VMINNMS /* 2407 */, ARM_INS_VMINNM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.32 $R, $V$lane */ + ARM_VGETLNi32 /* 2408 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.s16 $R, $V$lane */ + ARM_VGETLNs16 /* 2409 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.s8 $R, $V$lane */ + ARM_VGETLNs8 /* 2410 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.u16 $R, $V$lane */ + ARM_VGETLNu16 /* 2411 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.u8 $R, $V$lane */ + ARM_VGETLNu8 /* 2412 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${p}.s8 $Vd, $Vn, $Vm */ + ARM_VHADDsv16i8 /* 2413 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${p}.s32 $Vd, $Vn, $Vm */ + ARM_VHADDsv2i32 /* 2414 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${p}.s16 $Vd, $Vn, $Vm */ + ARM_VHADDsv4i16 /* 2415 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${p}.s32 $Vd, $Vn, $Vm */ + ARM_VHADDsv4i32 /* 2416 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${p}.s16 $Vd, $Vn, $Vm */ + ARM_VHADDsv8i16 /* 2417 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${p}.s8 $Vd, $Vn, $Vm */ + ARM_VHADDsv8i8 /* 2418 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${p}.u8 $Vd, $Vn, $Vm */ + ARM_VHADDuv16i8 /* 2419 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${p}.u32 $Vd, $Vn, $Vm */ + ARM_VHADDuv2i32 /* 2420 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${p}.u16 $Vd, $Vn, $Vm */ + ARM_VHADDuv4i16 /* 2421 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${p}.u32 $Vd, $Vn, $Vm */ + ARM_VHADDuv4i32 /* 2422 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${p}.u16 $Vd, $Vn, $Vm */ + ARM_VHADDuv8i16 /* 2423 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhadd${p}.u8 $Vd, $Vn, $Vm */ + ARM_VHADDuv8i8 /* 2424 */, ARM_INS_VHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${p}.s8 $Vd, $Vn, $Vm */ + ARM_VHSUBsv16i8 /* 2425 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${p}.s32 $Vd, $Vn, $Vm */ + ARM_VHSUBsv2i32 /* 2426 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${p}.s16 $Vd, $Vn, $Vm */ + ARM_VHSUBsv4i16 /* 2427 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${p}.s32 $Vd, $Vn, $Vm */ + ARM_VHSUBsv4i32 /* 2428 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${p}.s16 $Vd, $Vn, $Vm */ + ARM_VHSUBsv8i16 /* 2429 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${p}.s8 $Vd, $Vn, $Vm */ + ARM_VHSUBsv8i8 /* 2430 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${p}.u8 $Vd, $Vn, $Vm */ + ARM_VHSUBuv16i8 /* 2431 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${p}.u32 $Vd, $Vn, $Vm */ + ARM_VHSUBuv2i32 /* 2432 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${p}.u16 $Vd, $Vn, $Vm */ + ARM_VHSUBuv4i16 /* 2433 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${p}.u32 $Vd, $Vn, $Vm */ + ARM_VHSUBuv4i32 /* 2434 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${p}.u16 $Vd, $Vn, $Vm */ + ARM_VHSUBuv8i16 /* 2435 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vhsub${p}.u8 $Vd, $Vn, $Vm */ + ARM_VHSUBuv8i8 /* 2436 */, ARM_INS_VHSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vins.f16 $Sd, $Sm */ + ARM_VINSH /* 2437 */, ARM_INS_VINS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vjcvt${p}.s32.f64 $Sd, $Dm */ + ARM_VJCVT /* 2438 */, ARM_INS_VJCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasV8_3a, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn */ + ARM_VLD1DUPd16 /* 2439 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn! */ + ARM_VLD1DUPd16wb_fixed /* 2440 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn, $Rm */ + ARM_VLD1DUPd16wb_register /* 2441 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn */ + ARM_VLD1DUPd32 /* 2442 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn! */ + ARM_VLD1DUPd32wb_fixed /* 2443 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn, $Rm */ + ARM_VLD1DUPd32wb_register /* 2444 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn */ + ARM_VLD1DUPd8 /* 2445 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn! */ + ARM_VLD1DUPd8wb_fixed /* 2446 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn, $Rm */ + ARM_VLD1DUPd8wb_register /* 2447 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn */ + ARM_VLD1DUPq16 /* 2448 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn! */ + ARM_VLD1DUPq16wb_fixed /* 2449 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn, $Rm */ + ARM_VLD1DUPq16wb_register /* 2450 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn */ + ARM_VLD1DUPq32 /* 2451 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn! */ + ARM_VLD1DUPq32wb_fixed /* 2452 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn, $Rm */ + ARM_VLD1DUPq32wb_register /* 2453 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn */ + ARM_VLD1DUPq8 /* 2454 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn! */ + ARM_VLD1DUPq8wb_fixed /* 2455 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn, $Rm */ + ARM_VLD1DUPq8wb_register /* 2456 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 \{$Vd[$lane]\}, $Rn */ + ARM_VLD1LNd16 /* 2457 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 \{$Vd[$lane]\}, $Rn$Rm */ + ARM_VLD1LNd16_UPD /* 2458 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 \{$Vd[$lane]\}, $Rn */ + ARM_VLD1LNd32 /* 2459 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 \{$Vd[$lane]\}, $Rn$Rm */ + ARM_VLD1LNd32_UPD /* 2460 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 \{$Vd[$lane]\}, $Rn */ + ARM_VLD1LNd8 /* 2461 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 \{$Vd[$lane]\}, $Rn$Rm */ + ARM_VLD1LNd8_UPD /* 2462 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1LNq16Pseudo /* 2463 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1LNq16Pseudo_UPD /* 2464 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1LNq32Pseudo /* 2465 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1LNq32Pseudo_UPD /* 2466 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1LNq8Pseudo /* 2467 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1LNq8Pseudo_UPD /* 2468 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn */ + ARM_VLD1d16 /* 2469 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn */ + ARM_VLD1d16Q /* 2470 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d16QPseudo /* 2471 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d16QPseudoWB_fixed /* 2472 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d16QPseudoWB_register /* 2473 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn! */ + ARM_VLD1d16Qwb_fixed /* 2474 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn, $Rm */ + ARM_VLD1d16Qwb_register /* 2475 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn */ + ARM_VLD1d16T /* 2476 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d16TPseudo /* 2477 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d16TPseudoWB_fixed /* 2478 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d16TPseudoWB_register /* 2479 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn! */ + ARM_VLD1d16Twb_fixed /* 2480 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn, $Rm */ + ARM_VLD1d16Twb_register /* 2481 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn! */ + ARM_VLD1d16wb_fixed /* 2482 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn, $Rm */ + ARM_VLD1d16wb_register /* 2483 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn */ + ARM_VLD1d32 /* 2484 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn */ + ARM_VLD1d32Q /* 2485 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d32QPseudo /* 2486 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d32QPseudoWB_fixed /* 2487 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d32QPseudoWB_register /* 2488 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn! */ + ARM_VLD1d32Qwb_fixed /* 2489 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn, $Rm */ + ARM_VLD1d32Qwb_register /* 2490 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn */ + ARM_VLD1d32T /* 2491 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d32TPseudo /* 2492 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d32TPseudoWB_fixed /* 2493 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d32TPseudoWB_register /* 2494 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn! */ + ARM_VLD1d32Twb_fixed /* 2495 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn, $Rm */ + ARM_VLD1d32Twb_register /* 2496 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn! */ + ARM_VLD1d32wb_fixed /* 2497 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn, $Rm */ + ARM_VLD1d32wb_register /* 2498 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.64 $Vd, $Rn */ + ARM_VLD1d64 /* 2499 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.64 $Vd, $Rn */ + ARM_VLD1d64Q /* 2500 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d64QPseudo /* 2501 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d64QPseudoWB_fixed /* 2502 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d64QPseudoWB_register /* 2503 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.64 $Vd, $Rn! */ + ARM_VLD1d64Qwb_fixed /* 2504 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.64 $Vd, $Rn, $Rm */ + ARM_VLD1d64Qwb_register /* 2505 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.64 $Vd, $Rn */ + ARM_VLD1d64T /* 2506 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d64TPseudo /* 2507 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d64TPseudoWB_fixed /* 2508 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d64TPseudoWB_register /* 2509 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.64 $Vd, $Rn! */ + ARM_VLD1d64Twb_fixed /* 2510 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.64 $Vd, $Rn, $Rm */ + ARM_VLD1d64Twb_register /* 2511 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.64 $Vd, $Rn! */ + ARM_VLD1d64wb_fixed /* 2512 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.64 $Vd, $Rn, $Rm */ + ARM_VLD1d64wb_register /* 2513 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn */ + ARM_VLD1d8 /* 2514 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn */ + ARM_VLD1d8Q /* 2515 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d8QPseudo /* 2516 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d8QPseudoWB_fixed /* 2517 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d8QPseudoWB_register /* 2518 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn! */ + ARM_VLD1d8Qwb_fixed /* 2519 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn, $Rm */ + ARM_VLD1d8Qwb_register /* 2520 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn */ + ARM_VLD1d8T /* 2521 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d8TPseudo /* 2522 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d8TPseudoWB_fixed /* 2523 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1d8TPseudoWB_register /* 2524 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn! */ + ARM_VLD1d8Twb_fixed /* 2525 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn, $Rm */ + ARM_VLD1d8Twb_register /* 2526 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn! */ + ARM_VLD1d8wb_fixed /* 2527 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn, $Rm */ + ARM_VLD1d8wb_register /* 2528 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn */ + ARM_VLD1q16 /* 2529 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q16HighQPseudo /* 2530 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q16HighQPseudo_UPD /* 2531 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q16HighTPseudo /* 2532 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q16HighTPseudo_UPD /* 2533 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q16LowQPseudo_UPD /* 2534 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q16LowTPseudo_UPD /* 2535 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn! */ + ARM_VLD1q16wb_fixed /* 2536 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.16 $Vd, $Rn, $Rm */ + ARM_VLD1q16wb_register /* 2537 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn */ + ARM_VLD1q32 /* 2538 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q32HighQPseudo /* 2539 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q32HighQPseudo_UPD /* 2540 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q32HighTPseudo /* 2541 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q32HighTPseudo_UPD /* 2542 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q32LowQPseudo_UPD /* 2543 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q32LowTPseudo_UPD /* 2544 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn! */ + ARM_VLD1q32wb_fixed /* 2545 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.32 $Vd, $Rn, $Rm */ + ARM_VLD1q32wb_register /* 2546 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.64 $Vd, $Rn */ + ARM_VLD1q64 /* 2547 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q64HighQPseudo /* 2548 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q64HighQPseudo_UPD /* 2549 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q64HighTPseudo /* 2550 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q64HighTPseudo_UPD /* 2551 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q64LowQPseudo_UPD /* 2552 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q64LowTPseudo_UPD /* 2553 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.64 $Vd, $Rn! */ + ARM_VLD1q64wb_fixed /* 2554 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.64 $Vd, $Rn, $Rm */ + ARM_VLD1q64wb_register /* 2555 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn */ + ARM_VLD1q8 /* 2556 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q8HighQPseudo /* 2557 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q8HighQPseudo_UPD /* 2558 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q8HighTPseudo /* 2559 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q8HighTPseudo_UPD /* 2560 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q8LowQPseudo_UPD /* 2561 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD1q8LowTPseudo_UPD /* 2562 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn! */ + ARM_VLD1q8wb_fixed /* 2563 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld1${p}.8 $Vd, $Rn, $Rm */ + ARM_VLD1q8wb_register /* 2564 */, ARM_INS_VLD1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn */ + ARM_VLD2DUPd16 /* 2565 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn! */ + ARM_VLD2DUPd16wb_fixed /* 2566 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn, $Rm */ + ARM_VLD2DUPd16wb_register /* 2567 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn */ + ARM_VLD2DUPd16x2 /* 2568 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn! */ + ARM_VLD2DUPd16x2wb_fixed /* 2569 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn, $Rm */ + ARM_VLD2DUPd16x2wb_register /* 2570 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn */ + ARM_VLD2DUPd32 /* 2571 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn! */ + ARM_VLD2DUPd32wb_fixed /* 2572 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn, $Rm */ + ARM_VLD2DUPd32wb_register /* 2573 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn */ + ARM_VLD2DUPd32x2 /* 2574 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn! */ + ARM_VLD2DUPd32x2wb_fixed /* 2575 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn, $Rm */ + ARM_VLD2DUPd32x2wb_register /* 2576 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn */ + ARM_VLD2DUPd8 /* 2577 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn! */ + ARM_VLD2DUPd8wb_fixed /* 2578 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn, $Rm */ + ARM_VLD2DUPd8wb_register /* 2579 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn */ + ARM_VLD2DUPd8x2 /* 2580 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn! */ + ARM_VLD2DUPd8x2wb_fixed /* 2581 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn, $Rm */ + ARM_VLD2DUPd8x2wb_register /* 2582 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2DUPq16EvenPseudo /* 2583 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2DUPq16OddPseudo /* 2584 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2DUPq16OddPseudoWB_fixed /* 2585 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2DUPq16OddPseudoWB_register /* 2586 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2DUPq32EvenPseudo /* 2587 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2DUPq32OddPseudo /* 2588 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2DUPq32OddPseudoWB_fixed /* 2589 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2DUPq32OddPseudoWB_register /* 2590 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2DUPq8EvenPseudo /* 2591 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2DUPq8OddPseudo /* 2592 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2DUPq8OddPseudoWB_fixed /* 2593 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2DUPq8OddPseudoWB_register /* 2594 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 \{$Vd[$lane], $dst2[$lane]\}, $Rn */ + ARM_VLD2LNd16 /* 2595 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2LNd16Pseudo /* 2596 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2LNd16Pseudo_UPD /* 2597 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 \{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */ + ARM_VLD2LNd16_UPD /* 2598 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 \{$Vd[$lane], $dst2[$lane]\}, $Rn */ + ARM_VLD2LNd32 /* 2599 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2LNd32Pseudo /* 2600 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2LNd32Pseudo_UPD /* 2601 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 \{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */ + ARM_VLD2LNd32_UPD /* 2602 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 \{$Vd[$lane], $dst2[$lane]\}, $Rn */ + ARM_VLD2LNd8 /* 2603 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2LNd8Pseudo /* 2604 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2LNd8Pseudo_UPD /* 2605 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 \{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */ + ARM_VLD2LNd8_UPD /* 2606 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 \{$Vd[$lane], $dst2[$lane]\}, $Rn */ + ARM_VLD2LNq16 /* 2607 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2LNq16Pseudo /* 2608 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2LNq16Pseudo_UPD /* 2609 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 \{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */ + ARM_VLD2LNq16_UPD /* 2610 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 \{$Vd[$lane], $dst2[$lane]\}, $Rn */ + ARM_VLD2LNq32 /* 2611 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2LNq32Pseudo /* 2612 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2LNq32Pseudo_UPD /* 2613 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 \{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */ + ARM_VLD2LNq32_UPD /* 2614 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn */ + ARM_VLD2b16 /* 2615 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn! */ + ARM_VLD2b16wb_fixed /* 2616 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn, $Rm */ + ARM_VLD2b16wb_register /* 2617 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn */ + ARM_VLD2b32 /* 2618 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn! */ + ARM_VLD2b32wb_fixed /* 2619 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn, $Rm */ + ARM_VLD2b32wb_register /* 2620 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn */ + ARM_VLD2b8 /* 2621 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn! */ + ARM_VLD2b8wb_fixed /* 2622 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn, $Rm */ + ARM_VLD2b8wb_register /* 2623 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn */ + ARM_VLD2d16 /* 2624 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn! */ + ARM_VLD2d16wb_fixed /* 2625 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn, $Rm */ + ARM_VLD2d16wb_register /* 2626 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn */ + ARM_VLD2d32 /* 2627 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn! */ + ARM_VLD2d32wb_fixed /* 2628 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn, $Rm */ + ARM_VLD2d32wb_register /* 2629 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn */ + ARM_VLD2d8 /* 2630 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn! */ + ARM_VLD2d8wb_fixed /* 2631 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn, $Rm */ + ARM_VLD2d8wb_register /* 2632 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn */ + ARM_VLD2q16 /* 2633 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2q16Pseudo /* 2634 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2q16PseudoWB_fixed /* 2635 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2q16PseudoWB_register /* 2636 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn! */ + ARM_VLD2q16wb_fixed /* 2637 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.16 $Vd, $Rn, $Rm */ + ARM_VLD2q16wb_register /* 2638 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn */ + ARM_VLD2q32 /* 2639 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2q32Pseudo /* 2640 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2q32PseudoWB_fixed /* 2641 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2q32PseudoWB_register /* 2642 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn! */ + ARM_VLD2q32wb_fixed /* 2643 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.32 $Vd, $Rn, $Rm */ + ARM_VLD2q32wb_register /* 2644 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn */ + ARM_VLD2q8 /* 2645 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2q8Pseudo /* 2646 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2q8PseudoWB_fixed /* 2647 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD2q8PseudoWB_register /* 2648 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn! */ + ARM_VLD2q8wb_fixed /* 2649 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld2${p}.8 $Vd, $Rn, $Rm */ + ARM_VLD2q8wb_register /* 2650 */, ARM_INS_VLD2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 \{$Vd[], $dst2[], $dst3[]\}, $Rn */ + ARM_VLD3DUPd16 /* 2651 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPd16Pseudo /* 2652 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPd16Pseudo_UPD /* 2653 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 \{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */ + ARM_VLD3DUPd16_UPD /* 2654 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 \{$Vd[], $dst2[], $dst3[]\}, $Rn */ + ARM_VLD3DUPd32 /* 2655 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPd32Pseudo /* 2656 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPd32Pseudo_UPD /* 2657 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 \{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */ + ARM_VLD3DUPd32_UPD /* 2658 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 \{$Vd[], $dst2[], $dst3[]\}, $Rn */ + ARM_VLD3DUPd8 /* 2659 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPd8Pseudo /* 2660 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPd8Pseudo_UPD /* 2661 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 \{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */ + ARM_VLD3DUPd8_UPD /* 2662 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 \{$Vd[], $dst2[], $dst3[]\}, $Rn */ + ARM_VLD3DUPq16 /* 2663 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPq16EvenPseudo /* 2664 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPq16OddPseudo /* 2665 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPq16OddPseudo_UPD /* 2666 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 \{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */ + ARM_VLD3DUPq16_UPD /* 2667 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 \{$Vd[], $dst2[], $dst3[]\}, $Rn */ + ARM_VLD3DUPq32 /* 2668 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPq32EvenPseudo /* 2669 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPq32OddPseudo /* 2670 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPq32OddPseudo_UPD /* 2671 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 \{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */ + ARM_VLD3DUPq32_UPD /* 2672 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 \{$Vd[], $dst2[], $dst3[]\}, $Rn */ + ARM_VLD3DUPq8 /* 2673 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPq8EvenPseudo /* 2674 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPq8OddPseudo /* 2675 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3DUPq8OddPseudo_UPD /* 2676 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 \{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */ + ARM_VLD3DUPq8_UPD /* 2677 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */ + ARM_VLD3LNd16 /* 2678 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3LNd16Pseudo /* 2679 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3LNd16Pseudo_UPD /* 2680 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */ + ARM_VLD3LNd16_UPD /* 2681 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */ + ARM_VLD3LNd32 /* 2682 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3LNd32Pseudo /* 2683 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3LNd32Pseudo_UPD /* 2684 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */ + ARM_VLD3LNd32_UPD /* 2685 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */ + ARM_VLD3LNd8 /* 2686 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3LNd8Pseudo /* 2687 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3LNd8Pseudo_UPD /* 2688 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */ + ARM_VLD3LNd8_UPD /* 2689 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */ + ARM_VLD3LNq16 /* 2690 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3LNq16Pseudo /* 2691 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3LNq16Pseudo_UPD /* 2692 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */ + ARM_VLD3LNq16_UPD /* 2693 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */ + ARM_VLD3LNq32 /* 2694 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3LNq32Pseudo /* 2695 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3LNq32Pseudo_UPD /* 2696 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */ + ARM_VLD3LNq32_UPD /* 2697 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 \{$Vd, $dst2, $dst3\}, $Rn */ + ARM_VLD3d16 /* 2698 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3d16Pseudo /* 2699 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3d16Pseudo_UPD /* 2700 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 \{$Vd, $dst2, $dst3\}, $Rn$Rm */ + ARM_VLD3d16_UPD /* 2701 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 \{$Vd, $dst2, $dst3\}, $Rn */ + ARM_VLD3d32 /* 2702 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3d32Pseudo /* 2703 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3d32Pseudo_UPD /* 2704 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 \{$Vd, $dst2, $dst3\}, $Rn$Rm */ + ARM_VLD3d32_UPD /* 2705 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 \{$Vd, $dst2, $dst3\}, $Rn */ + ARM_VLD3d8 /* 2706 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3d8Pseudo /* 2707 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3d8Pseudo_UPD /* 2708 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 \{$Vd, $dst2, $dst3\}, $Rn$Rm */ + ARM_VLD3d8_UPD /* 2709 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 \{$Vd, $dst2, $dst3\}, $Rn */ + ARM_VLD3q16 /* 2710 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3q16Pseudo_UPD /* 2711 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.16 \{$Vd, $dst2, $dst3\}, $Rn$Rm */ + ARM_VLD3q16_UPD /* 2712 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3q16oddPseudo /* 2713 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3q16oddPseudo_UPD /* 2714 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 \{$Vd, $dst2, $dst3\}, $Rn */ + ARM_VLD3q32 /* 2715 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3q32Pseudo_UPD /* 2716 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.32 \{$Vd, $dst2, $dst3\}, $Rn$Rm */ + ARM_VLD3q32_UPD /* 2717 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3q32oddPseudo /* 2718 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3q32oddPseudo_UPD /* 2719 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 \{$Vd, $dst2, $dst3\}, $Rn */ + ARM_VLD3q8 /* 2720 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3q8Pseudo_UPD /* 2721 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld3${p}.8 \{$Vd, $dst2, $dst3\}, $Rn$Rm */ + ARM_VLD3q8_UPD /* 2722 */, ARM_INS_VLD3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3q8oddPseudo /* 2723 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD3q8oddPseudo_UPD /* 2724 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */ + ARM_VLD4DUPd16 /* 2725 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPd16Pseudo /* 2726 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPd16Pseudo_UPD /* 2727 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */ + ARM_VLD4DUPd16_UPD /* 2728 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */ + ARM_VLD4DUPd32 /* 2729 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPd32Pseudo /* 2730 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPd32Pseudo_UPD /* 2731 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */ + ARM_VLD4DUPd32_UPD /* 2732 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */ + ARM_VLD4DUPd8 /* 2733 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPd8Pseudo /* 2734 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPd8Pseudo_UPD /* 2735 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */ + ARM_VLD4DUPd8_UPD /* 2736 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */ + ARM_VLD4DUPq16 /* 2737 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPq16EvenPseudo /* 2738 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPq16OddPseudo /* 2739 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPq16OddPseudo_UPD /* 2740 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */ + ARM_VLD4DUPq16_UPD /* 2741 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */ + ARM_VLD4DUPq32 /* 2742 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPq32EvenPseudo /* 2743 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPq32OddPseudo /* 2744 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPq32OddPseudo_UPD /* 2745 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */ + ARM_VLD4DUPq32_UPD /* 2746 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */ + ARM_VLD4DUPq8 /* 2747 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPq8EvenPseudo /* 2748 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPq8OddPseudo /* 2749 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4DUPq8OddPseudo_UPD /* 2750 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */ + ARM_VLD4DUPq8_UPD /* 2751 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */ + ARM_VLD4LNd16 /* 2752 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4LNd16Pseudo /* 2753 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4LNd16Pseudo_UPD /* 2754 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */ + ARM_VLD4LNd16_UPD /* 2755 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */ + ARM_VLD4LNd32 /* 2756 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4LNd32Pseudo /* 2757 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4LNd32Pseudo_UPD /* 2758 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */ + ARM_VLD4LNd32_UPD /* 2759 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */ + ARM_VLD4LNd8 /* 2760 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4LNd8Pseudo /* 2761 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4LNd8Pseudo_UPD /* 2762 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */ + ARM_VLD4LNd8_UPD /* 2763 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */ + ARM_VLD4LNq16 /* 2764 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4LNq16Pseudo /* 2765 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4LNq16Pseudo_UPD /* 2766 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */ + ARM_VLD4LNq16_UPD /* 2767 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */ + ARM_VLD4LNq32 /* 2768 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4LNq32Pseudo /* 2769 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4LNq32Pseudo_UPD /* 2770 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */ + ARM_VLD4LNq32_UPD /* 2771 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 \{$Vd, $dst2, $dst3, $dst4\}, $Rn */ + ARM_VLD4d16 /* 2772 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4d16Pseudo /* 2773 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4d16Pseudo_UPD /* 2774 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 \{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */ + ARM_VLD4d16_UPD /* 2775 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 \{$Vd, $dst2, $dst3, $dst4\}, $Rn */ + ARM_VLD4d32 /* 2776 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4d32Pseudo /* 2777 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4d32Pseudo_UPD /* 2778 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 \{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */ + ARM_VLD4d32_UPD /* 2779 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 \{$Vd, $dst2, $dst3, $dst4\}, $Rn */ + ARM_VLD4d8 /* 2780 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4d8Pseudo /* 2781 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4d8Pseudo_UPD /* 2782 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 \{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */ + ARM_VLD4d8_UPD /* 2783 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 \{$Vd, $dst2, $dst3, $dst4\}, $Rn */ + ARM_VLD4q16 /* 2784 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4q16Pseudo_UPD /* 2785 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.16 \{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */ + ARM_VLD4q16_UPD /* 2786 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4q16oddPseudo /* 2787 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4q16oddPseudo_UPD /* 2788 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 \{$Vd, $dst2, $dst3, $dst4\}, $Rn */ + ARM_VLD4q32 /* 2789 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4q32Pseudo_UPD /* 2790 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.32 \{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */ + ARM_VLD4q32_UPD /* 2791 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4q32oddPseudo /* 2792 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4q32oddPseudo_UPD /* 2793 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 \{$Vd, $dst2, $dst3, $dst4\}, $Rn */ + ARM_VLD4q8 /* 2794 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4q8Pseudo_UPD /* 2795 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vld4${p}.8 \{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */ + ARM_VLD4q8_UPD /* 2796 */, ARM_INS_VLD4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4q8oddPseudo /* 2797 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLD4q8oddPseudo_UPD /* 2798 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vldmdb${p} $Rn!, $regs */ + ARM_VLDMDDB_UPD /* 2799 */, ARM_INS_VLDMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vldmia${p} $Rn, $regs */ + ARM_VLDMDIA /* 2800 */, ARM_INS_VLDMIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vldmia${p} $Rn!, $regs */ + ARM_VLDMDIA_UPD /* 2801 */, ARM_INS_VLDMIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VLDMQIA /* 2802 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vldmdb${p} $Rn!, $regs */ + ARM_VLDMSDB_UPD /* 2803 */, ARM_INS_VLDMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vldmia${p} $Rn, $regs */ + ARM_VLDMSIA /* 2804 */, ARM_INS_VLDMIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vldmia${p} $Rn!, $regs */ + ARM_VLDMSIA_UPD /* 2805 */, ARM_INS_VLDMIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} $Dd, $addr */ + ARM_VLDRD /* 2806 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p}.16 $Sd, $addr */ + ARM_VLDRH /* 2807 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs16, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} $Sd, $addr */ + ARM_VLDRS /* 2808 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} fpcxtns, $addr */ + ARM_VLDR_FPCXTNS_off /* 2809 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} fpcxtns, $Rn$addr */ + ARM_VLDR_FPCXTNS_post /* 2810 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} fpcxtns, $addr! */ + ARM_VLDR_FPCXTNS_pre /* 2811 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} fpcxts, $addr */ + ARM_VLDR_FPCXTS_off /* 2812 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} fpcxts, $Rn$addr */ + ARM_VLDR_FPCXTS_post /* 2813 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} fpcxts, $addr! */ + ARM_VLDR_FPCXTS_pre /* 2814 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} fpscr_nzcvqc, $addr */ + ARM_VLDR_FPSCR_NZCVQC_off /* 2815 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} fpscr_nzcvqc, $Rn$addr */ + ARM_VLDR_FPSCR_NZCVQC_post /* 2816 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} fpscr_nzcvqc, $addr! */ + ARM_VLDR_FPSCR_NZCVQC_pre /* 2817 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} fpscr, $addr */ + ARM_VLDR_FPSCR_off /* 2818 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} fpscr, $Rn$addr */ + ARM_VLDR_FPSCR_post /* 2819 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} fpscr, $addr! */ + ARM_VLDR_FPSCR_pre /* 2820 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} p0, $addr */ + ARM_VLDR_P0_off /* 2821 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} p0, $Rn$addr */ + ARM_VLDR_P0_post /* 2822 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} p0, $addr! */ + ARM_VLDR_P0_pre /* 2823 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} vpr, $addr */ + ARM_VLDR_VPR_off /* 2824 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} vpr, $Rn$addr */ + ARM_VLDR_VPR_post /* 2825 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vldr${p} vpr, $addr! */ + ARM_VLDR_VPR_pre /* 2826 */, ARM_INS_VLDR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vlldm${p} $Rn */ + ARM_VLLDM /* 2827 */, ARM_INS_VLLDM, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_Q0, ARM_REG_Q1, ARM_REG_Q2, ARM_REG_Q3, ARM_REG_Q4, ARM_REG_Q5, ARM_REG_Q6, ARM_REG_Q7, ARM_REG_VPR, ARM_REG_FPSCR, ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasV8MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vlstm${p} $Rn */ + ARM_VLSTM /* 2828 */, ARM_INS_VLSTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.f32 $Vd, $Vn, $Vm */ + ARM_VMAXfd /* 2829 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.f32 $Vd, $Vn, $Vm */ + ARM_VMAXfq /* 2830 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.f16 $Vd, $Vn, $Vm */ + ARM_VMAXhd /* 2831 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.f16 $Vd, $Vn, $Vm */ + ARM_VMAXhq /* 2832 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.s8 $Vd, $Vn, $Vm */ + ARM_VMAXsv16i8 /* 2833 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.s32 $Vd, $Vn, $Vm */ + ARM_VMAXsv2i32 /* 2834 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.s16 $Vd, $Vn, $Vm */ + ARM_VMAXsv4i16 /* 2835 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.s32 $Vd, $Vn, $Vm */ + ARM_VMAXsv4i32 /* 2836 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.s16 $Vd, $Vn, $Vm */ + ARM_VMAXsv8i16 /* 2837 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.s8 $Vd, $Vn, $Vm */ + ARM_VMAXsv8i8 /* 2838 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.u8 $Vd, $Vn, $Vm */ + ARM_VMAXuv16i8 /* 2839 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.u32 $Vd, $Vn, $Vm */ + ARM_VMAXuv2i32 /* 2840 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.u16 $Vd, $Vn, $Vm */ + ARM_VMAXuv4i16 /* 2841 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.u32 $Vd, $Vn, $Vm */ + ARM_VMAXuv4i32 /* 2842 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.u16 $Vd, $Vn, $Vm */ + ARM_VMAXuv8i16 /* 2843 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmax${p}.u8 $Vd, $Vn, $Vm */ + ARM_VMAXuv8i8 /* 2844 */, ARM_INS_VMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.f32 $Vd, $Vn, $Vm */ + ARM_VMINfd /* 2845 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.f32 $Vd, $Vn, $Vm */ + ARM_VMINfq /* 2846 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.f16 $Vd, $Vn, $Vm */ + ARM_VMINhd /* 2847 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.f16 $Vd, $Vn, $Vm */ + ARM_VMINhq /* 2848 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.s8 $Vd, $Vn, $Vm */ + ARM_VMINsv16i8 /* 2849 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.s32 $Vd, $Vn, $Vm */ + ARM_VMINsv2i32 /* 2850 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.s16 $Vd, $Vn, $Vm */ + ARM_VMINsv4i16 /* 2851 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.s32 $Vd, $Vn, $Vm */ + ARM_VMINsv4i32 /* 2852 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.s16 $Vd, $Vn, $Vm */ + ARM_VMINsv8i16 /* 2853 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.s8 $Vd, $Vn, $Vm */ + ARM_VMINsv8i8 /* 2854 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.u8 $Vd, $Vn, $Vm */ + ARM_VMINuv16i8 /* 2855 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.u32 $Vd, $Vn, $Vm */ + ARM_VMINuv2i32 /* 2856 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.u16 $Vd, $Vn, $Vm */ + ARM_VMINuv4i16 /* 2857 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.u32 $Vd, $Vn, $Vm */ + ARM_VMINuv4i32 /* 2858 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.u16 $Vd, $Vn, $Vm */ + ARM_VMINuv8i16 /* 2859 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmin${p}.u8 $Vd, $Vn, $Vm */ + ARM_VMINuv8i8 /* 2860 */, ARM_INS_VMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.f64 $Dd, $Dn, $Dm */ + ARM_VMLAD /* 2861 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.f16 $Sd, $Sn, $Sm */ + ARM_VMLAH /* 2862 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmlal${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VMLALslsv2i32 /* 2863 */, ARM_INS_VMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlal${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VMLALslsv4i16 /* 2864 */, ARM_INS_VMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlal${p}.u32 $Vd, $Vn, $Vm$lane */ + ARM_VMLALsluv2i32 /* 2865 */, ARM_INS_VMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlal${p}.u16 $Vd, $Vn, $Vm$lane */ + ARM_VMLALsluv4i16 /* 2866 */, ARM_INS_VMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlal${p}.s32 $Vd, $Vn, $Vm */ + ARM_VMLALsv2i64 /* 2867 */, ARM_INS_VMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlal${p}.s16 $Vd, $Vn, $Vm */ + ARM_VMLALsv4i32 /* 2868 */, ARM_INS_VMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlal${p}.s8 $Vd, $Vn, $Vm */ + ARM_VMLALsv8i16 /* 2869 */, ARM_INS_VMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlal${p}.u32 $Vd, $Vn, $Vm */ + ARM_VMLALuv2i64 /* 2870 */, ARM_INS_VMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlal${p}.u16 $Vd, $Vn, $Vm */ + ARM_VMLALuv4i32 /* 2871 */, ARM_INS_VMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlal${p}.u8 $Vd, $Vn, $Vm */ + ARM_VMLALuv8i16 /* 2872 */, ARM_INS_VMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.f32 $Sd, $Sn, $Sm */ + ARM_VMLAS /* 2873 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.f32 $Vd, $Vn, $Vm */ + ARM_VMLAfd /* 2874 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.f32 $Vd, $Vn, $Vm */ + ARM_VMLAfq /* 2875 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.f16 $Vd, $Vn, $Vm */ + ARM_VMLAhd /* 2876 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.f16 $Vd, $Vn, $Vm */ + ARM_VMLAhq /* 2877 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.f32 $Vd, $Vn, $Vm$lane */ + ARM_VMLAslfd /* 2878 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.f32 $Vd, $Vn, $Vm$lane */ + ARM_VMLAslfq /* 2879 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.f16 $Vd, $Vn, $Vm$lane */ + ARM_VMLAslhd /* 2880 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.f16 $Vd, $Vn, $Vm$lane */ + ARM_VMLAslhq /* 2881 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.i32 $Vd, $Vn, $Vm$lane */ + ARM_VMLAslv2i32 /* 2882 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.i16 $Vd, $Vn, $Vm$lane */ + ARM_VMLAslv4i16 /* 2883 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.i32 $Vd, $Vn, $Vm$lane */ + ARM_VMLAslv4i32 /* 2884 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.i16 $Vd, $Vn, $Vm$lane */ + ARM_VMLAslv8i16 /* 2885 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.i8 $Vd, $Vn, $Vm */ + ARM_VMLAv16i8 /* 2886 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.i32 $Vd, $Vn, $Vm */ + ARM_VMLAv2i32 /* 2887 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.i16 $Vd, $Vn, $Vm */ + ARM_VMLAv4i16 /* 2888 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.i32 $Vd, $Vn, $Vm */ + ARM_VMLAv4i32 /* 2889 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.i16 $Vd, $Vn, $Vm */ + ARM_VMLAv8i16 /* 2890 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmla${p}.i8 $Vd, $Vn, $Vm */ + ARM_VMLAv8i8 /* 2891 */, ARM_INS_VMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.f64 $Dd, $Dn, $Dm */ + ARM_VMLSD /* 2892 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.f16 $Sd, $Sn, $Sm */ + ARM_VMLSH /* 2893 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmlsl${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VMLSLslsv2i32 /* 2894 */, ARM_INS_VMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlsl${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VMLSLslsv4i16 /* 2895 */, ARM_INS_VMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlsl${p}.u32 $Vd, $Vn, $Vm$lane */ + ARM_VMLSLsluv2i32 /* 2896 */, ARM_INS_VMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlsl${p}.u16 $Vd, $Vn, $Vm$lane */ + ARM_VMLSLsluv4i16 /* 2897 */, ARM_INS_VMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlsl${p}.s32 $Vd, $Vn, $Vm */ + ARM_VMLSLsv2i64 /* 2898 */, ARM_INS_VMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlsl${p}.s16 $Vd, $Vn, $Vm */ + ARM_VMLSLsv4i32 /* 2899 */, ARM_INS_VMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlsl${p}.s8 $Vd, $Vn, $Vm */ + ARM_VMLSLsv8i16 /* 2900 */, ARM_INS_VMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlsl${p}.u32 $Vd, $Vn, $Vm */ + ARM_VMLSLuv2i64 /* 2901 */, ARM_INS_VMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlsl${p}.u16 $Vd, $Vn, $Vm */ + ARM_VMLSLuv4i32 /* 2902 */, ARM_INS_VMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmlsl${p}.u8 $Vd, $Vn, $Vm */ + ARM_VMLSLuv8i16 /* 2903 */, ARM_INS_VMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.f32 $Sd, $Sn, $Sm */ + ARM_VMLSS /* 2904 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.f32 $Vd, $Vn, $Vm */ + ARM_VMLSfd /* 2905 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.f32 $Vd, $Vn, $Vm */ + ARM_VMLSfq /* 2906 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.f16 $Vd, $Vn, $Vm */ + ARM_VMLShd /* 2907 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.f16 $Vd, $Vn, $Vm */ + ARM_VMLShq /* 2908 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.f32 $Vd, $Vn, $Vm$lane */ + ARM_VMLSslfd /* 2909 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.f32 $Vd, $Vn, $Vm$lane */ + ARM_VMLSslfq /* 2910 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.f16 $Vd, $Vn, $Vm$lane */ + ARM_VMLSslhd /* 2911 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.f16 $Vd, $Vn, $Vm$lane */ + ARM_VMLSslhq /* 2912 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.i32 $Vd, $Vn, $Vm$lane */ + ARM_VMLSslv2i32 /* 2913 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.i16 $Vd, $Vn, $Vm$lane */ + ARM_VMLSslv4i16 /* 2914 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.i32 $Vd, $Vn, $Vm$lane */ + ARM_VMLSslv4i32 /* 2915 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.i16 $Vd, $Vn, $Vm$lane */ + ARM_VMLSslv8i16 /* 2916 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.i8 $Vd, $Vn, $Vm */ + ARM_VMLSv16i8 /* 2917 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.i32 $Vd, $Vn, $Vm */ + ARM_VMLSv2i32 /* 2918 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.i16 $Vd, $Vn, $Vm */ + ARM_VMLSv4i16 /* 2919 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.i32 $Vd, $Vn, $Vm */ + ARM_VMLSv4i32 /* 2920 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.i16 $Vd, $Vn, $Vm */ + ARM_VMLSv8i16 /* 2921 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmls${p}.i8 $Vd, $Vn, $Vm */ + ARM_VMLSv8i8 /* 2922 */, ARM_INS_VMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmmla.bf16 $Vd, $Vn, $Vm */ + ARM_VMMLA /* 2923 */, ARM_INS_VMMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.f64 $Dd, $Dm */ + ARM_VMOVD /* 2924 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs64, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p} $Dm, $Rt, $Rt2 */ + ARM_VMOVDRR /* 2925 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmovx.f16 $Sd, $Sm */ + ARM_VMOVH /* 2926 */, ARM_INS_VMOVX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.f16 $Sn, $Rt */ + ARM_VMOVHR /* 2927 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs16, 0 }, 0, 0 + #endif +}, +{ + /* vmovl${p}.s32 $Vd, $Vm */ + ARM_VMOVLsv2i64 /* 2928 */, ARM_INS_VMOVL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmovl${p}.s16 $Vd, $Vm */ + ARM_VMOVLsv4i32 /* 2929 */, ARM_INS_VMOVL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmovl${p}.s8 $Vd, $Vm */ + ARM_VMOVLsv8i16 /* 2930 */, ARM_INS_VMOVL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmovl${p}.u32 $Vd, $Vm */ + ARM_VMOVLuv2i64 /* 2931 */, ARM_INS_VMOVL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmovl${p}.u16 $Vd, $Vm */ + ARM_VMOVLuv4i32 /* 2932 */, ARM_INS_VMOVL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmovl${p}.u8 $Vd, $Vm */ + ARM_VMOVLuv8i16 /* 2933 */, ARM_INS_VMOVL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmovn${p}.i64 $Vd, $Vm */ + ARM_VMOVNv2i32 /* 2934 */, ARM_INS_VMOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmovn${p}.i32 $Vd, $Vm */ + ARM_VMOVNv4i16 /* 2935 */, ARM_INS_VMOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmovn${p}.i16 $Vd, $Vm */ + ARM_VMOVNv8i8 /* 2936 */, ARM_INS_VMOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.f16 $Rt, $Sn */ + ARM_VMOVRH /* 2937 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs16, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p} $Rt, $Rt2, $Dm */ + ARM_VMOVRRD /* 2938 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p} $Rt, $Rt2, $src1, $src2 */ + ARM_VMOVRRS /* 2939 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p} $Rt, $Sn */ + ARM_VMOVRS /* 2940 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.f32 $Sd, $Sm */ + ARM_VMOVS /* 2941 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p} $Sn, $Rt */ + ARM_VMOVSR /* 2942 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p} $dst1, $dst2, $src1, $src2 */ + ARM_VMOVSRR /* 2943 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.i8 $Vd, $SIMM */ + ARM_VMOVv16i8 /* 2944 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.i64 $Vd, $SIMM */ + ARM_VMOVv1i64 /* 2945 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.f32 $Vd, $SIMM */ + ARM_VMOVv2f32 /* 2946 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.i32 $Vd, $SIMM */ + ARM_VMOVv2i32 /* 2947 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.i64 $Vd, $SIMM */ + ARM_VMOVv2i64 /* 2948 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.f32 $Vd, $SIMM */ + ARM_VMOVv4f32 /* 2949 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.i16 $Vd, $SIMM */ + ARM_VMOVv4i16 /* 2950 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.i32 $Vd, $SIMM */ + ARM_VMOVv4i32 /* 2951 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.i16 $Vd, $SIMM */ + ARM_VMOVv8i16 /* 2952 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.i8 $Vd, $SIMM */ + ARM_VMOVv8i8 /* 2953 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, fpscr */ + ARM_VMRS /* 2954 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, fpcxtns */ + ARM_VMRS_FPCXTNS /* 2955 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, fpcxts */ + ARM_VMRS_FPCXTS /* 2956 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, fpexc */ + ARM_VMRS_FPEXC /* 2957 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, fpinst */ + ARM_VMRS_FPINST /* 2958 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, fpinst2 */ + ARM_VMRS_FPINST2 /* 2959 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, fpscr_nzcvqc */ + ARM_VMRS_FPSCR_NZCVQC /* 2960 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, fpsid */ + ARM_VMRS_FPSID /* 2961 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, mvfr0 */ + ARM_VMRS_MVFR0 /* 2962 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, mvfr1 */ + ARM_VMRS_MVFR1 /* 2963 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, mvfr2 */ + ARM_VMRS_MVFR2 /* 2964 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, p0 */ + ARM_VMRS_P0 /* 2965 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmrs${p} $Rt, vpr */ + ARM_VMRS_VPR /* 2966 */, ARM_INS_VMRS, + #ifndef CAPSTONE_DIET + { ARM_REG_VPR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmsr${p} fpscr, $Rt */ + ARM_VMSR /* 2967 */, ARM_INS_VMSR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmsr${p} fpcxtns, $Rt */ + ARM_VMSR_FPCXTNS /* 2968 */, ARM_INS_VMSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vmsr${p} fpcxts, $Rt */ + ARM_VMSR_FPCXTS /* 2969 */, ARM_INS_VMSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vmsr${p} fpexc, $Rt */ + ARM_VMSR_FPEXC /* 2970 */, ARM_INS_VMSR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmsr${p} fpinst, $Rt */ + ARM_VMSR_FPINST /* 2971 */, ARM_INS_VMSR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmsr${p} fpinst2, $Rt */ + ARM_VMSR_FPINST2 /* 2972 */, ARM_INS_VMSR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmsr${p} fpscr_nzcvqc, $Rt */ + ARM_VMSR_FPSCR_NZCVQC /* 2973 */, ARM_INS_VMSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vmsr${p} fpsid, $Rt */ + ARM_VMSR_FPSID /* 2974 */, ARM_INS_VMSR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmsr${p} p0, $Rt */ + ARM_VMSR_P0 /* 2975 */, ARM_INS_VMSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmsr${p} vpr, $Rt */ + ARM_VMSR_VPR /* 2976 */, ARM_INS_VMSR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.f64 $Dd, $Dn, $Dm */ + ARM_VMULD /* 2977 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.f16 $Sd, $Sn, $Sm */ + ARM_VMULH /* 2978 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmull.p64 $Vd, $Vn, $Vm */ + ARM_VMULLp64 /* 2979 */, ARM_INS_VMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasAES, 0 }, 0, 0 + #endif +}, +{ + /* vmull${p}.p8 $Vd, $Vn, $Vm */ + ARM_VMULLp8 /* 2980 */, ARM_INS_VMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmull${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VMULLslsv2i32 /* 2981 */, ARM_INS_VMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmull${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VMULLslsv4i16 /* 2982 */, ARM_INS_VMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmull${p}.u32 $Vd, $Vn, $Vm$lane */ + ARM_VMULLsluv2i32 /* 2983 */, ARM_INS_VMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmull${p}.u16 $Vd, $Vn, $Vm$lane */ + ARM_VMULLsluv4i16 /* 2984 */, ARM_INS_VMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmull${p}.s32 $Vd, $Vn, $Vm */ + ARM_VMULLsv2i64 /* 2985 */, ARM_INS_VMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmull${p}.s16 $Vd, $Vn, $Vm */ + ARM_VMULLsv4i32 /* 2986 */, ARM_INS_VMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmull${p}.s8 $Vd, $Vn, $Vm */ + ARM_VMULLsv8i16 /* 2987 */, ARM_INS_VMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmull${p}.u32 $Vd, $Vn, $Vm */ + ARM_VMULLuv2i64 /* 2988 */, ARM_INS_VMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmull${p}.u16 $Vd, $Vn, $Vm */ + ARM_VMULLuv4i32 /* 2989 */, ARM_INS_VMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmull${p}.u8 $Vd, $Vn, $Vm */ + ARM_VMULLuv8i16 /* 2990 */, ARM_INS_VMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.f32 $Sd, $Sn, $Sm */ + ARM_VMULS /* 2991 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.f32 $Vd, $Vn, $Vm */ + ARM_VMULfd /* 2992 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.f32 $Vd, $Vn, $Vm */ + ARM_VMULfq /* 2993 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.f16 $Vd, $Vn, $Vm */ + ARM_VMULhd /* 2994 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.f16 $Vd, $Vn, $Vm */ + ARM_VMULhq /* 2995 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.p8 $Vd, $Vn, $Vm */ + ARM_VMULpd /* 2996 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.p8 $Vd, $Vn, $Vm */ + ARM_VMULpq /* 2997 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.f32 $Vd, $Vn, $Vm$lane */ + ARM_VMULslfd /* 2998 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.f32 $Vd, $Vn, $Vm$lane */ + ARM_VMULslfq /* 2999 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.f16 $Vd, $Vn, $Vm$lane */ + ARM_VMULslhd /* 3000 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.f16 $Vd, $Vn, $Vm$lane */ + ARM_VMULslhq /* 3001 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.i32 $Vd, $Vn, $Vm$lane */ + ARM_VMULslv2i32 /* 3002 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.i16 $Vd, $Vn, $Vm$lane */ + ARM_VMULslv4i16 /* 3003 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.i32 $Vd, $Vn, $Vm$lane */ + ARM_VMULslv4i32 /* 3004 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.i16 $Vd, $Vn, $Vm$lane */ + ARM_VMULslv8i16 /* 3005 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.i8 $Vd, $Vn, $Vm */ + ARM_VMULv16i8 /* 3006 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.i32 $Vd, $Vn, $Vm */ + ARM_VMULv2i32 /* 3007 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.i16 $Vd, $Vn, $Vm */ + ARM_VMULv4i16 /* 3008 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.i32 $Vd, $Vn, $Vm */ + ARM_VMULv4i32 /* 3009 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.i16 $Vd, $Vn, $Vm */ + ARM_VMULv8i16 /* 3010 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmul${p}.i8 $Vd, $Vn, $Vm */ + ARM_VMULv8i8 /* 3011 */, ARM_INS_VMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmvn${p} $Vd, $Vm */ + ARM_VMVNd /* 3012 */, ARM_INS_VMVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmvn${p} $Vd, $Vm */ + ARM_VMVNq /* 3013 */, ARM_INS_VMVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmvn${p}.i32 $Vd, $SIMM */ + ARM_VMVNv2i32 /* 3014 */, ARM_INS_VMVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmvn${p}.i16 $Vd, $SIMM */ + ARM_VMVNv4i16 /* 3015 */, ARM_INS_VMVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmvn${p}.i32 $Vd, $SIMM */ + ARM_VMVNv4i32 /* 3016 */, ARM_INS_VMVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmvn${p}.i16 $Vd, $SIMM */ + ARM_VMVNv8i16 /* 3017 */, ARM_INS_VMVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.f64 $Dd, $Dm */ + ARM_VNEGD /* 3018 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.f16 $Sd, $Sm */ + ARM_VNEGH /* 3019 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.f32 $Sd, $Sm */ + ARM_VNEGS /* 3020 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.f32 $Vd, $Vm */ + ARM_VNEGf32q /* 3021 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.f32 $Vd, $Vm */ + ARM_VNEGfd /* 3022 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.f16 $Vd, $Vm */ + ARM_VNEGhd /* 3023 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.f16 $Vd, $Vm */ + ARM_VNEGhq /* 3024 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.s16 $Vd, $Vm */ + ARM_VNEGs16d /* 3025 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.s16 $Vd, $Vm */ + ARM_VNEGs16q /* 3026 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.s32 $Vd, $Vm */ + ARM_VNEGs32d /* 3027 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.s32 $Vd, $Vm */ + ARM_VNEGs32q /* 3028 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.s8 $Vd, $Vm */ + ARM_VNEGs8d /* 3029 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vneg${p}.s8 $Vd, $Vm */ + ARM_VNEGs8q /* 3030 */, ARM_INS_VNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vnmla${p}.f64 $Dd, $Dn, $Dm */ + ARM_VNMLAD /* 3031 */, ARM_INS_VNMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vnmla${p}.f16 $Sd, $Sn, $Sm */ + ARM_VNMLAH /* 3032 */, ARM_INS_VNMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vnmla${p}.f32 $Sd, $Sn, $Sm */ + ARM_VNMLAS /* 3033 */, ARM_INS_VNMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vnmls${p}.f64 $Dd, $Dn, $Dm */ + ARM_VNMLSD /* 3034 */, ARM_INS_VNMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vnmls${p}.f16 $Sd, $Sn, $Sm */ + ARM_VNMLSH /* 3035 */, ARM_INS_VNMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vnmls${p}.f32 $Sd, $Sn, $Sm */ + ARM_VNMLSS /* 3036 */, ARM_INS_VNMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vnmul${p}.f64 $Dd, $Dn, $Dm */ + ARM_VNMULD /* 3037 */, ARM_INS_VNMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vnmul${p}.f16 $Sd, $Sn, $Sm */ + ARM_VNMULH /* 3038 */, ARM_INS_VNMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vnmul${p}.f32 $Sd, $Sn, $Sm */ + ARM_VNMULS /* 3039 */, ARM_INS_VNMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vorn${p} $Vd, $Vn, $Vm */ + ARM_VORNd /* 3040 */, ARM_INS_VORN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vorn${p} $Vd, $Vn, $Vm */ + ARM_VORNq /* 3041 */, ARM_INS_VORN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vorr${p} $Vd, $Vn, $Vm */ + ARM_VORRd /* 3042 */, ARM_INS_VORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vorr${p}.i32 $Vd, $SIMM */ + ARM_VORRiv2i32 /* 3043 */, ARM_INS_VORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vorr${p}.i16 $Vd, $SIMM */ + ARM_VORRiv4i16 /* 3044 */, ARM_INS_VORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vorr${p}.i32 $Vd, $SIMM */ + ARM_VORRiv4i32 /* 3045 */, ARM_INS_VORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vorr${p}.i16 $Vd, $SIMM */ + ARM_VORRiv8i16 /* 3046 */, ARM_INS_VORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vorr${p} $Vd, $Vn, $Vm */ + ARM_VORRq /* 3047 */, ARM_INS_VORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadal${p}.s8 $Vd, $Vm */ + ARM_VPADALsv16i8 /* 3048 */, ARM_INS_VPADAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadal${p}.s32 $Vd, $Vm */ + ARM_VPADALsv2i32 /* 3049 */, ARM_INS_VPADAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadal${p}.s16 $Vd, $Vm */ + ARM_VPADALsv4i16 /* 3050 */, ARM_INS_VPADAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadal${p}.s32 $Vd, $Vm */ + ARM_VPADALsv4i32 /* 3051 */, ARM_INS_VPADAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadal${p}.s16 $Vd, $Vm */ + ARM_VPADALsv8i16 /* 3052 */, ARM_INS_VPADAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadal${p}.s8 $Vd, $Vm */ + ARM_VPADALsv8i8 /* 3053 */, ARM_INS_VPADAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadal${p}.u8 $Vd, $Vm */ + ARM_VPADALuv16i8 /* 3054 */, ARM_INS_VPADAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadal${p}.u32 $Vd, $Vm */ + ARM_VPADALuv2i32 /* 3055 */, ARM_INS_VPADAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadal${p}.u16 $Vd, $Vm */ + ARM_VPADALuv4i16 /* 3056 */, ARM_INS_VPADAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadal${p}.u32 $Vd, $Vm */ + ARM_VPADALuv4i32 /* 3057 */, ARM_INS_VPADAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadal${p}.u16 $Vd, $Vm */ + ARM_VPADALuv8i16 /* 3058 */, ARM_INS_VPADAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadal${p}.u8 $Vd, $Vm */ + ARM_VPADALuv8i8 /* 3059 */, ARM_INS_VPADAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpaddl${p}.s8 $Vd, $Vm */ + ARM_VPADDLsv16i8 /* 3060 */, ARM_INS_VPADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpaddl${p}.s32 $Vd, $Vm */ + ARM_VPADDLsv2i32 /* 3061 */, ARM_INS_VPADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpaddl${p}.s16 $Vd, $Vm */ + ARM_VPADDLsv4i16 /* 3062 */, ARM_INS_VPADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpaddl${p}.s32 $Vd, $Vm */ + ARM_VPADDLsv4i32 /* 3063 */, ARM_INS_VPADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpaddl${p}.s16 $Vd, $Vm */ + ARM_VPADDLsv8i16 /* 3064 */, ARM_INS_VPADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpaddl${p}.s8 $Vd, $Vm */ + ARM_VPADDLsv8i8 /* 3065 */, ARM_INS_VPADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpaddl${p}.u8 $Vd, $Vm */ + ARM_VPADDLuv16i8 /* 3066 */, ARM_INS_VPADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpaddl${p}.u32 $Vd, $Vm */ + ARM_VPADDLuv2i32 /* 3067 */, ARM_INS_VPADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpaddl${p}.u16 $Vd, $Vm */ + ARM_VPADDLuv4i16 /* 3068 */, ARM_INS_VPADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpaddl${p}.u32 $Vd, $Vm */ + ARM_VPADDLuv4i32 /* 3069 */, ARM_INS_VPADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpaddl${p}.u16 $Vd, $Vm */ + ARM_VPADDLuv8i16 /* 3070 */, ARM_INS_VPADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpaddl${p}.u8 $Vd, $Vm */ + ARM_VPADDLuv8i8 /* 3071 */, ARM_INS_VPADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadd${p}.f32 $Vd, $Vn, $Vm */ + ARM_VPADDf /* 3072 */, ARM_INS_VPADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadd${p}.f16 $Vd, $Vn, $Vm */ + ARM_VPADDh /* 3073 */, ARM_INS_VPADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vpadd${p}.i16 $Vd, $Vn, $Vm */ + ARM_VPADDi16 /* 3074 */, ARM_INS_VPADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadd${p}.i32 $Vd, $Vn, $Vm */ + ARM_VPADDi32 /* 3075 */, ARM_INS_VPADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpadd${p}.i8 $Vd, $Vn, $Vm */ + ARM_VPADDi8 /* 3076 */, ARM_INS_VPADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmax${p}.f32 $Vd, $Vn, $Vm */ + ARM_VPMAXf /* 3077 */, ARM_INS_VPMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmax${p}.f16 $Vd, $Vn, $Vm */ + ARM_VPMAXh /* 3078 */, ARM_INS_VPMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vpmax${p}.s16 $Vd, $Vn, $Vm */ + ARM_VPMAXs16 /* 3079 */, ARM_INS_VPMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmax${p}.s32 $Vd, $Vn, $Vm */ + ARM_VPMAXs32 /* 3080 */, ARM_INS_VPMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmax${p}.s8 $Vd, $Vn, $Vm */ + ARM_VPMAXs8 /* 3081 */, ARM_INS_VPMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmax${p}.u16 $Vd, $Vn, $Vm */ + ARM_VPMAXu16 /* 3082 */, ARM_INS_VPMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmax${p}.u32 $Vd, $Vn, $Vm */ + ARM_VPMAXu32 /* 3083 */, ARM_INS_VPMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmax${p}.u8 $Vd, $Vn, $Vm */ + ARM_VPMAXu8 /* 3084 */, ARM_INS_VPMAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmin${p}.f32 $Vd, $Vn, $Vm */ + ARM_VPMINf /* 3085 */, ARM_INS_VPMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmin${p}.f16 $Vd, $Vn, $Vm */ + ARM_VPMINh /* 3086 */, ARM_INS_VPMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vpmin${p}.s16 $Vd, $Vn, $Vm */ + ARM_VPMINs16 /* 3087 */, ARM_INS_VPMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmin${p}.s32 $Vd, $Vn, $Vm */ + ARM_VPMINs32 /* 3088 */, ARM_INS_VPMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmin${p}.s8 $Vd, $Vn, $Vm */ + ARM_VPMINs8 /* 3089 */, ARM_INS_VPMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmin${p}.u16 $Vd, $Vn, $Vm */ + ARM_VPMINu16 /* 3090 */, ARM_INS_VPMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmin${p}.u32 $Vd, $Vn, $Vm */ + ARM_VPMINu32 /* 3091 */, ARM_INS_VPMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vpmin${p}.u8 $Vd, $Vn, $Vm */ + ARM_VPMINu8 /* 3092 */, ARM_INS_VPMIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqabs${p}.s8 $Vd, $Vm */ + ARM_VQABSv16i8 /* 3093 */, ARM_INS_VQABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqabs${p}.s32 $Vd, $Vm */ + ARM_VQABSv2i32 /* 3094 */, ARM_INS_VQABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqabs${p}.s16 $Vd, $Vm */ + ARM_VQABSv4i16 /* 3095 */, ARM_INS_VQABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqabs${p}.s32 $Vd, $Vm */ + ARM_VQABSv4i32 /* 3096 */, ARM_INS_VQABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqabs${p}.s16 $Vd, $Vm */ + ARM_VQABSv8i16 /* 3097 */, ARM_INS_VQABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqabs${p}.s8 $Vd, $Vm */ + ARM_VQABSv8i8 /* 3098 */, ARM_INS_VQABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.s8 $Vd, $Vn, $Vm */ + ARM_VQADDsv16i8 /* 3099 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.s64 $Vd, $Vn, $Vm */ + ARM_VQADDsv1i64 /* 3100 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQADDsv2i32 /* 3101 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.s64 $Vd, $Vn, $Vm */ + ARM_VQADDsv2i64 /* 3102 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQADDsv4i16 /* 3103 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQADDsv4i32 /* 3104 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQADDsv8i16 /* 3105 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.s8 $Vd, $Vn, $Vm */ + ARM_VQADDsv8i8 /* 3106 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.u8 $Vd, $Vn, $Vm */ + ARM_VQADDuv16i8 /* 3107 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.u64 $Vd, $Vn, $Vm */ + ARM_VQADDuv1i64 /* 3108 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.u32 $Vd, $Vn, $Vm */ + ARM_VQADDuv2i32 /* 3109 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.u64 $Vd, $Vn, $Vm */ + ARM_VQADDuv2i64 /* 3110 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.u16 $Vd, $Vn, $Vm */ + ARM_VQADDuv4i16 /* 3111 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.u32 $Vd, $Vn, $Vm */ + ARM_VQADDuv4i32 /* 3112 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.u16 $Vd, $Vn, $Vm */ + ARM_VQADDuv8i16 /* 3113 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqadd${p}.u8 $Vd, $Vn, $Vm */ + ARM_VQADDuv8i8 /* 3114 */, ARM_INS_VQADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlal${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VQDMLALslv2i32 /* 3115 */, ARM_INS_VQDMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlal${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VQDMLALslv4i16 /* 3116 */, ARM_INS_VQDMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlal${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQDMLALv2i64 /* 3117 */, ARM_INS_VQDMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlal${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQDMLALv4i32 /* 3118 */, ARM_INS_VQDMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlsl${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VQDMLSLslv2i32 /* 3119 */, ARM_INS_VQDMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlsl${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VQDMLSLslv4i16 /* 3120 */, ARM_INS_VQDMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlsl${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQDMLSLv2i64 /* 3121 */, ARM_INS_VQDMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmlsl${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQDMLSLv4i32 /* 3122 */, ARM_INS_VQDMLSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VQDMULHslv2i32 /* 3123 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VQDMULHslv4i16 /* 3124 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VQDMULHslv4i32 /* 3125 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VQDMULHslv8i16 /* 3126 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQDMULHv2i32 /* 3127 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQDMULHv4i16 /* 3128 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQDMULHv4i32 /* 3129 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmulh${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQDMULHv8i16 /* 3130 */, ARM_INS_VQDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmull${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VQDMULLslv2i32 /* 3131 */, ARM_INS_VQDMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmull${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VQDMULLslv4i16 /* 3132 */, ARM_INS_VQDMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmull${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQDMULLv2i64 /* 3133 */, ARM_INS_VQDMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqdmull${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQDMULLv4i32 /* 3134 */, ARM_INS_VQDMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqmovun${p}.s64 $Vd, $Vm */ + ARM_VQMOVNsuv2i32 /* 3135 */, ARM_INS_VQMOVUN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqmovun${p}.s32 $Vd, $Vm */ + ARM_VQMOVNsuv4i16 /* 3136 */, ARM_INS_VQMOVUN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqmovun${p}.s16 $Vd, $Vm */ + ARM_VQMOVNsuv8i8 /* 3137 */, ARM_INS_VQMOVUN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqmovn${p}.s64 $Vd, $Vm */ + ARM_VQMOVNsv2i32 /* 3138 */, ARM_INS_VQMOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqmovn${p}.s32 $Vd, $Vm */ + ARM_VQMOVNsv4i16 /* 3139 */, ARM_INS_VQMOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqmovn${p}.s16 $Vd, $Vm */ + ARM_VQMOVNsv8i8 /* 3140 */, ARM_INS_VQMOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqmovn${p}.u64 $Vd, $Vm */ + ARM_VQMOVNuv2i32 /* 3141 */, ARM_INS_VQMOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqmovn${p}.u32 $Vd, $Vm */ + ARM_VQMOVNuv4i16 /* 3142 */, ARM_INS_VQMOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqmovn${p}.u16 $Vd, $Vm */ + ARM_VQMOVNuv8i8 /* 3143 */, ARM_INS_VQMOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqneg${p}.s8 $Vd, $Vm */ + ARM_VQNEGv16i8 /* 3144 */, ARM_INS_VQNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqneg${p}.s32 $Vd, $Vm */ + ARM_VQNEGv2i32 /* 3145 */, ARM_INS_VQNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqneg${p}.s16 $Vd, $Vm */ + ARM_VQNEGv4i16 /* 3146 */, ARM_INS_VQNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqneg${p}.s32 $Vd, $Vm */ + ARM_VQNEGv4i32 /* 3147 */, ARM_INS_VQNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqneg${p}.s16 $Vd, $Vm */ + ARM_VQNEGv8i16 /* 3148 */, ARM_INS_VQNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqneg${p}.s8 $Vd, $Vm */ + ARM_VQNEGv8i8 /* 3149 */, ARM_INS_VQNEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlah${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VQRDMLAHslv2i32 /* 3150 */, ARM_INS_VQRDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlah${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VQRDMLAHslv4i16 /* 3151 */, ARM_INS_VQRDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlah${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VQRDMLAHslv4i32 /* 3152 */, ARM_INS_VQRDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlah${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VQRDMLAHslv8i16 /* 3153 */, ARM_INS_VQRDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlah${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQRDMLAHv2i32 /* 3154 */, ARM_INS_VQRDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlah${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQRDMLAHv4i16 /* 3155 */, ARM_INS_VQRDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlah${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQRDMLAHv4i32 /* 3156 */, ARM_INS_VQRDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlah${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQRDMLAHv8i16 /* 3157 */, ARM_INS_VQRDMLAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsh${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VQRDMLSHslv2i32 /* 3158 */, ARM_INS_VQRDMLSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsh${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VQRDMLSHslv4i16 /* 3159 */, ARM_INS_VQRDMLSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsh${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VQRDMLSHslv4i32 /* 3160 */, ARM_INS_VQRDMLSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsh${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VQRDMLSHslv8i16 /* 3161 */, ARM_INS_VQRDMLSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsh${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQRDMLSHv2i32 /* 3162 */, ARM_INS_VQRDMLSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsh${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQRDMLSHv4i16 /* 3163 */, ARM_INS_VQRDMLSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsh${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQRDMLSHv4i32 /* 3164 */, ARM_INS_VQRDMLSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmlsh${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQRDMLSHv8i16 /* 3165 */, ARM_INS_VQRDMLSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VQRDMULHslv2i32 /* 3166 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VQRDMULHslv4i16 /* 3167 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${p}.s32 $Vd, $Vn, $Vm$lane */ + ARM_VQRDMULHslv4i32 /* 3168 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${p}.s16 $Vd, $Vn, $Vm$lane */ + ARM_VQRDMULHslv8i16 /* 3169 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQRDMULHv2i32 /* 3170 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQRDMULHv4i16 /* 3171 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQRDMULHv4i32 /* 3172 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrdmulh${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQRDMULHv8i16 /* 3173 */, ARM_INS_VQRDMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.s8 $Vd, $Vm, $Vn */ + ARM_VQRSHLsv16i8 /* 3174 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.s64 $Vd, $Vm, $Vn */ + ARM_VQRSHLsv1i64 /* 3175 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.s32 $Vd, $Vm, $Vn */ + ARM_VQRSHLsv2i32 /* 3176 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.s64 $Vd, $Vm, $Vn */ + ARM_VQRSHLsv2i64 /* 3177 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.s16 $Vd, $Vm, $Vn */ + ARM_VQRSHLsv4i16 /* 3178 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.s32 $Vd, $Vm, $Vn */ + ARM_VQRSHLsv4i32 /* 3179 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.s16 $Vd, $Vm, $Vn */ + ARM_VQRSHLsv8i16 /* 3180 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.s8 $Vd, $Vm, $Vn */ + ARM_VQRSHLsv8i8 /* 3181 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.u8 $Vd, $Vm, $Vn */ + ARM_VQRSHLuv16i8 /* 3182 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.u64 $Vd, $Vm, $Vn */ + ARM_VQRSHLuv1i64 /* 3183 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.u32 $Vd, $Vm, $Vn */ + ARM_VQRSHLuv2i32 /* 3184 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.u64 $Vd, $Vm, $Vn */ + ARM_VQRSHLuv2i64 /* 3185 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.u16 $Vd, $Vm, $Vn */ + ARM_VQRSHLuv4i16 /* 3186 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.u32 $Vd, $Vm, $Vn */ + ARM_VQRSHLuv4i32 /* 3187 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.u16 $Vd, $Vm, $Vn */ + ARM_VQRSHLuv8i16 /* 3188 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshl${p}.u8 $Vd, $Vm, $Vn */ + ARM_VQRSHLuv8i8 /* 3189 */, ARM_INS_VQRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrn${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VQRSHRNsv2i32 /* 3190 */, ARM_INS_VQRSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrn${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VQRSHRNsv4i16 /* 3191 */, ARM_INS_VQRSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrn${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VQRSHRNsv8i8 /* 3192 */, ARM_INS_VQRSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrn${p}.u64 $Vd, $Vm, $SIMM */ + ARM_VQRSHRNuv2i32 /* 3193 */, ARM_INS_VQRSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrn${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VQRSHRNuv4i16 /* 3194 */, ARM_INS_VQRSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrn${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VQRSHRNuv8i8 /* 3195 */, ARM_INS_VQRSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrun${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VQRSHRUNv2i32 /* 3196 */, ARM_INS_VQRSHRUN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrun${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VQRSHRUNv4i16 /* 3197 */, ARM_INS_VQRSHRUN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqrshrun${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VQRSHRUNv8i8 /* 3198 */, ARM_INS_VQRSHRUN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VQSHLsiv16i8 /* 3199 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VQSHLsiv1i64 /* 3200 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VQSHLsiv2i32 /* 3201 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VQSHLsiv2i64 /* 3202 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VQSHLsiv4i16 /* 3203 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VQSHLsiv4i32 /* 3204 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VQSHLsiv8i16 /* 3205 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VQSHLsiv8i8 /* 3206 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshlu${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VQSHLsuv16i8 /* 3207 */, ARM_INS_VQSHLU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshlu${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VQSHLsuv1i64 /* 3208 */, ARM_INS_VQSHLU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshlu${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VQSHLsuv2i32 /* 3209 */, ARM_INS_VQSHLU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshlu${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VQSHLsuv2i64 /* 3210 */, ARM_INS_VQSHLU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshlu${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VQSHLsuv4i16 /* 3211 */, ARM_INS_VQSHLU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshlu${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VQSHLsuv4i32 /* 3212 */, ARM_INS_VQSHLU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshlu${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VQSHLsuv8i16 /* 3213 */, ARM_INS_VQSHLU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshlu${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VQSHLsuv8i8 /* 3214 */, ARM_INS_VQSHLU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s8 $Vd, $Vm, $Vn */ + ARM_VQSHLsv16i8 /* 3215 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s64 $Vd, $Vm, $Vn */ + ARM_VQSHLsv1i64 /* 3216 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s32 $Vd, $Vm, $Vn */ + ARM_VQSHLsv2i32 /* 3217 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s64 $Vd, $Vm, $Vn */ + ARM_VQSHLsv2i64 /* 3218 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s16 $Vd, $Vm, $Vn */ + ARM_VQSHLsv4i16 /* 3219 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s32 $Vd, $Vm, $Vn */ + ARM_VQSHLsv4i32 /* 3220 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s16 $Vd, $Vm, $Vn */ + ARM_VQSHLsv8i16 /* 3221 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.s8 $Vd, $Vm, $Vn */ + ARM_VQSHLsv8i8 /* 3222 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u8 $Vd, $Vm, $SIMM */ + ARM_VQSHLuiv16i8 /* 3223 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u64 $Vd, $Vm, $SIMM */ + ARM_VQSHLuiv1i64 /* 3224 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VQSHLuiv2i32 /* 3225 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u64 $Vd, $Vm, $SIMM */ + ARM_VQSHLuiv2i64 /* 3226 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VQSHLuiv4i16 /* 3227 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VQSHLuiv4i32 /* 3228 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VQSHLuiv8i16 /* 3229 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u8 $Vd, $Vm, $SIMM */ + ARM_VQSHLuiv8i8 /* 3230 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u8 $Vd, $Vm, $Vn */ + ARM_VQSHLuv16i8 /* 3231 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u64 $Vd, $Vm, $Vn */ + ARM_VQSHLuv1i64 /* 3232 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u32 $Vd, $Vm, $Vn */ + ARM_VQSHLuv2i32 /* 3233 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u64 $Vd, $Vm, $Vn */ + ARM_VQSHLuv2i64 /* 3234 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u16 $Vd, $Vm, $Vn */ + ARM_VQSHLuv4i16 /* 3235 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u32 $Vd, $Vm, $Vn */ + ARM_VQSHLuv4i32 /* 3236 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u16 $Vd, $Vm, $Vn */ + ARM_VQSHLuv8i16 /* 3237 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshl${p}.u8 $Vd, $Vm, $Vn */ + ARM_VQSHLuv8i8 /* 3238 */, ARM_INS_VQSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshrn${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VQSHRNsv2i32 /* 3239 */, ARM_INS_VQSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshrn${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VQSHRNsv4i16 /* 3240 */, ARM_INS_VQSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshrn${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VQSHRNsv8i8 /* 3241 */, ARM_INS_VQSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshrn${p}.u64 $Vd, $Vm, $SIMM */ + ARM_VQSHRNuv2i32 /* 3242 */, ARM_INS_VQSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshrn${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VQSHRNuv4i16 /* 3243 */, ARM_INS_VQSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshrn${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VQSHRNuv8i8 /* 3244 */, ARM_INS_VQSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshrun${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VQSHRUNv2i32 /* 3245 */, ARM_INS_VQSHRUN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshrun${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VQSHRUNv4i16 /* 3246 */, ARM_INS_VQSHRUN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqshrun${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VQSHRUNv8i8 /* 3247 */, ARM_INS_VQSHRUN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.s8 $Vd, $Vn, $Vm */ + ARM_VQSUBsv16i8 /* 3248 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.s64 $Vd, $Vn, $Vm */ + ARM_VQSUBsv1i64 /* 3249 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQSUBsv2i32 /* 3250 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.s64 $Vd, $Vn, $Vm */ + ARM_VQSUBsv2i64 /* 3251 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQSUBsv4i16 /* 3252 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.s32 $Vd, $Vn, $Vm */ + ARM_VQSUBsv4i32 /* 3253 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.s16 $Vd, $Vn, $Vm */ + ARM_VQSUBsv8i16 /* 3254 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.s8 $Vd, $Vn, $Vm */ + ARM_VQSUBsv8i8 /* 3255 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.u8 $Vd, $Vn, $Vm */ + ARM_VQSUBuv16i8 /* 3256 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.u64 $Vd, $Vn, $Vm */ + ARM_VQSUBuv1i64 /* 3257 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.u32 $Vd, $Vn, $Vm */ + ARM_VQSUBuv2i32 /* 3258 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.u64 $Vd, $Vn, $Vm */ + ARM_VQSUBuv2i64 /* 3259 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.u16 $Vd, $Vn, $Vm */ + ARM_VQSUBuv4i16 /* 3260 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.u32 $Vd, $Vn, $Vm */ + ARM_VQSUBuv4i32 /* 3261 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.u16 $Vd, $Vn, $Vm */ + ARM_VQSUBuv8i16 /* 3262 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vqsub${p}.u8 $Vd, $Vn, $Vm */ + ARM_VQSUBuv8i8 /* 3263 */, ARM_INS_VQSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vraddhn${p}.i64 $Vd, $Vn, $Vm */ + ARM_VRADDHNv2i32 /* 3264 */, ARM_INS_VRADDHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vraddhn${p}.i32 $Vd, $Vn, $Vm */ + ARM_VRADDHNv4i16 /* 3265 */, ARM_INS_VRADDHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vraddhn${p}.i16 $Vd, $Vn, $Vm */ + ARM_VRADDHNv8i8 /* 3266 */, ARM_INS_VRADDHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrecpe${p}.u32 $Vd, $Vm */ + ARM_VRECPEd /* 3267 */, ARM_INS_VRECPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrecpe${p}.f32 $Vd, $Vm */ + ARM_VRECPEfd /* 3268 */, ARM_INS_VRECPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrecpe${p}.f32 $Vd, $Vm */ + ARM_VRECPEfq /* 3269 */, ARM_INS_VRECPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrecpe${p}.f16 $Vd, $Vm */ + ARM_VRECPEhd /* 3270 */, ARM_INS_VRECPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrecpe${p}.f16 $Vd, $Vm */ + ARM_VRECPEhq /* 3271 */, ARM_INS_VRECPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrecpe${p}.u32 $Vd, $Vm */ + ARM_VRECPEq /* 3272 */, ARM_INS_VRECPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrecps${p}.f32 $Vd, $Vn, $Vm */ + ARM_VRECPSfd /* 3273 */, ARM_INS_VRECPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrecps${p}.f32 $Vd, $Vn, $Vm */ + ARM_VRECPSfq /* 3274 */, ARM_INS_VRECPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrecps${p}.f16 $Vd, $Vn, $Vm */ + ARM_VRECPShd /* 3275 */, ARM_INS_VRECPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrecps${p}.f16 $Vd, $Vn, $Vm */ + ARM_VRECPShq /* 3276 */, ARM_INS_VRECPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrev16${p}.8 $Vd, $Vm */ + ARM_VREV16d8 /* 3277 */, ARM_INS_VREV16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrev16${p}.8 $Vd, $Vm */ + ARM_VREV16q8 /* 3278 */, ARM_INS_VREV16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrev32${p}.16 $Vd, $Vm */ + ARM_VREV32d16 /* 3279 */, ARM_INS_VREV32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrev32${p}.8 $Vd, $Vm */ + ARM_VREV32d8 /* 3280 */, ARM_INS_VREV32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrev32${p}.16 $Vd, $Vm */ + ARM_VREV32q16 /* 3281 */, ARM_INS_VREV32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrev32${p}.8 $Vd, $Vm */ + ARM_VREV32q8 /* 3282 */, ARM_INS_VREV32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrev64${p}.16 $Vd, $Vm */ + ARM_VREV64d16 /* 3283 */, ARM_INS_VREV64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrev64${p}.32 $Vd, $Vm */ + ARM_VREV64d32 /* 3284 */, ARM_INS_VREV64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrev64${p}.8 $Vd, $Vm */ + ARM_VREV64d8 /* 3285 */, ARM_INS_VREV64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrev64${p}.16 $Vd, $Vm */ + ARM_VREV64q16 /* 3286 */, ARM_INS_VREV64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrev64${p}.32 $Vd, $Vm */ + ARM_VREV64q32 /* 3287 */, ARM_INS_VREV64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrev64${p}.8 $Vd, $Vm */ + ARM_VREV64q8 /* 3288 */, ARM_INS_VREV64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${p}.s8 $Vd, $Vn, $Vm */ + ARM_VRHADDsv16i8 /* 3289 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${p}.s32 $Vd, $Vn, $Vm */ + ARM_VRHADDsv2i32 /* 3290 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${p}.s16 $Vd, $Vn, $Vm */ + ARM_VRHADDsv4i16 /* 3291 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${p}.s32 $Vd, $Vn, $Vm */ + ARM_VRHADDsv4i32 /* 3292 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${p}.s16 $Vd, $Vn, $Vm */ + ARM_VRHADDsv8i16 /* 3293 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${p}.s8 $Vd, $Vn, $Vm */ + ARM_VRHADDsv8i8 /* 3294 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${p}.u8 $Vd, $Vn, $Vm */ + ARM_VRHADDuv16i8 /* 3295 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${p}.u32 $Vd, $Vn, $Vm */ + ARM_VRHADDuv2i32 /* 3296 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${p}.u16 $Vd, $Vn, $Vm */ + ARM_VRHADDuv4i16 /* 3297 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${p}.u32 $Vd, $Vn, $Vm */ + ARM_VRHADDuv4i32 /* 3298 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${p}.u16 $Vd, $Vn, $Vm */ + ARM_VRHADDuv8i16 /* 3299 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrhadd${p}.u8 $Vd, $Vn, $Vm */ + ARM_VRHADDuv8i8 /* 3300 */, ARM_INS_VRHADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrinta.f64 $Dd, $Dm */ + ARM_VRINTAD /* 3301 */, ARM_INS_VRINTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vrinta.f16 $Sd, $Sm */ + ARM_VRINTAH /* 3302 */, ARM_INS_VRINTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrinta.f32 $Vd, $Vm */ + ARM_VRINTANDf /* 3303 */, ARM_INS_VRINTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrinta.f16 $Vd, $Vm */ + ARM_VRINTANDh /* 3304 */, ARM_INS_VRINTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrinta.f32 $Vd, $Vm */ + ARM_VRINTANQf /* 3305 */, ARM_INS_VRINTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrinta.f16 $Vd, $Vm */ + ARM_VRINTANQh /* 3306 */, ARM_INS_VRINTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrinta.f32 $Sd, $Sm */ + ARM_VRINTAS /* 3307 */, ARM_INS_VRINTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vrintm.f64 $Dd, $Dm */ + ARM_VRINTMD /* 3308 */, ARM_INS_VRINTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vrintm.f16 $Sd, $Sm */ + ARM_VRINTMH /* 3309 */, ARM_INS_VRINTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintm.f32 $Vd, $Vm */ + ARM_VRINTMNDf /* 3310 */, ARM_INS_VRINTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrintm.f16 $Vd, $Vm */ + ARM_VRINTMNDh /* 3311 */, ARM_INS_VRINTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintm.f32 $Vd, $Vm */ + ARM_VRINTMNQf /* 3312 */, ARM_INS_VRINTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrintm.f16 $Vd, $Vm */ + ARM_VRINTMNQh /* 3313 */, ARM_INS_VRINTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintm.f32 $Sd, $Sm */ + ARM_VRINTMS /* 3314 */, ARM_INS_VRINTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vrintn.f64 $Dd, $Dm */ + ARM_VRINTND /* 3315 */, ARM_INS_VRINTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vrintn.f16 $Sd, $Sm */ + ARM_VRINTNH /* 3316 */, ARM_INS_VRINTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintn.f32 $Vd, $Vm */ + ARM_VRINTNNDf /* 3317 */, ARM_INS_VRINTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrintn.f16 $Vd, $Vm */ + ARM_VRINTNNDh /* 3318 */, ARM_INS_VRINTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintn.f32 $Vd, $Vm */ + ARM_VRINTNNQf /* 3319 */, ARM_INS_VRINTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrintn.f16 $Vd, $Vm */ + ARM_VRINTNNQh /* 3320 */, ARM_INS_VRINTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintn.f32 $Sd, $Sm */ + ARM_VRINTNS /* 3321 */, ARM_INS_VRINTN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vrintp.f64 $Dd, $Dm */ + ARM_VRINTPD /* 3322 */, ARM_INS_VRINTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vrintp.f16 $Sd, $Sm */ + ARM_VRINTPH /* 3323 */, ARM_INS_VRINTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintp.f32 $Vd, $Vm */ + ARM_VRINTPNDf /* 3324 */, ARM_INS_VRINTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrintp.f16 $Vd, $Vm */ + ARM_VRINTPNDh /* 3325 */, ARM_INS_VRINTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintp.f32 $Vd, $Vm */ + ARM_VRINTPNQf /* 3326 */, ARM_INS_VRINTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrintp.f16 $Vd, $Vm */ + ARM_VRINTPNQh /* 3327 */, ARM_INS_VRINTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintp.f32 $Sd, $Sm */ + ARM_VRINTPS /* 3328 */, ARM_INS_VRINTP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vrintr${p}.f64 $Dd, $Dm */ + ARM_VRINTRD /* 3329 */, ARM_INS_VRINTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vrintr${p}.f16 $Sd, $Sm */ + ARM_VRINTRH /* 3330 */, ARM_INS_VRINTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintr${p}.f32 $Sd, $Sm */ + ARM_VRINTRS /* 3331 */, ARM_INS_VRINTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vrintx${p}.f64 $Dd, $Dm */ + ARM_VRINTXD /* 3332 */, ARM_INS_VRINTX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vrintx${p}.f16 $Sd, $Sm */ + ARM_VRINTXH /* 3333 */, ARM_INS_VRINTX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintx.f32 $Vd, $Vm */ + ARM_VRINTXNDf /* 3334 */, ARM_INS_VRINTX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrintx.f16 $Vd, $Vm */ + ARM_VRINTXNDh /* 3335 */, ARM_INS_VRINTX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintx.f32 $Vd, $Vm */ + ARM_VRINTXNQf /* 3336 */, ARM_INS_VRINTX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrintx.f16 $Vd, $Vm */ + ARM_VRINTXNQh /* 3337 */, ARM_INS_VRINTX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintx${p}.f32 $Sd, $Sm */ + ARM_VRINTXS /* 3338 */, ARM_INS_VRINTX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vrintz${p}.f64 $Dd, $Dm */ + ARM_VRINTZD /* 3339 */, ARM_INS_VRINTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vrintz${p}.f16 $Sd, $Sm */ + ARM_VRINTZH /* 3340 */, ARM_INS_VRINTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintz.f32 $Vd, $Vm */ + ARM_VRINTZNDf /* 3341 */, ARM_INS_VRINTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrintz.f16 $Vd, $Vm */ + ARM_VRINTZNDh /* 3342 */, ARM_INS_VRINTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintz.f32 $Vd, $Vm */ + ARM_VRINTZNQf /* 3343 */, ARM_INS_VRINTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrintz.f16 $Vd, $Vm */ + ARM_VRINTZNQh /* 3344 */, ARM_INS_VRINTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrintz${p}.f32 $Sd, $Sm */ + ARM_VRINTZS /* 3345 */, ARM_INS_VRINTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.s8 $Vd, $Vm, $Vn */ + ARM_VRSHLsv16i8 /* 3346 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.s64 $Vd, $Vm, $Vn */ + ARM_VRSHLsv1i64 /* 3347 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.s32 $Vd, $Vm, $Vn */ + ARM_VRSHLsv2i32 /* 3348 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.s64 $Vd, $Vm, $Vn */ + ARM_VRSHLsv2i64 /* 3349 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.s16 $Vd, $Vm, $Vn */ + ARM_VRSHLsv4i16 /* 3350 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.s32 $Vd, $Vm, $Vn */ + ARM_VRSHLsv4i32 /* 3351 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.s16 $Vd, $Vm, $Vn */ + ARM_VRSHLsv8i16 /* 3352 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.s8 $Vd, $Vm, $Vn */ + ARM_VRSHLsv8i8 /* 3353 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.u8 $Vd, $Vm, $Vn */ + ARM_VRSHLuv16i8 /* 3354 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.u64 $Vd, $Vm, $Vn */ + ARM_VRSHLuv1i64 /* 3355 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.u32 $Vd, $Vm, $Vn */ + ARM_VRSHLuv2i32 /* 3356 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.u64 $Vd, $Vm, $Vn */ + ARM_VRSHLuv2i64 /* 3357 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.u16 $Vd, $Vm, $Vn */ + ARM_VRSHLuv4i16 /* 3358 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.u32 $Vd, $Vm, $Vn */ + ARM_VRSHLuv4i32 /* 3359 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.u16 $Vd, $Vm, $Vn */ + ARM_VRSHLuv8i16 /* 3360 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshl${p}.u8 $Vd, $Vm, $Vn */ + ARM_VRSHLuv8i8 /* 3361 */, ARM_INS_VRSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshrn${p}.i64 $Vd, $Vm, $SIMM */ + ARM_VRSHRNv2i32 /* 3362 */, ARM_INS_VRSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshrn${p}.i32 $Vd, $Vm, $SIMM */ + ARM_VRSHRNv4i16 /* 3363 */, ARM_INS_VRSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshrn${p}.i16 $Vd, $Vm, $SIMM */ + ARM_VRSHRNv8i8 /* 3364 */, ARM_INS_VRSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VRSHRsv16i8 /* 3365 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VRSHRsv1i64 /* 3366 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VRSHRsv2i32 /* 3367 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VRSHRsv2i64 /* 3368 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VRSHRsv4i16 /* 3369 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VRSHRsv4i32 /* 3370 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VRSHRsv8i16 /* 3371 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VRSHRsv8i8 /* 3372 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.u8 $Vd, $Vm, $SIMM */ + ARM_VRSHRuv16i8 /* 3373 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.u64 $Vd, $Vm, $SIMM */ + ARM_VRSHRuv1i64 /* 3374 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VRSHRuv2i32 /* 3375 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.u64 $Vd, $Vm, $SIMM */ + ARM_VRSHRuv2i64 /* 3376 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VRSHRuv4i16 /* 3377 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VRSHRuv4i32 /* 3378 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VRSHRuv8i16 /* 3379 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrshr${p}.u8 $Vd, $Vm, $SIMM */ + ARM_VRSHRuv8i8 /* 3380 */, ARM_INS_VRSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsqrte${p}.u32 $Vd, $Vm */ + ARM_VRSQRTEd /* 3381 */, ARM_INS_VRSQRTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsqrte${p}.f32 $Vd, $Vm */ + ARM_VRSQRTEfd /* 3382 */, ARM_INS_VRSQRTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsqrte${p}.f32 $Vd, $Vm */ + ARM_VRSQRTEfq /* 3383 */, ARM_INS_VRSQRTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsqrte${p}.f16 $Vd, $Vm */ + ARM_VRSQRTEhd /* 3384 */, ARM_INS_VRSQRTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrsqrte${p}.f16 $Vd, $Vm */ + ARM_VRSQRTEhq /* 3385 */, ARM_INS_VRSQRTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrsqrte${p}.u32 $Vd, $Vm */ + ARM_VRSQRTEq /* 3386 */, ARM_INS_VRSQRTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsqrts${p}.f32 $Vd, $Vn, $Vm */ + ARM_VRSQRTSfd /* 3387 */, ARM_INS_VRSQRTS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsqrts${p}.f32 $Vd, $Vn, $Vm */ + ARM_VRSQRTSfq /* 3388 */, ARM_INS_VRSQRTS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsqrts${p}.f16 $Vd, $Vn, $Vm */ + ARM_VRSQRTShd /* 3389 */, ARM_INS_VRSQRTS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrsqrts${p}.f16 $Vd, $Vn, $Vm */ + ARM_VRSQRTShq /* 3390 */, ARM_INS_VRSQRTS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VRSRAsv16i8 /* 3391 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VRSRAsv1i64 /* 3392 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VRSRAsv2i32 /* 3393 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VRSRAsv2i64 /* 3394 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VRSRAsv4i16 /* 3395 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VRSRAsv4i32 /* 3396 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VRSRAsv8i16 /* 3397 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VRSRAsv8i8 /* 3398 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.u8 $Vd, $Vm, $SIMM */ + ARM_VRSRAuv16i8 /* 3399 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.u64 $Vd, $Vm, $SIMM */ + ARM_VRSRAuv1i64 /* 3400 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VRSRAuv2i32 /* 3401 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.u64 $Vd, $Vm, $SIMM */ + ARM_VRSRAuv2i64 /* 3402 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VRSRAuv4i16 /* 3403 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VRSRAuv4i32 /* 3404 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VRSRAuv8i16 /* 3405 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsra${p}.u8 $Vd, $Vm, $SIMM */ + ARM_VRSRAuv8i8 /* 3406 */, ARM_INS_VRSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsubhn${p}.i64 $Vd, $Vn, $Vm */ + ARM_VRSUBHNv2i32 /* 3407 */, ARM_INS_VRSUBHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsubhn${p}.i32 $Vd, $Vn, $Vm */ + ARM_VRSUBHNv4i16 /* 3408 */, ARM_INS_VRSUBHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vrsubhn${p}.i16 $Vd, $Vn, $Vm */ + ARM_VRSUBHNv8i8 /* 3409 */, ARM_INS_VRSUBHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vscclrm{$p} $regs */ + ARM_VSCCLRMD /* 3410 */, ARM_INS_VSCCLRM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vscclrm{$p} $regs */ + ARM_VSCCLRMS /* 3411 */, ARM_INS_VSCCLRM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vsdot.s8 $Vd, $Vn, $Vm */ + ARM_VSDOTD /* 3412 */, ARM_INS_VSDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0 + #endif +}, +{ + /* vsdot.s8 $Vd, $Vn, $Vm$lane */ + ARM_VSDOTDI /* 3413 */, ARM_INS_VSDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0 + #endif +}, +{ + /* vsdot.s8 $Vd, $Vn, $Vm */ + ARM_VSDOTQ /* 3414 */, ARM_INS_VSDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0 + #endif +}, +{ + /* vsdot.s8 $Vd, $Vn, $Vm$lane */ + ARM_VSDOTQI /* 3415 */, ARM_INS_VSDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0 + #endif +}, +{ + /* vseleq.f64 $Dd, $Dn, $Dm */ + ARM_VSELEQD /* 3416 */, ARM_INS_VSELEQ, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vseleq.f16 $Sd, $Sn, $Sm */ + ARM_VSELEQH /* 3417 */, ARM_INS_VSELEQ, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vseleq.f32 $Sd, $Sn, $Sm */ + ARM_VSELEQS /* 3418 */, ARM_INS_VSELEQ, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vselge.f64 $Dd, $Dn, $Dm */ + ARM_VSELGED /* 3419 */, ARM_INS_VSELGE, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vselge.f16 $Sd, $Sn, $Sm */ + ARM_VSELGEH /* 3420 */, ARM_INS_VSELGE, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vselge.f32 $Sd, $Sn, $Sm */ + ARM_VSELGES /* 3421 */, ARM_INS_VSELGE, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vselgt.f64 $Dd, $Dn, $Dm */ + ARM_VSELGTD /* 3422 */, ARM_INS_VSELGT, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vselgt.f16 $Sd, $Sn, $Sm */ + ARM_VSELGTH /* 3423 */, ARM_INS_VSELGT, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vselgt.f32 $Sd, $Sn, $Sm */ + ARM_VSELGTS /* 3424 */, ARM_INS_VSELGT, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vselvs.f64 $Dd, $Dn, $Dm */ + ARM_VSELVSD /* 3425 */, ARM_INS_VSELVS, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vselvs.f16 $Sd, $Sn, $Sm */ + ARM_VSELVSH /* 3426 */, ARM_INS_VSELVS, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vselvs.f32 $Sd, $Sn, $Sm */ + ARM_VSELVSS /* 3427 */, ARM_INS_VSELVS, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.16 $V$lane, $R */ + ARM_VSETLNi16 /* 3428 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.32 $V$lane, $R */ + ARM_VSETLNi32 /* 3429 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vmov${p}.8 $V$lane, $R */ + ARM_VSETLNi8 /* 3430 */, ARM_INS_VMOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshll${p}.i16 $Vd, $Vm, $SIMM */ + ARM_VSHLLi16 /* 3431 */, ARM_INS_VSHLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshll${p}.i32 $Vd, $Vm, $SIMM */ + ARM_VSHLLi32 /* 3432 */, ARM_INS_VSHLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshll${p}.i8 $Vd, $Vm, $SIMM */ + ARM_VSHLLi8 /* 3433 */, ARM_INS_VSHLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshll${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VSHLLsv2i64 /* 3434 */, ARM_INS_VSHLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshll${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VSHLLsv4i32 /* 3435 */, ARM_INS_VSHLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshll${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VSHLLsv8i16 /* 3436 */, ARM_INS_VSHLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshll${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VSHLLuv2i64 /* 3437 */, ARM_INS_VSHLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshll${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VSHLLuv4i32 /* 3438 */, ARM_INS_VSHLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshll${p}.u8 $Vd, $Vm, $SIMM */ + ARM_VSHLLuv8i16 /* 3439 */, ARM_INS_VSHLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.i8 $Vd, $Vm, $SIMM */ + ARM_VSHLiv16i8 /* 3440 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.i64 $Vd, $Vm, $SIMM */ + ARM_VSHLiv1i64 /* 3441 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.i32 $Vd, $Vm, $SIMM */ + ARM_VSHLiv2i32 /* 3442 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.i64 $Vd, $Vm, $SIMM */ + ARM_VSHLiv2i64 /* 3443 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.i16 $Vd, $Vm, $SIMM */ + ARM_VSHLiv4i16 /* 3444 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.i32 $Vd, $Vm, $SIMM */ + ARM_VSHLiv4i32 /* 3445 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.i16 $Vd, $Vm, $SIMM */ + ARM_VSHLiv8i16 /* 3446 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.i8 $Vd, $Vm, $SIMM */ + ARM_VSHLiv8i8 /* 3447 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.s8 $Vd, $Vm, $Vn */ + ARM_VSHLsv16i8 /* 3448 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.s64 $Vd, $Vm, $Vn */ + ARM_VSHLsv1i64 /* 3449 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.s32 $Vd, $Vm, $Vn */ + ARM_VSHLsv2i32 /* 3450 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.s64 $Vd, $Vm, $Vn */ + ARM_VSHLsv2i64 /* 3451 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.s16 $Vd, $Vm, $Vn */ + ARM_VSHLsv4i16 /* 3452 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.s32 $Vd, $Vm, $Vn */ + ARM_VSHLsv4i32 /* 3453 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.s16 $Vd, $Vm, $Vn */ + ARM_VSHLsv8i16 /* 3454 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.s8 $Vd, $Vm, $Vn */ + ARM_VSHLsv8i8 /* 3455 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.u8 $Vd, $Vm, $Vn */ + ARM_VSHLuv16i8 /* 3456 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.u64 $Vd, $Vm, $Vn */ + ARM_VSHLuv1i64 /* 3457 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.u32 $Vd, $Vm, $Vn */ + ARM_VSHLuv2i32 /* 3458 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.u64 $Vd, $Vm, $Vn */ + ARM_VSHLuv2i64 /* 3459 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.u16 $Vd, $Vm, $Vn */ + ARM_VSHLuv4i16 /* 3460 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.u32 $Vd, $Vm, $Vn */ + ARM_VSHLuv4i32 /* 3461 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.u16 $Vd, $Vm, $Vn */ + ARM_VSHLuv8i16 /* 3462 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshl${p}.u8 $Vd, $Vm, $Vn */ + ARM_VSHLuv8i8 /* 3463 */, ARM_INS_VSHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshrn${p}.i64 $Vd, $Vm, $SIMM */ + ARM_VSHRNv2i32 /* 3464 */, ARM_INS_VSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshrn${p}.i32 $Vd, $Vm, $SIMM */ + ARM_VSHRNv4i16 /* 3465 */, ARM_INS_VSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshrn${p}.i16 $Vd, $Vm, $SIMM */ + ARM_VSHRNv8i8 /* 3466 */, ARM_INS_VSHRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VSHRsv16i8 /* 3467 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VSHRsv1i64 /* 3468 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VSHRsv2i32 /* 3469 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VSHRsv2i64 /* 3470 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VSHRsv4i16 /* 3471 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VSHRsv4i32 /* 3472 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VSHRsv8i16 /* 3473 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VSHRsv8i8 /* 3474 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.u8 $Vd, $Vm, $SIMM */ + ARM_VSHRuv16i8 /* 3475 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.u64 $Vd, $Vm, $SIMM */ + ARM_VSHRuv1i64 /* 3476 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VSHRuv2i32 /* 3477 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.u64 $Vd, $Vm, $SIMM */ + ARM_VSHRuv2i64 /* 3478 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VSHRuv4i16 /* 3479 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VSHRuv4i32 /* 3480 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VSHRuv8i16 /* 3481 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vshr${p}.u8 $Vd, $Vm, $SIMM */ + ARM_VSHRuv8i8 /* 3482 */, ARM_INS_VSHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f64.s16 $dst, $a, $fbits */ + ARM_VSHTOD /* 3483 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.s16 $dst, $a, $fbits */ + ARM_VSHTOH /* 3484 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.s16 $dst, $a, $fbits */ + ARM_VSHTOS /* 3485 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f64.s32 $Dd, $Sm */ + ARM_VSITOD /* 3486 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.s32 $Sd, $Sm */ + ARM_VSITOH /* 3487 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.s32 $Sd, $Sm */ + ARM_VSITOS /* 3488 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vsli${p}.8 $Vd, $Vm, $SIMM */ + ARM_VSLIv16i8 /* 3489 */, ARM_INS_VSLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsli${p}.64 $Vd, $Vm, $SIMM */ + ARM_VSLIv1i64 /* 3490 */, ARM_INS_VSLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsli${p}.32 $Vd, $Vm, $SIMM */ + ARM_VSLIv2i32 /* 3491 */, ARM_INS_VSLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsli${p}.64 $Vd, $Vm, $SIMM */ + ARM_VSLIv2i64 /* 3492 */, ARM_INS_VSLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsli${p}.16 $Vd, $Vm, $SIMM */ + ARM_VSLIv4i16 /* 3493 */, ARM_INS_VSLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsli${p}.32 $Vd, $Vm, $SIMM */ + ARM_VSLIv4i32 /* 3494 */, ARM_INS_VSLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsli${p}.16 $Vd, $Vm, $SIMM */ + ARM_VSLIv8i16 /* 3495 */, ARM_INS_VSLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsli${p}.8 $Vd, $Vm, $SIMM */ + ARM_VSLIv8i8 /* 3496 */, ARM_INS_VSLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f64.s32 $dst, $a, $fbits */ + ARM_VSLTOD /* 3497 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.s32 $dst, $a, $fbits */ + ARM_VSLTOH /* 3498 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.s32 $dst, $a, $fbits */ + ARM_VSLTOS /* 3499 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vsmmla.s8 $Vd, $Vn, $Vm */ + ARM_VSMMLA /* 3500 */, ARM_INS_VSMMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0 + #endif +}, +{ + /* vsqrt${p}.f64 $Dd, $Dm */ + ARM_VSQRTD /* 3501 */, ARM_INS_VSQRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vsqrt${p}.f16 $Sd, $Sm */ + ARM_VSQRTH /* 3502 */, ARM_INS_VSQRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vsqrt${p}.f32 $Sd, $Sm */ + ARM_VSQRTS /* 3503 */, ARM_INS_VSQRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VSRAsv16i8 /* 3504 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VSRAsv1i64 /* 3505 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VSRAsv2i32 /* 3506 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.s64 $Vd, $Vm, $SIMM */ + ARM_VSRAsv2i64 /* 3507 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VSRAsv4i16 /* 3508 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.s32 $Vd, $Vm, $SIMM */ + ARM_VSRAsv4i32 /* 3509 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.s16 $Vd, $Vm, $SIMM */ + ARM_VSRAsv8i16 /* 3510 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.s8 $Vd, $Vm, $SIMM */ + ARM_VSRAsv8i8 /* 3511 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.u8 $Vd, $Vm, $SIMM */ + ARM_VSRAuv16i8 /* 3512 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.u64 $Vd, $Vm, $SIMM */ + ARM_VSRAuv1i64 /* 3513 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VSRAuv2i32 /* 3514 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.u64 $Vd, $Vm, $SIMM */ + ARM_VSRAuv2i64 /* 3515 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VSRAuv4i16 /* 3516 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.u32 $Vd, $Vm, $SIMM */ + ARM_VSRAuv4i32 /* 3517 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.u16 $Vd, $Vm, $SIMM */ + ARM_VSRAuv8i16 /* 3518 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsra${p}.u8 $Vd, $Vm, $SIMM */ + ARM_VSRAuv8i8 /* 3519 */, ARM_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsri${p}.8 $Vd, $Vm, $SIMM */ + ARM_VSRIv16i8 /* 3520 */, ARM_INS_VSRI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsri${p}.64 $Vd, $Vm, $SIMM */ + ARM_VSRIv1i64 /* 3521 */, ARM_INS_VSRI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsri${p}.32 $Vd, $Vm, $SIMM */ + ARM_VSRIv2i32 /* 3522 */, ARM_INS_VSRI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsri${p}.64 $Vd, $Vm, $SIMM */ + ARM_VSRIv2i64 /* 3523 */, ARM_INS_VSRI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsri${p}.16 $Vd, $Vm, $SIMM */ + ARM_VSRIv4i16 /* 3524 */, ARM_INS_VSRI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsri${p}.32 $Vd, $Vm, $SIMM */ + ARM_VSRIv4i32 /* 3525 */, ARM_INS_VSRI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsri${p}.16 $Vd, $Vm, $SIMM */ + ARM_VSRIv8i16 /* 3526 */, ARM_INS_VSRI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsri${p}.8 $Vd, $Vm, $SIMM */ + ARM_VSRIv8i8 /* 3527 */, ARM_INS_VSRI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 \{$Vd[$lane]\}, $Rn */ + ARM_VST1LNd16 /* 3528 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 \{$Vd[$lane]\}, $Rn$Rm */ + ARM_VST1LNd16_UPD /* 3529 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 \{$Vd[$lane]\}, $Rn */ + ARM_VST1LNd32 /* 3530 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 \{$Vd[$lane]\}, $Rn$Rm */ + ARM_VST1LNd32_UPD /* 3531 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 \{$Vd[$lane]\}, $Rn */ + ARM_VST1LNd8 /* 3532 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 \{$Vd[$lane]\}, $Rn$Rm */ + ARM_VST1LNd8_UPD /* 3533 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1LNq16Pseudo /* 3534 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1LNq16Pseudo_UPD /* 3535 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1LNq32Pseudo /* 3536 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1LNq32Pseudo_UPD /* 3537 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1LNq8Pseudo /* 3538 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1LNq8Pseudo_UPD /* 3539 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $Vd, $Rn */ + ARM_VST1d16 /* 3540 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $Vd, $Rn */ + ARM_VST1d16Q /* 3541 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d16QPseudo /* 3542 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d16QPseudoWB_fixed /* 3543 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d16QPseudoWB_register /* 3544 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $Vd, $Rn! */ + ARM_VST1d16Qwb_fixed /* 3545 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $Vd, $Rn, $Rm */ + ARM_VST1d16Qwb_register /* 3546 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $Vd, $Rn */ + ARM_VST1d16T /* 3547 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d16TPseudo /* 3548 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d16TPseudoWB_fixed /* 3549 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d16TPseudoWB_register /* 3550 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $Vd, $Rn! */ + ARM_VST1d16Twb_fixed /* 3551 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $Vd, $Rn, $Rm */ + ARM_VST1d16Twb_register /* 3552 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $Vd, $Rn! */ + ARM_VST1d16wb_fixed /* 3553 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $Vd, $Rn, $Rm */ + ARM_VST1d16wb_register /* 3554 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $Vd, $Rn */ + ARM_VST1d32 /* 3555 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $Vd, $Rn */ + ARM_VST1d32Q /* 3556 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d32QPseudo /* 3557 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d32QPseudoWB_fixed /* 3558 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d32QPseudoWB_register /* 3559 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $Vd, $Rn! */ + ARM_VST1d32Qwb_fixed /* 3560 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $Vd, $Rn, $Rm */ + ARM_VST1d32Qwb_register /* 3561 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $Vd, $Rn */ + ARM_VST1d32T /* 3562 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d32TPseudo /* 3563 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d32TPseudoWB_fixed /* 3564 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d32TPseudoWB_register /* 3565 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $Vd, $Rn! */ + ARM_VST1d32Twb_fixed /* 3566 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $Vd, $Rn, $Rm */ + ARM_VST1d32Twb_register /* 3567 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $Vd, $Rn! */ + ARM_VST1d32wb_fixed /* 3568 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $Vd, $Rn, $Rm */ + ARM_VST1d32wb_register /* 3569 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.64 $Vd, $Rn */ + ARM_VST1d64 /* 3570 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.64 $Vd, $Rn */ + ARM_VST1d64Q /* 3571 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d64QPseudo /* 3572 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d64QPseudoWB_fixed /* 3573 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d64QPseudoWB_register /* 3574 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.64 $Vd, $Rn! */ + ARM_VST1d64Qwb_fixed /* 3575 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.64 $Vd, $Rn, $Rm */ + ARM_VST1d64Qwb_register /* 3576 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.64 $Vd, $Rn */ + ARM_VST1d64T /* 3577 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d64TPseudo /* 3578 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d64TPseudoWB_fixed /* 3579 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d64TPseudoWB_register /* 3580 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.64 $Vd, $Rn! */ + ARM_VST1d64Twb_fixed /* 3581 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.64 $Vd, $Rn, $Rm */ + ARM_VST1d64Twb_register /* 3582 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.64 $Vd, $Rn! */ + ARM_VST1d64wb_fixed /* 3583 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.64 $Vd, $Rn, $Rm */ + ARM_VST1d64wb_register /* 3584 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $Vd, $Rn */ + ARM_VST1d8 /* 3585 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $Vd, $Rn */ + ARM_VST1d8Q /* 3586 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d8QPseudo /* 3587 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d8QPseudoWB_fixed /* 3588 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d8QPseudoWB_register /* 3589 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $Vd, $Rn! */ + ARM_VST1d8Qwb_fixed /* 3590 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $Vd, $Rn, $Rm */ + ARM_VST1d8Qwb_register /* 3591 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $Vd, $Rn */ + ARM_VST1d8T /* 3592 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d8TPseudo /* 3593 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d8TPseudoWB_fixed /* 3594 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1d8TPseudoWB_register /* 3595 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $Vd, $Rn! */ + ARM_VST1d8Twb_fixed /* 3596 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $Vd, $Rn, $Rm */ + ARM_VST1d8Twb_register /* 3597 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $Vd, $Rn! */ + ARM_VST1d8wb_fixed /* 3598 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $Vd, $Rn, $Rm */ + ARM_VST1d8wb_register /* 3599 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $Vd, $Rn */ + ARM_VST1q16 /* 3600 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q16HighQPseudo /* 3601 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q16HighQPseudo_UPD /* 3602 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q16HighTPseudo /* 3603 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q16HighTPseudo_UPD /* 3604 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q16LowQPseudo_UPD /* 3605 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q16LowTPseudo_UPD /* 3606 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $Vd, $Rn! */ + ARM_VST1q16wb_fixed /* 3607 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.16 $Vd, $Rn, $Rm */ + ARM_VST1q16wb_register /* 3608 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $Vd, $Rn */ + ARM_VST1q32 /* 3609 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q32HighQPseudo /* 3610 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q32HighQPseudo_UPD /* 3611 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q32HighTPseudo /* 3612 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q32HighTPseudo_UPD /* 3613 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q32LowQPseudo_UPD /* 3614 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q32LowTPseudo_UPD /* 3615 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $Vd, $Rn! */ + ARM_VST1q32wb_fixed /* 3616 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.32 $Vd, $Rn, $Rm */ + ARM_VST1q32wb_register /* 3617 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.64 $Vd, $Rn */ + ARM_VST1q64 /* 3618 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q64HighQPseudo /* 3619 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q64HighQPseudo_UPD /* 3620 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q64HighTPseudo /* 3621 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q64HighTPseudo_UPD /* 3622 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q64LowQPseudo_UPD /* 3623 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q64LowTPseudo_UPD /* 3624 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.64 $Vd, $Rn! */ + ARM_VST1q64wb_fixed /* 3625 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.64 $Vd, $Rn, $Rm */ + ARM_VST1q64wb_register /* 3626 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $Vd, $Rn */ + ARM_VST1q8 /* 3627 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q8HighQPseudo /* 3628 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q8HighQPseudo_UPD /* 3629 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q8HighTPseudo /* 3630 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q8HighTPseudo_UPD /* 3631 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q8LowQPseudo_UPD /* 3632 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST1q8LowTPseudo_UPD /* 3633 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $Vd, $Rn! */ + ARM_VST1q8wb_fixed /* 3634 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst1${p}.8 $Vd, $Rn, $Rm */ + ARM_VST1q8wb_register /* 3635 */, ARM_INS_VST1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 \{$Vd[$lane], $src2[$lane]\}, $Rn */ + ARM_VST2LNd16 /* 3636 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2LNd16Pseudo /* 3637 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2LNd16Pseudo_UPD /* 3638 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 \{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */ + ARM_VST2LNd16_UPD /* 3639 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 \{$Vd[$lane], $src2[$lane]\}, $Rn */ + ARM_VST2LNd32 /* 3640 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2LNd32Pseudo /* 3641 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2LNd32Pseudo_UPD /* 3642 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 \{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */ + ARM_VST2LNd32_UPD /* 3643 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 \{$Vd[$lane], $src2[$lane]\}, $Rn */ + ARM_VST2LNd8 /* 3644 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2LNd8Pseudo /* 3645 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2LNd8Pseudo_UPD /* 3646 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 \{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */ + ARM_VST2LNd8_UPD /* 3647 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 \{$Vd[$lane], $src2[$lane]\}, $Rn */ + ARM_VST2LNq16 /* 3648 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2LNq16Pseudo /* 3649 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2LNq16Pseudo_UPD /* 3650 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 \{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */ + ARM_VST2LNq16_UPD /* 3651 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 \{$Vd[$lane], $src2[$lane]\}, $Rn */ + ARM_VST2LNq32 /* 3652 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2LNq32Pseudo /* 3653 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2LNq32Pseudo_UPD /* 3654 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 \{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */ + ARM_VST2LNq32_UPD /* 3655 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $Vd, $Rn */ + ARM_VST2b16 /* 3656 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $Vd, $Rn! */ + ARM_VST2b16wb_fixed /* 3657 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $Vd, $Rn, $Rm */ + ARM_VST2b16wb_register /* 3658 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $Vd, $Rn */ + ARM_VST2b32 /* 3659 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $Vd, $Rn! */ + ARM_VST2b32wb_fixed /* 3660 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $Vd, $Rn, $Rm */ + ARM_VST2b32wb_register /* 3661 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 $Vd, $Rn */ + ARM_VST2b8 /* 3662 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 $Vd, $Rn! */ + ARM_VST2b8wb_fixed /* 3663 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 $Vd, $Rn, $Rm */ + ARM_VST2b8wb_register /* 3664 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $Vd, $Rn */ + ARM_VST2d16 /* 3665 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $Vd, $Rn! */ + ARM_VST2d16wb_fixed /* 3666 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $Vd, $Rn, $Rm */ + ARM_VST2d16wb_register /* 3667 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $Vd, $Rn */ + ARM_VST2d32 /* 3668 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $Vd, $Rn! */ + ARM_VST2d32wb_fixed /* 3669 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $Vd, $Rn, $Rm */ + ARM_VST2d32wb_register /* 3670 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 $Vd, $Rn */ + ARM_VST2d8 /* 3671 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 $Vd, $Rn! */ + ARM_VST2d8wb_fixed /* 3672 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 $Vd, $Rn, $Rm */ + ARM_VST2d8wb_register /* 3673 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $Vd, $Rn */ + ARM_VST2q16 /* 3674 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2q16Pseudo /* 3675 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2q16PseudoWB_fixed /* 3676 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2q16PseudoWB_register /* 3677 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $Vd, $Rn! */ + ARM_VST2q16wb_fixed /* 3678 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.16 $Vd, $Rn, $Rm */ + ARM_VST2q16wb_register /* 3679 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $Vd, $Rn */ + ARM_VST2q32 /* 3680 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2q32Pseudo /* 3681 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2q32PseudoWB_fixed /* 3682 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2q32PseudoWB_register /* 3683 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $Vd, $Rn! */ + ARM_VST2q32wb_fixed /* 3684 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.32 $Vd, $Rn, $Rm */ + ARM_VST2q32wb_register /* 3685 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 $Vd, $Rn */ + ARM_VST2q8 /* 3686 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2q8Pseudo /* 3687 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2q8PseudoWB_fixed /* 3688 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST2q8PseudoWB_register /* 3689 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 $Vd, $Rn! */ + ARM_VST2q8wb_fixed /* 3690 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst2${p}.8 $Vd, $Rn, $Rm */ + ARM_VST2q8wb_register /* 3691 */, ARM_INS_VST2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */ + ARM_VST3LNd16 /* 3692 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3LNd16Pseudo /* 3693 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3LNd16Pseudo_UPD /* 3694 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */ + ARM_VST3LNd16_UPD /* 3695 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */ + ARM_VST3LNd32 /* 3696 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3LNd32Pseudo /* 3697 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3LNd32Pseudo_UPD /* 3698 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */ + ARM_VST3LNd32_UPD /* 3699 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */ + ARM_VST3LNd8 /* 3700 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3LNd8Pseudo /* 3701 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3LNd8Pseudo_UPD /* 3702 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */ + ARM_VST3LNd8_UPD /* 3703 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */ + ARM_VST3LNq16 /* 3704 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3LNq16Pseudo /* 3705 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3LNq16Pseudo_UPD /* 3706 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */ + ARM_VST3LNq16_UPD /* 3707 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */ + ARM_VST3LNq32 /* 3708 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3LNq32Pseudo /* 3709 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3LNq32Pseudo_UPD /* 3710 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */ + ARM_VST3LNq32_UPD /* 3711 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 \{$Vd, $src2, $src3\}, $Rn */ + ARM_VST3d16 /* 3712 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3d16Pseudo /* 3713 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3d16Pseudo_UPD /* 3714 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 \{$Vd, $src2, $src3\}, $Rn$Rm */ + ARM_VST3d16_UPD /* 3715 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 \{$Vd, $src2, $src3\}, $Rn */ + ARM_VST3d32 /* 3716 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3d32Pseudo /* 3717 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3d32Pseudo_UPD /* 3718 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 \{$Vd, $src2, $src3\}, $Rn$Rm */ + ARM_VST3d32_UPD /* 3719 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 \{$Vd, $src2, $src3\}, $Rn */ + ARM_VST3d8 /* 3720 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3d8Pseudo /* 3721 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3d8Pseudo_UPD /* 3722 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 \{$Vd, $src2, $src3\}, $Rn$Rm */ + ARM_VST3d8_UPD /* 3723 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 \{$Vd, $src2, $src3\}, $Rn */ + ARM_VST3q16 /* 3724 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3q16Pseudo_UPD /* 3725 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.16 \{$Vd, $src2, $src3\}, $Rn$Rm */ + ARM_VST3q16_UPD /* 3726 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3q16oddPseudo /* 3727 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3q16oddPseudo_UPD /* 3728 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 \{$Vd, $src2, $src3\}, $Rn */ + ARM_VST3q32 /* 3729 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3q32Pseudo_UPD /* 3730 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.32 \{$Vd, $src2, $src3\}, $Rn$Rm */ + ARM_VST3q32_UPD /* 3731 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3q32oddPseudo /* 3732 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3q32oddPseudo_UPD /* 3733 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 \{$Vd, $src2, $src3\}, $Rn */ + ARM_VST3q8 /* 3734 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3q8Pseudo_UPD /* 3735 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst3${p}.8 \{$Vd, $src2, $src3\}, $Rn$Rm */ + ARM_VST3q8_UPD /* 3736 */, ARM_INS_VST3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3q8oddPseudo /* 3737 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST3q8oddPseudo_UPD /* 3738 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */ + ARM_VST4LNd16 /* 3739 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4LNd16Pseudo /* 3740 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4LNd16Pseudo_UPD /* 3741 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */ + ARM_VST4LNd16_UPD /* 3742 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */ + ARM_VST4LNd32 /* 3743 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4LNd32Pseudo /* 3744 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4LNd32Pseudo_UPD /* 3745 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */ + ARM_VST4LNd32_UPD /* 3746 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */ + ARM_VST4LNd8 /* 3747 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4LNd8Pseudo /* 3748 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4LNd8Pseudo_UPD /* 3749 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */ + ARM_VST4LNd8_UPD /* 3750 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */ + ARM_VST4LNq16 /* 3751 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4LNq16Pseudo /* 3752 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4LNq16Pseudo_UPD /* 3753 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */ + ARM_VST4LNq16_UPD /* 3754 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */ + ARM_VST4LNq32 /* 3755 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4LNq32Pseudo /* 3756 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4LNq32Pseudo_UPD /* 3757 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */ + ARM_VST4LNq32_UPD /* 3758 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 \{$Vd, $src2, $src3, $src4\}, $Rn */ + ARM_VST4d16 /* 3759 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4d16Pseudo /* 3760 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4d16Pseudo_UPD /* 3761 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 \{$Vd, $src2, $src3, $src4\}, $Rn$Rm */ + ARM_VST4d16_UPD /* 3762 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 \{$Vd, $src2, $src3, $src4\}, $Rn */ + ARM_VST4d32 /* 3763 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4d32Pseudo /* 3764 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4d32Pseudo_UPD /* 3765 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 \{$Vd, $src2, $src3, $src4\}, $Rn$Rm */ + ARM_VST4d32_UPD /* 3766 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 \{$Vd, $src2, $src3, $src4\}, $Rn */ + ARM_VST4d8 /* 3767 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4d8Pseudo /* 3768 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4d8Pseudo_UPD /* 3769 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 \{$Vd, $src2, $src3, $src4\}, $Rn$Rm */ + ARM_VST4d8_UPD /* 3770 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 \{$Vd, $src2, $src3, $src4\}, $Rn */ + ARM_VST4q16 /* 3771 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4q16Pseudo_UPD /* 3772 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.16 \{$Vd, $src2, $src3, $src4\}, $Rn$Rm */ + ARM_VST4q16_UPD /* 3773 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4q16oddPseudo /* 3774 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4q16oddPseudo_UPD /* 3775 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 \{$Vd, $src2, $src3, $src4\}, $Rn */ + ARM_VST4q32 /* 3776 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4q32Pseudo_UPD /* 3777 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.32 \{$Vd, $src2, $src3, $src4\}, $Rn$Rm */ + ARM_VST4q32_UPD /* 3778 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4q32oddPseudo /* 3779 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4q32oddPseudo_UPD /* 3780 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 \{$Vd, $src2, $src3, $src4\}, $Rn */ + ARM_VST4q8 /* 3781 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4q8Pseudo_UPD /* 3782 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vst4${p}.8 \{$Vd, $src2, $src3, $src4\}, $Rn$Rm */ + ARM_VST4q8_UPD /* 3783 */, ARM_INS_VST4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4q8oddPseudo /* 3784 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VST4q8oddPseudo_UPD /* 3785 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vstmdb${p} $Rn!, $regs */ + ARM_VSTMDDB_UPD /* 3786 */, ARM_INS_VSTMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vstmia${p} $Rn, $regs */ + ARM_VSTMDIA /* 3787 */, ARM_INS_VSTMIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vstmia${p} $Rn!, $regs */ + ARM_VSTMDIA_UPD /* 3788 */, ARM_INS_VSTMIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VSTMQIA /* 3789 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vstmdb${p} $Rn!, $regs */ + ARM_VSTMSDB_UPD /* 3790 */, ARM_INS_VSTMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vstmia${p} $Rn, $regs */ + ARM_VSTMSIA /* 3791 */, ARM_INS_VSTMIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vstmia${p} $Rn!, $regs */ + ARM_VSTMSIA_UPD /* 3792 */, ARM_INS_VSTMIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} $Dd, $addr */ + ARM_VSTRD /* 3793 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p}.16 $Sd, $addr */ + ARM_VSTRH /* 3794 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs16, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} $Sd, $addr */ + ARM_VSTRS /* 3795 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} fpcxtns, $addr */ + ARM_VSTR_FPCXTNS_off /* 3796 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} fpcxtns, $Rn$addr */ + ARM_VSTR_FPCXTNS_post /* 3797 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} fpcxtns, $addr! */ + ARM_VSTR_FPCXTNS_pre /* 3798 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} fpcxts, $addr */ + ARM_VSTR_FPCXTS_off /* 3799 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} fpcxts, $Rn$addr */ + ARM_VSTR_FPCXTS_post /* 3800 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} fpcxts, $addr! */ + ARM_VSTR_FPCXTS_pre /* 3801 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} fpscr_nzcvqc, $addr */ + ARM_VSTR_FPSCR_NZCVQC_off /* 3802 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} fpscr_nzcvqc, $Rn$addr */ + ARM_VSTR_FPSCR_NZCVQC_post /* 3803 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} fpscr_nzcvqc, $addr! */ + ARM_VSTR_FPSCR_NZCVQC_pre /* 3804 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} fpscr, $addr */ + ARM_VSTR_FPSCR_off /* 3805 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} fpscr, $Rn$addr */ + ARM_VSTR_FPSCR_post /* 3806 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} fpscr, $addr! */ + ARM_VSTR_FPSCR_pre /* 3807 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} p0, $addr */ + ARM_VSTR_P0_off /* 3808 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} p0, $Rn$addr */ + ARM_VSTR_P0_post /* 3809 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} p0, $addr! */ + ARM_VSTR_P0_pre /* 3810 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} vpr, $addr */ + ARM_VSTR_VPR_off /* 3811 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { ARM_REG_VPR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} vpr, $Rn$addr */ + ARM_VSTR_VPR_post /* 3812 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { ARM_REG_VPR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vstr${p} vpr, $addr! */ + ARM_VSTR_VPR_pre /* 3813 */, ARM_INS_VSTR, + #ifndef CAPSTONE_DIET + { ARM_REG_VPR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.f64 $Dd, $Dn, $Dm */ + ARM_VSUBD /* 3814 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.f16 $Sd, $Sn, $Sm */ + ARM_VSUBH /* 3815 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vsubhn${p}.i64 $Vd, $Vn, $Vm */ + ARM_VSUBHNv2i32 /* 3816 */, ARM_INS_VSUBHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubhn${p}.i32 $Vd, $Vn, $Vm */ + ARM_VSUBHNv4i16 /* 3817 */, ARM_INS_VSUBHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubhn${p}.i16 $Vd, $Vn, $Vm */ + ARM_VSUBHNv8i8 /* 3818 */, ARM_INS_VSUBHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubl${p}.s32 $Vd, $Vn, $Vm */ + ARM_VSUBLsv2i64 /* 3819 */, ARM_INS_VSUBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubl${p}.s16 $Vd, $Vn, $Vm */ + ARM_VSUBLsv4i32 /* 3820 */, ARM_INS_VSUBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubl${p}.s8 $Vd, $Vn, $Vm */ + ARM_VSUBLsv8i16 /* 3821 */, ARM_INS_VSUBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubl${p}.u32 $Vd, $Vn, $Vm */ + ARM_VSUBLuv2i64 /* 3822 */, ARM_INS_VSUBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubl${p}.u16 $Vd, $Vn, $Vm */ + ARM_VSUBLuv4i32 /* 3823 */, ARM_INS_VSUBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubl${p}.u8 $Vd, $Vn, $Vm */ + ARM_VSUBLuv8i16 /* 3824 */, ARM_INS_VSUBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.f32 $Sd, $Sn, $Sm */ + ARM_VSUBS /* 3825 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vsubw${p}.s32 $Vd, $Vn, $Vm */ + ARM_VSUBWsv2i64 /* 3826 */, ARM_INS_VSUBW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubw${p}.s16 $Vd, $Vn, $Vm */ + ARM_VSUBWsv4i32 /* 3827 */, ARM_INS_VSUBW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubw${p}.s8 $Vd, $Vn, $Vm */ + ARM_VSUBWsv8i16 /* 3828 */, ARM_INS_VSUBW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubw${p}.u32 $Vd, $Vn, $Vm */ + ARM_VSUBWuv2i64 /* 3829 */, ARM_INS_VSUBW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubw${p}.u16 $Vd, $Vn, $Vm */ + ARM_VSUBWuv4i32 /* 3830 */, ARM_INS_VSUBW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsubw${p}.u8 $Vd, $Vn, $Vm */ + ARM_VSUBWuv8i16 /* 3831 */, ARM_INS_VSUBW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.f32 $Vd, $Vn, $Vm */ + ARM_VSUBfd /* 3832 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.f32 $Vd, $Vn, $Vm */ + ARM_VSUBfq /* 3833 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.f16 $Vd, $Vn, $Vm */ + ARM_VSUBhd /* 3834 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.f16 $Vd, $Vn, $Vm */ + ARM_VSUBhq /* 3835 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.i8 $Vd, $Vn, $Vm */ + ARM_VSUBv16i8 /* 3836 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.i64 $Vd, $Vn, $Vm */ + ARM_VSUBv1i64 /* 3837 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.i32 $Vd, $Vn, $Vm */ + ARM_VSUBv2i32 /* 3838 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.i64 $Vd, $Vn, $Vm */ + ARM_VSUBv2i64 /* 3839 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.i16 $Vd, $Vn, $Vm */ + ARM_VSUBv4i16 /* 3840 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.i32 $Vd, $Vn, $Vm */ + ARM_VSUBv4i32 /* 3841 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.i16 $Vd, $Vn, $Vm */ + ARM_VSUBv8i16 /* 3842 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsub${p}.i8 $Vd, $Vn, $Vm */ + ARM_VSUBv8i8 /* 3843 */, ARM_INS_VSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vsudot.u8 $Vd, $Vn, $Vm$lane */ + ARM_VSUDOTDI /* 3844 */, ARM_INS_VSUDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0 + #endif +}, +{ + /* vsudot.u8 $Vd, $Vn, $Vm$lane */ + ARM_VSUDOTQI /* 3845 */, ARM_INS_VSUDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0 + #endif +}, +{ + /* vswp${p} $Vd, $Vm */ + ARM_VSWPd /* 3846 */, ARM_INS_VSWP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vswp${p} $Vd, $Vm */ + ARM_VSWPq /* 3847 */, ARM_INS_VSWP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtbl${p}.8 $Vd, $Vn, $Vm */ + ARM_VTBL1 /* 3848 */, ARM_INS_VTBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtbl${p}.8 $Vd, $Vn, $Vm */ + ARM_VTBL2 /* 3849 */, ARM_INS_VTBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtbl${p}.8 $Vd, $Vn, $Vm */ + ARM_VTBL3 /* 3850 */, ARM_INS_VTBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VTBL3Pseudo /* 3851 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vtbl${p}.8 $Vd, $Vn, $Vm */ + ARM_VTBL4 /* 3852 */, ARM_INS_VTBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VTBL4Pseudo /* 3853 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vtbx${p}.8 $Vd, $Vn, $Vm */ + ARM_VTBX1 /* 3854 */, ARM_INS_VTBX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtbx${p}.8 $Vd, $Vn, $Vm */ + ARM_VTBX2 /* 3855 */, ARM_INS_VTBX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtbx${p}.8 $Vd, $Vn, $Vm */ + ARM_VTBX3 /* 3856 */, ARM_INS_VTBX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VTBX3Pseudo /* 3857 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vtbx${p}.8 $Vd, $Vn, $Vm */ + ARM_VTBX4 /* 3858 */, ARM_INS_VTBX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_VTBX4Pseudo /* 3859 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s16.f64 $dst, $a, $fbits */ + ARM_VTOSHD /* 3860 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s16.f16 $dst, $a, $fbits */ + ARM_VTOSHH /* 3861 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s16.f32 $dst, $a, $fbits */ + ARM_VTOSHS /* 3862 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcvtr${p}.s32.f64 $Sd, $Dm */ + ARM_VTOSIRD /* 3863 */, ARM_INS_VCVTR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtr${p}.s32.f16 $Sd, $Sm */ + ARM_VTOSIRH /* 3864 */, ARM_INS_VCVTR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtr${p}.s32.f32 $Sd, $Sm */ + ARM_VTOSIRS /* 3865 */, ARM_INS_VCVTR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s32.f64 $Sd, $Dm */ + ARM_VTOSIZD /* 3866 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s32.f16 $Sd, $Sm */ + ARM_VTOSIZH /* 3867 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s32.f32 $Sd, $Sm */ + ARM_VTOSIZS /* 3868 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s32.f64 $dst, $a, $fbits */ + ARM_VTOSLD /* 3869 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s32.f16 $dst, $a, $fbits */ + ARM_VTOSLH /* 3870 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.s32.f32 $dst, $a, $fbits */ + ARM_VTOSLS /* 3871 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u16.f64 $dst, $a, $fbits */ + ARM_VTOUHD /* 3872 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u16.f16 $dst, $a, $fbits */ + ARM_VTOUHH /* 3873 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u16.f32 $dst, $a, $fbits */ + ARM_VTOUHS /* 3874 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcvtr${p}.u32.f64 $Sd, $Dm */ + ARM_VTOUIRD /* 3875 */, ARM_INS_VCVTR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvtr${p}.u32.f16 $Sd, $Sm */ + ARM_VTOUIRH /* 3876 */, ARM_INS_VCVTR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvtr${p}.u32.f32 $Sd, $Sm */ + ARM_VTOUIRS /* 3877 */, ARM_INS_VCVTR, + #ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u32.f64 $Sd, $Dm */ + ARM_VTOUIZD /* 3878 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u32.f16 $Sd, $Sm */ + ARM_VTOUIZH /* 3879 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u32.f32 $Sd, $Sm */ + ARM_VTOUIZS /* 3880 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u32.f64 $dst, $a, $fbits */ + ARM_VTOULD /* 3881 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u32.f16 $dst, $a, $fbits */ + ARM_VTOULH /* 3882 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.u32.f32 $dst, $a, $fbits */ + ARM_VTOULS /* 3883 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vtrn${p}.16 $Vd, $Vm */ + ARM_VTRNd16 /* 3884 */, ARM_INS_VTRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtrn${p}.32 $Vd, $Vm */ + ARM_VTRNd32 /* 3885 */, ARM_INS_VTRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtrn${p}.8 $Vd, $Vm */ + ARM_VTRNd8 /* 3886 */, ARM_INS_VTRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtrn${p}.16 $Vd, $Vm */ + ARM_VTRNq16 /* 3887 */, ARM_INS_VTRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtrn${p}.32 $Vd, $Vm */ + ARM_VTRNq32 /* 3888 */, ARM_INS_VTRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtrn${p}.8 $Vd, $Vm */ + ARM_VTRNq8 /* 3889 */, ARM_INS_VTRN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtst${p}.8 $Vd, $Vn, $Vm */ + ARM_VTSTv16i8 /* 3890 */, ARM_INS_VTST, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtst${p}.32 $Vd, $Vn, $Vm */ + ARM_VTSTv2i32 /* 3891 */, ARM_INS_VTST, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtst${p}.16 $Vd, $Vn, $Vm */ + ARM_VTSTv4i16 /* 3892 */, ARM_INS_VTST, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtst${p}.32 $Vd, $Vn, $Vm */ + ARM_VTSTv4i32 /* 3893 */, ARM_INS_VTST, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtst${p}.16 $Vd, $Vn, $Vm */ + ARM_VTSTv8i16 /* 3894 */, ARM_INS_VTST, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vtst${p}.8 $Vd, $Vn, $Vm */ + ARM_VTSTv8i8 /* 3895 */, ARM_INS_VTST, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vudot.u8 $Vd, $Vn, $Vm */ + ARM_VUDOTD /* 3896 */, ARM_INS_VUDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0 + #endif +}, +{ + /* vudot.u8 $Vd, $Vn, $Vm$lane */ + ARM_VUDOTDI /* 3897 */, ARM_INS_VUDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0 + #endif +}, +{ + /* vudot.u8 $Vd, $Vn, $Vm */ + ARM_VUDOTQ /* 3898 */, ARM_INS_VUDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0 + #endif +}, +{ + /* vudot.u8 $Vd, $Vn, $Vm$lane */ + ARM_VUDOTQI /* 3899 */, ARM_INS_VUDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f64.u16 $dst, $a, $fbits */ + ARM_VUHTOD /* 3900 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.u16 $dst, $a, $fbits */ + ARM_VUHTOH /* 3901 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.u16 $dst, $a, $fbits */ + ARM_VUHTOS /* 3902 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f64.u32 $Dd, $Sm */ + ARM_VUITOD /* 3903 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.u32 $Sd, $Sm */ + ARM_VUITOH /* 3904 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.u32 $Sd, $Sm */ + ARM_VUITOS /* 3905 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f64.u32 $dst, $a, $fbits */ + ARM_VULTOD /* 3906 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f16.u32 $dst, $a, $fbits */ + ARM_VULTOH /* 3907 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0 + #endif +}, +{ + /* vcvt${p}.f32.u32 $dst, $a, $fbits */ + ARM_VULTOS /* 3908 */, ARM_INS_VCVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0 + #endif +}, +{ + /* vummla.u8 $Vd, $Vn, $Vm */ + ARM_VUMMLA /* 3909 */, ARM_INS_VUMMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0 + #endif +}, +{ + /* vusdot.s8 $Vd, $Vn, $Vm */ + ARM_VUSDOTD /* 3910 */, ARM_INS_VUSDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0 + #endif +}, +{ + /* vusdot.s8 $Vd, $Vn, $Vm$lane */ + ARM_VUSDOTDI /* 3911 */, ARM_INS_VUSDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0 + #endif +}, +{ + /* vusdot.s8 $Vd, $Vn, $Vm */ + ARM_VUSDOTQ /* 3912 */, ARM_INS_VUSDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0 + #endif +}, +{ + /* vusdot.s8 $Vd, $Vn, $Vm$lane */ + ARM_VUSDOTQI /* 3913 */, ARM_INS_VUSDOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0 + #endif +}, +{ + /* vusmmla.s8 $Vd, $Vn, $Vm */ + ARM_VUSMMLA /* 3914 */, ARM_INS_VUSMMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0 + #endif +}, +{ + /* vuzp${p}.16 $Vd, $Vm */ + ARM_VUZPd16 /* 3915 */, ARM_INS_VUZP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vuzp${p}.8 $Vd, $Vm */ + ARM_VUZPd8 /* 3916 */, ARM_INS_VUZP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vuzp${p}.16 $Vd, $Vm */ + ARM_VUZPq16 /* 3917 */, ARM_INS_VUZP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vuzp${p}.32 $Vd, $Vm */ + ARM_VUZPq32 /* 3918 */, ARM_INS_VUZP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vuzp${p}.8 $Vd, $Vm */ + ARM_VUZPq8 /* 3919 */, ARM_INS_VUZP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vzip${p}.16 $Vd, $Vm */ + ARM_VZIPd16 /* 3920 */, ARM_INS_VZIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vzip${p}.8 $Vd, $Vm */ + ARM_VZIPd8 /* 3921 */, ARM_INS_VZIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vzip${p}.16 $Vd, $Vm */ + ARM_VZIPq16 /* 3922 */, ARM_INS_VZIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vzip${p}.32 $Vd, $Vm */ + ARM_VZIPq32 /* 3923 */, ARM_INS_VZIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* vzip${p}.8 $Vd, $Vm */ + ARM_VZIPq8 /* 3924 */, ARM_INS_VZIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0 + #endif +}, +{ + /* ldmda${p} $Rn, $regs ^ */ + ARM_sysLDMDA /* 3925 */, ARM_INS_LDMDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldmda${p} $Rn!, $regs ^ */ + ARM_sysLDMDA_UPD /* 3926 */, ARM_INS_LDMDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldmdb${p} $Rn, $regs ^ */ + ARM_sysLDMDB /* 3927 */, ARM_INS_LDMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldmdb${p} $Rn!, $regs ^ */ + ARM_sysLDMDB_UPD /* 3928 */, ARM_INS_LDMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldm${p} $Rn, $regs ^ */ + ARM_sysLDMIA /* 3929 */, ARM_INS_LDM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldm${p} $Rn!, $regs ^ */ + ARM_sysLDMIA_UPD /* 3930 */, ARM_INS_LDM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldmib${p} $Rn, $regs ^ */ + ARM_sysLDMIB /* 3931 */, ARM_INS_LDMIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* ldmib${p} $Rn!, $regs ^ */ + ARM_sysLDMIB_UPD /* 3932 */, ARM_INS_LDMIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stmda${p} $Rn, $regs ^ */ + ARM_sysSTMDA /* 3933 */, ARM_INS_STMDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stmda${p} $Rn!, $regs ^ */ + ARM_sysSTMDA_UPD /* 3934 */, ARM_INS_STMDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stmdb${p} $Rn, $regs ^ */ + ARM_sysSTMDB /* 3935 */, ARM_INS_STMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stmdb${p} $Rn!, $regs ^ */ + ARM_sysSTMDB_UPD /* 3936 */, ARM_INS_STMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stm${p} $Rn, $regs ^ */ + ARM_sysSTMIA /* 3937 */, ARM_INS_STM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stm${p} $Rn!, $regs ^ */ + ARM_sysSTMIA_UPD /* 3938 */, ARM_INS_STM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stmib${p} $Rn, $regs ^ */ + ARM_sysSTMIB /* 3939 */, ARM_INS_STMIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* stmib${p} $Rn!, $regs ^ */ + ARM_sysSTMIB_UPD /* 3940 */, ARM_INS_STMIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0 + #endif +}, +{ + /* adc${s}${p} $Rd, $Rn, $imm */ + ARM_t2ADCri /* 3941 */, ARM_INS_ADC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* adc${s}${p}.w $Rd, $Rn, $Rm */ + ARM_t2ADCrr /* 3942 */, ARM_INS_ADC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* adc${s}${p}.w $Rd, $Rn, $ShiftedRm */ + ARM_t2ADCrs /* 3943 */, ARM_INS_ADC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* add${s}${p}.w $Rd, $Rn, $imm */ + ARM_t2ADDri /* 3944 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* addw${p} $Rd, $Rn, $imm */ + ARM_t2ADDri12 /* 3945 */, ARM_INS_ADDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* add${s}${p}.w $Rd, $Rn, $Rm */ + ARM_t2ADDrr /* 3946 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* add${s}${p}.w $Rd, $Rn, $ShiftedRm */ + ARM_t2ADDrs /* 3947 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* add${s}${p}.w $Rd, $Rn, $imm */ + ARM_t2ADDspImm /* 3948 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* addw${p} $Rd, $Rn, $imm */ + ARM_t2ADDspImm12 /* 3949 */, ARM_INS_ADDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* adr{$p}.w $Rd, $addr */ + ARM_t2ADR /* 3950 */, ARM_INS_ADR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* and${s}${p} $Rd, $Rn, $imm */ + ARM_t2ANDri /* 3951 */, ARM_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* and${s}${p}.w $Rd, $Rn, $Rm */ + ARM_t2ANDrr /* 3952 */, ARM_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* and${s}${p}.w $Rd, $Rn, $ShiftedRm */ + ARM_t2ANDrs /* 3953 */, ARM_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* asr${s}${p}.w $Rd, $Rm, $imm */ + ARM_t2ASRri /* 3954 */, ARM_INS_ASR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* asr${s}${p}.w $Rd, $Rn, $Rm */ + ARM_t2ASRrr /* 3955 */, ARM_INS_ASR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* aut r12, lr, sp */ + ARM_t2AUT /* 3956 */, ARM_INS_AUT, + #ifndef CAPSTONE_DIET + { ARM_REG_R12, ARM_REG_LR, ARM_REG_SP, 0 }, { 0 }, { ARM_FEATURE_HasV7, ARM_FEATURE_IsMClass, 0 }, 0, 0 + #endif +}, +{ + /* autg${p} $Ra, $Rn, $Rm */ + ARM_t2AUTG /* 3957 */, ARM_INS_AUTG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasPACBTI, 0 }, 0, 0 + #endif +}, +{ + /* b${p}.w $target */ + ARM_t2B /* 3958 */, ARM_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 1, 0 + #endif +}, +{ + /* bfc${p} $Rd, $imm */ + ARM_t2BFC /* 3959 */, ARM_INS_BFC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* bfi${p} $Rd, $Rn, $imm */ + ARM_t2BFI /* 3960 */, ARM_INS_BFI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* bfl${p} $b_label, $label */ + ARM_t2BFLi /* 3961 */, ARM_INS_BFL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 0, 0 + #endif +}, +{ + /* bflx${p} $b_label, $Rn */ + ARM_t2BFLr /* 3962 */, ARM_INS_BFLX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 0, 0 + #endif +}, +{ + /* bf${p} $b_label, $label */ + ARM_t2BFi /* 3963 */, ARM_INS_BF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 0, 0 + #endif +}, +{ + /* bfcsel $b_label, $label, $ba_label, $bcond */ + ARM_t2BFic /* 3964 */, ARM_INS_BFCSEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 0, 0 + #endif +}, +{ + /* bfx${p} $b_label, $Rn */ + ARM_t2BFr /* 3965 */, ARM_INS_BFX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 0, 0 + #endif +}, +{ + /* bic${s}${p} $Rd, $Rn, $imm */ + ARM_t2BICri /* 3966 */, ARM_INS_BIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* bic${s}${p}.w $Rd, $Rn, $Rm */ + ARM_t2BICrr /* 3967 */, ARM_INS_BIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* bic${s}${p}.w $Rd, $Rn, $ShiftedRm */ + ARM_t2BICrs /* 3968 */, ARM_INS_BIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* bti */ + ARM_t2BTI /* 3969 */, ARM_INS_BTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV7, ARM_FEATURE_IsMClass, 0 }, 0, 0 + #endif +}, +{ + /* bxaut${p} $Ra, $Rn, $Rm */ + ARM_t2BXAUT /* 3970 */, ARM_INS_BXAUT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasPACBTI, 0 }, 1, 1 + #endif +}, +{ + /* bxj${p} $func */ + ARM_t2BXJ /* 3971 */, ARM_INS_BXJ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 1, 1 + #endif +}, +{ + /* b${p}.w $target */ + ARM_t2Bcc /* 3972 */, ARM_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb2, 0 }, 1, 0 + #endif +}, +{ + /* cdp${p} $cop, $opc1, $CRd, $CRn, $CRm, $opc2 */ + ARM_t2CDP /* 3973 */, ARM_INS_CDP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* cdp2${p} $cop, $opc1, $CRd, $CRn, $CRm, $opc2 */ + ARM_t2CDP2 /* 3974 */, ARM_INS_CDP2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* clrex${p} */ + ARM_t2CLREX /* 3975 */, ARM_INS_CLREX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* clrm${p} $regs */ + ARM_t2CLRM /* 3976 */, ARM_INS_CLRM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* clz${p} $Rd, $Rm */ + ARM_t2CLZ /* 3977 */, ARM_INS_CLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* cmn${p}.w $Rn, $imm */ + ARM_t2CMNri /* 3978 */, ARM_INS_CMN, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* cmn${p}.w $Rn, $Rm */ + ARM_t2CMNzrr /* 3979 */, ARM_INS_CMN, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* cmn${p}.w $Rn, $ShiftedRm */ + ARM_t2CMNzrs /* 3980 */, ARM_INS_CMN, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* cmp${p}.w $Rn, $imm */ + ARM_t2CMPri /* 3981 */, ARM_INS_CMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* cmp${p}.w $Rn, $Rm */ + ARM_t2CMPrr /* 3982 */, ARM_INS_CMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* cmp${p}.w $Rn, $ShiftedRm */ + ARM_t2CMPrs /* 3983 */, ARM_INS_CMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* cps $mode */ + ARM_t2CPS1p /* 3984 */, ARM_INS_CPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* cps$imod.w $iflags */ + ARM_t2CPS2p /* 3985 */, ARM_INS_CPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* cps$imod $iflags, $mode */ + ARM_t2CPS3p /* 3986 */, ARM_INS_CPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* crc32b $Rd, $Rn, $Rm */ + ARM_t2CRC32B /* 3987 */, ARM_INS_CRC32B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0 + #endif +}, +{ + /* crc32cb $Rd, $Rn, $Rm */ + ARM_t2CRC32CB /* 3988 */, ARM_INS_CRC32CB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0 + #endif +}, +{ + /* crc32ch $Rd, $Rn, $Rm */ + ARM_t2CRC32CH /* 3989 */, ARM_INS_CRC32CH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0 + #endif +}, +{ + /* crc32cw $Rd, $Rn, $Rm */ + ARM_t2CRC32CW /* 3990 */, ARM_INS_CRC32CW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0 + #endif +}, +{ + /* crc32h $Rd, $Rn, $Rm */ + ARM_t2CRC32H /* 3991 */, ARM_INS_CRC32H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0 + #endif +}, +{ + /* crc32w $Rd, $Rn, $Rm */ + ARM_t2CRC32W /* 3992 */, ARM_INS_CRC32W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0 + #endif +}, +{ + /* csel $Rd, $Rn, $Rm, $fcond */ + ARM_t2CSEL /* 3993 */, ARM_INS_CSEL, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* csinc $Rd, $Rn, $Rm, $fcond */ + ARM_t2CSINC /* 3994 */, ARM_INS_CSINC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* csinv $Rd, $Rn, $Rm, $fcond */ + ARM_t2CSINV /* 3995 */, ARM_INS_CSINV, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* csneg $Rd, $Rn, $Rm, $fcond */ + ARM_t2CSNEG /* 3996 */, ARM_INS_CSNEG, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0 + #endif +}, +{ + /* dbg${p} $opt */ + ARM_t2DBG /* 3997 */, ARM_INS_DBG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* dcps1${p} */ + ARM_t2DCPS1 /* 3998 */, ARM_INS_DCPS1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, 0 }, 0, 0 + #endif +}, +{ + /* dcps2${p} */ + ARM_t2DCPS2 /* 3999 */, ARM_INS_DCPS2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, 0 }, 0, 0 + #endif +}, +{ + /* dcps3${p} */ + ARM_t2DCPS3 /* 4000 */, ARM_INS_DCPS3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, 0 }, 0, 0 + #endif +}, +{ + /* dls $LR, $Rn */ + ARM_t2DLS /* 4001 */, ARM_INS_DLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 0, 0 + #endif +}, +{ + /* dmb${p} $opt */ + ARM_t2DMB /* 4002 */, ARM_INS_DMB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasDB, 0 }, 0, 0 + #endif +}, +{ + /* dsb${p} $opt */ + ARM_t2DSB /* 4003 */, ARM_INS_DSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasDB, 0 }, 0, 0 + #endif +}, +{ + /* eor${s}${p} $Rd, $Rn, $imm */ + ARM_t2EORri /* 4004 */, ARM_INS_EOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* eor${s}${p}.w $Rd, $Rn, $Rm */ + ARM_t2EORrr /* 4005 */, ARM_INS_EOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* eor${s}${p}.w $Rd, $Rn, $ShiftedRm */ + ARM_t2EORrs /* 4006 */, ARM_INS_EOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* hint${p}.w $imm */ + ARM_t2HINT /* 4007 */, ARM_INS_HINT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* hvc.w $imm16 */ + ARM_t2HVC /* 4008 */, ARM_INS_HVC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsThumb2, ARM_FEATURE_HasVirtualization, 0 }, 0, 0 + #endif +}, +{ + /* isb${p} $opt */ + ARM_t2ISB /* 4009 */, ARM_INS_ISB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasDB, 0 }, 0, 0 + #endif +}, +{ + /* it$mask $cc */ + ARM_t2IT /* 4010 */, ARM_INS_IT, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_ITSTATE, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2Int_eh_sjlj_setjmp /* 4011 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_t2Int_eh_sjlj_setjmp_nofp /* 4012 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* lda${p} $Rt, $addr */ + ARM_t2LDA /* 4013 */, ARM_INS_LDA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0 + #endif +}, +{ + /* ldab${p} $Rt, $addr */ + ARM_t2LDAB /* 4014 */, ARM_INS_LDAB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0 + #endif +}, +{ + /* ldaex${p} $Rt, $addr */ + ARM_t2LDAEX /* 4015 */, ARM_INS_LDAEX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* ldaexb${p} $Rt, $addr */ + ARM_t2LDAEXB /* 4016 */, ARM_INS_LDAEXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* ldaexd${p} $Rt, $Rt2, $addr */ + ARM_t2LDAEXD /* 4017 */, ARM_INS_LDAEXD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* ldaexh${p} $Rt, $addr */ + ARM_t2LDAEXH /* 4018 */, ARM_INS_LDAEXH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* ldah${p} $Rt, $addr */ + ARM_t2LDAH /* 4019 */, ARM_INS_LDAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0 + #endif +}, +{ + /* ldc2l${p} $cop, $CRd, $addr */ + ARM_t2LDC2L_OFFSET /* 4020 */, ARM_INS_LDC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldc2l${p} $cop, $CRd, $addr, $option */ + ARM_t2LDC2L_OPTION /* 4021 */, ARM_INS_LDC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldc2l${p} $cop, $CRd, $addr, $offset */ + ARM_t2LDC2L_POST /* 4022 */, ARM_INS_LDC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldc2l${p} $cop, $CRd, $addr! */ + ARM_t2LDC2L_PRE /* 4023 */, ARM_INS_LDC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldc2${p} $cop, $CRd, $addr */ + ARM_t2LDC2_OFFSET /* 4024 */, ARM_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldc2${p} $cop, $CRd, $addr, $option */ + ARM_t2LDC2_OPTION /* 4025 */, ARM_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldc2${p} $cop, $CRd, $addr, $offset */ + ARM_t2LDC2_POST /* 4026 */, ARM_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldc2${p} $cop, $CRd, $addr! */ + ARM_t2LDC2_PRE /* 4027 */, ARM_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldcl${p} $cop, $CRd, $addr */ + ARM_t2LDCL_OFFSET /* 4028 */, ARM_INS_LDCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldcl${p} $cop, $CRd, $addr, $option */ + ARM_t2LDCL_OPTION /* 4029 */, ARM_INS_LDCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldcl${p} $cop, $CRd, $addr, $offset */ + ARM_t2LDCL_POST /* 4030 */, ARM_INS_LDCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldcl${p} $cop, $CRd, $addr! */ + ARM_t2LDCL_PRE /* 4031 */, ARM_INS_LDCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldc${p} $cop, $CRd, $addr */ + ARM_t2LDC_OFFSET /* 4032 */, ARM_INS_LDC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldc${p} $cop, $CRd, $addr, $option */ + ARM_t2LDC_OPTION /* 4033 */, ARM_INS_LDC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldc${p} $cop, $CRd, $addr, $offset */ + ARM_t2LDC_POST /* 4034 */, ARM_INS_LDC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldc${p} $cop, $CRd, $addr! */ + ARM_t2LDC_PRE /* 4035 */, ARM_INS_LDC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldmdb${p} $Rn, $regs */ + ARM_t2LDMDB /* 4036 */, ARM_INS_LDMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldmdb${p} $Rn!, $regs */ + ARM_t2LDMDB_UPD /* 4037 */, ARM_INS_LDMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldm${p}.w $Rn, $regs */ + ARM_t2LDMIA /* 4038 */, ARM_INS_LDM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldm${p}.w $Rn!, $regs */ + ARM_t2LDMIA_UPD /* 4039 */, ARM_INS_LDM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrbt${p} $Rt, $addr */ + ARM_t2LDRBT /* 4040 */, ARM_INS_LDRBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p} $Rt, $Rn$offset */ + ARM_t2LDRB_POST /* 4041 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p} $Rt, $addr! */ + ARM_t2LDRB_PRE /* 4042 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p}.w $Rt, $addr */ + ARM_t2LDRBi12 /* 4043 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p} $Rt, $addr */ + ARM_t2LDRBi8 /* 4044 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p}.w $Rt, $addr */ + ARM_t2LDRBpci /* 4045 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p}.w $Rt, $addr */ + ARM_t2LDRBs /* 4046 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrd${p} $Rt, $Rt2, $addr$imm */ + ARM_t2LDRD_POST /* 4047 */, ARM_INS_LDRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrd${p} $Rt, $Rt2, $addr! */ + ARM_t2LDRD_PRE /* 4048 */, ARM_INS_LDRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrd${p} $Rt, $Rt2, $addr */ + ARM_t2LDRDi8 /* 4049 */, ARM_INS_LDRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrex${p} $Rt, $addr */ + ARM_t2LDREX /* 4050 */, ARM_INS_LDREX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0 + #endif +}, +{ + /* ldrexb${p} $Rt, $addr */ + ARM_t2LDREXB /* 4051 */, ARM_INS_LDREXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0 + #endif +}, +{ + /* ldrexd${p} $Rt, $Rt2, $addr */ + ARM_t2LDREXD /* 4052 */, ARM_INS_LDREXD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* ldrexh${p} $Rt, $addr */ + ARM_t2LDREXH /* 4053 */, ARM_INS_LDREXH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0 + #endif +}, +{ + /* ldrht${p} $Rt, $addr */ + ARM_t2LDRHT /* 4054 */, ARM_INS_LDRHT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrh${p} $Rt, $Rn$offset */ + ARM_t2LDRH_POST /* 4055 */, ARM_INS_LDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrh${p} $Rt, $addr! */ + ARM_t2LDRH_PRE /* 4056 */, ARM_INS_LDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrh${p}.w $Rt, $addr */ + ARM_t2LDRHi12 /* 4057 */, ARM_INS_LDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrh${p} $Rt, $addr */ + ARM_t2LDRHi8 /* 4058 */, ARM_INS_LDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrh${p}.w $Rt, $addr */ + ARM_t2LDRHpci /* 4059 */, ARM_INS_LDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrh${p}.w $Rt, $addr */ + ARM_t2LDRHs /* 4060 */, ARM_INS_LDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsbt${p} $Rt, $addr */ + ARM_t2LDRSBT /* 4061 */, ARM_INS_LDRSBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsb${p} $Rt, $Rn$offset */ + ARM_t2LDRSB_POST /* 4062 */, ARM_INS_LDRSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsb${p} $Rt, $addr! */ + ARM_t2LDRSB_PRE /* 4063 */, ARM_INS_LDRSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsb${p}.w $Rt, $addr */ + ARM_t2LDRSBi12 /* 4064 */, ARM_INS_LDRSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsb${p} $Rt, $addr */ + ARM_t2LDRSBi8 /* 4065 */, ARM_INS_LDRSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsb${p}.w $Rt, $addr */ + ARM_t2LDRSBpci /* 4066 */, ARM_INS_LDRSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsb${p}.w $Rt, $addr */ + ARM_t2LDRSBs /* 4067 */, ARM_INS_LDRSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsht${p} $Rt, $addr */ + ARM_t2LDRSHT /* 4068 */, ARM_INS_LDRSHT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsh${p} $Rt, $Rn$offset */ + ARM_t2LDRSH_POST /* 4069 */, ARM_INS_LDRSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsh${p} $Rt, $addr! */ + ARM_t2LDRSH_PRE /* 4070 */, ARM_INS_LDRSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsh${p}.w $Rt, $addr */ + ARM_t2LDRSHi12 /* 4071 */, ARM_INS_LDRSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsh${p} $Rt, $addr */ + ARM_t2LDRSHi8 /* 4072 */, ARM_INS_LDRSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsh${p}.w $Rt, $addr */ + ARM_t2LDRSHpci /* 4073 */, ARM_INS_LDRSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrsh${p}.w $Rt, $addr */ + ARM_t2LDRSHs /* 4074 */, ARM_INS_LDRSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldrt${p} $Rt, $addr */ + ARM_t2LDRT /* 4075 */, ARM_INS_LDRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $Rn$offset */ + ARM_t2LDR_POST /* 4076 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr! */ + ARM_t2LDR_PRE /* 4077 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p}.w $Rt, $addr */ + ARM_t2LDRi12 /* 4078 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr */ + ARM_t2LDRi8 /* 4079 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p}.w $Rt, $addr */ + ARM_t2LDRpci /* 4080 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p}.w $Rt, $addr */ + ARM_t2LDRs /* 4081 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* le $label */ + ARM_t2LE /* 4082 */, ARM_INS_LE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 1, 0 + #endif +}, +{ + /* le $LRin, $label */ + ARM_t2LEUpdate /* 4083 */, ARM_INS_LE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 1, 0 + #endif +}, +{ + /* lsl${s}${p}.w $Rd, $Rm, $imm */ + ARM_t2LSLri /* 4084 */, ARM_INS_LSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* lsl${s}${p}.w $Rd, $Rn, $Rm */ + ARM_t2LSLrr /* 4085 */, ARM_INS_LSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* lsr${s}${p}.w $Rd, $Rm, $imm */ + ARM_t2LSRri /* 4086 */, ARM_INS_LSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* lsr${s}${p}.w $Rd, $Rn, $Rm */ + ARM_t2LSRrr /* 4087 */, ARM_INS_LSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* mcr${p} $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + ARM_t2MCR /* 4088 */, ARM_INS_MCR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + ARM_t2MCR2 /* 4089 */, ARM_INS_MCR2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* mcrr${p} $cop, $opc1, $Rt, $Rt2, $CRm */ + ARM_t2MCRR /* 4090 */, ARM_INS_MCRR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* mcrr2${p} $cop, $opc1, $Rt, $Rt2, $CRm */ + ARM_t2MCRR2 /* 4091 */, ARM_INS_MCRR2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* mla${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2MLA /* 4092 */, ARM_INS_MLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* mls${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2MLS /* 4093 */, ARM_INS_MLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* movt${p} $Rd, $imm */ + ARM_t2MOVTi16 /* 4094 */, ARM_INS_MOVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0 + #endif +}, +{ + /* mov${s}${p}.w $Rd, $imm */ + ARM_t2MOVi /* 4095 */, ARM_INS_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* movw${p} $Rd, $imm */ + ARM_t2MOVi16 /* 4096 */, ARM_INS_MOVW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0 + #endif +}, +{ + /* mov${s}${p}.w $Rd, $Rm */ + ARM_t2MOVr /* 4097 */, ARM_INS_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* asrs${p}.w $Rd, $Rm, #1 */ + ARM_t2MOVsra_flag /* 4098 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* lsrs${p}.w $Rd, $Rm, #1 */ + ARM_t2MOVsrl_flag /* 4099 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* mrc${p} $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + ARM_t2MRC /* 4100 */, ARM_INS_MRC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + ARM_t2MRC2 /* 4101 */, ARM_INS_MRC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* mrrc${p} $cop, $opc1, $Rt, $Rt2, $CRm */ + ARM_t2MRRC /* 4102 */, ARM_INS_MRRC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* mrrc2${p} $cop, $opc1, $Rt, $Rt2, $CRm */ + ARM_t2MRRC2 /* 4103 */, ARM_INS_MRRC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_PreV8, 0 }, 0, 0 + #endif +}, +{ + /* mrs${p} $Rd, apsr */ + ARM_t2MRS_AR /* 4104 */, ARM_INS_MRS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* mrs${p} $Rd, $SYSm */ + ARM_t2MRS_M /* 4105 */, ARM_INS_MRS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_IsMClass, 0 }, 0, 0 + #endif +}, +{ + /* mrs${p} $Rd, $banked */ + ARM_t2MRSbanked /* 4106 */, ARM_INS_MRS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasVirtualization, 0 }, 0, 0 + #endif +}, +{ + /* mrs${p} $Rd, spsr */ + ARM_t2MRSsys_AR /* 4107 */, ARM_INS_MRS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* msr${p} $mask, $Rn */ + ARM_t2MSR_AR /* 4108 */, ARM_INS_MSR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* msr${p} $SYSm, $Rn */ + ARM_t2MSR_M /* 4109 */, ARM_INS_MSR, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_IsMClass, 0 }, 0, 0 + #endif +}, +{ + /* msr${p} $banked, $Rn */ + ARM_t2MSRbanked /* 4110 */, ARM_INS_MSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasVirtualization, 0 }, 0, 0 + #endif +}, +{ + /* mul${p} $Rd, $Rn, $Rm */ + ARM_t2MUL /* 4111 */, ARM_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* mvn${s}${p} $Rd, $imm */ + ARM_t2MVNi /* 4112 */, ARM_INS_MVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* mvn${s}${p}.w $Rd, $Rm */ + ARM_t2MVNr /* 4113 */, ARM_INS_MVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* mvn${s}${p}.w $Rd, $ShiftedRm */ + ARM_t2MVNs /* 4114 */, ARM_INS_MVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* orn${s}${p} $Rd, $Rn, $imm */ + ARM_t2ORNri /* 4115 */, ARM_INS_ORN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* orn${s}${p} $Rd, $Rn, $Rm */ + ARM_t2ORNrr /* 4116 */, ARM_INS_ORN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* orn${s}${p} $Rd, $Rn, $ShiftedRm */ + ARM_t2ORNrs /* 4117 */, ARM_INS_ORN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* orr${s}${p} $Rd, $Rn, $imm */ + ARM_t2ORRri /* 4118 */, ARM_INS_ORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* orr${s}${p}.w $Rd, $Rn, $Rm */ + ARM_t2ORRrr /* 4119 */, ARM_INS_ORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* orr${s}${p}.w $Rd, $Rn, $ShiftedRm */ + ARM_t2ORRrs /* 4120 */, ARM_INS_ORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* pac r12, lr, sp */ + ARM_t2PAC /* 4121 */, ARM_INS_PAC, + #ifndef CAPSTONE_DIET + { ARM_REG_LR, ARM_REG_SP, 0 }, { ARM_REG_R12, 0 }, { ARM_FEATURE_HasV7, ARM_FEATURE_IsMClass, 0 }, 0, 0 + #endif +}, +{ + /* pacbti r12, lr, sp */ + ARM_t2PACBTI /* 4122 */, ARM_INS_PACBTI, + #ifndef CAPSTONE_DIET + { ARM_REG_LR, ARM_REG_SP, 0 }, { ARM_REG_R12, 0 }, { ARM_FEATURE_HasV7, ARM_FEATURE_IsMClass, 0 }, 0, 0 + #endif +}, +{ + /* pacg${p} $Rd, $Rn, $Rm */ + ARM_t2PACG /* 4123 */, ARM_INS_PACG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasPACBTI, 0 }, 0, 0 + #endif +}, +{ + /* pkhbt${p} $Rd, $Rn, $Rm$sh */ + ARM_t2PKHBT /* 4124 */, ARM_INS_PKHBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* pkhtb${p} $Rd, $Rn, $Rm$sh */ + ARM_t2PKHTB /* 4125 */, ARM_INS_PKHTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* pldw${p} $addr */ + ARM_t2PLDWi12 /* 4126 */, ARM_INS_PLDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, ARM_FEATURE_HasMP, 0 }, 0, 0 + #endif +}, +{ + /* pldw${p} $addr */ + ARM_t2PLDWi8 /* 4127 */, ARM_INS_PLDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, ARM_FEATURE_HasMP, 0 }, 0, 0 + #endif +}, +{ + /* pldw${p} $addr */ + ARM_t2PLDWs /* 4128 */, ARM_INS_PLDW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, ARM_FEATURE_HasMP, 0 }, 0, 0 + #endif +}, +{ + /* pld${p} $addr */ + ARM_t2PLDi12 /* 4129 */, ARM_INS_PLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* pld${p} $addr */ + ARM_t2PLDi8 /* 4130 */, ARM_INS_PLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* pld${p} $addr */ + ARM_t2PLDpci /* 4131 */, ARM_INS_PLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* pld${p} $addr */ + ARM_t2PLDs /* 4132 */, ARM_INS_PLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* pli${p} $addr */ + ARM_t2PLIi12 /* 4133 */, ARM_INS_PLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, 0 }, 0, 0 + #endif +}, +{ + /* pli${p} $addr */ + ARM_t2PLIi8 /* 4134 */, ARM_INS_PLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, 0 }, 0, 0 + #endif +}, +{ + /* pli${p} $addr */ + ARM_t2PLIpci /* 4135 */, ARM_INS_PLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, 0 }, 0, 0 + #endif +}, +{ + /* pli${p} $addr */ + ARM_t2PLIs /* 4136 */, ARM_INS_PLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, 0 }, 0, 0 + #endif +}, +{ + /* qadd${p} $Rd, $Rm, $Rn */ + ARM_t2QADD /* 4137 */, ARM_INS_QADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* qadd16${p} $Rd, $Rn, $Rm */ + ARM_t2QADD16 /* 4138 */, ARM_INS_QADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* qadd8${p} $Rd, $Rn, $Rm */ + ARM_t2QADD8 /* 4139 */, ARM_INS_QADD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* qasx${p} $Rd, $Rn, $Rm */ + ARM_t2QASX /* 4140 */, ARM_INS_QASX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* qdadd${p} $Rd, $Rm, $Rn */ + ARM_t2QDADD /* 4141 */, ARM_INS_QDADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* qdsub${p} $Rd, $Rm, $Rn */ + ARM_t2QDSUB /* 4142 */, ARM_INS_QDSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* qsax${p} $Rd, $Rn, $Rm */ + ARM_t2QSAX /* 4143 */, ARM_INS_QSAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* qsub${p} $Rd, $Rm, $Rn */ + ARM_t2QSUB /* 4144 */, ARM_INS_QSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* qsub16${p} $Rd, $Rn, $Rm */ + ARM_t2QSUB16 /* 4145 */, ARM_INS_QSUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* qsub8${p} $Rd, $Rn, $Rm */ + ARM_t2QSUB8 /* 4146 */, ARM_INS_QSUB8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* rbit${p} $Rd, $Rm */ + ARM_t2RBIT /* 4147 */, ARM_INS_RBIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* rev${p}.w $Rd, $Rm */ + ARM_t2REV /* 4148 */, ARM_INS_REV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* rev16${p}.w $Rd, $Rm */ + ARM_t2REV16 /* 4149 */, ARM_INS_REV16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* revsh${p}.w $Rd, $Rm */ + ARM_t2REVSH /* 4150 */, ARM_INS_REVSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* rfedb${p} $Rn */ + ARM_t2RFEDB /* 4151 */, ARM_INS_RFEDB, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_JUMP, ARM_GRP_RET, ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 1, 0 + #endif +}, +{ + /* rfedb${p} $Rn! */ + ARM_t2RFEDBW /* 4152 */, ARM_INS_RFEDB, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_JUMP, ARM_GRP_RET, ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 1, 0 + #endif +}, +{ + /* rfeia${p} $Rn */ + ARM_t2RFEIA /* 4153 */, ARM_INS_RFEIA, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_JUMP, ARM_GRP_RET, ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 1, 0 + #endif +}, +{ + /* rfeia${p} $Rn! */ + ARM_t2RFEIAW /* 4154 */, ARM_INS_RFEIA, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_JUMP, ARM_GRP_RET, ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 1, 0 + #endif +}, +{ + /* ror${s}${p}.w $Rd, $Rm, $imm */ + ARM_t2RORri /* 4155 */, ARM_INS_ROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ror${s}${p}.w $Rd, $Rn, $Rm */ + ARM_t2RORrr /* 4156 */, ARM_INS_ROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* rrx${s}${p} $Rd, $Rm */ + ARM_t2RRX /* 4157 */, ARM_INS_RRX, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* rsb${s}${p}.w $Rd, $Rn, $imm */ + ARM_t2RSBri /* 4158 */, ARM_INS_RSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* rsb${s}${p} $Rd, $Rn, $Rm */ + ARM_t2RSBrr /* 4159 */, ARM_INS_RSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* rsb${s}${p} $Rd, $Rn, $ShiftedRm */ + ARM_t2RSBrs /* 4160 */, ARM_INS_RSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sadd16${p} $Rd, $Rn, $Rm */ + ARM_t2SADD16 /* 4161 */, ARM_INS_SADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* sadd8${p} $Rd, $Rn, $Rm */ + ARM_t2SADD8 /* 4162 */, ARM_INS_SADD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* sasx${p} $Rd, $Rn, $Rm */ + ARM_t2SASX /* 4163 */, ARM_INS_SASX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* sb */ + ARM_t2SB /* 4164 */, ARM_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasSB, 0 }, 0, 0 + #endif +}, +{ + /* sbc${s}${p} $Rd, $Rn, $imm */ + ARM_t2SBCri /* 4165 */, ARM_INS_SBC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sbc${s}${p}.w $Rd, $Rn, $Rm */ + ARM_t2SBCrr /* 4166 */, ARM_INS_SBC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sbc${s}${p}.w $Rd, $Rn, $ShiftedRm */ + ARM_t2SBCrs /* 4167 */, ARM_INS_SBC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sbfx${p} $Rd, $Rn, $lsb, $msb */ + ARM_t2SBFX /* 4168 */, ARM_INS_SBFX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sdiv${p} $Rd, $Rn, $Rm */ + ARM_t2SDIV /* 4169 */, ARM_INS_SDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDivideInThumb, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0 + #endif +}, +{ + /* sel${p} $Rd, $Rn, $Rm */ + ARM_t2SEL /* 4170 */, ARM_INS_SEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* setpan $imm */ + ARM_t2SETPAN /* 4171 */, ARM_INS_SETPAN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasV8_1a, 0 }, 0, 0 + #endif +}, +{ + /* sg${p} */ + ARM_t2SG /* 4172 */, ARM_INS_SG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* shadd16${p} $Rd, $Rn, $Rm */ + ARM_t2SHADD16 /* 4173 */, ARM_INS_SHADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* shadd8${p} $Rd, $Rn, $Rm */ + ARM_t2SHADD8 /* 4174 */, ARM_INS_SHADD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* shasx${p} $Rd, $Rn, $Rm */ + ARM_t2SHASX /* 4175 */, ARM_INS_SHASX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* shsax${p} $Rd, $Rn, $Rm */ + ARM_t2SHSAX /* 4176 */, ARM_INS_SHSAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* shsub16${p} $Rd, $Rn, $Rm */ + ARM_t2SHSUB16 /* 4177 */, ARM_INS_SHSUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* shsub8${p} $Rd, $Rn, $Rm */ + ARM_t2SHSUB8 /* 4178 */, ARM_INS_SHSUB8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smc${p} $opt */ + ARM_t2SMC /* 4179 */, ARM_INS_SMC, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsThumb2, ARM_FEATURE_HasTrustZone, 0 }, 0, 0 + #endif +}, +{ + /* smlabb${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMLABB /* 4180 */, ARM_INS_SMLABB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlabt${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMLABT /* 4181 */, ARM_INS_SMLABT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlad${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMLAD /* 4182 */, ARM_INS_SMLAD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smladx${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMLADX /* 4183 */, ARM_INS_SMLADX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlal${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_t2SMLAL /* 4184 */, ARM_INS_SMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* smlalbb${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_t2SMLALBB /* 4185 */, ARM_INS_SMLALBB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlalbt${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_t2SMLALBT /* 4186 */, ARM_INS_SMLALBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlald${p} $Ra, $Rd, $Rn, $Rm */ + ARM_t2SMLALD /* 4187 */, ARM_INS_SMLALD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlaldx${p} $Ra, $Rd, $Rn, $Rm */ + ARM_t2SMLALDX /* 4188 */, ARM_INS_SMLALDX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlaltb${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_t2SMLALTB /* 4189 */, ARM_INS_SMLALTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlaltt${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_t2SMLALTT /* 4190 */, ARM_INS_SMLALTT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlatb${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMLATB /* 4191 */, ARM_INS_SMLATB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlatt${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMLATT /* 4192 */, ARM_INS_SMLATT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlawb${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMLAWB /* 4193 */, ARM_INS_SMLAWB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlawt${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMLAWT /* 4194 */, ARM_INS_SMLAWT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlsd${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMLSD /* 4195 */, ARM_INS_SMLSD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlsdx${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMLSDX /* 4196 */, ARM_INS_SMLSDX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlsld${p} $Ra, $Rd, $Rn, $Rm */ + ARM_t2SMLSLD /* 4197 */, ARM_INS_SMLSLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smlsldx${p} $Ra, $Rd, $Rn, $Rm */ + ARM_t2SMLSLDX /* 4198 */, ARM_INS_SMLSLDX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smmla${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMMLA /* 4199 */, ARM_INS_SMMLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smmlar${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMMLAR /* 4200 */, ARM_INS_SMMLAR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smmls${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMMLS /* 4201 */, ARM_INS_SMMLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smmlsr${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2SMMLSR /* 4202 */, ARM_INS_SMMLSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smmul${p} $Rd, $Rn, $Rm */ + ARM_t2SMMUL /* 4203 */, ARM_INS_SMMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smmulr${p} $Rd, $Rn, $Rm */ + ARM_t2SMMULR /* 4204 */, ARM_INS_SMMULR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smuad${p} $Rd, $Rn, $Rm */ + ARM_t2SMUAD /* 4205 */, ARM_INS_SMUAD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smuadx${p} $Rd, $Rn, $Rm */ + ARM_t2SMUADX /* 4206 */, ARM_INS_SMUADX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smulbb${p} $Rd, $Rn, $Rm */ + ARM_t2SMULBB /* 4207 */, ARM_INS_SMULBB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smulbt${p} $Rd, $Rn, $Rm */ + ARM_t2SMULBT /* 4208 */, ARM_INS_SMULBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smull${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_t2SMULL /* 4209 */, ARM_INS_SMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* smultb${p} $Rd, $Rn, $Rm */ + ARM_t2SMULTB /* 4210 */, ARM_INS_SMULTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smultt${p} $Rd, $Rn, $Rm */ + ARM_t2SMULTT /* 4211 */, ARM_INS_SMULTT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smulwb${p} $Rd, $Rn, $Rm */ + ARM_t2SMULWB /* 4212 */, ARM_INS_SMULWB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smulwt${p} $Rd, $Rn, $Rm */ + ARM_t2SMULWT /* 4213 */, ARM_INS_SMULWT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smusd${p} $Rd, $Rn, $Rm */ + ARM_t2SMUSD /* 4214 */, ARM_INS_SMUSD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* smusdx${p} $Rd, $Rn, $Rm */ + ARM_t2SMUSDX /* 4215 */, ARM_INS_SMUSDX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* srsdb${p} sp, $mode */ + ARM_t2SRSDB /* 4216 */, ARM_INS_SRSDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* srsdb${p} sp!, $mode */ + ARM_t2SRSDB_UPD /* 4217 */, ARM_INS_SRSDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* srsia${p} sp, $mode */ + ARM_t2SRSIA /* 4218 */, ARM_INS_SRSIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* srsia${p} sp!, $mode */ + ARM_t2SRSIA_UPD /* 4219 */, ARM_INS_SRSIA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* ssat${p} $Rd, $sat_imm, $Rn$sh */ + ARM_t2SSAT /* 4220 */, ARM_INS_SSAT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* ssat16${p} $Rd, $sat_imm, $Rn */ + ARM_t2SSAT16 /* 4221 */, ARM_INS_SSAT16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* ssax${p} $Rd, $Rn, $Rm */ + ARM_t2SSAX /* 4222 */, ARM_INS_SSAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* ssub16${p} $Rd, $Rn, $Rm */ + ARM_t2SSUB16 /* 4223 */, ARM_INS_SSUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* ssub8${p} $Rd, $Rn, $Rm */ + ARM_t2SSUB8 /* 4224 */, ARM_INS_SSUB8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* stc2l${p} $cop, $CRd, $addr */ + ARM_t2STC2L_OFFSET /* 4225 */, ARM_INS_STC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stc2l${p} $cop, $CRd, $addr, $option */ + ARM_t2STC2L_OPTION /* 4226 */, ARM_INS_STC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stc2l${p} $cop, $CRd, $addr, $offset */ + ARM_t2STC2L_POST /* 4227 */, ARM_INS_STC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stc2l${p} $cop, $CRd, $addr! */ + ARM_t2STC2L_PRE /* 4228 */, ARM_INS_STC2L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stc2${p} $cop, $CRd, $addr */ + ARM_t2STC2_OFFSET /* 4229 */, ARM_INS_STC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stc2${p} $cop, $CRd, $addr, $option */ + ARM_t2STC2_OPTION /* 4230 */, ARM_INS_STC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stc2${p} $cop, $CRd, $addr, $offset */ + ARM_t2STC2_POST /* 4231 */, ARM_INS_STC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stc2${p} $cop, $CRd, $addr! */ + ARM_t2STC2_PRE /* 4232 */, ARM_INS_STC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stcl${p} $cop, $CRd, $addr */ + ARM_t2STCL_OFFSET /* 4233 */, ARM_INS_STCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stcl${p} $cop, $CRd, $addr, $option */ + ARM_t2STCL_OPTION /* 4234 */, ARM_INS_STCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stcl${p} $cop, $CRd, $addr, $offset */ + ARM_t2STCL_POST /* 4235 */, ARM_INS_STCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stcl${p} $cop, $CRd, $addr! */ + ARM_t2STCL_PRE /* 4236 */, ARM_INS_STCL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stc${p} $cop, $CRd, $addr */ + ARM_t2STC_OFFSET /* 4237 */, ARM_INS_STC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stc${p} $cop, $CRd, $addr, $option */ + ARM_t2STC_OPTION /* 4238 */, ARM_INS_STC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stc${p} $cop, $CRd, $addr, $offset */ + ARM_t2STC_POST /* 4239 */, ARM_INS_STC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stc${p} $cop, $CRd, $addr! */ + ARM_t2STC_PRE /* 4240 */, ARM_INS_STC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stl${p} $Rt, $addr */ + ARM_t2STL /* 4241 */, ARM_INS_STL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0 + #endif +}, +{ + /* stlb${p} $Rt, $addr */ + ARM_t2STLB /* 4242 */, ARM_INS_STLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0 + #endif +}, +{ + /* stlex${p} $Rd, $Rt, $addr */ + ARM_t2STLEX /* 4243 */, ARM_INS_STLEX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* stlexb${p} $Rd, $Rt, $addr */ + ARM_t2STLEXB /* 4244 */, ARM_INS_STLEXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* stlexd${p} $Rd, $Rt, $Rt2, $addr */ + ARM_t2STLEXD /* 4245 */, ARM_INS_STLEXD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* stlexh${p} $Rd, $Rt, $addr */ + ARM_t2STLEXH /* 4246 */, ARM_INS_STLEXH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0 + #endif +}, +{ + /* stlh${p} $Rt, $addr */ + ARM_t2STLH /* 4247 */, ARM_INS_STLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0 + #endif +}, +{ + /* stmdb${p} $Rn, $regs */ + ARM_t2STMDB /* 4248 */, ARM_INS_STMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stmdb${p} $Rn!, $regs */ + ARM_t2STMDB_UPD /* 4249 */, ARM_INS_STMDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stm${p}.w $Rn, $regs */ + ARM_t2STMIA /* 4250 */, ARM_INS_STM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* stm${p}.w $Rn!, $regs */ + ARM_t2STMIA_UPD /* 4251 */, ARM_INS_STM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strbt${p} $Rt, $addr */ + ARM_t2STRBT /* 4252 */, ARM_INS_STRBT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strb${p} $Rt, $Rn$offset */ + ARM_t2STRB_POST /* 4253 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strb${p} $Rt, $addr! */ + ARM_t2STRB_PRE /* 4254 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strb${p}.w $Rt, $addr */ + ARM_t2STRBi12 /* 4255 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strb${p} $Rt, $addr */ + ARM_t2STRBi8 /* 4256 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strb${p}.w $Rt, $addr */ + ARM_t2STRBs /* 4257 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strd${p} $Rt, $Rt2, $addr$imm */ + ARM_t2STRD_POST /* 4258 */, ARM_INS_STRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strd${p} $Rt, $Rt2, $addr! */ + ARM_t2STRD_PRE /* 4259 */, ARM_INS_STRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strd${p} $Rt, $Rt2, $addr */ + ARM_t2STRDi8 /* 4260 */, ARM_INS_STRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strex${p} $Rd, $Rt, $addr */ + ARM_t2STREX /* 4261 */, ARM_INS_STREX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0 + #endif +}, +{ + /* strexb${p} $Rd, $Rt, $addr */ + ARM_t2STREXB /* 4262 */, ARM_INS_STREXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0 + #endif +}, +{ + /* strexd${p} $Rd, $Rt, $Rt2, $addr */ + ARM_t2STREXD /* 4263 */, ARM_INS_STREXD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* strexh${p} $Rd, $Rt, $addr */ + ARM_t2STREXH /* 4264 */, ARM_INS_STREXH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0 + #endif +}, +{ + /* strht${p} $Rt, $addr */ + ARM_t2STRHT /* 4265 */, ARM_INS_STRHT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strh${p} $Rt, $Rn$offset */ + ARM_t2STRH_POST /* 4266 */, ARM_INS_STRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strh${p} $Rt, $addr! */ + ARM_t2STRH_PRE /* 4267 */, ARM_INS_STRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strh${p}.w $Rt, $addr */ + ARM_t2STRHi12 /* 4268 */, ARM_INS_STRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strh${p} $Rt, $addr */ + ARM_t2STRHi8 /* 4269 */, ARM_INS_STRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strh${p}.w $Rt, $addr */ + ARM_t2STRHs /* 4270 */, ARM_INS_STRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* strt${p} $Rt, $addr */ + ARM_t2STRT /* 4271 */, ARM_INS_STRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* str${p} $Rt, $Rn$offset */ + ARM_t2STR_POST /* 4272 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* str${p} $Rt, $addr! */ + ARM_t2STR_PRE /* 4273 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* str${p}.w $Rt, $addr */ + ARM_t2STRi12 /* 4274 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* str${p} $Rt, $addr */ + ARM_t2STRi8 /* 4275 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* str${p}.w $Rt, $addr */ + ARM_t2STRs /* 4276 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* subs${p} pc, lr, $imm */ + ARM_t2SUBS_PC_LR /* 4277 */, ARM_INS_SUBS, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_JUMP, ARM_GRP_RET, ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 1, 0 + #endif +}, +{ + /* sub${s}${p}.w $Rd, $Rn, $imm */ + ARM_t2SUBri /* 4278 */, ARM_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* subw${p} $Rd, $Rn, $imm */ + ARM_t2SUBri12 /* 4279 */, ARM_INS_SUBW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sub${s}${p}.w $Rd, $Rn, $Rm */ + ARM_t2SUBrr /* 4280 */, ARM_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sub${s}${p}.w $Rd, $Rn, $ShiftedRm */ + ARM_t2SUBrs /* 4281 */, ARM_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sub${s}${p}.w $Rd, $Rn, $imm */ + ARM_t2SUBspImm /* 4282 */, ARM_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* subw${p} $Rd, $Rn, $imm */ + ARM_t2SUBspImm12 /* 4283 */, ARM_INS_SUBW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sxtab${p} $Rd, $Rn, $Rm$rot */ + ARM_t2SXTAB /* 4284 */, ARM_INS_SXTAB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sxtab16${p} $Rd, $Rn, $Rm$rot */ + ARM_t2SXTAB16 /* 4285 */, ARM_INS_SXTAB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sxtah${p} $Rd, $Rn, $Rm$rot */ + ARM_t2SXTAH /* 4286 */, ARM_INS_SXTAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sxtb${p}.w $Rd, $Rm$rot */ + ARM_t2SXTB /* 4287 */, ARM_INS_SXTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sxtb16${p} $Rd, $Rm$rot */ + ARM_t2SXTB16 /* 4288 */, ARM_INS_SXTB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* sxth${p}.w $Rd, $Rm$rot */ + ARM_t2SXTH /* 4289 */, ARM_INS_SXTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* tbb${p} $addr */ + ARM_t2TBB /* 4290 */, ARM_INS_TBB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsThumb2, 0 }, 1, 1 + #endif +}, +{ + /* tbh${p} $addr */ + ARM_t2TBH /* 4291 */, ARM_INS_TBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsThumb2, 0 }, 1, 1 + #endif +}, +{ + /* teq${p}.w $Rn, $imm */ + ARM_t2TEQri /* 4292 */, ARM_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* teq${p}.w $Rn, $Rm */ + ARM_t2TEQrr /* 4293 */, ARM_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* teq${p}.w $Rn, $ShiftedRm */ + ARM_t2TEQrs /* 4294 */, ARM_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* tsb${p} $opt */ + ARM_t2TSB /* 4295 */, ARM_INS_TSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8_4a, 0 }, 0, 0 + #endif +}, +{ + /* tst${p}.w $Rn, $imm */ + ARM_t2TSTri /* 4296 */, ARM_INS_TST, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* tst${p}.w $Rn, $Rm */ + ARM_t2TSTrr /* 4297 */, ARM_INS_TST, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* tst${p}.w $Rn, $ShiftedRm */ + ARM_t2TSTrs /* 4298 */, ARM_INS_TST, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* tt${p} $Rt, $Rn */ + ARM_t2TT /* 4299 */, ARM_INS_TT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* tta${p} $Rt, $Rn */ + ARM_t2TTA /* 4300 */, ARM_INS_TTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* ttat${p} $Rt, $Rn */ + ARM_t2TTAT /* 4301 */, ARM_INS_TTAT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* ttt${p} $Rt, $Rn */ + ARM_t2TTT /* 4302 */, ARM_INS_TTT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* uadd16${p} $Rd, $Rn, $Rm */ + ARM_t2UADD16 /* 4303 */, ARM_INS_UADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uadd8${p} $Rd, $Rn, $Rm */ + ARM_t2UADD8 /* 4304 */, ARM_INS_UADD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uasx${p} $Rd, $Rn, $Rm */ + ARM_t2UASX /* 4305 */, ARM_INS_UASX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* ubfx${p} $Rd, $Rn, $lsb, $msb */ + ARM_t2UBFX /* 4306 */, ARM_INS_UBFX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* udf.w $imm16 */ + ARM_t2UDF /* 4307 */, ARM_INS_UDF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* udiv${p} $Rd, $Rn, $Rm */ + ARM_t2UDIV /* 4308 */, ARM_INS_UDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDivideInThumb, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0 + #endif +}, +{ + /* uhadd16${p} $Rd, $Rn, $Rm */ + ARM_t2UHADD16 /* 4309 */, ARM_INS_UHADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uhadd8${p} $Rd, $Rn, $Rm */ + ARM_t2UHADD8 /* 4310 */, ARM_INS_UHADD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uhasx${p} $Rd, $Rn, $Rm */ + ARM_t2UHASX /* 4311 */, ARM_INS_UHASX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uhsax${p} $Rd, $Rn, $Rm */ + ARM_t2UHSAX /* 4312 */, ARM_INS_UHSAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uhsub16${p} $Rd, $Rn, $Rm */ + ARM_t2UHSUB16 /* 4313 */, ARM_INS_UHSUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uhsub8${p} $Rd, $Rn, $Rm */ + ARM_t2UHSUB8 /* 4314 */, ARM_INS_UHSUB8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* umaal${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_t2UMAAL /* 4315 */, ARM_INS_UMAAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* umlal${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_t2UMLAL /* 4316 */, ARM_INS_UMLAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* umull${p} $RdLo, $RdHi, $Rn, $Rm */ + ARM_t2UMULL /* 4317 */, ARM_INS_UMULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* uqadd16${p} $Rd, $Rn, $Rm */ + ARM_t2UQADD16 /* 4318 */, ARM_INS_UQADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uqadd8${p} $Rd, $Rn, $Rm */ + ARM_t2UQADD8 /* 4319 */, ARM_INS_UQADD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uqasx${p} $Rd, $Rn, $Rm */ + ARM_t2UQASX /* 4320 */, ARM_INS_UQASX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uqsax${p} $Rd, $Rn, $Rm */ + ARM_t2UQSAX /* 4321 */, ARM_INS_UQSAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uqsub16${p} $Rd, $Rn, $Rm */ + ARM_t2UQSUB16 /* 4322 */, ARM_INS_UQSUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uqsub8${p} $Rd, $Rn, $Rm */ + ARM_t2UQSUB8 /* 4323 */, ARM_INS_UQSUB8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* usad8${p} $Rd, $Rn, $Rm */ + ARM_t2USAD8 /* 4324 */, ARM_INS_USAD8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* usada8${p} $Rd, $Rn, $Rm, $Ra */ + ARM_t2USADA8 /* 4325 */, ARM_INS_USADA8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* usat${p} $Rd, $sat_imm, $Rn$sh */ + ARM_t2USAT /* 4326 */, ARM_INS_USAT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* usat16${p} $Rd, $sat_imm, $Rn */ + ARM_t2USAT16 /* 4327 */, ARM_INS_USAT16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* usax${p} $Rd, $Rn, $Rm */ + ARM_t2USAX /* 4328 */, ARM_INS_USAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* usub16${p} $Rd, $Rn, $Rm */ + ARM_t2USUB16 /* 4329 */, ARM_INS_USUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* usub8${p} $Rd, $Rn, $Rm */ + ARM_t2USUB8 /* 4330 */, ARM_INS_USUB8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0 + #endif +}, +{ + /* uxtab${p} $Rd, $Rn, $Rm$rot */ + ARM_t2UXTAB /* 4331 */, ARM_INS_UXTAB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* uxtab16${p} $Rd, $Rn, $Rm$rot */ + ARM_t2UXTAB16 /* 4332 */, ARM_INS_UXTAB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* uxtah${p} $Rd, $Rn, $Rm$rot */ + ARM_t2UXTAH /* 4333 */, ARM_INS_UXTAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* uxtb${p}.w $Rd, $Rm$rot */ + ARM_t2UXTB /* 4334 */, ARM_INS_UXTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* uxtb16${p} $Rd, $Rm$rot */ + ARM_t2UXTB16 /* 4335 */, ARM_INS_UXTB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* uxth${p}.w $Rd, $Rm$rot */ + ARM_t2UXTH /* 4336 */, ARM_INS_UXTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0 + #endif +}, +{ + /* wls $LR, $Rn, $label */ + ARM_t2WLS /* 4337 */, ARM_INS_WLS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 1, 0 + #endif +}, +{ + /* adc${s}${p} $Rdn, $Rm */ + ARM_tADC /* 4338 */, ARM_INS_ADC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* add${p} $Rdn, $Rm */ + ARM_tADDhirr /* 4339 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* add${s}${p} $Rd, $Rm, $imm3 */ + ARM_tADDi3 /* 4340 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* add${s}${p} $Rdn, $imm8 */ + ARM_tADDi8 /* 4341 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* add${p} $Rdn, $sp, $Rn */ + ARM_tADDrSP /* 4342 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* add${p} $dst, $sp, $imm */ + ARM_tADDrSPi /* 4343 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* add${s}${p} $Rd, $Rn, $Rm */ + ARM_tADDrr /* 4344 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* add${p} $Rdn, $imm */ + ARM_tADDspi /* 4345 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* add${p} $Rdn, $Rm */ + ARM_tADDspr /* 4346 */, ARM_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* adr{$p} $Rd, $addr */ + ARM_tADR /* 4347 */, ARM_INS_ADR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* and${s}${p} $Rdn, $Rm */ + ARM_tAND /* 4348 */, ARM_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* asr${s}${p} $Rd, $Rm, $imm5 */ + ARM_tASRri /* 4349 */, ARM_INS_ASR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* asr${s}${p} $Rdn, $Rm */ + ARM_tASRrr /* 4350 */, ARM_INS_ASR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* b${p} $target */ + ARM_tB /* 4351 */, ARM_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, 0 }, 1, 0 + #endif +}, +{ + /* bic${s}${p} $Rdn, $Rm */ + ARM_tBIC /* 4352 */, ARM_INS_BIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* bkpt $val */ + ARM_tBKPT /* 4353 */, ARM_INS_BKPT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* bl${p} $func */ + ARM_tBL /* 4354 */, ARM_INS_BL, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* blxns${p} $func */ + ARM_tBLXNSr /* 4355 */, ARM_INS_BLXNS, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsThumb, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0 + #endif +}, +{ + /* blx${p} $func */ + ARM_tBLXi /* 4356 */, ARM_INS_BLX, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV5T, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* blx${p} $func */ + ARM_tBLXr /* 4357 */, ARM_INS_BLX, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV5T, 0 }, 0, 0 + #endif +}, +{ + /* bx${p} $Rm */ + ARM_tBX /* 4358 */, ARM_INS_BX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsThumb, 0 }, 1, 1 + #endif +}, +{ + /* bxns${p} $Rm */ + ARM_tBXNS /* 4359 */, ARM_INS_BXNS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsThumb, ARM_FEATURE_Has8MSecExt, 0 }, 1, 1 + #endif +}, +{ + /* b${p} $target */ + ARM_tBcc /* 4360 */, ARM_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, 0 }, 1, 0 + #endif +}, +{ + /* cbnz $Rn, $target */ + ARM_tCBNZ /* 4361 */, ARM_INS_CBNZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 1, 0 + #endif +}, +{ + /* cbz $Rn, $target */ + ARM_tCBZ /* 4362 */, ARM_INS_CBZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 1, 0 + #endif +}, +{ + /* cmn${p} $Rn, $Rm */ + ARM_tCMNz /* 4363 */, ARM_INS_CMN, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* cmp${p} $Rn, $Rm */ + ARM_tCMPhir /* 4364 */, ARM_INS_CMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* cmp${p} $Rn, $imm8 */ + ARM_tCMPi8 /* 4365 */, ARM_INS_CMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* cmp${p} $Rn, $Rm */ + ARM_tCMPr /* 4366 */, ARM_INS_CMP, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* cps$imod $iflags */ + ARM_tCPS /* 4367 */, ARM_INS_CPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* eor${s}${p} $Rdn, $Rm */ + ARM_tEOR /* 4368 */, ARM_INS_EOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* hint${p} $imm */ + ARM_tHINT /* 4369 */, ARM_INS_HINT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6M, 0 }, 0, 0 + #endif +}, +{ + /* hlt $val */ + ARM_tHLT /* 4370 */, ARM_INS_HLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tInt_WIN_eh_sjlj_longjmp /* 4371 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tInt_eh_sjlj_longjmp /* 4372 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tInt_eh_sjlj_setjmp /* 4373 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* ldm${p} $Rn, $regs */ + ARM_tLDMIA /* 4374 */, ARM_INS_LDM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p} $Rt, $addr */ + ARM_tLDRBi /* 4375 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* ldrb${p} $Rt, $addr */ + ARM_tLDRBr /* 4376 */, ARM_INS_LDRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* ldrh${p} $Rt, $addr */ + ARM_tLDRHi /* 4377 */, ARM_INS_LDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* ldrh${p} $Rt, $addr */ + ARM_tLDRHr /* 4378 */, ARM_INS_LDRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* ldrsb${p} $Rt, $addr */ + ARM_tLDRSB /* 4379 */, ARM_INS_LDRSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* ldrsh${p} $Rt, $addr */ + ARM_tLDRSH /* 4380 */, ARM_INS_LDRSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr */ + ARM_tLDRi /* 4381 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr */ + ARM_tLDRpci /* 4382 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr */ + ARM_tLDRr /* 4383 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* ldr${p} $Rt, $addr */ + ARM_tLDRspi /* 4384 */, ARM_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* lsl${s}${p} $Rd, $Rm, $imm5 */ + ARM_tLSLri /* 4385 */, ARM_INS_LSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* lsl${s}${p} $Rdn, $Rm */ + ARM_tLSLrr /* 4386 */, ARM_INS_LSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* lsr${s}${p} $Rd, $Rm, $imm5 */ + ARM_tLSRri /* 4387 */, ARM_INS_LSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* lsr${s}${p} $Rdn, $Rm */ + ARM_tLSRrr /* 4388 */, ARM_INS_LSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* movs $Rd, $Rm */ + ARM_tMOVSr /* 4389 */, ARM_INS_MOVS, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* mov${s}${p} $Rd, $imm8 */ + ARM_tMOVi8 /* 4390 */, ARM_INS_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* mov${p} $Rd, $Rm */ + ARM_tMOVr /* 4391 */, ARM_INS_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* mul${s}${p} $Rd, $Rn, $Rm */ + ARM_tMUL /* 4392 */, ARM_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* mvn${s}${p} $Rd, $Rn */ + ARM_tMVN /* 4393 */, ARM_INS_MVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* orr${s}${p} $Rdn, $Rm */ + ARM_tORR /* 4394 */, ARM_INS_ORR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* */ + ARM_tPICADD /* 4395 */, ARM_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 + #endif +}, +{ + /* pop${p} $regs */ + ARM_tPOP /* 4396 */, ARM_INS_POP, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* push${p} $regs */ + ARM_tPUSH /* 4397 */, ARM_INS_PUSH, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* rev${p} $Rd, $Rm */ + ARM_tREV /* 4398 */, ARM_INS_REV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* rev16${p} $Rd, $Rm */ + ARM_tREV16 /* 4399 */, ARM_INS_REV16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* revsh${p} $Rd, $Rm */ + ARM_tREVSH /* 4400 */, ARM_INS_REVSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* ror${s}${p} $Rdn, $Rm */ + ARM_tROR /* 4401 */, ARM_INS_ROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* rsb${s}${p} $Rd, $Rn, #0 */ + ARM_tRSB /* 4402 */, ARM_INS_RSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* sbc${s}${p} $Rdn, $Rm */ + ARM_tSBC /* 4403 */, ARM_INS_SBC, + #ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* setend $end */ + ARM_tSETEND /* 4404 */, ARM_INS_SETEND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_IsNotMClass, 0 }, 0, 0 + #endif +}, +{ + /* stm${p} $Rn!, $regs */ + ARM_tSTMIA_UPD /* 4405 */, ARM_INS_STM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* strb${p} $Rt, $addr */ + ARM_tSTRBi /* 4406 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* strb${p} $Rt, $addr */ + ARM_tSTRBr /* 4407 */, ARM_INS_STRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* strh${p} $Rt, $addr */ + ARM_tSTRHi /* 4408 */, ARM_INS_STRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* strh${p} $Rt, $addr */ + ARM_tSTRHr /* 4409 */, ARM_INS_STRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* str${p} $Rt, $addr */ + ARM_tSTRi /* 4410 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* str${p} $Rt, $addr */ + ARM_tSTRr /* 4411 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* str${p} $Rt, $addr */ + ARM_tSTRspi /* 4412 */, ARM_INS_STR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* sub${s}${p} $Rd, $Rm, $imm3 */ + ARM_tSUBi3 /* 4413 */, ARM_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* sub${s}${p} $Rdn, $imm8 */ + ARM_tSUBi8 /* 4414 */, ARM_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* sub${s}${p} $Rd, $Rn, $Rm */ + ARM_tSUBrr /* 4415 */, ARM_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* sub${p} $Rdn, $imm */ + ARM_tSUBspi /* 4416 */, ARM_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* svc${p} $imm */ + ARM_tSVC /* 4417 */, ARM_INS_SVC, + #ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* sxtb${p} $Rd, $Rm */ + ARM_tSXTB /* 4418 */, ARM_INS_SXTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* sxth${p} $Rd, $Rm */ + ARM_tSXTH /* 4419 */, ARM_INS_SXTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* trap */ + ARM_tTRAP /* 4420 */, ARM_INS_TRAP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* tst${p} $Rn, $Rm */ + ARM_tTST /* 4421 */, ARM_INS_TST, + #ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* udf $imm8 */ + ARM_tUDF /* 4422 */, ARM_INS_UDF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, +{ + /* uxtb${p} $Rd, $Rm */ + ARM_tUXTB /* 4423 */, ARM_INS_UXTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* uxth${p} $Rd, $Rm */ + ARM_tUXTH /* 4424 */, ARM_INS_UXTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0 + #endif +}, +{ + /* __brkdiv0 */ + ARM_t__brkdiv0 /* 4425 */, ARM_INS___BRKDIV0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0 + #endif +}, diff --git a/thirdparty/capstone/arch/ARM/ARMGenCSMappingInsnName.inc b/thirdparty/capstone/arch/ARM/ARMGenCSMappingInsnName.inc new file mode 100644 index 0000000..fcf9f25 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMGenCSMappingInsnName.inc @@ -0,0 +1,650 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +"invalid", // ARM_INS_INVALID + "asr", // ARM_INS_ASR + "it", // ARM_INS_IT + "ldrbt", // ARM_INS_LDRBT + "ldr", // ARM_INS_LDR + "ldrht", // ARM_INS_LDRHT + "ldrsbt", // ARM_INS_LDRSBT + "ldrsht", // ARM_INS_LDRSHT + "ldrt", // ARM_INS_LDRT + "lsl", // ARM_INS_LSL + "lsr", // ARM_INS_LSR + "ror", // ARM_INS_ROR + "rrx", // ARM_INS_RRX + "strbt", // ARM_INS_STRBT + "strt", // ARM_INS_STRT + "vld1", // ARM_INS_VLD1 + "vld2", // ARM_INS_VLD2 + "vld3", // ARM_INS_VLD3 + "vld4", // ARM_INS_VLD4 + "vst1", // ARM_INS_VST1 + "vst2", // ARM_INS_VST2 + "vst3", // ARM_INS_VST3 + "vst4", // ARM_INS_VST4 + "ldrb", // ARM_INS_LDRB + "ldrh", // ARM_INS_LDRH + "ldrsb", // ARM_INS_LDRSB + "ldrsh", // ARM_INS_LDRSH + "movs", // ARM_INS_MOVS + "mov", // ARM_INS_MOV + "str", // ARM_INS_STR + "adc", // ARM_INS_ADC + "add", // ARM_INS_ADD + "adr", // ARM_INS_ADR + "aesd", // ARM_INS_AESD + "aese", // ARM_INS_AESE + "aesimc", // ARM_INS_AESIMC + "aesmc", // ARM_INS_AESMC + "and", // ARM_INS_AND + "vdot", // ARM_INS_VDOT + "vcvt", // ARM_INS_VCVT + "vcvtb", // ARM_INS_VCVTB + "vcvtt", // ARM_INS_VCVTT + "bfc", // ARM_INS_BFC + "bfi", // ARM_INS_BFI + "bic", // ARM_INS_BIC + "bkpt", // ARM_INS_BKPT + "bl", // ARM_INS_BL + "blx", // ARM_INS_BLX + "bx", // ARM_INS_BX + "bxj", // ARM_INS_BXJ + "b", // ARM_INS_B + "cx1", // ARM_INS_CX1 + "cx1a", // ARM_INS_CX1A + "cx1d", // ARM_INS_CX1D + "cx1da", // ARM_INS_CX1DA + "cx2", // ARM_INS_CX2 + "cx2a", // ARM_INS_CX2A + "cx2d", // ARM_INS_CX2D + "cx2da", // ARM_INS_CX2DA + "cx3", // ARM_INS_CX3 + "cx3a", // ARM_INS_CX3A + "cx3d", // ARM_INS_CX3D + "cx3da", // ARM_INS_CX3DA + "vcx1a", // ARM_INS_VCX1A + "vcx1", // ARM_INS_VCX1 + "vcx2a", // ARM_INS_VCX2A + "vcx2", // ARM_INS_VCX2 + "vcx3a", // ARM_INS_VCX3A + "vcx3", // ARM_INS_VCX3 + "cdp", // ARM_INS_CDP + "cdp2", // ARM_INS_CDP2 + "clrex", // ARM_INS_CLREX + "clz", // ARM_INS_CLZ + "cmn", // ARM_INS_CMN + "cmp", // ARM_INS_CMP + "cps", // ARM_INS_CPS + "crc32b", // ARM_INS_CRC32B + "crc32cb", // ARM_INS_CRC32CB + "crc32ch", // ARM_INS_CRC32CH + "crc32cw", // ARM_INS_CRC32CW + "crc32h", // ARM_INS_CRC32H + "crc32w", // ARM_INS_CRC32W + "dbg", // ARM_INS_DBG + "dmb", // ARM_INS_DMB + "dsb", // ARM_INS_DSB + "eor", // ARM_INS_EOR + "eret", // ARM_INS_ERET + "vmov", // ARM_INS_VMOV + "fldmdbx", // ARM_INS_FLDMDBX + "fldmiax", // ARM_INS_FLDMIAX + "vmrs", // ARM_INS_VMRS + "fstmdbx", // ARM_INS_FSTMDBX + "fstmiax", // ARM_INS_FSTMIAX + "hint", // ARM_INS_HINT + "hlt", // ARM_INS_HLT + "hvc", // ARM_INS_HVC + "isb", // ARM_INS_ISB + "lda", // ARM_INS_LDA + "ldab", // ARM_INS_LDAB + "ldaex", // ARM_INS_LDAEX + "ldaexb", // ARM_INS_LDAEXB + "ldaexd", // ARM_INS_LDAEXD + "ldaexh", // ARM_INS_LDAEXH + "ldah", // ARM_INS_LDAH + "ldc2l", // ARM_INS_LDC2L + "ldc2", // ARM_INS_LDC2 + "ldcl", // ARM_INS_LDCL + "ldc", // ARM_INS_LDC + "ldmda", // ARM_INS_LDMDA + "ldmdb", // ARM_INS_LDMDB + "ldm", // ARM_INS_LDM + "ldmib", // ARM_INS_LDMIB + "ldrd", // ARM_INS_LDRD + "ldrex", // ARM_INS_LDREX + "ldrexb", // ARM_INS_LDREXB + "ldrexd", // ARM_INS_LDREXD + "ldrexh", // ARM_INS_LDREXH + "mcr", // ARM_INS_MCR + "mcr2", // ARM_INS_MCR2 + "mcrr", // ARM_INS_MCRR + "mcrr2", // ARM_INS_MCRR2 + "mla", // ARM_INS_MLA + "mls", // ARM_INS_MLS + "movt", // ARM_INS_MOVT + "movw", // ARM_INS_MOVW + "mrc", // ARM_INS_MRC + "mrc2", // ARM_INS_MRC2 + "mrrc", // ARM_INS_MRRC + "mrrc2", // ARM_INS_MRRC2 + "mrs", // ARM_INS_MRS + "msr", // ARM_INS_MSR + "mul", // ARM_INS_MUL + "asrl", // ARM_INS_ASRL + "dlstp", // ARM_INS_DLSTP + "lctp", // ARM_INS_LCTP + "letp", // ARM_INS_LETP + "lsll", // ARM_INS_LSLL + "lsrl", // ARM_INS_LSRL + "sqrshr", // ARM_INS_SQRSHR + "sqrshrl", // ARM_INS_SQRSHRL + "sqshl", // ARM_INS_SQSHL + "sqshll", // ARM_INS_SQSHLL + "srshr", // ARM_INS_SRSHR + "srshrl", // ARM_INS_SRSHRL + "uqrshl", // ARM_INS_UQRSHL + "uqrshll", // ARM_INS_UQRSHLL + "uqshl", // ARM_INS_UQSHL + "uqshll", // ARM_INS_UQSHLL + "urshr", // ARM_INS_URSHR + "urshrl", // ARM_INS_URSHRL + "vabav", // ARM_INS_VABAV + "vabd", // ARM_INS_VABD + "vabs", // ARM_INS_VABS + "vadc", // ARM_INS_VADC + "vadci", // ARM_INS_VADCI + "vaddlva", // ARM_INS_VADDLVA + "vaddlv", // ARM_INS_VADDLV + "vaddva", // ARM_INS_VADDVA + "vaddv", // ARM_INS_VADDV + "vadd", // ARM_INS_VADD + "vand", // ARM_INS_VAND + "vbic", // ARM_INS_VBIC + "vbrsr", // ARM_INS_VBRSR + "vcadd", // ARM_INS_VCADD + "vcls", // ARM_INS_VCLS + "vclz", // ARM_INS_VCLZ + "vcmla", // ARM_INS_VCMLA + "vcmp", // ARM_INS_VCMP + "vcmul", // ARM_INS_VCMUL + "vctp", // ARM_INS_VCTP + "vcvta", // ARM_INS_VCVTA + "vcvtm", // ARM_INS_VCVTM + "vcvtn", // ARM_INS_VCVTN + "vcvtp", // ARM_INS_VCVTP + "vddup", // ARM_INS_VDDUP + "vdup", // ARM_INS_VDUP + "vdwdup", // ARM_INS_VDWDUP + "veor", // ARM_INS_VEOR + "vfmas", // ARM_INS_VFMAS + "vfma", // ARM_INS_VFMA + "vfms", // ARM_INS_VFMS + "vhadd", // ARM_INS_VHADD + "vhcadd", // ARM_INS_VHCADD + "vhsub", // ARM_INS_VHSUB + "vidup", // ARM_INS_VIDUP + "viwdup", // ARM_INS_VIWDUP + "vld20", // ARM_INS_VLD20 + "vld21", // ARM_INS_VLD21 + "vld40", // ARM_INS_VLD40 + "vld41", // ARM_INS_VLD41 + "vld42", // ARM_INS_VLD42 + "vld43", // ARM_INS_VLD43 + "vldrb", // ARM_INS_VLDRB + "vldrd", // ARM_INS_VLDRD + "vldrh", // ARM_INS_VLDRH + "vldrw", // ARM_INS_VLDRW + "vmaxav", // ARM_INS_VMAXAV + "vmaxa", // ARM_INS_VMAXA + "vmaxnmav", // ARM_INS_VMAXNMAV + "vmaxnma", // ARM_INS_VMAXNMA + "vmaxnmv", // ARM_INS_VMAXNMV + "vmaxnm", // ARM_INS_VMAXNM + "vmaxv", // ARM_INS_VMAXV + "vmax", // ARM_INS_VMAX + "vminav", // ARM_INS_VMINAV + "vmina", // ARM_INS_VMINA + "vminnmav", // ARM_INS_VMINNMAV + "vminnma", // ARM_INS_VMINNMA + "vminnmv", // ARM_INS_VMINNMV + "vminnm", // ARM_INS_VMINNM + "vminv", // ARM_INS_VMINV + "vmin", // ARM_INS_VMIN + "vmladava", // ARM_INS_VMLADAVA + "vmladavax", // ARM_INS_VMLADAVAX + "vmladav", // ARM_INS_VMLADAV + "vmladavx", // ARM_INS_VMLADAVX + "vmlaldava", // ARM_INS_VMLALDAVA + "vmlaldavax", // ARM_INS_VMLALDAVAX + "vmlaldav", // ARM_INS_VMLALDAV + "vmlaldavx", // ARM_INS_VMLALDAVX + "vmlas", // ARM_INS_VMLAS + "vmla", // ARM_INS_VMLA + "vmlsdava", // ARM_INS_VMLSDAVA + "vmlsdavax", // ARM_INS_VMLSDAVAX + "vmlsdav", // ARM_INS_VMLSDAV + "vmlsdavx", // ARM_INS_VMLSDAVX + "vmlsldava", // ARM_INS_VMLSLDAVA + "vmlsldavax", // ARM_INS_VMLSLDAVAX + "vmlsldav", // ARM_INS_VMLSLDAV + "vmlsldavx", // ARM_INS_VMLSLDAVX + "vmovlb", // ARM_INS_VMOVLB + "vmovlt", // ARM_INS_VMOVLT + "vmovnb", // ARM_INS_VMOVNB + "vmovnt", // ARM_INS_VMOVNT + "vmulh", // ARM_INS_VMULH + "vmullb", // ARM_INS_VMULLB + "vmullt", // ARM_INS_VMULLT + "vmul", // ARM_INS_VMUL + "vmvn", // ARM_INS_VMVN + "vneg", // ARM_INS_VNEG + "vorn", // ARM_INS_VORN + "vorr", // ARM_INS_VORR + "vpnot", // ARM_INS_VPNOT + "vpsel", // ARM_INS_VPSEL + "vpst", // ARM_INS_VPST + "vpt", // ARM_INS_VPT + "vqabs", // ARM_INS_VQABS + "vqadd", // ARM_INS_VQADD + "vqdmladhx", // ARM_INS_VQDMLADHX + "vqdmladh", // ARM_INS_VQDMLADH + "vqdmlah", // ARM_INS_VQDMLAH + "vqdmlash", // ARM_INS_VQDMLASH + "vqdmlsdhx", // ARM_INS_VQDMLSDHX + "vqdmlsdh", // ARM_INS_VQDMLSDH + "vqdmulh", // ARM_INS_VQDMULH + "vqdmullb", // ARM_INS_VQDMULLB + "vqdmullt", // ARM_INS_VQDMULLT + "vqmovnb", // ARM_INS_VQMOVNB + "vqmovnt", // ARM_INS_VQMOVNT + "vqmovunb", // ARM_INS_VQMOVUNB + "vqmovunt", // ARM_INS_VQMOVUNT + "vqneg", // ARM_INS_VQNEG + "vqrdmladhx", // ARM_INS_VQRDMLADHX + "vqrdmladh", // ARM_INS_VQRDMLADH + "vqrdmlah", // ARM_INS_VQRDMLAH + "vqrdmlash", // ARM_INS_VQRDMLASH + "vqrdmlsdhx", // ARM_INS_VQRDMLSDHX + "vqrdmlsdh", // ARM_INS_VQRDMLSDH + "vqrdmulh", // ARM_INS_VQRDMULH + "vqrshl", // ARM_INS_VQRSHL + "vqrshrnb", // ARM_INS_VQRSHRNB + "vqrshrnt", // ARM_INS_VQRSHRNT + "vqrshrunb", // ARM_INS_VQRSHRUNB + "vqrshrunt", // ARM_INS_VQRSHRUNT + "vqshlu", // ARM_INS_VQSHLU + "vqshl", // ARM_INS_VQSHL + "vqshrnb", // ARM_INS_VQSHRNB + "vqshrnt", // ARM_INS_VQSHRNT + "vqshrunb", // ARM_INS_VQSHRUNB + "vqshrunt", // ARM_INS_VQSHRUNT + "vqsub", // ARM_INS_VQSUB + "vrev16", // ARM_INS_VREV16 + "vrev32", // ARM_INS_VREV32 + "vrev64", // ARM_INS_VREV64 + "vrhadd", // ARM_INS_VRHADD + "vrinta", // ARM_INS_VRINTA + "vrintm", // ARM_INS_VRINTM + "vrintn", // ARM_INS_VRINTN + "vrintp", // ARM_INS_VRINTP + "vrintx", // ARM_INS_VRINTX + "vrintz", // ARM_INS_VRINTZ + "vrmlaldavha", // ARM_INS_VRMLALDAVHA + "vrmlaldavhax", // ARM_INS_VRMLALDAVHAX + "vrmlaldavh", // ARM_INS_VRMLALDAVH + "vrmlaldavhx", // ARM_INS_VRMLALDAVHX + "vrmlsldavha", // ARM_INS_VRMLSLDAVHA + "vrmlsldavhax", // ARM_INS_VRMLSLDAVHAX + "vrmlsldavh", // ARM_INS_VRMLSLDAVH + "vrmlsldavhx", // ARM_INS_VRMLSLDAVHX + "vrmulh", // ARM_INS_VRMULH + "vrshl", // ARM_INS_VRSHL + "vrshrnb", // ARM_INS_VRSHRNB + "vrshrnt", // ARM_INS_VRSHRNT + "vrshr", // ARM_INS_VRSHR + "vsbc", // ARM_INS_VSBC + "vsbci", // ARM_INS_VSBCI + "vshlc", // ARM_INS_VSHLC + "vshllb", // ARM_INS_VSHLLB + "vshllt", // ARM_INS_VSHLLT + "vshl", // ARM_INS_VSHL + "vshrnb", // ARM_INS_VSHRNB + "vshrnt", // ARM_INS_VSHRNT + "vshr", // ARM_INS_VSHR + "vsli", // ARM_INS_VSLI + "vsri", // ARM_INS_VSRI + "vst20", // ARM_INS_VST20 + "vst21", // ARM_INS_VST21 + "vst40", // ARM_INS_VST40 + "vst41", // ARM_INS_VST41 + "vst42", // ARM_INS_VST42 + "vst43", // ARM_INS_VST43 + "vstrb", // ARM_INS_VSTRB + "vstrd", // ARM_INS_VSTRD + "vstrh", // ARM_INS_VSTRH + "vstrw", // ARM_INS_VSTRW + "vsub", // ARM_INS_VSUB + "wlstp", // ARM_INS_WLSTP + "mvn", // ARM_INS_MVN + "orr", // ARM_INS_ORR + "pkhbt", // ARM_INS_PKHBT + "pkhtb", // ARM_INS_PKHTB + "pldw", // ARM_INS_PLDW + "pld", // ARM_INS_PLD + "pli", // ARM_INS_PLI + "qadd", // ARM_INS_QADD + "qadd16", // ARM_INS_QADD16 + "qadd8", // ARM_INS_QADD8 + "qasx", // ARM_INS_QASX + "qdadd", // ARM_INS_QDADD + "qdsub", // ARM_INS_QDSUB + "qsax", // ARM_INS_QSAX + "qsub", // ARM_INS_QSUB + "qsub16", // ARM_INS_QSUB16 + "qsub8", // ARM_INS_QSUB8 + "rbit", // ARM_INS_RBIT + "rev", // ARM_INS_REV + "rev16", // ARM_INS_REV16 + "revsh", // ARM_INS_REVSH + "rfeda", // ARM_INS_RFEDA + "rfedb", // ARM_INS_RFEDB + "rfeia", // ARM_INS_RFEIA + "rfeib", // ARM_INS_RFEIB + "rsb", // ARM_INS_RSB + "rsc", // ARM_INS_RSC + "sadd16", // ARM_INS_SADD16 + "sadd8", // ARM_INS_SADD8 + "sasx", // ARM_INS_SASX + "sb", // ARM_INS_SB + "sbc", // ARM_INS_SBC + "sbfx", // ARM_INS_SBFX + "sdiv", // ARM_INS_SDIV + "sel", // ARM_INS_SEL + "setend", // ARM_INS_SETEND + "setpan", // ARM_INS_SETPAN + "sha1c", // ARM_INS_SHA1C + "sha1h", // ARM_INS_SHA1H + "sha1m", // ARM_INS_SHA1M + "sha1p", // ARM_INS_SHA1P + "sha1su0", // ARM_INS_SHA1SU0 + "sha1su1", // ARM_INS_SHA1SU1 + "sha256h", // ARM_INS_SHA256H + "sha256h2", // ARM_INS_SHA256H2 + "sha256su0", // ARM_INS_SHA256SU0 + "sha256su1", // ARM_INS_SHA256SU1 + "shadd16", // ARM_INS_SHADD16 + "shadd8", // ARM_INS_SHADD8 + "shasx", // ARM_INS_SHASX + "shsax", // ARM_INS_SHSAX + "shsub16", // ARM_INS_SHSUB16 + "shsub8", // ARM_INS_SHSUB8 + "smc", // ARM_INS_SMC + "smlabb", // ARM_INS_SMLABB + "smlabt", // ARM_INS_SMLABT + "smlad", // ARM_INS_SMLAD + "smladx", // ARM_INS_SMLADX + "smlal", // ARM_INS_SMLAL + "smlalbb", // ARM_INS_SMLALBB + "smlalbt", // ARM_INS_SMLALBT + "smlald", // ARM_INS_SMLALD + "smlaldx", // ARM_INS_SMLALDX + "smlaltb", // ARM_INS_SMLALTB + "smlaltt", // ARM_INS_SMLALTT + "smlatb", // ARM_INS_SMLATB + "smlatt", // ARM_INS_SMLATT + "smlawb", // ARM_INS_SMLAWB + "smlawt", // ARM_INS_SMLAWT + "smlsd", // ARM_INS_SMLSD + "smlsdx", // ARM_INS_SMLSDX + "smlsld", // ARM_INS_SMLSLD + "smlsldx", // ARM_INS_SMLSLDX + "smmla", // ARM_INS_SMMLA + "smmlar", // ARM_INS_SMMLAR + "smmls", // ARM_INS_SMMLS + "smmlsr", // ARM_INS_SMMLSR + "smmul", // ARM_INS_SMMUL + "smmulr", // ARM_INS_SMMULR + "smuad", // ARM_INS_SMUAD + "smuadx", // ARM_INS_SMUADX + "smulbb", // ARM_INS_SMULBB + "smulbt", // ARM_INS_SMULBT + "smull", // ARM_INS_SMULL + "smultb", // ARM_INS_SMULTB + "smultt", // ARM_INS_SMULTT + "smulwb", // ARM_INS_SMULWB + "smulwt", // ARM_INS_SMULWT + "smusd", // ARM_INS_SMUSD + "smusdx", // ARM_INS_SMUSDX + "srsda", // ARM_INS_SRSDA + "srsdb", // ARM_INS_SRSDB + "srsia", // ARM_INS_SRSIA + "srsib", // ARM_INS_SRSIB + "ssat", // ARM_INS_SSAT + "ssat16", // ARM_INS_SSAT16 + "ssax", // ARM_INS_SSAX + "ssub16", // ARM_INS_SSUB16 + "ssub8", // ARM_INS_SSUB8 + "stc2l", // ARM_INS_STC2L + "stc2", // ARM_INS_STC2 + "stcl", // ARM_INS_STCL + "stc", // ARM_INS_STC + "stl", // ARM_INS_STL + "stlb", // ARM_INS_STLB + "stlex", // ARM_INS_STLEX + "stlexb", // ARM_INS_STLEXB + "stlexd", // ARM_INS_STLEXD + "stlexh", // ARM_INS_STLEXH + "stlh", // ARM_INS_STLH + "stmda", // ARM_INS_STMDA + "stmdb", // ARM_INS_STMDB + "stm", // ARM_INS_STM + "stmib", // ARM_INS_STMIB + "strb", // ARM_INS_STRB + "strd", // ARM_INS_STRD + "strex", // ARM_INS_STREX + "strexb", // ARM_INS_STREXB + "strexd", // ARM_INS_STREXD + "strexh", // ARM_INS_STREXH + "strh", // ARM_INS_STRH + "strht", // ARM_INS_STRHT + "sub", // ARM_INS_SUB + "svc", // ARM_INS_SVC + "swp", // ARM_INS_SWP + "swpb", // ARM_INS_SWPB + "sxtab", // ARM_INS_SXTAB + "sxtab16", // ARM_INS_SXTAB16 + "sxtah", // ARM_INS_SXTAH + "sxtb", // ARM_INS_SXTB + "sxtb16", // ARM_INS_SXTB16 + "sxth", // ARM_INS_SXTH + "teq", // ARM_INS_TEQ + "trap", // ARM_INS_TRAP + "tsb", // ARM_INS_TSB + "tst", // ARM_INS_TST + "uadd16", // ARM_INS_UADD16 + "uadd8", // ARM_INS_UADD8 + "uasx", // ARM_INS_UASX + "ubfx", // ARM_INS_UBFX + "udf", // ARM_INS_UDF + "udiv", // ARM_INS_UDIV + "uhadd16", // ARM_INS_UHADD16 + "uhadd8", // ARM_INS_UHADD8 + "uhasx", // ARM_INS_UHASX + "uhsax", // ARM_INS_UHSAX + "uhsub16", // ARM_INS_UHSUB16 + "uhsub8", // ARM_INS_UHSUB8 + "umaal", // ARM_INS_UMAAL + "umlal", // ARM_INS_UMLAL + "umull", // ARM_INS_UMULL + "uqadd16", // ARM_INS_UQADD16 + "uqadd8", // ARM_INS_UQADD8 + "uqasx", // ARM_INS_UQASX + "uqsax", // ARM_INS_UQSAX + "uqsub16", // ARM_INS_UQSUB16 + "uqsub8", // ARM_INS_UQSUB8 + "usad8", // ARM_INS_USAD8 + "usada8", // ARM_INS_USADA8 + "usat", // ARM_INS_USAT + "usat16", // ARM_INS_USAT16 + "usax", // ARM_INS_USAX + "usub16", // ARM_INS_USUB16 + "usub8", // ARM_INS_USUB8 + "uxtab", // ARM_INS_UXTAB + "uxtab16", // ARM_INS_UXTAB16 + "uxtah", // ARM_INS_UXTAH + "uxtb", // ARM_INS_UXTB + "uxtb16", // ARM_INS_UXTB16 + "uxth", // ARM_INS_UXTH + "vabal", // ARM_INS_VABAL + "vaba", // ARM_INS_VABA + "vabdl", // ARM_INS_VABDL + "vacge", // ARM_INS_VACGE + "vacgt", // ARM_INS_VACGT + "vaddhn", // ARM_INS_VADDHN + "vaddl", // ARM_INS_VADDL + "vaddw", // ARM_INS_VADDW + "vfmab", // ARM_INS_VFMAB + "vfmat", // ARM_INS_VFMAT + "vbif", // ARM_INS_VBIF + "vbit", // ARM_INS_VBIT + "vbsl", // ARM_INS_VBSL + "vceq", // ARM_INS_VCEQ + "vcge", // ARM_INS_VCGE + "vcgt", // ARM_INS_VCGT + "vcle", // ARM_INS_VCLE + "vclt", // ARM_INS_VCLT + "vcmpe", // ARM_INS_VCMPE + "vcnt", // ARM_INS_VCNT + "vdiv", // ARM_INS_VDIV + "vext", // ARM_INS_VEXT + "vfmal", // ARM_INS_VFMAL + "vfmsl", // ARM_INS_VFMSL + "vfnma", // ARM_INS_VFNMA + "vfnms", // ARM_INS_VFNMS + "vins", // ARM_INS_VINS + "vjcvt", // ARM_INS_VJCVT + "vldmdb", // ARM_INS_VLDMDB + "vldmia", // ARM_INS_VLDMIA + "vldr", // ARM_INS_VLDR + "vlldm", // ARM_INS_VLLDM + "vlstm", // ARM_INS_VLSTM + "vmlal", // ARM_INS_VMLAL + "vmls", // ARM_INS_VMLS + "vmlsl", // ARM_INS_VMLSL + "vmmla", // ARM_INS_VMMLA + "vmovx", // ARM_INS_VMOVX + "vmovl", // ARM_INS_VMOVL + "vmovn", // ARM_INS_VMOVN + "vmsr", // ARM_INS_VMSR + "vmull", // ARM_INS_VMULL + "vnmla", // ARM_INS_VNMLA + "vnmls", // ARM_INS_VNMLS + "vnmul", // ARM_INS_VNMUL + "vpadal", // ARM_INS_VPADAL + "vpaddl", // ARM_INS_VPADDL + "vpadd", // ARM_INS_VPADD + "vpmax", // ARM_INS_VPMAX + "vpmin", // ARM_INS_VPMIN + "vqdmlal", // ARM_INS_VQDMLAL + "vqdmlsl", // ARM_INS_VQDMLSL + "vqdmull", // ARM_INS_VQDMULL + "vqmovun", // ARM_INS_VQMOVUN + "vqmovn", // ARM_INS_VQMOVN + "vqrdmlsh", // ARM_INS_VQRDMLSH + "vqrshrn", // ARM_INS_VQRSHRN + "vqrshrun", // ARM_INS_VQRSHRUN + "vqshrn", // ARM_INS_VQSHRN + "vqshrun", // ARM_INS_VQSHRUN + "vraddhn", // ARM_INS_VRADDHN + "vrecpe", // ARM_INS_VRECPE + "vrecps", // ARM_INS_VRECPS + "vrintr", // ARM_INS_VRINTR + "vrshrn", // ARM_INS_VRSHRN + "vrsqrte", // ARM_INS_VRSQRTE + "vrsqrts", // ARM_INS_VRSQRTS + "vrsra", // ARM_INS_VRSRA + "vrsubhn", // ARM_INS_VRSUBHN + "vscclrm", // ARM_INS_VSCCLRM + "vsdot", // ARM_INS_VSDOT + "vseleq", // ARM_INS_VSELEQ + "vselge", // ARM_INS_VSELGE + "vselgt", // ARM_INS_VSELGT + "vselvs", // ARM_INS_VSELVS + "vshll", // ARM_INS_VSHLL + "vshrn", // ARM_INS_VSHRN + "vsmmla", // ARM_INS_VSMMLA + "vsqrt", // ARM_INS_VSQRT + "vsra", // ARM_INS_VSRA + "vstmdb", // ARM_INS_VSTMDB + "vstmia", // ARM_INS_VSTMIA + "vstr", // ARM_INS_VSTR + "vsubhn", // ARM_INS_VSUBHN + "vsubl", // ARM_INS_VSUBL + "vsubw", // ARM_INS_VSUBW + "vsudot", // ARM_INS_VSUDOT + "vswp", // ARM_INS_VSWP + "vtbl", // ARM_INS_VTBL + "vtbx", // ARM_INS_VTBX + "vcvtr", // ARM_INS_VCVTR + "vtrn", // ARM_INS_VTRN + "vtst", // ARM_INS_VTST + "vudot", // ARM_INS_VUDOT + "vummla", // ARM_INS_VUMMLA + "vusdot", // ARM_INS_VUSDOT + "vusmmla", // ARM_INS_VUSMMLA + "vuzp", // ARM_INS_VUZP + "vzip", // ARM_INS_VZIP + "addw", // ARM_INS_ADDW + "aut", // ARM_INS_AUT + "autg", // ARM_INS_AUTG + "bfl", // ARM_INS_BFL + "bflx", // ARM_INS_BFLX + "bf", // ARM_INS_BF + "bfcsel", // ARM_INS_BFCSEL + "bfx", // ARM_INS_BFX + "bti", // ARM_INS_BTI + "bxaut", // ARM_INS_BXAUT + "clrm", // ARM_INS_CLRM + "csel", // ARM_INS_CSEL + "csinc", // ARM_INS_CSINC + "csinv", // ARM_INS_CSINV + "csneg", // ARM_INS_CSNEG + "dcps1", // ARM_INS_DCPS1 + "dcps2", // ARM_INS_DCPS2 + "dcps3", // ARM_INS_DCPS3 + "dls", // ARM_INS_DLS + "le", // ARM_INS_LE + "orn", // ARM_INS_ORN + "pac", // ARM_INS_PAC + "pacbti", // ARM_INS_PACBTI + "pacg", // ARM_INS_PACG + "sg", // ARM_INS_SG + "subs", // ARM_INS_SUBS + "subw", // ARM_INS_SUBW + "tbb", // ARM_INS_TBB + "tbh", // ARM_INS_TBH + "tt", // ARM_INS_TT + "tta", // ARM_INS_TTA + "ttat", // ARM_INS_TTAT + "ttt", // ARM_INS_TTT + "wls", // ARM_INS_WLS + "blxns", // ARM_INS_BLXNS + "bxns", // ARM_INS_BXNS + "cbnz", // ARM_INS_CBNZ + "cbz", // ARM_INS_CBZ + "pop", // ARM_INS_POP + "push", // ARM_INS_PUSH + "__brkdiv0", // ARM_INS___BRKDIV0 diff --git a/thirdparty/capstone/arch/ARM/ARMGenCSMappingInsnOp.inc b/thirdparty/capstone/arch/ARM/ARMGenCSMappingInsnOp.inc new file mode 100644 index 0000000..12c9a1f --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMGenCSMappingInsnOp.inc @@ -0,0 +1,89779 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{ { { /* ARM_PHI (0) - ARM_INS_INVALID - PHINODE */ + 0 } } }, + { { { /* ARM_INLINEASM (1) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_INLINEASM_BR (2) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_CFI_INSTRUCTION (3) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_EH_LABEL (4) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_GC_LABEL (5) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_ANNOTATION_LABEL (6) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_KILL (7) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_EXTRACT_SUBREG (8) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_INSERT_SUBREG (9) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_IMPLICIT_DEF (10) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SUBREG_TO_REG (11) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_COPY_TO_REGCLASS (12) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_DBG_VALUE (13) - ARM_INS_INVALID - DBG_VALUE */ + 0 } } }, + { { { /* ARM_DBG_VALUE_LIST (14) - ARM_INS_INVALID - DBG_VALUE_LIST */ + 0 } } }, + { { { /* ARM_DBG_INSTR_REF (15) - ARM_INS_INVALID - DBG_INSTR_REF */ + 0 } } }, + { { { /* ARM_DBG_PHI (16) - ARM_INS_INVALID - DBG_PHI */ + 0 } } }, + { { { /* ARM_DBG_LABEL (17) - ARM_INS_INVALID - DBG_LABEL */ + 0 } } }, + { { { /* ARM_REG_SEQUENCE (18) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_COPY (19) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BUNDLE (20) - ARM_INS_INVALID - BUNDLE */ + 0 } } }, + { { { /* ARM_LIFETIME_START (21) - ARM_INS_INVALID - LIFETIME_START */ + 0 } } }, + { { { /* ARM_LIFETIME_END (22) - ARM_INS_INVALID - LIFETIME_END */ + 0 } } }, + { { { /* ARM_PSEUDO_PROBE (23) - ARM_INS_INVALID - PSEUDO_PROBE */ + 0 } } }, + { { { /* ARM_ARITH_FENCE (24) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_STACKMAP (25) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_FENTRY_CALL (26) - ARM_INS_INVALID - # FEntry call */ + 0 } } }, + { { { /* ARM_PATCHPOINT (27) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_LOAD_STACK_GUARD (28) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PREALLOCATED_SETUP (29) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PREALLOCATED_ARG (30) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_STATEPOINT (31) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_LOCAL_ESCAPE (32) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_FAULTING_OP (33) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PATCHABLE_OP (34) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PATCHABLE_FUNCTION_ENTER (35) - ARM_INS_INVALID - # XRay Function Enter. */ + 0 } } }, + { { { /* ARM_PATCHABLE_RET (36) - ARM_INS_INVALID - # XRay Function Patchable RET. */ + 0 } } }, + { { { /* ARM_PATCHABLE_FUNCTION_EXIT (37) - ARM_INS_INVALID - # XRay Function Exit. */ + 0 } } }, + { { { /* ARM_PATCHABLE_TAIL_CALL (38) - ARM_INS_INVALID - # XRay Tail Call Exit. */ + 0 } } }, + { { { /* ARM_PATCHABLE_EVENT_CALL (39) - ARM_INS_INVALID - # XRay Custom Event Log. */ + 0 } } }, + { { { /* ARM_PATCHABLE_TYPED_EVENT_CALL (40) - ARM_INS_INVALID - # XRay Typed Event Log. */ + 0 } } }, + { { { /* ARM_ICALL_BRANCH_FUNNEL (41) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MEMBARRIER (42) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ASSERT_SEXT (43) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ASSERT_ZEXT (44) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ASSERT_ALIGN (45) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ADD (46) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SUB (47) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_MUL (48) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SDIV (49) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UDIV (50) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SREM (51) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UREM (52) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SDIVREM (53) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UDIVREM (54) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_AND (55) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_OR (56) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_XOR (57) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_IMPLICIT_DEF (58) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_PHI (59) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FRAME_INDEX (60) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_GLOBAL_VALUE (61) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_EXTRACT (62) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UNMERGE_VALUES (63) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INSERT (64) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_MERGE_VALUES (65) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_BUILD_VECTOR (66) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_BUILD_VECTOR_TRUNC (67) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_CONCAT_VECTORS (68) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_PTRTOINT (69) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INTTOPTR (70) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_BITCAST (71) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FREEZE (72) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INTRINSIC_FPTRUNC_ROUND (73) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INTRINSIC_TRUNC (74) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INTRINSIC_ROUND (75) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INTRINSIC_LRINT (76) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INTRINSIC_ROUNDEVEN (77) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_READCYCLECOUNTER (78) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_LOAD (79) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SEXTLOAD (80) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ZEXTLOAD (81) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INDEXED_LOAD (82) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INDEXED_SEXTLOAD (83) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INDEXED_ZEXTLOAD (84) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_STORE (85) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INDEXED_STORE (86) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS (87) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMIC_CMPXCHG (88) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_XCHG (89) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_ADD (90) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_SUB (91) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_AND (92) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_NAND (93) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_OR (94) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_XOR (95) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_MAX (96) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_MIN (97) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_UMAX (98) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_UMIN (99) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_FADD (100) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_FSUB (101) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_FMAX (102) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_FMIN (103) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_UINC_WRAP (104) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ATOMICRMW_UDEC_WRAP (105) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FENCE (106) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_BRCOND (107) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_BRINDIRECT (108) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INVOKE_REGION_START (109) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INTRINSIC (110) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INTRINSIC_W_SIDE_EFFECTS (111) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ANYEXT (112) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_TRUNC (113) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_CONSTANT (114) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FCONSTANT (115) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VASTART (116) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VAARG (117) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SEXT (118) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SEXT_INREG (119) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ZEXT (120) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SHL (121) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_LSHR (122) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ASHR (123) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FSHL (124) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FSHR (125) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ROTR (126) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ROTL (127) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ICMP (128) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FCMP (129) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SELECT (130) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UADDO (131) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UADDE (132) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_USUBO (133) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_USUBE (134) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SADDO (135) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SADDE (136) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SSUBO (137) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SSUBE (138) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UMULO (139) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SMULO (140) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UMULH (141) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SMULH (142) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UADDSAT (143) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SADDSAT (144) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_USUBSAT (145) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SSUBSAT (146) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_USHLSAT (147) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SSHLSAT (148) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SMULFIX (149) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UMULFIX (150) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SMULFIXSAT (151) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UMULFIXSAT (152) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SDIVFIX (153) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UDIVFIX (154) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SDIVFIXSAT (155) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UDIVFIXSAT (156) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FADD (157) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FSUB (158) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FMUL (159) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FMA (160) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FMAD (161) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FDIV (162) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FREM (163) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FPOW (164) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FPOWI (165) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FEXP (166) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FEXP2 (167) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FLOG (168) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FLOG2 (169) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FLOG10 (170) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FNEG (171) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FPEXT (172) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FPTRUNC (173) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FPTOSI (174) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FPTOUI (175) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SITOFP (176) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UITOFP (177) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FABS (178) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FCOPYSIGN (179) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_IS_FPCLASS (180) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FCANONICALIZE (181) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FMINNUM (182) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FMAXNUM (183) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FMINNUM_IEEE (184) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FMAXNUM_IEEE (185) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FMINIMUM (186) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FMAXIMUM (187) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_PTR_ADD (188) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_PTRMASK (189) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SMIN (190) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SMAX (191) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UMIN (192) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UMAX (193) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ABS (194) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_LROUND (195) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_LLROUND (196) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_BR (197) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_BRJT (198) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_INSERT_VECTOR_ELT (199) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_EXTRACT_VECTOR_ELT (200) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SHUFFLE_VECTOR (201) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_CTTZ (202) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_CTTZ_ZERO_UNDEF (203) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_CTLZ (204) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_CTLZ_ZERO_UNDEF (205) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_CTPOP (206) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_BSWAP (207) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_BITREVERSE (208) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FCEIL (209) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FCOS (210) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FSIN (211) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FSQRT (212) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FFLOOR (213) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FRINT (214) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_FNEARBYINT (215) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_ADDRSPACE_CAST (216) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_BLOCK_ADDR (217) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_JUMP_TABLE (218) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_DYN_STACKALLOC (219) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_STRICT_FADD (220) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_STRICT_FSUB (221) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_STRICT_FMUL (222) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_STRICT_FDIV (223) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_STRICT_FREM (224) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_STRICT_FMA (225) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_STRICT_FSQRT (226) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_READ_REGISTER (227) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_WRITE_REGISTER (228) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_MEMCPY (229) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_MEMCPY_INLINE (230) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_MEMMOVE (231) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_MEMSET (232) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_BZERO (233) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_SEQ_FADD (234) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_SEQ_FMUL (235) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_FADD (236) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_FMUL (237) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_FMAX (238) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_FMIN (239) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_ADD (240) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_MUL (241) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_AND (242) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_OR (243) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_XOR (244) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_SMAX (245) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_SMIN (246) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_UMAX (247) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_VECREDUCE_UMIN (248) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_SBFX (249) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_G_UBFX (250) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_ABS (251) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_ADDSri (252) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_ADDSrr (253) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_ADDSrsi (254) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_ADDSrsr (255) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_ADJCALLSTACKDOWN (256) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_ADJCALLSTACKUP (257) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_ASRi (258) - ARM_INS_ASR - asr${s}${p} $Rd, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ASRr (259) - ARM_INS_ASR - asr${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { { { /* ARM_B (260) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BCCZi64 (261) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BCCi64 (262) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BLX_noip (263) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BLX_pred_noip (264) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BL_PUSHLR (265) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BMOVPCB_CALL (266) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BMOVPCRX_CALL (267) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BR_JTadd (268) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BR_JTm_i12 (269) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BR_JTm_rs (270) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BR_JTr (271) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_BX_CALL (272) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_CMP_SWAP_16 (273) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_CMP_SWAP_32 (274) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_CMP_SWAP_64 (275) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_CMP_SWAP_8 (276) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_CONSTPOOL_ENTRY (277) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_COPY_STRUCT_BYVAL_I32 (278) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_ITasm (279) - ARM_INS_IT - it$mask $cc */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { 0 } } + }, + { { { /* ARM_Int_eh_sjlj_dispatchsetup (280) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_Int_eh_sjlj_longjmp (281) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_Int_eh_sjlj_setjmp (282) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_Int_eh_sjlj_setjmp_nofp (283) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_Int_eh_sjlj_setup_dispatch (284) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_JUMPTABLE_ADDRS (285) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_JUMPTABLE_INSTS (286) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_JUMPTABLE_TBB (287) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_JUMPTABLE_TBH (288) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_LDMIA_RET (289) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_LDRBT_POST (290) - ARM_INS_LDRBT - ldrbt${q} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */ + { 0 } } + }, + { /* ARM_LDRConstPool (291) - ARM_INS_LDR - ldr${q} $Rt, $immediate */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* immediate */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */ + { 0 } } + }, + { /* ARM_LDRHTii (292) - ARM_INS_LDRHT - ldrht${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_LDRLIT_ga_abs (293) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_LDRLIT_ga_pcrel (294) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_LDRLIT_ga_pcrel_ldr (295) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_LDRSBTii (296) - ARM_INS_LDRSBT - ldrsbt${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRSHTii (297) - ARM_INS_LDRSHT - ldrsht${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRT_POST (298) - ARM_INS_LDRT - ldrt${q} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */ + { 0 } } + }, + { { { /* ARM_LEApcrel (299) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_LEApcrelJT (300) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_LOADDUAL (301) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_LSLi (302) - ARM_INS_LSL - lsl${s}${p} $Rd, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_LSLr (303) - ARM_INS_LSL - lsl${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_LSRi (304) - ARM_INS_LSR - lsr${s}${p} $Rd, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_LSRr (305) - ARM_INS_LSR - lsr${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { { { /* ARM_MEMCPY (306) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MLAv5 (307) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOVCCi (308) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOVCCi16 (309) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOVCCi32imm (310) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOVCCr (311) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOVCCsi (312) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOVCCsr (313) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOVPCRX (314) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOVTi16_ga_pcrel (315) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOV_ga_pcrel (316) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOV_ga_pcrel_ldr (317) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOVi16_ga_pcrel (318) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOVi32imm (319) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOVsra_flag (320) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MOVsrl_flag (321) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MQPRCopy (322) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MQQPRLoad (323) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MQQPRStore (324) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MQQQQPRLoad (325) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MQQQQPRStore (326) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MULv5 (327) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MVE_MEMCPYLOOPINST (328) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MVE_MEMSETLOOPINST (329) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_MVNCCi (330) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PICADD (331) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PICLDR (332) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PICLDRB (333) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PICLDRH (334) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PICLDRSB (335) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PICLDRSH (336) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PICSTR (337) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PICSTRB (338) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_PICSTRH (339) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_RORi (340) - ARM_INS_ROR - ror${s}${p} $Rd, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_RORr (341) - ARM_INS_ROR - ror${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { { { /* ARM_RRX (342) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_RRXi (343) - ARM_INS_RRX - rrx${s}${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { { { /* ARM_RSBSri (344) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_RSBSrsi (345) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_RSBSrsr (346) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SEH_EpilogEnd (347) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SEH_EpilogStart (348) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SEH_Nop (349) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SEH_Nop_Ret (350) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SEH_PrologEnd (351) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SEH_SaveFRegs (352) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SEH_SaveLR (353) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SEH_SaveRegs (354) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SEH_SaveRegs_Ret (355) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SEH_SaveSP (356) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SEH_StackAlloc (357) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SMLALv5 (358) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SMULLv5 (359) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SPACE (360) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_STOREDUAL (361) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_STRBT_POST (362) - ARM_INS_STRBT - strbt${q} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */ + { 0 } } + }, + { { { /* ARM_STRBi_preidx (363) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_STRBr_preidx (364) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_STRH_preidx (365) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_STRT_POST (366) - ARM_INS_STRT - strt${q} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */ + { 0 } } + }, + { { { /* ARM_STRi_preidx (367) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_STRr_preidx (368) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SUBS_PC_LR (369) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SUBSri (370) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SUBSrr (371) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SUBSrsi (372) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SUBSrsr (373) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SpeculationBarrierISBDSBEndBB (374) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_SpeculationBarrierSBEndBB (375) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_TAILJMPd (376) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_TAILJMPr (377) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_TAILJMPr4 (378) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_TCRETURNdi (379) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_TCRETURNri (380) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_TPsoft (381) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_UMLALv5 (382) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_UMULLv5 (383) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1LNdAsm_16 (384) - ARM_INS_VLD1 - vld1${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNdAsm_32 (385) - ARM_INS_VLD1 - vld1${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNdAsm_8 (386) - ARM_INS_VLD1 - vld1${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNdWB_fixed_Asm_16 (387) - ARM_INS_VLD1 - vld1${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNdWB_fixed_Asm_32 (388) - ARM_INS_VLD1 - vld1${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNdWB_fixed_Asm_8 (389) - ARM_INS_VLD1 - vld1${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNdWB_register_Asm_16 (390) - ARM_INS_VLD1 - vld1${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNdWB_register_Asm_32 (391) - ARM_INS_VLD1 - vld1${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNdWB_register_Asm_8 (392) - ARM_INS_VLD1 - vld1${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNdAsm_16 (393) - ARM_INS_VLD2 - vld2${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNdAsm_32 (394) - ARM_INS_VLD2 - vld2${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNdAsm_8 (395) - ARM_INS_VLD2 - vld2${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNdWB_fixed_Asm_16 (396) - ARM_INS_VLD2 - vld2${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNdWB_fixed_Asm_32 (397) - ARM_INS_VLD2 - vld2${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNdWB_fixed_Asm_8 (398) - ARM_INS_VLD2 - vld2${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNdWB_register_Asm_16 (399) - ARM_INS_VLD2 - vld2${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNdWB_register_Asm_32 (400) - ARM_INS_VLD2 - vld2${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNdWB_register_Asm_8 (401) - ARM_INS_VLD2 - vld2${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNqAsm_16 (402) - ARM_INS_VLD2 - vld2${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNqAsm_32 (403) - ARM_INS_VLD2 - vld2${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNqWB_fixed_Asm_16 (404) - ARM_INS_VLD2 - vld2${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNqWB_fixed_Asm_32 (405) - ARM_INS_VLD2 - vld2${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNqWB_register_Asm_16 (406) - ARM_INS_VLD2 - vld2${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNqWB_register_Asm_32 (407) - ARM_INS_VLD2 - vld2${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPdAsm_16 (408) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPdAsm_32 (409) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPdAsm_8 (410) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPdWB_fixed_Asm_16 (411) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPdWB_fixed_Asm_32 (412) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPdWB_fixed_Asm_8 (413) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPdWB_register_Asm_16 (414) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPdWB_register_Asm_32 (415) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPdWB_register_Asm_8 (416) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPqAsm_16 (417) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPqAsm_32 (418) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPqAsm_8 (419) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPqWB_fixed_Asm_16 (420) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPqWB_fixed_Asm_32 (421) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPqWB_fixed_Asm_8 (422) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPqWB_register_Asm_16 (423) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPqWB_register_Asm_32 (424) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPqWB_register_Asm_8 (425) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNdAsm_16 (426) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNdAsm_32 (427) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNdAsm_8 (428) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNdWB_fixed_Asm_16 (429) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNdWB_fixed_Asm_32 (430) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNdWB_fixed_Asm_8 (431) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNdWB_register_Asm_16 (432) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNdWB_register_Asm_32 (433) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNdWB_register_Asm_8 (434) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNqAsm_16 (435) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNqAsm_32 (436) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNqWB_fixed_Asm_16 (437) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNqWB_fixed_Asm_32 (438) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNqWB_register_Asm_16 (439) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNqWB_register_Asm_32 (440) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3dAsm_16 (441) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3dAsm_32 (442) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3dAsm_8 (443) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3dWB_fixed_Asm_16 (444) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3dWB_fixed_Asm_32 (445) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3dWB_fixed_Asm_8 (446) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3dWB_register_Asm_16 (447) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3dWB_register_Asm_32 (448) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3dWB_register_Asm_8 (449) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3qAsm_16 (450) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3qAsm_32 (451) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3qAsm_8 (452) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3qWB_fixed_Asm_16 (453) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3qWB_fixed_Asm_32 (454) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3qWB_fixed_Asm_8 (455) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3qWB_register_Asm_16 (456) - ARM_INS_VLD3 - vld3${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3qWB_register_Asm_32 (457) - ARM_INS_VLD3 - vld3${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3qWB_register_Asm_8 (458) - ARM_INS_VLD3 - vld3${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPdAsm_16 (459) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPdAsm_32 (460) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPdAsm_8 (461) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPdWB_fixed_Asm_16 (462) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPdWB_fixed_Asm_32 (463) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPdWB_fixed_Asm_8 (464) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPdWB_register_Asm_16 (465) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPdWB_register_Asm_32 (466) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPdWB_register_Asm_8 (467) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPqAsm_16 (468) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPqAsm_32 (469) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPqAsm_8 (470) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPqWB_fixed_Asm_16 (471) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPqWB_fixed_Asm_32 (472) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPqWB_fixed_Asm_8 (473) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPqWB_register_Asm_16 (474) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPqWB_register_Asm_32 (475) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPqWB_register_Asm_8 (476) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNdAsm_16 (477) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNdAsm_32 (478) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNdAsm_8 (479) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNdWB_fixed_Asm_16 (480) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNdWB_fixed_Asm_32 (481) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNdWB_fixed_Asm_8 (482) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNdWB_register_Asm_16 (483) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNdWB_register_Asm_32 (484) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNdWB_register_Asm_8 (485) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNqAsm_16 (486) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNqAsm_32 (487) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNqWB_fixed_Asm_16 (488) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNqWB_fixed_Asm_32 (489) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNqWB_register_Asm_16 (490) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNqWB_register_Asm_32 (491) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4dAsm_16 (492) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4dAsm_32 (493) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4dAsm_8 (494) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4dWB_fixed_Asm_16 (495) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4dWB_fixed_Asm_32 (496) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4dWB_fixed_Asm_8 (497) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4dWB_register_Asm_16 (498) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4dWB_register_Asm_32 (499) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4dWB_register_Asm_8 (500) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4qAsm_16 (501) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4qAsm_32 (502) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4qAsm_8 (503) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4qWB_fixed_Asm_16 (504) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4qWB_fixed_Asm_32 (505) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4qWB_fixed_Asm_8 (506) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4qWB_register_Asm_16 (507) - ARM_INS_VLD4 - vld4${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4qWB_register_Asm_32 (508) - ARM_INS_VLD4 - vld4${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4qWB_register_Asm_8 (509) - ARM_INS_VLD4 - vld4${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VMOVD0 (510) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VMOVDcc (511) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VMOVHcc (512) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VMOVQ0 (513) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VMOVScc (514) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1LNdAsm_16 (515) - ARM_INS_VST1 - vst1${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNdAsm_32 (516) - ARM_INS_VST1 - vst1${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNdAsm_8 (517) - ARM_INS_VST1 - vst1${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNdWB_fixed_Asm_16 (518) - ARM_INS_VST1 - vst1${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNdWB_fixed_Asm_32 (519) - ARM_INS_VST1 - vst1${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNdWB_fixed_Asm_8 (520) - ARM_INS_VST1 - vst1${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNdWB_register_Asm_16 (521) - ARM_INS_VST1 - vst1${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNdWB_register_Asm_32 (522) - ARM_INS_VST1 - vst1${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNdWB_register_Asm_8 (523) - ARM_INS_VST1 - vst1${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNdAsm_16 (524) - ARM_INS_VST2 - vst2${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNdAsm_32 (525) - ARM_INS_VST2 - vst2${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNdAsm_8 (526) - ARM_INS_VST2 - vst2${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNdWB_fixed_Asm_16 (527) - ARM_INS_VST2 - vst2${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNdWB_fixed_Asm_32 (528) - ARM_INS_VST2 - vst2${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNdWB_fixed_Asm_8 (529) - ARM_INS_VST2 - vst2${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNdWB_register_Asm_16 (530) - ARM_INS_VST2 - vst2${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNdWB_register_Asm_32 (531) - ARM_INS_VST2 - vst2${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNdWB_register_Asm_8 (532) - ARM_INS_VST2 - vst2${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNqAsm_16 (533) - ARM_INS_VST2 - vst2${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNqAsm_32 (534) - ARM_INS_VST2 - vst2${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNqWB_fixed_Asm_16 (535) - ARM_INS_VST2 - vst2${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNqWB_fixed_Asm_32 (536) - ARM_INS_VST2 - vst2${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNqWB_register_Asm_16 (537) - ARM_INS_VST2 - vst2${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNqWB_register_Asm_32 (538) - ARM_INS_VST2 - vst2${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNdAsm_16 (539) - ARM_INS_VST3 - vst3${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNdAsm_32 (540) - ARM_INS_VST3 - vst3${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNdAsm_8 (541) - ARM_INS_VST3 - vst3${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNdWB_fixed_Asm_16 (542) - ARM_INS_VST3 - vst3${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNdWB_fixed_Asm_32 (543) - ARM_INS_VST3 - vst3${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNdWB_fixed_Asm_8 (544) - ARM_INS_VST3 - vst3${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNdWB_register_Asm_16 (545) - ARM_INS_VST3 - vst3${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNdWB_register_Asm_32 (546) - ARM_INS_VST3 - vst3${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNdWB_register_Asm_8 (547) - ARM_INS_VST3 - vst3${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNqAsm_16 (548) - ARM_INS_VST3 - vst3${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNqAsm_32 (549) - ARM_INS_VST3 - vst3${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNqWB_fixed_Asm_16 (550) - ARM_INS_VST3 - vst3${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNqWB_fixed_Asm_32 (551) - ARM_INS_VST3 - vst3${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNqWB_register_Asm_16 (552) - ARM_INS_VST3 - vst3${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNqWB_register_Asm_32 (553) - ARM_INS_VST3 - vst3${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3dAsm_16 (554) - ARM_INS_VST3 - vst3${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3dAsm_32 (555) - ARM_INS_VST3 - vst3${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3dAsm_8 (556) - ARM_INS_VST3 - vst3${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3dWB_fixed_Asm_16 (557) - ARM_INS_VST3 - vst3${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3dWB_fixed_Asm_32 (558) - ARM_INS_VST3 - vst3${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3dWB_fixed_Asm_8 (559) - ARM_INS_VST3 - vst3${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3dWB_register_Asm_16 (560) - ARM_INS_VST3 - vst3${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3dWB_register_Asm_32 (561) - ARM_INS_VST3 - vst3${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3dWB_register_Asm_8 (562) - ARM_INS_VST3 - vst3${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3qAsm_16 (563) - ARM_INS_VST3 - vst3${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3qAsm_32 (564) - ARM_INS_VST3 - vst3${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3qAsm_8 (565) - ARM_INS_VST3 - vst3${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3qWB_fixed_Asm_16 (566) - ARM_INS_VST3 - vst3${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3qWB_fixed_Asm_32 (567) - ARM_INS_VST3 - vst3${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3qWB_fixed_Asm_8 (568) - ARM_INS_VST3 - vst3${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3qWB_register_Asm_16 (569) - ARM_INS_VST3 - vst3${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3qWB_register_Asm_32 (570) - ARM_INS_VST3 - vst3${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3qWB_register_Asm_8 (571) - ARM_INS_VST3 - vst3${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNdAsm_16 (572) - ARM_INS_VST4 - vst4${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNdAsm_32 (573) - ARM_INS_VST4 - vst4${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNdAsm_8 (574) - ARM_INS_VST4 - vst4${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNdWB_fixed_Asm_16 (575) - ARM_INS_VST4 - vst4${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNdWB_fixed_Asm_32 (576) - ARM_INS_VST4 - vst4${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNdWB_fixed_Asm_8 (577) - ARM_INS_VST4 - vst4${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNdWB_register_Asm_16 (578) - ARM_INS_VST4 - vst4${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNdWB_register_Asm_32 (579) - ARM_INS_VST4 - vst4${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNdWB_register_Asm_8 (580) - ARM_INS_VST4 - vst4${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNqAsm_16 (581) - ARM_INS_VST4 - vst4${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNqAsm_32 (582) - ARM_INS_VST4 - vst4${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNqWB_fixed_Asm_16 (583) - ARM_INS_VST4 - vst4${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNqWB_fixed_Asm_32 (584) - ARM_INS_VST4 - vst4${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNqWB_register_Asm_16 (585) - ARM_INS_VST4 - vst4${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNqWB_register_Asm_32 (586) - ARM_INS_VST4 - vst4${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list - DPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4dAsm_16 (587) - ARM_INS_VST4 - vst4${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4dAsm_32 (588) - ARM_INS_VST4 - vst4${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4dAsm_8 (589) - ARM_INS_VST4 - vst4${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4dWB_fixed_Asm_16 (590) - ARM_INS_VST4 - vst4${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4dWB_fixed_Asm_32 (591) - ARM_INS_VST4 - vst4${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4dWB_fixed_Asm_8 (592) - ARM_INS_VST4 - vst4${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4dWB_register_Asm_16 (593) - ARM_INS_VST4 - vst4${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4dWB_register_Asm_32 (594) - ARM_INS_VST4 - vst4${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4dWB_register_Asm_8 (595) - ARM_INS_VST4 - vst4${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4qAsm_16 (596) - ARM_INS_VST4 - vst4${p}.16 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4qAsm_32 (597) - ARM_INS_VST4 - vst4${p}.32 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4qAsm_8 (598) - ARM_INS_VST4 - vst4${p}.8 $list, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4qWB_fixed_Asm_16 (599) - ARM_INS_VST4 - vst4${p}.16 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4qWB_fixed_Asm_32 (600) - ARM_INS_VST4 - vst4${p}.32 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4qWB_fixed_Asm_8 (601) - ARM_INS_VST4 - vst4${p}.8 $list, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4qWB_register_Asm_16 (602) - ARM_INS_VST4 - vst4${p}.16 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4qWB_register_Asm_32 (603) - ARM_INS_VST4 - vst4${p}.32 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4qWB_register_Asm_8 (604) - ARM_INS_VST4 - vst4${p}.8 $list, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* list */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_WIN__CHKSTK (605) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_WIN__DBZCHK (606) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2ABS (607) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2ADDSri (608) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2ADDSrr (609) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2ADDSrs (610) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2BF_LabelPseudo (611) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2BR_JT (612) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2CALL_BTI (613) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2DoLoopStart (614) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2DoLoopStartTP (615) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2LDMIA_RET (616) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_t2LDRBpcrel (617) - ARM_INS_LDRB - ldrb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRConstPool (618) - ARM_INS_LDR - ldr${p} $Rt, $immediate */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* immediate */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRHpcrel (619) - ARM_INS_LDRH - ldrh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_t2LDRLIT_ga_pcrel (620) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_t2LDRSBpcrel (621) - ARM_INS_LDRSB - ldrsb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSHpcrel (622) - ARM_INS_LDRSH - ldrsh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDR_POST_imm (623) - ARM_INS_LDR - ldr${p}.w $Rt, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDR_PRE_imm (624) - ARM_INS_LDR - ldr${p}.w $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_t2LDRpci_pic (625) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_t2LDRpcrel (626) - ARM_INS_LDR - ldr${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_t2LEApcrel (627) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2LEApcrelJT (628) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2LoopDec (629) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2LoopEnd (630) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2LoopEndDec (631) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2MOVCCasr (632) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2MOVCCi (633) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2MOVCCi16 (634) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2MOVCCi32imm (635) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2MOVCClsl (636) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2MOVCClsr (637) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2MOVCCr (638) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2MOVCCror (639) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_t2MOVSsi (640) - ARM_INS_MOVS - movs${p} $Rd, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MOVSsr (641) - ARM_INS_MOVS - movs${p} $Rd, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_t2MOVTi16_ga_pcrel (642) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2MOV_ga_pcrel (643) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2MOVi16_ga_pcrel (644) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2MOVi32imm (645) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_t2MOVsi (646) - ARM_INS_MOV - mov${p} $Rd, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MOVsr (647) - ARM_INS_MOV - mov${p} $Rd, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_t2MVNCCi (648) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2RSBSri (649) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2RSBSrs (650) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2STRB_preidx (651) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2STRH_preidx (652) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_t2STR_POST_imm (653) - ARM_INS_STR - str${p}.w $Rt, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STR_PRE_imm (654) - ARM_INS_STR - str${p}.w $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_t2STR_preidx (655) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2SUBSri (656) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2SUBSrr (657) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2SUBSrs (658) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2SpeculationBarrierISBDSBEndBB (659) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2SpeculationBarrierSBEndBB (660) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2TBB_JT (661) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2TBH_JT (662) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2WhileLoopSetup (663) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2WhileLoopStart (664) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2WhileLoopStartLR (665) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2WhileLoopStartTP (666) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tADCS (667) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tADDSi3 (668) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tADDSi8 (669) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tADDSrr (670) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tADDframe (671) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tADJCALLSTACKDOWN (672) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tADJCALLSTACKUP (673) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tBLXNS_CALL (674) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tBLXr_noip (675) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tBL_PUSHLR (676) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tBRIND (677) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tBR_JTr (678) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tBXNS_RET (679) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tBX_CALL (680) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tBX_RET (681) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tBX_RET_vararg (682) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tBfar (683) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tCMP_SWAP_16 (684) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tCMP_SWAP_32 (685) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tCMP_SWAP_8 (686) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tLDMIA_UPD (687) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_tLDRConstPool (688) - ARM_INS_LDR - ldr${p} $Rt, $immediate */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* immediate */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_tLDRLIT_ga_abs (689) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tLDRLIT_ga_pcrel (690) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tLDR_postidx (691) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tLDRpci_pic (692) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tLEApcrel (693) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tLEApcrelJT (694) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tLSLSri (695) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tMOVCCr_pseudo (696) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tPOP_RET (697) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tRSBS (698) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tSBCS (699) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tSUBSi3 (700) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tSUBSi8 (701) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tSUBSrr (702) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tTAILJMPd (703) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tTAILJMPdND (704) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tTAILJMPr (705) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tTBB_JT (706) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tTBH_JT (707) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tTPsoft (708) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_ADCri (709) - ARM_INS_ADC - adc${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ADCrr (710) - ARM_INS_ADC - adc${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ADCrsi (711) - ARM_INS_ADC - adc${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ADCrsr (712) - ARM_INS_ADC - adc${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ADDri (713) - ARM_INS_ADD - add${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ADDrr (714) - ARM_INS_ADD - add${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ADDrsi (715) - ARM_INS_ADD - add${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ADDrsr (716) - ARM_INS_ADD - add${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ADR (717) - ARM_INS_ADR - adr${p} $Rd, $label */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* label */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_AESD (718) - ARM_INS_AESD - aesd.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_AESE (719) - ARM_INS_AESE - aese.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_AESIMC (720) - ARM_INS_AESIMC - aesimc.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_AESMC (721) - ARM_INS_AESMC - aesmc.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_ANDri (722) - ARM_INS_AND - and${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ANDrr (723) - ARM_INS_AND - and${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ANDrsi (724) - ARM_INS_AND - and${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ANDrsr (725) - ARM_INS_AND - and${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_BF16VDOTI_VDOTD (726) - ARM_INS_VDOT - vdot.bf16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { 0 } } + }, + { /* ARM_BF16VDOTI_VDOTQ (727) - ARM_INS_VDOT - vdot.bf16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { 0 } } + }, + { /* ARM_BF16VDOTS_VDOTD (728) - ARM_INS_VDOT - vdot.bf16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_BF16VDOTS_VDOTQ (729) - ARM_INS_VDOT - vdot.bf16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_BF16_VCVT (730) - ARM_INS_VCVT - vcvt${p}.bf16.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_BF16_VCVTB (731) - ARM_INS_VCVTB - vcvtb${p}.bf16.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_BF16_VCVTT (732) - ARM_INS_VCVTT - vcvtt${p}.bf16.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_BFC (733) - ARM_INS_BFC - bfc${p} $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_BFI (734) - ARM_INS_BFI - bfi${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_BICri (735) - ARM_INS_BIC - bic${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_BICrr (736) - ARM_INS_BIC - bic${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_BICrsi (737) - ARM_INS_BIC - bic${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_BICrsr (738) - ARM_INS_BIC - bic${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_BKPT (739) - ARM_INS_BKPT - bkpt $val */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { 0 } } + }, + { /* ARM_BL (740) - ARM_INS_BL - bl $func */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */ + { 0 } } + }, + { /* ARM_BLX (741) - ARM_INS_BLX - blx $func */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */ + { 0 } } + }, + { /* ARM_BLX_pred (742) - ARM_INS_BLX - blx${p} $func */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_BLXi (743) - ARM_INS_BLX - blx $target */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } } + }, + { /* ARM_BL_pred (744) - ARM_INS_BL - bl${p} $func */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_BX (745) - ARM_INS_BX - bx $dst */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { 0 } } + }, + { /* ARM_BXJ (746) - ARM_INS_BXJ - bxj${p} $func */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_BX_RET (747) - ARM_INS_BX - bx${p} lr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_BX_pred (748) - ARM_INS_BX - bx${p} $dst */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_Bcc (749) - ARM_INS_B - b${p} $target */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CDE_CX1 (750) - ARM_INS_CX1 - cx1 $coproc, $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_CX1A (751) - ARM_INS_CX1A - cx1a${p} $coproc, $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CDE_CX1D (752) - ARM_INS_CX1D - cx1d $coproc, $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_CX1DA (753) - ARM_INS_CX1DA - cx1da${p} $coproc, $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CDE_CX2 (754) - ARM_INS_CX2 - cx2 $coproc, $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_CX2A (755) - ARM_INS_CX2A - cx2a${p} $coproc, $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CDE_CX2D (756) - ARM_INS_CX2D - cx2d $coproc, $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_CX2DA (757) - ARM_INS_CX2DA - cx2da${p} $coproc, $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CDE_CX3 (758) - ARM_INS_CX3 - cx3 $coproc, $Rd, $Rn, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_CX3A (759) - ARM_INS_CX3A - cx3a${p} $coproc, $Rd, $Rn, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CDE_CX3D (760) - ARM_INS_CX3D - cx3d $coproc, $Rd, $Rn, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_CX3DA (761) - ARM_INS_CX3DA - cx3da${p} $coproc, $Rd, $Rn, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CDE_VCX1A_fpdp (762) - ARM_INS_VCX1A - vcx1a $coproc, $Vd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_VCX1A_fpsp (763) - ARM_INS_VCX1A - vcx1a $coproc, $Vd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_VCX1A_vec (764) - ARM_INS_VCX1A - vcx1a${vp} $coproc, $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_CDE_VCX1_fpdp (765) - ARM_INS_VCX1 - vcx1 $coproc, $Vd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_VCX1_fpsp (766) - ARM_INS_VCX1 - vcx1 $coproc, $Vd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_VCX1_vec (767) - ARM_INS_VCX1 - vcx1${vp} $coproc, $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_CDE_VCX2A_fpdp (768) - ARM_INS_VCX2A - vcx2a $coproc, $Vd, $Vm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_VCX2A_fpsp (769) - ARM_INS_VCX2A - vcx2a $coproc, $Vd, $Vm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_VCX2A_vec (770) - ARM_INS_VCX2A - vcx2a${vp} $coproc, $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_CDE_VCX2_fpdp (771) - ARM_INS_VCX2 - vcx2 $coproc, $Vd, $Vm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_VCX2_fpsp (772) - ARM_INS_VCX2 - vcx2 $coproc, $Vd, $Vm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_VCX2_vec (773) - ARM_INS_VCX2 - vcx2${vp} $coproc, $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_CDE_VCX3A_fpdp (774) - ARM_INS_VCX3A - vcx3a $coproc, $Vd, $Vn, $Vm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_VCX3A_fpsp (775) - ARM_INS_VCX3A - vcx3a $coproc, $Vd, $Vn, $Vm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_VCX3A_vec (776) - ARM_INS_VCX3A - vcx3a${vp} $coproc, $Qd, $Qn, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_CDE_VCX3_fpdp (777) - ARM_INS_VCX3 - vcx3 $coproc, $Vd, $Vn, $Vm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_VCX3_fpsp (778) - ARM_INS_VCX3 - vcx3 $coproc, $Vd, $Vn, $Vm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_CDE_VCX3_vec (779) - ARM_INS_VCX3 - vcx3${vp} $coproc, $Qd, $Qn, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_CDP (780) - ARM_INS_CDP - cdp${p} $cop, $opc1, $CRd, $CRn, $CRm, $opc2 */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CDP2 (781) - ARM_INS_CDP2 - cdp2 $cop, $opc1, $CRd, $CRn, $CRm, $opc2 */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */ + { 0 } } + }, + { /* ARM_CLREX (782) - ARM_INS_CLREX - clrex */ + { { 0 } } + }, + { /* ARM_CLZ (783) - ARM_INS_CLZ - clz${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CMNri (784) - ARM_INS_CMN - cmn${p} $Rn, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CMNzrr (785) - ARM_INS_CMN - cmn${p} $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CMNzrsi (786) - ARM_INS_CMN - cmn${p} $Rn, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CMNzrsr (787) - ARM_INS_CMN - cmn${p} $Rn, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CMPri (788) - ARM_INS_CMP - cmp${p} $Rn, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CMPrr (789) - ARM_INS_CMP - cmp${p} $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CMPrsi (790) - ARM_INS_CMP - cmp${p} $Rn, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CMPrsr (791) - ARM_INS_CMP - cmp${p} $Rn, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_CPS1p (792) - ARM_INS_CPS - cps $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { 0 } } + }, + { /* ARM_CPS2p (793) - ARM_INS_CPS - cps$imod $iflags */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imod */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* iflags */ + { 0 } } + }, + { /* ARM_CPS3p (794) - ARM_INS_CPS - cps$imod $iflags, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imod */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* iflags */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { 0 } } + }, + { /* ARM_CRC32B (795) - ARM_INS_CRC32B - crc32b $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_CRC32CB (796) - ARM_INS_CRC32CB - crc32cb $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_CRC32CH (797) - ARM_INS_CRC32CH - crc32ch $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_CRC32CW (798) - ARM_INS_CRC32CW - crc32cw $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_CRC32H (799) - ARM_INS_CRC32H - crc32h $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_CRC32W (800) - ARM_INS_CRC32W - crc32w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_DBG (801) - ARM_INS_DBG - dbg${p} $opt */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_DMB (802) - ARM_INS_DMB - dmb $opt */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */ + { 0 } } + }, + { /* ARM_DSB (803) - ARM_INS_DSB - dsb $opt */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */ + { 0 } } + }, + { /* ARM_EORri (804) - ARM_INS_EOR - eor${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_EORrr (805) - ARM_INS_EOR - eor${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_EORrsi (806) - ARM_INS_EOR - eor${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_EORrsr (807) - ARM_INS_EOR - eor${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ERET (808) - ARM_INS_ERET - eret${p} */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_FCONSTD (809) - ARM_INS_VMOV - vmov${p}.f64 $Dd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_FP, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_FCONSTH (810) - ARM_INS_VMOV - vmov${p}.f16 $Sd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_FP, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_FCONSTS (811) - ARM_INS_VMOV - vmov${p}.f32 $Sd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_FP, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_FLDMXDB_UPD (812) - ARM_INS_FLDMDBX - fldmdbx${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_FLDMXIA (813) - ARM_INS_FLDMIAX - fldmiax${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_FLDMXIA_UPD (814) - ARM_INS_FLDMIAX - fldmiax${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_FMSTAT (815) - ARM_INS_VMRS - vmrs${p} APSR_nzcv, fpscr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_FSTMXDB_UPD (816) - ARM_INS_FSTMDBX - fstmdbx${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_FSTMXIA (817) - ARM_INS_FSTMIAX - fstmiax${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_FSTMXIA_UPD (818) - ARM_INS_FSTMIAX - fstmiax${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_HINT (819) - ARM_INS_HINT - hint${p} $imm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_HLT (820) - ARM_INS_HLT - hlt $val */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { 0 } } + }, + { /* ARM_HVC (821) - ARM_INS_HVC - hvc $imm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_ISB (822) - ARM_INS_ISB - isb $opt */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */ + { 0 } } + }, + { /* ARM_LDA (823) - ARM_INS_LDA - lda${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDAB (824) - ARM_INS_LDAB - ldab${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDAEX (825) - ARM_INS_LDAEX - ldaex${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDAEXB (826) - ARM_INS_LDAEXB - ldaexb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDAEXD (827) - ARM_INS_LDAEXD - ldaexd${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDAEXH (828) - ARM_INS_LDAEXH - ldaexh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDAH (829) - ARM_INS_LDAH - ldah${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDC2L_OFFSET (830) - ARM_INS_LDC2L - ldc2l $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { 0 } } + }, + { /* ARM_LDC2L_OPTION (831) - ARM_INS_LDC2L - ldc2l $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { 0 } } + }, + { /* ARM_LDC2L_POST (832) - ARM_INS_LDC2L - ldc2l $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { 0 } } + }, + { /* ARM_LDC2L_PRE (833) - ARM_INS_LDC2L - ldc2l $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { 0 } } + }, + { /* ARM_LDC2_OFFSET (834) - ARM_INS_LDC2 - ldc2 $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { 0 } } + }, + { /* ARM_LDC2_OPTION (835) - ARM_INS_LDC2 - ldc2 $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { 0 } } + }, + { /* ARM_LDC2_POST (836) - ARM_INS_LDC2 - ldc2 $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { 0 } } + }, + { /* ARM_LDC2_PRE (837) - ARM_INS_LDC2 - ldc2 $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { 0 } } + }, + { /* ARM_LDCL_OFFSET (838) - ARM_INS_LDCL - ldcl${p} $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDCL_OPTION (839) - ARM_INS_LDCL - ldcl${p} $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDCL_POST (840) - ARM_INS_LDCL - ldcl${p} $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDCL_PRE (841) - ARM_INS_LDCL - ldcl${p} $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDC_OFFSET (842) - ARM_INS_LDC - ldc${p} $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDC_OPTION (843) - ARM_INS_LDC - ldc${p} $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDC_POST (844) - ARM_INS_LDC - ldc${p} $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDC_PRE (845) - ARM_INS_LDC - ldc${p} $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDMDA (846) - ARM_INS_LDMDA - ldmda${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_LDMDA_UPD (847) - ARM_INS_LDMDA - ldmda${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_LDMDB (848) - ARM_INS_LDMDB - ldmdb${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_LDMDB_UPD (849) - ARM_INS_LDMDB - ldmdb${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_LDMIA (850) - ARM_INS_LDM - ldm${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_LDMIA_UPD (851) - ARM_INS_LDM - ldm${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_LDMIB (852) - ARM_INS_LDMIB - ldmib${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_LDMIB_UPD (853) - ARM_INS_LDMIB - ldmib${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_LDRBT_POST_IMM (854) - ARM_INS_LDRBT - ldrbt${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRBT_POST_REG (855) - ARM_INS_LDRBT - ldrbt${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRB_POST_IMM (856) - ARM_INS_LDRB - ldrb${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRB_POST_REG (857) - ARM_INS_LDRB - ldrb${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRB_PRE_IMM (858) - ARM_INS_LDRB - ldrb${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRB_PRE_REG (859) - ARM_INS_LDRB - ldrb${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRBi12 (860) - ARM_INS_LDRB - ldrb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRBrs (861) - ARM_INS_LDRB - ldrb${p} $Rt, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRD (862) - ARM_INS_LDRD - ldrd${p} $Rt, $Rt2, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRD_POST (863) - ARM_INS_LDRD - ldrd${p} $Rt, $Rt2, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRD_PRE (864) - ARM_INS_LDRD - ldrd${p} $Rt, $Rt2, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDREX (865) - ARM_INS_LDREX - ldrex${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDREXB (866) - ARM_INS_LDREXB - ldrexb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDREXD (867) - ARM_INS_LDREXD - ldrexd${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDREXH (868) - ARM_INS_LDREXH - ldrexh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRH (869) - ARM_INS_LDRH - ldrh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRHTi (870) - ARM_INS_LDRHT - ldrht${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRHTr (871) - ARM_INS_LDRHT - ldrht${p} $Rt, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRH_POST (872) - ARM_INS_LDRH - ldrh${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRH_PRE (873) - ARM_INS_LDRH - ldrh${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRSB (874) - ARM_INS_LDRSB - ldrsb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRSBTi (875) - ARM_INS_LDRSBT - ldrsbt${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRSBTr (876) - ARM_INS_LDRSBT - ldrsbt${p} $Rt, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRSB_POST (877) - ARM_INS_LDRSB - ldrsb${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRSB_PRE (878) - ARM_INS_LDRSB - ldrsb${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRSH (879) - ARM_INS_LDRSH - ldrsh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRSHTi (880) - ARM_INS_LDRSHT - ldrsht${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRSHTr (881) - ARM_INS_LDRSHT - ldrsht${p} $Rt, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRSH_POST (882) - ARM_INS_LDRSH - ldrsh${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRSH_PRE (883) - ARM_INS_LDRSH - ldrsh${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRT_POST_IMM (884) - ARM_INS_LDRT - ldrt${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRT_POST_REG (885) - ARM_INS_LDRT - ldrt${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDR_POST_IMM (886) - ARM_INS_LDR - ldr${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDR_POST_REG (887) - ARM_INS_LDR - ldr${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDR_PRE_IMM (888) - ARM_INS_LDR - ldr${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDR_PRE_REG (889) - ARM_INS_LDR - ldr${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_LDRcp (890) - ARM_INS_INVALID - ldr${p} $Rt, $addr */ + 0 } } }, + { /* ARM_LDRi12 (891) - ARM_INS_LDR - ldr${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_LDRrs (892) - ARM_INS_LDR - ldr${p} $Rt, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MCR (893) - ARM_INS_MCR - mcr${p} $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MCR2 (894) - ARM_INS_MCR2 - mcr2 $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */ + { 0 } } + }, + { /* ARM_MCRR (895) - ARM_INS_MCRR - mcrr${p} $cop, $opc1, $Rt, $Rt2, $CRm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MCRR2 (896) - ARM_INS_MCRR2 - mcrr2 $cop, $opc1, $Rt, $Rt2, $CRm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { 0 } } + }, + { /* ARM_MLA (897) - ARM_INS_MLA - mla${s}${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_MLS (898) - ARM_INS_MLS - mls${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MOVPCLR (899) - ARM_INS_MOV - mov${p} pc, lr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MOVTi16 (900) - ARM_INS_MOVT - movt${p} $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MOVi (901) - ARM_INS_MOV - mov${s}${p} $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_MOVi16 (902) - ARM_INS_MOVW - movw${p} $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MOVr (903) - ARM_INS_MOV - mov${s}${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_MOVr_TC (904) - ARM_INS_MOV - mov${s}${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_MOVsi (905) - ARM_INS_MOV - mov${s}${p} $Rd, $src */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_MOVsr (906) - ARM_INS_MOV - mov${s}${p} $Rd, $src */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_MRC (907) - ARM_INS_MRC - mrc${p} $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MRC2 (908) - ARM_INS_MRC2 - mrc2 $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */ + { 0 } } + }, + { /* ARM_MRRC (909) - ARM_INS_MRRC - mrrc${p} $cop, $opc1, $Rt, $Rt2, $CRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MRRC2 (910) - ARM_INS_MRRC2 - mrrc2 $cop, $opc1, $Rt, $Rt2, $CRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { 0 } } + }, + { /* ARM_MRS (911) - ARM_INS_MRS - mrs${p} $Rd, apsr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MRSbanked (912) - ARM_INS_MRS - mrs${p} $Rd, $banked */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* banked */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MRSsys (913) - ARM_INS_MRS - mrs${p} $Rd, spsr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MSR (914) - ARM_INS_MSR - msr${p} $mask, $Rn */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MSRbanked (915) - ARM_INS_MSR - msr${p} $banked, $Rn */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* banked */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MSRi (916) - ARM_INS_MSR - msr${p} $mask, $imm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MUL (917) - ARM_INS_MUL - mul${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_MVE_ASRLi (918) - ARM_INS_ASRL - asrl${p} $RdaLo, $RdaHi, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_ASRLr (919) - ARM_INS_ASRL - asrl${p} $RdaLo, $RdaHi, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_DLSTP_16 (920) - ARM_INS_DLSTP - dlstp.16 $LR, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_MVE_DLSTP_32 (921) - ARM_INS_DLSTP - dlstp.32 $LR, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_MVE_DLSTP_64 (922) - ARM_INS_DLSTP - dlstp.64 $LR, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_MVE_DLSTP_8 (923) - ARM_INS_DLSTP - dlstp.8 $LR, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_MVE_LCTP (924) - ARM_INS_LCTP - lctp${p} */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_LETP (925) - ARM_INS_LETP - letp $LRin, $label */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LRout */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LRin */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */ + { 0 } } + }, + { /* ARM_MVE_LSLLi (926) - ARM_INS_LSLL - lsll${p} $RdaLo, $RdaHi, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_LSLLr (927) - ARM_INS_LSLL - lsll${p} $RdaLo, $RdaHi, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_LSRL (928) - ARM_INS_LSRL - lsrl${p} $RdaLo, $RdaHi, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_SQRSHR (929) - ARM_INS_SQRSHR - sqrshr${p} $RdaSrc, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_SQRSHRL (930) - ARM_INS_SQRSHRL - sqrshrl${p} $RdaLo, $RdaHi, $sat, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_SQSHL (931) - ARM_INS_SQSHL - sqshl${p} $RdaSrc, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_SQSHLL (932) - ARM_INS_SQSHLL - sqshll${p} $RdaLo, $RdaHi, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_SRSHR (933) - ARM_INS_SRSHR - srshr${p} $RdaSrc, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_SRSHRL (934) - ARM_INS_SRSHRL - srshrl${p} $RdaLo, $RdaHi, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_UQRSHL (935) - ARM_INS_UQRSHL - uqrshl${p} $RdaSrc, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_UQRSHLL (936) - ARM_INS_UQRSHLL - uqrshll${p} $RdaLo, $RdaHi, $sat, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_UQSHL (937) - ARM_INS_UQSHL - uqshl${p} $RdaSrc, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_UQSHLL (938) - ARM_INS_UQSHLL - uqshll${p} $RdaLo, $RdaHi, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_URSHR (939) - ARM_INS_URSHR - urshr${p} $RdaSrc, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_URSHRL (940) - ARM_INS_URSHRL - urshrl${p} $RdaLo, $RdaHi, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_VABAVs16 (941) - ARM_INS_VABAV - vabav${vp}.s16 $Rda, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VABAVs32 (942) - ARM_INS_VABAV - vabav${vp}.s32 $Rda, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VABAVs8 (943) - ARM_INS_VABAV - vabav${vp}.s8 $Rda, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VABAVu16 (944) - ARM_INS_VABAV - vabav${vp}.u16 $Rda, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VABAVu32 (945) - ARM_INS_VABAV - vabav${vp}.u32 $Rda, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VABAVu8 (946) - ARM_INS_VABAV - vabav${vp}.u8 $Rda, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VABDf16 (947) - ARM_INS_VABD - vabd${vp}.f16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VABDf32 (948) - ARM_INS_VABD - vabd${vp}.f32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VABDs16 (949) - ARM_INS_VABD - vabd${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VABDs32 (950) - ARM_INS_VABD - vabd${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VABDs8 (951) - ARM_INS_VABD - vabd${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VABDu16 (952) - ARM_INS_VABD - vabd${vp}.u16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VABDu32 (953) - ARM_INS_VABD - vabd${vp}.u32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VABDu8 (954) - ARM_INS_VABD - vabd${vp}.u8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VABSf16 (955) - ARM_INS_VABS - vabs${vp}.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VABSf32 (956) - ARM_INS_VABS - vabs${vp}.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VABSs16 (957) - ARM_INS_VABS - vabs${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VABSs32 (958) - ARM_INS_VABS - vabs${vp}.s32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VABSs8 (959) - ARM_INS_VABS - vabs${vp}.s8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VADC (960) - ARM_INS_VADC - vadc${vp}.i32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* carryout */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* carryin */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VADCI (961) - ARM_INS_VADCI - vadci${vp}.i32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* carryout */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VADDLVs32acc (962) - ARM_INS_VADDLVA - vaddlva${vp}.s32 $RdaLo, $RdaHi, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDLVs32no_acc (963) - ARM_INS_VADDLV - vaddlv${vp}.s32 $RdaLo, $RdaHi, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDLVu32acc (964) - ARM_INS_VADDLVA - vaddlva${vp}.u32 $RdaLo, $RdaHi, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDLVu32no_acc (965) - ARM_INS_VADDLV - vaddlv${vp}.u32 $RdaLo, $RdaHi, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDVs16acc (966) - ARM_INS_VADDVA - vaddva${vp}.s16 $Rda, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDVs16no_acc (967) - ARM_INS_VADDV - vaddv${vp}.s16 $Rda, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDVs32acc (968) - ARM_INS_VADDVA - vaddva${vp}.s32 $Rda, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDVs32no_acc (969) - ARM_INS_VADDV - vaddv${vp}.s32 $Rda, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDVs8acc (970) - ARM_INS_VADDVA - vaddva${vp}.s8 $Rda, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDVs8no_acc (971) - ARM_INS_VADDV - vaddv${vp}.s8 $Rda, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDVu16acc (972) - ARM_INS_VADDVA - vaddva${vp}.u16 $Rda, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDVu16no_acc (973) - ARM_INS_VADDV - vaddv${vp}.u16 $Rda, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDVu32acc (974) - ARM_INS_VADDVA - vaddva${vp}.u32 $Rda, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDVu32no_acc (975) - ARM_INS_VADDV - vaddv${vp}.u32 $Rda, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDVu8acc (976) - ARM_INS_VADDVA - vaddva${vp}.u8 $Rda, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADDVu8no_acc (977) - ARM_INS_VADDV - vaddv${vp}.u8 $Rda, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VADD_qr_f16 (978) - ARM_INS_VADD - vadd${vp}.f16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VADD_qr_f32 (979) - ARM_INS_VADD - vadd${vp}.f32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VADD_qr_i16 (980) - ARM_INS_VADD - vadd${vp}.i16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VADD_qr_i32 (981) - ARM_INS_VADD - vadd${vp}.i32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VADD_qr_i8 (982) - ARM_INS_VADD - vadd${vp}.i8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VADDf16 (983) - ARM_INS_VADD - vadd${vp}.f16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VADDf32 (984) - ARM_INS_VADD - vadd${vp}.f32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VADDi16 (985) - ARM_INS_VADD - vadd${vp}.i16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VADDi32 (986) - ARM_INS_VADD - vadd${vp}.i32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VADDi8 (987) - ARM_INS_VADD - vadd${vp}.i8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VAND (988) - ARM_INS_VAND - vand${vp} $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VBIC (989) - ARM_INS_VBIC - vbic${vp} $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VBICimmi16 (990) - ARM_INS_VBIC - vbic${vp}.i16 $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VBICimmi32 (991) - ARM_INS_VBIC - vbic${vp}.i32 $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VBRSR16 (992) - ARM_INS_VBRSR - vbrsr${vp}.16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VBRSR32 (993) - ARM_INS_VBRSR - vbrsr${vp}.32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VBRSR8 (994) - ARM_INS_VBRSR - vbrsr${vp}.8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCADDf16 (995) - ARM_INS_VCADD - vcadd${vp}.f16 $Qd, $Qn, $Qm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCADDf32 (996) - ARM_INS_VCADD - vcadd${vp}.f32 $Qd, $Qn, $Qm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCADDi16 (997) - ARM_INS_VCADD - vcadd${vp}.i16 $Qd, $Qn, $Qm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCADDi32 (998) - ARM_INS_VCADD - vcadd${vp}.i32 $Qd, $Qn, $Qm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCADDi8 (999) - ARM_INS_VCADD - vcadd${vp}.i8 $Qd, $Qn, $Qm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCLSs16 (1000) - ARM_INS_VCLS - vcls${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCLSs32 (1001) - ARM_INS_VCLS - vcls${vp}.s32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCLSs8 (1002) - ARM_INS_VCLS - vcls${vp}.s8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCLZs16 (1003) - ARM_INS_VCLZ - vclz${vp}.i16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCLZs32 (1004) - ARM_INS_VCLZ - vclz${vp}.i32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCLZs8 (1005) - ARM_INS_VCLZ - vclz${vp}.i8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCMLAf16 (1006) - ARM_INS_VCMLA - vcmla${vp}.f16 $Qd, $Qn, $Qm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMLAf32 (1007) - ARM_INS_VCMLA - vcmla${vp}.f32 $Qd, $Qn, $Qm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPf16 (1008) - ARM_INS_VCMP - vcmp${vp}.f16 $fc, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPf16r (1009) - ARM_INS_VCMP - vcmp${vp}.f16 $fc, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPf32 (1010) - ARM_INS_VCMP - vcmp${vp}.f32 $fc, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPf32r (1011) - ARM_INS_VCMP - vcmp${vp}.f32 $fc, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPi16 (1012) - ARM_INS_VCMP - vcmp${vp}.i16 $fc, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPi16r (1013) - ARM_INS_VCMP - vcmp${vp}.i16 $fc, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPi32 (1014) - ARM_INS_VCMP - vcmp${vp}.i32 $fc, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPi32r (1015) - ARM_INS_VCMP - vcmp${vp}.i32 $fc, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPi8 (1016) - ARM_INS_VCMP - vcmp${vp}.i8 $fc, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPi8r (1017) - ARM_INS_VCMP - vcmp${vp}.i8 $fc, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPs16 (1018) - ARM_INS_VCMP - vcmp${vp}.s16 $fc, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPs16r (1019) - ARM_INS_VCMP - vcmp${vp}.s16 $fc, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPs32 (1020) - ARM_INS_VCMP - vcmp${vp}.s32 $fc, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPs32r (1021) - ARM_INS_VCMP - vcmp${vp}.s32 $fc, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPs8 (1022) - ARM_INS_VCMP - vcmp${vp}.s8 $fc, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPs8r (1023) - ARM_INS_VCMP - vcmp${vp}.s8 $fc, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPu16 (1024) - ARM_INS_VCMP - vcmp${vp}.u16 $fc, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPu16r (1025) - ARM_INS_VCMP - vcmp${vp}.u16 $fc, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPu32 (1026) - ARM_INS_VCMP - vcmp${vp}.u32 $fc, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPu32r (1027) - ARM_INS_VCMP - vcmp${vp}.u32 $fc, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPu8 (1028) - ARM_INS_VCMP - vcmp${vp}.u8 $fc, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMPu8r (1029) - ARM_INS_VCMP - vcmp${vp}.u8 $fc, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCMULf16 (1030) - ARM_INS_VCMUL - vcmul${vp}.f16 $Qd, $Qn, $Qm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCMULf32 (1031) - ARM_INS_VCMUL - vcmul${vp}.f32 $Qd, $Qn, $Qm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCTP16 (1032) - ARM_INS_VCTP - vctp${vp}.16 $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCTP32 (1033) - ARM_INS_VCTP - vctp${vp}.32 $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCTP64 (1034) - ARM_INS_VCTP - vctp${vp}.64 $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCTP8 (1035) - ARM_INS_VCTP - vctp${vp}.8 $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCVTf16f32bh (1036) - ARM_INS_VCVTB - vcvtb${vp}.f16.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCVTf16f32th (1037) - ARM_INS_VCVTT - vcvtt${vp}.f16.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VCVTf16s16_fix (1038) - ARM_INS_VCVT - vcvt${vp}.f16.s16 $Qd, $Qm, $imm6 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTf16s16n (1039) - ARM_INS_VCVT - vcvt${vp}.f16.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTf16u16_fix (1040) - ARM_INS_VCVT - vcvt${vp}.f16.u16 $Qd, $Qm, $imm6 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTf16u16n (1041) - ARM_INS_VCVT - vcvt${vp}.f16.u16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTf32f16bh (1042) - ARM_INS_VCVTB - vcvtb${vp}.f32.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTf32f16th (1043) - ARM_INS_VCVTT - vcvtt${vp}.f32.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTf32s32_fix (1044) - ARM_INS_VCVT - vcvt${vp}.f32.s32 $Qd, $Qm, $imm6 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTf32s32n (1045) - ARM_INS_VCVT - vcvt${vp}.f32.s32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTf32u32_fix (1046) - ARM_INS_VCVT - vcvt${vp}.f32.u32 $Qd, $Qm, $imm6 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTf32u32n (1047) - ARM_INS_VCVT - vcvt${vp}.f32.u32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTs16f16_fix (1048) - ARM_INS_VCVT - vcvt${vp}.s16.f16 $Qd, $Qm, $imm6 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTs16f16a (1049) - ARM_INS_VCVTA - vcvta${vp}.s16.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTs16f16m (1050) - ARM_INS_VCVTM - vcvtm${vp}.s16.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTs16f16n (1051) - ARM_INS_VCVTN - vcvtn${vp}.s16.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTs16f16p (1052) - ARM_INS_VCVTP - vcvtp${vp}.s16.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTs16f16z (1053) - ARM_INS_VCVT - vcvt${vp}.s16.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTs32f32_fix (1054) - ARM_INS_VCVT - vcvt${vp}.s32.f32 $Qd, $Qm, $imm6 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTs32f32a (1055) - ARM_INS_VCVTA - vcvta${vp}.s32.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTs32f32m (1056) - ARM_INS_VCVTM - vcvtm${vp}.s32.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTs32f32n (1057) - ARM_INS_VCVTN - vcvtn${vp}.s32.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTs32f32p (1058) - ARM_INS_VCVTP - vcvtp${vp}.s32.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTs32f32z (1059) - ARM_INS_VCVT - vcvt${vp}.s32.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTu16f16_fix (1060) - ARM_INS_VCVT - vcvt${vp}.u16.f16 $Qd, $Qm, $imm6 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTu16f16a (1061) - ARM_INS_VCVTA - vcvta${vp}.u16.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTu16f16m (1062) - ARM_INS_VCVTM - vcvtm${vp}.u16.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTu16f16n (1063) - ARM_INS_VCVTN - vcvtn${vp}.u16.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTu16f16p (1064) - ARM_INS_VCVTP - vcvtp${vp}.u16.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTu16f16z (1065) - ARM_INS_VCVT - vcvt${vp}.u16.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTu32f32_fix (1066) - ARM_INS_VCVT - vcvt${vp}.u32.f32 $Qd, $Qm, $imm6 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTu32f32a (1067) - ARM_INS_VCVTA - vcvta${vp}.u32.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTu32f32m (1068) - ARM_INS_VCVTM - vcvtm${vp}.u32.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTu32f32n (1069) - ARM_INS_VCVTN - vcvtn${vp}.u32.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTu32f32p (1070) - ARM_INS_VCVTP - vcvtp${vp}.u32.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VCVTu32f32z (1071) - ARM_INS_VCVT - vcvt${vp}.u32.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VDDUPu16 (1072) - ARM_INS_VDDUP - vddup${vp}.u16 $Qd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VDDUPu32 (1073) - ARM_INS_VDDUP - vddup${vp}.u32 $Qd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VDDUPu8 (1074) - ARM_INS_VDDUP - vddup${vp}.u8 $Qd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VDUP16 (1075) - ARM_INS_VDUP - vdup${vp}.16 $Qd, $Rt */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VDUP32 (1076) - ARM_INS_VDUP - vdup${vp}.32 $Qd, $Rt */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VDUP8 (1077) - ARM_INS_VDUP - vdup${vp}.8 $Qd, $Rt */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VDWDUPu16 (1078) - ARM_INS_VDWDUP - vdwdup${vp}.u16 $Qd, $Rn, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VDWDUPu32 (1079) - ARM_INS_VDWDUP - vdwdup${vp}.u32 $Qd, $Rn, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VDWDUPu8 (1080) - ARM_INS_VDWDUP - vdwdup${vp}.u8 $Qd, $Rn, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VEOR (1081) - ARM_INS_VEOR - veor${vp} $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VFMA_qr_Sf16 (1082) - ARM_INS_VFMAS - vfmas${vp}.f16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VFMA_qr_Sf32 (1083) - ARM_INS_VFMAS - vfmas${vp}.f32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VFMA_qr_f16 (1084) - ARM_INS_VFMA - vfma${vp}.f16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VFMA_qr_f32 (1085) - ARM_INS_VFMA - vfma${vp}.f32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VFMAf16 (1086) - ARM_INS_VFMA - vfma${vp}.f16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VFMAf32 (1087) - ARM_INS_VFMA - vfma${vp}.f32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VFMSf16 (1088) - ARM_INS_VFMS - vfms${vp}.f16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VFMSf32 (1089) - ARM_INS_VFMS - vfms${vp}.f32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VHADD_qr_s16 (1090) - ARM_INS_VHADD - vhadd${vp}.s16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHADD_qr_s32 (1091) - ARM_INS_VHADD - vhadd${vp}.s32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHADD_qr_s8 (1092) - ARM_INS_VHADD - vhadd${vp}.s8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHADD_qr_u16 (1093) - ARM_INS_VHADD - vhadd${vp}.u16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHADD_qr_u32 (1094) - ARM_INS_VHADD - vhadd${vp}.u32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHADD_qr_u8 (1095) - ARM_INS_VHADD - vhadd${vp}.u8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHADDs16 (1096) - ARM_INS_VHADD - vhadd${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHADDs32 (1097) - ARM_INS_VHADD - vhadd${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHADDs8 (1098) - ARM_INS_VHADD - vhadd${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHADDu16 (1099) - ARM_INS_VHADD - vhadd${vp}.u16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHADDu32 (1100) - ARM_INS_VHADD - vhadd${vp}.u32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHADDu8 (1101) - ARM_INS_VHADD - vhadd${vp}.u8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHCADDs16 (1102) - ARM_INS_VHCADD - vhcadd${vp}.s16 $Qd, $Qn, $Qm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHCADDs32 (1103) - ARM_INS_VHCADD - vhcadd${vp}.s32 $Qd, $Qn, $Qm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHCADDs8 (1104) - ARM_INS_VHCADD - vhcadd${vp}.s8 $Qd, $Qn, $Qm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHSUB_qr_s16 (1105) - ARM_INS_VHSUB - vhsub${vp}.s16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHSUB_qr_s32 (1106) - ARM_INS_VHSUB - vhsub${vp}.s32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHSUB_qr_s8 (1107) - ARM_INS_VHSUB - vhsub${vp}.s8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHSUB_qr_u16 (1108) - ARM_INS_VHSUB - vhsub${vp}.u16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHSUB_qr_u32 (1109) - ARM_INS_VHSUB - vhsub${vp}.u32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHSUB_qr_u8 (1110) - ARM_INS_VHSUB - vhsub${vp}.u8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHSUBs16 (1111) - ARM_INS_VHSUB - vhsub${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHSUBs32 (1112) - ARM_INS_VHSUB - vhsub${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHSUBs8 (1113) - ARM_INS_VHSUB - vhsub${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHSUBu16 (1114) - ARM_INS_VHSUB - vhsub${vp}.u16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHSUBu32 (1115) - ARM_INS_VHSUB - vhsub${vp}.u32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VHSUBu8 (1116) - ARM_INS_VHSUB - vhsub${vp}.u8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VIDUPu16 (1117) - ARM_INS_VIDUP - vidup${vp}.u16 $Qd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VIDUPu32 (1118) - ARM_INS_VIDUP - vidup${vp}.u32 $Qd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VIDUPu8 (1119) - ARM_INS_VIDUP - vidup${vp}.u8 $Qd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VIWDUPu16 (1120) - ARM_INS_VIWDUP - viwdup${vp}.u16 $Qd, $Rn, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VIWDUPu32 (1121) - ARM_INS_VIWDUP - viwdup${vp}.u32 $Qd, $Rn, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VIWDUPu8 (1122) - ARM_INS_VIWDUP - viwdup${vp}.u8 $Qd, $Rn, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VLD20_16 (1123) - ARM_INS_VLD20 - vld20.16 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD20_16_wb (1124) - ARM_INS_VLD20 - vld20.16 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD20_32 (1125) - ARM_INS_VLD20 - vld20.32 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD20_32_wb (1126) - ARM_INS_VLD20 - vld20.32 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD20_8 (1127) - ARM_INS_VLD20 - vld20.8 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD20_8_wb (1128) - ARM_INS_VLD20 - vld20.8 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD21_16 (1129) - ARM_INS_VLD21 - vld21.16 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD21_16_wb (1130) - ARM_INS_VLD21 - vld21.16 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD21_32 (1131) - ARM_INS_VLD21 - vld21.32 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD21_32_wb (1132) - ARM_INS_VLD21 - vld21.32 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD21_8 (1133) - ARM_INS_VLD21 - vld21.8 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD21_8_wb (1134) - ARM_INS_VLD21 - vld21.8 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD40_16 (1135) - ARM_INS_VLD40 - vld40.16 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD40_16_wb (1136) - ARM_INS_VLD40 - vld40.16 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD40_32 (1137) - ARM_INS_VLD40 - vld40.32 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD40_32_wb (1138) - ARM_INS_VLD40 - vld40.32 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD40_8 (1139) - ARM_INS_VLD40 - vld40.8 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD40_8_wb (1140) - ARM_INS_VLD40 - vld40.8 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD41_16 (1141) - ARM_INS_VLD41 - vld41.16 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD41_16_wb (1142) - ARM_INS_VLD41 - vld41.16 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD41_32 (1143) - ARM_INS_VLD41 - vld41.32 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD41_32_wb (1144) - ARM_INS_VLD41 - vld41.32 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD41_8 (1145) - ARM_INS_VLD41 - vld41.8 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD41_8_wb (1146) - ARM_INS_VLD41 - vld41.8 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD42_16 (1147) - ARM_INS_VLD42 - vld42.16 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD42_16_wb (1148) - ARM_INS_VLD42 - vld42.16 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD42_32 (1149) - ARM_INS_VLD42 - vld42.32 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD42_32_wb (1150) - ARM_INS_VLD42 - vld42.32 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD42_8 (1151) - ARM_INS_VLD42 - vld42.8 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD42_8_wb (1152) - ARM_INS_VLD42 - vld42.8 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD43_16 (1153) - ARM_INS_VLD43 - vld43.16 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD43_16_wb (1154) - ARM_INS_VLD43 - vld43.16 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD43_32 (1155) - ARM_INS_VLD43 - vld43.32 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD43_32_wb (1156) - ARM_INS_VLD43 - vld43.32 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLD43_8 (1157) - ARM_INS_VLD43 - vld43.8 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VLD43_8_wb (1158) - ARM_INS_VLD43 - vld43.8 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VLDRBS16 (1159) - ARM_INS_VLDRB - vldrb${vp}.s16 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBS16_post (1160) - ARM_INS_VLDRB - vldrb${vp}.s16 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBS16_pre (1161) - ARM_INS_VLDRB - vldrb${vp}.s16 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBS16_rq (1162) - ARM_INS_VLDRB - vldrb${vp}.s16 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBS32 (1163) - ARM_INS_VLDRB - vldrb${vp}.s32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBS32_post (1164) - ARM_INS_VLDRB - vldrb${vp}.s32 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBS32_pre (1165) - ARM_INS_VLDRB - vldrb${vp}.s32 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBS32_rq (1166) - ARM_INS_VLDRB - vldrb${vp}.s32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBU16 (1167) - ARM_INS_VLDRB - vldrb${vp}.u16 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBU16_post (1168) - ARM_INS_VLDRB - vldrb${vp}.u16 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBU16_pre (1169) - ARM_INS_VLDRB - vldrb${vp}.u16 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBU16_rq (1170) - ARM_INS_VLDRB - vldrb${vp}.u16 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBU32 (1171) - ARM_INS_VLDRB - vldrb${vp}.u32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBU32_post (1172) - ARM_INS_VLDRB - vldrb${vp}.u32 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBU32_pre (1173) - ARM_INS_VLDRB - vldrb${vp}.u32 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBU32_rq (1174) - ARM_INS_VLDRB - vldrb${vp}.u32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBU8 (1175) - ARM_INS_VLDRB - vldrb${vp}.u8 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBU8_post (1176) - ARM_INS_VLDRB - vldrb${vp}.u8 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBU8_pre (1177) - ARM_INS_VLDRB - vldrb${vp}.u8 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRBU8_rq (1178) - ARM_INS_VLDRB - vldrb${vp}.u8 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRDU64_qi (1179) - ARM_INS_VLDRD - vldrd${vp}.u64 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRDU64_qi_pre (1180) - ARM_INS_VLDRD - vldrd${vp}.u64 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRDU64_rq (1181) - ARM_INS_VLDRD - vldrd${vp}.u64 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRDU64_rq_u (1182) - ARM_INS_VLDRD - vldrd${vp}.u64 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHS32 (1183) - ARM_INS_VLDRH - vldrh${vp}.s32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHS32_post (1184) - ARM_INS_VLDRH - vldrh${vp}.s32 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHS32_pre (1185) - ARM_INS_VLDRH - vldrh${vp}.s32 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHS32_rq (1186) - ARM_INS_VLDRH - vldrh${vp}.s32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHS32_rq_u (1187) - ARM_INS_VLDRH - vldrh${vp}.s32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHU16 (1188) - ARM_INS_VLDRH - vldrh${vp}.u16 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHU16_post (1189) - ARM_INS_VLDRH - vldrh${vp}.u16 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHU16_pre (1190) - ARM_INS_VLDRH - vldrh${vp}.u16 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHU16_rq (1191) - ARM_INS_VLDRH - vldrh${vp}.u16 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHU16_rq_u (1192) - ARM_INS_VLDRH - vldrh${vp}.u16 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHU32 (1193) - ARM_INS_VLDRH - vldrh${vp}.u32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHU32_post (1194) - ARM_INS_VLDRH - vldrh${vp}.u32 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHU32_pre (1195) - ARM_INS_VLDRH - vldrh${vp}.u32 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHU32_rq (1196) - ARM_INS_VLDRH - vldrh${vp}.u32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRHU32_rq_u (1197) - ARM_INS_VLDRH - vldrh${vp}.u32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRWU32 (1198) - ARM_INS_VLDRW - vldrw${vp}.u32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRWU32_post (1199) - ARM_INS_VLDRW - vldrw${vp}.u32 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRWU32_pre (1200) - ARM_INS_VLDRW - vldrw${vp}.u32 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRWU32_qi (1201) - ARM_INS_VLDRW - vldrw${vp}.u32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRWU32_qi_pre (1202) - ARM_INS_VLDRW - vldrw${vp}.u32 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRWU32_rq (1203) - ARM_INS_VLDRW - vldrw${vp}.u32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VLDRWU32_rq_u (1204) - ARM_INS_VLDRW - vldrw${vp}.u32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXAVs16 (1205) - ARM_INS_VMAXAV - vmaxav${vp}.s16 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXAVs32 (1206) - ARM_INS_VMAXAV - vmaxav${vp}.s32 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXAVs8 (1207) - ARM_INS_VMAXAV - vmaxav${vp}.s8 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXAs16 (1208) - ARM_INS_VMAXA - vmaxa${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXAs32 (1209) - ARM_INS_VMAXA - vmaxa${vp}.s32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXAs8 (1210) - ARM_INS_VMAXA - vmaxa${vp}.s8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXNMAVf16 (1211) - ARM_INS_VMAXNMAV - vmaxnmav${vp}.f16 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXNMAVf32 (1212) - ARM_INS_VMAXNMAV - vmaxnmav${vp}.f32 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXNMAf16 (1213) - ARM_INS_VMAXNMA - vmaxnma${vp}.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXNMAf32 (1214) - ARM_INS_VMAXNMA - vmaxnma${vp}.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXNMVf16 (1215) - ARM_INS_VMAXNMV - vmaxnmv${vp}.f16 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXNMVf32 (1216) - ARM_INS_VMAXNMV - vmaxnmv${vp}.f32 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXNMf16 (1217) - ARM_INS_VMAXNM - vmaxnm${vp}.f16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMAXNMf32 (1218) - ARM_INS_VMAXNM - vmaxnm${vp}.f32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMAXVs16 (1219) - ARM_INS_VMAXV - vmaxv${vp}.s16 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXVs32 (1220) - ARM_INS_VMAXV - vmaxv${vp}.s32 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXVs8 (1221) - ARM_INS_VMAXV - vmaxv${vp}.s8 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXVu16 (1222) - ARM_INS_VMAXV - vmaxv${vp}.u16 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXVu32 (1223) - ARM_INS_VMAXV - vmaxv${vp}.u32 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXVu8 (1224) - ARM_INS_VMAXV - vmaxv${vp}.u8 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMAXs16 (1225) - ARM_INS_VMAX - vmax${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMAXs32 (1226) - ARM_INS_VMAX - vmax${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMAXs8 (1227) - ARM_INS_VMAX - vmax${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMAXu16 (1228) - ARM_INS_VMAX - vmax${vp}.u16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMAXu32 (1229) - ARM_INS_VMAX - vmax${vp}.u32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMAXu8 (1230) - ARM_INS_VMAX - vmax${vp}.u8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMINAVs16 (1231) - ARM_INS_VMINAV - vminav${vp}.s16 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINAVs32 (1232) - ARM_INS_VMINAV - vminav${vp}.s32 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINAVs8 (1233) - ARM_INS_VMINAV - vminav${vp}.s8 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINAs16 (1234) - ARM_INS_VMINA - vmina${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINAs32 (1235) - ARM_INS_VMINA - vmina${vp}.s32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINAs8 (1236) - ARM_INS_VMINA - vmina${vp}.s8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINNMAVf16 (1237) - ARM_INS_VMINNMAV - vminnmav${vp}.f16 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINNMAVf32 (1238) - ARM_INS_VMINNMAV - vminnmav${vp}.f32 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINNMAf16 (1239) - ARM_INS_VMINNMA - vminnma${vp}.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINNMAf32 (1240) - ARM_INS_VMINNMA - vminnma${vp}.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINNMVf16 (1241) - ARM_INS_VMINNMV - vminnmv${vp}.f16 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINNMVf32 (1242) - ARM_INS_VMINNMV - vminnmv${vp}.f32 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINNMf16 (1243) - ARM_INS_VMINNM - vminnm${vp}.f16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMINNMf32 (1244) - ARM_INS_VMINNM - vminnm${vp}.f32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMINVs16 (1245) - ARM_INS_VMINV - vminv${vp}.s16 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINVs32 (1246) - ARM_INS_VMINV - vminv${vp}.s32 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINVs8 (1247) - ARM_INS_VMINV - vminv${vp}.s8 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINVu16 (1248) - ARM_INS_VMINV - vminv${vp}.u16 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINVu32 (1249) - ARM_INS_VMINV - vminv${vp}.u32 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINVu8 (1250) - ARM_INS_VMINV - vminv${vp}.u8 $RdaSrc, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMINs16 (1251) - ARM_INS_VMIN - vmin${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMINs32 (1252) - ARM_INS_VMIN - vmin${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMINs8 (1253) - ARM_INS_VMIN - vmin${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMINu16 (1254) - ARM_INS_VMIN - vmin${vp}.u16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMINu32 (1255) - ARM_INS_VMIN - vmin${vp}.u32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMINu8 (1256) - ARM_INS_VMIN - vmin${vp}.u8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVas16 (1257) - ARM_INS_VMLADAVA - vmladava${vp}.s16 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVas32 (1258) - ARM_INS_VMLADAVA - vmladava${vp}.s32 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVas8 (1259) - ARM_INS_VMLADAVA - vmladava${vp}.s8 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVau16 (1260) - ARM_INS_VMLADAVA - vmladava${vp}.u16 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVau32 (1261) - ARM_INS_VMLADAVA - vmladava${vp}.u32 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVau8 (1262) - ARM_INS_VMLADAVA - vmladava${vp}.u8 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVaxs16 (1263) - ARM_INS_VMLADAVAX - vmladavax${vp}.s16 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVaxs32 (1264) - ARM_INS_VMLADAVAX - vmladavax${vp}.s32 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVaxs8 (1265) - ARM_INS_VMLADAVAX - vmladavax${vp}.s8 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVs16 (1266) - ARM_INS_VMLADAV - vmladav${vp}.s16 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVs32 (1267) - ARM_INS_VMLADAV - vmladav${vp}.s32 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVs8 (1268) - ARM_INS_VMLADAV - vmladav${vp}.s8 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVu16 (1269) - ARM_INS_VMLADAV - vmladav${vp}.u16 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVu32 (1270) - ARM_INS_VMLADAV - vmladav${vp}.u32 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVu8 (1271) - ARM_INS_VMLADAV - vmladav${vp}.u8 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVxs16 (1272) - ARM_INS_VMLADAVX - vmladavx${vp}.s16 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVxs32 (1273) - ARM_INS_VMLADAVX - vmladavx${vp}.s32 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLADAVxs8 (1274) - ARM_INS_VMLADAVX - vmladavx${vp}.s8 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLALDAVas16 (1275) - ARM_INS_VMLALDAVA - vmlaldava${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLALDAVas32 (1276) - ARM_INS_VMLALDAVA - vmlaldava${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLALDAVau16 (1277) - ARM_INS_VMLALDAVA - vmlaldava${vp}.u16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLALDAVau32 (1278) - ARM_INS_VMLALDAVA - vmlaldava${vp}.u32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLALDAVaxs16 (1279) - ARM_INS_VMLALDAVAX - vmlaldavax${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLALDAVaxs32 (1280) - ARM_INS_VMLALDAVAX - vmlaldavax${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLALDAVs16 (1281) - ARM_INS_VMLALDAV - vmlaldav${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLALDAVs32 (1282) - ARM_INS_VMLALDAV - vmlaldav${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLALDAVu16 (1283) - ARM_INS_VMLALDAV - vmlaldav${vp}.u16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLALDAVu32 (1284) - ARM_INS_VMLALDAV - vmlaldav${vp}.u32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLALDAVxs16 (1285) - ARM_INS_VMLALDAVX - vmlaldavx${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLALDAVxs32 (1286) - ARM_INS_VMLALDAVX - vmlaldavx${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLAS_qr_i16 (1287) - ARM_INS_VMLAS - vmlas${vp}.i16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLAS_qr_i32 (1288) - ARM_INS_VMLAS - vmlas${vp}.i32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLAS_qr_i8 (1289) - ARM_INS_VMLAS - vmlas${vp}.i8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLA_qr_i16 (1290) - ARM_INS_VMLA - vmla${vp}.i16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLA_qr_i32 (1291) - ARM_INS_VMLA - vmla${vp}.i32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLA_qr_i8 (1292) - ARM_INS_VMLA - vmla${vp}.i8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSDAVas16 (1293) - ARM_INS_VMLSDAVA - vmlsdava${vp}.s16 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSDAVas32 (1294) - ARM_INS_VMLSDAVA - vmlsdava${vp}.s32 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSDAVas8 (1295) - ARM_INS_VMLSDAVA - vmlsdava${vp}.s8 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSDAVaxs16 (1296) - ARM_INS_VMLSDAVAX - vmlsdavax${vp}.s16 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSDAVaxs32 (1297) - ARM_INS_VMLSDAVAX - vmlsdavax${vp}.s32 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSDAVaxs8 (1298) - ARM_INS_VMLSDAVAX - vmlsdavax${vp}.s8 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSDAVs16 (1299) - ARM_INS_VMLSDAV - vmlsdav${vp}.s16 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSDAVs32 (1300) - ARM_INS_VMLSDAV - vmlsdav${vp}.s32 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSDAVs8 (1301) - ARM_INS_VMLSDAV - vmlsdav${vp}.s8 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSDAVxs16 (1302) - ARM_INS_VMLSDAVX - vmlsdavx${vp}.s16 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSDAVxs32 (1303) - ARM_INS_VMLSDAVX - vmlsdavx${vp}.s32 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSDAVxs8 (1304) - ARM_INS_VMLSDAVX - vmlsdavx${vp}.s8 $RdaDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSLDAVas16 (1305) - ARM_INS_VMLSLDAVA - vmlsldava${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSLDAVas32 (1306) - ARM_INS_VMLSLDAVA - vmlsldava${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSLDAVaxs16 (1307) - ARM_INS_VMLSLDAVAX - vmlsldavax${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSLDAVaxs32 (1308) - ARM_INS_VMLSLDAVAX - vmlsldavax${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSLDAVs16 (1309) - ARM_INS_VMLSLDAV - vmlsldav${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSLDAVs32 (1310) - ARM_INS_VMLSLDAV - vmlsldav${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSLDAVxs16 (1311) - ARM_INS_VMLSLDAVX - vmlsldavx${vp}.s16 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMLSLDAVxs32 (1312) - ARM_INS_VMLSLDAVX - vmlsldavx${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMOVLs16bh (1313) - ARM_INS_VMOVLB - vmovlb${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMOVLs16th (1314) - ARM_INS_VMOVLT - vmovlt${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMOVLs8bh (1315) - ARM_INS_VMOVLB - vmovlb${vp}.s8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMOVLs8th (1316) - ARM_INS_VMOVLT - vmovlt${vp}.s8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMOVLu16bh (1317) - ARM_INS_VMOVLB - vmovlb${vp}.u16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMOVLu16th (1318) - ARM_INS_VMOVLT - vmovlt${vp}.u16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMOVLu8bh (1319) - ARM_INS_VMOVLB - vmovlb${vp}.u8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMOVLu8th (1320) - ARM_INS_VMOVLT - vmovlt${vp}.u8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMOVNi16bh (1321) - ARM_INS_VMOVNB - vmovnb${vp}.i16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMOVNi16th (1322) - ARM_INS_VMOVNT - vmovnt${vp}.i16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMOVNi32bh (1323) - ARM_INS_VMOVNB - vmovnb${vp}.i32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMOVNi32th (1324) - ARM_INS_VMOVNT - vmovnt${vp}.i32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VMOV_from_lane_32 (1325) - ARM_INS_VMOV - vmov${p}.32 $Rt, $Qd$Idx */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_VMOV_from_lane_s16 (1326) - ARM_INS_VMOV - vmov${p}.s16 $Rt, $Qd$Idx */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_VMOV_from_lane_s8 (1327) - ARM_INS_VMOV - vmov${p}.s8 $Rt, $Qd$Idx */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_VMOV_from_lane_u16 (1328) - ARM_INS_VMOV - vmov${p}.u16 $Rt, $Qd$Idx */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_VMOV_from_lane_u8 (1329) - ARM_INS_VMOV - vmov${p}.u8 $Rt, $Qd$Idx */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_VMOV_q_rr (1330) - ARM_INS_VMOV - vmov${p} $Qd$idx, $QdSrc$idx2, $Rt, $Rt2 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx2 - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_VMOV_rr_q (1331) - ARM_INS_VMOV - vmov${p} $Rt, $Rt2, $Qd$idx, $Qd$idx2 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx2 - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_VMOV_to_lane_16 (1332) - ARM_INS_VMOV - vmov${p}.16 $Qd$Idx, $Rt */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_VMOV_to_lane_32 (1333) - ARM_INS_VMOV - vmov${p}.32 $Qd$Idx, $Rt */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_VMOV_to_lane_8 (1334) - ARM_INS_VMOV - vmov${p}.8 $Qd$Idx, $Rt */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_MVE_VMOVimmf32 (1335) - ARM_INS_VMOV - vmov${vp}.f32 $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMOVimmi16 (1336) - ARM_INS_VMOV - vmov${vp}.i16 $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMOVimmi32 (1337) - ARM_INS_VMOV - vmov${vp}.i32 $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMOVimmi64 (1338) - ARM_INS_VMOV - vmov${vp}.i64 $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMOVimmi8 (1339) - ARM_INS_VMOV - vmov${vp}.i8 $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULHs16 (1340) - ARM_INS_VMULH - vmulh${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULHs32 (1341) - ARM_INS_VMULH - vmulh${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULHs8 (1342) - ARM_INS_VMULH - vmulh${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULHu16 (1343) - ARM_INS_VMULH - vmulh${vp}.u16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULHu32 (1344) - ARM_INS_VMULH - vmulh${vp}.u32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULHu8 (1345) - ARM_INS_VMULH - vmulh${vp}.u8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLBp16 (1346) - ARM_INS_VMULLB - vmullb${vp}.p16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLBp8 (1347) - ARM_INS_VMULLB - vmullb${vp}.p8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLBs16 (1348) - ARM_INS_VMULLB - vmullb${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLBs32 (1349) - ARM_INS_VMULLB - vmullb${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLBs8 (1350) - ARM_INS_VMULLB - vmullb${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLBu16 (1351) - ARM_INS_VMULLB - vmullb${vp}.u16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLBu32 (1352) - ARM_INS_VMULLB - vmullb${vp}.u32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLBu8 (1353) - ARM_INS_VMULLB - vmullb${vp}.u8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLTp16 (1354) - ARM_INS_VMULLT - vmullt${vp}.p16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLTp8 (1355) - ARM_INS_VMULLT - vmullt${vp}.p8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLTs16 (1356) - ARM_INS_VMULLT - vmullt${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLTs32 (1357) - ARM_INS_VMULLT - vmullt${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLTs8 (1358) - ARM_INS_VMULLT - vmullt${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLTu16 (1359) - ARM_INS_VMULLT - vmullt${vp}.u16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLTu32 (1360) - ARM_INS_VMULLT - vmullt${vp}.u32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULLTu8 (1361) - ARM_INS_VMULLT - vmullt${vp}.u8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMUL_qr_f16 (1362) - ARM_INS_VMUL - vmul${vp}.f16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMUL_qr_f32 (1363) - ARM_INS_VMUL - vmul${vp}.f32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMUL_qr_i16 (1364) - ARM_INS_VMUL - vmul${vp}.i16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMUL_qr_i32 (1365) - ARM_INS_VMUL - vmul${vp}.i32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMUL_qr_i8 (1366) - ARM_INS_VMUL - vmul${vp}.i8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULf16 (1367) - ARM_INS_VMUL - vmul${vp}.f16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULf32 (1368) - ARM_INS_VMUL - vmul${vp}.f32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULi16 (1369) - ARM_INS_VMUL - vmul${vp}.i16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULi32 (1370) - ARM_INS_VMUL - vmul${vp}.i32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMULi8 (1371) - ARM_INS_VMUL - vmul${vp}.i8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMVN (1372) - ARM_INS_VMVN - vmvn${vp} $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMVNimmi16 (1373) - ARM_INS_VMVN - vmvn${vp}.i16 $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VMVNimmi32 (1374) - ARM_INS_VMVN - vmvn${vp}.i32 $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VNEGf16 (1375) - ARM_INS_VNEG - vneg${vp}.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VNEGf32 (1376) - ARM_INS_VNEG - vneg${vp}.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VNEGs16 (1377) - ARM_INS_VNEG - vneg${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VNEGs32 (1378) - ARM_INS_VNEG - vneg${vp}.s32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VNEGs8 (1379) - ARM_INS_VNEG - vneg${vp}.s8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VORN (1380) - ARM_INS_VORN - vorn${vp} $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VORR (1381) - ARM_INS_VORR - vorr${vp} $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VORRimmi16 (1382) - ARM_INS_VORR - vorr${vp}.i16 $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VORRimmi32 (1383) - ARM_INS_VORR - vorr${vp}.i32 $Qd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VPNOT (1384) - ARM_INS_VPNOT - vpnot${vp} */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0_in */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VPSEL (1385) - ARM_INS_VPSEL - vpsel${vp} $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VPST (1386) - ARM_INS_VPST - vpst${Mk} */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { 0 } } + }, + { /* ARM_MVE_VPTv16i8 (1387) - ARM_INS_VPT - vpt${Mk}.i8 $fc, $Qn, $Qm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv16i8r (1388) - ARM_INS_VPT - vpt${Mk}.i8 $fc, $Qn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv16s8 (1389) - ARM_INS_VPT - vpt${Mk}.s8 $fc, $Qn, $Qm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv16s8r (1390) - ARM_INS_VPT - vpt${Mk}.s8 $fc, $Qn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv16u8 (1391) - ARM_INS_VPT - vpt${Mk}.u8 $fc, $Qn, $Qm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv16u8r (1392) - ARM_INS_VPT - vpt${Mk}.u8 $fc, $Qn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv4f32 (1393) - ARM_INS_VPT - vpt${Mk}.f32 $fc, $Qn, $Qm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv4f32r (1394) - ARM_INS_VPT - vpt${Mk}.f32 $fc, $Qn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv4i32 (1395) - ARM_INS_VPT - vpt${Mk}.i32 $fc, $Qn, $Qm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv4i32r (1396) - ARM_INS_VPT - vpt${Mk}.i32 $fc, $Qn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv4s32 (1397) - ARM_INS_VPT - vpt${Mk}.s32 $fc, $Qn, $Qm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv4s32r (1398) - ARM_INS_VPT - vpt${Mk}.s32 $fc, $Qn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv4u32 (1399) - ARM_INS_VPT - vpt${Mk}.u32 $fc, $Qn, $Qm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv4u32r (1400) - ARM_INS_VPT - vpt${Mk}.u32 $fc, $Qn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv8f16 (1401) - ARM_INS_VPT - vpt${Mk}.f16 $fc, $Qn, $Qm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv8f16r (1402) - ARM_INS_VPT - vpt${Mk}.f16 $fc, $Qn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv8i16 (1403) - ARM_INS_VPT - vpt${Mk}.i16 $fc, $Qn, $Qm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv8i16r (1404) - ARM_INS_VPT - vpt${Mk}.i16 $fc, $Qn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv8s16 (1405) - ARM_INS_VPT - vpt${Mk}.s16 $fc, $Qn, $Qm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv8s16r (1406) - ARM_INS_VPT - vpt${Mk}.s16 $fc, $Qn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv8u16 (1407) - ARM_INS_VPT - vpt${Mk}.u16 $fc, $Qn, $Qm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VPTv8u16r (1408) - ARM_INS_VPT - vpt${Mk}.u16 $fc, $Qn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */ + { 0 } } + }, + { /* ARM_MVE_VQABSs16 (1409) - ARM_INS_VQABS - vqabs${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQABSs32 (1410) - ARM_INS_VQABS - vqabs${vp}.s32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQABSs8 (1411) - ARM_INS_VQABS - vqabs${vp}.s8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQADD_qr_s16 (1412) - ARM_INS_VQADD - vqadd${vp}.s16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQADD_qr_s32 (1413) - ARM_INS_VQADD - vqadd${vp}.s32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQADD_qr_s8 (1414) - ARM_INS_VQADD - vqadd${vp}.s8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQADD_qr_u16 (1415) - ARM_INS_VQADD - vqadd${vp}.u16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQADD_qr_u32 (1416) - ARM_INS_VQADD - vqadd${vp}.u32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQADD_qr_u8 (1417) - ARM_INS_VQADD - vqadd${vp}.u8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQADDs16 (1418) - ARM_INS_VQADD - vqadd${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQADDs32 (1419) - ARM_INS_VQADD - vqadd${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQADDs8 (1420) - ARM_INS_VQADD - vqadd${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQADDu16 (1421) - ARM_INS_VQADD - vqadd${vp}.u16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQADDu32 (1422) - ARM_INS_VQADD - vqadd${vp}.u32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQADDu8 (1423) - ARM_INS_VQADD - vqadd${vp}.u8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMLADHXs16 (1424) - ARM_INS_VQDMLADHX - vqdmladhx${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLADHXs32 (1425) - ARM_INS_VQDMLADHX - vqdmladhx${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLADHXs8 (1426) - ARM_INS_VQDMLADHX - vqdmladhx${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLADHs16 (1427) - ARM_INS_VQDMLADH - vqdmladh${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLADHs32 (1428) - ARM_INS_VQDMLADH - vqdmladh${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLADHs8 (1429) - ARM_INS_VQDMLADH - vqdmladh${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLAH_qrs16 (1430) - ARM_INS_VQDMLAH - vqdmlah${vp}.s16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLAH_qrs32 (1431) - ARM_INS_VQDMLAH - vqdmlah${vp}.s32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLAH_qrs8 (1432) - ARM_INS_VQDMLAH - vqdmlah${vp}.s8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLASH_qrs16 (1433) - ARM_INS_VQDMLASH - vqdmlash${vp}.s16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLASH_qrs32 (1434) - ARM_INS_VQDMLASH - vqdmlash${vp}.s32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLASH_qrs8 (1435) - ARM_INS_VQDMLASH - vqdmlash${vp}.s8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLSDHXs16 (1436) - ARM_INS_VQDMLSDHX - vqdmlsdhx${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLSDHXs32 (1437) - ARM_INS_VQDMLSDHX - vqdmlsdhx${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLSDHXs8 (1438) - ARM_INS_VQDMLSDHX - vqdmlsdhx${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLSDHs16 (1439) - ARM_INS_VQDMLSDH - vqdmlsdh${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLSDHs32 (1440) - ARM_INS_VQDMLSDH - vqdmlsdh${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMLSDHs8 (1441) - ARM_INS_VQDMLSDH - vqdmlsdh${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQDMULH_qr_s16 (1442) - ARM_INS_VQDMULH - vqdmulh${vp}.s16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULH_qr_s32 (1443) - ARM_INS_VQDMULH - vqdmulh${vp}.s32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULH_qr_s8 (1444) - ARM_INS_VQDMULH - vqdmulh${vp}.s8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULHi16 (1445) - ARM_INS_VQDMULH - vqdmulh${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULHi32 (1446) - ARM_INS_VQDMULH - vqdmulh${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULHi8 (1447) - ARM_INS_VQDMULH - vqdmulh${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULL_qr_s16bh (1448) - ARM_INS_VQDMULLB - vqdmullb${vp}.s16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULL_qr_s16th (1449) - ARM_INS_VQDMULLT - vqdmullt${vp}.s16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULL_qr_s32bh (1450) - ARM_INS_VQDMULLB - vqdmullb${vp}.s32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULL_qr_s32th (1451) - ARM_INS_VQDMULLT - vqdmullt${vp}.s32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULLs16bh (1452) - ARM_INS_VQDMULLB - vqdmullb${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULLs16th (1453) - ARM_INS_VQDMULLT - vqdmullt${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULLs32bh (1454) - ARM_INS_VQDMULLB - vqdmullb${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQDMULLs32th (1455) - ARM_INS_VQDMULLT - vqdmullt${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQMOVNs16bh (1456) - ARM_INS_VQMOVNB - vqmovnb${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQMOVNs16th (1457) - ARM_INS_VQMOVNT - vqmovnt${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQMOVNs32bh (1458) - ARM_INS_VQMOVNB - vqmovnb${vp}.s32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQMOVNs32th (1459) - ARM_INS_VQMOVNT - vqmovnt${vp}.s32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQMOVNu16bh (1460) - ARM_INS_VQMOVNB - vqmovnb${vp}.u16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQMOVNu16th (1461) - ARM_INS_VQMOVNT - vqmovnt${vp}.u16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQMOVNu32bh (1462) - ARM_INS_VQMOVNB - vqmovnb${vp}.u32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQMOVNu32th (1463) - ARM_INS_VQMOVNT - vqmovnt${vp}.u32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQMOVUNs16bh (1464) - ARM_INS_VQMOVUNB - vqmovunb${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQMOVUNs16th (1465) - ARM_INS_VQMOVUNT - vqmovunt${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQMOVUNs32bh (1466) - ARM_INS_VQMOVUNB - vqmovunb${vp}.s32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQMOVUNs32th (1467) - ARM_INS_VQMOVUNT - vqmovunt${vp}.s32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQNEGs16 (1468) - ARM_INS_VQNEG - vqneg${vp}.s16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQNEGs32 (1469) - ARM_INS_VQNEG - vqneg${vp}.s32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQNEGs8 (1470) - ARM_INS_VQNEG - vqneg${vp}.s8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLADHXs16 (1471) - ARM_INS_VQRDMLADHX - vqrdmladhx${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLADHXs32 (1472) - ARM_INS_VQRDMLADHX - vqrdmladhx${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLADHXs8 (1473) - ARM_INS_VQRDMLADHX - vqrdmladhx${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLADHs16 (1474) - ARM_INS_VQRDMLADH - vqrdmladh${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLADHs32 (1475) - ARM_INS_VQRDMLADH - vqrdmladh${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLADHs8 (1476) - ARM_INS_VQRDMLADH - vqrdmladh${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLAH_qrs16 (1477) - ARM_INS_VQRDMLAH - vqrdmlah${vp}.s16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLAH_qrs32 (1478) - ARM_INS_VQRDMLAH - vqrdmlah${vp}.s32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLAH_qrs8 (1479) - ARM_INS_VQRDMLAH - vqrdmlah${vp}.s8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLASH_qrs16 (1480) - ARM_INS_VQRDMLASH - vqrdmlash${vp}.s16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLASH_qrs32 (1481) - ARM_INS_VQRDMLASH - vqrdmlash${vp}.s32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLASH_qrs8 (1482) - ARM_INS_VQRDMLASH - vqrdmlash${vp}.s8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLSDHXs16 (1483) - ARM_INS_VQRDMLSDHX - vqrdmlsdhx${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLSDHXs32 (1484) - ARM_INS_VQRDMLSDHX - vqrdmlsdhx${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLSDHXs8 (1485) - ARM_INS_VQRDMLSDHX - vqrdmlsdhx${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLSDHs16 (1486) - ARM_INS_VQRDMLSDH - vqrdmlsdh${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLSDHs32 (1487) - ARM_INS_VQRDMLSDH - vqrdmlsdh${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMLSDHs8 (1488) - ARM_INS_VQRDMLSDH - vqrdmlsdh${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRDMULH_qr_s16 (1489) - ARM_INS_VQRDMULH - vqrdmulh${vp}.s16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRDMULH_qr_s32 (1490) - ARM_INS_VQRDMULH - vqrdmulh${vp}.s32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRDMULH_qr_s8 (1491) - ARM_INS_VQRDMULH - vqrdmulh${vp}.s8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRDMULHi16 (1492) - ARM_INS_VQRDMULH - vqrdmulh${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRDMULHi32 (1493) - ARM_INS_VQRDMULH - vqrdmulh${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRDMULHi8 (1494) - ARM_INS_VQRDMULH - vqrdmulh${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRSHL_by_vecs16 (1495) - ARM_INS_VQRSHL - vqrshl${vp}.s16 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRSHL_by_vecs32 (1496) - ARM_INS_VQRSHL - vqrshl${vp}.s32 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRSHL_by_vecs8 (1497) - ARM_INS_VQRSHL - vqrshl${vp}.s8 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRSHL_by_vecu16 (1498) - ARM_INS_VQRSHL - vqrshl${vp}.u16 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRSHL_by_vecu32 (1499) - ARM_INS_VQRSHL - vqrshl${vp}.u32 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRSHL_by_vecu8 (1500) - ARM_INS_VQRSHL - vqrshl${vp}.u8 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQRSHL_qrs16 (1501) - ARM_INS_VQRSHL - vqrshl${vp}.s16 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHL_qrs32 (1502) - ARM_INS_VQRSHL - vqrshl${vp}.s32 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHL_qrs8 (1503) - ARM_INS_VQRSHL - vqrshl${vp}.s8 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHL_qru16 (1504) - ARM_INS_VQRSHL - vqrshl${vp}.u16 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHL_qru32 (1505) - ARM_INS_VQRSHL - vqrshl${vp}.u32 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHL_qru8 (1506) - ARM_INS_VQRSHL - vqrshl${vp}.u8 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHRNbhs16 (1507) - ARM_INS_VQRSHRNB - vqrshrnb${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHRNbhs32 (1508) - ARM_INS_VQRSHRNB - vqrshrnb${vp}.s32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHRNbhu16 (1509) - ARM_INS_VQRSHRNB - vqrshrnb${vp}.u16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHRNbhu32 (1510) - ARM_INS_VQRSHRNB - vqrshrnb${vp}.u32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHRNths16 (1511) - ARM_INS_VQRSHRNT - vqrshrnt${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHRNths32 (1512) - ARM_INS_VQRSHRNT - vqrshrnt${vp}.s32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHRNthu16 (1513) - ARM_INS_VQRSHRNT - vqrshrnt${vp}.u16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHRNthu32 (1514) - ARM_INS_VQRSHRNT - vqrshrnt${vp}.u32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHRUNs16bh (1515) - ARM_INS_VQRSHRUNB - vqrshrunb${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHRUNs16th (1516) - ARM_INS_VQRSHRUNT - vqrshrunt${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHRUNs32bh (1517) - ARM_INS_VQRSHRUNB - vqrshrunb${vp}.s32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQRSHRUNs32th (1518) - ARM_INS_VQRSHRUNT - vqrshrunt${vp}.s32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHLU_imms16 (1519) - ARM_INS_VQSHLU - vqshlu${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHLU_imms32 (1520) - ARM_INS_VQSHLU - vqshlu${vp}.s32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHLU_imms8 (1521) - ARM_INS_VQSHLU - vqshlu${vp}.s8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHL_by_vecs16 (1522) - ARM_INS_VQSHL - vqshl${vp}.s16 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHL_by_vecs32 (1523) - ARM_INS_VQSHL - vqshl${vp}.s32 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHL_by_vecs8 (1524) - ARM_INS_VQSHL - vqshl${vp}.s8 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHL_by_vecu16 (1525) - ARM_INS_VQSHL - vqshl${vp}.u16 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHL_by_vecu32 (1526) - ARM_INS_VQSHL - vqshl${vp}.u32 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHL_by_vecu8 (1527) - ARM_INS_VQSHL - vqshl${vp}.u8 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHL_qrs16 (1528) - ARM_INS_VQSHL - vqshl${vp}.s16 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHL_qrs32 (1529) - ARM_INS_VQSHL - vqshl${vp}.s32 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHL_qrs8 (1530) - ARM_INS_VQSHL - vqshl${vp}.s8 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHL_qru16 (1531) - ARM_INS_VQSHL - vqshl${vp}.u16 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHL_qru32 (1532) - ARM_INS_VQSHL - vqshl${vp}.u32 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHL_qru8 (1533) - ARM_INS_VQSHL - vqshl${vp}.u8 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHLimms16 (1534) - ARM_INS_VQSHL - vqshl${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHLimms32 (1535) - ARM_INS_VQSHL - vqshl${vp}.s32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHLimms8 (1536) - ARM_INS_VQSHL - vqshl${vp}.s8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHLimmu16 (1537) - ARM_INS_VQSHL - vqshl${vp}.u16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHLimmu32 (1538) - ARM_INS_VQSHL - vqshl${vp}.u32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHLimmu8 (1539) - ARM_INS_VQSHL - vqshl${vp}.u8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSHRNbhs16 (1540) - ARM_INS_VQSHRNB - vqshrnb${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHRNbhs32 (1541) - ARM_INS_VQSHRNB - vqshrnb${vp}.s32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHRNbhu16 (1542) - ARM_INS_VQSHRNB - vqshrnb${vp}.u16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHRNbhu32 (1543) - ARM_INS_VQSHRNB - vqshrnb${vp}.u32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHRNths16 (1544) - ARM_INS_VQSHRNT - vqshrnt${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHRNths32 (1545) - ARM_INS_VQSHRNT - vqshrnt${vp}.s32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHRNthu16 (1546) - ARM_INS_VQSHRNT - vqshrnt${vp}.u16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHRNthu32 (1547) - ARM_INS_VQSHRNT - vqshrnt${vp}.u32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHRUNs16bh (1548) - ARM_INS_VQSHRUNB - vqshrunb${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHRUNs16th (1549) - ARM_INS_VQSHRUNT - vqshrunt${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHRUNs32bh (1550) - ARM_INS_VQSHRUNB - vqshrunb${vp}.s32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSHRUNs32th (1551) - ARM_INS_VQSHRUNT - vqshrunt${vp}.s32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VQSUB_qr_s16 (1552) - ARM_INS_VQSUB - vqsub${vp}.s16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSUB_qr_s32 (1553) - ARM_INS_VQSUB - vqsub${vp}.s32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSUB_qr_s8 (1554) - ARM_INS_VQSUB - vqsub${vp}.s8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSUB_qr_u16 (1555) - ARM_INS_VQSUB - vqsub${vp}.u16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSUB_qr_u32 (1556) - ARM_INS_VQSUB - vqsub${vp}.u32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSUB_qr_u8 (1557) - ARM_INS_VQSUB - vqsub${vp}.u8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSUBs16 (1558) - ARM_INS_VQSUB - vqsub${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSUBs32 (1559) - ARM_INS_VQSUB - vqsub${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSUBs8 (1560) - ARM_INS_VQSUB - vqsub${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSUBu16 (1561) - ARM_INS_VQSUB - vqsub${vp}.u16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSUBu32 (1562) - ARM_INS_VQSUB - vqsub${vp}.u32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VQSUBu8 (1563) - ARM_INS_VQSUB - vqsub${vp}.u8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VREV16_8 (1564) - ARM_INS_VREV16 - vrev16${vp}.8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VREV32_16 (1565) - ARM_INS_VREV32 - vrev32${vp}.16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VREV32_8 (1566) - ARM_INS_VREV32 - vrev32${vp}.8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VREV64_16 (1567) - ARM_INS_VREV64 - vrev64${vp}.16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VREV64_32 (1568) - ARM_INS_VREV64 - vrev64${vp}.32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VREV64_8 (1569) - ARM_INS_VREV64 - vrev64${vp}.8 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRHADDs16 (1570) - ARM_INS_VRHADD - vrhadd${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRHADDs32 (1571) - ARM_INS_VRHADD - vrhadd${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRHADDs8 (1572) - ARM_INS_VRHADD - vrhadd${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRHADDu16 (1573) - ARM_INS_VRHADD - vrhadd${vp}.u16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRHADDu32 (1574) - ARM_INS_VRHADD - vrhadd${vp}.u32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRHADDu8 (1575) - ARM_INS_VRHADD - vrhadd${vp}.u8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRINTf16A (1576) - ARM_INS_VRINTA - vrinta${vp}.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRINTf16M (1577) - ARM_INS_VRINTM - vrintm${vp}.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRINTf16N (1578) - ARM_INS_VRINTN - vrintn${vp}.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRINTf16P (1579) - ARM_INS_VRINTP - vrintp${vp}.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRINTf16X (1580) - ARM_INS_VRINTX - vrintx${vp}.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRINTf16Z (1581) - ARM_INS_VRINTZ - vrintz${vp}.f16 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRINTf32A (1582) - ARM_INS_VRINTA - vrinta${vp}.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRINTf32M (1583) - ARM_INS_VRINTM - vrintm${vp}.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRINTf32N (1584) - ARM_INS_VRINTN - vrintn${vp}.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRINTf32P (1585) - ARM_INS_VRINTP - vrintp${vp}.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRINTf32X (1586) - ARM_INS_VRINTX - vrintx${vp}.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRINTf32Z (1587) - ARM_INS_VRINTZ - vrintz${vp}.f32 $Qd, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRMLALDAVHas32 (1588) - ARM_INS_VRMLALDAVHA - vrmlaldavha${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRMLALDAVHau32 (1589) - ARM_INS_VRMLALDAVHA - vrmlaldavha${vp}.u32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRMLALDAVHaxs32 (1590) - ARM_INS_VRMLALDAVHAX - vrmlaldavhax${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRMLALDAVHs32 (1591) - ARM_INS_VRMLALDAVH - vrmlaldavh${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRMLALDAVHu32 (1592) - ARM_INS_VRMLALDAVH - vrmlaldavh${vp}.u32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRMLALDAVHxs32 (1593) - ARM_INS_VRMLALDAVHX - vrmlaldavhx${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRMLSLDAVHas32 (1594) - ARM_INS_VRMLSLDAVHA - vrmlsldavha${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRMLSLDAVHaxs32 (1595) - ARM_INS_VRMLSLDAVHAX - vrmlsldavhax${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRMLSLDAVHs32 (1596) - ARM_INS_VRMLSLDAVH - vrmlsldavh${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRMLSLDAVHxs32 (1597) - ARM_INS_VRMLSLDAVHX - vrmlsldavhx${vp}.s32 $RdaLoDest, $RdaHiDest, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRMULHs16 (1598) - ARM_INS_VRMULH - vrmulh${vp}.s16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRMULHs32 (1599) - ARM_INS_VRMULH - vrmulh${vp}.s32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRMULHs8 (1600) - ARM_INS_VRMULH - vrmulh${vp}.s8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRMULHu16 (1601) - ARM_INS_VRMULH - vrmulh${vp}.u16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRMULHu32 (1602) - ARM_INS_VRMULH - vrmulh${vp}.u32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRMULHu8 (1603) - ARM_INS_VRMULH - vrmulh${vp}.u8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRSHL_by_vecs16 (1604) - ARM_INS_VRSHL - vrshl${vp}.s16 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRSHL_by_vecs32 (1605) - ARM_INS_VRSHL - vrshl${vp}.s32 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRSHL_by_vecs8 (1606) - ARM_INS_VRSHL - vrshl${vp}.s8 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRSHL_by_vecu16 (1607) - ARM_INS_VRSHL - vrshl${vp}.u16 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRSHL_by_vecu32 (1608) - ARM_INS_VRSHL - vrshl${vp}.u32 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRSHL_by_vecu8 (1609) - ARM_INS_VRSHL - vrshl${vp}.u8 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRSHL_qrs16 (1610) - ARM_INS_VRSHL - vrshl${vp}.s16 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRSHL_qrs32 (1611) - ARM_INS_VRSHL - vrshl${vp}.s32 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRSHL_qrs8 (1612) - ARM_INS_VRSHL - vrshl${vp}.s8 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRSHL_qru16 (1613) - ARM_INS_VRSHL - vrshl${vp}.u16 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRSHL_qru32 (1614) - ARM_INS_VRSHL - vrshl${vp}.u32 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRSHL_qru8 (1615) - ARM_INS_VRSHL - vrshl${vp}.u8 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRSHRNi16bh (1616) - ARM_INS_VRSHRNB - vrshrnb${vp}.i16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRSHRNi16th (1617) - ARM_INS_VRSHRNT - vrshrnt${vp}.i16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRSHRNi32bh (1618) - ARM_INS_VRSHRNB - vrshrnb${vp}.i32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRSHRNi32th (1619) - ARM_INS_VRSHRNT - vrshrnt${vp}.i32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VRSHR_imms16 (1620) - ARM_INS_VRSHR - vrshr${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRSHR_imms32 (1621) - ARM_INS_VRSHR - vrshr${vp}.s32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRSHR_imms8 (1622) - ARM_INS_VRSHR - vrshr${vp}.s8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRSHR_immu16 (1623) - ARM_INS_VRSHR - vrshr${vp}.u16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRSHR_immu32 (1624) - ARM_INS_VRSHR - vrshr${vp}.u32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VRSHR_immu8 (1625) - ARM_INS_VRSHR - vrshr${vp}.u8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSBC (1626) - ARM_INS_VSBC - vsbc${vp}.i32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* carryout */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* carryin */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSBCI (1627) - ARM_INS_VSBCI - vsbci${vp}.i32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* carryout */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLC (1628) - ARM_INS_VSHLC - vshlc${vp} $QdSrc, $RdmSrc, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdmDest */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdmSrc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_imms16bh (1629) - ARM_INS_VSHLLB - vshllb${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_imms16th (1630) - ARM_INS_VSHLLT - vshllt${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_imms8bh (1631) - ARM_INS_VSHLLB - vshllb${vp}.s8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_imms8th (1632) - ARM_INS_VSHLLT - vshllt${vp}.s8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_immu16bh (1633) - ARM_INS_VSHLLB - vshllb${vp}.u16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_immu16th (1634) - ARM_INS_VSHLLT - vshllt${vp}.u16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_immu8bh (1635) - ARM_INS_VSHLLB - vshllb${vp}.u8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_immu8th (1636) - ARM_INS_VSHLLT - vshllt${vp}.u8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_lws16bh (1637) - ARM_INS_VSHLLB - vshllb${vp}.s16 $Qd, $Qm, #16 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_lws16th (1638) - ARM_INS_VSHLLT - vshllt${vp}.s16 $Qd, $Qm, #16 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_lws8bh (1639) - ARM_INS_VSHLLB - vshllb${vp}.s8 $Qd, $Qm, #8 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_lws8th (1640) - ARM_INS_VSHLLT - vshllt${vp}.s8 $Qd, $Qm, #8 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_lwu16bh (1641) - ARM_INS_VSHLLB - vshllb${vp}.u16 $Qd, $Qm, #16 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_lwu16th (1642) - ARM_INS_VSHLLT - vshllt${vp}.u16 $Qd, $Qm, #16 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_lwu8bh (1643) - ARM_INS_VSHLLB - vshllb${vp}.u8 $Qd, $Qm, #8 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHLL_lwu8th (1644) - ARM_INS_VSHLLT - vshllt${vp}.u8 $Qd, $Qm, #8 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHL_by_vecs16 (1645) - ARM_INS_VSHL - vshl${vp}.s16 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHL_by_vecs32 (1646) - ARM_INS_VSHL - vshl${vp}.s32 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHL_by_vecs8 (1647) - ARM_INS_VSHL - vshl${vp}.s8 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHL_by_vecu16 (1648) - ARM_INS_VSHL - vshl${vp}.u16 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHL_by_vecu32 (1649) - ARM_INS_VSHL - vshl${vp}.u32 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHL_by_vecu8 (1650) - ARM_INS_VSHL - vshl${vp}.u8 $Qd, $Qm, $Qn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHL_immi16 (1651) - ARM_INS_VSHL - vshl${vp}.i16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHL_immi32 (1652) - ARM_INS_VSHL - vshl${vp}.i32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHL_immi8 (1653) - ARM_INS_VSHL - vshl${vp}.i8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHL_qrs16 (1654) - ARM_INS_VSHL - vshl${vp}.s16 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSHL_qrs32 (1655) - ARM_INS_VSHL - vshl${vp}.s32 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSHL_qrs8 (1656) - ARM_INS_VSHL - vshl${vp}.s8 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSHL_qru16 (1657) - ARM_INS_VSHL - vshl${vp}.u16 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSHL_qru32 (1658) - ARM_INS_VSHL - vshl${vp}.u32 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSHL_qru8 (1659) - ARM_INS_VSHL - vshl${vp}.u8 $Qd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSHRNi16bh (1660) - ARM_INS_VSHRNB - vshrnb${vp}.i16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSHRNi16th (1661) - ARM_INS_VSHRNT - vshrnt${vp}.i16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSHRNi32bh (1662) - ARM_INS_VSHRNB - vshrnb${vp}.i32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSHRNi32th (1663) - ARM_INS_VSHRNT - vshrnt${vp}.i32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSHR_imms16 (1664) - ARM_INS_VSHR - vshr${vp}.s16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHR_imms32 (1665) - ARM_INS_VSHR - vshr${vp}.s32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHR_imms8 (1666) - ARM_INS_VSHR - vshr${vp}.s8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHR_immu16 (1667) - ARM_INS_VSHR - vshr${vp}.u16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHR_immu32 (1668) - ARM_INS_VSHR - vshr${vp}.u32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSHR_immu8 (1669) - ARM_INS_VSHR - vshr${vp}.u8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSLIimm16 (1670) - ARM_INS_VSLI - vsli${vp}.16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSLIimm32 (1671) - ARM_INS_VSLI - vsli${vp}.32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSLIimm8 (1672) - ARM_INS_VSLI - vsli${vp}.8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSRIimm16 (1673) - ARM_INS_VSRI - vsri${vp}.16 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSRIimm32 (1674) - ARM_INS_VSRI - vsri${vp}.32 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSRIimm8 (1675) - ARM_INS_VSRI - vsri${vp}.8 $Qd, $Qm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VST20_16 (1676) - ARM_INS_VST20 - vst20.16 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST20_16_wb (1677) - ARM_INS_VST20 - vst20.16 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST20_32 (1678) - ARM_INS_VST20 - vst20.32 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST20_32_wb (1679) - ARM_INS_VST20 - vst20.32 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST20_8 (1680) - ARM_INS_VST20 - vst20.8 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST20_8_wb (1681) - ARM_INS_VST20 - vst20.8 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST21_16 (1682) - ARM_INS_VST21 - vst21.16 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST21_16_wb (1683) - ARM_INS_VST21 - vst21.16 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST21_32 (1684) - ARM_INS_VST21 - vst21.32 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST21_32_wb (1685) - ARM_INS_VST21 - vst21.32 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST21_8 (1686) - ARM_INS_VST21 - vst21.8 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST21_8_wb (1687) - ARM_INS_VST21 - vst21.8 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST40_16 (1688) - ARM_INS_VST40 - vst40.16 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST40_16_wb (1689) - ARM_INS_VST40 - vst40.16 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST40_32 (1690) - ARM_INS_VST40 - vst40.32 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST40_32_wb (1691) - ARM_INS_VST40 - vst40.32 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST40_8 (1692) - ARM_INS_VST40 - vst40.8 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST40_8_wb (1693) - ARM_INS_VST40 - vst40.8 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST41_16 (1694) - ARM_INS_VST41 - vst41.16 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST41_16_wb (1695) - ARM_INS_VST41 - vst41.16 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST41_32 (1696) - ARM_INS_VST41 - vst41.32 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST41_32_wb (1697) - ARM_INS_VST41 - vst41.32 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST41_8 (1698) - ARM_INS_VST41 - vst41.8 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST41_8_wb (1699) - ARM_INS_VST41 - vst41.8 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST42_16 (1700) - ARM_INS_VST42 - vst42.16 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST42_16_wb (1701) - ARM_INS_VST42 - vst42.16 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST42_32 (1702) - ARM_INS_VST42 - vst42.32 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST42_32_wb (1703) - ARM_INS_VST42 - vst42.32 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST42_8 (1704) - ARM_INS_VST42 - vst42.8 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST42_8_wb (1705) - ARM_INS_VST42 - vst42.8 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST43_16 (1706) - ARM_INS_VST43 - vst43.16 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST43_16_wb (1707) - ARM_INS_VST43 - vst43.16 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST43_32 (1708) - ARM_INS_VST43 - vst43.32 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST43_32_wb (1709) - ARM_INS_VST43 - vst43.32 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VST43_8 (1710) - ARM_INS_VST43 - vst43.8 $VQd, $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { 0 } } + }, + { /* ARM_MVE_VST43_8_wb (1711) - ARM_INS_VST43 - vst43.8 $VQd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { 0 } } + }, + { /* ARM_MVE_VSTRB16 (1712) - ARM_INS_VSTRB - vstrb${vp}.16 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRB16_post (1713) - ARM_INS_VSTRB - vstrb${vp}.16 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRB16_pre (1714) - ARM_INS_VSTRB - vstrb${vp}.16 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRB16_rq (1715) - ARM_INS_VSTRB - vstrb${vp}.16 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRB32 (1716) - ARM_INS_VSTRB - vstrb${vp}.32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRB32_post (1717) - ARM_INS_VSTRB - vstrb${vp}.32 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRB32_pre (1718) - ARM_INS_VSTRB - vstrb${vp}.32 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRB32_rq (1719) - ARM_INS_VSTRB - vstrb${vp}.32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRB8_rq (1720) - ARM_INS_VSTRB - vstrb${vp}.8 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRBU8 (1721) - ARM_INS_VSTRB - vstrb${vp}.8 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRBU8_post (1722) - ARM_INS_VSTRB - vstrb${vp}.8 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRBU8_pre (1723) - ARM_INS_VSTRB - vstrb${vp}.8 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRD64_qi (1724) - ARM_INS_VSTRD - vstrd${vp}.64 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRD64_qi_pre (1725) - ARM_INS_VSTRD - vstrd${vp}.64 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRD64_rq (1726) - ARM_INS_VSTRD - vstrd${vp}.64 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRD64_rq_u (1727) - ARM_INS_VSTRD - vstrd${vp}.64 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRH16_rq (1728) - ARM_INS_VSTRH - vstrh${vp}.16 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRH16_rq_u (1729) - ARM_INS_VSTRH - vstrh${vp}.16 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRH32 (1730) - ARM_INS_VSTRH - vstrh${vp}.32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRH32_post (1731) - ARM_INS_VSTRH - vstrh${vp}.32 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRH32_pre (1732) - ARM_INS_VSTRH - vstrh${vp}.32 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRH32_rq (1733) - ARM_INS_VSTRH - vstrh${vp}.32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRH32_rq_u (1734) - ARM_INS_VSTRH - vstrh${vp}.32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRHU16 (1735) - ARM_INS_VSTRH - vstrh${vp}.16 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRHU16_post (1736) - ARM_INS_VSTRH - vstrh${vp}.16 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRHU16_pre (1737) - ARM_INS_VSTRH - vstrh${vp}.16 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRW32_qi (1738) - ARM_INS_VSTRW - vstrw${vp}.32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRW32_qi_pre (1739) - ARM_INS_VSTRW - vstrw${vp}.32 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRW32_rq (1740) - ARM_INS_VSTRW - vstrw${vp}.32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRW32_rq_u (1741) - ARM_INS_VSTRW - vstrw${vp}.32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRWU32 (1742) - ARM_INS_VSTRW - vstrw${vp}.32 $Qd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRWU32_post (1743) - ARM_INS_VSTRW - vstrw${vp}.32 $Qd, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSTRWU32_pre (1744) - ARM_INS_VSTRW - vstrw${vp}.32 $Qd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { 0 } } + }, + { /* ARM_MVE_VSUB_qr_f16 (1745) - ARM_INS_VSUB - vsub${vp}.f16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSUB_qr_f32 (1746) - ARM_INS_VSUB - vsub${vp}.f32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSUB_qr_i16 (1747) - ARM_INS_VSUB - vsub${vp}.i16 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSUB_qr_i32 (1748) - ARM_INS_VSUB - vsub${vp}.i32 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSUB_qr_i8 (1749) - ARM_INS_VSUB - vsub${vp}.i8 $Qd, $Qn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSUBf16 (1750) - ARM_INS_VSUB - vsub${vp}.f16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSUBf32 (1751) - ARM_INS_VSUB - vsub${vp}.f32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSUBi16 (1752) - ARM_INS_VSUB - vsub${vp}.i16 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSUBi32 (1753) - ARM_INS_VSUB - vsub${vp}.i32 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_VSUBi8 (1754) - ARM_INS_VSUB - vsub${vp}.i8 $Qd, $Qn, $Qm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* vp - VCCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */ + { 0 } } + }, + { /* ARM_MVE_WLSTP_16 (1755) - ARM_INS_WLSTP - wlstp.16 $LR, $Rn, $label */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */ + { 0 } } + }, + { /* ARM_MVE_WLSTP_32 (1756) - ARM_INS_WLSTP - wlstp.32 $LR, $Rn, $label */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */ + { 0 } } + }, + { /* ARM_MVE_WLSTP_64 (1757) - ARM_INS_WLSTP - wlstp.64 $LR, $Rn, $label */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */ + { 0 } } + }, + { /* ARM_MVE_WLSTP_8 (1758) - ARM_INS_WLSTP - wlstp.8 $LR, $Rn, $label */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */ + { 0 } } + }, + { /* ARM_MVNi (1759) - ARM_INS_MVN - mvn${s}${p} $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_MVNr (1760) - ARM_INS_MVN - mvn${s}${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_MVNsi (1761) - ARM_INS_MVN - mvn${s}${p} $Rd, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_MVNsr (1762) - ARM_INS_MVN - mvn${s}${p} $Rd, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_NEON_VMAXNMNDf (1763) - ARM_INS_VMAXNM - vmaxnm.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_NEON_VMAXNMNDh (1764) - ARM_INS_VMAXNM - vmaxnm.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_NEON_VMAXNMNQf (1765) - ARM_INS_VMAXNM - vmaxnm.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_NEON_VMAXNMNQh (1766) - ARM_INS_VMAXNM - vmaxnm.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_NEON_VMINNMNDf (1767) - ARM_INS_VMINNM - vminnm.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_NEON_VMINNMNDh (1768) - ARM_INS_VMINNM - vminnm.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_NEON_VMINNMNQf (1769) - ARM_INS_VMINNM - vminnm.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_NEON_VMINNMNQh (1770) - ARM_INS_VMINNM - vminnm.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_ORRri (1771) - ARM_INS_ORR - orr${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ORRrr (1772) - ARM_INS_ORR - orr${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ORRrsi (1773) - ARM_INS_ORR - orr${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_ORRrsr (1774) - ARM_INS_ORR - orr${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_PKHBT (1775) - ARM_INS_PKHBT - pkhbt${p} $Rd, $Rn, $Rm$sh */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_PKHTB (1776) - ARM_INS_PKHTB - pkhtb${p} $Rd, $Rn, $Rm$sh */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_PLDWi12 (1777) - ARM_INS_PLDW - pldw $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { 0 } } + }, + { /* ARM_PLDWrs (1778) - ARM_INS_PLDW - pldw $shift */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { 0 } } + }, + { /* ARM_PLDi12 (1779) - ARM_INS_PLD - pld $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { 0 } } + }, + { /* ARM_PLDrs (1780) - ARM_INS_PLD - pld $shift */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { 0 } } + }, + { /* ARM_PLIi12 (1781) - ARM_INS_PLI - pli $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { 0 } } + }, + { /* ARM_PLIrs (1782) - ARM_INS_PLI - pli $shift */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { 0 } } + }, + { /* ARM_QADD (1783) - ARM_INS_QADD - qadd${p} $Rd, $Rm, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_QADD16 (1784) - ARM_INS_QADD16 - qadd16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_QADD8 (1785) - ARM_INS_QADD8 - qadd8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_QASX (1786) - ARM_INS_QASX - qasx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_QDADD (1787) - ARM_INS_QDADD - qdadd${p} $Rd, $Rm, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_QDSUB (1788) - ARM_INS_QDSUB - qdsub${p} $Rd, $Rm, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_QSAX (1789) - ARM_INS_QSAX - qsax${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_QSUB (1790) - ARM_INS_QSUB - qsub${p} $Rd, $Rm, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_QSUB16 (1791) - ARM_INS_QSUB16 - qsub16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_QSUB8 (1792) - ARM_INS_QSUB8 - qsub8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_RBIT (1793) - ARM_INS_RBIT - rbit${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_REV (1794) - ARM_INS_REV - rev${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_REV16 (1795) - ARM_INS_REV16 - rev16${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_REVSH (1796) - ARM_INS_REVSH - revsh${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_RFEDA (1797) - ARM_INS_RFEDA - rfeda $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_RFEDA_UPD (1798) - ARM_INS_RFEDA - rfeda $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_RFEDB (1799) - ARM_INS_RFEDB - rfedb $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_RFEDB_UPD (1800) - ARM_INS_RFEDB - rfedb $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_RFEIA (1801) - ARM_INS_RFEIA - rfeia $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_RFEIA_UPD (1802) - ARM_INS_RFEIA - rfeia $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_RFEIB (1803) - ARM_INS_RFEIB - rfeib $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_RFEIB_UPD (1804) - ARM_INS_RFEIB - rfeib $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_RSBri (1805) - ARM_INS_RSB - rsb${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_RSBrr (1806) - ARM_INS_RSB - rsb${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_RSBrsi (1807) - ARM_INS_RSB - rsb${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_RSBrsr (1808) - ARM_INS_RSB - rsb${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_RSCri (1809) - ARM_INS_RSC - rsc${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_RSCrr (1810) - ARM_INS_RSC - rsc${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_RSCrsi (1811) - ARM_INS_RSC - rsc${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_RSCrsr (1812) - ARM_INS_RSC - rsc${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_SADD16 (1813) - ARM_INS_SADD16 - sadd16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SADD8 (1814) - ARM_INS_SADD8 - sadd8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SASX (1815) - ARM_INS_SASX - sasx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SB (1816) - ARM_INS_SB - sb */ + { { 0 } } + }, + { /* ARM_SBCri (1817) - ARM_INS_SBC - sbc${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_SBCrr (1818) - ARM_INS_SBC - sbc${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_SBCrsi (1819) - ARM_INS_SBC - sbc${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_SBCrsr (1820) - ARM_INS_SBC - sbc${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_SBFX (1821) - ARM_INS_SBFX - sbfx${p} $Rd, $Rn, $lsb, $width */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lsb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SDIV (1822) - ARM_INS_SDIV - sdiv${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SEL (1823) - ARM_INS_SEL - sel${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SETEND (1824) - ARM_INS_SETEND - setend $end */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* end */ + { 0 } } + }, + { /* ARM_SETPAN (1825) - ARM_INS_SETPAN - setpan $imm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_SHA1C (1826) - ARM_INS_SHA1C - sha1c.32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_SHA1H (1827) - ARM_INS_SHA1H - sha1h.32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_SHA1M (1828) - ARM_INS_SHA1M - sha1m.32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_SHA1P (1829) - ARM_INS_SHA1P - sha1p.32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_SHA1SU0 (1830) - ARM_INS_SHA1SU0 - sha1su0.32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_SHA1SU1 (1831) - ARM_INS_SHA1SU1 - sha1su1.32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_SHA256H (1832) - ARM_INS_SHA256H - sha256h.32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_SHA256H2 (1833) - ARM_INS_SHA256H2 - sha256h2.32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_SHA256SU0 (1834) - ARM_INS_SHA256SU0 - sha256su0.32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_SHA256SU1 (1835) - ARM_INS_SHA256SU1 - sha256su1.32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_SHADD16 (1836) - ARM_INS_SHADD16 - shadd16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SHADD8 (1837) - ARM_INS_SHADD8 - shadd8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SHASX (1838) - ARM_INS_SHASX - shasx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SHSAX (1839) - ARM_INS_SHSAX - shsax${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SHSUB16 (1840) - ARM_INS_SHSUB16 - shsub16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SHSUB8 (1841) - ARM_INS_SHSUB8 - shsub8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMC (1842) - ARM_INS_SMC - smc${p} $opt */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLABB (1843) - ARM_INS_SMLABB - smlabb${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLABT (1844) - ARM_INS_SMLABT - smlabt${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLAD (1845) - ARM_INS_SMLAD - smlad${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLADX (1846) - ARM_INS_SMLADX - smladx${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLAL (1847) - ARM_INS_SMLAL - smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_SMLALBB (1848) - ARM_INS_SMLALBB - smlalbb${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLALBT (1849) - ARM_INS_SMLALBT - smlalbt${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLALD (1850) - ARM_INS_SMLALD - smlald${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLALDX (1851) - ARM_INS_SMLALDX - smlaldx${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLALTB (1852) - ARM_INS_SMLALTB - smlaltb${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLALTT (1853) - ARM_INS_SMLALTT - smlaltt${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLATB (1854) - ARM_INS_SMLATB - smlatb${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLATT (1855) - ARM_INS_SMLATT - smlatt${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLAWB (1856) - ARM_INS_SMLAWB - smlawb${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLAWT (1857) - ARM_INS_SMLAWT - smlawt${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLSD (1858) - ARM_INS_SMLSD - smlsd${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLSDX (1859) - ARM_INS_SMLSDX - smlsdx${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLSLD (1860) - ARM_INS_SMLSLD - smlsld${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMLSLDX (1861) - ARM_INS_SMLSLDX - smlsldx${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMMLA (1862) - ARM_INS_SMMLA - smmla${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMMLAR (1863) - ARM_INS_SMMLAR - smmlar${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMMLS (1864) - ARM_INS_SMMLS - smmls${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMMLSR (1865) - ARM_INS_SMMLSR - smmlsr${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMMUL (1866) - ARM_INS_SMMUL - smmul${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMMULR (1867) - ARM_INS_SMMULR - smmulr${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMUAD (1868) - ARM_INS_SMUAD - smuad${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMUADX (1869) - ARM_INS_SMUADX - smuadx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMULBB (1870) - ARM_INS_SMULBB - smulbb${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMULBT (1871) - ARM_INS_SMULBT - smulbt${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMULL (1872) - ARM_INS_SMULL - smull${s}${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_SMULTB (1873) - ARM_INS_SMULTB - smultb${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMULTT (1874) - ARM_INS_SMULTT - smultt${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMULWB (1875) - ARM_INS_SMULWB - smulwb${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMULWT (1876) - ARM_INS_SMULWT - smulwt${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMUSD (1877) - ARM_INS_SMUSD - smusd${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SMUSDX (1878) - ARM_INS_SMUSDX - smusdx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SRSDA (1879) - ARM_INS_SRSDA - srsda sp, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { 0 } } + }, + { /* ARM_SRSDA_UPD (1880) - ARM_INS_SRSDA - srsda sp!, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { 0 } } + }, + { /* ARM_SRSDB (1881) - ARM_INS_SRSDB - srsdb sp, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { 0 } } + }, + { /* ARM_SRSDB_UPD (1882) - ARM_INS_SRSDB - srsdb sp!, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { 0 } } + }, + { /* ARM_SRSIA (1883) - ARM_INS_SRSIA - srsia sp, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { 0 } } + }, + { /* ARM_SRSIA_UPD (1884) - ARM_INS_SRSIA - srsia sp!, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { 0 } } + }, + { /* ARM_SRSIB (1885) - ARM_INS_SRSIB - srsib sp, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { 0 } } + }, + { /* ARM_SRSIB_UPD (1886) - ARM_INS_SRSIB - srsib sp!, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { 0 } } + }, + { /* ARM_SSAT (1887) - ARM_INS_SSAT - ssat${p} $Rd, $sat_imm, $Rn$sh */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SSAT16 (1888) - ARM_INS_SSAT16 - ssat16${p} $Rd, $sat_imm, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SSAX (1889) - ARM_INS_SSAX - ssax${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SSUB16 (1890) - ARM_INS_SSUB16 - ssub16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SSUB8 (1891) - ARM_INS_SSUB8 - ssub8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STC2L_OFFSET (1892) - ARM_INS_STC2L - stc2l $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { 0 } } + }, + { /* ARM_STC2L_OPTION (1893) - ARM_INS_STC2L - stc2l $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { 0 } } + }, + { /* ARM_STC2L_POST (1894) - ARM_INS_STC2L - stc2l $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { 0 } } + }, + { /* ARM_STC2L_PRE (1895) - ARM_INS_STC2L - stc2l $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { 0 } } + }, + { /* ARM_STC2_OFFSET (1896) - ARM_INS_STC2 - stc2 $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { 0 } } + }, + { /* ARM_STC2_OPTION (1897) - ARM_INS_STC2 - stc2 $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { 0 } } + }, + { /* ARM_STC2_POST (1898) - ARM_INS_STC2 - stc2 $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { 0 } } + }, + { /* ARM_STC2_PRE (1899) - ARM_INS_STC2 - stc2 $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { 0 } } + }, + { /* ARM_STCL_OFFSET (1900) - ARM_INS_STCL - stcl${p} $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STCL_OPTION (1901) - ARM_INS_STCL - stcl${p} $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STCL_POST (1902) - ARM_INS_STCL - stcl${p} $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STCL_PRE (1903) - ARM_INS_STCL - stcl${p} $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STC_OFFSET (1904) - ARM_INS_STC - stc${p} $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STC_OPTION (1905) - ARM_INS_STC - stc${p} $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STC_POST (1906) - ARM_INS_STC - stc${p} $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STC_PRE (1907) - ARM_INS_STC - stc${p} $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STL (1908) - ARM_INS_STL - stl${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STLB (1909) - ARM_INS_STLB - stlb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STLEX (1910) - ARM_INS_STLEX - stlex${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STLEXB (1911) - ARM_INS_STLEXB - stlexb${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STLEXD (1912) - ARM_INS_STLEXD - stlexd${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STLEXH (1913) - ARM_INS_STLEXH - stlexh${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STLH (1914) - ARM_INS_STLH - stlh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STMDA (1915) - ARM_INS_STMDA - stmda${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_STMDA_UPD (1916) - ARM_INS_STMDA - stmda${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_STMDB (1917) - ARM_INS_STMDB - stmdb${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_STMDB_UPD (1918) - ARM_INS_STMDB - stmdb${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_STMIA (1919) - ARM_INS_STM - stm${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_STMIA_UPD (1920) - ARM_INS_STM - stm${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_STMIB (1921) - ARM_INS_STMIB - stmib${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_STMIB_UPD (1922) - ARM_INS_STMIB - stmib${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_STRBT_POST_IMM (1923) - ARM_INS_STRBT - strbt${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRBT_POST_REG (1924) - ARM_INS_STRBT - strbt${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRB_POST_IMM (1925) - ARM_INS_STRB - strb${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRB_POST_REG (1926) - ARM_INS_STRB - strb${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRB_PRE_IMM (1927) - ARM_INS_STRB - strb${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRB_PRE_REG (1928) - ARM_INS_STRB - strb${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRBi12 (1929) - ARM_INS_STRB - strb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRBrs (1930) - ARM_INS_STRB - strb${p} $Rt, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRD (1931) - ARM_INS_STRD - strd${p} $Rt, $Rt2, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRD_POST (1932) - ARM_INS_STRD - strd${p} $Rt, $Rt2, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRD_PRE (1933) - ARM_INS_STRD - strd${p} $Rt, $Rt2, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STREX (1934) - ARM_INS_STREX - strex${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STREXB (1935) - ARM_INS_STREXB - strexb${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STREXD (1936) - ARM_INS_STREXD - strexd${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STREXH (1937) - ARM_INS_STREXH - strexh${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRH (1938) - ARM_INS_STRH - strh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRHTi (1939) - ARM_INS_STRHT - strht${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRHTr (1940) - ARM_INS_STRHT - strht${p} $Rt, $addr, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRH_POST (1941) - ARM_INS_STRH - strh${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRH_PRE (1942) - ARM_INS_STRH - strh${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRT_POST_IMM (1943) - ARM_INS_STRT - strt${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRT_POST_REG (1944) - ARM_INS_STRT - strt${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STR_POST_IMM (1945) - ARM_INS_STR - str${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STR_POST_REG (1946) - ARM_INS_STR - str${p} $Rt, $addr, $offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STR_PRE_IMM (1947) - ARM_INS_STR - str${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STR_PRE_REG (1948) - ARM_INS_STR - str${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRi12 (1949) - ARM_INS_STR - str${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_STRrs (1950) - ARM_INS_STR - str${p} $Rt, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SUBri (1951) - ARM_INS_SUB - sub${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_SUBrr (1952) - ARM_INS_SUB - sub${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_SUBrsi (1953) - ARM_INS_SUB - sub${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_SUBrsr (1954) - ARM_INS_SUB - sub${s}${p} $Rd, $Rn, $shift */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_SVC (1955) - ARM_INS_SVC - svc${p} $svc */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* svc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SWP (1956) - ARM_INS_SWP - swp${p} $Rt, $Rt2, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SWPB (1957) - ARM_INS_SWPB - swpb${p} $Rt, $Rt2, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SXTAB (1958) - ARM_INS_SXTAB - sxtab${p} $Rd, $Rn, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SXTAB16 (1959) - ARM_INS_SXTAB16 - sxtab16${p} $Rd, $Rn, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SXTAH (1960) - ARM_INS_SXTAH - sxtah${p} $Rd, $Rn, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SXTB (1961) - ARM_INS_SXTB - sxtb${p} $Rd, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SXTB16 (1962) - ARM_INS_SXTB16 - sxtb16${p} $Rd, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_SXTH (1963) - ARM_INS_SXTH - sxth${p} $Rd, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_TEQri (1964) - ARM_INS_TEQ - teq${p} $Rn, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_TEQrr (1965) - ARM_INS_TEQ - teq${p} $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_TEQrsi (1966) - ARM_INS_TEQ - teq${p} $Rn, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_TEQrsr (1967) - ARM_INS_TEQ - teq${p} $Rn, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_TRAP (1968) - ARM_INS_TRAP - trap */ + { { 0 } } + }, + { /* ARM_TRAPNaCl (1969) - ARM_INS_TRAP - trap */ + { { 0 } } + }, + { /* ARM_TSB (1970) - ARM_INS_TSB - tsb $opt */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */ + { 0 } } + }, + { /* ARM_TSTri (1971) - ARM_INS_TST - tst${p} $Rn, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_TSTrr (1972) - ARM_INS_TST - tst${p} $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_TSTrsi (1973) - ARM_INS_TST - tst${p} $Rn, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_TSTrsr (1974) - ARM_INS_TST - tst${p} $Rn, $shift */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UADD16 (1975) - ARM_INS_UADD16 - uadd16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UADD8 (1976) - ARM_INS_UADD8 - uadd8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UASX (1977) - ARM_INS_UASX - uasx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UBFX (1978) - ARM_INS_UBFX - ubfx${p} $Rd, $Rn, $lsb, $width */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lsb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UDF (1979) - ARM_INS_UDF - udf $imm16 */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } } + }, + { /* ARM_UDIV (1980) - ARM_INS_UDIV - udiv${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UHADD16 (1981) - ARM_INS_UHADD16 - uhadd16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UHADD8 (1982) - ARM_INS_UHADD8 - uhadd8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UHASX (1983) - ARM_INS_UHASX - uhasx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UHSAX (1984) - ARM_INS_UHSAX - uhsax${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UHSUB16 (1985) - ARM_INS_UHSUB16 - uhsub16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UHSUB8 (1986) - ARM_INS_UHSUB8 - uhsub8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UMAAL (1987) - ARM_INS_UMAAL - umaal${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UMLAL (1988) - ARM_INS_UMLAL - umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_UMULL (1989) - ARM_INS_UMULL - umull${s}${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_UQADD16 (1990) - ARM_INS_UQADD16 - uqadd16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UQADD8 (1991) - ARM_INS_UQADD8 - uqadd8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UQASX (1992) - ARM_INS_UQASX - uqasx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UQSAX (1993) - ARM_INS_UQSAX - uqsax${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UQSUB16 (1994) - ARM_INS_UQSUB16 - uqsub16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UQSUB8 (1995) - ARM_INS_UQSUB8 - uqsub8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_USAD8 (1996) - ARM_INS_USAD8 - usad8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_USADA8 (1997) - ARM_INS_USADA8 - usada8${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_USAT (1998) - ARM_INS_USAT - usat${p} $Rd, $sat_imm, $Rn$sh */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_USAT16 (1999) - ARM_INS_USAT16 - usat16${p} $Rd, $sat_imm, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_USAX (2000) - ARM_INS_USAX - usax${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_USUB16 (2001) - ARM_INS_USUB16 - usub16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_USUB8 (2002) - ARM_INS_USUB8 - usub8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UXTAB (2003) - ARM_INS_UXTAB - uxtab${p} $Rd, $Rn, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UXTAB16 (2004) - ARM_INS_UXTAB16 - uxtab16${p} $Rd, $Rn, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UXTAH (2005) - ARM_INS_UXTAH - uxtah${p} $Rd, $Rn, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UXTB (2006) - ARM_INS_UXTB - uxtb${p} $Rd, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UXTB16 (2007) - ARM_INS_UXTB16 - uxtb16${p} $Rd, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_UXTH (2008) - ARM_INS_UXTH - uxth${p} $Rd, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABALsv2i64 (2009) - ARM_INS_VABAL - vabal${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABALsv4i32 (2010) - ARM_INS_VABAL - vabal${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABALsv8i16 (2011) - ARM_INS_VABAL - vabal${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABALuv2i64 (2012) - ARM_INS_VABAL - vabal${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABALuv4i32 (2013) - ARM_INS_VABAL - vabal${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABALuv8i16 (2014) - ARM_INS_VABAL - vabal${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABAsv16i8 (2015) - ARM_INS_VABA - vaba${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABAsv2i32 (2016) - ARM_INS_VABA - vaba${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABAsv4i16 (2017) - ARM_INS_VABA - vaba${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABAsv4i32 (2018) - ARM_INS_VABA - vaba${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABAsv8i16 (2019) - ARM_INS_VABA - vaba${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABAsv8i8 (2020) - ARM_INS_VABA - vaba${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABAuv16i8 (2021) - ARM_INS_VABA - vaba${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABAuv2i32 (2022) - ARM_INS_VABA - vaba${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABAuv4i16 (2023) - ARM_INS_VABA - vaba${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABAuv4i32 (2024) - ARM_INS_VABA - vaba${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABAuv8i16 (2025) - ARM_INS_VABA - vaba${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABAuv8i8 (2026) - ARM_INS_VABA - vaba${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDLsv2i64 (2027) - ARM_INS_VABDL - vabdl${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDLsv4i32 (2028) - ARM_INS_VABDL - vabdl${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDLsv8i16 (2029) - ARM_INS_VABDL - vabdl${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDLuv2i64 (2030) - ARM_INS_VABDL - vabdl${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDLuv4i32 (2031) - ARM_INS_VABDL - vabdl${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDLuv8i16 (2032) - ARM_INS_VABDL - vabdl${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDfd (2033) - ARM_INS_VABD - vabd${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDfq (2034) - ARM_INS_VABD - vabd${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDhd (2035) - ARM_INS_VABD - vabd${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDhq (2036) - ARM_INS_VABD - vabd${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDsv16i8 (2037) - ARM_INS_VABD - vabd${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDsv2i32 (2038) - ARM_INS_VABD - vabd${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDsv4i16 (2039) - ARM_INS_VABD - vabd${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDsv4i32 (2040) - ARM_INS_VABD - vabd${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDsv8i16 (2041) - ARM_INS_VABD - vabd${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDsv8i8 (2042) - ARM_INS_VABD - vabd${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDuv16i8 (2043) - ARM_INS_VABD - vabd${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDuv2i32 (2044) - ARM_INS_VABD - vabd${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDuv4i16 (2045) - ARM_INS_VABD - vabd${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDuv4i32 (2046) - ARM_INS_VABD - vabd${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDuv8i16 (2047) - ARM_INS_VABD - vabd${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABDuv8i8 (2048) - ARM_INS_VABD - vabd${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABSD (2049) - ARM_INS_VABS - vabs${p}.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABSH (2050) - ARM_INS_VABS - vabs${p}.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABSS (2051) - ARM_INS_VABS - vabs${p}.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABSfd (2052) - ARM_INS_VABS - vabs${p}.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABSfq (2053) - ARM_INS_VABS - vabs${p}.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABShd (2054) - ARM_INS_VABS - vabs${p}.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABShq (2055) - ARM_INS_VABS - vabs${p}.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABSv16i8 (2056) - ARM_INS_VABS - vabs${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABSv2i32 (2057) - ARM_INS_VABS - vabs${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABSv4i16 (2058) - ARM_INS_VABS - vabs${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABSv4i32 (2059) - ARM_INS_VABS - vabs${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABSv8i16 (2060) - ARM_INS_VABS - vabs${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VABSv8i8 (2061) - ARM_INS_VABS - vabs${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VACGEfd (2062) - ARM_INS_VACGE - vacge${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VACGEfq (2063) - ARM_INS_VACGE - vacge${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VACGEhd (2064) - ARM_INS_VACGE - vacge${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VACGEhq (2065) - ARM_INS_VACGE - vacge${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VACGTfd (2066) - ARM_INS_VACGT - vacgt${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VACGTfq (2067) - ARM_INS_VACGT - vacgt${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VACGThd (2068) - ARM_INS_VACGT - vacgt${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VACGThq (2069) - ARM_INS_VACGT - vacgt${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDD (2070) - ARM_INS_VADD - vadd${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDH (2071) - ARM_INS_VADD - vadd${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDHNv2i32 (2072) - ARM_INS_VADDHN - vaddhn${p}.i64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDHNv4i16 (2073) - ARM_INS_VADDHN - vaddhn${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDHNv8i8 (2074) - ARM_INS_VADDHN - vaddhn${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDLsv2i64 (2075) - ARM_INS_VADDL - vaddl${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDLsv4i32 (2076) - ARM_INS_VADDL - vaddl${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDLsv8i16 (2077) - ARM_INS_VADDL - vaddl${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDLuv2i64 (2078) - ARM_INS_VADDL - vaddl${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDLuv4i32 (2079) - ARM_INS_VADDL - vaddl${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDLuv8i16 (2080) - ARM_INS_VADDL - vaddl${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDS (2081) - ARM_INS_VADD - vadd${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDWsv2i64 (2082) - ARM_INS_VADDW - vaddw${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDWsv4i32 (2083) - ARM_INS_VADDW - vaddw${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDWsv8i16 (2084) - ARM_INS_VADDW - vaddw${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDWuv2i64 (2085) - ARM_INS_VADDW - vaddw${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDWuv4i32 (2086) - ARM_INS_VADDW - vaddw${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDWuv8i16 (2087) - ARM_INS_VADDW - vaddw${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDfd (2088) - ARM_INS_VADD - vadd${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDfq (2089) - ARM_INS_VADD - vadd${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDhd (2090) - ARM_INS_VADD - vadd${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDhq (2091) - ARM_INS_VADD - vadd${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDv16i8 (2092) - ARM_INS_VADD - vadd${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDv1i64 (2093) - ARM_INS_VADD - vadd${p}.i64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDv2i32 (2094) - ARM_INS_VADD - vadd${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDv2i64 (2095) - ARM_INS_VADD - vadd${p}.i64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDv4i16 (2096) - ARM_INS_VADD - vadd${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDv4i32 (2097) - ARM_INS_VADD - vadd${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDv8i16 (2098) - ARM_INS_VADD - vadd${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VADDv8i8 (2099) - ARM_INS_VADD - vadd${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VANDd (2100) - ARM_INS_VAND - vand${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VANDq (2101) - ARM_INS_VAND - vand${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VBF16MALBQ (2102) - ARM_INS_VFMAB - vfmab.bf16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VBF16MALBQI (2103) - ARM_INS_VFMAB - vfmab.bf16 $Vd, $Vn, $Vm$idx */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */ + { 0 } } + }, + { /* ARM_VBF16MALTQ (2104) - ARM_INS_VFMAT - vfmat.bf16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VBF16MALTQI (2105) - ARM_INS_VFMAT - vfmat.bf16 $Vd, $Vn, $Vm$idx */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */ + { 0 } } + }, + { /* ARM_VBICd (2106) - ARM_INS_VBIC - vbic${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VBICiv2i32 (2107) - ARM_INS_VBIC - vbic${p}.i32 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VBICiv4i16 (2108) - ARM_INS_VBIC - vbic${p}.i16 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VBICiv4i32 (2109) - ARM_INS_VBIC - vbic${p}.i32 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VBICiv8i16 (2110) - ARM_INS_VBIC - vbic${p}.i16 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VBICq (2111) - ARM_INS_VBIC - vbic${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VBIFd (2112) - ARM_INS_VBIF - vbif${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VBIFq (2113) - ARM_INS_VBIF - vbif${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VBITd (2114) - ARM_INS_VBIT - vbit${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VBITq (2115) - ARM_INS_VBIT - vbit${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VBSLd (2116) - ARM_INS_VBSL - vbsl${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VBSLq (2117) - ARM_INS_VBSL - vbsl${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VBSPd (2118) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VBSPq (2119) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VCADDv2f32 (2120) - ARM_INS_VCADD - vcadd.f32 $Vd, $Vn, $Vm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { 0 } } + }, + { /* ARM_VCADDv4f16 (2121) - ARM_INS_VCADD - vcadd.f16 $Vd, $Vn, $Vm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { 0 } } + }, + { /* ARM_VCADDv4f32 (2122) - ARM_INS_VCADD - vcadd.f32 $Vd, $Vn, $Vm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { 0 } } + }, + { /* ARM_VCADDv8f16 (2123) - ARM_INS_VCADD - vcadd.f16 $Vd, $Vn, $Vm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { 0 } } + }, + { /* ARM_VCEQfd (2124) - ARM_INS_VCEQ - vceq${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQfq (2125) - ARM_INS_VCEQ - vceq${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQhd (2126) - ARM_INS_VCEQ - vceq${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQhq (2127) - ARM_INS_VCEQ - vceq${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQv16i8 (2128) - ARM_INS_VCEQ - vceq${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQv2i32 (2129) - ARM_INS_VCEQ - vceq${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQv4i16 (2130) - ARM_INS_VCEQ - vceq${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQv4i32 (2131) - ARM_INS_VCEQ - vceq${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQv8i16 (2132) - ARM_INS_VCEQ - vceq${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQv8i8 (2133) - ARM_INS_VCEQ - vceq${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQzv16i8 (2134) - ARM_INS_VCEQ - vceq${p}.i8 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQzv2f32 (2135) - ARM_INS_VCEQ - vceq${p}.f32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQzv2i32 (2136) - ARM_INS_VCEQ - vceq${p}.i32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQzv4f16 (2137) - ARM_INS_VCEQ - vceq${p}.f16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQzv4f32 (2138) - ARM_INS_VCEQ - vceq${p}.f32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQzv4i16 (2139) - ARM_INS_VCEQ - vceq${p}.i16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQzv4i32 (2140) - ARM_INS_VCEQ - vceq${p}.i32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQzv8f16 (2141) - ARM_INS_VCEQ - vceq${p}.f16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQzv8i16 (2142) - ARM_INS_VCEQ - vceq${p}.i16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCEQzv8i8 (2143) - ARM_INS_VCEQ - vceq${p}.i8 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEfd (2144) - ARM_INS_VCGE - vcge${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEfq (2145) - ARM_INS_VCGE - vcge${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEhd (2146) - ARM_INS_VCGE - vcge${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEhq (2147) - ARM_INS_VCGE - vcge${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEsv16i8 (2148) - ARM_INS_VCGE - vcge${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEsv2i32 (2149) - ARM_INS_VCGE - vcge${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEsv4i16 (2150) - ARM_INS_VCGE - vcge${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEsv4i32 (2151) - ARM_INS_VCGE - vcge${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEsv8i16 (2152) - ARM_INS_VCGE - vcge${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEsv8i8 (2153) - ARM_INS_VCGE - vcge${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEuv16i8 (2154) - ARM_INS_VCGE - vcge${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEuv2i32 (2155) - ARM_INS_VCGE - vcge${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEuv4i16 (2156) - ARM_INS_VCGE - vcge${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEuv4i32 (2157) - ARM_INS_VCGE - vcge${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEuv8i16 (2158) - ARM_INS_VCGE - vcge${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEuv8i8 (2159) - ARM_INS_VCGE - vcge${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEzv16i8 (2160) - ARM_INS_VCGE - vcge${p}.s8 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEzv2f32 (2161) - ARM_INS_VCGE - vcge${p}.f32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEzv2i32 (2162) - ARM_INS_VCGE - vcge${p}.s32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEzv4f16 (2163) - ARM_INS_VCGE - vcge${p}.f16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEzv4f32 (2164) - ARM_INS_VCGE - vcge${p}.f32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEzv4i16 (2165) - ARM_INS_VCGE - vcge${p}.s16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEzv4i32 (2166) - ARM_INS_VCGE - vcge${p}.s32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEzv8f16 (2167) - ARM_INS_VCGE - vcge${p}.f16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEzv8i16 (2168) - ARM_INS_VCGE - vcge${p}.s16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGEzv8i8 (2169) - ARM_INS_VCGE - vcge${p}.s8 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTfd (2170) - ARM_INS_VCGT - vcgt${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTfq (2171) - ARM_INS_VCGT - vcgt${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGThd (2172) - ARM_INS_VCGT - vcgt${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGThq (2173) - ARM_INS_VCGT - vcgt${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTsv16i8 (2174) - ARM_INS_VCGT - vcgt${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTsv2i32 (2175) - ARM_INS_VCGT - vcgt${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTsv4i16 (2176) - ARM_INS_VCGT - vcgt${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTsv4i32 (2177) - ARM_INS_VCGT - vcgt${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTsv8i16 (2178) - ARM_INS_VCGT - vcgt${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTsv8i8 (2179) - ARM_INS_VCGT - vcgt${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTuv16i8 (2180) - ARM_INS_VCGT - vcgt${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTuv2i32 (2181) - ARM_INS_VCGT - vcgt${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTuv4i16 (2182) - ARM_INS_VCGT - vcgt${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTuv4i32 (2183) - ARM_INS_VCGT - vcgt${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTuv8i16 (2184) - ARM_INS_VCGT - vcgt${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTuv8i8 (2185) - ARM_INS_VCGT - vcgt${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTzv16i8 (2186) - ARM_INS_VCGT - vcgt${p}.s8 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTzv2f32 (2187) - ARM_INS_VCGT - vcgt${p}.f32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTzv2i32 (2188) - ARM_INS_VCGT - vcgt${p}.s32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTzv4f16 (2189) - ARM_INS_VCGT - vcgt${p}.f16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTzv4f32 (2190) - ARM_INS_VCGT - vcgt${p}.f32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTzv4i16 (2191) - ARM_INS_VCGT - vcgt${p}.s16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTzv4i32 (2192) - ARM_INS_VCGT - vcgt${p}.s32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTzv8f16 (2193) - ARM_INS_VCGT - vcgt${p}.f16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTzv8i16 (2194) - ARM_INS_VCGT - vcgt${p}.s16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCGTzv8i8 (2195) - ARM_INS_VCGT - vcgt${p}.s8 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLEzv16i8 (2196) - ARM_INS_VCLE - vcle${p}.s8 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLEzv2f32 (2197) - ARM_INS_VCLE - vcle${p}.f32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLEzv2i32 (2198) - ARM_INS_VCLE - vcle${p}.s32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLEzv4f16 (2199) - ARM_INS_VCLE - vcle${p}.f16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLEzv4f32 (2200) - ARM_INS_VCLE - vcle${p}.f32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLEzv4i16 (2201) - ARM_INS_VCLE - vcle${p}.s16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLEzv4i32 (2202) - ARM_INS_VCLE - vcle${p}.s32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLEzv8f16 (2203) - ARM_INS_VCLE - vcle${p}.f16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLEzv8i16 (2204) - ARM_INS_VCLE - vcle${p}.s16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLEzv8i8 (2205) - ARM_INS_VCLE - vcle${p}.s8 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLSv16i8 (2206) - ARM_INS_VCLS - vcls${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLSv2i32 (2207) - ARM_INS_VCLS - vcls${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLSv4i16 (2208) - ARM_INS_VCLS - vcls${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLSv4i32 (2209) - ARM_INS_VCLS - vcls${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLSv8i16 (2210) - ARM_INS_VCLS - vcls${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLSv8i8 (2211) - ARM_INS_VCLS - vcls${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLTzv16i8 (2212) - ARM_INS_VCLT - vclt${p}.s8 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLTzv2f32 (2213) - ARM_INS_VCLT - vclt${p}.f32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLTzv2i32 (2214) - ARM_INS_VCLT - vclt${p}.s32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLTzv4f16 (2215) - ARM_INS_VCLT - vclt${p}.f16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLTzv4f32 (2216) - ARM_INS_VCLT - vclt${p}.f32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLTzv4i16 (2217) - ARM_INS_VCLT - vclt${p}.s16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLTzv4i32 (2218) - ARM_INS_VCLT - vclt${p}.s32 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLTzv8f16 (2219) - ARM_INS_VCLT - vclt${p}.f16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLTzv8i16 (2220) - ARM_INS_VCLT - vclt${p}.s16 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLTzv8i8 (2221) - ARM_INS_VCLT - vclt${p}.s8 $Vd, $Vm, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLZv16i8 (2222) - ARM_INS_VCLZ - vclz${p}.i8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLZv2i32 (2223) - ARM_INS_VCLZ - vclz${p}.i32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLZv4i16 (2224) - ARM_INS_VCLZ - vclz${p}.i16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLZv4i32 (2225) - ARM_INS_VCLZ - vclz${p}.i32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLZv8i16 (2226) - ARM_INS_VCLZ - vclz${p}.i16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCLZv8i8 (2227) - ARM_INS_VCLZ - vclz${p}.i8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCMLAv2f32 (2228) - ARM_INS_VCMLA - vcmla.f32 $Vd, $Vn, $Vm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { 0 } } + }, + { /* ARM_VCMLAv2f32_indexed (2229) - ARM_INS_VCMLA - vcmla.f32 $Vd, $Vn, $Vm$lane, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { 0 } } + }, + { /* ARM_VCMLAv4f16 (2230) - ARM_INS_VCMLA - vcmla.f16 $Vd, $Vn, $Vm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { 0 } } + }, + { /* ARM_VCMLAv4f16_indexed (2231) - ARM_INS_VCMLA - vcmla.f16 $Vd, $Vn, $Vm$lane, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { 0 } } + }, + { /* ARM_VCMLAv4f32 (2232) - ARM_INS_VCMLA - vcmla.f32 $Vd, $Vn, $Vm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { 0 } } + }, + { /* ARM_VCMLAv4f32_indexed (2233) - ARM_INS_VCMLA - vcmla.f32 $Vd, $Vn, $Vm$lane, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { 0 } } + }, + { /* ARM_VCMLAv8f16 (2234) - ARM_INS_VCMLA - vcmla.f16 $Vd, $Vn, $Vm, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { 0 } } + }, + { /* ARM_VCMLAv8f16_indexed (2235) - ARM_INS_VCMLA - vcmla.f16 $Vd, $Vn, $Vm$lane, $rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { 0 } } + }, + { /* ARM_VCMPD (2236) - ARM_INS_VCMP - vcmp${p}.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCMPED (2237) - ARM_INS_VCMPE - vcmpe${p}.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCMPEH (2238) - ARM_INS_VCMPE - vcmpe${p}.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCMPES (2239) - ARM_INS_VCMPE - vcmpe${p}.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCMPEZD (2240) - ARM_INS_VCMPE - vcmpe${p}.f64 $Dd, #0 */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCMPEZH (2241) - ARM_INS_VCMPE - vcmpe${p}.f16 $Sd, #0 */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCMPEZS (2242) - ARM_INS_VCMPE - vcmpe${p}.f32 $Sd, #0 */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCMPH (2243) - ARM_INS_VCMP - vcmp${p}.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCMPS (2244) - ARM_INS_VCMP - vcmp${p}.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCMPZD (2245) - ARM_INS_VCMP - vcmp${p}.f64 $Dd, #0 */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCMPZH (2246) - ARM_INS_VCMP - vcmp${p}.f16 $Sd, #0 */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCMPZS (2247) - ARM_INS_VCMP - vcmp${p}.f32 $Sd, #0 */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCNTd (2248) - ARM_INS_VCNT - vcnt${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCNTq (2249) - ARM_INS_VCNT - vcnt${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTANSDf (2250) - ARM_INS_VCVTA - vcvta.s32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTANSDh (2251) - ARM_INS_VCVTA - vcvta.s16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTANSQf (2252) - ARM_INS_VCVTA - vcvta.s32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTANSQh (2253) - ARM_INS_VCVTA - vcvta.s16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTANUDf (2254) - ARM_INS_VCVTA - vcvta.u32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTANUDh (2255) - ARM_INS_VCVTA - vcvta.u16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTANUQf (2256) - ARM_INS_VCVTA - vcvta.u32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTANUQh (2257) - ARM_INS_VCVTA - vcvta.u16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTASD (2258) - ARM_INS_VCVTA - vcvta.s32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VCVTASH (2259) - ARM_INS_VCVTA - vcvta.s32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTASS (2260) - ARM_INS_VCVTA - vcvta.s32.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTAUD (2261) - ARM_INS_VCVTA - vcvta.u32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VCVTAUH (2262) - ARM_INS_VCVTA - vcvta.u32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTAUS (2263) - ARM_INS_VCVTA - vcvta.u32.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTBDH (2264) - ARM_INS_VCVTB - vcvtb${p}.f16.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTBHD (2265) - ARM_INS_VCVTB - vcvtb${p}.f64.f16 $Dd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTBHS (2266) - ARM_INS_VCVTB - vcvtb${p}.f32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTBSH (2267) - ARM_INS_VCVTB - vcvtb${p}.f16.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTDS (2268) - ARM_INS_VCVT - vcvt${p}.f64.f32 $Dd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTMNSDf (2269) - ARM_INS_VCVTM - vcvtm.s32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTMNSDh (2270) - ARM_INS_VCVTM - vcvtm.s16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTMNSQf (2271) - ARM_INS_VCVTM - vcvtm.s32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTMNSQh (2272) - ARM_INS_VCVTM - vcvtm.s16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTMNUDf (2273) - ARM_INS_VCVTM - vcvtm.u32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTMNUDh (2274) - ARM_INS_VCVTM - vcvtm.u16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTMNUQf (2275) - ARM_INS_VCVTM - vcvtm.u32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTMNUQh (2276) - ARM_INS_VCVTM - vcvtm.u16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTMSD (2277) - ARM_INS_VCVTM - vcvtm.s32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VCVTMSH (2278) - ARM_INS_VCVTM - vcvtm.s32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTMSS (2279) - ARM_INS_VCVTM - vcvtm.s32.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTMUD (2280) - ARM_INS_VCVTM - vcvtm.u32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VCVTMUH (2281) - ARM_INS_VCVTM - vcvtm.u32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTMUS (2282) - ARM_INS_VCVTM - vcvtm.u32.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTNNSDf (2283) - ARM_INS_VCVTN - vcvtn.s32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTNNSDh (2284) - ARM_INS_VCVTN - vcvtn.s16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTNNSQf (2285) - ARM_INS_VCVTN - vcvtn.s32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTNNSQh (2286) - ARM_INS_VCVTN - vcvtn.s16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTNNUDf (2287) - ARM_INS_VCVTN - vcvtn.u32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTNNUDh (2288) - ARM_INS_VCVTN - vcvtn.u16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTNNUQf (2289) - ARM_INS_VCVTN - vcvtn.u32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTNNUQh (2290) - ARM_INS_VCVTN - vcvtn.u16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTNSD (2291) - ARM_INS_VCVTN - vcvtn.s32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VCVTNSH (2292) - ARM_INS_VCVTN - vcvtn.s32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTNSS (2293) - ARM_INS_VCVTN - vcvtn.s32.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTNUD (2294) - ARM_INS_VCVTN - vcvtn.u32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VCVTNUH (2295) - ARM_INS_VCVTN - vcvtn.u32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTNUS (2296) - ARM_INS_VCVTN - vcvtn.u32.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTPNSDf (2297) - ARM_INS_VCVTP - vcvtp.s32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTPNSDh (2298) - ARM_INS_VCVTP - vcvtp.s16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTPNSQf (2299) - ARM_INS_VCVTP - vcvtp.s32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTPNSQh (2300) - ARM_INS_VCVTP - vcvtp.s16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTPNUDf (2301) - ARM_INS_VCVTP - vcvtp.u32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTPNUDh (2302) - ARM_INS_VCVTP - vcvtp.u16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTPNUQf (2303) - ARM_INS_VCVTP - vcvtp.u32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTPNUQh (2304) - ARM_INS_VCVTP - vcvtp.u16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VCVTPSD (2305) - ARM_INS_VCVTP - vcvtp.s32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VCVTPSH (2306) - ARM_INS_VCVTP - vcvtp.s32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTPSS (2307) - ARM_INS_VCVTP - vcvtp.s32.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTPUD (2308) - ARM_INS_VCVTP - vcvtp.u32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VCVTPUH (2309) - ARM_INS_VCVTP - vcvtp.u32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTPUS (2310) - ARM_INS_VCVTP - vcvtp.u32.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VCVTSD (2311) - ARM_INS_VCVT - vcvt${p}.f32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTTDH (2312) - ARM_INS_VCVTT - vcvtt${p}.f16.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTTHD (2313) - ARM_INS_VCVTT - vcvtt${p}.f64.f16 $Dd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTTHS (2314) - ARM_INS_VCVTT - vcvtt${p}.f32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTTSH (2315) - ARM_INS_VCVTT - vcvtt${p}.f16.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTf2h (2316) - ARM_INS_VCVT - vcvt${p}.f16.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTf2sd (2317) - ARM_INS_VCVT - vcvt${p}.s32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTf2sq (2318) - ARM_INS_VCVT - vcvt${p}.s32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTf2ud (2319) - ARM_INS_VCVT - vcvt${p}.u32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTf2uq (2320) - ARM_INS_VCVT - vcvt${p}.u32.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTf2xsd (2321) - ARM_INS_VCVT - vcvt${p}.s32.f32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTf2xsq (2322) - ARM_INS_VCVT - vcvt${p}.s32.f32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTf2xud (2323) - ARM_INS_VCVT - vcvt${p}.u32.f32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTf2xuq (2324) - ARM_INS_VCVT - vcvt${p}.u32.f32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTh2f (2325) - ARM_INS_VCVT - vcvt${p}.f32.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTh2sd (2326) - ARM_INS_VCVT - vcvt${p}.s16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTh2sq (2327) - ARM_INS_VCVT - vcvt${p}.s16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTh2ud (2328) - ARM_INS_VCVT - vcvt${p}.u16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTh2uq (2329) - ARM_INS_VCVT - vcvt${p}.u16.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTh2xsd (2330) - ARM_INS_VCVT - vcvt${p}.s16.f16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTh2xsq (2331) - ARM_INS_VCVT - vcvt${p}.s16.f16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTh2xud (2332) - ARM_INS_VCVT - vcvt${p}.u16.f16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTh2xuq (2333) - ARM_INS_VCVT - vcvt${p}.u16.f16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTs2fd (2334) - ARM_INS_VCVT - vcvt${p}.f32.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTs2fq (2335) - ARM_INS_VCVT - vcvt${p}.f32.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTs2hd (2336) - ARM_INS_VCVT - vcvt${p}.f16.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTs2hq (2337) - ARM_INS_VCVT - vcvt${p}.f16.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTu2fd (2338) - ARM_INS_VCVT - vcvt${p}.f32.u32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTu2fq (2339) - ARM_INS_VCVT - vcvt${p}.f32.u32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTu2hd (2340) - ARM_INS_VCVT - vcvt${p}.f16.u16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTu2hq (2341) - ARM_INS_VCVT - vcvt${p}.f16.u16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTxs2fd (2342) - ARM_INS_VCVT - vcvt${p}.f32.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTxs2fq (2343) - ARM_INS_VCVT - vcvt${p}.f32.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTxs2hd (2344) - ARM_INS_VCVT - vcvt${p}.f16.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTxs2hq (2345) - ARM_INS_VCVT - vcvt${p}.f16.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTxu2fd (2346) - ARM_INS_VCVT - vcvt${p}.f32.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTxu2fq (2347) - ARM_INS_VCVT - vcvt${p}.f32.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTxu2hd (2348) - ARM_INS_VCVT - vcvt${p}.f16.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VCVTxu2hq (2349) - ARM_INS_VCVT - vcvt${p}.f16.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDIVD (2350) - ARM_INS_VDIV - vdiv${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDIVH (2351) - ARM_INS_VDIV - vdiv${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDIVS (2352) - ARM_INS_VDIV - vdiv${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDUP16d (2353) - ARM_INS_VDUP - vdup${p}.16 $V, $R */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDUP16q (2354) - ARM_INS_VDUP - vdup${p}.16 $V, $R */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDUP32d (2355) - ARM_INS_VDUP - vdup${p}.32 $V, $R */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDUP32q (2356) - ARM_INS_VDUP - vdup${p}.32 $V, $R */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDUP8d (2357) - ARM_INS_VDUP - vdup${p}.8 $V, $R */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDUP8q (2358) - ARM_INS_VDUP - vdup${p}.8 $V, $R */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDUPLN16d (2359) - ARM_INS_VDUP - vdup${p}.16 $Vd, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDUPLN16q (2360) - ARM_INS_VDUP - vdup${p}.16 $Vd, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDUPLN32d (2361) - ARM_INS_VDUP - vdup${p}.32 $Vd, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDUPLN32q (2362) - ARM_INS_VDUP - vdup${p}.32 $Vd, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDUPLN8d (2363) - ARM_INS_VDUP - vdup${p}.8 $Vd, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VDUPLN8q (2364) - ARM_INS_VDUP - vdup${p}.8 $Vd, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VEORd (2365) - ARM_INS_VEOR - veor${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VEORq (2366) - ARM_INS_VEOR - veor${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VEXTd16 (2367) - ARM_INS_VEXT - vext${p}.16 $Vd, $Vn, $Vm, $index */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VEXTd32 (2368) - ARM_INS_VEXT - vext${p}.32 $Vd, $Vn, $Vm, $index */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VEXTd8 (2369) - ARM_INS_VEXT - vext${p}.8 $Vd, $Vn, $Vm, $index */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VEXTq16 (2370) - ARM_INS_VEXT - vext${p}.16 $Vd, $Vn, $Vm, $index */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VEXTq32 (2371) - ARM_INS_VEXT - vext${p}.32 $Vd, $Vn, $Vm, $index */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VEXTq64 (2372) - ARM_INS_VEXT - vext${p}.64 $Vd, $Vn, $Vm, $index */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VEXTq8 (2373) - ARM_INS_VEXT - vext${p}.8 $Vd, $Vn, $Vm, $index */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMAD (2374) - ARM_INS_VFMA - vfma${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Ddin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMAH (2375) - ARM_INS_VFMA - vfma${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMALD (2376) - ARM_INS_VFMAL - vfmal.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VFMALDI (2377) - ARM_INS_VFMAL - vfmal.f16 $Vd, $Vn, $Vm$idx */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */ + { 0 } } + }, + { /* ARM_VFMALQ (2378) - ARM_INS_VFMAL - vfmal.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VFMALQI (2379) - ARM_INS_VFMAL - vfmal.f16 $Vd, $Vn, $Vm$idx */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */ + { 0 } } + }, + { /* ARM_VFMAS (2380) - ARM_INS_VFMA - vfma${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMAfd (2381) - ARM_INS_VFMA - vfma${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMAfq (2382) - ARM_INS_VFMA - vfma${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMAhd (2383) - ARM_INS_VFMA - vfma${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMAhq (2384) - ARM_INS_VFMA - vfma${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMSD (2385) - ARM_INS_VFMS - vfms${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Ddin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMSH (2386) - ARM_INS_VFMS - vfms${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMSLD (2387) - ARM_INS_VFMSL - vfmsl.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VFMSLDI (2388) - ARM_INS_VFMSL - vfmsl.f16 $Vd, $Vn, $Vm$idx */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */ + { 0 } } + }, + { /* ARM_VFMSLQ (2389) - ARM_INS_VFMSL - vfmsl.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VFMSLQI (2390) - ARM_INS_VFMSL - vfmsl.f16 $Vd, $Vn, $Vm$idx */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */ + { 0 } } + }, + { /* ARM_VFMSS (2391) - ARM_INS_VFMS - vfms${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMSfd (2392) - ARM_INS_VFMS - vfms${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMSfq (2393) - ARM_INS_VFMS - vfms${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMShd (2394) - ARM_INS_VFMS - vfms${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFMShq (2395) - ARM_INS_VFMS - vfms${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFNMAD (2396) - ARM_INS_VFNMA - vfnma${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Ddin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFNMAH (2397) - ARM_INS_VFNMA - vfnma${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFNMAS (2398) - ARM_INS_VFNMA - vfnma${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFNMSD (2399) - ARM_INS_VFNMS - vfnms${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Ddin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFNMSH (2400) - ARM_INS_VFNMS - vfnms${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFNMSS (2401) - ARM_INS_VFNMS - vfnms${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VFP_VMAXNMD (2402) - ARM_INS_VMAXNM - vmaxnm.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VFP_VMAXNMH (2403) - ARM_INS_VMAXNM - vmaxnm.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VFP_VMAXNMS (2404) - ARM_INS_VMAXNM - vmaxnm.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VFP_VMINNMD (2405) - ARM_INS_VMINNM - vminnm.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VFP_VMINNMH (2406) - ARM_INS_VMINNM - vminnm.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VFP_VMINNMS (2407) - ARM_INS_VMINNM - vminnm.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VGETLNi32 (2408) - ARM_INS_VMOV - vmov${p}.32 $R, $V$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VGETLNs16 (2409) - ARM_INS_VMOV - vmov${p}.s16 $R, $V$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VGETLNs8 (2410) - ARM_INS_VMOV - vmov${p}.s8 $R, $V$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VGETLNu16 (2411) - ARM_INS_VMOV - vmov${p}.u16 $R, $V$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VGETLNu8 (2412) - ARM_INS_VMOV - vmov${p}.u8 $R, $V$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHADDsv16i8 (2413) - ARM_INS_VHADD - vhadd${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHADDsv2i32 (2414) - ARM_INS_VHADD - vhadd${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHADDsv4i16 (2415) - ARM_INS_VHADD - vhadd${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHADDsv4i32 (2416) - ARM_INS_VHADD - vhadd${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHADDsv8i16 (2417) - ARM_INS_VHADD - vhadd${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHADDsv8i8 (2418) - ARM_INS_VHADD - vhadd${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHADDuv16i8 (2419) - ARM_INS_VHADD - vhadd${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHADDuv2i32 (2420) - ARM_INS_VHADD - vhadd${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHADDuv4i16 (2421) - ARM_INS_VHADD - vhadd${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHADDuv4i32 (2422) - ARM_INS_VHADD - vhadd${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHADDuv8i16 (2423) - ARM_INS_VHADD - vhadd${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHADDuv8i8 (2424) - ARM_INS_VHADD - vhadd${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHSUBsv16i8 (2425) - ARM_INS_VHSUB - vhsub${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHSUBsv2i32 (2426) - ARM_INS_VHSUB - vhsub${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHSUBsv4i16 (2427) - ARM_INS_VHSUB - vhsub${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHSUBsv4i32 (2428) - ARM_INS_VHSUB - vhsub${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHSUBsv8i16 (2429) - ARM_INS_VHSUB - vhsub${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHSUBsv8i8 (2430) - ARM_INS_VHSUB - vhsub${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHSUBuv16i8 (2431) - ARM_INS_VHSUB - vhsub${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHSUBuv2i32 (2432) - ARM_INS_VHSUB - vhsub${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHSUBuv4i16 (2433) - ARM_INS_VHSUB - vhsub${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHSUBuv4i32 (2434) - ARM_INS_VHSUB - vhsub${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHSUBuv8i16 (2435) - ARM_INS_VHSUB - vhsub${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VHSUBuv8i8 (2436) - ARM_INS_VHSUB - vhsub${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VINSH (2437) - ARM_INS_VINS - vins.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sda */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VJCVT (2438) - ARM_INS_VJCVT - vjcvt${p}.s32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPd16 (2439) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPd16wb_fixed (2440) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPd16wb_register (2441) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPd32 (2442) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPd32wb_fixed (2443) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPd32wb_register (2444) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPd8 (2445) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPd8wb_fixed (2446) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPd8wb_register (2447) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPq16 (2448) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPq16wb_fixed (2449) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPq16wb_register (2450) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPq32 (2451) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPq32wb_fixed (2452) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPq32wb_register (2453) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPq8 (2454) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPq8wb_fixed (2455) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1DUPq8wb_register (2456) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNd16 (2457) - ARM_INS_VLD1 - vld1${p}.16 \{$Vd[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNd16_UPD (2458) - ARM_INS_VLD1 - vld1${p}.16 \{$Vd[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNd32 (2459) - ARM_INS_VLD1 - vld1${p}.32 \{$Vd[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNd32_UPD (2460) - ARM_INS_VLD1 - vld1${p}.32 \{$Vd[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNd8 (2461) - ARM_INS_VLD1 - vld1${p}.8 \{$Vd[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1LNd8_UPD (2462) - ARM_INS_VLD1 - vld1${p}.8 \{$Vd[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1LNq16Pseudo (2463) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1LNq16Pseudo_UPD (2464) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1LNq32Pseudo (2465) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1LNq32Pseudo_UPD (2466) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1LNq8Pseudo (2467) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1LNq8Pseudo_UPD (2468) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1d16 (2469) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d16Q (2470) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1d16QPseudo (2471) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d16QPseudoWB_fixed (2472) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d16QPseudoWB_register (2473) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1d16Qwb_fixed (2474) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d16Qwb_register (2475) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d16T (2476) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1d16TPseudo (2477) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d16TPseudoWB_fixed (2478) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d16TPseudoWB_register (2479) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1d16Twb_fixed (2480) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d16Twb_register (2481) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d16wb_fixed (2482) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d16wb_register (2483) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d32 (2484) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d32Q (2485) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1d32QPseudo (2486) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d32QPseudoWB_fixed (2487) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d32QPseudoWB_register (2488) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1d32Qwb_fixed (2489) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d32Qwb_register (2490) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d32T (2491) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1d32TPseudo (2492) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d32TPseudoWB_fixed (2493) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d32TPseudoWB_register (2494) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1d32Twb_fixed (2495) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d32Twb_register (2496) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d32wb_fixed (2497) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d32wb_register (2498) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d64 (2499) - ARM_INS_VLD1 - vld1${p}.64 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d64Q (2500) - ARM_INS_VLD1 - vld1${p}.64 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1d64QPseudo (2501) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d64QPseudoWB_fixed (2502) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d64QPseudoWB_register (2503) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1d64Qwb_fixed (2504) - ARM_INS_VLD1 - vld1${p}.64 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d64Qwb_register (2505) - ARM_INS_VLD1 - vld1${p}.64 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d64T (2506) - ARM_INS_VLD1 - vld1${p}.64 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1d64TPseudo (2507) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d64TPseudoWB_fixed (2508) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d64TPseudoWB_register (2509) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1d64Twb_fixed (2510) - ARM_INS_VLD1 - vld1${p}.64 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d64Twb_register (2511) - ARM_INS_VLD1 - vld1${p}.64 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d64wb_fixed (2512) - ARM_INS_VLD1 - vld1${p}.64 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d64wb_register (2513) - ARM_INS_VLD1 - vld1${p}.64 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d8 (2514) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d8Q (2515) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1d8QPseudo (2516) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d8QPseudoWB_fixed (2517) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d8QPseudoWB_register (2518) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1d8Qwb_fixed (2519) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d8Qwb_register (2520) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d8T (2521) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1d8TPseudo (2522) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d8TPseudoWB_fixed (2523) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1d8TPseudoWB_register (2524) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1d8Twb_fixed (2525) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d8Twb_register (2526) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d8wb_fixed (2527) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1d8wb_register (2528) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1q16 (2529) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1q16HighQPseudo (2530) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q16HighQPseudo_UPD (2531) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q16HighTPseudo (2532) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q16HighTPseudo_UPD (2533) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q16LowQPseudo_UPD (2534) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q16LowTPseudo_UPD (2535) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1q16wb_fixed (2536) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1q16wb_register (2537) - ARM_INS_VLD1 - vld1${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1q32 (2538) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1q32HighQPseudo (2539) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q32HighQPseudo_UPD (2540) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q32HighTPseudo (2541) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q32HighTPseudo_UPD (2542) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q32LowQPseudo_UPD (2543) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q32LowTPseudo_UPD (2544) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1q32wb_fixed (2545) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1q32wb_register (2546) - ARM_INS_VLD1 - vld1${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1q64 (2547) - ARM_INS_VLD1 - vld1${p}.64 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1q64HighQPseudo (2548) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q64HighQPseudo_UPD (2549) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q64HighTPseudo (2550) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q64HighTPseudo_UPD (2551) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q64LowQPseudo_UPD (2552) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q64LowTPseudo_UPD (2553) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1q64wb_fixed (2554) - ARM_INS_VLD1 - vld1${p}.64 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1q64wb_register (2555) - ARM_INS_VLD1 - vld1${p}.64 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1q8 (2556) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD1q8HighQPseudo (2557) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q8HighQPseudo_UPD (2558) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q8HighTPseudo (2559) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q8HighTPseudo_UPD (2560) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q8LowQPseudo_UPD (2561) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD1q8LowTPseudo_UPD (2562) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD1q8wb_fixed (2563) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD1q8wb_register (2564) - ARM_INS_VLD1 - vld1${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd16 (2565) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd16wb_fixed (2566) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd16wb_register (2567) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd16x2 (2568) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd16x2wb_fixed (2569) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd16x2wb_register (2570) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd32 (2571) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd32wb_fixed (2572) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd32wb_register (2573) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd32x2 (2574) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd32x2wb_fixed (2575) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd32x2wb_register (2576) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd8 (2577) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd8wb_fixed (2578) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd8wb_register (2579) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd8x2 (2580) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd8x2wb_fixed (2581) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2DUPd8x2wb_register (2582) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD2DUPq16EvenPseudo (2583) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2DUPq16OddPseudo (2584) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2DUPq16OddPseudoWB_fixed (2585) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2DUPq16OddPseudoWB_register (2586) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2DUPq32EvenPseudo (2587) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2DUPq32OddPseudo (2588) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2DUPq32OddPseudoWB_fixed (2589) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2DUPq32OddPseudoWB_register (2590) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2DUPq8EvenPseudo (2591) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2DUPq8OddPseudo (2592) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2DUPq8OddPseudoWB_fixed (2593) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2DUPq8OddPseudoWB_register (2594) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD2LNd16 (2595) - ARM_INS_VLD2 - vld2${p}.16 \{$Vd[$lane], $dst2[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD2LNd16Pseudo (2596) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2LNd16Pseudo_UPD (2597) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD2LNd16_UPD (2598) - ARM_INS_VLD2 - vld2${p}.16 \{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNd32 (2599) - ARM_INS_VLD2 - vld2${p}.32 \{$Vd[$lane], $dst2[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD2LNd32Pseudo (2600) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2LNd32Pseudo_UPD (2601) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD2LNd32_UPD (2602) - ARM_INS_VLD2 - vld2${p}.32 \{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNd8 (2603) - ARM_INS_VLD2 - vld2${p}.8 \{$Vd[$lane], $dst2[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD2LNd8Pseudo (2604) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2LNd8Pseudo_UPD (2605) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD2LNd8_UPD (2606) - ARM_INS_VLD2 - vld2${p}.8 \{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNq16 (2607) - ARM_INS_VLD2 - vld2${p}.16 \{$Vd[$lane], $dst2[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD2LNq16Pseudo (2608) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2LNq16Pseudo_UPD (2609) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD2LNq16_UPD (2610) - ARM_INS_VLD2 - vld2${p}.16 \{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2LNq32 (2611) - ARM_INS_VLD2 - vld2${p}.32 \{$Vd[$lane], $dst2[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD2LNq32Pseudo (2612) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2LNq32Pseudo_UPD (2613) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD2LNq32_UPD (2614) - ARM_INS_VLD2 - vld2${p}.32 \{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2b16 (2615) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2b16wb_fixed (2616) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2b16wb_register (2617) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2b32 (2618) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2b32wb_fixed (2619) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2b32wb_register (2620) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2b8 (2621) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2b8wb_fixed (2622) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2b8wb_register (2623) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2d16 (2624) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2d16wb_fixed (2625) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2d16wb_register (2626) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2d32 (2627) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2d32wb_fixed (2628) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2d32wb_register (2629) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2d8 (2630) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2d8wb_fixed (2631) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2d8wb_register (2632) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2q16 (2633) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD2q16Pseudo (2634) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2q16PseudoWB_fixed (2635) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2q16PseudoWB_register (2636) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD2q16wb_fixed (2637) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2q16wb_register (2638) - ARM_INS_VLD2 - vld2${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2q32 (2639) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD2q32Pseudo (2640) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2q32PseudoWB_fixed (2641) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2q32PseudoWB_register (2642) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD2q32wb_fixed (2643) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2q32wb_register (2644) - ARM_INS_VLD2 - vld2${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2q8 (2645) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD2q8Pseudo (2646) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2q8PseudoWB_fixed (2647) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD2q8PseudoWB_register (2648) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD2q8wb_fixed (2649) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD2q8wb_register (2650) - ARM_INS_VLD2 - vld2${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPd16 (2651) - ARM_INS_VLD3 - vld3${p}.16 \{$Vd[], $dst2[], $dst3[]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3DUPd16Pseudo (2652) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3DUPd16Pseudo_UPD (2653) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3DUPd16_UPD (2654) - ARM_INS_VLD3 - vld3${p}.16 \{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPd32 (2655) - ARM_INS_VLD3 - vld3${p}.32 \{$Vd[], $dst2[], $dst3[]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3DUPd32Pseudo (2656) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3DUPd32Pseudo_UPD (2657) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3DUPd32_UPD (2658) - ARM_INS_VLD3 - vld3${p}.32 \{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPd8 (2659) - ARM_INS_VLD3 - vld3${p}.8 \{$Vd[], $dst2[], $dst3[]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3DUPd8Pseudo (2660) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3DUPd8Pseudo_UPD (2661) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3DUPd8_UPD (2662) - ARM_INS_VLD3 - vld3${p}.8 \{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPq16 (2663) - ARM_INS_VLD3 - vld3${p}.16 \{$Vd[], $dst2[], $dst3[]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3DUPq16EvenPseudo (2664) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3DUPq16OddPseudo (2665) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3DUPq16OddPseudo_UPD (2666) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3DUPq16_UPD (2667) - ARM_INS_VLD3 - vld3${p}.16 \{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPq32 (2668) - ARM_INS_VLD3 - vld3${p}.32 \{$Vd[], $dst2[], $dst3[]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3DUPq32EvenPseudo (2669) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3DUPq32OddPseudo (2670) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3DUPq32OddPseudo_UPD (2671) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3DUPq32_UPD (2672) - ARM_INS_VLD3 - vld3${p}.32 \{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3DUPq8 (2673) - ARM_INS_VLD3 - vld3${p}.8 \{$Vd[], $dst2[], $dst3[]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3DUPq8EvenPseudo (2674) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3DUPq8OddPseudo (2675) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3DUPq8OddPseudo_UPD (2676) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3DUPq8_UPD (2677) - ARM_INS_VLD3 - vld3${p}.8 \{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNd16 (2678) - ARM_INS_VLD3 - vld3${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3LNd16Pseudo (2679) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3LNd16Pseudo_UPD (2680) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3LNd16_UPD (2681) - ARM_INS_VLD3 - vld3${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNd32 (2682) - ARM_INS_VLD3 - vld3${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3LNd32Pseudo (2683) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3LNd32Pseudo_UPD (2684) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3LNd32_UPD (2685) - ARM_INS_VLD3 - vld3${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNd8 (2686) - ARM_INS_VLD3 - vld3${p}.8 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3LNd8Pseudo (2687) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3LNd8Pseudo_UPD (2688) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3LNd8_UPD (2689) - ARM_INS_VLD3 - vld3${p}.8 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNq16 (2690) - ARM_INS_VLD3 - vld3${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3LNq16Pseudo (2691) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3LNq16Pseudo_UPD (2692) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3LNq16_UPD (2693) - ARM_INS_VLD3 - vld3${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3LNq32 (2694) - ARM_INS_VLD3 - vld3${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3LNq32Pseudo (2695) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3LNq32Pseudo_UPD (2696) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3LNq32_UPD (2697) - ARM_INS_VLD3 - vld3${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3d16 (2698) - ARM_INS_VLD3 - vld3${p}.16 \{$Vd, $dst2, $dst3\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3d16Pseudo (2699) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3d16Pseudo_UPD (2700) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3d16_UPD (2701) - ARM_INS_VLD3 - vld3${p}.16 \{$Vd, $dst2, $dst3\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3d32 (2702) - ARM_INS_VLD3 - vld3${p}.32 \{$Vd, $dst2, $dst3\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3d32Pseudo (2703) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3d32Pseudo_UPD (2704) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3d32_UPD (2705) - ARM_INS_VLD3 - vld3${p}.32 \{$Vd, $dst2, $dst3\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3d8 (2706) - ARM_INS_VLD3 - vld3${p}.8 \{$Vd, $dst2, $dst3\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3d8Pseudo (2707) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3d8Pseudo_UPD (2708) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3d8_UPD (2709) - ARM_INS_VLD3 - vld3${p}.8 \{$Vd, $dst2, $dst3\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD3q16 (2710) - ARM_INS_VLD3 - vld3${p}.16 \{$Vd, $dst2, $dst3\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3q16Pseudo_UPD (2711) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3q16_UPD (2712) - ARM_INS_VLD3 - vld3${p}.16 \{$Vd, $dst2, $dst3\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3q16oddPseudo (2713) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3q16oddPseudo_UPD (2714) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3q32 (2715) - ARM_INS_VLD3 - vld3${p}.32 \{$Vd, $dst2, $dst3\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3q32Pseudo_UPD (2716) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3q32_UPD (2717) - ARM_INS_VLD3 - vld3${p}.32 \{$Vd, $dst2, $dst3\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3q32oddPseudo (2718) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3q32oddPseudo_UPD (2719) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3q8 (2720) - ARM_INS_VLD3 - vld3${p}.8 \{$Vd, $dst2, $dst3\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3q8Pseudo_UPD (2721) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD3q8_UPD (2722) - ARM_INS_VLD3 - vld3${p}.8 \{$Vd, $dst2, $dst3\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD3q8oddPseudo (2723) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD3q8oddPseudo_UPD (2724) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4DUPd16 (2725) - ARM_INS_VLD4 - vld4${p}.16 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4DUPd16Pseudo (2726) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4DUPd16Pseudo_UPD (2727) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4DUPd16_UPD (2728) - ARM_INS_VLD4 - vld4${p}.16 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPd32 (2729) - ARM_INS_VLD4 - vld4${p}.32 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4DUPd32Pseudo (2730) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4DUPd32Pseudo_UPD (2731) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4DUPd32_UPD (2732) - ARM_INS_VLD4 - vld4${p}.32 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPd8 (2733) - ARM_INS_VLD4 - vld4${p}.8 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4DUPd8Pseudo (2734) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4DUPd8Pseudo_UPD (2735) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4DUPd8_UPD (2736) - ARM_INS_VLD4 - vld4${p}.8 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPq16 (2737) - ARM_INS_VLD4 - vld4${p}.16 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4DUPq16EvenPseudo (2738) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4DUPq16OddPseudo (2739) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4DUPq16OddPseudo_UPD (2740) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4DUPq16_UPD (2741) - ARM_INS_VLD4 - vld4${p}.16 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPq32 (2742) - ARM_INS_VLD4 - vld4${p}.32 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4DUPq32EvenPseudo (2743) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4DUPq32OddPseudo (2744) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4DUPq32OddPseudo_UPD (2745) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4DUPq32_UPD (2746) - ARM_INS_VLD4 - vld4${p}.32 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4DUPq8 (2747) - ARM_INS_VLD4 - vld4${p}.8 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4DUPq8EvenPseudo (2748) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4DUPq8OddPseudo (2749) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4DUPq8OddPseudo_UPD (2750) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4DUPq8_UPD (2751) - ARM_INS_VLD4 - vld4${p}.8 \{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNd16 (2752) - ARM_INS_VLD4 - vld4${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4LNd16Pseudo (2753) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4LNd16Pseudo_UPD (2754) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4LNd16_UPD (2755) - ARM_INS_VLD4 - vld4${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNd32 (2756) - ARM_INS_VLD4 - vld4${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4LNd32Pseudo (2757) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4LNd32Pseudo_UPD (2758) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4LNd32_UPD (2759) - ARM_INS_VLD4 - vld4${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNd8 (2760) - ARM_INS_VLD4 - vld4${p}.8 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4LNd8Pseudo (2761) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4LNd8Pseudo_UPD (2762) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4LNd8_UPD (2763) - ARM_INS_VLD4 - vld4${p}.8 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNq16 (2764) - ARM_INS_VLD4 - vld4${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4LNq16Pseudo (2765) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4LNq16Pseudo_UPD (2766) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4LNq16_UPD (2767) - ARM_INS_VLD4 - vld4${p}.16 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4LNq32 (2768) - ARM_INS_VLD4 - vld4${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4LNq32Pseudo (2769) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4LNq32Pseudo_UPD (2770) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4LNq32_UPD (2771) - ARM_INS_VLD4 - vld4${p}.32 \{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4d16 (2772) - ARM_INS_VLD4 - vld4${p}.16 \{$Vd, $dst2, $dst3, $dst4\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4d16Pseudo (2773) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4d16Pseudo_UPD (2774) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4d16_UPD (2775) - ARM_INS_VLD4 - vld4${p}.16 \{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4d32 (2776) - ARM_INS_VLD4 - vld4${p}.32 \{$Vd, $dst2, $dst3, $dst4\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4d32Pseudo (2777) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4d32Pseudo_UPD (2778) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4d32_UPD (2779) - ARM_INS_VLD4 - vld4${p}.32 \{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4d8 (2780) - ARM_INS_VLD4 - vld4${p}.8 \{$Vd, $dst2, $dst3, $dst4\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4d8Pseudo (2781) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4d8Pseudo_UPD (2782) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4d8_UPD (2783) - ARM_INS_VLD4 - vld4${p}.8 \{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLD4q16 (2784) - ARM_INS_VLD4 - vld4${p}.16 \{$Vd, $dst2, $dst3, $dst4\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4q16Pseudo_UPD (2785) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4q16_UPD (2786) - ARM_INS_VLD4 - vld4${p}.16 \{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4q16oddPseudo (2787) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4q16oddPseudo_UPD (2788) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4q32 (2789) - ARM_INS_VLD4 - vld4${p}.32 \{$Vd, $dst2, $dst3, $dst4\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4q32Pseudo_UPD (2790) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4q32_UPD (2791) - ARM_INS_VLD4 - vld4${p}.32 \{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4q32oddPseudo (2792) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4q32oddPseudo_UPD (2793) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4q8 (2794) - ARM_INS_VLD4 - vld4${p}.8 \{$Vd, $dst2, $dst3, $dst4\}, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4q8Pseudo_UPD (2795) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLD4q8_UPD (2796) - ARM_INS_VLD4 - vld4${p}.8 \{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst3 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst4 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VLD4q8oddPseudo (2797) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VLD4q8oddPseudo_UPD (2798) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLDMDDB_UPD (2799) - ARM_INS_VLDMDB - vldmdb${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_VLDMDIA (2800) - ARM_INS_VLDMIA - vldmia${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_VLDMDIA_UPD (2801) - ARM_INS_VLDMIA - vldmia${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { { { /* ARM_VLDMQIA (2802) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VLDMSDB_UPD (2803) - ARM_INS_VLDMDB - vldmdb${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_VLDMSIA (2804) - ARM_INS_VLDMIA - vldmia${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_VLDMSIA_UPD (2805) - ARM_INS_VLDMIA - vldmia${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_VLDRD (2806) - ARM_INS_VLDR - vldr${p} $Dd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDRH (2807) - ARM_INS_VLDR - vldr${p}.16 $Sd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDRS (2808) - ARM_INS_VLDR - vldr${p} $Sd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_FPCXTNS_off (2809) - ARM_INS_VLDR - vldr${p} fpcxtns, $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_FPCXTNS_post (2810) - ARM_INS_VLDR - vldr${p} fpcxtns, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_FPCXTNS_pre (2811) - ARM_INS_VLDR - vldr${p} fpcxtns, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_FPCXTS_off (2812) - ARM_INS_VLDR - vldr${p} fpcxts, $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_FPCXTS_post (2813) - ARM_INS_VLDR - vldr${p} fpcxts, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_FPCXTS_pre (2814) - ARM_INS_VLDR - vldr${p} fpcxts, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_FPSCR_NZCVQC_off (2815) - ARM_INS_VLDR - vldr${p} fpscr_nzcvqc, $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_FPSCR_NZCVQC_post (2816) - ARM_INS_VLDR - vldr${p} fpscr_nzcvqc, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_FPSCR_NZCVQC_pre (2817) - ARM_INS_VLDR - vldr${p} fpscr_nzcvqc, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_FPSCR_off (2818) - ARM_INS_VLDR - vldr${p} fpscr, $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_FPSCR_post (2819) - ARM_INS_VLDR - vldr${p} fpscr, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_FPSCR_pre (2820) - ARM_INS_VLDR - vldr${p} fpscr, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_P0_off (2821) - ARM_INS_VLDR - vldr${p} p0, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_P0_post (2822) - ARM_INS_VLDR - vldr${p} p0, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_P0_pre (2823) - ARM_INS_VLDR - vldr${p} p0, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_VPR_off (2824) - ARM_INS_VLDR - vldr${p} vpr, $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_VPR_post (2825) - ARM_INS_VLDR - vldr${p} vpr, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLDR_VPR_pre (2826) - ARM_INS_VLDR - vldr${p} vpr, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLLDM (2827) - ARM_INS_VLLDM - vlldm${p} $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VLSTM (2828) - ARM_INS_VLSTM - vlstm${p} $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXfd (2829) - ARM_INS_VMAX - vmax${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXfq (2830) - ARM_INS_VMAX - vmax${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXhd (2831) - ARM_INS_VMAX - vmax${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXhq (2832) - ARM_INS_VMAX - vmax${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXsv16i8 (2833) - ARM_INS_VMAX - vmax${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXsv2i32 (2834) - ARM_INS_VMAX - vmax${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXsv4i16 (2835) - ARM_INS_VMAX - vmax${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXsv4i32 (2836) - ARM_INS_VMAX - vmax${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXsv8i16 (2837) - ARM_INS_VMAX - vmax${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXsv8i8 (2838) - ARM_INS_VMAX - vmax${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXuv16i8 (2839) - ARM_INS_VMAX - vmax${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXuv2i32 (2840) - ARM_INS_VMAX - vmax${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXuv4i16 (2841) - ARM_INS_VMAX - vmax${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXuv4i32 (2842) - ARM_INS_VMAX - vmax${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXuv8i16 (2843) - ARM_INS_VMAX - vmax${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMAXuv8i8 (2844) - ARM_INS_VMAX - vmax${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINfd (2845) - ARM_INS_VMIN - vmin${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINfq (2846) - ARM_INS_VMIN - vmin${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINhd (2847) - ARM_INS_VMIN - vmin${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINhq (2848) - ARM_INS_VMIN - vmin${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINsv16i8 (2849) - ARM_INS_VMIN - vmin${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINsv2i32 (2850) - ARM_INS_VMIN - vmin${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINsv4i16 (2851) - ARM_INS_VMIN - vmin${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINsv4i32 (2852) - ARM_INS_VMIN - vmin${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINsv8i16 (2853) - ARM_INS_VMIN - vmin${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINsv8i8 (2854) - ARM_INS_VMIN - vmin${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINuv16i8 (2855) - ARM_INS_VMIN - vmin${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINuv2i32 (2856) - ARM_INS_VMIN - vmin${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINuv4i16 (2857) - ARM_INS_VMIN - vmin${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINuv4i32 (2858) - ARM_INS_VMIN - vmin${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINuv8i16 (2859) - ARM_INS_VMIN - vmin${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMINuv8i8 (2860) - ARM_INS_VMIN - vmin${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAD (2861) - ARM_INS_VMLA - vmla${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Ddin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAH (2862) - ARM_INS_VMLA - vmla${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLALslsv2i32 (2863) - ARM_INS_VMLAL - vmlal${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLALslsv4i16 (2864) - ARM_INS_VMLAL - vmlal${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLALsluv2i32 (2865) - ARM_INS_VMLAL - vmlal${p}.u32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLALsluv4i16 (2866) - ARM_INS_VMLAL - vmlal${p}.u16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLALsv2i64 (2867) - ARM_INS_VMLAL - vmlal${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLALsv4i32 (2868) - ARM_INS_VMLAL - vmlal${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLALsv8i16 (2869) - ARM_INS_VMLAL - vmlal${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLALuv2i64 (2870) - ARM_INS_VMLAL - vmlal${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLALuv4i32 (2871) - ARM_INS_VMLAL - vmlal${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLALuv8i16 (2872) - ARM_INS_VMLAL - vmlal${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAS (2873) - ARM_INS_VMLA - vmla${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAfd (2874) - ARM_INS_VMLA - vmla${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAfq (2875) - ARM_INS_VMLA - vmla${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAhd (2876) - ARM_INS_VMLA - vmla${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAhq (2877) - ARM_INS_VMLA - vmla${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAslfd (2878) - ARM_INS_VMLA - vmla${p}.f32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAslfq (2879) - ARM_INS_VMLA - vmla${p}.f32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAslhd (2880) - ARM_INS_VMLA - vmla${p}.f16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAslhq (2881) - ARM_INS_VMLA - vmla${p}.f16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAslv2i32 (2882) - ARM_INS_VMLA - vmla${p}.i32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAslv4i16 (2883) - ARM_INS_VMLA - vmla${p}.i16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAslv4i32 (2884) - ARM_INS_VMLA - vmla${p}.i32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAslv8i16 (2885) - ARM_INS_VMLA - vmla${p}.i16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAv16i8 (2886) - ARM_INS_VMLA - vmla${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAv2i32 (2887) - ARM_INS_VMLA - vmla${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAv4i16 (2888) - ARM_INS_VMLA - vmla${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAv4i32 (2889) - ARM_INS_VMLA - vmla${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAv8i16 (2890) - ARM_INS_VMLA - vmla${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLAv8i8 (2891) - ARM_INS_VMLA - vmla${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSD (2892) - ARM_INS_VMLS - vmls${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Ddin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSH (2893) - ARM_INS_VMLS - vmls${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSLslsv2i32 (2894) - ARM_INS_VMLSL - vmlsl${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSLslsv4i16 (2895) - ARM_INS_VMLSL - vmlsl${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSLsluv2i32 (2896) - ARM_INS_VMLSL - vmlsl${p}.u32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSLsluv4i16 (2897) - ARM_INS_VMLSL - vmlsl${p}.u16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSLsv2i64 (2898) - ARM_INS_VMLSL - vmlsl${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSLsv4i32 (2899) - ARM_INS_VMLSL - vmlsl${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSLsv8i16 (2900) - ARM_INS_VMLSL - vmlsl${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSLuv2i64 (2901) - ARM_INS_VMLSL - vmlsl${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSLuv4i32 (2902) - ARM_INS_VMLSL - vmlsl${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSLuv8i16 (2903) - ARM_INS_VMLSL - vmlsl${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSS (2904) - ARM_INS_VMLS - vmls${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSfd (2905) - ARM_INS_VMLS - vmls${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSfq (2906) - ARM_INS_VMLS - vmls${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLShd (2907) - ARM_INS_VMLS - vmls${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLShq (2908) - ARM_INS_VMLS - vmls${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSslfd (2909) - ARM_INS_VMLS - vmls${p}.f32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSslfq (2910) - ARM_INS_VMLS - vmls${p}.f32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSslhd (2911) - ARM_INS_VMLS - vmls${p}.f16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSslhq (2912) - ARM_INS_VMLS - vmls${p}.f16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSslv2i32 (2913) - ARM_INS_VMLS - vmls${p}.i32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSslv4i16 (2914) - ARM_INS_VMLS - vmls${p}.i16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSslv4i32 (2915) - ARM_INS_VMLS - vmls${p}.i32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSslv8i16 (2916) - ARM_INS_VMLS - vmls${p}.i16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSv16i8 (2917) - ARM_INS_VMLS - vmls${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSv2i32 (2918) - ARM_INS_VMLS - vmls${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSv4i16 (2919) - ARM_INS_VMLS - vmls${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSv4i32 (2920) - ARM_INS_VMLS - vmls${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSv8i16 (2921) - ARM_INS_VMLS - vmls${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMLSv8i8 (2922) - ARM_INS_VMLS - vmls${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMMLA (2923) - ARM_INS_VMMLA - vmmla.bf16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VMOVD (2924) - ARM_INS_VMOV - vmov${p}.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVDRR (2925) - ARM_INS_VMOV - vmov${p} $Dm, $Rt, $Rt2 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVH (2926) - ARM_INS_VMOVX - vmovx.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VMOVHR (2927) - ARM_INS_VMOV - vmov${p}.f16 $Sn, $Rt */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVLsv2i64 (2928) - ARM_INS_VMOVL - vmovl${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVLsv4i32 (2929) - ARM_INS_VMOVL - vmovl${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVLsv8i16 (2930) - ARM_INS_VMOVL - vmovl${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVLuv2i64 (2931) - ARM_INS_VMOVL - vmovl${p}.u32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVLuv4i32 (2932) - ARM_INS_VMOVL - vmovl${p}.u16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVLuv8i16 (2933) - ARM_INS_VMOVL - vmovl${p}.u8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVNv2i32 (2934) - ARM_INS_VMOVN - vmovn${p}.i64 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVNv4i16 (2935) - ARM_INS_VMOVN - vmovn${p}.i32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVNv8i8 (2936) - ARM_INS_VMOVN - vmovn${p}.i16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVRH (2937) - ARM_INS_VMOV - vmov${p}.f16 $Rt, $Sn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVRRD (2938) - ARM_INS_VMOV - vmov${p} $Rt, $Rt2, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVRRS (2939) - ARM_INS_VMOV - vmov${p} $Rt, $Rt2, $src1, $src2 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVRS (2940) - ARM_INS_VMOV - vmov${p} $Rt, $Sn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVS (2941) - ARM_INS_VMOV - vmov${p}.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVSR (2942) - ARM_INS_VMOV - vmov${p} $Sn, $Rt */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVSRR (2943) - ARM_INS_VMOV - vmov${p} $dst1, $dst2, $src1, $src2 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst1 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVv16i8 (2944) - ARM_INS_VMOV - vmov${p}.i8 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVv1i64 (2945) - ARM_INS_VMOV - vmov${p}.i64 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVv2f32 (2946) - ARM_INS_VMOV - vmov${p}.f32 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVv2i32 (2947) - ARM_INS_VMOV - vmov${p}.i32 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVv2i64 (2948) - ARM_INS_VMOV - vmov${p}.i64 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVv4f32 (2949) - ARM_INS_VMOV - vmov${p}.f32 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVv4i16 (2950) - ARM_INS_VMOV - vmov${p}.i16 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVv4i32 (2951) - ARM_INS_VMOV - vmov${p}.i32 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVv8i16 (2952) - ARM_INS_VMOV - vmov${p}.i16 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMOVv8i8 (2953) - ARM_INS_VMOV - vmov${p}.i8 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS (2954) - ARM_INS_VMRS - vmrs${p} $Rt, fpscr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS_FPCXTNS (2955) - ARM_INS_VMRS - vmrs${p} $Rt, fpcxtns */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS_FPCXTS (2956) - ARM_INS_VMRS - vmrs${p} $Rt, fpcxts */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS_FPEXC (2957) - ARM_INS_VMRS - vmrs${p} $Rt, fpexc */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS_FPINST (2958) - ARM_INS_VMRS - vmrs${p} $Rt, fpinst */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS_FPINST2 (2959) - ARM_INS_VMRS - vmrs${p} $Rt, fpinst2 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS_FPSCR_NZCVQC (2960) - ARM_INS_VMRS - vmrs${p} $Rt, fpscr_nzcvqc */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fpscr_in */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS_FPSID (2961) - ARM_INS_VMRS - vmrs${p} $Rt, fpsid */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS_MVFR0 (2962) - ARM_INS_VMRS - vmrs${p} $Rt, mvfr0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS_MVFR1 (2963) - ARM_INS_VMRS - vmrs${p} $Rt, mvfr1 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS_MVFR2 (2964) - ARM_INS_VMRS - vmrs${p} $Rt, mvfr2 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS_P0 (2965) - ARM_INS_VMRS - vmrs${p} $Rt, p0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* cond */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMRS_VPR (2966) - ARM_INS_VMRS - vmrs${p} $Rt, vpr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMSR (2967) - ARM_INS_VMSR - vmsr${p} fpscr, $Rt */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMSR_FPCXTNS (2968) - ARM_INS_VMSR - vmsr${p} fpcxtns, $Rt */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMSR_FPCXTS (2969) - ARM_INS_VMSR - vmsr${p} fpcxts, $Rt */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMSR_FPEXC (2970) - ARM_INS_VMSR - vmsr${p} fpexc, $Rt */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMSR_FPINST (2971) - ARM_INS_VMSR - vmsr${p} fpinst, $Rt */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMSR_FPINST2 (2972) - ARM_INS_VMSR - vmsr${p} fpinst2, $Rt */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMSR_FPSCR_NZCVQC (2973) - ARM_INS_VMSR - vmsr${p} fpscr_nzcvqc, $Rt */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fpscr_out */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMSR_FPSID (2974) - ARM_INS_VMSR - vmsr${p} fpsid, $Rt */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMSR_P0 (2975) - ARM_INS_VMSR - vmsr${p} p0, $Rt */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* cond */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMSR_VPR (2976) - ARM_INS_VMSR - vmsr${p} vpr, $Rt */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULD (2977) - ARM_INS_VMUL - vmul${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULH (2978) - ARM_INS_VMUL - vmul${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULLp64 (2979) - ARM_INS_VMULL - vmull.p64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VMULLp8 (2980) - ARM_INS_VMULL - vmull${p}.p8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULLslsv2i32 (2981) - ARM_INS_VMULL - vmull${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULLslsv4i16 (2982) - ARM_INS_VMULL - vmull${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULLsluv2i32 (2983) - ARM_INS_VMULL - vmull${p}.u32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULLsluv4i16 (2984) - ARM_INS_VMULL - vmull${p}.u16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULLsv2i64 (2985) - ARM_INS_VMULL - vmull${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULLsv4i32 (2986) - ARM_INS_VMULL - vmull${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULLsv8i16 (2987) - ARM_INS_VMULL - vmull${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULLuv2i64 (2988) - ARM_INS_VMULL - vmull${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULLuv4i32 (2989) - ARM_INS_VMULL - vmull${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULLuv8i16 (2990) - ARM_INS_VMULL - vmull${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULS (2991) - ARM_INS_VMUL - vmul${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULfd (2992) - ARM_INS_VMUL - vmul${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULfq (2993) - ARM_INS_VMUL - vmul${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULhd (2994) - ARM_INS_VMUL - vmul${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULhq (2995) - ARM_INS_VMUL - vmul${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULpd (2996) - ARM_INS_VMUL - vmul${p}.p8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULpq (2997) - ARM_INS_VMUL - vmul${p}.p8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULslfd (2998) - ARM_INS_VMUL - vmul${p}.f32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULslfq (2999) - ARM_INS_VMUL - vmul${p}.f32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULslhd (3000) - ARM_INS_VMUL - vmul${p}.f16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULslhq (3001) - ARM_INS_VMUL - vmul${p}.f16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULslv2i32 (3002) - ARM_INS_VMUL - vmul${p}.i32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULslv4i16 (3003) - ARM_INS_VMUL - vmul${p}.i16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULslv4i32 (3004) - ARM_INS_VMUL - vmul${p}.i32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULslv8i16 (3005) - ARM_INS_VMUL - vmul${p}.i16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULv16i8 (3006) - ARM_INS_VMUL - vmul${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULv2i32 (3007) - ARM_INS_VMUL - vmul${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULv4i16 (3008) - ARM_INS_VMUL - vmul${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULv4i32 (3009) - ARM_INS_VMUL - vmul${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULv8i16 (3010) - ARM_INS_VMUL - vmul${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMULv8i8 (3011) - ARM_INS_VMUL - vmul${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMVNd (3012) - ARM_INS_VMVN - vmvn${p} $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMVNq (3013) - ARM_INS_VMVN - vmvn${p} $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMVNv2i32 (3014) - ARM_INS_VMVN - vmvn${p}.i32 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMVNv4i16 (3015) - ARM_INS_VMVN - vmvn${p}.i16 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMVNv4i32 (3016) - ARM_INS_VMVN - vmvn${p}.i32 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VMVNv8i16 (3017) - ARM_INS_VMVN - vmvn${p}.i16 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGD (3018) - ARM_INS_VNEG - vneg${p}.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGH (3019) - ARM_INS_VNEG - vneg${p}.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGS (3020) - ARM_INS_VNEG - vneg${p}.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGf32q (3021) - ARM_INS_VNEG - vneg${p}.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGfd (3022) - ARM_INS_VNEG - vneg${p}.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGhd (3023) - ARM_INS_VNEG - vneg${p}.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGhq (3024) - ARM_INS_VNEG - vneg${p}.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGs16d (3025) - ARM_INS_VNEG - vneg${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGs16q (3026) - ARM_INS_VNEG - vneg${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGs32d (3027) - ARM_INS_VNEG - vneg${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGs32q (3028) - ARM_INS_VNEG - vneg${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGs8d (3029) - ARM_INS_VNEG - vneg${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNEGs8q (3030) - ARM_INS_VNEG - vneg${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNMLAD (3031) - ARM_INS_VNMLA - vnmla${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Ddin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNMLAH (3032) - ARM_INS_VNMLA - vnmla${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNMLAS (3033) - ARM_INS_VNMLA - vnmla${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNMLSD (3034) - ARM_INS_VNMLS - vnmls${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Ddin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNMLSH (3035) - ARM_INS_VNMLS - vnmls${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNMLSS (3036) - ARM_INS_VNMLS - vnmls${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNMULD (3037) - ARM_INS_VNMUL - vnmul${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNMULH (3038) - ARM_INS_VNMUL - vnmul${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VNMULS (3039) - ARM_INS_VNMUL - vnmul${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VORNd (3040) - ARM_INS_VORN - vorn${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VORNq (3041) - ARM_INS_VORN - vorn${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VORRd (3042) - ARM_INS_VORR - vorr${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VORRiv2i32 (3043) - ARM_INS_VORR - vorr${p}.i32 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VORRiv4i16 (3044) - ARM_INS_VORR - vorr${p}.i16 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VORRiv4i32 (3045) - ARM_INS_VORR - vorr${p}.i32 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VORRiv8i16 (3046) - ARM_INS_VORR - vorr${p}.i16 $Vd, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VORRq (3047) - ARM_INS_VORR - vorr${p} $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADALsv16i8 (3048) - ARM_INS_VPADAL - vpadal${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADALsv2i32 (3049) - ARM_INS_VPADAL - vpadal${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADALsv4i16 (3050) - ARM_INS_VPADAL - vpadal${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADALsv4i32 (3051) - ARM_INS_VPADAL - vpadal${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADALsv8i16 (3052) - ARM_INS_VPADAL - vpadal${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADALsv8i8 (3053) - ARM_INS_VPADAL - vpadal${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADALuv16i8 (3054) - ARM_INS_VPADAL - vpadal${p}.u8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADALuv2i32 (3055) - ARM_INS_VPADAL - vpadal${p}.u32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADALuv4i16 (3056) - ARM_INS_VPADAL - vpadal${p}.u16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADALuv4i32 (3057) - ARM_INS_VPADAL - vpadal${p}.u32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADALuv8i16 (3058) - ARM_INS_VPADAL - vpadal${p}.u16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADALuv8i8 (3059) - ARM_INS_VPADAL - vpadal${p}.u8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDLsv16i8 (3060) - ARM_INS_VPADDL - vpaddl${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDLsv2i32 (3061) - ARM_INS_VPADDL - vpaddl${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDLsv4i16 (3062) - ARM_INS_VPADDL - vpaddl${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDLsv4i32 (3063) - ARM_INS_VPADDL - vpaddl${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDLsv8i16 (3064) - ARM_INS_VPADDL - vpaddl${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDLsv8i8 (3065) - ARM_INS_VPADDL - vpaddl${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDLuv16i8 (3066) - ARM_INS_VPADDL - vpaddl${p}.u8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDLuv2i32 (3067) - ARM_INS_VPADDL - vpaddl${p}.u32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDLuv4i16 (3068) - ARM_INS_VPADDL - vpaddl${p}.u16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDLuv4i32 (3069) - ARM_INS_VPADDL - vpaddl${p}.u32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDLuv8i16 (3070) - ARM_INS_VPADDL - vpaddl${p}.u16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDLuv8i8 (3071) - ARM_INS_VPADDL - vpaddl${p}.u8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDf (3072) - ARM_INS_VPADD - vpadd${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDh (3073) - ARM_INS_VPADD - vpadd${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDi16 (3074) - ARM_INS_VPADD - vpadd${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDi32 (3075) - ARM_INS_VPADD - vpadd${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPADDi8 (3076) - ARM_INS_VPADD - vpadd${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMAXf (3077) - ARM_INS_VPMAX - vpmax${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMAXh (3078) - ARM_INS_VPMAX - vpmax${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMAXs16 (3079) - ARM_INS_VPMAX - vpmax${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMAXs32 (3080) - ARM_INS_VPMAX - vpmax${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMAXs8 (3081) - ARM_INS_VPMAX - vpmax${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMAXu16 (3082) - ARM_INS_VPMAX - vpmax${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMAXu32 (3083) - ARM_INS_VPMAX - vpmax${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMAXu8 (3084) - ARM_INS_VPMAX - vpmax${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMINf (3085) - ARM_INS_VPMIN - vpmin${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMINh (3086) - ARM_INS_VPMIN - vpmin${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMINs16 (3087) - ARM_INS_VPMIN - vpmin${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMINs32 (3088) - ARM_INS_VPMIN - vpmin${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMINs8 (3089) - ARM_INS_VPMIN - vpmin${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMINu16 (3090) - ARM_INS_VPMIN - vpmin${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMINu32 (3091) - ARM_INS_VPMIN - vpmin${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VPMINu8 (3092) - ARM_INS_VPMIN - vpmin${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQABSv16i8 (3093) - ARM_INS_VQABS - vqabs${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQABSv2i32 (3094) - ARM_INS_VQABS - vqabs${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQABSv4i16 (3095) - ARM_INS_VQABS - vqabs${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQABSv4i32 (3096) - ARM_INS_VQABS - vqabs${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQABSv8i16 (3097) - ARM_INS_VQABS - vqabs${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQABSv8i8 (3098) - ARM_INS_VQABS - vqabs${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDsv16i8 (3099) - ARM_INS_VQADD - vqadd${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDsv1i64 (3100) - ARM_INS_VQADD - vqadd${p}.s64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDsv2i32 (3101) - ARM_INS_VQADD - vqadd${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDsv2i64 (3102) - ARM_INS_VQADD - vqadd${p}.s64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDsv4i16 (3103) - ARM_INS_VQADD - vqadd${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDsv4i32 (3104) - ARM_INS_VQADD - vqadd${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDsv8i16 (3105) - ARM_INS_VQADD - vqadd${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDsv8i8 (3106) - ARM_INS_VQADD - vqadd${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDuv16i8 (3107) - ARM_INS_VQADD - vqadd${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDuv1i64 (3108) - ARM_INS_VQADD - vqadd${p}.u64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDuv2i32 (3109) - ARM_INS_VQADD - vqadd${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDuv2i64 (3110) - ARM_INS_VQADD - vqadd${p}.u64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDuv4i16 (3111) - ARM_INS_VQADD - vqadd${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDuv4i32 (3112) - ARM_INS_VQADD - vqadd${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDuv8i16 (3113) - ARM_INS_VQADD - vqadd${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQADDuv8i8 (3114) - ARM_INS_VQADD - vqadd${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMLALslv2i32 (3115) - ARM_INS_VQDMLAL - vqdmlal${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMLALslv4i16 (3116) - ARM_INS_VQDMLAL - vqdmlal${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMLALv2i64 (3117) - ARM_INS_VQDMLAL - vqdmlal${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMLALv4i32 (3118) - ARM_INS_VQDMLAL - vqdmlal${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMLSLslv2i32 (3119) - ARM_INS_VQDMLSL - vqdmlsl${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMLSLslv4i16 (3120) - ARM_INS_VQDMLSL - vqdmlsl${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMLSLv2i64 (3121) - ARM_INS_VQDMLSL - vqdmlsl${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMLSLv4i32 (3122) - ARM_INS_VQDMLSL - vqdmlsl${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMULHslv2i32 (3123) - ARM_INS_VQDMULH - vqdmulh${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMULHslv4i16 (3124) - ARM_INS_VQDMULH - vqdmulh${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMULHslv4i32 (3125) - ARM_INS_VQDMULH - vqdmulh${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMULHslv8i16 (3126) - ARM_INS_VQDMULH - vqdmulh${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMULHv2i32 (3127) - ARM_INS_VQDMULH - vqdmulh${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMULHv4i16 (3128) - ARM_INS_VQDMULH - vqdmulh${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMULHv4i32 (3129) - ARM_INS_VQDMULH - vqdmulh${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMULHv8i16 (3130) - ARM_INS_VQDMULH - vqdmulh${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMULLslv2i32 (3131) - ARM_INS_VQDMULL - vqdmull${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMULLslv4i16 (3132) - ARM_INS_VQDMULL - vqdmull${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMULLv2i64 (3133) - ARM_INS_VQDMULL - vqdmull${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQDMULLv4i32 (3134) - ARM_INS_VQDMULL - vqdmull${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQMOVNsuv2i32 (3135) - ARM_INS_VQMOVUN - vqmovun${p}.s64 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQMOVNsuv4i16 (3136) - ARM_INS_VQMOVUN - vqmovun${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQMOVNsuv8i8 (3137) - ARM_INS_VQMOVUN - vqmovun${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQMOVNsv2i32 (3138) - ARM_INS_VQMOVN - vqmovn${p}.s64 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQMOVNsv4i16 (3139) - ARM_INS_VQMOVN - vqmovn${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQMOVNsv8i8 (3140) - ARM_INS_VQMOVN - vqmovn${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQMOVNuv2i32 (3141) - ARM_INS_VQMOVN - vqmovn${p}.u64 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQMOVNuv4i16 (3142) - ARM_INS_VQMOVN - vqmovn${p}.u32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQMOVNuv8i8 (3143) - ARM_INS_VQMOVN - vqmovn${p}.u16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQNEGv16i8 (3144) - ARM_INS_VQNEG - vqneg${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQNEGv2i32 (3145) - ARM_INS_VQNEG - vqneg${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQNEGv4i16 (3146) - ARM_INS_VQNEG - vqneg${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQNEGv4i32 (3147) - ARM_INS_VQNEG - vqneg${p}.s32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQNEGv8i16 (3148) - ARM_INS_VQNEG - vqneg${p}.s16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQNEGv8i8 (3149) - ARM_INS_VQNEG - vqneg${p}.s8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLAHslv2i32 (3150) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLAHslv4i16 (3151) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLAHslv4i32 (3152) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLAHslv8i16 (3153) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLAHv2i32 (3154) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLAHv4i16 (3155) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLAHv4i32 (3156) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLAHv8i16 (3157) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLSHslv2i32 (3158) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLSHslv4i16 (3159) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLSHslv4i32 (3160) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLSHslv8i16 (3161) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLSHv2i32 (3162) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLSHv4i16 (3163) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLSHv4i32 (3164) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMLSHv8i16 (3165) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMULHslv2i32 (3166) - ARM_INS_VQRDMULH - vqrdmulh${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMULHslv4i16 (3167) - ARM_INS_VQRDMULH - vqrdmulh${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMULHslv4i32 (3168) - ARM_INS_VQRDMULH - vqrdmulh${p}.s32 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMULHslv8i16 (3169) - ARM_INS_VQRDMULH - vqrdmulh${p}.s16 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMULHv2i32 (3170) - ARM_INS_VQRDMULH - vqrdmulh${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMULHv4i16 (3171) - ARM_INS_VQRDMULH - vqrdmulh${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMULHv4i32 (3172) - ARM_INS_VQRDMULH - vqrdmulh${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRDMULHv8i16 (3173) - ARM_INS_VQRDMULH - vqrdmulh${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLsv16i8 (3174) - ARM_INS_VQRSHL - vqrshl${p}.s8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLsv1i64 (3175) - ARM_INS_VQRSHL - vqrshl${p}.s64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLsv2i32 (3176) - ARM_INS_VQRSHL - vqrshl${p}.s32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLsv2i64 (3177) - ARM_INS_VQRSHL - vqrshl${p}.s64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLsv4i16 (3178) - ARM_INS_VQRSHL - vqrshl${p}.s16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLsv4i32 (3179) - ARM_INS_VQRSHL - vqrshl${p}.s32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLsv8i16 (3180) - ARM_INS_VQRSHL - vqrshl${p}.s16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLsv8i8 (3181) - ARM_INS_VQRSHL - vqrshl${p}.s8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLuv16i8 (3182) - ARM_INS_VQRSHL - vqrshl${p}.u8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLuv1i64 (3183) - ARM_INS_VQRSHL - vqrshl${p}.u64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLuv2i32 (3184) - ARM_INS_VQRSHL - vqrshl${p}.u32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLuv2i64 (3185) - ARM_INS_VQRSHL - vqrshl${p}.u64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLuv4i16 (3186) - ARM_INS_VQRSHL - vqrshl${p}.u16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLuv4i32 (3187) - ARM_INS_VQRSHL - vqrshl${p}.u32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLuv8i16 (3188) - ARM_INS_VQRSHL - vqrshl${p}.u16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHLuv8i8 (3189) - ARM_INS_VQRSHL - vqrshl${p}.u8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHRNsv2i32 (3190) - ARM_INS_VQRSHRN - vqrshrn${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHRNsv4i16 (3191) - ARM_INS_VQRSHRN - vqrshrn${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHRNsv8i8 (3192) - ARM_INS_VQRSHRN - vqrshrn${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHRNuv2i32 (3193) - ARM_INS_VQRSHRN - vqrshrn${p}.u64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHRNuv4i16 (3194) - ARM_INS_VQRSHRN - vqrshrn${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHRNuv8i8 (3195) - ARM_INS_VQRSHRN - vqrshrn${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHRUNv2i32 (3196) - ARM_INS_VQRSHRUN - vqrshrun${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHRUNv4i16 (3197) - ARM_INS_VQRSHRUN - vqrshrun${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQRSHRUNv8i8 (3198) - ARM_INS_VQRSHRUN - vqrshrun${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsiv16i8 (3199) - ARM_INS_VQSHL - vqshl${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsiv1i64 (3200) - ARM_INS_VQSHL - vqshl${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsiv2i32 (3201) - ARM_INS_VQSHL - vqshl${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsiv2i64 (3202) - ARM_INS_VQSHL - vqshl${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsiv4i16 (3203) - ARM_INS_VQSHL - vqshl${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsiv4i32 (3204) - ARM_INS_VQSHL - vqshl${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsiv8i16 (3205) - ARM_INS_VQSHL - vqshl${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsiv8i8 (3206) - ARM_INS_VQSHL - vqshl${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsuv16i8 (3207) - ARM_INS_VQSHLU - vqshlu${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsuv1i64 (3208) - ARM_INS_VQSHLU - vqshlu${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsuv2i32 (3209) - ARM_INS_VQSHLU - vqshlu${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsuv2i64 (3210) - ARM_INS_VQSHLU - vqshlu${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsuv4i16 (3211) - ARM_INS_VQSHLU - vqshlu${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsuv4i32 (3212) - ARM_INS_VQSHLU - vqshlu${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsuv8i16 (3213) - ARM_INS_VQSHLU - vqshlu${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsuv8i8 (3214) - ARM_INS_VQSHLU - vqshlu${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsv16i8 (3215) - ARM_INS_VQSHL - vqshl${p}.s8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsv1i64 (3216) - ARM_INS_VQSHL - vqshl${p}.s64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsv2i32 (3217) - ARM_INS_VQSHL - vqshl${p}.s32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsv2i64 (3218) - ARM_INS_VQSHL - vqshl${p}.s64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsv4i16 (3219) - ARM_INS_VQSHL - vqshl${p}.s16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsv4i32 (3220) - ARM_INS_VQSHL - vqshl${p}.s32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsv8i16 (3221) - ARM_INS_VQSHL - vqshl${p}.s16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLsv8i8 (3222) - ARM_INS_VQSHL - vqshl${p}.s8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuiv16i8 (3223) - ARM_INS_VQSHL - vqshl${p}.u8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuiv1i64 (3224) - ARM_INS_VQSHL - vqshl${p}.u64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuiv2i32 (3225) - ARM_INS_VQSHL - vqshl${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuiv2i64 (3226) - ARM_INS_VQSHL - vqshl${p}.u64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuiv4i16 (3227) - ARM_INS_VQSHL - vqshl${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuiv4i32 (3228) - ARM_INS_VQSHL - vqshl${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuiv8i16 (3229) - ARM_INS_VQSHL - vqshl${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuiv8i8 (3230) - ARM_INS_VQSHL - vqshl${p}.u8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuv16i8 (3231) - ARM_INS_VQSHL - vqshl${p}.u8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuv1i64 (3232) - ARM_INS_VQSHL - vqshl${p}.u64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuv2i32 (3233) - ARM_INS_VQSHL - vqshl${p}.u32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuv2i64 (3234) - ARM_INS_VQSHL - vqshl${p}.u64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuv4i16 (3235) - ARM_INS_VQSHL - vqshl${p}.u16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuv4i32 (3236) - ARM_INS_VQSHL - vqshl${p}.u32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuv8i16 (3237) - ARM_INS_VQSHL - vqshl${p}.u16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHLuv8i8 (3238) - ARM_INS_VQSHL - vqshl${p}.u8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHRNsv2i32 (3239) - ARM_INS_VQSHRN - vqshrn${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHRNsv4i16 (3240) - ARM_INS_VQSHRN - vqshrn${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHRNsv8i8 (3241) - ARM_INS_VQSHRN - vqshrn${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHRNuv2i32 (3242) - ARM_INS_VQSHRN - vqshrn${p}.u64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHRNuv4i16 (3243) - ARM_INS_VQSHRN - vqshrn${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHRNuv8i8 (3244) - ARM_INS_VQSHRN - vqshrn${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHRUNv2i32 (3245) - ARM_INS_VQSHRUN - vqshrun${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHRUNv4i16 (3246) - ARM_INS_VQSHRUN - vqshrun${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSHRUNv8i8 (3247) - ARM_INS_VQSHRUN - vqshrun${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBsv16i8 (3248) - ARM_INS_VQSUB - vqsub${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBsv1i64 (3249) - ARM_INS_VQSUB - vqsub${p}.s64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBsv2i32 (3250) - ARM_INS_VQSUB - vqsub${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBsv2i64 (3251) - ARM_INS_VQSUB - vqsub${p}.s64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBsv4i16 (3252) - ARM_INS_VQSUB - vqsub${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBsv4i32 (3253) - ARM_INS_VQSUB - vqsub${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBsv8i16 (3254) - ARM_INS_VQSUB - vqsub${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBsv8i8 (3255) - ARM_INS_VQSUB - vqsub${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBuv16i8 (3256) - ARM_INS_VQSUB - vqsub${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBuv1i64 (3257) - ARM_INS_VQSUB - vqsub${p}.u64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBuv2i32 (3258) - ARM_INS_VQSUB - vqsub${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBuv2i64 (3259) - ARM_INS_VQSUB - vqsub${p}.u64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBuv4i16 (3260) - ARM_INS_VQSUB - vqsub${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBuv4i32 (3261) - ARM_INS_VQSUB - vqsub${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBuv8i16 (3262) - ARM_INS_VQSUB - vqsub${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VQSUBuv8i8 (3263) - ARM_INS_VQSUB - vqsub${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRADDHNv2i32 (3264) - ARM_INS_VRADDHN - vraddhn${p}.i64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRADDHNv4i16 (3265) - ARM_INS_VRADDHN - vraddhn${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRADDHNv8i8 (3266) - ARM_INS_VRADDHN - vraddhn${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRECPEd (3267) - ARM_INS_VRECPE - vrecpe${p}.u32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRECPEfd (3268) - ARM_INS_VRECPE - vrecpe${p}.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRECPEfq (3269) - ARM_INS_VRECPE - vrecpe${p}.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRECPEhd (3270) - ARM_INS_VRECPE - vrecpe${p}.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRECPEhq (3271) - ARM_INS_VRECPE - vrecpe${p}.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRECPEq (3272) - ARM_INS_VRECPE - vrecpe${p}.u32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRECPSfd (3273) - ARM_INS_VRECPS - vrecps${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRECPSfq (3274) - ARM_INS_VRECPS - vrecps${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRECPShd (3275) - ARM_INS_VRECPS - vrecps${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRECPShq (3276) - ARM_INS_VRECPS - vrecps${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VREV16d8 (3277) - ARM_INS_VREV16 - vrev16${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VREV16q8 (3278) - ARM_INS_VREV16 - vrev16${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VREV32d16 (3279) - ARM_INS_VREV32 - vrev32${p}.16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VREV32d8 (3280) - ARM_INS_VREV32 - vrev32${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VREV32q16 (3281) - ARM_INS_VREV32 - vrev32${p}.16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VREV32q8 (3282) - ARM_INS_VREV32 - vrev32${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VREV64d16 (3283) - ARM_INS_VREV64 - vrev64${p}.16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VREV64d32 (3284) - ARM_INS_VREV64 - vrev64${p}.32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VREV64d8 (3285) - ARM_INS_VREV64 - vrev64${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VREV64q16 (3286) - ARM_INS_VREV64 - vrev64${p}.16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VREV64q32 (3287) - ARM_INS_VREV64 - vrev64${p}.32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VREV64q8 (3288) - ARM_INS_VREV64 - vrev64${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRHADDsv16i8 (3289) - ARM_INS_VRHADD - vrhadd${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRHADDsv2i32 (3290) - ARM_INS_VRHADD - vrhadd${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRHADDsv4i16 (3291) - ARM_INS_VRHADD - vrhadd${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRHADDsv4i32 (3292) - ARM_INS_VRHADD - vrhadd${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRHADDsv8i16 (3293) - ARM_INS_VRHADD - vrhadd${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRHADDsv8i8 (3294) - ARM_INS_VRHADD - vrhadd${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRHADDuv16i8 (3295) - ARM_INS_VRHADD - vrhadd${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRHADDuv2i32 (3296) - ARM_INS_VRHADD - vrhadd${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRHADDuv4i16 (3297) - ARM_INS_VRHADD - vrhadd${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRHADDuv4i32 (3298) - ARM_INS_VRHADD - vrhadd${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRHADDuv8i16 (3299) - ARM_INS_VRHADD - vrhadd${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRHADDuv8i8 (3300) - ARM_INS_VRHADD - vrhadd${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRINTAD (3301) - ARM_INS_VRINTA - vrinta.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VRINTAH (3302) - ARM_INS_VRINTA - vrinta.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VRINTANDf (3303) - ARM_INS_VRINTA - vrinta.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTANDh (3304) - ARM_INS_VRINTA - vrinta.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTANQf (3305) - ARM_INS_VRINTA - vrinta.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTANQh (3306) - ARM_INS_VRINTA - vrinta.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTAS (3307) - ARM_INS_VRINTA - vrinta.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VRINTMD (3308) - ARM_INS_VRINTM - vrintm.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VRINTMH (3309) - ARM_INS_VRINTM - vrintm.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VRINTMNDf (3310) - ARM_INS_VRINTM - vrintm.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTMNDh (3311) - ARM_INS_VRINTM - vrintm.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTMNQf (3312) - ARM_INS_VRINTM - vrintm.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTMNQh (3313) - ARM_INS_VRINTM - vrintm.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTMS (3314) - ARM_INS_VRINTM - vrintm.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VRINTND (3315) - ARM_INS_VRINTN - vrintn.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VRINTNH (3316) - ARM_INS_VRINTN - vrintn.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VRINTNNDf (3317) - ARM_INS_VRINTN - vrintn.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTNNDh (3318) - ARM_INS_VRINTN - vrintn.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTNNQf (3319) - ARM_INS_VRINTN - vrintn.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTNNQh (3320) - ARM_INS_VRINTN - vrintn.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTNS (3321) - ARM_INS_VRINTN - vrintn.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VRINTPD (3322) - ARM_INS_VRINTP - vrintp.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VRINTPH (3323) - ARM_INS_VRINTP - vrintp.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VRINTPNDf (3324) - ARM_INS_VRINTP - vrintp.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTPNDh (3325) - ARM_INS_VRINTP - vrintp.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTPNQf (3326) - ARM_INS_VRINTP - vrintp.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTPNQh (3327) - ARM_INS_VRINTP - vrintp.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTPS (3328) - ARM_INS_VRINTP - vrintp.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VRINTRD (3329) - ARM_INS_VRINTR - vrintr${p}.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRINTRH (3330) - ARM_INS_VRINTR - vrintr${p}.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRINTRS (3331) - ARM_INS_VRINTR - vrintr${p}.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRINTXD (3332) - ARM_INS_VRINTX - vrintx${p}.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRINTXH (3333) - ARM_INS_VRINTX - vrintx${p}.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRINTXNDf (3334) - ARM_INS_VRINTX - vrintx.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTXNDh (3335) - ARM_INS_VRINTX - vrintx.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTXNQf (3336) - ARM_INS_VRINTX - vrintx.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTXNQh (3337) - ARM_INS_VRINTX - vrintx.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTXS (3338) - ARM_INS_VRINTX - vrintx${p}.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRINTZD (3339) - ARM_INS_VRINTZ - vrintz${p}.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRINTZH (3340) - ARM_INS_VRINTZ - vrintz${p}.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRINTZNDf (3341) - ARM_INS_VRINTZ - vrintz.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTZNDh (3342) - ARM_INS_VRINTZ - vrintz.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTZNQf (3343) - ARM_INS_VRINTZ - vrintz.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTZNQh (3344) - ARM_INS_VRINTZ - vrintz.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VRINTZS (3345) - ARM_INS_VRINTZ - vrintz${p}.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLsv16i8 (3346) - ARM_INS_VRSHL - vrshl${p}.s8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLsv1i64 (3347) - ARM_INS_VRSHL - vrshl${p}.s64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLsv2i32 (3348) - ARM_INS_VRSHL - vrshl${p}.s32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLsv2i64 (3349) - ARM_INS_VRSHL - vrshl${p}.s64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLsv4i16 (3350) - ARM_INS_VRSHL - vrshl${p}.s16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLsv4i32 (3351) - ARM_INS_VRSHL - vrshl${p}.s32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLsv8i16 (3352) - ARM_INS_VRSHL - vrshl${p}.s16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLsv8i8 (3353) - ARM_INS_VRSHL - vrshl${p}.s8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLuv16i8 (3354) - ARM_INS_VRSHL - vrshl${p}.u8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLuv1i64 (3355) - ARM_INS_VRSHL - vrshl${p}.u64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLuv2i32 (3356) - ARM_INS_VRSHL - vrshl${p}.u32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLuv2i64 (3357) - ARM_INS_VRSHL - vrshl${p}.u64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLuv4i16 (3358) - ARM_INS_VRSHL - vrshl${p}.u16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLuv4i32 (3359) - ARM_INS_VRSHL - vrshl${p}.u32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLuv8i16 (3360) - ARM_INS_VRSHL - vrshl${p}.u16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHLuv8i8 (3361) - ARM_INS_VRSHL - vrshl${p}.u8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRNv2i32 (3362) - ARM_INS_VRSHRN - vrshrn${p}.i64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRNv4i16 (3363) - ARM_INS_VRSHRN - vrshrn${p}.i32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRNv8i8 (3364) - ARM_INS_VRSHRN - vrshrn${p}.i16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRsv16i8 (3365) - ARM_INS_VRSHR - vrshr${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRsv1i64 (3366) - ARM_INS_VRSHR - vrshr${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRsv2i32 (3367) - ARM_INS_VRSHR - vrshr${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRsv2i64 (3368) - ARM_INS_VRSHR - vrshr${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRsv4i16 (3369) - ARM_INS_VRSHR - vrshr${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRsv4i32 (3370) - ARM_INS_VRSHR - vrshr${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRsv8i16 (3371) - ARM_INS_VRSHR - vrshr${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRsv8i8 (3372) - ARM_INS_VRSHR - vrshr${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRuv16i8 (3373) - ARM_INS_VRSHR - vrshr${p}.u8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRuv1i64 (3374) - ARM_INS_VRSHR - vrshr${p}.u64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRuv2i32 (3375) - ARM_INS_VRSHR - vrshr${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRuv2i64 (3376) - ARM_INS_VRSHR - vrshr${p}.u64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRuv4i16 (3377) - ARM_INS_VRSHR - vrshr${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRuv4i32 (3378) - ARM_INS_VRSHR - vrshr${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRuv8i16 (3379) - ARM_INS_VRSHR - vrshr${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSHRuv8i8 (3380) - ARM_INS_VRSHR - vrshr${p}.u8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSQRTEd (3381) - ARM_INS_VRSQRTE - vrsqrte${p}.u32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSQRTEfd (3382) - ARM_INS_VRSQRTE - vrsqrte${p}.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSQRTEfq (3383) - ARM_INS_VRSQRTE - vrsqrte${p}.f32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSQRTEhd (3384) - ARM_INS_VRSQRTE - vrsqrte${p}.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSQRTEhq (3385) - ARM_INS_VRSQRTE - vrsqrte${p}.f16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSQRTEq (3386) - ARM_INS_VRSQRTE - vrsqrte${p}.u32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSQRTSfd (3387) - ARM_INS_VRSQRTS - vrsqrts${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSQRTSfq (3388) - ARM_INS_VRSQRTS - vrsqrts${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSQRTShd (3389) - ARM_INS_VRSQRTS - vrsqrts${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSQRTShq (3390) - ARM_INS_VRSQRTS - vrsqrts${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAsv16i8 (3391) - ARM_INS_VRSRA - vrsra${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAsv1i64 (3392) - ARM_INS_VRSRA - vrsra${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAsv2i32 (3393) - ARM_INS_VRSRA - vrsra${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAsv2i64 (3394) - ARM_INS_VRSRA - vrsra${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAsv4i16 (3395) - ARM_INS_VRSRA - vrsra${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAsv4i32 (3396) - ARM_INS_VRSRA - vrsra${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAsv8i16 (3397) - ARM_INS_VRSRA - vrsra${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAsv8i8 (3398) - ARM_INS_VRSRA - vrsra${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAuv16i8 (3399) - ARM_INS_VRSRA - vrsra${p}.u8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAuv1i64 (3400) - ARM_INS_VRSRA - vrsra${p}.u64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAuv2i32 (3401) - ARM_INS_VRSRA - vrsra${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAuv2i64 (3402) - ARM_INS_VRSRA - vrsra${p}.u64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAuv4i16 (3403) - ARM_INS_VRSRA - vrsra${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAuv4i32 (3404) - ARM_INS_VRSRA - vrsra${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAuv8i16 (3405) - ARM_INS_VRSRA - vrsra${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSRAuv8i8 (3406) - ARM_INS_VRSRA - vrsra${p}.u8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSUBHNv2i32 (3407) - ARM_INS_VRSUBHN - vrsubhn${p}.i64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSUBHNv4i16 (3408) - ARM_INS_VRSUBHN - vrsubhn${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VRSUBHNv8i8 (3409) - ARM_INS_VRSUBHN - vrsubhn${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSCCLRMD (3410) - ARM_INS_VSCCLRM - vscclrm{$p} $regs */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_VSCCLRMS (3411) - ARM_INS_VSCCLRM - vscclrm{$p} $regs */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_VSDOTD (3412) - ARM_INS_VSDOT - vsdot.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VSDOTDI (3413) - ARM_INS_VSDOT - vsdot.s8 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { 0 } } + }, + { /* ARM_VSDOTQ (3414) - ARM_INS_VSDOT - vsdot.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VSDOTQI (3415) - ARM_INS_VSDOT - vsdot.s8 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { 0 } } + }, + { /* ARM_VSELEQD (3416) - ARM_INS_VSELEQ - vseleq.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VSELEQH (3417) - ARM_INS_VSELEQ - vseleq.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VSELEQS (3418) - ARM_INS_VSELEQ - vseleq.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VSELGED (3419) - ARM_INS_VSELGE - vselge.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VSELGEH (3420) - ARM_INS_VSELGE - vselge.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VSELGES (3421) - ARM_INS_VSELGE - vselge.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VSELGTD (3422) - ARM_INS_VSELGT - vselgt.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VSELGTH (3423) - ARM_INS_VSELGT - vselgt.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VSELGTS (3424) - ARM_INS_VSELGT - vselgt.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VSELVSD (3425) - ARM_INS_VSELVS - vselvs.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { 0 } } + }, + { /* ARM_VSELVSH (3426) - ARM_INS_VSELVS - vselvs.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VSELVSS (3427) - ARM_INS_VSELVS - vselvs.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { 0 } } + }, + { /* ARM_VSETLNi16 (3428) - ARM_INS_VMOV - vmov${p}.16 $V$lane, $R */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSETLNi32 (3429) - ARM_INS_VMOV - vmov${p}.32 $V$lane, $R */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSETLNi8 (3430) - ARM_INS_VMOV - vmov${p}.8 $V$lane, $R */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* V */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLLi16 (3431) - ARM_INS_VSHLL - vshll${p}.i16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLLi32 (3432) - ARM_INS_VSHLL - vshll${p}.i32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLLi8 (3433) - ARM_INS_VSHLL - vshll${p}.i8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLLsv2i64 (3434) - ARM_INS_VSHLL - vshll${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLLsv4i32 (3435) - ARM_INS_VSHLL - vshll${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLLsv8i16 (3436) - ARM_INS_VSHLL - vshll${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLLuv2i64 (3437) - ARM_INS_VSHLL - vshll${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLLuv4i32 (3438) - ARM_INS_VSHLL - vshll${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLLuv8i16 (3439) - ARM_INS_VSHLL - vshll${p}.u8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLiv16i8 (3440) - ARM_INS_VSHL - vshl${p}.i8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLiv1i64 (3441) - ARM_INS_VSHL - vshl${p}.i64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLiv2i32 (3442) - ARM_INS_VSHL - vshl${p}.i32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLiv2i64 (3443) - ARM_INS_VSHL - vshl${p}.i64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLiv4i16 (3444) - ARM_INS_VSHL - vshl${p}.i16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLiv4i32 (3445) - ARM_INS_VSHL - vshl${p}.i32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLiv8i16 (3446) - ARM_INS_VSHL - vshl${p}.i16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLiv8i8 (3447) - ARM_INS_VSHL - vshl${p}.i8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLsv16i8 (3448) - ARM_INS_VSHL - vshl${p}.s8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLsv1i64 (3449) - ARM_INS_VSHL - vshl${p}.s64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLsv2i32 (3450) - ARM_INS_VSHL - vshl${p}.s32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLsv2i64 (3451) - ARM_INS_VSHL - vshl${p}.s64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLsv4i16 (3452) - ARM_INS_VSHL - vshl${p}.s16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLsv4i32 (3453) - ARM_INS_VSHL - vshl${p}.s32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLsv8i16 (3454) - ARM_INS_VSHL - vshl${p}.s16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLsv8i8 (3455) - ARM_INS_VSHL - vshl${p}.s8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLuv16i8 (3456) - ARM_INS_VSHL - vshl${p}.u8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLuv1i64 (3457) - ARM_INS_VSHL - vshl${p}.u64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLuv2i32 (3458) - ARM_INS_VSHL - vshl${p}.u32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLuv2i64 (3459) - ARM_INS_VSHL - vshl${p}.u64 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLuv4i16 (3460) - ARM_INS_VSHL - vshl${p}.u16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLuv4i32 (3461) - ARM_INS_VSHL - vshl${p}.u32 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLuv8i16 (3462) - ARM_INS_VSHL - vshl${p}.u16 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHLuv8i8 (3463) - ARM_INS_VSHL - vshl${p}.u8 $Vd, $Vm, $Vn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRNv2i32 (3464) - ARM_INS_VSHRN - vshrn${p}.i64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRNv4i16 (3465) - ARM_INS_VSHRN - vshrn${p}.i32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRNv8i8 (3466) - ARM_INS_VSHRN - vshrn${p}.i16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRsv16i8 (3467) - ARM_INS_VSHR - vshr${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRsv1i64 (3468) - ARM_INS_VSHR - vshr${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRsv2i32 (3469) - ARM_INS_VSHR - vshr${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRsv2i64 (3470) - ARM_INS_VSHR - vshr${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRsv4i16 (3471) - ARM_INS_VSHR - vshr${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRsv4i32 (3472) - ARM_INS_VSHR - vshr${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRsv8i16 (3473) - ARM_INS_VSHR - vshr${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRsv8i8 (3474) - ARM_INS_VSHR - vshr${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRuv16i8 (3475) - ARM_INS_VSHR - vshr${p}.u8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRuv1i64 (3476) - ARM_INS_VSHR - vshr${p}.u64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRuv2i32 (3477) - ARM_INS_VSHR - vshr${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRuv2i64 (3478) - ARM_INS_VSHR - vshr${p}.u64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRuv4i16 (3479) - ARM_INS_VSHR - vshr${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRuv4i32 (3480) - ARM_INS_VSHR - vshr${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRuv8i16 (3481) - ARM_INS_VSHR - vshr${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHRuv8i8 (3482) - ARM_INS_VSHR - vshr${p}.u8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHTOD (3483) - ARM_INS_VCVT - vcvt${p}.f64.s16 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHTOH (3484) - ARM_INS_VCVT - vcvt${p}.f16.s16 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSHTOS (3485) - ARM_INS_VCVT - vcvt${p}.f32.s16 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSITOD (3486) - ARM_INS_VCVT - vcvt${p}.f64.s32 $Dd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSITOH (3487) - ARM_INS_VCVT - vcvt${p}.f16.s32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSITOS (3488) - ARM_INS_VCVT - vcvt${p}.f32.s32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSLIv16i8 (3489) - ARM_INS_VSLI - vsli${p}.8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSLIv1i64 (3490) - ARM_INS_VSLI - vsli${p}.64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSLIv2i32 (3491) - ARM_INS_VSLI - vsli${p}.32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSLIv2i64 (3492) - ARM_INS_VSLI - vsli${p}.64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSLIv4i16 (3493) - ARM_INS_VSLI - vsli${p}.16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSLIv4i32 (3494) - ARM_INS_VSLI - vsli${p}.32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSLIv8i16 (3495) - ARM_INS_VSLI - vsli${p}.16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSLIv8i8 (3496) - ARM_INS_VSLI - vsli${p}.8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSLTOD (3497) - ARM_INS_VCVT - vcvt${p}.f64.s32 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSLTOH (3498) - ARM_INS_VCVT - vcvt${p}.f16.s32 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSLTOS (3499) - ARM_INS_VCVT - vcvt${p}.f32.s32 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSMMLA (3500) - ARM_INS_VSMMLA - vsmmla.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VSQRTD (3501) - ARM_INS_VSQRT - vsqrt${p}.f64 $Dd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSQRTH (3502) - ARM_INS_VSQRT - vsqrt${p}.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSQRTS (3503) - ARM_INS_VSQRT - vsqrt${p}.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAsv16i8 (3504) - ARM_INS_VSRA - vsra${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAsv1i64 (3505) - ARM_INS_VSRA - vsra${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAsv2i32 (3506) - ARM_INS_VSRA - vsra${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAsv2i64 (3507) - ARM_INS_VSRA - vsra${p}.s64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAsv4i16 (3508) - ARM_INS_VSRA - vsra${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAsv4i32 (3509) - ARM_INS_VSRA - vsra${p}.s32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAsv8i16 (3510) - ARM_INS_VSRA - vsra${p}.s16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAsv8i8 (3511) - ARM_INS_VSRA - vsra${p}.s8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAuv16i8 (3512) - ARM_INS_VSRA - vsra${p}.u8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAuv1i64 (3513) - ARM_INS_VSRA - vsra${p}.u64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAuv2i32 (3514) - ARM_INS_VSRA - vsra${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAuv2i64 (3515) - ARM_INS_VSRA - vsra${p}.u64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAuv4i16 (3516) - ARM_INS_VSRA - vsra${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAuv4i32 (3517) - ARM_INS_VSRA - vsra${p}.u32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAuv8i16 (3518) - ARM_INS_VSRA - vsra${p}.u16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRAuv8i8 (3519) - ARM_INS_VSRA - vsra${p}.u8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRIv16i8 (3520) - ARM_INS_VSRI - vsri${p}.8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRIv1i64 (3521) - ARM_INS_VSRI - vsri${p}.64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRIv2i32 (3522) - ARM_INS_VSRI - vsri${p}.32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRIv2i64 (3523) - ARM_INS_VSRI - vsri${p}.64 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRIv4i16 (3524) - ARM_INS_VSRI - vsri${p}.16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRIv4i32 (3525) - ARM_INS_VSRI - vsri${p}.32 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRIv8i16 (3526) - ARM_INS_VSRI - vsri${p}.16 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSRIv8i8 (3527) - ARM_INS_VSRI - vsri${p}.8 $Vd, $Vm, $SIMM */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNd16 (3528) - ARM_INS_VST1 - vst1${p}.16 \{$Vd[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNd16_UPD (3529) - ARM_INS_VST1 - vst1${p}.16 \{$Vd[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNd32 (3530) - ARM_INS_VST1 - vst1${p}.32 \{$Vd[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNd32_UPD (3531) - ARM_INS_VST1 - vst1${p}.32 \{$Vd[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNd8 (3532) - ARM_INS_VST1 - vst1${p}.8 \{$Vd[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1LNd8_UPD (3533) - ARM_INS_VST1 - vst1${p}.8 \{$Vd[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1LNq16Pseudo (3534) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1LNq16Pseudo_UPD (3535) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1LNq32Pseudo (3536) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1LNq32Pseudo_UPD (3537) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1LNq8Pseudo (3538) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1LNq8Pseudo_UPD (3539) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1d16 (3540) - ARM_INS_VST1 - vst1${p}.16 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d16Q (3541) - ARM_INS_VST1 - vst1${p}.16 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1d16QPseudo (3542) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d16QPseudoWB_fixed (3543) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d16QPseudoWB_register (3544) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1d16Qwb_fixed (3545) - ARM_INS_VST1 - vst1${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d16Qwb_register (3546) - ARM_INS_VST1 - vst1${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d16T (3547) - ARM_INS_VST1 - vst1${p}.16 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1d16TPseudo (3548) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d16TPseudoWB_fixed (3549) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d16TPseudoWB_register (3550) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1d16Twb_fixed (3551) - ARM_INS_VST1 - vst1${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d16Twb_register (3552) - ARM_INS_VST1 - vst1${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d16wb_fixed (3553) - ARM_INS_VST1 - vst1${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d16wb_register (3554) - ARM_INS_VST1 - vst1${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d32 (3555) - ARM_INS_VST1 - vst1${p}.32 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d32Q (3556) - ARM_INS_VST1 - vst1${p}.32 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1d32QPseudo (3557) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d32QPseudoWB_fixed (3558) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d32QPseudoWB_register (3559) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1d32Qwb_fixed (3560) - ARM_INS_VST1 - vst1${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d32Qwb_register (3561) - ARM_INS_VST1 - vst1${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d32T (3562) - ARM_INS_VST1 - vst1${p}.32 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1d32TPseudo (3563) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d32TPseudoWB_fixed (3564) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d32TPseudoWB_register (3565) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1d32Twb_fixed (3566) - ARM_INS_VST1 - vst1${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d32Twb_register (3567) - ARM_INS_VST1 - vst1${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d32wb_fixed (3568) - ARM_INS_VST1 - vst1${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d32wb_register (3569) - ARM_INS_VST1 - vst1${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d64 (3570) - ARM_INS_VST1 - vst1${p}.64 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d64Q (3571) - ARM_INS_VST1 - vst1${p}.64 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1d64QPseudo (3572) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d64QPseudoWB_fixed (3573) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d64QPseudoWB_register (3574) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1d64Qwb_fixed (3575) - ARM_INS_VST1 - vst1${p}.64 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d64Qwb_register (3576) - ARM_INS_VST1 - vst1${p}.64 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d64T (3577) - ARM_INS_VST1 - vst1${p}.64 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1d64TPseudo (3578) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d64TPseudoWB_fixed (3579) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d64TPseudoWB_register (3580) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1d64Twb_fixed (3581) - ARM_INS_VST1 - vst1${p}.64 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d64Twb_register (3582) - ARM_INS_VST1 - vst1${p}.64 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d64wb_fixed (3583) - ARM_INS_VST1 - vst1${p}.64 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d64wb_register (3584) - ARM_INS_VST1 - vst1${p}.64 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d8 (3585) - ARM_INS_VST1 - vst1${p}.8 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d8Q (3586) - ARM_INS_VST1 - vst1${p}.8 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1d8QPseudo (3587) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d8QPseudoWB_fixed (3588) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d8QPseudoWB_register (3589) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1d8Qwb_fixed (3590) - ARM_INS_VST1 - vst1${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d8Qwb_register (3591) - ARM_INS_VST1 - vst1${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d8T (3592) - ARM_INS_VST1 - vst1${p}.8 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1d8TPseudo (3593) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d8TPseudoWB_fixed (3594) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1d8TPseudoWB_register (3595) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1d8Twb_fixed (3596) - ARM_INS_VST1 - vst1${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d8Twb_register (3597) - ARM_INS_VST1 - vst1${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d8wb_fixed (3598) - ARM_INS_VST1 - vst1${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1d8wb_register (3599) - ARM_INS_VST1 - vst1${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1q16 (3600) - ARM_INS_VST1 - vst1${p}.16 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1q16HighQPseudo (3601) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q16HighQPseudo_UPD (3602) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q16HighTPseudo (3603) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q16HighTPseudo_UPD (3604) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q16LowQPseudo_UPD (3605) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q16LowTPseudo_UPD (3606) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1q16wb_fixed (3607) - ARM_INS_VST1 - vst1${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1q16wb_register (3608) - ARM_INS_VST1 - vst1${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1q32 (3609) - ARM_INS_VST1 - vst1${p}.32 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1q32HighQPseudo (3610) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q32HighQPseudo_UPD (3611) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q32HighTPseudo (3612) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q32HighTPseudo_UPD (3613) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q32LowQPseudo_UPD (3614) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q32LowTPseudo_UPD (3615) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1q32wb_fixed (3616) - ARM_INS_VST1 - vst1${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1q32wb_register (3617) - ARM_INS_VST1 - vst1${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1q64 (3618) - ARM_INS_VST1 - vst1${p}.64 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1q64HighQPseudo (3619) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q64HighQPseudo_UPD (3620) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q64HighTPseudo (3621) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q64HighTPseudo_UPD (3622) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q64LowQPseudo_UPD (3623) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q64LowTPseudo_UPD (3624) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1q64wb_fixed (3625) - ARM_INS_VST1 - vst1${p}.64 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1q64wb_register (3626) - ARM_INS_VST1 - vst1${p}.64 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1q8 (3627) - ARM_INS_VST1 - vst1${p}.8 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST1q8HighQPseudo (3628) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q8HighQPseudo_UPD (3629) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q8HighTPseudo (3630) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q8HighTPseudo_UPD (3631) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q8LowQPseudo_UPD (3632) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST1q8LowTPseudo_UPD (3633) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST1q8wb_fixed (3634) - ARM_INS_VST1 - vst1${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST1q8wb_register (3635) - ARM_INS_VST1 - vst1${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNd16 (3636) - ARM_INS_VST2 - vst2${p}.16 \{$Vd[$lane], $src2[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST2LNd16Pseudo (3637) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST2LNd16Pseudo_UPD (3638) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST2LNd16_UPD (3639) - ARM_INS_VST2 - vst2${p}.16 \{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNd32 (3640) - ARM_INS_VST2 - vst2${p}.32 \{$Vd[$lane], $src2[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST2LNd32Pseudo (3641) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST2LNd32Pseudo_UPD (3642) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST2LNd32_UPD (3643) - ARM_INS_VST2 - vst2${p}.32 \{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNd8 (3644) - ARM_INS_VST2 - vst2${p}.8 \{$Vd[$lane], $src2[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST2LNd8Pseudo (3645) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST2LNd8Pseudo_UPD (3646) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST2LNd8_UPD (3647) - ARM_INS_VST2 - vst2${p}.8 \{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNq16 (3648) - ARM_INS_VST2 - vst2${p}.16 \{$Vd[$lane], $src2[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST2LNq16Pseudo (3649) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST2LNq16Pseudo_UPD (3650) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST2LNq16_UPD (3651) - ARM_INS_VST2 - vst2${p}.16 \{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2LNq32 (3652) - ARM_INS_VST2 - vst2${p}.32 \{$Vd[$lane], $src2[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST2LNq32Pseudo (3653) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST2LNq32Pseudo_UPD (3654) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST2LNq32_UPD (3655) - ARM_INS_VST2 - vst2${p}.32 \{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2b16 (3656) - ARM_INS_VST2 - vst2${p}.16 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2b16wb_fixed (3657) - ARM_INS_VST2 - vst2${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2b16wb_register (3658) - ARM_INS_VST2 - vst2${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2b32 (3659) - ARM_INS_VST2 - vst2${p}.32 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2b32wb_fixed (3660) - ARM_INS_VST2 - vst2${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2b32wb_register (3661) - ARM_INS_VST2 - vst2${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2b8 (3662) - ARM_INS_VST2 - vst2${p}.8 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2b8wb_fixed (3663) - ARM_INS_VST2 - vst2${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2b8wb_register (3664) - ARM_INS_VST2 - vst2${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2d16 (3665) - ARM_INS_VST2 - vst2${p}.16 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2d16wb_fixed (3666) - ARM_INS_VST2 - vst2${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2d16wb_register (3667) - ARM_INS_VST2 - vst2${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2d32 (3668) - ARM_INS_VST2 - vst2${p}.32 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2d32wb_fixed (3669) - ARM_INS_VST2 - vst2${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2d32wb_register (3670) - ARM_INS_VST2 - vst2${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2d8 (3671) - ARM_INS_VST2 - vst2${p}.8 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2d8wb_fixed (3672) - ARM_INS_VST2 - vst2${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2d8wb_register (3673) - ARM_INS_VST2 - vst2${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2q16 (3674) - ARM_INS_VST2 - vst2${p}.16 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST2q16Pseudo (3675) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST2q16PseudoWB_fixed (3676) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST2q16PseudoWB_register (3677) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST2q16wb_fixed (3678) - ARM_INS_VST2 - vst2${p}.16 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2q16wb_register (3679) - ARM_INS_VST2 - vst2${p}.16 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2q32 (3680) - ARM_INS_VST2 - vst2${p}.32 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST2q32Pseudo (3681) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST2q32PseudoWB_fixed (3682) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST2q32PseudoWB_register (3683) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST2q32wb_fixed (3684) - ARM_INS_VST2 - vst2${p}.32 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2q32wb_register (3685) - ARM_INS_VST2 - vst2${p}.32 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2q8 (3686) - ARM_INS_VST2 - vst2${p}.8 $Vd, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST2q8Pseudo (3687) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST2q8PseudoWB_fixed (3688) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST2q8PseudoWB_register (3689) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST2q8wb_fixed (3690) - ARM_INS_VST2 - vst2${p}.8 $Vd, $Rn! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST2q8wb_register (3691) - ARM_INS_VST2 - vst2${p}.8 $Vd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNd16 (3692) - ARM_INS_VST3 - vst3${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3LNd16Pseudo (3693) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST3LNd16Pseudo_UPD (3694) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3LNd16_UPD (3695) - ARM_INS_VST3 - vst3${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNd32 (3696) - ARM_INS_VST3 - vst3${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3LNd32Pseudo (3697) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST3LNd32Pseudo_UPD (3698) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3LNd32_UPD (3699) - ARM_INS_VST3 - vst3${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNd8 (3700) - ARM_INS_VST3 - vst3${p}.8 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3LNd8Pseudo (3701) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST3LNd8Pseudo_UPD (3702) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3LNd8_UPD (3703) - ARM_INS_VST3 - vst3${p}.8 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNq16 (3704) - ARM_INS_VST3 - vst3${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3LNq16Pseudo (3705) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST3LNq16Pseudo_UPD (3706) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3LNq16_UPD (3707) - ARM_INS_VST3 - vst3${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3LNq32 (3708) - ARM_INS_VST3 - vst3${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3LNq32Pseudo (3709) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST3LNq32Pseudo_UPD (3710) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3LNq32_UPD (3711) - ARM_INS_VST3 - vst3${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3d16 (3712) - ARM_INS_VST3 - vst3${p}.16 \{$Vd, $src2, $src3\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3d16Pseudo (3713) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST3d16Pseudo_UPD (3714) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3d16_UPD (3715) - ARM_INS_VST3 - vst3${p}.16 \{$Vd, $src2, $src3\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3d32 (3716) - ARM_INS_VST3 - vst3${p}.32 \{$Vd, $src2, $src3\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3d32Pseudo (3717) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST3d32Pseudo_UPD (3718) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3d32_UPD (3719) - ARM_INS_VST3 - vst3${p}.32 \{$Vd, $src2, $src3\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3d8 (3720) - ARM_INS_VST3 - vst3${p}.8 \{$Vd, $src2, $src3\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3d8Pseudo (3721) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST3d8Pseudo_UPD (3722) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3d8_UPD (3723) - ARM_INS_VST3 - vst3${p}.8 \{$Vd, $src2, $src3\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST3q16 (3724) - ARM_INS_VST3 - vst3${p}.16 \{$Vd, $src2, $src3\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3q16Pseudo_UPD (3725) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3q16_UPD (3726) - ARM_INS_VST3 - vst3${p}.16 \{$Vd, $src2, $src3\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3q16oddPseudo (3727) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST3q16oddPseudo_UPD (3728) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3q32 (3729) - ARM_INS_VST3 - vst3${p}.32 \{$Vd, $src2, $src3\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3q32Pseudo_UPD (3730) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3q32_UPD (3731) - ARM_INS_VST3 - vst3${p}.32 \{$Vd, $src2, $src3\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3q32oddPseudo (3732) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST3q32oddPseudo_UPD (3733) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3q8 (3734) - ARM_INS_VST3 - vst3${p}.8 \{$Vd, $src2, $src3\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3q8Pseudo_UPD (3735) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST3q8_UPD (3736) - ARM_INS_VST3 - vst3${p}.8 \{$Vd, $src2, $src3\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST3q8oddPseudo (3737) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST3q8oddPseudo_UPD (3738) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4LNd16 (3739) - ARM_INS_VST4 - vst4${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4LNd16Pseudo (3740) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST4LNd16Pseudo_UPD (3741) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4LNd16_UPD (3742) - ARM_INS_VST4 - vst4${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNd32 (3743) - ARM_INS_VST4 - vst4${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4LNd32Pseudo (3744) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST4LNd32Pseudo_UPD (3745) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4LNd32_UPD (3746) - ARM_INS_VST4 - vst4${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNd8 (3747) - ARM_INS_VST4 - vst4${p}.8 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4LNd8Pseudo (3748) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST4LNd8Pseudo_UPD (3749) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4LNd8_UPD (3750) - ARM_INS_VST4 - vst4${p}.8 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNq16 (3751) - ARM_INS_VST4 - vst4${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4LNq16Pseudo (3752) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST4LNq16Pseudo_UPD (3753) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4LNq16_UPD (3754) - ARM_INS_VST4 - vst4${p}.16 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4LNq32 (3755) - ARM_INS_VST4 - vst4${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4LNq32Pseudo (3756) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST4LNq32Pseudo_UPD (3757) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4LNq32_UPD (3758) - ARM_INS_VST4 - vst4${p}.32 \{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4d16 (3759) - ARM_INS_VST4 - vst4${p}.16 \{$Vd, $src2, $src3, $src4\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4d16Pseudo (3760) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST4d16Pseudo_UPD (3761) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4d16_UPD (3762) - ARM_INS_VST4 - vst4${p}.16 \{$Vd, $src2, $src3, $src4\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4d32 (3763) - ARM_INS_VST4 - vst4${p}.32 \{$Vd, $src2, $src3, $src4\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4d32Pseudo (3764) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST4d32Pseudo_UPD (3765) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4d32_UPD (3766) - ARM_INS_VST4 - vst4${p}.32 \{$Vd, $src2, $src3, $src4\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4d8 (3767) - ARM_INS_VST4 - vst4${p}.8 \{$Vd, $src2, $src3, $src4\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4d8Pseudo (3768) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST4d8Pseudo_UPD (3769) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4d8_UPD (3770) - ARM_INS_VST4 - vst4${p}.8 \{$Vd, $src2, $src3, $src4\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VST4q16 (3771) - ARM_INS_VST4 - vst4${p}.16 \{$Vd, $src2, $src3, $src4\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4q16Pseudo_UPD (3772) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4q16_UPD (3773) - ARM_INS_VST4 - vst4${p}.16 \{$Vd, $src2, $src3, $src4\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4q16oddPseudo (3774) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST4q16oddPseudo_UPD (3775) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4q32 (3776) - ARM_INS_VST4 - vst4${p}.32 \{$Vd, $src2, $src3, $src4\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4q32Pseudo_UPD (3777) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4q32_UPD (3778) - ARM_INS_VST4 - vst4${p}.32 \{$Vd, $src2, $src3, $src4\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4q32oddPseudo (3779) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST4q32oddPseudo_UPD (3780) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4q8 (3781) - ARM_INS_VST4 - vst4${p}.8 \{$Vd, $src2, $src3, $src4\}, $Rn */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4q8Pseudo_UPD (3782) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VST4q8_UPD (3783) - ARM_INS_VST4 - vst4${p}.8 \{$Vd, $src2, $src3, $src4\}, $Rn$Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src3 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src4 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VST4q8oddPseudo (3784) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_VST4q8oddPseudo_UPD (3785) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VSTMDDB_UPD (3786) - ARM_INS_VSTMDB - vstmdb${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_VSTMDIA (3787) - ARM_INS_VSTMIA - vstmia${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_VSTMDIA_UPD (3788) - ARM_INS_VSTMIA - vstmia${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { { { /* ARM_VSTMQIA (3789) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VSTMSDB_UPD (3790) - ARM_INS_VSTMDB - vstmdb${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_VSTMSIA (3791) - ARM_INS_VSTMIA - vstmia${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_VSTMSIA_UPD (3792) - ARM_INS_VSTMIA - vstmia${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_VSTRD (3793) - ARM_INS_VSTR - vstr${p} $Dd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTRH (3794) - ARM_INS_VSTR - vstr${p}.16 $Sd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTRS (3795) - ARM_INS_VSTR - vstr${p} $Sd, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_FPCXTNS_off (3796) - ARM_INS_VSTR - vstr${p} fpcxtns, $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_FPCXTNS_post (3797) - ARM_INS_VSTR - vstr${p} fpcxtns, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_FPCXTNS_pre (3798) - ARM_INS_VSTR - vstr${p} fpcxtns, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_FPCXTS_off (3799) - ARM_INS_VSTR - vstr${p} fpcxts, $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_FPCXTS_post (3800) - ARM_INS_VSTR - vstr${p} fpcxts, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_FPCXTS_pre (3801) - ARM_INS_VSTR - vstr${p} fpcxts, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_FPSCR_NZCVQC_off (3802) - ARM_INS_VSTR - vstr${p} fpscr_nzcvqc, $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_FPSCR_NZCVQC_post (3803) - ARM_INS_VSTR - vstr${p} fpscr_nzcvqc, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_FPSCR_NZCVQC_pre (3804) - ARM_INS_VSTR - vstr${p} fpscr_nzcvqc, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_FPSCR_off (3805) - ARM_INS_VSTR - vstr${p} fpscr, $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_FPSCR_post (3806) - ARM_INS_VSTR - vstr${p} fpscr, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_FPSCR_pre (3807) - ARM_INS_VSTR - vstr${p} fpscr, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_P0_off (3808) - ARM_INS_VSTR - vstr${p} p0, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_P0_post (3809) - ARM_INS_VSTR - vstr${p} p0, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_P0_pre (3810) - ARM_INS_VSTR - vstr${p} p0, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, + CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, + CS_DATA_TYPE_LAST } }, /* P0 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_VPR_off (3811) - ARM_INS_VSTR - vstr${p} vpr, $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_VPR_post (3812) - ARM_INS_VSTR - vstr${p} vpr, $Rn$addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSTR_VPR_pre (3813) - ARM_INS_VSTR - vstr${p} vpr, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBD (3814) - ARM_INS_VSUB - vsub${p}.f64 $Dd, $Dn, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBH (3815) - ARM_INS_VSUB - vsub${p}.f16 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBHNv2i32 (3816) - ARM_INS_VSUBHN - vsubhn${p}.i64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBHNv4i16 (3817) - ARM_INS_VSUBHN - vsubhn${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBHNv8i8 (3818) - ARM_INS_VSUBHN - vsubhn${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBLsv2i64 (3819) - ARM_INS_VSUBL - vsubl${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBLsv4i32 (3820) - ARM_INS_VSUBL - vsubl${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBLsv8i16 (3821) - ARM_INS_VSUBL - vsubl${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBLuv2i64 (3822) - ARM_INS_VSUBL - vsubl${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBLuv4i32 (3823) - ARM_INS_VSUBL - vsubl${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBLuv8i16 (3824) - ARM_INS_VSUBL - vsubl${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBS (3825) - ARM_INS_VSUB - vsub${p}.f32 $Sd, $Sn, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBWsv2i64 (3826) - ARM_INS_VSUBW - vsubw${p}.s32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBWsv4i32 (3827) - ARM_INS_VSUBW - vsubw${p}.s16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBWsv8i16 (3828) - ARM_INS_VSUBW - vsubw${p}.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBWuv2i64 (3829) - ARM_INS_VSUBW - vsubw${p}.u32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBWuv4i32 (3830) - ARM_INS_VSUBW - vsubw${p}.u16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBWuv8i16 (3831) - ARM_INS_VSUBW - vsubw${p}.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBfd (3832) - ARM_INS_VSUB - vsub${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBfq (3833) - ARM_INS_VSUB - vsub${p}.f32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBhd (3834) - ARM_INS_VSUB - vsub${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBhq (3835) - ARM_INS_VSUB - vsub${p}.f16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBv16i8 (3836) - ARM_INS_VSUB - vsub${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBv1i64 (3837) - ARM_INS_VSUB - vsub${p}.i64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBv2i32 (3838) - ARM_INS_VSUB - vsub${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBv2i64 (3839) - ARM_INS_VSUB - vsub${p}.i64 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBv4i16 (3840) - ARM_INS_VSUB - vsub${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBv4i32 (3841) - ARM_INS_VSUB - vsub${p}.i32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBv8i16 (3842) - ARM_INS_VSUB - vsub${p}.i16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUBv8i8 (3843) - ARM_INS_VSUB - vsub${p}.i8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSUDOTDI (3844) - ARM_INS_VSUDOT - vsudot.u8 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { 0 } } + }, + { /* ARM_VSUDOTQI (3845) - ARM_INS_VSUDOT - vsudot.u8 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { 0 } } + }, + { /* ARM_VSWPd (3846) - ARM_INS_VSWP - vswp${p} $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* in1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* in2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VSWPq (3847) - ARM_INS_VSWP - vswp${p} $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* in1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* in2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTBL1 (3848) - ARM_INS_VTBL - vtbl${p}.8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTBL2 (3849) - ARM_INS_VTBL - vtbl${p}.8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTBL3 (3850) - ARM_INS_VTBL - vtbl${p}.8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VTBL3Pseudo (3851) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VTBL4 (3852) - ARM_INS_VTBL - vtbl${p}.8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VTBL4Pseudo (3853) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VTBX1 (3854) - ARM_INS_VTBX - vtbx${p}.8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* orig */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTBX2 (3855) - ARM_INS_VTBX - vtbx${p}.8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* orig */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTBX3 (3856) - ARM_INS_VTBX - vtbx${p}.8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* orig */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VTBX3Pseudo (3857) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VTBX4 (3858) - ARM_INS_VTBX - vtbx${p}.8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* orig */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_VTBX4Pseudo (3859) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_VTOSHD (3860) - ARM_INS_VCVT - vcvt${p}.s16.f64 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOSHH (3861) - ARM_INS_VCVT - vcvt${p}.s16.f16 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOSHS (3862) - ARM_INS_VCVT - vcvt${p}.s16.f32 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOSIRD (3863) - ARM_INS_VCVTR - vcvtr${p}.s32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOSIRH (3864) - ARM_INS_VCVTR - vcvtr${p}.s32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOSIRS (3865) - ARM_INS_VCVTR - vcvtr${p}.s32.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOSIZD (3866) - ARM_INS_VCVT - vcvt${p}.s32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOSIZH (3867) - ARM_INS_VCVT - vcvt${p}.s32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOSIZS (3868) - ARM_INS_VCVT - vcvt${p}.s32.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOSLD (3869) - ARM_INS_VCVT - vcvt${p}.s32.f64 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOSLH (3870) - ARM_INS_VCVT - vcvt${p}.s32.f16 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOSLS (3871) - ARM_INS_VCVT - vcvt${p}.s32.f32 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOUHD (3872) - ARM_INS_VCVT - vcvt${p}.u16.f64 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOUHH (3873) - ARM_INS_VCVT - vcvt${p}.u16.f16 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOUHS (3874) - ARM_INS_VCVT - vcvt${p}.u16.f32 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOUIRD (3875) - ARM_INS_VCVTR - vcvtr${p}.u32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOUIRH (3876) - ARM_INS_VCVTR - vcvtr${p}.u32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOUIRS (3877) - ARM_INS_VCVTR - vcvtr${p}.u32.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOUIZD (3878) - ARM_INS_VCVT - vcvt${p}.u32.f64 $Sd, $Dm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOUIZH (3879) - ARM_INS_VCVT - vcvt${p}.u32.f16 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOUIZS (3880) - ARM_INS_VCVT - vcvt${p}.u32.f32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOULD (3881) - ARM_INS_VCVT - vcvt${p}.u32.f64 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOULH (3882) - ARM_INS_VCVT - vcvt${p}.u32.f16 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTOULS (3883) - ARM_INS_VCVT - vcvt${p}.u32.f32 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTRNd16 (3884) - ARM_INS_VTRN - vtrn${p}.16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTRNd32 (3885) - ARM_INS_VTRN - vtrn${p}.32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTRNd8 (3886) - ARM_INS_VTRN - vtrn${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTRNq16 (3887) - ARM_INS_VTRN - vtrn${p}.16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTRNq32 (3888) - ARM_INS_VTRN - vtrn${p}.32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTRNq8 (3889) - ARM_INS_VTRN - vtrn${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTSTv16i8 (3890) - ARM_INS_VTST - vtst${p}.8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTSTv2i32 (3891) - ARM_INS_VTST - vtst${p}.32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTSTv4i16 (3892) - ARM_INS_VTST - vtst${p}.16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTSTv4i32 (3893) - ARM_INS_VTST - vtst${p}.32 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTSTv8i16 (3894) - ARM_INS_VTST - vtst${p}.16 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VTSTv8i8 (3895) - ARM_INS_VTST - vtst${p}.8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VUDOTD (3896) - ARM_INS_VUDOT - vudot.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VUDOTDI (3897) - ARM_INS_VUDOT - vudot.u8 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { 0 } } + }, + { /* ARM_VUDOTQ (3898) - ARM_INS_VUDOT - vudot.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VUDOTQI (3899) - ARM_INS_VUDOT - vudot.u8 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { 0 } } + }, + { /* ARM_VUHTOD (3900) - ARM_INS_VCVT - vcvt${p}.f64.u16 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VUHTOH (3901) - ARM_INS_VCVT - vcvt${p}.f16.u16 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VUHTOS (3902) - ARM_INS_VCVT - vcvt${p}.f32.u16 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VUITOD (3903) - ARM_INS_VCVT - vcvt${p}.f64.u32 $Dd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Dd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VUITOH (3904) - ARM_INS_VCVT - vcvt${p}.f16.u32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, + CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VUITOS (3905) - ARM_INS_VCVT - vcvt${p}.f32.u32 $Sd, $Sm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VULTOD (3906) - ARM_INS_VCVT - vcvt${p}.f64.u32 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VULTOH (3907) - ARM_INS_VCVT - vcvt${p}.f16.u32 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VULTOS (3908) - ARM_INS_VCVT - vcvt${p}.f32.u32 $dst, $a, $fbits */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VUMMLA (3909) - ARM_INS_VUMMLA - vummla.u8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VUSDOTD (3910) - ARM_INS_VUSDOT - vusdot.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VUSDOTDI (3911) - ARM_INS_VUSDOT - vusdot.s8 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { 0 } } + }, + { /* ARM_VUSDOTQ (3912) - ARM_INS_VUSDOT - vusdot.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VUSDOTQI (3913) - ARM_INS_VUSDOT - vusdot.s8 $Vd, $Vn, $Vm$lane */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */ + { 0 } } + }, + { /* ARM_VUSMMLA (3914) - ARM_INS_VUSMMLA - vusmmla.s8 $Vd, $Vn, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { 0 } } + }, + { /* ARM_VUZPd16 (3915) - ARM_INS_VUZP - vuzp${p}.16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VUZPd8 (3916) - ARM_INS_VUZP - vuzp${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VUZPq16 (3917) - ARM_INS_VUZP - vuzp${p}.16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VUZPq32 (3918) - ARM_INS_VUZP - vuzp${p}.32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VUZPq8 (3919) - ARM_INS_VUZP - vuzp${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VZIPd16 (3920) - ARM_INS_VZIP - vzip${p}.16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VZIPd8 (3921) - ARM_INS_VZIP - vzip${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, + CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, + CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VZIPq16 (3922) - ARM_INS_VZIP - vzip${p}.16 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VZIPq32 (3923) - ARM_INS_VZIP - vzip${p}.32 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_VZIPq8 (3924) - ARM_INS_VZIP - vzip${p}.8 $Vd, $Vm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* Vm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, + CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, + CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, + CS_DATA_TYPE_LAST } }, /* src2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_sysLDMDA (3925) - ARM_INS_LDMDA - ldmda${p} $Rn, $regs ^ */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysLDMDA_UPD (3926) - ARM_INS_LDMDA - ldmda${p} $Rn!, $regs ^ */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysLDMDB (3927) - ARM_INS_LDMDB - ldmdb${p} $Rn, $regs ^ */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysLDMDB_UPD (3928) - ARM_INS_LDMDB - ldmdb${p} $Rn!, $regs ^ */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysLDMIA (3929) - ARM_INS_LDM - ldm${p} $Rn, $regs ^ */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysLDMIA_UPD (3930) - ARM_INS_LDM - ldm${p} $Rn!, $regs ^ */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysLDMIB (3931) - ARM_INS_LDMIB - ldmib${p} $Rn, $regs ^ */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysLDMIB_UPD (3932) - ARM_INS_LDMIB - ldmib${p} $Rn!, $regs ^ */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysSTMDA (3933) - ARM_INS_STMDA - stmda${p} $Rn, $regs ^ */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysSTMDA_UPD (3934) - ARM_INS_STMDA - stmda${p} $Rn!, $regs ^ */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysSTMDB (3935) - ARM_INS_STMDB - stmdb${p} $Rn, $regs ^ */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysSTMDB_UPD (3936) - ARM_INS_STMDB - stmdb${p} $Rn!, $regs ^ */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysSTMIA (3937) - ARM_INS_STM - stm${p} $Rn, $regs ^ */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysSTMIA_UPD (3938) - ARM_INS_STM - stm${p} $Rn!, $regs ^ */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysSTMIB (3939) - ARM_INS_STMIB - stmib${p} $Rn, $regs ^ */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_sysSTMIB_UPD (3940) - ARM_INS_STMIB - stmib${p} $Rn!, $regs ^ */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_t2ADCri (3941) - ARM_INS_ADC - adc${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ADCrr (3942) - ARM_INS_ADC - adc${s}${p}.w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ADCrs (3943) - ARM_INS_ADC - adc${s}${p}.w $Rd, $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ADDri (3944) - ARM_INS_ADD - add${s}${p}.w $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ADDri12 (3945) - ARM_INS_ADDW - addw${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2ADDrr (3946) - ARM_INS_ADD - add${s}${p}.w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ADDrs (3947) - ARM_INS_ADD - add${s}${p}.w $Rd, $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ADDspImm (3948) - ARM_INS_ADD - add${s}${p}.w $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ADDspImm12 (3949) - ARM_INS_ADDW - addw${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2ADR (3950) - ARM_INS_ADR - adr{$p}.w $Rd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2ANDri (3951) - ARM_INS_AND - and${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ANDrr (3952) - ARM_INS_AND - and${s}${p}.w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ANDrs (3953) - ARM_INS_AND - and${s}${p}.w $Rd, $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ASRri (3954) - ARM_INS_ASR - asr${s}${p}.w $Rd, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ASRrr (3955) - ARM_INS_ASR - asr${s}${p}.w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2AUT (3956) - ARM_INS_AUT - aut r12, lr, sp */ + { { 0 } } + }, + { /* ARM_t2AUTG (3957) - ARM_INS_AUTG - autg${p} $Ra, $Rn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_t2B (3958) - ARM_INS_B - b${p}.w $target */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2BFC (3959) - ARM_INS_BFC - bfc${p} $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2BFI (3960) - ARM_INS_BFI - bfi${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2BFLi (3961) - ARM_INS_BFL - bfl${p} $b_label, $label */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* b_label */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2BFLr (3962) - ARM_INS_BFLX - bflx${p} $b_label, $Rn */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* b_label */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2BFi (3963) - ARM_INS_BF - bf${p} $b_label, $label */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* b_label */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2BFic (3964) - ARM_INS_BFCSEL - bfcsel $b_label, $label, $ba_label, $bcond */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* b_label */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* ba_label */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bcond */ + { 0 } } + }, + { /* ARM_t2BFr (3965) - ARM_INS_BFX - bfx${p} $b_label, $Rn */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* b_label */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2BICri (3966) - ARM_INS_BIC - bic${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2BICrr (3967) - ARM_INS_BIC - bic${s}${p}.w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2BICrs (3968) - ARM_INS_BIC - bic${s}${p}.w $Rd, $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2BTI (3969) - ARM_INS_BTI - bti */ + { { 0 } } + }, + { /* ARM_t2BXAUT (3970) - ARM_INS_BXAUT - bxaut${p} $Ra, $Rn, $Rm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_t2BXJ (3971) - ARM_INS_BXJ - bxj${p} $func */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2Bcc (3972) - ARM_INS_B - b${p}.w $target */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2CDP (3973) - ARM_INS_CDP - cdp${p} $cop, $opc1, $CRd, $CRn, $CRm, $opc2 */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2CDP2 (3974) - ARM_INS_CDP2 - cdp2${p} $cop, $opc1, $CRd, $CRn, $CRm, $opc2 */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2CLREX (3975) - ARM_INS_CLREX - clrex${p} */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2CLRM (3976) - ARM_INS_CLRM - clrm${p} $regs */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_t2CLZ (3977) - ARM_INS_CLZ - clz${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2CMNri (3978) - ARM_INS_CMN - cmn${p}.w $Rn, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2CMNzrr (3979) - ARM_INS_CMN - cmn${p}.w $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2CMNzrs (3980) - ARM_INS_CMN - cmn${p}.w $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2CMPri (3981) - ARM_INS_CMP - cmp${p}.w $Rn, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2CMPrr (3982) - ARM_INS_CMP - cmp${p}.w $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2CMPrs (3983) - ARM_INS_CMP - cmp${p}.w $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2CPS1p (3984) - ARM_INS_CPS - cps $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { 0 } } + }, + { /* ARM_t2CPS2p (3985) - ARM_INS_CPS - cps$imod.w $iflags */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imod */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* iflags */ + { 0 } } + }, + { /* ARM_t2CPS3p (3986) - ARM_INS_CPS - cps$imod $iflags, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imod */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* iflags */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { 0 } } + }, + { /* ARM_t2CRC32B (3987) - ARM_INS_CRC32B - crc32b $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_t2CRC32CB (3988) - ARM_INS_CRC32CB - crc32cb $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_t2CRC32CH (3989) - ARM_INS_CRC32CH - crc32ch $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_t2CRC32CW (3990) - ARM_INS_CRC32CW - crc32cw $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_t2CRC32H (3991) - ARM_INS_CRC32H - crc32h $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_t2CRC32W (3992) - ARM_INS_CRC32W - crc32w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_t2CSEL (3993) - ARM_INS_CSEL - csel $Rd, $Rn, $Rm, $fcond */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcond */ + { 0 } } + }, + { /* ARM_t2CSINC (3994) - ARM_INS_CSINC - csinc $Rd, $Rn, $Rm, $fcond */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcond */ + { 0 } } + }, + { /* ARM_t2CSINV (3995) - ARM_INS_CSINV - csinv $Rd, $Rn, $Rm, $fcond */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcond */ + { 0 } } + }, + { /* ARM_t2CSNEG (3996) - ARM_INS_CSNEG - csneg $Rd, $Rn, $Rm, $fcond */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcond */ + { 0 } } + }, + { /* ARM_t2DBG (3997) - ARM_INS_DBG - dbg${p} $opt */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2DCPS1 (3998) - ARM_INS_DCPS1 - dcps1${p} */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2DCPS2 (3999) - ARM_INS_DCPS2 - dcps2${p} */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2DCPS3 (4000) - ARM_INS_DCPS3 - dcps3${p} */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2DLS (4001) - ARM_INS_DLS - dls $LR, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { 0 } } + }, + { /* ARM_t2DMB (4002) - ARM_INS_DMB - dmb${p} $opt */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2DSB (4003) - ARM_INS_DSB - dsb${p} $opt */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2EORri (4004) - ARM_INS_EOR - eor${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2EORrr (4005) - ARM_INS_EOR - eor${s}${p}.w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2EORrs (4006) - ARM_INS_EOR - eor${s}${p}.w $Rd, $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2HINT (4007) - ARM_INS_HINT - hint${p}.w $imm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2HVC (4008) - ARM_INS_HVC - hvc.w $imm16 */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } } + }, + { /* ARM_t2ISB (4009) - ARM_INS_ISB - isb${p} $opt */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2IT (4010) - ARM_INS_IT - it$mask $cc */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { 0 } } + }, + { { { /* ARM_t2Int_eh_sjlj_setjmp (4011) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_t2Int_eh_sjlj_setjmp_nofp (4012) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_t2LDA (4013) - ARM_INS_LDA - lda${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDAB (4014) - ARM_INS_LDAB - ldab${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDAEX (4015) - ARM_INS_LDAEX - ldaex${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDAEXB (4016) - ARM_INS_LDAEXB - ldaexb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDAEXD (4017) - ARM_INS_LDAEXD - ldaexd${p} $Rt, $Rt2, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDAEXH (4018) - ARM_INS_LDAEXH - ldaexh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDAH (4019) - ARM_INS_LDAH - ldah${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDC2L_OFFSET (4020) - ARM_INS_LDC2L - ldc2l${p} $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDC2L_OPTION (4021) - ARM_INS_LDC2L - ldc2l${p} $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDC2L_POST (4022) - ARM_INS_LDC2L - ldc2l${p} $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDC2L_PRE (4023) - ARM_INS_LDC2L - ldc2l${p} $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDC2_OFFSET (4024) - ARM_INS_LDC2 - ldc2${p} $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDC2_OPTION (4025) - ARM_INS_LDC2 - ldc2${p} $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDC2_POST (4026) - ARM_INS_LDC2 - ldc2${p} $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDC2_PRE (4027) - ARM_INS_LDC2 - ldc2${p} $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDCL_OFFSET (4028) - ARM_INS_LDCL - ldcl${p} $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDCL_OPTION (4029) - ARM_INS_LDCL - ldcl${p} $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDCL_POST (4030) - ARM_INS_LDCL - ldcl${p} $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDCL_PRE (4031) - ARM_INS_LDCL - ldcl${p} $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDC_OFFSET (4032) - ARM_INS_LDC - ldc${p} $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDC_OPTION (4033) - ARM_INS_LDC - ldc${p} $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDC_POST (4034) - ARM_INS_LDC - ldc${p} $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDC_PRE (4035) - ARM_INS_LDC - ldc${p} $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDMDB (4036) - ARM_INS_LDMDB - ldmdb${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_t2LDMDB_UPD (4037) - ARM_INS_LDMDB - ldmdb${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_t2LDMIA (4038) - ARM_INS_LDM - ldm${p}.w $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_t2LDMIA_UPD (4039) - ARM_INS_LDM - ldm${p}.w $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_t2LDRBT (4040) - ARM_INS_LDRBT - ldrbt${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRB_POST (4041) - ARM_INS_LDRB - ldrb${p} $Rt, $Rn$offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRB_PRE (4042) - ARM_INS_LDRB - ldrb${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRBi12 (4043) - ARM_INS_LDRB - ldrb${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRBi8 (4044) - ARM_INS_LDRB - ldrb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRBpci (4045) - ARM_INS_LDRB - ldrb${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRBs (4046) - ARM_INS_LDRB - ldrb${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRD_POST (4047) - ARM_INS_LDRD - ldrd${p} $Rt, $Rt2, $addr$imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRD_PRE (4048) - ARM_INS_LDRD - ldrd${p} $Rt, $Rt2, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRDi8 (4049) - ARM_INS_LDRD - ldrd${p} $Rt, $Rt2, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDREX (4050) - ARM_INS_LDREX - ldrex${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDREXB (4051) - ARM_INS_LDREXB - ldrexb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDREXD (4052) - ARM_INS_LDREXD - ldrexd${p} $Rt, $Rt2, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDREXH (4053) - ARM_INS_LDREXH - ldrexh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRHT (4054) - ARM_INS_LDRHT - ldrht${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRH_POST (4055) - ARM_INS_LDRH - ldrh${p} $Rt, $Rn$offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRH_PRE (4056) - ARM_INS_LDRH - ldrh${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRHi12 (4057) - ARM_INS_LDRH - ldrh${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRHi8 (4058) - ARM_INS_LDRH - ldrh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRHpci (4059) - ARM_INS_LDRH - ldrh${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRHs (4060) - ARM_INS_LDRH - ldrh${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSBT (4061) - ARM_INS_LDRSBT - ldrsbt${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSB_POST (4062) - ARM_INS_LDRSB - ldrsb${p} $Rt, $Rn$offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSB_PRE (4063) - ARM_INS_LDRSB - ldrsb${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSBi12 (4064) - ARM_INS_LDRSB - ldrsb${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSBi8 (4065) - ARM_INS_LDRSB - ldrsb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSBpci (4066) - ARM_INS_LDRSB - ldrsb${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSBs (4067) - ARM_INS_LDRSB - ldrsb${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSHT (4068) - ARM_INS_LDRSHT - ldrsht${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSH_POST (4069) - ARM_INS_LDRSH - ldrsh${p} $Rt, $Rn$offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSH_PRE (4070) - ARM_INS_LDRSH - ldrsh${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSHi12 (4071) - ARM_INS_LDRSH - ldrsh${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSHi8 (4072) - ARM_INS_LDRSH - ldrsh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSHpci (4073) - ARM_INS_LDRSH - ldrsh${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRSHs (4074) - ARM_INS_LDRSH - ldrsh${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRT (4075) - ARM_INS_LDRT - ldrt${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDR_POST (4076) - ARM_INS_LDR - ldr${p} $Rt, $Rn$offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDR_PRE (4077) - ARM_INS_LDR - ldr${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRi12 (4078) - ARM_INS_LDR - ldr${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRi8 (4079) - ARM_INS_LDR - ldr${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRpci (4080) - ARM_INS_LDR - ldr${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LDRs (4081) - ARM_INS_LDR - ldr${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_INVALID, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2LE (4082) - ARM_INS_LE - le $label */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */ + { 0 } } + }, + { /* ARM_t2LEUpdate (4083) - ARM_INS_LE - le $LRin, $label */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LRout */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LRin */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */ + { 0 } } + }, + { /* ARM_t2LSLri (4084) - ARM_INS_LSL - lsl${s}${p}.w $Rd, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2LSLrr (4085) - ARM_INS_LSL - lsl${s}${p}.w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2LSRri (4086) - ARM_INS_LSR - lsr${s}${p}.w $Rd, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2LSRrr (4087) - ARM_INS_LSR - lsr${s}${p}.w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2MCR (4088) - ARM_INS_MCR - mcr${p} $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MCR2 (4089) - ARM_INS_MCR2 - mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MCRR (4090) - ARM_INS_MCRR - mcrr${p} $cop, $opc1, $Rt, $Rt2, $CRm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MCRR2 (4091) - ARM_INS_MCRR2 - mcrr2${p} $cop, $opc1, $Rt, $Rt2, $CRm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MLA (4092) - ARM_INS_MLA - mla${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MLS (4093) - ARM_INS_MLS - mls${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MOVTi16 (4094) - ARM_INS_MOVT - movt${p} $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MOVi (4095) - ARM_INS_MOV - mov${s}${p}.w $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2MOVi16 (4096) - ARM_INS_MOVW - movw${p} $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MOVr (4097) - ARM_INS_MOV - mov${s}${p}.w $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { { { /* ARM_t2MOVsra_flag (4098) - ARM_INS_INVALID - asrs${p}.w $Rd, $Rm, #1 */ + 0 } } }, + { { { /* ARM_t2MOVsrl_flag (4099) - ARM_INS_INVALID - lsrs${p}.w $Rd, $Rm, #1 */ + 0 } } }, + { /* ARM_t2MRC (4100) - ARM_INS_MRC - mrc${p} $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MRC2 (4101) - ARM_INS_MRC2 - mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm, $opc2 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MRRC (4102) - ARM_INS_MRRC - mrrc${p} $cop, $opc1, $Rt, $Rt2, $CRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MRRC2 (4103) - ARM_INS_MRRC2 - mrrc2${p} $cop, $opc1, $Rt, $Rt2, $CRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MRS_AR (4104) - ARM_INS_MRS - mrs${p} $Rd, apsr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MRS_M (4105) - ARM_INS_MRS - mrs${p} $Rd, $SYSm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SYSm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MRSbanked (4106) - ARM_INS_MRS - mrs${p} $Rd, $banked */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* banked */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MRSsys_AR (4107) - ARM_INS_MRS - mrs${p} $Rd, spsr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MSR_AR (4108) - ARM_INS_MSR - msr${p} $mask, $Rn */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MSR_M (4109) - ARM_INS_MSR - msr${p} $SYSm, $Rn */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SYSm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MSRbanked (4110) - ARM_INS_MSR - msr${p} $banked, $Rn */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* banked */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MUL (4111) - ARM_INS_MUL - mul${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2MVNi (4112) - ARM_INS_MVN - mvn${s}${p} $Rd, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2MVNr (4113) - ARM_INS_MVN - mvn${s}${p}.w $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2MVNs (4114) - ARM_INS_MVN - mvn${s}${p}.w $Rd, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ORNri (4115) - ARM_INS_ORN - orn${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ORNrr (4116) - ARM_INS_ORN - orn${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ORNrs (4117) - ARM_INS_ORN - orn${s}${p} $Rd, $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ORRri (4118) - ARM_INS_ORR - orr${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ORRrr (4119) - ARM_INS_ORR - orr${s}${p}.w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2ORRrs (4120) - ARM_INS_ORR - orr${s}${p}.w $Rd, $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2PAC (4121) - ARM_INS_PAC - pac r12, lr, sp */ + { { 0 } } + }, + { /* ARM_t2PACBTI (4122) - ARM_INS_PACBTI - pacbti r12, lr, sp */ + { { 0 } } + }, + { /* ARM_t2PACG (4123) - ARM_INS_PACG - pacg${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_t2PKHBT (4124) - ARM_INS_PKHBT - pkhbt${p} $Rd, $Rn, $Rm$sh */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2PKHTB (4125) - ARM_INS_PKHTB - pkhtb${p} $Rd, $Rn, $Rm$sh */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2PLDWi12 (4126) - ARM_INS_PLDW - pldw${p} $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2PLDWi8 (4127) - ARM_INS_PLDW - pldw${p} $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2PLDWs (4128) - ARM_INS_PLDW - pldw${p} $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2PLDi12 (4129) - ARM_INS_PLD - pld${p} $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2PLDi8 (4130) - ARM_INS_PLD - pld${p} $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2PLDpci (4131) - ARM_INS_PLD - pld${p} $addr */ + { { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2PLDs (4132) - ARM_INS_PLD - pld${p} $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2PLIi12 (4133) - ARM_INS_PLI - pli${p} $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2PLIi8 (4134) - ARM_INS_PLI - pli${p} $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2PLIpci (4135) - ARM_INS_PLI - pli${p} $addr */ + { { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2PLIs (4136) - ARM_INS_PLI - pli${p} $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2QADD (4137) - ARM_INS_QADD - qadd${p} $Rd, $Rm, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2QADD16 (4138) - ARM_INS_QADD16 - qadd16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2QADD8 (4139) - ARM_INS_QADD8 - qadd8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2QASX (4140) - ARM_INS_QASX - qasx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2QDADD (4141) - ARM_INS_QDADD - qdadd${p} $Rd, $Rm, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2QDSUB (4142) - ARM_INS_QDSUB - qdsub${p} $Rd, $Rm, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2QSAX (4143) - ARM_INS_QSAX - qsax${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2QSUB (4144) - ARM_INS_QSUB - qsub${p} $Rd, $Rm, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2QSUB16 (4145) - ARM_INS_QSUB16 - qsub16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2QSUB8 (4146) - ARM_INS_QSUB8 - qsub8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2RBIT (4147) - ARM_INS_RBIT - rbit${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2REV (4148) - ARM_INS_REV - rev${p}.w $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2REV16 (4149) - ARM_INS_REV16 - rev16${p}.w $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2REVSH (4150) - ARM_INS_REVSH - revsh${p}.w $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2RFEDB (4151) - ARM_INS_RFEDB - rfedb${p} $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2RFEDBW (4152) - ARM_INS_RFEDB - rfedb${p} $Rn! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2RFEIA (4153) - ARM_INS_RFEIA - rfeia${p} $Rn */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2RFEIAW (4154) - ARM_INS_RFEIA - rfeia${p} $Rn! */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2RORri (4155) - ARM_INS_ROR - ror${s}${p}.w $Rd, $Rm, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2RORrr (4156) - ARM_INS_ROR - ror${s}${p}.w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2RRX (4157) - ARM_INS_RRX - rrx${s}${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2RSBri (4158) - ARM_INS_RSB - rsb${s}${p}.w $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2RSBrr (4159) - ARM_INS_RSB - rsb${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2RSBrs (4160) - ARM_INS_RSB - rsb${s}${p} $Rd, $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2SADD16 (4161) - ARM_INS_SADD16 - sadd16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SADD8 (4162) - ARM_INS_SADD8 - sadd8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SASX (4163) - ARM_INS_SASX - sasx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SB (4164) - ARM_INS_SB - sb */ + { { 0 } } + }, + { /* ARM_t2SBCri (4165) - ARM_INS_SBC - sbc${s}${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2SBCrr (4166) - ARM_INS_SBC - sbc${s}${p}.w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2SBCrs (4167) - ARM_INS_SBC - sbc${s}${p}.w $Rd, $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2SBFX (4168) - ARM_INS_SBFX - sbfx${p} $Rd, $Rn, $lsb, $msb */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lsb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* msb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SDIV (4169) - ARM_INS_SDIV - sdiv${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SEL (4170) - ARM_INS_SEL - sel${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SETPAN (4171) - ARM_INS_SETPAN - setpan $imm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } } + }, + { /* ARM_t2SG (4172) - ARM_INS_SG - sg${p} */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SHADD16 (4173) - ARM_INS_SHADD16 - shadd16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SHADD8 (4174) - ARM_INS_SHADD8 - shadd8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SHASX (4175) - ARM_INS_SHASX - shasx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SHSAX (4176) - ARM_INS_SHSAX - shsax${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SHSUB16 (4177) - ARM_INS_SHSUB16 - shsub16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SHSUB8 (4178) - ARM_INS_SHSUB8 - shsub8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMC (4179) - ARM_INS_SMC - smc${p} $opt */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLABB (4180) - ARM_INS_SMLABB - smlabb${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLABT (4181) - ARM_INS_SMLABT - smlabt${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLAD (4182) - ARM_INS_SMLAD - smlad${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLADX (4183) - ARM_INS_SMLADX - smladx${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLAL (4184) - ARM_INS_SMLAL - smlal${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLALBB (4185) - ARM_INS_SMLALBB - smlalbb${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLALBT (4186) - ARM_INS_SMLALBT - smlalbt${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLALD (4187) - ARM_INS_SMLALD - smlald${p} $Ra, $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLALDX (4188) - ARM_INS_SMLALDX - smlaldx${p} $Ra, $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLALTB (4189) - ARM_INS_SMLALTB - smlaltb${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLALTT (4190) - ARM_INS_SMLALTT - smlaltt${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLATB (4191) - ARM_INS_SMLATB - smlatb${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLATT (4192) - ARM_INS_SMLATT - smlatt${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLAWB (4193) - ARM_INS_SMLAWB - smlawb${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLAWT (4194) - ARM_INS_SMLAWT - smlawt${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLSD (4195) - ARM_INS_SMLSD - smlsd${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLSDX (4196) - ARM_INS_SMLSDX - smlsdx${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLSLD (4197) - ARM_INS_SMLSLD - smlsld${p} $Ra, $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMLSLDX (4198) - ARM_INS_SMLSLDX - smlsldx${p} $Ra, $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMMLA (4199) - ARM_INS_SMMLA - smmla${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMMLAR (4200) - ARM_INS_SMMLAR - smmlar${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMMLS (4201) - ARM_INS_SMMLS - smmls${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMMLSR (4202) - ARM_INS_SMMLSR - smmlsr${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMMUL (4203) - ARM_INS_SMMUL - smmul${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMMULR (4204) - ARM_INS_SMMULR - smmulr${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMUAD (4205) - ARM_INS_SMUAD - smuad${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMUADX (4206) - ARM_INS_SMUADX - smuadx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMULBB (4207) - ARM_INS_SMULBB - smulbb${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMULBT (4208) - ARM_INS_SMULBT - smulbt${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMULL (4209) - ARM_INS_SMULL - smull${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMULTB (4210) - ARM_INS_SMULTB - smultb${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMULTT (4211) - ARM_INS_SMULTT - smultt${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMULWB (4212) - ARM_INS_SMULWB - smulwb${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMULWT (4213) - ARM_INS_SMULWT - smulwt${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMUSD (4214) - ARM_INS_SMUSD - smusd${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SMUSDX (4215) - ARM_INS_SMUSDX - smusdx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SRSDB (4216) - ARM_INS_SRSDB - srsdb${p} sp, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SRSDB_UPD (4217) - ARM_INS_SRSDB - srsdb${p} sp!, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SRSIA (4218) - ARM_INS_SRSIA - srsia${p} sp, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SRSIA_UPD (4219) - ARM_INS_SRSIA - srsia${p} sp!, $mode */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SSAT (4220) - ARM_INS_SSAT - ssat${p} $Rd, $sat_imm, $Rn$sh */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SSAT16 (4221) - ARM_INS_SSAT16 - ssat16${p} $Rd, $sat_imm, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SSAX (4222) - ARM_INS_SSAX - ssax${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SSUB16 (4223) - ARM_INS_SSUB16 - ssub16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SSUB8 (4224) - ARM_INS_SSUB8 - ssub8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STC2L_OFFSET (4225) - ARM_INS_STC2L - stc2l${p} $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STC2L_OPTION (4226) - ARM_INS_STC2L - stc2l${p} $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STC2L_POST (4227) - ARM_INS_STC2L - stc2l${p} $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STC2L_PRE (4228) - ARM_INS_STC2L - stc2l${p} $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STC2_OFFSET (4229) - ARM_INS_STC2 - stc2${p} $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STC2_OPTION (4230) - ARM_INS_STC2 - stc2${p} $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STC2_POST (4231) - ARM_INS_STC2 - stc2${p} $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STC2_PRE (4232) - ARM_INS_STC2 - stc2${p} $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STCL_OFFSET (4233) - ARM_INS_STCL - stcl${p} $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STCL_OPTION (4234) - ARM_INS_STCL - stcl${p} $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STCL_POST (4235) - ARM_INS_STCL - stcl${p} $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STCL_PRE (4236) - ARM_INS_STCL - stcl${p} $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STC_OFFSET (4237) - ARM_INS_STC - stc${p} $cop, $CRd, $addr */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STC_OPTION (4238) - ARM_INS_STC - stc${p} $cop, $CRd, $addr, $option */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STC_POST (4239) - ARM_INS_STC - stc${p} $cop, $CRd, $addr, $offset */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STC_PRE (4240) - ARM_INS_STC - stc${p} $cop, $CRd, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STL (4241) - ARM_INS_STL - stl${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STLB (4242) - ARM_INS_STLB - stlb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STLEX (4243) - ARM_INS_STLEX - stlex${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STLEXB (4244) - ARM_INS_STLEXB - stlexb${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STLEXD (4245) - ARM_INS_STLEXD - stlexd${p} $Rd, $Rt, $Rt2, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STLEXH (4246) - ARM_INS_STLEXH - stlexh${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STLH (4247) - ARM_INS_STLH - stlh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STMDB (4248) - ARM_INS_STMDB - stmdb${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_t2STMDB_UPD (4249) - ARM_INS_STMDB - stmdb${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_t2STMIA (4250) - ARM_INS_STM - stm${p}.w $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_t2STMIA_UPD (4251) - ARM_INS_STM - stm${p}.w $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_t2STRBT (4252) - ARM_INS_STRBT - strbt${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRB_POST (4253) - ARM_INS_STRB - strb${p} $Rt, $Rn$offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRB_PRE (4254) - ARM_INS_STRB - strb${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRBi12 (4255) - ARM_INS_STRB - strb${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRBi8 (4256) - ARM_INS_STRB - strb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRBs (4257) - ARM_INS_STRB - strb${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRD_POST (4258) - ARM_INS_STRD - strd${p} $Rt, $Rt2, $addr$imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRD_PRE (4259) - ARM_INS_STRD - strd${p} $Rt, $Rt2, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRDi8 (4260) - ARM_INS_STRD - strd${p} $Rt, $Rt2, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STREX (4261) - ARM_INS_STREX - strex${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STREXB (4262) - ARM_INS_STREXB - strexb${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STREXD (4263) - ARM_INS_STREXD - strexd${p} $Rd, $Rt, $Rt2, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STREXH (4264) - ARM_INS_STREXH - strexh${p} $Rd, $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRHT (4265) - ARM_INS_STRHT - strht${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRH_POST (4266) - ARM_INS_STRH - strh${p} $Rt, $Rn$offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRH_PRE (4267) - ARM_INS_STRH - strh${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRHi12 (4268) - ARM_INS_STRH - strh${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRHi8 (4269) - ARM_INS_STRH - strh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRHs (4270) - ARM_INS_STRH - strh${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRT (4271) - ARM_INS_STRT - strt${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STR_POST (4272) - ARM_INS_STR - str${p} $Rt, $Rn$offset */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STR_PRE (4273) - ARM_INS_STR - str${p} $Rt, $addr! */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRi12 (4274) - ARM_INS_STR - str${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRi8 (4275) - ARM_INS_STR - str${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2STRs (4276) - ARM_INS_STR - str${p}.w $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SUBS_PC_LR (4277) - ARM_INS_SUBS - subs${p} pc, lr, $imm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SUBri (4278) - ARM_INS_SUB - sub${s}${p}.w $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2SUBri12 (4279) - ARM_INS_SUBW - subw${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SUBrr (4280) - ARM_INS_SUB - sub${s}${p}.w $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2SUBrs (4281) - ARM_INS_SUB - sub${s}${p}.w $Rd, $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2SUBspImm (4282) - ARM_INS_SUB - sub${s}${p}.w $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { 0 } } + }, + { /* ARM_t2SUBspImm12 (4283) - ARM_INS_SUBW - subw${p} $Rd, $Rn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SXTAB (4284) - ARM_INS_SXTAB - sxtab${p} $Rd, $Rn, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SXTAB16 (4285) - ARM_INS_SXTAB16 - sxtab16${p} $Rd, $Rn, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SXTAH (4286) - ARM_INS_SXTAH - sxtah${p} $Rd, $Rn, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SXTB (4287) - ARM_INS_SXTB - sxtb${p}.w $Rd, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SXTB16 (4288) - ARM_INS_SXTB16 - sxtb16${p} $Rd, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2SXTH (4289) - ARM_INS_SXTH - sxth${p}.w $Rd, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TBB (4290) - ARM_INS_TBB - tbb${p} $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TBH (4291) - ARM_INS_TBH - tbh${p} $addr */ + { { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TEQri (4292) - ARM_INS_TEQ - teq${p}.w $Rn, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TEQrr (4293) - ARM_INS_TEQ - teq${p}.w $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TEQrs (4294) - ARM_INS_TEQ - teq${p}.w $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TSB (4295) - ARM_INS_TSB - tsb${p} $opt */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TSTri (4296) - ARM_INS_TST - tst${p}.w $Rn, $imm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TSTrr (4297) - ARM_INS_TST - tst${p}.w $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TSTrs (4298) - ARM_INS_TST - tst${p}.w $Rn, $ShiftedRm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TT (4299) - ARM_INS_TT - tt${p} $Rt, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TTA (4300) - ARM_INS_TTA - tta${p} $Rt, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TTAT (4301) - ARM_INS_TTAT - ttat${p} $Rt, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2TTT (4302) - ARM_INS_TTT - ttt${p} $Rt, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UADD16 (4303) - ARM_INS_UADD16 - uadd16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UADD8 (4304) - ARM_INS_UADD8 - uadd8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UASX (4305) - ARM_INS_UASX - uasx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UBFX (4306) - ARM_INS_UBFX - ubfx${p} $Rd, $Rn, $lsb, $msb */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lsb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* msb */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UDF (4307) - ARM_INS_UDF - udf.w $imm16 */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } } + }, + { /* ARM_t2UDIV (4308) - ARM_INS_UDIV - udiv${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UHADD16 (4309) - ARM_INS_UHADD16 - uhadd16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UHADD8 (4310) - ARM_INS_UHADD8 - uhadd8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UHASX (4311) - ARM_INS_UHASX - uhasx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UHSAX (4312) - ARM_INS_UHSAX - uhsax${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UHSUB16 (4313) - ARM_INS_UHSUB16 - uhsub16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UHSUB8 (4314) - ARM_INS_UHSUB8 - uhsub8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UMAAL (4315) - ARM_INS_UMAAL - umaal${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UMLAL (4316) - ARM_INS_UMLAL - umlal${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UMULL (4317) - ARM_INS_UMULL - umull${p} $RdLo, $RdHi, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UQADD16 (4318) - ARM_INS_UQADD16 - uqadd16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UQADD8 (4319) - ARM_INS_UQADD8 - uqadd8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UQASX (4320) - ARM_INS_UQASX - uqasx${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UQSAX (4321) - ARM_INS_UQSAX - uqsax${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UQSUB16 (4322) - ARM_INS_UQSUB16 - uqsub16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UQSUB8 (4323) - ARM_INS_UQSUB8 - uqsub8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2USAD8 (4324) - ARM_INS_USAD8 - usad8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2USADA8 (4325) - ARM_INS_USADA8 - usada8${p} $Rd, $Rn, $Rm, $Ra */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2USAT (4326) - ARM_INS_USAT - usat${p} $Rd, $sat_imm, $Rn$sh */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2USAT16 (4327) - ARM_INS_USAT16 - usat16${p} $Rd, $sat_imm, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2USAX (4328) - ARM_INS_USAX - usax${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2USUB16 (4329) - ARM_INS_USUB16 - usub16${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2USUB8 (4330) - ARM_INS_USUB8 - usub8${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UXTAB (4331) - ARM_INS_UXTAB - uxtab${p} $Rd, $Rn, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UXTAB16 (4332) - ARM_INS_UXTAB16 - uxtab16${p} $Rd, $Rn, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UXTAH (4333) - ARM_INS_UXTAH - uxtah${p} $Rd, $Rn, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UXTB (4334) - ARM_INS_UXTB - uxtb${p}.w $Rd, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UXTB16 (4335) - ARM_INS_UXTB16 - uxtb16${p} $Rd, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2UXTH (4336) - ARM_INS_UXTH - uxth${p}.w $Rd, $Rm$rot */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t2WLS (4337) - ARM_INS_WLS - wls $LR, $Rn, $label */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */ + { 0 } } + }, + { /* ARM_tADC (4338) - ARM_INS_ADC - adc${s}${p} $Rdn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tADDhirr (4339) - ARM_INS_ADD - add${p} $Rdn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tADDi3 (4340) - ARM_INS_ADD - add${s}${p} $Rd, $Rm, $imm3 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tADDi8 (4341) - ARM_INS_ADD - add${s}${p} $Rdn, $imm8 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tADDrSP (4342) - ARM_INS_ADD - add${p} $Rdn, $sp, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sp */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tADDrSPi (4343) - ARM_INS_ADD - add${p} $dst, $sp, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sp */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tADDrr (4344) - ARM_INS_ADD - add${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tADDspi (4345) - ARM_INS_ADD - add${p} $Rdn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tADDspr (4346) - ARM_INS_ADD - add${p} $Rdn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tADR (4347) - ARM_INS_ADR - adr{$p} $Rd, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tAND (4348) - ARM_INS_AND - and${s}${p} $Rdn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tASRri (4349) - ARM_INS_ASR - asr${s}${p} $Rd, $Rm, $imm5 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm5 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tASRrr (4350) - ARM_INS_ASR - asr${s}${p} $Rdn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tB (4351) - ARM_INS_B - b${p} $target */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tBIC (4352) - ARM_INS_BIC - bic${s}${p} $Rdn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tBKPT (4353) - ARM_INS_BKPT - bkpt $val */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { 0 } } + }, + { /* ARM_tBL (4354) - ARM_INS_BL - bl${p} $func */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */ + { 0 } } + }, + { /* ARM_tBLXNSr (4355) - ARM_INS_BLXNS - blxns${p} $func */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */ + { 0 } } + }, + { /* ARM_tBLXi (4356) - ARM_INS_BLX - blx${p} $func */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */ + { 0 } } + }, + { /* ARM_tBLXr (4357) - ARM_INS_BLX - blx${p} $func */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */ + { 0 } } + }, + { /* ARM_tBX (4358) - ARM_INS_BX - bx${p} $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tBXNS (4359) - ARM_INS_BXNS - bxns${p} $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tBcc (4360) - ARM_INS_B - b${p} $target */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tCBNZ (4361) - ARM_INS_CBNZ - cbnz $Rn, $target */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } } + }, + { /* ARM_tCBZ (4362) - ARM_INS_CBZ - cbz $Rn, $target */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } } + }, + { /* ARM_tCMNz (4363) - ARM_INS_CMN - cmn${p} $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tCMPhir (4364) - ARM_INS_CMP - cmp${p} $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tCMPi8 (4365) - ARM_INS_CMP - cmp${p} $Rn, $imm8 */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tCMPr (4366) - ARM_INS_CMP - cmp${p} $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tCPS (4367) - ARM_INS_CPS - cps$imod $iflags */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imod */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* iflags */ + { 0 } } + }, + { /* ARM_tEOR (4368) - ARM_INS_EOR - eor${s}${p} $Rdn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tHINT (4369) - ARM_INS_HINT - hint${p} $imm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tHLT (4370) - ARM_INS_HLT - hlt $val */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { 0 } } + }, + { { { /* ARM_tInt_WIN_eh_sjlj_longjmp (4371) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tInt_eh_sjlj_longjmp (4372) - ARM_INS_INVALID - */ + 0 } } }, + { { { /* ARM_tInt_eh_sjlj_setjmp (4373) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_tLDMIA (4374) - ARM_INS_LDM - ldm${p} $Rn, $regs */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_tLDRBi (4375) - ARM_INS_LDRB - ldrb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLDRBr (4376) - ARM_INS_LDRB - ldrb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLDRHi (4377) - ARM_INS_LDRH - ldrh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLDRHr (4378) - ARM_INS_LDRH - ldrh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLDRSB (4379) - ARM_INS_LDRSB - ldrsb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLDRSH (4380) - ARM_INS_LDRSH - ldrsh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLDRi (4381) - ARM_INS_LDR - ldr${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLDRpci (4382) - ARM_INS_LDR - ldr${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLDRr (4383) - ARM_INS_LDR - ldr${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLDRspi (4384) - ARM_INS_LDR - ldr${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLSLri (4385) - ARM_INS_LSL - lsl${s}${p} $Rd, $Rm, $imm5 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm5 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLSLrr (4386) - ARM_INS_LSL - lsl${s}${p} $Rdn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLSRri (4387) - ARM_INS_LSR - lsr${s}${p} $Rd, $Rm, $imm5 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm5 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tLSRrr (4388) - ARM_INS_LSR - lsr${s}${p} $Rdn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tMOVSr (4389) - ARM_INS_MOVS - movs $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { 0 } } + }, + { /* ARM_tMOVi8 (4390) - ARM_INS_MOV - mov${s}${p} $Rd, $imm8 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tMOVr (4391) - ARM_INS_MOV - mov${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tMUL (4392) - ARM_INS_MUL - mul${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tMVN (4393) - ARM_INS_MVN - mvn${s}${p} $Rd, $Rn */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tORR (4394) - ARM_INS_ORR - orr${s}${p} $Rdn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { { { /* ARM_tPICADD (4395) - ARM_INS_INVALID - */ + 0 } } }, + { /* ARM_tPOP (4396) - ARM_INS_POP - pop${p} $regs */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_tPUSH (4397) - ARM_INS_PUSH - push${p} $regs */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_tREV (4398) - ARM_INS_REV - rev${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tREV16 (4399) - ARM_INS_REV16 - rev16${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tREVSH (4400) - ARM_INS_REVSH - revsh${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tROR (4401) - ARM_INS_ROR - ror${s}${p} $Rdn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tRSB (4402) - ARM_INS_RSB - rsb${s}${p} $Rd, $Rn, #0 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSBC (4403) - ARM_INS_SBC - sbc${s}${p} $Rdn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSETEND (4404) - ARM_INS_SETEND - setend $end */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* end */ + { 0 } } + }, + { /* ARM_tSTMIA_UPD (4405) - ARM_INS_STM - stm${p} $Rn!, $regs */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } + }, + { /* ARM_tSTRBi (4406) - ARM_INS_STRB - strb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSTRBr (4407) - ARM_INS_STRB - strb${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSTRHi (4408) - ARM_INS_STRH - strh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSTRHr (4409) - ARM_INS_STRH - strh${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSTRi (4410) - ARM_INS_STR - str${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSTRr (4411) - ARM_INS_STR - str${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_READ | CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSTRspi (4412) - ARM_INS_STR - str${p} $Rt, $addr */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */ + { CS_OP_MEM | CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */ + { CS_OP_MEM | CS_OP_IMM, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSUBi3 (4413) - ARM_INS_SUB - sub${s}${p} $Rd, $Rm, $imm3 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm3 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSUBi8 (4414) - ARM_INS_SUB - sub${s}${p} $Rdn, $imm8 */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSUBrr (4415) - ARM_INS_SUB - sub${s}${p} $Rd, $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSUBspi (4416) - ARM_INS_SUB - sub${p} $Rdn, $imm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSVC (4417) - ARM_INS_SVC - svc${p} $imm */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSXTB (4418) - ARM_INS_SXTB - sxtb${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tSXTH (4419) - ARM_INS_SXTH - sxth${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tTRAP (4420) - ARM_INS_TRAP - trap */ + { { 0 } } + }, + { /* ARM_tTST (4421) - ARM_INS_TST - tst${p} $Rn, $Rm */ + { { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tUDF (4422) - ARM_INS_UDF - udf $imm8 */ + { { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } } + }, + { /* ARM_tUXTB (4423) - ARM_INS_UXTB - uxtb${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_tUXTH (4424) - ARM_INS_UXTH - uxth${p} $Rd, $Rm */ + { { CS_OP_REG, + CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ + { CS_OP_REG, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { 0 } } + }, + { /* ARM_t__brkdiv0 (4425) - ARM_INS___BRKDIV0 - __brkdiv0 */ + { { 0 } } + }, diff --git a/thirdparty/capstone/arch/ARM/ARMGenCSOpGroup.inc b/thirdparty/capstone/arch/ARM/ARMGenCSOpGroup.inc new file mode 100644 index 0000000..12a0ba9 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMGenCSOpGroup.inc @@ -0,0 +1,90 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +ARM_OP_GROUP_RegImmShift = 0, + ARM_OP_GROUP_LdStmModeOperand = 1, + ARM_OP_GROUP_MandatoryInvertedPredicateOperand = 2, + ARM_OP_GROUP_Operand = 3, ARM_OP_GROUP_ModImmOperand = 4, + ARM_OP_GROUP_PredicateOperand = 5, ARM_OP_GROUP_SORegImmOperand = 6, + ARM_OP_GROUP_SORegRegOperand = 7, ARM_OP_GROUP_SBitModifierOperand = 8, + ARM_OP_GROUP_AddrModeImm12Operand_0 = 9, + ARM_OP_GROUP_AddrMode2Operand = 10, ARM_OP_GROUP_CPInstOperand = 11, + ARM_OP_GROUP_MandatoryPredicateOperand = 12, + ARM_OP_GROUP_ThumbITMask = 13, ARM_OP_GROUP_RegisterList = 14, + ARM_OP_GROUP_AddrMode7Operand = 15, ARM_OP_GROUP_GPRPairOperand = 16, + ARM_OP_GROUP_AddrMode3Operand_0 = 17, ARM_OP_GROUP_PCLabel = 18, + ARM_OP_GROUP_AddrModePCOperand = 19, + ARM_OP_GROUP_AddrMode2OffsetOperand = 20, + ARM_OP_GROUP_AddrMode3OffsetOperand = 21, + ARM_OP_GROUP_AddrMode6Operand = 22, + ARM_OP_GROUP_VectorListThreeAllLanes = 23, + ARM_OP_GROUP_VectorListThreeSpacedAllLanes = 24, + ARM_OP_GROUP_VectorListThree = 25, + ARM_OP_GROUP_VectorListThreeSpaced = 26, + ARM_OP_GROUP_VectorListFourAllLanes = 27, + ARM_OP_GROUP_VectorListFourSpacedAllLanes = 28, + ARM_OP_GROUP_VectorListFour = 29, + ARM_OP_GROUP_VectorListFourSpaced = 30, ARM_OP_GROUP_T2SOOperand = 31, + ARM_OP_GROUP_T2AddrModeImm8OffsetOperand = 32, + ARM_OP_GROUP_T2AddrModeImm8Operand_1 = 33, + ARM_OP_GROUP_AdrLabelOperand_0 = 34, ARM_OP_GROUP_VectorIndex = 35, + ARM_OP_GROUP_BitfieldInvMaskImmOperand = 36, + ARM_OP_GROUP_PImmediate = 37, ARM_OP_GROUP_VPTPredicateOperand = 38, + ARM_OP_GROUP_CImmediate = 39, ARM_OP_GROUP_CPSIMod = 40, + ARM_OP_GROUP_CPSIFlag = 41, ARM_OP_GROUP_MemBOption = 42, + ARM_OP_GROUP_FPImmOperand = 43, ARM_OP_GROUP_InstSyncBOption = 44, + ARM_OP_GROUP_AddrMode5Operand_0 = 45, ARM_OP_GROUP_CoprocOptionImm = 46, + ARM_OP_GROUP_PostIdxImm8s4Operand = 47, + ARM_OP_GROUP_AddrMode5Operand_1 = 48, + ARM_OP_GROUP_AddrModeImm12Operand_1 = 49, + ARM_OP_GROUP_AddrMode3Operand_1 = 50, + ARM_OP_GROUP_PostIdxImm8Operand = 51, + ARM_OP_GROUP_PostIdxRegOperand = 52, ARM_OP_GROUP_BankedRegOperand = 53, + ARM_OP_GROUP_MSRMaskOperand = 54, ARM_OP_GROUP_MveSaturateOp = 55, + ARM_OP_GROUP_VMOVModImmOperand = 56, + ARM_OP_GROUP_ComplexRotationOp_180_90 = 57, + ARM_OP_GROUP_ComplexRotationOp_90_0 = 58, + ARM_OP_GROUP_MandatoryRestrictedPredicateOperand = 59, + ARM_OP_GROUP_MVEVectorList_2 = 60, ARM_OP_GROUP_MVEVectorList_4 = 61, + ARM_OP_GROUP_T2AddrModeImm8Operand_0 = 62, + ARM_OP_GROUP_MveAddrModeRQOperand_0 = 63, + ARM_OP_GROUP_MveAddrModeRQOperand_3 = 64, + ARM_OP_GROUP_MveAddrModeRQOperand_1 = 65, + ARM_OP_GROUP_MveAddrModeRQOperand_2 = 66, ARM_OP_GROUP_VPTMask = 67, + ARM_OP_GROUP_PKHLSLShiftImm = 68, ARM_OP_GROUP_PKHASRShiftImm = 69, + ARM_OP_GROUP_ImmPlusOneOperand = 70, ARM_OP_GROUP_SetendOperand = 71, + ARM_OP_GROUP_ShiftImmOperand = 72, ARM_OP_GROUP_RotImmOperand = 73, + ARM_OP_GROUP_TraceSyncBOption = 74, + ARM_OP_GROUP_VectorListOneAllLanes = 75, + ARM_OP_GROUP_VectorListTwoAllLanes = 76, + ARM_OP_GROUP_NoHashImmediate = 77, + ARM_OP_GROUP_AddrMode6OffsetOperand = 78, + ARM_OP_GROUP_VectorListOne = 79, ARM_OP_GROUP_VectorListTwo = 80, + ARM_OP_GROUP_VectorListTwoSpacedAllLanes = 81, + ARM_OP_GROUP_VectorListTwoSpaced = 82, + ARM_OP_GROUP_AddrMode5FP16Operand_0 = 83, + ARM_OP_GROUP_T2AddrModeImm8s4Operand_0 = 84, + ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand = 85, + ARM_OP_GROUP_T2AddrModeImm8s4Operand_1 = 86, ARM_OP_GROUP_FBits16 = 87, + ARM_OP_GROUP_FBits32 = 88, ARM_OP_GROUP_ThumbSRImm = 89, + ARM_OP_GROUP_ThumbLdrLabelOperand = 90, + ARM_OP_GROUP_T2AddrModeSoRegOperand = 91, + ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand = 92, + ARM_OP_GROUP_AddrModeTBB = 93, ARM_OP_GROUP_AddrModeTBH = 94, + ARM_OP_GROUP_ThumbS4ImmOperand = 95, + ARM_OP_GROUP_AdrLabelOperand_2 = 96, + ARM_OP_GROUP_ThumbAddrModeImm5S1Operand = 97, + ARM_OP_GROUP_ThumbAddrModeRROperand = 98, + ARM_OP_GROUP_ThumbAddrModeImm5S2Operand = 99, + ARM_OP_GROUP_ThumbAddrModeImm5S4Operand = 100, + ARM_OP_GROUP_ThumbAddrModeSPOperand = 101, diff --git a/thirdparty/capstone/arch/ARM/ARMGenDisassemblerTables.inc b/thirdparty/capstone/arch/ARM/ARMGenDisassemblerTables.inc new file mode 100644 index 0000000..66c2c4e --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMGenDisassemblerTables.inc @@ -0,0 +1,95237 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#include "../../MCInst.h" +#include "../../LEB128.h" + +// Helper function for extracting fields from encoded instructions. +#define FieldFromInstruction(fname, InsnType) \ + static InsnType fname(InsnType insn, unsigned startBit, \ + unsigned numBits) \ + { \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType) * 8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) \ + << startBit; \ + return (insn & fieldMask) >> startBit; \ + } + +static const uint8_t DecoderTableARM32[] = { + /* 0 */ MCD_OPC_ExtractField, + 25, + 3, // Inst{27-25} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 47, + 14, + 0, // Skip to: 3639 + /* 8 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 110, + 7, + 0, // Skip to: 1918 + /* 16 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 139, + 1, + 0, // Skip to: 419 + /* 24 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 27 */ MCD_OPC_FilterValue, + 0, + 123, + 0, + 0, // Skip to: 155 + /* 32 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 35 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 65 + /* 40 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 56 + /* 45 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 56 + /* 52 */ MCD_OPC_Decode, + 211, + 5, + 0, // Opcode: ANDrr + /* 56 */ MCD_OPC_CheckPredicate, + 0, + 128, + 32, + 0, // Skip to: 8381 + /* 61 */ MCD_OPC_Decode, + 212, + 5, + 1, // Opcode: ANDrsi + /* 65 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 95 + /* 70 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 86 + /* 75 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 86 + /* 82 */ MCD_OPC_Decode, + 160, + 15, + 0, // Opcode: SUBrr + /* 86 */ MCD_OPC_CheckPredicate, + 0, + 98, + 32, + 0, // Skip to: 8381 + /* 91 */ MCD_OPC_Decode, + 161, + 15, + 1, // Opcode: SUBrsi + /* 95 */ MCD_OPC_FilterValue, + 2, + 25, + 0, + 0, // Skip to: 125 + /* 100 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 116 + /* 105 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 116 + /* 112 */ MCD_OPC_Decode, + 202, + 5, + 0, // Opcode: ADDrr + /* 116 */ MCD_OPC_CheckPredicate, + 0, + 68, + 32, + 0, // Skip to: 8381 + /* 121 */ MCD_OPC_Decode, + 203, + 5, + 1, // Opcode: ADDrsi + /* 125 */ MCD_OPC_FilterValue, + 3, + 59, + 32, + 0, // Skip to: 8381 + /* 130 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 146 + /* 135 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 146 + /* 142 */ MCD_OPC_Decode, + 154, + 14, + 0, // Opcode: SBCrr + /* 146 */ MCD_OPC_CheckPredicate, + 0, + 38, + 32, + 0, // Skip to: 8381 + /* 151 */ MCD_OPC_Decode, + 155, + 14, + 1, // Opcode: SBCrsi + /* 155 */ MCD_OPC_FilterValue, + 1, + 29, + 32, + 0, // Skip to: 8381 + /* 160 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 163 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 227 + /* 168 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 171 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 185 + /* 176 */ MCD_OPC_CheckPredicate, + 0, + 8, + 32, + 0, // Skip to: 8381 + /* 181 */ MCD_OPC_Decode, + 213, + 5, + 2, // Opcode: ANDrsr + /* 185 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 199 + /* 190 */ MCD_OPC_CheckPredicate, + 0, + 250, + 31, + 0, // Skip to: 8381 + /* 195 */ MCD_OPC_Decode, + 162, + 15, + 2, // Opcode: SUBrsr + /* 199 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 213 + /* 204 */ MCD_OPC_CheckPredicate, + 0, + 236, + 31, + 0, // Skip to: 8381 + /* 209 */ MCD_OPC_Decode, + 204, + 5, + 2, // Opcode: ADDrsr + /* 213 */ MCD_OPC_FilterValue, + 3, + 227, + 31, + 0, // Skip to: 8381 + /* 218 */ MCD_OPC_CheckPredicate, + 0, + 222, + 31, + 0, // Skip to: 8381 + /* 223 */ MCD_OPC_Decode, + 156, + 14, + 3, // Opcode: SBCrsr + /* 227 */ MCD_OPC_FilterValue, + 1, + 213, + 31, + 0, // Skip to: 8381 + /* 232 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 235 */ MCD_OPC_FilterValue, + 0, + 71, + 0, + 0, // Skip to: 311 + /* 240 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 243 */ MCD_OPC_FilterValue, + 0, + 14, + 0, + 0, // Skip to: 262 + /* 248 */ MCD_OPC_CheckPredicate, + 1, + 192, + 31, + 0, // Skip to: 8381 + /* 253 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 258 */ MCD_OPC_Decode, + 149, + 7, + 4, // Opcode: MUL + /* 262 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 283 + /* 267 */ MCD_OPC_CheckPredicate, + 1, + 173, + 31, + 0, // Skip to: 8381 + /* 272 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 166, + 31, + 0, // Skip to: 8381 + /* 279 */ MCD_OPC_Decode, + 195, + 15, + 5, // Opcode: UMAAL + /* 283 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 297 + /* 288 */ MCD_OPC_CheckPredicate, + 1, + 152, + 31, + 0, // Skip to: 8381 + /* 293 */ MCD_OPC_Decode, + 197, + 15, + 6, // Opcode: UMULL + /* 297 */ MCD_OPC_FilterValue, + 3, + 143, + 31, + 0, // Skip to: 8381 + /* 302 */ MCD_OPC_CheckPredicate, + 1, + 138, + 31, + 0, // Skip to: 8381 + /* 307 */ MCD_OPC_Decode, + 208, + 14, + 6, // Opcode: SMULL + /* 311 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 347 + /* 316 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 319 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 333 + /* 324 */ MCD_OPC_CheckPredicate, + 0, + 116, + 31, + 0, // Skip to: 8381 + /* 329 */ MCD_OPC_Decode, + 149, + 15, + 7, // Opcode: STRH_POST + /* 333 */ MCD_OPC_FilterValue, + 1, + 107, + 31, + 0, // Skip to: 8381 + /* 338 */ MCD_OPC_CheckPredicate, + 0, + 102, + 31, + 0, // Skip to: 8381 + /* 343 */ MCD_OPC_Decode, + 232, + 6, + 7, // Opcode: LDRH_POST + /* 347 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 383 + /* 352 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 355 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 369 + /* 360 */ MCD_OPC_CheckPredicate, + 0, + 80, + 31, + 0, // Skip to: 8381 + /* 365 */ MCD_OPC_Decode, + 223, + 6, + 7, // Opcode: LDRD_POST + /* 369 */ MCD_OPC_FilterValue, + 1, + 71, + 31, + 0, // Skip to: 8381 + /* 374 */ MCD_OPC_CheckPredicate, + 0, + 66, + 31, + 0, // Skip to: 8381 + /* 379 */ MCD_OPC_Decode, + 237, + 6, + 7, // Opcode: LDRSB_POST + /* 383 */ MCD_OPC_FilterValue, + 3, + 57, + 31, + 0, // Skip to: 8381 + /* 388 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 391 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 405 + /* 396 */ MCD_OPC_CheckPredicate, + 0, + 44, + 31, + 0, // Skip to: 8381 + /* 401 */ MCD_OPC_Decode, + 140, + 15, + 7, // Opcode: STRD_POST + /* 405 */ MCD_OPC_FilterValue, + 1, + 35, + 31, + 0, // Skip to: 8381 + /* 410 */ MCD_OPC_CheckPredicate, + 0, + 30, + 31, + 0, // Skip to: 8381 + /* 415 */ MCD_OPC_Decode, + 242, + 6, + 7, // Opcode: LDRSH_POST + /* 419 */ MCD_OPC_FilterValue, + 1, + 21, + 31, + 0, // Skip to: 8381 + /* 424 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 427 */ MCD_OPC_FilterValue, + 0, + 6, + 2, + 0, // Skip to: 950 + /* 432 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 435 */ MCD_OPC_FilterValue, + 0, + 152, + 1, + 0, // Skip to: 848 + /* 440 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 443 */ MCD_OPC_FilterValue, + 0, + 66, + 1, + 0, // Skip to: 770 + /* 448 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 451 */ MCD_OPC_FilterValue, + 14, + 67, + 0, + 0, // Skip to: 523 + /* 456 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 459 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 491 + /* 464 */ MCD_OPC_CheckPredicate, + 2, + 171, + 0, + 0, // Skip to: 640 + /* 469 */ MCD_OPC_CheckField, + 6, + 2, + 1, + 164, + 0, + 0, // Skip to: 640 + /* 476 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 157, + 0, + 0, // Skip to: 640 + /* 483 */ MCD_OPC_SoftFail, + 128, + 26 /* 0xd00 */, + 0, + /* 487 */ MCD_OPC_Decode, + 155, + 6, + 8, // Opcode: CRC32B + /* 491 */ MCD_OPC_FilterValue, + 1, + 144, + 0, + 0, // Skip to: 640 + /* 496 */ MCD_OPC_CheckPredicate, + 2, + 139, + 0, + 0, // Skip to: 640 + /* 501 */ MCD_OPC_CheckField, + 6, + 2, + 1, + 132, + 0, + 0, // Skip to: 640 + /* 508 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 125, + 0, + 0, // Skip to: 640 + /* 515 */ MCD_OPC_SoftFail, + 128, + 26 /* 0xd00 */, + 0, + /* 519 */ MCD_OPC_Decode, + 156, + 6, + 8, // Opcode: CRC32CB + /* 523 */ MCD_OPC_FilterValue, + 15, + 112, + 0, + 0, // Skip to: 640 + /* 528 */ MCD_OPC_ExtractField, + 10, + 8, // Inst{17-10} ... + /* 531 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 559 + /* 536 */ MCD_OPC_CheckPredicate, + 0, + 99, + 0, + 0, // Skip to: 640 + /* 541 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 92, + 0, + 0, // Skip to: 640 + /* 548 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 85, + 0, + 0, // Skip to: 640 + /* 555 */ MCD_OPC_Decode, + 153, + 6, + 9, // Opcode: CPS2p + /* 559 */ MCD_OPC_FilterValue, + 64, + 30, + 0, + 0, // Skip to: 594 + /* 564 */ MCD_OPC_CheckPredicate, + 0, + 71, + 0, + 0, // Skip to: 640 + /* 569 */ MCD_OPC_CheckField, + 18, + 2, + 0, + 64, + 0, + 0, // Skip to: 640 + /* 576 */ MCD_OPC_CheckField, + 6, + 3, + 0, + 57, + 0, + 0, // Skip to: 640 + /* 583 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 50, + 0, + 0, // Skip to: 640 + /* 590 */ MCD_OPC_Decode, + 160, + 14, + 10, // Opcode: SETEND + /* 594 */ MCD_OPC_FilterValue, + 128, + 1, + 40, + 0, + 0, // Skip to: 640 + /* 600 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 603 */ MCD_OPC_FilterValue, + 0, + 32, + 0, + 0, // Skip to: 640 + /* 608 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 631 + /* 613 */ MCD_OPC_CheckField, + 18, + 2, + 0, + 11, + 0, + 0, // Skip to: 631 + /* 620 */ MCD_OPC_CheckField, + 6, + 3, + 0, + 4, + 0, + 0, // Skip to: 631 + /* 627 */ MCD_OPC_Decode, + 152, + 6, + 9, // Opcode: CPS1p + /* 631 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 640 + /* 636 */ MCD_OPC_Decode, + 154, + 6, + 9, // Opcode: CPS3p + /* 640 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 643 */ MCD_OPC_FilterValue, + 0, + 36, + 0, + 0, // Skip to: 684 + /* 648 */ MCD_OPC_CheckPredicate, + 0, + 88, + 4, + 0, // Skip to: 1765 + /* 653 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 81, + 4, + 0, // Skip to: 1765 + /* 660 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 74, + 4, + 0, // Skip to: 1765 + /* 667 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 67, + 4, + 0, // Skip to: 1765 + /* 674 */ MCD_OPC_SoftFail, + 143, + 26 /* 0xd0f */, + 128, + 128, + 56 /* 0xe0000 */, + /* 680 */ MCD_OPC_Decode, + 143, + 7, + 11, // Opcode: MRS + /* 684 */ MCD_OPC_FilterValue, + 1, + 20, + 0, + 0, // Skip to: 709 + /* 689 */ MCD_OPC_CheckPredicate, + 0, + 47, + 4, + 0, // Skip to: 1765 + /* 694 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 40, + 4, + 0, // Skip to: 1765 + /* 701 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 705 */ MCD_OPC_Decode, + 247, + 13, + 12, // Opcode: QADD + /* 709 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 749 + /* 714 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 717 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 731 + /* 722 */ MCD_OPC_CheckPredicate, + 3, + 14, + 4, + 0, // Skip to: 1765 + /* 727 */ MCD_OPC_Decode, + 179, + 14, + 13, // Opcode: SMLABB + /* 731 */ MCD_OPC_FilterValue, + 1, + 5, + 4, + 0, // Skip to: 1765 + /* 736 */ MCD_OPC_CheckPredicate, + 4, + 0, + 4, + 0, // Skip to: 1765 + /* 741 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 745 */ MCD_OPC_Decode, + 164, + 15, + 14, // Opcode: SWP + /* 749 */ MCD_OPC_FilterValue, + 3, + 243, + 3, + 0, // Skip to: 1765 + /* 754 */ MCD_OPC_CheckPredicate, + 3, + 238, + 3, + 0, // Skip to: 1765 + /* 759 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 231, + 3, + 0, // Skip to: 1765 + /* 766 */ MCD_OPC_Decode, + 180, + 14, + 13, // Opcode: SMLABT + /* 770 */ MCD_OPC_FilterValue, + 1, + 222, + 3, + 0, // Skip to: 1765 + /* 775 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 778 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 806 + /* 783 */ MCD_OPC_CheckPredicate, + 5, + 209, + 3, + 0, // Skip to: 1765 + /* 788 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 202, + 3, + 0, // Skip to: 1765 + /* 795 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 195, + 3, + 0, // Skip to: 1765 + /* 802 */ MCD_OPC_Decode, + 180, + 6, + 15, // Opcode: HLT + /* 806 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 827 + /* 811 */ MCD_OPC_CheckPredicate, + 3, + 181, + 3, + 0, // Skip to: 1765 + /* 816 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 174, + 3, + 0, // Skip to: 1765 + /* 823 */ MCD_OPC_Decode, + 190, + 14, + 13, // Opcode: SMLATB + /* 827 */ MCD_OPC_FilterValue, + 3, + 165, + 3, + 0, // Skip to: 1765 + /* 832 */ MCD_OPC_CheckPredicate, + 3, + 160, + 3, + 0, // Skip to: 1765 + /* 837 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 153, + 3, + 0, // Skip to: 1765 + /* 844 */ MCD_OPC_Decode, + 191, + 14, + 13, // Opcode: SMLATT + /* 848 */ MCD_OPC_FilterValue, + 1, + 144, + 3, + 0, // Skip to: 1765 + /* 853 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 856 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 924 + /* 861 */ MCD_OPC_CheckPredicate, + 0, + 16, + 0, + 0, // Skip to: 882 + /* 866 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 9, + 0, + 0, // Skip to: 882 + /* 873 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 878 */ MCD_OPC_Decode, + 180, + 15, + 16, // Opcode: TSTrr + /* 882 */ MCD_OPC_CheckPredicate, + 6, + 23, + 0, + 0, // Skip to: 910 + /* 887 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 16, + 0, + 0, // Skip to: 910 + /* 894 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 9, + 0, + 0, // Skip to: 910 + /* 901 */ MCD_OPC_SoftFail, + 143, + 250, + 63 /* 0xffd0f */, + 0, + /* 906 */ MCD_OPC_Decode, + 161, + 14, + 10, // Opcode: SETPAN + /* 910 */ MCD_OPC_CheckPredicate, + 0, + 82, + 3, + 0, // Skip to: 1765 + /* 915 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 920 */ MCD_OPC_Decode, + 181, + 15, + 17, // Opcode: TSTrsi + /* 924 */ MCD_OPC_FilterValue, + 1, + 68, + 3, + 0, // Skip to: 1765 + /* 929 */ MCD_OPC_CheckPredicate, + 0, + 63, + 3, + 0, // Skip to: 1765 + /* 934 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 56, + 3, + 0, // Skip to: 1765 + /* 941 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 946 */ MCD_OPC_Decode, + 182, + 15, + 18, // Opcode: TSTrsr + /* 950 */ MCD_OPC_FilterValue, + 1, + 62, + 1, + 0, // Skip to: 1273 + /* 955 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 958 */ MCD_OPC_FilterValue, + 0, + 192, + 0, + 0, // Skip to: 1155 + /* 963 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 966 */ MCD_OPC_FilterValue, + 0, + 144, + 0, + 0, // Skip to: 1115 + /* 971 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 974 */ MCD_OPC_FilterValue, + 0, + 22, + 0, + 0, // Skip to: 1001 + /* 979 */ MCD_OPC_CheckPredicate, + 0, + 13, + 3, + 0, // Skip to: 1765 + /* 984 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 6, + 3, + 0, // Skip to: 1765 + /* 991 */ MCD_OPC_SoftFail, + 143, + 26 /* 0xd0f */, + 128, + 128, + 60 /* 0xf0000 */, + /* 997 */ MCD_OPC_Decode, + 145, + 7, + 11, // Opcode: MRSsys + /* 1001 */ MCD_OPC_FilterValue, + 2, + 53, + 0, + 0, // Skip to: 1059 + /* 1006 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 1009 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 1034 + /* 1014 */ MCD_OPC_CheckPredicate, + 2, + 234, + 2, + 0, // Skip to: 1765 + /* 1019 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 227, + 2, + 0, // Skip to: 1765 + /* 1026 */ MCD_OPC_SoftFail, + 128, + 26 /* 0xd00 */, + 0, + /* 1030 */ MCD_OPC_Decode, + 160, + 6, + 8, // Opcode: CRC32W + /* 1034 */ MCD_OPC_FilterValue, + 1, + 214, + 2, + 0, // Skip to: 1765 + /* 1039 */ MCD_OPC_CheckPredicate, + 2, + 209, + 2, + 0, // Skip to: 1765 + /* 1044 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 202, + 2, + 0, // Skip to: 1765 + /* 1051 */ MCD_OPC_SoftFail, + 128, + 26 /* 0xd00 */, + 0, + /* 1055 */ MCD_OPC_Decode, + 158, + 6, + 8, // Opcode: CRC32CW + /* 1059 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1073 + /* 1064 */ MCD_OPC_CheckPredicate, + 3, + 184, + 2, + 0, // Skip to: 1765 + /* 1069 */ MCD_OPC_Decode, + 184, + 14, + 19, // Opcode: SMLALBB + /* 1073 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 1087 + /* 1078 */ MCD_OPC_CheckPredicate, + 3, + 170, + 2, + 0, // Skip to: 1765 + /* 1083 */ MCD_OPC_Decode, + 188, + 14, + 19, // Opcode: SMLALTB + /* 1087 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 1101 + /* 1092 */ MCD_OPC_CheckPredicate, + 3, + 156, + 2, + 0, // Skip to: 1765 + /* 1097 */ MCD_OPC_Decode, + 185, + 14, + 19, // Opcode: SMLALBT + /* 1101 */ MCD_OPC_FilterValue, + 7, + 147, + 2, + 0, // Skip to: 1765 + /* 1106 */ MCD_OPC_CheckPredicate, + 3, + 142, + 2, + 0, // Skip to: 1765 + /* 1111 */ MCD_OPC_Decode, + 189, + 14, + 19, // Opcode: SMLALTT + /* 1115 */ MCD_OPC_FilterValue, + 1, + 133, + 2, + 0, // Skip to: 1765 + /* 1120 */ MCD_OPC_CheckPredicate, + 0, + 16, + 0, + 0, // Skip to: 1141 + /* 1125 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 9, + 0, + 0, // Skip to: 1141 + /* 1132 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 1137 */ MCD_OPC_Decode, + 149, + 6, + 20, // Opcode: CMPrr + /* 1141 */ MCD_OPC_CheckPredicate, + 0, + 107, + 2, + 0, // Skip to: 1765 + /* 1146 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 1151 */ MCD_OPC_Decode, + 150, + 6, + 17, // Opcode: CMPrsi + /* 1155 */ MCD_OPC_FilterValue, + 1, + 93, + 2, + 0, // Skip to: 1765 + /* 1160 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1163 */ MCD_OPC_FilterValue, + 0, + 73, + 0, + 0, // Skip to: 1241 + /* 1168 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1171 */ MCD_OPC_FilterValue, + 0, + 46, + 0, + 0, // Skip to: 1222 + /* 1176 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 1179 */ MCD_OPC_FilterValue, + 2, + 13, + 0, + 0, // Skip to: 1197 + /* 1184 */ MCD_OPC_CheckPredicate, + 0, + 64, + 2, + 0, // Skip to: 1765 + /* 1189 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 1193 */ MCD_OPC_Decode, + 251, + 13, + 21, // Opcode: QDADD + /* 1197 */ MCD_OPC_FilterValue, + 3, + 51, + 2, + 0, // Skip to: 1765 + /* 1202 */ MCD_OPC_CheckPredicate, + 7, + 46, + 2, + 0, // Skip to: 1765 + /* 1207 */ MCD_OPC_SoftFail, + 128, + 128, + 128, + 128, + 1 /* 0x10000000 */, + 128, + 128, + 128, + 128, + 14 /* 0xffffffffe0000000 */, + /* 1218 */ MCD_OPC_Decode, + 181, + 6, + 15, // Opcode: HVC + /* 1222 */ MCD_OPC_FilterValue, + 1, + 26, + 2, + 0, // Skip to: 1765 + /* 1227 */ MCD_OPC_CheckPredicate, + 0, + 21, + 2, + 0, // Skip to: 1765 + /* 1232 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 1237 */ MCD_OPC_Decode, + 151, + 6, + 18, // Opcode: CMPrsr + /* 1241 */ MCD_OPC_FilterValue, + 1, + 7, + 2, + 0, // Skip to: 1765 + /* 1246 */ MCD_OPC_CheckPredicate, + 4, + 2, + 2, + 0, // Skip to: 1765 + /* 1251 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 251, + 1, + 0, // Skip to: 1765 + /* 1258 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 244, + 1, + 0, // Skip to: 1765 + /* 1265 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 1269 */ MCD_OPC_Decode, + 165, + 15, + 14, // Opcode: SWPB + /* 1273 */ MCD_OPC_FilterValue, + 2, + 241, + 0, + 0, // Skip to: 1519 + /* 1278 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1281 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1311 + /* 1286 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 1302 + /* 1291 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 1302 + /* 1298 */ MCD_OPC_Decode, + 236, + 13, + 0, // Opcode: ORRrr + /* 1302 */ MCD_OPC_CheckPredicate, + 0, + 202, + 1, + 0, // Skip to: 1765 + /* 1307 */ MCD_OPC_Decode, + 237, + 13, + 1, // Opcode: ORRrsi + /* 1311 */ MCD_OPC_FilterValue, + 1, + 193, + 1, + 0, // Skip to: 1765 + /* 1316 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1319 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1333 + /* 1324 */ MCD_OPC_CheckPredicate, + 0, + 180, + 1, + 0, // Skip to: 1765 + /* 1329 */ MCD_OPC_Decode, + 238, + 13, + 2, // Opcode: ORRrsr + /* 1333 */ MCD_OPC_FilterValue, + 1, + 171, + 1, + 0, // Skip to: 1765 + /* 1338 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 1341 */ MCD_OPC_FilterValue, + 12, + 59, + 0, + 0, // Skip to: 1405 + /* 1346 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1349 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 1377 + /* 1354 */ MCD_OPC_CheckPredicate, + 8, + 150, + 1, + 0, // Skip to: 1765 + /* 1359 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 143, + 1, + 0, // Skip to: 1765 + /* 1366 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 136, + 1, + 0, // Skip to: 1765 + /* 1373 */ MCD_OPC_Decode, + 244, + 14, + 22, // Opcode: STL + /* 1377 */ MCD_OPC_FilterValue, + 1, + 127, + 1, + 0, // Skip to: 1765 + /* 1382 */ MCD_OPC_CheckPredicate, + 8, + 122, + 1, + 0, // Skip to: 1765 + /* 1387 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 115, + 1, + 0, // Skip to: 1765 + /* 1394 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 108, + 1, + 0, // Skip to: 1765 + /* 1401 */ MCD_OPC_Decode, + 183, + 6, + 23, // Opcode: LDA + /* 1405 */ MCD_OPC_FilterValue, + 14, + 52, + 0, + 0, // Skip to: 1462 + /* 1410 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1413 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1434 + /* 1418 */ MCD_OPC_CheckPredicate, + 9, + 86, + 1, + 0, // Skip to: 1765 + /* 1423 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 79, + 1, + 0, // Skip to: 1765 + /* 1430 */ MCD_OPC_Decode, + 246, + 14, + 24, // Opcode: STLEX + /* 1434 */ MCD_OPC_FilterValue, + 1, + 70, + 1, + 0, // Skip to: 1765 + /* 1439 */ MCD_OPC_CheckPredicate, + 9, + 65, + 1, + 0, // Skip to: 1765 + /* 1444 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 58, + 1, + 0, // Skip to: 1765 + /* 1451 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 51, + 1, + 0, // Skip to: 1765 + /* 1458 */ MCD_OPC_Decode, + 185, + 6, + 23, // Opcode: LDAEX + /* 1462 */ MCD_OPC_FilterValue, + 15, + 42, + 1, + 0, // Skip to: 1765 + /* 1467 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1470 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1491 + /* 1475 */ MCD_OPC_CheckPredicate, + 0, + 29, + 1, + 0, // Skip to: 1765 + /* 1480 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 22, + 1, + 0, // Skip to: 1765 + /* 1487 */ MCD_OPC_Decode, + 142, + 15, + 24, // Opcode: STREX + /* 1491 */ MCD_OPC_FilterValue, + 1, + 13, + 1, + 0, // Skip to: 1765 + /* 1496 */ MCD_OPC_CheckPredicate, + 0, + 8, + 1, + 0, // Skip to: 1765 + /* 1501 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 1, + 1, + 0, // Skip to: 1765 + /* 1508 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 250, + 0, + 0, // Skip to: 1765 + /* 1515 */ MCD_OPC_Decode, + 225, + 6, + 23, // Opcode: LDREX + /* 1519 */ MCD_OPC_FilterValue, + 3, + 241, + 0, + 0, // Skip to: 1765 + /* 1524 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1527 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1557 + /* 1532 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 1548 + /* 1537 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 1548 + /* 1544 */ MCD_OPC_Decode, + 224, + 5, + 0, // Opcode: BICrr + /* 1548 */ MCD_OPC_CheckPredicate, + 0, + 212, + 0, + 0, // Skip to: 1765 + /* 1553 */ MCD_OPC_Decode, + 225, + 5, + 1, // Opcode: BICrsi + /* 1557 */ MCD_OPC_FilterValue, + 1, + 203, + 0, + 0, // Skip to: 1765 + /* 1562 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1565 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1579 + /* 1570 */ MCD_OPC_CheckPredicate, + 0, + 190, + 0, + 0, // Skip to: 1765 + /* 1575 */ MCD_OPC_Decode, + 226, + 5, + 2, // Opcode: BICrsr + /* 1579 */ MCD_OPC_FilterValue, + 1, + 181, + 0, + 0, // Skip to: 1765 + /* 1584 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 1587 */ MCD_OPC_FilterValue, + 12, + 59, + 0, + 0, // Skip to: 1651 + /* 1592 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1595 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 1623 + /* 1600 */ MCD_OPC_CheckPredicate, + 8, + 160, + 0, + 0, // Skip to: 1765 + /* 1605 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 153, + 0, + 0, // Skip to: 1765 + /* 1612 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 146, + 0, + 0, // Skip to: 1765 + /* 1619 */ MCD_OPC_Decode, + 245, + 14, + 22, // Opcode: STLB + /* 1623 */ MCD_OPC_FilterValue, + 1, + 137, + 0, + 0, // Skip to: 1765 + /* 1628 */ MCD_OPC_CheckPredicate, + 8, + 132, + 0, + 0, // Skip to: 1765 + /* 1633 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 125, + 0, + 0, // Skip to: 1765 + /* 1640 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 118, + 0, + 0, // Skip to: 1765 + /* 1647 */ MCD_OPC_Decode, + 184, + 6, + 23, // Opcode: LDAB + /* 1651 */ MCD_OPC_FilterValue, + 14, + 52, + 0, + 0, // Skip to: 1708 + /* 1656 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1659 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1680 + /* 1664 */ MCD_OPC_CheckPredicate, + 9, + 96, + 0, + 0, // Skip to: 1765 + /* 1669 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 89, + 0, + 0, // Skip to: 1765 + /* 1676 */ MCD_OPC_Decode, + 247, + 14, + 24, // Opcode: STLEXB + /* 1680 */ MCD_OPC_FilterValue, + 1, + 80, + 0, + 0, // Skip to: 1765 + /* 1685 */ MCD_OPC_CheckPredicate, + 9, + 75, + 0, + 0, // Skip to: 1765 + /* 1690 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 68, + 0, + 0, // Skip to: 1765 + /* 1697 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 61, + 0, + 0, // Skip to: 1765 + /* 1704 */ MCD_OPC_Decode, + 186, + 6, + 23, // Opcode: LDAEXB + /* 1708 */ MCD_OPC_FilterValue, + 15, + 52, + 0, + 0, // Skip to: 1765 + /* 1713 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1716 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1737 + /* 1721 */ MCD_OPC_CheckPredicate, + 0, + 39, + 0, + 0, // Skip to: 1765 + /* 1726 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 32, + 0, + 0, // Skip to: 1765 + /* 1733 */ MCD_OPC_Decode, + 143, + 15, + 24, // Opcode: STREXB + /* 1737 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 1765 + /* 1742 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 1765 + /* 1747 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 11, + 0, + 0, // Skip to: 1765 + /* 1754 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 4, + 0, + 0, // Skip to: 1765 + /* 1761 */ MCD_OPC_Decode, + 226, + 6, + 23, // Opcode: LDREXB + /* 1765 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 1768 */ MCD_OPC_FilterValue, + 0, + 37, + 0, + 0, // Skip to: 1810 + /* 1773 */ MCD_OPC_CheckPredicate, + 7, + 203, + 25, + 0, // Skip to: 8381 + /* 1778 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 196, + 25, + 0, // Skip to: 8381 + /* 1785 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 189, + 25, + 0, // Skip to: 8381 + /* 1792 */ MCD_OPC_CheckField, + 9, + 3, + 1, + 182, + 25, + 0, // Skip to: 8381 + /* 1799 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 175, + 25, + 0, // Skip to: 8381 + /* 1806 */ MCD_OPC_Decode, + 144, + 7, + 25, // Opcode: MRSbanked + /* 1810 */ MCD_OPC_FilterValue, + 11, + 31, + 0, + 0, // Skip to: 1846 + /* 1815 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1818 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1832 + /* 1823 */ MCD_OPC_CheckPredicate, + 0, + 153, + 25, + 0, // Skip to: 8381 + /* 1828 */ MCD_OPC_Decode, + 146, + 15, + 7, // Opcode: STRH + /* 1832 */ MCD_OPC_FilterValue, + 1, + 144, + 25, + 0, // Skip to: 8381 + /* 1837 */ MCD_OPC_CheckPredicate, + 0, + 139, + 25, + 0, // Skip to: 8381 + /* 1842 */ MCD_OPC_Decode, + 229, + 6, + 7, // Opcode: LDRH + /* 1846 */ MCD_OPC_FilterValue, + 13, + 31, + 0, + 0, // Skip to: 1882 + /* 1851 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1854 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1868 + /* 1859 */ MCD_OPC_CheckPredicate, + 3, + 117, + 25, + 0, // Skip to: 8381 + /* 1864 */ MCD_OPC_Decode, + 222, + 6, + 7, // Opcode: LDRD + /* 1868 */ MCD_OPC_FilterValue, + 1, + 108, + 25, + 0, // Skip to: 8381 + /* 1873 */ MCD_OPC_CheckPredicate, + 0, + 103, + 25, + 0, // Skip to: 8381 + /* 1878 */ MCD_OPC_Decode, + 234, + 6, + 7, // Opcode: LDRSB + /* 1882 */ MCD_OPC_FilterValue, + 15, + 94, + 25, + 0, // Skip to: 8381 + /* 1887 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1890 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1904 + /* 1895 */ MCD_OPC_CheckPredicate, + 3, + 81, + 25, + 0, // Skip to: 8381 + /* 1900 */ MCD_OPC_Decode, + 139, + 15, + 7, // Opcode: STRD + /* 1904 */ MCD_OPC_FilterValue, + 1, + 72, + 25, + 0, // Skip to: 8381 + /* 1909 */ MCD_OPC_CheckPredicate, + 0, + 67, + 25, + 0, // Skip to: 8381 + /* 1914 */ MCD_OPC_Decode, + 239, + 6, + 7, // Opcode: LDRSH + /* 1918 */ MCD_OPC_FilterValue, + 1, + 58, + 25, + 0, // Skip to: 8381 + /* 1923 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1926 */ MCD_OPC_FilterValue, + 0, + 180, + 2, + 0, // Skip to: 2623 + /* 1931 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 1934 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 2002 + /* 1939 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 1942 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1972 + /* 1947 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 1963 + /* 1952 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 1963 + /* 1959 */ MCD_OPC_Decode, + 165, + 6, + 0, // Opcode: EORrr + /* 1963 */ MCD_OPC_CheckPredicate, + 0, + 13, + 25, + 0, // Skip to: 8381 + /* 1968 */ MCD_OPC_Decode, + 166, + 6, + 1, // Opcode: EORrsi + /* 1972 */ MCD_OPC_FilterValue, + 1, + 4, + 25, + 0, // Skip to: 8381 + /* 1977 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 1993 + /* 1982 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 1993 + /* 1989 */ MCD_OPC_Decode, + 142, + 14, + 0, // Opcode: RSBrr + /* 1993 */ MCD_OPC_CheckPredicate, + 0, + 239, + 24, + 0, // Skip to: 8381 + /* 1998 */ MCD_OPC_Decode, + 143, + 14, + 1, // Opcode: RSBrsi + /* 2002 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 2070 + /* 2007 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2010 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2040 + /* 2015 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 2031 + /* 2020 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 2031 + /* 2027 */ MCD_OPC_Decode, + 198, + 5, + 0, // Opcode: ADCrr + /* 2031 */ MCD_OPC_CheckPredicate, + 0, + 201, + 24, + 0, // Skip to: 8381 + /* 2036 */ MCD_OPC_Decode, + 199, + 5, + 1, // Opcode: ADCrsi + /* 2040 */ MCD_OPC_FilterValue, + 1, + 192, + 24, + 0, // Skip to: 8381 + /* 2045 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 2061 + /* 2050 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 2061 + /* 2057 */ MCD_OPC_Decode, + 146, + 14, + 0, // Opcode: RSCrr + /* 2061 */ MCD_OPC_CheckPredicate, + 0, + 171, + 24, + 0, // Skip to: 8381 + /* 2066 */ MCD_OPC_Decode, + 147, + 14, + 1, // Opcode: RSCrsi + /* 2070 */ MCD_OPC_FilterValue, + 2, + 166, + 1, + 0, // Skip to: 2497 + /* 2075 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2078 */ MCD_OPC_FilterValue, + 0, + 70, + 1, + 0, // Skip to: 2409 + /* 2083 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 2086 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 2129 + /* 2091 */ MCD_OPC_ExtractField, + 9, + 7, // Inst{15-9} ... + /* 2094 */ MCD_OPC_FilterValue, + 120, + 16, + 0, + 0, // Skip to: 2115 + /* 2099 */ MCD_OPC_CheckPredicate, + 0, + 133, + 24, + 0, // Skip to: 8381 + /* 2104 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 126, + 24, + 0, // Skip to: 8381 + /* 2111 */ MCD_OPC_Decode, + 146, + 7, + 26, // Opcode: MSR + /* 2115 */ MCD_OPC_FilterValue, + 121, + 117, + 24, + 0, // Skip to: 8381 + /* 2120 */ MCD_OPC_CheckPredicate, + 7, + 112, + 24, + 0, // Skip to: 8381 + /* 2125 */ MCD_OPC_Decode, + 147, + 7, + 27, // Opcode: MSRbanked + /* 2129 */ MCD_OPC_FilterValue, + 1, + 24, + 0, + 0, // Skip to: 2158 + /* 2134 */ MCD_OPC_CheckPredicate, + 0, + 98, + 24, + 0, // Skip to: 8381 + /* 2139 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 91, + 24, + 0, // Skip to: 8381 + /* 2146 */ MCD_OPC_CheckField, + 8, + 12, + 255, + 31, + 83, + 24, + 0, // Skip to: 8381 + /* 2154 */ MCD_OPC_Decode, + 234, + 5, + 28, // Opcode: BXJ + /* 2158 */ MCD_OPC_FilterValue, + 2, + 67, + 0, + 0, // Skip to: 2230 + /* 2163 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 2166 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 2198 + /* 2171 */ MCD_OPC_CheckPredicate, + 2, + 61, + 24, + 0, // Skip to: 8381 + /* 2176 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 54, + 24, + 0, // Skip to: 8381 + /* 2183 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 47, + 24, + 0, // Skip to: 8381 + /* 2190 */ MCD_OPC_SoftFail, + 128, + 26 /* 0xd00 */, + 0, + /* 2194 */ MCD_OPC_Decode, + 159, + 6, + 8, // Opcode: CRC32H + /* 2198 */ MCD_OPC_FilterValue, + 1, + 34, + 24, + 0, // Skip to: 8381 + /* 2203 */ MCD_OPC_CheckPredicate, + 2, + 29, + 24, + 0, // Skip to: 8381 + /* 2208 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 22, + 24, + 0, // Skip to: 8381 + /* 2215 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 15, + 24, + 0, // Skip to: 8381 + /* 2222 */ MCD_OPC_SoftFail, + 128, + 26 /* 0xd00 */, + 0, + /* 2226 */ MCD_OPC_Decode, + 157, + 6, + 8, // Opcode: CRC32CH + /* 2230 */ MCD_OPC_FilterValue, + 3, + 30, + 0, + 0, // Skip to: 2265 + /* 2235 */ MCD_OPC_CheckPredicate, + 7, + 253, + 23, + 0, // Skip to: 8381 + /* 2240 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 246, + 23, + 0, // Skip to: 8381 + /* 2247 */ MCD_OPC_CheckField, + 8, + 12, + 0, + 239, + 23, + 0, // Skip to: 8381 + /* 2254 */ MCD_OPC_CheckField, + 0, + 4, + 14, + 232, + 23, + 0, // Skip to: 8381 + /* 2261 */ MCD_OPC_Decode, + 168, + 6, + 29, // Opcode: ERET + /* 2265 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 2301 + /* 2270 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2273 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2287 + /* 2278 */ MCD_OPC_CheckPredicate, + 3, + 210, + 23, + 0, // Skip to: 8381 + /* 2283 */ MCD_OPC_Decode, + 192, + 14, + 13, // Opcode: SMLAWB + /* 2287 */ MCD_OPC_FilterValue, + 1, + 201, + 23, + 0, // Skip to: 8381 + /* 2292 */ MCD_OPC_CheckPredicate, + 3, + 196, + 23, + 0, // Skip to: 8381 + /* 2297 */ MCD_OPC_Decode, + 206, + 14, + 30, // Opcode: SMULBB + /* 2301 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 2337 + /* 2306 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2309 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2323 + /* 2314 */ MCD_OPC_CheckPredicate, + 3, + 174, + 23, + 0, // Skip to: 8381 + /* 2319 */ MCD_OPC_Decode, + 211, + 14, + 30, // Opcode: SMULWB + /* 2323 */ MCD_OPC_FilterValue, + 1, + 165, + 23, + 0, // Skip to: 8381 + /* 2328 */ MCD_OPC_CheckPredicate, + 3, + 160, + 23, + 0, // Skip to: 8381 + /* 2333 */ MCD_OPC_Decode, + 209, + 14, + 30, // Opcode: SMULTB + /* 2337 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 2373 + /* 2342 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2345 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2359 + /* 2350 */ MCD_OPC_CheckPredicate, + 3, + 138, + 23, + 0, // Skip to: 8381 + /* 2355 */ MCD_OPC_Decode, + 193, + 14, + 13, // Opcode: SMLAWT + /* 2359 */ MCD_OPC_FilterValue, + 1, + 129, + 23, + 0, // Skip to: 8381 + /* 2364 */ MCD_OPC_CheckPredicate, + 3, + 124, + 23, + 0, // Skip to: 8381 + /* 2369 */ MCD_OPC_Decode, + 207, + 14, + 30, // Opcode: SMULBT + /* 2373 */ MCD_OPC_FilterValue, + 7, + 115, + 23, + 0, // Skip to: 8381 + /* 2378 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2381 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2395 + /* 2386 */ MCD_OPC_CheckPredicate, + 3, + 102, + 23, + 0, // Skip to: 8381 + /* 2391 */ MCD_OPC_Decode, + 212, + 14, + 30, // Opcode: SMULWT + /* 2395 */ MCD_OPC_FilterValue, + 1, + 93, + 23, + 0, // Skip to: 8381 + /* 2400 */ MCD_OPC_CheckPredicate, + 3, + 88, + 23, + 0, // Skip to: 8381 + /* 2405 */ MCD_OPC_Decode, + 210, + 14, + 30, // Opcode: SMULTT + /* 2409 */ MCD_OPC_FilterValue, + 1, + 79, + 23, + 0, // Skip to: 8381 + /* 2414 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2417 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 2457 + /* 2422 */ MCD_OPC_CheckPredicate, + 0, + 16, + 0, + 0, // Skip to: 2443 + /* 2427 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 9, + 0, + 0, // Skip to: 2443 + /* 2434 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 2439 */ MCD_OPC_Decode, + 173, + 15, + 20, // Opcode: TEQrr + /* 2443 */ MCD_OPC_CheckPredicate, + 0, + 45, + 23, + 0, // Skip to: 8381 + /* 2448 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 2453 */ MCD_OPC_Decode, + 174, + 15, + 17, // Opcode: TEQrsi + /* 2457 */ MCD_OPC_FilterValue, + 1, + 31, + 23, + 0, // Skip to: 8381 + /* 2462 */ MCD_OPC_CheckPredicate, + 0, + 16, + 0, + 0, // Skip to: 2483 + /* 2467 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 9, + 0, + 0, // Skip to: 2483 + /* 2474 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 2479 */ MCD_OPC_Decode, + 145, + 6, + 20, // Opcode: CMNzrr + /* 2483 */ MCD_OPC_CheckPredicate, + 0, + 5, + 23, + 0, // Skip to: 8381 + /* 2488 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 2493 */ MCD_OPC_Decode, + 146, + 6, + 17, // Opcode: CMNzrsi + /* 2497 */ MCD_OPC_FilterValue, + 3, + 247, + 22, + 0, // Skip to: 8381 + /* 2502 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2505 */ MCD_OPC_FilterValue, + 0, + 73, + 0, + 0, // Skip to: 2583 + /* 2510 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 2534 + /* 2515 */ MCD_OPC_CheckField, + 5, + 16, + 128, + 15, + 11, + 0, + 0, // Skip to: 2534 + /* 2523 */ MCD_OPC_CheckField, + 0, + 4, + 14, + 4, + 0, + 0, // Skip to: 2534 + /* 2530 */ MCD_OPC_Decode, + 131, + 7, + 29, // Opcode: MOVPCLR + /* 2534 */ MCD_OPC_ExtractField, + 5, + 7, // Inst{11-5} ... + /* 2537 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2567 + /* 2542 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 2558 + /* 2547 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 4, + 0, + 0, // Skip to: 2558 + /* 2554 */ MCD_OPC_Decode, + 135, + 7, + 31, // Opcode: MOVr + /* 2558 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 2567 + /* 2563 */ MCD_OPC_Decode, + 136, + 7, + 32, // Opcode: MOVr_TC + /* 2567 */ MCD_OPC_CheckPredicate, + 0, + 177, + 22, + 0, // Skip to: 8381 + /* 2572 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 170, + 22, + 0, // Skip to: 8381 + /* 2579 */ MCD_OPC_Decode, + 137, + 7, + 33, // Opcode: MOVsi + /* 2583 */ MCD_OPC_FilterValue, + 1, + 161, + 22, + 0, // Skip to: 8381 + /* 2588 */ MCD_OPC_CheckPredicate, + 0, + 16, + 0, + 0, // Skip to: 2609 + /* 2593 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 9, + 0, + 0, // Skip to: 2609 + /* 2600 */ MCD_OPC_SoftFail, + 128, + 128, + 60 /* 0xf0000 */, + 0, + /* 2605 */ MCD_OPC_Decode, + 224, + 13, + 31, // Opcode: MVNr + /* 2609 */ MCD_OPC_CheckPredicate, + 0, + 135, + 22, + 0, // Skip to: 8381 + /* 2614 */ MCD_OPC_SoftFail, + 128, + 128, + 60 /* 0xf0000 */, + 0, + /* 2619 */ MCD_OPC_Decode, + 225, + 13, + 33, // Opcode: MVNsi + /* 2623 */ MCD_OPC_FilterValue, + 1, + 121, + 22, + 0, // Skip to: 8381 + /* 2628 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 2631 */ MCD_OPC_FilterValue, + 0, + 113, + 1, + 0, // Skip to: 3005 + /* 2636 */ MCD_OPC_ExtractField, + 22, + 3, // Inst{24-22} ... + /* 2639 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2653 + /* 2644 */ MCD_OPC_CheckPredicate, + 0, + 100, + 22, + 0, // Skip to: 8381 + /* 2649 */ MCD_OPC_Decode, + 167, + 6, + 2, // Opcode: EORrsr + /* 2653 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 2667 + /* 2658 */ MCD_OPC_CheckPredicate, + 0, + 86, + 22, + 0, // Skip to: 8381 + /* 2663 */ MCD_OPC_Decode, + 144, + 14, + 2, // Opcode: RSBrsr + /* 2667 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2681 + /* 2672 */ MCD_OPC_CheckPredicate, + 0, + 72, + 22, + 0, // Skip to: 8381 + /* 2677 */ MCD_OPC_Decode, + 200, + 5, + 3, // Opcode: ADCrsr + /* 2681 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 2695 + /* 2686 */ MCD_OPC_CheckPredicate, + 0, + 58, + 22, + 0, // Skip to: 8381 + /* 2691 */ MCD_OPC_Decode, + 148, + 14, + 2, // Opcode: RSCrsr + /* 2695 */ MCD_OPC_FilterValue, + 4, + 163, + 0, + 0, // Skip to: 2863 + /* 2700 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2703 */ MCD_OPC_FilterValue, + 0, + 136, + 0, + 0, // Skip to: 2844 + /* 2708 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 2711 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 2766 + /* 2716 */ MCD_OPC_ExtractField, + 8, + 12, // Inst{19-8} ... + /* 2719 */ MCD_OPC_FilterValue, + 255, + 31, + 24, + 22, + 0, // Skip to: 8381 + /* 2725 */ MCD_OPC_CheckPredicate, + 10, + 11, + 0, + 0, // Skip to: 2741 + /* 2730 */ MCD_OPC_CheckField, + 0, + 4, + 14, + 4, + 0, + 0, // Skip to: 2741 + /* 2737 */ MCD_OPC_Decode, + 235, + 5, + 29, // Opcode: BX_RET + /* 2741 */ MCD_OPC_CheckPredicate, + 10, + 11, + 0, + 0, // Skip to: 2757 + /* 2746 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 4, + 0, + 0, // Skip to: 2757 + /* 2753 */ MCD_OPC_Decode, + 233, + 5, + 34, // Opcode: BX + /* 2757 */ MCD_OPC_CheckPredicate, + 10, + 243, + 21, + 0, // Skip to: 8381 + /* 2762 */ MCD_OPC_Decode, + 236, + 5, + 28, // Opcode: BX_pred + /* 2766 */ MCD_OPC_FilterValue, + 1, + 34, + 0, + 0, // Skip to: 2805 + /* 2771 */ MCD_OPC_ExtractField, + 8, + 12, // Inst{19-8} ... + /* 2774 */ MCD_OPC_FilterValue, + 255, + 31, + 225, + 21, + 0, // Skip to: 8381 + /* 2780 */ MCD_OPC_CheckPredicate, + 11, + 11, + 0, + 0, // Skip to: 2796 + /* 2785 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 4, + 0, + 0, // Skip to: 2796 + /* 2792 */ MCD_OPC_Decode, + 229, + 5, + 34, // Opcode: BLX + /* 2796 */ MCD_OPC_CheckPredicate, + 11, + 204, + 21, + 0, // Skip to: 8381 + /* 2801 */ MCD_OPC_Decode, + 230, + 5, + 28, // Opcode: BLX_pred + /* 2805 */ MCD_OPC_FilterValue, + 2, + 13, + 0, + 0, // Skip to: 2823 + /* 2810 */ MCD_OPC_CheckPredicate, + 0, + 190, + 21, + 0, // Skip to: 8381 + /* 2815 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 2819 */ MCD_OPC_Decode, + 254, + 13, + 21, // Opcode: QSUB + /* 2823 */ MCD_OPC_FilterValue, + 3, + 177, + 21, + 0, // Skip to: 8381 + /* 2828 */ MCD_OPC_CheckPredicate, + 0, + 172, + 21, + 0, // Skip to: 8381 + /* 2833 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 165, + 21, + 0, // Skip to: 8381 + /* 2840 */ MCD_OPC_Decode, + 227, + 5, + 15, // Opcode: BKPT + /* 2844 */ MCD_OPC_FilterValue, + 1, + 156, + 21, + 0, // Skip to: 8381 + /* 2849 */ MCD_OPC_CheckPredicate, + 0, + 151, + 21, + 0, // Skip to: 8381 + /* 2854 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 2859 */ MCD_OPC_Decode, + 175, + 15, + 18, // Opcode: TEQrsr + /* 2863 */ MCD_OPC_FilterValue, + 5, + 97, + 0, + 0, // Skip to: 2965 + /* 2868 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2871 */ MCD_OPC_FilterValue, + 0, + 70, + 0, + 0, // Skip to: 2946 + /* 2876 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 2879 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 2907 + /* 2884 */ MCD_OPC_CheckPredicate, + 11, + 116, + 21, + 0, // Skip to: 8381 + /* 2889 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 109, + 21, + 0, // Skip to: 8381 + /* 2896 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 102, + 21, + 0, // Skip to: 8381 + /* 2903 */ MCD_OPC_Decode, + 143, + 6, + 35, // Opcode: CLZ + /* 2907 */ MCD_OPC_FilterValue, + 2, + 13, + 0, + 0, // Skip to: 2925 + /* 2912 */ MCD_OPC_CheckPredicate, + 0, + 88, + 21, + 0, // Skip to: 8381 + /* 2917 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 2921 */ MCD_OPC_Decode, + 252, + 13, + 21, // Opcode: QDSUB + /* 2925 */ MCD_OPC_FilterValue, + 3, + 75, + 21, + 0, // Skip to: 8381 + /* 2930 */ MCD_OPC_CheckPredicate, + 12, + 70, + 21, + 0, // Skip to: 8381 + /* 2935 */ MCD_OPC_CheckField, + 8, + 12, + 0, + 63, + 21, + 0, // Skip to: 8381 + /* 2942 */ MCD_OPC_Decode, + 178, + 14, + 36, // Opcode: SMC + /* 2946 */ MCD_OPC_FilterValue, + 1, + 54, + 21, + 0, // Skip to: 8381 + /* 2951 */ MCD_OPC_CheckPredicate, + 0, + 49, + 21, + 0, // Skip to: 8381 + /* 2956 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 2961 */ MCD_OPC_Decode, + 147, + 6, + 18, // Opcode: CMNzrsr + /* 2965 */ MCD_OPC_FilterValue, + 6, + 16, + 0, + 0, // Skip to: 2986 + /* 2970 */ MCD_OPC_CheckPredicate, + 0, + 30, + 21, + 0, // Skip to: 8381 + /* 2975 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 23, + 21, + 0, // Skip to: 8381 + /* 2982 */ MCD_OPC_Decode, + 138, + 7, + 37, // Opcode: MOVsr + /* 2986 */ MCD_OPC_FilterValue, + 7, + 14, + 21, + 0, // Skip to: 8381 + /* 2991 */ MCD_OPC_CheckPredicate, + 0, + 9, + 21, + 0, // Skip to: 8381 + /* 2996 */ MCD_OPC_SoftFail, + 128, + 128, + 60 /* 0xf0000 */, + 0, + /* 3001 */ MCD_OPC_Decode, + 226, + 13, + 37, // Opcode: MVNsr + /* 3005 */ MCD_OPC_FilterValue, + 1, + 251, + 20, + 0, // Skip to: 8381 + /* 3010 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 3013 */ MCD_OPC_FilterValue, + 0, + 48, + 1, + 0, // Skip to: 3322 + /* 3018 */ MCD_OPC_ExtractField, + 22, + 3, // Inst{24-22} ... + /* 3021 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3035 + /* 3026 */ MCD_OPC_CheckPredicate, + 1, + 230, + 20, + 0, // Skip to: 8381 + /* 3031 */ MCD_OPC_Decode, + 129, + 7, + 38, // Opcode: MLA + /* 3035 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 3056 + /* 3040 */ MCD_OPC_CheckPredicate, + 13, + 216, + 20, + 0, // Skip to: 8381 + /* 3045 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 209, + 20, + 0, // Skip to: 8381 + /* 3052 */ MCD_OPC_Decode, + 130, + 7, + 39, // Opcode: MLS + /* 3056 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3070 + /* 3061 */ MCD_OPC_CheckPredicate, + 1, + 195, + 20, + 0, // Skip to: 8381 + /* 3066 */ MCD_OPC_Decode, + 196, + 15, + 40, // Opcode: UMLAL + /* 3070 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 3084 + /* 3075 */ MCD_OPC_CheckPredicate, + 1, + 181, + 20, + 0, // Skip to: 8381 + /* 3080 */ MCD_OPC_Decode, + 183, + 14, + 40, // Opcode: SMLAL + /* 3084 */ MCD_OPC_FilterValue, + 6, + 89, + 0, + 0, // Skip to: 3178 + /* 3089 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 3092 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 3135 + /* 3097 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3100 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3114 + /* 3105 */ MCD_OPC_CheckPredicate, + 9, + 151, + 20, + 0, // Skip to: 8381 + /* 3110 */ MCD_OPC_Decode, + 248, + 14, + 41, // Opcode: STLEXD + /* 3114 */ MCD_OPC_FilterValue, + 1, + 142, + 20, + 0, // Skip to: 8381 + /* 3119 */ MCD_OPC_CheckPredicate, + 9, + 137, + 20, + 0, // Skip to: 8381 + /* 3124 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 130, + 20, + 0, // Skip to: 8381 + /* 3131 */ MCD_OPC_Decode, + 187, + 6, + 42, // Opcode: LDAEXD + /* 3135 */ MCD_OPC_FilterValue, + 15, + 121, + 20, + 0, // Skip to: 8381 + /* 3140 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3143 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3157 + /* 3148 */ MCD_OPC_CheckPredicate, + 0, + 108, + 20, + 0, // Skip to: 8381 + /* 3153 */ MCD_OPC_Decode, + 144, + 15, + 41, // Opcode: STREXD + /* 3157 */ MCD_OPC_FilterValue, + 1, + 99, + 20, + 0, // Skip to: 8381 + /* 3162 */ MCD_OPC_CheckPredicate, + 0, + 94, + 20, + 0, // Skip to: 8381 + /* 3167 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 87, + 20, + 0, // Skip to: 8381 + /* 3174 */ MCD_OPC_Decode, + 227, + 6, + 42, // Opcode: LDREXD + /* 3178 */ MCD_OPC_FilterValue, + 7, + 78, + 20, + 0, // Skip to: 8381 + /* 3183 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 3186 */ MCD_OPC_FilterValue, + 12, + 45, + 0, + 0, // Skip to: 3236 + /* 3191 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3194 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3215 + /* 3199 */ MCD_OPC_CheckPredicate, + 8, + 57, + 20, + 0, // Skip to: 8381 + /* 3204 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 50, + 20, + 0, // Skip to: 8381 + /* 3211 */ MCD_OPC_Decode, + 250, + 14, + 22, // Opcode: STLH + /* 3215 */ MCD_OPC_FilterValue, + 1, + 41, + 20, + 0, // Skip to: 8381 + /* 3220 */ MCD_OPC_CheckPredicate, + 8, + 36, + 20, + 0, // Skip to: 8381 + /* 3225 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 29, + 20, + 0, // Skip to: 8381 + /* 3232 */ MCD_OPC_Decode, + 189, + 6, + 23, // Opcode: LDAH + /* 3236 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 3279 + /* 3241 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3244 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3258 + /* 3249 */ MCD_OPC_CheckPredicate, + 9, + 7, + 20, + 0, // Skip to: 8381 + /* 3254 */ MCD_OPC_Decode, + 249, + 14, + 24, // Opcode: STLEXH + /* 3258 */ MCD_OPC_FilterValue, + 1, + 254, + 19, + 0, // Skip to: 8381 + /* 3263 */ MCD_OPC_CheckPredicate, + 9, + 249, + 19, + 0, // Skip to: 8381 + /* 3268 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 242, + 19, + 0, // Skip to: 8381 + /* 3275 */ MCD_OPC_Decode, + 188, + 6, + 23, // Opcode: LDAEXH + /* 3279 */ MCD_OPC_FilterValue, + 15, + 233, + 19, + 0, // Skip to: 8381 + /* 3284 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3287 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3301 + /* 3292 */ MCD_OPC_CheckPredicate, + 0, + 220, + 19, + 0, // Skip to: 8381 + /* 3297 */ MCD_OPC_Decode, + 145, + 15, + 24, // Opcode: STREXH + /* 3301 */ MCD_OPC_FilterValue, + 1, + 211, + 19, + 0, // Skip to: 8381 + /* 3306 */ MCD_OPC_CheckPredicate, + 0, + 206, + 19, + 0, // Skip to: 8381 + /* 3311 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 199, + 19, + 0, // Skip to: 8381 + /* 3318 */ MCD_OPC_Decode, + 228, + 6, + 23, // Opcode: LDREXH + /* 3322 */ MCD_OPC_FilterValue, + 1, + 130, + 0, + 0, // Skip to: 3457 + /* 3327 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3330 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 3395 + /* 3335 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3338 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 3381 + /* 3343 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3346 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3367 + /* 3351 */ MCD_OPC_CheckPredicate, + 0, + 161, + 19, + 0, // Skip to: 8381 + /* 3356 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 154, + 19, + 0, // Skip to: 8381 + /* 3363 */ MCD_OPC_Decode, + 148, + 15, + 43, // Opcode: STRHTr + /* 3367 */ MCD_OPC_FilterValue, + 1, + 145, + 19, + 0, // Skip to: 8381 + /* 3372 */ MCD_OPC_CheckPredicate, + 0, + 140, + 19, + 0, // Skip to: 8381 + /* 3377 */ MCD_OPC_Decode, + 147, + 15, + 44, // Opcode: STRHTi + /* 3381 */ MCD_OPC_FilterValue, + 1, + 131, + 19, + 0, // Skip to: 8381 + /* 3386 */ MCD_OPC_CheckPredicate, + 0, + 126, + 19, + 0, // Skip to: 8381 + /* 3391 */ MCD_OPC_Decode, + 150, + 15, + 7, // Opcode: STRH_PRE + /* 3395 */ MCD_OPC_FilterValue, + 1, + 117, + 19, + 0, // Skip to: 8381 + /* 3400 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3403 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 3443 + /* 3408 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3411 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 3429 + /* 3416 */ MCD_OPC_CheckPredicate, + 0, + 96, + 19, + 0, // Skip to: 8381 + /* 3421 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 3425 */ MCD_OPC_Decode, + 231, + 6, + 45, // Opcode: LDRHTr + /* 3429 */ MCD_OPC_FilterValue, + 1, + 83, + 19, + 0, // Skip to: 8381 + /* 3434 */ MCD_OPC_CheckPredicate, + 0, + 78, + 19, + 0, // Skip to: 8381 + /* 3439 */ MCD_OPC_Decode, + 230, + 6, + 46, // Opcode: LDRHTi + /* 3443 */ MCD_OPC_FilterValue, + 1, + 69, + 19, + 0, // Skip to: 8381 + /* 3448 */ MCD_OPC_CheckPredicate, + 0, + 64, + 19, + 0, // Skip to: 8381 + /* 3453 */ MCD_OPC_Decode, + 233, + 6, + 7, // Opcode: LDRH_PRE + /* 3457 */ MCD_OPC_FilterValue, + 2, + 86, + 0, + 0, // Skip to: 3548 + /* 3462 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3465 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3486 + /* 3470 */ MCD_OPC_CheckPredicate, + 0, + 42, + 19, + 0, // Skip to: 8381 + /* 3475 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 35, + 19, + 0, // Skip to: 8381 + /* 3482 */ MCD_OPC_Decode, + 224, + 6, + 7, // Opcode: LDRD_PRE + /* 3486 */ MCD_OPC_FilterValue, + 1, + 26, + 19, + 0, // Skip to: 8381 + /* 3491 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3494 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 3534 + /* 3499 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3502 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 3520 + /* 3507 */ MCD_OPC_CheckPredicate, + 0, + 5, + 19, + 0, // Skip to: 8381 + /* 3512 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 3516 */ MCD_OPC_Decode, + 236, + 6, + 45, // Opcode: LDRSBTr + /* 3520 */ MCD_OPC_FilterValue, + 1, + 248, + 18, + 0, // Skip to: 8381 + /* 3525 */ MCD_OPC_CheckPredicate, + 0, + 243, + 18, + 0, // Skip to: 8381 + /* 3530 */ MCD_OPC_Decode, + 235, + 6, + 46, // Opcode: LDRSBTi + /* 3534 */ MCD_OPC_FilterValue, + 1, + 234, + 18, + 0, // Skip to: 8381 + /* 3539 */ MCD_OPC_CheckPredicate, + 0, + 229, + 18, + 0, // Skip to: 8381 + /* 3544 */ MCD_OPC_Decode, + 238, + 6, + 7, // Opcode: LDRSB_PRE + /* 3548 */ MCD_OPC_FilterValue, + 3, + 220, + 18, + 0, // Skip to: 8381 + /* 3553 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3556 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3577 + /* 3561 */ MCD_OPC_CheckPredicate, + 0, + 207, + 18, + 0, // Skip to: 8381 + /* 3566 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 200, + 18, + 0, // Skip to: 8381 + /* 3573 */ MCD_OPC_Decode, + 141, + 15, + 7, // Opcode: STRD_PRE + /* 3577 */ MCD_OPC_FilterValue, + 1, + 191, + 18, + 0, // Skip to: 8381 + /* 3582 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3585 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 3625 + /* 3590 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3593 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 3611 + /* 3598 */ MCD_OPC_CheckPredicate, + 0, + 170, + 18, + 0, // Skip to: 8381 + /* 3603 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 3607 */ MCD_OPC_Decode, + 241, + 6, + 45, // Opcode: LDRSHTr + /* 3611 */ MCD_OPC_FilterValue, + 1, + 157, + 18, + 0, // Skip to: 8381 + /* 3616 */ MCD_OPC_CheckPredicate, + 0, + 152, + 18, + 0, // Skip to: 8381 + /* 3621 */ MCD_OPC_Decode, + 240, + 6, + 46, // Opcode: LDRSHTi + /* 3625 */ MCD_OPC_FilterValue, + 1, + 143, + 18, + 0, // Skip to: 8381 + /* 3630 */ MCD_OPC_CheckPredicate, + 0, + 138, + 18, + 0, // Skip to: 8381 + /* 3635 */ MCD_OPC_Decode, + 243, + 6, + 7, // Opcode: LDRSH_PRE + /* 3639 */ MCD_OPC_FilterValue, + 1, + 0, + 2, + 0, // Skip to: 4156 + /* 3644 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 3647 */ MCD_OPC_FilterValue, + 0, + 201, + 0, + 0, // Skip to: 3853 + /* 3652 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3655 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 3735 + /* 3660 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 3663 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3677 + /* 3668 */ MCD_OPC_CheckPredicate, + 0, + 46, + 0, + 0, // Skip to: 3719 + /* 3673 */ MCD_OPC_Decode, + 210, + 5, + 47, // Opcode: ANDri + /* 3677 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3691 + /* 3682 */ MCD_OPC_CheckPredicate, + 0, + 32, + 0, + 0, // Skip to: 3719 + /* 3687 */ MCD_OPC_Decode, + 159, + 15, + 47, // Opcode: SUBri + /* 3691 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3705 + /* 3696 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 3719 + /* 3701 */ MCD_OPC_Decode, + 201, + 5, + 47, // Opcode: ADDri + /* 3705 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 3719 + /* 3710 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 3719 + /* 3715 */ MCD_OPC_Decode, + 153, + 14, + 47, // Opcode: SBCri + /* 3719 */ MCD_OPC_CheckPredicate, + 0, + 49, + 18, + 0, // Skip to: 8381 + /* 3724 */ MCD_OPC_CheckField, + 16, + 5, + 15, + 42, + 18, + 0, // Skip to: 8381 + /* 3731 */ MCD_OPC_Decode, + 205, + 5, + 48, // Opcode: ADR + /* 3735 */ MCD_OPC_FilterValue, + 1, + 33, + 18, + 0, // Skip to: 8381 + /* 3740 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 3743 */ MCD_OPC_FilterValue, + 0, + 36, + 0, + 0, // Skip to: 3784 + /* 3748 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3751 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3765 + /* 3756 */ MCD_OPC_CheckPredicate, + 13, + 12, + 18, + 0, // Skip to: 8381 + /* 3761 */ MCD_OPC_Decode, + 134, + 7, + 49, // Opcode: MOVi16 + /* 3765 */ MCD_OPC_FilterValue, + 1, + 3, + 18, + 0, // Skip to: 8381 + /* 3770 */ MCD_OPC_CheckPredicate, + 0, + 254, + 17, + 0, // Skip to: 8381 + /* 3775 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 3780 */ MCD_OPC_Decode, + 179, + 15, + 50, // Opcode: TSTri + /* 3784 */ MCD_OPC_FilterValue, + 1, + 36, + 0, + 0, // Skip to: 3825 + /* 3789 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3792 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3806 + /* 3797 */ MCD_OPC_CheckPredicate, + 13, + 227, + 17, + 0, // Skip to: 8381 + /* 3802 */ MCD_OPC_Decode, + 132, + 7, + 49, // Opcode: MOVTi16 + /* 3806 */ MCD_OPC_FilterValue, + 1, + 218, + 17, + 0, // Skip to: 8381 + /* 3811 */ MCD_OPC_CheckPredicate, + 0, + 213, + 17, + 0, // Skip to: 8381 + /* 3816 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 3821 */ MCD_OPC_Decode, + 148, + 6, + 50, // Opcode: CMPri + /* 3825 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3839 + /* 3830 */ MCD_OPC_CheckPredicate, + 0, + 194, + 17, + 0, // Skip to: 8381 + /* 3835 */ MCD_OPC_Decode, + 235, + 13, + 47, // Opcode: ORRri + /* 3839 */ MCD_OPC_FilterValue, + 3, + 185, + 17, + 0, // Skip to: 8381 + /* 3844 */ MCD_OPC_CheckPredicate, + 0, + 180, + 17, + 0, // Skip to: 8381 + /* 3849 */ MCD_OPC_Decode, + 223, + 5, + 47, // Opcode: BICri + /* 3853 */ MCD_OPC_FilterValue, + 1, + 171, + 17, + 0, // Skip to: 8381 + /* 3858 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 3861 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 3897 + /* 3866 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3869 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3883 + /* 3874 */ MCD_OPC_CheckPredicate, + 0, + 150, + 17, + 0, // Skip to: 8381 + /* 3879 */ MCD_OPC_Decode, + 164, + 6, + 47, // Opcode: EORri + /* 3883 */ MCD_OPC_FilterValue, + 1, + 141, + 17, + 0, // Skip to: 8381 + /* 3888 */ MCD_OPC_CheckPredicate, + 0, + 136, + 17, + 0, // Skip to: 8381 + /* 3893 */ MCD_OPC_Decode, + 141, + 14, + 47, // Opcode: RSBri + /* 3897 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 3933 + /* 3902 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3905 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3919 + /* 3910 */ MCD_OPC_CheckPredicate, + 0, + 114, + 17, + 0, // Skip to: 8381 + /* 3915 */ MCD_OPC_Decode, + 197, + 5, + 47, // Opcode: ADCri + /* 3919 */ MCD_OPC_FilterValue, + 1, + 105, + 17, + 0, // Skip to: 8381 + /* 3924 */ MCD_OPC_CheckPredicate, + 0, + 100, + 17, + 0, // Skip to: 8381 + /* 3929 */ MCD_OPC_Decode, + 145, + 14, + 47, // Opcode: RSCri + /* 3933 */ MCD_OPC_FilterValue, + 2, + 168, + 0, + 0, // Skip to: 4106 + /* 3938 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3941 */ MCD_OPC_FilterValue, + 0, + 114, + 0, + 0, // Skip to: 4060 + /* 3946 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 3949 */ MCD_OPC_FilterValue, + 15, + 75, + 17, + 0, // Skip to: 8381 + /* 3954 */ MCD_OPC_CheckPredicate, + 14, + 32, + 0, + 0, // Skip to: 3991 + /* 3959 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 25, + 0, + 0, // Skip to: 3991 + /* 3966 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 18, + 0, + 0, // Skip to: 3991 + /* 3973 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 11, + 0, + 0, // Skip to: 3991 + /* 3980 */ MCD_OPC_CheckField, + 0, + 12, + 18, + 4, + 0, + 0, // Skip to: 3991 + /* 3987 */ MCD_OPC_Decode, + 178, + 15, + 51, // Opcode: TSB + /* 3991 */ MCD_OPC_CheckPredicate, + 15, + 25, + 0, + 0, // Skip to: 4021 + /* 3996 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 18, + 0, + 0, // Skip to: 4021 + /* 4003 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 11, + 0, + 0, // Skip to: 4021 + /* 4010 */ MCD_OPC_CheckField, + 4, + 8, + 15, + 4, + 0, + 0, // Skip to: 4021 + /* 4017 */ MCD_OPC_Decode, + 161, + 6, + 36, // Opcode: DBG + /* 4021 */ MCD_OPC_CheckPredicate, + 1, + 25, + 0, + 0, // Skip to: 4051 + /* 4026 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 18, + 0, + 0, // Skip to: 4051 + /* 4033 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 11, + 0, + 0, // Skip to: 4051 + /* 4040 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 4051 + /* 4047 */ MCD_OPC_Decode, + 179, + 6, + 52, // Opcode: HINT + /* 4051 */ MCD_OPC_CheckPredicate, + 0, + 229, + 16, + 0, // Skip to: 8381 + /* 4056 */ MCD_OPC_Decode, + 148, + 7, + 53, // Opcode: MSRi + /* 4060 */ MCD_OPC_FilterValue, + 1, + 220, + 16, + 0, // Skip to: 8381 + /* 4065 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4068 */ MCD_OPC_FilterValue, + 0, + 14, + 0, + 0, // Skip to: 4087 + /* 4073 */ MCD_OPC_CheckPredicate, + 0, + 207, + 16, + 0, // Skip to: 8381 + /* 4078 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 4083 */ MCD_OPC_Decode, + 172, + 15, + 50, // Opcode: TEQri + /* 4087 */ MCD_OPC_FilterValue, + 1, + 193, + 16, + 0, // Skip to: 8381 + /* 4092 */ MCD_OPC_CheckPredicate, + 0, + 188, + 16, + 0, // Skip to: 8381 + /* 4097 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 4102 */ MCD_OPC_Decode, + 144, + 6, + 50, // Opcode: CMNri + /* 4106 */ MCD_OPC_FilterValue, + 3, + 174, + 16, + 0, // Skip to: 8381 + /* 4111 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4114 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 4135 + /* 4119 */ MCD_OPC_CheckPredicate, + 0, + 161, + 16, + 0, // Skip to: 8381 + /* 4124 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 154, + 16, + 0, // Skip to: 8381 + /* 4131 */ MCD_OPC_Decode, + 133, + 7, + 54, // Opcode: MOVi + /* 4135 */ MCD_OPC_FilterValue, + 1, + 145, + 16, + 0, // Skip to: 8381 + /* 4140 */ MCD_OPC_CheckPredicate, + 0, + 140, + 16, + 0, // Skip to: 8381 + /* 4145 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 133, + 16, + 0, // Skip to: 8381 + /* 4152 */ MCD_OPC_Decode, + 223, + 13, + 54, // Opcode: MVNi + /* 4156 */ MCD_OPC_FilterValue, + 2, + 9, + 2, + 0, // Skip to: 4682 + /* 4161 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 4164 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 4200 + /* 4169 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4172 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4186 + /* 4177 */ MCD_OPC_CheckPredicate, + 0, + 103, + 16, + 0, // Skip to: 8381 + /* 4182 */ MCD_OPC_Decode, + 153, + 15, + 55, // Opcode: STR_POST_IMM + /* 4186 */ MCD_OPC_FilterValue, + 1, + 94, + 16, + 0, // Skip to: 8381 + /* 4191 */ MCD_OPC_CheckPredicate, + 0, + 89, + 16, + 0, // Skip to: 8381 + /* 4196 */ MCD_OPC_Decode, + 157, + 15, + 56, // Opcode: STRi12 + /* 4200 */ MCD_OPC_FilterValue, + 1, + 54, + 0, + 0, // Skip to: 4259 + /* 4205 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4208 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4222 + /* 4213 */ MCD_OPC_CheckPredicate, + 0, + 67, + 16, + 0, // Skip to: 8381 + /* 4218 */ MCD_OPC_Decode, + 246, + 6, + 55, // Opcode: LDR_POST_IMM + /* 4222 */ MCD_OPC_FilterValue, + 1, + 58, + 16, + 0, // Skip to: 8381 + /* 4227 */ MCD_OPC_CheckPredicate, + 16, + 18, + 0, + 0, // Skip to: 4250 + /* 4232 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 4250 + /* 4239 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 4250 + /* 4246 */ MCD_OPC_Decode, + 241, + 13, + 57, // Opcode: PLDWi12 + /* 4250 */ MCD_OPC_CheckPredicate, + 0, + 30, + 16, + 0, // Skip to: 8381 + /* 4255 */ MCD_OPC_Decode, + 251, + 6, + 56, // Opcode: LDRi12 + /* 4259 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 4295 + /* 4264 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4267 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4281 + /* 4272 */ MCD_OPC_CheckPredicate, + 0, + 8, + 16, + 0, // Skip to: 8381 + /* 4277 */ MCD_OPC_Decode, + 151, + 15, + 55, // Opcode: STRT_POST_IMM + /* 4281 */ MCD_OPC_FilterValue, + 1, + 255, + 15, + 0, // Skip to: 8381 + /* 4286 */ MCD_OPC_CheckPredicate, + 0, + 250, + 15, + 0, // Skip to: 8381 + /* 4291 */ MCD_OPC_Decode, + 155, + 15, + 58, // Opcode: STR_PRE_IMM + /* 4295 */ MCD_OPC_FilterValue, + 3, + 31, + 0, + 0, // Skip to: 4331 + /* 4300 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4303 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4317 + /* 4308 */ MCD_OPC_CheckPredicate, + 0, + 228, + 15, + 0, // Skip to: 8381 + /* 4313 */ MCD_OPC_Decode, + 244, + 6, + 55, // Opcode: LDRT_POST_IMM + /* 4317 */ MCD_OPC_FilterValue, + 1, + 219, + 15, + 0, // Skip to: 8381 + /* 4322 */ MCD_OPC_CheckPredicate, + 0, + 214, + 15, + 0, // Skip to: 8381 + /* 4327 */ MCD_OPC_Decode, + 248, + 6, + 59, // Opcode: LDR_PRE_IMM + /* 4331 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 4367 + /* 4336 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4339 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4353 + /* 4344 */ MCD_OPC_CheckPredicate, + 0, + 192, + 15, + 0, // Skip to: 8381 + /* 4349 */ MCD_OPC_Decode, + 133, + 15, + 55, // Opcode: STRB_POST_IMM + /* 4353 */ MCD_OPC_FilterValue, + 1, + 183, + 15, + 0, // Skip to: 8381 + /* 4358 */ MCD_OPC_CheckPredicate, + 0, + 178, + 15, + 0, // Skip to: 8381 + /* 4363 */ MCD_OPC_Decode, + 137, + 15, + 60, // Opcode: STRBi12 + /* 4367 */ MCD_OPC_FilterValue, + 5, + 77, + 0, + 0, // Skip to: 4449 + /* 4372 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4375 */ MCD_OPC_FilterValue, + 0, + 32, + 0, + 0, // Skip to: 4412 + /* 4380 */ MCD_OPC_CheckPredicate, + 15, + 18, + 0, + 0, // Skip to: 4403 + /* 4385 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 4403 + /* 4392 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 4403 + /* 4399 */ MCD_OPC_Decode, + 245, + 13, + 57, // Opcode: PLIi12 + /* 4403 */ MCD_OPC_CheckPredicate, + 0, + 133, + 15, + 0, // Skip to: 8381 + /* 4408 */ MCD_OPC_Decode, + 216, + 6, + 55, // Opcode: LDRB_POST_IMM + /* 4412 */ MCD_OPC_FilterValue, + 1, + 124, + 15, + 0, // Skip to: 8381 + /* 4417 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 4440 + /* 4422 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 4440 + /* 4429 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 4440 + /* 4436 */ MCD_OPC_Decode, + 243, + 13, + 57, // Opcode: PLDi12 + /* 4440 */ MCD_OPC_CheckPredicate, + 0, + 96, + 15, + 0, // Skip to: 8381 + /* 4445 */ MCD_OPC_Decode, + 220, + 6, + 60, // Opcode: LDRBi12 + /* 4449 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 4485 + /* 4454 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4457 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4471 + /* 4462 */ MCD_OPC_CheckPredicate, + 0, + 74, + 15, + 0, // Skip to: 8381 + /* 4467 */ MCD_OPC_Decode, + 131, + 15, + 55, // Opcode: STRBT_POST_IMM + /* 4471 */ MCD_OPC_FilterValue, + 1, + 65, + 15, + 0, // Skip to: 8381 + /* 4476 */ MCD_OPC_CheckPredicate, + 0, + 60, + 15, + 0, // Skip to: 8381 + /* 4481 */ MCD_OPC_Decode, + 135, + 15, + 58, // Opcode: STRB_PRE_IMM + /* 4485 */ MCD_OPC_FilterValue, + 7, + 51, + 15, + 0, // Skip to: 8381 + /* 4490 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4493 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4507 + /* 4498 */ MCD_OPC_CheckPredicate, + 0, + 38, + 15, + 0, // Skip to: 8381 + /* 4503 */ MCD_OPC_Decode, + 214, + 6, + 55, // Opcode: LDRBT_POST_IMM + /* 4507 */ MCD_OPC_FilterValue, + 1, + 29, + 15, + 0, // Skip to: 8381 + /* 4512 */ MCD_OPC_CheckPredicate, + 17, + 27, + 0, + 0, // Skip to: 4544 + /* 4517 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 20, + 0, + 0, // Skip to: 4544 + /* 4524 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 13, + 0, + 0, // Skip to: 4544 + /* 4531 */ MCD_OPC_CheckField, + 0, + 20, + 159, + 224, + 63, + 4, + 0, + 0, // Skip to: 4544 + /* 4540 */ MCD_OPC_Decode, + 142, + 6, + 61, // Opcode: CLREX + /* 4544 */ MCD_OPC_ExtractField, + 4, + 16, // Inst{19-4} ... + /* 4547 */ MCD_OPC_FilterValue, + 132, + 254, + 3, + 23, + 0, + 0, // Skip to: 4577 + /* 4554 */ MCD_OPC_CheckPredicate, + 18, + 78, + 0, + 0, // Skip to: 4637 + /* 4559 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 71, + 0, + 0, // Skip to: 4637 + /* 4566 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 64, + 0, + 0, // Skip to: 4637 + /* 4573 */ MCD_OPC_Decode, + 163, + 6, + 62, // Opcode: DSB + /* 4577 */ MCD_OPC_FilterValue, + 133, + 254, + 3, + 23, + 0, + 0, // Skip to: 4607 + /* 4584 */ MCD_OPC_CheckPredicate, + 18, + 48, + 0, + 0, // Skip to: 4637 + /* 4589 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 41, + 0, + 0, // Skip to: 4637 + /* 4596 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 34, + 0, + 0, // Skip to: 4637 + /* 4603 */ MCD_OPC_Decode, + 162, + 6, + 62, // Opcode: DMB + /* 4607 */ MCD_OPC_FilterValue, + 134, + 254, + 3, + 23, + 0, + 0, // Skip to: 4637 + /* 4614 */ MCD_OPC_CheckPredicate, + 18, + 18, + 0, + 0, // Skip to: 4637 + /* 4619 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 4637 + /* 4626 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 4, + 0, + 0, // Skip to: 4637 + /* 4633 */ MCD_OPC_Decode, + 182, + 6, + 63, // Opcode: ISB + /* 4637 */ MCD_OPC_CheckPredicate, + 19, + 31, + 0, + 0, // Skip to: 4673 + /* 4642 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 24, + 0, + 0, // Skip to: 4673 + /* 4649 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 17, + 0, + 0, // Skip to: 4673 + /* 4656 */ MCD_OPC_CheckField, + 4, + 4, + 7, + 10, + 0, + 0, // Skip to: 4673 + /* 4663 */ MCD_OPC_SoftFail, + 143, + 30 /* 0xf0f */, + 128, + 224, + 63 /* 0xff000 */, + /* 4669 */ MCD_OPC_Decode, + 152, + 14, + 61, // Opcode: SB + /* 4673 */ MCD_OPC_CheckPredicate, + 0, + 119, + 14, + 0, // Skip to: 8381 + /* 4678 */ MCD_OPC_Decode, + 218, + 6, + 59, // Opcode: LDRB_PRE_IMM + /* 4682 */ MCD_OPC_FilterValue, + 3, + 129, + 10, + 0, // Skip to: 7376 + /* 4687 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 4690 */ MCD_OPC_FilterValue, + 0, + 200, + 2, + 0, // Skip to: 5407 + /* 4695 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 4698 */ MCD_OPC_FilterValue, + 0, + 98, + 0, + 0, // Skip to: 4801 + /* 4703 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 4706 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 4742 + /* 4711 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4714 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4728 + /* 4719 */ MCD_OPC_CheckPredicate, + 0, + 73, + 14, + 0, // Skip to: 8381 + /* 4724 */ MCD_OPC_Decode, + 154, + 15, + 55, // Opcode: STR_POST_REG + /* 4728 */ MCD_OPC_FilterValue, + 1, + 64, + 14, + 0, // Skip to: 8381 + /* 4733 */ MCD_OPC_CheckPredicate, + 0, + 59, + 14, + 0, // Skip to: 8381 + /* 4738 */ MCD_OPC_Decode, + 158, + 15, + 64, // Opcode: STRrs + /* 4742 */ MCD_OPC_FilterValue, + 1, + 50, + 14, + 0, // Skip to: 8381 + /* 4747 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4750 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4764 + /* 4755 */ MCD_OPC_CheckPredicate, + 0, + 37, + 14, + 0, // Skip to: 8381 + /* 4760 */ MCD_OPC_Decode, + 247, + 6, + 55, // Opcode: LDR_POST_REG + /* 4764 */ MCD_OPC_FilterValue, + 1, + 28, + 14, + 0, // Skip to: 8381 + /* 4769 */ MCD_OPC_CheckPredicate, + 16, + 18, + 0, + 0, // Skip to: 4792 + /* 4774 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 4792 + /* 4781 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 4792 + /* 4788 */ MCD_OPC_Decode, + 242, + 13, + 65, // Opcode: PLDWrs + /* 4792 */ MCD_OPC_CheckPredicate, + 0, + 0, + 14, + 0, // Skip to: 8381 + /* 4797 */ MCD_OPC_Decode, + 252, + 6, + 64, // Opcode: LDRrs + /* 4801 */ MCD_OPC_FilterValue, + 1, + 247, + 13, + 0, // Skip to: 8381 + /* 4806 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 4809 */ MCD_OPC_FilterValue, + 0, + 202, + 0, + 0, // Skip to: 5016 + /* 4814 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 4817 */ MCD_OPC_FilterValue, + 0, + 53, + 0, + 0, // Skip to: 4875 + /* 4822 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4825 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 4850 + /* 4830 */ MCD_OPC_CheckPredicate, + 0, + 218, + 13, + 0, // Skip to: 8381 + /* 4835 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 211, + 13, + 0, // Skip to: 8381 + /* 4842 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 4846 */ MCD_OPC_Decode, + 149, + 14, + 66, // Opcode: SADD16 + /* 4850 */ MCD_OPC_FilterValue, + 1, + 198, + 13, + 0, // Skip to: 8381 + /* 4855 */ MCD_OPC_CheckPredicate, + 0, + 193, + 13, + 0, // Skip to: 8381 + /* 4860 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 186, + 13, + 0, // Skip to: 8381 + /* 4867 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 4871 */ MCD_OPC_Decode, + 150, + 14, + 66, // Opcode: SADD8 + /* 4875 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 4896 + /* 4880 */ MCD_OPC_CheckPredicate, + 1, + 168, + 13, + 0, // Skip to: 8381 + /* 4885 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 161, + 13, + 0, // Skip to: 8381 + /* 4892 */ MCD_OPC_Decode, + 239, + 13, + 67, // Opcode: PKHBT + /* 4896 */ MCD_OPC_FilterValue, + 2, + 69, + 0, + 0, // Skip to: 4970 + /* 4901 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 4904 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 4942 + /* 4909 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4912 */ MCD_OPC_FilterValue, + 0, + 136, + 13, + 0, // Skip to: 8381 + /* 4917 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 4933 + /* 4922 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 4933 + /* 4929 */ MCD_OPC_Decode, + 204, + 14, + 68, // Opcode: SMUAD + /* 4933 */ MCD_OPC_CheckPredicate, + 1, + 115, + 13, + 0, // Skip to: 8381 + /* 4938 */ MCD_OPC_Decode, + 181, + 14, + 69, // Opcode: SMLAD + /* 4942 */ MCD_OPC_FilterValue, + 1, + 106, + 13, + 0, // Skip to: 8381 + /* 4947 */ MCD_OPC_CheckPredicate, + 20, + 101, + 13, + 0, // Skip to: 8381 + /* 4952 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 94, + 13, + 0, // Skip to: 8381 + /* 4959 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 87, + 13, + 0, // Skip to: 8381 + /* 4966 */ MCD_OPC_Decode, + 158, + 14, + 30, // Opcode: SDIV + /* 4970 */ MCD_OPC_FilterValue, + 3, + 78, + 13, + 0, // Skip to: 8381 + /* 4975 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4978 */ MCD_OPC_FilterValue, + 0, + 70, + 13, + 0, // Skip to: 8381 + /* 4983 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 4986 */ MCD_OPC_FilterValue, + 0, + 62, + 13, + 0, // Skip to: 8381 + /* 4991 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 5007 + /* 4996 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 5007 + /* 5003 */ MCD_OPC_Decode, + 204, + 15, + 30, // Opcode: USAD8 + /* 5007 */ MCD_OPC_CheckPredicate, + 1, + 41, + 13, + 0, // Skip to: 8381 + /* 5012 */ MCD_OPC_Decode, + 205, + 15, + 39, // Opcode: USADA8 + /* 5016 */ MCD_OPC_FilterValue, + 1, + 113, + 0, + 0, // Skip to: 5134 + /* 5021 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 5024 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 5056 + /* 5029 */ MCD_OPC_CheckPredicate, + 0, + 19, + 13, + 0, // Skip to: 8381 + /* 5034 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 13, + 0, // Skip to: 8381 + /* 5041 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 5, + 13, + 0, // Skip to: 8381 + /* 5048 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5052 */ MCD_OPC_Decode, + 151, + 14, + 66, // Opcode: SASX + /* 5056 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 5088 + /* 5061 */ MCD_OPC_CheckPredicate, + 1, + 243, + 12, + 0, // Skip to: 8381 + /* 5066 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 236, + 12, + 0, // Skip to: 8381 + /* 5073 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 229, + 12, + 0, // Skip to: 8381 + /* 5080 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5084 */ MCD_OPC_Decode, + 159, + 14, + 70, // Opcode: SEL + /* 5088 */ MCD_OPC_FilterValue, + 2, + 216, + 12, + 0, // Skip to: 8381 + /* 5093 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 5096 */ MCD_OPC_FilterValue, + 0, + 208, + 12, + 0, // Skip to: 8381 + /* 5101 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5104 */ MCD_OPC_FilterValue, + 0, + 200, + 12, + 0, // Skip to: 8381 + /* 5109 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 5125 + /* 5114 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 5125 + /* 5121 */ MCD_OPC_Decode, + 205, + 14, + 68, // Opcode: SMUADX + /* 5125 */ MCD_OPC_CheckPredicate, + 1, + 179, + 12, + 0, // Skip to: 8381 + /* 5130 */ MCD_OPC_Decode, + 182, + 14, + 69, // Opcode: SMLADX + /* 5134 */ MCD_OPC_FilterValue, + 2, + 102, + 0, + 0, // Skip to: 5241 + /* 5139 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 5142 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 5174 + /* 5147 */ MCD_OPC_CheckPredicate, + 0, + 157, + 12, + 0, // Skip to: 8381 + /* 5152 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 150, + 12, + 0, // Skip to: 8381 + /* 5159 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 143, + 12, + 0, // Skip to: 8381 + /* 5166 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5170 */ MCD_OPC_Decode, + 225, + 14, + 66, // Opcode: SSAX + /* 5174 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 5195 + /* 5179 */ MCD_OPC_CheckPredicate, + 1, + 125, + 12, + 0, // Skip to: 8381 + /* 5184 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 118, + 12, + 0, // Skip to: 8381 + /* 5191 */ MCD_OPC_Decode, + 240, + 13, + 67, // Opcode: PKHTB + /* 5195 */ MCD_OPC_FilterValue, + 2, + 109, + 12, + 0, // Skip to: 8381 + /* 5200 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 5203 */ MCD_OPC_FilterValue, + 0, + 101, + 12, + 0, // Skip to: 8381 + /* 5208 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5211 */ MCD_OPC_FilterValue, + 0, + 93, + 12, + 0, // Skip to: 8381 + /* 5216 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 5232 + /* 5221 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 5232 + /* 5228 */ MCD_OPC_Decode, + 213, + 14, + 68, // Opcode: SMUSD + /* 5232 */ MCD_OPC_CheckPredicate, + 1, + 72, + 12, + 0, // Skip to: 8381 + /* 5237 */ MCD_OPC_Decode, + 194, + 14, + 69, // Opcode: SMLSD + /* 5241 */ MCD_OPC_FilterValue, + 3, + 63, + 12, + 0, // Skip to: 8381 + /* 5246 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 5249 */ MCD_OPC_FilterValue, + 0, + 53, + 0, + 0, // Skip to: 5307 + /* 5254 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 5257 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 5282 + /* 5262 */ MCD_OPC_CheckPredicate, + 0, + 42, + 12, + 0, // Skip to: 8381 + /* 5267 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 35, + 12, + 0, // Skip to: 8381 + /* 5274 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5278 */ MCD_OPC_Decode, + 226, + 14, + 66, // Opcode: SSUB16 + /* 5282 */ MCD_OPC_FilterValue, + 1, + 22, + 12, + 0, // Skip to: 8381 + /* 5287 */ MCD_OPC_CheckPredicate, + 0, + 17, + 12, + 0, // Skip to: 8381 + /* 5292 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 10, + 12, + 0, // Skip to: 8381 + /* 5299 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5303 */ MCD_OPC_Decode, + 227, + 14, + 66, // Opcode: SSUB8 + /* 5307 */ MCD_OPC_FilterValue, + 1, + 49, + 0, + 0, // Skip to: 5361 + /* 5312 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 5315 */ MCD_OPC_FilterValue, + 0, + 245, + 11, + 0, // Skip to: 8381 + /* 5320 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5323 */ MCD_OPC_FilterValue, + 0, + 237, + 11, + 0, // Skip to: 8381 + /* 5328 */ MCD_OPC_CheckPredicate, + 1, + 15, + 0, + 0, // Skip to: 5348 + /* 5333 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 8, + 0, + 0, // Skip to: 5348 + /* 5340 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 5344 */ MCD_OPC_Decode, + 170, + 15, + 71, // Opcode: SXTB16 + /* 5348 */ MCD_OPC_CheckPredicate, + 1, + 212, + 11, + 0, // Skip to: 8381 + /* 5353 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 5357 */ MCD_OPC_Decode, + 167, + 15, + 72, // Opcode: SXTAB16 + /* 5361 */ MCD_OPC_FilterValue, + 2, + 199, + 11, + 0, // Skip to: 8381 + /* 5366 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 5369 */ MCD_OPC_FilterValue, + 0, + 191, + 11, + 0, // Skip to: 8381 + /* 5374 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5377 */ MCD_OPC_FilterValue, + 0, + 183, + 11, + 0, // Skip to: 8381 + /* 5382 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 5398 + /* 5387 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 5398 + /* 5394 */ MCD_OPC_Decode, + 214, + 14, + 68, // Opcode: SMUSDX + /* 5398 */ MCD_OPC_CheckPredicate, + 1, + 162, + 11, + 0, // Skip to: 8381 + /* 5403 */ MCD_OPC_Decode, + 195, + 14, + 69, // Opcode: SMLSDX + /* 5407 */ MCD_OPC_FilterValue, + 1, + 106, + 2, + 0, // Skip to: 6030 + /* 5412 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 5415 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 5495 + /* 5420 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5423 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 5459 + /* 5428 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 5431 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5445 + /* 5436 */ MCD_OPC_CheckPredicate, + 0, + 124, + 11, + 0, // Skip to: 8381 + /* 5441 */ MCD_OPC_Decode, + 152, + 15, + 55, // Opcode: STRT_POST_REG + /* 5445 */ MCD_OPC_FilterValue, + 1, + 115, + 11, + 0, // Skip to: 8381 + /* 5450 */ MCD_OPC_CheckPredicate, + 0, + 110, + 11, + 0, // Skip to: 8381 + /* 5455 */ MCD_OPC_Decode, + 156, + 15, + 73, // Opcode: STR_PRE_REG + /* 5459 */ MCD_OPC_FilterValue, + 1, + 101, + 11, + 0, // Skip to: 8381 + /* 5464 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 5467 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5481 + /* 5472 */ MCD_OPC_CheckPredicate, + 0, + 88, + 11, + 0, // Skip to: 8381 + /* 5477 */ MCD_OPC_Decode, + 245, + 6, + 55, // Opcode: LDRT_POST_REG + /* 5481 */ MCD_OPC_FilterValue, + 1, + 79, + 11, + 0, // Skip to: 8381 + /* 5486 */ MCD_OPC_CheckPredicate, + 0, + 74, + 11, + 0, // Skip to: 8381 + /* 5491 */ MCD_OPC_Decode, + 249, + 6, + 74, // Opcode: LDR_PRE_REG + /* 5495 */ MCD_OPC_FilterValue, + 1, + 65, + 11, + 0, // Skip to: 8381 + /* 5500 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 5503 */ MCD_OPC_FilterValue, + 0, + 11, + 1, + 0, // Skip to: 5775 + /* 5508 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 5511 */ MCD_OPC_FilterValue, + 0, + 39, + 0, + 0, // Skip to: 5555 + /* 5516 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5519 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 5537 + /* 5524 */ MCD_OPC_CheckPredicate, + 0, + 36, + 11, + 0, // Skip to: 8381 + /* 5529 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5533 */ MCD_OPC_Decode, + 248, + 13, + 66, // Opcode: QADD16 + /* 5537 */ MCD_OPC_FilterValue, + 1, + 23, + 11, + 0, // Skip to: 8381 + /* 5542 */ MCD_OPC_CheckPredicate, + 0, + 18, + 11, + 0, // Skip to: 8381 + /* 5547 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5551 */ MCD_OPC_Decode, + 172, + 14, + 66, // Opcode: SHADD16 + /* 5555 */ MCD_OPC_FilterValue, + 1, + 39, + 0, + 0, // Skip to: 5599 + /* 5560 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5563 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 5581 + /* 5568 */ MCD_OPC_CheckPredicate, + 0, + 248, + 10, + 0, // Skip to: 8381 + /* 5573 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5577 */ MCD_OPC_Decode, + 250, + 13, + 66, // Opcode: QASX + /* 5581 */ MCD_OPC_FilterValue, + 1, + 235, + 10, + 0, // Skip to: 8381 + /* 5586 */ MCD_OPC_CheckPredicate, + 0, + 230, + 10, + 0, // Skip to: 8381 + /* 5591 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5595 */ MCD_OPC_Decode, + 174, + 14, + 66, // Opcode: SHASX + /* 5599 */ MCD_OPC_FilterValue, + 2, + 39, + 0, + 0, // Skip to: 5643 + /* 5604 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5607 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 5625 + /* 5612 */ MCD_OPC_CheckPredicate, + 0, + 204, + 10, + 0, // Skip to: 8381 + /* 5617 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5621 */ MCD_OPC_Decode, + 253, + 13, + 66, // Opcode: QSAX + /* 5625 */ MCD_OPC_FilterValue, + 1, + 191, + 10, + 0, // Skip to: 8381 + /* 5630 */ MCD_OPC_CheckPredicate, + 0, + 186, + 10, + 0, // Skip to: 8381 + /* 5635 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5639 */ MCD_OPC_Decode, + 175, + 14, + 66, // Opcode: SHSAX + /* 5643 */ MCD_OPC_FilterValue, + 3, + 39, + 0, + 0, // Skip to: 5687 + /* 5648 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5651 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 5669 + /* 5656 */ MCD_OPC_CheckPredicate, + 0, + 160, + 10, + 0, // Skip to: 8381 + /* 5661 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5665 */ MCD_OPC_Decode, + 255, + 13, + 66, // Opcode: QSUB16 + /* 5669 */ MCD_OPC_FilterValue, + 1, + 147, + 10, + 0, // Skip to: 8381 + /* 5674 */ MCD_OPC_CheckPredicate, + 0, + 142, + 10, + 0, // Skip to: 8381 + /* 5679 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5683 */ MCD_OPC_Decode, + 176, + 14, + 66, // Opcode: SHSUB16 + /* 5687 */ MCD_OPC_FilterValue, + 4, + 39, + 0, + 0, // Skip to: 5731 + /* 5692 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5695 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 5713 + /* 5700 */ MCD_OPC_CheckPredicate, + 0, + 116, + 10, + 0, // Skip to: 8381 + /* 5705 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5709 */ MCD_OPC_Decode, + 249, + 13, + 66, // Opcode: QADD8 + /* 5713 */ MCD_OPC_FilterValue, + 1, + 103, + 10, + 0, // Skip to: 8381 + /* 5718 */ MCD_OPC_CheckPredicate, + 0, + 98, + 10, + 0, // Skip to: 8381 + /* 5723 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5727 */ MCD_OPC_Decode, + 173, + 14, + 66, // Opcode: SHADD8 + /* 5731 */ MCD_OPC_FilterValue, + 7, + 85, + 10, + 0, // Skip to: 8381 + /* 5736 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5739 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 5757 + /* 5744 */ MCD_OPC_CheckPredicate, + 0, + 72, + 10, + 0, // Skip to: 8381 + /* 5749 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5753 */ MCD_OPC_Decode, + 128, + 14, + 66, // Opcode: QSUB8 + /* 5757 */ MCD_OPC_FilterValue, + 1, + 59, + 10, + 0, // Skip to: 8381 + /* 5762 */ MCD_OPC_CheckPredicate, + 0, + 54, + 10, + 0, // Skip to: 8381 + /* 5767 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5771 */ MCD_OPC_Decode, + 177, + 14, + 66, // Opcode: SHSUB8 + /* 5775 */ MCD_OPC_FilterValue, + 1, + 194, + 0, + 0, // Skip to: 5974 + /* 5780 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 5783 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5797 + /* 5788 */ MCD_OPC_CheckPredicate, + 1, + 28, + 10, + 0, // Skip to: 8381 + /* 5793 */ MCD_OPC_Decode, + 223, + 14, + 75, // Opcode: SSAT + /* 5797 */ MCD_OPC_FilterValue, + 1, + 19, + 10, + 0, // Skip to: 8381 + /* 5802 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 5805 */ MCD_OPC_FilterValue, + 0, + 52, + 0, + 0, // Skip to: 5862 + /* 5810 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5813 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 5834 + /* 5818 */ MCD_OPC_CheckPredicate, + 1, + 254, + 9, + 0, // Skip to: 8381 + /* 5823 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 247, + 9, + 0, // Skip to: 8381 + /* 5830 */ MCD_OPC_Decode, + 224, + 14, + 76, // Opcode: SSAT16 + /* 5834 */ MCD_OPC_FilterValue, + 1, + 238, + 9, + 0, // Skip to: 8381 + /* 5839 */ MCD_OPC_CheckPredicate, + 1, + 233, + 9, + 0, // Skip to: 8381 + /* 5844 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 226, + 9, + 0, // Skip to: 8381 + /* 5851 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 219, + 9, + 0, // Skip to: 8381 + /* 5858 */ MCD_OPC_Decode, + 130, + 14, + 35, // Opcode: REV + /* 5862 */ MCD_OPC_FilterValue, + 1, + 79, + 0, + 0, // Skip to: 5946 + /* 5867 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5870 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 5908 + /* 5875 */ MCD_OPC_CheckPredicate, + 1, + 15, + 0, + 0, // Skip to: 5895 + /* 5880 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 8, + 0, + 0, // Skip to: 5895 + /* 5887 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 5891 */ MCD_OPC_Decode, + 169, + 15, + 71, // Opcode: SXTB + /* 5895 */ MCD_OPC_CheckPredicate, + 1, + 177, + 9, + 0, // Skip to: 8381 + /* 5900 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 5904 */ MCD_OPC_Decode, + 166, + 15, + 72, // Opcode: SXTAB + /* 5908 */ MCD_OPC_FilterValue, + 1, + 164, + 9, + 0, // Skip to: 8381 + /* 5913 */ MCD_OPC_CheckPredicate, + 1, + 15, + 0, + 0, // Skip to: 5933 + /* 5918 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 8, + 0, + 0, // Skip to: 5933 + /* 5925 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 5929 */ MCD_OPC_Decode, + 171, + 15, + 71, // Opcode: SXTH + /* 5933 */ MCD_OPC_CheckPredicate, + 1, + 139, + 9, + 0, // Skip to: 8381 + /* 5938 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 5942 */ MCD_OPC_Decode, + 168, + 15, + 72, // Opcode: SXTAH + /* 5946 */ MCD_OPC_FilterValue, + 2, + 126, + 9, + 0, // Skip to: 8381 + /* 5951 */ MCD_OPC_CheckPredicate, + 1, + 121, + 9, + 0, // Skip to: 8381 + /* 5956 */ MCD_OPC_CheckField, + 16, + 5, + 31, + 114, + 9, + 0, // Skip to: 8381 + /* 5963 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 107, + 9, + 0, // Skip to: 8381 + /* 5970 */ MCD_OPC_Decode, + 131, + 14, + 35, // Opcode: REV16 + /* 5974 */ MCD_OPC_FilterValue, + 2, + 30, + 0, + 0, // Skip to: 6009 + /* 5979 */ MCD_OPC_CheckPredicate, + 20, + 93, + 9, + 0, // Skip to: 8381 + /* 5984 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 86, + 9, + 0, // Skip to: 8381 + /* 5991 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 79, + 9, + 0, // Skip to: 8381 + /* 5998 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 72, + 9, + 0, // Skip to: 8381 + /* 6005 */ MCD_OPC_Decode, + 188, + 15, + 30, // Opcode: UDIV + /* 6009 */ MCD_OPC_FilterValue, + 3, + 63, + 9, + 0, // Skip to: 8381 + /* 6014 */ MCD_OPC_CheckPredicate, + 13, + 58, + 9, + 0, // Skip to: 8381 + /* 6019 */ MCD_OPC_CheckField, + 5, + 2, + 2, + 51, + 9, + 0, // Skip to: 8381 + /* 6026 */ MCD_OPC_Decode, + 157, + 14, + 77, // Opcode: SBFX + /* 6030 */ MCD_OPC_FilterValue, + 2, + 155, + 2, + 0, // Skip to: 6702 + /* 6035 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 6038 */ MCD_OPC_FilterValue, + 0, + 121, + 0, + 0, // Skip to: 6164 + /* 6043 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6046 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 6082 + /* 6051 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 6054 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6068 + /* 6059 */ MCD_OPC_CheckPredicate, + 0, + 13, + 9, + 0, // Skip to: 8381 + /* 6064 */ MCD_OPC_Decode, + 134, + 15, + 55, // Opcode: STRB_POST_REG + /* 6068 */ MCD_OPC_FilterValue, + 1, + 4, + 9, + 0, // Skip to: 8381 + /* 6073 */ MCD_OPC_CheckPredicate, + 0, + 255, + 8, + 0, // Skip to: 8381 + /* 6078 */ MCD_OPC_Decode, + 138, + 15, + 78, // Opcode: STRBrs + /* 6082 */ MCD_OPC_FilterValue, + 1, + 246, + 8, + 0, // Skip to: 8381 + /* 6087 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 6090 */ MCD_OPC_FilterValue, + 0, + 32, + 0, + 0, // Skip to: 6127 + /* 6095 */ MCD_OPC_CheckPredicate, + 15, + 18, + 0, + 0, // Skip to: 6118 + /* 6100 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 6118 + /* 6107 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 6118 + /* 6114 */ MCD_OPC_Decode, + 246, + 13, + 65, // Opcode: PLIrs + /* 6118 */ MCD_OPC_CheckPredicate, + 0, + 210, + 8, + 0, // Skip to: 8381 + /* 6123 */ MCD_OPC_Decode, + 217, + 6, + 55, // Opcode: LDRB_POST_REG + /* 6127 */ MCD_OPC_FilterValue, + 1, + 201, + 8, + 0, // Skip to: 8381 + /* 6132 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 6155 + /* 6137 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 6155 + /* 6144 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 6155 + /* 6151 */ MCD_OPC_Decode, + 244, + 13, + 65, // Opcode: PLDrs + /* 6155 */ MCD_OPC_CheckPredicate, + 0, + 173, + 8, + 0, // Skip to: 8381 + /* 6160 */ MCD_OPC_Decode, + 221, + 6, + 78, // Opcode: LDRBrs + /* 6164 */ MCD_OPC_FilterValue, + 1, + 164, + 8, + 0, // Skip to: 8381 + /* 6169 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 6172 */ MCD_OPC_FilterValue, + 0, + 158, + 0, + 0, // Skip to: 6335 + /* 6177 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 6180 */ MCD_OPC_FilterValue, + 0, + 53, + 0, + 0, // Skip to: 6238 + /* 6185 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6188 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 6213 + /* 6193 */ MCD_OPC_CheckPredicate, + 0, + 135, + 8, + 0, // Skip to: 8381 + /* 6198 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 128, + 8, + 0, // Skip to: 8381 + /* 6205 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6209 */ MCD_OPC_Decode, + 183, + 15, + 66, // Opcode: UADD16 + /* 6213 */ MCD_OPC_FilterValue, + 1, + 115, + 8, + 0, // Skip to: 8381 + /* 6218 */ MCD_OPC_CheckPredicate, + 0, + 110, + 8, + 0, // Skip to: 8381 + /* 6223 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 103, + 8, + 0, // Skip to: 8381 + /* 6230 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6234 */ MCD_OPC_Decode, + 184, + 15, + 66, // Opcode: UADD8 + /* 6238 */ MCD_OPC_FilterValue, + 2, + 62, + 0, + 0, // Skip to: 6305 + /* 6243 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6246 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 6267 + /* 6251 */ MCD_OPC_CheckPredicate, + 1, + 77, + 8, + 0, // Skip to: 8381 + /* 6256 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 70, + 8, + 0, // Skip to: 8381 + /* 6263 */ MCD_OPC_Decode, + 186, + 14, + 19, // Opcode: SMLALD + /* 6267 */ MCD_OPC_FilterValue, + 1, + 61, + 8, + 0, // Skip to: 8381 + /* 6272 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6275 */ MCD_OPC_FilterValue, + 0, + 53, + 8, + 0, // Skip to: 8381 + /* 6280 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 6296 + /* 6285 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 6296 + /* 6292 */ MCD_OPC_Decode, + 202, + 14, + 30, // Opcode: SMMUL + /* 6296 */ MCD_OPC_CheckPredicate, + 1, + 32, + 8, + 0, // Skip to: 8381 + /* 6301 */ MCD_OPC_Decode, + 198, + 14, + 39, // Opcode: SMMLA + /* 6305 */ MCD_OPC_FilterValue, + 3, + 23, + 8, + 0, // Skip to: 8381 + /* 6310 */ MCD_OPC_CheckPredicate, + 13, + 11, + 0, + 0, // Skip to: 6326 + /* 6315 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 4, + 0, + 0, // Skip to: 6326 + /* 6322 */ MCD_OPC_Decode, + 221, + 5, + 79, // Opcode: BFC + /* 6326 */ MCD_OPC_CheckPredicate, + 13, + 2, + 8, + 0, // Skip to: 8381 + /* 6331 */ MCD_OPC_Decode, + 222, + 5, + 80, // Opcode: BFI + /* 6335 */ MCD_OPC_FilterValue, + 1, + 102, + 0, + 0, // Skip to: 6442 + /* 6340 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6343 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 6371 + /* 6348 */ MCD_OPC_CheckPredicate, + 1, + 236, + 7, + 0, // Skip to: 8381 + /* 6353 */ MCD_OPC_CheckField, + 23, + 2, + 2, + 229, + 7, + 0, // Skip to: 8381 + /* 6360 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 222, + 7, + 0, // Skip to: 8381 + /* 6367 */ MCD_OPC_Decode, + 187, + 14, + 19, // Opcode: SMLALDX + /* 6371 */ MCD_OPC_FilterValue, + 1, + 213, + 7, + 0, // Skip to: 8381 + /* 6376 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 6379 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 6404 + /* 6384 */ MCD_OPC_CheckPredicate, + 0, + 200, + 7, + 0, // Skip to: 8381 + /* 6389 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 193, + 7, + 0, // Skip to: 8381 + /* 6396 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6400 */ MCD_OPC_Decode, + 185, + 15, + 66, // Opcode: UASX + /* 6404 */ MCD_OPC_FilterValue, + 2, + 180, + 7, + 0, // Skip to: 8381 + /* 6409 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6412 */ MCD_OPC_FilterValue, + 0, + 172, + 7, + 0, // Skip to: 8381 + /* 6417 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 6433 + /* 6422 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 6433 + /* 6429 */ MCD_OPC_Decode, + 203, + 14, + 30, // Opcode: SMMULR + /* 6433 */ MCD_OPC_CheckPredicate, + 1, + 151, + 7, + 0, // Skip to: 8381 + /* 6438 */ MCD_OPC_Decode, + 199, + 14, + 39, // Opcode: SMMLAR + /* 6442 */ MCD_OPC_FilterValue, + 2, + 85, + 0, + 0, // Skip to: 6532 + /* 6447 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6450 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 6504 + /* 6455 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6458 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 6479 + /* 6463 */ MCD_OPC_CheckPredicate, + 1, + 121, + 7, + 0, // Skip to: 8381 + /* 6468 */ MCD_OPC_CheckField, + 23, + 2, + 2, + 114, + 7, + 0, // Skip to: 8381 + /* 6475 */ MCD_OPC_Decode, + 196, + 14, + 19, // Opcode: SMLSLD + /* 6479 */ MCD_OPC_FilterValue, + 1, + 105, + 7, + 0, // Skip to: 8381 + /* 6484 */ MCD_OPC_CheckPredicate, + 0, + 100, + 7, + 0, // Skip to: 8381 + /* 6489 */ MCD_OPC_CheckField, + 23, + 2, + 0, + 93, + 7, + 0, // Skip to: 8381 + /* 6496 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6500 */ MCD_OPC_Decode, + 208, + 15, + 66, // Opcode: USAX + /* 6504 */ MCD_OPC_FilterValue, + 1, + 80, + 7, + 0, // Skip to: 8381 + /* 6509 */ MCD_OPC_CheckPredicate, + 1, + 75, + 7, + 0, // Skip to: 8381 + /* 6514 */ MCD_OPC_CheckField, + 23, + 2, + 2, + 68, + 7, + 0, // Skip to: 8381 + /* 6521 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 61, + 7, + 0, // Skip to: 8381 + /* 6528 */ MCD_OPC_Decode, + 200, + 14, + 39, // Opcode: SMMLS + /* 6532 */ MCD_OPC_FilterValue, + 3, + 52, + 7, + 0, // Skip to: 8381 + /* 6537 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 6540 */ MCD_OPC_FilterValue, + 0, + 53, + 0, + 0, // Skip to: 6598 + /* 6545 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6548 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 6573 + /* 6553 */ MCD_OPC_CheckPredicate, + 0, + 31, + 7, + 0, // Skip to: 8381 + /* 6558 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 24, + 7, + 0, // Skip to: 8381 + /* 6565 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6569 */ MCD_OPC_Decode, + 209, + 15, + 66, // Opcode: USUB16 + /* 6573 */ MCD_OPC_FilterValue, + 1, + 11, + 7, + 0, // Skip to: 8381 + /* 6578 */ MCD_OPC_CheckPredicate, + 0, + 6, + 7, + 0, // Skip to: 8381 + /* 6583 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 255, + 6, + 0, // Skip to: 8381 + /* 6590 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6594 */ MCD_OPC_Decode, + 210, + 15, + 66, // Opcode: USUB8 + /* 6598 */ MCD_OPC_FilterValue, + 1, + 49, + 0, + 0, // Skip to: 6652 + /* 6603 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6606 */ MCD_OPC_FilterValue, + 0, + 234, + 6, + 0, // Skip to: 8381 + /* 6611 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6614 */ MCD_OPC_FilterValue, + 0, + 226, + 6, + 0, // Skip to: 8381 + /* 6619 */ MCD_OPC_CheckPredicate, + 1, + 15, + 0, + 0, // Skip to: 6639 + /* 6624 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 8, + 0, + 0, // Skip to: 6639 + /* 6631 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 6635 */ MCD_OPC_Decode, + 215, + 15, + 71, // Opcode: UXTB16 + /* 6639 */ MCD_OPC_CheckPredicate, + 1, + 201, + 6, + 0, // Skip to: 8381 + /* 6644 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 6648 */ MCD_OPC_Decode, + 212, + 15, + 72, // Opcode: UXTAB16 + /* 6652 */ MCD_OPC_FilterValue, + 2, + 188, + 6, + 0, // Skip to: 8381 + /* 6657 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6660 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 6681 + /* 6665 */ MCD_OPC_CheckPredicate, + 1, + 175, + 6, + 0, // Skip to: 8381 + /* 6670 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 168, + 6, + 0, // Skip to: 8381 + /* 6677 */ MCD_OPC_Decode, + 197, + 14, + 19, // Opcode: SMLSLDX + /* 6681 */ MCD_OPC_FilterValue, + 1, + 159, + 6, + 0, // Skip to: 8381 + /* 6686 */ MCD_OPC_CheckPredicate, + 1, + 154, + 6, + 0, // Skip to: 8381 + /* 6691 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 147, + 6, + 0, // Skip to: 8381 + /* 6698 */ MCD_OPC_Decode, + 201, + 14, + 39, // Opcode: SMMLSR + /* 6702 */ MCD_OPC_FilterValue, + 3, + 138, + 6, + 0, // Skip to: 8381 + /* 6707 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 6710 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 6790 + /* 6715 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6718 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 6754 + /* 6723 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 6726 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6740 + /* 6731 */ MCD_OPC_CheckPredicate, + 0, + 109, + 6, + 0, // Skip to: 8381 + /* 6736 */ MCD_OPC_Decode, + 132, + 15, + 55, // Opcode: STRBT_POST_REG + /* 6740 */ MCD_OPC_FilterValue, + 1, + 100, + 6, + 0, // Skip to: 8381 + /* 6745 */ MCD_OPC_CheckPredicate, + 0, + 95, + 6, + 0, // Skip to: 8381 + /* 6750 */ MCD_OPC_Decode, + 136, + 15, + 73, // Opcode: STRB_PRE_REG + /* 6754 */ MCD_OPC_FilterValue, + 1, + 86, + 6, + 0, // Skip to: 8381 + /* 6759 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 6762 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6776 + /* 6767 */ MCD_OPC_CheckPredicate, + 0, + 73, + 6, + 0, // Skip to: 8381 + /* 6772 */ MCD_OPC_Decode, + 215, + 6, + 55, // Opcode: LDRBT_POST_REG + /* 6776 */ MCD_OPC_FilterValue, + 1, + 64, + 6, + 0, // Skip to: 8381 + /* 6781 */ MCD_OPC_CheckPredicate, + 0, + 59, + 6, + 0, // Skip to: 8381 + /* 6786 */ MCD_OPC_Decode, + 219, + 6, + 74, // Opcode: LDRB_PRE_REG + /* 6790 */ MCD_OPC_FilterValue, + 1, + 50, + 6, + 0, // Skip to: 8381 + /* 6795 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 6798 */ MCD_OPC_FilterValue, + 0, + 11, + 1, + 0, // Skip to: 7070 + /* 6803 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 6806 */ MCD_OPC_FilterValue, + 0, + 39, + 0, + 0, // Skip to: 6850 + /* 6811 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6814 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 6832 + /* 6819 */ MCD_OPC_CheckPredicate, + 0, + 21, + 6, + 0, // Skip to: 8381 + /* 6824 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6828 */ MCD_OPC_Decode, + 198, + 15, + 66, // Opcode: UQADD16 + /* 6832 */ MCD_OPC_FilterValue, + 1, + 8, + 6, + 0, // Skip to: 8381 + /* 6837 */ MCD_OPC_CheckPredicate, + 0, + 3, + 6, + 0, // Skip to: 8381 + /* 6842 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6846 */ MCD_OPC_Decode, + 189, + 15, + 66, // Opcode: UHADD16 + /* 6850 */ MCD_OPC_FilterValue, + 1, + 39, + 0, + 0, // Skip to: 6894 + /* 6855 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6858 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 6876 + /* 6863 */ MCD_OPC_CheckPredicate, + 0, + 233, + 5, + 0, // Skip to: 8381 + /* 6868 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6872 */ MCD_OPC_Decode, + 200, + 15, + 66, // Opcode: UQASX + /* 6876 */ MCD_OPC_FilterValue, + 1, + 220, + 5, + 0, // Skip to: 8381 + /* 6881 */ MCD_OPC_CheckPredicate, + 0, + 215, + 5, + 0, // Skip to: 8381 + /* 6886 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6890 */ MCD_OPC_Decode, + 191, + 15, + 66, // Opcode: UHASX + /* 6894 */ MCD_OPC_FilterValue, + 2, + 39, + 0, + 0, // Skip to: 6938 + /* 6899 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6902 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 6920 + /* 6907 */ MCD_OPC_CheckPredicate, + 0, + 189, + 5, + 0, // Skip to: 8381 + /* 6912 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6916 */ MCD_OPC_Decode, + 201, + 15, + 66, // Opcode: UQSAX + /* 6920 */ MCD_OPC_FilterValue, + 1, + 176, + 5, + 0, // Skip to: 8381 + /* 6925 */ MCD_OPC_CheckPredicate, + 0, + 171, + 5, + 0, // Skip to: 8381 + /* 6930 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6934 */ MCD_OPC_Decode, + 192, + 15, + 66, // Opcode: UHSAX + /* 6938 */ MCD_OPC_FilterValue, + 3, + 39, + 0, + 0, // Skip to: 6982 + /* 6943 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6946 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 6964 + /* 6951 */ MCD_OPC_CheckPredicate, + 0, + 145, + 5, + 0, // Skip to: 8381 + /* 6956 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6960 */ MCD_OPC_Decode, + 202, + 15, + 66, // Opcode: UQSUB16 + /* 6964 */ MCD_OPC_FilterValue, + 1, + 132, + 5, + 0, // Skip to: 8381 + /* 6969 */ MCD_OPC_CheckPredicate, + 0, + 127, + 5, + 0, // Skip to: 8381 + /* 6974 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6978 */ MCD_OPC_Decode, + 193, + 15, + 66, // Opcode: UHSUB16 + /* 6982 */ MCD_OPC_FilterValue, + 4, + 39, + 0, + 0, // Skip to: 7026 + /* 6987 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6990 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 7008 + /* 6995 */ MCD_OPC_CheckPredicate, + 0, + 101, + 5, + 0, // Skip to: 8381 + /* 7000 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 7004 */ MCD_OPC_Decode, + 199, + 15, + 66, // Opcode: UQADD8 + /* 7008 */ MCD_OPC_FilterValue, + 1, + 88, + 5, + 0, // Skip to: 8381 + /* 7013 */ MCD_OPC_CheckPredicate, + 0, + 83, + 5, + 0, // Skip to: 8381 + /* 7018 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 7022 */ MCD_OPC_Decode, + 190, + 15, + 66, // Opcode: UHADD8 + /* 7026 */ MCD_OPC_FilterValue, + 7, + 70, + 5, + 0, // Skip to: 8381 + /* 7031 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7034 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 7052 + /* 7039 */ MCD_OPC_CheckPredicate, + 0, + 57, + 5, + 0, // Skip to: 8381 + /* 7044 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 7048 */ MCD_OPC_Decode, + 203, + 15, + 66, // Opcode: UQSUB8 + /* 7052 */ MCD_OPC_FilterValue, + 1, + 44, + 5, + 0, // Skip to: 8381 + /* 7057 */ MCD_OPC_CheckPredicate, + 0, + 39, + 5, + 0, // Skip to: 8381 + /* 7062 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 7066 */ MCD_OPC_Decode, + 194, + 15, + 66, // Opcode: UHSUB8 + /* 7070 */ MCD_OPC_FilterValue, + 1, + 194, + 0, + 0, // Skip to: 7269 + /* 7075 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 7078 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7092 + /* 7083 */ MCD_OPC_CheckPredicate, + 1, + 13, + 5, + 0, // Skip to: 8381 + /* 7088 */ MCD_OPC_Decode, + 206, + 15, + 75, // Opcode: USAT + /* 7092 */ MCD_OPC_FilterValue, + 1, + 4, + 5, + 0, // Skip to: 8381 + /* 7097 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7100 */ MCD_OPC_FilterValue, + 0, + 52, + 0, + 0, // Skip to: 7157 + /* 7105 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7108 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 7129 + /* 7113 */ MCD_OPC_CheckPredicate, + 1, + 239, + 4, + 0, // Skip to: 8381 + /* 7118 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 232, + 4, + 0, // Skip to: 8381 + /* 7125 */ MCD_OPC_Decode, + 207, + 15, + 76, // Opcode: USAT16 + /* 7129 */ MCD_OPC_FilterValue, + 1, + 223, + 4, + 0, // Skip to: 8381 + /* 7134 */ MCD_OPC_CheckPredicate, + 13, + 218, + 4, + 0, // Skip to: 8381 + /* 7139 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 211, + 4, + 0, // Skip to: 8381 + /* 7146 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 204, + 4, + 0, // Skip to: 8381 + /* 7153 */ MCD_OPC_Decode, + 129, + 14, + 35, // Opcode: RBIT + /* 7157 */ MCD_OPC_FilterValue, + 1, + 79, + 0, + 0, // Skip to: 7241 + /* 7162 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7165 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 7203 + /* 7170 */ MCD_OPC_CheckPredicate, + 1, + 15, + 0, + 0, // Skip to: 7190 + /* 7175 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 8, + 0, + 0, // Skip to: 7190 + /* 7182 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 7186 */ MCD_OPC_Decode, + 214, + 15, + 71, // Opcode: UXTB + /* 7190 */ MCD_OPC_CheckPredicate, + 1, + 162, + 4, + 0, // Skip to: 8381 + /* 7195 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 7199 */ MCD_OPC_Decode, + 211, + 15, + 72, // Opcode: UXTAB + /* 7203 */ MCD_OPC_FilterValue, + 1, + 149, + 4, + 0, // Skip to: 8381 + /* 7208 */ MCD_OPC_CheckPredicate, + 1, + 15, + 0, + 0, // Skip to: 7228 + /* 7213 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 8, + 0, + 0, // Skip to: 7228 + /* 7220 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 7224 */ MCD_OPC_Decode, + 216, + 15, + 71, // Opcode: UXTH + /* 7228 */ MCD_OPC_CheckPredicate, + 1, + 124, + 4, + 0, // Skip to: 8381 + /* 7233 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 7237 */ MCD_OPC_Decode, + 213, + 15, + 72, // Opcode: UXTAH + /* 7241 */ MCD_OPC_FilterValue, + 2, + 111, + 4, + 0, // Skip to: 8381 + /* 7246 */ MCD_OPC_CheckPredicate, + 1, + 106, + 4, + 0, // Skip to: 8381 + /* 7251 */ MCD_OPC_CheckField, + 16, + 5, + 31, + 99, + 4, + 0, // Skip to: 8381 + /* 7258 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 92, + 4, + 0, // Skip to: 8381 + /* 7265 */ MCD_OPC_Decode, + 132, + 14, + 35, // Opcode: REVSH + /* 7269 */ MCD_OPC_FilterValue, + 3, + 83, + 4, + 0, // Skip to: 8381 + /* 7274 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 7277 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7291 + /* 7282 */ MCD_OPC_CheckPredicate, + 13, + 70, + 4, + 0, // Skip to: 8381 + /* 7287 */ MCD_OPC_Decode, + 186, + 15, + 77, // Opcode: UBFX + /* 7291 */ MCD_OPC_FilterValue, + 3, + 61, + 4, + 0, // Skip to: 8381 + /* 7296 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 7299 */ MCD_OPC_FilterValue, + 1, + 53, + 4, + 0, // Skip to: 8381 + /* 7304 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7307 */ MCD_OPC_FilterValue, + 1, + 45, + 4, + 0, // Skip to: 8381 + /* 7312 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7315 */ MCD_OPC_FilterValue, + 14, + 37, + 4, + 0, // Skip to: 8381 + /* 7320 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 7323 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7345 + /* 7328 */ MCD_OPC_CheckPredicate, + 21, + 34, + 0, + 0, // Skip to: 7367 + /* 7333 */ MCD_OPC_CheckField, + 8, + 12, + 222, + 29, + 26, + 0, + 0, // Skip to: 7367 + /* 7341 */ MCD_OPC_Decode, + 177, + 15, + 61, // Opcode: TRAPNaCl + /* 7345 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7367 + /* 7350 */ MCD_OPC_CheckPredicate, + 0, + 12, + 0, + 0, // Skip to: 7367 + /* 7355 */ MCD_OPC_CheckField, + 8, + 12, + 222, + 31, + 4, + 0, + 0, // Skip to: 7367 + /* 7363 */ MCD_OPC_Decode, + 176, + 15, + 61, // Opcode: TRAP + /* 7367 */ MCD_OPC_CheckPredicate, + 0, + 241, + 3, + 0, // Skip to: 8381 + /* 7372 */ MCD_OPC_Decode, + 187, + 15, + 15, // Opcode: UDF + /* 7376 */ MCD_OPC_FilterValue, + 4, + 75, + 3, + 0, // Skip to: 8224 + /* 7381 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 7384 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7398 + /* 7389 */ MCD_OPC_CheckPredicate, + 0, + 219, + 3, + 0, // Skip to: 8381 + /* 7394 */ MCD_OPC_Decode, + 251, + 14, + 81, // Opcode: STMDA + /* 7398 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 7436 + /* 7403 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 7427 + /* 7408 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 7427 + /* 7415 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 7427 + /* 7423 */ MCD_OPC_Decode, + 133, + 14, + 82, // Opcode: RFEDA + /* 7427 */ MCD_OPC_CheckPredicate, + 0, + 181, + 3, + 0, // Skip to: 8381 + /* 7432 */ MCD_OPC_Decode, + 206, + 6, + 81, // Opcode: LDMDA + /* 7436 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7450 + /* 7441 */ MCD_OPC_CheckPredicate, + 0, + 167, + 3, + 0, // Skip to: 8381 + /* 7446 */ MCD_OPC_Decode, + 252, + 14, + 83, // Opcode: STMDA_UPD + /* 7450 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 7488 + /* 7455 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 7479 + /* 7460 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 7479 + /* 7467 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 7479 + /* 7475 */ MCD_OPC_Decode, + 134, + 14, + 84, // Opcode: RFEDA_UPD + /* 7479 */ MCD_OPC_CheckPredicate, + 0, + 129, + 3, + 0, // Skip to: 8381 + /* 7484 */ MCD_OPC_Decode, + 207, + 6, + 83, // Opcode: LDMDA_UPD + /* 7488 */ MCD_OPC_FilterValue, + 4, + 34, + 0, + 0, // Skip to: 7527 + /* 7493 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 7518 + /* 7498 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 7518 + /* 7505 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 7518 + /* 7514 */ MCD_OPC_Decode, + 215, + 14, + 85, // Opcode: SRSDA + /* 7518 */ MCD_OPC_CheckPredicate, + 0, + 90, + 3, + 0, // Skip to: 8381 + /* 7523 */ MCD_OPC_Decode, + 221, + 30, + 81, // Opcode: sysSTMDA + /* 7527 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 7541 + /* 7532 */ MCD_OPC_CheckPredicate, + 0, + 76, + 3, + 0, // Skip to: 8381 + /* 7537 */ MCD_OPC_Decode, + 213, + 30, + 81, // Opcode: sysLDMDA + /* 7541 */ MCD_OPC_FilterValue, + 6, + 34, + 0, + 0, // Skip to: 7580 + /* 7546 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 7571 + /* 7551 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 7571 + /* 7558 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 7571 + /* 7567 */ MCD_OPC_Decode, + 216, + 14, + 85, // Opcode: SRSDA_UPD + /* 7571 */ MCD_OPC_CheckPredicate, + 0, + 37, + 3, + 0, // Skip to: 8381 + /* 7576 */ MCD_OPC_Decode, + 222, + 30, + 83, // Opcode: sysSTMDA_UPD + /* 7580 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 7594 + /* 7585 */ MCD_OPC_CheckPredicate, + 0, + 23, + 3, + 0, // Skip to: 8381 + /* 7590 */ MCD_OPC_Decode, + 214, + 30, + 83, // Opcode: sysLDMDA_UPD + /* 7594 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 7608 + /* 7599 */ MCD_OPC_CheckPredicate, + 0, + 9, + 3, + 0, // Skip to: 8381 + /* 7604 */ MCD_OPC_Decode, + 255, + 14, + 81, // Opcode: STMIA + /* 7608 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 7646 + /* 7613 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 7637 + /* 7618 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 7637 + /* 7625 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 7637 + /* 7633 */ MCD_OPC_Decode, + 137, + 14, + 82, // Opcode: RFEIA + /* 7637 */ MCD_OPC_CheckPredicate, + 0, + 227, + 2, + 0, // Skip to: 8381 + /* 7642 */ MCD_OPC_Decode, + 210, + 6, + 81, // Opcode: LDMIA + /* 7646 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 7660 + /* 7651 */ MCD_OPC_CheckPredicate, + 0, + 213, + 2, + 0, // Skip to: 8381 + /* 7656 */ MCD_OPC_Decode, + 128, + 15, + 83, // Opcode: STMIA_UPD + /* 7660 */ MCD_OPC_FilterValue, + 11, + 33, + 0, + 0, // Skip to: 7698 + /* 7665 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 7689 + /* 7670 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 7689 + /* 7677 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 7689 + /* 7685 */ MCD_OPC_Decode, + 138, + 14, + 84, // Opcode: RFEIA_UPD + /* 7689 */ MCD_OPC_CheckPredicate, + 0, + 175, + 2, + 0, // Skip to: 8381 + /* 7694 */ MCD_OPC_Decode, + 211, + 6, + 83, // Opcode: LDMIA_UPD + /* 7698 */ MCD_OPC_FilterValue, + 12, + 34, + 0, + 0, // Skip to: 7737 + /* 7703 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 7728 + /* 7708 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 7728 + /* 7715 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 7728 + /* 7724 */ MCD_OPC_Decode, + 219, + 14, + 85, // Opcode: SRSIA + /* 7728 */ MCD_OPC_CheckPredicate, + 0, + 136, + 2, + 0, // Skip to: 8381 + /* 7733 */ MCD_OPC_Decode, + 225, + 30, + 81, // Opcode: sysSTMIA + /* 7737 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 7751 + /* 7742 */ MCD_OPC_CheckPredicate, + 0, + 122, + 2, + 0, // Skip to: 8381 + /* 7747 */ MCD_OPC_Decode, + 217, + 30, + 81, // Opcode: sysLDMIA + /* 7751 */ MCD_OPC_FilterValue, + 14, + 34, + 0, + 0, // Skip to: 7790 + /* 7756 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 7781 + /* 7761 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 7781 + /* 7768 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 7781 + /* 7777 */ MCD_OPC_Decode, + 220, + 14, + 85, // Opcode: SRSIA_UPD + /* 7781 */ MCD_OPC_CheckPredicate, + 0, + 83, + 2, + 0, // Skip to: 8381 + /* 7786 */ MCD_OPC_Decode, + 226, + 30, + 83, // Opcode: sysSTMIA_UPD + /* 7790 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 7804 + /* 7795 */ MCD_OPC_CheckPredicate, + 0, + 69, + 2, + 0, // Skip to: 8381 + /* 7800 */ MCD_OPC_Decode, + 218, + 30, + 83, // Opcode: sysLDMIA_UPD + /* 7804 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 7818 + /* 7809 */ MCD_OPC_CheckPredicate, + 0, + 55, + 2, + 0, // Skip to: 8381 + /* 7814 */ MCD_OPC_Decode, + 253, + 14, + 81, // Opcode: STMDB + /* 7818 */ MCD_OPC_FilterValue, + 17, + 33, + 0, + 0, // Skip to: 7856 + /* 7823 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 7847 + /* 7828 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 7847 + /* 7835 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 7847 + /* 7843 */ MCD_OPC_Decode, + 135, + 14, + 82, // Opcode: RFEDB + /* 7847 */ MCD_OPC_CheckPredicate, + 0, + 17, + 2, + 0, // Skip to: 8381 + /* 7852 */ MCD_OPC_Decode, + 208, + 6, + 81, // Opcode: LDMDB + /* 7856 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 7870 + /* 7861 */ MCD_OPC_CheckPredicate, + 0, + 3, + 2, + 0, // Skip to: 8381 + /* 7866 */ MCD_OPC_Decode, + 254, + 14, + 83, // Opcode: STMDB_UPD + /* 7870 */ MCD_OPC_FilterValue, + 19, + 33, + 0, + 0, // Skip to: 7908 + /* 7875 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 7899 + /* 7880 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 7899 + /* 7887 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 7899 + /* 7895 */ MCD_OPC_Decode, + 136, + 14, + 84, // Opcode: RFEDB_UPD + /* 7899 */ MCD_OPC_CheckPredicate, + 0, + 221, + 1, + 0, // Skip to: 8381 + /* 7904 */ MCD_OPC_Decode, + 209, + 6, + 83, // Opcode: LDMDB_UPD + /* 7908 */ MCD_OPC_FilterValue, + 20, + 34, + 0, + 0, // Skip to: 7947 + /* 7913 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 7938 + /* 7918 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 7938 + /* 7925 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 7938 + /* 7934 */ MCD_OPC_Decode, + 217, + 14, + 85, // Opcode: SRSDB + /* 7938 */ MCD_OPC_CheckPredicate, + 0, + 182, + 1, + 0, // Skip to: 8381 + /* 7943 */ MCD_OPC_Decode, + 223, + 30, + 81, // Opcode: sysSTMDB + /* 7947 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 7961 + /* 7952 */ MCD_OPC_CheckPredicate, + 0, + 168, + 1, + 0, // Skip to: 8381 + /* 7957 */ MCD_OPC_Decode, + 215, + 30, + 81, // Opcode: sysLDMDB + /* 7961 */ MCD_OPC_FilterValue, + 22, + 34, + 0, + 0, // Skip to: 8000 + /* 7966 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 7991 + /* 7971 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 7991 + /* 7978 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 7991 + /* 7987 */ MCD_OPC_Decode, + 218, + 14, + 85, // Opcode: SRSDB_UPD + /* 7991 */ MCD_OPC_CheckPredicate, + 0, + 129, + 1, + 0, // Skip to: 8381 + /* 7996 */ MCD_OPC_Decode, + 224, + 30, + 83, // Opcode: sysSTMDB_UPD + /* 8000 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 8014 + /* 8005 */ MCD_OPC_CheckPredicate, + 0, + 115, + 1, + 0, // Skip to: 8381 + /* 8010 */ MCD_OPC_Decode, + 216, + 30, + 83, // Opcode: sysLDMDB_UPD + /* 8014 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 8028 + /* 8019 */ MCD_OPC_CheckPredicate, + 0, + 101, + 1, + 0, // Skip to: 8381 + /* 8024 */ MCD_OPC_Decode, + 129, + 15, + 81, // Opcode: STMIB + /* 8028 */ MCD_OPC_FilterValue, + 25, + 33, + 0, + 0, // Skip to: 8066 + /* 8033 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 8057 + /* 8038 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 8057 + /* 8045 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 8057 + /* 8053 */ MCD_OPC_Decode, + 139, + 14, + 82, // Opcode: RFEIB + /* 8057 */ MCD_OPC_CheckPredicate, + 0, + 63, + 1, + 0, // Skip to: 8381 + /* 8062 */ MCD_OPC_Decode, + 212, + 6, + 81, // Opcode: LDMIB + /* 8066 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 8080 + /* 8071 */ MCD_OPC_CheckPredicate, + 0, + 49, + 1, + 0, // Skip to: 8381 + /* 8076 */ MCD_OPC_Decode, + 130, + 15, + 83, // Opcode: STMIB_UPD + /* 8080 */ MCD_OPC_FilterValue, + 27, + 33, + 0, + 0, // Skip to: 8118 + /* 8085 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 8109 + /* 8090 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 8109 + /* 8097 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 8109 + /* 8105 */ MCD_OPC_Decode, + 140, + 14, + 84, // Opcode: RFEIB_UPD + /* 8109 */ MCD_OPC_CheckPredicate, + 0, + 11, + 1, + 0, // Skip to: 8381 + /* 8114 */ MCD_OPC_Decode, + 213, + 6, + 83, // Opcode: LDMIB_UPD + /* 8118 */ MCD_OPC_FilterValue, + 28, + 34, + 0, + 0, // Skip to: 8157 + /* 8123 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 8148 + /* 8128 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 8148 + /* 8135 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 8148 + /* 8144 */ MCD_OPC_Decode, + 221, + 14, + 85, // Opcode: SRSIB + /* 8148 */ MCD_OPC_CheckPredicate, + 0, + 228, + 0, + 0, // Skip to: 8381 + /* 8153 */ MCD_OPC_Decode, + 227, + 30, + 81, // Opcode: sysSTMIB + /* 8157 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 8171 + /* 8162 */ MCD_OPC_CheckPredicate, + 0, + 214, + 0, + 0, // Skip to: 8381 + /* 8167 */ MCD_OPC_Decode, + 219, + 30, + 81, // Opcode: sysLDMIB + /* 8171 */ MCD_OPC_FilterValue, + 30, + 34, + 0, + 0, // Skip to: 8210 + /* 8176 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 8201 + /* 8181 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 8201 + /* 8188 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 8201 + /* 8197 */ MCD_OPC_Decode, + 222, + 14, + 85, // Opcode: SRSIB_UPD + /* 8201 */ MCD_OPC_CheckPredicate, + 0, + 175, + 0, + 0, // Skip to: 8381 + /* 8206 */ MCD_OPC_Decode, + 228, + 30, + 83, // Opcode: sysSTMIB_UPD + /* 8210 */ MCD_OPC_FilterValue, + 31, + 166, + 0, + 0, // Skip to: 8381 + /* 8215 */ MCD_OPC_CheckPredicate, + 0, + 161, + 0, + 0, // Skip to: 8381 + /* 8220 */ MCD_OPC_Decode, + 220, + 30, + 83, // Opcode: sysLDMIB_UPD + /* 8224 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 8292 + /* 8229 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 8232 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8246 + /* 8237 */ MCD_OPC_CheckPredicate, + 0, + 34, + 0, + 0, // Skip to: 8276 + /* 8242 */ MCD_OPC_Decode, + 237, + 5, + 86, // Opcode: Bcc + /* 8246 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 8276 + /* 8251 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 8267 + /* 8256 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 4, + 0, + 0, // Skip to: 8267 + /* 8263 */ MCD_OPC_Decode, + 228, + 5, + 86, // Opcode: BL + /* 8267 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 8276 + /* 8272 */ MCD_OPC_Decode, + 232, + 5, + 86, // Opcode: BL_pred + /* 8276 */ MCD_OPC_CheckPredicate, + 11, + 100, + 0, + 0, // Skip to: 8381 + /* 8281 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 93, + 0, + 0, // Skip to: 8381 + /* 8288 */ MCD_OPC_Decode, + 231, + 5, + 87, // Opcode: BLXi + /* 8292 */ MCD_OPC_FilterValue, + 6, + 63, + 0, + 0, // Skip to: 8360 + /* 8297 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 8300 */ MCD_OPC_FilterValue, + 4, + 25, + 0, + 0, // Skip to: 8330 + /* 8305 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 8321 + /* 8310 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 8321 + /* 8317 */ MCD_OPC_Decode, + 128, + 7, + 88, // Opcode: MCRR2 + /* 8321 */ MCD_OPC_CheckPredicate, + 0, + 55, + 0, + 0, // Skip to: 8381 + /* 8326 */ MCD_OPC_Decode, + 255, + 6, + 89, // Opcode: MCRR + /* 8330 */ MCD_OPC_FilterValue, + 5, + 46, + 0, + 0, // Skip to: 8381 + /* 8335 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 8351 + /* 8340 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 8351 + /* 8347 */ MCD_OPC_Decode, + 142, + 7, + 88, // Opcode: MRRC2 + /* 8351 */ MCD_OPC_CheckPredicate, + 0, + 25, + 0, + 0, // Skip to: 8381 + /* 8356 */ MCD_OPC_Decode, + 141, + 7, + 90, // Opcode: MRRC + /* 8360 */ MCD_OPC_FilterValue, + 7, + 16, + 0, + 0, // Skip to: 8381 + /* 8365 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 8381 + /* 8370 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 4, + 0, + 0, // Skip to: 8381 + /* 8377 */ MCD_OPC_Decode, + 163, + 15, + 91, // Opcode: SVC + /* 8381 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableCoProc32[] = { + /* 0 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 3 */ MCD_OPC_FilterValue, + 12, + 19, + 1, + 0, // Skip to: 283 + /* 8 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 49 + /* 16 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 19 */ MCD_OPC_FilterValue, + 1, + 101, + 2, + 0, // Skip to: 637 + /* 24 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 40 + /* 29 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 40 + /* 36 */ MCD_OPC_Decode, + 233, + 14, + 92, // Opcode: STC2_OPTION + /* 40 */ MCD_OPC_CheckPredicate, + 0, + 80, + 2, + 0, // Skip to: 637 + /* 45 */ MCD_OPC_Decode, + 241, + 14, + 92, // Opcode: STC_OPTION + /* 49 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 87 + /* 54 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 57 */ MCD_OPC_FilterValue, + 1, + 63, + 2, + 0, // Skip to: 637 + /* 62 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 78 + /* 67 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 78 + /* 74 */ MCD_OPC_Decode, + 195, + 6, + 92, // Opcode: LDC2_OPTION + /* 78 */ MCD_OPC_CheckPredicate, + 0, + 42, + 2, + 0, // Skip to: 637 + /* 83 */ MCD_OPC_Decode, + 203, + 6, + 92, // Opcode: LDC_OPTION + /* 87 */ MCD_OPC_FilterValue, + 2, + 25, + 0, + 0, // Skip to: 117 + /* 92 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 108 + /* 97 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 108 + /* 104 */ MCD_OPC_Decode, + 234, + 14, + 92, // Opcode: STC2_POST + /* 108 */ MCD_OPC_CheckPredicate, + 0, + 12, + 2, + 0, // Skip to: 637 + /* 113 */ MCD_OPC_Decode, + 242, + 14, + 92, // Opcode: STC_POST + /* 117 */ MCD_OPC_FilterValue, + 3, + 25, + 0, + 0, // Skip to: 147 + /* 122 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 138 + /* 127 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 138 + /* 134 */ MCD_OPC_Decode, + 196, + 6, + 92, // Opcode: LDC2_POST + /* 138 */ MCD_OPC_CheckPredicate, + 0, + 238, + 1, + 0, // Skip to: 637 + /* 143 */ MCD_OPC_Decode, + 204, + 6, + 92, // Opcode: LDC_POST + /* 147 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 185 + /* 152 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 155 */ MCD_OPC_FilterValue, + 1, + 221, + 1, + 0, // Skip to: 637 + /* 160 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 176 + /* 165 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 176 + /* 172 */ MCD_OPC_Decode, + 229, + 14, + 92, // Opcode: STC2L_OPTION + /* 176 */ MCD_OPC_CheckPredicate, + 0, + 200, + 1, + 0, // Skip to: 637 + /* 181 */ MCD_OPC_Decode, + 237, + 14, + 92, // Opcode: STCL_OPTION + /* 185 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 223 + /* 190 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 193 */ MCD_OPC_FilterValue, + 1, + 183, + 1, + 0, // Skip to: 637 + /* 198 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 214 + /* 203 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 214 + /* 210 */ MCD_OPC_Decode, + 191, + 6, + 92, // Opcode: LDC2L_OPTION + /* 214 */ MCD_OPC_CheckPredicate, + 0, + 162, + 1, + 0, // Skip to: 637 + /* 219 */ MCD_OPC_Decode, + 199, + 6, + 92, // Opcode: LDCL_OPTION + /* 223 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 253 + /* 228 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 244 + /* 233 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 244 + /* 240 */ MCD_OPC_Decode, + 230, + 14, + 92, // Opcode: STC2L_POST + /* 244 */ MCD_OPC_CheckPredicate, + 0, + 132, + 1, + 0, // Skip to: 637 + /* 249 */ MCD_OPC_Decode, + 238, + 14, + 92, // Opcode: STCL_POST + /* 253 */ MCD_OPC_FilterValue, + 7, + 123, + 1, + 0, // Skip to: 637 + /* 258 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 274 + /* 263 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 274 + /* 270 */ MCD_OPC_Decode, + 192, + 6, + 92, // Opcode: LDC2L_POST + /* 274 */ MCD_OPC_CheckPredicate, + 0, + 102, + 1, + 0, // Skip to: 637 + /* 279 */ MCD_OPC_Decode, + 200, + 6, + 92, // Opcode: LDCL_POST + /* 283 */ MCD_OPC_FilterValue, + 13, + 243, + 0, + 0, // Skip to: 531 + /* 288 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 291 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 321 + /* 296 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 312 + /* 301 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 312 + /* 308 */ MCD_OPC_Decode, + 232, + 14, + 92, // Opcode: STC2_OFFSET + /* 312 */ MCD_OPC_CheckPredicate, + 0, + 64, + 1, + 0, // Skip to: 637 + /* 317 */ MCD_OPC_Decode, + 240, + 14, + 92, // Opcode: STC_OFFSET + /* 321 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 351 + /* 326 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 342 + /* 331 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 342 + /* 338 */ MCD_OPC_Decode, + 194, + 6, + 92, // Opcode: LDC2_OFFSET + /* 342 */ MCD_OPC_CheckPredicate, + 0, + 34, + 1, + 0, // Skip to: 637 + /* 347 */ MCD_OPC_Decode, + 202, + 6, + 92, // Opcode: LDC_OFFSET + /* 351 */ MCD_OPC_FilterValue, + 2, + 25, + 0, + 0, // Skip to: 381 + /* 356 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 372 + /* 361 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 372 + /* 368 */ MCD_OPC_Decode, + 235, + 14, + 92, // Opcode: STC2_PRE + /* 372 */ MCD_OPC_CheckPredicate, + 0, + 4, + 1, + 0, // Skip to: 637 + /* 377 */ MCD_OPC_Decode, + 243, + 14, + 92, // Opcode: STC_PRE + /* 381 */ MCD_OPC_FilterValue, + 3, + 25, + 0, + 0, // Skip to: 411 + /* 386 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 402 + /* 391 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 402 + /* 398 */ MCD_OPC_Decode, + 197, + 6, + 92, // Opcode: LDC2_PRE + /* 402 */ MCD_OPC_CheckPredicate, + 0, + 230, + 0, + 0, // Skip to: 637 + /* 407 */ MCD_OPC_Decode, + 205, + 6, + 92, // Opcode: LDC_PRE + /* 411 */ MCD_OPC_FilterValue, + 4, + 25, + 0, + 0, // Skip to: 441 + /* 416 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 432 + /* 421 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 432 + /* 428 */ MCD_OPC_Decode, + 228, + 14, + 92, // Opcode: STC2L_OFFSET + /* 432 */ MCD_OPC_CheckPredicate, + 0, + 200, + 0, + 0, // Skip to: 637 + /* 437 */ MCD_OPC_Decode, + 236, + 14, + 92, // Opcode: STCL_OFFSET + /* 441 */ MCD_OPC_FilterValue, + 5, + 25, + 0, + 0, // Skip to: 471 + /* 446 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 462 + /* 451 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 462 + /* 458 */ MCD_OPC_Decode, + 190, + 6, + 92, // Opcode: LDC2L_OFFSET + /* 462 */ MCD_OPC_CheckPredicate, + 0, + 170, + 0, + 0, // Skip to: 637 + /* 467 */ MCD_OPC_Decode, + 198, + 6, + 92, // Opcode: LDCL_OFFSET + /* 471 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 501 + /* 476 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 492 + /* 481 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 492 + /* 488 */ MCD_OPC_Decode, + 231, + 14, + 92, // Opcode: STC2L_PRE + /* 492 */ MCD_OPC_CheckPredicate, + 0, + 140, + 0, + 0, // Skip to: 637 + /* 497 */ MCD_OPC_Decode, + 239, + 14, + 92, // Opcode: STCL_PRE + /* 501 */ MCD_OPC_FilterValue, + 7, + 131, + 0, + 0, // Skip to: 637 + /* 506 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 522 + /* 511 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 522 + /* 518 */ MCD_OPC_Decode, + 193, + 6, + 92, // Opcode: LDC2L_PRE + /* 522 */ MCD_OPC_CheckPredicate, + 0, + 110, + 0, + 0, // Skip to: 637 + /* 527 */ MCD_OPC_Decode, + 201, + 6, + 92, // Opcode: LDCL_PRE + /* 531 */ MCD_OPC_FilterValue, + 14, + 101, + 0, + 0, // Skip to: 637 + /* 536 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 539 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 569 + /* 544 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 560 + /* 549 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 560 + /* 556 */ MCD_OPC_Decode, + 141, + 6, + 93, // Opcode: CDP2 + /* 560 */ MCD_OPC_CheckPredicate, + 4, + 72, + 0, + 0, // Skip to: 637 + /* 565 */ MCD_OPC_Decode, + 140, + 6, + 94, // Opcode: CDP + /* 569 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 637 + /* 574 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 577 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 607 + /* 582 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 598 + /* 587 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 598 + /* 594 */ MCD_OPC_Decode, + 254, + 6, + 95, // Opcode: MCR2 + /* 598 */ MCD_OPC_CheckPredicate, + 0, + 34, + 0, + 0, // Skip to: 637 + /* 603 */ MCD_OPC_Decode, + 253, + 6, + 96, // Opcode: MCR + /* 607 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 637 + /* 612 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 628 + /* 617 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 628 + /* 624 */ MCD_OPC_Decode, + 140, + 7, + 97, // Opcode: MRC2 + /* 628 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 637 + /* 633 */ MCD_OPC_Decode, + 139, + 7, + 98, // Opcode: MRC + /* 637 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMVE32[] = { + /* 0 */ MCD_OPC_ExtractField, + 25, + 3, // Inst{27-25} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 131, + 0, + 0, // Skip to: 139 + /* 8 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 43 + /* 16 */ MCD_OPC_CheckPredicate, + 22, + 235, + 98, + 0, // Skip to: 25344 + /* 21 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 228, + 98, + 0, // Skip to: 25344 + /* 28 */ MCD_OPC_CheckField, + 11, + 5, + 29, + 221, + 98, + 0, // Skip to: 25344 + /* 35 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 1, + /* 39 */ MCD_OPC_Decode, + 139, + 8, + 99, // Opcode: MVE_VCTP8 + /* 43 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 75 + /* 48 */ MCD_OPC_CheckPredicate, + 22, + 203, + 98, + 0, // Skip to: 25344 + /* 53 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 196, + 98, + 0, // Skip to: 25344 + /* 60 */ MCD_OPC_CheckField, + 11, + 5, + 29, + 189, + 98, + 0, // Skip to: 25344 + /* 67 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 1, + /* 71 */ MCD_OPC_Decode, + 136, + 8, + 99, // Opcode: MVE_VCTP16 + /* 75 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 107 + /* 80 */ MCD_OPC_CheckPredicate, + 22, + 171, + 98, + 0, // Skip to: 25344 + /* 85 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 164, + 98, + 0, // Skip to: 25344 + /* 92 */ MCD_OPC_CheckField, + 11, + 5, + 29, + 157, + 98, + 0, // Skip to: 25344 + /* 99 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 1, + /* 103 */ MCD_OPC_Decode, + 137, + 8, + 99, // Opcode: MVE_VCTP32 + /* 107 */ MCD_OPC_FilterValue, + 3, + 144, + 98, + 0, // Skip to: 25344 + /* 112 */ MCD_OPC_CheckPredicate, + 22, + 139, + 98, + 0, // Skip to: 25344 + /* 117 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 132, + 98, + 0, // Skip to: 25344 + /* 124 */ MCD_OPC_CheckField, + 11, + 5, + 29, + 125, + 98, + 0, // Skip to: 25344 + /* 131 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 1, + /* 135 */ MCD_OPC_Decode, + 138, + 8, + 99, // Opcode: MVE_VCTP64 + /* 139 */ MCD_OPC_FilterValue, + 5, + 238, + 1, + 0, // Skip to: 638 + /* 144 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 147 */ MCD_OPC_FilterValue, + 13, + 89, + 0, + 0, // Skip to: 241 + /* 152 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 155 */ MCD_OPC_FilterValue, + 5, + 96, + 98, + 0, // Skip to: 25344 + /* 160 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 163 */ MCD_OPC_FilterValue, + 14, + 88, + 98, + 0, // Skip to: 25344 + /* 168 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 171 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 192 + /* 176 */ MCD_OPC_CheckPredicate, + 23, + 39, + 0, + 0, // Skip to: 220 + /* 181 */ MCD_OPC_CheckField, + 6, + 3, + 4, + 32, + 0, + 0, // Skip to: 220 + /* 188 */ MCD_OPC_Decode, + 159, + 7, + 100, // Opcode: MVE_LSLLr + /* 192 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 220 + /* 197 */ MCD_OPC_CheckPredicate, + 23, + 18, + 0, + 0, // Skip to: 220 + /* 202 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 11, + 0, + 0, // Skip to: 220 + /* 209 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 4, + 0, + 0, // Skip to: 220 + /* 216 */ MCD_OPC_Decode, + 168, + 7, + 100, // Opcode: MVE_UQRSHLL + /* 220 */ MCD_OPC_CheckPredicate, + 23, + 31, + 98, + 0, // Skip to: 25344 + /* 225 */ MCD_OPC_CheckField, + 9, + 3, + 7, + 24, + 98, + 0, // Skip to: 25344 + /* 232 */ MCD_OPC_SoftFail, + 192, + 1 /* 0xc0 */, + 128, + 2 /* 0x100 */, + /* 237 */ MCD_OPC_Decode, + 167, + 7, + 101, // Opcode: MVE_UQRSHL + /* 241 */ MCD_OPC_FilterValue, + 15, + 73, + 0, + 0, // Skip to: 319 + /* 246 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 249 */ MCD_OPC_FilterValue, + 1, + 2, + 98, + 0, // Skip to: 25344 + /* 254 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 257 */ MCD_OPC_FilterValue, + 0, + 250, + 97, + 0, // Skip to: 25344 + /* 262 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 265 */ MCD_OPC_FilterValue, + 5, + 242, + 97, + 0, // Skip to: 25344 + /* 270 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 273 */ MCD_OPC_FilterValue, + 14, + 234, + 97, + 0, // Skip to: 25344 + /* 278 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 294 + /* 283 */ MCD_OPC_CheckField, + 9, + 3, + 7, + 4, + 0, + 0, // Skip to: 294 + /* 290 */ MCD_OPC_Decode, + 169, + 7, + 102, // Opcode: MVE_UQSHL + /* 294 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 310 + /* 299 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 4, + 0, + 0, // Skip to: 310 + /* 306 */ MCD_OPC_Decode, + 170, + 7, + 103, // Opcode: MVE_UQSHLL + /* 310 */ MCD_OPC_CheckPredicate, + 23, + 197, + 97, + 0, // Skip to: 25344 + /* 315 */ MCD_OPC_Decode, + 158, + 7, + 103, // Opcode: MVE_LSLLi + /* 319 */ MCD_OPC_FilterValue, + 31, + 73, + 0, + 0, // Skip to: 397 + /* 324 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 327 */ MCD_OPC_FilterValue, + 1, + 180, + 97, + 0, // Skip to: 25344 + /* 332 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 335 */ MCD_OPC_FilterValue, + 0, + 172, + 97, + 0, // Skip to: 25344 + /* 340 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 343 */ MCD_OPC_FilterValue, + 5, + 164, + 97, + 0, // Skip to: 25344 + /* 348 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 351 */ MCD_OPC_FilterValue, + 14, + 156, + 97, + 0, // Skip to: 25344 + /* 356 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 372 + /* 361 */ MCD_OPC_CheckField, + 9, + 3, + 7, + 4, + 0, + 0, // Skip to: 372 + /* 368 */ MCD_OPC_Decode, + 171, + 7, + 102, // Opcode: MVE_URSHR + /* 372 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 388 + /* 377 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 4, + 0, + 0, // Skip to: 388 + /* 384 */ MCD_OPC_Decode, + 172, + 7, + 103, // Opcode: MVE_URSHRL + /* 388 */ MCD_OPC_CheckPredicate, + 23, + 119, + 97, + 0, // Skip to: 25344 + /* 393 */ MCD_OPC_Decode, + 160, + 7, + 103, // Opcode: MVE_LSRL + /* 397 */ MCD_OPC_FilterValue, + 45, + 89, + 0, + 0, // Skip to: 491 + /* 402 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 405 */ MCD_OPC_FilterValue, + 5, + 102, + 97, + 0, // Skip to: 25344 + /* 410 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 413 */ MCD_OPC_FilterValue, + 14, + 94, + 97, + 0, // Skip to: 25344 + /* 418 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 421 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 442 + /* 426 */ MCD_OPC_CheckPredicate, + 23, + 39, + 0, + 0, // Skip to: 470 + /* 431 */ MCD_OPC_CheckField, + 6, + 3, + 4, + 32, + 0, + 0, // Skip to: 470 + /* 438 */ MCD_OPC_Decode, + 151, + 7, + 100, // Opcode: MVE_ASRLr + /* 442 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 470 + /* 447 */ MCD_OPC_CheckPredicate, + 23, + 18, + 0, + 0, // Skip to: 470 + /* 452 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 11, + 0, + 0, // Skip to: 470 + /* 459 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 4, + 0, + 0, // Skip to: 470 + /* 466 */ MCD_OPC_Decode, + 162, + 7, + 100, // Opcode: MVE_SQRSHRL + /* 470 */ MCD_OPC_CheckPredicate, + 23, + 37, + 97, + 0, // Skip to: 25344 + /* 475 */ MCD_OPC_CheckField, + 9, + 3, + 7, + 30, + 97, + 0, // Skip to: 25344 + /* 482 */ MCD_OPC_SoftFail, + 192, + 1 /* 0xc0 */, + 128, + 2 /* 0x100 */, + /* 487 */ MCD_OPC_Decode, + 161, + 7, + 101, // Opcode: MVE_SQRSHR + /* 491 */ MCD_OPC_FilterValue, + 47, + 73, + 0, + 0, // Skip to: 569 + /* 496 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 499 */ MCD_OPC_FilterValue, + 1, + 8, + 97, + 0, // Skip to: 25344 + /* 504 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 507 */ MCD_OPC_FilterValue, + 0, + 0, + 97, + 0, // Skip to: 25344 + /* 512 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 515 */ MCD_OPC_FilterValue, + 5, + 248, + 96, + 0, // Skip to: 25344 + /* 520 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 523 */ MCD_OPC_FilterValue, + 14, + 240, + 96, + 0, // Skip to: 25344 + /* 528 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 544 + /* 533 */ MCD_OPC_CheckField, + 9, + 3, + 7, + 4, + 0, + 0, // Skip to: 544 + /* 540 */ MCD_OPC_Decode, + 165, + 7, + 102, // Opcode: MVE_SRSHR + /* 544 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 560 + /* 549 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 4, + 0, + 0, // Skip to: 560 + /* 556 */ MCD_OPC_Decode, + 166, + 7, + 103, // Opcode: MVE_SRSHRL + /* 560 */ MCD_OPC_CheckPredicate, + 23, + 203, + 96, + 0, // Skip to: 25344 + /* 565 */ MCD_OPC_Decode, + 150, + 7, + 103, // Opcode: MVE_ASRLi + /* 569 */ MCD_OPC_FilterValue, + 63, + 194, + 96, + 0, // Skip to: 25344 + /* 574 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 577 */ MCD_OPC_FilterValue, + 1, + 186, + 96, + 0, // Skip to: 25344 + /* 582 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 585 */ MCD_OPC_FilterValue, + 0, + 178, + 96, + 0, // Skip to: 25344 + /* 590 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 593 */ MCD_OPC_FilterValue, + 5, + 170, + 96, + 0, // Skip to: 25344 + /* 598 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 601 */ MCD_OPC_FilterValue, + 14, + 162, + 96, + 0, // Skip to: 25344 + /* 606 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 622 + /* 611 */ MCD_OPC_CheckField, + 9, + 3, + 7, + 4, + 0, + 0, // Skip to: 622 + /* 618 */ MCD_OPC_Decode, + 163, + 7, + 102, // Opcode: MVE_SQSHL + /* 622 */ MCD_OPC_CheckPredicate, + 23, + 141, + 96, + 0, // Skip to: 25344 + /* 627 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 134, + 96, + 0, // Skip to: 25344 + /* 634 */ MCD_OPC_Decode, + 164, + 7, + 103, // Opcode: MVE_SQSHLL + /* 638 */ MCD_OPC_FilterValue, + 6, + 2, + 19, + 0, // Skip to: 5509 + /* 643 */ MCD_OPC_ExtractField, + 8, + 5, // Inst{12-8} ... + /* 646 */ MCD_OPC_FilterValue, + 8, + 213, + 0, + 0, // Skip to: 864 + /* 651 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 654 */ MCD_OPC_FilterValue, + 0, + 51, + 0, + 0, // Skip to: 710 + /* 659 */ MCD_OPC_CheckPredicate, + 24, + 104, + 96, + 0, // Skip to: 25344 + /* 664 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 97, + 96, + 0, // Skip to: 25344 + /* 671 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 90, + 96, + 0, // Skip to: 25344 + /* 678 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 83, + 96, + 0, // Skip to: 25344 + /* 685 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 76, + 96, + 0, // Skip to: 25344 + /* 692 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 69, + 96, + 0, // Skip to: 25344 + /* 699 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 62, + 96, + 0, // Skip to: 25344 + /* 706 */ MCD_OPC_Decode, + 227, + 7, + 104, // Opcode: MVE_VCADDf16 + /* 710 */ MCD_OPC_FilterValue, + 1, + 51, + 0, + 0, // Skip to: 766 + /* 715 */ MCD_OPC_CheckPredicate, + 24, + 48, + 96, + 0, // Skip to: 25344 + /* 720 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 41, + 96, + 0, // Skip to: 25344 + /* 727 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 34, + 96, + 0, // Skip to: 25344 + /* 734 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 27, + 96, + 0, // Skip to: 25344 + /* 741 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 20, + 96, + 0, // Skip to: 25344 + /* 748 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 13, + 96, + 0, // Skip to: 25344 + /* 755 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 6, + 96, + 0, // Skip to: 25344 + /* 762 */ MCD_OPC_Decode, + 228, + 7, + 104, // Opcode: MVE_VCADDf32 + /* 766 */ MCD_OPC_FilterValue, + 2, + 44, + 0, + 0, // Skip to: 815 + /* 771 */ MCD_OPC_CheckPredicate, + 24, + 248, + 95, + 0, // Skip to: 25344 + /* 776 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 241, + 95, + 0, // Skip to: 25344 + /* 783 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 234, + 95, + 0, // Skip to: 25344 + /* 790 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 227, + 95, + 0, // Skip to: 25344 + /* 797 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 220, + 95, + 0, // Skip to: 25344 + /* 804 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 213, + 95, + 0, // Skip to: 25344 + /* 811 */ MCD_OPC_Decode, + 238, + 7, + 105, // Opcode: MVE_VCMLAf16 + /* 815 */ MCD_OPC_FilterValue, + 3, + 204, + 95, + 0, // Skip to: 25344 + /* 820 */ MCD_OPC_CheckPredicate, + 24, + 199, + 95, + 0, // Skip to: 25344 + /* 825 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 192, + 95, + 0, // Skip to: 25344 + /* 832 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 185, + 95, + 0, // Skip to: 25344 + /* 839 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 178, + 95, + 0, // Skip to: 25344 + /* 846 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 171, + 95, + 0, // Skip to: 25344 + /* 853 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 95, + 0, // Skip to: 25344 + /* 860 */ MCD_OPC_Decode, + 239, + 7, + 105, // Opcode: MVE_VCMLAf32 + /* 864 */ MCD_OPC_FilterValue, + 14, + 135, + 2, + 0, // Skip to: 1516 + /* 869 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 872 */ MCD_OPC_FilterValue, + 0, + 188, + 0, + 0, // Skip to: 1065 + /* 877 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 880 */ MCD_OPC_FilterValue, + 0, + 37, + 0, + 0, // Skip to: 922 + /* 885 */ MCD_OPC_CheckPredicate, + 22, + 134, + 95, + 0, // Skip to: 25344 + /* 890 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 127, + 95, + 0, // Skip to: 25344 + /* 897 */ MCD_OPC_CheckField, + 23, + 2, + 1, + 120, + 95, + 0, // Skip to: 25344 + /* 904 */ MCD_OPC_CheckField, + 4, + 3, + 0, + 113, + 95, + 0, // Skip to: 25344 + /* 911 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 106, + 95, + 0, // Skip to: 25344 + /* 918 */ MCD_OPC_Decode, + 184, + 13, + 106, // Opcode: MVE_VSTRB8_rq + /* 922 */ MCD_OPC_FilterValue, + 1, + 97, + 95, + 0, // Skip to: 25344 + /* 927 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 930 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 1037 + /* 935 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 938 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 1002 + /* 943 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 946 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 974 + /* 951 */ MCD_OPC_CheckPredicate, + 22, + 68, + 95, + 0, // Skip to: 25344 + /* 956 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 61, + 95, + 0, // Skip to: 25344 + /* 963 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 54, + 95, + 0, // Skip to: 25344 + /* 970 */ MCD_OPC_Decode, + 179, + 13, + 106, // Opcode: MVE_VSTRB16_rq + /* 974 */ MCD_OPC_FilterValue, + 1, + 45, + 95, + 0, // Skip to: 25344 + /* 979 */ MCD_OPC_CheckPredicate, + 22, + 40, + 95, + 0, // Skip to: 25344 + /* 984 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 33, + 95, + 0, // Skip to: 25344 + /* 991 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 26, + 95, + 0, // Skip to: 25344 + /* 998 */ MCD_OPC_Decode, + 193, + 13, + 106, // Opcode: MVE_VSTRH16_rq_u + /* 1002 */ MCD_OPC_FilterValue, + 1, + 17, + 95, + 0, // Skip to: 25344 + /* 1007 */ MCD_OPC_CheckPredicate, + 22, + 12, + 95, + 0, // Skip to: 25344 + /* 1012 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 5, + 95, + 0, // Skip to: 25344 + /* 1019 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 254, + 94, + 0, // Skip to: 25344 + /* 1026 */ MCD_OPC_CheckField, + 4, + 3, + 1, + 247, + 94, + 0, // Skip to: 25344 + /* 1033 */ MCD_OPC_Decode, + 192, + 13, + 106, // Opcode: MVE_VSTRH16_rq + /* 1037 */ MCD_OPC_FilterValue, + 1, + 238, + 94, + 0, // Skip to: 25344 + /* 1042 */ MCD_OPC_CheckPredicate, + 22, + 233, + 94, + 0, // Skip to: 25344 + /* 1047 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 226, + 94, + 0, // Skip to: 25344 + /* 1054 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 219, + 94, + 0, // Skip to: 25344 + /* 1061 */ MCD_OPC_Decode, + 176, + 13, + 107, // Opcode: MVE_VSTRB16 + /* 1065 */ MCD_OPC_FilterValue, + 1, + 232, + 0, + 0, // Skip to: 1302 + /* 1070 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1073 */ MCD_OPC_FilterValue, + 0, + 37, + 0, + 0, // Skip to: 1115 + /* 1078 */ MCD_OPC_CheckPredicate, + 22, + 197, + 94, + 0, // Skip to: 25344 + /* 1083 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 190, + 94, + 0, // Skip to: 25344 + /* 1090 */ MCD_OPC_CheckField, + 23, + 2, + 1, + 183, + 94, + 0, // Skip to: 25344 + /* 1097 */ MCD_OPC_CheckField, + 4, + 3, + 0, + 176, + 94, + 0, // Skip to: 25344 + /* 1104 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 169, + 94, + 0, // Skip to: 25344 + /* 1111 */ MCD_OPC_Decode, + 154, + 9, + 106, // Opcode: MVE_VLDRBU8_rq + /* 1115 */ MCD_OPC_FilterValue, + 1, + 160, + 94, + 0, // Skip to: 25344 + /* 1120 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 1123 */ MCD_OPC_FilterValue, + 0, + 124, + 0, + 0, // Skip to: 1252 + /* 1128 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 1131 */ MCD_OPC_FilterValue, + 0, + 81, + 0, + 0, // Skip to: 1217 + /* 1136 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 1139 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 1189 + /* 1144 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 1147 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 1168 + /* 1152 */ MCD_OPC_CheckPredicate, + 22, + 123, + 94, + 0, // Skip to: 25344 + /* 1157 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 116, + 94, + 0, // Skip to: 25344 + /* 1164 */ MCD_OPC_Decode, + 138, + 9, + 106, // Opcode: MVE_VLDRBS16_rq + /* 1168 */ MCD_OPC_FilterValue, + 15, + 107, + 94, + 0, // Skip to: 25344 + /* 1173 */ MCD_OPC_CheckPredicate, + 22, + 102, + 94, + 0, // Skip to: 25344 + /* 1178 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 95, + 94, + 0, // Skip to: 25344 + /* 1185 */ MCD_OPC_Decode, + 146, + 9, + 106, // Opcode: MVE_VLDRBU16_rq + /* 1189 */ MCD_OPC_FilterValue, + 1, + 86, + 94, + 0, // Skip to: 25344 + /* 1194 */ MCD_OPC_CheckPredicate, + 22, + 81, + 94, + 0, // Skip to: 25344 + /* 1199 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 74, + 94, + 0, // Skip to: 25344 + /* 1206 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 67, + 94, + 0, // Skip to: 25344 + /* 1213 */ MCD_OPC_Decode, + 168, + 9, + 106, // Opcode: MVE_VLDRHU16_rq_u + /* 1217 */ MCD_OPC_FilterValue, + 1, + 58, + 94, + 0, // Skip to: 25344 + /* 1222 */ MCD_OPC_CheckPredicate, + 22, + 53, + 94, + 0, // Skip to: 25344 + /* 1227 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 46, + 94, + 0, // Skip to: 25344 + /* 1234 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 39, + 94, + 0, // Skip to: 25344 + /* 1241 */ MCD_OPC_CheckField, + 4, + 3, + 1, + 32, + 94, + 0, // Skip to: 25344 + /* 1248 */ MCD_OPC_Decode, + 167, + 9, + 106, // Opcode: MVE_VLDRHU16_rq + /* 1252 */ MCD_OPC_FilterValue, + 1, + 23, + 94, + 0, // Skip to: 25344 + /* 1257 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 1260 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 1281 + /* 1265 */ MCD_OPC_CheckPredicate, + 22, + 10, + 94, + 0, // Skip to: 25344 + /* 1270 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 3, + 94, + 0, // Skip to: 25344 + /* 1277 */ MCD_OPC_Decode, + 135, + 9, + 107, // Opcode: MVE_VLDRBS16 + /* 1281 */ MCD_OPC_FilterValue, + 15, + 250, + 93, + 0, // Skip to: 25344 + /* 1286 */ MCD_OPC_CheckPredicate, + 22, + 245, + 93, + 0, // Skip to: 25344 + /* 1291 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 238, + 93, + 0, // Skip to: 25344 + /* 1298 */ MCD_OPC_Decode, + 143, + 9, + 107, // Opcode: MVE_VLDRBU16 + /* 1302 */ MCD_OPC_FilterValue, + 2, + 73, + 0, + 0, // Skip to: 1380 + /* 1307 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 1310 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 1345 + /* 1315 */ MCD_OPC_CheckPredicate, + 22, + 216, + 93, + 0, // Skip to: 25344 + /* 1320 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 209, + 93, + 0, // Skip to: 25344 + /* 1327 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 202, + 93, + 0, // Skip to: 25344 + /* 1334 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 195, + 93, + 0, // Skip to: 25344 + /* 1341 */ MCD_OPC_Decode, + 177, + 13, + 108, // Opcode: MVE_VSTRB16_post + /* 1345 */ MCD_OPC_FilterValue, + 1, + 186, + 93, + 0, // Skip to: 25344 + /* 1350 */ MCD_OPC_CheckPredicate, + 22, + 181, + 93, + 0, // Skip to: 25344 + /* 1355 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 174, + 93, + 0, // Skip to: 25344 + /* 1362 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 167, + 93, + 0, // Skip to: 25344 + /* 1369 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 160, + 93, + 0, // Skip to: 25344 + /* 1376 */ MCD_OPC_Decode, + 178, + 13, + 109, // Opcode: MVE_VSTRB16_pre + /* 1380 */ MCD_OPC_FilterValue, + 3, + 151, + 93, + 0, // Skip to: 25344 + /* 1385 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 1388 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 1452 + /* 1393 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 1396 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 1424 + /* 1401 */ MCD_OPC_CheckPredicate, + 22, + 130, + 93, + 0, // Skip to: 25344 + /* 1406 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 123, + 93, + 0, // Skip to: 25344 + /* 1413 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 116, + 93, + 0, // Skip to: 25344 + /* 1420 */ MCD_OPC_Decode, + 136, + 9, + 108, // Opcode: MVE_VLDRBS16_post + /* 1424 */ MCD_OPC_FilterValue, + 15, + 107, + 93, + 0, // Skip to: 25344 + /* 1429 */ MCD_OPC_CheckPredicate, + 22, + 102, + 93, + 0, // Skip to: 25344 + /* 1434 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 95, + 93, + 0, // Skip to: 25344 + /* 1441 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 88, + 93, + 0, // Skip to: 25344 + /* 1448 */ MCD_OPC_Decode, + 144, + 9, + 108, // Opcode: MVE_VLDRBU16_post + /* 1452 */ MCD_OPC_FilterValue, + 1, + 79, + 93, + 0, // Skip to: 25344 + /* 1457 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 1460 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 1488 + /* 1465 */ MCD_OPC_CheckPredicate, + 22, + 66, + 93, + 0, // Skip to: 25344 + /* 1470 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 59, + 93, + 0, // Skip to: 25344 + /* 1477 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 52, + 93, + 0, // Skip to: 25344 + /* 1484 */ MCD_OPC_Decode, + 137, + 9, + 109, // Opcode: MVE_VLDRBS16_pre + /* 1488 */ MCD_OPC_FilterValue, + 15, + 43, + 93, + 0, // Skip to: 25344 + /* 1493 */ MCD_OPC_CheckPredicate, + 22, + 38, + 93, + 0, // Skip to: 25344 + /* 1498 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 31, + 93, + 0, // Skip to: 25344 + /* 1505 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 24, + 93, + 0, // Skip to: 25344 + /* 1512 */ MCD_OPC_Decode, + 145, + 9, + 109, // Opcode: MVE_VLDRBU16_pre + /* 1516 */ MCD_OPC_FilterValue, + 15, + 44, + 5, + 0, // Skip to: 2845 + /* 1521 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1524 */ MCD_OPC_FilterValue, + 0, + 119, + 1, + 0, // Skip to: 1904 + /* 1529 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1532 */ MCD_OPC_FilterValue, + 0, + 33, + 1, + 0, // Skip to: 1826 + /* 1537 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 1540 */ MCD_OPC_FilterValue, + 0, + 217, + 0, + 0, // Skip to: 1762 + /* 1545 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 1548 */ MCD_OPC_FilterValue, + 0, + 131, + 0, + 0, // Skip to: 1684 + /* 1553 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1556 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1577 + /* 1561 */ MCD_OPC_CheckPredicate, + 23, + 226, + 92, + 0, // Skip to: 25344 + /* 1566 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 219, + 92, + 0, // Skip to: 25344 + /* 1573 */ MCD_OPC_Decode, + 179, + 10, + 110, // Opcode: MVE_VMOV_rr_q + /* 1577 */ MCD_OPC_FilterValue, + 1, + 210, + 92, + 0, // Skip to: 25344 + /* 1582 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 1585 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 1649 + /* 1590 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1593 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 1621 + /* 1598 */ MCD_OPC_CheckPredicate, + 22, + 189, + 92, + 0, // Skip to: 25344 + /* 1603 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 182, + 92, + 0, // Skip to: 25344 + /* 1610 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 175, + 92, + 0, // Skip to: 25344 + /* 1617 */ MCD_OPC_Decode, + 183, + 13, + 106, // Opcode: MVE_VSTRB32_rq + /* 1621 */ MCD_OPC_FilterValue, + 1, + 166, + 92, + 0, // Skip to: 25344 + /* 1626 */ MCD_OPC_CheckPredicate, + 22, + 161, + 92, + 0, // Skip to: 25344 + /* 1631 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 154, + 92, + 0, // Skip to: 25344 + /* 1638 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 147, + 92, + 0, // Skip to: 25344 + /* 1645 */ MCD_OPC_Decode, + 198, + 13, + 106, // Opcode: MVE_VSTRH32_rq_u + /* 1649 */ MCD_OPC_FilterValue, + 1, + 138, + 92, + 0, // Skip to: 25344 + /* 1654 */ MCD_OPC_CheckPredicate, + 22, + 133, + 92, + 0, // Skip to: 25344 + /* 1659 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 126, + 92, + 0, // Skip to: 25344 + /* 1666 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 119, + 92, + 0, // Skip to: 25344 + /* 1673 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 112, + 92, + 0, // Skip to: 25344 + /* 1680 */ MCD_OPC_Decode, + 197, + 13, + 106, // Opcode: MVE_VSTRH32_rq + /* 1684 */ MCD_OPC_FilterValue, + 2, + 103, + 92, + 0, // Skip to: 25344 + /* 1689 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 1692 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 1727 + /* 1697 */ MCD_OPC_CheckPredicate, + 22, + 90, + 92, + 0, // Skip to: 25344 + /* 1702 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 83, + 92, + 0, // Skip to: 25344 + /* 1709 */ MCD_OPC_CheckField, + 22, + 2, + 2, + 76, + 92, + 0, // Skip to: 25344 + /* 1716 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 69, + 92, + 0, // Skip to: 25344 + /* 1723 */ MCD_OPC_Decode, + 205, + 13, + 106, // Opcode: MVE_VSTRW32_rq_u + /* 1727 */ MCD_OPC_FilterValue, + 1, + 60, + 92, + 0, // Skip to: 25344 + /* 1732 */ MCD_OPC_CheckPredicate, + 22, + 55, + 92, + 0, // Skip to: 25344 + /* 1737 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 48, + 92, + 0, // Skip to: 25344 + /* 1744 */ MCD_OPC_CheckField, + 22, + 2, + 2, + 41, + 92, + 0, // Skip to: 25344 + /* 1751 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 34, + 92, + 0, // Skip to: 25344 + /* 1758 */ MCD_OPC_Decode, + 204, + 13, + 106, // Opcode: MVE_VSTRW32_rq + /* 1762 */ MCD_OPC_FilterValue, + 1, + 25, + 92, + 0, // Skip to: 25344 + /* 1767 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 1770 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 1798 + /* 1775 */ MCD_OPC_CheckPredicate, + 22, + 12, + 92, + 0, // Skip to: 25344 + /* 1780 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 5, + 92, + 0, // Skip to: 25344 + /* 1787 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 254, + 91, + 0, // Skip to: 25344 + /* 1794 */ MCD_OPC_Decode, + 180, + 13, + 107, // Opcode: MVE_VSTRB32 + /* 1798 */ MCD_OPC_FilterValue, + 1, + 245, + 91, + 0, // Skip to: 25344 + /* 1803 */ MCD_OPC_CheckPredicate, + 22, + 240, + 91, + 0, // Skip to: 25344 + /* 1808 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 233, + 91, + 0, // Skip to: 25344 + /* 1815 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 226, + 91, + 0, // Skip to: 25344 + /* 1822 */ MCD_OPC_Decode, + 194, + 13, + 111, // Opcode: MVE_VSTRH32 + /* 1826 */ MCD_OPC_FilterValue, + 1, + 217, + 91, + 0, // Skip to: 25344 + /* 1831 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 1834 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 1869 + /* 1839 */ MCD_OPC_CheckPredicate, + 22, + 204, + 91, + 0, // Skip to: 25344 + /* 1844 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 197, + 91, + 0, // Skip to: 25344 + /* 1851 */ MCD_OPC_CheckField, + 22, + 3, + 2, + 190, + 91, + 0, // Skip to: 25344 + /* 1858 */ MCD_OPC_CheckField, + 4, + 3, + 5, + 183, + 91, + 0, // Skip to: 25344 + /* 1865 */ MCD_OPC_Decode, + 191, + 13, + 106, // Opcode: MVE_VSTRD64_rq_u + /* 1869 */ MCD_OPC_FilterValue, + 1, + 174, + 91, + 0, // Skip to: 25344 + /* 1874 */ MCD_OPC_CheckPredicate, + 22, + 169, + 91, + 0, // Skip to: 25344 + /* 1879 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 162, + 91, + 0, // Skip to: 25344 + /* 1886 */ MCD_OPC_CheckField, + 22, + 3, + 2, + 155, + 91, + 0, // Skip to: 25344 + /* 1893 */ MCD_OPC_CheckField, + 4, + 3, + 5, + 148, + 91, + 0, // Skip to: 25344 + /* 1900 */ MCD_OPC_Decode, + 190, + 13, + 106, // Opcode: MVE_VSTRD64_rq + /* 1904 */ MCD_OPC_FilterValue, + 1, + 236, + 1, + 0, // Skip to: 2401 + /* 1909 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1912 */ MCD_OPC_FilterValue, + 0, + 150, + 1, + 0, // Skip to: 2323 + /* 1917 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 1920 */ MCD_OPC_FilterValue, + 0, + 34, + 1, + 0, // Skip to: 2215 + /* 1925 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 1928 */ MCD_OPC_FilterValue, + 0, + 204, + 0, + 0, // Skip to: 2137 + /* 1933 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1936 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1957 + /* 1941 */ MCD_OPC_CheckPredicate, + 23, + 102, + 91, + 0, // Skip to: 25344 + /* 1946 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 95, + 91, + 0, // Skip to: 25344 + /* 1953 */ MCD_OPC_Decode, + 178, + 10, + 112, // Opcode: MVE_VMOV_q_rr + /* 1957 */ MCD_OPC_FilterValue, + 1, + 86, + 91, + 0, // Skip to: 25344 + /* 1962 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 1965 */ MCD_OPC_FilterValue, + 0, + 103, + 0, + 0, // Skip to: 2073 + /* 1970 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1973 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 2023 + /* 1978 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 1981 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 2002 + /* 1986 */ MCD_OPC_CheckPredicate, + 22, + 57, + 91, + 0, // Skip to: 25344 + /* 1991 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 50, + 91, + 0, // Skip to: 25344 + /* 1998 */ MCD_OPC_Decode, + 142, + 9, + 106, // Opcode: MVE_VLDRBS32_rq + /* 2002 */ MCD_OPC_FilterValue, + 15, + 41, + 91, + 0, // Skip to: 25344 + /* 2007 */ MCD_OPC_CheckPredicate, + 22, + 36, + 91, + 0, // Skip to: 25344 + /* 2012 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 29, + 91, + 0, // Skip to: 25344 + /* 2019 */ MCD_OPC_Decode, + 150, + 9, + 106, // Opcode: MVE_VLDRBU32_rq + /* 2023 */ MCD_OPC_FilterValue, + 1, + 20, + 91, + 0, // Skip to: 25344 + /* 2028 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2031 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 2052 + /* 2036 */ MCD_OPC_CheckPredicate, + 22, + 7, + 91, + 0, // Skip to: 25344 + /* 2041 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 0, + 91, + 0, // Skip to: 25344 + /* 2048 */ MCD_OPC_Decode, + 163, + 9, + 106, // Opcode: MVE_VLDRHS32_rq_u + /* 2052 */ MCD_OPC_FilterValue, + 15, + 247, + 90, + 0, // Skip to: 25344 + /* 2057 */ MCD_OPC_CheckPredicate, + 22, + 242, + 90, + 0, // Skip to: 25344 + /* 2062 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 235, + 90, + 0, // Skip to: 25344 + /* 2069 */ MCD_OPC_Decode, + 173, + 9, + 106, // Opcode: MVE_VLDRHU32_rq_u + /* 2073 */ MCD_OPC_FilterValue, + 1, + 226, + 90, + 0, // Skip to: 25344 + /* 2078 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2081 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 2109 + /* 2086 */ MCD_OPC_CheckPredicate, + 22, + 213, + 90, + 0, // Skip to: 25344 + /* 2091 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 206, + 90, + 0, // Skip to: 25344 + /* 2098 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 199, + 90, + 0, // Skip to: 25344 + /* 2105 */ MCD_OPC_Decode, + 162, + 9, + 106, // Opcode: MVE_VLDRHS32_rq + /* 2109 */ MCD_OPC_FilterValue, + 15, + 190, + 90, + 0, // Skip to: 25344 + /* 2114 */ MCD_OPC_CheckPredicate, + 22, + 185, + 90, + 0, // Skip to: 25344 + /* 2119 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 178, + 90, + 0, // Skip to: 25344 + /* 2126 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 171, + 90, + 0, // Skip to: 25344 + /* 2133 */ MCD_OPC_Decode, + 172, + 9, + 106, // Opcode: MVE_VLDRHU32_rq + /* 2137 */ MCD_OPC_FilterValue, + 2, + 162, + 90, + 0, // Skip to: 25344 + /* 2142 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 2145 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 2180 + /* 2150 */ MCD_OPC_CheckPredicate, + 22, + 149, + 90, + 0, // Skip to: 25344 + /* 2155 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 142, + 90, + 0, // Skip to: 25344 + /* 2162 */ MCD_OPC_CheckField, + 22, + 2, + 2, + 135, + 90, + 0, // Skip to: 25344 + /* 2169 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 128, + 90, + 0, // Skip to: 25344 + /* 2176 */ MCD_OPC_Decode, + 180, + 9, + 106, // Opcode: MVE_VLDRWU32_rq_u + /* 2180 */ MCD_OPC_FilterValue, + 1, + 119, + 90, + 0, // Skip to: 25344 + /* 2185 */ MCD_OPC_CheckPredicate, + 22, + 114, + 90, + 0, // Skip to: 25344 + /* 2190 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 107, + 90, + 0, // Skip to: 25344 + /* 2197 */ MCD_OPC_CheckField, + 22, + 2, + 2, + 100, + 90, + 0, // Skip to: 25344 + /* 2204 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 93, + 90, + 0, // Skip to: 25344 + /* 2211 */ MCD_OPC_Decode, + 179, + 9, + 106, // Opcode: MVE_VLDRWU32_rq + /* 2215 */ MCD_OPC_FilterValue, + 1, + 84, + 90, + 0, // Skip to: 25344 + /* 2220 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 2223 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 2273 + /* 2228 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2231 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 2252 + /* 2236 */ MCD_OPC_CheckPredicate, + 22, + 63, + 90, + 0, // Skip to: 25344 + /* 2241 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 56, + 90, + 0, // Skip to: 25344 + /* 2248 */ MCD_OPC_Decode, + 139, + 9, + 107, // Opcode: MVE_VLDRBS32 + /* 2252 */ MCD_OPC_FilterValue, + 15, + 47, + 90, + 0, // Skip to: 25344 + /* 2257 */ MCD_OPC_CheckPredicate, + 22, + 42, + 90, + 0, // Skip to: 25344 + /* 2262 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 35, + 90, + 0, // Skip to: 25344 + /* 2269 */ MCD_OPC_Decode, + 147, + 9, + 107, // Opcode: MVE_VLDRBU32 + /* 2273 */ MCD_OPC_FilterValue, + 1, + 26, + 90, + 0, // Skip to: 25344 + /* 2278 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2281 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 2302 + /* 2286 */ MCD_OPC_CheckPredicate, + 22, + 13, + 90, + 0, // Skip to: 25344 + /* 2291 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 6, + 90, + 0, // Skip to: 25344 + /* 2298 */ MCD_OPC_Decode, + 159, + 9, + 111, // Opcode: MVE_VLDRHS32 + /* 2302 */ MCD_OPC_FilterValue, + 15, + 253, + 89, + 0, // Skip to: 25344 + /* 2307 */ MCD_OPC_CheckPredicate, + 22, + 248, + 89, + 0, // Skip to: 25344 + /* 2312 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 241, + 89, + 0, // Skip to: 25344 + /* 2319 */ MCD_OPC_Decode, + 169, + 9, + 111, // Opcode: MVE_VLDRHU32 + /* 2323 */ MCD_OPC_FilterValue, + 1, + 232, + 89, + 0, // Skip to: 25344 + /* 2328 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 2331 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 2366 + /* 2336 */ MCD_OPC_CheckPredicate, + 22, + 219, + 89, + 0, // Skip to: 25344 + /* 2341 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 212, + 89, + 0, // Skip to: 25344 + /* 2348 */ MCD_OPC_CheckField, + 22, + 3, + 2, + 205, + 89, + 0, // Skip to: 25344 + /* 2355 */ MCD_OPC_CheckField, + 4, + 3, + 5, + 198, + 89, + 0, // Skip to: 25344 + /* 2362 */ MCD_OPC_Decode, + 158, + 9, + 106, // Opcode: MVE_VLDRDU64_rq_u + /* 2366 */ MCD_OPC_FilterValue, + 1, + 189, + 89, + 0, // Skip to: 25344 + /* 2371 */ MCD_OPC_CheckPredicate, + 22, + 184, + 89, + 0, // Skip to: 25344 + /* 2376 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 177, + 89, + 0, // Skip to: 25344 + /* 2383 */ MCD_OPC_CheckField, + 22, + 3, + 2, + 170, + 89, + 0, // Skip to: 25344 + /* 2390 */ MCD_OPC_CheckField, + 4, + 3, + 5, + 163, + 89, + 0, // Skip to: 25344 + /* 2397 */ MCD_OPC_Decode, + 157, + 9, + 106, // Opcode: MVE_VLDRDU64_rq + /* 2401 */ MCD_OPC_FilterValue, + 2, + 159, + 0, + 0, // Skip to: 2565 + /* 2406 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 2409 */ MCD_OPC_FilterValue, + 0, + 73, + 0, + 0, // Skip to: 2487 + /* 2414 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 2417 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 2452 + /* 2422 */ MCD_OPC_CheckPredicate, + 22, + 133, + 89, + 0, // Skip to: 25344 + /* 2427 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 126, + 89, + 0, // Skip to: 25344 + /* 2434 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 119, + 89, + 0, // Skip to: 25344 + /* 2441 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 112, + 89, + 0, // Skip to: 25344 + /* 2448 */ MCD_OPC_Decode, + 181, + 13, + 108, // Opcode: MVE_VSTRB32_post + /* 2452 */ MCD_OPC_FilterValue, + 1, + 103, + 89, + 0, // Skip to: 25344 + /* 2457 */ MCD_OPC_CheckPredicate, + 22, + 98, + 89, + 0, // Skip to: 25344 + /* 2462 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 91, + 89, + 0, // Skip to: 25344 + /* 2469 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 84, + 89, + 0, // Skip to: 25344 + /* 2476 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 77, + 89, + 0, // Skip to: 25344 + /* 2483 */ MCD_OPC_Decode, + 182, + 13, + 109, // Opcode: MVE_VSTRB32_pre + /* 2487 */ MCD_OPC_FilterValue, + 1, + 68, + 89, + 0, // Skip to: 25344 + /* 2492 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 2495 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 2530 + /* 2500 */ MCD_OPC_CheckPredicate, + 22, + 55, + 89, + 0, // Skip to: 25344 + /* 2505 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 48, + 89, + 0, // Skip to: 25344 + /* 2512 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 41, + 89, + 0, // Skip to: 25344 + /* 2519 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 34, + 89, + 0, // Skip to: 25344 + /* 2526 */ MCD_OPC_Decode, + 195, + 13, + 113, // Opcode: MVE_VSTRH32_post + /* 2530 */ MCD_OPC_FilterValue, + 1, + 25, + 89, + 0, // Skip to: 25344 + /* 2535 */ MCD_OPC_CheckPredicate, + 22, + 20, + 89, + 0, // Skip to: 25344 + /* 2540 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 13, + 89, + 0, // Skip to: 25344 + /* 2547 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 6, + 89, + 0, // Skip to: 25344 + /* 2554 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 255, + 88, + 0, // Skip to: 25344 + /* 2561 */ MCD_OPC_Decode, + 196, + 13, + 114, // Opcode: MVE_VSTRH32_pre + /* 2565 */ MCD_OPC_FilterValue, + 3, + 246, + 88, + 0, // Skip to: 25344 + /* 2570 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 2573 */ MCD_OPC_FilterValue, + 0, + 131, + 0, + 0, // Skip to: 2709 + /* 2578 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 2581 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 2645 + /* 2586 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2589 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 2617 + /* 2594 */ MCD_OPC_CheckPredicate, + 22, + 217, + 88, + 0, // Skip to: 25344 + /* 2599 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 210, + 88, + 0, // Skip to: 25344 + /* 2606 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 203, + 88, + 0, // Skip to: 25344 + /* 2613 */ MCD_OPC_Decode, + 140, + 9, + 108, // Opcode: MVE_VLDRBS32_post + /* 2617 */ MCD_OPC_FilterValue, + 15, + 194, + 88, + 0, // Skip to: 25344 + /* 2622 */ MCD_OPC_CheckPredicate, + 22, + 189, + 88, + 0, // Skip to: 25344 + /* 2627 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 182, + 88, + 0, // Skip to: 25344 + /* 2634 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 175, + 88, + 0, // Skip to: 25344 + /* 2641 */ MCD_OPC_Decode, + 148, + 9, + 108, // Opcode: MVE_VLDRBU32_post + /* 2645 */ MCD_OPC_FilterValue, + 1, + 166, + 88, + 0, // Skip to: 25344 + /* 2650 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2653 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 2681 + /* 2658 */ MCD_OPC_CheckPredicate, + 22, + 153, + 88, + 0, // Skip to: 25344 + /* 2663 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 146, + 88, + 0, // Skip to: 25344 + /* 2670 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 139, + 88, + 0, // Skip to: 25344 + /* 2677 */ MCD_OPC_Decode, + 141, + 9, + 109, // Opcode: MVE_VLDRBS32_pre + /* 2681 */ MCD_OPC_FilterValue, + 15, + 130, + 88, + 0, // Skip to: 25344 + /* 2686 */ MCD_OPC_CheckPredicate, + 22, + 125, + 88, + 0, // Skip to: 25344 + /* 2691 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 118, + 88, + 0, // Skip to: 25344 + /* 2698 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 111, + 88, + 0, // Skip to: 25344 + /* 2705 */ MCD_OPC_Decode, + 149, + 9, + 109, // Opcode: MVE_VLDRBU32_pre + /* 2709 */ MCD_OPC_FilterValue, + 1, + 102, + 88, + 0, // Skip to: 25344 + /* 2714 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 2717 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 2781 + /* 2722 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2725 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 2753 + /* 2730 */ MCD_OPC_CheckPredicate, + 22, + 81, + 88, + 0, // Skip to: 25344 + /* 2735 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 74, + 88, + 0, // Skip to: 25344 + /* 2742 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 67, + 88, + 0, // Skip to: 25344 + /* 2749 */ MCD_OPC_Decode, + 160, + 9, + 113, // Opcode: MVE_VLDRHS32_post + /* 2753 */ MCD_OPC_FilterValue, + 15, + 58, + 88, + 0, // Skip to: 25344 + /* 2758 */ MCD_OPC_CheckPredicate, + 22, + 53, + 88, + 0, // Skip to: 25344 + /* 2763 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 46, + 88, + 0, // Skip to: 25344 + /* 2770 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 39, + 88, + 0, // Skip to: 25344 + /* 2777 */ MCD_OPC_Decode, + 170, + 9, + 113, // Opcode: MVE_VLDRHU32_post + /* 2781 */ MCD_OPC_FilterValue, + 1, + 30, + 88, + 0, // Skip to: 25344 + /* 2786 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2789 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 2817 + /* 2794 */ MCD_OPC_CheckPredicate, + 22, + 17, + 88, + 0, // Skip to: 25344 + /* 2799 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 10, + 88, + 0, // Skip to: 25344 + /* 2806 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 3, + 88, + 0, // Skip to: 25344 + /* 2813 */ MCD_OPC_Decode, + 161, + 9, + 114, // Opcode: MVE_VLDRHS32_pre + /* 2817 */ MCD_OPC_FilterValue, + 15, + 250, + 87, + 0, // Skip to: 25344 + /* 2822 */ MCD_OPC_CheckPredicate, + 22, + 245, + 87, + 0, // Skip to: 25344 + /* 2827 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 238, + 87, + 0, // Skip to: 25344 + /* 2834 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 231, + 87, + 0, // Skip to: 25344 + /* 2841 */ MCD_OPC_Decode, + 171, + 9, + 114, // Opcode: MVE_VLDRHU32_pre + /* 2845 */ MCD_OPC_FilterValue, + 30, + 161, + 6, + 0, // Skip to: 4547 + /* 2850 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 2853 */ MCD_OPC_FilterValue, + 0, + 179, + 1, + 0, // Skip to: 3293 + /* 2858 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 2861 */ MCD_OPC_FilterValue, + 0, + 222, + 0, + 0, // Skip to: 3088 + /* 2866 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 2869 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 3045 + /* 2874 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 2877 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 2905 + /* 2882 */ MCD_OPC_CheckPredicate, + 22, + 185, + 87, + 0, // Skip to: 25344 + /* 2887 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 178, + 87, + 0, // Skip to: 25344 + /* 2894 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 171, + 87, + 0, // Skip to: 25344 + /* 2901 */ MCD_OPC_Decode, + 144, + 13, + 115, // Opcode: MVE_VST20_8 + /* 2905 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 2933 + /* 2910 */ MCD_OPC_CheckPredicate, + 22, + 157, + 87, + 0, // Skip to: 25344 + /* 2915 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 150, + 87, + 0, // Skip to: 25344 + /* 2922 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 143, + 87, + 0, // Skip to: 25344 + /* 2929 */ MCD_OPC_Decode, + 156, + 13, + 116, // Opcode: MVE_VST40_8 + /* 2933 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 2961 + /* 2938 */ MCD_OPC_CheckPredicate, + 22, + 129, + 87, + 0, // Skip to: 25344 + /* 2943 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 122, + 87, + 0, // Skip to: 25344 + /* 2950 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 115, + 87, + 0, // Skip to: 25344 + /* 2957 */ MCD_OPC_Decode, + 150, + 13, + 115, // Opcode: MVE_VST21_8 + /* 2961 */ MCD_OPC_FilterValue, + 33, + 23, + 0, + 0, // Skip to: 2989 + /* 2966 */ MCD_OPC_CheckPredicate, + 22, + 101, + 87, + 0, // Skip to: 25344 + /* 2971 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 94, + 87, + 0, // Skip to: 25344 + /* 2978 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 87, + 87, + 0, // Skip to: 25344 + /* 2985 */ MCD_OPC_Decode, + 162, + 13, + 116, // Opcode: MVE_VST41_8 + /* 2989 */ MCD_OPC_FilterValue, + 65, + 23, + 0, + 0, // Skip to: 3017 + /* 2994 */ MCD_OPC_CheckPredicate, + 22, + 73, + 87, + 0, // Skip to: 25344 + /* 2999 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 66, + 87, + 0, // Skip to: 25344 + /* 3006 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 59, + 87, + 0, // Skip to: 25344 + /* 3013 */ MCD_OPC_Decode, + 168, + 13, + 116, // Opcode: MVE_VST42_8 + /* 3017 */ MCD_OPC_FilterValue, + 97, + 50, + 87, + 0, // Skip to: 25344 + /* 3022 */ MCD_OPC_CheckPredicate, + 22, + 45, + 87, + 0, // Skip to: 25344 + /* 3027 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 38, + 87, + 0, // Skip to: 25344 + /* 3034 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 31, + 87, + 0, // Skip to: 25344 + /* 3041 */ MCD_OPC_Decode, + 174, + 13, + 116, // Opcode: MVE_VST43_8 + /* 3045 */ MCD_OPC_FilterValue, + 1, + 22, + 87, + 0, // Skip to: 25344 + /* 3050 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 3053 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 3067 + /* 3058 */ MCD_OPC_CheckPredicate, + 22, + 9, + 87, + 0, // Skip to: 25344 + /* 3063 */ MCD_OPC_Decode, + 185, + 13, + 117, // Opcode: MVE_VSTRBU8 + /* 3067 */ MCD_OPC_FilterValue, + 15, + 0, + 87, + 0, // Skip to: 25344 + /* 3072 */ MCD_OPC_CheckPredicate, + 22, + 251, + 86, + 0, // Skip to: 25344 + /* 3077 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 244, + 86, + 0, // Skip to: 25344 + /* 3084 */ MCD_OPC_Decode, + 202, + 13, + 118, // Opcode: MVE_VSTRW32_qi + /* 3088 */ MCD_OPC_FilterValue, + 1, + 235, + 86, + 0, // Skip to: 25344 + /* 3093 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3096 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 3272 + /* 3101 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 3104 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 3132 + /* 3109 */ MCD_OPC_CheckPredicate, + 22, + 214, + 86, + 0, // Skip to: 25344 + /* 3114 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 207, + 86, + 0, // Skip to: 25344 + /* 3121 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 200, + 86, + 0, // Skip to: 25344 + /* 3128 */ MCD_OPC_Decode, + 140, + 13, + 115, // Opcode: MVE_VST20_16 + /* 3132 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 3160 + /* 3137 */ MCD_OPC_CheckPredicate, + 22, + 186, + 86, + 0, // Skip to: 25344 + /* 3142 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 179, + 86, + 0, // Skip to: 25344 + /* 3149 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 172, + 86, + 0, // Skip to: 25344 + /* 3156 */ MCD_OPC_Decode, + 152, + 13, + 116, // Opcode: MVE_VST40_16 + /* 3160 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 3188 + /* 3165 */ MCD_OPC_CheckPredicate, + 22, + 158, + 86, + 0, // Skip to: 25344 + /* 3170 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 151, + 86, + 0, // Skip to: 25344 + /* 3177 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 144, + 86, + 0, // Skip to: 25344 + /* 3184 */ MCD_OPC_Decode, + 146, + 13, + 115, // Opcode: MVE_VST21_16 + /* 3188 */ MCD_OPC_FilterValue, + 33, + 23, + 0, + 0, // Skip to: 3216 + /* 3193 */ MCD_OPC_CheckPredicate, + 22, + 130, + 86, + 0, // Skip to: 25344 + /* 3198 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 123, + 86, + 0, // Skip to: 25344 + /* 3205 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 116, + 86, + 0, // Skip to: 25344 + /* 3212 */ MCD_OPC_Decode, + 158, + 13, + 116, // Opcode: MVE_VST41_16 + /* 3216 */ MCD_OPC_FilterValue, + 65, + 23, + 0, + 0, // Skip to: 3244 + /* 3221 */ MCD_OPC_CheckPredicate, + 22, + 102, + 86, + 0, // Skip to: 25344 + /* 3226 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 95, + 86, + 0, // Skip to: 25344 + /* 3233 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 88, + 86, + 0, // Skip to: 25344 + /* 3240 */ MCD_OPC_Decode, + 164, + 13, + 116, // Opcode: MVE_VST42_16 + /* 3244 */ MCD_OPC_FilterValue, + 97, + 79, + 86, + 0, // Skip to: 25344 + /* 3249 */ MCD_OPC_CheckPredicate, + 22, + 74, + 86, + 0, // Skip to: 25344 + /* 3254 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 67, + 86, + 0, // Skip to: 25344 + /* 3261 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 60, + 86, + 0, // Skip to: 25344 + /* 3268 */ MCD_OPC_Decode, + 170, + 13, + 116, // Opcode: MVE_VST43_16 + /* 3272 */ MCD_OPC_FilterValue, + 1, + 51, + 86, + 0, // Skip to: 25344 + /* 3277 */ MCD_OPC_CheckPredicate, + 22, + 46, + 86, + 0, // Skip to: 25344 + /* 3282 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 39, + 86, + 0, // Skip to: 25344 + /* 3289 */ MCD_OPC_Decode, + 199, + 13, + 119, // Opcode: MVE_VSTRHU16 + /* 3293 */ MCD_OPC_FilterValue, + 1, + 179, + 1, + 0, // Skip to: 3733 + /* 3298 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3301 */ MCD_OPC_FilterValue, + 0, + 222, + 0, + 0, // Skip to: 3528 + /* 3306 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3309 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 3485 + /* 3314 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 3317 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 3345 + /* 3322 */ MCD_OPC_CheckPredicate, + 22, + 1, + 86, + 0, // Skip to: 25344 + /* 3327 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 250, + 85, + 0, // Skip to: 25344 + /* 3334 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 243, + 85, + 0, // Skip to: 25344 + /* 3341 */ MCD_OPC_Decode, + 231, + 8, + 120, // Opcode: MVE_VLD20_8 + /* 3345 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 3373 + /* 3350 */ MCD_OPC_CheckPredicate, + 22, + 229, + 85, + 0, // Skip to: 25344 + /* 3355 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 222, + 85, + 0, // Skip to: 25344 + /* 3362 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 215, + 85, + 0, // Skip to: 25344 + /* 3369 */ MCD_OPC_Decode, + 243, + 8, + 121, // Opcode: MVE_VLD40_8 + /* 3373 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 3401 + /* 3378 */ MCD_OPC_CheckPredicate, + 22, + 201, + 85, + 0, // Skip to: 25344 + /* 3383 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 194, + 85, + 0, // Skip to: 25344 + /* 3390 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 187, + 85, + 0, // Skip to: 25344 + /* 3397 */ MCD_OPC_Decode, + 237, + 8, + 120, // Opcode: MVE_VLD21_8 + /* 3401 */ MCD_OPC_FilterValue, + 33, + 23, + 0, + 0, // Skip to: 3429 + /* 3406 */ MCD_OPC_CheckPredicate, + 22, + 173, + 85, + 0, // Skip to: 25344 + /* 3411 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 166, + 85, + 0, // Skip to: 25344 + /* 3418 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 159, + 85, + 0, // Skip to: 25344 + /* 3425 */ MCD_OPC_Decode, + 249, + 8, + 121, // Opcode: MVE_VLD41_8 + /* 3429 */ MCD_OPC_FilterValue, + 65, + 23, + 0, + 0, // Skip to: 3457 + /* 3434 */ MCD_OPC_CheckPredicate, + 22, + 145, + 85, + 0, // Skip to: 25344 + /* 3439 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 138, + 85, + 0, // Skip to: 25344 + /* 3446 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 131, + 85, + 0, // Skip to: 25344 + /* 3453 */ MCD_OPC_Decode, + 255, + 8, + 121, // Opcode: MVE_VLD42_8 + /* 3457 */ MCD_OPC_FilterValue, + 97, + 122, + 85, + 0, // Skip to: 25344 + /* 3462 */ MCD_OPC_CheckPredicate, + 22, + 117, + 85, + 0, // Skip to: 25344 + /* 3467 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 110, + 85, + 0, // Skip to: 25344 + /* 3474 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 103, + 85, + 0, // Skip to: 25344 + /* 3481 */ MCD_OPC_Decode, + 133, + 9, + 121, // Opcode: MVE_VLD43_8 + /* 3485 */ MCD_OPC_FilterValue, + 1, + 94, + 85, + 0, // Skip to: 25344 + /* 3490 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 3493 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 3507 + /* 3498 */ MCD_OPC_CheckPredicate, + 22, + 81, + 85, + 0, // Skip to: 25344 + /* 3503 */ MCD_OPC_Decode, + 151, + 9, + 117, // Opcode: MVE_VLDRBU8 + /* 3507 */ MCD_OPC_FilterValue, + 15, + 72, + 85, + 0, // Skip to: 25344 + /* 3512 */ MCD_OPC_CheckPredicate, + 22, + 67, + 85, + 0, // Skip to: 25344 + /* 3517 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 60, + 85, + 0, // Skip to: 25344 + /* 3524 */ MCD_OPC_Decode, + 177, + 9, + 118, // Opcode: MVE_VLDRWU32_qi + /* 3528 */ MCD_OPC_FilterValue, + 1, + 51, + 85, + 0, // Skip to: 25344 + /* 3533 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3536 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 3712 + /* 3541 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 3544 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 3572 + /* 3549 */ MCD_OPC_CheckPredicate, + 22, + 30, + 85, + 0, // Skip to: 25344 + /* 3554 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 23, + 85, + 0, // Skip to: 25344 + /* 3561 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 16, + 85, + 0, // Skip to: 25344 + /* 3568 */ MCD_OPC_Decode, + 227, + 8, + 120, // Opcode: MVE_VLD20_16 + /* 3572 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 3600 + /* 3577 */ MCD_OPC_CheckPredicate, + 22, + 2, + 85, + 0, // Skip to: 25344 + /* 3582 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 251, + 84, + 0, // Skip to: 25344 + /* 3589 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 244, + 84, + 0, // Skip to: 25344 + /* 3596 */ MCD_OPC_Decode, + 239, + 8, + 121, // Opcode: MVE_VLD40_16 + /* 3600 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 3628 + /* 3605 */ MCD_OPC_CheckPredicate, + 22, + 230, + 84, + 0, // Skip to: 25344 + /* 3610 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 223, + 84, + 0, // Skip to: 25344 + /* 3617 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 216, + 84, + 0, // Skip to: 25344 + /* 3624 */ MCD_OPC_Decode, + 233, + 8, + 120, // Opcode: MVE_VLD21_16 + /* 3628 */ MCD_OPC_FilterValue, + 33, + 23, + 0, + 0, // Skip to: 3656 + /* 3633 */ MCD_OPC_CheckPredicate, + 22, + 202, + 84, + 0, // Skip to: 25344 + /* 3638 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 195, + 84, + 0, // Skip to: 25344 + /* 3645 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 188, + 84, + 0, // Skip to: 25344 + /* 3652 */ MCD_OPC_Decode, + 245, + 8, + 121, // Opcode: MVE_VLD41_16 + /* 3656 */ MCD_OPC_FilterValue, + 65, + 23, + 0, + 0, // Skip to: 3684 + /* 3661 */ MCD_OPC_CheckPredicate, + 22, + 174, + 84, + 0, // Skip to: 25344 + /* 3666 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 167, + 84, + 0, // Skip to: 25344 + /* 3673 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 160, + 84, + 0, // Skip to: 25344 + /* 3680 */ MCD_OPC_Decode, + 251, + 8, + 121, // Opcode: MVE_VLD42_16 + /* 3684 */ MCD_OPC_FilterValue, + 97, + 151, + 84, + 0, // Skip to: 25344 + /* 3689 */ MCD_OPC_CheckPredicate, + 22, + 146, + 84, + 0, // Skip to: 25344 + /* 3694 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 139, + 84, + 0, // Skip to: 25344 + /* 3701 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 132, + 84, + 0, // Skip to: 25344 + /* 3708 */ MCD_OPC_Decode, + 129, + 9, + 121, // Opcode: MVE_VLD43_16 + /* 3712 */ MCD_OPC_FilterValue, + 1, + 123, + 84, + 0, // Skip to: 25344 + /* 3717 */ MCD_OPC_CheckPredicate, + 22, + 118, + 84, + 0, // Skip to: 25344 + /* 3722 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 111, + 84, + 0, // Skip to: 25344 + /* 3729 */ MCD_OPC_Decode, + 164, + 9, + 119, // Opcode: MVE_VLDRHU16 + /* 3733 */ MCD_OPC_FilterValue, + 2, + 140, + 1, + 0, // Skip to: 4134 + /* 3738 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3741 */ MCD_OPC_FilterValue, + 0, + 202, + 0, + 0, // Skip to: 3948 + /* 3746 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3749 */ MCD_OPC_FilterValue, + 0, + 151, + 0, + 0, // Skip to: 3905 + /* 3754 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 3757 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 3771 + /* 3762 */ MCD_OPC_CheckPredicate, + 22, + 73, + 84, + 0, // Skip to: 25344 + /* 3767 */ MCD_OPC_Decode, + 186, + 13, + 122, // Opcode: MVE_VSTRBU8_post + /* 3771 */ MCD_OPC_FilterValue, + 15, + 64, + 84, + 0, // Skip to: 25344 + /* 3776 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 3779 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3800 + /* 3784 */ MCD_OPC_CheckPredicate, + 22, + 51, + 84, + 0, // Skip to: 25344 + /* 3789 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 44, + 84, + 0, // Skip to: 25344 + /* 3796 */ MCD_OPC_Decode, + 145, + 13, + 123, // Opcode: MVE_VST20_8_wb + /* 3800 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 3821 + /* 3805 */ MCD_OPC_CheckPredicate, + 22, + 30, + 84, + 0, // Skip to: 25344 + /* 3810 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 23, + 84, + 0, // Skip to: 25344 + /* 3817 */ MCD_OPC_Decode, + 157, + 13, + 124, // Opcode: MVE_VST40_8_wb + /* 3821 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 3842 + /* 3826 */ MCD_OPC_CheckPredicate, + 22, + 9, + 84, + 0, // Skip to: 25344 + /* 3831 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 2, + 84, + 0, // Skip to: 25344 + /* 3838 */ MCD_OPC_Decode, + 151, + 13, + 123, // Opcode: MVE_VST21_8_wb + /* 3842 */ MCD_OPC_FilterValue, + 33, + 16, + 0, + 0, // Skip to: 3863 + /* 3847 */ MCD_OPC_CheckPredicate, + 22, + 244, + 83, + 0, // Skip to: 25344 + /* 3852 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 237, + 83, + 0, // Skip to: 25344 + /* 3859 */ MCD_OPC_Decode, + 163, + 13, + 124, // Opcode: MVE_VST41_8_wb + /* 3863 */ MCD_OPC_FilterValue, + 65, + 16, + 0, + 0, // Skip to: 3884 + /* 3868 */ MCD_OPC_CheckPredicate, + 22, + 223, + 83, + 0, // Skip to: 25344 + /* 3873 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 216, + 83, + 0, // Skip to: 25344 + /* 3880 */ MCD_OPC_Decode, + 169, + 13, + 124, // Opcode: MVE_VST42_8_wb + /* 3884 */ MCD_OPC_FilterValue, + 97, + 207, + 83, + 0, // Skip to: 25344 + /* 3889 */ MCD_OPC_CheckPredicate, + 22, + 202, + 83, + 0, // Skip to: 25344 + /* 3894 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 195, + 83, + 0, // Skip to: 25344 + /* 3901 */ MCD_OPC_Decode, + 175, + 13, + 124, // Opcode: MVE_VST43_8_wb + /* 3905 */ MCD_OPC_FilterValue, + 1, + 186, + 83, + 0, // Skip to: 25344 + /* 3910 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 3913 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 3927 + /* 3918 */ MCD_OPC_CheckPredicate, + 22, + 173, + 83, + 0, // Skip to: 25344 + /* 3923 */ MCD_OPC_Decode, + 187, + 13, + 125, // Opcode: MVE_VSTRBU8_pre + /* 3927 */ MCD_OPC_FilterValue, + 15, + 164, + 83, + 0, // Skip to: 25344 + /* 3932 */ MCD_OPC_CheckPredicate, + 22, + 159, + 83, + 0, // Skip to: 25344 + /* 3937 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 152, + 83, + 0, // Skip to: 25344 + /* 3944 */ MCD_OPC_Decode, + 203, + 13, + 126, // Opcode: MVE_VSTRW32_qi_pre + /* 3948 */ MCD_OPC_FilterValue, + 1, + 143, + 83, + 0, // Skip to: 25344 + /* 3953 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3956 */ MCD_OPC_FilterValue, + 0, + 151, + 0, + 0, // Skip to: 4112 + /* 3961 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 3964 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 3978 + /* 3969 */ MCD_OPC_CheckPredicate, + 22, + 122, + 83, + 0, // Skip to: 25344 + /* 3974 */ MCD_OPC_Decode, + 200, + 13, + 127, // Opcode: MVE_VSTRHU16_post + /* 3978 */ MCD_OPC_FilterValue, + 15, + 113, + 83, + 0, // Skip to: 25344 + /* 3983 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 3986 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 4007 + /* 3991 */ MCD_OPC_CheckPredicate, + 22, + 100, + 83, + 0, // Skip to: 25344 + /* 3996 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 93, + 83, + 0, // Skip to: 25344 + /* 4003 */ MCD_OPC_Decode, + 141, + 13, + 123, // Opcode: MVE_VST20_16_wb + /* 4007 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 4028 + /* 4012 */ MCD_OPC_CheckPredicate, + 22, + 79, + 83, + 0, // Skip to: 25344 + /* 4017 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 72, + 83, + 0, // Skip to: 25344 + /* 4024 */ MCD_OPC_Decode, + 153, + 13, + 124, // Opcode: MVE_VST40_16_wb + /* 4028 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 4049 + /* 4033 */ MCD_OPC_CheckPredicate, + 22, + 58, + 83, + 0, // Skip to: 25344 + /* 4038 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 51, + 83, + 0, // Skip to: 25344 + /* 4045 */ MCD_OPC_Decode, + 147, + 13, + 123, // Opcode: MVE_VST21_16_wb + /* 4049 */ MCD_OPC_FilterValue, + 33, + 16, + 0, + 0, // Skip to: 4070 + /* 4054 */ MCD_OPC_CheckPredicate, + 22, + 37, + 83, + 0, // Skip to: 25344 + /* 4059 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 30, + 83, + 0, // Skip to: 25344 + /* 4066 */ MCD_OPC_Decode, + 159, + 13, + 124, // Opcode: MVE_VST41_16_wb + /* 4070 */ MCD_OPC_FilterValue, + 65, + 16, + 0, + 0, // Skip to: 4091 + /* 4075 */ MCD_OPC_CheckPredicate, + 22, + 16, + 83, + 0, // Skip to: 25344 + /* 4080 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 9, + 83, + 0, // Skip to: 25344 + /* 4087 */ MCD_OPC_Decode, + 165, + 13, + 124, // Opcode: MVE_VST42_16_wb + /* 4091 */ MCD_OPC_FilterValue, + 97, + 0, + 83, + 0, // Skip to: 25344 + /* 4096 */ MCD_OPC_CheckPredicate, + 22, + 251, + 82, + 0, // Skip to: 25344 + /* 4101 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 244, + 82, + 0, // Skip to: 25344 + /* 4108 */ MCD_OPC_Decode, + 171, + 13, + 124, // Opcode: MVE_VST43_16_wb + /* 4112 */ MCD_OPC_FilterValue, + 1, + 235, + 82, + 0, // Skip to: 25344 + /* 4117 */ MCD_OPC_CheckPredicate, + 22, + 230, + 82, + 0, // Skip to: 25344 + /* 4122 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 223, + 82, + 0, // Skip to: 25344 + /* 4129 */ MCD_OPC_Decode, + 201, + 13, + 128, + 1, // Opcode: MVE_VSTRHU16_pre + /* 4134 */ MCD_OPC_FilterValue, + 3, + 213, + 82, + 0, // Skip to: 25344 + /* 4139 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4142 */ MCD_OPC_FilterValue, + 0, + 208, + 0, + 0, // Skip to: 4355 + /* 4147 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4150 */ MCD_OPC_FilterValue, + 0, + 157, + 0, + 0, // Skip to: 4312 + /* 4155 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 4158 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 4172 + /* 4163 */ MCD_OPC_CheckPredicate, + 22, + 184, + 82, + 0, // Skip to: 25344 + /* 4168 */ MCD_OPC_Decode, + 152, + 9, + 122, // Opcode: MVE_VLDRBU8_post + /* 4172 */ MCD_OPC_FilterValue, + 15, + 175, + 82, + 0, // Skip to: 25344 + /* 4177 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 4180 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4202 + /* 4185 */ MCD_OPC_CheckPredicate, + 22, + 162, + 82, + 0, // Skip to: 25344 + /* 4190 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 155, + 82, + 0, // Skip to: 25344 + /* 4197 */ MCD_OPC_Decode, + 232, + 8, + 129, + 1, // Opcode: MVE_VLD20_8_wb + /* 4202 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 4224 + /* 4207 */ MCD_OPC_CheckPredicate, + 22, + 140, + 82, + 0, // Skip to: 25344 + /* 4212 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 133, + 82, + 0, // Skip to: 25344 + /* 4219 */ MCD_OPC_Decode, + 244, + 8, + 130, + 1, // Opcode: MVE_VLD40_8_wb + /* 4224 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 4246 + /* 4229 */ MCD_OPC_CheckPredicate, + 22, + 118, + 82, + 0, // Skip to: 25344 + /* 4234 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 111, + 82, + 0, // Skip to: 25344 + /* 4241 */ MCD_OPC_Decode, + 238, + 8, + 129, + 1, // Opcode: MVE_VLD21_8_wb + /* 4246 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 4268 + /* 4251 */ MCD_OPC_CheckPredicate, + 22, + 96, + 82, + 0, // Skip to: 25344 + /* 4256 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 89, + 82, + 0, // Skip to: 25344 + /* 4263 */ MCD_OPC_Decode, + 250, + 8, + 130, + 1, // Opcode: MVE_VLD41_8_wb + /* 4268 */ MCD_OPC_FilterValue, + 65, + 17, + 0, + 0, // Skip to: 4290 + /* 4273 */ MCD_OPC_CheckPredicate, + 22, + 74, + 82, + 0, // Skip to: 25344 + /* 4278 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 67, + 82, + 0, // Skip to: 25344 + /* 4285 */ MCD_OPC_Decode, + 128, + 9, + 130, + 1, // Opcode: MVE_VLD42_8_wb + /* 4290 */ MCD_OPC_FilterValue, + 97, + 57, + 82, + 0, // Skip to: 25344 + /* 4295 */ MCD_OPC_CheckPredicate, + 22, + 52, + 82, + 0, // Skip to: 25344 + /* 4300 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 45, + 82, + 0, // Skip to: 25344 + /* 4307 */ MCD_OPC_Decode, + 134, + 9, + 130, + 1, // Opcode: MVE_VLD43_8_wb + /* 4312 */ MCD_OPC_FilterValue, + 1, + 35, + 82, + 0, // Skip to: 25344 + /* 4317 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 4320 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 4334 + /* 4325 */ MCD_OPC_CheckPredicate, + 22, + 22, + 82, + 0, // Skip to: 25344 + /* 4330 */ MCD_OPC_Decode, + 153, + 9, + 125, // Opcode: MVE_VLDRBU8_pre + /* 4334 */ MCD_OPC_FilterValue, + 15, + 13, + 82, + 0, // Skip to: 25344 + /* 4339 */ MCD_OPC_CheckPredicate, + 22, + 8, + 82, + 0, // Skip to: 25344 + /* 4344 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 1, + 82, + 0, // Skip to: 25344 + /* 4351 */ MCD_OPC_Decode, + 178, + 9, + 126, // Opcode: MVE_VLDRWU32_qi_pre + /* 4355 */ MCD_OPC_FilterValue, + 1, + 248, + 81, + 0, // Skip to: 25344 + /* 4360 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4363 */ MCD_OPC_FilterValue, + 0, + 157, + 0, + 0, // Skip to: 4525 + /* 4368 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 4371 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 4385 + /* 4376 */ MCD_OPC_CheckPredicate, + 22, + 227, + 81, + 0, // Skip to: 25344 + /* 4381 */ MCD_OPC_Decode, + 165, + 9, + 127, // Opcode: MVE_VLDRHU16_post + /* 4385 */ MCD_OPC_FilterValue, + 15, + 218, + 81, + 0, // Skip to: 25344 + /* 4390 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 4393 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4415 + /* 4398 */ MCD_OPC_CheckPredicate, + 22, + 205, + 81, + 0, // Skip to: 25344 + /* 4403 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 198, + 81, + 0, // Skip to: 25344 + /* 4410 */ MCD_OPC_Decode, + 228, + 8, + 129, + 1, // Opcode: MVE_VLD20_16_wb + /* 4415 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 4437 + /* 4420 */ MCD_OPC_CheckPredicate, + 22, + 183, + 81, + 0, // Skip to: 25344 + /* 4425 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 176, + 81, + 0, // Skip to: 25344 + /* 4432 */ MCD_OPC_Decode, + 240, + 8, + 130, + 1, // Opcode: MVE_VLD40_16_wb + /* 4437 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 4459 + /* 4442 */ MCD_OPC_CheckPredicate, + 22, + 161, + 81, + 0, // Skip to: 25344 + /* 4447 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 154, + 81, + 0, // Skip to: 25344 + /* 4454 */ MCD_OPC_Decode, + 234, + 8, + 129, + 1, // Opcode: MVE_VLD21_16_wb + /* 4459 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 4481 + /* 4464 */ MCD_OPC_CheckPredicate, + 22, + 139, + 81, + 0, // Skip to: 25344 + /* 4469 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 132, + 81, + 0, // Skip to: 25344 + /* 4476 */ MCD_OPC_Decode, + 246, + 8, + 130, + 1, // Opcode: MVE_VLD41_16_wb + /* 4481 */ MCD_OPC_FilterValue, + 65, + 17, + 0, + 0, // Skip to: 4503 + /* 4486 */ MCD_OPC_CheckPredicate, + 22, + 117, + 81, + 0, // Skip to: 25344 + /* 4491 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 110, + 81, + 0, // Skip to: 25344 + /* 4498 */ MCD_OPC_Decode, + 252, + 8, + 130, + 1, // Opcode: MVE_VLD42_16_wb + /* 4503 */ MCD_OPC_FilterValue, + 97, + 100, + 81, + 0, // Skip to: 25344 + /* 4508 */ MCD_OPC_CheckPredicate, + 22, + 95, + 81, + 0, // Skip to: 25344 + /* 4513 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 88, + 81, + 0, // Skip to: 25344 + /* 4520 */ MCD_OPC_Decode, + 130, + 9, + 130, + 1, // Opcode: MVE_VLD43_16_wb + /* 4525 */ MCD_OPC_FilterValue, + 1, + 78, + 81, + 0, // Skip to: 25344 + /* 4530 */ MCD_OPC_CheckPredicate, + 22, + 73, + 81, + 0, // Skip to: 25344 + /* 4535 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 66, + 81, + 0, // Skip to: 25344 + /* 4542 */ MCD_OPC_Decode, + 166, + 9, + 128, + 1, // Opcode: MVE_VLDRHU16_pre + /* 4547 */ MCD_OPC_FilterValue, + 31, + 56, + 81, + 0, // Skip to: 25344 + /* 4552 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 4555 */ MCD_OPC_FilterValue, + 0, + 238, + 0, + 0, // Skip to: 4798 + /* 4560 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4563 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 4739 + /* 4568 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 4571 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 4599 + /* 4576 */ MCD_OPC_CheckPredicate, + 22, + 27, + 81, + 0, // Skip to: 25344 + /* 4581 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 20, + 81, + 0, // Skip to: 25344 + /* 4588 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 13, + 81, + 0, // Skip to: 25344 + /* 4595 */ MCD_OPC_Decode, + 142, + 13, + 115, // Opcode: MVE_VST20_32 + /* 4599 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 4627 + /* 4604 */ MCD_OPC_CheckPredicate, + 22, + 255, + 80, + 0, // Skip to: 25344 + /* 4609 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 248, + 80, + 0, // Skip to: 25344 + /* 4616 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 241, + 80, + 0, // Skip to: 25344 + /* 4623 */ MCD_OPC_Decode, + 154, + 13, + 116, // Opcode: MVE_VST40_32 + /* 4627 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 4655 + /* 4632 */ MCD_OPC_CheckPredicate, + 22, + 227, + 80, + 0, // Skip to: 25344 + /* 4637 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 220, + 80, + 0, // Skip to: 25344 + /* 4644 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 213, + 80, + 0, // Skip to: 25344 + /* 4651 */ MCD_OPC_Decode, + 148, + 13, + 115, // Opcode: MVE_VST21_32 + /* 4655 */ MCD_OPC_FilterValue, + 33, + 23, + 0, + 0, // Skip to: 4683 + /* 4660 */ MCD_OPC_CheckPredicate, + 22, + 199, + 80, + 0, // Skip to: 25344 + /* 4665 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 192, + 80, + 0, // Skip to: 25344 + /* 4672 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 185, + 80, + 0, // Skip to: 25344 + /* 4679 */ MCD_OPC_Decode, + 160, + 13, + 116, // Opcode: MVE_VST41_32 + /* 4683 */ MCD_OPC_FilterValue, + 65, + 23, + 0, + 0, // Skip to: 4711 + /* 4688 */ MCD_OPC_CheckPredicate, + 22, + 171, + 80, + 0, // Skip to: 25344 + /* 4693 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 164, + 80, + 0, // Skip to: 25344 + /* 4700 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 157, + 80, + 0, // Skip to: 25344 + /* 4707 */ MCD_OPC_Decode, + 166, + 13, + 116, // Opcode: MVE_VST42_32 + /* 4711 */ MCD_OPC_FilterValue, + 97, + 148, + 80, + 0, // Skip to: 25344 + /* 4716 */ MCD_OPC_CheckPredicate, + 22, + 143, + 80, + 0, // Skip to: 25344 + /* 4721 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 136, + 80, + 0, // Skip to: 25344 + /* 4728 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 129, + 80, + 0, // Skip to: 25344 + /* 4735 */ MCD_OPC_Decode, + 172, + 13, + 116, // Opcode: MVE_VST43_32 + /* 4739 */ MCD_OPC_FilterValue, + 1, + 120, + 80, + 0, // Skip to: 25344 + /* 4744 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 4747 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 4769 + /* 4752 */ MCD_OPC_CheckPredicate, + 22, + 107, + 80, + 0, // Skip to: 25344 + /* 4757 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 100, + 80, + 0, // Skip to: 25344 + /* 4764 */ MCD_OPC_Decode, + 206, + 13, + 131, + 1, // Opcode: MVE_VSTRWU32 + /* 4769 */ MCD_OPC_FilterValue, + 15, + 90, + 80, + 0, // Skip to: 25344 + /* 4774 */ MCD_OPC_CheckPredicate, + 22, + 85, + 80, + 0, // Skip to: 25344 + /* 4779 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 78, + 80, + 0, // Skip to: 25344 + /* 4786 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 71, + 80, + 0, // Skip to: 25344 + /* 4793 */ MCD_OPC_Decode, + 188, + 13, + 132, + 1, // Opcode: MVE_VSTRD64_qi + /* 4798 */ MCD_OPC_FilterValue, + 1, + 238, + 0, + 0, // Skip to: 5041 + /* 4803 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4806 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 4982 + /* 4811 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 4814 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 4842 + /* 4819 */ MCD_OPC_CheckPredicate, + 22, + 40, + 80, + 0, // Skip to: 25344 + /* 4824 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 33, + 80, + 0, // Skip to: 25344 + /* 4831 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 26, + 80, + 0, // Skip to: 25344 + /* 4838 */ MCD_OPC_Decode, + 229, + 8, + 120, // Opcode: MVE_VLD20_32 + /* 4842 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 4870 + /* 4847 */ MCD_OPC_CheckPredicate, + 22, + 12, + 80, + 0, // Skip to: 25344 + /* 4852 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 5, + 80, + 0, // Skip to: 25344 + /* 4859 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 254, + 79, + 0, // Skip to: 25344 + /* 4866 */ MCD_OPC_Decode, + 241, + 8, + 121, // Opcode: MVE_VLD40_32 + /* 4870 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 4898 + /* 4875 */ MCD_OPC_CheckPredicate, + 22, + 240, + 79, + 0, // Skip to: 25344 + /* 4880 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 233, + 79, + 0, // Skip to: 25344 + /* 4887 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 226, + 79, + 0, // Skip to: 25344 + /* 4894 */ MCD_OPC_Decode, + 235, + 8, + 120, // Opcode: MVE_VLD21_32 + /* 4898 */ MCD_OPC_FilterValue, + 33, + 23, + 0, + 0, // Skip to: 4926 + /* 4903 */ MCD_OPC_CheckPredicate, + 22, + 212, + 79, + 0, // Skip to: 25344 + /* 4908 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 205, + 79, + 0, // Skip to: 25344 + /* 4915 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 198, + 79, + 0, // Skip to: 25344 + /* 4922 */ MCD_OPC_Decode, + 247, + 8, + 121, // Opcode: MVE_VLD41_32 + /* 4926 */ MCD_OPC_FilterValue, + 65, + 23, + 0, + 0, // Skip to: 4954 + /* 4931 */ MCD_OPC_CheckPredicate, + 22, + 184, + 79, + 0, // Skip to: 25344 + /* 4936 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 177, + 79, + 0, // Skip to: 25344 + /* 4943 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 170, + 79, + 0, // Skip to: 25344 + /* 4950 */ MCD_OPC_Decode, + 253, + 8, + 121, // Opcode: MVE_VLD42_32 + /* 4954 */ MCD_OPC_FilterValue, + 97, + 161, + 79, + 0, // Skip to: 25344 + /* 4959 */ MCD_OPC_CheckPredicate, + 22, + 156, + 79, + 0, // Skip to: 25344 + /* 4964 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 149, + 79, + 0, // Skip to: 25344 + /* 4971 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 142, + 79, + 0, // Skip to: 25344 + /* 4978 */ MCD_OPC_Decode, + 131, + 9, + 121, // Opcode: MVE_VLD43_32 + /* 4982 */ MCD_OPC_FilterValue, + 1, + 133, + 79, + 0, // Skip to: 25344 + /* 4987 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 4990 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5012 + /* 4995 */ MCD_OPC_CheckPredicate, + 22, + 120, + 79, + 0, // Skip to: 25344 + /* 5000 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 113, + 79, + 0, // Skip to: 25344 + /* 5007 */ MCD_OPC_Decode, + 174, + 9, + 131, + 1, // Opcode: MVE_VLDRWU32 + /* 5012 */ MCD_OPC_FilterValue, + 15, + 103, + 79, + 0, // Skip to: 25344 + /* 5017 */ MCD_OPC_CheckPredicate, + 22, + 98, + 79, + 0, // Skip to: 25344 + /* 5022 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 91, + 79, + 0, // Skip to: 25344 + /* 5029 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 84, + 79, + 0, // Skip to: 25344 + /* 5036 */ MCD_OPC_Decode, + 155, + 9, + 132, + 1, // Opcode: MVE_VLDRDU64_qi + /* 5041 */ MCD_OPC_FilterValue, + 2, + 226, + 0, + 0, // Skip to: 5272 + /* 5046 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 5049 */ MCD_OPC_FilterValue, + 0, + 159, + 0, + 0, // Skip to: 5213 + /* 5054 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5057 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5079 + /* 5062 */ MCD_OPC_CheckPredicate, + 22, + 53, + 79, + 0, // Skip to: 25344 + /* 5067 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 46, + 79, + 0, // Skip to: 25344 + /* 5074 */ MCD_OPC_Decode, + 207, + 13, + 133, + 1, // Opcode: MVE_VSTRWU32_post + /* 5079 */ MCD_OPC_FilterValue, + 15, + 36, + 79, + 0, // Skip to: 25344 + /* 5084 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 5087 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 5108 + /* 5092 */ MCD_OPC_CheckPredicate, + 22, + 23, + 79, + 0, // Skip to: 25344 + /* 5097 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 16, + 79, + 0, // Skip to: 25344 + /* 5104 */ MCD_OPC_Decode, + 143, + 13, + 123, // Opcode: MVE_VST20_32_wb + /* 5108 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 5129 + /* 5113 */ MCD_OPC_CheckPredicate, + 22, + 2, + 79, + 0, // Skip to: 25344 + /* 5118 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 251, + 78, + 0, // Skip to: 25344 + /* 5125 */ MCD_OPC_Decode, + 155, + 13, + 124, // Opcode: MVE_VST40_32_wb + /* 5129 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 5150 + /* 5134 */ MCD_OPC_CheckPredicate, + 22, + 237, + 78, + 0, // Skip to: 25344 + /* 5139 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 230, + 78, + 0, // Skip to: 25344 + /* 5146 */ MCD_OPC_Decode, + 149, + 13, + 123, // Opcode: MVE_VST21_32_wb + /* 5150 */ MCD_OPC_FilterValue, + 33, + 16, + 0, + 0, // Skip to: 5171 + /* 5155 */ MCD_OPC_CheckPredicate, + 22, + 216, + 78, + 0, // Skip to: 25344 + /* 5160 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 209, + 78, + 0, // Skip to: 25344 + /* 5167 */ MCD_OPC_Decode, + 161, + 13, + 124, // Opcode: MVE_VST41_32_wb + /* 5171 */ MCD_OPC_FilterValue, + 65, + 16, + 0, + 0, // Skip to: 5192 + /* 5176 */ MCD_OPC_CheckPredicate, + 22, + 195, + 78, + 0, // Skip to: 25344 + /* 5181 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 188, + 78, + 0, // Skip to: 25344 + /* 5188 */ MCD_OPC_Decode, + 167, + 13, + 124, // Opcode: MVE_VST42_32_wb + /* 5192 */ MCD_OPC_FilterValue, + 97, + 179, + 78, + 0, // Skip to: 25344 + /* 5197 */ MCD_OPC_CheckPredicate, + 22, + 174, + 78, + 0, // Skip to: 25344 + /* 5202 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 167, + 78, + 0, // Skip to: 25344 + /* 5209 */ MCD_OPC_Decode, + 173, + 13, + 124, // Opcode: MVE_VST43_32_wb + /* 5213 */ MCD_OPC_FilterValue, + 1, + 158, + 78, + 0, // Skip to: 25344 + /* 5218 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5221 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5243 + /* 5226 */ MCD_OPC_CheckPredicate, + 22, + 145, + 78, + 0, // Skip to: 25344 + /* 5231 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 138, + 78, + 0, // Skip to: 25344 + /* 5238 */ MCD_OPC_Decode, + 208, + 13, + 134, + 1, // Opcode: MVE_VSTRWU32_pre + /* 5243 */ MCD_OPC_FilterValue, + 15, + 128, + 78, + 0, // Skip to: 25344 + /* 5248 */ MCD_OPC_CheckPredicate, + 22, + 123, + 78, + 0, // Skip to: 25344 + /* 5253 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 116, + 78, + 0, // Skip to: 25344 + /* 5260 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 109, + 78, + 0, // Skip to: 25344 + /* 5267 */ MCD_OPC_Decode, + 189, + 13, + 135, + 1, // Opcode: MVE_VSTRD64_qi_pre + /* 5272 */ MCD_OPC_FilterValue, + 3, + 99, + 78, + 0, // Skip to: 25344 + /* 5277 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 5280 */ MCD_OPC_FilterValue, + 0, + 165, + 0, + 0, // Skip to: 5450 + /* 5285 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5288 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5310 + /* 5293 */ MCD_OPC_CheckPredicate, + 22, + 78, + 78, + 0, // Skip to: 25344 + /* 5298 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 71, + 78, + 0, // Skip to: 25344 + /* 5305 */ MCD_OPC_Decode, + 175, + 9, + 133, + 1, // Opcode: MVE_VLDRWU32_post + /* 5310 */ MCD_OPC_FilterValue, + 15, + 61, + 78, + 0, // Skip to: 25344 + /* 5315 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 5318 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 5340 + /* 5323 */ MCD_OPC_CheckPredicate, + 22, + 48, + 78, + 0, // Skip to: 25344 + /* 5328 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 41, + 78, + 0, // Skip to: 25344 + /* 5335 */ MCD_OPC_Decode, + 230, + 8, + 129, + 1, // Opcode: MVE_VLD20_32_wb + /* 5340 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 5362 + /* 5345 */ MCD_OPC_CheckPredicate, + 22, + 26, + 78, + 0, // Skip to: 25344 + /* 5350 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 19, + 78, + 0, // Skip to: 25344 + /* 5357 */ MCD_OPC_Decode, + 242, + 8, + 130, + 1, // Opcode: MVE_VLD40_32_wb + /* 5362 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 5384 + /* 5367 */ MCD_OPC_CheckPredicate, + 22, + 4, + 78, + 0, // Skip to: 25344 + /* 5372 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 253, + 77, + 0, // Skip to: 25344 + /* 5379 */ MCD_OPC_Decode, + 236, + 8, + 129, + 1, // Opcode: MVE_VLD21_32_wb + /* 5384 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 5406 + /* 5389 */ MCD_OPC_CheckPredicate, + 22, + 238, + 77, + 0, // Skip to: 25344 + /* 5394 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 231, + 77, + 0, // Skip to: 25344 + /* 5401 */ MCD_OPC_Decode, + 248, + 8, + 130, + 1, // Opcode: MVE_VLD41_32_wb + /* 5406 */ MCD_OPC_FilterValue, + 65, + 17, + 0, + 0, // Skip to: 5428 + /* 5411 */ MCD_OPC_CheckPredicate, + 22, + 216, + 77, + 0, // Skip to: 25344 + /* 5416 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 209, + 77, + 0, // Skip to: 25344 + /* 5423 */ MCD_OPC_Decode, + 254, + 8, + 130, + 1, // Opcode: MVE_VLD42_32_wb + /* 5428 */ MCD_OPC_FilterValue, + 97, + 199, + 77, + 0, // Skip to: 25344 + /* 5433 */ MCD_OPC_CheckPredicate, + 22, + 194, + 77, + 0, // Skip to: 25344 + /* 5438 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 187, + 77, + 0, // Skip to: 25344 + /* 5445 */ MCD_OPC_Decode, + 132, + 9, + 130, + 1, // Opcode: MVE_VLD43_32_wb + /* 5450 */ MCD_OPC_FilterValue, + 1, + 177, + 77, + 0, // Skip to: 25344 + /* 5455 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5458 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5480 + /* 5463 */ MCD_OPC_CheckPredicate, + 22, + 164, + 77, + 0, // Skip to: 25344 + /* 5468 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 157, + 77, + 0, // Skip to: 25344 + /* 5475 */ MCD_OPC_Decode, + 176, + 9, + 134, + 1, // Opcode: MVE_VLDRWU32_pre + /* 5480 */ MCD_OPC_FilterValue, + 15, + 147, + 77, + 0, // Skip to: 25344 + /* 5485 */ MCD_OPC_CheckPredicate, + 22, + 142, + 77, + 0, // Skip to: 25344 + /* 5490 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 135, + 77, + 0, // Skip to: 25344 + /* 5497 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 128, + 77, + 0, // Skip to: 25344 + /* 5504 */ MCD_OPC_Decode, + 156, + 9, + 135, + 1, // Opcode: MVE_VLDRDU64_qi_pre + /* 5509 */ MCD_OPC_FilterValue, + 7, + 118, + 77, + 0, // Skip to: 25344 + /* 5514 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 5517 */ MCD_OPC_FilterValue, + 0, + 179, + 28, + 0, // Skip to: 12869 + /* 5522 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 5525 */ MCD_OPC_FilterValue, + 11, + 195, + 0, + 0, // Skip to: 5725 + /* 5530 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5533 */ MCD_OPC_FilterValue, + 0, + 91, + 0, + 0, // Skip to: 5629 + /* 5538 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5541 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 5600 + /* 5546 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 5549 */ MCD_OPC_FilterValue, + 16, + 24, + 0, + 0, // Skip to: 5578 + /* 5554 */ MCD_OPC_CheckPredicate, + 25, + 73, + 77, + 0, // Skip to: 25344 + /* 5559 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 66, + 77, + 0, // Skip to: 25344 + /* 5566 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 59, + 77, + 0, // Skip to: 25344 + /* 5573 */ MCD_OPC_Decode, + 181, + 10, + 136, + 1, // Opcode: MVE_VMOV_to_lane_32 + /* 5578 */ MCD_OPC_FilterValue, + 48, + 49, + 77, + 0, // Skip to: 25344 + /* 5583 */ MCD_OPC_CheckPredicate, + 23, + 44, + 77, + 0, // Skip to: 25344 + /* 5588 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 37, + 77, + 0, // Skip to: 25344 + /* 5595 */ MCD_OPC_Decode, + 180, + 10, + 137, + 1, // Opcode: MVE_VMOV_to_lane_16 + /* 5600 */ MCD_OPC_FilterValue, + 1, + 27, + 77, + 0, // Skip to: 25344 + /* 5605 */ MCD_OPC_CheckPredicate, + 23, + 22, + 77, + 0, // Skip to: 25344 + /* 5610 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 15, + 77, + 0, // Skip to: 25344 + /* 5617 */ MCD_OPC_CheckField, + 0, + 5, + 16, + 8, + 77, + 0, // Skip to: 25344 + /* 5624 */ MCD_OPC_Decode, + 182, + 10, + 138, + 1, // Opcode: MVE_VMOV_to_lane_8 + /* 5629 */ MCD_OPC_FilterValue, + 1, + 254, + 76, + 0, // Skip to: 25344 + /* 5634 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5637 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 5696 + /* 5642 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 5645 */ MCD_OPC_FilterValue, + 16, + 24, + 0, + 0, // Skip to: 5674 + /* 5650 */ MCD_OPC_CheckPredicate, + 25, + 233, + 76, + 0, // Skip to: 25344 + /* 5655 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 226, + 76, + 0, // Skip to: 25344 + /* 5662 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 219, + 76, + 0, // Skip to: 25344 + /* 5669 */ MCD_OPC_Decode, + 173, + 10, + 139, + 1, // Opcode: MVE_VMOV_from_lane_32 + /* 5674 */ MCD_OPC_FilterValue, + 48, + 209, + 76, + 0, // Skip to: 25344 + /* 5679 */ MCD_OPC_CheckPredicate, + 23, + 204, + 76, + 0, // Skip to: 25344 + /* 5684 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 197, + 76, + 0, // Skip to: 25344 + /* 5691 */ MCD_OPC_Decode, + 174, + 10, + 140, + 1, // Opcode: MVE_VMOV_from_lane_s16 + /* 5696 */ MCD_OPC_FilterValue, + 1, + 187, + 76, + 0, // Skip to: 25344 + /* 5701 */ MCD_OPC_CheckPredicate, + 23, + 182, + 76, + 0, // Skip to: 25344 + /* 5706 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 175, + 76, + 0, // Skip to: 25344 + /* 5713 */ MCD_OPC_CheckField, + 0, + 5, + 16, + 168, + 76, + 0, // Skip to: 25344 + /* 5720 */ MCD_OPC_Decode, + 175, + 10, + 141, + 1, // Opcode: MVE_VMOV_from_lane_s8 + /* 5725 */ MCD_OPC_FilterValue, + 14, + 175, + 16, + 0, // Skip to: 10001 + /* 5730 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5733 */ MCD_OPC_FilterValue, + 0, + 227, + 2, + 0, // Skip to: 6477 + /* 5738 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5741 */ MCD_OPC_FilterValue, + 0, + 211, + 1, + 0, // Skip to: 6213 + /* 5746 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 5749 */ MCD_OPC_FilterValue, + 0, + 227, + 0, + 0, // Skip to: 5981 + /* 5754 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 5757 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 5869 + /* 5762 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 5765 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 5817 + /* 5770 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5773 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5795 + /* 5778 */ MCD_OPC_CheckPredicate, + 22, + 105, + 76, + 0, // Skip to: 25344 + /* 5783 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 98, + 76, + 0, // Skip to: 25344 + /* 5790 */ MCD_OPC_Decode, + 149, + 11, + 142, + 1, // Opcode: MVE_VQDMLADHs8 + /* 5795 */ MCD_OPC_FilterValue, + 15, + 88, + 76, + 0, // Skip to: 25344 + /* 5800 */ MCD_OPC_CheckPredicate, + 22, + 83, + 76, + 0, // Skip to: 25344 + /* 5805 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 76, + 76, + 0, // Skip to: 25344 + /* 5812 */ MCD_OPC_Decode, + 161, + 11, + 142, + 1, // Opcode: MVE_VQDMLSDHs8 + /* 5817 */ MCD_OPC_FilterValue, + 1, + 66, + 76, + 0, // Skip to: 25344 + /* 5822 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5825 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5847 + /* 5830 */ MCD_OPC_CheckPredicate, + 22, + 53, + 76, + 0, // Skip to: 25344 + /* 5835 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 46, + 76, + 0, // Skip to: 25344 + /* 5842 */ MCD_OPC_Decode, + 198, + 10, + 143, + 1, // Opcode: MVE_VMULLBs8 + /* 5847 */ MCD_OPC_FilterValue, + 15, + 36, + 76, + 0, // Skip to: 25344 + /* 5852 */ MCD_OPC_CheckPredicate, + 22, + 31, + 76, + 0, // Skip to: 25344 + /* 5857 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 24, + 76, + 0, // Skip to: 25344 + /* 5864 */ MCD_OPC_Decode, + 201, + 10, + 143, + 1, // Opcode: MVE_VMULLBu8 + /* 5869 */ MCD_OPC_FilterValue, + 1, + 14, + 76, + 0, // Skip to: 25344 + /* 5874 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 5877 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 5929 + /* 5882 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5885 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5907 + /* 5890 */ MCD_OPC_CheckPredicate, + 22, + 249, + 75, + 0, // Skip to: 25344 + /* 5895 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 242, + 75, + 0, // Skip to: 25344 + /* 5902 */ MCD_OPC_Decode, + 146, + 11, + 142, + 1, // Opcode: MVE_VQDMLADHXs8 + /* 5907 */ MCD_OPC_FilterValue, + 15, + 232, + 75, + 0, // Skip to: 25344 + /* 5912 */ MCD_OPC_CheckPredicate, + 22, + 227, + 75, + 0, // Skip to: 25344 + /* 5917 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 220, + 75, + 0, // Skip to: 25344 + /* 5924 */ MCD_OPC_Decode, + 158, + 11, + 142, + 1, // Opcode: MVE_VQDMLSDHXs8 + /* 5929 */ MCD_OPC_FilterValue, + 1, + 210, + 75, + 0, // Skip to: 25344 + /* 5934 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5937 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5959 + /* 5942 */ MCD_OPC_CheckPredicate, + 22, + 197, + 75, + 0, // Skip to: 25344 + /* 5947 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 190, + 75, + 0, // Skip to: 25344 + /* 5954 */ MCD_OPC_Decode, + 206, + 10, + 143, + 1, // Opcode: MVE_VMULLTs8 + /* 5959 */ MCD_OPC_FilterValue, + 15, + 180, + 75, + 0, // Skip to: 25344 + /* 5964 */ MCD_OPC_CheckPredicate, + 22, + 175, + 75, + 0, // Skip to: 25344 + /* 5969 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 168, + 75, + 0, // Skip to: 25344 + /* 5976 */ MCD_OPC_Decode, + 209, + 10, + 143, + 1, // Opcode: MVE_VMULLTu8 + /* 5981 */ MCD_OPC_FilterValue, + 1, + 158, + 75, + 0, // Skip to: 25344 + /* 5986 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 5989 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 6101 + /* 5994 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 5997 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6049 + /* 6002 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6005 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6027 + /* 6010 */ MCD_OPC_CheckPredicate, + 22, + 129, + 75, + 0, // Skip to: 25344 + /* 6015 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 122, + 75, + 0, // Skip to: 25344 + /* 6022 */ MCD_OPC_Decode, + 196, + 11, + 142, + 1, // Opcode: MVE_VQRDMLADHs8 + /* 6027 */ MCD_OPC_FilterValue, + 15, + 112, + 75, + 0, // Skip to: 25344 + /* 6032 */ MCD_OPC_CheckPredicate, + 22, + 107, + 75, + 0, // Skip to: 25344 + /* 6037 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 100, + 75, + 0, // Skip to: 25344 + /* 6044 */ MCD_OPC_Decode, + 208, + 11, + 142, + 1, // Opcode: MVE_VQRDMLSDHs8 + /* 6049 */ MCD_OPC_FilterValue, + 1, + 90, + 75, + 0, // Skip to: 25344 + /* 6054 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6057 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6079 + /* 6062 */ MCD_OPC_CheckPredicate, + 22, + 77, + 75, + 0, // Skip to: 25344 + /* 6067 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 70, + 75, + 0, // Skip to: 25344 + /* 6074 */ MCD_OPC_Decode, + 190, + 10, + 143, + 1, // Opcode: MVE_VMULHs8 + /* 6079 */ MCD_OPC_FilterValue, + 15, + 60, + 75, + 0, // Skip to: 25344 + /* 6084 */ MCD_OPC_CheckPredicate, + 22, + 55, + 75, + 0, // Skip to: 25344 + /* 6089 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 48, + 75, + 0, // Skip to: 25344 + /* 6096 */ MCD_OPC_Decode, + 193, + 10, + 143, + 1, // Opcode: MVE_VMULHu8 + /* 6101 */ MCD_OPC_FilterValue, + 1, + 38, + 75, + 0, // Skip to: 25344 + /* 6106 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6109 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6161 + /* 6114 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6117 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6139 + /* 6122 */ MCD_OPC_CheckPredicate, + 22, + 17, + 75, + 0, // Skip to: 25344 + /* 6127 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 10, + 75, + 0, // Skip to: 25344 + /* 6134 */ MCD_OPC_Decode, + 193, + 11, + 142, + 1, // Opcode: MVE_VQRDMLADHXs8 + /* 6139 */ MCD_OPC_FilterValue, + 15, + 0, + 75, + 0, // Skip to: 25344 + /* 6144 */ MCD_OPC_CheckPredicate, + 22, + 251, + 74, + 0, // Skip to: 25344 + /* 6149 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 244, + 74, + 0, // Skip to: 25344 + /* 6156 */ MCD_OPC_Decode, + 205, + 11, + 142, + 1, // Opcode: MVE_VQRDMLSDHXs8 + /* 6161 */ MCD_OPC_FilterValue, + 1, + 234, + 74, + 0, // Skip to: 25344 + /* 6166 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6169 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6191 + /* 6174 */ MCD_OPC_CheckPredicate, + 22, + 221, + 74, + 0, // Skip to: 25344 + /* 6179 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 214, + 74, + 0, // Skip to: 25344 + /* 6186 */ MCD_OPC_Decode, + 192, + 12, + 143, + 1, // Opcode: MVE_VRMULHs8 + /* 6191 */ MCD_OPC_FilterValue, + 15, + 204, + 74, + 0, // Skip to: 25344 + /* 6196 */ MCD_OPC_CheckPredicate, + 22, + 199, + 74, + 0, // Skip to: 25344 + /* 6201 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 192, + 74, + 0, // Skip to: 25344 + /* 6208 */ MCD_OPC_Decode, + 195, + 12, + 143, + 1, // Opcode: MVE_VRMULHu8 + /* 6213 */ MCD_OPC_FilterValue, + 1, + 182, + 74, + 0, // Skip to: 25344 + /* 6218 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 6221 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 6333 + /* 6226 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 6229 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6281 + /* 6234 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6237 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6259 + /* 6242 */ MCD_OPC_CheckPredicate, + 22, + 153, + 74, + 0, // Skip to: 25344 + /* 6247 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 146, + 74, + 0, // Skip to: 25344 + /* 6254 */ MCD_OPC_Decode, + 199, + 11, + 144, + 1, // Opcode: MVE_VQRDMLAH_qrs8 + /* 6259 */ MCD_OPC_FilterValue, + 1, + 136, + 74, + 0, // Skip to: 25344 + /* 6264 */ MCD_OPC_CheckPredicate, + 22, + 131, + 74, + 0, // Skip to: 25344 + /* 6269 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 124, + 74, + 0, // Skip to: 25344 + /* 6276 */ MCD_OPC_Decode, + 140, + 10, + 144, + 1, // Opcode: MVE_VMLA_qr_i8 + /* 6281 */ MCD_OPC_FilterValue, + 1, + 114, + 74, + 0, // Skip to: 25344 + /* 6286 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6289 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6311 + /* 6294 */ MCD_OPC_CheckPredicate, + 22, + 101, + 74, + 0, // Skip to: 25344 + /* 6299 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 94, + 74, + 0, // Skip to: 25344 + /* 6306 */ MCD_OPC_Decode, + 202, + 11, + 144, + 1, // Opcode: MVE_VQRDMLASH_qrs8 + /* 6311 */ MCD_OPC_FilterValue, + 1, + 84, + 74, + 0, // Skip to: 25344 + /* 6316 */ MCD_OPC_CheckPredicate, + 22, + 79, + 74, + 0, // Skip to: 25344 + /* 6321 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 72, + 74, + 0, // Skip to: 25344 + /* 6328 */ MCD_OPC_Decode, + 137, + 10, + 144, + 1, // Opcode: MVE_VMLAS_qr_i8 + /* 6333 */ MCD_OPC_FilterValue, + 2, + 62, + 74, + 0, // Skip to: 25344 + /* 6338 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 6341 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 6409 + /* 6346 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6349 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6371 + /* 6354 */ MCD_OPC_CheckPredicate, + 22, + 41, + 74, + 0, // Skip to: 25344 + /* 6359 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 34, + 74, + 0, // Skip to: 25344 + /* 6366 */ MCD_OPC_Decode, + 152, + 11, + 144, + 1, // Opcode: MVE_VQDMLAH_qrs8 + /* 6371 */ MCD_OPC_FilterValue, + 1, + 24, + 74, + 0, // Skip to: 25344 + /* 6376 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6379 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 6394 + /* 6384 */ MCD_OPC_CheckPredicate, + 22, + 11, + 74, + 0, // Skip to: 25344 + /* 6389 */ MCD_OPC_Decode, + 164, + 11, + 145, + 1, // Opcode: MVE_VQDMULH_qr_s8 + /* 6394 */ MCD_OPC_FilterValue, + 15, + 1, + 74, + 0, // Skip to: 25344 + /* 6399 */ MCD_OPC_CheckPredicate, + 22, + 252, + 73, + 0, // Skip to: 25344 + /* 6404 */ MCD_OPC_Decode, + 211, + 11, + 145, + 1, // Opcode: MVE_VQRDMULH_qr_s8 + /* 6409 */ MCD_OPC_FilterValue, + 1, + 242, + 73, + 0, // Skip to: 25344 + /* 6414 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6417 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6439 + /* 6422 */ MCD_OPC_CheckPredicate, + 22, + 229, + 73, + 0, // Skip to: 25344 + /* 6427 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 222, + 73, + 0, // Skip to: 25344 + /* 6434 */ MCD_OPC_Decode, + 155, + 11, + 144, + 1, // Opcode: MVE_VQDMLASH_qrs8 + /* 6439 */ MCD_OPC_FilterValue, + 1, + 212, + 73, + 0, // Skip to: 25344 + /* 6444 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6447 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 6462 + /* 6452 */ MCD_OPC_CheckPredicate, + 22, + 199, + 73, + 0, // Skip to: 25344 + /* 6457 */ MCD_OPC_Decode, + 214, + 10, + 145, + 1, // Opcode: MVE_VMUL_qr_i8 + /* 6462 */ MCD_OPC_FilterValue, + 15, + 189, + 73, + 0, // Skip to: 25344 + /* 6467 */ MCD_OPC_CheckPredicate, + 22, + 184, + 73, + 0, // Skip to: 25344 + /* 6472 */ MCD_OPC_Decode, + 226, + 7, + 145, + 1, // Opcode: MVE_VBRSR8 + /* 6477 */ MCD_OPC_FilterValue, + 1, + 227, + 2, + 0, // Skip to: 7221 + /* 6482 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6485 */ MCD_OPC_FilterValue, + 0, + 211, + 1, + 0, // Skip to: 6957 + /* 6490 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 6493 */ MCD_OPC_FilterValue, + 0, + 227, + 0, + 0, // Skip to: 6725 + /* 6498 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 6501 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 6613 + /* 6506 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6509 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6561 + /* 6514 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6517 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6539 + /* 6522 */ MCD_OPC_CheckPredicate, + 22, + 129, + 73, + 0, // Skip to: 25344 + /* 6527 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 122, + 73, + 0, // Skip to: 25344 + /* 6534 */ MCD_OPC_Decode, + 147, + 11, + 142, + 1, // Opcode: MVE_VQDMLADHs16 + /* 6539 */ MCD_OPC_FilterValue, + 15, + 112, + 73, + 0, // Skip to: 25344 + /* 6544 */ MCD_OPC_CheckPredicate, + 22, + 107, + 73, + 0, // Skip to: 25344 + /* 6549 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 100, + 73, + 0, // Skip to: 25344 + /* 6556 */ MCD_OPC_Decode, + 159, + 11, + 142, + 1, // Opcode: MVE_VQDMLSDHs16 + /* 6561 */ MCD_OPC_FilterValue, + 1, + 90, + 73, + 0, // Skip to: 25344 + /* 6566 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6569 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6591 + /* 6574 */ MCD_OPC_CheckPredicate, + 22, + 77, + 73, + 0, // Skip to: 25344 + /* 6579 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 70, + 73, + 0, // Skip to: 25344 + /* 6586 */ MCD_OPC_Decode, + 196, + 10, + 143, + 1, // Opcode: MVE_VMULLBs16 + /* 6591 */ MCD_OPC_FilterValue, + 15, + 60, + 73, + 0, // Skip to: 25344 + /* 6596 */ MCD_OPC_CheckPredicate, + 22, + 55, + 73, + 0, // Skip to: 25344 + /* 6601 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 48, + 73, + 0, // Skip to: 25344 + /* 6608 */ MCD_OPC_Decode, + 199, + 10, + 143, + 1, // Opcode: MVE_VMULLBu16 + /* 6613 */ MCD_OPC_FilterValue, + 1, + 38, + 73, + 0, // Skip to: 25344 + /* 6618 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6621 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6673 + /* 6626 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6629 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6651 + /* 6634 */ MCD_OPC_CheckPredicate, + 22, + 17, + 73, + 0, // Skip to: 25344 + /* 6639 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 10, + 73, + 0, // Skip to: 25344 + /* 6646 */ MCD_OPC_Decode, + 144, + 11, + 142, + 1, // Opcode: MVE_VQDMLADHXs16 + /* 6651 */ MCD_OPC_FilterValue, + 15, + 0, + 73, + 0, // Skip to: 25344 + /* 6656 */ MCD_OPC_CheckPredicate, + 22, + 251, + 72, + 0, // Skip to: 25344 + /* 6661 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 244, + 72, + 0, // Skip to: 25344 + /* 6668 */ MCD_OPC_Decode, + 156, + 11, + 142, + 1, // Opcode: MVE_VQDMLSDHXs16 + /* 6673 */ MCD_OPC_FilterValue, + 1, + 234, + 72, + 0, // Skip to: 25344 + /* 6678 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6681 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6703 + /* 6686 */ MCD_OPC_CheckPredicate, + 22, + 221, + 72, + 0, // Skip to: 25344 + /* 6691 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 214, + 72, + 0, // Skip to: 25344 + /* 6698 */ MCD_OPC_Decode, + 204, + 10, + 143, + 1, // Opcode: MVE_VMULLTs16 + /* 6703 */ MCD_OPC_FilterValue, + 15, + 204, + 72, + 0, // Skip to: 25344 + /* 6708 */ MCD_OPC_CheckPredicate, + 22, + 199, + 72, + 0, // Skip to: 25344 + /* 6713 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 192, + 72, + 0, // Skip to: 25344 + /* 6720 */ MCD_OPC_Decode, + 207, + 10, + 143, + 1, // Opcode: MVE_VMULLTu16 + /* 6725 */ MCD_OPC_FilterValue, + 1, + 182, + 72, + 0, // Skip to: 25344 + /* 6730 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 6733 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 6845 + /* 6738 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6741 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6793 + /* 6746 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6749 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6771 + /* 6754 */ MCD_OPC_CheckPredicate, + 22, + 153, + 72, + 0, // Skip to: 25344 + /* 6759 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 146, + 72, + 0, // Skip to: 25344 + /* 6766 */ MCD_OPC_Decode, + 194, + 11, + 142, + 1, // Opcode: MVE_VQRDMLADHs16 + /* 6771 */ MCD_OPC_FilterValue, + 15, + 136, + 72, + 0, // Skip to: 25344 + /* 6776 */ MCD_OPC_CheckPredicate, + 22, + 131, + 72, + 0, // Skip to: 25344 + /* 6781 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 124, + 72, + 0, // Skip to: 25344 + /* 6788 */ MCD_OPC_Decode, + 206, + 11, + 142, + 1, // Opcode: MVE_VQRDMLSDHs16 + /* 6793 */ MCD_OPC_FilterValue, + 1, + 114, + 72, + 0, // Skip to: 25344 + /* 6798 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6801 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6823 + /* 6806 */ MCD_OPC_CheckPredicate, + 22, + 101, + 72, + 0, // Skip to: 25344 + /* 6811 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 94, + 72, + 0, // Skip to: 25344 + /* 6818 */ MCD_OPC_Decode, + 188, + 10, + 143, + 1, // Opcode: MVE_VMULHs16 + /* 6823 */ MCD_OPC_FilterValue, + 15, + 84, + 72, + 0, // Skip to: 25344 + /* 6828 */ MCD_OPC_CheckPredicate, + 22, + 79, + 72, + 0, // Skip to: 25344 + /* 6833 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 72, + 72, + 0, // Skip to: 25344 + /* 6840 */ MCD_OPC_Decode, + 191, + 10, + 143, + 1, // Opcode: MVE_VMULHu16 + /* 6845 */ MCD_OPC_FilterValue, + 1, + 62, + 72, + 0, // Skip to: 25344 + /* 6850 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6853 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6905 + /* 6858 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6861 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6883 + /* 6866 */ MCD_OPC_CheckPredicate, + 22, + 41, + 72, + 0, // Skip to: 25344 + /* 6871 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 34, + 72, + 0, // Skip to: 25344 + /* 6878 */ MCD_OPC_Decode, + 191, + 11, + 142, + 1, // Opcode: MVE_VQRDMLADHXs16 + /* 6883 */ MCD_OPC_FilterValue, + 15, + 24, + 72, + 0, // Skip to: 25344 + /* 6888 */ MCD_OPC_CheckPredicate, + 22, + 19, + 72, + 0, // Skip to: 25344 + /* 6893 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 12, + 72, + 0, // Skip to: 25344 + /* 6900 */ MCD_OPC_Decode, + 203, + 11, + 142, + 1, // Opcode: MVE_VQRDMLSDHXs16 + /* 6905 */ MCD_OPC_FilterValue, + 1, + 2, + 72, + 0, // Skip to: 25344 + /* 6910 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6913 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6935 + /* 6918 */ MCD_OPC_CheckPredicate, + 22, + 245, + 71, + 0, // Skip to: 25344 + /* 6923 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 238, + 71, + 0, // Skip to: 25344 + /* 6930 */ MCD_OPC_Decode, + 190, + 12, + 143, + 1, // Opcode: MVE_VRMULHs16 + /* 6935 */ MCD_OPC_FilterValue, + 15, + 228, + 71, + 0, // Skip to: 25344 + /* 6940 */ MCD_OPC_CheckPredicate, + 22, + 223, + 71, + 0, // Skip to: 25344 + /* 6945 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 216, + 71, + 0, // Skip to: 25344 + /* 6952 */ MCD_OPC_Decode, + 193, + 12, + 143, + 1, // Opcode: MVE_VRMULHu16 + /* 6957 */ MCD_OPC_FilterValue, + 1, + 206, + 71, + 0, // Skip to: 25344 + /* 6962 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 6965 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 7077 + /* 6970 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 6973 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 7025 + /* 6978 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6981 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7003 + /* 6986 */ MCD_OPC_CheckPredicate, + 22, + 177, + 71, + 0, // Skip to: 25344 + /* 6991 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 170, + 71, + 0, // Skip to: 25344 + /* 6998 */ MCD_OPC_Decode, + 197, + 11, + 144, + 1, // Opcode: MVE_VQRDMLAH_qrs16 + /* 7003 */ MCD_OPC_FilterValue, + 1, + 160, + 71, + 0, // Skip to: 25344 + /* 7008 */ MCD_OPC_CheckPredicate, + 22, + 155, + 71, + 0, // Skip to: 25344 + /* 7013 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 148, + 71, + 0, // Skip to: 25344 + /* 7020 */ MCD_OPC_Decode, + 138, + 10, + 144, + 1, // Opcode: MVE_VMLA_qr_i16 + /* 7025 */ MCD_OPC_FilterValue, + 1, + 138, + 71, + 0, // Skip to: 25344 + /* 7030 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7033 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7055 + /* 7038 */ MCD_OPC_CheckPredicate, + 22, + 125, + 71, + 0, // Skip to: 25344 + /* 7043 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 118, + 71, + 0, // Skip to: 25344 + /* 7050 */ MCD_OPC_Decode, + 200, + 11, + 144, + 1, // Opcode: MVE_VQRDMLASH_qrs16 + /* 7055 */ MCD_OPC_FilterValue, + 1, + 108, + 71, + 0, // Skip to: 25344 + /* 7060 */ MCD_OPC_CheckPredicate, + 22, + 103, + 71, + 0, // Skip to: 25344 + /* 7065 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 96, + 71, + 0, // Skip to: 25344 + /* 7072 */ MCD_OPC_Decode, + 135, + 10, + 144, + 1, // Opcode: MVE_VMLAS_qr_i16 + /* 7077 */ MCD_OPC_FilterValue, + 2, + 86, + 71, + 0, // Skip to: 25344 + /* 7082 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 7085 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 7153 + /* 7090 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7093 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7115 + /* 7098 */ MCD_OPC_CheckPredicate, + 22, + 65, + 71, + 0, // Skip to: 25344 + /* 7103 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 58, + 71, + 0, // Skip to: 25344 + /* 7110 */ MCD_OPC_Decode, + 150, + 11, + 144, + 1, // Opcode: MVE_VQDMLAH_qrs16 + /* 7115 */ MCD_OPC_FilterValue, + 1, + 48, + 71, + 0, // Skip to: 25344 + /* 7120 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7123 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7138 + /* 7128 */ MCD_OPC_CheckPredicate, + 22, + 35, + 71, + 0, // Skip to: 25344 + /* 7133 */ MCD_OPC_Decode, + 162, + 11, + 145, + 1, // Opcode: MVE_VQDMULH_qr_s16 + /* 7138 */ MCD_OPC_FilterValue, + 15, + 25, + 71, + 0, // Skip to: 25344 + /* 7143 */ MCD_OPC_CheckPredicate, + 22, + 20, + 71, + 0, // Skip to: 25344 + /* 7148 */ MCD_OPC_Decode, + 209, + 11, + 145, + 1, // Opcode: MVE_VQRDMULH_qr_s16 + /* 7153 */ MCD_OPC_FilterValue, + 1, + 10, + 71, + 0, // Skip to: 25344 + /* 7158 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7161 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7183 + /* 7166 */ MCD_OPC_CheckPredicate, + 22, + 253, + 70, + 0, // Skip to: 25344 + /* 7171 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 246, + 70, + 0, // Skip to: 25344 + /* 7178 */ MCD_OPC_Decode, + 153, + 11, + 144, + 1, // Opcode: MVE_VQDMLASH_qrs16 + /* 7183 */ MCD_OPC_FilterValue, + 1, + 236, + 70, + 0, // Skip to: 25344 + /* 7188 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7191 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7206 + /* 7196 */ MCD_OPC_CheckPredicate, + 22, + 223, + 70, + 0, // Skip to: 25344 + /* 7201 */ MCD_OPC_Decode, + 212, + 10, + 145, + 1, // Opcode: MVE_VMUL_qr_i16 + /* 7206 */ MCD_OPC_FilterValue, + 15, + 213, + 70, + 0, // Skip to: 25344 + /* 7211 */ MCD_OPC_CheckPredicate, + 22, + 208, + 70, + 0, // Skip to: 25344 + /* 7216 */ MCD_OPC_Decode, + 224, + 7, + 145, + 1, // Opcode: MVE_VBRSR16 + /* 7221 */ MCD_OPC_FilterValue, + 2, + 227, + 2, + 0, // Skip to: 7965 + /* 7226 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 7229 */ MCD_OPC_FilterValue, + 0, + 211, + 1, + 0, // Skip to: 7701 + /* 7234 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 7237 */ MCD_OPC_FilterValue, + 0, + 227, + 0, + 0, // Skip to: 7469 + /* 7242 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 7245 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 7357 + /* 7250 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7253 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 7305 + /* 7258 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7261 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7283 + /* 7266 */ MCD_OPC_CheckPredicate, + 22, + 153, + 70, + 0, // Skip to: 25344 + /* 7271 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 146, + 70, + 0, // Skip to: 25344 + /* 7278 */ MCD_OPC_Decode, + 148, + 11, + 142, + 1, // Opcode: MVE_VQDMLADHs32 + /* 7283 */ MCD_OPC_FilterValue, + 15, + 136, + 70, + 0, // Skip to: 25344 + /* 7288 */ MCD_OPC_CheckPredicate, + 22, + 131, + 70, + 0, // Skip to: 25344 + /* 7293 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 124, + 70, + 0, // Skip to: 25344 + /* 7300 */ MCD_OPC_Decode, + 160, + 11, + 142, + 1, // Opcode: MVE_VQDMLSDHs32 + /* 7305 */ MCD_OPC_FilterValue, + 1, + 114, + 70, + 0, // Skip to: 25344 + /* 7310 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7313 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7335 + /* 7318 */ MCD_OPC_CheckPredicate, + 22, + 101, + 70, + 0, // Skip to: 25344 + /* 7323 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 94, + 70, + 0, // Skip to: 25344 + /* 7330 */ MCD_OPC_Decode, + 197, + 10, + 143, + 1, // Opcode: MVE_VMULLBs32 + /* 7335 */ MCD_OPC_FilterValue, + 15, + 84, + 70, + 0, // Skip to: 25344 + /* 7340 */ MCD_OPC_CheckPredicate, + 22, + 79, + 70, + 0, // Skip to: 25344 + /* 7345 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 72, + 70, + 0, // Skip to: 25344 + /* 7352 */ MCD_OPC_Decode, + 200, + 10, + 143, + 1, // Opcode: MVE_VMULLBu32 + /* 7357 */ MCD_OPC_FilterValue, + 1, + 62, + 70, + 0, // Skip to: 25344 + /* 7362 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7365 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 7417 + /* 7370 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7373 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7395 + /* 7378 */ MCD_OPC_CheckPredicate, + 22, + 41, + 70, + 0, // Skip to: 25344 + /* 7383 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 34, + 70, + 0, // Skip to: 25344 + /* 7390 */ MCD_OPC_Decode, + 145, + 11, + 142, + 1, // Opcode: MVE_VQDMLADHXs32 + /* 7395 */ MCD_OPC_FilterValue, + 15, + 24, + 70, + 0, // Skip to: 25344 + /* 7400 */ MCD_OPC_CheckPredicate, + 22, + 19, + 70, + 0, // Skip to: 25344 + /* 7405 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 12, + 70, + 0, // Skip to: 25344 + /* 7412 */ MCD_OPC_Decode, + 157, + 11, + 142, + 1, // Opcode: MVE_VQDMLSDHXs32 + /* 7417 */ MCD_OPC_FilterValue, + 1, + 2, + 70, + 0, // Skip to: 25344 + /* 7422 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7425 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7447 + /* 7430 */ MCD_OPC_CheckPredicate, + 22, + 245, + 69, + 0, // Skip to: 25344 + /* 7435 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 238, + 69, + 0, // Skip to: 25344 + /* 7442 */ MCD_OPC_Decode, + 205, + 10, + 143, + 1, // Opcode: MVE_VMULLTs32 + /* 7447 */ MCD_OPC_FilterValue, + 15, + 228, + 69, + 0, // Skip to: 25344 + /* 7452 */ MCD_OPC_CheckPredicate, + 22, + 223, + 69, + 0, // Skip to: 25344 + /* 7457 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 216, + 69, + 0, // Skip to: 25344 + /* 7464 */ MCD_OPC_Decode, + 208, + 10, + 143, + 1, // Opcode: MVE_VMULLTu32 + /* 7469 */ MCD_OPC_FilterValue, + 1, + 206, + 69, + 0, // Skip to: 25344 + /* 7474 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 7477 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 7589 + /* 7482 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7485 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 7537 + /* 7490 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7493 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7515 + /* 7498 */ MCD_OPC_CheckPredicate, + 22, + 177, + 69, + 0, // Skip to: 25344 + /* 7503 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 170, + 69, + 0, // Skip to: 25344 + /* 7510 */ MCD_OPC_Decode, + 195, + 11, + 142, + 1, // Opcode: MVE_VQRDMLADHs32 + /* 7515 */ MCD_OPC_FilterValue, + 15, + 160, + 69, + 0, // Skip to: 25344 + /* 7520 */ MCD_OPC_CheckPredicate, + 22, + 155, + 69, + 0, // Skip to: 25344 + /* 7525 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 148, + 69, + 0, // Skip to: 25344 + /* 7532 */ MCD_OPC_Decode, + 207, + 11, + 142, + 1, // Opcode: MVE_VQRDMLSDHs32 + /* 7537 */ MCD_OPC_FilterValue, + 1, + 138, + 69, + 0, // Skip to: 25344 + /* 7542 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7545 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7567 + /* 7550 */ MCD_OPC_CheckPredicate, + 22, + 125, + 69, + 0, // Skip to: 25344 + /* 7555 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 118, + 69, + 0, // Skip to: 25344 + /* 7562 */ MCD_OPC_Decode, + 189, + 10, + 143, + 1, // Opcode: MVE_VMULHs32 + /* 7567 */ MCD_OPC_FilterValue, + 15, + 108, + 69, + 0, // Skip to: 25344 + /* 7572 */ MCD_OPC_CheckPredicate, + 22, + 103, + 69, + 0, // Skip to: 25344 + /* 7577 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 96, + 69, + 0, // Skip to: 25344 + /* 7584 */ MCD_OPC_Decode, + 192, + 10, + 143, + 1, // Opcode: MVE_VMULHu32 + /* 7589 */ MCD_OPC_FilterValue, + 1, + 86, + 69, + 0, // Skip to: 25344 + /* 7594 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7597 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 7649 + /* 7602 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7605 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7627 + /* 7610 */ MCD_OPC_CheckPredicate, + 22, + 65, + 69, + 0, // Skip to: 25344 + /* 7615 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 58, + 69, + 0, // Skip to: 25344 + /* 7622 */ MCD_OPC_Decode, + 192, + 11, + 142, + 1, // Opcode: MVE_VQRDMLADHXs32 + /* 7627 */ MCD_OPC_FilterValue, + 15, + 48, + 69, + 0, // Skip to: 25344 + /* 7632 */ MCD_OPC_CheckPredicate, + 22, + 43, + 69, + 0, // Skip to: 25344 + /* 7637 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 36, + 69, + 0, // Skip to: 25344 + /* 7644 */ MCD_OPC_Decode, + 204, + 11, + 142, + 1, // Opcode: MVE_VQRDMLSDHXs32 + /* 7649 */ MCD_OPC_FilterValue, + 1, + 26, + 69, + 0, // Skip to: 25344 + /* 7654 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7657 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7679 + /* 7662 */ MCD_OPC_CheckPredicate, + 22, + 13, + 69, + 0, // Skip to: 25344 + /* 7667 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 6, + 69, + 0, // Skip to: 25344 + /* 7674 */ MCD_OPC_Decode, + 191, + 12, + 143, + 1, // Opcode: MVE_VRMULHs32 + /* 7679 */ MCD_OPC_FilterValue, + 15, + 252, + 68, + 0, // Skip to: 25344 + /* 7684 */ MCD_OPC_CheckPredicate, + 22, + 247, + 68, + 0, // Skip to: 25344 + /* 7689 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 240, + 68, + 0, // Skip to: 25344 + /* 7696 */ MCD_OPC_Decode, + 194, + 12, + 143, + 1, // Opcode: MVE_VRMULHu32 + /* 7701 */ MCD_OPC_FilterValue, + 1, + 230, + 68, + 0, // Skip to: 25344 + /* 7706 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 7709 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 7821 + /* 7714 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 7717 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 7769 + /* 7722 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7725 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7747 + /* 7730 */ MCD_OPC_CheckPredicate, + 22, + 201, + 68, + 0, // Skip to: 25344 + /* 7735 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 194, + 68, + 0, // Skip to: 25344 + /* 7742 */ MCD_OPC_Decode, + 198, + 11, + 144, + 1, // Opcode: MVE_VQRDMLAH_qrs32 + /* 7747 */ MCD_OPC_FilterValue, + 1, + 184, + 68, + 0, // Skip to: 25344 + /* 7752 */ MCD_OPC_CheckPredicate, + 22, + 179, + 68, + 0, // Skip to: 25344 + /* 7757 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 172, + 68, + 0, // Skip to: 25344 + /* 7764 */ MCD_OPC_Decode, + 139, + 10, + 144, + 1, // Opcode: MVE_VMLA_qr_i32 + /* 7769 */ MCD_OPC_FilterValue, + 1, + 162, + 68, + 0, // Skip to: 25344 + /* 7774 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7777 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7799 + /* 7782 */ MCD_OPC_CheckPredicate, + 22, + 149, + 68, + 0, // Skip to: 25344 + /* 7787 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 142, + 68, + 0, // Skip to: 25344 + /* 7794 */ MCD_OPC_Decode, + 201, + 11, + 144, + 1, // Opcode: MVE_VQRDMLASH_qrs32 + /* 7799 */ MCD_OPC_FilterValue, + 1, + 132, + 68, + 0, // Skip to: 25344 + /* 7804 */ MCD_OPC_CheckPredicate, + 22, + 127, + 68, + 0, // Skip to: 25344 + /* 7809 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 120, + 68, + 0, // Skip to: 25344 + /* 7816 */ MCD_OPC_Decode, + 136, + 10, + 144, + 1, // Opcode: MVE_VMLAS_qr_i32 + /* 7821 */ MCD_OPC_FilterValue, + 2, + 110, + 68, + 0, // Skip to: 25344 + /* 7826 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 7829 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 7897 + /* 7834 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7837 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7859 + /* 7842 */ MCD_OPC_CheckPredicate, + 22, + 89, + 68, + 0, // Skip to: 25344 + /* 7847 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 82, + 68, + 0, // Skip to: 25344 + /* 7854 */ MCD_OPC_Decode, + 151, + 11, + 144, + 1, // Opcode: MVE_VQDMLAH_qrs32 + /* 7859 */ MCD_OPC_FilterValue, + 1, + 72, + 68, + 0, // Skip to: 25344 + /* 7864 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7867 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7882 + /* 7872 */ MCD_OPC_CheckPredicate, + 22, + 59, + 68, + 0, // Skip to: 25344 + /* 7877 */ MCD_OPC_Decode, + 163, + 11, + 145, + 1, // Opcode: MVE_VQDMULH_qr_s32 + /* 7882 */ MCD_OPC_FilterValue, + 15, + 49, + 68, + 0, // Skip to: 25344 + /* 7887 */ MCD_OPC_CheckPredicate, + 22, + 44, + 68, + 0, // Skip to: 25344 + /* 7892 */ MCD_OPC_Decode, + 210, + 11, + 145, + 1, // Opcode: MVE_VQRDMULH_qr_s32 + /* 7897 */ MCD_OPC_FilterValue, + 1, + 34, + 68, + 0, // Skip to: 25344 + /* 7902 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7905 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7927 + /* 7910 */ MCD_OPC_CheckPredicate, + 22, + 21, + 68, + 0, // Skip to: 25344 + /* 7915 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 14, + 68, + 0, // Skip to: 25344 + /* 7922 */ MCD_OPC_Decode, + 154, + 11, + 144, + 1, // Opcode: MVE_VQDMLASH_qrs32 + /* 7927 */ MCD_OPC_FilterValue, + 1, + 4, + 68, + 0, // Skip to: 25344 + /* 7932 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7935 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7950 + /* 7940 */ MCD_OPC_CheckPredicate, + 22, + 247, + 67, + 0, // Skip to: 25344 + /* 7945 */ MCD_OPC_Decode, + 213, + 10, + 145, + 1, // Opcode: MVE_VMUL_qr_i32 + /* 7950 */ MCD_OPC_FilterValue, + 15, + 237, + 67, + 0, // Skip to: 25344 + /* 7955 */ MCD_OPC_CheckPredicate, + 22, + 232, + 67, + 0, // Skip to: 25344 + /* 7960 */ MCD_OPC_Decode, + 225, + 7, + 145, + 1, // Opcode: MVE_VBRSR32 + /* 7965 */ MCD_OPC_FilterValue, + 3, + 222, + 67, + 0, // Skip to: 25344 + /* 7970 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 7973 */ MCD_OPC_FilterValue, + 0, + 51, + 5, + 0, // Skip to: 9309 + /* 7978 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7981 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8033 + /* 7986 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7989 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8011 + /* 7994 */ MCD_OPC_CheckPredicate, + 24, + 193, + 67, + 0, // Skip to: 25344 + /* 7999 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 186, + 67, + 0, // Skip to: 25344 + /* 8006 */ MCD_OPC_Decode, + 134, + 8, + 146, + 1, // Opcode: MVE_VCMULf16 + /* 8011 */ MCD_OPC_FilterValue, + 15, + 176, + 67, + 0, // Skip to: 25344 + /* 8016 */ MCD_OPC_CheckPredicate, + 24, + 171, + 67, + 0, // Skip to: 25344 + /* 8021 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 164, + 67, + 0, // Skip to: 25344 + /* 8028 */ MCD_OPC_Decode, + 135, + 8, + 146, + 1, // Opcode: MVE_VCMULf32 + /* 8033 */ MCD_OPC_FilterValue, + 1, + 154, + 67, + 0, // Skip to: 25344 + /* 8038 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 8041 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 8153 + /* 8046 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8049 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8101 + /* 8054 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8057 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8079 + /* 8062 */ MCD_OPC_CheckPredicate, + 22, + 125, + 67, + 0, // Skip to: 25344 + /* 8067 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 118, + 67, + 0, // Skip to: 25344 + /* 8074 */ MCD_OPC_Decode, + 195, + 10, + 143, + 1, // Opcode: MVE_VMULLBp8 + /* 8079 */ MCD_OPC_FilterValue, + 15, + 108, + 67, + 0, // Skip to: 25344 + /* 8084 */ MCD_OPC_CheckPredicate, + 22, + 103, + 67, + 0, // Skip to: 25344 + /* 8089 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 96, + 67, + 0, // Skip to: 25344 + /* 8096 */ MCD_OPC_Decode, + 194, + 10, + 143, + 1, // Opcode: MVE_VMULLBp16 + /* 8101 */ MCD_OPC_FilterValue, + 1, + 86, + 67, + 0, // Skip to: 25344 + /* 8106 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8109 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8131 + /* 8114 */ MCD_OPC_CheckPredicate, + 22, + 73, + 67, + 0, // Skip to: 25344 + /* 8119 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 66, + 67, + 0, // Skip to: 25344 + /* 8126 */ MCD_OPC_Decode, + 203, + 10, + 143, + 1, // Opcode: MVE_VMULLTp8 + /* 8131 */ MCD_OPC_FilterValue, + 15, + 56, + 67, + 0, // Skip to: 25344 + /* 8136 */ MCD_OPC_CheckPredicate, + 22, + 51, + 67, + 0, // Skip to: 25344 + /* 8141 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 44, + 67, + 0, // Skip to: 25344 + /* 8148 */ MCD_OPC_Decode, + 202, + 10, + 143, + 1, // Opcode: MVE_VMULLTp16 + /* 8153 */ MCD_OPC_FilterValue, + 1, + 34, + 67, + 0, // Skip to: 25344 + /* 8158 */ MCD_OPC_ExtractField, + 17, + 3, // Inst{19-17} ... + /* 8161 */ MCD_OPC_FilterValue, + 0, + 227, + 0, + 0, // Skip to: 8393 + /* 8166 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 8169 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 8281 + /* 8174 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8177 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8229 + /* 8182 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8185 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8207 + /* 8190 */ MCD_OPC_CheckPredicate, + 22, + 253, + 66, + 0, // Skip to: 25344 + /* 8195 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 246, + 66, + 0, // Skip to: 25344 + /* 8202 */ MCD_OPC_Decode, + 231, + 12, + 147, + 1, // Opcode: MVE_VSHLL_lws8bh + /* 8207 */ MCD_OPC_FilterValue, + 15, + 236, + 66, + 0, // Skip to: 25344 + /* 8212 */ MCD_OPC_CheckPredicate, + 22, + 231, + 66, + 0, // Skip to: 25344 + /* 8217 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 224, + 66, + 0, // Skip to: 25344 + /* 8224 */ MCD_OPC_Decode, + 235, + 12, + 147, + 1, // Opcode: MVE_VSHLL_lwu8bh + /* 8229 */ MCD_OPC_FilterValue, + 1, + 214, + 66, + 0, // Skip to: 25344 + /* 8234 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8237 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8259 + /* 8242 */ MCD_OPC_CheckPredicate, + 22, + 201, + 66, + 0, // Skip to: 25344 + /* 8247 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 194, + 66, + 0, // Skip to: 25344 + /* 8254 */ MCD_OPC_Decode, + 232, + 12, + 147, + 1, // Opcode: MVE_VSHLL_lws8th + /* 8259 */ MCD_OPC_FilterValue, + 15, + 184, + 66, + 0, // Skip to: 25344 + /* 8264 */ MCD_OPC_CheckPredicate, + 22, + 179, + 66, + 0, // Skip to: 25344 + /* 8269 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 172, + 66, + 0, // Skip to: 25344 + /* 8276 */ MCD_OPC_Decode, + 236, + 12, + 147, + 1, // Opcode: MVE_VSHLL_lwu8th + /* 8281 */ MCD_OPC_FilterValue, + 1, + 162, + 66, + 0, // Skip to: 25344 + /* 8286 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8289 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8341 + /* 8294 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8297 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8319 + /* 8302 */ MCD_OPC_CheckPredicate, + 22, + 141, + 66, + 0, // Skip to: 25344 + /* 8307 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 134, + 66, + 0, // Skip to: 25344 + /* 8314 */ MCD_OPC_Decode, + 184, + 11, + 148, + 1, // Opcode: MVE_VQMOVUNs16bh + /* 8319 */ MCD_OPC_FilterValue, + 15, + 124, + 66, + 0, // Skip to: 25344 + /* 8324 */ MCD_OPC_CheckPredicate, + 22, + 119, + 66, + 0, // Skip to: 25344 + /* 8329 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 112, + 66, + 0, // Skip to: 25344 + /* 8336 */ MCD_OPC_Decode, + 169, + 10, + 148, + 1, // Opcode: MVE_VMOVNi16bh + /* 8341 */ MCD_OPC_FilterValue, + 1, + 102, + 66, + 0, // Skip to: 25344 + /* 8346 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8349 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8371 + /* 8354 */ MCD_OPC_CheckPredicate, + 22, + 89, + 66, + 0, // Skip to: 25344 + /* 8359 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 82, + 66, + 0, // Skip to: 25344 + /* 8366 */ MCD_OPC_Decode, + 185, + 11, + 148, + 1, // Opcode: MVE_VQMOVUNs16th + /* 8371 */ MCD_OPC_FilterValue, + 15, + 72, + 66, + 0, // Skip to: 25344 + /* 8376 */ MCD_OPC_CheckPredicate, + 22, + 67, + 66, + 0, // Skip to: 25344 + /* 8381 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 60, + 66, + 0, // Skip to: 25344 + /* 8388 */ MCD_OPC_Decode, + 170, + 10, + 148, + 1, // Opcode: MVE_VMOVNi16th + /* 8393 */ MCD_OPC_FilterValue, + 1, + 181, + 0, + 0, // Skip to: 8579 + /* 8398 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 8401 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 8513 + /* 8406 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8409 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8461 + /* 8414 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8417 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8439 + /* 8422 */ MCD_OPC_CheckPredicate, + 22, + 21, + 66, + 0, // Skip to: 25344 + /* 8427 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 14, + 66, + 0, // Skip to: 25344 + /* 8434 */ MCD_OPC_Decode, + 176, + 11, + 148, + 1, // Opcode: MVE_VQMOVNs16bh + /* 8439 */ MCD_OPC_FilterValue, + 15, + 4, + 66, + 0, // Skip to: 25344 + /* 8444 */ MCD_OPC_CheckPredicate, + 22, + 255, + 65, + 0, // Skip to: 25344 + /* 8449 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 248, + 65, + 0, // Skip to: 25344 + /* 8456 */ MCD_OPC_Decode, + 180, + 11, + 148, + 1, // Opcode: MVE_VQMOVNu16bh + /* 8461 */ MCD_OPC_FilterValue, + 1, + 238, + 65, + 0, // Skip to: 25344 + /* 8466 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8469 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8491 + /* 8474 */ MCD_OPC_CheckPredicate, + 22, + 225, + 65, + 0, // Skip to: 25344 + /* 8479 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 218, + 65, + 0, // Skip to: 25344 + /* 8486 */ MCD_OPC_Decode, + 177, + 11, + 148, + 1, // Opcode: MVE_VQMOVNs16th + /* 8491 */ MCD_OPC_FilterValue, + 15, + 208, + 65, + 0, // Skip to: 25344 + /* 8496 */ MCD_OPC_CheckPredicate, + 22, + 203, + 65, + 0, // Skip to: 25344 + /* 8501 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 196, + 65, + 0, // Skip to: 25344 + /* 8508 */ MCD_OPC_Decode, + 181, + 11, + 148, + 1, // Opcode: MVE_VQMOVNu16th + /* 8513 */ MCD_OPC_FilterValue, + 1, + 186, + 65, + 0, // Skip to: 25344 + /* 8518 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8521 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 8550 + /* 8526 */ MCD_OPC_CheckPredicate, + 22, + 173, + 65, + 0, // Skip to: 25344 + /* 8531 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 166, + 65, + 0, // Skip to: 25344 + /* 8538 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 159, + 65, + 0, // Skip to: 25344 + /* 8545 */ MCD_OPC_Decode, + 186, + 9, + 148, + 1, // Opcode: MVE_VMAXAs8 + /* 8550 */ MCD_OPC_FilterValue, + 1, + 149, + 65, + 0, // Skip to: 25344 + /* 8555 */ MCD_OPC_CheckPredicate, + 22, + 144, + 65, + 0, // Skip to: 25344 + /* 8560 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 137, + 65, + 0, // Skip to: 25344 + /* 8567 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 130, + 65, + 0, // Skip to: 25344 + /* 8574 */ MCD_OPC_Decode, + 212, + 9, + 148, + 1, // Opcode: MVE_VMINAs8 + /* 8579 */ MCD_OPC_FilterValue, + 2, + 227, + 0, + 0, // Skip to: 8811 + /* 8584 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 8587 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 8699 + /* 8592 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8595 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8647 + /* 8600 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8603 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8625 + /* 8608 */ MCD_OPC_CheckPredicate, + 22, + 91, + 65, + 0, // Skip to: 25344 + /* 8613 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 84, + 65, + 0, // Skip to: 25344 + /* 8620 */ MCD_OPC_Decode, + 229, + 12, + 147, + 1, // Opcode: MVE_VSHLL_lws16bh + /* 8625 */ MCD_OPC_FilterValue, + 15, + 74, + 65, + 0, // Skip to: 25344 + /* 8630 */ MCD_OPC_CheckPredicate, + 22, + 69, + 65, + 0, // Skip to: 25344 + /* 8635 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 62, + 65, + 0, // Skip to: 25344 + /* 8642 */ MCD_OPC_Decode, + 233, + 12, + 147, + 1, // Opcode: MVE_VSHLL_lwu16bh + /* 8647 */ MCD_OPC_FilterValue, + 1, + 52, + 65, + 0, // Skip to: 25344 + /* 8652 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8655 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8677 + /* 8660 */ MCD_OPC_CheckPredicate, + 22, + 39, + 65, + 0, // Skip to: 25344 + /* 8665 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 32, + 65, + 0, // Skip to: 25344 + /* 8672 */ MCD_OPC_Decode, + 230, + 12, + 147, + 1, // Opcode: MVE_VSHLL_lws16th + /* 8677 */ MCD_OPC_FilterValue, + 15, + 22, + 65, + 0, // Skip to: 25344 + /* 8682 */ MCD_OPC_CheckPredicate, + 22, + 17, + 65, + 0, // Skip to: 25344 + /* 8687 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 10, + 65, + 0, // Skip to: 25344 + /* 8694 */ MCD_OPC_Decode, + 234, + 12, + 147, + 1, // Opcode: MVE_VSHLL_lwu16th + /* 8699 */ MCD_OPC_FilterValue, + 1, + 0, + 65, + 0, // Skip to: 25344 + /* 8704 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8707 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8759 + /* 8712 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8715 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8737 + /* 8720 */ MCD_OPC_CheckPredicate, + 22, + 235, + 64, + 0, // Skip to: 25344 + /* 8725 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 228, + 64, + 0, // Skip to: 25344 + /* 8732 */ MCD_OPC_Decode, + 186, + 11, + 148, + 1, // Opcode: MVE_VQMOVUNs32bh + /* 8737 */ MCD_OPC_FilterValue, + 15, + 218, + 64, + 0, // Skip to: 25344 + /* 8742 */ MCD_OPC_CheckPredicate, + 22, + 213, + 64, + 0, // Skip to: 25344 + /* 8747 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 206, + 64, + 0, // Skip to: 25344 + /* 8754 */ MCD_OPC_Decode, + 171, + 10, + 148, + 1, // Opcode: MVE_VMOVNi32bh + /* 8759 */ MCD_OPC_FilterValue, + 1, + 196, + 64, + 0, // Skip to: 25344 + /* 8764 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8767 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8789 + /* 8772 */ MCD_OPC_CheckPredicate, + 22, + 183, + 64, + 0, // Skip to: 25344 + /* 8777 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 176, + 64, + 0, // Skip to: 25344 + /* 8784 */ MCD_OPC_Decode, + 187, + 11, + 148, + 1, // Opcode: MVE_VQMOVUNs32th + /* 8789 */ MCD_OPC_FilterValue, + 15, + 166, + 64, + 0, // Skip to: 25344 + /* 8794 */ MCD_OPC_CheckPredicate, + 22, + 161, + 64, + 0, // Skip to: 25344 + /* 8799 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 154, + 64, + 0, // Skip to: 25344 + /* 8806 */ MCD_OPC_Decode, + 172, + 10, + 148, + 1, // Opcode: MVE_VMOVNi32th + /* 8811 */ MCD_OPC_FilterValue, + 3, + 181, + 0, + 0, // Skip to: 8997 + /* 8816 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 8819 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 8931 + /* 8824 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8827 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8879 + /* 8832 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8835 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8857 + /* 8840 */ MCD_OPC_CheckPredicate, + 22, + 115, + 64, + 0, // Skip to: 25344 + /* 8845 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 108, + 64, + 0, // Skip to: 25344 + /* 8852 */ MCD_OPC_Decode, + 178, + 11, + 148, + 1, // Opcode: MVE_VQMOVNs32bh + /* 8857 */ MCD_OPC_FilterValue, + 15, + 98, + 64, + 0, // Skip to: 25344 + /* 8862 */ MCD_OPC_CheckPredicate, + 22, + 93, + 64, + 0, // Skip to: 25344 + /* 8867 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 86, + 64, + 0, // Skip to: 25344 + /* 8874 */ MCD_OPC_Decode, + 182, + 11, + 148, + 1, // Opcode: MVE_VQMOVNu32bh + /* 8879 */ MCD_OPC_FilterValue, + 1, + 76, + 64, + 0, // Skip to: 25344 + /* 8884 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8887 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8909 + /* 8892 */ MCD_OPC_CheckPredicate, + 22, + 63, + 64, + 0, // Skip to: 25344 + /* 8897 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 56, + 64, + 0, // Skip to: 25344 + /* 8904 */ MCD_OPC_Decode, + 179, + 11, + 148, + 1, // Opcode: MVE_VQMOVNs32th + /* 8909 */ MCD_OPC_FilterValue, + 15, + 46, + 64, + 0, // Skip to: 25344 + /* 8914 */ MCD_OPC_CheckPredicate, + 22, + 41, + 64, + 0, // Skip to: 25344 + /* 8919 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 34, + 64, + 0, // Skip to: 25344 + /* 8926 */ MCD_OPC_Decode, + 183, + 11, + 148, + 1, // Opcode: MVE_VQMOVNu32th + /* 8931 */ MCD_OPC_FilterValue, + 1, + 24, + 64, + 0, // Skip to: 25344 + /* 8936 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8939 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 8968 + /* 8944 */ MCD_OPC_CheckPredicate, + 22, + 11, + 64, + 0, // Skip to: 25344 + /* 8949 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 4, + 64, + 0, // Skip to: 25344 + /* 8956 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 253, + 63, + 0, // Skip to: 25344 + /* 8963 */ MCD_OPC_Decode, + 184, + 9, + 148, + 1, // Opcode: MVE_VMAXAs16 + /* 8968 */ MCD_OPC_FilterValue, + 1, + 243, + 63, + 0, // Skip to: 25344 + /* 8973 */ MCD_OPC_CheckPredicate, + 22, + 238, + 63, + 0, // Skip to: 25344 + /* 8978 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 231, + 63, + 0, // Skip to: 25344 + /* 8985 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 224, + 63, + 0, // Skip to: 25344 + /* 8992 */ MCD_OPC_Decode, + 210, + 9, + 148, + 1, // Opcode: MVE_VMINAs16 + /* 8997 */ MCD_OPC_FilterValue, + 5, + 75, + 0, + 0, // Skip to: 9077 + /* 9002 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 9005 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 9041 + /* 9010 */ MCD_OPC_CheckPredicate, + 22, + 201, + 63, + 0, // Skip to: 25344 + /* 9015 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 194, + 63, + 0, // Skip to: 25344 + /* 9022 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 187, + 63, + 0, // Skip to: 25344 + /* 9029 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 180, + 63, + 0, // Skip to: 25344 + /* 9036 */ MCD_OPC_Decode, + 185, + 9, + 148, + 1, // Opcode: MVE_VMAXAs32 + /* 9041 */ MCD_OPC_FilterValue, + 1, + 170, + 63, + 0, // Skip to: 25344 + /* 9046 */ MCD_OPC_CheckPredicate, + 22, + 165, + 63, + 0, // Skip to: 25344 + /* 9051 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 158, + 63, + 0, // Skip to: 25344 + /* 9058 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 151, + 63, + 0, // Skip to: 25344 + /* 9065 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 144, + 63, + 0, // Skip to: 25344 + /* 9072 */ MCD_OPC_Decode, + 211, + 9, + 148, + 1, // Opcode: MVE_VMINAs32 + /* 9077 */ MCD_OPC_FilterValue, + 7, + 134, + 63, + 0, // Skip to: 25344 + /* 9082 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9085 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 9197 + /* 9090 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 9093 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 9145 + /* 9098 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9101 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9123 + /* 9106 */ MCD_OPC_CheckPredicate, + 24, + 105, + 63, + 0, // Skip to: 25344 + /* 9111 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 98, + 63, + 0, // Skip to: 25344 + /* 9118 */ MCD_OPC_Decode, + 140, + 8, + 148, + 1, // Opcode: MVE_VCVTf16f32bh + /* 9123 */ MCD_OPC_FilterValue, + 15, + 88, + 63, + 0, // Skip to: 25344 + /* 9128 */ MCD_OPC_CheckPredicate, + 24, + 83, + 63, + 0, // Skip to: 25344 + /* 9133 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 76, + 63, + 0, // Skip to: 25344 + /* 9140 */ MCD_OPC_Decode, + 146, + 8, + 147, + 1, // Opcode: MVE_VCVTf32f16bh + /* 9145 */ MCD_OPC_FilterValue, + 1, + 66, + 63, + 0, // Skip to: 25344 + /* 9150 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9153 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9175 + /* 9158 */ MCD_OPC_CheckPredicate, + 24, + 53, + 63, + 0, // Skip to: 25344 + /* 9163 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 46, + 63, + 0, // Skip to: 25344 + /* 9170 */ MCD_OPC_Decode, + 141, + 8, + 148, + 1, // Opcode: MVE_VCVTf16f32th + /* 9175 */ MCD_OPC_FilterValue, + 15, + 36, + 63, + 0, // Skip to: 25344 + /* 9180 */ MCD_OPC_CheckPredicate, + 24, + 31, + 63, + 0, // Skip to: 25344 + /* 9185 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 24, + 63, + 0, // Skip to: 25344 + /* 9192 */ MCD_OPC_Decode, + 147, + 8, + 147, + 1, // Opcode: MVE_VCVTf32f16th + /* 9197 */ MCD_OPC_FilterValue, + 1, + 14, + 63, + 0, // Skip to: 25344 + /* 9202 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 9205 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 9257 + /* 9210 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9213 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9235 + /* 9218 */ MCD_OPC_CheckPredicate, + 24, + 249, + 62, + 0, // Skip to: 25344 + /* 9223 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 242, + 62, + 0, // Skip to: 25344 + /* 9230 */ MCD_OPC_Decode, + 190, + 9, + 148, + 1, // Opcode: MVE_VMAXNMAf32 + /* 9235 */ MCD_OPC_FilterValue, + 15, + 232, + 62, + 0, // Skip to: 25344 + /* 9240 */ MCD_OPC_CheckPredicate, + 24, + 227, + 62, + 0, // Skip to: 25344 + /* 9245 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 220, + 62, + 0, // Skip to: 25344 + /* 9252 */ MCD_OPC_Decode, + 189, + 9, + 148, + 1, // Opcode: MVE_VMAXNMAf16 + /* 9257 */ MCD_OPC_FilterValue, + 1, + 210, + 62, + 0, // Skip to: 25344 + /* 9262 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9265 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9287 + /* 9270 */ MCD_OPC_CheckPredicate, + 24, + 197, + 62, + 0, // Skip to: 25344 + /* 9275 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 190, + 62, + 0, // Skip to: 25344 + /* 9282 */ MCD_OPC_Decode, + 216, + 9, + 148, + 1, // Opcode: MVE_VMINNMAf32 + /* 9287 */ MCD_OPC_FilterValue, + 15, + 180, + 62, + 0, // Skip to: 25344 + /* 9292 */ MCD_OPC_CheckPredicate, + 24, + 175, + 62, + 0, // Skip to: 25344 + /* 9297 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 168, + 62, + 0, // Skip to: 25344 + /* 9304 */ MCD_OPC_Decode, + 215, + 9, + 148, + 1, // Opcode: MVE_VMINNMAf16 + /* 9309 */ MCD_OPC_FilterValue, + 1, + 158, + 62, + 0, // Skip to: 25344 + /* 9314 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 9317 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 9429 + /* 9322 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 9325 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 9377 + /* 9330 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9333 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9355 + /* 9338 */ MCD_OPC_CheckPredicate, + 24, + 129, + 62, + 0, // Skip to: 25344 + /* 9343 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 122, + 62, + 0, // Skip to: 25344 + /* 9350 */ MCD_OPC_Decode, + 189, + 8, + 144, + 1, // Opcode: MVE_VFMA_qr_f32 + /* 9355 */ MCD_OPC_FilterValue, + 15, + 112, + 62, + 0, // Skip to: 25344 + /* 9360 */ MCD_OPC_CheckPredicate, + 24, + 107, + 62, + 0, // Skip to: 25344 + /* 9365 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 100, + 62, + 0, // Skip to: 25344 + /* 9372 */ MCD_OPC_Decode, + 188, + 8, + 144, + 1, // Opcode: MVE_VFMA_qr_f16 + /* 9377 */ MCD_OPC_FilterValue, + 1, + 90, + 62, + 0, // Skip to: 25344 + /* 9382 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9385 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9407 + /* 9390 */ MCD_OPC_CheckPredicate, + 24, + 77, + 62, + 0, // Skip to: 25344 + /* 9395 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 70, + 62, + 0, // Skip to: 25344 + /* 9402 */ MCD_OPC_Decode, + 187, + 8, + 144, + 1, // Opcode: MVE_VFMA_qr_Sf32 + /* 9407 */ MCD_OPC_FilterValue, + 15, + 60, + 62, + 0, // Skip to: 25344 + /* 9412 */ MCD_OPC_CheckPredicate, + 24, + 55, + 62, + 0, // Skip to: 25344 + /* 9417 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 48, + 62, + 0, // Skip to: 25344 + /* 9424 */ MCD_OPC_Decode, + 186, + 8, + 144, + 1, // Opcode: MVE_VFMA_qr_Sf16 + /* 9429 */ MCD_OPC_FilterValue, + 2, + 38, + 62, + 0, // Skip to: 25344 + /* 9434 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 9437 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 9489 + /* 9442 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9445 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9467 + /* 9450 */ MCD_OPC_CheckPredicate, + 24, + 17, + 62, + 0, // Skip to: 25344 + /* 9455 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 10, + 62, + 0, // Skip to: 25344 + /* 9462 */ MCD_OPC_Decode, + 211, + 10, + 145, + 1, // Opcode: MVE_VMUL_qr_f32 + /* 9467 */ MCD_OPC_FilterValue, + 15, + 0, + 62, + 0, // Skip to: 25344 + /* 9472 */ MCD_OPC_CheckPredicate, + 24, + 251, + 61, + 0, // Skip to: 25344 + /* 9477 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 244, + 61, + 0, // Skip to: 25344 + /* 9484 */ MCD_OPC_Decode, + 210, + 10, + 145, + 1, // Opcode: MVE_VMUL_qr_f16 + /* 9489 */ MCD_OPC_FilterValue, + 1, + 234, + 61, + 0, // Skip to: 25344 + /* 9494 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9497 */ MCD_OPC_FilterValue, + 1, + 79, + 0, + 0, // Skip to: 9581 + /* 9502 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9505 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 9543 + /* 9510 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9513 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9528 + /* 9518 */ MCD_OPC_CheckPredicate, + 22, + 205, + 61, + 0, // Skip to: 25344 + /* 9523 */ MCD_OPC_Decode, + 248, + 12, + 149, + 1, // Opcode: MVE_VSHL_qrs8 + /* 9528 */ MCD_OPC_FilterValue, + 15, + 195, + 61, + 0, // Skip to: 25344 + /* 9533 */ MCD_OPC_CheckPredicate, + 22, + 190, + 61, + 0, // Skip to: 25344 + /* 9538 */ MCD_OPC_Decode, + 251, + 12, + 149, + 1, // Opcode: MVE_VSHL_qru8 + /* 9543 */ MCD_OPC_FilterValue, + 1, + 180, + 61, + 0, // Skip to: 25344 + /* 9548 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9551 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9566 + /* 9556 */ MCD_OPC_CheckPredicate, + 22, + 167, + 61, + 0, // Skip to: 25344 + /* 9561 */ MCD_OPC_Decode, + 250, + 11, + 149, + 1, // Opcode: MVE_VQSHL_qrs8 + /* 9566 */ MCD_OPC_FilterValue, + 15, + 157, + 61, + 0, // Skip to: 25344 + /* 9571 */ MCD_OPC_CheckPredicate, + 22, + 152, + 61, + 0, // Skip to: 25344 + /* 9576 */ MCD_OPC_Decode, + 253, + 11, + 149, + 1, // Opcode: MVE_VQSHL_qru8 + /* 9581 */ MCD_OPC_FilterValue, + 3, + 79, + 0, + 0, // Skip to: 9665 + /* 9586 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9589 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 9627 + /* 9594 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9597 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9612 + /* 9602 */ MCD_OPC_CheckPredicate, + 22, + 121, + 61, + 0, // Skip to: 25344 + /* 9607 */ MCD_OPC_Decode, + 204, + 12, + 149, + 1, // Opcode: MVE_VRSHL_qrs8 + /* 9612 */ MCD_OPC_FilterValue, + 15, + 111, + 61, + 0, // Skip to: 25344 + /* 9617 */ MCD_OPC_CheckPredicate, + 22, + 106, + 61, + 0, // Skip to: 25344 + /* 9622 */ MCD_OPC_Decode, + 207, + 12, + 149, + 1, // Opcode: MVE_VRSHL_qru8 + /* 9627 */ MCD_OPC_FilterValue, + 1, + 96, + 61, + 0, // Skip to: 25344 + /* 9632 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9635 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9650 + /* 9640 */ MCD_OPC_CheckPredicate, + 22, + 83, + 61, + 0, // Skip to: 25344 + /* 9645 */ MCD_OPC_Decode, + 223, + 11, + 149, + 1, // Opcode: MVE_VQRSHL_qrs8 + /* 9650 */ MCD_OPC_FilterValue, + 15, + 73, + 61, + 0, // Skip to: 25344 + /* 9655 */ MCD_OPC_CheckPredicate, + 22, + 68, + 61, + 0, // Skip to: 25344 + /* 9660 */ MCD_OPC_Decode, + 226, + 11, + 149, + 1, // Opcode: MVE_VQRSHL_qru8 + /* 9665 */ MCD_OPC_FilterValue, + 5, + 79, + 0, + 0, // Skip to: 9749 + /* 9670 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9673 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 9711 + /* 9678 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9681 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9696 + /* 9686 */ MCD_OPC_CheckPredicate, + 22, + 37, + 61, + 0, // Skip to: 25344 + /* 9691 */ MCD_OPC_Decode, + 246, + 12, + 149, + 1, // Opcode: MVE_VSHL_qrs16 + /* 9696 */ MCD_OPC_FilterValue, + 15, + 27, + 61, + 0, // Skip to: 25344 + /* 9701 */ MCD_OPC_CheckPredicate, + 22, + 22, + 61, + 0, // Skip to: 25344 + /* 9706 */ MCD_OPC_Decode, + 249, + 12, + 149, + 1, // Opcode: MVE_VSHL_qru16 + /* 9711 */ MCD_OPC_FilterValue, + 1, + 12, + 61, + 0, // Skip to: 25344 + /* 9716 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9719 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9734 + /* 9724 */ MCD_OPC_CheckPredicate, + 22, + 255, + 60, + 0, // Skip to: 25344 + /* 9729 */ MCD_OPC_Decode, + 248, + 11, + 149, + 1, // Opcode: MVE_VQSHL_qrs16 + /* 9734 */ MCD_OPC_FilterValue, + 15, + 245, + 60, + 0, // Skip to: 25344 + /* 9739 */ MCD_OPC_CheckPredicate, + 22, + 240, + 60, + 0, // Skip to: 25344 + /* 9744 */ MCD_OPC_Decode, + 251, + 11, + 149, + 1, // Opcode: MVE_VQSHL_qru16 + /* 9749 */ MCD_OPC_FilterValue, + 7, + 79, + 0, + 0, // Skip to: 9833 + /* 9754 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9757 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 9795 + /* 9762 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9765 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9780 + /* 9770 */ MCD_OPC_CheckPredicate, + 22, + 209, + 60, + 0, // Skip to: 25344 + /* 9775 */ MCD_OPC_Decode, + 202, + 12, + 149, + 1, // Opcode: MVE_VRSHL_qrs16 + /* 9780 */ MCD_OPC_FilterValue, + 15, + 199, + 60, + 0, // Skip to: 25344 + /* 9785 */ MCD_OPC_CheckPredicate, + 22, + 194, + 60, + 0, // Skip to: 25344 + /* 9790 */ MCD_OPC_Decode, + 205, + 12, + 149, + 1, // Opcode: MVE_VRSHL_qru16 + /* 9795 */ MCD_OPC_FilterValue, + 1, + 184, + 60, + 0, // Skip to: 25344 + /* 9800 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9803 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9818 + /* 9808 */ MCD_OPC_CheckPredicate, + 22, + 171, + 60, + 0, // Skip to: 25344 + /* 9813 */ MCD_OPC_Decode, + 221, + 11, + 149, + 1, // Opcode: MVE_VQRSHL_qrs16 + /* 9818 */ MCD_OPC_FilterValue, + 15, + 161, + 60, + 0, // Skip to: 25344 + /* 9823 */ MCD_OPC_CheckPredicate, + 22, + 156, + 60, + 0, // Skip to: 25344 + /* 9828 */ MCD_OPC_Decode, + 224, + 11, + 149, + 1, // Opcode: MVE_VQRSHL_qru16 + /* 9833 */ MCD_OPC_FilterValue, + 9, + 79, + 0, + 0, // Skip to: 9917 + /* 9838 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9841 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 9879 + /* 9846 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9849 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9864 + /* 9854 */ MCD_OPC_CheckPredicate, + 22, + 125, + 60, + 0, // Skip to: 25344 + /* 9859 */ MCD_OPC_Decode, + 247, + 12, + 149, + 1, // Opcode: MVE_VSHL_qrs32 + /* 9864 */ MCD_OPC_FilterValue, + 15, + 115, + 60, + 0, // Skip to: 25344 + /* 9869 */ MCD_OPC_CheckPredicate, + 22, + 110, + 60, + 0, // Skip to: 25344 + /* 9874 */ MCD_OPC_Decode, + 250, + 12, + 149, + 1, // Opcode: MVE_VSHL_qru32 + /* 9879 */ MCD_OPC_FilterValue, + 1, + 100, + 60, + 0, // Skip to: 25344 + /* 9884 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9887 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9902 + /* 9892 */ MCD_OPC_CheckPredicate, + 22, + 87, + 60, + 0, // Skip to: 25344 + /* 9897 */ MCD_OPC_Decode, + 249, + 11, + 149, + 1, // Opcode: MVE_VQSHL_qrs32 + /* 9902 */ MCD_OPC_FilterValue, + 15, + 77, + 60, + 0, // Skip to: 25344 + /* 9907 */ MCD_OPC_CheckPredicate, + 22, + 72, + 60, + 0, // Skip to: 25344 + /* 9912 */ MCD_OPC_Decode, + 252, + 11, + 149, + 1, // Opcode: MVE_VQSHL_qru32 + /* 9917 */ MCD_OPC_FilterValue, + 11, + 62, + 60, + 0, // Skip to: 25344 + /* 9922 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9925 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 9963 + /* 9930 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9933 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9948 + /* 9938 */ MCD_OPC_CheckPredicate, + 22, + 41, + 60, + 0, // Skip to: 25344 + /* 9943 */ MCD_OPC_Decode, + 203, + 12, + 149, + 1, // Opcode: MVE_VRSHL_qrs32 + /* 9948 */ MCD_OPC_FilterValue, + 15, + 31, + 60, + 0, // Skip to: 25344 + /* 9953 */ MCD_OPC_CheckPredicate, + 22, + 26, + 60, + 0, // Skip to: 25344 + /* 9958 */ MCD_OPC_Decode, + 206, + 12, + 149, + 1, // Opcode: MVE_VRSHL_qru32 + /* 9963 */ MCD_OPC_FilterValue, + 1, + 16, + 60, + 0, // Skip to: 25344 + /* 9968 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9971 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9986 + /* 9976 */ MCD_OPC_CheckPredicate, + 22, + 3, + 60, + 0, // Skip to: 25344 + /* 9981 */ MCD_OPC_Decode, + 222, + 11, + 149, + 1, // Opcode: MVE_VQRSHL_qrs32 + /* 9986 */ MCD_OPC_FilterValue, + 15, + 249, + 59, + 0, // Skip to: 25344 + /* 9991 */ MCD_OPC_CheckPredicate, + 22, + 244, + 59, + 0, // Skip to: 25344 + /* 9996 */ MCD_OPC_Decode, + 225, + 11, + 149, + 1, // Opcode: MVE_VQRSHL_qru32 + /* 10001 */ MCD_OPC_FilterValue, + 15, + 234, + 59, + 0, // Skip to: 25344 + /* 10006 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 10009 */ MCD_OPC_FilterValue, + 0, + 197, + 2, + 0, // Skip to: 10723 + /* 10014 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10017 */ MCD_OPC_FilterValue, + 0, + 250, + 0, + 0, // Skip to: 10272 + /* 10022 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10025 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 10091 + /* 10030 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10033 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 10062 + /* 10038 */ MCD_OPC_CheckPredicate, + 22, + 197, + 59, + 0, // Skip to: 25344 + /* 10043 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 190, + 59, + 0, // Skip to: 25344 + /* 10050 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 183, + 59, + 0, // Skip to: 25344 + /* 10057 */ MCD_OPC_Decode, + 208, + 8, + 150, + 1, // Opcode: MVE_VHCADDs8 + /* 10062 */ MCD_OPC_FilterValue, + 15, + 173, + 59, + 0, // Skip to: 25344 + /* 10067 */ MCD_OPC_CheckPredicate, + 22, + 168, + 59, + 0, // Skip to: 25344 + /* 10072 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 161, + 59, + 0, // Skip to: 25344 + /* 10079 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 154, + 59, + 0, // Skip to: 25344 + /* 10086 */ MCD_OPC_Decode, + 231, + 7, + 150, + 1, // Opcode: MVE_VCADDi8 + /* 10091 */ MCD_OPC_FilterValue, + 1, + 144, + 59, + 0, // Skip to: 25344 + /* 10096 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 10099 */ MCD_OPC_FilterValue, + 0, + 113, + 0, + 0, // Skip to: 10217 + /* 10104 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 10107 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 10162 + /* 10112 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10115 */ MCD_OPC_FilterValue, + 0, + 120, + 59, + 0, // Skip to: 25344 + /* 10120 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10123 */ MCD_OPC_FilterValue, + 15, + 112, + 59, + 0, // Skip to: 25344 + /* 10128 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10152 + /* 10133 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10152 + /* 10140 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10152 + /* 10147 */ MCD_OPC_Decode, + 248, + 7, + 151, + 1, // Opcode: MVE_VCMPi8 + /* 10152 */ MCD_OPC_CheckPredicate, + 22, + 83, + 59, + 0, // Skip to: 25344 + /* 10157 */ MCD_OPC_Decode, + 235, + 10, + 152, + 1, // Opcode: MVE_VPTv16i8 + /* 10162 */ MCD_OPC_FilterValue, + 1, + 73, + 59, + 0, // Skip to: 25344 + /* 10167 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10170 */ MCD_OPC_FilterValue, + 0, + 65, + 59, + 0, // Skip to: 25344 + /* 10175 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10178 */ MCD_OPC_FilterValue, + 15, + 57, + 59, + 0, // Skip to: 25344 + /* 10183 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10207 + /* 10188 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10207 + /* 10195 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10207 + /* 10202 */ MCD_OPC_Decode, + 132, + 8, + 153, + 1, // Opcode: MVE_VCMPu8 + /* 10207 */ MCD_OPC_CheckPredicate, + 22, + 28, + 59, + 0, // Skip to: 25344 + /* 10212 */ MCD_OPC_Decode, + 239, + 10, + 154, + 1, // Opcode: MVE_VPTv16u8 + /* 10217 */ MCD_OPC_FilterValue, + 1, + 18, + 59, + 0, // Skip to: 25344 + /* 10222 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10225 */ MCD_OPC_FilterValue, + 0, + 10, + 59, + 0, // Skip to: 25344 + /* 10230 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10233 */ MCD_OPC_FilterValue, + 15, + 2, + 59, + 0, // Skip to: 25344 + /* 10238 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10262 + /* 10243 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10262 + /* 10250 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10262 + /* 10257 */ MCD_OPC_Decode, + 254, + 7, + 155, + 1, // Opcode: MVE_VCMPs8 + /* 10262 */ MCD_OPC_CheckPredicate, + 22, + 229, + 58, + 0, // Skip to: 25344 + /* 10267 */ MCD_OPC_Decode, + 237, + 10, + 156, + 1, // Opcode: MVE_VPTv16s8 + /* 10272 */ MCD_OPC_FilterValue, + 1, + 219, + 58, + 0, // Skip to: 25344 + /* 10277 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 10280 */ MCD_OPC_FilterValue, + 0, + 236, + 0, + 0, // Skip to: 10521 + /* 10285 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 10288 */ MCD_OPC_FilterValue, + 0, + 103, + 0, + 0, // Skip to: 10396 + /* 10293 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10296 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 10334 + /* 10301 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10304 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10319 + /* 10309 */ MCD_OPC_CheckPredicate, + 22, + 182, + 58, + 0, // Skip to: 25344 + /* 10314 */ MCD_OPC_Decode, + 196, + 8, + 145, + 1, // Opcode: MVE_VHADD_qr_s8 + /* 10319 */ MCD_OPC_FilterValue, + 15, + 172, + 58, + 0, // Skip to: 25344 + /* 10324 */ MCD_OPC_CheckPredicate, + 22, + 167, + 58, + 0, // Skip to: 25344 + /* 10329 */ MCD_OPC_Decode, + 199, + 8, + 145, + 1, // Opcode: MVE_VHADD_qr_u8 + /* 10334 */ MCD_OPC_FilterValue, + 1, + 157, + 58, + 0, // Skip to: 25344 + /* 10339 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10342 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10357 + /* 10347 */ MCD_OPC_CheckPredicate, + 22, + 144, + 58, + 0, // Skip to: 25344 + /* 10352 */ MCD_OPC_Decode, + 214, + 7, + 145, + 1, // Opcode: MVE_VADD_qr_i8 + /* 10357 */ MCD_OPC_FilterValue, + 15, + 134, + 58, + 0, // Skip to: 25344 + /* 10362 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10386 + /* 10367 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10386 + /* 10374 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10386 + /* 10381 */ MCD_OPC_Decode, + 249, + 7, + 157, + 1, // Opcode: MVE_VCMPi8r + /* 10386 */ MCD_OPC_CheckPredicate, + 22, + 105, + 58, + 0, // Skip to: 25344 + /* 10391 */ MCD_OPC_Decode, + 236, + 10, + 158, + 1, // Opcode: MVE_VPTv16i8r + /* 10396 */ MCD_OPC_FilterValue, + 2, + 95, + 58, + 0, // Skip to: 25344 + /* 10401 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10404 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 10442 + /* 10409 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10412 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10427 + /* 10417 */ MCD_OPC_CheckPredicate, + 22, + 74, + 58, + 0, // Skip to: 25344 + /* 10422 */ MCD_OPC_Decode, + 134, + 11, + 145, + 1, // Opcode: MVE_VQADD_qr_s8 + /* 10427 */ MCD_OPC_FilterValue, + 15, + 64, + 58, + 0, // Skip to: 25344 + /* 10432 */ MCD_OPC_CheckPredicate, + 22, + 59, + 58, + 0, // Skip to: 25344 + /* 10437 */ MCD_OPC_Decode, + 137, + 11, + 145, + 1, // Opcode: MVE_VQADD_qr_u8 + /* 10442 */ MCD_OPC_FilterValue, + 1, + 49, + 58, + 0, // Skip to: 25344 + /* 10447 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10450 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 10482 + /* 10455 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 10472 + /* 10460 */ MCD_OPC_CheckField, + 1, + 3, + 7, + 5, + 0, + 0, // Skip to: 10472 + /* 10467 */ MCD_OPC_Decode, + 223, + 8, + 159, + 1, // Opcode: MVE_VIDUPu8 + /* 10472 */ MCD_OPC_CheckPredicate, + 22, + 19, + 58, + 0, // Skip to: 25344 + /* 10477 */ MCD_OPC_Decode, + 226, + 8, + 160, + 1, // Opcode: MVE_VIWDUPu8 + /* 10482 */ MCD_OPC_FilterValue, + 15, + 9, + 58, + 0, // Skip to: 25344 + /* 10487 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10511 + /* 10492 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10511 + /* 10499 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10511 + /* 10506 */ MCD_OPC_Decode, + 133, + 8, + 161, + 1, // Opcode: MVE_VCMPu8r + /* 10511 */ MCD_OPC_CheckPredicate, + 22, + 236, + 57, + 0, // Skip to: 25344 + /* 10516 */ MCD_OPC_Decode, + 240, + 10, + 162, + 1, // Opcode: MVE_VPTv16u8r + /* 10521 */ MCD_OPC_FilterValue, + 1, + 226, + 57, + 0, // Skip to: 25344 + /* 10526 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10529 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 10613 + /* 10534 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 10537 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 10575 + /* 10542 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10545 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10560 + /* 10550 */ MCD_OPC_CheckPredicate, + 22, + 197, + 57, + 0, // Skip to: 25344 + /* 10555 */ MCD_OPC_Decode, + 211, + 8, + 145, + 1, // Opcode: MVE_VHSUB_qr_s8 + /* 10560 */ MCD_OPC_FilterValue, + 15, + 187, + 57, + 0, // Skip to: 25344 + /* 10565 */ MCD_OPC_CheckPredicate, + 22, + 182, + 57, + 0, // Skip to: 25344 + /* 10570 */ MCD_OPC_Decode, + 214, + 8, + 145, + 1, // Opcode: MVE_VHSUB_qr_u8 + /* 10575 */ MCD_OPC_FilterValue, + 2, + 172, + 57, + 0, // Skip to: 25344 + /* 10580 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10583 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10598 + /* 10588 */ MCD_OPC_CheckPredicate, + 22, + 159, + 57, + 0, // Skip to: 25344 + /* 10593 */ MCD_OPC_Decode, + 146, + 12, + 145, + 1, // Opcode: MVE_VQSUB_qr_s8 + /* 10598 */ MCD_OPC_FilterValue, + 15, + 149, + 57, + 0, // Skip to: 25344 + /* 10603 */ MCD_OPC_CheckPredicate, + 22, + 144, + 57, + 0, // Skip to: 25344 + /* 10608 */ MCD_OPC_Decode, + 149, + 12, + 145, + 1, // Opcode: MVE_VQSUB_qr_u8 + /* 10613 */ MCD_OPC_FilterValue, + 1, + 134, + 57, + 0, // Skip to: 25344 + /* 10618 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10621 */ MCD_OPC_FilterValue, + 14, + 50, + 0, + 0, // Skip to: 10676 + /* 10626 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 10629 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10644 + /* 10634 */ MCD_OPC_CheckPredicate, + 22, + 113, + 57, + 0, // Skip to: 25344 + /* 10639 */ MCD_OPC_Decode, + 213, + 13, + 145, + 1, // Opcode: MVE_VSUB_qr_i8 + /* 10644 */ MCD_OPC_FilterValue, + 2, + 103, + 57, + 0, // Skip to: 25344 + /* 10649 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 10666 + /* 10654 */ MCD_OPC_CheckField, + 1, + 3, + 7, + 5, + 0, + 0, // Skip to: 10666 + /* 10661 */ MCD_OPC_Decode, + 178, + 8, + 159, + 1, // Opcode: MVE_VDDUPu8 + /* 10666 */ MCD_OPC_CheckPredicate, + 22, + 81, + 57, + 0, // Skip to: 25344 + /* 10671 */ MCD_OPC_Decode, + 184, + 8, + 160, + 1, // Opcode: MVE_VDWDUPu8 + /* 10676 */ MCD_OPC_FilterValue, + 15, + 71, + 57, + 0, // Skip to: 25344 + /* 10681 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10684 */ MCD_OPC_FilterValue, + 0, + 63, + 57, + 0, // Skip to: 25344 + /* 10689 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10713 + /* 10694 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10713 + /* 10701 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10713 + /* 10708 */ MCD_OPC_Decode, + 255, + 7, + 163, + 1, // Opcode: MVE_VCMPs8r + /* 10713 */ MCD_OPC_CheckPredicate, + 22, + 34, + 57, + 0, // Skip to: 25344 + /* 10718 */ MCD_OPC_Decode, + 238, + 10, + 164, + 1, // Opcode: MVE_VPTv16s8r + /* 10723 */ MCD_OPC_FilterValue, + 1, + 197, + 2, + 0, // Skip to: 11437 + /* 10728 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10731 */ MCD_OPC_FilterValue, + 0, + 250, + 0, + 0, // Skip to: 10986 + /* 10736 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10739 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 10805 + /* 10744 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10747 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 10776 + /* 10752 */ MCD_OPC_CheckPredicate, + 22, + 251, + 56, + 0, // Skip to: 25344 + /* 10757 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 244, + 56, + 0, // Skip to: 25344 + /* 10764 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 237, + 56, + 0, // Skip to: 25344 + /* 10771 */ MCD_OPC_Decode, + 206, + 8, + 150, + 1, // Opcode: MVE_VHCADDs16 + /* 10776 */ MCD_OPC_FilterValue, + 15, + 227, + 56, + 0, // Skip to: 25344 + /* 10781 */ MCD_OPC_CheckPredicate, + 22, + 222, + 56, + 0, // Skip to: 25344 + /* 10786 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 215, + 56, + 0, // Skip to: 25344 + /* 10793 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 208, + 56, + 0, // Skip to: 25344 + /* 10800 */ MCD_OPC_Decode, + 229, + 7, + 150, + 1, // Opcode: MVE_VCADDi16 + /* 10805 */ MCD_OPC_FilterValue, + 1, + 198, + 56, + 0, // Skip to: 25344 + /* 10810 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 10813 */ MCD_OPC_FilterValue, + 0, + 113, + 0, + 0, // Skip to: 10931 + /* 10818 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 10821 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 10876 + /* 10826 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10829 */ MCD_OPC_FilterValue, + 0, + 174, + 56, + 0, // Skip to: 25344 + /* 10834 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10837 */ MCD_OPC_FilterValue, + 15, + 166, + 56, + 0, // Skip to: 25344 + /* 10842 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10866 + /* 10847 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10866 + /* 10854 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10866 + /* 10861 */ MCD_OPC_Decode, + 244, + 7, + 151, + 1, // Opcode: MVE_VCMPi16 + /* 10866 */ MCD_OPC_CheckPredicate, + 22, + 137, + 56, + 0, // Skip to: 25344 + /* 10871 */ MCD_OPC_Decode, + 251, + 10, + 152, + 1, // Opcode: MVE_VPTv8i16 + /* 10876 */ MCD_OPC_FilterValue, + 1, + 127, + 56, + 0, // Skip to: 25344 + /* 10881 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10884 */ MCD_OPC_FilterValue, + 0, + 119, + 56, + 0, // Skip to: 25344 + /* 10889 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10892 */ MCD_OPC_FilterValue, + 15, + 111, + 56, + 0, // Skip to: 25344 + /* 10897 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10921 + /* 10902 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10921 + /* 10909 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10921 + /* 10916 */ MCD_OPC_Decode, + 128, + 8, + 153, + 1, // Opcode: MVE_VCMPu16 + /* 10921 */ MCD_OPC_CheckPredicate, + 22, + 82, + 56, + 0, // Skip to: 25344 + /* 10926 */ MCD_OPC_Decode, + 255, + 10, + 154, + 1, // Opcode: MVE_VPTv8u16 + /* 10931 */ MCD_OPC_FilterValue, + 1, + 72, + 56, + 0, // Skip to: 25344 + /* 10936 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10939 */ MCD_OPC_FilterValue, + 0, + 64, + 56, + 0, // Skip to: 25344 + /* 10944 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10947 */ MCD_OPC_FilterValue, + 15, + 56, + 56, + 0, // Skip to: 25344 + /* 10952 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10976 + /* 10957 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10976 + /* 10964 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10976 + /* 10971 */ MCD_OPC_Decode, + 250, + 7, + 155, + 1, // Opcode: MVE_VCMPs16 + /* 10976 */ MCD_OPC_CheckPredicate, + 22, + 27, + 56, + 0, // Skip to: 25344 + /* 10981 */ MCD_OPC_Decode, + 253, + 10, + 156, + 1, // Opcode: MVE_VPTv8s16 + /* 10986 */ MCD_OPC_FilterValue, + 1, + 17, + 56, + 0, // Skip to: 25344 + /* 10991 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 10994 */ MCD_OPC_FilterValue, + 0, + 236, + 0, + 0, // Skip to: 11235 + /* 10999 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 11002 */ MCD_OPC_FilterValue, + 0, + 103, + 0, + 0, // Skip to: 11110 + /* 11007 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11010 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 11048 + /* 11015 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11018 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11033 + /* 11023 */ MCD_OPC_CheckPredicate, + 22, + 236, + 55, + 0, // Skip to: 25344 + /* 11028 */ MCD_OPC_Decode, + 194, + 8, + 145, + 1, // Opcode: MVE_VHADD_qr_s16 + /* 11033 */ MCD_OPC_FilterValue, + 15, + 226, + 55, + 0, // Skip to: 25344 + /* 11038 */ MCD_OPC_CheckPredicate, + 22, + 221, + 55, + 0, // Skip to: 25344 + /* 11043 */ MCD_OPC_Decode, + 197, + 8, + 145, + 1, // Opcode: MVE_VHADD_qr_u16 + /* 11048 */ MCD_OPC_FilterValue, + 1, + 211, + 55, + 0, // Skip to: 25344 + /* 11053 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11056 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11071 + /* 11061 */ MCD_OPC_CheckPredicate, + 22, + 198, + 55, + 0, // Skip to: 25344 + /* 11066 */ MCD_OPC_Decode, + 212, + 7, + 145, + 1, // Opcode: MVE_VADD_qr_i16 + /* 11071 */ MCD_OPC_FilterValue, + 15, + 188, + 55, + 0, // Skip to: 25344 + /* 11076 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11100 + /* 11081 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11100 + /* 11088 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11100 + /* 11095 */ MCD_OPC_Decode, + 245, + 7, + 157, + 1, // Opcode: MVE_VCMPi16r + /* 11100 */ MCD_OPC_CheckPredicate, + 22, + 159, + 55, + 0, // Skip to: 25344 + /* 11105 */ MCD_OPC_Decode, + 252, + 10, + 158, + 1, // Opcode: MVE_VPTv8i16r + /* 11110 */ MCD_OPC_FilterValue, + 2, + 149, + 55, + 0, // Skip to: 25344 + /* 11115 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11118 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 11156 + /* 11123 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11126 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11141 + /* 11131 */ MCD_OPC_CheckPredicate, + 22, + 128, + 55, + 0, // Skip to: 25344 + /* 11136 */ MCD_OPC_Decode, + 132, + 11, + 145, + 1, // Opcode: MVE_VQADD_qr_s16 + /* 11141 */ MCD_OPC_FilterValue, + 15, + 118, + 55, + 0, // Skip to: 25344 + /* 11146 */ MCD_OPC_CheckPredicate, + 22, + 113, + 55, + 0, // Skip to: 25344 + /* 11151 */ MCD_OPC_Decode, + 135, + 11, + 145, + 1, // Opcode: MVE_VQADD_qr_u16 + /* 11156 */ MCD_OPC_FilterValue, + 1, + 103, + 55, + 0, // Skip to: 25344 + /* 11161 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11164 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 11196 + /* 11169 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 11186 + /* 11174 */ MCD_OPC_CheckField, + 1, + 3, + 7, + 5, + 0, + 0, // Skip to: 11186 + /* 11181 */ MCD_OPC_Decode, + 221, + 8, + 159, + 1, // Opcode: MVE_VIDUPu16 + /* 11186 */ MCD_OPC_CheckPredicate, + 22, + 73, + 55, + 0, // Skip to: 25344 + /* 11191 */ MCD_OPC_Decode, + 224, + 8, + 160, + 1, // Opcode: MVE_VIWDUPu16 + /* 11196 */ MCD_OPC_FilterValue, + 15, + 63, + 55, + 0, // Skip to: 25344 + /* 11201 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11225 + /* 11206 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11225 + /* 11213 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11225 + /* 11220 */ MCD_OPC_Decode, + 129, + 8, + 161, + 1, // Opcode: MVE_VCMPu16r + /* 11225 */ MCD_OPC_CheckPredicate, + 22, + 34, + 55, + 0, // Skip to: 25344 + /* 11230 */ MCD_OPC_Decode, + 128, + 11, + 162, + 1, // Opcode: MVE_VPTv8u16r + /* 11235 */ MCD_OPC_FilterValue, + 1, + 24, + 55, + 0, // Skip to: 25344 + /* 11240 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11243 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 11327 + /* 11248 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 11251 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 11289 + /* 11256 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11259 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11274 + /* 11264 */ MCD_OPC_CheckPredicate, + 22, + 251, + 54, + 0, // Skip to: 25344 + /* 11269 */ MCD_OPC_Decode, + 209, + 8, + 145, + 1, // Opcode: MVE_VHSUB_qr_s16 + /* 11274 */ MCD_OPC_FilterValue, + 15, + 241, + 54, + 0, // Skip to: 25344 + /* 11279 */ MCD_OPC_CheckPredicate, + 22, + 236, + 54, + 0, // Skip to: 25344 + /* 11284 */ MCD_OPC_Decode, + 212, + 8, + 145, + 1, // Opcode: MVE_VHSUB_qr_u16 + /* 11289 */ MCD_OPC_FilterValue, + 2, + 226, + 54, + 0, // Skip to: 25344 + /* 11294 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11297 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11312 + /* 11302 */ MCD_OPC_CheckPredicate, + 22, + 213, + 54, + 0, // Skip to: 25344 + /* 11307 */ MCD_OPC_Decode, + 144, + 12, + 145, + 1, // Opcode: MVE_VQSUB_qr_s16 + /* 11312 */ MCD_OPC_FilterValue, + 15, + 203, + 54, + 0, // Skip to: 25344 + /* 11317 */ MCD_OPC_CheckPredicate, + 22, + 198, + 54, + 0, // Skip to: 25344 + /* 11322 */ MCD_OPC_Decode, + 147, + 12, + 145, + 1, // Opcode: MVE_VQSUB_qr_u16 + /* 11327 */ MCD_OPC_FilterValue, + 1, + 188, + 54, + 0, // Skip to: 25344 + /* 11332 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11335 */ MCD_OPC_FilterValue, + 14, + 50, + 0, + 0, // Skip to: 11390 + /* 11340 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 11343 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11358 + /* 11348 */ MCD_OPC_CheckPredicate, + 22, + 167, + 54, + 0, // Skip to: 25344 + /* 11353 */ MCD_OPC_Decode, + 211, + 13, + 145, + 1, // Opcode: MVE_VSUB_qr_i16 + /* 11358 */ MCD_OPC_FilterValue, + 2, + 157, + 54, + 0, // Skip to: 25344 + /* 11363 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 11380 + /* 11368 */ MCD_OPC_CheckField, + 1, + 3, + 7, + 5, + 0, + 0, // Skip to: 11380 + /* 11375 */ MCD_OPC_Decode, + 176, + 8, + 159, + 1, // Opcode: MVE_VDDUPu16 + /* 11380 */ MCD_OPC_CheckPredicate, + 22, + 135, + 54, + 0, // Skip to: 25344 + /* 11385 */ MCD_OPC_Decode, + 182, + 8, + 160, + 1, // Opcode: MVE_VDWDUPu16 + /* 11390 */ MCD_OPC_FilterValue, + 15, + 125, + 54, + 0, // Skip to: 25344 + /* 11395 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 11398 */ MCD_OPC_FilterValue, + 0, + 117, + 54, + 0, // Skip to: 25344 + /* 11403 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11427 + /* 11408 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11427 + /* 11415 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11427 + /* 11422 */ MCD_OPC_Decode, + 251, + 7, + 163, + 1, // Opcode: MVE_VCMPs16r + /* 11427 */ MCD_OPC_CheckPredicate, + 22, + 88, + 54, + 0, // Skip to: 25344 + /* 11432 */ MCD_OPC_Decode, + 254, + 10, + 164, + 1, // Opcode: MVE_VPTv8s16r + /* 11437 */ MCD_OPC_FilterValue, + 2, + 197, + 2, + 0, // Skip to: 12151 + /* 11442 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 11445 */ MCD_OPC_FilterValue, + 0, + 250, + 0, + 0, // Skip to: 11700 + /* 11450 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11453 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 11519 + /* 11458 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11461 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 11490 + /* 11466 */ MCD_OPC_CheckPredicate, + 22, + 49, + 54, + 0, // Skip to: 25344 + /* 11471 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 42, + 54, + 0, // Skip to: 25344 + /* 11478 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 35, + 54, + 0, // Skip to: 25344 + /* 11485 */ MCD_OPC_Decode, + 207, + 8, + 150, + 1, // Opcode: MVE_VHCADDs32 + /* 11490 */ MCD_OPC_FilterValue, + 15, + 25, + 54, + 0, // Skip to: 25344 + /* 11495 */ MCD_OPC_CheckPredicate, + 22, + 20, + 54, + 0, // Skip to: 25344 + /* 11500 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 13, + 54, + 0, // Skip to: 25344 + /* 11507 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 6, + 54, + 0, // Skip to: 25344 + /* 11514 */ MCD_OPC_Decode, + 230, + 7, + 150, + 1, // Opcode: MVE_VCADDi32 + /* 11519 */ MCD_OPC_FilterValue, + 1, + 252, + 53, + 0, // Skip to: 25344 + /* 11524 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 11527 */ MCD_OPC_FilterValue, + 0, + 113, + 0, + 0, // Skip to: 11645 + /* 11532 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 11535 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 11590 + /* 11540 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 11543 */ MCD_OPC_FilterValue, + 0, + 228, + 53, + 0, // Skip to: 25344 + /* 11548 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11551 */ MCD_OPC_FilterValue, + 15, + 220, + 53, + 0, // Skip to: 25344 + /* 11556 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11580 + /* 11561 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11580 + /* 11568 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11580 + /* 11575 */ MCD_OPC_Decode, + 246, + 7, + 151, + 1, // Opcode: MVE_VCMPi32 + /* 11580 */ MCD_OPC_CheckPredicate, + 22, + 191, + 53, + 0, // Skip to: 25344 + /* 11585 */ MCD_OPC_Decode, + 243, + 10, + 152, + 1, // Opcode: MVE_VPTv4i32 + /* 11590 */ MCD_OPC_FilterValue, + 1, + 181, + 53, + 0, // Skip to: 25344 + /* 11595 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 11598 */ MCD_OPC_FilterValue, + 0, + 173, + 53, + 0, // Skip to: 25344 + /* 11603 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11606 */ MCD_OPC_FilterValue, + 15, + 165, + 53, + 0, // Skip to: 25344 + /* 11611 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11635 + /* 11616 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11635 + /* 11623 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11635 + /* 11630 */ MCD_OPC_Decode, + 130, + 8, + 153, + 1, // Opcode: MVE_VCMPu32 + /* 11635 */ MCD_OPC_CheckPredicate, + 22, + 136, + 53, + 0, // Skip to: 25344 + /* 11640 */ MCD_OPC_Decode, + 247, + 10, + 154, + 1, // Opcode: MVE_VPTv4u32 + /* 11645 */ MCD_OPC_FilterValue, + 1, + 126, + 53, + 0, // Skip to: 25344 + /* 11650 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 11653 */ MCD_OPC_FilterValue, + 0, + 118, + 53, + 0, // Skip to: 25344 + /* 11658 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11661 */ MCD_OPC_FilterValue, + 15, + 110, + 53, + 0, // Skip to: 25344 + /* 11666 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11690 + /* 11671 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11690 + /* 11678 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11690 + /* 11685 */ MCD_OPC_Decode, + 252, + 7, + 155, + 1, // Opcode: MVE_VCMPs32 + /* 11690 */ MCD_OPC_CheckPredicate, + 22, + 81, + 53, + 0, // Skip to: 25344 + /* 11695 */ MCD_OPC_Decode, + 245, + 10, + 156, + 1, // Opcode: MVE_VPTv4s32 + /* 11700 */ MCD_OPC_FilterValue, + 1, + 71, + 53, + 0, // Skip to: 25344 + /* 11705 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 11708 */ MCD_OPC_FilterValue, + 0, + 236, + 0, + 0, // Skip to: 11949 + /* 11713 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 11716 */ MCD_OPC_FilterValue, + 0, + 103, + 0, + 0, // Skip to: 11824 + /* 11721 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11724 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 11762 + /* 11729 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11732 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11747 + /* 11737 */ MCD_OPC_CheckPredicate, + 22, + 34, + 53, + 0, // Skip to: 25344 + /* 11742 */ MCD_OPC_Decode, + 195, + 8, + 145, + 1, // Opcode: MVE_VHADD_qr_s32 + /* 11747 */ MCD_OPC_FilterValue, + 15, + 24, + 53, + 0, // Skip to: 25344 + /* 11752 */ MCD_OPC_CheckPredicate, + 22, + 19, + 53, + 0, // Skip to: 25344 + /* 11757 */ MCD_OPC_Decode, + 198, + 8, + 145, + 1, // Opcode: MVE_VHADD_qr_u32 + /* 11762 */ MCD_OPC_FilterValue, + 1, + 9, + 53, + 0, // Skip to: 25344 + /* 11767 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11770 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11785 + /* 11775 */ MCD_OPC_CheckPredicate, + 22, + 252, + 52, + 0, // Skip to: 25344 + /* 11780 */ MCD_OPC_Decode, + 213, + 7, + 145, + 1, // Opcode: MVE_VADD_qr_i32 + /* 11785 */ MCD_OPC_FilterValue, + 15, + 242, + 52, + 0, // Skip to: 25344 + /* 11790 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11814 + /* 11795 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11814 + /* 11802 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11814 + /* 11809 */ MCD_OPC_Decode, + 247, + 7, + 157, + 1, // Opcode: MVE_VCMPi32r + /* 11814 */ MCD_OPC_CheckPredicate, + 22, + 213, + 52, + 0, // Skip to: 25344 + /* 11819 */ MCD_OPC_Decode, + 244, + 10, + 158, + 1, // Opcode: MVE_VPTv4i32r + /* 11824 */ MCD_OPC_FilterValue, + 2, + 203, + 52, + 0, // Skip to: 25344 + /* 11829 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11832 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 11870 + /* 11837 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11840 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11855 + /* 11845 */ MCD_OPC_CheckPredicate, + 22, + 182, + 52, + 0, // Skip to: 25344 + /* 11850 */ MCD_OPC_Decode, + 133, + 11, + 145, + 1, // Opcode: MVE_VQADD_qr_s32 + /* 11855 */ MCD_OPC_FilterValue, + 15, + 172, + 52, + 0, // Skip to: 25344 + /* 11860 */ MCD_OPC_CheckPredicate, + 22, + 167, + 52, + 0, // Skip to: 25344 + /* 11865 */ MCD_OPC_Decode, + 136, + 11, + 145, + 1, // Opcode: MVE_VQADD_qr_u32 + /* 11870 */ MCD_OPC_FilterValue, + 1, + 157, + 52, + 0, // Skip to: 25344 + /* 11875 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11878 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 11910 + /* 11883 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 11900 + /* 11888 */ MCD_OPC_CheckField, + 1, + 3, + 7, + 5, + 0, + 0, // Skip to: 11900 + /* 11895 */ MCD_OPC_Decode, + 222, + 8, + 159, + 1, // Opcode: MVE_VIDUPu32 + /* 11900 */ MCD_OPC_CheckPredicate, + 22, + 127, + 52, + 0, // Skip to: 25344 + /* 11905 */ MCD_OPC_Decode, + 225, + 8, + 160, + 1, // Opcode: MVE_VIWDUPu32 + /* 11910 */ MCD_OPC_FilterValue, + 15, + 117, + 52, + 0, // Skip to: 25344 + /* 11915 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11939 + /* 11920 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11939 + /* 11927 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11939 + /* 11934 */ MCD_OPC_Decode, + 131, + 8, + 161, + 1, // Opcode: MVE_VCMPu32r + /* 11939 */ MCD_OPC_CheckPredicate, + 22, + 88, + 52, + 0, // Skip to: 25344 + /* 11944 */ MCD_OPC_Decode, + 248, + 10, + 162, + 1, // Opcode: MVE_VPTv4u32r + /* 11949 */ MCD_OPC_FilterValue, + 1, + 78, + 52, + 0, // Skip to: 25344 + /* 11954 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11957 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 12041 + /* 11962 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 11965 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 12003 + /* 11970 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11973 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11988 + /* 11978 */ MCD_OPC_CheckPredicate, + 22, + 49, + 52, + 0, // Skip to: 25344 + /* 11983 */ MCD_OPC_Decode, + 210, + 8, + 145, + 1, // Opcode: MVE_VHSUB_qr_s32 + /* 11988 */ MCD_OPC_FilterValue, + 15, + 39, + 52, + 0, // Skip to: 25344 + /* 11993 */ MCD_OPC_CheckPredicate, + 22, + 34, + 52, + 0, // Skip to: 25344 + /* 11998 */ MCD_OPC_Decode, + 213, + 8, + 145, + 1, // Opcode: MVE_VHSUB_qr_u32 + /* 12003 */ MCD_OPC_FilterValue, + 2, + 24, + 52, + 0, // Skip to: 25344 + /* 12008 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12011 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12026 + /* 12016 */ MCD_OPC_CheckPredicate, + 22, + 11, + 52, + 0, // Skip to: 25344 + /* 12021 */ MCD_OPC_Decode, + 145, + 12, + 145, + 1, // Opcode: MVE_VQSUB_qr_s32 + /* 12026 */ MCD_OPC_FilterValue, + 15, + 1, + 52, + 0, // Skip to: 25344 + /* 12031 */ MCD_OPC_CheckPredicate, + 22, + 252, + 51, + 0, // Skip to: 25344 + /* 12036 */ MCD_OPC_Decode, + 148, + 12, + 145, + 1, // Opcode: MVE_VQSUB_qr_u32 + /* 12041 */ MCD_OPC_FilterValue, + 1, + 242, + 51, + 0, // Skip to: 25344 + /* 12046 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12049 */ MCD_OPC_FilterValue, + 14, + 50, + 0, + 0, // Skip to: 12104 + /* 12054 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 12057 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 12072 + /* 12062 */ MCD_OPC_CheckPredicate, + 22, + 221, + 51, + 0, // Skip to: 25344 + /* 12067 */ MCD_OPC_Decode, + 212, + 13, + 145, + 1, // Opcode: MVE_VSUB_qr_i32 + /* 12072 */ MCD_OPC_FilterValue, + 2, + 211, + 51, + 0, // Skip to: 25344 + /* 12077 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 12094 + /* 12082 */ MCD_OPC_CheckField, + 1, + 3, + 7, + 5, + 0, + 0, // Skip to: 12094 + /* 12089 */ MCD_OPC_Decode, + 177, + 8, + 159, + 1, // Opcode: MVE_VDDUPu32 + /* 12094 */ MCD_OPC_CheckPredicate, + 22, + 189, + 51, + 0, // Skip to: 25344 + /* 12099 */ MCD_OPC_Decode, + 183, + 8, + 160, + 1, // Opcode: MVE_VDWDUPu32 + /* 12104 */ MCD_OPC_FilterValue, + 15, + 179, + 51, + 0, // Skip to: 25344 + /* 12109 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 12112 */ MCD_OPC_FilterValue, + 0, + 171, + 51, + 0, // Skip to: 25344 + /* 12117 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 12141 + /* 12122 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 12141 + /* 12129 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 12141 + /* 12136 */ MCD_OPC_Decode, + 253, + 7, + 163, + 1, // Opcode: MVE_VCMPs32r + /* 12141 */ MCD_OPC_CheckPredicate, + 22, + 142, + 51, + 0, // Skip to: 25344 + /* 12146 */ MCD_OPC_Decode, + 246, + 10, + 164, + 1, // Opcode: MVE_VPTv4s32r + /* 12151 */ MCD_OPC_FilterValue, + 3, + 132, + 51, + 0, // Skip to: 25344 + /* 12156 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 12159 */ MCD_OPC_FilterValue, + 0, + 105, + 1, + 0, // Skip to: 12525 + /* 12164 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 12167 */ MCD_OPC_FilterValue, + 0, + 227, + 0, + 0, // Skip to: 12399 + /* 12172 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 12175 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 12287 + /* 12180 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 12183 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 12235 + /* 12188 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12191 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 12213 + /* 12196 */ MCD_OPC_CheckPredicate, + 22, + 87, + 51, + 0, // Skip to: 25344 + /* 12201 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 80, + 51, + 0, // Skip to: 25344 + /* 12208 */ MCD_OPC_Decode, + 192, + 7, + 165, + 1, // Opcode: MVE_VADC + /* 12213 */ MCD_OPC_FilterValue, + 15, + 70, + 51, + 0, // Skip to: 25344 + /* 12218 */ MCD_OPC_CheckPredicate, + 22, + 65, + 51, + 0, // Skip to: 25344 + /* 12223 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 58, + 51, + 0, // Skip to: 25344 + /* 12230 */ MCD_OPC_Decode, + 218, + 12, + 165, + 1, // Opcode: MVE_VSBC + /* 12235 */ MCD_OPC_FilterValue, + 1, + 48, + 51, + 0, // Skip to: 25344 + /* 12240 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12243 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 12265 + /* 12248 */ MCD_OPC_CheckPredicate, + 22, + 35, + 51, + 0, // Skip to: 25344 + /* 12253 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 28, + 51, + 0, // Skip to: 25344 + /* 12260 */ MCD_OPC_Decode, + 193, + 7, + 165, + 1, // Opcode: MVE_VADCI + /* 12265 */ MCD_OPC_FilterValue, + 15, + 18, + 51, + 0, // Skip to: 25344 + /* 12270 */ MCD_OPC_CheckPredicate, + 22, + 13, + 51, + 0, // Skip to: 25344 + /* 12275 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 6, + 51, + 0, // Skip to: 25344 + /* 12282 */ MCD_OPC_Decode, + 219, + 12, + 165, + 1, // Opcode: MVE_VSBCI + /* 12287 */ MCD_OPC_FilterValue, + 1, + 252, + 50, + 0, // Skip to: 25344 + /* 12292 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 12295 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 12347 + /* 12300 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12303 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 12325 + /* 12308 */ MCD_OPC_CheckPredicate, + 22, + 231, + 50, + 0, // Skip to: 25344 + /* 12313 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 224, + 50, + 0, // Skip to: 25344 + /* 12320 */ MCD_OPC_Decode, + 172, + 11, + 143, + 1, // Opcode: MVE_VQDMULLs16bh + /* 12325 */ MCD_OPC_FilterValue, + 15, + 214, + 50, + 0, // Skip to: 25344 + /* 12330 */ MCD_OPC_CheckPredicate, + 22, + 209, + 50, + 0, // Skip to: 25344 + /* 12335 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 202, + 50, + 0, // Skip to: 25344 + /* 12342 */ MCD_OPC_Decode, + 174, + 11, + 143, + 1, // Opcode: MVE_VQDMULLs32bh + /* 12347 */ MCD_OPC_FilterValue, + 1, + 192, + 50, + 0, // Skip to: 25344 + /* 12352 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12355 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 12377 + /* 12360 */ MCD_OPC_CheckPredicate, + 22, + 179, + 50, + 0, // Skip to: 25344 + /* 12365 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 172, + 50, + 0, // Skip to: 25344 + /* 12372 */ MCD_OPC_Decode, + 173, + 11, + 143, + 1, // Opcode: MVE_VQDMULLs16th + /* 12377 */ MCD_OPC_FilterValue, + 15, + 162, + 50, + 0, // Skip to: 25344 + /* 12382 */ MCD_OPC_CheckPredicate, + 22, + 157, + 50, + 0, // Skip to: 25344 + /* 12387 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 150, + 50, + 0, // Skip to: 25344 + /* 12394 */ MCD_OPC_Decode, + 175, + 11, + 143, + 1, // Opcode: MVE_VQDMULLs32th + /* 12399 */ MCD_OPC_FilterValue, + 1, + 140, + 50, + 0, // Skip to: 25344 + /* 12404 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12407 */ MCD_OPC_FilterValue, + 14, + 42, + 0, + 0, // Skip to: 12454 + /* 12412 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 12415 */ MCD_OPC_FilterValue, + 0, + 124, + 50, + 0, // Skip to: 25344 + /* 12420 */ MCD_OPC_CheckPredicate, + 24, + 19, + 0, + 0, // Skip to: 12444 + /* 12425 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 12444 + /* 12432 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 12444 + /* 12439 */ MCD_OPC_Decode, + 242, + 7, + 166, + 1, // Opcode: MVE_VCMPf32 + /* 12444 */ MCD_OPC_CheckPredicate, + 24, + 95, + 50, + 0, // Skip to: 25344 + /* 12449 */ MCD_OPC_Decode, + 241, + 10, + 167, + 1, // Opcode: MVE_VPTv4f32 + /* 12454 */ MCD_OPC_FilterValue, + 15, + 85, + 50, + 0, // Skip to: 25344 + /* 12459 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 12462 */ MCD_OPC_FilterValue, + 0, + 77, + 50, + 0, // Skip to: 25344 + /* 12467 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 12491 + /* 12472 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 12, + 0, + 0, // Skip to: 12491 + /* 12479 */ MCD_OPC_CheckField, + 0, + 1, + 1, + 5, + 0, + 0, // Skip to: 12491 + /* 12486 */ MCD_OPC_Decode, + 233, + 10, + 168, + 1, // Opcode: MVE_VPSEL + /* 12491 */ MCD_OPC_CheckPredicate, + 24, + 19, + 0, + 0, // Skip to: 12515 + /* 12496 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 12515 + /* 12503 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 12515 + /* 12510 */ MCD_OPC_Decode, + 240, + 7, + 166, + 1, // Opcode: MVE_VCMPf16 + /* 12515 */ MCD_OPC_CheckPredicate, + 24, + 24, + 50, + 0, // Skip to: 25344 + /* 12520 */ MCD_OPC_Decode, + 249, + 10, + 167, + 1, // Opcode: MVE_VPTv8f16 + /* 12525 */ MCD_OPC_FilterValue, + 1, + 14, + 50, + 0, // Skip to: 25344 + /* 12530 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 12533 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 12709 + /* 12538 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 12541 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 12625 + /* 12546 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 12549 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 12587 + /* 12554 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12557 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12572 + /* 12562 */ MCD_OPC_CheckPredicate, + 24, + 233, + 49, + 0, // Skip to: 25344 + /* 12567 */ MCD_OPC_Decode, + 211, + 7, + 145, + 1, // Opcode: MVE_VADD_qr_f32 + /* 12572 */ MCD_OPC_FilterValue, + 15, + 223, + 49, + 0, // Skip to: 25344 + /* 12577 */ MCD_OPC_CheckPredicate, + 24, + 218, + 49, + 0, // Skip to: 25344 + /* 12582 */ MCD_OPC_Decode, + 210, + 7, + 145, + 1, // Opcode: MVE_VADD_qr_f16 + /* 12587 */ MCD_OPC_FilterValue, + 1, + 208, + 49, + 0, // Skip to: 25344 + /* 12592 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12595 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12610 + /* 12600 */ MCD_OPC_CheckPredicate, + 24, + 195, + 49, + 0, // Skip to: 25344 + /* 12605 */ MCD_OPC_Decode, + 210, + 13, + 145, + 1, // Opcode: MVE_VSUB_qr_f32 + /* 12610 */ MCD_OPC_FilterValue, + 15, + 185, + 49, + 0, // Skip to: 25344 + /* 12615 */ MCD_OPC_CheckPredicate, + 24, + 180, + 49, + 0, // Skip to: 25344 + /* 12620 */ MCD_OPC_Decode, + 209, + 13, + 145, + 1, // Opcode: MVE_VSUB_qr_f16 + /* 12625 */ MCD_OPC_FilterValue, + 2, + 170, + 49, + 0, // Skip to: 25344 + /* 12630 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 12633 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 12671 + /* 12638 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12641 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12656 + /* 12646 */ MCD_OPC_CheckPredicate, + 22, + 149, + 49, + 0, // Skip to: 25344 + /* 12651 */ MCD_OPC_Decode, + 168, + 11, + 145, + 1, // Opcode: MVE_VQDMULL_qr_s16bh + /* 12656 */ MCD_OPC_FilterValue, + 15, + 139, + 49, + 0, // Skip to: 25344 + /* 12661 */ MCD_OPC_CheckPredicate, + 22, + 134, + 49, + 0, // Skip to: 25344 + /* 12666 */ MCD_OPC_Decode, + 170, + 11, + 145, + 1, // Opcode: MVE_VQDMULL_qr_s32bh + /* 12671 */ MCD_OPC_FilterValue, + 1, + 124, + 49, + 0, // Skip to: 25344 + /* 12676 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12679 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12694 + /* 12684 */ MCD_OPC_CheckPredicate, + 22, + 111, + 49, + 0, // Skip to: 25344 + /* 12689 */ MCD_OPC_Decode, + 169, + 11, + 145, + 1, // Opcode: MVE_VQDMULL_qr_s16th + /* 12694 */ MCD_OPC_FilterValue, + 15, + 101, + 49, + 0, // Skip to: 25344 + /* 12699 */ MCD_OPC_CheckPredicate, + 22, + 96, + 49, + 0, // Skip to: 25344 + /* 12704 */ MCD_OPC_Decode, + 171, + 11, + 145, + 1, // Opcode: MVE_VQDMULL_qr_s32th + /* 12709 */ MCD_OPC_FilterValue, + 1, + 86, + 49, + 0, // Skip to: 25344 + /* 12714 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12717 */ MCD_OPC_FilterValue, + 14, + 42, + 0, + 0, // Skip to: 12764 + /* 12722 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 12725 */ MCD_OPC_FilterValue, + 0, + 70, + 49, + 0, // Skip to: 25344 + /* 12730 */ MCD_OPC_CheckPredicate, + 24, + 19, + 0, + 0, // Skip to: 12754 + /* 12735 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 12754 + /* 12742 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 12754 + /* 12749 */ MCD_OPC_Decode, + 243, + 7, + 169, + 1, // Opcode: MVE_VCMPf32r + /* 12754 */ MCD_OPC_CheckPredicate, + 24, + 41, + 49, + 0, // Skip to: 25344 + /* 12759 */ MCD_OPC_Decode, + 242, + 10, + 170, + 1, // Opcode: MVE_VPTv4f32r + /* 12764 */ MCD_OPC_FilterValue, + 15, + 31, + 49, + 0, // Skip to: 25344 + /* 12769 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 12772 */ MCD_OPC_FilterValue, + 0, + 23, + 49, + 0, // Skip to: 25344 + /* 12777 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 12780 */ MCD_OPC_FilterValue, + 13, + 50, + 0, + 0, // Skip to: 12835 + /* 12785 */ MCD_OPC_CheckPredicate, + 22, + 24, + 0, + 0, // Skip to: 12814 + /* 12790 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 17, + 0, + 0, // Skip to: 12814 + /* 12797 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 10, + 0, + 0, // Skip to: 12814 + /* 12804 */ MCD_OPC_SoftFail, + 160, + 161, + 56 /* 0xe10a0 */, + 0, + /* 12809 */ MCD_OPC_Decode, + 232, + 10, + 171, + 1, // Opcode: MVE_VPNOT + /* 12814 */ MCD_OPC_CheckPredicate, + 22, + 16, + 0, + 0, // Skip to: 12835 + /* 12819 */ MCD_OPC_CheckField, + 17, + 3, + 0, + 9, + 0, + 0, // Skip to: 12835 + /* 12826 */ MCD_OPC_SoftFail, + 160, + 33 /* 0x10a0 */, + 0, + /* 12830 */ MCD_OPC_Decode, + 234, + 10, + 172, + 1, // Opcode: MVE_VPST + /* 12835 */ MCD_OPC_CheckPredicate, + 24, + 19, + 0, + 0, // Skip to: 12859 + /* 12840 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 12859 + /* 12847 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 12859 + /* 12854 */ MCD_OPC_Decode, + 241, + 7, + 169, + 1, // Opcode: MVE_VCMPf16r + /* 12859 */ MCD_OPC_CheckPredicate, + 24, + 192, + 48, + 0, // Skip to: 25344 + /* 12864 */ MCD_OPC_Decode, + 250, + 10, + 170, + 1, // Opcode: MVE_VPTv8f16r + /* 12869 */ MCD_OPC_FilterValue, + 1, + 119, + 16, + 0, // Skip to: 17089 + /* 12874 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 12877 */ MCD_OPC_FilterValue, + 11, + 179, + 0, + 0, // Skip to: 13061 + /* 12882 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 12885 */ MCD_OPC_FilterValue, + 0, + 105, + 0, + 0, // Skip to: 12995 + /* 12890 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 12893 */ MCD_OPC_FilterValue, + 16, + 61, + 0, + 0, // Skip to: 12959 + /* 12898 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 12901 */ MCD_OPC_FilterValue, + 1, + 24, + 0, + 0, // Skip to: 12930 + /* 12906 */ MCD_OPC_CheckPredicate, + 22, + 145, + 48, + 0, // Skip to: 25344 + /* 12911 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 138, + 48, + 0, // Skip to: 25344 + /* 12918 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 131, + 48, + 0, // Skip to: 25344 + /* 12925 */ MCD_OPC_Decode, + 180, + 8, + 173, + 1, // Opcode: MVE_VDUP32 + /* 12930 */ MCD_OPC_FilterValue, + 3, + 121, + 48, + 0, // Skip to: 25344 + /* 12935 */ MCD_OPC_CheckPredicate, + 22, + 116, + 48, + 0, // Skip to: 25344 + /* 12940 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 109, + 48, + 0, // Skip to: 25344 + /* 12947 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 102, + 48, + 0, // Skip to: 25344 + /* 12954 */ MCD_OPC_Decode, + 181, + 8, + 173, + 1, // Opcode: MVE_VDUP8 + /* 12959 */ MCD_OPC_FilterValue, + 48, + 92, + 48, + 0, // Skip to: 25344 + /* 12964 */ MCD_OPC_CheckPredicate, + 22, + 87, + 48, + 0, // Skip to: 25344 + /* 12969 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 80, + 48, + 0, // Skip to: 25344 + /* 12976 */ MCD_OPC_CheckField, + 21, + 2, + 1, + 73, + 48, + 0, // Skip to: 25344 + /* 12983 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 66, + 48, + 0, // Skip to: 25344 + /* 12990 */ MCD_OPC_Decode, + 179, + 8, + 173, + 1, // Opcode: MVE_VDUP16 + /* 12995 */ MCD_OPC_FilterValue, + 1, + 56, + 48, + 0, // Skip to: 25344 + /* 13000 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 13003 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 13032 + /* 13008 */ MCD_OPC_CheckPredicate, + 23, + 43, + 48, + 0, // Skip to: 25344 + /* 13013 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 36, + 48, + 0, // Skip to: 25344 + /* 13020 */ MCD_OPC_CheckField, + 0, + 6, + 48, + 29, + 48, + 0, // Skip to: 25344 + /* 13027 */ MCD_OPC_Decode, + 176, + 10, + 140, + 1, // Opcode: MVE_VMOV_from_lane_u16 + /* 13032 */ MCD_OPC_FilterValue, + 1, + 19, + 48, + 0, // Skip to: 25344 + /* 13037 */ MCD_OPC_CheckPredicate, + 23, + 14, + 48, + 0, // Skip to: 25344 + /* 13042 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 7, + 48, + 0, // Skip to: 25344 + /* 13049 */ MCD_OPC_CheckField, + 0, + 5, + 16, + 0, + 48, + 0, // Skip to: 25344 + /* 13056 */ MCD_OPC_Decode, + 177, + 10, + 141, + 1, // Opcode: MVE_VMOV_from_lane_u8 + /* 13061 */ MCD_OPC_FilterValue, + 14, + 243, + 3, + 0, // Skip to: 14077 + /* 13066 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 13069 */ MCD_OPC_FilterValue, + 0, + 243, + 1, + 0, // Skip to: 13573 + /* 13074 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 13077 */ MCD_OPC_FilterValue, + 0, + 243, + 0, + 0, // Skip to: 13325 + /* 13082 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 13085 */ MCD_OPC_FilterValue, + 0, + 147, + 0, + 0, // Skip to: 13237 + /* 13090 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13093 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 13165 + /* 13098 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13101 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13133 + /* 13106 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13123 + /* 13111 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13123 + /* 13118 */ MCD_OPC_Decode, + 242, + 9, + 174, + 1, // Opcode: MVE_VMLADAVs16 + /* 13123 */ MCD_OPC_CheckPredicate, + 22, + 184, + 47, + 0, // Skip to: 25344 + /* 13128 */ MCD_OPC_Decode, + 129, + 10, + 175, + 1, // Opcode: MVE_VMLALDAVs16 + /* 13133 */ MCD_OPC_FilterValue, + 15, + 174, + 47, + 0, // Skip to: 25344 + /* 13138 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13155 + /* 13143 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13155 + /* 13150 */ MCD_OPC_Decode, + 245, + 9, + 174, + 1, // Opcode: MVE_VMLADAVu16 + /* 13155 */ MCD_OPC_CheckPredicate, + 22, + 152, + 47, + 0, // Skip to: 25344 + /* 13160 */ MCD_OPC_Decode, + 131, + 10, + 175, + 1, // Opcode: MVE_VMLALDAVu16 + /* 13165 */ MCD_OPC_FilterValue, + 1, + 142, + 47, + 0, // Skip to: 25344 + /* 13170 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13173 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13205 + /* 13178 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13195 + /* 13183 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13195 + /* 13190 */ MCD_OPC_Decode, + 243, + 9, + 174, + 1, // Opcode: MVE_VMLADAVs32 + /* 13195 */ MCD_OPC_CheckPredicate, + 22, + 112, + 47, + 0, // Skip to: 25344 + /* 13200 */ MCD_OPC_Decode, + 130, + 10, + 175, + 1, // Opcode: MVE_VMLALDAVs32 + /* 13205 */ MCD_OPC_FilterValue, + 15, + 102, + 47, + 0, // Skip to: 25344 + /* 13210 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13227 + /* 13215 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13227 + /* 13222 */ MCD_OPC_Decode, + 246, + 9, + 174, + 1, // Opcode: MVE_VMLADAVu32 + /* 13227 */ MCD_OPC_CheckPredicate, + 22, + 80, + 47, + 0, // Skip to: 25344 + /* 13232 */ MCD_OPC_Decode, + 132, + 10, + 175, + 1, // Opcode: MVE_VMLALDAVu32 + /* 13237 */ MCD_OPC_FilterValue, + 1, + 70, + 47, + 0, // Skip to: 25344 + /* 13242 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13245 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 13285 + /* 13250 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13253 */ MCD_OPC_FilterValue, + 14, + 54, + 47, + 0, // Skip to: 25344 + /* 13258 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13275 + /* 13263 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13275 + /* 13270 */ MCD_OPC_Decode, + 248, + 9, + 174, + 1, // Opcode: MVE_VMLADAVxs16 + /* 13275 */ MCD_OPC_CheckPredicate, + 22, + 32, + 47, + 0, // Skip to: 25344 + /* 13280 */ MCD_OPC_Decode, + 133, + 10, + 175, + 1, // Opcode: MVE_VMLALDAVxs16 + /* 13285 */ MCD_OPC_FilterValue, + 1, + 22, + 47, + 0, // Skip to: 25344 + /* 13290 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13293 */ MCD_OPC_FilterValue, + 14, + 14, + 47, + 0, // Skip to: 25344 + /* 13298 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13315 + /* 13303 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13315 + /* 13310 */ MCD_OPC_Decode, + 249, + 9, + 174, + 1, // Opcode: MVE_VMLADAVxs32 + /* 13315 */ MCD_OPC_CheckPredicate, + 22, + 248, + 46, + 0, // Skip to: 25344 + /* 13320 */ MCD_OPC_Decode, + 134, + 10, + 175, + 1, // Opcode: MVE_VMLALDAVxs32 + /* 13325 */ MCD_OPC_FilterValue, + 2, + 238, + 46, + 0, // Skip to: 25344 + /* 13330 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 13333 */ MCD_OPC_FilterValue, + 0, + 147, + 0, + 0, // Skip to: 13485 + /* 13338 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13341 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 13413 + /* 13346 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13349 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13381 + /* 13354 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13371 + /* 13359 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13371 + /* 13366 */ MCD_OPC_Decode, + 233, + 9, + 176, + 1, // Opcode: MVE_VMLADAVas16 + /* 13371 */ MCD_OPC_CheckPredicate, + 22, + 192, + 46, + 0, // Skip to: 25344 + /* 13376 */ MCD_OPC_Decode, + 251, + 9, + 177, + 1, // Opcode: MVE_VMLALDAVas16 + /* 13381 */ MCD_OPC_FilterValue, + 15, + 182, + 46, + 0, // Skip to: 25344 + /* 13386 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13403 + /* 13391 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13403 + /* 13398 */ MCD_OPC_Decode, + 236, + 9, + 176, + 1, // Opcode: MVE_VMLADAVau16 + /* 13403 */ MCD_OPC_CheckPredicate, + 22, + 160, + 46, + 0, // Skip to: 25344 + /* 13408 */ MCD_OPC_Decode, + 253, + 9, + 177, + 1, // Opcode: MVE_VMLALDAVau16 + /* 13413 */ MCD_OPC_FilterValue, + 1, + 150, + 46, + 0, // Skip to: 25344 + /* 13418 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13421 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13453 + /* 13426 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13443 + /* 13431 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13443 + /* 13438 */ MCD_OPC_Decode, + 234, + 9, + 176, + 1, // Opcode: MVE_VMLADAVas32 + /* 13443 */ MCD_OPC_CheckPredicate, + 22, + 120, + 46, + 0, // Skip to: 25344 + /* 13448 */ MCD_OPC_Decode, + 252, + 9, + 177, + 1, // Opcode: MVE_VMLALDAVas32 + /* 13453 */ MCD_OPC_FilterValue, + 15, + 110, + 46, + 0, // Skip to: 25344 + /* 13458 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13475 + /* 13463 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13475 + /* 13470 */ MCD_OPC_Decode, + 237, + 9, + 176, + 1, // Opcode: MVE_VMLADAVau32 + /* 13475 */ MCD_OPC_CheckPredicate, + 22, + 88, + 46, + 0, // Skip to: 25344 + /* 13480 */ MCD_OPC_Decode, + 254, + 9, + 177, + 1, // Opcode: MVE_VMLALDAVau32 + /* 13485 */ MCD_OPC_FilterValue, + 1, + 78, + 46, + 0, // Skip to: 25344 + /* 13490 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13493 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 13533 + /* 13498 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13501 */ MCD_OPC_FilterValue, + 14, + 62, + 46, + 0, // Skip to: 25344 + /* 13506 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13523 + /* 13511 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13523 + /* 13518 */ MCD_OPC_Decode, + 239, + 9, + 176, + 1, // Opcode: MVE_VMLADAVaxs16 + /* 13523 */ MCD_OPC_CheckPredicate, + 22, + 40, + 46, + 0, // Skip to: 25344 + /* 13528 */ MCD_OPC_Decode, + 255, + 9, + 177, + 1, // Opcode: MVE_VMLALDAVaxs16 + /* 13533 */ MCD_OPC_FilterValue, + 1, + 30, + 46, + 0, // Skip to: 25344 + /* 13538 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13541 */ MCD_OPC_FilterValue, + 14, + 22, + 46, + 0, // Skip to: 25344 + /* 13546 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13563 + /* 13551 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13563 + /* 13558 */ MCD_OPC_Decode, + 240, + 9, + 176, + 1, // Opcode: MVE_VMLADAVaxs32 + /* 13563 */ MCD_OPC_CheckPredicate, + 22, + 0, + 46, + 0, // Skip to: 25344 + /* 13568 */ MCD_OPC_Decode, + 128, + 10, + 177, + 1, // Opcode: MVE_VMLALDAVaxs32 + /* 13573 */ MCD_OPC_FilterValue, + 1, + 246, + 45, + 0, // Skip to: 25344 + /* 13578 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 13581 */ MCD_OPC_FilterValue, + 0, + 243, + 0, + 0, // Skip to: 13829 + /* 13586 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 13589 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 13709 + /* 13594 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13597 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 13669 + /* 13602 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13605 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13637 + /* 13610 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13627 + /* 13615 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13627 + /* 13622 */ MCD_OPC_Decode, + 147, + 10, + 174, + 1, // Opcode: MVE_VMLSDAVs16 + /* 13627 */ MCD_OPC_CheckPredicate, + 22, + 192, + 45, + 0, // Skip to: 25344 + /* 13632 */ MCD_OPC_Decode, + 157, + 10, + 175, + 1, // Opcode: MVE_VMLSLDAVs16 + /* 13637 */ MCD_OPC_FilterValue, + 15, + 182, + 45, + 0, // Skip to: 25344 + /* 13642 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13659 + /* 13647 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13659 + /* 13654 */ MCD_OPC_Decode, + 149, + 10, + 174, + 1, // Opcode: MVE_VMLSDAVs8 + /* 13659 */ MCD_OPC_CheckPredicate, + 22, + 160, + 45, + 0, // Skip to: 25344 + /* 13664 */ MCD_OPC_Decode, + 188, + 12, + 175, + 1, // Opcode: MVE_VRMLSLDAVHs32 + /* 13669 */ MCD_OPC_FilterValue, + 1, + 150, + 45, + 0, // Skip to: 25344 + /* 13674 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13677 */ MCD_OPC_FilterValue, + 14, + 142, + 45, + 0, // Skip to: 25344 + /* 13682 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13699 + /* 13687 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13699 + /* 13694 */ MCD_OPC_Decode, + 148, + 10, + 174, + 1, // Opcode: MVE_VMLSDAVs32 + /* 13699 */ MCD_OPC_CheckPredicate, + 22, + 120, + 45, + 0, // Skip to: 25344 + /* 13704 */ MCD_OPC_Decode, + 158, + 10, + 175, + 1, // Opcode: MVE_VMLSLDAVs32 + /* 13709 */ MCD_OPC_FilterValue, + 1, + 110, + 45, + 0, // Skip to: 25344 + /* 13714 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13717 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 13789 + /* 13722 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13725 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13757 + /* 13730 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13747 + /* 13735 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13747 + /* 13742 */ MCD_OPC_Decode, + 150, + 10, + 174, + 1, // Opcode: MVE_VMLSDAVxs16 + /* 13747 */ MCD_OPC_CheckPredicate, + 22, + 72, + 45, + 0, // Skip to: 25344 + /* 13752 */ MCD_OPC_Decode, + 159, + 10, + 175, + 1, // Opcode: MVE_VMLSLDAVxs16 + /* 13757 */ MCD_OPC_FilterValue, + 15, + 62, + 45, + 0, // Skip to: 25344 + /* 13762 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13779 + /* 13767 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13779 + /* 13774 */ MCD_OPC_Decode, + 152, + 10, + 174, + 1, // Opcode: MVE_VMLSDAVxs8 + /* 13779 */ MCD_OPC_CheckPredicate, + 22, + 40, + 45, + 0, // Skip to: 25344 + /* 13784 */ MCD_OPC_Decode, + 189, + 12, + 175, + 1, // Opcode: MVE_VRMLSLDAVHxs32 + /* 13789 */ MCD_OPC_FilterValue, + 1, + 30, + 45, + 0, // Skip to: 25344 + /* 13794 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13797 */ MCD_OPC_FilterValue, + 14, + 22, + 45, + 0, // Skip to: 25344 + /* 13802 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13819 + /* 13807 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13819 + /* 13814 */ MCD_OPC_Decode, + 151, + 10, + 174, + 1, // Opcode: MVE_VMLSDAVxs32 + /* 13819 */ MCD_OPC_CheckPredicate, + 22, + 0, + 45, + 0, // Skip to: 25344 + /* 13824 */ MCD_OPC_Decode, + 160, + 10, + 175, + 1, // Opcode: MVE_VMLSLDAVxs32 + /* 13829 */ MCD_OPC_FilterValue, + 2, + 246, + 44, + 0, // Skip to: 25344 + /* 13834 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 13837 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 13957 + /* 13842 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13845 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 13917 + /* 13850 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13853 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13885 + /* 13858 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13875 + /* 13863 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13875 + /* 13870 */ MCD_OPC_Decode, + 141, + 10, + 176, + 1, // Opcode: MVE_VMLSDAVas16 + /* 13875 */ MCD_OPC_CheckPredicate, + 22, + 200, + 44, + 0, // Skip to: 25344 + /* 13880 */ MCD_OPC_Decode, + 153, + 10, + 177, + 1, // Opcode: MVE_VMLSLDAVas16 + /* 13885 */ MCD_OPC_FilterValue, + 15, + 190, + 44, + 0, // Skip to: 25344 + /* 13890 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13907 + /* 13895 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13907 + /* 13902 */ MCD_OPC_Decode, + 143, + 10, + 176, + 1, // Opcode: MVE_VMLSDAVas8 + /* 13907 */ MCD_OPC_CheckPredicate, + 22, + 168, + 44, + 0, // Skip to: 25344 + /* 13912 */ MCD_OPC_Decode, + 186, + 12, + 177, + 1, // Opcode: MVE_VRMLSLDAVHas32 + /* 13917 */ MCD_OPC_FilterValue, + 1, + 158, + 44, + 0, // Skip to: 25344 + /* 13922 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13925 */ MCD_OPC_FilterValue, + 14, + 150, + 44, + 0, // Skip to: 25344 + /* 13930 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13947 + /* 13935 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13947 + /* 13942 */ MCD_OPC_Decode, + 142, + 10, + 176, + 1, // Opcode: MVE_VMLSDAVas32 + /* 13947 */ MCD_OPC_CheckPredicate, + 22, + 128, + 44, + 0, // Skip to: 25344 + /* 13952 */ MCD_OPC_Decode, + 154, + 10, + 177, + 1, // Opcode: MVE_VMLSLDAVas32 + /* 13957 */ MCD_OPC_FilterValue, + 1, + 118, + 44, + 0, // Skip to: 25344 + /* 13962 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13965 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 14037 + /* 13970 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13973 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 14005 + /* 13978 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13995 + /* 13983 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13995 + /* 13990 */ MCD_OPC_Decode, + 144, + 10, + 176, + 1, // Opcode: MVE_VMLSDAVaxs16 + /* 13995 */ MCD_OPC_CheckPredicate, + 22, + 80, + 44, + 0, // Skip to: 25344 + /* 14000 */ MCD_OPC_Decode, + 155, + 10, + 177, + 1, // Opcode: MVE_VMLSLDAVaxs16 + /* 14005 */ MCD_OPC_FilterValue, + 15, + 70, + 44, + 0, // Skip to: 25344 + /* 14010 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14027 + /* 14015 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14027 + /* 14022 */ MCD_OPC_Decode, + 146, + 10, + 176, + 1, // Opcode: MVE_VMLSDAVaxs8 + /* 14027 */ MCD_OPC_CheckPredicate, + 22, + 48, + 44, + 0, // Skip to: 25344 + /* 14032 */ MCD_OPC_Decode, + 187, + 12, + 177, + 1, // Opcode: MVE_VRMLSLDAVHaxs32 + /* 14037 */ MCD_OPC_FilterValue, + 1, + 38, + 44, + 0, // Skip to: 25344 + /* 14042 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14045 */ MCD_OPC_FilterValue, + 14, + 30, + 44, + 0, // Skip to: 25344 + /* 14050 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14067 + /* 14055 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14067 + /* 14062 */ MCD_OPC_Decode, + 145, + 10, + 176, + 1, // Opcode: MVE_VMLSDAVaxs32 + /* 14067 */ MCD_OPC_CheckPredicate, + 22, + 8, + 44, + 0, // Skip to: 25344 + /* 14072 */ MCD_OPC_Decode, + 156, + 10, + 177, + 1, // Opcode: MVE_VMLSLDAVaxs32 + /* 14077 */ MCD_OPC_FilterValue, + 15, + 254, + 43, + 0, // Skip to: 25344 + /* 14082 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 14085 */ MCD_OPC_FilterValue, + 0, + 154, + 5, + 0, // Skip to: 15524 + /* 14090 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 14093 */ MCD_OPC_FilterValue, + 0, + 196, + 4, + 0, // Skip to: 15318 + /* 14098 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 14101 */ MCD_OPC_FilterValue, + 0, + 56, + 3, + 0, // Skip to: 14930 + /* 14106 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 14109 */ MCD_OPC_FilterValue, + 0, + 40, + 2, + 0, // Skip to: 14666 + /* 14114 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 14117 */ MCD_OPC_FilterValue, + 0, + 60, + 1, + 0, // Skip to: 14438 + /* 14122 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14125 */ MCD_OPC_FilterValue, + 14, + 190, + 0, + 0, // Skip to: 14320 + /* 14130 */ MCD_OPC_ExtractField, + 17, + 6, // Inst{22-17} ... + /* 14133 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 14148 + /* 14138 */ MCD_OPC_CheckPredicate, + 22, + 110, + 0, + 0, // Skip to: 14253 + /* 14143 */ MCD_OPC_Decode, + 183, + 9, + 178, + 1, // Opcode: MVE_VMAXAVs8 + /* 14148 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 14163 + /* 14153 */ MCD_OPC_CheckPredicate, + 22, + 95, + 0, + 0, // Skip to: 14253 + /* 14158 */ MCD_OPC_Decode, + 197, + 9, + 178, + 1, // Opcode: MVE_VMAXVs8 + /* 14163 */ MCD_OPC_FilterValue, + 50, + 10, + 0, + 0, // Skip to: 14178 + /* 14168 */ MCD_OPC_CheckPredicate, + 22, + 80, + 0, + 0, // Skip to: 14253 + /* 14173 */ MCD_OPC_Decode, + 181, + 9, + 178, + 1, // Opcode: MVE_VMAXAVs16 + /* 14178 */ MCD_OPC_FilterValue, + 51, + 10, + 0, + 0, // Skip to: 14193 + /* 14183 */ MCD_OPC_CheckPredicate, + 22, + 65, + 0, + 0, // Skip to: 14253 + /* 14188 */ MCD_OPC_Decode, + 195, + 9, + 178, + 1, // Opcode: MVE_VMAXVs16 + /* 14193 */ MCD_OPC_FilterValue, + 52, + 10, + 0, + 0, // Skip to: 14208 + /* 14198 */ MCD_OPC_CheckPredicate, + 22, + 50, + 0, + 0, // Skip to: 14253 + /* 14203 */ MCD_OPC_Decode, + 182, + 9, + 178, + 1, // Opcode: MVE_VMAXAVs32 + /* 14208 */ MCD_OPC_FilterValue, + 53, + 10, + 0, + 0, // Skip to: 14223 + /* 14213 */ MCD_OPC_CheckPredicate, + 22, + 35, + 0, + 0, // Skip to: 14253 + /* 14218 */ MCD_OPC_Decode, + 196, + 9, + 178, + 1, // Opcode: MVE_VMAXVs32 + /* 14223 */ MCD_OPC_FilterValue, + 54, + 10, + 0, + 0, // Skip to: 14238 + /* 14228 */ MCD_OPC_CheckPredicate, + 24, + 20, + 0, + 0, // Skip to: 14253 + /* 14233 */ MCD_OPC_Decode, + 188, + 9, + 178, + 1, // Opcode: MVE_VMAXNMAVf32 + /* 14238 */ MCD_OPC_FilterValue, + 55, + 10, + 0, + 0, // Skip to: 14253 + /* 14243 */ MCD_OPC_CheckPredicate, + 24, + 5, + 0, + 0, // Skip to: 14253 + /* 14248 */ MCD_OPC_Decode, + 192, + 9, + 178, + 1, // Opcode: MVE_VMAXNMVf32 + /* 14253 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 14256 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 14288 + /* 14261 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14278 + /* 14266 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14278 + /* 14273 */ MCD_OPC_Decode, + 244, + 9, + 174, + 1, // Opcode: MVE_VMLADAVs8 + /* 14278 */ MCD_OPC_CheckPredicate, + 22, + 53, + 43, + 0, // Skip to: 25344 + /* 14283 */ MCD_OPC_Decode, + 183, + 12, + 175, + 1, // Opcode: MVE_VRMLALDAVHs32 + /* 14288 */ MCD_OPC_FilterValue, + 1, + 43, + 43, + 0, // Skip to: 25344 + /* 14293 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14310 + /* 14298 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14310 + /* 14305 */ MCD_OPC_Decode, + 250, + 9, + 174, + 1, // Opcode: MVE_VMLADAVxs8 + /* 14310 */ MCD_OPC_CheckPredicate, + 22, + 21, + 43, + 0, // Skip to: 25344 + /* 14315 */ MCD_OPC_Decode, + 185, + 12, + 175, + 1, // Opcode: MVE_VRMLALDAVHxs32 + /* 14320 */ MCD_OPC_FilterValue, + 15, + 11, + 43, + 0, // Skip to: 25344 + /* 14325 */ MCD_OPC_ExtractField, + 17, + 6, // Inst{22-17} ... + /* 14328 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 14343 + /* 14333 */ MCD_OPC_CheckPredicate, + 22, + 65, + 0, + 0, // Skip to: 14403 + /* 14338 */ MCD_OPC_Decode, + 200, + 9, + 178, + 1, // Opcode: MVE_VMAXVu8 + /* 14343 */ MCD_OPC_FilterValue, + 51, + 10, + 0, + 0, // Skip to: 14358 + /* 14348 */ MCD_OPC_CheckPredicate, + 22, + 50, + 0, + 0, // Skip to: 14403 + /* 14353 */ MCD_OPC_Decode, + 198, + 9, + 178, + 1, // Opcode: MVE_VMAXVu16 + /* 14358 */ MCD_OPC_FilterValue, + 53, + 10, + 0, + 0, // Skip to: 14373 + /* 14363 */ MCD_OPC_CheckPredicate, + 22, + 35, + 0, + 0, // Skip to: 14403 + /* 14368 */ MCD_OPC_Decode, + 199, + 9, + 178, + 1, // Opcode: MVE_VMAXVu32 + /* 14373 */ MCD_OPC_FilterValue, + 54, + 10, + 0, + 0, // Skip to: 14388 + /* 14378 */ MCD_OPC_CheckPredicate, + 24, + 20, + 0, + 0, // Skip to: 14403 + /* 14383 */ MCD_OPC_Decode, + 187, + 9, + 178, + 1, // Opcode: MVE_VMAXNMAVf16 + /* 14388 */ MCD_OPC_FilterValue, + 55, + 10, + 0, + 0, // Skip to: 14403 + /* 14393 */ MCD_OPC_CheckPredicate, + 24, + 5, + 0, + 0, // Skip to: 14403 + /* 14398 */ MCD_OPC_Decode, + 191, + 9, + 178, + 1, // Opcode: MVE_VMAXNMVf16 + /* 14403 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 14406 */ MCD_OPC_FilterValue, + 0, + 181, + 42, + 0, // Skip to: 25344 + /* 14411 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14428 + /* 14416 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14428 + /* 14423 */ MCD_OPC_Decode, + 247, + 9, + 174, + 1, // Opcode: MVE_VMLADAVu8 + /* 14428 */ MCD_OPC_CheckPredicate, + 22, + 159, + 42, + 0, // Skip to: 25344 + /* 14433 */ MCD_OPC_Decode, + 184, + 12, + 175, + 1, // Opcode: MVE_VRMLALDAVHu32 + /* 14438 */ MCD_OPC_FilterValue, + 1, + 149, + 42, + 0, // Skip to: 25344 + /* 14443 */ MCD_OPC_ExtractField, + 17, + 3, // Inst{19-17} ... + /* 14446 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 14512 + /* 14451 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14454 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 14483 + /* 14459 */ MCD_OPC_CheckPredicate, + 22, + 128, + 42, + 0, // Skip to: 25344 + /* 14464 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 121, + 42, + 0, // Skip to: 25344 + /* 14471 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 114, + 42, + 0, // Skip to: 25344 + /* 14478 */ MCD_OPC_Decode, + 203, + 7, + 179, + 1, // Opcode: MVE_VADDVs8no_acc + /* 14483 */ MCD_OPC_FilterValue, + 15, + 104, + 42, + 0, // Skip to: 25344 + /* 14488 */ MCD_OPC_CheckPredicate, + 22, + 99, + 42, + 0, // Skip to: 25344 + /* 14493 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 92, + 42, + 0, // Skip to: 25344 + /* 14500 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 85, + 42, + 0, // Skip to: 25344 + /* 14507 */ MCD_OPC_Decode, + 209, + 7, + 179, + 1, // Opcode: MVE_VADDVu8no_acc + /* 14512 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 14578 + /* 14517 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14520 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 14549 + /* 14525 */ MCD_OPC_CheckPredicate, + 22, + 62, + 42, + 0, // Skip to: 25344 + /* 14530 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 55, + 42, + 0, // Skip to: 25344 + /* 14537 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 48, + 42, + 0, // Skip to: 25344 + /* 14544 */ MCD_OPC_Decode, + 199, + 7, + 179, + 1, // Opcode: MVE_VADDVs16no_acc + /* 14549 */ MCD_OPC_FilterValue, + 15, + 38, + 42, + 0, // Skip to: 25344 + /* 14554 */ MCD_OPC_CheckPredicate, + 22, + 33, + 42, + 0, // Skip to: 25344 + /* 14559 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 26, + 42, + 0, // Skip to: 25344 + /* 14566 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 19, + 42, + 0, // Skip to: 25344 + /* 14573 */ MCD_OPC_Decode, + 205, + 7, + 179, + 1, // Opcode: MVE_VADDVu16no_acc + /* 14578 */ MCD_OPC_FilterValue, + 4, + 9, + 42, + 0, // Skip to: 25344 + /* 14583 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14586 */ MCD_OPC_FilterValue, + 14, + 35, + 0, + 0, // Skip to: 14626 + /* 14591 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 14594 */ MCD_OPC_FilterValue, + 0, + 249, + 41, + 0, // Skip to: 25344 + /* 14599 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14616 + /* 14604 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14616 + /* 14611 */ MCD_OPC_Decode, + 201, + 7, + 179, + 1, // Opcode: MVE_VADDVs32no_acc + /* 14616 */ MCD_OPC_CheckPredicate, + 22, + 227, + 41, + 0, // Skip to: 25344 + /* 14621 */ MCD_OPC_Decode, + 195, + 7, + 180, + 1, // Opcode: MVE_VADDLVs32no_acc + /* 14626 */ MCD_OPC_FilterValue, + 15, + 217, + 41, + 0, // Skip to: 25344 + /* 14631 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 14634 */ MCD_OPC_FilterValue, + 0, + 209, + 41, + 0, // Skip to: 25344 + /* 14639 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14656 + /* 14644 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14656 + /* 14651 */ MCD_OPC_Decode, + 207, + 7, + 179, + 1, // Opcode: MVE_VADDVu32no_acc + /* 14656 */ MCD_OPC_CheckPredicate, + 22, + 187, + 41, + 0, // Skip to: 25344 + /* 14661 */ MCD_OPC_Decode, + 197, + 7, + 180, + 1, // Opcode: MVE_VADDLVu32no_acc + /* 14666 */ MCD_OPC_FilterValue, + 1, + 177, + 41, + 0, // Skip to: 25344 + /* 14671 */ MCD_OPC_ExtractField, + 16, + 7, // Inst{22-16} ... + /* 14674 */ MCD_OPC_FilterValue, + 96, + 17, + 0, + 0, // Skip to: 14696 + /* 14679 */ MCD_OPC_CheckPredicate, + 22, + 164, + 41, + 0, // Skip to: 25344 + /* 14684 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 157, + 41, + 0, // Skip to: 25344 + /* 14691 */ MCD_OPC_Decode, + 209, + 9, + 178, + 1, // Opcode: MVE_VMINAVs8 + /* 14696 */ MCD_OPC_FilterValue, + 98, + 33, + 0, + 0, // Skip to: 14734 + /* 14701 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14704 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 14719 + /* 14709 */ MCD_OPC_CheckPredicate, + 22, + 134, + 41, + 0, // Skip to: 25344 + /* 14714 */ MCD_OPC_Decode, + 223, + 9, + 178, + 1, // Opcode: MVE_VMINVs8 + /* 14719 */ MCD_OPC_FilterValue, + 15, + 124, + 41, + 0, // Skip to: 25344 + /* 14724 */ MCD_OPC_CheckPredicate, + 22, + 119, + 41, + 0, // Skip to: 25344 + /* 14729 */ MCD_OPC_Decode, + 226, + 9, + 178, + 1, // Opcode: MVE_VMINVu8 + /* 14734 */ MCD_OPC_FilterValue, + 100, + 17, + 0, + 0, // Skip to: 14756 + /* 14739 */ MCD_OPC_CheckPredicate, + 22, + 104, + 41, + 0, // Skip to: 25344 + /* 14744 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 97, + 41, + 0, // Skip to: 25344 + /* 14751 */ MCD_OPC_Decode, + 207, + 9, + 178, + 1, // Opcode: MVE_VMINAVs16 + /* 14756 */ MCD_OPC_FilterValue, + 102, + 33, + 0, + 0, // Skip to: 14794 + /* 14761 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14764 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 14779 + /* 14769 */ MCD_OPC_CheckPredicate, + 22, + 74, + 41, + 0, // Skip to: 25344 + /* 14774 */ MCD_OPC_Decode, + 221, + 9, + 178, + 1, // Opcode: MVE_VMINVs16 + /* 14779 */ MCD_OPC_FilterValue, + 15, + 64, + 41, + 0, // Skip to: 25344 + /* 14784 */ MCD_OPC_CheckPredicate, + 22, + 59, + 41, + 0, // Skip to: 25344 + /* 14789 */ MCD_OPC_Decode, + 224, + 9, + 178, + 1, // Opcode: MVE_VMINVu16 + /* 14794 */ MCD_OPC_FilterValue, + 104, + 17, + 0, + 0, // Skip to: 14816 + /* 14799 */ MCD_OPC_CheckPredicate, + 22, + 44, + 41, + 0, // Skip to: 25344 + /* 14804 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 37, + 41, + 0, // Skip to: 25344 + /* 14811 */ MCD_OPC_Decode, + 208, + 9, + 178, + 1, // Opcode: MVE_VMINAVs32 + /* 14816 */ MCD_OPC_FilterValue, + 106, + 33, + 0, + 0, // Skip to: 14854 + /* 14821 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14824 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 14839 + /* 14829 */ MCD_OPC_CheckPredicate, + 22, + 14, + 41, + 0, // Skip to: 25344 + /* 14834 */ MCD_OPC_Decode, + 222, + 9, + 178, + 1, // Opcode: MVE_VMINVs32 + /* 14839 */ MCD_OPC_FilterValue, + 15, + 4, + 41, + 0, // Skip to: 25344 + /* 14844 */ MCD_OPC_CheckPredicate, + 22, + 255, + 40, + 0, // Skip to: 25344 + /* 14849 */ MCD_OPC_Decode, + 225, + 9, + 178, + 1, // Opcode: MVE_VMINVu32 + /* 14854 */ MCD_OPC_FilterValue, + 108, + 33, + 0, + 0, // Skip to: 14892 + /* 14859 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14862 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 14877 + /* 14867 */ MCD_OPC_CheckPredicate, + 24, + 232, + 40, + 0, // Skip to: 25344 + /* 14872 */ MCD_OPC_Decode, + 214, + 9, + 178, + 1, // Opcode: MVE_VMINNMAVf32 + /* 14877 */ MCD_OPC_FilterValue, + 15, + 222, + 40, + 0, // Skip to: 25344 + /* 14882 */ MCD_OPC_CheckPredicate, + 24, + 217, + 40, + 0, // Skip to: 25344 + /* 14887 */ MCD_OPC_Decode, + 213, + 9, + 178, + 1, // Opcode: MVE_VMINNMAVf16 + /* 14892 */ MCD_OPC_FilterValue, + 110, + 207, + 40, + 0, // Skip to: 25344 + /* 14897 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14900 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 14915 + /* 14905 */ MCD_OPC_CheckPredicate, + 24, + 194, + 40, + 0, // Skip to: 25344 + /* 14910 */ MCD_OPC_Decode, + 218, + 9, + 178, + 1, // Opcode: MVE_VMINNMVf32 + /* 14915 */ MCD_OPC_FilterValue, + 15, + 184, + 40, + 0, // Skip to: 25344 + /* 14920 */ MCD_OPC_CheckPredicate, + 24, + 179, + 40, + 0, // Skip to: 25344 + /* 14925 */ MCD_OPC_Decode, + 217, + 9, + 178, + 1, // Opcode: MVE_VMINNMVf16 + /* 14930 */ MCD_OPC_FilterValue, + 2, + 169, + 40, + 0, // Skip to: 25344 + /* 14935 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 14938 */ MCD_OPC_FilterValue, + 0, + 63, + 1, + 0, // Skip to: 15262 + /* 14943 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 14946 */ MCD_OPC_FilterValue, + 0, + 83, + 0, + 0, // Skip to: 15034 + /* 14951 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14954 */ MCD_OPC_FilterValue, + 14, + 35, + 0, + 0, // Skip to: 14994 + /* 14959 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 14962 */ MCD_OPC_FilterValue, + 0, + 137, + 40, + 0, // Skip to: 25344 + /* 14967 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14984 + /* 14972 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14984 + /* 14979 */ MCD_OPC_Decode, + 235, + 9, + 176, + 1, // Opcode: MVE_VMLADAVas8 + /* 14984 */ MCD_OPC_CheckPredicate, + 22, + 115, + 40, + 0, // Skip to: 25344 + /* 14989 */ MCD_OPC_Decode, + 180, + 12, + 177, + 1, // Opcode: MVE_VRMLALDAVHas32 + /* 14994 */ MCD_OPC_FilterValue, + 15, + 105, + 40, + 0, // Skip to: 25344 + /* 14999 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 15002 */ MCD_OPC_FilterValue, + 0, + 97, + 40, + 0, // Skip to: 25344 + /* 15007 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 15024 + /* 15012 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 15024 + /* 15019 */ MCD_OPC_Decode, + 238, + 9, + 176, + 1, // Opcode: MVE_VMLADAVau8 + /* 15024 */ MCD_OPC_CheckPredicate, + 22, + 75, + 40, + 0, // Skip to: 25344 + /* 15029 */ MCD_OPC_Decode, + 181, + 12, + 177, + 1, // Opcode: MVE_VRMLALDAVHau32 + /* 15034 */ MCD_OPC_FilterValue, + 1, + 65, + 40, + 0, // Skip to: 25344 + /* 15039 */ MCD_OPC_ExtractField, + 17, + 3, // Inst{19-17} ... + /* 15042 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 15108 + /* 15047 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15050 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15079 + /* 15055 */ MCD_OPC_CheckPredicate, + 22, + 44, + 40, + 0, // Skip to: 25344 + /* 15060 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 37, + 40, + 0, // Skip to: 25344 + /* 15067 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 30, + 40, + 0, // Skip to: 25344 + /* 15074 */ MCD_OPC_Decode, + 202, + 7, + 181, + 1, // Opcode: MVE_VADDVs8acc + /* 15079 */ MCD_OPC_FilterValue, + 15, + 20, + 40, + 0, // Skip to: 25344 + /* 15084 */ MCD_OPC_CheckPredicate, + 22, + 15, + 40, + 0, // Skip to: 25344 + /* 15089 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 8, + 40, + 0, // Skip to: 25344 + /* 15096 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 1, + 40, + 0, // Skip to: 25344 + /* 15103 */ MCD_OPC_Decode, + 208, + 7, + 181, + 1, // Opcode: MVE_VADDVu8acc + /* 15108 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 15174 + /* 15113 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15116 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15145 + /* 15121 */ MCD_OPC_CheckPredicate, + 22, + 234, + 39, + 0, // Skip to: 25344 + /* 15126 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 227, + 39, + 0, // Skip to: 25344 + /* 15133 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 220, + 39, + 0, // Skip to: 25344 + /* 15140 */ MCD_OPC_Decode, + 198, + 7, + 181, + 1, // Opcode: MVE_VADDVs16acc + /* 15145 */ MCD_OPC_FilterValue, + 15, + 210, + 39, + 0, // Skip to: 25344 + /* 15150 */ MCD_OPC_CheckPredicate, + 22, + 205, + 39, + 0, // Skip to: 25344 + /* 15155 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 198, + 39, + 0, // Skip to: 25344 + /* 15162 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 191, + 39, + 0, // Skip to: 25344 + /* 15169 */ MCD_OPC_Decode, + 204, + 7, + 181, + 1, // Opcode: MVE_VADDVu16acc + /* 15174 */ MCD_OPC_FilterValue, + 4, + 181, + 39, + 0, // Skip to: 25344 + /* 15179 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15182 */ MCD_OPC_FilterValue, + 14, + 35, + 0, + 0, // Skip to: 15222 + /* 15187 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 15190 */ MCD_OPC_FilterValue, + 0, + 165, + 39, + 0, // Skip to: 25344 + /* 15195 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 15212 + /* 15200 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 15212 + /* 15207 */ MCD_OPC_Decode, + 200, + 7, + 181, + 1, // Opcode: MVE_VADDVs32acc + /* 15212 */ MCD_OPC_CheckPredicate, + 22, + 143, + 39, + 0, // Skip to: 25344 + /* 15217 */ MCD_OPC_Decode, + 194, + 7, + 182, + 1, // Opcode: MVE_VADDLVs32acc + /* 15222 */ MCD_OPC_FilterValue, + 15, + 133, + 39, + 0, // Skip to: 25344 + /* 15227 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 15230 */ MCD_OPC_FilterValue, + 0, + 125, + 39, + 0, // Skip to: 25344 + /* 15235 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 15252 + /* 15240 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 15252 + /* 15247 */ MCD_OPC_Decode, + 206, + 7, + 181, + 1, // Opcode: MVE_VADDVu32acc + /* 15252 */ MCD_OPC_CheckPredicate, + 22, + 103, + 39, + 0, // Skip to: 25344 + /* 15257 */ MCD_OPC_Decode, + 196, + 7, + 182, + 1, // Opcode: MVE_VADDLVu32acc + /* 15262 */ MCD_OPC_FilterValue, + 1, + 93, + 39, + 0, // Skip to: 25344 + /* 15267 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 15270 */ MCD_OPC_FilterValue, + 0, + 85, + 39, + 0, // Skip to: 25344 + /* 15275 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 15278 */ MCD_OPC_FilterValue, + 0, + 77, + 39, + 0, // Skip to: 25344 + /* 15283 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15286 */ MCD_OPC_FilterValue, + 14, + 69, + 39, + 0, // Skip to: 25344 + /* 15291 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 15308 + /* 15296 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 15308 + /* 15303 */ MCD_OPC_Decode, + 241, + 9, + 176, + 1, // Opcode: MVE_VMLADAVaxs8 + /* 15308 */ MCD_OPC_CheckPredicate, + 22, + 47, + 39, + 0, // Skip to: 25344 + /* 15313 */ MCD_OPC_Decode, + 182, + 12, + 177, + 1, // Opcode: MVE_VRMLALDAVHaxs32 + /* 15318 */ MCD_OPC_FilterValue, + 1, + 37, + 39, + 0, // Skip to: 25344 + /* 15323 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 15326 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 15392 + /* 15331 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15334 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15363 + /* 15339 */ MCD_OPC_CheckPredicate, + 22, + 16, + 39, + 0, // Skip to: 25344 + /* 15344 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 9, + 39, + 0, // Skip to: 25344 + /* 15351 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 2, + 39, + 0, // Skip to: 25344 + /* 15358 */ MCD_OPC_Decode, + 175, + 7, + 183, + 1, // Opcode: MVE_VABAVs8 + /* 15363 */ MCD_OPC_FilterValue, + 15, + 248, + 38, + 0, // Skip to: 25344 + /* 15368 */ MCD_OPC_CheckPredicate, + 22, + 243, + 38, + 0, // Skip to: 25344 + /* 15373 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 236, + 38, + 0, // Skip to: 25344 + /* 15380 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 229, + 38, + 0, // Skip to: 25344 + /* 15387 */ MCD_OPC_Decode, + 178, + 7, + 183, + 1, // Opcode: MVE_VABAVu8 + /* 15392 */ MCD_OPC_FilterValue, + 1, + 61, + 0, + 0, // Skip to: 15458 + /* 15397 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15400 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15429 + /* 15405 */ MCD_OPC_CheckPredicate, + 22, + 206, + 38, + 0, // Skip to: 25344 + /* 15410 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 199, + 38, + 0, // Skip to: 25344 + /* 15417 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 192, + 38, + 0, // Skip to: 25344 + /* 15424 */ MCD_OPC_Decode, + 173, + 7, + 183, + 1, // Opcode: MVE_VABAVs16 + /* 15429 */ MCD_OPC_FilterValue, + 15, + 182, + 38, + 0, // Skip to: 25344 + /* 15434 */ MCD_OPC_CheckPredicate, + 22, + 177, + 38, + 0, // Skip to: 25344 + /* 15439 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 170, + 38, + 0, // Skip to: 25344 + /* 15446 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 163, + 38, + 0, // Skip to: 25344 + /* 15453 */ MCD_OPC_Decode, + 176, + 7, + 183, + 1, // Opcode: MVE_VABAVu16 + /* 15458 */ MCD_OPC_FilterValue, + 2, + 153, + 38, + 0, // Skip to: 25344 + /* 15463 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15466 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15495 + /* 15471 */ MCD_OPC_CheckPredicate, + 22, + 140, + 38, + 0, // Skip to: 25344 + /* 15476 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 133, + 38, + 0, // Skip to: 25344 + /* 15483 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 126, + 38, + 0, // Skip to: 25344 + /* 15490 */ MCD_OPC_Decode, + 174, + 7, + 183, + 1, // Opcode: MVE_VABAVs32 + /* 15495 */ MCD_OPC_FilterValue, + 15, + 116, + 38, + 0, // Skip to: 25344 + /* 15500 */ MCD_OPC_CheckPredicate, + 22, + 111, + 38, + 0, // Skip to: 25344 + /* 15505 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 104, + 38, + 0, // Skip to: 25344 + /* 15512 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 97, + 38, + 0, // Skip to: 25344 + /* 15519 */ MCD_OPC_Decode, + 177, + 7, + 183, + 1, // Opcode: MVE_VABAVu32 + /* 15524 */ MCD_OPC_FilterValue, + 1, + 87, + 38, + 0, // Skip to: 25344 + /* 15529 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 15532 */ MCD_OPC_FilterValue, + 0, + 219, + 3, + 0, // Skip to: 16524 + /* 15537 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 15540 */ MCD_OPC_FilterValue, + 0, + 27, + 1, + 0, // Skip to: 15828 + /* 15545 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 15548 */ MCD_OPC_FilterValue, + 0, + 135, + 0, + 0, // Skip to: 15688 + /* 15553 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 15556 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 15622 + /* 15561 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15564 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15593 + /* 15569 */ MCD_OPC_CheckPredicate, + 22, + 42, + 38, + 0, // Skip to: 25344 + /* 15574 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 35, + 38, + 0, // Skip to: 25344 + /* 15581 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 28, + 38, + 0, // Skip to: 25344 + /* 15588 */ MCD_OPC_Decode, + 132, + 12, + 184, + 1, // Opcode: MVE_VQSHRNbhs16 + /* 15593 */ MCD_OPC_FilterValue, + 15, + 18, + 38, + 0, // Skip to: 25344 + /* 15598 */ MCD_OPC_CheckPredicate, + 22, + 13, + 38, + 0, // Skip to: 25344 + /* 15603 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 6, + 38, + 0, // Skip to: 25344 + /* 15610 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 255, + 37, + 0, // Skip to: 25344 + /* 15617 */ MCD_OPC_Decode, + 134, + 12, + 184, + 1, // Opcode: MVE_VQSHRNbhu16 + /* 15622 */ MCD_OPC_FilterValue, + 1, + 245, + 37, + 0, // Skip to: 25344 + /* 15627 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15630 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15659 + /* 15635 */ MCD_OPC_CheckPredicate, + 22, + 232, + 37, + 0, // Skip to: 25344 + /* 15640 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 225, + 37, + 0, // Skip to: 25344 + /* 15647 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 218, + 37, + 0, // Skip to: 25344 + /* 15654 */ MCD_OPC_Decode, + 136, + 12, + 184, + 1, // Opcode: MVE_VQSHRNths16 + /* 15659 */ MCD_OPC_FilterValue, + 15, + 208, + 37, + 0, // Skip to: 25344 + /* 15664 */ MCD_OPC_CheckPredicate, + 22, + 203, + 37, + 0, // Skip to: 25344 + /* 15669 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 196, + 37, + 0, // Skip to: 25344 + /* 15676 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 189, + 37, + 0, // Skip to: 25344 + /* 15683 */ MCD_OPC_Decode, + 138, + 12, + 184, + 1, // Opcode: MVE_VQSHRNthu16 + /* 15688 */ MCD_OPC_FilterValue, + 1, + 179, + 37, + 0, // Skip to: 25344 + /* 15693 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 15696 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 15762 + /* 15701 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15704 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15733 + /* 15709 */ MCD_OPC_CheckPredicate, + 22, + 158, + 37, + 0, // Skip to: 25344 + /* 15714 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 151, + 37, + 0, // Skip to: 25344 + /* 15721 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 144, + 37, + 0, // Skip to: 25344 + /* 15728 */ MCD_OPC_Decode, + 227, + 11, + 184, + 1, // Opcode: MVE_VQRSHRNbhs16 + /* 15733 */ MCD_OPC_FilterValue, + 15, + 134, + 37, + 0, // Skip to: 25344 + /* 15738 */ MCD_OPC_CheckPredicate, + 22, + 129, + 37, + 0, // Skip to: 25344 + /* 15743 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 122, + 37, + 0, // Skip to: 25344 + /* 15750 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 115, + 37, + 0, // Skip to: 25344 + /* 15757 */ MCD_OPC_Decode, + 229, + 11, + 184, + 1, // Opcode: MVE_VQRSHRNbhu16 + /* 15762 */ MCD_OPC_FilterValue, + 1, + 105, + 37, + 0, // Skip to: 25344 + /* 15767 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15770 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15799 + /* 15775 */ MCD_OPC_CheckPredicate, + 22, + 92, + 37, + 0, // Skip to: 25344 + /* 15780 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 85, + 37, + 0, // Skip to: 25344 + /* 15787 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 78, + 37, + 0, // Skip to: 25344 + /* 15794 */ MCD_OPC_Decode, + 231, + 11, + 184, + 1, // Opcode: MVE_VQRSHRNths16 + /* 15799 */ MCD_OPC_FilterValue, + 15, + 68, + 37, + 0, // Skip to: 25344 + /* 15804 */ MCD_OPC_CheckPredicate, + 22, + 63, + 37, + 0, // Skip to: 25344 + /* 15809 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 56, + 37, + 0, // Skip to: 25344 + /* 15816 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 49, + 37, + 0, // Skip to: 25344 + /* 15823 */ MCD_OPC_Decode, + 233, + 11, + 184, + 1, // Opcode: MVE_VQRSHRNthu16 + /* 15828 */ MCD_OPC_FilterValue, + 1, + 227, + 0, + 0, // Skip to: 16060 + /* 15833 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 15836 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 15948 + /* 15841 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 15844 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 15896 + /* 15849 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15852 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 15874 + /* 15857 */ MCD_OPC_CheckPredicate, + 22, + 10, + 37, + 0, // Skip to: 25344 + /* 15862 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 3, + 37, + 0, // Skip to: 25344 + /* 15869 */ MCD_OPC_Decode, + 133, + 12, + 185, + 1, // Opcode: MVE_VQSHRNbhs32 + /* 15874 */ MCD_OPC_FilterValue, + 15, + 249, + 36, + 0, // Skip to: 25344 + /* 15879 */ MCD_OPC_CheckPredicate, + 22, + 244, + 36, + 0, // Skip to: 25344 + /* 15884 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 237, + 36, + 0, // Skip to: 25344 + /* 15891 */ MCD_OPC_Decode, + 135, + 12, + 185, + 1, // Opcode: MVE_VQSHRNbhu32 + /* 15896 */ MCD_OPC_FilterValue, + 1, + 227, + 36, + 0, // Skip to: 25344 + /* 15901 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15904 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 15926 + /* 15909 */ MCD_OPC_CheckPredicate, + 22, + 214, + 36, + 0, // Skip to: 25344 + /* 15914 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 207, + 36, + 0, // Skip to: 25344 + /* 15921 */ MCD_OPC_Decode, + 137, + 12, + 185, + 1, // Opcode: MVE_VQSHRNths32 + /* 15926 */ MCD_OPC_FilterValue, + 15, + 197, + 36, + 0, // Skip to: 25344 + /* 15931 */ MCD_OPC_CheckPredicate, + 22, + 192, + 36, + 0, // Skip to: 25344 + /* 15936 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 185, + 36, + 0, // Skip to: 25344 + /* 15943 */ MCD_OPC_Decode, + 139, + 12, + 185, + 1, // Opcode: MVE_VQSHRNthu32 + /* 15948 */ MCD_OPC_FilterValue, + 1, + 175, + 36, + 0, // Skip to: 25344 + /* 15953 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 15956 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 16008 + /* 15961 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15964 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 15986 + /* 15969 */ MCD_OPC_CheckPredicate, + 22, + 154, + 36, + 0, // Skip to: 25344 + /* 15974 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 147, + 36, + 0, // Skip to: 25344 + /* 15981 */ MCD_OPC_Decode, + 228, + 11, + 185, + 1, // Opcode: MVE_VQRSHRNbhs32 + /* 15986 */ MCD_OPC_FilterValue, + 15, + 137, + 36, + 0, // Skip to: 25344 + /* 15991 */ MCD_OPC_CheckPredicate, + 22, + 132, + 36, + 0, // Skip to: 25344 + /* 15996 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 125, + 36, + 0, // Skip to: 25344 + /* 16003 */ MCD_OPC_Decode, + 230, + 11, + 185, + 1, // Opcode: MVE_VQRSHRNbhu32 + /* 16008 */ MCD_OPC_FilterValue, + 1, + 115, + 36, + 0, // Skip to: 25344 + /* 16013 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16016 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 16038 + /* 16021 */ MCD_OPC_CheckPredicate, + 22, + 102, + 36, + 0, // Skip to: 25344 + /* 16026 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 95, + 36, + 0, // Skip to: 25344 + /* 16033 */ MCD_OPC_Decode, + 232, + 11, + 185, + 1, // Opcode: MVE_VQRSHRNths32 + /* 16038 */ MCD_OPC_FilterValue, + 15, + 85, + 36, + 0, // Skip to: 25344 + /* 16043 */ MCD_OPC_CheckPredicate, + 22, + 80, + 36, + 0, // Skip to: 25344 + /* 16048 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 73, + 36, + 0, // Skip to: 25344 + /* 16055 */ MCD_OPC_Decode, + 234, + 11, + 185, + 1, // Opcode: MVE_VQRSHRNthu32 + /* 16060 */ MCD_OPC_FilterValue, + 2, + 243, + 0, + 0, // Skip to: 16308 + /* 16065 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 16068 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 16188 + /* 16073 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16076 */ MCD_OPC_FilterValue, + 14, + 51, + 0, + 0, // Skip to: 16132 + /* 16081 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16084 */ MCD_OPC_FilterValue, + 0, + 39, + 36, + 0, // Skip to: 25344 + /* 16089 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16092 */ MCD_OPC_FilterValue, + 0, + 31, + 36, + 0, // Skip to: 25344 + /* 16097 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 16100 */ MCD_OPC_FilterValue, + 1, + 23, + 36, + 0, // Skip to: 25344 + /* 16105 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16122 + /* 16110 */ MCD_OPC_CheckField, + 16, + 3, + 0, + 5, + 0, + 0, // Skip to: 16122 + /* 16117 */ MCD_OPC_Decode, + 163, + 10, + 147, + 1, // Opcode: MVE_VMOVLs8bh + /* 16122 */ MCD_OPC_CheckPredicate, + 22, + 1, + 36, + 0, // Skip to: 25344 + /* 16127 */ MCD_OPC_Decode, + 223, + 12, + 186, + 1, // Opcode: MVE_VSHLL_imms8bh + /* 16132 */ MCD_OPC_FilterValue, + 15, + 247, + 35, + 0, // Skip to: 25344 + /* 16137 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16140 */ MCD_OPC_FilterValue, + 0, + 239, + 35, + 0, // Skip to: 25344 + /* 16145 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16148 */ MCD_OPC_FilterValue, + 0, + 231, + 35, + 0, // Skip to: 25344 + /* 16153 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 16156 */ MCD_OPC_FilterValue, + 1, + 223, + 35, + 0, // Skip to: 25344 + /* 16161 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16178 + /* 16166 */ MCD_OPC_CheckField, + 16, + 3, + 0, + 5, + 0, + 0, // Skip to: 16178 + /* 16173 */ MCD_OPC_Decode, + 167, + 10, + 147, + 1, // Opcode: MVE_VMOVLu8bh + /* 16178 */ MCD_OPC_CheckPredicate, + 22, + 201, + 35, + 0, // Skip to: 25344 + /* 16183 */ MCD_OPC_Decode, + 227, + 12, + 186, + 1, // Opcode: MVE_VSHLL_immu8bh + /* 16188 */ MCD_OPC_FilterValue, + 1, + 191, + 35, + 0, // Skip to: 25344 + /* 16193 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16196 */ MCD_OPC_FilterValue, + 14, + 51, + 0, + 0, // Skip to: 16252 + /* 16201 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16204 */ MCD_OPC_FilterValue, + 0, + 175, + 35, + 0, // Skip to: 25344 + /* 16209 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16212 */ MCD_OPC_FilterValue, + 0, + 167, + 35, + 0, // Skip to: 25344 + /* 16217 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 16220 */ MCD_OPC_FilterValue, + 1, + 159, + 35, + 0, // Skip to: 25344 + /* 16225 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16242 + /* 16230 */ MCD_OPC_CheckField, + 16, + 3, + 0, + 5, + 0, + 0, // Skip to: 16242 + /* 16237 */ MCD_OPC_Decode, + 164, + 10, + 147, + 1, // Opcode: MVE_VMOVLs8th + /* 16242 */ MCD_OPC_CheckPredicate, + 22, + 137, + 35, + 0, // Skip to: 25344 + /* 16247 */ MCD_OPC_Decode, + 224, + 12, + 186, + 1, // Opcode: MVE_VSHLL_imms8th + /* 16252 */ MCD_OPC_FilterValue, + 15, + 127, + 35, + 0, // Skip to: 25344 + /* 16257 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16260 */ MCD_OPC_FilterValue, + 0, + 119, + 35, + 0, // Skip to: 25344 + /* 16265 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16268 */ MCD_OPC_FilterValue, + 0, + 111, + 35, + 0, // Skip to: 25344 + /* 16273 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 16276 */ MCD_OPC_FilterValue, + 1, + 103, + 35, + 0, // Skip to: 25344 + /* 16281 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16298 + /* 16286 */ MCD_OPC_CheckField, + 16, + 3, + 0, + 5, + 0, + 0, // Skip to: 16298 + /* 16293 */ MCD_OPC_Decode, + 168, + 10, + 147, + 1, // Opcode: MVE_VMOVLu8th + /* 16298 */ MCD_OPC_CheckPredicate, + 22, + 81, + 35, + 0, // Skip to: 25344 + /* 16303 */ MCD_OPC_Decode, + 228, + 12, + 186, + 1, // Opcode: MVE_VSHLL_immu8th + /* 16308 */ MCD_OPC_FilterValue, + 3, + 71, + 35, + 0, // Skip to: 25344 + /* 16313 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 16316 */ MCD_OPC_FilterValue, + 0, + 99, + 0, + 0, // Skip to: 16420 + /* 16321 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16324 */ MCD_OPC_FilterValue, + 14, + 43, + 0, + 0, // Skip to: 16372 + /* 16329 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16332 */ MCD_OPC_FilterValue, + 0, + 47, + 35, + 0, // Skip to: 25344 + /* 16337 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16340 */ MCD_OPC_FilterValue, + 0, + 39, + 35, + 0, // Skip to: 25344 + /* 16345 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16362 + /* 16350 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 16362 + /* 16357 */ MCD_OPC_Decode, + 161, + 10, + 147, + 1, // Opcode: MVE_VMOVLs16bh + /* 16362 */ MCD_OPC_CheckPredicate, + 22, + 17, + 35, + 0, // Skip to: 25344 + /* 16367 */ MCD_OPC_Decode, + 221, + 12, + 187, + 1, // Opcode: MVE_VSHLL_imms16bh + /* 16372 */ MCD_OPC_FilterValue, + 15, + 7, + 35, + 0, // Skip to: 25344 + /* 16377 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16380 */ MCD_OPC_FilterValue, + 0, + 255, + 34, + 0, // Skip to: 25344 + /* 16385 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16388 */ MCD_OPC_FilterValue, + 0, + 247, + 34, + 0, // Skip to: 25344 + /* 16393 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16410 + /* 16398 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 16410 + /* 16405 */ MCD_OPC_Decode, + 165, + 10, + 147, + 1, // Opcode: MVE_VMOVLu16bh + /* 16410 */ MCD_OPC_CheckPredicate, + 22, + 225, + 34, + 0, // Skip to: 25344 + /* 16415 */ MCD_OPC_Decode, + 225, + 12, + 187, + 1, // Opcode: MVE_VSHLL_immu16bh + /* 16420 */ MCD_OPC_FilterValue, + 1, + 215, + 34, + 0, // Skip to: 25344 + /* 16425 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16428 */ MCD_OPC_FilterValue, + 14, + 43, + 0, + 0, // Skip to: 16476 + /* 16433 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16436 */ MCD_OPC_FilterValue, + 0, + 199, + 34, + 0, // Skip to: 25344 + /* 16441 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16444 */ MCD_OPC_FilterValue, + 0, + 191, + 34, + 0, // Skip to: 25344 + /* 16449 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16466 + /* 16454 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 16466 + /* 16461 */ MCD_OPC_Decode, + 162, + 10, + 147, + 1, // Opcode: MVE_VMOVLs16th + /* 16466 */ MCD_OPC_CheckPredicate, + 22, + 169, + 34, + 0, // Skip to: 25344 + /* 16471 */ MCD_OPC_Decode, + 222, + 12, + 187, + 1, // Opcode: MVE_VSHLL_imms16th + /* 16476 */ MCD_OPC_FilterValue, + 15, + 159, + 34, + 0, // Skip to: 25344 + /* 16481 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16484 */ MCD_OPC_FilterValue, + 0, + 151, + 34, + 0, // Skip to: 25344 + /* 16489 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16492 */ MCD_OPC_FilterValue, + 0, + 143, + 34, + 0, // Skip to: 25344 + /* 16497 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16514 + /* 16502 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 16514 + /* 16509 */ MCD_OPC_Decode, + 166, + 10, + 147, + 1, // Opcode: MVE_VMOVLu16th + /* 16514 */ MCD_OPC_CheckPredicate, + 22, + 121, + 34, + 0, // Skip to: 25344 + /* 16519 */ MCD_OPC_Decode, + 226, + 12, + 187, + 1, // Opcode: MVE_VSHLL_immu16th + /* 16524 */ MCD_OPC_FilterValue, + 1, + 111, + 34, + 0, // Skip to: 25344 + /* 16529 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 16532 */ MCD_OPC_FilterValue, + 0, + 36, + 1, + 0, // Skip to: 16829 + /* 16537 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 16540 */ MCD_OPC_FilterValue, + 0, + 255, + 0, + 0, // Skip to: 16800 + /* 16545 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16548 */ MCD_OPC_FilterValue, + 0, + 121, + 0, + 0, // Skip to: 16674 + /* 16553 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 16556 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 16622 + /* 16561 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16564 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 16593 + /* 16569 */ MCD_OPC_CheckPredicate, + 22, + 66, + 34, + 0, // Skip to: 25344 + /* 16574 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 59, + 34, + 0, // Skip to: 25344 + /* 16581 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 52, + 34, + 0, // Skip to: 25344 + /* 16588 */ MCD_OPC_Decode, + 140, + 12, + 184, + 1, // Opcode: MVE_VQSHRUNs16bh + /* 16593 */ MCD_OPC_FilterValue, + 15, + 42, + 34, + 0, // Skip to: 25344 + /* 16598 */ MCD_OPC_CheckPredicate, + 22, + 37, + 34, + 0, // Skip to: 25344 + /* 16603 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 30, + 34, + 0, // Skip to: 25344 + /* 16610 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 23, + 34, + 0, // Skip to: 25344 + /* 16617 */ MCD_OPC_Decode, + 235, + 11, + 184, + 1, // Opcode: MVE_VQRSHRUNs16bh + /* 16622 */ MCD_OPC_FilterValue, + 1, + 13, + 34, + 0, // Skip to: 25344 + /* 16627 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16630 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 16652 + /* 16635 */ MCD_OPC_CheckPredicate, + 22, + 0, + 34, + 0, // Skip to: 25344 + /* 16640 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 249, + 33, + 0, // Skip to: 25344 + /* 16647 */ MCD_OPC_Decode, + 142, + 12, + 185, + 1, // Opcode: MVE_VQSHRUNs32bh + /* 16652 */ MCD_OPC_FilterValue, + 15, + 239, + 33, + 0, // Skip to: 25344 + /* 16657 */ MCD_OPC_CheckPredicate, + 22, + 234, + 33, + 0, // Skip to: 25344 + /* 16662 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 227, + 33, + 0, // Skip to: 25344 + /* 16669 */ MCD_OPC_Decode, + 237, + 11, + 185, + 1, // Opcode: MVE_VQRSHRUNs32bh + /* 16674 */ MCD_OPC_FilterValue, + 1, + 217, + 33, + 0, // Skip to: 25344 + /* 16679 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 16682 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 16748 + /* 16687 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16690 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 16719 + /* 16695 */ MCD_OPC_CheckPredicate, + 22, + 196, + 33, + 0, // Skip to: 25344 + /* 16700 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 189, + 33, + 0, // Skip to: 25344 + /* 16707 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 182, + 33, + 0, // Skip to: 25344 + /* 16714 */ MCD_OPC_Decode, + 252, + 12, + 184, + 1, // Opcode: MVE_VSHRNi16bh + /* 16719 */ MCD_OPC_FilterValue, + 15, + 172, + 33, + 0, // Skip to: 25344 + /* 16724 */ MCD_OPC_CheckPredicate, + 22, + 167, + 33, + 0, // Skip to: 25344 + /* 16729 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 160, + 33, + 0, // Skip to: 25344 + /* 16736 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 153, + 33, + 0, // Skip to: 25344 + /* 16743 */ MCD_OPC_Decode, + 208, + 12, + 184, + 1, // Opcode: MVE_VRSHRNi16bh + /* 16748 */ MCD_OPC_FilterValue, + 1, + 143, + 33, + 0, // Skip to: 25344 + /* 16753 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16756 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 16778 + /* 16761 */ MCD_OPC_CheckPredicate, + 22, + 130, + 33, + 0, // Skip to: 25344 + /* 16766 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 123, + 33, + 0, // Skip to: 25344 + /* 16773 */ MCD_OPC_Decode, + 254, + 12, + 185, + 1, // Opcode: MVE_VSHRNi32bh + /* 16778 */ MCD_OPC_FilterValue, + 15, + 113, + 33, + 0, // Skip to: 25344 + /* 16783 */ MCD_OPC_CheckPredicate, + 22, + 108, + 33, + 0, // Skip to: 25344 + /* 16788 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 101, + 33, + 0, // Skip to: 25344 + /* 16795 */ MCD_OPC_Decode, + 210, + 12, + 185, + 1, // Opcode: MVE_VRSHRNi32bh + /* 16800 */ MCD_OPC_FilterValue, + 1, + 91, + 33, + 0, // Skip to: 25344 + /* 16805 */ MCD_OPC_CheckPredicate, + 22, + 86, + 33, + 0, // Skip to: 25344 + /* 16810 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 79, + 33, + 0, // Skip to: 25344 + /* 16817 */ MCD_OPC_CheckField, + 4, + 2, + 0, + 72, + 33, + 0, // Skip to: 25344 + /* 16824 */ MCD_OPC_Decode, + 220, + 12, + 188, + 1, // Opcode: MVE_VSHLC + /* 16829 */ MCD_OPC_FilterValue, + 1, + 62, + 33, + 0, // Skip to: 25344 + /* 16834 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16837 */ MCD_OPC_FilterValue, + 0, + 121, + 0, + 0, // Skip to: 16963 + /* 16842 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16845 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 16911 + /* 16850 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16853 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 16882 + /* 16858 */ MCD_OPC_CheckPredicate, + 22, + 33, + 33, + 0, // Skip to: 25344 + /* 16863 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 26, + 33, + 0, // Skip to: 25344 + /* 16870 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 19, + 33, + 0, // Skip to: 25344 + /* 16877 */ MCD_OPC_Decode, + 141, + 12, + 184, + 1, // Opcode: MVE_VQSHRUNs16th + /* 16882 */ MCD_OPC_FilterValue, + 15, + 9, + 33, + 0, // Skip to: 25344 + /* 16887 */ MCD_OPC_CheckPredicate, + 22, + 4, + 33, + 0, // Skip to: 25344 + /* 16892 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 253, + 32, + 0, // Skip to: 25344 + /* 16899 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 246, + 32, + 0, // Skip to: 25344 + /* 16906 */ MCD_OPC_Decode, + 236, + 11, + 184, + 1, // Opcode: MVE_VQRSHRUNs16th + /* 16911 */ MCD_OPC_FilterValue, + 1, + 236, + 32, + 0, // Skip to: 25344 + /* 16916 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16919 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 16941 + /* 16924 */ MCD_OPC_CheckPredicate, + 22, + 223, + 32, + 0, // Skip to: 25344 + /* 16929 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 216, + 32, + 0, // Skip to: 25344 + /* 16936 */ MCD_OPC_Decode, + 143, + 12, + 185, + 1, // Opcode: MVE_VQSHRUNs32th + /* 16941 */ MCD_OPC_FilterValue, + 15, + 206, + 32, + 0, // Skip to: 25344 + /* 16946 */ MCD_OPC_CheckPredicate, + 22, + 201, + 32, + 0, // Skip to: 25344 + /* 16951 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 194, + 32, + 0, // Skip to: 25344 + /* 16958 */ MCD_OPC_Decode, + 238, + 11, + 185, + 1, // Opcode: MVE_VQRSHRUNs32th + /* 16963 */ MCD_OPC_FilterValue, + 1, + 184, + 32, + 0, // Skip to: 25344 + /* 16968 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16971 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 17037 + /* 16976 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16979 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 17008 + /* 16984 */ MCD_OPC_CheckPredicate, + 22, + 163, + 32, + 0, // Skip to: 25344 + /* 16989 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 156, + 32, + 0, // Skip to: 25344 + /* 16996 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 149, + 32, + 0, // Skip to: 25344 + /* 17003 */ MCD_OPC_Decode, + 253, + 12, + 184, + 1, // Opcode: MVE_VSHRNi16th + /* 17008 */ MCD_OPC_FilterValue, + 15, + 139, + 32, + 0, // Skip to: 25344 + /* 17013 */ MCD_OPC_CheckPredicate, + 22, + 134, + 32, + 0, // Skip to: 25344 + /* 17018 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 127, + 32, + 0, // Skip to: 25344 + /* 17025 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 120, + 32, + 0, // Skip to: 25344 + /* 17032 */ MCD_OPC_Decode, + 209, + 12, + 184, + 1, // Opcode: MVE_VRSHRNi16th + /* 17037 */ MCD_OPC_FilterValue, + 1, + 110, + 32, + 0, // Skip to: 25344 + /* 17042 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17045 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 17067 + /* 17050 */ MCD_OPC_CheckPredicate, + 22, + 97, + 32, + 0, // Skip to: 25344 + /* 17055 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 90, + 32, + 0, // Skip to: 25344 + /* 17062 */ MCD_OPC_Decode, + 255, + 12, + 185, + 1, // Opcode: MVE_VSHRNi32th + /* 17067 */ MCD_OPC_FilterValue, + 15, + 80, + 32, + 0, // Skip to: 25344 + /* 17072 */ MCD_OPC_CheckPredicate, + 22, + 75, + 32, + 0, // Skip to: 25344 + /* 17077 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 68, + 32, + 0, // Skip to: 25344 + /* 17084 */ MCD_OPC_Decode, + 211, + 12, + 185, + 1, // Opcode: MVE_VRSHRNi32th + /* 17089 */ MCD_OPC_FilterValue, + 2, + 15, + 19, + 0, // Skip to: 21973 + /* 17094 */ MCD_OPC_ExtractField, + 8, + 5, // Inst{12-8} ... + /* 17097 */ MCD_OPC_FilterValue, + 0, + 251, + 1, + 0, // Skip to: 17609 + /* 17102 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 17105 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 17273 + /* 17110 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17113 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 17193 + /* 17118 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17121 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17157 + /* 17126 */ MCD_OPC_CheckPredicate, + 22, + 21, + 32, + 0, // Skip to: 25344 + /* 17131 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 14, + 32, + 0, // Skip to: 25344 + /* 17138 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 7, + 32, + 0, // Skip to: 25344 + /* 17145 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 0, + 32, + 0, // Skip to: 25344 + /* 17152 */ MCD_OPC_Decode, + 202, + 8, + 143, + 1, // Opcode: MVE_VHADDs8 + /* 17157 */ MCD_OPC_FilterValue, + 15, + 246, + 31, + 0, // Skip to: 25344 + /* 17162 */ MCD_OPC_CheckPredicate, + 22, + 241, + 31, + 0, // Skip to: 25344 + /* 17167 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 234, + 31, + 0, // Skip to: 25344 + /* 17174 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 227, + 31, + 0, // Skip to: 25344 + /* 17181 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 220, + 31, + 0, // Skip to: 25344 + /* 17188 */ MCD_OPC_Decode, + 205, + 8, + 143, + 1, // Opcode: MVE_VHADDu8 + /* 17193 */ MCD_OPC_FilterValue, + 1, + 210, + 31, + 0, // Skip to: 25344 + /* 17198 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17201 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17237 + /* 17206 */ MCD_OPC_CheckPredicate, + 22, + 197, + 31, + 0, // Skip to: 25344 + /* 17211 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 190, + 31, + 0, // Skip to: 25344 + /* 17218 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 183, + 31, + 0, // Skip to: 25344 + /* 17225 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 176, + 31, + 0, // Skip to: 25344 + /* 17232 */ MCD_OPC_Decode, + 140, + 11, + 143, + 1, // Opcode: MVE_VQADDs8 + /* 17237 */ MCD_OPC_FilterValue, + 15, + 166, + 31, + 0, // Skip to: 25344 + /* 17242 */ MCD_OPC_CheckPredicate, + 22, + 161, + 31, + 0, // Skip to: 25344 + /* 17247 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 154, + 31, + 0, // Skip to: 25344 + /* 17254 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 147, + 31, + 0, // Skip to: 25344 + /* 17261 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 140, + 31, + 0, // Skip to: 25344 + /* 17268 */ MCD_OPC_Decode, + 143, + 11, + 143, + 1, // Opcode: MVE_VQADDu8 + /* 17273 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 17441 + /* 17278 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17281 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 17361 + /* 17286 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17289 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17325 + /* 17294 */ MCD_OPC_CheckPredicate, + 22, + 109, + 31, + 0, // Skip to: 25344 + /* 17299 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 102, + 31, + 0, // Skip to: 25344 + /* 17306 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 95, + 31, + 0, // Skip to: 25344 + /* 17313 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 88, + 31, + 0, // Skip to: 25344 + /* 17320 */ MCD_OPC_Decode, + 200, + 8, + 143, + 1, // Opcode: MVE_VHADDs16 + /* 17325 */ MCD_OPC_FilterValue, + 15, + 78, + 31, + 0, // Skip to: 25344 + /* 17330 */ MCD_OPC_CheckPredicate, + 22, + 73, + 31, + 0, // Skip to: 25344 + /* 17335 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 66, + 31, + 0, // Skip to: 25344 + /* 17342 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 59, + 31, + 0, // Skip to: 25344 + /* 17349 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 52, + 31, + 0, // Skip to: 25344 + /* 17356 */ MCD_OPC_Decode, + 203, + 8, + 143, + 1, // Opcode: MVE_VHADDu16 + /* 17361 */ MCD_OPC_FilterValue, + 1, + 42, + 31, + 0, // Skip to: 25344 + /* 17366 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17369 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17405 + /* 17374 */ MCD_OPC_CheckPredicate, + 22, + 29, + 31, + 0, // Skip to: 25344 + /* 17379 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 22, + 31, + 0, // Skip to: 25344 + /* 17386 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 15, + 31, + 0, // Skip to: 25344 + /* 17393 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 8, + 31, + 0, // Skip to: 25344 + /* 17400 */ MCD_OPC_Decode, + 138, + 11, + 143, + 1, // Opcode: MVE_VQADDs16 + /* 17405 */ MCD_OPC_FilterValue, + 15, + 254, + 30, + 0, // Skip to: 25344 + /* 17410 */ MCD_OPC_CheckPredicate, + 22, + 249, + 30, + 0, // Skip to: 25344 + /* 17415 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 242, + 30, + 0, // Skip to: 25344 + /* 17422 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 235, + 30, + 0, // Skip to: 25344 + /* 17429 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 228, + 30, + 0, // Skip to: 25344 + /* 17436 */ MCD_OPC_Decode, + 141, + 11, + 143, + 1, // Opcode: MVE_VQADDu16 + /* 17441 */ MCD_OPC_FilterValue, + 2, + 218, + 30, + 0, // Skip to: 25344 + /* 17446 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17449 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 17529 + /* 17454 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17457 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17493 + /* 17462 */ MCD_OPC_CheckPredicate, + 22, + 197, + 30, + 0, // Skip to: 25344 + /* 17467 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 190, + 30, + 0, // Skip to: 25344 + /* 17474 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 183, + 30, + 0, // Skip to: 25344 + /* 17481 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 176, + 30, + 0, // Skip to: 25344 + /* 17488 */ MCD_OPC_Decode, + 201, + 8, + 143, + 1, // Opcode: MVE_VHADDs32 + /* 17493 */ MCD_OPC_FilterValue, + 15, + 166, + 30, + 0, // Skip to: 25344 + /* 17498 */ MCD_OPC_CheckPredicate, + 22, + 161, + 30, + 0, // Skip to: 25344 + /* 17503 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 154, + 30, + 0, // Skip to: 25344 + /* 17510 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 147, + 30, + 0, // Skip to: 25344 + /* 17517 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 140, + 30, + 0, // Skip to: 25344 + /* 17524 */ MCD_OPC_Decode, + 204, + 8, + 143, + 1, // Opcode: MVE_VHADDu32 + /* 17529 */ MCD_OPC_FilterValue, + 1, + 130, + 30, + 0, // Skip to: 25344 + /* 17534 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17537 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17573 + /* 17542 */ MCD_OPC_CheckPredicate, + 22, + 117, + 30, + 0, // Skip to: 25344 + /* 17547 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 110, + 30, + 0, // Skip to: 25344 + /* 17554 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 103, + 30, + 0, // Skip to: 25344 + /* 17561 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 96, + 30, + 0, // Skip to: 25344 + /* 17568 */ MCD_OPC_Decode, + 139, + 11, + 143, + 1, // Opcode: MVE_VQADDs32 + /* 17573 */ MCD_OPC_FilterValue, + 15, + 86, + 30, + 0, // Skip to: 25344 + /* 17578 */ MCD_OPC_CheckPredicate, + 22, + 81, + 30, + 0, // Skip to: 25344 + /* 17583 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 74, + 30, + 0, // Skip to: 25344 + /* 17590 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 67, + 30, + 0, // Skip to: 25344 + /* 17597 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 60, + 30, + 0, // Skip to: 25344 + /* 17604 */ MCD_OPC_Decode, + 142, + 11, + 143, + 1, // Opcode: MVE_VQADDu32 + /* 17609 */ MCD_OPC_FilterValue, + 1, + 227, + 1, + 0, // Skip to: 18097 + /* 17614 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 17617 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 17785 + /* 17622 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17625 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 17705 + /* 17630 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17633 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17669 + /* 17638 */ MCD_OPC_CheckPredicate, + 22, + 21, + 30, + 0, // Skip to: 25344 + /* 17643 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 14, + 30, + 0, // Skip to: 25344 + /* 17650 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 7, + 30, + 0, // Skip to: 25344 + /* 17657 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 0, + 30, + 0, // Skip to: 25344 + /* 17664 */ MCD_OPC_Decode, + 164, + 12, + 143, + 1, // Opcode: MVE_VRHADDs8 + /* 17669 */ MCD_OPC_FilterValue, + 15, + 246, + 29, + 0, // Skip to: 25344 + /* 17674 */ MCD_OPC_CheckPredicate, + 22, + 241, + 29, + 0, // Skip to: 25344 + /* 17679 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 234, + 29, + 0, // Skip to: 25344 + /* 17686 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 227, + 29, + 0, // Skip to: 25344 + /* 17693 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 220, + 29, + 0, // Skip to: 25344 + /* 17700 */ MCD_OPC_Decode, + 167, + 12, + 143, + 1, // Opcode: MVE_VRHADDu8 + /* 17705 */ MCD_OPC_FilterValue, + 1, + 210, + 29, + 0, // Skip to: 25344 + /* 17710 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17713 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17749 + /* 17718 */ MCD_OPC_CheckPredicate, + 22, + 197, + 29, + 0, // Skip to: 25344 + /* 17723 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 190, + 29, + 0, // Skip to: 25344 + /* 17730 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 183, + 29, + 0, // Skip to: 25344 + /* 17737 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 176, + 29, + 0, // Skip to: 25344 + /* 17744 */ MCD_OPC_Decode, + 220, + 7, + 143, + 1, // Opcode: MVE_VAND + /* 17749 */ MCD_OPC_FilterValue, + 15, + 166, + 29, + 0, // Skip to: 25344 + /* 17754 */ MCD_OPC_CheckPredicate, + 22, + 161, + 29, + 0, // Skip to: 25344 + /* 17759 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 154, + 29, + 0, // Skip to: 25344 + /* 17766 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 147, + 29, + 0, // Skip to: 25344 + /* 17773 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 140, + 29, + 0, // Skip to: 25344 + /* 17780 */ MCD_OPC_Decode, + 185, + 8, + 143, + 1, // Opcode: MVE_VEOR + /* 17785 */ MCD_OPC_FilterValue, + 1, + 126, + 0, + 0, // Skip to: 17916 + /* 17790 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17793 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 17873 + /* 17798 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17801 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17837 + /* 17806 */ MCD_OPC_CheckPredicate, + 22, + 109, + 29, + 0, // Skip to: 25344 + /* 17811 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 102, + 29, + 0, // Skip to: 25344 + /* 17818 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 95, + 29, + 0, // Skip to: 25344 + /* 17825 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 88, + 29, + 0, // Skip to: 25344 + /* 17832 */ MCD_OPC_Decode, + 162, + 12, + 143, + 1, // Opcode: MVE_VRHADDs16 + /* 17837 */ MCD_OPC_FilterValue, + 15, + 78, + 29, + 0, // Skip to: 25344 + /* 17842 */ MCD_OPC_CheckPredicate, + 22, + 73, + 29, + 0, // Skip to: 25344 + /* 17847 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 66, + 29, + 0, // Skip to: 25344 + /* 17854 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 59, + 29, + 0, // Skip to: 25344 + /* 17861 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 52, + 29, + 0, // Skip to: 25344 + /* 17868 */ MCD_OPC_Decode, + 165, + 12, + 143, + 1, // Opcode: MVE_VRHADDu16 + /* 17873 */ MCD_OPC_FilterValue, + 1, + 42, + 29, + 0, // Skip to: 25344 + /* 17878 */ MCD_OPC_CheckPredicate, + 22, + 37, + 29, + 0, // Skip to: 25344 + /* 17883 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 30, + 29, + 0, // Skip to: 25344 + /* 17890 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 23, + 29, + 0, // Skip to: 25344 + /* 17897 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 16, + 29, + 0, // Skip to: 25344 + /* 17904 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 9, + 29, + 0, // Skip to: 25344 + /* 17911 */ MCD_OPC_Decode, + 221, + 7, + 143, + 1, // Opcode: MVE_VBIC + /* 17916 */ MCD_OPC_FilterValue, + 2, + 126, + 0, + 0, // Skip to: 18047 + /* 17921 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17924 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 18004 + /* 17929 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17932 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17968 + /* 17937 */ MCD_OPC_CheckPredicate, + 22, + 234, + 28, + 0, // Skip to: 25344 + /* 17942 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 227, + 28, + 0, // Skip to: 25344 + /* 17949 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 220, + 28, + 0, // Skip to: 25344 + /* 17956 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 213, + 28, + 0, // Skip to: 25344 + /* 17963 */ MCD_OPC_Decode, + 163, + 12, + 143, + 1, // Opcode: MVE_VRHADDs32 + /* 17968 */ MCD_OPC_FilterValue, + 15, + 203, + 28, + 0, // Skip to: 25344 + /* 17973 */ MCD_OPC_CheckPredicate, + 22, + 198, + 28, + 0, // Skip to: 25344 + /* 17978 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 191, + 28, + 0, // Skip to: 25344 + /* 17985 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 184, + 28, + 0, // Skip to: 25344 + /* 17992 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 177, + 28, + 0, // Skip to: 25344 + /* 17999 */ MCD_OPC_Decode, + 166, + 12, + 143, + 1, // Opcode: MVE_VRHADDu32 + /* 18004 */ MCD_OPC_FilterValue, + 1, + 167, + 28, + 0, // Skip to: 25344 + /* 18009 */ MCD_OPC_CheckPredicate, + 22, + 162, + 28, + 0, // Skip to: 25344 + /* 18014 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 155, + 28, + 0, // Skip to: 25344 + /* 18021 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 148, + 28, + 0, // Skip to: 25344 + /* 18028 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 141, + 28, + 0, // Skip to: 25344 + /* 18035 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 134, + 28, + 0, // Skip to: 25344 + /* 18042 */ MCD_OPC_Decode, + 229, + 10, + 143, + 1, // Opcode: MVE_VORR + /* 18047 */ MCD_OPC_FilterValue, + 3, + 124, + 28, + 0, // Skip to: 25344 + /* 18052 */ MCD_OPC_CheckPredicate, + 22, + 119, + 28, + 0, // Skip to: 25344 + /* 18057 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 112, + 28, + 0, // Skip to: 25344 + /* 18064 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 105, + 28, + 0, // Skip to: 25344 + /* 18071 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 98, + 28, + 0, // Skip to: 25344 + /* 18078 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 91, + 28, + 0, // Skip to: 25344 + /* 18085 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 84, + 28, + 0, // Skip to: 25344 + /* 18092 */ MCD_OPC_Decode, + 228, + 10, + 143, + 1, // Opcode: MVE_VORN + /* 18097 */ MCD_OPC_FilterValue, + 2, + 251, + 1, + 0, // Skip to: 18609 + /* 18102 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 18105 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 18273 + /* 18110 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18113 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 18193 + /* 18118 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18121 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18157 + /* 18126 */ MCD_OPC_CheckPredicate, + 22, + 45, + 28, + 0, // Skip to: 25344 + /* 18131 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 38, + 28, + 0, // Skip to: 25344 + /* 18138 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 31, + 28, + 0, // Skip to: 25344 + /* 18145 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 24, + 28, + 0, // Skip to: 25344 + /* 18152 */ MCD_OPC_Decode, + 217, + 8, + 143, + 1, // Opcode: MVE_VHSUBs8 + /* 18157 */ MCD_OPC_FilterValue, + 15, + 14, + 28, + 0, // Skip to: 25344 + /* 18162 */ MCD_OPC_CheckPredicate, + 22, + 9, + 28, + 0, // Skip to: 25344 + /* 18167 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 2, + 28, + 0, // Skip to: 25344 + /* 18174 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 251, + 27, + 0, // Skip to: 25344 + /* 18181 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 244, + 27, + 0, // Skip to: 25344 + /* 18188 */ MCD_OPC_Decode, + 220, + 8, + 143, + 1, // Opcode: MVE_VHSUBu8 + /* 18193 */ MCD_OPC_FilterValue, + 1, + 234, + 27, + 0, // Skip to: 25344 + /* 18198 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18201 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18237 + /* 18206 */ MCD_OPC_CheckPredicate, + 22, + 221, + 27, + 0, // Skip to: 25344 + /* 18211 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 27, + 0, // Skip to: 25344 + /* 18218 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 27, + 0, // Skip to: 25344 + /* 18225 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 27, + 0, // Skip to: 25344 + /* 18232 */ MCD_OPC_Decode, + 152, + 12, + 143, + 1, // Opcode: MVE_VQSUBs8 + /* 18237 */ MCD_OPC_FilterValue, + 15, + 190, + 27, + 0, // Skip to: 25344 + /* 18242 */ MCD_OPC_CheckPredicate, + 22, + 185, + 27, + 0, // Skip to: 25344 + /* 18247 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 27, + 0, // Skip to: 25344 + /* 18254 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 27, + 0, // Skip to: 25344 + /* 18261 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 27, + 0, // Skip to: 25344 + /* 18268 */ MCD_OPC_Decode, + 155, + 12, + 143, + 1, // Opcode: MVE_VQSUBu8 + /* 18273 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 18441 + /* 18278 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18281 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 18361 + /* 18286 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18289 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18325 + /* 18294 */ MCD_OPC_CheckPredicate, + 22, + 133, + 27, + 0, // Skip to: 25344 + /* 18299 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 126, + 27, + 0, // Skip to: 25344 + /* 18306 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 119, + 27, + 0, // Skip to: 25344 + /* 18313 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 112, + 27, + 0, // Skip to: 25344 + /* 18320 */ MCD_OPC_Decode, + 215, + 8, + 143, + 1, // Opcode: MVE_VHSUBs16 + /* 18325 */ MCD_OPC_FilterValue, + 15, + 102, + 27, + 0, // Skip to: 25344 + /* 18330 */ MCD_OPC_CheckPredicate, + 22, + 97, + 27, + 0, // Skip to: 25344 + /* 18335 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 90, + 27, + 0, // Skip to: 25344 + /* 18342 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 83, + 27, + 0, // Skip to: 25344 + /* 18349 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 76, + 27, + 0, // Skip to: 25344 + /* 18356 */ MCD_OPC_Decode, + 218, + 8, + 143, + 1, // Opcode: MVE_VHSUBu16 + /* 18361 */ MCD_OPC_FilterValue, + 1, + 66, + 27, + 0, // Skip to: 25344 + /* 18366 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18369 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18405 + /* 18374 */ MCD_OPC_CheckPredicate, + 22, + 53, + 27, + 0, // Skip to: 25344 + /* 18379 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 46, + 27, + 0, // Skip to: 25344 + /* 18386 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 39, + 27, + 0, // Skip to: 25344 + /* 18393 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 32, + 27, + 0, // Skip to: 25344 + /* 18400 */ MCD_OPC_Decode, + 150, + 12, + 143, + 1, // Opcode: MVE_VQSUBs16 + /* 18405 */ MCD_OPC_FilterValue, + 15, + 22, + 27, + 0, // Skip to: 25344 + /* 18410 */ MCD_OPC_CheckPredicate, + 22, + 17, + 27, + 0, // Skip to: 25344 + /* 18415 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 10, + 27, + 0, // Skip to: 25344 + /* 18422 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 3, + 27, + 0, // Skip to: 25344 + /* 18429 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 252, + 26, + 0, // Skip to: 25344 + /* 18436 */ MCD_OPC_Decode, + 153, + 12, + 143, + 1, // Opcode: MVE_VQSUBu16 + /* 18441 */ MCD_OPC_FilterValue, + 2, + 242, + 26, + 0, // Skip to: 25344 + /* 18446 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18449 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 18529 + /* 18454 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18457 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18493 + /* 18462 */ MCD_OPC_CheckPredicate, + 22, + 221, + 26, + 0, // Skip to: 25344 + /* 18467 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 26, + 0, // Skip to: 25344 + /* 18474 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 26, + 0, // Skip to: 25344 + /* 18481 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 26, + 0, // Skip to: 25344 + /* 18488 */ MCD_OPC_Decode, + 216, + 8, + 143, + 1, // Opcode: MVE_VHSUBs32 + /* 18493 */ MCD_OPC_FilterValue, + 15, + 190, + 26, + 0, // Skip to: 25344 + /* 18498 */ MCD_OPC_CheckPredicate, + 22, + 185, + 26, + 0, // Skip to: 25344 + /* 18503 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 26, + 0, // Skip to: 25344 + /* 18510 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 26, + 0, // Skip to: 25344 + /* 18517 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 26, + 0, // Skip to: 25344 + /* 18524 */ MCD_OPC_Decode, + 219, + 8, + 143, + 1, // Opcode: MVE_VHSUBu32 + /* 18529 */ MCD_OPC_FilterValue, + 1, + 154, + 26, + 0, // Skip to: 25344 + /* 18534 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18537 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18573 + /* 18542 */ MCD_OPC_CheckPredicate, + 22, + 141, + 26, + 0, // Skip to: 25344 + /* 18547 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 134, + 26, + 0, // Skip to: 25344 + /* 18554 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 127, + 26, + 0, // Skip to: 25344 + /* 18561 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 120, + 26, + 0, // Skip to: 25344 + /* 18568 */ MCD_OPC_Decode, + 151, + 12, + 143, + 1, // Opcode: MVE_VQSUBs32 + /* 18573 */ MCD_OPC_FilterValue, + 15, + 110, + 26, + 0, // Skip to: 25344 + /* 18578 */ MCD_OPC_CheckPredicate, + 22, + 105, + 26, + 0, // Skip to: 25344 + /* 18583 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 98, + 26, + 0, // Skip to: 25344 + /* 18590 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 91, + 26, + 0, // Skip to: 25344 + /* 18597 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 84, + 26, + 0, // Skip to: 25344 + /* 18604 */ MCD_OPC_Decode, + 154, + 12, + 143, + 1, // Opcode: MVE_VQSUBu32 + /* 18609 */ MCD_OPC_FilterValue, + 4, + 251, + 1, + 0, // Skip to: 19121 + /* 18614 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 18617 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 18785 + /* 18622 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18625 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 18705 + /* 18630 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18633 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18669 + /* 18638 */ MCD_OPC_CheckPredicate, + 22, + 45, + 26, + 0, // Skip to: 25344 + /* 18643 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 38, + 26, + 0, // Skip to: 25344 + /* 18650 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 31, + 26, + 0, // Skip to: 25344 + /* 18657 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 24, + 26, + 0, // Skip to: 25344 + /* 18664 */ MCD_OPC_Decode, + 239, + 12, + 189, + 1, // Opcode: MVE_VSHL_by_vecs8 + /* 18669 */ MCD_OPC_FilterValue, + 15, + 14, + 26, + 0, // Skip to: 25344 + /* 18674 */ MCD_OPC_CheckPredicate, + 22, + 9, + 26, + 0, // Skip to: 25344 + /* 18679 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 2, + 26, + 0, // Skip to: 25344 + /* 18686 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 251, + 25, + 0, // Skip to: 25344 + /* 18693 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 244, + 25, + 0, // Skip to: 25344 + /* 18700 */ MCD_OPC_Decode, + 242, + 12, + 189, + 1, // Opcode: MVE_VSHL_by_vecu8 + /* 18705 */ MCD_OPC_FilterValue, + 1, + 234, + 25, + 0, // Skip to: 25344 + /* 18710 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18713 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18749 + /* 18718 */ MCD_OPC_CheckPredicate, + 22, + 221, + 25, + 0, // Skip to: 25344 + /* 18723 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 25, + 0, // Skip to: 25344 + /* 18730 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 25, + 0, // Skip to: 25344 + /* 18737 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 25, + 0, // Skip to: 25344 + /* 18744 */ MCD_OPC_Decode, + 244, + 11, + 189, + 1, // Opcode: MVE_VQSHL_by_vecs8 + /* 18749 */ MCD_OPC_FilterValue, + 15, + 190, + 25, + 0, // Skip to: 25344 + /* 18754 */ MCD_OPC_CheckPredicate, + 22, + 185, + 25, + 0, // Skip to: 25344 + /* 18759 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 25, + 0, // Skip to: 25344 + /* 18766 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 25, + 0, // Skip to: 25344 + /* 18773 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 25, + 0, // Skip to: 25344 + /* 18780 */ MCD_OPC_Decode, + 247, + 11, + 189, + 1, // Opcode: MVE_VQSHL_by_vecu8 + /* 18785 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 18953 + /* 18790 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18793 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 18873 + /* 18798 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18801 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18837 + /* 18806 */ MCD_OPC_CheckPredicate, + 22, + 133, + 25, + 0, // Skip to: 25344 + /* 18811 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 126, + 25, + 0, // Skip to: 25344 + /* 18818 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 119, + 25, + 0, // Skip to: 25344 + /* 18825 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 112, + 25, + 0, // Skip to: 25344 + /* 18832 */ MCD_OPC_Decode, + 237, + 12, + 189, + 1, // Opcode: MVE_VSHL_by_vecs16 + /* 18837 */ MCD_OPC_FilterValue, + 15, + 102, + 25, + 0, // Skip to: 25344 + /* 18842 */ MCD_OPC_CheckPredicate, + 22, + 97, + 25, + 0, // Skip to: 25344 + /* 18847 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 90, + 25, + 0, // Skip to: 25344 + /* 18854 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 83, + 25, + 0, // Skip to: 25344 + /* 18861 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 76, + 25, + 0, // Skip to: 25344 + /* 18868 */ MCD_OPC_Decode, + 240, + 12, + 189, + 1, // Opcode: MVE_VSHL_by_vecu16 + /* 18873 */ MCD_OPC_FilterValue, + 1, + 66, + 25, + 0, // Skip to: 25344 + /* 18878 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18881 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18917 + /* 18886 */ MCD_OPC_CheckPredicate, + 22, + 53, + 25, + 0, // Skip to: 25344 + /* 18891 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 46, + 25, + 0, // Skip to: 25344 + /* 18898 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 39, + 25, + 0, // Skip to: 25344 + /* 18905 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 32, + 25, + 0, // Skip to: 25344 + /* 18912 */ MCD_OPC_Decode, + 242, + 11, + 189, + 1, // Opcode: MVE_VQSHL_by_vecs16 + /* 18917 */ MCD_OPC_FilterValue, + 15, + 22, + 25, + 0, // Skip to: 25344 + /* 18922 */ MCD_OPC_CheckPredicate, + 22, + 17, + 25, + 0, // Skip to: 25344 + /* 18927 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 10, + 25, + 0, // Skip to: 25344 + /* 18934 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 3, + 25, + 0, // Skip to: 25344 + /* 18941 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 252, + 24, + 0, // Skip to: 25344 + /* 18948 */ MCD_OPC_Decode, + 245, + 11, + 189, + 1, // Opcode: MVE_VQSHL_by_vecu16 + /* 18953 */ MCD_OPC_FilterValue, + 2, + 242, + 24, + 0, // Skip to: 25344 + /* 18958 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18961 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 19041 + /* 18966 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18969 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19005 + /* 18974 */ MCD_OPC_CheckPredicate, + 22, + 221, + 24, + 0, // Skip to: 25344 + /* 18979 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 24, + 0, // Skip to: 25344 + /* 18986 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 24, + 0, // Skip to: 25344 + /* 18993 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 24, + 0, // Skip to: 25344 + /* 19000 */ MCD_OPC_Decode, + 238, + 12, + 189, + 1, // Opcode: MVE_VSHL_by_vecs32 + /* 19005 */ MCD_OPC_FilterValue, + 15, + 190, + 24, + 0, // Skip to: 25344 + /* 19010 */ MCD_OPC_CheckPredicate, + 22, + 185, + 24, + 0, // Skip to: 25344 + /* 19015 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 24, + 0, // Skip to: 25344 + /* 19022 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 24, + 0, // Skip to: 25344 + /* 19029 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 24, + 0, // Skip to: 25344 + /* 19036 */ MCD_OPC_Decode, + 241, + 12, + 189, + 1, // Opcode: MVE_VSHL_by_vecu32 + /* 19041 */ MCD_OPC_FilterValue, + 1, + 154, + 24, + 0, // Skip to: 25344 + /* 19046 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19049 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19085 + /* 19054 */ MCD_OPC_CheckPredicate, + 22, + 141, + 24, + 0, // Skip to: 25344 + /* 19059 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 134, + 24, + 0, // Skip to: 25344 + /* 19066 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 127, + 24, + 0, // Skip to: 25344 + /* 19073 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 120, + 24, + 0, // Skip to: 25344 + /* 19080 */ MCD_OPC_Decode, + 243, + 11, + 189, + 1, // Opcode: MVE_VQSHL_by_vecs32 + /* 19085 */ MCD_OPC_FilterValue, + 15, + 110, + 24, + 0, // Skip to: 25344 + /* 19090 */ MCD_OPC_CheckPredicate, + 22, + 105, + 24, + 0, // Skip to: 25344 + /* 19095 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 98, + 24, + 0, // Skip to: 25344 + /* 19102 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 91, + 24, + 0, // Skip to: 25344 + /* 19109 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 84, + 24, + 0, // Skip to: 25344 + /* 19116 */ MCD_OPC_Decode, + 246, + 11, + 189, + 1, // Opcode: MVE_VQSHL_by_vecu32 + /* 19121 */ MCD_OPC_FilterValue, + 5, + 251, + 1, + 0, // Skip to: 19633 + /* 19126 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 19129 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 19297 + /* 19134 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19137 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 19217 + /* 19142 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19145 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19181 + /* 19150 */ MCD_OPC_CheckPredicate, + 22, + 45, + 24, + 0, // Skip to: 25344 + /* 19155 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 38, + 24, + 0, // Skip to: 25344 + /* 19162 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 31, + 24, + 0, // Skip to: 25344 + /* 19169 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 24, + 24, + 0, // Skip to: 25344 + /* 19176 */ MCD_OPC_Decode, + 198, + 12, + 189, + 1, // Opcode: MVE_VRSHL_by_vecs8 + /* 19181 */ MCD_OPC_FilterValue, + 15, + 14, + 24, + 0, // Skip to: 25344 + /* 19186 */ MCD_OPC_CheckPredicate, + 22, + 9, + 24, + 0, // Skip to: 25344 + /* 19191 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 2, + 24, + 0, // Skip to: 25344 + /* 19198 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 251, + 23, + 0, // Skip to: 25344 + /* 19205 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 244, + 23, + 0, // Skip to: 25344 + /* 19212 */ MCD_OPC_Decode, + 201, + 12, + 189, + 1, // Opcode: MVE_VRSHL_by_vecu8 + /* 19217 */ MCD_OPC_FilterValue, + 1, + 234, + 23, + 0, // Skip to: 25344 + /* 19222 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19225 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19261 + /* 19230 */ MCD_OPC_CheckPredicate, + 22, + 221, + 23, + 0, // Skip to: 25344 + /* 19235 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 23, + 0, // Skip to: 25344 + /* 19242 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 23, + 0, // Skip to: 25344 + /* 19249 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 23, + 0, // Skip to: 25344 + /* 19256 */ MCD_OPC_Decode, + 217, + 11, + 189, + 1, // Opcode: MVE_VQRSHL_by_vecs8 + /* 19261 */ MCD_OPC_FilterValue, + 15, + 190, + 23, + 0, // Skip to: 25344 + /* 19266 */ MCD_OPC_CheckPredicate, + 22, + 185, + 23, + 0, // Skip to: 25344 + /* 19271 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 23, + 0, // Skip to: 25344 + /* 19278 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 23, + 0, // Skip to: 25344 + /* 19285 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 23, + 0, // Skip to: 25344 + /* 19292 */ MCD_OPC_Decode, + 220, + 11, + 189, + 1, // Opcode: MVE_VQRSHL_by_vecu8 + /* 19297 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 19465 + /* 19302 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19305 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 19385 + /* 19310 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19313 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19349 + /* 19318 */ MCD_OPC_CheckPredicate, + 22, + 133, + 23, + 0, // Skip to: 25344 + /* 19323 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 126, + 23, + 0, // Skip to: 25344 + /* 19330 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 119, + 23, + 0, // Skip to: 25344 + /* 19337 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 112, + 23, + 0, // Skip to: 25344 + /* 19344 */ MCD_OPC_Decode, + 196, + 12, + 189, + 1, // Opcode: MVE_VRSHL_by_vecs16 + /* 19349 */ MCD_OPC_FilterValue, + 15, + 102, + 23, + 0, // Skip to: 25344 + /* 19354 */ MCD_OPC_CheckPredicate, + 22, + 97, + 23, + 0, // Skip to: 25344 + /* 19359 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 90, + 23, + 0, // Skip to: 25344 + /* 19366 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 83, + 23, + 0, // Skip to: 25344 + /* 19373 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 76, + 23, + 0, // Skip to: 25344 + /* 19380 */ MCD_OPC_Decode, + 199, + 12, + 189, + 1, // Opcode: MVE_VRSHL_by_vecu16 + /* 19385 */ MCD_OPC_FilterValue, + 1, + 66, + 23, + 0, // Skip to: 25344 + /* 19390 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19393 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19429 + /* 19398 */ MCD_OPC_CheckPredicate, + 22, + 53, + 23, + 0, // Skip to: 25344 + /* 19403 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 46, + 23, + 0, // Skip to: 25344 + /* 19410 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 39, + 23, + 0, // Skip to: 25344 + /* 19417 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 32, + 23, + 0, // Skip to: 25344 + /* 19424 */ MCD_OPC_Decode, + 215, + 11, + 189, + 1, // Opcode: MVE_VQRSHL_by_vecs16 + /* 19429 */ MCD_OPC_FilterValue, + 15, + 22, + 23, + 0, // Skip to: 25344 + /* 19434 */ MCD_OPC_CheckPredicate, + 22, + 17, + 23, + 0, // Skip to: 25344 + /* 19439 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 10, + 23, + 0, // Skip to: 25344 + /* 19446 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 3, + 23, + 0, // Skip to: 25344 + /* 19453 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 252, + 22, + 0, // Skip to: 25344 + /* 19460 */ MCD_OPC_Decode, + 218, + 11, + 189, + 1, // Opcode: MVE_VQRSHL_by_vecu16 + /* 19465 */ MCD_OPC_FilterValue, + 2, + 242, + 22, + 0, // Skip to: 25344 + /* 19470 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19473 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 19553 + /* 19478 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19481 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19517 + /* 19486 */ MCD_OPC_CheckPredicate, + 22, + 221, + 22, + 0, // Skip to: 25344 + /* 19491 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 22, + 0, // Skip to: 25344 + /* 19498 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 22, + 0, // Skip to: 25344 + /* 19505 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 22, + 0, // Skip to: 25344 + /* 19512 */ MCD_OPC_Decode, + 197, + 12, + 189, + 1, // Opcode: MVE_VRSHL_by_vecs32 + /* 19517 */ MCD_OPC_FilterValue, + 15, + 190, + 22, + 0, // Skip to: 25344 + /* 19522 */ MCD_OPC_CheckPredicate, + 22, + 185, + 22, + 0, // Skip to: 25344 + /* 19527 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 22, + 0, // Skip to: 25344 + /* 19534 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 22, + 0, // Skip to: 25344 + /* 19541 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 22, + 0, // Skip to: 25344 + /* 19548 */ MCD_OPC_Decode, + 200, + 12, + 189, + 1, // Opcode: MVE_VRSHL_by_vecu32 + /* 19553 */ MCD_OPC_FilterValue, + 1, + 154, + 22, + 0, // Skip to: 25344 + /* 19558 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19561 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19597 + /* 19566 */ MCD_OPC_CheckPredicate, + 22, + 141, + 22, + 0, // Skip to: 25344 + /* 19571 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 134, + 22, + 0, // Skip to: 25344 + /* 19578 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 127, + 22, + 0, // Skip to: 25344 + /* 19585 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 120, + 22, + 0, // Skip to: 25344 + /* 19592 */ MCD_OPC_Decode, + 216, + 11, + 189, + 1, // Opcode: MVE_VQRSHL_by_vecs32 + /* 19597 */ MCD_OPC_FilterValue, + 15, + 110, + 22, + 0, // Skip to: 25344 + /* 19602 */ MCD_OPC_CheckPredicate, + 22, + 105, + 22, + 0, // Skip to: 25344 + /* 19607 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 98, + 22, + 0, // Skip to: 25344 + /* 19614 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 91, + 22, + 0, // Skip to: 25344 + /* 19621 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 84, + 22, + 0, // Skip to: 25344 + /* 19628 */ MCD_OPC_Decode, + 219, + 11, + 189, + 1, // Opcode: MVE_VQRSHL_by_vecu32 + /* 19633 */ MCD_OPC_FilterValue, + 6, + 251, + 1, + 0, // Skip to: 20145 + /* 19638 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 19641 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 19809 + /* 19646 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19649 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 19729 + /* 19654 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19657 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19693 + /* 19662 */ MCD_OPC_CheckPredicate, + 22, + 45, + 22, + 0, // Skip to: 25344 + /* 19667 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 38, + 22, + 0, // Skip to: 25344 + /* 19674 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 31, + 22, + 0, // Skip to: 25344 + /* 19681 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 24, + 22, + 0, // Skip to: 25344 + /* 19688 */ MCD_OPC_Decode, + 203, + 9, + 143, + 1, // Opcode: MVE_VMAXs8 + /* 19693 */ MCD_OPC_FilterValue, + 15, + 14, + 22, + 0, // Skip to: 25344 + /* 19698 */ MCD_OPC_CheckPredicate, + 22, + 9, + 22, + 0, // Skip to: 25344 + /* 19703 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 2, + 22, + 0, // Skip to: 25344 + /* 19710 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 251, + 21, + 0, // Skip to: 25344 + /* 19717 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 244, + 21, + 0, // Skip to: 25344 + /* 19724 */ MCD_OPC_Decode, + 206, + 9, + 143, + 1, // Opcode: MVE_VMAXu8 + /* 19729 */ MCD_OPC_FilterValue, + 1, + 234, + 21, + 0, // Skip to: 25344 + /* 19734 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19737 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19773 + /* 19742 */ MCD_OPC_CheckPredicate, + 22, + 221, + 21, + 0, // Skip to: 25344 + /* 19747 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 21, + 0, // Skip to: 25344 + /* 19754 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 21, + 0, // Skip to: 25344 + /* 19761 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 21, + 0, // Skip to: 25344 + /* 19768 */ MCD_OPC_Decode, + 229, + 9, + 143, + 1, // Opcode: MVE_VMINs8 + /* 19773 */ MCD_OPC_FilterValue, + 15, + 190, + 21, + 0, // Skip to: 25344 + /* 19778 */ MCD_OPC_CheckPredicate, + 22, + 185, + 21, + 0, // Skip to: 25344 + /* 19783 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 21, + 0, // Skip to: 25344 + /* 19790 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 21, + 0, // Skip to: 25344 + /* 19797 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 21, + 0, // Skip to: 25344 + /* 19804 */ MCD_OPC_Decode, + 232, + 9, + 143, + 1, // Opcode: MVE_VMINu8 + /* 19809 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 19977 + /* 19814 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19817 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 19897 + /* 19822 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19825 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19861 + /* 19830 */ MCD_OPC_CheckPredicate, + 22, + 133, + 21, + 0, // Skip to: 25344 + /* 19835 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 126, + 21, + 0, // Skip to: 25344 + /* 19842 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 119, + 21, + 0, // Skip to: 25344 + /* 19849 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 112, + 21, + 0, // Skip to: 25344 + /* 19856 */ MCD_OPC_Decode, + 201, + 9, + 143, + 1, // Opcode: MVE_VMAXs16 + /* 19861 */ MCD_OPC_FilterValue, + 15, + 102, + 21, + 0, // Skip to: 25344 + /* 19866 */ MCD_OPC_CheckPredicate, + 22, + 97, + 21, + 0, // Skip to: 25344 + /* 19871 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 90, + 21, + 0, // Skip to: 25344 + /* 19878 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 83, + 21, + 0, // Skip to: 25344 + /* 19885 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 76, + 21, + 0, // Skip to: 25344 + /* 19892 */ MCD_OPC_Decode, + 204, + 9, + 143, + 1, // Opcode: MVE_VMAXu16 + /* 19897 */ MCD_OPC_FilterValue, + 1, + 66, + 21, + 0, // Skip to: 25344 + /* 19902 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19905 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19941 + /* 19910 */ MCD_OPC_CheckPredicate, + 22, + 53, + 21, + 0, // Skip to: 25344 + /* 19915 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 46, + 21, + 0, // Skip to: 25344 + /* 19922 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 39, + 21, + 0, // Skip to: 25344 + /* 19929 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 32, + 21, + 0, // Skip to: 25344 + /* 19936 */ MCD_OPC_Decode, + 227, + 9, + 143, + 1, // Opcode: MVE_VMINs16 + /* 19941 */ MCD_OPC_FilterValue, + 15, + 22, + 21, + 0, // Skip to: 25344 + /* 19946 */ MCD_OPC_CheckPredicate, + 22, + 17, + 21, + 0, // Skip to: 25344 + /* 19951 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 10, + 21, + 0, // Skip to: 25344 + /* 19958 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 3, + 21, + 0, // Skip to: 25344 + /* 19965 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 252, + 20, + 0, // Skip to: 25344 + /* 19972 */ MCD_OPC_Decode, + 230, + 9, + 143, + 1, // Opcode: MVE_VMINu16 + /* 19977 */ MCD_OPC_FilterValue, + 2, + 242, + 20, + 0, // Skip to: 25344 + /* 19982 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19985 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 20065 + /* 19990 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19993 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 20029 + /* 19998 */ MCD_OPC_CheckPredicate, + 22, + 221, + 20, + 0, // Skip to: 25344 + /* 20003 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 20, + 0, // Skip to: 25344 + /* 20010 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 20, + 0, // Skip to: 25344 + /* 20017 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 20, + 0, // Skip to: 25344 + /* 20024 */ MCD_OPC_Decode, + 202, + 9, + 143, + 1, // Opcode: MVE_VMAXs32 + /* 20029 */ MCD_OPC_FilterValue, + 15, + 190, + 20, + 0, // Skip to: 25344 + /* 20034 */ MCD_OPC_CheckPredicate, + 22, + 185, + 20, + 0, // Skip to: 25344 + /* 20039 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 20, + 0, // Skip to: 25344 + /* 20046 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 20, + 0, // Skip to: 25344 + /* 20053 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 20, + 0, // Skip to: 25344 + /* 20060 */ MCD_OPC_Decode, + 205, + 9, + 143, + 1, // Opcode: MVE_VMAXu32 + /* 20065 */ MCD_OPC_FilterValue, + 1, + 154, + 20, + 0, // Skip to: 25344 + /* 20070 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20073 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 20109 + /* 20078 */ MCD_OPC_CheckPredicate, + 22, + 141, + 20, + 0, // Skip to: 25344 + /* 20083 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 134, + 20, + 0, // Skip to: 25344 + /* 20090 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 127, + 20, + 0, // Skip to: 25344 + /* 20097 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 120, + 20, + 0, // Skip to: 25344 + /* 20104 */ MCD_OPC_Decode, + 228, + 9, + 143, + 1, // Opcode: MVE_VMINs32 + /* 20109 */ MCD_OPC_FilterValue, + 15, + 110, + 20, + 0, // Skip to: 25344 + /* 20114 */ MCD_OPC_CheckPredicate, + 22, + 105, + 20, + 0, // Skip to: 25344 + /* 20119 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 98, + 20, + 0, // Skip to: 25344 + /* 20126 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 91, + 20, + 0, // Skip to: 25344 + /* 20133 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 84, + 20, + 0, // Skip to: 25344 + /* 20140 */ MCD_OPC_Decode, + 231, + 9, + 143, + 1, // Opcode: MVE_VMINu32 + /* 20145 */ MCD_OPC_FilterValue, + 7, + 29, + 1, + 0, // Skip to: 20435 + /* 20150 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 20153 */ MCD_OPC_FilterValue, + 0, + 89, + 0, + 0, // Skip to: 20247 + /* 20158 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20161 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20204 + /* 20166 */ MCD_OPC_CheckPredicate, + 22, + 53, + 20, + 0, // Skip to: 25344 + /* 20171 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 46, + 20, + 0, // Skip to: 25344 + /* 20178 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 39, + 20, + 0, // Skip to: 25344 + /* 20185 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 32, + 20, + 0, // Skip to: 25344 + /* 20192 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 25, + 20, + 0, // Skip to: 25344 + /* 20199 */ MCD_OPC_Decode, + 183, + 7, + 143, + 1, // Opcode: MVE_VABDs8 + /* 20204 */ MCD_OPC_FilterValue, + 15, + 15, + 20, + 0, // Skip to: 25344 + /* 20209 */ MCD_OPC_CheckPredicate, + 22, + 10, + 20, + 0, // Skip to: 25344 + /* 20214 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 3, + 20, + 0, // Skip to: 25344 + /* 20221 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 252, + 19, + 0, // Skip to: 25344 + /* 20228 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 245, + 19, + 0, // Skip to: 25344 + /* 20235 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 238, + 19, + 0, // Skip to: 25344 + /* 20242 */ MCD_OPC_Decode, + 186, + 7, + 143, + 1, // Opcode: MVE_VABDu8 + /* 20247 */ MCD_OPC_FilterValue, + 1, + 89, + 0, + 0, // Skip to: 20341 + /* 20252 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20255 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20298 + /* 20260 */ MCD_OPC_CheckPredicate, + 22, + 215, + 19, + 0, // Skip to: 25344 + /* 20265 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 208, + 19, + 0, // Skip to: 25344 + /* 20272 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 201, + 19, + 0, // Skip to: 25344 + /* 20279 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 194, + 19, + 0, // Skip to: 25344 + /* 20286 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 187, + 19, + 0, // Skip to: 25344 + /* 20293 */ MCD_OPC_Decode, + 181, + 7, + 143, + 1, // Opcode: MVE_VABDs16 + /* 20298 */ MCD_OPC_FilterValue, + 15, + 177, + 19, + 0, // Skip to: 25344 + /* 20303 */ MCD_OPC_CheckPredicate, + 22, + 172, + 19, + 0, // Skip to: 25344 + /* 20308 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 165, + 19, + 0, // Skip to: 25344 + /* 20315 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 158, + 19, + 0, // Skip to: 25344 + /* 20322 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 151, + 19, + 0, // Skip to: 25344 + /* 20329 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 144, + 19, + 0, // Skip to: 25344 + /* 20336 */ MCD_OPC_Decode, + 184, + 7, + 143, + 1, // Opcode: MVE_VABDu16 + /* 20341 */ MCD_OPC_FilterValue, + 2, + 134, + 19, + 0, // Skip to: 25344 + /* 20346 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20349 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20392 + /* 20354 */ MCD_OPC_CheckPredicate, + 22, + 121, + 19, + 0, // Skip to: 25344 + /* 20359 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 114, + 19, + 0, // Skip to: 25344 + /* 20366 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 107, + 19, + 0, // Skip to: 25344 + /* 20373 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 100, + 19, + 0, // Skip to: 25344 + /* 20380 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 93, + 19, + 0, // Skip to: 25344 + /* 20387 */ MCD_OPC_Decode, + 182, + 7, + 143, + 1, // Opcode: MVE_VABDs32 + /* 20392 */ MCD_OPC_FilterValue, + 15, + 83, + 19, + 0, // Skip to: 25344 + /* 20397 */ MCD_OPC_CheckPredicate, + 22, + 78, + 19, + 0, // Skip to: 25344 + /* 20402 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 71, + 19, + 0, // Skip to: 25344 + /* 20409 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 64, + 19, + 0, // Skip to: 25344 + /* 20416 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 57, + 19, + 0, // Skip to: 25344 + /* 20423 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 50, + 19, + 0, // Skip to: 25344 + /* 20430 */ MCD_OPC_Decode, + 185, + 7, + 143, + 1, // Opcode: MVE_VABDu32 + /* 20435 */ MCD_OPC_FilterValue, + 8, + 29, + 1, + 0, // Skip to: 20725 + /* 20440 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 20443 */ MCD_OPC_FilterValue, + 0, + 89, + 0, + 0, // Skip to: 20537 + /* 20448 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20451 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20494 + /* 20456 */ MCD_OPC_CheckPredicate, + 22, + 19, + 19, + 0, // Skip to: 25344 + /* 20461 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 12, + 19, + 0, // Skip to: 25344 + /* 20468 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 5, + 19, + 0, // Skip to: 25344 + /* 20475 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 254, + 18, + 0, // Skip to: 25344 + /* 20482 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 247, + 18, + 0, // Skip to: 25344 + /* 20489 */ MCD_OPC_Decode, + 219, + 7, + 143, + 1, // Opcode: MVE_VADDi8 + /* 20494 */ MCD_OPC_FilterValue, + 15, + 237, + 18, + 0, // Skip to: 25344 + /* 20499 */ MCD_OPC_CheckPredicate, + 22, + 232, + 18, + 0, // Skip to: 25344 + /* 20504 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 225, + 18, + 0, // Skip to: 25344 + /* 20511 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 218, + 18, + 0, // Skip to: 25344 + /* 20518 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 211, + 18, + 0, // Skip to: 25344 + /* 20525 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 204, + 18, + 0, // Skip to: 25344 + /* 20532 */ MCD_OPC_Decode, + 218, + 13, + 143, + 1, // Opcode: MVE_VSUBi8 + /* 20537 */ MCD_OPC_FilterValue, + 1, + 89, + 0, + 0, // Skip to: 20631 + /* 20542 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20545 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20588 + /* 20550 */ MCD_OPC_CheckPredicate, + 22, + 181, + 18, + 0, // Skip to: 25344 + /* 20555 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 174, + 18, + 0, // Skip to: 25344 + /* 20562 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 167, + 18, + 0, // Skip to: 25344 + /* 20569 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 160, + 18, + 0, // Skip to: 25344 + /* 20576 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 153, + 18, + 0, // Skip to: 25344 + /* 20583 */ MCD_OPC_Decode, + 217, + 7, + 143, + 1, // Opcode: MVE_VADDi16 + /* 20588 */ MCD_OPC_FilterValue, + 15, + 143, + 18, + 0, // Skip to: 25344 + /* 20593 */ MCD_OPC_CheckPredicate, + 22, + 138, + 18, + 0, // Skip to: 25344 + /* 20598 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 131, + 18, + 0, // Skip to: 25344 + /* 20605 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 124, + 18, + 0, // Skip to: 25344 + /* 20612 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 117, + 18, + 0, // Skip to: 25344 + /* 20619 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 110, + 18, + 0, // Skip to: 25344 + /* 20626 */ MCD_OPC_Decode, + 216, + 13, + 143, + 1, // Opcode: MVE_VSUBi16 + /* 20631 */ MCD_OPC_FilterValue, + 2, + 100, + 18, + 0, // Skip to: 25344 + /* 20636 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20639 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20682 + /* 20644 */ MCD_OPC_CheckPredicate, + 22, + 87, + 18, + 0, // Skip to: 25344 + /* 20649 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 80, + 18, + 0, // Skip to: 25344 + /* 20656 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 73, + 18, + 0, // Skip to: 25344 + /* 20663 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 66, + 18, + 0, // Skip to: 25344 + /* 20670 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 59, + 18, + 0, // Skip to: 25344 + /* 20677 */ MCD_OPC_Decode, + 218, + 7, + 143, + 1, // Opcode: MVE_VADDi32 + /* 20682 */ MCD_OPC_FilterValue, + 15, + 49, + 18, + 0, // Skip to: 25344 + /* 20687 */ MCD_OPC_CheckPredicate, + 22, + 44, + 18, + 0, // Skip to: 25344 + /* 20692 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 37, + 18, + 0, // Skip to: 25344 + /* 20699 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 30, + 18, + 0, // Skip to: 25344 + /* 20706 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 23, + 18, + 0, // Skip to: 25344 + /* 20713 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 16, + 18, + 0, // Skip to: 25344 + /* 20720 */ MCD_OPC_Decode, + 217, + 13, + 143, + 1, // Opcode: MVE_VSUBi32 + /* 20725 */ MCD_OPC_FilterValue, + 9, + 153, + 0, + 0, // Skip to: 20883 + /* 20730 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 20733 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 20783 + /* 20738 */ MCD_OPC_CheckPredicate, + 22, + 249, + 17, + 0, // Skip to: 25344 + /* 20743 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 242, + 17, + 0, // Skip to: 25344 + /* 20750 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 235, + 17, + 0, // Skip to: 25344 + /* 20757 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 228, + 17, + 0, // Skip to: 25344 + /* 20764 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 221, + 17, + 0, // Skip to: 25344 + /* 20771 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 214, + 17, + 0, // Skip to: 25344 + /* 20778 */ MCD_OPC_Decode, + 219, + 10, + 143, + 1, // Opcode: MVE_VMULi8 + /* 20783 */ MCD_OPC_FilterValue, + 1, + 45, + 0, + 0, // Skip to: 20833 + /* 20788 */ MCD_OPC_CheckPredicate, + 22, + 199, + 17, + 0, // Skip to: 25344 + /* 20793 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 192, + 17, + 0, // Skip to: 25344 + /* 20800 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 185, + 17, + 0, // Skip to: 25344 + /* 20807 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 178, + 17, + 0, // Skip to: 25344 + /* 20814 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 171, + 17, + 0, // Skip to: 25344 + /* 20821 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 17, + 0, // Skip to: 25344 + /* 20828 */ MCD_OPC_Decode, + 217, + 10, + 143, + 1, // Opcode: MVE_VMULi16 + /* 20833 */ MCD_OPC_FilterValue, + 2, + 154, + 17, + 0, // Skip to: 25344 + /* 20838 */ MCD_OPC_CheckPredicate, + 22, + 149, + 17, + 0, // Skip to: 25344 + /* 20843 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 142, + 17, + 0, // Skip to: 25344 + /* 20850 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 135, + 17, + 0, // Skip to: 25344 + /* 20857 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 128, + 17, + 0, // Skip to: 25344 + /* 20864 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 121, + 17, + 0, // Skip to: 25344 + /* 20871 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 114, + 17, + 0, // Skip to: 25344 + /* 20878 */ MCD_OPC_Decode, + 218, + 10, + 143, + 1, // Opcode: MVE_VMULi32 + /* 20883 */ MCD_OPC_FilterValue, + 11, + 29, + 1, + 0, // Skip to: 21173 + /* 20888 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 20891 */ MCD_OPC_FilterValue, + 0, + 89, + 0, + 0, // Skip to: 20985 + /* 20896 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20899 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20942 + /* 20904 */ MCD_OPC_CheckPredicate, + 22, + 83, + 17, + 0, // Skip to: 25344 + /* 20909 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 76, + 17, + 0, // Skip to: 25344 + /* 20916 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 69, + 17, + 0, // Skip to: 25344 + /* 20923 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 62, + 17, + 0, // Skip to: 25344 + /* 20930 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 55, + 17, + 0, // Skip to: 25344 + /* 20937 */ MCD_OPC_Decode, + 167, + 11, + 143, + 1, // Opcode: MVE_VQDMULHi8 + /* 20942 */ MCD_OPC_FilterValue, + 15, + 45, + 17, + 0, // Skip to: 25344 + /* 20947 */ MCD_OPC_CheckPredicate, + 22, + 40, + 17, + 0, // Skip to: 25344 + /* 20952 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 33, + 17, + 0, // Skip to: 25344 + /* 20959 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 26, + 17, + 0, // Skip to: 25344 + /* 20966 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 19, + 17, + 0, // Skip to: 25344 + /* 20973 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 12, + 17, + 0, // Skip to: 25344 + /* 20980 */ MCD_OPC_Decode, + 214, + 11, + 143, + 1, // Opcode: MVE_VQRDMULHi8 + /* 20985 */ MCD_OPC_FilterValue, + 1, + 89, + 0, + 0, // Skip to: 21079 + /* 20990 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20993 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 21036 + /* 20998 */ MCD_OPC_CheckPredicate, + 22, + 245, + 16, + 0, // Skip to: 25344 + /* 21003 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 238, + 16, + 0, // Skip to: 25344 + /* 21010 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 231, + 16, + 0, // Skip to: 25344 + /* 21017 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 224, + 16, + 0, // Skip to: 25344 + /* 21024 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 217, + 16, + 0, // Skip to: 25344 + /* 21031 */ MCD_OPC_Decode, + 165, + 11, + 143, + 1, // Opcode: MVE_VQDMULHi16 + /* 21036 */ MCD_OPC_FilterValue, + 15, + 207, + 16, + 0, // Skip to: 25344 + /* 21041 */ MCD_OPC_CheckPredicate, + 22, + 202, + 16, + 0, // Skip to: 25344 + /* 21046 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 195, + 16, + 0, // Skip to: 25344 + /* 21053 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 188, + 16, + 0, // Skip to: 25344 + /* 21060 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 181, + 16, + 0, // Skip to: 25344 + /* 21067 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 174, + 16, + 0, // Skip to: 25344 + /* 21074 */ MCD_OPC_Decode, + 212, + 11, + 143, + 1, // Opcode: MVE_VQRDMULHi16 + /* 21079 */ MCD_OPC_FilterValue, + 2, + 164, + 16, + 0, // Skip to: 25344 + /* 21084 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 21087 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 21130 + /* 21092 */ MCD_OPC_CheckPredicate, + 22, + 151, + 16, + 0, // Skip to: 25344 + /* 21097 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 144, + 16, + 0, // Skip to: 25344 + /* 21104 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 137, + 16, + 0, // Skip to: 25344 + /* 21111 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 130, + 16, + 0, // Skip to: 25344 + /* 21118 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 123, + 16, + 0, // Skip to: 25344 + /* 21125 */ MCD_OPC_Decode, + 166, + 11, + 143, + 1, // Opcode: MVE_VQDMULHi32 + /* 21130 */ MCD_OPC_FilterValue, + 15, + 113, + 16, + 0, // Skip to: 25344 + /* 21135 */ MCD_OPC_CheckPredicate, + 22, + 108, + 16, + 0, // Skip to: 25344 + /* 21140 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 101, + 16, + 0, // Skip to: 25344 + /* 21147 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 94, + 16, + 0, // Skip to: 25344 + /* 21154 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 87, + 16, + 0, // Skip to: 25344 + /* 21161 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 80, + 16, + 0, // Skip to: 25344 + /* 21168 */ MCD_OPC_Decode, + 213, + 11, + 143, + 1, // Opcode: MVE_VQRDMULHi32 + /* 21173 */ MCD_OPC_FilterValue, + 12, + 203, + 0, + 0, // Skip to: 21381 + /* 21178 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 21181 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 21231 + /* 21186 */ MCD_OPC_CheckPredicate, + 24, + 57, + 16, + 0, // Skip to: 25344 + /* 21191 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 50, + 16, + 0, // Skip to: 25344 + /* 21198 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 43, + 16, + 0, // Skip to: 25344 + /* 21205 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 36, + 16, + 0, // Skip to: 25344 + /* 21212 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 29, + 16, + 0, // Skip to: 25344 + /* 21219 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 22, + 16, + 0, // Skip to: 25344 + /* 21226 */ MCD_OPC_Decode, + 191, + 8, + 142, + 1, // Opcode: MVE_VFMAf32 + /* 21231 */ MCD_OPC_FilterValue, + 1, + 45, + 0, + 0, // Skip to: 21281 + /* 21236 */ MCD_OPC_CheckPredicate, + 24, + 7, + 16, + 0, // Skip to: 25344 + /* 21241 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 0, + 16, + 0, // Skip to: 25344 + /* 21248 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 249, + 15, + 0, // Skip to: 25344 + /* 21255 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 242, + 15, + 0, // Skip to: 25344 + /* 21262 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 235, + 15, + 0, // Skip to: 25344 + /* 21269 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 228, + 15, + 0, // Skip to: 25344 + /* 21276 */ MCD_OPC_Decode, + 190, + 8, + 142, + 1, // Opcode: MVE_VFMAf16 + /* 21281 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 21331 + /* 21286 */ MCD_OPC_CheckPredicate, + 24, + 213, + 15, + 0, // Skip to: 25344 + /* 21291 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 206, + 15, + 0, // Skip to: 25344 + /* 21298 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 199, + 15, + 0, // Skip to: 25344 + /* 21305 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 192, + 15, + 0, // Skip to: 25344 + /* 21312 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 185, + 15, + 0, // Skip to: 25344 + /* 21319 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 178, + 15, + 0, // Skip to: 25344 + /* 21326 */ MCD_OPC_Decode, + 193, + 8, + 142, + 1, // Opcode: MVE_VFMSf32 + /* 21331 */ MCD_OPC_FilterValue, + 3, + 168, + 15, + 0, // Skip to: 25344 + /* 21336 */ MCD_OPC_CheckPredicate, + 24, + 163, + 15, + 0, // Skip to: 25344 + /* 21341 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 156, + 15, + 0, // Skip to: 25344 + /* 21348 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 149, + 15, + 0, // Skip to: 25344 + /* 21355 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 142, + 15, + 0, // Skip to: 25344 + /* 21362 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 135, + 15, + 0, // Skip to: 25344 + /* 21369 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 128, + 15, + 0, // Skip to: 25344 + /* 21376 */ MCD_OPC_Decode, + 192, + 8, + 142, + 1, // Opcode: MVE_VFMSf16 + /* 21381 */ MCD_OPC_FilterValue, + 13, + 123, + 1, + 0, // Skip to: 21765 + /* 21386 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 21389 */ MCD_OPC_FilterValue, + 0, + 89, + 0, + 0, // Skip to: 21483 + /* 21394 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 21397 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 21440 + /* 21402 */ MCD_OPC_CheckPredicate, + 24, + 97, + 15, + 0, // Skip to: 25344 + /* 21407 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 90, + 15, + 0, // Skip to: 25344 + /* 21414 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 83, + 15, + 0, // Skip to: 25344 + /* 21421 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 76, + 15, + 0, // Skip to: 25344 + /* 21428 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 69, + 15, + 0, // Skip to: 25344 + /* 21435 */ MCD_OPC_Decode, + 216, + 7, + 143, + 1, // Opcode: MVE_VADDf32 + /* 21440 */ MCD_OPC_FilterValue, + 1, + 59, + 15, + 0, // Skip to: 25344 + /* 21445 */ MCD_OPC_CheckPredicate, + 24, + 54, + 15, + 0, // Skip to: 25344 + /* 21450 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 47, + 15, + 0, // Skip to: 25344 + /* 21457 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 40, + 15, + 0, // Skip to: 25344 + /* 21464 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 33, + 15, + 0, // Skip to: 25344 + /* 21471 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 26, + 15, + 0, // Skip to: 25344 + /* 21478 */ MCD_OPC_Decode, + 216, + 10, + 143, + 1, // Opcode: MVE_VMULf32 + /* 21483 */ MCD_OPC_FilterValue, + 1, + 89, + 0, + 0, // Skip to: 21577 + /* 21488 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 21491 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 21534 + /* 21496 */ MCD_OPC_CheckPredicate, + 24, + 3, + 15, + 0, // Skip to: 25344 + /* 21501 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 252, + 14, + 0, // Skip to: 25344 + /* 21508 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 245, + 14, + 0, // Skip to: 25344 + /* 21515 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 238, + 14, + 0, // Skip to: 25344 + /* 21522 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 231, + 14, + 0, // Skip to: 25344 + /* 21529 */ MCD_OPC_Decode, + 215, + 7, + 143, + 1, // Opcode: MVE_VADDf16 + /* 21534 */ MCD_OPC_FilterValue, + 1, + 221, + 14, + 0, // Skip to: 25344 + /* 21539 */ MCD_OPC_CheckPredicate, + 24, + 216, + 14, + 0, // Skip to: 25344 + /* 21544 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 209, + 14, + 0, // Skip to: 25344 + /* 21551 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 202, + 14, + 0, // Skip to: 25344 + /* 21558 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 195, + 14, + 0, // Skip to: 25344 + /* 21565 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 188, + 14, + 0, // Skip to: 25344 + /* 21572 */ MCD_OPC_Decode, + 215, + 10, + 143, + 1, // Opcode: MVE_VMULf16 + /* 21577 */ MCD_OPC_FilterValue, + 2, + 89, + 0, + 0, // Skip to: 21671 + /* 21582 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 21585 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 21628 + /* 21590 */ MCD_OPC_CheckPredicate, + 24, + 165, + 14, + 0, // Skip to: 25344 + /* 21595 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 158, + 14, + 0, // Skip to: 25344 + /* 21602 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 151, + 14, + 0, // Skip to: 25344 + /* 21609 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 144, + 14, + 0, // Skip to: 25344 + /* 21616 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 137, + 14, + 0, // Skip to: 25344 + /* 21623 */ MCD_OPC_Decode, + 215, + 13, + 143, + 1, // Opcode: MVE_VSUBf32 + /* 21628 */ MCD_OPC_FilterValue, + 15, + 127, + 14, + 0, // Skip to: 25344 + /* 21633 */ MCD_OPC_CheckPredicate, + 24, + 122, + 14, + 0, // Skip to: 25344 + /* 21638 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 115, + 14, + 0, // Skip to: 25344 + /* 21645 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 108, + 14, + 0, // Skip to: 25344 + /* 21652 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 101, + 14, + 0, // Skip to: 25344 + /* 21659 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 94, + 14, + 0, // Skip to: 25344 + /* 21666 */ MCD_OPC_Decode, + 180, + 7, + 143, + 1, // Opcode: MVE_VABDf32 + /* 21671 */ MCD_OPC_FilterValue, + 3, + 84, + 14, + 0, // Skip to: 25344 + /* 21676 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 21679 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 21722 + /* 21684 */ MCD_OPC_CheckPredicate, + 24, + 71, + 14, + 0, // Skip to: 25344 + /* 21689 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 64, + 14, + 0, // Skip to: 25344 + /* 21696 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 57, + 14, + 0, // Skip to: 25344 + /* 21703 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 50, + 14, + 0, // Skip to: 25344 + /* 21710 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 43, + 14, + 0, // Skip to: 25344 + /* 21717 */ MCD_OPC_Decode, + 214, + 13, + 143, + 1, // Opcode: MVE_VSUBf16 + /* 21722 */ MCD_OPC_FilterValue, + 15, + 33, + 14, + 0, // Skip to: 25344 + /* 21727 */ MCD_OPC_CheckPredicate, + 24, + 28, + 14, + 0, // Skip to: 25344 + /* 21732 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 21, + 14, + 0, // Skip to: 25344 + /* 21739 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 14, + 14, + 0, // Skip to: 25344 + /* 21746 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 7, + 14, + 0, // Skip to: 25344 + /* 21753 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 0, + 14, + 0, // Skip to: 25344 + /* 21760 */ MCD_OPC_Decode, + 179, + 7, + 143, + 1, // Opcode: MVE_VABDf16 + /* 21765 */ MCD_OPC_FilterValue, + 15, + 246, + 13, + 0, // Skip to: 25344 + /* 21770 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 21773 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 21823 + /* 21778 */ MCD_OPC_CheckPredicate, + 24, + 233, + 13, + 0, // Skip to: 25344 + /* 21783 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 226, + 13, + 0, // Skip to: 25344 + /* 21790 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 219, + 13, + 0, // Skip to: 25344 + /* 21797 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 212, + 13, + 0, // Skip to: 25344 + /* 21804 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 205, + 13, + 0, // Skip to: 25344 + /* 21811 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 198, + 13, + 0, // Skip to: 25344 + /* 21818 */ MCD_OPC_Decode, + 194, + 9, + 143, + 1, // Opcode: MVE_VMAXNMf32 + /* 21823 */ MCD_OPC_FilterValue, + 1, + 45, + 0, + 0, // Skip to: 21873 + /* 21828 */ MCD_OPC_CheckPredicate, + 24, + 183, + 13, + 0, // Skip to: 25344 + /* 21833 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 176, + 13, + 0, // Skip to: 25344 + /* 21840 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 169, + 13, + 0, // Skip to: 25344 + /* 21847 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 162, + 13, + 0, // Skip to: 25344 + /* 21854 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 155, + 13, + 0, // Skip to: 25344 + /* 21861 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 148, + 13, + 0, // Skip to: 25344 + /* 21868 */ MCD_OPC_Decode, + 193, + 9, + 143, + 1, // Opcode: MVE_VMAXNMf16 + /* 21873 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 21923 + /* 21878 */ MCD_OPC_CheckPredicate, + 24, + 133, + 13, + 0, // Skip to: 25344 + /* 21883 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 126, + 13, + 0, // Skip to: 25344 + /* 21890 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 119, + 13, + 0, // Skip to: 25344 + /* 21897 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 112, + 13, + 0, // Skip to: 25344 + /* 21904 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 105, + 13, + 0, // Skip to: 25344 + /* 21911 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 98, + 13, + 0, // Skip to: 25344 + /* 21918 */ MCD_OPC_Decode, + 220, + 9, + 143, + 1, // Opcode: MVE_VMINNMf32 + /* 21923 */ MCD_OPC_FilterValue, + 3, + 88, + 13, + 0, // Skip to: 25344 + /* 21928 */ MCD_OPC_CheckPredicate, + 24, + 83, + 13, + 0, // Skip to: 25344 + /* 21933 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 76, + 13, + 0, // Skip to: 25344 + /* 21940 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 69, + 13, + 0, // Skip to: 25344 + /* 21947 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 62, + 13, + 0, // Skip to: 25344 + /* 21954 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 55, + 13, + 0, // Skip to: 25344 + /* 21961 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 48, + 13, + 0, // Skip to: 25344 + /* 21968 */ MCD_OPC_Decode, + 219, + 9, + 143, + 1, // Opcode: MVE_VMINNMf16 + /* 21973 */ MCD_OPC_FilterValue, + 3, + 38, + 13, + 0, // Skip to: 25344 + /* 21978 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 21981 */ MCD_OPC_FilterValue, + 0, + 224, + 7, + 0, // Skip to: 24002 + /* 21986 */ MCD_OPC_ExtractField, + 6, + 7, // Inst{12-6} ... + /* 21989 */ MCD_OPC_FilterValue, + 1, + 148, + 0, + 0, // Skip to: 22142 + /* 21994 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 21997 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 22026 + /* 22002 */ MCD_OPC_CheckPredicate, + 22, + 9, + 13, + 0, // Skip to: 25344 + /* 22007 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 2, + 13, + 0, // Skip to: 25344 + /* 22014 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 251, + 12, + 0, // Skip to: 25344 + /* 22021 */ MCD_OPC_Decode, + 161, + 12, + 147, + 1, // Opcode: MVE_VREV64_8 + /* 22026 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 22055 + /* 22031 */ MCD_OPC_CheckPredicate, + 22, + 236, + 12, + 0, // Skip to: 25344 + /* 22036 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 229, + 12, + 0, // Skip to: 25344 + /* 22043 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 222, + 12, + 0, // Skip to: 25344 + /* 22050 */ MCD_OPC_Decode, + 159, + 12, + 147, + 1, // Opcode: MVE_VREV64_16 + /* 22055 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22084 + /* 22060 */ MCD_OPC_CheckPredicate, + 24, + 207, + 12, + 0, // Skip to: 25344 + /* 22065 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 200, + 12, + 0, // Skip to: 25344 + /* 22072 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 193, + 12, + 0, // Skip to: 25344 + /* 22079 */ MCD_OPC_Decode, + 153, + 8, + 147, + 1, // Opcode: MVE_VCVTs16f16a + /* 22084 */ MCD_OPC_FilterValue, + 56, + 24, + 0, + 0, // Skip to: 22113 + /* 22089 */ MCD_OPC_CheckPredicate, + 22, + 178, + 12, + 0, // Skip to: 25344 + /* 22094 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 171, + 12, + 0, // Skip to: 25344 + /* 22101 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 12, + 0, // Skip to: 25344 + /* 22108 */ MCD_OPC_Decode, + 160, + 12, + 147, + 1, // Opcode: MVE_VREV64_32 + /* 22113 */ MCD_OPC_FilterValue, + 59, + 154, + 12, + 0, // Skip to: 25344 + /* 22118 */ MCD_OPC_CheckPredicate, + 24, + 149, + 12, + 0, // Skip to: 25344 + /* 22123 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 142, + 12, + 0, // Skip to: 25344 + /* 22130 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 135, + 12, + 0, // Skip to: 25344 + /* 22137 */ MCD_OPC_Decode, + 159, + 8, + 147, + 1, // Opcode: MVE_VCVTs32f32a + /* 22142 */ MCD_OPC_FilterValue, + 3, + 119, + 0, + 0, // Skip to: 22266 + /* 22147 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22150 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 22179 + /* 22155 */ MCD_OPC_CheckPredicate, + 22, + 112, + 12, + 0, // Skip to: 25344 + /* 22160 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 105, + 12, + 0, // Skip to: 25344 + /* 22167 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 98, + 12, + 0, // Skip to: 25344 + /* 22174 */ MCD_OPC_Decode, + 158, + 12, + 147, + 1, // Opcode: MVE_VREV32_8 + /* 22179 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 22208 + /* 22184 */ MCD_OPC_CheckPredicate, + 22, + 83, + 12, + 0, // Skip to: 25344 + /* 22189 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 76, + 12, + 0, // Skip to: 25344 + /* 22196 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 69, + 12, + 0, // Skip to: 25344 + /* 22203 */ MCD_OPC_Decode, + 157, + 12, + 147, + 1, // Opcode: MVE_VREV32_16 + /* 22208 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22237 + /* 22213 */ MCD_OPC_CheckPredicate, + 24, + 54, + 12, + 0, // Skip to: 25344 + /* 22218 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 47, + 12, + 0, // Skip to: 25344 + /* 22225 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 40, + 12, + 0, // Skip to: 25344 + /* 22232 */ MCD_OPC_Decode, + 165, + 8, + 147, + 1, // Opcode: MVE_VCVTu16f16a + /* 22237 */ MCD_OPC_FilterValue, + 59, + 30, + 12, + 0, // Skip to: 25344 + /* 22242 */ MCD_OPC_CheckPredicate, + 24, + 25, + 12, + 0, // Skip to: 25344 + /* 22247 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 18, + 12, + 0, // Skip to: 25344 + /* 22254 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 11, + 12, + 0, // Skip to: 25344 + /* 22261 */ MCD_OPC_Decode, + 171, + 8, + 147, + 1, // Opcode: MVE_VCVTu32f32a + /* 22266 */ MCD_OPC_FilterValue, + 5, + 90, + 0, + 0, // Skip to: 22361 + /* 22271 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22274 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 22303 + /* 22279 */ MCD_OPC_CheckPredicate, + 22, + 244, + 11, + 0, // Skip to: 25344 + /* 22284 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 237, + 11, + 0, // Skip to: 25344 + /* 22291 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 230, + 11, + 0, // Skip to: 25344 + /* 22298 */ MCD_OPC_Decode, + 156, + 12, + 147, + 1, // Opcode: MVE_VREV16_8 + /* 22303 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22332 + /* 22308 */ MCD_OPC_CheckPredicate, + 24, + 215, + 11, + 0, // Skip to: 25344 + /* 22313 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 208, + 11, + 0, // Skip to: 25344 + /* 22320 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 201, + 11, + 0, // Skip to: 25344 + /* 22327 */ MCD_OPC_Decode, + 155, + 8, + 147, + 1, // Opcode: MVE_VCVTs16f16n + /* 22332 */ MCD_OPC_FilterValue, + 59, + 191, + 11, + 0, // Skip to: 25344 + /* 22337 */ MCD_OPC_CheckPredicate, + 24, + 186, + 11, + 0, // Skip to: 25344 + /* 22342 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 179, + 11, + 0, // Skip to: 25344 + /* 22349 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 172, + 11, + 0, // Skip to: 25344 + /* 22356 */ MCD_OPC_Decode, + 161, + 8, + 147, + 1, // Opcode: MVE_VCVTs32f32n + /* 22361 */ MCD_OPC_FilterValue, + 7, + 61, + 0, + 0, // Skip to: 22427 + /* 22366 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22369 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22398 + /* 22374 */ MCD_OPC_CheckPredicate, + 24, + 149, + 11, + 0, // Skip to: 25344 + /* 22379 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 142, + 11, + 0, // Skip to: 25344 + /* 22386 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 135, + 11, + 0, // Skip to: 25344 + /* 22393 */ MCD_OPC_Decode, + 167, + 8, + 147, + 1, // Opcode: MVE_VCVTu16f16n + /* 22398 */ MCD_OPC_FilterValue, + 59, + 125, + 11, + 0, // Skip to: 25344 + /* 22403 */ MCD_OPC_CheckPredicate, + 24, + 120, + 11, + 0, // Skip to: 25344 + /* 22408 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 113, + 11, + 0, // Skip to: 25344 + /* 22415 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 106, + 11, + 0, // Skip to: 25344 + /* 22422 */ MCD_OPC_Decode, + 173, + 8, + 147, + 1, // Opcode: MVE_VCVTu32f32n + /* 22427 */ MCD_OPC_FilterValue, + 9, + 61, + 0, + 0, // Skip to: 22493 + /* 22432 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22435 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22464 + /* 22440 */ MCD_OPC_CheckPredicate, + 24, + 83, + 11, + 0, // Skip to: 25344 + /* 22445 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 76, + 11, + 0, // Skip to: 25344 + /* 22452 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 69, + 11, + 0, // Skip to: 25344 + /* 22459 */ MCD_OPC_Decode, + 156, + 8, + 147, + 1, // Opcode: MVE_VCVTs16f16p + /* 22464 */ MCD_OPC_FilterValue, + 59, + 59, + 11, + 0, // Skip to: 25344 + /* 22469 */ MCD_OPC_CheckPredicate, + 24, + 54, + 11, + 0, // Skip to: 25344 + /* 22474 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 47, + 11, + 0, // Skip to: 25344 + /* 22481 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 40, + 11, + 0, // Skip to: 25344 + /* 22488 */ MCD_OPC_Decode, + 162, + 8, + 147, + 1, // Opcode: MVE_VCVTs32f32p + /* 22493 */ MCD_OPC_FilterValue, + 11, + 61, + 0, + 0, // Skip to: 22559 + /* 22498 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22501 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22530 + /* 22506 */ MCD_OPC_CheckPredicate, + 24, + 17, + 11, + 0, // Skip to: 25344 + /* 22511 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 10, + 11, + 0, // Skip to: 25344 + /* 22518 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 3, + 11, + 0, // Skip to: 25344 + /* 22525 */ MCD_OPC_Decode, + 168, + 8, + 147, + 1, // Opcode: MVE_VCVTu16f16p + /* 22530 */ MCD_OPC_FilterValue, + 59, + 249, + 10, + 0, // Skip to: 25344 + /* 22535 */ MCD_OPC_CheckPredicate, + 24, + 244, + 10, + 0, // Skip to: 25344 + /* 22540 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 237, + 10, + 0, // Skip to: 25344 + /* 22547 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 230, + 10, + 0, // Skip to: 25344 + /* 22554 */ MCD_OPC_Decode, + 174, + 8, + 147, + 1, // Opcode: MVE_VCVTu32f32p + /* 22559 */ MCD_OPC_FilterValue, + 13, + 148, + 0, + 0, // Skip to: 22712 + /* 22564 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22567 */ MCD_OPC_FilterValue, + 49, + 24, + 0, + 0, // Skip to: 22596 + /* 22572 */ MCD_OPC_CheckPredicate, + 22, + 207, + 10, + 0, // Skip to: 25344 + /* 22577 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 200, + 10, + 0, // Skip to: 25344 + /* 22584 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 193, + 10, + 0, // Skip to: 25344 + /* 22591 */ MCD_OPC_Decode, + 191, + 7, + 147, + 1, // Opcode: MVE_VABSs8 + /* 22596 */ MCD_OPC_FilterValue, + 53, + 24, + 0, + 0, // Skip to: 22625 + /* 22601 */ MCD_OPC_CheckPredicate, + 22, + 178, + 10, + 0, // Skip to: 25344 + /* 22606 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 171, + 10, + 0, // Skip to: 25344 + /* 22613 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 10, + 0, // Skip to: 25344 + /* 22620 */ MCD_OPC_Decode, + 189, + 7, + 147, + 1, // Opcode: MVE_VABSs16 + /* 22625 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22654 + /* 22630 */ MCD_OPC_CheckPredicate, + 24, + 149, + 10, + 0, // Skip to: 25344 + /* 22635 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 142, + 10, + 0, // Skip to: 25344 + /* 22642 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 135, + 10, + 0, // Skip to: 25344 + /* 22649 */ MCD_OPC_Decode, + 154, + 8, + 147, + 1, // Opcode: MVE_VCVTs16f16m + /* 22654 */ MCD_OPC_FilterValue, + 57, + 24, + 0, + 0, // Skip to: 22683 + /* 22659 */ MCD_OPC_CheckPredicate, + 22, + 120, + 10, + 0, // Skip to: 25344 + /* 22664 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 113, + 10, + 0, // Skip to: 25344 + /* 22671 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 106, + 10, + 0, // Skip to: 25344 + /* 22678 */ MCD_OPC_Decode, + 190, + 7, + 147, + 1, // Opcode: MVE_VABSs32 + /* 22683 */ MCD_OPC_FilterValue, + 59, + 96, + 10, + 0, // Skip to: 25344 + /* 22688 */ MCD_OPC_CheckPredicate, + 24, + 91, + 10, + 0, // Skip to: 25344 + /* 22693 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 84, + 10, + 0, // Skip to: 25344 + /* 22700 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 77, + 10, + 0, // Skip to: 25344 + /* 22707 */ MCD_OPC_Decode, + 160, + 8, + 147, + 1, // Opcode: MVE_VCVTs32f32m + /* 22712 */ MCD_OPC_FilterValue, + 15, + 148, + 0, + 0, // Skip to: 22865 + /* 22717 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22720 */ MCD_OPC_FilterValue, + 49, + 24, + 0, + 0, // Skip to: 22749 + /* 22725 */ MCD_OPC_CheckPredicate, + 22, + 54, + 10, + 0, // Skip to: 25344 + /* 22730 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 47, + 10, + 0, // Skip to: 25344 + /* 22737 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 40, + 10, + 0, // Skip to: 25344 + /* 22744 */ MCD_OPC_Decode, + 227, + 10, + 147, + 1, // Opcode: MVE_VNEGs8 + /* 22749 */ MCD_OPC_FilterValue, + 53, + 24, + 0, + 0, // Skip to: 22778 + /* 22754 */ MCD_OPC_CheckPredicate, + 22, + 25, + 10, + 0, // Skip to: 25344 + /* 22759 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 18, + 10, + 0, // Skip to: 25344 + /* 22766 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 11, + 10, + 0, // Skip to: 25344 + /* 22773 */ MCD_OPC_Decode, + 225, + 10, + 147, + 1, // Opcode: MVE_VNEGs16 + /* 22778 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22807 + /* 22783 */ MCD_OPC_CheckPredicate, + 24, + 252, + 9, + 0, // Skip to: 25344 + /* 22788 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 245, + 9, + 0, // Skip to: 25344 + /* 22795 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 238, + 9, + 0, // Skip to: 25344 + /* 22802 */ MCD_OPC_Decode, + 166, + 8, + 147, + 1, // Opcode: MVE_VCVTu16f16m + /* 22807 */ MCD_OPC_FilterValue, + 57, + 24, + 0, + 0, // Skip to: 22836 + /* 22812 */ MCD_OPC_CheckPredicate, + 22, + 223, + 9, + 0, // Skip to: 25344 + /* 22817 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 216, + 9, + 0, // Skip to: 25344 + /* 22824 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 209, + 9, + 0, // Skip to: 25344 + /* 22831 */ MCD_OPC_Decode, + 226, + 10, + 147, + 1, // Opcode: MVE_VNEGs32 + /* 22836 */ MCD_OPC_FilterValue, + 59, + 199, + 9, + 0, // Skip to: 25344 + /* 22841 */ MCD_OPC_CheckPredicate, + 24, + 194, + 9, + 0, // Skip to: 25344 + /* 22846 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 187, + 9, + 0, // Skip to: 25344 + /* 22853 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 180, + 9, + 0, // Skip to: 25344 + /* 22860 */ MCD_OPC_Decode, + 172, + 8, + 147, + 1, // Opcode: MVE_VCVTu32f32m + /* 22865 */ MCD_OPC_FilterValue, + 17, + 148, + 0, + 0, // Skip to: 23018 + /* 22870 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22873 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 22902 + /* 22878 */ MCD_OPC_CheckPredicate, + 22, + 157, + 9, + 0, // Skip to: 25344 + /* 22883 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 150, + 9, + 0, // Skip to: 25344 + /* 22890 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 143, + 9, + 0, // Skip to: 25344 + /* 22897 */ MCD_OPC_Decode, + 234, + 7, + 147, + 1, // Opcode: MVE_VCLSs8 + /* 22902 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 22931 + /* 22907 */ MCD_OPC_CheckPredicate, + 22, + 128, + 9, + 0, // Skip to: 25344 + /* 22912 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 121, + 9, + 0, // Skip to: 25344 + /* 22919 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 114, + 9, + 0, // Skip to: 25344 + /* 22926 */ MCD_OPC_Decode, + 232, + 7, + 147, + 1, // Opcode: MVE_VCLSs16 + /* 22931 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 22960 + /* 22936 */ MCD_OPC_CheckPredicate, + 24, + 99, + 9, + 0, // Skip to: 25344 + /* 22941 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 92, + 9, + 0, // Skip to: 25344 + /* 22948 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 85, + 9, + 0, // Skip to: 25344 + /* 22955 */ MCD_OPC_Decode, + 170, + 12, + 147, + 1, // Opcode: MVE_VRINTf16N + /* 22960 */ MCD_OPC_FilterValue, + 56, + 24, + 0, + 0, // Skip to: 22989 + /* 22965 */ MCD_OPC_CheckPredicate, + 22, + 70, + 9, + 0, // Skip to: 25344 + /* 22970 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 63, + 9, + 0, // Skip to: 25344 + /* 22977 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 56, + 9, + 0, // Skip to: 25344 + /* 22984 */ MCD_OPC_Decode, + 233, + 7, + 147, + 1, // Opcode: MVE_VCLSs32 + /* 22989 */ MCD_OPC_FilterValue, + 58, + 46, + 9, + 0, // Skip to: 25344 + /* 22994 */ MCD_OPC_CheckPredicate, + 24, + 41, + 9, + 0, // Skip to: 25344 + /* 22999 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 34, + 9, + 0, // Skip to: 25344 + /* 23006 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 27, + 9, + 0, // Skip to: 25344 + /* 23013 */ MCD_OPC_Decode, + 176, + 12, + 147, + 1, // Opcode: MVE_VRINTf32N + /* 23018 */ MCD_OPC_FilterValue, + 19, + 148, + 0, + 0, // Skip to: 23171 + /* 23023 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23026 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 23055 + /* 23031 */ MCD_OPC_CheckPredicate, + 22, + 4, + 9, + 0, // Skip to: 25344 + /* 23036 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 253, + 8, + 0, // Skip to: 25344 + /* 23043 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 246, + 8, + 0, // Skip to: 25344 + /* 23050 */ MCD_OPC_Decode, + 237, + 7, + 147, + 1, // Opcode: MVE_VCLZs8 + /* 23055 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 23084 + /* 23060 */ MCD_OPC_CheckPredicate, + 22, + 231, + 8, + 0, // Skip to: 25344 + /* 23065 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 224, + 8, + 0, // Skip to: 25344 + /* 23072 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 217, + 8, + 0, // Skip to: 25344 + /* 23079 */ MCD_OPC_Decode, + 235, + 7, + 147, + 1, // Opcode: MVE_VCLZs16 + /* 23084 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 23113 + /* 23089 */ MCD_OPC_CheckPredicate, + 24, + 202, + 8, + 0, // Skip to: 25344 + /* 23094 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 195, + 8, + 0, // Skip to: 25344 + /* 23101 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 188, + 8, + 0, // Skip to: 25344 + /* 23108 */ MCD_OPC_Decode, + 172, + 12, + 147, + 1, // Opcode: MVE_VRINTf16X + /* 23113 */ MCD_OPC_FilterValue, + 56, + 24, + 0, + 0, // Skip to: 23142 + /* 23118 */ MCD_OPC_CheckPredicate, + 22, + 173, + 8, + 0, // Skip to: 25344 + /* 23123 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 166, + 8, + 0, // Skip to: 25344 + /* 23130 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 159, + 8, + 0, // Skip to: 25344 + /* 23137 */ MCD_OPC_Decode, + 236, + 7, + 147, + 1, // Opcode: MVE_VCLZs32 + /* 23142 */ MCD_OPC_FilterValue, + 58, + 149, + 8, + 0, // Skip to: 25344 + /* 23147 */ MCD_OPC_CheckPredicate, + 24, + 144, + 8, + 0, // Skip to: 25344 + /* 23152 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 137, + 8, + 0, // Skip to: 25344 + /* 23159 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 130, + 8, + 0, // Skip to: 25344 + /* 23166 */ MCD_OPC_Decode, + 178, + 12, + 147, + 1, // Opcode: MVE_VRINTf32X + /* 23171 */ MCD_OPC_FilterValue, + 21, + 61, + 0, + 0, // Skip to: 23237 + /* 23176 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23179 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 23208 + /* 23184 */ MCD_OPC_CheckPredicate, + 24, + 107, + 8, + 0, // Skip to: 25344 + /* 23189 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 100, + 8, + 0, // Skip to: 25344 + /* 23196 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 93, + 8, + 0, // Skip to: 25344 + /* 23203 */ MCD_OPC_Decode, + 168, + 12, + 147, + 1, // Opcode: MVE_VRINTf16A + /* 23208 */ MCD_OPC_FilterValue, + 58, + 83, + 8, + 0, // Skip to: 25344 + /* 23213 */ MCD_OPC_CheckPredicate, + 24, + 78, + 8, + 0, // Skip to: 25344 + /* 23218 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 71, + 8, + 0, // Skip to: 25344 + /* 23225 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 64, + 8, + 0, // Skip to: 25344 + /* 23232 */ MCD_OPC_Decode, + 174, + 12, + 147, + 1, // Opcode: MVE_VRINTf32A + /* 23237 */ MCD_OPC_FilterValue, + 23, + 90, + 0, + 0, // Skip to: 23332 + /* 23242 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23245 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 23274 + /* 23250 */ MCD_OPC_CheckPredicate, + 22, + 41, + 8, + 0, // Skip to: 25344 + /* 23255 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 34, + 8, + 0, // Skip to: 25344 + /* 23262 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 27, + 8, + 0, // Skip to: 25344 + /* 23269 */ MCD_OPC_Decode, + 220, + 10, + 147, + 1, // Opcode: MVE_VMVN + /* 23274 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 23303 + /* 23279 */ MCD_OPC_CheckPredicate, + 24, + 12, + 8, + 0, // Skip to: 25344 + /* 23284 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 5, + 8, + 0, // Skip to: 25344 + /* 23291 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 254, + 7, + 0, // Skip to: 25344 + /* 23298 */ MCD_OPC_Decode, + 173, + 12, + 147, + 1, // Opcode: MVE_VRINTf16Z + /* 23303 */ MCD_OPC_FilterValue, + 58, + 244, + 7, + 0, // Skip to: 25344 + /* 23308 */ MCD_OPC_CheckPredicate, + 24, + 239, + 7, + 0, // Skip to: 25344 + /* 23313 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 232, + 7, + 0, // Skip to: 25344 + /* 23320 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 225, + 7, + 0, // Skip to: 25344 + /* 23327 */ MCD_OPC_Decode, + 179, + 12, + 147, + 1, // Opcode: MVE_VRINTf32Z + /* 23332 */ MCD_OPC_FilterValue, + 25, + 61, + 0, + 0, // Skip to: 23398 + /* 23337 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23340 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 23369 + /* 23345 */ MCD_OPC_CheckPredicate, + 24, + 202, + 7, + 0, // Skip to: 25344 + /* 23350 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 195, + 7, + 0, // Skip to: 25344 + /* 23357 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 188, + 7, + 0, // Skip to: 25344 + /* 23364 */ MCD_OPC_Decode, + 143, + 8, + 147, + 1, // Opcode: MVE_VCVTf16s16n + /* 23369 */ MCD_OPC_FilterValue, + 59, + 178, + 7, + 0, // Skip to: 25344 + /* 23374 */ MCD_OPC_CheckPredicate, + 24, + 173, + 7, + 0, // Skip to: 25344 + /* 23379 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 166, + 7, + 0, // Skip to: 25344 + /* 23386 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 159, + 7, + 0, // Skip to: 25344 + /* 23393 */ MCD_OPC_Decode, + 149, + 8, + 147, + 1, // Opcode: MVE_VCVTf32s32n + /* 23398 */ MCD_OPC_FilterValue, + 27, + 119, + 0, + 0, // Skip to: 23522 + /* 23403 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23406 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 23435 + /* 23411 */ MCD_OPC_CheckPredicate, + 24, + 136, + 7, + 0, // Skip to: 25344 + /* 23416 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 129, + 7, + 0, // Skip to: 25344 + /* 23423 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 122, + 7, + 0, // Skip to: 25344 + /* 23430 */ MCD_OPC_Decode, + 169, + 12, + 147, + 1, // Opcode: MVE_VRINTf16M + /* 23435 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 23464 + /* 23440 */ MCD_OPC_CheckPredicate, + 24, + 107, + 7, + 0, // Skip to: 25344 + /* 23445 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 100, + 7, + 0, // Skip to: 25344 + /* 23452 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 93, + 7, + 0, // Skip to: 25344 + /* 23459 */ MCD_OPC_Decode, + 145, + 8, + 147, + 1, // Opcode: MVE_VCVTf16u16n + /* 23464 */ MCD_OPC_FilterValue, + 58, + 24, + 0, + 0, // Skip to: 23493 + /* 23469 */ MCD_OPC_CheckPredicate, + 24, + 78, + 7, + 0, // Skip to: 25344 + /* 23474 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 71, + 7, + 0, // Skip to: 25344 + /* 23481 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 64, + 7, + 0, // Skip to: 25344 + /* 23488 */ MCD_OPC_Decode, + 175, + 12, + 147, + 1, // Opcode: MVE_VRINTf32M + /* 23493 */ MCD_OPC_FilterValue, + 59, + 54, + 7, + 0, // Skip to: 25344 + /* 23498 */ MCD_OPC_CheckPredicate, + 24, + 49, + 7, + 0, // Skip to: 25344 + /* 23503 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 42, + 7, + 0, // Skip to: 25344 + /* 23510 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 35, + 7, + 0, // Skip to: 25344 + /* 23517 */ MCD_OPC_Decode, + 151, + 8, + 147, + 1, // Opcode: MVE_VCVTf32u32n + /* 23522 */ MCD_OPC_FilterValue, + 29, + 206, + 0, + 0, // Skip to: 23733 + /* 23527 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23530 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 23559 + /* 23535 */ MCD_OPC_CheckPredicate, + 22, + 12, + 7, + 0, // Skip to: 25344 + /* 23540 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 5, + 7, + 0, // Skip to: 25344 + /* 23547 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 254, + 6, + 0, // Skip to: 25344 + /* 23554 */ MCD_OPC_Decode, + 131, + 11, + 147, + 1, // Opcode: MVE_VQABSs8 + /* 23559 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 23588 + /* 23564 */ MCD_OPC_CheckPredicate, + 22, + 239, + 6, + 0, // Skip to: 25344 + /* 23569 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 232, + 6, + 0, // Skip to: 25344 + /* 23576 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 225, + 6, + 0, // Skip to: 25344 + /* 23583 */ MCD_OPC_Decode, + 129, + 11, + 147, + 1, // Opcode: MVE_VQABSs16 + /* 23588 */ MCD_OPC_FilterValue, + 53, + 24, + 0, + 0, // Skip to: 23617 + /* 23593 */ MCD_OPC_CheckPredicate, + 24, + 210, + 6, + 0, // Skip to: 25344 + /* 23598 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 203, + 6, + 0, // Skip to: 25344 + /* 23605 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 196, + 6, + 0, // Skip to: 25344 + /* 23612 */ MCD_OPC_Decode, + 187, + 7, + 147, + 1, // Opcode: MVE_VABSf16 + /* 23617 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 23646 + /* 23622 */ MCD_OPC_CheckPredicate, + 24, + 181, + 6, + 0, // Skip to: 25344 + /* 23627 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 174, + 6, + 0, // Skip to: 25344 + /* 23634 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 167, + 6, + 0, // Skip to: 25344 + /* 23641 */ MCD_OPC_Decode, + 157, + 8, + 147, + 1, // Opcode: MVE_VCVTs16f16z + /* 23646 */ MCD_OPC_FilterValue, + 56, + 24, + 0, + 0, // Skip to: 23675 + /* 23651 */ MCD_OPC_CheckPredicate, + 22, + 152, + 6, + 0, // Skip to: 25344 + /* 23656 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 145, + 6, + 0, // Skip to: 25344 + /* 23663 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 138, + 6, + 0, // Skip to: 25344 + /* 23670 */ MCD_OPC_Decode, + 130, + 11, + 147, + 1, // Opcode: MVE_VQABSs32 + /* 23675 */ MCD_OPC_FilterValue, + 57, + 24, + 0, + 0, // Skip to: 23704 + /* 23680 */ MCD_OPC_CheckPredicate, + 24, + 123, + 6, + 0, // Skip to: 25344 + /* 23685 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 116, + 6, + 0, // Skip to: 25344 + /* 23692 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 109, + 6, + 0, // Skip to: 25344 + /* 23699 */ MCD_OPC_Decode, + 188, + 7, + 147, + 1, // Opcode: MVE_VABSf32 + /* 23704 */ MCD_OPC_FilterValue, + 59, + 99, + 6, + 0, // Skip to: 25344 + /* 23709 */ MCD_OPC_CheckPredicate, + 24, + 94, + 6, + 0, // Skip to: 25344 + /* 23714 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 87, + 6, + 0, // Skip to: 25344 + /* 23721 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 80, + 6, + 0, // Skip to: 25344 + /* 23728 */ MCD_OPC_Decode, + 163, + 8, + 147, + 1, // Opcode: MVE_VCVTs32f32z + /* 23733 */ MCD_OPC_FilterValue, + 31, + 70, + 6, + 0, // Skip to: 25344 + /* 23738 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23741 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 23770 + /* 23746 */ MCD_OPC_CheckPredicate, + 22, + 57, + 6, + 0, // Skip to: 25344 + /* 23751 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 50, + 6, + 0, // Skip to: 25344 + /* 23758 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 43, + 6, + 0, // Skip to: 25344 + /* 23765 */ MCD_OPC_Decode, + 190, + 11, + 147, + 1, // Opcode: MVE_VQNEGs8 + /* 23770 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 23799 + /* 23775 */ MCD_OPC_CheckPredicate, + 22, + 28, + 6, + 0, // Skip to: 25344 + /* 23780 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 21, + 6, + 0, // Skip to: 25344 + /* 23787 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 14, + 6, + 0, // Skip to: 25344 + /* 23794 */ MCD_OPC_Decode, + 188, + 11, + 147, + 1, // Opcode: MVE_VQNEGs16 + /* 23799 */ MCD_OPC_FilterValue, + 53, + 24, + 0, + 0, // Skip to: 23828 + /* 23804 */ MCD_OPC_CheckPredicate, + 24, + 255, + 5, + 0, // Skip to: 25344 + /* 23809 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 248, + 5, + 0, // Skip to: 25344 + /* 23816 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 241, + 5, + 0, // Skip to: 25344 + /* 23823 */ MCD_OPC_Decode, + 223, + 10, + 147, + 1, // Opcode: MVE_VNEGf16 + /* 23828 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 23857 + /* 23833 */ MCD_OPC_CheckPredicate, + 24, + 226, + 5, + 0, // Skip to: 25344 + /* 23838 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 219, + 5, + 0, // Skip to: 25344 + /* 23845 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 212, + 5, + 0, // Skip to: 25344 + /* 23852 */ MCD_OPC_Decode, + 171, + 12, + 147, + 1, // Opcode: MVE_VRINTf16P + /* 23857 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 23886 + /* 23862 */ MCD_OPC_CheckPredicate, + 24, + 197, + 5, + 0, // Skip to: 25344 + /* 23867 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 190, + 5, + 0, // Skip to: 25344 + /* 23874 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 183, + 5, + 0, // Skip to: 25344 + /* 23881 */ MCD_OPC_Decode, + 169, + 8, + 147, + 1, // Opcode: MVE_VCVTu16f16z + /* 23886 */ MCD_OPC_FilterValue, + 56, + 24, + 0, + 0, // Skip to: 23915 + /* 23891 */ MCD_OPC_CheckPredicate, + 22, + 168, + 5, + 0, // Skip to: 25344 + /* 23896 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 161, + 5, + 0, // Skip to: 25344 + /* 23903 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 154, + 5, + 0, // Skip to: 25344 + /* 23910 */ MCD_OPC_Decode, + 189, + 11, + 147, + 1, // Opcode: MVE_VQNEGs32 + /* 23915 */ MCD_OPC_FilterValue, + 57, + 24, + 0, + 0, // Skip to: 23944 + /* 23920 */ MCD_OPC_CheckPredicate, + 24, + 139, + 5, + 0, // Skip to: 25344 + /* 23925 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 132, + 5, + 0, // Skip to: 25344 + /* 23932 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 125, + 5, + 0, // Skip to: 25344 + /* 23939 */ MCD_OPC_Decode, + 224, + 10, + 147, + 1, // Opcode: MVE_VNEGf32 + /* 23944 */ MCD_OPC_FilterValue, + 58, + 24, + 0, + 0, // Skip to: 23973 + /* 23949 */ MCD_OPC_CheckPredicate, + 24, + 110, + 5, + 0, // Skip to: 25344 + /* 23954 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 103, + 5, + 0, // Skip to: 25344 + /* 23961 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 96, + 5, + 0, // Skip to: 25344 + /* 23968 */ MCD_OPC_Decode, + 177, + 12, + 147, + 1, // Opcode: MVE_VRINTf32P + /* 23973 */ MCD_OPC_FilterValue, + 59, + 86, + 5, + 0, // Skip to: 25344 + /* 23978 */ MCD_OPC_CheckPredicate, + 24, + 81, + 5, + 0, // Skip to: 25344 + /* 23983 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 74, + 5, + 0, // Skip to: 25344 + /* 23990 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 67, + 5, + 0, // Skip to: 25344 + /* 23997 */ MCD_OPC_Decode, + 175, + 8, + 147, + 1, // Opcode: MVE_VCVTu32f32z + /* 24002 */ MCD_OPC_FilterValue, + 1, + 57, + 5, + 0, // Skip to: 25344 + /* 24007 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 24010 */ MCD_OPC_FilterValue, + 0, + 51, + 3, + 0, // Skip to: 24834 + /* 24015 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 24018 */ MCD_OPC_FilterValue, + 0, + 25, + 2, + 0, // Skip to: 24560 + /* 24023 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 24026 */ MCD_OPC_FilterValue, + 0, + 255, + 0, + 0, // Skip to: 24286 + /* 24031 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 24034 */ MCD_OPC_FilterValue, + 2, + 129, + 0, + 0, // Skip to: 24168 + /* 24039 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 24042 */ MCD_OPC_FilterValue, + 0, + 17, + 5, + 0, // Skip to: 25344 + /* 24047 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 24050 */ MCD_OPC_FilterValue, + 7, + 9, + 5, + 0, // Skip to: 25344 + /* 24055 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 24058 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 24073 + /* 24063 */ MCD_OPC_CheckPredicate, + 22, + 20, + 0, + 0, // Skip to: 24088 + /* 24068 */ MCD_OPC_Decode, + 187, + 10, + 190, + 1, // Opcode: MVE_VMOVimmi8 + /* 24073 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 24088 + /* 24078 */ MCD_OPC_CheckPredicate, + 22, + 5, + 0, + 0, // Skip to: 24088 + /* 24083 */ MCD_OPC_Decode, + 183, + 10, + 190, + 1, // Opcode: MVE_VMOVimmf32 + /* 24088 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 24091 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 24113 + /* 24096 */ MCD_OPC_CheckPredicate, + 22, + 57, + 0, + 0, // Skip to: 24158 + /* 24101 */ MCD_OPC_CheckField, + 10, + 2, + 2, + 50, + 0, + 0, // Skip to: 24158 + /* 24108 */ MCD_OPC_Decode, + 184, + 10, + 190, + 1, // Opcode: MVE_VMOVimmi16 + /* 24113 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 24158 + /* 24118 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 24121 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 24136 + /* 24126 */ MCD_OPC_CheckPredicate, + 22, + 27, + 0, + 0, // Skip to: 24158 + /* 24131 */ MCD_OPC_Decode, + 231, + 10, + 191, + 1, // Opcode: MVE_VORRimmi32 + /* 24136 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 24158 + /* 24141 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 24158 + /* 24146 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 5, + 0, + 0, // Skip to: 24158 + /* 24153 */ MCD_OPC_Decode, + 230, + 10, + 192, + 1, // Opcode: MVE_VORRimmi16 + /* 24158 */ MCD_OPC_CheckPredicate, + 22, + 157, + 4, + 0, // Skip to: 25344 + /* 24163 */ MCD_OPC_Decode, + 185, + 10, + 190, + 1, // Opcode: MVE_VMOVimmi32 + /* 24168 */ MCD_OPC_FilterValue, + 3, + 147, + 4, + 0, // Skip to: 25344 + /* 24173 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 24176 */ MCD_OPC_FilterValue, + 0, + 139, + 4, + 0, // Skip to: 25344 + /* 24181 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 24184 */ MCD_OPC_FilterValue, + 7, + 131, + 4, + 0, // Skip to: 25344 + /* 24189 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 24206 + /* 24194 */ MCD_OPC_CheckField, + 8, + 4, + 14, + 5, + 0, + 0, // Skip to: 24206 + /* 24201 */ MCD_OPC_Decode, + 186, + 10, + 190, + 1, // Opcode: MVE_VMOVimmi64 + /* 24206 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 24209 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 24231 + /* 24214 */ MCD_OPC_CheckPredicate, + 22, + 57, + 0, + 0, // Skip to: 24276 + /* 24219 */ MCD_OPC_CheckField, + 10, + 2, + 2, + 50, + 0, + 0, // Skip to: 24276 + /* 24226 */ MCD_OPC_Decode, + 221, + 10, + 190, + 1, // Opcode: MVE_VMVNimmi16 + /* 24231 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 24276 + /* 24236 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 24239 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 24254 + /* 24244 */ MCD_OPC_CheckPredicate, + 22, + 27, + 0, + 0, // Skip to: 24276 + /* 24249 */ MCD_OPC_Decode, + 223, + 7, + 191, + 1, // Opcode: MVE_VBICimmi32 + /* 24254 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 24276 + /* 24259 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 24276 + /* 24264 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 5, + 0, + 0, // Skip to: 24276 + /* 24271 */ MCD_OPC_Decode, + 222, + 7, + 192, + 1, // Opcode: MVE_VBICimmi16 + /* 24276 */ MCD_OPC_CheckPredicate, + 22, + 39, + 4, + 0, // Skip to: 25344 + /* 24281 */ MCD_OPC_Decode, + 222, + 10, + 190, + 1, // Opcode: MVE_VMVNimmi32 + /* 24286 */ MCD_OPC_FilterValue, + 1, + 29, + 4, + 0, // Skip to: 25344 + /* 24291 */ MCD_OPC_ExtractField, + 6, + 7, // Inst{12-6} ... + /* 24294 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 24346 + /* 24299 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24302 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24324 + /* 24307 */ MCD_OPC_CheckPredicate, + 22, + 8, + 4, + 0, // Skip to: 25344 + /* 24312 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 1, + 4, + 0, // Skip to: 25344 + /* 24319 */ MCD_OPC_Decode, + 130, + 13, + 193, + 1, // Opcode: MVE_VSHR_imms8 + /* 24324 */ MCD_OPC_FilterValue, + 15, + 247, + 3, + 0, // Skip to: 25344 + /* 24329 */ MCD_OPC_CheckPredicate, + 22, + 242, + 3, + 0, // Skip to: 25344 + /* 24334 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 235, + 3, + 0, // Skip to: 25344 + /* 24341 */ MCD_OPC_Decode, + 133, + 13, + 193, + 1, // Opcode: MVE_VSHR_immu8 + /* 24346 */ MCD_OPC_FilterValue, + 9, + 47, + 0, + 0, // Skip to: 24398 + /* 24351 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24354 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24376 + /* 24359 */ MCD_OPC_CheckPredicate, + 22, + 212, + 3, + 0, // Skip to: 25344 + /* 24364 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 205, + 3, + 0, // Skip to: 25344 + /* 24371 */ MCD_OPC_Decode, + 214, + 12, + 193, + 1, // Opcode: MVE_VRSHR_imms8 + /* 24376 */ MCD_OPC_FilterValue, + 15, + 195, + 3, + 0, // Skip to: 25344 + /* 24381 */ MCD_OPC_CheckPredicate, + 22, + 190, + 3, + 0, // Skip to: 25344 + /* 24386 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 183, + 3, + 0, // Skip to: 25344 + /* 24393 */ MCD_OPC_Decode, + 217, + 12, + 193, + 1, // Opcode: MVE_VRSHR_immu8 + /* 24398 */ MCD_OPC_FilterValue, + 17, + 24, + 0, + 0, // Skip to: 24427 + /* 24403 */ MCD_OPC_CheckPredicate, + 22, + 168, + 3, + 0, // Skip to: 25344 + /* 24408 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 161, + 3, + 0, // Skip to: 25344 + /* 24415 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 154, + 3, + 0, // Skip to: 25344 + /* 24422 */ MCD_OPC_Decode, + 139, + 13, + 184, + 1, // Opcode: MVE_VSRIimm8 + /* 24427 */ MCD_OPC_FilterValue, + 21, + 47, + 0, + 0, // Skip to: 24479 + /* 24432 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24435 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24457 + /* 24440 */ MCD_OPC_CheckPredicate, + 22, + 131, + 3, + 0, // Skip to: 25344 + /* 24445 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 124, + 3, + 0, // Skip to: 25344 + /* 24452 */ MCD_OPC_Decode, + 245, + 12, + 186, + 1, // Opcode: MVE_VSHL_immi8 + /* 24457 */ MCD_OPC_FilterValue, + 15, + 114, + 3, + 0, // Skip to: 25344 + /* 24462 */ MCD_OPC_CheckPredicate, + 22, + 109, + 3, + 0, // Skip to: 25344 + /* 24467 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 102, + 3, + 0, // Skip to: 25344 + /* 24474 */ MCD_OPC_Decode, + 136, + 13, + 194, + 1, // Opcode: MVE_VSLIimm8 + /* 24479 */ MCD_OPC_FilterValue, + 25, + 24, + 0, + 0, // Skip to: 24508 + /* 24484 */ MCD_OPC_CheckPredicate, + 22, + 87, + 3, + 0, // Skip to: 25344 + /* 24489 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 80, + 3, + 0, // Skip to: 25344 + /* 24496 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 73, + 3, + 0, // Skip to: 25344 + /* 24503 */ MCD_OPC_Decode, + 241, + 11, + 186, + 1, // Opcode: MVE_VQSHLU_imms8 + /* 24508 */ MCD_OPC_FilterValue, + 29, + 63, + 3, + 0, // Skip to: 25344 + /* 24513 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24516 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24538 + /* 24521 */ MCD_OPC_CheckPredicate, + 22, + 50, + 3, + 0, // Skip to: 25344 + /* 24526 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 43, + 3, + 0, // Skip to: 25344 + /* 24533 */ MCD_OPC_Decode, + 128, + 12, + 186, + 1, // Opcode: MVE_VQSHLimms8 + /* 24538 */ MCD_OPC_FilterValue, + 15, + 33, + 3, + 0, // Skip to: 25344 + /* 24543 */ MCD_OPC_CheckPredicate, + 22, + 28, + 3, + 0, // Skip to: 25344 + /* 24548 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 21, + 3, + 0, // Skip to: 25344 + /* 24555 */ MCD_OPC_Decode, + 131, + 12, + 186, + 1, // Opcode: MVE_VQSHLimmu8 + /* 24560 */ MCD_OPC_FilterValue, + 1, + 11, + 3, + 0, // Skip to: 25344 + /* 24565 */ MCD_OPC_ExtractField, + 6, + 7, // Inst{12-6} ... + /* 24568 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 24620 + /* 24573 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24576 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24598 + /* 24581 */ MCD_OPC_CheckPredicate, + 22, + 246, + 2, + 0, // Skip to: 25344 + /* 24586 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 239, + 2, + 0, // Skip to: 25344 + /* 24593 */ MCD_OPC_Decode, + 128, + 13, + 195, + 1, // Opcode: MVE_VSHR_imms16 + /* 24598 */ MCD_OPC_FilterValue, + 15, + 229, + 2, + 0, // Skip to: 25344 + /* 24603 */ MCD_OPC_CheckPredicate, + 22, + 224, + 2, + 0, // Skip to: 25344 + /* 24608 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 217, + 2, + 0, // Skip to: 25344 + /* 24615 */ MCD_OPC_Decode, + 131, + 13, + 195, + 1, // Opcode: MVE_VSHR_immu16 + /* 24620 */ MCD_OPC_FilterValue, + 9, + 47, + 0, + 0, // Skip to: 24672 + /* 24625 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24628 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24650 + /* 24633 */ MCD_OPC_CheckPredicate, + 22, + 194, + 2, + 0, // Skip to: 25344 + /* 24638 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 187, + 2, + 0, // Skip to: 25344 + /* 24645 */ MCD_OPC_Decode, + 212, + 12, + 195, + 1, // Opcode: MVE_VRSHR_imms16 + /* 24650 */ MCD_OPC_FilterValue, + 15, + 177, + 2, + 0, // Skip to: 25344 + /* 24655 */ MCD_OPC_CheckPredicate, + 22, + 172, + 2, + 0, // Skip to: 25344 + /* 24660 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 165, + 2, + 0, // Skip to: 25344 + /* 24667 */ MCD_OPC_Decode, + 215, + 12, + 195, + 1, // Opcode: MVE_VRSHR_immu16 + /* 24672 */ MCD_OPC_FilterValue, + 17, + 24, + 0, + 0, // Skip to: 24701 + /* 24677 */ MCD_OPC_CheckPredicate, + 22, + 150, + 2, + 0, // Skip to: 25344 + /* 24682 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 143, + 2, + 0, // Skip to: 25344 + /* 24689 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 136, + 2, + 0, // Skip to: 25344 + /* 24696 */ MCD_OPC_Decode, + 137, + 13, + 185, + 1, // Opcode: MVE_VSRIimm16 + /* 24701 */ MCD_OPC_FilterValue, + 21, + 47, + 0, + 0, // Skip to: 24753 + /* 24706 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24709 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24731 + /* 24714 */ MCD_OPC_CheckPredicate, + 22, + 113, + 2, + 0, // Skip to: 25344 + /* 24719 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 106, + 2, + 0, // Skip to: 25344 + /* 24726 */ MCD_OPC_Decode, + 243, + 12, + 187, + 1, // Opcode: MVE_VSHL_immi16 + /* 24731 */ MCD_OPC_FilterValue, + 15, + 96, + 2, + 0, // Skip to: 25344 + /* 24736 */ MCD_OPC_CheckPredicate, + 22, + 91, + 2, + 0, // Skip to: 25344 + /* 24741 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 84, + 2, + 0, // Skip to: 25344 + /* 24748 */ MCD_OPC_Decode, + 134, + 13, + 196, + 1, // Opcode: MVE_VSLIimm16 + /* 24753 */ MCD_OPC_FilterValue, + 25, + 24, + 0, + 0, // Skip to: 24782 + /* 24758 */ MCD_OPC_CheckPredicate, + 22, + 69, + 2, + 0, // Skip to: 25344 + /* 24763 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 62, + 2, + 0, // Skip to: 25344 + /* 24770 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 55, + 2, + 0, // Skip to: 25344 + /* 24777 */ MCD_OPC_Decode, + 239, + 11, + 187, + 1, // Opcode: MVE_VQSHLU_imms16 + /* 24782 */ MCD_OPC_FilterValue, + 29, + 45, + 2, + 0, // Skip to: 25344 + /* 24787 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24790 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24812 + /* 24795 */ MCD_OPC_CheckPredicate, + 22, + 32, + 2, + 0, // Skip to: 25344 + /* 24800 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 25, + 2, + 0, // Skip to: 25344 + /* 24807 */ MCD_OPC_Decode, + 254, + 11, + 187, + 1, // Opcode: MVE_VQSHLimms16 + /* 24812 */ MCD_OPC_FilterValue, + 15, + 15, + 2, + 0, // Skip to: 25344 + /* 24817 */ MCD_OPC_CheckPredicate, + 22, + 10, + 2, + 0, // Skip to: 25344 + /* 24822 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 3, + 2, + 0, // Skip to: 25344 + /* 24829 */ MCD_OPC_Decode, + 129, + 12, + 187, + 1, // Opcode: MVE_VQSHLimmu16 + /* 24834 */ MCD_OPC_FilterValue, + 1, + 249, + 1, + 0, // Skip to: 25344 + /* 24839 */ MCD_OPC_ExtractField, + 6, + 7, // Inst{12-6} ... + /* 24842 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 24894 + /* 24847 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24850 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24872 + /* 24855 */ MCD_OPC_CheckPredicate, + 22, + 228, + 1, + 0, // Skip to: 25344 + /* 24860 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 221, + 1, + 0, // Skip to: 25344 + /* 24867 */ MCD_OPC_Decode, + 129, + 13, + 197, + 1, // Opcode: MVE_VSHR_imms32 + /* 24872 */ MCD_OPC_FilterValue, + 15, + 211, + 1, + 0, // Skip to: 25344 + /* 24877 */ MCD_OPC_CheckPredicate, + 22, + 206, + 1, + 0, // Skip to: 25344 + /* 24882 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 199, + 1, + 0, // Skip to: 25344 + /* 24889 */ MCD_OPC_Decode, + 132, + 13, + 197, + 1, // Opcode: MVE_VSHR_immu32 + /* 24894 */ MCD_OPC_FilterValue, + 9, + 47, + 0, + 0, // Skip to: 24946 + /* 24899 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24902 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24924 + /* 24907 */ MCD_OPC_CheckPredicate, + 22, + 176, + 1, + 0, // Skip to: 25344 + /* 24912 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 169, + 1, + 0, // Skip to: 25344 + /* 24919 */ MCD_OPC_Decode, + 213, + 12, + 197, + 1, // Opcode: MVE_VRSHR_imms32 + /* 24924 */ MCD_OPC_FilterValue, + 15, + 159, + 1, + 0, // Skip to: 25344 + /* 24929 */ MCD_OPC_CheckPredicate, + 22, + 154, + 1, + 0, // Skip to: 25344 + /* 24934 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 147, + 1, + 0, // Skip to: 25344 + /* 24941 */ MCD_OPC_Decode, + 216, + 12, + 197, + 1, // Opcode: MVE_VRSHR_immu32 + /* 24946 */ MCD_OPC_FilterValue, + 17, + 24, + 0, + 0, // Skip to: 24975 + /* 24951 */ MCD_OPC_CheckPredicate, + 22, + 132, + 1, + 0, // Skip to: 25344 + /* 24956 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 125, + 1, + 0, // Skip to: 25344 + /* 24963 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 118, + 1, + 0, // Skip to: 25344 + /* 24970 */ MCD_OPC_Decode, + 138, + 13, + 198, + 1, // Opcode: MVE_VSRIimm32 + /* 24975 */ MCD_OPC_FilterValue, + 21, + 47, + 0, + 0, // Skip to: 25027 + /* 24980 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24983 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 25005 + /* 24988 */ MCD_OPC_CheckPredicate, + 22, + 95, + 1, + 0, // Skip to: 25344 + /* 24993 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 88, + 1, + 0, // Skip to: 25344 + /* 25000 */ MCD_OPC_Decode, + 244, + 12, + 199, + 1, // Opcode: MVE_VSHL_immi32 + /* 25005 */ MCD_OPC_FilterValue, + 15, + 78, + 1, + 0, // Skip to: 25344 + /* 25010 */ MCD_OPC_CheckPredicate, + 22, + 73, + 1, + 0, // Skip to: 25344 + /* 25015 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 66, + 1, + 0, // Skip to: 25344 + /* 25022 */ MCD_OPC_Decode, + 135, + 13, + 200, + 1, // Opcode: MVE_VSLIimm32 + /* 25027 */ MCD_OPC_FilterValue, + 25, + 24, + 0, + 0, // Skip to: 25056 + /* 25032 */ MCD_OPC_CheckPredicate, + 22, + 51, + 1, + 0, // Skip to: 25344 + /* 25037 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 44, + 1, + 0, // Skip to: 25344 + /* 25044 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 37, + 1, + 0, // Skip to: 25344 + /* 25051 */ MCD_OPC_Decode, + 240, + 11, + 199, + 1, // Opcode: MVE_VQSHLU_imms32 + /* 25056 */ MCD_OPC_FilterValue, + 29, + 47, + 0, + 0, // Skip to: 25108 + /* 25061 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 25064 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 25086 + /* 25069 */ MCD_OPC_CheckPredicate, + 22, + 14, + 1, + 0, // Skip to: 25344 + /* 25074 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 7, + 1, + 0, // Skip to: 25344 + /* 25081 */ MCD_OPC_Decode, + 255, + 11, + 199, + 1, // Opcode: MVE_VQSHLimms32 + /* 25086 */ MCD_OPC_FilterValue, + 15, + 253, + 0, + 0, // Skip to: 25344 + /* 25091 */ MCD_OPC_CheckPredicate, + 22, + 248, + 0, + 0, // Skip to: 25344 + /* 25096 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 241, + 0, + 0, // Skip to: 25344 + /* 25103 */ MCD_OPC_Decode, + 130, + 12, + 199, + 1, // Opcode: MVE_VQSHLimmu32 + /* 25108 */ MCD_OPC_FilterValue, + 49, + 61, + 0, + 0, // Skip to: 25174 + /* 25113 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 25116 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 25145 + /* 25121 */ MCD_OPC_CheckPredicate, + 24, + 218, + 0, + 0, // Skip to: 25344 + /* 25126 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 211, + 0, + 0, // Skip to: 25344 + /* 25133 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 204, + 0, + 0, // Skip to: 25344 + /* 25140 */ MCD_OPC_Decode, + 142, + 8, + 201, + 1, // Opcode: MVE_VCVTf16s16_fix + /* 25145 */ MCD_OPC_FilterValue, + 15, + 194, + 0, + 0, // Skip to: 25344 + /* 25150 */ MCD_OPC_CheckPredicate, + 24, + 189, + 0, + 0, // Skip to: 25344 + /* 25155 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 182, + 0, + 0, // Skip to: 25344 + /* 25162 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 175, + 0, + 0, // Skip to: 25344 + /* 25169 */ MCD_OPC_Decode, + 144, + 8, + 201, + 1, // Opcode: MVE_VCVTf16u16_fix + /* 25174 */ MCD_OPC_FilterValue, + 53, + 61, + 0, + 0, // Skip to: 25240 + /* 25179 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 25182 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 25211 + /* 25187 */ MCD_OPC_CheckPredicate, + 24, + 152, + 0, + 0, // Skip to: 25344 + /* 25192 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 145, + 0, + 0, // Skip to: 25344 + /* 25199 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 138, + 0, + 0, // Skip to: 25344 + /* 25206 */ MCD_OPC_Decode, + 152, + 8, + 201, + 1, // Opcode: MVE_VCVTs16f16_fix + /* 25211 */ MCD_OPC_FilterValue, + 15, + 128, + 0, + 0, // Skip to: 25344 + /* 25216 */ MCD_OPC_CheckPredicate, + 24, + 123, + 0, + 0, // Skip to: 25344 + /* 25221 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 116, + 0, + 0, // Skip to: 25344 + /* 25228 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 109, + 0, + 0, // Skip to: 25344 + /* 25235 */ MCD_OPC_Decode, + 164, + 8, + 201, + 1, // Opcode: MVE_VCVTu16f16_fix + /* 25240 */ MCD_OPC_FilterValue, + 57, + 47, + 0, + 0, // Skip to: 25292 + /* 25245 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 25248 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 25270 + /* 25253 */ MCD_OPC_CheckPredicate, + 24, + 86, + 0, + 0, // Skip to: 25344 + /* 25258 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 79, + 0, + 0, // Skip to: 25344 + /* 25265 */ MCD_OPC_Decode, + 148, + 8, + 201, + 1, // Opcode: MVE_VCVTf32s32_fix + /* 25270 */ MCD_OPC_FilterValue, + 15, + 69, + 0, + 0, // Skip to: 25344 + /* 25275 */ MCD_OPC_CheckPredicate, + 24, + 64, + 0, + 0, // Skip to: 25344 + /* 25280 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 57, + 0, + 0, // Skip to: 25344 + /* 25287 */ MCD_OPC_Decode, + 150, + 8, + 201, + 1, // Opcode: MVE_VCVTf32u32_fix + /* 25292 */ MCD_OPC_FilterValue, + 61, + 47, + 0, + 0, // Skip to: 25344 + /* 25297 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 25300 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 25322 + /* 25305 */ MCD_OPC_CheckPredicate, + 24, + 34, + 0, + 0, // Skip to: 25344 + /* 25310 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 27, + 0, + 0, // Skip to: 25344 + /* 25317 */ MCD_OPC_Decode, + 158, + 8, + 201, + 1, // Opcode: MVE_VCVTs32f32_fix + /* 25322 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 25344 + /* 25327 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 25344 + /* 25332 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 5, + 0, + 0, // Skip to: 25344 + /* 25339 */ MCD_OPC_Decode, + 170, + 8, + 201, + 1, // Opcode: MVE_VCVTu32f32_fix + /* 25344 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNEONData32[] = { + /* 0 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 198, + 41, + 0, // Skip to: 10702 + /* 8 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 148, + 6, + 0, // Skip to: 1700 + /* 16 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 127, + 0, + 0, // Skip to: 151 + /* 24 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 27 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 66 + /* 33 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 36 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51 + /* 41 */ MCD_OPC_CheckPredicate, + 26, + 241, + 74, + 0, // Skip to: 19231 + /* 46 */ MCD_OPC_Decode, + 242, + 18, + 202, + 1, // Opcode: VHADDsv8i8 + /* 51 */ MCD_OPC_FilterValue, + 1, + 231, + 74, + 0, // Skip to: 19231 + /* 56 */ MCD_OPC_CheckPredicate, + 26, + 226, + 74, + 0, // Skip to: 19231 + /* 61 */ MCD_OPC_Decode, + 237, + 18, + 203, + 1, // Opcode: VHADDsv16i8 + /* 66 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 89 + /* 72 */ MCD_OPC_CheckPredicate, + 26, + 210, + 74, + 0, // Skip to: 19231 + /* 77 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 203, + 74, + 0, // Skip to: 19231 + /* 84 */ MCD_OPC_Decode, + 157, + 16, + 204, + 1, // Opcode: VADDLsv8i16 + /* 89 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 128 + /* 95 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 98 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 113 + /* 103 */ MCD_OPC_CheckPredicate, + 26, + 179, + 74, + 0, // Skip to: 19231 + /* 108 */ MCD_OPC_Decode, + 248, + 18, + 202, + 1, // Opcode: VHADDuv8i8 + /* 113 */ MCD_OPC_FilterValue, + 1, + 169, + 74, + 0, // Skip to: 19231 + /* 118 */ MCD_OPC_CheckPredicate, + 26, + 164, + 74, + 0, // Skip to: 19231 + /* 123 */ MCD_OPC_Decode, + 243, + 18, + 203, + 1, // Opcode: VHADDuv16i8 + /* 128 */ MCD_OPC_FilterValue, + 231, + 3, + 153, + 74, + 0, // Skip to: 19231 + /* 134 */ MCD_OPC_CheckPredicate, + 26, + 148, + 74, + 0, // Skip to: 19231 + /* 139 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 141, + 74, + 0, // Skip to: 19231 + /* 146 */ MCD_OPC_Decode, + 160, + 16, + 204, + 1, // Opcode: VADDLuv8i16 + /* 151 */ MCD_OPC_FilterValue, + 1, + 127, + 0, + 0, // Skip to: 283 + /* 156 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 159 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 198 + /* 165 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 168 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 183 + /* 173 */ MCD_OPC_CheckPredicate, + 26, + 109, + 74, + 0, // Skip to: 19231 + /* 178 */ MCD_OPC_Decode, + 222, + 25, + 202, + 1, // Opcode: VRHADDsv8i8 + /* 183 */ MCD_OPC_FilterValue, + 1, + 99, + 74, + 0, // Skip to: 19231 + /* 188 */ MCD_OPC_CheckPredicate, + 26, + 94, + 74, + 0, // Skip to: 19231 + /* 193 */ MCD_OPC_Decode, + 217, + 25, + 203, + 1, // Opcode: VRHADDsv16i8 + /* 198 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 221 + /* 204 */ MCD_OPC_CheckPredicate, + 26, + 78, + 74, + 0, // Skip to: 19231 + /* 209 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 71, + 74, + 0, // Skip to: 19231 + /* 216 */ MCD_OPC_Decode, + 164, + 16, + 205, + 1, // Opcode: VADDWsv8i16 + /* 221 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 260 + /* 227 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 230 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 245 + /* 235 */ MCD_OPC_CheckPredicate, + 26, + 47, + 74, + 0, // Skip to: 19231 + /* 240 */ MCD_OPC_Decode, + 228, + 25, + 202, + 1, // Opcode: VRHADDuv8i8 + /* 245 */ MCD_OPC_FilterValue, + 1, + 37, + 74, + 0, // Skip to: 19231 + /* 250 */ MCD_OPC_CheckPredicate, + 26, + 32, + 74, + 0, // Skip to: 19231 + /* 255 */ MCD_OPC_Decode, + 223, + 25, + 203, + 1, // Opcode: VRHADDuv16i8 + /* 260 */ MCD_OPC_FilterValue, + 231, + 3, + 21, + 74, + 0, // Skip to: 19231 + /* 266 */ MCD_OPC_CheckPredicate, + 26, + 16, + 74, + 0, // Skip to: 19231 + /* 271 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 9, + 74, + 0, // Skip to: 19231 + /* 278 */ MCD_OPC_Decode, + 167, + 16, + 205, + 1, // Opcode: VADDWuv8i16 + /* 283 */ MCD_OPC_FilterValue, + 2, + 127, + 0, + 0, // Skip to: 415 + /* 288 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 291 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 330 + /* 297 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 300 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 315 + /* 305 */ MCD_OPC_CheckPredicate, + 26, + 233, + 73, + 0, // Skip to: 19231 + /* 310 */ MCD_OPC_Decode, + 254, + 18, + 202, + 1, // Opcode: VHSUBsv8i8 + /* 315 */ MCD_OPC_FilterValue, + 1, + 223, + 73, + 0, // Skip to: 19231 + /* 320 */ MCD_OPC_CheckPredicate, + 26, + 218, + 73, + 0, // Skip to: 19231 + /* 325 */ MCD_OPC_Decode, + 249, + 18, + 203, + 1, // Opcode: VHSUBsv16i8 + /* 330 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 353 + /* 336 */ MCD_OPC_CheckPredicate, + 26, + 202, + 73, + 0, // Skip to: 19231 + /* 341 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 195, + 73, + 0, // Skip to: 19231 + /* 348 */ MCD_OPC_Decode, + 237, + 29, + 204, + 1, // Opcode: VSUBLsv8i16 + /* 353 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 392 + /* 359 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 362 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 377 + /* 367 */ MCD_OPC_CheckPredicate, + 26, + 171, + 73, + 0, // Skip to: 19231 + /* 372 */ MCD_OPC_Decode, + 132, + 19, + 202, + 1, // Opcode: VHSUBuv8i8 + /* 377 */ MCD_OPC_FilterValue, + 1, + 161, + 73, + 0, // Skip to: 19231 + /* 382 */ MCD_OPC_CheckPredicate, + 26, + 156, + 73, + 0, // Skip to: 19231 + /* 387 */ MCD_OPC_Decode, + 255, + 18, + 203, + 1, // Opcode: VHSUBuv16i8 + /* 392 */ MCD_OPC_FilterValue, + 231, + 3, + 145, + 73, + 0, // Skip to: 19231 + /* 398 */ MCD_OPC_CheckPredicate, + 26, + 140, + 73, + 0, // Skip to: 19231 + /* 403 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 133, + 73, + 0, // Skip to: 19231 + /* 410 */ MCD_OPC_Decode, + 240, + 29, + 204, + 1, // Opcode: VSUBLuv8i16 + /* 415 */ MCD_OPC_FilterValue, + 3, + 127, + 0, + 0, // Skip to: 547 + /* 420 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 423 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 462 + /* 429 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 432 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 447 + /* 437 */ MCD_OPC_CheckPredicate, + 26, + 101, + 73, + 0, // Skip to: 19231 + /* 442 */ MCD_OPC_Decode, + 131, + 17, + 202, + 1, // Opcode: VCGTsv8i8 + /* 447 */ MCD_OPC_FilterValue, + 1, + 91, + 73, + 0, // Skip to: 19231 + /* 452 */ MCD_OPC_CheckPredicate, + 26, + 86, + 73, + 0, // Skip to: 19231 + /* 457 */ MCD_OPC_Decode, + 254, + 16, + 203, + 1, // Opcode: VCGTsv16i8 + /* 462 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 485 + /* 468 */ MCD_OPC_CheckPredicate, + 26, + 70, + 73, + 0, // Skip to: 19231 + /* 473 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 63, + 73, + 0, // Skip to: 19231 + /* 480 */ MCD_OPC_Decode, + 244, + 29, + 205, + 1, // Opcode: VSUBWsv8i16 + /* 485 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 524 + /* 491 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 494 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 509 + /* 499 */ MCD_OPC_CheckPredicate, + 26, + 39, + 73, + 0, // Skip to: 19231 + /* 504 */ MCD_OPC_Decode, + 137, + 17, + 202, + 1, // Opcode: VCGTuv8i8 + /* 509 */ MCD_OPC_FilterValue, + 1, + 29, + 73, + 0, // Skip to: 19231 + /* 514 */ MCD_OPC_CheckPredicate, + 26, + 24, + 73, + 0, // Skip to: 19231 + /* 519 */ MCD_OPC_Decode, + 132, + 17, + 203, + 1, // Opcode: VCGTuv16i8 + /* 524 */ MCD_OPC_FilterValue, + 231, + 3, + 13, + 73, + 0, // Skip to: 19231 + /* 530 */ MCD_OPC_CheckPredicate, + 26, + 8, + 73, + 0, // Skip to: 19231 + /* 535 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 1, + 73, + 0, // Skip to: 19231 + /* 542 */ MCD_OPC_Decode, + 247, + 29, + 205, + 1, // Opcode: VSUBWuv8i16 + /* 547 */ MCD_OPC_FilterValue, + 4, + 127, + 0, + 0, // Skip to: 679 + /* 552 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 555 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 594 + /* 561 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 564 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 579 + /* 569 */ MCD_OPC_CheckPredicate, + 26, + 225, + 72, + 0, // Skip to: 19231 + /* 574 */ MCD_OPC_Decode, + 255, + 26, + 206, + 1, // Opcode: VSHLsv8i8 + /* 579 */ MCD_OPC_FilterValue, + 1, + 215, + 72, + 0, // Skip to: 19231 + /* 584 */ MCD_OPC_CheckPredicate, + 26, + 210, + 72, + 0, // Skip to: 19231 + /* 589 */ MCD_OPC_Decode, + 248, + 26, + 207, + 1, // Opcode: VSHLsv16i8 + /* 594 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 617 + /* 600 */ MCD_OPC_CheckPredicate, + 26, + 194, + 72, + 0, // Skip to: 19231 + /* 605 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 187, + 72, + 0, // Skip to: 19231 + /* 612 */ MCD_OPC_Decode, + 154, + 16, + 208, + 1, // Opcode: VADDHNv8i8 + /* 617 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 656 + /* 623 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 626 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 641 + /* 631 */ MCD_OPC_CheckPredicate, + 26, + 163, + 72, + 0, // Skip to: 19231 + /* 636 */ MCD_OPC_Decode, + 135, + 27, + 206, + 1, // Opcode: VSHLuv8i8 + /* 641 */ MCD_OPC_FilterValue, + 1, + 153, + 72, + 0, // Skip to: 19231 + /* 646 */ MCD_OPC_CheckPredicate, + 26, + 148, + 72, + 0, // Skip to: 19231 + /* 651 */ MCD_OPC_Decode, + 128, + 27, + 207, + 1, // Opcode: VSHLuv16i8 + /* 656 */ MCD_OPC_FilterValue, + 231, + 3, + 137, + 72, + 0, // Skip to: 19231 + /* 662 */ MCD_OPC_CheckPredicate, + 26, + 132, + 72, + 0, // Skip to: 19231 + /* 667 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 125, + 72, + 0, // Skip to: 19231 + /* 674 */ MCD_OPC_Decode, + 194, + 25, + 208, + 1, // Opcode: VRADDHNv8i8 + /* 679 */ MCD_OPC_FilterValue, + 5, + 127, + 0, + 0, // Skip to: 811 + /* 684 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 687 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 726 + /* 693 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 696 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 711 + /* 701 */ MCD_OPC_CheckPredicate, + 26, + 93, + 72, + 0, // Skip to: 19231 + /* 706 */ MCD_OPC_Decode, + 153, + 26, + 206, + 1, // Opcode: VRSHLsv8i8 + /* 711 */ MCD_OPC_FilterValue, + 1, + 83, + 72, + 0, // Skip to: 19231 + /* 716 */ MCD_OPC_CheckPredicate, + 26, + 78, + 72, + 0, // Skip to: 19231 + /* 721 */ MCD_OPC_Decode, + 146, + 26, + 207, + 1, // Opcode: VRSHLsv16i8 + /* 726 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 749 + /* 732 */ MCD_OPC_CheckPredicate, + 26, + 62, + 72, + 0, // Skip to: 19231 + /* 737 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 55, + 72, + 0, // Skip to: 19231 + /* 744 */ MCD_OPC_Decode, + 219, + 15, + 209, + 1, // Opcode: VABALsv8i16 + /* 749 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 788 + /* 755 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 758 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 773 + /* 763 */ MCD_OPC_CheckPredicate, + 26, + 31, + 72, + 0, // Skip to: 19231 + /* 768 */ MCD_OPC_Decode, + 161, + 26, + 206, + 1, // Opcode: VRSHLuv8i8 + /* 773 */ MCD_OPC_FilterValue, + 1, + 21, + 72, + 0, // Skip to: 19231 + /* 778 */ MCD_OPC_CheckPredicate, + 26, + 16, + 72, + 0, // Skip to: 19231 + /* 783 */ MCD_OPC_Decode, + 154, + 26, + 207, + 1, // Opcode: VRSHLuv16i8 + /* 788 */ MCD_OPC_FilterValue, + 231, + 3, + 5, + 72, + 0, // Skip to: 19231 + /* 794 */ MCD_OPC_CheckPredicate, + 26, + 0, + 72, + 0, // Skip to: 19231 + /* 799 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 249, + 71, + 0, // Skip to: 19231 + /* 806 */ MCD_OPC_Decode, + 222, + 15, + 209, + 1, // Opcode: VABALuv8i16 + /* 811 */ MCD_OPC_FilterValue, + 6, + 127, + 0, + 0, // Skip to: 943 + /* 816 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 819 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 858 + /* 825 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 828 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 843 + /* 833 */ MCD_OPC_CheckPredicate, + 26, + 217, + 71, + 0, // Skip to: 19231 + /* 838 */ MCD_OPC_Decode, + 150, + 22, + 202, + 1, // Opcode: VMAXsv8i8 + /* 843 */ MCD_OPC_FilterValue, + 1, + 207, + 71, + 0, // Skip to: 19231 + /* 848 */ MCD_OPC_CheckPredicate, + 26, + 202, + 71, + 0, // Skip to: 19231 + /* 853 */ MCD_OPC_Decode, + 145, + 22, + 203, + 1, // Opcode: VMAXsv16i8 + /* 858 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 881 + /* 864 */ MCD_OPC_CheckPredicate, + 26, + 186, + 71, + 0, // Skip to: 19231 + /* 869 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 179, + 71, + 0, // Skip to: 19231 + /* 876 */ MCD_OPC_Decode, + 234, + 29, + 208, + 1, // Opcode: VSUBHNv8i8 + /* 881 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 920 + /* 887 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 890 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 905 + /* 895 */ MCD_OPC_CheckPredicate, + 26, + 155, + 71, + 0, // Skip to: 19231 + /* 900 */ MCD_OPC_Decode, + 156, + 22, + 202, + 1, // Opcode: VMAXuv8i8 + /* 905 */ MCD_OPC_FilterValue, + 1, + 145, + 71, + 0, // Skip to: 19231 + /* 910 */ MCD_OPC_CheckPredicate, + 26, + 140, + 71, + 0, // Skip to: 19231 + /* 915 */ MCD_OPC_Decode, + 151, + 22, + 203, + 1, // Opcode: VMAXuv16i8 + /* 920 */ MCD_OPC_FilterValue, + 231, + 3, + 129, + 71, + 0, // Skip to: 19231 + /* 926 */ MCD_OPC_CheckPredicate, + 26, + 124, + 71, + 0, // Skip to: 19231 + /* 931 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 117, + 71, + 0, // Skip to: 19231 + /* 938 */ MCD_OPC_Decode, + 209, + 26, + 208, + 1, // Opcode: VRSUBHNv8i8 + /* 943 */ MCD_OPC_FilterValue, + 7, + 127, + 0, + 0, // Skip to: 1075 + /* 948 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 951 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 990 + /* 957 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 960 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 975 + /* 965 */ MCD_OPC_CheckPredicate, + 26, + 85, + 71, + 0, // Skip to: 19231 + /* 970 */ MCD_OPC_Decode, + 250, + 15, + 202, + 1, // Opcode: VABDsv8i8 + /* 975 */ MCD_OPC_FilterValue, + 1, + 75, + 71, + 0, // Skip to: 19231 + /* 980 */ MCD_OPC_CheckPredicate, + 26, + 70, + 71, + 0, // Skip to: 19231 + /* 985 */ MCD_OPC_Decode, + 245, + 15, + 203, + 1, // Opcode: VABDsv16i8 + /* 990 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 1013 + /* 996 */ MCD_OPC_CheckPredicate, + 26, + 54, + 71, + 0, // Skip to: 19231 + /* 1001 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 47, + 71, + 0, // Skip to: 19231 + /* 1008 */ MCD_OPC_Decode, + 237, + 15, + 204, + 1, // Opcode: VABDLsv8i16 + /* 1013 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 1052 + /* 1019 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1022 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1037 + /* 1027 */ MCD_OPC_CheckPredicate, + 26, + 23, + 71, + 0, // Skip to: 19231 + /* 1032 */ MCD_OPC_Decode, + 128, + 16, + 202, + 1, // Opcode: VABDuv8i8 + /* 1037 */ MCD_OPC_FilterValue, + 1, + 13, + 71, + 0, // Skip to: 19231 + /* 1042 */ MCD_OPC_CheckPredicate, + 26, + 8, + 71, + 0, // Skip to: 19231 + /* 1047 */ MCD_OPC_Decode, + 251, + 15, + 203, + 1, // Opcode: VABDuv16i8 + /* 1052 */ MCD_OPC_FilterValue, + 231, + 3, + 253, + 70, + 0, // Skip to: 19231 + /* 1058 */ MCD_OPC_CheckPredicate, + 26, + 248, + 70, + 0, // Skip to: 19231 + /* 1063 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 241, + 70, + 0, // Skip to: 19231 + /* 1070 */ MCD_OPC_Decode, + 240, + 15, + 204, + 1, // Opcode: VABDLuv8i16 + /* 1075 */ MCD_OPC_FilterValue, + 8, + 127, + 0, + 0, // Skip to: 1207 + /* 1080 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1083 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 1122 + /* 1089 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1092 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1107 + /* 1097 */ MCD_OPC_CheckPredicate, + 26, + 209, + 70, + 0, // Skip to: 19231 + /* 1102 */ MCD_OPC_Decode, + 179, + 16, + 202, + 1, // Opcode: VADDv8i8 + /* 1107 */ MCD_OPC_FilterValue, + 1, + 199, + 70, + 0, // Skip to: 19231 + /* 1112 */ MCD_OPC_CheckPredicate, + 26, + 194, + 70, + 0, // Skip to: 19231 + /* 1117 */ MCD_OPC_Decode, + 172, + 16, + 203, + 1, // Opcode: VADDv16i8 + /* 1122 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 1145 + /* 1128 */ MCD_OPC_CheckPredicate, + 26, + 178, + 70, + 0, // Skip to: 19231 + /* 1133 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 171, + 70, + 0, // Skip to: 19231 + /* 1140 */ MCD_OPC_Decode, + 181, + 22, + 209, + 1, // Opcode: VMLALsv8i16 + /* 1145 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 1184 + /* 1151 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1154 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1169 + /* 1159 */ MCD_OPC_CheckPredicate, + 26, + 147, + 70, + 0, // Skip to: 19231 + /* 1164 */ MCD_OPC_Decode, + 131, + 30, + 202, + 1, // Opcode: VSUBv8i8 + /* 1169 */ MCD_OPC_FilterValue, + 1, + 137, + 70, + 0, // Skip to: 19231 + /* 1174 */ MCD_OPC_CheckPredicate, + 26, + 132, + 70, + 0, // Skip to: 19231 + /* 1179 */ MCD_OPC_Decode, + 252, + 29, + 203, + 1, // Opcode: VSUBv16i8 + /* 1184 */ MCD_OPC_FilterValue, + 231, + 3, + 121, + 70, + 0, // Skip to: 19231 + /* 1190 */ MCD_OPC_CheckPredicate, + 26, + 116, + 70, + 0, // Skip to: 19231 + /* 1195 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 109, + 70, + 0, // Skip to: 19231 + /* 1202 */ MCD_OPC_Decode, + 184, + 22, + 209, + 1, // Opcode: VMLALuv8i16 + /* 1207 */ MCD_OPC_FilterValue, + 9, + 83, + 0, + 0, // Skip to: 1295 + /* 1212 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1215 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 1255 + /* 1220 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1223 */ MCD_OPC_FilterValue, + 228, + 3, + 10, + 0, + 0, // Skip to: 1239 + /* 1229 */ MCD_OPC_CheckPredicate, + 26, + 77, + 70, + 0, // Skip to: 19231 + /* 1234 */ MCD_OPC_Decode, + 203, + 22, + 210, + 1, // Opcode: VMLAv8i8 + /* 1239 */ MCD_OPC_FilterValue, + 230, + 3, + 66, + 70, + 0, // Skip to: 19231 + /* 1245 */ MCD_OPC_CheckPredicate, + 26, + 61, + 70, + 0, // Skip to: 19231 + /* 1250 */ MCD_OPC_Decode, + 234, + 22, + 210, + 1, // Opcode: VMLSv8i8 + /* 1255 */ MCD_OPC_FilterValue, + 1, + 51, + 70, + 0, // Skip to: 19231 + /* 1260 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1263 */ MCD_OPC_FilterValue, + 228, + 3, + 10, + 0, + 0, // Skip to: 1279 + /* 1269 */ MCD_OPC_CheckPredicate, + 26, + 37, + 70, + 0, // Skip to: 19231 + /* 1274 */ MCD_OPC_Decode, + 198, + 22, + 211, + 1, // Opcode: VMLAv16i8 + /* 1279 */ MCD_OPC_FilterValue, + 230, + 3, + 26, + 70, + 0, // Skip to: 19231 + /* 1285 */ MCD_OPC_CheckPredicate, + 26, + 21, + 70, + 0, // Skip to: 19231 + /* 1290 */ MCD_OPC_Decode, + 229, + 22, + 211, + 1, // Opcode: VMLSv16i8 + /* 1295 */ MCD_OPC_FilterValue, + 10, + 95, + 0, + 0, // Skip to: 1395 + /* 1300 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1303 */ MCD_OPC_FilterValue, + 228, + 3, + 17, + 0, + 0, // Skip to: 1326 + /* 1309 */ MCD_OPC_CheckPredicate, + 26, + 253, + 69, + 0, // Skip to: 19231 + /* 1314 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 246, + 69, + 0, // Skip to: 19231 + /* 1321 */ MCD_OPC_Decode, + 137, + 24, + 202, + 1, // Opcode: VPMAXs8 + /* 1326 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 1349 + /* 1332 */ MCD_OPC_CheckPredicate, + 26, + 230, + 69, + 0, // Skip to: 19231 + /* 1337 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 223, + 69, + 0, // Skip to: 19231 + /* 1344 */ MCD_OPC_Decode, + 212, + 22, + 209, + 1, // Opcode: VMLSLsv8i16 + /* 1349 */ MCD_OPC_FilterValue, + 230, + 3, + 17, + 0, + 0, // Skip to: 1372 + /* 1355 */ MCD_OPC_CheckPredicate, + 26, + 207, + 69, + 0, // Skip to: 19231 + /* 1360 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 200, + 69, + 0, // Skip to: 19231 + /* 1367 */ MCD_OPC_Decode, + 140, + 24, + 202, + 1, // Opcode: VPMAXu8 + /* 1372 */ MCD_OPC_FilterValue, + 231, + 3, + 189, + 69, + 0, // Skip to: 19231 + /* 1378 */ MCD_OPC_CheckPredicate, + 26, + 184, + 69, + 0, // Skip to: 19231 + /* 1383 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 177, + 69, + 0, // Skip to: 19231 + /* 1390 */ MCD_OPC_Decode, + 215, + 22, + 209, + 1, // Opcode: VMLSLuv8i16 + /* 1395 */ MCD_OPC_FilterValue, + 12, + 49, + 0, + 0, // Skip to: 1449 + /* 1400 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1403 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 1426 + /* 1409 */ MCD_OPC_CheckPredicate, + 26, + 153, + 69, + 0, // Skip to: 19231 + /* 1414 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 146, + 69, + 0, // Skip to: 19231 + /* 1421 */ MCD_OPC_Decode, + 171, + 23, + 204, + 1, // Opcode: VMULLsv8i16 + /* 1426 */ MCD_OPC_FilterValue, + 231, + 3, + 135, + 69, + 0, // Skip to: 19231 + /* 1432 */ MCD_OPC_CheckPredicate, + 26, + 130, + 69, + 0, // Skip to: 19231 + /* 1437 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 123, + 69, + 0, // Skip to: 19231 + /* 1444 */ MCD_OPC_Decode, + 174, + 23, + 204, + 1, // Opcode: VMULLuv8i16 + /* 1449 */ MCD_OPC_FilterValue, + 13, + 66, + 0, + 0, // Skip to: 1520 + /* 1454 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1457 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 1497 + /* 1462 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1465 */ MCD_OPC_FilterValue, + 228, + 3, + 10, + 0, + 0, // Skip to: 1481 + /* 1471 */ MCD_OPC_CheckPredicate, + 26, + 91, + 69, + 0, // Skip to: 19231 + /* 1476 */ MCD_OPC_Decode, + 168, + 16, + 202, + 1, // Opcode: VADDfd + /* 1481 */ MCD_OPC_FilterValue, + 230, + 3, + 80, + 69, + 0, // Skip to: 19231 + /* 1487 */ MCD_OPC_CheckPredicate, + 26, + 75, + 69, + 0, // Skip to: 19231 + /* 1492 */ MCD_OPC_Decode, + 128, + 24, + 202, + 1, // Opcode: VPADDf + /* 1497 */ MCD_OPC_FilterValue, + 1, + 65, + 69, + 0, // Skip to: 19231 + /* 1502 */ MCD_OPC_CheckPredicate, + 26, + 60, + 69, + 0, // Skip to: 19231 + /* 1507 */ MCD_OPC_CheckField, + 23, + 9, + 228, + 3, + 52, + 69, + 0, // Skip to: 19231 + /* 1515 */ MCD_OPC_Decode, + 169, + 16, + 203, + 1, // Opcode: VADDfq + /* 1520 */ MCD_OPC_FilterValue, + 14, + 104, + 0, + 0, // Skip to: 1629 + /* 1525 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1528 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 1567 + /* 1534 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1537 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1552 + /* 1542 */ MCD_OPC_CheckPredicate, + 26, + 20, + 69, + 0, // Skip to: 19231 + /* 1547 */ MCD_OPC_Decode, + 204, + 16, + 202, + 1, // Opcode: VCEQfd + /* 1552 */ MCD_OPC_FilterValue, + 1, + 10, + 69, + 0, // Skip to: 19231 + /* 1557 */ MCD_OPC_CheckPredicate, + 26, + 5, + 69, + 0, // Skip to: 19231 + /* 1562 */ MCD_OPC_Decode, + 205, + 16, + 203, + 1, // Opcode: VCEQfq + /* 1567 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 1590 + /* 1573 */ MCD_OPC_CheckPredicate, + 26, + 245, + 68, + 0, // Skip to: 19231 + /* 1578 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 238, + 68, + 0, // Skip to: 19231 + /* 1585 */ MCD_OPC_Decode, + 164, + 23, + 204, + 1, // Opcode: VMULLp8 + /* 1590 */ MCD_OPC_FilterValue, + 230, + 3, + 227, + 68, + 0, // Skip to: 19231 + /* 1596 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1599 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1614 + /* 1604 */ MCD_OPC_CheckPredicate, + 26, + 214, + 68, + 0, // Skip to: 19231 + /* 1609 */ MCD_OPC_Decode, + 224, + 16, + 202, + 1, // Opcode: VCGEfd + /* 1614 */ MCD_OPC_FilterValue, + 1, + 204, + 68, + 0, // Skip to: 19231 + /* 1619 */ MCD_OPC_CheckPredicate, + 26, + 199, + 68, + 0, // Skip to: 19231 + /* 1624 */ MCD_OPC_Decode, + 225, + 16, + 203, + 1, // Opcode: VCGEfq + /* 1629 */ MCD_OPC_FilterValue, + 15, + 189, + 68, + 0, // Skip to: 19231 + /* 1634 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1637 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 1677 + /* 1642 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1645 */ MCD_OPC_FilterValue, + 228, + 3, + 10, + 0, + 0, // Skip to: 1661 + /* 1651 */ MCD_OPC_CheckPredicate, + 26, + 167, + 68, + 0, // Skip to: 19231 + /* 1656 */ MCD_OPC_Decode, + 141, + 22, + 202, + 1, // Opcode: VMAXfd + /* 1661 */ MCD_OPC_FilterValue, + 230, + 3, + 156, + 68, + 0, // Skip to: 19231 + /* 1667 */ MCD_OPC_CheckPredicate, + 26, + 151, + 68, + 0, // Skip to: 19231 + /* 1672 */ MCD_OPC_Decode, + 133, + 24, + 202, + 1, // Opcode: VPMAXf + /* 1677 */ MCD_OPC_FilterValue, + 1, + 141, + 68, + 0, // Skip to: 19231 + /* 1682 */ MCD_OPC_CheckPredicate, + 26, + 136, + 68, + 0, // Skip to: 19231 + /* 1687 */ MCD_OPC_CheckField, + 23, + 9, + 228, + 3, + 128, + 68, + 0, // Skip to: 19231 + /* 1695 */ MCD_OPC_Decode, + 142, + 22, + 203, + 1, // Opcode: VMAXfq + /* 1700 */ MCD_OPC_FilterValue, + 1, + 16, + 9, + 0, // Skip to: 4025 + /* 1705 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 1708 */ MCD_OPC_FilterValue, + 0, + 159, + 0, + 0, // Skip to: 1872 + /* 1713 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1716 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 1755 + /* 1722 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1725 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1740 + /* 1730 */ MCD_OPC_CheckPredicate, + 26, + 88, + 68, + 0, // Skip to: 19231 + /* 1735 */ MCD_OPC_Decode, + 239, + 18, + 202, + 1, // Opcode: VHADDsv4i16 + /* 1740 */ MCD_OPC_FilterValue, + 1, + 78, + 68, + 0, // Skip to: 19231 + /* 1745 */ MCD_OPC_CheckPredicate, + 26, + 73, + 68, + 0, // Skip to: 19231 + /* 1750 */ MCD_OPC_Decode, + 241, + 18, + 203, + 1, // Opcode: VHADDsv8i16 + /* 1755 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 1794 + /* 1761 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1764 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1779 + /* 1769 */ MCD_OPC_CheckPredicate, + 26, + 49, + 68, + 0, // Skip to: 19231 + /* 1774 */ MCD_OPC_Decode, + 156, + 16, + 204, + 1, // Opcode: VADDLsv4i32 + /* 1779 */ MCD_OPC_FilterValue, + 1, + 39, + 68, + 0, // Skip to: 19231 + /* 1784 */ MCD_OPC_CheckPredicate, + 26, + 34, + 68, + 0, // Skip to: 19231 + /* 1789 */ MCD_OPC_Decode, + 195, + 22, + 212, + 1, // Opcode: VMLAslv4i16 + /* 1794 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 1833 + /* 1800 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1803 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1818 + /* 1808 */ MCD_OPC_CheckPredicate, + 26, + 10, + 68, + 0, // Skip to: 19231 + /* 1813 */ MCD_OPC_Decode, + 245, + 18, + 202, + 1, // Opcode: VHADDuv4i16 + /* 1818 */ MCD_OPC_FilterValue, + 1, + 0, + 68, + 0, // Skip to: 19231 + /* 1823 */ MCD_OPC_CheckPredicate, + 26, + 251, + 67, + 0, // Skip to: 19231 + /* 1828 */ MCD_OPC_Decode, + 247, + 18, + 203, + 1, // Opcode: VHADDuv8i16 + /* 1833 */ MCD_OPC_FilterValue, + 231, + 3, + 240, + 67, + 0, // Skip to: 19231 + /* 1839 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1842 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1857 + /* 1847 */ MCD_OPC_CheckPredicate, + 26, + 227, + 67, + 0, // Skip to: 19231 + /* 1852 */ MCD_OPC_Decode, + 159, + 16, + 204, + 1, // Opcode: VADDLuv4i32 + /* 1857 */ MCD_OPC_FilterValue, + 1, + 217, + 67, + 0, // Skip to: 19231 + /* 1862 */ MCD_OPC_CheckPredicate, + 26, + 212, + 67, + 0, // Skip to: 19231 + /* 1867 */ MCD_OPC_Decode, + 197, + 22, + 213, + 1, // Opcode: VMLAslv8i16 + /* 1872 */ MCD_OPC_FilterValue, + 1, + 159, + 0, + 0, // Skip to: 2036 + /* 1877 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1880 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 1919 + /* 1886 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1889 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1904 + /* 1894 */ MCD_OPC_CheckPredicate, + 26, + 180, + 67, + 0, // Skip to: 19231 + /* 1899 */ MCD_OPC_Decode, + 219, + 25, + 202, + 1, // Opcode: VRHADDsv4i16 + /* 1904 */ MCD_OPC_FilterValue, + 1, + 170, + 67, + 0, // Skip to: 19231 + /* 1909 */ MCD_OPC_CheckPredicate, + 26, + 165, + 67, + 0, // Skip to: 19231 + /* 1914 */ MCD_OPC_Decode, + 221, + 25, + 203, + 1, // Opcode: VRHADDsv8i16 + /* 1919 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 1958 + /* 1925 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1928 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1943 + /* 1933 */ MCD_OPC_CheckPredicate, + 26, + 141, + 67, + 0, // Skip to: 19231 + /* 1938 */ MCD_OPC_Decode, + 163, + 16, + 205, + 1, // Opcode: VADDWsv4i32 + /* 1943 */ MCD_OPC_FilterValue, + 1, + 131, + 67, + 0, // Skip to: 19231 + /* 1948 */ MCD_OPC_CheckPredicate, + 27, + 126, + 67, + 0, // Skip to: 19231 + /* 1953 */ MCD_OPC_Decode, + 192, + 22, + 212, + 1, // Opcode: VMLAslhd + /* 1958 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 1997 + /* 1964 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1967 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1982 + /* 1972 */ MCD_OPC_CheckPredicate, + 26, + 102, + 67, + 0, // Skip to: 19231 + /* 1977 */ MCD_OPC_Decode, + 225, + 25, + 202, + 1, // Opcode: VRHADDuv4i16 + /* 1982 */ MCD_OPC_FilterValue, + 1, + 92, + 67, + 0, // Skip to: 19231 + /* 1987 */ MCD_OPC_CheckPredicate, + 26, + 87, + 67, + 0, // Skip to: 19231 + /* 1992 */ MCD_OPC_Decode, + 227, + 25, + 203, + 1, // Opcode: VRHADDuv8i16 + /* 1997 */ MCD_OPC_FilterValue, + 231, + 3, + 76, + 67, + 0, // Skip to: 19231 + /* 2003 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2006 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2021 + /* 2011 */ MCD_OPC_CheckPredicate, + 26, + 63, + 67, + 0, // Skip to: 19231 + /* 2016 */ MCD_OPC_Decode, + 166, + 16, + 205, + 1, // Opcode: VADDWuv4i32 + /* 2021 */ MCD_OPC_FilterValue, + 1, + 53, + 67, + 0, // Skip to: 19231 + /* 2026 */ MCD_OPC_CheckPredicate, + 27, + 48, + 67, + 0, // Skip to: 19231 + /* 2031 */ MCD_OPC_Decode, + 193, + 22, + 213, + 1, // Opcode: VMLAslhq + /* 2036 */ MCD_OPC_FilterValue, + 2, + 159, + 0, + 0, // Skip to: 2200 + /* 2041 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2044 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 2083 + /* 2050 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2053 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2068 + /* 2058 */ MCD_OPC_CheckPredicate, + 26, + 16, + 67, + 0, // Skip to: 19231 + /* 2063 */ MCD_OPC_Decode, + 251, + 18, + 202, + 1, // Opcode: VHSUBsv4i16 + /* 2068 */ MCD_OPC_FilterValue, + 1, + 6, + 67, + 0, // Skip to: 19231 + /* 2073 */ MCD_OPC_CheckPredicate, + 26, + 1, + 67, + 0, // Skip to: 19231 + /* 2078 */ MCD_OPC_Decode, + 253, + 18, + 203, + 1, // Opcode: VHSUBsv8i16 + /* 2083 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 2122 + /* 2089 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2092 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2107 + /* 2097 */ MCD_OPC_CheckPredicate, + 26, + 233, + 66, + 0, // Skip to: 19231 + /* 2102 */ MCD_OPC_Decode, + 236, + 29, + 204, + 1, // Opcode: VSUBLsv4i32 + /* 2107 */ MCD_OPC_FilterValue, + 1, + 223, + 66, + 0, // Skip to: 19231 + /* 2112 */ MCD_OPC_CheckPredicate, + 26, + 218, + 66, + 0, // Skip to: 19231 + /* 2117 */ MCD_OPC_Decode, + 176, + 22, + 214, + 1, // Opcode: VMLALslsv4i16 + /* 2122 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 2161 + /* 2128 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2131 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2146 + /* 2136 */ MCD_OPC_CheckPredicate, + 26, + 194, + 66, + 0, // Skip to: 19231 + /* 2141 */ MCD_OPC_Decode, + 129, + 19, + 202, + 1, // Opcode: VHSUBuv4i16 + /* 2146 */ MCD_OPC_FilterValue, + 1, + 184, + 66, + 0, // Skip to: 19231 + /* 2151 */ MCD_OPC_CheckPredicate, + 26, + 179, + 66, + 0, // Skip to: 19231 + /* 2156 */ MCD_OPC_Decode, + 131, + 19, + 203, + 1, // Opcode: VHSUBuv8i16 + /* 2161 */ MCD_OPC_FilterValue, + 231, + 3, + 168, + 66, + 0, // Skip to: 19231 + /* 2167 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2170 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2185 + /* 2175 */ MCD_OPC_CheckPredicate, + 26, + 155, + 66, + 0, // Skip to: 19231 + /* 2180 */ MCD_OPC_Decode, + 239, + 29, + 204, + 1, // Opcode: VSUBLuv4i32 + /* 2185 */ MCD_OPC_FilterValue, + 1, + 145, + 66, + 0, // Skip to: 19231 + /* 2190 */ MCD_OPC_CheckPredicate, + 26, + 140, + 66, + 0, // Skip to: 19231 + /* 2195 */ MCD_OPC_Decode, + 178, + 22, + 214, + 1, // Opcode: VMLALsluv4i16 + /* 2200 */ MCD_OPC_FilterValue, + 3, + 143, + 0, + 0, // Skip to: 2348 + /* 2205 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2208 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 2247 + /* 2214 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2217 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2232 + /* 2222 */ MCD_OPC_CheckPredicate, + 26, + 108, + 66, + 0, // Skip to: 19231 + /* 2227 */ MCD_OPC_Decode, + 128, + 17, + 202, + 1, // Opcode: VCGTsv4i16 + /* 2232 */ MCD_OPC_FilterValue, + 1, + 98, + 66, + 0, // Skip to: 19231 + /* 2237 */ MCD_OPC_CheckPredicate, + 26, + 93, + 66, + 0, // Skip to: 19231 + /* 2242 */ MCD_OPC_Decode, + 130, + 17, + 203, + 1, // Opcode: VCGTsv8i16 + /* 2247 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 2286 + /* 2253 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2256 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2271 + /* 2261 */ MCD_OPC_CheckPredicate, + 26, + 69, + 66, + 0, // Skip to: 19231 + /* 2266 */ MCD_OPC_Decode, + 243, + 29, + 205, + 1, // Opcode: VSUBWsv4i32 + /* 2271 */ MCD_OPC_FilterValue, + 1, + 59, + 66, + 0, // Skip to: 19231 + /* 2276 */ MCD_OPC_CheckPredicate, + 26, + 54, + 66, + 0, // Skip to: 19231 + /* 2281 */ MCD_OPC_Decode, + 172, + 24, + 214, + 1, // Opcode: VQDMLALslv4i16 + /* 2286 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 2325 + /* 2292 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2295 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2310 + /* 2300 */ MCD_OPC_CheckPredicate, + 26, + 30, + 66, + 0, // Skip to: 19231 + /* 2305 */ MCD_OPC_Decode, + 134, + 17, + 202, + 1, // Opcode: VCGTuv4i16 + /* 2310 */ MCD_OPC_FilterValue, + 1, + 20, + 66, + 0, // Skip to: 19231 + /* 2315 */ MCD_OPC_CheckPredicate, + 26, + 15, + 66, + 0, // Skip to: 19231 + /* 2320 */ MCD_OPC_Decode, + 136, + 17, + 203, + 1, // Opcode: VCGTuv8i16 + /* 2325 */ MCD_OPC_FilterValue, + 231, + 3, + 4, + 66, + 0, // Skip to: 19231 + /* 2331 */ MCD_OPC_CheckPredicate, + 26, + 255, + 65, + 0, // Skip to: 19231 + /* 2336 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 248, + 65, + 0, // Skip to: 19231 + /* 2343 */ MCD_OPC_Decode, + 246, + 29, + 205, + 1, // Opcode: VSUBWuv4i32 + /* 2348 */ MCD_OPC_FilterValue, + 4, + 159, + 0, + 0, // Skip to: 2512 + /* 2353 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2356 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 2395 + /* 2362 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2365 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2380 + /* 2370 */ MCD_OPC_CheckPredicate, + 26, + 216, + 65, + 0, // Skip to: 19231 + /* 2375 */ MCD_OPC_Decode, + 252, + 26, + 206, + 1, // Opcode: VSHLsv4i16 + /* 2380 */ MCD_OPC_FilterValue, + 1, + 206, + 65, + 0, // Skip to: 19231 + /* 2385 */ MCD_OPC_CheckPredicate, + 26, + 201, + 65, + 0, // Skip to: 19231 + /* 2390 */ MCD_OPC_Decode, + 254, + 26, + 207, + 1, // Opcode: VSHLsv8i16 + /* 2395 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 2434 + /* 2401 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2404 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2419 + /* 2409 */ MCD_OPC_CheckPredicate, + 26, + 177, + 65, + 0, // Skip to: 19231 + /* 2414 */ MCD_OPC_Decode, + 153, + 16, + 208, + 1, // Opcode: VADDHNv4i16 + /* 2419 */ MCD_OPC_FilterValue, + 1, + 167, + 65, + 0, // Skip to: 19231 + /* 2424 */ MCD_OPC_CheckPredicate, + 26, + 162, + 65, + 0, // Skip to: 19231 + /* 2429 */ MCD_OPC_Decode, + 226, + 22, + 212, + 1, // Opcode: VMLSslv4i16 + /* 2434 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 2473 + /* 2440 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2443 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2458 + /* 2448 */ MCD_OPC_CheckPredicate, + 26, + 138, + 65, + 0, // Skip to: 19231 + /* 2453 */ MCD_OPC_Decode, + 132, + 27, + 206, + 1, // Opcode: VSHLuv4i16 + /* 2458 */ MCD_OPC_FilterValue, + 1, + 128, + 65, + 0, // Skip to: 19231 + /* 2463 */ MCD_OPC_CheckPredicate, + 26, + 123, + 65, + 0, // Skip to: 19231 + /* 2468 */ MCD_OPC_Decode, + 134, + 27, + 207, + 1, // Opcode: VSHLuv8i16 + /* 2473 */ MCD_OPC_FilterValue, + 231, + 3, + 112, + 65, + 0, // Skip to: 19231 + /* 2479 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2482 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2497 + /* 2487 */ MCD_OPC_CheckPredicate, + 26, + 99, + 65, + 0, // Skip to: 19231 + /* 2492 */ MCD_OPC_Decode, + 193, + 25, + 208, + 1, // Opcode: VRADDHNv4i16 + /* 2497 */ MCD_OPC_FilterValue, + 1, + 89, + 65, + 0, // Skip to: 19231 + /* 2502 */ MCD_OPC_CheckPredicate, + 26, + 84, + 65, + 0, // Skip to: 19231 + /* 2507 */ MCD_OPC_Decode, + 228, + 22, + 213, + 1, // Opcode: VMLSslv8i16 + /* 2512 */ MCD_OPC_FilterValue, + 5, + 159, + 0, + 0, // Skip to: 2676 + /* 2517 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2520 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 2559 + /* 2526 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2529 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2544 + /* 2534 */ MCD_OPC_CheckPredicate, + 26, + 52, + 65, + 0, // Skip to: 19231 + /* 2539 */ MCD_OPC_Decode, + 150, + 26, + 206, + 1, // Opcode: VRSHLsv4i16 + /* 2544 */ MCD_OPC_FilterValue, + 1, + 42, + 65, + 0, // Skip to: 19231 + /* 2549 */ MCD_OPC_CheckPredicate, + 26, + 37, + 65, + 0, // Skip to: 19231 + /* 2554 */ MCD_OPC_Decode, + 152, + 26, + 207, + 1, // Opcode: VRSHLsv8i16 + /* 2559 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 2598 + /* 2565 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2568 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2583 + /* 2573 */ MCD_OPC_CheckPredicate, + 26, + 13, + 65, + 0, // Skip to: 19231 + /* 2578 */ MCD_OPC_Decode, + 218, + 15, + 209, + 1, // Opcode: VABALsv4i32 + /* 2583 */ MCD_OPC_FilterValue, + 1, + 3, + 65, + 0, // Skip to: 19231 + /* 2588 */ MCD_OPC_CheckPredicate, + 27, + 254, + 64, + 0, // Skip to: 19231 + /* 2593 */ MCD_OPC_Decode, + 223, + 22, + 212, + 1, // Opcode: VMLSslhd + /* 2598 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 2637 + /* 2604 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2607 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2622 + /* 2612 */ MCD_OPC_CheckPredicate, + 26, + 230, + 64, + 0, // Skip to: 19231 + /* 2617 */ MCD_OPC_Decode, + 158, + 26, + 206, + 1, // Opcode: VRSHLuv4i16 + /* 2622 */ MCD_OPC_FilterValue, + 1, + 220, + 64, + 0, // Skip to: 19231 + /* 2627 */ MCD_OPC_CheckPredicate, + 26, + 215, + 64, + 0, // Skip to: 19231 + /* 2632 */ MCD_OPC_Decode, + 160, + 26, + 207, + 1, // Opcode: VRSHLuv8i16 + /* 2637 */ MCD_OPC_FilterValue, + 231, + 3, + 204, + 64, + 0, // Skip to: 19231 + /* 2643 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2646 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2661 + /* 2651 */ MCD_OPC_CheckPredicate, + 26, + 191, + 64, + 0, // Skip to: 19231 + /* 2656 */ MCD_OPC_Decode, + 221, + 15, + 209, + 1, // Opcode: VABALuv4i32 + /* 2661 */ MCD_OPC_FilterValue, + 1, + 181, + 64, + 0, // Skip to: 19231 + /* 2666 */ MCD_OPC_CheckPredicate, + 27, + 176, + 64, + 0, // Skip to: 19231 + /* 2671 */ MCD_OPC_Decode, + 224, + 22, + 213, + 1, // Opcode: VMLSslhq + /* 2676 */ MCD_OPC_FilterValue, + 6, + 159, + 0, + 0, // Skip to: 2840 + /* 2681 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2684 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 2723 + /* 2690 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2693 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2708 + /* 2698 */ MCD_OPC_CheckPredicate, + 26, + 144, + 64, + 0, // Skip to: 19231 + /* 2703 */ MCD_OPC_Decode, + 147, + 22, + 202, + 1, // Opcode: VMAXsv4i16 + /* 2708 */ MCD_OPC_FilterValue, + 1, + 134, + 64, + 0, // Skip to: 19231 + /* 2713 */ MCD_OPC_CheckPredicate, + 26, + 129, + 64, + 0, // Skip to: 19231 + /* 2718 */ MCD_OPC_Decode, + 149, + 22, + 203, + 1, // Opcode: VMAXsv8i16 + /* 2723 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 2762 + /* 2729 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2732 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2747 + /* 2737 */ MCD_OPC_CheckPredicate, + 26, + 105, + 64, + 0, // Skip to: 19231 + /* 2742 */ MCD_OPC_Decode, + 233, + 29, + 208, + 1, // Opcode: VSUBHNv4i16 + /* 2747 */ MCD_OPC_FilterValue, + 1, + 95, + 64, + 0, // Skip to: 19231 + /* 2752 */ MCD_OPC_CheckPredicate, + 26, + 90, + 64, + 0, // Skip to: 19231 + /* 2757 */ MCD_OPC_Decode, + 207, + 22, + 214, + 1, // Opcode: VMLSLslsv4i16 + /* 2762 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 2801 + /* 2768 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2771 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2786 + /* 2776 */ MCD_OPC_CheckPredicate, + 26, + 66, + 64, + 0, // Skip to: 19231 + /* 2781 */ MCD_OPC_Decode, + 153, + 22, + 202, + 1, // Opcode: VMAXuv4i16 + /* 2786 */ MCD_OPC_FilterValue, + 1, + 56, + 64, + 0, // Skip to: 19231 + /* 2791 */ MCD_OPC_CheckPredicate, + 26, + 51, + 64, + 0, // Skip to: 19231 + /* 2796 */ MCD_OPC_Decode, + 155, + 22, + 203, + 1, // Opcode: VMAXuv8i16 + /* 2801 */ MCD_OPC_FilterValue, + 231, + 3, + 40, + 64, + 0, // Skip to: 19231 + /* 2807 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2810 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2825 + /* 2815 */ MCD_OPC_CheckPredicate, + 26, + 27, + 64, + 0, // Skip to: 19231 + /* 2820 */ MCD_OPC_Decode, + 208, + 26, + 208, + 1, // Opcode: VRSUBHNv4i16 + /* 2825 */ MCD_OPC_FilterValue, + 1, + 17, + 64, + 0, // Skip to: 19231 + /* 2830 */ MCD_OPC_CheckPredicate, + 26, + 12, + 64, + 0, // Skip to: 19231 + /* 2835 */ MCD_OPC_Decode, + 209, + 22, + 214, + 1, // Opcode: VMLSLsluv4i16 + /* 2840 */ MCD_OPC_FilterValue, + 7, + 143, + 0, + 0, // Skip to: 2988 + /* 2845 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2848 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 2887 + /* 2854 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2857 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2872 + /* 2862 */ MCD_OPC_CheckPredicate, + 26, + 236, + 63, + 0, // Skip to: 19231 + /* 2867 */ MCD_OPC_Decode, + 247, + 15, + 202, + 1, // Opcode: VABDsv4i16 + /* 2872 */ MCD_OPC_FilterValue, + 1, + 226, + 63, + 0, // Skip to: 19231 + /* 2877 */ MCD_OPC_CheckPredicate, + 26, + 221, + 63, + 0, // Skip to: 19231 + /* 2882 */ MCD_OPC_Decode, + 249, + 15, + 203, + 1, // Opcode: VABDsv8i16 + /* 2887 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 2926 + /* 2893 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2896 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2911 + /* 2901 */ MCD_OPC_CheckPredicate, + 26, + 197, + 63, + 0, // Skip to: 19231 + /* 2906 */ MCD_OPC_Decode, + 236, + 15, + 204, + 1, // Opcode: VABDLsv4i32 + /* 2911 */ MCD_OPC_FilterValue, + 1, + 187, + 63, + 0, // Skip to: 19231 + /* 2916 */ MCD_OPC_CheckPredicate, + 26, + 182, + 63, + 0, // Skip to: 19231 + /* 2921 */ MCD_OPC_Decode, + 176, + 24, + 214, + 1, // Opcode: VQDMLSLslv4i16 + /* 2926 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 2965 + /* 2932 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2935 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2950 + /* 2940 */ MCD_OPC_CheckPredicate, + 26, + 158, + 63, + 0, // Skip to: 19231 + /* 2945 */ MCD_OPC_Decode, + 253, + 15, + 202, + 1, // Opcode: VABDuv4i16 + /* 2950 */ MCD_OPC_FilterValue, + 1, + 148, + 63, + 0, // Skip to: 19231 + /* 2955 */ MCD_OPC_CheckPredicate, + 26, + 143, + 63, + 0, // Skip to: 19231 + /* 2960 */ MCD_OPC_Decode, + 255, + 15, + 203, + 1, // Opcode: VABDuv8i16 + /* 2965 */ MCD_OPC_FilterValue, + 231, + 3, + 132, + 63, + 0, // Skip to: 19231 + /* 2971 */ MCD_OPC_CheckPredicate, + 26, + 127, + 63, + 0, // Skip to: 19231 + /* 2976 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 120, + 63, + 0, // Skip to: 19231 + /* 2983 */ MCD_OPC_Decode, + 239, + 15, + 204, + 1, // Opcode: VABDLuv4i32 + /* 2988 */ MCD_OPC_FilterValue, + 8, + 159, + 0, + 0, // Skip to: 3152 + /* 2993 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2996 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 3035 + /* 3002 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3005 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3020 + /* 3010 */ MCD_OPC_CheckPredicate, + 26, + 88, + 63, + 0, // Skip to: 19231 + /* 3015 */ MCD_OPC_Decode, + 176, + 16, + 202, + 1, // Opcode: VADDv4i16 + /* 3020 */ MCD_OPC_FilterValue, + 1, + 78, + 63, + 0, // Skip to: 19231 + /* 3025 */ MCD_OPC_CheckPredicate, + 26, + 73, + 63, + 0, // Skip to: 19231 + /* 3030 */ MCD_OPC_Decode, + 178, + 16, + 203, + 1, // Opcode: VADDv8i16 + /* 3035 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 3074 + /* 3041 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3044 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3059 + /* 3049 */ MCD_OPC_CheckPredicate, + 26, + 49, + 63, + 0, // Skip to: 19231 + /* 3054 */ MCD_OPC_Decode, + 180, + 22, + 209, + 1, // Opcode: VMLALsv4i32 + /* 3059 */ MCD_OPC_FilterValue, + 1, + 39, + 63, + 0, // Skip to: 19231 + /* 3064 */ MCD_OPC_CheckPredicate, + 26, + 34, + 63, + 0, // Skip to: 19231 + /* 3069 */ MCD_OPC_Decode, + 187, + 23, + 215, + 1, // Opcode: VMULslv4i16 + /* 3074 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 3113 + /* 3080 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3083 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3098 + /* 3088 */ MCD_OPC_CheckPredicate, + 26, + 10, + 63, + 0, // Skip to: 19231 + /* 3093 */ MCD_OPC_Decode, + 128, + 30, + 202, + 1, // Opcode: VSUBv4i16 + /* 3098 */ MCD_OPC_FilterValue, + 1, + 0, + 63, + 0, // Skip to: 19231 + /* 3103 */ MCD_OPC_CheckPredicate, + 26, + 251, + 62, + 0, // Skip to: 19231 + /* 3108 */ MCD_OPC_Decode, + 130, + 30, + 203, + 1, // Opcode: VSUBv8i16 + /* 3113 */ MCD_OPC_FilterValue, + 231, + 3, + 240, + 62, + 0, // Skip to: 19231 + /* 3119 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3122 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3137 + /* 3127 */ MCD_OPC_CheckPredicate, + 26, + 227, + 62, + 0, // Skip to: 19231 + /* 3132 */ MCD_OPC_Decode, + 183, + 22, + 209, + 1, // Opcode: VMLALuv4i32 + /* 3137 */ MCD_OPC_FilterValue, + 1, + 217, + 62, + 0, // Skip to: 19231 + /* 3142 */ MCD_OPC_CheckPredicate, + 26, + 212, + 62, + 0, // Skip to: 19231 + /* 3147 */ MCD_OPC_Decode, + 189, + 23, + 216, + 1, // Opcode: VMULslv8i16 + /* 3152 */ MCD_OPC_FilterValue, + 9, + 143, + 0, + 0, // Skip to: 3300 + /* 3157 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3160 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 3199 + /* 3166 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3169 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3184 + /* 3174 */ MCD_OPC_CheckPredicate, + 26, + 180, + 62, + 0, // Skip to: 19231 + /* 3179 */ MCD_OPC_Decode, + 200, + 22, + 210, + 1, // Opcode: VMLAv4i16 + /* 3184 */ MCD_OPC_FilterValue, + 1, + 170, + 62, + 0, // Skip to: 19231 + /* 3189 */ MCD_OPC_CheckPredicate, + 26, + 165, + 62, + 0, // Skip to: 19231 + /* 3194 */ MCD_OPC_Decode, + 202, + 22, + 211, + 1, // Opcode: VMLAv8i16 + /* 3199 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 3238 + /* 3205 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3208 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3223 + /* 3213 */ MCD_OPC_CheckPredicate, + 26, + 141, + 62, + 0, // Skip to: 19231 + /* 3218 */ MCD_OPC_Decode, + 174, + 24, + 209, + 1, // Opcode: VQDMLALv4i32 + /* 3223 */ MCD_OPC_FilterValue, + 1, + 131, + 62, + 0, // Skip to: 19231 + /* 3228 */ MCD_OPC_CheckPredicate, + 27, + 126, + 62, + 0, // Skip to: 19231 + /* 3233 */ MCD_OPC_Decode, + 184, + 23, + 215, + 1, // Opcode: VMULslhd + /* 3238 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 3277 + /* 3244 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3247 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3262 + /* 3252 */ MCD_OPC_CheckPredicate, + 26, + 102, + 62, + 0, // Skip to: 19231 + /* 3257 */ MCD_OPC_Decode, + 231, + 22, + 210, + 1, // Opcode: VMLSv4i16 + /* 3262 */ MCD_OPC_FilterValue, + 1, + 92, + 62, + 0, // Skip to: 19231 + /* 3267 */ MCD_OPC_CheckPredicate, + 26, + 87, + 62, + 0, // Skip to: 19231 + /* 3272 */ MCD_OPC_Decode, + 233, + 22, + 211, + 1, // Opcode: VMLSv8i16 + /* 3277 */ MCD_OPC_FilterValue, + 231, + 3, + 76, + 62, + 0, // Skip to: 19231 + /* 3283 */ MCD_OPC_CheckPredicate, + 27, + 71, + 62, + 0, // Skip to: 19231 + /* 3288 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 64, + 62, + 0, // Skip to: 19231 + /* 3295 */ MCD_OPC_Decode, + 185, + 23, + 216, + 1, // Opcode: VMULslhq + /* 3300 */ MCD_OPC_FilterValue, + 10, + 127, + 0, + 0, // Skip to: 3432 + /* 3305 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3308 */ MCD_OPC_FilterValue, + 228, + 3, + 17, + 0, + 0, // Skip to: 3331 + /* 3314 */ MCD_OPC_CheckPredicate, + 26, + 40, + 62, + 0, // Skip to: 19231 + /* 3319 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 33, + 62, + 0, // Skip to: 19231 + /* 3326 */ MCD_OPC_Decode, + 135, + 24, + 202, + 1, // Opcode: VPMAXs16 + /* 3331 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 3370 + /* 3337 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3340 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3355 + /* 3345 */ MCD_OPC_CheckPredicate, + 26, + 9, + 62, + 0, // Skip to: 19231 + /* 3350 */ MCD_OPC_Decode, + 211, + 22, + 209, + 1, // Opcode: VMLSLsv4i32 + /* 3355 */ MCD_OPC_FilterValue, + 1, + 255, + 61, + 0, // Skip to: 19231 + /* 3360 */ MCD_OPC_CheckPredicate, + 26, + 250, + 61, + 0, // Skip to: 19231 + /* 3365 */ MCD_OPC_Decode, + 166, + 23, + 217, + 1, // Opcode: VMULLslsv4i16 + /* 3370 */ MCD_OPC_FilterValue, + 230, + 3, + 17, + 0, + 0, // Skip to: 3393 + /* 3376 */ MCD_OPC_CheckPredicate, + 26, + 234, + 61, + 0, // Skip to: 19231 + /* 3381 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 227, + 61, + 0, // Skip to: 19231 + /* 3388 */ MCD_OPC_Decode, + 138, + 24, + 202, + 1, // Opcode: VPMAXu16 + /* 3393 */ MCD_OPC_FilterValue, + 231, + 3, + 216, + 61, + 0, // Skip to: 19231 + /* 3399 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3402 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3417 + /* 3407 */ MCD_OPC_CheckPredicate, + 26, + 203, + 61, + 0, // Skip to: 19231 + /* 3412 */ MCD_OPC_Decode, + 214, + 22, + 209, + 1, // Opcode: VMLSLuv4i32 + /* 3417 */ MCD_OPC_FilterValue, + 1, + 193, + 61, + 0, // Skip to: 19231 + /* 3422 */ MCD_OPC_CheckPredicate, + 26, + 188, + 61, + 0, // Skip to: 19231 + /* 3427 */ MCD_OPC_Decode, + 168, + 23, + 217, + 1, // Opcode: VMULLsluv4i16 + /* 3432 */ MCD_OPC_FilterValue, + 11, + 120, + 0, + 0, // Skip to: 3557 + /* 3437 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3440 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 3479 + /* 3446 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3449 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3464 + /* 3454 */ MCD_OPC_CheckPredicate, + 26, + 156, + 61, + 0, // Skip to: 19231 + /* 3459 */ MCD_OPC_Decode, + 184, + 24, + 202, + 1, // Opcode: VQDMULHv4i16 + /* 3464 */ MCD_OPC_FilterValue, + 1, + 146, + 61, + 0, // Skip to: 19231 + /* 3469 */ MCD_OPC_CheckPredicate, + 26, + 141, + 61, + 0, // Skip to: 19231 + /* 3474 */ MCD_OPC_Decode, + 186, + 24, + 203, + 1, // Opcode: VQDMULHv8i16 + /* 3479 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 3518 + /* 3485 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3488 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3503 + /* 3493 */ MCD_OPC_CheckPredicate, + 26, + 117, + 61, + 0, // Skip to: 19231 + /* 3498 */ MCD_OPC_Decode, + 178, + 24, + 209, + 1, // Opcode: VQDMLSLv4i32 + /* 3503 */ MCD_OPC_FilterValue, + 1, + 107, + 61, + 0, // Skip to: 19231 + /* 3508 */ MCD_OPC_CheckPredicate, + 26, + 102, + 61, + 0, // Skip to: 19231 + /* 3513 */ MCD_OPC_Decode, + 188, + 24, + 217, + 1, // Opcode: VQDMULLslv4i16 + /* 3518 */ MCD_OPC_FilterValue, + 230, + 3, + 91, + 61, + 0, // Skip to: 19231 + /* 3524 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3527 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3542 + /* 3532 */ MCD_OPC_CheckPredicate, + 26, + 78, + 61, + 0, // Skip to: 19231 + /* 3537 */ MCD_OPC_Decode, + 227, + 24, + 202, + 1, // Opcode: VQRDMULHv4i16 + /* 3542 */ MCD_OPC_FilterValue, + 1, + 68, + 61, + 0, // Skip to: 19231 + /* 3547 */ MCD_OPC_CheckPredicate, + 26, + 63, + 61, + 0, // Skip to: 19231 + /* 3552 */ MCD_OPC_Decode, + 229, + 24, + 203, + 1, // Opcode: VQRDMULHv8i16 + /* 3557 */ MCD_OPC_FilterValue, + 12, + 83, + 0, + 0, // Skip to: 3645 + /* 3562 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3565 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 3605 + /* 3570 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3573 */ MCD_OPC_FilterValue, + 229, + 3, + 10, + 0, + 0, // Skip to: 3589 + /* 3579 */ MCD_OPC_CheckPredicate, + 26, + 31, + 61, + 0, // Skip to: 19231 + /* 3584 */ MCD_OPC_Decode, + 170, + 23, + 204, + 1, // Opcode: VMULLsv4i32 + /* 3589 */ MCD_OPC_FilterValue, + 231, + 3, + 20, + 61, + 0, // Skip to: 19231 + /* 3595 */ MCD_OPC_CheckPredicate, + 26, + 15, + 61, + 0, // Skip to: 19231 + /* 3600 */ MCD_OPC_Decode, + 173, + 23, + 204, + 1, // Opcode: VMULLuv4i32 + /* 3605 */ MCD_OPC_FilterValue, + 1, + 5, + 61, + 0, // Skip to: 19231 + /* 3610 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3613 */ MCD_OPC_FilterValue, + 229, + 3, + 10, + 0, + 0, // Skip to: 3629 + /* 3619 */ MCD_OPC_CheckPredicate, + 26, + 247, + 60, + 0, // Skip to: 19231 + /* 3624 */ MCD_OPC_Decode, + 180, + 24, + 215, + 1, // Opcode: VQDMULHslv4i16 + /* 3629 */ MCD_OPC_FilterValue, + 231, + 3, + 236, + 60, + 0, // Skip to: 19231 + /* 3635 */ MCD_OPC_CheckPredicate, + 26, + 231, + 60, + 0, // Skip to: 19231 + /* 3640 */ MCD_OPC_Decode, + 182, + 24, + 216, + 1, // Opcode: VQDMULHslv8i16 + /* 3645 */ MCD_OPC_FilterValue, + 13, + 127, + 0, + 0, // Skip to: 3777 + /* 3650 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3653 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 3692 + /* 3659 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3662 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3677 + /* 3667 */ MCD_OPC_CheckPredicate, + 27, + 199, + 60, + 0, // Skip to: 19231 + /* 3672 */ MCD_OPC_Decode, + 170, + 16, + 202, + 1, // Opcode: VADDhd + /* 3677 */ MCD_OPC_FilterValue, + 1, + 189, + 60, + 0, // Skip to: 19231 + /* 3682 */ MCD_OPC_CheckPredicate, + 27, + 184, + 60, + 0, // Skip to: 19231 + /* 3687 */ MCD_OPC_Decode, + 171, + 16, + 203, + 1, // Opcode: VADDhq + /* 3692 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 3731 + /* 3698 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3701 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3716 + /* 3706 */ MCD_OPC_CheckPredicate, + 26, + 160, + 60, + 0, // Skip to: 19231 + /* 3711 */ MCD_OPC_Decode, + 190, + 24, + 204, + 1, // Opcode: VQDMULLv4i32 + /* 3716 */ MCD_OPC_FilterValue, + 1, + 150, + 60, + 0, // Skip to: 19231 + /* 3721 */ MCD_OPC_CheckPredicate, + 26, + 145, + 60, + 0, // Skip to: 19231 + /* 3726 */ MCD_OPC_Decode, + 223, + 24, + 215, + 1, // Opcode: VQRDMULHslv4i16 + /* 3731 */ MCD_OPC_FilterValue, + 230, + 3, + 17, + 0, + 0, // Skip to: 3754 + /* 3737 */ MCD_OPC_CheckPredicate, + 27, + 129, + 60, + 0, // Skip to: 19231 + /* 3742 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 122, + 60, + 0, // Skip to: 19231 + /* 3749 */ MCD_OPC_Decode, + 129, + 24, + 202, + 1, // Opcode: VPADDh + /* 3754 */ MCD_OPC_FilterValue, + 231, + 3, + 111, + 60, + 0, // Skip to: 19231 + /* 3760 */ MCD_OPC_CheckPredicate, + 26, + 106, + 60, + 0, // Skip to: 19231 + /* 3765 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 99, + 60, + 0, // Skip to: 19231 + /* 3772 */ MCD_OPC_Decode, + 225, + 24, + 216, + 1, // Opcode: VQRDMULHslv8i16 + /* 3777 */ MCD_OPC_FilterValue, + 14, + 127, + 0, + 0, // Skip to: 3909 + /* 3782 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3785 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 3824 + /* 3791 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3794 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3809 + /* 3799 */ MCD_OPC_CheckPredicate, + 27, + 67, + 60, + 0, // Skip to: 19231 + /* 3804 */ MCD_OPC_Decode, + 206, + 16, + 202, + 1, // Opcode: VCEQhd + /* 3809 */ MCD_OPC_FilterValue, + 1, + 57, + 60, + 0, // Skip to: 19231 + /* 3814 */ MCD_OPC_CheckPredicate, + 27, + 52, + 60, + 0, // Skip to: 19231 + /* 3819 */ MCD_OPC_Decode, + 207, + 16, + 203, + 1, // Opcode: VCEQhq + /* 3824 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 3847 + /* 3830 */ MCD_OPC_CheckPredicate, + 28, + 36, + 60, + 0, // Skip to: 19231 + /* 3835 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 29, + 60, + 0, // Skip to: 19231 + /* 3842 */ MCD_OPC_Decode, + 207, + 24, + 212, + 1, // Opcode: VQRDMLAHslv4i16 + /* 3847 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 3886 + /* 3853 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3856 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3871 + /* 3861 */ MCD_OPC_CheckPredicate, + 27, + 5, + 60, + 0, // Skip to: 19231 + /* 3866 */ MCD_OPC_Decode, + 226, + 16, + 202, + 1, // Opcode: VCGEhd + /* 3871 */ MCD_OPC_FilterValue, + 1, + 251, + 59, + 0, // Skip to: 19231 + /* 3876 */ MCD_OPC_CheckPredicate, + 27, + 246, + 59, + 0, // Skip to: 19231 + /* 3881 */ MCD_OPC_Decode, + 227, + 16, + 203, + 1, // Opcode: VCGEhq + /* 3886 */ MCD_OPC_FilterValue, + 231, + 3, + 235, + 59, + 0, // Skip to: 19231 + /* 3892 */ MCD_OPC_CheckPredicate, + 28, + 230, + 59, + 0, // Skip to: 19231 + /* 3897 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 223, + 59, + 0, // Skip to: 19231 + /* 3904 */ MCD_OPC_Decode, + 209, + 24, + 213, + 1, // Opcode: VQRDMLAHslv8i16 + /* 3909 */ MCD_OPC_FilterValue, + 15, + 213, + 59, + 0, // Skip to: 19231 + /* 3914 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3917 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 3956 + /* 3923 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3926 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3941 + /* 3931 */ MCD_OPC_CheckPredicate, + 27, + 191, + 59, + 0, // Skip to: 19231 + /* 3936 */ MCD_OPC_Decode, + 143, + 22, + 202, + 1, // Opcode: VMAXhd + /* 3941 */ MCD_OPC_FilterValue, + 1, + 181, + 59, + 0, // Skip to: 19231 + /* 3946 */ MCD_OPC_CheckPredicate, + 27, + 176, + 59, + 0, // Skip to: 19231 + /* 3951 */ MCD_OPC_Decode, + 144, + 22, + 203, + 1, // Opcode: VMAXhq + /* 3956 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 3979 + /* 3962 */ MCD_OPC_CheckPredicate, + 28, + 160, + 59, + 0, // Skip to: 19231 + /* 3967 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 153, + 59, + 0, // Skip to: 19231 + /* 3974 */ MCD_OPC_Decode, + 215, + 24, + 212, + 1, // Opcode: VQRDMLSHslv4i16 + /* 3979 */ MCD_OPC_FilterValue, + 230, + 3, + 17, + 0, + 0, // Skip to: 4002 + /* 3985 */ MCD_OPC_CheckPredicate, + 27, + 137, + 59, + 0, // Skip to: 19231 + /* 3990 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 130, + 59, + 0, // Skip to: 19231 + /* 3997 */ MCD_OPC_Decode, + 134, + 24, + 202, + 1, // Opcode: VPMAXh + /* 4002 */ MCD_OPC_FilterValue, + 231, + 3, + 119, + 59, + 0, // Skip to: 19231 + /* 4008 */ MCD_OPC_CheckPredicate, + 28, + 114, + 59, + 0, // Skip to: 19231 + /* 4013 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 107, + 59, + 0, // Skip to: 19231 + /* 4020 */ MCD_OPC_Decode, + 217, + 24, + 213, + 1, // Opcode: VQRDMLSHslv8i16 + /* 4025 */ MCD_OPC_FilterValue, + 2, + 9, + 9, + 0, // Skip to: 6343 + /* 4030 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 4033 */ MCD_OPC_FilterValue, + 0, + 159, + 0, + 0, // Skip to: 4197 + /* 4038 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4041 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 4080 + /* 4047 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4050 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4065 + /* 4055 */ MCD_OPC_CheckPredicate, + 26, + 67, + 59, + 0, // Skip to: 19231 + /* 4060 */ MCD_OPC_Decode, + 238, + 18, + 202, + 1, // Opcode: VHADDsv2i32 + /* 4065 */ MCD_OPC_FilterValue, + 1, + 57, + 59, + 0, // Skip to: 19231 + /* 4070 */ MCD_OPC_CheckPredicate, + 26, + 52, + 59, + 0, // Skip to: 19231 + /* 4075 */ MCD_OPC_Decode, + 240, + 18, + 203, + 1, // Opcode: VHADDsv4i32 + /* 4080 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 4119 + /* 4086 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4089 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4104 + /* 4094 */ MCD_OPC_CheckPredicate, + 26, + 28, + 59, + 0, // Skip to: 19231 + /* 4099 */ MCD_OPC_Decode, + 155, + 16, + 204, + 1, // Opcode: VADDLsv2i64 + /* 4104 */ MCD_OPC_FilterValue, + 1, + 18, + 59, + 0, // Skip to: 19231 + /* 4109 */ MCD_OPC_CheckPredicate, + 26, + 13, + 59, + 0, // Skip to: 19231 + /* 4114 */ MCD_OPC_Decode, + 194, + 22, + 218, + 1, // Opcode: VMLAslv2i32 + /* 4119 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 4158 + /* 4125 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4128 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4143 + /* 4133 */ MCD_OPC_CheckPredicate, + 26, + 245, + 58, + 0, // Skip to: 19231 + /* 4138 */ MCD_OPC_Decode, + 244, + 18, + 202, + 1, // Opcode: VHADDuv2i32 + /* 4143 */ MCD_OPC_FilterValue, + 1, + 235, + 58, + 0, // Skip to: 19231 + /* 4148 */ MCD_OPC_CheckPredicate, + 26, + 230, + 58, + 0, // Skip to: 19231 + /* 4153 */ MCD_OPC_Decode, + 246, + 18, + 203, + 1, // Opcode: VHADDuv4i32 + /* 4158 */ MCD_OPC_FilterValue, + 231, + 3, + 219, + 58, + 0, // Skip to: 19231 + /* 4164 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4167 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4182 + /* 4172 */ MCD_OPC_CheckPredicate, + 26, + 206, + 58, + 0, // Skip to: 19231 + /* 4177 */ MCD_OPC_Decode, + 158, + 16, + 204, + 1, // Opcode: VADDLuv2i64 + /* 4182 */ MCD_OPC_FilterValue, + 1, + 196, + 58, + 0, // Skip to: 19231 + /* 4187 */ MCD_OPC_CheckPredicate, + 26, + 191, + 58, + 0, // Skip to: 19231 + /* 4192 */ MCD_OPC_Decode, + 196, + 22, + 219, + 1, // Opcode: VMLAslv4i32 + /* 4197 */ MCD_OPC_FilterValue, + 1, + 159, + 0, + 0, // Skip to: 4361 + /* 4202 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4205 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 4244 + /* 4211 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4214 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4229 + /* 4219 */ MCD_OPC_CheckPredicate, + 26, + 159, + 58, + 0, // Skip to: 19231 + /* 4224 */ MCD_OPC_Decode, + 218, + 25, + 202, + 1, // Opcode: VRHADDsv2i32 + /* 4229 */ MCD_OPC_FilterValue, + 1, + 149, + 58, + 0, // Skip to: 19231 + /* 4234 */ MCD_OPC_CheckPredicate, + 26, + 144, + 58, + 0, // Skip to: 19231 + /* 4239 */ MCD_OPC_Decode, + 220, + 25, + 203, + 1, // Opcode: VRHADDsv4i32 + /* 4244 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 4283 + /* 4250 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4253 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4268 + /* 4258 */ MCD_OPC_CheckPredicate, + 26, + 120, + 58, + 0, // Skip to: 19231 + /* 4263 */ MCD_OPC_Decode, + 162, + 16, + 205, + 1, // Opcode: VADDWsv2i64 + /* 4268 */ MCD_OPC_FilterValue, + 1, + 110, + 58, + 0, // Skip to: 19231 + /* 4273 */ MCD_OPC_CheckPredicate, + 26, + 105, + 58, + 0, // Skip to: 19231 + /* 4278 */ MCD_OPC_Decode, + 190, + 22, + 218, + 1, // Opcode: VMLAslfd + /* 4283 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 4322 + /* 4289 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4292 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4307 + /* 4297 */ MCD_OPC_CheckPredicate, + 26, + 81, + 58, + 0, // Skip to: 19231 + /* 4302 */ MCD_OPC_Decode, + 224, + 25, + 202, + 1, // Opcode: VRHADDuv2i32 + /* 4307 */ MCD_OPC_FilterValue, + 1, + 71, + 58, + 0, // Skip to: 19231 + /* 4312 */ MCD_OPC_CheckPredicate, + 26, + 66, + 58, + 0, // Skip to: 19231 + /* 4317 */ MCD_OPC_Decode, + 226, + 25, + 203, + 1, // Opcode: VRHADDuv4i32 + /* 4322 */ MCD_OPC_FilterValue, + 231, + 3, + 55, + 58, + 0, // Skip to: 19231 + /* 4328 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4331 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4346 + /* 4336 */ MCD_OPC_CheckPredicate, + 26, + 42, + 58, + 0, // Skip to: 19231 + /* 4341 */ MCD_OPC_Decode, + 165, + 16, + 205, + 1, // Opcode: VADDWuv2i64 + /* 4346 */ MCD_OPC_FilterValue, + 1, + 32, + 58, + 0, // Skip to: 19231 + /* 4351 */ MCD_OPC_CheckPredicate, + 26, + 27, + 58, + 0, // Skip to: 19231 + /* 4356 */ MCD_OPC_Decode, + 191, + 22, + 219, + 1, // Opcode: VMLAslfq + /* 4361 */ MCD_OPC_FilterValue, + 2, + 159, + 0, + 0, // Skip to: 4525 + /* 4366 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4369 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 4408 + /* 4375 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4378 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4393 + /* 4383 */ MCD_OPC_CheckPredicate, + 26, + 251, + 57, + 0, // Skip to: 19231 + /* 4388 */ MCD_OPC_Decode, + 250, + 18, + 202, + 1, // Opcode: VHSUBsv2i32 + /* 4393 */ MCD_OPC_FilterValue, + 1, + 241, + 57, + 0, // Skip to: 19231 + /* 4398 */ MCD_OPC_CheckPredicate, + 26, + 236, + 57, + 0, // Skip to: 19231 + /* 4403 */ MCD_OPC_Decode, + 252, + 18, + 203, + 1, // Opcode: VHSUBsv4i32 + /* 4408 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 4447 + /* 4414 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4417 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4432 + /* 4422 */ MCD_OPC_CheckPredicate, + 26, + 212, + 57, + 0, // Skip to: 19231 + /* 4427 */ MCD_OPC_Decode, + 235, + 29, + 204, + 1, // Opcode: VSUBLsv2i64 + /* 4432 */ MCD_OPC_FilterValue, + 1, + 202, + 57, + 0, // Skip to: 19231 + /* 4437 */ MCD_OPC_CheckPredicate, + 26, + 197, + 57, + 0, // Skip to: 19231 + /* 4442 */ MCD_OPC_Decode, + 175, + 22, + 220, + 1, // Opcode: VMLALslsv2i32 + /* 4447 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 4486 + /* 4453 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4456 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4471 + /* 4461 */ MCD_OPC_CheckPredicate, + 26, + 173, + 57, + 0, // Skip to: 19231 + /* 4466 */ MCD_OPC_Decode, + 128, + 19, + 202, + 1, // Opcode: VHSUBuv2i32 + /* 4471 */ MCD_OPC_FilterValue, + 1, + 163, + 57, + 0, // Skip to: 19231 + /* 4476 */ MCD_OPC_CheckPredicate, + 26, + 158, + 57, + 0, // Skip to: 19231 + /* 4481 */ MCD_OPC_Decode, + 130, + 19, + 203, + 1, // Opcode: VHSUBuv4i32 + /* 4486 */ MCD_OPC_FilterValue, + 231, + 3, + 147, + 57, + 0, // Skip to: 19231 + /* 4492 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4495 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4510 + /* 4500 */ MCD_OPC_CheckPredicate, + 26, + 134, + 57, + 0, // Skip to: 19231 + /* 4505 */ MCD_OPC_Decode, + 238, + 29, + 204, + 1, // Opcode: VSUBLuv2i64 + /* 4510 */ MCD_OPC_FilterValue, + 1, + 124, + 57, + 0, // Skip to: 19231 + /* 4515 */ MCD_OPC_CheckPredicate, + 26, + 119, + 57, + 0, // Skip to: 19231 + /* 4520 */ MCD_OPC_Decode, + 177, + 22, + 220, + 1, // Opcode: VMLALsluv2i32 + /* 4525 */ MCD_OPC_FilterValue, + 3, + 143, + 0, + 0, // Skip to: 4673 + /* 4530 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4533 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 4572 + /* 4539 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4542 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4557 + /* 4547 */ MCD_OPC_CheckPredicate, + 26, + 87, + 57, + 0, // Skip to: 19231 + /* 4552 */ MCD_OPC_Decode, + 255, + 16, + 202, + 1, // Opcode: VCGTsv2i32 + /* 4557 */ MCD_OPC_FilterValue, + 1, + 77, + 57, + 0, // Skip to: 19231 + /* 4562 */ MCD_OPC_CheckPredicate, + 26, + 72, + 57, + 0, // Skip to: 19231 + /* 4567 */ MCD_OPC_Decode, + 129, + 17, + 203, + 1, // Opcode: VCGTsv4i32 + /* 4572 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 4611 + /* 4578 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4581 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4596 + /* 4586 */ MCD_OPC_CheckPredicate, + 26, + 48, + 57, + 0, // Skip to: 19231 + /* 4591 */ MCD_OPC_Decode, + 242, + 29, + 205, + 1, // Opcode: VSUBWsv2i64 + /* 4596 */ MCD_OPC_FilterValue, + 1, + 38, + 57, + 0, // Skip to: 19231 + /* 4601 */ MCD_OPC_CheckPredicate, + 26, + 33, + 57, + 0, // Skip to: 19231 + /* 4606 */ MCD_OPC_Decode, + 171, + 24, + 220, + 1, // Opcode: VQDMLALslv2i32 + /* 4611 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 4650 + /* 4617 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4620 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4635 + /* 4625 */ MCD_OPC_CheckPredicate, + 26, + 9, + 57, + 0, // Skip to: 19231 + /* 4630 */ MCD_OPC_Decode, + 133, + 17, + 202, + 1, // Opcode: VCGTuv2i32 + /* 4635 */ MCD_OPC_FilterValue, + 1, + 255, + 56, + 0, // Skip to: 19231 + /* 4640 */ MCD_OPC_CheckPredicate, + 26, + 250, + 56, + 0, // Skip to: 19231 + /* 4645 */ MCD_OPC_Decode, + 135, + 17, + 203, + 1, // Opcode: VCGTuv4i32 + /* 4650 */ MCD_OPC_FilterValue, + 231, + 3, + 239, + 56, + 0, // Skip to: 19231 + /* 4656 */ MCD_OPC_CheckPredicate, + 26, + 234, + 56, + 0, // Skip to: 19231 + /* 4661 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 227, + 56, + 0, // Skip to: 19231 + /* 4668 */ MCD_OPC_Decode, + 245, + 29, + 205, + 1, // Opcode: VSUBWuv2i64 + /* 4673 */ MCD_OPC_FilterValue, + 4, + 159, + 0, + 0, // Skip to: 4837 + /* 4678 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4681 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 4720 + /* 4687 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4690 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4705 + /* 4695 */ MCD_OPC_CheckPredicate, + 26, + 195, + 56, + 0, // Skip to: 19231 + /* 4700 */ MCD_OPC_Decode, + 250, + 26, + 206, + 1, // Opcode: VSHLsv2i32 + /* 4705 */ MCD_OPC_FilterValue, + 1, + 185, + 56, + 0, // Skip to: 19231 + /* 4710 */ MCD_OPC_CheckPredicate, + 26, + 180, + 56, + 0, // Skip to: 19231 + /* 4715 */ MCD_OPC_Decode, + 253, + 26, + 207, + 1, // Opcode: VSHLsv4i32 + /* 4720 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 4759 + /* 4726 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4729 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4744 + /* 4734 */ MCD_OPC_CheckPredicate, + 26, + 156, + 56, + 0, // Skip to: 19231 + /* 4739 */ MCD_OPC_Decode, + 152, + 16, + 208, + 1, // Opcode: VADDHNv2i32 + /* 4744 */ MCD_OPC_FilterValue, + 1, + 146, + 56, + 0, // Skip to: 19231 + /* 4749 */ MCD_OPC_CheckPredicate, + 26, + 141, + 56, + 0, // Skip to: 19231 + /* 4754 */ MCD_OPC_Decode, + 225, + 22, + 218, + 1, // Opcode: VMLSslv2i32 + /* 4759 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 4798 + /* 4765 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4768 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4783 + /* 4773 */ MCD_OPC_CheckPredicate, + 26, + 117, + 56, + 0, // Skip to: 19231 + /* 4778 */ MCD_OPC_Decode, + 130, + 27, + 206, + 1, // Opcode: VSHLuv2i32 + /* 4783 */ MCD_OPC_FilterValue, + 1, + 107, + 56, + 0, // Skip to: 19231 + /* 4788 */ MCD_OPC_CheckPredicate, + 26, + 102, + 56, + 0, // Skip to: 19231 + /* 4793 */ MCD_OPC_Decode, + 133, + 27, + 207, + 1, // Opcode: VSHLuv4i32 + /* 4798 */ MCD_OPC_FilterValue, + 231, + 3, + 91, + 56, + 0, // Skip to: 19231 + /* 4804 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4807 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4822 + /* 4812 */ MCD_OPC_CheckPredicate, + 26, + 78, + 56, + 0, // Skip to: 19231 + /* 4817 */ MCD_OPC_Decode, + 192, + 25, + 208, + 1, // Opcode: VRADDHNv2i32 + /* 4822 */ MCD_OPC_FilterValue, + 1, + 68, + 56, + 0, // Skip to: 19231 + /* 4827 */ MCD_OPC_CheckPredicate, + 26, + 63, + 56, + 0, // Skip to: 19231 + /* 4832 */ MCD_OPC_Decode, + 227, + 22, + 219, + 1, // Opcode: VMLSslv4i32 + /* 4837 */ MCD_OPC_FilterValue, + 5, + 159, + 0, + 0, // Skip to: 5001 + /* 4842 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4845 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 4884 + /* 4851 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4854 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4869 + /* 4859 */ MCD_OPC_CheckPredicate, + 26, + 31, + 56, + 0, // Skip to: 19231 + /* 4864 */ MCD_OPC_Decode, + 148, + 26, + 206, + 1, // Opcode: VRSHLsv2i32 + /* 4869 */ MCD_OPC_FilterValue, + 1, + 21, + 56, + 0, // Skip to: 19231 + /* 4874 */ MCD_OPC_CheckPredicate, + 26, + 16, + 56, + 0, // Skip to: 19231 + /* 4879 */ MCD_OPC_Decode, + 151, + 26, + 207, + 1, // Opcode: VRSHLsv4i32 + /* 4884 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 4923 + /* 4890 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4893 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4908 + /* 4898 */ MCD_OPC_CheckPredicate, + 26, + 248, + 55, + 0, // Skip to: 19231 + /* 4903 */ MCD_OPC_Decode, + 217, + 15, + 209, + 1, // Opcode: VABALsv2i64 + /* 4908 */ MCD_OPC_FilterValue, + 1, + 238, + 55, + 0, // Skip to: 19231 + /* 4913 */ MCD_OPC_CheckPredicate, + 26, + 233, + 55, + 0, // Skip to: 19231 + /* 4918 */ MCD_OPC_Decode, + 221, + 22, + 218, + 1, // Opcode: VMLSslfd + /* 4923 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 4962 + /* 4929 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4932 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4947 + /* 4937 */ MCD_OPC_CheckPredicate, + 26, + 209, + 55, + 0, // Skip to: 19231 + /* 4942 */ MCD_OPC_Decode, + 156, + 26, + 206, + 1, // Opcode: VRSHLuv2i32 + /* 4947 */ MCD_OPC_FilterValue, + 1, + 199, + 55, + 0, // Skip to: 19231 + /* 4952 */ MCD_OPC_CheckPredicate, + 26, + 194, + 55, + 0, // Skip to: 19231 + /* 4957 */ MCD_OPC_Decode, + 159, + 26, + 207, + 1, // Opcode: VRSHLuv4i32 + /* 4962 */ MCD_OPC_FilterValue, + 231, + 3, + 183, + 55, + 0, // Skip to: 19231 + /* 4968 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4971 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4986 + /* 4976 */ MCD_OPC_CheckPredicate, + 26, + 170, + 55, + 0, // Skip to: 19231 + /* 4981 */ MCD_OPC_Decode, + 220, + 15, + 209, + 1, // Opcode: VABALuv2i64 + /* 4986 */ MCD_OPC_FilterValue, + 1, + 160, + 55, + 0, // Skip to: 19231 + /* 4991 */ MCD_OPC_CheckPredicate, + 26, + 155, + 55, + 0, // Skip to: 19231 + /* 4996 */ MCD_OPC_Decode, + 222, + 22, + 219, + 1, // Opcode: VMLSslfq + /* 5001 */ MCD_OPC_FilterValue, + 6, + 159, + 0, + 0, // Skip to: 5165 + /* 5006 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5009 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 5048 + /* 5015 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5018 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5033 + /* 5023 */ MCD_OPC_CheckPredicate, + 26, + 123, + 55, + 0, // Skip to: 19231 + /* 5028 */ MCD_OPC_Decode, + 146, + 22, + 202, + 1, // Opcode: VMAXsv2i32 + /* 5033 */ MCD_OPC_FilterValue, + 1, + 113, + 55, + 0, // Skip to: 19231 + /* 5038 */ MCD_OPC_CheckPredicate, + 26, + 108, + 55, + 0, // Skip to: 19231 + /* 5043 */ MCD_OPC_Decode, + 148, + 22, + 203, + 1, // Opcode: VMAXsv4i32 + /* 5048 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 5087 + /* 5054 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5057 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5072 + /* 5062 */ MCD_OPC_CheckPredicate, + 26, + 84, + 55, + 0, // Skip to: 19231 + /* 5067 */ MCD_OPC_Decode, + 232, + 29, + 208, + 1, // Opcode: VSUBHNv2i32 + /* 5072 */ MCD_OPC_FilterValue, + 1, + 74, + 55, + 0, // Skip to: 19231 + /* 5077 */ MCD_OPC_CheckPredicate, + 26, + 69, + 55, + 0, // Skip to: 19231 + /* 5082 */ MCD_OPC_Decode, + 206, + 22, + 220, + 1, // Opcode: VMLSLslsv2i32 + /* 5087 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 5126 + /* 5093 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5096 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5111 + /* 5101 */ MCD_OPC_CheckPredicate, + 26, + 45, + 55, + 0, // Skip to: 19231 + /* 5106 */ MCD_OPC_Decode, + 152, + 22, + 202, + 1, // Opcode: VMAXuv2i32 + /* 5111 */ MCD_OPC_FilterValue, + 1, + 35, + 55, + 0, // Skip to: 19231 + /* 5116 */ MCD_OPC_CheckPredicate, + 26, + 30, + 55, + 0, // Skip to: 19231 + /* 5121 */ MCD_OPC_Decode, + 154, + 22, + 203, + 1, // Opcode: VMAXuv4i32 + /* 5126 */ MCD_OPC_FilterValue, + 231, + 3, + 19, + 55, + 0, // Skip to: 19231 + /* 5132 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5135 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5150 + /* 5140 */ MCD_OPC_CheckPredicate, + 26, + 6, + 55, + 0, // Skip to: 19231 + /* 5145 */ MCD_OPC_Decode, + 207, + 26, + 208, + 1, // Opcode: VRSUBHNv2i32 + /* 5150 */ MCD_OPC_FilterValue, + 1, + 252, + 54, + 0, // Skip to: 19231 + /* 5155 */ MCD_OPC_CheckPredicate, + 26, + 247, + 54, + 0, // Skip to: 19231 + /* 5160 */ MCD_OPC_Decode, + 208, + 22, + 220, + 1, // Opcode: VMLSLsluv2i32 + /* 5165 */ MCD_OPC_FilterValue, + 7, + 143, + 0, + 0, // Skip to: 5313 + /* 5170 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5173 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 5212 + /* 5179 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5182 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5197 + /* 5187 */ MCD_OPC_CheckPredicate, + 26, + 215, + 54, + 0, // Skip to: 19231 + /* 5192 */ MCD_OPC_Decode, + 246, + 15, + 202, + 1, // Opcode: VABDsv2i32 + /* 5197 */ MCD_OPC_FilterValue, + 1, + 205, + 54, + 0, // Skip to: 19231 + /* 5202 */ MCD_OPC_CheckPredicate, + 26, + 200, + 54, + 0, // Skip to: 19231 + /* 5207 */ MCD_OPC_Decode, + 248, + 15, + 203, + 1, // Opcode: VABDsv4i32 + /* 5212 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 5251 + /* 5218 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5221 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5236 + /* 5226 */ MCD_OPC_CheckPredicate, + 26, + 176, + 54, + 0, // Skip to: 19231 + /* 5231 */ MCD_OPC_Decode, + 235, + 15, + 204, + 1, // Opcode: VABDLsv2i64 + /* 5236 */ MCD_OPC_FilterValue, + 1, + 166, + 54, + 0, // Skip to: 19231 + /* 5241 */ MCD_OPC_CheckPredicate, + 26, + 161, + 54, + 0, // Skip to: 19231 + /* 5246 */ MCD_OPC_Decode, + 175, + 24, + 220, + 1, // Opcode: VQDMLSLslv2i32 + /* 5251 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 5290 + /* 5257 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5260 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5275 + /* 5265 */ MCD_OPC_CheckPredicate, + 26, + 137, + 54, + 0, // Skip to: 19231 + /* 5270 */ MCD_OPC_Decode, + 252, + 15, + 202, + 1, // Opcode: VABDuv2i32 + /* 5275 */ MCD_OPC_FilterValue, + 1, + 127, + 54, + 0, // Skip to: 19231 + /* 5280 */ MCD_OPC_CheckPredicate, + 26, + 122, + 54, + 0, // Skip to: 19231 + /* 5285 */ MCD_OPC_Decode, + 254, + 15, + 203, + 1, // Opcode: VABDuv4i32 + /* 5290 */ MCD_OPC_FilterValue, + 231, + 3, + 111, + 54, + 0, // Skip to: 19231 + /* 5296 */ MCD_OPC_CheckPredicate, + 26, + 106, + 54, + 0, // Skip to: 19231 + /* 5301 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 99, + 54, + 0, // Skip to: 19231 + /* 5308 */ MCD_OPC_Decode, + 238, + 15, + 204, + 1, // Opcode: VABDLuv2i64 + /* 5313 */ MCD_OPC_FilterValue, + 8, + 159, + 0, + 0, // Skip to: 5477 + /* 5318 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5321 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 5360 + /* 5327 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5330 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5345 + /* 5335 */ MCD_OPC_CheckPredicate, + 26, + 67, + 54, + 0, // Skip to: 19231 + /* 5340 */ MCD_OPC_Decode, + 174, + 16, + 202, + 1, // Opcode: VADDv2i32 + /* 5345 */ MCD_OPC_FilterValue, + 1, + 57, + 54, + 0, // Skip to: 19231 + /* 5350 */ MCD_OPC_CheckPredicate, + 26, + 52, + 54, + 0, // Skip to: 19231 + /* 5355 */ MCD_OPC_Decode, + 177, + 16, + 203, + 1, // Opcode: VADDv4i32 + /* 5360 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 5399 + /* 5366 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5369 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5384 + /* 5374 */ MCD_OPC_CheckPredicate, + 26, + 28, + 54, + 0, // Skip to: 19231 + /* 5379 */ MCD_OPC_Decode, + 179, + 22, + 209, + 1, // Opcode: VMLALsv2i64 + /* 5384 */ MCD_OPC_FilterValue, + 1, + 18, + 54, + 0, // Skip to: 19231 + /* 5389 */ MCD_OPC_CheckPredicate, + 26, + 13, + 54, + 0, // Skip to: 19231 + /* 5394 */ MCD_OPC_Decode, + 186, + 23, + 221, + 1, // Opcode: VMULslv2i32 + /* 5399 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 5438 + /* 5405 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5408 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5423 + /* 5413 */ MCD_OPC_CheckPredicate, + 26, + 245, + 53, + 0, // Skip to: 19231 + /* 5418 */ MCD_OPC_Decode, + 254, + 29, + 202, + 1, // Opcode: VSUBv2i32 + /* 5423 */ MCD_OPC_FilterValue, + 1, + 235, + 53, + 0, // Skip to: 19231 + /* 5428 */ MCD_OPC_CheckPredicate, + 26, + 230, + 53, + 0, // Skip to: 19231 + /* 5433 */ MCD_OPC_Decode, + 129, + 30, + 203, + 1, // Opcode: VSUBv4i32 + /* 5438 */ MCD_OPC_FilterValue, + 231, + 3, + 219, + 53, + 0, // Skip to: 19231 + /* 5444 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5447 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5462 + /* 5452 */ MCD_OPC_CheckPredicate, + 26, + 206, + 53, + 0, // Skip to: 19231 + /* 5457 */ MCD_OPC_Decode, + 182, + 22, + 209, + 1, // Opcode: VMLALuv2i64 + /* 5462 */ MCD_OPC_FilterValue, + 1, + 196, + 53, + 0, // Skip to: 19231 + /* 5467 */ MCD_OPC_CheckPredicate, + 26, + 191, + 53, + 0, // Skip to: 19231 + /* 5472 */ MCD_OPC_Decode, + 188, + 23, + 222, + 1, // Opcode: VMULslv4i32 + /* 5477 */ MCD_OPC_FilterValue, + 9, + 143, + 0, + 0, // Skip to: 5625 + /* 5482 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5485 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 5524 + /* 5491 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5494 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5509 + /* 5499 */ MCD_OPC_CheckPredicate, + 26, + 159, + 53, + 0, // Skip to: 19231 + /* 5504 */ MCD_OPC_Decode, + 199, + 22, + 210, + 1, // Opcode: VMLAv2i32 + /* 5509 */ MCD_OPC_FilterValue, + 1, + 149, + 53, + 0, // Skip to: 19231 + /* 5514 */ MCD_OPC_CheckPredicate, + 26, + 144, + 53, + 0, // Skip to: 19231 + /* 5519 */ MCD_OPC_Decode, + 201, + 22, + 211, + 1, // Opcode: VMLAv4i32 + /* 5524 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 5563 + /* 5530 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5533 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5548 + /* 5538 */ MCD_OPC_CheckPredicate, + 26, + 120, + 53, + 0, // Skip to: 19231 + /* 5543 */ MCD_OPC_Decode, + 173, + 24, + 209, + 1, // Opcode: VQDMLALv2i64 + /* 5548 */ MCD_OPC_FilterValue, + 1, + 110, + 53, + 0, // Skip to: 19231 + /* 5553 */ MCD_OPC_CheckPredicate, + 26, + 105, + 53, + 0, // Skip to: 19231 + /* 5558 */ MCD_OPC_Decode, + 182, + 23, + 221, + 1, // Opcode: VMULslfd + /* 5563 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 5602 + /* 5569 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5572 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5587 + /* 5577 */ MCD_OPC_CheckPredicate, + 26, + 81, + 53, + 0, // Skip to: 19231 + /* 5582 */ MCD_OPC_Decode, + 230, + 22, + 210, + 1, // Opcode: VMLSv2i32 + /* 5587 */ MCD_OPC_FilterValue, + 1, + 71, + 53, + 0, // Skip to: 19231 + /* 5592 */ MCD_OPC_CheckPredicate, + 26, + 66, + 53, + 0, // Skip to: 19231 + /* 5597 */ MCD_OPC_Decode, + 232, + 22, + 211, + 1, // Opcode: VMLSv4i32 + /* 5602 */ MCD_OPC_FilterValue, + 231, + 3, + 55, + 53, + 0, // Skip to: 19231 + /* 5608 */ MCD_OPC_CheckPredicate, + 26, + 50, + 53, + 0, // Skip to: 19231 + /* 5613 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 43, + 53, + 0, // Skip to: 19231 + /* 5620 */ MCD_OPC_Decode, + 183, + 23, + 222, + 1, // Opcode: VMULslfq + /* 5625 */ MCD_OPC_FilterValue, + 10, + 127, + 0, + 0, // Skip to: 5757 + /* 5630 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5633 */ MCD_OPC_FilterValue, + 228, + 3, + 17, + 0, + 0, // Skip to: 5656 + /* 5639 */ MCD_OPC_CheckPredicate, + 26, + 19, + 53, + 0, // Skip to: 19231 + /* 5644 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 12, + 53, + 0, // Skip to: 19231 + /* 5651 */ MCD_OPC_Decode, + 136, + 24, + 202, + 1, // Opcode: VPMAXs32 + /* 5656 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 5695 + /* 5662 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5665 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5680 + /* 5670 */ MCD_OPC_CheckPredicate, + 26, + 244, + 52, + 0, // Skip to: 19231 + /* 5675 */ MCD_OPC_Decode, + 210, + 22, + 209, + 1, // Opcode: VMLSLsv2i64 + /* 5680 */ MCD_OPC_FilterValue, + 1, + 234, + 52, + 0, // Skip to: 19231 + /* 5685 */ MCD_OPC_CheckPredicate, + 26, + 229, + 52, + 0, // Skip to: 19231 + /* 5690 */ MCD_OPC_Decode, + 165, + 23, + 223, + 1, // Opcode: VMULLslsv2i32 + /* 5695 */ MCD_OPC_FilterValue, + 230, + 3, + 17, + 0, + 0, // Skip to: 5718 + /* 5701 */ MCD_OPC_CheckPredicate, + 26, + 213, + 52, + 0, // Skip to: 19231 + /* 5706 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 206, + 52, + 0, // Skip to: 19231 + /* 5713 */ MCD_OPC_Decode, + 139, + 24, + 202, + 1, // Opcode: VPMAXu32 + /* 5718 */ MCD_OPC_FilterValue, + 231, + 3, + 195, + 52, + 0, // Skip to: 19231 + /* 5724 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5727 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5742 + /* 5732 */ MCD_OPC_CheckPredicate, + 26, + 182, + 52, + 0, // Skip to: 19231 + /* 5737 */ MCD_OPC_Decode, + 213, + 22, + 209, + 1, // Opcode: VMLSLuv2i64 + /* 5742 */ MCD_OPC_FilterValue, + 1, + 172, + 52, + 0, // Skip to: 19231 + /* 5747 */ MCD_OPC_CheckPredicate, + 26, + 167, + 52, + 0, // Skip to: 19231 + /* 5752 */ MCD_OPC_Decode, + 167, + 23, + 223, + 1, // Opcode: VMULLsluv2i32 + /* 5757 */ MCD_OPC_FilterValue, + 11, + 120, + 0, + 0, // Skip to: 5882 + /* 5762 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5765 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 5804 + /* 5771 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5774 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5789 + /* 5779 */ MCD_OPC_CheckPredicate, + 26, + 135, + 52, + 0, // Skip to: 19231 + /* 5784 */ MCD_OPC_Decode, + 183, + 24, + 202, + 1, // Opcode: VQDMULHv2i32 + /* 5789 */ MCD_OPC_FilterValue, + 1, + 125, + 52, + 0, // Skip to: 19231 + /* 5794 */ MCD_OPC_CheckPredicate, + 26, + 120, + 52, + 0, // Skip to: 19231 + /* 5799 */ MCD_OPC_Decode, + 185, + 24, + 203, + 1, // Opcode: VQDMULHv4i32 + /* 5804 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 5843 + /* 5810 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5813 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5828 + /* 5818 */ MCD_OPC_CheckPredicate, + 26, + 96, + 52, + 0, // Skip to: 19231 + /* 5823 */ MCD_OPC_Decode, + 177, + 24, + 209, + 1, // Opcode: VQDMLSLv2i64 + /* 5828 */ MCD_OPC_FilterValue, + 1, + 86, + 52, + 0, // Skip to: 19231 + /* 5833 */ MCD_OPC_CheckPredicate, + 26, + 81, + 52, + 0, // Skip to: 19231 + /* 5838 */ MCD_OPC_Decode, + 187, + 24, + 223, + 1, // Opcode: VQDMULLslv2i32 + /* 5843 */ MCD_OPC_FilterValue, + 230, + 3, + 70, + 52, + 0, // Skip to: 19231 + /* 5849 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5852 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5867 + /* 5857 */ MCD_OPC_CheckPredicate, + 26, + 57, + 52, + 0, // Skip to: 19231 + /* 5862 */ MCD_OPC_Decode, + 226, + 24, + 202, + 1, // Opcode: VQRDMULHv2i32 + /* 5867 */ MCD_OPC_FilterValue, + 1, + 47, + 52, + 0, // Skip to: 19231 + /* 5872 */ MCD_OPC_CheckPredicate, + 26, + 42, + 52, + 0, // Skip to: 19231 + /* 5877 */ MCD_OPC_Decode, + 228, + 24, + 203, + 1, // Opcode: VQRDMULHv4i32 + /* 5882 */ MCD_OPC_FilterValue, + 12, + 83, + 0, + 0, // Skip to: 5970 + /* 5887 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5890 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 5930 + /* 5895 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5898 */ MCD_OPC_FilterValue, + 229, + 3, + 10, + 0, + 0, // Skip to: 5914 + /* 5904 */ MCD_OPC_CheckPredicate, + 26, + 10, + 52, + 0, // Skip to: 19231 + /* 5909 */ MCD_OPC_Decode, + 169, + 23, + 204, + 1, // Opcode: VMULLsv2i64 + /* 5914 */ MCD_OPC_FilterValue, + 231, + 3, + 255, + 51, + 0, // Skip to: 19231 + /* 5920 */ MCD_OPC_CheckPredicate, + 26, + 250, + 51, + 0, // Skip to: 19231 + /* 5925 */ MCD_OPC_Decode, + 172, + 23, + 204, + 1, // Opcode: VMULLuv2i64 + /* 5930 */ MCD_OPC_FilterValue, + 1, + 240, + 51, + 0, // Skip to: 19231 + /* 5935 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5938 */ MCD_OPC_FilterValue, + 229, + 3, + 10, + 0, + 0, // Skip to: 5954 + /* 5944 */ MCD_OPC_CheckPredicate, + 26, + 226, + 51, + 0, // Skip to: 19231 + /* 5949 */ MCD_OPC_Decode, + 179, + 24, + 221, + 1, // Opcode: VQDMULHslv2i32 + /* 5954 */ MCD_OPC_FilterValue, + 231, + 3, + 215, + 51, + 0, // Skip to: 19231 + /* 5960 */ MCD_OPC_CheckPredicate, + 26, + 210, + 51, + 0, // Skip to: 19231 + /* 5965 */ MCD_OPC_Decode, + 181, + 24, + 222, + 1, // Opcode: VQDMULHslv4i32 + /* 5970 */ MCD_OPC_FilterValue, + 13, + 143, + 0, + 0, // Skip to: 6118 + /* 5975 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5978 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 6017 + /* 5984 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5987 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6002 + /* 5992 */ MCD_OPC_CheckPredicate, + 26, + 178, + 51, + 0, // Skip to: 19231 + /* 5997 */ MCD_OPC_Decode, + 248, + 29, + 202, + 1, // Opcode: VSUBfd + /* 6002 */ MCD_OPC_FilterValue, + 1, + 168, + 51, + 0, // Skip to: 19231 + /* 6007 */ MCD_OPC_CheckPredicate, + 26, + 163, + 51, + 0, // Skip to: 19231 + /* 6012 */ MCD_OPC_Decode, + 249, + 29, + 203, + 1, // Opcode: VSUBfq + /* 6017 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 6056 + /* 6023 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6026 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6041 + /* 6031 */ MCD_OPC_CheckPredicate, + 26, + 139, + 51, + 0, // Skip to: 19231 + /* 6036 */ MCD_OPC_Decode, + 189, + 24, + 204, + 1, // Opcode: VQDMULLv2i64 + /* 6041 */ MCD_OPC_FilterValue, + 1, + 129, + 51, + 0, // Skip to: 19231 + /* 6046 */ MCD_OPC_CheckPredicate, + 26, + 124, + 51, + 0, // Skip to: 19231 + /* 6051 */ MCD_OPC_Decode, + 222, + 24, + 221, + 1, // Opcode: VQRDMULHslv2i32 + /* 6056 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 6095 + /* 6062 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6065 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6080 + /* 6070 */ MCD_OPC_CheckPredicate, + 26, + 100, + 51, + 0, // Skip to: 19231 + /* 6075 */ MCD_OPC_Decode, + 241, + 15, + 202, + 1, // Opcode: VABDfd + /* 6080 */ MCD_OPC_FilterValue, + 1, + 90, + 51, + 0, // Skip to: 19231 + /* 6085 */ MCD_OPC_CheckPredicate, + 26, + 85, + 51, + 0, // Skip to: 19231 + /* 6090 */ MCD_OPC_Decode, + 242, + 15, + 203, + 1, // Opcode: VABDfq + /* 6095 */ MCD_OPC_FilterValue, + 231, + 3, + 74, + 51, + 0, // Skip to: 19231 + /* 6101 */ MCD_OPC_CheckPredicate, + 26, + 69, + 51, + 0, // Skip to: 19231 + /* 6106 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 62, + 51, + 0, // Skip to: 19231 + /* 6113 */ MCD_OPC_Decode, + 224, + 24, + 222, + 1, // Opcode: VQRDMULHslv4i32 + /* 6118 */ MCD_OPC_FilterValue, + 14, + 104, + 0, + 0, // Skip to: 6227 + /* 6123 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6126 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 6165 + /* 6132 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6135 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6150 + /* 6140 */ MCD_OPC_CheckPredicate, + 29, + 30, + 51, + 0, // Skip to: 19231 + /* 6145 */ MCD_OPC_Decode, + 163, + 23, + 204, + 1, // Opcode: VMULLp64 + /* 6150 */ MCD_OPC_FilterValue, + 1, + 20, + 51, + 0, // Skip to: 19231 + /* 6155 */ MCD_OPC_CheckPredicate, + 28, + 15, + 51, + 0, // Skip to: 19231 + /* 6160 */ MCD_OPC_Decode, + 206, + 24, + 218, + 1, // Opcode: VQRDMLAHslv2i32 + /* 6165 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 6204 + /* 6171 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6174 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6189 + /* 6179 */ MCD_OPC_CheckPredicate, + 26, + 247, + 50, + 0, // Skip to: 19231 + /* 6184 */ MCD_OPC_Decode, + 250, + 16, + 202, + 1, // Opcode: VCGTfd + /* 6189 */ MCD_OPC_FilterValue, + 1, + 237, + 50, + 0, // Skip to: 19231 + /* 6194 */ MCD_OPC_CheckPredicate, + 26, + 232, + 50, + 0, // Skip to: 19231 + /* 6199 */ MCD_OPC_Decode, + 251, + 16, + 203, + 1, // Opcode: VCGTfq + /* 6204 */ MCD_OPC_FilterValue, + 231, + 3, + 221, + 50, + 0, // Skip to: 19231 + /* 6210 */ MCD_OPC_CheckPredicate, + 28, + 216, + 50, + 0, // Skip to: 19231 + /* 6215 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 209, + 50, + 0, // Skip to: 19231 + /* 6222 */ MCD_OPC_Decode, + 208, + 24, + 219, + 1, // Opcode: VQRDMLAHslv4i32 + /* 6227 */ MCD_OPC_FilterValue, + 15, + 199, + 50, + 0, // Skip to: 19231 + /* 6232 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6235 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 6274 + /* 6241 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6244 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6259 + /* 6249 */ MCD_OPC_CheckPredicate, + 26, + 177, + 50, + 0, // Skip to: 19231 + /* 6254 */ MCD_OPC_Decode, + 157, + 22, + 202, + 1, // Opcode: VMINfd + /* 6259 */ MCD_OPC_FilterValue, + 1, + 167, + 50, + 0, // Skip to: 19231 + /* 6264 */ MCD_OPC_CheckPredicate, + 26, + 162, + 50, + 0, // Skip to: 19231 + /* 6269 */ MCD_OPC_Decode, + 158, + 22, + 203, + 1, // Opcode: VMINfq + /* 6274 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 6297 + /* 6280 */ MCD_OPC_CheckPredicate, + 28, + 146, + 50, + 0, // Skip to: 19231 + /* 6285 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 139, + 50, + 0, // Skip to: 19231 + /* 6292 */ MCD_OPC_Decode, + 214, + 24, + 218, + 1, // Opcode: VQRDMLSHslv2i32 + /* 6297 */ MCD_OPC_FilterValue, + 230, + 3, + 17, + 0, + 0, // Skip to: 6320 + /* 6303 */ MCD_OPC_CheckPredicate, + 26, + 123, + 50, + 0, // Skip to: 19231 + /* 6308 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 116, + 50, + 0, // Skip to: 19231 + /* 6315 */ MCD_OPC_Decode, + 141, + 24, + 202, + 1, // Opcode: VPMINf + /* 6320 */ MCD_OPC_FilterValue, + 231, + 3, + 105, + 50, + 0, // Skip to: 19231 + /* 6326 */ MCD_OPC_CheckPredicate, + 28, + 100, + 50, + 0, // Skip to: 19231 + /* 6331 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 93, + 50, + 0, // Skip to: 19231 + /* 6338 */ MCD_OPC_Decode, + 216, + 24, + 219, + 1, // Opcode: VQRDMLSHslv4i32 + /* 6343 */ MCD_OPC_FilterValue, + 3, + 83, + 50, + 0, // Skip to: 19231 + /* 6348 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6351 */ MCD_OPC_FilterValue, + 228, + 3, + 193, + 0, + 0, // Skip to: 6550 + /* 6357 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 6360 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 6398 + /* 6365 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6368 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6383 + /* 6373 */ MCD_OPC_CheckPredicate, + 26, + 53, + 50, + 0, // Skip to: 19231 + /* 6378 */ MCD_OPC_Decode, + 249, + 26, + 206, + 1, // Opcode: VSHLsv1i64 + /* 6383 */ MCD_OPC_FilterValue, + 1, + 43, + 50, + 0, // Skip to: 19231 + /* 6388 */ MCD_OPC_CheckPredicate, + 26, + 38, + 50, + 0, // Skip to: 19231 + /* 6393 */ MCD_OPC_Decode, + 251, + 26, + 207, + 1, // Opcode: VSHLsv2i64 + /* 6398 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 6436 + /* 6403 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6406 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6421 + /* 6411 */ MCD_OPC_CheckPredicate, + 26, + 15, + 50, + 0, // Skip to: 19231 + /* 6416 */ MCD_OPC_Decode, + 147, + 26, + 206, + 1, // Opcode: VRSHLsv1i64 + /* 6421 */ MCD_OPC_FilterValue, + 1, + 5, + 50, + 0, // Skip to: 19231 + /* 6426 */ MCD_OPC_CheckPredicate, + 26, + 0, + 50, + 0, // Skip to: 19231 + /* 6431 */ MCD_OPC_Decode, + 149, + 26, + 207, + 1, // Opcode: VRSHLsv2i64 + /* 6436 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 6474 + /* 6441 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6444 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6459 + /* 6449 */ MCD_OPC_CheckPredicate, + 26, + 233, + 49, + 0, // Skip to: 19231 + /* 6454 */ MCD_OPC_Decode, + 173, + 16, + 202, + 1, // Opcode: VADDv1i64 + /* 6459 */ MCD_OPC_FilterValue, + 1, + 223, + 49, + 0, // Skip to: 19231 + /* 6464 */ MCD_OPC_CheckPredicate, + 26, + 218, + 49, + 0, // Skip to: 19231 + /* 6469 */ MCD_OPC_Decode, + 175, + 16, + 203, + 1, // Opcode: VADDv2i64 + /* 6474 */ MCD_OPC_FilterValue, + 13, + 33, + 0, + 0, // Skip to: 6512 + /* 6479 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6482 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6497 + /* 6487 */ MCD_OPC_CheckPredicate, + 27, + 195, + 49, + 0, // Skip to: 19231 + /* 6492 */ MCD_OPC_Decode, + 250, + 29, + 202, + 1, // Opcode: VSUBhd + /* 6497 */ MCD_OPC_FilterValue, + 1, + 185, + 49, + 0, // Skip to: 19231 + /* 6502 */ MCD_OPC_CheckPredicate, + 27, + 180, + 49, + 0, // Skip to: 19231 + /* 6507 */ MCD_OPC_Decode, + 251, + 29, + 203, + 1, // Opcode: VSUBhq + /* 6512 */ MCD_OPC_FilterValue, + 15, + 170, + 49, + 0, // Skip to: 19231 + /* 6517 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6520 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6535 + /* 6525 */ MCD_OPC_CheckPredicate, + 27, + 157, + 49, + 0, // Skip to: 19231 + /* 6530 */ MCD_OPC_Decode, + 159, + 22, + 202, + 1, // Opcode: VMINhd + /* 6535 */ MCD_OPC_FilterValue, + 1, + 147, + 49, + 0, // Skip to: 19231 + /* 6540 */ MCD_OPC_CheckPredicate, + 27, + 142, + 49, + 0, // Skip to: 19231 + /* 6545 */ MCD_OPC_Decode, + 160, + 22, + 203, + 1, // Opcode: VMINhq + /* 6550 */ MCD_OPC_FilterValue, + 229, + 3, + 126, + 0, + 0, // Skip to: 6682 + /* 6556 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6559 */ MCD_OPC_FilterValue, + 0, + 52, + 0, + 0, // Skip to: 6616 + /* 6564 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 6567 */ MCD_OPC_FilterValue, + 0, + 115, + 49, + 0, // Skip to: 19231 + /* 6572 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6589 + /* 6577 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 5, + 0, + 0, // Skip to: 6589 + /* 6584 */ MCD_OPC_Decode, + 192, + 18, + 224, + 1, // Opcode: VEXTd32 + /* 6589 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6606 + /* 6594 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 5, + 0, + 0, // Skip to: 6606 + /* 6601 */ MCD_OPC_Decode, + 191, + 18, + 225, + 1, // Opcode: VEXTd16 + /* 6606 */ MCD_OPC_CheckPredicate, + 26, + 76, + 49, + 0, // Skip to: 19231 + /* 6611 */ MCD_OPC_Decode, + 193, + 18, + 226, + 1, // Opcode: VEXTd8 + /* 6616 */ MCD_OPC_FilterValue, + 1, + 66, + 49, + 0, // Skip to: 19231 + /* 6621 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6638 + /* 6626 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 5, + 0, + 0, // Skip to: 6638 + /* 6633 */ MCD_OPC_Decode, + 196, + 18, + 227, + 1, // Opcode: VEXTq64 + /* 6638 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6655 + /* 6643 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 5, + 0, + 0, // Skip to: 6655 + /* 6650 */ MCD_OPC_Decode, + 195, + 18, + 228, + 1, // Opcode: VEXTq32 + /* 6655 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6672 + /* 6660 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 5, + 0, + 0, // Skip to: 6672 + /* 6667 */ MCD_OPC_Decode, + 194, + 18, + 229, + 1, // Opcode: VEXTq16 + /* 6672 */ MCD_OPC_CheckPredicate, + 26, + 10, + 49, + 0, // Skip to: 19231 + /* 6677 */ MCD_OPC_Decode, + 197, + 18, + 230, + 1, // Opcode: VEXTq8 + /* 6682 */ MCD_OPC_FilterValue, + 230, + 3, + 215, + 0, + 0, // Skip to: 6903 + /* 6688 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 6691 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 6729 + /* 6696 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6699 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6714 + /* 6704 */ MCD_OPC_CheckPredicate, + 26, + 234, + 48, + 0, // Skip to: 19231 + /* 6709 */ MCD_OPC_Decode, + 129, + 27, + 206, + 1, // Opcode: VSHLuv1i64 + /* 6714 */ MCD_OPC_FilterValue, + 1, + 224, + 48, + 0, // Skip to: 19231 + /* 6719 */ MCD_OPC_CheckPredicate, + 26, + 219, + 48, + 0, // Skip to: 19231 + /* 6724 */ MCD_OPC_Decode, + 131, + 27, + 207, + 1, // Opcode: VSHLuv2i64 + /* 6729 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 6767 + /* 6734 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6737 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6752 + /* 6742 */ MCD_OPC_CheckPredicate, + 26, + 196, + 48, + 0, // Skip to: 19231 + /* 6747 */ MCD_OPC_Decode, + 155, + 26, + 206, + 1, // Opcode: VRSHLuv1i64 + /* 6752 */ MCD_OPC_FilterValue, + 1, + 186, + 48, + 0, // Skip to: 19231 + /* 6757 */ MCD_OPC_CheckPredicate, + 26, + 181, + 48, + 0, // Skip to: 19231 + /* 6762 */ MCD_OPC_Decode, + 157, + 26, + 207, + 1, // Opcode: VRSHLuv2i64 + /* 6767 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 6805 + /* 6772 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6775 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6790 + /* 6780 */ MCD_OPC_CheckPredicate, + 26, + 158, + 48, + 0, // Skip to: 19231 + /* 6785 */ MCD_OPC_Decode, + 253, + 29, + 202, + 1, // Opcode: VSUBv1i64 + /* 6790 */ MCD_OPC_FilterValue, + 1, + 148, + 48, + 0, // Skip to: 19231 + /* 6795 */ MCD_OPC_CheckPredicate, + 26, + 143, + 48, + 0, // Skip to: 19231 + /* 6800 */ MCD_OPC_Decode, + 255, + 29, + 203, + 1, // Opcode: VSUBv2i64 + /* 6805 */ MCD_OPC_FilterValue, + 13, + 33, + 0, + 0, // Skip to: 6843 + /* 6810 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6813 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6828 + /* 6818 */ MCD_OPC_CheckPredicate, + 27, + 120, + 48, + 0, // Skip to: 19231 + /* 6823 */ MCD_OPC_Decode, + 243, + 15, + 202, + 1, // Opcode: VABDhd + /* 6828 */ MCD_OPC_FilterValue, + 1, + 110, + 48, + 0, // Skip to: 19231 + /* 6833 */ MCD_OPC_CheckPredicate, + 27, + 105, + 48, + 0, // Skip to: 19231 + /* 6838 */ MCD_OPC_Decode, + 244, + 15, + 203, + 1, // Opcode: VABDhq + /* 6843 */ MCD_OPC_FilterValue, + 14, + 33, + 0, + 0, // Skip to: 6881 + /* 6848 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6851 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6866 + /* 6856 */ MCD_OPC_CheckPredicate, + 27, + 82, + 48, + 0, // Skip to: 19231 + /* 6861 */ MCD_OPC_Decode, + 252, + 16, + 202, + 1, // Opcode: VCGThd + /* 6866 */ MCD_OPC_FilterValue, + 1, + 72, + 48, + 0, // Skip to: 19231 + /* 6871 */ MCD_OPC_CheckPredicate, + 27, + 67, + 48, + 0, // Skip to: 19231 + /* 6876 */ MCD_OPC_Decode, + 253, + 16, + 203, + 1, // Opcode: VCGThq + /* 6881 */ MCD_OPC_FilterValue, + 15, + 57, + 48, + 0, // Skip to: 19231 + /* 6886 */ MCD_OPC_CheckPredicate, + 27, + 52, + 48, + 0, // Skip to: 19231 + /* 6891 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 45, + 48, + 0, // Skip to: 19231 + /* 6898 */ MCD_OPC_Decode, + 142, + 24, + 202, + 1, // Opcode: VPMINh + /* 6903 */ MCD_OPC_FilterValue, + 231, + 3, + 34, + 48, + 0, // Skip to: 19231 + /* 6909 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 6912 */ MCD_OPC_FilterValue, + 0, + 13, + 2, + 0, // Skip to: 7442 + /* 6917 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 6920 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 6988 + /* 6925 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 6928 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6943 + /* 6933 */ MCD_OPC_CheckPredicate, + 26, + 5, + 48, + 0, // Skip to: 19231 + /* 6938 */ MCD_OPC_Decode, + 213, + 25, + 231, + 1, // Opcode: VREV64d8 + /* 6943 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6958 + /* 6948 */ MCD_OPC_CheckPredicate, + 26, + 246, + 47, + 0, // Skip to: 19231 + /* 6953 */ MCD_OPC_Decode, + 216, + 25, + 232, + 1, // Opcode: VREV64q8 + /* 6958 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6973 + /* 6963 */ MCD_OPC_CheckPredicate, + 26, + 231, + 47, + 0, // Skip to: 19231 + /* 6968 */ MCD_OPC_Decode, + 208, + 25, + 231, + 1, // Opcode: VREV32d8 + /* 6973 */ MCD_OPC_FilterValue, + 3, + 221, + 47, + 0, // Skip to: 19231 + /* 6978 */ MCD_OPC_CheckPredicate, + 26, + 216, + 47, + 0, // Skip to: 19231 + /* 6983 */ MCD_OPC_Decode, + 210, + 25, + 232, + 1, // Opcode: VREV32q8 + /* 6988 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 7056 + /* 6993 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 6996 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7011 + /* 7001 */ MCD_OPC_CheckPredicate, + 26, + 193, + 47, + 0, // Skip to: 19231 + /* 7006 */ MCD_OPC_Decode, + 147, + 17, + 231, + 1, // Opcode: VCGTzv8i8 + /* 7011 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7026 + /* 7016 */ MCD_OPC_CheckPredicate, + 26, + 178, + 47, + 0, // Skip to: 19231 + /* 7021 */ MCD_OPC_Decode, + 138, + 17, + 232, + 1, // Opcode: VCGTzv16i8 + /* 7026 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7041 + /* 7031 */ MCD_OPC_CheckPredicate, + 26, + 163, + 47, + 0, // Skip to: 19231 + /* 7036 */ MCD_OPC_Decode, + 249, + 16, + 231, + 1, // Opcode: VCGEzv8i8 + /* 7041 */ MCD_OPC_FilterValue, + 3, + 153, + 47, + 0, // Skip to: 19231 + /* 7046 */ MCD_OPC_CheckPredicate, + 26, + 148, + 47, + 0, // Skip to: 19231 + /* 7051 */ MCD_OPC_Decode, + 240, + 16, + 232, + 1, // Opcode: VCGEzv16i8 + /* 7056 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 7124 + /* 7061 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7064 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7079 + /* 7069 */ MCD_OPC_CheckPredicate, + 26, + 125, + 47, + 0, // Skip to: 19231 + /* 7074 */ MCD_OPC_Decode, + 134, + 30, + 233, + 1, // Opcode: VSWPd + /* 7079 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7094 + /* 7084 */ MCD_OPC_CheckPredicate, + 26, + 110, + 47, + 0, // Skip to: 19231 + /* 7089 */ MCD_OPC_Decode, + 135, + 30, + 234, + 1, // Opcode: VSWPq + /* 7094 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7109 + /* 7099 */ MCD_OPC_CheckPredicate, + 26, + 95, + 47, + 0, // Skip to: 19231 + /* 7104 */ MCD_OPC_Decode, + 174, + 30, + 233, + 1, // Opcode: VTRNd8 + /* 7109 */ MCD_OPC_FilterValue, + 3, + 85, + 47, + 0, // Skip to: 19231 + /* 7114 */ MCD_OPC_CheckPredicate, + 26, + 80, + 47, + 0, // Skip to: 19231 + /* 7119 */ MCD_OPC_Decode, + 177, + 30, + 234, + 1, // Opcode: VTRNq8 + /* 7124 */ MCD_OPC_FilterValue, + 4, + 63, + 0, + 0, // Skip to: 7192 + /* 7129 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7132 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7147 + /* 7137 */ MCD_OPC_CheckPredicate, + 26, + 57, + 47, + 0, // Skip to: 19231 + /* 7142 */ MCD_OPC_Decode, + 211, + 25, + 231, + 1, // Opcode: VREV64d16 + /* 7147 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7162 + /* 7152 */ MCD_OPC_CheckPredicate, + 26, + 42, + 47, + 0, // Skip to: 19231 + /* 7157 */ MCD_OPC_Decode, + 214, + 25, + 232, + 1, // Opcode: VREV64q16 + /* 7162 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7177 + /* 7167 */ MCD_OPC_CheckPredicate, + 26, + 27, + 47, + 0, // Skip to: 19231 + /* 7172 */ MCD_OPC_Decode, + 207, + 25, + 231, + 1, // Opcode: VREV32d16 + /* 7177 */ MCD_OPC_FilterValue, + 3, + 17, + 47, + 0, // Skip to: 19231 + /* 7182 */ MCD_OPC_CheckPredicate, + 26, + 12, + 47, + 0, // Skip to: 19231 + /* 7187 */ MCD_OPC_Decode, + 209, + 25, + 232, + 1, // Opcode: VREV32q16 + /* 7192 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 7260 + /* 7197 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7200 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7215 + /* 7205 */ MCD_OPC_CheckPredicate, + 26, + 245, + 46, + 0, // Skip to: 19231 + /* 7210 */ MCD_OPC_Decode, + 143, + 17, + 231, + 1, // Opcode: VCGTzv4i16 + /* 7215 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7230 + /* 7220 */ MCD_OPC_CheckPredicate, + 26, + 230, + 46, + 0, // Skip to: 19231 + /* 7225 */ MCD_OPC_Decode, + 146, + 17, + 232, + 1, // Opcode: VCGTzv8i16 + /* 7230 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7245 + /* 7235 */ MCD_OPC_CheckPredicate, + 26, + 215, + 46, + 0, // Skip to: 19231 + /* 7240 */ MCD_OPC_Decode, + 245, + 16, + 231, + 1, // Opcode: VCGEzv4i16 + /* 7245 */ MCD_OPC_FilterValue, + 3, + 205, + 46, + 0, // Skip to: 19231 + /* 7250 */ MCD_OPC_CheckPredicate, + 26, + 200, + 46, + 0, // Skip to: 19231 + /* 7255 */ MCD_OPC_Decode, + 248, + 16, + 232, + 1, // Opcode: VCGEzv8i16 + /* 7260 */ MCD_OPC_FilterValue, + 6, + 33, + 0, + 0, // Skip to: 7298 + /* 7265 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7268 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7283 + /* 7273 */ MCD_OPC_CheckPredicate, + 26, + 177, + 46, + 0, // Skip to: 19231 + /* 7278 */ MCD_OPC_Decode, + 172, + 30, + 233, + 1, // Opcode: VTRNd16 + /* 7283 */ MCD_OPC_FilterValue, + 3, + 167, + 46, + 0, // Skip to: 19231 + /* 7288 */ MCD_OPC_CheckPredicate, + 26, + 162, + 46, + 0, // Skip to: 19231 + /* 7293 */ MCD_OPC_Decode, + 175, + 30, + 234, + 1, // Opcode: VTRNq16 + /* 7298 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 7336 + /* 7303 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7306 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7321 + /* 7311 */ MCD_OPC_CheckPredicate, + 26, + 139, + 46, + 0, // Skip to: 19231 + /* 7316 */ MCD_OPC_Decode, + 212, + 25, + 231, + 1, // Opcode: VREV64d32 + /* 7321 */ MCD_OPC_FilterValue, + 1, + 129, + 46, + 0, // Skip to: 19231 + /* 7326 */ MCD_OPC_CheckPredicate, + 26, + 124, + 46, + 0, // Skip to: 19231 + /* 7331 */ MCD_OPC_Decode, + 215, + 25, + 232, + 1, // Opcode: VREV64q32 + /* 7336 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 7404 + /* 7341 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7344 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7359 + /* 7349 */ MCD_OPC_CheckPredicate, + 26, + 101, + 46, + 0, // Skip to: 19231 + /* 7354 */ MCD_OPC_Decode, + 140, + 17, + 231, + 1, // Opcode: VCGTzv2i32 + /* 7359 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7374 + /* 7364 */ MCD_OPC_CheckPredicate, + 26, + 86, + 46, + 0, // Skip to: 19231 + /* 7369 */ MCD_OPC_Decode, + 144, + 17, + 232, + 1, // Opcode: VCGTzv4i32 + /* 7374 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7389 + /* 7379 */ MCD_OPC_CheckPredicate, + 26, + 71, + 46, + 0, // Skip to: 19231 + /* 7384 */ MCD_OPC_Decode, + 242, + 16, + 231, + 1, // Opcode: VCGEzv2i32 + /* 7389 */ MCD_OPC_FilterValue, + 3, + 61, + 46, + 0, // Skip to: 19231 + /* 7394 */ MCD_OPC_CheckPredicate, + 26, + 56, + 46, + 0, // Skip to: 19231 + /* 7399 */ MCD_OPC_Decode, + 246, + 16, + 232, + 1, // Opcode: VCGEzv4i32 + /* 7404 */ MCD_OPC_FilterValue, + 10, + 46, + 46, + 0, // Skip to: 19231 + /* 7409 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7412 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7427 + /* 7417 */ MCD_OPC_CheckPredicate, + 26, + 33, + 46, + 0, // Skip to: 19231 + /* 7422 */ MCD_OPC_Decode, + 173, + 30, + 233, + 1, // Opcode: VTRNd32 + /* 7427 */ MCD_OPC_FilterValue, + 3, + 23, + 46, + 0, // Skip to: 19231 + /* 7432 */ MCD_OPC_CheckPredicate, + 26, + 18, + 46, + 0, // Skip to: 19231 + /* 7437 */ MCD_OPC_Decode, + 176, + 30, + 234, + 1, // Opcode: VTRNq32 + /* 7442 */ MCD_OPC_FilterValue, + 1, + 163, + 1, + 0, // Skip to: 7866 + /* 7447 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 7450 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 7488 + /* 7455 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7458 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7473 + /* 7463 */ MCD_OPC_CheckPredicate, + 26, + 243, + 45, + 0, // Skip to: 19231 + /* 7468 */ MCD_OPC_Decode, + 205, + 25, + 231, + 1, // Opcode: VREV16d8 + /* 7473 */ MCD_OPC_FilterValue, + 1, + 233, + 45, + 0, // Skip to: 19231 + /* 7478 */ MCD_OPC_CheckPredicate, + 26, + 228, + 45, + 0, // Skip to: 19231 + /* 7483 */ MCD_OPC_Decode, + 206, + 25, + 232, + 1, // Opcode: VREV16q8 + /* 7488 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 7556 + /* 7493 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7496 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7511 + /* 7501 */ MCD_OPC_CheckPredicate, + 26, + 205, + 45, + 0, // Skip to: 19231 + /* 7506 */ MCD_OPC_Decode, + 223, + 16, + 231, + 1, // Opcode: VCEQzv8i8 + /* 7511 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7526 + /* 7516 */ MCD_OPC_CheckPredicate, + 26, + 190, + 45, + 0, // Skip to: 19231 + /* 7521 */ MCD_OPC_Decode, + 214, + 16, + 232, + 1, // Opcode: VCEQzv16i8 + /* 7526 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7541 + /* 7531 */ MCD_OPC_CheckPredicate, + 26, + 175, + 45, + 0, // Skip to: 19231 + /* 7536 */ MCD_OPC_Decode, + 157, + 17, + 231, + 1, // Opcode: VCLEzv8i8 + /* 7541 */ MCD_OPC_FilterValue, + 3, + 165, + 45, + 0, // Skip to: 19231 + /* 7546 */ MCD_OPC_CheckPredicate, + 26, + 160, + 45, + 0, // Skip to: 19231 + /* 7551 */ MCD_OPC_Decode, + 148, + 17, + 232, + 1, // Opcode: VCLEzv16i8 + /* 7556 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 7624 + /* 7561 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7564 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7579 + /* 7569 */ MCD_OPC_CheckPredicate, + 26, + 137, + 45, + 0, // Skip to: 19231 + /* 7574 */ MCD_OPC_Decode, + 204, + 30, + 233, + 1, // Opcode: VUZPd8 + /* 7579 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7594 + /* 7584 */ MCD_OPC_CheckPredicate, + 26, + 122, + 45, + 0, // Skip to: 19231 + /* 7589 */ MCD_OPC_Decode, + 207, + 30, + 234, + 1, // Opcode: VUZPq8 + /* 7594 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7609 + /* 7599 */ MCD_OPC_CheckPredicate, + 26, + 107, + 45, + 0, // Skip to: 19231 + /* 7604 */ MCD_OPC_Decode, + 209, + 30, + 233, + 1, // Opcode: VZIPd8 + /* 7609 */ MCD_OPC_FilterValue, + 3, + 97, + 45, + 0, // Skip to: 19231 + /* 7614 */ MCD_OPC_CheckPredicate, + 26, + 92, + 45, + 0, // Skip to: 19231 + /* 7619 */ MCD_OPC_Decode, + 212, + 30, + 234, + 1, // Opcode: VZIPq8 + /* 7624 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 7692 + /* 7629 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7632 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7647 + /* 7637 */ MCD_OPC_CheckPredicate, + 26, + 69, + 45, + 0, // Skip to: 19231 + /* 7642 */ MCD_OPC_Decode, + 219, + 16, + 231, + 1, // Opcode: VCEQzv4i16 + /* 7647 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7662 + /* 7652 */ MCD_OPC_CheckPredicate, + 26, + 54, + 45, + 0, // Skip to: 19231 + /* 7657 */ MCD_OPC_Decode, + 222, + 16, + 232, + 1, // Opcode: VCEQzv8i16 + /* 7662 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7677 + /* 7667 */ MCD_OPC_CheckPredicate, + 26, + 39, + 45, + 0, // Skip to: 19231 + /* 7672 */ MCD_OPC_Decode, + 153, + 17, + 231, + 1, // Opcode: VCLEzv4i16 + /* 7677 */ MCD_OPC_FilterValue, + 3, + 29, + 45, + 0, // Skip to: 19231 + /* 7682 */ MCD_OPC_CheckPredicate, + 26, + 24, + 45, + 0, // Skip to: 19231 + /* 7687 */ MCD_OPC_Decode, + 156, + 17, + 232, + 1, // Opcode: VCLEzv8i16 + /* 7692 */ MCD_OPC_FilterValue, + 6, + 63, + 0, + 0, // Skip to: 7760 + /* 7697 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7700 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7715 + /* 7705 */ MCD_OPC_CheckPredicate, + 26, + 1, + 45, + 0, // Skip to: 19231 + /* 7710 */ MCD_OPC_Decode, + 203, + 30, + 233, + 1, // Opcode: VUZPd16 + /* 7715 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7730 + /* 7720 */ MCD_OPC_CheckPredicate, + 26, + 242, + 44, + 0, // Skip to: 19231 + /* 7725 */ MCD_OPC_Decode, + 205, + 30, + 234, + 1, // Opcode: VUZPq16 + /* 7730 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7745 + /* 7735 */ MCD_OPC_CheckPredicate, + 26, + 227, + 44, + 0, // Skip to: 19231 + /* 7740 */ MCD_OPC_Decode, + 208, + 30, + 233, + 1, // Opcode: VZIPd16 + /* 7745 */ MCD_OPC_FilterValue, + 3, + 217, + 44, + 0, // Skip to: 19231 + /* 7750 */ MCD_OPC_CheckPredicate, + 26, + 212, + 44, + 0, // Skip to: 19231 + /* 7755 */ MCD_OPC_Decode, + 210, + 30, + 234, + 1, // Opcode: VZIPq16 + /* 7760 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 7828 + /* 7765 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7768 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7783 + /* 7773 */ MCD_OPC_CheckPredicate, + 26, + 189, + 44, + 0, // Skip to: 19231 + /* 7778 */ MCD_OPC_Decode, + 216, + 16, + 231, + 1, // Opcode: VCEQzv2i32 + /* 7783 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7798 + /* 7788 */ MCD_OPC_CheckPredicate, + 26, + 174, + 44, + 0, // Skip to: 19231 + /* 7793 */ MCD_OPC_Decode, + 220, + 16, + 232, + 1, // Opcode: VCEQzv4i32 + /* 7798 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7813 + /* 7803 */ MCD_OPC_CheckPredicate, + 26, + 159, + 44, + 0, // Skip to: 19231 + /* 7808 */ MCD_OPC_Decode, + 150, + 17, + 231, + 1, // Opcode: VCLEzv2i32 + /* 7813 */ MCD_OPC_FilterValue, + 3, + 149, + 44, + 0, // Skip to: 19231 + /* 7818 */ MCD_OPC_CheckPredicate, + 26, + 144, + 44, + 0, // Skip to: 19231 + /* 7823 */ MCD_OPC_Decode, + 154, + 17, + 232, + 1, // Opcode: VCLEzv4i32 + /* 7828 */ MCD_OPC_FilterValue, + 10, + 134, + 44, + 0, // Skip to: 19231 + /* 7833 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7836 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7851 + /* 7841 */ MCD_OPC_CheckPredicate, + 26, + 121, + 44, + 0, // Skip to: 19231 + /* 7846 */ MCD_OPC_Decode, + 206, + 30, + 234, + 1, // Opcode: VUZPq32 + /* 7851 */ MCD_OPC_FilterValue, + 3, + 111, + 44, + 0, // Skip to: 19231 + /* 7856 */ MCD_OPC_CheckPredicate, + 26, + 106, + 44, + 0, // Skip to: 19231 + /* 7861 */ MCD_OPC_Decode, + 211, + 30, + 234, + 1, // Opcode: VZIPq32 + /* 7866 */ MCD_OPC_FilterValue, + 2, + 13, + 2, + 0, // Skip to: 8396 + /* 7871 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 7874 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 7942 + /* 7879 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7882 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7897 + /* 7887 */ MCD_OPC_CheckPredicate, + 26, + 75, + 44, + 0, // Skip to: 19231 + /* 7892 */ MCD_OPC_Decode, + 249, + 23, + 231, + 1, // Opcode: VPADDLsv8i8 + /* 7897 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7912 + /* 7902 */ MCD_OPC_CheckPredicate, + 26, + 60, + 44, + 0, // Skip to: 19231 + /* 7907 */ MCD_OPC_Decode, + 244, + 23, + 232, + 1, // Opcode: VPADDLsv16i8 + /* 7912 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7927 + /* 7917 */ MCD_OPC_CheckPredicate, + 26, + 45, + 44, + 0, // Skip to: 19231 + /* 7922 */ MCD_OPC_Decode, + 255, + 23, + 231, + 1, // Opcode: VPADDLuv8i8 + /* 7927 */ MCD_OPC_FilterValue, + 3, + 35, + 44, + 0, // Skip to: 19231 + /* 7932 */ MCD_OPC_CheckPredicate, + 26, + 30, + 44, + 0, // Skip to: 19231 + /* 7937 */ MCD_OPC_Decode, + 250, + 23, + 232, + 1, // Opcode: VPADDLuv16i8 + /* 7942 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 7980 + /* 7947 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7950 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7965 + /* 7955 */ MCD_OPC_CheckPredicate, + 26, + 7, + 44, + 0, // Skip to: 19231 + /* 7960 */ MCD_OPC_Decode, + 173, + 17, + 231, + 1, // Opcode: VCLTzv8i8 + /* 7965 */ MCD_OPC_FilterValue, + 1, + 253, + 43, + 0, // Skip to: 19231 + /* 7970 */ MCD_OPC_CheckPredicate, + 26, + 248, + 43, + 0, // Skip to: 19231 + /* 7975 */ MCD_OPC_Decode, + 164, + 17, + 232, + 1, // Opcode: VCLTzv16i8 + /* 7980 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 8048 + /* 7985 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7988 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8003 + /* 7993 */ MCD_OPC_CheckPredicate, + 26, + 225, + 43, + 0, // Skip to: 19231 + /* 7998 */ MCD_OPC_Decode, + 248, + 22, + 235, + 1, // Opcode: VMOVNv8i8 + /* 8003 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8018 + /* 8008 */ MCD_OPC_CheckPredicate, + 26, + 210, + 43, + 0, // Skip to: 19231 + /* 8013 */ MCD_OPC_Decode, + 193, + 24, + 235, + 1, // Opcode: VQMOVNsuv8i8 + /* 8018 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8033 + /* 8023 */ MCD_OPC_CheckPredicate, + 26, + 195, + 43, + 0, // Skip to: 19231 + /* 8028 */ MCD_OPC_Decode, + 196, + 24, + 235, + 1, // Opcode: VQMOVNsv8i8 + /* 8033 */ MCD_OPC_FilterValue, + 3, + 185, + 43, + 0, // Skip to: 19231 + /* 8038 */ MCD_OPC_CheckPredicate, + 26, + 180, + 43, + 0, // Skip to: 19231 + /* 8043 */ MCD_OPC_Decode, + 199, + 24, + 235, + 1, // Opcode: VQMOVNuv8i8 + /* 8048 */ MCD_OPC_FilterValue, + 4, + 63, + 0, + 0, // Skip to: 8116 + /* 8053 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8056 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8071 + /* 8061 */ MCD_OPC_CheckPredicate, + 26, + 157, + 43, + 0, // Skip to: 19231 + /* 8066 */ MCD_OPC_Decode, + 246, + 23, + 231, + 1, // Opcode: VPADDLsv4i16 + /* 8071 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8086 + /* 8076 */ MCD_OPC_CheckPredicate, + 26, + 142, + 43, + 0, // Skip to: 19231 + /* 8081 */ MCD_OPC_Decode, + 248, + 23, + 232, + 1, // Opcode: VPADDLsv8i16 + /* 8086 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8101 + /* 8091 */ MCD_OPC_CheckPredicate, + 26, + 127, + 43, + 0, // Skip to: 19231 + /* 8096 */ MCD_OPC_Decode, + 252, + 23, + 231, + 1, // Opcode: VPADDLuv4i16 + /* 8101 */ MCD_OPC_FilterValue, + 3, + 117, + 43, + 0, // Skip to: 19231 + /* 8106 */ MCD_OPC_CheckPredicate, + 26, + 112, + 43, + 0, // Skip to: 19231 + /* 8111 */ MCD_OPC_Decode, + 254, + 23, + 232, + 1, // Opcode: VPADDLuv8i16 + /* 8116 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 8154 + /* 8121 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8124 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8139 + /* 8129 */ MCD_OPC_CheckPredicate, + 26, + 89, + 43, + 0, // Skip to: 19231 + /* 8134 */ MCD_OPC_Decode, + 169, + 17, + 231, + 1, // Opcode: VCLTzv4i16 + /* 8139 */ MCD_OPC_FilterValue, + 1, + 79, + 43, + 0, // Skip to: 19231 + /* 8144 */ MCD_OPC_CheckPredicate, + 26, + 74, + 43, + 0, // Skip to: 19231 + /* 8149 */ MCD_OPC_Decode, + 172, + 17, + 232, + 1, // Opcode: VCLTzv8i16 + /* 8154 */ MCD_OPC_FilterValue, + 6, + 63, + 0, + 0, // Skip to: 8222 + /* 8159 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8162 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8177 + /* 8167 */ MCD_OPC_CheckPredicate, + 26, + 51, + 43, + 0, // Skip to: 19231 + /* 8172 */ MCD_OPC_Decode, + 247, + 22, + 235, + 1, // Opcode: VMOVNv4i16 + /* 8177 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8192 + /* 8182 */ MCD_OPC_CheckPredicate, + 26, + 36, + 43, + 0, // Skip to: 19231 + /* 8187 */ MCD_OPC_Decode, + 192, + 24, + 235, + 1, // Opcode: VQMOVNsuv4i16 + /* 8192 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8207 + /* 8197 */ MCD_OPC_CheckPredicate, + 26, + 21, + 43, + 0, // Skip to: 19231 + /* 8202 */ MCD_OPC_Decode, + 195, + 24, + 235, + 1, // Opcode: VQMOVNsv4i16 + /* 8207 */ MCD_OPC_FilterValue, + 3, + 11, + 43, + 0, // Skip to: 19231 + /* 8212 */ MCD_OPC_CheckPredicate, + 26, + 6, + 43, + 0, // Skip to: 19231 + /* 8217 */ MCD_OPC_Decode, + 198, + 24, + 235, + 1, // Opcode: VQMOVNuv4i16 + /* 8222 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 8290 + /* 8227 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8230 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8245 + /* 8235 */ MCD_OPC_CheckPredicate, + 26, + 239, + 42, + 0, // Skip to: 19231 + /* 8240 */ MCD_OPC_Decode, + 245, + 23, + 231, + 1, // Opcode: VPADDLsv2i32 + /* 8245 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8260 + /* 8250 */ MCD_OPC_CheckPredicate, + 26, + 224, + 42, + 0, // Skip to: 19231 + /* 8255 */ MCD_OPC_Decode, + 247, + 23, + 232, + 1, // Opcode: VPADDLsv4i32 + /* 8260 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8275 + /* 8265 */ MCD_OPC_CheckPredicate, + 26, + 209, + 42, + 0, // Skip to: 19231 + /* 8270 */ MCD_OPC_Decode, + 251, + 23, + 231, + 1, // Opcode: VPADDLuv2i32 + /* 8275 */ MCD_OPC_FilterValue, + 3, + 199, + 42, + 0, // Skip to: 19231 + /* 8280 */ MCD_OPC_CheckPredicate, + 26, + 194, + 42, + 0, // Skip to: 19231 + /* 8285 */ MCD_OPC_Decode, + 253, + 23, + 232, + 1, // Opcode: VPADDLuv4i32 + /* 8290 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 8328 + /* 8295 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8298 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8313 + /* 8303 */ MCD_OPC_CheckPredicate, + 26, + 171, + 42, + 0, // Skip to: 19231 + /* 8308 */ MCD_OPC_Decode, + 166, + 17, + 231, + 1, // Opcode: VCLTzv2i32 + /* 8313 */ MCD_OPC_FilterValue, + 1, + 161, + 42, + 0, // Skip to: 19231 + /* 8318 */ MCD_OPC_CheckPredicate, + 26, + 156, + 42, + 0, // Skip to: 19231 + /* 8323 */ MCD_OPC_Decode, + 170, + 17, + 232, + 1, // Opcode: VCLTzv4i32 + /* 8328 */ MCD_OPC_FilterValue, + 10, + 146, + 42, + 0, // Skip to: 19231 + /* 8333 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8336 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8351 + /* 8341 */ MCD_OPC_CheckPredicate, + 26, + 133, + 42, + 0, // Skip to: 19231 + /* 8346 */ MCD_OPC_Decode, + 246, + 22, + 235, + 1, // Opcode: VMOVNv2i32 + /* 8351 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8366 + /* 8356 */ MCD_OPC_CheckPredicate, + 26, + 118, + 42, + 0, // Skip to: 19231 + /* 8361 */ MCD_OPC_Decode, + 191, + 24, + 235, + 1, // Opcode: VQMOVNsuv2i32 + /* 8366 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8381 + /* 8371 */ MCD_OPC_CheckPredicate, + 26, + 103, + 42, + 0, // Skip to: 19231 + /* 8376 */ MCD_OPC_Decode, + 194, + 24, + 235, + 1, // Opcode: VQMOVNsv2i32 + /* 8381 */ MCD_OPC_FilterValue, + 3, + 93, + 42, + 0, // Skip to: 19231 + /* 8386 */ MCD_OPC_CheckPredicate, + 26, + 88, + 42, + 0, // Skip to: 19231 + /* 8391 */ MCD_OPC_Decode, + 197, + 24, + 235, + 1, // Opcode: VQMOVNuv2i32 + /* 8396 */ MCD_OPC_FilterValue, + 3, + 17, + 1, + 0, // Skip to: 8674 + /* 8401 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 8404 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 8472 + /* 8409 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8412 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8427 + /* 8417 */ MCD_OPC_CheckPredicate, + 26, + 57, + 42, + 0, // Skip to: 19231 + /* 8422 */ MCD_OPC_Decode, + 141, + 16, + 231, + 1, // Opcode: VABSv8i8 + /* 8427 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8442 + /* 8432 */ MCD_OPC_CheckPredicate, + 26, + 42, + 42, + 0, // Skip to: 19231 + /* 8437 */ MCD_OPC_Decode, + 136, + 16, + 232, + 1, // Opcode: VABSv16i8 + /* 8442 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8457 + /* 8447 */ MCD_OPC_CheckPredicate, + 26, + 27, + 42, + 0, // Skip to: 19231 + /* 8452 */ MCD_OPC_Decode, + 213, + 23, + 231, + 1, // Opcode: VNEGs8d + /* 8457 */ MCD_OPC_FilterValue, + 3, + 17, + 42, + 0, // Skip to: 19231 + /* 8462 */ MCD_OPC_CheckPredicate, + 26, + 12, + 42, + 0, // Skip to: 19231 + /* 8467 */ MCD_OPC_Decode, + 214, + 23, + 232, + 1, // Opcode: VNEGs8q + /* 8472 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 8494 + /* 8477 */ MCD_OPC_CheckPredicate, + 26, + 253, + 41, + 0, // Skip to: 19231 + /* 8482 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 246, + 41, + 0, // Skip to: 19231 + /* 8489 */ MCD_OPC_Decode, + 233, + 26, + 236, + 1, // Opcode: VSHLLi8 + /* 8494 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 8562 + /* 8499 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8502 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8517 + /* 8507 */ MCD_OPC_CheckPredicate, + 26, + 223, + 41, + 0, // Skip to: 19231 + /* 8512 */ MCD_OPC_Decode, + 138, + 16, + 231, + 1, // Opcode: VABSv4i16 + /* 8517 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8532 + /* 8522 */ MCD_OPC_CheckPredicate, + 26, + 208, + 41, + 0, // Skip to: 19231 + /* 8527 */ MCD_OPC_Decode, + 140, + 16, + 232, + 1, // Opcode: VABSv8i16 + /* 8532 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8547 + /* 8537 */ MCD_OPC_CheckPredicate, + 26, + 193, + 41, + 0, // Skip to: 19231 + /* 8542 */ MCD_OPC_Decode, + 209, + 23, + 231, + 1, // Opcode: VNEGs16d + /* 8547 */ MCD_OPC_FilterValue, + 3, + 183, + 41, + 0, // Skip to: 19231 + /* 8552 */ MCD_OPC_CheckPredicate, + 26, + 178, + 41, + 0, // Skip to: 19231 + /* 8557 */ MCD_OPC_Decode, + 210, + 23, + 232, + 1, // Opcode: VNEGs16q + /* 8562 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 8584 + /* 8567 */ MCD_OPC_CheckPredicate, + 26, + 163, + 41, + 0, // Skip to: 19231 + /* 8572 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 156, + 41, + 0, // Skip to: 19231 + /* 8579 */ MCD_OPC_Decode, + 231, + 26, + 236, + 1, // Opcode: VSHLLi16 + /* 8584 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 8652 + /* 8589 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8592 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8607 + /* 8597 */ MCD_OPC_CheckPredicate, + 26, + 133, + 41, + 0, // Skip to: 19231 + /* 8602 */ MCD_OPC_Decode, + 137, + 16, + 231, + 1, // Opcode: VABSv2i32 + /* 8607 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8622 + /* 8612 */ MCD_OPC_CheckPredicate, + 26, + 118, + 41, + 0, // Skip to: 19231 + /* 8617 */ MCD_OPC_Decode, + 139, + 16, + 232, + 1, // Opcode: VABSv4i32 + /* 8622 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8637 + /* 8627 */ MCD_OPC_CheckPredicate, + 26, + 103, + 41, + 0, // Skip to: 19231 + /* 8632 */ MCD_OPC_Decode, + 211, + 23, + 231, + 1, // Opcode: VNEGs32d + /* 8637 */ MCD_OPC_FilterValue, + 3, + 93, + 41, + 0, // Skip to: 19231 + /* 8642 */ MCD_OPC_CheckPredicate, + 26, + 88, + 41, + 0, // Skip to: 19231 + /* 8647 */ MCD_OPC_Decode, + 212, + 23, + 232, + 1, // Opcode: VNEGs32q + /* 8652 */ MCD_OPC_FilterValue, + 10, + 78, + 41, + 0, // Skip to: 19231 + /* 8657 */ MCD_OPC_CheckPredicate, + 26, + 73, + 41, + 0, // Skip to: 19231 + /* 8662 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 66, + 41, + 0, // Skip to: 19231 + /* 8669 */ MCD_OPC_Decode, + 232, + 26, + 236, + 1, // Opcode: VSHLLi32 + /* 8674 */ MCD_OPC_FilterValue, + 4, + 155, + 1, + 0, // Skip to: 9090 + /* 8679 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 8682 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 8750 + /* 8687 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8690 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8705 + /* 8695 */ MCD_OPC_CheckPredicate, + 26, + 35, + 41, + 0, // Skip to: 19231 + /* 8700 */ MCD_OPC_Decode, + 163, + 17, + 231, + 1, // Opcode: VCLSv8i8 + /* 8705 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8720 + /* 8710 */ MCD_OPC_CheckPredicate, + 26, + 20, + 41, + 0, // Skip to: 19231 + /* 8715 */ MCD_OPC_Decode, + 158, + 17, + 232, + 1, // Opcode: VCLSv16i8 + /* 8720 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8735 + /* 8725 */ MCD_OPC_CheckPredicate, + 26, + 5, + 41, + 0, // Skip to: 19231 + /* 8730 */ MCD_OPC_Decode, + 179, + 17, + 231, + 1, // Opcode: VCLZv8i8 + /* 8735 */ MCD_OPC_FilterValue, + 3, + 251, + 40, + 0, // Skip to: 19231 + /* 8740 */ MCD_OPC_CheckPredicate, + 26, + 246, + 40, + 0, // Skip to: 19231 + /* 8745 */ MCD_OPC_Decode, + 174, + 17, + 232, + 1, // Opcode: VCLZv16i8 + /* 8750 */ MCD_OPC_FilterValue, + 4, + 63, + 0, + 0, // Skip to: 8818 + /* 8755 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8758 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8773 + /* 8763 */ MCD_OPC_CheckPredicate, + 26, + 223, + 40, + 0, // Skip to: 19231 + /* 8768 */ MCD_OPC_Decode, + 160, + 17, + 231, + 1, // Opcode: VCLSv4i16 + /* 8773 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8788 + /* 8778 */ MCD_OPC_CheckPredicate, + 26, + 208, + 40, + 0, // Skip to: 19231 + /* 8783 */ MCD_OPC_Decode, + 162, + 17, + 232, + 1, // Opcode: VCLSv8i16 + /* 8788 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8803 + /* 8793 */ MCD_OPC_CheckPredicate, + 26, + 193, + 40, + 0, // Skip to: 19231 + /* 8798 */ MCD_OPC_Decode, + 176, + 17, + 231, + 1, // Opcode: VCLZv4i16 + /* 8803 */ MCD_OPC_FilterValue, + 3, + 183, + 40, + 0, // Skip to: 19231 + /* 8808 */ MCD_OPC_CheckPredicate, + 26, + 178, + 40, + 0, // Skip to: 19231 + /* 8813 */ MCD_OPC_Decode, + 178, + 17, + 232, + 1, // Opcode: VCLZv8i16 + /* 8818 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 8886 + /* 8823 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8826 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8841 + /* 8831 */ MCD_OPC_CheckPredicate, + 27, + 155, + 40, + 0, // Skip to: 19231 + /* 8836 */ MCD_OPC_Decode, + 141, + 17, + 231, + 1, // Opcode: VCGTzv4f16 + /* 8841 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8856 + /* 8846 */ MCD_OPC_CheckPredicate, + 27, + 140, + 40, + 0, // Skip to: 19231 + /* 8851 */ MCD_OPC_Decode, + 145, + 17, + 232, + 1, // Opcode: VCGTzv8f16 + /* 8856 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8871 + /* 8861 */ MCD_OPC_CheckPredicate, + 27, + 125, + 40, + 0, // Skip to: 19231 + /* 8866 */ MCD_OPC_Decode, + 243, + 16, + 231, + 1, // Opcode: VCGEzv4f16 + /* 8871 */ MCD_OPC_FilterValue, + 3, + 115, + 40, + 0, // Skip to: 19231 + /* 8876 */ MCD_OPC_CheckPredicate, + 27, + 110, + 40, + 0, // Skip to: 19231 + /* 8881 */ MCD_OPC_Decode, + 247, + 16, + 232, + 1, // Opcode: VCGEzv8f16 + /* 8886 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 8954 + /* 8891 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8894 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8909 + /* 8899 */ MCD_OPC_CheckPredicate, + 26, + 87, + 40, + 0, // Skip to: 19231 + /* 8904 */ MCD_OPC_Decode, + 159, + 17, + 231, + 1, // Opcode: VCLSv2i32 + /* 8909 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8924 + /* 8914 */ MCD_OPC_CheckPredicate, + 26, + 72, + 40, + 0, // Skip to: 19231 + /* 8919 */ MCD_OPC_Decode, + 161, + 17, + 232, + 1, // Opcode: VCLSv4i32 + /* 8924 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8939 + /* 8929 */ MCD_OPC_CheckPredicate, + 26, + 57, + 40, + 0, // Skip to: 19231 + /* 8934 */ MCD_OPC_Decode, + 175, + 17, + 231, + 1, // Opcode: VCLZv2i32 + /* 8939 */ MCD_OPC_FilterValue, + 3, + 47, + 40, + 0, // Skip to: 19231 + /* 8944 */ MCD_OPC_CheckPredicate, + 26, + 42, + 40, + 0, // Skip to: 19231 + /* 8949 */ MCD_OPC_Decode, + 177, + 17, + 232, + 1, // Opcode: VCLZv4i32 + /* 8954 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 9022 + /* 8959 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8962 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8977 + /* 8967 */ MCD_OPC_CheckPredicate, + 26, + 19, + 40, + 0, // Skip to: 19231 + /* 8972 */ MCD_OPC_Decode, + 139, + 17, + 231, + 1, // Opcode: VCGTzv2f32 + /* 8977 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8992 + /* 8982 */ MCD_OPC_CheckPredicate, + 26, + 4, + 40, + 0, // Skip to: 19231 + /* 8987 */ MCD_OPC_Decode, + 142, + 17, + 232, + 1, // Opcode: VCGTzv4f32 + /* 8992 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9007 + /* 8997 */ MCD_OPC_CheckPredicate, + 26, + 245, + 39, + 0, // Skip to: 19231 + /* 9002 */ MCD_OPC_Decode, + 241, + 16, + 231, + 1, // Opcode: VCGEzv2f32 + /* 9007 */ MCD_OPC_FilterValue, + 3, + 235, + 39, + 0, // Skip to: 19231 + /* 9012 */ MCD_OPC_CheckPredicate, + 26, + 230, + 39, + 0, // Skip to: 19231 + /* 9017 */ MCD_OPC_Decode, + 244, + 16, + 232, + 1, // Opcode: VCGEzv4f32 + /* 9022 */ MCD_OPC_FilterValue, + 11, + 220, + 39, + 0, // Skip to: 19231 + /* 9027 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9030 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9045 + /* 9035 */ MCD_OPC_CheckPredicate, + 26, + 207, + 39, + 0, // Skip to: 19231 + /* 9040 */ MCD_OPC_Decode, + 195, + 25, + 231, + 1, // Opcode: VRECPEd + /* 9045 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9060 + /* 9050 */ MCD_OPC_CheckPredicate, + 26, + 192, + 39, + 0, // Skip to: 19231 + /* 9055 */ MCD_OPC_Decode, + 200, + 25, + 232, + 1, // Opcode: VRECPEq + /* 9060 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9075 + /* 9065 */ MCD_OPC_CheckPredicate, + 26, + 177, + 39, + 0, // Skip to: 19231 + /* 9070 */ MCD_OPC_Decode, + 181, + 26, + 231, + 1, // Opcode: VRSQRTEd + /* 9075 */ MCD_OPC_FilterValue, + 3, + 167, + 39, + 0, // Skip to: 19231 + /* 9080 */ MCD_OPC_CheckPredicate, + 26, + 162, + 39, + 0, // Skip to: 19231 + /* 9085 */ MCD_OPC_Decode, + 186, + 26, + 232, + 1, // Opcode: VRSQRTEq + /* 9090 */ MCD_OPC_FilterValue, + 5, + 87, + 1, + 0, // Skip to: 9438 + /* 9095 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9098 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 9166 + /* 9103 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9106 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9121 + /* 9111 */ MCD_OPC_CheckPredicate, + 26, + 131, + 39, + 0, // Skip to: 19231 + /* 9116 */ MCD_OPC_Decode, + 200, + 17, + 231, + 1, // Opcode: VCNTd + /* 9121 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9136 + /* 9126 */ MCD_OPC_CheckPredicate, + 26, + 116, + 39, + 0, // Skip to: 19231 + /* 9131 */ MCD_OPC_Decode, + 201, + 17, + 232, + 1, // Opcode: VCNTq + /* 9136 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9151 + /* 9141 */ MCD_OPC_CheckPredicate, + 26, + 101, + 39, + 0, // Skip to: 19231 + /* 9146 */ MCD_OPC_Decode, + 196, + 23, + 231, + 1, // Opcode: VMVNd + /* 9151 */ MCD_OPC_FilterValue, + 3, + 91, + 39, + 0, // Skip to: 19231 + /* 9156 */ MCD_OPC_CheckPredicate, + 26, + 86, + 39, + 0, // Skip to: 19231 + /* 9161 */ MCD_OPC_Decode, + 197, + 23, + 232, + 1, // Opcode: VMVNq + /* 9166 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 9234 + /* 9171 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9174 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9189 + /* 9179 */ MCD_OPC_CheckPredicate, + 27, + 63, + 39, + 0, // Skip to: 19231 + /* 9184 */ MCD_OPC_Decode, + 217, + 16, + 231, + 1, // Opcode: VCEQzv4f16 + /* 9189 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9204 + /* 9194 */ MCD_OPC_CheckPredicate, + 27, + 48, + 39, + 0, // Skip to: 19231 + /* 9199 */ MCD_OPC_Decode, + 221, + 16, + 232, + 1, // Opcode: VCEQzv8f16 + /* 9204 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9219 + /* 9209 */ MCD_OPC_CheckPredicate, + 27, + 33, + 39, + 0, // Skip to: 19231 + /* 9214 */ MCD_OPC_Decode, + 151, + 17, + 231, + 1, // Opcode: VCLEzv4f16 + /* 9219 */ MCD_OPC_FilterValue, + 3, + 23, + 39, + 0, // Skip to: 19231 + /* 9224 */ MCD_OPC_CheckPredicate, + 27, + 18, + 39, + 0, // Skip to: 19231 + /* 9229 */ MCD_OPC_Decode, + 155, + 17, + 232, + 1, // Opcode: VCLEzv8f16 + /* 9234 */ MCD_OPC_FilterValue, + 7, + 63, + 0, + 0, // Skip to: 9302 + /* 9239 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9242 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9257 + /* 9247 */ MCD_OPC_CheckPredicate, + 27, + 251, + 38, + 0, // Skip to: 19231 + /* 9252 */ MCD_OPC_Decode, + 198, + 25, + 231, + 1, // Opcode: VRECPEhd + /* 9257 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9272 + /* 9262 */ MCD_OPC_CheckPredicate, + 27, + 236, + 38, + 0, // Skip to: 19231 + /* 9267 */ MCD_OPC_Decode, + 199, + 25, + 232, + 1, // Opcode: VRECPEhq + /* 9272 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9287 + /* 9277 */ MCD_OPC_CheckPredicate, + 27, + 221, + 38, + 0, // Skip to: 19231 + /* 9282 */ MCD_OPC_Decode, + 184, + 26, + 231, + 1, // Opcode: VRSQRTEhd + /* 9287 */ MCD_OPC_FilterValue, + 3, + 211, + 38, + 0, // Skip to: 19231 + /* 9292 */ MCD_OPC_CheckPredicate, + 27, + 206, + 38, + 0, // Skip to: 19231 + /* 9297 */ MCD_OPC_Decode, + 185, + 26, + 232, + 1, // Opcode: VRSQRTEhq + /* 9302 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 9370 + /* 9307 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9310 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9325 + /* 9315 */ MCD_OPC_CheckPredicate, + 26, + 183, + 38, + 0, // Skip to: 19231 + /* 9320 */ MCD_OPC_Decode, + 215, + 16, + 231, + 1, // Opcode: VCEQzv2f32 + /* 9325 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9340 + /* 9330 */ MCD_OPC_CheckPredicate, + 26, + 168, + 38, + 0, // Skip to: 19231 + /* 9335 */ MCD_OPC_Decode, + 218, + 16, + 232, + 1, // Opcode: VCEQzv4f32 + /* 9340 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9355 + /* 9345 */ MCD_OPC_CheckPredicate, + 26, + 153, + 38, + 0, // Skip to: 19231 + /* 9350 */ MCD_OPC_Decode, + 149, + 17, + 231, + 1, // Opcode: VCLEzv2f32 + /* 9355 */ MCD_OPC_FilterValue, + 3, + 143, + 38, + 0, // Skip to: 19231 + /* 9360 */ MCD_OPC_CheckPredicate, + 26, + 138, + 38, + 0, // Skip to: 19231 + /* 9365 */ MCD_OPC_Decode, + 152, + 17, + 232, + 1, // Opcode: VCLEzv4f32 + /* 9370 */ MCD_OPC_FilterValue, + 11, + 128, + 38, + 0, // Skip to: 19231 + /* 9375 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9378 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9393 + /* 9383 */ MCD_OPC_CheckPredicate, + 26, + 115, + 38, + 0, // Skip to: 19231 + /* 9388 */ MCD_OPC_Decode, + 196, + 25, + 231, + 1, // Opcode: VRECPEfd + /* 9393 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9408 + /* 9398 */ MCD_OPC_CheckPredicate, + 26, + 100, + 38, + 0, // Skip to: 19231 + /* 9403 */ MCD_OPC_Decode, + 197, + 25, + 232, + 1, // Opcode: VRECPEfq + /* 9408 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9423 + /* 9413 */ MCD_OPC_CheckPredicate, + 26, + 85, + 38, + 0, // Skip to: 19231 + /* 9418 */ MCD_OPC_Decode, + 182, + 26, + 231, + 1, // Opcode: VRSQRTEfd + /* 9423 */ MCD_OPC_FilterValue, + 3, + 75, + 38, + 0, // Skip to: 19231 + /* 9428 */ MCD_OPC_CheckPredicate, + 26, + 70, + 38, + 0, // Skip to: 19231 + /* 9433 */ MCD_OPC_Decode, + 183, + 26, + 232, + 1, // Opcode: VRSQRTEfq + /* 9438 */ MCD_OPC_FilterValue, + 6, + 201, + 1, + 0, // Skip to: 9900 + /* 9443 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9446 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 9514 + /* 9451 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9454 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9469 + /* 9459 */ MCD_OPC_CheckPredicate, + 26, + 39, + 38, + 0, // Skip to: 19231 + /* 9464 */ MCD_OPC_Decode, + 237, + 23, + 237, + 1, // Opcode: VPADALsv8i8 + /* 9469 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9484 + /* 9474 */ MCD_OPC_CheckPredicate, + 26, + 24, + 38, + 0, // Skip to: 19231 + /* 9479 */ MCD_OPC_Decode, + 232, + 23, + 238, + 1, // Opcode: VPADALsv16i8 + /* 9484 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9499 + /* 9489 */ MCD_OPC_CheckPredicate, + 26, + 9, + 38, + 0, // Skip to: 19231 + /* 9494 */ MCD_OPC_Decode, + 243, + 23, + 237, + 1, // Opcode: VPADALuv8i8 + /* 9499 */ MCD_OPC_FilterValue, + 3, + 255, + 37, + 0, // Skip to: 19231 + /* 9504 */ MCD_OPC_CheckPredicate, + 26, + 250, + 37, + 0, // Skip to: 19231 + /* 9509 */ MCD_OPC_Decode, + 238, + 23, + 238, + 1, // Opcode: VPADALuv16i8 + /* 9514 */ MCD_OPC_FilterValue, + 4, + 63, + 0, + 0, // Skip to: 9582 + /* 9519 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9522 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9537 + /* 9527 */ MCD_OPC_CheckPredicate, + 26, + 227, + 37, + 0, // Skip to: 19231 + /* 9532 */ MCD_OPC_Decode, + 234, + 23, + 237, + 1, // Opcode: VPADALsv4i16 + /* 9537 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9552 + /* 9542 */ MCD_OPC_CheckPredicate, + 26, + 212, + 37, + 0, // Skip to: 19231 + /* 9547 */ MCD_OPC_Decode, + 236, + 23, + 238, + 1, // Opcode: VPADALsv8i16 + /* 9552 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9567 + /* 9557 */ MCD_OPC_CheckPredicate, + 26, + 197, + 37, + 0, // Skip to: 19231 + /* 9562 */ MCD_OPC_Decode, + 240, + 23, + 237, + 1, // Opcode: VPADALuv4i16 + /* 9567 */ MCD_OPC_FilterValue, + 3, + 187, + 37, + 0, // Skip to: 19231 + /* 9572 */ MCD_OPC_CheckPredicate, + 26, + 182, + 37, + 0, // Skip to: 19231 + /* 9577 */ MCD_OPC_Decode, + 242, + 23, + 238, + 1, // Opcode: VPADALuv8i16 + /* 9582 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 9620 + /* 9587 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9590 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9605 + /* 9595 */ MCD_OPC_CheckPredicate, + 27, + 159, + 37, + 0, // Skip to: 19231 + /* 9600 */ MCD_OPC_Decode, + 167, + 17, + 231, + 1, // Opcode: VCLTzv4f16 + /* 9605 */ MCD_OPC_FilterValue, + 1, + 149, + 37, + 0, // Skip to: 19231 + /* 9610 */ MCD_OPC_CheckPredicate, + 27, + 144, + 37, + 0, // Skip to: 19231 + /* 9615 */ MCD_OPC_Decode, + 171, + 17, + 232, + 1, // Opcode: VCLTzv8f16 + /* 9620 */ MCD_OPC_FilterValue, + 6, + 33, + 0, + 0, // Skip to: 9658 + /* 9625 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9628 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9643 + /* 9633 */ MCD_OPC_CheckPredicate, + 30, + 121, + 37, + 0, // Skip to: 19231 + /* 9638 */ MCD_OPC_Decode, + 140, + 18, + 235, + 1, // Opcode: VCVTf2h + /* 9643 */ MCD_OPC_FilterValue, + 1, + 111, + 37, + 0, // Skip to: 19231 + /* 9648 */ MCD_OPC_CheckPredicate, + 31, + 106, + 37, + 0, // Skip to: 19231 + /* 9653 */ MCD_OPC_Decode, + 218, + 5, + 235, + 1, // Opcode: BF16_VCVT + /* 9658 */ MCD_OPC_FilterValue, + 7, + 63, + 0, + 0, // Skip to: 9726 + /* 9663 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9666 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9681 + /* 9671 */ MCD_OPC_CheckPredicate, + 27, + 83, + 37, + 0, // Skip to: 19231 + /* 9676 */ MCD_OPC_Decode, + 160, + 18, + 231, + 1, // Opcode: VCVTs2hd + /* 9681 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9696 + /* 9686 */ MCD_OPC_CheckPredicate, + 27, + 68, + 37, + 0, // Skip to: 19231 + /* 9691 */ MCD_OPC_Decode, + 161, + 18, + 232, + 1, // Opcode: VCVTs2hq + /* 9696 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9711 + /* 9701 */ MCD_OPC_CheckPredicate, + 27, + 53, + 37, + 0, // Skip to: 19231 + /* 9706 */ MCD_OPC_Decode, + 164, + 18, + 231, + 1, // Opcode: VCVTu2hd + /* 9711 */ MCD_OPC_FilterValue, + 3, + 43, + 37, + 0, // Skip to: 19231 + /* 9716 */ MCD_OPC_CheckPredicate, + 27, + 38, + 37, + 0, // Skip to: 19231 + /* 9721 */ MCD_OPC_Decode, + 165, + 18, + 232, + 1, // Opcode: VCVTu2hq + /* 9726 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 9794 + /* 9731 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9734 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9749 + /* 9739 */ MCD_OPC_CheckPredicate, + 26, + 15, + 37, + 0, // Skip to: 19231 + /* 9744 */ MCD_OPC_Decode, + 233, + 23, + 237, + 1, // Opcode: VPADALsv2i32 + /* 9749 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9764 + /* 9754 */ MCD_OPC_CheckPredicate, + 26, + 0, + 37, + 0, // Skip to: 19231 + /* 9759 */ MCD_OPC_Decode, + 235, + 23, + 238, + 1, // Opcode: VPADALsv4i32 + /* 9764 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9779 + /* 9769 */ MCD_OPC_CheckPredicate, + 26, + 241, + 36, + 0, // Skip to: 19231 + /* 9774 */ MCD_OPC_Decode, + 239, + 23, + 237, + 1, // Opcode: VPADALuv2i32 + /* 9779 */ MCD_OPC_FilterValue, + 3, + 231, + 36, + 0, // Skip to: 19231 + /* 9784 */ MCD_OPC_CheckPredicate, + 26, + 226, + 36, + 0, // Skip to: 19231 + /* 9789 */ MCD_OPC_Decode, + 241, + 23, + 238, + 1, // Opcode: VPADALuv4i32 + /* 9794 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 9832 + /* 9799 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9802 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9817 + /* 9807 */ MCD_OPC_CheckPredicate, + 26, + 203, + 36, + 0, // Skip to: 19231 + /* 9812 */ MCD_OPC_Decode, + 165, + 17, + 231, + 1, // Opcode: VCLTzv2f32 + /* 9817 */ MCD_OPC_FilterValue, + 1, + 193, + 36, + 0, // Skip to: 19231 + /* 9822 */ MCD_OPC_CheckPredicate, + 26, + 188, + 36, + 0, // Skip to: 19231 + /* 9827 */ MCD_OPC_Decode, + 168, + 17, + 232, + 1, // Opcode: VCLTzv4f32 + /* 9832 */ MCD_OPC_FilterValue, + 11, + 178, + 36, + 0, // Skip to: 19231 + /* 9837 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9840 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9855 + /* 9845 */ MCD_OPC_CheckPredicate, + 26, + 165, + 36, + 0, // Skip to: 19231 + /* 9850 */ MCD_OPC_Decode, + 158, + 18, + 231, + 1, // Opcode: VCVTs2fd + /* 9855 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9870 + /* 9860 */ MCD_OPC_CheckPredicate, + 26, + 150, + 36, + 0, // Skip to: 19231 + /* 9865 */ MCD_OPC_Decode, + 159, + 18, + 232, + 1, // Opcode: VCVTs2fq + /* 9870 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9885 + /* 9875 */ MCD_OPC_CheckPredicate, + 26, + 135, + 36, + 0, // Skip to: 19231 + /* 9880 */ MCD_OPC_Decode, + 162, + 18, + 231, + 1, // Opcode: VCVTu2fd + /* 9885 */ MCD_OPC_FilterValue, + 3, + 125, + 36, + 0, // Skip to: 19231 + /* 9890 */ MCD_OPC_CheckPredicate, + 26, + 120, + 36, + 0, // Skip to: 19231 + /* 9895 */ MCD_OPC_Decode, + 163, + 18, + 232, + 1, // Opcode: VCVTu2fq + /* 9900 */ MCD_OPC_FilterValue, + 7, + 245, + 1, + 0, // Skip to: 10406 + /* 9905 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9908 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 9976 + /* 9913 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9916 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9931 + /* 9921 */ MCD_OPC_CheckPredicate, + 26, + 89, + 36, + 0, // Skip to: 19231 + /* 9926 */ MCD_OPC_Decode, + 154, + 24, + 231, + 1, // Opcode: VQABSv8i8 + /* 9931 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9946 + /* 9936 */ MCD_OPC_CheckPredicate, + 26, + 74, + 36, + 0, // Skip to: 19231 + /* 9941 */ MCD_OPC_Decode, + 149, + 24, + 232, + 1, // Opcode: VQABSv16i8 + /* 9946 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9961 + /* 9951 */ MCD_OPC_CheckPredicate, + 26, + 59, + 36, + 0, // Skip to: 19231 + /* 9956 */ MCD_OPC_Decode, + 205, + 24, + 231, + 1, // Opcode: VQNEGv8i8 + /* 9961 */ MCD_OPC_FilterValue, + 3, + 49, + 36, + 0, // Skip to: 19231 + /* 9966 */ MCD_OPC_CheckPredicate, + 26, + 44, + 36, + 0, // Skip to: 19231 + /* 9971 */ MCD_OPC_Decode, + 200, + 24, + 232, + 1, // Opcode: VQNEGv16i8 + /* 9976 */ MCD_OPC_FilterValue, + 4, + 63, + 0, + 0, // Skip to: 10044 + /* 9981 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9984 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9999 + /* 9989 */ MCD_OPC_CheckPredicate, + 26, + 21, + 36, + 0, // Skip to: 19231 + /* 9994 */ MCD_OPC_Decode, + 151, + 24, + 231, + 1, // Opcode: VQABSv4i16 + /* 9999 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10014 + /* 10004 */ MCD_OPC_CheckPredicate, + 26, + 6, + 36, + 0, // Skip to: 19231 + /* 10009 */ MCD_OPC_Decode, + 153, + 24, + 232, + 1, // Opcode: VQABSv8i16 + /* 10014 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10029 + /* 10019 */ MCD_OPC_CheckPredicate, + 26, + 247, + 35, + 0, // Skip to: 19231 + /* 10024 */ MCD_OPC_Decode, + 202, + 24, + 231, + 1, // Opcode: VQNEGv4i16 + /* 10029 */ MCD_OPC_FilterValue, + 3, + 237, + 35, + 0, // Skip to: 19231 + /* 10034 */ MCD_OPC_CheckPredicate, + 26, + 232, + 35, + 0, // Skip to: 19231 + /* 10039 */ MCD_OPC_Decode, + 204, + 24, + 232, + 1, // Opcode: VQNEGv8i16 + /* 10044 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 10112 + /* 10049 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 10052 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10067 + /* 10057 */ MCD_OPC_CheckPredicate, + 27, + 209, + 35, + 0, // Skip to: 19231 + /* 10062 */ MCD_OPC_Decode, + 134, + 16, + 231, + 1, // Opcode: VABShd + /* 10067 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10082 + /* 10072 */ MCD_OPC_CheckPredicate, + 27, + 194, + 35, + 0, // Skip to: 19231 + /* 10077 */ MCD_OPC_Decode, + 135, + 16, + 232, + 1, // Opcode: VABShq + /* 10082 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10097 + /* 10087 */ MCD_OPC_CheckPredicate, + 27, + 179, + 35, + 0, // Skip to: 19231 + /* 10092 */ MCD_OPC_Decode, + 207, + 23, + 231, + 1, // Opcode: VNEGhd + /* 10097 */ MCD_OPC_FilterValue, + 3, + 169, + 35, + 0, // Skip to: 19231 + /* 10102 */ MCD_OPC_CheckPredicate, + 27, + 164, + 35, + 0, // Skip to: 19231 + /* 10107 */ MCD_OPC_Decode, + 208, + 23, + 232, + 1, // Opcode: VNEGhq + /* 10112 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 10134 + /* 10117 */ MCD_OPC_CheckPredicate, + 30, + 149, + 35, + 0, // Skip to: 19231 + /* 10122 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 142, + 35, + 0, // Skip to: 19231 + /* 10129 */ MCD_OPC_Decode, + 149, + 18, + 239, + 1, // Opcode: VCVTh2f + /* 10134 */ MCD_OPC_FilterValue, + 7, + 63, + 0, + 0, // Skip to: 10202 + /* 10139 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 10142 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10157 + /* 10147 */ MCD_OPC_CheckPredicate, + 27, + 119, + 35, + 0, // Skip to: 19231 + /* 10152 */ MCD_OPC_Decode, + 150, + 18, + 231, + 1, // Opcode: VCVTh2sd + /* 10157 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10172 + /* 10162 */ MCD_OPC_CheckPredicate, + 27, + 104, + 35, + 0, // Skip to: 19231 + /* 10167 */ MCD_OPC_Decode, + 151, + 18, + 232, + 1, // Opcode: VCVTh2sq + /* 10172 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10187 + /* 10177 */ MCD_OPC_CheckPredicate, + 27, + 89, + 35, + 0, // Skip to: 19231 + /* 10182 */ MCD_OPC_Decode, + 152, + 18, + 231, + 1, // Opcode: VCVTh2ud + /* 10187 */ MCD_OPC_FilterValue, + 3, + 79, + 35, + 0, // Skip to: 19231 + /* 10192 */ MCD_OPC_CheckPredicate, + 27, + 74, + 35, + 0, // Skip to: 19231 + /* 10197 */ MCD_OPC_Decode, + 153, + 18, + 232, + 1, // Opcode: VCVTh2uq + /* 10202 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 10270 + /* 10207 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 10210 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10225 + /* 10215 */ MCD_OPC_CheckPredicate, + 26, + 51, + 35, + 0, // Skip to: 19231 + /* 10220 */ MCD_OPC_Decode, + 150, + 24, + 231, + 1, // Opcode: VQABSv2i32 + /* 10225 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10240 + /* 10230 */ MCD_OPC_CheckPredicate, + 26, + 36, + 35, + 0, // Skip to: 19231 + /* 10235 */ MCD_OPC_Decode, + 152, + 24, + 232, + 1, // Opcode: VQABSv4i32 + /* 10240 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10255 + /* 10245 */ MCD_OPC_CheckPredicate, + 26, + 21, + 35, + 0, // Skip to: 19231 + /* 10250 */ MCD_OPC_Decode, + 201, + 24, + 231, + 1, // Opcode: VQNEGv2i32 + /* 10255 */ MCD_OPC_FilterValue, + 3, + 11, + 35, + 0, // Skip to: 19231 + /* 10260 */ MCD_OPC_CheckPredicate, + 26, + 6, + 35, + 0, // Skip to: 19231 + /* 10265 */ MCD_OPC_Decode, + 203, + 24, + 232, + 1, // Opcode: VQNEGv4i32 + /* 10270 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 10338 + /* 10275 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 10278 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10293 + /* 10283 */ MCD_OPC_CheckPredicate, + 26, + 239, + 34, + 0, // Skip to: 19231 + /* 10288 */ MCD_OPC_Decode, + 132, + 16, + 231, + 1, // Opcode: VABSfd + /* 10293 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10308 + /* 10298 */ MCD_OPC_CheckPredicate, + 26, + 224, + 34, + 0, // Skip to: 19231 + /* 10303 */ MCD_OPC_Decode, + 133, + 16, + 232, + 1, // Opcode: VABSfq + /* 10308 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10323 + /* 10313 */ MCD_OPC_CheckPredicate, + 26, + 209, + 34, + 0, // Skip to: 19231 + /* 10318 */ MCD_OPC_Decode, + 206, + 23, + 231, + 1, // Opcode: VNEGfd + /* 10323 */ MCD_OPC_FilterValue, + 3, + 199, + 34, + 0, // Skip to: 19231 + /* 10328 */ MCD_OPC_CheckPredicate, + 26, + 194, + 34, + 0, // Skip to: 19231 + /* 10333 */ MCD_OPC_Decode, + 205, + 23, + 232, + 1, // Opcode: VNEGf32q + /* 10338 */ MCD_OPC_FilterValue, + 11, + 184, + 34, + 0, // Skip to: 19231 + /* 10343 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 10346 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10361 + /* 10351 */ MCD_OPC_CheckPredicate, + 26, + 171, + 34, + 0, // Skip to: 19231 + /* 10356 */ MCD_OPC_Decode, + 141, + 18, + 231, + 1, // Opcode: VCVTf2sd + /* 10361 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10376 + /* 10366 */ MCD_OPC_CheckPredicate, + 26, + 156, + 34, + 0, // Skip to: 19231 + /* 10371 */ MCD_OPC_Decode, + 142, + 18, + 232, + 1, // Opcode: VCVTf2sq + /* 10376 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10391 + /* 10381 */ MCD_OPC_CheckPredicate, + 26, + 141, + 34, + 0, // Skip to: 19231 + /* 10386 */ MCD_OPC_Decode, + 143, + 18, + 231, + 1, // Opcode: VCVTf2ud + /* 10391 */ MCD_OPC_FilterValue, + 3, + 131, + 34, + 0, // Skip to: 19231 + /* 10396 */ MCD_OPC_CheckPredicate, + 26, + 126, + 34, + 0, // Skip to: 19231 + /* 10401 */ MCD_OPC_Decode, + 144, + 18, + 232, + 1, // Opcode: VCVTf2uq + /* 10406 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 10444 + /* 10411 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10414 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10429 + /* 10419 */ MCD_OPC_CheckPredicate, + 26, + 103, + 34, + 0, // Skip to: 19231 + /* 10424 */ MCD_OPC_Decode, + 136, + 30, + 240, + 1, // Opcode: VTBL1 + /* 10429 */ MCD_OPC_FilterValue, + 1, + 93, + 34, + 0, // Skip to: 19231 + /* 10434 */ MCD_OPC_CheckPredicate, + 26, + 88, + 34, + 0, // Skip to: 19231 + /* 10439 */ MCD_OPC_Decode, + 142, + 30, + 240, + 1, // Opcode: VTBX1 + /* 10444 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 10482 + /* 10449 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10452 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10467 + /* 10457 */ MCD_OPC_CheckPredicate, + 26, + 65, + 34, + 0, // Skip to: 19231 + /* 10462 */ MCD_OPC_Decode, + 137, + 30, + 240, + 1, // Opcode: VTBL2 + /* 10467 */ MCD_OPC_FilterValue, + 1, + 55, + 34, + 0, // Skip to: 19231 + /* 10472 */ MCD_OPC_CheckPredicate, + 26, + 50, + 34, + 0, // Skip to: 19231 + /* 10477 */ MCD_OPC_Decode, + 143, + 30, + 240, + 1, // Opcode: VTBX2 + /* 10482 */ MCD_OPC_FilterValue, + 10, + 33, + 0, + 0, // Skip to: 10520 + /* 10487 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10490 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10505 + /* 10495 */ MCD_OPC_CheckPredicate, + 26, + 27, + 34, + 0, // Skip to: 19231 + /* 10500 */ MCD_OPC_Decode, + 138, + 30, + 240, + 1, // Opcode: VTBL3 + /* 10505 */ MCD_OPC_FilterValue, + 1, + 17, + 34, + 0, // Skip to: 19231 + /* 10510 */ MCD_OPC_CheckPredicate, + 26, + 12, + 34, + 0, // Skip to: 19231 + /* 10515 */ MCD_OPC_Decode, + 144, + 30, + 240, + 1, // Opcode: VTBX3 + /* 10520 */ MCD_OPC_FilterValue, + 11, + 33, + 0, + 0, // Skip to: 10558 + /* 10525 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10528 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10543 + /* 10533 */ MCD_OPC_CheckPredicate, + 26, + 245, + 33, + 0, // Skip to: 19231 + /* 10538 */ MCD_OPC_Decode, + 140, + 30, + 240, + 1, // Opcode: VTBL4 + /* 10543 */ MCD_OPC_FilterValue, + 1, + 235, + 33, + 0, // Skip to: 19231 + /* 10548 */ MCD_OPC_CheckPredicate, + 26, + 230, + 33, + 0, // Skip to: 19231 + /* 10553 */ MCD_OPC_Decode, + 146, + 30, + 240, + 1, // Opcode: VTBX4 + /* 10558 */ MCD_OPC_FilterValue, + 12, + 220, + 33, + 0, // Skip to: 19231 + /* 10563 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 10566 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 10634 + /* 10571 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10574 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 10619 + /* 10579 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 10582 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 10604 + /* 10587 */ MCD_OPC_CheckPredicate, + 26, + 191, + 33, + 0, // Skip to: 19231 + /* 10592 */ MCD_OPC_CheckField, + 18, + 1, + 1, + 184, + 33, + 0, // Skip to: 19231 + /* 10599 */ MCD_OPC_Decode, + 185, + 18, + 241, + 1, // Opcode: VDUPLN32d + /* 10604 */ MCD_OPC_FilterValue, + 1, + 174, + 33, + 0, // Skip to: 19231 + /* 10609 */ MCD_OPC_CheckPredicate, + 26, + 169, + 33, + 0, // Skip to: 19231 + /* 10614 */ MCD_OPC_Decode, + 183, + 18, + 242, + 1, // Opcode: VDUPLN16d + /* 10619 */ MCD_OPC_FilterValue, + 1, + 159, + 33, + 0, // Skip to: 19231 + /* 10624 */ MCD_OPC_CheckPredicate, + 26, + 154, + 33, + 0, // Skip to: 19231 + /* 10629 */ MCD_OPC_Decode, + 187, + 18, + 243, + 1, // Opcode: VDUPLN8d + /* 10634 */ MCD_OPC_FilterValue, + 1, + 144, + 33, + 0, // Skip to: 19231 + /* 10639 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10642 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 10687 + /* 10647 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 10650 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 10672 + /* 10655 */ MCD_OPC_CheckPredicate, + 26, + 123, + 33, + 0, // Skip to: 19231 + /* 10660 */ MCD_OPC_CheckField, + 18, + 1, + 1, + 116, + 33, + 0, // Skip to: 19231 + /* 10667 */ MCD_OPC_Decode, + 186, + 18, + 244, + 1, // Opcode: VDUPLN32q + /* 10672 */ MCD_OPC_FilterValue, + 1, + 106, + 33, + 0, // Skip to: 19231 + /* 10677 */ MCD_OPC_CheckPredicate, + 26, + 101, + 33, + 0, // Skip to: 19231 + /* 10682 */ MCD_OPC_Decode, + 184, + 18, + 245, + 1, // Opcode: VDUPLN16q + /* 10687 */ MCD_OPC_FilterValue, + 1, + 91, + 33, + 0, // Skip to: 19231 + /* 10692 */ MCD_OPC_CheckPredicate, + 26, + 86, + 33, + 0, // Skip to: 19231 + /* 10697 */ MCD_OPC_Decode, + 188, + 18, + 246, + 1, // Opcode: VDUPLN8q + /* 10702 */ MCD_OPC_FilterValue, + 1, + 76, + 33, + 0, // Skip to: 19231 + /* 10707 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10710 */ MCD_OPC_FilterValue, + 0, + 120, + 17, + 0, // Skip to: 15187 + /* 10715 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 10718 */ MCD_OPC_FilterValue, + 0, + 108, + 8, + 0, // Skip to: 12879 + /* 10723 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 10726 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 10894 + /* 10731 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 10734 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 10774 + /* 10739 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10742 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 10758 + /* 10748 */ MCD_OPC_CheckPredicate, + 26, + 30, + 33, + 0, // Skip to: 19231 + /* 10753 */ MCD_OPC_Decode, + 162, + 24, + 202, + 1, // Opcode: VQADDsv8i8 + /* 10758 */ MCD_OPC_FilterValue, + 243, + 1, + 19, + 33, + 0, // Skip to: 19231 + /* 10764 */ MCD_OPC_CheckPredicate, + 26, + 14, + 33, + 0, // Skip to: 19231 + /* 10769 */ MCD_OPC_Decode, + 170, + 24, + 202, + 1, // Opcode: VQADDuv8i8 + /* 10774 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 10814 + /* 10779 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10782 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 10798 + /* 10788 */ MCD_OPC_CheckPredicate, + 26, + 246, + 32, + 0, // Skip to: 19231 + /* 10793 */ MCD_OPC_Decode, + 159, + 24, + 202, + 1, // Opcode: VQADDsv4i16 + /* 10798 */ MCD_OPC_FilterValue, + 243, + 1, + 235, + 32, + 0, // Skip to: 19231 + /* 10804 */ MCD_OPC_CheckPredicate, + 26, + 230, + 32, + 0, // Skip to: 19231 + /* 10809 */ MCD_OPC_Decode, + 167, + 24, + 202, + 1, // Opcode: VQADDuv4i16 + /* 10814 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 10854 + /* 10819 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10822 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 10838 + /* 10828 */ MCD_OPC_CheckPredicate, + 26, + 206, + 32, + 0, // Skip to: 19231 + /* 10833 */ MCD_OPC_Decode, + 157, + 24, + 202, + 1, // Opcode: VQADDsv2i32 + /* 10838 */ MCD_OPC_FilterValue, + 243, + 1, + 195, + 32, + 0, // Skip to: 19231 + /* 10844 */ MCD_OPC_CheckPredicate, + 26, + 190, + 32, + 0, // Skip to: 19231 + /* 10849 */ MCD_OPC_Decode, + 165, + 24, + 202, + 1, // Opcode: VQADDuv2i32 + /* 10854 */ MCD_OPC_FilterValue, + 3, + 180, + 32, + 0, // Skip to: 19231 + /* 10859 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10862 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 10878 + /* 10868 */ MCD_OPC_CheckPredicate, + 26, + 166, + 32, + 0, // Skip to: 19231 + /* 10873 */ MCD_OPC_Decode, + 156, + 24, + 202, + 1, // Opcode: VQADDsv1i64 + /* 10878 */ MCD_OPC_FilterValue, + 243, + 1, + 155, + 32, + 0, // Skip to: 19231 + /* 10884 */ MCD_OPC_CheckPredicate, + 26, + 150, + 32, + 0, // Skip to: 19231 + /* 10889 */ MCD_OPC_Decode, + 164, + 24, + 202, + 1, // Opcode: VQADDuv1i64 + /* 10894 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 11062 + /* 10899 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 10902 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 10942 + /* 10907 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10910 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 10926 + /* 10916 */ MCD_OPC_CheckPredicate, + 26, + 118, + 32, + 0, // Skip to: 19231 + /* 10921 */ MCD_OPC_Decode, + 180, + 16, + 202, + 1, // Opcode: VANDd + /* 10926 */ MCD_OPC_FilterValue, + 243, + 1, + 107, + 32, + 0, // Skip to: 19231 + /* 10932 */ MCD_OPC_CheckPredicate, + 26, + 102, + 32, + 0, // Skip to: 19231 + /* 10937 */ MCD_OPC_Decode, + 189, + 18, + 202, + 1, // Opcode: VEORd + /* 10942 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 10982 + /* 10947 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10950 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 10966 + /* 10956 */ MCD_OPC_CheckPredicate, + 26, + 78, + 32, + 0, // Skip to: 19231 + /* 10961 */ MCD_OPC_Decode, + 186, + 16, + 202, + 1, // Opcode: VBICd + /* 10966 */ MCD_OPC_FilterValue, + 243, + 1, + 67, + 32, + 0, // Skip to: 19231 + /* 10972 */ MCD_OPC_CheckPredicate, + 26, + 62, + 32, + 0, // Skip to: 19231 + /* 10977 */ MCD_OPC_Decode, + 196, + 16, + 210, + 1, // Opcode: VBSLd + /* 10982 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 11022 + /* 10987 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10990 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11006 + /* 10996 */ MCD_OPC_CheckPredicate, + 26, + 38, + 32, + 0, // Skip to: 19231 + /* 11001 */ MCD_OPC_Decode, + 226, + 23, + 202, + 1, // Opcode: VORRd + /* 11006 */ MCD_OPC_FilterValue, + 243, + 1, + 27, + 32, + 0, // Skip to: 19231 + /* 11012 */ MCD_OPC_CheckPredicate, + 26, + 22, + 32, + 0, // Skip to: 19231 + /* 11017 */ MCD_OPC_Decode, + 194, + 16, + 210, + 1, // Opcode: VBITd + /* 11022 */ MCD_OPC_FilterValue, + 3, + 12, + 32, + 0, // Skip to: 19231 + /* 11027 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11030 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11046 + /* 11036 */ MCD_OPC_CheckPredicate, + 26, + 254, + 31, + 0, // Skip to: 19231 + /* 11041 */ MCD_OPC_Decode, + 224, + 23, + 202, + 1, // Opcode: VORNd + /* 11046 */ MCD_OPC_FilterValue, + 243, + 1, + 243, + 31, + 0, // Skip to: 19231 + /* 11052 */ MCD_OPC_CheckPredicate, + 26, + 238, + 31, + 0, // Skip to: 19231 + /* 11057 */ MCD_OPC_Decode, + 192, + 16, + 210, + 1, // Opcode: VBIFd + /* 11062 */ MCD_OPC_FilterValue, + 2, + 163, + 0, + 0, // Skip to: 11230 + /* 11067 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11070 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11110 + /* 11075 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11078 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11094 + /* 11084 */ MCD_OPC_CheckPredicate, + 26, + 206, + 31, + 0, // Skip to: 19231 + /* 11089 */ MCD_OPC_Decode, + 183, + 25, + 202, + 1, // Opcode: VQSUBsv8i8 + /* 11094 */ MCD_OPC_FilterValue, + 243, + 1, + 195, + 31, + 0, // Skip to: 19231 + /* 11100 */ MCD_OPC_CheckPredicate, + 26, + 190, + 31, + 0, // Skip to: 19231 + /* 11105 */ MCD_OPC_Decode, + 191, + 25, + 202, + 1, // Opcode: VQSUBuv8i8 + /* 11110 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 11150 + /* 11115 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11118 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11134 + /* 11124 */ MCD_OPC_CheckPredicate, + 26, + 166, + 31, + 0, // Skip to: 19231 + /* 11129 */ MCD_OPC_Decode, + 180, + 25, + 202, + 1, // Opcode: VQSUBsv4i16 + /* 11134 */ MCD_OPC_FilterValue, + 243, + 1, + 155, + 31, + 0, // Skip to: 19231 + /* 11140 */ MCD_OPC_CheckPredicate, + 26, + 150, + 31, + 0, // Skip to: 19231 + /* 11145 */ MCD_OPC_Decode, + 188, + 25, + 202, + 1, // Opcode: VQSUBuv4i16 + /* 11150 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 11190 + /* 11155 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11158 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11174 + /* 11164 */ MCD_OPC_CheckPredicate, + 26, + 126, + 31, + 0, // Skip to: 19231 + /* 11169 */ MCD_OPC_Decode, + 178, + 25, + 202, + 1, // Opcode: VQSUBsv2i32 + /* 11174 */ MCD_OPC_FilterValue, + 243, + 1, + 115, + 31, + 0, // Skip to: 19231 + /* 11180 */ MCD_OPC_CheckPredicate, + 26, + 110, + 31, + 0, // Skip to: 19231 + /* 11185 */ MCD_OPC_Decode, + 186, + 25, + 202, + 1, // Opcode: VQSUBuv2i32 + /* 11190 */ MCD_OPC_FilterValue, + 3, + 100, + 31, + 0, // Skip to: 19231 + /* 11195 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11198 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11214 + /* 11204 */ MCD_OPC_CheckPredicate, + 26, + 86, + 31, + 0, // Skip to: 19231 + /* 11209 */ MCD_OPC_Decode, + 177, + 25, + 202, + 1, // Opcode: VQSUBsv1i64 + /* 11214 */ MCD_OPC_FilterValue, + 243, + 1, + 75, + 31, + 0, // Skip to: 19231 + /* 11220 */ MCD_OPC_CheckPredicate, + 26, + 70, + 31, + 0, // Skip to: 19231 + /* 11225 */ MCD_OPC_Decode, + 185, + 25, + 202, + 1, // Opcode: VQSUBuv1i64 + /* 11230 */ MCD_OPC_FilterValue, + 3, + 123, + 0, + 0, // Skip to: 11358 + /* 11235 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11238 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11278 + /* 11243 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11246 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11262 + /* 11252 */ MCD_OPC_CheckPredicate, + 26, + 38, + 31, + 0, // Skip to: 19231 + /* 11257 */ MCD_OPC_Decode, + 233, + 16, + 202, + 1, // Opcode: VCGEsv8i8 + /* 11262 */ MCD_OPC_FilterValue, + 243, + 1, + 27, + 31, + 0, // Skip to: 19231 + /* 11268 */ MCD_OPC_CheckPredicate, + 26, + 22, + 31, + 0, // Skip to: 19231 + /* 11273 */ MCD_OPC_Decode, + 239, + 16, + 202, + 1, // Opcode: VCGEuv8i8 + /* 11278 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 11318 + /* 11283 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11286 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11302 + /* 11292 */ MCD_OPC_CheckPredicate, + 26, + 254, + 30, + 0, // Skip to: 19231 + /* 11297 */ MCD_OPC_Decode, + 230, + 16, + 202, + 1, // Opcode: VCGEsv4i16 + /* 11302 */ MCD_OPC_FilterValue, + 243, + 1, + 243, + 30, + 0, // Skip to: 19231 + /* 11308 */ MCD_OPC_CheckPredicate, + 26, + 238, + 30, + 0, // Skip to: 19231 + /* 11313 */ MCD_OPC_Decode, + 236, + 16, + 202, + 1, // Opcode: VCGEuv4i16 + /* 11318 */ MCD_OPC_FilterValue, + 2, + 228, + 30, + 0, // Skip to: 19231 + /* 11323 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11326 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11342 + /* 11332 */ MCD_OPC_CheckPredicate, + 26, + 214, + 30, + 0, // Skip to: 19231 + /* 11337 */ MCD_OPC_Decode, + 229, + 16, + 202, + 1, // Opcode: VCGEsv2i32 + /* 11342 */ MCD_OPC_FilterValue, + 243, + 1, + 203, + 30, + 0, // Skip to: 19231 + /* 11348 */ MCD_OPC_CheckPredicate, + 26, + 198, + 30, + 0, // Skip to: 19231 + /* 11353 */ MCD_OPC_Decode, + 235, + 16, + 202, + 1, // Opcode: VCGEuv2i32 + /* 11358 */ MCD_OPC_FilterValue, + 4, + 163, + 0, + 0, // Skip to: 11526 + /* 11363 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11366 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11406 + /* 11371 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11374 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11390 + /* 11380 */ MCD_OPC_CheckPredicate, + 26, + 166, + 30, + 0, // Skip to: 19231 + /* 11385 */ MCD_OPC_Decode, + 150, + 25, + 206, + 1, // Opcode: VQSHLsv8i8 + /* 11390 */ MCD_OPC_FilterValue, + 243, + 1, + 155, + 30, + 0, // Skip to: 19231 + /* 11396 */ MCD_OPC_CheckPredicate, + 26, + 150, + 30, + 0, // Skip to: 19231 + /* 11401 */ MCD_OPC_Decode, + 166, + 25, + 206, + 1, // Opcode: VQSHLuv8i8 + /* 11406 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 11446 + /* 11411 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11414 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11430 + /* 11420 */ MCD_OPC_CheckPredicate, + 26, + 126, + 30, + 0, // Skip to: 19231 + /* 11425 */ MCD_OPC_Decode, + 147, + 25, + 206, + 1, // Opcode: VQSHLsv4i16 + /* 11430 */ MCD_OPC_FilterValue, + 243, + 1, + 115, + 30, + 0, // Skip to: 19231 + /* 11436 */ MCD_OPC_CheckPredicate, + 26, + 110, + 30, + 0, // Skip to: 19231 + /* 11441 */ MCD_OPC_Decode, + 163, + 25, + 206, + 1, // Opcode: VQSHLuv4i16 + /* 11446 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 11486 + /* 11451 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11454 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11470 + /* 11460 */ MCD_OPC_CheckPredicate, + 26, + 86, + 30, + 0, // Skip to: 19231 + /* 11465 */ MCD_OPC_Decode, + 145, + 25, + 206, + 1, // Opcode: VQSHLsv2i32 + /* 11470 */ MCD_OPC_FilterValue, + 243, + 1, + 75, + 30, + 0, // Skip to: 19231 + /* 11476 */ MCD_OPC_CheckPredicate, + 26, + 70, + 30, + 0, // Skip to: 19231 + /* 11481 */ MCD_OPC_Decode, + 161, + 25, + 206, + 1, // Opcode: VQSHLuv2i32 + /* 11486 */ MCD_OPC_FilterValue, + 3, + 60, + 30, + 0, // Skip to: 19231 + /* 11491 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11494 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11510 + /* 11500 */ MCD_OPC_CheckPredicate, + 26, + 46, + 30, + 0, // Skip to: 19231 + /* 11505 */ MCD_OPC_Decode, + 144, + 25, + 206, + 1, // Opcode: VQSHLsv1i64 + /* 11510 */ MCD_OPC_FilterValue, + 243, + 1, + 35, + 30, + 0, // Skip to: 19231 + /* 11516 */ MCD_OPC_CheckPredicate, + 26, + 30, + 30, + 0, // Skip to: 19231 + /* 11521 */ MCD_OPC_Decode, + 160, + 25, + 206, + 1, // Opcode: VQSHLuv1i64 + /* 11526 */ MCD_OPC_FilterValue, + 5, + 163, + 0, + 0, // Skip to: 11694 + /* 11531 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11534 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11574 + /* 11539 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11542 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11558 + /* 11548 */ MCD_OPC_CheckPredicate, + 26, + 254, + 29, + 0, // Skip to: 19231 + /* 11553 */ MCD_OPC_Decode, + 237, + 24, + 206, + 1, // Opcode: VQRSHLsv8i8 + /* 11558 */ MCD_OPC_FilterValue, + 243, + 1, + 243, + 29, + 0, // Skip to: 19231 + /* 11564 */ MCD_OPC_CheckPredicate, + 26, + 238, + 29, + 0, // Skip to: 19231 + /* 11569 */ MCD_OPC_Decode, + 245, + 24, + 206, + 1, // Opcode: VQRSHLuv8i8 + /* 11574 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 11614 + /* 11579 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11582 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11598 + /* 11588 */ MCD_OPC_CheckPredicate, + 26, + 214, + 29, + 0, // Skip to: 19231 + /* 11593 */ MCD_OPC_Decode, + 234, + 24, + 206, + 1, // Opcode: VQRSHLsv4i16 + /* 11598 */ MCD_OPC_FilterValue, + 243, + 1, + 203, + 29, + 0, // Skip to: 19231 + /* 11604 */ MCD_OPC_CheckPredicate, + 26, + 198, + 29, + 0, // Skip to: 19231 + /* 11609 */ MCD_OPC_Decode, + 242, + 24, + 206, + 1, // Opcode: VQRSHLuv4i16 + /* 11614 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 11654 + /* 11619 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11622 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11638 + /* 11628 */ MCD_OPC_CheckPredicate, + 26, + 174, + 29, + 0, // Skip to: 19231 + /* 11633 */ MCD_OPC_Decode, + 232, + 24, + 206, + 1, // Opcode: VQRSHLsv2i32 + /* 11638 */ MCD_OPC_FilterValue, + 243, + 1, + 163, + 29, + 0, // Skip to: 19231 + /* 11644 */ MCD_OPC_CheckPredicate, + 26, + 158, + 29, + 0, // Skip to: 19231 + /* 11649 */ MCD_OPC_Decode, + 240, + 24, + 206, + 1, // Opcode: VQRSHLuv2i32 + /* 11654 */ MCD_OPC_FilterValue, + 3, + 148, + 29, + 0, // Skip to: 19231 + /* 11659 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11662 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11678 + /* 11668 */ MCD_OPC_CheckPredicate, + 26, + 134, + 29, + 0, // Skip to: 19231 + /* 11673 */ MCD_OPC_Decode, + 231, + 24, + 206, + 1, // Opcode: VQRSHLsv1i64 + /* 11678 */ MCD_OPC_FilterValue, + 243, + 1, + 123, + 29, + 0, // Skip to: 19231 + /* 11684 */ MCD_OPC_CheckPredicate, + 26, + 118, + 29, + 0, // Skip to: 19231 + /* 11689 */ MCD_OPC_Decode, + 239, + 24, + 206, + 1, // Opcode: VQRSHLuv1i64 + /* 11694 */ MCD_OPC_FilterValue, + 6, + 123, + 0, + 0, // Skip to: 11822 + /* 11699 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11702 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11742 + /* 11707 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11710 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11726 + /* 11716 */ MCD_OPC_CheckPredicate, + 26, + 86, + 29, + 0, // Skip to: 19231 + /* 11721 */ MCD_OPC_Decode, + 166, + 22, + 202, + 1, // Opcode: VMINsv8i8 + /* 11726 */ MCD_OPC_FilterValue, + 243, + 1, + 75, + 29, + 0, // Skip to: 19231 + /* 11732 */ MCD_OPC_CheckPredicate, + 26, + 70, + 29, + 0, // Skip to: 19231 + /* 11737 */ MCD_OPC_Decode, + 172, + 22, + 202, + 1, // Opcode: VMINuv8i8 + /* 11742 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 11782 + /* 11747 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11750 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11766 + /* 11756 */ MCD_OPC_CheckPredicate, + 26, + 46, + 29, + 0, // Skip to: 19231 + /* 11761 */ MCD_OPC_Decode, + 163, + 22, + 202, + 1, // Opcode: VMINsv4i16 + /* 11766 */ MCD_OPC_FilterValue, + 243, + 1, + 35, + 29, + 0, // Skip to: 19231 + /* 11772 */ MCD_OPC_CheckPredicate, + 26, + 30, + 29, + 0, // Skip to: 19231 + /* 11777 */ MCD_OPC_Decode, + 169, + 22, + 202, + 1, // Opcode: VMINuv4i16 + /* 11782 */ MCD_OPC_FilterValue, + 2, + 20, + 29, + 0, // Skip to: 19231 + /* 11787 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11790 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11806 + /* 11796 */ MCD_OPC_CheckPredicate, + 26, + 6, + 29, + 0, // Skip to: 19231 + /* 11801 */ MCD_OPC_Decode, + 162, + 22, + 202, + 1, // Opcode: VMINsv2i32 + /* 11806 */ MCD_OPC_FilterValue, + 243, + 1, + 251, + 28, + 0, // Skip to: 19231 + /* 11812 */ MCD_OPC_CheckPredicate, + 26, + 246, + 28, + 0, // Skip to: 19231 + /* 11817 */ MCD_OPC_Decode, + 168, + 22, + 202, + 1, // Opcode: VMINuv2i32 + /* 11822 */ MCD_OPC_FilterValue, + 7, + 123, + 0, + 0, // Skip to: 11950 + /* 11827 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11830 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11870 + /* 11835 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11838 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11854 + /* 11844 */ MCD_OPC_CheckPredicate, + 26, + 214, + 28, + 0, // Skip to: 19231 + /* 11849 */ MCD_OPC_Decode, + 228, + 15, + 210, + 1, // Opcode: VABAsv8i8 + /* 11854 */ MCD_OPC_FilterValue, + 243, + 1, + 203, + 28, + 0, // Skip to: 19231 + /* 11860 */ MCD_OPC_CheckPredicate, + 26, + 198, + 28, + 0, // Skip to: 19231 + /* 11865 */ MCD_OPC_Decode, + 234, + 15, + 210, + 1, // Opcode: VABAuv8i8 + /* 11870 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 11910 + /* 11875 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11878 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11894 + /* 11884 */ MCD_OPC_CheckPredicate, + 26, + 174, + 28, + 0, // Skip to: 19231 + /* 11889 */ MCD_OPC_Decode, + 225, + 15, + 210, + 1, // Opcode: VABAsv4i16 + /* 11894 */ MCD_OPC_FilterValue, + 243, + 1, + 163, + 28, + 0, // Skip to: 19231 + /* 11900 */ MCD_OPC_CheckPredicate, + 26, + 158, + 28, + 0, // Skip to: 19231 + /* 11905 */ MCD_OPC_Decode, + 231, + 15, + 210, + 1, // Opcode: VABAuv4i16 + /* 11910 */ MCD_OPC_FilterValue, + 2, + 148, + 28, + 0, // Skip to: 19231 + /* 11915 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11918 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11934 + /* 11924 */ MCD_OPC_CheckPredicate, + 26, + 134, + 28, + 0, // Skip to: 19231 + /* 11929 */ MCD_OPC_Decode, + 224, + 15, + 210, + 1, // Opcode: VABAsv2i32 + /* 11934 */ MCD_OPC_FilterValue, + 243, + 1, + 123, + 28, + 0, // Skip to: 19231 + /* 11940 */ MCD_OPC_CheckPredicate, + 26, + 118, + 28, + 0, // Skip to: 19231 + /* 11945 */ MCD_OPC_Decode, + 230, + 15, + 210, + 1, // Opcode: VABAuv2i32 + /* 11950 */ MCD_OPC_FilterValue, + 8, + 123, + 0, + 0, // Skip to: 12078 + /* 11955 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11958 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11998 + /* 11963 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11966 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11982 + /* 11972 */ MCD_OPC_CheckPredicate, + 26, + 86, + 28, + 0, // Skip to: 19231 + /* 11977 */ MCD_OPC_Decode, + 183, + 30, + 202, + 1, // Opcode: VTSTv8i8 + /* 11982 */ MCD_OPC_FilterValue, + 243, + 1, + 75, + 28, + 0, // Skip to: 19231 + /* 11988 */ MCD_OPC_CheckPredicate, + 26, + 70, + 28, + 0, // Skip to: 19231 + /* 11993 */ MCD_OPC_Decode, + 213, + 16, + 202, + 1, // Opcode: VCEQv8i8 + /* 11998 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 12038 + /* 12003 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12006 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12022 + /* 12012 */ MCD_OPC_CheckPredicate, + 26, + 46, + 28, + 0, // Skip to: 19231 + /* 12017 */ MCD_OPC_Decode, + 180, + 30, + 202, + 1, // Opcode: VTSTv4i16 + /* 12022 */ MCD_OPC_FilterValue, + 243, + 1, + 35, + 28, + 0, // Skip to: 19231 + /* 12028 */ MCD_OPC_CheckPredicate, + 26, + 30, + 28, + 0, // Skip to: 19231 + /* 12033 */ MCD_OPC_Decode, + 210, + 16, + 202, + 1, // Opcode: VCEQv4i16 + /* 12038 */ MCD_OPC_FilterValue, + 2, + 20, + 28, + 0, // Skip to: 19231 + /* 12043 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12046 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12062 + /* 12052 */ MCD_OPC_CheckPredicate, + 26, + 6, + 28, + 0, // Skip to: 19231 + /* 12057 */ MCD_OPC_Decode, + 179, + 30, + 202, + 1, // Opcode: VTSTv2i32 + /* 12062 */ MCD_OPC_FilterValue, + 243, + 1, + 251, + 27, + 0, // Skip to: 19231 + /* 12068 */ MCD_OPC_CheckPredicate, + 26, + 246, + 27, + 0, // Skip to: 19231 + /* 12073 */ MCD_OPC_Decode, + 209, + 16, + 202, + 1, // Opcode: VCEQv2i32 + /* 12078 */ MCD_OPC_FilterValue, + 9, + 89, + 0, + 0, // Skip to: 12172 + /* 12083 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12086 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 12126 + /* 12091 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12094 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12110 + /* 12100 */ MCD_OPC_CheckPredicate, + 26, + 214, + 27, + 0, // Skip to: 19231 + /* 12105 */ MCD_OPC_Decode, + 195, + 23, + 202, + 1, // Opcode: VMULv8i8 + /* 12110 */ MCD_OPC_FilterValue, + 243, + 1, + 203, + 27, + 0, // Skip to: 19231 + /* 12116 */ MCD_OPC_CheckPredicate, + 26, + 198, + 27, + 0, // Skip to: 19231 + /* 12121 */ MCD_OPC_Decode, + 180, + 23, + 202, + 1, // Opcode: VMULpd + /* 12126 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 12149 + /* 12131 */ MCD_OPC_CheckPredicate, + 26, + 183, + 27, + 0, // Skip to: 19231 + /* 12136 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 175, + 27, + 0, // Skip to: 19231 + /* 12144 */ MCD_OPC_Decode, + 192, + 23, + 202, + 1, // Opcode: VMULv4i16 + /* 12149 */ MCD_OPC_FilterValue, + 2, + 165, + 27, + 0, // Skip to: 19231 + /* 12154 */ MCD_OPC_CheckPredicate, + 26, + 160, + 27, + 0, // Skip to: 19231 + /* 12159 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 152, + 27, + 0, // Skip to: 19231 + /* 12167 */ MCD_OPC_Decode, + 191, + 23, + 202, + 1, // Opcode: VMULv2i32 + /* 12172 */ MCD_OPC_FilterValue, + 10, + 123, + 0, + 0, // Skip to: 12300 + /* 12177 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12180 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 12220 + /* 12185 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12188 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12204 + /* 12194 */ MCD_OPC_CheckPredicate, + 26, + 120, + 27, + 0, // Skip to: 19231 + /* 12199 */ MCD_OPC_Decode, + 145, + 24, + 202, + 1, // Opcode: VPMINs8 + /* 12204 */ MCD_OPC_FilterValue, + 243, + 1, + 109, + 27, + 0, // Skip to: 19231 + /* 12210 */ MCD_OPC_CheckPredicate, + 26, + 104, + 27, + 0, // Skip to: 19231 + /* 12215 */ MCD_OPC_Decode, + 148, + 24, + 202, + 1, // Opcode: VPMINu8 + /* 12220 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 12260 + /* 12225 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12228 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12244 + /* 12234 */ MCD_OPC_CheckPredicate, + 26, + 80, + 27, + 0, // Skip to: 19231 + /* 12239 */ MCD_OPC_Decode, + 143, + 24, + 202, + 1, // Opcode: VPMINs16 + /* 12244 */ MCD_OPC_FilterValue, + 243, + 1, + 69, + 27, + 0, // Skip to: 19231 + /* 12250 */ MCD_OPC_CheckPredicate, + 26, + 64, + 27, + 0, // Skip to: 19231 + /* 12255 */ MCD_OPC_Decode, + 146, + 24, + 202, + 1, // Opcode: VPMINu16 + /* 12260 */ MCD_OPC_FilterValue, + 2, + 54, + 27, + 0, // Skip to: 19231 + /* 12265 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12268 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12284 + /* 12274 */ MCD_OPC_CheckPredicate, + 26, + 40, + 27, + 0, // Skip to: 19231 + /* 12279 */ MCD_OPC_Decode, + 144, + 24, + 202, + 1, // Opcode: VPMINs32 + /* 12284 */ MCD_OPC_FilterValue, + 243, + 1, + 29, + 27, + 0, // Skip to: 19231 + /* 12290 */ MCD_OPC_CheckPredicate, + 26, + 24, + 27, + 0, // Skip to: 19231 + /* 12295 */ MCD_OPC_Decode, + 147, + 24, + 202, + 1, // Opcode: VPMINu32 + /* 12300 */ MCD_OPC_FilterValue, + 11, + 106, + 0, + 0, // Skip to: 12411 + /* 12305 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12308 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 12331 + /* 12313 */ MCD_OPC_CheckPredicate, + 26, + 1, + 27, + 0, // Skip to: 19231 + /* 12318 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 249, + 26, + 0, // Skip to: 19231 + /* 12326 */ MCD_OPC_Decode, + 132, + 24, + 202, + 1, // Opcode: VPADDi8 + /* 12331 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 12371 + /* 12336 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12339 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12355 + /* 12345 */ MCD_OPC_CheckPredicate, + 26, + 225, + 26, + 0, // Skip to: 19231 + /* 12350 */ MCD_OPC_Decode, + 130, + 24, + 202, + 1, // Opcode: VPADDi16 + /* 12355 */ MCD_OPC_FilterValue, + 243, + 1, + 214, + 26, + 0, // Skip to: 19231 + /* 12361 */ MCD_OPC_CheckPredicate, + 28, + 209, + 26, + 0, // Skip to: 19231 + /* 12366 */ MCD_OPC_Decode, + 211, + 24, + 210, + 1, // Opcode: VQRDMLAHv4i16 + /* 12371 */ MCD_OPC_FilterValue, + 2, + 199, + 26, + 0, // Skip to: 19231 + /* 12376 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12379 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12395 + /* 12385 */ MCD_OPC_CheckPredicate, + 26, + 185, + 26, + 0, // Skip to: 19231 + /* 12390 */ MCD_OPC_Decode, + 131, + 24, + 202, + 1, // Opcode: VPADDi32 + /* 12395 */ MCD_OPC_FilterValue, + 243, + 1, + 174, + 26, + 0, // Skip to: 19231 + /* 12401 */ MCD_OPC_CheckPredicate, + 28, + 169, + 26, + 0, // Skip to: 19231 + /* 12406 */ MCD_OPC_Decode, + 210, + 24, + 210, + 1, // Opcode: VQRDMLAHv2i32 + /* 12411 */ MCD_OPC_FilterValue, + 12, + 129, + 0, + 0, // Skip to: 12545 + /* 12416 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12419 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 12442 + /* 12424 */ MCD_OPC_CheckPredicate, + 32, + 146, + 26, + 0, // Skip to: 19231 + /* 12429 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 138, + 26, + 0, // Skip to: 19231 + /* 12437 */ MCD_OPC_Decode, + 205, + 18, + 210, + 1, // Opcode: VFMAfd + /* 12442 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 12482 + /* 12447 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12450 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12466 + /* 12456 */ MCD_OPC_CheckPredicate, + 27, + 114, + 26, + 0, // Skip to: 19231 + /* 12461 */ MCD_OPC_Decode, + 207, + 18, + 210, + 1, // Opcode: VFMAhd + /* 12466 */ MCD_OPC_FilterValue, + 243, + 1, + 103, + 26, + 0, // Skip to: 19231 + /* 12472 */ MCD_OPC_CheckPredicate, + 28, + 98, + 26, + 0, // Skip to: 19231 + /* 12477 */ MCD_OPC_Decode, + 219, + 24, + 210, + 1, // Opcode: VQRDMLSHv4i16 + /* 12482 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 12522 + /* 12487 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12490 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12506 + /* 12496 */ MCD_OPC_CheckPredicate, + 32, + 74, + 26, + 0, // Skip to: 19231 + /* 12501 */ MCD_OPC_Decode, + 216, + 18, + 210, + 1, // Opcode: VFMSfd + /* 12506 */ MCD_OPC_FilterValue, + 243, + 1, + 63, + 26, + 0, // Skip to: 19231 + /* 12512 */ MCD_OPC_CheckPredicate, + 28, + 58, + 26, + 0, // Skip to: 19231 + /* 12517 */ MCD_OPC_Decode, + 218, + 24, + 210, + 1, // Opcode: VQRDMLSHv2i32 + /* 12522 */ MCD_OPC_FilterValue, + 3, + 48, + 26, + 0, // Skip to: 19231 + /* 12527 */ MCD_OPC_CheckPredicate, + 27, + 43, + 26, + 0, // Skip to: 19231 + /* 12532 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 35, + 26, + 0, // Skip to: 19231 + /* 12540 */ MCD_OPC_Decode, + 218, + 18, + 210, + 1, // Opcode: VFMShd + /* 12545 */ MCD_OPC_FilterValue, + 13, + 129, + 0, + 0, // Skip to: 12679 + /* 12550 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12553 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 12593 + /* 12558 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12561 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12577 + /* 12567 */ MCD_OPC_CheckPredicate, + 26, + 3, + 26, + 0, // Skip to: 19231 + /* 12572 */ MCD_OPC_Decode, + 186, + 22, + 210, + 1, // Opcode: VMLAfd + /* 12577 */ MCD_OPC_FilterValue, + 243, + 1, + 248, + 25, + 0, // Skip to: 19231 + /* 12583 */ MCD_OPC_CheckPredicate, + 26, + 243, + 25, + 0, // Skip to: 19231 + /* 12588 */ MCD_OPC_Decode, + 176, + 23, + 202, + 1, // Opcode: VMULfd + /* 12593 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 12633 + /* 12598 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12601 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12617 + /* 12607 */ MCD_OPC_CheckPredicate, + 27, + 219, + 25, + 0, // Skip to: 19231 + /* 12612 */ MCD_OPC_Decode, + 188, + 22, + 210, + 1, // Opcode: VMLAhd + /* 12617 */ MCD_OPC_FilterValue, + 243, + 1, + 208, + 25, + 0, // Skip to: 19231 + /* 12623 */ MCD_OPC_CheckPredicate, + 27, + 203, + 25, + 0, // Skip to: 19231 + /* 12628 */ MCD_OPC_Decode, + 178, + 23, + 202, + 1, // Opcode: VMULhd + /* 12633 */ MCD_OPC_FilterValue, + 2, + 18, + 0, + 0, // Skip to: 12656 + /* 12638 */ MCD_OPC_CheckPredicate, + 26, + 188, + 25, + 0, // Skip to: 19231 + /* 12643 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 180, + 25, + 0, // Skip to: 19231 + /* 12651 */ MCD_OPC_Decode, + 217, + 22, + 210, + 1, // Opcode: VMLSfd + /* 12656 */ MCD_OPC_FilterValue, + 3, + 170, + 25, + 0, // Skip to: 19231 + /* 12661 */ MCD_OPC_CheckPredicate, + 27, + 165, + 25, + 0, // Skip to: 19231 + /* 12666 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 157, + 25, + 0, // Skip to: 19231 + /* 12674 */ MCD_OPC_Decode, + 219, + 22, + 210, + 1, // Opcode: VMLShd + /* 12679 */ MCD_OPC_FilterValue, + 14, + 95, + 0, + 0, // Skip to: 12779 + /* 12684 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12687 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 12710 + /* 12692 */ MCD_OPC_CheckPredicate, + 26, + 134, + 25, + 0, // Skip to: 19231 + /* 12697 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 126, + 25, + 0, // Skip to: 19231 + /* 12705 */ MCD_OPC_Decode, + 142, + 16, + 202, + 1, // Opcode: VACGEfd + /* 12710 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 12733 + /* 12715 */ MCD_OPC_CheckPredicate, + 27, + 111, + 25, + 0, // Skip to: 19231 + /* 12720 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 103, + 25, + 0, // Skip to: 19231 + /* 12728 */ MCD_OPC_Decode, + 144, + 16, + 202, + 1, // Opcode: VACGEhd + /* 12733 */ MCD_OPC_FilterValue, + 2, + 18, + 0, + 0, // Skip to: 12756 + /* 12738 */ MCD_OPC_CheckPredicate, + 26, + 88, + 25, + 0, // Skip to: 19231 + /* 12743 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 80, + 25, + 0, // Skip to: 19231 + /* 12751 */ MCD_OPC_Decode, + 146, + 16, + 202, + 1, // Opcode: VACGTfd + /* 12756 */ MCD_OPC_FilterValue, + 3, + 70, + 25, + 0, // Skip to: 19231 + /* 12761 */ MCD_OPC_CheckPredicate, + 27, + 65, + 25, + 0, // Skip to: 19231 + /* 12766 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 57, + 25, + 0, // Skip to: 19231 + /* 12774 */ MCD_OPC_Decode, + 148, + 16, + 202, + 1, // Opcode: VACGThd + /* 12779 */ MCD_OPC_FilterValue, + 15, + 47, + 25, + 0, // Skip to: 19231 + /* 12784 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12787 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 12810 + /* 12792 */ MCD_OPC_CheckPredicate, + 26, + 34, + 25, + 0, // Skip to: 19231 + /* 12797 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 26, + 25, + 0, // Skip to: 19231 + /* 12805 */ MCD_OPC_Decode, + 201, + 25, + 202, + 1, // Opcode: VRECPSfd + /* 12810 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 12833 + /* 12815 */ MCD_OPC_CheckPredicate, + 27, + 11, + 25, + 0, // Skip to: 19231 + /* 12820 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 3, + 25, + 0, // Skip to: 19231 + /* 12828 */ MCD_OPC_Decode, + 203, + 25, + 202, + 1, // Opcode: VRECPShd + /* 12833 */ MCD_OPC_FilterValue, + 2, + 18, + 0, + 0, // Skip to: 12856 + /* 12838 */ MCD_OPC_CheckPredicate, + 26, + 244, + 24, + 0, // Skip to: 19231 + /* 12843 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 236, + 24, + 0, // Skip to: 19231 + /* 12851 */ MCD_OPC_Decode, + 187, + 26, + 202, + 1, // Opcode: VRSQRTSfd + /* 12856 */ MCD_OPC_FilterValue, + 3, + 226, + 24, + 0, // Skip to: 19231 + /* 12861 */ MCD_OPC_CheckPredicate, + 27, + 221, + 24, + 0, // Skip to: 19231 + /* 12866 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 213, + 24, + 0, // Skip to: 19231 + /* 12874 */ MCD_OPC_Decode, + 189, + 26, + 202, + 1, // Opcode: VRSQRTShd + /* 12879 */ MCD_OPC_FilterValue, + 1, + 203, + 24, + 0, // Skip to: 19231 + /* 12884 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 12887 */ MCD_OPC_FilterValue, + 0, + 209, + 7, + 0, // Skip to: 14893 + /* 12892 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 12895 */ MCD_OPC_FilterValue, + 121, + 187, + 24, + 0, // Skip to: 19231 + /* 12900 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 12903 */ MCD_OPC_FilterValue, + 0, + 139, + 0, + 0, // Skip to: 13047 + /* 12908 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 12911 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 13009 + /* 12916 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 12919 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 12971 + /* 12924 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 12927 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 12949 + /* 12932 */ MCD_OPC_CheckPredicate, + 26, + 231, + 6, + 0, // Skip to: 14704 + /* 12937 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 224, + 6, + 0, // Skip to: 14704 + /* 12944 */ MCD_OPC_Decode, + 146, + 27, + 247, + 1, // Opcode: VSHRsv8i8 + /* 12949 */ MCD_OPC_FilterValue, + 1, + 214, + 6, + 0, // Skip to: 14704 + /* 12954 */ MCD_OPC_CheckPredicate, + 26, + 209, + 6, + 0, // Skip to: 14704 + /* 12959 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 202, + 6, + 0, // Skip to: 14704 + /* 12966 */ MCD_OPC_Decode, + 154, + 27, + 247, + 1, // Opcode: VSHRuv8i8 + /* 12971 */ MCD_OPC_FilterValue, + 1, + 192, + 6, + 0, // Skip to: 14704 + /* 12976 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 12979 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 12994 + /* 12984 */ MCD_OPC_CheckPredicate, + 26, + 179, + 6, + 0, // Skip to: 14704 + /* 12989 */ MCD_OPC_Decode, + 143, + 27, + 248, + 1, // Opcode: VSHRsv4i16 + /* 12994 */ MCD_OPC_FilterValue, + 1, + 169, + 6, + 0, // Skip to: 14704 + /* 12999 */ MCD_OPC_CheckPredicate, + 26, + 164, + 6, + 0, // Skip to: 14704 + /* 13004 */ MCD_OPC_Decode, + 151, + 27, + 248, + 1, // Opcode: VSHRuv4i16 + /* 13009 */ MCD_OPC_FilterValue, + 1, + 154, + 6, + 0, // Skip to: 14704 + /* 13014 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13017 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13032 + /* 13022 */ MCD_OPC_CheckPredicate, + 26, + 141, + 6, + 0, // Skip to: 14704 + /* 13027 */ MCD_OPC_Decode, + 141, + 27, + 249, + 1, // Opcode: VSHRsv2i32 + /* 13032 */ MCD_OPC_FilterValue, + 1, + 131, + 6, + 0, // Skip to: 14704 + /* 13037 */ MCD_OPC_CheckPredicate, + 26, + 126, + 6, + 0, // Skip to: 14704 + /* 13042 */ MCD_OPC_Decode, + 149, + 27, + 249, + 1, // Opcode: VSHRuv2i32 + /* 13047 */ MCD_OPC_FilterValue, + 1, + 139, + 0, + 0, // Skip to: 13191 + /* 13052 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13055 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 13153 + /* 13060 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13063 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 13115 + /* 13068 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13071 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 13093 + /* 13076 */ MCD_OPC_CheckPredicate, + 26, + 87, + 6, + 0, // Skip to: 14704 + /* 13081 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 80, + 6, + 0, // Skip to: 14704 + /* 13088 */ MCD_OPC_Decode, + 183, + 27, + 250, + 1, // Opcode: VSRAsv8i8 + /* 13093 */ MCD_OPC_FilterValue, + 1, + 70, + 6, + 0, // Skip to: 14704 + /* 13098 */ MCD_OPC_CheckPredicate, + 26, + 65, + 6, + 0, // Skip to: 14704 + /* 13103 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 58, + 6, + 0, // Skip to: 14704 + /* 13110 */ MCD_OPC_Decode, + 191, + 27, + 250, + 1, // Opcode: VSRAuv8i8 + /* 13115 */ MCD_OPC_FilterValue, + 1, + 48, + 6, + 0, // Skip to: 14704 + /* 13120 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13123 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13138 + /* 13128 */ MCD_OPC_CheckPredicate, + 26, + 35, + 6, + 0, // Skip to: 14704 + /* 13133 */ MCD_OPC_Decode, + 180, + 27, + 251, + 1, // Opcode: VSRAsv4i16 + /* 13138 */ MCD_OPC_FilterValue, + 1, + 25, + 6, + 0, // Skip to: 14704 + /* 13143 */ MCD_OPC_CheckPredicate, + 26, + 20, + 6, + 0, // Skip to: 14704 + /* 13148 */ MCD_OPC_Decode, + 188, + 27, + 251, + 1, // Opcode: VSRAuv4i16 + /* 13153 */ MCD_OPC_FilterValue, + 1, + 10, + 6, + 0, // Skip to: 14704 + /* 13158 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13161 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13176 + /* 13166 */ MCD_OPC_CheckPredicate, + 26, + 253, + 5, + 0, // Skip to: 14704 + /* 13171 */ MCD_OPC_Decode, + 178, + 27, + 252, + 1, // Opcode: VSRAsv2i32 + /* 13176 */ MCD_OPC_FilterValue, + 1, + 243, + 5, + 0, // Skip to: 14704 + /* 13181 */ MCD_OPC_CheckPredicate, + 26, + 238, + 5, + 0, // Skip to: 14704 + /* 13186 */ MCD_OPC_Decode, + 186, + 27, + 252, + 1, // Opcode: VSRAuv2i32 + /* 13191 */ MCD_OPC_FilterValue, + 2, + 139, + 0, + 0, // Skip to: 13335 + /* 13196 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13199 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 13297 + /* 13204 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13207 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 13259 + /* 13212 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13215 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 13237 + /* 13220 */ MCD_OPC_CheckPredicate, + 26, + 199, + 5, + 0, // Skip to: 14704 + /* 13225 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 192, + 5, + 0, // Skip to: 14704 + /* 13232 */ MCD_OPC_Decode, + 172, + 26, + 247, + 1, // Opcode: VRSHRsv8i8 + /* 13237 */ MCD_OPC_FilterValue, + 1, + 182, + 5, + 0, // Skip to: 14704 + /* 13242 */ MCD_OPC_CheckPredicate, + 26, + 177, + 5, + 0, // Skip to: 14704 + /* 13247 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 170, + 5, + 0, // Skip to: 14704 + /* 13254 */ MCD_OPC_Decode, + 180, + 26, + 247, + 1, // Opcode: VRSHRuv8i8 + /* 13259 */ MCD_OPC_FilterValue, + 1, + 160, + 5, + 0, // Skip to: 14704 + /* 13264 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13267 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13282 + /* 13272 */ MCD_OPC_CheckPredicate, + 26, + 147, + 5, + 0, // Skip to: 14704 + /* 13277 */ MCD_OPC_Decode, + 169, + 26, + 248, + 1, // Opcode: VRSHRsv4i16 + /* 13282 */ MCD_OPC_FilterValue, + 1, + 137, + 5, + 0, // Skip to: 14704 + /* 13287 */ MCD_OPC_CheckPredicate, + 26, + 132, + 5, + 0, // Skip to: 14704 + /* 13292 */ MCD_OPC_Decode, + 177, + 26, + 248, + 1, // Opcode: VRSHRuv4i16 + /* 13297 */ MCD_OPC_FilterValue, + 1, + 122, + 5, + 0, // Skip to: 14704 + /* 13302 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13305 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13320 + /* 13310 */ MCD_OPC_CheckPredicate, + 26, + 109, + 5, + 0, // Skip to: 14704 + /* 13315 */ MCD_OPC_Decode, + 167, + 26, + 249, + 1, // Opcode: VRSHRsv2i32 + /* 13320 */ MCD_OPC_FilterValue, + 1, + 99, + 5, + 0, // Skip to: 14704 + /* 13325 */ MCD_OPC_CheckPredicate, + 26, + 94, + 5, + 0, // Skip to: 14704 + /* 13330 */ MCD_OPC_Decode, + 175, + 26, + 249, + 1, // Opcode: VRSHRuv2i32 + /* 13335 */ MCD_OPC_FilterValue, + 3, + 139, + 0, + 0, // Skip to: 13479 + /* 13340 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13343 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 13441 + /* 13348 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13351 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 13403 + /* 13356 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13359 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 13381 + /* 13364 */ MCD_OPC_CheckPredicate, + 26, + 55, + 5, + 0, // Skip to: 14704 + /* 13369 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 48, + 5, + 0, // Skip to: 14704 + /* 13376 */ MCD_OPC_Decode, + 198, + 26, + 250, + 1, // Opcode: VRSRAsv8i8 + /* 13381 */ MCD_OPC_FilterValue, + 1, + 38, + 5, + 0, // Skip to: 14704 + /* 13386 */ MCD_OPC_CheckPredicate, + 26, + 33, + 5, + 0, // Skip to: 14704 + /* 13391 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 26, + 5, + 0, // Skip to: 14704 + /* 13398 */ MCD_OPC_Decode, + 206, + 26, + 250, + 1, // Opcode: VRSRAuv8i8 + /* 13403 */ MCD_OPC_FilterValue, + 1, + 16, + 5, + 0, // Skip to: 14704 + /* 13408 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13411 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13426 + /* 13416 */ MCD_OPC_CheckPredicate, + 26, + 3, + 5, + 0, // Skip to: 14704 + /* 13421 */ MCD_OPC_Decode, + 195, + 26, + 251, + 1, // Opcode: VRSRAsv4i16 + /* 13426 */ MCD_OPC_FilterValue, + 1, + 249, + 4, + 0, // Skip to: 14704 + /* 13431 */ MCD_OPC_CheckPredicate, + 26, + 244, + 4, + 0, // Skip to: 14704 + /* 13436 */ MCD_OPC_Decode, + 203, + 26, + 251, + 1, // Opcode: VRSRAuv4i16 + /* 13441 */ MCD_OPC_FilterValue, + 1, + 234, + 4, + 0, // Skip to: 14704 + /* 13446 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13449 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13464 + /* 13454 */ MCD_OPC_CheckPredicate, + 26, + 221, + 4, + 0, // Skip to: 14704 + /* 13459 */ MCD_OPC_Decode, + 193, + 26, + 252, + 1, // Opcode: VRSRAsv2i32 + /* 13464 */ MCD_OPC_FilterValue, + 1, + 211, + 4, + 0, // Skip to: 14704 + /* 13469 */ MCD_OPC_CheckPredicate, + 26, + 206, + 4, + 0, // Skip to: 14704 + /* 13474 */ MCD_OPC_Decode, + 201, + 26, + 252, + 1, // Opcode: VRSRAuv2i32 + /* 13479 */ MCD_OPC_FilterValue, + 4, + 84, + 0, + 0, // Skip to: 13568 + /* 13484 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13487 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 13546 + /* 13492 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13495 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 13524 + /* 13500 */ MCD_OPC_CheckPredicate, + 26, + 175, + 4, + 0, // Skip to: 14704 + /* 13505 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 168, + 4, + 0, // Skip to: 14704 + /* 13512 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 161, + 4, + 0, // Skip to: 14704 + /* 13519 */ MCD_OPC_Decode, + 199, + 27, + 250, + 1, // Opcode: VSRIv8i8 + /* 13524 */ MCD_OPC_FilterValue, + 1, + 151, + 4, + 0, // Skip to: 14704 + /* 13529 */ MCD_OPC_CheckPredicate, + 26, + 146, + 4, + 0, // Skip to: 14704 + /* 13534 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 139, + 4, + 0, // Skip to: 14704 + /* 13541 */ MCD_OPC_Decode, + 196, + 27, + 251, + 1, // Opcode: VSRIv4i16 + /* 13546 */ MCD_OPC_FilterValue, + 1, + 129, + 4, + 0, // Skip to: 14704 + /* 13551 */ MCD_OPC_CheckPredicate, + 26, + 124, + 4, + 0, // Skip to: 14704 + /* 13556 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 117, + 4, + 0, // Skip to: 14704 + /* 13563 */ MCD_OPC_Decode, + 194, + 27, + 252, + 1, // Opcode: VSRIv2i32 + /* 13568 */ MCD_OPC_FilterValue, + 5, + 139, + 0, + 0, // Skip to: 13712 + /* 13573 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13576 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 13674 + /* 13581 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13584 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 13636 + /* 13589 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13592 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 13614 + /* 13597 */ MCD_OPC_CheckPredicate, + 26, + 78, + 4, + 0, // Skip to: 14704 + /* 13602 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 71, + 4, + 0, // Skip to: 14704 + /* 13609 */ MCD_OPC_Decode, + 247, + 26, + 253, + 1, // Opcode: VSHLiv8i8 + /* 13614 */ MCD_OPC_FilterValue, + 1, + 61, + 4, + 0, // Skip to: 14704 + /* 13619 */ MCD_OPC_CheckPredicate, + 26, + 56, + 4, + 0, // Skip to: 14704 + /* 13624 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 49, + 4, + 0, // Skip to: 14704 + /* 13631 */ MCD_OPC_Decode, + 168, + 27, + 254, + 1, // Opcode: VSLIv8i8 + /* 13636 */ MCD_OPC_FilterValue, + 1, + 39, + 4, + 0, // Skip to: 14704 + /* 13641 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13644 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13659 + /* 13649 */ MCD_OPC_CheckPredicate, + 26, + 26, + 4, + 0, // Skip to: 14704 + /* 13654 */ MCD_OPC_Decode, + 244, + 26, + 255, + 1, // Opcode: VSHLiv4i16 + /* 13659 */ MCD_OPC_FilterValue, + 1, + 16, + 4, + 0, // Skip to: 14704 + /* 13664 */ MCD_OPC_CheckPredicate, + 26, + 11, + 4, + 0, // Skip to: 14704 + /* 13669 */ MCD_OPC_Decode, + 165, + 27, + 128, + 2, // Opcode: VSLIv4i16 + /* 13674 */ MCD_OPC_FilterValue, + 1, + 1, + 4, + 0, // Skip to: 14704 + /* 13679 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13682 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13697 + /* 13687 */ MCD_OPC_CheckPredicate, + 26, + 244, + 3, + 0, // Skip to: 14704 + /* 13692 */ MCD_OPC_Decode, + 242, + 26, + 129, + 2, // Opcode: VSHLiv2i32 + /* 13697 */ MCD_OPC_FilterValue, + 1, + 234, + 3, + 0, // Skip to: 14704 + /* 13702 */ MCD_OPC_CheckPredicate, + 26, + 229, + 3, + 0, // Skip to: 14704 + /* 13707 */ MCD_OPC_Decode, + 163, + 27, + 130, + 2, // Opcode: VSLIv2i32 + /* 13712 */ MCD_OPC_FilterValue, + 6, + 84, + 0, + 0, // Skip to: 13801 + /* 13717 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13720 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 13779 + /* 13725 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13728 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 13757 + /* 13733 */ MCD_OPC_CheckPredicate, + 26, + 198, + 3, + 0, // Skip to: 14704 + /* 13738 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 191, + 3, + 0, // Skip to: 14704 + /* 13745 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 184, + 3, + 0, // Skip to: 14704 + /* 13752 */ MCD_OPC_Decode, + 142, + 25, + 253, + 1, // Opcode: VQSHLsuv8i8 + /* 13757 */ MCD_OPC_FilterValue, + 1, + 174, + 3, + 0, // Skip to: 14704 + /* 13762 */ MCD_OPC_CheckPredicate, + 26, + 169, + 3, + 0, // Skip to: 14704 + /* 13767 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 162, + 3, + 0, // Skip to: 14704 + /* 13774 */ MCD_OPC_Decode, + 139, + 25, + 255, + 1, // Opcode: VQSHLsuv4i16 + /* 13779 */ MCD_OPC_FilterValue, + 1, + 152, + 3, + 0, // Skip to: 14704 + /* 13784 */ MCD_OPC_CheckPredicate, + 26, + 147, + 3, + 0, // Skip to: 14704 + /* 13789 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 140, + 3, + 0, // Skip to: 14704 + /* 13796 */ MCD_OPC_Decode, + 137, + 25, + 129, + 2, // Opcode: VQSHLsuv2i32 + /* 13801 */ MCD_OPC_FilterValue, + 7, + 139, + 0, + 0, // Skip to: 13945 + /* 13806 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13809 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 13907 + /* 13814 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13817 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 13869 + /* 13822 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13825 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 13847 + /* 13830 */ MCD_OPC_CheckPredicate, + 26, + 101, + 3, + 0, // Skip to: 14704 + /* 13835 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 94, + 3, + 0, // Skip to: 14704 + /* 13842 */ MCD_OPC_Decode, + 134, + 25, + 253, + 1, // Opcode: VQSHLsiv8i8 + /* 13847 */ MCD_OPC_FilterValue, + 1, + 84, + 3, + 0, // Skip to: 14704 + /* 13852 */ MCD_OPC_CheckPredicate, + 26, + 79, + 3, + 0, // Skip to: 14704 + /* 13857 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 72, + 3, + 0, // Skip to: 14704 + /* 13864 */ MCD_OPC_Decode, + 158, + 25, + 253, + 1, // Opcode: VQSHLuiv8i8 + /* 13869 */ MCD_OPC_FilterValue, + 1, + 62, + 3, + 0, // Skip to: 14704 + /* 13874 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13877 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13892 + /* 13882 */ MCD_OPC_CheckPredicate, + 26, + 49, + 3, + 0, // Skip to: 14704 + /* 13887 */ MCD_OPC_Decode, + 131, + 25, + 255, + 1, // Opcode: VQSHLsiv4i16 + /* 13892 */ MCD_OPC_FilterValue, + 1, + 39, + 3, + 0, // Skip to: 14704 + /* 13897 */ MCD_OPC_CheckPredicate, + 26, + 34, + 3, + 0, // Skip to: 14704 + /* 13902 */ MCD_OPC_Decode, + 155, + 25, + 255, + 1, // Opcode: VQSHLuiv4i16 + /* 13907 */ MCD_OPC_FilterValue, + 1, + 24, + 3, + 0, // Skip to: 14704 + /* 13912 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13915 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13930 + /* 13920 */ MCD_OPC_CheckPredicate, + 26, + 11, + 3, + 0, // Skip to: 14704 + /* 13925 */ MCD_OPC_Decode, + 129, + 25, + 129, + 2, // Opcode: VQSHLsiv2i32 + /* 13930 */ MCD_OPC_FilterValue, + 1, + 1, + 3, + 0, // Skip to: 14704 + /* 13935 */ MCD_OPC_CheckPredicate, + 26, + 252, + 2, + 0, // Skip to: 14704 + /* 13940 */ MCD_OPC_Decode, + 153, + 25, + 129, + 2, // Opcode: VQSHLuiv2i32 + /* 13945 */ MCD_OPC_FilterValue, + 8, + 139, + 0, + 0, // Skip to: 14089 + /* 13950 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13953 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 14051 + /* 13958 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13961 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 14013 + /* 13966 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13969 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 13991 + /* 13974 */ MCD_OPC_CheckPredicate, + 26, + 213, + 2, + 0, // Skip to: 14704 + /* 13979 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 206, + 2, + 0, // Skip to: 14704 + /* 13986 */ MCD_OPC_Decode, + 138, + 27, + 131, + 2, // Opcode: VSHRNv8i8 + /* 13991 */ MCD_OPC_FilterValue, + 1, + 196, + 2, + 0, // Skip to: 14704 + /* 13996 */ MCD_OPC_CheckPredicate, + 26, + 191, + 2, + 0, // Skip to: 14704 + /* 14001 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 184, + 2, + 0, // Skip to: 14704 + /* 14008 */ MCD_OPC_Decode, + 175, + 25, + 131, + 2, // Opcode: VQSHRUNv8i8 + /* 14013 */ MCD_OPC_FilterValue, + 1, + 174, + 2, + 0, // Skip to: 14704 + /* 14018 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14021 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14036 + /* 14026 */ MCD_OPC_CheckPredicate, + 26, + 161, + 2, + 0, // Skip to: 14704 + /* 14031 */ MCD_OPC_Decode, + 137, + 27, + 132, + 2, // Opcode: VSHRNv4i16 + /* 14036 */ MCD_OPC_FilterValue, + 1, + 151, + 2, + 0, // Skip to: 14704 + /* 14041 */ MCD_OPC_CheckPredicate, + 26, + 146, + 2, + 0, // Skip to: 14704 + /* 14046 */ MCD_OPC_Decode, + 174, + 25, + 132, + 2, // Opcode: VQSHRUNv4i16 + /* 14051 */ MCD_OPC_FilterValue, + 1, + 136, + 2, + 0, // Skip to: 14704 + /* 14056 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14059 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14074 + /* 14064 */ MCD_OPC_CheckPredicate, + 26, + 123, + 2, + 0, // Skip to: 14704 + /* 14069 */ MCD_OPC_Decode, + 136, + 27, + 133, + 2, // Opcode: VSHRNv2i32 + /* 14074 */ MCD_OPC_FilterValue, + 1, + 113, + 2, + 0, // Skip to: 14704 + /* 14079 */ MCD_OPC_CheckPredicate, + 26, + 108, + 2, + 0, // Skip to: 14704 + /* 14084 */ MCD_OPC_Decode, + 173, + 25, + 133, + 2, // Opcode: VQSHRUNv2i32 + /* 14089 */ MCD_OPC_FilterValue, + 9, + 139, + 0, + 0, // Skip to: 14233 + /* 14094 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 14097 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 14195 + /* 14102 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 14105 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 14157 + /* 14110 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14113 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 14135 + /* 14118 */ MCD_OPC_CheckPredicate, + 26, + 69, + 2, + 0, // Skip to: 14704 + /* 14123 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 62, + 2, + 0, // Skip to: 14704 + /* 14130 */ MCD_OPC_Decode, + 169, + 25, + 131, + 2, // Opcode: VQSHRNsv8i8 + /* 14135 */ MCD_OPC_FilterValue, + 1, + 52, + 2, + 0, // Skip to: 14704 + /* 14140 */ MCD_OPC_CheckPredicate, + 26, + 47, + 2, + 0, // Skip to: 14704 + /* 14145 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 40, + 2, + 0, // Skip to: 14704 + /* 14152 */ MCD_OPC_Decode, + 172, + 25, + 131, + 2, // Opcode: VQSHRNuv8i8 + /* 14157 */ MCD_OPC_FilterValue, + 1, + 30, + 2, + 0, // Skip to: 14704 + /* 14162 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14165 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14180 + /* 14170 */ MCD_OPC_CheckPredicate, + 26, + 17, + 2, + 0, // Skip to: 14704 + /* 14175 */ MCD_OPC_Decode, + 168, + 25, + 132, + 2, // Opcode: VQSHRNsv4i16 + /* 14180 */ MCD_OPC_FilterValue, + 1, + 7, + 2, + 0, // Skip to: 14704 + /* 14185 */ MCD_OPC_CheckPredicate, + 26, + 2, + 2, + 0, // Skip to: 14704 + /* 14190 */ MCD_OPC_Decode, + 171, + 25, + 132, + 2, // Opcode: VQSHRNuv4i16 + /* 14195 */ MCD_OPC_FilterValue, + 1, + 248, + 1, + 0, // Skip to: 14704 + /* 14200 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14203 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14218 + /* 14208 */ MCD_OPC_CheckPredicate, + 26, + 235, + 1, + 0, // Skip to: 14704 + /* 14213 */ MCD_OPC_Decode, + 167, + 25, + 133, + 2, // Opcode: VQSHRNsv2i32 + /* 14218 */ MCD_OPC_FilterValue, + 1, + 225, + 1, + 0, // Skip to: 14704 + /* 14223 */ MCD_OPC_CheckPredicate, + 26, + 220, + 1, + 0, // Skip to: 14704 + /* 14228 */ MCD_OPC_Decode, + 170, + 25, + 133, + 2, // Opcode: VQSHRNuv2i32 + /* 14233 */ MCD_OPC_FilterValue, + 10, + 243, + 0, + 0, // Skip to: 14481 + /* 14238 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 14241 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 14409 + /* 14246 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 14249 */ MCD_OPC_FilterValue, + 0, + 83, + 0, + 0, // Skip to: 14337 + /* 14254 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14257 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 14297 + /* 14262 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 14265 */ MCD_OPC_FilterValue, + 1, + 178, + 1, + 0, // Skip to: 14704 + /* 14270 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14287 + /* 14275 */ MCD_OPC_CheckField, + 16, + 3, + 0, + 5, + 0, + 0, // Skip to: 14287 + /* 14282 */ MCD_OPC_Decode, + 242, + 22, + 239, + 1, // Opcode: VMOVLsv8i16 + /* 14287 */ MCD_OPC_CheckPredicate, + 26, + 156, + 1, + 0, // Skip to: 14704 + /* 14292 */ MCD_OPC_Decode, + 236, + 26, + 134, + 2, // Opcode: VSHLLsv8i16 + /* 14297 */ MCD_OPC_FilterValue, + 1, + 146, + 1, + 0, // Skip to: 14704 + /* 14302 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 14305 */ MCD_OPC_FilterValue, + 1, + 138, + 1, + 0, // Skip to: 14704 + /* 14310 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14327 + /* 14315 */ MCD_OPC_CheckField, + 16, + 3, + 0, + 5, + 0, + 0, // Skip to: 14327 + /* 14322 */ MCD_OPC_Decode, + 245, + 22, + 239, + 1, // Opcode: VMOVLuv8i16 + /* 14327 */ MCD_OPC_CheckPredicate, + 26, + 116, + 1, + 0, // Skip to: 14704 + /* 14332 */ MCD_OPC_Decode, + 239, + 26, + 134, + 2, // Opcode: VSHLLuv8i16 + /* 14337 */ MCD_OPC_FilterValue, + 1, + 106, + 1, + 0, // Skip to: 14704 + /* 14342 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14345 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 14377 + /* 14350 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14367 + /* 14355 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 14367 + /* 14362 */ MCD_OPC_Decode, + 241, + 22, + 239, + 1, // Opcode: VMOVLsv4i32 + /* 14367 */ MCD_OPC_CheckPredicate, + 26, + 76, + 1, + 0, // Skip to: 14704 + /* 14372 */ MCD_OPC_Decode, + 235, + 26, + 135, + 2, // Opcode: VSHLLsv4i32 + /* 14377 */ MCD_OPC_FilterValue, + 1, + 66, + 1, + 0, // Skip to: 14704 + /* 14382 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14399 + /* 14387 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 14399 + /* 14394 */ MCD_OPC_Decode, + 244, + 22, + 239, + 1, // Opcode: VMOVLuv4i32 + /* 14399 */ MCD_OPC_CheckPredicate, + 26, + 44, + 1, + 0, // Skip to: 14704 + /* 14404 */ MCD_OPC_Decode, + 238, + 26, + 135, + 2, // Opcode: VSHLLuv4i32 + /* 14409 */ MCD_OPC_FilterValue, + 1, + 34, + 1, + 0, // Skip to: 14704 + /* 14414 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14417 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 14449 + /* 14422 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14439 + /* 14427 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 14439 + /* 14434 */ MCD_OPC_Decode, + 240, + 22, + 239, + 1, // Opcode: VMOVLsv2i64 + /* 14439 */ MCD_OPC_CheckPredicate, + 26, + 4, + 1, + 0, // Skip to: 14704 + /* 14444 */ MCD_OPC_Decode, + 234, + 26, + 136, + 2, // Opcode: VSHLLsv2i64 + /* 14449 */ MCD_OPC_FilterValue, + 1, + 250, + 0, + 0, // Skip to: 14704 + /* 14454 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14471 + /* 14459 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 14471 + /* 14466 */ MCD_OPC_Decode, + 243, + 22, + 239, + 1, // Opcode: VMOVLuv2i64 + /* 14471 */ MCD_OPC_CheckPredicate, + 26, + 228, + 0, + 0, // Skip to: 14704 + /* 14476 */ MCD_OPC_Decode, + 237, + 26, + 136, + 2, // Opcode: VSHLLuv2i64 + /* 14481 */ MCD_OPC_FilterValue, + 12, + 33, + 0, + 0, // Skip to: 14519 + /* 14486 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14489 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14504 + /* 14494 */ MCD_OPC_CheckPredicate, + 27, + 205, + 0, + 0, // Skip to: 14704 + /* 14499 */ MCD_OPC_Decode, + 168, + 18, + 137, + 2, // Opcode: VCVTxs2hd + /* 14504 */ MCD_OPC_FilterValue, + 1, + 195, + 0, + 0, // Skip to: 14704 + /* 14509 */ MCD_OPC_CheckPredicate, + 27, + 190, + 0, + 0, // Skip to: 14704 + /* 14514 */ MCD_OPC_Decode, + 172, + 18, + 137, + 2, // Opcode: VCVTxu2hd + /* 14519 */ MCD_OPC_FilterValue, + 13, + 33, + 0, + 0, // Skip to: 14557 + /* 14524 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14527 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14542 + /* 14532 */ MCD_OPC_CheckPredicate, + 27, + 167, + 0, + 0, // Skip to: 14704 + /* 14537 */ MCD_OPC_Decode, + 154, + 18, + 137, + 2, // Opcode: VCVTh2xsd + /* 14542 */ MCD_OPC_FilterValue, + 1, + 157, + 0, + 0, // Skip to: 14704 + /* 14547 */ MCD_OPC_CheckPredicate, + 27, + 152, + 0, + 0, // Skip to: 14704 + /* 14552 */ MCD_OPC_Decode, + 156, + 18, + 137, + 2, // Opcode: VCVTh2xud + /* 14557 */ MCD_OPC_FilterValue, + 14, + 80, + 0, + 0, // Skip to: 14642 + /* 14562 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 14565 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 14587 + /* 14570 */ MCD_OPC_CheckPredicate, + 26, + 34, + 0, + 0, // Skip to: 14609 + /* 14575 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 27, + 0, + 0, // Skip to: 14609 + /* 14582 */ MCD_OPC_Decode, + 137, + 23, + 138, + 2, // Opcode: VMOVv8i8 + /* 14587 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 14609 + /* 14592 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14609 + /* 14597 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 5, + 0, + 0, // Skip to: 14609 + /* 14604 */ MCD_OPC_Decode, + 129, + 23, + 138, + 2, // Opcode: VMOVv1i64 + /* 14609 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14612 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14627 + /* 14617 */ MCD_OPC_CheckPredicate, + 26, + 82, + 0, + 0, // Skip to: 14704 + /* 14622 */ MCD_OPC_Decode, + 166, + 18, + 137, + 2, // Opcode: VCVTxs2fd + /* 14627 */ MCD_OPC_FilterValue, + 1, + 72, + 0, + 0, // Skip to: 14704 + /* 14632 */ MCD_OPC_CheckPredicate, + 26, + 67, + 0, + 0, // Skip to: 14704 + /* 14637 */ MCD_OPC_Decode, + 170, + 18, + 137, + 2, // Opcode: VCVTxu2fd + /* 14642 */ MCD_OPC_FilterValue, + 15, + 57, + 0, + 0, // Skip to: 14704 + /* 14647 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14650 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14665 + /* 14655 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 14680 + /* 14660 */ MCD_OPC_Decode, + 145, + 18, + 137, + 2, // Opcode: VCVTf2xsd + /* 14665 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 14680 + /* 14670 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 14680 + /* 14675 */ MCD_OPC_Decode, + 147, + 18, + 137, + 2, // Opcode: VCVTf2xud + /* 14680 */ MCD_OPC_CheckPredicate, + 26, + 19, + 0, + 0, // Skip to: 14704 + /* 14685 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 12, + 0, + 0, // Skip to: 14704 + /* 14692 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 5, + 0, + 0, // Skip to: 14704 + /* 14699 */ MCD_OPC_Decode, + 130, + 23, + 138, + 2, // Opcode: VMOVv2f32 + /* 14704 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 14707 */ MCD_OPC_FilterValue, + 0, + 88, + 0, + 0, // Skip to: 14800 + /* 14712 */ MCD_OPC_ExtractField, + 19, + 3, // Inst{21-19} ... + /* 14715 */ MCD_OPC_FilterValue, + 0, + 159, + 17, + 0, // Skip to: 19231 + /* 14720 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 14723 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 14745 + /* 14728 */ MCD_OPC_CheckPredicate, + 26, + 57, + 0, + 0, // Skip to: 14790 + /* 14733 */ MCD_OPC_CheckField, + 10, + 2, + 2, + 50, + 0, + 0, // Skip to: 14790 + /* 14740 */ MCD_OPC_Decode, + 134, + 23, + 138, + 2, // Opcode: VMOVv4i16 + /* 14745 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 14790 + /* 14750 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 14753 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14768 + /* 14758 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 14790 + /* 14763 */ MCD_OPC_Decode, + 227, + 23, + 138, + 2, // Opcode: VORRiv2i32 + /* 14768 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 14790 + /* 14773 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14790 + /* 14778 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 5, + 0, + 0, // Skip to: 14790 + /* 14785 */ MCD_OPC_Decode, + 228, + 23, + 138, + 2, // Opcode: VORRiv4i16 + /* 14790 */ MCD_OPC_CheckPredicate, + 26, + 84, + 17, + 0, // Skip to: 19231 + /* 14795 */ MCD_OPC_Decode, + 131, + 23, + 138, + 2, // Opcode: VMOVv2i32 + /* 14800 */ MCD_OPC_FilterValue, + 1, + 74, + 17, + 0, // Skip to: 19231 + /* 14805 */ MCD_OPC_ExtractField, + 19, + 3, // Inst{21-19} ... + /* 14808 */ MCD_OPC_FilterValue, + 0, + 66, + 17, + 0, // Skip to: 19231 + /* 14813 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 14816 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 14838 + /* 14821 */ MCD_OPC_CheckPredicate, + 26, + 57, + 0, + 0, // Skip to: 14883 + /* 14826 */ MCD_OPC_CheckField, + 10, + 2, + 2, + 50, + 0, + 0, // Skip to: 14883 + /* 14833 */ MCD_OPC_Decode, + 199, + 23, + 138, + 2, // Opcode: VMVNv4i16 + /* 14838 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 14883 + /* 14843 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 14846 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14861 + /* 14851 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 14883 + /* 14856 */ MCD_OPC_Decode, + 187, + 16, + 138, + 2, // Opcode: VBICiv2i32 + /* 14861 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 14883 + /* 14866 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14883 + /* 14871 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 5, + 0, + 0, // Skip to: 14883 + /* 14878 */ MCD_OPC_Decode, + 188, + 16, + 138, + 2, // Opcode: VBICiv4i16 + /* 14883 */ MCD_OPC_CheckPredicate, + 26, + 247, + 16, + 0, // Skip to: 19231 + /* 14888 */ MCD_OPC_Decode, + 198, + 23, + 138, + 2, // Opcode: VMVNv2i32 + /* 14893 */ MCD_OPC_FilterValue, + 1, + 237, + 16, + 0, // Skip to: 19231 + /* 14898 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 14901 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 14941 + /* 14906 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 14909 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 14925 + /* 14915 */ MCD_OPC_CheckPredicate, + 26, + 215, + 16, + 0, // Skip to: 19231 + /* 14920 */ MCD_OPC_Decode, + 140, + 27, + 139, + 2, // Opcode: VSHRsv1i64 + /* 14925 */ MCD_OPC_FilterValue, + 243, + 1, + 204, + 16, + 0, // Skip to: 19231 + /* 14931 */ MCD_OPC_CheckPredicate, + 26, + 199, + 16, + 0, // Skip to: 19231 + /* 14936 */ MCD_OPC_Decode, + 148, + 27, + 139, + 2, // Opcode: VSHRuv1i64 + /* 14941 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 14981 + /* 14946 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 14949 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 14965 + /* 14955 */ MCD_OPC_CheckPredicate, + 26, + 175, + 16, + 0, // Skip to: 19231 + /* 14960 */ MCD_OPC_Decode, + 177, + 27, + 140, + 2, // Opcode: VSRAsv1i64 + /* 14965 */ MCD_OPC_FilterValue, + 243, + 1, + 164, + 16, + 0, // Skip to: 19231 + /* 14971 */ MCD_OPC_CheckPredicate, + 26, + 159, + 16, + 0, // Skip to: 19231 + /* 14976 */ MCD_OPC_Decode, + 185, + 27, + 140, + 2, // Opcode: VSRAuv1i64 + /* 14981 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 15021 + /* 14986 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 14989 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15005 + /* 14995 */ MCD_OPC_CheckPredicate, + 26, + 135, + 16, + 0, // Skip to: 19231 + /* 15000 */ MCD_OPC_Decode, + 166, + 26, + 139, + 2, // Opcode: VRSHRsv1i64 + /* 15005 */ MCD_OPC_FilterValue, + 243, + 1, + 124, + 16, + 0, // Skip to: 19231 + /* 15011 */ MCD_OPC_CheckPredicate, + 26, + 119, + 16, + 0, // Skip to: 19231 + /* 15016 */ MCD_OPC_Decode, + 174, + 26, + 139, + 2, // Opcode: VRSHRuv1i64 + /* 15021 */ MCD_OPC_FilterValue, + 3, + 35, + 0, + 0, // Skip to: 15061 + /* 15026 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15029 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15045 + /* 15035 */ MCD_OPC_CheckPredicate, + 26, + 95, + 16, + 0, // Skip to: 19231 + /* 15040 */ MCD_OPC_Decode, + 192, + 26, + 140, + 2, // Opcode: VRSRAsv1i64 + /* 15045 */ MCD_OPC_FilterValue, + 243, + 1, + 84, + 16, + 0, // Skip to: 19231 + /* 15051 */ MCD_OPC_CheckPredicate, + 26, + 79, + 16, + 0, // Skip to: 19231 + /* 15056 */ MCD_OPC_Decode, + 200, + 26, + 140, + 2, // Opcode: VRSRAuv1i64 + /* 15061 */ MCD_OPC_FilterValue, + 4, + 18, + 0, + 0, // Skip to: 15084 + /* 15066 */ MCD_OPC_CheckPredicate, + 26, + 64, + 16, + 0, // Skip to: 19231 + /* 15071 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 56, + 16, + 0, // Skip to: 19231 + /* 15079 */ MCD_OPC_Decode, + 193, + 27, + 140, + 2, // Opcode: VSRIv1i64 + /* 15084 */ MCD_OPC_FilterValue, + 5, + 35, + 0, + 0, // Skip to: 15124 + /* 15089 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15092 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15108 + /* 15098 */ MCD_OPC_CheckPredicate, + 26, + 32, + 16, + 0, // Skip to: 19231 + /* 15103 */ MCD_OPC_Decode, + 241, + 26, + 141, + 2, // Opcode: VSHLiv1i64 + /* 15108 */ MCD_OPC_FilterValue, + 243, + 1, + 21, + 16, + 0, // Skip to: 19231 + /* 15114 */ MCD_OPC_CheckPredicate, + 26, + 16, + 16, + 0, // Skip to: 19231 + /* 15119 */ MCD_OPC_Decode, + 162, + 27, + 142, + 2, // Opcode: VSLIv1i64 + /* 15124 */ MCD_OPC_FilterValue, + 6, + 18, + 0, + 0, // Skip to: 15147 + /* 15129 */ MCD_OPC_CheckPredicate, + 26, + 1, + 16, + 0, // Skip to: 19231 + /* 15134 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 249, + 15, + 0, // Skip to: 19231 + /* 15142 */ MCD_OPC_Decode, + 136, + 25, + 141, + 2, // Opcode: VQSHLsuv1i64 + /* 15147 */ MCD_OPC_FilterValue, + 7, + 239, + 15, + 0, // Skip to: 19231 + /* 15152 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15155 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15171 + /* 15161 */ MCD_OPC_CheckPredicate, + 26, + 225, + 15, + 0, // Skip to: 19231 + /* 15166 */ MCD_OPC_Decode, + 128, + 25, + 141, + 2, // Opcode: VQSHLsiv1i64 + /* 15171 */ MCD_OPC_FilterValue, + 243, + 1, + 214, + 15, + 0, // Skip to: 19231 + /* 15177 */ MCD_OPC_CheckPredicate, + 26, + 209, + 15, + 0, // Skip to: 19231 + /* 15182 */ MCD_OPC_Decode, + 152, + 25, + 141, + 2, // Opcode: VQSHLuiv1i64 + /* 15187 */ MCD_OPC_FilterValue, + 1, + 199, + 15, + 0, // Skip to: 19231 + /* 15192 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 15195 */ MCD_OPC_FilterValue, + 0, + 179, + 7, + 0, // Skip to: 17171 + /* 15200 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 15203 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 15371 + /* 15208 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 15211 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 15251 + /* 15216 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15219 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15235 + /* 15225 */ MCD_OPC_CheckPredicate, + 26, + 161, + 15, + 0, // Skip to: 19231 + /* 15230 */ MCD_OPC_Decode, + 155, + 24, + 203, + 1, // Opcode: VQADDsv16i8 + /* 15235 */ MCD_OPC_FilterValue, + 243, + 1, + 150, + 15, + 0, // Skip to: 19231 + /* 15241 */ MCD_OPC_CheckPredicate, + 26, + 145, + 15, + 0, // Skip to: 19231 + /* 15246 */ MCD_OPC_Decode, + 163, + 24, + 203, + 1, // Opcode: VQADDuv16i8 + /* 15251 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 15291 + /* 15256 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15259 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15275 + /* 15265 */ MCD_OPC_CheckPredicate, + 26, + 121, + 15, + 0, // Skip to: 19231 + /* 15270 */ MCD_OPC_Decode, + 161, + 24, + 203, + 1, // Opcode: VQADDsv8i16 + /* 15275 */ MCD_OPC_FilterValue, + 243, + 1, + 110, + 15, + 0, // Skip to: 19231 + /* 15281 */ MCD_OPC_CheckPredicate, + 26, + 105, + 15, + 0, // Skip to: 19231 + /* 15286 */ MCD_OPC_Decode, + 169, + 24, + 203, + 1, // Opcode: VQADDuv8i16 + /* 15291 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 15331 + /* 15296 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15299 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15315 + /* 15305 */ MCD_OPC_CheckPredicate, + 26, + 81, + 15, + 0, // Skip to: 19231 + /* 15310 */ MCD_OPC_Decode, + 160, + 24, + 203, + 1, // Opcode: VQADDsv4i32 + /* 15315 */ MCD_OPC_FilterValue, + 243, + 1, + 70, + 15, + 0, // Skip to: 19231 + /* 15321 */ MCD_OPC_CheckPredicate, + 26, + 65, + 15, + 0, // Skip to: 19231 + /* 15326 */ MCD_OPC_Decode, + 168, + 24, + 203, + 1, // Opcode: VQADDuv4i32 + /* 15331 */ MCD_OPC_FilterValue, + 3, + 55, + 15, + 0, // Skip to: 19231 + /* 15336 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15339 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15355 + /* 15345 */ MCD_OPC_CheckPredicate, + 26, + 41, + 15, + 0, // Skip to: 19231 + /* 15350 */ MCD_OPC_Decode, + 158, + 24, + 203, + 1, // Opcode: VQADDsv2i64 + /* 15355 */ MCD_OPC_FilterValue, + 243, + 1, + 30, + 15, + 0, // Skip to: 19231 + /* 15361 */ MCD_OPC_CheckPredicate, + 26, + 25, + 15, + 0, // Skip to: 19231 + /* 15366 */ MCD_OPC_Decode, + 166, + 24, + 203, + 1, // Opcode: VQADDuv2i64 + /* 15371 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 15539 + /* 15376 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 15379 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 15419 + /* 15384 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15387 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15403 + /* 15393 */ MCD_OPC_CheckPredicate, + 26, + 249, + 14, + 0, // Skip to: 19231 + /* 15398 */ MCD_OPC_Decode, + 181, + 16, + 203, + 1, // Opcode: VANDq + /* 15403 */ MCD_OPC_FilterValue, + 243, + 1, + 238, + 14, + 0, // Skip to: 19231 + /* 15409 */ MCD_OPC_CheckPredicate, + 26, + 233, + 14, + 0, // Skip to: 19231 + /* 15414 */ MCD_OPC_Decode, + 190, + 18, + 203, + 1, // Opcode: VEORq + /* 15419 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 15459 + /* 15424 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15427 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15443 + /* 15433 */ MCD_OPC_CheckPredicate, + 26, + 209, + 14, + 0, // Skip to: 19231 + /* 15438 */ MCD_OPC_Decode, + 191, + 16, + 203, + 1, // Opcode: VBICq + /* 15443 */ MCD_OPC_FilterValue, + 243, + 1, + 198, + 14, + 0, // Skip to: 19231 + /* 15449 */ MCD_OPC_CheckPredicate, + 26, + 193, + 14, + 0, // Skip to: 19231 + /* 15454 */ MCD_OPC_Decode, + 197, + 16, + 211, + 1, // Opcode: VBSLq + /* 15459 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 15499 + /* 15464 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15467 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15483 + /* 15473 */ MCD_OPC_CheckPredicate, + 26, + 169, + 14, + 0, // Skip to: 19231 + /* 15478 */ MCD_OPC_Decode, + 231, + 23, + 203, + 1, // Opcode: VORRq + /* 15483 */ MCD_OPC_FilterValue, + 243, + 1, + 158, + 14, + 0, // Skip to: 19231 + /* 15489 */ MCD_OPC_CheckPredicate, + 26, + 153, + 14, + 0, // Skip to: 19231 + /* 15494 */ MCD_OPC_Decode, + 195, + 16, + 211, + 1, // Opcode: VBITq + /* 15499 */ MCD_OPC_FilterValue, + 3, + 143, + 14, + 0, // Skip to: 19231 + /* 15504 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15507 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15523 + /* 15513 */ MCD_OPC_CheckPredicate, + 26, + 129, + 14, + 0, // Skip to: 19231 + /* 15518 */ MCD_OPC_Decode, + 225, + 23, + 203, + 1, // Opcode: VORNq + /* 15523 */ MCD_OPC_FilterValue, + 243, + 1, + 118, + 14, + 0, // Skip to: 19231 + /* 15529 */ MCD_OPC_CheckPredicate, + 26, + 113, + 14, + 0, // Skip to: 19231 + /* 15534 */ MCD_OPC_Decode, + 193, + 16, + 211, + 1, // Opcode: VBIFq + /* 15539 */ MCD_OPC_FilterValue, + 2, + 163, + 0, + 0, // Skip to: 15707 + /* 15544 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 15547 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 15587 + /* 15552 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15555 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15571 + /* 15561 */ MCD_OPC_CheckPredicate, + 26, + 81, + 14, + 0, // Skip to: 19231 + /* 15566 */ MCD_OPC_Decode, + 176, + 25, + 203, + 1, // Opcode: VQSUBsv16i8 + /* 15571 */ MCD_OPC_FilterValue, + 243, + 1, + 70, + 14, + 0, // Skip to: 19231 + /* 15577 */ MCD_OPC_CheckPredicate, + 26, + 65, + 14, + 0, // Skip to: 19231 + /* 15582 */ MCD_OPC_Decode, + 184, + 25, + 203, + 1, // Opcode: VQSUBuv16i8 + /* 15587 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 15627 + /* 15592 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15595 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15611 + /* 15601 */ MCD_OPC_CheckPredicate, + 26, + 41, + 14, + 0, // Skip to: 19231 + /* 15606 */ MCD_OPC_Decode, + 182, + 25, + 203, + 1, // Opcode: VQSUBsv8i16 + /* 15611 */ MCD_OPC_FilterValue, + 243, + 1, + 30, + 14, + 0, // Skip to: 19231 + /* 15617 */ MCD_OPC_CheckPredicate, + 26, + 25, + 14, + 0, // Skip to: 19231 + /* 15622 */ MCD_OPC_Decode, + 190, + 25, + 203, + 1, // Opcode: VQSUBuv8i16 + /* 15627 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 15667 + /* 15632 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15635 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15651 + /* 15641 */ MCD_OPC_CheckPredicate, + 26, + 1, + 14, + 0, // Skip to: 19231 + /* 15646 */ MCD_OPC_Decode, + 181, + 25, + 203, + 1, // Opcode: VQSUBsv4i32 + /* 15651 */ MCD_OPC_FilterValue, + 243, + 1, + 246, + 13, + 0, // Skip to: 19231 + /* 15657 */ MCD_OPC_CheckPredicate, + 26, + 241, + 13, + 0, // Skip to: 19231 + /* 15662 */ MCD_OPC_Decode, + 189, + 25, + 203, + 1, // Opcode: VQSUBuv4i32 + /* 15667 */ MCD_OPC_FilterValue, + 3, + 231, + 13, + 0, // Skip to: 19231 + /* 15672 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15675 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15691 + /* 15681 */ MCD_OPC_CheckPredicate, + 26, + 217, + 13, + 0, // Skip to: 19231 + /* 15686 */ MCD_OPC_Decode, + 179, + 25, + 203, + 1, // Opcode: VQSUBsv2i64 + /* 15691 */ MCD_OPC_FilterValue, + 243, + 1, + 206, + 13, + 0, // Skip to: 19231 + /* 15697 */ MCD_OPC_CheckPredicate, + 26, + 201, + 13, + 0, // Skip to: 19231 + /* 15702 */ MCD_OPC_Decode, + 187, + 25, + 203, + 1, // Opcode: VQSUBuv2i64 + /* 15707 */ MCD_OPC_FilterValue, + 3, + 123, + 0, + 0, // Skip to: 15835 + /* 15712 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 15715 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 15755 + /* 15720 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15723 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15739 + /* 15729 */ MCD_OPC_CheckPredicate, + 26, + 169, + 13, + 0, // Skip to: 19231 + /* 15734 */ MCD_OPC_Decode, + 228, + 16, + 203, + 1, // Opcode: VCGEsv16i8 + /* 15739 */ MCD_OPC_FilterValue, + 243, + 1, + 158, + 13, + 0, // Skip to: 19231 + /* 15745 */ MCD_OPC_CheckPredicate, + 26, + 153, + 13, + 0, // Skip to: 19231 + /* 15750 */ MCD_OPC_Decode, + 234, + 16, + 203, + 1, // Opcode: VCGEuv16i8 + /* 15755 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 15795 + /* 15760 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15763 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15779 + /* 15769 */ MCD_OPC_CheckPredicate, + 26, + 129, + 13, + 0, // Skip to: 19231 + /* 15774 */ MCD_OPC_Decode, + 232, + 16, + 203, + 1, // Opcode: VCGEsv8i16 + /* 15779 */ MCD_OPC_FilterValue, + 243, + 1, + 118, + 13, + 0, // Skip to: 19231 + /* 15785 */ MCD_OPC_CheckPredicate, + 26, + 113, + 13, + 0, // Skip to: 19231 + /* 15790 */ MCD_OPC_Decode, + 238, + 16, + 203, + 1, // Opcode: VCGEuv8i16 + /* 15795 */ MCD_OPC_FilterValue, + 2, + 103, + 13, + 0, // Skip to: 19231 + /* 15800 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15803 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15819 + /* 15809 */ MCD_OPC_CheckPredicate, + 26, + 89, + 13, + 0, // Skip to: 19231 + /* 15814 */ MCD_OPC_Decode, + 231, + 16, + 203, + 1, // Opcode: VCGEsv4i32 + /* 15819 */ MCD_OPC_FilterValue, + 243, + 1, + 78, + 13, + 0, // Skip to: 19231 + /* 15825 */ MCD_OPC_CheckPredicate, + 26, + 73, + 13, + 0, // Skip to: 19231 + /* 15830 */ MCD_OPC_Decode, + 237, + 16, + 203, + 1, // Opcode: VCGEuv4i32 + /* 15835 */ MCD_OPC_FilterValue, + 4, + 163, + 0, + 0, // Skip to: 16003 + /* 15840 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 15843 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 15883 + /* 15848 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15851 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15867 + /* 15857 */ MCD_OPC_CheckPredicate, + 26, + 41, + 13, + 0, // Skip to: 19231 + /* 15862 */ MCD_OPC_Decode, + 143, + 25, + 207, + 1, // Opcode: VQSHLsv16i8 + /* 15867 */ MCD_OPC_FilterValue, + 243, + 1, + 30, + 13, + 0, // Skip to: 19231 + /* 15873 */ MCD_OPC_CheckPredicate, + 26, + 25, + 13, + 0, // Skip to: 19231 + /* 15878 */ MCD_OPC_Decode, + 159, + 25, + 207, + 1, // Opcode: VQSHLuv16i8 + /* 15883 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 15923 + /* 15888 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15891 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15907 + /* 15897 */ MCD_OPC_CheckPredicate, + 26, + 1, + 13, + 0, // Skip to: 19231 + /* 15902 */ MCD_OPC_Decode, + 149, + 25, + 207, + 1, // Opcode: VQSHLsv8i16 + /* 15907 */ MCD_OPC_FilterValue, + 243, + 1, + 246, + 12, + 0, // Skip to: 19231 + /* 15913 */ MCD_OPC_CheckPredicate, + 26, + 241, + 12, + 0, // Skip to: 19231 + /* 15918 */ MCD_OPC_Decode, + 165, + 25, + 207, + 1, // Opcode: VQSHLuv8i16 + /* 15923 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 15963 + /* 15928 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15931 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15947 + /* 15937 */ MCD_OPC_CheckPredicate, + 26, + 217, + 12, + 0, // Skip to: 19231 + /* 15942 */ MCD_OPC_Decode, + 148, + 25, + 207, + 1, // Opcode: VQSHLsv4i32 + /* 15947 */ MCD_OPC_FilterValue, + 243, + 1, + 206, + 12, + 0, // Skip to: 19231 + /* 15953 */ MCD_OPC_CheckPredicate, + 26, + 201, + 12, + 0, // Skip to: 19231 + /* 15958 */ MCD_OPC_Decode, + 164, + 25, + 207, + 1, // Opcode: VQSHLuv4i32 + /* 15963 */ MCD_OPC_FilterValue, + 3, + 191, + 12, + 0, // Skip to: 19231 + /* 15968 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15971 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15987 + /* 15977 */ MCD_OPC_CheckPredicate, + 26, + 177, + 12, + 0, // Skip to: 19231 + /* 15982 */ MCD_OPC_Decode, + 146, + 25, + 207, + 1, // Opcode: VQSHLsv2i64 + /* 15987 */ MCD_OPC_FilterValue, + 243, + 1, + 166, + 12, + 0, // Skip to: 19231 + /* 15993 */ MCD_OPC_CheckPredicate, + 26, + 161, + 12, + 0, // Skip to: 19231 + /* 15998 */ MCD_OPC_Decode, + 162, + 25, + 207, + 1, // Opcode: VQSHLuv2i64 + /* 16003 */ MCD_OPC_FilterValue, + 5, + 163, + 0, + 0, // Skip to: 16171 + /* 16008 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16011 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 16051 + /* 16016 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16019 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16035 + /* 16025 */ MCD_OPC_CheckPredicate, + 26, + 129, + 12, + 0, // Skip to: 19231 + /* 16030 */ MCD_OPC_Decode, + 230, + 24, + 207, + 1, // Opcode: VQRSHLsv16i8 + /* 16035 */ MCD_OPC_FilterValue, + 243, + 1, + 118, + 12, + 0, // Skip to: 19231 + /* 16041 */ MCD_OPC_CheckPredicate, + 26, + 113, + 12, + 0, // Skip to: 19231 + /* 16046 */ MCD_OPC_Decode, + 238, + 24, + 207, + 1, // Opcode: VQRSHLuv16i8 + /* 16051 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 16091 + /* 16056 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16059 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16075 + /* 16065 */ MCD_OPC_CheckPredicate, + 26, + 89, + 12, + 0, // Skip to: 19231 + /* 16070 */ MCD_OPC_Decode, + 236, + 24, + 207, + 1, // Opcode: VQRSHLsv8i16 + /* 16075 */ MCD_OPC_FilterValue, + 243, + 1, + 78, + 12, + 0, // Skip to: 19231 + /* 16081 */ MCD_OPC_CheckPredicate, + 26, + 73, + 12, + 0, // Skip to: 19231 + /* 16086 */ MCD_OPC_Decode, + 244, + 24, + 207, + 1, // Opcode: VQRSHLuv8i16 + /* 16091 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 16131 + /* 16096 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16099 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16115 + /* 16105 */ MCD_OPC_CheckPredicate, + 26, + 49, + 12, + 0, // Skip to: 19231 + /* 16110 */ MCD_OPC_Decode, + 235, + 24, + 207, + 1, // Opcode: VQRSHLsv4i32 + /* 16115 */ MCD_OPC_FilterValue, + 243, + 1, + 38, + 12, + 0, // Skip to: 19231 + /* 16121 */ MCD_OPC_CheckPredicate, + 26, + 33, + 12, + 0, // Skip to: 19231 + /* 16126 */ MCD_OPC_Decode, + 243, + 24, + 207, + 1, // Opcode: VQRSHLuv4i32 + /* 16131 */ MCD_OPC_FilterValue, + 3, + 23, + 12, + 0, // Skip to: 19231 + /* 16136 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16139 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16155 + /* 16145 */ MCD_OPC_CheckPredicate, + 26, + 9, + 12, + 0, // Skip to: 19231 + /* 16150 */ MCD_OPC_Decode, + 233, + 24, + 207, + 1, // Opcode: VQRSHLsv2i64 + /* 16155 */ MCD_OPC_FilterValue, + 243, + 1, + 254, + 11, + 0, // Skip to: 19231 + /* 16161 */ MCD_OPC_CheckPredicate, + 26, + 249, + 11, + 0, // Skip to: 19231 + /* 16166 */ MCD_OPC_Decode, + 241, + 24, + 207, + 1, // Opcode: VQRSHLuv2i64 + /* 16171 */ MCD_OPC_FilterValue, + 6, + 123, + 0, + 0, // Skip to: 16299 + /* 16176 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16179 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 16219 + /* 16184 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16187 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16203 + /* 16193 */ MCD_OPC_CheckPredicate, + 26, + 217, + 11, + 0, // Skip to: 19231 + /* 16198 */ MCD_OPC_Decode, + 161, + 22, + 203, + 1, // Opcode: VMINsv16i8 + /* 16203 */ MCD_OPC_FilterValue, + 243, + 1, + 206, + 11, + 0, // Skip to: 19231 + /* 16209 */ MCD_OPC_CheckPredicate, + 26, + 201, + 11, + 0, // Skip to: 19231 + /* 16214 */ MCD_OPC_Decode, + 167, + 22, + 203, + 1, // Opcode: VMINuv16i8 + /* 16219 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 16259 + /* 16224 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16227 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16243 + /* 16233 */ MCD_OPC_CheckPredicate, + 26, + 177, + 11, + 0, // Skip to: 19231 + /* 16238 */ MCD_OPC_Decode, + 165, + 22, + 203, + 1, // Opcode: VMINsv8i16 + /* 16243 */ MCD_OPC_FilterValue, + 243, + 1, + 166, + 11, + 0, // Skip to: 19231 + /* 16249 */ MCD_OPC_CheckPredicate, + 26, + 161, + 11, + 0, // Skip to: 19231 + /* 16254 */ MCD_OPC_Decode, + 171, + 22, + 203, + 1, // Opcode: VMINuv8i16 + /* 16259 */ MCD_OPC_FilterValue, + 2, + 151, + 11, + 0, // Skip to: 19231 + /* 16264 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16267 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16283 + /* 16273 */ MCD_OPC_CheckPredicate, + 26, + 137, + 11, + 0, // Skip to: 19231 + /* 16278 */ MCD_OPC_Decode, + 164, + 22, + 203, + 1, // Opcode: VMINsv4i32 + /* 16283 */ MCD_OPC_FilterValue, + 243, + 1, + 126, + 11, + 0, // Skip to: 19231 + /* 16289 */ MCD_OPC_CheckPredicate, + 26, + 121, + 11, + 0, // Skip to: 19231 + /* 16294 */ MCD_OPC_Decode, + 170, + 22, + 203, + 1, // Opcode: VMINuv4i32 + /* 16299 */ MCD_OPC_FilterValue, + 7, + 123, + 0, + 0, // Skip to: 16427 + /* 16304 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16307 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 16347 + /* 16312 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16315 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16331 + /* 16321 */ MCD_OPC_CheckPredicate, + 26, + 89, + 11, + 0, // Skip to: 19231 + /* 16326 */ MCD_OPC_Decode, + 223, + 15, + 211, + 1, // Opcode: VABAsv16i8 + /* 16331 */ MCD_OPC_FilterValue, + 243, + 1, + 78, + 11, + 0, // Skip to: 19231 + /* 16337 */ MCD_OPC_CheckPredicate, + 26, + 73, + 11, + 0, // Skip to: 19231 + /* 16342 */ MCD_OPC_Decode, + 229, + 15, + 211, + 1, // Opcode: VABAuv16i8 + /* 16347 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 16387 + /* 16352 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16355 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16371 + /* 16361 */ MCD_OPC_CheckPredicate, + 26, + 49, + 11, + 0, // Skip to: 19231 + /* 16366 */ MCD_OPC_Decode, + 227, + 15, + 211, + 1, // Opcode: VABAsv8i16 + /* 16371 */ MCD_OPC_FilterValue, + 243, + 1, + 38, + 11, + 0, // Skip to: 19231 + /* 16377 */ MCD_OPC_CheckPredicate, + 26, + 33, + 11, + 0, // Skip to: 19231 + /* 16382 */ MCD_OPC_Decode, + 233, + 15, + 211, + 1, // Opcode: VABAuv8i16 + /* 16387 */ MCD_OPC_FilterValue, + 2, + 23, + 11, + 0, // Skip to: 19231 + /* 16392 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16395 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16411 + /* 16401 */ MCD_OPC_CheckPredicate, + 26, + 9, + 11, + 0, // Skip to: 19231 + /* 16406 */ MCD_OPC_Decode, + 226, + 15, + 211, + 1, // Opcode: VABAsv4i32 + /* 16411 */ MCD_OPC_FilterValue, + 243, + 1, + 254, + 10, + 0, // Skip to: 19231 + /* 16417 */ MCD_OPC_CheckPredicate, + 26, + 249, + 10, + 0, // Skip to: 19231 + /* 16422 */ MCD_OPC_Decode, + 232, + 15, + 211, + 1, // Opcode: VABAuv4i32 + /* 16427 */ MCD_OPC_FilterValue, + 8, + 123, + 0, + 0, // Skip to: 16555 + /* 16432 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16435 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 16475 + /* 16440 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16443 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16459 + /* 16449 */ MCD_OPC_CheckPredicate, + 26, + 217, + 10, + 0, // Skip to: 19231 + /* 16454 */ MCD_OPC_Decode, + 178, + 30, + 203, + 1, // Opcode: VTSTv16i8 + /* 16459 */ MCD_OPC_FilterValue, + 243, + 1, + 206, + 10, + 0, // Skip to: 19231 + /* 16465 */ MCD_OPC_CheckPredicate, + 26, + 201, + 10, + 0, // Skip to: 19231 + /* 16470 */ MCD_OPC_Decode, + 208, + 16, + 203, + 1, // Opcode: VCEQv16i8 + /* 16475 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 16515 + /* 16480 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16483 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16499 + /* 16489 */ MCD_OPC_CheckPredicate, + 26, + 177, + 10, + 0, // Skip to: 19231 + /* 16494 */ MCD_OPC_Decode, + 182, + 30, + 203, + 1, // Opcode: VTSTv8i16 + /* 16499 */ MCD_OPC_FilterValue, + 243, + 1, + 166, + 10, + 0, // Skip to: 19231 + /* 16505 */ MCD_OPC_CheckPredicate, + 26, + 161, + 10, + 0, // Skip to: 19231 + /* 16510 */ MCD_OPC_Decode, + 212, + 16, + 203, + 1, // Opcode: VCEQv8i16 + /* 16515 */ MCD_OPC_FilterValue, + 2, + 151, + 10, + 0, // Skip to: 19231 + /* 16520 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16523 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16539 + /* 16529 */ MCD_OPC_CheckPredicate, + 26, + 137, + 10, + 0, // Skip to: 19231 + /* 16534 */ MCD_OPC_Decode, + 181, + 30, + 203, + 1, // Opcode: VTSTv4i32 + /* 16539 */ MCD_OPC_FilterValue, + 243, + 1, + 126, + 10, + 0, // Skip to: 19231 + /* 16545 */ MCD_OPC_CheckPredicate, + 26, + 121, + 10, + 0, // Skip to: 19231 + /* 16550 */ MCD_OPC_Decode, + 211, + 16, + 203, + 1, // Opcode: VCEQv4i32 + /* 16555 */ MCD_OPC_FilterValue, + 9, + 89, + 0, + 0, // Skip to: 16649 + /* 16560 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16563 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 16603 + /* 16568 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16571 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16587 + /* 16577 */ MCD_OPC_CheckPredicate, + 26, + 89, + 10, + 0, // Skip to: 19231 + /* 16582 */ MCD_OPC_Decode, + 190, + 23, + 203, + 1, // Opcode: VMULv16i8 + /* 16587 */ MCD_OPC_FilterValue, + 243, + 1, + 78, + 10, + 0, // Skip to: 19231 + /* 16593 */ MCD_OPC_CheckPredicate, + 26, + 73, + 10, + 0, // Skip to: 19231 + /* 16598 */ MCD_OPC_Decode, + 181, + 23, + 203, + 1, // Opcode: VMULpq + /* 16603 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 16626 + /* 16608 */ MCD_OPC_CheckPredicate, + 26, + 58, + 10, + 0, // Skip to: 19231 + /* 16613 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 50, + 10, + 0, // Skip to: 19231 + /* 16621 */ MCD_OPC_Decode, + 194, + 23, + 203, + 1, // Opcode: VMULv8i16 + /* 16626 */ MCD_OPC_FilterValue, + 2, + 40, + 10, + 0, // Skip to: 19231 + /* 16631 */ MCD_OPC_CheckPredicate, + 26, + 35, + 10, + 0, // Skip to: 19231 + /* 16636 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 27, + 10, + 0, // Skip to: 19231 + /* 16644 */ MCD_OPC_Decode, + 193, + 23, + 203, + 1, // Opcode: VMULv4i32 + /* 16649 */ MCD_OPC_FilterValue, + 11, + 49, + 0, + 0, // Skip to: 16703 + /* 16654 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16657 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 16680 + /* 16662 */ MCD_OPC_CheckPredicate, + 28, + 4, + 10, + 0, // Skip to: 19231 + /* 16667 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 252, + 9, + 0, // Skip to: 19231 + /* 16675 */ MCD_OPC_Decode, + 213, + 24, + 211, + 1, // Opcode: VQRDMLAHv8i16 + /* 16680 */ MCD_OPC_FilterValue, + 2, + 242, + 9, + 0, // Skip to: 19231 + /* 16685 */ MCD_OPC_CheckPredicate, + 28, + 237, + 9, + 0, // Skip to: 19231 + /* 16690 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 229, + 9, + 0, // Skip to: 19231 + /* 16698 */ MCD_OPC_Decode, + 212, + 24, + 211, + 1, // Opcode: VQRDMLAHv4i32 + /* 16703 */ MCD_OPC_FilterValue, + 12, + 129, + 0, + 0, // Skip to: 16837 + /* 16708 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16711 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 16734 + /* 16716 */ MCD_OPC_CheckPredicate, + 32, + 206, + 9, + 0, // Skip to: 19231 + /* 16721 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 198, + 9, + 0, // Skip to: 19231 + /* 16729 */ MCD_OPC_Decode, + 206, + 18, + 211, + 1, // Opcode: VFMAfq + /* 16734 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 16774 + /* 16739 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16742 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16758 + /* 16748 */ MCD_OPC_CheckPredicate, + 27, + 174, + 9, + 0, // Skip to: 19231 + /* 16753 */ MCD_OPC_Decode, + 208, + 18, + 211, + 1, // Opcode: VFMAhq + /* 16758 */ MCD_OPC_FilterValue, + 243, + 1, + 163, + 9, + 0, // Skip to: 19231 + /* 16764 */ MCD_OPC_CheckPredicate, + 28, + 158, + 9, + 0, // Skip to: 19231 + /* 16769 */ MCD_OPC_Decode, + 221, + 24, + 211, + 1, // Opcode: VQRDMLSHv8i16 + /* 16774 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 16814 + /* 16779 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16782 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16798 + /* 16788 */ MCD_OPC_CheckPredicate, + 32, + 134, + 9, + 0, // Skip to: 19231 + /* 16793 */ MCD_OPC_Decode, + 217, + 18, + 211, + 1, // Opcode: VFMSfq + /* 16798 */ MCD_OPC_FilterValue, + 243, + 1, + 123, + 9, + 0, // Skip to: 19231 + /* 16804 */ MCD_OPC_CheckPredicate, + 28, + 118, + 9, + 0, // Skip to: 19231 + /* 16809 */ MCD_OPC_Decode, + 220, + 24, + 211, + 1, // Opcode: VQRDMLSHv4i32 + /* 16814 */ MCD_OPC_FilterValue, + 3, + 108, + 9, + 0, // Skip to: 19231 + /* 16819 */ MCD_OPC_CheckPredicate, + 27, + 103, + 9, + 0, // Skip to: 19231 + /* 16824 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 95, + 9, + 0, // Skip to: 19231 + /* 16832 */ MCD_OPC_Decode, + 219, + 18, + 211, + 1, // Opcode: VFMShq + /* 16837 */ MCD_OPC_FilterValue, + 13, + 129, + 0, + 0, // Skip to: 16971 + /* 16842 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16845 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 16885 + /* 16850 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16853 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16869 + /* 16859 */ MCD_OPC_CheckPredicate, + 26, + 63, + 9, + 0, // Skip to: 19231 + /* 16864 */ MCD_OPC_Decode, + 187, + 22, + 211, + 1, // Opcode: VMLAfq + /* 16869 */ MCD_OPC_FilterValue, + 243, + 1, + 52, + 9, + 0, // Skip to: 19231 + /* 16875 */ MCD_OPC_CheckPredicate, + 26, + 47, + 9, + 0, // Skip to: 19231 + /* 16880 */ MCD_OPC_Decode, + 177, + 23, + 203, + 1, // Opcode: VMULfq + /* 16885 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 16925 + /* 16890 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16893 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16909 + /* 16899 */ MCD_OPC_CheckPredicate, + 27, + 23, + 9, + 0, // Skip to: 19231 + /* 16904 */ MCD_OPC_Decode, + 189, + 22, + 211, + 1, // Opcode: VMLAhq + /* 16909 */ MCD_OPC_FilterValue, + 243, + 1, + 12, + 9, + 0, // Skip to: 19231 + /* 16915 */ MCD_OPC_CheckPredicate, + 27, + 7, + 9, + 0, // Skip to: 19231 + /* 16920 */ MCD_OPC_Decode, + 179, + 23, + 203, + 1, // Opcode: VMULhq + /* 16925 */ MCD_OPC_FilterValue, + 2, + 18, + 0, + 0, // Skip to: 16948 + /* 16930 */ MCD_OPC_CheckPredicate, + 26, + 248, + 8, + 0, // Skip to: 19231 + /* 16935 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 240, + 8, + 0, // Skip to: 19231 + /* 16943 */ MCD_OPC_Decode, + 218, + 22, + 211, + 1, // Opcode: VMLSfq + /* 16948 */ MCD_OPC_FilterValue, + 3, + 230, + 8, + 0, // Skip to: 19231 + /* 16953 */ MCD_OPC_CheckPredicate, + 27, + 225, + 8, + 0, // Skip to: 19231 + /* 16958 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 217, + 8, + 0, // Skip to: 19231 + /* 16966 */ MCD_OPC_Decode, + 220, + 22, + 211, + 1, // Opcode: VMLShq + /* 16971 */ MCD_OPC_FilterValue, + 14, + 95, + 0, + 0, // Skip to: 17071 + /* 16976 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16979 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 17002 + /* 16984 */ MCD_OPC_CheckPredicate, + 26, + 194, + 8, + 0, // Skip to: 19231 + /* 16989 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 186, + 8, + 0, // Skip to: 19231 + /* 16997 */ MCD_OPC_Decode, + 143, + 16, + 203, + 1, // Opcode: VACGEfq + /* 17002 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 17025 + /* 17007 */ MCD_OPC_CheckPredicate, + 27, + 171, + 8, + 0, // Skip to: 19231 + /* 17012 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 163, + 8, + 0, // Skip to: 19231 + /* 17020 */ MCD_OPC_Decode, + 145, + 16, + 203, + 1, // Opcode: VACGEhq + /* 17025 */ MCD_OPC_FilterValue, + 2, + 18, + 0, + 0, // Skip to: 17048 + /* 17030 */ MCD_OPC_CheckPredicate, + 26, + 148, + 8, + 0, // Skip to: 19231 + /* 17035 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 140, + 8, + 0, // Skip to: 19231 + /* 17043 */ MCD_OPC_Decode, + 147, + 16, + 203, + 1, // Opcode: VACGTfq + /* 17048 */ MCD_OPC_FilterValue, + 3, + 130, + 8, + 0, // Skip to: 19231 + /* 17053 */ MCD_OPC_CheckPredicate, + 27, + 125, + 8, + 0, // Skip to: 19231 + /* 17058 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 117, + 8, + 0, // Skip to: 19231 + /* 17066 */ MCD_OPC_Decode, + 149, + 16, + 203, + 1, // Opcode: VACGThq + /* 17071 */ MCD_OPC_FilterValue, + 15, + 107, + 8, + 0, // Skip to: 19231 + /* 17076 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 17079 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 17102 + /* 17084 */ MCD_OPC_CheckPredicate, + 26, + 94, + 8, + 0, // Skip to: 19231 + /* 17089 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 86, + 8, + 0, // Skip to: 19231 + /* 17097 */ MCD_OPC_Decode, + 202, + 25, + 203, + 1, // Opcode: VRECPSfq + /* 17102 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 17125 + /* 17107 */ MCD_OPC_CheckPredicate, + 27, + 71, + 8, + 0, // Skip to: 19231 + /* 17112 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 63, + 8, + 0, // Skip to: 19231 + /* 17120 */ MCD_OPC_Decode, + 204, + 25, + 203, + 1, // Opcode: VRECPShq + /* 17125 */ MCD_OPC_FilterValue, + 2, + 18, + 0, + 0, // Skip to: 17148 + /* 17130 */ MCD_OPC_CheckPredicate, + 26, + 48, + 8, + 0, // Skip to: 19231 + /* 17135 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 40, + 8, + 0, // Skip to: 19231 + /* 17143 */ MCD_OPC_Decode, + 188, + 26, + 203, + 1, // Opcode: VRSQRTSfq + /* 17148 */ MCD_OPC_FilterValue, + 3, + 30, + 8, + 0, // Skip to: 19231 + /* 17153 */ MCD_OPC_CheckPredicate, + 27, + 25, + 8, + 0, // Skip to: 19231 + /* 17158 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 17, + 8, + 0, // Skip to: 19231 + /* 17166 */ MCD_OPC_Decode, + 190, + 26, + 203, + 1, // Opcode: VRSQRTShq + /* 17171 */ MCD_OPC_FilterValue, + 1, + 7, + 8, + 0, // Skip to: 19231 + /* 17176 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 17179 */ MCD_OPC_FilterValue, + 0, + 217, + 6, + 0, // Skip to: 18937 + /* 17184 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 17187 */ MCD_OPC_FilterValue, + 121, + 247, + 7, + 0, // Skip to: 19231 + /* 17192 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 17195 */ MCD_OPC_FilterValue, + 0, + 139, + 0, + 0, // Skip to: 17339 + /* 17200 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 17203 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 17301 + /* 17208 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 17211 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 17263 + /* 17216 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17219 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 17241 + /* 17224 */ MCD_OPC_CheckPredicate, + 26, + 239, + 5, + 0, // Skip to: 18748 + /* 17229 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 232, + 5, + 0, // Skip to: 18748 + /* 17236 */ MCD_OPC_Decode, + 139, + 27, + 143, + 2, // Opcode: VSHRsv16i8 + /* 17241 */ MCD_OPC_FilterValue, + 1, + 222, + 5, + 0, // Skip to: 18748 + /* 17246 */ MCD_OPC_CheckPredicate, + 26, + 217, + 5, + 0, // Skip to: 18748 + /* 17251 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 210, + 5, + 0, // Skip to: 18748 + /* 17258 */ MCD_OPC_Decode, + 147, + 27, + 143, + 2, // Opcode: VSHRuv16i8 + /* 17263 */ MCD_OPC_FilterValue, + 1, + 200, + 5, + 0, // Skip to: 18748 + /* 17268 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17271 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17286 + /* 17276 */ MCD_OPC_CheckPredicate, + 26, + 187, + 5, + 0, // Skip to: 18748 + /* 17281 */ MCD_OPC_Decode, + 145, + 27, + 144, + 2, // Opcode: VSHRsv8i16 + /* 17286 */ MCD_OPC_FilterValue, + 1, + 177, + 5, + 0, // Skip to: 18748 + /* 17291 */ MCD_OPC_CheckPredicate, + 26, + 172, + 5, + 0, // Skip to: 18748 + /* 17296 */ MCD_OPC_Decode, + 153, + 27, + 144, + 2, // Opcode: VSHRuv8i16 + /* 17301 */ MCD_OPC_FilterValue, + 1, + 162, + 5, + 0, // Skip to: 18748 + /* 17306 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17309 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17324 + /* 17314 */ MCD_OPC_CheckPredicate, + 26, + 149, + 5, + 0, // Skip to: 18748 + /* 17319 */ MCD_OPC_Decode, + 144, + 27, + 145, + 2, // Opcode: VSHRsv4i32 + /* 17324 */ MCD_OPC_FilterValue, + 1, + 139, + 5, + 0, // Skip to: 18748 + /* 17329 */ MCD_OPC_CheckPredicate, + 26, + 134, + 5, + 0, // Skip to: 18748 + /* 17334 */ MCD_OPC_Decode, + 152, + 27, + 145, + 2, // Opcode: VSHRuv4i32 + /* 17339 */ MCD_OPC_FilterValue, + 1, + 139, + 0, + 0, // Skip to: 17483 + /* 17344 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 17347 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 17445 + /* 17352 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 17355 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 17407 + /* 17360 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17363 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 17385 + /* 17368 */ MCD_OPC_CheckPredicate, + 26, + 95, + 5, + 0, // Skip to: 18748 + /* 17373 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 88, + 5, + 0, // Skip to: 18748 + /* 17380 */ MCD_OPC_Decode, + 176, + 27, + 146, + 2, // Opcode: VSRAsv16i8 + /* 17385 */ MCD_OPC_FilterValue, + 1, + 78, + 5, + 0, // Skip to: 18748 + /* 17390 */ MCD_OPC_CheckPredicate, + 26, + 73, + 5, + 0, // Skip to: 18748 + /* 17395 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 66, + 5, + 0, // Skip to: 18748 + /* 17402 */ MCD_OPC_Decode, + 184, + 27, + 146, + 2, // Opcode: VSRAuv16i8 + /* 17407 */ MCD_OPC_FilterValue, + 1, + 56, + 5, + 0, // Skip to: 18748 + /* 17412 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17415 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17430 + /* 17420 */ MCD_OPC_CheckPredicate, + 26, + 43, + 5, + 0, // Skip to: 18748 + /* 17425 */ MCD_OPC_Decode, + 182, + 27, + 147, + 2, // Opcode: VSRAsv8i16 + /* 17430 */ MCD_OPC_FilterValue, + 1, + 33, + 5, + 0, // Skip to: 18748 + /* 17435 */ MCD_OPC_CheckPredicate, + 26, + 28, + 5, + 0, // Skip to: 18748 + /* 17440 */ MCD_OPC_Decode, + 190, + 27, + 147, + 2, // Opcode: VSRAuv8i16 + /* 17445 */ MCD_OPC_FilterValue, + 1, + 18, + 5, + 0, // Skip to: 18748 + /* 17450 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17453 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17468 + /* 17458 */ MCD_OPC_CheckPredicate, + 26, + 5, + 5, + 0, // Skip to: 18748 + /* 17463 */ MCD_OPC_Decode, + 181, + 27, + 148, + 2, // Opcode: VSRAsv4i32 + /* 17468 */ MCD_OPC_FilterValue, + 1, + 251, + 4, + 0, // Skip to: 18748 + /* 17473 */ MCD_OPC_CheckPredicate, + 26, + 246, + 4, + 0, // Skip to: 18748 + /* 17478 */ MCD_OPC_Decode, + 189, + 27, + 148, + 2, // Opcode: VSRAuv4i32 + /* 17483 */ MCD_OPC_FilterValue, + 2, + 139, + 0, + 0, // Skip to: 17627 + /* 17488 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 17491 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 17589 + /* 17496 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 17499 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 17551 + /* 17504 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17507 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 17529 + /* 17512 */ MCD_OPC_CheckPredicate, + 26, + 207, + 4, + 0, // Skip to: 18748 + /* 17517 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 200, + 4, + 0, // Skip to: 18748 + /* 17524 */ MCD_OPC_Decode, + 165, + 26, + 143, + 2, // Opcode: VRSHRsv16i8 + /* 17529 */ MCD_OPC_FilterValue, + 1, + 190, + 4, + 0, // Skip to: 18748 + /* 17534 */ MCD_OPC_CheckPredicate, + 26, + 185, + 4, + 0, // Skip to: 18748 + /* 17539 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 178, + 4, + 0, // Skip to: 18748 + /* 17546 */ MCD_OPC_Decode, + 173, + 26, + 143, + 2, // Opcode: VRSHRuv16i8 + /* 17551 */ MCD_OPC_FilterValue, + 1, + 168, + 4, + 0, // Skip to: 18748 + /* 17556 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17559 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17574 + /* 17564 */ MCD_OPC_CheckPredicate, + 26, + 155, + 4, + 0, // Skip to: 18748 + /* 17569 */ MCD_OPC_Decode, + 171, + 26, + 144, + 2, // Opcode: VRSHRsv8i16 + /* 17574 */ MCD_OPC_FilterValue, + 1, + 145, + 4, + 0, // Skip to: 18748 + /* 17579 */ MCD_OPC_CheckPredicate, + 26, + 140, + 4, + 0, // Skip to: 18748 + /* 17584 */ MCD_OPC_Decode, + 179, + 26, + 144, + 2, // Opcode: VRSHRuv8i16 + /* 17589 */ MCD_OPC_FilterValue, + 1, + 130, + 4, + 0, // Skip to: 18748 + /* 17594 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17597 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17612 + /* 17602 */ MCD_OPC_CheckPredicate, + 26, + 117, + 4, + 0, // Skip to: 18748 + /* 17607 */ MCD_OPC_Decode, + 170, + 26, + 145, + 2, // Opcode: VRSHRsv4i32 + /* 17612 */ MCD_OPC_FilterValue, + 1, + 107, + 4, + 0, // Skip to: 18748 + /* 17617 */ MCD_OPC_CheckPredicate, + 26, + 102, + 4, + 0, // Skip to: 18748 + /* 17622 */ MCD_OPC_Decode, + 178, + 26, + 145, + 2, // Opcode: VRSHRuv4i32 + /* 17627 */ MCD_OPC_FilterValue, + 3, + 139, + 0, + 0, // Skip to: 17771 + /* 17632 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 17635 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 17733 + /* 17640 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 17643 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 17695 + /* 17648 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17651 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 17673 + /* 17656 */ MCD_OPC_CheckPredicate, + 26, + 63, + 4, + 0, // Skip to: 18748 + /* 17661 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 56, + 4, + 0, // Skip to: 18748 + /* 17668 */ MCD_OPC_Decode, + 191, + 26, + 146, + 2, // Opcode: VRSRAsv16i8 + /* 17673 */ MCD_OPC_FilterValue, + 1, + 46, + 4, + 0, // Skip to: 18748 + /* 17678 */ MCD_OPC_CheckPredicate, + 26, + 41, + 4, + 0, // Skip to: 18748 + /* 17683 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 34, + 4, + 0, // Skip to: 18748 + /* 17690 */ MCD_OPC_Decode, + 199, + 26, + 146, + 2, // Opcode: VRSRAuv16i8 + /* 17695 */ MCD_OPC_FilterValue, + 1, + 24, + 4, + 0, // Skip to: 18748 + /* 17700 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17703 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17718 + /* 17708 */ MCD_OPC_CheckPredicate, + 26, + 11, + 4, + 0, // Skip to: 18748 + /* 17713 */ MCD_OPC_Decode, + 197, + 26, + 147, + 2, // Opcode: VRSRAsv8i16 + /* 17718 */ MCD_OPC_FilterValue, + 1, + 1, + 4, + 0, // Skip to: 18748 + /* 17723 */ MCD_OPC_CheckPredicate, + 26, + 252, + 3, + 0, // Skip to: 18748 + /* 17728 */ MCD_OPC_Decode, + 205, + 26, + 147, + 2, // Opcode: VRSRAuv8i16 + /* 17733 */ MCD_OPC_FilterValue, + 1, + 242, + 3, + 0, // Skip to: 18748 + /* 17738 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17741 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17756 + /* 17746 */ MCD_OPC_CheckPredicate, + 26, + 229, + 3, + 0, // Skip to: 18748 + /* 17751 */ MCD_OPC_Decode, + 196, + 26, + 148, + 2, // Opcode: VRSRAsv4i32 + /* 17756 */ MCD_OPC_FilterValue, + 1, + 219, + 3, + 0, // Skip to: 18748 + /* 17761 */ MCD_OPC_CheckPredicate, + 26, + 214, + 3, + 0, // Skip to: 18748 + /* 17766 */ MCD_OPC_Decode, + 204, + 26, + 148, + 2, // Opcode: VRSRAuv4i32 + /* 17771 */ MCD_OPC_FilterValue, + 4, + 84, + 0, + 0, // Skip to: 17860 + /* 17776 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 17779 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 17838 + /* 17784 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 17787 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 17816 + /* 17792 */ MCD_OPC_CheckPredicate, + 26, + 183, + 3, + 0, // Skip to: 18748 + /* 17797 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 176, + 3, + 0, // Skip to: 18748 + /* 17804 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 169, + 3, + 0, // Skip to: 18748 + /* 17811 */ MCD_OPC_Decode, + 192, + 27, + 146, + 2, // Opcode: VSRIv16i8 + /* 17816 */ MCD_OPC_FilterValue, + 1, + 159, + 3, + 0, // Skip to: 18748 + /* 17821 */ MCD_OPC_CheckPredicate, + 26, + 154, + 3, + 0, // Skip to: 18748 + /* 17826 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 147, + 3, + 0, // Skip to: 18748 + /* 17833 */ MCD_OPC_Decode, + 198, + 27, + 147, + 2, // Opcode: VSRIv8i16 + /* 17838 */ MCD_OPC_FilterValue, + 1, + 137, + 3, + 0, // Skip to: 18748 + /* 17843 */ MCD_OPC_CheckPredicate, + 26, + 132, + 3, + 0, // Skip to: 18748 + /* 17848 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 125, + 3, + 0, // Skip to: 18748 + /* 17855 */ MCD_OPC_Decode, + 197, + 27, + 148, + 2, // Opcode: VSRIv4i32 + /* 17860 */ MCD_OPC_FilterValue, + 5, + 139, + 0, + 0, // Skip to: 18004 + /* 17865 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 17868 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 17966 + /* 17873 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 17876 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 17928 + /* 17881 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17884 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 17906 + /* 17889 */ MCD_OPC_CheckPredicate, + 26, + 86, + 3, + 0, // Skip to: 18748 + /* 17894 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 79, + 3, + 0, // Skip to: 18748 + /* 17901 */ MCD_OPC_Decode, + 240, + 26, + 149, + 2, // Opcode: VSHLiv16i8 + /* 17906 */ MCD_OPC_FilterValue, + 1, + 69, + 3, + 0, // Skip to: 18748 + /* 17911 */ MCD_OPC_CheckPredicate, + 26, + 64, + 3, + 0, // Skip to: 18748 + /* 17916 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 57, + 3, + 0, // Skip to: 18748 + /* 17923 */ MCD_OPC_Decode, + 161, + 27, + 150, + 2, // Opcode: VSLIv16i8 + /* 17928 */ MCD_OPC_FilterValue, + 1, + 47, + 3, + 0, // Skip to: 18748 + /* 17933 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17936 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17951 + /* 17941 */ MCD_OPC_CheckPredicate, + 26, + 34, + 3, + 0, // Skip to: 18748 + /* 17946 */ MCD_OPC_Decode, + 246, + 26, + 151, + 2, // Opcode: VSHLiv8i16 + /* 17951 */ MCD_OPC_FilterValue, + 1, + 24, + 3, + 0, // Skip to: 18748 + /* 17956 */ MCD_OPC_CheckPredicate, + 26, + 19, + 3, + 0, // Skip to: 18748 + /* 17961 */ MCD_OPC_Decode, + 167, + 27, + 152, + 2, // Opcode: VSLIv8i16 + /* 17966 */ MCD_OPC_FilterValue, + 1, + 9, + 3, + 0, // Skip to: 18748 + /* 17971 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17974 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17989 + /* 17979 */ MCD_OPC_CheckPredicate, + 26, + 252, + 2, + 0, // Skip to: 18748 + /* 17984 */ MCD_OPC_Decode, + 245, + 26, + 153, + 2, // Opcode: VSHLiv4i32 + /* 17989 */ MCD_OPC_FilterValue, + 1, + 242, + 2, + 0, // Skip to: 18748 + /* 17994 */ MCD_OPC_CheckPredicate, + 26, + 237, + 2, + 0, // Skip to: 18748 + /* 17999 */ MCD_OPC_Decode, + 166, + 27, + 154, + 2, // Opcode: VSLIv4i32 + /* 18004 */ MCD_OPC_FilterValue, + 6, + 84, + 0, + 0, // Skip to: 18093 + /* 18009 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 18012 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 18071 + /* 18017 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 18020 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 18049 + /* 18025 */ MCD_OPC_CheckPredicate, + 26, + 206, + 2, + 0, // Skip to: 18748 + /* 18030 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 199, + 2, + 0, // Skip to: 18748 + /* 18037 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 192, + 2, + 0, // Skip to: 18748 + /* 18044 */ MCD_OPC_Decode, + 135, + 25, + 149, + 2, // Opcode: VQSHLsuv16i8 + /* 18049 */ MCD_OPC_FilterValue, + 1, + 182, + 2, + 0, // Skip to: 18748 + /* 18054 */ MCD_OPC_CheckPredicate, + 26, + 177, + 2, + 0, // Skip to: 18748 + /* 18059 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 170, + 2, + 0, // Skip to: 18748 + /* 18066 */ MCD_OPC_Decode, + 141, + 25, + 151, + 2, // Opcode: VQSHLsuv8i16 + /* 18071 */ MCD_OPC_FilterValue, + 1, + 160, + 2, + 0, // Skip to: 18748 + /* 18076 */ MCD_OPC_CheckPredicate, + 26, + 155, + 2, + 0, // Skip to: 18748 + /* 18081 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 148, + 2, + 0, // Skip to: 18748 + /* 18088 */ MCD_OPC_Decode, + 140, + 25, + 153, + 2, // Opcode: VQSHLsuv4i32 + /* 18093 */ MCD_OPC_FilterValue, + 7, + 139, + 0, + 0, // Skip to: 18237 + /* 18098 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 18101 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 18199 + /* 18106 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 18109 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 18161 + /* 18114 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18117 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18139 + /* 18122 */ MCD_OPC_CheckPredicate, + 26, + 109, + 2, + 0, // Skip to: 18748 + /* 18127 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 102, + 2, + 0, // Skip to: 18748 + /* 18134 */ MCD_OPC_Decode, + 255, + 24, + 149, + 2, // Opcode: VQSHLsiv16i8 + /* 18139 */ MCD_OPC_FilterValue, + 1, + 92, + 2, + 0, // Skip to: 18748 + /* 18144 */ MCD_OPC_CheckPredicate, + 26, + 87, + 2, + 0, // Skip to: 18748 + /* 18149 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 80, + 2, + 0, // Skip to: 18748 + /* 18156 */ MCD_OPC_Decode, + 151, + 25, + 149, + 2, // Opcode: VQSHLuiv16i8 + /* 18161 */ MCD_OPC_FilterValue, + 1, + 70, + 2, + 0, // Skip to: 18748 + /* 18166 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18169 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18184 + /* 18174 */ MCD_OPC_CheckPredicate, + 26, + 57, + 2, + 0, // Skip to: 18748 + /* 18179 */ MCD_OPC_Decode, + 133, + 25, + 151, + 2, // Opcode: VQSHLsiv8i16 + /* 18184 */ MCD_OPC_FilterValue, + 1, + 47, + 2, + 0, // Skip to: 18748 + /* 18189 */ MCD_OPC_CheckPredicate, + 26, + 42, + 2, + 0, // Skip to: 18748 + /* 18194 */ MCD_OPC_Decode, + 157, + 25, + 151, + 2, // Opcode: VQSHLuiv8i16 + /* 18199 */ MCD_OPC_FilterValue, + 1, + 32, + 2, + 0, // Skip to: 18748 + /* 18204 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18207 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18222 + /* 18212 */ MCD_OPC_CheckPredicate, + 26, + 19, + 2, + 0, // Skip to: 18748 + /* 18217 */ MCD_OPC_Decode, + 132, + 25, + 153, + 2, // Opcode: VQSHLsiv4i32 + /* 18222 */ MCD_OPC_FilterValue, + 1, + 9, + 2, + 0, // Skip to: 18748 + /* 18227 */ MCD_OPC_CheckPredicate, + 26, + 4, + 2, + 0, // Skip to: 18748 + /* 18232 */ MCD_OPC_Decode, + 156, + 25, + 153, + 2, // Opcode: VQSHLuiv4i32 + /* 18237 */ MCD_OPC_FilterValue, + 8, + 139, + 0, + 0, // Skip to: 18381 + /* 18242 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 18245 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 18343 + /* 18250 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 18253 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 18305 + /* 18258 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18261 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18283 + /* 18266 */ MCD_OPC_CheckPredicate, + 26, + 221, + 1, + 0, // Skip to: 18748 + /* 18271 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 214, + 1, + 0, // Skip to: 18748 + /* 18278 */ MCD_OPC_Decode, + 164, + 26, + 131, + 2, // Opcode: VRSHRNv8i8 + /* 18283 */ MCD_OPC_FilterValue, + 1, + 204, + 1, + 0, // Skip to: 18748 + /* 18288 */ MCD_OPC_CheckPredicate, + 26, + 199, + 1, + 0, // Skip to: 18748 + /* 18293 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 192, + 1, + 0, // Skip to: 18748 + /* 18300 */ MCD_OPC_Decode, + 254, + 24, + 131, + 2, // Opcode: VQRSHRUNv8i8 + /* 18305 */ MCD_OPC_FilterValue, + 1, + 182, + 1, + 0, // Skip to: 18748 + /* 18310 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18313 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18328 + /* 18318 */ MCD_OPC_CheckPredicate, + 26, + 169, + 1, + 0, // Skip to: 18748 + /* 18323 */ MCD_OPC_Decode, + 163, + 26, + 132, + 2, // Opcode: VRSHRNv4i16 + /* 18328 */ MCD_OPC_FilterValue, + 1, + 159, + 1, + 0, // Skip to: 18748 + /* 18333 */ MCD_OPC_CheckPredicate, + 26, + 154, + 1, + 0, // Skip to: 18748 + /* 18338 */ MCD_OPC_Decode, + 253, + 24, + 132, + 2, // Opcode: VQRSHRUNv4i16 + /* 18343 */ MCD_OPC_FilterValue, + 1, + 144, + 1, + 0, // Skip to: 18748 + /* 18348 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18351 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18366 + /* 18356 */ MCD_OPC_CheckPredicate, + 26, + 131, + 1, + 0, // Skip to: 18748 + /* 18361 */ MCD_OPC_Decode, + 162, + 26, + 133, + 2, // Opcode: VRSHRNv2i32 + /* 18366 */ MCD_OPC_FilterValue, + 1, + 121, + 1, + 0, // Skip to: 18748 + /* 18371 */ MCD_OPC_CheckPredicate, + 26, + 116, + 1, + 0, // Skip to: 18748 + /* 18376 */ MCD_OPC_Decode, + 252, + 24, + 133, + 2, // Opcode: VQRSHRUNv2i32 + /* 18381 */ MCD_OPC_FilterValue, + 9, + 139, + 0, + 0, // Skip to: 18525 + /* 18386 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 18389 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 18487 + /* 18394 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 18397 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 18449 + /* 18402 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18405 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18427 + /* 18410 */ MCD_OPC_CheckPredicate, + 26, + 77, + 1, + 0, // Skip to: 18748 + /* 18415 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 70, + 1, + 0, // Skip to: 18748 + /* 18422 */ MCD_OPC_Decode, + 248, + 24, + 131, + 2, // Opcode: VQRSHRNsv8i8 + /* 18427 */ MCD_OPC_FilterValue, + 1, + 60, + 1, + 0, // Skip to: 18748 + /* 18432 */ MCD_OPC_CheckPredicate, + 26, + 55, + 1, + 0, // Skip to: 18748 + /* 18437 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 48, + 1, + 0, // Skip to: 18748 + /* 18444 */ MCD_OPC_Decode, + 251, + 24, + 131, + 2, // Opcode: VQRSHRNuv8i8 + /* 18449 */ MCD_OPC_FilterValue, + 1, + 38, + 1, + 0, // Skip to: 18748 + /* 18454 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18457 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18472 + /* 18462 */ MCD_OPC_CheckPredicate, + 26, + 25, + 1, + 0, // Skip to: 18748 + /* 18467 */ MCD_OPC_Decode, + 247, + 24, + 132, + 2, // Opcode: VQRSHRNsv4i16 + /* 18472 */ MCD_OPC_FilterValue, + 1, + 15, + 1, + 0, // Skip to: 18748 + /* 18477 */ MCD_OPC_CheckPredicate, + 26, + 10, + 1, + 0, // Skip to: 18748 + /* 18482 */ MCD_OPC_Decode, + 250, + 24, + 132, + 2, // Opcode: VQRSHRNuv4i16 + /* 18487 */ MCD_OPC_FilterValue, + 1, + 0, + 1, + 0, // Skip to: 18748 + /* 18492 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18495 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18510 + /* 18500 */ MCD_OPC_CheckPredicate, + 26, + 243, + 0, + 0, // Skip to: 18748 + /* 18505 */ MCD_OPC_Decode, + 246, + 24, + 133, + 2, // Opcode: VQRSHRNsv2i32 + /* 18510 */ MCD_OPC_FilterValue, + 1, + 233, + 0, + 0, // Skip to: 18748 + /* 18515 */ MCD_OPC_CheckPredicate, + 26, + 228, + 0, + 0, // Skip to: 18748 + /* 18520 */ MCD_OPC_Decode, + 249, + 24, + 133, + 2, // Opcode: VQRSHRNuv2i32 + /* 18525 */ MCD_OPC_FilterValue, + 12, + 33, + 0, + 0, // Skip to: 18563 + /* 18530 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18533 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18548 + /* 18538 */ MCD_OPC_CheckPredicate, + 27, + 205, + 0, + 0, // Skip to: 18748 + /* 18543 */ MCD_OPC_Decode, + 169, + 18, + 155, + 2, // Opcode: VCVTxs2hq + /* 18548 */ MCD_OPC_FilterValue, + 1, + 195, + 0, + 0, // Skip to: 18748 + /* 18553 */ MCD_OPC_CheckPredicate, + 27, + 190, + 0, + 0, // Skip to: 18748 + /* 18558 */ MCD_OPC_Decode, + 173, + 18, + 155, + 2, // Opcode: VCVTxu2hq + /* 18563 */ MCD_OPC_FilterValue, + 13, + 33, + 0, + 0, // Skip to: 18601 + /* 18568 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18571 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18586 + /* 18576 */ MCD_OPC_CheckPredicate, + 27, + 167, + 0, + 0, // Skip to: 18748 + /* 18581 */ MCD_OPC_Decode, + 155, + 18, + 155, + 2, // Opcode: VCVTh2xsq + /* 18586 */ MCD_OPC_FilterValue, + 1, + 157, + 0, + 0, // Skip to: 18748 + /* 18591 */ MCD_OPC_CheckPredicate, + 27, + 152, + 0, + 0, // Skip to: 18748 + /* 18596 */ MCD_OPC_Decode, + 157, + 18, + 155, + 2, // Opcode: VCVTh2xuq + /* 18601 */ MCD_OPC_FilterValue, + 14, + 80, + 0, + 0, // Skip to: 18686 + /* 18606 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 18609 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18631 + /* 18614 */ MCD_OPC_CheckPredicate, + 26, + 34, + 0, + 0, // Skip to: 18653 + /* 18619 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 27, + 0, + 0, // Skip to: 18653 + /* 18626 */ MCD_OPC_Decode, + 128, + 23, + 138, + 2, // Opcode: VMOVv16i8 + /* 18631 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 18653 + /* 18636 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 18653 + /* 18641 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 5, + 0, + 0, // Skip to: 18653 + /* 18648 */ MCD_OPC_Decode, + 132, + 23, + 138, + 2, // Opcode: VMOVv2i64 + /* 18653 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18656 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18671 + /* 18661 */ MCD_OPC_CheckPredicate, + 26, + 82, + 0, + 0, // Skip to: 18748 + /* 18666 */ MCD_OPC_Decode, + 167, + 18, + 155, + 2, // Opcode: VCVTxs2fq + /* 18671 */ MCD_OPC_FilterValue, + 1, + 72, + 0, + 0, // Skip to: 18748 + /* 18676 */ MCD_OPC_CheckPredicate, + 26, + 67, + 0, + 0, // Skip to: 18748 + /* 18681 */ MCD_OPC_Decode, + 171, + 18, + 155, + 2, // Opcode: VCVTxu2fq + /* 18686 */ MCD_OPC_FilterValue, + 15, + 57, + 0, + 0, // Skip to: 18748 + /* 18691 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18694 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18709 + /* 18699 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 18724 + /* 18704 */ MCD_OPC_Decode, + 146, + 18, + 155, + 2, // Opcode: VCVTf2xsq + /* 18709 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 18724 + /* 18714 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 18724 + /* 18719 */ MCD_OPC_Decode, + 148, + 18, + 155, + 2, // Opcode: VCVTf2xuq + /* 18724 */ MCD_OPC_CheckPredicate, + 26, + 19, + 0, + 0, // Skip to: 18748 + /* 18729 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 12, + 0, + 0, // Skip to: 18748 + /* 18736 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 5, + 0, + 0, // Skip to: 18748 + /* 18743 */ MCD_OPC_Decode, + 133, + 23, + 138, + 2, // Opcode: VMOVv4f32 + /* 18748 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 18751 */ MCD_OPC_FilterValue, + 0, + 88, + 0, + 0, // Skip to: 18844 + /* 18756 */ MCD_OPC_ExtractField, + 19, + 3, // Inst{21-19} ... + /* 18759 */ MCD_OPC_FilterValue, + 0, + 211, + 1, + 0, // Skip to: 19231 + /* 18764 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 18767 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18789 + /* 18772 */ MCD_OPC_CheckPredicate, + 26, + 57, + 0, + 0, // Skip to: 18834 + /* 18777 */ MCD_OPC_CheckField, + 10, + 2, + 2, + 50, + 0, + 0, // Skip to: 18834 + /* 18784 */ MCD_OPC_Decode, + 136, + 23, + 138, + 2, // Opcode: VMOVv8i16 + /* 18789 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 18834 + /* 18794 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 18797 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18812 + /* 18802 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 18834 + /* 18807 */ MCD_OPC_Decode, + 229, + 23, + 138, + 2, // Opcode: VORRiv4i32 + /* 18812 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 18834 + /* 18817 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 18834 + /* 18822 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 5, + 0, + 0, // Skip to: 18834 + /* 18829 */ MCD_OPC_Decode, + 230, + 23, + 138, + 2, // Opcode: VORRiv8i16 + /* 18834 */ MCD_OPC_CheckPredicate, + 26, + 136, + 1, + 0, // Skip to: 19231 + /* 18839 */ MCD_OPC_Decode, + 135, + 23, + 138, + 2, // Opcode: VMOVv4i32 + /* 18844 */ MCD_OPC_FilterValue, + 1, + 126, + 1, + 0, // Skip to: 19231 + /* 18849 */ MCD_OPC_ExtractField, + 19, + 3, // Inst{21-19} ... + /* 18852 */ MCD_OPC_FilterValue, + 0, + 118, + 1, + 0, // Skip to: 19231 + /* 18857 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 18860 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18882 + /* 18865 */ MCD_OPC_CheckPredicate, + 26, + 57, + 0, + 0, // Skip to: 18927 + /* 18870 */ MCD_OPC_CheckField, + 10, + 2, + 2, + 50, + 0, + 0, // Skip to: 18927 + /* 18877 */ MCD_OPC_Decode, + 201, + 23, + 138, + 2, // Opcode: VMVNv8i16 + /* 18882 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 18927 + /* 18887 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 18890 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18905 + /* 18895 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 18927 + /* 18900 */ MCD_OPC_Decode, + 189, + 16, + 138, + 2, // Opcode: VBICiv4i32 + /* 18905 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 18927 + /* 18910 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 18927 + /* 18915 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 5, + 0, + 0, // Skip to: 18927 + /* 18922 */ MCD_OPC_Decode, + 190, + 16, + 138, + 2, // Opcode: VBICiv8i16 + /* 18927 */ MCD_OPC_CheckPredicate, + 26, + 43, + 1, + 0, // Skip to: 19231 + /* 18932 */ MCD_OPC_Decode, + 200, + 23, + 138, + 2, // Opcode: VMVNv4i32 + /* 18937 */ MCD_OPC_FilterValue, + 1, + 33, + 1, + 0, // Skip to: 19231 + /* 18942 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 18945 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 18985 + /* 18950 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 18953 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 18969 + /* 18959 */ MCD_OPC_CheckPredicate, + 26, + 11, + 1, + 0, // Skip to: 19231 + /* 18964 */ MCD_OPC_Decode, + 142, + 27, + 156, + 2, // Opcode: VSHRsv2i64 + /* 18969 */ MCD_OPC_FilterValue, + 243, + 1, + 0, + 1, + 0, // Skip to: 19231 + /* 18975 */ MCD_OPC_CheckPredicate, + 26, + 251, + 0, + 0, // Skip to: 19231 + /* 18980 */ MCD_OPC_Decode, + 150, + 27, + 156, + 2, // Opcode: VSHRuv2i64 + /* 18985 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 19025 + /* 18990 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 18993 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 19009 + /* 18999 */ MCD_OPC_CheckPredicate, + 26, + 227, + 0, + 0, // Skip to: 19231 + /* 19004 */ MCD_OPC_Decode, + 179, + 27, + 157, + 2, // Opcode: VSRAsv2i64 + /* 19009 */ MCD_OPC_FilterValue, + 243, + 1, + 216, + 0, + 0, // Skip to: 19231 + /* 19015 */ MCD_OPC_CheckPredicate, + 26, + 211, + 0, + 0, // Skip to: 19231 + /* 19020 */ MCD_OPC_Decode, + 187, + 27, + 157, + 2, // Opcode: VSRAuv2i64 + /* 19025 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 19065 + /* 19030 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 19033 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 19049 + /* 19039 */ MCD_OPC_CheckPredicate, + 26, + 187, + 0, + 0, // Skip to: 19231 + /* 19044 */ MCD_OPC_Decode, + 168, + 26, + 156, + 2, // Opcode: VRSHRsv2i64 + /* 19049 */ MCD_OPC_FilterValue, + 243, + 1, + 176, + 0, + 0, // Skip to: 19231 + /* 19055 */ MCD_OPC_CheckPredicate, + 26, + 171, + 0, + 0, // Skip to: 19231 + /* 19060 */ MCD_OPC_Decode, + 176, + 26, + 156, + 2, // Opcode: VRSHRuv2i64 + /* 19065 */ MCD_OPC_FilterValue, + 3, + 35, + 0, + 0, // Skip to: 19105 + /* 19070 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 19073 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 19089 + /* 19079 */ MCD_OPC_CheckPredicate, + 26, + 147, + 0, + 0, // Skip to: 19231 + /* 19084 */ MCD_OPC_Decode, + 194, + 26, + 157, + 2, // Opcode: VRSRAsv2i64 + /* 19089 */ MCD_OPC_FilterValue, + 243, + 1, + 136, + 0, + 0, // Skip to: 19231 + /* 19095 */ MCD_OPC_CheckPredicate, + 26, + 131, + 0, + 0, // Skip to: 19231 + /* 19100 */ MCD_OPC_Decode, + 202, + 26, + 157, + 2, // Opcode: VRSRAuv2i64 + /* 19105 */ MCD_OPC_FilterValue, + 4, + 18, + 0, + 0, // Skip to: 19128 + /* 19110 */ MCD_OPC_CheckPredicate, + 26, + 116, + 0, + 0, // Skip to: 19231 + /* 19115 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 108, + 0, + 0, // Skip to: 19231 + /* 19123 */ MCD_OPC_Decode, + 195, + 27, + 157, + 2, // Opcode: VSRIv2i64 + /* 19128 */ MCD_OPC_FilterValue, + 5, + 35, + 0, + 0, // Skip to: 19168 + /* 19133 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 19136 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 19152 + /* 19142 */ MCD_OPC_CheckPredicate, + 26, + 84, + 0, + 0, // Skip to: 19231 + /* 19147 */ MCD_OPC_Decode, + 243, + 26, + 158, + 2, // Opcode: VSHLiv2i64 + /* 19152 */ MCD_OPC_FilterValue, + 243, + 1, + 73, + 0, + 0, // Skip to: 19231 + /* 19158 */ MCD_OPC_CheckPredicate, + 26, + 68, + 0, + 0, // Skip to: 19231 + /* 19163 */ MCD_OPC_Decode, + 164, + 27, + 159, + 2, // Opcode: VSLIv2i64 + /* 19168 */ MCD_OPC_FilterValue, + 6, + 18, + 0, + 0, // Skip to: 19191 + /* 19173 */ MCD_OPC_CheckPredicate, + 26, + 53, + 0, + 0, // Skip to: 19231 + /* 19178 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 45, + 0, + 0, // Skip to: 19231 + /* 19186 */ MCD_OPC_Decode, + 138, + 25, + 158, + 2, // Opcode: VQSHLsuv2i64 + /* 19191 */ MCD_OPC_FilterValue, + 7, + 35, + 0, + 0, // Skip to: 19231 + /* 19196 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 19199 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 19215 + /* 19205 */ MCD_OPC_CheckPredicate, + 26, + 21, + 0, + 0, // Skip to: 19231 + /* 19210 */ MCD_OPC_Decode, + 130, + 25, + 158, + 2, // Opcode: VQSHLsiv2i64 + /* 19215 */ MCD_OPC_FilterValue, + 243, + 1, + 10, + 0, + 0, // Skip to: 19231 + /* 19221 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 19231 + /* 19226 */ MCD_OPC_Decode, + 154, + 25, + 158, + 2, // Opcode: VQSHLuiv2i64 + /* 19231 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNEONDup32[] = { + /* 0 */ MCD_OPC_ExtractField, + 22, + 6, // Inst{27-22} ... + /* 3 */ MCD_OPC_FilterValue, + 56, + 121, + 0, + 0, // Skip to: 129 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 16, + 61, + 0, + 0, // Skip to: 77 + /* 16 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 48 + /* 24 */ MCD_OPC_CheckPredicate, + 33, + 183, + 1, + 0, // Skip to: 468 + /* 29 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 176, + 1, + 0, // Skip to: 468 + /* 36 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 169, + 1, + 0, // Skip to: 468 + /* 43 */ MCD_OPC_Decode, + 229, + 26, + 160, + 2, // Opcode: VSETLNi32 + /* 48 */ MCD_OPC_FilterValue, + 1, + 159, + 1, + 0, // Skip to: 468 + /* 53 */ MCD_OPC_CheckPredicate, + 34, + 154, + 1, + 0, // Skip to: 468 + /* 58 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 147, + 1, + 0, // Skip to: 468 + /* 65 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 140, + 1, + 0, // Skip to: 468 + /* 72 */ MCD_OPC_Decode, + 232, + 18, + 161, + 2, // Opcode: VGETLNi32 + /* 77 */ MCD_OPC_FilterValue, + 48, + 130, + 1, + 0, // Skip to: 468 + /* 82 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 85 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 107 + /* 90 */ MCD_OPC_CheckPredicate, + 26, + 117, + 1, + 0, // Skip to: 468 + /* 95 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 110, + 1, + 0, // Skip to: 468 + /* 102 */ MCD_OPC_Decode, + 228, + 26, + 162, + 2, // Opcode: VSETLNi16 + /* 107 */ MCD_OPC_FilterValue, + 1, + 100, + 1, + 0, // Skip to: 468 + /* 112 */ MCD_OPC_CheckPredicate, + 26, + 95, + 1, + 0, // Skip to: 468 + /* 117 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 88, + 1, + 0, // Skip to: 468 + /* 124 */ MCD_OPC_Decode, + 233, + 18, + 163, + 2, // Opcode: VGETLNs16 + /* 129 */ MCD_OPC_FilterValue, + 57, + 61, + 0, + 0, // Skip to: 195 + /* 134 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 137 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 166 + /* 142 */ MCD_OPC_CheckPredicate, + 26, + 65, + 1, + 0, // Skip to: 468 + /* 147 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 58, + 1, + 0, // Skip to: 468 + /* 154 */ MCD_OPC_CheckField, + 0, + 5, + 16, + 51, + 1, + 0, // Skip to: 468 + /* 161 */ MCD_OPC_Decode, + 230, + 26, + 164, + 2, // Opcode: VSETLNi8 + /* 166 */ MCD_OPC_FilterValue, + 1, + 41, + 1, + 0, // Skip to: 468 + /* 171 */ MCD_OPC_CheckPredicate, + 26, + 36, + 1, + 0, // Skip to: 468 + /* 176 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 29, + 1, + 0, // Skip to: 468 + /* 183 */ MCD_OPC_CheckField, + 0, + 5, + 16, + 22, + 1, + 0, // Skip to: 468 + /* 190 */ MCD_OPC_Decode, + 234, + 18, + 165, + 2, // Opcode: VGETLNs8 + /* 195 */ MCD_OPC_FilterValue, + 58, + 165, + 0, + 0, // Skip to: 365 + /* 200 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 203 */ MCD_OPC_FilterValue, + 16, + 61, + 0, + 0, // Skip to: 269 + /* 208 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 211 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 240 + /* 216 */ MCD_OPC_CheckPredicate, + 26, + 247, + 0, + 0, // Skip to: 468 + /* 221 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 240, + 0, + 0, // Skip to: 468 + /* 228 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 233, + 0, + 0, // Skip to: 468 + /* 235 */ MCD_OPC_Decode, + 179, + 18, + 166, + 2, // Opcode: VDUP32d + /* 240 */ MCD_OPC_FilterValue, + 2, + 223, + 0, + 0, // Skip to: 468 + /* 245 */ MCD_OPC_CheckPredicate, + 26, + 218, + 0, + 0, // Skip to: 468 + /* 250 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 211, + 0, + 0, // Skip to: 468 + /* 257 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 204, + 0, + 0, // Skip to: 468 + /* 264 */ MCD_OPC_Decode, + 180, + 18, + 167, + 2, // Opcode: VDUP32q + /* 269 */ MCD_OPC_FilterValue, + 48, + 194, + 0, + 0, // Skip to: 468 + /* 274 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 277 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 343 + /* 282 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 285 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 314 + /* 290 */ MCD_OPC_CheckPredicate, + 26, + 173, + 0, + 0, // Skip to: 468 + /* 295 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 166, + 0, + 0, // Skip to: 468 + /* 302 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 159, + 0, + 0, // Skip to: 468 + /* 309 */ MCD_OPC_Decode, + 177, + 18, + 166, + 2, // Opcode: VDUP16d + /* 314 */ MCD_OPC_FilterValue, + 1, + 149, + 0, + 0, // Skip to: 468 + /* 319 */ MCD_OPC_CheckPredicate, + 26, + 144, + 0, + 0, // Skip to: 468 + /* 324 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 137, + 0, + 0, // Skip to: 468 + /* 331 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 130, + 0, + 0, // Skip to: 468 + /* 338 */ MCD_OPC_Decode, + 178, + 18, + 167, + 2, // Opcode: VDUP16q + /* 343 */ MCD_OPC_FilterValue, + 1, + 120, + 0, + 0, // Skip to: 468 + /* 348 */ MCD_OPC_CheckPredicate, + 26, + 115, + 0, + 0, // Skip to: 468 + /* 353 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 108, + 0, + 0, // Skip to: 468 + /* 360 */ MCD_OPC_Decode, + 235, + 18, + 163, + 2, // Opcode: VGETLNu16 + /* 365 */ MCD_OPC_FilterValue, + 59, + 98, + 0, + 0, // Skip to: 468 + /* 370 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 373 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 439 + /* 378 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 381 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 410 + /* 386 */ MCD_OPC_CheckPredicate, + 26, + 77, + 0, + 0, // Skip to: 468 + /* 391 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 70, + 0, + 0, // Skip to: 468 + /* 398 */ MCD_OPC_CheckField, + 0, + 7, + 16, + 63, + 0, + 0, // Skip to: 468 + /* 405 */ MCD_OPC_Decode, + 181, + 18, + 166, + 2, // Opcode: VDUP8d + /* 410 */ MCD_OPC_FilterValue, + 1, + 53, + 0, + 0, // Skip to: 468 + /* 415 */ MCD_OPC_CheckPredicate, + 26, + 48, + 0, + 0, // Skip to: 468 + /* 420 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 41, + 0, + 0, // Skip to: 468 + /* 427 */ MCD_OPC_CheckField, + 0, + 7, + 16, + 34, + 0, + 0, // Skip to: 468 + /* 434 */ MCD_OPC_Decode, + 182, + 18, + 167, + 2, // Opcode: VDUP8q + /* 439 */ MCD_OPC_FilterValue, + 1, + 24, + 0, + 0, // Skip to: 468 + /* 444 */ MCD_OPC_CheckPredicate, + 26, + 19, + 0, + 0, // Skip to: 468 + /* 449 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 12, + 0, + 0, // Skip to: 468 + /* 456 */ MCD_OPC_CheckField, + 0, + 5, + 16, + 5, + 0, + 0, // Skip to: 468 + /* 463 */ MCD_OPC_Decode, + 236, + 18, + 165, + 2, // Opcode: VGETLNu8 + /* 468 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNEONLoadStore32[] = { + /* 0 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 55, + 1, + 0, // Skip to: 319 + /* 8 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 149, + 0, + 0, // Skip to: 165 + /* 16 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 19 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 124 + /* 25 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 28 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 60 + /* 33 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 50 + /* 38 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 50 + /* 45 */ MCD_OPC_Decode, + 183, + 29, + 168, + 2, // Opcode: VST4d8 + /* 50 */ MCD_OPC_CheckPredicate, + 26, + 246, + 25, + 0, // Skip to: 6701 + /* 55 */ MCD_OPC_Decode, + 186, + 29, + 168, + 2, // Opcode: VST4d8_UPD + /* 60 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 92 + /* 65 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 82 + /* 70 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 82 + /* 77 */ MCD_OPC_Decode, + 175, + 29, + 168, + 2, // Opcode: VST4d16 + /* 82 */ MCD_OPC_CheckPredicate, + 26, + 214, + 25, + 0, // Skip to: 6701 + /* 87 */ MCD_OPC_Decode, + 178, + 29, + 168, + 2, // Opcode: VST4d16_UPD + /* 92 */ MCD_OPC_FilterValue, + 2, + 204, + 25, + 0, // Skip to: 6701 + /* 97 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 114 + /* 102 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 114 + /* 109 */ MCD_OPC_Decode, + 179, + 29, + 168, + 2, // Opcode: VST4d32 + /* 114 */ MCD_OPC_CheckPredicate, + 26, + 182, + 25, + 0, // Skip to: 6701 + /* 119 */ MCD_OPC_Decode, + 182, + 29, + 168, + 2, // Opcode: VST4d32_UPD + /* 124 */ MCD_OPC_FilterValue, + 233, + 3, + 171, + 25, + 0, // Skip to: 6701 + /* 130 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 133 */ MCD_OPC_FilterValue, + 0, + 163, + 25, + 0, // Skip to: 6701 + /* 138 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 155 + /* 143 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 155 + /* 150 */ MCD_OPC_Decode, + 204, + 27, + 169, + 2, // Opcode: VST1LNd8 + /* 155 */ MCD_OPC_CheckPredicate, + 26, + 141, + 25, + 0, // Skip to: 6701 + /* 160 */ MCD_OPC_Decode, + 205, + 27, + 169, + 2, // Opcode: VST1LNd8_UPD + /* 165 */ MCD_OPC_FilterValue, + 2, + 131, + 25, + 0, // Skip to: 6701 + /* 170 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 173 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 278 + /* 179 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 182 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 214 + /* 187 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 204 + /* 192 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 204 + /* 199 */ MCD_OPC_Decode, + 220, + 21, + 168, + 2, // Opcode: VLD4d8 + /* 204 */ MCD_OPC_CheckPredicate, + 26, + 92, + 25, + 0, // Skip to: 6701 + /* 209 */ MCD_OPC_Decode, + 223, + 21, + 168, + 2, // Opcode: VLD4d8_UPD + /* 214 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 246 + /* 219 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 236 + /* 224 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 236 + /* 231 */ MCD_OPC_Decode, + 212, + 21, + 168, + 2, // Opcode: VLD4d16 + /* 236 */ MCD_OPC_CheckPredicate, + 26, + 60, + 25, + 0, // Skip to: 6701 + /* 241 */ MCD_OPC_Decode, + 215, + 21, + 168, + 2, // Opcode: VLD4d16_UPD + /* 246 */ MCD_OPC_FilterValue, + 2, + 50, + 25, + 0, // Skip to: 6701 + /* 251 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 268 + /* 256 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 268 + /* 263 */ MCD_OPC_Decode, + 216, + 21, + 168, + 2, // Opcode: VLD4d32 + /* 268 */ MCD_OPC_CheckPredicate, + 26, + 28, + 25, + 0, // Skip to: 6701 + /* 273 */ MCD_OPC_Decode, + 219, + 21, + 168, + 2, // Opcode: VLD4d32_UPD + /* 278 */ MCD_OPC_FilterValue, + 233, + 3, + 17, + 25, + 0, // Skip to: 6701 + /* 284 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 287 */ MCD_OPC_FilterValue, + 0, + 9, + 25, + 0, // Skip to: 6701 + /* 292 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 309 + /* 297 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 309 + /* 304 */ MCD_OPC_Decode, + 157, + 19, + 170, + 2, // Opcode: VLD1LNd8 + /* 309 */ MCD_OPC_CheckPredicate, + 26, + 243, + 24, + 0, // Skip to: 6701 + /* 314 */ MCD_OPC_Decode, + 158, + 19, + 170, + 2, // Opcode: VLD1LNd8_UPD + /* 319 */ MCD_OPC_FilterValue, + 1, + 39, + 1, + 0, // Skip to: 619 + /* 324 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 327 */ MCD_OPC_FilterValue, + 0, + 141, + 0, + 0, // Skip to: 473 + /* 332 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 335 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 440 + /* 341 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 344 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 376 + /* 349 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 366 + /* 354 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 366 + /* 361 */ MCD_OPC_Decode, + 197, + 29, + 168, + 2, // Opcode: VST4q8 + /* 366 */ MCD_OPC_CheckPredicate, + 26, + 186, + 24, + 0, // Skip to: 6701 + /* 371 */ MCD_OPC_Decode, + 199, + 29, + 168, + 2, // Opcode: VST4q8_UPD + /* 376 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 408 + /* 381 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 398 + /* 386 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 398 + /* 393 */ MCD_OPC_Decode, + 187, + 29, + 168, + 2, // Opcode: VST4q16 + /* 398 */ MCD_OPC_CheckPredicate, + 26, + 154, + 24, + 0, // Skip to: 6701 + /* 403 */ MCD_OPC_Decode, + 189, + 29, + 168, + 2, // Opcode: VST4q16_UPD + /* 408 */ MCD_OPC_FilterValue, + 2, + 144, + 24, + 0, // Skip to: 6701 + /* 413 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 430 + /* 418 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 430 + /* 425 */ MCD_OPC_Decode, + 192, + 29, + 168, + 2, // Opcode: VST4q32 + /* 430 */ MCD_OPC_CheckPredicate, + 26, + 122, + 24, + 0, // Skip to: 6701 + /* 435 */ MCD_OPC_Decode, + 194, + 29, + 168, + 2, // Opcode: VST4q32_UPD + /* 440 */ MCD_OPC_FilterValue, + 233, + 3, + 111, + 24, + 0, // Skip to: 6701 + /* 446 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 463 + /* 451 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 463 + /* 458 */ MCD_OPC_Decode, + 188, + 28, + 171, + 2, // Opcode: VST2LNd8 + /* 463 */ MCD_OPC_CheckPredicate, + 26, + 89, + 24, + 0, // Skip to: 6701 + /* 468 */ MCD_OPC_Decode, + 191, + 28, + 171, + 2, // Opcode: VST2LNd8_UPD + /* 473 */ MCD_OPC_FilterValue, + 2, + 79, + 24, + 0, // Skip to: 6701 + /* 478 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 481 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 586 + /* 487 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 490 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 522 + /* 495 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 512 + /* 500 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 512 + /* 507 */ MCD_OPC_Decode, + 234, + 21, + 168, + 2, // Opcode: VLD4q8 + /* 512 */ MCD_OPC_CheckPredicate, + 26, + 40, + 24, + 0, // Skip to: 6701 + /* 517 */ MCD_OPC_Decode, + 236, + 21, + 168, + 2, // Opcode: VLD4q8_UPD + /* 522 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 554 + /* 527 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 544 + /* 532 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 544 + /* 539 */ MCD_OPC_Decode, + 224, + 21, + 168, + 2, // Opcode: VLD4q16 + /* 544 */ MCD_OPC_CheckPredicate, + 26, + 8, + 24, + 0, // Skip to: 6701 + /* 549 */ MCD_OPC_Decode, + 226, + 21, + 168, + 2, // Opcode: VLD4q16_UPD + /* 554 */ MCD_OPC_FilterValue, + 2, + 254, + 23, + 0, // Skip to: 6701 + /* 559 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 576 + /* 564 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 576 + /* 571 */ MCD_OPC_Decode, + 229, + 21, + 168, + 2, // Opcode: VLD4q32 + /* 576 */ MCD_OPC_CheckPredicate, + 26, + 232, + 23, + 0, // Skip to: 6701 + /* 581 */ MCD_OPC_Decode, + 231, + 21, + 168, + 2, // Opcode: VLD4q32_UPD + /* 586 */ MCD_OPC_FilterValue, + 233, + 3, + 221, + 23, + 0, // Skip to: 6701 + /* 592 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 609 + /* 597 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 609 + /* 604 */ MCD_OPC_Decode, + 171, + 20, + 172, + 2, // Opcode: VLD2LNd8 + /* 609 */ MCD_OPC_CheckPredicate, + 26, + 199, + 23, + 0, // Skip to: 6701 + /* 614 */ MCD_OPC_Decode, + 174, + 20, + 172, + 2, // Opcode: VLD2LNd8_UPD + /* 619 */ MCD_OPC_FilterValue, + 2, + 247, + 1, + 0, // Skip to: 1127 + /* 624 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 627 */ MCD_OPC_FilterValue, + 0, + 245, + 0, + 0, // Skip to: 877 + /* 632 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 635 */ MCD_OPC_FilterValue, + 232, + 3, + 195, + 0, + 0, // Skip to: 836 + /* 641 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 644 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 692 + /* 649 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 652 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 667 + /* 657 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 682 + /* 662 */ MCD_OPC_Decode, + 134, + 28, + 173, + 2, // Opcode: VST1d8Qwb_fixed + /* 667 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 682 + /* 672 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 682 + /* 677 */ MCD_OPC_Decode, + 130, + 28, + 173, + 2, // Opcode: VST1d8Q + /* 682 */ MCD_OPC_CheckPredicate, + 26, + 126, + 23, + 0, // Skip to: 6701 + /* 687 */ MCD_OPC_Decode, + 135, + 28, + 173, + 2, // Opcode: VST1d8Qwb_register + /* 692 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 740 + /* 697 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 700 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 715 + /* 705 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 730 + /* 710 */ MCD_OPC_Decode, + 217, + 27, + 173, + 2, // Opcode: VST1d16Qwb_fixed + /* 715 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 730 + /* 720 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 730 + /* 725 */ MCD_OPC_Decode, + 213, + 27, + 173, + 2, // Opcode: VST1d16Q + /* 730 */ MCD_OPC_CheckPredicate, + 26, + 78, + 23, + 0, // Skip to: 6701 + /* 735 */ MCD_OPC_Decode, + 218, + 27, + 173, + 2, // Opcode: VST1d16Qwb_register + /* 740 */ MCD_OPC_FilterValue, + 2, + 43, + 0, + 0, // Skip to: 788 + /* 745 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 748 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 763 + /* 753 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 778 + /* 758 */ MCD_OPC_Decode, + 232, + 27, + 173, + 2, // Opcode: VST1d32Qwb_fixed + /* 763 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 778 + /* 768 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 778 + /* 773 */ MCD_OPC_Decode, + 228, + 27, + 173, + 2, // Opcode: VST1d32Q + /* 778 */ MCD_OPC_CheckPredicate, + 26, + 30, + 23, + 0, // Skip to: 6701 + /* 783 */ MCD_OPC_Decode, + 233, + 27, + 173, + 2, // Opcode: VST1d32Qwb_register + /* 788 */ MCD_OPC_FilterValue, + 3, + 20, + 23, + 0, // Skip to: 6701 + /* 793 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 796 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 811 + /* 801 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 826 + /* 806 */ MCD_OPC_Decode, + 247, + 27, + 173, + 2, // Opcode: VST1d64Qwb_fixed + /* 811 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 826 + /* 816 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 826 + /* 821 */ MCD_OPC_Decode, + 243, + 27, + 173, + 2, // Opcode: VST1d64Q + /* 826 */ MCD_OPC_CheckPredicate, + 26, + 238, + 22, + 0, // Skip to: 6701 + /* 831 */ MCD_OPC_Decode, + 248, + 27, + 173, + 2, // Opcode: VST1d64Qwb_register + /* 836 */ MCD_OPC_FilterValue, + 233, + 3, + 227, + 22, + 0, // Skip to: 6701 + /* 842 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 845 */ MCD_OPC_FilterValue, + 0, + 219, + 22, + 0, // Skip to: 6701 + /* 850 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 867 + /* 855 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 867 + /* 862 */ MCD_OPC_Decode, + 244, + 28, + 174, + 2, // Opcode: VST3LNd8 + /* 867 */ MCD_OPC_CheckPredicate, + 26, + 197, + 22, + 0, // Skip to: 6701 + /* 872 */ MCD_OPC_Decode, + 247, + 28, + 174, + 2, // Opcode: VST3LNd8_UPD + /* 877 */ MCD_OPC_FilterValue, + 2, + 187, + 22, + 0, // Skip to: 6701 + /* 882 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 885 */ MCD_OPC_FilterValue, + 232, + 3, + 195, + 0, + 0, // Skip to: 1086 + /* 891 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 894 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 942 + /* 899 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 902 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 917 + /* 907 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 932 + /* 912 */ MCD_OPC_Decode, + 215, + 19, + 173, + 2, // Opcode: VLD1d8Qwb_fixed + /* 917 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 932 + /* 922 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 932 + /* 927 */ MCD_OPC_Decode, + 211, + 19, + 173, + 2, // Opcode: VLD1d8Q + /* 932 */ MCD_OPC_CheckPredicate, + 26, + 132, + 22, + 0, // Skip to: 6701 + /* 937 */ MCD_OPC_Decode, + 216, + 19, + 173, + 2, // Opcode: VLD1d8Qwb_register + /* 942 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 990 + /* 947 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 950 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 965 + /* 955 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 980 + /* 960 */ MCD_OPC_Decode, + 170, + 19, + 173, + 2, // Opcode: VLD1d16Qwb_fixed + /* 965 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 980 + /* 970 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 980 + /* 975 */ MCD_OPC_Decode, + 166, + 19, + 173, + 2, // Opcode: VLD1d16Q + /* 980 */ MCD_OPC_CheckPredicate, + 26, + 84, + 22, + 0, // Skip to: 6701 + /* 985 */ MCD_OPC_Decode, + 171, + 19, + 173, + 2, // Opcode: VLD1d16Qwb_register + /* 990 */ MCD_OPC_FilterValue, + 2, + 43, + 0, + 0, // Skip to: 1038 + /* 995 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 998 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1013 + /* 1003 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1028 + /* 1008 */ MCD_OPC_Decode, + 185, + 19, + 173, + 2, // Opcode: VLD1d32Qwb_fixed + /* 1013 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1028 + /* 1018 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1028 + /* 1023 */ MCD_OPC_Decode, + 181, + 19, + 173, + 2, // Opcode: VLD1d32Q + /* 1028 */ MCD_OPC_CheckPredicate, + 26, + 36, + 22, + 0, // Skip to: 6701 + /* 1033 */ MCD_OPC_Decode, + 186, + 19, + 173, + 2, // Opcode: VLD1d32Qwb_register + /* 1038 */ MCD_OPC_FilterValue, + 3, + 26, + 22, + 0, // Skip to: 6701 + /* 1043 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1046 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1061 + /* 1051 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1076 + /* 1056 */ MCD_OPC_Decode, + 200, + 19, + 173, + 2, // Opcode: VLD1d64Qwb_fixed + /* 1061 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1076 + /* 1066 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1076 + /* 1071 */ MCD_OPC_Decode, + 196, + 19, + 173, + 2, // Opcode: VLD1d64Q + /* 1076 */ MCD_OPC_CheckPredicate, + 26, + 244, + 21, + 0, // Skip to: 6701 + /* 1081 */ MCD_OPC_Decode, + 201, + 19, + 173, + 2, // Opcode: VLD1d64Qwb_register + /* 1086 */ MCD_OPC_FilterValue, + 233, + 3, + 233, + 21, + 0, // Skip to: 6701 + /* 1092 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1095 */ MCD_OPC_FilterValue, + 0, + 225, + 21, + 0, // Skip to: 6701 + /* 1100 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1117 + /* 1105 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1117 + /* 1112 */ MCD_OPC_Decode, + 254, + 20, + 175, + 2, // Opcode: VLD3LNd8 + /* 1117 */ MCD_OPC_CheckPredicate, + 26, + 203, + 21, + 0, // Skip to: 6701 + /* 1122 */ MCD_OPC_Decode, + 129, + 21, + 175, + 2, // Opcode: VLD3LNd8_UPD + /* 1127 */ MCD_OPC_FilterValue, + 3, + 135, + 1, + 0, // Skip to: 1523 + /* 1132 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1135 */ MCD_OPC_FilterValue, + 0, + 189, + 0, + 0, // Skip to: 1329 + /* 1140 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1143 */ MCD_OPC_FilterValue, + 232, + 3, + 147, + 0, + 0, // Skip to: 1296 + /* 1149 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1152 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 1200 + /* 1157 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1160 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1175 + /* 1165 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1190 + /* 1170 */ MCD_OPC_Decode, + 234, + 28, + 176, + 2, // Opcode: VST2q8wb_fixed + /* 1175 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1190 + /* 1180 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1190 + /* 1185 */ MCD_OPC_Decode, + 230, + 28, + 176, + 2, // Opcode: VST2q8 + /* 1190 */ MCD_OPC_CheckPredicate, + 26, + 130, + 21, + 0, // Skip to: 6701 + /* 1195 */ MCD_OPC_Decode, + 235, + 28, + 176, + 2, // Opcode: VST2q8wb_register + /* 1200 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 1248 + /* 1205 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1208 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1223 + /* 1213 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1238 + /* 1218 */ MCD_OPC_Decode, + 222, + 28, + 176, + 2, // Opcode: VST2q16wb_fixed + /* 1223 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1238 + /* 1228 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1238 + /* 1233 */ MCD_OPC_Decode, + 218, + 28, + 176, + 2, // Opcode: VST2q16 + /* 1238 */ MCD_OPC_CheckPredicate, + 26, + 82, + 21, + 0, // Skip to: 6701 + /* 1243 */ MCD_OPC_Decode, + 223, + 28, + 176, + 2, // Opcode: VST2q16wb_register + /* 1248 */ MCD_OPC_FilterValue, + 2, + 72, + 21, + 0, // Skip to: 6701 + /* 1253 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1256 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1271 + /* 1261 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1286 + /* 1266 */ MCD_OPC_Decode, + 228, + 28, + 176, + 2, // Opcode: VST2q32wb_fixed + /* 1271 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1286 + /* 1276 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1286 + /* 1281 */ MCD_OPC_Decode, + 224, + 28, + 176, + 2, // Opcode: VST2q32 + /* 1286 */ MCD_OPC_CheckPredicate, + 26, + 34, + 21, + 0, // Skip to: 6701 + /* 1291 */ MCD_OPC_Decode, + 229, + 28, + 176, + 2, // Opcode: VST2q32wb_register + /* 1296 */ MCD_OPC_FilterValue, + 233, + 3, + 23, + 21, + 0, // Skip to: 6701 + /* 1302 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1319 + /* 1307 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1319 + /* 1314 */ MCD_OPC_Decode, + 163, + 29, + 177, + 2, // Opcode: VST4LNd8 + /* 1319 */ MCD_OPC_CheckPredicate, + 26, + 1, + 21, + 0, // Skip to: 6701 + /* 1324 */ MCD_OPC_Decode, + 166, + 29, + 177, + 2, // Opcode: VST4LNd8_UPD + /* 1329 */ MCD_OPC_FilterValue, + 2, + 247, + 20, + 0, // Skip to: 6701 + /* 1334 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1337 */ MCD_OPC_FilterValue, + 232, + 3, + 147, + 0, + 0, // Skip to: 1490 + /* 1343 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1346 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 1394 + /* 1351 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1354 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1369 + /* 1359 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1384 + /* 1364 */ MCD_OPC_Decode, + 217, + 20, + 176, + 2, // Opcode: VLD2q8wb_fixed + /* 1369 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1384 + /* 1374 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1384 + /* 1379 */ MCD_OPC_Decode, + 213, + 20, + 176, + 2, // Opcode: VLD2q8 + /* 1384 */ MCD_OPC_CheckPredicate, + 26, + 192, + 20, + 0, // Skip to: 6701 + /* 1389 */ MCD_OPC_Decode, + 218, + 20, + 176, + 2, // Opcode: VLD2q8wb_register + /* 1394 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 1442 + /* 1399 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1402 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1417 + /* 1407 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1432 + /* 1412 */ MCD_OPC_Decode, + 205, + 20, + 176, + 2, // Opcode: VLD2q16wb_fixed + /* 1417 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1432 + /* 1422 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1432 + /* 1427 */ MCD_OPC_Decode, + 201, + 20, + 176, + 2, // Opcode: VLD2q16 + /* 1432 */ MCD_OPC_CheckPredicate, + 26, + 144, + 20, + 0, // Skip to: 6701 + /* 1437 */ MCD_OPC_Decode, + 206, + 20, + 176, + 2, // Opcode: VLD2q16wb_register + /* 1442 */ MCD_OPC_FilterValue, + 2, + 134, + 20, + 0, // Skip to: 6701 + /* 1447 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1450 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1465 + /* 1455 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1480 + /* 1460 */ MCD_OPC_Decode, + 211, + 20, + 176, + 2, // Opcode: VLD2q32wb_fixed + /* 1465 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1480 + /* 1470 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1480 + /* 1475 */ MCD_OPC_Decode, + 207, + 20, + 176, + 2, // Opcode: VLD2q32 + /* 1480 */ MCD_OPC_CheckPredicate, + 26, + 96, + 20, + 0, // Skip to: 6701 + /* 1485 */ MCD_OPC_Decode, + 212, + 20, + 176, + 2, // Opcode: VLD2q32wb_register + /* 1490 */ MCD_OPC_FilterValue, + 233, + 3, + 85, + 20, + 0, // Skip to: 6701 + /* 1496 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1513 + /* 1501 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1513 + /* 1508 */ MCD_OPC_Decode, + 200, + 21, + 178, + 2, // Opcode: VLD4LNd8 + /* 1513 */ MCD_OPC_CheckPredicate, + 26, + 63, + 20, + 0, // Skip to: 6701 + /* 1518 */ MCD_OPC_Decode, + 203, + 21, + 178, + 2, // Opcode: VLD4LNd8_UPD + /* 1523 */ MCD_OPC_FilterValue, + 4, + 54, + 1, + 0, // Skip to: 1838 + /* 1528 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1531 */ MCD_OPC_FilterValue, + 0, + 149, + 0, + 0, // Skip to: 1685 + /* 1536 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1539 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 1644 + /* 1545 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 1548 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 1580 + /* 1553 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1570 + /* 1558 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1570 + /* 1565 */ MCD_OPC_Decode, + 136, + 29, + 179, + 2, // Opcode: VST3d8 + /* 1570 */ MCD_OPC_CheckPredicate, + 26, + 6, + 20, + 0, // Skip to: 6701 + /* 1575 */ MCD_OPC_Decode, + 139, + 29, + 179, + 2, // Opcode: VST3d8_UPD + /* 1580 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 1612 + /* 1585 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1602 + /* 1590 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1602 + /* 1597 */ MCD_OPC_Decode, + 128, + 29, + 179, + 2, // Opcode: VST3d16 + /* 1602 */ MCD_OPC_CheckPredicate, + 26, + 230, + 19, + 0, // Skip to: 6701 + /* 1607 */ MCD_OPC_Decode, + 131, + 29, + 179, + 2, // Opcode: VST3d16_UPD + /* 1612 */ MCD_OPC_FilterValue, + 4, + 220, + 19, + 0, // Skip to: 6701 + /* 1617 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1634 + /* 1622 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1634 + /* 1629 */ MCD_OPC_Decode, + 132, + 29, + 179, + 2, // Opcode: VST3d32 + /* 1634 */ MCD_OPC_CheckPredicate, + 26, + 198, + 19, + 0, // Skip to: 6701 + /* 1639 */ MCD_OPC_Decode, + 135, + 29, + 179, + 2, // Opcode: VST3d32_UPD + /* 1644 */ MCD_OPC_FilterValue, + 233, + 3, + 187, + 19, + 0, // Skip to: 6701 + /* 1650 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 1653 */ MCD_OPC_FilterValue, + 0, + 179, + 19, + 0, // Skip to: 6701 + /* 1658 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1675 + /* 1663 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1675 + /* 1670 */ MCD_OPC_Decode, + 200, + 27, + 169, + 2, // Opcode: VST1LNd16 + /* 1675 */ MCD_OPC_CheckPredicate, + 26, + 157, + 19, + 0, // Skip to: 6701 + /* 1680 */ MCD_OPC_Decode, + 201, + 27, + 169, + 2, // Opcode: VST1LNd16_UPD + /* 1685 */ MCD_OPC_FilterValue, + 2, + 147, + 19, + 0, // Skip to: 6701 + /* 1690 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1693 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 1798 + /* 1699 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 1702 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 1734 + /* 1707 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1724 + /* 1712 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1724 + /* 1719 */ MCD_OPC_Decode, + 146, + 21, + 179, + 2, // Opcode: VLD3d8 + /* 1724 */ MCD_OPC_CheckPredicate, + 26, + 108, + 19, + 0, // Skip to: 6701 + /* 1729 */ MCD_OPC_Decode, + 149, + 21, + 179, + 2, // Opcode: VLD3d8_UPD + /* 1734 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 1766 + /* 1739 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1756 + /* 1744 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1756 + /* 1751 */ MCD_OPC_Decode, + 138, + 21, + 179, + 2, // Opcode: VLD3d16 + /* 1756 */ MCD_OPC_CheckPredicate, + 26, + 76, + 19, + 0, // Skip to: 6701 + /* 1761 */ MCD_OPC_Decode, + 141, + 21, + 179, + 2, // Opcode: VLD3d16_UPD + /* 1766 */ MCD_OPC_FilterValue, + 4, + 66, + 19, + 0, // Skip to: 6701 + /* 1771 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1788 + /* 1776 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1788 + /* 1783 */ MCD_OPC_Decode, + 142, + 21, + 179, + 2, // Opcode: VLD3d32 + /* 1788 */ MCD_OPC_CheckPredicate, + 26, + 44, + 19, + 0, // Skip to: 6701 + /* 1793 */ MCD_OPC_Decode, + 145, + 21, + 179, + 2, // Opcode: VLD3d32_UPD + /* 1798 */ MCD_OPC_FilterValue, + 233, + 3, + 33, + 19, + 0, // Skip to: 6701 + /* 1804 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1821 + /* 1809 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1821 + /* 1816 */ MCD_OPC_Decode, + 153, + 19, + 170, + 2, // Opcode: VLD1LNd16 + /* 1821 */ MCD_OPC_CheckPredicate, + 26, + 11, + 19, + 0, // Skip to: 6701 + /* 1826 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 4, + 19, + 0, // Skip to: 6701 + /* 1833 */ MCD_OPC_Decode, + 154, + 19, + 170, + 2, // Opcode: VLD1LNd16_UPD + /* 1838 */ MCD_OPC_FilterValue, + 5, + 137, + 1, + 0, // Skip to: 2236 + /* 1843 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 1846 */ MCD_OPC_FilterValue, + 0, + 39, + 1, + 0, // Skip to: 2146 + /* 1851 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1854 */ MCD_OPC_FilterValue, + 0, + 141, + 0, + 0, // Skip to: 2000 + /* 1859 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1862 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 1967 + /* 1868 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1871 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 1903 + /* 1876 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1893 + /* 1881 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1893 + /* 1888 */ MCD_OPC_Decode, + 150, + 29, + 179, + 2, // Opcode: VST3q8 + /* 1893 */ MCD_OPC_CheckPredicate, + 26, + 195, + 18, + 0, // Skip to: 6701 + /* 1898 */ MCD_OPC_Decode, + 152, + 29, + 179, + 2, // Opcode: VST3q8_UPD + /* 1903 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 1935 + /* 1908 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1925 + /* 1913 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1925 + /* 1920 */ MCD_OPC_Decode, + 140, + 29, + 179, + 2, // Opcode: VST3q16 + /* 1925 */ MCD_OPC_CheckPredicate, + 26, + 163, + 18, + 0, // Skip to: 6701 + /* 1930 */ MCD_OPC_Decode, + 142, + 29, + 179, + 2, // Opcode: VST3q16_UPD + /* 1935 */ MCD_OPC_FilterValue, + 2, + 153, + 18, + 0, // Skip to: 6701 + /* 1940 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1957 + /* 1945 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1957 + /* 1952 */ MCD_OPC_Decode, + 145, + 29, + 179, + 2, // Opcode: VST3q32 + /* 1957 */ MCD_OPC_CheckPredicate, + 26, + 131, + 18, + 0, // Skip to: 6701 + /* 1962 */ MCD_OPC_Decode, + 147, + 29, + 179, + 2, // Opcode: VST3q32_UPD + /* 1967 */ MCD_OPC_FilterValue, + 233, + 3, + 120, + 18, + 0, // Skip to: 6701 + /* 1973 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1990 + /* 1978 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1990 + /* 1985 */ MCD_OPC_Decode, + 180, + 28, + 171, + 2, // Opcode: VST2LNd16 + /* 1990 */ MCD_OPC_CheckPredicate, + 26, + 98, + 18, + 0, // Skip to: 6701 + /* 1995 */ MCD_OPC_Decode, + 183, + 28, + 171, + 2, // Opcode: VST2LNd16_UPD + /* 2000 */ MCD_OPC_FilterValue, + 2, + 88, + 18, + 0, // Skip to: 6701 + /* 2005 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2008 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 2113 + /* 2014 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 2017 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 2049 + /* 2022 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2039 + /* 2027 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2039 + /* 2034 */ MCD_OPC_Decode, + 160, + 21, + 179, + 2, // Opcode: VLD3q8 + /* 2039 */ MCD_OPC_CheckPredicate, + 26, + 49, + 18, + 0, // Skip to: 6701 + /* 2044 */ MCD_OPC_Decode, + 162, + 21, + 179, + 2, // Opcode: VLD3q8_UPD + /* 2049 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 2081 + /* 2054 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2071 + /* 2059 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2071 + /* 2066 */ MCD_OPC_Decode, + 150, + 21, + 179, + 2, // Opcode: VLD3q16 + /* 2071 */ MCD_OPC_CheckPredicate, + 26, + 17, + 18, + 0, // Skip to: 6701 + /* 2076 */ MCD_OPC_Decode, + 152, + 21, + 179, + 2, // Opcode: VLD3q16_UPD + /* 2081 */ MCD_OPC_FilterValue, + 2, + 7, + 18, + 0, // Skip to: 6701 + /* 2086 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2103 + /* 2091 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2103 + /* 2098 */ MCD_OPC_Decode, + 155, + 21, + 179, + 2, // Opcode: VLD3q32 + /* 2103 */ MCD_OPC_CheckPredicate, + 26, + 241, + 17, + 0, // Skip to: 6701 + /* 2108 */ MCD_OPC_Decode, + 157, + 21, + 179, + 2, // Opcode: VLD3q32_UPD + /* 2113 */ MCD_OPC_FilterValue, + 233, + 3, + 230, + 17, + 0, // Skip to: 6701 + /* 2119 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2136 + /* 2124 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2136 + /* 2131 */ MCD_OPC_Decode, + 163, + 20, + 172, + 2, // Opcode: VLD2LNd16 + /* 2136 */ MCD_OPC_CheckPredicate, + 26, + 208, + 17, + 0, // Skip to: 6701 + /* 2141 */ MCD_OPC_Decode, + 166, + 20, + 172, + 2, // Opcode: VLD2LNd16_UPD + /* 2146 */ MCD_OPC_FilterValue, + 1, + 198, + 17, + 0, // Skip to: 6701 + /* 2151 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 2154 */ MCD_OPC_FilterValue, + 0, + 36, + 0, + 0, // Skip to: 2195 + /* 2159 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2162 */ MCD_OPC_FilterValue, + 233, + 3, + 181, + 17, + 0, // Skip to: 6701 + /* 2168 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2185 + /* 2173 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2185 + /* 2180 */ MCD_OPC_Decode, + 192, + 28, + 171, + 2, // Opcode: VST2LNq16 + /* 2185 */ MCD_OPC_CheckPredicate, + 26, + 159, + 17, + 0, // Skip to: 6701 + /* 2190 */ MCD_OPC_Decode, + 195, + 28, + 171, + 2, // Opcode: VST2LNq16_UPD + /* 2195 */ MCD_OPC_FilterValue, + 2, + 149, + 17, + 0, // Skip to: 6701 + /* 2200 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2203 */ MCD_OPC_FilterValue, + 233, + 3, + 140, + 17, + 0, // Skip to: 6701 + /* 2209 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2226 + /* 2214 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2226 + /* 2221 */ MCD_OPC_Decode, + 175, + 20, + 172, + 2, // Opcode: VLD2LNq16 + /* 2226 */ MCD_OPC_CheckPredicate, + 26, + 118, + 17, + 0, // Skip to: 6701 + /* 2231 */ MCD_OPC_Decode, + 178, + 20, + 172, + 2, // Opcode: VLD2LNq16_UPD + /* 2236 */ MCD_OPC_FilterValue, + 6, + 108, + 2, + 0, // Skip to: 2861 + /* 2241 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 2244 */ MCD_OPC_FilterValue, + 0, + 49, + 1, + 0, // Skip to: 2554 + /* 2249 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2252 */ MCD_OPC_FilterValue, + 232, + 3, + 223, + 0, + 0, // Skip to: 2481 + /* 2258 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 2261 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 2316 + /* 2266 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2269 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2284 + /* 2274 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 2306 + /* 2279 */ MCD_OPC_Decode, + 140, + 28, + 173, + 2, // Opcode: VST1d8Twb_fixed + /* 2284 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2306 + /* 2289 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2306 + /* 2294 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 5, + 0, + 0, // Skip to: 2306 + /* 2301 */ MCD_OPC_Decode, + 136, + 28, + 173, + 2, // Opcode: VST1d8T + /* 2306 */ MCD_OPC_CheckPredicate, + 26, + 38, + 17, + 0, // Skip to: 6701 + /* 2311 */ MCD_OPC_Decode, + 141, + 28, + 173, + 2, // Opcode: VST1d8Twb_register + /* 2316 */ MCD_OPC_FilterValue, + 1, + 50, + 0, + 0, // Skip to: 2371 + /* 2321 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2324 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2339 + /* 2329 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 2361 + /* 2334 */ MCD_OPC_Decode, + 223, + 27, + 173, + 2, // Opcode: VST1d16Twb_fixed + /* 2339 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2361 + /* 2344 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2361 + /* 2349 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 5, + 0, + 0, // Skip to: 2361 + /* 2356 */ MCD_OPC_Decode, + 219, + 27, + 173, + 2, // Opcode: VST1d16T + /* 2361 */ MCD_OPC_CheckPredicate, + 26, + 239, + 16, + 0, // Skip to: 6701 + /* 2366 */ MCD_OPC_Decode, + 224, + 27, + 173, + 2, // Opcode: VST1d16Twb_register + /* 2371 */ MCD_OPC_FilterValue, + 2, + 50, + 0, + 0, // Skip to: 2426 + /* 2376 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2379 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2394 + /* 2384 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 2416 + /* 2389 */ MCD_OPC_Decode, + 238, + 27, + 173, + 2, // Opcode: VST1d32Twb_fixed + /* 2394 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2416 + /* 2399 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2416 + /* 2404 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 5, + 0, + 0, // Skip to: 2416 + /* 2411 */ MCD_OPC_Decode, + 234, + 27, + 173, + 2, // Opcode: VST1d32T + /* 2416 */ MCD_OPC_CheckPredicate, + 26, + 184, + 16, + 0, // Skip to: 6701 + /* 2421 */ MCD_OPC_Decode, + 239, + 27, + 173, + 2, // Opcode: VST1d32Twb_register + /* 2426 */ MCD_OPC_FilterValue, + 3, + 174, + 16, + 0, // Skip to: 6701 + /* 2431 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2434 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2449 + /* 2439 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 2471 + /* 2444 */ MCD_OPC_Decode, + 253, + 27, + 173, + 2, // Opcode: VST1d64Twb_fixed + /* 2449 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2471 + /* 2454 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2471 + /* 2459 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 5, + 0, + 0, // Skip to: 2471 + /* 2466 */ MCD_OPC_Decode, + 249, + 27, + 173, + 2, // Opcode: VST1d64T + /* 2471 */ MCD_OPC_CheckPredicate, + 26, + 129, + 16, + 0, // Skip to: 6701 + /* 2476 */ MCD_OPC_Decode, + 254, + 27, + 173, + 2, // Opcode: VST1d64Twb_register + /* 2481 */ MCD_OPC_FilterValue, + 233, + 3, + 118, + 16, + 0, // Skip to: 6701 + /* 2487 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 2490 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 2522 + /* 2495 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2512 + /* 2500 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2512 + /* 2507 */ MCD_OPC_Decode, + 236, + 28, + 174, + 2, // Opcode: VST3LNd16 + /* 2512 */ MCD_OPC_CheckPredicate, + 26, + 88, + 16, + 0, // Skip to: 6701 + /* 2517 */ MCD_OPC_Decode, + 239, + 28, + 174, + 2, // Opcode: VST3LNd16_UPD + /* 2522 */ MCD_OPC_FilterValue, + 2, + 78, + 16, + 0, // Skip to: 6701 + /* 2527 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2544 + /* 2532 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2544 + /* 2539 */ MCD_OPC_Decode, + 248, + 28, + 174, + 2, // Opcode: VST3LNq16 + /* 2544 */ MCD_OPC_CheckPredicate, + 26, + 56, + 16, + 0, // Skip to: 6701 + /* 2549 */ MCD_OPC_Decode, + 251, + 28, + 174, + 2, // Opcode: VST3LNq16_UPD + /* 2554 */ MCD_OPC_FilterValue, + 2, + 46, + 16, + 0, // Skip to: 6701 + /* 2559 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 2562 */ MCD_OPC_FilterValue, + 0, + 245, + 0, + 0, // Skip to: 2812 + /* 2567 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2570 */ MCD_OPC_FilterValue, + 232, + 3, + 195, + 0, + 0, // Skip to: 2771 + /* 2576 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 2579 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 2627 + /* 2584 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2587 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2602 + /* 2592 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 2617 + /* 2597 */ MCD_OPC_Decode, + 221, + 19, + 173, + 2, // Opcode: VLD1d8Twb_fixed + /* 2602 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2617 + /* 2607 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 2617 + /* 2612 */ MCD_OPC_Decode, + 217, + 19, + 173, + 2, // Opcode: VLD1d8T + /* 2617 */ MCD_OPC_CheckPredicate, + 26, + 239, + 15, + 0, // Skip to: 6701 + /* 2622 */ MCD_OPC_Decode, + 222, + 19, + 173, + 2, // Opcode: VLD1d8Twb_register + /* 2627 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 2675 + /* 2632 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2635 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2650 + /* 2640 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 2665 + /* 2645 */ MCD_OPC_Decode, + 176, + 19, + 173, + 2, // Opcode: VLD1d16Twb_fixed + /* 2650 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2665 + /* 2655 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 2665 + /* 2660 */ MCD_OPC_Decode, + 172, + 19, + 173, + 2, // Opcode: VLD1d16T + /* 2665 */ MCD_OPC_CheckPredicate, + 26, + 191, + 15, + 0, // Skip to: 6701 + /* 2670 */ MCD_OPC_Decode, + 177, + 19, + 173, + 2, // Opcode: VLD1d16Twb_register + /* 2675 */ MCD_OPC_FilterValue, + 2, + 43, + 0, + 0, // Skip to: 2723 + /* 2680 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2683 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2698 + /* 2688 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 2713 + /* 2693 */ MCD_OPC_Decode, + 191, + 19, + 173, + 2, // Opcode: VLD1d32Twb_fixed + /* 2698 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2713 + /* 2703 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 2713 + /* 2708 */ MCD_OPC_Decode, + 187, + 19, + 173, + 2, // Opcode: VLD1d32T + /* 2713 */ MCD_OPC_CheckPredicate, + 26, + 143, + 15, + 0, // Skip to: 6701 + /* 2718 */ MCD_OPC_Decode, + 192, + 19, + 173, + 2, // Opcode: VLD1d32Twb_register + /* 2723 */ MCD_OPC_FilterValue, + 3, + 133, + 15, + 0, // Skip to: 6701 + /* 2728 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2731 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2746 + /* 2736 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 2761 + /* 2741 */ MCD_OPC_Decode, + 206, + 19, + 173, + 2, // Opcode: VLD1d64Twb_fixed + /* 2746 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2761 + /* 2751 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 2761 + /* 2756 */ MCD_OPC_Decode, + 202, + 19, + 173, + 2, // Opcode: VLD1d64T + /* 2761 */ MCD_OPC_CheckPredicate, + 26, + 95, + 15, + 0, // Skip to: 6701 + /* 2766 */ MCD_OPC_Decode, + 207, + 19, + 173, + 2, // Opcode: VLD1d64Twb_register + /* 2771 */ MCD_OPC_FilterValue, + 233, + 3, + 84, + 15, + 0, // Skip to: 6701 + /* 2777 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 2780 */ MCD_OPC_FilterValue, + 0, + 76, + 15, + 0, // Skip to: 6701 + /* 2785 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2802 + /* 2790 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2802 + /* 2797 */ MCD_OPC_Decode, + 246, + 20, + 175, + 2, // Opcode: VLD3LNd16 + /* 2802 */ MCD_OPC_CheckPredicate, + 26, + 54, + 15, + 0, // Skip to: 6701 + /* 2807 */ MCD_OPC_Decode, + 249, + 20, + 175, + 2, // Opcode: VLD3LNd16_UPD + /* 2812 */ MCD_OPC_FilterValue, + 1, + 44, + 15, + 0, // Skip to: 6701 + /* 2817 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 2820 */ MCD_OPC_FilterValue, + 0, + 36, + 15, + 0, // Skip to: 6701 + /* 2825 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2828 */ MCD_OPC_FilterValue, + 233, + 3, + 27, + 15, + 0, // Skip to: 6701 + /* 2834 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2851 + /* 2839 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2851 + /* 2846 */ MCD_OPC_Decode, + 130, + 21, + 175, + 2, // Opcode: VLD3LNq16 + /* 2851 */ MCD_OPC_CheckPredicate, + 26, + 5, + 15, + 0, // Skip to: 6701 + /* 2856 */ MCD_OPC_Decode, + 133, + 21, + 175, + 2, // Opcode: VLD3LNq16_UPD + /* 2861 */ MCD_OPC_FilterValue, + 7, + 73, + 2, + 0, // Skip to: 3451 + /* 2866 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 2869 */ MCD_OPC_FilterValue, + 0, + 231, + 1, + 0, // Skip to: 3361 + /* 2874 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 2877 */ MCD_OPC_FilterValue, + 0, + 237, + 0, + 0, // Skip to: 3119 + /* 2882 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2885 */ MCD_OPC_FilterValue, + 232, + 3, + 195, + 0, + 0, // Skip to: 3086 + /* 2891 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 2894 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 2942 + /* 2899 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2902 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2917 + /* 2907 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 2932 + /* 2912 */ MCD_OPC_Decode, + 142, + 28, + 173, + 2, // Opcode: VST1d8wb_fixed + /* 2917 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2932 + /* 2922 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 2932 + /* 2927 */ MCD_OPC_Decode, + 129, + 28, + 173, + 2, // Opcode: VST1d8 + /* 2932 */ MCD_OPC_CheckPredicate, + 26, + 180, + 14, + 0, // Skip to: 6701 + /* 2937 */ MCD_OPC_Decode, + 143, + 28, + 173, + 2, // Opcode: VST1d8wb_register + /* 2942 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 2990 + /* 2947 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2950 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2965 + /* 2955 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 2980 + /* 2960 */ MCD_OPC_Decode, + 225, + 27, + 173, + 2, // Opcode: VST1d16wb_fixed + /* 2965 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2980 + /* 2970 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 2980 + /* 2975 */ MCD_OPC_Decode, + 212, + 27, + 173, + 2, // Opcode: VST1d16 + /* 2980 */ MCD_OPC_CheckPredicate, + 26, + 132, + 14, + 0, // Skip to: 6701 + /* 2985 */ MCD_OPC_Decode, + 226, + 27, + 173, + 2, // Opcode: VST1d16wb_register + /* 2990 */ MCD_OPC_FilterValue, + 2, + 43, + 0, + 0, // Skip to: 3038 + /* 2995 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2998 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3013 + /* 3003 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3028 + /* 3008 */ MCD_OPC_Decode, + 240, + 27, + 173, + 2, // Opcode: VST1d32wb_fixed + /* 3013 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3028 + /* 3018 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3028 + /* 3023 */ MCD_OPC_Decode, + 227, + 27, + 173, + 2, // Opcode: VST1d32 + /* 3028 */ MCD_OPC_CheckPredicate, + 26, + 84, + 14, + 0, // Skip to: 6701 + /* 3033 */ MCD_OPC_Decode, + 241, + 27, + 173, + 2, // Opcode: VST1d32wb_register + /* 3038 */ MCD_OPC_FilterValue, + 3, + 74, + 14, + 0, // Skip to: 6701 + /* 3043 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3046 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3061 + /* 3051 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3076 + /* 3056 */ MCD_OPC_Decode, + 255, + 27, + 173, + 2, // Opcode: VST1d64wb_fixed + /* 3061 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3076 + /* 3066 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3076 + /* 3071 */ MCD_OPC_Decode, + 242, + 27, + 173, + 2, // Opcode: VST1d64 + /* 3076 */ MCD_OPC_CheckPredicate, + 26, + 36, + 14, + 0, // Skip to: 6701 + /* 3081 */ MCD_OPC_Decode, + 128, + 28, + 173, + 2, // Opcode: VST1d64wb_register + /* 3086 */ MCD_OPC_FilterValue, + 233, + 3, + 25, + 14, + 0, // Skip to: 6701 + /* 3092 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 3109 + /* 3097 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 3109 + /* 3104 */ MCD_OPC_Decode, + 155, + 29, + 177, + 2, // Opcode: VST4LNd16 + /* 3109 */ MCD_OPC_CheckPredicate, + 26, + 3, + 14, + 0, // Skip to: 6701 + /* 3114 */ MCD_OPC_Decode, + 158, + 29, + 177, + 2, // Opcode: VST4LNd16_UPD + /* 3119 */ MCD_OPC_FilterValue, + 2, + 249, + 13, + 0, // Skip to: 6701 + /* 3124 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3127 */ MCD_OPC_FilterValue, + 232, + 3, + 195, + 0, + 0, // Skip to: 3328 + /* 3133 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 3136 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 3184 + /* 3141 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3144 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3159 + /* 3149 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3174 + /* 3154 */ MCD_OPC_Decode, + 223, + 19, + 173, + 2, // Opcode: VLD1d8wb_fixed + /* 3159 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3174 + /* 3164 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3174 + /* 3169 */ MCD_OPC_Decode, + 210, + 19, + 173, + 2, // Opcode: VLD1d8 + /* 3174 */ MCD_OPC_CheckPredicate, + 26, + 194, + 13, + 0, // Skip to: 6701 + /* 3179 */ MCD_OPC_Decode, + 224, + 19, + 173, + 2, // Opcode: VLD1d8wb_register + /* 3184 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 3232 + /* 3189 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3192 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3207 + /* 3197 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3222 + /* 3202 */ MCD_OPC_Decode, + 178, + 19, + 173, + 2, // Opcode: VLD1d16wb_fixed + /* 3207 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3222 + /* 3212 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3222 + /* 3217 */ MCD_OPC_Decode, + 165, + 19, + 173, + 2, // Opcode: VLD1d16 + /* 3222 */ MCD_OPC_CheckPredicate, + 26, + 146, + 13, + 0, // Skip to: 6701 + /* 3227 */ MCD_OPC_Decode, + 179, + 19, + 173, + 2, // Opcode: VLD1d16wb_register + /* 3232 */ MCD_OPC_FilterValue, + 2, + 43, + 0, + 0, // Skip to: 3280 + /* 3237 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3240 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3255 + /* 3245 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3270 + /* 3250 */ MCD_OPC_Decode, + 193, + 19, + 173, + 2, // Opcode: VLD1d32wb_fixed + /* 3255 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3270 + /* 3260 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3270 + /* 3265 */ MCD_OPC_Decode, + 180, + 19, + 173, + 2, // Opcode: VLD1d32 + /* 3270 */ MCD_OPC_CheckPredicate, + 26, + 98, + 13, + 0, // Skip to: 6701 + /* 3275 */ MCD_OPC_Decode, + 194, + 19, + 173, + 2, // Opcode: VLD1d32wb_register + /* 3280 */ MCD_OPC_FilterValue, + 3, + 88, + 13, + 0, // Skip to: 6701 + /* 3285 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3288 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3303 + /* 3293 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3318 + /* 3298 */ MCD_OPC_Decode, + 208, + 19, + 173, + 2, // Opcode: VLD1d64wb_fixed + /* 3303 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3318 + /* 3308 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3318 + /* 3313 */ MCD_OPC_Decode, + 195, + 19, + 173, + 2, // Opcode: VLD1d64 + /* 3318 */ MCD_OPC_CheckPredicate, + 26, + 50, + 13, + 0, // Skip to: 6701 + /* 3323 */ MCD_OPC_Decode, + 209, + 19, + 173, + 2, // Opcode: VLD1d64wb_register + /* 3328 */ MCD_OPC_FilterValue, + 233, + 3, + 39, + 13, + 0, // Skip to: 6701 + /* 3334 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 3351 + /* 3339 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 3351 + /* 3346 */ MCD_OPC_Decode, + 192, + 21, + 178, + 2, // Opcode: VLD4LNd16 + /* 3351 */ MCD_OPC_CheckPredicate, + 26, + 17, + 13, + 0, // Skip to: 6701 + /* 3356 */ MCD_OPC_Decode, + 195, + 21, + 178, + 2, // Opcode: VLD4LNd16_UPD + /* 3361 */ MCD_OPC_FilterValue, + 1, + 7, + 13, + 0, // Skip to: 6701 + /* 3366 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3369 */ MCD_OPC_FilterValue, + 0, + 36, + 0, + 0, // Skip to: 3410 + /* 3374 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3377 */ MCD_OPC_FilterValue, + 233, + 3, + 246, + 12, + 0, // Skip to: 6701 + /* 3383 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 3400 + /* 3388 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 3400 + /* 3395 */ MCD_OPC_Decode, + 167, + 29, + 177, + 2, // Opcode: VST4LNq16 + /* 3400 */ MCD_OPC_CheckPredicate, + 26, + 224, + 12, + 0, // Skip to: 6701 + /* 3405 */ MCD_OPC_Decode, + 170, + 29, + 177, + 2, // Opcode: VST4LNq16_UPD + /* 3410 */ MCD_OPC_FilterValue, + 2, + 214, + 12, + 0, // Skip to: 6701 + /* 3415 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3418 */ MCD_OPC_FilterValue, + 233, + 3, + 205, + 12, + 0, // Skip to: 6701 + /* 3424 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 3441 + /* 3429 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 3441 + /* 3436 */ MCD_OPC_Decode, + 204, + 21, + 178, + 2, // Opcode: VLD4LNq16 + /* 3441 */ MCD_OPC_CheckPredicate, + 26, + 183, + 12, + 0, // Skip to: 6701 + /* 3446 */ MCD_OPC_Decode, + 207, + 21, + 178, + 2, // Opcode: VLD4LNq16_UPD + /* 3451 */ MCD_OPC_FilterValue, + 8, + 185, + 1, + 0, // Skip to: 3897 + /* 3456 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3459 */ MCD_OPC_FilterValue, + 0, + 39, + 1, + 0, // Skip to: 3759 + /* 3464 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3467 */ MCD_OPC_FilterValue, + 0, + 141, + 0, + 0, // Skip to: 3613 + /* 3472 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3475 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 3580 + /* 3481 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3484 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 3532 + /* 3489 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3492 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3507 + /* 3497 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3522 + /* 3502 */ MCD_OPC_Decode, + 216, + 28, + 176, + 2, // Opcode: VST2d8wb_fixed + /* 3507 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3522 + /* 3512 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3522 + /* 3517 */ MCD_OPC_Decode, + 215, + 28, + 176, + 2, // Opcode: VST2d8 + /* 3522 */ MCD_OPC_CheckPredicate, + 26, + 102, + 12, + 0, // Skip to: 6701 + /* 3527 */ MCD_OPC_Decode, + 217, + 28, + 176, + 2, // Opcode: VST2d8wb_register + /* 3532 */ MCD_OPC_FilterValue, + 1, + 92, + 12, + 0, // Skip to: 6701 + /* 3537 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3540 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3555 + /* 3545 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3570 + /* 3550 */ MCD_OPC_Decode, + 213, + 28, + 176, + 2, // Opcode: VST2d32wb_fixed + /* 3555 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3570 + /* 3560 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3570 + /* 3565 */ MCD_OPC_Decode, + 212, + 28, + 176, + 2, // Opcode: VST2d32 + /* 3570 */ MCD_OPC_CheckPredicate, + 26, + 54, + 12, + 0, // Skip to: 6701 + /* 3575 */ MCD_OPC_Decode, + 214, + 28, + 176, + 2, // Opcode: VST2d32wb_register + /* 3580 */ MCD_OPC_FilterValue, + 233, + 3, + 43, + 12, + 0, // Skip to: 6701 + /* 3586 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 3603 + /* 3591 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 3603 + /* 3598 */ MCD_OPC_Decode, + 202, + 27, + 169, + 2, // Opcode: VST1LNd32 + /* 3603 */ MCD_OPC_CheckPredicate, + 26, + 21, + 12, + 0, // Skip to: 6701 + /* 3608 */ MCD_OPC_Decode, + 203, + 27, + 169, + 2, // Opcode: VST1LNd32_UPD + /* 3613 */ MCD_OPC_FilterValue, + 2, + 11, + 12, + 0, // Skip to: 6701 + /* 3618 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3621 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 3726 + /* 3627 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3630 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 3678 + /* 3635 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3638 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3653 + /* 3643 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3668 + /* 3648 */ MCD_OPC_Decode, + 199, + 20, + 176, + 2, // Opcode: VLD2d8wb_fixed + /* 3653 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3668 + /* 3658 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3668 + /* 3663 */ MCD_OPC_Decode, + 198, + 20, + 176, + 2, // Opcode: VLD2d8 + /* 3668 */ MCD_OPC_CheckPredicate, + 26, + 212, + 11, + 0, // Skip to: 6701 + /* 3673 */ MCD_OPC_Decode, + 200, + 20, + 176, + 2, // Opcode: VLD2d8wb_register + /* 3678 */ MCD_OPC_FilterValue, + 1, + 202, + 11, + 0, // Skip to: 6701 + /* 3683 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3686 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3701 + /* 3691 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3716 + /* 3696 */ MCD_OPC_Decode, + 196, + 20, + 176, + 2, // Opcode: VLD2d32wb_fixed + /* 3701 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3716 + /* 3706 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3716 + /* 3711 */ MCD_OPC_Decode, + 195, + 20, + 176, + 2, // Opcode: VLD2d32 + /* 3716 */ MCD_OPC_CheckPredicate, + 26, + 164, + 11, + 0, // Skip to: 6701 + /* 3721 */ MCD_OPC_Decode, + 197, + 20, + 176, + 2, // Opcode: VLD2d32wb_register + /* 3726 */ MCD_OPC_FilterValue, + 233, + 3, + 153, + 11, + 0, // Skip to: 6701 + /* 3732 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 3749 + /* 3737 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 3749 + /* 3744 */ MCD_OPC_Decode, + 155, + 19, + 170, + 2, // Opcode: VLD1LNd32 + /* 3749 */ MCD_OPC_CheckPredicate, + 26, + 131, + 11, + 0, // Skip to: 6701 + /* 3754 */ MCD_OPC_Decode, + 156, + 19, + 170, + 2, // Opcode: VLD1LNd32_UPD + /* 3759 */ MCD_OPC_FilterValue, + 1, + 121, + 11, + 0, // Skip to: 6701 + /* 3764 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3767 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 3832 + /* 3772 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3775 */ MCD_OPC_FilterValue, + 0, + 105, + 11, + 0, // Skip to: 6701 + /* 3780 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3783 */ MCD_OPC_FilterValue, + 232, + 3, + 96, + 11, + 0, // Skip to: 6701 + /* 3789 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3792 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3807 + /* 3797 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3822 + /* 3802 */ MCD_OPC_Decode, + 210, + 28, + 176, + 2, // Opcode: VST2d16wb_fixed + /* 3807 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3822 + /* 3812 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3822 + /* 3817 */ MCD_OPC_Decode, + 209, + 28, + 176, + 2, // Opcode: VST2d16 + /* 3822 */ MCD_OPC_CheckPredicate, + 26, + 58, + 11, + 0, // Skip to: 6701 + /* 3827 */ MCD_OPC_Decode, + 211, + 28, + 176, + 2, // Opcode: VST2d16wb_register + /* 3832 */ MCD_OPC_FilterValue, + 2, + 48, + 11, + 0, // Skip to: 6701 + /* 3837 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3840 */ MCD_OPC_FilterValue, + 0, + 40, + 11, + 0, // Skip to: 6701 + /* 3845 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3848 */ MCD_OPC_FilterValue, + 232, + 3, + 31, + 11, + 0, // Skip to: 6701 + /* 3854 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3857 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3872 + /* 3862 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3887 + /* 3867 */ MCD_OPC_Decode, + 193, + 20, + 176, + 2, // Opcode: VLD2d16wb_fixed + /* 3872 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3887 + /* 3877 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3887 + /* 3882 */ MCD_OPC_Decode, + 192, + 20, + 176, + 2, // Opcode: VLD2d16 + /* 3887 */ MCD_OPC_CheckPredicate, + 26, + 249, + 10, + 0, // Skip to: 6701 + /* 3892 */ MCD_OPC_Decode, + 194, + 20, + 176, + 2, // Opcode: VLD2d16wb_register + /* 3897 */ MCD_OPC_FilterValue, + 9, + 27, + 2, + 0, // Skip to: 4441 + /* 3902 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3905 */ MCD_OPC_FilterValue, + 0, + 55, + 1, + 0, // Skip to: 4221 + /* 3910 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3913 */ MCD_OPC_FilterValue, + 0, + 149, + 0, + 0, // Skip to: 4067 + /* 3918 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3921 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 4026 + /* 3927 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3930 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 3978 + /* 3935 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3938 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3953 + /* 3943 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3968 + /* 3948 */ MCD_OPC_Decode, + 207, + 28, + 176, + 2, // Opcode: VST2b8wb_fixed + /* 3953 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3968 + /* 3958 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3968 + /* 3963 */ MCD_OPC_Decode, + 206, + 28, + 176, + 2, // Opcode: VST2b8 + /* 3968 */ MCD_OPC_CheckPredicate, + 26, + 168, + 10, + 0, // Skip to: 6701 + /* 3973 */ MCD_OPC_Decode, + 208, + 28, + 176, + 2, // Opcode: VST2b8wb_register + /* 3978 */ MCD_OPC_FilterValue, + 1, + 158, + 10, + 0, // Skip to: 6701 + /* 3983 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3986 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4001 + /* 3991 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4016 + /* 3996 */ MCD_OPC_Decode, + 204, + 28, + 176, + 2, // Opcode: VST2b32wb_fixed + /* 4001 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4016 + /* 4006 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4016 + /* 4011 */ MCD_OPC_Decode, + 203, + 28, + 176, + 2, // Opcode: VST2b32 + /* 4016 */ MCD_OPC_CheckPredicate, + 26, + 120, + 10, + 0, // Skip to: 6701 + /* 4021 */ MCD_OPC_Decode, + 205, + 28, + 176, + 2, // Opcode: VST2b32wb_register + /* 4026 */ MCD_OPC_FilterValue, + 233, + 3, + 109, + 10, + 0, // Skip to: 6701 + /* 4032 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 4035 */ MCD_OPC_FilterValue, + 0, + 101, + 10, + 0, // Skip to: 6701 + /* 4040 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4057 + /* 4045 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4057 + /* 4052 */ MCD_OPC_Decode, + 184, + 28, + 171, + 2, // Opcode: VST2LNd32 + /* 4057 */ MCD_OPC_CheckPredicate, + 26, + 79, + 10, + 0, // Skip to: 6701 + /* 4062 */ MCD_OPC_Decode, + 187, + 28, + 171, + 2, // Opcode: VST2LNd32_UPD + /* 4067 */ MCD_OPC_FilterValue, + 2, + 69, + 10, + 0, // Skip to: 6701 + /* 4072 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4075 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 4180 + /* 4081 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4084 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 4132 + /* 4089 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4092 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4107 + /* 4097 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4122 + /* 4102 */ MCD_OPC_Decode, + 190, + 20, + 176, + 2, // Opcode: VLD2b8wb_fixed + /* 4107 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4122 + /* 4112 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4122 + /* 4117 */ MCD_OPC_Decode, + 189, + 20, + 176, + 2, // Opcode: VLD2b8 + /* 4122 */ MCD_OPC_CheckPredicate, + 26, + 14, + 10, + 0, // Skip to: 6701 + /* 4127 */ MCD_OPC_Decode, + 191, + 20, + 176, + 2, // Opcode: VLD2b8wb_register + /* 4132 */ MCD_OPC_FilterValue, + 1, + 4, + 10, + 0, // Skip to: 6701 + /* 4137 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4140 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4155 + /* 4145 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4170 + /* 4150 */ MCD_OPC_Decode, + 187, + 20, + 176, + 2, // Opcode: VLD2b32wb_fixed + /* 4155 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4170 + /* 4160 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4170 + /* 4165 */ MCD_OPC_Decode, + 186, + 20, + 176, + 2, // Opcode: VLD2b32 + /* 4170 */ MCD_OPC_CheckPredicate, + 26, + 222, + 9, + 0, // Skip to: 6701 + /* 4175 */ MCD_OPC_Decode, + 188, + 20, + 176, + 2, // Opcode: VLD2b32wb_register + /* 4180 */ MCD_OPC_FilterValue, + 233, + 3, + 211, + 9, + 0, // Skip to: 6701 + /* 4186 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 4189 */ MCD_OPC_FilterValue, + 0, + 203, + 9, + 0, // Skip to: 6701 + /* 4194 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4211 + /* 4199 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4211 + /* 4206 */ MCD_OPC_Decode, + 167, + 20, + 172, + 2, // Opcode: VLD2LNd32 + /* 4211 */ MCD_OPC_CheckPredicate, + 26, + 181, + 9, + 0, // Skip to: 6701 + /* 4216 */ MCD_OPC_Decode, + 170, + 20, + 172, + 2, // Opcode: VLD2LNd32_UPD + /* 4221 */ MCD_OPC_FilterValue, + 1, + 171, + 9, + 0, // Skip to: 6701 + /* 4226 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 4229 */ MCD_OPC_FilterValue, + 0, + 101, + 0, + 0, // Skip to: 4335 + /* 4234 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4237 */ MCD_OPC_FilterValue, + 232, + 3, + 51, + 0, + 0, // Skip to: 4294 + /* 4243 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4246 */ MCD_OPC_FilterValue, + 0, + 146, + 9, + 0, // Skip to: 6701 + /* 4251 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4254 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4269 + /* 4259 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4284 + /* 4264 */ MCD_OPC_Decode, + 201, + 28, + 176, + 2, // Opcode: VST2b16wb_fixed + /* 4269 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4284 + /* 4274 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4284 + /* 4279 */ MCD_OPC_Decode, + 200, + 28, + 176, + 2, // Opcode: VST2b16 + /* 4284 */ MCD_OPC_CheckPredicate, + 26, + 108, + 9, + 0, // Skip to: 6701 + /* 4289 */ MCD_OPC_Decode, + 202, + 28, + 176, + 2, // Opcode: VST2b16wb_register + /* 4294 */ MCD_OPC_FilterValue, + 233, + 3, + 97, + 9, + 0, // Skip to: 6701 + /* 4300 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 4303 */ MCD_OPC_FilterValue, + 0, + 89, + 9, + 0, // Skip to: 6701 + /* 4308 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4325 + /* 4313 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4325 + /* 4320 */ MCD_OPC_Decode, + 196, + 28, + 171, + 2, // Opcode: VST2LNq32 + /* 4325 */ MCD_OPC_CheckPredicate, + 26, + 67, + 9, + 0, // Skip to: 6701 + /* 4330 */ MCD_OPC_Decode, + 199, + 28, + 171, + 2, // Opcode: VST2LNq32_UPD + /* 4335 */ MCD_OPC_FilterValue, + 2, + 57, + 9, + 0, // Skip to: 6701 + /* 4340 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4343 */ MCD_OPC_FilterValue, + 232, + 3, + 51, + 0, + 0, // Skip to: 4400 + /* 4349 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4352 */ MCD_OPC_FilterValue, + 0, + 40, + 9, + 0, // Skip to: 6701 + /* 4357 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4360 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4375 + /* 4365 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4390 + /* 4370 */ MCD_OPC_Decode, + 184, + 20, + 176, + 2, // Opcode: VLD2b16wb_fixed + /* 4375 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4390 + /* 4380 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4390 + /* 4385 */ MCD_OPC_Decode, + 183, + 20, + 176, + 2, // Opcode: VLD2b16 + /* 4390 */ MCD_OPC_CheckPredicate, + 26, + 2, + 9, + 0, // Skip to: 6701 + /* 4395 */ MCD_OPC_Decode, + 185, + 20, + 176, + 2, // Opcode: VLD2b16wb_register + /* 4400 */ MCD_OPC_FilterValue, + 233, + 3, + 247, + 8, + 0, // Skip to: 6701 + /* 4406 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 4409 */ MCD_OPC_FilterValue, + 0, + 239, + 8, + 0, // Skip to: 6701 + /* 4414 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4431 + /* 4419 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4431 + /* 4426 */ MCD_OPC_Decode, + 179, + 20, + 172, + 2, // Opcode: VLD2LNq32 + /* 4431 */ MCD_OPC_CheckPredicate, + 26, + 217, + 8, + 0, // Skip to: 6701 + /* 4436 */ MCD_OPC_Decode, + 182, + 20, + 172, + 2, // Opcode: VLD2LNq32_UPD + /* 4441 */ MCD_OPC_FilterValue, + 10, + 123, + 2, + 0, // Skip to: 5081 + /* 4446 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4449 */ MCD_OPC_FilterValue, + 0, + 55, + 1, + 0, // Skip to: 4765 + /* 4454 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 4457 */ MCD_OPC_FilterValue, + 0, + 149, + 0, + 0, // Skip to: 4611 + /* 4462 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4465 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 4570 + /* 4471 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4474 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 4522 + /* 4479 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4482 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4497 + /* 4487 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4512 + /* 4492 */ MCD_OPC_Decode, + 178, + 28, + 173, + 2, // Opcode: VST1q8wb_fixed + /* 4497 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4512 + /* 4502 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4512 + /* 4507 */ MCD_OPC_Decode, + 171, + 28, + 173, + 2, // Opcode: VST1q8 + /* 4512 */ MCD_OPC_CheckPredicate, + 26, + 136, + 8, + 0, // Skip to: 6701 + /* 4517 */ MCD_OPC_Decode, + 179, + 28, + 173, + 2, // Opcode: VST1q8wb_register + /* 4522 */ MCD_OPC_FilterValue, + 1, + 126, + 8, + 0, // Skip to: 6701 + /* 4527 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4530 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4545 + /* 4535 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4560 + /* 4540 */ MCD_OPC_Decode, + 160, + 28, + 173, + 2, // Opcode: VST1q32wb_fixed + /* 4545 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4560 + /* 4550 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4560 + /* 4555 */ MCD_OPC_Decode, + 153, + 28, + 173, + 2, // Opcode: VST1q32 + /* 4560 */ MCD_OPC_CheckPredicate, + 26, + 88, + 8, + 0, // Skip to: 6701 + /* 4565 */ MCD_OPC_Decode, + 161, + 28, + 173, + 2, // Opcode: VST1q32wb_register + /* 4570 */ MCD_OPC_FilterValue, + 233, + 3, + 77, + 8, + 0, // Skip to: 6701 + /* 4576 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 4579 */ MCD_OPC_FilterValue, + 0, + 69, + 8, + 0, // Skip to: 6701 + /* 4584 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4601 + /* 4589 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4601 + /* 4596 */ MCD_OPC_Decode, + 240, + 28, + 174, + 2, // Opcode: VST3LNd32 + /* 4601 */ MCD_OPC_CheckPredicate, + 26, + 47, + 8, + 0, // Skip to: 6701 + /* 4606 */ MCD_OPC_Decode, + 243, + 28, + 174, + 2, // Opcode: VST3LNd32_UPD + /* 4611 */ MCD_OPC_FilterValue, + 2, + 37, + 8, + 0, // Skip to: 6701 + /* 4616 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4619 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 4724 + /* 4625 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4628 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 4676 + /* 4633 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4636 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4651 + /* 4641 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4666 + /* 4646 */ MCD_OPC_Decode, + 131, + 20, + 173, + 2, // Opcode: VLD1q8wb_fixed + /* 4651 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4666 + /* 4656 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4666 + /* 4661 */ MCD_OPC_Decode, + 252, + 19, + 173, + 2, // Opcode: VLD1q8 + /* 4666 */ MCD_OPC_CheckPredicate, + 26, + 238, + 7, + 0, // Skip to: 6701 + /* 4671 */ MCD_OPC_Decode, + 132, + 20, + 173, + 2, // Opcode: VLD1q8wb_register + /* 4676 */ MCD_OPC_FilterValue, + 1, + 228, + 7, + 0, // Skip to: 6701 + /* 4681 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4684 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4699 + /* 4689 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4714 + /* 4694 */ MCD_OPC_Decode, + 241, + 19, + 173, + 2, // Opcode: VLD1q32wb_fixed + /* 4699 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4714 + /* 4704 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4714 + /* 4709 */ MCD_OPC_Decode, + 234, + 19, + 173, + 2, // Opcode: VLD1q32 + /* 4714 */ MCD_OPC_CheckPredicate, + 26, + 190, + 7, + 0, // Skip to: 6701 + /* 4719 */ MCD_OPC_Decode, + 242, + 19, + 173, + 2, // Opcode: VLD1q32wb_register + /* 4724 */ MCD_OPC_FilterValue, + 233, + 3, + 179, + 7, + 0, // Skip to: 6701 + /* 4730 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 4733 */ MCD_OPC_FilterValue, + 0, + 171, + 7, + 0, // Skip to: 6701 + /* 4738 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4755 + /* 4743 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4755 + /* 4750 */ MCD_OPC_Decode, + 250, + 20, + 175, + 2, // Opcode: VLD3LNd32 + /* 4755 */ MCD_OPC_CheckPredicate, + 26, + 149, + 7, + 0, // Skip to: 6701 + /* 4760 */ MCD_OPC_Decode, + 253, + 20, + 175, + 2, // Opcode: VLD3LNd32_UPD + /* 4765 */ MCD_OPC_FilterValue, + 1, + 139, + 7, + 0, // Skip to: 6701 + /* 4770 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 4773 */ MCD_OPC_FilterValue, + 0, + 149, + 0, + 0, // Skip to: 4927 + /* 4778 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4781 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 4886 + /* 4787 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4790 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 4838 + /* 4795 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4798 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4813 + /* 4803 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4828 + /* 4808 */ MCD_OPC_Decode, + 151, + 28, + 173, + 2, // Opcode: VST1q16wb_fixed + /* 4813 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4828 + /* 4818 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4828 + /* 4823 */ MCD_OPC_Decode, + 144, + 28, + 173, + 2, // Opcode: VST1q16 + /* 4828 */ MCD_OPC_CheckPredicate, + 26, + 76, + 7, + 0, // Skip to: 6701 + /* 4833 */ MCD_OPC_Decode, + 152, + 28, + 173, + 2, // Opcode: VST1q16wb_register + /* 4838 */ MCD_OPC_FilterValue, + 1, + 66, + 7, + 0, // Skip to: 6701 + /* 4843 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4846 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4861 + /* 4851 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4876 + /* 4856 */ MCD_OPC_Decode, + 169, + 28, + 173, + 2, // Opcode: VST1q64wb_fixed + /* 4861 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4876 + /* 4866 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4876 + /* 4871 */ MCD_OPC_Decode, + 162, + 28, + 173, + 2, // Opcode: VST1q64 + /* 4876 */ MCD_OPC_CheckPredicate, + 26, + 28, + 7, + 0, // Skip to: 6701 + /* 4881 */ MCD_OPC_Decode, + 170, + 28, + 173, + 2, // Opcode: VST1q64wb_register + /* 4886 */ MCD_OPC_FilterValue, + 233, + 3, + 17, + 7, + 0, // Skip to: 6701 + /* 4892 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 4895 */ MCD_OPC_FilterValue, + 0, + 9, + 7, + 0, // Skip to: 6701 + /* 4900 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4917 + /* 4905 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4917 + /* 4912 */ MCD_OPC_Decode, + 252, + 28, + 174, + 2, // Opcode: VST3LNq32 + /* 4917 */ MCD_OPC_CheckPredicate, + 26, + 243, + 6, + 0, // Skip to: 6701 + /* 4922 */ MCD_OPC_Decode, + 255, + 28, + 174, + 2, // Opcode: VST3LNq32_UPD + /* 4927 */ MCD_OPC_FilterValue, + 2, + 233, + 6, + 0, // Skip to: 6701 + /* 4932 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4935 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 5040 + /* 4941 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4944 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 4992 + /* 4949 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4952 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4967 + /* 4957 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4982 + /* 4962 */ MCD_OPC_Decode, + 232, + 19, + 173, + 2, // Opcode: VLD1q16wb_fixed + /* 4967 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4982 + /* 4972 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4982 + /* 4977 */ MCD_OPC_Decode, + 225, + 19, + 173, + 2, // Opcode: VLD1q16 + /* 4982 */ MCD_OPC_CheckPredicate, + 26, + 178, + 6, + 0, // Skip to: 6701 + /* 4987 */ MCD_OPC_Decode, + 233, + 19, + 173, + 2, // Opcode: VLD1q16wb_register + /* 4992 */ MCD_OPC_FilterValue, + 1, + 168, + 6, + 0, // Skip to: 6701 + /* 4997 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5000 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5015 + /* 5005 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5030 + /* 5010 */ MCD_OPC_Decode, + 250, + 19, + 173, + 2, // Opcode: VLD1q64wb_fixed + /* 5015 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5030 + /* 5020 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5030 + /* 5025 */ MCD_OPC_Decode, + 243, + 19, + 173, + 2, // Opcode: VLD1q64 + /* 5030 */ MCD_OPC_CheckPredicate, + 26, + 130, + 6, + 0, // Skip to: 6701 + /* 5035 */ MCD_OPC_Decode, + 251, + 19, + 173, + 2, // Opcode: VLD1q64wb_register + /* 5040 */ MCD_OPC_FilterValue, + 233, + 3, + 119, + 6, + 0, // Skip to: 6701 + /* 5046 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 5049 */ MCD_OPC_FilterValue, + 0, + 111, + 6, + 0, // Skip to: 6701 + /* 5054 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 5071 + /* 5059 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 5071 + /* 5066 */ MCD_OPC_Decode, + 134, + 21, + 175, + 2, // Opcode: VLD3LNq32 + /* 5071 */ MCD_OPC_CheckPredicate, + 26, + 89, + 6, + 0, // Skip to: 6701 + /* 5076 */ MCD_OPC_Decode, + 137, + 21, + 175, + 2, // Opcode: VLD3LNq32_UPD + /* 5081 */ MCD_OPC_FilterValue, + 11, + 183, + 0, + 0, // Skip to: 5269 + /* 5086 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5089 */ MCD_OPC_FilterValue, + 0, + 85, + 0, + 0, // Skip to: 5179 + /* 5094 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5097 */ MCD_OPC_FilterValue, + 0, + 36, + 0, + 0, // Skip to: 5138 + /* 5102 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5105 */ MCD_OPC_FilterValue, + 233, + 3, + 54, + 6, + 0, // Skip to: 6701 + /* 5111 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 5128 + /* 5116 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 5128 + /* 5123 */ MCD_OPC_Decode, + 159, + 29, + 177, + 2, // Opcode: VST4LNd32 + /* 5128 */ MCD_OPC_CheckPredicate, + 26, + 32, + 6, + 0, // Skip to: 6701 + /* 5133 */ MCD_OPC_Decode, + 162, + 29, + 177, + 2, // Opcode: VST4LNd32_UPD + /* 5138 */ MCD_OPC_FilterValue, + 2, + 22, + 6, + 0, // Skip to: 6701 + /* 5143 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5146 */ MCD_OPC_FilterValue, + 233, + 3, + 13, + 6, + 0, // Skip to: 6701 + /* 5152 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 5169 + /* 5157 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 5169 + /* 5164 */ MCD_OPC_Decode, + 196, + 21, + 178, + 2, // Opcode: VLD4LNd32 + /* 5169 */ MCD_OPC_CheckPredicate, + 26, + 247, + 5, + 0, // Skip to: 6701 + /* 5174 */ MCD_OPC_Decode, + 199, + 21, + 178, + 2, // Opcode: VLD4LNd32_UPD + /* 5179 */ MCD_OPC_FilterValue, + 1, + 237, + 5, + 0, // Skip to: 6701 + /* 5184 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5187 */ MCD_OPC_FilterValue, + 0, + 36, + 0, + 0, // Skip to: 5228 + /* 5192 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5195 */ MCD_OPC_FilterValue, + 233, + 3, + 220, + 5, + 0, // Skip to: 6701 + /* 5201 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 5218 + /* 5206 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 5218 + /* 5213 */ MCD_OPC_Decode, + 171, + 29, + 177, + 2, // Opcode: VST4LNq32 + /* 5218 */ MCD_OPC_CheckPredicate, + 26, + 198, + 5, + 0, // Skip to: 6701 + /* 5223 */ MCD_OPC_Decode, + 174, + 29, + 177, + 2, // Opcode: VST4LNq32_UPD + /* 5228 */ MCD_OPC_FilterValue, + 2, + 188, + 5, + 0, // Skip to: 6701 + /* 5233 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5236 */ MCD_OPC_FilterValue, + 233, + 3, + 179, + 5, + 0, // Skip to: 6701 + /* 5242 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 5259 + /* 5247 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 5259 + /* 5254 */ MCD_OPC_Decode, + 208, + 21, + 178, + 2, // Opcode: VLD4LNq32 + /* 5259 */ MCD_OPC_CheckPredicate, + 26, + 157, + 5, + 0, // Skip to: 6701 + /* 5264 */ MCD_OPC_Decode, + 211, + 21, + 178, + 2, // Opcode: VLD4LNq32_UPD + /* 5269 */ MCD_OPC_FilterValue, + 12, + 137, + 1, + 0, // Skip to: 5667 + /* 5274 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 5277 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 5342 + /* 5282 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5285 */ MCD_OPC_FilterValue, + 2, + 131, + 5, + 0, // Skip to: 6701 + /* 5290 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5293 */ MCD_OPC_FilterValue, + 233, + 3, + 122, + 5, + 0, // Skip to: 6701 + /* 5299 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5302 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5317 + /* 5307 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5332 + /* 5312 */ MCD_OPC_Decode, + 142, + 19, + 180, + 2, // Opcode: VLD1DUPd8wb_fixed + /* 5317 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5332 + /* 5322 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5332 + /* 5327 */ MCD_OPC_Decode, + 141, + 19, + 180, + 2, // Opcode: VLD1DUPd8 + /* 5332 */ MCD_OPC_CheckPredicate, + 26, + 84, + 5, + 0, // Skip to: 6701 + /* 5337 */ MCD_OPC_Decode, + 143, + 19, + 180, + 2, // Opcode: VLD1DUPd8wb_register + /* 5342 */ MCD_OPC_FilterValue, + 1, + 60, + 0, + 0, // Skip to: 5407 + /* 5347 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5350 */ MCD_OPC_FilterValue, + 2, + 66, + 5, + 0, // Skip to: 6701 + /* 5355 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5358 */ MCD_OPC_FilterValue, + 233, + 3, + 57, + 5, + 0, // Skip to: 6701 + /* 5364 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5367 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5382 + /* 5372 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5397 + /* 5377 */ MCD_OPC_Decode, + 151, + 19, + 180, + 2, // Opcode: VLD1DUPq8wb_fixed + /* 5382 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5397 + /* 5387 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5397 + /* 5392 */ MCD_OPC_Decode, + 150, + 19, + 180, + 2, // Opcode: VLD1DUPq8 + /* 5397 */ MCD_OPC_CheckPredicate, + 26, + 19, + 5, + 0, // Skip to: 6701 + /* 5402 */ MCD_OPC_Decode, + 152, + 19, + 180, + 2, // Opcode: VLD1DUPq8wb_register + /* 5407 */ MCD_OPC_FilterValue, + 2, + 60, + 0, + 0, // Skip to: 5472 + /* 5412 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5415 */ MCD_OPC_FilterValue, + 2, + 1, + 5, + 0, // Skip to: 6701 + /* 5420 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5423 */ MCD_OPC_FilterValue, + 233, + 3, + 248, + 4, + 0, // Skip to: 6701 + /* 5429 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5432 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5447 + /* 5437 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5462 + /* 5442 */ MCD_OPC_Decode, + 136, + 19, + 180, + 2, // Opcode: VLD1DUPd16wb_fixed + /* 5447 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5462 + /* 5452 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5462 + /* 5457 */ MCD_OPC_Decode, + 135, + 19, + 180, + 2, // Opcode: VLD1DUPd16 + /* 5462 */ MCD_OPC_CheckPredicate, + 26, + 210, + 4, + 0, // Skip to: 6701 + /* 5467 */ MCD_OPC_Decode, + 137, + 19, + 180, + 2, // Opcode: VLD1DUPd16wb_register + /* 5472 */ MCD_OPC_FilterValue, + 3, + 60, + 0, + 0, // Skip to: 5537 + /* 5477 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5480 */ MCD_OPC_FilterValue, + 2, + 192, + 4, + 0, // Skip to: 6701 + /* 5485 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5488 */ MCD_OPC_FilterValue, + 233, + 3, + 183, + 4, + 0, // Skip to: 6701 + /* 5494 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5497 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5512 + /* 5502 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5527 + /* 5507 */ MCD_OPC_Decode, + 145, + 19, + 180, + 2, // Opcode: VLD1DUPq16wb_fixed + /* 5512 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5527 + /* 5517 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5527 + /* 5522 */ MCD_OPC_Decode, + 144, + 19, + 180, + 2, // Opcode: VLD1DUPq16 + /* 5527 */ MCD_OPC_CheckPredicate, + 26, + 145, + 4, + 0, // Skip to: 6701 + /* 5532 */ MCD_OPC_Decode, + 146, + 19, + 180, + 2, // Opcode: VLD1DUPq16wb_register + /* 5537 */ MCD_OPC_FilterValue, + 4, + 60, + 0, + 0, // Skip to: 5602 + /* 5542 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5545 */ MCD_OPC_FilterValue, + 2, + 127, + 4, + 0, // Skip to: 6701 + /* 5550 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5553 */ MCD_OPC_FilterValue, + 233, + 3, + 118, + 4, + 0, // Skip to: 6701 + /* 5559 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5562 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5577 + /* 5567 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5592 + /* 5572 */ MCD_OPC_Decode, + 139, + 19, + 180, + 2, // Opcode: VLD1DUPd32wb_fixed + /* 5577 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5592 + /* 5582 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5592 + /* 5587 */ MCD_OPC_Decode, + 138, + 19, + 180, + 2, // Opcode: VLD1DUPd32 + /* 5592 */ MCD_OPC_CheckPredicate, + 26, + 80, + 4, + 0, // Skip to: 6701 + /* 5597 */ MCD_OPC_Decode, + 140, + 19, + 180, + 2, // Opcode: VLD1DUPd32wb_register + /* 5602 */ MCD_OPC_FilterValue, + 5, + 70, + 4, + 0, // Skip to: 6701 + /* 5607 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5610 */ MCD_OPC_FilterValue, + 2, + 62, + 4, + 0, // Skip to: 6701 + /* 5615 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5618 */ MCD_OPC_FilterValue, + 233, + 3, + 53, + 4, + 0, // Skip to: 6701 + /* 5624 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5627 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5642 + /* 5632 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5657 + /* 5637 */ MCD_OPC_Decode, + 148, + 19, + 180, + 2, // Opcode: VLD1DUPq32wb_fixed + /* 5642 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5657 + /* 5647 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5657 + /* 5652 */ MCD_OPC_Decode, + 147, + 19, + 180, + 2, // Opcode: VLD1DUPq32 + /* 5657 */ MCD_OPC_CheckPredicate, + 26, + 15, + 4, + 0, // Skip to: 6701 + /* 5662 */ MCD_OPC_Decode, + 149, + 19, + 180, + 2, // Opcode: VLD1DUPq32wb_register + /* 5667 */ MCD_OPC_FilterValue, + 13, + 137, + 1, + 0, // Skip to: 6065 + /* 5672 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 5675 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 5740 + /* 5680 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5683 */ MCD_OPC_FilterValue, + 2, + 245, + 3, + 0, // Skip to: 6701 + /* 5688 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5691 */ MCD_OPC_FilterValue, + 233, + 3, + 236, + 3, + 0, // Skip to: 6701 + /* 5697 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5700 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5715 + /* 5705 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5730 + /* 5710 */ MCD_OPC_Decode, + 146, + 20, + 181, + 2, // Opcode: VLD2DUPd8wb_fixed + /* 5715 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5730 + /* 5720 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5730 + /* 5725 */ MCD_OPC_Decode, + 145, + 20, + 181, + 2, // Opcode: VLD2DUPd8 + /* 5730 */ MCD_OPC_CheckPredicate, + 26, + 198, + 3, + 0, // Skip to: 6701 + /* 5735 */ MCD_OPC_Decode, + 147, + 20, + 181, + 2, // Opcode: VLD2DUPd8wb_register + /* 5740 */ MCD_OPC_FilterValue, + 1, + 60, + 0, + 0, // Skip to: 5805 + /* 5745 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5748 */ MCD_OPC_FilterValue, + 2, + 180, + 3, + 0, // Skip to: 6701 + /* 5753 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5756 */ MCD_OPC_FilterValue, + 233, + 3, + 171, + 3, + 0, // Skip to: 6701 + /* 5762 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5765 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5780 + /* 5770 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5795 + /* 5775 */ MCD_OPC_Decode, + 149, + 20, + 181, + 2, // Opcode: VLD2DUPd8x2wb_fixed + /* 5780 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5795 + /* 5785 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5795 + /* 5790 */ MCD_OPC_Decode, + 148, + 20, + 181, + 2, // Opcode: VLD2DUPd8x2 + /* 5795 */ MCD_OPC_CheckPredicate, + 26, + 133, + 3, + 0, // Skip to: 6701 + /* 5800 */ MCD_OPC_Decode, + 150, + 20, + 181, + 2, // Opcode: VLD2DUPd8x2wb_register + /* 5805 */ MCD_OPC_FilterValue, + 2, + 60, + 0, + 0, // Skip to: 5870 + /* 5810 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5813 */ MCD_OPC_FilterValue, + 2, + 115, + 3, + 0, // Skip to: 6701 + /* 5818 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5821 */ MCD_OPC_FilterValue, + 233, + 3, + 106, + 3, + 0, // Skip to: 6701 + /* 5827 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5830 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5845 + /* 5835 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5860 + /* 5840 */ MCD_OPC_Decode, + 134, + 20, + 181, + 2, // Opcode: VLD2DUPd16wb_fixed + /* 5845 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5860 + /* 5850 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5860 + /* 5855 */ MCD_OPC_Decode, + 133, + 20, + 181, + 2, // Opcode: VLD2DUPd16 + /* 5860 */ MCD_OPC_CheckPredicate, + 26, + 68, + 3, + 0, // Skip to: 6701 + /* 5865 */ MCD_OPC_Decode, + 135, + 20, + 181, + 2, // Opcode: VLD2DUPd16wb_register + /* 5870 */ MCD_OPC_FilterValue, + 3, + 60, + 0, + 0, // Skip to: 5935 + /* 5875 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5878 */ MCD_OPC_FilterValue, + 2, + 50, + 3, + 0, // Skip to: 6701 + /* 5883 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5886 */ MCD_OPC_FilterValue, + 233, + 3, + 41, + 3, + 0, // Skip to: 6701 + /* 5892 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5895 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5910 + /* 5900 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5925 + /* 5905 */ MCD_OPC_Decode, + 137, + 20, + 181, + 2, // Opcode: VLD2DUPd16x2wb_fixed + /* 5910 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5925 + /* 5915 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5925 + /* 5920 */ MCD_OPC_Decode, + 136, + 20, + 181, + 2, // Opcode: VLD2DUPd16x2 + /* 5925 */ MCD_OPC_CheckPredicate, + 26, + 3, + 3, + 0, // Skip to: 6701 + /* 5930 */ MCD_OPC_Decode, + 138, + 20, + 181, + 2, // Opcode: VLD2DUPd16x2wb_register + /* 5935 */ MCD_OPC_FilterValue, + 4, + 60, + 0, + 0, // Skip to: 6000 + /* 5940 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5943 */ MCD_OPC_FilterValue, + 2, + 241, + 2, + 0, // Skip to: 6701 + /* 5948 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5951 */ MCD_OPC_FilterValue, + 233, + 3, + 232, + 2, + 0, // Skip to: 6701 + /* 5957 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5960 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5975 + /* 5965 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5990 + /* 5970 */ MCD_OPC_Decode, + 140, + 20, + 181, + 2, // Opcode: VLD2DUPd32wb_fixed + /* 5975 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5990 + /* 5980 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5990 + /* 5985 */ MCD_OPC_Decode, + 139, + 20, + 181, + 2, // Opcode: VLD2DUPd32 + /* 5990 */ MCD_OPC_CheckPredicate, + 26, + 194, + 2, + 0, // Skip to: 6701 + /* 5995 */ MCD_OPC_Decode, + 141, + 20, + 181, + 2, // Opcode: VLD2DUPd32wb_register + /* 6000 */ MCD_OPC_FilterValue, + 5, + 184, + 2, + 0, // Skip to: 6701 + /* 6005 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6008 */ MCD_OPC_FilterValue, + 2, + 176, + 2, + 0, // Skip to: 6701 + /* 6013 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6016 */ MCD_OPC_FilterValue, + 233, + 3, + 167, + 2, + 0, // Skip to: 6701 + /* 6022 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 6025 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 6040 + /* 6030 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 6055 + /* 6035 */ MCD_OPC_Decode, + 143, + 20, + 181, + 2, // Opcode: VLD2DUPd32x2wb_fixed + /* 6040 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 6055 + /* 6045 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 6055 + /* 6050 */ MCD_OPC_Decode, + 142, + 20, + 181, + 2, // Opcode: VLD2DUPd32x2 + /* 6055 */ MCD_OPC_CheckPredicate, + 26, + 129, + 2, + 0, // Skip to: 6701 + /* 6060 */ MCD_OPC_Decode, + 144, + 20, + 181, + 2, // Opcode: VLD2DUPd32x2wb_register + /* 6065 */ MCD_OPC_FilterValue, + 14, + 41, + 1, + 0, // Skip to: 6367 + /* 6070 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 6073 */ MCD_OPC_FilterValue, + 0, + 44, + 0, + 0, // Skip to: 6122 + /* 6078 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6081 */ MCD_OPC_FilterValue, + 2, + 103, + 2, + 0, // Skip to: 6701 + /* 6086 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6089 */ MCD_OPC_FilterValue, + 233, + 3, + 94, + 2, + 0, // Skip to: 6701 + /* 6095 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6112 + /* 6100 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6112 + /* 6107 */ MCD_OPC_Decode, + 227, + 20, + 182, + 2, // Opcode: VLD3DUPd8 + /* 6112 */ MCD_OPC_CheckPredicate, + 26, + 72, + 2, + 0, // Skip to: 6701 + /* 6117 */ MCD_OPC_Decode, + 230, + 20, + 182, + 2, // Opcode: VLD3DUPd8_UPD + /* 6122 */ MCD_OPC_FilterValue, + 2, + 44, + 0, + 0, // Skip to: 6171 + /* 6127 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6130 */ MCD_OPC_FilterValue, + 2, + 54, + 2, + 0, // Skip to: 6701 + /* 6135 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6138 */ MCD_OPC_FilterValue, + 233, + 3, + 45, + 2, + 0, // Skip to: 6701 + /* 6144 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6161 + /* 6149 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6161 + /* 6156 */ MCD_OPC_Decode, + 241, + 20, + 182, + 2, // Opcode: VLD3DUPq8 + /* 6161 */ MCD_OPC_CheckPredicate, + 26, + 23, + 2, + 0, // Skip to: 6701 + /* 6166 */ MCD_OPC_Decode, + 245, + 20, + 182, + 2, // Opcode: VLD3DUPq8_UPD + /* 6171 */ MCD_OPC_FilterValue, + 4, + 44, + 0, + 0, // Skip to: 6220 + /* 6176 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6179 */ MCD_OPC_FilterValue, + 2, + 5, + 2, + 0, // Skip to: 6701 + /* 6184 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6187 */ MCD_OPC_FilterValue, + 233, + 3, + 252, + 1, + 0, // Skip to: 6701 + /* 6193 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6210 + /* 6198 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6210 + /* 6205 */ MCD_OPC_Decode, + 219, + 20, + 182, + 2, // Opcode: VLD3DUPd16 + /* 6210 */ MCD_OPC_CheckPredicate, + 26, + 230, + 1, + 0, // Skip to: 6701 + /* 6215 */ MCD_OPC_Decode, + 222, + 20, + 182, + 2, // Opcode: VLD3DUPd16_UPD + /* 6220 */ MCD_OPC_FilterValue, + 6, + 44, + 0, + 0, // Skip to: 6269 + /* 6225 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6228 */ MCD_OPC_FilterValue, + 2, + 212, + 1, + 0, // Skip to: 6701 + /* 6233 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6236 */ MCD_OPC_FilterValue, + 233, + 3, + 203, + 1, + 0, // Skip to: 6701 + /* 6242 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6259 + /* 6247 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6259 + /* 6254 */ MCD_OPC_Decode, + 231, + 20, + 182, + 2, // Opcode: VLD3DUPq16 + /* 6259 */ MCD_OPC_CheckPredicate, + 26, + 181, + 1, + 0, // Skip to: 6701 + /* 6264 */ MCD_OPC_Decode, + 235, + 20, + 182, + 2, // Opcode: VLD3DUPq16_UPD + /* 6269 */ MCD_OPC_FilterValue, + 8, + 44, + 0, + 0, // Skip to: 6318 + /* 6274 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6277 */ MCD_OPC_FilterValue, + 2, + 163, + 1, + 0, // Skip to: 6701 + /* 6282 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6285 */ MCD_OPC_FilterValue, + 233, + 3, + 154, + 1, + 0, // Skip to: 6701 + /* 6291 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6308 + /* 6296 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6308 + /* 6303 */ MCD_OPC_Decode, + 223, + 20, + 182, + 2, // Opcode: VLD3DUPd32 + /* 6308 */ MCD_OPC_CheckPredicate, + 26, + 132, + 1, + 0, // Skip to: 6701 + /* 6313 */ MCD_OPC_Decode, + 226, + 20, + 182, + 2, // Opcode: VLD3DUPd32_UPD + /* 6318 */ MCD_OPC_FilterValue, + 10, + 122, + 1, + 0, // Skip to: 6701 + /* 6323 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6326 */ MCD_OPC_FilterValue, + 2, + 114, + 1, + 0, // Skip to: 6701 + /* 6331 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6334 */ MCD_OPC_FilterValue, + 233, + 3, + 105, + 1, + 0, // Skip to: 6701 + /* 6340 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6357 + /* 6345 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6357 + /* 6352 */ MCD_OPC_Decode, + 236, + 20, + 182, + 2, // Opcode: VLD3DUPq32 + /* 6357 */ MCD_OPC_CheckPredicate, + 26, + 83, + 1, + 0, // Skip to: 6701 + /* 6362 */ MCD_OPC_Decode, + 240, + 20, + 182, + 2, // Opcode: VLD3DUPq32_UPD + /* 6367 */ MCD_OPC_FilterValue, + 15, + 73, + 1, + 0, // Skip to: 6701 + /* 6372 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 6375 */ MCD_OPC_FilterValue, + 0, + 158, + 0, + 0, // Skip to: 6538 + /* 6380 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6383 */ MCD_OPC_FilterValue, + 0, + 101, + 0, + 0, // Skip to: 6489 + /* 6388 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6391 */ MCD_OPC_FilterValue, + 0, + 44, + 0, + 0, // Skip to: 6440 + /* 6396 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6399 */ MCD_OPC_FilterValue, + 2, + 41, + 1, + 0, // Skip to: 6701 + /* 6404 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6407 */ MCD_OPC_FilterValue, + 233, + 3, + 32, + 1, + 0, // Skip to: 6701 + /* 6413 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6430 + /* 6418 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6430 + /* 6425 */ MCD_OPC_Decode, + 173, + 21, + 183, + 2, // Opcode: VLD4DUPd8 + /* 6430 */ MCD_OPC_CheckPredicate, + 26, + 10, + 1, + 0, // Skip to: 6701 + /* 6435 */ MCD_OPC_Decode, + 176, + 21, + 183, + 2, // Opcode: VLD4DUPd8_UPD + /* 6440 */ MCD_OPC_FilterValue, + 1, + 0, + 1, + 0, // Skip to: 6701 + /* 6445 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6448 */ MCD_OPC_FilterValue, + 2, + 248, + 0, + 0, // Skip to: 6701 + /* 6453 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6456 */ MCD_OPC_FilterValue, + 233, + 3, + 239, + 0, + 0, // Skip to: 6701 + /* 6462 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6479 + /* 6467 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6479 + /* 6474 */ MCD_OPC_Decode, + 165, + 21, + 183, + 2, // Opcode: VLD4DUPd16 + /* 6479 */ MCD_OPC_CheckPredicate, + 26, + 217, + 0, + 0, // Skip to: 6701 + /* 6484 */ MCD_OPC_Decode, + 168, + 21, + 183, + 2, // Opcode: VLD4DUPd16_UPD + /* 6489 */ MCD_OPC_FilterValue, + 1, + 207, + 0, + 0, // Skip to: 6701 + /* 6494 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6497 */ MCD_OPC_FilterValue, + 2, + 199, + 0, + 0, // Skip to: 6701 + /* 6502 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6505 */ MCD_OPC_FilterValue, + 233, + 3, + 190, + 0, + 0, // Skip to: 6701 + /* 6511 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6528 + /* 6516 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6528 + /* 6523 */ MCD_OPC_Decode, + 169, + 21, + 183, + 2, // Opcode: VLD4DUPd32 + /* 6528 */ MCD_OPC_CheckPredicate, + 26, + 168, + 0, + 0, // Skip to: 6701 + /* 6533 */ MCD_OPC_Decode, + 172, + 21, + 183, + 2, // Opcode: VLD4DUPd32_UPD + /* 6538 */ MCD_OPC_FilterValue, + 1, + 158, + 0, + 0, // Skip to: 6701 + /* 6543 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6546 */ MCD_OPC_FilterValue, + 0, + 101, + 0, + 0, // Skip to: 6652 + /* 6551 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6554 */ MCD_OPC_FilterValue, + 0, + 44, + 0, + 0, // Skip to: 6603 + /* 6559 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6562 */ MCD_OPC_FilterValue, + 2, + 134, + 0, + 0, // Skip to: 6701 + /* 6567 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6570 */ MCD_OPC_FilterValue, + 233, + 3, + 125, + 0, + 0, // Skip to: 6701 + /* 6576 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6593 + /* 6581 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6593 + /* 6588 */ MCD_OPC_Decode, + 187, + 21, + 183, + 2, // Opcode: VLD4DUPq8 + /* 6593 */ MCD_OPC_CheckPredicate, + 26, + 103, + 0, + 0, // Skip to: 6701 + /* 6598 */ MCD_OPC_Decode, + 191, + 21, + 183, + 2, // Opcode: VLD4DUPq8_UPD + /* 6603 */ MCD_OPC_FilterValue, + 1, + 93, + 0, + 0, // Skip to: 6701 + /* 6608 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6611 */ MCD_OPC_FilterValue, + 2, + 85, + 0, + 0, // Skip to: 6701 + /* 6616 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6619 */ MCD_OPC_FilterValue, + 233, + 3, + 76, + 0, + 0, // Skip to: 6701 + /* 6625 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6642 + /* 6630 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6642 + /* 6637 */ MCD_OPC_Decode, + 177, + 21, + 183, + 2, // Opcode: VLD4DUPq16 + /* 6642 */ MCD_OPC_CheckPredicate, + 26, + 54, + 0, + 0, // Skip to: 6701 + /* 6647 */ MCD_OPC_Decode, + 181, + 21, + 183, + 2, // Opcode: VLD4DUPq16_UPD + /* 6652 */ MCD_OPC_FilterValue, + 1, + 44, + 0, + 0, // Skip to: 6701 + /* 6657 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6660 */ MCD_OPC_FilterValue, + 2, + 36, + 0, + 0, // Skip to: 6701 + /* 6665 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6668 */ MCD_OPC_FilterValue, + 233, + 3, + 27, + 0, + 0, // Skip to: 6701 + /* 6674 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6691 + /* 6679 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6691 + /* 6686 */ MCD_OPC_Decode, + 182, + 21, + 183, + 2, // Opcode: VLD4DUPq32 + /* 6691 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 6701 + /* 6696 */ MCD_OPC_Decode, + 186, + 21, + 183, + 2, // Opcode: VLD4DUPq32_UPD + /* 6701 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumb16[] = { + /* 0 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 25 + /* 8 */ MCD_OPC_CheckPredicate, + 35, + 181, + 4, + 0, // Skip to: 1218 + /* 13 */ MCD_OPC_CheckField, + 6, + 6, + 0, + 174, + 4, + 0, // Skip to: 1218 + /* 20 */ MCD_OPC_Decode, + 165, + 34, + 184, + 2, // Opcode: tMOVSr + /* 25 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 47 + /* 30 */ MCD_OPC_CheckPredicate, + 35, + 159, + 4, + 0, // Skip to: 1218 + /* 35 */ MCD_OPC_CheckField, + 11, + 1, + 1, + 152, + 4, + 0, // Skip to: 1218 + /* 42 */ MCD_OPC_Decode, + 141, + 34, + 185, + 2, // Opcode: tCMPi8 + /* 47 */ MCD_OPC_FilterValue, + 4, + 3, + 1, + 0, // Skip to: 311 + /* 52 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 55 */ MCD_OPC_FilterValue, + 0, + 236, + 0, + 0, // Skip to: 296 + /* 60 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 63 */ MCD_OPC_FilterValue, + 2, + 48, + 0, + 0, // Skip to: 116 + /* 68 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 71 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 86 + /* 76 */ MCD_OPC_CheckPredicate, + 35, + 113, + 4, + 0, // Skip to: 1218 + /* 81 */ MCD_OPC_Decode, + 197, + 34, + 184, + 2, // Opcode: tTST + /* 86 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 101 + /* 91 */ MCD_OPC_CheckPredicate, + 35, + 98, + 4, + 0, // Skip to: 1218 + /* 96 */ MCD_OPC_Decode, + 142, + 34, + 184, + 2, // Opcode: tCMPr + /* 101 */ MCD_OPC_FilterValue, + 3, + 88, + 4, + 0, // Skip to: 1218 + /* 106 */ MCD_OPC_CheckPredicate, + 35, + 83, + 4, + 0, // Skip to: 1218 + /* 111 */ MCD_OPC_Decode, + 139, + 34, + 184, + 2, // Opcode: tCMNz + /* 116 */ MCD_OPC_FilterValue, + 4, + 51, + 0, + 0, // Skip to: 172 + /* 121 */ MCD_OPC_CheckPredicate, + 35, + 12, + 0, + 0, // Skip to: 138 + /* 126 */ MCD_OPC_CheckField, + 3, + 4, + 13, + 5, + 0, + 0, // Skip to: 138 + /* 133 */ MCD_OPC_Decode, + 246, + 33, + 186, + 2, // Opcode: tADDrSP + /* 138 */ MCD_OPC_CheckPredicate, + 35, + 19, + 0, + 0, // Skip to: 162 + /* 143 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 12, + 0, + 0, // Skip to: 162 + /* 150 */ MCD_OPC_CheckField, + 0, + 3, + 5, + 5, + 0, + 0, // Skip to: 162 + /* 157 */ MCD_OPC_Decode, + 250, + 33, + 186, + 2, // Opcode: tADDspr + /* 162 */ MCD_OPC_CheckPredicate, + 35, + 27, + 4, + 0, // Skip to: 1218 + /* 167 */ MCD_OPC_Decode, + 243, + 33, + 187, + 2, // Opcode: tADDhirr + /* 172 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 187 + /* 177 */ MCD_OPC_CheckPredicate, + 35, + 12, + 4, + 0, // Skip to: 1218 + /* 182 */ MCD_OPC_Decode, + 140, + 34, + 188, + 2, // Opcode: tCMPhir + /* 187 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 202 + /* 192 */ MCD_OPC_CheckPredicate, + 35, + 253, + 3, + 0, // Skip to: 1218 + /* 197 */ MCD_OPC_Decode, + 167, + 34, + 188, + 2, // Opcode: tMOVr + /* 202 */ MCD_OPC_FilterValue, + 7, + 243, + 3, + 0, // Skip to: 1218 + /* 207 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 210 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 248 + /* 215 */ MCD_OPC_CheckPredicate, + 36, + 15, + 0, + 0, // Skip to: 235 + /* 220 */ MCD_OPC_CheckField, + 2, + 1, + 1, + 8, + 0, + 0, // Skip to: 235 + /* 227 */ MCD_OPC_SoftFail, + 3, + 0, + /* 230 */ MCD_OPC_Decode, + 135, + 34, + 189, + 2, // Opcode: tBXNS + /* 235 */ MCD_OPC_CheckPredicate, + 35, + 210, + 3, + 0, // Skip to: 1218 + /* 240 */ MCD_OPC_SoftFail, + 7, + 0, + /* 243 */ MCD_OPC_Decode, + 134, + 34, + 189, + 2, // Opcode: tBX + /* 248 */ MCD_OPC_FilterValue, + 1, + 197, + 3, + 0, // Skip to: 1218 + /* 253 */ MCD_OPC_ExtractField, + 2, + 1, // Inst{2} ... + /* 256 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 278 + /* 261 */ MCD_OPC_CheckPredicate, + 37, + 184, + 3, + 0, // Skip to: 1218 + /* 266 */ MCD_OPC_CheckField, + 0, + 2, + 0, + 177, + 3, + 0, // Skip to: 1218 + /* 273 */ MCD_OPC_Decode, + 133, + 34, + 189, + 2, // Opcode: tBLXr + /* 278 */ MCD_OPC_FilterValue, + 1, + 167, + 3, + 0, // Skip to: 1218 + /* 283 */ MCD_OPC_CheckPredicate, + 36, + 162, + 3, + 0, // Skip to: 1218 + /* 288 */ MCD_OPC_SoftFail, + 3, + 0, + /* 291 */ MCD_OPC_Decode, + 131, + 34, + 190, + 2, // Opcode: tBLXNSr + /* 296 */ MCD_OPC_FilterValue, + 1, + 149, + 3, + 0, // Skip to: 1218 + /* 301 */ MCD_OPC_CheckPredicate, + 35, + 144, + 3, + 0, // Skip to: 1218 + /* 306 */ MCD_OPC_Decode, + 158, + 34, + 191, + 2, // Opcode: tLDRpci + /* 311 */ MCD_OPC_FilterValue, + 5, + 123, + 0, + 0, // Skip to: 439 + /* 316 */ MCD_OPC_ExtractField, + 9, + 3, // Inst{11-9} ... + /* 319 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 334 + /* 324 */ MCD_OPC_CheckPredicate, + 35, + 121, + 3, + 0, // Skip to: 1218 + /* 329 */ MCD_OPC_Decode, + 187, + 34, + 192, + 2, // Opcode: tSTRr + /* 334 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 349 + /* 339 */ MCD_OPC_CheckPredicate, + 35, + 106, + 3, + 0, // Skip to: 1218 + /* 344 */ MCD_OPC_Decode, + 185, + 34, + 192, + 2, // Opcode: tSTRHr + /* 349 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 364 + /* 354 */ MCD_OPC_CheckPredicate, + 35, + 91, + 3, + 0, // Skip to: 1218 + /* 359 */ MCD_OPC_Decode, + 183, + 34, + 192, + 2, // Opcode: tSTRBr + /* 364 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 379 + /* 369 */ MCD_OPC_CheckPredicate, + 35, + 76, + 3, + 0, // Skip to: 1218 + /* 374 */ MCD_OPC_Decode, + 155, + 34, + 192, + 2, // Opcode: tLDRSB + /* 379 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 394 + /* 384 */ MCD_OPC_CheckPredicate, + 35, + 61, + 3, + 0, // Skip to: 1218 + /* 389 */ MCD_OPC_Decode, + 159, + 34, + 192, + 2, // Opcode: tLDRr + /* 394 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 409 + /* 399 */ MCD_OPC_CheckPredicate, + 35, + 46, + 3, + 0, // Skip to: 1218 + /* 404 */ MCD_OPC_Decode, + 154, + 34, + 192, + 2, // Opcode: tLDRHr + /* 409 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 424 + /* 414 */ MCD_OPC_CheckPredicate, + 35, + 31, + 3, + 0, // Skip to: 1218 + /* 419 */ MCD_OPC_Decode, + 152, + 34, + 192, + 2, // Opcode: tLDRBr + /* 424 */ MCD_OPC_FilterValue, + 7, + 21, + 3, + 0, // Skip to: 1218 + /* 429 */ MCD_OPC_CheckPredicate, + 35, + 16, + 3, + 0, // Skip to: 1218 + /* 434 */ MCD_OPC_Decode, + 156, + 34, + 192, + 2, // Opcode: tLDRSH + /* 439 */ MCD_OPC_FilterValue, + 6, + 33, + 0, + 0, // Skip to: 477 + /* 444 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 447 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 462 + /* 452 */ MCD_OPC_CheckPredicate, + 35, + 249, + 2, + 0, // Skip to: 1218 + /* 457 */ MCD_OPC_Decode, + 186, + 34, + 193, + 2, // Opcode: tSTRi + /* 462 */ MCD_OPC_FilterValue, + 1, + 239, + 2, + 0, // Skip to: 1218 + /* 467 */ MCD_OPC_CheckPredicate, + 35, + 234, + 2, + 0, // Skip to: 1218 + /* 472 */ MCD_OPC_Decode, + 157, + 34, + 193, + 2, // Opcode: tLDRi + /* 477 */ MCD_OPC_FilterValue, + 7, + 33, + 0, + 0, // Skip to: 515 + /* 482 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 485 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 500 + /* 490 */ MCD_OPC_CheckPredicate, + 35, + 211, + 2, + 0, // Skip to: 1218 + /* 495 */ MCD_OPC_Decode, + 182, + 34, + 193, + 2, // Opcode: tSTRBi + /* 500 */ MCD_OPC_FilterValue, + 1, + 201, + 2, + 0, // Skip to: 1218 + /* 505 */ MCD_OPC_CheckPredicate, + 35, + 196, + 2, + 0, // Skip to: 1218 + /* 510 */ MCD_OPC_Decode, + 151, + 34, + 193, + 2, // Opcode: tLDRBi + /* 515 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 553 + /* 520 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 523 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 538 + /* 528 */ MCD_OPC_CheckPredicate, + 35, + 173, + 2, + 0, // Skip to: 1218 + /* 533 */ MCD_OPC_Decode, + 184, + 34, + 193, + 2, // Opcode: tSTRHi + /* 538 */ MCD_OPC_FilterValue, + 1, + 163, + 2, + 0, // Skip to: 1218 + /* 543 */ MCD_OPC_CheckPredicate, + 35, + 158, + 2, + 0, // Skip to: 1218 + /* 548 */ MCD_OPC_Decode, + 153, + 34, + 193, + 2, // Opcode: tLDRHi + /* 553 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 591 + /* 558 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 561 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 576 + /* 566 */ MCD_OPC_CheckPredicate, + 35, + 135, + 2, + 0, // Skip to: 1218 + /* 571 */ MCD_OPC_Decode, + 188, + 34, + 194, + 2, // Opcode: tSTRspi + /* 576 */ MCD_OPC_FilterValue, + 1, + 125, + 2, + 0, // Skip to: 1218 + /* 581 */ MCD_OPC_CheckPredicate, + 35, + 120, + 2, + 0, // Skip to: 1218 + /* 586 */ MCD_OPC_Decode, + 160, + 34, + 194, + 2, // Opcode: tLDRspi + /* 591 */ MCD_OPC_FilterValue, + 10, + 33, + 0, + 0, // Skip to: 629 + /* 596 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 599 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 614 + /* 604 */ MCD_OPC_CheckPredicate, + 35, + 97, + 2, + 0, // Skip to: 1218 + /* 609 */ MCD_OPC_Decode, + 251, + 33, + 195, + 2, // Opcode: tADR + /* 614 */ MCD_OPC_FilterValue, + 1, + 87, + 2, + 0, // Skip to: 1218 + /* 619 */ MCD_OPC_CheckPredicate, + 35, + 82, + 2, + 0, // Skip to: 1218 + /* 624 */ MCD_OPC_Decode, + 247, + 33, + 195, + 2, // Opcode: tADDrSPi + /* 629 */ MCD_OPC_FilterValue, + 11, + 187, + 1, + 0, // Skip to: 1077 + /* 634 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 637 */ MCD_OPC_FilterValue, + 0, + 148, + 0, + 0, // Skip to: 790 + /* 642 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 645 */ MCD_OPC_FilterValue, + 0, + 125, + 0, + 0, // Skip to: 775 + /* 650 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 653 */ MCD_OPC_FilterValue, + 0, + 56, + 0, + 0, // Skip to: 714 + /* 658 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 661 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 676 + /* 666 */ MCD_OPC_CheckPredicate, + 35, + 35, + 2, + 0, // Skip to: 1218 + /* 671 */ MCD_OPC_Decode, + 249, + 33, + 196, + 2, // Opcode: tADDspi + /* 676 */ MCD_OPC_FilterValue, + 1, + 25, + 2, + 0, // Skip to: 1218 + /* 681 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 684 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 699 + /* 689 */ MCD_OPC_CheckPredicate, + 38, + 12, + 2, + 0, // Skip to: 1218 + /* 694 */ MCD_OPC_Decode, + 195, + 34, + 184, + 2, // Opcode: tSXTH + /* 699 */ MCD_OPC_FilterValue, + 1, + 2, + 2, + 0, // Skip to: 1218 + /* 704 */ MCD_OPC_CheckPredicate, + 38, + 253, + 1, + 0, // Skip to: 1218 + /* 709 */ MCD_OPC_Decode, + 194, + 34, + 184, + 2, // Opcode: tSXTB + /* 714 */ MCD_OPC_FilterValue, + 1, + 243, + 1, + 0, // Skip to: 1218 + /* 719 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 722 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 737 + /* 727 */ MCD_OPC_CheckPredicate, + 35, + 230, + 1, + 0, // Skip to: 1218 + /* 732 */ MCD_OPC_Decode, + 192, + 34, + 196, + 2, // Opcode: tSUBspi + /* 737 */ MCD_OPC_FilterValue, + 1, + 220, + 1, + 0, // Skip to: 1218 + /* 742 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 745 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 760 + /* 750 */ MCD_OPC_CheckPredicate, + 38, + 207, + 1, + 0, // Skip to: 1218 + /* 755 */ MCD_OPC_Decode, + 200, + 34, + 184, + 2, // Opcode: tUXTH + /* 760 */ MCD_OPC_FilterValue, + 1, + 197, + 1, + 0, // Skip to: 1218 + /* 765 */ MCD_OPC_CheckPredicate, + 38, + 192, + 1, + 0, // Skip to: 1218 + /* 770 */ MCD_OPC_Decode, + 199, + 34, + 184, + 2, // Opcode: tUXTB + /* 775 */ MCD_OPC_FilterValue, + 1, + 182, + 1, + 0, // Skip to: 1218 + /* 780 */ MCD_OPC_CheckPredicate, + 39, + 177, + 1, + 0, // Skip to: 1218 + /* 785 */ MCD_OPC_Decode, + 138, + 34, + 197, + 2, // Opcode: tCBZ + /* 790 */ MCD_OPC_FilterValue, + 1, + 95, + 0, + 0, // Skip to: 890 + /* 795 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 798 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 813 + /* 803 */ MCD_OPC_CheckPredicate, + 35, + 154, + 1, + 0, // Skip to: 1218 + /* 808 */ MCD_OPC_Decode, + 173, + 34, + 198, + 2, // Opcode: tPUSH + /* 813 */ MCD_OPC_FilterValue, + 1, + 144, + 1, + 0, // Skip to: 1218 + /* 818 */ MCD_OPC_ExtractField, + 5, + 4, // Inst{8-5} ... + /* 821 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 839 + /* 826 */ MCD_OPC_CheckPredicate, + 40, + 131, + 1, + 0, // Skip to: 1218 + /* 831 */ MCD_OPC_SoftFail, + 7, + 16, + /* 834 */ MCD_OPC_Decode, + 203, + 32, + 199, + 2, // Opcode: t2SETPAN + /* 839 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 868 + /* 844 */ MCD_OPC_CheckPredicate, + 41, + 113, + 1, + 0, // Skip to: 1218 + /* 849 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 106, + 1, + 0, // Skip to: 1218 + /* 856 */ MCD_OPC_CheckField, + 0, + 3, + 0, + 99, + 1, + 0, // Skip to: 1218 + /* 863 */ MCD_OPC_Decode, + 180, + 34, + 199, + 2, // Opcode: tSETEND + /* 868 */ MCD_OPC_FilterValue, + 3, + 89, + 1, + 0, // Skip to: 1218 + /* 873 */ MCD_OPC_CheckPredicate, + 35, + 84, + 1, + 0, // Skip to: 1218 + /* 878 */ MCD_OPC_CheckField, + 3, + 1, + 0, + 77, + 1, + 0, // Skip to: 1218 + /* 885 */ MCD_OPC_Decode, + 143, + 34, + 200, + 2, // Opcode: tCPS + /* 890 */ MCD_OPC_FilterValue, + 2, + 114, + 0, + 0, // Skip to: 1009 + /* 895 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 898 */ MCD_OPC_FilterValue, + 0, + 91, + 0, + 0, // Skip to: 994 + /* 903 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 906 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 928 + /* 911 */ MCD_OPC_CheckPredicate, + 38, + 46, + 1, + 0, // Skip to: 1218 + /* 916 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 39, + 1, + 0, // Skip to: 1218 + /* 923 */ MCD_OPC_Decode, + 174, + 34, + 184, + 2, // Opcode: tREV + /* 928 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 950 + /* 933 */ MCD_OPC_CheckPredicate, + 38, + 24, + 1, + 0, // Skip to: 1218 + /* 938 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 17, + 1, + 0, // Skip to: 1218 + /* 945 */ MCD_OPC_Decode, + 175, + 34, + 184, + 2, // Opcode: tREV16 + /* 950 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 972 + /* 955 */ MCD_OPC_CheckPredicate, + 42, + 2, + 1, + 0, // Skip to: 1218 + /* 960 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 251, + 0, + 0, // Skip to: 1218 + /* 967 */ MCD_OPC_Decode, + 146, + 34, + 201, + 2, // Opcode: tHLT + /* 972 */ MCD_OPC_FilterValue, + 3, + 241, + 0, + 0, // Skip to: 1218 + /* 977 */ MCD_OPC_CheckPredicate, + 38, + 236, + 0, + 0, // Skip to: 1218 + /* 982 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 229, + 0, + 0, // Skip to: 1218 + /* 989 */ MCD_OPC_Decode, + 176, + 34, + 184, + 2, // Opcode: tREVSH + /* 994 */ MCD_OPC_FilterValue, + 1, + 219, + 0, + 0, // Skip to: 1218 + /* 999 */ MCD_OPC_CheckPredicate, + 39, + 214, + 0, + 0, // Skip to: 1218 + /* 1004 */ MCD_OPC_Decode, + 137, + 34, + 197, + 2, // Opcode: tCBNZ + /* 1009 */ MCD_OPC_FilterValue, + 3, + 204, + 0, + 0, // Skip to: 1218 + /* 1014 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 1017 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1032 + /* 1022 */ MCD_OPC_CheckPredicate, + 35, + 191, + 0, + 0, // Skip to: 1218 + /* 1027 */ MCD_OPC_Decode, + 172, + 34, + 202, + 2, // Opcode: tPOP + /* 1032 */ MCD_OPC_FilterValue, + 1, + 181, + 0, + 0, // Skip to: 1218 + /* 1037 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 1040 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1055 + /* 1045 */ MCD_OPC_CheckPredicate, + 35, + 168, + 0, + 0, // Skip to: 1218 + /* 1050 */ MCD_OPC_Decode, + 129, + 34, + 203, + 2, // Opcode: tBKPT + /* 1055 */ MCD_OPC_FilterValue, + 1, + 158, + 0, + 0, // Skip to: 1218 + /* 1060 */ MCD_OPC_CheckPredicate, + 43, + 153, + 0, + 0, // Skip to: 1218 + /* 1065 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 146, + 0, + 0, // Skip to: 1218 + /* 1072 */ MCD_OPC_Decode, + 145, + 34, + 204, + 2, // Opcode: tHINT + /* 1077 */ MCD_OPC_FilterValue, + 12, + 33, + 0, + 0, // Skip to: 1115 + /* 1082 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 1085 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1100 + /* 1090 */ MCD_OPC_CheckPredicate, + 35, + 123, + 0, + 0, // Skip to: 1218 + /* 1095 */ MCD_OPC_Decode, + 181, + 34, + 205, + 2, // Opcode: tSTMIA_UPD + /* 1100 */ MCD_OPC_FilterValue, + 1, + 113, + 0, + 0, // Skip to: 1218 + /* 1105 */ MCD_OPC_CheckPredicate, + 35, + 108, + 0, + 0, // Skip to: 1218 + /* 1110 */ MCD_OPC_Decode, + 150, + 34, + 206, + 2, // Opcode: tLDMIA + /* 1115 */ MCD_OPC_FilterValue, + 13, + 76, + 0, + 0, // Skip to: 1196 + /* 1120 */ MCD_OPC_ExtractField, + 0, + 12, // Inst{11-0} ... + /* 1123 */ MCD_OPC_FilterValue, + 249, + 29, + 9, + 0, + 0, // Skip to: 1138 + /* 1129 */ MCD_OPC_CheckPredicate, + 35, + 19, + 0, + 0, // Skip to: 1153 + /* 1134 */ MCD_OPC_Decode, + 201, + 34, + 61, // Opcode: t__brkdiv0 + /* 1138 */ MCD_OPC_FilterValue, + 254, + 29, + 9, + 0, + 0, // Skip to: 1153 + /* 1144 */ MCD_OPC_CheckPredicate, + 35, + 4, + 0, + 0, // Skip to: 1153 + /* 1149 */ MCD_OPC_Decode, + 196, + 34, + 61, // Opcode: tTRAP + /* 1153 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 1156 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1171 + /* 1161 */ MCD_OPC_CheckPredicate, + 35, + 20, + 0, + 0, // Skip to: 1186 + /* 1166 */ MCD_OPC_Decode, + 198, + 34, + 203, + 2, // Opcode: tUDF + /* 1171 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1186 + /* 1176 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 1186 + /* 1181 */ MCD_OPC_Decode, + 193, + 34, + 203, + 2, // Opcode: tSVC + /* 1186 */ MCD_OPC_CheckPredicate, + 35, + 27, + 0, + 0, // Skip to: 1218 + /* 1191 */ MCD_OPC_Decode, + 136, + 34, + 207, + 2, // Opcode: tBcc + /* 1196 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 1218 + /* 1201 */ MCD_OPC_CheckPredicate, + 35, + 12, + 0, + 0, // Skip to: 1218 + /* 1206 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 5, + 0, + 0, // Skip to: 1218 + /* 1213 */ MCD_OPC_Decode, + 255, + 33, + 208, + 2, // Opcode: tB + /* 1218 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumb32[] = { + /* 0 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 39 + /* 8 */ MCD_OPC_CheckPredicate, + 44, + 55, + 0, + 0, // Skip to: 68 + /* 13 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 48, + 0, + 0, // Skip to: 68 + /* 20 */ MCD_OPC_CheckField, + 14, + 2, + 3, + 41, + 0, + 0, // Skip to: 68 + /* 27 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 34, + 0, + 0, // Skip to: 68 + /* 34 */ MCD_OPC_Decode, + 132, + 34, + 209, + 2, // Opcode: tBLXi + /* 39 */ MCD_OPC_FilterValue, + 1, + 24, + 0, + 0, // Skip to: 68 + /* 44 */ MCD_OPC_CheckPredicate, + 35, + 19, + 0, + 0, // Skip to: 68 + /* 49 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 12, + 0, + 0, // Skip to: 68 + /* 56 */ MCD_OPC_CheckField, + 14, + 2, + 3, + 5, + 0, + 0, // Skip to: 68 + /* 63 */ MCD_OPC_Decode, + 130, + 34, + 210, + 2, // Opcode: tBL + /* 68 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumb216[] = { + /* 0 */ MCD_OPC_CheckPredicate, + 45, + 13, + 0, + 0, // Skip to: 18 + /* 5 */ MCD_OPC_CheckField, + 8, + 8, + 191, + 1, + 5, + 0, + 0, // Skip to: 18 + /* 13 */ MCD_OPC_Decode, + 170, + 31, + 211, + 2, // Opcode: t2IT + /* 18 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumb232[] = { + /* 0 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 3 */ MCD_OPC_FilterValue, + 29, + 41, + 9, + 0, // Skip to: 2353 + /* 8 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 11, + 2, + 0, // Skip to: 539 + /* 16 */ MCD_OPC_ExtractField, + 23, + 4, // Inst{26-23} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 73 + /* 24 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 27 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 50 + /* 32 */ MCD_OPC_CheckPredicate, + 46, + 109, + 35, + 0, // Skip to: 9106 + /* 37 */ MCD_OPC_CheckField, + 5, + 15, + 128, + 220, + 1, + 100, + 35, + 0, // Skip to: 9106 + /* 46 */ MCD_OPC_Decode, + 248, + 32, + 85, // Opcode: t2SRSDB + /* 50 */ MCD_OPC_FilterValue, + 1, + 91, + 35, + 0, // Skip to: 9106 + /* 55 */ MCD_OPC_CheckPredicate, + 46, + 86, + 35, + 0, // Skip to: 9106 + /* 60 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 128, + 3, + 77, + 35, + 0, // Skip to: 9106 + /* 69 */ MCD_OPC_Decode, + 183, + 32, + 82, // Opcode: t2RFEDB + /* 73 */ MCD_OPC_FilterValue, + 1, + 71, + 0, + 0, // Skip to: 149 + /* 78 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 81 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 110 + /* 86 */ MCD_OPC_CheckPredicate, + 45, + 55, + 35, + 0, // Skip to: 9106 + /* 91 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 48, + 35, + 0, // Skip to: 9106 + /* 98 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 41, + 35, + 0, // Skip to: 9106 + /* 105 */ MCD_OPC_Decode, + 154, + 33, + 212, + 2, // Opcode: t2STMIA + /* 110 */ MCD_OPC_FilterValue, + 1, + 31, + 35, + 0, // Skip to: 9106 + /* 115 */ MCD_OPC_CheckPredicate, + 47, + 19, + 0, + 0, // Skip to: 139 + /* 120 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 12, + 0, + 0, // Skip to: 139 + /* 127 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 5, + 0, + 0, // Skip to: 139 + /* 134 */ MCD_OPC_Decode, + 136, + 31, + 213, + 2, // Opcode: t2CLRM + /* 139 */ MCD_OPC_CheckPredicate, + 45, + 2, + 35, + 0, // Skip to: 9106 + /* 144 */ MCD_OPC_Decode, + 198, + 31, + 214, + 2, // Opcode: t2LDMIA + /* 149 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 201 + /* 154 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 157 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 186 + /* 162 */ MCD_OPC_CheckPredicate, + 45, + 235, + 34, + 0, // Skip to: 9106 + /* 167 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 228, + 34, + 0, // Skip to: 9106 + /* 174 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 221, + 34, + 0, // Skip to: 9106 + /* 181 */ MCD_OPC_Decode, + 152, + 33, + 212, + 2, // Opcode: t2STMDB + /* 186 */ MCD_OPC_FilterValue, + 1, + 211, + 34, + 0, // Skip to: 9106 + /* 191 */ MCD_OPC_CheckPredicate, + 45, + 206, + 34, + 0, // Skip to: 9106 + /* 196 */ MCD_OPC_Decode, + 196, + 31, + 214, + 2, // Opcode: t2LDMDB + /* 201 */ MCD_OPC_FilterValue, + 3, + 49, + 0, + 0, // Skip to: 255 + /* 206 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 209 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 232 + /* 214 */ MCD_OPC_CheckPredicate, + 46, + 183, + 34, + 0, // Skip to: 9106 + /* 219 */ MCD_OPC_CheckField, + 5, + 15, + 128, + 220, + 1, + 174, + 34, + 0, // Skip to: 9106 + /* 228 */ MCD_OPC_Decode, + 250, + 32, + 85, // Opcode: t2SRSIA + /* 232 */ MCD_OPC_FilterValue, + 1, + 165, + 34, + 0, // Skip to: 9106 + /* 237 */ MCD_OPC_CheckPredicate, + 46, + 160, + 34, + 0, // Skip to: 9106 + /* 242 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 128, + 3, + 151, + 34, + 0, // Skip to: 9106 + /* 251 */ MCD_OPC_Decode, + 185, + 32, + 82, // Opcode: t2RFEIA + /* 255 */ MCD_OPC_FilterValue, + 4, + 93, + 0, + 0, // Skip to: 353 + /* 260 */ MCD_OPC_CheckPredicate, + 45, + 20, + 0, + 0, // Skip to: 285 + /* 265 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 13, + 0, + 0, // Skip to: 285 + /* 272 */ MCD_OPC_CheckField, + 4, + 11, + 240, + 1, + 5, + 0, + 0, // Skip to: 285 + /* 280 */ MCD_OPC_Decode, + 201, + 33, + 215, + 2, // Opcode: t2TSTrr + /* 285 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 309 + /* 290 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 0, + 0, // Skip to: 309 + /* 297 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 309 + /* 304 */ MCD_OPC_Decode, + 202, + 33, + 216, + 2, // Opcode: t2TSTrs + /* 309 */ MCD_OPC_CheckPredicate, + 45, + 24, + 0, + 0, // Skip to: 338 + /* 314 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 17, + 0, + 0, // Skip to: 338 + /* 321 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 10, + 0, + 0, // Skip to: 338 + /* 328 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 333 */ MCD_OPC_Decode, + 240, + 30, + 217, + 2, // Opcode: t2ANDrr + /* 338 */ MCD_OPC_CheckPredicate, + 45, + 59, + 34, + 0, // Skip to: 9106 + /* 343 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 348 */ MCD_OPC_Decode, + 241, + 30, + 218, + 2, // Opcode: t2ANDrs + /* 353 */ MCD_OPC_FilterValue, + 5, + 93, + 0, + 0, // Skip to: 451 + /* 358 */ MCD_OPC_CheckPredicate, + 45, + 20, + 0, + 0, // Skip to: 383 + /* 363 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 13, + 0, + 0, // Skip to: 383 + /* 370 */ MCD_OPC_CheckField, + 4, + 11, + 240, + 1, + 5, + 0, + 0, // Skip to: 383 + /* 378 */ MCD_OPC_Decode, + 197, + 33, + 215, + 2, // Opcode: t2TEQrr + /* 383 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 407 + /* 388 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 0, + 0, // Skip to: 407 + /* 395 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 407 + /* 402 */ MCD_OPC_Decode, + 198, + 33, + 216, + 2, // Opcode: t2TEQrs + /* 407 */ MCD_OPC_CheckPredicate, + 45, + 24, + 0, + 0, // Skip to: 436 + /* 412 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 17, + 0, + 0, // Skip to: 436 + /* 419 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 10, + 0, + 0, // Skip to: 436 + /* 426 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 431 */ MCD_OPC_Decode, + 165, + 31, + 217, + 2, // Opcode: t2EORrr + /* 436 */ MCD_OPC_CheckPredicate, + 45, + 217, + 33, + 0, // Skip to: 9106 + /* 441 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 446 */ MCD_OPC_Decode, + 166, + 31, + 218, + 2, // Opcode: t2EORrs + /* 451 */ MCD_OPC_FilterValue, + 6, + 202, + 33, + 0, // Skip to: 9106 + /* 456 */ MCD_OPC_CheckPredicate, + 45, + 20, + 0, + 0, // Skip to: 481 + /* 461 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 13, + 0, + 0, // Skip to: 481 + /* 468 */ MCD_OPC_CheckField, + 4, + 11, + 240, + 1, + 5, + 0, + 0, // Skip to: 481 + /* 476 */ MCD_OPC_Decode, + 139, + 31, + 219, + 2, // Opcode: t2CMNzrr + /* 481 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 505 + /* 486 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 0, + 0, // Skip to: 505 + /* 493 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 505 + /* 500 */ MCD_OPC_Decode, + 140, + 31, + 220, + 2, // Opcode: t2CMNzrs + /* 505 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 529 + /* 510 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 12, + 0, + 0, // Skip to: 529 + /* 517 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 5, + 0, + 0, // Skip to: 529 + /* 524 */ MCD_OPC_Decode, + 234, + 30, + 221, + 2, // Opcode: t2ADDrr + /* 529 */ MCD_OPC_CheckPredicate, + 45, + 124, + 33, + 0, // Skip to: 9106 + /* 534 */ MCD_OPC_Decode, + 235, + 30, + 222, + 2, // Opcode: t2ADDrs + /* 539 */ MCD_OPC_FilterValue, + 1, + 96, + 1, + 0, // Skip to: 896 + /* 544 */ MCD_OPC_ExtractField, + 23, + 4, // Inst{26-23} ... + /* 547 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 601 + /* 552 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 555 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 578 + /* 560 */ MCD_OPC_CheckPredicate, + 46, + 93, + 33, + 0, // Skip to: 9106 + /* 565 */ MCD_OPC_CheckField, + 5, + 15, + 128, + 220, + 1, + 84, + 33, + 0, // Skip to: 9106 + /* 574 */ MCD_OPC_Decode, + 249, + 32, + 85, // Opcode: t2SRSDB_UPD + /* 578 */ MCD_OPC_FilterValue, + 1, + 75, + 33, + 0, // Skip to: 9106 + /* 583 */ MCD_OPC_CheckPredicate, + 46, + 70, + 33, + 0, // Skip to: 9106 + /* 588 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 128, + 3, + 61, + 33, + 0, // Skip to: 9106 + /* 597 */ MCD_OPC_Decode, + 184, + 32, + 82, // Opcode: t2RFEDBW + /* 601 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 653 + /* 606 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 609 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 638 + /* 614 */ MCD_OPC_CheckPredicate, + 45, + 39, + 33, + 0, // Skip to: 9106 + /* 619 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 32, + 33, + 0, // Skip to: 9106 + /* 626 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 25, + 33, + 0, // Skip to: 9106 + /* 633 */ MCD_OPC_Decode, + 155, + 33, + 223, + 2, // Opcode: t2STMIA_UPD + /* 638 */ MCD_OPC_FilterValue, + 1, + 15, + 33, + 0, // Skip to: 9106 + /* 643 */ MCD_OPC_CheckPredicate, + 45, + 10, + 33, + 0, // Skip to: 9106 + /* 648 */ MCD_OPC_Decode, + 199, + 31, + 224, + 2, // Opcode: t2LDMIA_UPD + /* 653 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 705 + /* 658 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 661 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 690 + /* 666 */ MCD_OPC_CheckPredicate, + 45, + 243, + 32, + 0, // Skip to: 9106 + /* 671 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 236, + 32, + 0, // Skip to: 9106 + /* 678 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 229, + 32, + 0, // Skip to: 9106 + /* 685 */ MCD_OPC_Decode, + 153, + 33, + 223, + 2, // Opcode: t2STMDB_UPD + /* 690 */ MCD_OPC_FilterValue, + 1, + 219, + 32, + 0, // Skip to: 9106 + /* 695 */ MCD_OPC_CheckPredicate, + 45, + 214, + 32, + 0, // Skip to: 9106 + /* 700 */ MCD_OPC_Decode, + 197, + 31, + 224, + 2, // Opcode: t2LDMDB_UPD + /* 705 */ MCD_OPC_FilterValue, + 3, + 49, + 0, + 0, // Skip to: 759 + /* 710 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 713 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 736 + /* 718 */ MCD_OPC_CheckPredicate, + 46, + 191, + 32, + 0, // Skip to: 9106 + /* 723 */ MCD_OPC_CheckField, + 5, + 15, + 128, + 220, + 1, + 182, + 32, + 0, // Skip to: 9106 + /* 732 */ MCD_OPC_Decode, + 251, + 32, + 85, // Opcode: t2SRSIA_UPD + /* 736 */ MCD_OPC_FilterValue, + 1, + 173, + 32, + 0, // Skip to: 9106 + /* 741 */ MCD_OPC_CheckPredicate, + 46, + 168, + 32, + 0, // Skip to: 9106 + /* 746 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 128, + 3, + 159, + 32, + 0, // Skip to: 9106 + /* 755 */ MCD_OPC_Decode, + 186, + 32, + 82, // Opcode: t2RFEIAW + /* 759 */ MCD_OPC_FilterValue, + 4, + 44, + 0, + 0, // Skip to: 808 + /* 764 */ MCD_OPC_CheckPredicate, + 45, + 24, + 0, + 0, // Skip to: 793 + /* 769 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 17, + 0, + 0, // Skip to: 793 + /* 776 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 10, + 0, + 0, // Skip to: 793 + /* 783 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 788 */ MCD_OPC_Decode, + 255, + 30, + 217, + 2, // Opcode: t2BICrr + /* 793 */ MCD_OPC_CheckPredicate, + 45, + 116, + 32, + 0, // Skip to: 9106 + /* 798 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 803 */ MCD_OPC_Decode, + 128, + 31, + 218, + 2, // Opcode: t2BICrs + /* 808 */ MCD_OPC_FilterValue, + 7, + 101, + 32, + 0, // Skip to: 9106 + /* 813 */ MCD_OPC_CheckPredicate, + 45, + 20, + 0, + 0, // Skip to: 838 + /* 818 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 13, + 0, + 0, // Skip to: 838 + /* 825 */ MCD_OPC_CheckField, + 4, + 11, + 240, + 1, + 5, + 0, + 0, // Skip to: 838 + /* 833 */ MCD_OPC_Decode, + 142, + 31, + 219, + 2, // Opcode: t2CMPrr + /* 838 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 862 + /* 843 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 0, + 0, // Skip to: 862 + /* 850 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 862 + /* 857 */ MCD_OPC_Decode, + 143, + 31, + 220, + 2, // Opcode: t2CMPrs + /* 862 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 886 + /* 867 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 12, + 0, + 0, // Skip to: 886 + /* 874 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 5, + 0, + 0, // Skip to: 886 + /* 881 */ MCD_OPC_Decode, + 184, + 33, + 221, + 2, // Opcode: t2SUBrr + /* 886 */ MCD_OPC_CheckPredicate, + 45, + 23, + 32, + 0, // Skip to: 9106 + /* 891 */ MCD_OPC_Decode, + 185, + 33, + 222, + 2, // Opcode: t2SUBrs + /* 896 */ MCD_OPC_FilterValue, + 2, + 179, + 4, + 0, // Skip to: 2104 + /* 901 */ MCD_OPC_ExtractField, + 24, + 3, // Inst{26-24} ... + /* 904 */ MCD_OPC_FilterValue, + 0, + 212, + 2, + 0, // Skip to: 1633 + /* 909 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 912 */ MCD_OPC_FilterValue, + 0, + 100, + 1, + 0, // Skip to: 1273 + /* 917 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 920 */ MCD_OPC_FilterValue, + 0, + 113, + 0, + 0, // Skip to: 1038 + /* 925 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 928 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 953 + /* 933 */ MCD_OPC_CheckPredicate, + 36, + 90, + 0, + 0, // Skip to: 1028 + /* 938 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 83, + 0, + 0, // Skip to: 1028 + /* 945 */ MCD_OPC_SoftFail, + 63, + 0, + /* 948 */ MCD_OPC_Decode, + 203, + 33, + 225, + 2, // Opcode: t2TT + /* 953 */ MCD_OPC_FilterValue, + 1, + 20, + 0, + 0, // Skip to: 978 + /* 958 */ MCD_OPC_CheckPredicate, + 36, + 65, + 0, + 0, // Skip to: 1028 + /* 963 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 58, + 0, + 0, // Skip to: 1028 + /* 970 */ MCD_OPC_SoftFail, + 63, + 0, + /* 973 */ MCD_OPC_Decode, + 206, + 33, + 225, + 2, // Opcode: t2TTT + /* 978 */ MCD_OPC_FilterValue, + 2, + 20, + 0, + 0, // Skip to: 1003 + /* 983 */ MCD_OPC_CheckPredicate, + 36, + 40, + 0, + 0, // Skip to: 1028 + /* 988 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 33, + 0, + 0, // Skip to: 1028 + /* 995 */ MCD_OPC_SoftFail, + 63, + 0, + /* 998 */ MCD_OPC_Decode, + 204, + 33, + 225, + 2, // Opcode: t2TTA + /* 1003 */ MCD_OPC_FilterValue, + 3, + 20, + 0, + 0, // Skip to: 1028 + /* 1008 */ MCD_OPC_CheckPredicate, + 36, + 15, + 0, + 0, // Skip to: 1028 + /* 1013 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 8, + 0, + 0, // Skip to: 1028 + /* 1020 */ MCD_OPC_SoftFail, + 63, + 0, + /* 1023 */ MCD_OPC_Decode, + 205, + 33, + 225, + 2, // Opcode: t2TTAT + /* 1028 */ MCD_OPC_CheckPredicate, + 39, + 137, + 31, + 0, // Skip to: 9106 + /* 1033 */ MCD_OPC_Decode, + 165, + 33, + 226, + 2, // Opcode: t2STREX + /* 1038 */ MCD_OPC_FilterValue, + 1, + 127, + 31, + 0, // Skip to: 9106 + /* 1043 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 1046 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 1068 + /* 1051 */ MCD_OPC_CheckPredicate, + 39, + 114, + 31, + 0, // Skip to: 9106 + /* 1056 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 107, + 31, + 0, // Skip to: 9106 + /* 1063 */ MCD_OPC_Decode, + 166, + 33, + 227, + 2, // Opcode: t2STREXB + /* 1068 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 1090 + /* 1073 */ MCD_OPC_CheckPredicate, + 39, + 92, + 31, + 0, // Skip to: 9106 + /* 1078 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 85, + 31, + 0, // Skip to: 9106 + /* 1085 */ MCD_OPC_Decode, + 168, + 33, + 227, + 2, // Opcode: t2STREXH + /* 1090 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 1105 + /* 1095 */ MCD_OPC_CheckPredicate, + 46, + 70, + 31, + 0, // Skip to: 9106 + /* 1100 */ MCD_OPC_Decode, + 167, + 33, + 228, + 2, // Opcode: t2STREXD + /* 1105 */ MCD_OPC_FilterValue, + 8, + 24, + 0, + 0, // Skip to: 1134 + /* 1110 */ MCD_OPC_CheckPredicate, + 48, + 55, + 31, + 0, // Skip to: 9106 + /* 1115 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 48, + 31, + 0, // Skip to: 9106 + /* 1122 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 41, + 31, + 0, // Skip to: 9106 + /* 1129 */ MCD_OPC_Decode, + 146, + 33, + 229, + 2, // Opcode: t2STLB + /* 1134 */ MCD_OPC_FilterValue, + 9, + 24, + 0, + 0, // Skip to: 1163 + /* 1139 */ MCD_OPC_CheckPredicate, + 48, + 26, + 31, + 0, // Skip to: 9106 + /* 1144 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 19, + 31, + 0, // Skip to: 9106 + /* 1151 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 12, + 31, + 0, // Skip to: 9106 + /* 1158 */ MCD_OPC_Decode, + 151, + 33, + 229, + 2, // Opcode: t2STLH + /* 1163 */ MCD_OPC_FilterValue, + 10, + 24, + 0, + 0, // Skip to: 1192 + /* 1168 */ MCD_OPC_CheckPredicate, + 48, + 253, + 30, + 0, // Skip to: 9106 + /* 1173 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 246, + 30, + 0, // Skip to: 9106 + /* 1180 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 239, + 30, + 0, // Skip to: 9106 + /* 1187 */ MCD_OPC_Decode, + 145, + 33, + 229, + 2, // Opcode: t2STL + /* 1192 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 1214 + /* 1197 */ MCD_OPC_CheckPredicate, + 49, + 224, + 30, + 0, // Skip to: 9106 + /* 1202 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 217, + 30, + 0, // Skip to: 9106 + /* 1209 */ MCD_OPC_Decode, + 148, + 33, + 227, + 2, // Opcode: t2STLEXB + /* 1214 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 1236 + /* 1219 */ MCD_OPC_CheckPredicate, + 49, + 202, + 30, + 0, // Skip to: 9106 + /* 1224 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 195, + 30, + 0, // Skip to: 9106 + /* 1231 */ MCD_OPC_Decode, + 150, + 33, + 227, + 2, // Opcode: t2STLEXH + /* 1236 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 1258 + /* 1241 */ MCD_OPC_CheckPredicate, + 49, + 180, + 30, + 0, // Skip to: 9106 + /* 1246 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 173, + 30, + 0, // Skip to: 9106 + /* 1253 */ MCD_OPC_Decode, + 147, + 33, + 227, + 2, // Opcode: t2STLEX + /* 1258 */ MCD_OPC_FilterValue, + 15, + 163, + 30, + 0, // Skip to: 9106 + /* 1263 */ MCD_OPC_CheckPredicate, + 50, + 158, + 30, + 0, // Skip to: 9106 + /* 1268 */ MCD_OPC_Decode, + 149, + 33, + 228, + 2, // Opcode: t2STLEXD + /* 1273 */ MCD_OPC_FilterValue, + 1, + 148, + 30, + 0, // Skip to: 9106 + /* 1278 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1281 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1303 + /* 1286 */ MCD_OPC_CheckPredicate, + 39, + 135, + 30, + 0, // Skip to: 9106 + /* 1291 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 128, + 30, + 0, // Skip to: 9106 + /* 1298 */ MCD_OPC_Decode, + 210, + 31, + 230, + 2, // Opcode: t2LDREX + /* 1303 */ MCD_OPC_FilterValue, + 1, + 118, + 30, + 0, // Skip to: 9106 + /* 1308 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 1311 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 1334 + /* 1316 */ MCD_OPC_CheckPredicate, + 45, + 105, + 30, + 0, // Skip to: 9106 + /* 1321 */ MCD_OPC_CheckField, + 8, + 8, + 240, + 1, + 97, + 30, + 0, // Skip to: 9106 + /* 1329 */ MCD_OPC_Decode, + 194, + 33, + 231, + 2, // Opcode: t2TBB + /* 1334 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 1357 + /* 1339 */ MCD_OPC_CheckPredicate, + 45, + 82, + 30, + 0, // Skip to: 9106 + /* 1344 */ MCD_OPC_CheckField, + 8, + 8, + 240, + 1, + 74, + 30, + 0, // Skip to: 9106 + /* 1352 */ MCD_OPC_Decode, + 195, + 33, + 231, + 2, // Opcode: t2TBH + /* 1357 */ MCD_OPC_FilterValue, + 4, + 24, + 0, + 0, // Skip to: 1386 + /* 1362 */ MCD_OPC_CheckPredicate, + 39, + 59, + 30, + 0, // Skip to: 9106 + /* 1367 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 52, + 30, + 0, // Skip to: 9106 + /* 1374 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 45, + 30, + 0, // Skip to: 9106 + /* 1381 */ MCD_OPC_Decode, + 211, + 31, + 229, + 2, // Opcode: t2LDREXB + /* 1386 */ MCD_OPC_FilterValue, + 5, + 24, + 0, + 0, // Skip to: 1415 + /* 1391 */ MCD_OPC_CheckPredicate, + 39, + 30, + 30, + 0, // Skip to: 9106 + /* 1396 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 23, + 30, + 0, // Skip to: 9106 + /* 1403 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 16, + 30, + 0, // Skip to: 9106 + /* 1410 */ MCD_OPC_Decode, + 213, + 31, + 229, + 2, // Opcode: t2LDREXH + /* 1415 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 1437 + /* 1420 */ MCD_OPC_CheckPredicate, + 46, + 1, + 30, + 0, // Skip to: 9106 + /* 1425 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 250, + 29, + 0, // Skip to: 9106 + /* 1432 */ MCD_OPC_Decode, + 212, + 31, + 232, + 2, // Opcode: t2LDREXD + /* 1437 */ MCD_OPC_FilterValue, + 8, + 24, + 0, + 0, // Skip to: 1466 + /* 1442 */ MCD_OPC_CheckPredicate, + 48, + 235, + 29, + 0, // Skip to: 9106 + /* 1447 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 228, + 29, + 0, // Skip to: 9106 + /* 1454 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 221, + 29, + 0, // Skip to: 9106 + /* 1461 */ MCD_OPC_Decode, + 174, + 31, + 229, + 2, // Opcode: t2LDAB + /* 1466 */ MCD_OPC_FilterValue, + 9, + 24, + 0, + 0, // Skip to: 1495 + /* 1471 */ MCD_OPC_CheckPredicate, + 48, + 206, + 29, + 0, // Skip to: 9106 + /* 1476 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 199, + 29, + 0, // Skip to: 9106 + /* 1483 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 192, + 29, + 0, // Skip to: 9106 + /* 1490 */ MCD_OPC_Decode, + 179, + 31, + 229, + 2, // Opcode: t2LDAH + /* 1495 */ MCD_OPC_FilterValue, + 10, + 24, + 0, + 0, // Skip to: 1524 + /* 1500 */ MCD_OPC_CheckPredicate, + 48, + 177, + 29, + 0, // Skip to: 9106 + /* 1505 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 170, + 29, + 0, // Skip to: 9106 + /* 1512 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 163, + 29, + 0, // Skip to: 9106 + /* 1519 */ MCD_OPC_Decode, + 173, + 31, + 229, + 2, // Opcode: t2LDA + /* 1524 */ MCD_OPC_FilterValue, + 12, + 24, + 0, + 0, // Skip to: 1553 + /* 1529 */ MCD_OPC_CheckPredicate, + 49, + 148, + 29, + 0, // Skip to: 9106 + /* 1534 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 141, + 29, + 0, // Skip to: 9106 + /* 1541 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 134, + 29, + 0, // Skip to: 9106 + /* 1548 */ MCD_OPC_Decode, + 176, + 31, + 229, + 2, // Opcode: t2LDAEXB + /* 1553 */ MCD_OPC_FilterValue, + 13, + 24, + 0, + 0, // Skip to: 1582 + /* 1558 */ MCD_OPC_CheckPredicate, + 49, + 119, + 29, + 0, // Skip to: 9106 + /* 1563 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 112, + 29, + 0, // Skip to: 9106 + /* 1570 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 105, + 29, + 0, // Skip to: 9106 + /* 1577 */ MCD_OPC_Decode, + 178, + 31, + 229, + 2, // Opcode: t2LDAEXH + /* 1582 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 1611 + /* 1587 */ MCD_OPC_CheckPredicate, + 49, + 90, + 29, + 0, // Skip to: 9106 + /* 1592 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 83, + 29, + 0, // Skip to: 9106 + /* 1599 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 76, + 29, + 0, // Skip to: 9106 + /* 1606 */ MCD_OPC_Decode, + 175, + 31, + 229, + 2, // Opcode: t2LDAEX + /* 1611 */ MCD_OPC_FilterValue, + 15, + 66, + 29, + 0, // Skip to: 9106 + /* 1616 */ MCD_OPC_CheckPredicate, + 50, + 61, + 29, + 0, // Skip to: 9106 + /* 1621 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 54, + 29, + 0, // Skip to: 9106 + /* 1628 */ MCD_OPC_Decode, + 177, + 31, + 232, + 2, // Opcode: t2LDAEXD + /* 1633 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 1671 + /* 1638 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1641 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1656 + /* 1646 */ MCD_OPC_CheckPredicate, + 45, + 31, + 29, + 0, // Skip to: 9106 + /* 1651 */ MCD_OPC_Decode, + 164, + 33, + 233, + 2, // Opcode: t2STRDi8 + /* 1656 */ MCD_OPC_FilterValue, + 1, + 21, + 29, + 0, // Skip to: 9106 + /* 1661 */ MCD_OPC_CheckPredicate, + 45, + 16, + 29, + 0, // Skip to: 9106 + /* 1666 */ MCD_OPC_Decode, + 209, + 31, + 233, + 2, // Opcode: t2LDRDi8 + /* 1671 */ MCD_OPC_FilterValue, + 2, + 86, + 1, + 0, // Skip to: 2018 + /* 1676 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1679 */ MCD_OPC_FilterValue, + 0, + 26, + 1, + 0, // Skip to: 1966 + /* 1684 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 1687 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 1727 + /* 1692 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 1695 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 1761 + /* 1700 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 1717 + /* 1705 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 1717 + /* 1712 */ MCD_OPC_Decode, + 129, + 32, + 234, + 2, // Opcode: t2MOVr + /* 1717 */ MCD_OPC_CheckPredicate, + 45, + 39, + 0, + 0, // Skip to: 1761 + /* 1722 */ MCD_OPC_Decode, + 151, + 32, + 217, + 2, // Opcode: t2ORRrr + /* 1727 */ MCD_OPC_FilterValue, + 3, + 29, + 0, + 0, // Skip to: 1761 + /* 1732 */ MCD_OPC_CheckPredicate, + 45, + 24, + 0, + 0, // Skip to: 1761 + /* 1737 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 17, + 0, + 0, // Skip to: 1761 + /* 1744 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 10, + 0, + 0, // Skip to: 1761 + /* 1751 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 1756 */ MCD_OPC_Decode, + 189, + 32, + 235, + 2, // Opcode: t2RRX + /* 1761 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 1764 */ MCD_OPC_FilterValue, + 0, + 101, + 0, + 0, // Skip to: 1870 + /* 1769 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 1772 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1794 + /* 1777 */ MCD_OPC_CheckPredicate, + 45, + 78, + 0, + 0, // Skip to: 1860 + /* 1782 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 71, + 0, + 0, // Skip to: 1860 + /* 1789 */ MCD_OPC_Decode, + 244, + 31, + 236, + 2, // Opcode: t2LSLri + /* 1794 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 1816 + /* 1799 */ MCD_OPC_CheckPredicate, + 45, + 56, + 0, + 0, // Skip to: 1860 + /* 1804 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 49, + 0, + 0, // Skip to: 1860 + /* 1811 */ MCD_OPC_Decode, + 246, + 31, + 236, + 2, // Opcode: t2LSRri + /* 1816 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 1838 + /* 1821 */ MCD_OPC_CheckPredicate, + 45, + 34, + 0, + 0, // Skip to: 1860 + /* 1826 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 27, + 0, + 0, // Skip to: 1860 + /* 1833 */ MCD_OPC_Decode, + 242, + 30, + 236, + 2, // Opcode: t2ASRri + /* 1838 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 1860 + /* 1843 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 1860 + /* 1848 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 1860 + /* 1855 */ MCD_OPC_Decode, + 187, + 32, + 236, + 2, // Opcode: t2RORri + /* 1860 */ MCD_OPC_CheckPredicate, + 45, + 73, + 28, + 0, // Skip to: 9106 + /* 1865 */ MCD_OPC_Decode, + 152, + 32, + 218, + 2, // Opcode: t2ORRrs + /* 1870 */ MCD_OPC_FilterValue, + 1, + 63, + 28, + 0, // Skip to: 9106 + /* 1875 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 1878 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1900 + /* 1883 */ MCD_OPC_CheckPredicate, + 47, + 50, + 28, + 0, // Skip to: 9106 + /* 1888 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 43, + 28, + 0, // Skip to: 9106 + /* 1895 */ MCD_OPC_Decode, + 153, + 31, + 237, + 2, // Opcode: t2CSEL + /* 1900 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 1922 + /* 1905 */ MCD_OPC_CheckPredicate, + 47, + 28, + 28, + 0, // Skip to: 9106 + /* 1910 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 21, + 28, + 0, // Skip to: 9106 + /* 1917 */ MCD_OPC_Decode, + 154, + 31, + 237, + 2, // Opcode: t2CSINC + /* 1922 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 1944 + /* 1927 */ MCD_OPC_CheckPredicate, + 47, + 6, + 28, + 0, // Skip to: 9106 + /* 1932 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 255, + 27, + 0, // Skip to: 9106 + /* 1939 */ MCD_OPC_Decode, + 155, + 31, + 237, + 2, // Opcode: t2CSINV + /* 1944 */ MCD_OPC_FilterValue, + 3, + 245, + 27, + 0, // Skip to: 9106 + /* 1949 */ MCD_OPC_CheckPredicate, + 47, + 240, + 27, + 0, // Skip to: 9106 + /* 1954 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 233, + 27, + 0, // Skip to: 9106 + /* 1961 */ MCD_OPC_Decode, + 156, + 31, + 237, + 2, // Opcode: t2CSNEG + /* 1966 */ MCD_OPC_FilterValue, + 1, + 223, + 27, + 0, // Skip to: 9106 + /* 1971 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 1974 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1996 + /* 1979 */ MCD_OPC_CheckPredicate, + 51, + 210, + 27, + 0, // Skip to: 9106 + /* 1984 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 203, + 27, + 0, // Skip to: 9106 + /* 1991 */ MCD_OPC_Decode, + 156, + 32, + 238, + 2, // Opcode: t2PKHBT + /* 1996 */ MCD_OPC_FilterValue, + 2, + 193, + 27, + 0, // Skip to: 9106 + /* 2001 */ MCD_OPC_CheckPredicate, + 51, + 188, + 27, + 0, // Skip to: 9106 + /* 2006 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 181, + 27, + 0, // Skip to: 9106 + /* 2013 */ MCD_OPC_Decode, + 157, + 32, + 238, + 2, // Opcode: t2PKHTB + /* 2018 */ MCD_OPC_FilterValue, + 3, + 171, + 27, + 0, // Skip to: 9106 + /* 2023 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 2026 */ MCD_OPC_FilterValue, + 0, + 34, + 0, + 0, // Skip to: 2065 + /* 2031 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 2055 + /* 2036 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 12, + 0, + 0, // Skip to: 2055 + /* 2043 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 5, + 0, + 0, // Skip to: 2055 + /* 2050 */ MCD_OPC_Decode, + 230, + 30, + 217, + 2, // Opcode: t2ADCrr + /* 2055 */ MCD_OPC_CheckPredicate, + 45, + 134, + 27, + 0, // Skip to: 9106 + /* 2060 */ MCD_OPC_Decode, + 231, + 30, + 218, + 2, // Opcode: t2ADCrs + /* 2065 */ MCD_OPC_FilterValue, + 1, + 124, + 27, + 0, // Skip to: 9106 + /* 2070 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 2094 + /* 2075 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 12, + 0, + 0, // Skip to: 2094 + /* 2082 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 5, + 0, + 0, // Skip to: 2094 + /* 2089 */ MCD_OPC_Decode, + 191, + 32, + 217, + 2, // Opcode: t2RSBrr + /* 2094 */ MCD_OPC_CheckPredicate, + 45, + 95, + 27, + 0, // Skip to: 9106 + /* 2099 */ MCD_OPC_Decode, + 192, + 32, + 218, + 2, // Opcode: t2RSBrs + /* 2104 */ MCD_OPC_FilterValue, + 3, + 85, + 27, + 0, // Skip to: 9106 + /* 2109 */ MCD_OPC_ExtractField, + 24, + 3, // Inst{26-24} ... + /* 2112 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 2150 + /* 2117 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2120 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2135 + /* 2125 */ MCD_OPC_CheckPredicate, + 45, + 64, + 27, + 0, // Skip to: 9106 + /* 2130 */ MCD_OPC_Decode, + 162, + 33, + 239, + 2, // Opcode: t2STRD_POST + /* 2135 */ MCD_OPC_FilterValue, + 1, + 54, + 27, + 0, // Skip to: 9106 + /* 2140 */ MCD_OPC_CheckPredicate, + 45, + 49, + 27, + 0, // Skip to: 9106 + /* 2145 */ MCD_OPC_Decode, + 207, + 31, + 240, + 2, // Opcode: t2LDRD_POST + /* 2150 */ MCD_OPC_FilterValue, + 1, + 58, + 0, + 0, // Skip to: 2213 + /* 2155 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2158 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2173 + /* 2163 */ MCD_OPC_CheckPredicate, + 45, + 26, + 27, + 0, // Skip to: 9106 + /* 2168 */ MCD_OPC_Decode, + 163, + 33, + 241, + 2, // Opcode: t2STRD_PRE + /* 2173 */ MCD_OPC_FilterValue, + 1, + 16, + 27, + 0, // Skip to: 9106 + /* 2178 */ MCD_OPC_CheckPredicate, + 52, + 20, + 0, + 0, // Skip to: 2203 + /* 2183 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 13, + 0, + 0, // Skip to: 2203 + /* 2190 */ MCD_OPC_CheckField, + 0, + 20, + 255, + 210, + 63, + 4, + 0, + 0, // Skip to: 2203 + /* 2199 */ MCD_OPC_Decode, + 204, + 32, + 61, // Opcode: t2SG + /* 2203 */ MCD_OPC_CheckPredicate, + 45, + 242, + 26, + 0, // Skip to: 9106 + /* 2208 */ MCD_OPC_Decode, + 208, + 31, + 242, + 2, // Opcode: t2LDRD_PRE + /* 2213 */ MCD_OPC_FilterValue, + 2, + 88, + 0, + 0, // Skip to: 2306 + /* 2218 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 2221 */ MCD_OPC_FilterValue, + 0, + 224, + 26, + 0, // Skip to: 9106 + /* 2226 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 2229 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 2274 + /* 2234 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 2237 */ MCD_OPC_FilterValue, + 0, + 32, + 0, + 0, // Skip to: 2274 + /* 2242 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 2259 + /* 2247 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 2259 + /* 2254 */ MCD_OPC_Decode, + 145, + 32, + 235, + 2, // Opcode: t2MVNr + /* 2259 */ MCD_OPC_CheckPredicate, + 45, + 10, + 0, + 0, // Skip to: 2274 + /* 2264 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 2269 */ MCD_OPC_Decode, + 148, + 32, + 217, + 2, // Opcode: t2ORNrr + /* 2274 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 2291 + /* 2279 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 2291 + /* 2286 */ MCD_OPC_Decode, + 146, + 32, + 243, + 2, // Opcode: t2MVNs + /* 2291 */ MCD_OPC_CheckPredicate, + 45, + 154, + 26, + 0, // Skip to: 9106 + /* 2296 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 2301 */ MCD_OPC_Decode, + 149, + 32, + 218, + 2, // Opcode: t2ORNrs + /* 2306 */ MCD_OPC_FilterValue, + 3, + 139, + 26, + 0, // Skip to: 9106 + /* 2311 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 2314 */ MCD_OPC_FilterValue, + 0, + 131, + 26, + 0, // Skip to: 9106 + /* 2319 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 2343 + /* 2324 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 12, + 0, + 0, // Skip to: 2343 + /* 2331 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 5, + 0, + 0, // Skip to: 2343 + /* 2338 */ MCD_OPC_Decode, + 198, + 32, + 217, + 2, // Opcode: t2SBCrr + /* 2343 */ MCD_OPC_CheckPredicate, + 45, + 102, + 26, + 0, // Skip to: 9106 + /* 2348 */ MCD_OPC_Decode, + 199, + 32, + 218, + 2, // Opcode: t2SBCrs + /* 2353 */ MCD_OPC_FilterValue, + 30, + 84, + 8, + 0, // Skip to: 4490 + /* 2358 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 2361 */ MCD_OPC_FilterValue, + 0, + 36, + 3, + 0, // Skip to: 3170 + /* 2366 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 2369 */ MCD_OPC_FilterValue, + 0, + 160, + 0, + 0, // Skip to: 2534 + /* 2374 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 2377 */ MCD_OPC_FilterValue, + 0, + 34, + 0, + 0, // Skip to: 2416 + /* 2382 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 2406 + /* 2387 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 0, + 0, // Skip to: 2406 + /* 2394 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 2406 + /* 2401 */ MCD_OPC_Decode, + 200, + 33, + 244, + 2, // Opcode: t2TSTri + /* 2406 */ MCD_OPC_CheckPredicate, + 45, + 39, + 26, + 0, // Skip to: 9106 + /* 2411 */ MCD_OPC_Decode, + 239, + 30, + 245, + 2, // Opcode: t2ANDri + /* 2416 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2431 + /* 2421 */ MCD_OPC_CheckPredicate, + 45, + 24, + 26, + 0, // Skip to: 9106 + /* 2426 */ MCD_OPC_Decode, + 254, + 30, + 245, + 2, // Opcode: t2BICri + /* 2431 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 2463 + /* 2436 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 2453 + /* 2441 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 2453 + /* 2448 */ MCD_OPC_Decode, + 255, + 31, + 246, + 2, // Opcode: t2MOVi + /* 2453 */ MCD_OPC_CheckPredicate, + 45, + 248, + 25, + 0, // Skip to: 9106 + /* 2458 */ MCD_OPC_Decode, + 150, + 32, + 245, + 2, // Opcode: t2ORRri + /* 2463 */ MCD_OPC_FilterValue, + 3, + 27, + 0, + 0, // Skip to: 2495 + /* 2468 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 2485 + /* 2473 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 2485 + /* 2480 */ MCD_OPC_Decode, + 144, + 32, + 246, + 2, // Opcode: t2MVNi + /* 2485 */ MCD_OPC_CheckPredicate, + 45, + 216, + 25, + 0, // Skip to: 9106 + /* 2490 */ MCD_OPC_Decode, + 147, + 32, + 245, + 2, // Opcode: t2ORNri + /* 2495 */ MCD_OPC_FilterValue, + 4, + 206, + 25, + 0, // Skip to: 9106 + /* 2500 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 2524 + /* 2505 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 0, + 0, // Skip to: 2524 + /* 2512 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 2524 + /* 2519 */ MCD_OPC_Decode, + 196, + 33, + 244, + 2, // Opcode: t2TEQri + /* 2524 */ MCD_OPC_CheckPredicate, + 45, + 177, + 25, + 0, // Skip to: 9106 + /* 2529 */ MCD_OPC_Decode, + 164, + 31, + 245, + 2, // Opcode: t2EORri + /* 2534 */ MCD_OPC_FilterValue, + 1, + 172, + 0, + 0, // Skip to: 2711 + /* 2539 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 2542 */ MCD_OPC_FilterValue, + 0, + 57, + 0, + 0, // Skip to: 2604 + /* 2547 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 2550 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 2572 + /* 2555 */ MCD_OPC_CheckPredicate, + 45, + 34, + 0, + 0, // Skip to: 2594 + /* 2560 */ MCD_OPC_CheckField, + 16, + 4, + 13, + 27, + 0, + 0, // Skip to: 2594 + /* 2567 */ MCD_OPC_Decode, + 236, + 30, + 247, + 2, // Opcode: t2ADDspImm + /* 2572 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2594 + /* 2577 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 2594 + /* 2582 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 5, + 0, + 0, // Skip to: 2594 + /* 2589 */ MCD_OPC_Decode, + 138, + 31, + 248, + 2, // Opcode: t2CMNri + /* 2594 */ MCD_OPC_CheckPredicate, + 45, + 107, + 25, + 0, // Skip to: 9106 + /* 2599 */ MCD_OPC_Decode, + 232, + 30, + 249, + 2, // Opcode: t2ADDri + /* 2604 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2619 + /* 2609 */ MCD_OPC_CheckPredicate, + 45, + 92, + 25, + 0, // Skip to: 9106 + /* 2614 */ MCD_OPC_Decode, + 229, + 30, + 245, + 2, // Opcode: t2ADCri + /* 2619 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 2634 + /* 2624 */ MCD_OPC_CheckPredicate, + 45, + 77, + 25, + 0, // Skip to: 9106 + /* 2629 */ MCD_OPC_Decode, + 197, + 32, + 245, + 2, // Opcode: t2SBCri + /* 2634 */ MCD_OPC_FilterValue, + 5, + 57, + 0, + 0, // Skip to: 2696 + /* 2639 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 2642 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 2664 + /* 2647 */ MCD_OPC_CheckPredicate, + 45, + 34, + 0, + 0, // Skip to: 2686 + /* 2652 */ MCD_OPC_CheckField, + 16, + 4, + 13, + 27, + 0, + 0, // Skip to: 2686 + /* 2659 */ MCD_OPC_Decode, + 186, + 33, + 247, + 2, // Opcode: t2SUBspImm + /* 2664 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2686 + /* 2669 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 2686 + /* 2674 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 5, + 0, + 0, // Skip to: 2686 + /* 2681 */ MCD_OPC_Decode, + 141, + 31, + 248, + 2, // Opcode: t2CMPri + /* 2686 */ MCD_OPC_CheckPredicate, + 45, + 15, + 25, + 0, // Skip to: 9106 + /* 2691 */ MCD_OPC_Decode, + 182, + 33, + 249, + 2, // Opcode: t2SUBri + /* 2696 */ MCD_OPC_FilterValue, + 6, + 5, + 25, + 0, // Skip to: 9106 + /* 2701 */ MCD_OPC_CheckPredicate, + 45, + 0, + 25, + 0, // Skip to: 9106 + /* 2706 */ MCD_OPC_Decode, + 190, + 32, + 245, + 2, // Opcode: t2RSBri + /* 2711 */ MCD_OPC_FilterValue, + 2, + 199, + 0, + 0, // Skip to: 2915 + /* 2716 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2719 */ MCD_OPC_FilterValue, + 0, + 139, + 0, + 0, // Skip to: 2863 + /* 2724 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2727 */ MCD_OPC_FilterValue, + 0, + 230, + 24, + 0, // Skip to: 9106 + /* 2732 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 2735 */ MCD_OPC_FilterValue, + 13, + 61, + 0, + 0, // Skip to: 2801 + /* 2740 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 2743 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 2772 + /* 2748 */ MCD_OPC_CheckPredicate, + 45, + 63, + 0, + 0, // Skip to: 2816 + /* 2753 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 56, + 0, + 0, // Skip to: 2816 + /* 2760 */ MCD_OPC_CheckField, + 8, + 4, + 13, + 49, + 0, + 0, // Skip to: 2816 + /* 2767 */ MCD_OPC_Decode, + 237, + 30, + 247, + 2, // Opcode: t2ADDspImm12 + /* 2772 */ MCD_OPC_FilterValue, + 1, + 39, + 0, + 0, // Skip to: 2816 + /* 2777 */ MCD_OPC_CheckPredicate, + 45, + 34, + 0, + 0, // Skip to: 2816 + /* 2782 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 27, + 0, + 0, // Skip to: 2816 + /* 2789 */ MCD_OPC_CheckField, + 8, + 4, + 13, + 20, + 0, + 0, // Skip to: 2816 + /* 2796 */ MCD_OPC_Decode, + 187, + 33, + 247, + 2, // Opcode: t2SUBspImm12 + /* 2801 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2816 + /* 2806 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 2816 + /* 2811 */ MCD_OPC_Decode, + 238, + 30, + 250, + 2, // Opcode: t2ADR + /* 2816 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 2819 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2841 + /* 2824 */ MCD_OPC_CheckPredicate, + 45, + 133, + 24, + 0, // Skip to: 9106 + /* 2829 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 126, + 24, + 0, // Skip to: 9106 + /* 2836 */ MCD_OPC_Decode, + 233, + 30, + 251, + 2, // Opcode: t2ADDri12 + /* 2841 */ MCD_OPC_FilterValue, + 1, + 116, + 24, + 0, // Skip to: 9106 + /* 2846 */ MCD_OPC_CheckPredicate, + 45, + 111, + 24, + 0, // Skip to: 9106 + /* 2851 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 104, + 24, + 0, // Skip to: 9106 + /* 2858 */ MCD_OPC_Decode, + 183, + 33, + 251, + 2, // Opcode: t2SUBri12 + /* 2863 */ MCD_OPC_FilterValue, + 1, + 94, + 24, + 0, // Skip to: 9106 + /* 2868 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 2871 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2893 + /* 2876 */ MCD_OPC_CheckPredicate, + 39, + 81, + 24, + 0, // Skip to: 9106 + /* 2881 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 74, + 24, + 0, // Skip to: 9106 + /* 2888 */ MCD_OPC_Decode, + 128, + 32, + 252, + 2, // Opcode: t2MOVi16 + /* 2893 */ MCD_OPC_FilterValue, + 1, + 64, + 24, + 0, // Skip to: 9106 + /* 2898 */ MCD_OPC_CheckPredicate, + 39, + 59, + 24, + 0, // Skip to: 9106 + /* 2903 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 52, + 24, + 0, // Skip to: 9106 + /* 2910 */ MCD_OPC_Decode, + 254, + 31, + 252, + 2, // Opcode: t2MOVTi16 + /* 2915 */ MCD_OPC_FilterValue, + 3, + 42, + 24, + 0, // Skip to: 9106 + /* 2920 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 2923 */ MCD_OPC_FilterValue, + 0, + 72, + 0, + 0, // Skip to: 3000 + /* 2928 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 2931 */ MCD_OPC_FilterValue, + 0, + 26, + 24, + 0, // Skip to: 9106 + /* 2936 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2939 */ MCD_OPC_FilterValue, + 0, + 18, + 24, + 0, // Skip to: 9106 + /* 2944 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 2947 */ MCD_OPC_FilterValue, + 0, + 10, + 24, + 0, // Skip to: 9106 + /* 2952 */ MCD_OPC_CheckPredicate, + 53, + 33, + 0, + 0, // Skip to: 2990 + /* 2957 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 26, + 0, + 0, // Skip to: 2990 + /* 2964 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 19, + 0, + 0, // Skip to: 2990 + /* 2971 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 12, + 0, + 0, // Skip to: 2990 + /* 2978 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 5, + 0, + 0, // Skip to: 2990 + /* 2985 */ MCD_OPC_Decode, + 253, + 32, + 253, + 2, // Opcode: t2SSAT16 + /* 2990 */ MCD_OPC_CheckPredicate, + 45, + 223, + 23, + 0, // Skip to: 9106 + /* 2995 */ MCD_OPC_Decode, + 252, + 32, + 254, + 2, // Opcode: t2SSAT + /* 3000 */ MCD_OPC_FilterValue, + 1, + 66, + 0, + 0, // Skip to: 3071 + /* 3005 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3008 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3023 + /* 3013 */ MCD_OPC_CheckPredicate, + 45, + 200, + 23, + 0, // Skip to: 9106 + /* 3018 */ MCD_OPC_Decode, + 200, + 32, + 255, + 2, // Opcode: t2SBFX + /* 3023 */ MCD_OPC_FilterValue, + 2, + 190, + 23, + 0, // Skip to: 9106 + /* 3028 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 3031 */ MCD_OPC_FilterValue, + 0, + 182, + 23, + 0, // Skip to: 9106 + /* 3036 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 3039 */ MCD_OPC_FilterValue, + 0, + 174, + 23, + 0, // Skip to: 9106 + /* 3044 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 3061 + /* 3049 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 3061 + /* 3056 */ MCD_OPC_Decode, + 247, + 30, + 128, + 3, // Opcode: t2BFC + /* 3061 */ MCD_OPC_CheckPredicate, + 45, + 152, + 23, + 0, // Skip to: 9106 + /* 3066 */ MCD_OPC_Decode, + 248, + 30, + 129, + 3, // Opcode: t2BFI + /* 3071 */ MCD_OPC_FilterValue, + 2, + 72, + 0, + 0, // Skip to: 3148 + /* 3076 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 3079 */ MCD_OPC_FilterValue, + 0, + 134, + 23, + 0, // Skip to: 9106 + /* 3084 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3087 */ MCD_OPC_FilterValue, + 0, + 126, + 23, + 0, // Skip to: 9106 + /* 3092 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 3095 */ MCD_OPC_FilterValue, + 0, + 118, + 23, + 0, // Skip to: 9106 + /* 3100 */ MCD_OPC_CheckPredicate, + 53, + 33, + 0, + 0, // Skip to: 3138 + /* 3105 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 26, + 0, + 0, // Skip to: 3138 + /* 3112 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 19, + 0, + 0, // Skip to: 3138 + /* 3119 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 12, + 0, + 0, // Skip to: 3138 + /* 3126 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 5, + 0, + 0, // Skip to: 3138 + /* 3133 */ MCD_OPC_Decode, + 231, + 33, + 253, + 2, // Opcode: t2USAT16 + /* 3138 */ MCD_OPC_CheckPredicate, + 45, + 75, + 23, + 0, // Skip to: 9106 + /* 3143 */ MCD_OPC_Decode, + 230, + 33, + 254, + 2, // Opcode: t2USAT + /* 3148 */ MCD_OPC_FilterValue, + 3, + 65, + 23, + 0, // Skip to: 9106 + /* 3153 */ MCD_OPC_CheckPredicate, + 45, + 60, + 23, + 0, // Skip to: 9106 + /* 3158 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 53, + 23, + 0, // Skip to: 9106 + /* 3165 */ MCD_OPC_Decode, + 210, + 33, + 255, + 2, // Opcode: t2UBFX + /* 3170 */ MCD_OPC_FilterValue, + 1, + 43, + 23, + 0, // Skip to: 9106 + /* 3175 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 3178 */ MCD_OPC_FilterValue, + 0, + 5, + 5, + 0, // Skip to: 4468 + /* 3183 */ MCD_OPC_ExtractField, + 14, + 1, // Inst{14} ... + /* 3186 */ MCD_OPC_FilterValue, + 0, + 62, + 3, + 0, // Skip to: 4021 + /* 3191 */ MCD_OPC_ExtractField, + 0, + 12, // Inst{11-0} ... + /* 3194 */ MCD_OPC_FilterValue, + 1, + 24, + 0, + 0, // Skip to: 3223 + /* 3199 */ MCD_OPC_CheckPredicate, + 54, + 166, + 0, + 0, // Skip to: 3370 + /* 3204 */ MCD_OPC_CheckField, + 16, + 11, + 143, + 15, + 158, + 0, + 0, // Skip to: 3370 + /* 3212 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 151, + 0, + 0, // Skip to: 3370 + /* 3219 */ MCD_OPC_Decode, + 158, + 31, + 61, // Opcode: t2DCPS1 + /* 3223 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 3252 + /* 3228 */ MCD_OPC_CheckPredicate, + 54, + 137, + 0, + 0, // Skip to: 3370 + /* 3233 */ MCD_OPC_CheckField, + 16, + 11, + 143, + 15, + 129, + 0, + 0, // Skip to: 3370 + /* 3241 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 122, + 0, + 0, // Skip to: 3370 + /* 3248 */ MCD_OPC_Decode, + 159, + 31, + 61, // Opcode: t2DCPS2 + /* 3252 */ MCD_OPC_FilterValue, + 3, + 24, + 0, + 0, // Skip to: 3281 + /* 3257 */ MCD_OPC_CheckPredicate, + 54, + 108, + 0, + 0, // Skip to: 3370 + /* 3262 */ MCD_OPC_CheckField, + 16, + 11, + 143, + 15, + 100, + 0, + 0, // Skip to: 3370 + /* 3270 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 93, + 0, + 0, // Skip to: 3370 + /* 3277 */ MCD_OPC_Decode, + 160, + 31, + 61, // Opcode: t2DCPS3 + /* 3281 */ MCD_OPC_FilterValue, + 18, + 24, + 0, + 0, // Skip to: 3310 + /* 3286 */ MCD_OPC_CheckPredicate, + 55, + 79, + 0, + 0, // Skip to: 3370 + /* 3291 */ MCD_OPC_CheckField, + 16, + 11, + 175, + 7, + 71, + 0, + 0, // Skip to: 3370 + /* 3299 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 64, + 0, + 0, // Skip to: 3370 + /* 3306 */ MCD_OPC_Decode, + 199, + 33, + 51, // Opcode: t2TSB + /* 3310 */ MCD_OPC_FilterValue, + 128, + 30, + 24, + 0, + 0, // Skip to: 3340 + /* 3316 */ MCD_OPC_CheckPredicate, + 46, + 49, + 0, + 0, // Skip to: 3370 + /* 3321 */ MCD_OPC_CheckField, + 20, + 7, + 60, + 42, + 0, + 0, // Skip to: 3370 + /* 3328 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 35, + 0, + 0, // Skip to: 3370 + /* 3335 */ MCD_OPC_Decode, + 131, + 31, + 130, + 3, // Opcode: t2BXJ + /* 3340 */ MCD_OPC_FilterValue, + 175, + 30, + 24, + 0, + 0, // Skip to: 3370 + /* 3346 */ MCD_OPC_CheckPredicate, + 56, + 19, + 0, + 0, // Skip to: 3370 + /* 3351 */ MCD_OPC_CheckField, + 16, + 11, + 191, + 7, + 11, + 0, + 0, // Skip to: 3370 + /* 3359 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 4, + 0, + 0, // Skip to: 3370 + /* 3366 */ MCD_OPC_Decode, + 135, + 31, + 61, // Opcode: t2CLREX + /* 3370 */ MCD_OPC_ExtractField, + 16, + 11, // Inst{26-16} ... + /* 3373 */ MCD_OPC_FilterValue, + 175, + 7, + 131, + 0, + 0, // Skip to: 3510 + /* 3379 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 3382 */ MCD_OPC_FilterValue, + 0, + 68, + 0, + 0, // Skip to: 3455 + /* 3387 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 3390 */ MCD_OPC_FilterValue, + 0, + 24, + 1, + 0, // Skip to: 3675 + /* 3395 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 3398 */ MCD_OPC_FilterValue, + 0, + 16, + 1, + 0, // Skip to: 3675 + /* 3403 */ MCD_OPC_ExtractField, + 9, + 2, // Inst{10-9} ... + /* 3406 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 3438 + /* 3411 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 3428 + /* 3416 */ MCD_OPC_CheckField, + 4, + 4, + 15, + 5, + 0, + 0, // Skip to: 3428 + /* 3423 */ MCD_OPC_Decode, + 157, + 31, + 131, + 3, // Opcode: t2DBG + /* 3428 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 3438 + /* 3433 */ MCD_OPC_Decode, + 167, + 31, + 132, + 3, // Opcode: t2HINT + /* 3438 */ MCD_OPC_CheckPredicate, + 46, + 232, + 0, + 0, // Skip to: 3675 + /* 3443 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 225, + 0, + 0, // Skip to: 3675 + /* 3450 */ MCD_OPC_Decode, + 145, + 31, + 133, + 3, // Opcode: t2CPS2p + /* 3455 */ MCD_OPC_FilterValue, + 1, + 215, + 0, + 0, // Skip to: 3675 + /* 3460 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 3463 */ MCD_OPC_FilterValue, + 0, + 207, + 0, + 0, // Skip to: 3675 + /* 3468 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 3471 */ MCD_OPC_FilterValue, + 0, + 199, + 0, + 0, // Skip to: 3675 + /* 3476 */ MCD_OPC_CheckPredicate, + 46, + 19, + 0, + 0, // Skip to: 3500 + /* 3481 */ MCD_OPC_CheckField, + 9, + 2, + 0, + 12, + 0, + 0, // Skip to: 3500 + /* 3488 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 5, + 0, + 0, // Skip to: 3500 + /* 3495 */ MCD_OPC_Decode, + 144, + 31, + 133, + 3, // Opcode: t2CPS1p + /* 3500 */ MCD_OPC_CheckPredicate, + 46, + 170, + 0, + 0, // Skip to: 3675 + /* 3505 */ MCD_OPC_Decode, + 146, + 31, + 133, + 3, // Opcode: t2CPS3p + /* 3510 */ MCD_OPC_FilterValue, + 191, + 7, + 69, + 0, + 0, // Skip to: 3585 + /* 3516 */ MCD_OPC_ExtractField, + 4, + 8, // Inst{11-4} ... + /* 3519 */ MCD_OPC_FilterValue, + 244, + 1, + 16, + 0, + 0, // Skip to: 3541 + /* 3525 */ MCD_OPC_CheckPredicate, + 57, + 145, + 0, + 0, // Skip to: 3675 + /* 3530 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 138, + 0, + 0, // Skip to: 3675 + /* 3537 */ MCD_OPC_Decode, + 163, + 31, + 62, // Opcode: t2DSB + /* 3541 */ MCD_OPC_FilterValue, + 245, + 1, + 16, + 0, + 0, // Skip to: 3563 + /* 3547 */ MCD_OPC_CheckPredicate, + 57, + 123, + 0, + 0, // Skip to: 3675 + /* 3552 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 116, + 0, + 0, // Skip to: 3675 + /* 3559 */ MCD_OPC_Decode, + 162, + 31, + 62, // Opcode: t2DMB + /* 3563 */ MCD_OPC_FilterValue, + 246, + 1, + 106, + 0, + 0, // Skip to: 3675 + /* 3569 */ MCD_OPC_CheckPredicate, + 57, + 101, + 0, + 0, // Skip to: 3675 + /* 3574 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 94, + 0, + 0, // Skip to: 3675 + /* 3581 */ MCD_OPC_Decode, + 169, + 31, + 63, // Opcode: t2ISB + /* 3585 */ MCD_OPC_FilterValue, + 222, + 7, + 24, + 0, + 0, // Skip to: 3615 + /* 3591 */ MCD_OPC_CheckPredicate, + 46, + 79, + 0, + 0, // Skip to: 3675 + /* 3596 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 72, + 0, + 0, // Skip to: 3675 + /* 3603 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 65, + 0, + 0, // Skip to: 3675 + /* 3610 */ MCD_OPC_Decode, + 181, + 33, + 203, + 2, // Opcode: t2SUBS_PC_LR + /* 3615 */ MCD_OPC_FilterValue, + 239, + 7, + 24, + 0, + 0, // Skip to: 3645 + /* 3621 */ MCD_OPC_CheckPredicate, + 46, + 49, + 0, + 0, // Skip to: 3675 + /* 3626 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 42, + 0, + 0, // Skip to: 3675 + /* 3633 */ MCD_OPC_CheckField, + 0, + 8, + 0, + 35, + 0, + 0, // Skip to: 3675 + /* 3640 */ MCD_OPC_Decode, + 136, + 32, + 134, + 3, // Opcode: t2MRS_AR + /* 3645 */ MCD_OPC_FilterValue, + 255, + 7, + 24, + 0, + 0, // Skip to: 3675 + /* 3651 */ MCD_OPC_CheckPredicate, + 46, + 19, + 0, + 0, // Skip to: 3675 + /* 3656 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 12, + 0, + 0, // Skip to: 3675 + /* 3663 */ MCD_OPC_CheckField, + 0, + 8, + 0, + 5, + 0, + 0, // Skip to: 3675 + /* 3670 */ MCD_OPC_Decode, + 139, + 32, + 134, + 3, // Opcode: t2MRSsys_AR + /* 3675 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 3678 */ MCD_OPC_FilterValue, + 13, + 23, + 0, + 0, // Skip to: 3706 + /* 3683 */ MCD_OPC_CheckPredicate, + 58, + 102, + 0, + 0, // Skip to: 3790 + /* 3688 */ MCD_OPC_CheckField, + 20, + 7, + 58, + 95, + 0, + 0, // Skip to: 3790 + /* 3695 */ MCD_OPC_SoftFail, + 128, + 80 /* 0x2800 */, + 128, + 128, + 60 /* 0xf0000 */, + /* 3701 */ MCD_OPC_Decode, + 154, + 32, + 132, + 3, // Opcode: t2PACBTI + /* 3706 */ MCD_OPC_FilterValue, + 15, + 23, + 0, + 0, // Skip to: 3734 + /* 3711 */ MCD_OPC_CheckPredicate, + 58, + 74, + 0, + 0, // Skip to: 3790 + /* 3716 */ MCD_OPC_CheckField, + 20, + 7, + 58, + 67, + 0, + 0, // Skip to: 3790 + /* 3723 */ MCD_OPC_SoftFail, + 128, + 80 /* 0x2800 */, + 128, + 128, + 60 /* 0xf0000 */, + /* 3729 */ MCD_OPC_Decode, + 129, + 31, + 132, + 3, // Opcode: t2BTI + /* 3734 */ MCD_OPC_FilterValue, + 29, + 23, + 0, + 0, // Skip to: 3762 + /* 3739 */ MCD_OPC_CheckPredicate, + 58, + 46, + 0, + 0, // Skip to: 3790 + /* 3744 */ MCD_OPC_CheckField, + 20, + 7, + 58, + 39, + 0, + 0, // Skip to: 3790 + /* 3751 */ MCD_OPC_SoftFail, + 128, + 80 /* 0x2800 */, + 128, + 128, + 60 /* 0xf0000 */, + /* 3757 */ MCD_OPC_Decode, + 153, + 32, + 132, + 3, // Opcode: t2PAC + /* 3762 */ MCD_OPC_FilterValue, + 45, + 23, + 0, + 0, // Skip to: 3790 + /* 3767 */ MCD_OPC_CheckPredicate, + 58, + 18, + 0, + 0, // Skip to: 3790 + /* 3772 */ MCD_OPC_CheckField, + 20, + 7, + 58, + 11, + 0, + 0, // Skip to: 3790 + /* 3779 */ MCD_OPC_SoftFail, + 128, + 80 /* 0x2800 */, + 128, + 128, + 60 /* 0xf0000 */, + /* 3785 */ MCD_OPC_Decode, + 244, + 30, + 132, + 3, // Opcode: t2AUT + /* 3790 */ MCD_OPC_ExtractField, + 20, + 7, // Inst{26-20} ... + /* 3793 */ MCD_OPC_FilterValue, + 59, + 22, + 0, + 0, // Skip to: 3820 + /* 3798 */ MCD_OPC_CheckPredicate, + 59, + 77, + 0, + 0, // Skip to: 3880 + /* 3803 */ MCD_OPC_CheckField, + 4, + 4, + 7, + 70, + 0, + 0, // Skip to: 3880 + /* 3810 */ MCD_OPC_SoftFail, + 143, + 64 /* 0x200f */, + 128, + 158, + 60 /* 0xf0f00 */, + /* 3816 */ MCD_OPC_Decode, + 196, + 32, + 61, // Opcode: t2SB + /* 3820 */ MCD_OPC_FilterValue, + 126, + 17, + 0, + 0, // Skip to: 3842 + /* 3825 */ MCD_OPC_CheckPredicate, + 60, + 50, + 0, + 0, // Skip to: 3880 + /* 3830 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 43, + 0, + 0, // Skip to: 3880 + /* 3837 */ MCD_OPC_Decode, + 168, + 31, + 135, + 3, // Opcode: t2HVC + /* 3842 */ MCD_OPC_FilterValue, + 127, + 33, + 0, + 0, // Skip to: 3880 + /* 3847 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 3850 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3865 + /* 3855 */ MCD_OPC_CheckPredicate, + 61, + 20, + 0, + 0, // Skip to: 3880 + /* 3860 */ MCD_OPC_Decode, + 211, + 32, + 136, + 3, // Opcode: t2SMC + /* 3865 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 3880 + /* 3870 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 3880 + /* 3875 */ MCD_OPC_Decode, + 211, + 33, + 135, + 3, // Opcode: t2UDF + /* 3880 */ MCD_OPC_ExtractField, + 21, + 6, // Inst{26-21} ... + /* 3883 */ MCD_OPC_FilterValue, + 28, + 70, + 0, + 0, // Skip to: 3958 + /* 3888 */ MCD_OPC_CheckPredicate, + 46, + 19, + 0, + 0, // Skip to: 3912 + /* 3893 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 12, + 0, + 0, // Skip to: 3912 + /* 3900 */ MCD_OPC_CheckField, + 0, + 8, + 0, + 5, + 0, + 0, // Skip to: 3912 + /* 3907 */ MCD_OPC_Decode, + 140, + 32, + 137, + 3, // Opcode: t2MSR_AR + /* 3912 */ MCD_OPC_CheckPredicate, + 62, + 26, + 0, + 0, // Skip to: 3943 + /* 3917 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 19, + 0, + 0, // Skip to: 3943 + /* 3924 */ MCD_OPC_CheckField, + 5, + 3, + 1, + 12, + 0, + 0, // Skip to: 3943 + /* 3931 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 5, + 0, + 0, // Skip to: 3943 + /* 3938 */ MCD_OPC_Decode, + 142, + 32, + 138, + 3, // Opcode: t2MSRbanked + /* 3943 */ MCD_OPC_CheckPredicate, + 63, + 63, + 0, + 0, // Skip to: 4011 + /* 3948 */ MCD_OPC_SoftFail, + 128, + 198, + 64 /* 0x102300 */, + 0, + /* 3953 */ MCD_OPC_Decode, + 141, + 32, + 139, + 3, // Opcode: t2MSR_M + /* 3958 */ MCD_OPC_FilterValue, + 31, + 48, + 0, + 0, // Skip to: 4011 + /* 3963 */ MCD_OPC_CheckPredicate, + 62, + 26, + 0, + 0, // Skip to: 3994 + /* 3968 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 19, + 0, + 0, // Skip to: 3994 + /* 3975 */ MCD_OPC_CheckField, + 5, + 3, + 1, + 12, + 0, + 0, // Skip to: 3994 + /* 3982 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 5, + 0, + 0, // Skip to: 3994 + /* 3989 */ MCD_OPC_Decode, + 138, + 32, + 140, + 3, // Opcode: t2MRSbanked + /* 3994 */ MCD_OPC_CheckPredicate, + 63, + 12, + 0, + 0, // Skip to: 4011 + /* 3999 */ MCD_OPC_SoftFail, + 128, + 192, + 64 /* 0x102000 */, + 128, + 128, + 60 /* 0xf0000 */, + /* 4006 */ MCD_OPC_Decode, + 137, + 32, + 141, + 3, // Opcode: t2MRS_M + /* 4011 */ MCD_OPC_CheckPredicate, + 45, + 226, + 19, + 0, // Skip to: 9106 + /* 4016 */ MCD_OPC_Decode, + 132, + 31, + 142, + 3, // Opcode: t2Bcc + /* 4021 */ MCD_OPC_FilterValue, + 1, + 216, + 19, + 0, // Skip to: 9106 + /* 4026 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 4029 */ MCD_OPC_FilterValue, + 0, + 144, + 0, + 0, // Skip to: 4178 + /* 4034 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 4037 */ MCD_OPC_FilterValue, + 1, + 200, + 19, + 0, // Skip to: 9106 + /* 4042 */ MCD_OPC_ExtractField, + 16, + 11, // Inst{26-16} ... + /* 4045 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4060 + /* 4050 */ MCD_OPC_CheckPredicate, + 64, + 35, + 0, + 0, // Skip to: 4090 + /* 4055 */ MCD_OPC_Decode, + 243, + 31, + 143, + 3, // Opcode: t2LEUpdate + /* 4060 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 4075 + /* 4065 */ MCD_OPC_CheckPredicate, + 22, + 20, + 0, + 0, // Skip to: 4090 + /* 4070 */ MCD_OPC_Decode, + 157, + 7, + 143, + 3, // Opcode: MVE_LETP + /* 4075 */ MCD_OPC_FilterValue, + 47, + 10, + 0, + 0, // Skip to: 4090 + /* 4080 */ MCD_OPC_CheckPredicate, + 64, + 5, + 0, + 0, // Skip to: 4090 + /* 4085 */ MCD_OPC_Decode, + 242, + 31, + 143, + 3, // Opcode: t2LE + /* 4090 */ MCD_OPC_ExtractField, + 20, + 7, // Inst{26-20} ... + /* 4093 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4108 + /* 4098 */ MCD_OPC_CheckPredicate, + 22, + 65, + 0, + 0, // Skip to: 4168 + /* 4103 */ MCD_OPC_Decode, + 222, + 13, + 143, + 3, // Opcode: MVE_WLSTP_8 + /* 4108 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 4123 + /* 4113 */ MCD_OPC_CheckPredicate, + 22, + 50, + 0, + 0, // Skip to: 4168 + /* 4118 */ MCD_OPC_Decode, + 219, + 13, + 143, + 3, // Opcode: MVE_WLSTP_16 + /* 4123 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 4138 + /* 4128 */ MCD_OPC_CheckPredicate, + 22, + 35, + 0, + 0, // Skip to: 4168 + /* 4133 */ MCD_OPC_Decode, + 220, + 13, + 143, + 3, // Opcode: MVE_WLSTP_32 + /* 4138 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 4153 + /* 4143 */ MCD_OPC_CheckPredicate, + 22, + 20, + 0, + 0, // Skip to: 4168 + /* 4148 */ MCD_OPC_Decode, + 221, + 13, + 143, + 3, // Opcode: MVE_WLSTP_64 + /* 4153 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 4168 + /* 4158 */ MCD_OPC_CheckPredicate, + 64, + 5, + 0, + 0, // Skip to: 4168 + /* 4163 */ MCD_OPC_Decode, + 241, + 33, + 143, + 3, // Opcode: t2WLS + /* 4168 */ MCD_OPC_CheckPredicate, + 64, + 69, + 19, + 0, // Skip to: 9106 + /* 4173 */ MCD_OPC_Decode, + 249, + 30, + 144, + 3, // Opcode: t2BFLi + /* 4178 */ MCD_OPC_FilterValue, + 1, + 59, + 19, + 0, // Skip to: 9106 + /* 4183 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4186 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 4354 + /* 4191 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 4194 */ MCD_OPC_FilterValue, + 1, + 43, + 19, + 0, // Skip to: 9106 + /* 4199 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 4202 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 4314 + /* 4207 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 4210 */ MCD_OPC_FilterValue, + 0, + 21, + 0, + 0, // Skip to: 4236 + /* 4215 */ MCD_OPC_CheckPredicate, + 22, + 94, + 0, + 0, // Skip to: 4314 + /* 4220 */ MCD_OPC_CheckField, + 23, + 4, + 0, + 87, + 0, + 0, // Skip to: 4314 + /* 4227 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 0, + /* 4231 */ MCD_OPC_Decode, + 155, + 7, + 143, + 3, // Opcode: MVE_DLSTP_8 + /* 4236 */ MCD_OPC_FilterValue, + 1, + 21, + 0, + 0, // Skip to: 4262 + /* 4241 */ MCD_OPC_CheckPredicate, + 22, + 68, + 0, + 0, // Skip to: 4314 + /* 4246 */ MCD_OPC_CheckField, + 23, + 4, + 0, + 61, + 0, + 0, // Skip to: 4314 + /* 4253 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 0, + /* 4257 */ MCD_OPC_Decode, + 152, + 7, + 143, + 3, // Opcode: MVE_DLSTP_16 + /* 4262 */ MCD_OPC_FilterValue, + 2, + 21, + 0, + 0, // Skip to: 4288 + /* 4267 */ MCD_OPC_CheckPredicate, + 22, + 42, + 0, + 0, // Skip to: 4314 + /* 4272 */ MCD_OPC_CheckField, + 23, + 4, + 0, + 35, + 0, + 0, // Skip to: 4314 + /* 4279 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 0, + /* 4283 */ MCD_OPC_Decode, + 153, + 7, + 143, + 3, // Opcode: MVE_DLSTP_32 + /* 4288 */ MCD_OPC_FilterValue, + 3, + 21, + 0, + 0, // Skip to: 4314 + /* 4293 */ MCD_OPC_CheckPredicate, + 22, + 16, + 0, + 0, // Skip to: 4314 + /* 4298 */ MCD_OPC_CheckField, + 23, + 4, + 0, + 9, + 0, + 0, // Skip to: 4314 + /* 4305 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 0, + /* 4309 */ MCD_OPC_Decode, + 154, + 7, + 143, + 3, // Opcode: MVE_DLSTP_64 + /* 4314 */ MCD_OPC_CheckPredicate, + 22, + 25, + 0, + 0, // Skip to: 4344 + /* 4319 */ MCD_OPC_CheckField, + 23, + 4, + 0, + 18, + 0, + 0, // Skip to: 4344 + /* 4326 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 11, + 0, + 0, // Skip to: 4344 + /* 4333 */ MCD_OPC_SoftFail, + 254, + 159, + 192, + 1 /* 0x300ffe */, + 0, + /* 4339 */ MCD_OPC_Decode, + 156, + 7, + 143, + 3, // Opcode: MVE_LCTP + /* 4344 */ MCD_OPC_CheckPredicate, + 64, + 149, + 18, + 0, // Skip to: 9106 + /* 4349 */ MCD_OPC_Decode, + 252, + 30, + 145, + 3, // Opcode: t2BFic + /* 4354 */ MCD_OPC_FilterValue, + 1, + 139, + 18, + 0, // Skip to: 9106 + /* 4359 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 4362 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 4416 + /* 4367 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 4370 */ MCD_OPC_FilterValue, + 1, + 123, + 18, + 0, // Skip to: 9106 + /* 4375 */ MCD_OPC_CheckPredicate, + 64, + 26, + 0, + 0, // Skip to: 4406 + /* 4380 */ MCD_OPC_CheckField, + 23, + 4, + 0, + 19, + 0, + 0, // Skip to: 4406 + /* 4387 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 12, + 0, + 0, // Skip to: 4406 + /* 4394 */ MCD_OPC_CheckField, + 1, + 11, + 0, + 5, + 0, + 0, // Skip to: 4406 + /* 4401 */ MCD_OPC_Decode, + 161, + 31, + 143, + 3, // Opcode: t2DLS + /* 4406 */ MCD_OPC_CheckPredicate, + 64, + 87, + 18, + 0, // Skip to: 9106 + /* 4411 */ MCD_OPC_Decode, + 251, + 30, + 146, + 3, // Opcode: t2BFi + /* 4416 */ MCD_OPC_FilterValue, + 1, + 77, + 18, + 0, // Skip to: 9106 + /* 4421 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 4424 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4446 + /* 4429 */ MCD_OPC_CheckPredicate, + 64, + 64, + 18, + 0, // Skip to: 9106 + /* 4434 */ MCD_OPC_CheckField, + 0, + 12, + 1, + 57, + 18, + 0, // Skip to: 9106 + /* 4441 */ MCD_OPC_Decode, + 253, + 30, + 147, + 3, // Opcode: t2BFr + /* 4446 */ MCD_OPC_FilterValue, + 1, + 47, + 18, + 0, // Skip to: 9106 + /* 4451 */ MCD_OPC_CheckPredicate, + 64, + 42, + 18, + 0, // Skip to: 9106 + /* 4456 */ MCD_OPC_CheckField, + 0, + 12, + 1, + 35, + 18, + 0, // Skip to: 9106 + /* 4463 */ MCD_OPC_Decode, + 250, + 30, + 147, + 3, // Opcode: t2BFLr + /* 4468 */ MCD_OPC_FilterValue, + 1, + 25, + 18, + 0, // Skip to: 9106 + /* 4473 */ MCD_OPC_CheckPredicate, + 39, + 20, + 18, + 0, // Skip to: 9106 + /* 4478 */ MCD_OPC_CheckField, + 14, + 1, + 0, + 13, + 18, + 0, // Skip to: 9106 + /* 4485 */ MCD_OPC_Decode, + 246, + 30, + 148, + 3, // Opcode: t2B + /* 4490 */ MCD_OPC_FilterValue, + 31, + 3, + 18, + 0, // Skip to: 9106 + /* 4495 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 4498 */ MCD_OPC_FilterValue, + 0, + 96, + 6, + 0, // Skip to: 6135 + /* 4503 */ MCD_OPC_ExtractField, + 24, + 3, // Inst{26-24} ... + /* 4506 */ MCD_OPC_FilterValue, + 0, + 100, + 1, + 0, // Skip to: 4867 + /* 4511 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 4514 */ MCD_OPC_FilterValue, + 0, + 125, + 0, + 0, // Skip to: 4644 + /* 4519 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 4522 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 4629 + /* 4527 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 4530 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4552 + /* 4535 */ MCD_OPC_CheckPredicate, + 45, + 214, + 17, + 0, // Skip to: 9106 + /* 4540 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 207, + 17, + 0, // Skip to: 9106 + /* 4547 */ MCD_OPC_Decode, + 161, + 33, + 149, + 3, // Opcode: t2STRBs + /* 4552 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 4574 + /* 4557 */ MCD_OPC_CheckPredicate, + 45, + 192, + 17, + 0, // Skip to: 9106 + /* 4562 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 185, + 17, + 0, // Skip to: 9106 + /* 4569 */ MCD_OPC_Decode, + 157, + 33, + 150, + 3, // Opcode: t2STRB_POST + /* 4574 */ MCD_OPC_FilterValue, + 3, + 175, + 17, + 0, // Skip to: 9106 + /* 4579 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 4582 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 4614 + /* 4587 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 4604 + /* 4592 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 5, + 0, + 0, // Skip to: 4604 + /* 4599 */ MCD_OPC_Decode, + 156, + 33, + 151, + 3, // Opcode: t2STRBT + /* 4604 */ MCD_OPC_CheckPredicate, + 45, + 145, + 17, + 0, // Skip to: 9106 + /* 4609 */ MCD_OPC_Decode, + 160, + 33, + 152, + 3, // Opcode: t2STRBi8 + /* 4614 */ MCD_OPC_FilterValue, + 1, + 135, + 17, + 0, // Skip to: 9106 + /* 4619 */ MCD_OPC_CheckPredicate, + 45, + 130, + 17, + 0, // Skip to: 9106 + /* 4624 */ MCD_OPC_Decode, + 158, + 33, + 150, + 3, // Opcode: t2STRB_PRE + /* 4629 */ MCD_OPC_FilterValue, + 1, + 120, + 17, + 0, // Skip to: 9106 + /* 4634 */ MCD_OPC_CheckPredicate, + 45, + 115, + 17, + 0, // Skip to: 9106 + /* 4639 */ MCD_OPC_Decode, + 159, + 33, + 153, + 3, // Opcode: t2STRBi12 + /* 4644 */ MCD_OPC_FilterValue, + 1, + 105, + 17, + 0, // Skip to: 9106 + /* 4649 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 4652 */ MCD_OPC_FilterValue, + 0, + 143, + 0, + 0, // Skip to: 4800 + /* 4657 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 4660 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 4700 + /* 4665 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 4668 */ MCD_OPC_FilterValue, + 0, + 159, + 0, + 0, // Skip to: 4832 + /* 4673 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 4690 + /* 4678 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 4690 + /* 4685 */ MCD_OPC_Decode, + 164, + 32, + 154, + 3, // Opcode: t2PLDs + /* 4690 */ MCD_OPC_CheckPredicate, + 45, + 137, + 0, + 0, // Skip to: 4832 + /* 4695 */ MCD_OPC_Decode, + 206, + 31, + 154, + 3, // Opcode: t2LDRBs + /* 4700 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 4722 + /* 4705 */ MCD_OPC_CheckPredicate, + 45, + 122, + 0, + 0, // Skip to: 4832 + /* 4710 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 115, + 0, + 0, // Skip to: 4832 + /* 4717 */ MCD_OPC_Decode, + 201, + 31, + 150, + 3, // Opcode: t2LDRB_POST + /* 4722 */ MCD_OPC_FilterValue, + 3, + 105, + 0, + 0, // Skip to: 4832 + /* 4727 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 4730 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 4785 + /* 4735 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 4738 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4760 + /* 4743 */ MCD_OPC_CheckPredicate, + 45, + 27, + 0, + 0, // Skip to: 4775 + /* 4748 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 20, + 0, + 0, // Skip to: 4775 + /* 4755 */ MCD_OPC_Decode, + 162, + 32, + 155, + 3, // Opcode: t2PLDi8 + /* 4760 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 4775 + /* 4765 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 4775 + /* 4770 */ MCD_OPC_Decode, + 200, + 31, + 156, + 3, // Opcode: t2LDRBT + /* 4775 */ MCD_OPC_CheckPredicate, + 45, + 52, + 0, + 0, // Skip to: 4832 + /* 4780 */ MCD_OPC_Decode, + 204, + 31, + 155, + 3, // Opcode: t2LDRBi8 + /* 4785 */ MCD_OPC_FilterValue, + 1, + 42, + 0, + 0, // Skip to: 4832 + /* 4790 */ MCD_OPC_CheckPredicate, + 45, + 37, + 0, + 0, // Skip to: 4832 + /* 4795 */ MCD_OPC_Decode, + 202, + 31, + 150, + 3, // Opcode: t2LDRB_PRE + /* 4800 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 4832 + /* 4805 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 4822 + /* 4810 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 4822 + /* 4817 */ MCD_OPC_Decode, + 161, + 32, + 157, + 3, // Opcode: t2PLDi12 + /* 4822 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 4832 + /* 4827 */ MCD_OPC_Decode, + 203, + 31, + 157, + 3, // Opcode: t2LDRBi12 + /* 4832 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 4835 */ MCD_OPC_FilterValue, + 15, + 170, + 16, + 0, // Skip to: 9106 + /* 4840 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 4857 + /* 4845 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 4857 + /* 4852 */ MCD_OPC_Decode, + 163, + 32, + 158, + 3, // Opcode: t2PLDpci + /* 4857 */ MCD_OPC_CheckPredicate, + 45, + 148, + 16, + 0, // Skip to: 9106 + /* 4862 */ MCD_OPC_Decode, + 205, + 31, + 158, + 3, // Opcode: t2LDRBpci + /* 4867 */ MCD_OPC_FilterValue, + 1, + 226, + 0, + 0, // Skip to: 5098 + /* 4872 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 4875 */ MCD_OPC_FilterValue, + 1, + 130, + 16, + 0, // Skip to: 9106 + /* 4880 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 4883 */ MCD_OPC_FilterValue, + 0, + 143, + 0, + 0, // Skip to: 5031 + /* 4888 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 4891 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 4931 + /* 4896 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 4899 */ MCD_OPC_FilterValue, + 0, + 159, + 0, + 0, // Skip to: 5063 + /* 4904 */ MCD_OPC_CheckPredicate, + 65, + 12, + 0, + 0, // Skip to: 4921 + /* 4909 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 4921 + /* 4916 */ MCD_OPC_Decode, + 168, + 32, + 154, + 3, // Opcode: t2PLIs + /* 4921 */ MCD_OPC_CheckPredicate, + 45, + 137, + 0, + 0, // Skip to: 5063 + /* 4926 */ MCD_OPC_Decode, + 227, + 31, + 154, + 3, // Opcode: t2LDRSBs + /* 4931 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 4953 + /* 4936 */ MCD_OPC_CheckPredicate, + 45, + 122, + 0, + 0, // Skip to: 5063 + /* 4941 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 115, + 0, + 0, // Skip to: 5063 + /* 4948 */ MCD_OPC_Decode, + 222, + 31, + 150, + 3, // Opcode: t2LDRSB_POST + /* 4953 */ MCD_OPC_FilterValue, + 3, + 105, + 0, + 0, // Skip to: 5063 + /* 4958 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 4961 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 5016 + /* 4966 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 4969 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4991 + /* 4974 */ MCD_OPC_CheckPredicate, + 65, + 27, + 0, + 0, // Skip to: 5006 + /* 4979 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 20, + 0, + 0, // Skip to: 5006 + /* 4986 */ MCD_OPC_Decode, + 166, + 32, + 155, + 3, // Opcode: t2PLIi8 + /* 4991 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5006 + /* 4996 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 5006 + /* 5001 */ MCD_OPC_Decode, + 221, + 31, + 156, + 3, // Opcode: t2LDRSBT + /* 5006 */ MCD_OPC_CheckPredicate, + 45, + 52, + 0, + 0, // Skip to: 5063 + /* 5011 */ MCD_OPC_Decode, + 225, + 31, + 155, + 3, // Opcode: t2LDRSBi8 + /* 5016 */ MCD_OPC_FilterValue, + 1, + 42, + 0, + 0, // Skip to: 5063 + /* 5021 */ MCD_OPC_CheckPredicate, + 45, + 37, + 0, + 0, // Skip to: 5063 + /* 5026 */ MCD_OPC_Decode, + 223, + 31, + 150, + 3, // Opcode: t2LDRSB_PRE + /* 5031 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 5063 + /* 5036 */ MCD_OPC_CheckPredicate, + 65, + 12, + 0, + 0, // Skip to: 5053 + /* 5041 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 5053 + /* 5048 */ MCD_OPC_Decode, + 165, + 32, + 157, + 3, // Opcode: t2PLIi12 + /* 5053 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 5063 + /* 5058 */ MCD_OPC_Decode, + 224, + 31, + 157, + 3, // Opcode: t2LDRSBi12 + /* 5063 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 5066 */ MCD_OPC_FilterValue, + 15, + 195, + 15, + 0, // Skip to: 9106 + /* 5071 */ MCD_OPC_CheckPredicate, + 65, + 12, + 0, + 0, // Skip to: 5088 + /* 5076 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 5088 + /* 5083 */ MCD_OPC_Decode, + 167, + 32, + 158, + 3, // Opcode: t2PLIpci + /* 5088 */ MCD_OPC_CheckPredicate, + 45, + 173, + 15, + 0, // Skip to: 9106 + /* 5093 */ MCD_OPC_Decode, + 226, + 31, + 158, + 3, // Opcode: t2LDRSBpci + /* 5098 */ MCD_OPC_FilterValue, + 2, + 207, + 2, + 0, // Skip to: 5822 + /* 5103 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 5106 */ MCD_OPC_FilterValue, + 0, + 159, + 1, + 0, // Skip to: 5526 + /* 5111 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 5114 */ MCD_OPC_FilterValue, + 0, + 77, + 0, + 0, // Skip to: 5196 + /* 5119 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5122 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 5144 + /* 5127 */ MCD_OPC_CheckPredicate, + 45, + 134, + 15, + 0, // Skip to: 9106 + /* 5132 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 127, + 15, + 0, // Skip to: 9106 + /* 5139 */ MCD_OPC_Decode, + 245, + 31, + 217, + 2, // Opcode: t2LSLrr + /* 5144 */ MCD_OPC_FilterValue, + 1, + 117, + 15, + 0, // Skip to: 9106 + /* 5149 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5152 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 5174 + /* 5157 */ MCD_OPC_CheckPredicate, + 53, + 104, + 15, + 0, // Skip to: 9106 + /* 5162 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 97, + 15, + 0, // Skip to: 9106 + /* 5169 */ MCD_OPC_Decode, + 194, + 32, + 159, + 3, // Opcode: t2SADD8 + /* 5174 */ MCD_OPC_FilterValue, + 1, + 87, + 15, + 0, // Skip to: 9106 + /* 5179 */ MCD_OPC_CheckPredicate, + 53, + 82, + 15, + 0, // Skip to: 9106 + /* 5184 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 75, + 15, + 0, // Skip to: 9106 + /* 5191 */ MCD_OPC_Decode, + 193, + 32, + 159, + 3, // Opcode: t2SADD16 + /* 5196 */ MCD_OPC_FilterValue, + 1, + 61, + 0, + 0, // Skip to: 5262 + /* 5201 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5204 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 5233 + /* 5209 */ MCD_OPC_CheckPredicate, + 53, + 52, + 15, + 0, // Skip to: 9106 + /* 5214 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 45, + 15, + 0, // Skip to: 9106 + /* 5221 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 38, + 15, + 0, // Skip to: 9106 + /* 5228 */ MCD_OPC_Decode, + 171, + 32, + 159, + 3, // Opcode: t2QADD8 + /* 5233 */ MCD_OPC_FilterValue, + 1, + 28, + 15, + 0, // Skip to: 9106 + /* 5238 */ MCD_OPC_CheckPredicate, + 53, + 23, + 15, + 0, // Skip to: 9106 + /* 5243 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 16, + 15, + 0, // Skip to: 9106 + /* 5250 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 9, + 15, + 0, // Skip to: 9106 + /* 5257 */ MCD_OPC_Decode, + 170, + 32, + 159, + 3, // Opcode: t2QADD16 + /* 5262 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 5328 + /* 5267 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5270 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 5299 + /* 5275 */ MCD_OPC_CheckPredicate, + 53, + 242, + 14, + 0, // Skip to: 9106 + /* 5280 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 235, + 14, + 0, // Skip to: 9106 + /* 5287 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 228, + 14, + 0, // Skip to: 9106 + /* 5294 */ MCD_OPC_Decode, + 206, + 32, + 159, + 3, // Opcode: t2SHADD8 + /* 5299 */ MCD_OPC_FilterValue, + 1, + 218, + 14, + 0, // Skip to: 9106 + /* 5304 */ MCD_OPC_CheckPredicate, + 53, + 213, + 14, + 0, // Skip to: 9106 + /* 5309 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 206, + 14, + 0, // Skip to: 9106 + /* 5316 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 199, + 14, + 0, // Skip to: 9106 + /* 5323 */ MCD_OPC_Decode, + 205, + 32, + 159, + 3, // Opcode: t2SHADD16 + /* 5328 */ MCD_OPC_FilterValue, + 4, + 61, + 0, + 0, // Skip to: 5394 + /* 5333 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5336 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 5365 + /* 5341 */ MCD_OPC_CheckPredicate, + 53, + 176, + 14, + 0, // Skip to: 9106 + /* 5346 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 169, + 14, + 0, // Skip to: 9106 + /* 5353 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 162, + 14, + 0, // Skip to: 9106 + /* 5360 */ MCD_OPC_Decode, + 208, + 33, + 159, + 3, // Opcode: t2UADD8 + /* 5365 */ MCD_OPC_FilterValue, + 1, + 152, + 14, + 0, // Skip to: 9106 + /* 5370 */ MCD_OPC_CheckPredicate, + 53, + 147, + 14, + 0, // Skip to: 9106 + /* 5375 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 140, + 14, + 0, // Skip to: 9106 + /* 5382 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 133, + 14, + 0, // Skip to: 9106 + /* 5389 */ MCD_OPC_Decode, + 207, + 33, + 159, + 3, // Opcode: t2UADD16 + /* 5394 */ MCD_OPC_FilterValue, + 5, + 61, + 0, + 0, // Skip to: 5460 + /* 5399 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5402 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 5431 + /* 5407 */ MCD_OPC_CheckPredicate, + 53, + 110, + 14, + 0, // Skip to: 9106 + /* 5412 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 103, + 14, + 0, // Skip to: 9106 + /* 5419 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 96, + 14, + 0, // Skip to: 9106 + /* 5426 */ MCD_OPC_Decode, + 223, + 33, + 159, + 3, // Opcode: t2UQADD8 + /* 5431 */ MCD_OPC_FilterValue, + 1, + 86, + 14, + 0, // Skip to: 9106 + /* 5436 */ MCD_OPC_CheckPredicate, + 53, + 81, + 14, + 0, // Skip to: 9106 + /* 5441 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 74, + 14, + 0, // Skip to: 9106 + /* 5448 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 67, + 14, + 0, // Skip to: 9106 + /* 5455 */ MCD_OPC_Decode, + 222, + 33, + 159, + 3, // Opcode: t2UQADD16 + /* 5460 */ MCD_OPC_FilterValue, + 6, + 57, + 14, + 0, // Skip to: 9106 + /* 5465 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5468 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 5497 + /* 5473 */ MCD_OPC_CheckPredicate, + 53, + 44, + 14, + 0, // Skip to: 9106 + /* 5478 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 37, + 14, + 0, // Skip to: 9106 + /* 5485 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 30, + 14, + 0, // Skip to: 9106 + /* 5492 */ MCD_OPC_Decode, + 214, + 33, + 159, + 3, // Opcode: t2UHADD8 + /* 5497 */ MCD_OPC_FilterValue, + 1, + 20, + 14, + 0, // Skip to: 9106 + /* 5502 */ MCD_OPC_CheckPredicate, + 53, + 15, + 14, + 0, // Skip to: 9106 + /* 5507 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 8, + 14, + 0, // Skip to: 9106 + /* 5514 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 1, + 14, + 0, // Skip to: 9106 + /* 5521 */ MCD_OPC_Decode, + 213, + 33, + 159, + 3, // Opcode: t2UHADD16 + /* 5526 */ MCD_OPC_FilterValue, + 1, + 247, + 13, + 0, // Skip to: 9106 + /* 5531 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5534 */ MCD_OPC_FilterValue, + 0, + 139, + 0, + 0, // Skip to: 5678 + /* 5539 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5542 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 5582 + /* 5547 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5550 */ MCD_OPC_FilterValue, + 15, + 223, + 13, + 0, // Skip to: 9106 + /* 5555 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 5572 + /* 5560 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 5572 + /* 5567 */ MCD_OPC_Decode, + 193, + 33, + 160, + 3, // Opcode: t2SXTH + /* 5572 */ MCD_OPC_CheckPredicate, + 51, + 201, + 13, + 0, // Skip to: 9106 + /* 5577 */ MCD_OPC_Decode, + 190, + 33, + 161, + 3, // Opcode: t2SXTAH + /* 5582 */ MCD_OPC_FilterValue, + 1, + 191, + 13, + 0, // Skip to: 9106 + /* 5587 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 5590 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 5612 + /* 5595 */ MCD_OPC_CheckPredicate, + 53, + 178, + 13, + 0, // Skip to: 9106 + /* 5600 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 171, + 13, + 0, // Skip to: 9106 + /* 5607 */ MCD_OPC_Decode, + 169, + 32, + 162, + 3, // Opcode: t2QADD + /* 5612 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 5634 + /* 5617 */ MCD_OPC_CheckPredicate, + 53, + 156, + 13, + 0, // Skip to: 9106 + /* 5622 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 149, + 13, + 0, // Skip to: 9106 + /* 5629 */ MCD_OPC_Decode, + 173, + 32, + 162, + 3, // Opcode: t2QDADD + /* 5634 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 5656 + /* 5639 */ MCD_OPC_CheckPredicate, + 53, + 134, + 13, + 0, // Skip to: 9106 + /* 5644 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 127, + 13, + 0, // Skip to: 9106 + /* 5651 */ MCD_OPC_Decode, + 176, + 32, + 162, + 3, // Opcode: t2QSUB + /* 5656 */ MCD_OPC_FilterValue, + 3, + 117, + 13, + 0, // Skip to: 9106 + /* 5661 */ MCD_OPC_CheckPredicate, + 53, + 112, + 13, + 0, // Skip to: 9106 + /* 5666 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 105, + 13, + 0, // Skip to: 9106 + /* 5673 */ MCD_OPC_Decode, + 174, + 32, + 162, + 3, // Opcode: t2QDSUB + /* 5678 */ MCD_OPC_FilterValue, + 1, + 95, + 13, + 0, // Skip to: 9106 + /* 5683 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5686 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 5726 + /* 5691 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5694 */ MCD_OPC_FilterValue, + 15, + 79, + 13, + 0, // Skip to: 9106 + /* 5699 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 5716 + /* 5704 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 5716 + /* 5711 */ MCD_OPC_Decode, + 240, + 33, + 160, + 3, // Opcode: t2UXTH + /* 5716 */ MCD_OPC_CheckPredicate, + 51, + 57, + 13, + 0, // Skip to: 9106 + /* 5721 */ MCD_OPC_Decode, + 237, + 33, + 161, + 3, // Opcode: t2UXTAH + /* 5726 */ MCD_OPC_FilterValue, + 1, + 47, + 13, + 0, // Skip to: 9106 + /* 5731 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 5734 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 5756 + /* 5739 */ MCD_OPC_CheckPredicate, + 45, + 34, + 13, + 0, // Skip to: 9106 + /* 5744 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 27, + 13, + 0, // Skip to: 9106 + /* 5751 */ MCD_OPC_Decode, + 180, + 32, + 163, + 3, // Opcode: t2REV + /* 5756 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 5778 + /* 5761 */ MCD_OPC_CheckPredicate, + 45, + 12, + 13, + 0, // Skip to: 9106 + /* 5766 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 13, + 0, // Skip to: 9106 + /* 5773 */ MCD_OPC_Decode, + 181, + 32, + 163, + 3, // Opcode: t2REV16 + /* 5778 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 5800 + /* 5783 */ MCD_OPC_CheckPredicate, + 45, + 246, + 12, + 0, // Skip to: 9106 + /* 5788 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 239, + 12, + 0, // Skip to: 9106 + /* 5795 */ MCD_OPC_Decode, + 179, + 32, + 163, + 3, // Opcode: t2RBIT + /* 5800 */ MCD_OPC_FilterValue, + 3, + 229, + 12, + 0, // Skip to: 9106 + /* 5805 */ MCD_OPC_CheckPredicate, + 45, + 224, + 12, + 0, // Skip to: 9106 + /* 5810 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 217, + 12, + 0, // Skip to: 9106 + /* 5817 */ MCD_OPC_Decode, + 182, + 32, + 163, + 3, // Opcode: t2REVSH + /* 5822 */ MCD_OPC_FilterValue, + 3, + 207, + 12, + 0, // Skip to: 9106 + /* 5827 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 5830 */ MCD_OPC_FilterValue, + 0, + 98, + 0, + 0, // Skip to: 5933 + /* 5835 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5838 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 5893 + /* 5843 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5846 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 5878 + /* 5851 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 5868 + /* 5856 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 5868 + /* 5863 */ MCD_OPC_Decode, + 143, + 32, + 159, + 3, // Opcode: t2MUL + /* 5868 */ MCD_OPC_CheckPredicate, + 66, + 161, + 12, + 0, // Skip to: 9106 + /* 5873 */ MCD_OPC_Decode, + 252, + 31, + 164, + 3, // Opcode: t2MLA + /* 5878 */ MCD_OPC_FilterValue, + 1, + 151, + 12, + 0, // Skip to: 9106 + /* 5883 */ MCD_OPC_CheckPredicate, + 45, + 146, + 12, + 0, // Skip to: 9106 + /* 5888 */ MCD_OPC_Decode, + 241, + 32, + 165, + 3, // Opcode: t2SMULL + /* 5893 */ MCD_OPC_FilterValue, + 1, + 136, + 12, + 0, // Skip to: 9106 + /* 5898 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5901 */ MCD_OPC_FilterValue, + 0, + 128, + 12, + 0, // Skip to: 9106 + /* 5906 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 5923 + /* 5911 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 5923 + /* 5918 */ MCD_OPC_Decode, + 239, + 32, + 159, + 3, // Opcode: t2SMULBB + /* 5923 */ MCD_OPC_CheckPredicate, + 53, + 106, + 12, + 0, // Skip to: 9106 + /* 5928 */ MCD_OPC_Decode, + 212, + 32, + 164, + 3, // Opcode: t2SMLABB + /* 5933 */ MCD_OPC_FilterValue, + 1, + 65, + 0, + 0, // Skip to: 6003 + /* 5938 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5941 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 5963 + /* 5946 */ MCD_OPC_CheckPredicate, + 66, + 83, + 12, + 0, // Skip to: 9106 + /* 5951 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 76, + 12, + 0, // Skip to: 9106 + /* 5958 */ MCD_OPC_Decode, + 253, + 31, + 164, + 3, // Opcode: t2MLS + /* 5963 */ MCD_OPC_FilterValue, + 1, + 66, + 12, + 0, // Skip to: 9106 + /* 5968 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5971 */ MCD_OPC_FilterValue, + 0, + 58, + 12, + 0, // Skip to: 9106 + /* 5976 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 5993 + /* 5981 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 5993 + /* 5988 */ MCD_OPC_Decode, + 240, + 32, + 159, + 3, // Opcode: t2SMULBT + /* 5993 */ MCD_OPC_CheckPredicate, + 53, + 36, + 12, + 0, // Skip to: 9106 + /* 5998 */ MCD_OPC_Decode, + 213, + 32, + 164, + 3, // Opcode: t2SMLABT + /* 6003 */ MCD_OPC_FilterValue, + 2, + 43, + 0, + 0, // Skip to: 6051 + /* 6008 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6011 */ MCD_OPC_FilterValue, + 1, + 18, + 12, + 0, // Skip to: 9106 + /* 6016 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6019 */ MCD_OPC_FilterValue, + 0, + 10, + 12, + 0, // Skip to: 9106 + /* 6024 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 6041 + /* 6029 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 6041 + /* 6036 */ MCD_OPC_Decode, + 242, + 32, + 159, + 3, // Opcode: t2SMULTB + /* 6041 */ MCD_OPC_CheckPredicate, + 53, + 244, + 11, + 0, // Skip to: 9106 + /* 6046 */ MCD_OPC_Decode, + 223, + 32, + 164, + 3, // Opcode: t2SMLATB + /* 6051 */ MCD_OPC_FilterValue, + 3, + 43, + 0, + 0, // Skip to: 6099 + /* 6056 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6059 */ MCD_OPC_FilterValue, + 1, + 226, + 11, + 0, // Skip to: 9106 + /* 6064 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6067 */ MCD_OPC_FilterValue, + 0, + 218, + 11, + 0, // Skip to: 9106 + /* 6072 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 6089 + /* 6077 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 6089 + /* 6084 */ MCD_OPC_Decode, + 243, + 32, + 159, + 3, // Opcode: t2SMULTT + /* 6089 */ MCD_OPC_CheckPredicate, + 53, + 196, + 11, + 0, // Skip to: 9106 + /* 6094 */ MCD_OPC_Decode, + 224, + 32, + 164, + 3, // Opcode: t2SMLATT + /* 6099 */ MCD_OPC_FilterValue, + 15, + 186, + 11, + 0, // Skip to: 9106 + /* 6104 */ MCD_OPC_CheckPredicate, + 67, + 181, + 11, + 0, // Skip to: 9106 + /* 6109 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 174, + 11, + 0, // Skip to: 9106 + /* 6116 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 167, + 11, + 0, // Skip to: 9106 + /* 6123 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 160, + 11, + 0, // Skip to: 9106 + /* 6130 */ MCD_OPC_Decode, + 201, + 32, + 159, + 3, // Opcode: t2SDIV + /* 6135 */ MCD_OPC_FilterValue, + 1, + 129, + 4, + 0, // Skip to: 7293 + /* 6140 */ MCD_OPC_ExtractField, + 24, + 3, // Inst{26-24} ... + /* 6143 */ MCD_OPC_FilterValue, + 0, + 82, + 1, + 0, // Skip to: 6486 + /* 6148 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6151 */ MCD_OPC_FilterValue, + 0, + 125, + 0, + 0, // Skip to: 6281 + /* 6156 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6159 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 6266 + /* 6164 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 6167 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6189 + /* 6172 */ MCD_OPC_CheckPredicate, + 45, + 113, + 11, + 0, // Skip to: 9106 + /* 6177 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 106, + 11, + 0, // Skip to: 9106 + /* 6184 */ MCD_OPC_Decode, + 174, + 33, + 149, + 3, // Opcode: t2STRHs + /* 6189 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 6211 + /* 6194 */ MCD_OPC_CheckPredicate, + 45, + 91, + 11, + 0, // Skip to: 9106 + /* 6199 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 84, + 11, + 0, // Skip to: 9106 + /* 6206 */ MCD_OPC_Decode, + 170, + 33, + 150, + 3, // Opcode: t2STRH_POST + /* 6211 */ MCD_OPC_FilterValue, + 3, + 74, + 11, + 0, // Skip to: 9106 + /* 6216 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 6219 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 6251 + /* 6224 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 6241 + /* 6229 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 5, + 0, + 0, // Skip to: 6241 + /* 6236 */ MCD_OPC_Decode, + 169, + 33, + 151, + 3, // Opcode: t2STRHT + /* 6241 */ MCD_OPC_CheckPredicate, + 45, + 44, + 11, + 0, // Skip to: 9106 + /* 6246 */ MCD_OPC_Decode, + 173, + 33, + 152, + 3, // Opcode: t2STRHi8 + /* 6251 */ MCD_OPC_FilterValue, + 1, + 34, + 11, + 0, // Skip to: 9106 + /* 6256 */ MCD_OPC_CheckPredicate, + 45, + 29, + 11, + 0, // Skip to: 9106 + /* 6261 */ MCD_OPC_Decode, + 171, + 33, + 150, + 3, // Opcode: t2STRH_PRE + /* 6266 */ MCD_OPC_FilterValue, + 1, + 19, + 11, + 0, // Skip to: 9106 + /* 6271 */ MCD_OPC_CheckPredicate, + 45, + 14, + 11, + 0, // Skip to: 9106 + /* 6276 */ MCD_OPC_Decode, + 172, + 33, + 153, + 3, // Opcode: t2STRHi12 + /* 6281 */ MCD_OPC_FilterValue, + 1, + 4, + 11, + 0, // Skip to: 9106 + /* 6286 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6289 */ MCD_OPC_FilterValue, + 0, + 143, + 0, + 0, // Skip to: 6437 + /* 6294 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 6297 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 6337 + /* 6302 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 6305 */ MCD_OPC_FilterValue, + 0, + 159, + 0, + 0, // Skip to: 6469 + /* 6310 */ MCD_OPC_CheckPredicate, + 68, + 12, + 0, + 0, // Skip to: 6327 + /* 6315 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 6327 + /* 6322 */ MCD_OPC_Decode, + 160, + 32, + 154, + 3, // Opcode: t2PLDWs + /* 6327 */ MCD_OPC_CheckPredicate, + 45, + 137, + 0, + 0, // Skip to: 6469 + /* 6332 */ MCD_OPC_Decode, + 220, + 31, + 154, + 3, // Opcode: t2LDRHs + /* 6337 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 6359 + /* 6342 */ MCD_OPC_CheckPredicate, + 45, + 122, + 0, + 0, // Skip to: 6469 + /* 6347 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 115, + 0, + 0, // Skip to: 6469 + /* 6354 */ MCD_OPC_Decode, + 215, + 31, + 150, + 3, // Opcode: t2LDRH_POST + /* 6359 */ MCD_OPC_FilterValue, + 3, + 105, + 0, + 0, // Skip to: 6469 + /* 6364 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 6367 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 6422 + /* 6372 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 6375 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6397 + /* 6380 */ MCD_OPC_CheckPredicate, + 68, + 27, + 0, + 0, // Skip to: 6412 + /* 6385 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 20, + 0, + 0, // Skip to: 6412 + /* 6392 */ MCD_OPC_Decode, + 159, + 32, + 155, + 3, // Opcode: t2PLDWi8 + /* 6397 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6412 + /* 6402 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 6412 + /* 6407 */ MCD_OPC_Decode, + 214, + 31, + 156, + 3, // Opcode: t2LDRHT + /* 6412 */ MCD_OPC_CheckPredicate, + 45, + 52, + 0, + 0, // Skip to: 6469 + /* 6417 */ MCD_OPC_Decode, + 218, + 31, + 155, + 3, // Opcode: t2LDRHi8 + /* 6422 */ MCD_OPC_FilterValue, + 1, + 42, + 0, + 0, // Skip to: 6469 + /* 6427 */ MCD_OPC_CheckPredicate, + 45, + 37, + 0, + 0, // Skip to: 6469 + /* 6432 */ MCD_OPC_Decode, + 216, + 31, + 150, + 3, // Opcode: t2LDRH_PRE + /* 6437 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 6469 + /* 6442 */ MCD_OPC_CheckPredicate, + 68, + 12, + 0, + 0, // Skip to: 6459 + /* 6447 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 6459 + /* 6454 */ MCD_OPC_Decode, + 158, + 32, + 157, + 3, // Opcode: t2PLDWi12 + /* 6459 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 6469 + /* 6464 */ MCD_OPC_Decode, + 217, + 31, + 157, + 3, // Opcode: t2LDRHi12 + /* 6469 */ MCD_OPC_CheckPredicate, + 45, + 72, + 10, + 0, // Skip to: 9106 + /* 6474 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 65, + 10, + 0, // Skip to: 9106 + /* 6481 */ MCD_OPC_Decode, + 219, + 31, + 158, + 3, // Opcode: t2LDRHpci + /* 6486 */ MCD_OPC_FilterValue, + 1, + 150, + 0, + 0, // Skip to: 6641 + /* 6491 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6494 */ MCD_OPC_FilterValue, + 1, + 47, + 10, + 0, // Skip to: 9106 + /* 6499 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6502 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 6609 + /* 6507 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 6510 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6532 + /* 6515 */ MCD_OPC_CheckPredicate, + 45, + 104, + 0, + 0, // Skip to: 6624 + /* 6520 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 97, + 0, + 0, // Skip to: 6624 + /* 6527 */ MCD_OPC_Decode, + 234, + 31, + 154, + 3, // Opcode: t2LDRSHs + /* 6532 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 6554 + /* 6537 */ MCD_OPC_CheckPredicate, + 45, + 82, + 0, + 0, // Skip to: 6624 + /* 6542 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 75, + 0, + 0, // Skip to: 6624 + /* 6549 */ MCD_OPC_Decode, + 229, + 31, + 150, + 3, // Opcode: t2LDRSH_POST + /* 6554 */ MCD_OPC_FilterValue, + 3, + 65, + 0, + 0, // Skip to: 6624 + /* 6559 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 6562 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 6594 + /* 6567 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 6584 + /* 6572 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 5, + 0, + 0, // Skip to: 6584 + /* 6579 */ MCD_OPC_Decode, + 228, + 31, + 156, + 3, // Opcode: t2LDRSHT + /* 6584 */ MCD_OPC_CheckPredicate, + 45, + 35, + 0, + 0, // Skip to: 6624 + /* 6589 */ MCD_OPC_Decode, + 232, + 31, + 155, + 3, // Opcode: t2LDRSHi8 + /* 6594 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 6624 + /* 6599 */ MCD_OPC_CheckPredicate, + 45, + 20, + 0, + 0, // Skip to: 6624 + /* 6604 */ MCD_OPC_Decode, + 230, + 31, + 150, + 3, // Opcode: t2LDRSH_PRE + /* 6609 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6624 + /* 6614 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 6624 + /* 6619 */ MCD_OPC_Decode, + 231, + 31, + 157, + 3, // Opcode: t2LDRSHi12 + /* 6624 */ MCD_OPC_CheckPredicate, + 45, + 173, + 9, + 0, // Skip to: 9106 + /* 6629 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 166, + 9, + 0, // Skip to: 9106 + /* 6636 */ MCD_OPC_Decode, + 233, + 31, + 158, + 3, // Opcode: t2LDRSHpci + /* 6641 */ MCD_OPC_FilterValue, + 2, + 156, + 1, + 0, // Skip to: 7058 + /* 6646 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6649 */ MCD_OPC_FilterValue, + 0, + 242, + 0, + 0, // Skip to: 6896 + /* 6654 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 6657 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 6716 + /* 6662 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6665 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6687 + /* 6670 */ MCD_OPC_CheckPredicate, + 45, + 127, + 9, + 0, // Skip to: 9106 + /* 6675 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 120, + 9, + 0, // Skip to: 9106 + /* 6682 */ MCD_OPC_Decode, + 247, + 31, + 217, + 2, // Opcode: t2LSRrr + /* 6687 */ MCD_OPC_FilterValue, + 1, + 110, + 9, + 0, // Skip to: 9106 + /* 6692 */ MCD_OPC_CheckPredicate, + 53, + 105, + 9, + 0, // Skip to: 9106 + /* 6697 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 98, + 9, + 0, // Skip to: 9106 + /* 6704 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 91, + 9, + 0, // Skip to: 9106 + /* 6711 */ MCD_OPC_Decode, + 195, + 32, + 159, + 3, // Opcode: t2SASX + /* 6716 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 6752 + /* 6721 */ MCD_OPC_CheckPredicate, + 53, + 76, + 9, + 0, // Skip to: 9106 + /* 6726 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 69, + 9, + 0, // Skip to: 9106 + /* 6733 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 62, + 9, + 0, // Skip to: 9106 + /* 6740 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 55, + 9, + 0, // Skip to: 9106 + /* 6747 */ MCD_OPC_Decode, + 172, + 32, + 159, + 3, // Opcode: t2QASX + /* 6752 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 6788 + /* 6757 */ MCD_OPC_CheckPredicate, + 53, + 40, + 9, + 0, // Skip to: 9106 + /* 6762 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 33, + 9, + 0, // Skip to: 9106 + /* 6769 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 26, + 9, + 0, // Skip to: 9106 + /* 6776 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 19, + 9, + 0, // Skip to: 9106 + /* 6783 */ MCD_OPC_Decode, + 207, + 32, + 159, + 3, // Opcode: t2SHASX + /* 6788 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 6824 + /* 6793 */ MCD_OPC_CheckPredicate, + 53, + 4, + 9, + 0, // Skip to: 9106 + /* 6798 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 253, + 8, + 0, // Skip to: 9106 + /* 6805 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 246, + 8, + 0, // Skip to: 9106 + /* 6812 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 239, + 8, + 0, // Skip to: 9106 + /* 6819 */ MCD_OPC_Decode, + 209, + 33, + 159, + 3, // Opcode: t2UASX + /* 6824 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 6860 + /* 6829 */ MCD_OPC_CheckPredicate, + 53, + 224, + 8, + 0, // Skip to: 9106 + /* 6834 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 217, + 8, + 0, // Skip to: 9106 + /* 6841 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 210, + 8, + 0, // Skip to: 9106 + /* 6848 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 203, + 8, + 0, // Skip to: 9106 + /* 6855 */ MCD_OPC_Decode, + 224, + 33, + 159, + 3, // Opcode: t2UQASX + /* 6860 */ MCD_OPC_FilterValue, + 6, + 193, + 8, + 0, // Skip to: 9106 + /* 6865 */ MCD_OPC_CheckPredicate, + 53, + 188, + 8, + 0, // Skip to: 9106 + /* 6870 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 181, + 8, + 0, // Skip to: 9106 + /* 6877 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 174, + 8, + 0, // Skip to: 9106 + /* 6884 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 167, + 8, + 0, // Skip to: 9106 + /* 6891 */ MCD_OPC_Decode, + 215, + 33, + 159, + 3, // Opcode: t2UHASX + /* 6896 */ MCD_OPC_FilterValue, + 1, + 157, + 8, + 0, // Skip to: 9106 + /* 6901 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6904 */ MCD_OPC_FilterValue, + 0, + 72, + 0, + 0, // Skip to: 6981 + /* 6909 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6912 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 6952 + /* 6917 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6920 */ MCD_OPC_FilterValue, + 15, + 133, + 8, + 0, // Skip to: 9106 + /* 6925 */ MCD_OPC_CheckPredicate, + 51, + 12, + 0, + 0, // Skip to: 6942 + /* 6930 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 6942 + /* 6937 */ MCD_OPC_Decode, + 192, + 33, + 160, + 3, // Opcode: t2SXTB16 + /* 6942 */ MCD_OPC_CheckPredicate, + 51, + 111, + 8, + 0, // Skip to: 9106 + /* 6947 */ MCD_OPC_Decode, + 189, + 33, + 161, + 3, // Opcode: t2SXTAB16 + /* 6952 */ MCD_OPC_FilterValue, + 1, + 101, + 8, + 0, // Skip to: 9106 + /* 6957 */ MCD_OPC_CheckPredicate, + 53, + 96, + 8, + 0, // Skip to: 9106 + /* 6962 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 89, + 8, + 0, // Skip to: 9106 + /* 6969 */ MCD_OPC_CheckField, + 4, + 3, + 0, + 82, + 8, + 0, // Skip to: 9106 + /* 6976 */ MCD_OPC_Decode, + 202, + 32, + 166, + 3, // Opcode: t2SEL + /* 6981 */ MCD_OPC_FilterValue, + 1, + 72, + 8, + 0, // Skip to: 9106 + /* 6986 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6989 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 7029 + /* 6994 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6997 */ MCD_OPC_FilterValue, + 15, + 56, + 8, + 0, // Skip to: 9106 + /* 7002 */ MCD_OPC_CheckPredicate, + 51, + 12, + 0, + 0, // Skip to: 7019 + /* 7007 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 7019 + /* 7014 */ MCD_OPC_Decode, + 239, + 33, + 160, + 3, // Opcode: t2UXTB16 + /* 7019 */ MCD_OPC_CheckPredicate, + 51, + 34, + 8, + 0, // Skip to: 9106 + /* 7024 */ MCD_OPC_Decode, + 236, + 33, + 161, + 3, // Opcode: t2UXTAB16 + /* 7029 */ MCD_OPC_FilterValue, + 1, + 24, + 8, + 0, // Skip to: 9106 + /* 7034 */ MCD_OPC_CheckPredicate, + 45, + 19, + 8, + 0, // Skip to: 9106 + /* 7039 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 12, + 8, + 0, // Skip to: 9106 + /* 7046 */ MCD_OPC_CheckField, + 4, + 3, + 0, + 5, + 8, + 0, // Skip to: 9106 + /* 7053 */ MCD_OPC_Decode, + 137, + 31, + 163, + 3, // Opcode: t2CLZ + /* 7058 */ MCD_OPC_FilterValue, + 3, + 251, + 7, + 0, // Skip to: 9106 + /* 7063 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 7066 */ MCD_OPC_FilterValue, + 0, + 98, + 0, + 0, // Skip to: 7169 + /* 7071 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7074 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 7129 + /* 7079 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7082 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 7114 + /* 7087 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 7104 + /* 7092 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 7104 + /* 7099 */ MCD_OPC_Decode, + 237, + 32, + 159, + 3, // Opcode: t2SMUAD + /* 7104 */ MCD_OPC_CheckPredicate, + 53, + 205, + 7, + 0, // Skip to: 9106 + /* 7109 */ MCD_OPC_Decode, + 214, + 32, + 164, + 3, // Opcode: t2SMLAD + /* 7114 */ MCD_OPC_FilterValue, + 1, + 195, + 7, + 0, // Skip to: 9106 + /* 7119 */ MCD_OPC_CheckPredicate, + 45, + 190, + 7, + 0, // Skip to: 9106 + /* 7124 */ MCD_OPC_Decode, + 221, + 33, + 165, + 3, // Opcode: t2UMULL + /* 7129 */ MCD_OPC_FilterValue, + 1, + 180, + 7, + 0, // Skip to: 9106 + /* 7134 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7137 */ MCD_OPC_FilterValue, + 0, + 172, + 7, + 0, // Skip to: 9106 + /* 7142 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 7159 + /* 7147 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 7159 + /* 7154 */ MCD_OPC_Decode, + 244, + 32, + 159, + 3, // Opcode: t2SMULWB + /* 7159 */ MCD_OPC_CheckPredicate, + 53, + 150, + 7, + 0, // Skip to: 9106 + /* 7164 */ MCD_OPC_Decode, + 225, + 32, + 164, + 3, // Opcode: t2SMLAWB + /* 7169 */ MCD_OPC_FilterValue, + 1, + 83, + 0, + 0, // Skip to: 7257 + /* 7174 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7177 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 7217 + /* 7182 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7185 */ MCD_OPC_FilterValue, + 0, + 124, + 7, + 0, // Skip to: 9106 + /* 7190 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 7207 + /* 7195 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 7207 + /* 7202 */ MCD_OPC_Decode, + 238, + 32, + 159, + 3, // Opcode: t2SMUADX + /* 7207 */ MCD_OPC_CheckPredicate, + 53, + 102, + 7, + 0, // Skip to: 9106 + /* 7212 */ MCD_OPC_Decode, + 215, + 32, + 164, + 3, // Opcode: t2SMLADX + /* 7217 */ MCD_OPC_FilterValue, + 1, + 92, + 7, + 0, // Skip to: 9106 + /* 7222 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7225 */ MCD_OPC_FilterValue, + 0, + 84, + 7, + 0, // Skip to: 9106 + /* 7230 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 7247 + /* 7235 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 7247 + /* 7242 */ MCD_OPC_Decode, + 245, + 32, + 159, + 3, // Opcode: t2SMULWT + /* 7247 */ MCD_OPC_CheckPredicate, + 53, + 62, + 7, + 0, // Skip to: 9106 + /* 7252 */ MCD_OPC_Decode, + 226, + 32, + 164, + 3, // Opcode: t2SMLAWT + /* 7257 */ MCD_OPC_FilterValue, + 15, + 52, + 7, + 0, // Skip to: 9106 + /* 7262 */ MCD_OPC_CheckPredicate, + 67, + 47, + 7, + 0, // Skip to: 9106 + /* 7267 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 40, + 7, + 0, // Skip to: 9106 + /* 7274 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 33, + 7, + 0, // Skip to: 9106 + /* 7281 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 26, + 7, + 0, // Skip to: 9106 + /* 7288 */ MCD_OPC_Decode, + 212, + 33, + 159, + 3, // Opcode: t2UDIV + /* 7293 */ MCD_OPC_FilterValue, + 2, + 141, + 5, + 0, // Skip to: 8719 + /* 7298 */ MCD_OPC_ExtractField, + 24, + 3, // Inst{26-24} ... + /* 7301 */ MCD_OPC_FilterValue, + 0, + 24, + 1, + 0, // Skip to: 7586 + /* 7306 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7309 */ MCD_OPC_FilterValue, + 0, + 125, + 0, + 0, // Skip to: 7439 + /* 7314 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7317 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 7424 + /* 7322 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 7325 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7347 + /* 7330 */ MCD_OPC_CheckPredicate, + 45, + 235, + 6, + 0, // Skip to: 9106 + /* 7335 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 228, + 6, + 0, // Skip to: 9106 + /* 7342 */ MCD_OPC_Decode, + 180, + 33, + 167, + 3, // Opcode: t2STRs + /* 7347 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 7369 + /* 7352 */ MCD_OPC_CheckPredicate, + 45, + 213, + 6, + 0, // Skip to: 9106 + /* 7357 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 206, + 6, + 0, // Skip to: 9106 + /* 7364 */ MCD_OPC_Decode, + 176, + 33, + 150, + 3, // Opcode: t2STR_POST + /* 7369 */ MCD_OPC_FilterValue, + 3, + 196, + 6, + 0, // Skip to: 9106 + /* 7374 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 7377 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 7409 + /* 7382 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 7399 + /* 7387 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 5, + 0, + 0, // Skip to: 7399 + /* 7394 */ MCD_OPC_Decode, + 175, + 33, + 151, + 3, // Opcode: t2STRT + /* 7399 */ MCD_OPC_CheckPredicate, + 45, + 166, + 6, + 0, // Skip to: 9106 + /* 7404 */ MCD_OPC_Decode, + 179, + 33, + 168, + 3, // Opcode: t2STRi8 + /* 7409 */ MCD_OPC_FilterValue, + 1, + 156, + 6, + 0, // Skip to: 9106 + /* 7414 */ MCD_OPC_CheckPredicate, + 45, + 151, + 6, + 0, // Skip to: 9106 + /* 7419 */ MCD_OPC_Decode, + 177, + 33, + 150, + 3, // Opcode: t2STR_PRE + /* 7424 */ MCD_OPC_FilterValue, + 1, + 141, + 6, + 0, // Skip to: 9106 + /* 7429 */ MCD_OPC_CheckPredicate, + 45, + 136, + 6, + 0, // Skip to: 9106 + /* 7434 */ MCD_OPC_Decode, + 178, + 33, + 169, + 3, // Opcode: t2STRi12 + /* 7439 */ MCD_OPC_FilterValue, + 1, + 126, + 6, + 0, // Skip to: 9106 + /* 7444 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7447 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 7554 + /* 7452 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 7455 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7477 + /* 7460 */ MCD_OPC_CheckPredicate, + 45, + 104, + 0, + 0, // Skip to: 7569 + /* 7465 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 97, + 0, + 0, // Skip to: 7569 + /* 7472 */ MCD_OPC_Decode, + 241, + 31, + 154, + 3, // Opcode: t2LDRs + /* 7477 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 7499 + /* 7482 */ MCD_OPC_CheckPredicate, + 45, + 82, + 0, + 0, // Skip to: 7569 + /* 7487 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 75, + 0, + 0, // Skip to: 7569 + /* 7494 */ MCD_OPC_Decode, + 236, + 31, + 150, + 3, // Opcode: t2LDR_POST + /* 7499 */ MCD_OPC_FilterValue, + 3, + 65, + 0, + 0, // Skip to: 7569 + /* 7504 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 7507 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 7539 + /* 7512 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 7529 + /* 7517 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 5, + 0, + 0, // Skip to: 7529 + /* 7524 */ MCD_OPC_Decode, + 235, + 31, + 156, + 3, // Opcode: t2LDRT + /* 7529 */ MCD_OPC_CheckPredicate, + 45, + 35, + 0, + 0, // Skip to: 7569 + /* 7534 */ MCD_OPC_Decode, + 239, + 31, + 155, + 3, // Opcode: t2LDRi8 + /* 7539 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 7569 + /* 7544 */ MCD_OPC_CheckPredicate, + 45, + 20, + 0, + 0, // Skip to: 7569 + /* 7549 */ MCD_OPC_Decode, + 237, + 31, + 150, + 3, // Opcode: t2LDR_PRE + /* 7554 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7569 + /* 7559 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 7569 + /* 7564 */ MCD_OPC_Decode, + 238, + 31, + 157, + 3, // Opcode: t2LDRi12 + /* 7569 */ MCD_OPC_CheckPredicate, + 45, + 252, + 5, + 0, // Skip to: 9106 + /* 7574 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 245, + 5, + 0, // Skip to: 9106 + /* 7581 */ MCD_OPC_Decode, + 240, + 31, + 158, + 3, // Opcode: t2LDRpci + /* 7586 */ MCD_OPC_FilterValue, + 2, + 163, + 2, + 0, // Skip to: 8266 + /* 7591 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 7594 */ MCD_OPC_FilterValue, + 0, + 159, + 1, + 0, // Skip to: 8014 + /* 7599 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 7602 */ MCD_OPC_FilterValue, + 0, + 77, + 0, + 0, // Skip to: 7684 + /* 7607 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7610 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7632 + /* 7615 */ MCD_OPC_CheckPredicate, + 45, + 206, + 5, + 0, // Skip to: 9106 + /* 7620 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 199, + 5, + 0, // Skip to: 9106 + /* 7627 */ MCD_OPC_Decode, + 243, + 30, + 217, + 2, // Opcode: t2ASRrr + /* 7632 */ MCD_OPC_FilterValue, + 1, + 189, + 5, + 0, // Skip to: 9106 + /* 7637 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7640 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7662 + /* 7645 */ MCD_OPC_CheckPredicate, + 53, + 176, + 5, + 0, // Skip to: 9106 + /* 7650 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 169, + 5, + 0, // Skip to: 9106 + /* 7657 */ MCD_OPC_Decode, + 128, + 33, + 159, + 3, // Opcode: t2SSUB8 + /* 7662 */ MCD_OPC_FilterValue, + 1, + 159, + 5, + 0, // Skip to: 9106 + /* 7667 */ MCD_OPC_CheckPredicate, + 53, + 154, + 5, + 0, // Skip to: 9106 + /* 7672 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 147, + 5, + 0, // Skip to: 9106 + /* 7679 */ MCD_OPC_Decode, + 255, + 32, + 159, + 3, // Opcode: t2SSUB16 + /* 7684 */ MCD_OPC_FilterValue, + 1, + 61, + 0, + 0, // Skip to: 7750 + /* 7689 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7692 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 7721 + /* 7697 */ MCD_OPC_CheckPredicate, + 53, + 124, + 5, + 0, // Skip to: 9106 + /* 7702 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 117, + 5, + 0, // Skip to: 9106 + /* 7709 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 110, + 5, + 0, // Skip to: 9106 + /* 7716 */ MCD_OPC_Decode, + 178, + 32, + 159, + 3, // Opcode: t2QSUB8 + /* 7721 */ MCD_OPC_FilterValue, + 1, + 100, + 5, + 0, // Skip to: 9106 + /* 7726 */ MCD_OPC_CheckPredicate, + 53, + 95, + 5, + 0, // Skip to: 9106 + /* 7731 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 88, + 5, + 0, // Skip to: 9106 + /* 7738 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 81, + 5, + 0, // Skip to: 9106 + /* 7745 */ MCD_OPC_Decode, + 177, + 32, + 159, + 3, // Opcode: t2QSUB16 + /* 7750 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 7816 + /* 7755 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7758 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 7787 + /* 7763 */ MCD_OPC_CheckPredicate, + 53, + 58, + 5, + 0, // Skip to: 9106 + /* 7768 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 51, + 5, + 0, // Skip to: 9106 + /* 7775 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 44, + 5, + 0, // Skip to: 9106 + /* 7782 */ MCD_OPC_Decode, + 210, + 32, + 159, + 3, // Opcode: t2SHSUB8 + /* 7787 */ MCD_OPC_FilterValue, + 1, + 34, + 5, + 0, // Skip to: 9106 + /* 7792 */ MCD_OPC_CheckPredicate, + 53, + 29, + 5, + 0, // Skip to: 9106 + /* 7797 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 22, + 5, + 0, // Skip to: 9106 + /* 7804 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 15, + 5, + 0, // Skip to: 9106 + /* 7811 */ MCD_OPC_Decode, + 209, + 32, + 159, + 3, // Opcode: t2SHSUB16 + /* 7816 */ MCD_OPC_FilterValue, + 4, + 61, + 0, + 0, // Skip to: 7882 + /* 7821 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7824 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 7853 + /* 7829 */ MCD_OPC_CheckPredicate, + 53, + 248, + 4, + 0, // Skip to: 9106 + /* 7834 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 241, + 4, + 0, // Skip to: 9106 + /* 7841 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 234, + 4, + 0, // Skip to: 9106 + /* 7848 */ MCD_OPC_Decode, + 234, + 33, + 159, + 3, // Opcode: t2USUB8 + /* 7853 */ MCD_OPC_FilterValue, + 1, + 224, + 4, + 0, // Skip to: 9106 + /* 7858 */ MCD_OPC_CheckPredicate, + 53, + 219, + 4, + 0, // Skip to: 9106 + /* 7863 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 212, + 4, + 0, // Skip to: 9106 + /* 7870 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 205, + 4, + 0, // Skip to: 9106 + /* 7877 */ MCD_OPC_Decode, + 233, + 33, + 159, + 3, // Opcode: t2USUB16 + /* 7882 */ MCD_OPC_FilterValue, + 5, + 61, + 0, + 0, // Skip to: 7948 + /* 7887 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7890 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 7919 + /* 7895 */ MCD_OPC_CheckPredicate, + 53, + 182, + 4, + 0, // Skip to: 9106 + /* 7900 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 175, + 4, + 0, // Skip to: 9106 + /* 7907 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 168, + 4, + 0, // Skip to: 9106 + /* 7914 */ MCD_OPC_Decode, + 227, + 33, + 159, + 3, // Opcode: t2UQSUB8 + /* 7919 */ MCD_OPC_FilterValue, + 1, + 158, + 4, + 0, // Skip to: 9106 + /* 7924 */ MCD_OPC_CheckPredicate, + 53, + 153, + 4, + 0, // Skip to: 9106 + /* 7929 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 146, + 4, + 0, // Skip to: 9106 + /* 7936 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 139, + 4, + 0, // Skip to: 9106 + /* 7943 */ MCD_OPC_Decode, + 226, + 33, + 159, + 3, // Opcode: t2UQSUB16 + /* 7948 */ MCD_OPC_FilterValue, + 6, + 129, + 4, + 0, // Skip to: 9106 + /* 7953 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7956 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 7985 + /* 7961 */ MCD_OPC_CheckPredicate, + 53, + 116, + 4, + 0, // Skip to: 9106 + /* 7966 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 109, + 4, + 0, // Skip to: 9106 + /* 7973 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 102, + 4, + 0, // Skip to: 9106 + /* 7980 */ MCD_OPC_Decode, + 218, + 33, + 159, + 3, // Opcode: t2UHSUB8 + /* 7985 */ MCD_OPC_FilterValue, + 1, + 92, + 4, + 0, // Skip to: 9106 + /* 7990 */ MCD_OPC_CheckPredicate, + 53, + 87, + 4, + 0, // Skip to: 9106 + /* 7995 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 80, + 4, + 0, // Skip to: 9106 + /* 8002 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 73, + 4, + 0, // Skip to: 9106 + /* 8009 */ MCD_OPC_Decode, + 217, + 33, + 159, + 3, // Opcode: t2UHSUB16 + /* 8014 */ MCD_OPC_FilterValue, + 1, + 63, + 4, + 0, // Skip to: 9106 + /* 8019 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 8022 */ MCD_OPC_FilterValue, + 0, + 117, + 0, + 0, // Skip to: 8144 + /* 8027 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 8030 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 8070 + /* 8035 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 8038 */ MCD_OPC_FilterValue, + 15, + 39, + 4, + 0, // Skip to: 9106 + /* 8043 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 8060 + /* 8048 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 8060 + /* 8055 */ MCD_OPC_Decode, + 191, + 33, + 160, + 3, // Opcode: t2SXTB + /* 8060 */ MCD_OPC_CheckPredicate, + 51, + 17, + 4, + 0, // Skip to: 9106 + /* 8065 */ MCD_OPC_Decode, + 188, + 33, + 161, + 3, // Opcode: t2SXTAB + /* 8070 */ MCD_OPC_FilterValue, + 1, + 7, + 4, + 0, // Skip to: 9106 + /* 8075 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 8078 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 8100 + /* 8083 */ MCD_OPC_CheckPredicate, + 69, + 250, + 3, + 0, // Skip to: 9106 + /* 8088 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 243, + 3, + 0, // Skip to: 9106 + /* 8095 */ MCD_OPC_Decode, + 147, + 31, + 159, + 3, // Opcode: t2CRC32B + /* 8100 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 8122 + /* 8105 */ MCD_OPC_CheckPredicate, + 69, + 228, + 3, + 0, // Skip to: 9106 + /* 8110 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 221, + 3, + 0, // Skip to: 9106 + /* 8117 */ MCD_OPC_Decode, + 151, + 31, + 159, + 3, // Opcode: t2CRC32H + /* 8122 */ MCD_OPC_FilterValue, + 2, + 211, + 3, + 0, // Skip to: 9106 + /* 8127 */ MCD_OPC_CheckPredicate, + 69, + 206, + 3, + 0, // Skip to: 9106 + /* 8132 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 199, + 3, + 0, // Skip to: 9106 + /* 8139 */ MCD_OPC_Decode, + 152, + 31, + 159, + 3, // Opcode: t2CRC32W + /* 8144 */ MCD_OPC_FilterValue, + 1, + 189, + 3, + 0, // Skip to: 9106 + /* 8149 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 8152 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 8192 + /* 8157 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 8160 */ MCD_OPC_FilterValue, + 15, + 173, + 3, + 0, // Skip to: 9106 + /* 8165 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 8182 + /* 8170 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 8182 + /* 8177 */ MCD_OPC_Decode, + 238, + 33, + 160, + 3, // Opcode: t2UXTB + /* 8182 */ MCD_OPC_CheckPredicate, + 51, + 151, + 3, + 0, // Skip to: 9106 + /* 8187 */ MCD_OPC_Decode, + 235, + 33, + 161, + 3, // Opcode: t2UXTAB + /* 8192 */ MCD_OPC_FilterValue, + 1, + 141, + 3, + 0, // Skip to: 9106 + /* 8197 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 8200 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 8222 + /* 8205 */ MCD_OPC_CheckPredicate, + 69, + 128, + 3, + 0, // Skip to: 9106 + /* 8210 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 121, + 3, + 0, // Skip to: 9106 + /* 8217 */ MCD_OPC_Decode, + 148, + 31, + 159, + 3, // Opcode: t2CRC32CB + /* 8222 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 8244 + /* 8227 */ MCD_OPC_CheckPredicate, + 69, + 106, + 3, + 0, // Skip to: 9106 + /* 8232 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 99, + 3, + 0, // Skip to: 9106 + /* 8239 */ MCD_OPC_Decode, + 149, + 31, + 159, + 3, // Opcode: t2CRC32CH + /* 8244 */ MCD_OPC_FilterValue, + 2, + 89, + 3, + 0, // Skip to: 9106 + /* 8249 */ MCD_OPC_CheckPredicate, + 69, + 84, + 3, + 0, // Skip to: 9106 + /* 8254 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 77, + 3, + 0, // Skip to: 9106 + /* 8261 */ MCD_OPC_Decode, + 150, + 31, + 159, + 3, // Opcode: t2CRC32CW + /* 8266 */ MCD_OPC_FilterValue, + 3, + 67, + 3, + 0, // Skip to: 9106 + /* 8271 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 8274 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 8394 + /* 8279 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 8282 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 8337 + /* 8287 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 8290 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 8322 + /* 8295 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 8312 + /* 8300 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 8312 + /* 8307 */ MCD_OPC_Decode, + 246, + 32, + 159, + 3, // Opcode: t2SMUSD + /* 8312 */ MCD_OPC_CheckPredicate, + 53, + 21, + 3, + 0, // Skip to: 9106 + /* 8317 */ MCD_OPC_Decode, + 227, + 32, + 164, + 3, // Opcode: t2SMLSD + /* 8322 */ MCD_OPC_FilterValue, + 1, + 11, + 3, + 0, // Skip to: 9106 + /* 8327 */ MCD_OPC_CheckPredicate, + 45, + 6, + 3, + 0, // Skip to: 9106 + /* 8332 */ MCD_OPC_Decode, + 216, + 32, + 170, + 3, // Opcode: t2SMLAL + /* 8337 */ MCD_OPC_FilterValue, + 1, + 252, + 2, + 0, // Skip to: 9106 + /* 8342 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 8345 */ MCD_OPC_FilterValue, + 0, + 244, + 2, + 0, // Skip to: 9106 + /* 8350 */ MCD_OPC_CheckPredicate, + 70, + 12, + 0, + 0, // Skip to: 8367 + /* 8355 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 8367 + /* 8362 */ MCD_OPC_Decode, + 245, + 30, + 171, + 3, // Opcode: t2AUTG + /* 8367 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 8384 + /* 8372 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 8384 + /* 8379 */ MCD_OPC_Decode, + 235, + 32, + 159, + 3, // Opcode: t2SMMUL + /* 8384 */ MCD_OPC_CheckPredicate, + 53, + 205, + 2, + 0, // Skip to: 9106 + /* 8389 */ MCD_OPC_Decode, + 231, + 32, + 164, + 3, // Opcode: t2SMMLA + /* 8394 */ MCD_OPC_FilterValue, + 1, + 100, + 0, + 0, // Skip to: 8499 + /* 8399 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 8402 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 8442 + /* 8407 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 8410 */ MCD_OPC_FilterValue, + 0, + 179, + 2, + 0, // Skip to: 9106 + /* 8415 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 8432 + /* 8420 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 8432 + /* 8427 */ MCD_OPC_Decode, + 247, + 32, + 159, + 3, // Opcode: t2SMUSDX + /* 8432 */ MCD_OPC_CheckPredicate, + 53, + 157, + 2, + 0, // Skip to: 9106 + /* 8437 */ MCD_OPC_Decode, + 228, + 32, + 164, + 3, // Opcode: t2SMLSDX + /* 8442 */ MCD_OPC_FilterValue, + 1, + 147, + 2, + 0, // Skip to: 9106 + /* 8447 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 8450 */ MCD_OPC_FilterValue, + 0, + 139, + 2, + 0, // Skip to: 9106 + /* 8455 */ MCD_OPC_CheckPredicate, + 70, + 12, + 0, + 0, // Skip to: 8472 + /* 8460 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 8472 + /* 8467 */ MCD_OPC_Decode, + 130, + 31, + 172, + 3, // Opcode: t2BXAUT + /* 8472 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 8489 + /* 8477 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 8489 + /* 8484 */ MCD_OPC_Decode, + 236, + 32, + 159, + 3, // Opcode: t2SMMULR + /* 8489 */ MCD_OPC_CheckPredicate, + 53, + 100, + 2, + 0, // Skip to: 9106 + /* 8494 */ MCD_OPC_Decode, + 232, + 32, + 164, + 3, // Opcode: t2SMMLAR + /* 8499 */ MCD_OPC_FilterValue, + 8, + 24, + 0, + 0, // Skip to: 8528 + /* 8504 */ MCD_OPC_CheckPredicate, + 53, + 85, + 2, + 0, // Skip to: 9106 + /* 8509 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 78, + 2, + 0, // Skip to: 9106 + /* 8516 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 71, + 2, + 0, // Skip to: 9106 + /* 8523 */ MCD_OPC_Decode, + 217, + 32, + 170, + 3, // Opcode: t2SMLALBB + /* 8528 */ MCD_OPC_FilterValue, + 9, + 24, + 0, + 0, // Skip to: 8557 + /* 8533 */ MCD_OPC_CheckPredicate, + 53, + 56, + 2, + 0, // Skip to: 9106 + /* 8538 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 49, + 2, + 0, // Skip to: 9106 + /* 8545 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 42, + 2, + 0, // Skip to: 9106 + /* 8552 */ MCD_OPC_Decode, + 218, + 32, + 170, + 3, // Opcode: t2SMLALBT + /* 8557 */ MCD_OPC_FilterValue, + 10, + 24, + 0, + 0, // Skip to: 8586 + /* 8562 */ MCD_OPC_CheckPredicate, + 53, + 27, + 2, + 0, // Skip to: 9106 + /* 8567 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 20, + 2, + 0, // Skip to: 9106 + /* 8574 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 13, + 2, + 0, // Skip to: 9106 + /* 8581 */ MCD_OPC_Decode, + 221, + 32, + 170, + 3, // Opcode: t2SMLALTB + /* 8586 */ MCD_OPC_FilterValue, + 11, + 24, + 0, + 0, // Skip to: 8615 + /* 8591 */ MCD_OPC_CheckPredicate, + 53, + 254, + 1, + 0, // Skip to: 9106 + /* 8596 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 247, + 1, + 0, // Skip to: 9106 + /* 8603 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 240, + 1, + 0, // Skip to: 9106 + /* 8610 */ MCD_OPC_Decode, + 222, + 32, + 170, + 3, // Opcode: t2SMLALTT + /* 8615 */ MCD_OPC_FilterValue, + 12, + 47, + 0, + 0, // Skip to: 8667 + /* 8620 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 8623 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 8645 + /* 8628 */ MCD_OPC_CheckPredicate, + 53, + 217, + 1, + 0, // Skip to: 9106 + /* 8633 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 210, + 1, + 0, // Skip to: 9106 + /* 8640 */ MCD_OPC_Decode, + 219, + 32, + 170, + 3, // Opcode: t2SMLALD + /* 8645 */ MCD_OPC_FilterValue, + 1, + 200, + 1, + 0, // Skip to: 9106 + /* 8650 */ MCD_OPC_CheckPredicate, + 53, + 195, + 1, + 0, // Skip to: 9106 + /* 8655 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 188, + 1, + 0, // Skip to: 9106 + /* 8662 */ MCD_OPC_Decode, + 229, + 32, + 170, + 3, // Opcode: t2SMLSLD + /* 8667 */ MCD_OPC_FilterValue, + 13, + 178, + 1, + 0, // Skip to: 9106 + /* 8672 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 8675 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 8697 + /* 8680 */ MCD_OPC_CheckPredicate, + 53, + 165, + 1, + 0, // Skip to: 9106 + /* 8685 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 158, + 1, + 0, // Skip to: 9106 + /* 8692 */ MCD_OPC_Decode, + 220, + 32, + 170, + 3, // Opcode: t2SMLALDX + /* 8697 */ MCD_OPC_FilterValue, + 1, + 148, + 1, + 0, // Skip to: 9106 + /* 8702 */ MCD_OPC_CheckPredicate, + 53, + 143, + 1, + 0, // Skip to: 9106 + /* 8707 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 136, + 1, + 0, // Skip to: 9106 + /* 8714 */ MCD_OPC_Decode, + 230, + 32, + 170, + 3, // Opcode: t2SMLSLDX + /* 8719 */ MCD_OPC_FilterValue, + 3, + 126, + 1, + 0, // Skip to: 9106 + /* 8724 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 8727 */ MCD_OPC_FilterValue, + 0, + 148, + 0, + 0, // Skip to: 8880 + /* 8732 */ MCD_OPC_ExtractField, + 23, + 4, // Inst{26-23} ... + /* 8735 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 8757 + /* 8740 */ MCD_OPC_CheckPredicate, + 45, + 105, + 1, + 0, // Skip to: 9106 + /* 8745 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 98, + 1, + 0, // Skip to: 9106 + /* 8752 */ MCD_OPC_Decode, + 188, + 32, + 217, + 2, // Opcode: t2RORrr + /* 8757 */ MCD_OPC_FilterValue, + 5, + 24, + 0, + 0, // Skip to: 8786 + /* 8762 */ MCD_OPC_CheckPredicate, + 53, + 83, + 1, + 0, // Skip to: 9106 + /* 8767 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 76, + 1, + 0, // Skip to: 9106 + /* 8774 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 69, + 1, + 0, // Skip to: 9106 + /* 8781 */ MCD_OPC_Decode, + 254, + 32, + 159, + 3, // Opcode: t2SSAX + /* 8786 */ MCD_OPC_FilterValue, + 6, + 67, + 0, + 0, // Skip to: 8858 + /* 8791 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 8794 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 8826 + /* 8799 */ MCD_OPC_CheckPredicate, + 70, + 12, + 0, + 0, // Skip to: 8816 + /* 8804 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 8816 + /* 8811 */ MCD_OPC_Decode, + 155, + 32, + 173, + 3, // Opcode: t2PACG + /* 8816 */ MCD_OPC_CheckPredicate, + 53, + 29, + 1, + 0, // Skip to: 9106 + /* 8821 */ MCD_OPC_Decode, + 233, + 32, + 164, + 3, // Opcode: t2SMMLS + /* 8826 */ MCD_OPC_FilterValue, + 1, + 19, + 1, + 0, // Skip to: 9106 + /* 8831 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 8848 + /* 8836 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 8848 + /* 8843 */ MCD_OPC_Decode, + 228, + 33, + 159, + 3, // Opcode: t2USAD8 + /* 8848 */ MCD_OPC_CheckPredicate, + 53, + 253, + 0, + 0, // Skip to: 9106 + /* 8853 */ MCD_OPC_Decode, + 229, + 33, + 164, + 3, // Opcode: t2USADA8 + /* 8858 */ MCD_OPC_FilterValue, + 7, + 243, + 0, + 0, // Skip to: 9106 + /* 8863 */ MCD_OPC_CheckPredicate, + 45, + 238, + 0, + 0, // Skip to: 9106 + /* 8868 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 231, + 0, + 0, // Skip to: 9106 + /* 8875 */ MCD_OPC_Decode, + 220, + 33, + 170, + 3, // Opcode: t2UMLAL + /* 8880 */ MCD_OPC_FilterValue, + 1, + 54, + 0, + 0, // Skip to: 8939 + /* 8885 */ MCD_OPC_ExtractField, + 23, + 4, // Inst{26-23} ... + /* 8888 */ MCD_OPC_FilterValue, + 5, + 24, + 0, + 0, // Skip to: 8917 + /* 8893 */ MCD_OPC_CheckPredicate, + 53, + 208, + 0, + 0, // Skip to: 9106 + /* 8898 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 201, + 0, + 0, // Skip to: 9106 + /* 8905 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 194, + 0, + 0, // Skip to: 9106 + /* 8912 */ MCD_OPC_Decode, + 175, + 32, + 159, + 3, // Opcode: t2QSAX + /* 8917 */ MCD_OPC_FilterValue, + 6, + 184, + 0, + 0, // Skip to: 9106 + /* 8922 */ MCD_OPC_CheckPredicate, + 53, + 179, + 0, + 0, // Skip to: 9106 + /* 8927 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 172, + 0, + 0, // Skip to: 9106 + /* 8934 */ MCD_OPC_Decode, + 234, + 32, + 164, + 3, // Opcode: t2SMMLSR + /* 8939 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 8975 + /* 8944 */ MCD_OPC_CheckPredicate, + 53, + 157, + 0, + 0, // Skip to: 9106 + /* 8949 */ MCD_OPC_CheckField, + 23, + 4, + 5, + 150, + 0, + 0, // Skip to: 9106 + /* 8956 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 143, + 0, + 0, // Skip to: 9106 + /* 8963 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 136, + 0, + 0, // Skip to: 9106 + /* 8970 */ MCD_OPC_Decode, + 208, + 32, + 159, + 3, // Opcode: t2SHSAX + /* 8975 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 9011 + /* 8980 */ MCD_OPC_CheckPredicate, + 53, + 121, + 0, + 0, // Skip to: 9106 + /* 8985 */ MCD_OPC_CheckField, + 23, + 4, + 5, + 114, + 0, + 0, // Skip to: 9106 + /* 8992 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 107, + 0, + 0, // Skip to: 9106 + /* 8999 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 100, + 0, + 0, // Skip to: 9106 + /* 9006 */ MCD_OPC_Decode, + 232, + 33, + 159, + 3, // Opcode: t2USAX + /* 9011 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 9047 + /* 9016 */ MCD_OPC_CheckPredicate, + 53, + 85, + 0, + 0, // Skip to: 9106 + /* 9021 */ MCD_OPC_CheckField, + 23, + 4, + 5, + 78, + 0, + 0, // Skip to: 9106 + /* 9028 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 71, + 0, + 0, // Skip to: 9106 + /* 9035 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 64, + 0, + 0, // Skip to: 9106 + /* 9042 */ MCD_OPC_Decode, + 225, + 33, + 159, + 3, // Opcode: t2UQSAX + /* 9047 */ MCD_OPC_FilterValue, + 6, + 54, + 0, + 0, // Skip to: 9106 + /* 9052 */ MCD_OPC_ExtractField, + 23, + 4, // Inst{26-23} ... + /* 9055 */ MCD_OPC_FilterValue, + 5, + 24, + 0, + 0, // Skip to: 9084 + /* 9060 */ MCD_OPC_CheckPredicate, + 53, + 41, + 0, + 0, // Skip to: 9106 + /* 9065 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 34, + 0, + 0, // Skip to: 9106 + /* 9072 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 27, + 0, + 0, // Skip to: 9106 + /* 9079 */ MCD_OPC_Decode, + 216, + 33, + 159, + 3, // Opcode: t2UHSAX + /* 9084 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 9106 + /* 9089 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 9106 + /* 9094 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 5, + 0, + 0, // Skip to: 9106 + /* 9101 */ MCD_OPC_Decode, + 219, + 33, + 170, + 3, // Opcode: t2UMAAL + /* 9106 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumb2CDE32[] = { + /* 0 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 3 */ MCD_OPC_FilterValue, + 118, + 24, + 1, + 0, // Skip to: 288 + /* 8 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 151, + 0, + 0, // Skip to: 167 + /* 16 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 71 + /* 24 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 27 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 49 + /* 32 */ MCD_OPC_CheckPredicate, + 71, + 112, + 3, + 0, // Skip to: 917 + /* 37 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 105, + 3, + 0, // Skip to: 917 + /* 44 */ MCD_OPC_Decode, + 254, + 5, + 174, + 3, // Opcode: CDE_VCX1_fpsp + /* 49 */ MCD_OPC_FilterValue, + 3, + 95, + 3, + 0, // Skip to: 917 + /* 54 */ MCD_OPC_CheckPredicate, + 71, + 90, + 3, + 0, // Skip to: 917 + /* 59 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 83, + 3, + 0, // Skip to: 917 + /* 66 */ MCD_OPC_Decode, + 132, + 6, + 175, + 3, // Opcode: CDE_VCX2_fpsp + /* 71 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 93 + /* 76 */ MCD_OPC_CheckPredicate, + 71, + 68, + 3, + 0, // Skip to: 917 + /* 81 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 61, + 3, + 0, // Skip to: 917 + /* 88 */ MCD_OPC_Decode, + 138, + 6, + 176, + 3, // Opcode: CDE_VCX3_fpsp + /* 93 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 145 + /* 98 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 101 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 123 + /* 106 */ MCD_OPC_CheckPredicate, + 71, + 38, + 3, + 0, // Skip to: 917 + /* 111 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 31, + 3, + 0, // Skip to: 917 + /* 118 */ MCD_OPC_Decode, + 253, + 5, + 177, + 3, // Opcode: CDE_VCX1_fpdp + /* 123 */ MCD_OPC_FilterValue, + 3, + 21, + 3, + 0, // Skip to: 917 + /* 128 */ MCD_OPC_CheckPredicate, + 71, + 16, + 3, + 0, // Skip to: 917 + /* 133 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 9, + 3, + 0, // Skip to: 917 + /* 140 */ MCD_OPC_Decode, + 131, + 6, + 178, + 3, // Opcode: CDE_VCX2_fpdp + /* 145 */ MCD_OPC_FilterValue, + 3, + 255, + 2, + 0, // Skip to: 917 + /* 150 */ MCD_OPC_CheckPredicate, + 71, + 250, + 2, + 0, // Skip to: 917 + /* 155 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 243, + 2, + 0, // Skip to: 917 + /* 162 */ MCD_OPC_Decode, + 137, + 6, + 179, + 3, // Opcode: CDE_VCX3_fpdp + /* 167 */ MCD_OPC_FilterValue, + 1, + 233, + 2, + 0, // Skip to: 917 + /* 172 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 175 */ MCD_OPC_FilterValue, + 0, + 66, + 0, + 0, // Skip to: 246 + /* 180 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 183 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 211 + /* 188 */ MCD_OPC_CheckPredicate, + 72, + 212, + 2, + 0, // Skip to: 917 + /* 193 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 205, + 2, + 0, // Skip to: 917 + /* 200 */ MCD_OPC_SoftFail, + 128, + 128, + 128, + 2 /* 0x400000 */, + 0, + /* 206 */ MCD_OPC_Decode, + 255, + 5, + 180, + 3, // Opcode: CDE_VCX1_vec + /* 211 */ MCD_OPC_FilterValue, + 3, + 189, + 2, + 0, // Skip to: 917 + /* 216 */ MCD_OPC_CheckPredicate, + 72, + 184, + 2, + 0, // Skip to: 917 + /* 221 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 177, + 2, + 0, // Skip to: 917 + /* 228 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 170, + 2, + 0, // Skip to: 917 + /* 235 */ MCD_OPC_SoftFail, + 160, + 128, + 128, + 2 /* 0x400020 */, + 0, + /* 241 */ MCD_OPC_Decode, + 133, + 6, + 181, + 3, // Opcode: CDE_VCX2_vec + /* 246 */ MCD_OPC_FilterValue, + 1, + 154, + 2, + 0, // Skip to: 917 + /* 251 */ MCD_OPC_CheckPredicate, + 72, + 149, + 2, + 0, // Skip to: 917 + /* 256 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 142, + 2, + 0, // Skip to: 917 + /* 263 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 135, + 2, + 0, // Skip to: 917 + /* 270 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 128, + 2, + 0, // Skip to: 917 + /* 277 */ MCD_OPC_SoftFail, + 160, + 129, + 128, + 2 /* 0x4000a0 */, + 0, + /* 283 */ MCD_OPC_Decode, + 139, + 6, + 182, + 3, // Opcode: CDE_VCX3_vec + /* 288 */ MCD_OPC_FilterValue, + 119, + 167, + 0, + 0, // Skip to: 460 + /* 293 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 296 */ MCD_OPC_FilterValue, + 0, + 77, + 0, + 0, // Skip to: 378 + /* 301 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 304 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 356 + /* 309 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 312 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 334 + /* 317 */ MCD_OPC_CheckPredicate, + 73, + 83, + 2, + 0, // Skip to: 917 + /* 322 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 76, + 2, + 0, // Skip to: 917 + /* 329 */ MCD_OPC_Decode, + 238, + 5, + 183, + 3, // Opcode: CDE_CX1 + /* 334 */ MCD_OPC_FilterValue, + 1, + 66, + 2, + 0, // Skip to: 917 + /* 339 */ MCD_OPC_CheckPredicate, + 73, + 61, + 2, + 0, // Skip to: 917 + /* 344 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 54, + 2, + 0, // Skip to: 917 + /* 351 */ MCD_OPC_Decode, + 242, + 5, + 184, + 3, // Opcode: CDE_CX2 + /* 356 */ MCD_OPC_FilterValue, + 1, + 44, + 2, + 0, // Skip to: 917 + /* 361 */ MCD_OPC_CheckPredicate, + 73, + 39, + 2, + 0, // Skip to: 917 + /* 366 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 32, + 2, + 0, // Skip to: 917 + /* 373 */ MCD_OPC_Decode, + 246, + 5, + 185, + 3, // Opcode: CDE_CX3 + /* 378 */ MCD_OPC_FilterValue, + 1, + 22, + 2, + 0, // Skip to: 917 + /* 383 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 386 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 438 + /* 391 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 394 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 416 + /* 399 */ MCD_OPC_CheckPredicate, + 73, + 1, + 2, + 0, // Skip to: 917 + /* 404 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 250, + 1, + 0, // Skip to: 917 + /* 411 */ MCD_OPC_Decode, + 240, + 5, + 186, + 3, // Opcode: CDE_CX1D + /* 416 */ MCD_OPC_FilterValue, + 1, + 240, + 1, + 0, // Skip to: 917 + /* 421 */ MCD_OPC_CheckPredicate, + 73, + 235, + 1, + 0, // Skip to: 917 + /* 426 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 228, + 1, + 0, // Skip to: 917 + /* 433 */ MCD_OPC_Decode, + 244, + 5, + 187, + 3, // Opcode: CDE_CX2D + /* 438 */ MCD_OPC_FilterValue, + 1, + 218, + 1, + 0, // Skip to: 917 + /* 443 */ MCD_OPC_CheckPredicate, + 73, + 213, + 1, + 0, // Skip to: 917 + /* 448 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 206, + 1, + 0, // Skip to: 917 + /* 455 */ MCD_OPC_Decode, + 248, + 5, + 188, + 3, // Opcode: CDE_CX3D + /* 460 */ MCD_OPC_FilterValue, + 126, + 24, + 1, + 0, // Skip to: 745 + /* 465 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 468 */ MCD_OPC_FilterValue, + 0, + 151, + 0, + 0, // Skip to: 624 + /* 473 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 476 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 528 + /* 481 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 484 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 506 + /* 489 */ MCD_OPC_CheckPredicate, + 71, + 167, + 1, + 0, // Skip to: 917 + /* 494 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 160, + 1, + 0, // Skip to: 917 + /* 501 */ MCD_OPC_Decode, + 251, + 5, + 189, + 3, // Opcode: CDE_VCX1A_fpsp + /* 506 */ MCD_OPC_FilterValue, + 3, + 150, + 1, + 0, // Skip to: 917 + /* 511 */ MCD_OPC_CheckPredicate, + 71, + 145, + 1, + 0, // Skip to: 917 + /* 516 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 138, + 1, + 0, // Skip to: 917 + /* 523 */ MCD_OPC_Decode, + 129, + 6, + 190, + 3, // Opcode: CDE_VCX2A_fpsp + /* 528 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 550 + /* 533 */ MCD_OPC_CheckPredicate, + 71, + 123, + 1, + 0, // Skip to: 917 + /* 538 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 116, + 1, + 0, // Skip to: 917 + /* 545 */ MCD_OPC_Decode, + 135, + 6, + 191, + 3, // Opcode: CDE_VCX3A_fpsp + /* 550 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 602 + /* 555 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 558 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 580 + /* 563 */ MCD_OPC_CheckPredicate, + 71, + 93, + 1, + 0, // Skip to: 917 + /* 568 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 86, + 1, + 0, // Skip to: 917 + /* 575 */ MCD_OPC_Decode, + 250, + 5, + 192, + 3, // Opcode: CDE_VCX1A_fpdp + /* 580 */ MCD_OPC_FilterValue, + 3, + 76, + 1, + 0, // Skip to: 917 + /* 585 */ MCD_OPC_CheckPredicate, + 71, + 71, + 1, + 0, // Skip to: 917 + /* 590 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 64, + 1, + 0, // Skip to: 917 + /* 597 */ MCD_OPC_Decode, + 128, + 6, + 193, + 3, // Opcode: CDE_VCX2A_fpdp + /* 602 */ MCD_OPC_FilterValue, + 3, + 54, + 1, + 0, // Skip to: 917 + /* 607 */ MCD_OPC_CheckPredicate, + 71, + 49, + 1, + 0, // Skip to: 917 + /* 612 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 42, + 1, + 0, // Skip to: 917 + /* 619 */ MCD_OPC_Decode, + 134, + 6, + 194, + 3, // Opcode: CDE_VCX3A_fpdp + /* 624 */ MCD_OPC_FilterValue, + 1, + 32, + 1, + 0, // Skip to: 917 + /* 629 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 632 */ MCD_OPC_FilterValue, + 0, + 66, + 0, + 0, // Skip to: 703 + /* 637 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 640 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 668 + /* 645 */ MCD_OPC_CheckPredicate, + 72, + 11, + 1, + 0, // Skip to: 917 + /* 650 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 1, + 0, // Skip to: 917 + /* 657 */ MCD_OPC_SoftFail, + 128, + 128, + 128, + 2 /* 0x400000 */, + 0, + /* 663 */ MCD_OPC_Decode, + 252, + 5, + 195, + 3, // Opcode: CDE_VCX1A_vec + /* 668 */ MCD_OPC_FilterValue, + 3, + 244, + 0, + 0, // Skip to: 917 + /* 673 */ MCD_OPC_CheckPredicate, + 72, + 239, + 0, + 0, // Skip to: 917 + /* 678 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 232, + 0, + 0, // Skip to: 917 + /* 685 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 225, + 0, + 0, // Skip to: 917 + /* 692 */ MCD_OPC_SoftFail, + 160, + 128, + 128, + 2 /* 0x400020 */, + 0, + /* 698 */ MCD_OPC_Decode, + 130, + 6, + 196, + 3, // Opcode: CDE_VCX2A_vec + /* 703 */ MCD_OPC_FilterValue, + 1, + 209, + 0, + 0, // Skip to: 917 + /* 708 */ MCD_OPC_CheckPredicate, + 72, + 204, + 0, + 0, // Skip to: 917 + /* 713 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 197, + 0, + 0, // Skip to: 917 + /* 720 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 190, + 0, + 0, // Skip to: 917 + /* 727 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 183, + 0, + 0, // Skip to: 917 + /* 734 */ MCD_OPC_SoftFail, + 160, + 129, + 128, + 2 /* 0x4000a0 */, + 0, + /* 740 */ MCD_OPC_Decode, + 136, + 6, + 197, + 3, // Opcode: CDE_VCX3A_vec + /* 745 */ MCD_OPC_FilterValue, + 127, + 167, + 0, + 0, // Skip to: 917 + /* 750 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 753 */ MCD_OPC_FilterValue, + 0, + 77, + 0, + 0, // Skip to: 835 + /* 758 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 761 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 813 + /* 766 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 769 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 791 + /* 774 */ MCD_OPC_CheckPredicate, + 73, + 138, + 0, + 0, // Skip to: 917 + /* 779 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 131, + 0, + 0, // Skip to: 917 + /* 786 */ MCD_OPC_Decode, + 239, + 5, + 198, + 3, // Opcode: CDE_CX1A + /* 791 */ MCD_OPC_FilterValue, + 1, + 121, + 0, + 0, // Skip to: 917 + /* 796 */ MCD_OPC_CheckPredicate, + 73, + 116, + 0, + 0, // Skip to: 917 + /* 801 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 109, + 0, + 0, // Skip to: 917 + /* 808 */ MCD_OPC_Decode, + 243, + 5, + 199, + 3, // Opcode: CDE_CX2A + /* 813 */ MCD_OPC_FilterValue, + 1, + 99, + 0, + 0, // Skip to: 917 + /* 818 */ MCD_OPC_CheckPredicate, + 73, + 94, + 0, + 0, // Skip to: 917 + /* 823 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 87, + 0, + 0, // Skip to: 917 + /* 830 */ MCD_OPC_Decode, + 247, + 5, + 200, + 3, // Opcode: CDE_CX3A + /* 835 */ MCD_OPC_FilterValue, + 1, + 77, + 0, + 0, // Skip to: 917 + /* 840 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 843 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 895 + /* 848 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 851 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 873 + /* 856 */ MCD_OPC_CheckPredicate, + 73, + 56, + 0, + 0, // Skip to: 917 + /* 861 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 49, + 0, + 0, // Skip to: 917 + /* 868 */ MCD_OPC_Decode, + 241, + 5, + 201, + 3, // Opcode: CDE_CX1DA + /* 873 */ MCD_OPC_FilterValue, + 1, + 39, + 0, + 0, // Skip to: 917 + /* 878 */ MCD_OPC_CheckPredicate, + 73, + 34, + 0, + 0, // Skip to: 917 + /* 883 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 27, + 0, + 0, // Skip to: 917 + /* 890 */ MCD_OPC_Decode, + 245, + 5, + 202, + 3, // Opcode: CDE_CX2DA + /* 895 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 917 + /* 900 */ MCD_OPC_CheckPredicate, + 73, + 12, + 0, + 0, // Skip to: 917 + /* 905 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 5, + 0, + 0, // Skip to: 917 + /* 912 */ MCD_OPC_Decode, + 249, + 5, + 203, + 3, // Opcode: CDE_CX3DA + /* 917 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumb2CoProc32[] = { + /* 0 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 3 */ MCD_OPC_FilterValue, + 236, + 1, + 175, + 0, + 0, // Skip to: 184 + /* 9 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 12 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 33 + /* 17 */ MCD_OPC_CheckPredicate, + 45, + 191, + 2, + 0, // Skip to: 725 + /* 22 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 184, + 2, + 0, // Skip to: 725 + /* 29 */ MCD_OPC_Decode, + 142, + 33, + 92, // Opcode: t2STC_OPTION + /* 33 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 54 + /* 38 */ MCD_OPC_CheckPredicate, + 45, + 170, + 2, + 0, // Skip to: 725 + /* 43 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 163, + 2, + 0, // Skip to: 725 + /* 50 */ MCD_OPC_Decode, + 193, + 31, + 92, // Opcode: t2LDC_OPTION + /* 54 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 68 + /* 59 */ MCD_OPC_CheckPredicate, + 45, + 149, + 2, + 0, // Skip to: 725 + /* 64 */ MCD_OPC_Decode, + 143, + 33, + 92, // Opcode: t2STC_POST + /* 68 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 82 + /* 73 */ MCD_OPC_CheckPredicate, + 45, + 135, + 2, + 0, // Skip to: 725 + /* 78 */ MCD_OPC_Decode, + 194, + 31, + 92, // Opcode: t2LDC_POST + /* 82 */ MCD_OPC_FilterValue, + 4, + 32, + 0, + 0, // Skip to: 119 + /* 87 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 90 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 105 + /* 95 */ MCD_OPC_CheckPredicate, + 45, + 113, + 2, + 0, // Skip to: 725 + /* 100 */ MCD_OPC_Decode, + 250, + 31, + 204, + 3, // Opcode: t2MCRR + /* 105 */ MCD_OPC_FilterValue, + 1, + 103, + 2, + 0, // Skip to: 725 + /* 110 */ MCD_OPC_CheckPredicate, + 45, + 98, + 2, + 0, // Skip to: 725 + /* 115 */ MCD_OPC_Decode, + 138, + 33, + 92, // Opcode: t2STCL_OPTION + /* 119 */ MCD_OPC_FilterValue, + 5, + 32, + 0, + 0, // Skip to: 156 + /* 124 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 127 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 142 + /* 132 */ MCD_OPC_CheckPredicate, + 45, + 76, + 2, + 0, // Skip to: 725 + /* 137 */ MCD_OPC_Decode, + 134, + 32, + 205, + 3, // Opcode: t2MRRC + /* 142 */ MCD_OPC_FilterValue, + 1, + 66, + 2, + 0, // Skip to: 725 + /* 147 */ MCD_OPC_CheckPredicate, + 45, + 61, + 2, + 0, // Skip to: 725 + /* 152 */ MCD_OPC_Decode, + 189, + 31, + 92, // Opcode: t2LDCL_OPTION + /* 156 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 170 + /* 161 */ MCD_OPC_CheckPredicate, + 45, + 47, + 2, + 0, // Skip to: 725 + /* 166 */ MCD_OPC_Decode, + 139, + 33, + 92, // Opcode: t2STCL_POST + /* 170 */ MCD_OPC_FilterValue, + 7, + 38, + 2, + 0, // Skip to: 725 + /* 175 */ MCD_OPC_CheckPredicate, + 45, + 33, + 2, + 0, // Skip to: 725 + /* 180 */ MCD_OPC_Decode, + 190, + 31, + 92, // Opcode: t2LDCL_POST + /* 184 */ MCD_OPC_FilterValue, + 237, + 1, + 115, + 0, + 0, // Skip to: 305 + /* 190 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 193 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 207 + /* 198 */ MCD_OPC_CheckPredicate, + 45, + 10, + 2, + 0, // Skip to: 725 + /* 203 */ MCD_OPC_Decode, + 141, + 33, + 92, // Opcode: t2STC_OFFSET + /* 207 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 221 + /* 212 */ MCD_OPC_CheckPredicate, + 45, + 252, + 1, + 0, // Skip to: 725 + /* 217 */ MCD_OPC_Decode, + 192, + 31, + 92, // Opcode: t2LDC_OFFSET + /* 221 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 235 + /* 226 */ MCD_OPC_CheckPredicate, + 45, + 238, + 1, + 0, // Skip to: 725 + /* 231 */ MCD_OPC_Decode, + 144, + 33, + 92, // Opcode: t2STC_PRE + /* 235 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 249 + /* 240 */ MCD_OPC_CheckPredicate, + 45, + 224, + 1, + 0, // Skip to: 725 + /* 245 */ MCD_OPC_Decode, + 195, + 31, + 92, // Opcode: t2LDC_PRE + /* 249 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 263 + /* 254 */ MCD_OPC_CheckPredicate, + 45, + 210, + 1, + 0, // Skip to: 725 + /* 259 */ MCD_OPC_Decode, + 137, + 33, + 92, // Opcode: t2STCL_OFFSET + /* 263 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 277 + /* 268 */ MCD_OPC_CheckPredicate, + 45, + 196, + 1, + 0, // Skip to: 725 + /* 273 */ MCD_OPC_Decode, + 188, + 31, + 92, // Opcode: t2LDCL_OFFSET + /* 277 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 291 + /* 282 */ MCD_OPC_CheckPredicate, + 45, + 182, + 1, + 0, // Skip to: 725 + /* 287 */ MCD_OPC_Decode, + 140, + 33, + 92, // Opcode: t2STCL_PRE + /* 291 */ MCD_OPC_FilterValue, + 7, + 173, + 1, + 0, // Skip to: 725 + /* 296 */ MCD_OPC_CheckPredicate, + 45, + 168, + 1, + 0, // Skip to: 725 + /* 301 */ MCD_OPC_Decode, + 191, + 31, + 92, // Opcode: t2LDCL_PRE + /* 305 */ MCD_OPC_FilterValue, + 238, + 1, + 53, + 0, + 0, // Skip to: 364 + /* 311 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 314 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 328 + /* 319 */ MCD_OPC_CheckPredicate, + 74, + 145, + 1, + 0, // Skip to: 725 + /* 324 */ MCD_OPC_Decode, + 133, + 31, + 93, // Opcode: t2CDP + /* 328 */ MCD_OPC_FilterValue, + 1, + 136, + 1, + 0, // Skip to: 725 + /* 333 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 336 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 350 + /* 341 */ MCD_OPC_CheckPredicate, + 45, + 123, + 1, + 0, // Skip to: 725 + /* 346 */ MCD_OPC_Decode, + 248, + 31, + 95, // Opcode: t2MCR + /* 350 */ MCD_OPC_FilterValue, + 1, + 114, + 1, + 0, // Skip to: 725 + /* 355 */ MCD_OPC_CheckPredicate, + 45, + 109, + 1, + 0, // Skip to: 725 + /* 360 */ MCD_OPC_Decode, + 132, + 32, + 97, // Opcode: t2MRC + /* 364 */ MCD_OPC_FilterValue, + 252, + 1, + 175, + 0, + 0, // Skip to: 545 + /* 370 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 373 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 394 + /* 378 */ MCD_OPC_CheckPredicate, + 75, + 86, + 1, + 0, // Skip to: 725 + /* 383 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 79, + 1, + 0, // Skip to: 725 + /* 390 */ MCD_OPC_Decode, + 134, + 33, + 92, // Opcode: t2STC2_OPTION + /* 394 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 415 + /* 399 */ MCD_OPC_CheckPredicate, + 75, + 65, + 1, + 0, // Skip to: 725 + /* 404 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 58, + 1, + 0, // Skip to: 725 + /* 411 */ MCD_OPC_Decode, + 185, + 31, + 92, // Opcode: t2LDC2_OPTION + /* 415 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 429 + /* 420 */ MCD_OPC_CheckPredicate, + 75, + 44, + 1, + 0, // Skip to: 725 + /* 425 */ MCD_OPC_Decode, + 135, + 33, + 92, // Opcode: t2STC2_POST + /* 429 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 443 + /* 434 */ MCD_OPC_CheckPredicate, + 75, + 30, + 1, + 0, // Skip to: 725 + /* 439 */ MCD_OPC_Decode, + 186, + 31, + 92, // Opcode: t2LDC2_POST + /* 443 */ MCD_OPC_FilterValue, + 4, + 32, + 0, + 0, // Skip to: 480 + /* 448 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 451 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 466 + /* 456 */ MCD_OPC_CheckPredicate, + 74, + 8, + 1, + 0, // Skip to: 725 + /* 461 */ MCD_OPC_Decode, + 251, + 31, + 204, + 3, // Opcode: t2MCRR2 + /* 466 */ MCD_OPC_FilterValue, + 1, + 254, + 0, + 0, // Skip to: 725 + /* 471 */ MCD_OPC_CheckPredicate, + 75, + 249, + 0, + 0, // Skip to: 725 + /* 476 */ MCD_OPC_Decode, + 130, + 33, + 92, // Opcode: t2STC2L_OPTION + /* 480 */ MCD_OPC_FilterValue, + 5, + 32, + 0, + 0, // Skip to: 517 + /* 485 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 488 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 503 + /* 493 */ MCD_OPC_CheckPredicate, + 74, + 227, + 0, + 0, // Skip to: 725 + /* 498 */ MCD_OPC_Decode, + 135, + 32, + 205, + 3, // Opcode: t2MRRC2 + /* 503 */ MCD_OPC_FilterValue, + 1, + 217, + 0, + 0, // Skip to: 725 + /* 508 */ MCD_OPC_CheckPredicate, + 75, + 212, + 0, + 0, // Skip to: 725 + /* 513 */ MCD_OPC_Decode, + 181, + 31, + 92, // Opcode: t2LDC2L_OPTION + /* 517 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 531 + /* 522 */ MCD_OPC_CheckPredicate, + 75, + 198, + 0, + 0, // Skip to: 725 + /* 527 */ MCD_OPC_Decode, + 131, + 33, + 92, // Opcode: t2STC2L_POST + /* 531 */ MCD_OPC_FilterValue, + 7, + 189, + 0, + 0, // Skip to: 725 + /* 536 */ MCD_OPC_CheckPredicate, + 75, + 184, + 0, + 0, // Skip to: 725 + /* 541 */ MCD_OPC_Decode, + 182, + 31, + 92, // Opcode: t2LDC2L_POST + /* 545 */ MCD_OPC_FilterValue, + 253, + 1, + 115, + 0, + 0, // Skip to: 666 + /* 551 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 554 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 568 + /* 559 */ MCD_OPC_CheckPredicate, + 75, + 161, + 0, + 0, // Skip to: 725 + /* 564 */ MCD_OPC_Decode, + 133, + 33, + 92, // Opcode: t2STC2_OFFSET + /* 568 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 582 + /* 573 */ MCD_OPC_CheckPredicate, + 75, + 147, + 0, + 0, // Skip to: 725 + /* 578 */ MCD_OPC_Decode, + 184, + 31, + 92, // Opcode: t2LDC2_OFFSET + /* 582 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 596 + /* 587 */ MCD_OPC_CheckPredicate, + 75, + 133, + 0, + 0, // Skip to: 725 + /* 592 */ MCD_OPC_Decode, + 136, + 33, + 92, // Opcode: t2STC2_PRE + /* 596 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 610 + /* 601 */ MCD_OPC_CheckPredicate, + 75, + 119, + 0, + 0, // Skip to: 725 + /* 606 */ MCD_OPC_Decode, + 187, + 31, + 92, // Opcode: t2LDC2_PRE + /* 610 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 624 + /* 615 */ MCD_OPC_CheckPredicate, + 75, + 105, + 0, + 0, // Skip to: 725 + /* 620 */ MCD_OPC_Decode, + 129, + 33, + 92, // Opcode: t2STC2L_OFFSET + /* 624 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 638 + /* 629 */ MCD_OPC_CheckPredicate, + 75, + 91, + 0, + 0, // Skip to: 725 + /* 634 */ MCD_OPC_Decode, + 180, + 31, + 92, // Opcode: t2LDC2L_OFFSET + /* 638 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 652 + /* 643 */ MCD_OPC_CheckPredicate, + 75, + 77, + 0, + 0, // Skip to: 725 + /* 648 */ MCD_OPC_Decode, + 132, + 33, + 92, // Opcode: t2STC2L_PRE + /* 652 */ MCD_OPC_FilterValue, + 7, + 68, + 0, + 0, // Skip to: 725 + /* 657 */ MCD_OPC_CheckPredicate, + 75, + 63, + 0, + 0, // Skip to: 725 + /* 662 */ MCD_OPC_Decode, + 183, + 31, + 92, // Opcode: t2LDC2L_PRE + /* 666 */ MCD_OPC_FilterValue, + 254, + 1, + 53, + 0, + 0, // Skip to: 725 + /* 672 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 675 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 689 + /* 680 */ MCD_OPC_CheckPredicate, + 74, + 40, + 0, + 0, // Skip to: 725 + /* 685 */ MCD_OPC_Decode, + 134, + 31, + 93, // Opcode: t2CDP2 + /* 689 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 725 + /* 694 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 697 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 711 + /* 702 */ MCD_OPC_CheckPredicate, + 74, + 18, + 0, + 0, // Skip to: 725 + /* 707 */ MCD_OPC_Decode, + 249, + 31, + 95, // Opcode: t2MCR2 + /* 711 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 725 + /* 716 */ MCD_OPC_CheckPredicate, + 74, + 4, + 0, + 0, // Skip to: 725 + /* 721 */ MCD_OPC_Decode, + 133, + 32, + 97, // Opcode: t2MRC2 + /* 725 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumbSBit16[] = { + /* 0 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18 + /* 8 */ MCD_OPC_CheckPredicate, + 35, + 95, + 1, + 0, // Skip to: 364 + /* 13 */ MCD_OPC_Decode, + 161, + 34, + 206, + 3, // Opcode: tLSLri + /* 18 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 33 + /* 23 */ MCD_OPC_CheckPredicate, + 35, + 80, + 1, + 0, // Skip to: 364 + /* 28 */ MCD_OPC_Decode, + 163, + 34, + 206, + 3, // Opcode: tLSRri + /* 33 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 48 + /* 38 */ MCD_OPC_CheckPredicate, + 35, + 65, + 1, + 0, // Skip to: 364 + /* 43 */ MCD_OPC_Decode, + 253, + 33, + 206, + 3, // Opcode: tASRri + /* 48 */ MCD_OPC_FilterValue, + 3, + 63, + 0, + 0, // Skip to: 116 + /* 53 */ MCD_OPC_ExtractField, + 9, + 2, // Inst{10-9} ... + /* 56 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 71 + /* 61 */ MCD_OPC_CheckPredicate, + 35, + 42, + 1, + 0, // Skip to: 364 + /* 66 */ MCD_OPC_Decode, + 248, + 33, + 207, + 3, // Opcode: tADDrr + /* 71 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 86 + /* 76 */ MCD_OPC_CheckPredicate, + 35, + 27, + 1, + 0, // Skip to: 364 + /* 81 */ MCD_OPC_Decode, + 191, + 34, + 207, + 3, // Opcode: tSUBrr + /* 86 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 101 + /* 91 */ MCD_OPC_CheckPredicate, + 35, + 12, + 1, + 0, // Skip to: 364 + /* 96 */ MCD_OPC_Decode, + 244, + 33, + 208, + 3, // Opcode: tADDi3 + /* 101 */ MCD_OPC_FilterValue, + 3, + 2, + 1, + 0, // Skip to: 364 + /* 106 */ MCD_OPC_CheckPredicate, + 35, + 253, + 0, + 0, // Skip to: 364 + /* 111 */ MCD_OPC_Decode, + 189, + 34, + 208, + 3, // Opcode: tSUBi3 + /* 116 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 131 + /* 121 */ MCD_OPC_CheckPredicate, + 35, + 238, + 0, + 0, // Skip to: 364 + /* 126 */ MCD_OPC_Decode, + 166, + 34, + 185, + 2, // Opcode: tMOVi8 + /* 131 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 146 + /* 136 */ MCD_OPC_CheckPredicate, + 35, + 223, + 0, + 0, // Skip to: 364 + /* 141 */ MCD_OPC_Decode, + 245, + 33, + 209, + 3, // Opcode: tADDi8 + /* 146 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 161 + /* 151 */ MCD_OPC_CheckPredicate, + 35, + 208, + 0, + 0, // Skip to: 364 + /* 156 */ MCD_OPC_Decode, + 190, + 34, + 209, + 3, // Opcode: tSUBi8 + /* 161 */ MCD_OPC_FilterValue, + 8, + 198, + 0, + 0, // Skip to: 364 + /* 166 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 169 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 184 + /* 174 */ MCD_OPC_CheckPredicate, + 35, + 185, + 0, + 0, // Skip to: 364 + /* 179 */ MCD_OPC_Decode, + 252, + 33, + 210, + 3, // Opcode: tAND + /* 184 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 199 + /* 189 */ MCD_OPC_CheckPredicate, + 35, + 170, + 0, + 0, // Skip to: 364 + /* 194 */ MCD_OPC_Decode, + 144, + 34, + 210, + 3, // Opcode: tEOR + /* 199 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 214 + /* 204 */ MCD_OPC_CheckPredicate, + 35, + 155, + 0, + 0, // Skip to: 364 + /* 209 */ MCD_OPC_Decode, + 162, + 34, + 210, + 3, // Opcode: tLSLrr + /* 214 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 229 + /* 219 */ MCD_OPC_CheckPredicate, + 35, + 140, + 0, + 0, // Skip to: 364 + /* 224 */ MCD_OPC_Decode, + 164, + 34, + 210, + 3, // Opcode: tLSRrr + /* 229 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 244 + /* 234 */ MCD_OPC_CheckPredicate, + 35, + 125, + 0, + 0, // Skip to: 364 + /* 239 */ MCD_OPC_Decode, + 254, + 33, + 210, + 3, // Opcode: tASRrr + /* 244 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 259 + /* 249 */ MCD_OPC_CheckPredicate, + 35, + 110, + 0, + 0, // Skip to: 364 + /* 254 */ MCD_OPC_Decode, + 242, + 33, + 210, + 3, // Opcode: tADC + /* 259 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 274 + /* 264 */ MCD_OPC_CheckPredicate, + 35, + 95, + 0, + 0, // Skip to: 364 + /* 269 */ MCD_OPC_Decode, + 179, + 34, + 210, + 3, // Opcode: tSBC + /* 274 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 289 + /* 279 */ MCD_OPC_CheckPredicate, + 35, + 80, + 0, + 0, // Skip to: 364 + /* 284 */ MCD_OPC_Decode, + 177, + 34, + 210, + 3, // Opcode: tROR + /* 289 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 304 + /* 294 */ MCD_OPC_CheckPredicate, + 35, + 65, + 0, + 0, // Skip to: 364 + /* 299 */ MCD_OPC_Decode, + 178, + 34, + 184, + 2, // Opcode: tRSB + /* 304 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 319 + /* 309 */ MCD_OPC_CheckPredicate, + 35, + 50, + 0, + 0, // Skip to: 364 + /* 314 */ MCD_OPC_Decode, + 170, + 34, + 210, + 3, // Opcode: tORR + /* 319 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 334 + /* 324 */ MCD_OPC_CheckPredicate, + 35, + 35, + 0, + 0, // Skip to: 364 + /* 329 */ MCD_OPC_Decode, + 168, + 34, + 211, + 3, // Opcode: tMUL + /* 334 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 349 + /* 339 */ MCD_OPC_CheckPredicate, + 35, + 20, + 0, + 0, // Skip to: 364 + /* 344 */ MCD_OPC_Decode, + 128, + 34, + 210, + 3, // Opcode: tBIC + /* 349 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 364 + /* 354 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 364 + /* 359 */ MCD_OPC_Decode, + 169, + 34, + 184, + 2, // Opcode: tMVN + /* 364 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableVFP32[] = { + /* 0 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 3 */ MCD_OPC_FilterValue, + 9, + 112, + 4, + 0, // Skip to: 1144 + /* 8 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 130, + 0, + 0, // Skip to: 146 + /* 16 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 19 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 34 + /* 24 */ MCD_OPC_CheckPredicate, + 76, + 222, + 21, + 0, // Skip to: 5627 + /* 29 */ MCD_OPC_Decode, + 210, + 29, + 212, + 3, // Opcode: VSTRH + /* 34 */ MCD_OPC_FilterValue, + 14, + 212, + 21, + 0, // Skip to: 5627 + /* 39 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 42 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 110 + /* 47 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 50 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 88 + /* 55 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 58 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 73 + /* 63 */ MCD_OPC_CheckPredicate, + 77, + 183, + 21, + 0, // Skip to: 5627 + /* 68 */ MCD_OPC_Decode, + 174, + 22, + 213, + 3, // Opcode: VMLAH + /* 73 */ MCD_OPC_FilterValue, + 1, + 173, + 21, + 0, // Skip to: 5627 + /* 78 */ MCD_OPC_CheckPredicate, + 77, + 168, + 21, + 0, // Skip to: 5627 + /* 83 */ MCD_OPC_Decode, + 175, + 18, + 214, + 3, // Opcode: VDIVH + /* 88 */ MCD_OPC_FilterValue, + 1, + 158, + 21, + 0, // Skip to: 5627 + /* 93 */ MCD_OPC_CheckPredicate, + 77, + 153, + 21, + 0, // Skip to: 5627 + /* 98 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 146, + 21, + 0, // Skip to: 5627 + /* 105 */ MCD_OPC_Decode, + 205, + 22, + 213, + 3, // Opcode: VMLSH + /* 110 */ MCD_OPC_FilterValue, + 1, + 136, + 21, + 0, // Skip to: 5627 + /* 115 */ MCD_OPC_CheckPredicate, + 76, + 131, + 21, + 0, // Skip to: 5627 + /* 120 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 124, + 21, + 0, // Skip to: 5627 + /* 127 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 117, + 21, + 0, // Skip to: 5627 + /* 134 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 110, + 21, + 0, // Skip to: 5627 + /* 141 */ MCD_OPC_Decode, + 239, + 22, + 215, + 3, // Opcode: VMOVHR + /* 146 */ MCD_OPC_FilterValue, + 1, + 146, + 0, + 0, // Skip to: 297 + /* 151 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 154 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 169 + /* 159 */ MCD_OPC_CheckPredicate, + 76, + 87, + 21, + 0, // Skip to: 5627 + /* 164 */ MCD_OPC_Decode, + 247, + 21, + 212, + 3, // Opcode: VLDRH + /* 169 */ MCD_OPC_FilterValue, + 14, + 77, + 21, + 0, // Skip to: 5627 + /* 174 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 177 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 261 + /* 182 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 185 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 223 + /* 190 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 193 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 208 + /* 198 */ MCD_OPC_CheckPredicate, + 77, + 48, + 21, + 0, // Skip to: 5627 + /* 203 */ MCD_OPC_Decode, + 219, + 23, + 213, + 3, // Opcode: VNMLSH + /* 208 */ MCD_OPC_FilterValue, + 1, + 38, + 21, + 0, // Skip to: 5627 + /* 213 */ MCD_OPC_CheckPredicate, + 77, + 33, + 21, + 0, // Skip to: 5627 + /* 218 */ MCD_OPC_Decode, + 224, + 18, + 213, + 3, // Opcode: VFNMSH + /* 223 */ MCD_OPC_FilterValue, + 1, + 23, + 21, + 0, // Skip to: 5627 + /* 228 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 231 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 246 + /* 236 */ MCD_OPC_CheckPredicate, + 77, + 10, + 21, + 0, // Skip to: 5627 + /* 241 */ MCD_OPC_Decode, + 216, + 23, + 213, + 3, // Opcode: VNMLAH + /* 246 */ MCD_OPC_FilterValue, + 1, + 0, + 21, + 0, // Skip to: 5627 + /* 251 */ MCD_OPC_CheckPredicate, + 77, + 251, + 20, + 0, // Skip to: 5627 + /* 256 */ MCD_OPC_Decode, + 221, + 18, + 213, + 3, // Opcode: VFNMAH + /* 261 */ MCD_OPC_FilterValue, + 1, + 241, + 20, + 0, // Skip to: 5627 + /* 266 */ MCD_OPC_CheckPredicate, + 76, + 236, + 20, + 0, // Skip to: 5627 + /* 271 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 229, + 20, + 0, // Skip to: 5627 + /* 278 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 222, + 20, + 0, // Skip to: 5627 + /* 285 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 215, + 20, + 0, // Skip to: 5627 + /* 292 */ MCD_OPC_Decode, + 249, + 22, + 216, + 3, // Opcode: VMOVRH + /* 297 */ MCD_OPC_FilterValue, + 2, + 107, + 0, + 0, // Skip to: 409 + /* 302 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 305 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 357 + /* 310 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 313 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 335 + /* 318 */ MCD_OPC_CheckPredicate, + 77, + 184, + 20, + 0, // Skip to: 5627 + /* 323 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 177, + 20, + 0, // Skip to: 5627 + /* 330 */ MCD_OPC_Decode, + 162, + 23, + 214, + 3, // Opcode: VMULH + /* 335 */ MCD_OPC_FilterValue, + 29, + 167, + 20, + 0, // Skip to: 5627 + /* 340 */ MCD_OPC_CheckPredicate, + 77, + 162, + 20, + 0, // Skip to: 5627 + /* 345 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 155, + 20, + 0, // Skip to: 5627 + /* 352 */ MCD_OPC_Decode, + 199, + 18, + 213, + 3, // Opcode: VFMAH + /* 357 */ MCD_OPC_FilterValue, + 1, + 145, + 20, + 0, // Skip to: 5627 + /* 362 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 365 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 387 + /* 370 */ MCD_OPC_CheckPredicate, + 77, + 132, + 20, + 0, // Skip to: 5627 + /* 375 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 125, + 20, + 0, // Skip to: 5627 + /* 382 */ MCD_OPC_Decode, + 222, + 23, + 214, + 3, // Opcode: VNMULH + /* 387 */ MCD_OPC_FilterValue, + 29, + 115, + 20, + 0, // Skip to: 5627 + /* 392 */ MCD_OPC_CheckPredicate, + 77, + 110, + 20, + 0, // Skip to: 5627 + /* 397 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 103, + 20, + 0, // Skip to: 5627 + /* 404 */ MCD_OPC_Decode, + 210, + 18, + 213, + 3, // Opcode: VFMSH + /* 409 */ MCD_OPC_FilterValue, + 3, + 93, + 20, + 0, // Skip to: 5627 + /* 414 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 417 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 476 + /* 422 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 425 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 447 + /* 430 */ MCD_OPC_CheckPredicate, + 77, + 72, + 20, + 0, // Skip to: 5627 + /* 435 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 65, + 20, + 0, // Skip to: 5627 + /* 442 */ MCD_OPC_Decode, + 151, + 16, + 214, + 3, // Opcode: VADDH + /* 447 */ MCD_OPC_FilterValue, + 29, + 55, + 20, + 0, // Skip to: 5627 + /* 452 */ MCD_OPC_CheckPredicate, + 77, + 50, + 20, + 0, // Skip to: 5627 + /* 457 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 43, + 20, + 0, // Skip to: 5627 + /* 464 */ MCD_OPC_CheckField, + 4, + 2, + 0, + 36, + 20, + 0, // Skip to: 5627 + /* 471 */ MCD_OPC_Decode, + 170, + 6, + 217, + 3, // Opcode: FCONSTH + /* 476 */ MCD_OPC_FilterValue, + 1, + 26, + 20, + 0, // Skip to: 5627 + /* 481 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 484 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 506 + /* 489 */ MCD_OPC_CheckPredicate, + 77, + 13, + 20, + 0, // Skip to: 5627 + /* 494 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 6, + 20, + 0, // Skip to: 5627 + /* 501 */ MCD_OPC_Decode, + 231, + 29, + 214, + 3, // Opcode: VSUBH + /* 506 */ MCD_OPC_FilterValue, + 29, + 252, + 19, + 0, // Skip to: 5627 + /* 511 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 514 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 543 + /* 519 */ MCD_OPC_CheckPredicate, + 77, + 239, + 19, + 0, // Skip to: 5627 + /* 524 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 232, + 19, + 0, // Skip to: 5627 + /* 531 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 225, + 19, + 0, // Skip to: 5627 + /* 538 */ MCD_OPC_Decode, + 130, + 16, + 218, + 3, // Opcode: VABSH + /* 543 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 595 + /* 548 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 551 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 573 + /* 556 */ MCD_OPC_CheckPredicate, + 77, + 202, + 19, + 0, // Skip to: 5627 + /* 561 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 195, + 19, + 0, // Skip to: 5627 + /* 568 */ MCD_OPC_Decode, + 203, + 23, + 218, + 3, // Opcode: VNEGH + /* 573 */ MCD_OPC_FilterValue, + 1, + 185, + 19, + 0, // Skip to: 5627 + /* 578 */ MCD_OPC_CheckPredicate, + 77, + 180, + 19, + 0, // Skip to: 5627 + /* 583 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 173, + 19, + 0, // Skip to: 5627 + /* 590 */ MCD_OPC_Decode, + 174, + 27, + 218, + 3, // Opcode: VSQRTH + /* 595 */ MCD_OPC_FilterValue, + 4, + 47, + 0, + 0, // Skip to: 647 + /* 600 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 603 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 625 + /* 608 */ MCD_OPC_CheckPredicate, + 77, + 150, + 19, + 0, // Skip to: 5627 + /* 613 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 143, + 19, + 0, // Skip to: 5627 + /* 620 */ MCD_OPC_Decode, + 195, + 17, + 218, + 3, // Opcode: VCMPH + /* 625 */ MCD_OPC_FilterValue, + 1, + 133, + 19, + 0, // Skip to: 5627 + /* 630 */ MCD_OPC_CheckPredicate, + 77, + 128, + 19, + 0, // Skip to: 5627 + /* 635 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 121, + 19, + 0, // Skip to: 5627 + /* 642 */ MCD_OPC_Decode, + 190, + 17, + 218, + 3, // Opcode: VCMPEH + /* 647 */ MCD_OPC_FilterValue, + 5, + 47, + 0, + 0, // Skip to: 699 + /* 652 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 655 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 677 + /* 660 */ MCD_OPC_CheckPredicate, + 77, + 98, + 19, + 0, // Skip to: 5627 + /* 665 */ MCD_OPC_CheckField, + 0, + 6, + 0, + 91, + 19, + 0, // Skip to: 5627 + /* 672 */ MCD_OPC_Decode, + 198, + 17, + 219, + 3, // Opcode: VCMPZH + /* 677 */ MCD_OPC_FilterValue, + 1, + 81, + 19, + 0, // Skip to: 5627 + /* 682 */ MCD_OPC_CheckPredicate, + 77, + 76, + 19, + 0, // Skip to: 5627 + /* 687 */ MCD_OPC_CheckField, + 0, + 6, + 0, + 69, + 19, + 0, // Skip to: 5627 + /* 694 */ MCD_OPC_Decode, + 193, + 17, + 219, + 3, // Opcode: VCMPEZH + /* 699 */ MCD_OPC_FilterValue, + 6, + 47, + 0, + 0, // Skip to: 751 + /* 704 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 707 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 729 + /* 712 */ MCD_OPC_CheckPredicate, + 77, + 46, + 19, + 0, // Skip to: 5627 + /* 717 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 39, + 19, + 0, // Skip to: 5627 + /* 724 */ MCD_OPC_Decode, + 130, + 26, + 218, + 3, // Opcode: VRINTRH + /* 729 */ MCD_OPC_FilterValue, + 1, + 29, + 19, + 0, // Skip to: 5627 + /* 734 */ MCD_OPC_CheckPredicate, + 77, + 24, + 19, + 0, // Skip to: 5627 + /* 739 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 17, + 19, + 0, // Skip to: 5627 + /* 746 */ MCD_OPC_Decode, + 140, + 26, + 218, + 3, // Opcode: VRINTZH + /* 751 */ MCD_OPC_FilterValue, + 7, + 24, + 0, + 0, // Skip to: 780 + /* 756 */ MCD_OPC_CheckPredicate, + 77, + 2, + 19, + 0, // Skip to: 5627 + /* 761 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 251, + 18, + 0, // Skip to: 5627 + /* 768 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 244, + 18, + 0, // Skip to: 5627 + /* 775 */ MCD_OPC_Decode, + 133, + 26, + 218, + 3, // Opcode: VRINTXH + /* 780 */ MCD_OPC_FilterValue, + 8, + 47, + 0, + 0, // Skip to: 832 + /* 785 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 788 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 810 + /* 793 */ MCD_OPC_CheckPredicate, + 77, + 221, + 18, + 0, // Skip to: 5627 + /* 798 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 214, + 18, + 0, // Skip to: 5627 + /* 805 */ MCD_OPC_Decode, + 192, + 30, + 220, + 3, // Opcode: VUITOH + /* 810 */ MCD_OPC_FilterValue, + 1, + 204, + 18, + 0, // Skip to: 5627 + /* 815 */ MCD_OPC_CheckPredicate, + 77, + 199, + 18, + 0, // Skip to: 5627 + /* 820 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 192, + 18, + 0, // Skip to: 5627 + /* 827 */ MCD_OPC_Decode, + 159, + 27, + 220, + 3, // Opcode: VSITOH + /* 832 */ MCD_OPC_FilterValue, + 10, + 47, + 0, + 0, // Skip to: 884 + /* 837 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 840 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 862 + /* 845 */ MCD_OPC_CheckPredicate, + 77, + 169, + 18, + 0, // Skip to: 5627 + /* 850 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 162, + 18, + 0, // Skip to: 5627 + /* 857 */ MCD_OPC_Decode, + 156, + 27, + 221, + 3, // Opcode: VSHTOH + /* 862 */ MCD_OPC_FilterValue, + 1, + 152, + 18, + 0, // Skip to: 5627 + /* 867 */ MCD_OPC_CheckPredicate, + 77, + 147, + 18, + 0, // Skip to: 5627 + /* 872 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 140, + 18, + 0, // Skip to: 5627 + /* 879 */ MCD_OPC_Decode, + 170, + 27, + 221, + 3, // Opcode: VSLTOH + /* 884 */ MCD_OPC_FilterValue, + 11, + 47, + 0, + 0, // Skip to: 936 + /* 889 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 892 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 914 + /* 897 */ MCD_OPC_CheckPredicate, + 77, + 117, + 18, + 0, // Skip to: 5627 + /* 902 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 110, + 18, + 0, // Skip to: 5627 + /* 909 */ MCD_OPC_Decode, + 189, + 30, + 221, + 3, // Opcode: VUHTOH + /* 914 */ MCD_OPC_FilterValue, + 1, + 100, + 18, + 0, // Skip to: 5627 + /* 919 */ MCD_OPC_CheckPredicate, + 77, + 95, + 18, + 0, // Skip to: 5627 + /* 924 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 88, + 18, + 0, // Skip to: 5627 + /* 931 */ MCD_OPC_Decode, + 195, + 30, + 221, + 3, // Opcode: VULTOH + /* 936 */ MCD_OPC_FilterValue, + 12, + 47, + 0, + 0, // Skip to: 988 + /* 941 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 944 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 966 + /* 949 */ MCD_OPC_CheckPredicate, + 77, + 65, + 18, + 0, // Skip to: 5627 + /* 954 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 58, + 18, + 0, // Skip to: 5627 + /* 961 */ MCD_OPC_Decode, + 164, + 30, + 222, + 3, // Opcode: VTOUIRH + /* 966 */ MCD_OPC_FilterValue, + 1, + 48, + 18, + 0, // Skip to: 5627 + /* 971 */ MCD_OPC_CheckPredicate, + 77, + 43, + 18, + 0, // Skip to: 5627 + /* 976 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 36, + 18, + 0, // Skip to: 5627 + /* 983 */ MCD_OPC_Decode, + 167, + 30, + 223, + 3, // Opcode: VTOUIZH + /* 988 */ MCD_OPC_FilterValue, + 13, + 47, + 0, + 0, // Skip to: 1040 + /* 993 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 996 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1018 + /* 1001 */ MCD_OPC_CheckPredicate, + 77, + 13, + 18, + 0, // Skip to: 5627 + /* 1006 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 6, + 18, + 0, // Skip to: 5627 + /* 1013 */ MCD_OPC_Decode, + 152, + 30, + 222, + 3, // Opcode: VTOSIRH + /* 1018 */ MCD_OPC_FilterValue, + 1, + 252, + 17, + 0, // Skip to: 5627 + /* 1023 */ MCD_OPC_CheckPredicate, + 77, + 247, + 17, + 0, // Skip to: 5627 + /* 1028 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 240, + 17, + 0, // Skip to: 5627 + /* 1035 */ MCD_OPC_Decode, + 155, + 30, + 223, + 3, // Opcode: VTOSIZH + /* 1040 */ MCD_OPC_FilterValue, + 14, + 47, + 0, + 0, // Skip to: 1092 + /* 1045 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1048 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1070 + /* 1053 */ MCD_OPC_CheckPredicate, + 77, + 217, + 17, + 0, // Skip to: 5627 + /* 1058 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 210, + 17, + 0, // Skip to: 5627 + /* 1065 */ MCD_OPC_Decode, + 149, + 30, + 221, + 3, // Opcode: VTOSHH + /* 1070 */ MCD_OPC_FilterValue, + 1, + 200, + 17, + 0, // Skip to: 5627 + /* 1075 */ MCD_OPC_CheckPredicate, + 77, + 195, + 17, + 0, // Skip to: 5627 + /* 1080 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 188, + 17, + 0, // Skip to: 5627 + /* 1087 */ MCD_OPC_Decode, + 158, + 30, + 221, + 3, // Opcode: VTOSLH + /* 1092 */ MCD_OPC_FilterValue, + 15, + 178, + 17, + 0, // Skip to: 5627 + /* 1097 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1100 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1122 + /* 1105 */ MCD_OPC_CheckPredicate, + 77, + 165, + 17, + 0, // Skip to: 5627 + /* 1110 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 158, + 17, + 0, // Skip to: 5627 + /* 1117 */ MCD_OPC_Decode, + 161, + 30, + 221, + 3, // Opcode: VTOUHH + /* 1122 */ MCD_OPC_FilterValue, + 1, + 148, + 17, + 0, // Skip to: 5627 + /* 1127 */ MCD_OPC_CheckPredicate, + 77, + 143, + 17, + 0, // Skip to: 5627 + /* 1132 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 136, + 17, + 0, // Skip to: 5627 + /* 1139 */ MCD_OPC_Decode, + 170, + 30, + 221, + 3, // Opcode: VTOULH + /* 1144 */ MCD_OPC_FilterValue, + 10, + 105, + 7, + 0, // Skip to: 3046 + /* 1149 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1152 */ MCD_OPC_FilterValue, + 0, + 189, + 0, + 0, // Skip to: 1346 + /* 1157 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 1160 */ MCD_OPC_FilterValue, + 12, + 54, + 0, + 0, // Skip to: 1219 + /* 1165 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1168 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 1204 + /* 1173 */ MCD_OPC_CheckPredicate, + 34, + 97, + 17, + 0, // Skip to: 5627 + /* 1178 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 90, + 17, + 0, // Skip to: 5627 + /* 1185 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 83, + 17, + 0, // Skip to: 5627 + /* 1192 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 76, + 17, + 0, // Skip to: 5627 + /* 1199 */ MCD_OPC_Decode, + 255, + 22, + 224, + 3, // Opcode: VMOVSRR + /* 1204 */ MCD_OPC_FilterValue, + 1, + 66, + 17, + 0, // Skip to: 5627 + /* 1209 */ MCD_OPC_CheckPredicate, + 34, + 61, + 17, + 0, // Skip to: 5627 + /* 1214 */ MCD_OPC_Decode, + 207, + 29, + 225, + 3, // Opcode: VSTMSIA + /* 1219 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1234 + /* 1224 */ MCD_OPC_CheckPredicate, + 34, + 46, + 17, + 0, // Skip to: 5627 + /* 1229 */ MCD_OPC_Decode, + 211, + 29, + 226, + 3, // Opcode: VSTRS + /* 1234 */ MCD_OPC_FilterValue, + 14, + 36, + 17, + 0, // Skip to: 5627 + /* 1239 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1242 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 1310 + /* 1247 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1250 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 1288 + /* 1255 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1258 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1273 + /* 1263 */ MCD_OPC_CheckPredicate, + 33, + 7, + 17, + 0, // Skip to: 5627 + /* 1268 */ MCD_OPC_Decode, + 185, + 22, + 227, + 3, // Opcode: VMLAS + /* 1273 */ MCD_OPC_FilterValue, + 1, + 253, + 16, + 0, // Skip to: 5627 + /* 1278 */ MCD_OPC_CheckPredicate, + 33, + 248, + 16, + 0, // Skip to: 5627 + /* 1283 */ MCD_OPC_Decode, + 176, + 18, + 228, + 3, // Opcode: VDIVS + /* 1288 */ MCD_OPC_FilterValue, + 1, + 238, + 16, + 0, // Skip to: 5627 + /* 1293 */ MCD_OPC_CheckPredicate, + 33, + 233, + 16, + 0, // Skip to: 5627 + /* 1298 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 226, + 16, + 0, // Skip to: 5627 + /* 1305 */ MCD_OPC_Decode, + 216, + 22, + 227, + 3, // Opcode: VMLSS + /* 1310 */ MCD_OPC_FilterValue, + 1, + 216, + 16, + 0, // Skip to: 5627 + /* 1315 */ MCD_OPC_CheckPredicate, + 34, + 211, + 16, + 0, // Skip to: 5627 + /* 1320 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 204, + 16, + 0, // Skip to: 5627 + /* 1327 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 197, + 16, + 0, // Skip to: 5627 + /* 1334 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 190, + 16, + 0, // Skip to: 5627 + /* 1341 */ MCD_OPC_Decode, + 254, + 22, + 229, + 3, // Opcode: VMOVSR + /* 1346 */ MCD_OPC_FilterValue, + 1, + 229, + 0, + 0, // Skip to: 1580 + /* 1351 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 1354 */ MCD_OPC_FilterValue, + 12, + 78, + 0, + 0, // Skip to: 1437 + /* 1359 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1362 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 1398 + /* 1367 */ MCD_OPC_CheckPredicate, + 34, + 159, + 16, + 0, // Skip to: 5627 + /* 1372 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 152, + 16, + 0, // Skip to: 5627 + /* 1379 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 145, + 16, + 0, // Skip to: 5627 + /* 1386 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 138, + 16, + 0, // Skip to: 5627 + /* 1393 */ MCD_OPC_Decode, + 251, + 22, + 230, + 3, // Opcode: VMOVRRS + /* 1398 */ MCD_OPC_FilterValue, + 1, + 128, + 16, + 0, // Skip to: 5627 + /* 1403 */ MCD_OPC_CheckPredicate, + 78, + 19, + 0, + 0, // Skip to: 1427 + /* 1408 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 12, + 0, + 0, // Skip to: 1427 + /* 1415 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 1427 + /* 1422 */ MCD_OPC_Decode, + 211, + 26, + 231, + 3, // Opcode: VSCCLRMS + /* 1427 */ MCD_OPC_CheckPredicate, + 34, + 99, + 16, + 0, // Skip to: 5627 + /* 1432 */ MCD_OPC_Decode, + 244, + 21, + 225, + 3, // Opcode: VLDMSIA + /* 1437 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1452 + /* 1442 */ MCD_OPC_CheckPredicate, + 34, + 84, + 16, + 0, // Skip to: 5627 + /* 1447 */ MCD_OPC_Decode, + 248, + 21, + 226, + 3, // Opcode: VLDRS + /* 1452 */ MCD_OPC_FilterValue, + 14, + 74, + 16, + 0, // Skip to: 5627 + /* 1457 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1460 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 1544 + /* 1465 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1468 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 1506 + /* 1473 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1476 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1491 + /* 1481 */ MCD_OPC_CheckPredicate, + 33, + 45, + 16, + 0, // Skip to: 5627 + /* 1486 */ MCD_OPC_Decode, + 220, + 23, + 227, + 3, // Opcode: VNMLSS + /* 1491 */ MCD_OPC_FilterValue, + 1, + 35, + 16, + 0, // Skip to: 5627 + /* 1496 */ MCD_OPC_CheckPredicate, + 79, + 30, + 16, + 0, // Skip to: 5627 + /* 1501 */ MCD_OPC_Decode, + 225, + 18, + 227, + 3, // Opcode: VFNMSS + /* 1506 */ MCD_OPC_FilterValue, + 1, + 20, + 16, + 0, // Skip to: 5627 + /* 1511 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1514 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1529 + /* 1519 */ MCD_OPC_CheckPredicate, + 33, + 7, + 16, + 0, // Skip to: 5627 + /* 1524 */ MCD_OPC_Decode, + 217, + 23, + 227, + 3, // Opcode: VNMLAS + /* 1529 */ MCD_OPC_FilterValue, + 1, + 253, + 15, + 0, // Skip to: 5627 + /* 1534 */ MCD_OPC_CheckPredicate, + 79, + 248, + 15, + 0, // Skip to: 5627 + /* 1539 */ MCD_OPC_Decode, + 222, + 18, + 227, + 3, // Opcode: VFNMAS + /* 1544 */ MCD_OPC_FilterValue, + 1, + 238, + 15, + 0, // Skip to: 5627 + /* 1549 */ MCD_OPC_CheckPredicate, + 34, + 233, + 15, + 0, // Skip to: 5627 + /* 1554 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 226, + 15, + 0, // Skip to: 5627 + /* 1561 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 219, + 15, + 0, // Skip to: 5627 + /* 1568 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 212, + 15, + 0, // Skip to: 5627 + /* 1575 */ MCD_OPC_Decode, + 252, + 22, + 232, + 3, // Opcode: VMOVRS + /* 1580 */ MCD_OPC_FilterValue, + 2, + 179, + 1, + 0, // Skip to: 2020 + /* 1585 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 1588 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 1624 + /* 1593 */ MCD_OPC_CheckPredicate, + 80, + 189, + 15, + 0, // Skip to: 5627 + /* 1598 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 182, + 15, + 0, // Skip to: 5627 + /* 1605 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 175, + 15, + 0, // Skip to: 5627 + /* 1612 */ MCD_OPC_CheckField, + 0, + 8, + 0, + 168, + 15, + 0, // Skip to: 5627 + /* 1619 */ MCD_OPC_Decode, + 140, + 22, + 233, + 3, // Opcode: VLSTM + /* 1624 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 1639 + /* 1629 */ MCD_OPC_CheckPredicate, + 34, + 153, + 15, + 0, // Skip to: 5627 + /* 1634 */ MCD_OPC_Decode, + 208, + 29, + 234, + 3, // Opcode: VSTMSIA_UPD + /* 1639 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 1654 + /* 1644 */ MCD_OPC_CheckPredicate, + 34, + 138, + 15, + 0, // Skip to: 5627 + /* 1649 */ MCD_OPC_Decode, + 206, + 29, + 234, + 3, // Opcode: VSTMSDB_UPD + /* 1654 */ MCD_OPC_FilterValue, + 28, + 47, + 0, + 0, // Skip to: 1706 + /* 1659 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1662 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1684 + /* 1667 */ MCD_OPC_CheckPredicate, + 33, + 115, + 15, + 0, // Skip to: 5627 + /* 1672 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 108, + 15, + 0, // Skip to: 5627 + /* 1679 */ MCD_OPC_Decode, + 175, + 23, + 228, + 3, // Opcode: VMULS + /* 1684 */ MCD_OPC_FilterValue, + 1, + 98, + 15, + 0, // Skip to: 5627 + /* 1689 */ MCD_OPC_CheckPredicate, + 33, + 93, + 15, + 0, // Skip to: 5627 + /* 1694 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 86, + 15, + 0, // Skip to: 5627 + /* 1701 */ MCD_OPC_Decode, + 223, + 23, + 228, + 3, // Opcode: VNMULS + /* 1706 */ MCD_OPC_FilterValue, + 29, + 76, + 15, + 0, // Skip to: 5627 + /* 1711 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1714 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 1752 + /* 1719 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1722 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1737 + /* 1727 */ MCD_OPC_CheckPredicate, + 79, + 55, + 15, + 0, // Skip to: 5627 + /* 1732 */ MCD_OPC_Decode, + 204, + 18, + 227, + 3, // Opcode: VFMAS + /* 1737 */ MCD_OPC_FilterValue, + 1, + 45, + 15, + 0, // Skip to: 5627 + /* 1742 */ MCD_OPC_CheckPredicate, + 79, + 40, + 15, + 0, // Skip to: 5627 + /* 1747 */ MCD_OPC_Decode, + 215, + 18, + 227, + 3, // Opcode: VFMSS + /* 1752 */ MCD_OPC_FilterValue, + 1, + 30, + 15, + 0, // Skip to: 5627 + /* 1757 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 1760 */ MCD_OPC_FilterValue, + 0, + 21, + 0, + 0, // Skip to: 1786 + /* 1765 */ MCD_OPC_CheckPredicate, + 33, + 17, + 15, + 0, // Skip to: 5627 + /* 1770 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 10, + 15, + 0, // Skip to: 5627 + /* 1777 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1781 */ MCD_OPC_Decode, + 158, + 23, + 235, + 3, // Opcode: VMSR_FPSID + /* 1786 */ MCD_OPC_FilterValue, + 1, + 21, + 0, + 0, // Skip to: 1812 + /* 1791 */ MCD_OPC_CheckPredicate, + 34, + 247, + 14, + 0, // Skip to: 5627 + /* 1796 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 240, + 14, + 0, // Skip to: 5627 + /* 1803 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1807 */ MCD_OPC_Decode, + 151, + 23, + 235, + 3, // Opcode: VMSR + /* 1812 */ MCD_OPC_FilterValue, + 2, + 21, + 0, + 0, // Skip to: 1838 + /* 1817 */ MCD_OPC_CheckPredicate, + 81, + 221, + 14, + 0, // Skip to: 5627 + /* 1822 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 214, + 14, + 0, // Skip to: 5627 + /* 1829 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1833 */ MCD_OPC_Decode, + 157, + 23, + 235, + 3, // Opcode: VMSR_FPSCR_NZCVQC + /* 1838 */ MCD_OPC_FilterValue, + 8, + 21, + 0, + 0, // Skip to: 1864 + /* 1843 */ MCD_OPC_CheckPredicate, + 33, + 195, + 14, + 0, // Skip to: 5627 + /* 1848 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 188, + 14, + 0, // Skip to: 5627 + /* 1855 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1859 */ MCD_OPC_Decode, + 154, + 23, + 235, + 3, // Opcode: VMSR_FPEXC + /* 1864 */ MCD_OPC_FilterValue, + 9, + 21, + 0, + 0, // Skip to: 1890 + /* 1869 */ MCD_OPC_CheckPredicate, + 33, + 169, + 14, + 0, // Skip to: 5627 + /* 1874 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 162, + 14, + 0, // Skip to: 5627 + /* 1881 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1885 */ MCD_OPC_Decode, + 155, + 23, + 235, + 3, // Opcode: VMSR_FPINST + /* 1890 */ MCD_OPC_FilterValue, + 10, + 21, + 0, + 0, // Skip to: 1916 + /* 1895 */ MCD_OPC_CheckPredicate, + 33, + 143, + 14, + 0, // Skip to: 5627 + /* 1900 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 136, + 14, + 0, // Skip to: 5627 + /* 1907 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1911 */ MCD_OPC_Decode, + 156, + 23, + 235, + 3, // Opcode: VMSR_FPINST2 + /* 1916 */ MCD_OPC_FilterValue, + 12, + 21, + 0, + 0, // Skip to: 1942 + /* 1921 */ MCD_OPC_CheckPredicate, + 23, + 117, + 14, + 0, // Skip to: 5627 + /* 1926 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 110, + 14, + 0, // Skip to: 5627 + /* 1933 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1937 */ MCD_OPC_Decode, + 160, + 23, + 235, + 3, // Opcode: VMSR_VPR + /* 1942 */ MCD_OPC_FilterValue, + 13, + 21, + 0, + 0, // Skip to: 1968 + /* 1947 */ MCD_OPC_CheckPredicate, + 23, + 91, + 14, + 0, // Skip to: 5627 + /* 1952 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 84, + 14, + 0, // Skip to: 5627 + /* 1959 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1963 */ MCD_OPC_Decode, + 159, + 23, + 235, + 3, // Opcode: VMSR_P0 + /* 1968 */ MCD_OPC_FilterValue, + 14, + 21, + 0, + 0, // Skip to: 1994 + /* 1973 */ MCD_OPC_CheckPredicate, + 78, + 65, + 14, + 0, // Skip to: 5627 + /* 1978 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 58, + 14, + 0, // Skip to: 5627 + /* 1985 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1989 */ MCD_OPC_Decode, + 152, + 23, + 235, + 3, // Opcode: VMSR_FPCXTNS + /* 1994 */ MCD_OPC_FilterValue, + 15, + 44, + 14, + 0, // Skip to: 5627 + /* 1999 */ MCD_OPC_CheckPredicate, + 78, + 39, + 14, + 0, // Skip to: 5627 + /* 2004 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 32, + 14, + 0, // Skip to: 5627 + /* 2011 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2015 */ MCD_OPC_Decode, + 153, + 23, + 235, + 3, // Opcode: VMSR_FPCXTS + /* 2020 */ MCD_OPC_FilterValue, + 3, + 18, + 14, + 0, // Skip to: 5627 + /* 2025 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 2028 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 2064 + /* 2033 */ MCD_OPC_CheckPredicate, + 80, + 5, + 14, + 0, // Skip to: 5627 + /* 2038 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 254, + 13, + 0, // Skip to: 5627 + /* 2045 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 247, + 13, + 0, // Skip to: 5627 + /* 2052 */ MCD_OPC_CheckField, + 0, + 8, + 0, + 240, + 13, + 0, // Skip to: 5627 + /* 2059 */ MCD_OPC_Decode, + 139, + 22, + 233, + 3, // Opcode: VLLDM + /* 2064 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 2079 + /* 2069 */ MCD_OPC_CheckPredicate, + 34, + 225, + 13, + 0, // Skip to: 5627 + /* 2074 */ MCD_OPC_Decode, + 245, + 21, + 234, + 3, // Opcode: VLDMSIA_UPD + /* 2079 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 2094 + /* 2084 */ MCD_OPC_CheckPredicate, + 34, + 210, + 13, + 0, // Skip to: 5627 + /* 2089 */ MCD_OPC_Decode, + 243, + 21, + 234, + 3, // Opcode: VLDMSDB_UPD + /* 2094 */ MCD_OPC_FilterValue, + 28, + 47, + 0, + 0, // Skip to: 2146 + /* 2099 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2102 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2124 + /* 2107 */ MCD_OPC_CheckPredicate, + 33, + 187, + 13, + 0, // Skip to: 5627 + /* 2112 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 180, + 13, + 0, // Skip to: 5627 + /* 2119 */ MCD_OPC_Decode, + 161, + 16, + 228, + 3, // Opcode: VADDS + /* 2124 */ MCD_OPC_FilterValue, + 1, + 170, + 13, + 0, // Skip to: 5627 + /* 2129 */ MCD_OPC_CheckPredicate, + 33, + 165, + 13, + 0, // Skip to: 5627 + /* 2134 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 158, + 13, + 0, // Skip to: 5627 + /* 2141 */ MCD_OPC_Decode, + 241, + 29, + 228, + 3, // Opcode: VSUBS + /* 2146 */ MCD_OPC_FilterValue, + 29, + 148, + 13, + 0, // Skip to: 5627 + /* 2151 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 2154 */ MCD_OPC_FilterValue, + 0, + 7, + 2, + 0, // Skip to: 2678 + /* 2159 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 2162 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2184 + /* 2167 */ MCD_OPC_CheckPredicate, + 82, + 127, + 13, + 0, // Skip to: 5627 + /* 2172 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 120, + 13, + 0, // Skip to: 5627 + /* 2179 */ MCD_OPC_Decode, + 171, + 6, + 236, + 3, // Opcode: FCONSTS + /* 2184 */ MCD_OPC_FilterValue, + 1, + 242, + 0, + 0, // Skip to: 2431 + /* 2189 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 2192 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2207 + /* 2197 */ MCD_OPC_CheckPredicate, + 34, + 97, + 13, + 0, // Skip to: 5627 + /* 2202 */ MCD_OPC_Decode, + 253, + 22, + 222, + 3, // Opcode: VMOVS + /* 2207 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2222 + /* 2212 */ MCD_OPC_CheckPredicate, + 33, + 82, + 13, + 0, // Skip to: 5627 + /* 2217 */ MCD_OPC_Decode, + 204, + 23, + 222, + 3, // Opcode: VNEGS + /* 2222 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2237 + /* 2227 */ MCD_OPC_CheckPredicate, + 83, + 67, + 13, + 0, // Skip to: 5627 + /* 2232 */ MCD_OPC_Decode, + 218, + 17, + 222, + 3, // Opcode: VCVTBHS + /* 2237 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 2252 + /* 2242 */ MCD_OPC_CheckPredicate, + 83, + 52, + 13, + 0, // Skip to: 5627 + /* 2247 */ MCD_OPC_Decode, + 219, + 17, + 237, + 3, // Opcode: VCVTBSH + /* 2252 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 2267 + /* 2257 */ MCD_OPC_CheckPredicate, + 33, + 37, + 13, + 0, // Skip to: 5627 + /* 2262 */ MCD_OPC_Decode, + 196, + 17, + 222, + 3, // Opcode: VCMPS + /* 2267 */ MCD_OPC_FilterValue, + 5, + 24, + 0, + 0, // Skip to: 2296 + /* 2272 */ MCD_OPC_CheckPredicate, + 33, + 22, + 13, + 0, // Skip to: 5627 + /* 2277 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 15, + 13, + 0, // Skip to: 5627 + /* 2284 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 8, + 13, + 0, // Skip to: 5627 + /* 2291 */ MCD_OPC_Decode, + 199, + 17, + 238, + 3, // Opcode: VCMPZS + /* 2296 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 2311 + /* 2301 */ MCD_OPC_CheckPredicate, + 84, + 249, + 12, + 0, // Skip to: 5627 + /* 2306 */ MCD_OPC_Decode, + 131, + 26, + 222, + 3, // Opcode: VRINTRS + /* 2311 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 2326 + /* 2316 */ MCD_OPC_CheckPredicate, + 84, + 234, + 12, + 0, // Skip to: 5627 + /* 2321 */ MCD_OPC_Decode, + 138, + 26, + 222, + 3, // Opcode: VRINTXS + /* 2326 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 2341 + /* 2331 */ MCD_OPC_CheckPredicate, + 33, + 219, + 12, + 0, // Skip to: 5627 + /* 2336 */ MCD_OPC_Decode, + 193, + 30, + 222, + 3, // Opcode: VUITOS + /* 2341 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 2356 + /* 2346 */ MCD_OPC_CheckPredicate, + 33, + 204, + 12, + 0, // Skip to: 5627 + /* 2351 */ MCD_OPC_Decode, + 157, + 27, + 221, + 3, // Opcode: VSHTOS + /* 2356 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 2371 + /* 2361 */ MCD_OPC_CheckPredicate, + 33, + 189, + 12, + 0, // Skip to: 5627 + /* 2366 */ MCD_OPC_Decode, + 190, + 30, + 221, + 3, // Opcode: VUHTOS + /* 2371 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 2386 + /* 2376 */ MCD_OPC_CheckPredicate, + 33, + 174, + 12, + 0, // Skip to: 5627 + /* 2381 */ MCD_OPC_Decode, + 165, + 30, + 222, + 3, // Opcode: VTOUIRS + /* 2386 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2401 + /* 2391 */ MCD_OPC_CheckPredicate, + 33, + 159, + 12, + 0, // Skip to: 5627 + /* 2396 */ MCD_OPC_Decode, + 153, + 30, + 222, + 3, // Opcode: VTOSIRS + /* 2401 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 2416 + /* 2406 */ MCD_OPC_CheckPredicate, + 33, + 144, + 12, + 0, // Skip to: 5627 + /* 2411 */ MCD_OPC_Decode, + 150, + 30, + 221, + 3, // Opcode: VTOSHS + /* 2416 */ MCD_OPC_FilterValue, + 15, + 134, + 12, + 0, // Skip to: 5627 + /* 2421 */ MCD_OPC_CheckPredicate, + 33, + 129, + 12, + 0, // Skip to: 5627 + /* 2426 */ MCD_OPC_Decode, + 162, + 30, + 221, + 3, // Opcode: VTOUHS + /* 2431 */ MCD_OPC_FilterValue, + 3, + 119, + 12, + 0, // Skip to: 5627 + /* 2436 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 2439 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2454 + /* 2444 */ MCD_OPC_CheckPredicate, + 33, + 106, + 12, + 0, // Skip to: 5627 + /* 2449 */ MCD_OPC_Decode, + 131, + 16, + 222, + 3, // Opcode: VABSS + /* 2454 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2469 + /* 2459 */ MCD_OPC_CheckPredicate, + 33, + 91, + 12, + 0, // Skip to: 5627 + /* 2464 */ MCD_OPC_Decode, + 175, + 27, + 222, + 3, // Opcode: VSQRTS + /* 2469 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2484 + /* 2474 */ MCD_OPC_CheckPredicate, + 83, + 76, + 12, + 0, // Skip to: 5627 + /* 2479 */ MCD_OPC_Decode, + 138, + 18, + 222, + 3, // Opcode: VCVTTHS + /* 2484 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 2499 + /* 2489 */ MCD_OPC_CheckPredicate, + 83, + 61, + 12, + 0, // Skip to: 5627 + /* 2494 */ MCD_OPC_Decode, + 139, + 18, + 237, + 3, // Opcode: VCVTTSH + /* 2499 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 2514 + /* 2504 */ MCD_OPC_CheckPredicate, + 33, + 46, + 12, + 0, // Skip to: 5627 + /* 2509 */ MCD_OPC_Decode, + 191, + 17, + 222, + 3, // Opcode: VCMPES + /* 2514 */ MCD_OPC_FilterValue, + 5, + 24, + 0, + 0, // Skip to: 2543 + /* 2519 */ MCD_OPC_CheckPredicate, + 33, + 31, + 12, + 0, // Skip to: 5627 + /* 2524 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 24, + 12, + 0, // Skip to: 5627 + /* 2531 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 17, + 12, + 0, // Skip to: 5627 + /* 2538 */ MCD_OPC_Decode, + 194, + 17, + 238, + 3, // Opcode: VCMPEZS + /* 2543 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 2558 + /* 2548 */ MCD_OPC_CheckPredicate, + 84, + 2, + 12, + 0, // Skip to: 5627 + /* 2553 */ MCD_OPC_Decode, + 145, + 26, + 222, + 3, // Opcode: VRINTZS + /* 2558 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 2573 + /* 2563 */ MCD_OPC_CheckPredicate, + 85, + 243, + 11, + 0, // Skip to: 5627 + /* 2568 */ MCD_OPC_Decode, + 220, + 17, + 239, + 3, // Opcode: VCVTDS + /* 2573 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 2588 + /* 2578 */ MCD_OPC_CheckPredicate, + 33, + 228, + 11, + 0, // Skip to: 5627 + /* 2583 */ MCD_OPC_Decode, + 160, + 27, + 222, + 3, // Opcode: VSITOS + /* 2588 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 2603 + /* 2593 */ MCD_OPC_CheckPredicate, + 33, + 213, + 11, + 0, // Skip to: 5627 + /* 2598 */ MCD_OPC_Decode, + 171, + 27, + 221, + 3, // Opcode: VSLTOS + /* 2603 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 2618 + /* 2608 */ MCD_OPC_CheckPredicate, + 33, + 198, + 11, + 0, // Skip to: 5627 + /* 2613 */ MCD_OPC_Decode, + 196, + 30, + 221, + 3, // Opcode: VULTOS + /* 2618 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 2633 + /* 2623 */ MCD_OPC_CheckPredicate, + 33, + 183, + 11, + 0, // Skip to: 5627 + /* 2628 */ MCD_OPC_Decode, + 168, + 30, + 222, + 3, // Opcode: VTOUIZS + /* 2633 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2648 + /* 2638 */ MCD_OPC_CheckPredicate, + 33, + 168, + 11, + 0, // Skip to: 5627 + /* 2643 */ MCD_OPC_Decode, + 156, + 30, + 222, + 3, // Opcode: VTOSIZS + /* 2648 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 2663 + /* 2653 */ MCD_OPC_CheckPredicate, + 33, + 153, + 11, + 0, // Skip to: 5627 + /* 2658 */ MCD_OPC_Decode, + 159, + 30, + 221, + 3, // Opcode: VTOSLS + /* 2663 */ MCD_OPC_FilterValue, + 15, + 143, + 11, + 0, // Skip to: 5627 + /* 2668 */ MCD_OPC_CheckPredicate, + 33, + 138, + 11, + 0, // Skip to: 5627 + /* 2673 */ MCD_OPC_Decode, + 171, + 30, + 221, + 3, // Opcode: VTOULS + /* 2678 */ MCD_OPC_FilterValue, + 1, + 128, + 11, + 0, // Skip to: 5627 + /* 2683 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 2686 */ MCD_OPC_FilterValue, + 0, + 21, + 0, + 0, // Skip to: 2712 + /* 2691 */ MCD_OPC_CheckPredicate, + 33, + 115, + 11, + 0, // Skip to: 5627 + /* 2696 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 108, + 11, + 0, // Skip to: 5627 + /* 2703 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2707 */ MCD_OPC_Decode, + 145, + 23, + 235, + 3, // Opcode: VMRS_FPSID + /* 2712 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 2760 + /* 2717 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2720 */ MCD_OPC_FilterValue, + 1, + 86, + 11, + 0, // Skip to: 5627 + /* 2725 */ MCD_OPC_CheckPredicate, + 34, + 16, + 0, + 0, // Skip to: 2746 + /* 2730 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 9, + 0, + 0, // Skip to: 2746 + /* 2737 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2741 */ MCD_OPC_Decode, + 175, + 6, + 235, + 3, // Opcode: FMSTAT + /* 2746 */ MCD_OPC_CheckPredicate, + 34, + 60, + 11, + 0, // Skip to: 5627 + /* 2751 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2755 */ MCD_OPC_Decode, + 138, + 23, + 235, + 3, // Opcode: VMRS + /* 2760 */ MCD_OPC_FilterValue, + 2, + 21, + 0, + 0, // Skip to: 2786 + /* 2765 */ MCD_OPC_CheckPredicate, + 81, + 41, + 11, + 0, // Skip to: 5627 + /* 2770 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 34, + 11, + 0, // Skip to: 5627 + /* 2777 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2781 */ MCD_OPC_Decode, + 144, + 23, + 235, + 3, // Opcode: VMRS_FPSCR_NZCVQC + /* 2786 */ MCD_OPC_FilterValue, + 5, + 21, + 0, + 0, // Skip to: 2812 + /* 2791 */ MCD_OPC_CheckPredicate, + 84, + 15, + 11, + 0, // Skip to: 5627 + /* 2796 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 8, + 11, + 0, // Skip to: 5627 + /* 2803 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2807 */ MCD_OPC_Decode, + 148, + 23, + 235, + 3, // Opcode: VMRS_MVFR2 + /* 2812 */ MCD_OPC_FilterValue, + 6, + 21, + 0, + 0, // Skip to: 2838 + /* 2817 */ MCD_OPC_CheckPredicate, + 33, + 245, + 10, + 0, // Skip to: 5627 + /* 2822 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 238, + 10, + 0, // Skip to: 5627 + /* 2829 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2833 */ MCD_OPC_Decode, + 147, + 23, + 235, + 3, // Opcode: VMRS_MVFR1 + /* 2838 */ MCD_OPC_FilterValue, + 7, + 21, + 0, + 0, // Skip to: 2864 + /* 2843 */ MCD_OPC_CheckPredicate, + 33, + 219, + 10, + 0, // Skip to: 5627 + /* 2848 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 212, + 10, + 0, // Skip to: 5627 + /* 2855 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2859 */ MCD_OPC_Decode, + 146, + 23, + 235, + 3, // Opcode: VMRS_MVFR0 + /* 2864 */ MCD_OPC_FilterValue, + 8, + 21, + 0, + 0, // Skip to: 2890 + /* 2869 */ MCD_OPC_CheckPredicate, + 33, + 193, + 10, + 0, // Skip to: 5627 + /* 2874 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 186, + 10, + 0, // Skip to: 5627 + /* 2881 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2885 */ MCD_OPC_Decode, + 141, + 23, + 235, + 3, // Opcode: VMRS_FPEXC + /* 2890 */ MCD_OPC_FilterValue, + 9, + 21, + 0, + 0, // Skip to: 2916 + /* 2895 */ MCD_OPC_CheckPredicate, + 33, + 167, + 10, + 0, // Skip to: 5627 + /* 2900 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 160, + 10, + 0, // Skip to: 5627 + /* 2907 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2911 */ MCD_OPC_Decode, + 142, + 23, + 235, + 3, // Opcode: VMRS_FPINST + /* 2916 */ MCD_OPC_FilterValue, + 10, + 21, + 0, + 0, // Skip to: 2942 + /* 2921 */ MCD_OPC_CheckPredicate, + 33, + 141, + 10, + 0, // Skip to: 5627 + /* 2926 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 134, + 10, + 0, // Skip to: 5627 + /* 2933 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2937 */ MCD_OPC_Decode, + 143, + 23, + 235, + 3, // Opcode: VMRS_FPINST2 + /* 2942 */ MCD_OPC_FilterValue, + 12, + 21, + 0, + 0, // Skip to: 2968 + /* 2947 */ MCD_OPC_CheckPredicate, + 23, + 115, + 10, + 0, // Skip to: 5627 + /* 2952 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 108, + 10, + 0, // Skip to: 5627 + /* 2959 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2963 */ MCD_OPC_Decode, + 150, + 23, + 235, + 3, // Opcode: VMRS_VPR + /* 2968 */ MCD_OPC_FilterValue, + 13, + 21, + 0, + 0, // Skip to: 2994 + /* 2973 */ MCD_OPC_CheckPredicate, + 23, + 89, + 10, + 0, // Skip to: 5627 + /* 2978 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 82, + 10, + 0, // Skip to: 5627 + /* 2985 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2989 */ MCD_OPC_Decode, + 149, + 23, + 235, + 3, // Opcode: VMRS_P0 + /* 2994 */ MCD_OPC_FilterValue, + 14, + 21, + 0, + 0, // Skip to: 3020 + /* 2999 */ MCD_OPC_CheckPredicate, + 78, + 63, + 10, + 0, // Skip to: 5627 + /* 3004 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 56, + 10, + 0, // Skip to: 5627 + /* 3011 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 3015 */ MCD_OPC_Decode, + 139, + 23, + 235, + 3, // Opcode: VMRS_FPCXTNS + /* 3020 */ MCD_OPC_FilterValue, + 15, + 42, + 10, + 0, // Skip to: 5627 + /* 3025 */ MCD_OPC_CheckPredicate, + 78, + 37, + 10, + 0, // Skip to: 5627 + /* 3030 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 30, + 10, + 0, // Skip to: 5627 + /* 3037 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 3041 */ MCD_OPC_Decode, + 140, + 23, + 235, + 3, // Opcode: VMRS_FPCXTS + /* 3046 */ MCD_OPC_FilterValue, + 11, + 252, + 5, + 0, // Skip to: 4583 + /* 3051 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3054 */ MCD_OPC_FilterValue, + 0, + 196, + 0, + 0, // Skip to: 3255 + /* 3059 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 3062 */ MCD_OPC_FilterValue, + 12, + 84, + 0, + 0, // Skip to: 3151 + /* 3067 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 3070 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 3106 + /* 3075 */ MCD_OPC_CheckPredicate, + 34, + 243, + 9, + 0, // Skip to: 5627 + /* 3080 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 236, + 9, + 0, // Skip to: 5627 + /* 3087 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 229, + 9, + 0, // Skip to: 5627 + /* 3094 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 222, + 9, + 0, // Skip to: 5627 + /* 3101 */ MCD_OPC_Decode, + 237, + 22, + 240, + 3, // Opcode: VMOVDRR + /* 3106 */ MCD_OPC_FilterValue, + 1, + 212, + 9, + 0, // Skip to: 5627 + /* 3111 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3114 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3129 + /* 3119 */ MCD_OPC_CheckPredicate, + 34, + 199, + 9, + 0, // Skip to: 5627 + /* 3124 */ MCD_OPC_Decode, + 203, + 29, + 241, + 3, // Opcode: VSTMDIA + /* 3129 */ MCD_OPC_FilterValue, + 1, + 189, + 9, + 0, // Skip to: 5627 + /* 3134 */ MCD_OPC_CheckPredicate, + 34, + 184, + 9, + 0, // Skip to: 5627 + /* 3139 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 177, + 9, + 0, // Skip to: 5627 + /* 3146 */ MCD_OPC_Decode, + 177, + 6, + 242, + 3, // Opcode: FSTMXIA + /* 3151 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3166 + /* 3156 */ MCD_OPC_CheckPredicate, + 34, + 162, + 9, + 0, // Skip to: 5627 + /* 3161 */ MCD_OPC_Decode, + 209, + 29, + 243, + 3, // Opcode: VSTRD + /* 3166 */ MCD_OPC_FilterValue, + 14, + 152, + 9, + 0, // Skip to: 5627 + /* 3171 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3174 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 3226 + /* 3179 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 3182 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3204 + /* 3187 */ MCD_OPC_CheckPredicate, + 85, + 131, + 9, + 0, // Skip to: 5627 + /* 3192 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 124, + 9, + 0, // Skip to: 5627 + /* 3199 */ MCD_OPC_Decode, + 173, + 22, + 244, + 3, // Opcode: VMLAD + /* 3204 */ MCD_OPC_FilterValue, + 1, + 114, + 9, + 0, // Skip to: 5627 + /* 3209 */ MCD_OPC_CheckPredicate, + 85, + 109, + 9, + 0, // Skip to: 5627 + /* 3214 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 102, + 9, + 0, // Skip to: 5627 + /* 3221 */ MCD_OPC_Decode, + 174, + 18, + 245, + 3, // Opcode: VDIVD + /* 3226 */ MCD_OPC_FilterValue, + 1, + 92, + 9, + 0, // Skip to: 5627 + /* 3231 */ MCD_OPC_CheckPredicate, + 85, + 87, + 9, + 0, // Skip to: 5627 + /* 3236 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 80, + 9, + 0, // Skip to: 5627 + /* 3243 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 73, + 9, + 0, // Skip to: 5627 + /* 3250 */ MCD_OPC_Decode, + 204, + 22, + 244, + 3, // Opcode: VMLSD + /* 3255 */ MCD_OPC_FilterValue, + 1, + 243, + 0, + 0, // Skip to: 3503 + /* 3260 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 3263 */ MCD_OPC_FilterValue, + 12, + 108, + 0, + 0, // Skip to: 3376 + /* 3268 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 3271 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 3307 + /* 3276 */ MCD_OPC_CheckPredicate, + 34, + 42, + 9, + 0, // Skip to: 5627 + /* 3281 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 35, + 9, + 0, // Skip to: 5627 + /* 3288 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 28, + 9, + 0, // Skip to: 5627 + /* 3295 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 21, + 9, + 0, // Skip to: 5627 + /* 3302 */ MCD_OPC_Decode, + 250, + 22, + 246, + 3, // Opcode: VMOVRRD + /* 3307 */ MCD_OPC_FilterValue, + 1, + 11, + 9, + 0, // Skip to: 5627 + /* 3312 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3315 */ MCD_OPC_FilterValue, + 0, + 34, + 0, + 0, // Skip to: 3354 + /* 3320 */ MCD_OPC_CheckPredicate, + 78, + 19, + 0, + 0, // Skip to: 3344 + /* 3325 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 12, + 0, + 0, // Skip to: 3344 + /* 3332 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 3344 + /* 3339 */ MCD_OPC_Decode, + 210, + 26, + 231, + 3, // Opcode: VSCCLRMD + /* 3344 */ MCD_OPC_CheckPredicate, + 34, + 230, + 8, + 0, // Skip to: 5627 + /* 3349 */ MCD_OPC_Decode, + 240, + 21, + 241, + 3, // Opcode: VLDMDIA + /* 3354 */ MCD_OPC_FilterValue, + 1, + 220, + 8, + 0, // Skip to: 5627 + /* 3359 */ MCD_OPC_CheckPredicate, + 34, + 215, + 8, + 0, // Skip to: 5627 + /* 3364 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 208, + 8, + 0, // Skip to: 5627 + /* 3371 */ MCD_OPC_Decode, + 173, + 6, + 242, + 3, // Opcode: FLDMXIA + /* 3376 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3391 + /* 3381 */ MCD_OPC_CheckPredicate, + 34, + 193, + 8, + 0, // Skip to: 5627 + /* 3386 */ MCD_OPC_Decode, + 246, + 21, + 243, + 3, // Opcode: VLDRD + /* 3391 */ MCD_OPC_FilterValue, + 14, + 183, + 8, + 0, // Skip to: 5627 + /* 3396 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3399 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 3451 + /* 3404 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 3407 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3429 + /* 3412 */ MCD_OPC_CheckPredicate, + 85, + 162, + 8, + 0, // Skip to: 5627 + /* 3417 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 155, + 8, + 0, // Skip to: 5627 + /* 3424 */ MCD_OPC_Decode, + 218, + 23, + 244, + 3, // Opcode: VNMLSD + /* 3429 */ MCD_OPC_FilterValue, + 1, + 145, + 8, + 0, // Skip to: 5627 + /* 3434 */ MCD_OPC_CheckPredicate, + 86, + 140, + 8, + 0, // Skip to: 5627 + /* 3439 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 133, + 8, + 0, // Skip to: 5627 + /* 3446 */ MCD_OPC_Decode, + 223, + 18, + 244, + 3, // Opcode: VFNMSD + /* 3451 */ MCD_OPC_FilterValue, + 1, + 123, + 8, + 0, // Skip to: 5627 + /* 3456 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 3459 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3481 + /* 3464 */ MCD_OPC_CheckPredicate, + 85, + 110, + 8, + 0, // Skip to: 5627 + /* 3469 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 103, + 8, + 0, // Skip to: 5627 + /* 3476 */ MCD_OPC_Decode, + 215, + 23, + 244, + 3, // Opcode: VNMLAD + /* 3481 */ MCD_OPC_FilterValue, + 1, + 93, + 8, + 0, // Skip to: 5627 + /* 3486 */ MCD_OPC_CheckPredicate, + 86, + 88, + 8, + 0, // Skip to: 5627 + /* 3491 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 81, + 8, + 0, // Skip to: 5627 + /* 3498 */ MCD_OPC_Decode, + 220, + 18, + 244, + 3, // Opcode: VFNMAD + /* 3503 */ MCD_OPC_FilterValue, + 2, + 197, + 0, + 0, // Skip to: 3705 + /* 3508 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 3511 */ MCD_OPC_FilterValue, + 25, + 40, + 0, + 0, // Skip to: 3556 + /* 3516 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3519 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3534 + /* 3524 */ MCD_OPC_CheckPredicate, + 34, + 50, + 8, + 0, // Skip to: 5627 + /* 3529 */ MCD_OPC_Decode, + 204, + 29, + 247, + 3, // Opcode: VSTMDIA_UPD + /* 3534 */ MCD_OPC_FilterValue, + 1, + 40, + 8, + 0, // Skip to: 5627 + /* 3539 */ MCD_OPC_CheckPredicate, + 34, + 35, + 8, + 0, // Skip to: 5627 + /* 3544 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 28, + 8, + 0, // Skip to: 5627 + /* 3551 */ MCD_OPC_Decode, + 178, + 6, + 248, + 3, // Opcode: FSTMXIA_UPD + /* 3556 */ MCD_OPC_FilterValue, + 26, + 40, + 0, + 0, // Skip to: 3601 + /* 3561 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3564 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3579 + /* 3569 */ MCD_OPC_CheckPredicate, + 34, + 5, + 8, + 0, // Skip to: 5627 + /* 3574 */ MCD_OPC_Decode, + 202, + 29, + 247, + 3, // Opcode: VSTMDDB_UPD + /* 3579 */ MCD_OPC_FilterValue, + 1, + 251, + 7, + 0, // Skip to: 5627 + /* 3584 */ MCD_OPC_CheckPredicate, + 34, + 246, + 7, + 0, // Skip to: 5627 + /* 3589 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 239, + 7, + 0, // Skip to: 5627 + /* 3596 */ MCD_OPC_Decode, + 176, + 6, + 248, + 3, // Opcode: FSTMXDB_UPD + /* 3601 */ MCD_OPC_FilterValue, + 28, + 47, + 0, + 0, // Skip to: 3653 + /* 3606 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3609 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3631 + /* 3614 */ MCD_OPC_CheckPredicate, + 85, + 216, + 7, + 0, // Skip to: 5627 + /* 3619 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 209, + 7, + 0, // Skip to: 5627 + /* 3626 */ MCD_OPC_Decode, + 161, + 23, + 245, + 3, // Opcode: VMULD + /* 3631 */ MCD_OPC_FilterValue, + 1, + 199, + 7, + 0, // Skip to: 5627 + /* 3636 */ MCD_OPC_CheckPredicate, + 85, + 194, + 7, + 0, // Skip to: 5627 + /* 3641 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 187, + 7, + 0, // Skip to: 5627 + /* 3648 */ MCD_OPC_Decode, + 221, + 23, + 245, + 3, // Opcode: VNMULD + /* 3653 */ MCD_OPC_FilterValue, + 29, + 177, + 7, + 0, // Skip to: 5627 + /* 3658 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3661 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3683 + /* 3666 */ MCD_OPC_CheckPredicate, + 86, + 164, + 7, + 0, // Skip to: 5627 + /* 3671 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 157, + 7, + 0, // Skip to: 5627 + /* 3678 */ MCD_OPC_Decode, + 198, + 18, + 244, + 3, // Opcode: VFMAD + /* 3683 */ MCD_OPC_FilterValue, + 1, + 147, + 7, + 0, // Skip to: 5627 + /* 3688 */ MCD_OPC_CheckPredicate, + 86, + 142, + 7, + 0, // Skip to: 5627 + /* 3693 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 135, + 7, + 0, // Skip to: 5627 + /* 3700 */ MCD_OPC_Decode, + 209, + 18, + 244, + 3, // Opcode: VFMSD + /* 3705 */ MCD_OPC_FilterValue, + 3, + 125, + 7, + 0, // Skip to: 5627 + /* 3710 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 3713 */ MCD_OPC_FilterValue, + 25, + 40, + 0, + 0, // Skip to: 3758 + /* 3718 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3721 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3736 + /* 3726 */ MCD_OPC_CheckPredicate, + 34, + 104, + 7, + 0, // Skip to: 5627 + /* 3731 */ MCD_OPC_Decode, + 241, + 21, + 247, + 3, // Opcode: VLDMDIA_UPD + /* 3736 */ MCD_OPC_FilterValue, + 1, + 94, + 7, + 0, // Skip to: 5627 + /* 3741 */ MCD_OPC_CheckPredicate, + 34, + 89, + 7, + 0, // Skip to: 5627 + /* 3746 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 82, + 7, + 0, // Skip to: 5627 + /* 3753 */ MCD_OPC_Decode, + 174, + 6, + 248, + 3, // Opcode: FLDMXIA_UPD + /* 3758 */ MCD_OPC_FilterValue, + 26, + 40, + 0, + 0, // Skip to: 3803 + /* 3763 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3766 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3781 + /* 3771 */ MCD_OPC_CheckPredicate, + 34, + 59, + 7, + 0, // Skip to: 5627 + /* 3776 */ MCD_OPC_Decode, + 239, + 21, + 247, + 3, // Opcode: VLDMDDB_UPD + /* 3781 */ MCD_OPC_FilterValue, + 1, + 49, + 7, + 0, // Skip to: 5627 + /* 3786 */ MCD_OPC_CheckPredicate, + 34, + 44, + 7, + 0, // Skip to: 5627 + /* 3791 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 37, + 7, + 0, // Skip to: 5627 + /* 3798 */ MCD_OPC_Decode, + 172, + 6, + 248, + 3, // Opcode: FLDMXDB_UPD + /* 3803 */ MCD_OPC_FilterValue, + 28, + 47, + 0, + 0, // Skip to: 3855 + /* 3808 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3811 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3833 + /* 3816 */ MCD_OPC_CheckPredicate, + 85, + 14, + 7, + 0, // Skip to: 5627 + /* 3821 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 7, + 7, + 0, // Skip to: 5627 + /* 3828 */ MCD_OPC_Decode, + 150, + 16, + 245, + 3, // Opcode: VADDD + /* 3833 */ MCD_OPC_FilterValue, + 1, + 253, + 6, + 0, // Skip to: 5627 + /* 3838 */ MCD_OPC_CheckPredicate, + 85, + 248, + 6, + 0, // Skip to: 5627 + /* 3843 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 241, + 6, + 0, // Skip to: 5627 + /* 3850 */ MCD_OPC_Decode, + 230, + 29, + 245, + 3, // Opcode: VSUBD + /* 3855 */ MCD_OPC_FilterValue, + 29, + 231, + 6, + 0, // Skip to: 5627 + /* 3860 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 3863 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3885 + /* 3868 */ MCD_OPC_CheckPredicate, + 87, + 218, + 6, + 0, // Skip to: 5627 + /* 3873 */ MCD_OPC_CheckField, + 4, + 2, + 0, + 211, + 6, + 0, // Skip to: 5627 + /* 3880 */ MCD_OPC_Decode, + 169, + 6, + 249, + 3, // Opcode: FCONSTD + /* 3885 */ MCD_OPC_FilterValue, + 1, + 77, + 1, + 0, // Skip to: 4223 + /* 3890 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 3893 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3915 + /* 3898 */ MCD_OPC_CheckPredicate, + 88, + 188, + 6, + 0, // Skip to: 5627 + /* 3903 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 181, + 6, + 0, // Skip to: 5627 + /* 3910 */ MCD_OPC_Decode, + 236, + 22, + 250, + 3, // Opcode: VMOVD + /* 3915 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 3937 + /* 3920 */ MCD_OPC_CheckPredicate, + 85, + 166, + 6, + 0, // Skip to: 5627 + /* 3925 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 159, + 6, + 0, // Skip to: 5627 + /* 3932 */ MCD_OPC_Decode, + 202, + 23, + 250, + 3, // Opcode: VNEGD + /* 3937 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 3959 + /* 3942 */ MCD_OPC_CheckPredicate, + 89, + 144, + 6, + 0, // Skip to: 5627 + /* 3947 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 137, + 6, + 0, // Skip to: 5627 + /* 3954 */ MCD_OPC_Decode, + 217, + 17, + 239, + 3, // Opcode: VCVTBHD + /* 3959 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 3981 + /* 3964 */ MCD_OPC_CheckPredicate, + 89, + 122, + 6, + 0, // Skip to: 5627 + /* 3969 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 115, + 6, + 0, // Skip to: 5627 + /* 3976 */ MCD_OPC_Decode, + 216, + 17, + 251, + 3, // Opcode: VCVTBDH + /* 3981 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 4003 + /* 3986 */ MCD_OPC_CheckPredicate, + 85, + 100, + 6, + 0, // Skip to: 5627 + /* 3991 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 93, + 6, + 0, // Skip to: 5627 + /* 3998 */ MCD_OPC_Decode, + 188, + 17, + 250, + 3, // Opcode: VCMPD + /* 4003 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 4025 + /* 4008 */ MCD_OPC_CheckPredicate, + 85, + 78, + 6, + 0, // Skip to: 5627 + /* 4013 */ MCD_OPC_CheckField, + 0, + 6, + 0, + 71, + 6, + 0, // Skip to: 5627 + /* 4020 */ MCD_OPC_Decode, + 197, + 17, + 252, + 3, // Opcode: VCMPZD + /* 4025 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 4047 + /* 4030 */ MCD_OPC_CheckPredicate, + 89, + 56, + 6, + 0, // Skip to: 5627 + /* 4035 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 49, + 6, + 0, // Skip to: 5627 + /* 4042 */ MCD_OPC_Decode, + 129, + 26, + 250, + 3, // Opcode: VRINTRD + /* 4047 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 4069 + /* 4052 */ MCD_OPC_CheckPredicate, + 89, + 34, + 6, + 0, // Skip to: 5627 + /* 4057 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 27, + 6, + 0, // Skip to: 5627 + /* 4064 */ MCD_OPC_Decode, + 132, + 26, + 250, + 3, // Opcode: VRINTXD + /* 4069 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 4091 + /* 4074 */ MCD_OPC_CheckPredicate, + 85, + 12, + 6, + 0, // Skip to: 5627 + /* 4079 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 5, + 6, + 0, // Skip to: 5627 + /* 4086 */ MCD_OPC_Decode, + 191, + 30, + 239, + 3, // Opcode: VUITOD + /* 4091 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 4113 + /* 4096 */ MCD_OPC_CheckPredicate, + 85, + 246, + 5, + 0, // Skip to: 5627 + /* 4101 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 239, + 5, + 0, // Skip to: 5627 + /* 4108 */ MCD_OPC_Decode, + 155, + 27, + 253, + 3, // Opcode: VSHTOD + /* 4113 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 4135 + /* 4118 */ MCD_OPC_CheckPredicate, + 85, + 224, + 5, + 0, // Skip to: 5627 + /* 4123 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 217, + 5, + 0, // Skip to: 5627 + /* 4130 */ MCD_OPC_Decode, + 188, + 30, + 253, + 3, // Opcode: VUHTOD + /* 4135 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 4157 + /* 4140 */ MCD_OPC_CheckPredicate, + 85, + 202, + 5, + 0, // Skip to: 5627 + /* 4145 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 195, + 5, + 0, // Skip to: 5627 + /* 4152 */ MCD_OPC_Decode, + 163, + 30, + 254, + 3, // Opcode: VTOUIRD + /* 4157 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 4179 + /* 4162 */ MCD_OPC_CheckPredicate, + 85, + 180, + 5, + 0, // Skip to: 5627 + /* 4167 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 173, + 5, + 0, // Skip to: 5627 + /* 4174 */ MCD_OPC_Decode, + 151, + 30, + 254, + 3, // Opcode: VTOSIRD + /* 4179 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 4201 + /* 4184 */ MCD_OPC_CheckPredicate, + 85, + 158, + 5, + 0, // Skip to: 5627 + /* 4189 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 151, + 5, + 0, // Skip to: 5627 + /* 4196 */ MCD_OPC_Decode, + 148, + 30, + 253, + 3, // Opcode: VTOSHD + /* 4201 */ MCD_OPC_FilterValue, + 15, + 141, + 5, + 0, // Skip to: 5627 + /* 4206 */ MCD_OPC_CheckPredicate, + 85, + 136, + 5, + 0, // Skip to: 5627 + /* 4211 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 129, + 5, + 0, // Skip to: 5627 + /* 4218 */ MCD_OPC_Decode, + 160, + 30, + 253, + 3, // Opcode: VTOUHD + /* 4223 */ MCD_OPC_FilterValue, + 3, + 119, + 5, + 0, // Skip to: 5627 + /* 4228 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 4231 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4253 + /* 4236 */ MCD_OPC_CheckPredicate, + 85, + 106, + 5, + 0, // Skip to: 5627 + /* 4241 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 99, + 5, + 0, // Skip to: 5627 + /* 4248 */ MCD_OPC_Decode, + 129, + 16, + 250, + 3, // Opcode: VABSD + /* 4253 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 4275 + /* 4258 */ MCD_OPC_CheckPredicate, + 85, + 84, + 5, + 0, // Skip to: 5627 + /* 4263 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 77, + 5, + 0, // Skip to: 5627 + /* 4270 */ MCD_OPC_Decode, + 173, + 27, + 250, + 3, // Opcode: VSQRTD + /* 4275 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 4297 + /* 4280 */ MCD_OPC_CheckPredicate, + 89, + 62, + 5, + 0, // Skip to: 5627 + /* 4285 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 55, + 5, + 0, // Skip to: 5627 + /* 4292 */ MCD_OPC_Decode, + 137, + 18, + 239, + 3, // Opcode: VCVTTHD + /* 4297 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 4319 + /* 4302 */ MCD_OPC_CheckPredicate, + 89, + 40, + 5, + 0, // Skip to: 5627 + /* 4307 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 33, + 5, + 0, // Skip to: 5627 + /* 4314 */ MCD_OPC_Decode, + 136, + 18, + 251, + 3, // Opcode: VCVTTDH + /* 4319 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 4341 + /* 4324 */ MCD_OPC_CheckPredicate, + 85, + 18, + 5, + 0, // Skip to: 5627 + /* 4329 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 11, + 5, + 0, // Skip to: 5627 + /* 4336 */ MCD_OPC_Decode, + 189, + 17, + 250, + 3, // Opcode: VCMPED + /* 4341 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 4363 + /* 4346 */ MCD_OPC_CheckPredicate, + 85, + 252, + 4, + 0, // Skip to: 5627 + /* 4351 */ MCD_OPC_CheckField, + 0, + 6, + 0, + 245, + 4, + 0, // Skip to: 5627 + /* 4358 */ MCD_OPC_Decode, + 192, + 17, + 252, + 3, // Opcode: VCMPEZD + /* 4363 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 4385 + /* 4368 */ MCD_OPC_CheckPredicate, + 89, + 230, + 4, + 0, // Skip to: 5627 + /* 4373 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 223, + 4, + 0, // Skip to: 5627 + /* 4380 */ MCD_OPC_Decode, + 139, + 26, + 250, + 3, // Opcode: VRINTZD + /* 4385 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 4407 + /* 4390 */ MCD_OPC_CheckPredicate, + 85, + 208, + 4, + 0, // Skip to: 5627 + /* 4395 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 201, + 4, + 0, // Skip to: 5627 + /* 4402 */ MCD_OPC_Decode, + 135, + 18, + 254, + 3, // Opcode: VCVTSD + /* 4407 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 4429 + /* 4412 */ MCD_OPC_CheckPredicate, + 85, + 186, + 4, + 0, // Skip to: 5627 + /* 4417 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 179, + 4, + 0, // Skip to: 5627 + /* 4424 */ MCD_OPC_Decode, + 158, + 27, + 239, + 3, // Opcode: VSITOD + /* 4429 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 4451 + /* 4434 */ MCD_OPC_CheckPredicate, + 90, + 164, + 4, + 0, // Skip to: 5627 + /* 4439 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 157, + 4, + 0, // Skip to: 5627 + /* 4446 */ MCD_OPC_Decode, + 134, + 19, + 254, + 3, // Opcode: VJCVT + /* 4451 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 4473 + /* 4456 */ MCD_OPC_CheckPredicate, + 85, + 142, + 4, + 0, // Skip to: 5627 + /* 4461 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 135, + 4, + 0, // Skip to: 5627 + /* 4468 */ MCD_OPC_Decode, + 169, + 27, + 253, + 3, // Opcode: VSLTOD + /* 4473 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 4495 + /* 4478 */ MCD_OPC_CheckPredicate, + 85, + 120, + 4, + 0, // Skip to: 5627 + /* 4483 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 113, + 4, + 0, // Skip to: 5627 + /* 4490 */ MCD_OPC_Decode, + 194, + 30, + 253, + 3, // Opcode: VULTOD + /* 4495 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 4517 + /* 4500 */ MCD_OPC_CheckPredicate, + 85, + 98, + 4, + 0, // Skip to: 5627 + /* 4505 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 91, + 4, + 0, // Skip to: 5627 + /* 4512 */ MCD_OPC_Decode, + 166, + 30, + 254, + 3, // Opcode: VTOUIZD + /* 4517 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 4539 + /* 4522 */ MCD_OPC_CheckPredicate, + 85, + 76, + 4, + 0, // Skip to: 5627 + /* 4527 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 69, + 4, + 0, // Skip to: 5627 + /* 4534 */ MCD_OPC_Decode, + 154, + 30, + 254, + 3, // Opcode: VTOSIZD + /* 4539 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 4561 + /* 4544 */ MCD_OPC_CheckPredicate, + 85, + 54, + 4, + 0, // Skip to: 5627 + /* 4549 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 47, + 4, + 0, // Skip to: 5627 + /* 4556 */ MCD_OPC_Decode, + 157, + 30, + 253, + 3, // Opcode: VTOSLD + /* 4561 */ MCD_OPC_FilterValue, + 15, + 37, + 4, + 0, // Skip to: 5627 + /* 4566 */ MCD_OPC_CheckPredicate, + 85, + 32, + 4, + 0, // Skip to: 5627 + /* 4571 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 25, + 4, + 0, // Skip to: 5627 + /* 4578 */ MCD_OPC_Decode, + 169, + 30, + 253, + 3, // Opcode: VTOULD + /* 4583 */ MCD_OPC_FilterValue, + 15, + 15, + 4, + 0, // Skip to: 5627 + /* 4588 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 4591 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 4657 + /* 4596 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4599 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 4628 + /* 4604 */ MCD_OPC_CheckPredicate, + 25, + 250, + 3, + 0, // Skip to: 5627 + /* 4609 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 243, + 3, + 0, // Skip to: 5627 + /* 4616 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 236, + 3, + 0, // Skip to: 5627 + /* 4623 */ MCD_OPC_Decode, + 221, + 29, + 255, + 3, // Opcode: VSTR_FPSCR_off + /* 4628 */ MCD_OPC_FilterValue, + 4, + 226, + 3, + 0, // Skip to: 5627 + /* 4633 */ MCD_OPC_CheckPredicate, + 25, + 221, + 3, + 0, // Skip to: 5627 + /* 4638 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 214, + 3, + 0, // Skip to: 5627 + /* 4645 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 207, + 3, + 0, // Skip to: 5627 + /* 4652 */ MCD_OPC_Decode, + 218, + 29, + 255, + 3, // Opcode: VSTR_FPSCR_NZCVQC_off + /* 4657 */ MCD_OPC_FilterValue, + 1, + 61, + 0, + 0, // Skip to: 4723 + /* 4662 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4665 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 4694 + /* 4670 */ MCD_OPC_CheckPredicate, + 25, + 184, + 3, + 0, // Skip to: 5627 + /* 4675 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 177, + 3, + 0, // Skip to: 5627 + /* 4682 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 170, + 3, + 0, // Skip to: 5627 + /* 4689 */ MCD_OPC_Decode, + 130, + 22, + 255, + 3, // Opcode: VLDR_FPSCR_off + /* 4694 */ MCD_OPC_FilterValue, + 4, + 160, + 3, + 0, // Skip to: 5627 + /* 4699 */ MCD_OPC_CheckPredicate, + 25, + 155, + 3, + 0, // Skip to: 5627 + /* 4704 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 148, + 3, + 0, // Skip to: 5627 + /* 4711 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 141, + 3, + 0, // Skip to: 5627 + /* 4718 */ MCD_OPC_Decode, + 255, + 21, + 255, + 3, // Opcode: VLDR_FPSCR_NZCVQC_off + /* 4723 */ MCD_OPC_FilterValue, + 2, + 107, + 0, + 0, // Skip to: 4835 + /* 4728 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4731 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 4783 + /* 4736 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 4739 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 4761 + /* 4744 */ MCD_OPC_CheckPredicate, + 25, + 110, + 3, + 0, // Skip to: 5627 + /* 4749 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 103, + 3, + 0, // Skip to: 5627 + /* 4756 */ MCD_OPC_Decode, + 222, + 29, + 128, + 4, // Opcode: VSTR_FPSCR_post + /* 4761 */ MCD_OPC_FilterValue, + 13, + 93, + 3, + 0, // Skip to: 5627 + /* 4766 */ MCD_OPC_CheckPredicate, + 25, + 88, + 3, + 0, // Skip to: 5627 + /* 4771 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 81, + 3, + 0, // Skip to: 5627 + /* 4778 */ MCD_OPC_Decode, + 223, + 29, + 128, + 4, // Opcode: VSTR_FPSCR_pre + /* 4783 */ MCD_OPC_FilterValue, + 4, + 71, + 3, + 0, // Skip to: 5627 + /* 4788 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 4791 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 4813 + /* 4796 */ MCD_OPC_CheckPredicate, + 25, + 58, + 3, + 0, // Skip to: 5627 + /* 4801 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 51, + 3, + 0, // Skip to: 5627 + /* 4808 */ MCD_OPC_Decode, + 219, + 29, + 128, + 4, // Opcode: VSTR_FPSCR_NZCVQC_post + /* 4813 */ MCD_OPC_FilterValue, + 13, + 41, + 3, + 0, // Skip to: 5627 + /* 4818 */ MCD_OPC_CheckPredicate, + 25, + 36, + 3, + 0, // Skip to: 5627 + /* 4823 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 29, + 3, + 0, // Skip to: 5627 + /* 4830 */ MCD_OPC_Decode, + 220, + 29, + 128, + 4, // Opcode: VSTR_FPSCR_NZCVQC_pre + /* 4835 */ MCD_OPC_FilterValue, + 3, + 107, + 0, + 0, // Skip to: 4947 + /* 4840 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4843 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 4895 + /* 4848 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 4851 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 4873 + /* 4856 */ MCD_OPC_CheckPredicate, + 25, + 254, + 2, + 0, // Skip to: 5627 + /* 4861 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 247, + 2, + 0, // Skip to: 5627 + /* 4868 */ MCD_OPC_Decode, + 131, + 22, + 128, + 4, // Opcode: VLDR_FPSCR_post + /* 4873 */ MCD_OPC_FilterValue, + 13, + 237, + 2, + 0, // Skip to: 5627 + /* 4878 */ MCD_OPC_CheckPredicate, + 25, + 232, + 2, + 0, // Skip to: 5627 + /* 4883 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 225, + 2, + 0, // Skip to: 5627 + /* 4890 */ MCD_OPC_Decode, + 132, + 22, + 128, + 4, // Opcode: VLDR_FPSCR_pre + /* 4895 */ MCD_OPC_FilterValue, + 4, + 215, + 2, + 0, // Skip to: 5627 + /* 4900 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 4903 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 4925 + /* 4908 */ MCD_OPC_CheckPredicate, + 25, + 202, + 2, + 0, // Skip to: 5627 + /* 4913 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 195, + 2, + 0, // Skip to: 5627 + /* 4920 */ MCD_OPC_Decode, + 128, + 22, + 128, + 4, // Opcode: VLDR_FPSCR_NZCVQC_post + /* 4925 */ MCD_OPC_FilterValue, + 13, + 185, + 2, + 0, // Skip to: 5627 + /* 4930 */ MCD_OPC_CheckPredicate, + 25, + 180, + 2, + 0, // Skip to: 5627 + /* 4935 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 173, + 2, + 0, // Skip to: 5627 + /* 4942 */ MCD_OPC_Decode, + 129, + 22, + 128, + 4, // Opcode: VLDR_FPSCR_NZCVQC_pre + /* 4947 */ MCD_OPC_FilterValue, + 4, + 119, + 0, + 0, // Skip to: 5071 + /* 4952 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4955 */ MCD_OPC_FilterValue, + 8, + 24, + 0, + 0, // Skip to: 4984 + /* 4960 */ MCD_OPC_CheckPredicate, + 23, + 150, + 2, + 0, // Skip to: 5627 + /* 4965 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 143, + 2, + 0, // Skip to: 5627 + /* 4972 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 136, + 2, + 0, // Skip to: 5627 + /* 4979 */ MCD_OPC_Decode, + 227, + 29, + 255, + 3, // Opcode: VSTR_VPR_off + /* 4984 */ MCD_OPC_FilterValue, + 10, + 24, + 0, + 0, // Skip to: 5013 + /* 4989 */ MCD_OPC_CheckPredicate, + 23, + 121, + 2, + 0, // Skip to: 5627 + /* 4994 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 114, + 2, + 0, // Skip to: 5627 + /* 5001 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 107, + 2, + 0, // Skip to: 5627 + /* 5008 */ MCD_OPC_Decode, + 224, + 29, + 255, + 3, // Opcode: VSTR_P0_off + /* 5013 */ MCD_OPC_FilterValue, + 12, + 24, + 0, + 0, // Skip to: 5042 + /* 5018 */ MCD_OPC_CheckPredicate, + 78, + 92, + 2, + 0, // Skip to: 5627 + /* 5023 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 85, + 2, + 0, // Skip to: 5627 + /* 5030 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 78, + 2, + 0, // Skip to: 5627 + /* 5037 */ MCD_OPC_Decode, + 212, + 29, + 255, + 3, // Opcode: VSTR_FPCXTNS_off + /* 5042 */ MCD_OPC_FilterValue, + 14, + 68, + 2, + 0, // Skip to: 5627 + /* 5047 */ MCD_OPC_CheckPredicate, + 78, + 63, + 2, + 0, // Skip to: 5627 + /* 5052 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 56, + 2, + 0, // Skip to: 5627 + /* 5059 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 49, + 2, + 0, // Skip to: 5627 + /* 5066 */ MCD_OPC_Decode, + 215, + 29, + 255, + 3, // Opcode: VSTR_FPCXTS_off + /* 5071 */ MCD_OPC_FilterValue, + 5, + 119, + 0, + 0, // Skip to: 5195 + /* 5076 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5079 */ MCD_OPC_FilterValue, + 8, + 24, + 0, + 0, // Skip to: 5108 + /* 5084 */ MCD_OPC_CheckPredicate, + 23, + 26, + 2, + 0, // Skip to: 5627 + /* 5089 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 19, + 2, + 0, // Skip to: 5627 + /* 5096 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 12, + 2, + 0, // Skip to: 5627 + /* 5103 */ MCD_OPC_Decode, + 136, + 22, + 255, + 3, // Opcode: VLDR_VPR_off + /* 5108 */ MCD_OPC_FilterValue, + 10, + 24, + 0, + 0, // Skip to: 5137 + /* 5113 */ MCD_OPC_CheckPredicate, + 23, + 253, + 1, + 0, // Skip to: 5627 + /* 5118 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 246, + 1, + 0, // Skip to: 5627 + /* 5125 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 239, + 1, + 0, // Skip to: 5627 + /* 5132 */ MCD_OPC_Decode, + 133, + 22, + 255, + 3, // Opcode: VLDR_P0_off + /* 5137 */ MCD_OPC_FilterValue, + 12, + 24, + 0, + 0, // Skip to: 5166 + /* 5142 */ MCD_OPC_CheckPredicate, + 78, + 224, + 1, + 0, // Skip to: 5627 + /* 5147 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 217, + 1, + 0, // Skip to: 5627 + /* 5154 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 210, + 1, + 0, // Skip to: 5627 + /* 5161 */ MCD_OPC_Decode, + 249, + 21, + 255, + 3, // Opcode: VLDR_FPCXTNS_off + /* 5166 */ MCD_OPC_FilterValue, + 14, + 200, + 1, + 0, // Skip to: 5627 + /* 5171 */ MCD_OPC_CheckPredicate, + 78, + 195, + 1, + 0, // Skip to: 5627 + /* 5176 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 188, + 1, + 0, // Skip to: 5627 + /* 5183 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 181, + 1, + 0, // Skip to: 5627 + /* 5190 */ MCD_OPC_Decode, + 252, + 21, + 255, + 3, // Opcode: VLDR_FPCXTS_off + /* 5195 */ MCD_OPC_FilterValue, + 6, + 211, + 0, + 0, // Skip to: 5411 + /* 5200 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5203 */ MCD_OPC_FilterValue, + 8, + 47, + 0, + 0, // Skip to: 5255 + /* 5208 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5211 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5233 + /* 5216 */ MCD_OPC_CheckPredicate, + 23, + 150, + 1, + 0, // Skip to: 5627 + /* 5221 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 143, + 1, + 0, // Skip to: 5627 + /* 5228 */ MCD_OPC_Decode, + 228, + 29, + 128, + 4, // Opcode: VSTR_VPR_post + /* 5233 */ MCD_OPC_FilterValue, + 13, + 133, + 1, + 0, // Skip to: 5627 + /* 5238 */ MCD_OPC_CheckPredicate, + 23, + 128, + 1, + 0, // Skip to: 5627 + /* 5243 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 121, + 1, + 0, // Skip to: 5627 + /* 5250 */ MCD_OPC_Decode, + 229, + 29, + 128, + 4, // Opcode: VSTR_VPR_pre + /* 5255 */ MCD_OPC_FilterValue, + 10, + 47, + 0, + 0, // Skip to: 5307 + /* 5260 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5263 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5285 + /* 5268 */ MCD_OPC_CheckPredicate, + 23, + 98, + 1, + 0, // Skip to: 5627 + /* 5273 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 91, + 1, + 0, // Skip to: 5627 + /* 5280 */ MCD_OPC_Decode, + 225, + 29, + 128, + 4, // Opcode: VSTR_P0_post + /* 5285 */ MCD_OPC_FilterValue, + 13, + 81, + 1, + 0, // Skip to: 5627 + /* 5290 */ MCD_OPC_CheckPredicate, + 23, + 76, + 1, + 0, // Skip to: 5627 + /* 5295 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 69, + 1, + 0, // Skip to: 5627 + /* 5302 */ MCD_OPC_Decode, + 226, + 29, + 128, + 4, // Opcode: VSTR_P0_pre + /* 5307 */ MCD_OPC_FilterValue, + 12, + 47, + 0, + 0, // Skip to: 5359 + /* 5312 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5315 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5337 + /* 5320 */ MCD_OPC_CheckPredicate, + 78, + 46, + 1, + 0, // Skip to: 5627 + /* 5325 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 39, + 1, + 0, // Skip to: 5627 + /* 5332 */ MCD_OPC_Decode, + 213, + 29, + 128, + 4, // Opcode: VSTR_FPCXTNS_post + /* 5337 */ MCD_OPC_FilterValue, + 13, + 29, + 1, + 0, // Skip to: 5627 + /* 5342 */ MCD_OPC_CheckPredicate, + 78, + 24, + 1, + 0, // Skip to: 5627 + /* 5347 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 17, + 1, + 0, // Skip to: 5627 + /* 5354 */ MCD_OPC_Decode, + 214, + 29, + 128, + 4, // Opcode: VSTR_FPCXTNS_pre + /* 5359 */ MCD_OPC_FilterValue, + 14, + 7, + 1, + 0, // Skip to: 5627 + /* 5364 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5367 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5389 + /* 5372 */ MCD_OPC_CheckPredicate, + 78, + 250, + 0, + 0, // Skip to: 5627 + /* 5377 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 243, + 0, + 0, // Skip to: 5627 + /* 5384 */ MCD_OPC_Decode, + 216, + 29, + 128, + 4, // Opcode: VSTR_FPCXTS_post + /* 5389 */ MCD_OPC_FilterValue, + 13, + 233, + 0, + 0, // Skip to: 5627 + /* 5394 */ MCD_OPC_CheckPredicate, + 78, + 228, + 0, + 0, // Skip to: 5627 + /* 5399 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 221, + 0, + 0, // Skip to: 5627 + /* 5406 */ MCD_OPC_Decode, + 217, + 29, + 128, + 4, // Opcode: VSTR_FPCXTS_pre + /* 5411 */ MCD_OPC_FilterValue, + 7, + 211, + 0, + 0, // Skip to: 5627 + /* 5416 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5419 */ MCD_OPC_FilterValue, + 8, + 47, + 0, + 0, // Skip to: 5471 + /* 5424 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5427 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5449 + /* 5432 */ MCD_OPC_CheckPredicate, + 23, + 190, + 0, + 0, // Skip to: 5627 + /* 5437 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 183, + 0, + 0, // Skip to: 5627 + /* 5444 */ MCD_OPC_Decode, + 137, + 22, + 128, + 4, // Opcode: VLDR_VPR_post + /* 5449 */ MCD_OPC_FilterValue, + 13, + 173, + 0, + 0, // Skip to: 5627 + /* 5454 */ MCD_OPC_CheckPredicate, + 23, + 168, + 0, + 0, // Skip to: 5627 + /* 5459 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 161, + 0, + 0, // Skip to: 5627 + /* 5466 */ MCD_OPC_Decode, + 138, + 22, + 128, + 4, // Opcode: VLDR_VPR_pre + /* 5471 */ MCD_OPC_FilterValue, + 10, + 47, + 0, + 0, // Skip to: 5523 + /* 5476 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5479 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5501 + /* 5484 */ MCD_OPC_CheckPredicate, + 23, + 138, + 0, + 0, // Skip to: 5627 + /* 5489 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 131, + 0, + 0, // Skip to: 5627 + /* 5496 */ MCD_OPC_Decode, + 134, + 22, + 128, + 4, // Opcode: VLDR_P0_post + /* 5501 */ MCD_OPC_FilterValue, + 13, + 121, + 0, + 0, // Skip to: 5627 + /* 5506 */ MCD_OPC_CheckPredicate, + 23, + 116, + 0, + 0, // Skip to: 5627 + /* 5511 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 109, + 0, + 0, // Skip to: 5627 + /* 5518 */ MCD_OPC_Decode, + 135, + 22, + 128, + 4, // Opcode: VLDR_P0_pre + /* 5523 */ MCD_OPC_FilterValue, + 12, + 47, + 0, + 0, // Skip to: 5575 + /* 5528 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5531 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5553 + /* 5536 */ MCD_OPC_CheckPredicate, + 78, + 86, + 0, + 0, // Skip to: 5627 + /* 5541 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 79, + 0, + 0, // Skip to: 5627 + /* 5548 */ MCD_OPC_Decode, + 250, + 21, + 128, + 4, // Opcode: VLDR_FPCXTNS_post + /* 5553 */ MCD_OPC_FilterValue, + 13, + 69, + 0, + 0, // Skip to: 5627 + /* 5558 */ MCD_OPC_CheckPredicate, + 78, + 64, + 0, + 0, // Skip to: 5627 + /* 5563 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 57, + 0, + 0, // Skip to: 5627 + /* 5570 */ MCD_OPC_Decode, + 251, + 21, + 128, + 4, // Opcode: VLDR_FPCXTNS_pre + /* 5575 */ MCD_OPC_FilterValue, + 14, + 47, + 0, + 0, // Skip to: 5627 + /* 5580 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5583 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5605 + /* 5588 */ MCD_OPC_CheckPredicate, + 78, + 34, + 0, + 0, // Skip to: 5627 + /* 5593 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 27, + 0, + 0, // Skip to: 5627 + /* 5600 */ MCD_OPC_Decode, + 253, + 21, + 128, + 4, // Opcode: VLDR_FPCXTS_post + /* 5605 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 5627 + /* 5610 */ MCD_OPC_CheckPredicate, + 78, + 12, + 0, + 0, // Skip to: 5627 + /* 5615 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 5, + 0, + 0, // Skip to: 5627 + /* 5622 */ MCD_OPC_Decode, + 254, + 21, + 128, + 4, // Opcode: VLDR_FPCXTS_pre + /* 5627 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableVFPV832[] = { + /* 0 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 3 */ MCD_OPC_FilterValue, + 8, + 47, + 2, + 0, // Skip to: 567 + /* 8 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 3, + 1, + 0, // Skip to: 275 + /* 16 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 123, + 0, + 0, // Skip to: 147 + /* 24 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 27 */ MCD_OPC_FilterValue, + 126, + 77, + 0, + 0, // Skip to: 109 + /* 32 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 35 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 57 + /* 40 */ MCD_OPC_CheckPredicate, + 91, + 119, + 12, + 0, // Skip to: 3236 + /* 45 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 112, + 12, + 0, // Skip to: 3236 + /* 52 */ MCD_OPC_Decode, + 201, + 16, + 129, + 4, // Opcode: VCADDv4f16 + /* 57 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 79 + /* 62 */ MCD_OPC_CheckPredicate, + 92, + 97, + 12, + 0, // Skip to: 3236 + /* 67 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 90, + 12, + 0, // Skip to: 3236 + /* 74 */ MCD_OPC_Decode, + 200, + 16, + 129, + 4, // Opcode: VCADDv2f32 + /* 79 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 94 + /* 84 */ MCD_OPC_CheckPredicate, + 91, + 75, + 12, + 0, // Skip to: 3236 + /* 89 */ MCD_OPC_Decode, + 182, + 17, + 130, + 4, // Opcode: VCMLAv4f16 + /* 94 */ MCD_OPC_FilterValue, + 3, + 65, + 12, + 0, // Skip to: 3236 + /* 99 */ MCD_OPC_CheckPredicate, + 92, + 60, + 12, + 0, // Skip to: 3236 + /* 104 */ MCD_OPC_Decode, + 180, + 17, + 130, + 4, // Opcode: VCMLAv2f32 + /* 109 */ MCD_OPC_FilterValue, + 127, + 50, + 12, + 0, // Skip to: 3236 + /* 114 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 117 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 132 + /* 122 */ MCD_OPC_CheckPredicate, + 91, + 37, + 12, + 0, // Skip to: 3236 + /* 127 */ MCD_OPC_Decode, + 183, + 17, + 131, + 4, // Opcode: VCMLAv4f16_indexed + /* 132 */ MCD_OPC_FilterValue, + 1, + 27, + 12, + 0, // Skip to: 3236 + /* 137 */ MCD_OPC_CheckPredicate, + 92, + 22, + 12, + 0, // Skip to: 3236 + /* 142 */ MCD_OPC_Decode, + 181, + 17, + 132, + 4, // Opcode: VCMLAv2f32_indexed + /* 147 */ MCD_OPC_FilterValue, + 1, + 12, + 12, + 0, // Skip to: 3236 + /* 152 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 155 */ MCD_OPC_FilterValue, + 126, + 77, + 0, + 0, // Skip to: 237 + /* 160 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 163 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 185 + /* 168 */ MCD_OPC_CheckPredicate, + 91, + 247, + 11, + 0, // Skip to: 3236 + /* 173 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 240, + 11, + 0, // Skip to: 3236 + /* 180 */ MCD_OPC_Decode, + 203, + 16, + 133, + 4, // Opcode: VCADDv8f16 + /* 185 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 207 + /* 190 */ MCD_OPC_CheckPredicate, + 92, + 225, + 11, + 0, // Skip to: 3236 + /* 195 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 218, + 11, + 0, // Skip to: 3236 + /* 202 */ MCD_OPC_Decode, + 202, + 16, + 133, + 4, // Opcode: VCADDv4f32 + /* 207 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 222 + /* 212 */ MCD_OPC_CheckPredicate, + 91, + 203, + 11, + 0, // Skip to: 3236 + /* 217 */ MCD_OPC_Decode, + 186, + 17, + 134, + 4, // Opcode: VCMLAv8f16 + /* 222 */ MCD_OPC_FilterValue, + 3, + 193, + 11, + 0, // Skip to: 3236 + /* 227 */ MCD_OPC_CheckPredicate, + 92, + 188, + 11, + 0, // Skip to: 3236 + /* 232 */ MCD_OPC_Decode, + 184, + 17, + 134, + 4, // Opcode: VCMLAv4f32 + /* 237 */ MCD_OPC_FilterValue, + 127, + 178, + 11, + 0, // Skip to: 3236 + /* 242 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 245 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 260 + /* 250 */ MCD_OPC_CheckPredicate, + 91, + 165, + 11, + 0, // Skip to: 3236 + /* 255 */ MCD_OPC_Decode, + 187, + 17, + 135, + 4, // Opcode: VCMLAv8f16_indexed + /* 260 */ MCD_OPC_FilterValue, + 1, + 155, + 11, + 0, // Skip to: 3236 + /* 265 */ MCD_OPC_CheckPredicate, + 92, + 150, + 11, + 0, // Skip to: 3236 + /* 270 */ MCD_OPC_Decode, + 185, + 17, + 132, + 4, // Opcode: VCMLAv4f32_indexed + /* 275 */ MCD_OPC_FilterValue, + 1, + 140, + 11, + 0, // Skip to: 3236 + /* 280 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 283 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 337 + /* 288 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 291 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 314 + /* 296 */ MCD_OPC_CheckPredicate, + 93, + 119, + 11, + 0, // Skip to: 3236 + /* 301 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 111, + 11, + 0, // Skip to: 3236 + /* 309 */ MCD_OPC_Decode, + 201, + 18, + 136, + 4, // Opcode: VFMALDI + /* 314 */ MCD_OPC_FilterValue, + 1, + 101, + 11, + 0, // Skip to: 3236 + /* 319 */ MCD_OPC_CheckPredicate, + 93, + 96, + 11, + 0, // Skip to: 3236 + /* 324 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 88, + 11, + 0, // Skip to: 3236 + /* 332 */ MCD_OPC_Decode, + 203, + 18, + 217, + 1, // Opcode: VFMALQI + /* 337 */ MCD_OPC_FilterValue, + 1, + 49, + 0, + 0, // Skip to: 391 + /* 342 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 345 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 368 + /* 350 */ MCD_OPC_CheckPredicate, + 93, + 65, + 11, + 0, // Skip to: 3236 + /* 355 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 57, + 11, + 0, // Skip to: 3236 + /* 363 */ MCD_OPC_Decode, + 212, + 18, + 136, + 4, // Opcode: VFMSLDI + /* 368 */ MCD_OPC_FilterValue, + 1, + 47, + 11, + 0, // Skip to: 3236 + /* 373 */ MCD_OPC_CheckPredicate, + 93, + 42, + 11, + 0, // Skip to: 3236 + /* 378 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 34, + 11, + 0, // Skip to: 3236 + /* 386 */ MCD_OPC_Decode, + 214, + 18, + 217, + 1, // Opcode: VFMSLQI + /* 391 */ MCD_OPC_FilterValue, + 2, + 83, + 0, + 0, // Skip to: 479 + /* 396 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 399 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 439 + /* 404 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 407 */ MCD_OPC_FilterValue, + 248, + 3, + 10, + 0, + 0, // Skip to: 423 + /* 413 */ MCD_OPC_CheckPredicate, + 93, + 2, + 11, + 0, // Skip to: 3236 + /* 418 */ MCD_OPC_Decode, + 200, + 18, + 137, + 4, // Opcode: VFMALD + /* 423 */ MCD_OPC_FilterValue, + 249, + 3, + 247, + 10, + 0, // Skip to: 3236 + /* 429 */ MCD_OPC_CheckPredicate, + 93, + 242, + 10, + 0, // Skip to: 3236 + /* 434 */ MCD_OPC_Decode, + 211, + 18, + 137, + 4, // Opcode: VFMSLD + /* 439 */ MCD_OPC_FilterValue, + 1, + 232, + 10, + 0, // Skip to: 3236 + /* 444 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 447 */ MCD_OPC_FilterValue, + 248, + 3, + 10, + 0, + 0, // Skip to: 463 + /* 453 */ MCD_OPC_CheckPredicate, + 93, + 218, + 10, + 0, // Skip to: 3236 + /* 458 */ MCD_OPC_Decode, + 202, + 18, + 204, + 1, // Opcode: VFMALQ + /* 463 */ MCD_OPC_FilterValue, + 249, + 3, + 207, + 10, + 0, // Skip to: 3236 + /* 469 */ MCD_OPC_CheckPredicate, + 93, + 202, + 10, + 0, // Skip to: 3236 + /* 474 */ MCD_OPC_Decode, + 213, + 18, + 204, + 1, // Opcode: VFMSLQ + /* 479 */ MCD_OPC_FilterValue, + 3, + 192, + 10, + 0, // Skip to: 3236 + /* 484 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 487 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 527 + /* 492 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 495 */ MCD_OPC_FilterValue, + 248, + 3, + 10, + 0, + 0, // Skip to: 511 + /* 501 */ MCD_OPC_CheckPredicate, + 31, + 170, + 10, + 0, // Skip to: 3236 + /* 506 */ MCD_OPC_Decode, + 182, + 16, + 211, + 1, // Opcode: VBF16MALBQ + /* 511 */ MCD_OPC_FilterValue, + 252, + 3, + 159, + 10, + 0, // Skip to: 3236 + /* 517 */ MCD_OPC_CheckPredicate, + 31, + 154, + 10, + 0, // Skip to: 3236 + /* 522 */ MCD_OPC_Decode, + 183, + 16, + 213, + 1, // Opcode: VBF16MALBQI + /* 527 */ MCD_OPC_FilterValue, + 1, + 144, + 10, + 0, // Skip to: 3236 + /* 532 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 535 */ MCD_OPC_FilterValue, + 248, + 3, + 10, + 0, + 0, // Skip to: 551 + /* 541 */ MCD_OPC_CheckPredicate, + 31, + 130, + 10, + 0, // Skip to: 3236 + /* 546 */ MCD_OPC_Decode, + 184, + 16, + 211, + 1, // Opcode: VBF16MALTQ + /* 551 */ MCD_OPC_FilterValue, + 252, + 3, + 119, + 10, + 0, // Skip to: 3236 + /* 557 */ MCD_OPC_CheckPredicate, + 31, + 114, + 10, + 0, // Skip to: 3236 + /* 562 */ MCD_OPC_Decode, + 185, + 16, + 213, + 1, // Opcode: VBF16MALTQI + /* 567 */ MCD_OPC_FilterValue, + 9, + 189, + 2, + 0, // Skip to: 1273 + /* 572 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 575 */ MCD_OPC_FilterValue, + 0, + 87, + 0, + 0, // Skip to: 667 + /* 580 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 583 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 637 + /* 588 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 591 */ MCD_OPC_FilterValue, + 252, + 3, + 17, + 0, + 0, // Skip to: 614 + /* 597 */ MCD_OPC_CheckPredicate, + 77, + 74, + 10, + 0, // Skip to: 3236 + /* 602 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 67, + 10, + 0, // Skip to: 3236 + /* 609 */ MCD_OPC_Decode, + 217, + 26, + 138, + 4, // Opcode: VSELEQH + /* 614 */ MCD_OPC_FilterValue, + 253, + 3, + 56, + 10, + 0, // Skip to: 3236 + /* 620 */ MCD_OPC_CheckPredicate, + 77, + 51, + 10, + 0, // Skip to: 3236 + /* 625 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 44, + 10, + 0, // Skip to: 3236 + /* 632 */ MCD_OPC_Decode, + 227, + 18, + 138, + 4, // Opcode: VFP_VMAXNMH + /* 637 */ MCD_OPC_FilterValue, + 1, + 34, + 10, + 0, // Skip to: 3236 + /* 642 */ MCD_OPC_CheckPredicate, + 77, + 29, + 10, + 0, // Skip to: 3236 + /* 647 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 21, + 10, + 0, // Skip to: 3236 + /* 655 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 14, + 10, + 0, // Skip to: 3236 + /* 662 */ MCD_OPC_Decode, + 230, + 18, + 138, + 4, // Opcode: VFP_VMINNMH + /* 667 */ MCD_OPC_FilterValue, + 1, + 32, + 0, + 0, // Skip to: 704 + /* 672 */ MCD_OPC_CheckPredicate, + 77, + 255, + 9, + 0, // Skip to: 3236 + /* 677 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 247, + 9, + 0, // Skip to: 3236 + /* 685 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 240, + 9, + 0, // Skip to: 3236 + /* 692 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 233, + 9, + 0, // Skip to: 3236 + /* 699 */ MCD_OPC_Decode, + 226, + 26, + 138, + 4, // Opcode: VSELVSH + /* 704 */ MCD_OPC_FilterValue, + 2, + 32, + 0, + 0, // Skip to: 741 + /* 709 */ MCD_OPC_CheckPredicate, + 77, + 218, + 9, + 0, // Skip to: 3236 + /* 714 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 210, + 9, + 0, // Skip to: 3236 + /* 722 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 203, + 9, + 0, // Skip to: 3236 + /* 729 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 196, + 9, + 0, // Skip to: 3236 + /* 736 */ MCD_OPC_Decode, + 220, + 26, + 138, + 4, // Opcode: VSELGEH + /* 741 */ MCD_OPC_FilterValue, + 3, + 186, + 9, + 0, // Skip to: 3236 + /* 746 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 749 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 779 + /* 754 */ MCD_OPC_CheckPredicate, + 77, + 173, + 9, + 0, // Skip to: 3236 + /* 759 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 165, + 9, + 0, // Skip to: 3236 + /* 767 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 158, + 9, + 0, // Skip to: 3236 + /* 774 */ MCD_OPC_Decode, + 223, + 26, + 138, + 4, // Opcode: VSELGTH + /* 779 */ MCD_OPC_FilterValue, + 1, + 148, + 9, + 0, // Skip to: 3236 + /* 784 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 787 */ MCD_OPC_FilterValue, + 3, + 61, + 0, + 0, // Skip to: 853 + /* 792 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 795 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 824 + /* 800 */ MCD_OPC_CheckPredicate, + 94, + 127, + 9, + 0, // Skip to: 3236 + /* 805 */ MCD_OPC_CheckField, + 23, + 5, + 29, + 120, + 9, + 0, // Skip to: 3236 + /* 812 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 113, + 9, + 0, // Skip to: 3236 + /* 819 */ MCD_OPC_Decode, + 219, + 5, + 237, + 3, // Opcode: BF16_VCVTB + /* 824 */ MCD_OPC_FilterValue, + 1, + 103, + 9, + 0, // Skip to: 3236 + /* 829 */ MCD_OPC_CheckPredicate, + 94, + 98, + 9, + 0, // Skip to: 3236 + /* 834 */ MCD_OPC_CheckField, + 23, + 5, + 29, + 91, + 9, + 0, // Skip to: 3236 + /* 841 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 84, + 9, + 0, // Skip to: 3236 + /* 848 */ MCD_OPC_Decode, + 220, + 5, + 237, + 3, // Opcode: BF16_VCVTT + /* 853 */ MCD_OPC_FilterValue, + 8, + 32, + 0, + 0, // Skip to: 890 + /* 858 */ MCD_OPC_CheckPredicate, + 77, + 69, + 9, + 0, // Skip to: 3236 + /* 863 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 61, + 9, + 0, // Skip to: 3236 + /* 871 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 54, + 9, + 0, // Skip to: 3236 + /* 878 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 47, + 9, + 0, // Skip to: 3236 + /* 885 */ MCD_OPC_Decode, + 230, + 25, + 139, + 4, // Opcode: VRINTAH + /* 890 */ MCD_OPC_FilterValue, + 9, + 32, + 0, + 0, // Skip to: 927 + /* 895 */ MCD_OPC_CheckPredicate, + 77, + 32, + 9, + 0, // Skip to: 3236 + /* 900 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 24, + 9, + 0, // Skip to: 3236 + /* 908 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 17, + 9, + 0, // Skip to: 3236 + /* 915 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 10, + 9, + 0, // Skip to: 3236 + /* 922 */ MCD_OPC_Decode, + 244, + 25, + 139, + 4, // Opcode: VRINTNH + /* 927 */ MCD_OPC_FilterValue, + 10, + 32, + 0, + 0, // Skip to: 964 + /* 932 */ MCD_OPC_CheckPredicate, + 77, + 251, + 8, + 0, // Skip to: 3236 + /* 937 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 243, + 8, + 0, // Skip to: 3236 + /* 945 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 236, + 8, + 0, // Skip to: 3236 + /* 952 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 229, + 8, + 0, // Skip to: 3236 + /* 959 */ MCD_OPC_Decode, + 251, + 25, + 139, + 4, // Opcode: VRINTPH + /* 964 */ MCD_OPC_FilterValue, + 11, + 32, + 0, + 0, // Skip to: 1001 + /* 969 */ MCD_OPC_CheckPredicate, + 77, + 214, + 8, + 0, // Skip to: 3236 + /* 974 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 206, + 8, + 0, // Skip to: 3236 + /* 982 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 199, + 8, + 0, // Skip to: 3236 + /* 989 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 192, + 8, + 0, // Skip to: 3236 + /* 996 */ MCD_OPC_Decode, + 237, + 25, + 139, + 4, // Opcode: VRINTMH + /* 1001 */ MCD_OPC_FilterValue, + 12, + 63, + 0, + 0, // Skip to: 1069 + /* 1006 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1009 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1039 + /* 1014 */ MCD_OPC_CheckPredicate, + 77, + 169, + 8, + 0, // Skip to: 3236 + /* 1019 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 161, + 8, + 0, // Skip to: 3236 + /* 1027 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 154, + 8, + 0, // Skip to: 3236 + /* 1034 */ MCD_OPC_Decode, + 214, + 17, + 140, + 4, // Opcode: VCVTAUH + /* 1039 */ MCD_OPC_FilterValue, + 1, + 144, + 8, + 0, // Skip to: 3236 + /* 1044 */ MCD_OPC_CheckPredicate, + 77, + 139, + 8, + 0, // Skip to: 3236 + /* 1049 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 131, + 8, + 0, // Skip to: 3236 + /* 1057 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 124, + 8, + 0, // Skip to: 3236 + /* 1064 */ MCD_OPC_Decode, + 211, + 17, + 140, + 4, // Opcode: VCVTASH + /* 1069 */ MCD_OPC_FilterValue, + 13, + 63, + 0, + 0, // Skip to: 1137 + /* 1074 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1077 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1107 + /* 1082 */ MCD_OPC_CheckPredicate, + 77, + 101, + 8, + 0, // Skip to: 3236 + /* 1087 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 93, + 8, + 0, // Skip to: 3236 + /* 1095 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 86, + 8, + 0, // Skip to: 3236 + /* 1102 */ MCD_OPC_Decode, + 247, + 17, + 140, + 4, // Opcode: VCVTNUH + /* 1107 */ MCD_OPC_FilterValue, + 1, + 76, + 8, + 0, // Skip to: 3236 + /* 1112 */ MCD_OPC_CheckPredicate, + 77, + 71, + 8, + 0, // Skip to: 3236 + /* 1117 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 63, + 8, + 0, // Skip to: 3236 + /* 1125 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 56, + 8, + 0, // Skip to: 3236 + /* 1132 */ MCD_OPC_Decode, + 244, + 17, + 140, + 4, // Opcode: VCVTNSH + /* 1137 */ MCD_OPC_FilterValue, + 14, + 63, + 0, + 0, // Skip to: 1205 + /* 1142 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1145 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1175 + /* 1150 */ MCD_OPC_CheckPredicate, + 77, + 33, + 8, + 0, // Skip to: 3236 + /* 1155 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 25, + 8, + 0, // Skip to: 3236 + /* 1163 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 18, + 8, + 0, // Skip to: 3236 + /* 1170 */ MCD_OPC_Decode, + 133, + 18, + 140, + 4, // Opcode: VCVTPUH + /* 1175 */ MCD_OPC_FilterValue, + 1, + 8, + 8, + 0, // Skip to: 3236 + /* 1180 */ MCD_OPC_CheckPredicate, + 77, + 3, + 8, + 0, // Skip to: 3236 + /* 1185 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 251, + 7, + 0, // Skip to: 3236 + /* 1193 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 244, + 7, + 0, // Skip to: 3236 + /* 1200 */ MCD_OPC_Decode, + 130, + 18, + 140, + 4, // Opcode: VCVTPSH + /* 1205 */ MCD_OPC_FilterValue, + 15, + 234, + 7, + 0, // Skip to: 3236 + /* 1210 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1213 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1243 + /* 1218 */ MCD_OPC_CheckPredicate, + 77, + 221, + 7, + 0, // Skip to: 3236 + /* 1223 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 213, + 7, + 0, // Skip to: 3236 + /* 1231 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 206, + 7, + 0, // Skip to: 3236 + /* 1238 */ MCD_OPC_Decode, + 233, + 17, + 140, + 4, // Opcode: VCVTMUH + /* 1243 */ MCD_OPC_FilterValue, + 1, + 196, + 7, + 0, // Skip to: 3236 + /* 1248 */ MCD_OPC_CheckPredicate, + 77, + 191, + 7, + 0, // Skip to: 3236 + /* 1253 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 183, + 7, + 0, // Skip to: 3236 + /* 1261 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 176, + 7, + 0, // Skip to: 3236 + /* 1268 */ MCD_OPC_Decode, + 230, + 17, + 140, + 4, // Opcode: VCVTMSH + /* 1273 */ MCD_OPC_FilterValue, + 10, + 191, + 2, + 0, // Skip to: 1981 + /* 1278 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1281 */ MCD_OPC_FilterValue, + 0, + 87, + 0, + 0, // Skip to: 1373 + /* 1286 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1289 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 1343 + /* 1294 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1297 */ MCD_OPC_FilterValue, + 252, + 3, + 17, + 0, + 0, // Skip to: 1320 + /* 1303 */ MCD_OPC_CheckPredicate, + 84, + 136, + 7, + 0, // Skip to: 3236 + /* 1308 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 129, + 7, + 0, // Skip to: 3236 + /* 1315 */ MCD_OPC_Decode, + 218, + 26, + 141, + 4, // Opcode: VSELEQS + /* 1320 */ MCD_OPC_FilterValue, + 253, + 3, + 118, + 7, + 0, // Skip to: 3236 + /* 1326 */ MCD_OPC_CheckPredicate, + 84, + 113, + 7, + 0, // Skip to: 3236 + /* 1331 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 106, + 7, + 0, // Skip to: 3236 + /* 1338 */ MCD_OPC_Decode, + 228, + 18, + 141, + 4, // Opcode: VFP_VMAXNMS + /* 1343 */ MCD_OPC_FilterValue, + 1, + 96, + 7, + 0, // Skip to: 3236 + /* 1348 */ MCD_OPC_CheckPredicate, + 84, + 91, + 7, + 0, // Skip to: 3236 + /* 1353 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 83, + 7, + 0, // Skip to: 3236 + /* 1361 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 76, + 7, + 0, // Skip to: 3236 + /* 1368 */ MCD_OPC_Decode, + 231, + 18, + 141, + 4, // Opcode: VFP_VMINNMS + /* 1373 */ MCD_OPC_FilterValue, + 1, + 32, + 0, + 0, // Skip to: 1410 + /* 1378 */ MCD_OPC_CheckPredicate, + 84, + 61, + 7, + 0, // Skip to: 3236 + /* 1383 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 53, + 7, + 0, // Skip to: 3236 + /* 1391 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 46, + 7, + 0, // Skip to: 3236 + /* 1398 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 39, + 7, + 0, // Skip to: 3236 + /* 1405 */ MCD_OPC_Decode, + 227, + 26, + 141, + 4, // Opcode: VSELVSS + /* 1410 */ MCD_OPC_FilterValue, + 2, + 32, + 0, + 0, // Skip to: 1447 + /* 1415 */ MCD_OPC_CheckPredicate, + 84, + 24, + 7, + 0, // Skip to: 3236 + /* 1420 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 16, + 7, + 0, // Skip to: 3236 + /* 1428 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 9, + 7, + 0, // Skip to: 3236 + /* 1435 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 2, + 7, + 0, // Skip to: 3236 + /* 1442 */ MCD_OPC_Decode, + 221, + 26, + 141, + 4, // Opcode: VSELGES + /* 1447 */ MCD_OPC_FilterValue, + 3, + 248, + 6, + 0, // Skip to: 3236 + /* 1452 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1455 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1485 + /* 1460 */ MCD_OPC_CheckPredicate, + 84, + 235, + 6, + 0, // Skip to: 3236 + /* 1465 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 227, + 6, + 0, // Skip to: 3236 + /* 1473 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 220, + 6, + 0, // Skip to: 3236 + /* 1480 */ MCD_OPC_Decode, + 224, + 26, + 141, + 4, // Opcode: VSELGTS + /* 1485 */ MCD_OPC_FilterValue, + 1, + 210, + 6, + 0, // Skip to: 3236 + /* 1490 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 1493 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 1561 + /* 1498 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1501 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1531 + /* 1506 */ MCD_OPC_CheckPredicate, + 77, + 189, + 6, + 0, // Skip to: 3236 + /* 1511 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 181, + 6, + 0, // Skip to: 3236 + /* 1519 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 174, + 6, + 0, // Skip to: 3236 + /* 1526 */ MCD_OPC_Decode, + 238, + 22, + 142, + 4, // Opcode: VMOVH + /* 1531 */ MCD_OPC_FilterValue, + 1, + 164, + 6, + 0, // Skip to: 3236 + /* 1536 */ MCD_OPC_CheckPredicate, + 77, + 159, + 6, + 0, // Skip to: 3236 + /* 1541 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 151, + 6, + 0, // Skip to: 3236 + /* 1549 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 144, + 6, + 0, // Skip to: 3236 + /* 1556 */ MCD_OPC_Decode, + 133, + 19, + 143, + 4, // Opcode: VINSH + /* 1561 */ MCD_OPC_FilterValue, + 8, + 32, + 0, + 0, // Skip to: 1598 + /* 1566 */ MCD_OPC_CheckPredicate, + 84, + 129, + 6, + 0, // Skip to: 3236 + /* 1571 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 121, + 6, + 0, // Skip to: 3236 + /* 1579 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 114, + 6, + 0, // Skip to: 3236 + /* 1586 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 107, + 6, + 0, // Skip to: 3236 + /* 1593 */ MCD_OPC_Decode, + 235, + 25, + 142, + 4, // Opcode: VRINTAS + /* 1598 */ MCD_OPC_FilterValue, + 9, + 32, + 0, + 0, // Skip to: 1635 + /* 1603 */ MCD_OPC_CheckPredicate, + 84, + 92, + 6, + 0, // Skip to: 3236 + /* 1608 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 84, + 6, + 0, // Skip to: 3236 + /* 1616 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 77, + 6, + 0, // Skip to: 3236 + /* 1623 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 70, + 6, + 0, // Skip to: 3236 + /* 1630 */ MCD_OPC_Decode, + 249, + 25, + 142, + 4, // Opcode: VRINTNS + /* 1635 */ MCD_OPC_FilterValue, + 10, + 32, + 0, + 0, // Skip to: 1672 + /* 1640 */ MCD_OPC_CheckPredicate, + 84, + 55, + 6, + 0, // Skip to: 3236 + /* 1645 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 47, + 6, + 0, // Skip to: 3236 + /* 1653 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 40, + 6, + 0, // Skip to: 3236 + /* 1660 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 33, + 6, + 0, // Skip to: 3236 + /* 1667 */ MCD_OPC_Decode, + 128, + 26, + 142, + 4, // Opcode: VRINTPS + /* 1672 */ MCD_OPC_FilterValue, + 11, + 32, + 0, + 0, // Skip to: 1709 + /* 1677 */ MCD_OPC_CheckPredicate, + 84, + 18, + 6, + 0, // Skip to: 3236 + /* 1682 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 10, + 6, + 0, // Skip to: 3236 + /* 1690 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 3, + 6, + 0, // Skip to: 3236 + /* 1697 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 252, + 5, + 0, // Skip to: 3236 + /* 1704 */ MCD_OPC_Decode, + 242, + 25, + 142, + 4, // Opcode: VRINTMS + /* 1709 */ MCD_OPC_FilterValue, + 12, + 63, + 0, + 0, // Skip to: 1777 + /* 1714 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1717 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1747 + /* 1722 */ MCD_OPC_CheckPredicate, + 84, + 229, + 5, + 0, // Skip to: 3236 + /* 1727 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 221, + 5, + 0, // Skip to: 3236 + /* 1735 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 214, + 5, + 0, // Skip to: 3236 + /* 1742 */ MCD_OPC_Decode, + 215, + 17, + 142, + 4, // Opcode: VCVTAUS + /* 1747 */ MCD_OPC_FilterValue, + 1, + 204, + 5, + 0, // Skip to: 3236 + /* 1752 */ MCD_OPC_CheckPredicate, + 84, + 199, + 5, + 0, // Skip to: 3236 + /* 1757 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 191, + 5, + 0, // Skip to: 3236 + /* 1765 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 184, + 5, + 0, // Skip to: 3236 + /* 1772 */ MCD_OPC_Decode, + 212, + 17, + 142, + 4, // Opcode: VCVTASS + /* 1777 */ MCD_OPC_FilterValue, + 13, + 63, + 0, + 0, // Skip to: 1845 + /* 1782 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1785 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1815 + /* 1790 */ MCD_OPC_CheckPredicate, + 84, + 161, + 5, + 0, // Skip to: 3236 + /* 1795 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 153, + 5, + 0, // Skip to: 3236 + /* 1803 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 146, + 5, + 0, // Skip to: 3236 + /* 1810 */ MCD_OPC_Decode, + 248, + 17, + 142, + 4, // Opcode: VCVTNUS + /* 1815 */ MCD_OPC_FilterValue, + 1, + 136, + 5, + 0, // Skip to: 3236 + /* 1820 */ MCD_OPC_CheckPredicate, + 84, + 131, + 5, + 0, // Skip to: 3236 + /* 1825 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 123, + 5, + 0, // Skip to: 3236 + /* 1833 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 116, + 5, + 0, // Skip to: 3236 + /* 1840 */ MCD_OPC_Decode, + 245, + 17, + 142, + 4, // Opcode: VCVTNSS + /* 1845 */ MCD_OPC_FilterValue, + 14, + 63, + 0, + 0, // Skip to: 1913 + /* 1850 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1853 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1883 + /* 1858 */ MCD_OPC_CheckPredicate, + 84, + 93, + 5, + 0, // Skip to: 3236 + /* 1863 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 85, + 5, + 0, // Skip to: 3236 + /* 1871 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 78, + 5, + 0, // Skip to: 3236 + /* 1878 */ MCD_OPC_Decode, + 134, + 18, + 142, + 4, // Opcode: VCVTPUS + /* 1883 */ MCD_OPC_FilterValue, + 1, + 68, + 5, + 0, // Skip to: 3236 + /* 1888 */ MCD_OPC_CheckPredicate, + 84, + 63, + 5, + 0, // Skip to: 3236 + /* 1893 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 55, + 5, + 0, // Skip to: 3236 + /* 1901 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 48, + 5, + 0, // Skip to: 3236 + /* 1908 */ MCD_OPC_Decode, + 131, + 18, + 142, + 4, // Opcode: VCVTPSS + /* 1913 */ MCD_OPC_FilterValue, + 15, + 38, + 5, + 0, // Skip to: 3236 + /* 1918 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1921 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1951 + /* 1926 */ MCD_OPC_CheckPredicate, + 84, + 25, + 5, + 0, // Skip to: 3236 + /* 1931 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 17, + 5, + 0, // Skip to: 3236 + /* 1939 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 10, + 5, + 0, // Skip to: 3236 + /* 1946 */ MCD_OPC_Decode, + 234, + 17, + 142, + 4, // Opcode: VCVTMUS + /* 1951 */ MCD_OPC_FilterValue, + 1, + 0, + 5, + 0, // Skip to: 3236 + /* 1956 */ MCD_OPC_CheckPredicate, + 84, + 251, + 4, + 0, // Skip to: 3236 + /* 1961 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 243, + 4, + 0, // Skip to: 3236 + /* 1969 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 236, + 4, + 0, // Skip to: 3236 + /* 1976 */ MCD_OPC_Decode, + 231, + 17, + 142, + 4, // Opcode: VCVTMSS + /* 1981 */ MCD_OPC_FilterValue, + 11, + 123, + 2, + 0, // Skip to: 2621 + /* 1986 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1989 */ MCD_OPC_FilterValue, + 0, + 87, + 0, + 0, // Skip to: 2081 + /* 1994 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1997 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 2051 + /* 2002 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2005 */ MCD_OPC_FilterValue, + 252, + 3, + 17, + 0, + 0, // Skip to: 2028 + /* 2011 */ MCD_OPC_CheckPredicate, + 89, + 196, + 4, + 0, // Skip to: 3236 + /* 2016 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 189, + 4, + 0, // Skip to: 3236 + /* 2023 */ MCD_OPC_Decode, + 216, + 26, + 202, + 1, // Opcode: VSELEQD + /* 2028 */ MCD_OPC_FilterValue, + 253, + 3, + 178, + 4, + 0, // Skip to: 3236 + /* 2034 */ MCD_OPC_CheckPredicate, + 89, + 173, + 4, + 0, // Skip to: 3236 + /* 2039 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 166, + 4, + 0, // Skip to: 3236 + /* 2046 */ MCD_OPC_Decode, + 226, + 18, + 202, + 1, // Opcode: VFP_VMAXNMD + /* 2051 */ MCD_OPC_FilterValue, + 1, + 156, + 4, + 0, // Skip to: 3236 + /* 2056 */ MCD_OPC_CheckPredicate, + 89, + 151, + 4, + 0, // Skip to: 3236 + /* 2061 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 143, + 4, + 0, // Skip to: 3236 + /* 2069 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 136, + 4, + 0, // Skip to: 3236 + /* 2076 */ MCD_OPC_Decode, + 229, + 18, + 202, + 1, // Opcode: VFP_VMINNMD + /* 2081 */ MCD_OPC_FilterValue, + 1, + 32, + 0, + 0, // Skip to: 2118 + /* 2086 */ MCD_OPC_CheckPredicate, + 89, + 121, + 4, + 0, // Skip to: 3236 + /* 2091 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 113, + 4, + 0, // Skip to: 3236 + /* 2099 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 106, + 4, + 0, // Skip to: 3236 + /* 2106 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 99, + 4, + 0, // Skip to: 3236 + /* 2113 */ MCD_OPC_Decode, + 225, + 26, + 202, + 1, // Opcode: VSELVSD + /* 2118 */ MCD_OPC_FilterValue, + 2, + 32, + 0, + 0, // Skip to: 2155 + /* 2123 */ MCD_OPC_CheckPredicate, + 89, + 84, + 4, + 0, // Skip to: 3236 + /* 2128 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 76, + 4, + 0, // Skip to: 3236 + /* 2136 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 69, + 4, + 0, // Skip to: 3236 + /* 2143 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 62, + 4, + 0, // Skip to: 3236 + /* 2150 */ MCD_OPC_Decode, + 219, + 26, + 202, + 1, // Opcode: VSELGED + /* 2155 */ MCD_OPC_FilterValue, + 3, + 52, + 4, + 0, // Skip to: 3236 + /* 2160 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2163 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2193 + /* 2168 */ MCD_OPC_CheckPredicate, + 89, + 39, + 4, + 0, // Skip to: 3236 + /* 2173 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 31, + 4, + 0, // Skip to: 3236 + /* 2181 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 24, + 4, + 0, // Skip to: 3236 + /* 2188 */ MCD_OPC_Decode, + 222, + 26, + 202, + 1, // Opcode: VSELGTD + /* 2193 */ MCD_OPC_FilterValue, + 1, + 14, + 4, + 0, // Skip to: 3236 + /* 2198 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 2201 */ MCD_OPC_FilterValue, + 8, + 32, + 0, + 0, // Skip to: 2238 + /* 2206 */ MCD_OPC_CheckPredicate, + 89, + 1, + 4, + 0, // Skip to: 3236 + /* 2211 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 249, + 3, + 0, // Skip to: 3236 + /* 2219 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 242, + 3, + 0, // Skip to: 3236 + /* 2226 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 235, + 3, + 0, // Skip to: 3236 + /* 2233 */ MCD_OPC_Decode, + 229, + 25, + 231, + 1, // Opcode: VRINTAD + /* 2238 */ MCD_OPC_FilterValue, + 9, + 32, + 0, + 0, // Skip to: 2275 + /* 2243 */ MCD_OPC_CheckPredicate, + 89, + 220, + 3, + 0, // Skip to: 3236 + /* 2248 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 212, + 3, + 0, // Skip to: 3236 + /* 2256 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 205, + 3, + 0, // Skip to: 3236 + /* 2263 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 198, + 3, + 0, // Skip to: 3236 + /* 2270 */ MCD_OPC_Decode, + 243, + 25, + 231, + 1, // Opcode: VRINTND + /* 2275 */ MCD_OPC_FilterValue, + 10, + 32, + 0, + 0, // Skip to: 2312 + /* 2280 */ MCD_OPC_CheckPredicate, + 89, + 183, + 3, + 0, // Skip to: 3236 + /* 2285 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 175, + 3, + 0, // Skip to: 3236 + /* 2293 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 168, + 3, + 0, // Skip to: 3236 + /* 2300 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 161, + 3, + 0, // Skip to: 3236 + /* 2307 */ MCD_OPC_Decode, + 250, + 25, + 231, + 1, // Opcode: VRINTPD + /* 2312 */ MCD_OPC_FilterValue, + 11, + 32, + 0, + 0, // Skip to: 2349 + /* 2317 */ MCD_OPC_CheckPredicate, + 89, + 146, + 3, + 0, // Skip to: 3236 + /* 2322 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 138, + 3, + 0, // Skip to: 3236 + /* 2330 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 131, + 3, + 0, // Skip to: 3236 + /* 2337 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 124, + 3, + 0, // Skip to: 3236 + /* 2344 */ MCD_OPC_Decode, + 236, + 25, + 231, + 1, // Opcode: VRINTMD + /* 2349 */ MCD_OPC_FilterValue, + 12, + 63, + 0, + 0, // Skip to: 2417 + /* 2354 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 2357 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2387 + /* 2362 */ MCD_OPC_CheckPredicate, + 89, + 101, + 3, + 0, // Skip to: 3236 + /* 2367 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 93, + 3, + 0, // Skip to: 3236 + /* 2375 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 86, + 3, + 0, // Skip to: 3236 + /* 2382 */ MCD_OPC_Decode, + 213, + 17, + 144, + 4, // Opcode: VCVTAUD + /* 2387 */ MCD_OPC_FilterValue, + 1, + 76, + 3, + 0, // Skip to: 3236 + /* 2392 */ MCD_OPC_CheckPredicate, + 89, + 71, + 3, + 0, // Skip to: 3236 + /* 2397 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 63, + 3, + 0, // Skip to: 3236 + /* 2405 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 56, + 3, + 0, // Skip to: 3236 + /* 2412 */ MCD_OPC_Decode, + 210, + 17, + 144, + 4, // Opcode: VCVTASD + /* 2417 */ MCD_OPC_FilterValue, + 13, + 63, + 0, + 0, // Skip to: 2485 + /* 2422 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 2425 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2455 + /* 2430 */ MCD_OPC_CheckPredicate, + 89, + 33, + 3, + 0, // Skip to: 3236 + /* 2435 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 25, + 3, + 0, // Skip to: 3236 + /* 2443 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 18, + 3, + 0, // Skip to: 3236 + /* 2450 */ MCD_OPC_Decode, + 246, + 17, + 144, + 4, // Opcode: VCVTNUD + /* 2455 */ MCD_OPC_FilterValue, + 1, + 8, + 3, + 0, // Skip to: 3236 + /* 2460 */ MCD_OPC_CheckPredicate, + 89, + 3, + 3, + 0, // Skip to: 3236 + /* 2465 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 251, + 2, + 0, // Skip to: 3236 + /* 2473 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 244, + 2, + 0, // Skip to: 3236 + /* 2480 */ MCD_OPC_Decode, + 243, + 17, + 144, + 4, // Opcode: VCVTNSD + /* 2485 */ MCD_OPC_FilterValue, + 14, + 63, + 0, + 0, // Skip to: 2553 + /* 2490 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 2493 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2523 + /* 2498 */ MCD_OPC_CheckPredicate, + 89, + 221, + 2, + 0, // Skip to: 3236 + /* 2503 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 213, + 2, + 0, // Skip to: 3236 + /* 2511 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 206, + 2, + 0, // Skip to: 3236 + /* 2518 */ MCD_OPC_Decode, + 132, + 18, + 144, + 4, // Opcode: VCVTPUD + /* 2523 */ MCD_OPC_FilterValue, + 1, + 196, + 2, + 0, // Skip to: 3236 + /* 2528 */ MCD_OPC_CheckPredicate, + 89, + 191, + 2, + 0, // Skip to: 3236 + /* 2533 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 183, + 2, + 0, // Skip to: 3236 + /* 2541 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 176, + 2, + 0, // Skip to: 3236 + /* 2548 */ MCD_OPC_Decode, + 129, + 18, + 144, + 4, // Opcode: VCVTPSD + /* 2553 */ MCD_OPC_FilterValue, + 15, + 166, + 2, + 0, // Skip to: 3236 + /* 2558 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 2561 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2591 + /* 2566 */ MCD_OPC_CheckPredicate, + 89, + 153, + 2, + 0, // Skip to: 3236 + /* 2571 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 145, + 2, + 0, // Skip to: 3236 + /* 2579 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 138, + 2, + 0, // Skip to: 3236 + /* 2586 */ MCD_OPC_Decode, + 232, + 17, + 144, + 4, // Opcode: VCVTMUD + /* 2591 */ MCD_OPC_FilterValue, + 1, + 128, + 2, + 0, // Skip to: 3236 + /* 2596 */ MCD_OPC_CheckPredicate, + 89, + 123, + 2, + 0, // Skip to: 3236 + /* 2601 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 115, + 2, + 0, // Skip to: 3236 + /* 2609 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 108, + 2, + 0, // Skip to: 3236 + /* 2616 */ MCD_OPC_Decode, + 229, + 17, + 144, + 4, // Opcode: VCVTMSD + /* 2621 */ MCD_OPC_FilterValue, + 12, + 132, + 0, + 0, // Skip to: 2758 + /* 2626 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 2629 */ MCD_OPC_FilterValue, + 0, + 87, + 0, + 0, // Skip to: 2721 + /* 2634 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 2637 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2667 + /* 2642 */ MCD_OPC_CheckPredicate, + 31, + 77, + 2, + 0, // Skip to: 3236 + /* 2647 */ MCD_OPC_CheckField, + 23, + 9, + 248, + 3, + 69, + 2, + 0, // Skip to: 3236 + /* 2655 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 62, + 2, + 0, // Skip to: 3236 + /* 2662 */ MCD_OPC_Decode, + 235, + 22, + 211, + 1, // Opcode: VMMLA + /* 2667 */ MCD_OPC_FilterValue, + 2, + 52, + 2, + 0, // Skip to: 3236 + /* 2672 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2675 */ MCD_OPC_FilterValue, + 248, + 3, + 17, + 0, + 0, // Skip to: 2698 + /* 2681 */ MCD_OPC_CheckPredicate, + 95, + 38, + 2, + 0, // Skip to: 3236 + /* 2686 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 31, + 2, + 0, // Skip to: 3236 + /* 2693 */ MCD_OPC_Decode, + 172, + 27, + 211, + 1, // Opcode: VSMMLA + /* 2698 */ MCD_OPC_FilterValue, + 249, + 3, + 20, + 2, + 0, // Skip to: 3236 + /* 2704 */ MCD_OPC_CheckPredicate, + 95, + 15, + 2, + 0, // Skip to: 3236 + /* 2709 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 8, + 2, + 0, // Skip to: 3236 + /* 2716 */ MCD_OPC_Decode, + 202, + 30, + 211, + 1, // Opcode: VUSMMLA + /* 2721 */ MCD_OPC_FilterValue, + 1, + 254, + 1, + 0, // Skip to: 3236 + /* 2726 */ MCD_OPC_CheckPredicate, + 95, + 249, + 1, + 0, // Skip to: 3236 + /* 2731 */ MCD_OPC_CheckField, + 23, + 9, + 248, + 3, + 241, + 1, + 0, // Skip to: 3236 + /* 2739 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 234, + 1, + 0, // Skip to: 3236 + /* 2746 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 227, + 1, + 0, // Skip to: 3236 + /* 2753 */ MCD_OPC_Decode, + 197, + 30, + 211, + 1, // Opcode: VUMMLA + /* 2758 */ MCD_OPC_FilterValue, + 13, + 217, + 1, + 0, // Skip to: 3236 + /* 2763 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2766 */ MCD_OPC_FilterValue, + 248, + 3, + 139, + 0, + 0, // Skip to: 2911 + /* 2772 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 2775 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 2859 + /* 2780 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2783 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 2821 + /* 2788 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 2791 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2806 + /* 2796 */ MCD_OPC_CheckPredicate, + 31, + 179, + 1, + 0, // Skip to: 3236 + /* 2801 */ MCD_OPC_Decode, + 216, + 5, + 210, + 1, // Opcode: BF16VDOTS_VDOTD + /* 2806 */ MCD_OPC_FilterValue, + 2, + 169, + 1, + 0, // Skip to: 3236 + /* 2811 */ MCD_OPC_CheckPredicate, + 96, + 164, + 1, + 0, // Skip to: 3236 + /* 2816 */ MCD_OPC_Decode, + 212, + 26, + 210, + 1, // Opcode: VSDOTD + /* 2821 */ MCD_OPC_FilterValue, + 1, + 154, + 1, + 0, // Skip to: 3236 + /* 2826 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 2829 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2844 + /* 2834 */ MCD_OPC_CheckPredicate, + 31, + 141, + 1, + 0, // Skip to: 3236 + /* 2839 */ MCD_OPC_Decode, + 217, + 5, + 211, + 1, // Opcode: BF16VDOTS_VDOTQ + /* 2844 */ MCD_OPC_FilterValue, + 2, + 131, + 1, + 0, // Skip to: 3236 + /* 2849 */ MCD_OPC_CheckPredicate, + 96, + 126, + 1, + 0, // Skip to: 3236 + /* 2854 */ MCD_OPC_Decode, + 214, + 26, + 211, + 1, // Opcode: VSDOTQ + /* 2859 */ MCD_OPC_FilterValue, + 1, + 116, + 1, + 0, // Skip to: 3236 + /* 2864 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2867 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2889 + /* 2872 */ MCD_OPC_CheckPredicate, + 96, + 103, + 1, + 0, // Skip to: 3236 + /* 2877 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 96, + 1, + 0, // Skip to: 3236 + /* 2884 */ MCD_OPC_Decode, + 184, + 30, + 210, + 1, // Opcode: VUDOTD + /* 2889 */ MCD_OPC_FilterValue, + 1, + 86, + 1, + 0, // Skip to: 3236 + /* 2894 */ MCD_OPC_CheckPredicate, + 96, + 81, + 1, + 0, // Skip to: 3236 + /* 2899 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 74, + 1, + 0, // Skip to: 3236 + /* 2906 */ MCD_OPC_Decode, + 186, + 30, + 211, + 1, // Opcode: VUDOTQ + /* 2911 */ MCD_OPC_FilterValue, + 249, + 3, + 61, + 0, + 0, // Skip to: 2978 + /* 2917 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2920 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 2949 + /* 2925 */ MCD_OPC_CheckPredicate, + 95, + 50, + 1, + 0, // Skip to: 3236 + /* 2930 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 43, + 1, + 0, // Skip to: 3236 + /* 2937 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 36, + 1, + 0, // Skip to: 3236 + /* 2944 */ MCD_OPC_Decode, + 198, + 30, + 210, + 1, // Opcode: VUSDOTD + /* 2949 */ MCD_OPC_FilterValue, + 1, + 26, + 1, + 0, // Skip to: 3236 + /* 2954 */ MCD_OPC_CheckPredicate, + 95, + 21, + 1, + 0, // Skip to: 3236 + /* 2959 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 14, + 1, + 0, // Skip to: 3236 + /* 2966 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 7, + 1, + 0, // Skip to: 3236 + /* 2973 */ MCD_OPC_Decode, + 200, + 30, + 211, + 1, // Opcode: VUSDOTQ + /* 2978 */ MCD_OPC_FilterValue, + 252, + 3, + 139, + 0, + 0, // Skip to: 3123 + /* 2984 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 2987 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 3071 + /* 2992 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2995 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 3033 + /* 3000 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3003 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3018 + /* 3008 */ MCD_OPC_CheckPredicate, + 31, + 223, + 0, + 0, // Skip to: 3236 + /* 3013 */ MCD_OPC_Decode, + 214, + 5, + 218, + 1, // Opcode: BF16VDOTI_VDOTD + /* 3018 */ MCD_OPC_FilterValue, + 2, + 213, + 0, + 0, // Skip to: 3236 + /* 3023 */ MCD_OPC_CheckPredicate, + 96, + 208, + 0, + 0, // Skip to: 3236 + /* 3028 */ MCD_OPC_Decode, + 213, + 26, + 218, + 1, // Opcode: VSDOTDI + /* 3033 */ MCD_OPC_FilterValue, + 1, + 198, + 0, + 0, // Skip to: 3236 + /* 3038 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3041 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3056 + /* 3046 */ MCD_OPC_CheckPredicate, + 31, + 185, + 0, + 0, // Skip to: 3236 + /* 3051 */ MCD_OPC_Decode, + 215, + 5, + 219, + 1, // Opcode: BF16VDOTI_VDOTQ + /* 3056 */ MCD_OPC_FilterValue, + 2, + 175, + 0, + 0, // Skip to: 3236 + /* 3061 */ MCD_OPC_CheckPredicate, + 96, + 170, + 0, + 0, // Skip to: 3236 + /* 3066 */ MCD_OPC_Decode, + 215, + 26, + 219, + 1, // Opcode: VSDOTQI + /* 3071 */ MCD_OPC_FilterValue, + 1, + 160, + 0, + 0, // Skip to: 3236 + /* 3076 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3079 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3101 + /* 3084 */ MCD_OPC_CheckPredicate, + 96, + 147, + 0, + 0, // Skip to: 3236 + /* 3089 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 140, + 0, + 0, // Skip to: 3236 + /* 3096 */ MCD_OPC_Decode, + 185, + 30, + 218, + 1, // Opcode: VUDOTDI + /* 3101 */ MCD_OPC_FilterValue, + 1, + 130, + 0, + 0, // Skip to: 3236 + /* 3106 */ MCD_OPC_CheckPredicate, + 96, + 125, + 0, + 0, // Skip to: 3236 + /* 3111 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 118, + 0, + 0, // Skip to: 3236 + /* 3118 */ MCD_OPC_Decode, + 187, + 30, + 219, + 1, // Opcode: VUDOTQI + /* 3123 */ MCD_OPC_FilterValue, + 253, + 3, + 107, + 0, + 0, // Skip to: 3236 + /* 3129 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 3132 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 3184 + /* 3137 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3140 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3162 + /* 3145 */ MCD_OPC_CheckPredicate, + 95, + 86, + 0, + 0, // Skip to: 3236 + /* 3150 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 79, + 0, + 0, // Skip to: 3236 + /* 3157 */ MCD_OPC_Decode, + 199, + 30, + 218, + 1, // Opcode: VUSDOTDI + /* 3162 */ MCD_OPC_FilterValue, + 1, + 69, + 0, + 0, // Skip to: 3236 + /* 3167 */ MCD_OPC_CheckPredicate, + 95, + 64, + 0, + 0, // Skip to: 3236 + /* 3172 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 57, + 0, + 0, // Skip to: 3236 + /* 3179 */ MCD_OPC_Decode, + 201, + 30, + 219, + 1, // Opcode: VUSDOTQI + /* 3184 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 3236 + /* 3189 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3192 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3214 + /* 3197 */ MCD_OPC_CheckPredicate, + 95, + 34, + 0, + 0, // Skip to: 3236 + /* 3202 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 27, + 0, + 0, // Skip to: 3236 + /* 3209 */ MCD_OPC_Decode, + 132, + 30, + 218, + 1, // Opcode: VSUDOTDI + /* 3214 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 3236 + /* 3219 */ MCD_OPC_CheckPredicate, + 95, + 12, + 0, + 0, // Skip to: 3236 + /* 3224 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 5, + 0, + 0, // Skip to: 3236 + /* 3231 */ MCD_OPC_Decode, + 133, + 30, + 219, + 1, // Opcode: VSUDOTQI + /* 3236 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTablev8Crypto32[] = { + /* 0 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 77, + 0, + 0, // Skip to: 85 + /* 8 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 11 */ MCD_OPC_FilterValue, + 228, + 3, + 31, + 0, + 0, // Skip to: 48 + /* 17 */ MCD_OPC_CheckPredicate, + 97, + 22, + 2, + 0, // Skip to: 556 + /* 22 */ MCD_OPC_CheckField, + 8, + 4, + 12, + 15, + 2, + 0, // Skip to: 556 + /* 29 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 8, + 2, + 0, // Skip to: 556 + /* 36 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 1, + 2, + 0, // Skip to: 556 + /* 43 */ MCD_OPC_Decode, + 162, + 14, + 211, + 1, // Opcode: SHA1C + /* 48 */ MCD_OPC_FilterValue, + 230, + 3, + 246, + 1, + 0, // Skip to: 556 + /* 54 */ MCD_OPC_CheckPredicate, + 97, + 241, + 1, + 0, // Skip to: 556 + /* 59 */ MCD_OPC_CheckField, + 8, + 4, + 12, + 234, + 1, + 0, // Skip to: 556 + /* 66 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 227, + 1, + 0, // Skip to: 556 + /* 73 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 220, + 1, + 0, // Skip to: 556 + /* 80 */ MCD_OPC_Decode, + 168, + 14, + 211, + 1, // Opcode: SHA256H + /* 85 */ MCD_OPC_FilterValue, + 1, + 77, + 0, + 0, // Skip to: 167 + /* 90 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 93 */ MCD_OPC_FilterValue, + 228, + 3, + 31, + 0, + 0, // Skip to: 130 + /* 99 */ MCD_OPC_CheckPredicate, + 97, + 196, + 1, + 0, // Skip to: 556 + /* 104 */ MCD_OPC_CheckField, + 8, + 4, + 12, + 189, + 1, + 0, // Skip to: 556 + /* 111 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 182, + 1, + 0, // Skip to: 556 + /* 118 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 175, + 1, + 0, // Skip to: 556 + /* 125 */ MCD_OPC_Decode, + 165, + 14, + 211, + 1, // Opcode: SHA1P + /* 130 */ MCD_OPC_FilterValue, + 230, + 3, + 164, + 1, + 0, // Skip to: 556 + /* 136 */ MCD_OPC_CheckPredicate, + 97, + 159, + 1, + 0, // Skip to: 556 + /* 141 */ MCD_OPC_CheckField, + 8, + 4, + 12, + 152, + 1, + 0, // Skip to: 556 + /* 148 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 145, + 1, + 0, // Skip to: 556 + /* 155 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 138, + 1, + 0, // Skip to: 556 + /* 162 */ MCD_OPC_Decode, + 169, + 14, + 211, + 1, // Opcode: SHA256H2 + /* 167 */ MCD_OPC_FilterValue, + 2, + 77, + 0, + 0, // Skip to: 249 + /* 172 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 175 */ MCD_OPC_FilterValue, + 228, + 3, + 31, + 0, + 0, // Skip to: 212 + /* 181 */ MCD_OPC_CheckPredicate, + 97, + 114, + 1, + 0, // Skip to: 556 + /* 186 */ MCD_OPC_CheckField, + 8, + 4, + 12, + 107, + 1, + 0, // Skip to: 556 + /* 193 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 100, + 1, + 0, // Skip to: 556 + /* 200 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 93, + 1, + 0, // Skip to: 556 + /* 207 */ MCD_OPC_Decode, + 164, + 14, + 211, + 1, // Opcode: SHA1M + /* 212 */ MCD_OPC_FilterValue, + 230, + 3, + 82, + 1, + 0, // Skip to: 556 + /* 218 */ MCD_OPC_CheckPredicate, + 97, + 77, + 1, + 0, // Skip to: 556 + /* 223 */ MCD_OPC_CheckField, + 8, + 4, + 12, + 70, + 1, + 0, // Skip to: 556 + /* 230 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 63, + 1, + 0, // Skip to: 556 + /* 237 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 56, + 1, + 0, // Skip to: 556 + /* 244 */ MCD_OPC_Decode, + 171, + 14, + 211, + 1, // Opcode: SHA256SU1 + /* 249 */ MCD_OPC_FilterValue, + 3, + 46, + 1, + 0, // Skip to: 556 + /* 254 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 257 */ MCD_OPC_FilterValue, + 2, + 39, + 0, + 0, // Skip to: 301 + /* 262 */ MCD_OPC_CheckPredicate, + 97, + 33, + 1, + 0, // Skip to: 556 + /* 267 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 25, + 1, + 0, // Skip to: 556 + /* 275 */ MCD_OPC_CheckField, + 16, + 4, + 9, + 18, + 1, + 0, // Skip to: 556 + /* 282 */ MCD_OPC_CheckField, + 6, + 2, + 3, + 11, + 1, + 0, // Skip to: 556 + /* 289 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 4, + 1, + 0, // Skip to: 556 + /* 296 */ MCD_OPC_Decode, + 163, + 14, + 232, + 1, // Opcode: SHA1H + /* 301 */ MCD_OPC_FilterValue, + 3, + 213, + 0, + 0, // Skip to: 519 + /* 306 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 309 */ MCD_OPC_FilterValue, + 0, + 32, + 0, + 0, // Skip to: 346 + /* 314 */ MCD_OPC_CheckPredicate, + 29, + 237, + 0, + 0, // Skip to: 556 + /* 319 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 229, + 0, + 0, // Skip to: 556 + /* 327 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 222, + 0, + 0, // Skip to: 556 + /* 334 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 215, + 0, + 0, // Skip to: 556 + /* 341 */ MCD_OPC_Decode, + 207, + 5, + 238, + 1, // Opcode: AESE + /* 346 */ MCD_OPC_FilterValue, + 1, + 32, + 0, + 0, // Skip to: 383 + /* 351 */ MCD_OPC_CheckPredicate, + 29, + 200, + 0, + 0, // Skip to: 556 + /* 356 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 192, + 0, + 0, // Skip to: 556 + /* 364 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 185, + 0, + 0, // Skip to: 556 + /* 371 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 178, + 0, + 0, // Skip to: 556 + /* 378 */ MCD_OPC_Decode, + 206, + 5, + 238, + 1, // Opcode: AESD + /* 383 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 451 + /* 388 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 391 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 421 + /* 396 */ MCD_OPC_CheckPredicate, + 29, + 155, + 0, + 0, // Skip to: 556 + /* 401 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 147, + 0, + 0, // Skip to: 556 + /* 409 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 140, + 0, + 0, // Skip to: 556 + /* 416 */ MCD_OPC_Decode, + 209, + 5, + 232, + 1, // Opcode: AESMC + /* 421 */ MCD_OPC_FilterValue, + 10, + 130, + 0, + 0, // Skip to: 556 + /* 426 */ MCD_OPC_CheckPredicate, + 97, + 125, + 0, + 0, // Skip to: 556 + /* 431 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 117, + 0, + 0, // Skip to: 556 + /* 439 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 110, + 0, + 0, // Skip to: 556 + /* 446 */ MCD_OPC_Decode, + 167, + 14, + 238, + 1, // Opcode: SHA1SU1 + /* 451 */ MCD_OPC_FilterValue, + 3, + 100, + 0, + 0, // Skip to: 556 + /* 456 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 459 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 489 + /* 464 */ MCD_OPC_CheckPredicate, + 29, + 87, + 0, + 0, // Skip to: 556 + /* 469 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 79, + 0, + 0, // Skip to: 556 + /* 477 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 72, + 0, + 0, // Skip to: 556 + /* 484 */ MCD_OPC_Decode, + 208, + 5, + 232, + 1, // Opcode: AESIMC + /* 489 */ MCD_OPC_FilterValue, + 10, + 62, + 0, + 0, // Skip to: 556 + /* 494 */ MCD_OPC_CheckPredicate, + 97, + 57, + 0, + 0, // Skip to: 556 + /* 499 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 49, + 0, + 0, // Skip to: 556 + /* 507 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 42, + 0, + 0, // Skip to: 556 + /* 514 */ MCD_OPC_Decode, + 170, + 14, + 238, + 1, // Opcode: SHA256SU0 + /* 519 */ MCD_OPC_FilterValue, + 12, + 32, + 0, + 0, // Skip to: 556 + /* 524 */ MCD_OPC_CheckPredicate, + 97, + 27, + 0, + 0, // Skip to: 556 + /* 529 */ MCD_OPC_CheckField, + 23, + 9, + 228, + 3, + 19, + 0, + 0, // Skip to: 556 + /* 537 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 12, + 0, + 0, // Skip to: 556 + /* 544 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 5, + 0, + 0, // Skip to: 556 + /* 551 */ MCD_OPC_Decode, + 166, + 14, + 211, + 1, // Opcode: SHA1SU0 + /* 556 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTablev8NEON32[] = { + /* 0 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 19, + 1, + 0, // Skip to: 283 + /* 8 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 79 + /* 16 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 19 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 49 + /* 24 */ MCD_OPC_CheckPredicate, + 98, + 174, + 8, + 0, // Skip to: 2251 + /* 29 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 166, + 8, + 0, // Skip to: 2251 + /* 37 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 159, + 8, + 0, // Skip to: 2251 + /* 44 */ MCD_OPC_Decode, + 203, + 17, + 231, + 1, // Opcode: VCVTANSDh + /* 49 */ MCD_OPC_FilterValue, + 59, + 149, + 8, + 0, // Skip to: 2251 + /* 54 */ MCD_OPC_CheckPredicate, + 99, + 144, + 8, + 0, // Skip to: 2251 + /* 59 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 136, + 8, + 0, // Skip to: 2251 + /* 67 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 129, + 8, + 0, // Skip to: 2251 + /* 74 */ MCD_OPC_Decode, + 202, + 17, + 231, + 1, // Opcode: VCVTANSDf + /* 79 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 147 + /* 84 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 87 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 117 + /* 92 */ MCD_OPC_CheckPredicate, + 98, + 106, + 8, + 0, // Skip to: 2251 + /* 97 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 98, + 8, + 0, // Skip to: 2251 + /* 105 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 91, + 8, + 0, // Skip to: 2251 + /* 112 */ MCD_OPC_Decode, + 205, + 17, + 232, + 1, // Opcode: VCVTANSQh + /* 117 */ MCD_OPC_FilterValue, + 59, + 81, + 8, + 0, // Skip to: 2251 + /* 122 */ MCD_OPC_CheckPredicate, + 99, + 76, + 8, + 0, // Skip to: 2251 + /* 127 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 68, + 8, + 0, // Skip to: 2251 + /* 135 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 61, + 8, + 0, // Skip to: 2251 + /* 142 */ MCD_OPC_Decode, + 204, + 17, + 232, + 1, // Opcode: VCVTANSQf + /* 147 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 215 + /* 152 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 155 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 185 + /* 160 */ MCD_OPC_CheckPredicate, + 98, + 38, + 8, + 0, // Skip to: 2251 + /* 165 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 30, + 8, + 0, // Skip to: 2251 + /* 173 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 23, + 8, + 0, // Skip to: 2251 + /* 180 */ MCD_OPC_Decode, + 207, + 17, + 231, + 1, // Opcode: VCVTANUDh + /* 185 */ MCD_OPC_FilterValue, + 59, + 13, + 8, + 0, // Skip to: 2251 + /* 190 */ MCD_OPC_CheckPredicate, + 99, + 8, + 8, + 0, // Skip to: 2251 + /* 195 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 0, + 8, + 0, // Skip to: 2251 + /* 203 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 249, + 7, + 0, // Skip to: 2251 + /* 210 */ MCD_OPC_Decode, + 206, + 17, + 231, + 1, // Opcode: VCVTANUDf + /* 215 */ MCD_OPC_FilterValue, + 3, + 239, + 7, + 0, // Skip to: 2251 + /* 220 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 223 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 253 + /* 228 */ MCD_OPC_CheckPredicate, + 98, + 226, + 7, + 0, // Skip to: 2251 + /* 233 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 218, + 7, + 0, // Skip to: 2251 + /* 241 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 211, + 7, + 0, // Skip to: 2251 + /* 248 */ MCD_OPC_Decode, + 209, + 17, + 232, + 1, // Opcode: VCVTANUQh + /* 253 */ MCD_OPC_FilterValue, + 59, + 201, + 7, + 0, // Skip to: 2251 + /* 258 */ MCD_OPC_CheckPredicate, + 99, + 196, + 7, + 0, // Skip to: 2251 + /* 263 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 188, + 7, + 0, // Skip to: 2251 + /* 271 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 181, + 7, + 0, // Skip to: 2251 + /* 278 */ MCD_OPC_Decode, + 208, + 17, + 232, + 1, // Opcode: VCVTANUQf + /* 283 */ MCD_OPC_FilterValue, + 1, + 19, + 1, + 0, // Skip to: 563 + /* 288 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 291 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 359 + /* 296 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 299 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 329 + /* 304 */ MCD_OPC_CheckPredicate, + 98, + 150, + 7, + 0, // Skip to: 2251 + /* 309 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 142, + 7, + 0, // Skip to: 2251 + /* 317 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 135, + 7, + 0, // Skip to: 2251 + /* 324 */ MCD_OPC_Decode, + 236, + 17, + 231, + 1, // Opcode: VCVTNNSDh + /* 329 */ MCD_OPC_FilterValue, + 59, + 125, + 7, + 0, // Skip to: 2251 + /* 334 */ MCD_OPC_CheckPredicate, + 99, + 120, + 7, + 0, // Skip to: 2251 + /* 339 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 112, + 7, + 0, // Skip to: 2251 + /* 347 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 105, + 7, + 0, // Skip to: 2251 + /* 354 */ MCD_OPC_Decode, + 235, + 17, + 231, + 1, // Opcode: VCVTNNSDf + /* 359 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 427 + /* 364 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 367 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 397 + /* 372 */ MCD_OPC_CheckPredicate, + 98, + 82, + 7, + 0, // Skip to: 2251 + /* 377 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 74, + 7, + 0, // Skip to: 2251 + /* 385 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 67, + 7, + 0, // Skip to: 2251 + /* 392 */ MCD_OPC_Decode, + 238, + 17, + 232, + 1, // Opcode: VCVTNNSQh + /* 397 */ MCD_OPC_FilterValue, + 59, + 57, + 7, + 0, // Skip to: 2251 + /* 402 */ MCD_OPC_CheckPredicate, + 99, + 52, + 7, + 0, // Skip to: 2251 + /* 407 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 44, + 7, + 0, // Skip to: 2251 + /* 415 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 37, + 7, + 0, // Skip to: 2251 + /* 422 */ MCD_OPC_Decode, + 237, + 17, + 232, + 1, // Opcode: VCVTNNSQf + /* 427 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 495 + /* 432 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 435 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 465 + /* 440 */ MCD_OPC_CheckPredicate, + 98, + 14, + 7, + 0, // Skip to: 2251 + /* 445 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 6, + 7, + 0, // Skip to: 2251 + /* 453 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 255, + 6, + 0, // Skip to: 2251 + /* 460 */ MCD_OPC_Decode, + 240, + 17, + 231, + 1, // Opcode: VCVTNNUDh + /* 465 */ MCD_OPC_FilterValue, + 59, + 245, + 6, + 0, // Skip to: 2251 + /* 470 */ MCD_OPC_CheckPredicate, + 99, + 240, + 6, + 0, // Skip to: 2251 + /* 475 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 232, + 6, + 0, // Skip to: 2251 + /* 483 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 225, + 6, + 0, // Skip to: 2251 + /* 490 */ MCD_OPC_Decode, + 239, + 17, + 231, + 1, // Opcode: VCVTNNUDf + /* 495 */ MCD_OPC_FilterValue, + 3, + 215, + 6, + 0, // Skip to: 2251 + /* 500 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 503 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 533 + /* 508 */ MCD_OPC_CheckPredicate, + 98, + 202, + 6, + 0, // Skip to: 2251 + /* 513 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 194, + 6, + 0, // Skip to: 2251 + /* 521 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 187, + 6, + 0, // Skip to: 2251 + /* 528 */ MCD_OPC_Decode, + 242, + 17, + 232, + 1, // Opcode: VCVTNNUQh + /* 533 */ MCD_OPC_FilterValue, + 59, + 177, + 6, + 0, // Skip to: 2251 + /* 538 */ MCD_OPC_CheckPredicate, + 99, + 172, + 6, + 0, // Skip to: 2251 + /* 543 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 164, + 6, + 0, // Skip to: 2251 + /* 551 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 157, + 6, + 0, // Skip to: 2251 + /* 558 */ MCD_OPC_Decode, + 241, + 17, + 232, + 1, // Opcode: VCVTNNUQf + /* 563 */ MCD_OPC_FilterValue, + 2, + 19, + 1, + 0, // Skip to: 843 + /* 568 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 571 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 639 + /* 576 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 579 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 609 + /* 584 */ MCD_OPC_CheckPredicate, + 98, + 126, + 6, + 0, // Skip to: 2251 + /* 589 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 118, + 6, + 0, // Skip to: 2251 + /* 597 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 111, + 6, + 0, // Skip to: 2251 + /* 604 */ MCD_OPC_Decode, + 250, + 17, + 231, + 1, // Opcode: VCVTPNSDh + /* 609 */ MCD_OPC_FilterValue, + 59, + 101, + 6, + 0, // Skip to: 2251 + /* 614 */ MCD_OPC_CheckPredicate, + 99, + 96, + 6, + 0, // Skip to: 2251 + /* 619 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 88, + 6, + 0, // Skip to: 2251 + /* 627 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 81, + 6, + 0, // Skip to: 2251 + /* 634 */ MCD_OPC_Decode, + 249, + 17, + 231, + 1, // Opcode: VCVTPNSDf + /* 639 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 707 + /* 644 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 647 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 677 + /* 652 */ MCD_OPC_CheckPredicate, + 98, + 58, + 6, + 0, // Skip to: 2251 + /* 657 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 50, + 6, + 0, // Skip to: 2251 + /* 665 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 43, + 6, + 0, // Skip to: 2251 + /* 672 */ MCD_OPC_Decode, + 252, + 17, + 232, + 1, // Opcode: VCVTPNSQh + /* 677 */ MCD_OPC_FilterValue, + 59, + 33, + 6, + 0, // Skip to: 2251 + /* 682 */ MCD_OPC_CheckPredicate, + 99, + 28, + 6, + 0, // Skip to: 2251 + /* 687 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 20, + 6, + 0, // Skip to: 2251 + /* 695 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 13, + 6, + 0, // Skip to: 2251 + /* 702 */ MCD_OPC_Decode, + 251, + 17, + 232, + 1, // Opcode: VCVTPNSQf + /* 707 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 775 + /* 712 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 715 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 745 + /* 720 */ MCD_OPC_CheckPredicate, + 98, + 246, + 5, + 0, // Skip to: 2251 + /* 725 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 238, + 5, + 0, // Skip to: 2251 + /* 733 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 231, + 5, + 0, // Skip to: 2251 + /* 740 */ MCD_OPC_Decode, + 254, + 17, + 231, + 1, // Opcode: VCVTPNUDh + /* 745 */ MCD_OPC_FilterValue, + 59, + 221, + 5, + 0, // Skip to: 2251 + /* 750 */ MCD_OPC_CheckPredicate, + 99, + 216, + 5, + 0, // Skip to: 2251 + /* 755 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 208, + 5, + 0, // Skip to: 2251 + /* 763 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 201, + 5, + 0, // Skip to: 2251 + /* 770 */ MCD_OPC_Decode, + 253, + 17, + 231, + 1, // Opcode: VCVTPNUDf + /* 775 */ MCD_OPC_FilterValue, + 3, + 191, + 5, + 0, // Skip to: 2251 + /* 780 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 783 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 813 + /* 788 */ MCD_OPC_CheckPredicate, + 98, + 178, + 5, + 0, // Skip to: 2251 + /* 793 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 170, + 5, + 0, // Skip to: 2251 + /* 801 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 163, + 5, + 0, // Skip to: 2251 + /* 808 */ MCD_OPC_Decode, + 128, + 18, + 232, + 1, // Opcode: VCVTPNUQh + /* 813 */ MCD_OPC_FilterValue, + 59, + 153, + 5, + 0, // Skip to: 2251 + /* 818 */ MCD_OPC_CheckPredicate, + 99, + 148, + 5, + 0, // Skip to: 2251 + /* 823 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 140, + 5, + 0, // Skip to: 2251 + /* 831 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 133, + 5, + 0, // Skip to: 2251 + /* 838 */ MCD_OPC_Decode, + 255, + 17, + 232, + 1, // Opcode: VCVTPNUQf + /* 843 */ MCD_OPC_FilterValue, + 3, + 19, + 1, + 0, // Skip to: 1123 + /* 848 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 851 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 919 + /* 856 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 859 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 889 + /* 864 */ MCD_OPC_CheckPredicate, + 98, + 102, + 5, + 0, // Skip to: 2251 + /* 869 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 94, + 5, + 0, // Skip to: 2251 + /* 877 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 87, + 5, + 0, // Skip to: 2251 + /* 884 */ MCD_OPC_Decode, + 222, + 17, + 231, + 1, // Opcode: VCVTMNSDh + /* 889 */ MCD_OPC_FilterValue, + 59, + 77, + 5, + 0, // Skip to: 2251 + /* 894 */ MCD_OPC_CheckPredicate, + 99, + 72, + 5, + 0, // Skip to: 2251 + /* 899 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 64, + 5, + 0, // Skip to: 2251 + /* 907 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 57, + 5, + 0, // Skip to: 2251 + /* 914 */ MCD_OPC_Decode, + 221, + 17, + 231, + 1, // Opcode: VCVTMNSDf + /* 919 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 987 + /* 924 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 927 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 957 + /* 932 */ MCD_OPC_CheckPredicate, + 98, + 34, + 5, + 0, // Skip to: 2251 + /* 937 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 26, + 5, + 0, // Skip to: 2251 + /* 945 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 19, + 5, + 0, // Skip to: 2251 + /* 952 */ MCD_OPC_Decode, + 224, + 17, + 232, + 1, // Opcode: VCVTMNSQh + /* 957 */ MCD_OPC_FilterValue, + 59, + 9, + 5, + 0, // Skip to: 2251 + /* 962 */ MCD_OPC_CheckPredicate, + 99, + 4, + 5, + 0, // Skip to: 2251 + /* 967 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 252, + 4, + 0, // Skip to: 2251 + /* 975 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 245, + 4, + 0, // Skip to: 2251 + /* 982 */ MCD_OPC_Decode, + 223, + 17, + 232, + 1, // Opcode: VCVTMNSQf + /* 987 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 1055 + /* 992 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 995 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 1025 + /* 1000 */ MCD_OPC_CheckPredicate, + 98, + 222, + 4, + 0, // Skip to: 2251 + /* 1005 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 214, + 4, + 0, // Skip to: 2251 + /* 1013 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 207, + 4, + 0, // Skip to: 2251 + /* 1020 */ MCD_OPC_Decode, + 226, + 17, + 231, + 1, // Opcode: VCVTMNUDh + /* 1025 */ MCD_OPC_FilterValue, + 59, + 197, + 4, + 0, // Skip to: 2251 + /* 1030 */ MCD_OPC_CheckPredicate, + 99, + 192, + 4, + 0, // Skip to: 2251 + /* 1035 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 184, + 4, + 0, // Skip to: 2251 + /* 1043 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 177, + 4, + 0, // Skip to: 2251 + /* 1050 */ MCD_OPC_Decode, + 225, + 17, + 231, + 1, // Opcode: VCVTMNUDf + /* 1055 */ MCD_OPC_FilterValue, + 3, + 167, + 4, + 0, // Skip to: 2251 + /* 1060 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1063 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 1093 + /* 1068 */ MCD_OPC_CheckPredicate, + 98, + 154, + 4, + 0, // Skip to: 2251 + /* 1073 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 146, + 4, + 0, // Skip to: 2251 + /* 1081 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 139, + 4, + 0, // Skip to: 2251 + /* 1088 */ MCD_OPC_Decode, + 228, + 17, + 232, + 1, // Opcode: VCVTMNUQh + /* 1093 */ MCD_OPC_FilterValue, + 59, + 129, + 4, + 0, // Skip to: 2251 + /* 1098 */ MCD_OPC_CheckPredicate, + 99, + 124, + 4, + 0, // Skip to: 2251 + /* 1103 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 116, + 4, + 0, // Skip to: 2251 + /* 1111 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 109, + 4, + 0, // Skip to: 2251 + /* 1118 */ MCD_OPC_Decode, + 227, + 17, + 232, + 1, // Opcode: VCVTMNUQf + /* 1123 */ MCD_OPC_FilterValue, + 4, + 19, + 1, + 0, // Skip to: 1403 + /* 1128 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1131 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 1199 + /* 1136 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1139 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1169 + /* 1144 */ MCD_OPC_CheckPredicate, + 98, + 78, + 4, + 0, // Skip to: 2251 + /* 1149 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 70, + 4, + 0, // Skip to: 2251 + /* 1157 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 63, + 4, + 0, // Skip to: 2251 + /* 1164 */ MCD_OPC_Decode, + 246, + 25, + 231, + 1, // Opcode: VRINTNNDh + /* 1169 */ MCD_OPC_FilterValue, + 58, + 53, + 4, + 0, // Skip to: 2251 + /* 1174 */ MCD_OPC_CheckPredicate, + 99, + 48, + 4, + 0, // Skip to: 2251 + /* 1179 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 40, + 4, + 0, // Skip to: 2251 + /* 1187 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 33, + 4, + 0, // Skip to: 2251 + /* 1194 */ MCD_OPC_Decode, + 245, + 25, + 231, + 1, // Opcode: VRINTNNDf + /* 1199 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 1267 + /* 1204 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1207 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1237 + /* 1212 */ MCD_OPC_CheckPredicate, + 98, + 10, + 4, + 0, // Skip to: 2251 + /* 1217 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 2, + 4, + 0, // Skip to: 2251 + /* 1225 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 251, + 3, + 0, // Skip to: 2251 + /* 1232 */ MCD_OPC_Decode, + 248, + 25, + 232, + 1, // Opcode: VRINTNNQh + /* 1237 */ MCD_OPC_FilterValue, + 58, + 241, + 3, + 0, // Skip to: 2251 + /* 1242 */ MCD_OPC_CheckPredicate, + 99, + 236, + 3, + 0, // Skip to: 2251 + /* 1247 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 228, + 3, + 0, // Skip to: 2251 + /* 1255 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 221, + 3, + 0, // Skip to: 2251 + /* 1262 */ MCD_OPC_Decode, + 247, + 25, + 232, + 1, // Opcode: VRINTNNQf + /* 1267 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 1335 + /* 1272 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1275 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1305 + /* 1280 */ MCD_OPC_CheckPredicate, + 98, + 198, + 3, + 0, // Skip to: 2251 + /* 1285 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 190, + 3, + 0, // Skip to: 2251 + /* 1293 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 183, + 3, + 0, // Skip to: 2251 + /* 1300 */ MCD_OPC_Decode, + 135, + 26, + 231, + 1, // Opcode: VRINTXNDh + /* 1305 */ MCD_OPC_FilterValue, + 58, + 173, + 3, + 0, // Skip to: 2251 + /* 1310 */ MCD_OPC_CheckPredicate, + 99, + 168, + 3, + 0, // Skip to: 2251 + /* 1315 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 160, + 3, + 0, // Skip to: 2251 + /* 1323 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 153, + 3, + 0, // Skip to: 2251 + /* 1330 */ MCD_OPC_Decode, + 134, + 26, + 231, + 1, // Opcode: VRINTXNDf + /* 1335 */ MCD_OPC_FilterValue, + 3, + 143, + 3, + 0, // Skip to: 2251 + /* 1340 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1343 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1373 + /* 1348 */ MCD_OPC_CheckPredicate, + 98, + 130, + 3, + 0, // Skip to: 2251 + /* 1353 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 122, + 3, + 0, // Skip to: 2251 + /* 1361 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 115, + 3, + 0, // Skip to: 2251 + /* 1368 */ MCD_OPC_Decode, + 137, + 26, + 232, + 1, // Opcode: VRINTXNQh + /* 1373 */ MCD_OPC_FilterValue, + 58, + 105, + 3, + 0, // Skip to: 2251 + /* 1378 */ MCD_OPC_CheckPredicate, + 99, + 100, + 3, + 0, // Skip to: 2251 + /* 1383 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 92, + 3, + 0, // Skip to: 2251 + /* 1391 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 85, + 3, + 0, // Skip to: 2251 + /* 1398 */ MCD_OPC_Decode, + 136, + 26, + 232, + 1, // Opcode: VRINTXNQf + /* 1403 */ MCD_OPC_FilterValue, + 5, + 19, + 1, + 0, // Skip to: 1683 + /* 1408 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1411 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 1479 + /* 1416 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1419 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1449 + /* 1424 */ MCD_OPC_CheckPredicate, + 98, + 54, + 3, + 0, // Skip to: 2251 + /* 1429 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 46, + 3, + 0, // Skip to: 2251 + /* 1437 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 39, + 3, + 0, // Skip to: 2251 + /* 1444 */ MCD_OPC_Decode, + 232, + 25, + 231, + 1, // Opcode: VRINTANDh + /* 1449 */ MCD_OPC_FilterValue, + 58, + 29, + 3, + 0, // Skip to: 2251 + /* 1454 */ MCD_OPC_CheckPredicate, + 99, + 24, + 3, + 0, // Skip to: 2251 + /* 1459 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 16, + 3, + 0, // Skip to: 2251 + /* 1467 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 9, + 3, + 0, // Skip to: 2251 + /* 1474 */ MCD_OPC_Decode, + 231, + 25, + 231, + 1, // Opcode: VRINTANDf + /* 1479 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 1547 + /* 1484 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1487 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1517 + /* 1492 */ MCD_OPC_CheckPredicate, + 98, + 242, + 2, + 0, // Skip to: 2251 + /* 1497 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 234, + 2, + 0, // Skip to: 2251 + /* 1505 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 227, + 2, + 0, // Skip to: 2251 + /* 1512 */ MCD_OPC_Decode, + 234, + 25, + 232, + 1, // Opcode: VRINTANQh + /* 1517 */ MCD_OPC_FilterValue, + 58, + 217, + 2, + 0, // Skip to: 2251 + /* 1522 */ MCD_OPC_CheckPredicate, + 99, + 212, + 2, + 0, // Skip to: 2251 + /* 1527 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 204, + 2, + 0, // Skip to: 2251 + /* 1535 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 197, + 2, + 0, // Skip to: 2251 + /* 1542 */ MCD_OPC_Decode, + 233, + 25, + 232, + 1, // Opcode: VRINTANQf + /* 1547 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 1615 + /* 1552 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1555 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1585 + /* 1560 */ MCD_OPC_CheckPredicate, + 98, + 174, + 2, + 0, // Skip to: 2251 + /* 1565 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 166, + 2, + 0, // Skip to: 2251 + /* 1573 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 159, + 2, + 0, // Skip to: 2251 + /* 1580 */ MCD_OPC_Decode, + 142, + 26, + 231, + 1, // Opcode: VRINTZNDh + /* 1585 */ MCD_OPC_FilterValue, + 58, + 149, + 2, + 0, // Skip to: 2251 + /* 1590 */ MCD_OPC_CheckPredicate, + 99, + 144, + 2, + 0, // Skip to: 2251 + /* 1595 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 136, + 2, + 0, // Skip to: 2251 + /* 1603 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 129, + 2, + 0, // Skip to: 2251 + /* 1610 */ MCD_OPC_Decode, + 141, + 26, + 231, + 1, // Opcode: VRINTZNDf + /* 1615 */ MCD_OPC_FilterValue, + 3, + 119, + 2, + 0, // Skip to: 2251 + /* 1620 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1623 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1653 + /* 1628 */ MCD_OPC_CheckPredicate, + 98, + 106, + 2, + 0, // Skip to: 2251 + /* 1633 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 98, + 2, + 0, // Skip to: 2251 + /* 1641 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 91, + 2, + 0, // Skip to: 2251 + /* 1648 */ MCD_OPC_Decode, + 144, + 26, + 232, + 1, // Opcode: VRINTZNQh + /* 1653 */ MCD_OPC_FilterValue, + 58, + 81, + 2, + 0, // Skip to: 2251 + /* 1658 */ MCD_OPC_CheckPredicate, + 99, + 76, + 2, + 0, // Skip to: 2251 + /* 1663 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 68, + 2, + 0, // Skip to: 2251 + /* 1671 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 61, + 2, + 0, // Skip to: 2251 + /* 1678 */ MCD_OPC_Decode, + 143, + 26, + 232, + 1, // Opcode: VRINTZNQf + /* 1683 */ MCD_OPC_FilterValue, + 6, + 139, + 0, + 0, // Skip to: 1827 + /* 1688 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1691 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 1759 + /* 1696 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1699 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1729 + /* 1704 */ MCD_OPC_CheckPredicate, + 98, + 30, + 2, + 0, // Skip to: 2251 + /* 1709 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 22, + 2, + 0, // Skip to: 2251 + /* 1717 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 15, + 2, + 0, // Skip to: 2251 + /* 1724 */ MCD_OPC_Decode, + 239, + 25, + 231, + 1, // Opcode: VRINTMNDh + /* 1729 */ MCD_OPC_FilterValue, + 58, + 5, + 2, + 0, // Skip to: 2251 + /* 1734 */ MCD_OPC_CheckPredicate, + 99, + 0, + 2, + 0, // Skip to: 2251 + /* 1739 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 248, + 1, + 0, // Skip to: 2251 + /* 1747 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 241, + 1, + 0, // Skip to: 2251 + /* 1754 */ MCD_OPC_Decode, + 238, + 25, + 231, + 1, // Opcode: VRINTMNDf + /* 1759 */ MCD_OPC_FilterValue, + 3, + 231, + 1, + 0, // Skip to: 2251 + /* 1764 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1767 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1797 + /* 1772 */ MCD_OPC_CheckPredicate, + 98, + 218, + 1, + 0, // Skip to: 2251 + /* 1777 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 210, + 1, + 0, // Skip to: 2251 + /* 1785 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 203, + 1, + 0, // Skip to: 2251 + /* 1792 */ MCD_OPC_Decode, + 241, + 25, + 232, + 1, // Opcode: VRINTMNQh + /* 1797 */ MCD_OPC_FilterValue, + 58, + 193, + 1, + 0, // Skip to: 2251 + /* 1802 */ MCD_OPC_CheckPredicate, + 99, + 188, + 1, + 0, // Skip to: 2251 + /* 1807 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 180, + 1, + 0, // Skip to: 2251 + /* 1815 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 173, + 1, + 0, // Skip to: 2251 + /* 1822 */ MCD_OPC_Decode, + 240, + 25, + 232, + 1, // Opcode: VRINTMNQf + /* 1827 */ MCD_OPC_FilterValue, + 7, + 139, + 0, + 0, // Skip to: 1971 + /* 1832 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1835 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 1903 + /* 1840 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1843 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1873 + /* 1848 */ MCD_OPC_CheckPredicate, + 98, + 142, + 1, + 0, // Skip to: 2251 + /* 1853 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 134, + 1, + 0, // Skip to: 2251 + /* 1861 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 127, + 1, + 0, // Skip to: 2251 + /* 1868 */ MCD_OPC_Decode, + 253, + 25, + 231, + 1, // Opcode: VRINTPNDh + /* 1873 */ MCD_OPC_FilterValue, + 58, + 117, + 1, + 0, // Skip to: 2251 + /* 1878 */ MCD_OPC_CheckPredicate, + 99, + 112, + 1, + 0, // Skip to: 2251 + /* 1883 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 104, + 1, + 0, // Skip to: 2251 + /* 1891 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 97, + 1, + 0, // Skip to: 2251 + /* 1898 */ MCD_OPC_Decode, + 252, + 25, + 231, + 1, // Opcode: VRINTPNDf + /* 1903 */ MCD_OPC_FilterValue, + 3, + 87, + 1, + 0, // Skip to: 2251 + /* 1908 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1911 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1941 + /* 1916 */ MCD_OPC_CheckPredicate, + 98, + 74, + 1, + 0, // Skip to: 2251 + /* 1921 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 66, + 1, + 0, // Skip to: 2251 + /* 1929 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 59, + 1, + 0, // Skip to: 2251 + /* 1936 */ MCD_OPC_Decode, + 255, + 25, + 232, + 1, // Opcode: VRINTPNQh + /* 1941 */ MCD_OPC_FilterValue, + 58, + 49, + 1, + 0, // Skip to: 2251 + /* 1946 */ MCD_OPC_CheckPredicate, + 99, + 44, + 1, + 0, // Skip to: 2251 + /* 1951 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 36, + 1, + 0, // Skip to: 2251 + /* 1959 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 29, + 1, + 0, // Skip to: 2251 + /* 1966 */ MCD_OPC_Decode, + 254, + 25, + 232, + 1, // Opcode: VRINTPNQf + /* 1971 */ MCD_OPC_FilterValue, + 15, + 19, + 1, + 0, // Skip to: 2251 + /* 1976 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1979 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 2047 + /* 1984 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1987 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2017 + /* 1992 */ MCD_OPC_CheckPredicate, + 99, + 254, + 0, + 0, // Skip to: 2251 + /* 1997 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 246, + 0, + 0, // Skip to: 2251 + /* 2005 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 239, + 0, + 0, // Skip to: 2251 + /* 2012 */ MCD_OPC_Decode, + 227, + 13, + 202, + 1, // Opcode: NEON_VMAXNMNDf + /* 2017 */ MCD_OPC_FilterValue, + 1, + 229, + 0, + 0, // Skip to: 2251 + /* 2022 */ MCD_OPC_CheckPredicate, + 99, + 224, + 0, + 0, // Skip to: 2251 + /* 2027 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 216, + 0, + 0, // Skip to: 2251 + /* 2035 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 209, + 0, + 0, // Skip to: 2251 + /* 2042 */ MCD_OPC_Decode, + 229, + 13, + 203, + 1, // Opcode: NEON_VMAXNMNQf + /* 2047 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 2115 + /* 2052 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2055 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2085 + /* 2060 */ MCD_OPC_CheckPredicate, + 98, + 186, + 0, + 0, // Skip to: 2251 + /* 2065 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 178, + 0, + 0, // Skip to: 2251 + /* 2073 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 171, + 0, + 0, // Skip to: 2251 + /* 2080 */ MCD_OPC_Decode, + 228, + 13, + 202, + 1, // Opcode: NEON_VMAXNMNDh + /* 2085 */ MCD_OPC_FilterValue, + 1, + 161, + 0, + 0, // Skip to: 2251 + /* 2090 */ MCD_OPC_CheckPredicate, + 98, + 156, + 0, + 0, // Skip to: 2251 + /* 2095 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 148, + 0, + 0, // Skip to: 2251 + /* 2103 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 141, + 0, + 0, // Skip to: 2251 + /* 2110 */ MCD_OPC_Decode, + 230, + 13, + 203, + 1, // Opcode: NEON_VMAXNMNQh + /* 2115 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 2183 + /* 2120 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2123 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2153 + /* 2128 */ MCD_OPC_CheckPredicate, + 99, + 118, + 0, + 0, // Skip to: 2251 + /* 2133 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 110, + 0, + 0, // Skip to: 2251 + /* 2141 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 103, + 0, + 0, // Skip to: 2251 + /* 2148 */ MCD_OPC_Decode, + 231, + 13, + 202, + 1, // Opcode: NEON_VMINNMNDf + /* 2153 */ MCD_OPC_FilterValue, + 1, + 93, + 0, + 0, // Skip to: 2251 + /* 2158 */ MCD_OPC_CheckPredicate, + 99, + 88, + 0, + 0, // Skip to: 2251 + /* 2163 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 80, + 0, + 0, // Skip to: 2251 + /* 2171 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 73, + 0, + 0, // Skip to: 2251 + /* 2178 */ MCD_OPC_Decode, + 233, + 13, + 203, + 1, // Opcode: NEON_VMINNMNQf + /* 2183 */ MCD_OPC_FilterValue, + 3, + 63, + 0, + 0, // Skip to: 2251 + /* 2188 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2191 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2221 + /* 2196 */ MCD_OPC_CheckPredicate, + 98, + 50, + 0, + 0, // Skip to: 2251 + /* 2201 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 42, + 0, + 0, // Skip to: 2251 + /* 2209 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 35, + 0, + 0, // Skip to: 2251 + /* 2216 */ MCD_OPC_Decode, + 232, + 13, + 202, + 1, // Opcode: NEON_VMINNMNDh + /* 2221 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 2251 + /* 2226 */ MCD_OPC_CheckPredicate, + 98, + 20, + 0, + 0, // Skip to: 2251 + /* 2231 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 12, + 0, + 0, // Skip to: 2251 + /* 2239 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 5, + 0, + 0, // Skip to: 2251 + /* 2246 */ MCD_OPC_Decode, + 234, + 13, + 203, + 1, // Opcode: NEON_VMINNMNQh + /* 2251 */ MCD_OPC_Fail, + 0 +}; + +static bool checkDecoderPredicate(MCInst *Inst, unsigned Idx) +{ + switch (Idx) { + default: /* llvm_unreachable("Invalid index!"); */ + case 0: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb)); + case 1: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV6Ops)); + case 2: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureCRC)); + case 3: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV5TEOps)); + case 4: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)); + case 5: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)); + case 6: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps)); + case 7: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureVirtualization)); + case 8: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureAcquireRelease)); + case 9: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureAcquireRelease) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureV7Clrex)); + case 10: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV4TOps)); + case 11: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV5TOps)); + case 12: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureTrustZone)); + case 13: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV6T2Ops)); + case 14: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_4aOps)); + case 15: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops)); + case 16: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP)); + case 17: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV6KOps)); + case 18: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDB)); + case 19: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureSB)); + case 20: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureHWDivARM)); + case 21: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureNaClTrap)); + case 22: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_HasMVEIntegerOps)); + case 23: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV8_1MMainlineOps) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_HasMVEIntegerOps)); + case 24: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_HasMVEFloatOps)); + case 25: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureFPRegs) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV8_1MMainlineOps)); + case 26: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON)); + case 27: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureFullFP16)); + case 28: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps)); + case 29: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureAES)); + case 30: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP16)); + case 31: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureBF16) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON)); + case 32: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureVFP4_D16_SP)); + case 33: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureVFP2_SP)); + case 34: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFPRegs)); + case 35: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb)); + case 36: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_Feature8MSecExt)); + case 37: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV5TOps)); + case 38: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV6Ops)); + case 39: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV8MBaselineOps)); + case 40: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps)); + case 41: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + !ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureMClass)); + case 42: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)); + case 43: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV6MOps)); + case 44: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV5TOps) && + !ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureMClass)); + case 45: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)); + case 46: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + !ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureMClass)); + case 47: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV8_1MMainlineOps)); + case 48: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureAcquireRelease)); + case 49: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureAcquireRelease) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureV7Clrex)); + case 50: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureAcquireRelease) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureV7Clrex) && + !ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureMClass)); + case 51: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDSP) && + (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2))); + case 52: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_Feature8MSecExt)); + case 53: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDSP)); + case 54: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)); + case 55: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_4aOps)); + case 56: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureV7Clrex)); + case 57: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDB)); + case 58: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass)); + case 59: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureSB)); + case 60: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureVirtualization)); + case 61: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureTrustZone)); + case 62: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureVirtualization)); + case 63: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass)); + case 64: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV8_1MMainlineOps) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureLOB)); + case 65: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops)); + case 66: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2))); + case 67: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureHWDivThumb) && + ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV8MBaselineOps)); + case 68: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP)); + case 69: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureCRC)); + case 70: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV8_1MMainlineOps) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeaturePACBTI)); + case 71: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasCDEOps) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFPRegs)); + case 72: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasCDEOps) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_HasMVEIntegerOps)); + case 73: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasCDEOps)); + case 74: + return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2)) && + !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)); + case 75: + return (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && + (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureThumb2))); + case 76: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureFPRegs16)); + case 77: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureFullFP16)); + case 78: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV8_1MMainlineOps) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_Feature8MSecExt)); + case 79: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureVFP4_D16_SP)); + case 80: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV8MMainlineOps) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_Feature8MSecExt)); + case 81: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_HasV8_1MMainlineOps) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFPRegs)); + case 82: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureVFP3_D16_SP)); + case 83: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP16)); + case 84: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureFPARMv8_D16_SP)); + case 85: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureVFP2_SP) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP64)); + case 86: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureVFP4_D16_SP) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP64)); + case 87: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureVFP3_D16_SP) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP64)); + case 88: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureFPRegs64)); + case 89: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureFPARMv8_D16_SP) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP64)); + case 90: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureFPARMv8_D16_SP) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_3aOps)); + case 91: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_3aOps) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureFullFP16)); + case 92: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && + ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_3aOps)); + case 93: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureFP16FML)); + case 94: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureBF16)); + case 95: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureMatMulInt8)); + case 96: + return (ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureDotProd)); + case 97: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureSHA2)); + case 98: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && + ARM_getFeatureBits(Inst->csh->mode, + ARM_FeatureFullFP16)); + case 99: + return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && + ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON)); + } +} + +#define DecodeToMCInst(fname, fieldname, InsnType) \ + static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, \ + MCInst *MI, uint64_t Address, bool *Decoder) \ + { \ + InsnType tmp; \ + switch (Idx) { \ + default: /* llvm_unreachable("Invalid index!"); */ \ + case 0: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 1: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 2: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 3: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 4: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 5: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 6: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 7: \ + if (!Check(&S, DecodeAddrMode3Instruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 8: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 9: \ + if (!Check(&S, DecodeCPSInstruction(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 10: \ + tmp = fieldname(insn, 9, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 11: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 12: \ + if (!Check(&S, DecodeQADDInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 13: \ + if (!Check(&S, DecodeSMLAInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 14: \ + if (!Check(&S, \ + DecodeSwap(MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 15: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 8, 12) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 16: \ + if (!Check(&S, DecodeTSTInstruction(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 17: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 18: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 19: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 20: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 21: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 22: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 23: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 24: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 25: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (!Check(&S, DecodeBankedReg(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 26: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeMSRMask(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 27: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (!Check(&S, DecodeBankedReg(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 28: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 29: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 30: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 31: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 32: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodetcGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodetcGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 33: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 34: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 35: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 36: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 37: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 38: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 39: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 40: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 41: \ + if (!Check(&S, DecodeDoubleRegStore(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 42: \ + if (!Check(&S, DecodeDoubleRegLoad(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 43: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 23, 1) << 4; \ + if (!Check(&S, DecodePostIdxReg(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 44: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 8, 4) << 4; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 45: \ + if (!Check(&S, \ + DecodeLDR(MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 46: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 8, 4) << 4; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 47: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 48: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 22, 2) << 12; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 49: \ + if (!Check(&S, DecodeArmMOVTWInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 50: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 51: \ + if (!Check(&S, DecodeTSBInstruction(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 52: \ + if (!Check(&S, DecodeHINTInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 53: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeMSRMask(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 54: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 55: \ + if (!Check(&S, DecodeAddrMode2IdxInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 56: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (!Check(&S, DecodeAddrModeImm12Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 57: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (!Check(&S, DecodeAddrModeImm12Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 58: \ + if (!Check(&S, DecodeSTRPreImm(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 59: \ + if (!Check(&S, DecodeLDRPreImm(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 60: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (!Check(&S, DecodeAddrModeImm12Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 61: \ + return S; \ + case 62: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeMemBarrierOption( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 63: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeInstSyncBarrierOption( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 64: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 65: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 66: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 67: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 68: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 69: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 70: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 71: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 72: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 73: \ + if (!Check(&S, DecodeSTRPreReg(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 74: \ + if (!Check(&S, DecodeLDRPreReg(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 75: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 1) << 5; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 76: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 77: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 78: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 79: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 5; \ + if (!Check(&S, DecodeBitfieldMaskOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 80: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 5; \ + if (!Check(&S, DecodeBitfieldMaskOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 81: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 82: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 83: \ + if (!Check(&S, DecodeMemMultipleWritebackInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 84: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 85: \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 86: \ + if (!Check(&S, DecodeBranchImmInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 87: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 24) << 1; \ + tmp |= fieldname(insn, 24, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 88: \ + if (!Check(&S, DecoderForMRRC2AndMCRR2( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 89: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 90: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 91: \ + tmp = fieldname(insn, 0, 24); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 92: \ + if (!Check(&S, DecodeCopMemInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 93: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 94: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 95: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 96: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 97: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRwithAPSRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 98: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRwithAPSRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 99: \ + if (!Check(&S, DecodeMveVCTP(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 100: \ + if (!Check(&S, DecodeMVEOverlappingLongShift( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 101: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 102: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + if (!Check(&S, DecodeLongShiftOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 103: \ + tmp = fieldname(insn, 17, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 3) << 1; \ + if (!Check(&S, DecodetGPROddRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 3) << 1; \ + if (!Check(&S, DecodetGPROddRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + if (!Check(&S, DecodeLongShiftOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 104: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 105: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 23, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 106: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 16, 4) << 3; \ + if (!Check(&S, DecodeMveAddrModeRQ(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 107: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 16, 3) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (!Check(&S, DecodeTAddrModeImm7_0(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 108: \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (!Check(&S, DecodeT2Imm7_0(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 109: \ + if (!Check(&S, DecodeMVE_MEM_1_pre_0( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 110: \ + if (!Check(&S, DecodeMVEVMOVQtoDReg(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 111: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 16, 3) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (!Check(&S, DecodeTAddrModeImm7_1(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 112: \ + if (!Check(&S, DecodeMVEVMOVDRegtoQ(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 113: \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (!Check(&S, DecodeT2Imm7_1(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 114: \ + if (!Check(&S, DecodeMVE_MEM_1_pre_1( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 115: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 116: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQQQQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 117: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 16, 4) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (!Check(&S, DecodeT2AddrModeImm7_0_0( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 118: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 17, 3) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (!Check(&S, DecodeMveAddrModeQ_2(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 119: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 16, 4) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (!Check(&S, DecodeT2AddrModeImm7_1_0( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 120: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 121: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQQQQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQQQQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 122: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (!Check(&S, DecodeT2Imm7_0(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 123: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 124: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQQQQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 125: \ + if (!Check(&S, DecodeMVE_MEM_2_pre_0( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 126: \ + if (!Check(&S, DecodeMVE_MEM_3_pre_2( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 127: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (!Check(&S, DecodeT2Imm7_1(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 128: \ + if (!Check(&S, DecodeMVE_MEM_2_pre_1( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 129: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 130: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQQQQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQQQQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 131: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 16, 4) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (!Check(&S, DecodeT2AddrModeImm7_2_0( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 132: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 17, 3) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (!Check(&S, DecodeMveAddrModeQ_3(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 133: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (!Check(&S, DecodeT2Imm7_2(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 134: \ + if (!Check(&S, DecodeMVE_MEM_2_pre_2( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 135: \ + if (!Check(&S, DecodeMVE_MEM_3_pre_3( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 136: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 137: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 1) << 0; \ + tmp |= fieldname(insn, 16, 1) << 2; \ + tmp |= fieldname(insn, 21, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 138: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 2) << 0; \ + tmp |= fieldname(insn, 16, 1) << 3; \ + tmp |= fieldname(insn, 21, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 139: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 140: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 1) << 0; \ + tmp |= fieldname(insn, 16, 1) << 2; \ + tmp |= fieldname(insn, 21, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 141: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 2) << 0; \ + tmp |= fieldname(insn, 16, 1) << 3; \ + tmp |= fieldname(insn, 21, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 142: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 143: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 144: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 145: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 146: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 0; \ + tmp |= fieldname(insn, 12, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 147: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 148: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 149: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 150: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 151: \ + if (!Check(&S, \ + DecodeMVEVCMP_0_DecodeRestrictedIPredicateOperand( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 152: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 1); \ + if (!Check(&S, DecodeRestrictedIPredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 153: \ + if (!Check(&S, \ + DecodeMVEVCMP_0_DecodeRestrictedUPredicateOperand( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 154: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 1); \ + if (!Check(&S, DecodeRestrictedUPredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 155: \ + if (!Check(&S, \ + DecodeMVEVCMP_0_DecodeRestrictedSPredicateOperand( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 156: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 1; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + if (!Check(&S, DecodeRestrictedSPredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 157: \ + if (!Check(&S, \ + DecodeMVEVCMP_1_DecodeRestrictedIPredicateOperand( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 158: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRwithZRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 1); \ + if (!Check(&S, DecodeRestrictedIPredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 159: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + if (!Check(&S, DecodePowerTwoOperand_0_3( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 160: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3) << 1; \ + if (!Check(&S, DecodetGPROddRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + if (!Check(&S, DecodePowerTwoOperand_0_3( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 161: \ + if (!Check(&S, \ + DecodeMVEVCMP_1_DecodeRestrictedUPredicateOperand( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 162: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRwithZRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 1); \ + if (!Check(&S, DecodeRestrictedUPredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 163: \ + if (!Check(&S, \ + DecodeMVEVCMP_1_DecodeRestrictedSPredicateOperand( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 164: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRwithZRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + if (!Check(&S, DecodeRestrictedSPredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 165: \ + if (!Check(&S, DecodeMVEVADCInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 166: \ + if (!Check(&S, \ + DecodeMVEVCMP_0_DecodeRestrictedFPPredicateOperand( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 167: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 1; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 12, 1) << 2; \ + if (!Check(&S, DecodeRestrictedFPPredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 168: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 169: \ + if (!Check(&S, \ + DecodeMVEVCMP_1_DecodeRestrictedFPPredicateOperand( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 170: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRwithZRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 12, 1) << 2; \ + if (!Check(&S, DecodeRestrictedFPPredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 171: \ + if (!Check(&S, DecodeMVEVPNOT(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 172: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 173: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 174: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 175: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 3) << 1; \ + if (!Check(&S, DecodetGPROddRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 176: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 177: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 3) << 1; \ + if (!Check(&S, DecodetGPROddRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 3) << 1; \ + if (!Check(&S, DecodetGPROddRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 178: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 179: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 180: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 3) << 1; \ + if (!Check(&S, DecodetGPROddRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 181: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 182: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 3) << 1; \ + if (!Check(&S, DecodetGPROddRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (!Check(&S, DecodetGPREvenRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 3) << 1; \ + if (!Check(&S, DecodetGPROddRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 183: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 184: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 185: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 186: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 187: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 188: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeLongShiftOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 189: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 190: \ + if (!Check(&S, DecodeMVEModImmInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 191: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 9, 2) << 9; \ + tmp |= fieldname(insn, 16, 3) << 4; \ + tmp |= fieldname(insn, 28, 1) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 192: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 9, 1) << 9; \ + tmp |= fieldname(insn, 16, 3) << 4; \ + tmp |= fieldname(insn, 28, 1) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 193: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 194: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 195: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 196: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 197: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 198: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 199: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 200: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 201: \ + if (!Check(&S, DecodeMVEVCVTt1fp(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 202: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 203: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 204: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 205: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 206: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 207: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 208: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 209: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 210: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 211: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 212: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeDPR_8RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 213: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeDPR_8RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 214: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeDPR_8RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 215: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeDPR_8RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 216: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeDPR_8RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 217: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeDPR_8RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 218: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 219: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 220: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 221: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 222: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 223: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 224: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 225: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 226: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 227: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 228: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 229: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 230: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 231: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 232: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 233: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 234: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 235: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 236: \ + if (!Check(&S, DecodeVSHLMaxInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 237: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 238: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 239: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 240: \ + if (!Check(&S, DecodeTBLInstruction(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 241: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 242: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 243: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 244: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 245: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 246: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 247: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 248: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 249: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 250: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 251: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 252: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 253: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 254: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 255: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 256: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 257: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 258: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 259: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 260: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 261: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 262: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 263: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 264: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 265: \ + if (!Check(&S, \ + DecodeVCVTD(MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 266: \ + if (!Check(&S, DecodeVMOVModImmInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 267: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 268: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 269: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 270: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 271: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 272: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 273: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 274: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 275: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 276: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 277: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 278: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 279: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 280: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 281: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 282: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 283: \ + if (!Check(&S, \ + DecodeVCVTQ(MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 284: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 285: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 286: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 287: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 288: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 289: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 290: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 1) << 0; \ + tmp |= fieldname(insn, 21, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 291: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 1) << 0; \ + tmp |= fieldname(insn, 21, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 292: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 2) << 0; \ + tmp |= fieldname(insn, 21, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 293: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 2) << 0; \ + tmp |= fieldname(insn, 21, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 294: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 295: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 296: \ + if (!Check(&S, DecodeVLDST4Instruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 297: \ + if (!Check(&S, DecodeVST1LN(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 298: \ + if (!Check(&S, DecodeVLD1LN(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 299: \ + if (!Check(&S, DecodeVST2LN(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 300: \ + if (!Check(&S, DecodeVLD2LN(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 301: \ + if (!Check(&S, DecodeVLDST1Instruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 302: \ + if (!Check(&S, DecodeVST3LN(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 303: \ + if (!Check(&S, DecodeVLD3LN(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 304: \ + if (!Check(&S, DecodeVLDST2Instruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 305: \ + if (!Check(&S, DecodeVST4LN(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 306: \ + if (!Check(&S, DecodeVLD4LN(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 307: \ + if (!Check(&S, DecodeVLDST3Instruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 308: \ + if (!Check(&S, DecodeVLD1DupInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 309: \ + if (!Check(&S, DecodeVLD2DupInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 310: \ + if (!Check(&S, DecodeVLD3DupInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 311: \ + if (!Check(&S, DecodeVLD4DupInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 312: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 313: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 314: \ + if (!Check(&S, DecodeThumbAddSPReg(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 315: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 316: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 317: \ + tmp = fieldname(insn, 3, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 318: \ + tmp = fieldname(insn, 3, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 319: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeThumbAddrModePC(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 320: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 6); \ + if (!Check(&S, DecodeThumbAddrModeRR(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 321: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 8); \ + if (!Check(&S, DecodeThumbAddrModeIS(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 322: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeThumbAddrModeSP(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 323: \ + if (!Check(&S, DecodeThumbAddSpecialReg( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 324: \ + if (!Check(&S, DecodeThumbAddSPImm(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 325: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 5) << 0; \ + tmp |= fieldname(insn, 9, 1) << 5; \ + if (!Check(&S, DecodeThumbCmpBROperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 326: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 8, 1) << 14; \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 327: \ + tmp = fieldname(insn, 3, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 328: \ + if (!Check(&S, DecodeThumbCPS(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 329: \ + tmp = fieldname(insn, 0, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 330: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 8, 1) << 15; \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 331: \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 332: \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 333: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 334: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 335: \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeThumbBCCTargetOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 336: \ + tmp = fieldname(insn, 0, 11); \ + if (!Check(&S, DecodeThumbBROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 337: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + tmp |= fieldname(insn, 11, 1) << 21; \ + tmp |= fieldname(insn, 13, 1) << 22; \ + tmp |= fieldname(insn, 16, 10) << 11; \ + tmp |= fieldname(insn, 26, 1) << 23; \ + if (!Check(&S, DecodeThumbBLXOffset(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 338: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 11) << 0; \ + tmp |= fieldname(insn, 11, 1) << 21; \ + tmp |= fieldname(insn, 13, 1) << 22; \ + tmp |= fieldname(insn, 16, 10) << 11; \ + tmp |= fieldname(insn, 26, 1) << 23; \ + if (!Check(&S, DecodeThumbBLTargetOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 339: \ + if (!Check(&S, \ + DecodeIT(MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 340: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 13) << 0; \ + tmp |= fieldname(insn, 14, 1) << 14; \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 341: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 13) << 0; \ + tmp |= fieldname(insn, 14, 2) << 14; \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 342: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 343: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 344: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 345: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 346: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 347: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 348: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 349: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 350: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 351: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 13) << 0; \ + tmp |= fieldname(insn, 14, 1) << 14; \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 352: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 353: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 354: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 8; \ + if (!Check(&S, DecodeT2AddrModeImm0_1020s4( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 355: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 356: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 357: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 358: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 8; \ + if (!Check(&S, DecodeT2AddrModeImm0_1020s4( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 359: \ + if (!Check(&S, DecodeThumbTableBranch( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 360: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 361: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (!Check(&S, DecodeT2AddrModeImm8s4( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 362: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 363: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 364: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 365: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRwithZRnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRwithZRnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodePredNoALOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 366: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 367: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 368: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 369: \ + if (!Check(&S, DecodeT2STRDPreInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 370: \ + if (!Check(&S, DecodeT2LDRDPreInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 371: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 372: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 373: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 374: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 375: \ + if (!Check(&S, DecodeT2AddSubSPImm(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 376: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 377: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 378: \ + if (!Check(&S, \ + DecodeT2Adr(MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 379: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 380: \ + if (!Check(&S, DecodeT2MOVTWInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 381: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 382: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + tmp |= fieldname(insn, 21, 1) << 5; \ + if (!Check(&S, DecodeT2ShifterImmOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 383: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 384: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 5; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + if (!Check(&S, DecodeBitfieldMaskOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 385: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 5; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + if (!Check(&S, DecodeBitfieldMaskOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 386: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 387: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 388: \ + if (!Check(&S, DecodeT2HintSpaceInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 389: \ + if (!Check(&S, DecodeT2CPSInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 390: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 391: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 12; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 392: \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 393: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 20, 1) << 4; \ + if (!Check(&S, DecodeMSRMask(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 394: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 20, 1) << 5; \ + if (!Check(&S, DecodeBankedReg(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 395: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 10, 2) << 10; \ + if (!Check(&S, DecodeMSRMask(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 396: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 20, 1) << 5; \ + if (!Check(&S, DecodeBankedReg(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 397: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeMSRMask(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 398: \ + if (!Check(&S, DecodeThumb2BCCInstruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 399: \ + if (!Check(&S, DecodeLOLoop(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 400: \ + tmp = fieldname(insn, 23, 4); \ + if (!Check(&S, DecodeBFLabelOperand_0_0_0_4( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + tmp |= fieldname(insn, 11, 1) << 0; \ + tmp |= fieldname(insn, 16, 7) << 11; \ + if (!Check(&S, DecodeBFLabelOperand_1_0_1_18( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 401: \ + tmp = fieldname(insn, 23, 4); \ + if (!Check(&S, DecodeBFLabelOperand_0_0_0_4( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + tmp |= fieldname(insn, 11, 1) << 0; \ + tmp |= fieldname(insn, 16, 1) << 11; \ + if (!Check(&S, DecodeBFLabelOperand_1_0_1_12( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 1); \ + if (!Check(&S, DecodeBFAfterTargetOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 4); \ + if (!Check(&S, DecodePredNoALOperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 402: \ + tmp = fieldname(insn, 23, 4); \ + if (!Check(&S, DecodeBFLabelOperand_0_0_0_4( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + tmp |= fieldname(insn, 11, 1) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + if (!Check(&S, DecodeBFLabelOperand_1_0_1_16( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 403: \ + tmp = fieldname(insn, 23, 4); \ + if (!Check(&S, DecodeBFLabelOperand_0_0_0_4( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 404: \ + if (!Check(&S, DecodeT2BInstruction(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 405: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 2; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 16, 4) << 6; \ + if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 406: \ + if (!Check(&S, DecodeT2LdStPre(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 407: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 408: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 9, 1) << 8; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 409: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x1000; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 410: \ + if (!Check(&S, DecodeT2LoadShift(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 411: \ + if (!Check(&S, DecodeT2LoadImm8(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 412: \ + if (!Check(&S, DecodeT2LoadT(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 413: \ + if (!Check(&S, DecodeT2LoadImm12(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 414: \ + if (!Check(&S, DecodeT2LoadLabel(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 415: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 416: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 417: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 418: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 419: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 420: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 421: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 422: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 423: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 2; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 16, 4) << 6; \ + if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 424: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 9, 1) << 8; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 425: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x1000; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 426: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 427: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 428: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 429: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 430: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 4) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 431: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 432: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 433: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 4) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 434: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 435: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 436: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 4) << 7; \ + tmp |= fieldname(insn, 24, 1) << 11; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 437: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + tmp |= fieldname(insn, 24, 1) << 6; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 438: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + tmp |= fieldname(insn, 24, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 439: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 6) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 440: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 20, 2) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 441: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 7, 1) << 2; \ + tmp |= fieldname(insn, 20, 3) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 442: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRPairnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 6) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 443: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRPairnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 20, 2) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 444: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRPairnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 7, 1) << 2; \ + tmp |= fieldname(insn, 20, 3) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 445: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 4) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 446: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 447: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 448: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 4) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 449: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 450: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 451: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 4) << 7; \ + tmp |= fieldname(insn, 24, 1) << 11; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 452: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + tmp |= fieldname(insn, 24, 1) << 6; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 453: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeMQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + tmp |= fieldname(insn, 24, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 454: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 6) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 455: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 20, 2) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 456: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 7, 1) << 2; \ + tmp |= fieldname(insn, 20, 3) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 457: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRPairnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRPairnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 6) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 458: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRPairnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRPairnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 20, 2) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 459: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRPairnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRPairnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, \ + DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 7, 1) << 2; \ + tmp |= fieldname(insn, 20, 3) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 460: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 461: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 462: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 463: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 464: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 465: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 466: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 467: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 468: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (!Check(&S, DecodeAddrMode5FP16Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 469: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 470: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 471: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 472: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 473: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 16, 4) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 474: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 475: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 476: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 477: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 478: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 479: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 480: \ + if (!Check(&S, DecodeVMOVSRR(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 481: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 4) << 9; \ + tmp |= fieldname(insn, 22, 1) << 8; \ + if (!Check(&S, DecodeSPRRegListOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 482: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (!Check(&S, DecodeAddrMode5Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 483: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 484: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 485: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 486: \ + if (!Check(&S, DecodeVMOVRRS(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 487: \ + if (!Check(&S, DecodeVSCCLRM(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 488: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 489: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 490: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 4) << 9; \ + tmp |= fieldname(insn, 22, 1) << 8; \ + if (!Check(&S, DecodeSPRRegListOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 491: \ + if (!Check(&S, DecodeForVMRSandVMSR(MI, insn, Address, \ + Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 492: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 16, 4) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 493: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 494: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 495: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 496: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 497: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 7) << 1; \ + tmp |= fieldname(insn, 12, 4) << 8; \ + tmp |= fieldname(insn, 22, 1) << 12; \ + if (!Check(&S, DecodeDPRRegListOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 498: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 7) << 1; \ + tmp |= fieldname(insn, 12, 4) << 8; \ + if (!Check(&S, DecodeDPRRegListOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 499: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (!Check(&S, DecodeAddrMode5Operand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 500: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 501: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 502: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 503: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 7) << 1; \ + tmp |= fieldname(insn, 12, 4) << 8; \ + tmp |= fieldname(insn, 22, 1) << 12; \ + if (!Check(&S, DecodeDPRRegListOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 504: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 7) << 1; \ + tmp |= fieldname(insn, 12, 4) << 8; \ + if (!Check(&S, DecodeDPRRegListOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 505: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 16, 4) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 506: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 507: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 508: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 509: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 510: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 511: \ + if (!Check(&S, DecodeVSTRVLDR_SYSREG_0( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 512: \ + if (!Check(&S, DecodeVSTRVLDR_SYSREG_1( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 513: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 514: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 23, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 515: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 20, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 516: \ + if (!Check(&S, DecodeNEONComplexLane64Instruction( \ + MI, insn, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 517: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 518: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 23, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 519: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 20, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 520: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPR_8RegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 521: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 522: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 523: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 524: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 525: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 526: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 527: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 528: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass( \ + MI, tmp, Address, Decoder))) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + } \ + } + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ + static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address) \ + { \ + const uint8_t *Ptr = DecodeTable; \ + uint64_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + while (true) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + unsigned Start = *++Ptr; \ + unsigned Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + /* Decode the field value. */ \ + unsigned Len; \ + uint64_t Val = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + unsigned Start = *++Ptr; \ + unsigned Len = *++Ptr; \ + uint64_t FieldValue = \ + fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + unsigned PtrLen = 0; \ + uint64_t ExpectedValue = \ + decodeULEB128(++Ptr, &PtrLen); \ + Ptr += PtrLen; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + unsigned Len; \ + /* Decode the Predicate Index value. */ \ + unsigned PIdx = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + bool Pred = checkDecoderPredicate(MI, PIdx); \ + if (!Pred) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + unsigned Len; \ + /* Decode the Opcode value. */ \ + unsigned Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + bool DecodeComplete = false; \ + S = decoder(S, DecodeIdx, insn, MI, Address, \ + &DecodeComplete); \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + unsigned Len; \ + /* Decode the Opcode value. */ \ + unsigned Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + bool DecodeComplete = false; \ + S = decoder(S, DecodeIdx, insn, MI, Address, \ + &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ + } \ + case MCD_OPC_SoftFail: { \ + /* Decode the mask values. */ \ + unsigned Len; \ + uint64_t PositiveMask = \ + decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + uint64_t NegativeMask = \ + decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + bool Fail = (insn & PositiveMask) != 0 || \ + (~insn & NegativeMask) != 0; \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ + /* Bogisity detected in disassembler state machine! */ \ + } + +FieldFromInstruction(fieldFromInstruction_2, uint16_t) + DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, + uint16_t) DecodeInstruction(decodeInstruction_2, + fieldFromInstruction_2, + decodeToMCInst_2, uint16_t) + + FieldFromInstruction(fieldFromInstruction_4, uint32_t) + DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, + uint32_t) + DecodeInstruction(decodeInstruction_4, + fieldFromInstruction_4, + decodeToMCInst_4, uint32_t) diff --git a/thirdparty/capstone/arch/ARM/ARMGenInstrInfo.inc b/thirdparty/capstone/arch/ARM/ARMGenInstrInfo.inc new file mode 100644 index 0000000..6724686 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMGenInstrInfo.inc @@ -0,0 +1,13384 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + +enum { + ARM_PHI = 0, + ARM_INLINEASM = 1, + ARM_INLINEASM_BR = 2, + ARM_CFI_INSTRUCTION = 3, + ARM_EH_LABEL = 4, + ARM_GC_LABEL = 5, + ARM_ANNOTATION_LABEL = 6, + ARM_KILL = 7, + ARM_EXTRACT_SUBREG = 8, + ARM_INSERT_SUBREG = 9, + ARM_IMPLICIT_DEF = 10, + ARM_SUBREG_TO_REG = 11, + ARM_COPY_TO_REGCLASS = 12, + ARM_DBG_VALUE = 13, + ARM_DBG_VALUE_LIST = 14, + ARM_DBG_INSTR_REF = 15, + ARM_DBG_PHI = 16, + ARM_DBG_LABEL = 17, + ARM_REG_SEQUENCE = 18, + ARM_COPY = 19, + ARM_BUNDLE = 20, + ARM_LIFETIME_START = 21, + ARM_LIFETIME_END = 22, + ARM_PSEUDO_PROBE = 23, + ARM_ARITH_FENCE = 24, + ARM_STACKMAP = 25, + ARM_FENTRY_CALL = 26, + ARM_PATCHPOINT = 27, + ARM_LOAD_STACK_GUARD = 28, + ARM_PREALLOCATED_SETUP = 29, + ARM_PREALLOCATED_ARG = 30, + ARM_STATEPOINT = 31, + ARM_LOCAL_ESCAPE = 32, + ARM_FAULTING_OP = 33, + ARM_PATCHABLE_OP = 34, + ARM_PATCHABLE_FUNCTION_ENTER = 35, + ARM_PATCHABLE_RET = 36, + ARM_PATCHABLE_FUNCTION_EXIT = 37, + ARM_PATCHABLE_TAIL_CALL = 38, + ARM_PATCHABLE_EVENT_CALL = 39, + ARM_PATCHABLE_TYPED_EVENT_CALL = 40, + ARM_ICALL_BRANCH_FUNNEL = 41, + ARM_MEMBARRIER = 42, + ARM_G_ASSERT_SEXT = 43, + ARM_G_ASSERT_ZEXT = 44, + ARM_G_ASSERT_ALIGN = 45, + ARM_G_ADD = 46, + ARM_G_SUB = 47, + ARM_G_MUL = 48, + ARM_G_SDIV = 49, + ARM_G_UDIV = 50, + ARM_G_SREM = 51, + ARM_G_UREM = 52, + ARM_G_SDIVREM = 53, + ARM_G_UDIVREM = 54, + ARM_G_AND = 55, + ARM_G_OR = 56, + ARM_G_XOR = 57, + ARM_G_IMPLICIT_DEF = 58, + ARM_G_PHI = 59, + ARM_G_FRAME_INDEX = 60, + ARM_G_GLOBAL_VALUE = 61, + ARM_G_EXTRACT = 62, + ARM_G_UNMERGE_VALUES = 63, + ARM_G_INSERT = 64, + ARM_G_MERGE_VALUES = 65, + ARM_G_BUILD_VECTOR = 66, + ARM_G_BUILD_VECTOR_TRUNC = 67, + ARM_G_CONCAT_VECTORS = 68, + ARM_G_PTRTOINT = 69, + ARM_G_INTTOPTR = 70, + ARM_G_BITCAST = 71, + ARM_G_FREEZE = 72, + ARM_G_INTRINSIC_FPTRUNC_ROUND = 73, + ARM_G_INTRINSIC_TRUNC = 74, + ARM_G_INTRINSIC_ROUND = 75, + ARM_G_INTRINSIC_LRINT = 76, + ARM_G_INTRINSIC_ROUNDEVEN = 77, + ARM_G_READCYCLECOUNTER = 78, + ARM_G_LOAD = 79, + ARM_G_SEXTLOAD = 80, + ARM_G_ZEXTLOAD = 81, + ARM_G_INDEXED_LOAD = 82, + ARM_G_INDEXED_SEXTLOAD = 83, + ARM_G_INDEXED_ZEXTLOAD = 84, + ARM_G_STORE = 85, + ARM_G_INDEXED_STORE = 86, + ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87, + ARM_G_ATOMIC_CMPXCHG = 88, + ARM_G_ATOMICRMW_XCHG = 89, + ARM_G_ATOMICRMW_ADD = 90, + ARM_G_ATOMICRMW_SUB = 91, + ARM_G_ATOMICRMW_AND = 92, + ARM_G_ATOMICRMW_NAND = 93, + ARM_G_ATOMICRMW_OR = 94, + ARM_G_ATOMICRMW_XOR = 95, + ARM_G_ATOMICRMW_MAX = 96, + ARM_G_ATOMICRMW_MIN = 97, + ARM_G_ATOMICRMW_UMAX = 98, + ARM_G_ATOMICRMW_UMIN = 99, + ARM_G_ATOMICRMW_FADD = 100, + ARM_G_ATOMICRMW_FSUB = 101, + ARM_G_ATOMICRMW_FMAX = 102, + ARM_G_ATOMICRMW_FMIN = 103, + ARM_G_ATOMICRMW_UINC_WRAP = 104, + ARM_G_ATOMICRMW_UDEC_WRAP = 105, + ARM_G_FENCE = 106, + ARM_G_BRCOND = 107, + ARM_G_BRINDIRECT = 108, + ARM_G_INVOKE_REGION_START = 109, + ARM_G_INTRINSIC = 110, + ARM_G_INTRINSIC_W_SIDE_EFFECTS = 111, + ARM_G_ANYEXT = 112, + ARM_G_TRUNC = 113, + ARM_G_CONSTANT = 114, + ARM_G_FCONSTANT = 115, + ARM_G_VASTART = 116, + ARM_G_VAARG = 117, + ARM_G_SEXT = 118, + ARM_G_SEXT_INREG = 119, + ARM_G_ZEXT = 120, + ARM_G_SHL = 121, + ARM_G_LSHR = 122, + ARM_G_ASHR = 123, + ARM_G_FSHL = 124, + ARM_G_FSHR = 125, + ARM_G_ROTR = 126, + ARM_G_ROTL = 127, + ARM_G_ICMP = 128, + ARM_G_FCMP = 129, + ARM_G_SELECT = 130, + ARM_G_UADDO = 131, + ARM_G_UADDE = 132, + ARM_G_USUBO = 133, + ARM_G_USUBE = 134, + ARM_G_SADDO = 135, + ARM_G_SADDE = 136, + ARM_G_SSUBO = 137, + ARM_G_SSUBE = 138, + ARM_G_UMULO = 139, + ARM_G_SMULO = 140, + ARM_G_UMULH = 141, + ARM_G_SMULH = 142, + ARM_G_UADDSAT = 143, + ARM_G_SADDSAT = 144, + ARM_G_USUBSAT = 145, + ARM_G_SSUBSAT = 146, + ARM_G_USHLSAT = 147, + ARM_G_SSHLSAT = 148, + ARM_G_SMULFIX = 149, + ARM_G_UMULFIX = 150, + ARM_G_SMULFIXSAT = 151, + ARM_G_UMULFIXSAT = 152, + ARM_G_SDIVFIX = 153, + ARM_G_UDIVFIX = 154, + ARM_G_SDIVFIXSAT = 155, + ARM_G_UDIVFIXSAT = 156, + ARM_G_FADD = 157, + ARM_G_FSUB = 158, + ARM_G_FMUL = 159, + ARM_G_FMA = 160, + ARM_G_FMAD = 161, + ARM_G_FDIV = 162, + ARM_G_FREM = 163, + ARM_G_FPOW = 164, + ARM_G_FPOWI = 165, + ARM_G_FEXP = 166, + ARM_G_FEXP2 = 167, + ARM_G_FLOG = 168, + ARM_G_FLOG2 = 169, + ARM_G_FLOG10 = 170, + ARM_G_FNEG = 171, + ARM_G_FPEXT = 172, + ARM_G_FPTRUNC = 173, + ARM_G_FPTOSI = 174, + ARM_G_FPTOUI = 175, + ARM_G_SITOFP = 176, + ARM_G_UITOFP = 177, + ARM_G_FABS = 178, + ARM_G_FCOPYSIGN = 179, + ARM_G_IS_FPCLASS = 180, + ARM_G_FCANONICALIZE = 181, + ARM_G_FMINNUM = 182, + ARM_G_FMAXNUM = 183, + ARM_G_FMINNUM_IEEE = 184, + ARM_G_FMAXNUM_IEEE = 185, + ARM_G_FMINIMUM = 186, + ARM_G_FMAXIMUM = 187, + ARM_G_PTR_ADD = 188, + ARM_G_PTRMASK = 189, + ARM_G_SMIN = 190, + ARM_G_SMAX = 191, + ARM_G_UMIN = 192, + ARM_G_UMAX = 193, + ARM_G_ABS = 194, + ARM_G_LROUND = 195, + ARM_G_LLROUND = 196, + ARM_G_BR = 197, + ARM_G_BRJT = 198, + ARM_G_INSERT_VECTOR_ELT = 199, + ARM_G_EXTRACT_VECTOR_ELT = 200, + ARM_G_SHUFFLE_VECTOR = 201, + ARM_G_CTTZ = 202, + ARM_G_CTTZ_ZERO_UNDEF = 203, + ARM_G_CTLZ = 204, + ARM_G_CTLZ_ZERO_UNDEF = 205, + ARM_G_CTPOP = 206, + ARM_G_BSWAP = 207, + ARM_G_BITREVERSE = 208, + ARM_G_FCEIL = 209, + ARM_G_FCOS = 210, + ARM_G_FSIN = 211, + ARM_G_FSQRT = 212, + ARM_G_FFLOOR = 213, + ARM_G_FRINT = 214, + ARM_G_FNEARBYINT = 215, + ARM_G_ADDRSPACE_CAST = 216, + ARM_G_BLOCK_ADDR = 217, + ARM_G_JUMP_TABLE = 218, + ARM_G_DYN_STACKALLOC = 219, + ARM_G_STRICT_FADD = 220, + ARM_G_STRICT_FSUB = 221, + ARM_G_STRICT_FMUL = 222, + ARM_G_STRICT_FDIV = 223, + ARM_G_STRICT_FREM = 224, + ARM_G_STRICT_FMA = 225, + ARM_G_STRICT_FSQRT = 226, + ARM_G_READ_REGISTER = 227, + ARM_G_WRITE_REGISTER = 228, + ARM_G_MEMCPY = 229, + ARM_G_MEMCPY_INLINE = 230, + ARM_G_MEMMOVE = 231, + ARM_G_MEMSET = 232, + ARM_G_BZERO = 233, + ARM_G_VECREDUCE_SEQ_FADD = 234, + ARM_G_VECREDUCE_SEQ_FMUL = 235, + ARM_G_VECREDUCE_FADD = 236, + ARM_G_VECREDUCE_FMUL = 237, + ARM_G_VECREDUCE_FMAX = 238, + ARM_G_VECREDUCE_FMIN = 239, + ARM_G_VECREDUCE_ADD = 240, + ARM_G_VECREDUCE_MUL = 241, + ARM_G_VECREDUCE_AND = 242, + ARM_G_VECREDUCE_OR = 243, + ARM_G_VECREDUCE_XOR = 244, + ARM_G_VECREDUCE_SMAX = 245, + ARM_G_VECREDUCE_SMIN = 246, + ARM_G_VECREDUCE_UMAX = 247, + ARM_G_VECREDUCE_UMIN = 248, + ARM_G_SBFX = 249, + ARM_G_UBFX = 250, + ARM_ABS = 251, + ARM_ADDSri = 252, + ARM_ADDSrr = 253, + ARM_ADDSrsi = 254, + ARM_ADDSrsr = 255, + ARM_ADJCALLSTACKDOWN = 256, + ARM_ADJCALLSTACKUP = 257, + ARM_ASRi = 258, + ARM_ASRr = 259, + ARM_B = 260, + ARM_BCCZi64 = 261, + ARM_BCCi64 = 262, + ARM_BLX_noip = 263, + ARM_BLX_pred_noip = 264, + ARM_BL_PUSHLR = 265, + ARM_BMOVPCB_CALL = 266, + ARM_BMOVPCRX_CALL = 267, + ARM_BR_JTadd = 268, + ARM_BR_JTm_i12 = 269, + ARM_BR_JTm_rs = 270, + ARM_BR_JTr = 271, + ARM_BX_CALL = 272, + ARM_CMP_SWAP_16 = 273, + ARM_CMP_SWAP_32 = 274, + ARM_CMP_SWAP_64 = 275, + ARM_CMP_SWAP_8 = 276, + ARM_CONSTPOOL_ENTRY = 277, + ARM_COPY_STRUCT_BYVAL_I32 = 278, + ARM_ITasm = 279, + ARM_Int_eh_sjlj_dispatchsetup = 280, + ARM_Int_eh_sjlj_longjmp = 281, + ARM_Int_eh_sjlj_setjmp = 282, + ARM_Int_eh_sjlj_setjmp_nofp = 283, + ARM_Int_eh_sjlj_setup_dispatch = 284, + ARM_JUMPTABLE_ADDRS = 285, + ARM_JUMPTABLE_INSTS = 286, + ARM_JUMPTABLE_TBB = 287, + ARM_JUMPTABLE_TBH = 288, + ARM_LDMIA_RET = 289, + ARM_LDRBT_POST = 290, + ARM_LDRConstPool = 291, + ARM_LDRHTii = 292, + ARM_LDRLIT_ga_abs = 293, + ARM_LDRLIT_ga_pcrel = 294, + ARM_LDRLIT_ga_pcrel_ldr = 295, + ARM_LDRSBTii = 296, + ARM_LDRSHTii = 297, + ARM_LDRT_POST = 298, + ARM_LEApcrel = 299, + ARM_LEApcrelJT = 300, + ARM_LOADDUAL = 301, + ARM_LSLi = 302, + ARM_LSLr = 303, + ARM_LSRi = 304, + ARM_LSRr = 305, + ARM_MEMCPY = 306, + ARM_MLAv5 = 307, + ARM_MOVCCi = 308, + ARM_MOVCCi16 = 309, + ARM_MOVCCi32imm = 310, + ARM_MOVCCr = 311, + ARM_MOVCCsi = 312, + ARM_MOVCCsr = 313, + ARM_MOVPCRX = 314, + ARM_MOVTi16_ga_pcrel = 315, + ARM_MOV_ga_pcrel = 316, + ARM_MOV_ga_pcrel_ldr = 317, + ARM_MOVi16_ga_pcrel = 318, + ARM_MOVi32imm = 319, + ARM_MOVsra_flag = 320, + ARM_MOVsrl_flag = 321, + ARM_MQPRCopy = 322, + ARM_MQQPRLoad = 323, + ARM_MQQPRStore = 324, + ARM_MQQQQPRLoad = 325, + ARM_MQQQQPRStore = 326, + ARM_MULv5 = 327, + ARM_MVE_MEMCPYLOOPINST = 328, + ARM_MVE_MEMSETLOOPINST = 329, + ARM_MVNCCi = 330, + ARM_PICADD = 331, + ARM_PICLDR = 332, + ARM_PICLDRB = 333, + ARM_PICLDRH = 334, + ARM_PICLDRSB = 335, + ARM_PICLDRSH = 336, + ARM_PICSTR = 337, + ARM_PICSTRB = 338, + ARM_PICSTRH = 339, + ARM_RORi = 340, + ARM_RORr = 341, + ARM_RRX = 342, + ARM_RRXi = 343, + ARM_RSBSri = 344, + ARM_RSBSrsi = 345, + ARM_RSBSrsr = 346, + ARM_SEH_EpilogEnd = 347, + ARM_SEH_EpilogStart = 348, + ARM_SEH_Nop = 349, + ARM_SEH_Nop_Ret = 350, + ARM_SEH_PrologEnd = 351, + ARM_SEH_SaveFRegs = 352, + ARM_SEH_SaveLR = 353, + ARM_SEH_SaveRegs = 354, + ARM_SEH_SaveRegs_Ret = 355, + ARM_SEH_SaveSP = 356, + ARM_SEH_StackAlloc = 357, + ARM_SMLALv5 = 358, + ARM_SMULLv5 = 359, + ARM_SPACE = 360, + ARM_STOREDUAL = 361, + ARM_STRBT_POST = 362, + ARM_STRBi_preidx = 363, + ARM_STRBr_preidx = 364, + ARM_STRH_preidx = 365, + ARM_STRT_POST = 366, + ARM_STRi_preidx = 367, + ARM_STRr_preidx = 368, + ARM_SUBS_PC_LR = 369, + ARM_SUBSri = 370, + ARM_SUBSrr = 371, + ARM_SUBSrsi = 372, + ARM_SUBSrsr = 373, + ARM_SpeculationBarrierISBDSBEndBB = 374, + ARM_SpeculationBarrierSBEndBB = 375, + ARM_TAILJMPd = 376, + ARM_TAILJMPr = 377, + ARM_TAILJMPr4 = 378, + ARM_TCRETURNdi = 379, + ARM_TCRETURNri = 380, + ARM_TPsoft = 381, + ARM_UMLALv5 = 382, + ARM_UMULLv5 = 383, + ARM_VLD1LNdAsm_16 = 384, + ARM_VLD1LNdAsm_32 = 385, + ARM_VLD1LNdAsm_8 = 386, + ARM_VLD1LNdWB_fixed_Asm_16 = 387, + ARM_VLD1LNdWB_fixed_Asm_32 = 388, + ARM_VLD1LNdWB_fixed_Asm_8 = 389, + ARM_VLD1LNdWB_register_Asm_16 = 390, + ARM_VLD1LNdWB_register_Asm_32 = 391, + ARM_VLD1LNdWB_register_Asm_8 = 392, + ARM_VLD2LNdAsm_16 = 393, + ARM_VLD2LNdAsm_32 = 394, + ARM_VLD2LNdAsm_8 = 395, + ARM_VLD2LNdWB_fixed_Asm_16 = 396, + ARM_VLD2LNdWB_fixed_Asm_32 = 397, + ARM_VLD2LNdWB_fixed_Asm_8 = 398, + ARM_VLD2LNdWB_register_Asm_16 = 399, + ARM_VLD2LNdWB_register_Asm_32 = 400, + ARM_VLD2LNdWB_register_Asm_8 = 401, + ARM_VLD2LNqAsm_16 = 402, + ARM_VLD2LNqAsm_32 = 403, + ARM_VLD2LNqWB_fixed_Asm_16 = 404, + ARM_VLD2LNqWB_fixed_Asm_32 = 405, + ARM_VLD2LNqWB_register_Asm_16 = 406, + ARM_VLD2LNqWB_register_Asm_32 = 407, + ARM_VLD3DUPdAsm_16 = 408, + ARM_VLD3DUPdAsm_32 = 409, + ARM_VLD3DUPdAsm_8 = 410, + ARM_VLD3DUPdWB_fixed_Asm_16 = 411, + ARM_VLD3DUPdWB_fixed_Asm_32 = 412, + ARM_VLD3DUPdWB_fixed_Asm_8 = 413, + ARM_VLD3DUPdWB_register_Asm_16 = 414, + ARM_VLD3DUPdWB_register_Asm_32 = 415, + ARM_VLD3DUPdWB_register_Asm_8 = 416, + ARM_VLD3DUPqAsm_16 = 417, + ARM_VLD3DUPqAsm_32 = 418, + ARM_VLD3DUPqAsm_8 = 419, + ARM_VLD3DUPqWB_fixed_Asm_16 = 420, + ARM_VLD3DUPqWB_fixed_Asm_32 = 421, + ARM_VLD3DUPqWB_fixed_Asm_8 = 422, + ARM_VLD3DUPqWB_register_Asm_16 = 423, + ARM_VLD3DUPqWB_register_Asm_32 = 424, + ARM_VLD3DUPqWB_register_Asm_8 = 425, + ARM_VLD3LNdAsm_16 = 426, + ARM_VLD3LNdAsm_32 = 427, + ARM_VLD3LNdAsm_8 = 428, + ARM_VLD3LNdWB_fixed_Asm_16 = 429, + ARM_VLD3LNdWB_fixed_Asm_32 = 430, + ARM_VLD3LNdWB_fixed_Asm_8 = 431, + ARM_VLD3LNdWB_register_Asm_16 = 432, + ARM_VLD3LNdWB_register_Asm_32 = 433, + ARM_VLD3LNdWB_register_Asm_8 = 434, + ARM_VLD3LNqAsm_16 = 435, + ARM_VLD3LNqAsm_32 = 436, + ARM_VLD3LNqWB_fixed_Asm_16 = 437, + ARM_VLD3LNqWB_fixed_Asm_32 = 438, + ARM_VLD3LNqWB_register_Asm_16 = 439, + ARM_VLD3LNqWB_register_Asm_32 = 440, + ARM_VLD3dAsm_16 = 441, + ARM_VLD3dAsm_32 = 442, + ARM_VLD3dAsm_8 = 443, + ARM_VLD3dWB_fixed_Asm_16 = 444, + ARM_VLD3dWB_fixed_Asm_32 = 445, + ARM_VLD3dWB_fixed_Asm_8 = 446, + ARM_VLD3dWB_register_Asm_16 = 447, + ARM_VLD3dWB_register_Asm_32 = 448, + ARM_VLD3dWB_register_Asm_8 = 449, + ARM_VLD3qAsm_16 = 450, + ARM_VLD3qAsm_32 = 451, + ARM_VLD3qAsm_8 = 452, + ARM_VLD3qWB_fixed_Asm_16 = 453, + ARM_VLD3qWB_fixed_Asm_32 = 454, + ARM_VLD3qWB_fixed_Asm_8 = 455, + ARM_VLD3qWB_register_Asm_16 = 456, + ARM_VLD3qWB_register_Asm_32 = 457, + ARM_VLD3qWB_register_Asm_8 = 458, + ARM_VLD4DUPdAsm_16 = 459, + ARM_VLD4DUPdAsm_32 = 460, + ARM_VLD4DUPdAsm_8 = 461, + ARM_VLD4DUPdWB_fixed_Asm_16 = 462, + ARM_VLD4DUPdWB_fixed_Asm_32 = 463, + ARM_VLD4DUPdWB_fixed_Asm_8 = 464, + ARM_VLD4DUPdWB_register_Asm_16 = 465, + ARM_VLD4DUPdWB_register_Asm_32 = 466, + ARM_VLD4DUPdWB_register_Asm_8 = 467, + ARM_VLD4DUPqAsm_16 = 468, + ARM_VLD4DUPqAsm_32 = 469, + ARM_VLD4DUPqAsm_8 = 470, + ARM_VLD4DUPqWB_fixed_Asm_16 = 471, + ARM_VLD4DUPqWB_fixed_Asm_32 = 472, + ARM_VLD4DUPqWB_fixed_Asm_8 = 473, + ARM_VLD4DUPqWB_register_Asm_16 = 474, + ARM_VLD4DUPqWB_register_Asm_32 = 475, + ARM_VLD4DUPqWB_register_Asm_8 = 476, + ARM_VLD4LNdAsm_16 = 477, + ARM_VLD4LNdAsm_32 = 478, + ARM_VLD4LNdAsm_8 = 479, + ARM_VLD4LNdWB_fixed_Asm_16 = 480, + ARM_VLD4LNdWB_fixed_Asm_32 = 481, + ARM_VLD4LNdWB_fixed_Asm_8 = 482, + ARM_VLD4LNdWB_register_Asm_16 = 483, + ARM_VLD4LNdWB_register_Asm_32 = 484, + ARM_VLD4LNdWB_register_Asm_8 = 485, + ARM_VLD4LNqAsm_16 = 486, + ARM_VLD4LNqAsm_32 = 487, + ARM_VLD4LNqWB_fixed_Asm_16 = 488, + ARM_VLD4LNqWB_fixed_Asm_32 = 489, + ARM_VLD4LNqWB_register_Asm_16 = 490, + ARM_VLD4LNqWB_register_Asm_32 = 491, + ARM_VLD4dAsm_16 = 492, + ARM_VLD4dAsm_32 = 493, + ARM_VLD4dAsm_8 = 494, + ARM_VLD4dWB_fixed_Asm_16 = 495, + ARM_VLD4dWB_fixed_Asm_32 = 496, + ARM_VLD4dWB_fixed_Asm_8 = 497, + ARM_VLD4dWB_register_Asm_16 = 498, + ARM_VLD4dWB_register_Asm_32 = 499, + ARM_VLD4dWB_register_Asm_8 = 500, + ARM_VLD4qAsm_16 = 501, + ARM_VLD4qAsm_32 = 502, + ARM_VLD4qAsm_8 = 503, + ARM_VLD4qWB_fixed_Asm_16 = 504, + ARM_VLD4qWB_fixed_Asm_32 = 505, + ARM_VLD4qWB_fixed_Asm_8 = 506, + ARM_VLD4qWB_register_Asm_16 = 507, + ARM_VLD4qWB_register_Asm_32 = 508, + ARM_VLD4qWB_register_Asm_8 = 509, + ARM_VMOVD0 = 510, + ARM_VMOVDcc = 511, + ARM_VMOVHcc = 512, + ARM_VMOVQ0 = 513, + ARM_VMOVScc = 514, + ARM_VST1LNdAsm_16 = 515, + ARM_VST1LNdAsm_32 = 516, + ARM_VST1LNdAsm_8 = 517, + ARM_VST1LNdWB_fixed_Asm_16 = 518, + ARM_VST1LNdWB_fixed_Asm_32 = 519, + ARM_VST1LNdWB_fixed_Asm_8 = 520, + ARM_VST1LNdWB_register_Asm_16 = 521, + ARM_VST1LNdWB_register_Asm_32 = 522, + ARM_VST1LNdWB_register_Asm_8 = 523, + ARM_VST2LNdAsm_16 = 524, + ARM_VST2LNdAsm_32 = 525, + ARM_VST2LNdAsm_8 = 526, + ARM_VST2LNdWB_fixed_Asm_16 = 527, + ARM_VST2LNdWB_fixed_Asm_32 = 528, + ARM_VST2LNdWB_fixed_Asm_8 = 529, + ARM_VST2LNdWB_register_Asm_16 = 530, + ARM_VST2LNdWB_register_Asm_32 = 531, + ARM_VST2LNdWB_register_Asm_8 = 532, + ARM_VST2LNqAsm_16 = 533, + ARM_VST2LNqAsm_32 = 534, + ARM_VST2LNqWB_fixed_Asm_16 = 535, + ARM_VST2LNqWB_fixed_Asm_32 = 536, + ARM_VST2LNqWB_register_Asm_16 = 537, + ARM_VST2LNqWB_register_Asm_32 = 538, + ARM_VST3LNdAsm_16 = 539, + ARM_VST3LNdAsm_32 = 540, + ARM_VST3LNdAsm_8 = 541, + ARM_VST3LNdWB_fixed_Asm_16 = 542, + ARM_VST3LNdWB_fixed_Asm_32 = 543, + ARM_VST3LNdWB_fixed_Asm_8 = 544, + ARM_VST3LNdWB_register_Asm_16 = 545, + ARM_VST3LNdWB_register_Asm_32 = 546, + ARM_VST3LNdWB_register_Asm_8 = 547, + ARM_VST3LNqAsm_16 = 548, + ARM_VST3LNqAsm_32 = 549, + ARM_VST3LNqWB_fixed_Asm_16 = 550, + ARM_VST3LNqWB_fixed_Asm_32 = 551, + ARM_VST3LNqWB_register_Asm_16 = 552, + ARM_VST3LNqWB_register_Asm_32 = 553, + ARM_VST3dAsm_16 = 554, + ARM_VST3dAsm_32 = 555, + ARM_VST3dAsm_8 = 556, + ARM_VST3dWB_fixed_Asm_16 = 557, + ARM_VST3dWB_fixed_Asm_32 = 558, + ARM_VST3dWB_fixed_Asm_8 = 559, + ARM_VST3dWB_register_Asm_16 = 560, + ARM_VST3dWB_register_Asm_32 = 561, + ARM_VST3dWB_register_Asm_8 = 562, + ARM_VST3qAsm_16 = 563, + ARM_VST3qAsm_32 = 564, + ARM_VST3qAsm_8 = 565, + ARM_VST3qWB_fixed_Asm_16 = 566, + ARM_VST3qWB_fixed_Asm_32 = 567, + ARM_VST3qWB_fixed_Asm_8 = 568, + ARM_VST3qWB_register_Asm_16 = 569, + ARM_VST3qWB_register_Asm_32 = 570, + ARM_VST3qWB_register_Asm_8 = 571, + ARM_VST4LNdAsm_16 = 572, + ARM_VST4LNdAsm_32 = 573, + ARM_VST4LNdAsm_8 = 574, + ARM_VST4LNdWB_fixed_Asm_16 = 575, + ARM_VST4LNdWB_fixed_Asm_32 = 576, + ARM_VST4LNdWB_fixed_Asm_8 = 577, + ARM_VST4LNdWB_register_Asm_16 = 578, + ARM_VST4LNdWB_register_Asm_32 = 579, + ARM_VST4LNdWB_register_Asm_8 = 580, + ARM_VST4LNqAsm_16 = 581, + ARM_VST4LNqAsm_32 = 582, + ARM_VST4LNqWB_fixed_Asm_16 = 583, + ARM_VST4LNqWB_fixed_Asm_32 = 584, + ARM_VST4LNqWB_register_Asm_16 = 585, + ARM_VST4LNqWB_register_Asm_32 = 586, + ARM_VST4dAsm_16 = 587, + ARM_VST4dAsm_32 = 588, + ARM_VST4dAsm_8 = 589, + ARM_VST4dWB_fixed_Asm_16 = 590, + ARM_VST4dWB_fixed_Asm_32 = 591, + ARM_VST4dWB_fixed_Asm_8 = 592, + ARM_VST4dWB_register_Asm_16 = 593, + ARM_VST4dWB_register_Asm_32 = 594, + ARM_VST4dWB_register_Asm_8 = 595, + ARM_VST4qAsm_16 = 596, + ARM_VST4qAsm_32 = 597, + ARM_VST4qAsm_8 = 598, + ARM_VST4qWB_fixed_Asm_16 = 599, + ARM_VST4qWB_fixed_Asm_32 = 600, + ARM_VST4qWB_fixed_Asm_8 = 601, + ARM_VST4qWB_register_Asm_16 = 602, + ARM_VST4qWB_register_Asm_32 = 603, + ARM_VST4qWB_register_Asm_8 = 604, + ARM_WIN__CHKSTK = 605, + ARM_WIN__DBZCHK = 606, + ARM_t2ABS = 607, + ARM_t2ADDSri = 608, + ARM_t2ADDSrr = 609, + ARM_t2ADDSrs = 610, + ARM_t2BF_LabelPseudo = 611, + ARM_t2BR_JT = 612, + ARM_t2CALL_BTI = 613, + ARM_t2DoLoopStart = 614, + ARM_t2DoLoopStartTP = 615, + ARM_t2LDMIA_RET = 616, + ARM_t2LDRBpcrel = 617, + ARM_t2LDRConstPool = 618, + ARM_t2LDRHpcrel = 619, + ARM_t2LDRLIT_ga_pcrel = 620, + ARM_t2LDRSBpcrel = 621, + ARM_t2LDRSHpcrel = 622, + ARM_t2LDR_POST_imm = 623, + ARM_t2LDR_PRE_imm = 624, + ARM_t2LDRpci_pic = 625, + ARM_t2LDRpcrel = 626, + ARM_t2LEApcrel = 627, + ARM_t2LEApcrelJT = 628, + ARM_t2LoopDec = 629, + ARM_t2LoopEnd = 630, + ARM_t2LoopEndDec = 631, + ARM_t2MOVCCasr = 632, + ARM_t2MOVCCi = 633, + ARM_t2MOVCCi16 = 634, + ARM_t2MOVCCi32imm = 635, + ARM_t2MOVCClsl = 636, + ARM_t2MOVCClsr = 637, + ARM_t2MOVCCr = 638, + ARM_t2MOVCCror = 639, + ARM_t2MOVSsi = 640, + ARM_t2MOVSsr = 641, + ARM_t2MOVTi16_ga_pcrel = 642, + ARM_t2MOV_ga_pcrel = 643, + ARM_t2MOVi16_ga_pcrel = 644, + ARM_t2MOVi32imm = 645, + ARM_t2MOVsi = 646, + ARM_t2MOVsr = 647, + ARM_t2MVNCCi = 648, + ARM_t2RSBSri = 649, + ARM_t2RSBSrs = 650, + ARM_t2STRB_preidx = 651, + ARM_t2STRH_preidx = 652, + ARM_t2STR_POST_imm = 653, + ARM_t2STR_PRE_imm = 654, + ARM_t2STR_preidx = 655, + ARM_t2SUBSri = 656, + ARM_t2SUBSrr = 657, + ARM_t2SUBSrs = 658, + ARM_t2SpeculationBarrierISBDSBEndBB = 659, + ARM_t2SpeculationBarrierSBEndBB = 660, + ARM_t2TBB_JT = 661, + ARM_t2TBH_JT = 662, + ARM_t2WhileLoopSetup = 663, + ARM_t2WhileLoopStart = 664, + ARM_t2WhileLoopStartLR = 665, + ARM_t2WhileLoopStartTP = 666, + ARM_tADCS = 667, + ARM_tADDSi3 = 668, + ARM_tADDSi8 = 669, + ARM_tADDSrr = 670, + ARM_tADDframe = 671, + ARM_tADJCALLSTACKDOWN = 672, + ARM_tADJCALLSTACKUP = 673, + ARM_tBLXNS_CALL = 674, + ARM_tBLXr_noip = 675, + ARM_tBL_PUSHLR = 676, + ARM_tBRIND = 677, + ARM_tBR_JTr = 678, + ARM_tBXNS_RET = 679, + ARM_tBX_CALL = 680, + ARM_tBX_RET = 681, + ARM_tBX_RET_vararg = 682, + ARM_tBfar = 683, + ARM_tCMP_SWAP_16 = 684, + ARM_tCMP_SWAP_32 = 685, + ARM_tCMP_SWAP_8 = 686, + ARM_tLDMIA_UPD = 687, + ARM_tLDRConstPool = 688, + ARM_tLDRLIT_ga_abs = 689, + ARM_tLDRLIT_ga_pcrel = 690, + ARM_tLDR_postidx = 691, + ARM_tLDRpci_pic = 692, + ARM_tLEApcrel = 693, + ARM_tLEApcrelJT = 694, + ARM_tLSLSri = 695, + ARM_tMOVCCr_pseudo = 696, + ARM_tPOP_RET = 697, + ARM_tRSBS = 698, + ARM_tSBCS = 699, + ARM_tSUBSi3 = 700, + ARM_tSUBSi8 = 701, + ARM_tSUBSrr = 702, + ARM_tTAILJMPd = 703, + ARM_tTAILJMPdND = 704, + ARM_tTAILJMPr = 705, + ARM_tTBB_JT = 706, + ARM_tTBH_JT = 707, + ARM_tTPsoft = 708, + ARM_ADCri = 709, + ARM_ADCrr = 710, + ARM_ADCrsi = 711, + ARM_ADCrsr = 712, + ARM_ADDri = 713, + ARM_ADDrr = 714, + ARM_ADDrsi = 715, + ARM_ADDrsr = 716, + ARM_ADR = 717, + ARM_AESD = 718, + ARM_AESE = 719, + ARM_AESIMC = 720, + ARM_AESMC = 721, + ARM_ANDri = 722, + ARM_ANDrr = 723, + ARM_ANDrsi = 724, + ARM_ANDrsr = 725, + ARM_BF16VDOTI_VDOTD = 726, + ARM_BF16VDOTI_VDOTQ = 727, + ARM_BF16VDOTS_VDOTD = 728, + ARM_BF16VDOTS_VDOTQ = 729, + ARM_BF16_VCVT = 730, + ARM_BF16_VCVTB = 731, + ARM_BF16_VCVTT = 732, + ARM_BFC = 733, + ARM_BFI = 734, + ARM_BICri = 735, + ARM_BICrr = 736, + ARM_BICrsi = 737, + ARM_BICrsr = 738, + ARM_BKPT = 739, + ARM_BL = 740, + ARM_BLX = 741, + ARM_BLX_pred = 742, + ARM_BLXi = 743, + ARM_BL_pred = 744, + ARM_BX = 745, + ARM_BXJ = 746, + ARM_BX_RET = 747, + ARM_BX_pred = 748, + ARM_Bcc = 749, + ARM_CDE_CX1 = 750, + ARM_CDE_CX1A = 751, + ARM_CDE_CX1D = 752, + ARM_CDE_CX1DA = 753, + ARM_CDE_CX2 = 754, + ARM_CDE_CX2A = 755, + ARM_CDE_CX2D = 756, + ARM_CDE_CX2DA = 757, + ARM_CDE_CX3 = 758, + ARM_CDE_CX3A = 759, + ARM_CDE_CX3D = 760, + ARM_CDE_CX3DA = 761, + ARM_CDE_VCX1A_fpdp = 762, + ARM_CDE_VCX1A_fpsp = 763, + ARM_CDE_VCX1A_vec = 764, + ARM_CDE_VCX1_fpdp = 765, + ARM_CDE_VCX1_fpsp = 766, + ARM_CDE_VCX1_vec = 767, + ARM_CDE_VCX2A_fpdp = 768, + ARM_CDE_VCX2A_fpsp = 769, + ARM_CDE_VCX2A_vec = 770, + ARM_CDE_VCX2_fpdp = 771, + ARM_CDE_VCX2_fpsp = 772, + ARM_CDE_VCX2_vec = 773, + ARM_CDE_VCX3A_fpdp = 774, + ARM_CDE_VCX3A_fpsp = 775, + ARM_CDE_VCX3A_vec = 776, + ARM_CDE_VCX3_fpdp = 777, + ARM_CDE_VCX3_fpsp = 778, + ARM_CDE_VCX3_vec = 779, + ARM_CDP = 780, + ARM_CDP2 = 781, + ARM_CLREX = 782, + ARM_CLZ = 783, + ARM_CMNri = 784, + ARM_CMNzrr = 785, + ARM_CMNzrsi = 786, + ARM_CMNzrsr = 787, + ARM_CMPri = 788, + ARM_CMPrr = 789, + ARM_CMPrsi = 790, + ARM_CMPrsr = 791, + ARM_CPS1p = 792, + ARM_CPS2p = 793, + ARM_CPS3p = 794, + ARM_CRC32B = 795, + ARM_CRC32CB = 796, + ARM_CRC32CH = 797, + ARM_CRC32CW = 798, + ARM_CRC32H = 799, + ARM_CRC32W = 800, + ARM_DBG = 801, + ARM_DMB = 802, + ARM_DSB = 803, + ARM_EORri = 804, + ARM_EORrr = 805, + ARM_EORrsi = 806, + ARM_EORrsr = 807, + ARM_ERET = 808, + ARM_FCONSTD = 809, + ARM_FCONSTH = 810, + ARM_FCONSTS = 811, + ARM_FLDMXDB_UPD = 812, + ARM_FLDMXIA = 813, + ARM_FLDMXIA_UPD = 814, + ARM_FMSTAT = 815, + ARM_FSTMXDB_UPD = 816, + ARM_FSTMXIA = 817, + ARM_FSTMXIA_UPD = 818, + ARM_HINT = 819, + ARM_HLT = 820, + ARM_HVC = 821, + ARM_ISB = 822, + ARM_LDA = 823, + ARM_LDAB = 824, + ARM_LDAEX = 825, + ARM_LDAEXB = 826, + ARM_LDAEXD = 827, + ARM_LDAEXH = 828, + ARM_LDAH = 829, + ARM_LDC2L_OFFSET = 830, + ARM_LDC2L_OPTION = 831, + ARM_LDC2L_POST = 832, + ARM_LDC2L_PRE = 833, + ARM_LDC2_OFFSET = 834, + ARM_LDC2_OPTION = 835, + ARM_LDC2_POST = 836, + ARM_LDC2_PRE = 837, + ARM_LDCL_OFFSET = 838, + ARM_LDCL_OPTION = 839, + ARM_LDCL_POST = 840, + ARM_LDCL_PRE = 841, + ARM_LDC_OFFSET = 842, + ARM_LDC_OPTION = 843, + ARM_LDC_POST = 844, + ARM_LDC_PRE = 845, + ARM_LDMDA = 846, + ARM_LDMDA_UPD = 847, + ARM_LDMDB = 848, + ARM_LDMDB_UPD = 849, + ARM_LDMIA = 850, + ARM_LDMIA_UPD = 851, + ARM_LDMIB = 852, + ARM_LDMIB_UPD = 853, + ARM_LDRBT_POST_IMM = 854, + ARM_LDRBT_POST_REG = 855, + ARM_LDRB_POST_IMM = 856, + ARM_LDRB_POST_REG = 857, + ARM_LDRB_PRE_IMM = 858, + ARM_LDRB_PRE_REG = 859, + ARM_LDRBi12 = 860, + ARM_LDRBrs = 861, + ARM_LDRD = 862, + ARM_LDRD_POST = 863, + ARM_LDRD_PRE = 864, + ARM_LDREX = 865, + ARM_LDREXB = 866, + ARM_LDREXD = 867, + ARM_LDREXH = 868, + ARM_LDRH = 869, + ARM_LDRHTi = 870, + ARM_LDRHTr = 871, + ARM_LDRH_POST = 872, + ARM_LDRH_PRE = 873, + ARM_LDRSB = 874, + ARM_LDRSBTi = 875, + ARM_LDRSBTr = 876, + ARM_LDRSB_POST = 877, + ARM_LDRSB_PRE = 878, + ARM_LDRSH = 879, + ARM_LDRSHTi = 880, + ARM_LDRSHTr = 881, + ARM_LDRSH_POST = 882, + ARM_LDRSH_PRE = 883, + ARM_LDRT_POST_IMM = 884, + ARM_LDRT_POST_REG = 885, + ARM_LDR_POST_IMM = 886, + ARM_LDR_POST_REG = 887, + ARM_LDR_PRE_IMM = 888, + ARM_LDR_PRE_REG = 889, + ARM_LDRcp = 890, + ARM_LDRi12 = 891, + ARM_LDRrs = 892, + ARM_MCR = 893, + ARM_MCR2 = 894, + ARM_MCRR = 895, + ARM_MCRR2 = 896, + ARM_MLA = 897, + ARM_MLS = 898, + ARM_MOVPCLR = 899, + ARM_MOVTi16 = 900, + ARM_MOVi = 901, + ARM_MOVi16 = 902, + ARM_MOVr = 903, + ARM_MOVr_TC = 904, + ARM_MOVsi = 905, + ARM_MOVsr = 906, + ARM_MRC = 907, + ARM_MRC2 = 908, + ARM_MRRC = 909, + ARM_MRRC2 = 910, + ARM_MRS = 911, + ARM_MRSbanked = 912, + ARM_MRSsys = 913, + ARM_MSR = 914, + ARM_MSRbanked = 915, + ARM_MSRi = 916, + ARM_MUL = 917, + ARM_MVE_ASRLi = 918, + ARM_MVE_ASRLr = 919, + ARM_MVE_DLSTP_16 = 920, + ARM_MVE_DLSTP_32 = 921, + ARM_MVE_DLSTP_64 = 922, + ARM_MVE_DLSTP_8 = 923, + ARM_MVE_LCTP = 924, + ARM_MVE_LETP = 925, + ARM_MVE_LSLLi = 926, + ARM_MVE_LSLLr = 927, + ARM_MVE_LSRL = 928, + ARM_MVE_SQRSHR = 929, + ARM_MVE_SQRSHRL = 930, + ARM_MVE_SQSHL = 931, + ARM_MVE_SQSHLL = 932, + ARM_MVE_SRSHR = 933, + ARM_MVE_SRSHRL = 934, + ARM_MVE_UQRSHL = 935, + ARM_MVE_UQRSHLL = 936, + ARM_MVE_UQSHL = 937, + ARM_MVE_UQSHLL = 938, + ARM_MVE_URSHR = 939, + ARM_MVE_URSHRL = 940, + ARM_MVE_VABAVs16 = 941, + ARM_MVE_VABAVs32 = 942, + ARM_MVE_VABAVs8 = 943, + ARM_MVE_VABAVu16 = 944, + ARM_MVE_VABAVu32 = 945, + ARM_MVE_VABAVu8 = 946, + ARM_MVE_VABDf16 = 947, + ARM_MVE_VABDf32 = 948, + ARM_MVE_VABDs16 = 949, + ARM_MVE_VABDs32 = 950, + ARM_MVE_VABDs8 = 951, + ARM_MVE_VABDu16 = 952, + ARM_MVE_VABDu32 = 953, + ARM_MVE_VABDu8 = 954, + ARM_MVE_VABSf16 = 955, + ARM_MVE_VABSf32 = 956, + ARM_MVE_VABSs16 = 957, + ARM_MVE_VABSs32 = 958, + ARM_MVE_VABSs8 = 959, + ARM_MVE_VADC = 960, + ARM_MVE_VADCI = 961, + ARM_MVE_VADDLVs32acc = 962, + ARM_MVE_VADDLVs32no_acc = 963, + ARM_MVE_VADDLVu32acc = 964, + ARM_MVE_VADDLVu32no_acc = 965, + ARM_MVE_VADDVs16acc = 966, + ARM_MVE_VADDVs16no_acc = 967, + ARM_MVE_VADDVs32acc = 968, + ARM_MVE_VADDVs32no_acc = 969, + ARM_MVE_VADDVs8acc = 970, + ARM_MVE_VADDVs8no_acc = 971, + ARM_MVE_VADDVu16acc = 972, + ARM_MVE_VADDVu16no_acc = 973, + ARM_MVE_VADDVu32acc = 974, + ARM_MVE_VADDVu32no_acc = 975, + ARM_MVE_VADDVu8acc = 976, + ARM_MVE_VADDVu8no_acc = 977, + ARM_MVE_VADD_qr_f16 = 978, + ARM_MVE_VADD_qr_f32 = 979, + ARM_MVE_VADD_qr_i16 = 980, + ARM_MVE_VADD_qr_i32 = 981, + ARM_MVE_VADD_qr_i8 = 982, + ARM_MVE_VADDf16 = 983, + ARM_MVE_VADDf32 = 984, + ARM_MVE_VADDi16 = 985, + ARM_MVE_VADDi32 = 986, + ARM_MVE_VADDi8 = 987, + ARM_MVE_VAND = 988, + ARM_MVE_VBIC = 989, + ARM_MVE_VBICimmi16 = 990, + ARM_MVE_VBICimmi32 = 991, + ARM_MVE_VBRSR16 = 992, + ARM_MVE_VBRSR32 = 993, + ARM_MVE_VBRSR8 = 994, + ARM_MVE_VCADDf16 = 995, + ARM_MVE_VCADDf32 = 996, + ARM_MVE_VCADDi16 = 997, + ARM_MVE_VCADDi32 = 998, + ARM_MVE_VCADDi8 = 999, + ARM_MVE_VCLSs16 = 1000, + ARM_MVE_VCLSs32 = 1001, + ARM_MVE_VCLSs8 = 1002, + ARM_MVE_VCLZs16 = 1003, + ARM_MVE_VCLZs32 = 1004, + ARM_MVE_VCLZs8 = 1005, + ARM_MVE_VCMLAf16 = 1006, + ARM_MVE_VCMLAf32 = 1007, + ARM_MVE_VCMPf16 = 1008, + ARM_MVE_VCMPf16r = 1009, + ARM_MVE_VCMPf32 = 1010, + ARM_MVE_VCMPf32r = 1011, + ARM_MVE_VCMPi16 = 1012, + ARM_MVE_VCMPi16r = 1013, + ARM_MVE_VCMPi32 = 1014, + ARM_MVE_VCMPi32r = 1015, + ARM_MVE_VCMPi8 = 1016, + ARM_MVE_VCMPi8r = 1017, + ARM_MVE_VCMPs16 = 1018, + ARM_MVE_VCMPs16r = 1019, + ARM_MVE_VCMPs32 = 1020, + ARM_MVE_VCMPs32r = 1021, + ARM_MVE_VCMPs8 = 1022, + ARM_MVE_VCMPs8r = 1023, + ARM_MVE_VCMPu16 = 1024, + ARM_MVE_VCMPu16r = 1025, + ARM_MVE_VCMPu32 = 1026, + ARM_MVE_VCMPu32r = 1027, + ARM_MVE_VCMPu8 = 1028, + ARM_MVE_VCMPu8r = 1029, + ARM_MVE_VCMULf16 = 1030, + ARM_MVE_VCMULf32 = 1031, + ARM_MVE_VCTP16 = 1032, + ARM_MVE_VCTP32 = 1033, + ARM_MVE_VCTP64 = 1034, + ARM_MVE_VCTP8 = 1035, + ARM_MVE_VCVTf16f32bh = 1036, + ARM_MVE_VCVTf16f32th = 1037, + ARM_MVE_VCVTf16s16_fix = 1038, + ARM_MVE_VCVTf16s16n = 1039, + ARM_MVE_VCVTf16u16_fix = 1040, + ARM_MVE_VCVTf16u16n = 1041, + ARM_MVE_VCVTf32f16bh = 1042, + ARM_MVE_VCVTf32f16th = 1043, + ARM_MVE_VCVTf32s32_fix = 1044, + ARM_MVE_VCVTf32s32n = 1045, + ARM_MVE_VCVTf32u32_fix = 1046, + ARM_MVE_VCVTf32u32n = 1047, + ARM_MVE_VCVTs16f16_fix = 1048, + ARM_MVE_VCVTs16f16a = 1049, + ARM_MVE_VCVTs16f16m = 1050, + ARM_MVE_VCVTs16f16n = 1051, + ARM_MVE_VCVTs16f16p = 1052, + ARM_MVE_VCVTs16f16z = 1053, + ARM_MVE_VCVTs32f32_fix = 1054, + ARM_MVE_VCVTs32f32a = 1055, + ARM_MVE_VCVTs32f32m = 1056, + ARM_MVE_VCVTs32f32n = 1057, + ARM_MVE_VCVTs32f32p = 1058, + ARM_MVE_VCVTs32f32z = 1059, + ARM_MVE_VCVTu16f16_fix = 1060, + ARM_MVE_VCVTu16f16a = 1061, + ARM_MVE_VCVTu16f16m = 1062, + ARM_MVE_VCVTu16f16n = 1063, + ARM_MVE_VCVTu16f16p = 1064, + ARM_MVE_VCVTu16f16z = 1065, + ARM_MVE_VCVTu32f32_fix = 1066, + ARM_MVE_VCVTu32f32a = 1067, + ARM_MVE_VCVTu32f32m = 1068, + ARM_MVE_VCVTu32f32n = 1069, + ARM_MVE_VCVTu32f32p = 1070, + ARM_MVE_VCVTu32f32z = 1071, + ARM_MVE_VDDUPu16 = 1072, + ARM_MVE_VDDUPu32 = 1073, + ARM_MVE_VDDUPu8 = 1074, + ARM_MVE_VDUP16 = 1075, + ARM_MVE_VDUP32 = 1076, + ARM_MVE_VDUP8 = 1077, + ARM_MVE_VDWDUPu16 = 1078, + ARM_MVE_VDWDUPu32 = 1079, + ARM_MVE_VDWDUPu8 = 1080, + ARM_MVE_VEOR = 1081, + ARM_MVE_VFMA_qr_Sf16 = 1082, + ARM_MVE_VFMA_qr_Sf32 = 1083, + ARM_MVE_VFMA_qr_f16 = 1084, + ARM_MVE_VFMA_qr_f32 = 1085, + ARM_MVE_VFMAf16 = 1086, + ARM_MVE_VFMAf32 = 1087, + ARM_MVE_VFMSf16 = 1088, + ARM_MVE_VFMSf32 = 1089, + ARM_MVE_VHADD_qr_s16 = 1090, + ARM_MVE_VHADD_qr_s32 = 1091, + ARM_MVE_VHADD_qr_s8 = 1092, + ARM_MVE_VHADD_qr_u16 = 1093, + ARM_MVE_VHADD_qr_u32 = 1094, + ARM_MVE_VHADD_qr_u8 = 1095, + ARM_MVE_VHADDs16 = 1096, + ARM_MVE_VHADDs32 = 1097, + ARM_MVE_VHADDs8 = 1098, + ARM_MVE_VHADDu16 = 1099, + ARM_MVE_VHADDu32 = 1100, + ARM_MVE_VHADDu8 = 1101, + ARM_MVE_VHCADDs16 = 1102, + ARM_MVE_VHCADDs32 = 1103, + ARM_MVE_VHCADDs8 = 1104, + ARM_MVE_VHSUB_qr_s16 = 1105, + ARM_MVE_VHSUB_qr_s32 = 1106, + ARM_MVE_VHSUB_qr_s8 = 1107, + ARM_MVE_VHSUB_qr_u16 = 1108, + ARM_MVE_VHSUB_qr_u32 = 1109, + ARM_MVE_VHSUB_qr_u8 = 1110, + ARM_MVE_VHSUBs16 = 1111, + ARM_MVE_VHSUBs32 = 1112, + ARM_MVE_VHSUBs8 = 1113, + ARM_MVE_VHSUBu16 = 1114, + ARM_MVE_VHSUBu32 = 1115, + ARM_MVE_VHSUBu8 = 1116, + ARM_MVE_VIDUPu16 = 1117, + ARM_MVE_VIDUPu32 = 1118, + ARM_MVE_VIDUPu8 = 1119, + ARM_MVE_VIWDUPu16 = 1120, + ARM_MVE_VIWDUPu32 = 1121, + ARM_MVE_VIWDUPu8 = 1122, + ARM_MVE_VLD20_16 = 1123, + ARM_MVE_VLD20_16_wb = 1124, + ARM_MVE_VLD20_32 = 1125, + ARM_MVE_VLD20_32_wb = 1126, + ARM_MVE_VLD20_8 = 1127, + ARM_MVE_VLD20_8_wb = 1128, + ARM_MVE_VLD21_16 = 1129, + ARM_MVE_VLD21_16_wb = 1130, + ARM_MVE_VLD21_32 = 1131, + ARM_MVE_VLD21_32_wb = 1132, + ARM_MVE_VLD21_8 = 1133, + ARM_MVE_VLD21_8_wb = 1134, + ARM_MVE_VLD40_16 = 1135, + ARM_MVE_VLD40_16_wb = 1136, + ARM_MVE_VLD40_32 = 1137, + ARM_MVE_VLD40_32_wb = 1138, + ARM_MVE_VLD40_8 = 1139, + ARM_MVE_VLD40_8_wb = 1140, + ARM_MVE_VLD41_16 = 1141, + ARM_MVE_VLD41_16_wb = 1142, + ARM_MVE_VLD41_32 = 1143, + ARM_MVE_VLD41_32_wb = 1144, + ARM_MVE_VLD41_8 = 1145, + ARM_MVE_VLD41_8_wb = 1146, + ARM_MVE_VLD42_16 = 1147, + ARM_MVE_VLD42_16_wb = 1148, + ARM_MVE_VLD42_32 = 1149, + ARM_MVE_VLD42_32_wb = 1150, + ARM_MVE_VLD42_8 = 1151, + ARM_MVE_VLD42_8_wb = 1152, + ARM_MVE_VLD43_16 = 1153, + ARM_MVE_VLD43_16_wb = 1154, + ARM_MVE_VLD43_32 = 1155, + ARM_MVE_VLD43_32_wb = 1156, + ARM_MVE_VLD43_8 = 1157, + ARM_MVE_VLD43_8_wb = 1158, + ARM_MVE_VLDRBS16 = 1159, + ARM_MVE_VLDRBS16_post = 1160, + ARM_MVE_VLDRBS16_pre = 1161, + ARM_MVE_VLDRBS16_rq = 1162, + ARM_MVE_VLDRBS32 = 1163, + ARM_MVE_VLDRBS32_post = 1164, + ARM_MVE_VLDRBS32_pre = 1165, + ARM_MVE_VLDRBS32_rq = 1166, + ARM_MVE_VLDRBU16 = 1167, + ARM_MVE_VLDRBU16_post = 1168, + ARM_MVE_VLDRBU16_pre = 1169, + ARM_MVE_VLDRBU16_rq = 1170, + ARM_MVE_VLDRBU32 = 1171, + ARM_MVE_VLDRBU32_post = 1172, + ARM_MVE_VLDRBU32_pre = 1173, + ARM_MVE_VLDRBU32_rq = 1174, + ARM_MVE_VLDRBU8 = 1175, + ARM_MVE_VLDRBU8_post = 1176, + ARM_MVE_VLDRBU8_pre = 1177, + ARM_MVE_VLDRBU8_rq = 1178, + ARM_MVE_VLDRDU64_qi = 1179, + ARM_MVE_VLDRDU64_qi_pre = 1180, + ARM_MVE_VLDRDU64_rq = 1181, + ARM_MVE_VLDRDU64_rq_u = 1182, + ARM_MVE_VLDRHS32 = 1183, + ARM_MVE_VLDRHS32_post = 1184, + ARM_MVE_VLDRHS32_pre = 1185, + ARM_MVE_VLDRHS32_rq = 1186, + ARM_MVE_VLDRHS32_rq_u = 1187, + ARM_MVE_VLDRHU16 = 1188, + ARM_MVE_VLDRHU16_post = 1189, + ARM_MVE_VLDRHU16_pre = 1190, + ARM_MVE_VLDRHU16_rq = 1191, + ARM_MVE_VLDRHU16_rq_u = 1192, + ARM_MVE_VLDRHU32 = 1193, + ARM_MVE_VLDRHU32_post = 1194, + ARM_MVE_VLDRHU32_pre = 1195, + ARM_MVE_VLDRHU32_rq = 1196, + ARM_MVE_VLDRHU32_rq_u = 1197, + ARM_MVE_VLDRWU32 = 1198, + ARM_MVE_VLDRWU32_post = 1199, + ARM_MVE_VLDRWU32_pre = 1200, + ARM_MVE_VLDRWU32_qi = 1201, + ARM_MVE_VLDRWU32_qi_pre = 1202, + ARM_MVE_VLDRWU32_rq = 1203, + ARM_MVE_VLDRWU32_rq_u = 1204, + ARM_MVE_VMAXAVs16 = 1205, + ARM_MVE_VMAXAVs32 = 1206, + ARM_MVE_VMAXAVs8 = 1207, + ARM_MVE_VMAXAs16 = 1208, + ARM_MVE_VMAXAs32 = 1209, + ARM_MVE_VMAXAs8 = 1210, + ARM_MVE_VMAXNMAVf16 = 1211, + ARM_MVE_VMAXNMAVf32 = 1212, + ARM_MVE_VMAXNMAf16 = 1213, + ARM_MVE_VMAXNMAf32 = 1214, + ARM_MVE_VMAXNMVf16 = 1215, + ARM_MVE_VMAXNMVf32 = 1216, + ARM_MVE_VMAXNMf16 = 1217, + ARM_MVE_VMAXNMf32 = 1218, + ARM_MVE_VMAXVs16 = 1219, + ARM_MVE_VMAXVs32 = 1220, + ARM_MVE_VMAXVs8 = 1221, + ARM_MVE_VMAXVu16 = 1222, + ARM_MVE_VMAXVu32 = 1223, + ARM_MVE_VMAXVu8 = 1224, + ARM_MVE_VMAXs16 = 1225, + ARM_MVE_VMAXs32 = 1226, + ARM_MVE_VMAXs8 = 1227, + ARM_MVE_VMAXu16 = 1228, + ARM_MVE_VMAXu32 = 1229, + ARM_MVE_VMAXu8 = 1230, + ARM_MVE_VMINAVs16 = 1231, + ARM_MVE_VMINAVs32 = 1232, + ARM_MVE_VMINAVs8 = 1233, + ARM_MVE_VMINAs16 = 1234, + ARM_MVE_VMINAs32 = 1235, + ARM_MVE_VMINAs8 = 1236, + ARM_MVE_VMINNMAVf16 = 1237, + ARM_MVE_VMINNMAVf32 = 1238, + ARM_MVE_VMINNMAf16 = 1239, + ARM_MVE_VMINNMAf32 = 1240, + ARM_MVE_VMINNMVf16 = 1241, + ARM_MVE_VMINNMVf32 = 1242, + ARM_MVE_VMINNMf16 = 1243, + ARM_MVE_VMINNMf32 = 1244, + ARM_MVE_VMINVs16 = 1245, + ARM_MVE_VMINVs32 = 1246, + ARM_MVE_VMINVs8 = 1247, + ARM_MVE_VMINVu16 = 1248, + ARM_MVE_VMINVu32 = 1249, + ARM_MVE_VMINVu8 = 1250, + ARM_MVE_VMINs16 = 1251, + ARM_MVE_VMINs32 = 1252, + ARM_MVE_VMINs8 = 1253, + ARM_MVE_VMINu16 = 1254, + ARM_MVE_VMINu32 = 1255, + ARM_MVE_VMINu8 = 1256, + ARM_MVE_VMLADAVas16 = 1257, + ARM_MVE_VMLADAVas32 = 1258, + ARM_MVE_VMLADAVas8 = 1259, + ARM_MVE_VMLADAVau16 = 1260, + ARM_MVE_VMLADAVau32 = 1261, + ARM_MVE_VMLADAVau8 = 1262, + ARM_MVE_VMLADAVaxs16 = 1263, + ARM_MVE_VMLADAVaxs32 = 1264, + ARM_MVE_VMLADAVaxs8 = 1265, + ARM_MVE_VMLADAVs16 = 1266, + ARM_MVE_VMLADAVs32 = 1267, + ARM_MVE_VMLADAVs8 = 1268, + ARM_MVE_VMLADAVu16 = 1269, + ARM_MVE_VMLADAVu32 = 1270, + ARM_MVE_VMLADAVu8 = 1271, + ARM_MVE_VMLADAVxs16 = 1272, + ARM_MVE_VMLADAVxs32 = 1273, + ARM_MVE_VMLADAVxs8 = 1274, + ARM_MVE_VMLALDAVas16 = 1275, + ARM_MVE_VMLALDAVas32 = 1276, + ARM_MVE_VMLALDAVau16 = 1277, + ARM_MVE_VMLALDAVau32 = 1278, + ARM_MVE_VMLALDAVaxs16 = 1279, + ARM_MVE_VMLALDAVaxs32 = 1280, + ARM_MVE_VMLALDAVs16 = 1281, + ARM_MVE_VMLALDAVs32 = 1282, + ARM_MVE_VMLALDAVu16 = 1283, + ARM_MVE_VMLALDAVu32 = 1284, + ARM_MVE_VMLALDAVxs16 = 1285, + ARM_MVE_VMLALDAVxs32 = 1286, + ARM_MVE_VMLAS_qr_i16 = 1287, + ARM_MVE_VMLAS_qr_i32 = 1288, + ARM_MVE_VMLAS_qr_i8 = 1289, + ARM_MVE_VMLA_qr_i16 = 1290, + ARM_MVE_VMLA_qr_i32 = 1291, + ARM_MVE_VMLA_qr_i8 = 1292, + ARM_MVE_VMLSDAVas16 = 1293, + ARM_MVE_VMLSDAVas32 = 1294, + ARM_MVE_VMLSDAVas8 = 1295, + ARM_MVE_VMLSDAVaxs16 = 1296, + ARM_MVE_VMLSDAVaxs32 = 1297, + ARM_MVE_VMLSDAVaxs8 = 1298, + ARM_MVE_VMLSDAVs16 = 1299, + ARM_MVE_VMLSDAVs32 = 1300, + ARM_MVE_VMLSDAVs8 = 1301, + ARM_MVE_VMLSDAVxs16 = 1302, + ARM_MVE_VMLSDAVxs32 = 1303, + ARM_MVE_VMLSDAVxs8 = 1304, + ARM_MVE_VMLSLDAVas16 = 1305, + ARM_MVE_VMLSLDAVas32 = 1306, + ARM_MVE_VMLSLDAVaxs16 = 1307, + ARM_MVE_VMLSLDAVaxs32 = 1308, + ARM_MVE_VMLSLDAVs16 = 1309, + ARM_MVE_VMLSLDAVs32 = 1310, + ARM_MVE_VMLSLDAVxs16 = 1311, + ARM_MVE_VMLSLDAVxs32 = 1312, + ARM_MVE_VMOVLs16bh = 1313, + ARM_MVE_VMOVLs16th = 1314, + ARM_MVE_VMOVLs8bh = 1315, + ARM_MVE_VMOVLs8th = 1316, + ARM_MVE_VMOVLu16bh = 1317, + ARM_MVE_VMOVLu16th = 1318, + ARM_MVE_VMOVLu8bh = 1319, + ARM_MVE_VMOVLu8th = 1320, + ARM_MVE_VMOVNi16bh = 1321, + ARM_MVE_VMOVNi16th = 1322, + ARM_MVE_VMOVNi32bh = 1323, + ARM_MVE_VMOVNi32th = 1324, + ARM_MVE_VMOV_from_lane_32 = 1325, + ARM_MVE_VMOV_from_lane_s16 = 1326, + ARM_MVE_VMOV_from_lane_s8 = 1327, + ARM_MVE_VMOV_from_lane_u16 = 1328, + ARM_MVE_VMOV_from_lane_u8 = 1329, + ARM_MVE_VMOV_q_rr = 1330, + ARM_MVE_VMOV_rr_q = 1331, + ARM_MVE_VMOV_to_lane_16 = 1332, + ARM_MVE_VMOV_to_lane_32 = 1333, + ARM_MVE_VMOV_to_lane_8 = 1334, + ARM_MVE_VMOVimmf32 = 1335, + ARM_MVE_VMOVimmi16 = 1336, + ARM_MVE_VMOVimmi32 = 1337, + ARM_MVE_VMOVimmi64 = 1338, + ARM_MVE_VMOVimmi8 = 1339, + ARM_MVE_VMULHs16 = 1340, + ARM_MVE_VMULHs32 = 1341, + ARM_MVE_VMULHs8 = 1342, + ARM_MVE_VMULHu16 = 1343, + ARM_MVE_VMULHu32 = 1344, + ARM_MVE_VMULHu8 = 1345, + ARM_MVE_VMULLBp16 = 1346, + ARM_MVE_VMULLBp8 = 1347, + ARM_MVE_VMULLBs16 = 1348, + ARM_MVE_VMULLBs32 = 1349, + ARM_MVE_VMULLBs8 = 1350, + ARM_MVE_VMULLBu16 = 1351, + ARM_MVE_VMULLBu32 = 1352, + ARM_MVE_VMULLBu8 = 1353, + ARM_MVE_VMULLTp16 = 1354, + ARM_MVE_VMULLTp8 = 1355, + ARM_MVE_VMULLTs16 = 1356, + ARM_MVE_VMULLTs32 = 1357, + ARM_MVE_VMULLTs8 = 1358, + ARM_MVE_VMULLTu16 = 1359, + ARM_MVE_VMULLTu32 = 1360, + ARM_MVE_VMULLTu8 = 1361, + ARM_MVE_VMUL_qr_f16 = 1362, + ARM_MVE_VMUL_qr_f32 = 1363, + ARM_MVE_VMUL_qr_i16 = 1364, + ARM_MVE_VMUL_qr_i32 = 1365, + ARM_MVE_VMUL_qr_i8 = 1366, + ARM_MVE_VMULf16 = 1367, + ARM_MVE_VMULf32 = 1368, + ARM_MVE_VMULi16 = 1369, + ARM_MVE_VMULi32 = 1370, + ARM_MVE_VMULi8 = 1371, + ARM_MVE_VMVN = 1372, + ARM_MVE_VMVNimmi16 = 1373, + ARM_MVE_VMVNimmi32 = 1374, + ARM_MVE_VNEGf16 = 1375, + ARM_MVE_VNEGf32 = 1376, + ARM_MVE_VNEGs16 = 1377, + ARM_MVE_VNEGs32 = 1378, + ARM_MVE_VNEGs8 = 1379, + ARM_MVE_VORN = 1380, + ARM_MVE_VORR = 1381, + ARM_MVE_VORRimmi16 = 1382, + ARM_MVE_VORRimmi32 = 1383, + ARM_MVE_VPNOT = 1384, + ARM_MVE_VPSEL = 1385, + ARM_MVE_VPST = 1386, + ARM_MVE_VPTv16i8 = 1387, + ARM_MVE_VPTv16i8r = 1388, + ARM_MVE_VPTv16s8 = 1389, + ARM_MVE_VPTv16s8r = 1390, + ARM_MVE_VPTv16u8 = 1391, + ARM_MVE_VPTv16u8r = 1392, + ARM_MVE_VPTv4f32 = 1393, + ARM_MVE_VPTv4f32r = 1394, + ARM_MVE_VPTv4i32 = 1395, + ARM_MVE_VPTv4i32r = 1396, + ARM_MVE_VPTv4s32 = 1397, + ARM_MVE_VPTv4s32r = 1398, + ARM_MVE_VPTv4u32 = 1399, + ARM_MVE_VPTv4u32r = 1400, + ARM_MVE_VPTv8f16 = 1401, + ARM_MVE_VPTv8f16r = 1402, + ARM_MVE_VPTv8i16 = 1403, + ARM_MVE_VPTv8i16r = 1404, + ARM_MVE_VPTv8s16 = 1405, + ARM_MVE_VPTv8s16r = 1406, + ARM_MVE_VPTv8u16 = 1407, + ARM_MVE_VPTv8u16r = 1408, + ARM_MVE_VQABSs16 = 1409, + ARM_MVE_VQABSs32 = 1410, + ARM_MVE_VQABSs8 = 1411, + ARM_MVE_VQADD_qr_s16 = 1412, + ARM_MVE_VQADD_qr_s32 = 1413, + ARM_MVE_VQADD_qr_s8 = 1414, + ARM_MVE_VQADD_qr_u16 = 1415, + ARM_MVE_VQADD_qr_u32 = 1416, + ARM_MVE_VQADD_qr_u8 = 1417, + ARM_MVE_VQADDs16 = 1418, + ARM_MVE_VQADDs32 = 1419, + ARM_MVE_VQADDs8 = 1420, + ARM_MVE_VQADDu16 = 1421, + ARM_MVE_VQADDu32 = 1422, + ARM_MVE_VQADDu8 = 1423, + ARM_MVE_VQDMLADHXs16 = 1424, + ARM_MVE_VQDMLADHXs32 = 1425, + ARM_MVE_VQDMLADHXs8 = 1426, + ARM_MVE_VQDMLADHs16 = 1427, + ARM_MVE_VQDMLADHs32 = 1428, + ARM_MVE_VQDMLADHs8 = 1429, + ARM_MVE_VQDMLAH_qrs16 = 1430, + ARM_MVE_VQDMLAH_qrs32 = 1431, + ARM_MVE_VQDMLAH_qrs8 = 1432, + ARM_MVE_VQDMLASH_qrs16 = 1433, + ARM_MVE_VQDMLASH_qrs32 = 1434, + ARM_MVE_VQDMLASH_qrs8 = 1435, + ARM_MVE_VQDMLSDHXs16 = 1436, + ARM_MVE_VQDMLSDHXs32 = 1437, + ARM_MVE_VQDMLSDHXs8 = 1438, + ARM_MVE_VQDMLSDHs16 = 1439, + ARM_MVE_VQDMLSDHs32 = 1440, + ARM_MVE_VQDMLSDHs8 = 1441, + ARM_MVE_VQDMULH_qr_s16 = 1442, + ARM_MVE_VQDMULH_qr_s32 = 1443, + ARM_MVE_VQDMULH_qr_s8 = 1444, + ARM_MVE_VQDMULHi16 = 1445, + ARM_MVE_VQDMULHi32 = 1446, + ARM_MVE_VQDMULHi8 = 1447, + ARM_MVE_VQDMULL_qr_s16bh = 1448, + ARM_MVE_VQDMULL_qr_s16th = 1449, + ARM_MVE_VQDMULL_qr_s32bh = 1450, + ARM_MVE_VQDMULL_qr_s32th = 1451, + ARM_MVE_VQDMULLs16bh = 1452, + ARM_MVE_VQDMULLs16th = 1453, + ARM_MVE_VQDMULLs32bh = 1454, + ARM_MVE_VQDMULLs32th = 1455, + ARM_MVE_VQMOVNs16bh = 1456, + ARM_MVE_VQMOVNs16th = 1457, + ARM_MVE_VQMOVNs32bh = 1458, + ARM_MVE_VQMOVNs32th = 1459, + ARM_MVE_VQMOVNu16bh = 1460, + ARM_MVE_VQMOVNu16th = 1461, + ARM_MVE_VQMOVNu32bh = 1462, + ARM_MVE_VQMOVNu32th = 1463, + ARM_MVE_VQMOVUNs16bh = 1464, + ARM_MVE_VQMOVUNs16th = 1465, + ARM_MVE_VQMOVUNs32bh = 1466, + ARM_MVE_VQMOVUNs32th = 1467, + ARM_MVE_VQNEGs16 = 1468, + ARM_MVE_VQNEGs32 = 1469, + ARM_MVE_VQNEGs8 = 1470, + ARM_MVE_VQRDMLADHXs16 = 1471, + ARM_MVE_VQRDMLADHXs32 = 1472, + ARM_MVE_VQRDMLADHXs8 = 1473, + ARM_MVE_VQRDMLADHs16 = 1474, + ARM_MVE_VQRDMLADHs32 = 1475, + ARM_MVE_VQRDMLADHs8 = 1476, + ARM_MVE_VQRDMLAH_qrs16 = 1477, + ARM_MVE_VQRDMLAH_qrs32 = 1478, + ARM_MVE_VQRDMLAH_qrs8 = 1479, + ARM_MVE_VQRDMLASH_qrs16 = 1480, + ARM_MVE_VQRDMLASH_qrs32 = 1481, + ARM_MVE_VQRDMLASH_qrs8 = 1482, + ARM_MVE_VQRDMLSDHXs16 = 1483, + ARM_MVE_VQRDMLSDHXs32 = 1484, + ARM_MVE_VQRDMLSDHXs8 = 1485, + ARM_MVE_VQRDMLSDHs16 = 1486, + ARM_MVE_VQRDMLSDHs32 = 1487, + ARM_MVE_VQRDMLSDHs8 = 1488, + ARM_MVE_VQRDMULH_qr_s16 = 1489, + ARM_MVE_VQRDMULH_qr_s32 = 1490, + ARM_MVE_VQRDMULH_qr_s8 = 1491, + ARM_MVE_VQRDMULHi16 = 1492, + ARM_MVE_VQRDMULHi32 = 1493, + ARM_MVE_VQRDMULHi8 = 1494, + ARM_MVE_VQRSHL_by_vecs16 = 1495, + ARM_MVE_VQRSHL_by_vecs32 = 1496, + ARM_MVE_VQRSHL_by_vecs8 = 1497, + ARM_MVE_VQRSHL_by_vecu16 = 1498, + ARM_MVE_VQRSHL_by_vecu32 = 1499, + ARM_MVE_VQRSHL_by_vecu8 = 1500, + ARM_MVE_VQRSHL_qrs16 = 1501, + ARM_MVE_VQRSHL_qrs32 = 1502, + ARM_MVE_VQRSHL_qrs8 = 1503, + ARM_MVE_VQRSHL_qru16 = 1504, + ARM_MVE_VQRSHL_qru32 = 1505, + ARM_MVE_VQRSHL_qru8 = 1506, + ARM_MVE_VQRSHRNbhs16 = 1507, + ARM_MVE_VQRSHRNbhs32 = 1508, + ARM_MVE_VQRSHRNbhu16 = 1509, + ARM_MVE_VQRSHRNbhu32 = 1510, + ARM_MVE_VQRSHRNths16 = 1511, + ARM_MVE_VQRSHRNths32 = 1512, + ARM_MVE_VQRSHRNthu16 = 1513, + ARM_MVE_VQRSHRNthu32 = 1514, + ARM_MVE_VQRSHRUNs16bh = 1515, + ARM_MVE_VQRSHRUNs16th = 1516, + ARM_MVE_VQRSHRUNs32bh = 1517, + ARM_MVE_VQRSHRUNs32th = 1518, + ARM_MVE_VQSHLU_imms16 = 1519, + ARM_MVE_VQSHLU_imms32 = 1520, + ARM_MVE_VQSHLU_imms8 = 1521, + ARM_MVE_VQSHL_by_vecs16 = 1522, + ARM_MVE_VQSHL_by_vecs32 = 1523, + ARM_MVE_VQSHL_by_vecs8 = 1524, + ARM_MVE_VQSHL_by_vecu16 = 1525, + ARM_MVE_VQSHL_by_vecu32 = 1526, + ARM_MVE_VQSHL_by_vecu8 = 1527, + ARM_MVE_VQSHL_qrs16 = 1528, + ARM_MVE_VQSHL_qrs32 = 1529, + ARM_MVE_VQSHL_qrs8 = 1530, + ARM_MVE_VQSHL_qru16 = 1531, + ARM_MVE_VQSHL_qru32 = 1532, + ARM_MVE_VQSHL_qru8 = 1533, + ARM_MVE_VQSHLimms16 = 1534, + ARM_MVE_VQSHLimms32 = 1535, + ARM_MVE_VQSHLimms8 = 1536, + ARM_MVE_VQSHLimmu16 = 1537, + ARM_MVE_VQSHLimmu32 = 1538, + ARM_MVE_VQSHLimmu8 = 1539, + ARM_MVE_VQSHRNbhs16 = 1540, + ARM_MVE_VQSHRNbhs32 = 1541, + ARM_MVE_VQSHRNbhu16 = 1542, + ARM_MVE_VQSHRNbhu32 = 1543, + ARM_MVE_VQSHRNths16 = 1544, + ARM_MVE_VQSHRNths32 = 1545, + ARM_MVE_VQSHRNthu16 = 1546, + ARM_MVE_VQSHRNthu32 = 1547, + ARM_MVE_VQSHRUNs16bh = 1548, + ARM_MVE_VQSHRUNs16th = 1549, + ARM_MVE_VQSHRUNs32bh = 1550, + ARM_MVE_VQSHRUNs32th = 1551, + ARM_MVE_VQSUB_qr_s16 = 1552, + ARM_MVE_VQSUB_qr_s32 = 1553, + ARM_MVE_VQSUB_qr_s8 = 1554, + ARM_MVE_VQSUB_qr_u16 = 1555, + ARM_MVE_VQSUB_qr_u32 = 1556, + ARM_MVE_VQSUB_qr_u8 = 1557, + ARM_MVE_VQSUBs16 = 1558, + ARM_MVE_VQSUBs32 = 1559, + ARM_MVE_VQSUBs8 = 1560, + ARM_MVE_VQSUBu16 = 1561, + ARM_MVE_VQSUBu32 = 1562, + ARM_MVE_VQSUBu8 = 1563, + ARM_MVE_VREV16_8 = 1564, + ARM_MVE_VREV32_16 = 1565, + ARM_MVE_VREV32_8 = 1566, + ARM_MVE_VREV64_16 = 1567, + ARM_MVE_VREV64_32 = 1568, + ARM_MVE_VREV64_8 = 1569, + ARM_MVE_VRHADDs16 = 1570, + ARM_MVE_VRHADDs32 = 1571, + ARM_MVE_VRHADDs8 = 1572, + ARM_MVE_VRHADDu16 = 1573, + ARM_MVE_VRHADDu32 = 1574, + ARM_MVE_VRHADDu8 = 1575, + ARM_MVE_VRINTf16A = 1576, + ARM_MVE_VRINTf16M = 1577, + ARM_MVE_VRINTf16N = 1578, + ARM_MVE_VRINTf16P = 1579, + ARM_MVE_VRINTf16X = 1580, + ARM_MVE_VRINTf16Z = 1581, + ARM_MVE_VRINTf32A = 1582, + ARM_MVE_VRINTf32M = 1583, + ARM_MVE_VRINTf32N = 1584, + ARM_MVE_VRINTf32P = 1585, + ARM_MVE_VRINTf32X = 1586, + ARM_MVE_VRINTf32Z = 1587, + ARM_MVE_VRMLALDAVHas32 = 1588, + ARM_MVE_VRMLALDAVHau32 = 1589, + ARM_MVE_VRMLALDAVHaxs32 = 1590, + ARM_MVE_VRMLALDAVHs32 = 1591, + ARM_MVE_VRMLALDAVHu32 = 1592, + ARM_MVE_VRMLALDAVHxs32 = 1593, + ARM_MVE_VRMLSLDAVHas32 = 1594, + ARM_MVE_VRMLSLDAVHaxs32 = 1595, + ARM_MVE_VRMLSLDAVHs32 = 1596, + ARM_MVE_VRMLSLDAVHxs32 = 1597, + ARM_MVE_VRMULHs16 = 1598, + ARM_MVE_VRMULHs32 = 1599, + ARM_MVE_VRMULHs8 = 1600, + ARM_MVE_VRMULHu16 = 1601, + ARM_MVE_VRMULHu32 = 1602, + ARM_MVE_VRMULHu8 = 1603, + ARM_MVE_VRSHL_by_vecs16 = 1604, + ARM_MVE_VRSHL_by_vecs32 = 1605, + ARM_MVE_VRSHL_by_vecs8 = 1606, + ARM_MVE_VRSHL_by_vecu16 = 1607, + ARM_MVE_VRSHL_by_vecu32 = 1608, + ARM_MVE_VRSHL_by_vecu8 = 1609, + ARM_MVE_VRSHL_qrs16 = 1610, + ARM_MVE_VRSHL_qrs32 = 1611, + ARM_MVE_VRSHL_qrs8 = 1612, + ARM_MVE_VRSHL_qru16 = 1613, + ARM_MVE_VRSHL_qru32 = 1614, + ARM_MVE_VRSHL_qru8 = 1615, + ARM_MVE_VRSHRNi16bh = 1616, + ARM_MVE_VRSHRNi16th = 1617, + ARM_MVE_VRSHRNi32bh = 1618, + ARM_MVE_VRSHRNi32th = 1619, + ARM_MVE_VRSHR_imms16 = 1620, + ARM_MVE_VRSHR_imms32 = 1621, + ARM_MVE_VRSHR_imms8 = 1622, + ARM_MVE_VRSHR_immu16 = 1623, + ARM_MVE_VRSHR_immu32 = 1624, + ARM_MVE_VRSHR_immu8 = 1625, + ARM_MVE_VSBC = 1626, + ARM_MVE_VSBCI = 1627, + ARM_MVE_VSHLC = 1628, + ARM_MVE_VSHLL_imms16bh = 1629, + ARM_MVE_VSHLL_imms16th = 1630, + ARM_MVE_VSHLL_imms8bh = 1631, + ARM_MVE_VSHLL_imms8th = 1632, + ARM_MVE_VSHLL_immu16bh = 1633, + ARM_MVE_VSHLL_immu16th = 1634, + ARM_MVE_VSHLL_immu8bh = 1635, + ARM_MVE_VSHLL_immu8th = 1636, + ARM_MVE_VSHLL_lws16bh = 1637, + ARM_MVE_VSHLL_lws16th = 1638, + ARM_MVE_VSHLL_lws8bh = 1639, + ARM_MVE_VSHLL_lws8th = 1640, + ARM_MVE_VSHLL_lwu16bh = 1641, + ARM_MVE_VSHLL_lwu16th = 1642, + ARM_MVE_VSHLL_lwu8bh = 1643, + ARM_MVE_VSHLL_lwu8th = 1644, + ARM_MVE_VSHL_by_vecs16 = 1645, + ARM_MVE_VSHL_by_vecs32 = 1646, + ARM_MVE_VSHL_by_vecs8 = 1647, + ARM_MVE_VSHL_by_vecu16 = 1648, + ARM_MVE_VSHL_by_vecu32 = 1649, + ARM_MVE_VSHL_by_vecu8 = 1650, + ARM_MVE_VSHL_immi16 = 1651, + ARM_MVE_VSHL_immi32 = 1652, + ARM_MVE_VSHL_immi8 = 1653, + ARM_MVE_VSHL_qrs16 = 1654, + ARM_MVE_VSHL_qrs32 = 1655, + ARM_MVE_VSHL_qrs8 = 1656, + ARM_MVE_VSHL_qru16 = 1657, + ARM_MVE_VSHL_qru32 = 1658, + ARM_MVE_VSHL_qru8 = 1659, + ARM_MVE_VSHRNi16bh = 1660, + ARM_MVE_VSHRNi16th = 1661, + ARM_MVE_VSHRNi32bh = 1662, + ARM_MVE_VSHRNi32th = 1663, + ARM_MVE_VSHR_imms16 = 1664, + ARM_MVE_VSHR_imms32 = 1665, + ARM_MVE_VSHR_imms8 = 1666, + ARM_MVE_VSHR_immu16 = 1667, + ARM_MVE_VSHR_immu32 = 1668, + ARM_MVE_VSHR_immu8 = 1669, + ARM_MVE_VSLIimm16 = 1670, + ARM_MVE_VSLIimm32 = 1671, + ARM_MVE_VSLIimm8 = 1672, + ARM_MVE_VSRIimm16 = 1673, + ARM_MVE_VSRIimm32 = 1674, + ARM_MVE_VSRIimm8 = 1675, + ARM_MVE_VST20_16 = 1676, + ARM_MVE_VST20_16_wb = 1677, + ARM_MVE_VST20_32 = 1678, + ARM_MVE_VST20_32_wb = 1679, + ARM_MVE_VST20_8 = 1680, + ARM_MVE_VST20_8_wb = 1681, + ARM_MVE_VST21_16 = 1682, + ARM_MVE_VST21_16_wb = 1683, + ARM_MVE_VST21_32 = 1684, + ARM_MVE_VST21_32_wb = 1685, + ARM_MVE_VST21_8 = 1686, + ARM_MVE_VST21_8_wb = 1687, + ARM_MVE_VST40_16 = 1688, + ARM_MVE_VST40_16_wb = 1689, + ARM_MVE_VST40_32 = 1690, + ARM_MVE_VST40_32_wb = 1691, + ARM_MVE_VST40_8 = 1692, + ARM_MVE_VST40_8_wb = 1693, + ARM_MVE_VST41_16 = 1694, + ARM_MVE_VST41_16_wb = 1695, + ARM_MVE_VST41_32 = 1696, + ARM_MVE_VST41_32_wb = 1697, + ARM_MVE_VST41_8 = 1698, + ARM_MVE_VST41_8_wb = 1699, + ARM_MVE_VST42_16 = 1700, + ARM_MVE_VST42_16_wb = 1701, + ARM_MVE_VST42_32 = 1702, + ARM_MVE_VST42_32_wb = 1703, + ARM_MVE_VST42_8 = 1704, + ARM_MVE_VST42_8_wb = 1705, + ARM_MVE_VST43_16 = 1706, + ARM_MVE_VST43_16_wb = 1707, + ARM_MVE_VST43_32 = 1708, + ARM_MVE_VST43_32_wb = 1709, + ARM_MVE_VST43_8 = 1710, + ARM_MVE_VST43_8_wb = 1711, + ARM_MVE_VSTRB16 = 1712, + ARM_MVE_VSTRB16_post = 1713, + ARM_MVE_VSTRB16_pre = 1714, + ARM_MVE_VSTRB16_rq = 1715, + ARM_MVE_VSTRB32 = 1716, + ARM_MVE_VSTRB32_post = 1717, + ARM_MVE_VSTRB32_pre = 1718, + ARM_MVE_VSTRB32_rq = 1719, + ARM_MVE_VSTRB8_rq = 1720, + ARM_MVE_VSTRBU8 = 1721, + ARM_MVE_VSTRBU8_post = 1722, + ARM_MVE_VSTRBU8_pre = 1723, + ARM_MVE_VSTRD64_qi = 1724, + ARM_MVE_VSTRD64_qi_pre = 1725, + ARM_MVE_VSTRD64_rq = 1726, + ARM_MVE_VSTRD64_rq_u = 1727, + ARM_MVE_VSTRH16_rq = 1728, + ARM_MVE_VSTRH16_rq_u = 1729, + ARM_MVE_VSTRH32 = 1730, + ARM_MVE_VSTRH32_post = 1731, + ARM_MVE_VSTRH32_pre = 1732, + ARM_MVE_VSTRH32_rq = 1733, + ARM_MVE_VSTRH32_rq_u = 1734, + ARM_MVE_VSTRHU16 = 1735, + ARM_MVE_VSTRHU16_post = 1736, + ARM_MVE_VSTRHU16_pre = 1737, + ARM_MVE_VSTRW32_qi = 1738, + ARM_MVE_VSTRW32_qi_pre = 1739, + ARM_MVE_VSTRW32_rq = 1740, + ARM_MVE_VSTRW32_rq_u = 1741, + ARM_MVE_VSTRWU32 = 1742, + ARM_MVE_VSTRWU32_post = 1743, + ARM_MVE_VSTRWU32_pre = 1744, + ARM_MVE_VSUB_qr_f16 = 1745, + ARM_MVE_VSUB_qr_f32 = 1746, + ARM_MVE_VSUB_qr_i16 = 1747, + ARM_MVE_VSUB_qr_i32 = 1748, + ARM_MVE_VSUB_qr_i8 = 1749, + ARM_MVE_VSUBf16 = 1750, + ARM_MVE_VSUBf32 = 1751, + ARM_MVE_VSUBi16 = 1752, + ARM_MVE_VSUBi32 = 1753, + ARM_MVE_VSUBi8 = 1754, + ARM_MVE_WLSTP_16 = 1755, + ARM_MVE_WLSTP_32 = 1756, + ARM_MVE_WLSTP_64 = 1757, + ARM_MVE_WLSTP_8 = 1758, + ARM_MVNi = 1759, + ARM_MVNr = 1760, + ARM_MVNsi = 1761, + ARM_MVNsr = 1762, + ARM_NEON_VMAXNMNDf = 1763, + ARM_NEON_VMAXNMNDh = 1764, + ARM_NEON_VMAXNMNQf = 1765, + ARM_NEON_VMAXNMNQh = 1766, + ARM_NEON_VMINNMNDf = 1767, + ARM_NEON_VMINNMNDh = 1768, + ARM_NEON_VMINNMNQf = 1769, + ARM_NEON_VMINNMNQh = 1770, + ARM_ORRri = 1771, + ARM_ORRrr = 1772, + ARM_ORRrsi = 1773, + ARM_ORRrsr = 1774, + ARM_PKHBT = 1775, + ARM_PKHTB = 1776, + ARM_PLDWi12 = 1777, + ARM_PLDWrs = 1778, + ARM_PLDi12 = 1779, + ARM_PLDrs = 1780, + ARM_PLIi12 = 1781, + ARM_PLIrs = 1782, + ARM_QADD = 1783, + ARM_QADD16 = 1784, + ARM_QADD8 = 1785, + ARM_QASX = 1786, + ARM_QDADD = 1787, + ARM_QDSUB = 1788, + ARM_QSAX = 1789, + ARM_QSUB = 1790, + ARM_QSUB16 = 1791, + ARM_QSUB8 = 1792, + ARM_RBIT = 1793, + ARM_REV = 1794, + ARM_REV16 = 1795, + ARM_REVSH = 1796, + ARM_RFEDA = 1797, + ARM_RFEDA_UPD = 1798, + ARM_RFEDB = 1799, + ARM_RFEDB_UPD = 1800, + ARM_RFEIA = 1801, + ARM_RFEIA_UPD = 1802, + ARM_RFEIB = 1803, + ARM_RFEIB_UPD = 1804, + ARM_RSBri = 1805, + ARM_RSBrr = 1806, + ARM_RSBrsi = 1807, + ARM_RSBrsr = 1808, + ARM_RSCri = 1809, + ARM_RSCrr = 1810, + ARM_RSCrsi = 1811, + ARM_RSCrsr = 1812, + ARM_SADD16 = 1813, + ARM_SADD8 = 1814, + ARM_SASX = 1815, + ARM_SB = 1816, + ARM_SBCri = 1817, + ARM_SBCrr = 1818, + ARM_SBCrsi = 1819, + ARM_SBCrsr = 1820, + ARM_SBFX = 1821, + ARM_SDIV = 1822, + ARM_SEL = 1823, + ARM_SETEND = 1824, + ARM_SETPAN = 1825, + ARM_SHA1C = 1826, + ARM_SHA1H = 1827, + ARM_SHA1M = 1828, + ARM_SHA1P = 1829, + ARM_SHA1SU0 = 1830, + ARM_SHA1SU1 = 1831, + ARM_SHA256H = 1832, + ARM_SHA256H2 = 1833, + ARM_SHA256SU0 = 1834, + ARM_SHA256SU1 = 1835, + ARM_SHADD16 = 1836, + ARM_SHADD8 = 1837, + ARM_SHASX = 1838, + ARM_SHSAX = 1839, + ARM_SHSUB16 = 1840, + ARM_SHSUB8 = 1841, + ARM_SMC = 1842, + ARM_SMLABB = 1843, + ARM_SMLABT = 1844, + ARM_SMLAD = 1845, + ARM_SMLADX = 1846, + ARM_SMLAL = 1847, + ARM_SMLALBB = 1848, + ARM_SMLALBT = 1849, + ARM_SMLALD = 1850, + ARM_SMLALDX = 1851, + ARM_SMLALTB = 1852, + ARM_SMLALTT = 1853, + ARM_SMLATB = 1854, + ARM_SMLATT = 1855, + ARM_SMLAWB = 1856, + ARM_SMLAWT = 1857, + ARM_SMLSD = 1858, + ARM_SMLSDX = 1859, + ARM_SMLSLD = 1860, + ARM_SMLSLDX = 1861, + ARM_SMMLA = 1862, + ARM_SMMLAR = 1863, + ARM_SMMLS = 1864, + ARM_SMMLSR = 1865, + ARM_SMMUL = 1866, + ARM_SMMULR = 1867, + ARM_SMUAD = 1868, + ARM_SMUADX = 1869, + ARM_SMULBB = 1870, + ARM_SMULBT = 1871, + ARM_SMULL = 1872, + ARM_SMULTB = 1873, + ARM_SMULTT = 1874, + ARM_SMULWB = 1875, + ARM_SMULWT = 1876, + ARM_SMUSD = 1877, + ARM_SMUSDX = 1878, + ARM_SRSDA = 1879, + ARM_SRSDA_UPD = 1880, + ARM_SRSDB = 1881, + ARM_SRSDB_UPD = 1882, + ARM_SRSIA = 1883, + ARM_SRSIA_UPD = 1884, + ARM_SRSIB = 1885, + ARM_SRSIB_UPD = 1886, + ARM_SSAT = 1887, + ARM_SSAT16 = 1888, + ARM_SSAX = 1889, + ARM_SSUB16 = 1890, + ARM_SSUB8 = 1891, + ARM_STC2L_OFFSET = 1892, + ARM_STC2L_OPTION = 1893, + ARM_STC2L_POST = 1894, + ARM_STC2L_PRE = 1895, + ARM_STC2_OFFSET = 1896, + ARM_STC2_OPTION = 1897, + ARM_STC2_POST = 1898, + ARM_STC2_PRE = 1899, + ARM_STCL_OFFSET = 1900, + ARM_STCL_OPTION = 1901, + ARM_STCL_POST = 1902, + ARM_STCL_PRE = 1903, + ARM_STC_OFFSET = 1904, + ARM_STC_OPTION = 1905, + ARM_STC_POST = 1906, + ARM_STC_PRE = 1907, + ARM_STL = 1908, + ARM_STLB = 1909, + ARM_STLEX = 1910, + ARM_STLEXB = 1911, + ARM_STLEXD = 1912, + ARM_STLEXH = 1913, + ARM_STLH = 1914, + ARM_STMDA = 1915, + ARM_STMDA_UPD = 1916, + ARM_STMDB = 1917, + ARM_STMDB_UPD = 1918, + ARM_STMIA = 1919, + ARM_STMIA_UPD = 1920, + ARM_STMIB = 1921, + ARM_STMIB_UPD = 1922, + ARM_STRBT_POST_IMM = 1923, + ARM_STRBT_POST_REG = 1924, + ARM_STRB_POST_IMM = 1925, + ARM_STRB_POST_REG = 1926, + ARM_STRB_PRE_IMM = 1927, + ARM_STRB_PRE_REG = 1928, + ARM_STRBi12 = 1929, + ARM_STRBrs = 1930, + ARM_STRD = 1931, + ARM_STRD_POST = 1932, + ARM_STRD_PRE = 1933, + ARM_STREX = 1934, + ARM_STREXB = 1935, + ARM_STREXD = 1936, + ARM_STREXH = 1937, + ARM_STRH = 1938, + ARM_STRHTi = 1939, + ARM_STRHTr = 1940, + ARM_STRH_POST = 1941, + ARM_STRH_PRE = 1942, + ARM_STRT_POST_IMM = 1943, + ARM_STRT_POST_REG = 1944, + ARM_STR_POST_IMM = 1945, + ARM_STR_POST_REG = 1946, + ARM_STR_PRE_IMM = 1947, + ARM_STR_PRE_REG = 1948, + ARM_STRi12 = 1949, + ARM_STRrs = 1950, + ARM_SUBri = 1951, + ARM_SUBrr = 1952, + ARM_SUBrsi = 1953, + ARM_SUBrsr = 1954, + ARM_SVC = 1955, + ARM_SWP = 1956, + ARM_SWPB = 1957, + ARM_SXTAB = 1958, + ARM_SXTAB16 = 1959, + ARM_SXTAH = 1960, + ARM_SXTB = 1961, + ARM_SXTB16 = 1962, + ARM_SXTH = 1963, + ARM_TEQri = 1964, + ARM_TEQrr = 1965, + ARM_TEQrsi = 1966, + ARM_TEQrsr = 1967, + ARM_TRAP = 1968, + ARM_TRAPNaCl = 1969, + ARM_TSB = 1970, + ARM_TSTri = 1971, + ARM_TSTrr = 1972, + ARM_TSTrsi = 1973, + ARM_TSTrsr = 1974, + ARM_UADD16 = 1975, + ARM_UADD8 = 1976, + ARM_UASX = 1977, + ARM_UBFX = 1978, + ARM_UDF = 1979, + ARM_UDIV = 1980, + ARM_UHADD16 = 1981, + ARM_UHADD8 = 1982, + ARM_UHASX = 1983, + ARM_UHSAX = 1984, + ARM_UHSUB16 = 1985, + ARM_UHSUB8 = 1986, + ARM_UMAAL = 1987, + ARM_UMLAL = 1988, + ARM_UMULL = 1989, + ARM_UQADD16 = 1990, + ARM_UQADD8 = 1991, + ARM_UQASX = 1992, + ARM_UQSAX = 1993, + ARM_UQSUB16 = 1994, + ARM_UQSUB8 = 1995, + ARM_USAD8 = 1996, + ARM_USADA8 = 1997, + ARM_USAT = 1998, + ARM_USAT16 = 1999, + ARM_USAX = 2000, + ARM_USUB16 = 2001, + ARM_USUB8 = 2002, + ARM_UXTAB = 2003, + ARM_UXTAB16 = 2004, + ARM_UXTAH = 2005, + ARM_UXTB = 2006, + ARM_UXTB16 = 2007, + ARM_UXTH = 2008, + ARM_VABALsv2i64 = 2009, + ARM_VABALsv4i32 = 2010, + ARM_VABALsv8i16 = 2011, + ARM_VABALuv2i64 = 2012, + ARM_VABALuv4i32 = 2013, + ARM_VABALuv8i16 = 2014, + ARM_VABAsv16i8 = 2015, + ARM_VABAsv2i32 = 2016, + ARM_VABAsv4i16 = 2017, + ARM_VABAsv4i32 = 2018, + ARM_VABAsv8i16 = 2019, + ARM_VABAsv8i8 = 2020, + ARM_VABAuv16i8 = 2021, + ARM_VABAuv2i32 = 2022, + ARM_VABAuv4i16 = 2023, + ARM_VABAuv4i32 = 2024, + ARM_VABAuv8i16 = 2025, + ARM_VABAuv8i8 = 2026, + ARM_VABDLsv2i64 = 2027, + ARM_VABDLsv4i32 = 2028, + ARM_VABDLsv8i16 = 2029, + ARM_VABDLuv2i64 = 2030, + ARM_VABDLuv4i32 = 2031, + ARM_VABDLuv8i16 = 2032, + ARM_VABDfd = 2033, + ARM_VABDfq = 2034, + ARM_VABDhd = 2035, + ARM_VABDhq = 2036, + ARM_VABDsv16i8 = 2037, + ARM_VABDsv2i32 = 2038, + ARM_VABDsv4i16 = 2039, + ARM_VABDsv4i32 = 2040, + ARM_VABDsv8i16 = 2041, + ARM_VABDsv8i8 = 2042, + ARM_VABDuv16i8 = 2043, + ARM_VABDuv2i32 = 2044, + ARM_VABDuv4i16 = 2045, + ARM_VABDuv4i32 = 2046, + ARM_VABDuv8i16 = 2047, + ARM_VABDuv8i8 = 2048, + ARM_VABSD = 2049, + ARM_VABSH = 2050, + ARM_VABSS = 2051, + ARM_VABSfd = 2052, + ARM_VABSfq = 2053, + ARM_VABShd = 2054, + ARM_VABShq = 2055, + ARM_VABSv16i8 = 2056, + ARM_VABSv2i32 = 2057, + ARM_VABSv4i16 = 2058, + ARM_VABSv4i32 = 2059, + ARM_VABSv8i16 = 2060, + ARM_VABSv8i8 = 2061, + ARM_VACGEfd = 2062, + ARM_VACGEfq = 2063, + ARM_VACGEhd = 2064, + ARM_VACGEhq = 2065, + ARM_VACGTfd = 2066, + ARM_VACGTfq = 2067, + ARM_VACGThd = 2068, + ARM_VACGThq = 2069, + ARM_VADDD = 2070, + ARM_VADDH = 2071, + ARM_VADDHNv2i32 = 2072, + ARM_VADDHNv4i16 = 2073, + ARM_VADDHNv8i8 = 2074, + ARM_VADDLsv2i64 = 2075, + ARM_VADDLsv4i32 = 2076, + ARM_VADDLsv8i16 = 2077, + ARM_VADDLuv2i64 = 2078, + ARM_VADDLuv4i32 = 2079, + ARM_VADDLuv8i16 = 2080, + ARM_VADDS = 2081, + ARM_VADDWsv2i64 = 2082, + ARM_VADDWsv4i32 = 2083, + ARM_VADDWsv8i16 = 2084, + ARM_VADDWuv2i64 = 2085, + ARM_VADDWuv4i32 = 2086, + ARM_VADDWuv8i16 = 2087, + ARM_VADDfd = 2088, + ARM_VADDfq = 2089, + ARM_VADDhd = 2090, + ARM_VADDhq = 2091, + ARM_VADDv16i8 = 2092, + ARM_VADDv1i64 = 2093, + ARM_VADDv2i32 = 2094, + ARM_VADDv2i64 = 2095, + ARM_VADDv4i16 = 2096, + ARM_VADDv4i32 = 2097, + ARM_VADDv8i16 = 2098, + ARM_VADDv8i8 = 2099, + ARM_VANDd = 2100, + ARM_VANDq = 2101, + ARM_VBF16MALBQ = 2102, + ARM_VBF16MALBQI = 2103, + ARM_VBF16MALTQ = 2104, + ARM_VBF16MALTQI = 2105, + ARM_VBICd = 2106, + ARM_VBICiv2i32 = 2107, + ARM_VBICiv4i16 = 2108, + ARM_VBICiv4i32 = 2109, + ARM_VBICiv8i16 = 2110, + ARM_VBICq = 2111, + ARM_VBIFd = 2112, + ARM_VBIFq = 2113, + ARM_VBITd = 2114, + ARM_VBITq = 2115, + ARM_VBSLd = 2116, + ARM_VBSLq = 2117, + ARM_VBSPd = 2118, + ARM_VBSPq = 2119, + ARM_VCADDv2f32 = 2120, + ARM_VCADDv4f16 = 2121, + ARM_VCADDv4f32 = 2122, + ARM_VCADDv8f16 = 2123, + ARM_VCEQfd = 2124, + ARM_VCEQfq = 2125, + ARM_VCEQhd = 2126, + ARM_VCEQhq = 2127, + ARM_VCEQv16i8 = 2128, + ARM_VCEQv2i32 = 2129, + ARM_VCEQv4i16 = 2130, + ARM_VCEQv4i32 = 2131, + ARM_VCEQv8i16 = 2132, + ARM_VCEQv8i8 = 2133, + ARM_VCEQzv16i8 = 2134, + ARM_VCEQzv2f32 = 2135, + ARM_VCEQzv2i32 = 2136, + ARM_VCEQzv4f16 = 2137, + ARM_VCEQzv4f32 = 2138, + ARM_VCEQzv4i16 = 2139, + ARM_VCEQzv4i32 = 2140, + ARM_VCEQzv8f16 = 2141, + ARM_VCEQzv8i16 = 2142, + ARM_VCEQzv8i8 = 2143, + ARM_VCGEfd = 2144, + ARM_VCGEfq = 2145, + ARM_VCGEhd = 2146, + ARM_VCGEhq = 2147, + ARM_VCGEsv16i8 = 2148, + ARM_VCGEsv2i32 = 2149, + ARM_VCGEsv4i16 = 2150, + ARM_VCGEsv4i32 = 2151, + ARM_VCGEsv8i16 = 2152, + ARM_VCGEsv8i8 = 2153, + ARM_VCGEuv16i8 = 2154, + ARM_VCGEuv2i32 = 2155, + ARM_VCGEuv4i16 = 2156, + ARM_VCGEuv4i32 = 2157, + ARM_VCGEuv8i16 = 2158, + ARM_VCGEuv8i8 = 2159, + ARM_VCGEzv16i8 = 2160, + ARM_VCGEzv2f32 = 2161, + ARM_VCGEzv2i32 = 2162, + ARM_VCGEzv4f16 = 2163, + ARM_VCGEzv4f32 = 2164, + ARM_VCGEzv4i16 = 2165, + ARM_VCGEzv4i32 = 2166, + ARM_VCGEzv8f16 = 2167, + ARM_VCGEzv8i16 = 2168, + ARM_VCGEzv8i8 = 2169, + ARM_VCGTfd = 2170, + ARM_VCGTfq = 2171, + ARM_VCGThd = 2172, + ARM_VCGThq = 2173, + ARM_VCGTsv16i8 = 2174, + ARM_VCGTsv2i32 = 2175, + ARM_VCGTsv4i16 = 2176, + ARM_VCGTsv4i32 = 2177, + ARM_VCGTsv8i16 = 2178, + ARM_VCGTsv8i8 = 2179, + ARM_VCGTuv16i8 = 2180, + ARM_VCGTuv2i32 = 2181, + ARM_VCGTuv4i16 = 2182, + ARM_VCGTuv4i32 = 2183, + ARM_VCGTuv8i16 = 2184, + ARM_VCGTuv8i8 = 2185, + ARM_VCGTzv16i8 = 2186, + ARM_VCGTzv2f32 = 2187, + ARM_VCGTzv2i32 = 2188, + ARM_VCGTzv4f16 = 2189, + ARM_VCGTzv4f32 = 2190, + ARM_VCGTzv4i16 = 2191, + ARM_VCGTzv4i32 = 2192, + ARM_VCGTzv8f16 = 2193, + ARM_VCGTzv8i16 = 2194, + ARM_VCGTzv8i8 = 2195, + ARM_VCLEzv16i8 = 2196, + ARM_VCLEzv2f32 = 2197, + ARM_VCLEzv2i32 = 2198, + ARM_VCLEzv4f16 = 2199, + ARM_VCLEzv4f32 = 2200, + ARM_VCLEzv4i16 = 2201, + ARM_VCLEzv4i32 = 2202, + ARM_VCLEzv8f16 = 2203, + ARM_VCLEzv8i16 = 2204, + ARM_VCLEzv8i8 = 2205, + ARM_VCLSv16i8 = 2206, + ARM_VCLSv2i32 = 2207, + ARM_VCLSv4i16 = 2208, + ARM_VCLSv4i32 = 2209, + ARM_VCLSv8i16 = 2210, + ARM_VCLSv8i8 = 2211, + ARM_VCLTzv16i8 = 2212, + ARM_VCLTzv2f32 = 2213, + ARM_VCLTzv2i32 = 2214, + ARM_VCLTzv4f16 = 2215, + ARM_VCLTzv4f32 = 2216, + ARM_VCLTzv4i16 = 2217, + ARM_VCLTzv4i32 = 2218, + ARM_VCLTzv8f16 = 2219, + ARM_VCLTzv8i16 = 2220, + ARM_VCLTzv8i8 = 2221, + ARM_VCLZv16i8 = 2222, + ARM_VCLZv2i32 = 2223, + ARM_VCLZv4i16 = 2224, + ARM_VCLZv4i32 = 2225, + ARM_VCLZv8i16 = 2226, + ARM_VCLZv8i8 = 2227, + ARM_VCMLAv2f32 = 2228, + ARM_VCMLAv2f32_indexed = 2229, + ARM_VCMLAv4f16 = 2230, + ARM_VCMLAv4f16_indexed = 2231, + ARM_VCMLAv4f32 = 2232, + ARM_VCMLAv4f32_indexed = 2233, + ARM_VCMLAv8f16 = 2234, + ARM_VCMLAv8f16_indexed = 2235, + ARM_VCMPD = 2236, + ARM_VCMPED = 2237, + ARM_VCMPEH = 2238, + ARM_VCMPES = 2239, + ARM_VCMPEZD = 2240, + ARM_VCMPEZH = 2241, + ARM_VCMPEZS = 2242, + ARM_VCMPH = 2243, + ARM_VCMPS = 2244, + ARM_VCMPZD = 2245, + ARM_VCMPZH = 2246, + ARM_VCMPZS = 2247, + ARM_VCNTd = 2248, + ARM_VCNTq = 2249, + ARM_VCVTANSDf = 2250, + ARM_VCVTANSDh = 2251, + ARM_VCVTANSQf = 2252, + ARM_VCVTANSQh = 2253, + ARM_VCVTANUDf = 2254, + ARM_VCVTANUDh = 2255, + ARM_VCVTANUQf = 2256, + ARM_VCVTANUQh = 2257, + ARM_VCVTASD = 2258, + ARM_VCVTASH = 2259, + ARM_VCVTASS = 2260, + ARM_VCVTAUD = 2261, + ARM_VCVTAUH = 2262, + ARM_VCVTAUS = 2263, + ARM_VCVTBDH = 2264, + ARM_VCVTBHD = 2265, + ARM_VCVTBHS = 2266, + ARM_VCVTBSH = 2267, + ARM_VCVTDS = 2268, + ARM_VCVTMNSDf = 2269, + ARM_VCVTMNSDh = 2270, + ARM_VCVTMNSQf = 2271, + ARM_VCVTMNSQh = 2272, + ARM_VCVTMNUDf = 2273, + ARM_VCVTMNUDh = 2274, + ARM_VCVTMNUQf = 2275, + ARM_VCVTMNUQh = 2276, + ARM_VCVTMSD = 2277, + ARM_VCVTMSH = 2278, + ARM_VCVTMSS = 2279, + ARM_VCVTMUD = 2280, + ARM_VCVTMUH = 2281, + ARM_VCVTMUS = 2282, + ARM_VCVTNNSDf = 2283, + ARM_VCVTNNSDh = 2284, + ARM_VCVTNNSQf = 2285, + ARM_VCVTNNSQh = 2286, + ARM_VCVTNNUDf = 2287, + ARM_VCVTNNUDh = 2288, + ARM_VCVTNNUQf = 2289, + ARM_VCVTNNUQh = 2290, + ARM_VCVTNSD = 2291, + ARM_VCVTNSH = 2292, + ARM_VCVTNSS = 2293, + ARM_VCVTNUD = 2294, + ARM_VCVTNUH = 2295, + ARM_VCVTNUS = 2296, + ARM_VCVTPNSDf = 2297, + ARM_VCVTPNSDh = 2298, + ARM_VCVTPNSQf = 2299, + ARM_VCVTPNSQh = 2300, + ARM_VCVTPNUDf = 2301, + ARM_VCVTPNUDh = 2302, + ARM_VCVTPNUQf = 2303, + ARM_VCVTPNUQh = 2304, + ARM_VCVTPSD = 2305, + ARM_VCVTPSH = 2306, + ARM_VCVTPSS = 2307, + ARM_VCVTPUD = 2308, + ARM_VCVTPUH = 2309, + ARM_VCVTPUS = 2310, + ARM_VCVTSD = 2311, + ARM_VCVTTDH = 2312, + ARM_VCVTTHD = 2313, + ARM_VCVTTHS = 2314, + ARM_VCVTTSH = 2315, + ARM_VCVTf2h = 2316, + ARM_VCVTf2sd = 2317, + ARM_VCVTf2sq = 2318, + ARM_VCVTf2ud = 2319, + ARM_VCVTf2uq = 2320, + ARM_VCVTf2xsd = 2321, + ARM_VCVTf2xsq = 2322, + ARM_VCVTf2xud = 2323, + ARM_VCVTf2xuq = 2324, + ARM_VCVTh2f = 2325, + ARM_VCVTh2sd = 2326, + ARM_VCVTh2sq = 2327, + ARM_VCVTh2ud = 2328, + ARM_VCVTh2uq = 2329, + ARM_VCVTh2xsd = 2330, + ARM_VCVTh2xsq = 2331, + ARM_VCVTh2xud = 2332, + ARM_VCVTh2xuq = 2333, + ARM_VCVTs2fd = 2334, + ARM_VCVTs2fq = 2335, + ARM_VCVTs2hd = 2336, + ARM_VCVTs2hq = 2337, + ARM_VCVTu2fd = 2338, + ARM_VCVTu2fq = 2339, + ARM_VCVTu2hd = 2340, + ARM_VCVTu2hq = 2341, + ARM_VCVTxs2fd = 2342, + ARM_VCVTxs2fq = 2343, + ARM_VCVTxs2hd = 2344, + ARM_VCVTxs2hq = 2345, + ARM_VCVTxu2fd = 2346, + ARM_VCVTxu2fq = 2347, + ARM_VCVTxu2hd = 2348, + ARM_VCVTxu2hq = 2349, + ARM_VDIVD = 2350, + ARM_VDIVH = 2351, + ARM_VDIVS = 2352, + ARM_VDUP16d = 2353, + ARM_VDUP16q = 2354, + ARM_VDUP32d = 2355, + ARM_VDUP32q = 2356, + ARM_VDUP8d = 2357, + ARM_VDUP8q = 2358, + ARM_VDUPLN16d = 2359, + ARM_VDUPLN16q = 2360, + ARM_VDUPLN32d = 2361, + ARM_VDUPLN32q = 2362, + ARM_VDUPLN8d = 2363, + ARM_VDUPLN8q = 2364, + ARM_VEORd = 2365, + ARM_VEORq = 2366, + ARM_VEXTd16 = 2367, + ARM_VEXTd32 = 2368, + ARM_VEXTd8 = 2369, + ARM_VEXTq16 = 2370, + ARM_VEXTq32 = 2371, + ARM_VEXTq64 = 2372, + ARM_VEXTq8 = 2373, + ARM_VFMAD = 2374, + ARM_VFMAH = 2375, + ARM_VFMALD = 2376, + ARM_VFMALDI = 2377, + ARM_VFMALQ = 2378, + ARM_VFMALQI = 2379, + ARM_VFMAS = 2380, + ARM_VFMAfd = 2381, + ARM_VFMAfq = 2382, + ARM_VFMAhd = 2383, + ARM_VFMAhq = 2384, + ARM_VFMSD = 2385, + ARM_VFMSH = 2386, + ARM_VFMSLD = 2387, + ARM_VFMSLDI = 2388, + ARM_VFMSLQ = 2389, + ARM_VFMSLQI = 2390, + ARM_VFMSS = 2391, + ARM_VFMSfd = 2392, + ARM_VFMSfq = 2393, + ARM_VFMShd = 2394, + ARM_VFMShq = 2395, + ARM_VFNMAD = 2396, + ARM_VFNMAH = 2397, + ARM_VFNMAS = 2398, + ARM_VFNMSD = 2399, + ARM_VFNMSH = 2400, + ARM_VFNMSS = 2401, + ARM_VFP_VMAXNMD = 2402, + ARM_VFP_VMAXNMH = 2403, + ARM_VFP_VMAXNMS = 2404, + ARM_VFP_VMINNMD = 2405, + ARM_VFP_VMINNMH = 2406, + ARM_VFP_VMINNMS = 2407, + ARM_VGETLNi32 = 2408, + ARM_VGETLNs16 = 2409, + ARM_VGETLNs8 = 2410, + ARM_VGETLNu16 = 2411, + ARM_VGETLNu8 = 2412, + ARM_VHADDsv16i8 = 2413, + ARM_VHADDsv2i32 = 2414, + ARM_VHADDsv4i16 = 2415, + ARM_VHADDsv4i32 = 2416, + ARM_VHADDsv8i16 = 2417, + ARM_VHADDsv8i8 = 2418, + ARM_VHADDuv16i8 = 2419, + ARM_VHADDuv2i32 = 2420, + ARM_VHADDuv4i16 = 2421, + ARM_VHADDuv4i32 = 2422, + ARM_VHADDuv8i16 = 2423, + ARM_VHADDuv8i8 = 2424, + ARM_VHSUBsv16i8 = 2425, + ARM_VHSUBsv2i32 = 2426, + ARM_VHSUBsv4i16 = 2427, + ARM_VHSUBsv4i32 = 2428, + ARM_VHSUBsv8i16 = 2429, + ARM_VHSUBsv8i8 = 2430, + ARM_VHSUBuv16i8 = 2431, + ARM_VHSUBuv2i32 = 2432, + ARM_VHSUBuv4i16 = 2433, + ARM_VHSUBuv4i32 = 2434, + ARM_VHSUBuv8i16 = 2435, + ARM_VHSUBuv8i8 = 2436, + ARM_VINSH = 2437, + ARM_VJCVT = 2438, + ARM_VLD1DUPd16 = 2439, + ARM_VLD1DUPd16wb_fixed = 2440, + ARM_VLD1DUPd16wb_register = 2441, + ARM_VLD1DUPd32 = 2442, + ARM_VLD1DUPd32wb_fixed = 2443, + ARM_VLD1DUPd32wb_register = 2444, + ARM_VLD1DUPd8 = 2445, + ARM_VLD1DUPd8wb_fixed = 2446, + ARM_VLD1DUPd8wb_register = 2447, + ARM_VLD1DUPq16 = 2448, + ARM_VLD1DUPq16wb_fixed = 2449, + ARM_VLD1DUPq16wb_register = 2450, + ARM_VLD1DUPq32 = 2451, + ARM_VLD1DUPq32wb_fixed = 2452, + ARM_VLD1DUPq32wb_register = 2453, + ARM_VLD1DUPq8 = 2454, + ARM_VLD1DUPq8wb_fixed = 2455, + ARM_VLD1DUPq8wb_register = 2456, + ARM_VLD1LNd16 = 2457, + ARM_VLD1LNd16_UPD = 2458, + ARM_VLD1LNd32 = 2459, + ARM_VLD1LNd32_UPD = 2460, + ARM_VLD1LNd8 = 2461, + ARM_VLD1LNd8_UPD = 2462, + ARM_VLD1LNq16Pseudo = 2463, + ARM_VLD1LNq16Pseudo_UPD = 2464, + ARM_VLD1LNq32Pseudo = 2465, + ARM_VLD1LNq32Pseudo_UPD = 2466, + ARM_VLD1LNq8Pseudo = 2467, + ARM_VLD1LNq8Pseudo_UPD = 2468, + ARM_VLD1d16 = 2469, + ARM_VLD1d16Q = 2470, + ARM_VLD1d16QPseudo = 2471, + ARM_VLD1d16QPseudoWB_fixed = 2472, + ARM_VLD1d16QPseudoWB_register = 2473, + ARM_VLD1d16Qwb_fixed = 2474, + ARM_VLD1d16Qwb_register = 2475, + ARM_VLD1d16T = 2476, + ARM_VLD1d16TPseudo = 2477, + ARM_VLD1d16TPseudoWB_fixed = 2478, + ARM_VLD1d16TPseudoWB_register = 2479, + ARM_VLD1d16Twb_fixed = 2480, + ARM_VLD1d16Twb_register = 2481, + ARM_VLD1d16wb_fixed = 2482, + ARM_VLD1d16wb_register = 2483, + ARM_VLD1d32 = 2484, + ARM_VLD1d32Q = 2485, + ARM_VLD1d32QPseudo = 2486, + ARM_VLD1d32QPseudoWB_fixed = 2487, + ARM_VLD1d32QPseudoWB_register = 2488, + ARM_VLD1d32Qwb_fixed = 2489, + ARM_VLD1d32Qwb_register = 2490, + ARM_VLD1d32T = 2491, + ARM_VLD1d32TPseudo = 2492, + ARM_VLD1d32TPseudoWB_fixed = 2493, + ARM_VLD1d32TPseudoWB_register = 2494, + ARM_VLD1d32Twb_fixed = 2495, + ARM_VLD1d32Twb_register = 2496, + ARM_VLD1d32wb_fixed = 2497, + ARM_VLD1d32wb_register = 2498, + ARM_VLD1d64 = 2499, + ARM_VLD1d64Q = 2500, + ARM_VLD1d64QPseudo = 2501, + ARM_VLD1d64QPseudoWB_fixed = 2502, + ARM_VLD1d64QPseudoWB_register = 2503, + ARM_VLD1d64Qwb_fixed = 2504, + ARM_VLD1d64Qwb_register = 2505, + ARM_VLD1d64T = 2506, + ARM_VLD1d64TPseudo = 2507, + ARM_VLD1d64TPseudoWB_fixed = 2508, + ARM_VLD1d64TPseudoWB_register = 2509, + ARM_VLD1d64Twb_fixed = 2510, + ARM_VLD1d64Twb_register = 2511, + ARM_VLD1d64wb_fixed = 2512, + ARM_VLD1d64wb_register = 2513, + ARM_VLD1d8 = 2514, + ARM_VLD1d8Q = 2515, + ARM_VLD1d8QPseudo = 2516, + ARM_VLD1d8QPseudoWB_fixed = 2517, + ARM_VLD1d8QPseudoWB_register = 2518, + ARM_VLD1d8Qwb_fixed = 2519, + ARM_VLD1d8Qwb_register = 2520, + ARM_VLD1d8T = 2521, + ARM_VLD1d8TPseudo = 2522, + ARM_VLD1d8TPseudoWB_fixed = 2523, + ARM_VLD1d8TPseudoWB_register = 2524, + ARM_VLD1d8Twb_fixed = 2525, + ARM_VLD1d8Twb_register = 2526, + ARM_VLD1d8wb_fixed = 2527, + ARM_VLD1d8wb_register = 2528, + ARM_VLD1q16 = 2529, + ARM_VLD1q16HighQPseudo = 2530, + ARM_VLD1q16HighQPseudo_UPD = 2531, + ARM_VLD1q16HighTPseudo = 2532, + ARM_VLD1q16HighTPseudo_UPD = 2533, + ARM_VLD1q16LowQPseudo_UPD = 2534, + ARM_VLD1q16LowTPseudo_UPD = 2535, + ARM_VLD1q16wb_fixed = 2536, + ARM_VLD1q16wb_register = 2537, + ARM_VLD1q32 = 2538, + ARM_VLD1q32HighQPseudo = 2539, + ARM_VLD1q32HighQPseudo_UPD = 2540, + ARM_VLD1q32HighTPseudo = 2541, + ARM_VLD1q32HighTPseudo_UPD = 2542, + ARM_VLD1q32LowQPseudo_UPD = 2543, + ARM_VLD1q32LowTPseudo_UPD = 2544, + ARM_VLD1q32wb_fixed = 2545, + ARM_VLD1q32wb_register = 2546, + ARM_VLD1q64 = 2547, + ARM_VLD1q64HighQPseudo = 2548, + ARM_VLD1q64HighQPseudo_UPD = 2549, + ARM_VLD1q64HighTPseudo = 2550, + ARM_VLD1q64HighTPseudo_UPD = 2551, + ARM_VLD1q64LowQPseudo_UPD = 2552, + ARM_VLD1q64LowTPseudo_UPD = 2553, + ARM_VLD1q64wb_fixed = 2554, + ARM_VLD1q64wb_register = 2555, + ARM_VLD1q8 = 2556, + ARM_VLD1q8HighQPseudo = 2557, + ARM_VLD1q8HighQPseudo_UPD = 2558, + ARM_VLD1q8HighTPseudo = 2559, + ARM_VLD1q8HighTPseudo_UPD = 2560, + ARM_VLD1q8LowQPseudo_UPD = 2561, + ARM_VLD1q8LowTPseudo_UPD = 2562, + ARM_VLD1q8wb_fixed = 2563, + ARM_VLD1q8wb_register = 2564, + ARM_VLD2DUPd16 = 2565, + ARM_VLD2DUPd16wb_fixed = 2566, + ARM_VLD2DUPd16wb_register = 2567, + ARM_VLD2DUPd16x2 = 2568, + ARM_VLD2DUPd16x2wb_fixed = 2569, + ARM_VLD2DUPd16x2wb_register = 2570, + ARM_VLD2DUPd32 = 2571, + ARM_VLD2DUPd32wb_fixed = 2572, + ARM_VLD2DUPd32wb_register = 2573, + ARM_VLD2DUPd32x2 = 2574, + ARM_VLD2DUPd32x2wb_fixed = 2575, + ARM_VLD2DUPd32x2wb_register = 2576, + ARM_VLD2DUPd8 = 2577, + ARM_VLD2DUPd8wb_fixed = 2578, + ARM_VLD2DUPd8wb_register = 2579, + ARM_VLD2DUPd8x2 = 2580, + ARM_VLD2DUPd8x2wb_fixed = 2581, + ARM_VLD2DUPd8x2wb_register = 2582, + ARM_VLD2DUPq16EvenPseudo = 2583, + ARM_VLD2DUPq16OddPseudo = 2584, + ARM_VLD2DUPq16OddPseudoWB_fixed = 2585, + ARM_VLD2DUPq16OddPseudoWB_register = 2586, + ARM_VLD2DUPq32EvenPseudo = 2587, + ARM_VLD2DUPq32OddPseudo = 2588, + ARM_VLD2DUPq32OddPseudoWB_fixed = 2589, + ARM_VLD2DUPq32OddPseudoWB_register = 2590, + ARM_VLD2DUPq8EvenPseudo = 2591, + ARM_VLD2DUPq8OddPseudo = 2592, + ARM_VLD2DUPq8OddPseudoWB_fixed = 2593, + ARM_VLD2DUPq8OddPseudoWB_register = 2594, + ARM_VLD2LNd16 = 2595, + ARM_VLD2LNd16Pseudo = 2596, + ARM_VLD2LNd16Pseudo_UPD = 2597, + ARM_VLD2LNd16_UPD = 2598, + ARM_VLD2LNd32 = 2599, + ARM_VLD2LNd32Pseudo = 2600, + ARM_VLD2LNd32Pseudo_UPD = 2601, + ARM_VLD2LNd32_UPD = 2602, + ARM_VLD2LNd8 = 2603, + ARM_VLD2LNd8Pseudo = 2604, + ARM_VLD2LNd8Pseudo_UPD = 2605, + ARM_VLD2LNd8_UPD = 2606, + ARM_VLD2LNq16 = 2607, + ARM_VLD2LNq16Pseudo = 2608, + ARM_VLD2LNq16Pseudo_UPD = 2609, + ARM_VLD2LNq16_UPD = 2610, + ARM_VLD2LNq32 = 2611, + ARM_VLD2LNq32Pseudo = 2612, + ARM_VLD2LNq32Pseudo_UPD = 2613, + ARM_VLD2LNq32_UPD = 2614, + ARM_VLD2b16 = 2615, + ARM_VLD2b16wb_fixed = 2616, + ARM_VLD2b16wb_register = 2617, + ARM_VLD2b32 = 2618, + ARM_VLD2b32wb_fixed = 2619, + ARM_VLD2b32wb_register = 2620, + ARM_VLD2b8 = 2621, + ARM_VLD2b8wb_fixed = 2622, + ARM_VLD2b8wb_register = 2623, + ARM_VLD2d16 = 2624, + ARM_VLD2d16wb_fixed = 2625, + ARM_VLD2d16wb_register = 2626, + ARM_VLD2d32 = 2627, + ARM_VLD2d32wb_fixed = 2628, + ARM_VLD2d32wb_register = 2629, + ARM_VLD2d8 = 2630, + ARM_VLD2d8wb_fixed = 2631, + ARM_VLD2d8wb_register = 2632, + ARM_VLD2q16 = 2633, + ARM_VLD2q16Pseudo = 2634, + ARM_VLD2q16PseudoWB_fixed = 2635, + ARM_VLD2q16PseudoWB_register = 2636, + ARM_VLD2q16wb_fixed = 2637, + ARM_VLD2q16wb_register = 2638, + ARM_VLD2q32 = 2639, + ARM_VLD2q32Pseudo = 2640, + ARM_VLD2q32PseudoWB_fixed = 2641, + ARM_VLD2q32PseudoWB_register = 2642, + ARM_VLD2q32wb_fixed = 2643, + ARM_VLD2q32wb_register = 2644, + ARM_VLD2q8 = 2645, + ARM_VLD2q8Pseudo = 2646, + ARM_VLD2q8PseudoWB_fixed = 2647, + ARM_VLD2q8PseudoWB_register = 2648, + ARM_VLD2q8wb_fixed = 2649, + ARM_VLD2q8wb_register = 2650, + ARM_VLD3DUPd16 = 2651, + ARM_VLD3DUPd16Pseudo = 2652, + ARM_VLD3DUPd16Pseudo_UPD = 2653, + ARM_VLD3DUPd16_UPD = 2654, + ARM_VLD3DUPd32 = 2655, + ARM_VLD3DUPd32Pseudo = 2656, + ARM_VLD3DUPd32Pseudo_UPD = 2657, + ARM_VLD3DUPd32_UPD = 2658, + ARM_VLD3DUPd8 = 2659, + ARM_VLD3DUPd8Pseudo = 2660, + ARM_VLD3DUPd8Pseudo_UPD = 2661, + ARM_VLD3DUPd8_UPD = 2662, + ARM_VLD3DUPq16 = 2663, + ARM_VLD3DUPq16EvenPseudo = 2664, + ARM_VLD3DUPq16OddPseudo = 2665, + ARM_VLD3DUPq16OddPseudo_UPD = 2666, + ARM_VLD3DUPq16_UPD = 2667, + ARM_VLD3DUPq32 = 2668, + ARM_VLD3DUPq32EvenPseudo = 2669, + ARM_VLD3DUPq32OddPseudo = 2670, + ARM_VLD3DUPq32OddPseudo_UPD = 2671, + ARM_VLD3DUPq32_UPD = 2672, + ARM_VLD3DUPq8 = 2673, + ARM_VLD3DUPq8EvenPseudo = 2674, + ARM_VLD3DUPq8OddPseudo = 2675, + ARM_VLD3DUPq8OddPseudo_UPD = 2676, + ARM_VLD3DUPq8_UPD = 2677, + ARM_VLD3LNd16 = 2678, + ARM_VLD3LNd16Pseudo = 2679, + ARM_VLD3LNd16Pseudo_UPD = 2680, + ARM_VLD3LNd16_UPD = 2681, + ARM_VLD3LNd32 = 2682, + ARM_VLD3LNd32Pseudo = 2683, + ARM_VLD3LNd32Pseudo_UPD = 2684, + ARM_VLD3LNd32_UPD = 2685, + ARM_VLD3LNd8 = 2686, + ARM_VLD3LNd8Pseudo = 2687, + ARM_VLD3LNd8Pseudo_UPD = 2688, + ARM_VLD3LNd8_UPD = 2689, + ARM_VLD3LNq16 = 2690, + ARM_VLD3LNq16Pseudo = 2691, + ARM_VLD3LNq16Pseudo_UPD = 2692, + ARM_VLD3LNq16_UPD = 2693, + ARM_VLD3LNq32 = 2694, + ARM_VLD3LNq32Pseudo = 2695, + ARM_VLD3LNq32Pseudo_UPD = 2696, + ARM_VLD3LNq32_UPD = 2697, + ARM_VLD3d16 = 2698, + ARM_VLD3d16Pseudo = 2699, + ARM_VLD3d16Pseudo_UPD = 2700, + ARM_VLD3d16_UPD = 2701, + ARM_VLD3d32 = 2702, + ARM_VLD3d32Pseudo = 2703, + ARM_VLD3d32Pseudo_UPD = 2704, + ARM_VLD3d32_UPD = 2705, + ARM_VLD3d8 = 2706, + ARM_VLD3d8Pseudo = 2707, + ARM_VLD3d8Pseudo_UPD = 2708, + ARM_VLD3d8_UPD = 2709, + ARM_VLD3q16 = 2710, + ARM_VLD3q16Pseudo_UPD = 2711, + ARM_VLD3q16_UPD = 2712, + ARM_VLD3q16oddPseudo = 2713, + ARM_VLD3q16oddPseudo_UPD = 2714, + ARM_VLD3q32 = 2715, + ARM_VLD3q32Pseudo_UPD = 2716, + ARM_VLD3q32_UPD = 2717, + ARM_VLD3q32oddPseudo = 2718, + ARM_VLD3q32oddPseudo_UPD = 2719, + ARM_VLD3q8 = 2720, + ARM_VLD3q8Pseudo_UPD = 2721, + ARM_VLD3q8_UPD = 2722, + ARM_VLD3q8oddPseudo = 2723, + ARM_VLD3q8oddPseudo_UPD = 2724, + ARM_VLD4DUPd16 = 2725, + ARM_VLD4DUPd16Pseudo = 2726, + ARM_VLD4DUPd16Pseudo_UPD = 2727, + ARM_VLD4DUPd16_UPD = 2728, + ARM_VLD4DUPd32 = 2729, + ARM_VLD4DUPd32Pseudo = 2730, + ARM_VLD4DUPd32Pseudo_UPD = 2731, + ARM_VLD4DUPd32_UPD = 2732, + ARM_VLD4DUPd8 = 2733, + ARM_VLD4DUPd8Pseudo = 2734, + ARM_VLD4DUPd8Pseudo_UPD = 2735, + ARM_VLD4DUPd8_UPD = 2736, + ARM_VLD4DUPq16 = 2737, + ARM_VLD4DUPq16EvenPseudo = 2738, + ARM_VLD4DUPq16OddPseudo = 2739, + ARM_VLD4DUPq16OddPseudo_UPD = 2740, + ARM_VLD4DUPq16_UPD = 2741, + ARM_VLD4DUPq32 = 2742, + ARM_VLD4DUPq32EvenPseudo = 2743, + ARM_VLD4DUPq32OddPseudo = 2744, + ARM_VLD4DUPq32OddPseudo_UPD = 2745, + ARM_VLD4DUPq32_UPD = 2746, + ARM_VLD4DUPq8 = 2747, + ARM_VLD4DUPq8EvenPseudo = 2748, + ARM_VLD4DUPq8OddPseudo = 2749, + ARM_VLD4DUPq8OddPseudo_UPD = 2750, + ARM_VLD4DUPq8_UPD = 2751, + ARM_VLD4LNd16 = 2752, + ARM_VLD4LNd16Pseudo = 2753, + ARM_VLD4LNd16Pseudo_UPD = 2754, + ARM_VLD4LNd16_UPD = 2755, + ARM_VLD4LNd32 = 2756, + ARM_VLD4LNd32Pseudo = 2757, + ARM_VLD4LNd32Pseudo_UPD = 2758, + ARM_VLD4LNd32_UPD = 2759, + ARM_VLD4LNd8 = 2760, + ARM_VLD4LNd8Pseudo = 2761, + ARM_VLD4LNd8Pseudo_UPD = 2762, + ARM_VLD4LNd8_UPD = 2763, + ARM_VLD4LNq16 = 2764, + ARM_VLD4LNq16Pseudo = 2765, + ARM_VLD4LNq16Pseudo_UPD = 2766, + ARM_VLD4LNq16_UPD = 2767, + ARM_VLD4LNq32 = 2768, + ARM_VLD4LNq32Pseudo = 2769, + ARM_VLD4LNq32Pseudo_UPD = 2770, + ARM_VLD4LNq32_UPD = 2771, + ARM_VLD4d16 = 2772, + ARM_VLD4d16Pseudo = 2773, + ARM_VLD4d16Pseudo_UPD = 2774, + ARM_VLD4d16_UPD = 2775, + ARM_VLD4d32 = 2776, + ARM_VLD4d32Pseudo = 2777, + ARM_VLD4d32Pseudo_UPD = 2778, + ARM_VLD4d32_UPD = 2779, + ARM_VLD4d8 = 2780, + ARM_VLD4d8Pseudo = 2781, + ARM_VLD4d8Pseudo_UPD = 2782, + ARM_VLD4d8_UPD = 2783, + ARM_VLD4q16 = 2784, + ARM_VLD4q16Pseudo_UPD = 2785, + ARM_VLD4q16_UPD = 2786, + ARM_VLD4q16oddPseudo = 2787, + ARM_VLD4q16oddPseudo_UPD = 2788, + ARM_VLD4q32 = 2789, + ARM_VLD4q32Pseudo_UPD = 2790, + ARM_VLD4q32_UPD = 2791, + ARM_VLD4q32oddPseudo = 2792, + ARM_VLD4q32oddPseudo_UPD = 2793, + ARM_VLD4q8 = 2794, + ARM_VLD4q8Pseudo_UPD = 2795, + ARM_VLD4q8_UPD = 2796, + ARM_VLD4q8oddPseudo = 2797, + ARM_VLD4q8oddPseudo_UPD = 2798, + ARM_VLDMDDB_UPD = 2799, + ARM_VLDMDIA = 2800, + ARM_VLDMDIA_UPD = 2801, + ARM_VLDMQIA = 2802, + ARM_VLDMSDB_UPD = 2803, + ARM_VLDMSIA = 2804, + ARM_VLDMSIA_UPD = 2805, + ARM_VLDRD = 2806, + ARM_VLDRH = 2807, + ARM_VLDRS = 2808, + ARM_VLDR_FPCXTNS_off = 2809, + ARM_VLDR_FPCXTNS_post = 2810, + ARM_VLDR_FPCXTNS_pre = 2811, + ARM_VLDR_FPCXTS_off = 2812, + ARM_VLDR_FPCXTS_post = 2813, + ARM_VLDR_FPCXTS_pre = 2814, + ARM_VLDR_FPSCR_NZCVQC_off = 2815, + ARM_VLDR_FPSCR_NZCVQC_post = 2816, + ARM_VLDR_FPSCR_NZCVQC_pre = 2817, + ARM_VLDR_FPSCR_off = 2818, + ARM_VLDR_FPSCR_post = 2819, + ARM_VLDR_FPSCR_pre = 2820, + ARM_VLDR_P0_off = 2821, + ARM_VLDR_P0_post = 2822, + ARM_VLDR_P0_pre = 2823, + ARM_VLDR_VPR_off = 2824, + ARM_VLDR_VPR_post = 2825, + ARM_VLDR_VPR_pre = 2826, + ARM_VLLDM = 2827, + ARM_VLSTM = 2828, + ARM_VMAXfd = 2829, + ARM_VMAXfq = 2830, + ARM_VMAXhd = 2831, + ARM_VMAXhq = 2832, + ARM_VMAXsv16i8 = 2833, + ARM_VMAXsv2i32 = 2834, + ARM_VMAXsv4i16 = 2835, + ARM_VMAXsv4i32 = 2836, + ARM_VMAXsv8i16 = 2837, + ARM_VMAXsv8i8 = 2838, + ARM_VMAXuv16i8 = 2839, + ARM_VMAXuv2i32 = 2840, + ARM_VMAXuv4i16 = 2841, + ARM_VMAXuv4i32 = 2842, + ARM_VMAXuv8i16 = 2843, + ARM_VMAXuv8i8 = 2844, + ARM_VMINfd = 2845, + ARM_VMINfq = 2846, + ARM_VMINhd = 2847, + ARM_VMINhq = 2848, + ARM_VMINsv16i8 = 2849, + ARM_VMINsv2i32 = 2850, + ARM_VMINsv4i16 = 2851, + ARM_VMINsv4i32 = 2852, + ARM_VMINsv8i16 = 2853, + ARM_VMINsv8i8 = 2854, + ARM_VMINuv16i8 = 2855, + ARM_VMINuv2i32 = 2856, + ARM_VMINuv4i16 = 2857, + ARM_VMINuv4i32 = 2858, + ARM_VMINuv8i16 = 2859, + ARM_VMINuv8i8 = 2860, + ARM_VMLAD = 2861, + ARM_VMLAH = 2862, + ARM_VMLALslsv2i32 = 2863, + ARM_VMLALslsv4i16 = 2864, + ARM_VMLALsluv2i32 = 2865, + ARM_VMLALsluv4i16 = 2866, + ARM_VMLALsv2i64 = 2867, + ARM_VMLALsv4i32 = 2868, + ARM_VMLALsv8i16 = 2869, + ARM_VMLALuv2i64 = 2870, + ARM_VMLALuv4i32 = 2871, + ARM_VMLALuv8i16 = 2872, + ARM_VMLAS = 2873, + ARM_VMLAfd = 2874, + ARM_VMLAfq = 2875, + ARM_VMLAhd = 2876, + ARM_VMLAhq = 2877, + ARM_VMLAslfd = 2878, + ARM_VMLAslfq = 2879, + ARM_VMLAslhd = 2880, + ARM_VMLAslhq = 2881, + ARM_VMLAslv2i32 = 2882, + ARM_VMLAslv4i16 = 2883, + ARM_VMLAslv4i32 = 2884, + ARM_VMLAslv8i16 = 2885, + ARM_VMLAv16i8 = 2886, + ARM_VMLAv2i32 = 2887, + ARM_VMLAv4i16 = 2888, + ARM_VMLAv4i32 = 2889, + ARM_VMLAv8i16 = 2890, + ARM_VMLAv8i8 = 2891, + ARM_VMLSD = 2892, + ARM_VMLSH = 2893, + ARM_VMLSLslsv2i32 = 2894, + ARM_VMLSLslsv4i16 = 2895, + ARM_VMLSLsluv2i32 = 2896, + ARM_VMLSLsluv4i16 = 2897, + ARM_VMLSLsv2i64 = 2898, + ARM_VMLSLsv4i32 = 2899, + ARM_VMLSLsv8i16 = 2900, + ARM_VMLSLuv2i64 = 2901, + ARM_VMLSLuv4i32 = 2902, + ARM_VMLSLuv8i16 = 2903, + ARM_VMLSS = 2904, + ARM_VMLSfd = 2905, + ARM_VMLSfq = 2906, + ARM_VMLShd = 2907, + ARM_VMLShq = 2908, + ARM_VMLSslfd = 2909, + ARM_VMLSslfq = 2910, + ARM_VMLSslhd = 2911, + ARM_VMLSslhq = 2912, + ARM_VMLSslv2i32 = 2913, + ARM_VMLSslv4i16 = 2914, + ARM_VMLSslv4i32 = 2915, + ARM_VMLSslv8i16 = 2916, + ARM_VMLSv16i8 = 2917, + ARM_VMLSv2i32 = 2918, + ARM_VMLSv4i16 = 2919, + ARM_VMLSv4i32 = 2920, + ARM_VMLSv8i16 = 2921, + ARM_VMLSv8i8 = 2922, + ARM_VMMLA = 2923, + ARM_VMOVD = 2924, + ARM_VMOVDRR = 2925, + ARM_VMOVH = 2926, + ARM_VMOVHR = 2927, + ARM_VMOVLsv2i64 = 2928, + ARM_VMOVLsv4i32 = 2929, + ARM_VMOVLsv8i16 = 2930, + ARM_VMOVLuv2i64 = 2931, + ARM_VMOVLuv4i32 = 2932, + ARM_VMOVLuv8i16 = 2933, + ARM_VMOVNv2i32 = 2934, + ARM_VMOVNv4i16 = 2935, + ARM_VMOVNv8i8 = 2936, + ARM_VMOVRH = 2937, + ARM_VMOVRRD = 2938, + ARM_VMOVRRS = 2939, + ARM_VMOVRS = 2940, + ARM_VMOVS = 2941, + ARM_VMOVSR = 2942, + ARM_VMOVSRR = 2943, + ARM_VMOVv16i8 = 2944, + ARM_VMOVv1i64 = 2945, + ARM_VMOVv2f32 = 2946, + ARM_VMOVv2i32 = 2947, + ARM_VMOVv2i64 = 2948, + ARM_VMOVv4f32 = 2949, + ARM_VMOVv4i16 = 2950, + ARM_VMOVv4i32 = 2951, + ARM_VMOVv8i16 = 2952, + ARM_VMOVv8i8 = 2953, + ARM_VMRS = 2954, + ARM_VMRS_FPCXTNS = 2955, + ARM_VMRS_FPCXTS = 2956, + ARM_VMRS_FPEXC = 2957, + ARM_VMRS_FPINST = 2958, + ARM_VMRS_FPINST2 = 2959, + ARM_VMRS_FPSCR_NZCVQC = 2960, + ARM_VMRS_FPSID = 2961, + ARM_VMRS_MVFR0 = 2962, + ARM_VMRS_MVFR1 = 2963, + ARM_VMRS_MVFR2 = 2964, + ARM_VMRS_P0 = 2965, + ARM_VMRS_VPR = 2966, + ARM_VMSR = 2967, + ARM_VMSR_FPCXTNS = 2968, + ARM_VMSR_FPCXTS = 2969, + ARM_VMSR_FPEXC = 2970, + ARM_VMSR_FPINST = 2971, + ARM_VMSR_FPINST2 = 2972, + ARM_VMSR_FPSCR_NZCVQC = 2973, + ARM_VMSR_FPSID = 2974, + ARM_VMSR_P0 = 2975, + ARM_VMSR_VPR = 2976, + ARM_VMULD = 2977, + ARM_VMULH = 2978, + ARM_VMULLp64 = 2979, + ARM_VMULLp8 = 2980, + ARM_VMULLslsv2i32 = 2981, + ARM_VMULLslsv4i16 = 2982, + ARM_VMULLsluv2i32 = 2983, + ARM_VMULLsluv4i16 = 2984, + ARM_VMULLsv2i64 = 2985, + ARM_VMULLsv4i32 = 2986, + ARM_VMULLsv8i16 = 2987, + ARM_VMULLuv2i64 = 2988, + ARM_VMULLuv4i32 = 2989, + ARM_VMULLuv8i16 = 2990, + ARM_VMULS = 2991, + ARM_VMULfd = 2992, + ARM_VMULfq = 2993, + ARM_VMULhd = 2994, + ARM_VMULhq = 2995, + ARM_VMULpd = 2996, + ARM_VMULpq = 2997, + ARM_VMULslfd = 2998, + ARM_VMULslfq = 2999, + ARM_VMULslhd = 3000, + ARM_VMULslhq = 3001, + ARM_VMULslv2i32 = 3002, + ARM_VMULslv4i16 = 3003, + ARM_VMULslv4i32 = 3004, + ARM_VMULslv8i16 = 3005, + ARM_VMULv16i8 = 3006, + ARM_VMULv2i32 = 3007, + ARM_VMULv4i16 = 3008, + ARM_VMULv4i32 = 3009, + ARM_VMULv8i16 = 3010, + ARM_VMULv8i8 = 3011, + ARM_VMVNd = 3012, + ARM_VMVNq = 3013, + ARM_VMVNv2i32 = 3014, + ARM_VMVNv4i16 = 3015, + ARM_VMVNv4i32 = 3016, + ARM_VMVNv8i16 = 3017, + ARM_VNEGD = 3018, + ARM_VNEGH = 3019, + ARM_VNEGS = 3020, + ARM_VNEGf32q = 3021, + ARM_VNEGfd = 3022, + ARM_VNEGhd = 3023, + ARM_VNEGhq = 3024, + ARM_VNEGs16d = 3025, + ARM_VNEGs16q = 3026, + ARM_VNEGs32d = 3027, + ARM_VNEGs32q = 3028, + ARM_VNEGs8d = 3029, + ARM_VNEGs8q = 3030, + ARM_VNMLAD = 3031, + ARM_VNMLAH = 3032, + ARM_VNMLAS = 3033, + ARM_VNMLSD = 3034, + ARM_VNMLSH = 3035, + ARM_VNMLSS = 3036, + ARM_VNMULD = 3037, + ARM_VNMULH = 3038, + ARM_VNMULS = 3039, + ARM_VORNd = 3040, + ARM_VORNq = 3041, + ARM_VORRd = 3042, + ARM_VORRiv2i32 = 3043, + ARM_VORRiv4i16 = 3044, + ARM_VORRiv4i32 = 3045, + ARM_VORRiv8i16 = 3046, + ARM_VORRq = 3047, + ARM_VPADALsv16i8 = 3048, + ARM_VPADALsv2i32 = 3049, + ARM_VPADALsv4i16 = 3050, + ARM_VPADALsv4i32 = 3051, + ARM_VPADALsv8i16 = 3052, + ARM_VPADALsv8i8 = 3053, + ARM_VPADALuv16i8 = 3054, + ARM_VPADALuv2i32 = 3055, + ARM_VPADALuv4i16 = 3056, + ARM_VPADALuv4i32 = 3057, + ARM_VPADALuv8i16 = 3058, + ARM_VPADALuv8i8 = 3059, + ARM_VPADDLsv16i8 = 3060, + ARM_VPADDLsv2i32 = 3061, + ARM_VPADDLsv4i16 = 3062, + ARM_VPADDLsv4i32 = 3063, + ARM_VPADDLsv8i16 = 3064, + ARM_VPADDLsv8i8 = 3065, + ARM_VPADDLuv16i8 = 3066, + ARM_VPADDLuv2i32 = 3067, + ARM_VPADDLuv4i16 = 3068, + ARM_VPADDLuv4i32 = 3069, + ARM_VPADDLuv8i16 = 3070, + ARM_VPADDLuv8i8 = 3071, + ARM_VPADDf = 3072, + ARM_VPADDh = 3073, + ARM_VPADDi16 = 3074, + ARM_VPADDi32 = 3075, + ARM_VPADDi8 = 3076, + ARM_VPMAXf = 3077, + ARM_VPMAXh = 3078, + ARM_VPMAXs16 = 3079, + ARM_VPMAXs32 = 3080, + ARM_VPMAXs8 = 3081, + ARM_VPMAXu16 = 3082, + ARM_VPMAXu32 = 3083, + ARM_VPMAXu8 = 3084, + ARM_VPMINf = 3085, + ARM_VPMINh = 3086, + ARM_VPMINs16 = 3087, + ARM_VPMINs32 = 3088, + ARM_VPMINs8 = 3089, + ARM_VPMINu16 = 3090, + ARM_VPMINu32 = 3091, + ARM_VPMINu8 = 3092, + ARM_VQABSv16i8 = 3093, + ARM_VQABSv2i32 = 3094, + ARM_VQABSv4i16 = 3095, + ARM_VQABSv4i32 = 3096, + ARM_VQABSv8i16 = 3097, + ARM_VQABSv8i8 = 3098, + ARM_VQADDsv16i8 = 3099, + ARM_VQADDsv1i64 = 3100, + ARM_VQADDsv2i32 = 3101, + ARM_VQADDsv2i64 = 3102, + ARM_VQADDsv4i16 = 3103, + ARM_VQADDsv4i32 = 3104, + ARM_VQADDsv8i16 = 3105, + ARM_VQADDsv8i8 = 3106, + ARM_VQADDuv16i8 = 3107, + ARM_VQADDuv1i64 = 3108, + ARM_VQADDuv2i32 = 3109, + ARM_VQADDuv2i64 = 3110, + ARM_VQADDuv4i16 = 3111, + ARM_VQADDuv4i32 = 3112, + ARM_VQADDuv8i16 = 3113, + ARM_VQADDuv8i8 = 3114, + ARM_VQDMLALslv2i32 = 3115, + ARM_VQDMLALslv4i16 = 3116, + ARM_VQDMLALv2i64 = 3117, + ARM_VQDMLALv4i32 = 3118, + ARM_VQDMLSLslv2i32 = 3119, + ARM_VQDMLSLslv4i16 = 3120, + ARM_VQDMLSLv2i64 = 3121, + ARM_VQDMLSLv4i32 = 3122, + ARM_VQDMULHslv2i32 = 3123, + ARM_VQDMULHslv4i16 = 3124, + ARM_VQDMULHslv4i32 = 3125, + ARM_VQDMULHslv8i16 = 3126, + ARM_VQDMULHv2i32 = 3127, + ARM_VQDMULHv4i16 = 3128, + ARM_VQDMULHv4i32 = 3129, + ARM_VQDMULHv8i16 = 3130, + ARM_VQDMULLslv2i32 = 3131, + ARM_VQDMULLslv4i16 = 3132, + ARM_VQDMULLv2i64 = 3133, + ARM_VQDMULLv4i32 = 3134, + ARM_VQMOVNsuv2i32 = 3135, + ARM_VQMOVNsuv4i16 = 3136, + ARM_VQMOVNsuv8i8 = 3137, + ARM_VQMOVNsv2i32 = 3138, + ARM_VQMOVNsv4i16 = 3139, + ARM_VQMOVNsv8i8 = 3140, + ARM_VQMOVNuv2i32 = 3141, + ARM_VQMOVNuv4i16 = 3142, + ARM_VQMOVNuv8i8 = 3143, + ARM_VQNEGv16i8 = 3144, + ARM_VQNEGv2i32 = 3145, + ARM_VQNEGv4i16 = 3146, + ARM_VQNEGv4i32 = 3147, + ARM_VQNEGv8i16 = 3148, + ARM_VQNEGv8i8 = 3149, + ARM_VQRDMLAHslv2i32 = 3150, + ARM_VQRDMLAHslv4i16 = 3151, + ARM_VQRDMLAHslv4i32 = 3152, + ARM_VQRDMLAHslv8i16 = 3153, + ARM_VQRDMLAHv2i32 = 3154, + ARM_VQRDMLAHv4i16 = 3155, + ARM_VQRDMLAHv4i32 = 3156, + ARM_VQRDMLAHv8i16 = 3157, + ARM_VQRDMLSHslv2i32 = 3158, + ARM_VQRDMLSHslv4i16 = 3159, + ARM_VQRDMLSHslv4i32 = 3160, + ARM_VQRDMLSHslv8i16 = 3161, + ARM_VQRDMLSHv2i32 = 3162, + ARM_VQRDMLSHv4i16 = 3163, + ARM_VQRDMLSHv4i32 = 3164, + ARM_VQRDMLSHv8i16 = 3165, + ARM_VQRDMULHslv2i32 = 3166, + ARM_VQRDMULHslv4i16 = 3167, + ARM_VQRDMULHslv4i32 = 3168, + ARM_VQRDMULHslv8i16 = 3169, + ARM_VQRDMULHv2i32 = 3170, + ARM_VQRDMULHv4i16 = 3171, + ARM_VQRDMULHv4i32 = 3172, + ARM_VQRDMULHv8i16 = 3173, + ARM_VQRSHLsv16i8 = 3174, + ARM_VQRSHLsv1i64 = 3175, + ARM_VQRSHLsv2i32 = 3176, + ARM_VQRSHLsv2i64 = 3177, + ARM_VQRSHLsv4i16 = 3178, + ARM_VQRSHLsv4i32 = 3179, + ARM_VQRSHLsv8i16 = 3180, + ARM_VQRSHLsv8i8 = 3181, + ARM_VQRSHLuv16i8 = 3182, + ARM_VQRSHLuv1i64 = 3183, + ARM_VQRSHLuv2i32 = 3184, + ARM_VQRSHLuv2i64 = 3185, + ARM_VQRSHLuv4i16 = 3186, + ARM_VQRSHLuv4i32 = 3187, + ARM_VQRSHLuv8i16 = 3188, + ARM_VQRSHLuv8i8 = 3189, + ARM_VQRSHRNsv2i32 = 3190, + ARM_VQRSHRNsv4i16 = 3191, + ARM_VQRSHRNsv8i8 = 3192, + ARM_VQRSHRNuv2i32 = 3193, + ARM_VQRSHRNuv4i16 = 3194, + ARM_VQRSHRNuv8i8 = 3195, + ARM_VQRSHRUNv2i32 = 3196, + ARM_VQRSHRUNv4i16 = 3197, + ARM_VQRSHRUNv8i8 = 3198, + ARM_VQSHLsiv16i8 = 3199, + ARM_VQSHLsiv1i64 = 3200, + ARM_VQSHLsiv2i32 = 3201, + ARM_VQSHLsiv2i64 = 3202, + ARM_VQSHLsiv4i16 = 3203, + ARM_VQSHLsiv4i32 = 3204, + ARM_VQSHLsiv8i16 = 3205, + ARM_VQSHLsiv8i8 = 3206, + ARM_VQSHLsuv16i8 = 3207, + ARM_VQSHLsuv1i64 = 3208, + ARM_VQSHLsuv2i32 = 3209, + ARM_VQSHLsuv2i64 = 3210, + ARM_VQSHLsuv4i16 = 3211, + ARM_VQSHLsuv4i32 = 3212, + ARM_VQSHLsuv8i16 = 3213, + ARM_VQSHLsuv8i8 = 3214, + ARM_VQSHLsv16i8 = 3215, + ARM_VQSHLsv1i64 = 3216, + ARM_VQSHLsv2i32 = 3217, + ARM_VQSHLsv2i64 = 3218, + ARM_VQSHLsv4i16 = 3219, + ARM_VQSHLsv4i32 = 3220, + ARM_VQSHLsv8i16 = 3221, + ARM_VQSHLsv8i8 = 3222, + ARM_VQSHLuiv16i8 = 3223, + ARM_VQSHLuiv1i64 = 3224, + ARM_VQSHLuiv2i32 = 3225, + ARM_VQSHLuiv2i64 = 3226, + ARM_VQSHLuiv4i16 = 3227, + ARM_VQSHLuiv4i32 = 3228, + ARM_VQSHLuiv8i16 = 3229, + ARM_VQSHLuiv8i8 = 3230, + ARM_VQSHLuv16i8 = 3231, + ARM_VQSHLuv1i64 = 3232, + ARM_VQSHLuv2i32 = 3233, + ARM_VQSHLuv2i64 = 3234, + ARM_VQSHLuv4i16 = 3235, + ARM_VQSHLuv4i32 = 3236, + ARM_VQSHLuv8i16 = 3237, + ARM_VQSHLuv8i8 = 3238, + ARM_VQSHRNsv2i32 = 3239, + ARM_VQSHRNsv4i16 = 3240, + ARM_VQSHRNsv8i8 = 3241, + ARM_VQSHRNuv2i32 = 3242, + ARM_VQSHRNuv4i16 = 3243, + ARM_VQSHRNuv8i8 = 3244, + ARM_VQSHRUNv2i32 = 3245, + ARM_VQSHRUNv4i16 = 3246, + ARM_VQSHRUNv8i8 = 3247, + ARM_VQSUBsv16i8 = 3248, + ARM_VQSUBsv1i64 = 3249, + ARM_VQSUBsv2i32 = 3250, + ARM_VQSUBsv2i64 = 3251, + ARM_VQSUBsv4i16 = 3252, + ARM_VQSUBsv4i32 = 3253, + ARM_VQSUBsv8i16 = 3254, + ARM_VQSUBsv8i8 = 3255, + ARM_VQSUBuv16i8 = 3256, + ARM_VQSUBuv1i64 = 3257, + ARM_VQSUBuv2i32 = 3258, + ARM_VQSUBuv2i64 = 3259, + ARM_VQSUBuv4i16 = 3260, + ARM_VQSUBuv4i32 = 3261, + ARM_VQSUBuv8i16 = 3262, + ARM_VQSUBuv8i8 = 3263, + ARM_VRADDHNv2i32 = 3264, + ARM_VRADDHNv4i16 = 3265, + ARM_VRADDHNv8i8 = 3266, + ARM_VRECPEd = 3267, + ARM_VRECPEfd = 3268, + ARM_VRECPEfq = 3269, + ARM_VRECPEhd = 3270, + ARM_VRECPEhq = 3271, + ARM_VRECPEq = 3272, + ARM_VRECPSfd = 3273, + ARM_VRECPSfq = 3274, + ARM_VRECPShd = 3275, + ARM_VRECPShq = 3276, + ARM_VREV16d8 = 3277, + ARM_VREV16q8 = 3278, + ARM_VREV32d16 = 3279, + ARM_VREV32d8 = 3280, + ARM_VREV32q16 = 3281, + ARM_VREV32q8 = 3282, + ARM_VREV64d16 = 3283, + ARM_VREV64d32 = 3284, + ARM_VREV64d8 = 3285, + ARM_VREV64q16 = 3286, + ARM_VREV64q32 = 3287, + ARM_VREV64q8 = 3288, + ARM_VRHADDsv16i8 = 3289, + ARM_VRHADDsv2i32 = 3290, + ARM_VRHADDsv4i16 = 3291, + ARM_VRHADDsv4i32 = 3292, + ARM_VRHADDsv8i16 = 3293, + ARM_VRHADDsv8i8 = 3294, + ARM_VRHADDuv16i8 = 3295, + ARM_VRHADDuv2i32 = 3296, + ARM_VRHADDuv4i16 = 3297, + ARM_VRHADDuv4i32 = 3298, + ARM_VRHADDuv8i16 = 3299, + ARM_VRHADDuv8i8 = 3300, + ARM_VRINTAD = 3301, + ARM_VRINTAH = 3302, + ARM_VRINTANDf = 3303, + ARM_VRINTANDh = 3304, + ARM_VRINTANQf = 3305, + ARM_VRINTANQh = 3306, + ARM_VRINTAS = 3307, + ARM_VRINTMD = 3308, + ARM_VRINTMH = 3309, + ARM_VRINTMNDf = 3310, + ARM_VRINTMNDh = 3311, + ARM_VRINTMNQf = 3312, + ARM_VRINTMNQh = 3313, + ARM_VRINTMS = 3314, + ARM_VRINTND = 3315, + ARM_VRINTNH = 3316, + ARM_VRINTNNDf = 3317, + ARM_VRINTNNDh = 3318, + ARM_VRINTNNQf = 3319, + ARM_VRINTNNQh = 3320, + ARM_VRINTNS = 3321, + ARM_VRINTPD = 3322, + ARM_VRINTPH = 3323, + ARM_VRINTPNDf = 3324, + ARM_VRINTPNDh = 3325, + ARM_VRINTPNQf = 3326, + ARM_VRINTPNQh = 3327, + ARM_VRINTPS = 3328, + ARM_VRINTRD = 3329, + ARM_VRINTRH = 3330, + ARM_VRINTRS = 3331, + ARM_VRINTXD = 3332, + ARM_VRINTXH = 3333, + ARM_VRINTXNDf = 3334, + ARM_VRINTXNDh = 3335, + ARM_VRINTXNQf = 3336, + ARM_VRINTXNQh = 3337, + ARM_VRINTXS = 3338, + ARM_VRINTZD = 3339, + ARM_VRINTZH = 3340, + ARM_VRINTZNDf = 3341, + ARM_VRINTZNDh = 3342, + ARM_VRINTZNQf = 3343, + ARM_VRINTZNQh = 3344, + ARM_VRINTZS = 3345, + ARM_VRSHLsv16i8 = 3346, + ARM_VRSHLsv1i64 = 3347, + ARM_VRSHLsv2i32 = 3348, + ARM_VRSHLsv2i64 = 3349, + ARM_VRSHLsv4i16 = 3350, + ARM_VRSHLsv4i32 = 3351, + ARM_VRSHLsv8i16 = 3352, + ARM_VRSHLsv8i8 = 3353, + ARM_VRSHLuv16i8 = 3354, + ARM_VRSHLuv1i64 = 3355, + ARM_VRSHLuv2i32 = 3356, + ARM_VRSHLuv2i64 = 3357, + ARM_VRSHLuv4i16 = 3358, + ARM_VRSHLuv4i32 = 3359, + ARM_VRSHLuv8i16 = 3360, + ARM_VRSHLuv8i8 = 3361, + ARM_VRSHRNv2i32 = 3362, + ARM_VRSHRNv4i16 = 3363, + ARM_VRSHRNv8i8 = 3364, + ARM_VRSHRsv16i8 = 3365, + ARM_VRSHRsv1i64 = 3366, + ARM_VRSHRsv2i32 = 3367, + ARM_VRSHRsv2i64 = 3368, + ARM_VRSHRsv4i16 = 3369, + ARM_VRSHRsv4i32 = 3370, + ARM_VRSHRsv8i16 = 3371, + ARM_VRSHRsv8i8 = 3372, + ARM_VRSHRuv16i8 = 3373, + ARM_VRSHRuv1i64 = 3374, + ARM_VRSHRuv2i32 = 3375, + ARM_VRSHRuv2i64 = 3376, + ARM_VRSHRuv4i16 = 3377, + ARM_VRSHRuv4i32 = 3378, + ARM_VRSHRuv8i16 = 3379, + ARM_VRSHRuv8i8 = 3380, + ARM_VRSQRTEd = 3381, + ARM_VRSQRTEfd = 3382, + ARM_VRSQRTEfq = 3383, + ARM_VRSQRTEhd = 3384, + ARM_VRSQRTEhq = 3385, + ARM_VRSQRTEq = 3386, + ARM_VRSQRTSfd = 3387, + ARM_VRSQRTSfq = 3388, + ARM_VRSQRTShd = 3389, + ARM_VRSQRTShq = 3390, + ARM_VRSRAsv16i8 = 3391, + ARM_VRSRAsv1i64 = 3392, + ARM_VRSRAsv2i32 = 3393, + ARM_VRSRAsv2i64 = 3394, + ARM_VRSRAsv4i16 = 3395, + ARM_VRSRAsv4i32 = 3396, + ARM_VRSRAsv8i16 = 3397, + ARM_VRSRAsv8i8 = 3398, + ARM_VRSRAuv16i8 = 3399, + ARM_VRSRAuv1i64 = 3400, + ARM_VRSRAuv2i32 = 3401, + ARM_VRSRAuv2i64 = 3402, + ARM_VRSRAuv4i16 = 3403, + ARM_VRSRAuv4i32 = 3404, + ARM_VRSRAuv8i16 = 3405, + ARM_VRSRAuv8i8 = 3406, + ARM_VRSUBHNv2i32 = 3407, + ARM_VRSUBHNv4i16 = 3408, + ARM_VRSUBHNv8i8 = 3409, + ARM_VSCCLRMD = 3410, + ARM_VSCCLRMS = 3411, + ARM_VSDOTD = 3412, + ARM_VSDOTDI = 3413, + ARM_VSDOTQ = 3414, + ARM_VSDOTQI = 3415, + ARM_VSELEQD = 3416, + ARM_VSELEQH = 3417, + ARM_VSELEQS = 3418, + ARM_VSELGED = 3419, + ARM_VSELGEH = 3420, + ARM_VSELGES = 3421, + ARM_VSELGTD = 3422, + ARM_VSELGTH = 3423, + ARM_VSELGTS = 3424, + ARM_VSELVSD = 3425, + ARM_VSELVSH = 3426, + ARM_VSELVSS = 3427, + ARM_VSETLNi16 = 3428, + ARM_VSETLNi32 = 3429, + ARM_VSETLNi8 = 3430, + ARM_VSHLLi16 = 3431, + ARM_VSHLLi32 = 3432, + ARM_VSHLLi8 = 3433, + ARM_VSHLLsv2i64 = 3434, + ARM_VSHLLsv4i32 = 3435, + ARM_VSHLLsv8i16 = 3436, + ARM_VSHLLuv2i64 = 3437, + ARM_VSHLLuv4i32 = 3438, + ARM_VSHLLuv8i16 = 3439, + ARM_VSHLiv16i8 = 3440, + ARM_VSHLiv1i64 = 3441, + ARM_VSHLiv2i32 = 3442, + ARM_VSHLiv2i64 = 3443, + ARM_VSHLiv4i16 = 3444, + ARM_VSHLiv4i32 = 3445, + ARM_VSHLiv8i16 = 3446, + ARM_VSHLiv8i8 = 3447, + ARM_VSHLsv16i8 = 3448, + ARM_VSHLsv1i64 = 3449, + ARM_VSHLsv2i32 = 3450, + ARM_VSHLsv2i64 = 3451, + ARM_VSHLsv4i16 = 3452, + ARM_VSHLsv4i32 = 3453, + ARM_VSHLsv8i16 = 3454, + ARM_VSHLsv8i8 = 3455, + ARM_VSHLuv16i8 = 3456, + ARM_VSHLuv1i64 = 3457, + ARM_VSHLuv2i32 = 3458, + ARM_VSHLuv2i64 = 3459, + ARM_VSHLuv4i16 = 3460, + ARM_VSHLuv4i32 = 3461, + ARM_VSHLuv8i16 = 3462, + ARM_VSHLuv8i8 = 3463, + ARM_VSHRNv2i32 = 3464, + ARM_VSHRNv4i16 = 3465, + ARM_VSHRNv8i8 = 3466, + ARM_VSHRsv16i8 = 3467, + ARM_VSHRsv1i64 = 3468, + ARM_VSHRsv2i32 = 3469, + ARM_VSHRsv2i64 = 3470, + ARM_VSHRsv4i16 = 3471, + ARM_VSHRsv4i32 = 3472, + ARM_VSHRsv8i16 = 3473, + ARM_VSHRsv8i8 = 3474, + ARM_VSHRuv16i8 = 3475, + ARM_VSHRuv1i64 = 3476, + ARM_VSHRuv2i32 = 3477, + ARM_VSHRuv2i64 = 3478, + ARM_VSHRuv4i16 = 3479, + ARM_VSHRuv4i32 = 3480, + ARM_VSHRuv8i16 = 3481, + ARM_VSHRuv8i8 = 3482, + ARM_VSHTOD = 3483, + ARM_VSHTOH = 3484, + ARM_VSHTOS = 3485, + ARM_VSITOD = 3486, + ARM_VSITOH = 3487, + ARM_VSITOS = 3488, + ARM_VSLIv16i8 = 3489, + ARM_VSLIv1i64 = 3490, + ARM_VSLIv2i32 = 3491, + ARM_VSLIv2i64 = 3492, + ARM_VSLIv4i16 = 3493, + ARM_VSLIv4i32 = 3494, + ARM_VSLIv8i16 = 3495, + ARM_VSLIv8i8 = 3496, + ARM_VSLTOD = 3497, + ARM_VSLTOH = 3498, + ARM_VSLTOS = 3499, + ARM_VSMMLA = 3500, + ARM_VSQRTD = 3501, + ARM_VSQRTH = 3502, + ARM_VSQRTS = 3503, + ARM_VSRAsv16i8 = 3504, + ARM_VSRAsv1i64 = 3505, + ARM_VSRAsv2i32 = 3506, + ARM_VSRAsv2i64 = 3507, + ARM_VSRAsv4i16 = 3508, + ARM_VSRAsv4i32 = 3509, + ARM_VSRAsv8i16 = 3510, + ARM_VSRAsv8i8 = 3511, + ARM_VSRAuv16i8 = 3512, + ARM_VSRAuv1i64 = 3513, + ARM_VSRAuv2i32 = 3514, + ARM_VSRAuv2i64 = 3515, + ARM_VSRAuv4i16 = 3516, + ARM_VSRAuv4i32 = 3517, + ARM_VSRAuv8i16 = 3518, + ARM_VSRAuv8i8 = 3519, + ARM_VSRIv16i8 = 3520, + ARM_VSRIv1i64 = 3521, + ARM_VSRIv2i32 = 3522, + ARM_VSRIv2i64 = 3523, + ARM_VSRIv4i16 = 3524, + ARM_VSRIv4i32 = 3525, + ARM_VSRIv8i16 = 3526, + ARM_VSRIv8i8 = 3527, + ARM_VST1LNd16 = 3528, + ARM_VST1LNd16_UPD = 3529, + ARM_VST1LNd32 = 3530, + ARM_VST1LNd32_UPD = 3531, + ARM_VST1LNd8 = 3532, + ARM_VST1LNd8_UPD = 3533, + ARM_VST1LNq16Pseudo = 3534, + ARM_VST1LNq16Pseudo_UPD = 3535, + ARM_VST1LNq32Pseudo = 3536, + ARM_VST1LNq32Pseudo_UPD = 3537, + ARM_VST1LNq8Pseudo = 3538, + ARM_VST1LNq8Pseudo_UPD = 3539, + ARM_VST1d16 = 3540, + ARM_VST1d16Q = 3541, + ARM_VST1d16QPseudo = 3542, + ARM_VST1d16QPseudoWB_fixed = 3543, + ARM_VST1d16QPseudoWB_register = 3544, + ARM_VST1d16Qwb_fixed = 3545, + ARM_VST1d16Qwb_register = 3546, + ARM_VST1d16T = 3547, + ARM_VST1d16TPseudo = 3548, + ARM_VST1d16TPseudoWB_fixed = 3549, + ARM_VST1d16TPseudoWB_register = 3550, + ARM_VST1d16Twb_fixed = 3551, + ARM_VST1d16Twb_register = 3552, + ARM_VST1d16wb_fixed = 3553, + ARM_VST1d16wb_register = 3554, + ARM_VST1d32 = 3555, + ARM_VST1d32Q = 3556, + ARM_VST1d32QPseudo = 3557, + ARM_VST1d32QPseudoWB_fixed = 3558, + ARM_VST1d32QPseudoWB_register = 3559, + ARM_VST1d32Qwb_fixed = 3560, + ARM_VST1d32Qwb_register = 3561, + ARM_VST1d32T = 3562, + ARM_VST1d32TPseudo = 3563, + ARM_VST1d32TPseudoWB_fixed = 3564, + ARM_VST1d32TPseudoWB_register = 3565, + ARM_VST1d32Twb_fixed = 3566, + ARM_VST1d32Twb_register = 3567, + ARM_VST1d32wb_fixed = 3568, + ARM_VST1d32wb_register = 3569, + ARM_VST1d64 = 3570, + ARM_VST1d64Q = 3571, + ARM_VST1d64QPseudo = 3572, + ARM_VST1d64QPseudoWB_fixed = 3573, + ARM_VST1d64QPseudoWB_register = 3574, + ARM_VST1d64Qwb_fixed = 3575, + ARM_VST1d64Qwb_register = 3576, + ARM_VST1d64T = 3577, + ARM_VST1d64TPseudo = 3578, + ARM_VST1d64TPseudoWB_fixed = 3579, + ARM_VST1d64TPseudoWB_register = 3580, + ARM_VST1d64Twb_fixed = 3581, + ARM_VST1d64Twb_register = 3582, + ARM_VST1d64wb_fixed = 3583, + ARM_VST1d64wb_register = 3584, + ARM_VST1d8 = 3585, + ARM_VST1d8Q = 3586, + ARM_VST1d8QPseudo = 3587, + ARM_VST1d8QPseudoWB_fixed = 3588, + ARM_VST1d8QPseudoWB_register = 3589, + ARM_VST1d8Qwb_fixed = 3590, + ARM_VST1d8Qwb_register = 3591, + ARM_VST1d8T = 3592, + ARM_VST1d8TPseudo = 3593, + ARM_VST1d8TPseudoWB_fixed = 3594, + ARM_VST1d8TPseudoWB_register = 3595, + ARM_VST1d8Twb_fixed = 3596, + ARM_VST1d8Twb_register = 3597, + ARM_VST1d8wb_fixed = 3598, + ARM_VST1d8wb_register = 3599, + ARM_VST1q16 = 3600, + ARM_VST1q16HighQPseudo = 3601, + ARM_VST1q16HighQPseudo_UPD = 3602, + ARM_VST1q16HighTPseudo = 3603, + ARM_VST1q16HighTPseudo_UPD = 3604, + ARM_VST1q16LowQPseudo_UPD = 3605, + ARM_VST1q16LowTPseudo_UPD = 3606, + ARM_VST1q16wb_fixed = 3607, + ARM_VST1q16wb_register = 3608, + ARM_VST1q32 = 3609, + ARM_VST1q32HighQPseudo = 3610, + ARM_VST1q32HighQPseudo_UPD = 3611, + ARM_VST1q32HighTPseudo = 3612, + ARM_VST1q32HighTPseudo_UPD = 3613, + ARM_VST1q32LowQPseudo_UPD = 3614, + ARM_VST1q32LowTPseudo_UPD = 3615, + ARM_VST1q32wb_fixed = 3616, + ARM_VST1q32wb_register = 3617, + ARM_VST1q64 = 3618, + ARM_VST1q64HighQPseudo = 3619, + ARM_VST1q64HighQPseudo_UPD = 3620, + ARM_VST1q64HighTPseudo = 3621, + ARM_VST1q64HighTPseudo_UPD = 3622, + ARM_VST1q64LowQPseudo_UPD = 3623, + ARM_VST1q64LowTPseudo_UPD = 3624, + ARM_VST1q64wb_fixed = 3625, + ARM_VST1q64wb_register = 3626, + ARM_VST1q8 = 3627, + ARM_VST1q8HighQPseudo = 3628, + ARM_VST1q8HighQPseudo_UPD = 3629, + ARM_VST1q8HighTPseudo = 3630, + ARM_VST1q8HighTPseudo_UPD = 3631, + ARM_VST1q8LowQPseudo_UPD = 3632, + ARM_VST1q8LowTPseudo_UPD = 3633, + ARM_VST1q8wb_fixed = 3634, + ARM_VST1q8wb_register = 3635, + ARM_VST2LNd16 = 3636, + ARM_VST2LNd16Pseudo = 3637, + ARM_VST2LNd16Pseudo_UPD = 3638, + ARM_VST2LNd16_UPD = 3639, + ARM_VST2LNd32 = 3640, + ARM_VST2LNd32Pseudo = 3641, + ARM_VST2LNd32Pseudo_UPD = 3642, + ARM_VST2LNd32_UPD = 3643, + ARM_VST2LNd8 = 3644, + ARM_VST2LNd8Pseudo = 3645, + ARM_VST2LNd8Pseudo_UPD = 3646, + ARM_VST2LNd8_UPD = 3647, + ARM_VST2LNq16 = 3648, + ARM_VST2LNq16Pseudo = 3649, + ARM_VST2LNq16Pseudo_UPD = 3650, + ARM_VST2LNq16_UPD = 3651, + ARM_VST2LNq32 = 3652, + ARM_VST2LNq32Pseudo = 3653, + ARM_VST2LNq32Pseudo_UPD = 3654, + ARM_VST2LNq32_UPD = 3655, + ARM_VST2b16 = 3656, + ARM_VST2b16wb_fixed = 3657, + ARM_VST2b16wb_register = 3658, + ARM_VST2b32 = 3659, + ARM_VST2b32wb_fixed = 3660, + ARM_VST2b32wb_register = 3661, + ARM_VST2b8 = 3662, + ARM_VST2b8wb_fixed = 3663, + ARM_VST2b8wb_register = 3664, + ARM_VST2d16 = 3665, + ARM_VST2d16wb_fixed = 3666, + ARM_VST2d16wb_register = 3667, + ARM_VST2d32 = 3668, + ARM_VST2d32wb_fixed = 3669, + ARM_VST2d32wb_register = 3670, + ARM_VST2d8 = 3671, + ARM_VST2d8wb_fixed = 3672, + ARM_VST2d8wb_register = 3673, + ARM_VST2q16 = 3674, + ARM_VST2q16Pseudo = 3675, + ARM_VST2q16PseudoWB_fixed = 3676, + ARM_VST2q16PseudoWB_register = 3677, + ARM_VST2q16wb_fixed = 3678, + ARM_VST2q16wb_register = 3679, + ARM_VST2q32 = 3680, + ARM_VST2q32Pseudo = 3681, + ARM_VST2q32PseudoWB_fixed = 3682, + ARM_VST2q32PseudoWB_register = 3683, + ARM_VST2q32wb_fixed = 3684, + ARM_VST2q32wb_register = 3685, + ARM_VST2q8 = 3686, + ARM_VST2q8Pseudo = 3687, + ARM_VST2q8PseudoWB_fixed = 3688, + ARM_VST2q8PseudoWB_register = 3689, + ARM_VST2q8wb_fixed = 3690, + ARM_VST2q8wb_register = 3691, + ARM_VST3LNd16 = 3692, + ARM_VST3LNd16Pseudo = 3693, + ARM_VST3LNd16Pseudo_UPD = 3694, + ARM_VST3LNd16_UPD = 3695, + ARM_VST3LNd32 = 3696, + ARM_VST3LNd32Pseudo = 3697, + ARM_VST3LNd32Pseudo_UPD = 3698, + ARM_VST3LNd32_UPD = 3699, + ARM_VST3LNd8 = 3700, + ARM_VST3LNd8Pseudo = 3701, + ARM_VST3LNd8Pseudo_UPD = 3702, + ARM_VST3LNd8_UPD = 3703, + ARM_VST3LNq16 = 3704, + ARM_VST3LNq16Pseudo = 3705, + ARM_VST3LNq16Pseudo_UPD = 3706, + ARM_VST3LNq16_UPD = 3707, + ARM_VST3LNq32 = 3708, + ARM_VST3LNq32Pseudo = 3709, + ARM_VST3LNq32Pseudo_UPD = 3710, + ARM_VST3LNq32_UPD = 3711, + ARM_VST3d16 = 3712, + ARM_VST3d16Pseudo = 3713, + ARM_VST3d16Pseudo_UPD = 3714, + ARM_VST3d16_UPD = 3715, + ARM_VST3d32 = 3716, + ARM_VST3d32Pseudo = 3717, + ARM_VST3d32Pseudo_UPD = 3718, + ARM_VST3d32_UPD = 3719, + ARM_VST3d8 = 3720, + ARM_VST3d8Pseudo = 3721, + ARM_VST3d8Pseudo_UPD = 3722, + ARM_VST3d8_UPD = 3723, + ARM_VST3q16 = 3724, + ARM_VST3q16Pseudo_UPD = 3725, + ARM_VST3q16_UPD = 3726, + ARM_VST3q16oddPseudo = 3727, + ARM_VST3q16oddPseudo_UPD = 3728, + ARM_VST3q32 = 3729, + ARM_VST3q32Pseudo_UPD = 3730, + ARM_VST3q32_UPD = 3731, + ARM_VST3q32oddPseudo = 3732, + ARM_VST3q32oddPseudo_UPD = 3733, + ARM_VST3q8 = 3734, + ARM_VST3q8Pseudo_UPD = 3735, + ARM_VST3q8_UPD = 3736, + ARM_VST3q8oddPseudo = 3737, + ARM_VST3q8oddPseudo_UPD = 3738, + ARM_VST4LNd16 = 3739, + ARM_VST4LNd16Pseudo = 3740, + ARM_VST4LNd16Pseudo_UPD = 3741, + ARM_VST4LNd16_UPD = 3742, + ARM_VST4LNd32 = 3743, + ARM_VST4LNd32Pseudo = 3744, + ARM_VST4LNd32Pseudo_UPD = 3745, + ARM_VST4LNd32_UPD = 3746, + ARM_VST4LNd8 = 3747, + ARM_VST4LNd8Pseudo = 3748, + ARM_VST4LNd8Pseudo_UPD = 3749, + ARM_VST4LNd8_UPD = 3750, + ARM_VST4LNq16 = 3751, + ARM_VST4LNq16Pseudo = 3752, + ARM_VST4LNq16Pseudo_UPD = 3753, + ARM_VST4LNq16_UPD = 3754, + ARM_VST4LNq32 = 3755, + ARM_VST4LNq32Pseudo = 3756, + ARM_VST4LNq32Pseudo_UPD = 3757, + ARM_VST4LNq32_UPD = 3758, + ARM_VST4d16 = 3759, + ARM_VST4d16Pseudo = 3760, + ARM_VST4d16Pseudo_UPD = 3761, + ARM_VST4d16_UPD = 3762, + ARM_VST4d32 = 3763, + ARM_VST4d32Pseudo = 3764, + ARM_VST4d32Pseudo_UPD = 3765, + ARM_VST4d32_UPD = 3766, + ARM_VST4d8 = 3767, + ARM_VST4d8Pseudo = 3768, + ARM_VST4d8Pseudo_UPD = 3769, + ARM_VST4d8_UPD = 3770, + ARM_VST4q16 = 3771, + ARM_VST4q16Pseudo_UPD = 3772, + ARM_VST4q16_UPD = 3773, + ARM_VST4q16oddPseudo = 3774, + ARM_VST4q16oddPseudo_UPD = 3775, + ARM_VST4q32 = 3776, + ARM_VST4q32Pseudo_UPD = 3777, + ARM_VST4q32_UPD = 3778, + ARM_VST4q32oddPseudo = 3779, + ARM_VST4q32oddPseudo_UPD = 3780, + ARM_VST4q8 = 3781, + ARM_VST4q8Pseudo_UPD = 3782, + ARM_VST4q8_UPD = 3783, + ARM_VST4q8oddPseudo = 3784, + ARM_VST4q8oddPseudo_UPD = 3785, + ARM_VSTMDDB_UPD = 3786, + ARM_VSTMDIA = 3787, + ARM_VSTMDIA_UPD = 3788, + ARM_VSTMQIA = 3789, + ARM_VSTMSDB_UPD = 3790, + ARM_VSTMSIA = 3791, + ARM_VSTMSIA_UPD = 3792, + ARM_VSTRD = 3793, + ARM_VSTRH = 3794, + ARM_VSTRS = 3795, + ARM_VSTR_FPCXTNS_off = 3796, + ARM_VSTR_FPCXTNS_post = 3797, + ARM_VSTR_FPCXTNS_pre = 3798, + ARM_VSTR_FPCXTS_off = 3799, + ARM_VSTR_FPCXTS_post = 3800, + ARM_VSTR_FPCXTS_pre = 3801, + ARM_VSTR_FPSCR_NZCVQC_off = 3802, + ARM_VSTR_FPSCR_NZCVQC_post = 3803, + ARM_VSTR_FPSCR_NZCVQC_pre = 3804, + ARM_VSTR_FPSCR_off = 3805, + ARM_VSTR_FPSCR_post = 3806, + ARM_VSTR_FPSCR_pre = 3807, + ARM_VSTR_P0_off = 3808, + ARM_VSTR_P0_post = 3809, + ARM_VSTR_P0_pre = 3810, + ARM_VSTR_VPR_off = 3811, + ARM_VSTR_VPR_post = 3812, + ARM_VSTR_VPR_pre = 3813, + ARM_VSUBD = 3814, + ARM_VSUBH = 3815, + ARM_VSUBHNv2i32 = 3816, + ARM_VSUBHNv4i16 = 3817, + ARM_VSUBHNv8i8 = 3818, + ARM_VSUBLsv2i64 = 3819, + ARM_VSUBLsv4i32 = 3820, + ARM_VSUBLsv8i16 = 3821, + ARM_VSUBLuv2i64 = 3822, + ARM_VSUBLuv4i32 = 3823, + ARM_VSUBLuv8i16 = 3824, + ARM_VSUBS = 3825, + ARM_VSUBWsv2i64 = 3826, + ARM_VSUBWsv4i32 = 3827, + ARM_VSUBWsv8i16 = 3828, + ARM_VSUBWuv2i64 = 3829, + ARM_VSUBWuv4i32 = 3830, + ARM_VSUBWuv8i16 = 3831, + ARM_VSUBfd = 3832, + ARM_VSUBfq = 3833, + ARM_VSUBhd = 3834, + ARM_VSUBhq = 3835, + ARM_VSUBv16i8 = 3836, + ARM_VSUBv1i64 = 3837, + ARM_VSUBv2i32 = 3838, + ARM_VSUBv2i64 = 3839, + ARM_VSUBv4i16 = 3840, + ARM_VSUBv4i32 = 3841, + ARM_VSUBv8i16 = 3842, + ARM_VSUBv8i8 = 3843, + ARM_VSUDOTDI = 3844, + ARM_VSUDOTQI = 3845, + ARM_VSWPd = 3846, + ARM_VSWPq = 3847, + ARM_VTBL1 = 3848, + ARM_VTBL2 = 3849, + ARM_VTBL3 = 3850, + ARM_VTBL3Pseudo = 3851, + ARM_VTBL4 = 3852, + ARM_VTBL4Pseudo = 3853, + ARM_VTBX1 = 3854, + ARM_VTBX2 = 3855, + ARM_VTBX3 = 3856, + ARM_VTBX3Pseudo = 3857, + ARM_VTBX4 = 3858, + ARM_VTBX4Pseudo = 3859, + ARM_VTOSHD = 3860, + ARM_VTOSHH = 3861, + ARM_VTOSHS = 3862, + ARM_VTOSIRD = 3863, + ARM_VTOSIRH = 3864, + ARM_VTOSIRS = 3865, + ARM_VTOSIZD = 3866, + ARM_VTOSIZH = 3867, + ARM_VTOSIZS = 3868, + ARM_VTOSLD = 3869, + ARM_VTOSLH = 3870, + ARM_VTOSLS = 3871, + ARM_VTOUHD = 3872, + ARM_VTOUHH = 3873, + ARM_VTOUHS = 3874, + ARM_VTOUIRD = 3875, + ARM_VTOUIRH = 3876, + ARM_VTOUIRS = 3877, + ARM_VTOUIZD = 3878, + ARM_VTOUIZH = 3879, + ARM_VTOUIZS = 3880, + ARM_VTOULD = 3881, + ARM_VTOULH = 3882, + ARM_VTOULS = 3883, + ARM_VTRNd16 = 3884, + ARM_VTRNd32 = 3885, + ARM_VTRNd8 = 3886, + ARM_VTRNq16 = 3887, + ARM_VTRNq32 = 3888, + ARM_VTRNq8 = 3889, + ARM_VTSTv16i8 = 3890, + ARM_VTSTv2i32 = 3891, + ARM_VTSTv4i16 = 3892, + ARM_VTSTv4i32 = 3893, + ARM_VTSTv8i16 = 3894, + ARM_VTSTv8i8 = 3895, + ARM_VUDOTD = 3896, + ARM_VUDOTDI = 3897, + ARM_VUDOTQ = 3898, + ARM_VUDOTQI = 3899, + ARM_VUHTOD = 3900, + ARM_VUHTOH = 3901, + ARM_VUHTOS = 3902, + ARM_VUITOD = 3903, + ARM_VUITOH = 3904, + ARM_VUITOS = 3905, + ARM_VULTOD = 3906, + ARM_VULTOH = 3907, + ARM_VULTOS = 3908, + ARM_VUMMLA = 3909, + ARM_VUSDOTD = 3910, + ARM_VUSDOTDI = 3911, + ARM_VUSDOTQ = 3912, + ARM_VUSDOTQI = 3913, + ARM_VUSMMLA = 3914, + ARM_VUZPd16 = 3915, + ARM_VUZPd8 = 3916, + ARM_VUZPq16 = 3917, + ARM_VUZPq32 = 3918, + ARM_VUZPq8 = 3919, + ARM_VZIPd16 = 3920, + ARM_VZIPd8 = 3921, + ARM_VZIPq16 = 3922, + ARM_VZIPq32 = 3923, + ARM_VZIPq8 = 3924, + ARM_sysLDMDA = 3925, + ARM_sysLDMDA_UPD = 3926, + ARM_sysLDMDB = 3927, + ARM_sysLDMDB_UPD = 3928, + ARM_sysLDMIA = 3929, + ARM_sysLDMIA_UPD = 3930, + ARM_sysLDMIB = 3931, + ARM_sysLDMIB_UPD = 3932, + ARM_sysSTMDA = 3933, + ARM_sysSTMDA_UPD = 3934, + ARM_sysSTMDB = 3935, + ARM_sysSTMDB_UPD = 3936, + ARM_sysSTMIA = 3937, + ARM_sysSTMIA_UPD = 3938, + ARM_sysSTMIB = 3939, + ARM_sysSTMIB_UPD = 3940, + ARM_t2ADCri = 3941, + ARM_t2ADCrr = 3942, + ARM_t2ADCrs = 3943, + ARM_t2ADDri = 3944, + ARM_t2ADDri12 = 3945, + ARM_t2ADDrr = 3946, + ARM_t2ADDrs = 3947, + ARM_t2ADDspImm = 3948, + ARM_t2ADDspImm12 = 3949, + ARM_t2ADR = 3950, + ARM_t2ANDri = 3951, + ARM_t2ANDrr = 3952, + ARM_t2ANDrs = 3953, + ARM_t2ASRri = 3954, + ARM_t2ASRrr = 3955, + ARM_t2AUT = 3956, + ARM_t2AUTG = 3957, + ARM_t2B = 3958, + ARM_t2BFC = 3959, + ARM_t2BFI = 3960, + ARM_t2BFLi = 3961, + ARM_t2BFLr = 3962, + ARM_t2BFi = 3963, + ARM_t2BFic = 3964, + ARM_t2BFr = 3965, + ARM_t2BICri = 3966, + ARM_t2BICrr = 3967, + ARM_t2BICrs = 3968, + ARM_t2BTI = 3969, + ARM_t2BXAUT = 3970, + ARM_t2BXJ = 3971, + ARM_t2Bcc = 3972, + ARM_t2CDP = 3973, + ARM_t2CDP2 = 3974, + ARM_t2CLREX = 3975, + ARM_t2CLRM = 3976, + ARM_t2CLZ = 3977, + ARM_t2CMNri = 3978, + ARM_t2CMNzrr = 3979, + ARM_t2CMNzrs = 3980, + ARM_t2CMPri = 3981, + ARM_t2CMPrr = 3982, + ARM_t2CMPrs = 3983, + ARM_t2CPS1p = 3984, + ARM_t2CPS2p = 3985, + ARM_t2CPS3p = 3986, + ARM_t2CRC32B = 3987, + ARM_t2CRC32CB = 3988, + ARM_t2CRC32CH = 3989, + ARM_t2CRC32CW = 3990, + ARM_t2CRC32H = 3991, + ARM_t2CRC32W = 3992, + ARM_t2CSEL = 3993, + ARM_t2CSINC = 3994, + ARM_t2CSINV = 3995, + ARM_t2CSNEG = 3996, + ARM_t2DBG = 3997, + ARM_t2DCPS1 = 3998, + ARM_t2DCPS2 = 3999, + ARM_t2DCPS3 = 4000, + ARM_t2DLS = 4001, + ARM_t2DMB = 4002, + ARM_t2DSB = 4003, + ARM_t2EORri = 4004, + ARM_t2EORrr = 4005, + ARM_t2EORrs = 4006, + ARM_t2HINT = 4007, + ARM_t2HVC = 4008, + ARM_t2ISB = 4009, + ARM_t2IT = 4010, + ARM_t2Int_eh_sjlj_setjmp = 4011, + ARM_t2Int_eh_sjlj_setjmp_nofp = 4012, + ARM_t2LDA = 4013, + ARM_t2LDAB = 4014, + ARM_t2LDAEX = 4015, + ARM_t2LDAEXB = 4016, + ARM_t2LDAEXD = 4017, + ARM_t2LDAEXH = 4018, + ARM_t2LDAH = 4019, + ARM_t2LDC2L_OFFSET = 4020, + ARM_t2LDC2L_OPTION = 4021, + ARM_t2LDC2L_POST = 4022, + ARM_t2LDC2L_PRE = 4023, + ARM_t2LDC2_OFFSET = 4024, + ARM_t2LDC2_OPTION = 4025, + ARM_t2LDC2_POST = 4026, + ARM_t2LDC2_PRE = 4027, + ARM_t2LDCL_OFFSET = 4028, + ARM_t2LDCL_OPTION = 4029, + ARM_t2LDCL_POST = 4030, + ARM_t2LDCL_PRE = 4031, + ARM_t2LDC_OFFSET = 4032, + ARM_t2LDC_OPTION = 4033, + ARM_t2LDC_POST = 4034, + ARM_t2LDC_PRE = 4035, + ARM_t2LDMDB = 4036, + ARM_t2LDMDB_UPD = 4037, + ARM_t2LDMIA = 4038, + ARM_t2LDMIA_UPD = 4039, + ARM_t2LDRBT = 4040, + ARM_t2LDRB_POST = 4041, + ARM_t2LDRB_PRE = 4042, + ARM_t2LDRBi12 = 4043, + ARM_t2LDRBi8 = 4044, + ARM_t2LDRBpci = 4045, + ARM_t2LDRBs = 4046, + ARM_t2LDRD_POST = 4047, + ARM_t2LDRD_PRE = 4048, + ARM_t2LDRDi8 = 4049, + ARM_t2LDREX = 4050, + ARM_t2LDREXB = 4051, + ARM_t2LDREXD = 4052, + ARM_t2LDREXH = 4053, + ARM_t2LDRHT = 4054, + ARM_t2LDRH_POST = 4055, + ARM_t2LDRH_PRE = 4056, + ARM_t2LDRHi12 = 4057, + ARM_t2LDRHi8 = 4058, + ARM_t2LDRHpci = 4059, + ARM_t2LDRHs = 4060, + ARM_t2LDRSBT = 4061, + ARM_t2LDRSB_POST = 4062, + ARM_t2LDRSB_PRE = 4063, + ARM_t2LDRSBi12 = 4064, + ARM_t2LDRSBi8 = 4065, + ARM_t2LDRSBpci = 4066, + ARM_t2LDRSBs = 4067, + ARM_t2LDRSHT = 4068, + ARM_t2LDRSH_POST = 4069, + ARM_t2LDRSH_PRE = 4070, + ARM_t2LDRSHi12 = 4071, + ARM_t2LDRSHi8 = 4072, + ARM_t2LDRSHpci = 4073, + ARM_t2LDRSHs = 4074, + ARM_t2LDRT = 4075, + ARM_t2LDR_POST = 4076, + ARM_t2LDR_PRE = 4077, + ARM_t2LDRi12 = 4078, + ARM_t2LDRi8 = 4079, + ARM_t2LDRpci = 4080, + ARM_t2LDRs = 4081, + ARM_t2LE = 4082, + ARM_t2LEUpdate = 4083, + ARM_t2LSLri = 4084, + ARM_t2LSLrr = 4085, + ARM_t2LSRri = 4086, + ARM_t2LSRrr = 4087, + ARM_t2MCR = 4088, + ARM_t2MCR2 = 4089, + ARM_t2MCRR = 4090, + ARM_t2MCRR2 = 4091, + ARM_t2MLA = 4092, + ARM_t2MLS = 4093, + ARM_t2MOVTi16 = 4094, + ARM_t2MOVi = 4095, + ARM_t2MOVi16 = 4096, + ARM_t2MOVr = 4097, + ARM_t2MOVsra_flag = 4098, + ARM_t2MOVsrl_flag = 4099, + ARM_t2MRC = 4100, + ARM_t2MRC2 = 4101, + ARM_t2MRRC = 4102, + ARM_t2MRRC2 = 4103, + ARM_t2MRS_AR = 4104, + ARM_t2MRS_M = 4105, + ARM_t2MRSbanked = 4106, + ARM_t2MRSsys_AR = 4107, + ARM_t2MSR_AR = 4108, + ARM_t2MSR_M = 4109, + ARM_t2MSRbanked = 4110, + ARM_t2MUL = 4111, + ARM_t2MVNi = 4112, + ARM_t2MVNr = 4113, + ARM_t2MVNs = 4114, + ARM_t2ORNri = 4115, + ARM_t2ORNrr = 4116, + ARM_t2ORNrs = 4117, + ARM_t2ORRri = 4118, + ARM_t2ORRrr = 4119, + ARM_t2ORRrs = 4120, + ARM_t2PAC = 4121, + ARM_t2PACBTI = 4122, + ARM_t2PACG = 4123, + ARM_t2PKHBT = 4124, + ARM_t2PKHTB = 4125, + ARM_t2PLDWi12 = 4126, + ARM_t2PLDWi8 = 4127, + ARM_t2PLDWs = 4128, + ARM_t2PLDi12 = 4129, + ARM_t2PLDi8 = 4130, + ARM_t2PLDpci = 4131, + ARM_t2PLDs = 4132, + ARM_t2PLIi12 = 4133, + ARM_t2PLIi8 = 4134, + ARM_t2PLIpci = 4135, + ARM_t2PLIs = 4136, + ARM_t2QADD = 4137, + ARM_t2QADD16 = 4138, + ARM_t2QADD8 = 4139, + ARM_t2QASX = 4140, + ARM_t2QDADD = 4141, + ARM_t2QDSUB = 4142, + ARM_t2QSAX = 4143, + ARM_t2QSUB = 4144, + ARM_t2QSUB16 = 4145, + ARM_t2QSUB8 = 4146, + ARM_t2RBIT = 4147, + ARM_t2REV = 4148, + ARM_t2REV16 = 4149, + ARM_t2REVSH = 4150, + ARM_t2RFEDB = 4151, + ARM_t2RFEDBW = 4152, + ARM_t2RFEIA = 4153, + ARM_t2RFEIAW = 4154, + ARM_t2RORri = 4155, + ARM_t2RORrr = 4156, + ARM_t2RRX = 4157, + ARM_t2RSBri = 4158, + ARM_t2RSBrr = 4159, + ARM_t2RSBrs = 4160, + ARM_t2SADD16 = 4161, + ARM_t2SADD8 = 4162, + ARM_t2SASX = 4163, + ARM_t2SB = 4164, + ARM_t2SBCri = 4165, + ARM_t2SBCrr = 4166, + ARM_t2SBCrs = 4167, + ARM_t2SBFX = 4168, + ARM_t2SDIV = 4169, + ARM_t2SEL = 4170, + ARM_t2SETPAN = 4171, + ARM_t2SG = 4172, + ARM_t2SHADD16 = 4173, + ARM_t2SHADD8 = 4174, + ARM_t2SHASX = 4175, + ARM_t2SHSAX = 4176, + ARM_t2SHSUB16 = 4177, + ARM_t2SHSUB8 = 4178, + ARM_t2SMC = 4179, + ARM_t2SMLABB = 4180, + ARM_t2SMLABT = 4181, + ARM_t2SMLAD = 4182, + ARM_t2SMLADX = 4183, + ARM_t2SMLAL = 4184, + ARM_t2SMLALBB = 4185, + ARM_t2SMLALBT = 4186, + ARM_t2SMLALD = 4187, + ARM_t2SMLALDX = 4188, + ARM_t2SMLALTB = 4189, + ARM_t2SMLALTT = 4190, + ARM_t2SMLATB = 4191, + ARM_t2SMLATT = 4192, + ARM_t2SMLAWB = 4193, + ARM_t2SMLAWT = 4194, + ARM_t2SMLSD = 4195, + ARM_t2SMLSDX = 4196, + ARM_t2SMLSLD = 4197, + ARM_t2SMLSLDX = 4198, + ARM_t2SMMLA = 4199, + ARM_t2SMMLAR = 4200, + ARM_t2SMMLS = 4201, + ARM_t2SMMLSR = 4202, + ARM_t2SMMUL = 4203, + ARM_t2SMMULR = 4204, + ARM_t2SMUAD = 4205, + ARM_t2SMUADX = 4206, + ARM_t2SMULBB = 4207, + ARM_t2SMULBT = 4208, + ARM_t2SMULL = 4209, + ARM_t2SMULTB = 4210, + ARM_t2SMULTT = 4211, + ARM_t2SMULWB = 4212, + ARM_t2SMULWT = 4213, + ARM_t2SMUSD = 4214, + ARM_t2SMUSDX = 4215, + ARM_t2SRSDB = 4216, + ARM_t2SRSDB_UPD = 4217, + ARM_t2SRSIA = 4218, + ARM_t2SRSIA_UPD = 4219, + ARM_t2SSAT = 4220, + ARM_t2SSAT16 = 4221, + ARM_t2SSAX = 4222, + ARM_t2SSUB16 = 4223, + ARM_t2SSUB8 = 4224, + ARM_t2STC2L_OFFSET = 4225, + ARM_t2STC2L_OPTION = 4226, + ARM_t2STC2L_POST = 4227, + ARM_t2STC2L_PRE = 4228, + ARM_t2STC2_OFFSET = 4229, + ARM_t2STC2_OPTION = 4230, + ARM_t2STC2_POST = 4231, + ARM_t2STC2_PRE = 4232, + ARM_t2STCL_OFFSET = 4233, + ARM_t2STCL_OPTION = 4234, + ARM_t2STCL_POST = 4235, + ARM_t2STCL_PRE = 4236, + ARM_t2STC_OFFSET = 4237, + ARM_t2STC_OPTION = 4238, + ARM_t2STC_POST = 4239, + ARM_t2STC_PRE = 4240, + ARM_t2STL = 4241, + ARM_t2STLB = 4242, + ARM_t2STLEX = 4243, + ARM_t2STLEXB = 4244, + ARM_t2STLEXD = 4245, + ARM_t2STLEXH = 4246, + ARM_t2STLH = 4247, + ARM_t2STMDB = 4248, + ARM_t2STMDB_UPD = 4249, + ARM_t2STMIA = 4250, + ARM_t2STMIA_UPD = 4251, + ARM_t2STRBT = 4252, + ARM_t2STRB_POST = 4253, + ARM_t2STRB_PRE = 4254, + ARM_t2STRBi12 = 4255, + ARM_t2STRBi8 = 4256, + ARM_t2STRBs = 4257, + ARM_t2STRD_POST = 4258, + ARM_t2STRD_PRE = 4259, + ARM_t2STRDi8 = 4260, + ARM_t2STREX = 4261, + ARM_t2STREXB = 4262, + ARM_t2STREXD = 4263, + ARM_t2STREXH = 4264, + ARM_t2STRHT = 4265, + ARM_t2STRH_POST = 4266, + ARM_t2STRH_PRE = 4267, + ARM_t2STRHi12 = 4268, + ARM_t2STRHi8 = 4269, + ARM_t2STRHs = 4270, + ARM_t2STRT = 4271, + ARM_t2STR_POST = 4272, + ARM_t2STR_PRE = 4273, + ARM_t2STRi12 = 4274, + ARM_t2STRi8 = 4275, + ARM_t2STRs = 4276, + ARM_t2SUBS_PC_LR = 4277, + ARM_t2SUBri = 4278, + ARM_t2SUBri12 = 4279, + ARM_t2SUBrr = 4280, + ARM_t2SUBrs = 4281, + ARM_t2SUBspImm = 4282, + ARM_t2SUBspImm12 = 4283, + ARM_t2SXTAB = 4284, + ARM_t2SXTAB16 = 4285, + ARM_t2SXTAH = 4286, + ARM_t2SXTB = 4287, + ARM_t2SXTB16 = 4288, + ARM_t2SXTH = 4289, + ARM_t2TBB = 4290, + ARM_t2TBH = 4291, + ARM_t2TEQri = 4292, + ARM_t2TEQrr = 4293, + ARM_t2TEQrs = 4294, + ARM_t2TSB = 4295, + ARM_t2TSTri = 4296, + ARM_t2TSTrr = 4297, + ARM_t2TSTrs = 4298, + ARM_t2TT = 4299, + ARM_t2TTA = 4300, + ARM_t2TTAT = 4301, + ARM_t2TTT = 4302, + ARM_t2UADD16 = 4303, + ARM_t2UADD8 = 4304, + ARM_t2UASX = 4305, + ARM_t2UBFX = 4306, + ARM_t2UDF = 4307, + ARM_t2UDIV = 4308, + ARM_t2UHADD16 = 4309, + ARM_t2UHADD8 = 4310, + ARM_t2UHASX = 4311, + ARM_t2UHSAX = 4312, + ARM_t2UHSUB16 = 4313, + ARM_t2UHSUB8 = 4314, + ARM_t2UMAAL = 4315, + ARM_t2UMLAL = 4316, + ARM_t2UMULL = 4317, + ARM_t2UQADD16 = 4318, + ARM_t2UQADD8 = 4319, + ARM_t2UQASX = 4320, + ARM_t2UQSAX = 4321, + ARM_t2UQSUB16 = 4322, + ARM_t2UQSUB8 = 4323, + ARM_t2USAD8 = 4324, + ARM_t2USADA8 = 4325, + ARM_t2USAT = 4326, + ARM_t2USAT16 = 4327, + ARM_t2USAX = 4328, + ARM_t2USUB16 = 4329, + ARM_t2USUB8 = 4330, + ARM_t2UXTAB = 4331, + ARM_t2UXTAB16 = 4332, + ARM_t2UXTAH = 4333, + ARM_t2UXTB = 4334, + ARM_t2UXTB16 = 4335, + ARM_t2UXTH = 4336, + ARM_t2WLS = 4337, + ARM_tADC = 4338, + ARM_tADDhirr = 4339, + ARM_tADDi3 = 4340, + ARM_tADDi8 = 4341, + ARM_tADDrSP = 4342, + ARM_tADDrSPi = 4343, + ARM_tADDrr = 4344, + ARM_tADDspi = 4345, + ARM_tADDspr = 4346, + ARM_tADR = 4347, + ARM_tAND = 4348, + ARM_tASRri = 4349, + ARM_tASRrr = 4350, + ARM_tB = 4351, + ARM_tBIC = 4352, + ARM_tBKPT = 4353, + ARM_tBL = 4354, + ARM_tBLXNSr = 4355, + ARM_tBLXi = 4356, + ARM_tBLXr = 4357, + ARM_tBX = 4358, + ARM_tBXNS = 4359, + ARM_tBcc = 4360, + ARM_tCBNZ = 4361, + ARM_tCBZ = 4362, + ARM_tCMNz = 4363, + ARM_tCMPhir = 4364, + ARM_tCMPi8 = 4365, + ARM_tCMPr = 4366, + ARM_tCPS = 4367, + ARM_tEOR = 4368, + ARM_tHINT = 4369, + ARM_tHLT = 4370, + ARM_tInt_WIN_eh_sjlj_longjmp = 4371, + ARM_tInt_eh_sjlj_longjmp = 4372, + ARM_tInt_eh_sjlj_setjmp = 4373, + ARM_tLDMIA = 4374, + ARM_tLDRBi = 4375, + ARM_tLDRBr = 4376, + ARM_tLDRHi = 4377, + ARM_tLDRHr = 4378, + ARM_tLDRSB = 4379, + ARM_tLDRSH = 4380, + ARM_tLDRi = 4381, + ARM_tLDRpci = 4382, + ARM_tLDRr = 4383, + ARM_tLDRspi = 4384, + ARM_tLSLri = 4385, + ARM_tLSLrr = 4386, + ARM_tLSRri = 4387, + ARM_tLSRrr = 4388, + ARM_tMOVSr = 4389, + ARM_tMOVi8 = 4390, + ARM_tMOVr = 4391, + ARM_tMUL = 4392, + ARM_tMVN = 4393, + ARM_tORR = 4394, + ARM_tPICADD = 4395, + ARM_tPOP = 4396, + ARM_tPUSH = 4397, + ARM_tREV = 4398, + ARM_tREV16 = 4399, + ARM_tREVSH = 4400, + ARM_tROR = 4401, + ARM_tRSB = 4402, + ARM_tSBC = 4403, + ARM_tSETEND = 4404, + ARM_tSTMIA_UPD = 4405, + ARM_tSTRBi = 4406, + ARM_tSTRBr = 4407, + ARM_tSTRHi = 4408, + ARM_tSTRHr = 4409, + ARM_tSTRi = 4410, + ARM_tSTRr = 4411, + ARM_tSTRspi = 4412, + ARM_tSUBi3 = 4413, + ARM_tSUBi8 = 4414, + ARM_tSUBrr = 4415, + ARM_tSUBspi = 4416, + ARM_tSVC = 4417, + ARM_tSXTB = 4418, + ARM_tSXTH = 4419, + ARM_tTRAP = 4420, + ARM_tTST = 4421, + ARM_tUDF = 4422, + ARM_tUXTB = 4423, + ARM_tUXTH = 4424, + ARM_t__brkdiv0 = 4425, + INSTRUCTION_LIST_END = 4426 +}; + +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const MCOperandInfo OperandInfo2[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo3[] = { + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo4[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo5[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo6[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo7[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo8[] = { + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo9[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo10[] = { + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo11[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo12[] = { + { 0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo13[] = { + { 0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo14[] = { + { 0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo15[] = { + { 0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo16[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { 0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo17[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, +}; +static const MCOperandInfo OperandInfo18[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, +}; +static const MCOperandInfo OperandInfo19[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, +}; +static const MCOperandInfo OperandInfo20[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, +}; +static const MCOperandInfo OperandInfo21[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo22[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, +}; +static const MCOperandInfo OperandInfo23[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, +}; +static const MCOperandInfo OperandInfo24[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, +}; +static const MCOperandInfo OperandInfo25[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, +}; +static const MCOperandInfo OperandInfo26[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo27[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo28[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo29[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, +}; +static const MCOperandInfo OperandInfo30[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, +}; +static const MCOperandInfo OperandInfo31[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, +}; +static const MCOperandInfo OperandInfo32[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo33[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, +}; +static const MCOperandInfo OperandInfo34[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, +}; +static const MCOperandInfo OperandInfo35[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, +}; +static const MCOperandInfo OperandInfo36[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, +}; +static const MCOperandInfo OperandInfo37[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, +}; +static const MCOperandInfo OperandInfo38[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, +}; +static const MCOperandInfo OperandInfo39[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, +}; +static const MCOperandInfo OperandInfo40[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, +}; +static const MCOperandInfo OperandInfo41[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo42[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, +}; +static const MCOperandInfo OperandInfo43[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, +}; +static const MCOperandInfo OperandInfo44[] = { + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, + { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, +}; +static const MCOperandInfo OperandInfo45[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo46[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo47[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo48[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo49[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo50[] = { + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo51[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo52[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo53[] = { + { -1, 0, MCOI_OPERAND_PCREL, 0 }, +}; +static const MCOperandInfo OperandInfo54[] = { + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, +}; +static const MCOperandInfo OperandInfo55[] = { + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, +}; +static const MCOperandInfo OperandInfo56[] = { + { ARM_GPRnoipRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo57[] = { + { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, +}; +static const MCOperandInfo OperandInfo58[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo59[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo60[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo61[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo62[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo63[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo64[] = { + { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo65[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo66[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo67[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo68[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo69[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo70[] = { + { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, +}; +static const MCOperandInfo OperandInfo71[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo72[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo73[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo74[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo75[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo76[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo77[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo78[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo79[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo80[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo81[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo82[] = { + { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo83[] = { + { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo84[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo85[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo86[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo87[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo88[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo89[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo90[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo91[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo92[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo93[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo94[] = { + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo95[] = { + { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo96[] = { + { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo97[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo98[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo99[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo100[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo101[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo102[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo103[] = { + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo104[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo105[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo106[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo107[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo108[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo109[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo110[] = { + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, +}; +static const MCOperandInfo OperandInfo111[] = { + { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo112[] = { + { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo113[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo114[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo115[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo116[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo117[] = { + { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo118[] = { + { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, +}; +static const MCOperandInfo OperandInfo119[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo120[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo121[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo122[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo123[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo124[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo125[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo126[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo127[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo128[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo129[] = { + { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, +}; +static const MCOperandInfo OperandInfo130[] = { + { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, +}; +static const MCOperandInfo OperandInfo131[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo132[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo133[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo134[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo135[] = { + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnoipRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo136[] = { + { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, +}; +static const MCOperandInfo OperandInfo137[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo138[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo139[] = { + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo140[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo141[] = { + { -1, 0, MCOI_OPERAND_PCREL, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo142[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo143[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo144[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo145[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo146[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo147[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo148[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo149[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo150[] = { + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo151[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo152[] = { + { ARM_tGPRwithpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, +}; +static const MCOperandInfo OperandInfo153[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo154[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo155[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo156[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo157[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo158[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo159[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo160[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo161[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo162[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo163[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo164[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo165[] = { + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo166[] = { + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo167[] = { + { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo168[] = { + { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo169[] = { + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo170[] = { + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo171[] = { + { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo172[] = { + { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo173[] = { + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo174[] = { + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo175[] = { + { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo176[] = { + { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo177[] = { + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo178[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo179[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo180[] = { + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo181[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo182[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo183[] = { + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo184[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo185[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo186[] = { + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo187[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo188[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo189[] = { + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo190[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo191[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo192[] = { + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo193[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo194[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo195[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo196[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo197[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo198[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo199[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo200[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo201[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo202[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo203[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo204[] = { + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo205[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo206[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo207[] = { + { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo208[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, +}; +static const MCOperandInfo OperandInfo209[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo210[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, +}; +static const MCOperandInfo OperandInfo211[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo212[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo213[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo214[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo215[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo216[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo217[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo218[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo219[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(2) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo220[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo221[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo222[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo223[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo224[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo225[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo226[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo227[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo228[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo229[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo230[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo231[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo232[] = { + { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo233[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo234[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo235[] = { + { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo236[] = { + { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo237[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo238[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo239[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo240[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo241[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo242[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo243[] = { + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo244[] = { + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo245[] = { + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo246[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo247[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo248[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo249[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo250[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo251[] = { + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo252[] = { + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo253[] = { + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo254[] = { + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo255[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo256[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo257[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo258[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo259[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo260[] = { + { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo261[] = { + { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRwithZRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo262[] = { + { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo263[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo264[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo265[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo266[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo267[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo268[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo269[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo270[] = { + { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, +}; +static const MCOperandInfo OperandInfo271[] = { + { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, +}; +static const MCOperandInfo OperandInfo272[] = { + { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, +}; +static const MCOperandInfo OperandInfo273[] = { + { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, +}; +static const MCOperandInfo OperandInfo274[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo275[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo276[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo277[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo278[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo279[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo280[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo281[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo282[] = { + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo283[] = { + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo284[] = { + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo285[] = { + { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo286[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo287[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo288[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo289[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo290[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo291[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo292[] = { + { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo293[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo294[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo295[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRwithZRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo296[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo297[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo298[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo299[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo300[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, ARM_OP_VPRED_R, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, + { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo301[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo302[] = { + { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, +}; +static const MCOperandInfo OperandInfo303[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo304[] = { + { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, +}; +static const MCOperandInfo OperandInfo305[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo306[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo307[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo308[] = { + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, ARM_OP_VPRED_N, 0 }, + { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, + { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, +}; +static const MCOperandInfo OperandInfo309[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo310[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo311[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo312[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo313[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, +}; +static const MCOperandInfo OperandInfo314[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, +}; +static const MCOperandInfo OperandInfo315[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo316[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, +}; +static const MCOperandInfo OperandInfo317[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo318[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo319[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo320[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo321[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo322[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo323[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo324[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo325[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo326[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo327[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo328[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo329[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo330[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo331[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo332[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo333[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo334[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo335[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo336[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo337[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo338[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo339[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo340[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo341[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo342[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo343[] = { + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo344[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo345[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo346[] = { + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo347[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo348[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo349[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo350[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo351[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo352[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo353[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo354[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo355[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo356[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo357[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo358[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo359[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo360[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo361[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo362[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo363[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo364[] = { + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo365[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo366[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo367[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo368[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo369[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo370[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo371[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo372[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo373[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo374[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo375[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo376[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo377[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo378[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo379[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo380[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo381[] = { + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo382[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo383[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo384[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo385[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo386[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo387[] = { + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo388[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo389[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo390[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo391[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo392[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo393[] = { + { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo394[] = { + { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo395[] = { + { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo396[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo397[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo398[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo399[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo400[] = { + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo401[] = { + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo402[] = { + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo403[] = { + { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo404[] = { + { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo405[] = { + { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo406[] = { + { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo407[] = { + { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo408[] = { + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo409[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo410[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(2) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo411[] = { + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo412[] = { + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo413[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo414[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(3) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo415[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(2) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo416[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(3) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(2) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo417[] = { + { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo418[] = { + { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo419[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo420[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(4) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo421[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(2) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(3) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo422[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(4) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(2) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(3) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo423[] = { + { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo424[] = { + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo425[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo426[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo427[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo428[] = { + { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo429[] = { + { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo430[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo431[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo432[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo433[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo434[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo435[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo436[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo437[] = { + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo438[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo439[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo440[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo441[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo442[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo443[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo444[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo445[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo446[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo447[] = { + { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo448[] = { + { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo449[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo450[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo451[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo452[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo453[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo454[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo455[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo456[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo457[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo458[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo459[] = { + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo460[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo461[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo462[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo463[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo464[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo465[] = { + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo466[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo467[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo468[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo469[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo470[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo471[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo472[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo473[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo474[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo475[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo476[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo477[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo478[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo479[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo480[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo481[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo482[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo483[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo484[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo485[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo486[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo487[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo488[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo489[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo490[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo491[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo492[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo493[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo494[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo495[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo496[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo497[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo498[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo499[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo500[] = { + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo501[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo502[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo503[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo504[] = { + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo505[] = { + { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo506[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo507[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo508[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo509[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo510[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo511[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo512[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo513[] = { + { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo514[] = { + { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo515[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo516[] = { + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo517[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo518[] = { + { -1, 0, MCOI_OPERAND_PCREL, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo519[] = { + { -1, 0, MCOI_OPERAND_PCREL, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo520[] = { + { -1, 0, MCOI_OPERAND_PCREL, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo521[] = { + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo522[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo523[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo524[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo525[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRwithZRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRwithZRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo526[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo527[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo528[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo529[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo530[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo531[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(2) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo532[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo533[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo534[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo535[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo536[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo537[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo538[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo539[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo540[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo541[] = { + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo542[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo543[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo544[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, +}; +static const MCOperandInfo OperandInfo545[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo546[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo547[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo548[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo549[] = { + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo550[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo551[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(1) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo552[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo553[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo554[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo555[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo556[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo557[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo558[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo559[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo560[] = { + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_EARLY_CLOBBER }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo561[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo562[] = { + { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo563[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo564[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo565[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo566[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo567[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo568[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo569[] = { + { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo570[] = { + { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo571[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo572[] = { + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo573[] = { + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, +}; +static const MCOperandInfo OperandInfo574[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_PCREL, 0 }, +}; +static const MCOperandInfo OperandInfo575[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo576[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo577[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo578[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo579[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo580[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo581[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo582[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo583[] = { + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, + 0 }, + { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, + { -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, +}; +static const MCOperandInfo OperandInfo584[] = { + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, + CONSTRAINT_MCOI_TIED_TO(0) }, + { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, +}; + +static const MCInstrDesc ARMInsts[] = { + { 1, OperandInfo2 }, // Inst #0 = PHI + { 0, 0 }, // Inst #1 = INLINEASM + { 0, 0 }, // Inst #2 = INLINEASM_BR + { 1, OperandInfo3 }, // Inst #3 = CFI_INSTRUCTION + { 1, OperandInfo3 }, // Inst #4 = EH_LABEL + { 1, OperandInfo3 }, // Inst #5 = GC_LABEL + { 1, OperandInfo3 }, // Inst #6 = ANNOTATION_LABEL + { 0, 0 }, // Inst #7 = KILL + { 3, OperandInfo4 }, // Inst #8 = EXTRACT_SUBREG + { 4, OperandInfo5 }, // Inst #9 = INSERT_SUBREG + { 1, OperandInfo2 }, // Inst #10 = IMPLICIT_DEF + { 4, OperandInfo6 }, // Inst #11 = SUBREG_TO_REG + { 3, OperandInfo4 }, // Inst #12 = COPY_TO_REGCLASS + { 0, 0 }, // Inst #13 = DBG_VALUE + { 0, 0 }, // Inst #14 = DBG_VALUE_LIST + { 0, 0 }, // Inst #15 = DBG_INSTR_REF + { 0, 0 }, // Inst #16 = DBG_PHI + { 1, OperandInfo2 }, // Inst #17 = DBG_LABEL + { 2, OperandInfo7 }, // Inst #18 = REG_SEQUENCE + { 2, OperandInfo7 }, // Inst #19 = COPY + { 0, 0 }, // Inst #20 = BUNDLE + { 1, OperandInfo3 }, // Inst #21 = LIFETIME_START + { 1, OperandInfo3 }, // Inst #22 = LIFETIME_END + { 4, OperandInfo8 }, // Inst #23 = PSEUDO_PROBE + { 2, OperandInfo9 }, // Inst #24 = ARITH_FENCE + { 2, OperandInfo10 }, // Inst #25 = STACKMAP + { 0, 0 }, // Inst #26 = FENTRY_CALL + { 6, OperandInfo11 }, // Inst #27 = PATCHPOINT + { 1, OperandInfo12 }, // Inst #28 = LOAD_STACK_GUARD + { 1, OperandInfo3 }, // Inst #29 = PREALLOCATED_SETUP + { 3, OperandInfo13 }, // Inst #30 = PREALLOCATED_ARG + { 0, 0 }, // Inst #31 = STATEPOINT + { 2, OperandInfo14 }, // Inst #32 = LOCAL_ESCAPE + { 1, OperandInfo2 }, // Inst #33 = FAULTING_OP + { 0, 0 }, // Inst #34 = PATCHABLE_OP + { 0, 0 }, // Inst #35 = PATCHABLE_FUNCTION_ENTER + { 0, 0 }, // Inst #36 = PATCHABLE_RET + { 0, 0 }, // Inst #37 = PATCHABLE_FUNCTION_EXIT + { 0, 0 }, // Inst #38 = PATCHABLE_TAIL_CALL + { 2, OperandInfo15 }, // Inst #39 = PATCHABLE_EVENT_CALL + { 3, OperandInfo16 }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL + { 0, 0 }, // Inst #41 = ICALL_BRANCH_FUNNEL + { 0, 0 }, // Inst #42 = MEMBARRIER + { 3, OperandInfo17 }, // Inst #43 = G_ASSERT_SEXT + { 3, OperandInfo17 }, // Inst #44 = G_ASSERT_ZEXT + { 3, OperandInfo17 }, // Inst #45 = G_ASSERT_ALIGN + { 3, OperandInfo18 }, // Inst #46 = G_ADD + { 3, OperandInfo18 }, // Inst #47 = G_SUB + { 3, OperandInfo18 }, // Inst #48 = G_MUL + { 3, OperandInfo18 }, // Inst #49 = G_SDIV + { 3, OperandInfo18 }, // Inst #50 = G_UDIV + { 3, OperandInfo18 }, // Inst #51 = G_SREM + { 3, OperandInfo18 }, // Inst #52 = G_UREM + { 4, OperandInfo19 }, // Inst #53 = G_SDIVREM + { 4, OperandInfo19 }, // Inst #54 = G_UDIVREM + { 3, OperandInfo18 }, // Inst #55 = G_AND + { 3, OperandInfo18 }, // Inst #56 = G_OR + { 3, OperandInfo18 }, // Inst #57 = G_XOR + { 1, OperandInfo20 }, // Inst #58 = G_IMPLICIT_DEF + { 1, OperandInfo20 }, // Inst #59 = G_PHI + { 2, OperandInfo21 }, // Inst #60 = G_FRAME_INDEX + { 2, OperandInfo21 }, // Inst #61 = G_GLOBAL_VALUE + { 3, OperandInfo22 }, // Inst #62 = G_EXTRACT + { 2, OperandInfo23 }, // Inst #63 = G_UNMERGE_VALUES + { 4, OperandInfo24 }, // Inst #64 = G_INSERT + { 2, OperandInfo23 }, // Inst #65 = G_MERGE_VALUES + { 2, OperandInfo23 }, // Inst #66 = G_BUILD_VECTOR + { 2, OperandInfo23 }, // Inst #67 = G_BUILD_VECTOR_TRUNC + { 2, OperandInfo23 }, // Inst #68 = G_CONCAT_VECTORS + { 2, OperandInfo23 }, // Inst #69 = G_PTRTOINT + { 2, OperandInfo23 }, // Inst #70 = G_INTTOPTR + { 2, OperandInfo23 }, // Inst #71 = G_BITCAST + { 2, OperandInfo25 }, // Inst #72 = G_FREEZE + { 3, OperandInfo26 }, // Inst #73 = G_INTRINSIC_FPTRUNC_ROUND + { 2, OperandInfo25 }, // Inst #74 = G_INTRINSIC_TRUNC + { 2, OperandInfo25 }, // Inst #75 = G_INTRINSIC_ROUND + { 2, OperandInfo23 }, // Inst #76 = G_INTRINSIC_LRINT + { 2, OperandInfo25 }, // Inst #77 = G_INTRINSIC_ROUNDEVEN + { 1, OperandInfo20 }, // Inst #78 = G_READCYCLECOUNTER + { 2, OperandInfo23 }, // Inst #79 = G_LOAD + { 2, OperandInfo23 }, // Inst #80 = G_SEXTLOAD + { 2, OperandInfo23 }, // Inst #81 = G_ZEXTLOAD + { 5, OperandInfo27 }, // Inst #82 = G_INDEXED_LOAD + { 5, OperandInfo27 }, // Inst #83 = G_INDEXED_SEXTLOAD + { 5, OperandInfo27 }, // Inst #84 = G_INDEXED_ZEXTLOAD + { 2, OperandInfo23 }, // Inst #85 = G_STORE + { 5, OperandInfo28 }, // Inst #86 = G_INDEXED_STORE + { 5, OperandInfo29 }, // Inst #87 = G_ATOMIC_CMPXCHG_WITH_SUCCESS + { 4, OperandInfo30 }, // Inst #88 = G_ATOMIC_CMPXCHG + { 3, OperandInfo31 }, // Inst #89 = G_ATOMICRMW_XCHG + { 3, OperandInfo31 }, // Inst #90 = G_ATOMICRMW_ADD + { 3, OperandInfo31 }, // Inst #91 = G_ATOMICRMW_SUB + { 3, OperandInfo31 }, // Inst #92 = G_ATOMICRMW_AND + { 3, OperandInfo31 }, // Inst #93 = G_ATOMICRMW_NAND + { 3, OperandInfo31 }, // Inst #94 = G_ATOMICRMW_OR + { 3, OperandInfo31 }, // Inst #95 = G_ATOMICRMW_XOR + { 3, OperandInfo31 }, // Inst #96 = G_ATOMICRMW_MAX + { 3, OperandInfo31 }, // Inst #97 = G_ATOMICRMW_MIN + { 3, OperandInfo31 }, // Inst #98 = G_ATOMICRMW_UMAX + { 3, OperandInfo31 }, // Inst #99 = G_ATOMICRMW_UMIN + { 3, OperandInfo31 }, // Inst #100 = G_ATOMICRMW_FADD + { 3, OperandInfo31 }, // Inst #101 = G_ATOMICRMW_FSUB + { 3, OperandInfo31 }, // Inst #102 = G_ATOMICRMW_FMAX + { 3, OperandInfo31 }, // Inst #103 = G_ATOMICRMW_FMIN + { 3, OperandInfo31 }, // Inst #104 = G_ATOMICRMW_UINC_WRAP + { 3, OperandInfo31 }, // Inst #105 = G_ATOMICRMW_UDEC_WRAP + { 2, OperandInfo10 }, // Inst #106 = G_FENCE + { 2, OperandInfo21 }, // Inst #107 = G_BRCOND + { 1, OperandInfo20 }, // Inst #108 = G_BRINDIRECT + { 0, 0 }, // Inst #109 = G_INVOKE_REGION_START + { 1, OperandInfo2 }, // Inst #110 = G_INTRINSIC + { 1, OperandInfo2 }, // Inst #111 = G_INTRINSIC_W_SIDE_EFFECTS + { 2, OperandInfo23 }, // Inst #112 = G_ANYEXT + { 2, OperandInfo23 }, // Inst #113 = G_TRUNC + { 2, OperandInfo21 }, // Inst #114 = G_CONSTANT + { 2, OperandInfo21 }, // Inst #115 = G_FCONSTANT + { 1, OperandInfo20 }, // Inst #116 = G_VASTART + { 3, OperandInfo32 }, // Inst #117 = G_VAARG + { 2, OperandInfo23 }, // Inst #118 = G_SEXT + { 3, OperandInfo17 }, // Inst #119 = G_SEXT_INREG + { 2, OperandInfo23 }, // Inst #120 = G_ZEXT + { 3, OperandInfo33 }, // Inst #121 = G_SHL + { 3, OperandInfo33 }, // Inst #122 = G_LSHR + { 3, OperandInfo33 }, // Inst #123 = G_ASHR + { 4, OperandInfo34 }, // Inst #124 = G_FSHL + { 4, OperandInfo34 }, // Inst #125 = G_FSHR + { 3, OperandInfo33 }, // Inst #126 = G_ROTR + { 3, OperandInfo33 }, // Inst #127 = G_ROTL + { 4, OperandInfo35 }, // Inst #128 = G_ICMP + { 4, OperandInfo35 }, // Inst #129 = G_FCMP + { 4, OperandInfo30 }, // Inst #130 = G_SELECT + { 4, OperandInfo30 }, // Inst #131 = G_UADDO + { 5, OperandInfo36 }, // Inst #132 = G_UADDE + { 4, OperandInfo30 }, // Inst #133 = G_USUBO + { 5, OperandInfo36 }, // Inst #134 = G_USUBE + { 4, OperandInfo30 }, // Inst #135 = G_SADDO + { 5, OperandInfo36 }, // Inst #136 = G_SADDE + { 4, OperandInfo30 }, // Inst #137 = G_SSUBO + { 5, OperandInfo36 }, // Inst #138 = G_SSUBE + { 4, OperandInfo30 }, // Inst #139 = G_UMULO + { 4, OperandInfo30 }, // Inst #140 = G_SMULO + { 3, OperandInfo18 }, // Inst #141 = G_UMULH + { 3, OperandInfo18 }, // Inst #142 = G_SMULH + { 3, OperandInfo18 }, // Inst #143 = G_UADDSAT + { 3, OperandInfo18 }, // Inst #144 = G_SADDSAT + { 3, OperandInfo18 }, // Inst #145 = G_USUBSAT + { 3, OperandInfo18 }, // Inst #146 = G_SSUBSAT + { 3, OperandInfo33 }, // Inst #147 = G_USHLSAT + { 3, OperandInfo33 }, // Inst #148 = G_SSHLSAT + { 4, OperandInfo37 }, // Inst #149 = G_SMULFIX + { 4, OperandInfo37 }, // Inst #150 = G_UMULFIX + { 4, OperandInfo37 }, // Inst #151 = G_SMULFIXSAT + { 4, OperandInfo37 }, // Inst #152 = G_UMULFIXSAT + { 4, OperandInfo37 }, // Inst #153 = G_SDIVFIX + { 4, OperandInfo37 }, // Inst #154 = G_UDIVFIX + { 4, OperandInfo37 }, // Inst #155 = G_SDIVFIXSAT + { 4, OperandInfo37 }, // Inst #156 = G_UDIVFIXSAT + { 3, OperandInfo18 }, // Inst #157 = G_FADD + { 3, OperandInfo18 }, // Inst #158 = G_FSUB + { 3, OperandInfo18 }, // Inst #159 = G_FMUL + { 4, OperandInfo19 }, // Inst #160 = G_FMA + { 4, OperandInfo19 }, // Inst #161 = G_FMAD + { 3, OperandInfo18 }, // Inst #162 = G_FDIV + { 3, OperandInfo18 }, // Inst #163 = G_FREM + { 3, OperandInfo18 }, // Inst #164 = G_FPOW + { 3, OperandInfo33 }, // Inst #165 = G_FPOWI + { 2, OperandInfo25 }, // Inst #166 = G_FEXP + { 2, OperandInfo25 }, // Inst #167 = G_FEXP2 + { 2, OperandInfo25 }, // Inst #168 = G_FLOG + { 2, OperandInfo25 }, // Inst #169 = G_FLOG2 + { 2, OperandInfo25 }, // Inst #170 = G_FLOG10 + { 2, OperandInfo25 }, // Inst #171 = G_FNEG + { 2, OperandInfo23 }, // Inst #172 = G_FPEXT + { 2, OperandInfo23 }, // Inst #173 = G_FPTRUNC + { 2, OperandInfo23 }, // Inst #174 = G_FPTOSI + { 2, OperandInfo23 }, // Inst #175 = G_FPTOUI + { 2, OperandInfo23 }, // Inst #176 = G_SITOFP + { 2, OperandInfo23 }, // Inst #177 = G_UITOFP + { 2, OperandInfo25 }, // Inst #178 = G_FABS + { 3, OperandInfo33 }, // Inst #179 = G_FCOPYSIGN + { 3, OperandInfo32 }, // Inst #180 = G_IS_FPCLASS + { 2, OperandInfo25 }, // Inst #181 = G_FCANONICALIZE + { 3, OperandInfo18 }, // Inst #182 = G_FMINNUM + { 3, OperandInfo18 }, // Inst #183 = G_FMAXNUM + { 3, OperandInfo18 }, // Inst #184 = G_FMINNUM_IEEE + { 3, OperandInfo18 }, // Inst #185 = G_FMAXNUM_IEEE + { 3, OperandInfo18 }, // Inst #186 = G_FMINIMUM + { 3, OperandInfo18 }, // Inst #187 = G_FMAXIMUM + { 3, OperandInfo33 }, // Inst #188 = G_PTR_ADD + { 3, OperandInfo33 }, // Inst #189 = G_PTRMASK + { 3, OperandInfo18 }, // Inst #190 = G_SMIN + { 3, OperandInfo18 }, // Inst #191 = G_SMAX + { 3, OperandInfo18 }, // Inst #192 = G_UMIN + { 3, OperandInfo18 }, // Inst #193 = G_UMAX + { 2, OperandInfo25 }, // Inst #194 = G_ABS + { 2, OperandInfo23 }, // Inst #195 = G_LROUND + { 2, OperandInfo23 }, // Inst #196 = G_LLROUND + { 1, OperandInfo2 }, // Inst #197 = G_BR + { 3, OperandInfo38 }, // Inst #198 = G_BRJT + { 4, OperandInfo39 }, // Inst #199 = G_INSERT_VECTOR_ELT + { 3, OperandInfo40 }, // Inst #200 = G_EXTRACT_VECTOR_ELT + { 4, OperandInfo41 }, // Inst #201 = G_SHUFFLE_VECTOR + { 2, OperandInfo23 }, // Inst #202 = G_CTTZ + { 2, OperandInfo23 }, // Inst #203 = G_CTTZ_ZERO_UNDEF + { 2, OperandInfo23 }, // Inst #204 = G_CTLZ + { 2, OperandInfo23 }, // Inst #205 = G_CTLZ_ZERO_UNDEF + { 2, OperandInfo23 }, // Inst #206 = G_CTPOP + { 2, OperandInfo25 }, // Inst #207 = G_BSWAP + { 2, OperandInfo25 }, // Inst #208 = G_BITREVERSE + { 2, OperandInfo25 }, // Inst #209 = G_FCEIL + { 2, OperandInfo25 }, // Inst #210 = G_FCOS + { 2, OperandInfo25 }, // Inst #211 = G_FSIN + { 2, OperandInfo25 }, // Inst #212 = G_FSQRT + { 2, OperandInfo25 }, // Inst #213 = G_FFLOOR + { 2, OperandInfo25 }, // Inst #214 = G_FRINT + { 2, OperandInfo25 }, // Inst #215 = G_FNEARBYINT + { 2, OperandInfo23 }, // Inst #216 = G_ADDRSPACE_CAST + { 2, OperandInfo21 }, // Inst #217 = G_BLOCK_ADDR + { 2, OperandInfo21 }, // Inst #218 = G_JUMP_TABLE + { 3, OperandInfo26 }, // Inst #219 = G_DYN_STACKALLOC + { 3, OperandInfo18 }, // Inst #220 = G_STRICT_FADD + { 3, OperandInfo18 }, // Inst #221 = G_STRICT_FSUB + { 3, OperandInfo18 }, // Inst #222 = G_STRICT_FMUL + { 3, OperandInfo18 }, // Inst #223 = G_STRICT_FDIV + { 3, OperandInfo18 }, // Inst #224 = G_STRICT_FREM + { 4, OperandInfo19 }, // Inst #225 = G_STRICT_FMA + { 2, OperandInfo25 }, // Inst #226 = G_STRICT_FSQRT + { 2, OperandInfo21 }, // Inst #227 = G_READ_REGISTER + { 2, OperandInfo42 }, // Inst #228 = G_WRITE_REGISTER + { 4, OperandInfo43 }, // Inst #229 = G_MEMCPY + { 3, OperandInfo40 }, // Inst #230 = G_MEMCPY_INLINE + { 4, OperandInfo43 }, // Inst #231 = G_MEMMOVE + { 4, OperandInfo43 }, // Inst #232 = G_MEMSET + { 3, OperandInfo22 }, // Inst #233 = G_BZERO + { 3, OperandInfo40 }, // Inst #234 = G_VECREDUCE_SEQ_FADD + { 3, OperandInfo40 }, // Inst #235 = G_VECREDUCE_SEQ_FMUL + { 2, OperandInfo23 }, // Inst #236 = G_VECREDUCE_FADD + { 2, OperandInfo23 }, // Inst #237 = G_VECREDUCE_FMUL + { 2, OperandInfo23 }, // Inst #238 = G_VECREDUCE_FMAX + { 2, OperandInfo23 }, // Inst #239 = G_VECREDUCE_FMIN + { 2, OperandInfo23 }, // Inst #240 = G_VECREDUCE_ADD + { 2, OperandInfo23 }, // Inst #241 = G_VECREDUCE_MUL + { 2, OperandInfo23 }, // Inst #242 = G_VECREDUCE_AND + { 2, OperandInfo23 }, // Inst #243 = G_VECREDUCE_OR + { 2, OperandInfo23 }, // Inst #244 = G_VECREDUCE_XOR + { 2, OperandInfo23 }, // Inst #245 = G_VECREDUCE_SMAX + { 2, OperandInfo23 }, // Inst #246 = G_VECREDUCE_SMIN + { 2, OperandInfo23 }, // Inst #247 = G_VECREDUCE_UMAX + { 2, OperandInfo23 }, // Inst #248 = G_VECREDUCE_UMIN + { 4, OperandInfo44 }, // Inst #249 = G_SBFX + { 4, OperandInfo44 }, // Inst #250 = G_UBFX + { 2, OperandInfo45 }, // Inst #251 = ABS + { 5, OperandInfo46 }, // Inst #252 = ADDSri + { 5, OperandInfo47 }, // Inst #253 = ADDSrr + { 6, OperandInfo48 }, // Inst #254 = ADDSrsi + { 7, OperandInfo49 }, // Inst #255 = ADDSrsr + { 4, OperandInfo50 }, // Inst #256 = ADJCALLSTACKDOWN + { 4, OperandInfo50 }, // Inst #257 = ADJCALLSTACKUP + { 6, OperandInfo51 }, // Inst #258 = ASRi + { 6, OperandInfo52 }, // Inst #259 = ASRr + { 1, OperandInfo53 }, // Inst #260 = B + { 4, OperandInfo54 }, // Inst #261 = BCCZi64 + { 6, OperandInfo55 }, // Inst #262 = BCCi64 + { 1, OperandInfo56 }, // Inst #263 = BLX_noip + { 1, OperandInfo56 }, // Inst #264 = BLX_pred_noip + { 2, OperandInfo57 }, // Inst #265 = BL_PUSHLR + { 1, OperandInfo53 }, // Inst #266 = BMOVPCB_CALL + { 1, OperandInfo58 }, // Inst #267 = BMOVPCRX_CALL + { 3, OperandInfo59 }, // Inst #268 = BR_JTadd + { 3, OperandInfo60 }, // Inst #269 = BR_JTm_i12 + { 4, OperandInfo61 }, // Inst #270 = BR_JTm_rs + { 2, OperandInfo62 }, // Inst #271 = BR_JTr + { 1, OperandInfo58 }, // Inst #272 = BX_CALL + { 5, OperandInfo63 }, // Inst #273 = CMP_SWAP_16 + { 5, OperandInfo63 }, // Inst #274 = CMP_SWAP_32 + { 5, OperandInfo64 }, // Inst #275 = CMP_SWAP_64 + { 5, OperandInfo63 }, // Inst #276 = CMP_SWAP_8 + { 3, OperandInfo4 }, // Inst #277 = CONSTPOOL_ENTRY + { 4, OperandInfo65 }, // Inst #278 = COPY_STRUCT_BYVAL_I32 + { 2, OperandInfo7 }, // Inst #279 = ITasm + { 0, 0 }, // Inst #280 = Int_eh_sjlj_dispatchsetup + { 2, OperandInfo45 }, // Inst #281 = Int_eh_sjlj_longjmp + { 2, OperandInfo45 }, // Inst #282 = Int_eh_sjlj_setjmp + { 2, OperandInfo45 }, // Inst #283 = Int_eh_sjlj_setjmp_nofp + { 0, 0 }, // Inst #284 = Int_eh_sjlj_setup_dispatch + { 3, OperandInfo4 }, // Inst #285 = JUMPTABLE_ADDRS + { 3, OperandInfo4 }, // Inst #286 = JUMPTABLE_INSTS + { 3, OperandInfo4 }, // Inst #287 = JUMPTABLE_TBB + { 3, OperandInfo4 }, // Inst #288 = JUMPTABLE_TBH + { 5, OperandInfo66 }, // Inst #289 = LDMIA_RET + { 4, OperandInfo67 }, // Inst #290 = LDRBT_POST + { 4, OperandInfo68 }, // Inst #291 = LDRConstPool + { 4, OperandInfo67 }, // Inst #292 = LDRHTii + { 2, OperandInfo62 }, // Inst #293 = LDRLIT_ga_abs + { 2, OperandInfo62 }, // Inst #294 = LDRLIT_ga_pcrel + { 2, OperandInfo62 }, // Inst #295 = LDRLIT_ga_pcrel_ldr + { 4, OperandInfo67 }, // Inst #296 = LDRSBTii + { 4, OperandInfo67 }, // Inst #297 = LDRSHTii + { 4, OperandInfo67 }, // Inst #298 = LDRT_POST + { 4, OperandInfo69 }, // Inst #299 = LEApcrel + { 4, OperandInfo69 }, // Inst #300 = LEApcrelJT + { 4, OperandInfo70 }, // Inst #301 = LOADDUAL + { 6, OperandInfo51 }, // Inst #302 = LSLi + { 6, OperandInfo52 }, // Inst #303 = LSLr + { 6, OperandInfo51 }, // Inst #304 = LSRi + { 6, OperandInfo52 }, // Inst #305 = LSRr + { 5, OperandInfo71 }, // Inst #306 = MEMCPY + { 7, OperandInfo72 }, // Inst #307 = MLAv5 + { 5, OperandInfo73 }, // Inst #308 = MOVCCi + { 5, OperandInfo73 }, // Inst #309 = MOVCCi16 + { 5, OperandInfo74 }, // Inst #310 = MOVCCi32imm + { 5, OperandInfo75 }, // Inst #311 = MOVCCr + { 6, OperandInfo76 }, // Inst #312 = MOVCCsi + { 7, OperandInfo77 }, // Inst #313 = MOVCCsr + { 1, OperandInfo78 }, // Inst #314 = MOVPCRX + { 4, OperandInfo79 }, // Inst #315 = MOVTi16_ga_pcrel + { 2, OperandInfo62 }, // Inst #316 = MOV_ga_pcrel + { 2, OperandInfo62 }, // Inst #317 = MOV_ga_pcrel_ldr + { 3, OperandInfo80 }, // Inst #318 = MOVi16_ga_pcrel + { 2, OperandInfo62 }, // Inst #319 = MOVi32imm + { 2, OperandInfo45 }, // Inst #320 = MOVsra_flag + { 2, OperandInfo45 }, // Inst #321 = MOVsrl_flag + { 2, OperandInfo81 }, // Inst #322 = MQPRCopy + { 2, OperandInfo82 }, // Inst #323 = MQQPRLoad + { 2, OperandInfo82 }, // Inst #324 = MQQPRStore + { 2, OperandInfo83 }, // Inst #325 = MQQQQPRLoad + { 2, OperandInfo83 }, // Inst #326 = MQQQQPRStore + { 6, OperandInfo84 }, // Inst #327 = MULv5 + { 3, OperandInfo85 }, // Inst #328 = MVE_MEMCPYLOOPINST + { 3, OperandInfo86 }, // Inst #329 = MVE_MEMSETLOOPINST + { 5, OperandInfo73 }, // Inst #330 = MVNCCi + { 5, OperandInfo46 }, // Inst #331 = PICADD + { 5, OperandInfo87 }, // Inst #332 = PICLDR + { 5, OperandInfo87 }, // Inst #333 = PICLDRB + { 5, OperandInfo87 }, // Inst #334 = PICLDRH + { 5, OperandInfo87 }, // Inst #335 = PICLDRSB + { 5, OperandInfo87 }, // Inst #336 = PICLDRSH + { 5, OperandInfo87 }, // Inst #337 = PICSTR + { 5, OperandInfo87 }, // Inst #338 = PICSTRB + { 5, OperandInfo87 }, // Inst #339 = PICSTRH + { 6, OperandInfo51 }, // Inst #340 = RORi + { 6, OperandInfo52 }, // Inst #341 = RORr + { 2, OperandInfo45 }, // Inst #342 = RRX + { 5, OperandInfo88 }, // Inst #343 = RRXi + { 5, OperandInfo46 }, // Inst #344 = RSBSri + { 6, OperandInfo48 }, // Inst #345 = RSBSrsi + { 7, OperandInfo49 }, // Inst #346 = RSBSrsr + { 0, 0 }, // Inst #347 = SEH_EpilogEnd + { 0, 0 }, // Inst #348 = SEH_EpilogStart + { 1, OperandInfo3 }, // Inst #349 = SEH_Nop + { 1, OperandInfo3 }, // Inst #350 = SEH_Nop_Ret + { 0, 0 }, // Inst #351 = SEH_PrologEnd + { 2, OperandInfo10 }, // Inst #352 = SEH_SaveFRegs + { 1, OperandInfo3 }, // Inst #353 = SEH_SaveLR + { 2, OperandInfo10 }, // Inst #354 = SEH_SaveRegs + { 2, OperandInfo10 }, // Inst #355 = SEH_SaveRegs_Ret + { 1, OperandInfo3 }, // Inst #356 = SEH_SaveSP + { 2, OperandInfo10 }, // Inst #357 = SEH_StackAlloc + { 9, OperandInfo89 }, // Inst #358 = SMLALv5 + { 7, OperandInfo90 }, // Inst #359 = SMULLv5 + { 3, OperandInfo91 }, // Inst #360 = SPACE + { 4, OperandInfo70 }, // Inst #361 = STOREDUAL + { 4, OperandInfo67 }, // Inst #362 = STRBT_POST + { 7, OperandInfo92 }, // Inst #363 = STRBi_preidx + { 7, OperandInfo92 }, // Inst #364 = STRBr_preidx + { 7, OperandInfo93 }, // Inst #365 = STRH_preidx + { 4, OperandInfo67 }, // Inst #366 = STRT_POST + { 7, OperandInfo92 }, // Inst #367 = STRi_preidx + { 7, OperandInfo92 }, // Inst #368 = STRr_preidx + { 3, OperandInfo94 }, // Inst #369 = SUBS_PC_LR + { 5, OperandInfo46 }, // Inst #370 = SUBSri + { 5, OperandInfo47 }, // Inst #371 = SUBSrr + { 6, OperandInfo48 }, // Inst #372 = SUBSrsi + { 7, OperandInfo49 }, // Inst #373 = SUBSrsr + { 0, 0 }, // Inst #374 = SpeculationBarrierISBDSBEndBB + { 0, 0 }, // Inst #375 = SpeculationBarrierSBEndBB + { 1, OperandInfo53 }, // Inst #376 = TAILJMPd + { 1, OperandInfo95 }, // Inst #377 = TAILJMPr + { 1, OperandInfo78 }, // Inst #378 = TAILJMPr4 + { 2, OperandInfo10 }, // Inst #379 = TCRETURNdi + { 2, OperandInfo96 }, // Inst #380 = TCRETURNri + { 0, 0 }, // Inst #381 = TPsoft + { 9, OperandInfo89 }, // Inst #382 = UMLALv5 + { 7, OperandInfo90 }, // Inst #383 = UMULLv5 + { 6, OperandInfo97 }, // Inst #384 = VLD1LNdAsm_16 + { 6, OperandInfo97 }, // Inst #385 = VLD1LNdAsm_32 + { 6, OperandInfo97 }, // Inst #386 = VLD1LNdAsm_8 + { 6, OperandInfo97 }, // Inst #387 = VLD1LNdWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #388 = VLD1LNdWB_fixed_Asm_32 + { 6, OperandInfo97 }, // Inst #389 = VLD1LNdWB_fixed_Asm_8 + { 7, OperandInfo98 }, // Inst #390 = VLD1LNdWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #391 = VLD1LNdWB_register_Asm_32 + { 7, OperandInfo98 }, // Inst #392 = VLD1LNdWB_register_Asm_8 + { 6, OperandInfo97 }, // Inst #393 = VLD2LNdAsm_16 + { 6, OperandInfo97 }, // Inst #394 = VLD2LNdAsm_32 + { 6, OperandInfo97 }, // Inst #395 = VLD2LNdAsm_8 + { 6, OperandInfo97 }, // Inst #396 = VLD2LNdWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #397 = VLD2LNdWB_fixed_Asm_32 + { 6, OperandInfo97 }, // Inst #398 = VLD2LNdWB_fixed_Asm_8 + { 7, OperandInfo98 }, // Inst #399 = VLD2LNdWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #400 = VLD2LNdWB_register_Asm_32 + { 7, OperandInfo98 }, // Inst #401 = VLD2LNdWB_register_Asm_8 + { 6, OperandInfo97 }, // Inst #402 = VLD2LNqAsm_16 + { 6, OperandInfo97 }, // Inst #403 = VLD2LNqAsm_32 + { 6, OperandInfo97 }, // Inst #404 = VLD2LNqWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #405 = VLD2LNqWB_fixed_Asm_32 + { 7, OperandInfo98 }, // Inst #406 = VLD2LNqWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #407 = VLD2LNqWB_register_Asm_32 + { 5, OperandInfo99 }, // Inst #408 = VLD3DUPdAsm_16 + { 5, OperandInfo99 }, // Inst #409 = VLD3DUPdAsm_32 + { 5, OperandInfo99 }, // Inst #410 = VLD3DUPdAsm_8 + { 5, OperandInfo99 }, // Inst #411 = VLD3DUPdWB_fixed_Asm_16 + { 5, OperandInfo99 }, // Inst #412 = VLD3DUPdWB_fixed_Asm_32 + { 5, OperandInfo99 }, // Inst #413 = VLD3DUPdWB_fixed_Asm_8 + { 6, OperandInfo100 }, // Inst #414 = VLD3DUPdWB_register_Asm_16 + { 6, OperandInfo100 }, // Inst #415 = VLD3DUPdWB_register_Asm_32 + { 6, OperandInfo100 }, // Inst #416 = VLD3DUPdWB_register_Asm_8 + { 5, OperandInfo99 }, // Inst #417 = VLD3DUPqAsm_16 + { 5, OperandInfo99 }, // Inst #418 = VLD3DUPqAsm_32 + { 5, OperandInfo99 }, // Inst #419 = VLD3DUPqAsm_8 + { 5, OperandInfo99 }, // Inst #420 = VLD3DUPqWB_fixed_Asm_16 + { 5, OperandInfo99 }, // Inst #421 = VLD3DUPqWB_fixed_Asm_32 + { 5, OperandInfo99 }, // Inst #422 = VLD3DUPqWB_fixed_Asm_8 + { 6, OperandInfo100 }, // Inst #423 = VLD3DUPqWB_register_Asm_16 + { 6, OperandInfo100 }, // Inst #424 = VLD3DUPqWB_register_Asm_32 + { 6, OperandInfo100 }, // Inst #425 = VLD3DUPqWB_register_Asm_8 + { 6, OperandInfo97 }, // Inst #426 = VLD3LNdAsm_16 + { 6, OperandInfo97 }, // Inst #427 = VLD3LNdAsm_32 + { 6, OperandInfo97 }, // Inst #428 = VLD3LNdAsm_8 + { 6, OperandInfo97 }, // Inst #429 = VLD3LNdWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #430 = VLD3LNdWB_fixed_Asm_32 + { 6, OperandInfo97 }, // Inst #431 = VLD3LNdWB_fixed_Asm_8 + { 7, OperandInfo98 }, // Inst #432 = VLD3LNdWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #433 = VLD3LNdWB_register_Asm_32 + { 7, OperandInfo98 }, // Inst #434 = VLD3LNdWB_register_Asm_8 + { 6, OperandInfo97 }, // Inst #435 = VLD3LNqAsm_16 + { 6, OperandInfo97 }, // Inst #436 = VLD3LNqAsm_32 + { 6, OperandInfo97 }, // Inst #437 = VLD3LNqWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #438 = VLD3LNqWB_fixed_Asm_32 + { 7, OperandInfo98 }, // Inst #439 = VLD3LNqWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #440 = VLD3LNqWB_register_Asm_32 + { 5, OperandInfo99 }, // Inst #441 = VLD3dAsm_16 + { 5, OperandInfo99 }, // Inst #442 = VLD3dAsm_32 + { 5, OperandInfo99 }, // Inst #443 = VLD3dAsm_8 + { 5, OperandInfo99 }, // Inst #444 = VLD3dWB_fixed_Asm_16 + { 5, OperandInfo99 }, // Inst #445 = VLD3dWB_fixed_Asm_32 + { 5, OperandInfo99 }, // Inst #446 = VLD3dWB_fixed_Asm_8 + { 6, OperandInfo100 }, // Inst #447 = VLD3dWB_register_Asm_16 + { 6, OperandInfo100 }, // Inst #448 = VLD3dWB_register_Asm_32 + { 6, OperandInfo100 }, // Inst #449 = VLD3dWB_register_Asm_8 + { 5, OperandInfo99 }, // Inst #450 = VLD3qAsm_16 + { 5, OperandInfo99 }, // Inst #451 = VLD3qAsm_32 + { 5, OperandInfo99 }, // Inst #452 = VLD3qAsm_8 + { 5, OperandInfo99 }, // Inst #453 = VLD3qWB_fixed_Asm_16 + { 5, OperandInfo99 }, // Inst #454 = VLD3qWB_fixed_Asm_32 + { 5, OperandInfo99 }, // Inst #455 = VLD3qWB_fixed_Asm_8 + { 6, OperandInfo100 }, // Inst #456 = VLD3qWB_register_Asm_16 + { 6, OperandInfo100 }, // Inst #457 = VLD3qWB_register_Asm_32 + { 6, OperandInfo100 }, // Inst #458 = VLD3qWB_register_Asm_8 + { 5, OperandInfo99 }, // Inst #459 = VLD4DUPdAsm_16 + { 5, OperandInfo99 }, // Inst #460 = VLD4DUPdAsm_32 + { 5, OperandInfo99 }, // Inst #461 = VLD4DUPdAsm_8 + { 5, OperandInfo99 }, // Inst #462 = VLD4DUPdWB_fixed_Asm_16 + { 5, OperandInfo99 }, // Inst #463 = VLD4DUPdWB_fixed_Asm_32 + { 5, OperandInfo99 }, // Inst #464 = VLD4DUPdWB_fixed_Asm_8 + { 6, OperandInfo100 }, // Inst #465 = VLD4DUPdWB_register_Asm_16 + { 6, OperandInfo100 }, // Inst #466 = VLD4DUPdWB_register_Asm_32 + { 6, OperandInfo100 }, // Inst #467 = VLD4DUPdWB_register_Asm_8 + { 5, OperandInfo99 }, // Inst #468 = VLD4DUPqAsm_16 + { 5, OperandInfo99 }, // Inst #469 = VLD4DUPqAsm_32 + { 5, OperandInfo99 }, // Inst #470 = VLD4DUPqAsm_8 + { 5, OperandInfo99 }, // Inst #471 = VLD4DUPqWB_fixed_Asm_16 + { 5, OperandInfo99 }, // Inst #472 = VLD4DUPqWB_fixed_Asm_32 + { 5, OperandInfo99 }, // Inst #473 = VLD4DUPqWB_fixed_Asm_8 + { 6, OperandInfo100 }, // Inst #474 = VLD4DUPqWB_register_Asm_16 + { 6, OperandInfo100 }, // Inst #475 = VLD4DUPqWB_register_Asm_32 + { 6, OperandInfo100 }, // Inst #476 = VLD4DUPqWB_register_Asm_8 + { 6, OperandInfo97 }, // Inst #477 = VLD4LNdAsm_16 + { 6, OperandInfo97 }, // Inst #478 = VLD4LNdAsm_32 + { 6, OperandInfo97 }, // Inst #479 = VLD4LNdAsm_8 + { 6, OperandInfo97 }, // Inst #480 = VLD4LNdWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #481 = VLD4LNdWB_fixed_Asm_32 + { 6, OperandInfo97 }, // Inst #482 = VLD4LNdWB_fixed_Asm_8 + { 7, OperandInfo98 }, // Inst #483 = VLD4LNdWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #484 = VLD4LNdWB_register_Asm_32 + { 7, OperandInfo98 }, // Inst #485 = VLD4LNdWB_register_Asm_8 + { 6, OperandInfo97 }, // Inst #486 = VLD4LNqAsm_16 + { 6, OperandInfo97 }, // Inst #487 = VLD4LNqAsm_32 + { 6, OperandInfo97 }, // Inst #488 = VLD4LNqWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #489 = VLD4LNqWB_fixed_Asm_32 + { 7, OperandInfo98 }, // Inst #490 = VLD4LNqWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #491 = VLD4LNqWB_register_Asm_32 + { 5, OperandInfo99 }, // Inst #492 = VLD4dAsm_16 + { 5, OperandInfo99 }, // Inst #493 = VLD4dAsm_32 + { 5, OperandInfo99 }, // Inst #494 = VLD4dAsm_8 + { 5, OperandInfo99 }, // Inst #495 = VLD4dWB_fixed_Asm_16 + { 5, OperandInfo99 }, // Inst #496 = VLD4dWB_fixed_Asm_32 + { 5, OperandInfo99 }, // Inst #497 = VLD4dWB_fixed_Asm_8 + { 6, OperandInfo100 }, // Inst #498 = VLD4dWB_register_Asm_16 + { 6, OperandInfo100 }, // Inst #499 = VLD4dWB_register_Asm_32 + { 6, OperandInfo100 }, // Inst #500 = VLD4dWB_register_Asm_8 + { 5, OperandInfo99 }, // Inst #501 = VLD4qAsm_16 + { 5, OperandInfo99 }, // Inst #502 = VLD4qAsm_32 + { 5, OperandInfo99 }, // Inst #503 = VLD4qAsm_8 + { 5, OperandInfo99 }, // Inst #504 = VLD4qWB_fixed_Asm_16 + { 5, OperandInfo99 }, // Inst #505 = VLD4qWB_fixed_Asm_32 + { 5, OperandInfo99 }, // Inst #506 = VLD4qWB_fixed_Asm_8 + { 6, OperandInfo100 }, // Inst #507 = VLD4qWB_register_Asm_16 + { 6, OperandInfo100 }, // Inst #508 = VLD4qWB_register_Asm_32 + { 6, OperandInfo100 }, // Inst #509 = VLD4qWB_register_Asm_8 + { 1, OperandInfo101 }, // Inst #510 = VMOVD0 + { 5, OperandInfo102 }, // Inst #511 = VMOVDcc + { 5, OperandInfo103 }, // Inst #512 = VMOVHcc + { 1, OperandInfo104 }, // Inst #513 = VMOVQ0 + { 5, OperandInfo105 }, // Inst #514 = VMOVScc + { 6, OperandInfo97 }, // Inst #515 = VST1LNdAsm_16 + { 6, OperandInfo97 }, // Inst #516 = VST1LNdAsm_32 + { 6, OperandInfo97 }, // Inst #517 = VST1LNdAsm_8 + { 6, OperandInfo97 }, // Inst #518 = VST1LNdWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #519 = VST1LNdWB_fixed_Asm_32 + { 6, OperandInfo97 }, // Inst #520 = VST1LNdWB_fixed_Asm_8 + { 7, OperandInfo98 }, // Inst #521 = VST1LNdWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #522 = VST1LNdWB_register_Asm_32 + { 7, OperandInfo98 }, // Inst #523 = VST1LNdWB_register_Asm_8 + { 6, OperandInfo97 }, // Inst #524 = VST2LNdAsm_16 + { 6, OperandInfo97 }, // Inst #525 = VST2LNdAsm_32 + { 6, OperandInfo97 }, // Inst #526 = VST2LNdAsm_8 + { 6, OperandInfo97 }, // Inst #527 = VST2LNdWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #528 = VST2LNdWB_fixed_Asm_32 + { 6, OperandInfo97 }, // Inst #529 = VST2LNdWB_fixed_Asm_8 + { 7, OperandInfo98 }, // Inst #530 = VST2LNdWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #531 = VST2LNdWB_register_Asm_32 + { 7, OperandInfo98 }, // Inst #532 = VST2LNdWB_register_Asm_8 + { 6, OperandInfo97 }, // Inst #533 = VST2LNqAsm_16 + { 6, OperandInfo97 }, // Inst #534 = VST2LNqAsm_32 + { 6, OperandInfo97 }, // Inst #535 = VST2LNqWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #536 = VST2LNqWB_fixed_Asm_32 + { 7, OperandInfo98 }, // Inst #537 = VST2LNqWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #538 = VST2LNqWB_register_Asm_32 + { 6, OperandInfo97 }, // Inst #539 = VST3LNdAsm_16 + { 6, OperandInfo97 }, // Inst #540 = VST3LNdAsm_32 + { 6, OperandInfo97 }, // Inst #541 = VST3LNdAsm_8 + { 6, OperandInfo97 }, // Inst #542 = VST3LNdWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #543 = VST3LNdWB_fixed_Asm_32 + { 6, OperandInfo97 }, // Inst #544 = VST3LNdWB_fixed_Asm_8 + { 7, OperandInfo98 }, // Inst #545 = VST3LNdWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #546 = VST3LNdWB_register_Asm_32 + { 7, OperandInfo98 }, // Inst #547 = VST3LNdWB_register_Asm_8 + { 6, OperandInfo97 }, // Inst #548 = VST3LNqAsm_16 + { 6, OperandInfo97 }, // Inst #549 = VST3LNqAsm_32 + { 6, OperandInfo97 }, // Inst #550 = VST3LNqWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #551 = VST3LNqWB_fixed_Asm_32 + { 7, OperandInfo98 }, // Inst #552 = VST3LNqWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #553 = VST3LNqWB_register_Asm_32 + { 5, OperandInfo99 }, // Inst #554 = VST3dAsm_16 + { 5, OperandInfo99 }, // Inst #555 = VST3dAsm_32 + { 5, OperandInfo99 }, // Inst #556 = VST3dAsm_8 + { 5, OperandInfo99 }, // Inst #557 = VST3dWB_fixed_Asm_16 + { 5, OperandInfo99 }, // Inst #558 = VST3dWB_fixed_Asm_32 + { 5, OperandInfo99 }, // Inst #559 = VST3dWB_fixed_Asm_8 + { 6, OperandInfo100 }, // Inst #560 = VST3dWB_register_Asm_16 + { 6, OperandInfo100 }, // Inst #561 = VST3dWB_register_Asm_32 + { 6, OperandInfo100 }, // Inst #562 = VST3dWB_register_Asm_8 + { 5, OperandInfo99 }, // Inst #563 = VST3qAsm_16 + { 5, OperandInfo99 }, // Inst #564 = VST3qAsm_32 + { 5, OperandInfo99 }, // Inst #565 = VST3qAsm_8 + { 5, OperandInfo99 }, // Inst #566 = VST3qWB_fixed_Asm_16 + { 5, OperandInfo99 }, // Inst #567 = VST3qWB_fixed_Asm_32 + { 5, OperandInfo99 }, // Inst #568 = VST3qWB_fixed_Asm_8 + { 6, OperandInfo100 }, // Inst #569 = VST3qWB_register_Asm_16 + { 6, OperandInfo100 }, // Inst #570 = VST3qWB_register_Asm_32 + { 6, OperandInfo100 }, // Inst #571 = VST3qWB_register_Asm_8 + { 6, OperandInfo97 }, // Inst #572 = VST4LNdAsm_16 + { 6, OperandInfo97 }, // Inst #573 = VST4LNdAsm_32 + { 6, OperandInfo97 }, // Inst #574 = VST4LNdAsm_8 + { 6, OperandInfo97 }, // Inst #575 = VST4LNdWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #576 = VST4LNdWB_fixed_Asm_32 + { 6, OperandInfo97 }, // Inst #577 = VST4LNdWB_fixed_Asm_8 + { 7, OperandInfo98 }, // Inst #578 = VST4LNdWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #579 = VST4LNdWB_register_Asm_32 + { 7, OperandInfo98 }, // Inst #580 = VST4LNdWB_register_Asm_8 + { 6, OperandInfo97 }, // Inst #581 = VST4LNqAsm_16 + { 6, OperandInfo97 }, // Inst #582 = VST4LNqAsm_32 + { 6, OperandInfo97 }, // Inst #583 = VST4LNqWB_fixed_Asm_16 + { 6, OperandInfo97 }, // Inst #584 = VST4LNqWB_fixed_Asm_32 + { 7, OperandInfo98 }, // Inst #585 = VST4LNqWB_register_Asm_16 + { 7, OperandInfo98 }, // Inst #586 = VST4LNqWB_register_Asm_32 + { 5, OperandInfo99 }, // Inst #587 = VST4dAsm_16 + { 5, OperandInfo99 }, // Inst #588 = VST4dAsm_32 + { 5, OperandInfo99 }, // Inst #589 = VST4dAsm_8 + { 5, OperandInfo99 }, // Inst #590 = VST4dWB_fixed_Asm_16 + { 5, OperandInfo99 }, // Inst #591 = VST4dWB_fixed_Asm_32 + { 5, OperandInfo99 }, // Inst #592 = VST4dWB_fixed_Asm_8 + { 6, OperandInfo100 }, // Inst #593 = VST4dWB_register_Asm_16 + { 6, OperandInfo100 }, // Inst #594 = VST4dWB_register_Asm_32 + { 6, OperandInfo100 }, // Inst #595 = VST4dWB_register_Asm_8 + { 5, OperandInfo99 }, // Inst #596 = VST4qAsm_16 + { 5, OperandInfo99 }, // Inst #597 = VST4qAsm_32 + { 5, OperandInfo99 }, // Inst #598 = VST4qAsm_8 + { 5, OperandInfo99 }, // Inst #599 = VST4qWB_fixed_Asm_16 + { 5, OperandInfo99 }, // Inst #600 = VST4qWB_fixed_Asm_32 + { 5, OperandInfo99 }, // Inst #601 = VST4qWB_fixed_Asm_8 + { 6, OperandInfo100 }, // Inst #602 = VST4qWB_register_Asm_16 + { 6, OperandInfo100 }, // Inst #603 = VST4qWB_register_Asm_32 + { 6, OperandInfo100 }, // Inst #604 = VST4qWB_register_Asm_8 + { 0, 0 }, // Inst #605 = WIN__CHKSTK + { 1, OperandInfo58 }, // Inst #606 = WIN__DBZCHK + { 2, OperandInfo106 }, // Inst #607 = t2ABS + { 5, OperandInfo107 }, // Inst #608 = t2ADDSri + { 5, OperandInfo108 }, // Inst #609 = t2ADDSrr + { 6, OperandInfo109 }, // Inst #610 = t2ADDSrs + { 1, OperandInfo2 }, // Inst #611 = t2BF_LabelPseudo + { 3, OperandInfo59 }, // Inst #612 = t2BR_JT + { 3, OperandInfo110 }, // Inst #613 = t2CALL_BTI + { 2, OperandInfo111 }, // Inst #614 = t2DoLoopStart + { 3, OperandInfo112 }, // Inst #615 = t2DoLoopStartTP + { 5, OperandInfo66 }, // Inst #616 = t2LDMIA_RET + { 4, OperandInfo113 }, // Inst #617 = t2LDRBpcrel + { 4, OperandInfo68 }, // Inst #618 = t2LDRConstPool + { 4, OperandInfo113 }, // Inst #619 = t2LDRHpcrel + { 2, OperandInfo114 }, // Inst #620 = t2LDRLIT_ga_pcrel + { 4, OperandInfo113 }, // Inst #621 = t2LDRSBpcrel + { 4, OperandInfo113 }, // Inst #622 = t2LDRSHpcrel + { 5, OperandInfo87 }, // Inst #623 = t2LDR_POST_imm + { 5, OperandInfo87 }, // Inst #624 = t2LDR_PRE_imm + { 3, OperandInfo115 }, // Inst #625 = t2LDRpci_pic + { 4, OperandInfo68 }, // Inst #626 = t2LDRpcrel + { 4, OperandInfo116 }, // Inst #627 = t2LEApcrel + { 4, OperandInfo116 }, // Inst #628 = t2LEApcrelJT + { 3, OperandInfo117 }, // Inst #629 = t2LoopDec + { 2, OperandInfo57 }, // Inst #630 = t2LoopEnd + { 3, OperandInfo118 }, // Inst #631 = t2LoopEndDec + { 6, OperandInfo119 }, // Inst #632 = t2MOVCCasr + { 5, OperandInfo120 }, // Inst #633 = t2MOVCCi + { 5, OperandInfo120 }, // Inst #634 = t2MOVCCi16 + { 5, OperandInfo121 }, // Inst #635 = t2MOVCCi32imm + { 6, OperandInfo119 }, // Inst #636 = t2MOVCClsl + { 6, OperandInfo119 }, // Inst #637 = t2MOVCClsr + { 5, OperandInfo122 }, // Inst #638 = t2MOVCCr + { 6, OperandInfo119 }, // Inst #639 = t2MOVCCror + { 5, OperandInfo123 }, // Inst #640 = t2MOVSsi + { 6, OperandInfo124 }, // Inst #641 = t2MOVSsr + { 4, OperandInfo125 }, // Inst #642 = t2MOVTi16_ga_pcrel + { 2, OperandInfo114 }, // Inst #643 = t2MOV_ga_pcrel + { 3, OperandInfo115 }, // Inst #644 = t2MOVi16_ga_pcrel + { 2, OperandInfo114 }, // Inst #645 = t2MOVi32imm + { 5, OperandInfo123 }, // Inst #646 = t2MOVsi + { 6, OperandInfo124 }, // Inst #647 = t2MOVsr + { 5, OperandInfo120 }, // Inst #648 = t2MVNCCi + { 5, OperandInfo126 }, // Inst #649 = t2RSBSri + { 6, OperandInfo127 }, // Inst #650 = t2RSBSrs + { 6, OperandInfo128 }, // Inst #651 = t2STRB_preidx + { 6, OperandInfo128 }, // Inst #652 = t2STRH_preidx + { 5, OperandInfo87 }, // Inst #653 = t2STR_POST_imm + { 5, OperandInfo87 }, // Inst #654 = t2STR_PRE_imm + { 6, OperandInfo128 }, // Inst #655 = t2STR_preidx + { 5, OperandInfo107 }, // Inst #656 = t2SUBSri + { 5, OperandInfo108 }, // Inst #657 = t2SUBSrr + { 6, OperandInfo109 }, // Inst #658 = t2SUBSrs + { 0, 0 }, // Inst #659 = t2SpeculationBarrierISBDSBEndBB + { 0, 0 }, // Inst #660 = t2SpeculationBarrierSBEndBB + { 4, OperandInfo65 }, // Inst #661 = t2TBB_JT + { 4, OperandInfo65 }, // Inst #662 = t2TBH_JT + { 2, OperandInfo111 }, // Inst #663 = t2WhileLoopSetup + { 2, OperandInfo57 }, // Inst #664 = t2WhileLoopStart + { 3, OperandInfo129 }, // Inst #665 = t2WhileLoopStartLR + { 4, OperandInfo130 }, // Inst #666 = t2WhileLoopStartTP + { 3, OperandInfo131 }, // Inst #667 = tADCS + { 3, OperandInfo132 }, // Inst #668 = tADDSi3 + { 3, OperandInfo132 }, // Inst #669 = tADDSi8 + { 3, OperandInfo131 }, // Inst #670 = tADDSrr + { 3, OperandInfo133 }, // Inst #671 = tADDframe + { 2, OperandInfo10 }, // Inst #672 = tADJCALLSTACKDOWN + { 2, OperandInfo10 }, // Inst #673 = tADJCALLSTACKUP + { 1, OperandInfo134 }, // Inst #674 = tBLXNS_CALL + { 3, OperandInfo135 }, // Inst #675 = tBLXr_noip + { 4, OperandInfo136 }, // Inst #676 = tBL_PUSHLR + { 3, OperandInfo137 }, // Inst #677 = tBRIND + { 2, OperandInfo138 }, // Inst #678 = tBR_JTr + { 0, 0 }, // Inst #679 = tBXNS_RET + { 1, OperandInfo58 }, // Inst #680 = tBX_CALL + { 2, OperandInfo139 }, // Inst #681 = tBX_RET + { 3, OperandInfo140 }, // Inst #682 = tBX_RET_vararg + { 3, OperandInfo141 }, // Inst #683 = tBfar + { 5, OperandInfo142 }, // Inst #684 = tCMP_SWAP_16 + { 5, OperandInfo143 }, // Inst #685 = tCMP_SWAP_32 + { 5, OperandInfo142 }, // Inst #686 = tCMP_SWAP_8 + { 5, OperandInfo144 }, // Inst #687 = tLDMIA_UPD + { 4, OperandInfo145 }, // Inst #688 = tLDRConstPool + { 2, OperandInfo138 }, // Inst #689 = tLDRLIT_ga_abs + { 2, OperandInfo138 }, // Inst #690 = tLDRLIT_ga_pcrel + { 5, OperandInfo146 }, // Inst #691 = tLDR_postidx + { 3, OperandInfo147 }, // Inst #692 = tLDRpci_pic + { 4, OperandInfo148 }, // Inst #693 = tLEApcrel + { 4, OperandInfo148 }, // Inst #694 = tLEApcrelJT + { 3, OperandInfo132 }, // Inst #695 = tLSLSri + { 5, OperandInfo149 }, // Inst #696 = tMOVCCr_pseudo + { 3, OperandInfo150 }, // Inst #697 = tPOP_RET + { 2, OperandInfo151 }, // Inst #698 = tRSBS + { 3, OperandInfo131 }, // Inst #699 = tSBCS + { 3, OperandInfo132 }, // Inst #700 = tSUBSi3 + { 3, OperandInfo132 }, // Inst #701 = tSUBSi8 + { 3, OperandInfo131 }, // Inst #702 = tSUBSrr + { 3, OperandInfo141 }, // Inst #703 = tTAILJMPd + { 3, OperandInfo141 }, // Inst #704 = tTAILJMPdND + { 1, OperandInfo95 }, // Inst #705 = tTAILJMPr + { 4, OperandInfo152 }, // Inst #706 = tTBB_JT + { 4, OperandInfo152 }, // Inst #707 = tTBH_JT + { 0, 0 }, // Inst #708 = tTPsoft + { 6, OperandInfo51 }, // Inst #709 = ADCri + { 6, OperandInfo153 }, // Inst #710 = ADCrr + { 7, OperandInfo154 }, // Inst #711 = ADCrsi + { 8, OperandInfo155 }, // Inst #712 = ADCrsr + { 6, OperandInfo51 }, // Inst #713 = ADDri + { 6, OperandInfo153 }, // Inst #714 = ADDrr + { 7, OperandInfo154 }, // Inst #715 = ADDrsi + { 8, OperandInfo156 }, // Inst #716 = ADDrsr + { 4, OperandInfo68 }, // Inst #717 = ADR + { 3, OperandInfo157 }, // Inst #718 = AESD + { 3, OperandInfo157 }, // Inst #719 = AESE + { 2, OperandInfo158 }, // Inst #720 = AESIMC + { 2, OperandInfo158 }, // Inst #721 = AESMC + { 6, OperandInfo51 }, // Inst #722 = ANDri + { 6, OperandInfo153 }, // Inst #723 = ANDrr + { 7, OperandInfo154 }, // Inst #724 = ANDrsi + { 8, OperandInfo156 }, // Inst #725 = ANDrsr + { 5, OperandInfo159 }, // Inst #726 = BF16VDOTI_VDOTD + { 5, OperandInfo160 }, // Inst #727 = BF16VDOTI_VDOTQ + { 4, OperandInfo161 }, // Inst #728 = BF16VDOTS_VDOTD + { 4, OperandInfo162 }, // Inst #729 = BF16VDOTS_VDOTQ + { 4, OperandInfo163 }, // Inst #730 = BF16_VCVT + { 5, OperandInfo105 }, // Inst #731 = BF16_VCVTB + { 5, OperandInfo105 }, // Inst #732 = BF16_VCVTT + { 5, OperandInfo73 }, // Inst #733 = BFC + { 6, OperandInfo164 }, // Inst #734 = BFI + { 6, OperandInfo51 }, // Inst #735 = BICri + { 6, OperandInfo153 }, // Inst #736 = BICrr + { 7, OperandInfo154 }, // Inst #737 = BICrsi + { 8, OperandInfo156 }, // Inst #738 = BICrsr + { 1, OperandInfo2 }, // Inst #739 = BKPT + { 1, OperandInfo53 }, // Inst #740 = BL + { 1, OperandInfo78 }, // Inst #741 = BLX + { 3, OperandInfo137 }, // Inst #742 = BLX_pred + { 1, OperandInfo53 }, // Inst #743 = BLXi + { 3, OperandInfo141 }, // Inst #744 = BL_pred + { 1, OperandInfo78 }, // Inst #745 = BX + { 3, OperandInfo137 }, // Inst #746 = BXJ + { 2, OperandInfo139 }, // Inst #747 = BX_RET + { 3, OperandInfo137 }, // Inst #748 = BX_pred + { 3, OperandInfo141 }, // Inst #749 = Bcc + { 3, OperandInfo165 }, // Inst #750 = CDE_CX1 + { 6, OperandInfo166 }, // Inst #751 = CDE_CX1A + { 3, OperandInfo167 }, // Inst #752 = CDE_CX1D + { 6, OperandInfo168 }, // Inst #753 = CDE_CX1DA + { 4, OperandInfo169 }, // Inst #754 = CDE_CX2 + { 7, OperandInfo170 }, // Inst #755 = CDE_CX2A + { 4, OperandInfo171 }, // Inst #756 = CDE_CX2D + { 7, OperandInfo172 }, // Inst #757 = CDE_CX2DA + { 5, OperandInfo173 }, // Inst #758 = CDE_CX3 + { 8, OperandInfo174 }, // Inst #759 = CDE_CX3A + { 5, OperandInfo175 }, // Inst #760 = CDE_CX3D + { 8, OperandInfo176 }, // Inst #761 = CDE_CX3DA + { 4, OperandInfo177 }, // Inst #762 = CDE_VCX1A_fpdp + { 4, OperandInfo178 }, // Inst #763 = CDE_VCX1A_fpsp + { 7, OperandInfo179 }, // Inst #764 = CDE_VCX1A_vec + { 3, OperandInfo180 }, // Inst #765 = CDE_VCX1_fpdp + { 3, OperandInfo181 }, // Inst #766 = CDE_VCX1_fpsp + { 7, OperandInfo182 }, // Inst #767 = CDE_VCX1_vec + { 5, OperandInfo183 }, // Inst #768 = CDE_VCX2A_fpdp + { 5, OperandInfo184 }, // Inst #769 = CDE_VCX2A_fpsp + { 8, OperandInfo185 }, // Inst #770 = CDE_VCX2A_vec + { 4, OperandInfo186 }, // Inst #771 = CDE_VCX2_fpdp + { 4, OperandInfo187 }, // Inst #772 = CDE_VCX2_fpsp + { 8, OperandInfo188 }, // Inst #773 = CDE_VCX2_vec + { 6, OperandInfo189 }, // Inst #774 = CDE_VCX3A_fpdp + { 6, OperandInfo190 }, // Inst #775 = CDE_VCX3A_fpsp + { 9, OperandInfo191 }, // Inst #776 = CDE_VCX3A_vec + { 5, OperandInfo192 }, // Inst #777 = CDE_VCX3_fpdp + { 5, OperandInfo193 }, // Inst #778 = CDE_VCX3_fpsp + { 9, OperandInfo194 }, // Inst #779 = CDE_VCX3_vec + { 8, OperandInfo195 }, // Inst #780 = CDP + { 6, OperandInfo196 }, // Inst #781 = CDP2 + { 0, 0 }, // Inst #782 = CLREX + { 4, OperandInfo197 }, // Inst #783 = CLZ + { 4, OperandInfo68 }, // Inst #784 = CMNri + { 4, OperandInfo197 }, // Inst #785 = CMNzrr + { 5, OperandInfo198 }, // Inst #786 = CMNzrsi + { 6, OperandInfo199 }, // Inst #787 = CMNzrsr + { 4, OperandInfo68 }, // Inst #788 = CMPri + { 4, OperandInfo197 }, // Inst #789 = CMPrr + { 5, OperandInfo198 }, // Inst #790 = CMPrsi + { 6, OperandInfo199 }, // Inst #791 = CMPrsr + { 1, OperandInfo2 }, // Inst #792 = CPS1p + { 2, OperandInfo7 }, // Inst #793 = CPS2p + { 3, OperandInfo200 }, // Inst #794 = CPS3p + { 3, OperandInfo201 }, // Inst #795 = CRC32B + { 3, OperandInfo201 }, // Inst #796 = CRC32CB + { 3, OperandInfo201 }, // Inst #797 = CRC32CH + { 3, OperandInfo201 }, // Inst #798 = CRC32CW + { 3, OperandInfo201 }, // Inst #799 = CRC32H + { 3, OperandInfo201 }, // Inst #800 = CRC32W + { 3, OperandInfo202 }, // Inst #801 = DBG + { 1, OperandInfo2 }, // Inst #802 = DMB + { 1, OperandInfo2 }, // Inst #803 = DSB + { 6, OperandInfo51 }, // Inst #804 = EORri + { 6, OperandInfo153 }, // Inst #805 = EORrr + { 7, OperandInfo154 }, // Inst #806 = EORrsi + { 8, OperandInfo156 }, // Inst #807 = EORrsr + { 2, OperandInfo139 }, // Inst #808 = ERET + { 4, OperandInfo203 }, // Inst #809 = FCONSTD + { 4, OperandInfo204 }, // Inst #810 = FCONSTH + { 4, OperandInfo205 }, // Inst #811 = FCONSTS + { 5, OperandInfo66 }, // Inst #812 = FLDMXDB_UPD + { 4, OperandInfo206 }, // Inst #813 = FLDMXIA + { 5, OperandInfo66 }, // Inst #814 = FLDMXIA_UPD + { 2, OperandInfo139 }, // Inst #815 = FMSTAT + { 5, OperandInfo66 }, // Inst #816 = FSTMXDB_UPD + { 4, OperandInfo206 }, // Inst #817 = FSTMXIA + { 5, OperandInfo66 }, // Inst #818 = FSTMXIA_UPD + { 3, OperandInfo202 }, // Inst #819 = HINT + { 1, OperandInfo2 }, // Inst #820 = HLT + { 1, OperandInfo2 }, // Inst #821 = HVC + { 1, OperandInfo2 }, // Inst #822 = ISB + { 4, OperandInfo67 }, // Inst #823 = LDA + { 4, OperandInfo67 }, // Inst #824 = LDAB + { 4, OperandInfo67 }, // Inst #825 = LDAEX + { 4, OperandInfo67 }, // Inst #826 = LDAEXB + { 4, OperandInfo207 }, // Inst #827 = LDAEXD + { 4, OperandInfo67 }, // Inst #828 = LDAEXH + { 4, OperandInfo67 }, // Inst #829 = LDAH + { 4, OperandInfo208 }, // Inst #830 = LDC2L_OFFSET + { 4, OperandInfo209 }, // Inst #831 = LDC2L_OPTION + { 4, OperandInfo208 }, // Inst #832 = LDC2L_POST + { 5, OperandInfo210 }, // Inst #833 = LDC2L_PRE + { 4, OperandInfo208 }, // Inst #834 = LDC2_OFFSET + { 4, OperandInfo209 }, // Inst #835 = LDC2_OPTION + { 4, OperandInfo208 }, // Inst #836 = LDC2_POST + { 5, OperandInfo210 }, // Inst #837 = LDC2_PRE + { 6, OperandInfo211 }, // Inst #838 = LDCL_OFFSET + { 6, OperandInfo212 }, // Inst #839 = LDCL_OPTION + { 6, OperandInfo211 }, // Inst #840 = LDCL_POST + { 7, OperandInfo213 }, // Inst #841 = LDCL_PRE + { 6, OperandInfo211 }, // Inst #842 = LDC_OFFSET + { 6, OperandInfo212 }, // Inst #843 = LDC_OPTION + { 6, OperandInfo211 }, // Inst #844 = LDC_POST + { 7, OperandInfo213 }, // Inst #845 = LDC_PRE + { 4, OperandInfo206 }, // Inst #846 = LDMDA + { 5, OperandInfo66 }, // Inst #847 = LDMDA_UPD + { 4, OperandInfo206 }, // Inst #848 = LDMDB + { 5, OperandInfo66 }, // Inst #849 = LDMDB_UPD + { 4, OperandInfo206 }, // Inst #850 = LDMIA + { 5, OperandInfo66 }, // Inst #851 = LDMIA_UPD + { 4, OperandInfo206 }, // Inst #852 = LDMIB + { 5, OperandInfo66 }, // Inst #853 = LDMIB_UPD + { 7, OperandInfo214 }, // Inst #854 = LDRBT_POST_IMM + { 7, OperandInfo214 }, // Inst #855 = LDRBT_POST_REG + { 7, OperandInfo214 }, // Inst #856 = LDRB_POST_IMM + { 7, OperandInfo214 }, // Inst #857 = LDRB_POST_REG + { 6, OperandInfo215 }, // Inst #858 = LDRB_PRE_IMM + { 7, OperandInfo214 }, // Inst #859 = LDRB_PRE_REG + { 5, OperandInfo216 }, // Inst #860 = LDRBi12 + { 6, OperandInfo217 }, // Inst #861 = LDRBrs + { 7, OperandInfo218 }, // Inst #862 = LDRD + { 8, OperandInfo219 }, // Inst #863 = LDRD_POST + { 8, OperandInfo219 }, // Inst #864 = LDRD_PRE + { 4, OperandInfo67 }, // Inst #865 = LDREX + { 4, OperandInfo67 }, // Inst #866 = LDREXB + { 4, OperandInfo207 }, // Inst #867 = LDREXD + { 4, OperandInfo67 }, // Inst #868 = LDREXH + { 6, OperandInfo220 }, // Inst #869 = LDRH + { 6, OperandInfo215 }, // Inst #870 = LDRHTi + { 7, OperandInfo221 }, // Inst #871 = LDRHTr + { 7, OperandInfo222 }, // Inst #872 = LDRH_POST + { 7, OperandInfo222 }, // Inst #873 = LDRH_PRE + { 6, OperandInfo220 }, // Inst #874 = LDRSB + { 6, OperandInfo215 }, // Inst #875 = LDRSBTi + { 7, OperandInfo221 }, // Inst #876 = LDRSBTr + { 7, OperandInfo222 }, // Inst #877 = LDRSB_POST + { 7, OperandInfo222 }, // Inst #878 = LDRSB_PRE + { 6, OperandInfo220 }, // Inst #879 = LDRSH + { 6, OperandInfo215 }, // Inst #880 = LDRSHTi + { 7, OperandInfo221 }, // Inst #881 = LDRSHTr + { 7, OperandInfo222 }, // Inst #882 = LDRSH_POST + { 7, OperandInfo222 }, // Inst #883 = LDRSH_PRE + { 7, OperandInfo214 }, // Inst #884 = LDRT_POST_IMM + { 7, OperandInfo214 }, // Inst #885 = LDRT_POST_REG + { 7, OperandInfo214 }, // Inst #886 = LDR_POST_IMM + { 7, OperandInfo214 }, // Inst #887 = LDR_POST_REG + { 6, OperandInfo215 }, // Inst #888 = LDR_PRE_IMM + { 7, OperandInfo214 }, // Inst #889 = LDR_PRE_REG + { 5, OperandInfo87 }, // Inst #890 = LDRcp + { 5, OperandInfo87 }, // Inst #891 = LDRi12 + { 6, OperandInfo223 }, // Inst #892 = LDRrs + { 8, OperandInfo224 }, // Inst #893 = MCR + { 6, OperandInfo225 }, // Inst #894 = MCR2 + { 7, OperandInfo226 }, // Inst #895 = MCRR + { 5, OperandInfo227 }, // Inst #896 = MCRR2 + { 7, OperandInfo228 }, // Inst #897 = MLA + { 6, OperandInfo229 }, // Inst #898 = MLS + { 2, OperandInfo139 }, // Inst #899 = MOVPCLR + { 5, OperandInfo230 }, // Inst #900 = MOVTi16 + { 5, OperandInfo231 }, // Inst #901 = MOVi + { 4, OperandInfo68 }, // Inst #902 = MOVi16 + { 5, OperandInfo88 }, // Inst #903 = MOVr + { 5, OperandInfo232 }, // Inst #904 = MOVr_TC + { 6, OperandInfo233 }, // Inst #905 = MOVsi + { 7, OperandInfo234 }, // Inst #906 = MOVsr + { 8, OperandInfo235 }, // Inst #907 = MRC + { 6, OperandInfo236 }, // Inst #908 = MRC2 + { 7, OperandInfo237 }, // Inst #909 = MRRC + { 5, OperandInfo238 }, // Inst #910 = MRRC2 + { 3, OperandInfo239 }, // Inst #911 = MRS + { 4, OperandInfo113 }, // Inst #912 = MRSbanked + { 3, OperandInfo239 }, // Inst #913 = MRSsys + { 4, OperandInfo240 }, // Inst #914 = MSR + { 4, OperandInfo241 }, // Inst #915 = MSRbanked + { 4, OperandInfo242 }, // Inst #916 = MSRi + { 6, OperandInfo52 }, // Inst #917 = MUL + { 7, OperandInfo243 }, // Inst #918 = MVE_ASRLi + { 7, OperandInfo244 }, // Inst #919 = MVE_ASRLr + { 2, OperandInfo111 }, // Inst #920 = MVE_DLSTP_16 + { 2, OperandInfo111 }, // Inst #921 = MVE_DLSTP_32 + { 2, OperandInfo111 }, // Inst #922 = MVE_DLSTP_64 + { 2, OperandInfo111 }, // Inst #923 = MVE_DLSTP_8 + { 2, OperandInfo139 }, // Inst #924 = MVE_LCTP + { 3, OperandInfo118 }, // Inst #925 = MVE_LETP + { 7, OperandInfo243 }, // Inst #926 = MVE_LSLLi + { 7, OperandInfo244 }, // Inst #927 = MVE_LSLLr + { 7, OperandInfo243 }, // Inst #928 = MVE_LSRL + { 5, OperandInfo122 }, // Inst #929 = MVE_SQRSHR + { 8, OperandInfo245 }, // Inst #930 = MVE_SQRSHRL + { 5, OperandInfo120 }, // Inst #931 = MVE_SQSHL + { 7, OperandInfo243 }, // Inst #932 = MVE_SQSHLL + { 5, OperandInfo120 }, // Inst #933 = MVE_SRSHR + { 7, OperandInfo243 }, // Inst #934 = MVE_SRSHRL + { 5, OperandInfo122 }, // Inst #935 = MVE_UQRSHL + { 8, OperandInfo245 }, // Inst #936 = MVE_UQRSHLL + { 5, OperandInfo120 }, // Inst #937 = MVE_UQSHL + { 7, OperandInfo243 }, // Inst #938 = MVE_UQSHLL + { 5, OperandInfo120 }, // Inst #939 = MVE_URSHR + { 7, OperandInfo243 }, // Inst #940 = MVE_URSHRL + { 7, OperandInfo246 }, // Inst #941 = MVE_VABAVs16 + { 7, OperandInfo246 }, // Inst #942 = MVE_VABAVs32 + { 7, OperandInfo246 }, // Inst #943 = MVE_VABAVs8 + { 7, OperandInfo246 }, // Inst #944 = MVE_VABAVu16 + { 7, OperandInfo246 }, // Inst #945 = MVE_VABAVu32 + { 7, OperandInfo246 }, // Inst #946 = MVE_VABAVu8 + { 7, OperandInfo247 }, // Inst #947 = MVE_VABDf16 + { 7, OperandInfo247 }, // Inst #948 = MVE_VABDf32 + { 7, OperandInfo247 }, // Inst #949 = MVE_VABDs16 + { 7, OperandInfo247 }, // Inst #950 = MVE_VABDs32 + { 7, OperandInfo247 }, // Inst #951 = MVE_VABDs8 + { 7, OperandInfo247 }, // Inst #952 = MVE_VABDu16 + { 7, OperandInfo247 }, // Inst #953 = MVE_VABDu32 + { 7, OperandInfo247 }, // Inst #954 = MVE_VABDu8 + { 6, OperandInfo248 }, // Inst #955 = MVE_VABSf16 + { 6, OperandInfo248 }, // Inst #956 = MVE_VABSf32 + { 6, OperandInfo248 }, // Inst #957 = MVE_VABSs16 + { 6, OperandInfo248 }, // Inst #958 = MVE_VABSs32 + { 6, OperandInfo248 }, // Inst #959 = MVE_VABSs8 + { 9, OperandInfo249 }, // Inst #960 = MVE_VADC + { 8, OperandInfo250 }, // Inst #961 = MVE_VADCI + { 8, OperandInfo251 }, // Inst #962 = MVE_VADDLVs32acc + { 6, OperandInfo252 }, // Inst #963 = MVE_VADDLVs32no_acc + { 8, OperandInfo251 }, // Inst #964 = MVE_VADDLVu32acc + { 6, OperandInfo252 }, // Inst #965 = MVE_VADDLVu32no_acc + { 6, OperandInfo253 }, // Inst #966 = MVE_VADDVs16acc + { 5, OperandInfo254 }, // Inst #967 = MVE_VADDVs16no_acc + { 6, OperandInfo253 }, // Inst #968 = MVE_VADDVs32acc + { 5, OperandInfo254 }, // Inst #969 = MVE_VADDVs32no_acc + { 6, OperandInfo253 }, // Inst #970 = MVE_VADDVs8acc + { 5, OperandInfo254 }, // Inst #971 = MVE_VADDVs8no_acc + { 6, OperandInfo253 }, // Inst #972 = MVE_VADDVu16acc + { 5, OperandInfo254 }, // Inst #973 = MVE_VADDVu16no_acc + { 6, OperandInfo253 }, // Inst #974 = MVE_VADDVu32acc + { 5, OperandInfo254 }, // Inst #975 = MVE_VADDVu32no_acc + { 6, OperandInfo253 }, // Inst #976 = MVE_VADDVu8acc + { 5, OperandInfo254 }, // Inst #977 = MVE_VADDVu8no_acc + { 7, OperandInfo255 }, // Inst #978 = MVE_VADD_qr_f16 + { 7, OperandInfo255 }, // Inst #979 = MVE_VADD_qr_f32 + { 7, OperandInfo255 }, // Inst #980 = MVE_VADD_qr_i16 + { 7, OperandInfo255 }, // Inst #981 = MVE_VADD_qr_i32 + { 7, OperandInfo255 }, // Inst #982 = MVE_VADD_qr_i8 + { 7, OperandInfo247 }, // Inst #983 = MVE_VADDf16 + { 7, OperandInfo247 }, // Inst #984 = MVE_VADDf32 + { 7, OperandInfo247 }, // Inst #985 = MVE_VADDi16 + { 7, OperandInfo247 }, // Inst #986 = MVE_VADDi32 + { 7, OperandInfo247 }, // Inst #987 = MVE_VADDi8 + { 7, OperandInfo247 }, // Inst #988 = MVE_VAND + { 7, OperandInfo247 }, // Inst #989 = MVE_VBIC + { 6, OperandInfo256 }, // Inst #990 = MVE_VBICimmi16 + { 6, OperandInfo256 }, // Inst #991 = MVE_VBICimmi32 + { 7, OperandInfo255 }, // Inst #992 = MVE_VBRSR16 + { 7, OperandInfo255 }, // Inst #993 = MVE_VBRSR32 + { 7, OperandInfo255 }, // Inst #994 = MVE_VBRSR8 + { 8, OperandInfo257 }, // Inst #995 = MVE_VCADDf16 + { 8, OperandInfo258 }, // Inst #996 = MVE_VCADDf32 + { 8, OperandInfo257 }, // Inst #997 = MVE_VCADDi16 + { 8, OperandInfo258 }, // Inst #998 = MVE_VCADDi32 + { 8, OperandInfo257 }, // Inst #999 = MVE_VCADDi8 + { 6, OperandInfo248 }, // Inst #1000 = MVE_VCLSs16 + { 6, OperandInfo248 }, // Inst #1001 = MVE_VCLSs32 + { 6, OperandInfo248 }, // Inst #1002 = MVE_VCLSs8 + { 6, OperandInfo248 }, // Inst #1003 = MVE_VCLZs16 + { 6, OperandInfo248 }, // Inst #1004 = MVE_VCLZs32 + { 6, OperandInfo248 }, // Inst #1005 = MVE_VCLZs8 + { 8, OperandInfo259 }, // Inst #1006 = MVE_VCMLAf16 + { 8, OperandInfo259 }, // Inst #1007 = MVE_VCMLAf32 + { 7, OperandInfo260 }, // Inst #1008 = MVE_VCMPf16 + { 7, OperandInfo261 }, // Inst #1009 = MVE_VCMPf16r + { 7, OperandInfo260 }, // Inst #1010 = MVE_VCMPf32 + { 7, OperandInfo261 }, // Inst #1011 = MVE_VCMPf32r + { 7, OperandInfo260 }, // Inst #1012 = MVE_VCMPi16 + { 7, OperandInfo261 }, // Inst #1013 = MVE_VCMPi16r + { 7, OperandInfo260 }, // Inst #1014 = MVE_VCMPi32 + { 7, OperandInfo261 }, // Inst #1015 = MVE_VCMPi32r + { 7, OperandInfo260 }, // Inst #1016 = MVE_VCMPi8 + { 7, OperandInfo261 }, // Inst #1017 = MVE_VCMPi8r + { 7, OperandInfo260 }, // Inst #1018 = MVE_VCMPs16 + { 7, OperandInfo261 }, // Inst #1019 = MVE_VCMPs16r + { 7, OperandInfo260 }, // Inst #1020 = MVE_VCMPs32 + { 7, OperandInfo261 }, // Inst #1021 = MVE_VCMPs32r + { 7, OperandInfo260 }, // Inst #1022 = MVE_VCMPs8 + { 7, OperandInfo261 }, // Inst #1023 = MVE_VCMPs8r + { 7, OperandInfo260 }, // Inst #1024 = MVE_VCMPu16 + { 7, OperandInfo261 }, // Inst #1025 = MVE_VCMPu16r + { 7, OperandInfo260 }, // Inst #1026 = MVE_VCMPu32 + { 7, OperandInfo261 }, // Inst #1027 = MVE_VCMPu32r + { 7, OperandInfo260 }, // Inst #1028 = MVE_VCMPu8 + { 7, OperandInfo261 }, // Inst #1029 = MVE_VCMPu8r + { 8, OperandInfo257 }, // Inst #1030 = MVE_VCMULf16 + { 8, OperandInfo258 }, // Inst #1031 = MVE_VCMULf32 + { 5, OperandInfo262 }, // Inst #1032 = MVE_VCTP16 + { 5, OperandInfo262 }, // Inst #1033 = MVE_VCTP32 + { 5, OperandInfo262 }, // Inst #1034 = MVE_VCTP64 + { 5, OperandInfo262 }, // Inst #1035 = MVE_VCTP8 + { 6, OperandInfo263 }, // Inst #1036 = MVE_VCVTf16f32bh + { 6, OperandInfo263 }, // Inst #1037 = MVE_VCVTf16f32th + { 7, OperandInfo264 }, // Inst #1038 = MVE_VCVTf16s16_fix + { 6, OperandInfo248 }, // Inst #1039 = MVE_VCVTf16s16n + { 7, OperandInfo264 }, // Inst #1040 = MVE_VCVTf16u16_fix + { 6, OperandInfo248 }, // Inst #1041 = MVE_VCVTf16u16n + { 6, OperandInfo248 }, // Inst #1042 = MVE_VCVTf32f16bh + { 6, OperandInfo248 }, // Inst #1043 = MVE_VCVTf32f16th + { 7, OperandInfo264 }, // Inst #1044 = MVE_VCVTf32s32_fix + { 6, OperandInfo248 }, // Inst #1045 = MVE_VCVTf32s32n + { 7, OperandInfo264 }, // Inst #1046 = MVE_VCVTf32u32_fix + { 6, OperandInfo248 }, // Inst #1047 = MVE_VCVTf32u32n + { 7, OperandInfo264 }, // Inst #1048 = MVE_VCVTs16f16_fix + { 6, OperandInfo248 }, // Inst #1049 = MVE_VCVTs16f16a + { 6, OperandInfo248 }, // Inst #1050 = MVE_VCVTs16f16m + { 6, OperandInfo248 }, // Inst #1051 = MVE_VCVTs16f16n + { 6, OperandInfo248 }, // Inst #1052 = MVE_VCVTs16f16p + { 6, OperandInfo248 }, // Inst #1053 = MVE_VCVTs16f16z + { 7, OperandInfo264 }, // Inst #1054 = MVE_VCVTs32f32_fix + { 6, OperandInfo248 }, // Inst #1055 = MVE_VCVTs32f32a + { 6, OperandInfo248 }, // Inst #1056 = MVE_VCVTs32f32m + { 6, OperandInfo248 }, // Inst #1057 = MVE_VCVTs32f32n + { 6, OperandInfo248 }, // Inst #1058 = MVE_VCVTs32f32p + { 6, OperandInfo248 }, // Inst #1059 = MVE_VCVTs32f32z + { 7, OperandInfo264 }, // Inst #1060 = MVE_VCVTu16f16_fix + { 6, OperandInfo248 }, // Inst #1061 = MVE_VCVTu16f16a + { 6, OperandInfo248 }, // Inst #1062 = MVE_VCVTu16f16m + { 6, OperandInfo248 }, // Inst #1063 = MVE_VCVTu16f16n + { 6, OperandInfo248 }, // Inst #1064 = MVE_VCVTu16f16p + { 6, OperandInfo248 }, // Inst #1065 = MVE_VCVTu16f16z + { 7, OperandInfo264 }, // Inst #1066 = MVE_VCVTu32f32_fix + { 6, OperandInfo248 }, // Inst #1067 = MVE_VCVTu32f32a + { 6, OperandInfo248 }, // Inst #1068 = MVE_VCVTu32f32m + { 6, OperandInfo248 }, // Inst #1069 = MVE_VCVTu32f32n + { 6, OperandInfo248 }, // Inst #1070 = MVE_VCVTu32f32p + { 6, OperandInfo248 }, // Inst #1071 = MVE_VCVTu32f32z + { 8, OperandInfo265 }, // Inst #1072 = MVE_VDDUPu16 + { 8, OperandInfo265 }, // Inst #1073 = MVE_VDDUPu32 + { 8, OperandInfo265 }, // Inst #1074 = MVE_VDDUPu8 + { 6, OperandInfo266 }, // Inst #1075 = MVE_VDUP16 + { 6, OperandInfo266 }, // Inst #1076 = MVE_VDUP32 + { 6, OperandInfo266 }, // Inst #1077 = MVE_VDUP8 + { 9, OperandInfo267 }, // Inst #1078 = MVE_VDWDUPu16 + { 9, OperandInfo267 }, // Inst #1079 = MVE_VDWDUPu32 + { 9, OperandInfo267 }, // Inst #1080 = MVE_VDWDUPu8 + { 7, OperandInfo247 }, // Inst #1081 = MVE_VEOR + { 7, OperandInfo268 }, // Inst #1082 = MVE_VFMA_qr_Sf16 + { 7, OperandInfo268 }, // Inst #1083 = MVE_VFMA_qr_Sf32 + { 7, OperandInfo268 }, // Inst #1084 = MVE_VFMA_qr_f16 + { 7, OperandInfo268 }, // Inst #1085 = MVE_VFMA_qr_f32 + { 7, OperandInfo269 }, // Inst #1086 = MVE_VFMAf16 + { 7, OperandInfo269 }, // Inst #1087 = MVE_VFMAf32 + { 7, OperandInfo269 }, // Inst #1088 = MVE_VFMSf16 + { 7, OperandInfo269 }, // Inst #1089 = MVE_VFMSf32 + { 7, OperandInfo255 }, // Inst #1090 = MVE_VHADD_qr_s16 + { 7, OperandInfo255 }, // Inst #1091 = MVE_VHADD_qr_s32 + { 7, OperandInfo255 }, // Inst #1092 = MVE_VHADD_qr_s8 + { 7, OperandInfo255 }, // Inst #1093 = MVE_VHADD_qr_u16 + { 7, OperandInfo255 }, // Inst #1094 = MVE_VHADD_qr_u32 + { 7, OperandInfo255 }, // Inst #1095 = MVE_VHADD_qr_u8 + { 7, OperandInfo247 }, // Inst #1096 = MVE_VHADDs16 + { 7, OperandInfo247 }, // Inst #1097 = MVE_VHADDs32 + { 7, OperandInfo247 }, // Inst #1098 = MVE_VHADDs8 + { 7, OperandInfo247 }, // Inst #1099 = MVE_VHADDu16 + { 7, OperandInfo247 }, // Inst #1100 = MVE_VHADDu32 + { 7, OperandInfo247 }, // Inst #1101 = MVE_VHADDu8 + { 8, OperandInfo257 }, // Inst #1102 = MVE_VHCADDs16 + { 8, OperandInfo258 }, // Inst #1103 = MVE_VHCADDs32 + { 8, OperandInfo257 }, // Inst #1104 = MVE_VHCADDs8 + { 7, OperandInfo255 }, // Inst #1105 = MVE_VHSUB_qr_s16 + { 7, OperandInfo255 }, // Inst #1106 = MVE_VHSUB_qr_s32 + { 7, OperandInfo255 }, // Inst #1107 = MVE_VHSUB_qr_s8 + { 7, OperandInfo255 }, // Inst #1108 = MVE_VHSUB_qr_u16 + { 7, OperandInfo255 }, // Inst #1109 = MVE_VHSUB_qr_u32 + { 7, OperandInfo255 }, // Inst #1110 = MVE_VHSUB_qr_u8 + { 7, OperandInfo247 }, // Inst #1111 = MVE_VHSUBs16 + { 7, OperandInfo247 }, // Inst #1112 = MVE_VHSUBs32 + { 7, OperandInfo247 }, // Inst #1113 = MVE_VHSUBs8 + { 7, OperandInfo247 }, // Inst #1114 = MVE_VHSUBu16 + { 7, OperandInfo247 }, // Inst #1115 = MVE_VHSUBu32 + { 7, OperandInfo247 }, // Inst #1116 = MVE_VHSUBu8 + { 8, OperandInfo265 }, // Inst #1117 = MVE_VIDUPu16 + { 8, OperandInfo265 }, // Inst #1118 = MVE_VIDUPu32 + { 8, OperandInfo265 }, // Inst #1119 = MVE_VIDUPu8 + { 9, OperandInfo267 }, // Inst #1120 = MVE_VIWDUPu16 + { 9, OperandInfo267 }, // Inst #1121 = MVE_VIWDUPu32 + { 9, OperandInfo267 }, // Inst #1122 = MVE_VIWDUPu8 + { 3, OperandInfo270 }, // Inst #1123 = MVE_VLD20_16 + { 4, OperandInfo271 }, // Inst #1124 = MVE_VLD20_16_wb + { 3, OperandInfo270 }, // Inst #1125 = MVE_VLD20_32 + { 4, OperandInfo271 }, // Inst #1126 = MVE_VLD20_32_wb + { 3, OperandInfo270 }, // Inst #1127 = MVE_VLD20_8 + { 4, OperandInfo271 }, // Inst #1128 = MVE_VLD20_8_wb + { 3, OperandInfo270 }, // Inst #1129 = MVE_VLD21_16 + { 4, OperandInfo271 }, // Inst #1130 = MVE_VLD21_16_wb + { 3, OperandInfo270 }, // Inst #1131 = MVE_VLD21_32 + { 4, OperandInfo271 }, // Inst #1132 = MVE_VLD21_32_wb + { 3, OperandInfo270 }, // Inst #1133 = MVE_VLD21_8 + { 4, OperandInfo271 }, // Inst #1134 = MVE_VLD21_8_wb + { 3, OperandInfo272 }, // Inst #1135 = MVE_VLD40_16 + { 4, OperandInfo273 }, // Inst #1136 = MVE_VLD40_16_wb + { 3, OperandInfo272 }, // Inst #1137 = MVE_VLD40_32 + { 4, OperandInfo273 }, // Inst #1138 = MVE_VLD40_32_wb + { 3, OperandInfo272 }, // Inst #1139 = MVE_VLD40_8 + { 4, OperandInfo273 }, // Inst #1140 = MVE_VLD40_8_wb + { 3, OperandInfo272 }, // Inst #1141 = MVE_VLD41_16 + { 4, OperandInfo273 }, // Inst #1142 = MVE_VLD41_16_wb + { 3, OperandInfo272 }, // Inst #1143 = MVE_VLD41_32 + { 4, OperandInfo273 }, // Inst #1144 = MVE_VLD41_32_wb + { 3, OperandInfo272 }, // Inst #1145 = MVE_VLD41_8 + { 4, OperandInfo273 }, // Inst #1146 = MVE_VLD41_8_wb + { 3, OperandInfo272 }, // Inst #1147 = MVE_VLD42_16 + { 4, OperandInfo273 }, // Inst #1148 = MVE_VLD42_16_wb + { 3, OperandInfo272 }, // Inst #1149 = MVE_VLD42_32 + { 4, OperandInfo273 }, // Inst #1150 = MVE_VLD42_32_wb + { 3, OperandInfo272 }, // Inst #1151 = MVE_VLD42_8 + { 4, OperandInfo273 }, // Inst #1152 = MVE_VLD42_8_wb + { 3, OperandInfo272 }, // Inst #1153 = MVE_VLD43_16 + { 4, OperandInfo273 }, // Inst #1154 = MVE_VLD43_16_wb + { 3, OperandInfo272 }, // Inst #1155 = MVE_VLD43_32 + { 4, OperandInfo273 }, // Inst #1156 = MVE_VLD43_32_wb + { 3, OperandInfo272 }, // Inst #1157 = MVE_VLD43_8 + { 4, OperandInfo273 }, // Inst #1158 = MVE_VLD43_8_wb + { 6, OperandInfo274 }, // Inst #1159 = MVE_VLDRBS16 + { 7, OperandInfo275 }, // Inst #1160 = MVE_VLDRBS16_post + { 7, OperandInfo275 }, // Inst #1161 = MVE_VLDRBS16_pre + { 6, OperandInfo276 }, // Inst #1162 = MVE_VLDRBS16_rq + { 6, OperandInfo274 }, // Inst #1163 = MVE_VLDRBS32 + { 7, OperandInfo275 }, // Inst #1164 = MVE_VLDRBS32_post + { 7, OperandInfo275 }, // Inst #1165 = MVE_VLDRBS32_pre + { 6, OperandInfo276 }, // Inst #1166 = MVE_VLDRBS32_rq + { 6, OperandInfo274 }, // Inst #1167 = MVE_VLDRBU16 + { 7, OperandInfo275 }, // Inst #1168 = MVE_VLDRBU16_post + { 7, OperandInfo275 }, // Inst #1169 = MVE_VLDRBU16_pre + { 6, OperandInfo276 }, // Inst #1170 = MVE_VLDRBU16_rq + { 6, OperandInfo274 }, // Inst #1171 = MVE_VLDRBU32 + { 7, OperandInfo275 }, // Inst #1172 = MVE_VLDRBU32_post + { 7, OperandInfo275 }, // Inst #1173 = MVE_VLDRBU32_pre + { 6, OperandInfo276 }, // Inst #1174 = MVE_VLDRBU32_rq + { 6, OperandInfo277 }, // Inst #1175 = MVE_VLDRBU8 + { 7, OperandInfo278 }, // Inst #1176 = MVE_VLDRBU8_post + { 7, OperandInfo278 }, // Inst #1177 = MVE_VLDRBU8_pre + { 6, OperandInfo276 }, // Inst #1178 = MVE_VLDRBU8_rq + { 6, OperandInfo279 }, // Inst #1179 = MVE_VLDRDU64_qi + { 7, OperandInfo280 }, // Inst #1180 = MVE_VLDRDU64_qi_pre + { 6, OperandInfo276 }, // Inst #1181 = MVE_VLDRDU64_rq + { 6, OperandInfo276 }, // Inst #1182 = MVE_VLDRDU64_rq_u + { 6, OperandInfo274 }, // Inst #1183 = MVE_VLDRHS32 + { 7, OperandInfo275 }, // Inst #1184 = MVE_VLDRHS32_post + { 7, OperandInfo275 }, // Inst #1185 = MVE_VLDRHS32_pre + { 6, OperandInfo276 }, // Inst #1186 = MVE_VLDRHS32_rq + { 6, OperandInfo276 }, // Inst #1187 = MVE_VLDRHS32_rq_u + { 6, OperandInfo277 }, // Inst #1188 = MVE_VLDRHU16 + { 7, OperandInfo278 }, // Inst #1189 = MVE_VLDRHU16_post + { 7, OperandInfo278 }, // Inst #1190 = MVE_VLDRHU16_pre + { 6, OperandInfo276 }, // Inst #1191 = MVE_VLDRHU16_rq + { 6, OperandInfo276 }, // Inst #1192 = MVE_VLDRHU16_rq_u + { 6, OperandInfo274 }, // Inst #1193 = MVE_VLDRHU32 + { 7, OperandInfo275 }, // Inst #1194 = MVE_VLDRHU32_post + { 7, OperandInfo275 }, // Inst #1195 = MVE_VLDRHU32_pre + { 6, OperandInfo276 }, // Inst #1196 = MVE_VLDRHU32_rq + { 6, OperandInfo276 }, // Inst #1197 = MVE_VLDRHU32_rq_u + { 6, OperandInfo277 }, // Inst #1198 = MVE_VLDRWU32 + { 7, OperandInfo278 }, // Inst #1199 = MVE_VLDRWU32_post + { 7, OperandInfo278 }, // Inst #1200 = MVE_VLDRWU32_pre + { 6, OperandInfo279 }, // Inst #1201 = MVE_VLDRWU32_qi + { 7, OperandInfo280 }, // Inst #1202 = MVE_VLDRWU32_qi_pre + { 6, OperandInfo276 }, // Inst #1203 = MVE_VLDRWU32_rq + { 6, OperandInfo276 }, // Inst #1204 = MVE_VLDRWU32_rq_u + { 6, OperandInfo281 }, // Inst #1205 = MVE_VMAXAVs16 + { 6, OperandInfo281 }, // Inst #1206 = MVE_VMAXAVs32 + { 6, OperandInfo281 }, // Inst #1207 = MVE_VMAXAVs8 + { 6, OperandInfo263 }, // Inst #1208 = MVE_VMAXAs16 + { 6, OperandInfo263 }, // Inst #1209 = MVE_VMAXAs32 + { 6, OperandInfo263 }, // Inst #1210 = MVE_VMAXAs8 + { 6, OperandInfo281 }, // Inst #1211 = MVE_VMAXNMAVf16 + { 6, OperandInfo281 }, // Inst #1212 = MVE_VMAXNMAVf32 + { 6, OperandInfo263 }, // Inst #1213 = MVE_VMAXNMAf16 + { 6, OperandInfo263 }, // Inst #1214 = MVE_VMAXNMAf32 + { 6, OperandInfo281 }, // Inst #1215 = MVE_VMAXNMVf16 + { 6, OperandInfo281 }, // Inst #1216 = MVE_VMAXNMVf32 + { 7, OperandInfo247 }, // Inst #1217 = MVE_VMAXNMf16 + { 7, OperandInfo247 }, // Inst #1218 = MVE_VMAXNMf32 + { 6, OperandInfo281 }, // Inst #1219 = MVE_VMAXVs16 + { 6, OperandInfo281 }, // Inst #1220 = MVE_VMAXVs32 + { 6, OperandInfo281 }, // Inst #1221 = MVE_VMAXVs8 + { 6, OperandInfo281 }, // Inst #1222 = MVE_VMAXVu16 + { 6, OperandInfo281 }, // Inst #1223 = MVE_VMAXVu32 + { 6, OperandInfo281 }, // Inst #1224 = MVE_VMAXVu8 + { 7, OperandInfo247 }, // Inst #1225 = MVE_VMAXs16 + { 7, OperandInfo247 }, // Inst #1226 = MVE_VMAXs32 + { 7, OperandInfo247 }, // Inst #1227 = MVE_VMAXs8 + { 7, OperandInfo247 }, // Inst #1228 = MVE_VMAXu16 + { 7, OperandInfo247 }, // Inst #1229 = MVE_VMAXu32 + { 7, OperandInfo247 }, // Inst #1230 = MVE_VMAXu8 + { 6, OperandInfo281 }, // Inst #1231 = MVE_VMINAVs16 + { 6, OperandInfo281 }, // Inst #1232 = MVE_VMINAVs32 + { 6, OperandInfo281 }, // Inst #1233 = MVE_VMINAVs8 + { 6, OperandInfo263 }, // Inst #1234 = MVE_VMINAs16 + { 6, OperandInfo263 }, // Inst #1235 = MVE_VMINAs32 + { 6, OperandInfo263 }, // Inst #1236 = MVE_VMINAs8 + { 6, OperandInfo281 }, // Inst #1237 = MVE_VMINNMAVf16 + { 6, OperandInfo281 }, // Inst #1238 = MVE_VMINNMAVf32 + { 6, OperandInfo263 }, // Inst #1239 = MVE_VMINNMAf16 + { 6, OperandInfo263 }, // Inst #1240 = MVE_VMINNMAf32 + { 6, OperandInfo281 }, // Inst #1241 = MVE_VMINNMVf16 + { 6, OperandInfo281 }, // Inst #1242 = MVE_VMINNMVf32 + { 7, OperandInfo247 }, // Inst #1243 = MVE_VMINNMf16 + { 7, OperandInfo247 }, // Inst #1244 = MVE_VMINNMf32 + { 6, OperandInfo281 }, // Inst #1245 = MVE_VMINVs16 + { 6, OperandInfo281 }, // Inst #1246 = MVE_VMINVs32 + { 6, OperandInfo281 }, // Inst #1247 = MVE_VMINVs8 + { 6, OperandInfo281 }, // Inst #1248 = MVE_VMINVu16 + { 6, OperandInfo281 }, // Inst #1249 = MVE_VMINVu32 + { 6, OperandInfo281 }, // Inst #1250 = MVE_VMINVu8 + { 7, OperandInfo247 }, // Inst #1251 = MVE_VMINs16 + { 7, OperandInfo247 }, // Inst #1252 = MVE_VMINs32 + { 7, OperandInfo247 }, // Inst #1253 = MVE_VMINs8 + { 7, OperandInfo247 }, // Inst #1254 = MVE_VMINu16 + { 7, OperandInfo247 }, // Inst #1255 = MVE_VMINu32 + { 7, OperandInfo247 }, // Inst #1256 = MVE_VMINu8 + { 7, OperandInfo282 }, // Inst #1257 = MVE_VMLADAVas16 + { 7, OperandInfo282 }, // Inst #1258 = MVE_VMLADAVas32 + { 7, OperandInfo282 }, // Inst #1259 = MVE_VMLADAVas8 + { 7, OperandInfo282 }, // Inst #1260 = MVE_VMLADAVau16 + { 7, OperandInfo282 }, // Inst #1261 = MVE_VMLADAVau32 + { 7, OperandInfo282 }, // Inst #1262 = MVE_VMLADAVau8 + { 7, OperandInfo282 }, // Inst #1263 = MVE_VMLADAVaxs16 + { 7, OperandInfo282 }, // Inst #1264 = MVE_VMLADAVaxs32 + { 7, OperandInfo282 }, // Inst #1265 = MVE_VMLADAVaxs8 + { 6, OperandInfo283 }, // Inst #1266 = MVE_VMLADAVs16 + { 6, OperandInfo283 }, // Inst #1267 = MVE_VMLADAVs32 + { 6, OperandInfo283 }, // Inst #1268 = MVE_VMLADAVs8 + { 6, OperandInfo283 }, // Inst #1269 = MVE_VMLADAVu16 + { 6, OperandInfo283 }, // Inst #1270 = MVE_VMLADAVu32 + { 6, OperandInfo283 }, // Inst #1271 = MVE_VMLADAVu8 + { 6, OperandInfo283 }, // Inst #1272 = MVE_VMLADAVxs16 + { 6, OperandInfo283 }, // Inst #1273 = MVE_VMLADAVxs32 + { 6, OperandInfo283 }, // Inst #1274 = MVE_VMLADAVxs8 + { 9, OperandInfo284 }, // Inst #1275 = MVE_VMLALDAVas16 + { 9, OperandInfo284 }, // Inst #1276 = MVE_VMLALDAVas32 + { 9, OperandInfo284 }, // Inst #1277 = MVE_VMLALDAVau16 + { 9, OperandInfo284 }, // Inst #1278 = MVE_VMLALDAVau32 + { 9, OperandInfo284 }, // Inst #1279 = MVE_VMLALDAVaxs16 + { 9, OperandInfo284 }, // Inst #1280 = MVE_VMLALDAVaxs32 + { 7, OperandInfo285 }, // Inst #1281 = MVE_VMLALDAVs16 + { 7, OperandInfo285 }, // Inst #1282 = MVE_VMLALDAVs32 + { 7, OperandInfo285 }, // Inst #1283 = MVE_VMLALDAVu16 + { 7, OperandInfo285 }, // Inst #1284 = MVE_VMLALDAVu32 + { 7, OperandInfo285 }, // Inst #1285 = MVE_VMLALDAVxs16 + { 7, OperandInfo285 }, // Inst #1286 = MVE_VMLALDAVxs32 + { 7, OperandInfo268 }, // Inst #1287 = MVE_VMLAS_qr_i16 + { 7, OperandInfo268 }, // Inst #1288 = MVE_VMLAS_qr_i32 + { 7, OperandInfo268 }, // Inst #1289 = MVE_VMLAS_qr_i8 + { 7, OperandInfo268 }, // Inst #1290 = MVE_VMLA_qr_i16 + { 7, OperandInfo268 }, // Inst #1291 = MVE_VMLA_qr_i32 + { 7, OperandInfo268 }, // Inst #1292 = MVE_VMLA_qr_i8 + { 7, OperandInfo282 }, // Inst #1293 = MVE_VMLSDAVas16 + { 7, OperandInfo282 }, // Inst #1294 = MVE_VMLSDAVas32 + { 7, OperandInfo282 }, // Inst #1295 = MVE_VMLSDAVas8 + { 7, OperandInfo282 }, // Inst #1296 = MVE_VMLSDAVaxs16 + { 7, OperandInfo282 }, // Inst #1297 = MVE_VMLSDAVaxs32 + { 7, OperandInfo282 }, // Inst #1298 = MVE_VMLSDAVaxs8 + { 6, OperandInfo283 }, // Inst #1299 = MVE_VMLSDAVs16 + { 6, OperandInfo283 }, // Inst #1300 = MVE_VMLSDAVs32 + { 6, OperandInfo283 }, // Inst #1301 = MVE_VMLSDAVs8 + { 6, OperandInfo283 }, // Inst #1302 = MVE_VMLSDAVxs16 + { 6, OperandInfo283 }, // Inst #1303 = MVE_VMLSDAVxs32 + { 6, OperandInfo283 }, // Inst #1304 = MVE_VMLSDAVxs8 + { 9, OperandInfo284 }, // Inst #1305 = MVE_VMLSLDAVas16 + { 9, OperandInfo284 }, // Inst #1306 = MVE_VMLSLDAVas32 + { 9, OperandInfo284 }, // Inst #1307 = MVE_VMLSLDAVaxs16 + { 9, OperandInfo284 }, // Inst #1308 = MVE_VMLSLDAVaxs32 + { 7, OperandInfo285 }, // Inst #1309 = MVE_VMLSLDAVs16 + { 7, OperandInfo285 }, // Inst #1310 = MVE_VMLSLDAVs32 + { 7, OperandInfo285 }, // Inst #1311 = MVE_VMLSLDAVxs16 + { 7, OperandInfo285 }, // Inst #1312 = MVE_VMLSLDAVxs32 + { 6, OperandInfo248 }, // Inst #1313 = MVE_VMOVLs16bh + { 6, OperandInfo248 }, // Inst #1314 = MVE_VMOVLs16th + { 6, OperandInfo248 }, // Inst #1315 = MVE_VMOVLs8bh + { 6, OperandInfo248 }, // Inst #1316 = MVE_VMOVLs8th + { 6, OperandInfo248 }, // Inst #1317 = MVE_VMOVLu16bh + { 6, OperandInfo248 }, // Inst #1318 = MVE_VMOVLu16th + { 6, OperandInfo248 }, // Inst #1319 = MVE_VMOVLu8bh + { 6, OperandInfo248 }, // Inst #1320 = MVE_VMOVLu8th + { 6, OperandInfo263 }, // Inst #1321 = MVE_VMOVNi16bh + { 6, OperandInfo263 }, // Inst #1322 = MVE_VMOVNi16th + { 6, OperandInfo263 }, // Inst #1323 = MVE_VMOVNi32bh + { 6, OperandInfo263 }, // Inst #1324 = MVE_VMOVNi32th + { 5, OperandInfo286 }, // Inst #1325 = MVE_VMOV_from_lane_32 + { 5, OperandInfo286 }, // Inst #1326 = MVE_VMOV_from_lane_s16 + { 5, OperandInfo286 }, // Inst #1327 = MVE_VMOV_from_lane_s8 + { 5, OperandInfo286 }, // Inst #1328 = MVE_VMOV_from_lane_u16 + { 5, OperandInfo286 }, // Inst #1329 = MVE_VMOV_from_lane_u8 + { 8, OperandInfo287 }, // Inst #1330 = MVE_VMOV_q_rr + { 7, OperandInfo288 }, // Inst #1331 = MVE_VMOV_rr_q + { 6, OperandInfo289 }, // Inst #1332 = MVE_VMOV_to_lane_16 + { 6, OperandInfo289 }, // Inst #1333 = MVE_VMOV_to_lane_32 + { 6, OperandInfo289 }, // Inst #1334 = MVE_VMOV_to_lane_8 + { 6, OperandInfo290 }, // Inst #1335 = MVE_VMOVimmf32 + { 6, OperandInfo290 }, // Inst #1336 = MVE_VMOVimmi16 + { 6, OperandInfo290 }, // Inst #1337 = MVE_VMOVimmi32 + { 6, OperandInfo290 }, // Inst #1338 = MVE_VMOVimmi64 + { 6, OperandInfo290 }, // Inst #1339 = MVE_VMOVimmi8 + { 7, OperandInfo247 }, // Inst #1340 = MVE_VMULHs16 + { 7, OperandInfo247 }, // Inst #1341 = MVE_VMULHs32 + { 7, OperandInfo247 }, // Inst #1342 = MVE_VMULHs8 + { 7, OperandInfo247 }, // Inst #1343 = MVE_VMULHu16 + { 7, OperandInfo247 }, // Inst #1344 = MVE_VMULHu32 + { 7, OperandInfo247 }, // Inst #1345 = MVE_VMULHu8 + { 7, OperandInfo247 }, // Inst #1346 = MVE_VMULLBp16 + { 7, OperandInfo247 }, // Inst #1347 = MVE_VMULLBp8 + { 7, OperandInfo247 }, // Inst #1348 = MVE_VMULLBs16 + { 7, OperandInfo291 }, // Inst #1349 = MVE_VMULLBs32 + { 7, OperandInfo247 }, // Inst #1350 = MVE_VMULLBs8 + { 7, OperandInfo247 }, // Inst #1351 = MVE_VMULLBu16 + { 7, OperandInfo291 }, // Inst #1352 = MVE_VMULLBu32 + { 7, OperandInfo247 }, // Inst #1353 = MVE_VMULLBu8 + { 7, OperandInfo247 }, // Inst #1354 = MVE_VMULLTp16 + { 7, OperandInfo247 }, // Inst #1355 = MVE_VMULLTp8 + { 7, OperandInfo247 }, // Inst #1356 = MVE_VMULLTs16 + { 7, OperandInfo291 }, // Inst #1357 = MVE_VMULLTs32 + { 7, OperandInfo247 }, // Inst #1358 = MVE_VMULLTs8 + { 7, OperandInfo247 }, // Inst #1359 = MVE_VMULLTu16 + { 7, OperandInfo291 }, // Inst #1360 = MVE_VMULLTu32 + { 7, OperandInfo247 }, // Inst #1361 = MVE_VMULLTu8 + { 7, OperandInfo255 }, // Inst #1362 = MVE_VMUL_qr_f16 + { 7, OperandInfo255 }, // Inst #1363 = MVE_VMUL_qr_f32 + { 7, OperandInfo255 }, // Inst #1364 = MVE_VMUL_qr_i16 + { 7, OperandInfo255 }, // Inst #1365 = MVE_VMUL_qr_i32 + { 7, OperandInfo255 }, // Inst #1366 = MVE_VMUL_qr_i8 + { 7, OperandInfo247 }, // Inst #1367 = MVE_VMULf16 + { 7, OperandInfo247 }, // Inst #1368 = MVE_VMULf32 + { 7, OperandInfo247 }, // Inst #1369 = MVE_VMULi16 + { 7, OperandInfo247 }, // Inst #1370 = MVE_VMULi32 + { 7, OperandInfo247 }, // Inst #1371 = MVE_VMULi8 + { 6, OperandInfo248 }, // Inst #1372 = MVE_VMVN + { 6, OperandInfo290 }, // Inst #1373 = MVE_VMVNimmi16 + { 6, OperandInfo290 }, // Inst #1374 = MVE_VMVNimmi32 + { 6, OperandInfo248 }, // Inst #1375 = MVE_VNEGf16 + { 6, OperandInfo248 }, // Inst #1376 = MVE_VNEGf32 + { 6, OperandInfo248 }, // Inst #1377 = MVE_VNEGs16 + { 6, OperandInfo248 }, // Inst #1378 = MVE_VNEGs32 + { 6, OperandInfo248 }, // Inst #1379 = MVE_VNEGs8 + { 7, OperandInfo247 }, // Inst #1380 = MVE_VORN + { 7, OperandInfo247 }, // Inst #1381 = MVE_VORR + { 6, OperandInfo256 }, // Inst #1382 = MVE_VORRimmi16 + { 6, OperandInfo256 }, // Inst #1383 = MVE_VORRimmi32 + { 5, OperandInfo292 }, // Inst #1384 = MVE_VPNOT + { 6, OperandInfo293 }, // Inst #1385 = MVE_VPSEL + { 1, OperandInfo2 }, // Inst #1386 = MVE_VPST + { 4, OperandInfo294 }, // Inst #1387 = MVE_VPTv16i8 + { 4, OperandInfo295 }, // Inst #1388 = MVE_VPTv16i8r + { 4, OperandInfo294 }, // Inst #1389 = MVE_VPTv16s8 + { 4, OperandInfo295 }, // Inst #1390 = MVE_VPTv16s8r + { 4, OperandInfo294 }, // Inst #1391 = MVE_VPTv16u8 + { 4, OperandInfo295 }, // Inst #1392 = MVE_VPTv16u8r + { 4, OperandInfo294 }, // Inst #1393 = MVE_VPTv4f32 + { 4, OperandInfo295 }, // Inst #1394 = MVE_VPTv4f32r + { 4, OperandInfo294 }, // Inst #1395 = MVE_VPTv4i32 + { 4, OperandInfo295 }, // Inst #1396 = MVE_VPTv4i32r + { 4, OperandInfo294 }, // Inst #1397 = MVE_VPTv4s32 + { 4, OperandInfo295 }, // Inst #1398 = MVE_VPTv4s32r + { 4, OperandInfo294 }, // Inst #1399 = MVE_VPTv4u32 + { 4, OperandInfo295 }, // Inst #1400 = MVE_VPTv4u32r + { 4, OperandInfo294 }, // Inst #1401 = MVE_VPTv8f16 + { 4, OperandInfo295 }, // Inst #1402 = MVE_VPTv8f16r + { 4, OperandInfo294 }, // Inst #1403 = MVE_VPTv8i16 + { 4, OperandInfo295 }, // Inst #1404 = MVE_VPTv8i16r + { 4, OperandInfo294 }, // Inst #1405 = MVE_VPTv8s16 + { 4, OperandInfo295 }, // Inst #1406 = MVE_VPTv8s16r + { 4, OperandInfo294 }, // Inst #1407 = MVE_VPTv8u16 + { 4, OperandInfo295 }, // Inst #1408 = MVE_VPTv8u16r + { 6, OperandInfo248 }, // Inst #1409 = MVE_VQABSs16 + { 6, OperandInfo248 }, // Inst #1410 = MVE_VQABSs32 + { 6, OperandInfo248 }, // Inst #1411 = MVE_VQABSs8 + { 7, OperandInfo255 }, // Inst #1412 = MVE_VQADD_qr_s16 + { 7, OperandInfo255 }, // Inst #1413 = MVE_VQADD_qr_s32 + { 7, OperandInfo255 }, // Inst #1414 = MVE_VQADD_qr_s8 + { 7, OperandInfo255 }, // Inst #1415 = MVE_VQADD_qr_u16 + { 7, OperandInfo255 }, // Inst #1416 = MVE_VQADD_qr_u32 + { 7, OperandInfo255 }, // Inst #1417 = MVE_VQADD_qr_u8 + { 7, OperandInfo247 }, // Inst #1418 = MVE_VQADDs16 + { 7, OperandInfo247 }, // Inst #1419 = MVE_VQADDs32 + { 7, OperandInfo247 }, // Inst #1420 = MVE_VQADDs8 + { 7, OperandInfo247 }, // Inst #1421 = MVE_VQADDu16 + { 7, OperandInfo247 }, // Inst #1422 = MVE_VQADDu32 + { 7, OperandInfo247 }, // Inst #1423 = MVE_VQADDu8 + { 7, OperandInfo269 }, // Inst #1424 = MVE_VQDMLADHXs16 + { 7, OperandInfo296 }, // Inst #1425 = MVE_VQDMLADHXs32 + { 7, OperandInfo269 }, // Inst #1426 = MVE_VQDMLADHXs8 + { 7, OperandInfo269 }, // Inst #1427 = MVE_VQDMLADHs16 + { 7, OperandInfo296 }, // Inst #1428 = MVE_VQDMLADHs32 + { 7, OperandInfo269 }, // Inst #1429 = MVE_VQDMLADHs8 + { 7, OperandInfo268 }, // Inst #1430 = MVE_VQDMLAH_qrs16 + { 7, OperandInfo268 }, // Inst #1431 = MVE_VQDMLAH_qrs32 + { 7, OperandInfo268 }, // Inst #1432 = MVE_VQDMLAH_qrs8 + { 7, OperandInfo268 }, // Inst #1433 = MVE_VQDMLASH_qrs16 + { 7, OperandInfo268 }, // Inst #1434 = MVE_VQDMLASH_qrs32 + { 7, OperandInfo268 }, // Inst #1435 = MVE_VQDMLASH_qrs8 + { 7, OperandInfo269 }, // Inst #1436 = MVE_VQDMLSDHXs16 + { 7, OperandInfo296 }, // Inst #1437 = MVE_VQDMLSDHXs32 + { 7, OperandInfo269 }, // Inst #1438 = MVE_VQDMLSDHXs8 + { 7, OperandInfo269 }, // Inst #1439 = MVE_VQDMLSDHs16 + { 7, OperandInfo296 }, // Inst #1440 = MVE_VQDMLSDHs32 + { 7, OperandInfo269 }, // Inst #1441 = MVE_VQDMLSDHs8 + { 7, OperandInfo255 }, // Inst #1442 = MVE_VQDMULH_qr_s16 + { 7, OperandInfo255 }, // Inst #1443 = MVE_VQDMULH_qr_s32 + { 7, OperandInfo255 }, // Inst #1444 = MVE_VQDMULH_qr_s8 + { 7, OperandInfo247 }, // Inst #1445 = MVE_VQDMULHi16 + { 7, OperandInfo247 }, // Inst #1446 = MVE_VQDMULHi32 + { 7, OperandInfo247 }, // Inst #1447 = MVE_VQDMULHi8 + { 7, OperandInfo255 }, // Inst #1448 = MVE_VQDMULL_qr_s16bh + { 7, OperandInfo255 }, // Inst #1449 = MVE_VQDMULL_qr_s16th + { 7, OperandInfo297 }, // Inst #1450 = MVE_VQDMULL_qr_s32bh + { 7, OperandInfo297 }, // Inst #1451 = MVE_VQDMULL_qr_s32th + { 7, OperandInfo247 }, // Inst #1452 = MVE_VQDMULLs16bh + { 7, OperandInfo247 }, // Inst #1453 = MVE_VQDMULLs16th + { 7, OperandInfo291 }, // Inst #1454 = MVE_VQDMULLs32bh + { 7, OperandInfo291 }, // Inst #1455 = MVE_VQDMULLs32th + { 6, OperandInfo263 }, // Inst #1456 = MVE_VQMOVNs16bh + { 6, OperandInfo263 }, // Inst #1457 = MVE_VQMOVNs16th + { 6, OperandInfo263 }, // Inst #1458 = MVE_VQMOVNs32bh + { 6, OperandInfo263 }, // Inst #1459 = MVE_VQMOVNs32th + { 6, OperandInfo263 }, // Inst #1460 = MVE_VQMOVNu16bh + { 6, OperandInfo263 }, // Inst #1461 = MVE_VQMOVNu16th + { 6, OperandInfo263 }, // Inst #1462 = MVE_VQMOVNu32bh + { 6, OperandInfo263 }, // Inst #1463 = MVE_VQMOVNu32th + { 6, OperandInfo263 }, // Inst #1464 = MVE_VQMOVUNs16bh + { 6, OperandInfo263 }, // Inst #1465 = MVE_VQMOVUNs16th + { 6, OperandInfo263 }, // Inst #1466 = MVE_VQMOVUNs32bh + { 6, OperandInfo263 }, // Inst #1467 = MVE_VQMOVUNs32th + { 6, OperandInfo248 }, // Inst #1468 = MVE_VQNEGs16 + { 6, OperandInfo248 }, // Inst #1469 = MVE_VQNEGs32 + { 6, OperandInfo248 }, // Inst #1470 = MVE_VQNEGs8 + { 7, OperandInfo269 }, // Inst #1471 = MVE_VQRDMLADHXs16 + { 7, OperandInfo296 }, // Inst #1472 = MVE_VQRDMLADHXs32 + { 7, OperandInfo269 }, // Inst #1473 = MVE_VQRDMLADHXs8 + { 7, OperandInfo269 }, // Inst #1474 = MVE_VQRDMLADHs16 + { 7, OperandInfo296 }, // Inst #1475 = MVE_VQRDMLADHs32 + { 7, OperandInfo269 }, // Inst #1476 = MVE_VQRDMLADHs8 + { 7, OperandInfo268 }, // Inst #1477 = MVE_VQRDMLAH_qrs16 + { 7, OperandInfo268 }, // Inst #1478 = MVE_VQRDMLAH_qrs32 + { 7, OperandInfo268 }, // Inst #1479 = MVE_VQRDMLAH_qrs8 + { 7, OperandInfo268 }, // Inst #1480 = MVE_VQRDMLASH_qrs16 + { 7, OperandInfo268 }, // Inst #1481 = MVE_VQRDMLASH_qrs32 + { 7, OperandInfo268 }, // Inst #1482 = MVE_VQRDMLASH_qrs8 + { 7, OperandInfo269 }, // Inst #1483 = MVE_VQRDMLSDHXs16 + { 7, OperandInfo296 }, // Inst #1484 = MVE_VQRDMLSDHXs32 + { 7, OperandInfo269 }, // Inst #1485 = MVE_VQRDMLSDHXs8 + { 7, OperandInfo269 }, // Inst #1486 = MVE_VQRDMLSDHs16 + { 7, OperandInfo296 }, // Inst #1487 = MVE_VQRDMLSDHs32 + { 7, OperandInfo269 }, // Inst #1488 = MVE_VQRDMLSDHs8 + { 7, OperandInfo255 }, // Inst #1489 = MVE_VQRDMULH_qr_s16 + { 7, OperandInfo255 }, // Inst #1490 = MVE_VQRDMULH_qr_s32 + { 7, OperandInfo255 }, // Inst #1491 = MVE_VQRDMULH_qr_s8 + { 7, OperandInfo247 }, // Inst #1492 = MVE_VQRDMULHi16 + { 7, OperandInfo247 }, // Inst #1493 = MVE_VQRDMULHi32 + { 7, OperandInfo247 }, // Inst #1494 = MVE_VQRDMULHi8 + { 7, OperandInfo247 }, // Inst #1495 = MVE_VQRSHL_by_vecs16 + { 7, OperandInfo247 }, // Inst #1496 = MVE_VQRSHL_by_vecs32 + { 7, OperandInfo247 }, // Inst #1497 = MVE_VQRSHL_by_vecs8 + { 7, OperandInfo247 }, // Inst #1498 = MVE_VQRSHL_by_vecu16 + { 7, OperandInfo247 }, // Inst #1499 = MVE_VQRSHL_by_vecu32 + { 7, OperandInfo247 }, // Inst #1500 = MVE_VQRSHL_by_vecu8 + { 6, OperandInfo298 }, // Inst #1501 = MVE_VQRSHL_qrs16 + { 6, OperandInfo298 }, // Inst #1502 = MVE_VQRSHL_qrs32 + { 6, OperandInfo298 }, // Inst #1503 = MVE_VQRSHL_qrs8 + { 6, OperandInfo298 }, // Inst #1504 = MVE_VQRSHL_qru16 + { 6, OperandInfo298 }, // Inst #1505 = MVE_VQRSHL_qru32 + { 6, OperandInfo298 }, // Inst #1506 = MVE_VQRSHL_qru8 + { 7, OperandInfo299 }, // Inst #1507 = MVE_VQRSHRNbhs16 + { 7, OperandInfo299 }, // Inst #1508 = MVE_VQRSHRNbhs32 + { 7, OperandInfo299 }, // Inst #1509 = MVE_VQRSHRNbhu16 + { 7, OperandInfo299 }, // Inst #1510 = MVE_VQRSHRNbhu32 + { 7, OperandInfo299 }, // Inst #1511 = MVE_VQRSHRNths16 + { 7, OperandInfo299 }, // Inst #1512 = MVE_VQRSHRNths32 + { 7, OperandInfo299 }, // Inst #1513 = MVE_VQRSHRNthu16 + { 7, OperandInfo299 }, // Inst #1514 = MVE_VQRSHRNthu32 + { 7, OperandInfo299 }, // Inst #1515 = MVE_VQRSHRUNs16bh + { 7, OperandInfo299 }, // Inst #1516 = MVE_VQRSHRUNs16th + { 7, OperandInfo299 }, // Inst #1517 = MVE_VQRSHRUNs32bh + { 7, OperandInfo299 }, // Inst #1518 = MVE_VQRSHRUNs32th + { 7, OperandInfo264 }, // Inst #1519 = MVE_VQSHLU_imms16 + { 7, OperandInfo264 }, // Inst #1520 = MVE_VQSHLU_imms32 + { 7, OperandInfo264 }, // Inst #1521 = MVE_VQSHLU_imms8 + { 7, OperandInfo247 }, // Inst #1522 = MVE_VQSHL_by_vecs16 + { 7, OperandInfo247 }, // Inst #1523 = MVE_VQSHL_by_vecs32 + { 7, OperandInfo247 }, // Inst #1524 = MVE_VQSHL_by_vecs8 + { 7, OperandInfo247 }, // Inst #1525 = MVE_VQSHL_by_vecu16 + { 7, OperandInfo247 }, // Inst #1526 = MVE_VQSHL_by_vecu32 + { 7, OperandInfo247 }, // Inst #1527 = MVE_VQSHL_by_vecu8 + { 6, OperandInfo298 }, // Inst #1528 = MVE_VQSHL_qrs16 + { 6, OperandInfo298 }, // Inst #1529 = MVE_VQSHL_qrs32 + { 6, OperandInfo298 }, // Inst #1530 = MVE_VQSHL_qrs8 + { 6, OperandInfo298 }, // Inst #1531 = MVE_VQSHL_qru16 + { 6, OperandInfo298 }, // Inst #1532 = MVE_VQSHL_qru32 + { 6, OperandInfo298 }, // Inst #1533 = MVE_VQSHL_qru8 + { 7, OperandInfo264 }, // Inst #1534 = MVE_VQSHLimms16 + { 7, OperandInfo264 }, // Inst #1535 = MVE_VQSHLimms32 + { 7, OperandInfo264 }, // Inst #1536 = MVE_VQSHLimms8 + { 7, OperandInfo264 }, // Inst #1537 = MVE_VQSHLimmu16 + { 7, OperandInfo264 }, // Inst #1538 = MVE_VQSHLimmu32 + { 7, OperandInfo264 }, // Inst #1539 = MVE_VQSHLimmu8 + { 7, OperandInfo299 }, // Inst #1540 = MVE_VQSHRNbhs16 + { 7, OperandInfo299 }, // Inst #1541 = MVE_VQSHRNbhs32 + { 7, OperandInfo299 }, // Inst #1542 = MVE_VQSHRNbhu16 + { 7, OperandInfo299 }, // Inst #1543 = MVE_VQSHRNbhu32 + { 7, OperandInfo299 }, // Inst #1544 = MVE_VQSHRNths16 + { 7, OperandInfo299 }, // Inst #1545 = MVE_VQSHRNths32 + { 7, OperandInfo299 }, // Inst #1546 = MVE_VQSHRNthu16 + { 7, OperandInfo299 }, // Inst #1547 = MVE_VQSHRNthu32 + { 7, OperandInfo299 }, // Inst #1548 = MVE_VQSHRUNs16bh + { 7, OperandInfo299 }, // Inst #1549 = MVE_VQSHRUNs16th + { 7, OperandInfo299 }, // Inst #1550 = MVE_VQSHRUNs32bh + { 7, OperandInfo299 }, // Inst #1551 = MVE_VQSHRUNs32th + { 7, OperandInfo255 }, // Inst #1552 = MVE_VQSUB_qr_s16 + { 7, OperandInfo255 }, // Inst #1553 = MVE_VQSUB_qr_s32 + { 7, OperandInfo255 }, // Inst #1554 = MVE_VQSUB_qr_s8 + { 7, OperandInfo255 }, // Inst #1555 = MVE_VQSUB_qr_u16 + { 7, OperandInfo255 }, // Inst #1556 = MVE_VQSUB_qr_u32 + { 7, OperandInfo255 }, // Inst #1557 = MVE_VQSUB_qr_u8 + { 7, OperandInfo247 }, // Inst #1558 = MVE_VQSUBs16 + { 7, OperandInfo247 }, // Inst #1559 = MVE_VQSUBs32 + { 7, OperandInfo247 }, // Inst #1560 = MVE_VQSUBs8 + { 7, OperandInfo247 }, // Inst #1561 = MVE_VQSUBu16 + { 7, OperandInfo247 }, // Inst #1562 = MVE_VQSUBu32 + { 7, OperandInfo247 }, // Inst #1563 = MVE_VQSUBu8 + { 6, OperandInfo248 }, // Inst #1564 = MVE_VREV16_8 + { 6, OperandInfo248 }, // Inst #1565 = MVE_VREV32_16 + { 6, OperandInfo248 }, // Inst #1566 = MVE_VREV32_8 + { 6, OperandInfo300 }, // Inst #1567 = MVE_VREV64_16 + { 6, OperandInfo300 }, // Inst #1568 = MVE_VREV64_32 + { 6, OperandInfo300 }, // Inst #1569 = MVE_VREV64_8 + { 7, OperandInfo247 }, // Inst #1570 = MVE_VRHADDs16 + { 7, OperandInfo247 }, // Inst #1571 = MVE_VRHADDs32 + { 7, OperandInfo247 }, // Inst #1572 = MVE_VRHADDs8 + { 7, OperandInfo247 }, // Inst #1573 = MVE_VRHADDu16 + { 7, OperandInfo247 }, // Inst #1574 = MVE_VRHADDu32 + { 7, OperandInfo247 }, // Inst #1575 = MVE_VRHADDu8 + { 6, OperandInfo248 }, // Inst #1576 = MVE_VRINTf16A + { 6, OperandInfo248 }, // Inst #1577 = MVE_VRINTf16M + { 6, OperandInfo248 }, // Inst #1578 = MVE_VRINTf16N + { 6, OperandInfo248 }, // Inst #1579 = MVE_VRINTf16P + { 6, OperandInfo248 }, // Inst #1580 = MVE_VRINTf16X + { 6, OperandInfo248 }, // Inst #1581 = MVE_VRINTf16Z + { 6, OperandInfo248 }, // Inst #1582 = MVE_VRINTf32A + { 6, OperandInfo248 }, // Inst #1583 = MVE_VRINTf32M + { 6, OperandInfo248 }, // Inst #1584 = MVE_VRINTf32N + { 6, OperandInfo248 }, // Inst #1585 = MVE_VRINTf32P + { 6, OperandInfo248 }, // Inst #1586 = MVE_VRINTf32X + { 6, OperandInfo248 }, // Inst #1587 = MVE_VRINTf32Z + { 9, OperandInfo284 }, // Inst #1588 = MVE_VRMLALDAVHas32 + { 9, OperandInfo284 }, // Inst #1589 = MVE_VRMLALDAVHau32 + { 9, OperandInfo284 }, // Inst #1590 = MVE_VRMLALDAVHaxs32 + { 7, OperandInfo285 }, // Inst #1591 = MVE_VRMLALDAVHs32 + { 7, OperandInfo285 }, // Inst #1592 = MVE_VRMLALDAVHu32 + { 7, OperandInfo285 }, // Inst #1593 = MVE_VRMLALDAVHxs32 + { 9, OperandInfo284 }, // Inst #1594 = MVE_VRMLSLDAVHas32 + { 9, OperandInfo284 }, // Inst #1595 = MVE_VRMLSLDAVHaxs32 + { 7, OperandInfo285 }, // Inst #1596 = MVE_VRMLSLDAVHs32 + { 7, OperandInfo285 }, // Inst #1597 = MVE_VRMLSLDAVHxs32 + { 7, OperandInfo247 }, // Inst #1598 = MVE_VRMULHs16 + { 7, OperandInfo247 }, // Inst #1599 = MVE_VRMULHs32 + { 7, OperandInfo247 }, // Inst #1600 = MVE_VRMULHs8 + { 7, OperandInfo247 }, // Inst #1601 = MVE_VRMULHu16 + { 7, OperandInfo247 }, // Inst #1602 = MVE_VRMULHu32 + { 7, OperandInfo247 }, // Inst #1603 = MVE_VRMULHu8 + { 7, OperandInfo247 }, // Inst #1604 = MVE_VRSHL_by_vecs16 + { 7, OperandInfo247 }, // Inst #1605 = MVE_VRSHL_by_vecs32 + { 7, OperandInfo247 }, // Inst #1606 = MVE_VRSHL_by_vecs8 + { 7, OperandInfo247 }, // Inst #1607 = MVE_VRSHL_by_vecu16 + { 7, OperandInfo247 }, // Inst #1608 = MVE_VRSHL_by_vecu32 + { 7, OperandInfo247 }, // Inst #1609 = MVE_VRSHL_by_vecu8 + { 6, OperandInfo298 }, // Inst #1610 = MVE_VRSHL_qrs16 + { 6, OperandInfo298 }, // Inst #1611 = MVE_VRSHL_qrs32 + { 6, OperandInfo298 }, // Inst #1612 = MVE_VRSHL_qrs8 + { 6, OperandInfo298 }, // Inst #1613 = MVE_VRSHL_qru16 + { 6, OperandInfo298 }, // Inst #1614 = MVE_VRSHL_qru32 + { 6, OperandInfo298 }, // Inst #1615 = MVE_VRSHL_qru8 + { 7, OperandInfo299 }, // Inst #1616 = MVE_VRSHRNi16bh + { 7, OperandInfo299 }, // Inst #1617 = MVE_VRSHRNi16th + { 7, OperandInfo299 }, // Inst #1618 = MVE_VRSHRNi32bh + { 7, OperandInfo299 }, // Inst #1619 = MVE_VRSHRNi32th + { 7, OperandInfo264 }, // Inst #1620 = MVE_VRSHR_imms16 + { 7, OperandInfo264 }, // Inst #1621 = MVE_VRSHR_imms32 + { 7, OperandInfo264 }, // Inst #1622 = MVE_VRSHR_imms8 + { 7, OperandInfo264 }, // Inst #1623 = MVE_VRSHR_immu16 + { 7, OperandInfo264 }, // Inst #1624 = MVE_VRSHR_immu32 + { 7, OperandInfo264 }, // Inst #1625 = MVE_VRSHR_immu8 + { 9, OperandInfo249 }, // Inst #1626 = MVE_VSBC + { 8, OperandInfo250 }, // Inst #1627 = MVE_VSBCI + { 8, OperandInfo301 }, // Inst #1628 = MVE_VSHLC + { 7, OperandInfo264 }, // Inst #1629 = MVE_VSHLL_imms16bh + { 7, OperandInfo264 }, // Inst #1630 = MVE_VSHLL_imms16th + { 7, OperandInfo264 }, // Inst #1631 = MVE_VSHLL_imms8bh + { 7, OperandInfo264 }, // Inst #1632 = MVE_VSHLL_imms8th + { 7, OperandInfo264 }, // Inst #1633 = MVE_VSHLL_immu16bh + { 7, OperandInfo264 }, // Inst #1634 = MVE_VSHLL_immu16th + { 7, OperandInfo264 }, // Inst #1635 = MVE_VSHLL_immu8bh + { 7, OperandInfo264 }, // Inst #1636 = MVE_VSHLL_immu8th + { 6, OperandInfo248 }, // Inst #1637 = MVE_VSHLL_lws16bh + { 6, OperandInfo248 }, // Inst #1638 = MVE_VSHLL_lws16th + { 6, OperandInfo248 }, // Inst #1639 = MVE_VSHLL_lws8bh + { 6, OperandInfo248 }, // Inst #1640 = MVE_VSHLL_lws8th + { 6, OperandInfo248 }, // Inst #1641 = MVE_VSHLL_lwu16bh + { 6, OperandInfo248 }, // Inst #1642 = MVE_VSHLL_lwu16th + { 6, OperandInfo248 }, // Inst #1643 = MVE_VSHLL_lwu8bh + { 6, OperandInfo248 }, // Inst #1644 = MVE_VSHLL_lwu8th + { 7, OperandInfo247 }, // Inst #1645 = MVE_VSHL_by_vecs16 + { 7, OperandInfo247 }, // Inst #1646 = MVE_VSHL_by_vecs32 + { 7, OperandInfo247 }, // Inst #1647 = MVE_VSHL_by_vecs8 + { 7, OperandInfo247 }, // Inst #1648 = MVE_VSHL_by_vecu16 + { 7, OperandInfo247 }, // Inst #1649 = MVE_VSHL_by_vecu32 + { 7, OperandInfo247 }, // Inst #1650 = MVE_VSHL_by_vecu8 + { 7, OperandInfo264 }, // Inst #1651 = MVE_VSHL_immi16 + { 7, OperandInfo264 }, // Inst #1652 = MVE_VSHL_immi32 + { 7, OperandInfo264 }, // Inst #1653 = MVE_VSHL_immi8 + { 6, OperandInfo298 }, // Inst #1654 = MVE_VSHL_qrs16 + { 6, OperandInfo298 }, // Inst #1655 = MVE_VSHL_qrs32 + { 6, OperandInfo298 }, // Inst #1656 = MVE_VSHL_qrs8 + { 6, OperandInfo298 }, // Inst #1657 = MVE_VSHL_qru16 + { 6, OperandInfo298 }, // Inst #1658 = MVE_VSHL_qru32 + { 6, OperandInfo298 }, // Inst #1659 = MVE_VSHL_qru8 + { 7, OperandInfo299 }, // Inst #1660 = MVE_VSHRNi16bh + { 7, OperandInfo299 }, // Inst #1661 = MVE_VSHRNi16th + { 7, OperandInfo299 }, // Inst #1662 = MVE_VSHRNi32bh + { 7, OperandInfo299 }, // Inst #1663 = MVE_VSHRNi32th + { 7, OperandInfo264 }, // Inst #1664 = MVE_VSHR_imms16 + { 7, OperandInfo264 }, // Inst #1665 = MVE_VSHR_imms32 + { 7, OperandInfo264 }, // Inst #1666 = MVE_VSHR_imms8 + { 7, OperandInfo264 }, // Inst #1667 = MVE_VSHR_immu16 + { 7, OperandInfo264 }, // Inst #1668 = MVE_VSHR_immu32 + { 7, OperandInfo264 }, // Inst #1669 = MVE_VSHR_immu8 + { 7, OperandInfo299 }, // Inst #1670 = MVE_VSLIimm16 + { 7, OperandInfo299 }, // Inst #1671 = MVE_VSLIimm32 + { 7, OperandInfo299 }, // Inst #1672 = MVE_VSLIimm8 + { 7, OperandInfo299 }, // Inst #1673 = MVE_VSRIimm16 + { 7, OperandInfo299 }, // Inst #1674 = MVE_VSRIimm32 + { 7, OperandInfo299 }, // Inst #1675 = MVE_VSRIimm8 + { 2, OperandInfo302 }, // Inst #1676 = MVE_VST20_16 + { 3, OperandInfo303 }, // Inst #1677 = MVE_VST20_16_wb + { 2, OperandInfo302 }, // Inst #1678 = MVE_VST20_32 + { 3, OperandInfo303 }, // Inst #1679 = MVE_VST20_32_wb + { 2, OperandInfo302 }, // Inst #1680 = MVE_VST20_8 + { 3, OperandInfo303 }, // Inst #1681 = MVE_VST20_8_wb + { 2, OperandInfo302 }, // Inst #1682 = MVE_VST21_16 + { 3, OperandInfo303 }, // Inst #1683 = MVE_VST21_16_wb + { 2, OperandInfo302 }, // Inst #1684 = MVE_VST21_32 + { 3, OperandInfo303 }, // Inst #1685 = MVE_VST21_32_wb + { 2, OperandInfo302 }, // Inst #1686 = MVE_VST21_8 + { 3, OperandInfo303 }, // Inst #1687 = MVE_VST21_8_wb + { 2, OperandInfo304 }, // Inst #1688 = MVE_VST40_16 + { 3, OperandInfo305 }, // Inst #1689 = MVE_VST40_16_wb + { 2, OperandInfo304 }, // Inst #1690 = MVE_VST40_32 + { 3, OperandInfo305 }, // Inst #1691 = MVE_VST40_32_wb + { 2, OperandInfo304 }, // Inst #1692 = MVE_VST40_8 + { 3, OperandInfo305 }, // Inst #1693 = MVE_VST40_8_wb + { 2, OperandInfo304 }, // Inst #1694 = MVE_VST41_16 + { 3, OperandInfo305 }, // Inst #1695 = MVE_VST41_16_wb + { 2, OperandInfo304 }, // Inst #1696 = MVE_VST41_32 + { 3, OperandInfo305 }, // Inst #1697 = MVE_VST41_32_wb + { 2, OperandInfo304 }, // Inst #1698 = MVE_VST41_8 + { 3, OperandInfo305 }, // Inst #1699 = MVE_VST41_8_wb + { 2, OperandInfo304 }, // Inst #1700 = MVE_VST42_16 + { 3, OperandInfo305 }, // Inst #1701 = MVE_VST42_16_wb + { 2, OperandInfo304 }, // Inst #1702 = MVE_VST42_32 + { 3, OperandInfo305 }, // Inst #1703 = MVE_VST42_32_wb + { 2, OperandInfo304 }, // Inst #1704 = MVE_VST42_8 + { 3, OperandInfo305 }, // Inst #1705 = MVE_VST42_8_wb + { 2, OperandInfo304 }, // Inst #1706 = MVE_VST43_16 + { 3, OperandInfo305 }, // Inst #1707 = MVE_VST43_16_wb + { 2, OperandInfo304 }, // Inst #1708 = MVE_VST43_32 + { 3, OperandInfo305 }, // Inst #1709 = MVE_VST43_32_wb + { 2, OperandInfo304 }, // Inst #1710 = MVE_VST43_8 + { 3, OperandInfo305 }, // Inst #1711 = MVE_VST43_8_wb + { 6, OperandInfo274 }, // Inst #1712 = MVE_VSTRB16 + { 7, OperandInfo275 }, // Inst #1713 = MVE_VSTRB16_post + { 7, OperandInfo275 }, // Inst #1714 = MVE_VSTRB16_pre + { 6, OperandInfo306 }, // Inst #1715 = MVE_VSTRB16_rq + { 6, OperandInfo274 }, // Inst #1716 = MVE_VSTRB32 + { 7, OperandInfo275 }, // Inst #1717 = MVE_VSTRB32_post + { 7, OperandInfo275 }, // Inst #1718 = MVE_VSTRB32_pre + { 6, OperandInfo306 }, // Inst #1719 = MVE_VSTRB32_rq + { 6, OperandInfo306 }, // Inst #1720 = MVE_VSTRB8_rq + { 6, OperandInfo277 }, // Inst #1721 = MVE_VSTRBU8 + { 7, OperandInfo278 }, // Inst #1722 = MVE_VSTRBU8_post + { 7, OperandInfo278 }, // Inst #1723 = MVE_VSTRBU8_pre + { 6, OperandInfo307 }, // Inst #1724 = MVE_VSTRD64_qi + { 7, OperandInfo308 }, // Inst #1725 = MVE_VSTRD64_qi_pre + { 6, OperandInfo306 }, // Inst #1726 = MVE_VSTRD64_rq + { 6, OperandInfo306 }, // Inst #1727 = MVE_VSTRD64_rq_u + { 6, OperandInfo306 }, // Inst #1728 = MVE_VSTRH16_rq + { 6, OperandInfo306 }, // Inst #1729 = MVE_VSTRH16_rq_u + { 6, OperandInfo274 }, // Inst #1730 = MVE_VSTRH32 + { 7, OperandInfo275 }, // Inst #1731 = MVE_VSTRH32_post + { 7, OperandInfo275 }, // Inst #1732 = MVE_VSTRH32_pre + { 6, OperandInfo306 }, // Inst #1733 = MVE_VSTRH32_rq + { 6, OperandInfo306 }, // Inst #1734 = MVE_VSTRH32_rq_u + { 6, OperandInfo277 }, // Inst #1735 = MVE_VSTRHU16 + { 7, OperandInfo278 }, // Inst #1736 = MVE_VSTRHU16_post + { 7, OperandInfo278 }, // Inst #1737 = MVE_VSTRHU16_pre + { 6, OperandInfo307 }, // Inst #1738 = MVE_VSTRW32_qi + { 7, OperandInfo308 }, // Inst #1739 = MVE_VSTRW32_qi_pre + { 6, OperandInfo306 }, // Inst #1740 = MVE_VSTRW32_rq + { 6, OperandInfo306 }, // Inst #1741 = MVE_VSTRW32_rq_u + { 6, OperandInfo277 }, // Inst #1742 = MVE_VSTRWU32 + { 7, OperandInfo278 }, // Inst #1743 = MVE_VSTRWU32_post + { 7, OperandInfo278 }, // Inst #1744 = MVE_VSTRWU32_pre + { 7, OperandInfo255 }, // Inst #1745 = MVE_VSUB_qr_f16 + { 7, OperandInfo255 }, // Inst #1746 = MVE_VSUB_qr_f32 + { 7, OperandInfo255 }, // Inst #1747 = MVE_VSUB_qr_i16 + { 7, OperandInfo255 }, // Inst #1748 = MVE_VSUB_qr_i32 + { 7, OperandInfo255 }, // Inst #1749 = MVE_VSUB_qr_i8 + { 7, OperandInfo247 }, // Inst #1750 = MVE_VSUBf16 + { 7, OperandInfo247 }, // Inst #1751 = MVE_VSUBf32 + { 7, OperandInfo247 }, // Inst #1752 = MVE_VSUBi16 + { 7, OperandInfo247 }, // Inst #1753 = MVE_VSUBi32 + { 7, OperandInfo247 }, // Inst #1754 = MVE_VSUBi8 + { 3, OperandInfo129 }, // Inst #1755 = MVE_WLSTP_16 + { 3, OperandInfo129 }, // Inst #1756 = MVE_WLSTP_32 + { 3, OperandInfo129 }, // Inst #1757 = MVE_WLSTP_64 + { 3, OperandInfo129 }, // Inst #1758 = MVE_WLSTP_8 + { 5, OperandInfo231 }, // Inst #1759 = MVNi + { 5, OperandInfo88 }, // Inst #1760 = MVNr + { 6, OperandInfo233 }, // Inst #1761 = MVNsi + { 7, OperandInfo309 }, // Inst #1762 = MVNsr + { 3, OperandInfo310 }, // Inst #1763 = NEON_VMAXNMNDf + { 3, OperandInfo310 }, // Inst #1764 = NEON_VMAXNMNDh + { 3, OperandInfo311 }, // Inst #1765 = NEON_VMAXNMNQf + { 3, OperandInfo311 }, // Inst #1766 = NEON_VMAXNMNQh + { 3, OperandInfo310 }, // Inst #1767 = NEON_VMINNMNDf + { 3, OperandInfo310 }, // Inst #1768 = NEON_VMINNMNDh + { 3, OperandInfo311 }, // Inst #1769 = NEON_VMINNMNQf + { 3, OperandInfo311 }, // Inst #1770 = NEON_VMINNMNQh + { 6, OperandInfo51 }, // Inst #1771 = ORRri + { 6, OperandInfo153 }, // Inst #1772 = ORRrr + { 7, OperandInfo154 }, // Inst #1773 = ORRrsi + { 8, OperandInfo156 }, // Inst #1774 = ORRrsr + { 6, OperandInfo312 }, // Inst #1775 = PKHBT + { 6, OperandInfo312 }, // Inst #1776 = PKHTB + { 2, OperandInfo313 }, // Inst #1777 = PLDWi12 + { 3, OperandInfo314 }, // Inst #1778 = PLDWrs + { 2, OperandInfo313 }, // Inst #1779 = PLDi12 + { 3, OperandInfo314 }, // Inst #1780 = PLDrs + { 2, OperandInfo313 }, // Inst #1781 = PLIi12 + { 3, OperandInfo314 }, // Inst #1782 = PLIrs + { 5, OperandInfo315 }, // Inst #1783 = QADD + { 5, OperandInfo315 }, // Inst #1784 = QADD16 + { 5, OperandInfo315 }, // Inst #1785 = QADD8 + { 5, OperandInfo315 }, // Inst #1786 = QASX + { 5, OperandInfo315 }, // Inst #1787 = QDADD + { 5, OperandInfo315 }, // Inst #1788 = QDSUB + { 5, OperandInfo315 }, // Inst #1789 = QSAX + { 5, OperandInfo315 }, // Inst #1790 = QSUB + { 5, OperandInfo315 }, // Inst #1791 = QSUB16 + { 5, OperandInfo315 }, // Inst #1792 = QSUB8 + { 4, OperandInfo197 }, // Inst #1793 = RBIT + { 4, OperandInfo197 }, // Inst #1794 = REV + { 4, OperandInfo197 }, // Inst #1795 = REV16 + { 4, OperandInfo197 }, // Inst #1796 = REVSH + { 1, OperandInfo78 }, // Inst #1797 = RFEDA + { 2, OperandInfo316 }, // Inst #1798 = RFEDA_UPD + { 1, OperandInfo78 }, // Inst #1799 = RFEDB + { 2, OperandInfo316 }, // Inst #1800 = RFEDB_UPD + { 1, OperandInfo78 }, // Inst #1801 = RFEIA + { 2, OperandInfo316 }, // Inst #1802 = RFEIA_UPD + { 1, OperandInfo78 }, // Inst #1803 = RFEIB + { 2, OperandInfo316 }, // Inst #1804 = RFEIB_UPD + { 6, OperandInfo51 }, // Inst #1805 = RSBri + { 6, OperandInfo153 }, // Inst #1806 = RSBrr + { 7, OperandInfo154 }, // Inst #1807 = RSBrsi + { 8, OperandInfo156 }, // Inst #1808 = RSBrsr + { 6, OperandInfo51 }, // Inst #1809 = RSCri + { 6, OperandInfo153 }, // Inst #1810 = RSCrr + { 7, OperandInfo154 }, // Inst #1811 = RSCrsi + { 8, OperandInfo156 }, // Inst #1812 = RSCrsr + { 5, OperandInfo315 }, // Inst #1813 = SADD16 + { 5, OperandInfo315 }, // Inst #1814 = SADD8 + { 5, OperandInfo315 }, // Inst #1815 = SASX + { 0, 0 }, // Inst #1816 = SB + { 6, OperandInfo51 }, // Inst #1817 = SBCri + { 6, OperandInfo153 }, // Inst #1818 = SBCrr + { 7, OperandInfo154 }, // Inst #1819 = SBCrsi + { 8, OperandInfo155 }, // Inst #1820 = SBCrsr + { 6, OperandInfo317 }, // Inst #1821 = SBFX + { 5, OperandInfo47 }, // Inst #1822 = SDIV + { 5, OperandInfo47 }, // Inst #1823 = SEL + { 1, OperandInfo2 }, // Inst #1824 = SETEND + { 1, OperandInfo2 }, // Inst #1825 = SETPAN + { 4, OperandInfo162 }, // Inst #1826 = SHA1C + { 2, OperandInfo158 }, // Inst #1827 = SHA1H + { 4, OperandInfo162 }, // Inst #1828 = SHA1M + { 4, OperandInfo162 }, // Inst #1829 = SHA1P + { 4, OperandInfo162 }, // Inst #1830 = SHA1SU0 + { 3, OperandInfo157 }, // Inst #1831 = SHA1SU1 + { 4, OperandInfo162 }, // Inst #1832 = SHA256H + { 4, OperandInfo162 }, // Inst #1833 = SHA256H2 + { 3, OperandInfo157 }, // Inst #1834 = SHA256SU0 + { 4, OperandInfo162 }, // Inst #1835 = SHA256SU1 + { 5, OperandInfo315 }, // Inst #1836 = SHADD16 + { 5, OperandInfo315 }, // Inst #1837 = SHADD8 + { 5, OperandInfo315 }, // Inst #1838 = SHASX + { 5, OperandInfo315 }, // Inst #1839 = SHSAX + { 5, OperandInfo315 }, // Inst #1840 = SHSUB16 + { 5, OperandInfo315 }, // Inst #1841 = SHSUB8 + { 3, OperandInfo202 }, // Inst #1842 = SMC + { 6, OperandInfo318 }, // Inst #1843 = SMLABB + { 6, OperandInfo318 }, // Inst #1844 = SMLABT + { 6, OperandInfo318 }, // Inst #1845 = SMLAD + { 6, OperandInfo318 }, // Inst #1846 = SMLADX + { 9, OperandInfo319 }, // Inst #1847 = SMLAL + { 8, OperandInfo320 }, // Inst #1848 = SMLALBB + { 8, OperandInfo320 }, // Inst #1849 = SMLALBT + { 8, OperandInfo320 }, // Inst #1850 = SMLALD + { 8, OperandInfo320 }, // Inst #1851 = SMLALDX + { 8, OperandInfo320 }, // Inst #1852 = SMLALTB + { 8, OperandInfo320 }, // Inst #1853 = SMLALTT + { 6, OperandInfo318 }, // Inst #1854 = SMLATB + { 6, OperandInfo318 }, // Inst #1855 = SMLATT + { 6, OperandInfo318 }, // Inst #1856 = SMLAWB + { 6, OperandInfo318 }, // Inst #1857 = SMLAWT + { 6, OperandInfo318 }, // Inst #1858 = SMLSD + { 6, OperandInfo318 }, // Inst #1859 = SMLSDX + { 8, OperandInfo320 }, // Inst #1860 = SMLSLD + { 8, OperandInfo320 }, // Inst #1861 = SMLSLDX + { 6, OperandInfo229 }, // Inst #1862 = SMMLA + { 6, OperandInfo229 }, // Inst #1863 = SMMLAR + { 6, OperandInfo229 }, // Inst #1864 = SMMLS + { 6, OperandInfo229 }, // Inst #1865 = SMMLSR + { 5, OperandInfo47 }, // Inst #1866 = SMMUL + { 5, OperandInfo47 }, // Inst #1867 = SMMULR + { 5, OperandInfo315 }, // Inst #1868 = SMUAD + { 5, OperandInfo315 }, // Inst #1869 = SMUADX + { 5, OperandInfo47 }, // Inst #1870 = SMULBB + { 5, OperandInfo47 }, // Inst #1871 = SMULBT + { 7, OperandInfo321 }, // Inst #1872 = SMULL + { 5, OperandInfo47 }, // Inst #1873 = SMULTB + { 5, OperandInfo47 }, // Inst #1874 = SMULTT + { 5, OperandInfo47 }, // Inst #1875 = SMULWB + { 5, OperandInfo47 }, // Inst #1876 = SMULWT + { 5, OperandInfo315 }, // Inst #1877 = SMUSD + { 5, OperandInfo315 }, // Inst #1878 = SMUSDX + { 1, OperandInfo2 }, // Inst #1879 = SRSDA + { 1, OperandInfo2 }, // Inst #1880 = SRSDA_UPD + { 1, OperandInfo2 }, // Inst #1881 = SRSDB + { 1, OperandInfo2 }, // Inst #1882 = SRSDB_UPD + { 1, OperandInfo2 }, // Inst #1883 = SRSIA + { 1, OperandInfo2 }, // Inst #1884 = SRSIA_UPD + { 1, OperandInfo2 }, // Inst #1885 = SRSIB + { 1, OperandInfo2 }, // Inst #1886 = SRSIB_UPD + { 6, OperandInfo322 }, // Inst #1887 = SSAT + { 5, OperandInfo323 }, // Inst #1888 = SSAT16 + { 5, OperandInfo315 }, // Inst #1889 = SSAX + { 5, OperandInfo315 }, // Inst #1890 = SSUB16 + { 5, OperandInfo315 }, // Inst #1891 = SSUB8 + { 4, OperandInfo208 }, // Inst #1892 = STC2L_OFFSET + { 4, OperandInfo209 }, // Inst #1893 = STC2L_OPTION + { 4, OperandInfo208 }, // Inst #1894 = STC2L_POST + { 5, OperandInfo210 }, // Inst #1895 = STC2L_PRE + { 4, OperandInfo208 }, // Inst #1896 = STC2_OFFSET + { 4, OperandInfo209 }, // Inst #1897 = STC2_OPTION + { 4, OperandInfo208 }, // Inst #1898 = STC2_POST + { 5, OperandInfo210 }, // Inst #1899 = STC2_PRE + { 6, OperandInfo211 }, // Inst #1900 = STCL_OFFSET + { 6, OperandInfo212 }, // Inst #1901 = STCL_OPTION + { 6, OperandInfo211 }, // Inst #1902 = STCL_POST + { 7, OperandInfo213 }, // Inst #1903 = STCL_PRE + { 6, OperandInfo211 }, // Inst #1904 = STC_OFFSET + { 6, OperandInfo212 }, // Inst #1905 = STC_OPTION + { 6, OperandInfo211 }, // Inst #1906 = STC_POST + { 7, OperandInfo213 }, // Inst #1907 = STC_PRE + { 4, OperandInfo67 }, // Inst #1908 = STL + { 4, OperandInfo67 }, // Inst #1909 = STLB + { 5, OperandInfo324 }, // Inst #1910 = STLEX + { 5, OperandInfo324 }, // Inst #1911 = STLEXB + { 5, OperandInfo325 }, // Inst #1912 = STLEXD + { 5, OperandInfo324 }, // Inst #1913 = STLEXH + { 4, OperandInfo67 }, // Inst #1914 = STLH + { 4, OperandInfo206 }, // Inst #1915 = STMDA + { 5, OperandInfo66 }, // Inst #1916 = STMDA_UPD + { 4, OperandInfo206 }, // Inst #1917 = STMDB + { 5, OperandInfo66 }, // Inst #1918 = STMDB_UPD + { 4, OperandInfo206 }, // Inst #1919 = STMIA + { 5, OperandInfo66 }, // Inst #1920 = STMIA_UPD + { 4, OperandInfo206 }, // Inst #1921 = STMIB + { 5, OperandInfo66 }, // Inst #1922 = STMIB_UPD + { 7, OperandInfo326 }, // Inst #1923 = STRBT_POST_IMM + { 7, OperandInfo326 }, // Inst #1924 = STRBT_POST_REG + { 7, OperandInfo327 }, // Inst #1925 = STRB_POST_IMM + { 7, OperandInfo327 }, // Inst #1926 = STRB_POST_REG + { 6, OperandInfo328 }, // Inst #1927 = STRB_PRE_IMM + { 7, OperandInfo327 }, // Inst #1928 = STRB_PRE_REG + { 5, OperandInfo216 }, // Inst #1929 = STRBi12 + { 6, OperandInfo217 }, // Inst #1930 = STRBrs + { 7, OperandInfo218 }, // Inst #1931 = STRD + { 8, OperandInfo329 }, // Inst #1932 = STRD_POST + { 8, OperandInfo329 }, // Inst #1933 = STRD_PRE + { 5, OperandInfo324 }, // Inst #1934 = STREX + { 5, OperandInfo324 }, // Inst #1935 = STREXB + { 5, OperandInfo325 }, // Inst #1936 = STREXD + { 5, OperandInfo324 }, // Inst #1937 = STREXH + { 6, OperandInfo220 }, // Inst #1938 = STRH + { 6, OperandInfo330 }, // Inst #1939 = STRHTi + { 7, OperandInfo326 }, // Inst #1940 = STRHTr + { 7, OperandInfo331 }, // Inst #1941 = STRH_POST + { 7, OperandInfo331 }, // Inst #1942 = STRH_PRE + { 7, OperandInfo326 }, // Inst #1943 = STRT_POST_IMM + { 7, OperandInfo326 }, // Inst #1944 = STRT_POST_REG + { 7, OperandInfo327 }, // Inst #1945 = STR_POST_IMM + { 7, OperandInfo327 }, // Inst #1946 = STR_POST_REG + { 6, OperandInfo328 }, // Inst #1947 = STR_PRE_IMM + { 7, OperandInfo327 }, // Inst #1948 = STR_PRE_REG + { 5, OperandInfo87 }, // Inst #1949 = STRi12 + { 6, OperandInfo223 }, // Inst #1950 = STRrs + { 6, OperandInfo51 }, // Inst #1951 = SUBri + { 6, OperandInfo153 }, // Inst #1952 = SUBrr + { 7, OperandInfo154 }, // Inst #1953 = SUBrsi + { 8, OperandInfo156 }, // Inst #1954 = SUBrsr + { 3, OperandInfo202 }, // Inst #1955 = SVC + { 5, OperandInfo332 }, // Inst #1956 = SWP + { 5, OperandInfo332 }, // Inst #1957 = SWPB + { 6, OperandInfo333 }, // Inst #1958 = SXTAB + { 6, OperandInfo333 }, // Inst #1959 = SXTAB16 + { 6, OperandInfo333 }, // Inst #1960 = SXTAH + { 5, OperandInfo334 }, // Inst #1961 = SXTB + { 5, OperandInfo334 }, // Inst #1962 = SXTB16 + { 5, OperandInfo334 }, // Inst #1963 = SXTH + { 4, OperandInfo68 }, // Inst #1964 = TEQri + { 4, OperandInfo197 }, // Inst #1965 = TEQrr + { 5, OperandInfo198 }, // Inst #1966 = TEQrsi + { 6, OperandInfo199 }, // Inst #1967 = TEQrsr + { 0, 0 }, // Inst #1968 = TRAP + { 0, 0 }, // Inst #1969 = TRAPNaCl + { 1, OperandInfo2 }, // Inst #1970 = TSB + { 4, OperandInfo68 }, // Inst #1971 = TSTri + { 4, OperandInfo197 }, // Inst #1972 = TSTrr + { 5, OperandInfo198 }, // Inst #1973 = TSTrsi + { 6, OperandInfo199 }, // Inst #1974 = TSTrsr + { 5, OperandInfo315 }, // Inst #1975 = UADD16 + { 5, OperandInfo315 }, // Inst #1976 = UADD8 + { 5, OperandInfo315 }, // Inst #1977 = UASX + { 6, OperandInfo317 }, // Inst #1978 = UBFX + { 1, OperandInfo2 }, // Inst #1979 = UDF + { 5, OperandInfo47 }, // Inst #1980 = UDIV + { 5, OperandInfo315 }, // Inst #1981 = UHADD16 + { 5, OperandInfo315 }, // Inst #1982 = UHADD8 + { 5, OperandInfo315 }, // Inst #1983 = UHASX + { 5, OperandInfo315 }, // Inst #1984 = UHSAX + { 5, OperandInfo315 }, // Inst #1985 = UHSUB16 + { 5, OperandInfo315 }, // Inst #1986 = UHSUB8 + { 8, OperandInfo335 }, // Inst #1987 = UMAAL + { 9, OperandInfo319 }, // Inst #1988 = UMLAL + { 7, OperandInfo321 }, // Inst #1989 = UMULL + { 5, OperandInfo315 }, // Inst #1990 = UQADD16 + { 5, OperandInfo315 }, // Inst #1991 = UQADD8 + { 5, OperandInfo315 }, // Inst #1992 = UQASX + { 5, OperandInfo315 }, // Inst #1993 = UQSAX + { 5, OperandInfo315 }, // Inst #1994 = UQSUB16 + { 5, OperandInfo315 }, // Inst #1995 = UQSUB8 + { 5, OperandInfo47 }, // Inst #1996 = USAD8 + { 6, OperandInfo229 }, // Inst #1997 = USADA8 + { 6, OperandInfo322 }, // Inst #1998 = USAT + { 5, OperandInfo323 }, // Inst #1999 = USAT16 + { 5, OperandInfo315 }, // Inst #2000 = USAX + { 5, OperandInfo315 }, // Inst #2001 = USUB16 + { 5, OperandInfo315 }, // Inst #2002 = USUB8 + { 6, OperandInfo333 }, // Inst #2003 = UXTAB + { 6, OperandInfo333 }, // Inst #2004 = UXTAB16 + { 6, OperandInfo333 }, // Inst #2005 = UXTAH + { 5, OperandInfo334 }, // Inst #2006 = UXTB + { 5, OperandInfo334 }, // Inst #2007 = UXTB16 + { 5, OperandInfo334 }, // Inst #2008 = UXTH + { 6, OperandInfo336 }, // Inst #2009 = VABALsv2i64 + { 6, OperandInfo336 }, // Inst #2010 = VABALsv4i32 + { 6, OperandInfo336 }, // Inst #2011 = VABALsv8i16 + { 6, OperandInfo336 }, // Inst #2012 = VABALuv2i64 + { 6, OperandInfo336 }, // Inst #2013 = VABALuv4i32 + { 6, OperandInfo336 }, // Inst #2014 = VABALuv8i16 + { 6, OperandInfo337 }, // Inst #2015 = VABAsv16i8 + { 6, OperandInfo338 }, // Inst #2016 = VABAsv2i32 + { 6, OperandInfo338 }, // Inst #2017 = VABAsv4i16 + { 6, OperandInfo337 }, // Inst #2018 = VABAsv4i32 + { 6, OperandInfo337 }, // Inst #2019 = VABAsv8i16 + { 6, OperandInfo338 }, // Inst #2020 = VABAsv8i8 + { 6, OperandInfo337 }, // Inst #2021 = VABAuv16i8 + { 6, OperandInfo338 }, // Inst #2022 = VABAuv2i32 + { 6, OperandInfo338 }, // Inst #2023 = VABAuv4i16 + { 6, OperandInfo337 }, // Inst #2024 = VABAuv4i32 + { 6, OperandInfo337 }, // Inst #2025 = VABAuv8i16 + { 6, OperandInfo338 }, // Inst #2026 = VABAuv8i8 + { 5, OperandInfo339 }, // Inst #2027 = VABDLsv2i64 + { 5, OperandInfo339 }, // Inst #2028 = VABDLsv4i32 + { 5, OperandInfo339 }, // Inst #2029 = VABDLsv8i16 + { 5, OperandInfo339 }, // Inst #2030 = VABDLuv2i64 + { 5, OperandInfo339 }, // Inst #2031 = VABDLuv4i32 + { 5, OperandInfo339 }, // Inst #2032 = VABDLuv8i16 + { 5, OperandInfo340 }, // Inst #2033 = VABDfd + { 5, OperandInfo341 }, // Inst #2034 = VABDfq + { 5, OperandInfo340 }, // Inst #2035 = VABDhd + { 5, OperandInfo341 }, // Inst #2036 = VABDhq + { 5, OperandInfo341 }, // Inst #2037 = VABDsv16i8 + { 5, OperandInfo340 }, // Inst #2038 = VABDsv2i32 + { 5, OperandInfo340 }, // Inst #2039 = VABDsv4i16 + { 5, OperandInfo341 }, // Inst #2040 = VABDsv4i32 + { 5, OperandInfo341 }, // Inst #2041 = VABDsv8i16 + { 5, OperandInfo340 }, // Inst #2042 = VABDsv8i8 + { 5, OperandInfo341 }, // Inst #2043 = VABDuv16i8 + { 5, OperandInfo340 }, // Inst #2044 = VABDuv2i32 + { 5, OperandInfo340 }, // Inst #2045 = VABDuv4i16 + { 5, OperandInfo341 }, // Inst #2046 = VABDuv4i32 + { 5, OperandInfo341 }, // Inst #2047 = VABDuv8i16 + { 5, OperandInfo340 }, // Inst #2048 = VABDuv8i8 + { 4, OperandInfo342 }, // Inst #2049 = VABSD + { 4, OperandInfo343 }, // Inst #2050 = VABSH + { 4, OperandInfo344 }, // Inst #2051 = VABSS + { 4, OperandInfo342 }, // Inst #2052 = VABSfd + { 4, OperandInfo345 }, // Inst #2053 = VABSfq + { 4, OperandInfo342 }, // Inst #2054 = VABShd + { 4, OperandInfo345 }, // Inst #2055 = VABShq + { 4, OperandInfo345 }, // Inst #2056 = VABSv16i8 + { 4, OperandInfo342 }, // Inst #2057 = VABSv2i32 + { 4, OperandInfo342 }, // Inst #2058 = VABSv4i16 + { 4, OperandInfo345 }, // Inst #2059 = VABSv4i32 + { 4, OperandInfo345 }, // Inst #2060 = VABSv8i16 + { 4, OperandInfo342 }, // Inst #2061 = VABSv8i8 + { 5, OperandInfo340 }, // Inst #2062 = VACGEfd + { 5, OperandInfo341 }, // Inst #2063 = VACGEfq + { 5, OperandInfo340 }, // Inst #2064 = VACGEhd + { 5, OperandInfo341 }, // Inst #2065 = VACGEhq + { 5, OperandInfo340 }, // Inst #2066 = VACGTfd + { 5, OperandInfo341 }, // Inst #2067 = VACGTfq + { 5, OperandInfo340 }, // Inst #2068 = VACGThd + { 5, OperandInfo341 }, // Inst #2069 = VACGThq + { 5, OperandInfo340 }, // Inst #2070 = VADDD + { 5, OperandInfo346 }, // Inst #2071 = VADDH + { 5, OperandInfo347 }, // Inst #2072 = VADDHNv2i32 + { 5, OperandInfo347 }, // Inst #2073 = VADDHNv4i16 + { 5, OperandInfo347 }, // Inst #2074 = VADDHNv8i8 + { 5, OperandInfo339 }, // Inst #2075 = VADDLsv2i64 + { 5, OperandInfo339 }, // Inst #2076 = VADDLsv4i32 + { 5, OperandInfo339 }, // Inst #2077 = VADDLsv8i16 + { 5, OperandInfo339 }, // Inst #2078 = VADDLuv2i64 + { 5, OperandInfo339 }, // Inst #2079 = VADDLuv4i32 + { 5, OperandInfo339 }, // Inst #2080 = VADDLuv8i16 + { 5, OperandInfo348 }, // Inst #2081 = VADDS + { 5, OperandInfo349 }, // Inst #2082 = VADDWsv2i64 + { 5, OperandInfo349 }, // Inst #2083 = VADDWsv4i32 + { 5, OperandInfo349 }, // Inst #2084 = VADDWsv8i16 + { 5, OperandInfo349 }, // Inst #2085 = VADDWuv2i64 + { 5, OperandInfo349 }, // Inst #2086 = VADDWuv4i32 + { 5, OperandInfo349 }, // Inst #2087 = VADDWuv8i16 + { 5, OperandInfo340 }, // Inst #2088 = VADDfd + { 5, OperandInfo341 }, // Inst #2089 = VADDfq + { 5, OperandInfo340 }, // Inst #2090 = VADDhd + { 5, OperandInfo341 }, // Inst #2091 = VADDhq + { 5, OperandInfo341 }, // Inst #2092 = VADDv16i8 + { 5, OperandInfo340 }, // Inst #2093 = VADDv1i64 + { 5, OperandInfo340 }, // Inst #2094 = VADDv2i32 + { 5, OperandInfo341 }, // Inst #2095 = VADDv2i64 + { 5, OperandInfo340 }, // Inst #2096 = VADDv4i16 + { 5, OperandInfo341 }, // Inst #2097 = VADDv4i32 + { 5, OperandInfo341 }, // Inst #2098 = VADDv8i16 + { 5, OperandInfo340 }, // Inst #2099 = VADDv8i8 + { 5, OperandInfo340 }, // Inst #2100 = VANDd + { 5, OperandInfo341 }, // Inst #2101 = VANDq + { 4, OperandInfo162 }, // Inst #2102 = VBF16MALBQ + { 5, OperandInfo350 }, // Inst #2103 = VBF16MALBQI + { 4, OperandInfo162 }, // Inst #2104 = VBF16MALTQ + { 5, OperandInfo350 }, // Inst #2105 = VBF16MALTQI + { 5, OperandInfo340 }, // Inst #2106 = VBICd + { 5, OperandInfo351 }, // Inst #2107 = VBICiv2i32 + { 5, OperandInfo351 }, // Inst #2108 = VBICiv4i16 + { 5, OperandInfo352 }, // Inst #2109 = VBICiv4i32 + { 5, OperandInfo352 }, // Inst #2110 = VBICiv8i16 + { 5, OperandInfo341 }, // Inst #2111 = VBICq + { 6, OperandInfo338 }, // Inst #2112 = VBIFd + { 6, OperandInfo337 }, // Inst #2113 = VBIFq + { 6, OperandInfo338 }, // Inst #2114 = VBITd + { 6, OperandInfo337 }, // Inst #2115 = VBITq + { 6, OperandInfo338 }, // Inst #2116 = VBSLd + { 6, OperandInfo337 }, // Inst #2117 = VBSLq + { 6, OperandInfo353 }, // Inst #2118 = VBSPd + { 6, OperandInfo354 }, // Inst #2119 = VBSPq + { 4, OperandInfo355 }, // Inst #2120 = VCADDv2f32 + { 4, OperandInfo355 }, // Inst #2121 = VCADDv4f16 + { 4, OperandInfo356 }, // Inst #2122 = VCADDv4f32 + { 4, OperandInfo356 }, // Inst #2123 = VCADDv8f16 + { 5, OperandInfo340 }, // Inst #2124 = VCEQfd + { 5, OperandInfo341 }, // Inst #2125 = VCEQfq + { 5, OperandInfo340 }, // Inst #2126 = VCEQhd + { 5, OperandInfo341 }, // Inst #2127 = VCEQhq + { 5, OperandInfo341 }, // Inst #2128 = VCEQv16i8 + { 5, OperandInfo340 }, // Inst #2129 = VCEQv2i32 + { 5, OperandInfo340 }, // Inst #2130 = VCEQv4i16 + { 5, OperandInfo341 }, // Inst #2131 = VCEQv4i32 + { 5, OperandInfo341 }, // Inst #2132 = VCEQv8i16 + { 5, OperandInfo340 }, // Inst #2133 = VCEQv8i8 + { 4, OperandInfo345 }, // Inst #2134 = VCEQzv16i8 + { 4, OperandInfo342 }, // Inst #2135 = VCEQzv2f32 + { 4, OperandInfo342 }, // Inst #2136 = VCEQzv2i32 + { 4, OperandInfo342 }, // Inst #2137 = VCEQzv4f16 + { 4, OperandInfo345 }, // Inst #2138 = VCEQzv4f32 + { 4, OperandInfo342 }, // Inst #2139 = VCEQzv4i16 + { 4, OperandInfo345 }, // Inst #2140 = VCEQzv4i32 + { 4, OperandInfo345 }, // Inst #2141 = VCEQzv8f16 + { 4, OperandInfo345 }, // Inst #2142 = VCEQzv8i16 + { 4, OperandInfo342 }, // Inst #2143 = VCEQzv8i8 + { 5, OperandInfo340 }, // Inst #2144 = VCGEfd + { 5, OperandInfo341 }, // Inst #2145 = VCGEfq + { 5, OperandInfo340 }, // Inst #2146 = VCGEhd + { 5, OperandInfo341 }, // Inst #2147 = VCGEhq + { 5, OperandInfo341 }, // Inst #2148 = VCGEsv16i8 + { 5, OperandInfo340 }, // Inst #2149 = VCGEsv2i32 + { 5, OperandInfo340 }, // Inst #2150 = VCGEsv4i16 + { 5, OperandInfo341 }, // Inst #2151 = VCGEsv4i32 + { 5, OperandInfo341 }, // Inst #2152 = VCGEsv8i16 + { 5, OperandInfo340 }, // Inst #2153 = VCGEsv8i8 + { 5, OperandInfo341 }, // Inst #2154 = VCGEuv16i8 + { 5, OperandInfo340 }, // Inst #2155 = VCGEuv2i32 + { 5, OperandInfo340 }, // Inst #2156 = VCGEuv4i16 + { 5, OperandInfo341 }, // Inst #2157 = VCGEuv4i32 + { 5, OperandInfo341 }, // Inst #2158 = VCGEuv8i16 + { 5, OperandInfo340 }, // Inst #2159 = VCGEuv8i8 + { 4, OperandInfo345 }, // Inst #2160 = VCGEzv16i8 + { 4, OperandInfo342 }, // Inst #2161 = VCGEzv2f32 + { 4, OperandInfo342 }, // Inst #2162 = VCGEzv2i32 + { 4, OperandInfo342 }, // Inst #2163 = VCGEzv4f16 + { 4, OperandInfo345 }, // Inst #2164 = VCGEzv4f32 + { 4, OperandInfo342 }, // Inst #2165 = VCGEzv4i16 + { 4, OperandInfo345 }, // Inst #2166 = VCGEzv4i32 + { 4, OperandInfo345 }, // Inst #2167 = VCGEzv8f16 + { 4, OperandInfo345 }, // Inst #2168 = VCGEzv8i16 + { 4, OperandInfo342 }, // Inst #2169 = VCGEzv8i8 + { 5, OperandInfo340 }, // Inst #2170 = VCGTfd + { 5, OperandInfo341 }, // Inst #2171 = VCGTfq + { 5, OperandInfo340 }, // Inst #2172 = VCGThd + { 5, OperandInfo341 }, // Inst #2173 = VCGThq + { 5, OperandInfo341 }, // Inst #2174 = VCGTsv16i8 + { 5, OperandInfo340 }, // Inst #2175 = VCGTsv2i32 + { 5, OperandInfo340 }, // Inst #2176 = VCGTsv4i16 + { 5, OperandInfo341 }, // Inst #2177 = VCGTsv4i32 + { 5, OperandInfo341 }, // Inst #2178 = VCGTsv8i16 + { 5, OperandInfo340 }, // Inst #2179 = VCGTsv8i8 + { 5, OperandInfo341 }, // Inst #2180 = VCGTuv16i8 + { 5, OperandInfo340 }, // Inst #2181 = VCGTuv2i32 + { 5, OperandInfo340 }, // Inst #2182 = VCGTuv4i16 + { 5, OperandInfo341 }, // Inst #2183 = VCGTuv4i32 + { 5, OperandInfo341 }, // Inst #2184 = VCGTuv8i16 + { 5, OperandInfo340 }, // Inst #2185 = VCGTuv8i8 + { 4, OperandInfo345 }, // Inst #2186 = VCGTzv16i8 + { 4, OperandInfo342 }, // Inst #2187 = VCGTzv2f32 + { 4, OperandInfo342 }, // Inst #2188 = VCGTzv2i32 + { 4, OperandInfo342 }, // Inst #2189 = VCGTzv4f16 + { 4, OperandInfo345 }, // Inst #2190 = VCGTzv4f32 + { 4, OperandInfo342 }, // Inst #2191 = VCGTzv4i16 + { 4, OperandInfo345 }, // Inst #2192 = VCGTzv4i32 + { 4, OperandInfo345 }, // Inst #2193 = VCGTzv8f16 + { 4, OperandInfo345 }, // Inst #2194 = VCGTzv8i16 + { 4, OperandInfo342 }, // Inst #2195 = VCGTzv8i8 + { 4, OperandInfo345 }, // Inst #2196 = VCLEzv16i8 + { 4, OperandInfo342 }, // Inst #2197 = VCLEzv2f32 + { 4, OperandInfo342 }, // Inst #2198 = VCLEzv2i32 + { 4, OperandInfo342 }, // Inst #2199 = VCLEzv4f16 + { 4, OperandInfo345 }, // Inst #2200 = VCLEzv4f32 + { 4, OperandInfo342 }, // Inst #2201 = VCLEzv4i16 + { 4, OperandInfo345 }, // Inst #2202 = VCLEzv4i32 + { 4, OperandInfo345 }, // Inst #2203 = VCLEzv8f16 + { 4, OperandInfo345 }, // Inst #2204 = VCLEzv8i16 + { 4, OperandInfo342 }, // Inst #2205 = VCLEzv8i8 + { 4, OperandInfo345 }, // Inst #2206 = VCLSv16i8 + { 4, OperandInfo342 }, // Inst #2207 = VCLSv2i32 + { 4, OperandInfo342 }, // Inst #2208 = VCLSv4i16 + { 4, OperandInfo345 }, // Inst #2209 = VCLSv4i32 + { 4, OperandInfo345 }, // Inst #2210 = VCLSv8i16 + { 4, OperandInfo342 }, // Inst #2211 = VCLSv8i8 + { 4, OperandInfo345 }, // Inst #2212 = VCLTzv16i8 + { 4, OperandInfo342 }, // Inst #2213 = VCLTzv2f32 + { 4, OperandInfo342 }, // Inst #2214 = VCLTzv2i32 + { 4, OperandInfo342 }, // Inst #2215 = VCLTzv4f16 + { 4, OperandInfo345 }, // Inst #2216 = VCLTzv4f32 + { 4, OperandInfo342 }, // Inst #2217 = VCLTzv4i16 + { 4, OperandInfo345 }, // Inst #2218 = VCLTzv4i32 + { 4, OperandInfo345 }, // Inst #2219 = VCLTzv8f16 + { 4, OperandInfo345 }, // Inst #2220 = VCLTzv8i16 + { 4, OperandInfo342 }, // Inst #2221 = VCLTzv8i8 + { 4, OperandInfo345 }, // Inst #2222 = VCLZv16i8 + { 4, OperandInfo342 }, // Inst #2223 = VCLZv2i32 + { 4, OperandInfo342 }, // Inst #2224 = VCLZv4i16 + { 4, OperandInfo345 }, // Inst #2225 = VCLZv4i32 + { 4, OperandInfo345 }, // Inst #2226 = VCLZv8i16 + { 4, OperandInfo342 }, // Inst #2227 = VCLZv8i8 + { 5, OperandInfo357 }, // Inst #2228 = VCMLAv2f32 + { 6, OperandInfo358 }, // Inst #2229 = VCMLAv2f32_indexed + { 5, OperandInfo357 }, // Inst #2230 = VCMLAv4f16 + { 6, OperandInfo359 }, // Inst #2231 = VCMLAv4f16_indexed + { 5, OperandInfo360 }, // Inst #2232 = VCMLAv4f32 + { 6, OperandInfo361 }, // Inst #2233 = VCMLAv4f32_indexed + { 5, OperandInfo360 }, // Inst #2234 = VCMLAv8f16 + { 6, OperandInfo362 }, // Inst #2235 = VCMLAv8f16_indexed + { 4, OperandInfo342 }, // Inst #2236 = VCMPD + { 4, OperandInfo342 }, // Inst #2237 = VCMPED + { 4, OperandInfo343 }, // Inst #2238 = VCMPEH + { 4, OperandInfo344 }, // Inst #2239 = VCMPES + { 3, OperandInfo363 }, // Inst #2240 = VCMPEZD + { 3, OperandInfo364 }, // Inst #2241 = VCMPEZH + { 3, OperandInfo365 }, // Inst #2242 = VCMPEZS + { 4, OperandInfo343 }, // Inst #2243 = VCMPH + { 4, OperandInfo344 }, // Inst #2244 = VCMPS + { 3, OperandInfo363 }, // Inst #2245 = VCMPZD + { 3, OperandInfo364 }, // Inst #2246 = VCMPZH + { 3, OperandInfo365 }, // Inst #2247 = VCMPZS + { 4, OperandInfo342 }, // Inst #2248 = VCNTd + { 4, OperandInfo345 }, // Inst #2249 = VCNTq + { 2, OperandInfo366 }, // Inst #2250 = VCVTANSDf + { 2, OperandInfo366 }, // Inst #2251 = VCVTANSDh + { 2, OperandInfo158 }, // Inst #2252 = VCVTANSQf + { 2, OperandInfo158 }, // Inst #2253 = VCVTANSQh + { 2, OperandInfo366 }, // Inst #2254 = VCVTANUDf + { 2, OperandInfo366 }, // Inst #2255 = VCVTANUDh + { 2, OperandInfo158 }, // Inst #2256 = VCVTANUQf + { 2, OperandInfo158 }, // Inst #2257 = VCVTANUQh + { 2, OperandInfo367 }, // Inst #2258 = VCVTASD + { 2, OperandInfo368 }, // Inst #2259 = VCVTASH + { 2, OperandInfo369 }, // Inst #2260 = VCVTASS + { 2, OperandInfo367 }, // Inst #2261 = VCVTAUD + { 2, OperandInfo368 }, // Inst #2262 = VCVTAUH + { 2, OperandInfo369 }, // Inst #2263 = VCVTAUS + { 5, OperandInfo370 }, // Inst #2264 = VCVTBDH + { 4, OperandInfo371 }, // Inst #2265 = VCVTBHD + { 4, OperandInfo344 }, // Inst #2266 = VCVTBHS + { 5, OperandInfo105 }, // Inst #2267 = VCVTBSH + { 4, OperandInfo371 }, // Inst #2268 = VCVTDS + { 2, OperandInfo366 }, // Inst #2269 = VCVTMNSDf + { 2, OperandInfo366 }, // Inst #2270 = VCVTMNSDh + { 2, OperandInfo158 }, // Inst #2271 = VCVTMNSQf + { 2, OperandInfo158 }, // Inst #2272 = VCVTMNSQh + { 2, OperandInfo366 }, // Inst #2273 = VCVTMNUDf + { 2, OperandInfo366 }, // Inst #2274 = VCVTMNUDh + { 2, OperandInfo158 }, // Inst #2275 = VCVTMNUQf + { 2, OperandInfo158 }, // Inst #2276 = VCVTMNUQh + { 2, OperandInfo367 }, // Inst #2277 = VCVTMSD + { 2, OperandInfo368 }, // Inst #2278 = VCVTMSH + { 2, OperandInfo369 }, // Inst #2279 = VCVTMSS + { 2, OperandInfo367 }, // Inst #2280 = VCVTMUD + { 2, OperandInfo368 }, // Inst #2281 = VCVTMUH + { 2, OperandInfo369 }, // Inst #2282 = VCVTMUS + { 2, OperandInfo366 }, // Inst #2283 = VCVTNNSDf + { 2, OperandInfo366 }, // Inst #2284 = VCVTNNSDh + { 2, OperandInfo158 }, // Inst #2285 = VCVTNNSQf + { 2, OperandInfo158 }, // Inst #2286 = VCVTNNSQh + { 2, OperandInfo366 }, // Inst #2287 = VCVTNNUDf + { 2, OperandInfo366 }, // Inst #2288 = VCVTNNUDh + { 2, OperandInfo158 }, // Inst #2289 = VCVTNNUQf + { 2, OperandInfo158 }, // Inst #2290 = VCVTNNUQh + { 2, OperandInfo367 }, // Inst #2291 = VCVTNSD + { 2, OperandInfo368 }, // Inst #2292 = VCVTNSH + { 2, OperandInfo369 }, // Inst #2293 = VCVTNSS + { 2, OperandInfo367 }, // Inst #2294 = VCVTNUD + { 2, OperandInfo368 }, // Inst #2295 = VCVTNUH + { 2, OperandInfo369 }, // Inst #2296 = VCVTNUS + { 2, OperandInfo366 }, // Inst #2297 = VCVTPNSDf + { 2, OperandInfo366 }, // Inst #2298 = VCVTPNSDh + { 2, OperandInfo158 }, // Inst #2299 = VCVTPNSQf + { 2, OperandInfo158 }, // Inst #2300 = VCVTPNSQh + { 2, OperandInfo366 }, // Inst #2301 = VCVTPNUDf + { 2, OperandInfo366 }, // Inst #2302 = VCVTPNUDh + { 2, OperandInfo158 }, // Inst #2303 = VCVTPNUQf + { 2, OperandInfo158 }, // Inst #2304 = VCVTPNUQh + { 2, OperandInfo367 }, // Inst #2305 = VCVTPSD + { 2, OperandInfo368 }, // Inst #2306 = VCVTPSH + { 2, OperandInfo369 }, // Inst #2307 = VCVTPSS + { 2, OperandInfo367 }, // Inst #2308 = VCVTPUD + { 2, OperandInfo368 }, // Inst #2309 = VCVTPUH + { 2, OperandInfo369 }, // Inst #2310 = VCVTPUS + { 4, OperandInfo372 }, // Inst #2311 = VCVTSD + { 5, OperandInfo370 }, // Inst #2312 = VCVTTDH + { 4, OperandInfo371 }, // Inst #2313 = VCVTTHD + { 4, OperandInfo344 }, // Inst #2314 = VCVTTHS + { 5, OperandInfo105 }, // Inst #2315 = VCVTTSH + { 4, OperandInfo163 }, // Inst #2316 = VCVTf2h + { 4, OperandInfo342 }, // Inst #2317 = VCVTf2sd + { 4, OperandInfo345 }, // Inst #2318 = VCVTf2sq + { 4, OperandInfo342 }, // Inst #2319 = VCVTf2ud + { 4, OperandInfo345 }, // Inst #2320 = VCVTf2uq + { 5, OperandInfo373 }, // Inst #2321 = VCVTf2xsd + { 5, OperandInfo374 }, // Inst #2322 = VCVTf2xsq + { 5, OperandInfo373 }, // Inst #2323 = VCVTf2xud + { 5, OperandInfo374 }, // Inst #2324 = VCVTf2xuq + { 4, OperandInfo375 }, // Inst #2325 = VCVTh2f + { 4, OperandInfo342 }, // Inst #2326 = VCVTh2sd + { 4, OperandInfo345 }, // Inst #2327 = VCVTh2sq + { 4, OperandInfo342 }, // Inst #2328 = VCVTh2ud + { 4, OperandInfo345 }, // Inst #2329 = VCVTh2uq + { 5, OperandInfo373 }, // Inst #2330 = VCVTh2xsd + { 5, OperandInfo374 }, // Inst #2331 = VCVTh2xsq + { 5, OperandInfo373 }, // Inst #2332 = VCVTh2xud + { 5, OperandInfo374 }, // Inst #2333 = VCVTh2xuq + { 4, OperandInfo342 }, // Inst #2334 = VCVTs2fd + { 4, OperandInfo345 }, // Inst #2335 = VCVTs2fq + { 4, OperandInfo342 }, // Inst #2336 = VCVTs2hd + { 4, OperandInfo345 }, // Inst #2337 = VCVTs2hq + { 4, OperandInfo342 }, // Inst #2338 = VCVTu2fd + { 4, OperandInfo345 }, // Inst #2339 = VCVTu2fq + { 4, OperandInfo342 }, // Inst #2340 = VCVTu2hd + { 4, OperandInfo345 }, // Inst #2341 = VCVTu2hq + { 5, OperandInfo373 }, // Inst #2342 = VCVTxs2fd + { 5, OperandInfo374 }, // Inst #2343 = VCVTxs2fq + { 5, OperandInfo373 }, // Inst #2344 = VCVTxs2hd + { 5, OperandInfo374 }, // Inst #2345 = VCVTxs2hq + { 5, OperandInfo373 }, // Inst #2346 = VCVTxu2fd + { 5, OperandInfo374 }, // Inst #2347 = VCVTxu2fq + { 5, OperandInfo373 }, // Inst #2348 = VCVTxu2hd + { 5, OperandInfo374 }, // Inst #2349 = VCVTxu2hq + { 5, OperandInfo340 }, // Inst #2350 = VDIVD + { 5, OperandInfo346 }, // Inst #2351 = VDIVH + { 5, OperandInfo348 }, // Inst #2352 = VDIVS + { 4, OperandInfo376 }, // Inst #2353 = VDUP16d + { 4, OperandInfo377 }, // Inst #2354 = VDUP16q + { 4, OperandInfo376 }, // Inst #2355 = VDUP32d + { 4, OperandInfo377 }, // Inst #2356 = VDUP32q + { 4, OperandInfo376 }, // Inst #2357 = VDUP8d + { 4, OperandInfo377 }, // Inst #2358 = VDUP8q + { 5, OperandInfo373 }, // Inst #2359 = VDUPLN16d + { 5, OperandInfo378 }, // Inst #2360 = VDUPLN16q + { 5, OperandInfo373 }, // Inst #2361 = VDUPLN32d + { 5, OperandInfo378 }, // Inst #2362 = VDUPLN32q + { 5, OperandInfo373 }, // Inst #2363 = VDUPLN8d + { 5, OperandInfo378 }, // Inst #2364 = VDUPLN8q + { 5, OperandInfo340 }, // Inst #2365 = VEORd + { 5, OperandInfo341 }, // Inst #2366 = VEORq + { 6, OperandInfo379 }, // Inst #2367 = VEXTd16 + { 6, OperandInfo379 }, // Inst #2368 = VEXTd32 + { 6, OperandInfo379 }, // Inst #2369 = VEXTd8 + { 6, OperandInfo380 }, // Inst #2370 = VEXTq16 + { 6, OperandInfo380 }, // Inst #2371 = VEXTq32 + { 6, OperandInfo380 }, // Inst #2372 = VEXTq64 + { 6, OperandInfo380 }, // Inst #2373 = VEXTq8 + { 6, OperandInfo338 }, // Inst #2374 = VFMAD + { 6, OperandInfo381 }, // Inst #2375 = VFMAH + { 3, OperandInfo382 }, // Inst #2376 = VFMALD + { 4, OperandInfo383 }, // Inst #2377 = VFMALDI + { 3, OperandInfo384 }, // Inst #2378 = VFMALQ + { 4, OperandInfo385 }, // Inst #2379 = VFMALQI + { 6, OperandInfo386 }, // Inst #2380 = VFMAS + { 6, OperandInfo338 }, // Inst #2381 = VFMAfd + { 6, OperandInfo337 }, // Inst #2382 = VFMAfq + { 6, OperandInfo338 }, // Inst #2383 = VFMAhd + { 6, OperandInfo337 }, // Inst #2384 = VFMAhq + { 6, OperandInfo338 }, // Inst #2385 = VFMSD + { 6, OperandInfo381 }, // Inst #2386 = VFMSH + { 3, OperandInfo382 }, // Inst #2387 = VFMSLD + { 4, OperandInfo383 }, // Inst #2388 = VFMSLDI + { 3, OperandInfo384 }, // Inst #2389 = VFMSLQ + { 4, OperandInfo385 }, // Inst #2390 = VFMSLQI + { 6, OperandInfo386 }, // Inst #2391 = VFMSS + { 6, OperandInfo338 }, // Inst #2392 = VFMSfd + { 6, OperandInfo337 }, // Inst #2393 = VFMSfq + { 6, OperandInfo338 }, // Inst #2394 = VFMShd + { 6, OperandInfo337 }, // Inst #2395 = VFMShq + { 6, OperandInfo338 }, // Inst #2396 = VFNMAD + { 6, OperandInfo381 }, // Inst #2397 = VFNMAH + { 6, OperandInfo386 }, // Inst #2398 = VFNMAS + { 6, OperandInfo338 }, // Inst #2399 = VFNMSD + { 6, OperandInfo381 }, // Inst #2400 = VFNMSH + { 6, OperandInfo386 }, // Inst #2401 = VFNMSS + { 3, OperandInfo310 }, // Inst #2402 = VFP_VMAXNMD + { 3, OperandInfo387 }, // Inst #2403 = VFP_VMAXNMH + { 3, OperandInfo388 }, // Inst #2404 = VFP_VMAXNMS + { 3, OperandInfo310 }, // Inst #2405 = VFP_VMINNMD + { 3, OperandInfo387 }, // Inst #2406 = VFP_VMINNMH + { 3, OperandInfo388 }, // Inst #2407 = VFP_VMINNMS + { 5, OperandInfo389 }, // Inst #2408 = VGETLNi32 + { 5, OperandInfo389 }, // Inst #2409 = VGETLNs16 + { 5, OperandInfo389 }, // Inst #2410 = VGETLNs8 + { 5, OperandInfo389 }, // Inst #2411 = VGETLNu16 + { 5, OperandInfo389 }, // Inst #2412 = VGETLNu8 + { 5, OperandInfo341 }, // Inst #2413 = VHADDsv16i8 + { 5, OperandInfo340 }, // Inst #2414 = VHADDsv2i32 + { 5, OperandInfo340 }, // Inst #2415 = VHADDsv4i16 + { 5, OperandInfo341 }, // Inst #2416 = VHADDsv4i32 + { 5, OperandInfo341 }, // Inst #2417 = VHADDsv8i16 + { 5, OperandInfo340 }, // Inst #2418 = VHADDsv8i8 + { 5, OperandInfo341 }, // Inst #2419 = VHADDuv16i8 + { 5, OperandInfo340 }, // Inst #2420 = VHADDuv2i32 + { 5, OperandInfo340 }, // Inst #2421 = VHADDuv4i16 + { 5, OperandInfo341 }, // Inst #2422 = VHADDuv4i32 + { 5, OperandInfo341 }, // Inst #2423 = VHADDuv8i16 + { 5, OperandInfo340 }, // Inst #2424 = VHADDuv8i8 + { 5, OperandInfo341 }, // Inst #2425 = VHSUBsv16i8 + { 5, OperandInfo340 }, // Inst #2426 = VHSUBsv2i32 + { 5, OperandInfo340 }, // Inst #2427 = VHSUBsv4i16 + { 5, OperandInfo341 }, // Inst #2428 = VHSUBsv4i32 + { 5, OperandInfo341 }, // Inst #2429 = VHSUBsv8i16 + { 5, OperandInfo340 }, // Inst #2430 = VHSUBsv8i8 + { 5, OperandInfo341 }, // Inst #2431 = VHSUBuv16i8 + { 5, OperandInfo340 }, // Inst #2432 = VHSUBuv2i32 + { 5, OperandInfo340 }, // Inst #2433 = VHSUBuv4i16 + { 5, OperandInfo341 }, // Inst #2434 = VHSUBuv4i32 + { 5, OperandInfo341 }, // Inst #2435 = VHSUBuv8i16 + { 5, OperandInfo340 }, // Inst #2436 = VHSUBuv8i8 + { 3, OperandInfo390 }, // Inst #2437 = VINSH + { 4, OperandInfo372 }, // Inst #2438 = VJCVT + { 5, OperandInfo99 }, // Inst #2439 = VLD1DUPd16 + { 6, OperandInfo391 }, // Inst #2440 = VLD1DUPd16wb_fixed + { 7, OperandInfo392 }, // Inst #2441 = VLD1DUPd16wb_register + { 5, OperandInfo99 }, // Inst #2442 = VLD1DUPd32 + { 6, OperandInfo391 }, // Inst #2443 = VLD1DUPd32wb_fixed + { 7, OperandInfo392 }, // Inst #2444 = VLD1DUPd32wb_register + { 5, OperandInfo99 }, // Inst #2445 = VLD1DUPd8 + { 6, OperandInfo391 }, // Inst #2446 = VLD1DUPd8wb_fixed + { 7, OperandInfo392 }, // Inst #2447 = VLD1DUPd8wb_register + { 5, OperandInfo393 }, // Inst #2448 = VLD1DUPq16 + { 6, OperandInfo394 }, // Inst #2449 = VLD1DUPq16wb_fixed + { 7, OperandInfo395 }, // Inst #2450 = VLD1DUPq16wb_register + { 5, OperandInfo393 }, // Inst #2451 = VLD1DUPq32 + { 6, OperandInfo394 }, // Inst #2452 = VLD1DUPq32wb_fixed + { 7, OperandInfo395 }, // Inst #2453 = VLD1DUPq32wb_register + { 5, OperandInfo393 }, // Inst #2454 = VLD1DUPq8 + { 6, OperandInfo394 }, // Inst #2455 = VLD1DUPq8wb_fixed + { 7, OperandInfo395 }, // Inst #2456 = VLD1DUPq8wb_register + { 7, OperandInfo396 }, // Inst #2457 = VLD1LNd16 + { 9, OperandInfo397 }, // Inst #2458 = VLD1LNd16_UPD + { 7, OperandInfo396 }, // Inst #2459 = VLD1LNd32 + { 9, OperandInfo397 }, // Inst #2460 = VLD1LNd32_UPD + { 7, OperandInfo396 }, // Inst #2461 = VLD1LNd8 + { 9, OperandInfo397 }, // Inst #2462 = VLD1LNd8_UPD + { 7, OperandInfo398 }, // Inst #2463 = VLD1LNq16Pseudo + { 9, OperandInfo399 }, // Inst #2464 = VLD1LNq16Pseudo_UPD + { 7, OperandInfo398 }, // Inst #2465 = VLD1LNq32Pseudo + { 9, OperandInfo399 }, // Inst #2466 = VLD1LNq32Pseudo_UPD + { 7, OperandInfo398 }, // Inst #2467 = VLD1LNq8Pseudo + { 9, OperandInfo399 }, // Inst #2468 = VLD1LNq8Pseudo_UPD + { 5, OperandInfo99 }, // Inst #2469 = VLD1d16 + { 5, OperandInfo99 }, // Inst #2470 = VLD1d16Q + { 5, OperandInfo400 }, // Inst #2471 = VLD1d16QPseudo + { 6, OperandInfo401 }, // Inst #2472 = VLD1d16QPseudoWB_fixed + { 7, OperandInfo402 }, // Inst #2473 = VLD1d16QPseudoWB_register + { 6, OperandInfo391 }, // Inst #2474 = VLD1d16Qwb_fixed + { 7, OperandInfo392 }, // Inst #2475 = VLD1d16Qwb_register + { 5, OperandInfo99 }, // Inst #2476 = VLD1d16T + { 5, OperandInfo400 }, // Inst #2477 = VLD1d16TPseudo + { 6, OperandInfo401 }, // Inst #2478 = VLD1d16TPseudoWB_fixed + { 7, OperandInfo402 }, // Inst #2479 = VLD1d16TPseudoWB_register + { 6, OperandInfo391 }, // Inst #2480 = VLD1d16Twb_fixed + { 7, OperandInfo392 }, // Inst #2481 = VLD1d16Twb_register + { 6, OperandInfo391 }, // Inst #2482 = VLD1d16wb_fixed + { 7, OperandInfo392 }, // Inst #2483 = VLD1d16wb_register + { 5, OperandInfo99 }, // Inst #2484 = VLD1d32 + { 5, OperandInfo99 }, // Inst #2485 = VLD1d32Q + { 5, OperandInfo400 }, // Inst #2486 = VLD1d32QPseudo + { 6, OperandInfo401 }, // Inst #2487 = VLD1d32QPseudoWB_fixed + { 7, OperandInfo402 }, // Inst #2488 = VLD1d32QPseudoWB_register + { 6, OperandInfo391 }, // Inst #2489 = VLD1d32Qwb_fixed + { 7, OperandInfo392 }, // Inst #2490 = VLD1d32Qwb_register + { 5, OperandInfo99 }, // Inst #2491 = VLD1d32T + { 5, OperandInfo400 }, // Inst #2492 = VLD1d32TPseudo + { 6, OperandInfo401 }, // Inst #2493 = VLD1d32TPseudoWB_fixed + { 7, OperandInfo402 }, // Inst #2494 = VLD1d32TPseudoWB_register + { 6, OperandInfo391 }, // Inst #2495 = VLD1d32Twb_fixed + { 7, OperandInfo392 }, // Inst #2496 = VLD1d32Twb_register + { 6, OperandInfo391 }, // Inst #2497 = VLD1d32wb_fixed + { 7, OperandInfo392 }, // Inst #2498 = VLD1d32wb_register + { 5, OperandInfo99 }, // Inst #2499 = VLD1d64 + { 5, OperandInfo99 }, // Inst #2500 = VLD1d64Q + { 5, OperandInfo400 }, // Inst #2501 = VLD1d64QPseudo + { 6, OperandInfo401 }, // Inst #2502 = VLD1d64QPseudoWB_fixed + { 7, OperandInfo402 }, // Inst #2503 = VLD1d64QPseudoWB_register + { 6, OperandInfo391 }, // Inst #2504 = VLD1d64Qwb_fixed + { 7, OperandInfo392 }, // Inst #2505 = VLD1d64Qwb_register + { 5, OperandInfo99 }, // Inst #2506 = VLD1d64T + { 5, OperandInfo400 }, // Inst #2507 = VLD1d64TPseudo + { 6, OperandInfo401 }, // Inst #2508 = VLD1d64TPseudoWB_fixed + { 7, OperandInfo402 }, // Inst #2509 = VLD1d64TPseudoWB_register + { 6, OperandInfo391 }, // Inst #2510 = VLD1d64Twb_fixed + { 7, OperandInfo392 }, // Inst #2511 = VLD1d64Twb_register + { 6, OperandInfo391 }, // Inst #2512 = VLD1d64wb_fixed + { 7, OperandInfo392 }, // Inst #2513 = VLD1d64wb_register + { 5, OperandInfo99 }, // Inst #2514 = VLD1d8 + { 5, OperandInfo99 }, // Inst #2515 = VLD1d8Q + { 5, OperandInfo400 }, // Inst #2516 = VLD1d8QPseudo + { 6, OperandInfo401 }, // Inst #2517 = VLD1d8QPseudoWB_fixed + { 7, OperandInfo402 }, // Inst #2518 = VLD1d8QPseudoWB_register + { 6, OperandInfo391 }, // Inst #2519 = VLD1d8Qwb_fixed + { 7, OperandInfo392 }, // Inst #2520 = VLD1d8Qwb_register + { 5, OperandInfo99 }, // Inst #2521 = VLD1d8T + { 5, OperandInfo400 }, // Inst #2522 = VLD1d8TPseudo + { 6, OperandInfo401 }, // Inst #2523 = VLD1d8TPseudoWB_fixed + { 7, OperandInfo402 }, // Inst #2524 = VLD1d8TPseudoWB_register + { 6, OperandInfo391 }, // Inst #2525 = VLD1d8Twb_fixed + { 7, OperandInfo392 }, // Inst #2526 = VLD1d8Twb_register + { 6, OperandInfo391 }, // Inst #2527 = VLD1d8wb_fixed + { 7, OperandInfo392 }, // Inst #2528 = VLD1d8wb_register + { 5, OperandInfo393 }, // Inst #2529 = VLD1q16 + { 6, OperandInfo403 }, // Inst #2530 = VLD1q16HighQPseudo + { 8, OperandInfo404 }, // Inst #2531 = VLD1q16HighQPseudo_UPD + { 6, OperandInfo403 }, // Inst #2532 = VLD1q16HighTPseudo + { 8, OperandInfo404 }, // Inst #2533 = VLD1q16HighTPseudo_UPD + { 8, OperandInfo404 }, // Inst #2534 = VLD1q16LowQPseudo_UPD + { 8, OperandInfo404 }, // Inst #2535 = VLD1q16LowTPseudo_UPD + { 6, OperandInfo394 }, // Inst #2536 = VLD1q16wb_fixed + { 7, OperandInfo395 }, // Inst #2537 = VLD1q16wb_register + { 5, OperandInfo393 }, // Inst #2538 = VLD1q32 + { 6, OperandInfo403 }, // Inst #2539 = VLD1q32HighQPseudo + { 8, OperandInfo404 }, // Inst #2540 = VLD1q32HighQPseudo_UPD + { 6, OperandInfo403 }, // Inst #2541 = VLD1q32HighTPseudo + { 8, OperandInfo404 }, // Inst #2542 = VLD1q32HighTPseudo_UPD + { 8, OperandInfo404 }, // Inst #2543 = VLD1q32LowQPseudo_UPD + { 8, OperandInfo404 }, // Inst #2544 = VLD1q32LowTPseudo_UPD + { 6, OperandInfo394 }, // Inst #2545 = VLD1q32wb_fixed + { 7, OperandInfo395 }, // Inst #2546 = VLD1q32wb_register + { 5, OperandInfo393 }, // Inst #2547 = VLD1q64 + { 6, OperandInfo403 }, // Inst #2548 = VLD1q64HighQPseudo + { 8, OperandInfo404 }, // Inst #2549 = VLD1q64HighQPseudo_UPD + { 6, OperandInfo403 }, // Inst #2550 = VLD1q64HighTPseudo + { 8, OperandInfo404 }, // Inst #2551 = VLD1q64HighTPseudo_UPD + { 8, OperandInfo404 }, // Inst #2552 = VLD1q64LowQPseudo_UPD + { 8, OperandInfo404 }, // Inst #2553 = VLD1q64LowTPseudo_UPD + { 6, OperandInfo394 }, // Inst #2554 = VLD1q64wb_fixed + { 7, OperandInfo395 }, // Inst #2555 = VLD1q64wb_register + { 5, OperandInfo393 }, // Inst #2556 = VLD1q8 + { 6, OperandInfo403 }, // Inst #2557 = VLD1q8HighQPseudo + { 8, OperandInfo404 }, // Inst #2558 = VLD1q8HighQPseudo_UPD + { 6, OperandInfo403 }, // Inst #2559 = VLD1q8HighTPseudo + { 8, OperandInfo404 }, // Inst #2560 = VLD1q8HighTPseudo_UPD + { 8, OperandInfo404 }, // Inst #2561 = VLD1q8LowQPseudo_UPD + { 8, OperandInfo404 }, // Inst #2562 = VLD1q8LowTPseudo_UPD + { 6, OperandInfo394 }, // Inst #2563 = VLD1q8wb_fixed + { 7, OperandInfo395 }, // Inst #2564 = VLD1q8wb_register + { 5, OperandInfo393 }, // Inst #2565 = VLD2DUPd16 + { 6, OperandInfo394 }, // Inst #2566 = VLD2DUPd16wb_fixed + { 7, OperandInfo395 }, // Inst #2567 = VLD2DUPd16wb_register + { 5, OperandInfo405 }, // Inst #2568 = VLD2DUPd16x2 + { 6, OperandInfo406 }, // Inst #2569 = VLD2DUPd16x2wb_fixed + { 7, OperandInfo407 }, // Inst #2570 = VLD2DUPd16x2wb_register + { 5, OperandInfo393 }, // Inst #2571 = VLD2DUPd32 + { 6, OperandInfo394 }, // Inst #2572 = VLD2DUPd32wb_fixed + { 7, OperandInfo395 }, // Inst #2573 = VLD2DUPd32wb_register + { 5, OperandInfo405 }, // Inst #2574 = VLD2DUPd32x2 + { 6, OperandInfo406 }, // Inst #2575 = VLD2DUPd32x2wb_fixed + { 7, OperandInfo407 }, // Inst #2576 = VLD2DUPd32x2wb_register + { 5, OperandInfo393 }, // Inst #2577 = VLD2DUPd8 + { 6, OperandInfo394 }, // Inst #2578 = VLD2DUPd8wb_fixed + { 7, OperandInfo395 }, // Inst #2579 = VLD2DUPd8wb_register + { 5, OperandInfo405 }, // Inst #2580 = VLD2DUPd8x2 + { 6, OperandInfo406 }, // Inst #2581 = VLD2DUPd8x2wb_fixed + { 7, OperandInfo407 }, // Inst #2582 = VLD2DUPd8x2wb_register + { 5, OperandInfo400 }, // Inst #2583 = VLD2DUPq16EvenPseudo + { 5, OperandInfo400 }, // Inst #2584 = VLD2DUPq16OddPseudo + { 6, OperandInfo401 }, // Inst #2585 = VLD2DUPq16OddPseudoWB_fixed + { 7, OperandInfo408 }, // Inst #2586 = VLD2DUPq16OddPseudoWB_register + { 5, OperandInfo400 }, // Inst #2587 = VLD2DUPq32EvenPseudo + { 5, OperandInfo400 }, // Inst #2588 = VLD2DUPq32OddPseudo + { 6, OperandInfo401 }, // Inst #2589 = VLD2DUPq32OddPseudoWB_fixed + { 7, OperandInfo408 }, // Inst #2590 = VLD2DUPq32OddPseudoWB_register + { 5, OperandInfo400 }, // Inst #2591 = VLD2DUPq8EvenPseudo + { 5, OperandInfo400 }, // Inst #2592 = VLD2DUPq8OddPseudo + { 6, OperandInfo401 }, // Inst #2593 = VLD2DUPq8OddPseudoWB_fixed + { 7, OperandInfo408 }, // Inst #2594 = VLD2DUPq8OddPseudoWB_register + { 9, OperandInfo409 }, // Inst #2595 = VLD2LNd16 + { 7, OperandInfo398 }, // Inst #2596 = VLD2LNd16Pseudo + { 9, OperandInfo399 }, // Inst #2597 = VLD2LNd16Pseudo_UPD + { 11, OperandInfo410 }, // Inst #2598 = VLD2LNd16_UPD + { 9, OperandInfo409 }, // Inst #2599 = VLD2LNd32 + { 7, OperandInfo398 }, // Inst #2600 = VLD2LNd32Pseudo + { 9, OperandInfo399 }, // Inst #2601 = VLD2LNd32Pseudo_UPD + { 11, OperandInfo410 }, // Inst #2602 = VLD2LNd32_UPD + { 9, OperandInfo409 }, // Inst #2603 = VLD2LNd8 + { 7, OperandInfo398 }, // Inst #2604 = VLD2LNd8Pseudo + { 9, OperandInfo399 }, // Inst #2605 = VLD2LNd8Pseudo_UPD + { 11, OperandInfo410 }, // Inst #2606 = VLD2LNd8_UPD + { 9, OperandInfo409 }, // Inst #2607 = VLD2LNq16 + { 7, OperandInfo411 }, // Inst #2608 = VLD2LNq16Pseudo + { 9, OperandInfo412 }, // Inst #2609 = VLD2LNq16Pseudo_UPD + { 11, OperandInfo410 }, // Inst #2610 = VLD2LNq16_UPD + { 9, OperandInfo409 }, // Inst #2611 = VLD2LNq32 + { 7, OperandInfo411 }, // Inst #2612 = VLD2LNq32Pseudo + { 9, OperandInfo412 }, // Inst #2613 = VLD2LNq32Pseudo_UPD + { 11, OperandInfo410 }, // Inst #2614 = VLD2LNq32_UPD + { 5, OperandInfo393 }, // Inst #2615 = VLD2b16 + { 6, OperandInfo394 }, // Inst #2616 = VLD2b16wb_fixed + { 7, OperandInfo395 }, // Inst #2617 = VLD2b16wb_register + { 5, OperandInfo393 }, // Inst #2618 = VLD2b32 + { 6, OperandInfo394 }, // Inst #2619 = VLD2b32wb_fixed + { 7, OperandInfo395 }, // Inst #2620 = VLD2b32wb_register + { 5, OperandInfo393 }, // Inst #2621 = VLD2b8 + { 6, OperandInfo394 }, // Inst #2622 = VLD2b8wb_fixed + { 7, OperandInfo395 }, // Inst #2623 = VLD2b8wb_register + { 5, OperandInfo393 }, // Inst #2624 = VLD2d16 + { 6, OperandInfo394 }, // Inst #2625 = VLD2d16wb_fixed + { 7, OperandInfo395 }, // Inst #2626 = VLD2d16wb_register + { 5, OperandInfo393 }, // Inst #2627 = VLD2d32 + { 6, OperandInfo394 }, // Inst #2628 = VLD2d32wb_fixed + { 7, OperandInfo395 }, // Inst #2629 = VLD2d32wb_register + { 5, OperandInfo393 }, // Inst #2630 = VLD2d8 + { 6, OperandInfo394 }, // Inst #2631 = VLD2d8wb_fixed + { 7, OperandInfo395 }, // Inst #2632 = VLD2d8wb_register + { 5, OperandInfo99 }, // Inst #2633 = VLD2q16 + { 5, OperandInfo400 }, // Inst #2634 = VLD2q16Pseudo + { 6, OperandInfo401 }, // Inst #2635 = VLD2q16PseudoWB_fixed + { 7, OperandInfo402 }, // Inst #2636 = VLD2q16PseudoWB_register + { 6, OperandInfo391 }, // Inst #2637 = VLD2q16wb_fixed + { 7, OperandInfo392 }, // Inst #2638 = VLD2q16wb_register + { 5, OperandInfo99 }, // Inst #2639 = VLD2q32 + { 5, OperandInfo400 }, // Inst #2640 = VLD2q32Pseudo + { 6, OperandInfo401 }, // Inst #2641 = VLD2q32PseudoWB_fixed + { 7, OperandInfo402 }, // Inst #2642 = VLD2q32PseudoWB_register + { 6, OperandInfo391 }, // Inst #2643 = VLD2q32wb_fixed + { 7, OperandInfo392 }, // Inst #2644 = VLD2q32wb_register + { 5, OperandInfo99 }, // Inst #2645 = VLD2q8 + { 5, OperandInfo400 }, // Inst #2646 = VLD2q8Pseudo + { 6, OperandInfo401 }, // Inst #2647 = VLD2q8PseudoWB_fixed + { 7, OperandInfo402 }, // Inst #2648 = VLD2q8PseudoWB_register + { 6, OperandInfo391 }, // Inst #2649 = VLD2q8wb_fixed + { 7, OperandInfo392 }, // Inst #2650 = VLD2q8wb_register + { 7, OperandInfo413 }, // Inst #2651 = VLD3DUPd16 + { 5, OperandInfo400 }, // Inst #2652 = VLD3DUPd16Pseudo + { 7, OperandInfo408 }, // Inst #2653 = VLD3DUPd16Pseudo_UPD + { 9, OperandInfo414 }, // Inst #2654 = VLD3DUPd16_UPD + { 7, OperandInfo413 }, // Inst #2655 = VLD3DUPd32 + { 5, OperandInfo400 }, // Inst #2656 = VLD3DUPd32Pseudo + { 7, OperandInfo408 }, // Inst #2657 = VLD3DUPd32Pseudo_UPD + { 9, OperandInfo414 }, // Inst #2658 = VLD3DUPd32_UPD + { 7, OperandInfo413 }, // Inst #2659 = VLD3DUPd8 + { 5, OperandInfo400 }, // Inst #2660 = VLD3DUPd8Pseudo + { 7, OperandInfo408 }, // Inst #2661 = VLD3DUPd8Pseudo_UPD + { 9, OperandInfo414 }, // Inst #2662 = VLD3DUPd8_UPD + { 7, OperandInfo413 }, // Inst #2663 = VLD3DUPq16 + { 6, OperandInfo403 }, // Inst #2664 = VLD3DUPq16EvenPseudo + { 6, OperandInfo403 }, // Inst #2665 = VLD3DUPq16OddPseudo + { 8, OperandInfo404 }, // Inst #2666 = VLD3DUPq16OddPseudo_UPD + { 9, OperandInfo414 }, // Inst #2667 = VLD3DUPq16_UPD + { 7, OperandInfo413 }, // Inst #2668 = VLD3DUPq32 + { 6, OperandInfo403 }, // Inst #2669 = VLD3DUPq32EvenPseudo + { 6, OperandInfo403 }, // Inst #2670 = VLD3DUPq32OddPseudo + { 8, OperandInfo404 }, // Inst #2671 = VLD3DUPq32OddPseudo_UPD + { 9, OperandInfo414 }, // Inst #2672 = VLD3DUPq32_UPD + { 7, OperandInfo413 }, // Inst #2673 = VLD3DUPq8 + { 6, OperandInfo403 }, // Inst #2674 = VLD3DUPq8EvenPseudo + { 6, OperandInfo403 }, // Inst #2675 = VLD3DUPq8OddPseudo + { 8, OperandInfo404 }, // Inst #2676 = VLD3DUPq8OddPseudo_UPD + { 9, OperandInfo414 }, // Inst #2677 = VLD3DUPq8_UPD + { 11, OperandInfo415 }, // Inst #2678 = VLD3LNd16 + { 7, OperandInfo411 }, // Inst #2679 = VLD3LNd16Pseudo + { 9, OperandInfo412 }, // Inst #2680 = VLD3LNd16Pseudo_UPD + { 13, OperandInfo416 }, // Inst #2681 = VLD3LNd16_UPD + { 11, OperandInfo415 }, // Inst #2682 = VLD3LNd32 + { 7, OperandInfo411 }, // Inst #2683 = VLD3LNd32Pseudo + { 9, OperandInfo412 }, // Inst #2684 = VLD3LNd32Pseudo_UPD + { 13, OperandInfo416 }, // Inst #2685 = VLD3LNd32_UPD + { 11, OperandInfo415 }, // Inst #2686 = VLD3LNd8 + { 7, OperandInfo411 }, // Inst #2687 = VLD3LNd8Pseudo + { 9, OperandInfo412 }, // Inst #2688 = VLD3LNd8Pseudo_UPD + { 13, OperandInfo416 }, // Inst #2689 = VLD3LNd8_UPD + { 11, OperandInfo415 }, // Inst #2690 = VLD3LNq16 + { 7, OperandInfo417 }, // Inst #2691 = VLD3LNq16Pseudo + { 9, OperandInfo418 }, // Inst #2692 = VLD3LNq16Pseudo_UPD + { 13, OperandInfo416 }, // Inst #2693 = VLD3LNq16_UPD + { 11, OperandInfo415 }, // Inst #2694 = VLD3LNq32 + { 7, OperandInfo417 }, // Inst #2695 = VLD3LNq32Pseudo + { 9, OperandInfo418 }, // Inst #2696 = VLD3LNq32Pseudo_UPD + { 13, OperandInfo416 }, // Inst #2697 = VLD3LNq32_UPD + { 7, OperandInfo413 }, // Inst #2698 = VLD3d16 + { 5, OperandInfo400 }, // Inst #2699 = VLD3d16Pseudo + { 7, OperandInfo408 }, // Inst #2700 = VLD3d16Pseudo_UPD + { 9, OperandInfo414 }, // Inst #2701 = VLD3d16_UPD + { 7, OperandInfo413 }, // Inst #2702 = VLD3d32 + { 5, OperandInfo400 }, // Inst #2703 = VLD3d32Pseudo + { 7, OperandInfo408 }, // Inst #2704 = VLD3d32Pseudo_UPD + { 9, OperandInfo414 }, // Inst #2705 = VLD3d32_UPD + { 7, OperandInfo413 }, // Inst #2706 = VLD3d8 + { 5, OperandInfo400 }, // Inst #2707 = VLD3d8Pseudo + { 7, OperandInfo408 }, // Inst #2708 = VLD3d8Pseudo_UPD + { 9, OperandInfo414 }, // Inst #2709 = VLD3d8_UPD + { 7, OperandInfo413 }, // Inst #2710 = VLD3q16 + { 8, OperandInfo404 }, // Inst #2711 = VLD3q16Pseudo_UPD + { 9, OperandInfo414 }, // Inst #2712 = VLD3q16_UPD + { 6, OperandInfo403 }, // Inst #2713 = VLD3q16oddPseudo + { 8, OperandInfo404 }, // Inst #2714 = VLD3q16oddPseudo_UPD + { 7, OperandInfo413 }, // Inst #2715 = VLD3q32 + { 8, OperandInfo404 }, // Inst #2716 = VLD3q32Pseudo_UPD + { 9, OperandInfo414 }, // Inst #2717 = VLD3q32_UPD + { 6, OperandInfo403 }, // Inst #2718 = VLD3q32oddPseudo + { 8, OperandInfo404 }, // Inst #2719 = VLD3q32oddPseudo_UPD + { 7, OperandInfo413 }, // Inst #2720 = VLD3q8 + { 8, OperandInfo404 }, // Inst #2721 = VLD3q8Pseudo_UPD + { 9, OperandInfo414 }, // Inst #2722 = VLD3q8_UPD + { 6, OperandInfo403 }, // Inst #2723 = VLD3q8oddPseudo + { 8, OperandInfo404 }, // Inst #2724 = VLD3q8oddPseudo_UPD + { 8, OperandInfo419 }, // Inst #2725 = VLD4DUPd16 + { 5, OperandInfo400 }, // Inst #2726 = VLD4DUPd16Pseudo + { 7, OperandInfo408 }, // Inst #2727 = VLD4DUPd16Pseudo_UPD + { 10, OperandInfo420 }, // Inst #2728 = VLD4DUPd16_UPD + { 8, OperandInfo419 }, // Inst #2729 = VLD4DUPd32 + { 5, OperandInfo400 }, // Inst #2730 = VLD4DUPd32Pseudo + { 7, OperandInfo408 }, // Inst #2731 = VLD4DUPd32Pseudo_UPD + { 10, OperandInfo420 }, // Inst #2732 = VLD4DUPd32_UPD + { 8, OperandInfo419 }, // Inst #2733 = VLD4DUPd8 + { 5, OperandInfo400 }, // Inst #2734 = VLD4DUPd8Pseudo + { 7, OperandInfo408 }, // Inst #2735 = VLD4DUPd8Pseudo_UPD + { 10, OperandInfo420 }, // Inst #2736 = VLD4DUPd8_UPD + { 8, OperandInfo419 }, // Inst #2737 = VLD4DUPq16 + { 6, OperandInfo403 }, // Inst #2738 = VLD4DUPq16EvenPseudo + { 6, OperandInfo403 }, // Inst #2739 = VLD4DUPq16OddPseudo + { 8, OperandInfo404 }, // Inst #2740 = VLD4DUPq16OddPseudo_UPD + { 10, OperandInfo420 }, // Inst #2741 = VLD4DUPq16_UPD + { 8, OperandInfo419 }, // Inst #2742 = VLD4DUPq32 + { 6, OperandInfo403 }, // Inst #2743 = VLD4DUPq32EvenPseudo + { 6, OperandInfo403 }, // Inst #2744 = VLD4DUPq32OddPseudo + { 8, OperandInfo404 }, // Inst #2745 = VLD4DUPq32OddPseudo_UPD + { 10, OperandInfo420 }, // Inst #2746 = VLD4DUPq32_UPD + { 8, OperandInfo419 }, // Inst #2747 = VLD4DUPq8 + { 6, OperandInfo403 }, // Inst #2748 = VLD4DUPq8EvenPseudo + { 6, OperandInfo403 }, // Inst #2749 = VLD4DUPq8OddPseudo + { 8, OperandInfo404 }, // Inst #2750 = VLD4DUPq8OddPseudo_UPD + { 10, OperandInfo420 }, // Inst #2751 = VLD4DUPq8_UPD + { 13, OperandInfo421 }, // Inst #2752 = VLD4LNd16 + { 7, OperandInfo411 }, // Inst #2753 = VLD4LNd16Pseudo + { 9, OperandInfo412 }, // Inst #2754 = VLD4LNd16Pseudo_UPD + { 15, OperandInfo422 }, // Inst #2755 = VLD4LNd16_UPD + { 13, OperandInfo421 }, // Inst #2756 = VLD4LNd32 + { 7, OperandInfo411 }, // Inst #2757 = VLD4LNd32Pseudo + { 9, OperandInfo412 }, // Inst #2758 = VLD4LNd32Pseudo_UPD + { 15, OperandInfo422 }, // Inst #2759 = VLD4LNd32_UPD + { 13, OperandInfo421 }, // Inst #2760 = VLD4LNd8 + { 7, OperandInfo411 }, // Inst #2761 = VLD4LNd8Pseudo + { 9, OperandInfo412 }, // Inst #2762 = VLD4LNd8Pseudo_UPD + { 15, OperandInfo422 }, // Inst #2763 = VLD4LNd8_UPD + { 13, OperandInfo421 }, // Inst #2764 = VLD4LNq16 + { 7, OperandInfo417 }, // Inst #2765 = VLD4LNq16Pseudo + { 9, OperandInfo418 }, // Inst #2766 = VLD4LNq16Pseudo_UPD + { 15, OperandInfo422 }, // Inst #2767 = VLD4LNq16_UPD + { 13, OperandInfo421 }, // Inst #2768 = VLD4LNq32 + { 7, OperandInfo417 }, // Inst #2769 = VLD4LNq32Pseudo + { 9, OperandInfo418 }, // Inst #2770 = VLD4LNq32Pseudo_UPD + { 15, OperandInfo422 }, // Inst #2771 = VLD4LNq32_UPD + { 8, OperandInfo419 }, // Inst #2772 = VLD4d16 + { 5, OperandInfo400 }, // Inst #2773 = VLD4d16Pseudo + { 7, OperandInfo408 }, // Inst #2774 = VLD4d16Pseudo_UPD + { 10, OperandInfo420 }, // Inst #2775 = VLD4d16_UPD + { 8, OperandInfo419 }, // Inst #2776 = VLD4d32 + { 5, OperandInfo400 }, // Inst #2777 = VLD4d32Pseudo + { 7, OperandInfo408 }, // Inst #2778 = VLD4d32Pseudo_UPD + { 10, OperandInfo420 }, // Inst #2779 = VLD4d32_UPD + { 8, OperandInfo419 }, // Inst #2780 = VLD4d8 + { 5, OperandInfo400 }, // Inst #2781 = VLD4d8Pseudo + { 7, OperandInfo408 }, // Inst #2782 = VLD4d8Pseudo_UPD + { 10, OperandInfo420 }, // Inst #2783 = VLD4d8_UPD + { 8, OperandInfo419 }, // Inst #2784 = VLD4q16 + { 8, OperandInfo404 }, // Inst #2785 = VLD4q16Pseudo_UPD + { 10, OperandInfo420 }, // Inst #2786 = VLD4q16_UPD + { 6, OperandInfo403 }, // Inst #2787 = VLD4q16oddPseudo + { 8, OperandInfo404 }, // Inst #2788 = VLD4q16oddPseudo_UPD + { 8, OperandInfo419 }, // Inst #2789 = VLD4q32 + { 8, OperandInfo404 }, // Inst #2790 = VLD4q32Pseudo_UPD + { 10, OperandInfo420 }, // Inst #2791 = VLD4q32_UPD + { 6, OperandInfo403 }, // Inst #2792 = VLD4q32oddPseudo + { 8, OperandInfo404 }, // Inst #2793 = VLD4q32oddPseudo_UPD + { 8, OperandInfo419 }, // Inst #2794 = VLD4q8 + { 8, OperandInfo404 }, // Inst #2795 = VLD4q8Pseudo_UPD + { 10, OperandInfo420 }, // Inst #2796 = VLD4q8_UPD + { 6, OperandInfo403 }, // Inst #2797 = VLD4q8oddPseudo + { 8, OperandInfo404 }, // Inst #2798 = VLD4q8oddPseudo_UPD + { 5, OperandInfo66 }, // Inst #2799 = VLDMDDB_UPD + { 4, OperandInfo206 }, // Inst #2800 = VLDMDIA + { 5, OperandInfo66 }, // Inst #2801 = VLDMDIA_UPD + { 4, OperandInfo423 }, // Inst #2802 = VLDMQIA + { 5, OperandInfo66 }, // Inst #2803 = VLDMSDB_UPD + { 4, OperandInfo206 }, // Inst #2804 = VLDMSIA + { 5, OperandInfo66 }, // Inst #2805 = VLDMSIA_UPD + { 5, OperandInfo99 }, // Inst #2806 = VLDRD + { 5, OperandInfo424 }, // Inst #2807 = VLDRH + { 5, OperandInfo425 }, // Inst #2808 = VLDRS + { 4, OperandInfo426 }, // Inst #2809 = VLDR_FPCXTNS_off + { 5, OperandInfo427 }, // Inst #2810 = VLDR_FPCXTNS_post + { 5, OperandInfo427 }, // Inst #2811 = VLDR_FPCXTNS_pre + { 4, OperandInfo426 }, // Inst #2812 = VLDR_FPCXTS_off + { 5, OperandInfo427 }, // Inst #2813 = VLDR_FPCXTS_post + { 5, OperandInfo427 }, // Inst #2814 = VLDR_FPCXTS_pre + { 4, OperandInfo426 }, // Inst #2815 = VLDR_FPSCR_NZCVQC_off + { 5, OperandInfo427 }, // Inst #2816 = VLDR_FPSCR_NZCVQC_post + { 5, OperandInfo427 }, // Inst #2817 = VLDR_FPSCR_NZCVQC_pre + { 4, OperandInfo426 }, // Inst #2818 = VLDR_FPSCR_off + { 5, OperandInfo427 }, // Inst #2819 = VLDR_FPSCR_post + { 5, OperandInfo427 }, // Inst #2820 = VLDR_FPSCR_pre + { 5, OperandInfo428 }, // Inst #2821 = VLDR_P0_off + { 6, OperandInfo429 }, // Inst #2822 = VLDR_P0_post + { 6, OperandInfo429 }, // Inst #2823 = VLDR_P0_pre + { 4, OperandInfo426 }, // Inst #2824 = VLDR_VPR_off + { 5, OperandInfo427 }, // Inst #2825 = VLDR_VPR_post + { 5, OperandInfo427 }, // Inst #2826 = VLDR_VPR_pre + { 3, OperandInfo239 }, // Inst #2827 = VLLDM + { 3, OperandInfo239 }, // Inst #2828 = VLSTM + { 5, OperandInfo340 }, // Inst #2829 = VMAXfd + { 5, OperandInfo341 }, // Inst #2830 = VMAXfq + { 5, OperandInfo340 }, // Inst #2831 = VMAXhd + { 5, OperandInfo341 }, // Inst #2832 = VMAXhq + { 5, OperandInfo341 }, // Inst #2833 = VMAXsv16i8 + { 5, OperandInfo340 }, // Inst #2834 = VMAXsv2i32 + { 5, OperandInfo340 }, // Inst #2835 = VMAXsv4i16 + { 5, OperandInfo341 }, // Inst #2836 = VMAXsv4i32 + { 5, OperandInfo341 }, // Inst #2837 = VMAXsv8i16 + { 5, OperandInfo340 }, // Inst #2838 = VMAXsv8i8 + { 5, OperandInfo341 }, // Inst #2839 = VMAXuv16i8 + { 5, OperandInfo340 }, // Inst #2840 = VMAXuv2i32 + { 5, OperandInfo340 }, // Inst #2841 = VMAXuv4i16 + { 5, OperandInfo341 }, // Inst #2842 = VMAXuv4i32 + { 5, OperandInfo341 }, // Inst #2843 = VMAXuv8i16 + { 5, OperandInfo340 }, // Inst #2844 = VMAXuv8i8 + { 5, OperandInfo340 }, // Inst #2845 = VMINfd + { 5, OperandInfo341 }, // Inst #2846 = VMINfq + { 5, OperandInfo340 }, // Inst #2847 = VMINhd + { 5, OperandInfo341 }, // Inst #2848 = VMINhq + { 5, OperandInfo341 }, // Inst #2849 = VMINsv16i8 + { 5, OperandInfo340 }, // Inst #2850 = VMINsv2i32 + { 5, OperandInfo340 }, // Inst #2851 = VMINsv4i16 + { 5, OperandInfo341 }, // Inst #2852 = VMINsv4i32 + { 5, OperandInfo341 }, // Inst #2853 = VMINsv8i16 + { 5, OperandInfo340 }, // Inst #2854 = VMINsv8i8 + { 5, OperandInfo341 }, // Inst #2855 = VMINuv16i8 + { 5, OperandInfo340 }, // Inst #2856 = VMINuv2i32 + { 5, OperandInfo340 }, // Inst #2857 = VMINuv4i16 + { 5, OperandInfo341 }, // Inst #2858 = VMINuv4i32 + { 5, OperandInfo341 }, // Inst #2859 = VMINuv8i16 + { 5, OperandInfo340 }, // Inst #2860 = VMINuv8i8 + { 6, OperandInfo338 }, // Inst #2861 = VMLAD + { 6, OperandInfo381 }, // Inst #2862 = VMLAH + { 7, OperandInfo430 }, // Inst #2863 = VMLALslsv2i32 + { 7, OperandInfo431 }, // Inst #2864 = VMLALslsv4i16 + { 7, OperandInfo430 }, // Inst #2865 = VMLALsluv2i32 + { 7, OperandInfo431 }, // Inst #2866 = VMLALsluv4i16 + { 6, OperandInfo336 }, // Inst #2867 = VMLALsv2i64 + { 6, OperandInfo336 }, // Inst #2868 = VMLALsv4i32 + { 6, OperandInfo336 }, // Inst #2869 = VMLALsv8i16 + { 6, OperandInfo336 }, // Inst #2870 = VMLALuv2i64 + { 6, OperandInfo336 }, // Inst #2871 = VMLALuv4i32 + { 6, OperandInfo336 }, // Inst #2872 = VMLALuv8i16 + { 6, OperandInfo386 }, // Inst #2873 = VMLAS + { 6, OperandInfo338 }, // Inst #2874 = VMLAfd + { 6, OperandInfo337 }, // Inst #2875 = VMLAfq + { 6, OperandInfo338 }, // Inst #2876 = VMLAhd + { 6, OperandInfo337 }, // Inst #2877 = VMLAhq + { 7, OperandInfo432 }, // Inst #2878 = VMLAslfd + { 7, OperandInfo433 }, // Inst #2879 = VMLAslfq + { 7, OperandInfo434 }, // Inst #2880 = VMLAslhd + { 7, OperandInfo435 }, // Inst #2881 = VMLAslhq + { 7, OperandInfo432 }, // Inst #2882 = VMLAslv2i32 + { 7, OperandInfo434 }, // Inst #2883 = VMLAslv4i16 + { 7, OperandInfo433 }, // Inst #2884 = VMLAslv4i32 + { 7, OperandInfo435 }, // Inst #2885 = VMLAslv8i16 + { 6, OperandInfo337 }, // Inst #2886 = VMLAv16i8 + { 6, OperandInfo338 }, // Inst #2887 = VMLAv2i32 + { 6, OperandInfo338 }, // Inst #2888 = VMLAv4i16 + { 6, OperandInfo337 }, // Inst #2889 = VMLAv4i32 + { 6, OperandInfo337 }, // Inst #2890 = VMLAv8i16 + { 6, OperandInfo338 }, // Inst #2891 = VMLAv8i8 + { 6, OperandInfo338 }, // Inst #2892 = VMLSD + { 6, OperandInfo381 }, // Inst #2893 = VMLSH + { 7, OperandInfo430 }, // Inst #2894 = VMLSLslsv2i32 + { 7, OperandInfo431 }, // Inst #2895 = VMLSLslsv4i16 + { 7, OperandInfo430 }, // Inst #2896 = VMLSLsluv2i32 + { 7, OperandInfo431 }, // Inst #2897 = VMLSLsluv4i16 + { 6, OperandInfo336 }, // Inst #2898 = VMLSLsv2i64 + { 6, OperandInfo336 }, // Inst #2899 = VMLSLsv4i32 + { 6, OperandInfo336 }, // Inst #2900 = VMLSLsv8i16 + { 6, OperandInfo336 }, // Inst #2901 = VMLSLuv2i64 + { 6, OperandInfo336 }, // Inst #2902 = VMLSLuv4i32 + { 6, OperandInfo336 }, // Inst #2903 = VMLSLuv8i16 + { 6, OperandInfo386 }, // Inst #2904 = VMLSS + { 6, OperandInfo338 }, // Inst #2905 = VMLSfd + { 6, OperandInfo337 }, // Inst #2906 = VMLSfq + { 6, OperandInfo338 }, // Inst #2907 = VMLShd + { 6, OperandInfo337 }, // Inst #2908 = VMLShq + { 7, OperandInfo432 }, // Inst #2909 = VMLSslfd + { 7, OperandInfo433 }, // Inst #2910 = VMLSslfq + { 7, OperandInfo434 }, // Inst #2911 = VMLSslhd + { 7, OperandInfo435 }, // Inst #2912 = VMLSslhq + { 7, OperandInfo432 }, // Inst #2913 = VMLSslv2i32 + { 7, OperandInfo434 }, // Inst #2914 = VMLSslv4i16 + { 7, OperandInfo433 }, // Inst #2915 = VMLSslv4i32 + { 7, OperandInfo435 }, // Inst #2916 = VMLSslv8i16 + { 6, OperandInfo337 }, // Inst #2917 = VMLSv16i8 + { 6, OperandInfo338 }, // Inst #2918 = VMLSv2i32 + { 6, OperandInfo338 }, // Inst #2919 = VMLSv4i16 + { 6, OperandInfo337 }, // Inst #2920 = VMLSv4i32 + { 6, OperandInfo337 }, // Inst #2921 = VMLSv8i16 + { 6, OperandInfo338 }, // Inst #2922 = VMLSv8i8 + { 4, OperandInfo162 }, // Inst #2923 = VMMLA + { 4, OperandInfo342 }, // Inst #2924 = VMOVD + { 5, OperandInfo436 }, // Inst #2925 = VMOVDRR + { 2, OperandInfo369 }, // Inst #2926 = VMOVH + { 4, OperandInfo437 }, // Inst #2927 = VMOVHR + { 4, OperandInfo375 }, // Inst #2928 = VMOVLsv2i64 + { 4, OperandInfo375 }, // Inst #2929 = VMOVLsv4i32 + { 4, OperandInfo375 }, // Inst #2930 = VMOVLsv8i16 + { 4, OperandInfo375 }, // Inst #2931 = VMOVLuv2i64 + { 4, OperandInfo375 }, // Inst #2932 = VMOVLuv4i32 + { 4, OperandInfo375 }, // Inst #2933 = VMOVLuv8i16 + { 4, OperandInfo163 }, // Inst #2934 = VMOVNv2i32 + { 4, OperandInfo163 }, // Inst #2935 = VMOVNv4i16 + { 4, OperandInfo163 }, // Inst #2936 = VMOVNv8i8 + { 4, OperandInfo438 }, // Inst #2937 = VMOVRH + { 5, OperandInfo439 }, // Inst #2938 = VMOVRRD + { 6, OperandInfo440 }, // Inst #2939 = VMOVRRS + { 4, OperandInfo441 }, // Inst #2940 = VMOVRS + { 4, OperandInfo344 }, // Inst #2941 = VMOVS + { 4, OperandInfo442 }, // Inst #2942 = VMOVSR + { 6, OperandInfo443 }, // Inst #2943 = VMOVSRR + { 4, OperandInfo444 }, // Inst #2944 = VMOVv16i8 + { 4, OperandInfo203 }, // Inst #2945 = VMOVv1i64 + { 4, OperandInfo203 }, // Inst #2946 = VMOVv2f32 + { 4, OperandInfo203 }, // Inst #2947 = VMOVv2i32 + { 4, OperandInfo444 }, // Inst #2948 = VMOVv2i64 + { 4, OperandInfo444 }, // Inst #2949 = VMOVv4f32 + { 4, OperandInfo203 }, // Inst #2950 = VMOVv4i16 + { 4, OperandInfo444 }, // Inst #2951 = VMOVv4i32 + { 4, OperandInfo444 }, // Inst #2952 = VMOVv8i16 + { 4, OperandInfo203 }, // Inst #2953 = VMOVv8i8 + { 3, OperandInfo239 }, // Inst #2954 = VMRS + { 3, OperandInfo137 }, // Inst #2955 = VMRS_FPCXTNS + { 3, OperandInfo137 }, // Inst #2956 = VMRS_FPCXTS + { 3, OperandInfo239 }, // Inst #2957 = VMRS_FPEXC + { 3, OperandInfo239 }, // Inst #2958 = VMRS_FPINST + { 3, OperandInfo239 }, // Inst #2959 = VMRS_FPINST2 + { 4, OperandInfo445 }, // Inst #2960 = VMRS_FPSCR_NZCVQC + { 3, OperandInfo239 }, // Inst #2961 = VMRS_FPSID + { 3, OperandInfo239 }, // Inst #2962 = VMRS_MVFR0 + { 3, OperandInfo239 }, // Inst #2963 = VMRS_MVFR1 + { 3, OperandInfo239 }, // Inst #2964 = VMRS_MVFR2 + { 4, OperandInfo446 }, // Inst #2965 = VMRS_P0 + { 3, OperandInfo137 }, // Inst #2966 = VMRS_VPR + { 3, OperandInfo239 }, // Inst #2967 = VMSR + { 3, OperandInfo137 }, // Inst #2968 = VMSR_FPCXTNS + { 3, OperandInfo137 }, // Inst #2969 = VMSR_FPCXTS + { 3, OperandInfo239 }, // Inst #2970 = VMSR_FPEXC + { 3, OperandInfo239 }, // Inst #2971 = VMSR_FPINST + { 3, OperandInfo239 }, // Inst #2972 = VMSR_FPINST2 + { 4, OperandInfo447 }, // Inst #2973 = VMSR_FPSCR_NZCVQC + { 3, OperandInfo239 }, // Inst #2974 = VMSR_FPSID + { 4, OperandInfo448 }, // Inst #2975 = VMSR_P0 + { 3, OperandInfo137 }, // Inst #2976 = VMSR_VPR + { 5, OperandInfo340 }, // Inst #2977 = VMULD + { 5, OperandInfo346 }, // Inst #2978 = VMULH + { 3, OperandInfo384 }, // Inst #2979 = VMULLp64 + { 5, OperandInfo339 }, // Inst #2980 = VMULLp8 + { 6, OperandInfo449 }, // Inst #2981 = VMULLslsv2i32 + { 6, OperandInfo450 }, // Inst #2982 = VMULLslsv4i16 + { 6, OperandInfo449 }, // Inst #2983 = VMULLsluv2i32 + { 6, OperandInfo450 }, // Inst #2984 = VMULLsluv4i16 + { 5, OperandInfo339 }, // Inst #2985 = VMULLsv2i64 + { 5, OperandInfo339 }, // Inst #2986 = VMULLsv4i32 + { 5, OperandInfo339 }, // Inst #2987 = VMULLsv8i16 + { 5, OperandInfo339 }, // Inst #2988 = VMULLuv2i64 + { 5, OperandInfo339 }, // Inst #2989 = VMULLuv4i32 + { 5, OperandInfo339 }, // Inst #2990 = VMULLuv8i16 + { 5, OperandInfo348 }, // Inst #2991 = VMULS + { 5, OperandInfo340 }, // Inst #2992 = VMULfd + { 5, OperandInfo341 }, // Inst #2993 = VMULfq + { 5, OperandInfo340 }, // Inst #2994 = VMULhd + { 5, OperandInfo341 }, // Inst #2995 = VMULhq + { 5, OperandInfo340 }, // Inst #2996 = VMULpd + { 5, OperandInfo341 }, // Inst #2997 = VMULpq + { 6, OperandInfo451 }, // Inst #2998 = VMULslfd + { 6, OperandInfo452 }, // Inst #2999 = VMULslfq + { 6, OperandInfo453 }, // Inst #3000 = VMULslhd + { 6, OperandInfo454 }, // Inst #3001 = VMULslhq + { 6, OperandInfo451 }, // Inst #3002 = VMULslv2i32 + { 6, OperandInfo453 }, // Inst #3003 = VMULslv4i16 + { 6, OperandInfo452 }, // Inst #3004 = VMULslv4i32 + { 6, OperandInfo454 }, // Inst #3005 = VMULslv8i16 + { 5, OperandInfo341 }, // Inst #3006 = VMULv16i8 + { 5, OperandInfo340 }, // Inst #3007 = VMULv2i32 + { 5, OperandInfo340 }, // Inst #3008 = VMULv4i16 + { 5, OperandInfo341 }, // Inst #3009 = VMULv4i32 + { 5, OperandInfo341 }, // Inst #3010 = VMULv8i16 + { 5, OperandInfo340 }, // Inst #3011 = VMULv8i8 + { 4, OperandInfo342 }, // Inst #3012 = VMVNd + { 4, OperandInfo345 }, // Inst #3013 = VMVNq + { 4, OperandInfo203 }, // Inst #3014 = VMVNv2i32 + { 4, OperandInfo203 }, // Inst #3015 = VMVNv4i16 + { 4, OperandInfo444 }, // Inst #3016 = VMVNv4i32 + { 4, OperandInfo444 }, // Inst #3017 = VMVNv8i16 + { 4, OperandInfo342 }, // Inst #3018 = VNEGD + { 4, OperandInfo343 }, // Inst #3019 = VNEGH + { 4, OperandInfo344 }, // Inst #3020 = VNEGS + { 4, OperandInfo345 }, // Inst #3021 = VNEGf32q + { 4, OperandInfo342 }, // Inst #3022 = VNEGfd + { 4, OperandInfo342 }, // Inst #3023 = VNEGhd + { 4, OperandInfo345 }, // Inst #3024 = VNEGhq + { 4, OperandInfo342 }, // Inst #3025 = VNEGs16d + { 4, OperandInfo345 }, // Inst #3026 = VNEGs16q + { 4, OperandInfo342 }, // Inst #3027 = VNEGs32d + { 4, OperandInfo345 }, // Inst #3028 = VNEGs32q + { 4, OperandInfo342 }, // Inst #3029 = VNEGs8d + { 4, OperandInfo345 }, // Inst #3030 = VNEGs8q + { 6, OperandInfo338 }, // Inst #3031 = VNMLAD + { 6, OperandInfo381 }, // Inst #3032 = VNMLAH + { 6, OperandInfo386 }, // Inst #3033 = VNMLAS + { 6, OperandInfo338 }, // Inst #3034 = VNMLSD + { 6, OperandInfo381 }, // Inst #3035 = VNMLSH + { 6, OperandInfo386 }, // Inst #3036 = VNMLSS + { 5, OperandInfo340 }, // Inst #3037 = VNMULD + { 5, OperandInfo346 }, // Inst #3038 = VNMULH + { 5, OperandInfo348 }, // Inst #3039 = VNMULS + { 5, OperandInfo340 }, // Inst #3040 = VORNd + { 5, OperandInfo341 }, // Inst #3041 = VORNq + { 5, OperandInfo340 }, // Inst #3042 = VORRd + { 5, OperandInfo351 }, // Inst #3043 = VORRiv2i32 + { 5, OperandInfo351 }, // Inst #3044 = VORRiv4i16 + { 5, OperandInfo352 }, // Inst #3045 = VORRiv4i32 + { 5, OperandInfo352 }, // Inst #3046 = VORRiv8i16 + { 5, OperandInfo341 }, // Inst #3047 = VORRq + { 5, OperandInfo455 }, // Inst #3048 = VPADALsv16i8 + { 5, OperandInfo102 }, // Inst #3049 = VPADALsv2i32 + { 5, OperandInfo102 }, // Inst #3050 = VPADALsv4i16 + { 5, OperandInfo455 }, // Inst #3051 = VPADALsv4i32 + { 5, OperandInfo455 }, // Inst #3052 = VPADALsv8i16 + { 5, OperandInfo102 }, // Inst #3053 = VPADALsv8i8 + { 5, OperandInfo455 }, // Inst #3054 = VPADALuv16i8 + { 5, OperandInfo102 }, // Inst #3055 = VPADALuv2i32 + { 5, OperandInfo102 }, // Inst #3056 = VPADALuv4i16 + { 5, OperandInfo455 }, // Inst #3057 = VPADALuv4i32 + { 5, OperandInfo455 }, // Inst #3058 = VPADALuv8i16 + { 5, OperandInfo102 }, // Inst #3059 = VPADALuv8i8 + { 4, OperandInfo345 }, // Inst #3060 = VPADDLsv16i8 + { 4, OperandInfo342 }, // Inst #3061 = VPADDLsv2i32 + { 4, OperandInfo342 }, // Inst #3062 = VPADDLsv4i16 + { 4, OperandInfo345 }, // Inst #3063 = VPADDLsv4i32 + { 4, OperandInfo345 }, // Inst #3064 = VPADDLsv8i16 + { 4, OperandInfo342 }, // Inst #3065 = VPADDLsv8i8 + { 4, OperandInfo345 }, // Inst #3066 = VPADDLuv16i8 + { 4, OperandInfo342 }, // Inst #3067 = VPADDLuv2i32 + { 4, OperandInfo342 }, // Inst #3068 = VPADDLuv4i16 + { 4, OperandInfo345 }, // Inst #3069 = VPADDLuv4i32 + { 4, OperandInfo345 }, // Inst #3070 = VPADDLuv8i16 + { 4, OperandInfo342 }, // Inst #3071 = VPADDLuv8i8 + { 5, OperandInfo340 }, // Inst #3072 = VPADDf + { 5, OperandInfo340 }, // Inst #3073 = VPADDh + { 5, OperandInfo340 }, // Inst #3074 = VPADDi16 + { 5, OperandInfo340 }, // Inst #3075 = VPADDi32 + { 5, OperandInfo340 }, // Inst #3076 = VPADDi8 + { 5, OperandInfo340 }, // Inst #3077 = VPMAXf + { 5, OperandInfo340 }, // Inst #3078 = VPMAXh + { 5, OperandInfo340 }, // Inst #3079 = VPMAXs16 + { 5, OperandInfo340 }, // Inst #3080 = VPMAXs32 + { 5, OperandInfo340 }, // Inst #3081 = VPMAXs8 + { 5, OperandInfo340 }, // Inst #3082 = VPMAXu16 + { 5, OperandInfo340 }, // Inst #3083 = VPMAXu32 + { 5, OperandInfo340 }, // Inst #3084 = VPMAXu8 + { 5, OperandInfo340 }, // Inst #3085 = VPMINf + { 5, OperandInfo340 }, // Inst #3086 = VPMINh + { 5, OperandInfo340 }, // Inst #3087 = VPMINs16 + { 5, OperandInfo340 }, // Inst #3088 = VPMINs32 + { 5, OperandInfo340 }, // Inst #3089 = VPMINs8 + { 5, OperandInfo340 }, // Inst #3090 = VPMINu16 + { 5, OperandInfo340 }, // Inst #3091 = VPMINu32 + { 5, OperandInfo340 }, // Inst #3092 = VPMINu8 + { 4, OperandInfo345 }, // Inst #3093 = VQABSv16i8 + { 4, OperandInfo342 }, // Inst #3094 = VQABSv2i32 + { 4, OperandInfo342 }, // Inst #3095 = VQABSv4i16 + { 4, OperandInfo345 }, // Inst #3096 = VQABSv4i32 + { 4, OperandInfo345 }, // Inst #3097 = VQABSv8i16 + { 4, OperandInfo342 }, // Inst #3098 = VQABSv8i8 + { 5, OperandInfo341 }, // Inst #3099 = VQADDsv16i8 + { 5, OperandInfo340 }, // Inst #3100 = VQADDsv1i64 + { 5, OperandInfo340 }, // Inst #3101 = VQADDsv2i32 + { 5, OperandInfo341 }, // Inst #3102 = VQADDsv2i64 + { 5, OperandInfo340 }, // Inst #3103 = VQADDsv4i16 + { 5, OperandInfo341 }, // Inst #3104 = VQADDsv4i32 + { 5, OperandInfo341 }, // Inst #3105 = VQADDsv8i16 + { 5, OperandInfo340 }, // Inst #3106 = VQADDsv8i8 + { 5, OperandInfo341 }, // Inst #3107 = VQADDuv16i8 + { 5, OperandInfo340 }, // Inst #3108 = VQADDuv1i64 + { 5, OperandInfo340 }, // Inst #3109 = VQADDuv2i32 + { 5, OperandInfo341 }, // Inst #3110 = VQADDuv2i64 + { 5, OperandInfo340 }, // Inst #3111 = VQADDuv4i16 + { 5, OperandInfo341 }, // Inst #3112 = VQADDuv4i32 + { 5, OperandInfo341 }, // Inst #3113 = VQADDuv8i16 + { 5, OperandInfo340 }, // Inst #3114 = VQADDuv8i8 + { 7, OperandInfo430 }, // Inst #3115 = VQDMLALslv2i32 + { 7, OperandInfo431 }, // Inst #3116 = VQDMLALslv4i16 + { 6, OperandInfo336 }, // Inst #3117 = VQDMLALv2i64 + { 6, OperandInfo336 }, // Inst #3118 = VQDMLALv4i32 + { 7, OperandInfo430 }, // Inst #3119 = VQDMLSLslv2i32 + { 7, OperandInfo431 }, // Inst #3120 = VQDMLSLslv4i16 + { 6, OperandInfo336 }, // Inst #3121 = VQDMLSLv2i64 + { 6, OperandInfo336 }, // Inst #3122 = VQDMLSLv4i32 + { 6, OperandInfo451 }, // Inst #3123 = VQDMULHslv2i32 + { 6, OperandInfo453 }, // Inst #3124 = VQDMULHslv4i16 + { 6, OperandInfo452 }, // Inst #3125 = VQDMULHslv4i32 + { 6, OperandInfo454 }, // Inst #3126 = VQDMULHslv8i16 + { 5, OperandInfo340 }, // Inst #3127 = VQDMULHv2i32 + { 5, OperandInfo340 }, // Inst #3128 = VQDMULHv4i16 + { 5, OperandInfo341 }, // Inst #3129 = VQDMULHv4i32 + { 5, OperandInfo341 }, // Inst #3130 = VQDMULHv8i16 + { 6, OperandInfo449 }, // Inst #3131 = VQDMULLslv2i32 + { 6, OperandInfo450 }, // Inst #3132 = VQDMULLslv4i16 + { 5, OperandInfo339 }, // Inst #3133 = VQDMULLv2i64 + { 5, OperandInfo339 }, // Inst #3134 = VQDMULLv4i32 + { 4, OperandInfo163 }, // Inst #3135 = VQMOVNsuv2i32 + { 4, OperandInfo163 }, // Inst #3136 = VQMOVNsuv4i16 + { 4, OperandInfo163 }, // Inst #3137 = VQMOVNsuv8i8 + { 4, OperandInfo163 }, // Inst #3138 = VQMOVNsv2i32 + { 4, OperandInfo163 }, // Inst #3139 = VQMOVNsv4i16 + { 4, OperandInfo163 }, // Inst #3140 = VQMOVNsv8i8 + { 4, OperandInfo163 }, // Inst #3141 = VQMOVNuv2i32 + { 4, OperandInfo163 }, // Inst #3142 = VQMOVNuv4i16 + { 4, OperandInfo163 }, // Inst #3143 = VQMOVNuv8i8 + { 4, OperandInfo345 }, // Inst #3144 = VQNEGv16i8 + { 4, OperandInfo342 }, // Inst #3145 = VQNEGv2i32 + { 4, OperandInfo342 }, // Inst #3146 = VQNEGv4i16 + { 4, OperandInfo345 }, // Inst #3147 = VQNEGv4i32 + { 4, OperandInfo345 }, // Inst #3148 = VQNEGv8i16 + { 4, OperandInfo342 }, // Inst #3149 = VQNEGv8i8 + { 7, OperandInfo432 }, // Inst #3150 = VQRDMLAHslv2i32 + { 7, OperandInfo434 }, // Inst #3151 = VQRDMLAHslv4i16 + { 7, OperandInfo433 }, // Inst #3152 = VQRDMLAHslv4i32 + { 7, OperandInfo435 }, // Inst #3153 = VQRDMLAHslv8i16 + { 6, OperandInfo338 }, // Inst #3154 = VQRDMLAHv2i32 + { 6, OperandInfo338 }, // Inst #3155 = VQRDMLAHv4i16 + { 6, OperandInfo337 }, // Inst #3156 = VQRDMLAHv4i32 + { 6, OperandInfo337 }, // Inst #3157 = VQRDMLAHv8i16 + { 7, OperandInfo432 }, // Inst #3158 = VQRDMLSHslv2i32 + { 7, OperandInfo434 }, // Inst #3159 = VQRDMLSHslv4i16 + { 7, OperandInfo433 }, // Inst #3160 = VQRDMLSHslv4i32 + { 7, OperandInfo435 }, // Inst #3161 = VQRDMLSHslv8i16 + { 6, OperandInfo338 }, // Inst #3162 = VQRDMLSHv2i32 + { 6, OperandInfo338 }, // Inst #3163 = VQRDMLSHv4i16 + { 6, OperandInfo337 }, // Inst #3164 = VQRDMLSHv4i32 + { 6, OperandInfo337 }, // Inst #3165 = VQRDMLSHv8i16 + { 6, OperandInfo451 }, // Inst #3166 = VQRDMULHslv2i32 + { 6, OperandInfo453 }, // Inst #3167 = VQRDMULHslv4i16 + { 6, OperandInfo452 }, // Inst #3168 = VQRDMULHslv4i32 + { 6, OperandInfo454 }, // Inst #3169 = VQRDMULHslv8i16 + { 5, OperandInfo340 }, // Inst #3170 = VQRDMULHv2i32 + { 5, OperandInfo340 }, // Inst #3171 = VQRDMULHv4i16 + { 5, OperandInfo341 }, // Inst #3172 = VQRDMULHv4i32 + { 5, OperandInfo341 }, // Inst #3173 = VQRDMULHv8i16 + { 5, OperandInfo341 }, // Inst #3174 = VQRSHLsv16i8 + { 5, OperandInfo340 }, // Inst #3175 = VQRSHLsv1i64 + { 5, OperandInfo340 }, // Inst #3176 = VQRSHLsv2i32 + { 5, OperandInfo341 }, // Inst #3177 = VQRSHLsv2i64 + { 5, OperandInfo340 }, // Inst #3178 = VQRSHLsv4i16 + { 5, OperandInfo341 }, // Inst #3179 = VQRSHLsv4i32 + { 5, OperandInfo341 }, // Inst #3180 = VQRSHLsv8i16 + { 5, OperandInfo340 }, // Inst #3181 = VQRSHLsv8i8 + { 5, OperandInfo341 }, // Inst #3182 = VQRSHLuv16i8 + { 5, OperandInfo340 }, // Inst #3183 = VQRSHLuv1i64 + { 5, OperandInfo340 }, // Inst #3184 = VQRSHLuv2i32 + { 5, OperandInfo341 }, // Inst #3185 = VQRSHLuv2i64 + { 5, OperandInfo340 }, // Inst #3186 = VQRSHLuv4i16 + { 5, OperandInfo341 }, // Inst #3187 = VQRSHLuv4i32 + { 5, OperandInfo341 }, // Inst #3188 = VQRSHLuv8i16 + { 5, OperandInfo340 }, // Inst #3189 = VQRSHLuv8i8 + { 5, OperandInfo456 }, // Inst #3190 = VQRSHRNsv2i32 + { 5, OperandInfo456 }, // Inst #3191 = VQRSHRNsv4i16 + { 5, OperandInfo456 }, // Inst #3192 = VQRSHRNsv8i8 + { 5, OperandInfo456 }, // Inst #3193 = VQRSHRNuv2i32 + { 5, OperandInfo456 }, // Inst #3194 = VQRSHRNuv4i16 + { 5, OperandInfo456 }, // Inst #3195 = VQRSHRNuv8i8 + { 5, OperandInfo456 }, // Inst #3196 = VQRSHRUNv2i32 + { 5, OperandInfo456 }, // Inst #3197 = VQRSHRUNv4i16 + { 5, OperandInfo456 }, // Inst #3198 = VQRSHRUNv8i8 + { 5, OperandInfo457 }, // Inst #3199 = VQSHLsiv16i8 + { 5, OperandInfo458 }, // Inst #3200 = VQSHLsiv1i64 + { 5, OperandInfo458 }, // Inst #3201 = VQSHLsiv2i32 + { 5, OperandInfo457 }, // Inst #3202 = VQSHLsiv2i64 + { 5, OperandInfo458 }, // Inst #3203 = VQSHLsiv4i16 + { 5, OperandInfo457 }, // Inst #3204 = VQSHLsiv4i32 + { 5, OperandInfo457 }, // Inst #3205 = VQSHLsiv8i16 + { 5, OperandInfo458 }, // Inst #3206 = VQSHLsiv8i8 + { 5, OperandInfo457 }, // Inst #3207 = VQSHLsuv16i8 + { 5, OperandInfo458 }, // Inst #3208 = VQSHLsuv1i64 + { 5, OperandInfo458 }, // Inst #3209 = VQSHLsuv2i32 + { 5, OperandInfo457 }, // Inst #3210 = VQSHLsuv2i64 + { 5, OperandInfo458 }, // Inst #3211 = VQSHLsuv4i16 + { 5, OperandInfo457 }, // Inst #3212 = VQSHLsuv4i32 + { 5, OperandInfo457 }, // Inst #3213 = VQSHLsuv8i16 + { 5, OperandInfo458 }, // Inst #3214 = VQSHLsuv8i8 + { 5, OperandInfo341 }, // Inst #3215 = VQSHLsv16i8 + { 5, OperandInfo340 }, // Inst #3216 = VQSHLsv1i64 + { 5, OperandInfo340 }, // Inst #3217 = VQSHLsv2i32 + { 5, OperandInfo341 }, // Inst #3218 = VQSHLsv2i64 + { 5, OperandInfo340 }, // Inst #3219 = VQSHLsv4i16 + { 5, OperandInfo341 }, // Inst #3220 = VQSHLsv4i32 + { 5, OperandInfo341 }, // Inst #3221 = VQSHLsv8i16 + { 5, OperandInfo340 }, // Inst #3222 = VQSHLsv8i8 + { 5, OperandInfo457 }, // Inst #3223 = VQSHLuiv16i8 + { 5, OperandInfo458 }, // Inst #3224 = VQSHLuiv1i64 + { 5, OperandInfo458 }, // Inst #3225 = VQSHLuiv2i32 + { 5, OperandInfo457 }, // Inst #3226 = VQSHLuiv2i64 + { 5, OperandInfo458 }, // Inst #3227 = VQSHLuiv4i16 + { 5, OperandInfo457 }, // Inst #3228 = VQSHLuiv4i32 + { 5, OperandInfo457 }, // Inst #3229 = VQSHLuiv8i16 + { 5, OperandInfo458 }, // Inst #3230 = VQSHLuiv8i8 + { 5, OperandInfo341 }, // Inst #3231 = VQSHLuv16i8 + { 5, OperandInfo340 }, // Inst #3232 = VQSHLuv1i64 + { 5, OperandInfo340 }, // Inst #3233 = VQSHLuv2i32 + { 5, OperandInfo341 }, // Inst #3234 = VQSHLuv2i64 + { 5, OperandInfo340 }, // Inst #3235 = VQSHLuv4i16 + { 5, OperandInfo341 }, // Inst #3236 = VQSHLuv4i32 + { 5, OperandInfo341 }, // Inst #3237 = VQSHLuv8i16 + { 5, OperandInfo340 }, // Inst #3238 = VQSHLuv8i8 + { 5, OperandInfo456 }, // Inst #3239 = VQSHRNsv2i32 + { 5, OperandInfo456 }, // Inst #3240 = VQSHRNsv4i16 + { 5, OperandInfo456 }, // Inst #3241 = VQSHRNsv8i8 + { 5, OperandInfo456 }, // Inst #3242 = VQSHRNuv2i32 + { 5, OperandInfo456 }, // Inst #3243 = VQSHRNuv4i16 + { 5, OperandInfo456 }, // Inst #3244 = VQSHRNuv8i8 + { 5, OperandInfo456 }, // Inst #3245 = VQSHRUNv2i32 + { 5, OperandInfo456 }, // Inst #3246 = VQSHRUNv4i16 + { 5, OperandInfo456 }, // Inst #3247 = VQSHRUNv8i8 + { 5, OperandInfo341 }, // Inst #3248 = VQSUBsv16i8 + { 5, OperandInfo340 }, // Inst #3249 = VQSUBsv1i64 + { 5, OperandInfo340 }, // Inst #3250 = VQSUBsv2i32 + { 5, OperandInfo341 }, // Inst #3251 = VQSUBsv2i64 + { 5, OperandInfo340 }, // Inst #3252 = VQSUBsv4i16 + { 5, OperandInfo341 }, // Inst #3253 = VQSUBsv4i32 + { 5, OperandInfo341 }, // Inst #3254 = VQSUBsv8i16 + { 5, OperandInfo340 }, // Inst #3255 = VQSUBsv8i8 + { 5, OperandInfo341 }, // Inst #3256 = VQSUBuv16i8 + { 5, OperandInfo340 }, // Inst #3257 = VQSUBuv1i64 + { 5, OperandInfo340 }, // Inst #3258 = VQSUBuv2i32 + { 5, OperandInfo341 }, // Inst #3259 = VQSUBuv2i64 + { 5, OperandInfo340 }, // Inst #3260 = VQSUBuv4i16 + { 5, OperandInfo341 }, // Inst #3261 = VQSUBuv4i32 + { 5, OperandInfo341 }, // Inst #3262 = VQSUBuv8i16 + { 5, OperandInfo340 }, // Inst #3263 = VQSUBuv8i8 + { 5, OperandInfo347 }, // Inst #3264 = VRADDHNv2i32 + { 5, OperandInfo347 }, // Inst #3265 = VRADDHNv4i16 + { 5, OperandInfo347 }, // Inst #3266 = VRADDHNv8i8 + { 4, OperandInfo342 }, // Inst #3267 = VRECPEd + { 4, OperandInfo342 }, // Inst #3268 = VRECPEfd + { 4, OperandInfo345 }, // Inst #3269 = VRECPEfq + { 4, OperandInfo342 }, // Inst #3270 = VRECPEhd + { 4, OperandInfo345 }, // Inst #3271 = VRECPEhq + { 4, OperandInfo345 }, // Inst #3272 = VRECPEq + { 5, OperandInfo340 }, // Inst #3273 = VRECPSfd + { 5, OperandInfo341 }, // Inst #3274 = VRECPSfq + { 5, OperandInfo340 }, // Inst #3275 = VRECPShd + { 5, OperandInfo341 }, // Inst #3276 = VRECPShq + { 4, OperandInfo342 }, // Inst #3277 = VREV16d8 + { 4, OperandInfo345 }, // Inst #3278 = VREV16q8 + { 4, OperandInfo342 }, // Inst #3279 = VREV32d16 + { 4, OperandInfo342 }, // Inst #3280 = VREV32d8 + { 4, OperandInfo345 }, // Inst #3281 = VREV32q16 + { 4, OperandInfo345 }, // Inst #3282 = VREV32q8 + { 4, OperandInfo342 }, // Inst #3283 = VREV64d16 + { 4, OperandInfo342 }, // Inst #3284 = VREV64d32 + { 4, OperandInfo342 }, // Inst #3285 = VREV64d8 + { 4, OperandInfo345 }, // Inst #3286 = VREV64q16 + { 4, OperandInfo345 }, // Inst #3287 = VREV64q32 + { 4, OperandInfo345 }, // Inst #3288 = VREV64q8 + { 5, OperandInfo341 }, // Inst #3289 = VRHADDsv16i8 + { 5, OperandInfo340 }, // Inst #3290 = VRHADDsv2i32 + { 5, OperandInfo340 }, // Inst #3291 = VRHADDsv4i16 + { 5, OperandInfo341 }, // Inst #3292 = VRHADDsv4i32 + { 5, OperandInfo341 }, // Inst #3293 = VRHADDsv8i16 + { 5, OperandInfo340 }, // Inst #3294 = VRHADDsv8i8 + { 5, OperandInfo341 }, // Inst #3295 = VRHADDuv16i8 + { 5, OperandInfo340 }, // Inst #3296 = VRHADDuv2i32 + { 5, OperandInfo340 }, // Inst #3297 = VRHADDuv4i16 + { 5, OperandInfo341 }, // Inst #3298 = VRHADDuv4i32 + { 5, OperandInfo341 }, // Inst #3299 = VRHADDuv8i16 + { 5, OperandInfo340 }, // Inst #3300 = VRHADDuv8i8 + { 2, OperandInfo366 }, // Inst #3301 = VRINTAD + { 2, OperandInfo459 }, // Inst #3302 = VRINTAH + { 2, OperandInfo366 }, // Inst #3303 = VRINTANDf + { 2, OperandInfo366 }, // Inst #3304 = VRINTANDh + { 2, OperandInfo158 }, // Inst #3305 = VRINTANQf + { 2, OperandInfo158 }, // Inst #3306 = VRINTANQh + { 2, OperandInfo369 }, // Inst #3307 = VRINTAS + { 2, OperandInfo366 }, // Inst #3308 = VRINTMD + { 2, OperandInfo459 }, // Inst #3309 = VRINTMH + { 2, OperandInfo366 }, // Inst #3310 = VRINTMNDf + { 2, OperandInfo366 }, // Inst #3311 = VRINTMNDh + { 2, OperandInfo158 }, // Inst #3312 = VRINTMNQf + { 2, OperandInfo158 }, // Inst #3313 = VRINTMNQh + { 2, OperandInfo369 }, // Inst #3314 = VRINTMS + { 2, OperandInfo366 }, // Inst #3315 = VRINTND + { 2, OperandInfo459 }, // Inst #3316 = VRINTNH + { 2, OperandInfo366 }, // Inst #3317 = VRINTNNDf + { 2, OperandInfo366 }, // Inst #3318 = VRINTNNDh + { 2, OperandInfo158 }, // Inst #3319 = VRINTNNQf + { 2, OperandInfo158 }, // Inst #3320 = VRINTNNQh + { 2, OperandInfo369 }, // Inst #3321 = VRINTNS + { 2, OperandInfo366 }, // Inst #3322 = VRINTPD + { 2, OperandInfo459 }, // Inst #3323 = VRINTPH + { 2, OperandInfo366 }, // Inst #3324 = VRINTPNDf + { 2, OperandInfo366 }, // Inst #3325 = VRINTPNDh + { 2, OperandInfo158 }, // Inst #3326 = VRINTPNQf + { 2, OperandInfo158 }, // Inst #3327 = VRINTPNQh + { 2, OperandInfo369 }, // Inst #3328 = VRINTPS + { 4, OperandInfo342 }, // Inst #3329 = VRINTRD + { 4, OperandInfo343 }, // Inst #3330 = VRINTRH + { 4, OperandInfo344 }, // Inst #3331 = VRINTRS + { 4, OperandInfo342 }, // Inst #3332 = VRINTXD + { 4, OperandInfo343 }, // Inst #3333 = VRINTXH + { 2, OperandInfo366 }, // Inst #3334 = VRINTXNDf + { 2, OperandInfo366 }, // Inst #3335 = VRINTXNDh + { 2, OperandInfo158 }, // Inst #3336 = VRINTXNQf + { 2, OperandInfo158 }, // Inst #3337 = VRINTXNQh + { 4, OperandInfo344 }, // Inst #3338 = VRINTXS + { 4, OperandInfo342 }, // Inst #3339 = VRINTZD + { 4, OperandInfo343 }, // Inst #3340 = VRINTZH + { 2, OperandInfo366 }, // Inst #3341 = VRINTZNDf + { 2, OperandInfo366 }, // Inst #3342 = VRINTZNDh + { 2, OperandInfo158 }, // Inst #3343 = VRINTZNQf + { 2, OperandInfo158 }, // Inst #3344 = VRINTZNQh + { 4, OperandInfo344 }, // Inst #3345 = VRINTZS + { 5, OperandInfo341 }, // Inst #3346 = VRSHLsv16i8 + { 5, OperandInfo340 }, // Inst #3347 = VRSHLsv1i64 + { 5, OperandInfo340 }, // Inst #3348 = VRSHLsv2i32 + { 5, OperandInfo341 }, // Inst #3349 = VRSHLsv2i64 + { 5, OperandInfo340 }, // Inst #3350 = VRSHLsv4i16 + { 5, OperandInfo341 }, // Inst #3351 = VRSHLsv4i32 + { 5, OperandInfo341 }, // Inst #3352 = VRSHLsv8i16 + { 5, OperandInfo340 }, // Inst #3353 = VRSHLsv8i8 + { 5, OperandInfo341 }, // Inst #3354 = VRSHLuv16i8 + { 5, OperandInfo340 }, // Inst #3355 = VRSHLuv1i64 + { 5, OperandInfo340 }, // Inst #3356 = VRSHLuv2i32 + { 5, OperandInfo341 }, // Inst #3357 = VRSHLuv2i64 + { 5, OperandInfo340 }, // Inst #3358 = VRSHLuv4i16 + { 5, OperandInfo341 }, // Inst #3359 = VRSHLuv4i32 + { 5, OperandInfo341 }, // Inst #3360 = VRSHLuv8i16 + { 5, OperandInfo340 }, // Inst #3361 = VRSHLuv8i8 + { 5, OperandInfo456 }, // Inst #3362 = VRSHRNv2i32 + { 5, OperandInfo456 }, // Inst #3363 = VRSHRNv4i16 + { 5, OperandInfo456 }, // Inst #3364 = VRSHRNv8i8 + { 5, OperandInfo374 }, // Inst #3365 = VRSHRsv16i8 + { 5, OperandInfo373 }, // Inst #3366 = VRSHRsv1i64 + { 5, OperandInfo373 }, // Inst #3367 = VRSHRsv2i32 + { 5, OperandInfo374 }, // Inst #3368 = VRSHRsv2i64 + { 5, OperandInfo373 }, // Inst #3369 = VRSHRsv4i16 + { 5, OperandInfo374 }, // Inst #3370 = VRSHRsv4i32 + { 5, OperandInfo374 }, // Inst #3371 = VRSHRsv8i16 + { 5, OperandInfo373 }, // Inst #3372 = VRSHRsv8i8 + { 5, OperandInfo374 }, // Inst #3373 = VRSHRuv16i8 + { 5, OperandInfo373 }, // Inst #3374 = VRSHRuv1i64 + { 5, OperandInfo373 }, // Inst #3375 = VRSHRuv2i32 + { 5, OperandInfo374 }, // Inst #3376 = VRSHRuv2i64 + { 5, OperandInfo373 }, // Inst #3377 = VRSHRuv4i16 + { 5, OperandInfo374 }, // Inst #3378 = VRSHRuv4i32 + { 5, OperandInfo374 }, // Inst #3379 = VRSHRuv8i16 + { 5, OperandInfo373 }, // Inst #3380 = VRSHRuv8i8 + { 4, OperandInfo342 }, // Inst #3381 = VRSQRTEd + { 4, OperandInfo342 }, // Inst #3382 = VRSQRTEfd + { 4, OperandInfo345 }, // Inst #3383 = VRSQRTEfq + { 4, OperandInfo342 }, // Inst #3384 = VRSQRTEhd + { 4, OperandInfo345 }, // Inst #3385 = VRSQRTEhq + { 4, OperandInfo345 }, // Inst #3386 = VRSQRTEq + { 5, OperandInfo340 }, // Inst #3387 = VRSQRTSfd + { 5, OperandInfo341 }, // Inst #3388 = VRSQRTSfq + { 5, OperandInfo340 }, // Inst #3389 = VRSQRTShd + { 5, OperandInfo341 }, // Inst #3390 = VRSQRTShq + { 6, OperandInfo460 }, // Inst #3391 = VRSRAsv16i8 + { 6, OperandInfo461 }, // Inst #3392 = VRSRAsv1i64 + { 6, OperandInfo461 }, // Inst #3393 = VRSRAsv2i32 + { 6, OperandInfo460 }, // Inst #3394 = VRSRAsv2i64 + { 6, OperandInfo461 }, // Inst #3395 = VRSRAsv4i16 + { 6, OperandInfo460 }, // Inst #3396 = VRSRAsv4i32 + { 6, OperandInfo460 }, // Inst #3397 = VRSRAsv8i16 + { 6, OperandInfo461 }, // Inst #3398 = VRSRAsv8i8 + { 6, OperandInfo460 }, // Inst #3399 = VRSRAuv16i8 + { 6, OperandInfo461 }, // Inst #3400 = VRSRAuv1i64 + { 6, OperandInfo461 }, // Inst #3401 = VRSRAuv2i32 + { 6, OperandInfo460 }, // Inst #3402 = VRSRAuv2i64 + { 6, OperandInfo461 }, // Inst #3403 = VRSRAuv4i16 + { 6, OperandInfo460 }, // Inst #3404 = VRSRAuv4i32 + { 6, OperandInfo460 }, // Inst #3405 = VRSRAuv8i16 + { 6, OperandInfo461 }, // Inst #3406 = VRSRAuv8i8 + { 5, OperandInfo347 }, // Inst #3407 = VRSUBHNv2i32 + { 5, OperandInfo347 }, // Inst #3408 = VRSUBHNv4i16 + { 5, OperandInfo347 }, // Inst #3409 = VRSUBHNv8i8 + { 3, OperandInfo150 }, // Inst #3410 = VSCCLRMD + { 3, OperandInfo150 }, // Inst #3411 = VSCCLRMS + { 4, OperandInfo161 }, // Inst #3412 = VSDOTD + { 5, OperandInfo159 }, // Inst #3413 = VSDOTDI + { 4, OperandInfo162 }, // Inst #3414 = VSDOTQ + { 5, OperandInfo160 }, // Inst #3415 = VSDOTQI + { 3, OperandInfo310 }, // Inst #3416 = VSELEQD + { 3, OperandInfo387 }, // Inst #3417 = VSELEQH + { 3, OperandInfo388 }, // Inst #3418 = VSELEQS + { 3, OperandInfo310 }, // Inst #3419 = VSELGED + { 3, OperandInfo387 }, // Inst #3420 = VSELGEH + { 3, OperandInfo388 }, // Inst #3421 = VSELGES + { 3, OperandInfo310 }, // Inst #3422 = VSELGTD + { 3, OperandInfo387 }, // Inst #3423 = VSELGTH + { 3, OperandInfo388 }, // Inst #3424 = VSELGTS + { 3, OperandInfo310 }, // Inst #3425 = VSELVSD + { 3, OperandInfo387 }, // Inst #3426 = VSELVSH + { 3, OperandInfo388 }, // Inst #3427 = VSELVSS + { 6, OperandInfo462 }, // Inst #3428 = VSETLNi16 + { 6, OperandInfo462 }, // Inst #3429 = VSETLNi32 + { 6, OperandInfo462 }, // Inst #3430 = VSETLNi8 + { 5, OperandInfo378 }, // Inst #3431 = VSHLLi16 + { 5, OperandInfo378 }, // Inst #3432 = VSHLLi32 + { 5, OperandInfo378 }, // Inst #3433 = VSHLLi8 + { 5, OperandInfo378 }, // Inst #3434 = VSHLLsv2i64 + { 5, OperandInfo378 }, // Inst #3435 = VSHLLsv4i32 + { 5, OperandInfo378 }, // Inst #3436 = VSHLLsv8i16 + { 5, OperandInfo378 }, // Inst #3437 = VSHLLuv2i64 + { 5, OperandInfo378 }, // Inst #3438 = VSHLLuv4i32 + { 5, OperandInfo378 }, // Inst #3439 = VSHLLuv8i16 + { 5, OperandInfo457 }, // Inst #3440 = VSHLiv16i8 + { 5, OperandInfo458 }, // Inst #3441 = VSHLiv1i64 + { 5, OperandInfo458 }, // Inst #3442 = VSHLiv2i32 + { 5, OperandInfo457 }, // Inst #3443 = VSHLiv2i64 + { 5, OperandInfo458 }, // Inst #3444 = VSHLiv4i16 + { 5, OperandInfo457 }, // Inst #3445 = VSHLiv4i32 + { 5, OperandInfo457 }, // Inst #3446 = VSHLiv8i16 + { 5, OperandInfo458 }, // Inst #3447 = VSHLiv8i8 + { 5, OperandInfo341 }, // Inst #3448 = VSHLsv16i8 + { 5, OperandInfo340 }, // Inst #3449 = VSHLsv1i64 + { 5, OperandInfo340 }, // Inst #3450 = VSHLsv2i32 + { 5, OperandInfo341 }, // Inst #3451 = VSHLsv2i64 + { 5, OperandInfo340 }, // Inst #3452 = VSHLsv4i16 + { 5, OperandInfo341 }, // Inst #3453 = VSHLsv4i32 + { 5, OperandInfo341 }, // Inst #3454 = VSHLsv8i16 + { 5, OperandInfo340 }, // Inst #3455 = VSHLsv8i8 + { 5, OperandInfo341 }, // Inst #3456 = VSHLuv16i8 + { 5, OperandInfo340 }, // Inst #3457 = VSHLuv1i64 + { 5, OperandInfo340 }, // Inst #3458 = VSHLuv2i32 + { 5, OperandInfo341 }, // Inst #3459 = VSHLuv2i64 + { 5, OperandInfo340 }, // Inst #3460 = VSHLuv4i16 + { 5, OperandInfo341 }, // Inst #3461 = VSHLuv4i32 + { 5, OperandInfo341 }, // Inst #3462 = VSHLuv8i16 + { 5, OperandInfo340 }, // Inst #3463 = VSHLuv8i8 + { 5, OperandInfo456 }, // Inst #3464 = VSHRNv2i32 + { 5, OperandInfo456 }, // Inst #3465 = VSHRNv4i16 + { 5, OperandInfo456 }, // Inst #3466 = VSHRNv8i8 + { 5, OperandInfo374 }, // Inst #3467 = VSHRsv16i8 + { 5, OperandInfo373 }, // Inst #3468 = VSHRsv1i64 + { 5, OperandInfo373 }, // Inst #3469 = VSHRsv2i32 + { 5, OperandInfo374 }, // Inst #3470 = VSHRsv2i64 + { 5, OperandInfo373 }, // Inst #3471 = VSHRsv4i16 + { 5, OperandInfo374 }, // Inst #3472 = VSHRsv4i32 + { 5, OperandInfo374 }, // Inst #3473 = VSHRsv8i16 + { 5, OperandInfo373 }, // Inst #3474 = VSHRsv8i8 + { 5, OperandInfo374 }, // Inst #3475 = VSHRuv16i8 + { 5, OperandInfo373 }, // Inst #3476 = VSHRuv1i64 + { 5, OperandInfo373 }, // Inst #3477 = VSHRuv2i32 + { 5, OperandInfo374 }, // Inst #3478 = VSHRuv2i64 + { 5, OperandInfo373 }, // Inst #3479 = VSHRuv4i16 + { 5, OperandInfo374 }, // Inst #3480 = VSHRuv4i32 + { 5, OperandInfo374 }, // Inst #3481 = VSHRuv8i16 + { 5, OperandInfo373 }, // Inst #3482 = VSHRuv8i8 + { 5, OperandInfo463 }, // Inst #3483 = VSHTOD + { 5, OperandInfo464 }, // Inst #3484 = VSHTOH + { 5, OperandInfo464 }, // Inst #3485 = VSHTOS + { 4, OperandInfo371 }, // Inst #3486 = VSITOD + { 4, OperandInfo465 }, // Inst #3487 = VSITOH + { 4, OperandInfo344 }, // Inst #3488 = VSITOS + { 6, OperandInfo466 }, // Inst #3489 = VSLIv16i8 + { 6, OperandInfo467 }, // Inst #3490 = VSLIv1i64 + { 6, OperandInfo467 }, // Inst #3491 = VSLIv2i32 + { 6, OperandInfo466 }, // Inst #3492 = VSLIv2i64 + { 6, OperandInfo467 }, // Inst #3493 = VSLIv4i16 + { 6, OperandInfo466 }, // Inst #3494 = VSLIv4i32 + { 6, OperandInfo466 }, // Inst #3495 = VSLIv8i16 + { 6, OperandInfo467 }, // Inst #3496 = VSLIv8i8 + { 5, OperandInfo463 }, // Inst #3497 = VSLTOD + { 5, OperandInfo464 }, // Inst #3498 = VSLTOH + { 5, OperandInfo464 }, // Inst #3499 = VSLTOS + { 4, OperandInfo162 }, // Inst #3500 = VSMMLA + { 4, OperandInfo342 }, // Inst #3501 = VSQRTD + { 4, OperandInfo343 }, // Inst #3502 = VSQRTH + { 4, OperandInfo344 }, // Inst #3503 = VSQRTS + { 6, OperandInfo460 }, // Inst #3504 = VSRAsv16i8 + { 6, OperandInfo461 }, // Inst #3505 = VSRAsv1i64 + { 6, OperandInfo461 }, // Inst #3506 = VSRAsv2i32 + { 6, OperandInfo460 }, // Inst #3507 = VSRAsv2i64 + { 6, OperandInfo461 }, // Inst #3508 = VSRAsv4i16 + { 6, OperandInfo460 }, // Inst #3509 = VSRAsv4i32 + { 6, OperandInfo460 }, // Inst #3510 = VSRAsv8i16 + { 6, OperandInfo461 }, // Inst #3511 = VSRAsv8i8 + { 6, OperandInfo460 }, // Inst #3512 = VSRAuv16i8 + { 6, OperandInfo461 }, // Inst #3513 = VSRAuv1i64 + { 6, OperandInfo461 }, // Inst #3514 = VSRAuv2i32 + { 6, OperandInfo460 }, // Inst #3515 = VSRAuv2i64 + { 6, OperandInfo461 }, // Inst #3516 = VSRAuv4i16 + { 6, OperandInfo460 }, // Inst #3517 = VSRAuv4i32 + { 6, OperandInfo460 }, // Inst #3518 = VSRAuv8i16 + { 6, OperandInfo461 }, // Inst #3519 = VSRAuv8i8 + { 6, OperandInfo460 }, // Inst #3520 = VSRIv16i8 + { 6, OperandInfo461 }, // Inst #3521 = VSRIv1i64 + { 6, OperandInfo461 }, // Inst #3522 = VSRIv2i32 + { 6, OperandInfo460 }, // Inst #3523 = VSRIv2i64 + { 6, OperandInfo461 }, // Inst #3524 = VSRIv4i16 + { 6, OperandInfo460 }, // Inst #3525 = VSRIv4i32 + { 6, OperandInfo460 }, // Inst #3526 = VSRIv8i16 + { 6, OperandInfo461 }, // Inst #3527 = VSRIv8i8 + { 6, OperandInfo468 }, // Inst #3528 = VST1LNd16 + { 8, OperandInfo469 }, // Inst #3529 = VST1LNd16_UPD + { 6, OperandInfo468 }, // Inst #3530 = VST1LNd32 + { 8, OperandInfo469 }, // Inst #3531 = VST1LNd32_UPD + { 6, OperandInfo468 }, // Inst #3532 = VST1LNd8 + { 8, OperandInfo469 }, // Inst #3533 = VST1LNd8_UPD + { 6, OperandInfo470 }, // Inst #3534 = VST1LNq16Pseudo + { 8, OperandInfo471 }, // Inst #3535 = VST1LNq16Pseudo_UPD + { 6, OperandInfo470 }, // Inst #3536 = VST1LNq32Pseudo + { 8, OperandInfo471 }, // Inst #3537 = VST1LNq32Pseudo_UPD + { 6, OperandInfo470 }, // Inst #3538 = VST1LNq8Pseudo + { 8, OperandInfo471 }, // Inst #3539 = VST1LNq8Pseudo_UPD + { 5, OperandInfo472 }, // Inst #3540 = VST1d16 + { 5, OperandInfo472 }, // Inst #3541 = VST1d16Q + { 5, OperandInfo473 }, // Inst #3542 = VST1d16QPseudo + { 6, OperandInfo474 }, // Inst #3543 = VST1d16QPseudoWB_fixed + { 7, OperandInfo475 }, // Inst #3544 = VST1d16QPseudoWB_register + { 6, OperandInfo476 }, // Inst #3545 = VST1d16Qwb_fixed + { 7, OperandInfo477 }, // Inst #3546 = VST1d16Qwb_register + { 5, OperandInfo472 }, // Inst #3547 = VST1d16T + { 5, OperandInfo473 }, // Inst #3548 = VST1d16TPseudo + { 6, OperandInfo474 }, // Inst #3549 = VST1d16TPseudoWB_fixed + { 7, OperandInfo475 }, // Inst #3550 = VST1d16TPseudoWB_register + { 6, OperandInfo476 }, // Inst #3551 = VST1d16Twb_fixed + { 7, OperandInfo477 }, // Inst #3552 = VST1d16Twb_register + { 6, OperandInfo476 }, // Inst #3553 = VST1d16wb_fixed + { 7, OperandInfo477 }, // Inst #3554 = VST1d16wb_register + { 5, OperandInfo472 }, // Inst #3555 = VST1d32 + { 5, OperandInfo472 }, // Inst #3556 = VST1d32Q + { 5, OperandInfo473 }, // Inst #3557 = VST1d32QPseudo + { 6, OperandInfo474 }, // Inst #3558 = VST1d32QPseudoWB_fixed + { 7, OperandInfo475 }, // Inst #3559 = VST1d32QPseudoWB_register + { 6, OperandInfo476 }, // Inst #3560 = VST1d32Qwb_fixed + { 7, OperandInfo477 }, // Inst #3561 = VST1d32Qwb_register + { 5, OperandInfo472 }, // Inst #3562 = VST1d32T + { 5, OperandInfo473 }, // Inst #3563 = VST1d32TPseudo + { 6, OperandInfo474 }, // Inst #3564 = VST1d32TPseudoWB_fixed + { 7, OperandInfo475 }, // Inst #3565 = VST1d32TPseudoWB_register + { 6, OperandInfo476 }, // Inst #3566 = VST1d32Twb_fixed + { 7, OperandInfo477 }, // Inst #3567 = VST1d32Twb_register + { 6, OperandInfo476 }, // Inst #3568 = VST1d32wb_fixed + { 7, OperandInfo477 }, // Inst #3569 = VST1d32wb_register + { 5, OperandInfo472 }, // Inst #3570 = VST1d64 + { 5, OperandInfo472 }, // Inst #3571 = VST1d64Q + { 5, OperandInfo473 }, // Inst #3572 = VST1d64QPseudo + { 6, OperandInfo474 }, // Inst #3573 = VST1d64QPseudoWB_fixed + { 7, OperandInfo475 }, // Inst #3574 = VST1d64QPseudoWB_register + { 6, OperandInfo476 }, // Inst #3575 = VST1d64Qwb_fixed + { 7, OperandInfo477 }, // Inst #3576 = VST1d64Qwb_register + { 5, OperandInfo472 }, // Inst #3577 = VST1d64T + { 5, OperandInfo473 }, // Inst #3578 = VST1d64TPseudo + { 6, OperandInfo474 }, // Inst #3579 = VST1d64TPseudoWB_fixed + { 7, OperandInfo475 }, // Inst #3580 = VST1d64TPseudoWB_register + { 6, OperandInfo476 }, // Inst #3581 = VST1d64Twb_fixed + { 7, OperandInfo477 }, // Inst #3582 = VST1d64Twb_register + { 6, OperandInfo476 }, // Inst #3583 = VST1d64wb_fixed + { 7, OperandInfo477 }, // Inst #3584 = VST1d64wb_register + { 5, OperandInfo472 }, // Inst #3585 = VST1d8 + { 5, OperandInfo472 }, // Inst #3586 = VST1d8Q + { 5, OperandInfo473 }, // Inst #3587 = VST1d8QPseudo + { 6, OperandInfo474 }, // Inst #3588 = VST1d8QPseudoWB_fixed + { 7, OperandInfo475 }, // Inst #3589 = VST1d8QPseudoWB_register + { 6, OperandInfo476 }, // Inst #3590 = VST1d8Qwb_fixed + { 7, OperandInfo477 }, // Inst #3591 = VST1d8Qwb_register + { 5, OperandInfo472 }, // Inst #3592 = VST1d8T + { 5, OperandInfo473 }, // Inst #3593 = VST1d8TPseudo + { 6, OperandInfo474 }, // Inst #3594 = VST1d8TPseudoWB_fixed + { 7, OperandInfo475 }, // Inst #3595 = VST1d8TPseudoWB_register + { 6, OperandInfo476 }, // Inst #3596 = VST1d8Twb_fixed + { 7, OperandInfo477 }, // Inst #3597 = VST1d8Twb_register + { 6, OperandInfo476 }, // Inst #3598 = VST1d8wb_fixed + { 7, OperandInfo477 }, // Inst #3599 = VST1d8wb_register + { 5, OperandInfo478 }, // Inst #3600 = VST1q16 + { 5, OperandInfo479 }, // Inst #3601 = VST1q16HighQPseudo + { 7, OperandInfo480 }, // Inst #3602 = VST1q16HighQPseudo_UPD + { 5, OperandInfo479 }, // Inst #3603 = VST1q16HighTPseudo + { 7, OperandInfo480 }, // Inst #3604 = VST1q16HighTPseudo_UPD + { 7, OperandInfo480 }, // Inst #3605 = VST1q16LowQPseudo_UPD + { 7, OperandInfo480 }, // Inst #3606 = VST1q16LowTPseudo_UPD + { 6, OperandInfo481 }, // Inst #3607 = VST1q16wb_fixed + { 7, OperandInfo482 }, // Inst #3608 = VST1q16wb_register + { 5, OperandInfo478 }, // Inst #3609 = VST1q32 + { 5, OperandInfo479 }, // Inst #3610 = VST1q32HighQPseudo + { 7, OperandInfo480 }, // Inst #3611 = VST1q32HighQPseudo_UPD + { 5, OperandInfo479 }, // Inst #3612 = VST1q32HighTPseudo + { 7, OperandInfo480 }, // Inst #3613 = VST1q32HighTPseudo_UPD + { 7, OperandInfo480 }, // Inst #3614 = VST1q32LowQPseudo_UPD + { 7, OperandInfo480 }, // Inst #3615 = VST1q32LowTPseudo_UPD + { 6, OperandInfo481 }, // Inst #3616 = VST1q32wb_fixed + { 7, OperandInfo482 }, // Inst #3617 = VST1q32wb_register + { 5, OperandInfo478 }, // Inst #3618 = VST1q64 + { 5, OperandInfo479 }, // Inst #3619 = VST1q64HighQPseudo + { 7, OperandInfo480 }, // Inst #3620 = VST1q64HighQPseudo_UPD + { 5, OperandInfo479 }, // Inst #3621 = VST1q64HighTPseudo + { 7, OperandInfo480 }, // Inst #3622 = VST1q64HighTPseudo_UPD + { 7, OperandInfo480 }, // Inst #3623 = VST1q64LowQPseudo_UPD + { 7, OperandInfo480 }, // Inst #3624 = VST1q64LowTPseudo_UPD + { 6, OperandInfo481 }, // Inst #3625 = VST1q64wb_fixed + { 7, OperandInfo482 }, // Inst #3626 = VST1q64wb_register + { 5, OperandInfo478 }, // Inst #3627 = VST1q8 + { 5, OperandInfo479 }, // Inst #3628 = VST1q8HighQPseudo + { 7, OperandInfo480 }, // Inst #3629 = VST1q8HighQPseudo_UPD + { 5, OperandInfo479 }, // Inst #3630 = VST1q8HighTPseudo + { 7, OperandInfo480 }, // Inst #3631 = VST1q8HighTPseudo_UPD + { 7, OperandInfo480 }, // Inst #3632 = VST1q8LowQPseudo_UPD + { 7, OperandInfo480 }, // Inst #3633 = VST1q8LowTPseudo_UPD + { 6, OperandInfo481 }, // Inst #3634 = VST1q8wb_fixed + { 7, OperandInfo482 }, // Inst #3635 = VST1q8wb_register + { 7, OperandInfo483 }, // Inst #3636 = VST2LNd16 + { 6, OperandInfo470 }, // Inst #3637 = VST2LNd16Pseudo + { 8, OperandInfo471 }, // Inst #3638 = VST2LNd16Pseudo_UPD + { 9, OperandInfo484 }, // Inst #3639 = VST2LNd16_UPD + { 7, OperandInfo483 }, // Inst #3640 = VST2LNd32 + { 6, OperandInfo470 }, // Inst #3641 = VST2LNd32Pseudo + { 8, OperandInfo471 }, // Inst #3642 = VST2LNd32Pseudo_UPD + { 9, OperandInfo484 }, // Inst #3643 = VST2LNd32_UPD + { 7, OperandInfo483 }, // Inst #3644 = VST2LNd8 + { 6, OperandInfo470 }, // Inst #3645 = VST2LNd8Pseudo + { 8, OperandInfo471 }, // Inst #3646 = VST2LNd8Pseudo_UPD + { 9, OperandInfo484 }, // Inst #3647 = VST2LNd8_UPD + { 7, OperandInfo483 }, // Inst #3648 = VST2LNq16 + { 6, OperandInfo485 }, // Inst #3649 = VST2LNq16Pseudo + { 8, OperandInfo486 }, // Inst #3650 = VST2LNq16Pseudo_UPD + { 9, OperandInfo484 }, // Inst #3651 = VST2LNq16_UPD + { 7, OperandInfo483 }, // Inst #3652 = VST2LNq32 + { 6, OperandInfo485 }, // Inst #3653 = VST2LNq32Pseudo + { 8, OperandInfo486 }, // Inst #3654 = VST2LNq32Pseudo_UPD + { 9, OperandInfo484 }, // Inst #3655 = VST2LNq32_UPD + { 5, OperandInfo478 }, // Inst #3656 = VST2b16 + { 6, OperandInfo481 }, // Inst #3657 = VST2b16wb_fixed + { 7, OperandInfo482 }, // Inst #3658 = VST2b16wb_register + { 5, OperandInfo478 }, // Inst #3659 = VST2b32 + { 6, OperandInfo481 }, // Inst #3660 = VST2b32wb_fixed + { 7, OperandInfo482 }, // Inst #3661 = VST2b32wb_register + { 5, OperandInfo478 }, // Inst #3662 = VST2b8 + { 6, OperandInfo481 }, // Inst #3663 = VST2b8wb_fixed + { 7, OperandInfo482 }, // Inst #3664 = VST2b8wb_register + { 5, OperandInfo478 }, // Inst #3665 = VST2d16 + { 6, OperandInfo481 }, // Inst #3666 = VST2d16wb_fixed + { 7, OperandInfo482 }, // Inst #3667 = VST2d16wb_register + { 5, OperandInfo478 }, // Inst #3668 = VST2d32 + { 6, OperandInfo481 }, // Inst #3669 = VST2d32wb_fixed + { 7, OperandInfo482 }, // Inst #3670 = VST2d32wb_register + { 5, OperandInfo478 }, // Inst #3671 = VST2d8 + { 6, OperandInfo481 }, // Inst #3672 = VST2d8wb_fixed + { 7, OperandInfo482 }, // Inst #3673 = VST2d8wb_register + { 5, OperandInfo472 }, // Inst #3674 = VST2q16 + { 5, OperandInfo473 }, // Inst #3675 = VST2q16Pseudo + { 6, OperandInfo474 }, // Inst #3676 = VST2q16PseudoWB_fixed + { 7, OperandInfo487 }, // Inst #3677 = VST2q16PseudoWB_register + { 6, OperandInfo476 }, // Inst #3678 = VST2q16wb_fixed + { 7, OperandInfo477 }, // Inst #3679 = VST2q16wb_register + { 5, OperandInfo472 }, // Inst #3680 = VST2q32 + { 5, OperandInfo473 }, // Inst #3681 = VST2q32Pseudo + { 6, OperandInfo474 }, // Inst #3682 = VST2q32PseudoWB_fixed + { 7, OperandInfo487 }, // Inst #3683 = VST2q32PseudoWB_register + { 6, OperandInfo476 }, // Inst #3684 = VST2q32wb_fixed + { 7, OperandInfo477 }, // Inst #3685 = VST2q32wb_register + { 5, OperandInfo472 }, // Inst #3686 = VST2q8 + { 5, OperandInfo473 }, // Inst #3687 = VST2q8Pseudo + { 6, OperandInfo474 }, // Inst #3688 = VST2q8PseudoWB_fixed + { 7, OperandInfo487 }, // Inst #3689 = VST2q8PseudoWB_register + { 6, OperandInfo476 }, // Inst #3690 = VST2q8wb_fixed + { 7, OperandInfo477 }, // Inst #3691 = VST2q8wb_register + { 8, OperandInfo488 }, // Inst #3692 = VST3LNd16 + { 6, OperandInfo485 }, // Inst #3693 = VST3LNd16Pseudo + { 8, OperandInfo486 }, // Inst #3694 = VST3LNd16Pseudo_UPD + { 10, OperandInfo489 }, // Inst #3695 = VST3LNd16_UPD + { 8, OperandInfo488 }, // Inst #3696 = VST3LNd32 + { 6, OperandInfo485 }, // Inst #3697 = VST3LNd32Pseudo + { 8, OperandInfo486 }, // Inst #3698 = VST3LNd32Pseudo_UPD + { 10, OperandInfo489 }, // Inst #3699 = VST3LNd32_UPD + { 8, OperandInfo488 }, // Inst #3700 = VST3LNd8 + { 6, OperandInfo485 }, // Inst #3701 = VST3LNd8Pseudo + { 8, OperandInfo486 }, // Inst #3702 = VST3LNd8Pseudo_UPD + { 10, OperandInfo489 }, // Inst #3703 = VST3LNd8_UPD + { 8, OperandInfo488 }, // Inst #3704 = VST3LNq16 + { 6, OperandInfo490 }, // Inst #3705 = VST3LNq16Pseudo + { 8, OperandInfo491 }, // Inst #3706 = VST3LNq16Pseudo_UPD + { 10, OperandInfo489 }, // Inst #3707 = VST3LNq16_UPD + { 8, OperandInfo488 }, // Inst #3708 = VST3LNq32 + { 6, OperandInfo490 }, // Inst #3709 = VST3LNq32Pseudo + { 8, OperandInfo491 }, // Inst #3710 = VST3LNq32Pseudo_UPD + { 10, OperandInfo489 }, // Inst #3711 = VST3LNq32_UPD + { 7, OperandInfo492 }, // Inst #3712 = VST3d16 + { 5, OperandInfo473 }, // Inst #3713 = VST3d16Pseudo + { 7, OperandInfo475 }, // Inst #3714 = VST3d16Pseudo_UPD + { 9, OperandInfo493 }, // Inst #3715 = VST3d16_UPD + { 7, OperandInfo492 }, // Inst #3716 = VST3d32 + { 5, OperandInfo473 }, // Inst #3717 = VST3d32Pseudo + { 7, OperandInfo475 }, // Inst #3718 = VST3d32Pseudo_UPD + { 9, OperandInfo493 }, // Inst #3719 = VST3d32_UPD + { 7, OperandInfo492 }, // Inst #3720 = VST3d8 + { 5, OperandInfo473 }, // Inst #3721 = VST3d8Pseudo + { 7, OperandInfo475 }, // Inst #3722 = VST3d8Pseudo_UPD + { 9, OperandInfo493 }, // Inst #3723 = VST3d8_UPD + { 7, OperandInfo492 }, // Inst #3724 = VST3q16 + { 7, OperandInfo480 }, // Inst #3725 = VST3q16Pseudo_UPD + { 9, OperandInfo493 }, // Inst #3726 = VST3q16_UPD + { 5, OperandInfo479 }, // Inst #3727 = VST3q16oddPseudo + { 7, OperandInfo480 }, // Inst #3728 = VST3q16oddPseudo_UPD + { 7, OperandInfo492 }, // Inst #3729 = VST3q32 + { 7, OperandInfo480 }, // Inst #3730 = VST3q32Pseudo_UPD + { 9, OperandInfo493 }, // Inst #3731 = VST3q32_UPD + { 5, OperandInfo479 }, // Inst #3732 = VST3q32oddPseudo + { 7, OperandInfo480 }, // Inst #3733 = VST3q32oddPseudo_UPD + { 7, OperandInfo492 }, // Inst #3734 = VST3q8 + { 7, OperandInfo480 }, // Inst #3735 = VST3q8Pseudo_UPD + { 9, OperandInfo493 }, // Inst #3736 = VST3q8_UPD + { 5, OperandInfo479 }, // Inst #3737 = VST3q8oddPseudo + { 7, OperandInfo480 }, // Inst #3738 = VST3q8oddPseudo_UPD + { 9, OperandInfo494 }, // Inst #3739 = VST4LNd16 + { 6, OperandInfo485 }, // Inst #3740 = VST4LNd16Pseudo + { 8, OperandInfo486 }, // Inst #3741 = VST4LNd16Pseudo_UPD + { 11, OperandInfo495 }, // Inst #3742 = VST4LNd16_UPD + { 9, OperandInfo494 }, // Inst #3743 = VST4LNd32 + { 6, OperandInfo485 }, // Inst #3744 = VST4LNd32Pseudo + { 8, OperandInfo486 }, // Inst #3745 = VST4LNd32Pseudo_UPD + { 11, OperandInfo495 }, // Inst #3746 = VST4LNd32_UPD + { 9, OperandInfo494 }, // Inst #3747 = VST4LNd8 + { 6, OperandInfo485 }, // Inst #3748 = VST4LNd8Pseudo + { 8, OperandInfo486 }, // Inst #3749 = VST4LNd8Pseudo_UPD + { 11, OperandInfo495 }, // Inst #3750 = VST4LNd8_UPD + { 9, OperandInfo494 }, // Inst #3751 = VST4LNq16 + { 6, OperandInfo490 }, // Inst #3752 = VST4LNq16Pseudo + { 8, OperandInfo491 }, // Inst #3753 = VST4LNq16Pseudo_UPD + { 11, OperandInfo495 }, // Inst #3754 = VST4LNq16_UPD + { 9, OperandInfo494 }, // Inst #3755 = VST4LNq32 + { 6, OperandInfo490 }, // Inst #3756 = VST4LNq32Pseudo + { 8, OperandInfo491 }, // Inst #3757 = VST4LNq32Pseudo_UPD + { 11, OperandInfo495 }, // Inst #3758 = VST4LNq32_UPD + { 8, OperandInfo496 }, // Inst #3759 = VST4d16 + { 5, OperandInfo473 }, // Inst #3760 = VST4d16Pseudo + { 7, OperandInfo475 }, // Inst #3761 = VST4d16Pseudo_UPD + { 10, OperandInfo497 }, // Inst #3762 = VST4d16_UPD + { 8, OperandInfo496 }, // Inst #3763 = VST4d32 + { 5, OperandInfo473 }, // Inst #3764 = VST4d32Pseudo + { 7, OperandInfo475 }, // Inst #3765 = VST4d32Pseudo_UPD + { 10, OperandInfo497 }, // Inst #3766 = VST4d32_UPD + { 8, OperandInfo496 }, // Inst #3767 = VST4d8 + { 5, OperandInfo473 }, // Inst #3768 = VST4d8Pseudo + { 7, OperandInfo475 }, // Inst #3769 = VST4d8Pseudo_UPD + { 10, OperandInfo497 }, // Inst #3770 = VST4d8_UPD + { 8, OperandInfo496 }, // Inst #3771 = VST4q16 + { 7, OperandInfo480 }, // Inst #3772 = VST4q16Pseudo_UPD + { 10, OperandInfo497 }, // Inst #3773 = VST4q16_UPD + { 5, OperandInfo479 }, // Inst #3774 = VST4q16oddPseudo + { 7, OperandInfo480 }, // Inst #3775 = VST4q16oddPseudo_UPD + { 8, OperandInfo496 }, // Inst #3776 = VST4q32 + { 7, OperandInfo480 }, // Inst #3777 = VST4q32Pseudo_UPD + { 10, OperandInfo497 }, // Inst #3778 = VST4q32_UPD + { 5, OperandInfo479 }, // Inst #3779 = VST4q32oddPseudo + { 7, OperandInfo480 }, // Inst #3780 = VST4q32oddPseudo_UPD + { 8, OperandInfo496 }, // Inst #3781 = VST4q8 + { 7, OperandInfo480 }, // Inst #3782 = VST4q8Pseudo_UPD + { 10, OperandInfo497 }, // Inst #3783 = VST4q8_UPD + { 5, OperandInfo479 }, // Inst #3784 = VST4q8oddPseudo + { 7, OperandInfo480 }, // Inst #3785 = VST4q8oddPseudo_UPD + { 5, OperandInfo66 }, // Inst #3786 = VSTMDDB_UPD + { 4, OperandInfo206 }, // Inst #3787 = VSTMDIA + { 5, OperandInfo66 }, // Inst #3788 = VSTMDIA_UPD + { 4, OperandInfo423 }, // Inst #3789 = VSTMQIA + { 5, OperandInfo66 }, // Inst #3790 = VSTMSDB_UPD + { 4, OperandInfo206 }, // Inst #3791 = VSTMSIA + { 5, OperandInfo66 }, // Inst #3792 = VSTMSIA_UPD + { 5, OperandInfo99 }, // Inst #3793 = VSTRD + { 5, OperandInfo424 }, // Inst #3794 = VSTRH + { 5, OperandInfo425 }, // Inst #3795 = VSTRS + { 4, OperandInfo426 }, // Inst #3796 = VSTR_FPCXTNS_off + { 5, OperandInfo427 }, // Inst #3797 = VSTR_FPCXTNS_post + { 5, OperandInfo427 }, // Inst #3798 = VSTR_FPCXTNS_pre + { 4, OperandInfo426 }, // Inst #3799 = VSTR_FPCXTS_off + { 5, OperandInfo427 }, // Inst #3800 = VSTR_FPCXTS_post + { 5, OperandInfo427 }, // Inst #3801 = VSTR_FPCXTS_pre + { 4, OperandInfo426 }, // Inst #3802 = VSTR_FPSCR_NZCVQC_off + { 5, OperandInfo427 }, // Inst #3803 = VSTR_FPSCR_NZCVQC_post + { 5, OperandInfo427 }, // Inst #3804 = VSTR_FPSCR_NZCVQC_pre + { 4, OperandInfo426 }, // Inst #3805 = VSTR_FPSCR_off + { 5, OperandInfo427 }, // Inst #3806 = VSTR_FPSCR_post + { 5, OperandInfo427 }, // Inst #3807 = VSTR_FPSCR_pre + { 5, OperandInfo428 }, // Inst #3808 = VSTR_P0_off + { 6, OperandInfo498 }, // Inst #3809 = VSTR_P0_post + { 6, OperandInfo498 }, // Inst #3810 = VSTR_P0_pre + { 4, OperandInfo426 }, // Inst #3811 = VSTR_VPR_off + { 5, OperandInfo427 }, // Inst #3812 = VSTR_VPR_post + { 5, OperandInfo427 }, // Inst #3813 = VSTR_VPR_pre + { 5, OperandInfo340 }, // Inst #3814 = VSUBD + { 5, OperandInfo346 }, // Inst #3815 = VSUBH + { 5, OperandInfo347 }, // Inst #3816 = VSUBHNv2i32 + { 5, OperandInfo347 }, // Inst #3817 = VSUBHNv4i16 + { 5, OperandInfo347 }, // Inst #3818 = VSUBHNv8i8 + { 5, OperandInfo339 }, // Inst #3819 = VSUBLsv2i64 + { 5, OperandInfo339 }, // Inst #3820 = VSUBLsv4i32 + { 5, OperandInfo339 }, // Inst #3821 = VSUBLsv8i16 + { 5, OperandInfo339 }, // Inst #3822 = VSUBLuv2i64 + { 5, OperandInfo339 }, // Inst #3823 = VSUBLuv4i32 + { 5, OperandInfo339 }, // Inst #3824 = VSUBLuv8i16 + { 5, OperandInfo348 }, // Inst #3825 = VSUBS + { 5, OperandInfo349 }, // Inst #3826 = VSUBWsv2i64 + { 5, OperandInfo349 }, // Inst #3827 = VSUBWsv4i32 + { 5, OperandInfo349 }, // Inst #3828 = VSUBWsv8i16 + { 5, OperandInfo349 }, // Inst #3829 = VSUBWuv2i64 + { 5, OperandInfo349 }, // Inst #3830 = VSUBWuv4i32 + { 5, OperandInfo349 }, // Inst #3831 = VSUBWuv8i16 + { 5, OperandInfo340 }, // Inst #3832 = VSUBfd + { 5, OperandInfo341 }, // Inst #3833 = VSUBfq + { 5, OperandInfo340 }, // Inst #3834 = VSUBhd + { 5, OperandInfo341 }, // Inst #3835 = VSUBhq + { 5, OperandInfo341 }, // Inst #3836 = VSUBv16i8 + { 5, OperandInfo340 }, // Inst #3837 = VSUBv1i64 + { 5, OperandInfo340 }, // Inst #3838 = VSUBv2i32 + { 5, OperandInfo341 }, // Inst #3839 = VSUBv2i64 + { 5, OperandInfo340 }, // Inst #3840 = VSUBv4i16 + { 5, OperandInfo341 }, // Inst #3841 = VSUBv4i32 + { 5, OperandInfo341 }, // Inst #3842 = VSUBv8i16 + { 5, OperandInfo340 }, // Inst #3843 = VSUBv8i8 + { 5, OperandInfo159 }, // Inst #3844 = VSUDOTDI + { 5, OperandInfo160 }, // Inst #3845 = VSUDOTQI + { 6, OperandInfo499 }, // Inst #3846 = VSWPd + { 6, OperandInfo500 }, // Inst #3847 = VSWPq + { 5, OperandInfo340 }, // Inst #3848 = VTBL1 + { 5, OperandInfo501 }, // Inst #3849 = VTBL2 + { 5, OperandInfo340 }, // Inst #3850 = VTBL3 + { 5, OperandInfo502 }, // Inst #3851 = VTBL3Pseudo + { 5, OperandInfo340 }, // Inst #3852 = VTBL4 + { 5, OperandInfo502 }, // Inst #3853 = VTBL4Pseudo + { 6, OperandInfo338 }, // Inst #3854 = VTBX1 + { 6, OperandInfo503 }, // Inst #3855 = VTBX2 + { 6, OperandInfo338 }, // Inst #3856 = VTBX3 + { 6, OperandInfo504 }, // Inst #3857 = VTBX3Pseudo + { 6, OperandInfo338 }, // Inst #3858 = VTBX4 + { 6, OperandInfo504 }, // Inst #3859 = VTBX4Pseudo + { 5, OperandInfo463 }, // Inst #3860 = VTOSHD + { 5, OperandInfo464 }, // Inst #3861 = VTOSHH + { 5, OperandInfo464 }, // Inst #3862 = VTOSHS + { 4, OperandInfo372 }, // Inst #3863 = VTOSIRD + { 4, OperandInfo344 }, // Inst #3864 = VTOSIRH + { 4, OperandInfo344 }, // Inst #3865 = VTOSIRS + { 4, OperandInfo372 }, // Inst #3866 = VTOSIZD + { 4, OperandInfo505 }, // Inst #3867 = VTOSIZH + { 4, OperandInfo344 }, // Inst #3868 = VTOSIZS + { 5, OperandInfo463 }, // Inst #3869 = VTOSLD + { 5, OperandInfo464 }, // Inst #3870 = VTOSLH + { 5, OperandInfo464 }, // Inst #3871 = VTOSLS + { 5, OperandInfo463 }, // Inst #3872 = VTOUHD + { 5, OperandInfo464 }, // Inst #3873 = VTOUHH + { 5, OperandInfo464 }, // Inst #3874 = VTOUHS + { 4, OperandInfo372 }, // Inst #3875 = VTOUIRD + { 4, OperandInfo344 }, // Inst #3876 = VTOUIRH + { 4, OperandInfo344 }, // Inst #3877 = VTOUIRS + { 4, OperandInfo372 }, // Inst #3878 = VTOUIZD + { 4, OperandInfo505 }, // Inst #3879 = VTOUIZH + { 4, OperandInfo344 }, // Inst #3880 = VTOUIZS + { 5, OperandInfo463 }, // Inst #3881 = VTOULD + { 5, OperandInfo464 }, // Inst #3882 = VTOULH + { 5, OperandInfo464 }, // Inst #3883 = VTOULS + { 6, OperandInfo499 }, // Inst #3884 = VTRNd16 + { 6, OperandInfo499 }, // Inst #3885 = VTRNd32 + { 6, OperandInfo499 }, // Inst #3886 = VTRNd8 + { 6, OperandInfo500 }, // Inst #3887 = VTRNq16 + { 6, OperandInfo500 }, // Inst #3888 = VTRNq32 + { 6, OperandInfo500 }, // Inst #3889 = VTRNq8 + { 5, OperandInfo341 }, // Inst #3890 = VTSTv16i8 + { 5, OperandInfo340 }, // Inst #3891 = VTSTv2i32 + { 5, OperandInfo340 }, // Inst #3892 = VTSTv4i16 + { 5, OperandInfo341 }, // Inst #3893 = VTSTv4i32 + { 5, OperandInfo341 }, // Inst #3894 = VTSTv8i16 + { 5, OperandInfo340 }, // Inst #3895 = VTSTv8i8 + { 4, OperandInfo161 }, // Inst #3896 = VUDOTD + { 5, OperandInfo159 }, // Inst #3897 = VUDOTDI + { 4, OperandInfo162 }, // Inst #3898 = VUDOTQ + { 5, OperandInfo160 }, // Inst #3899 = VUDOTQI + { 5, OperandInfo463 }, // Inst #3900 = VUHTOD + { 5, OperandInfo464 }, // Inst #3901 = VUHTOH + { 5, OperandInfo464 }, // Inst #3902 = VUHTOS + { 4, OperandInfo371 }, // Inst #3903 = VUITOD + { 4, OperandInfo465 }, // Inst #3904 = VUITOH + { 4, OperandInfo344 }, // Inst #3905 = VUITOS + { 5, OperandInfo463 }, // Inst #3906 = VULTOD + { 5, OperandInfo464 }, // Inst #3907 = VULTOH + { 5, OperandInfo464 }, // Inst #3908 = VULTOS + { 4, OperandInfo162 }, // Inst #3909 = VUMMLA + { 4, OperandInfo161 }, // Inst #3910 = VUSDOTD + { 5, OperandInfo159 }, // Inst #3911 = VUSDOTDI + { 4, OperandInfo162 }, // Inst #3912 = VUSDOTQ + { 5, OperandInfo160 }, // Inst #3913 = VUSDOTQI + { 4, OperandInfo162 }, // Inst #3914 = VUSMMLA + { 6, OperandInfo499 }, // Inst #3915 = VUZPd16 + { 6, OperandInfo499 }, // Inst #3916 = VUZPd8 + { 6, OperandInfo500 }, // Inst #3917 = VUZPq16 + { 6, OperandInfo500 }, // Inst #3918 = VUZPq32 + { 6, OperandInfo500 }, // Inst #3919 = VUZPq8 + { 6, OperandInfo499 }, // Inst #3920 = VZIPd16 + { 6, OperandInfo499 }, // Inst #3921 = VZIPd8 + { 6, OperandInfo500 }, // Inst #3922 = VZIPq16 + { 6, OperandInfo500 }, // Inst #3923 = VZIPq32 + { 6, OperandInfo500 }, // Inst #3924 = VZIPq8 + { 4, OperandInfo206 }, // Inst #3925 = sysLDMDA + { 5, OperandInfo66 }, // Inst #3926 = sysLDMDA_UPD + { 4, OperandInfo206 }, // Inst #3927 = sysLDMDB + { 5, OperandInfo66 }, // Inst #3928 = sysLDMDB_UPD + { 4, OperandInfo206 }, // Inst #3929 = sysLDMIA + { 5, OperandInfo66 }, // Inst #3930 = sysLDMIA_UPD + { 4, OperandInfo206 }, // Inst #3931 = sysLDMIB + { 5, OperandInfo66 }, // Inst #3932 = sysLDMIB_UPD + { 4, OperandInfo206 }, // Inst #3933 = sysSTMDA + { 5, OperandInfo66 }, // Inst #3934 = sysSTMDA_UPD + { 4, OperandInfo206 }, // Inst #3935 = sysSTMDB + { 5, OperandInfo66 }, // Inst #3936 = sysSTMDB_UPD + { 4, OperandInfo206 }, // Inst #3937 = sysSTMIA + { 5, OperandInfo66 }, // Inst #3938 = sysSTMIA_UPD + { 4, OperandInfo206 }, // Inst #3939 = sysSTMIB + { 5, OperandInfo66 }, // Inst #3940 = sysSTMIB_UPD + { 6, OperandInfo506 }, // Inst #3941 = t2ADCri + { 6, OperandInfo507 }, // Inst #3942 = t2ADCrr + { 7, OperandInfo508 }, // Inst #3943 = t2ADCrs + { 6, OperandInfo509 }, // Inst #3944 = t2ADDri + { 5, OperandInfo510 }, // Inst #3945 = t2ADDri12 + { 6, OperandInfo511 }, // Inst #3946 = t2ADDrr + { 7, OperandInfo512 }, // Inst #3947 = t2ADDrs + { 6, OperandInfo513 }, // Inst #3948 = t2ADDspImm + { 5, OperandInfo514 }, // Inst #3949 = t2ADDspImm12 + { 4, OperandInfo515 }, // Inst #3950 = t2ADR + { 6, OperandInfo506 }, // Inst #3951 = t2ANDri + { 6, OperandInfo507 }, // Inst #3952 = t2ANDrr + { 7, OperandInfo508 }, // Inst #3953 = t2ANDrs + { 6, OperandInfo506 }, // Inst #3954 = t2ASRri + { 6, OperandInfo507 }, // Inst #3955 = t2ASRrr + { 0, 0 }, // Inst #3956 = t2AUT + { 5, OperandInfo516 }, // Inst #3957 = t2AUTG + { 3, OperandInfo141 }, // Inst #3958 = t2B + { 5, OperandInfo120 }, // Inst #3959 = t2BFC + { 6, OperandInfo517 }, // Inst #3960 = t2BFI + { 4, OperandInfo518 }, // Inst #3961 = t2BFLi + { 4, OperandInfo519 }, // Inst #3962 = t2BFLr + { 4, OperandInfo518 }, // Inst #3963 = t2BFi + { 4, OperandInfo520 }, // Inst #3964 = t2BFic + { 4, OperandInfo519 }, // Inst #3965 = t2BFr + { 6, OperandInfo506 }, // Inst #3966 = t2BICri + { 6, OperandInfo507 }, // Inst #3967 = t2BICrr + { 7, OperandInfo508 }, // Inst #3968 = t2BICrs + { 0, 0 }, // Inst #3969 = t2BTI + { 5, OperandInfo521 }, // Inst #3970 = t2BXAUT + { 3, OperandInfo239 }, // Inst #3971 = t2BXJ + { 3, OperandInfo141 }, // Inst #3972 = t2Bcc + { 8, OperandInfo195 }, // Inst #3973 = t2CDP + { 8, OperandInfo195 }, // Inst #3974 = t2CDP2 + { 2, OperandInfo139 }, // Inst #3975 = t2CLREX + { 3, OperandInfo150 }, // Inst #3976 = t2CLRM + { 4, OperandInfo522 }, // Inst #3977 = t2CLZ + { 4, OperandInfo113 }, // Inst #3978 = t2CMNri + { 4, OperandInfo523 }, // Inst #3979 = t2CMNzrr + { 5, OperandInfo524 }, // Inst #3980 = t2CMNzrs + { 4, OperandInfo113 }, // Inst #3981 = t2CMPri + { 4, OperandInfo523 }, // Inst #3982 = t2CMPrr + { 5, OperandInfo524 }, // Inst #3983 = t2CMPrs + { 1, OperandInfo2 }, // Inst #3984 = t2CPS1p + { 2, OperandInfo7 }, // Inst #3985 = t2CPS2p + { 3, OperandInfo4 }, // Inst #3986 = t2CPS3p + { 3, OperandInfo85 }, // Inst #3987 = t2CRC32B + { 3, OperandInfo85 }, // Inst #3988 = t2CRC32CB + { 3, OperandInfo85 }, // Inst #3989 = t2CRC32CH + { 3, OperandInfo85 }, // Inst #3990 = t2CRC32CW + { 3, OperandInfo85 }, // Inst #3991 = t2CRC32H + { 3, OperandInfo85 }, // Inst #3992 = t2CRC32W + { 4, OperandInfo525 }, // Inst #3993 = t2CSEL + { 4, OperandInfo525 }, // Inst #3994 = t2CSINC + { 4, OperandInfo525 }, // Inst #3995 = t2CSINV + { 4, OperandInfo525 }, // Inst #3996 = t2CSNEG + { 3, OperandInfo202 }, // Inst #3997 = t2DBG + { 2, OperandInfo139 }, // Inst #3998 = t2DCPS1 + { 2, OperandInfo139 }, // Inst #3999 = t2DCPS2 + { 2, OperandInfo139 }, // Inst #4000 = t2DCPS3 + { 2, OperandInfo111 }, // Inst #4001 = t2DLS + { 3, OperandInfo202 }, // Inst #4002 = t2DMB + { 3, OperandInfo202 }, // Inst #4003 = t2DSB + { 6, OperandInfo506 }, // Inst #4004 = t2EORri + { 6, OperandInfo507 }, // Inst #4005 = t2EORrr + { 7, OperandInfo508 }, // Inst #4006 = t2EORrs + { 3, OperandInfo202 }, // Inst #4007 = t2HINT + { 1, OperandInfo2 }, // Inst #4008 = t2HVC + { 3, OperandInfo202 }, // Inst #4009 = t2ISB + { 2, OperandInfo7 }, // Inst #4010 = t2IT + { 2, OperandInfo151 }, // Inst #4011 = t2Int_eh_sjlj_setjmp + { 2, OperandInfo151 }, // Inst #4012 = t2Int_eh_sjlj_setjmp_nofp + { 4, OperandInfo526 }, // Inst #4013 = t2LDA + { 4, OperandInfo526 }, // Inst #4014 = t2LDAB + { 4, OperandInfo526 }, // Inst #4015 = t2LDAEX + { 4, OperandInfo526 }, // Inst #4016 = t2LDAEXB + { 5, OperandInfo527 }, // Inst #4017 = t2LDAEXD + { 4, OperandInfo526 }, // Inst #4018 = t2LDAEXH + { 4, OperandInfo526 }, // Inst #4019 = t2LDAH + { 6, OperandInfo211 }, // Inst #4020 = t2LDC2L_OFFSET + { 6, OperandInfo212 }, // Inst #4021 = t2LDC2L_OPTION + { 6, OperandInfo211 }, // Inst #4022 = t2LDC2L_POST + { 7, OperandInfo213 }, // Inst #4023 = t2LDC2L_PRE + { 6, OperandInfo211 }, // Inst #4024 = t2LDC2_OFFSET + { 6, OperandInfo212 }, // Inst #4025 = t2LDC2_OPTION + { 6, OperandInfo211 }, // Inst #4026 = t2LDC2_POST + { 7, OperandInfo213 }, // Inst #4027 = t2LDC2_PRE + { 6, OperandInfo211 }, // Inst #4028 = t2LDCL_OFFSET + { 6, OperandInfo212 }, // Inst #4029 = t2LDCL_OPTION + { 6, OperandInfo211 }, // Inst #4030 = t2LDCL_POST + { 7, OperandInfo213 }, // Inst #4031 = t2LDCL_PRE + { 6, OperandInfo211 }, // Inst #4032 = t2LDC_OFFSET + { 6, OperandInfo212 }, // Inst #4033 = t2LDC_OPTION + { 6, OperandInfo211 }, // Inst #4034 = t2LDC_POST + { 7, OperandInfo213 }, // Inst #4035 = t2LDC_PRE + { 4, OperandInfo206 }, // Inst #4036 = t2LDMDB + { 5, OperandInfo66 }, // Inst #4037 = t2LDMDB_UPD + { 4, OperandInfo206 }, // Inst #4038 = t2LDMIA + { 5, OperandInfo66 }, // Inst #4039 = t2LDMIA_UPD + { 5, OperandInfo528 }, // Inst #4040 = t2LDRBT + { 6, OperandInfo215 }, // Inst #4041 = t2LDRB_POST + { 6, OperandInfo215 }, // Inst #4042 = t2LDRB_PRE + { 5, OperandInfo216 }, // Inst #4043 = t2LDRBi12 + { 5, OperandInfo216 }, // Inst #4044 = t2LDRBi8 + { 4, OperandInfo529 }, // Inst #4045 = t2LDRBpci + { 6, OperandInfo530 }, // Inst #4046 = t2LDRBs + { 7, OperandInfo531 }, // Inst #4047 = t2LDRD_POST + { 7, OperandInfo531 }, // Inst #4048 = t2LDRD_PRE + { 6, OperandInfo532 }, // Inst #4049 = t2LDRDi8 + { 5, OperandInfo533 }, // Inst #4050 = t2LDREX + { 4, OperandInfo526 }, // Inst #4051 = t2LDREXB + { 5, OperandInfo527 }, // Inst #4052 = t2LDREXD + { 4, OperandInfo526 }, // Inst #4053 = t2LDREXH + { 5, OperandInfo528 }, // Inst #4054 = t2LDRHT + { 6, OperandInfo215 }, // Inst #4055 = t2LDRH_POST + { 6, OperandInfo215 }, // Inst #4056 = t2LDRH_PRE + { 5, OperandInfo216 }, // Inst #4057 = t2LDRHi12 + { 5, OperandInfo216 }, // Inst #4058 = t2LDRHi8 + { 4, OperandInfo529 }, // Inst #4059 = t2LDRHpci + { 6, OperandInfo530 }, // Inst #4060 = t2LDRHs + { 5, OperandInfo528 }, // Inst #4061 = t2LDRSBT + { 6, OperandInfo215 }, // Inst #4062 = t2LDRSB_POST + { 6, OperandInfo215 }, // Inst #4063 = t2LDRSB_PRE + { 5, OperandInfo216 }, // Inst #4064 = t2LDRSBi12 + { 5, OperandInfo216 }, // Inst #4065 = t2LDRSBi8 + { 4, OperandInfo529 }, // Inst #4066 = t2LDRSBpci + { 6, OperandInfo530 }, // Inst #4067 = t2LDRSBs + { 5, OperandInfo528 }, // Inst #4068 = t2LDRSHT + { 6, OperandInfo215 }, // Inst #4069 = t2LDRSH_POST + { 6, OperandInfo215 }, // Inst #4070 = t2LDRSH_PRE + { 5, OperandInfo216 }, // Inst #4071 = t2LDRSHi12 + { 5, OperandInfo216 }, // Inst #4072 = t2LDRSHi8 + { 4, OperandInfo529 }, // Inst #4073 = t2LDRSHpci + { 6, OperandInfo530 }, // Inst #4074 = t2LDRSHs + { 5, OperandInfo528 }, // Inst #4075 = t2LDRT + { 6, OperandInfo215 }, // Inst #4076 = t2LDR_POST + { 6, OperandInfo215 }, // Inst #4077 = t2LDR_PRE + { 5, OperandInfo87 }, // Inst #4078 = t2LDRi12 + { 5, OperandInfo87 }, // Inst #4079 = t2LDRi8 + { 4, OperandInfo534 }, // Inst #4080 = t2LDRpci + { 6, OperandInfo535 }, // Inst #4081 = t2LDRs + { 1, OperandInfo53 }, // Inst #4082 = t2LE + { 3, OperandInfo118 }, // Inst #4083 = t2LEUpdate + { 6, OperandInfo506 }, // Inst #4084 = t2LSLri + { 6, OperandInfo507 }, // Inst #4085 = t2LSLrr + { 6, OperandInfo506 }, // Inst #4086 = t2LSRri + { 6, OperandInfo507 }, // Inst #4087 = t2LSRrr + { 8, OperandInfo224 }, // Inst #4088 = t2MCR + { 8, OperandInfo224 }, // Inst #4089 = t2MCR2 + { 7, OperandInfo536 }, // Inst #4090 = t2MCRR + { 7, OperandInfo536 }, // Inst #4091 = t2MCRR2 + { 6, OperandInfo537 }, // Inst #4092 = t2MLA + { 6, OperandInfo537 }, // Inst #4093 = t2MLS + { 5, OperandInfo120 }, // Inst #4094 = t2MOVTi16 + { 5, OperandInfo538 }, // Inst #4095 = t2MOVi + { 4, OperandInfo515 }, // Inst #4096 = t2MOVi16 + { 5, OperandInfo539 }, // Inst #4097 = t2MOVr + { 4, OperandInfo522 }, // Inst #4098 = t2MOVsra_flag + { 4, OperandInfo522 }, // Inst #4099 = t2MOVsrl_flag + { 8, OperandInfo235 }, // Inst #4100 = t2MRC + { 8, OperandInfo235 }, // Inst #4101 = t2MRC2 + { 7, OperandInfo540 }, // Inst #4102 = t2MRRC + { 7, OperandInfo540 }, // Inst #4103 = t2MRRC2 + { 3, OperandInfo137 }, // Inst #4104 = t2MRS_AR + { 4, OperandInfo515 }, // Inst #4105 = t2MRS_M + { 4, OperandInfo515 }, // Inst #4106 = t2MRSbanked + { 3, OperandInfo137 }, // Inst #4107 = t2MRSsys_AR + { 4, OperandInfo541 }, // Inst #4108 = t2MSR_AR + { 4, OperandInfo541 }, // Inst #4109 = t2MSR_M + { 4, OperandInfo541 }, // Inst #4110 = t2MSRbanked + { 5, OperandInfo542 }, // Inst #4111 = t2MUL + { 5, OperandInfo538 }, // Inst #4112 = t2MVNi + { 5, OperandInfo543 }, // Inst #4113 = t2MVNr + { 6, OperandInfo544 }, // Inst #4114 = t2MVNs + { 6, OperandInfo506 }, // Inst #4115 = t2ORNri + { 6, OperandInfo507 }, // Inst #4116 = t2ORNrr + { 7, OperandInfo508 }, // Inst #4117 = t2ORNrs + { 6, OperandInfo506 }, // Inst #4118 = t2ORRri + { 6, OperandInfo507 }, // Inst #4119 = t2ORRrr + { 7, OperandInfo508 }, // Inst #4120 = t2ORRrs + { 0, 0 }, // Inst #4121 = t2PAC + { 0, 0 }, // Inst #4122 = t2PACBTI + { 5, OperandInfo545 }, // Inst #4123 = t2PACG + { 6, OperandInfo546 }, // Inst #4124 = t2PKHBT + { 6, OperandInfo546 }, // Inst #4125 = t2PKHTB + { 4, OperandInfo547 }, // Inst #4126 = t2PLDWi12 + { 4, OperandInfo547 }, // Inst #4127 = t2PLDWi8 + { 5, OperandInfo548 }, // Inst #4128 = t2PLDWs + { 4, OperandInfo547 }, // Inst #4129 = t2PLDi12 + { 4, OperandInfo547 }, // Inst #4130 = t2PLDi8 + { 3, OperandInfo549 }, // Inst #4131 = t2PLDpci + { 5, OperandInfo548 }, // Inst #4132 = t2PLDs + { 4, OperandInfo547 }, // Inst #4133 = t2PLIi12 + { 4, OperandInfo547 }, // Inst #4134 = t2PLIi8 + { 3, OperandInfo549 }, // Inst #4135 = t2PLIpci + { 5, OperandInfo548 }, // Inst #4136 = t2PLIs + { 5, OperandInfo542 }, // Inst #4137 = t2QADD + { 5, OperandInfo542 }, // Inst #4138 = t2QADD16 + { 5, OperandInfo542 }, // Inst #4139 = t2QADD8 + { 5, OperandInfo542 }, // Inst #4140 = t2QASX + { 5, OperandInfo542 }, // Inst #4141 = t2QDADD + { 5, OperandInfo542 }, // Inst #4142 = t2QDSUB + { 5, OperandInfo542 }, // Inst #4143 = t2QSAX + { 5, OperandInfo542 }, // Inst #4144 = t2QSUB + { 5, OperandInfo542 }, // Inst #4145 = t2QSUB16 + { 5, OperandInfo542 }, // Inst #4146 = t2QSUB8 + { 4, OperandInfo522 }, // Inst #4147 = t2RBIT + { 4, OperandInfo522 }, // Inst #4148 = t2REV + { 4, OperandInfo522 }, // Inst #4149 = t2REV16 + { 4, OperandInfo522 }, // Inst #4150 = t2REVSH + { 3, OperandInfo137 }, // Inst #4151 = t2RFEDB + { 3, OperandInfo137 }, // Inst #4152 = t2RFEDBW + { 3, OperandInfo137 }, // Inst #4153 = t2RFEIA + { 3, OperandInfo137 }, // Inst #4154 = t2RFEIAW + { 6, OperandInfo506 }, // Inst #4155 = t2RORri + { 6, OperandInfo507 }, // Inst #4156 = t2RORrr + { 5, OperandInfo543 }, // Inst #4157 = t2RRX + { 6, OperandInfo506 }, // Inst #4158 = t2RSBri + { 6, OperandInfo507 }, // Inst #4159 = t2RSBrr + { 7, OperandInfo508 }, // Inst #4160 = t2RSBrs + { 5, OperandInfo542 }, // Inst #4161 = t2SADD16 + { 5, OperandInfo542 }, // Inst #4162 = t2SADD8 + { 5, OperandInfo542 }, // Inst #4163 = t2SASX + { 0, 0 }, // Inst #4164 = t2SB + { 6, OperandInfo506 }, // Inst #4165 = t2SBCri + { 6, OperandInfo507 }, // Inst #4166 = t2SBCrr + { 7, OperandInfo508 }, // Inst #4167 = t2SBCrs + { 6, OperandInfo550 }, // Inst #4168 = t2SBFX + { 5, OperandInfo542 }, // Inst #4169 = t2SDIV + { 5, OperandInfo47 }, // Inst #4170 = t2SEL + { 1, OperandInfo2 }, // Inst #4171 = t2SETPAN + { 2, OperandInfo139 }, // Inst #4172 = t2SG + { 5, OperandInfo542 }, // Inst #4173 = t2SHADD16 + { 5, OperandInfo542 }, // Inst #4174 = t2SHADD8 + { 5, OperandInfo542 }, // Inst #4175 = t2SHASX + { 5, OperandInfo542 }, // Inst #4176 = t2SHSAX + { 5, OperandInfo542 }, // Inst #4177 = t2SHSUB16 + { 5, OperandInfo542 }, // Inst #4178 = t2SHSUB8 + { 3, OperandInfo202 }, // Inst #4179 = t2SMC + { 6, OperandInfo537 }, // Inst #4180 = t2SMLABB + { 6, OperandInfo537 }, // Inst #4181 = t2SMLABT + { 6, OperandInfo537 }, // Inst #4182 = t2SMLAD + { 6, OperandInfo537 }, // Inst #4183 = t2SMLADX + { 8, OperandInfo551 }, // Inst #4184 = t2SMLAL + { 8, OperandInfo551 }, // Inst #4185 = t2SMLALBB + { 8, OperandInfo551 }, // Inst #4186 = t2SMLALBT + { 8, OperandInfo551 }, // Inst #4187 = t2SMLALD + { 8, OperandInfo551 }, // Inst #4188 = t2SMLALDX + { 8, OperandInfo551 }, // Inst #4189 = t2SMLALTB + { 8, OperandInfo551 }, // Inst #4190 = t2SMLALTT + { 6, OperandInfo537 }, // Inst #4191 = t2SMLATB + { 6, OperandInfo537 }, // Inst #4192 = t2SMLATT + { 6, OperandInfo537 }, // Inst #4193 = t2SMLAWB + { 6, OperandInfo537 }, // Inst #4194 = t2SMLAWT + { 6, OperandInfo537 }, // Inst #4195 = t2SMLSD + { 6, OperandInfo537 }, // Inst #4196 = t2SMLSDX + { 8, OperandInfo551 }, // Inst #4197 = t2SMLSLD + { 8, OperandInfo551 }, // Inst #4198 = t2SMLSLDX + { 6, OperandInfo537 }, // Inst #4199 = t2SMMLA + { 6, OperandInfo537 }, // Inst #4200 = t2SMMLAR + { 6, OperandInfo537 }, // Inst #4201 = t2SMMLS + { 6, OperandInfo537 }, // Inst #4202 = t2SMMLSR + { 5, OperandInfo542 }, // Inst #4203 = t2SMMUL + { 5, OperandInfo542 }, // Inst #4204 = t2SMMULR + { 5, OperandInfo542 }, // Inst #4205 = t2SMUAD + { 5, OperandInfo542 }, // Inst #4206 = t2SMUADX + { 5, OperandInfo542 }, // Inst #4207 = t2SMULBB + { 5, OperandInfo542 }, // Inst #4208 = t2SMULBT + { 6, OperandInfo537 }, // Inst #4209 = t2SMULL + { 5, OperandInfo542 }, // Inst #4210 = t2SMULTB + { 5, OperandInfo542 }, // Inst #4211 = t2SMULTT + { 5, OperandInfo542 }, // Inst #4212 = t2SMULWB + { 5, OperandInfo542 }, // Inst #4213 = t2SMULWT + { 5, OperandInfo542 }, // Inst #4214 = t2SMUSD + { 5, OperandInfo542 }, // Inst #4215 = t2SMUSDX + { 3, OperandInfo202 }, // Inst #4216 = t2SRSDB + { 3, OperandInfo202 }, // Inst #4217 = t2SRSDB_UPD + { 3, OperandInfo202 }, // Inst #4218 = t2SRSIA + { 3, OperandInfo202 }, // Inst #4219 = t2SRSIA_UPD + { 6, OperandInfo552 }, // Inst #4220 = t2SSAT + { 5, OperandInfo553 }, // Inst #4221 = t2SSAT16 + { 5, OperandInfo542 }, // Inst #4222 = t2SSAX + { 5, OperandInfo542 }, // Inst #4223 = t2SSUB16 + { 5, OperandInfo542 }, // Inst #4224 = t2SSUB8 + { 6, OperandInfo211 }, // Inst #4225 = t2STC2L_OFFSET + { 6, OperandInfo212 }, // Inst #4226 = t2STC2L_OPTION + { 6, OperandInfo211 }, // Inst #4227 = t2STC2L_POST + { 7, OperandInfo213 }, // Inst #4228 = t2STC2L_PRE + { 6, OperandInfo211 }, // Inst #4229 = t2STC2_OFFSET + { 6, OperandInfo212 }, // Inst #4230 = t2STC2_OPTION + { 6, OperandInfo211 }, // Inst #4231 = t2STC2_POST + { 7, OperandInfo213 }, // Inst #4232 = t2STC2_PRE + { 6, OperandInfo211 }, // Inst #4233 = t2STCL_OFFSET + { 6, OperandInfo212 }, // Inst #4234 = t2STCL_OPTION + { 6, OperandInfo211 }, // Inst #4235 = t2STCL_POST + { 7, OperandInfo213 }, // Inst #4236 = t2STCL_PRE + { 6, OperandInfo211 }, // Inst #4237 = t2STC_OFFSET + { 6, OperandInfo212 }, // Inst #4238 = t2STC_OPTION + { 6, OperandInfo211 }, // Inst #4239 = t2STC_POST + { 7, OperandInfo213 }, // Inst #4240 = t2STC_PRE + { 4, OperandInfo526 }, // Inst #4241 = t2STL + { 4, OperandInfo526 }, // Inst #4242 = t2STLB + { 5, OperandInfo554 }, // Inst #4243 = t2STLEX + { 5, OperandInfo554 }, // Inst #4244 = t2STLEXB + { 6, OperandInfo555 }, // Inst #4245 = t2STLEXD + { 5, OperandInfo554 }, // Inst #4246 = t2STLEXH + { 4, OperandInfo526 }, // Inst #4247 = t2STLH + { 4, OperandInfo206 }, // Inst #4248 = t2STMDB + { 5, OperandInfo66 }, // Inst #4249 = t2STMDB_UPD + { 4, OperandInfo206 }, // Inst #4250 = t2STMIA + { 5, OperandInfo66 }, // Inst #4251 = t2STMIA_UPD + { 5, OperandInfo528 }, // Inst #4252 = t2STRBT + { 6, OperandInfo556 }, // Inst #4253 = t2STRB_POST + { 6, OperandInfo556 }, // Inst #4254 = t2STRB_PRE + { 5, OperandInfo528 }, // Inst #4255 = t2STRBi12 + { 5, OperandInfo528 }, // Inst #4256 = t2STRBi8 + { 6, OperandInfo557 }, // Inst #4257 = t2STRBs + { 7, OperandInfo558 }, // Inst #4258 = t2STRD_POST + { 7, OperandInfo558 }, // Inst #4259 = t2STRD_PRE + { 6, OperandInfo532 }, // Inst #4260 = t2STRDi8 + { 6, OperandInfo559 }, // Inst #4261 = t2STREX + { 5, OperandInfo554 }, // Inst #4262 = t2STREXB + { 6, OperandInfo555 }, // Inst #4263 = t2STREXD + { 5, OperandInfo554 }, // Inst #4264 = t2STREXH + { 5, OperandInfo528 }, // Inst #4265 = t2STRHT + { 6, OperandInfo556 }, // Inst #4266 = t2STRH_POST + { 6, OperandInfo556 }, // Inst #4267 = t2STRH_PRE + { 5, OperandInfo528 }, // Inst #4268 = t2STRHi12 + { 5, OperandInfo528 }, // Inst #4269 = t2STRHi8 + { 6, OperandInfo557 }, // Inst #4270 = t2STRHs + { 5, OperandInfo528 }, // Inst #4271 = t2STRT + { 6, OperandInfo560 }, // Inst #4272 = t2STR_POST + { 6, OperandInfo560 }, // Inst #4273 = t2STR_PRE + { 5, OperandInfo87 }, // Inst #4274 = t2STRi12 + { 5, OperandInfo87 }, // Inst #4275 = t2STRi8 + { 6, OperandInfo535 }, // Inst #4276 = t2STRs + { 3, OperandInfo202 }, // Inst #4277 = t2SUBS_PC_LR + { 6, OperandInfo509 }, // Inst #4278 = t2SUBri + { 5, OperandInfo510 }, // Inst #4279 = t2SUBri12 + { 6, OperandInfo511 }, // Inst #4280 = t2SUBrr + { 7, OperandInfo512 }, // Inst #4281 = t2SUBrs + { 6, OperandInfo513 }, // Inst #4282 = t2SUBspImm + { 5, OperandInfo514 }, // Inst #4283 = t2SUBspImm12 + { 6, OperandInfo546 }, // Inst #4284 = t2SXTAB + { 6, OperandInfo546 }, // Inst #4285 = t2SXTAB16 + { 6, OperandInfo546 }, // Inst #4286 = t2SXTAH + { 5, OperandInfo126 }, // Inst #4287 = t2SXTB + { 5, OperandInfo126 }, // Inst #4288 = t2SXTB16 + { 5, OperandInfo126 }, // Inst #4289 = t2SXTH + { 4, OperandInfo561 }, // Inst #4290 = t2TBB + { 4, OperandInfo561 }, // Inst #4291 = t2TBH + { 4, OperandInfo515 }, // Inst #4292 = t2TEQri + { 4, OperandInfo522 }, // Inst #4293 = t2TEQrr + { 5, OperandInfo123 }, // Inst #4294 = t2TEQrs + { 3, OperandInfo202 }, // Inst #4295 = t2TSB + { 4, OperandInfo515 }, // Inst #4296 = t2TSTri + { 4, OperandInfo522 }, // Inst #4297 = t2TSTrr + { 5, OperandInfo123 }, // Inst #4298 = t2TSTrs + { 4, OperandInfo562 }, // Inst #4299 = t2TT + { 4, OperandInfo562 }, // Inst #4300 = t2TTA + { 4, OperandInfo562 }, // Inst #4301 = t2TTAT + { 4, OperandInfo562 }, // Inst #4302 = t2TTT + { 5, OperandInfo542 }, // Inst #4303 = t2UADD16 + { 5, OperandInfo542 }, // Inst #4304 = t2UADD8 + { 5, OperandInfo542 }, // Inst #4305 = t2UASX + { 6, OperandInfo550 }, // Inst #4306 = t2UBFX + { 1, OperandInfo2 }, // Inst #4307 = t2UDF + { 5, OperandInfo542 }, // Inst #4308 = t2UDIV + { 5, OperandInfo542 }, // Inst #4309 = t2UHADD16 + { 5, OperandInfo542 }, // Inst #4310 = t2UHADD8 + { 5, OperandInfo542 }, // Inst #4311 = t2UHASX + { 5, OperandInfo542 }, // Inst #4312 = t2UHSAX + { 5, OperandInfo542 }, // Inst #4313 = t2UHSUB16 + { 5, OperandInfo542 }, // Inst #4314 = t2UHSUB8 + { 8, OperandInfo551 }, // Inst #4315 = t2UMAAL + { 8, OperandInfo551 }, // Inst #4316 = t2UMLAL + { 6, OperandInfo537 }, // Inst #4317 = t2UMULL + { 5, OperandInfo542 }, // Inst #4318 = t2UQADD16 + { 5, OperandInfo542 }, // Inst #4319 = t2UQADD8 + { 5, OperandInfo542 }, // Inst #4320 = t2UQASX + { 5, OperandInfo542 }, // Inst #4321 = t2UQSAX + { 5, OperandInfo542 }, // Inst #4322 = t2UQSUB16 + { 5, OperandInfo542 }, // Inst #4323 = t2UQSUB8 + { 5, OperandInfo542 }, // Inst #4324 = t2USAD8 + { 6, OperandInfo537 }, // Inst #4325 = t2USADA8 + { 6, OperandInfo552 }, // Inst #4326 = t2USAT + { 5, OperandInfo553 }, // Inst #4327 = t2USAT16 + { 5, OperandInfo542 }, // Inst #4328 = t2USAX + { 5, OperandInfo542 }, // Inst #4329 = t2USUB16 + { 5, OperandInfo542 }, // Inst #4330 = t2USUB8 + { 6, OperandInfo546 }, // Inst #4331 = t2UXTAB + { 6, OperandInfo546 }, // Inst #4332 = t2UXTAB16 + { 6, OperandInfo546 }, // Inst #4333 = t2UXTAH + { 5, OperandInfo126 }, // Inst #4334 = t2UXTB + { 5, OperandInfo126 }, // Inst #4335 = t2UXTB16 + { 5, OperandInfo126 }, // Inst #4336 = t2UXTH + { 3, OperandInfo129 }, // Inst #4337 = t2WLS + { 6, OperandInfo563 }, // Inst #4338 = tADC + { 5, OperandInfo75 }, // Inst #4339 = tADDhirr + { 6, OperandInfo564 }, // Inst #4340 = tADDi3 + { 6, OperandInfo565 }, // Inst #4341 = tADDi8 + { 5, OperandInfo566 }, // Inst #4342 = tADDrSP + { 5, OperandInfo567 }, // Inst #4343 = tADDrSPi + { 6, OperandInfo568 }, // Inst #4344 = tADDrr + { 5, OperandInfo569 }, // Inst #4345 = tADDspi + { 5, OperandInfo570 }, // Inst #4346 = tADDspr + { 4, OperandInfo571 }, // Inst #4347 = tADR + { 6, OperandInfo563 }, // Inst #4348 = tAND + { 6, OperandInfo564 }, // Inst #4349 = tASRri + { 6, OperandInfo563 }, // Inst #4350 = tASRrr + { 3, OperandInfo141 }, // Inst #4351 = tB + { 6, OperandInfo563 }, // Inst #4352 = tBIC + { 1, OperandInfo2 }, // Inst #4353 = tBKPT + { 3, OperandInfo110 }, // Inst #4354 = tBL + { 3, OperandInfo572 }, // Inst #4355 = tBLXNSr + { 3, OperandInfo110 }, // Inst #4356 = tBLXi + { 3, OperandInfo573 }, // Inst #4357 = tBLXr + { 3, OperandInfo137 }, // Inst #4358 = tBX + { 3, OperandInfo137 }, // Inst #4359 = tBXNS + { 3, OperandInfo141 }, // Inst #4360 = tBcc + { 2, OperandInfo574 }, // Inst #4361 = tCBNZ + { 2, OperandInfo574 }, // Inst #4362 = tCBZ + { 4, OperandInfo575 }, // Inst #4363 = tCMNz + { 4, OperandInfo197 }, // Inst #4364 = tCMPhir + { 4, OperandInfo145 }, // Inst #4365 = tCMPi8 + { 4, OperandInfo575 }, // Inst #4366 = tCMPr + { 2, OperandInfo7 }, // Inst #4367 = tCPS + { 6, OperandInfo563 }, // Inst #4368 = tEOR + { 3, OperandInfo202 }, // Inst #4369 = tHINT + { 1, OperandInfo2 }, // Inst #4370 = tHLT + { 2, OperandInfo45 }, // Inst #4371 = tInt_WIN_eh_sjlj_longjmp + { 2, OperandInfo151 }, // Inst #4372 = tInt_eh_sjlj_longjmp + { 2, OperandInfo151 }, // Inst #4373 = tInt_eh_sjlj_setjmp + { 4, OperandInfo576 }, // Inst #4374 = tLDMIA + { 5, OperandInfo577 }, // Inst #4375 = tLDRBi + { 5, OperandInfo578 }, // Inst #4376 = tLDRBr + { 5, OperandInfo577 }, // Inst #4377 = tLDRHi + { 5, OperandInfo578 }, // Inst #4378 = tLDRHr + { 5, OperandInfo578 }, // Inst #4379 = tLDRSB + { 5, OperandInfo578 }, // Inst #4380 = tLDRSH + { 5, OperandInfo577 }, // Inst #4381 = tLDRi + { 4, OperandInfo579 }, // Inst #4382 = tLDRpci + { 5, OperandInfo578 }, // Inst #4383 = tLDRr + { 5, OperandInfo580 }, // Inst #4384 = tLDRspi + { 6, OperandInfo564 }, // Inst #4385 = tLSLri + { 6, OperandInfo563 }, // Inst #4386 = tLSLrr + { 6, OperandInfo564 }, // Inst #4387 = tLSRri + { 6, OperandInfo563 }, // Inst #4388 = tLSRrr + { 2, OperandInfo151 }, // Inst #4389 = tMOVSr + { 5, OperandInfo581 }, // Inst #4390 = tMOVi8 + { 4, OperandInfo197 }, // Inst #4391 = tMOVr + { 6, OperandInfo582 }, // Inst #4392 = tMUL + { 5, OperandInfo583 }, // Inst #4393 = tMVN + { 6, OperandInfo563 }, // Inst #4394 = tORR + { 3, OperandInfo584 }, // Inst #4395 = tPICADD + { 3, OperandInfo150 }, // Inst #4396 = tPOP + { 3, OperandInfo150 }, // Inst #4397 = tPUSH + { 4, OperandInfo575 }, // Inst #4398 = tREV + { 4, OperandInfo575 }, // Inst #4399 = tREV16 + { 4, OperandInfo575 }, // Inst #4400 = tREVSH + { 6, OperandInfo563 }, // Inst #4401 = tROR + { 5, OperandInfo583 }, // Inst #4402 = tRSB + { 6, OperandInfo563 }, // Inst #4403 = tSBC + { 1, OperandInfo2 }, // Inst #4404 = tSETEND + { 5, OperandInfo144 }, // Inst #4405 = tSTMIA_UPD + { 5, OperandInfo577 }, // Inst #4406 = tSTRBi + { 5, OperandInfo578 }, // Inst #4407 = tSTRBr + { 5, OperandInfo577 }, // Inst #4408 = tSTRHi + { 5, OperandInfo578 }, // Inst #4409 = tSTRHr + { 5, OperandInfo577 }, // Inst #4410 = tSTRi + { 5, OperandInfo578 }, // Inst #4411 = tSTRr + { 5, OperandInfo580 }, // Inst #4412 = tSTRspi + { 6, OperandInfo564 }, // Inst #4413 = tSUBi3 + { 6, OperandInfo565 }, // Inst #4414 = tSUBi8 + { 6, OperandInfo568 }, // Inst #4415 = tSUBrr + { 5, OperandInfo569 }, // Inst #4416 = tSUBspi + { 3, OperandInfo202 }, // Inst #4417 = tSVC + { 4, OperandInfo575 }, // Inst #4418 = tSXTB + { 4, OperandInfo575 }, // Inst #4419 = tSXTH + { 0, 0 }, // Inst #4420 = tTRAP + { 4, OperandInfo575 }, // Inst #4421 = tTST + { 1, OperandInfo2 }, // Inst #4422 = tUDF + { 4, OperandInfo575 }, // Inst #4423 = tUXTB + { 4, OperandInfo575 }, // Inst #4424 = tUXTH + { 0, 0 }, // Inst #4425 = t__brkdiv0 +}; + +#endif // GET_INSTRINFO_MC_DESC diff --git a/thirdparty/capstone/arch/ARM/ARMGenRegisterInfo.inc b/thirdparty/capstone/arch/ARM/ARMGenRegisterInfo.inc new file mode 100644 index 0000000..953621b --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMGenRegisterInfo.inc @@ -0,0 +1,7572 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +enum { + ARM_NoRegister, + ARM_APSR = 1, + ARM_APSR_NZCV = 2, + ARM_CPSR = 3, + ARM_FPCXTNS = 4, + ARM_FPCXTS = 5, + ARM_FPEXC = 6, + ARM_FPINST = 7, + ARM_FPSCR = 8, + ARM_FPSCR_NZCV = 9, + ARM_FPSCR_NZCVQC = 10, + ARM_FPSID = 11, + ARM_ITSTATE = 12, + ARM_LR = 13, + ARM_PC = 14, + ARM_RA_AUTH_CODE = 15, + ARM_SP = 16, + ARM_SPSR = 17, + ARM_VPR = 18, + ARM_ZR = 19, + ARM_D0 = 20, + ARM_D1 = 21, + ARM_D2 = 22, + ARM_D3 = 23, + ARM_D4 = 24, + ARM_D5 = 25, + ARM_D6 = 26, + ARM_D7 = 27, + ARM_D8 = 28, + ARM_D9 = 29, + ARM_D10 = 30, + ARM_D11 = 31, + ARM_D12 = 32, + ARM_D13 = 33, + ARM_D14 = 34, + ARM_D15 = 35, + ARM_D16 = 36, + ARM_D17 = 37, + ARM_D18 = 38, + ARM_D19 = 39, + ARM_D20 = 40, + ARM_D21 = 41, + ARM_D22 = 42, + ARM_D23 = 43, + ARM_D24 = 44, + ARM_D25 = 45, + ARM_D26 = 46, + ARM_D27 = 47, + ARM_D28 = 48, + ARM_D29 = 49, + ARM_D30 = 50, + ARM_D31 = 51, + ARM_FPINST2 = 52, + ARM_MVFR0 = 53, + ARM_MVFR1 = 54, + ARM_MVFR2 = 55, + ARM_P0 = 56, + ARM_Q0 = 57, + ARM_Q1 = 58, + ARM_Q2 = 59, + ARM_Q3 = 60, + ARM_Q4 = 61, + ARM_Q5 = 62, + ARM_Q6 = 63, + ARM_Q7 = 64, + ARM_Q8 = 65, + ARM_Q9 = 66, + ARM_Q10 = 67, + ARM_Q11 = 68, + ARM_Q12 = 69, + ARM_Q13 = 70, + ARM_Q14 = 71, + ARM_Q15 = 72, + ARM_R0 = 73, + ARM_R1 = 74, + ARM_R2 = 75, + ARM_R3 = 76, + ARM_R4 = 77, + ARM_R5 = 78, + ARM_R6 = 79, + ARM_R7 = 80, + ARM_R8 = 81, + ARM_R9 = 82, + ARM_R10 = 83, + ARM_R11 = 84, + ARM_R12 = 85, + ARM_S0 = 86, + ARM_S1 = 87, + ARM_S2 = 88, + ARM_S3 = 89, + ARM_S4 = 90, + ARM_S5 = 91, + ARM_S6 = 92, + ARM_S7 = 93, + ARM_S8 = 94, + ARM_S9 = 95, + ARM_S10 = 96, + ARM_S11 = 97, + ARM_S12 = 98, + ARM_S13 = 99, + ARM_S14 = 100, + ARM_S15 = 101, + ARM_S16 = 102, + ARM_S17 = 103, + ARM_S18 = 104, + ARM_S19 = 105, + ARM_S20 = 106, + ARM_S21 = 107, + ARM_S22 = 108, + ARM_S23 = 109, + ARM_S24 = 110, + ARM_S25 = 111, + ARM_S26 = 112, + ARM_S27 = 113, + ARM_S28 = 114, + ARM_S29 = 115, + ARM_S30 = 116, + ARM_S31 = 117, + ARM_D0_D2 = 118, + ARM_D1_D3 = 119, + ARM_D2_D4 = 120, + ARM_D3_D5 = 121, + ARM_D4_D6 = 122, + ARM_D5_D7 = 123, + ARM_D6_D8 = 124, + ARM_D7_D9 = 125, + ARM_D8_D10 = 126, + ARM_D9_D11 = 127, + ARM_D10_D12 = 128, + ARM_D11_D13 = 129, + ARM_D12_D14 = 130, + ARM_D13_D15 = 131, + ARM_D14_D16 = 132, + ARM_D15_D17 = 133, + ARM_D16_D18 = 134, + ARM_D17_D19 = 135, + ARM_D18_D20 = 136, + ARM_D19_D21 = 137, + ARM_D20_D22 = 138, + ARM_D21_D23 = 139, + ARM_D22_D24 = 140, + ARM_D23_D25 = 141, + ARM_D24_D26 = 142, + ARM_D25_D27 = 143, + ARM_D26_D28 = 144, + ARM_D27_D29 = 145, + ARM_D28_D30 = 146, + ARM_D29_D31 = 147, + ARM_Q0_Q1 = 148, + ARM_Q1_Q2 = 149, + ARM_Q2_Q3 = 150, + ARM_Q3_Q4 = 151, + ARM_Q4_Q5 = 152, + ARM_Q5_Q6 = 153, + ARM_Q6_Q7 = 154, + ARM_Q7_Q8 = 155, + ARM_Q8_Q9 = 156, + ARM_Q9_Q10 = 157, + ARM_Q10_Q11 = 158, + ARM_Q11_Q12 = 159, + ARM_Q12_Q13 = 160, + ARM_Q13_Q14 = 161, + ARM_Q14_Q15 = 162, + ARM_Q0_Q1_Q2_Q3 = 163, + ARM_Q1_Q2_Q3_Q4 = 164, + ARM_Q2_Q3_Q4_Q5 = 165, + ARM_Q3_Q4_Q5_Q6 = 166, + ARM_Q4_Q5_Q6_Q7 = 167, + ARM_Q5_Q6_Q7_Q8 = 168, + ARM_Q6_Q7_Q8_Q9 = 169, + ARM_Q7_Q8_Q9_Q10 = 170, + ARM_Q8_Q9_Q10_Q11 = 171, + ARM_Q9_Q10_Q11_Q12 = 172, + ARM_Q10_Q11_Q12_Q13 = 173, + ARM_Q11_Q12_Q13_Q14 = 174, + ARM_Q12_Q13_Q14_Q15 = 175, + ARM_R0_R1 = 176, + ARM_R2_R3 = 177, + ARM_R4_R5 = 178, + ARM_R6_R7 = 179, + ARM_R8_R9 = 180, + ARM_R10_R11 = 181, + ARM_R12_SP = 182, + ARM_D0_D1_D2 = 183, + ARM_D1_D2_D3 = 184, + ARM_D2_D3_D4 = 185, + ARM_D3_D4_D5 = 186, + ARM_D4_D5_D6 = 187, + ARM_D5_D6_D7 = 188, + ARM_D6_D7_D8 = 189, + ARM_D7_D8_D9 = 190, + ARM_D8_D9_D10 = 191, + ARM_D9_D10_D11 = 192, + ARM_D10_D11_D12 = 193, + ARM_D11_D12_D13 = 194, + ARM_D12_D13_D14 = 195, + ARM_D13_D14_D15 = 196, + ARM_D14_D15_D16 = 197, + ARM_D15_D16_D17 = 198, + ARM_D16_D17_D18 = 199, + ARM_D17_D18_D19 = 200, + ARM_D18_D19_D20 = 201, + ARM_D19_D20_D21 = 202, + ARM_D20_D21_D22 = 203, + ARM_D21_D22_D23 = 204, + ARM_D22_D23_D24 = 205, + ARM_D23_D24_D25 = 206, + ARM_D24_D25_D26 = 207, + ARM_D25_D26_D27 = 208, + ARM_D26_D27_D28 = 209, + ARM_D27_D28_D29 = 210, + ARM_D28_D29_D30 = 211, + ARM_D29_D30_D31 = 212, + ARM_D0_D2_D4 = 213, + ARM_D1_D3_D5 = 214, + ARM_D2_D4_D6 = 215, + ARM_D3_D5_D7 = 216, + ARM_D4_D6_D8 = 217, + ARM_D5_D7_D9 = 218, + ARM_D6_D8_D10 = 219, + ARM_D7_D9_D11 = 220, + ARM_D8_D10_D12 = 221, + ARM_D9_D11_D13 = 222, + ARM_D10_D12_D14 = 223, + ARM_D11_D13_D15 = 224, + ARM_D12_D14_D16 = 225, + ARM_D13_D15_D17 = 226, + ARM_D14_D16_D18 = 227, + ARM_D15_D17_D19 = 228, + ARM_D16_D18_D20 = 229, + ARM_D17_D19_D21 = 230, + ARM_D18_D20_D22 = 231, + ARM_D19_D21_D23 = 232, + ARM_D20_D22_D24 = 233, + ARM_D21_D23_D25 = 234, + ARM_D22_D24_D26 = 235, + ARM_D23_D25_D27 = 236, + ARM_D24_D26_D28 = 237, + ARM_D25_D27_D29 = 238, + ARM_D26_D28_D30 = 239, + ARM_D27_D29_D31 = 240, + ARM_D0_D2_D4_D6 = 241, + ARM_D1_D3_D5_D7 = 242, + ARM_D2_D4_D6_D8 = 243, + ARM_D3_D5_D7_D9 = 244, + ARM_D4_D6_D8_D10 = 245, + ARM_D5_D7_D9_D11 = 246, + ARM_D6_D8_D10_D12 = 247, + ARM_D7_D9_D11_D13 = 248, + ARM_D8_D10_D12_D14 = 249, + ARM_D9_D11_D13_D15 = 250, + ARM_D10_D12_D14_D16 = 251, + ARM_D11_D13_D15_D17 = 252, + ARM_D12_D14_D16_D18 = 253, + ARM_D13_D15_D17_D19 = 254, + ARM_D14_D16_D18_D20 = 255, + ARM_D15_D17_D19_D21 = 256, + ARM_D16_D18_D20_D22 = 257, + ARM_D17_D19_D21_D23 = 258, + ARM_D18_D20_D22_D24 = 259, + ARM_D19_D21_D23_D25 = 260, + ARM_D20_D22_D24_D26 = 261, + ARM_D21_D23_D25_D27 = 262, + ARM_D22_D24_D26_D28 = 263, + ARM_D23_D25_D27_D29 = 264, + ARM_D24_D26_D28_D30 = 265, + ARM_D25_D27_D29_D31 = 266, + ARM_D1_D2 = 267, + ARM_D3_D4 = 268, + ARM_D5_D6 = 269, + ARM_D7_D8 = 270, + ARM_D9_D10 = 271, + ARM_D11_D12 = 272, + ARM_D13_D14 = 273, + ARM_D15_D16 = 274, + ARM_D17_D18 = 275, + ARM_D19_D20 = 276, + ARM_D21_D22 = 277, + ARM_D23_D24 = 278, + ARM_D25_D26 = 279, + ARM_D27_D28 = 280, + ARM_D29_D30 = 281, + ARM_D1_D2_D3_D4 = 282, + ARM_D3_D4_D5_D6 = 283, + ARM_D5_D6_D7_D8 = 284, + ARM_D7_D8_D9_D10 = 285, + ARM_D9_D10_D11_D12 = 286, + ARM_D11_D12_D13_D14 = 287, + ARM_D13_D14_D15_D16 = 288, + ARM_D15_D16_D17_D18 = 289, + ARM_D17_D18_D19_D20 = 290, + ARM_D19_D20_D21_D22 = 291, + ARM_D21_D22_D23_D24 = 292, + ARM_D23_D24_D25_D26 = 293, + ARM_D25_D26_D27_D28 = 294, + ARM_D27_D28_D29_D30 = 295, + NUM_TARGET_REGS // 296 +}; + +// Register classes + +enum { + ARM_HPRRegClassID = 0, + ARM_FPWithVPRRegClassID = 1, + ARM_SPRRegClassID = 2, + ARM_FPWithVPR_with_ssub_0RegClassID = 3, + ARM_GPRRegClassID = 4, + ARM_GPRwithAPSRRegClassID = 5, + ARM_GPRwithZRRegClassID = 6, + ARM_SPR_8RegClassID = 7, + ARM_GPRnopcRegClassID = 8, + ARM_GPRnospRegClassID = 9, + ARM_GPRwithAPSR_NZCVnospRegClassID = 10, + ARM_GPRwithAPSRnospRegClassID = 11, + ARM_GPRwithZRnospRegClassID = 12, + ARM_GPRnoipRegClassID = 13, + ARM_rGPRRegClassID = 14, + ARM_GPRnoip_and_GPRnopcRegClassID = 15, + ARM_GPRnoip_and_GPRnospRegClassID = 16, + ARM_GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID = 17, + ARM_tGPRwithpcRegClassID = 18, + ARM_FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID = 19, + ARM_hGPRRegClassID = 20, + ARM_tGPRRegClassID = 21, + ARM_tGPREvenRegClassID = 22, + ARM_GPRnopc_and_hGPRRegClassID = 23, + ARM_GPRnosp_and_hGPRRegClassID = 24, + ARM_GPRnoip_and_hGPRRegClassID = 25, + ARM_GPRnoip_and_tGPREvenRegClassID = 26, + ARM_GPRnosp_and_GPRnopc_and_hGPRRegClassID = 27, + ARM_tGPROddRegClassID = 28, + ARM_GPRnopc_and_GPRnoip_and_hGPRRegClassID = 29, + ARM_GPRnosp_and_GPRnoip_and_hGPRRegClassID = 30, + ARM_tcGPRRegClassID = 31, + ARM_GPRnoip_and_tcGPRRegClassID = 32, + ARM_GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID = 33, + ARM_hGPR_and_tGPREvenRegClassID = 34, + ARM_tGPR_and_tGPREvenRegClassID = 35, + ARM_tGPR_and_tGPROddRegClassID = 36, + ARM_tGPREven_and_tcGPRRegClassID = 37, + ARM_hGPR_and_GPRnoip_and_tGPREvenRegClassID = 38, + ARM_hGPR_and_tGPROddRegClassID = 39, + ARM_tGPREven_and_GPRnoip_and_tcGPRRegClassID = 40, + ARM_tGPROdd_and_tcGPRRegClassID = 41, + ARM_CCRRegClassID = 42, + ARM_FPCXTRegsRegClassID = 43, + ARM_GPRlrRegClassID = 44, + ARM_GPRspRegClassID = 45, + ARM_VCCRRegClassID = 46, + ARM_cl_FPSCR_NZCVRegClassID = 47, + ARM_hGPR_and_tGPRwithpcRegClassID = 48, + ARM_hGPR_and_tcGPRRegClassID = 49, + ARM_DPRRegClassID = 50, + ARM_DPR_VFP2RegClassID = 51, + ARM_DPR_8RegClassID = 52, + ARM_GPRPairRegClassID = 53, + ARM_GPRPairnospRegClassID = 54, + ARM_GPRPair_with_gsub_0_in_tGPRRegClassID = 55, + ARM_GPRPair_with_gsub_0_in_hGPRRegClassID = 56, + ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID = 57, + ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID = 58, + ARM_GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID = 59, + ARM_GPRPair_with_gsub_1_in_GPRspRegClassID = 60, + ARM_DPairSpcRegClassID = 61, + ARM_DPairSpc_with_ssub_0RegClassID = 62, + ARM_DPairSpc_with_ssub_4RegClassID = 63, + ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID = 64, + ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID = 65, + ARM_DPairRegClassID = 66, + ARM_DPair_with_ssub_0RegClassID = 67, + ARM_QPRRegClassID = 68, + ARM_DPair_with_ssub_2RegClassID = 69, + ARM_DPair_with_dsub_0_in_DPR_8RegClassID = 70, + ARM_MQPRRegClassID = 71, + ARM_QPR_VFP2RegClassID = 72, + ARM_DPair_with_dsub_1_in_DPR_8RegClassID = 73, + ARM_QPR_8RegClassID = 74, + ARM_DTripleRegClassID = 75, + ARM_DTripleSpcRegClassID = 76, + ARM_DTripleSpc_with_ssub_0RegClassID = 77, + ARM_DTriple_with_ssub_0RegClassID = 78, + ARM_DTriple_with_qsub_0_in_QPRRegClassID = 79, + ARM_DTriple_with_ssub_2RegClassID = 80, + ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 81, + ARM_DTripleSpc_with_ssub_4RegClassID = 82, + ARM_DTriple_with_ssub_4RegClassID = 83, + ARM_DTripleSpc_with_ssub_8RegClassID = 84, + ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 85, + ARM_DTriple_with_dsub_0_in_DPR_8RegClassID = 86, + ARM_DTriple_with_qsub_0_in_MQPRRegClassID = 87, + ARM_DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = + 88, + ARM_DTriple_with_dsub_1_in_DPR_8RegClassID = 89, + ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 90, + ARM_DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID = 91, + ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 92, + ARM_DTriple_with_dsub_2_in_DPR_8RegClassID = 93, + ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 94, + ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = + 95, + ARM_DTriple_with_qsub_0_in_QPR_8RegClassID = 96, + ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClassID = + 97, + ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 98, + ARM_DQuadSpcRegClassID = 99, + ARM_DQuadSpc_with_ssub_0RegClassID = 100, + ARM_DQuadSpc_with_ssub_4RegClassID = 101, + ARM_DQuadSpc_with_ssub_8RegClassID = 102, + ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 103, + ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 104, + ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 105, + ARM_DQuadRegClassID = 106, + ARM_DQuad_with_ssub_0RegClassID = 107, + ARM_DQuad_with_ssub_2RegClassID = 108, + ARM_QQPRRegClassID = 109, + ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 110, + ARM_DQuad_with_ssub_4RegClassID = 111, + ARM_DQuad_with_ssub_6RegClassID = 112, + ARM_DQuad_with_dsub_0_in_DPR_8RegClassID = 113, + ARM_DQuad_with_qsub_0_in_MQPRRegClassID = 114, + ARM_DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = + 115, + ARM_DQuad_with_dsub_1_in_DPR_8RegClassID = 116, + ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 117, + ARM_MQQPRRegClassID = 118, + ARM_DQuad_with_dsub_2_in_DPR_8RegClassID = 119, + ARM_DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = + 120, + ARM_DQuad_with_dsub_3_in_DPR_8RegClassID = 121, + ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = + 122, + ARM_DQuad_with_qsub_0_in_QPR_8RegClassID = 123, + ARM_DQuad_with_qsub_1_in_QPR_8RegClassID = 124, + ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 125, + ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = + 126, + ARM_QQQQPRRegClassID = 127, + ARM_QQQQPR_with_ssub_0RegClassID = 128, + ARM_QQQQPR_with_ssub_4RegClassID = 129, + ARM_QQQQPR_with_ssub_8RegClassID = 130, + ARM_MQQQQPRRegClassID = 131, + ARM_MQQQQPR_with_dsub_0_in_DPR_8RegClassID = 132, + ARM_MQQQQPR_with_dsub_2_in_DPR_8RegClassID = 133, + ARM_MQQQQPR_with_dsub_4_in_DPR_8RegClassID = 134, + ARM_MQQQQPR_with_dsub_6_in_DPR_8RegClassID = 135, + +}; + +// Register alternate name indices + +enum { + ARM_NoRegAltName, // 0 + ARM_RegNamesRaw, // 1 + NUM_TARGET_REG_ALT_NAMES = 2 +}; + +// Subregister indices + +enum { + ARM_NoSubRegister, + ARM_dsub_0, // 1 + ARM_dsub_1, // 2 + ARM_dsub_2, // 3 + ARM_dsub_3, // 4 + ARM_dsub_4, // 5 + ARM_dsub_5, // 6 + ARM_dsub_6, // 7 + ARM_dsub_7, // 8 + ARM_gsub_0, // 9 + ARM_gsub_1, // 10 + ARM_qqsub_0, // 11 + ARM_qqsub_1, // 12 + ARM_qsub_0, // 13 + ARM_qsub_1, // 14 + ARM_qsub_2, // 15 + ARM_qsub_3, // 16 + ARM_ssub_0, // 17 + ARM_ssub_1, // 18 + ARM_ssub_2, // 19 + ARM_ssub_3, // 20 + ARM_ssub_4, // 21 + ARM_ssub_5, // 22 + ARM_ssub_6, // 23 + ARM_ssub_7, // 24 + ARM_ssub_8, // 25 + ARM_ssub_9, // 26 + ARM_ssub_10, // 27 + ARM_ssub_11, // 28 + ARM_ssub_12, // 29 + ARM_ssub_13, // 30 + ARM_ssub_14, // 31 + ARM_ssub_15, // 32 + ARM_ssub_0_ssub_1_ssub_4_ssub_5, // 33 + ARM_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, // 34 + ARM_ssub_2_ssub_3_ssub_6_ssub_7, // 35 + ARM_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, // 36 + ARM_ssub_2_ssub_3_ssub_4_ssub_5, // 37 + ARM_ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, // 38 + ARM_ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 39 + ARM_ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40 + ARM_ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7, // 41 + ARM_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 42 + ARM_ssub_4_ssub_5_ssub_8_ssub_9, // 43 + ARM_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 44 + ARM_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 45 + ARM_ssub_6_ssub_7_dsub_5, // 46 + ARM_ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47 + ARM_ssub_6_ssub_7_dsub_5_dsub_7, // 48 + ARM_ssub_6_ssub_7_ssub_8_ssub_9, // 49 + ARM_ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50 + ARM_ssub_8_ssub_9_ssub_12_ssub_13, // 51 + ARM_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52 + ARM_dsub_5_dsub_7, // 53 + ARM_dsub_5_ssub_12_ssub_13_dsub_7, // 54 + ARM_dsub_5_ssub_12_ssub_13, // 55 + ARM_ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56 + ARM_NUM_TARGET_SUBREGS +}; +#endif // GET_REGINFO_ENUM + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg ARMRegDiffLists[] = { + /* 0 */ -634, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 17 */ 38, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 32 */ 42, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 45 */ 46, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 56 */ -1108, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 65 */ -574, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 74 */ -292, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 83 */ 44, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 91 */ 46, + 1, + 1, + 1, + 1, + 1, + 0, + /* 98 */ -348, + 1, + 1, + 1, + 1, + 1, + 0, + /* 105 */ 46, + 1, + 1, + 1, + 1, + 0, + /* 111 */ 48, + 1, + 1, + 1, + 1, + 0, + /* 117 */ 48, + 1, + 1, + 1, + 0, + /* 122 */ -1048, + 1, + 1, + 1, + 0, + /* 127 */ -529, + 1, + 1, + 1, + 0, + /* 132 */ -262, + 1, + 1, + 1, + 0, + /* 137 */ -210, + 1, + 1, + 1, + 0, + /* 142 */ 13, + 1, + 1, + 0, + /* 146 */ 48, + 1, + 1, + 0, + /* 150 */ -149, + 1, + 1, + 0, + /* 154 */ 137, + -47, + 48, + -47, + 12, + 121, + -120, + 1, + 1, + 0, + /* 164 */ 136, + -46, + 47, + -46, + 12, + 121, + -120, + 1, + 1, + 0, + /* 174 */ 135, + -45, + 46, + -45, + 12, + 121, + -120, + 1, + 1, + 0, + /* 184 */ 134, + -44, + 45, + -44, + 12, + 121, + -120, + 1, + 1, + 0, + /* 194 */ 133, + -43, + 44, + -43, + 12, + 121, + -120, + 1, + 1, + 0, + /* 204 */ 132, + -42, + 43, + -42, + 12, + 121, + -120, + 1, + 1, + 0, + /* 214 */ 131, + -41, + 42, + -41, + 12, + 121, + -120, + 1, + 1, + 0, + /* 224 */ 130, + -40, + 41, + -40, + 12, + 121, + -120, + 1, + 1, + 0, + /* 234 */ 129, + -39, + 40, + -39, + 12, + 121, + -120, + 1, + 1, + 0, + /* 244 */ 128, + -38, + 39, + -38, + 12, + 121, + -120, + 1, + 1, + 0, + /* 254 */ -47, + 133, + -120, + 1, + 1, + 0, + /* 260 */ -46, + 133, + -120, + 1, + 1, + 0, + /* 266 */ -45, + 133, + -120, + 1, + 1, + 0, + /* 272 */ -44, + 133, + -120, + 1, + 1, + 0, + /* 278 */ -43, + 133, + -120, + 1, + 1, + 0, + /* 284 */ -42, + 133, + -120, + 1, + 1, + 0, + /* 290 */ -41, + 133, + -120, + 1, + 1, + 0, + /* 296 */ -40, + 133, + -120, + 1, + 1, + 0, + /* 302 */ -39, + 133, + -120, + 1, + 1, + 0, + /* 308 */ -38, + 133, + -120, + 1, + 1, + 0, + /* 314 */ 127, + -37, + 38, + -37, + 133, + -120, + 1, + 1, + 0, + /* 323 */ -464, + 1, + 3, + 1, + 3, + 1, + 3, + 1, + 0, + /* 332 */ -408, + 1, + 3, + 1, + 3, + 1, + 0, + /* 339 */ -218, + 1, + 3, + 1, + 0, + /* 344 */ 13, + 1, + 0, + /* 347 */ 14, + 1, + 0, + /* 350 */ 66, + 1, + 0, + /* 353 */ -37, + 66, + 1, + -66, + 67, + 1, + 0, + /* 360 */ -246, + 67, + 1, + -67, + 68, + 1, + 0, + /* 367 */ -98, + 66, + 1, + -65, + 68, + 1, + 0, + /* 374 */ -36, + 68, + 1, + -68, + 69, + 1, + 0, + /* 381 */ -98, + 67, + 1, + -66, + 69, + 1, + 0, + /* 388 */ -245, + 69, + 1, + -69, + 70, + 1, + 0, + /* 395 */ -98, + 68, + 1, + -67, + 70, + 1, + 0, + /* 402 */ -35, + 70, + 1, + -70, + 71, + 1, + 0, + /* 409 */ -98, + 69, + 1, + -68, + 71, + 1, + 0, + /* 416 */ -244, + 71, + 1, + -71, + 72, + 1, + 0, + /* 423 */ -98, + 70, + 1, + -69, + 72, + 1, + 0, + /* 430 */ -34, + 72, + 1, + -72, + 73, + 1, + 0, + /* 437 */ -98, + 71, + 1, + -70, + 73, + 1, + 0, + /* 444 */ -243, + 73, + 1, + -73, + 74, + 1, + 0, + /* 451 */ -98, + 72, + 1, + -71, + 74, + 1, + 0, + /* 458 */ -33, + 74, + 1, + -74, + 75, + 1, + 0, + /* 465 */ -98, + 73, + 1, + -72, + 75, + 1, + 0, + /* 472 */ -242, + 75, + 1, + -75, + 76, + 1, + 0, + /* 479 */ -98, + 74, + 1, + -73, + 76, + 1, + 0, + /* 486 */ -32, + 76, + 1, + -76, + 77, + 1, + 0, + /* 493 */ -98, + 75, + 1, + -74, + 77, + 1, + 0, + /* 500 */ -241, + 77, + 1, + -77, + 78, + 1, + 0, + /* 507 */ -98, + 76, + 1, + -75, + 78, + 1, + 0, + /* 514 */ -31, + 78, + 1, + -78, + 79, + 1, + 0, + /* 521 */ -98, + 77, + 1, + -76, + 79, + 1, + 0, + /* 528 */ -240, + 79, + 1, + -79, + 80, + 1, + 0, + /* 535 */ -98, + 78, + 1, + -77, + 80, + 1, + 0, + /* 542 */ -30, + 80, + 1, + -80, + 81, + 1, + 0, + /* 549 */ -98, + 79, + 1, + -78, + 81, + 1, + 0, + /* 556 */ -499, + 1, + 0, + /* 559 */ -281, + 1, + 0, + /* 562 */ -238, + 1, + 0, + /* 565 */ -237, + 1, + 0, + /* 568 */ -236, + 1, + 0, + /* 571 */ -235, + 1, + 0, + /* 574 */ -234, + 1, + 0, + /* 577 */ -233, + 1, + 0, + /* 580 */ -232, + 1, + 0, + /* 583 */ -83, + 1, + -37, + 133, + 1, + -120, + 1, + 0, + /* 591 */ 138, + -48, + 49, + -48, + 12, + 121, + -120, + 1, + 0, + /* 600 */ -48, + 13, + 121, + -120, + 1, + 0, + /* 606 */ -47, + 13, + 121, + -120, + 1, + 0, + /* 612 */ -46, + 13, + 121, + -120, + 1, + 0, + /* 618 */ -45, + 13, + 121, + -120, + 1, + 0, + /* 624 */ -44, + 13, + 121, + -120, + 1, + 0, + /* 630 */ -43, + 13, + 121, + -120, + 1, + 0, + /* 636 */ -42, + 13, + 121, + -120, + 1, + 0, + /* 642 */ -41, + 13, + 121, + -120, + 1, + 0, + /* 648 */ -40, + 13, + 121, + -120, + 1, + 0, + /* 654 */ -39, + 13, + 121, + -120, + 1, + 0, + /* 660 */ -38, + 13, + 121, + -120, + 1, + 0, + /* 666 */ -72, + 1, + -48, + 133, + -120, + 121, + -120, + 1, + 0, + /* 675 */ -73, + 1, + -47, + 133, + -120, + 121, + -120, + 1, + 0, + /* 684 */ -74, + 1, + -46, + 133, + -120, + 121, + -120, + 1, + 0, + /* 693 */ -75, + 1, + -45, + 133, + -120, + 121, + -120, + 1, + 0, + /* 702 */ -76, + 1, + -44, + 133, + -120, + 121, + -120, + 1, + 0, + /* 711 */ -77, + 1, + -43, + 133, + -120, + 121, + -120, + 1, + 0, + /* 720 */ -78, + 1, + -42, + 133, + -120, + 121, + -120, + 1, + 0, + /* 729 */ -79, + 1, + -41, + 133, + -120, + 121, + -120, + 1, + 0, + /* 738 */ -80, + 1, + -40, + 133, + -120, + 121, + -120, + 1, + 0, + /* 747 */ -81, + 1, + -39, + 133, + -120, + 121, + -120, + 1, + 0, + /* 756 */ -82, + 1, + -38, + 133, + -120, + 121, + -120, + 1, + 0, + /* 765 */ -48, + 133, + -120, + 1, + 0, + /* 770 */ -37, + 134, + -120, + 1, + 0, + /* 775 */ 126, + -36, + 37, + -36, + 133, + -119, + 1, + 0, + /* 783 */ -103, + 1, + 0, + /* 786 */ -102, + 1, + 0, + /* 789 */ -101, + 1, + 0, + /* 792 */ -100, + 1, + 0, + /* 795 */ -99, + 1, + 0, + /* 798 */ -98, + 1, + 0, + /* 801 */ -80, + 1, + 0, + /* 804 */ -29, + 1, + 0, + /* 807 */ -28, + 1, + 0, + /* 810 */ -27, + 1, + 0, + /* 813 */ -26, + 1, + 0, + /* 816 */ -25, + 1, + 0, + /* 819 */ -24, + 1, + 0, + /* 822 */ -23, + 1, + 0, + /* 825 */ -22, + 1, + 0, + /* 828 */ -464, + 1, + 3, + 1, + 3, + 1, + 2, + 0, + /* 836 */ -408, + 1, + 3, + 1, + 2, + 0, + /* 842 */ -218, + 1, + 2, + 0, + /* 846 */ -464, + 1, + 3, + 1, + 2, + 2, + 0, + /* 853 */ -408, + 1, + 2, + 2, + 0, + /* 858 */ -464, + 1, + 2, + 2, + 2, + 0, + /* 864 */ -207, + 2, + 2, + 2, + 0, + /* 869 */ -464, + 1, + 3, + 2, + 2, + 0, + /* 875 */ -179, + 2, + 2, + 0, + /* 879 */ -464, + 1, + 3, + 1, + 3, + 2, + 0, + /* 886 */ -408, + 1, + 3, + 2, + 0, + /* 891 */ -193, + 77, + 1, + -76, + 79, + 1, + -78, + 81, + 1, + 12, + 2, + 0, + /* 903 */ -193, + 76, + 1, + -75, + 78, + 1, + -77, + 80, + 1, + 13, + 2, + 0, + /* 915 */ -193, + 75, + 1, + -74, + 77, + 1, + -76, + 79, + 1, + 14, + 2, + 0, + /* 927 */ -193, + 74, + 1, + -73, + 76, + 1, + -75, + 78, + 1, + 15, + 2, + 0, + /* 939 */ -193, + 73, + 1, + -72, + 75, + 1, + -74, + 77, + 1, + 16, + 2, + 0, + /* 951 */ -193, + 72, + 1, + -71, + 74, + 1, + -73, + 76, + 1, + 17, + 2, + 0, + /* 963 */ -193, + 71, + 1, + -70, + 73, + 1, + -72, + 75, + 1, + 18, + 2, + 0, + /* 975 */ -193, + 70, + 1, + -69, + 72, + 1, + -71, + 74, + 1, + 19, + 2, + 0, + /* 987 */ -193, + 69, + 1, + -68, + 71, + 1, + -70, + 73, + 1, + 20, + 2, + 0, + /* 999 */ -193, + 68, + 1, + -67, + 70, + 1, + -69, + 72, + 1, + 21, + 2, + 0, + /* 1011 */ -193, + 67, + 1, + -66, + 69, + 1, + -68, + 71, + 1, + 22, + 2, + 0, + /* 1023 */ -193, + 66, + 1, + -65, + 68, + 1, + -67, + 70, + 1, + 23, + 2, + 0, + /* 1035 */ -193, + 2, + 2, + 94, + 2, + 0, + /* 1041 */ -193, + 81, + 1, + -80, + 2, + 94, + 2, + 0, + /* 1049 */ -193, + 80, + 1, + -79, + 2, + 94, + 2, + 0, + /* 1057 */ -193, + 79, + 1, + -78, + 81, + 1, + -80, + 94, + 2, + 0, + /* 1067 */ -193, + 78, + 1, + -77, + 80, + 1, + -79, + 94, + 2, + 0, + /* 1077 */ -98, + 2, + 0, + /* 1080 */ -84, + 2, + 0, + /* 1083 */ -464, + 1, + 3, + 1, + 3, + 1, + 3, + 0, + /* 1091 */ -408, + 1, + 3, + 1, + 3, + 0, + /* 1097 */ -218, + 1, + 3, + 0, + /* 1101 */ 7, + 0, + /* 1103 */ 140, + -50, + 13, + 0, + /* 1107 */ 14, + 0, + /* 1109 */ 126, + -35, + 15, + 0, + /* 1113 */ 14, + 69, + 0, + /* 1116 */ -91, + -23, + 1, + 23, + -22, + 1, + 95, + 65, + -64, + 65, + 69, + 0, + /* 1128 */ -91, + -24, + 1, + 24, + -23, + 1, + 95, + 65, + -64, + 65, + 70, + 0, + /* 1140 */ -91, + -25, + 1, + 25, + -24, + 1, + 95, + 65, + -64, + 65, + 71, + 0, + /* 1152 */ -91, + -26, + 1, + 26, + -25, + 1, + 95, + 65, + -64, + 65, + 72, + 0, + /* 1164 */ -91, + -27, + 1, + 27, + -26, + 1, + 95, + 65, + -64, + 65, + 73, + 0, + /* 1176 */ -91, + -28, + 1, + 28, + -27, + 1, + 95, + 65, + -64, + 65, + 74, + 0, + /* 1188 */ -91, + -29, + 1, + 29, + -28, + 1, + 95, + 65, + -64, + 65, + 75, + 0, + /* 1200 */ -91, + -30, + 80, + 1, + -80, + 81, + 1, + -52, + -29, + 1, + 95, + 65, + -64, + 65, + 76, + 0, + /* 1216 */ -91, + -31, + 78, + 1, + -78, + 79, + 1, + -49, + -30, + 80, + 1, + -80, + 81, + 1, + 13, + 65, + -64, + 65, + 77, + 0, + /* 1236 */ -91, + -32, + 76, + 1, + -76, + 77, + 1, + -46, + -31, + 78, + 1, + -78, + 79, + 1, + 15, + 65, + -64, + 65, + 78, + 0, + /* 1256 */ -91, + -33, + 74, + 1, + -74, + 75, + 1, + -43, + -32, + 76, + 1, + -76, + 77, + 1, + 17, + 65, + -64, + 65, + 79, + 0, + /* 1276 */ -91, + -34, + 72, + 1, + -72, + 73, + 1, + -40, + -33, + 74, + 1, + -74, + 75, + 1, + 19, + 65, + -64, + 65, + 80, + 0, + /* 1296 */ -91, + -35, + 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-42, + 68, + 26, + 38, + -120, + 58, + 26, + 37, + -120, + 59, + 26, + -84, + 86, + -85, + 0, + /* 3346 */ 65, + -42, + 70, + 26, + 37, + -120, + 59, + 26, + -84, + 86, + -85, + 0, + /* 3358 */ -78, + 31, + 65, + 2, + 63, + -40, + 120, + -79, + 1, + -41, + 67, + 26, + -81, + 57, + 26, + 38, + -120, + 58, + 26, + 37, + -120, + 85, + -84, + 0, + /* 3382 */ -77, + 31, + 65, + 2, + 63, + -40, + 120, + -79, + 1, + -41, + 67, + 26, + -81, + 57, + 26, + 38, + -120, + 58, + 26, + 37, + -120, + 85, + -84, + 0, + /* 3406 */ 65, + -41, + 69, + 26, + -82, + 58, + 26, + 37, + -120, + 85, + -84, + 0, + /* 3418 */ -79, + 31, + 65, + 2, + 142, + -79, + 1, + -41, + 42, + -41, + 67, + 26, + 39, + -120, + 57, + 26, + 38, + -120, + 58, + 26, + -83, + 85, + -84, + 0, + /* 3442 */ -78, + 31, + 65, + 2, + 142, + -79, + 1, + -41, + 42, + -41, + 67, + 26, + 39, + -120, + 57, + 26, + 38, + -120, + 58, + 26, + -83, + 85, + -84, + 0, + /* 3466 */ 65, + -41, + 69, + 26, + 38, + -120, + 58, + 26, + -83, + 85, + -84, + 0, + /* 3478 */ -76, + 32, + 64, + 2, + 63, + -39, + 120, + -80, + 1, + -40, + 66, + 26, + -80, + 56, + 26, + 39, + -120, + 57, + 26, + 38, + -120, + 84, + -83, + 0, + /* 3502 */ -75, + 32, + 64, + 2, + 63, + -39, + 120, + -80, + 1, + -40, + 66, + 26, + -80, + 56, + 26, + 39, + -120, + 57, + 26, + 38, + -120, + 84, + -83, + 0, + /* 3526 */ 65, + -40, + 68, + 26, + -81, + 57, + 26, + 38, + -120, + 84, + -83, + 0, + /* 3538 */ -77, + 32, + 64, + 2, + 143, + -80, + 1, + -40, + 41, + -40, + 66, + 26, + 40, + -120, + 56, + 26, + 39, + -120, + 57, + 26, + -82, + 84, + -83, + 0, + /* 3562 */ -76, + 32, + 64, + 2, + 143, + -80, + 1, + -40, + 41, + -40, + 66, + 26, + 40, + -120, + 56, + 26, + 39, + -120, + 57, + 26, + -82, + 84, + -83, + 0, + /* 3586 */ 65, + -40, + 68, + 26, + 39, + -120, + 57, + 26, + -82, + 84, + -83, + 0, + /* 3598 */ -74, + 33, + 63, + 2, + 63, + -38, + 120, + -81, + 1, + -39, + 65, + 26, + -79, + 55, + 26, + 40, + -120, + 56, + 26, + 39, + -120, + 83, + -82, + 0, + /* 3622 */ -73, + 33, + 63, + 2, + 63, + -38, + 120, + -81, + 1, + -39, + 65, + 26, + -79, + 55, + 26, + 40, + -120, + 56, + 26, + 39, + -120, + 83, + -82, + 0, + /* 3646 */ 65, + -39, + 67, + 26, + -80, + 56, + 26, + 39, + -120, + 83, + -82, + 0, + /* 3658 */ -75, + 33, + 63, + 2, + 144, + -81, + 1, + -39, + 40, + -39, + 65, + 26, + 41, + -120, + 55, + 26, + 40, + -120, + 56, + 26, + -81, + 83, + -82, + 0, + /* 3682 */ -74, + 33, + 63, + 2, + 144, + -81, + 1, + -39, + 40, + -39, + 65, + 26, + 41, + -120, + 55, + 26, + 40, + -120, + 56, + 26, + -81, + 83, + -82, + 0, + /* 3706 */ 65, + -39, + 67, + 26, + 40, + -120, + 56, + 26, + -81, + 83, + -82, + 0, + /* 3718 */ -239, + 81, + 1, + -81, + 0, + /* 3723 */ -72, + 34, + 62, + 2, + 63, + -37, + 120, + -82, + 1, + -38, + 64, + 2, + 26, + 41, + -120, + 55, + 26, + 40, + -120, + 82, + -81, + 0, + /* 3745 */ -71, + 34, + 62, + 2, + 63, + -37, + 120, + -82, + 1, + -38, + 64, + 2, + 26, + 41, + -120, + 55, + 26, + 40, + -120, + 82, + -81, + 0, + /* 3767 */ 65, + -38, + 66, + 26, + -79, + 55, + 26, + 40, + -120, + 82, + -81, + 0, + /* 3779 */ -73, + 34, + 62, + 2, + 145, + -82, + 1, + -38, + 39, + -38, + 64, + 26, + 42, + -120, + 54, + 26, + 41, + -120, + 55, + 26, + -80, + 82, + -81, + 0, + /* 3803 */ -72, + 34, + 62, + 2, + 145, + -82, + 1, + -38, + 39, + -38, + 64, + 26, + 42, + -120, + 54, + 26, + 41, + -120, + 55, + 26, + -80, + 82, + -81, + 0, + /* 3827 */ 65, + -38, + 66, + 26, + 41, + -120, + 55, + 26, + -80, + 82, + -81, + 0, + /* 3839 */ -98, + 81, + 1, + -80, + 0, + /* 3844 */ -70, + 35, + 61, + 2, + 63, + -36, + 120, + -83, + 1, + -37, + 65, + 2, + 26, + 40, + 1, + -120, + 81, + -80, + 0, + /* 3863 */ -69, + 35, + 61, + 2, + 63, + -36, + 120, + -83, + 1, + -37, + 65, + 2, + 26, + 40, + 1, + -120, + 81, + -80, + 0, + /* 3882 */ 65, + -37, + 65, + 2, + 26, + 41, + -120, + 81, + -80, + 0, + /* 3892 */ -71, + 35, + 61, + 2, + 146, + -83, + 1, + -37, + 38, + -37, + 63, + 2, + 26, + 41, + 1, + -120, + 54, + 26, + -79, + 81, + -80, + 0, + /* 3914 */ -70, + 35, + 61, + 2, + 146, + -83, + 1, + -37, + 38, + -37, + 63, + 2, + 26, + 41, + 1, + -120, + 54, + 26, + -79, + 81, + -80, + 0, + /* 3936 */ 65, + -37, + 65, + 26, + 42, + -120, + 54, + 26, + -79, + 81, + -80, + 0, + /* 3948 */ -98, + 80, + 1, + -79, + 0, + /* 3953 */ 28, + -79, + 0, + /* 3956 */ -69, + 36, + 60, + 2, + 147, + -84, + 1, + -36, + 37, + -36, + 64, + 2, + 26, + 41, + -119, + 80, + -79, + 0, + /* 3974 */ -68, + 36, + 60, + 2, + 147, + -84, + 1, + -36, + 37, + -36, + 64, + 2, + 26, + 41, + -119, + 80, + -79, + 0, + /* 3992 */ 65, + -36, + 64, + 2, + 26, + 41, + -119, + 80, + -79, + 0, + /* 4002 */ 26, + -78, + 80, + -79, + 0, + /* 4007 */ -67, + 37, + 61, + 65, + -35, + 65, + 28, + -78, + 0, + /* 4016 */ -66, + 37, + 61, + 65, + -35, + 65, + 28, + -78, + 0, + /* 4025 */ -163, + 1, + 1, + 230, + -134, + -75, + 0, + /* 4032 */ -163, + 1, + 1, + 231, + -135, + -74, + 0, + /* 4039 */ -163, + 1, + 1, + 232, + -136, + -73, + 0, + /* 4046 */ -163, + 1, + 1, + 233, + -137, + -72, + 0, + /* 4053 */ -163, + 1, + 1, + 234, + -138, + -71, + 0, + /* 4060 */ -163, + 1, + 1, + 235, + -139, + -70, + 0, + /* 4067 */ -163, + 1, + 1, + 236, + -140, + -69, + 0, + /* 4074 */ -97, + -69, + 0, + /* 4077 */ -163, + 81, + 1, + -81, + 1, + 237, + -141, + -68, + 0, + /* 4086 */ -163, + 79, + 1, + -79, + 80, + 1, + -80, + 81, + 1, + 156, + -142, + -67, + 0, + /* 4099 */ -163, + 77, + 1, + -77, + 78, + 1, + -78, + 79, + 1, + 159, + -143, + -66, + 0, + /* 4112 */ -163, + 75, + 1, + -75, + 76, + 1, + -76, + 77, + 1, + 162, + -144, + -65, + 0, + /* 4125 */ -163, + 73, + 1, + -73, + 74, + 1, + -74, + 75, + 1, + 165, + -145, + -64, + 0, + /* 4138 */ -163, + 71, + 1, + -71, + 72, + 1, + -72, + 73, + 1, + 168, + -146, + -63, + 0, + /* 4151 */ -163, + 69, + 1, + -69, + 70, + 1, + -70, + 71, + 1, + 171, + -147, + -62, + 0, + /* 4164 */ -163, + 67, + 1, + -67, + 68, + 1, + -68, + 69, + 1, + 174, + -148, + -61, + 0, + /* 4177 */ -2, + 0, + /* 4179 */ -1, + 0, +}; + +static const uint16_t ARMSubRegIdxLists[] = { + /* 0 */ 1, + 2, + 0, + /* 3 */ 1, + 17, + 18, + 2, + 0, + /* 8 */ 1, + 3, + 0, + /* 11 */ 1, + 17, + 18, + 3, + 0, + /* 16 */ 9, + 10, + 0, + /* 19 */ 17, + 18, + 0, + /* 22 */ 1, + 17, + 18, + 2, + 19, + 20, + 0, + /* 29 */ 1, + 17, + 18, + 3, + 21, + 22, + 0, + /* 36 */ 1, + 2, + 3, + 13, + 33, + 37, + 0, + /* 43 */ 1, + 17, + 18, + 2, + 3, + 13, + 33, + 37, + 0, + /* 52 */ 1, + 17, + 18, + 2, + 19, + 20, + 3, + 13, + 33, + 37, + 0, + /* 63 */ 1, + 17, + 18, + 2, + 19, + 20, + 3, + 21, + 22, + 13, + 33, + 37, + 0, + /* 76 */ 13, + 1, + 2, + 14, + 3, + 4, + 33, + 34, + 35, + 36, + 37, + 0, + /* 88 */ 13, + 1, + 17, + 18, + 2, + 19, + 20, + 14, + 3, + 4, + 33, + 34, + 35, + 36, + 37, + 0, + /* 104 */ 1, + 2, + 3, + 4, + 13, + 14, + 33, + 34, + 35, + 36, + 37, + 0, + /* 116 */ 1, + 17, + 18, + 2, + 3, + 4, + 13, + 14, + 33, + 34, + 35, + 36, + 37, + 0, + /* 130 */ 1, + 17, + 18, + 2, + 19, + 20, + 3, + 21, + 22, + 4, + 13, + 14, + 33, + 34, + 35, + 36, + 37, + 0, + /* 148 */ 1, + 17, + 18, + 2, + 19, + 20, + 3, + 21, + 22, + 4, + 23, + 24, + 13, + 14, + 33, + 34, + 35, + 36, + 37, + 0, + /* 168 */ 13, + 1, + 17, + 18, + 2, + 19, + 20, + 14, + 3, + 21, + 22, + 4, + 23, + 24, + 33, + 34, + 35, + 36, + 37, + 0, + /* 188 */ 1, + 3, + 5, + 33, + 43, + 0, + /* 194 */ 1, + 17, + 18, + 3, + 5, + 33, + 43, + 0, + /* 202 */ 1, + 17, + 18, + 3, + 21, + 22, + 5, + 33, + 43, + 0, + /* 212 */ 1, + 17, + 18, + 3, + 21, + 22, + 5, + 25, + 26, + 33, + 43, + 0, + /* 224 */ 1, + 3, + 5, + 7, + 33, + 38, + 43, + 45, + 51, + 0, + /* 234 */ 1, + 17, + 18, + 3, + 5, + 7, + 33, + 38, + 43, + 45, + 51, + 0, + /* 246 */ 1, + 17, + 18, + 3, + 21, + 22, + 5, + 7, + 33, + 38, + 43, + 45, + 51, + 0, + /* 260 */ 1, + 17, + 18, + 3, + 21, + 22, + 5, + 25, + 26, + 7, + 33, + 38, + 43, + 45, + 51, + 0, + /* 276 */ 1, + 17, + 18, + 3, + 21, + 22, + 5, + 25, + 26, + 7, + 29, + 30, + 33, + 38, + 43, + 45, + 51, + 0, + /* 294 */ 11, + 13, + 1, + 2, + 14, + 3, + 4, + 33, + 34, + 35, + 36, + 37, + 12, + 15, + 5, + 6, + 16, + 7, + 8, + 51, + 52, + 53, + 54, + 55, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 56, + 0, + /* 333 */ 11, + 13, + 1, + 17, + 18, + 2, + 19, + 20, + 14, + 3, + 4, + 33, + 34, + 35, + 36, + 37, + 12, + 15, + 5, + 6, + 16, + 7, + 8, + 51, + 52, + 53, + 54, + 55, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 56, + 0, + /* 376 */ 11, + 13, + 1, + 17, + 18, + 2, + 19, + 20, + 14, + 3, + 21, + 22, + 4, + 23, + 24, + 33, + 34, + 35, + 36, + 37, + 12, + 15, + 5, + 6, + 16, + 7, + 8, + 51, + 52, + 53, + 54, + 55, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 56, + 0, + /* 423 */ 11, + 13, + 1, + 17, + 18, + 2, + 19, + 20, + 14, + 3, + 21, + 22, + 4, + 23, + 24, + 33, + 34, + 35, + 36, + 37, + 12, + 15, + 5, + 25, + 26, + 6, + 27, + 28, + 16, + 7, + 8, + 51, + 52, + 53, + 54, + 55, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 56, + 0, + /* 474 */ 11, + 13, + 1, + 17, + 18, + 2, + 19, + 20, + 14, + 3, + 21, + 22, + 4, + 23, + 24, + 33, + 34, + 35, + 36, + 37, + 12, + 15, + 5, + 25, + 26, + 6, + 27, + 28, + 16, + 7, + 29, + 30, + 8, + 31, + 32, + 51, + 52, + 53, + 54, + 55, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 56, + 0, +}; + +static const MCRegisterDesc ARMRegDesc[] = { + // Descriptors + { 12, 0, 0, 0, 0, 0 }, + { 1268, 16, 16, 2, 66865, 0 }, + { 1319, 16, 16, 2, 66865, 0 }, + { 1273, 16, 16, 2, 66865, 0 }, + { 1286, 16, 16, 2, 66865, 0 }, + { 1294, 16, 16, 2, 66865, 0 }, + { 1215, 16, 16, 2, 66865, 0 }, + { 1301, 16, 16, 2, 66865, 0 }, + { 1255, 16, 16, 2, 17616, 0 }, + { 1308, 16, 16, 2, 17616, 0 }, + { 1202, 16, 16, 2, 66833, 0 }, + { 1221, 16, 16, 2, 66833, 0 }, + { 1240, 16, 16, 2, 66833, 0 }, + { 1261, 16, 16, 2, 66833, 0 }, + { 1199, 16, 16, 2, 66833, 0 }, + { 1227, 16, 16, 2, 66833, 0 }, + { 1252, 16, 1521, 2, 66833, 0 }, + { 1278, 16, 16, 2, 66833, 0 }, + { 1264, 16, 16, 2, 66833, 0 }, + { 1283, 16, 16, 2, 66833, 0 }, + { 119, 350, 4008, 19, 13202, 8 }, + { 251, 357, 2474, 19, 13202, 8 }, + { 366, 364, 3957, 19, 13202, 8 }, + { 482, 378, 3845, 19, 13202, 8 }, + { 608, 392, 3893, 19, 13202, 8 }, + { 726, 406, 3724, 19, 13202, 8 }, + { 840, 420, 3780, 19, 13202, 8 }, + { 946, 434, 3599, 19, 13202, 8 }, + { 1060, 448, 3659, 19, 13202, 8 }, + { 1166, 462, 3479, 19, 13202, 8 }, + { 9, 476, 3539, 19, 13202, 8 }, + { 144, 490, 3359, 19, 13202, 8 }, + { 285, 504, 3419, 19, 13202, 8 }, + { 411, 518, 3239, 19, 13202, 8 }, + { 526, 532, 3299, 19, 13202, 8 }, + { 652, 546, 3144, 19, 13202, 8 }, + { 771, 16, 3203, 2, 17713, 0 }, + { 885, 16, 3073, 2, 17713, 0 }, + { 991, 16, 3108, 2, 17713, 0 }, + { 1105, 16, 3003, 2, 17713, 0 }, + { 59, 16, 3038, 2, 17713, 0 }, + { 195, 16, 2933, 2, 17713, 0 }, + { 339, 16, 2968, 2, 17713, 0 }, + { 459, 16, 2863, 2, 17713, 0 }, + { 578, 16, 2898, 2, 17713, 0 }, + { 700, 16, 2792, 2, 17713, 0 }, + { 807, 16, 2832, 2, 17713, 0 }, + { 917, 16, 2358, 2, 17713, 0 }, + { 1027, 16, 2406, 2, 17713, 0 }, + { 1137, 16, 2379, 2, 17713, 0 }, + { 95, 16, 2424, 2, 17713, 0 }, + { 227, 16, 2784, 2, 17713, 0 }, + { 393, 16, 16, 2, 17713, 0 }, + { 128, 16, 16, 2, 17713, 0 }, + { 260, 16, 16, 2, 17713, 0 }, + { 384, 16, 16, 2, 17713, 0 }, + { 122, 16, 16, 2, 17713, 0 }, + { 125, 353, 1109, 22, 2196, 11 }, + { 257, 374, 775, 22, 2196, 11 }, + { 381, 402, 314, 22, 2196, 11 }, + { 503, 430, 244, 22, 2196, 11 }, + { 632, 458, 234, 22, 2196, 11 }, + { 747, 486, 224, 22, 2196, 11 }, + { 864, 514, 214, 22, 2196, 11 }, + { 967, 542, 204, 22, 2196, 11 }, + { 1084, 804, 194, 0, 12818, 20 }, + { 1187, 807, 184, 0, 12818, 20 }, + { 35, 810, 174, 0, 12818, 20 }, + { 171, 813, 164, 0, 12818, 20 }, + { 315, 816, 154, 0, 12818, 20 }, + { 439, 819, 591, 0, 12818, 20 }, + { 558, 822, 2442, 0, 12818, 20 }, + { 680, 825, 1103, 0, 12818, 20 }, + { 131, 16, 1368, 2, 66833, 0 }, + { 263, 16, 1366, 2, 66833, 0 }, + { 387, 16, 1366, 2, 66833, 0 }, + { 509, 16, 1364, 2, 66833, 0 }, + { 635, 16, 1364, 2, 66833, 0 }, + { 753, 16, 1362, 2, 66833, 0 }, + { 867, 16, 1362, 2, 66833, 0 }, + { 973, 16, 1360, 2, 66833, 0 }, + { 1087, 16, 1360, 2, 66833, 0 }, + { 1193, 16, 1358, 2, 66833, 0 }, + { 39, 16, 1358, 2, 66833, 0 }, + { 179, 16, 1356, 2, 66833, 0 }, + { 319, 16, 1356, 2, 66833, 0 }, + { 134, 16, 4016, 2, 65345, 0 }, + { 272, 16, 4007, 2, 65345, 0 }, + { 390, 16, 2485, 2, 65345, 0 }, + { 512, 16, 2473, 2, 65345, 0 }, + { 638, 16, 3974, 2, 65345, 0 }, + { 756, 16, 3956, 2, 65345, 0 }, + { 870, 16, 3863, 2, 65345, 0 }, + { 976, 16, 3844, 2, 65345, 0 }, + { 1090, 16, 3914, 2, 65345, 0 }, + { 1196, 16, 3892, 2, 65345, 0 }, + { 43, 16, 3745, 2, 65345, 0 }, + { 183, 16, 3723, 2, 65345, 0 }, + { 323, 16, 3803, 2, 65345, 0 }, + { 443, 16, 3779, 2, 65345, 0 }, + { 562, 16, 3622, 2, 65345, 0 }, + { 684, 16, 3598, 2, 65345, 0 }, + { 791, 16, 3682, 2, 65345, 0 }, + { 901, 16, 3658, 2, 65345, 0 }, + { 1011, 16, 3502, 2, 65345, 0 }, + { 1121, 16, 3478, 2, 65345, 0 }, + { 79, 16, 3562, 2, 65345, 0 }, + { 215, 16, 3538, 2, 65345, 0 }, + { 359, 16, 3382, 2, 65345, 0 }, + { 475, 16, 3358, 2, 65345, 0 }, + { 598, 16, 3442, 2, 65345, 0 }, + { 716, 16, 3418, 2, 65345, 0 }, + { 827, 16, 3262, 2, 65345, 0 }, + { 933, 16, 3238, 2, 65345, 0 }, + { 1047, 16, 3322, 2, 65345, 0 }, + { 1153, 16, 3298, 2, 65345, 0 }, + { 115, 16, 3167, 2, 65345, 0 }, + { 247, 16, 3143, 2, 65345, 0 }, + { 363, 367, 4010, 29, 5426, 23 }, + { 479, 381, 2497, 29, 5426, 23 }, + { 605, 395, 3992, 29, 5426, 23 }, + { 723, 409, 3882, 29, 5426, 23 }, + { 837, 423, 3936, 29, 5426, 23 }, + { 943, 437, 3767, 29, 5426, 23 }, + { 1057, 451, 3827, 29, 5426, 23 }, + { 1163, 465, 3646, 29, 5426, 23 }, + { 6, 479, 3706, 29, 5426, 23 }, + { 154, 493, 3526, 29, 5426, 23 }, + { 281, 507, 3586, 29, 5426, 23 }, + { 407, 521, 3406, 29, 5426, 23 }, + { 522, 535, 3466, 29, 5426, 23 }, + { 648, 549, 3286, 29, 5426, 23 }, + { 767, 3948, 3346, 11, 17554, 35 }, + { 881, 3839, 3191, 11, 13474, 35 }, + { 987, 1077, 3226, 8, 17281, 39 }, + { 1101, 1077, 3096, 8, 17281, 39 }, + { 55, 1077, 3131, 8, 17281, 39 }, + { 207, 1077, 3026, 8, 17281, 39 }, + { 335, 1077, 3061, 8, 17281, 39 }, + { 455, 1077, 2956, 8, 17281, 39 }, + { 574, 1077, 2991, 8, 17281, 39 }, + { 696, 1077, 2886, 8, 17281, 39 }, + { 803, 1077, 2921, 8, 17281, 39 }, + { 913, 1077, 2815, 8, 17281, 39 }, + { 1023, 1077, 2853, 8, 17281, 39 }, + { 1133, 1077, 2396, 8, 17281, 39 }, + { 91, 1077, 2435, 8, 17281, 39 }, + { 239, 1077, 2786, 8, 17281, 39 }, + { 254, 1336, 1111, 168, 1044, 57 }, + { 378, 1316, 347, 168, 1044, 57 }, + { 500, 1296, 142, 168, 1044, 57 }, + { 629, 1276, 142, 168, 1044, 57 }, + { 744, 1256, 142, 168, 1044, 57 }, + { 861, 1236, 142, 168, 1044, 57 }, + { 964, 1216, 142, 168, 1044, 57 }, + { 1081, 1200, 142, 88, 1456, 74 }, + { 1184, 1188, 142, 76, 2114, 87 }, + { 32, 1176, 142, 76, 2114, 87 }, + { 167, 1164, 142, 76, 2114, 87 }, + { 311, 1152, 142, 76, 2114, 87 }, + { 435, 1140, 142, 76, 2114, 87 }, + { 554, 1128, 344, 76, 2114, 87 }, + { 676, 1116, 1105, 76, 2114, 87 }, + { 494, 2151, 16, 474, 4, 149 }, + { 623, 2096, 16, 474, 4, 149 }, + { 738, 2041, 16, 474, 4, 149 }, + { 855, 1986, 16, 474, 4, 149 }, + { 958, 1931, 16, 474, 4, 149 }, + { 1075, 1880, 16, 423, 272, 166 }, + { 1178, 1833, 16, 376, 512, 181 }, + { 26, 1790, 16, 333, 720, 194 }, + { 161, 1751, 16, 294, 1186, 205 }, + { 304, 1712, 16, 294, 1186, 205 }, + { 427, 1673, 16, 294, 1186, 205 }, + { 546, 1634, 16, 294, 1186, 205 }, + { 668, 1595, 16, 294, 1186, 205 }, + { 266, 783, 16, 16, 8946, 5 }, + { 506, 786, 16, 16, 8946, 5 }, + { 750, 789, 16, 16, 8946, 5 }, + { 970, 792, 16, 16, 8946, 5 }, + { 1190, 795, 16, 16, 8946, 5 }, + { 175, 798, 16, 16, 8946, 5 }, + { 1248, 4074, 16, 16, 17808, 2 }, + { 369, 1508, 1110, 63, 1570, 28 }, + { 485, 4164, 2506, 63, 1570, 28 }, + { 614, 1495, 778, 63, 1570, 28 }, + { 729, 4151, 770, 63, 1570, 28 }, + { 846, 1482, 317, 63, 1570, 28 }, + { 949, 4138, 660, 63, 1570, 28 }, + { 1066, 1469, 308, 63, 1570, 28 }, + { 1169, 4125, 654, 63, 1570, 28 }, + { 16, 1456, 302, 63, 1570, 28 }, + { 137, 4112, 648, 63, 1570, 28 }, + { 292, 1443, 296, 63, 1570, 28 }, + { 415, 4099, 642, 63, 1570, 28 }, + { 534, 1430, 290, 63, 1570, 28 }, + { 656, 4086, 636, 63, 1570, 28 }, + { 779, 1419, 284, 52, 1680, 42 }, + { 889, 4077, 630, 43, 1872, 48 }, + { 999, 1412, 278, 36, 2401, 53 }, + { 1109, 4067, 624, 36, 2401, 53 }, + { 67, 1405, 272, 36, 2401, 53 }, + { 187, 4060, 618, 36, 2401, 53 }, + { 347, 1398, 266, 36, 2401, 53 }, + { 463, 4053, 612, 36, 2401, 53 }, + { 586, 1391, 260, 36, 2401, 53 }, + { 704, 4046, 606, 36, 2401, 53 }, + { 815, 1384, 254, 36, 2401, 53 }, + { 921, 4039, 600, 36, 2401, 53 }, + { 1035, 1377, 765, 36, 2401, 53 }, + { 1141, 4032, 2450, 36, 2401, 53 }, + { 103, 1370, 2469, 36, 2401, 53 }, + { 219, 4025, 1104, 36, 2401, 53 }, + { 602, 1023, 4013, 212, 5314, 92 }, + { 720, 1011, 3953, 212, 5314, 92 }, + { 834, 999, 4002, 212, 5314, 92 }, + { 940, 987, 3909, 212, 5314, 92 }, + { 1054, 975, 3909, 212, 5314, 92 }, + { 1160, 963, 3798, 212, 5314, 92 }, + { 3, 951, 3798, 212, 5314, 92 }, + { 151, 939, 3677, 212, 5314, 92 }, + { 278, 927, 3677, 212, 5314, 92 }, + { 404, 915, 3557, 212, 5314, 92 }, + { 518, 903, 3557, 212, 5314, 92 }, + { 644, 891, 3437, 212, 5314, 92 }, + { 763, 1067, 3437, 202, 17458, 99 }, + { 877, 1057, 3317, 202, 13378, 99 }, + { 983, 1049, 3317, 194, 14178, 105 }, + { 1097, 1041, 3221, 194, 13650, 105 }, + { 51, 1035, 3221, 188, 14001, 110 }, + { 203, 1035, 3126, 188, 14001, 110 }, + { 331, 1035, 3126, 188, 14001, 110 }, + { 451, 1035, 3056, 188, 14001, 110 }, + { 570, 1035, 3056, 188, 14001, 110 }, + { 692, 1035, 2986, 188, 14001, 110 }, + { 799, 1035, 2986, 188, 14001, 110 }, + { 909, 1035, 2916, 188, 14001, 110 }, + { 1019, 1035, 2916, 188, 14001, 110 }, + { 1129, 1035, 2827, 188, 14001, 110 }, + { 87, 1035, 2850, 188, 14001, 110 }, + { 235, 1035, 2789, 188, 14001, 110 }, + { 831, 2672, 4014, 276, 5170, 114 }, + { 937, 2654, 3951, 276, 5170, 114 }, + { 1051, 2636, 3951, 276, 5170, 114 }, + { 1157, 2618, 3842, 276, 5170, 114 }, + { 0, 2600, 3842, 276, 5170, 114 }, + { 148, 2582, 3721, 276, 5170, 114 }, + { 275, 2564, 3721, 276, 5170, 114 }, + { 401, 2546, 3620, 276, 5170, 114 }, + { 515, 2528, 3620, 276, 5170, 114 }, + { 641, 2510, 3500, 276, 5170, 114 }, + { 759, 2768, 3500, 260, 17330, 123 }, + { 873, 2752, 3380, 260, 13250, 123 }, + { 979, 2738, 3380, 246, 14066, 131 }, + { 1093, 2724, 3260, 246, 13538, 131 }, + { 47, 2712, 3260, 234, 13906, 138 }, + { 199, 2700, 3165, 234, 13730, 138 }, + { 327, 2690, 3165, 224, 13825, 144 }, + { 447, 2690, 3094, 224, 13825, 144 }, + { 566, 2690, 3094, 224, 13825, 144 }, + { 688, 2690, 3024, 224, 13825, 144 }, + { 795, 2690, 3024, 224, 13825, 144 }, + { 905, 2690, 2954, 224, 13825, 144 }, + { 1015, 2690, 2954, 224, 13825, 144 }, + { 1125, 2690, 2851, 224, 13825, 144 }, + { 83, 2690, 2851, 224, 13825, 144 }, + { 231, 2690, 2790, 224, 13825, 144 }, + { 372, 360, 2504, 22, 1956, 11 }, + { 617, 388, 583, 22, 1956, 11 }, + { 849, 416, 756, 22, 1956, 11 }, + { 1069, 444, 747, 22, 1956, 11 }, + { 19, 472, 738, 22, 1956, 11 }, + { 296, 500, 729, 22, 1956, 11 }, + { 538, 528, 720, 22, 1956, 11 }, + { 783, 3718, 711, 3, 2336, 16 }, + { 1003, 562, 702, 0, 8898, 20 }, + { 71, 565, 693, 0, 8898, 20 }, + { 351, 568, 684, 0, 8898, 20 }, + { 590, 571, 675, 0, 8898, 20 }, + { 819, 574, 666, 0, 8898, 20 }, + { 1039, 577, 2455, 0, 8898, 20 }, + { 107, 580, 2463, 0, 8898, 20 }, + { 611, 2338, 2483, 148, 900, 57 }, + { 843, 2318, 588, 148, 900, 57 }, + { 1063, 2298, 588, 148, 900, 57 }, + { 13, 2278, 588, 148, 900, 57 }, + { 289, 2258, 588, 148, 900, 57 }, + { 530, 2238, 588, 148, 900, 57 }, + { 775, 2220, 588, 130, 1328, 66 }, + { 995, 2206, 588, 116, 1776, 81 }, + { 63, 1583, 588, 104, 2034, 87 }, + { 343, 1571, 588, 104, 2034, 87 }, + { 582, 1559, 588, 104, 2034, 87 }, + { 811, 1547, 588, 104, 2034, 87 }, + { 1031, 1535, 588, 104, 2034, 87 }, + { 99, 1523, 2377, 104, 2034, 87 }, +}; + +// HPR Register Class... +static const MCPhysReg HPR[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, + ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, + ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, + ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, +}; + +// HPR Bit set. +static const uint8_t HPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, +}; + +// FPWithVPR Register Class... +static const MCPhysReg FPWithVPR[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, + ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, + ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, + ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, + ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, + ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, + ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31, + ARM_VPR, +}; + +// FPWithVPR Bit set. +static const uint8_t FPWithVPRBits[] = { + 0x00, 0x00, 0xf4, 0xff, 0xff, 0xff, 0x0f, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, +}; + +// SPR Register Class... +static const MCPhysReg SPR[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, + ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, + ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, + ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, +}; + +// SPR Bit set. +static const uint8_t SPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, +}; + +// FPWithVPR_with_ssub_0 Register Class... +static const MCPhysReg FPWithVPR_with_ssub_0[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, + ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, +}; + +// FPWithVPR_with_ssub_0 Bit set. +static const uint8_t FPWithVPR_with_ssub_0Bits[] = { + 0x00, 0x00, 0xf0, 0xff, 0x0f, +}; + +// GPR Register Class... +static const MCPhysReg GPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, +}; + +// GPR Bit set. +static const uint8_t GPRBits[] = { + 0x00, 0x60, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, +}; + +// GPRwithAPSR Register Class... +static const MCPhysReg GPRwithAPSR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, + ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, + ARM_R12, ARM_SP, ARM_LR, ARM_APSR_NZCV, +}; + +// GPRwithAPSR Bit set. +static const uint8_t GPRwithAPSRBits[] = { + 0x04, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, +}; + +// GPRwithZR Register Class... +static const MCPhysReg GPRwithZR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_ZR, +}; + +// GPRwithZR Bit set. +static const uint8_t GPRwithZRBits[] = { + 0x00, 0x20, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, +}; + +// SPR_8 Register Class... +static const MCPhysReg SPR_8[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, + ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, +}; + +// SPR_8 Bit set. +static const uint8_t SPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, +}; + +// GPRnopc Register Class... +static const MCPhysReg GPRnopc[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, +}; + +// GPRnopc Bit set. +static const uint8_t GPRnopcBits[] = { + 0x00, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, +}; + +// GPRnosp Register Class... +static const MCPhysReg GPRnosp[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_PC, +}; + +// GPRnosp Bit set. +static const uint8_t GPRnospBits[] = { + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, +}; + +// GPRwithAPSR_NZCVnosp Register Class... +static const MCPhysReg GPRwithAPSR_NZCVnosp[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, + ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, + ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_APSR_NZCV, +}; + +// GPRwithAPSR_NZCVnosp Bit set. +static const uint8_t GPRwithAPSR_NZCVnospBits[] = { + 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, +}; + +// GPRwithAPSRnosp Register Class... +static const MCPhysReg GPRwithAPSRnosp[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_APSR, +}; + +// GPRwithAPSRnosp Bit set. +static const uint8_t GPRwithAPSRnospBits[] = { + 0x02, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, +}; + +// GPRwithZRnosp Register Class... +static const MCPhysReg GPRwithZRnosp[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_ZR, +}; + +// GPRwithZRnosp Bit set. +static const uint8_t GPRwithZRnospBits[] = { + 0x00, 0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, +}; + +// GPRnoip Register Class... +static const MCPhysReg GPRnoip[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, + ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, ARM_PC, +}; + +// GPRnoip Bit set. +static const uint8_t GPRnoipBits[] = { + 0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f, +}; + +// rGPR Register Class... +static const MCPhysReg rGPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, + ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, +}; + +// rGPR Bit set. +static const uint8_t rGPRBits[] = { + 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, +}; + +// GPRnoip_and_GPRnopc Register Class... +static const MCPhysReg GPRnoip_and_GPRnopc[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, + ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, +}; + +// GPRnoip_and_GPRnopc Bit set. +static const uint8_t GPRnoip_and_GPRnopcBits[] = { + 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f, +}; + +// GPRnoip_and_GPRnosp Register Class... +static const MCPhysReg GPRnoip_and_GPRnosp[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, + ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_PC, +}; + +// GPRnoip_and_GPRnosp Bit set. +static const uint8_t GPRnoip_and_GPRnospBits[] = { + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f, +}; + +// GPRnoip_and_GPRwithAPSR_NZCVnosp Register Class... +static const MCPhysReg GPRnoip_and_GPRwithAPSR_NZCVnosp[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, + ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, +}; + +// GPRnoip_and_GPRwithAPSR_NZCVnosp Bit set. +static const uint8_t GPRnoip_and_GPRwithAPSR_NZCVnospBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f, +}; + +// tGPRwithpc Register Class... +static const MCPhysReg tGPRwithpc[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_PC, +}; + +// tGPRwithpc Bit set. +static const uint8_t tGPRwithpcBits[] = { + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, +}; + +// FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Register Class... +static const MCPhysReg FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, +}; + +// FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Bit set. +static const uint8_t FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits[] = { + 0x00, + 0x00, + 0xf0, + 0x0f, +}; + +// hGPR Register Class... +static const MCPhysReg hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, +}; + +// hGPR Bit set. +static const uint8_t hGPRBits[] = { + 0x00, 0x60, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, +}; + +// tGPR Register Class... +static const MCPhysReg tGPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, +}; + +// tGPR Bit set. +static const uint8_t tGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, +}; + +// tGPREven Register Class... +static const MCPhysReg tGPREven[] = { + ARM_R0, ARM_R2, ARM_R4, ARM_R6, ARM_R8, ARM_R10, ARM_R12, ARM_LR, +}; + +// tGPREven Bit set. +static const uint8_t tGPREvenBits[] = { + 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, +}; + +// GPRnopc_and_hGPR Register Class... +static const MCPhysReg GPRnopc_and_hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, +}; + +// GPRnopc_and_hGPR Bit set. +static const uint8_t GPRnopc_and_hGPRBits[] = { + 0x00, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, +}; + +// GPRnosp_and_hGPR Register Class... +static const MCPhysReg GPRnosp_and_hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_PC, +}; + +// GPRnosp_and_hGPR Bit set. +static const uint8_t GPRnosp_and_hGPRBits[] = { + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, +}; + +// GPRnoip_and_hGPR Register Class... +static const MCPhysReg GPRnoip_and_hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, ARM_PC, +}; + +// GPRnoip_and_hGPR Bit set. +static const uint8_t GPRnoip_and_hGPRBits[] = { + 0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, +}; + +// GPRnoip_and_tGPREven Register Class... +static const MCPhysReg GPRnoip_and_tGPREven[] = { + ARM_R0, ARM_R2, ARM_R4, ARM_R6, ARM_R8, ARM_R10, +}; + +// GPRnoip_and_tGPREven Bit set. +static const uint8_t GPRnoip_and_tGPREvenBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x0a, +}; + +// GPRnosp_and_GPRnopc_and_hGPR Register Class... +static const MCPhysReg GPRnosp_and_GPRnopc_and_hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, +}; + +// GPRnosp_and_GPRnopc_and_hGPR Bit set. +static const uint8_t GPRnosp_and_GPRnopc_and_hGPRBits[] = { + 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, +}; + +// tGPROdd Register Class... +static const MCPhysReg tGPROdd[] = { + ARM_R1, ARM_R3, ARM_R5, ARM_R7, ARM_R9, ARM_R11, +}; + +// tGPROdd Bit set. +static const uint8_t tGPROddBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x15, +}; + +// GPRnopc_and_GPRnoip_and_hGPR Register Class... +static const MCPhysReg GPRnopc_and_GPRnoip_and_hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, +}; + +// GPRnopc_and_GPRnoip_and_hGPR Bit set. +static const uint8_t GPRnopc_and_GPRnoip_and_hGPRBits[] = { + 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, +}; + +// GPRnosp_and_GPRnoip_and_hGPR Register Class... +static const MCPhysReg GPRnosp_and_GPRnoip_and_hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_PC, +}; + +// GPRnosp_and_GPRnoip_and_hGPR Bit set. +static const uint8_t GPRnosp_and_GPRnoip_and_hGPRBits[] = { + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, +}; + +// tcGPR Register Class... +static const MCPhysReg tcGPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R12, +}; + +// tcGPR Bit set. +static const uint8_t tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x20, +}; + +// GPRnoip_and_tcGPR Register Class... +static const MCPhysReg GPRnoip_and_tcGPR[] = { + ARM_R0, + ARM_R1, + ARM_R2, + ARM_R3, +}; + +// GPRnoip_and_tcGPR Bit set. +static const uint8_t GPRnoip_and_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, +}; + +// GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR Register Class... +static const MCPhysReg GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR[] = { + ARM_R8, + ARM_R9, + ARM_R10, + ARM_R11, +}; + +// GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR Bit set. +static const uint8_t GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, +}; + +// hGPR_and_tGPREven Register Class... +static const MCPhysReg hGPR_and_tGPREven[] = { + ARM_R8, + ARM_R10, + ARM_R12, + ARM_LR, +}; + +// hGPR_and_tGPREven Bit set. +static const uint8_t hGPR_and_tGPREvenBits[] = { + 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, +}; + +// tGPR_and_tGPREven Register Class... +static const MCPhysReg tGPR_and_tGPREven[] = { + ARM_R0, + ARM_R2, + ARM_R4, + ARM_R6, +}; + +// tGPR_and_tGPREven Bit set. +static const uint8_t tGPR_and_tGPREvenBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, +}; + +// tGPR_and_tGPROdd Register Class... +static const MCPhysReg tGPR_and_tGPROdd[] = { + ARM_R1, + ARM_R3, + ARM_R5, + ARM_R7, +}; + +// tGPR_and_tGPROdd Bit set. +static const uint8_t tGPR_and_tGPROddBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x01, +}; + +// tGPREven_and_tcGPR Register Class... +static const MCPhysReg tGPREven_and_tcGPR[] = { + ARM_R0, + ARM_R2, + ARM_R12, +}; + +// tGPREven_and_tcGPR Bit set. +static const uint8_t tGPREven_and_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x20, +}; + +// hGPR_and_GPRnoip_and_tGPREven Register Class... +static const MCPhysReg hGPR_and_GPRnoip_and_tGPREven[] = { + ARM_R8, + ARM_R10, +}; + +// hGPR_and_GPRnoip_and_tGPREven Bit set. +static const uint8_t hGPR_and_GPRnoip_and_tGPREvenBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, +}; + +// hGPR_and_tGPROdd Register Class... +static const MCPhysReg hGPR_and_tGPROdd[] = { + ARM_R9, + ARM_R11, +}; + +// hGPR_and_tGPROdd Bit set. +static const uint8_t hGPR_and_tGPROddBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, +}; + +// tGPREven_and_GPRnoip_and_tcGPR Register Class... +static const MCPhysReg tGPREven_and_GPRnoip_and_tcGPR[] = { + ARM_R0, + ARM_R2, +}; + +// tGPREven_and_GPRnoip_and_tcGPR Bit set. +static const uint8_t tGPREven_and_GPRnoip_and_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, +}; + +// tGPROdd_and_tcGPR Register Class... +static const MCPhysReg tGPROdd_and_tcGPR[] = { + ARM_R1, + ARM_R3, +}; + +// tGPROdd_and_tcGPR Bit set. +static const uint8_t tGPROdd_and_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, +}; + +// CCR Register Class... +static const MCPhysReg CCR[] = { + ARM_CPSR, +}; + +// CCR Bit set. +static const uint8_t CCRBits[] = { + 0x08, +}; + +// FPCXTRegs Register Class... +static const MCPhysReg FPCXTRegs[] = { + ARM_FPCXTNS, +}; + +// FPCXTRegs Bit set. +static const uint8_t FPCXTRegsBits[] = { + 0x10, +}; + +// GPRlr Register Class... +static const MCPhysReg GPRlr[] = { + ARM_LR, +}; + +// GPRlr Bit set. +static const uint8_t GPRlrBits[] = { + 0x00, + 0x20, +}; + +// GPRsp Register Class... +static const MCPhysReg GPRsp[] = { + ARM_SP, +}; + +// GPRsp Bit set. +static const uint8_t GPRspBits[] = { + 0x00, + 0x00, + 0x01, +}; + +// VCCR Register Class... +static const MCPhysReg VCCR[] = { + ARM_VPR, +}; + +// VCCR Bit set. +static const uint8_t VCCRBits[] = { + 0x00, + 0x00, + 0x04, +}; + +// cl_FPSCR_NZCV Register Class... +static const MCPhysReg cl_FPSCR_NZCV[] = { + ARM_FPSCR_NZCV, +}; + +// cl_FPSCR_NZCV Bit set. +static const uint8_t cl_FPSCR_NZCVBits[] = { + 0x00, + 0x02, +}; + +// hGPR_and_tGPRwithpc Register Class... +static const MCPhysReg hGPR_and_tGPRwithpc[] = { + ARM_PC, +}; + +// hGPR_and_tGPRwithpc Bit set. +static const uint8_t hGPR_and_tGPRwithpcBits[] = { + 0x00, + 0x40, +}; + +// hGPR_and_tcGPR Register Class... +static const MCPhysReg hGPR_and_tcGPR[] = { + ARM_R12, +}; + +// hGPR_and_tcGPR Bit set. +static const uint8_t hGPR_and_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, +}; + +// DPR Register Class... +static const MCPhysReg DPR[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, + ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, + ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, + ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31, +}; + +// DPR Bit set. +static const uint8_t DPRBits[] = { + 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, +}; + +// DPR_VFP2 Register Class... +static const MCPhysReg DPR_VFP2[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, + ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, +}; + +// DPR_VFP2 Bit set. +static const uint8_t DPR_VFP2Bits[] = { + 0x00, 0x00, 0xf0, 0xff, 0x0f, +}; + +// DPR_8 Register Class... +static const MCPhysReg DPR_8[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, +}; + +// DPR_8 Bit set. +static const uint8_t DPR_8Bits[] = { + 0x00, + 0x00, + 0xf0, + 0x0f, +}; + +// GPRPair Register Class... +static const MCPhysReg GPRPair[] = { + ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, + ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, +}; + +// GPRPair Bit set. +static const uint8_t GPRPairBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, +}; + +// GPRPairnosp Register Class... +static const MCPhysReg GPRPairnosp[] = { + ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, +}; + +// GPRPairnosp Bit set. +static const uint8_t GPRPairnospBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, +}; + +// GPRPair_with_gsub_0_in_tGPR Register Class... +static const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = { + ARM_R0_R1, + ARM_R2_R3, + ARM_R4_R5, + ARM_R6_R7, +}; + +// GPRPair_with_gsub_0_in_tGPR Bit set. +static const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, +}; + +// GPRPair_with_gsub_0_in_hGPR Register Class... +static const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = { + ARM_R8_R9, + ARM_R10_R11, + ARM_R12_SP, +}; + +// GPRPair_with_gsub_0_in_hGPR Bit set. +static const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, +}; + +// GPRPair_with_gsub_0_in_tcGPR Register Class... +static const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = { + ARM_R0_R1, + ARM_R2_R3, + ARM_R12_SP, +}; + +// GPRPair_with_gsub_0_in_tcGPR Bit set. +static const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, +}; + +// GPRPair_with_gsub_1_in_tcGPR Register Class... +static const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = { + ARM_R0_R1, + ARM_R2_R3, +}; + +// GPRPair_with_gsub_1_in_tcGPR Bit set. +static const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, +}; + +// GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Register Class... +static const MCPhysReg GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR[] = { + ARM_R8_R9, + ARM_R10_R11, +}; + +// GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Bit set. +static const uint8_t GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, +}; + +// GPRPair_with_gsub_1_in_GPRsp Register Class... +static const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = { + ARM_R12_SP, +}; + +// GPRPair_with_gsub_1_in_GPRsp Bit set. +static const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, +}; + +// DPairSpc Register Class... +static const MCPhysReg DPairSpc[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, + ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, + ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, + ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, + ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, + ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31, +}; + +// DPairSpc Bit set. +static const uint8_t DPairSpcBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x0f, +}; + +// DPairSpc_with_ssub_0 Register Class... +static const MCPhysReg DPairSpc_with_ssub_0[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, + ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, + ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, + ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, +}; + +// DPairSpc_with_ssub_0 Bit set. +static const uint8_t DPairSpc_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, +}; + +// DPairSpc_with_ssub_4 Register Class... +static const MCPhysReg DPairSpc_with_ssub_4[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, + ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, + ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, +}; + +// DPairSpc_with_ssub_4 Bit set. +static const uint8_t DPairSpc_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, +}; + +// DPairSpc_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, + ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, +}; + +// DPairSpc_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, +}; + +// DPairSpc_with_dsub_2_in_DPR_8 Register Class... +static const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, +}; + +// DPairSpc_with_dsub_2_in_DPR_8 Bit set. +static const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, +}; + +// DPair Register Class... +static const MCPhysReg DPair[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, + ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, + ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, + ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, + ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, + ARM_Q15, +}; + +// DPair Bit set. +static const uint8_t DPairBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, +}; + +// DPair_with_ssub_0 Register Class... +static const MCPhysReg DPair_with_ssub_0[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, + ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, + ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, +}; + +// DPair_with_ssub_0 Bit set. +static const uint8_t DPair_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, +}; + +// QPR Register Class... +static const MCPhysReg QPR[] = { + ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, + ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, +}; + +// QPR Bit set. +static const uint8_t QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, +}; + +// DPair_with_ssub_2 Register Class... +static const MCPhysReg DPair_with_ssub_2[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, + ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, + ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, +}; + +// DPair_with_ssub_2 Bit set. +static const uint8_t DPair_with_ssub_2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, +}; + +// DPair_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, + ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, +}; + +// DPair_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, +}; + +// MQPR Register Class... +static const MCPhysReg MQPR[] = { + ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, +}; + +// MQPR Bit set. +static const uint8_t MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, +}; + +// QPR_VFP2 Register Class... +static const MCPhysReg QPR_VFP2[] = { + ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, +}; + +// QPR_VFP2 Bit set. +static const uint8_t QPR_VFP2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, +}; + +// DPair_with_dsub_1_in_DPR_8 Register Class... +static const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, +}; + +// DPair_with_dsub_1_in_DPR_8 Bit set. +static const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, +}; + +// QPR_8 Register Class... +static const MCPhysReg QPR_8[] = { + ARM_Q0, + ARM_Q1, + ARM_Q2, + ARM_Q3, +}; + +// QPR_8 Bit set. +static const uint8_t QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, +}; + +// DTriple Register Class... +static const MCPhysReg DTriple[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, + ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, + ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, + ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, + ARM_D16_D17_D18, ARM_D17_D18_D19, ARM_D18_D19_D20, ARM_D19_D20_D21, + ARM_D20_D21_D22, ARM_D21_D22_D23, ARM_D22_D23_D24, ARM_D23_D24_D25, + ARM_D24_D25_D26, ARM_D25_D26_D27, ARM_D26_D27_D28, ARM_D27_D28_D29, + ARM_D28_D29_D30, ARM_D29_D30_D31, +}; + +// DTriple Bit set. +static const uint8_t DTripleBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, +}; + +// DTripleSpc Register Class... +static const MCPhysReg DTripleSpc[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, + ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, + ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, + ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, +}; + +// DTripleSpc Bit set. +static const uint8_t DTripleSpcBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x01, +}; + +// DTripleSpc_with_ssub_0 Register Class... +static const MCPhysReg DTripleSpc_with_ssub_0[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, +}; + +// DTripleSpc_with_ssub_0 Bit set. +static const uint8_t DTripleSpc_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, +}; + +// DTriple_with_ssub_0 Register Class... +static const MCPhysReg DTriple_with_ssub_0[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, + ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, + ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, + ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, +}; + +// DTriple_with_ssub_0 Bit set. +static const uint8_t DTriple_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, +}; + +// DTriple_with_qsub_0_in_QPR Register Class... +static const MCPhysReg DTriple_with_qsub_0_in_QPR[] = { + ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, + ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, + ARM_D16_D17_D18, ARM_D18_D19_D20, ARM_D20_D21_D22, ARM_D22_D23_D24, + ARM_D24_D25_D26, ARM_D26_D27_D28, ARM_D28_D29_D30, +}; + +// DTriple_with_qsub_0_in_QPR Bit set. +static const uint8_t DTriple_with_qsub_0_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0x0a, +}; + +// DTriple_with_ssub_2 Register Class... +static const MCPhysReg DTriple_with_ssub_2[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, + ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, + ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, + ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, +}; + +// DTriple_with_ssub_2 Bit set. +static const uint8_t DTriple_with_ssub_2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f, +}; + +// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... +static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, + ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, + ARM_D17_D18_D19, ARM_D19_D20_D21, ARM_D21_D22_D23, ARM_D23_D24_D25, + ARM_D25_D26_D27, ARM_D27_D28_D29, ARM_D29_D30_D31, +}; + +// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. +static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, +}; + +// DTripleSpc_with_ssub_4 Register Class... +static const MCPhysReg DTripleSpc_with_ssub_4[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + ARM_D12_D14_D16, ARM_D13_D15_D17, +}; + +// DTripleSpc_with_ssub_4 Bit set. +static const uint8_t DTripleSpc_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, +}; + +// DTriple_with_ssub_4 Register Class... +static const MCPhysReg DTriple_with_ssub_4[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, + ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, + ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, + ARM_D12_D13_D14, ARM_D13_D14_D15, +}; + +// DTriple_with_ssub_4 Bit set. +static const uint8_t DTriple_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, +}; + +// DTripleSpc_with_ssub_8 Register Class... +static const MCPhysReg DTripleSpc_with_ssub_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, +}; + +// DTripleSpc_with_ssub_8 Bit set. +static const uint8_t DTripleSpc_with_ssub_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x01, +}; + +// DTripleSpc_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, +}; + +// DTripleSpc_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, +}; + +// DTriple_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, + ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, +}; + +// DTriple_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, +}; + +// DTriple_with_qsub_0_in_MQPR Register Class... +static const MCPhysReg DTriple_with_qsub_0_in_MQPR[] = { + ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, + ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, +}; + +// DTriple_with_qsub_0_in_MQPR Bit set. +static const uint8_t DTriple_with_qsub_0_in_MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a, +}; + +// DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... +static const MCPhysReg + DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR + [] = { + ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, + ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, + ARM_D13_D14_D15, ARM_D15_D16_D17, + }; + +// DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. +static const uint8_t + DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, + }; + +// DTriple_with_dsub_1_in_DPR_8 Register Class... +static const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, + ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, +}; + +// DTriple_with_dsub_1_in_DPR_8 Bit set. +static const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, +}; + +// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... +static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { + ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, + ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, +}; + +// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. +static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, +}; + +// DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Register Class... +static const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR[] = { + ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, + ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, +}; + +// DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Bit set. +static const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x0a, +}; + +// DTripleSpc_with_dsub_2_in_DPR_8 Register Class... +static const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, + ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, +}; + +// DTripleSpc_with_dsub_2_in_DPR_8 Bit set. +static const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, +}; + +// DTriple_with_dsub_2_in_DPR_8 Register Class... +static const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, + ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, +}; + +// DTriple_with_dsub_2_in_DPR_8 Bit set. +static const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, +}; + +// DTripleSpc_with_dsub_4_in_DPR_8 Register Class... +static const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = { + ARM_D0_D2_D4, + ARM_D1_D3_D5, + ARM_D2_D4_D6, + ARM_D3_D5_D7, +}; + +// DTripleSpc_with_dsub_4_in_DPR_8 Bit set. +static const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, +}; + +// DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... +static const MCPhysReg + DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR + [] = { + ARM_D1_D2_D3, + ARM_D3_D4_D5, + ARM_D5_D6_D7, + ARM_D7_D8_D9, + }; + +// DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. +static const uint8_t + DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, + }; + +// DTriple_with_qsub_0_in_QPR_8 Register Class... +static const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = { + ARM_D0_D1_D2, + ARM_D2_D3_D4, + ARM_D4_D5_D6, + ARM_D6_D7_D8, +}; + +// DTriple_with_qsub_0_in_QPR_8 Bit set. +static const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a, +}; + +// DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR Register Class... +static const MCPhysReg + DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR[] = { + ARM_D0_D1_D2, + ARM_D2_D3_D4, + ARM_D4_D5_D6, + }; + +// DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR Bit set. +static const uint8_t + DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0a, + }; + +// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class... +static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = { + ARM_D1_D2_D3, + ARM_D3_D4_D5, + ARM_D5_D6_D7, +}; + +// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set. +static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, +}; + +// DQuadSpc Register Class... +static const MCPhysReg DQuadSpc[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, + ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, + ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, + ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, +}; + +// DQuadSpc Bit set. +static const uint8_t DQuadSpcBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x01, +}; + +// DQuadSpc_with_ssub_0 Register Class... +static const MCPhysReg DQuadSpc_with_ssub_0[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, +}; + +// DQuadSpc_with_ssub_0 Bit set. +static const uint8_t DQuadSpc_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, +}; + +// DQuadSpc_with_ssub_4 Register Class... +static const MCPhysReg DQuadSpc_with_ssub_4[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + ARM_D12_D14_D16, ARM_D13_D15_D17, +}; + +// DQuadSpc_with_ssub_4 Bit set. +static const uint8_t DQuadSpc_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, +}; + +// DQuadSpc_with_ssub_8 Register Class... +static const MCPhysReg DQuadSpc_with_ssub_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, +}; + +// DQuadSpc_with_ssub_8 Bit set. +static const uint8_t DQuadSpc_with_ssub_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x01, +}; + +// DQuadSpc_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, +}; + +// DQuadSpc_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, +}; + +// DQuadSpc_with_dsub_2_in_DPR_8 Register Class... +static const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, + ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, +}; + +// DQuadSpc_with_dsub_2_in_DPR_8 Bit set. +static const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, +}; + +// DQuadSpc_with_dsub_4_in_DPR_8 Register Class... +static const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = { + ARM_D0_D2_D4, + ARM_D1_D3_D5, + ARM_D2_D4_D6, + ARM_D3_D5_D7, +}; + +// DQuadSpc_with_dsub_4_in_DPR_8 Bit set. +static const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, +}; + +// DQuad Register Class... +static const MCPhysReg DQuad[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, + ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, + ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, + ARM_Q8_Q9, ARM_D17_D18_D19_D20, ARM_Q9_Q10, ARM_D19_D20_D21_D22, + ARM_Q10_Q11, ARM_D21_D22_D23_D24, ARM_Q11_Q12, ARM_D23_D24_D25_D26, + ARM_Q12_Q13, ARM_D25_D26_D27_D28, ARM_Q13_Q14, ARM_D27_D28_D29_D30, + ARM_Q14_Q15, +}; + +// DQuad Bit set. +static const uint8_t DQuadBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, + 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, +}; + +// DQuad_with_ssub_0 Register Class... +static const MCPhysReg DQuad_with_ssub_0[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, + ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, + ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, +}; + +// DQuad_with_ssub_0 Bit set. +static const uint8_t DQuad_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, +}; + +// DQuad_with_ssub_2 Register Class... +static const MCPhysReg DQuad_with_ssub_2[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, + ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, + ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, +}; + +// DQuad_with_ssub_2 Bit set. +static const uint8_t DQuad_with_ssub_2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, +}; + +// QQPR Register Class... +static const MCPhysReg QQPR[] = { + ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, + ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, ARM_Q8_Q9, ARM_Q9_Q10, + ARM_Q10_Q11, ARM_Q11_Q12, ARM_Q12_Q13, ARM_Q13_Q14, ARM_Q14_Q15, +}; + +// QQPR Bit set. +static const uint8_t QQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, +}; + +// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... +static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, + ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, + ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, ARM_D17_D18_D19_D20, + ARM_D19_D20_D21_D22, ARM_D21_D22_D23_D24, ARM_D23_D24_D25_D26, + ARM_D25_D26_D27_D28, ARM_D27_D28_D29_D30, +}; + +// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. +static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, +}; + +// DQuad_with_ssub_4 Register Class... +static const MCPhysReg DQuad_with_ssub_4[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, + ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, + ARM_Q6_Q7, ARM_D13_D14_D15_D16, +}; + +// DQuad_with_ssub_4 Bit set. +static const uint8_t DQuad_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, +}; + +// DQuad_with_ssub_6 Register Class... +static const MCPhysReg DQuad_with_ssub_6[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, + ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, + ARM_Q6_Q7, +}; + +// DQuad_with_ssub_6 Bit set. +static const uint8_t DQuad_with_ssub_6Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, +}; + +// DQuad_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, +}; + +// DQuad_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, +}; + +// DQuad_with_qsub_0_in_MQPR Register Class... +static const MCPhysReg DQuad_with_qsub_0_in_MQPR[] = { + ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, + ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, +}; + +// DQuad_with_qsub_0_in_MQPR Bit set. +static const uint8_t DQuad_with_qsub_0_in_MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, +}; + +// DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... +static const MCPhysReg + DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, + ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, + ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, + }; + +// DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. +static const uint8_t + DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xfc, 0x03, + }; + +// DQuad_with_dsub_1_in_DPR_8 Register Class... +static const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, +}; + +// DQuad_with_dsub_1_in_DPR_8 Bit set. +static const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, +}; + +// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... +static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, + ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, + ARM_D13_D14_D15_D16, +}; + +// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. +static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, +}; + +// MQQPR Register Class... +static const MCPhysReg MQQPR[] = { + ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, + ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, +}; + +// MQQPR Bit set. +static const uint8_t MQQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, +}; + +// DQuad_with_dsub_2_in_DPR_8 Register Class... +static const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, + ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, +}; + +// DQuad_with_dsub_2_in_DPR_8 Bit set. +static const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, +}; + +// DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... +static const MCPhysReg + DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, + ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, + }; + +// DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. +static const uint8_t + DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, + }; + +// DQuad_with_dsub_3_in_DPR_8 Register Class... +static const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, +}; + +// DQuad_with_dsub_3_in_DPR_8 Bit set. +static const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, +}; + +// DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... +static const MCPhysReg + DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR + [] = { + ARM_D1_D2_D3_D4, + ARM_D3_D4_D5_D6, + ARM_D5_D6_D7_D8, + ARM_D7_D8_D9_D10, + }; + +// DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. +static const uint8_t + DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, + }; + +// DQuad_with_qsub_0_in_QPR_8 Register Class... +static const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = { + ARM_Q0_Q1, + ARM_Q1_Q2, + ARM_Q2_Q3, + ARM_Q3_Q4, +}; + +// DQuad_with_qsub_0_in_QPR_8 Bit set. +static const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, +}; + +// DQuad_with_qsub_1_in_QPR_8 Register Class... +static const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = { + ARM_Q0_Q1, + ARM_Q1_Q2, + ARM_Q2_Q3, +}; + +// DQuad_with_qsub_1_in_QPR_8 Bit set. +static const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, +}; + +// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class... +static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = { + ARM_D1_D2_D3_D4, + ARM_D3_D4_D5_D6, + ARM_D5_D6_D7_D8, +}; + +// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set. +static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, +}; + +// DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... +static const MCPhysReg + DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR + [] = { + ARM_D1_D2_D3_D4, + ARM_D3_D4_D5_D6, + }; + +// DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. +static const uint8_t + DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, + }; + +// QQQQPR Register Class... +static const MCPhysReg QQQQPR[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, + ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, + ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, ARM_Q8_Q9_Q10_Q11, + ARM_Q9_Q10_Q11_Q12, ARM_Q10_Q11_Q12_Q13, ARM_Q11_Q12_Q13_Q14, + ARM_Q12_Q13_Q14_Q15, +}; + +// QQQQPR Bit set. +static const uint8_t QQQQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, +}; + +// QQQQPR_with_ssub_0 Register Class... +static const MCPhysReg QQQQPR_with_ssub_0[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, + ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, +}; + +// QQQQPR_with_ssub_0 Bit set. +static const uint8_t QQQQPR_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, +}; + +// QQQQPR_with_ssub_4 Register Class... +static const MCPhysReg QQQQPR_with_ssub_4[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, + ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, +}; + +// QQQQPR_with_ssub_4 Bit set. +static const uint8_t QQQQPR_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, +}; + +// QQQQPR_with_ssub_8 Register Class... +static const MCPhysReg QQQQPR_with_ssub_8[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, + ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, +}; + +// QQQQPR_with_ssub_8 Bit set. +static const uint8_t QQQQPR_with_ssub_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, +}; + +// MQQQQPR Register Class... +static const MCPhysReg MQQQQPR[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, + ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, +}; + +// MQQQQPR Bit set. +static const uint8_t MQQQQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, +}; + +// MQQQQPR_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg MQQQQPR_with_dsub_0_in_DPR_8[] = { + ARM_Q0_Q1_Q2_Q3, + ARM_Q1_Q2_Q3_Q4, + ARM_Q2_Q3_Q4_Q5, + ARM_Q3_Q4_Q5_Q6, +}; + +// MQQQQPR_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t MQQQQPR_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, +}; + +// MQQQQPR_with_dsub_2_in_DPR_8 Register Class... +static const MCPhysReg MQQQQPR_with_dsub_2_in_DPR_8[] = { + ARM_Q0_Q1_Q2_Q3, + ARM_Q1_Q2_Q3_Q4, + ARM_Q2_Q3_Q4_Q5, +}; + +// MQQQQPR_with_dsub_2_in_DPR_8 Bit set. +static const uint8_t MQQQQPR_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, +}; + +// MQQQQPR_with_dsub_4_in_DPR_8 Register Class... +static const MCPhysReg MQQQQPR_with_dsub_4_in_DPR_8[] = { + ARM_Q0_Q1_Q2_Q3, + ARM_Q1_Q2_Q3_Q4, +}; + +// MQQQQPR_with_dsub_4_in_DPR_8 Bit set. +static const uint8_t MQQQQPR_with_dsub_4_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, +}; + +// MQQQQPR_with_dsub_6_in_DPR_8 Register Class... +static const MCPhysReg MQQQQPR_with_dsub_6_in_DPR_8[] = { + ARM_Q0_Q1_Q2_Q3, +}; + +// MQQQQPR_with_dsub_6_in_DPR_8 Bit set. +static const uint8_t MQQQQPR_with_dsub_6_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, +}; + +static const MCRegisterClass ARMMCRegisterClasses[] = { + { HPR, HPRBits, sizeof(HPRBits) }, + { FPWithVPR, FPWithVPRBits, sizeof(FPWithVPRBits) }, + { SPR, SPRBits, sizeof(SPRBits) }, + { FPWithVPR_with_ssub_0, FPWithVPR_with_ssub_0Bits, + sizeof(FPWithVPR_with_ssub_0Bits) }, + { GPR, GPRBits, sizeof(GPRBits) }, + { GPRwithAPSR, GPRwithAPSRBits, sizeof(GPRwithAPSRBits) }, + { GPRwithZR, GPRwithZRBits, sizeof(GPRwithZRBits) }, + { SPR_8, SPR_8Bits, sizeof(SPR_8Bits) }, + { GPRnopc, GPRnopcBits, sizeof(GPRnopcBits) }, + { GPRnosp, GPRnospBits, sizeof(GPRnospBits) }, + { GPRwithAPSR_NZCVnosp, GPRwithAPSR_NZCVnospBits, + sizeof(GPRwithAPSR_NZCVnospBits) }, + { GPRwithAPSRnosp, GPRwithAPSRnospBits, sizeof(GPRwithAPSRnospBits) }, + { GPRwithZRnosp, GPRwithZRnospBits, sizeof(GPRwithZRnospBits) }, + { GPRnoip, GPRnoipBits, sizeof(GPRnoipBits) }, + { rGPR, rGPRBits, sizeof(rGPRBits) }, + { GPRnoip_and_GPRnopc, GPRnoip_and_GPRnopcBits, + sizeof(GPRnoip_and_GPRnopcBits) }, + { GPRnoip_and_GPRnosp, GPRnoip_and_GPRnospBits, + sizeof(GPRnoip_and_GPRnospBits) }, + { GPRnoip_and_GPRwithAPSR_NZCVnosp, + GPRnoip_and_GPRwithAPSR_NZCVnospBits, + sizeof(GPRnoip_and_GPRwithAPSR_NZCVnospBits) }, + { tGPRwithpc, tGPRwithpcBits, sizeof(tGPRwithpcBits) }, + { FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8, + FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits, + sizeof(FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits) }, + { hGPR, hGPRBits, sizeof(hGPRBits) }, + { tGPR, tGPRBits, sizeof(tGPRBits) }, + { tGPREven, tGPREvenBits, sizeof(tGPREvenBits) }, + { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, + sizeof(GPRnopc_and_hGPRBits) }, + { GPRnosp_and_hGPR, GPRnosp_and_hGPRBits, + sizeof(GPRnosp_and_hGPRBits) }, + { GPRnoip_and_hGPR, GPRnoip_and_hGPRBits, + sizeof(GPRnoip_and_hGPRBits) }, + { GPRnoip_and_tGPREven, GPRnoip_and_tGPREvenBits, + sizeof(GPRnoip_and_tGPREvenBits) }, + { GPRnosp_and_GPRnopc_and_hGPR, GPRnosp_and_GPRnopc_and_hGPRBits, + sizeof(GPRnosp_and_GPRnopc_and_hGPRBits) }, + { tGPROdd, tGPROddBits, sizeof(tGPROddBits) }, + { GPRnopc_and_GPRnoip_and_hGPR, GPRnopc_and_GPRnoip_and_hGPRBits, + sizeof(GPRnopc_and_GPRnoip_and_hGPRBits) }, + { GPRnosp_and_GPRnoip_and_hGPR, GPRnosp_and_GPRnoip_and_hGPRBits, + sizeof(GPRnosp_and_GPRnoip_and_hGPRBits) }, + { tcGPR, tcGPRBits, sizeof(tcGPRBits) }, + { GPRnoip_and_tcGPR, GPRnoip_and_tcGPRBits, + sizeof(GPRnoip_and_tcGPRBits) }, + { GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR, + GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits, + sizeof(GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits) }, + { hGPR_and_tGPREven, hGPR_and_tGPREvenBits, + sizeof(hGPR_and_tGPREvenBits) }, + { tGPR_and_tGPREven, tGPR_and_tGPREvenBits, + sizeof(tGPR_and_tGPREvenBits) }, + { tGPR_and_tGPROdd, tGPR_and_tGPROddBits, + sizeof(tGPR_and_tGPROddBits) }, + { tGPREven_and_tcGPR, tGPREven_and_tcGPRBits, + sizeof(tGPREven_and_tcGPRBits) }, + { hGPR_and_GPRnoip_and_tGPREven, hGPR_and_GPRnoip_and_tGPREvenBits, + sizeof(hGPR_and_GPRnoip_and_tGPREvenBits) }, + { hGPR_and_tGPROdd, hGPR_and_tGPROddBits, + sizeof(hGPR_and_tGPROddBits) }, + { tGPREven_and_GPRnoip_and_tcGPR, tGPREven_and_GPRnoip_and_tcGPRBits, + sizeof(tGPREven_and_GPRnoip_and_tcGPRBits) }, + { tGPROdd_and_tcGPR, tGPROdd_and_tcGPRBits, + sizeof(tGPROdd_and_tcGPRBits) }, + { CCR, CCRBits, sizeof(CCRBits) }, + { FPCXTRegs, FPCXTRegsBits, sizeof(FPCXTRegsBits) }, + { GPRlr, GPRlrBits, sizeof(GPRlrBits) }, + { GPRsp, GPRspBits, sizeof(GPRspBits) }, + { VCCR, VCCRBits, sizeof(VCCRBits) }, + { cl_FPSCR_NZCV, cl_FPSCR_NZCVBits, sizeof(cl_FPSCR_NZCVBits) }, + { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, + sizeof(hGPR_and_tGPRwithpcBits) }, + { hGPR_and_tcGPR, hGPR_and_tcGPRBits, sizeof(hGPR_and_tcGPRBits) }, + { DPR, DPRBits, sizeof(DPRBits) }, + { DPR_VFP2, DPR_VFP2Bits, sizeof(DPR_VFP2Bits) }, + { DPR_8, DPR_8Bits, sizeof(DPR_8Bits) }, + { GPRPair, GPRPairBits, sizeof(GPRPairBits) }, + { GPRPairnosp, GPRPairnospBits, sizeof(GPRPairnospBits) }, + { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, + sizeof(GPRPair_with_gsub_0_in_tGPRBits) }, + { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, + sizeof(GPRPair_with_gsub_0_in_hGPRBits) }, + { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, + sizeof(GPRPair_with_gsub_0_in_tcGPRBits) }, + { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, + sizeof(GPRPair_with_gsub_1_in_tcGPRBits) }, + { GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR, + GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits, + sizeof(GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits) }, + { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, + sizeof(GPRPair_with_gsub_1_in_GPRspBits) }, + { DPairSpc, DPairSpcBits, sizeof(DPairSpcBits) }, + { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, + sizeof(DPairSpc_with_ssub_0Bits) }, + { DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, + sizeof(DPairSpc_with_ssub_4Bits) }, + { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, + sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits) }, + { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, + sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits) }, + { DPair, DPairBits, sizeof(DPairBits) }, + { DPair_with_ssub_0, DPair_with_ssub_0Bits, + sizeof(DPair_with_ssub_0Bits) }, + { QPR, QPRBits, sizeof(QPRBits) }, + { DPair_with_ssub_2, DPair_with_ssub_2Bits, + sizeof(DPair_with_ssub_2Bits) }, + { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, + sizeof(DPair_with_dsub_0_in_DPR_8Bits) }, + { MQPR, MQPRBits, sizeof(MQPRBits) }, + { QPR_VFP2, QPR_VFP2Bits, sizeof(QPR_VFP2Bits) }, + { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, + sizeof(DPair_with_dsub_1_in_DPR_8Bits) }, + { QPR_8, QPR_8Bits, sizeof(QPR_8Bits) }, + { DTriple, DTripleBits, sizeof(DTripleBits) }, + { DTripleSpc, DTripleSpcBits, sizeof(DTripleSpcBits) }, + { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, + sizeof(DTripleSpc_with_ssub_0Bits) }, + { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, + sizeof(DTriple_with_ssub_0Bits) }, + { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, + sizeof(DTriple_with_qsub_0_in_QPRBits) }, + { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, + sizeof(DTriple_with_ssub_2Bits) }, + { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, + DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, + sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, + { DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, + sizeof(DTripleSpc_with_ssub_4Bits) }, + { DTriple_with_ssub_4, DTriple_with_ssub_4Bits, + sizeof(DTriple_with_ssub_4Bits) }, + { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, + sizeof(DTripleSpc_with_ssub_8Bits) }, + { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, + sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits) }, + { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, + sizeof(DTriple_with_dsub_0_in_DPR_8Bits) }, + { DTriple_with_qsub_0_in_MQPR, DTriple_with_qsub_0_in_MQPRBits, + sizeof(DTriple_with_qsub_0_in_MQPRBits) }, + { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, + DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, + sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, + { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, + sizeof(DTriple_with_dsub_1_in_DPR_8Bits) }, + { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, + DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, + sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) }, + { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR, + DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits, + sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits) }, + { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, + sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits) }, + { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, + sizeof(DTriple_with_dsub_2_in_DPR_8Bits) }, + { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, + sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits) }, + { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, + DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, + sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) }, + { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, + sizeof(DTriple_with_qsub_0_in_QPR_8Bits) }, + { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR, + DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits, + sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits) }, + { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, + DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, + sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits) }, + { DQuadSpc, DQuadSpcBits, sizeof(DQuadSpcBits) }, + { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, + sizeof(DQuadSpc_with_ssub_0Bits) }, + { DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, + sizeof(DQuadSpc_with_ssub_4Bits) }, + { DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, + sizeof(DQuadSpc_with_ssub_8Bits) }, + { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, + sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits) }, + { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, + sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits) }, + { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, + sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits) }, + { DQuad, DQuadBits, sizeof(DQuadBits) }, + { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, + sizeof(DQuad_with_ssub_0Bits) }, + { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, + sizeof(DQuad_with_ssub_2Bits) }, + { QQPR, QQPRBits, sizeof(QQPRBits) }, + { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, + DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, + sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, + { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, + sizeof(DQuad_with_ssub_4Bits) }, + { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, + sizeof(DQuad_with_ssub_6Bits) }, + { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, + sizeof(DQuad_with_dsub_0_in_DPR_8Bits) }, + { DQuad_with_qsub_0_in_MQPR, DQuad_with_qsub_0_in_MQPRBits, + sizeof(DQuad_with_qsub_0_in_MQPRBits) }, + { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, + DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, + sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, + { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, + sizeof(DQuad_with_dsub_1_in_DPR_8Bits) }, + { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, + DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, + sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) }, + { MQQPR, MQQPRBits, sizeof(MQQPRBits) }, + { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, + sizeof(DQuad_with_dsub_2_in_DPR_8Bits) }, + { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, + DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, + sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) }, + { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, + sizeof(DQuad_with_dsub_3_in_DPR_8Bits) }, + { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, + DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, + sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) }, + { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, + sizeof(DQuad_with_qsub_0_in_QPR_8Bits) }, + { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, + sizeof(DQuad_with_qsub_1_in_QPR_8Bits) }, + { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, + DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, + sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits) }, + { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, + DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, + sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) }, + { QQQQPR, QQQQPRBits, sizeof(QQQQPRBits) }, + { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, + sizeof(QQQQPR_with_ssub_0Bits) }, + { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, + sizeof(QQQQPR_with_ssub_4Bits) }, + { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, + sizeof(QQQQPR_with_ssub_8Bits) }, + { MQQQQPR, MQQQQPRBits, sizeof(MQQQQPRBits) }, + { MQQQQPR_with_dsub_0_in_DPR_8, MQQQQPR_with_dsub_0_in_DPR_8Bits, + sizeof(MQQQQPR_with_dsub_0_in_DPR_8Bits) }, + { MQQQQPR_with_dsub_2_in_DPR_8, MQQQQPR_with_dsub_2_in_DPR_8Bits, + sizeof(MQQQQPR_with_dsub_2_in_DPR_8Bits) }, + { MQQQQPR_with_dsub_4_in_DPR_8, MQQQQPR_with_dsub_4_in_DPR_8Bits, + sizeof(MQQQQPR_with_dsub_4_in_DPR_8Bits) }, + { MQQQQPR_with_dsub_6_in_DPR_8, MQQQQPR_with_dsub_6_in_DPR_8Bits, + sizeof(MQQQQPR_with_dsub_6_in_DPR_8Bits) }, +}; + +#endif // GET_REGINFO_MC_DESC \ No newline at end of file diff --git a/thirdparty/capstone/arch/ARM/ARMGenSubtargetInfo.inc b/thirdparty/capstone/arch/ARM/ARMGenSubtargetInfo.inc new file mode 100644 index 0000000..9503323 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMGenSubtargetInfo.inc @@ -0,0 +1,241 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#ifdef GET_SUBTARGETINFO_ENUM +#undef GET_SUBTARGETINFO_ENUM + +enum { + ARM_ARMv4 = 0, + ARM_ARMv4t = 1, + ARM_ARMv5t = 2, + ARM_ARMv5te = 3, + ARM_ARMv5tej = 4, + ARM_ARMv6 = 5, + ARM_ARMv6j = 6, + ARM_ARMv6k = 7, + ARM_ARMv6kz = 8, + ARM_ARMv6m = 9, + ARM_ARMv6sm = 10, + ARM_ARMv6t2 = 11, + ARM_ARMv7a = 12, + ARM_ARMv7em = 13, + ARM_ARMv7k = 14, + ARM_ARMv7m = 15, + ARM_ARMv7r = 16, + ARM_ARMv7s = 17, + ARM_ARMv7ve = 18, + ARM_ARMv8a = 19, + ARM_ARMv8mBaseline = 20, + ARM_ARMv8mMainline = 21, + ARM_ARMv8r = 22, + ARM_ARMv9a = 23, + ARM_ARMv81a = 24, + ARM_ARMv81mMainline = 25, + ARM_ARMv82a = 26, + ARM_ARMv83a = 27, + ARM_ARMv84a = 28, + ARM_ARMv85a = 29, + ARM_ARMv86a = 30, + ARM_ARMv87a = 31, + ARM_ARMv88a = 32, + ARM_ARMv89a = 33, + ARM_ARMv91a = 34, + ARM_ARMv92a = 35, + ARM_ARMv93a = 36, + ARM_ARMv94a = 37, + ARM_Feature8MSecExt = 38, + ARM_FeatureAAPCSFrameChain = 39, + ARM_FeatureAAPCSFrameChainLeaf = 40, + ARM_FeatureAClass = 41, + ARM_FeatureAES = 42, + ARM_FeatureAcquireRelease = 43, + ARM_FeatureAtomics32 = 44, + ARM_FeatureAvoidMOVsShOp = 45, + ARM_FeatureAvoidPartialCPSR = 46, + ARM_FeatureBF16 = 47, + ARM_FeatureCLRBHB = 48, + ARM_FeatureCRC = 49, + ARM_FeatureCheapPredicableCPSR = 50, + ARM_FeatureCheckVLDnAlign = 51, + ARM_FeatureCoprocCDE0 = 52, + ARM_FeatureCoprocCDE1 = 53, + ARM_FeatureCoprocCDE2 = 54, + ARM_FeatureCoprocCDE3 = 55, + ARM_FeatureCoprocCDE4 = 56, + ARM_FeatureCoprocCDE5 = 57, + ARM_FeatureCoprocCDE6 = 58, + ARM_FeatureCoprocCDE7 = 59, + ARM_FeatureCrypto = 60, + ARM_FeatureD32 = 61, + ARM_FeatureDB = 62, + ARM_FeatureDFB = 63, + ARM_FeatureDSP = 64, + ARM_FeatureDontWidenVMOVS = 65, + ARM_FeatureDotProd = 66, + ARM_FeatureExecuteOnly = 67, + ARM_FeatureExpandMLx = 68, + ARM_FeatureFP16 = 69, + ARM_FeatureFP16FML = 70, + ARM_FeatureFP64 = 71, + ARM_FeatureFPAO = 72, + ARM_FeatureFPARMv8 = 73, + ARM_FeatureFPARMv8_D16 = 74, + ARM_FeatureFPARMv8_D16_SP = 75, + ARM_FeatureFPARMv8_SP = 76, + ARM_FeatureFPRegs = 77, + ARM_FeatureFPRegs16 = 78, + ARM_FeatureFPRegs64 = 79, + ARM_FeatureFixCMSE_CVE_2021_35465 = 80, + ARM_FeatureFixCortexA57AES1742098 = 81, + ARM_FeatureFullFP16 = 82, + ARM_FeatureFuseAES = 83, + ARM_FeatureFuseLiterals = 84, + ARM_FeatureHWDivARM = 85, + ARM_FeatureHWDivThumb = 86, + ARM_FeatureHardenSlsBlr = 87, + ARM_FeatureHardenSlsNoComdat = 88, + ARM_FeatureHardenSlsRetBr = 89, + ARM_FeatureHasNoBranchPredictor = 90, + ARM_FeatureHasRetAddrStack = 91, + ARM_FeatureHasSlowFPVFMx = 92, + ARM_FeatureHasSlowFPVMLx = 93, + ARM_FeatureHasVMLxHazards = 94, + ARM_FeatureLOB = 95, + ARM_FeatureLongCalls = 96, + ARM_FeatureMClass = 97, + ARM_FeatureMP = 98, + ARM_FeatureMVEVectorCostFactor1 = 99, + ARM_FeatureMVEVectorCostFactor2 = 100, + ARM_FeatureMVEVectorCostFactor4 = 101, + ARM_FeatureMatMulInt8 = 102, + ARM_FeatureMuxedUnits = 103, + ARM_FeatureNEON = 104, + ARM_FeatureNEONForFP = 105, + ARM_FeatureNEONForFPMovs = 106, + ARM_FeatureNaClTrap = 107, + ARM_FeatureNoARM = 108, + ARM_FeatureNoBTIAtReturnTwice = 109, + ARM_FeatureNoMovt = 110, + ARM_FeatureNoNegativeImmediates = 111, + ARM_FeatureNoPostRASched = 112, + ARM_FeatureNonpipelinedVFP = 113, + ARM_FeaturePACBTI = 114, + ARM_FeaturePerfMon = 115, + ARM_FeaturePref32BitThumb = 116, + ARM_FeaturePrefISHSTBarrier = 117, + ARM_FeaturePrefLoopAlign32 = 118, + ARM_FeaturePreferVMOVSR = 119, + ARM_FeatureProfUnpredicate = 120, + ARM_FeatureRAS = 121, + ARM_FeatureRClass = 122, + ARM_FeatureReadTp = 123, + ARM_FeatureReserveR9 = 124, + ARM_FeatureSB = 125, + ARM_FeatureSHA2 = 126, + ARM_FeatureSlowFPBrcc = 127, + ARM_FeatureSlowLoadDSubreg = 128, + ARM_FeatureSlowOddRegister = 129, + ARM_FeatureSlowVDUP32 = 130, + ARM_FeatureSlowVGETLNi32 = 131, + ARM_FeatureSplatVFPToNeon = 132, + ARM_FeatureStrictAlign = 133, + ARM_FeatureThumb2 = 134, + ARM_FeatureTrustZone = 135, + ARM_FeatureUseMIPipeliner = 136, + ARM_FeatureUseMISched = 137, + ARM_FeatureUseWideStrideVFP = 138, + ARM_FeatureV7Clrex = 139, + ARM_FeatureVFP2 = 140, + ARM_FeatureVFP2_SP = 141, + ARM_FeatureVFP3 = 142, + ARM_FeatureVFP3_D16 = 143, + ARM_FeatureVFP3_D16_SP = 144, + ARM_FeatureVFP3_SP = 145, + ARM_FeatureVFP4 = 146, + ARM_FeatureVFP4_D16 = 147, + ARM_FeatureVFP4_D16_SP = 148, + ARM_FeatureVFP4_SP = 149, + ARM_FeatureVMLxForwarding = 150, + ARM_FeatureVirtualization = 151, + ARM_FeatureZCZeroing = 152, + ARM_HasCDEOps = 153, + ARM_HasMVEFloatOps = 154, + ARM_HasMVEIntegerOps = 155, + ARM_HasV4TOps = 156, + ARM_HasV5TEOps = 157, + ARM_HasV5TOps = 158, + ARM_HasV6KOps = 159, + ARM_HasV6MOps = 160, + ARM_HasV6Ops = 161, + ARM_HasV6T2Ops = 162, + ARM_HasV7Ops = 163, + ARM_HasV8MBaselineOps = 164, + ARM_HasV8MMainlineOps = 165, + ARM_HasV8Ops = 166, + ARM_HasV8_1MMainlineOps = 167, + ARM_HasV8_1aOps = 168, + ARM_HasV8_2aOps = 169, + ARM_HasV8_3aOps = 170, + ARM_HasV8_4aOps = 171, + ARM_HasV8_5aOps = 172, + ARM_HasV8_6aOps = 173, + ARM_HasV8_7aOps = 174, + ARM_HasV8_8aOps = 175, + ARM_HasV8_9aOps = 176, + ARM_HasV9_0aOps = 177, + ARM_HasV9_1aOps = 178, + ARM_HasV9_2aOps = 179, + ARM_HasV9_3aOps = 180, + ARM_HasV9_4aOps = 181, + ARM_IWMMXT = 182, + ARM_IWMMXT2 = 183, + ARM_ModeBigEndianInstructions = 184, + ARM_ModeSoftFloat = 185, + ARM_ModeThumb = 186, + ARM_ProcA5 = 187, + ARM_ProcA7 = 188, + ARM_ProcA8 = 189, + ARM_ProcA9 = 190, + ARM_ProcA12 = 191, + ARM_ProcA15 = 192, + ARM_ProcA17 = 193, + ARM_ProcA32 = 194, + ARM_ProcA35 = 195, + ARM_ProcA53 = 196, + ARM_ProcA55 = 197, + ARM_ProcA57 = 198, + ARM_ProcA72 = 199, + ARM_ProcA73 = 200, + ARM_ProcA75 = 201, + ARM_ProcA76 = 202, + ARM_ProcA77 = 203, + ARM_ProcA78 = 204, + ARM_ProcA78C = 205, + ARM_ProcA710 = 206, + ARM_ProcExynos = 207, + ARM_ProcKrait = 208, + ARM_ProcKryo = 209, + ARM_ProcM3 = 210, + ARM_ProcM7 = 211, + ARM_ProcR4 = 212, + ARM_ProcR5 = 213, + ARM_ProcR7 = 214, + ARM_ProcR52 = 215, + ARM_ProcSwift = 216, + ARM_ProcV1 = 217, + ARM_ProcX1 = 218, + ARM_ProcX1C = 219, + ARM_XScale = 220, + ARM_NumSubtargetFeatures = 221 +}; +#endif // GET_SUBTARGETINFO_ENUM diff --git a/thirdparty/capstone/arch/ARM/ARMGenSystemRegister.inc b/thirdparty/capstone/arch/ARM/ARMGenSystemRegister.inc new file mode 100644 index 0000000..2a714d5 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMGenSystemRegister.inc @@ -0,0 +1,575 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#ifdef GET_BANKEDREG_DECL +#endif + +#ifdef GET_MCLASSSYSREG_DECL +#endif + +#ifdef GET_BANKEDREG_DECL +const ARMBankedReg_BankedReg * +ARMBankedReg_lookupBankedRegByName(const char *Name); +const ARMBankedReg_BankedReg * +ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding); +#endif + +#ifdef GET_MCLASSSYSREG_DECL +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegByName(const char *Name); +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12); +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8); +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding); +#endif + +#ifdef GET_BANKEDREG_IMPL +static const ARMBankedReg_BankedReg BankedRegsList[] = { + { "elr_hyp", { .bankedreg = ARM_BANKEDREG_ELR_HYP }, 0x1E }, // 0 + { "lr_abt", { .bankedreg = ARM_BANKEDREG_LR_ABT }, 0x14 }, // 1 + { "lr_fiq", { .bankedreg = ARM_BANKEDREG_LR_FIQ }, 0xE }, // 2 + { "lr_irq", { .bankedreg = ARM_BANKEDREG_LR_IRQ }, 0x10 }, // 3 + { "lr_mon", { .bankedreg = ARM_BANKEDREG_LR_MON }, 0x1C }, // 4 + { "lr_svc", { .bankedreg = ARM_BANKEDREG_LR_SVC }, 0x12 }, // 5 + { "lr_und", { .bankedreg = ARM_BANKEDREG_LR_UND }, 0x16 }, // 6 + { "lr_usr", { .bankedreg = ARM_BANKEDREG_LR_USR }, 0x6 }, // 7 + { "r10_fiq", { .bankedreg = ARM_BANKEDREG_R10_FIQ }, 0xA }, // 8 + { "r10_usr", { .bankedreg = ARM_BANKEDREG_R10_USR }, 0x2 }, // 9 + { "r11_fiq", { .bankedreg = ARM_BANKEDREG_R11_FIQ }, 0xB }, // 10 + { "r11_usr", { .bankedreg = ARM_BANKEDREG_R11_USR }, 0x3 }, // 11 + { "r12_fiq", { .bankedreg = ARM_BANKEDREG_R12_FIQ }, 0xC }, // 12 + { "r12_usr", { .bankedreg = ARM_BANKEDREG_R12_USR }, 0x4 }, // 13 + { "r8_fiq", { .bankedreg = ARM_BANKEDREG_R8_FIQ }, 0x8 }, // 14 + { "r8_usr", { .bankedreg = ARM_BANKEDREG_R8_USR }, 0x0 }, // 15 + { "r9_fiq", { .bankedreg = ARM_BANKEDREG_R9_FIQ }, 0x9 }, // 16 + { "r9_usr", { .bankedreg = ARM_BANKEDREG_R9_USR }, 0x1 }, // 17 + { "spsr_abt", { .bankedreg = ARM_BANKEDREG_SPSR_ABT }, 0x34 }, // 18 + { "spsr_fiq", { .bankedreg = ARM_BANKEDREG_SPSR_FIQ }, 0x2E }, // 19 + { "spsr_hyp", { .bankedreg = ARM_BANKEDREG_SPSR_HYP }, 0x3E }, // 20 + { "spsr_irq", { .bankedreg = ARM_BANKEDREG_SPSR_IRQ }, 0x30 }, // 21 + { "spsr_mon", { .bankedreg = ARM_BANKEDREG_SPSR_MON }, 0x3C }, // 22 + { "spsr_svc", { .bankedreg = ARM_BANKEDREG_SPSR_SVC }, 0x32 }, // 23 + { "spsr_und", { .bankedreg = ARM_BANKEDREG_SPSR_UND }, 0x36 }, // 24 + { "sp_abt", { .bankedreg = ARM_BANKEDREG_SP_ABT }, 0x15 }, // 25 + { "sp_fiq", { .bankedreg = ARM_BANKEDREG_SP_FIQ }, 0xD }, // 26 + { "sp_hyp", { .bankedreg = ARM_BANKEDREG_SP_HYP }, 0x1F }, // 27 + { "sp_irq", { .bankedreg = ARM_BANKEDREG_SP_IRQ }, 0x11 }, // 28 + { "sp_mon", { .bankedreg = ARM_BANKEDREG_SP_MON }, 0x1D }, // 29 + { "sp_svc", { .bankedreg = ARM_BANKEDREG_SP_SVC }, 0x13 }, // 30 + { "sp_und", { .bankedreg = ARM_BANKEDREG_SP_UND }, 0x17 }, // 31 + { "sp_usr", { .bankedreg = ARM_BANKEDREG_SP_USR }, 0x5 }, // 32 +}; + +const ARMBankedReg_BankedReg * +ARMBankedReg_lookupBankedRegByName(const char *Name) +{ + static const struct IndexTypeStr Index[] = { + { "ELR_HYP", 0 }, { "LR_ABT", 1 }, { "LR_FIQ", 2 }, + { "LR_IRQ", 3 }, { "LR_MON", 4 }, { "LR_SVC", 5 }, + { "LR_UND", 6 }, { "LR_USR", 7 }, { "R10_FIQ", 8 }, + { "R10_USR", 9 }, { "R11_FIQ", 10 }, { "R11_USR", 11 }, + { "R12_FIQ", 12 }, { "R12_USR", 13 }, { "R8_FIQ", 14 }, + { "R8_USR", 15 }, { "R9_FIQ", 16 }, { "R9_USR", 17 }, + { "SPSR_ABT", 18 }, { "SPSR_FIQ", 19 }, { "SPSR_HYP", 20 }, + { "SPSR_IRQ", 21 }, { "SPSR_MON", 22 }, { "SPSR_SVC", 23 }, + { "SPSR_UND", 24 }, { "SP_ABT", 25 }, { "SP_FIQ", 26 }, + { "SP_HYP", 27 }, { "SP_IRQ", 28 }, { "SP_MON", 29 }, + { "SP_SVC", 30 }, { "SP_UND", 31 }, { "SP_USR", 32 }, + }; + + unsigned i = + binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name); + if (i == -1) + return NULL; + else + return &BankedRegsList[Index[i].index]; +} + +const ARMBankedReg_BankedReg * +ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding) +{ + static const struct IndexType Index[] = { + { 0x0, 15 }, { 0x1, 17 }, { 0x2, 9 }, { 0x3, 11 }, + { 0x4, 13 }, { 0x5, 32 }, { 0x6, 7 }, { 0x8, 14 }, + { 0x9, 16 }, { 0xA, 8 }, { 0xB, 10 }, { 0xC, 12 }, + { 0xD, 26 }, { 0xE, 2 }, { 0x10, 3 }, { 0x11, 28 }, + { 0x12, 5 }, { 0x13, 30 }, { 0x14, 1 }, { 0x15, 25 }, + { 0x16, 6 }, { 0x17, 31 }, { 0x1C, 4 }, { 0x1D, 29 }, + { 0x1E, 0 }, { 0x1F, 27 }, { 0x2E, 19 }, { 0x30, 21 }, + { 0x32, 23 }, { 0x34, 18 }, { 0x36, 24 }, { 0x3C, 22 }, + { 0x3E, 20 }, + }; + + unsigned i = + binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &BankedRegsList[Index[i].index]; +} + +#endif + +#ifdef GET_MCLASSSYSREG_IMPL +static const ARMSysReg_MClassSysReg MClassSysRegsList[] = { + { "apsr", + { .mclasssysreg = ARM_MCLASSSYSREG_APSR }, + 0x800, + 0x100, + 0x800, + { 0 } }, // 0 + { "apsr_g", + { .mclasssysreg = ARM_MCLASSSYSREG_APSR_G }, + 0x400, + 0x0, + 0x400, + { ARM_FeatureDSP } }, // 1 + { "apsr_nzcvq", + { .mclasssysreg = ARM_MCLASSSYSREG_APSR_NZCVQ }, + 0x1800, + 0x200, + 0x800, + { 0 } }, // 2 + { "apsr_nzcvqg", + { .mclasssysreg = ARM_MCLASSSYSREG_APSR_NZCVQG }, + 0xC00, + 0x300, + 0xC00, + { ARM_FeatureDSP } }, // 3 + { "basepri", + { .mclasssysreg = ARM_MCLASSSYSREG_BASEPRI }, + 0x811, + 0x111, + 0x811, + { ARM_HasV7Ops } }, // 4 + { "basepri_max", + { .mclasssysreg = ARM_MCLASSSYSREG_BASEPRI_MAX }, + 0x812, + 0x112, + 0x812, + { ARM_HasV7Ops } }, // 5 + { "basepri_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_BASEPRI_NS }, + 0x891, + 0x191, + 0x891, + { ARM_Feature8MSecExt, ARM_HasV7Ops } }, // 6 + { "control", + { .mclasssysreg = ARM_MCLASSSYSREG_CONTROL }, + 0x814, + 0x114, + 0x814, + { 0 } }, // 7 + { "control_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_CONTROL_NS }, + 0x894, + 0x194, + 0x894, + { ARM_Feature8MSecExt } }, // 8 + { "eapsr", + { .mclasssysreg = ARM_MCLASSSYSREG_EAPSR }, + 0x802, + 0x102, + 0x802, + { 0 } }, // 9 + { "eapsr_g", + { .mclasssysreg = ARM_MCLASSSYSREG_EAPSR_G }, + 0x402, + 0x2, + 0x402, + { ARM_FeatureDSP } }, // 10 + { "eapsr_nzcvq", + { .mclasssysreg = ARM_MCLASSSYSREG_EAPSR_NZCVQ }, + 0x1802, + 0x202, + 0x802, + { 0 } }, // 11 + { "eapsr_nzcvqg", + { .mclasssysreg = ARM_MCLASSSYSREG_EAPSR_NZCVQG }, + 0xC02, + 0x302, + 0xC02, + { ARM_FeatureDSP } }, // 12 + { "epsr", + { .mclasssysreg = ARM_MCLASSSYSREG_EPSR }, + 0x806, + 0x106, + 0x806, + { 0 } }, // 13 + { "faultmask", + { .mclasssysreg = ARM_MCLASSSYSREG_FAULTMASK }, + 0x813, + 0x113, + 0x813, + { ARM_HasV7Ops } }, // 14 + { "faultmask_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_FAULTMASK_NS }, + 0x893, + 0x193, + 0x893, + { ARM_Feature8MSecExt, ARM_HasV7Ops } }, // 15 + { "iapsr", + { .mclasssysreg = ARM_MCLASSSYSREG_IAPSR }, + 0x801, + 0x101, + 0x801, + { 0 } }, // 16 + { "iapsr_g", + { .mclasssysreg = ARM_MCLASSSYSREG_IAPSR_G }, + 0x401, + 0x1, + 0x401, + { ARM_FeatureDSP } }, // 17 + { "iapsr_nzcvq", + { .mclasssysreg = ARM_MCLASSSYSREG_IAPSR_NZCVQ }, + 0x1801, + 0x201, + 0x801, + { 0 } }, // 18 + { "iapsr_nzcvqg", + { .mclasssysreg = ARM_MCLASSSYSREG_IAPSR_NZCVQG }, + 0xC01, + 0x301, + 0xC01, + { ARM_FeatureDSP } }, // 19 + { "iepsr", + { .mclasssysreg = ARM_MCLASSSYSREG_IEPSR }, + 0x807, + 0x107, + 0x807, + { 0 } }, // 20 + { "ipsr", + { .mclasssysreg = ARM_MCLASSSYSREG_IPSR }, + 0x805, + 0x105, + 0x805, + { 0 } }, // 21 + { "msp", + { .mclasssysreg = ARM_MCLASSSYSREG_MSP }, + 0x808, + 0x108, + 0x808, + { 0 } }, // 22 + { "msplim", + { .mclasssysreg = ARM_MCLASSSYSREG_MSPLIM }, + 0x80A, + 0x10A, + 0x80A, + { ARM_HasV8MBaselineOps } }, // 23 + { "msplim_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_MSPLIM_NS }, + 0x88A, + 0x18A, + 0x88A, + { ARM_Feature8MSecExt, ARM_HasV8MBaselineOps } }, // 24 + { "msp_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_MSP_NS }, + 0x888, + 0x188, + 0x888, + { ARM_Feature8MSecExt } }, // 25 + { "pac_key_p_0", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_0 }, + 0x820, + 0x120, + 0x820, + { ARM_FeaturePACBTI } }, // 26 + { "pac_key_p_0_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_0_NS }, + 0x8A0, + 0x1A0, + 0x8A0, + { ARM_FeaturePACBTI } }, // 27 + { "pac_key_p_1", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_1 }, + 0x821, + 0x121, + 0x821, + { ARM_FeaturePACBTI } }, // 28 + { "pac_key_p_1_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_1_NS }, + 0x8A1, + 0x1A1, + 0x8A1, + { ARM_FeaturePACBTI } }, // 29 + { "pac_key_p_2", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_2 }, + 0x822, + 0x122, + 0x822, + { ARM_FeaturePACBTI } }, // 30 + { "pac_key_p_2_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_2_NS }, + 0x8A2, + 0x1A2, + 0x8A2, + { ARM_FeaturePACBTI } }, // 31 + { "pac_key_p_3", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_3 }, + 0x823, + 0x123, + 0x823, + { ARM_FeaturePACBTI } }, // 32 + { "pac_key_p_3_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_P_3_NS }, + 0x8A3, + 0x1A3, + 0x8A3, + { ARM_FeaturePACBTI } }, // 33 + { "pac_key_u_0", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_0 }, + 0x824, + 0x124, + 0x824, + { ARM_FeaturePACBTI } }, // 34 + { "pac_key_u_0_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_0_NS }, + 0x8A4, + 0x1A4, + 0x8A4, + { ARM_FeaturePACBTI } }, // 35 + { "pac_key_u_1", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_1 }, + 0x825, + 0x125, + 0x825, + { ARM_FeaturePACBTI } }, // 36 + { "pac_key_u_1_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_1_NS }, + 0x8A5, + 0x1A5, + 0x8A5, + { ARM_FeaturePACBTI } }, // 37 + { "pac_key_u_2", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_2 }, + 0x826, + 0x126, + 0x826, + { ARM_FeaturePACBTI } }, // 38 + { "pac_key_u_2_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_2_NS }, + 0x8A6, + 0x1A6, + 0x8A6, + { ARM_FeaturePACBTI } }, // 39 + { "pac_key_u_3", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_3 }, + 0x827, + 0x127, + 0x827, + { ARM_FeaturePACBTI } }, // 40 + { "pac_key_u_3_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_PAC_KEY_U_3_NS }, + 0x8A7, + 0x1A7, + 0x8A7, + { ARM_FeaturePACBTI } }, // 41 + { "primask", + { .mclasssysreg = ARM_MCLASSSYSREG_PRIMASK }, + 0x810, + 0x110, + 0x810, + { 0 } }, // 42 + { "primask_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_PRIMASK_NS }, + 0x890, + 0x190, + 0x890, + { 0 } }, // 43 + { "psp", + { .mclasssysreg = ARM_MCLASSSYSREG_PSP }, + 0x809, + 0x109, + 0x809, + { 0 } }, // 44 + { "psplim", + { .mclasssysreg = ARM_MCLASSSYSREG_PSPLIM }, + 0x80B, + 0x10B, + 0x80B, + { ARM_HasV8MBaselineOps } }, // 45 + { "psplim_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_PSPLIM_NS }, + 0x88B, + 0x18B, + 0x88B, + { ARM_Feature8MSecExt, ARM_HasV8MBaselineOps } }, // 46 + { "psp_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_PSP_NS }, + 0x889, + 0x189, + 0x889, + { ARM_Feature8MSecExt } }, // 47 + { "sp_ns", + { .mclasssysreg = ARM_MCLASSSYSREG_SP_NS }, + 0x898, + 0x198, + 0x898, + { ARM_Feature8MSecExt } }, // 48 + { "xpsr", + { .mclasssysreg = ARM_MCLASSSYSREG_XPSR }, + 0x803, + 0x103, + 0x803, + { 0 } }, // 49 + { "xpsr_g", + { .mclasssysreg = ARM_MCLASSSYSREG_XPSR_G }, + 0x403, + 0x3, + 0x403, + { ARM_FeatureDSP } }, // 50 + { "xpsr_nzcvq", + { .mclasssysreg = ARM_MCLASSSYSREG_XPSR_NZCVQ }, + 0x1803, + 0x203, + 0x803, + { 0 } }, // 51 + { "xpsr_nzcvqg", + { .mclasssysreg = ARM_MCLASSSYSREG_XPSR_NZCVQG }, + 0xC03, + 0x303, + 0xC03, + { ARM_FeatureDSP } }, // 52 +}; + +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegByName(const char *Name) +{ + static const struct IndexTypeStr Index[] = { + { "APSR", 0 }, { "APSR_G", 1 }, + { "APSR_NZCVQ", 2 }, { "APSR_NZCVQG", 3 }, + { "BASEPRI", 4 }, { "BASEPRI_MAX", 5 }, + { "BASEPRI_NS", 6 }, { "CONTROL", 7 }, + { "CONTROL_NS", 8 }, { "EAPSR", 9 }, + { "EAPSR_G", 10 }, { "EAPSR_NZCVQ", 11 }, + { "EAPSR_NZCVQG", 12 }, { "EPSR", 13 }, + { "FAULTMASK", 14 }, { "FAULTMASK_NS", 15 }, + { "IAPSR", 16 }, { "IAPSR_G", 17 }, + { "IAPSR_NZCVQ", 18 }, { "IAPSR_NZCVQG", 19 }, + { "IEPSR", 20 }, { "IPSR", 21 }, + { "MSP", 22 }, { "MSPLIM", 23 }, + { "MSPLIM_NS", 24 }, { "MSP_NS", 25 }, + { "PAC_KEY_P_0", 26 }, { "PAC_KEY_P_0_NS", 27 }, + { "PAC_KEY_P_1", 28 }, { "PAC_KEY_P_1_NS", 29 }, + { "PAC_KEY_P_2", 30 }, { "PAC_KEY_P_2_NS", 31 }, + { "PAC_KEY_P_3", 32 }, { "PAC_KEY_P_3_NS", 33 }, + { "PAC_KEY_U_0", 34 }, { "PAC_KEY_U_0_NS", 35 }, + { "PAC_KEY_U_1", 36 }, { "PAC_KEY_U_1_NS", 37 }, + { "PAC_KEY_U_2", 38 }, { "PAC_KEY_U_2_NS", 39 }, + { "PAC_KEY_U_3", 40 }, { "PAC_KEY_U_3_NS", 41 }, + { "PRIMASK", 42 }, { "PRIMASK_NS", 43 }, + { "PSP", 44 }, { "PSPLIM", 45 }, + { "PSPLIM_NS", 46 }, { "PSP_NS", 47 }, + { "SP_NS", 48 }, { "XPSR", 49 }, + { "XPSR_G", 50 }, { "XPSR_NZCVQ", 51 }, + { "XPSR_NZCVQG", 52 }, + }; + + unsigned i = + binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name); + if (i == -1) + return NULL; + else + return &MClassSysRegsList[Index[i].index]; +} + +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12) +{ + static const struct IndexType Index[] = { + { 0x400, 1 }, { 0x401, 17 }, { 0x402, 10 }, { 0x403, 50 }, + { 0x800, 0 }, { 0x801, 16 }, { 0x802, 9 }, { 0x803, 49 }, + { 0x805, 21 }, { 0x806, 13 }, { 0x807, 20 }, { 0x808, 22 }, + { 0x809, 44 }, { 0x80A, 23 }, { 0x80B, 45 }, { 0x810, 42 }, + { 0x811, 4 }, { 0x812, 5 }, { 0x813, 14 }, { 0x814, 7 }, + { 0x820, 26 }, { 0x821, 28 }, { 0x822, 30 }, { 0x823, 32 }, + { 0x824, 34 }, { 0x825, 36 }, { 0x826, 38 }, { 0x827, 40 }, + { 0x888, 25 }, { 0x889, 47 }, { 0x88A, 24 }, { 0x88B, 46 }, + { 0x890, 43 }, { 0x891, 6 }, { 0x893, 15 }, { 0x894, 8 }, + { 0x898, 48 }, { 0x8A0, 27 }, { 0x8A1, 29 }, { 0x8A2, 31 }, + { 0x8A3, 33 }, { 0x8A4, 35 }, { 0x8A5, 37 }, { 0x8A6, 39 }, + { 0x8A7, 41 }, { 0xC00, 3 }, { 0xC01, 19 }, { 0xC02, 12 }, + { 0xC03, 52 }, { 0x1800, 2 }, { 0x1801, 18 }, { 0x1802, 11 }, + { 0x1803, 51 }, + }; + + unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), + M1Encoding12); + if (i == -1) + return NULL; + else + return &MClassSysRegsList[Index[i].index]; +} + +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8) +{ + static const struct IndexType Index[] = { + { 0x0, 1 }, { 0x1, 17 }, { 0x2, 10 }, { 0x3, 50 }, + { 0x100, 0 }, { 0x101, 16 }, { 0x102, 9 }, { 0x103, 49 }, + { 0x105, 21 }, { 0x106, 13 }, { 0x107, 20 }, { 0x108, 22 }, + { 0x109, 44 }, { 0x10A, 23 }, { 0x10B, 45 }, { 0x110, 42 }, + { 0x111, 4 }, { 0x112, 5 }, { 0x113, 14 }, { 0x114, 7 }, + { 0x120, 26 }, { 0x121, 28 }, { 0x122, 30 }, { 0x123, 32 }, + { 0x124, 34 }, { 0x125, 36 }, { 0x126, 38 }, { 0x127, 40 }, + { 0x188, 25 }, { 0x189, 47 }, { 0x18A, 24 }, { 0x18B, 46 }, + { 0x190, 43 }, { 0x191, 6 }, { 0x193, 15 }, { 0x194, 8 }, + { 0x198, 48 }, { 0x1A0, 27 }, { 0x1A1, 29 }, { 0x1A2, 31 }, + { 0x1A3, 33 }, { 0x1A4, 35 }, { 0x1A5, 37 }, { 0x1A6, 39 }, + { 0x1A7, 41 }, { 0x200, 2 }, { 0x201, 18 }, { 0x202, 11 }, + { 0x203, 51 }, { 0x300, 3 }, { 0x301, 19 }, { 0x302, 12 }, + { 0x303, 52 }, + }; + + unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), + M2M3Encoding8); + if (i == -1) + return NULL; + else + return &MClassSysRegsList[Index[i].index]; +} + +const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding) +{ + static const struct IndexType Index[] = { + { 0x400, 1 }, { 0x401, 17 }, { 0x402, 10 }, { 0x403, 50 }, + { 0x800, 0 }, { 0x800, 2 }, { 0x801, 16 }, { 0x801, 18 }, + { 0x802, 9 }, { 0x802, 11 }, { 0x803, 49 }, { 0x803, 51 }, + { 0x805, 21 }, { 0x806, 13 }, { 0x807, 20 }, { 0x808, 22 }, + { 0x809, 44 }, { 0x80A, 23 }, { 0x80B, 45 }, { 0x810, 42 }, + { 0x811, 4 }, { 0x812, 5 }, { 0x813, 14 }, { 0x814, 7 }, + { 0x820, 26 }, { 0x821, 28 }, { 0x822, 30 }, { 0x823, 32 }, + { 0x824, 34 }, { 0x825, 36 }, { 0x826, 38 }, { 0x827, 40 }, + { 0x888, 25 }, { 0x889, 47 }, { 0x88A, 24 }, { 0x88B, 46 }, + { 0x890, 43 }, { 0x891, 6 }, { 0x893, 15 }, { 0x894, 8 }, + { 0x898, 48 }, { 0x8A0, 27 }, { 0x8A1, 29 }, { 0x8A2, 31 }, + { 0x8A3, 33 }, { 0x8A4, 35 }, { 0x8A5, 37 }, { 0x8A6, 39 }, + { 0x8A7, 41 }, { 0xC00, 3 }, { 0xC01, 19 }, { 0xC02, 12 }, + { 0xC03, 52 }, + }; + + unsigned i = + binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &MClassSysRegsList[Index[i].index]; +} + +#endif + +#undef GET_BANKEDREG_DECL +#undef GET_MCLASSSYSREG_DECL diff --git a/thirdparty/capstone/arch/ARM/ARMInsnEnum.inc b/thirdparty/capstone/arch/ARM/ARMInsnEnum.inc new file mode 100644 index 0000000..7e47d4a --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMInsnEnum.inc @@ -0,0 +1,162 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ +/* By Rot127 , 2023 */ + +/* Auto generated file. Do not edit. */ +/* Code generator: https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + +ARM_INS___BRKDIV0, ARM_INS_ADC, ARM_INS_ADD, ARM_INS_ADDW, ARM_INS_ADR, + ARM_INS_AESD, ARM_INS_AESE, ARM_INS_AESIMC, ARM_INS_AESMC, ARM_INS_AND, + ARM_INS_ASR, ARM_INS_ASRL, ARM_INS_AUT, ARM_INS_AUTG, ARM_INS_B, + ARM_INS_BF, ARM_INS_BFC, ARM_INS_BFCSEL, ARM_INS_BFI, ARM_INS_BFL, + ARM_INS_BFLX, ARM_INS_BFX, ARM_INS_BIC, ARM_INS_BKPT, ARM_INS_BL, + ARM_INS_BLX, ARM_INS_BLXNS, ARM_INS_BTI, ARM_INS_BX, ARM_INS_BXAUT, + ARM_INS_BXJ, ARM_INS_BXNS, ARM_INS_CBNZ, ARM_INS_CBZ, ARM_INS_CDP, + ARM_INS_CDP2, ARM_INS_CINC, ARM_INS_CINV, ARM_INS_CLRBHB, ARM_INS_CLREX, + ARM_INS_CLRM, ARM_INS_CLZ, ARM_INS_CMN, ARM_INS_CMP, ARM_INS_CNEG, + ARM_INS_CPS, ARM_INS_CRC32B, ARM_INS_CRC32CB, ARM_INS_CRC32CH, + ARM_INS_CRC32CW, ARM_INS_CRC32H, ARM_INS_CRC32W, ARM_INS_CSDB, + ARM_INS_CSEL, ARM_INS_CSET, ARM_INS_CSETM, ARM_INS_CSINC, ARM_INS_CSINV, + ARM_INS_CSNEG, ARM_INS_CX1, ARM_INS_CX1A, ARM_INS_CX1D, ARM_INS_CX1DA, + ARM_INS_CX2, ARM_INS_CX2A, ARM_INS_CX2D, ARM_INS_CX2DA, ARM_INS_CX3, + ARM_INS_CX3A, ARM_INS_CX3D, ARM_INS_CX3DA, ARM_INS_DBG, ARM_INS_DCPS1, + ARM_INS_DCPS2, ARM_INS_DCPS3, ARM_INS_DFB, ARM_INS_DLS, ARM_INS_DLSTP, + ARM_INS_DMB, ARM_INS_DSB, ARM_INS_EOR, ARM_INS_ERET, ARM_INS_ESB, + ARM_INS_FADDD, ARM_INS_FADDS, ARM_INS_FCMPZD, ARM_INS_FCMPZS, + ARM_INS_FCONSTD, ARM_INS_FCONSTS, ARM_INS_FLDMDBX, ARM_INS_FLDMIAX, + ARM_INS_FMDHR, ARM_INS_FMDLR, ARM_INS_FMSTAT, ARM_INS_FSTMDBX, + ARM_INS_FSTMIAX, ARM_INS_FSUBD, ARM_INS_FSUBS, ARM_INS_HINT, + ARM_INS_HLT, ARM_INS_HVC, ARM_INS_ISB, ARM_INS_IT, ARM_INS_LCTP, + ARM_INS_LDA, ARM_INS_LDAB, ARM_INS_LDAEX, ARM_INS_LDAEXB, + ARM_INS_LDAEXD, ARM_INS_LDAEXH, ARM_INS_LDAH, ARM_INS_LDC, ARM_INS_LDC2, + ARM_INS_LDC2L, ARM_INS_LDCL, ARM_INS_LDM, ARM_INS_LDMDA, ARM_INS_LDMDB, + ARM_INS_LDMIB, ARM_INS_LDR, ARM_INS_LDRB, ARM_INS_LDRBT, ARM_INS_LDRD, + ARM_INS_LDREX, ARM_INS_LDREXB, ARM_INS_LDREXD, ARM_INS_LDREXH, + ARM_INS_LDRH, ARM_INS_LDRHT, ARM_INS_LDRSB, ARM_INS_LDRSBT, + ARM_INS_LDRSH, ARM_INS_LDRSHT, ARM_INS_LDRT, ARM_INS_LE, ARM_INS_LETP, + ARM_INS_LSL, ARM_INS_LSLL, ARM_INS_LSR, ARM_INS_LSRL, ARM_INS_MCR, + ARM_INS_MCR2, ARM_INS_MCRR, ARM_INS_MCRR2, ARM_INS_MLA, ARM_INS_MLS, + ARM_INS_MOV, ARM_INS_MOVS, ARM_INS_MOVT, ARM_INS_MOVW, ARM_INS_MRC, + ARM_INS_MRC2, ARM_INS_MRRC, ARM_INS_MRRC2, ARM_INS_MRS, ARM_INS_MSR, + ARM_INS_MUL, ARM_INS_MVN, ARM_INS_NEG, ARM_INS_NOP, ARM_INS_ORN, + ARM_INS_ORR, ARM_INS_PAC, ARM_INS_PACBTI, ARM_INS_PACG, ARM_INS_PKHBT, + ARM_INS_PKHTB, ARM_INS_PLD, ARM_INS_PLDW, ARM_INS_PLI, ARM_INS_POP, + ARM_INS_PSSBB, ARM_INS_PUSH, ARM_INS_QADD, ARM_INS_QADD16, + ARM_INS_QADD8, ARM_INS_QASX, ARM_INS_QDADD, ARM_INS_QDSUB, ARM_INS_QSAX, + ARM_INS_QSUB, ARM_INS_QSUB16, ARM_INS_QSUB8, ARM_INS_RBIT, ARM_INS_REV, + ARM_INS_REV16, ARM_INS_REVSH, ARM_INS_RFEDA, ARM_INS_RFEDB, + ARM_INS_RFEIA, ARM_INS_RFEIB, ARM_INS_ROR, ARM_INS_RRX, ARM_INS_RSB, + ARM_INS_RSC, ARM_INS_SADD16, ARM_INS_SADD8, ARM_INS_SASX, ARM_INS_SB, + ARM_INS_SBC, ARM_INS_SBFX, ARM_INS_SDIV, ARM_INS_SEL, ARM_INS_SETEND, + ARM_INS_SETPAN, ARM_INS_SEV, ARM_INS_SEVL, ARM_INS_SG, ARM_INS_SHA1C, + ARM_INS_SHA1H, ARM_INS_SHA1M, ARM_INS_SHA1P, ARM_INS_SHA1SU0, + ARM_INS_SHA1SU1, ARM_INS_SHA256H, ARM_INS_SHA256H2, ARM_INS_SHA256SU0, + ARM_INS_SHA256SU1, ARM_INS_SHADD16, ARM_INS_SHADD8, ARM_INS_SHASX, + ARM_INS_SHSAX, ARM_INS_SHSUB16, ARM_INS_SHSUB8, ARM_INS_SMC, + ARM_INS_SMLABB, ARM_INS_SMLABT, ARM_INS_SMLAD, ARM_INS_SMLADX, + ARM_INS_SMLAL, ARM_INS_SMLALBB, ARM_INS_SMLALBT, ARM_INS_SMLALD, + ARM_INS_SMLALDX, ARM_INS_SMLALTB, ARM_INS_SMLALTT, ARM_INS_SMLATB, + ARM_INS_SMLATT, ARM_INS_SMLAWB, ARM_INS_SMLAWT, ARM_INS_SMLSD, + ARM_INS_SMLSDX, ARM_INS_SMLSLD, ARM_INS_SMLSLDX, ARM_INS_SMMLA, + ARM_INS_SMMLAR, ARM_INS_SMMLS, ARM_INS_SMMLSR, ARM_INS_SMMUL, + ARM_INS_SMMULR, ARM_INS_SMUAD, ARM_INS_SMUADX, ARM_INS_SMULBB, + ARM_INS_SMULBT, ARM_INS_SMULL, ARM_INS_SMULTB, ARM_INS_SMULTT, + ARM_INS_SMULWB, ARM_INS_SMULWT, ARM_INS_SMUSD, ARM_INS_SMUSDX, + ARM_INS_SQRSHR, ARM_INS_SQRSHRL, ARM_INS_SQSHL, ARM_INS_SQSHLL, + ARM_INS_SRSDA, ARM_INS_SRSDB, ARM_INS_SRSHR, ARM_INS_SRSHRL, + ARM_INS_SRSIA, ARM_INS_SRSIB, ARM_INS_SSAT, ARM_INS_SSAT16, + ARM_INS_SSAX, ARM_INS_SSBB, ARM_INS_SSUB16, ARM_INS_SSUB8, ARM_INS_STC, + ARM_INS_STC2, ARM_INS_STC2L, ARM_INS_STCL, ARM_INS_STL, ARM_INS_STLB, + ARM_INS_STLEX, ARM_INS_STLEXB, ARM_INS_STLEXD, ARM_INS_STLEXH, + ARM_INS_STLH, ARM_INS_STM, ARM_INS_STMDA, ARM_INS_STMDB, ARM_INS_STMIB, + ARM_INS_STR, ARM_INS_STRB, ARM_INS_STRBT, ARM_INS_STRD, ARM_INS_STREX, + ARM_INS_STREXB, ARM_INS_STREXD, ARM_INS_STREXH, ARM_INS_STRH, + ARM_INS_STRHT, ARM_INS_STRT, ARM_INS_SUB, ARM_INS_SUBS, ARM_INS_SUBW, + ARM_INS_SVC, ARM_INS_SWP, ARM_INS_SWPB, ARM_INS_SXTAB, ARM_INS_SXTAB16, + ARM_INS_SXTAH, ARM_INS_SXTB, ARM_INS_SXTB16, ARM_INS_SXTH, ARM_INS_TBB, + ARM_INS_TBH, ARM_INS_TEQ, ARM_INS_TRAP, ARM_INS_TSB, ARM_INS_TST, + ARM_INS_TT, ARM_INS_TTA, ARM_INS_TTAT, ARM_INS_TTT, ARM_INS_UADD16, + ARM_INS_UADD8, ARM_INS_UASX, ARM_INS_UBFX, ARM_INS_UDF, ARM_INS_UDIV, + ARM_INS_UHADD16, ARM_INS_UHADD8, ARM_INS_UHASX, ARM_INS_UHSAX, + ARM_INS_UHSUB16, ARM_INS_UHSUB8, ARM_INS_UMAAL, ARM_INS_UMLAL, + ARM_INS_UMULL, ARM_INS_UQADD16, ARM_INS_UQADD8, ARM_INS_UQASX, + ARM_INS_UQRSHL, ARM_INS_UQRSHLL, ARM_INS_UQSAX, ARM_INS_UQSHL, + ARM_INS_UQSHLL, ARM_INS_UQSUB16, ARM_INS_UQSUB8, ARM_INS_URSHR, + ARM_INS_URSHRL, ARM_INS_USAD8, ARM_INS_USADA8, ARM_INS_USAT, + ARM_INS_USAT16, ARM_INS_USAX, ARM_INS_USUB16, ARM_INS_USUB8, + ARM_INS_UXTAB, ARM_INS_UXTAB16, ARM_INS_UXTAH, ARM_INS_UXTB, + ARM_INS_UXTB16, ARM_INS_UXTH, ARM_INS_VABA, ARM_INS_VABAL, + ARM_INS_VABAV, ARM_INS_VABD, ARM_INS_VABDL, ARM_INS_VABS, ARM_INS_VACGE, + ARM_INS_VACGT, ARM_INS_VACLE, ARM_INS_VACLT, ARM_INS_VADC, + ARM_INS_VADCI, ARM_INS_VADD, ARM_INS_VADDHN, ARM_INS_VADDL, + ARM_INS_VADDLV, ARM_INS_VADDLVA, ARM_INS_VADDV, ARM_INS_VADDVA, + ARM_INS_VADDW, ARM_INS_VAND, ARM_INS_VBIC, ARM_INS_VBIF, ARM_INS_VBIT, + ARM_INS_VBRSR, ARM_INS_VBSL, ARM_INS_VCADD, ARM_INS_VCEQ, ARM_INS_VCGE, + ARM_INS_VCGT, ARM_INS_VCLE, ARM_INS_VCLS, ARM_INS_VCLT, ARM_INS_VCLZ, + ARM_INS_VCMLA, ARM_INS_VCMP, ARM_INS_VCMPE, ARM_INS_VCMUL, ARM_INS_VCNT, + ARM_INS_VCTP, ARM_INS_VCVT, ARM_INS_VCVTA, ARM_INS_VCVTB, ARM_INS_VCVTM, + ARM_INS_VCVTN, ARM_INS_VCVTP, ARM_INS_VCVTR, ARM_INS_VCVTT, + ARM_INS_VCX1, ARM_INS_VCX1A, ARM_INS_VCX2, ARM_INS_VCX2A, ARM_INS_VCX3, + ARM_INS_VCX3A, ARM_INS_VDDUP, ARM_INS_VDIV, ARM_INS_VDOT, ARM_INS_VDUP, + ARM_INS_VDWDUP, ARM_INS_VEOR, ARM_INS_VEXT, ARM_INS_VFMA, ARM_INS_VFMAB, + ARM_INS_VFMAL, ARM_INS_VFMAS, ARM_INS_VFMAT, ARM_INS_VFMS, + ARM_INS_VFMSL, ARM_INS_VFNMA, ARM_INS_VFNMS, ARM_INS_VHADD, + ARM_INS_VHCADD, ARM_INS_VHSUB, ARM_INS_VIDUP, ARM_INS_VINS, + ARM_INS_VIWDUP, ARM_INS_VJCVT, ARM_INS_VLD1, ARM_INS_VLD2, + ARM_INS_VLD20, ARM_INS_VLD21, ARM_INS_VLD3, ARM_INS_VLD4, ARM_INS_VLD40, + ARM_INS_VLD41, ARM_INS_VLD42, ARM_INS_VLD43, ARM_INS_VLDMDB, + ARM_INS_VLDMIA, ARM_INS_VLDR, ARM_INS_VLDRB, ARM_INS_VLDRD, + ARM_INS_VLDRH, ARM_INS_VLDRW, ARM_INS_VLLDM, ARM_INS_VLSTM, + ARM_INS_VMAX, ARM_INS_VMAXA, ARM_INS_VMAXAV, ARM_INS_VMAXNM, + ARM_INS_VMAXNMA, ARM_INS_VMAXNMAV, ARM_INS_VMAXNMV, ARM_INS_VMAXV, + ARM_INS_VMIN, ARM_INS_VMINA, ARM_INS_VMINAV, ARM_INS_VMINNM, + ARM_INS_VMINNMA, ARM_INS_VMINNMAV, ARM_INS_VMINNMV, ARM_INS_VMINV, + ARM_INS_VMLA, ARM_INS_VMLADAV, ARM_INS_VMLADAVA, ARM_INS_VMLADAVAX, + ARM_INS_VMLADAVX, ARM_INS_VMLAL, ARM_INS_VMLALDAV, ARM_INS_VMLALDAVA, + ARM_INS_VMLALDAVAX, ARM_INS_VMLALDAVX, ARM_INS_VMLALV, ARM_INS_VMLALVA, + ARM_INS_VMLAS, ARM_INS_VMLAV, ARM_INS_VMLAVA, ARM_INS_VMLS, + ARM_INS_VMLSDAV, ARM_INS_VMLSDAVA, ARM_INS_VMLSDAVAX, ARM_INS_VMLSDAVX, + ARM_INS_VMLSL, ARM_INS_VMLSLDAV, ARM_INS_VMLSLDAVA, ARM_INS_VMLSLDAVAX, + ARM_INS_VMLSLDAVX, ARM_INS_VMMLA, ARM_INS_VMOV, ARM_INS_VMOVL, + ARM_INS_VMOVLB, ARM_INS_VMOVLT, ARM_INS_VMOVN, ARM_INS_VMOVNB, + ARM_INS_VMOVNT, ARM_INS_VMOVX, ARM_INS_VMRS, ARM_INS_VMSR, ARM_INS_VMUL, + ARM_INS_VMULH, ARM_INS_VMULL, ARM_INS_VMULLB, ARM_INS_VMULLT, + ARM_INS_VMVN, ARM_INS_VNEG, ARM_INS_VNMLA, ARM_INS_VNMLS, ARM_INS_VNMUL, + ARM_INS_VORN, ARM_INS_VORR, ARM_INS_VPADAL, ARM_INS_VPADD, + ARM_INS_VPADDL, ARM_INS_VPMAX, ARM_INS_VPMIN, ARM_INS_VPNOT, + ARM_INS_VPOP, ARM_INS_VPSEL, ARM_INS_VPST, ARM_INS_VPT, ARM_INS_VPUSH, + ARM_INS_VQABS, ARM_INS_VQADD, ARM_INS_VQDMLADH, ARM_INS_VQDMLADHX, + ARM_INS_VQDMLAH, ARM_INS_VQDMLAL, ARM_INS_VQDMLASH, ARM_INS_VQDMLSDH, + ARM_INS_VQDMLSDHX, ARM_INS_VQDMLSL, ARM_INS_VQDMULH, ARM_INS_VQDMULL, + ARM_INS_VQDMULLB, ARM_INS_VQDMULLT, ARM_INS_VQMOVN, ARM_INS_VQMOVNB, + ARM_INS_VQMOVNT, ARM_INS_VQMOVUN, ARM_INS_VQMOVUNB, ARM_INS_VQMOVUNT, + ARM_INS_VQNEG, ARM_INS_VQRDMLADH, ARM_INS_VQRDMLADHX, ARM_INS_VQRDMLAH, + ARM_INS_VQRDMLASH, ARM_INS_VQRDMLSDH, ARM_INS_VQRDMLSDHX, + ARM_INS_VQRDMLSH, ARM_INS_VQRDMULH, ARM_INS_VQRSHL, ARM_INS_VQRSHRN, + ARM_INS_VQRSHRNB, ARM_INS_VQRSHRNT, ARM_INS_VQRSHRUN, ARM_INS_VQRSHRUNB, + ARM_INS_VQRSHRUNT, ARM_INS_VQSHL, ARM_INS_VQSHLU, ARM_INS_VQSHRN, + ARM_INS_VQSHRNB, ARM_INS_VQSHRNT, ARM_INS_VQSHRUN, ARM_INS_VQSHRUNB, + ARM_INS_VQSHRUNT, ARM_INS_VQSUB, ARM_INS_VRADDHN, ARM_INS_VRECPE, + ARM_INS_VRECPS, ARM_INS_VREV16, ARM_INS_VREV32, ARM_INS_VREV64, + ARM_INS_VRHADD, ARM_INS_VRINTA, ARM_INS_VRINTM, ARM_INS_VRINTN, + ARM_INS_VRINTP, ARM_INS_VRINTR, ARM_INS_VRINTX, ARM_INS_VRINTZ, + ARM_INS_VRMLALDAVH, ARM_INS_VRMLALDAVHA, ARM_INS_VRMLALDAVHAX, + ARM_INS_VRMLALDAVHX, ARM_INS_VRMLALVH, ARM_INS_VRMLALVHA, + ARM_INS_VRMLSLDAVH, ARM_INS_VRMLSLDAVHA, ARM_INS_VRMLSLDAVHAX, + ARM_INS_VRMLSLDAVHX, ARM_INS_VRMULH, ARM_INS_VRSHL, ARM_INS_VRSHR, + ARM_INS_VRSHRN, ARM_INS_VRSHRNB, ARM_INS_VRSHRNT, ARM_INS_VRSQRTE, + ARM_INS_VRSQRTS, ARM_INS_VRSRA, ARM_INS_VRSUBHN, ARM_INS_VSBC, + ARM_INS_VSBCI, ARM_INS_VSCCLRM, ARM_INS_VSDOT, ARM_INS_VSELEQ, + ARM_INS_VSELGE, ARM_INS_VSELGT, ARM_INS_VSELVS, ARM_INS_VSHL, + ARM_INS_VSHLC, ARM_INS_VSHLL, ARM_INS_VSHLLB, ARM_INS_VSHLLT, + ARM_INS_VSHR, ARM_INS_VSHRN, ARM_INS_VSHRNB, ARM_INS_VSHRNT, + ARM_INS_VSLI, ARM_INS_VSMMLA, ARM_INS_VSQRT, ARM_INS_VSRA, ARM_INS_VSRI, + ARM_INS_VST1, ARM_INS_VST2, ARM_INS_VST20, ARM_INS_VST21, ARM_INS_VST3, + ARM_INS_VST4, ARM_INS_VST40, ARM_INS_VST41, ARM_INS_VST42, + ARM_INS_VST43, ARM_INS_VSTMDB, ARM_INS_VSTMIA, ARM_INS_VSTR, + ARM_INS_VSTRB, ARM_INS_VSTRD, ARM_INS_VSTRH, ARM_INS_VSTRW, + ARM_INS_VSUB, ARM_INS_VSUBHN, ARM_INS_VSUBL, ARM_INS_VSUBW, + ARM_INS_VSUDOT, ARM_INS_VSWP, ARM_INS_VTBL, ARM_INS_VTBX, ARM_INS_VTRN, + ARM_INS_VTST, ARM_INS_VUDOT, ARM_INS_VUMMLA, ARM_INS_VUSDOT, + ARM_INS_VUSMMLA, ARM_INS_VUZP, ARM_INS_VZIP, ARM_INS_WFE, ARM_INS_WFI, + ARM_INS_WLS, ARM_INS_WLSTP, ARM_INS_YIELD, diff --git a/thirdparty/capstone/arch/ARM/ARMInstPrinter.c b/thirdparty/capstone/arch/ARM/ARMInstPrinter.c new file mode 100644 index 0000000..677c27a --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMInstPrinter.c @@ -0,0 +1,1979 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + +//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This class prints an ARM MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +#include +#include +#include +#include + +#include "../../Mapping.h" +#include "../../MCInst.h" +#include "../../MCInstPrinter.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" +#include "../../utils.h" +#include "ARMAddressingModes.h" +#include "ARMBaseInfo.h" +#include "ARMDisassemblerExtension.h" +#include "ARMInstPrinter.h" +#include "ARMLinkage.h" +#include "ARMMapping.h" + +#define GET_BANKEDREG_IMPL +#include "ARMGenSystemRegister.inc" + +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b + +#define DEBUG_TYPE "asm-printer" + +// Static function declarations. These are functions which have the same identifiers +// over all architectures. Therefor they need to be static. +#ifndef CAPSTONE_DIET +static void printCustomAliasOperand(MCInst *MI, uint64_t Address, + unsigned OpIdx, unsigned PrintMethodIdx, + SStream *O); +#endif +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printRegName(SStream *OS, unsigned RegNo); +static void printInst(MCInst *MI, SStream *O, void *info); + +#define PRINT_ALIAS_INSTR +#include "ARMGenAsmWriter.inc" + +/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. +/// +/// getSORegOffset returns an integer from 0-31, representing '32' as 0. +unsigned translateShiftImm(unsigned imm) +{ + // lsr #32 and asr #32 exist, but should be encoded as a 0. + + if (imm == 0) + return 32; + return imm; +} + +/// Prints the shift value with an immediate value. +static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, + unsigned ShImm, bool UseMarkup) +{ + add_cs_detail(MI, ARM_OP_GROUP_RegImmShift, ShOpc, ShImm); + if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm)) + return; + SStream_concat0(O, ", "); + + SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); + + if (ShOpc != ARM_AM_rrx) { + SStream_concat0(O, " "); + if (getUseMarkup()) + SStream_concat0(O, ""); + } +} + +static void printRegName(SStream *OS, unsigned RegNo) +{ + SStream_concat(OS, "%s%s", markup("")); +} + +static void printInst(MCInst *MI, SStream *O, void *info) +{ + bool isAlias = false; + bool useAliasDetails = map_use_alias_details(MI); + map_set_fill_detail_ops(MI, useAliasDetails); + unsigned Opcode = MCInst_getOpcode(MI); + uint64_t Address = MI->address; + + switch (Opcode) { + // Check for MOVs and print canonical forms, instead. + case ARM_MOVsr: { + isAlias = true; + MCInst_setIsAlias(MI, isAlias); + // FIXME: Thumb variants? + MCOperand *MO3 = MCInst_getOperand(MI, (3)); + + SStream_concat1(O, ' '); + SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp( + MCOperand_getImm(MO3)))); + printSBitModifierOperand(MI, 6, O); + printPredicateOperand(MI, 4, O); + + SStream_concat0(O, " "); + + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + + if (useAliasDetails) + return; + else + goto add_real_detail; + } + + case ARM_MOVsi: { + isAlias = true; + MCInst_setIsAlias(MI, isAlias); + // FIXME: Thumb variants? + MCOperand *MO2 = MCInst_getOperand(MI, (2)); + + SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp( + MCOperand_getImm(MO2)))); + printSBitModifierOperand(MI, 5, O); + printPredicateOperand(MI, 3, O); + + SStream_concat0(O, " "); + + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + + if (ARM_AM_getSORegShOp(MCOperand_getImm(MO2)) == ARM_AM_rrx) { + if (useAliasDetails) + return; + else + goto add_real_detail; + } + + SStream_concat(O, "%s%s%s%d", ", ", markup("")); + if (useAliasDetails) + return; + else + goto add_real_detail; + } + + // A8.6.123 PUSH + case ARM_STMDB_UPD: + case ARM_t2STMDB_UPD: + if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP && + MCInst_getNumOperands(MI) > 5) { + isAlias = true; + MCInst_setIsAlias(MI, isAlias); + // Should only print PUSH if there are at least two registers in the + // list. + SStream_concat0(O, "push"); + printPredicateOperand(MI, 2, O); + if (Opcode == ARM_t2STMDB_UPD) + SStream_concat0(O, ".w"); + SStream_concat0(O, " "); + + printRegisterList(MI, 4, O); + if (useAliasDetails) + return; + else + goto add_real_detail; + } else + break; + + case ARM_STR_PRE_IMM: + if (MCOperand_getReg(MCInst_getOperand(MI, (2))) == ARM_SP && + MCOperand_getImm(MCInst_getOperand(MI, (3))) == -4) { + isAlias = true; + MCInst_setIsAlias(MI, isAlias); + SStream_concat1(O, ' '); + SStream_concat0(O, "push"); + printPredicateOperand(MI, 4, O); + SStream_concat0(O, " {"); + printOperand(MI, 1, O); + SStream_concat0(O, "}"); + if (useAliasDetails) + return; + else + goto add_real_detail; + } else + break; + + // A8.6.122 POP + case ARM_LDMIA_UPD: + case ARM_t2LDMIA_UPD: + if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP && + MCInst_getNumOperands(MI) > 5) { + isAlias = true; + MCInst_setIsAlias(MI, isAlias); + // Should only print POP if there are at least two registers in the + // list. + SStream_concat0(O, "pop"); + printPredicateOperand(MI, 2, O); + if (Opcode == ARM_t2LDMIA_UPD) + SStream_concat0(O, ".w"); + SStream_concat0(O, " "); + + printRegisterList(MI, 4, O); + if (useAliasDetails) + return; + else + goto add_real_detail; + } else + break; + + case ARM_LDR_POST_IMM: + if ((MCOperand_getReg(MCInst_getOperand(MI, (2))) == ARM_SP) && + ((ARM_AM_getAM2Offset(MCOperand_getImm( + MCInst_getOperand(MI, (4)))) == 4))) { + isAlias = true; + MCInst_setIsAlias(MI, isAlias); + SStream_concat0(O, "pop"); + printPredicateOperand(MI, 5, O); + SStream_concat0(O, " {"); + printOperand(MI, 0, O); + SStream_concat0(O, "}"); + if (useAliasDetails) + return; + else + goto add_real_detail; + } else + break; + case ARM_t2LDR_POST: + if ((MCOperand_getReg(MCInst_getOperand(MI, (2))) == ARM_SP) && + (Opcode == ARM_t2LDR_POST && + (MCOperand_getImm(MCInst_getOperand(MI, (3))) == 4))) { + isAlias = true; + MCInst_setIsAlias(MI, isAlias); + SStream_concat0(O, "pop"); + printPredicateOperand(MI, 4, O); + SStream_concat0(O, " {"); + printOperand(MI, 0, O); + SStream_concat0(O, "}"); + if (useAliasDetails) + return; + else + goto add_real_detail; + } else + break; + + // A8.6.355 VPUSH + case ARM_VSTMSDB_UPD: + case ARM_VSTMDDB_UPD: + if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP) { + isAlias = true; + MCInst_setIsAlias(MI, isAlias); + SStream_concat0(O, "vpush"); + printPredicateOperand(MI, 2, O); + SStream_concat0(O, " "); + + printRegisterList(MI, 4, O); + if (useAliasDetails) + return; + else + goto add_real_detail; + } else + break; + + // A8.6.354 VPOP + case ARM_VLDMSIA_UPD: + case ARM_VLDMDIA_UPD: + if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP) { + isAlias = true; + MCInst_setIsAlias(MI, isAlias); + SStream_concat1(O, ' '); + SStream_concat0(O, "vpop"); + printPredicateOperand(MI, 2, O); + SStream_concat0(O, " "); + + printRegisterList(MI, 4, O); + if (useAliasDetails) + return; + else + goto add_real_detail; + } else + break; + + case ARM_tLDMIA: { + isAlias = true; + MCInst_setIsAlias(MI, isAlias); + bool Writeback = true; + unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, (0))); + for (unsigned i = 3; i < MCInst_getNumOperands(MI); ++i) { + if (MCOperand_getReg(MCInst_getOperand(MI, (i))) == + BaseReg) + Writeback = false; + } + + SStream_concat0(O, "ldm"); + + printPredicateOperand(MI, 1, O); + SStream_concat0(O, " "); + + printOperand(MI, 0, O); + if (Writeback) { + SStream_concat0(O, "!"); + } + SStream_concat0(O, ", "); + printRegisterList(MI, 3, O); + if (useAliasDetails) + return; + else + goto add_real_detail; + } + + // Combine 2 GPRs from disassember into a GPRPair to match with instr def. + // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, + // a single GPRPair reg operand is used in the .td file to replace the two + // GPRs. However, when decoding them, the two GRPs cannot be automatically + // expressed as a GPRPair, so we have to manually merge them. + // FIXME: We would really like to be able to tablegen'erate this. + case ARM_LDREXD: + case ARM_STREXD: + case ARM_LDAEXD: + case ARM_STLEXD: { + const MCRegisterClass *MRC = + MCRegisterInfo_getRegClass(MI->MRI, ARM_GPRRegClassID); + bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD; + unsigned Reg = MCOperand_getReg( + MCInst_getOperand(MI, isStore ? 1 : 0)); + + if (MCRegisterClass_contains(MRC, Reg)) { + MCInst NewMI; + + MCInst_Init(&NewMI); + MCInst_setOpcode(&NewMI, Opcode); + + if (isStore) + MCInst_addOperand2(&NewMI, + MCInst_getOperand(MI, 0)); + + MCOperand_CreateReg0( + &NewMI, + MCRegisterInfo_getMatchingSuperReg( + MI->MRI, Reg, ARM_gsub_0, + MCRegisterInfo_getRegClass( + MI->MRI, ARM_GPRPairRegClassID))); + + // Copy the rest operands into NewMI. + for (unsigned i = isStore ? 3 : 2; + i < MCInst_getNumOperands(MI); ++i) + MCInst_addOperand2(&NewMI, + MCInst_getOperand(MI, i)); + + printInstruction(&NewMI, Address, O); + return; + } + break; + } + case ARM_TSB: + case ARM_t2TSB: + isAlias = true; + MCInst_setIsAlias(MI, isAlias); + + SStream_concat0(O, " tsb csync"); + if (useAliasDetails) + return; + else + goto add_real_detail; + case ARM_t2DSB: + isAlias = true; + MCInst_setIsAlias(MI, isAlias); + + switch (MCOperand_getImm(MCInst_getOperand(MI, (0)))) { + default: + if (!printAliasInstr(MI, Address, O)) + printInstruction(MI, Address, O); + break; + case 0: + SStream_concat0(O, " ssbb"); + break; + case 4: + SStream_concat0(O, " pssbb"); + break; + }; + if (useAliasDetails) + return; + else + goto add_real_detail; + } + + if (!isAlias) + isAlias |= printAliasInstr(MI, Address, O); + +add_real_detail: + MCInst_setIsAlias(MI, isAlias); + if (!isAlias || !useAliasDetails) { + map_set_fill_detail_ops(MI, !(isAlias && useAliasDetails)); + if (isAlias) + SStream_Close(O); + printInstruction(MI, Address, O); + if (isAlias) + SStream_Open(O); + } +} + +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_Operand, OpNo); + MCOperand *Op = MCInst_getOperand(MI, (OpNo)); + if (MCOperand_isReg(Op)) { + unsigned Reg = MCOperand_getReg(Op); + printRegName(O, Reg); + } else if (MCOperand_isImm(Op)) { + SStream_concat(O, "%s", markup("")); + } else { + assert(0 && "Expressions are not supported."); + } +} + +void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, (OpNum)); + if (!MCOperand_isImm(Op) || MI->csh->PrintBranchImmNotAsAddress || + getUseMarkup()) { + printOperand(MI, OpNum, O); + return; + } + int64_t Imm = MCOperand_getImm(Op); + // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it + // is 4 bytes. + uint64_t Offset = ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) ? 4 : + 8; + + // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code + // which is 32-bit aligned. The target address for the case is calculated as + // targetAddress = Align(PC,4) + imm32; + // where + // Align(x, y) = y * (x DIV y); + if (MCInst_getOpcode(MI) == ARM_tBLXi) + Address &= ~0x3; + + uint64_t Target = Address + Imm + Offset; + + Target &= 0xffffffff; + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, Target); + printUInt64(O, Target); +} + +void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_ThumbLdrLabelOperand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + if (MCOperand_isExpr(MO1)) { + // MO1.getExpr()->print(O, &MAI); + return; + } + + SStream_concat(O, "%s", markup("")); + } else { + SStream_concat(O, "%s", markup("")); + } + SStream_concat(O, "%s", "]"); + SStream_concat0(O, markup(">")); +} + +// so_reg is a 4-operand unit corresponding to register forms of the A5.1 +// "Addressing Mode 1 - Data-processing operands" forms. This includes: +// REG 0 0 - e.g. R5 +// REG REG 0,SH_OPC - e.g. R5, ROR R3 +// REG 0 IMM,SH_OPC - e.g. R5, LSL #3 +void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_SORegRegOperand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); + MCOperand *MO3 = MCInst_getOperand(MI, (OpNum + 2)); + + printRegName(O, MCOperand_getReg(MO1)); + + // Print the shift opc. + ARM_AM_ShiftOpc ShOpc = ARM_AM_getSORegShOp(MCOperand_getImm(MO3)); + SStream_concat(O, "%s", ", "); + SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); + if (ShOpc == ARM_AM_rrx) + return; + + SStream_concat0(O, " "); + + printRegName(O, MCOperand_getReg(MO2)); +} + +void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_SORegImmOperand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); + + printRegName(O, MCOperand_getReg(MO1)); + + // Print the shift opc. + printRegImmShift(MI, O, ARM_AM_getSORegShOp(MCOperand_getImm(MO2)), + ARM_AM_getSORegOffset(MCOperand_getImm(MO2)), + getUseMarkup()); +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #2 +//===--------------------------------------------------------------------===// + +void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, (Op)); + MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1)); + MCOperand *MO3 = MCInst_getOperand(MI, (Op + 2)); + + SStream_concat(O, "%s", markup("")); + } + SStream_concat(O, "%s", "]"); + SStream_concat0(O, markup(">")); + return; + } + + SStream_concat0(O, ", "); + SStream_concat0(O, ARM_AM_getAddrOpcStr( + ARM_AM_getAM2Op(MCOperand_getImm(MO3)))); + printRegName(O, MCOperand_getReg(MO2)); + + printRegImmShift(MI, O, ARM_AM_getAM2ShiftOpc(MCOperand_getImm(MO3)), + ARM_AM_getAM2Offset(MCOperand_getImm(MO3)), + getUseMarkup()); + SStream_concat(O, "%s", "]"); + SStream_concat0(O, markup(">")); +} + +void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_AddrModeTBB, Op); + MCOperand *MO1 = MCInst_getOperand(MI, (Op)); + MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1)); + SStream_concat(O, "%s", markup("")); +} + +void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_AddrModeTBH, Op); + MCOperand *MO1 = MCInst_getOperand(MI, (Op)); + MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1)); + SStream_concat(O, "%s", markup(""), "]"); + SStream_concat0(O, markup(">")); +} + +void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_AddrMode2Operand, Op); + MCOperand *MO1 = MCInst_getOperand(MI, (Op)); + + if (!MCOperand_isReg( + MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, Op, O); + return; + } + + printAM2PreOrOffsetIndexOp(MI, Op, O); +} + +void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_AddrMode2OffsetOperand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); + + if (!MCOperand_getReg(MO1)) { + unsigned ImmOffs = ARM_AM_getAM2Offset(MCOperand_getImm(MO2)); + SStream_concat(O, "%s", markup("")); + return; + } + + SStream_concat0(O, ARM_AM_getAddrOpcStr( + ARM_AM_getAM2Op(MCOperand_getImm(MO2)))); + printRegName(O, MCOperand_getReg(MO1)); + + printRegImmShift(MI, O, ARM_AM_getAM2ShiftOpc(MCOperand_getImm(MO2)), + ARM_AM_getAM2Offset(MCOperand_getImm(MO2)), + getUseMarkup()); +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #3 +//===--------------------------------------------------------------------===// + +void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, + bool AlwaysPrintImm0) +{ + MCOperand *MO1 = MCInst_getOperand(MI, (Op)); + MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1)); + MCOperand *MO3 = MCInst_getOperand(MI, (Op + 2)); + + SStream_concat(O, "%s", markup("")); + return; + } + + // If the op is sub we have to print the immediate even if it is 0 + unsigned ImmOffs = ARM_AM_getAM3Offset(MCOperand_getImm(MO3)); + ARM_AM_AddrOpc op = ARM_AM_getAM3Op(MCOperand_getImm(MO3)); + + if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM_sub)) { + SStream_concat(O, "%s%s%s%s", ", ", markup("")); + } + SStream_concat1(O, ']'); + SStream_concat0(O, markup(">")); +} + +#define DEFINE_printAddrMode3Operand(AlwaysPrintImm0) \ + void CONCAT(printAddrMode3Operand, \ + AlwaysPrintImm0)(MCInst * MI, unsigned Op, SStream *O) \ + { \ + add_cs_detail(MI, \ + CONCAT(ARM_OP_GROUP_AddrMode3Operand, \ + AlwaysPrintImm0), \ + Op, AlwaysPrintImm0); \ + MCOperand *MO1 = MCInst_getOperand(MI, (Op)); \ + if (!MCOperand_isReg(MO1)) { \ + printOperand(MI, Op, O); \ + return; \ + } \ +\ + printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0); \ + } +DEFINE_printAddrMode3Operand(false) DEFINE_printAddrMode3Operand(true) + + void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_AddrMode3OffsetOperand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); + + if (MCOperand_getReg(MO1)) { + SStream_concat0(O, ARM_AM_getAddrOpcStr(ARM_AM_getAM3Op( + MCOperand_getImm(MO2)))); + printRegName(O, MCOperand_getReg(MO1)); + return; + } + + unsigned ImmOffs = ARM_AM_getAM3Offset(MCOperand_getImm(MO2)); + SStream_concat(O, "%s", markup("")); +} + +void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_PostIdxImm8Operand, OpNum); + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); + unsigned Imm = MCOperand_getImm(MO); + SStream_concat(O, "%s", markup("")); +} + +void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_PostIdxRegOperand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); + + SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-")); + printRegName(O, MCOperand_getReg(MO1)); +} + +void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_PostIdxImm8s4Operand, OpNum); + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); + unsigned Imm = MCOperand_getImm(MO); + SStream_concat(O, "%s", markup("")); +} + +#define DEFINE_printMveAddrModeRQOperand(shift) \ + void CONCAT(printMveAddrModeRQOperand, \ + shift)(MCInst * MI, unsigned OpNum, SStream *O) \ + { \ + add_cs_detail( \ + MI, CONCAT(ARM_OP_GROUP_MveAddrModeRQOperand, shift), \ + OpNum, shift); \ + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); \ + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); \ +\ + SStream_concat(O, "%s", markup(" 0) \ + printRegImmShift(MI, O, ARM_AM_uxtw, shift, \ + getUseMarkup()); \ +\ + SStream_concat(O, "%s", "]"); \ + SStream_concat0(O, markup(">")); \ + } +DEFINE_printMveAddrModeRQOperand(0) DEFINE_printMveAddrModeRQOperand(3) + DEFINE_printMveAddrModeRQOperand(1) DEFINE_printMveAddrModeRQOperand(2) + + void printLdStmModeOperand(MCInst *MI, unsigned OpNum, + SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_LdStmModeOperand, OpNum); + ARM_AM_SubMode Mode = ARM_AM_getAM4SubMode( + MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, ARM_AM_getAMSubModeStr(Mode)); +} + +#define DEFINE_printAddrMode5Operand(AlwaysPrintImm0) \ + void CONCAT(printAddrMode5Operand, \ + AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O) \ + { \ + add_cs_detail(MI, \ + CONCAT(ARM_OP_GROUP_AddrMode5Operand, \ + AlwaysPrintImm0), \ + OpNum, AlwaysPrintImm0); \ + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); \ + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); \ +\ + SStream_concat(O, "%s", markup("")); \ + } \ + SStream_concat(O, "%s", "]"); \ + SStream_concat0(O, markup(">")); \ + } +DEFINE_printAddrMode5Operand(false) DEFINE_printAddrMode5Operand(true) + +#define DEFINE_printAddrMode5FP16Operand(AlwaysPrintImm0) \ + void CONCAT(printAddrMode5FP16Operand, \ + AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O) \ + { \ + add_cs_detail(MI, \ + CONCAT(ARM_OP_GROUP_AddrMode5FP16Operand, \ + AlwaysPrintImm0), \ + OpNum, AlwaysPrintImm0); \ + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); \ + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); \ +\ + if (!MCOperand_isReg(MO1)) { \ + printOperand(MI, OpNum, O); \ + return; \ + } \ +\ + SStream_concat(O, "%s", markup("")); \ + } \ + SStream_concat(O, "%s", "]"); \ + SStream_concat0(O, markup(">")); \ + } + DEFINE_printAddrMode5FP16Operand(false) + + void printAddrMode6Operand(MCInst *MI, unsigned OpNum, + SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_AddrMode6Operand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); + + SStream_concat(O, "%s", markup("")); +} + +void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_AddrMode7Operand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + SStream_concat(O, "%s", markup("")); +} + +void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_AddrMode6OffsetOperand, OpNum); + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); + if (MCOperand_getReg(MO) == 0) + SStream_concat0(O, "!"); + else { + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MO)); + } +} + +void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_BitfieldInvMaskImmOperand, OpNum); + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); + uint32_t v = ~MCOperand_getImm(MO); + int32_t lsb = CountTrailingZeros_32(v); + int32_t width = (32 - countLeadingZeros(v)) - lsb; + + SStream_concat(O, "%s", markup(""), ", ", markup("")); +} + +void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_MemBOption, OpNum); + unsigned val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + SStream_concat0(O, ARM_MB_MemBOptToString( + val, ARM_getFeatureBits(MI->csh->mode, + ARM_HasV8Ops))); +} + +void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_InstSyncBOption, OpNum); + unsigned val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val)); +} + +void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_TraceSyncBOption, OpNum); + unsigned val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + SStream_concat0(O, ARM_TSB_TraceSyncBOptToString(val)); +} + +void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_ShiftImmOperand, OpNum); + unsigned ShiftOp = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + bool isASR = (ShiftOp & (1 << 5)) != 0; + unsigned Amt = ShiftOp & 0x1f; + if (isASR) { + SStream_concat(O, "%s%s%s", ", asr ", markup("")); + } else if (Amt) { + SStream_concat(O, "%s%s%s", ", lsl ", markup("")); + } +} + +void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_PKHLSLShiftImm, OpNum); + unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + if (Imm == 0) + return; + + SStream_concat(O, "%s%s%s", ", lsl ", markup("")); +} + +void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_PKHASRShiftImm, OpNum); + unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + // A shift amount of 32 is encoded as 0. + if (Imm == 0) + Imm = 32; + + SStream_concat(O, "%s%s%s", ", asr ", markup("")); +} + +void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_RegisterList, OpNum); + if (MCInst_getOpcode(MI) != ARM_t2CLRM) { + } + + SStream_concat0(O, "{"); + for (unsigned i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) { + if (i != OpNum) + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (i)))); + } + SStream_concat0(O, "}"); +} + +void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_GPRPairOperand, OpNum); + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); + printRegName(O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0)); + SStream_concat0(O, ", "); + printRegName(O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1)); +} + +void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_SetendOperand, OpNum); + MCOperand *Op = MCInst_getOperand(MI, (OpNum)); + if (MCOperand_getImm(Op)) + SStream_concat0(O, "be"); + else + SStream_concat0(O, "le"); +} + +void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_CPSIMod, OpNum); + MCOperand *Op = MCInst_getOperand(MI, (OpNum)); + SStream_concat0(O, ARM_PROC_IModToString(MCOperand_getImm(Op))); +} + +void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_CPSIFlag, OpNum); + MCOperand *Op = MCInst_getOperand(MI, (OpNum)); + unsigned IFlags = MCOperand_getImm(Op); + for (int i = 2; i >= 0; --i) + if (IFlags & (1 << i)) + SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i)); + + if (IFlags == 0) + SStream_concat0(O, "none"); +} + +void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_MSRMaskOperand, OpNum); + MCOperand *Op = MCInst_getOperand(MI, (OpNum)); + + if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) { + unsigned SYSm = MCOperand_getImm(Op) & 0xFFF; // 12-bit SYSm + unsigned Opcode = MCInst_getOpcode(MI); + + // For writes, handle extended mask bits if the DSP extension is + // present. + if (Opcode == ARM_t2MSR_M && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)) { + const ARMSysReg_MClassSysReg *TheReg = + ARMSysReg_lookupMClassSysRegBy12bitSYSmValue( + SYSm); + if (TheReg && MClassSysReg_isInRequiredFeatures( + TheReg, ARM_FeatureDSP)) { + SStream_concat0(O, TheReg->Name); + return; + } + } + + // Handle the basic 8-bit mask. + SYSm &= 0xff; + if (Opcode == ARM_t2MSR_M && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)) { + // ARMv7-M deprecates using MSR APSR without a _ qualifier as + // an alias for MSR APSR_nzcvq. + const ARMSysReg_MClassSysReg *TheReg = + ARMSysReg_lookupMClassSysRegAPSRNonDeprecated( + SYSm); + if (TheReg) { + SStream_concat0(O, TheReg->Name); + return; + } + } + + const ARMSysReg_MClassSysReg *TheReg = + ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(SYSm); + if (TheReg) { + SStream_concat0(O, TheReg->Name); + return; + } + + printUInt32(O, SYSm); + + return; + } + + // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as + // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. + unsigned SpecRegRBit = MCOperand_getImm(Op) >> 4; + unsigned Mask = MCOperand_getImm(Op) & 0xf; + + if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { + SStream_concat0(O, "apsr_"); + switch (Mask) { + default: + assert(0 && "Unexpected mask value!"); + case 4: + SStream_concat0(O, "g"); + return; + case 8: + SStream_concat0(O, "nzcvq"); + return; + case 12: + SStream_concat0(O, "nzcvqg"); + return; + } + } + + if (SpecRegRBit) + SStream_concat0(O, "spsr"); + else + SStream_concat0(O, "cpsr"); + + if (Mask) { + SStream_concat0(O, "_"); + + if (Mask & 8) + SStream_concat0(O, "f"); + + if (Mask & 4) + SStream_concat0(O, "s"); + + if (Mask & 2) + SStream_concat0(O, "x"); + + if (Mask & 1) + SStream_concat0(O, "c"); + } +} + +void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_BankedRegOperand, OpNum); + uint32_t Banked = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + const ARMBankedReg_BankedReg *TheReg = + ARMBankedReg_lookupBankedRegByEncoding(Banked); + + const char *Name = TheReg->Name; + + // uint32_t isSPSR = (Banked & 0x20) >> 5; + // if (isSPSR) + // Name.replace(0, 4, "SPSR"); // convert 'spsr_' to 'SPSR_' + SStream_concat0(O, Name); +} + +static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_PredicateOperand, OpNum); + ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm( + MCInst_getOperand(MI, (OpNum))); + // Handle the undefined 15 CC value here for printing so we don't abort(). + if ((unsigned)CC == 15) + SStream_concat0(O, ""); + else if (CC != ARMCC_AL) + SStream_concat0(O, ARMCondCodeToString(CC)); +} + +void printMandatoryRestrictedPredicateOperand(MCInst *MI, unsigned OpNum, + SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_MandatoryRestrictedPredicateOperand, + OpNum); + if ((ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, (OpNum))) == + ARMCC_HS) + SStream_concat0(O, "cs"); + else + printMandatoryPredicateOperand(MI, OpNum, O); +} + +void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_MandatoryPredicateOperand, OpNum); + ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm( + MCInst_getOperand(MI, (OpNum))); + SStream_concat0(O, ARMCondCodeToString(CC)); +} + +void printMandatoryInvertedPredicateOperand(MCInst *MI, unsigned OpNum, + SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_MandatoryInvertedPredicateOperand, + OpNum); + ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm( + MCInst_getOperand(MI, (OpNum))); + SStream_concat0(O, ARMCondCodeToString(ARMCC_getOppositeCondition(CC))); +} + +void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_SBitModifierOperand, OpNum); + if (MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))) { + SStream_concat0(O, "s"); + } +} + +void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_NoHashImmediate, OpNum); + printInt64(O, MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); +} + +void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_PImmediate, OpNum); + SStream_concat(O, "%s%d", "p", + MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); +} + +void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_CImmediate, OpNum); + SStream_concat(O, "%s%d", "c", + MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); +} + +void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_CoprocOptionImm, OpNum); + SStream_concat(O, "%s", "{"); + printInt64(O, MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, "}"); +} + +void printPCLabel(MCInst *MI, unsigned OpNum, SStream *O) +{ + // add_cs_detail(MI, ARM_OP_GROUP_PCLabel, OpNum); + assert(0 && "Unhandled PC-relative pseudo-instruction!"); +} + +#define DEFINE_printAdrLabelOperand(scale) \ + void CONCAT(printAdrLabelOperand, scale)(MCInst * MI, unsigned OpNum, \ + SStream *O) \ + { \ + add_cs_detail(MI, CONCAT(ARM_OP_GROUP_AdrLabelOperand, scale), \ + OpNum, scale); \ + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); \ +\ + if (MCOperand_isExpr(MO)) { \ + return; \ + } \ +\ + int32_t OffImm = (uint32_t)MCOperand_getImm(MO) << scale; \ +\ + SStream_concat0(O, markup("")); \ + } +DEFINE_printAdrLabelOperand(0) DEFINE_printAdrLabelOperand(2) + + void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_ThumbS4ImmOperand, OpNum); + SStream_concat(O, "%s", markup("")); +} + +void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_ThumbSRImm, OpNum); + unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + SStream_concat(O, "%s", markup("")); +} + +void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_ThumbITMask, OpNum); + // (3 - the number of trailing zeros) is the number of then / else. + unsigned Mask = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + unsigned NumTZ = CountTrailingZeros_32(Mask); + + for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { + if ((Mask >> Pos) & 1) + SStream_concat0(O, "e"); + + else + SStream_concat0(O, "t"); + } +} + +void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_ThumbAddrModeRROperand, Op); + MCOperand *MO1 = MCInst_getOperand(MI, (Op)); + MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1)); + + if (!MCOperand_isReg( + MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, Op, O); + return; + } + + SStream_concat(O, "%s", markup("")); +} + +void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O, + unsigned Scale) +{ + MCOperand *MO1 = MCInst_getOperand(MI, (Op)); + MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1)); + + if (!MCOperand_isReg( + MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, Op, O); + return; + } + + SStream_concat(O, "%s", markup("")); + } + SStream_concat(O, "%s", "]"); + SStream_concat0(O, markup(">")); +} + +void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_ThumbAddrModeImm5S1Operand, Op); + printThumbAddrModeImm5SOperand(MI, Op, O, 1); +} + +void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_ThumbAddrModeImm5S2Operand, Op); + printThumbAddrModeImm5SOperand(MI, Op, O, 2); +} + +void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_ThumbAddrModeImm5S4Operand, Op); + printThumbAddrModeImm5SOperand(MI, Op, O, 4); +} + +void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_ThumbAddrModeSPOperand, Op); + printThumbAddrModeImm5SOperand(MI, Op, O, 4); +} + +// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 +// register with shift forms. +// REG 0 0 - e.g. R5 +// REG IMM, SH_OPC - e.g. R5, LSL #3 +void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_T2SOOperand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); + + unsigned Reg = MCOperand_getReg(MO1); + printRegName(O, Reg); + + // Print the shift opc. + + printRegImmShift(MI, O, ARM_AM_getSORegShOp(MCOperand_getImm(MO2)), + ARM_AM_getSORegOffset(MCOperand_getImm(MO2)), + getUseMarkup()); +} + +#define DEFINE_printAddrModeImm12Operand(AlwaysPrintImm0) \ + void CONCAT(printAddrModeImm12Operand, \ + AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O) \ + { \ + add_cs_detail(MI, \ + CONCAT(ARM_OP_GROUP_AddrModeImm12Operand, \ + AlwaysPrintImm0), \ + OpNum, AlwaysPrintImm0); \ + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); \ + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); \ +\ + if (!MCOperand_isReg(MO1)) { \ + printOperand(MI, OpNum, O); \ + return; \ + } \ +\ + SStream_concat(O, "%s", markup("")); \ + } else if (AlwaysPrintImm0 || OffImm > 0) { \ + SStream_concat(O, "%s%s", ", ", markup("")); \ + } \ + SStream_concat(O, "%s", "]"); \ + SStream_concat0(O, markup(">")); \ + } +DEFINE_printAddrModeImm12Operand(false) DEFINE_printAddrModeImm12Operand(true) + +#define DEFINE_printT2AddrModeImm8Operand(AlwaysPrintImm0) \ + void CONCAT(printT2AddrModeImm8Operand, \ + AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O) \ + { \ + add_cs_detail(MI, \ + CONCAT(ARM_OP_GROUP_T2AddrModeImm8Operand, \ + AlwaysPrintImm0), \ + OpNum, AlwaysPrintImm0); \ + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); \ + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); \ +\ + SStream_concat(O, "%s", markup("")); \ + } else if (AlwaysPrintImm0 || OffImm > 0) { \ + SStream_concat(O, "%s%s", ", ", markup("")); \ + } \ + SStream_concat(O, "%s", "]"); \ + SStream_concat0(O, markup(">")); \ + } + DEFINE_printT2AddrModeImm8Operand(true) + DEFINE_printT2AddrModeImm8Operand(false) + +#define DEFINE_printT2AddrModeImm8s4Operand(AlwaysPrintImm0) \ + void CONCAT(printT2AddrModeImm8s4Operand, \ + AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O) \ + { \ + add_cs_detail(MI, \ + CONCAT(ARM_OP_GROUP_T2AddrModeImm8s4Operand, \ + AlwaysPrintImm0), \ + OpNum, AlwaysPrintImm0); \ + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); \ + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); \ +\ + if (!MCOperand_isReg(MO1)) { \ + printOperand(MI, OpNum, O); \ + return; \ + } \ +\ + SStream_concat(O, "%s", markup("")); \ + } else if (AlwaysPrintImm0 || OffImm > 0) { \ + SStream_concat(O, "%s%s", ", ", markup("")); \ + } \ + SStream_concat(O, "%s", "]"); \ + SStream_concat0(O, markup(">")); \ + } + DEFINE_printT2AddrModeImm8s4Operand(false) + DEFINE_printT2AddrModeImm8s4Operand(true) + + void printT2AddrModeImm0_1020s4Operand( + MCInst *MI, unsigned OpNum, + SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); + + SStream_concat(O, "%s", markup("")); + } + SStream_concat(O, "%s", "]"); + SStream_concat0(O, markup(">")); +} + +void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_T2AddrModeImm8OffsetOperand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + int32_t OffImm = (int32_t)MCOperand_getImm(MO1); + SStream_concat(O, "%s", ", "); + SStream_concat0(O, markup("")); +} + +void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + int32_t OffImm = (int32_t)MCOperand_getImm(MO1); + + SStream_concat(O, "%s", ", "); + SStream_concat0(O, markup("")); +} + +void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_T2AddrModeSoRegOperand, OpNum); + MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); + MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); + MCOperand *MO3 = MCInst_getOperand(MI, (OpNum + 2)); + + SStream_concat(O, "%s", markup("")); + } + SStream_concat(O, "%s", "]"); + SStream_concat0(O, markup(">")); +} + +void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_FPImmOperand, OpNum); + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); + SStream_concat(O, "%s", markup("")); +} + +void printVMOVModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VMOVModImmOperand, OpNum); + unsigned EncodedImm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + unsigned EltBits; + uint64_t Val = ARM_AM_decodeVMOVModImm(EncodedImm, &EltBits); + SStream_concat(O, "%s", markup("")); +} + +void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_ImmPlusOneOperand, OpNum); + unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + SStream_concat(O, "%s", markup("")); +} + +void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_RotImmOperand, OpNum); + unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + if (Imm == 0) + return; + + SStream_concat(O, "%s%s%s%d", ", ror ", markup("")); +} + +void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_ModImmOperand, OpNum); + MCOperand *Op = MCInst_getOperand(MI, (OpNum)); + + // Support for fixups (MCFixup) + if (MCOperand_isExpr(Op)) { + printOperand(MI, OpNum, O); + return; + } + + unsigned Bits = MCOperand_getImm(Op) & 0xFF; + unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7; + + bool PrintUnsigned = false; + switch (MCInst_getOpcode(MI)) { + case ARM_MOVi: + // Movs to PC should be treated unsigned + PrintUnsigned = + (MCOperand_getReg(MCInst_getOperand(MI, (OpNum - 1))) == + ARM_PC); + break; + case ARM_MSRi: + // Movs to special registers should be treated unsigned + PrintUnsigned = true; + break; + } + + int32_t Rotated = ARM_AM_rotr32(Bits, Rot); + if (ARM_AM_getSOImmVal(Rotated) == MCOperand_getImm(Op)) { + // #rot has the least possible value + SStream_concat(O, "%s", "#"); + SStream_concat0(O, markup("")); + return; + } + + // Explicit #bits, #rot implied + SStream_concat(O, "%s%s%u", "#", markup(""), ", #", markup("")); +} + +void printFBits16(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_FBits16, OpNum); + SStream_concat(O, "%s%s", markup("")); +} + +void printFBits32(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_FBits32, OpNum); + SStream_concat(O, "%s%s", markup("")); +} + +void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorIndex, OpNum); + SStream_concat(O, "%s", "["); + printInt64(O, + (int32_t)MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, "]"); +} + +void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListOne, OpNum); + SStream_concat0(O, "{"); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, "}"); +} + +void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListTwo, OpNum); + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); + unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); + unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1); + SStream_concat0(O, "{"); + printRegName(O, Reg0); + SStream_concat0(O, ", "); + printRegName(O, Reg1); + SStream_concat0(O, "}"); +} + +void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListTwoSpaced, OpNum); + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); + unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); + unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); + SStream_concat0(O, "{"); + printRegName(O, Reg0); + SStream_concat0(O, ", "); + printRegName(O, Reg1); + SStream_concat0(O, "}"); +} + +void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListThree, OpNum); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 1); + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2); + SStream_concat0(O, "}"); +} + +void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListFour, OpNum); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 1); + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2); + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 3); + SStream_concat0(O, "}"); +} + +void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListOneAllLanes, OpNum); + SStream_concat0(O, "{"); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, "[]}"); +} + +void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListTwoAllLanes, OpNum); + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); + unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); + unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1); + SStream_concat0(O, "{"); + printRegName(O, Reg0); + SStream_concat0(O, "[], "); + printRegName(O, Reg1); + SStream_concat0(O, "[]}"); +} + +void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListThreeAllLanes, OpNum); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, "[], "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 1); + SStream_concat0(O, "[], "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2); + SStream_concat0(O, "[]}"); +} + +void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListFourAllLanes, OpNum); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, "[], "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 1); + SStream_concat0(O, "[], "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2); + SStream_concat0(O, "[], "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 3); + SStream_concat0(O, "[]}"); +} + +void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListTwoSpacedAllLanes, OpNum); + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); + unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); + unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); + SStream_concat0(O, "{"); + printRegName(O, Reg0); + SStream_concat0(O, "[], "); + printRegName(O, Reg1); + SStream_concat0(O, "[]}"); +} + +void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListThreeSpacedAllLanes, OpNum); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, "[], "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2); + SStream_concat0(O, "[], "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 4); + SStream_concat0(O, "[]}"); +} + +void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListFourSpacedAllLanes, OpNum); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, "[], "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2); + SStream_concat0(O, "[], "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 4); + SStream_concat0(O, "[], "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 6); + SStream_concat0(O, "[]}"); +} + +void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListThreeSpaced, OpNum); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2); + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 4); + SStream_concat0(O, "}"); +} + +void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VectorListFourSpaced, OpNum); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2); + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 4); + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 6); + SStream_concat0(O, "}"); +} + +#define DEFINE_printMVEVectorList(NumRegs) \ + void CONCAT(printMVEVectorList, NumRegs)(MCInst * MI, unsigned OpNum, \ + SStream *O) \ + { \ + add_cs_detail(MI, CONCAT(ARM_OP_GROUP_MVEVectorList, NumRegs), \ + OpNum, NumRegs); \ + unsigned Reg = \ + MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ + const char *Prefix = "{"; \ + for (unsigned i = 0; i < NumRegs; i++) { \ + SStream_concat0(O, Prefix); \ + printRegName( \ + O, MCRegisterInfo_getSubReg(MI->MRI, Reg, \ + ARM_qsub_0 + i)); \ + Prefix = ", "; \ + } \ + SStream_concat0(O, "}"); \ + } +DEFINE_printMVEVectorList(2) DEFINE_printMVEVectorList(4) + +#define DEFINE_printComplexRotationOp(Angle, Remainder) \ + void CONCAT(printComplexRotationOp, CONCAT(Angle, Remainder))( \ + MCInst * MI, unsigned OpNo, SStream *O) \ + { \ + add_cs_detail( \ + MI, \ + CONCAT(CONCAT(ARM_OP_GROUP_ComplexRotationOp, Angle), \ + Remainder), \ + OpNo, Angle, Remainder); \ + unsigned Val = \ + MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); \ + SStream_concat(O, "#%d", (Val * Angle) + Remainder); \ + } + DEFINE_printComplexRotationOp(90, 0) DEFINE_printComplexRotationOp(180, + 90) + + void printVPTPredicateOperand(MCInst *MI, unsigned OpNum, + SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VPTPredicateOperand, OpNum); + ARMVCC_VPTCodes CC = (ARMVCC_VPTCodes)MCOperand_getImm( + MCInst_getOperand(MI, (OpNum))); + if (CC != ARMVCC_None) + SStream_concat0(O, ARMVPTPredToString(CC)); +} + +void printVPTMask(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_VPTMask, OpNum); + // (3 - the number of trailing zeroes) is the number of them / else. + unsigned Mask = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + unsigned NumTZ = CountTrailingZeros_32(Mask); + + for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { + bool T = ((Mask >> Pos) & 1) == 0; + if (T) + SStream_concat0(O, "t"); + + else + SStream_concat0(O, "e"); + } +} + +void printMveSaturateOp(MCInst *MI, unsigned OpNum, SStream *O) +{ + add_cs_detail(MI, ARM_OP_GROUP_MveSaturateOp, OpNum); + uint32_t Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + + printUInt32Bang(O, (Val == 1 ? 48 : 64)); +} + +const char *ARM_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx) +{ + return getRegisterName(RegNo, AltIdx); +} + +void ARM_LLVM_printInstruction(MCInst *MI, SStream *O, + void * /* MCRegisterInfo* */ info) +{ + printInst(MI, O, info); +} diff --git a/thirdparty/capstone/arch/ARM/ARMInstPrinter.h b/thirdparty/capstone/arch/ARM/ARMInstPrinter.h new file mode 100644 index 0000000..dcc7ba1 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMInstPrinter.h @@ -0,0 +1,203 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */ +/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + +//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This class prints an ARM MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +#ifndef CS_ARM_INSTPRINTER_H +#define CS_ARM_INSTPRINTER_H + +#include +#include +#include +#include + +#include "../../MCInst.h" +#include "../../MCInstPrinter.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" +#include "../../utils.h" +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b + +bool applyTargetSpecificCLOption(const char *Opt); +// Autogenerated by tblgen. +void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O); +void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O); +void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O); +void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O); +void printAM2PostIndexOp(MCInst *MI, unsigned OpNum, SStream *O); +void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O); +void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); +#define DECLARE_printAddrMode3Operand(AlwaysPrintImm0) \ + void CONCAT(printAddrMode3Operand, \ + AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O); +DECLARE_printAddrMode3Operand(false) DECLARE_printAddrMode3Operand(true) + + void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, + SStream *O); +void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, + bool AlwaysPrintImm0); +void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O); +void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O); +void printLdStmModeOperand(MCInst *MI, unsigned OpNum, SStream *O); +#define DECLARE_printAddrMode5Operand(AlwaysPrintImm0) \ + void CONCAT(printAddrMode5Operand, \ + AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O); +DECLARE_printAddrMode5Operand(false) DECLARE_printAddrMode5Operand(true) + +#define DECLARE_printAddrMode5FP16Operand(AlwaysPrintImm0) \ + void CONCAT(printAddrMode5FP16Operand, \ + AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O); + DECLARE_printAddrMode5FP16Operand(false) + + void printAddrMode6Operand(MCInst *MI, unsigned OpNum, + SStream *O); +void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O); +void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O); +void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O); +void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O); +void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O); +void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O); +#define DECLARE_printAdrLabelOperand(scale) \ + void CONCAT(printAdrLabelOperand, scale)(MCInst * MI, unsigned OpNum, \ + SStream *O); +DECLARE_printAdrLabelOperand(0) DECLARE_printAdrLabelOperand(2) + +#define DEFINE_printAdrLabelOperandAddr(scale) \ + static inline void CONCAT(printAdrLabelOperandAddr, scale)( \ + MCInst * MI, uint64_t Address, unsigned OpNum, SStream *O) \ + { \ + CONCAT(printAdrLabelOperand, scale)(MI, OpNum, O); \ + } + DEFINE_printAdrLabelOperandAddr(0) DEFINE_printAdrLabelOperandAddr(2) + + void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, + SStream *O); +void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O); +void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O); +void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O); +void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O, + unsigned Scale); +void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O); +void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O); +void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O); +void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O); +#define DECLARE_printAddrModeImm12Operand(AlwaysPrintImm0) \ + void CONCAT(printAddrModeImm12Operand, \ + AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O); +DECLARE_printAddrModeImm12Operand(false) DECLARE_printAddrModeImm12Operand(true) + +#define DECLARE_printT2AddrModeImm8Operand(AlwaysPrintImm0) \ + void CONCAT(printT2AddrModeImm8Operand, \ + AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O); + DECLARE_printT2AddrModeImm8Operand(true) + DECLARE_printT2AddrModeImm8Operand(false) + +#define DECLARE_printT2AddrModeImm8s4Operand(AlwaysPrintImm0) \ + void CONCAT(printT2AddrModeImm8s4Operand, \ + AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O); + DECLARE_printT2AddrModeImm8s4Operand(false) + DECLARE_printT2AddrModeImm8s4Operand(true) + + void printT2AddrModeImm0_1020s4Operand( + MCInst *MI, unsigned OpNum, + SStream *O); +void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O); +void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O); +void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printMandatoryRestrictedPredicateOperand(MCInst *MI, unsigned OpNum, + SStream *O); +void printMandatoryInvertedPredicateOperand(MCInst *MI, unsigned OpNum, + SStream *O); +void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O); +void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O); +void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O); +void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O); +void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O); +void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printVMOVModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printPCLabel(MCInst *MI, unsigned OpNum, SStream *O); +void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printFBits16(MCInst *MI, unsigned OpNum, SStream *O); +void printFBits32(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O); +void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O); +#define DECLARE_printMVEVectorList(NumRegs) \ + void CONCAT(printMVEVectorList, NumRegs)(MCInst * MI, unsigned OpNum, \ + SStream *O); +DECLARE_printMVEVectorList(2) DECLARE_printMVEVectorList(4) + +#define DECLARE_printComplexRotationOp(Angle, Remainder) \ + void CONCAT(printComplexRotationOp, CONCAT(Angle, Remainder))( \ + MCInst * MI, unsigned OpNum, SStream *O); + DECLARE_printComplexRotationOp(90, 0) + DECLARE_printComplexRotationOp(180, 90) + + // MVE + void printVPTPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); +void printVPTMask(MCInst *MI, unsigned OpNum, SStream *O); +#define DECLARE_printMveAddrModeRQOperand(shift) \ + void CONCAT(printMveAddrModeRQOperand, \ + shift)(MCInst * MI, unsigned OpNum, SStream *O); +DECLARE_printMveAddrModeRQOperand(0) DECLARE_printMveAddrModeRQOperand(3) + DECLARE_printMveAddrModeRQOperand(1) + DECLARE_printMveAddrModeRQOperand(2) + + void printMveSaturateOp(MCInst *MI, unsigned OpNum, + SStream *O); + +unsigned translateShiftImm(unsigned imm); + +#endif // CS_ARM_INSTPRINTER_H diff --git a/thirdparty/capstone/arch/ARM/ARMLinkage.h b/thirdparty/capstone/arch/ARM/ARMLinkage.h new file mode 100644 index 0000000..3dc431d --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMLinkage.h @@ -0,0 +1,22 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +#ifndef CS_ARM_LINKAGE_H +#define CS_ARM_LINKAGE_H + +// Function definitions to call static LLVM functions. + +#include "../../MCDisassembler.h" +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" +#include "capstone/capstone.h" + +DecodeStatus ARM_LLVM_getInstruction(csh handle, const uint8_t *Bytes, + size_t ByteLen, MCInst *MI, uint16_t *Size, + uint64_t Address, void *Info); +const char *ARM_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx); +void ARM_LLVM_printInstruction(MCInst *MI, SStream *O, + void * /* MCRegisterInfo* */ info); + +#endif // CS_ARM_LINKAGE_H diff --git a/thirdparty/capstone/arch/ARM/ARMMapping.c b/thirdparty/capstone/arch/ARM/ARMMapping.c new file mode 100644 index 0000000..22ba146 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMMapping.c @@ -0,0 +1,2144 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ +/* Rot127 , 2022-2023 */ + +#ifdef CAPSTONE_HAS_ARM + +#include +#include + +#include "capstone/arm.h" +#include "capstone/capstone.h" + +#include "../../Mapping.h" +#include "../../MCDisassembler.h" +#include "../../cs_priv.h" +#include "../../cs_simple_types.h" + +#include "ARMAddressingModes.h" +#include "ARMDisassemblerExtension.h" +#include "ARMBaseInfo.h" +#include "ARMLinkage.h" +#include "ARMInstPrinter.h" +#include "ARMMapping.h" + +static const name_map insn_alias_mnem_map[] = { + #include "ARMGenCSAliasMnemMap.inc" + { ARM_INS_ALIAS_ASR, "asr" }, + { ARM_INS_ALIAS_LSL, "lsl" }, + { ARM_INS_ALIAS_LSR, "lsr" }, + { ARM_INS_ALIAS_ROR, "ror" }, + { ARM_INS_ALIAS_RRX, "rrx" }, + { ARM_INS_ALIAS_UXTW, "uxtw" }, + { ARM_INS_ALIAS_LDM, "ldm" }, + { ARM_INS_ALIAS_POP, "pop" }, + { ARM_INS_ALIAS_PUSH, "push" }, + { ARM_INS_ALIAS_POPW, "pop.w" }, + { ARM_INS_ALIAS_PUSHW, "push.w" }, + { ARM_INS_ALIAS_VPOP, "vpop" }, + { ARM_INS_ALIAS_VPUSH, "vpush" }, + { ARM_INS_ALIAS_END, NULL } +}; + +static const char *get_custom_reg_alias(unsigned reg) +{ + switch (reg) { + case ARM_REG_R9: + return "sb"; + case ARM_REG_R10: + return "sl"; + case ARM_REG_R11: + return "fp"; + case ARM_REG_R12: + return "ip"; + case ARM_REG_R13: + return "sp"; + case ARM_REG_R14: + return "lr"; + case ARM_REG_R15: + return "pc"; + } + return NULL; +} + +const char *ARM_reg_name(csh handle, unsigned int reg) +{ + int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax; + const char *alias = get_custom_reg_alias(reg); + if ((syntax_opt & CS_OPT_SYNTAX_CS_REG_ALIAS) && alias) + return alias; + + if (reg == ARM_REG_INVALID || reg >= ARM_REG_ENDING) { + // This might be a system register or banked register encoding. + // Note: The system and banked register encodings can overlap. + // So this might return a system register name although a + // banked register name is expected. + const ARMSysReg_MClassSysReg *sys_reg = + ARMSysReg_lookupMClassSysRegByEncoding(reg); + if (sys_reg) + return sys_reg->Name; + const ARMBankedReg_BankedReg *banked_reg = + ARMBankedReg_lookupBankedRegByEncoding(reg); + if (banked_reg) + return banked_reg->Name; + } + + if (syntax_opt & CS_OPT_SYNTAX_NOREGNAME) { + return ARM_LLVM_getRegisterName(reg, ARM_NoRegAltName); + } + return ARM_LLVM_getRegisterName(reg, ARM_RegNamesRaw); +} + +const insn_map arm_insns[] = { +#include "ARMGenCSMappingInsn.inc" +}; + +void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + // Not used by ARM. Information is set after disassembly. +} + +/// Patches the register names with Capstone specific alias. +/// Those are common alias for registers (e.g. r15 = pc) +/// which are not set in LLVM. +static void patch_cs_reg_alias(char *asm_str) +{ + char *r9 = strstr(asm_str, "r9"); + while (r9) { + r9[0] = 's'; + r9[1] = 'b'; + r9 = strstr(asm_str, "r9"); + } + char *r10 = strstr(asm_str, "r10"); + while (r10) { + r10[0] = 's'; + r10[1] = 'l'; + memmove(r10 + 2, r10 + 3, strlen(r10 + 3)); + asm_str[strlen(asm_str) - 1] = '\0'; + r10 = strstr(asm_str, "r10"); + } + char *r11 = strstr(asm_str, "r11"); + while (r11) { + r11[0] = 'f'; + r11[1] = 'p'; + memmove(r11 + 2, r11 + 3, strlen(r11 + 3)); + asm_str[strlen(asm_str) - 1] = '\0'; + r11 = strstr(asm_str, "r11"); + } + char *r12 = strstr(asm_str, "r12"); + while (r12) { + r12[0] = 'i'; + r12[1] = 'p'; + memmove(r12 + 2, r12 + 3, strlen(r12 + 3)); + asm_str[strlen(asm_str) - 1] = '\0'; + r12 = strstr(asm_str, "r12"); + } + char *r13 = strstr(asm_str, "r13"); + while (r13) { + r13[0] = 's'; + r13[1] = 'p'; + memmove(r13 + 2, r13 + 3, strlen(r13 + 3)); + asm_str[strlen(asm_str) - 1] = '\0'; + r13 = strstr(asm_str, "r13"); + } + char *r14 = strstr(asm_str, "r14"); + while (r14) { + r14[0] = 'l'; + r14[1] = 'r'; + memmove(r14 + 2, r14 + 3, strlen(r14 + 3)); + asm_str[strlen(asm_str) - 1] = '\0'; + r14 = strstr(asm_str, "r14"); + } + char *r15 = strstr(asm_str, "r15"); + while (r15) { + r15[0] = 'p'; + r15[1] = 'c'; + memmove(r15 + 2, r15 + 3, strlen(r15 + 3)); + asm_str[strlen(asm_str) - 1] = '\0'; + r15 = strstr(asm_str, "r15"); + } +} + +/// Check if PC is updated from stack. Those POP instructions +/// are considered of group RETURN. +static void check_pop_return(MCInst *MI) { + if (!MI->flat_insn->detail) + return; + if (MI->flat_insn->id != ARM_INS_POP && MI->flat_insn->alias_id != ARM_INS_ALIAS_POP) { + return; + } + for (size_t i = 0; i < ARM_get_detail(MI)->op_count; ++i) { + cs_arm_op *op = &ARM_get_detail(MI)->operands[i]; + if (op->type == ARM_OP_REG && op->reg == ARM_REG_PC) { + add_group(MI, ARM_GRP_RET); + } + } +} + +/// Check if PC is directly written.Those instructions +/// are considered of group BRANCH. +static void check_writes_to_pc(MCInst *MI) { + if (!MI->flat_insn->detail) + return; + for (size_t i = 0; i < ARM_get_detail(MI)->op_count; ++i) { + cs_arm_op *op = &ARM_get_detail(MI)->operands[i]; + if (op->type == ARM_OP_REG && op->reg == ARM_REG_PC && (op->access & CS_AC_WRITE)) { + add_group(MI, ARM_GRP_JUMP); + return; + } + } +} + +/// Adds group to the instruction which are not defined in LLVM. +static void ARM_add_cs_groups(MCInst *MI) +{ + if (!MI->flat_insn->detail) + return; + check_pop_return(MI); + check_writes_to_pc(MI); + unsigned Opcode = MI->flat_insn->id; + switch (Opcode) { + default: + return; + case ARM_INS_SVC: + add_group(MI, ARM_GRP_INT); + break; + case ARM_INS_CDP: + case ARM_INS_CDP2: + case ARM_INS_MCR: + case ARM_INS_MCR2: + case ARM_INS_MCRR: + case ARM_INS_MCRR2: + case ARM_INS_MRC: + case ARM_INS_MRC2: + case ARM_INS_SMC: + add_group(MI, ARM_GRP_PRIVILEGE); + break; + } +} + +static void add_alias_details(MCInst *MI) { + if (!detail_is_set(MI)) + return; + switch (MI->flat_insn->alias_id) { + default: + return; + case ARM_INS_ALIAS_POP: + // Doesn't get set because memop is not printed. + ARM_get_detail(MI)->post_index = true; + // fallthrough + case ARM_INS_ALIAS_PUSH: + case ARM_INS_ALIAS_VPUSH: + case ARM_INS_ALIAS_VPOP: + map_add_implicit_read(MI, ARM_REG_SP); + map_add_implicit_write(MI, ARM_REG_SP); + break; + case ARM_INS_ALIAS_LDM: { + bool Writeback = true; + unsigned BaseReg = MCInst_getOpVal(MI, 0); + for (unsigned i = 3; i < MCInst_getNumOperands(MI); ++i) { + if (MCInst_getOpVal(MI, i) == BaseReg) + Writeback = false; + } + if (Writeback && detail_is_set(MI)) { + ARM_get_detail(MI)->operands[0].access |= CS_AC_WRITE; + MI->flat_insn->detail->writeback = true; + } + break; + } + } +} + +/// Some instructions have their operands not defined but +/// hardcoded as string. +/// Here we add those oprands to detail. +static void ARM_add_not_defined_ops(MCInst *MI) +{ + if (!detail_is_set(MI)) + return; + + if (MI->flat_insn->is_alias && MI->flat_insn->usesAliasDetails) { + add_alias_details(MI); + return; + } + + unsigned Opcode = MCInst_getOpcode(MI); + switch (Opcode) { + default: + return; + case ARM_t2MOVsra_flag: + case ARM_t2MOVsrl_flag: + ARM_insert_detail_op_imm_at(MI, 2, 1, CS_AC_READ); + break; + case ARM_VCMPEZD: + case ARM_VCMPZD: + case ARM_tRSB: + case ARM_VCMPEZH: + case ARM_VCMPEZS: + case ARM_VCMPZH: + case ARM_VCMPZS: + ARM_insert_detail_op_imm_at(MI, 1, 0, CS_AC_READ); + break; + case ARM_MVE_VSHLL_lws16bh: + case ARM_MVE_VSHLL_lws16th: + case ARM_MVE_VSHLL_lwu16bh: + case ARM_MVE_VSHLL_lwu16th: + ARM_insert_detail_op_imm_at(MI, 2, 16, CS_AC_READ); + break; + case ARM_MVE_VSHLL_lws8bh: + case ARM_MVE_VSHLL_lws8th: + case ARM_MVE_VSHLL_lwu8bh: + case ARM_MVE_VSHLL_lwu8th: + ARM_insert_detail_op_imm_at(MI, 2, 8, CS_AC_READ); + break; + case ARM_VCEQzv16i8: + case ARM_VCEQzv2f32: + case ARM_VCEQzv2i32: + case ARM_VCEQzv4f16: + case ARM_VCEQzv4f32: + case ARM_VCEQzv4i16: + case ARM_VCEQzv4i32: + case ARM_VCEQzv8f16: + case ARM_VCEQzv8i16: + case ARM_VCEQzv8i8: + case ARM_VCGEzv16i8: + case ARM_VCGEzv2f32: + case ARM_VCGEzv2i32: + case ARM_VCGEzv4f16: + case ARM_VCGEzv4f32: + case ARM_VCGEzv4i16: + case ARM_VCGEzv4i32: + case ARM_VCGEzv8f16: + case ARM_VCGEzv8i16: + case ARM_VCGEzv8i8: + case ARM_VCLEzv16i8: + case ARM_VCLEzv2f32: + case ARM_VCLEzv2i32: + case ARM_VCLEzv4f16: + case ARM_VCLEzv4f32: + case ARM_VCLEzv4i16: + case ARM_VCLEzv4i32: + case ARM_VCLEzv8f16: + case ARM_VCLEzv8i16: + case ARM_VCLEzv8i8: + case ARM_VCLTzv16i8: + case ARM_VCLTzv2f32: + case ARM_VCLTzv2i32: + case ARM_VCLTzv4f16: + case ARM_VCLTzv4f32: + case ARM_VCLTzv4i16: + case ARM_VCLTzv4i32: + case ARM_VCLTzv8f16: + case ARM_VCLTzv8i16: + case ARM_VCLTzv8i8: + case ARM_VCGTzv16i8: + case ARM_VCGTzv2f32: + case ARM_VCGTzv2i32: + case ARM_VCGTzv4f16: + case ARM_VCGTzv4f32: + case ARM_VCGTzv4i16: + case ARM_VCGTzv4i32: + case ARM_VCGTzv8f16: + case ARM_VCGTzv8i16: + case ARM_VCGTzv8i8: + ARM_insert_detail_op_imm_at(MI, 2, 0, CS_AC_READ); + break; + case ARM_BX_RET: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_LR, CS_AC_READ); + break; + case ARM_MOVPCLR: + case ARM_t2SUBS_PC_LR: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_PC, CS_AC_WRITE); + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_LR, CS_AC_READ); + break; + case ARM_FMSTAT: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_APSR_NZCV, + CS_AC_WRITE); + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPSCR, CS_AC_READ); + break; + case ARM_VLDR_FPCXTNS_off: + case ARM_VLDR_FPCXTNS_post: + case ARM_VLDR_FPCXTNS_pre: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPCXTNS, + CS_AC_WRITE); + break; + case ARM_VSTR_FPCXTNS_off: + case ARM_VSTR_FPCXTNS_post: + case ARM_VSTR_FPCXTNS_pre: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPCXTNS, CS_AC_READ); + break; + case ARM_VLDR_FPCXTS_off: + case ARM_VLDR_FPCXTS_post: + case ARM_VLDR_FPCXTS_pre: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPCXTS, CS_AC_WRITE); + break; + case ARM_VSTR_FPCXTS_off: + case ARM_VSTR_FPCXTS_post: + case ARM_VSTR_FPCXTS_pre: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPCXTS, CS_AC_READ); + break; + case ARM_VLDR_FPSCR_NZCVQC_off: + case ARM_VLDR_FPSCR_NZCVQC_post: + case ARM_VLDR_FPSCR_NZCVQC_pre: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSCR_NZCVQC, + CS_AC_WRITE); + break; + case ARM_VSTR_FPSCR_NZCVQC_off: + case ARM_VSTR_FPSCR_NZCVQC_post: + case ARM_VSTR_FPSCR_NZCVQC_pre: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSCR_NZCVQC, + CS_AC_READ); + break; + case ARM_VMSR: + case ARM_VLDR_FPSCR_off: + case ARM_VLDR_FPSCR_post: + case ARM_VLDR_FPSCR_pre: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSCR, CS_AC_WRITE); + break; + case ARM_VSTR_FPSCR_off: + case ARM_VSTR_FPSCR_post: + case ARM_VSTR_FPSCR_pre: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSCR, CS_AC_READ); + break; + case ARM_VLDR_P0_off: + case ARM_VLDR_P0_post: + case ARM_VLDR_P0_pre: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_P0, CS_AC_WRITE); + break; + case ARM_VSTR_P0_off: + case ARM_VSTR_P0_post: + case ARM_VSTR_P0_pre: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_P0, CS_AC_READ); + break; + case ARM_VLDR_VPR_off: + case ARM_VLDR_VPR_post: + case ARM_VLDR_VPR_pre: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_VPR, CS_AC_WRITE); + break; + case ARM_VSTR_VPR_off: + case ARM_VSTR_VPR_post: + case ARM_VSTR_VPR_pre: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_VPR, CS_AC_READ); + break; + case ARM_VMSR_FPEXC: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPEXC, CS_AC_WRITE); + break; + case ARM_VMSR_FPINST: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPINST, CS_AC_WRITE); + break; + case ARM_VMSR_FPINST2: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPINST2, + CS_AC_WRITE); + break; + case ARM_VMSR_FPSID: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSID, CS_AC_WRITE); + break; + case ARM_t2SRSDB: + case ARM_t2SRSIA: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_SP, CS_AC_WRITE); + break; + case ARM_t2SRSDB_UPD: + case ARM_t2SRSIA_UPD: + ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_SP, + CS_AC_READ | CS_AC_WRITE); + break; + case ARM_MRSsys: + case ARM_t2MRSsys_AR: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_SPSR, CS_AC_READ); + break; + case ARM_MRS: + case ARM_t2MRS_AR: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_APSR, CS_AC_READ); + break; + case ARM_VMRS: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPSCR, CS_AC_READ); + break; + case ARM_VMRS_FPCXTNS: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPCXTNS, CS_AC_READ); + break; + case ARM_VMRS_FPCXTS: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPCXTS, CS_AC_READ); + break; + case ARM_VMRS_FPEXC: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPEXC, CS_AC_READ); + break; + case ARM_VMRS_FPINST: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPINST, CS_AC_READ); + break; + case ARM_VMRS_FPINST2: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPINST2, CS_AC_READ); + break; + case ARM_VMRS_FPSCR_NZCVQC: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPSCR_NZCVQC, + CS_AC_READ); + break; + case ARM_VMRS_FPSID: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPSID, CS_AC_READ); + break; + case ARM_VMRS_MVFR0: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_MVFR0, CS_AC_READ); + break; + case ARM_VMRS_MVFR1: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_MVFR1, CS_AC_READ); + break; + case ARM_VMRS_MVFR2: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_MVFR2, CS_AC_READ); + break; + case ARM_VMRS_P0: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_P0, CS_AC_READ); + break; + case ARM_VMRS_VPR: + ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_VPR, CS_AC_READ); + break; + case ARM_MOVsr: + // Add shift information + ARM_get_detail(MI)->operands[1].shift.type = + (arm_shifter)ARM_AM_getSORegShOp( + MCInst_getOpVal(MI, 3)) + + ARM_SFT_ASR_REG - 1; + ARM_get_detail(MI)->operands[1].shift.value = + MCInst_getOpVal(MI, 2); + break; + case ARM_MOVsi: + if (ARM_AM_getSORegShOp(MCInst_getOpVal(MI, 2)) == ARM_AM_rrx) { + ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_RRX; + ARM_get_detail_op(MI, -1)->shift.value = + translateShiftImm(ARM_AM_getSORegOffset( + MCInst_getOpVal(MI, 2))); + return; + } + + ARM_get_detail_op(MI, -1)->shift.type = + (arm_shifter)ARM_AM_getSORegShOp( + MCInst_getOpVal(MI, 2)); + ARM_get_detail_op(MI, -1)->shift.value = translateShiftImm( + ARM_AM_getSORegOffset(MCInst_getOpVal(MI, 2))); + break; + case ARM_tLDMIA: { + bool Writeback = true; + unsigned BaseReg = MCInst_getOpVal(MI, 0); + for (unsigned i = 3; i < MCInst_getNumOperands(MI); ++i) { + if (MCInst_getOpVal(MI, i) == BaseReg) + Writeback = false; + } + if (Writeback && detail_is_set(MI)) { + ARM_get_detail(MI)->operands[0].access |= CS_AC_WRITE; + MI->flat_insn->detail->writeback = true; + } + break; + } + } +} + +/// Unfortunately there is currently no way to easily extract +/// information about the vector data usage (sign and width used). +/// See: https://github.com/capstone-engine/capstone/issues/2152 +void ARM_add_vector_data(MCInst *MI, arm_vectordata_type data_type) +{ + if (!detail_is_set(MI)) + return; + ARM_get_detail(MI)->vector_data = data_type; +} + +/// Unfortunately there is currently no way to easily extract +/// information about the vector size. +/// See: https://github.com/capstone-engine/capstone/issues/2152 +void ARM_add_vector_size(MCInst *MI, unsigned size) +{ + if (!detail_is_set(MI)) + return; + ARM_get_detail(MI)->vector_size = size; +} + +/// For ARM the attributation of post-indexed instructions is poor. +/// Disponents or index register are sometimes not defined as such. +/// Here we try to detect such cases. We check if the base register +/// is a writeback register, but no other memory operand +/// was disassembled. +/// Because there must be a second memory operand (disponent/index) +/// We assume that the following operand is actually +/// the disponent/index reg. +static void ARM_post_index_detection(MCInst *MI) +{ + if (!detail_is_set(MI) || ARM_get_detail(MI)->post_index) + return; + + int i = 0; + for (; i < ARM_get_detail(MI)->op_count; ++i) { + if (ARM_get_detail(MI)->operands[i].type & ARM_OP_MEM) + break; + } + if (i >= ARM_get_detail(MI)->op_count) { + // Last operand + return; + } + + cs_arm_op *op = &ARM_get_detail(MI)->operands[i]; + cs_arm_op op_next = ARM_get_detail(MI)->operands[i + 1]; + if (op_next.type == ARM_OP_INVALID || op->mem.disp != 0 || op->mem.index != ARM_REG_INVALID) + return; + + if (op_next.type & CS_OP_IMM) + op->mem.disp = op_next.imm; + else if (op_next.type & CS_OP_REG) + op->mem.index = op_next.reg; + + op->subtracted = op_next.subtracted; + ARM_get_detail(MI)->post_index = true; + MI->flat_insn->detail->writeback = true; + ARM_dec_op_count(MI); +} + +/// Decodes the asm string for a given instruction +/// and fills the detail information about the instruction and its operands. +void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info) +{ + MCRegisterInfo *MRI = (MCRegisterInfo *)info; + MI->MRI = MRI; + MI->fillDetailOps = detail_is_set(MI); + MI->flat_insn->usesAliasDetails = map_use_alias_details(MI); + ARM_LLVM_printInstruction(MI, O, info); + map_set_alias_id(MI, O, insn_alias_mnem_map, ARR_SIZE(insn_alias_mnem_map) - 1); + ARM_add_not_defined_ops(MI); + ARM_post_index_detection(MI); + ARM_add_cs_groups(MI); + int syntax_opt = MI->csh->syntax; + if (syntax_opt & CS_OPT_SYNTAX_CS_REG_ALIAS) + patch_cs_reg_alias(O->buffer); +} + +#ifndef CAPSTONE_DIET +static const char *const insn_name_maps[] = { +#include "ARMGenCSMappingInsnName.inc" + // Hard coded alias in LLVM, not defined as alias or instruction. + // We give them a unique ID for convenience. + "vpop", + "vpush", +}; +#endif + +#ifndef CAPSTONE_DIET +static const arm_reg arm_flag_regs[] = { + ARM_REG_APSR, ARM_REG_APSR_NZCV, ARM_REG_CPSR, + ARM_REG_FPCXTNS, ARM_REG_FPCXTS, ARM_REG_FPEXC, + ARM_REG_FPINST, ARM_REG_FPSCR, ARM_REG_FPSCR_NZCV, + ARM_REG_FPSCR_NZCVQC, +}; +#endif // CAPSTONE_DIET + +const char *ARM_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + if (id < ARM_INS_ALIAS_END && id > ARM_INS_ALIAS_BEGIN) { + if (id - ARM_INS_ALIAS_BEGIN >= ARR_SIZE(insn_alias_mnem_map)) + return NULL; + + return insn_alias_mnem_map[id - ARM_INS_ALIAS_BEGIN - 1].name; + } + if (id >= ARM_INS_ENDING) + return NULL; + + if (id < ARR_SIZE(insn_name_maps)) + return insn_name_maps[id]; + + // not found + return NULL; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static const name_map group_name_maps[] = { + // generic groups + { ARM_GRP_INVALID, NULL }, + { ARM_GRP_JUMP, "jump" }, + { ARM_GRP_CALL, "call" }, + { ARM_GRP_RET, "return" }, + { ARM_GRP_INT, "int" }, + { ARM_GRP_PRIVILEGE, "privilege" }, + { ARM_GRP_BRANCH_RELATIVE, "branch_relative" }, + +// architecture-specific groups +#include "ARMGenCSFeatureName.inc" +}; +#endif + +const char *ARM_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + +// list all relative branch instructions +// ie: insns[i].branch && !insns[i].indirect_branch +static const unsigned int insn_rel[] = { + ARM_BL, ARM_BLX_pred, ARM_Bcc, ARM_t2B, ARM_t2Bcc, + ARM_tB, ARM_tBcc, ARM_tCBNZ, ARM_tCBZ, ARM_BL_pred, + ARM_BLXi, ARM_tBL, ARM_tBLXi, 0 +}; + +static const unsigned int insn_blx_rel_to_arm[] = { ARM_tBLXi, 0 }; + +// check if this insn is relative branch +bool ARM_rel_branch(cs_struct *h, unsigned int id) +{ + int i; + + for (i = 0; insn_rel[i]; i++) { + if (id == insn_rel[i]) { + return true; + } + } + + // not found + return false; +} + +bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) +{ + int i; + + for (i = 0; insn_blx_rel_to_arm[i]; i++) + if (id == insn_blx_rel_to_arm[i]) + return true; + + // not found + return false; +} + +void ARM_check_updates_flags(MCInst *MI) +{ +#ifndef CAPSTONE_DIET + if (!detail_is_set(MI)) + return; + cs_detail *detail = get_detail(MI); + for (int i = 0; i < detail->regs_write_count; ++i) { + if (detail->regs_write[i] == 0) + return; + for (int j = 0; j < ARR_SIZE(arm_flag_regs); ++j) { + if (detail->regs_write[i] == arm_flag_regs[j]) { + detail->arm.update_flags = true; + return; + } + } + } +#endif // CAPSTONE_DIET +} + +void ARM_set_instr_map_data(MCInst *MI) +{ + map_cs_id(MI, arm_insns, ARR_SIZE(arm_insns)); + map_implicit_reads(MI, arm_insns); + map_implicit_writes(MI, arm_insns); + ARM_check_updates_flags(MI); + map_groups(MI, arm_insns); +} + +bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info) +{ + ARM_init_cs_detail(instr); + bool Result = ARM_LLVM_getInstruction(handle, code, code_len, instr, + size, address, + info) != MCDisassembler_Fail; + ARM_set_instr_map_data(instr); + return Result; +} + +#define GET_REGINFO_MC_DESC +#include "ARMGenRegisterInfo.inc" + +void ARM_init_mri(MCRegisterInfo *MRI) +{ + MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, ARM_REG_ENDING, 0, 0, + ARMMCRegisterClasses, + ARR_SIZE(ARMMCRegisterClasses), 0, 0, + ARMRegDiffLists, 0, ARMSubRegIdxLists, + ARR_SIZE(ARMSubRegIdxLists), 0); +} + +#ifndef CAPSTONE_DIET +static const map_insn_ops insn_operands[] = { +#include "ARMGenCSMappingInsnOp.inc" +}; + +void ARM_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count) +{ + uint8_t i; + uint8_t read_count, write_count; + cs_arm *arm = &(insn->detail->arm); + + read_count = insn->detail->regs_read_count; + write_count = insn->detail->regs_write_count; + + // implicit registers + memcpy(regs_read, insn->detail->regs_read, + read_count * sizeof(insn->detail->regs_read[0])); + memcpy(regs_write, insn->detail->regs_write, + write_count * sizeof(insn->detail->regs_write[0])); + + // explicit registers + for (i = 0; i < arm->op_count; i++) { + cs_arm_op *op = &(arm->operands[i]); + switch ((int)op->type) { + case ARM_OP_REG: + if ((op->access & CS_AC_READ) && + !arr_exist(regs_read, read_count, op->reg)) { + regs_read[read_count] = (uint16_t)op->reg; + read_count++; + } + if ((op->access & CS_AC_WRITE) && + !arr_exist(regs_write, write_count, op->reg)) { + regs_write[write_count] = (uint16_t)op->reg; + write_count++; + } + break; + case ARM_OP_MEM: + // registers appeared in memory references always being read + if ((op->mem.base != ARM_REG_INVALID) && + !arr_exist(regs_read, read_count, op->mem.base)) { + regs_read[read_count] = (uint16_t)op->mem.base; + read_count++; + } + if ((op->mem.index != ARM_REG_INVALID) && + !arr_exist(regs_read, read_count, op->mem.index)) { + regs_read[read_count] = (uint16_t)op->mem.index; + read_count++; + } + if ((insn->detail->writeback) && + (op->mem.base != ARM_REG_INVALID) && + !arr_exist(regs_write, write_count, op->mem.base)) { + regs_write[write_count] = + (uint16_t)op->mem.base; + write_count++; + } + default: + break; + } + } + + *regs_read_count = read_count; + *regs_write_count = write_count; +} +#endif + +void ARM_setup_op(cs_arm_op *op) +{ + memset(op, 0, sizeof(cs_arm_op)); + op->type = ARM_OP_INVALID; + op->vector_index = -1; + op->neon_lane = -1; +} + +void ARM_init_cs_detail(MCInst *MI) +{ + if (detail_is_set(MI)) { + unsigned int i; + + memset(get_detail(MI), 0, + offsetof(cs_detail, arm) + sizeof(cs_arm)); + + for (i = 0; i < ARR_SIZE(ARM_get_detail(MI)->operands); i++) + ARM_setup_op(&ARM_get_detail(MI)->operands[i]); + ARM_get_detail(MI)->cc = ARMCC_UNDEF; + ARM_get_detail(MI)->vcc = ARMVCC_None; + } +} + +static uint64_t t_add_pc(MCInst *MI, uint64_t v) +{ + int32_t imm = (int32_t)v; + if (ARM_rel_branch(MI->csh, MI->Opcode)) { + uint32_t address; + + // only do this for relative branch + if (MI->csh->mode & CS_MODE_THUMB) { + address = (uint32_t)MI->address + 4; + if (ARM_blx_to_arm_mode(MI->csh, MI->Opcode)) { + // here need to align down to the nearest 4-byte address +#define _ALIGN_DOWN(v, align_width) ((v / align_width) * align_width) + address = _ALIGN_DOWN(address, 4); +#undef _ALIGN_DOWN + } + } else { + address = (uint32_t)MI->address + 8; + } + + imm += address; + return imm; + } + return v; +} + +/// Transform a Qs register to its corresponding Ds + Offset register. +static uint64_t t_qpr_to_dpr_list(MCInst *MI, unsigned OpNum, uint8_t offset) +{ + uint64_t v = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + if (v >= ARM_REG_Q0 && v <= ARM_REG_Q15) + return ARM_REG_D0 + offset + (v - ARM_REG_Q0) * 2; + return v + offset; +} + +static uint64_t t_mod_imm_rotate(uint64_t v) +{ + unsigned Bits = v & 0xFF; + unsigned Rot = (v & 0xF00) >> 7; + int32_t Rotated = ARM_AM_rotr32(Bits, Rot); + return Rotated; +} + +inline static uint64_t t_mod_imm_bits(uint64_t v) +{ + unsigned Bits = v & 0xFF; + return Bits; +} + +inline static uint64_t t_mod_imm_rot(uint64_t v) +{ + unsigned Rot = (v & 0xF00) >> 7; + return Rot; +} + +static uint64_t t_vmov_mod_imm(uint64_t v) +{ + unsigned EltBits; + uint64_t Val = ARM_AM_decodeVMOVModImm(v, &EltBits); + return Val; +} + +/// Initializes or finishes a memory operand of Capstone (depending on \p +/// status). A memory operand in Capstone can be assembled by two LLVM operands. +/// E.g. the base register and the immediate disponent. +static void ARM_set_mem_access(MCInst *MI, bool status) +{ + if (!detail_is_set(MI)) + return; + set_doing_mem(MI, status); + if (status) { + ARM_get_detail_op(MI, 0)->type = ARM_OP_MEM; + ARM_get_detail_op(MI, 0)->mem.base = ARM_REG_INVALID; + ARM_get_detail_op(MI, 0)->mem.index = ARM_REG_INVALID; + ARM_get_detail_op(MI, 0)->mem.scale = 1; + ARM_get_detail_op(MI, 0)->mem.disp = 0; + +#ifndef CAPSTONE_DIET + uint8_t access = + map_get_op_access(MI, ARM_get_detail(MI)->op_count); + ARM_get_detail_op(MI, 0)->access = access; +#endif + } else { + // done, select the next operand slot + ARM_inc_op_count(MI); + } +} + +/// Fills cs_detail with operand shift information for the last added operand. +static void add_cs_detail_RegImmShift(MCInst *MI, ARM_AM_ShiftOpc ShOpc, + unsigned ShImm) +{ + if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm)) + return; + + if (!detail_is_set(MI)) + return; + + if (doing_mem(MI)) + ARM_get_detail_op(MI, 0)->shift.type = (arm_shifter)ShOpc; + else + ARM_get_detail_op(MI, -1)->shift.type = (arm_shifter)ShOpc; + + if (ShOpc != ARM_AM_rrx) { + if (doing_mem(MI)) + ARM_get_detail_op(MI, 0)->shift.value = + translateShiftImm(ShImm); + else + ARM_get_detail_op(MI, -1)->shift.value = + translateShiftImm(ShImm); + } +} + +/// Fills cs_detail with the data of the operand. +/// This function handles operands which's original printer function has no +/// specialities. +static void add_cs_detail_general(MCInst *MI, arm_op_group op_group, + unsigned OpNum) +{ + if (!detail_is_set(MI)) + return; + cs_op_type op_type = map_get_op_type(MI, OpNum); + + // Fill cs_detail + switch (op_group) { + default: + printf("ERROR: Operand group %d not handled!\n", op_group); + assert(0); + case ARM_OP_GROUP_PredicateOperand: + case ARM_OP_GROUP_MandatoryPredicateOperand: + case ARM_OP_GROUP_MandatoryInvertedPredicateOperand: + case ARM_OP_GROUP_MandatoryRestrictedPredicateOperand: { + ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm( + MCInst_getOperand(MI, OpNum)); + if ((unsigned)CC == 15 && + op_group == ARM_OP_GROUP_PredicateOperand) { + ARM_get_detail(MI)->cc = ARMCC_UNDEF; + return; + } + if (CC == ARMCC_HS && + op_group == + ARM_OP_GROUP_MandatoryRestrictedPredicateOperand) { + ARM_get_detail(MI)->cc = ARMCC_HS; + return; + } + ARM_get_detail(MI)->cc = CC; + if (CC != ARMCC_AL) + map_add_implicit_read(MI, ARM_REG_CPSR); + break; + } + case ARM_OP_GROUP_VPTPredicateOperand: { + ARMVCC_VPTCodes VCC = (ARMVCC_VPTCodes)MCOperand_getImm( + MCInst_getOperand(MI, OpNum)); + assert(VCC <= ARMVCC_Else); + if (VCC != ARMVCC_None) + ARM_get_detail(MI)->vcc = VCC; + break; + } + case ARM_OP_GROUP_Operand: + if (op_type == CS_OP_IMM) { + if (doing_mem(MI)) { + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, + MCInst_getOpVal(MI, + OpNum)); + } else { + ARM_set_detail_op_imm( + MI, OpNum, ARM_OP_IMM, + t_add_pc(MI, + MCInst_getOpVal(MI, OpNum))); + } + } else if (op_type == CS_OP_REG) + if (doing_mem(MI)) { + bool is_index_reg = map_get_op_type(MI, OpNum) & + CS_OP_MEM; + ARM_set_detail_op_mem( + MI, OpNum, is_index_reg, 0, 0, + MCInst_getOpVal(MI, OpNum)); + } else { + ARM_set_detail_op_reg( + MI, OpNum, MCInst_getOpVal(MI, OpNum)); + } + else + assert(0 && "Op type not handled."); + break; + case ARM_OP_GROUP_PImmediate: + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_PIMM, + MCInst_getOpVal(MI, OpNum)); + break; + case ARM_OP_GROUP_CImmediate: + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_CIMM, + MCInst_getOpVal(MI, OpNum)); + break; + case ARM_OP_GROUP_AddrMode6Operand: + if (!doing_mem(MI)) + ARM_set_mem_access(MI, true); + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, + MCInst_getOpVal(MI, OpNum)); + ARM_get_detail_op(MI, 0)->mem.align = + MCInst_getOpVal(MI, OpNum + 1) << 3; + ARM_set_mem_access(MI, false); + break; + case ARM_OP_GROUP_AddrMode6OffsetOperand: { + arm_reg reg = MCInst_getOpVal(MI, OpNum); + if (reg != 0) { + ARM_set_detail_op_mem_offset(MI, OpNum, reg, false); + } + break; + } + case ARM_OP_GROUP_AddrMode7Operand: + if (!doing_mem(MI)) + ARM_set_mem_access(MI, true); + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, + MCInst_getOpVal(MI, OpNum)); + ARM_set_mem_access(MI, false); + break; + case ARM_OP_GROUP_SBitModifierOperand: { + unsigned SBit = MCInst_getOpVal(MI, OpNum); + + if (SBit == 0) { + // Does not edit set flags. + map_remove_implicit_write(MI, ARM_CPSR); + ARM_get_detail(MI)->update_flags = false; + break; + } + // Add the implicit write again. Some instruction miss it. + map_add_implicit_write(MI, ARM_CPSR); + ARM_get_detail(MI)->update_flags = true; + break; + } + case ARM_OP_GROUP_VectorListOne: + case ARM_OP_GROUP_VectorListOneAllLanes: + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 0)); + break; + case ARM_OP_GROUP_VectorListTwo: + case ARM_OP_GROUP_VectorListTwoAllLanes: { + unsigned Reg = MCInst_getOpVal(MI, OpNum); + ARM_set_detail_op_reg(MI, OpNum, + MCRegisterInfo_getSubReg(MI->MRI, Reg, + ARM_dsub_0)); + ARM_set_detail_op_reg(MI, OpNum, + MCRegisterInfo_getSubReg(MI->MRI, Reg, + ARM_dsub_1)); + break; + } + case ARM_OP_GROUP_VectorListTwoSpacedAllLanes: + case ARM_OP_GROUP_VectorListTwoSpaced: { + unsigned Reg = MCInst_getOpVal(MI, OpNum); + ARM_set_detail_op_reg(MI, OpNum, + MCRegisterInfo_getSubReg(MI->MRI, Reg, + ARM_dsub_0)); + ARM_set_detail_op_reg(MI, OpNum, + MCRegisterInfo_getSubReg(MI->MRI, Reg, + ARM_dsub_2)); + break; + } + case ARM_OP_GROUP_VectorListThree: + case ARM_OP_GROUP_VectorListThreeAllLanes: + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 0)); + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 1)); + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 2)); + break; + case ARM_OP_GROUP_VectorListThreeSpacedAllLanes: + case ARM_OP_GROUP_VectorListThreeSpaced: + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 0)); + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 2)); + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 4)); + break; + case ARM_OP_GROUP_VectorListFour: + case ARM_OP_GROUP_VectorListFourAllLanes: + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 0)); + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 1)); + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 2)); + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 3)); + break; + case ARM_OP_GROUP_VectorListFourSpacedAllLanes: + case ARM_OP_GROUP_VectorListFourSpaced: + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 0)); + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 2)); + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 4)); + ARM_set_detail_op_reg(MI, OpNum, + t_qpr_to_dpr_list(MI, OpNum, 6)); + break; + case ARM_OP_GROUP_NoHashImmediate: + ARM_set_detail_op_neon_lane(MI, OpNum); + break; + case ARM_OP_GROUP_RegisterList: { + // All operands n MI from OpNum on are registers. + // But the MappingInsnOps.inc has only a single entry for the whole + // list. So all registers in the list share those attributes. + unsigned access = map_get_op_access(MI, OpNum); + for (unsigned i = OpNum, e = MCInst_getNumOperands(MI); i != e; + ++i) { + unsigned Reg = + MCOperand_getReg(MCInst_getOperand(MI, i)); + + ARM_get_detail_op(MI, 0)->type = ARM_OP_REG; + ARM_get_detail_op(MI, 0)->reg = Reg; + ARM_get_detail_op(MI, 0)->access = access; + ARM_inc_op_count(MI); + } + break; + } + case ARM_OP_GROUP_ThumbITMask: { + unsigned Mask = MCInst_getOpVal(MI, OpNum); + unsigned Firstcond = MCInst_getOpVal(MI, OpNum - 1); + unsigned CondBit0 = Firstcond & 1; + unsigned NumTZ = CountTrailingZeros_32(Mask); + unsigned Pos, e; + ARM_PredBlockMask PredMask = 0; + + // Check the documentation of ARM_PredBlockMask how the bits are set. + for (Pos = 3, e = NumTZ; Pos > e; --Pos) { + bool Then = ((Mask >> Pos) & 1) == CondBit0; + if (Then) + PredMask <<= 1; + else { + PredMask |= 1; + PredMask <<= 1; + } + } + PredMask |= 1; + ARM_get_detail(MI)->pred_mask = PredMask; + break; + } + case ARM_OP_GROUP_VPTMask: { + unsigned Mask = MCInst_getOpVal(MI, OpNum); + unsigned NumTZ = CountTrailingZeros_32(Mask); + ARM_PredBlockMask PredMask = 0; + + // Check the documentation of ARM_PredBlockMask how the bits are set. + for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { + bool T = ((Mask >> Pos) & 1) == 0; + if (T) + PredMask <<= 1; + else { + PredMask |= 1; + PredMask <<= 1; + } + } + PredMask |= 1; + ARM_get_detail(MI)->pred_mask = PredMask; + break; + } + case ARM_OP_GROUP_MSRMaskOperand: { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4; + unsigned Mask = (unsigned)MCOperand_getImm(Op) & 0xf; + bool IsOutReg = OpNum == 0; + + if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) { + const ARMSysReg_MClassSysReg *TheReg; + unsigned SYSm = (unsigned)MCOperand_getImm(Op) & + 0xFFF; // 12-bit SYMm + unsigned Opcode = MCInst_getOpcode(MI); + + if (Opcode == ARM_t2MSR_M && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)) { + TheReg = + ARMSysReg_lookupMClassSysRegBy12bitSYSmValue( + SYSm); + if (TheReg && MClassSysReg_isInRequiredFeatures( + TheReg, ARM_FeatureDSP)) { + ARM_set_detail_op_sysop( + MI, TheReg->sysreg.mclasssysreg, + ARM_OP_SYSREG, IsOutReg, Mask, + SYSm); + return; + } + } + + SYSm &= 0xff; + if (Opcode == ARM_t2MSR_M && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)) { + TheReg = + ARMSysReg_lookupMClassSysRegAPSRNonDeprecated( + SYSm); + if (TheReg) { + ARM_set_detail_op_sysop( + MI, TheReg->sysreg.mclasssysreg, + ARM_OP_SYSREG, IsOutReg, Mask, + SYSm); + return; + } + } + + TheReg = ARMSysReg_lookupMClassSysRegBy8bitSYSmValue( + SYSm); + if (TheReg) { + ARM_set_detail_op_sysop( + MI, TheReg->sysreg.mclasssysreg, + ARM_OP_SYSREG, IsOutReg, Mask, SYSm); + return; + } + + if (detail_is_set(MI)) + MCOperand_CreateImm0(MI, SYSm); + + ARM_set_detail_op_sysop(MI, SYSm, ARM_OP_SYSREG, + IsOutReg, Mask, SYSm); + + return; + } + + if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { + switch (Mask) { + default: + assert(0 && "Unexpected mask value!"); + case 4: + ARM_set_detail_op_sysop(MI, + ARM_MCLASSSYSREG_APSR_G, + ARM_OP_SYSREG, IsOutReg, + Mask, UINT16_MAX); + return; + case 8: + ARM_set_detail_op_sysop( + MI, ARM_MCLASSSYSREG_APSR_NZCVQ, + ARM_OP_SYSREG, IsOutReg, Mask, + UINT16_MAX); + return; + case 12: + ARM_set_detail_op_sysop( + MI, ARM_MCLASSSYSREG_APSR_NZCVQG, + ARM_OP_SYSREG, IsOutReg, Mask, + UINT16_MAX); + return; + } + } + + unsigned field = 0; + if (Mask) { + if (Mask & 8) + field += SpecRegRBit ? ARM_FIELD_SPSR_F : + ARM_FIELD_CPSR_F; + if (Mask & 4) + field += SpecRegRBit ? ARM_FIELD_SPSR_S : + ARM_FIELD_CPSR_S; + if (Mask & 2) + field += SpecRegRBit ? ARM_FIELD_SPSR_X : + ARM_FIELD_CPSR_X; + if (Mask & 1) + field += SpecRegRBit ? ARM_FIELD_SPSR_C : + ARM_FIELD_CPSR_C; + + ARM_set_detail_op_sysop(MI, field, + SpecRegRBit ? ARM_OP_SPSR : + ARM_OP_CPSR, + IsOutReg, Mask, UINT16_MAX); + } + break; + } + case ARM_OP_GROUP_SORegRegOperand: { + int64_t imm = + MCOperand_getImm(MCInst_getOperand(MI, OpNum + 2)); + ARM_get_detail_op(MI, 0)->shift.type = + (imm & 7) + ARM_SFT_ASR_REG - 1; + if (ARM_AM_getSORegShOp(imm) != ARM_AM_rrx) + ARM_get_detail_op(MI, 0)->shift.value = + MCInst_getOpVal(MI, OpNum + 1); + + ARM_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum)); + break; + } + case ARM_OP_GROUP_ModImmOperand: { + int64_t imm = MCInst_getOpVal(MI, OpNum); + int32_t Rotated = t_mod_imm_rotate(imm); + if (ARM_AM_getSOImmVal(Rotated) == imm) { + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, + t_mod_imm_rotate(imm)); + return; + } + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, + t_mod_imm_bits(imm)); + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, + t_mod_imm_rot(imm)); + break; + } + case ARM_OP_GROUP_VMOVModImmOperand: + ARM_set_detail_op_imm( + MI, OpNum, ARM_OP_IMM, + t_vmov_mod_imm(MCInst_getOpVal(MI, OpNum))); + break; + case ARM_OP_GROUP_FPImmOperand: + ARM_set_detail_op_float(MI, OpNum, MCInst_getOpVal(MI, OpNum)); + break; + case ARM_OP_GROUP_ImmPlusOneOperand: + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, + MCInst_getOpVal(MI, OpNum) + 1); + break; + case ARM_OP_GROUP_RotImmOperand: { + unsigned RotImm = MCInst_getOpVal(MI, OpNum); + if (RotImm == 0) + return; + ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_ROR; + ARM_get_detail_op(MI, -1)->shift.value = RotImm * 8; + break; + } + case ARM_OP_GROUP_FBits16: + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, + 16 - MCInst_getOpVal(MI, OpNum)); + break; + case ARM_OP_GROUP_FBits32: + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, + 32 - MCInst_getOpVal(MI, OpNum)); + break; + case ARM_OP_GROUP_T2SOOperand: + case ARM_OP_GROUP_SORegImmOperand: + ARM_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum)); + uint64_t imm = MCInst_getOpVal(MI, OpNum + 1); + ARM_AM_ShiftOpc ShOpc = ARM_AM_getSORegShOp(imm); + unsigned ShImm = ARM_AM_getSORegOffset(imm); + if (op_group == ARM_OP_GROUP_SORegImmOperand) { + if (ShOpc == ARM_AM_no_shift || + (ShOpc == ARM_AM_lsl && !ShImm)) + return; + } + add_cs_detail_RegImmShift(MI, ShOpc, ShImm); + break; + case ARM_OP_GROUP_PostIdxRegOperand: { + bool sub = MCInst_getOpVal(MI, OpNum + 1) ? false : true; + ARM_set_detail_op_mem_offset(MI, OpNum, + MCInst_getOpVal(MI, OpNum), sub); + ARM_get_detail(MI)->post_index = true; + break; + } + case ARM_OP_GROUP_PostIdxImm8Operand: { + unsigned Imm8 = MCInst_getOpVal(MI, OpNum); + bool sub = !(Imm8 & 256); + ARM_set_detail_op_mem_offset(MI, OpNum, (Imm8 & 0xff), sub); + ARM_get_detail(MI)->post_index = true; + break; + } + case ARM_OP_GROUP_PostIdxImm8s4Operand: { + unsigned Imm8s = MCInst_getOpVal(MI, OpNum); + bool sub = !(Imm8s & 256); + ARM_set_detail_op_mem_offset(MI, OpNum, (Imm8s & 0xff) << 2, sub); + ARM_get_detail(MI)->post_index = true; + break; + } + case ARM_OP_GROUP_AddrModeTBB: + case ARM_OP_GROUP_AddrModeTBH: + ARM_set_mem_access(MI, true); + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, + MCInst_getOpVal(MI, OpNum)); + ARM_set_detail_op_mem(MI, OpNum + 1, true, 0, 0, + MCInst_getOpVal(MI, OpNum + 1)); + if (op_group == ARM_OP_GROUP_AddrModeTBH) { + ARM_get_detail_op(MI, 0)->shift.type = ARM_SFT_LSL; + ARM_get_detail_op(MI, 0)->shift.value = 1; + ARM_get_detail_op(MI, 0)->mem.lshift = 1; + } + ARM_set_mem_access(MI, false); + break; + case ARM_OP_GROUP_AddrMode2Operand: { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + if (!MCOperand_isReg(MO1)) + // Handled in printOperand + break; + + ARM_set_mem_access(MI, true); + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, + MCInst_getOpVal(MI, OpNum)); + unsigned int imm3 = MCInst_getOpVal(MI, OpNum + 2); + unsigned ShOff = ARM_AM_getAM2Offset(imm3); + ARM_AM_AddrOpc subtracted = ARM_AM_getAM2Op(imm3); + if (!MCOperand_getReg(MCInst_getOperand(MI, OpNum + 1)) && + ShOff) { + ARM_get_detail_op(MI, 0)->shift.type = + (arm_shifter)subtracted; + ARM_get_detail_op(MI, 0)->shift.value = ShOff; + ARM_get_detail_op(MI, 0)->subtracted = subtracted == + ARM_AM_sub; + ARM_set_mem_access(MI, false); + break; + } + ARM_get_detail_op(MI, 0)->shift.type = subtracted == ARM_AM_sub; + ARM_set_detail_op_mem(MI, OpNum + 1, true, 0, 0, + MCInst_getOpVal(MI, OpNum + 1)); + add_cs_detail_RegImmShift(MI, ARM_AM_getAM2ShiftOpc(imm3), + ARM_AM_getAM2Offset(imm3)); + ARM_set_mem_access(MI, false); + break; + } + case ARM_OP_GROUP_AddrMode2OffsetOperand: { + uint64_t imm2 = MCInst_getOpVal(MI, OpNum + 1); + ARM_AM_AddrOpc subtracted = ARM_AM_getAM2Op(imm2); + if (!MCInst_getOpVal(MI, OpNum)) { + ARM_set_detail_op_mem_offset(MI, OpNum + 1, + ARM_AM_getAM2Offset(imm2), + subtracted == ARM_AM_sub); + ARM_get_detail(MI)->post_index = true; + return; + } + ARM_set_detail_op_mem_offset(MI, OpNum, + MCInst_getOpVal(MI, OpNum), + subtracted == ARM_AM_sub); + ARM_get_detail(MI)->post_index = true; + add_cs_detail_RegImmShift(MI, ARM_AM_getAM2ShiftOpc(imm2), + ARM_AM_getAM2Offset(imm2)); + break; + } + case ARM_OP_GROUP_AddrMode3OffsetOperand: { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + ARM_AM_AddrOpc subtracted = + ARM_AM_getAM3Op(MCOperand_getImm(MO2)); + if (MCOperand_getReg(MO1)) { + ARM_set_detail_op_mem_offset(MI, OpNum, + MCInst_getOpVal(MI, OpNum), + subtracted == ARM_AM_sub); + ARM_get_detail(MI)->post_index = true; + return; + } + ARM_set_detail_op_mem_offset( + MI, OpNum + 1, + ARM_AM_getAM3Offset(MCInst_getOpVal(MI, OpNum + 1)), + subtracted == ARM_AM_sub); + ARM_get_detail(MI)->post_index = true; + break; + } + case ARM_OP_GROUP_ThumbAddrModeSPOperand: + case ARM_OP_GROUP_ThumbAddrModeImm5S1Operand: + case ARM_OP_GROUP_ThumbAddrModeImm5S2Operand: + case ARM_OP_GROUP_ThumbAddrModeImm5S4Operand: { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + if (!MCOperand_isReg(MO1)) + // Handled in printOperand + break; + + ARM_set_mem_access(MI, true); + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, + MCInst_getOpVal(MI, OpNum)); + unsigned ImmOffs = MCInst_getOpVal(MI, OpNum + 1); + if (ImmOffs) { + unsigned Scale = 0; + switch (op_group) { + default: + assert(0 && + "Cannot determine scale. Operand group not handled."); + case ARM_OP_GROUP_ThumbAddrModeImm5S1Operand: + Scale = 1; + break; + case ARM_OP_GROUP_ThumbAddrModeImm5S2Operand: + Scale = 2; + break; + case ARM_OP_GROUP_ThumbAddrModeImm5S4Operand: + case ARM_OP_GROUP_ThumbAddrModeSPOperand: + Scale = 4; + break; + } + ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0, + ImmOffs * Scale); + } + ARM_set_mem_access(MI, false); + break; + } + case ARM_OP_GROUP_ThumbAddrModeRROperand: { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + if (!MCOperand_isReg(MO1)) + // Handled in printOperand + break; + + ARM_set_mem_access(MI, true); + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, + MCInst_getOpVal(MI, OpNum)); + arm_reg RegNum = MCInst_getOpVal(MI, OpNum + 1); + if (RegNum) + ARM_set_detail_op_mem(MI, OpNum + 1, true, 0, 0, + RegNum); + ARM_set_mem_access(MI, false); + break; + } + case ARM_OP_GROUP_T2AddrModeImm8OffsetOperand: + case ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand: { + int32_t OffImm = MCInst_getOpVal(MI, OpNum); + if (OffImm == INT32_MIN) + ARM_set_detail_op_mem_offset(MI, OpNum, 0, false); + else { + bool sub = OffImm < 0; + OffImm = OffImm < 0 ? OffImm * -1 : OffImm; + ARM_set_detail_op_mem_offset(MI, OpNum, OffImm, sub); + } + ARM_get_detail(MI)->post_index = true; + break; + } + case ARM_OP_GROUP_T2AddrModeSoRegOperand: { + if (!doing_mem(MI)) + ARM_set_mem_access(MI, true); + + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, + MCInst_getOpVal(MI, OpNum)); + ARM_set_detail_op_mem(MI, OpNum + 1, true, 0, 0, + MCInst_getOpVal(MI, OpNum + 1)); + unsigned ShAmt = MCInst_getOpVal(MI, OpNum + 2); + if (ShAmt) { + ARM_get_detail_op(MI, 0)->shift.type = ARM_SFT_LSL; + ARM_get_detail_op(MI, 0)->shift.value = ShAmt; + } + ARM_set_mem_access(MI, false); + break; + } + case ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand: + ARM_set_mem_access(MI, true); + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, + MCInst_getOpVal(MI, OpNum)); + int64_t Imm0_1024s4 = MCInst_getOpVal(MI, OpNum + 1); + if (Imm0_1024s4) + ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0, + Imm0_1024s4 * 4); + ARM_set_mem_access(MI, false); + break; + case ARM_OP_GROUP_PKHLSLShiftImm: { + unsigned ShiftImm = MCInst_getOpVal(MI, OpNum); + if (ShiftImm == 0) + return; + ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_LSL; + ARM_get_detail_op(MI, -1)->shift.value = ShiftImm; + break; + } + case ARM_OP_GROUP_PKHASRShiftImm: { + unsigned RShiftImm = MCInst_getOpVal(MI, OpNum); + if (RShiftImm == 0) + RShiftImm = 32; + ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_ASR; + ARM_get_detail_op(MI, -1)->shift.value = RShiftImm; + break; + } + case ARM_OP_GROUP_ThumbS4ImmOperand: + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, + MCInst_getOpVal(MI, OpNum) * 4); + break; + case ARM_OP_GROUP_ThumbSRImm: { + unsigned SRImm = MCInst_getOpVal(MI, OpNum); + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, + SRImm == 0 ? 32 : SRImm); + break; + } + case ARM_OP_GROUP_BitfieldInvMaskImmOperand: { + uint32_t v = ~MCInst_getOpVal(MI, OpNum); + int32_t lsb = CountTrailingZeros_32(v); + int32_t width = (32 - countLeadingZeros(v)) - lsb; + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, lsb); + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, width); + break; + } + case ARM_OP_GROUP_CPSIMod: { + unsigned Mode = MCInst_getOpVal(MI, OpNum); + ARM_get_detail(MI)->cps_mode = Mode; + break; + } + case ARM_OP_GROUP_CPSIFlag: { + unsigned IFlags = MCInst_getOpVal(MI, OpNum); + ARM_get_detail(MI)->cps_flag = IFlags == 0 ? ARM_CPSFLAG_NONE : + IFlags; + break; + } + case ARM_OP_GROUP_GPRPairOperand: { + unsigned Reg = MCInst_getOpVal(MI, OpNum); + ARM_set_detail_op_reg(MI, OpNum, + MCRegisterInfo_getSubReg(MI->MRI, Reg, + ARM_gsub_0)); + ARM_set_detail_op_reg(MI, OpNum, + MCRegisterInfo_getSubReg(MI->MRI, Reg, + ARM_gsub_1)); + break; + } + case ARM_OP_GROUP_MemBOption: + case ARM_OP_GROUP_InstSyncBOption: + case ARM_OP_GROUP_TraceSyncBOption: + ARM_get_detail(MI)->mem_barrier = MCInst_getOpVal(MI, OpNum); + break; + case ARM_OP_GROUP_ShiftImmOperand: { + unsigned ShiftOp = MCInst_getOpVal(MI, OpNum); + bool isASR = (ShiftOp & (1 << 5)) != 0; + unsigned Amt = ShiftOp & 0x1f; + if (isASR) { + unsigned tmp = Amt == 0 ? 32 : Amt; + ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_ASR; + ARM_get_detail_op(MI, -1)->shift.value = tmp; + } else if (Amt) { + ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_LSL; + ARM_get_detail_op(MI, -1)->shift.value = Amt; + } + break; + } + case ARM_OP_GROUP_VectorIndex: + ARM_get_detail_op(MI, -1)->vector_index = + MCInst_getOpVal(MI, OpNum); + break; + case ARM_OP_GROUP_CoprocOptionImm: + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, + MCInst_getOpVal(MI, OpNum)); + break; + case ARM_OP_GROUP_ThumbLdrLabelOperand: { + int32_t OffImm = MCInst_getOpVal(MI, OpNum); + if (OffImm == INT32_MIN) + OffImm = 0; + ARM_get_detail_op(MI, 0)->type = ARM_OP_MEM; + ARM_get_detail_op(MI, 0)->mem.base = ARM_REG_PC; + ARM_get_detail_op(MI, 0)->mem.index = ARM_REG_INVALID; + ARM_get_detail_op(MI, 0)->mem.scale = 1; + ARM_get_detail_op(MI, 0)->mem.disp = OffImm; + ARM_get_detail_op(MI, 0)->access = CS_AC_READ; + ARM_inc_op_count(MI); + break; + } + case ARM_OP_GROUP_BankedRegOperand: { + uint32_t Banked = MCInst_getOpVal(MI, OpNum); + const ARMBankedReg_BankedReg *TheReg = + ARMBankedReg_lookupBankedRegByEncoding(Banked); + bool IsOutReg = OpNum == 0; + ARM_set_detail_op_sysop(MI, TheReg->sysreg.bankedreg, + ARM_OP_BANKEDREG, IsOutReg, UINT8_MAX, + TheReg->Encoding & + 0xf); // Bit[4:0] are SYSm + break; + } + case ARM_OP_GROUP_SetendOperand: { + bool be = MCInst_getOpVal(MI, OpNum) != 0; + if (be) { + ARM_get_detail_op(MI, 0)->type = ARM_OP_SETEND; + ARM_get_detail_op(MI, 0)->setend = ARM_SETEND_BE; + } else { + ARM_get_detail_op(MI, 0)->type = ARM_OP_SETEND; + ARM_get_detail_op(MI, 0)->setend = ARM_SETEND_LE; + } + ARM_inc_op_count(MI); + break; + } + case ARM_OP_GROUP_MveSaturateOp: { + uint32_t Val = MCInst_getOpVal(MI, OpNum); + Val = Val == 1 ? 48 : 64; + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, Val); + break; + } + } +} + +/// Fills cs_detail with the data of the operand. +/// This function handles operands which original printer function is a template +/// with one argument. +static void add_cs_detail_template_1(MCInst *MI, arm_op_group op_group, + unsigned OpNum, uint64_t temp_arg_0) +{ + if (!detail_is_set(MI)) + return; + switch (op_group) { + default: + printf("ERROR: Operand group %d not handled!\n", op_group); + assert(0); + case ARM_OP_GROUP_AddrModeImm12Operand_0: + case ARM_OP_GROUP_AddrModeImm12Operand_1: + case ARM_OP_GROUP_T2AddrModeImm8s4Operand_0: + case ARM_OP_GROUP_T2AddrModeImm8s4Operand_1: { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + if (!MCOperand_isReg(MO1)) + // Handled in printOperand + return; + } + // fallthrough + case ARM_OP_GROUP_T2AddrModeImm8Operand_0: + case ARM_OP_GROUP_T2AddrModeImm8Operand_1: { + bool AlwaysPrintImm0 = temp_arg_0; + ARM_set_mem_access(MI, true); + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, + MCInst_getOpVal(MI, OpNum)); + int32_t Imm8 = MCInst_getOpVal(MI, OpNum + 1); + if (Imm8 == INT32_MIN) + Imm8 = 0; + ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0, Imm8); + if (AlwaysPrintImm0) + map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum)); + + ARM_set_mem_access(MI, false); + break; + } + case ARM_OP_GROUP_AdrLabelOperand_0: + case ARM_OP_GROUP_AdrLabelOperand_2: { + unsigned Scale = temp_arg_0; + int32_t OffImm = MCInst_getOpVal(MI, OpNum) << Scale; + if (OffImm == INT32_MIN) + OffImm = 0; + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, OffImm); + break; + } + case ARM_OP_GROUP_AddrMode3Operand_0: + case ARM_OP_GROUP_AddrMode3Operand_1: { + bool AlwaysPrintImm0 = temp_arg_0; + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + if (!MCOperand_isReg(MO1)) + // Handled in printOperand + break; + + ARM_set_mem_access(MI, true); + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, + MCInst_getOpVal(MI, OpNum)); + + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + ARM_AM_AddrOpc Sign = + ARM_AM_getAM3Op(MCInst_getOpVal(MI, OpNum + 2)); + + if (MCOperand_getReg(MO2)) { + ARM_set_detail_op_mem(MI, OpNum + 1, true, 0, 0, + MCInst_getOpVal(MI, OpNum + 1)); + ARM_get_detail_op(MI, 0)->subtracted = Sign == + ARM_AM_sub; + ARM_set_mem_access(MI, false); + break; + } + unsigned ImmOffs = + ARM_AM_getAM3Offset(MCInst_getOpVal(MI, OpNum + 2)); + + if (AlwaysPrintImm0 || ImmOffs || Sign == ARM_AM_sub) { + ARM_set_detail_op_mem(MI, OpNum + 2, false, 0, 0, + ImmOffs); + ARM_get_detail_op(MI, 0)->subtracted = Sign == + ARM_AM_sub; + } + ARM_set_mem_access(MI, false); + break; + } + case ARM_OP_GROUP_AddrMode5Operand_0: + case ARM_OP_GROUP_AddrMode5Operand_1: + case ARM_OP_GROUP_AddrMode5FP16Operand_0: { + bool AlwaysPrintImm0 = temp_arg_0; + + if (AlwaysPrintImm0) + map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum)); + + cs_arm_op *Op = ARM_get_detail_op(MI, 0); + Op->type = ARM_OP_MEM; + Op->mem.base = MCInst_getOpVal(MI, OpNum); + Op->mem.index = ARM_REG_INVALID; + Op->mem.scale = 1; + Op->mem.disp = 0; + Op->access = CS_AC_READ; + + ARM_AM_AddrOpc SubFlag = + ARM_AM_getAM5Op(MCInst_getOpVal(MI, OpNum + 1)); + unsigned ImmOffs = + ARM_AM_getAM5Offset(MCInst_getOpVal(MI, OpNum + 1)); + + if (AlwaysPrintImm0 || ImmOffs || SubFlag == ARM_AM_sub) { + if (op_group == ARM_OP_GROUP_AddrMode5FP16Operand_0) { + Op->mem.disp = ImmOffs * 2; + } else { + Op->mem.disp = ImmOffs * 4; + } + Op->subtracted = SubFlag == ARM_AM_sub; + } + ARM_inc_op_count(MI); + break; + } + case ARM_OP_GROUP_MveAddrModeRQOperand_0: + case ARM_OP_GROUP_MveAddrModeRQOperand_1: + case ARM_OP_GROUP_MveAddrModeRQOperand_2: + case ARM_OP_GROUP_MveAddrModeRQOperand_3: { + unsigned Shift = temp_arg_0; + ARM_set_mem_access(MI, true); + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, + MCInst_getOpVal(MI, OpNum)); + ARM_set_detail_op_mem(MI, OpNum + 1, true, 0, 0, + MCInst_getOpVal(MI, OpNum + 1)); + if (Shift > 0) { + add_cs_detail_RegImmShift(MI, ARM_AM_uxtw, Shift); + } + ARM_set_mem_access(MI, false); + break; + } + case ARM_OP_GROUP_MVEVectorList_2: + case ARM_OP_GROUP_MVEVectorList_4: { + unsigned NumRegs = temp_arg_0; + arm_reg Reg = MCInst_getOpVal(MI, OpNum); + for (unsigned i = 0; i < NumRegs; ++i) { + arm_reg SubReg = MCRegisterInfo_getSubReg( + MI->MRI, Reg, ARM_qsub_0 + i); + ARM_set_detail_op_reg(MI, OpNum, SubReg); + } + break; + } + } +} + +/// Fills cs_detail with the data of the operand. +/// This function handles operands which's original printer function is a +/// template with two arguments. +static void add_cs_detail_template_2(MCInst *MI, arm_op_group op_group, + unsigned OpNum, uint64_t temp_arg_0, + uint64_t temp_arg_1) +{ + if (!detail_is_set(MI)) + return; + switch (op_group) { + default: + printf("ERROR: Operand group %d not handled!\n", op_group); + assert(0); + case ARM_OP_GROUP_ComplexRotationOp_90_0: + case ARM_OP_GROUP_ComplexRotationOp_180_90: { + unsigned Angle = temp_arg_0; + unsigned Remainder = temp_arg_1; + unsigned Rotation = (MCInst_getOpVal(MI, OpNum) * Angle) + Remainder; + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, Rotation); + break; + } + } +} + +/// Fills cs_detail with the data of the operand. +/// Calls to this function are should not be added by hand! Please checkout the +/// patch `AddCSDetail` of the CppTranslator. +void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, + va_list args) +{ + if (!detail_is_set(MI) || !map_fill_detail_ops(MI)) + return; + switch (op_group) { + case ARM_OP_GROUP_RegImmShift: { + ARM_AM_ShiftOpc shift_opc = va_arg(args, ARM_AM_ShiftOpc); + unsigned shift_imm = va_arg(args, unsigned); + add_cs_detail_RegImmShift(MI, shift_opc, shift_imm); + return; + } + case ARM_OP_GROUP_AdrLabelOperand_0: + case ARM_OP_GROUP_AdrLabelOperand_2: + case ARM_OP_GROUP_AddrMode3Operand_0: + case ARM_OP_GROUP_AddrMode3Operand_1: + case ARM_OP_GROUP_AddrMode5Operand_0: + case ARM_OP_GROUP_AddrMode5Operand_1: + case ARM_OP_GROUP_AddrModeImm12Operand_0: + case ARM_OP_GROUP_AddrModeImm12Operand_1: + case ARM_OP_GROUP_T2AddrModeImm8Operand_0: + case ARM_OP_GROUP_T2AddrModeImm8Operand_1: + case ARM_OP_GROUP_T2AddrModeImm8s4Operand_0: + case ARM_OP_GROUP_T2AddrModeImm8s4Operand_1: + case ARM_OP_GROUP_MVEVectorList_2: + case ARM_OP_GROUP_MVEVectorList_4: + case ARM_OP_GROUP_AddrMode5FP16Operand_0: + case ARM_OP_GROUP_MveAddrModeRQOperand_0: + case ARM_OP_GROUP_MveAddrModeRQOperand_3: + case ARM_OP_GROUP_MveAddrModeRQOperand_1: + case ARM_OP_GROUP_MveAddrModeRQOperand_2: { + unsigned op_num = va_arg(args, unsigned); + uint64_t templ_arg_0 = va_arg(args, uint64_t); + add_cs_detail_template_1(MI, op_group, op_num, templ_arg_0); + return; + } + case ARM_OP_GROUP_ComplexRotationOp_180_90: + case ARM_OP_GROUP_ComplexRotationOp_90_0: { + unsigned op_num = va_arg(args, unsigned); + uint64_t templ_arg_0 = va_arg(args, uint64_t); + uint64_t templ_arg_1 = va_arg(args, uint64_t); + add_cs_detail_template_2(MI, op_group, op_num, templ_arg_0, + templ_arg_1); + return; + } + } + unsigned op_num = va_arg(args, unsigned); + add_cs_detail_general(MI, op_group, op_num); +} + +/// Inserts a register to the detail operands at @index. +/// Already present operands are moved. +void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg, + cs_ac_type access) +{ + if (!detail_is_set(MI)) + return; + + assert(ARM_get_detail(MI)->op_count < MAX_ARM_OPS); + + cs_arm_op op; + ARM_setup_op(&op); + op.type = ARM_OP_REG; + op.reg = Reg; + op.access = access; + + cs_arm_op *ops = ARM_get_detail(MI)->operands; + int i = ARM_get_detail(MI)->op_count; + assert(i < MAX_ARM_OPS); + for (; i > 0 && i > index; --i) { + ops[i] = ops[i - 1]; + } + ops[index] = op; + ARM_inc_op_count(MI); +} + +/// Inserts a immediate to the detail operands at @index. +/// Already present operands are moved. +void ARM_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Val, + cs_ac_type access) +{ + if (!detail_is_set(MI)) + return; + + assert(ARM_get_detail(MI)->op_count < MAX_ARM_OPS); + + cs_arm_op op; + ARM_setup_op(&op); + op.type = ARM_OP_IMM; + op.imm = Val; + op.access = access; + + cs_arm_op *ops = ARM_get_detail(MI)->operands; + int i = ARM_get_detail(MI)->op_count; + assert(i < MAX_ARM_OPS); + for (; i > 0 && i > index; --i) { + ops[i] = ops[i - 1]; + } + ops[index] = op; + ARM_inc_op_count(MI); +} + +/// Adds a register ARM operand at position OpNum and increases the op_count by +/// one. +void ARM_set_detail_op_reg(MCInst *MI, unsigned OpNum, arm_reg Reg) +{ + if (!detail_is_set(MI)) + return; + assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM)); + assert(map_get_op_type(MI, OpNum) == CS_OP_REG); + + ARM_get_detail_op(MI, 0)->type = ARM_OP_REG; + ARM_get_detail_op(MI, 0)->reg = Reg; + ARM_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); + ARM_inc_op_count(MI); +} + +/// Adds an immediate ARM operand at position OpNum and increases the op_count +/// by one. +void ARM_set_detail_op_imm(MCInst *MI, unsigned OpNum, arm_op_type ImmType, + int64_t Imm) +{ + if (!detail_is_set(MI)) + return; + assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM)); + assert(map_get_op_type(MI, OpNum) == CS_OP_IMM); + assert(ImmType == ARM_OP_IMM || ImmType == ARM_OP_PIMM || + ImmType == ARM_OP_CIMM); + + ARM_get_detail_op(MI, 0)->type = ImmType; + ARM_get_detail_op(MI, 0)->imm = Imm; + ARM_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); + ARM_inc_op_count(MI); +} + +/// Adds the operand as to the previously added memory operand. +void ARM_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val, + bool subtracted) +{ + assert(map_get_op_type(MI, OpNum) & CS_OP_MEM); + + if (!doing_mem(MI)) { + assert((ARM_get_detail_op(MI, -1) != NULL) && + (ARM_get_detail_op(MI, -1)->type == ARM_OP_MEM)); + ARM_dec_op_count(MI); + } + + if ((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM) + ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, Val); + else if ((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG) + ARM_set_detail_op_mem(MI, OpNum, true, 0, 0, Val); + else + assert(0 && "Memory type incorrect."); + ARM_get_detail_op(MI, 0)->subtracted = subtracted; + + if (!doing_mem(MI)) + ARM_inc_op_count(MI); +} + +/// Adds a memory ARM operand at position OpNum. op_count is *not* increased by +/// one. This is done by ARM_set_mem_access(). +void ARM_set_detail_op_mem(MCInst *MI, unsigned OpNum, bool is_index_reg, + int scale, int lshift, uint64_t Val) +{ + if (!detail_is_set(MI)) + return; + assert(map_get_op_type(MI, OpNum) & CS_OP_MEM); + cs_op_type secondary_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM; + switch (secondary_type) { + default: + assert(0 && "Secondary type not supported yet."); + case CS_OP_REG: { + assert(secondary_type == CS_OP_REG); + if (!is_index_reg) { + ARM_get_detail_op(MI, 0)->mem.base = Val; + if (MCInst_opIsTying(MI, OpNum) || MCInst_opIsTied(MI, OpNum)) { + // Base registers can be writeback registers. + // For this they tie an MC operand which has write + // access. But this one is never processed in the printer + // (because it is never emitted). Therefor it is never + // added to the modified list. + // Here we check for this case and add the memory register + // to the modified list. + map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum)); + MI->flat_insn->detail->writeback = true; + } else { + // If the base register is not tied, set the writebak flag to false. + // Writeback for ARM only refers to the memory base register. + // But other registers might be marked as tied as well. + MI->flat_insn->detail->writeback = false; + } + } else { + ARM_get_detail_op(MI, 0)->mem.index = Val; + } + ARM_get_detail_op(MI, 0)->mem.scale = scale; + ARM_get_detail_op(MI, 0)->mem.lshift = lshift; + + break; + } + case CS_OP_IMM: { + assert(secondary_type == CS_OP_IMM); + if (((int32_t)Val) < 0) + ARM_get_detail_op(MI, 0)->subtracted = true; + ARM_get_detail_op(MI, 0)->mem.disp = ((int64_t)Val < 0) ? -Val : + Val; + break; + } + } + + ARM_get_detail_op(MI, 0)->type = ARM_OP_MEM; + ARM_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); +} + +/// Sets the neon_lane in the previous operand to the value of +/// MI->operands[OpNum] Decrements op_count by 1. +void ARM_set_detail_op_neon_lane(MCInst *MI, unsigned OpNum) +{ + if (!detail_is_set(MI)) + return; + assert(map_get_op_type(MI, OpNum) == CS_OP_IMM); + unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + ARM_get_detail_op(MI, -1)->neon_lane = Val; +} + +/// Adds a System Register and increments op_count by one. +/// @type ARM_OP_SYSREG, ARM_OP_BANKEDREG, ARM_OP_SYSM... +/// @p Mask is the MSR mask or UINT8_MAX if not set. +void ARM_set_detail_op_sysop(MCInst *MI, int Val, arm_op_type type, + bool IsOutReg, uint8_t Mask, uint16_t Sysm) +{ + if (!detail_is_set(MI)) + return; + ARM_get_detail_op(MI, 0)->type = type; + switch (type) { + default: + assert(0 && "Unknown system operand type."); + case ARM_OP_SYSREG: + ARM_get_detail_op(MI, 0)->sysop.reg.mclasssysreg = Val; + break; + case ARM_OP_BANKEDREG: + ARM_get_detail_op(MI, 0)->sysop.reg.bankedreg = Val; + break; + case ARM_OP_SPSR: + case ARM_OP_CPSR: + ARM_get_detail_op(MI, 0)->reg = + type == ARM_OP_SPSR ? ARM_REG_SPSR : ARM_REG_CPSR; + ARM_get_detail_op(MI, 0)->sysop.psr_bits = Val; + break; + } + ARM_get_detail_op(MI, 0)->sysop.sysm = Sysm; + ARM_get_detail_op(MI, 0)->sysop.msr_mask = Mask; + ARM_get_detail_op(MI, 0)->access = IsOutReg ? CS_AC_WRITE : CS_AC_READ; + ARM_inc_op_count(MI); +} + +/// Transforms the immediate of the operand to a float and stores it. +/// Increments the op_counter by one. +void ARM_set_detail_op_float(MCInst *MI, unsigned OpNum, uint64_t Imm) +{ + if (!detail_is_set(MI)) + return; + ARM_get_detail_op(MI, 0)->type = ARM_OP_FP; + ARM_get_detail_op(MI, 0)->fp = ARM_AM_getFPImmFloat(Imm); + ARM_inc_op_count(MI); +} + +#endif diff --git a/thirdparty/capstone/arch/ARM/ARMMapping.h b/thirdparty/capstone/arch/ARM/ARMMapping.h new file mode 100644 index 0000000..2109242 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMMapping.h @@ -0,0 +1,88 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +#ifndef CS_ARM_MAPPING_H +#define CS_ARM_MAPPING_H + +#include "../../include/capstone/capstone.h" +#include "../../utils.h" +#include "ARMBaseInfo.h" + +typedef enum { +#include "ARMGenCSOpGroup.inc" +} arm_op_group; + +extern const ARMBankedReg_BankedReg * +ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding); +extern const ARMSysReg_MClassSysReg * +ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding); + +// return name of register in friendly string +const char *ARM_reg_name(csh handle, unsigned int reg); + +void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info); + +// given internal insn id, return public instruction ID +void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +const char *ARM_insn_name(csh handle, unsigned int id); + +const char *ARM_group_name(csh handle, unsigned int id); + +// check if this insn is relative branch +bool ARM_rel_branch(cs_struct *h, unsigned int insn_id); + +bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id); + +void ARM_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count); + +const ARMBankedReg_BankedReg * +ARMBankedReg_lookupBankedRegByEncoding(uint8_t encoding); + +bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info); +void ARM_set_instr_map_data(MCInst *MI); + +void ARM_init_mri(MCRegisterInfo *MRI); + +// cs_detail related functions +void ARM_init_cs_detail(MCInst *MI); +void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, + va_list args); +static inline void add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, + ...) +{ + if (!MI->flat_insn->detail) + return; + va_list args; + va_start(args, op_group); + ARM_add_cs_detail(MI, op_group, args); + va_end(args); +} + +void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg, + cs_ac_type access); +void ARM_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Val, + cs_ac_type access); +void ARM_set_detail_op_reg(MCInst *MI, unsigned OpNum, arm_reg Reg); +void ARM_set_detail_op_sysop(MCInst *MI, int SysReg, arm_op_type type, + bool IsOutReg, uint8_t Mask, uint16_t Sysm); +void ARM_set_detail_op_imm(MCInst *MI, unsigned OpNum, arm_op_type ImmType, + int64_t Imm); +void ARM_set_detail_op_float(MCInst *MI, unsigned OpNum, uint64_t Imm); +void ARM_set_detail_op_mem(MCInst *MI, unsigned OpNum, bool is_index_reg, + int scale, int lshift, uint64_t Val); +void ARM_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val, + bool subtracted); +void ARM_set_detail_op_neon_lane(MCInst *MI, unsigned OpNum); + +void ARM_check_updates_flags(MCInst *MI); + +void ARM_setup_op(cs_arm_op *op); +void ARM_add_vector_data(MCInst *MI, arm_vectordata_type data_type); +void ARM_add_vector_size(MCInst *MI, unsigned size); + +#endif // CS_ARM_MAPPING_H diff --git a/thirdparty/capstone/arch/ARM/ARMMappingInsn.inc b/thirdparty/capstone/arch/ARM/ARMMappingInsn.inc new file mode 100644 index 0000000..59b6b9f --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMMappingInsn.inc @@ -0,0 +1,20189 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +{ ARM_ASRi, ARM_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + + { ARM_ASRr, ARM_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_ITasm, ARM_INS_IT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_LDRBT_POST, ARM_INS_LDRBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_LDRConstPool, + ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_LDRT_POST, ARM_INS_LDRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_LSLi, ARM_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_LSLr, ARM_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_LSRi, ARM_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_LSRr, ARM_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_RORi, ARM_INS_ROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_RORr, ARM_INS_ROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_RRXi, ARM_INS_RRX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_STRBT_POST, ARM_INS_STRBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_STRT_POST, ARM_INS_STRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD1LNdAsm_16, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1LNdAsm_32, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1LNdAsm_8, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1LNdWB_fixed_Asm_16, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1LNdWB_fixed_Asm_32, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1LNdWB_fixed_Asm_8, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1LNdWB_register_Asm_16, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1LNdWB_register_Asm_32, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1LNdWB_register_Asm_8, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNdAsm_16, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNdAsm_32, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNdAsm_8, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNdWB_fixed_Asm_16, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNdWB_fixed_Asm_32, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNdWB_fixed_Asm_8, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNdWB_register_Asm_16, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNdWB_register_Asm_32, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNdWB_register_Asm_8, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNqAsm_16, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNqAsm_32, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNqWB_fixed_Asm_16, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNqWB_fixed_Asm_32, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNqWB_register_Asm_16, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNqWB_register_Asm_32, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPdAsm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPdAsm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPdAsm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPdWB_fixed_Asm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPdWB_fixed_Asm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPdWB_fixed_Asm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPdWB_register_Asm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPdWB_register_Asm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPdWB_register_Asm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPqAsm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPqAsm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPqAsm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPqWB_fixed_Asm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPqWB_fixed_Asm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPqWB_fixed_Asm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPqWB_register_Asm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPqWB_register_Asm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPqWB_register_Asm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNdAsm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNdAsm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNdAsm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNdWB_fixed_Asm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNdWB_fixed_Asm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNdWB_fixed_Asm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNdWB_register_Asm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNdWB_register_Asm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNdWB_register_Asm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNqAsm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNqAsm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNqWB_fixed_Asm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNqWB_fixed_Asm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNqWB_register_Asm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNqWB_register_Asm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3dAsm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD3dAsm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD3dAsm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD3dWB_fixed_Asm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3dWB_fixed_Asm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3dWB_fixed_Asm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3dWB_register_Asm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3dWB_register_Asm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3dWB_register_Asm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3qAsm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD3qAsm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD3qAsm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD3qWB_fixed_Asm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3qWB_fixed_Asm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3qWB_fixed_Asm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3qWB_register_Asm_16, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3qWB_register_Asm_32, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3qWB_register_Asm_8, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPdAsm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPdAsm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPdAsm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPdWB_fixed_Asm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPdWB_fixed_Asm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPdWB_fixed_Asm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPdWB_register_Asm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPdWB_register_Asm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPdWB_register_Asm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPqAsm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPqAsm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPqAsm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPqWB_fixed_Asm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPqWB_fixed_Asm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPqWB_fixed_Asm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPqWB_register_Asm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPqWB_register_Asm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPqWB_register_Asm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNdAsm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNdAsm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNdAsm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNdWB_fixed_Asm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNdWB_fixed_Asm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNdWB_fixed_Asm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNdWB_register_Asm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNdWB_register_Asm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNdWB_register_Asm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNqAsm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNqAsm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNqWB_fixed_Asm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNqWB_fixed_Asm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNqWB_register_Asm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNqWB_register_Asm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4dAsm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD4dAsm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD4dAsm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD4dWB_fixed_Asm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4dWB_fixed_Asm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4dWB_fixed_Asm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4dWB_register_Asm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4dWB_register_Asm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4dWB_register_Asm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4qAsm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD4qAsm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD4qAsm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD4qWB_fixed_Asm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4qWB_fixed_Asm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4qWB_fixed_Asm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4qWB_register_Asm_16, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4qWB_register_Asm_32, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4qWB_register_Asm_8, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1LNdAsm_16, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1LNdAsm_32, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1LNdAsm_8, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1LNdWB_fixed_Asm_16, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1LNdWB_fixed_Asm_32, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1LNdWB_fixed_Asm_8, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1LNdWB_register_Asm_16, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1LNdWB_register_Asm_32, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1LNdWB_register_Asm_8, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNdAsm_16, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNdAsm_32, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNdAsm_8, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNdWB_fixed_Asm_16, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNdWB_fixed_Asm_32, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNdWB_fixed_Asm_8, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNdWB_register_Asm_16, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNdWB_register_Asm_32, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNdWB_register_Asm_8, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNqAsm_16, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNqAsm_32, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNqWB_fixed_Asm_16, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNqWB_fixed_Asm_32, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNqWB_register_Asm_16, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNqWB_register_Asm_32, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNdAsm_16, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNdAsm_32, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNdAsm_8, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNdWB_fixed_Asm_16, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNdWB_fixed_Asm_32, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNdWB_fixed_Asm_8, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNdWB_register_Asm_16, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNdWB_register_Asm_32, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNdWB_register_Asm_8, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNqAsm_16, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNqAsm_32, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNqWB_fixed_Asm_16, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNqWB_fixed_Asm_32, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNqWB_register_Asm_16, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNqWB_register_Asm_32, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3dAsm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VST3dAsm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VST3dAsm_8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VST3dWB_fixed_Asm_16, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3dWB_fixed_Asm_32, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3dWB_fixed_Asm_8, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3dWB_register_Asm_16, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3dWB_register_Asm_32, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3dWB_register_Asm_8, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3qAsm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VST3qAsm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VST3qAsm_8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VST3qWB_fixed_Asm_16, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3qWB_fixed_Asm_32, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3qWB_fixed_Asm_8, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3qWB_register_Asm_16, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3qWB_register_Asm_32, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3qWB_register_Asm_8, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNdAsm_16, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNdAsm_32, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNdAsm_8, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNdWB_fixed_Asm_16, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNdWB_fixed_Asm_32, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNdWB_fixed_Asm_8, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNdWB_register_Asm_16, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNdWB_register_Asm_32, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNdWB_register_Asm_8, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNqAsm_16, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNqAsm_32, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNqWB_fixed_Asm_16, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNqWB_fixed_Asm_32, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNqWB_register_Asm_16, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNqWB_register_Asm_32, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4dAsm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VST4dAsm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VST4dAsm_8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VST4dWB_fixed_Asm_16, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4dWB_fixed_Asm_32, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4dWB_fixed_Asm_8, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4dWB_register_Asm_16, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4dWB_register_Asm_32, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4dWB_register_Asm_8, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4qAsm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VST4qAsm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VST4qAsm_8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VST4qWB_fixed_Asm_16, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4qWB_fixed_Asm_32, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4qWB_fixed_Asm_8, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4qWB_register_Asm_16, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4qWB_register_Asm_32, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4qWB_register_Asm_8, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDRBpcrel, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRConstPool, + ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDRHpcrel, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSBpcrel, + ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDRSHpcrel, + ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDRpcrel, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2MOVSsi, ARM_INS_MOVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2MOVSsr, ARM_INS_MOVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2MOVsi, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2MOVsr, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_tLDRConstPool, + ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_ADCri, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ADCrr, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ADCrsi, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ADCrsr, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ADDri, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ADDrr, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ADDrsi, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ADDrsr, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ADR, ARM_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_AESD, ARM_INS_AESD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif + }, + + { ARM_AESE, ARM_INS_AESE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif + }, + + { ARM_AESIMC, ARM_INS_AESIMC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif + }, + + { ARM_AESMC, ARM_INS_AESMC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif + }, + + { ARM_ANDri, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ANDrr, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ANDrsi, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ANDrsr, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_BFC, ARM_INS_BFC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif + }, + + { ARM_BFI, ARM_INS_BFI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif + }, + + { ARM_BICri, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_BICrr, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_BICrsi, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_BICrsr, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_BKPT, ARM_INS_BKPT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_BL, + ARM_INS_BL, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, + { ARM_REG_LR, ARM_REG_PC, 0 }, + { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, + 1, + 0 +#endif + }, + + { ARM_BLX, + ARM_INS_BLX, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, + { ARM_REG_LR, ARM_REG_PC, 0 }, + { ARM_GRP_CALL, ARM_GRP_V5T, 0 }, + 0, + 1 +#endif + }, + + { ARM_BLX_pred, + ARM_INS_BLX, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, + { ARM_REG_LR, ARM_REG_PC, 0 }, + { ARM_GRP_CALL, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, + 0, + 1 +#endif + }, + + { ARM_BLXi, + ARM_INS_BLX, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, + { ARM_REG_LR, ARM_REG_PC, 0 }, + { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, ARM_GRP_V5T, + 0 }, + 1, + 0 +#endif + }, + + { ARM_BL_pred, + ARM_INS_BL, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, + { ARM_REG_LR, ARM_REG_PC, 0 }, + { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, + 1, + 0 +#endif + }, + + { ARM_BX, ARM_INS_BX, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 +#endif + }, + + { ARM_BXJ, ARM_INS_BXJ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, 0 }, 0, 1 +#endif + }, + + { ARM_BX_RET, ARM_INS_BX, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 +#endif + }, + + { ARM_BX_pred, ARM_INS_BX, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 +#endif + }, + + { ARM_Bcc, + ARM_INS_B, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, + { ARM_REG_PC, 0 }, + { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, + 1, + 0 +#endif + }, + + { ARM_CDP, ARM_INS_CDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_CDP2, ARM_INS_CDP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_CLREX, ARM_INS_CLREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 +#endif + }, + + { ARM_CLZ, ARM_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0 +#endif + }, + + { ARM_CMNri, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_CMNzrr, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_CMNzrsi, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_CMNzrsr, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_CMPri, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_CMPrr, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_CMPrsi, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_CMPrsr, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_CPS1p, ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_CPS2p, ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_CPS3p, ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_CRC32B, + ARM_INS_CRC32B, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, + 0, + 0 +#endif + }, + + { ARM_CRC32CB, + ARM_INS_CRC32CB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, + 0, + 0 +#endif + }, + + { ARM_CRC32CH, + ARM_INS_CRC32CH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, + 0, + 0 +#endif + }, + + { ARM_CRC32CW, + ARM_INS_CRC32CW, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, + 0, + 0 +#endif + }, + + { ARM_CRC32H, + ARM_INS_CRC32H, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, + 0, + 0 +#endif + }, + + { ARM_CRC32W, + ARM_INS_CRC32W, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, + 0, + 0 +#endif + }, + + { ARM_DBG, ARM_INS_DBG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 +#endif + }, + + { ARM_DMB, ARM_INS_DMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 +#endif + }, + + { ARM_DSB, ARM_INS_DSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 +#endif + }, + + { ARM_EORri, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_EORrr, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_EORrsi, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_EORrsr, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ERET, + ARM_INS_ERET, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_PC, 0 }, + { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, + 0, + 0 +#endif + }, + + { ARM_FCONSTD, ARM_INS_FCONSTD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP3, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_FCONSTH, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_FCONSTS, ARM_INS_FCONSTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP3, 0 }, 0, 0 +#endif + }, + + { ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_FLDMXIA, ARM_INS_FLDMIAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_FMSTAT, + ARM_INS_FMSTAT, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR_NZCV, 0 }, + { ARM_REG_CPSR, 0 }, + { ARM_GRP_VFP2, 0 }, + 0, + 0 +#endif + }, + + { ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_FSTMXIA, ARM_INS_FSTMIAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_HINT, ARM_INS_HINT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_HLT, ARM_INS_HLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_HVC, ARM_INS_HVC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 +#endif + }, + + { ARM_ISB, ARM_INS_ISB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 +#endif + }, + + { ARM_LDA, ARM_INS_LDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_LDAB, ARM_INS_LDAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_LDAEX, ARM_INS_LDAEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_LDAEXB, ARM_INS_LDAEXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_LDAEXD, ARM_INS_LDAEXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_LDAEXH, ARM_INS_LDAEXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_LDAH, ARM_INS_LDAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_LDC2L_OFFSET, + ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, 0 }, + 0, + 0 +#endif + }, + + { ARM_LDC2L_OPTION, + ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, 0 }, + 0, + 0 +#endif + }, + + { ARM_LDC2L_POST, ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_LDC2L_PRE, ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_LDC2_OFFSET, ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_LDC2_OPTION, ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_LDC2_POST, ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_LDC2_PRE, ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_LDCL_OFFSET, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDCL_OPTION, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDCL_POST, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDCL_PRE, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDC_OFFSET, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDC_OPTION, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDC_POST, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDC_PRE, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDMDA, ARM_INS_LDMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDMDA_UPD, ARM_INS_LDMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDMDB, ARM_INS_LDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDMDB_UPD, ARM_INS_LDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDMIA, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDMIA_UPD, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDMIB, ARM_INS_LDMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDMIB_UPD, ARM_INS_LDMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRBT_POST_IMM, + ARM_INS_LDRBT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_LDRBT_POST_REG, + ARM_INS_LDRBT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_LDRB_POST_IMM, + ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_LDRB_POST_REG, + ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_LDRB_PRE_IMM, + ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_LDRB_PRE_REG, + ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_LDRBi12, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRBrs, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRD, ARM_INS_LDRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif + }, + + { ARM_LDRD_POST, ARM_INS_LDRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRD_PRE, ARM_INS_LDRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDREX, ARM_INS_LDREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDREXB, ARM_INS_LDREXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDREXD, ARM_INS_LDREXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDREXH, ARM_INS_LDREXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRH, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRHTi, ARM_INS_LDRHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRHTr, ARM_INS_LDRHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRH_POST, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRH_PRE, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRSB, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRSBTi, ARM_INS_LDRSBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRSBTr, ARM_INS_LDRSBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRSB_POST, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRSB_PRE, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRSH, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRSHTi, ARM_INS_LDRSHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRSHTr, ARM_INS_LDRSHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRSH_POST, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRSH_PRE, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRT_POST_IMM, + ARM_INS_LDRT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_LDRT_POST_REG, + ARM_INS_LDRT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_LDR_POST_IMM, + ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_LDR_POST_REG, + ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_LDR_PRE_IMM, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDR_PRE_REG, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRcp, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRi12, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_LDRrs, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MCR, ARM_INS_MCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MCR2, ARM_INS_MCR2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_MCRR, ARM_INS_MCRR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MCRR2, ARM_INS_MCRR2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, + 0 +#endif + }, + + { ARM_MLA, + ARM_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_MLS, + ARM_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V6T2, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_MOVPCLR, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MOVTi16, ARM_INS_MOVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif + }, + + { ARM_MOVi, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MOVi16, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif + }, + + { ARM_MOVr, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MOVr_TC, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MOVsi, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MOVsr, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MRC, ARM_INS_MRC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MRC2, ARM_INS_MRC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_MRRC, ARM_INS_MRRC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MRRC2, ARM_INS_MRRC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_MRS, ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MRSbanked, + ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, + 0, + 0 +#endif + }, + + { ARM_MRSsys, ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MSR, ARM_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MSRbanked, + ARM_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, + 0, + 0 +#endif + }, + + { ARM_MSRi, ARM_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MUL, ARM_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_MVNi, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MVNr, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MVNsi, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_MVNsr, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ORRri, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ORRrr, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ORRrsi, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_ORRrsr, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_PKHBT, ARM_INS_PKHBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_PKHTB, ARM_INS_PKHTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_PLDWi12, + ARM_INS_PLDW, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, + 0, + 0 +#endif + }, + + { ARM_PLDWrs, + ARM_INS_PLDW, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, + 0, + 0 +#endif + }, + + { ARM_PLDi12, ARM_INS_PLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_PLDrs, ARM_INS_PLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_PLIi12, ARM_INS_PLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 +#endif + }, + + { ARM_PLIrs, ARM_INS_PLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 +#endif + }, + + { ARM_QADD, ARM_INS_QADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_QADD16, ARM_INS_QADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_QADD8, ARM_INS_QADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_QASX, ARM_INS_QASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_QDADD, ARM_INS_QDADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_QDSUB, ARM_INS_QDSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_QSAX, ARM_INS_QSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_QSUB, ARM_INS_QSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_QSUB16, ARM_INS_QSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_QSUB8, ARM_INS_QSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RBIT, ARM_INS_RBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif + }, + + { ARM_REV, ARM_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_REV16, ARM_INS_REV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_REVSH, ARM_INS_REVSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_RFEDA, ARM_INS_RFEDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RFEDA_UPD, ARM_INS_RFEDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RFEDB, ARM_INS_RFEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RFEDB_UPD, ARM_INS_RFEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RFEIA, ARM_INS_RFEIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RFEIA_UPD, ARM_INS_RFEIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RFEIB, ARM_INS_RFEIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RFEIB_UPD, ARM_INS_RFEIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RSBri, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RSBrr, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RSBrsi, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RSBrsr, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RSCri, ARM_INS_RSC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RSCrr, ARM_INS_RSC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RSCrsi, ARM_INS_RSC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_RSCrsr, ARM_INS_RSC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SADD16, ARM_INS_SADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SADD8, ARM_INS_SADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SASX, ARM_INS_SASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SBCri, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SBCrr, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SBCrsi, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SBCrsr, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SBFX, ARM_INS_SBFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif + }, + + { ARM_SDIV, ARM_INS_SDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SEL, ARM_INS_SEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SETEND, ARM_INS_SETEND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SETPAN, ARM_INS_SETPAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_SHA1C, ARM_INS_SHA1C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif + }, + + { ARM_SHA1H, ARM_INS_SHA1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif + }, + + { ARM_SHA1M, ARM_INS_SHA1M, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif + }, + + { ARM_SHA1P, ARM_INS_SHA1P, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif + }, + + { ARM_SHA1SU0, ARM_INS_SHA1SU0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif + }, + + { ARM_SHA1SU1, ARM_INS_SHA1SU1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif + }, + + { ARM_SHA256H, ARM_INS_SHA256H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif + }, + + { ARM_SHA256H2, + ARM_INS_SHA256H2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, + 0, + 0 +#endif + }, + + { ARM_SHA256SU0, + ARM_INS_SHA256SU0, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, + 0, + 0 +#endif + }, + + { ARM_SHA256SU1, + ARM_INS_SHA256SU1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, + 0, + 0 +#endif + }, + + { ARM_SHADD16, ARM_INS_SHADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SHADD8, ARM_INS_SHADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SHASX, ARM_INS_SHASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SHSAX, ARM_INS_SHSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SHSUB16, ARM_INS_SHSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SHSUB8, ARM_INS_SHSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SMC, + ARM_INS_SMC, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0 }, + 0, + 0 +#endif + }, + + { ARM_SMLABB, + ARM_INS_SMLABB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_SMLABT, + ARM_INS_SMLABT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_SMLAD, ARM_INS_SMLAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMLADX, ARM_INS_SMLADX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMLAL, ARM_INS_SMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMLALBB, ARM_INS_SMLALBB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif + }, + + { ARM_SMLALBT, ARM_INS_SMLALBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif + }, + + { ARM_SMLALD, ARM_INS_SMLALD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMLALDX, ARM_INS_SMLALDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMLALTB, ARM_INS_SMLALTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif + }, + + { ARM_SMLALTT, ARM_INS_SMLALTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif + }, + + { ARM_SMLATB, + ARM_INS_SMLATB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_SMLATT, + ARM_INS_SMLATT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_SMLAWB, + ARM_INS_SMLAWB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_SMLAWT, + ARM_INS_SMLAWT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_SMLSD, ARM_INS_SMLSD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMLSDX, ARM_INS_SMLSDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMLSLD, ARM_INS_SMLSLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMLSLDX, ARM_INS_SMLSLDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMMLA, + ARM_INS_SMMLA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_SMMLAR, ARM_INS_SMMLAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMMLS, + ARM_INS_SMMLS, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_SMMLSR, ARM_INS_SMMLSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMMUL, ARM_INS_SMMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMMULR, ARM_INS_SMMULR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMUAD, ARM_INS_SMUAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMUADX, ARM_INS_SMUADX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMULBB, ARM_INS_SMULBB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif + }, + + { ARM_SMULBT, ARM_INS_SMULBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif + }, + + { ARM_SMULL, ARM_INS_SMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMULTB, ARM_INS_SMULTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif + }, + + { ARM_SMULTT, ARM_INS_SMULTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif + }, + + { ARM_SMULWB, ARM_INS_SMULWB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif + }, + + { ARM_SMULWT, ARM_INS_SMULWT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif + }, + + { ARM_SMUSD, ARM_INS_SMUSD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SMUSDX, ARM_INS_SMUSDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SRSDA, ARM_INS_SRSDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SRSDA_UPD, ARM_INS_SRSDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SRSDB, ARM_INS_SRSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SRSDB_UPD, ARM_INS_SRSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SRSIA, ARM_INS_SRSIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SRSIA_UPD, ARM_INS_SRSIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SRSIB, ARM_INS_SRSIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SRSIB_UPD, ARM_INS_SRSIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SSAT, ARM_INS_SSAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SSAT16, ARM_INS_SSAT16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SSAX, ARM_INS_SSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SSUB16, ARM_INS_SSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SSUB8, ARM_INS_SSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STC2L_OFFSET, + ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, 0 }, + 0, + 0 +#endif + }, + + { ARM_STC2L_OPTION, + ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, 0 }, + 0, + 0 +#endif + }, + + { ARM_STC2L_POST, ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_STC2L_PRE, ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_STC2_OFFSET, ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_STC2_OPTION, ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_STC2_POST, ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_STC2_PRE, ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_STCL_OFFSET, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STCL_OPTION, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STCL_POST, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STCL_PRE, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STC_OFFSET, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STC_OPTION, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STC_POST, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STC_PRE, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STL, ARM_INS_STL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_STLB, ARM_INS_STLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_STLEX, ARM_INS_STLEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_STLEXB, ARM_INS_STLEXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_STLEXD, ARM_INS_STLEXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_STLEXH, ARM_INS_STLEXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_STLH, ARM_INS_STLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_STMDA, ARM_INS_STMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STMDA_UPD, ARM_INS_STMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STMDB, ARM_INS_STMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STMDB_UPD, ARM_INS_STMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STMIA, ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STMIA_UPD, ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STMIB, ARM_INS_STMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STMIB_UPD, ARM_INS_STMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STRBT_POST_IMM, + ARM_INS_STRBT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_STRBT_POST_REG, + ARM_INS_STRBT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_STRB_POST_IMM, + ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_STRB_POST_REG, + ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_STRB_PRE_IMM, + ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_STRB_PRE_REG, + ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_STRBi12, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STRBrs, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STRD, ARM_INS_STRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif + }, + + { ARM_STRD_POST, ARM_INS_STRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STRD_PRE, ARM_INS_STRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STREX, ARM_INS_STREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STREXB, ARM_INS_STREXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STREXD, ARM_INS_STREXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STREXH, ARM_INS_STREXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STRH, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STRHTi, ARM_INS_STRHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STRHTr, ARM_INS_STRHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STRH_POST, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STRH_PRE, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STRT_POST_IMM, + ARM_INS_STRT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_STRT_POST_REG, + ARM_INS_STRT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_STR_POST_IMM, + ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_STR_POST_REG, + ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_STR_PRE_IMM, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STR_PRE_REG, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STRi12, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_STRrs, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SUBri, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SUBrr, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SUBrsi, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SUBrsr, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_SVC, + ARM_INS_SVC, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, + { ARM_REG_LR, 0 }, + { ARM_GRP_ARM, ARM_GRP_INT, 0 }, + 0, + 0 +#endif + }, + + { ARM_SWP, ARM_INS_SWP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_SWPB, ARM_INS_SWPB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_SXTAB, ARM_INS_SXTAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SXTAB16, ARM_INS_SXTAB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SXTAH, ARM_INS_SXTAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SXTB, ARM_INS_SXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SXTB16, ARM_INS_SXTB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_SXTH, ARM_INS_SXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_TEQri, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_TEQrr, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_TEQrsi, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_TEQrsr, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_TRAP, ARM_INS_TRAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_TRAPNaCl, ARM_INS_TRAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_TSB, ARM_INS_TSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_TSTri, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_TSTrr, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_TSTrsi, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_TSTrsr, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UADD16, ARM_INS_UADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UADD8, ARM_INS_UADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UASX, ARM_INS_UASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UBFX, ARM_INS_UBFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif + }, + + { ARM_UDF, ARM_INS_UDF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UDIV, ARM_INS_UDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UHADD16, ARM_INS_UHADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UHADD8, ARM_INS_UHADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UHASX, ARM_INS_UHASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UHSAX, ARM_INS_UHSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UHSUB16, ARM_INS_UHSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UHSUB8, ARM_INS_UHSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UMAAL, ARM_INS_UMAAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_UMLAL, ARM_INS_UMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_UMULL, ARM_INS_UMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_UQADD16, ARM_INS_UQADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UQADD8, ARM_INS_UQADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UQASX, ARM_INS_UQASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UQSAX, ARM_INS_UQSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UQSUB16, ARM_INS_UQSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UQSUB8, ARM_INS_UQSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_USAD8, ARM_INS_USAD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_USADA8, ARM_INS_USADA8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_USAT, ARM_INS_USAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_USAT16, ARM_INS_USAT16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_USAX, ARM_INS_USAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_USUB16, ARM_INS_USUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_USUB8, ARM_INS_USUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_UXTAB, ARM_INS_UXTAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_UXTAB16, ARM_INS_UXTAB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_UXTAH, ARM_INS_UXTAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_UXTB, ARM_INS_UXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_UXTB16, ARM_INS_UXTB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_UXTH, ARM_INS_UXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif + }, + + { ARM_VABALsv2i64, ARM_INS_VABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABALsv4i32, ARM_INS_VABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABALsv8i16, ARM_INS_VABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABALuv2i64, ARM_INS_VABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABALuv4i32, ARM_INS_VABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABALuv8i16, ARM_INS_VABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABAsv16i8, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABAsv2i32, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABAsv4i16, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABAsv4i32, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABAsv8i16, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABAsv8i8, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABAuv16i8, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABAuv2i32, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABAuv4i16, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABAuv4i32, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABAuv8i16, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABAuv8i8, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDLsv2i64, ARM_INS_VABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDLsv4i32, ARM_INS_VABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDLsv8i16, ARM_INS_VABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDLuv2i64, ARM_INS_VABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDLuv4i32, ARM_INS_VABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDLuv8i16, ARM_INS_VABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDfd, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDfq, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDhd, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VABDhq, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VABDsv16i8, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDsv2i32, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDsv4i16, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDsv4i32, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDsv8i16, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDsv8i8, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDuv16i8, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDuv2i32, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDuv4i16, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDuv4i32, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDuv8i16, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABDuv8i8, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABSD, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VABSH, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VABSS, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VABSfd, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABSfq, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABShd, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VABShq, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VABSv16i8, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABSv2i32, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABSv4i16, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABSv4i32, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABSv8i16, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VABSv8i8, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VACGEfd, ARM_INS_VACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VACGEfq, ARM_INS_VACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VACGEhd, ARM_INS_VACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VACGEhq, ARM_INS_VACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VACGTfd, ARM_INS_VACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VACGTfq, ARM_INS_VACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VACGThd, ARM_INS_VACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VACGThq, ARM_INS_VACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VADDD, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VADDH, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VADDHNv2i32, ARM_INS_VADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDHNv4i16, ARM_INS_VADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDHNv8i8, ARM_INS_VADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDLsv2i64, ARM_INS_VADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDLsv4i32, ARM_INS_VADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDLsv8i16, ARM_INS_VADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDLuv2i64, ARM_INS_VADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDLuv4i32, ARM_INS_VADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDLuv8i16, ARM_INS_VADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDS, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VADDWsv2i64, ARM_INS_VADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDWsv4i32, ARM_INS_VADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDWsv8i16, ARM_INS_VADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDWuv2i64, ARM_INS_VADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDWuv4i32, ARM_INS_VADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDWuv8i16, ARM_INS_VADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDfd, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDfq, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDhd, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VADDhq, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VADDv16i8, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDv1i64, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDv2i32, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDv2i64, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDv4i16, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDv4i32, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDv8i16, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VADDv8i8, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VANDd, ARM_INS_VAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VANDq, ARM_INS_VAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VBICd, ARM_INS_VBIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VBICiv2i32, ARM_INS_VBIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VBICiv4i16, ARM_INS_VBIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VBICiv4i32, ARM_INS_VBIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VBICiv8i16, ARM_INS_VBIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VBICq, ARM_INS_VBIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VBIFd, ARM_INS_VBIF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VBIFq, ARM_INS_VBIF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VBITd, ARM_INS_VBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VBITq, ARM_INS_VBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VBSLd, ARM_INS_VBSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VBSLq, ARM_INS_VBSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCADDv2f32, ARM_INS_VCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCADDv4f16, ARM_INS_VCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCADDv4f32, ARM_INS_VCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCADDv8f16, ARM_INS_VCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCEQfd, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQfq, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQhd, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCEQhq, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCEQv16i8, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQv2i32, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQv4i16, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQv4i32, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQv8i16, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQv8i8, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQzv16i8, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQzv2f32, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQzv2i32, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQzv4f16, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCEQzv4f32, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQzv4i16, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQzv4i32, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQzv8f16, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCEQzv8i16, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCEQzv8i8, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEfd, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEfq, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEhd, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCGEhq, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCGEsv16i8, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEsv2i32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEsv4i16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEsv4i32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEsv8i16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEsv8i8, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEuv16i8, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEuv2i32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEuv4i16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEuv4i32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEuv8i16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEuv8i8, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEzv16i8, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEzv2f32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEzv2i32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEzv4f16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCGEzv4f32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEzv4i16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEzv4i32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEzv8f16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCGEzv8i16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGEzv8i8, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTfd, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTfq, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGThd, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCGThq, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCGTsv16i8, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTsv2i32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTsv4i16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTsv4i32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTsv8i16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTsv8i8, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTuv16i8, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTuv2i32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTuv4i16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTuv4i32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTuv8i16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTuv8i8, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTzv16i8, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTzv2f32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTzv2i32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTzv4f16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCGTzv4f32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTzv4i16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTzv4i32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTzv8f16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCGTzv8i16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCGTzv8i8, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLEzv16i8, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLEzv2f32, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLEzv2i32, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLEzv4f16, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCLEzv4f32, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLEzv4i16, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLEzv4i32, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLEzv8f16, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCLEzv8i16, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLEzv8i8, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLSv16i8, ARM_INS_VCLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLSv2i32, ARM_INS_VCLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLSv4i16, ARM_INS_VCLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLSv4i32, ARM_INS_VCLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLSv8i16, ARM_INS_VCLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLSv8i8, ARM_INS_VCLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLTzv16i8, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLTzv2f32, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLTzv2i32, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLTzv4f16, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCLTzv4f32, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLTzv4i16, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLTzv4i32, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLTzv8f16, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCLTzv8i16, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLTzv8i8, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLZv16i8, ARM_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLZv2i32, ARM_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLZv4i16, ARM_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLZv4i32, ARM_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLZv8i16, ARM_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCLZv8i8, ARM_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCMLAv2f32, ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCMLAv2f32_indexed, + ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VCMLAv4f16, ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCMLAv4f16_indexed, + ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VCMLAv4f32, ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCMLAv4f32_indexed, + ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VCMLAv8f16, ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCMLAv8f16_indexed, + ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VCMPD, + ARM_INS_VCMP, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_FPSCR_NZCV, 0 }, + { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCMPED, + ARM_INS_VCMPE, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_FPSCR_NZCV, 0 }, + { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCMPEH, ARM_INS_VCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCMPES, + ARM_INS_VCMPE, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_FPSCR_NZCV, 0 }, + { ARM_GRP_VFP2, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCMPEZD, + ARM_INS_VCMPE, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_FPSCR_NZCV, 0 }, + { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCMPEZH, ARM_INS_VCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCMPEZS, + ARM_INS_VCMPE, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_FPSCR_NZCV, 0 }, + { ARM_GRP_VFP2, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCMPH, ARM_INS_VCMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCMPS, + ARM_INS_VCMP, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_FPSCR_NZCV, 0 }, + { ARM_GRP_VFP2, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCMPZD, + ARM_INS_VCMP, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_FPSCR_NZCV, 0 }, + { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCMPZH, ARM_INS_VCMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCMPZS, + ARM_INS_VCMP, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_FPSCR_NZCV, 0 }, + { ARM_GRP_VFP2, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCNTd, ARM_INS_VCNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCNTq, ARM_INS_VCNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTANSDf, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTANSDh, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTANSQf, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTANSQh, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTANUDf, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTANUDh, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTANUQf, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTANUQh, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTASD, + ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCVTASH, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTASS, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTAUD, + ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCVTAUH, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTAUS, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTBDH, + ARM_INS_VCVTB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCVTBHD, + ARM_INS_VCVTB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCVTBHS, ARM_INS_VCVTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTBSH, ARM_INS_VCVTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTDS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTMNSDf, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTMNSDh, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTMNSQf, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTMNSQh, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTMNUDf, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTMNUDh, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTMNUQf, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTMNUQh, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTMSD, + ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCVTMSH, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTMSS, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTMUD, + ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCVTMUH, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTMUS, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTNNSDf, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTNNSDh, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTNNSQf, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTNNSQh, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTNNUDf, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTNNUDh, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTNNUQf, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTNNUQh, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTNSD, + ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCVTNSH, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTNSS, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTNUD, + ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCVTNUH, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTNUS, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTPNSDf, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTPNSDh, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTPNSQf, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTPNSQh, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTPNUDf, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTPNUDh, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTPNUQf, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTPNUQh, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTPSD, + ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCVTPSH, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTPSS, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTPUD, + ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCVTPUH, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTPUS, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTSD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTTDH, + ARM_INS_VCVTT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCVTTHD, + ARM_INS_VCVTT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VCVTTHS, ARM_INS_VCVTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTTSH, ARM_INS_VCVTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTf2h, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTf2sd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTf2sq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTf2ud, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTf2uq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTf2xsd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTf2xsq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTf2xud, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTf2xuq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTh2f, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTh2sd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTh2sq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTh2ud, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTh2uq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTh2xsd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTh2xsq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTh2xud, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTh2xuq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTs2fd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTs2fq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTs2hd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTs2hq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTu2fd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTu2fq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTu2hd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTu2hq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTxs2fd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTxs2fq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTxs2hd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTxs2hq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTxu2fd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTxu2fq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VCVTxu2hd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VCVTxu2hq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VDIVD, ARM_INS_VDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VDIVH, ARM_INS_VDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VDIVS, ARM_INS_VDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VDUP16d, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VDUP16q, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VDUP32d, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VDUP32q, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VDUP8d, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VDUP8q, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VDUPLN16d, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VDUPLN16q, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VDUPLN32d, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VDUPLN32q, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VDUPLN8d, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VDUPLN8q, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VEORd, ARM_INS_VEOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VEORq, ARM_INS_VEOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VEXTd16, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VEXTd32, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VEXTd8, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VEXTq16, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VEXTq32, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VEXTq64, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VEXTq8, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VFMAD, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VFMAH, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VFMAS, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 +#endif + }, + + { ARM_VFMAfd, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 +#endif + }, + + { ARM_VFMAfq, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 +#endif + }, + + { ARM_VFMAhd, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VFMAhq, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VFMSD, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VFMSH, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VFMSS, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 +#endif + }, + + { ARM_VFMSfd, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 +#endif + }, + + { ARM_VFMSfq, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 +#endif + }, + + { ARM_VFMShd, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VFMShq, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VFNMAD, ARM_INS_VFNMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VFNMAH, ARM_INS_VFNMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VFNMAS, ARM_INS_VFNMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 +#endif + }, + + { ARM_VFNMSD, ARM_INS_VFNMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VFNMSH, ARM_INS_VFNMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VFNMSS, ARM_INS_VFNMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 +#endif + }, + + { ARM_VGETLNi32, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VGETLNs16, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VGETLNs8, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VGETLNu16, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VGETLNu8, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHADDsv16i8, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHADDsv2i32, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHADDsv4i16, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHADDsv4i32, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHADDsv8i16, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHADDsv8i8, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHADDuv16i8, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHADDuv2i32, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHADDuv4i16, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHADDuv4i32, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHADDuv8i16, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHADDuv8i8, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHSUBsv16i8, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHSUBsv2i32, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHSUBsv4i16, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHSUBsv4i32, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHSUBsv8i16, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHSUBsv8i8, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHSUBuv16i8, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHSUBuv2i32, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHSUBuv4i16, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHSUBuv4i32, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHSUBuv8i16, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VHSUBuv8i8, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VINSH, ARM_INS_VINS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VJCVT, ARM_INS_VJCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLD1DUPd16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1DUPd16wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1DUPd16wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1DUPd32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1DUPd32wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1DUPd32wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1DUPd8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1DUPd8wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1DUPd8wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1DUPq16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1DUPq16wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1DUPq16wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1DUPq32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1DUPq32wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1DUPq32wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1DUPq8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1DUPq8wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1DUPq8wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1LNd16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1LNd16_UPD, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1LNd32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1LNd32_UPD, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1LNd8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1LNd8_UPD, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1d16Q, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1d16Qwb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d16Qwb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d16T, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1d16Twb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d16Twb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d16wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d16wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1d32Q, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1d32Qwb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d32Qwb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d32T, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1d32Twb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d32Twb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d32wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d32wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d64, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1d64Q, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1d64Qwb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d64Qwb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d64T, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1d64Twb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d64Twb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d64wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d64wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1d8Q, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1d8Qwb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d8Qwb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d8T, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1d8Twb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d8Twb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d8wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1d8wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1q16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1q16wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1q16wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1q32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1q32wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1q32wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1q64, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1q64wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1q64wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1q8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD1q8wb_fixed, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD1q8wb_register, + ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2DUPd16wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd16wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd16x2, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd16x2wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd16x2wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2DUPd32wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd32wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd32x2, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd32x2wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd32x2wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2DUPd8wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd8wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd8x2, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2DUPd8x2wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2DUPd8x2wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNd16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2LNd16_UPD, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNd32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2LNd32_UPD, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNd8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2LNd8_UPD, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNq16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2LNq16_UPD, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2LNq32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2LNq32_UPD, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2b16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2b16wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2b16wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2b32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2b32wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2b32wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2b8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2b8wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2b8wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2d16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2d16wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2d16wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2d32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2d32wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2d32wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2d8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2d8wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2d8wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2q16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2q16wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2q16wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2q32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2q32wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2q32wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2q8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD2q8wb_fixed, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD2q8wb_register, + ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPd16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3DUPd16_UPD, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPd32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3DUPd32_UPD, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPd8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3DUPd8_UPD, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPq16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3DUPq16_UPD, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPq32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3DUPq32_UPD, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3DUPq8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3DUPq8_UPD, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNd16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3LNd16_UPD, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNd32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3LNd32_UPD, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNd8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3LNd8_UPD, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNq16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3LNq16_UPD, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3LNq32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3LNq32_UPD, + ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD3d16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3d16_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3d32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3d32_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3d8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3d8_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3q16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3q16_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3q32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3q32_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3q8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD3q8_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4DUPd16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4DUPd16_UPD, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPd32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4DUPd32_UPD, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPd8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4DUPd8_UPD, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPq16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4DUPq16_UPD, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPq32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4DUPq32_UPD, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4DUPq8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4DUPq8_UPD, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNd16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4LNd16_UPD, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNd32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4LNd32_UPD, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNd8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4LNd8_UPD, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNq16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4LNq16_UPD, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4LNq32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4LNq32_UPD, + ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VLD4d16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4d16_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4d32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4d32_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4d8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4d8_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4q16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4q16_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4q32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4q32_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4q8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLD4q8_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VLDMDDB_UPD, ARM_INS_VLDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VLDMDIA, ARM_INS_VLDMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VLDMDIA_UPD, ARM_INS_VLDMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VLDMSDB_UPD, ARM_INS_VLDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VLDMSIA, ARM_INS_VLDMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VLDMSIA_UPD, ARM_INS_VLDMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VLDRD, ARM_INS_VLDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VLDRH, ARM_INS_VLDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLDRS, ARM_INS_VLDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VLLDM, ARM_INS_VLLDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VLSTM, ARM_INS_VLSTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMAXNMD, + ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMAXNMH, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMAXNMNDf, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMAXNMNDh, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMAXNMNQf, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMAXNMNQh, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMAXNMS, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXfd, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXfq, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXhd, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMAXhq, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMAXsv16i8, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXsv2i32, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXsv4i16, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXsv4i32, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXsv8i16, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXsv8i8, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXuv16i8, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXuv2i32, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXuv4i16, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXuv4i32, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXuv8i16, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMAXuv8i8, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINNMD, + ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMINNMH, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMINNMNDf, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMINNMNDh, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMINNMNQf, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMINNMNQh, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMINNMS, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VMINfd, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINfq, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINhd, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMINhq, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMINsv16i8, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINsv2i32, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINsv4i16, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINsv4i32, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINsv8i16, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINsv8i8, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINuv16i8, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINuv2i32, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINuv4i16, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINuv4i32, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINuv8i16, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMINuv8i8, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAD, + ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMLAH, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMLALslsv2i32, + ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMLALslsv4i16, + ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMLALsluv2i32, + ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMLALsluv4i16, + ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMLALsv2i64, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLALsv4i32, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLALsv8i16, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLALuv2i64, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLALuv4i32, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLALuv8i16, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAS, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAfd, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAfq, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAhd, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMLAhq, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMLAslfd, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAslfq, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAslhd, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMLAslhq, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMLAslv2i32, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAslv4i16, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAslv4i32, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAslv8i16, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAv16i8, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAv2i32, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAv4i16, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAv4i32, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAv8i16, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLAv8i8, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSD, + ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMLSH, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMLSLslsv2i32, + ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMLSLslsv4i16, + ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMLSLsluv2i32, + ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMLSLsluv4i16, + ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMLSLsv2i64, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSLsv4i32, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSLsv8i16, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSLuv2i64, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSLuv4i32, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSLuv8i16, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSS, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSfd, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSfq, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif + }, + + { ARM_VMLShd, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMLShq, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMLSslfd, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSslfq, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSslhd, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMLSslhq, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMLSslv2i32, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSslv4i16, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSslv4i32, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSslv8i16, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSv16i8, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSv2i32, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSv4i16, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSv4i32, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSv8i16, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMLSv8i8, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVD, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVDRR, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVH, ARM_INS_VMOVX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMOVHR, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMOVLsv2i64, ARM_INS_VMOVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVLsv4i32, ARM_INS_VMOVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVLsv8i16, ARM_INS_VMOVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVLuv2i64, ARM_INS_VMOVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVLuv4i32, ARM_INS_VMOVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVLuv8i16, ARM_INS_VMOVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVNv2i32, ARM_INS_VMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVNv4i16, ARM_INS_VMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVNv8i8, ARM_INS_VMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVRH, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMOVRRD, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVRRS, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVRS, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVS, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVSR, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVSRR, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVv16i8, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVv1i64, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVv2f32, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVv2i32, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVv2i64, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVv4f32, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVv4i16, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVv4i32, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVv8i16, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMOVv8i8, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMRS, + ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, + { 0 }, + { ARM_GRP_VFP2, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMRS_FPEXC, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMRS_FPINST, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMRS_FPINST2, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMRS_FPSID, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMRS_MVFR0, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMRS_MVFR1, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMRS_MVFR2, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VMSR, ARM_INS_VMSR, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMSR_FPEXC, ARM_INS_VMSR, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMSR_FPINST, ARM_INS_VMSR, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMSR_FPINST2, + ARM_INS_VMSR, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_FPSCR, 0 }, + { ARM_GRP_VFP2, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMSR_FPSID, ARM_INS_VMSR, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMULD, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VMULH, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMULLp64, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif + }, + + { ARM_VMULLp8, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULLslsv2i32, + ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMULLslsv4i16, + ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMULLsluv2i32, + ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMULLsluv4i16, + ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VMULLsv2i64, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULLsv4i32, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULLsv8i16, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULLuv2i64, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULLuv4i32, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULLuv8i16, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULS, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VMULfd, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULfq, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULhd, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMULhq, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMULpd, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULpq, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULslfd, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULslfq, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULslhd, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMULslhq, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VMULslv2i32, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULslv4i16, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULslv4i32, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULslv8i16, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULv16i8, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULv2i32, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULv4i16, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULv4i32, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULv8i16, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMULv8i8, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMVNd, ARM_INS_VMVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMVNq, ARM_INS_VMVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMVNv2i32, ARM_INS_VMVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMVNv4i16, ARM_INS_VMVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMVNv4i32, ARM_INS_VMVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VMVNv8i16, ARM_INS_VMVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VNEGD, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VNEGH, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VNEGS, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VNEGf32q, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VNEGfd, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VNEGhd, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VNEGhq, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VNEGs16d, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VNEGs16q, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VNEGs32d, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VNEGs32q, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VNEGs8d, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VNEGs8q, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VNMLAD, + ARM_INS_VNMLA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, + 0, + 0 +#endif + }, + + { ARM_VNMLAH, ARM_INS_VNMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VNMLAS, ARM_INS_VNMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif + }, + + { ARM_VNMLSD, + ARM_INS_VNMLS, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, + 0, + 0 +#endif + }, + + { ARM_VNMLSH, ARM_INS_VNMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VNMLSS, ARM_INS_VNMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif + }, + + { ARM_VNMULD, ARM_INS_VNMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VNMULH, ARM_INS_VNMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VNMULS, ARM_INS_VNMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VORNd, ARM_INS_VORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VORNq, ARM_INS_VORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VORRd, ARM_INS_VORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VORRiv2i32, ARM_INS_VORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VORRiv4i16, ARM_INS_VORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VORRiv4i32, ARM_INS_VORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VORRiv8i16, ARM_INS_VORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VORRq, ARM_INS_VORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPADALsv16i8, + ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADALsv2i32, + ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADALsv4i16, + ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADALsv4i32, + ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADALsv8i16, + ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADALsv8i8, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPADALuv16i8, + ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADALuv2i32, + ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADALuv4i16, + ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADALuv4i32, + ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADALuv8i16, + ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADALuv8i8, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPADDLsv16i8, + ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADDLsv2i32, + ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADDLsv4i16, + ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADDLsv4i32, + ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADDLsv8i16, + ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADDLsv8i8, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPADDLuv16i8, + ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADDLuv2i32, + ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADDLuv4i16, + ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADDLuv4i32, + ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADDLuv8i16, + ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VPADDLuv8i8, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPADDf, ARM_INS_VPADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPADDh, ARM_INS_VPADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VPADDi16, ARM_INS_VPADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPADDi32, ARM_INS_VPADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPADDi8, ARM_INS_VPADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMAXf, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMAXh, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VPMAXs16, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMAXs32, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMAXs8, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMAXu16, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMAXu32, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMAXu8, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMINf, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMINh, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VPMINs16, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMINs32, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMINs8, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMINu16, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMINu32, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VPMINu8, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQABSv16i8, ARM_INS_VQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQABSv2i32, ARM_INS_VQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQABSv4i16, ARM_INS_VQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQABSv4i32, ARM_INS_VQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQABSv8i16, ARM_INS_VQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQABSv8i8, ARM_INS_VQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDsv16i8, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDsv1i64, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDsv2i32, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDsv2i64, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDsv4i16, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDsv4i32, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDsv8i16, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDsv8i8, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDuv16i8, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDuv1i64, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDuv2i32, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDuv2i64, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDuv4i16, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDuv4i32, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDuv8i16, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQADDuv8i8, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQDMLALslv2i32, + ARM_INS_VQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMLALslv4i16, + ARM_INS_VQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMLALv2i64, + ARM_INS_VQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMLALv4i32, + ARM_INS_VQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMLSLslv2i32, + ARM_INS_VQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMLSLslv4i16, + ARM_INS_VQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMLSLv2i64, + ARM_INS_VQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMLSLv4i32, + ARM_INS_VQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMULHslv2i32, + ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMULHslv4i16, + ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMULHslv4i32, + ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMULHslv8i16, + ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMULHv2i32, + ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMULHv4i16, + ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMULHv4i32, + ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMULHv8i16, + ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMULLslv2i32, + ARM_INS_VQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMULLslv4i16, + ARM_INS_VQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMULLv2i64, + ARM_INS_VQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQDMULLv4i32, + ARM_INS_VQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQMOVNsuv2i32, + ARM_INS_VQMOVUN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQMOVNsuv4i16, + ARM_INS_VQMOVUN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQMOVNsuv8i8, + ARM_INS_VQMOVUN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQMOVNsv2i32, + ARM_INS_VQMOVN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQMOVNsv4i16, + ARM_INS_VQMOVN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQMOVNsv8i8, ARM_INS_VQMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQMOVNuv2i32, + ARM_INS_VQMOVN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQMOVNuv4i16, + ARM_INS_VQMOVN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQMOVNuv8i8, ARM_INS_VQMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQNEGv16i8, ARM_INS_VQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQNEGv2i32, ARM_INS_VQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQNEGv4i16, ARM_INS_VQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQNEGv4i32, ARM_INS_VQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQNEGv8i16, ARM_INS_VQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQNEGv8i8, ARM_INS_VQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQRDMLAHslv2i32, + ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLAHslv4i16, + ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLAHslv4i32, + ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLAHslv8i16, + ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLAHv2i32, + ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLAHv4i16, + ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLAHv4i32, + ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLAHv8i16, + ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLSHslv2i32, + ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLSHslv4i16, + ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLSHslv4i32, + ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLSHslv8i16, + ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLSHv2i32, + ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLSHv4i16, + ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLSHv4i32, + ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMLSHv8i16, + ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMULHslv2i32, + ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMULHslv4i16, + ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMULHslv4i32, + ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMULHslv8i16, + ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMULHv2i32, + ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMULHv4i16, + ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMULHv4i32, + ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRDMULHv8i16, + ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLsv16i8, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLsv1i64, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLsv2i32, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLsv2i64, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLsv4i16, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLsv4i32, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLsv8i16, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLsv8i8, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQRSHLuv16i8, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLuv1i64, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLuv2i32, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLuv2i64, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLuv4i16, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLuv4i32, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLuv8i16, + ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHLuv8i8, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQRSHRNsv2i32, + ARM_INS_VQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHRNsv4i16, + ARM_INS_VQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHRNsv8i8, + ARM_INS_VQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHRNuv2i32, + ARM_INS_VQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHRNuv4i16, + ARM_INS_VQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHRNuv8i8, + ARM_INS_VQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHRUNv2i32, + ARM_INS_VQRSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHRUNv4i16, + ARM_INS_VQRSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQRSHRUNv8i8, + ARM_INS_VQRSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsiv16i8, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsiv1i64, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsiv2i32, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsiv2i64, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsiv4i16, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsiv4i32, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsiv8i16, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsiv8i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLsuv16i8, + ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsuv1i64, + ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsuv2i32, + ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsuv2i64, + ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsuv4i16, + ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsuv4i32, + ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsuv8i16, + ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLsuv8i8, ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLsv16i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLsv1i64, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLsv2i32, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLsv2i64, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLsv4i16, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLsv4i32, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLsv8i16, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLsv8i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLuiv16i8, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLuiv1i64, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLuiv2i32, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLuiv2i64, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLuiv4i16, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLuiv4i32, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLuiv8i16, + ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHLuiv8i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLuv16i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLuv1i64, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLuv2i32, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLuv2i64, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLuv4i16, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLuv4i32, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLuv8i16, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHLuv8i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHRNsv2i32, + ARM_INS_VQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHRNsv4i16, + ARM_INS_VQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHRNsv8i8, ARM_INS_VQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHRNuv2i32, + ARM_INS_VQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHRNuv4i16, + ARM_INS_VQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHRNuv8i8, ARM_INS_VQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSHRUNv2i32, + ARM_INS_VQSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHRUNv4i16, + ARM_INS_VQSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBsv16i8, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBsv1i64, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBsv2i32, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBsv2i64, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBsv4i16, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBsv4i32, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBsv8i16, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBsv8i8, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBuv16i8, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBuv1i64, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBuv2i32, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBuv2i64, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBuv4i16, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBuv4i32, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBuv8i16, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VQSUBuv8i8, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRADDHNv2i32, + ARM_INS_VRADDHN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRADDHNv4i16, + ARM_INS_VRADDHN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRADDHNv8i8, ARM_INS_VRADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRECPEd, ARM_INS_VRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRECPEfd, ARM_INS_VRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRECPEfq, ARM_INS_VRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRECPEhd, ARM_INS_VRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRECPEhq, ARM_INS_VRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRECPEq, ARM_INS_VRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRECPSfd, ARM_INS_VRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRECPSfq, ARM_INS_VRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRECPShd, ARM_INS_VRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRECPShq, ARM_INS_VRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VREV16d8, ARM_INS_VREV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VREV16q8, ARM_INS_VREV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VREV32d16, ARM_INS_VREV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VREV32d8, ARM_INS_VREV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VREV32q16, ARM_INS_VREV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VREV32q8, ARM_INS_VREV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VREV64d16, ARM_INS_VREV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VREV64d32, ARM_INS_VREV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VREV64d8, ARM_INS_VREV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VREV64q16, ARM_INS_VREV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VREV64q32, ARM_INS_VREV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VREV64q8, ARM_INS_VREV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRHADDsv16i8, + ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRHADDsv2i32, + ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRHADDsv4i16, + ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRHADDsv4i32, + ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRHADDsv8i16, + ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRHADDsv8i8, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRHADDuv16i8, + ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRHADDuv2i32, + ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRHADDuv4i16, + ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRHADDuv4i32, + ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRHADDuv8i16, + ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRHADDuv8i8, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRINTAD, + ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRINTAH, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTANDf, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTANDh, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTANQf, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTANQh, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTAS, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VRINTMD, + ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRINTMH, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTMNDf, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTMNDh, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTMNQf, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTMNQh, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTMS, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VRINTND, + ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRINTNH, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTNNDf, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTNNDh, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTNNQf, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTNNQh, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTNS, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VRINTPD, + ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRINTPH, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTPNDf, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTPNDh, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTPNQf, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTPNQh, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTPS, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VRINTRD, + ARM_INS_VRINTR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRINTRH, ARM_INS_VRINTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTRS, ARM_INS_VRINTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VRINTXD, + ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRINTXH, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTXNDf, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTXNDh, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTXNQf, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTXNQh, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTXS, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VRINTZD, + ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRINTZH, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTZNDf, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTZNDh, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTZNQf, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTZNQh, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRINTZS, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLsv16i8, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLsv1i64, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLsv2i32, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLsv2i64, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLsv4i16, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLsv4i32, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLsv8i16, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLsv8i8, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLuv16i8, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLuv1i64, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLuv2i32, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLuv2i64, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLuv4i16, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLuv4i32, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLuv8i16, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHLuv8i8, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRNv2i32, ARM_INS_VRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRNv4i16, ARM_INS_VRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRNv8i8, ARM_INS_VRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRsv16i8, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRsv1i64, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRsv2i32, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRsv2i64, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRsv4i16, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRsv4i32, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRsv8i16, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRsv8i8, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRuv16i8, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRuv1i64, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRuv2i32, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRuv2i64, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRuv4i16, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRuv4i32, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRuv8i16, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSHRuv8i8, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSQRTEd, ARM_INS_VRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSQRTEfd, ARM_INS_VRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSQRTEfq, ARM_INS_VRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSQRTEhd, ARM_INS_VRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRSQRTEhq, ARM_INS_VRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRSQRTEq, ARM_INS_VRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSQRTSfd, ARM_INS_VRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSQRTSfq, ARM_INS_VRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSQRTShd, ARM_INS_VRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRSQRTShq, ARM_INS_VRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAsv16i8, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAsv1i64, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAsv2i32, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAsv2i64, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAsv4i16, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAsv4i32, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAsv8i16, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAsv8i8, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAuv16i8, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAuv1i64, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAuv2i32, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAuv2i64, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAuv4i16, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAuv4i32, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAuv8i16, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSRAuv8i8, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VRSUBHNv2i32, + ARM_INS_VRSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRSUBHNv4i16, + ARM_INS_VRSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSDOTD, ARM_INS_VSDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSDOTDI, ARM_INS_VSDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSDOTQ, ARM_INS_VSDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSDOTQI, ARM_INS_VSDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSELEQD, + ARM_INS_VSELEQ, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VSELEQH, ARM_INS_VSELEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSELEQS, ARM_INS_VSELEQ, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VSELGED, + ARM_INS_VSELGE, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VSELGEH, ARM_INS_VSELGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSELGES, ARM_INS_VSELGE, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VSELGTD, + ARM_INS_VSELGT, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VSELGTH, ARM_INS_VSELGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSELGTS, ARM_INS_VSELGT, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VSELVSD, + ARM_INS_VSELVS, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, + { 0 }, + { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VSELVSH, ARM_INS_VSELVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSELVSS, ARM_INS_VSELVS, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif + }, + + { ARM_VSETLNi16, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSETLNi32, ARM_INS_FMDHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSETLNi8, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLLi16, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLLi32, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLLi8, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLLsv2i64, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLLsv4i32, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLLsv8i16, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLLuv2i64, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLLuv4i32, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLLuv8i16, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLiv16i8, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLiv1i64, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLiv2i32, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLiv2i64, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLiv4i16, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLiv4i32, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLiv8i16, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLiv8i8, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLsv16i8, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLsv1i64, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLsv2i32, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLsv2i64, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLsv4i16, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLsv4i32, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLsv8i16, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLsv8i8, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLuv16i8, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLuv1i64, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLuv2i32, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLuv2i64, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLuv4i16, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLuv4i32, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLuv8i16, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHLuv8i8, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRNv2i32, ARM_INS_VSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRNv4i16, ARM_INS_VSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRNv8i8, ARM_INS_VSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRsv16i8, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRsv1i64, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRsv2i32, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRsv2i64, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRsv4i16, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRsv4i32, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRsv8i16, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRsv8i8, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRuv16i8, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRuv1i64, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRuv2i32, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRuv2i64, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRuv4i16, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRuv4i32, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRuv8i16, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHRuv8i8, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSHTOD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VSHTOH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSHTOS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSITOD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VSITOH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSITOS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSLIv16i8, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSLIv1i64, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSLIv2i32, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSLIv2i64, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSLIv4i16, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSLIv4i32, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSLIv8i16, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSLIv8i8, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSLTOD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VSLTOH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSLTOS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSQRTD, ARM_INS_VSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VSQRTH, ARM_INS_VSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSQRTS, ARM_INS_VSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAsv16i8, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAsv1i64, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAsv2i32, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAsv2i64, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAsv4i16, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAsv4i32, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAsv8i16, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAsv8i8, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAuv16i8, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAuv1i64, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAuv2i32, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAuv2i64, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAuv4i16, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAuv4i32, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAuv8i16, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRAuv8i8, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRIv16i8, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRIv1i64, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRIv2i32, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRIv2i64, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRIv4i16, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRIv4i32, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRIv8i16, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSRIv8i8, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1LNd16, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1LNd16_UPD, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1LNd32, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1LNd32_UPD, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1LNd8, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1LNd8_UPD, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d16, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1d16Q, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1d16Qwb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d16Qwb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d16T, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1d16Twb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d16Twb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d16wb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d16wb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d32, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1d32Q, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1d32Qwb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d32Qwb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d32T, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1d32Twb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d32Twb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d32wb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d32wb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d64, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1d64Q, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1d64Qwb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d64Qwb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d64T, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1d64Twb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d64Twb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d64wb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d64wb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d8, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1d8Q, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1d8Qwb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d8Qwb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d8T, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1d8Twb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d8Twb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d8wb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1d8wb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1q16, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1q16wb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1q16wb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1q32, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1q32wb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1q32wb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1q64, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1q64wb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1q64wb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1q8, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST1q8wb_fixed, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST1q8wb_register, + ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNd16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2LNd16_UPD, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNd32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2LNd32_UPD, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNd8, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2LNd8_UPD, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNq16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2LNq16_UPD, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2LNq32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2LNq32_UPD, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2b16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2b16wb_fixed, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2b16wb_register, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2b32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2b32wb_fixed, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2b32wb_register, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2b8, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2b8wb_fixed, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2b8wb_register, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2d16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2d16wb_fixed, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2d16wb_register, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2d32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2d32wb_fixed, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2d32wb_register, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2d8, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2d8wb_fixed, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2d8wb_register, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2q16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2q16wb_fixed, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2q16wb_register, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2q32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2q32wb_fixed, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2q32wb_register, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2q8, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST2q8wb_fixed, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST2q8wb_register, + ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNd16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3LNd16_UPD, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNd32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3LNd32_UPD, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNd8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3LNd8_UPD, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNq16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3LNq16_UPD, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3LNq32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3LNq32_UPD, + ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST3d16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3d16_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3d32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3d32_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3d8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3d8_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3q16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3q16_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3q32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3q32_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3q8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST3q8_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4LNd16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4LNd16_UPD, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNd32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4LNd32_UPD, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNd8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4LNd8_UPD, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNq16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4LNq16_UPD, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4LNq32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4LNq32_UPD, + ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_NEON, 0 }, + 0, + 0 +#endif + }, + + { ARM_VST4d16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4d16_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4d32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4d32_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4d8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4d8_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4q16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4q16_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4q32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4q32_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4q8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VST4q8_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSTMDDB_UPD, ARM_INS_VSTMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSTMDIA, ARM_INS_VSTMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSTMDIA_UPD, ARM_INS_VSTMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSTMSDB_UPD, ARM_INS_VSTMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSTMSIA, ARM_INS_VSTMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSTMSIA_UPD, ARM_INS_VSTMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSTRD, ARM_INS_VSTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSTRH, ARM_INS_VSTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSTRS, ARM_INS_VSTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBD, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBH, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSUBHNv2i32, ARM_INS_VSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBHNv4i16, ARM_INS_VSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBHNv8i8, ARM_INS_VSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBLsv2i64, ARM_INS_VSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBLsv4i32, ARM_INS_VSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBLsv8i16, ARM_INS_VSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBLuv2i64, ARM_INS_VSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBLuv4i32, ARM_INS_VSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBLuv8i16, ARM_INS_VSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBS, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBWsv2i64, ARM_INS_VSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBWsv4i32, ARM_INS_VSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBWsv8i16, ARM_INS_VSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBWuv2i64, ARM_INS_VSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBWuv4i32, ARM_INS_VSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBWuv8i16, ARM_INS_VSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBfd, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBfq, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBhd, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSUBhq, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VSUBv16i8, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBv1i64, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBv2i32, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBv2i64, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBv4i16, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBv4i32, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBv8i16, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSUBv8i8, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSWPd, ARM_INS_VSWP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VSWPq, ARM_INS_VSWP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTBL1, ARM_INS_VTBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTBL2, ARM_INS_VTBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTBL3, ARM_INS_VTBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTBL4, ARM_INS_VTBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTBX1, ARM_INS_VTBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTBX2, ARM_INS_VTBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTBX3, ARM_INS_VTBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTBX4, ARM_INS_VTBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTOSHD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VTOSHH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VTOSHS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VTOSIRD, + ARM_INS_VCVTR, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, + { 0 }, + { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VTOSIRH, ARM_INS_VCVTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VTOSIRS, ARM_INS_VCVTR, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VTOSIZD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VTOSIZH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VTOSIZS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VTOSLD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VTOSLH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VTOSLS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VTOUHD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VTOUHH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VTOUHS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VTOUIRD, + ARM_INS_VCVTR, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, + { 0 }, + { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, + 0, + 0 +#endif + }, + + { ARM_VTOUIRH, ARM_INS_VCVTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VTOUIRS, ARM_INS_VCVTR, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VTOUIZD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VTOUIZH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VTOUIZS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VTOULD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VTOULH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VTOULS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VTRNd16, ARM_INS_VTRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTRNd32, ARM_INS_VTRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTRNd8, ARM_INS_VTRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTRNq16, ARM_INS_VTRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTRNq32, ARM_INS_VTRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTRNq8, ARM_INS_VTRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTSTv16i8, ARM_INS_VTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTSTv2i32, ARM_INS_VTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTSTv4i16, ARM_INS_VTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTSTv4i32, ARM_INS_VTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTSTv8i16, ARM_INS_VTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VTSTv8i8, ARM_INS_VTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VUDOTD, ARM_INS_VUDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VUDOTDI, ARM_INS_VUDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VUDOTQ, ARM_INS_VUDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VUDOTQI, ARM_INS_VUDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VUHTOD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VUHTOH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VUHTOS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VUITOD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VUITOH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VUITOS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VULTOD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif + }, + + { ARM_VULTOH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_VULTOS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif + }, + + { ARM_VUZPd16, ARM_INS_VUZP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VUZPd8, ARM_INS_VUZP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VUZPq16, ARM_INS_VUZP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VUZPq32, ARM_INS_VUZP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VUZPq8, ARM_INS_VUZP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VZIPd16, ARM_INS_VZIP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VZIPd8, ARM_INS_VZIP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VZIPq16, ARM_INS_VZIP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VZIPq32, ARM_INS_VZIP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_VZIPq8, ARM_INS_VZIP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif + }, + + { ARM_sysLDMDA, ARM_INS_LDMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_sysLDMDA_UPD, + ARM_INS_LDMDA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_sysLDMDB, ARM_INS_LDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_sysLDMDB_UPD, + ARM_INS_LDMDB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_sysLDMIA, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_sysLDMIA_UPD, + ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_sysLDMIB, ARM_INS_LDMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_sysLDMIB_UPD, + ARM_INS_LDMIB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_sysSTMDA, ARM_INS_STMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_sysSTMDA_UPD, + ARM_INS_STMDA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_sysSTMDB, ARM_INS_STMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_sysSTMDB_UPD, + ARM_INS_STMDB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_sysSTMIA, ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_sysSTMIA_UPD, + ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_sysSTMIB, ARM_INS_STMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif + }, + + { ARM_sysSTMIB_UPD, + ARM_INS_STMIB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_ARM, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2ADCri, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ADCrr, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ADCrs, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ADDri, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ADDri12, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ADDrr, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ADDrs, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ADR, ARM_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ANDri, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ANDrr, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ANDrs, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ASRri, ARM_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ASRrr, ARM_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2B, ARM_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, + 1, 0 +#endif + }, + + { ARM_t2BFC, ARM_INS_BFC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2BFI, ARM_INS_BFI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2BICri, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2BICrr, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2BICrs, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2BXJ, + ARM_INS_BXJ, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, ARM_GRP_PREV8, 0 }, + 0, + 1 +#endif + }, + + { ARM_t2Bcc, ARM_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, + 1, 0 +#endif + }, + + { ARM_t2CDP, + ARM_INS_CDP, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2CDP2, + ARM_INS_CDP2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2CLREX, ARM_INS_CLREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 +#endif + }, + + { ARM_t2CLZ, ARM_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2CMNri, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2CMNzrr, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2CMNzrs, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2CMPri, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2CMPrr, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2CMPrs, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2CPS1p, + ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2CPS2p, + ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2CPS3p, + ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2CRC32B, + ARM_INS_CRC32B, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2CRC32CB, + ARM_INS_CRC32CB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2CRC32CH, + ARM_INS_CRC32CH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2CRC32CW, + ARM_INS_CRC32CW, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2CRC32H, + ARM_INS_CRC32H, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2CRC32W, + ARM_INS_CRC32W, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2DBG, ARM_INS_DBG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2DCPS1, ARM_INS_DCPS1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2DCPS2, ARM_INS_DCPS2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2DCPS3, ARM_INS_DCPS3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2DMB, ARM_INS_DMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, + 0 +#endif + }, + + { ARM_t2DSB, ARM_INS_DSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, + 0 +#endif + }, + + { ARM_t2EORri, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2EORrr, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2EORrs, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2HINT, ARM_INS_HINT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2HVC, + ARM_INS_HVC, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_VIRTUALIZATION, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2ISB, ARM_INS_ISB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, + 0 +#endif + }, + + { ARM_t2IT, + ARM_INS_IT, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_ITSTATE, 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDA, ARM_INS_LDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDAB, ARM_INS_LDAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDAEX, ARM_INS_LDAEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDAEXB, ARM_INS_LDAEXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDAEXD, ARM_INS_LDAEXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDAEXH, ARM_INS_LDAEXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDAH, ARM_INS_LDAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDC2L_OFFSET, + ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDC2L_OPTION, + ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDC2L_POST, + ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDC2L_PRE, + ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDC2_OFFSET, + ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDC2_OPTION, + ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDC2_POST, + ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDC2_PRE, + ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDCL_OFFSET, + ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDCL_OPTION, + ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDCL_POST, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDCL_PRE, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDC_OFFSET, + ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDC_OPTION, + ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDC_POST, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDC_PRE, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDMDB, ARM_INS_LDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDMDB_UPD, ARM_INS_LDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDMIA, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDMIA_UPD, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRBT, ARM_INS_LDRBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRB_POST, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRB_PRE, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRBi12, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRBi8, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRBpci, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRBs, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRD_POST, ARM_INS_LDRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRD_PRE, ARM_INS_LDRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRDi8, ARM_INS_LDRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDREX, ARM_INS_LDREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDREXB, ARM_INS_LDREXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDREXD, + ARM_INS_LDREXD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDREXH, ARM_INS_LDREXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRHT, ARM_INS_LDRHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRH_POST, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRH_PRE, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRHi12, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRHi8, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRHpci, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRHs, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSBT, ARM_INS_LDRSBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSB_POST, + ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDRSB_PRE, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSBi12, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSBi8, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSBpci, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSBs, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSHT, ARM_INS_LDRSHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSH_POST, + ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2LDRSH_PRE, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSHi12, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSHi8, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSHpci, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRSHs, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRT, ARM_INS_LDRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDR_POST, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDR_PRE, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRi12, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRi8, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRpci, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LDRs, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LSLri, ARM_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LSLrr, ARM_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LSRri, ARM_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2LSRrr, ARM_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2MCR, ARM_INS_MCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2MCR2, + ARM_INS_MCR2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2MCRR, ARM_INS_MCRR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, + 0 +#endif + }, + + { ARM_t2MCRR2, + ARM_INS_MCRR2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2MLA, ARM_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif + }, + + { ARM_t2MLS, ARM_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif + }, + + { ARM_t2MOVTi16, ARM_INS_MOVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2MOVi, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2MOVi16, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2MOVr, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2MOVsra_flag, + ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_CPSR, 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2MOVsrl_flag, + ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_CPSR, 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2MRC, ARM_INS_MRC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2MRC2, + ARM_INS_MRC2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2MRRC, ARM_INS_MRRC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2MRRC2, ARM_INS_MRRC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 +#endif + }, + + { ARM_t2MRS_AR, + ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2MRS_M, ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 +#endif + }, + + { ARM_t2MRSbanked, + ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2MRSsys_AR, + ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2MSR_AR, + ARM_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2MSR_M, ARM_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 +#endif + }, + + { ARM_t2MSRbanked, + ARM_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2MUL, ARM_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2MVNi, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2MVNr, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2MVNs, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ORNri, ARM_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ORNrr, ARM_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ORNrs, ARM_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ORRri, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ORRrr, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2ORRrs, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2PKHBT, + ARM_INS_PKHBT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2PKHTB, + ARM_INS_PKHTB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2PLDWi12, + ARM_INS_PLDW, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2PLDWi8, + ARM_INS_PLDW, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2PLDWs, + ARM_INS_PLDW, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2PLDi12, ARM_INS_PLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2PLDi8, ARM_INS_PLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2PLDpci, ARM_INS_PLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2PLDs, ARM_INS_PLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2PLIi12, ARM_INS_PLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 +#endif + }, + + { ARM_t2PLIi8, ARM_INS_PLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 +#endif + }, + + { ARM_t2PLIpci, ARM_INS_PLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 +#endif + }, + + { ARM_t2PLIs, ARM_INS_PLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 +#endif + }, + + { ARM_t2QADD, ARM_INS_QADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, + 0 +#endif + }, + + { ARM_t2QADD16, + ARM_INS_QADD16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2QADD8, + ARM_INS_QADD8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2QASX, ARM_INS_QASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, + 0 +#endif + }, + + { ARM_t2QDADD, + ARM_INS_QDADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2QDSUB, + ARM_INS_QDSUB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2QSAX, ARM_INS_QSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, + 0 +#endif + }, + + { ARM_t2QSUB, ARM_INS_QSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, + 0 +#endif + }, + + { ARM_t2QSUB16, + ARM_INS_QSUB16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2QSUB8, + ARM_INS_QSUB8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2RBIT, ARM_INS_RBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2REV, ARM_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2REV16, ARM_INS_REV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2REVSH, ARM_INS_REVSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2RFEDB, + ARM_INS_RFEDB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2RFEDBW, + ARM_INS_RFEDB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2RFEIA, + ARM_INS_RFEIA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2RFEIAW, + ARM_INS_RFEIA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2RORri, ARM_INS_ROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2RORrr, ARM_INS_ROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2RRX, ARM_INS_RRX, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2RSBri, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2RSBrr, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2RSBrs, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SADD16, + ARM_INS_SADD16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SADD8, + ARM_INS_SADD8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SASX, ARM_INS_SASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, + 0 +#endif + }, + + { ARM_t2SBCri, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SBCrr, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SBCrs, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SBFX, ARM_INS_SBFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SDIV, ARM_INS_SDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SEL, ARM_INS_SEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif + }, + + { ARM_t2SETPAN, ARM_INS_SETPAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2SG, ARM_INS_SG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2SHADD16, + ARM_INS_SHADD16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SHADD8, + ARM_INS_SHADD8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SHASX, + ARM_INS_SHASX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SHSAX, + ARM_INS_SHSAX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SHSUB16, + ARM_INS_SHSUB16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SHSUB8, + ARM_INS_SHSUB8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMC, + ARM_INS_SMC, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_TRUSTZONE, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLABB, + ARM_INS_SMLABB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLABT, + ARM_INS_SMLABT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLAD, + ARM_INS_SMLAD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLADX, + ARM_INS_SMLADX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLAL, ARM_INS_SMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SMLALBB, + ARM_INS_SMLALBB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLALBT, + ARM_INS_SMLALBT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLALD, + ARM_INS_SMLALD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLALDX, + ARM_INS_SMLALDX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLALTB, + ARM_INS_SMLALTB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLALTT, + ARM_INS_SMLALTT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLATB, + ARM_INS_SMLATB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLATT, + ARM_INS_SMLATT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLAWB, + ARM_INS_SMLAWB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLAWT, + ARM_INS_SMLAWT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLSD, + ARM_INS_SMLSD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLSDX, + ARM_INS_SMLSDX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLSLD, + ARM_INS_SMLSLD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMLSLDX, + ARM_INS_SMLSLDX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMMLA, + ARM_INS_SMMLA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMMLAR, + ARM_INS_SMMLAR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMMLS, + ARM_INS_SMMLS, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMMLSR, + ARM_INS_SMMLSR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMMUL, + ARM_INS_SMMUL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMMULR, + ARM_INS_SMMULR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMUAD, + ARM_INS_SMUAD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMUADX, + ARM_INS_SMUADX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMULBB, + ARM_INS_SMULBB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMULBT, + ARM_INS_SMULBT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMULL, ARM_INS_SMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SMULTB, + ARM_INS_SMULTB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMULTT, + ARM_INS_SMULTT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMULWB, + ARM_INS_SMULWB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMULWT, + ARM_INS_SMULWT, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMUSD, + ARM_INS_SMUSD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SMUSDX, + ARM_INS_SMUSDX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SRSDB, + ARM_INS_SRSDB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SRSDB_UPD, + ARM_INS_SRSDB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SRSIA, + ARM_INS_SRSIA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SRSIA_UPD, + ARM_INS_SRSIA, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SSAT, ARM_INS_SSAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SSAT16, + ARM_INS_SSAT16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SSAX, ARM_INS_SSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, + 0 +#endif + }, + + { ARM_t2SSUB16, + ARM_INS_SSUB16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SSUB8, + ARM_INS_SSUB8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STC2L_OFFSET, + ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STC2L_OPTION, + ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STC2L_POST, + ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STC2L_PRE, + ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STC2_OFFSET, + ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STC2_OPTION, + ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STC2_POST, + ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STC2_PRE, + ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STCL_OFFSET, + ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STCL_OPTION, + ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STCL_POST, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STCL_PRE, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STC_OFFSET, + ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STC_OPTION, + ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STC_POST, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STC_PRE, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STL, ARM_INS_STL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2STLB, ARM_INS_STLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2STLEX, ARM_INS_STLEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2STLEXB, ARM_INS_STLEXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2STLEXD, ARM_INS_STLEXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2STLEXH, ARM_INS_STLEXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2STLH, ARM_INS_STLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_t2STMDB, ARM_INS_STMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STMDB_UPD, ARM_INS_STMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STMIA, ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STMIA_UPD, ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRBT, ARM_INS_STRBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRB_POST, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRB_PRE, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRBi12, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRBi8, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRBs, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRD_POST, ARM_INS_STRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRD_PRE, ARM_INS_STRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRDi8, ARM_INS_STRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STREX, ARM_INS_STREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STREXB, ARM_INS_STREXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STREXD, + ARM_INS_STREXD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2STREXH, ARM_INS_STREXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRHT, ARM_INS_STRHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRH_POST, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRH_PRE, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRHi12, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRHi8, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRHs, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRT, ARM_INS_STRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STR_POST, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STR_PRE, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRi12, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRi8, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2STRs, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SUBS_PC_LR, + ARM_INS_SUBS, +#ifndef CAPSTONE_DIET + { ARM_REG_SPSR, ARM_REG_LR, ARM_REG_PC, 0 }, + { ARM_REG_CPSR, ARM_REG_PC, 0 }, + { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SUBri, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SUBri12, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SUBrr, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SUBrs, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SXTAB, + ARM_INS_SXTAB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SXTAB16, + ARM_INS_SXTAB16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SXTAH, + ARM_INS_SXTAH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SXTB, ARM_INS_SXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2SXTB16, + ARM_INS_SXTB16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_T2EXTRACTPACK, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2SXTH, ARM_INS_SXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2TBB, ARM_INS_TBB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 +#endif + }, + + { ARM_t2TBH, ARM_INS_TBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 +#endif + }, + + { ARM_t2TEQri, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2TEQrr, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2TEQrs, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2TSB, ARM_INS_TSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2TSTri, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2TSTrr, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2TSTrs, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2TT, ARM_INS_TT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2TTA, ARM_INS_TTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2TTAT, ARM_INS_TTAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2TTT, ARM_INS_TTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_t2UADD16, + ARM_INS_UADD16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UADD8, + ARM_INS_UADD8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UASX, ARM_INS_UASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, + 0 +#endif + }, + + { ARM_t2UBFX, ARM_INS_UBFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2UDF, ARM_INS_UDF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2UDIV, ARM_INS_UDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2UHADD16, + ARM_INS_UHADD16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UHADD8, + ARM_INS_UHADD8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UHASX, + ARM_INS_UHASX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UHSAX, + ARM_INS_UHSAX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UHSUB16, + ARM_INS_UHSUB16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UHSUB8, + ARM_INS_UHSUB8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UMAAL, + ARM_INS_UMAAL, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UMLAL, ARM_INS_UMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2UMULL, ARM_INS_UMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2UQADD16, + ARM_INS_UQADD16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UQADD8, + ARM_INS_UQADD8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UQASX, + ARM_INS_UQASX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UQSAX, + ARM_INS_UQSAX, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UQSUB16, + ARM_INS_UQSUB16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UQSUB8, + ARM_INS_UQSUB8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2USAD8, + ARM_INS_USAD8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2USADA8, + ARM_INS_USADA8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2USAT, ARM_INS_USAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2USAT16, + ARM_INS_USAT16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2USAX, ARM_INS_USAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, + 0 +#endif + }, + + { ARM_t2USUB16, + ARM_INS_USUB16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2USUB8, + ARM_INS_USUB8, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UXTAB, + ARM_INS_UXTAB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UXTAB16, + ARM_INS_UXTAB16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UXTAH, + ARM_INS_UXTAH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UXTB, ARM_INS_UXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_t2UXTB16, + ARM_INS_UXTB16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, + 0, + 0 +#endif + }, + + { ARM_t2UXTH, ARM_INS_UXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif + }, + + { ARM_tADC, + ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tADDhirr, + ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tADDi3, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tADDi8, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tADDrSP, + ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tADDrSPi, + ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tADDrr, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tADDspi, + ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tADDspr, + ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tADR, ARM_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tAND, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tASRri, ARM_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tASRrr, ARM_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tB, + ARM_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 1, + 0 +#endif + }, + + { ARM_tBIC, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tBKPT, ARM_INS_BKPT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tBL, + ARM_INS_BL, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, + { ARM_REG_LR, ARM_REG_PC, 0 }, + { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_CALL, 0 }, + 1, + 0 +#endif + }, + + { ARM_tBLXNSr, ARM_INS_BLXNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_tBLXi, + ARM_INS_BLX, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, + { ARM_REG_LR, ARM_REG_PC, 0 }, + { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_V5T, + ARM_GRP_NOTMCLASS, ARM_GRP_CALL, 0 }, + 1, + 0 +#endif + }, + + { ARM_tBLXr, + ARM_INS_BLX, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, + { ARM_REG_LR, ARM_REG_PC, 0 }, + { ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_CALL, 0 }, + 0, + 1 +#endif + }, + + { ARM_tBX, ARM_INS_BX, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_THUMB, 0 }, 0, 1 +#endif + }, + + { ARM_tBXNS, ARM_INS_BXNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { ARM_tBcc, + ARM_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_PC, 0 }, + { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 1, + 0 +#endif + }, + + { ARM_tCBNZ, + ARM_INS_CBNZ, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, + 1, + 0 +#endif + }, + + { ARM_tCBZ, + ARM_INS_CBZ, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, + 1, + 0 +#endif + }, + + { ARM_tCMNz, + ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_CPSR, 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tCMPhir, + ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_CPSR, 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tCMPi8, + ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_CPSR, 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tCMPr, + ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_CPSR, 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tCPS, ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tEOR, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tHINT, ARM_INS_HINT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6M, 0 }, 0, 0 +#endif + }, + + { ARM_tHLT, ARM_INS_HLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif + }, + + { ARM_tLDMIA, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tLDRBi, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tLDRBr, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tLDRHi, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tLDRHr, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tLDRSB, + ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tLDRSH, + ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tLDRi, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tLDRpci, + ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tLDRr, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tLDRspi, + ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tLSLri, ARM_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tLSLrr, ARM_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tLSRri, ARM_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tLSRrr, ARM_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tMOVSr, + ARM_INS_MOVS, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_CPSR, 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tMOVi8, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tMOVr, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tMUL, ARM_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tMVN, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tORR, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tPOP, + ARM_INS_POP, +#ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, + { ARM_REG_SP, 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tPUSH, + ARM_INS_PUSH, +#ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, + { ARM_REG_SP, 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tREV, + ARM_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, + 0, + 0 +#endif + }, + + { ARM_tREV16, + ARM_INS_REV16, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, + 0, + 0 +#endif + }, + + { ARM_tREVSH, + ARM_INS_REVSH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, + 0, + 0 +#endif + }, + + { ARM_tROR, ARM_INS_ROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tRSB, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tSBC, + ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tSETEND, + ARM_INS_SETEND, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_V6, ARM_GRP_NOTMCLASS, 0 }, + 0, + 0 +#endif + }, + + { ARM_tSTMIA_UPD, + ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tSTRBi, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tSTRBr, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tSTRHi, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tSTRHr, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tSTRi, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tSTRr, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif + }, + + { ARM_tSTRspi, + ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tSUBi3, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tSUBi8, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tSUBrr, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, + 0 +#endif + }, + + { ARM_tSUBspi, + ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tSVC, + ARM_INS_SVC, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, + { ARM_REG_LR, 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_INT, 0 }, + 0, + 0 +#endif + }, + + { ARM_tSXTB, + ARM_INS_SXTB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, + 0, + 0 +#endif + }, + + { ARM_tSXTH, + ARM_INS_SXTH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, + 0, + 0 +#endif + }, + + { ARM_tTRAP, ARM_INS_TRAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 +#endif + }, + + { ARM_tTST, + ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, + { ARM_REG_CPSR, 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, + 0, + 0 +#endif + }, + + { ARM_tUDF, ARM_INS_UDF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 +#endif + }, + + { ARM_tUXTB, + ARM_INS_UXTB, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, + 0, + 0 +#endif + }, + + { ARM_tUXTH, + ARM_INS_UXTH, +#ifndef CAPSTONE_DIET + { 0 }, + { 0 }, + { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, + 0, + 0 +#endif + }, diff --git a/thirdparty/capstone/arch/ARM/ARMMappingInsnName.inc b/thirdparty/capstone/arch/ARM/ARMMappingInsnName.inc new file mode 100644 index 0000000..f7c81e4 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMMappingInsnName.inc @@ -0,0 +1,475 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +"adc", // ARM_INS_ADC, + "add", // ARM_INS_ADD, + "addw", // ARM_INS_ADDW, + "adr", // ARM_INS_ADR, + "aesd", // ARM_INS_AESD, + "aese", // ARM_INS_AESE, + "aesimc", // ARM_INS_AESIMC, + "aesmc", // ARM_INS_AESMC, + "and", // ARM_INS_AND, + "asr", // ARM_INS_ASR, + "b", // ARM_INS_B, + "bfc", // ARM_INS_BFC, + "bfi", // ARM_INS_BFI, + "bic", // ARM_INS_BIC, + "bkpt", // ARM_INS_BKPT, + "bl", // ARM_INS_BL, + "blx", // ARM_INS_BLX, + "blxns", // ARM_INS_BLXNS, + "bx", // ARM_INS_BX, + "bxj", // ARM_INS_BXJ, + "bxns", // ARM_INS_BXNS, + "cbnz", // ARM_INS_CBNZ, + "cbz", // ARM_INS_CBZ, + "cdp", // ARM_INS_CDP, + "cdp2", // ARM_INS_CDP2, + "clrex", // ARM_INS_CLREX, + "clz", // ARM_INS_CLZ, + "cmn", // ARM_INS_CMN, + "cmp", // ARM_INS_CMP, + "cps", // ARM_INS_CPS, + "crc32b", // ARM_INS_CRC32B, + "crc32cb", // ARM_INS_CRC32CB, + "crc32ch", // ARM_INS_CRC32CH, + "crc32cw", // ARM_INS_CRC32CW, + "crc32h", // ARM_INS_CRC32H, + "crc32w", // ARM_INS_CRC32W, + "csdb", // ARM_INS_CSDB, + "dbg", // ARM_INS_DBG, + "dcps1", // ARM_INS_DCPS1, + "dcps2", // ARM_INS_DCPS2, + "dcps3", // ARM_INS_DCPS3, + "dfb", // ARM_INS_DFB, + "dmb", // ARM_INS_DMB, + "dsb", // ARM_INS_DSB, + "eor", // ARM_INS_EOR, + "eret", // ARM_INS_ERET, + "esb", // ARM_INS_ESB, + "faddd", // ARM_INS_FADDD, + "fadds", // ARM_INS_FADDS, + "fcmpzd", // ARM_INS_FCMPZD, + "fcmpzs", // ARM_INS_FCMPZS, + "fconstd", // ARM_INS_FCONSTD, + "fconsts", // ARM_INS_FCONSTS, + "fldmdbx", // ARM_INS_FLDMDBX, + "fldmiax", // ARM_INS_FLDMIAX, + "fmdhr", // ARM_INS_FMDHR, + "fmdlr", // ARM_INS_FMDLR, + "fmstat", // ARM_INS_FMSTAT, + "fstmdbx", // ARM_INS_FSTMDBX, + "fstmiax", // ARM_INS_FSTMIAX, + "fsubd", // ARM_INS_FSUBD, + "fsubs", // ARM_INS_FSUBS, + "hint", // ARM_INS_HINT, + "hlt", // ARM_INS_HLT, + "hvc", // ARM_INS_HVC, + "isb", // ARM_INS_ISB, + "it", // ARM_INS_IT, + "lda", // ARM_INS_LDA, + "ldab", // ARM_INS_LDAB, + "ldaex", // ARM_INS_LDAEX, + "ldaexb", // ARM_INS_LDAEXB, + "ldaexd", // ARM_INS_LDAEXD, + "ldaexh", // ARM_INS_LDAEXH, + "ldah", // ARM_INS_LDAH, + "ldc", // ARM_INS_LDC, + "ldc2", // ARM_INS_LDC2, + "ldc2l", // ARM_INS_LDC2L, + "ldcl", // ARM_INS_LDCL, + "ldm", // ARM_INS_LDM, + "ldmda", // ARM_INS_LDMDA, + "ldmdb", // ARM_INS_LDMDB, + "ldmib", // ARM_INS_LDMIB, + "ldr", // ARM_INS_LDR, + "ldrb", // ARM_INS_LDRB, + "ldrbt", // ARM_INS_LDRBT, + "ldrd", // ARM_INS_LDRD, + "ldrex", // ARM_INS_LDREX, + "ldrexb", // ARM_INS_LDREXB, + "ldrexd", // ARM_INS_LDREXD, + "ldrexh", // ARM_INS_LDREXH, + "ldrh", // ARM_INS_LDRH, + "ldrht", // ARM_INS_LDRHT, + "ldrsb", // ARM_INS_LDRSB, + "ldrsbt", // ARM_INS_LDRSBT, + "ldrsh", // ARM_INS_LDRSH, + "ldrsht", // ARM_INS_LDRSHT, + "ldrt", // ARM_INS_LDRT, + "lsl", // ARM_INS_LSL, + "lsr", // ARM_INS_LSR, + "mcr", // ARM_INS_MCR, + "mcr2", // ARM_INS_MCR2, + "mcrr", // ARM_INS_MCRR, + "mcrr2", // ARM_INS_MCRR2, + "mla", // ARM_INS_MLA, + "mls", // ARM_INS_MLS, + "mov", // ARM_INS_MOV, + "movs", // ARM_INS_MOVS, + "movt", // ARM_INS_MOVT, + "movw", // ARM_INS_MOVW, + "mrc", // ARM_INS_MRC, + "mrc2", // ARM_INS_MRC2, + "mrrc", // ARM_INS_MRRC, + "mrrc2", // ARM_INS_MRRC2, + "mrs", // ARM_INS_MRS, + "msr", // ARM_INS_MSR, + "mul", // ARM_INS_MUL, + "mvn", // ARM_INS_MVN, + "neg", // ARM_INS_NEG, + "nop", // ARM_INS_NOP, + "orn", // ARM_INS_ORN, + "orr", // ARM_INS_ORR, + "pkhbt", // ARM_INS_PKHBT, + "pkhtb", // ARM_INS_PKHTB, + "pld", // ARM_INS_PLD, + "pldw", // ARM_INS_PLDW, + "pli", // ARM_INS_PLI, + "pop", // ARM_INS_POP, + "push", // ARM_INS_PUSH, + "qadd", // ARM_INS_QADD, + "qadd16", // ARM_INS_QADD16, + "qadd8", // ARM_INS_QADD8, + "qasx", // ARM_INS_QASX, + "qdadd", // ARM_INS_QDADD, + "qdsub", // ARM_INS_QDSUB, + "qsax", // ARM_INS_QSAX, + "qsub", // ARM_INS_QSUB, + "qsub16", // ARM_INS_QSUB16, + "qsub8", // ARM_INS_QSUB8, + "rbit", // ARM_INS_RBIT, + "rev", // ARM_INS_REV, + "rev16", // ARM_INS_REV16, + "revsh", // ARM_INS_REVSH, + "rfeda", // ARM_INS_RFEDA, + "rfedb", // ARM_INS_RFEDB, + "rfeia", // ARM_INS_RFEIA, + "rfeib", // ARM_INS_RFEIB, + "ror", // ARM_INS_ROR, + "rrx", // ARM_INS_RRX, + "rsb", // ARM_INS_RSB, + "rsc", // ARM_INS_RSC, + "sadd16", // ARM_INS_SADD16, + "sadd8", // ARM_INS_SADD8, + "sasx", // ARM_INS_SASX, + "sbc", // ARM_INS_SBC, + "sbfx", // ARM_INS_SBFX, + "sdiv", // ARM_INS_SDIV, + "sel", // ARM_INS_SEL, + "setend", // ARM_INS_SETEND, + "setpan", // ARM_INS_SETPAN, + "sev", // ARM_INS_SEV, + "sevl", // ARM_INS_SEVL, + "sg", // ARM_INS_SG, + "sha1c", // ARM_INS_SHA1C, + "sha1h", // ARM_INS_SHA1H, + "sha1m", // ARM_INS_SHA1M, + "sha1p", // ARM_INS_SHA1P, + "sha1su0", // ARM_INS_SHA1SU0, + "sha1su1", // ARM_INS_SHA1SU1, + "sha256h", // ARM_INS_SHA256H, + "sha256h2", // ARM_INS_SHA256H2, + "sha256su0", // ARM_INS_SHA256SU0, + "sha256su1", // ARM_INS_SHA256SU1, + "shadd16", // ARM_INS_SHADD16, + "shadd8", // ARM_INS_SHADD8, + "shasx", // ARM_INS_SHASX, + "shsax", // ARM_INS_SHSAX, + "shsub16", // ARM_INS_SHSUB16, + "shsub8", // ARM_INS_SHSUB8, + "smc", // ARM_INS_SMC, + "smlabb", // ARM_INS_SMLABB, + "smlabt", // ARM_INS_SMLABT, + "smlad", // ARM_INS_SMLAD, + "smladx", // ARM_INS_SMLADX, + "smlal", // ARM_INS_SMLAL, + "smlalbb", // ARM_INS_SMLALBB, + "smlalbt", // ARM_INS_SMLALBT, + "smlald", // ARM_INS_SMLALD, + "smlaldx", // ARM_INS_SMLALDX, + "smlaltb", // ARM_INS_SMLALTB, + "smlaltt", // ARM_INS_SMLALTT, + "smlatb", // ARM_INS_SMLATB, + "smlatt", // ARM_INS_SMLATT, + "smlawb", // ARM_INS_SMLAWB, + "smlawt", // ARM_INS_SMLAWT, + "smlsd", // ARM_INS_SMLSD, + "smlsdx", // ARM_INS_SMLSDX, + "smlsld", // ARM_INS_SMLSLD, + "smlsldx", // ARM_INS_SMLSLDX, + "smmla", // ARM_INS_SMMLA, + "smmlar", // ARM_INS_SMMLAR, + "smmls", // ARM_INS_SMMLS, + "smmlsr", // ARM_INS_SMMLSR, + "smmul", // ARM_INS_SMMUL, + "smmulr", // ARM_INS_SMMULR, + "smuad", // ARM_INS_SMUAD, + "smuadx", // ARM_INS_SMUADX, + "smulbb", // ARM_INS_SMULBB, + "smulbt", // ARM_INS_SMULBT, + "smull", // ARM_INS_SMULL, + "smultb", // ARM_INS_SMULTB, + "smultt", // ARM_INS_SMULTT, + "smulwb", // ARM_INS_SMULWB, + "smulwt", // ARM_INS_SMULWT, + "smusd", // ARM_INS_SMUSD, + "smusdx", // ARM_INS_SMUSDX, + "srsda", // ARM_INS_SRSDA, + "srsdb", // ARM_INS_SRSDB, + "srsia", // ARM_INS_SRSIA, + "srsib", // ARM_INS_SRSIB, + "ssat", // ARM_INS_SSAT, + "ssat16", // ARM_INS_SSAT16, + "ssax", // ARM_INS_SSAX, + "ssub16", // ARM_INS_SSUB16, + "ssub8", // ARM_INS_SSUB8, + "stc", // ARM_INS_STC, + "stc2", // ARM_INS_STC2, + "stc2l", // ARM_INS_STC2L, + "stcl", // ARM_INS_STCL, + "stl", // ARM_INS_STL, + "stlb", // ARM_INS_STLB, + "stlex", // ARM_INS_STLEX, + "stlexb", // ARM_INS_STLEXB, + "stlexd", // ARM_INS_STLEXD, + "stlexh", // ARM_INS_STLEXH, + "stlh", // ARM_INS_STLH, + "stm", // ARM_INS_STM, + "stmda", // ARM_INS_STMDA, + "stmdb", // ARM_INS_STMDB, + "stmib", // ARM_INS_STMIB, + "str", // ARM_INS_STR, + "strb", // ARM_INS_STRB, + "strbt", // ARM_INS_STRBT, + "strd", // ARM_INS_STRD, + "strex", // ARM_INS_STREX, + "strexb", // ARM_INS_STREXB, + "strexd", // ARM_INS_STREXD, + "strexh", // ARM_INS_STREXH, + "strh", // ARM_INS_STRH, + "strht", // ARM_INS_STRHT, + "strt", // ARM_INS_STRT, + "sub", // ARM_INS_SUB, + "subs", // ARM_INS_SUBS, + "subw", // ARM_INS_SUBW, + "svc", // ARM_INS_SVC, + "swp", // ARM_INS_SWP, + "swpb", // ARM_INS_SWPB, + "sxtab", // ARM_INS_SXTAB, + "sxtab16", // ARM_INS_SXTAB16, + "sxtah", // ARM_INS_SXTAH, + "sxtb", // ARM_INS_SXTB, + "sxtb16", // ARM_INS_SXTB16, + "sxth", // ARM_INS_SXTH, + "tbb", // ARM_INS_TBB, + "tbh", // ARM_INS_TBH, + "teq", // ARM_INS_TEQ, + "trap", // ARM_INS_TRAP, + "tsb", // ARM_INS_TSB, + "tst", // ARM_INS_TST, + "tt", // ARM_INS_TT, + "tta", // ARM_INS_TTA, + "ttat", // ARM_INS_TTAT, + "ttt", // ARM_INS_TTT, + "uadd16", // ARM_INS_UADD16, + "uadd8", // ARM_INS_UADD8, + "uasx", // ARM_INS_UASX, + "ubfx", // ARM_INS_UBFX, + "udf", // ARM_INS_UDF, + "udiv", // ARM_INS_UDIV, + "uhadd16", // ARM_INS_UHADD16, + "uhadd8", // ARM_INS_UHADD8, + "uhasx", // ARM_INS_UHASX, + "uhsax", // ARM_INS_UHSAX, + "uhsub16", // ARM_INS_UHSUB16, + "uhsub8", // ARM_INS_UHSUB8, + "umaal", // ARM_INS_UMAAL, + "umlal", // ARM_INS_UMLAL, + "umull", // ARM_INS_UMULL, + "uqadd16", // ARM_INS_UQADD16, + "uqadd8", // ARM_INS_UQADD8, + "uqasx", // ARM_INS_UQASX, + "uqsax", // ARM_INS_UQSAX, + "uqsub16", // ARM_INS_UQSUB16, + "uqsub8", // ARM_INS_UQSUB8, + "usad8", // ARM_INS_USAD8, + "usada8", // ARM_INS_USADA8, + "usat", // ARM_INS_USAT, + "usat16", // ARM_INS_USAT16, + "usax", // ARM_INS_USAX, + "usub16", // ARM_INS_USUB16, + "usub8", // ARM_INS_USUB8, + "uxtab", // ARM_INS_UXTAB, + "uxtab16", // ARM_INS_UXTAB16, + "uxtah", // ARM_INS_UXTAH, + "uxtb", // ARM_INS_UXTB, + "uxtb16", // ARM_INS_UXTB16, + "uxth", // ARM_INS_UXTH, + "vaba", // ARM_INS_VABA, + "vabal", // ARM_INS_VABAL, + "vabd", // ARM_INS_VABD, + "vabdl", // ARM_INS_VABDL, + "vabs", // ARM_INS_VABS, + "vacge", // ARM_INS_VACGE, + "vacgt", // ARM_INS_VACGT, + "vacle", // ARM_INS_VACLE, + "vaclt", // ARM_INS_VACLT, + "vadd", // ARM_INS_VADD, + "vaddhn", // ARM_INS_VADDHN, + "vaddl", // ARM_INS_VADDL, + "vaddw", // ARM_INS_VADDW, + "vand", // ARM_INS_VAND, + "vbic", // ARM_INS_VBIC, + "vbif", // ARM_INS_VBIF, + "vbit", // ARM_INS_VBIT, + "vbsl", // ARM_INS_VBSL, + "vcadd", // ARM_INS_VCADD, + "vceq", // ARM_INS_VCEQ, + "vcge", // ARM_INS_VCGE, + "vcgt", // ARM_INS_VCGT, + "vcle", // ARM_INS_VCLE, + "vcls", // ARM_INS_VCLS, + "vclt", // ARM_INS_VCLT, + "vclz", // ARM_INS_VCLZ, + "vcmla", // ARM_INS_VCMLA, + "vcmp", // ARM_INS_VCMP, + "vcmpe", // ARM_INS_VCMPE, + "vcnt", // ARM_INS_VCNT, + "vcvt", // ARM_INS_VCVT, + "vcvta", // ARM_INS_VCVTA, + "vcvtb", // ARM_INS_VCVTB, + "vcvtm", // ARM_INS_VCVTM, + "vcvtn", // ARM_INS_VCVTN, + "vcvtp", // ARM_INS_VCVTP, + "vcvtr", // ARM_INS_VCVTR, + "vcvtt", // ARM_INS_VCVTT, + "vdiv", // ARM_INS_VDIV, + "vdup", // ARM_INS_VDUP, + "veor", // ARM_INS_VEOR, + "vext", // ARM_INS_VEXT, + "vfma", // ARM_INS_VFMA, + "vfms", // ARM_INS_VFMS, + "vfnma", // ARM_INS_VFNMA, + "vfnms", // ARM_INS_VFNMS, + "vhadd", // ARM_INS_VHADD, + "vhsub", // ARM_INS_VHSUB, + "vins", // ARM_INS_VINS, + "vjcvt", // ARM_INS_VJCVT, + "vld1", // ARM_INS_VLD1, + "vld2", // ARM_INS_VLD2, + "vld3", // ARM_INS_VLD3, + "vld4", // ARM_INS_VLD4, + "vldmdb", // ARM_INS_VLDMDB, + "vldmia", // ARM_INS_VLDMIA, + "vldr", // ARM_INS_VLDR, + "vlldm", // ARM_INS_VLLDM, + "vlstm", // ARM_INS_VLSTM, + "vmax", // ARM_INS_VMAX, + "vmaxnm", // ARM_INS_VMAXNM, + "vmin", // ARM_INS_VMIN, + "vminnm", // ARM_INS_VMINNM, + "vmla", // ARM_INS_VMLA, + "vmlal", // ARM_INS_VMLAL, + "vmls", // ARM_INS_VMLS, + "vmlsl", // ARM_INS_VMLSL, + "vmov", // ARM_INS_VMOV, + "vmovl", // ARM_INS_VMOVL, + "vmovn", // ARM_INS_VMOVN, + "vmovx", // ARM_INS_VMOVX, + "vmrs", // ARM_INS_VMRS, + "vmsr", // ARM_INS_VMSR, + "vmul", // ARM_INS_VMUL, + "vmull", // ARM_INS_VMULL, + "vmvn", // ARM_INS_VMVN, + "vneg", // ARM_INS_VNEG, + "vnmla", // ARM_INS_VNMLA, + "vnmls", // ARM_INS_VNMLS, + "vnmul", // ARM_INS_VNMUL, + "vorn", // ARM_INS_VORN, + "vorr", // ARM_INS_VORR, + "vpadal", // ARM_INS_VPADAL, + "vpadd", // ARM_INS_VPADD, + "vpaddl", // ARM_INS_VPADDL, + "vpmax", // ARM_INS_VPMAX, + "vpmin", // ARM_INS_VPMIN, + "vpop", // ARM_INS_VPOP, + "vpush", // ARM_INS_VPUSH, + "vqabs", // ARM_INS_VQABS, + "vqadd", // ARM_INS_VQADD, + "vqdmlal", // ARM_INS_VQDMLAL, + "vqdmlsl", // ARM_INS_VQDMLSL, + "vqdmulh", // ARM_INS_VQDMULH, + "vqdmull", // ARM_INS_VQDMULL, + "vqmovn", // ARM_INS_VQMOVN, + "vqmovun", // ARM_INS_VQMOVUN, + "vqneg", // ARM_INS_VQNEG, + "vqrdmlah", // ARM_INS_VQRDMLAH, + "vqrdmlsh", // ARM_INS_VQRDMLSH, + "vqrdmulh", // ARM_INS_VQRDMULH, + "vqrshl", // ARM_INS_VQRSHL, + "vqrshrn", // ARM_INS_VQRSHRN, + "vqrshrun", // ARM_INS_VQRSHRUN, + "vqshl", // ARM_INS_VQSHL, + "vqshlu", // ARM_INS_VQSHLU, + "vqshrn", // ARM_INS_VQSHRN, + "vqshrun", // ARM_INS_VQSHRUN, + "vqsub", // ARM_INS_VQSUB, + "vraddhn", // ARM_INS_VRADDHN, + "vrecpe", // ARM_INS_VRECPE, + "vrecps", // ARM_INS_VRECPS, + "vrev16", // ARM_INS_VREV16, + "vrev32", // ARM_INS_VREV32, + "vrev64", // ARM_INS_VREV64, + "vrhadd", // ARM_INS_VRHADD, + "vrinta", // ARM_INS_VRINTA, + "vrintm", // ARM_INS_VRINTM, + "vrintn", // ARM_INS_VRINTN, + "vrintp", // ARM_INS_VRINTP, + "vrintr", // ARM_INS_VRINTR, + "vrintx", // ARM_INS_VRINTX, + "vrintz", // ARM_INS_VRINTZ, + "vrshl", // ARM_INS_VRSHL, + "vrshr", // ARM_INS_VRSHR, + "vrshrn", // ARM_INS_VRSHRN, + "vrsqrte", // ARM_INS_VRSQRTE, + "vrsqrts", // ARM_INS_VRSQRTS, + "vrsra", // ARM_INS_VRSRA, + "vrsubhn", // ARM_INS_VRSUBHN, + "vsdot", // ARM_INS_VSDOT, + "vseleq", // ARM_INS_VSELEQ, + "vselge", // ARM_INS_VSELGE, + "vselgt", // ARM_INS_VSELGT, + "vselvs", // ARM_INS_VSELVS, + "vshl", // ARM_INS_VSHL, + "vshll", // ARM_INS_VSHLL, + "vshr", // ARM_INS_VSHR, + "vshrn", // ARM_INS_VSHRN, + "vsli", // ARM_INS_VSLI, + "vsqrt", // ARM_INS_VSQRT, + "vsra", // ARM_INS_VSRA, + "vsri", // ARM_INS_VSRI, + "vst1", // ARM_INS_VST1, + "vst2", // ARM_INS_VST2, + "vst3", // ARM_INS_VST3, + "vst4", // ARM_INS_VST4, + "vstmdb", // ARM_INS_VSTMDB, + "vstmia", // ARM_INS_VSTMIA, + "vstr", // ARM_INS_VSTR, + "vsub", // ARM_INS_VSUB, + "vsubhn", // ARM_INS_VSUBHN, + "vsubl", // ARM_INS_VSUBL, + "vsubw", // ARM_INS_VSUBW, + "vswp", // ARM_INS_VSWP, + "vtbl", // ARM_INS_VTBL, + "vtbx", // ARM_INS_VTBX, + "vtrn", // ARM_INS_VTRN, + "vtst", // ARM_INS_VTST, + "vudot", // ARM_INS_VUDOT, + "vuzp", // ARM_INS_VUZP, + "vzip", // ARM_INS_VZIP, + "wfe", // ARM_INS_WFE, + "wfi", // ARM_INS_WFI, + "yield", // ARM_INS_YIELD, diff --git a/thirdparty/capstone/arch/ARM/ARMMappingInsnOp.inc b/thirdparty/capstone/arch/ARM/ARMMappingInsnOp.inc new file mode 100644 index 0000000..8daecd4 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMMappingInsnOp.inc @@ -0,0 +1,10739 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +{ /* ARM_ASRi, ARM_INS_ASR: asr */ + { 0 } +}, + + { /* ARM_ASRr, ARM_INS_ASR: asr */ + { 0 } + }, + + { /* ARM_ITasm, ARM_INS_IT: it */ + { 0 } + }, + + { /* ARM_LDRBT_POST, ARM_INS_LDRBT: ldrbt */ + { 0 } + }, + + { /* ARM_LDRConstPool, ARM_INS_LDR: ldr */ + { 0 } + }, + + { /* ARM_LDRT_POST, ARM_INS_LDRT: ldrt */ + { 0 } + }, + + { /* ARM_LSLi, ARM_INS_LSL: lsl */ + { 0 } + }, + + { /* ARM_LSLr, ARM_INS_LSL: lsl */ + { 0 } + }, + + { /* ARM_LSRi, ARM_INS_LSR: lsr */ + { 0 } + }, + + { /* ARM_LSRr, ARM_INS_LSR: lsr */ + { 0 } + }, + + { /* ARM_RORi, ARM_INS_ROR: ror */ + { 0 } + }, + + { /* ARM_RORr, ARM_INS_ROR: ror */ + { 0 } + }, + + { /* ARM_RRXi, ARM_INS_RRX: rrx */ + { 0 } + }, + + { /* ARM_STRBT_POST, ARM_INS_STRBT: strbt */ + { 0 } + }, + + { /* ARM_STRT_POST, ARM_INS_STRT: strt */ + { 0 } + }, + + { /* ARM_VLD1LNdAsm_16, ARM_INS_VLD1: vld1 */ + { 0 } + }, + + { /* ARM_VLD1LNdAsm_32, ARM_INS_VLD1: vld1 */ + { 0 } + }, + + { /* ARM_VLD1LNdAsm_8, ARM_INS_VLD1: vld1 */ + { 0 } + }, + + { /* ARM_VLD1LNdWB_fixed_Asm_16, ARM_INS_VLD1: vld1 */ + { 0 } + }, + + { /* ARM_VLD1LNdWB_fixed_Asm_32, ARM_INS_VLD1: vld1 */ + { 0 } + }, + + { /* ARM_VLD1LNdWB_fixed_Asm_8, ARM_INS_VLD1: vld1 */ + { 0 } + }, + + { /* ARM_VLD1LNdWB_register_Asm_16, ARM_INS_VLD1: vld1 */ + { 0 } + }, + + { /* ARM_VLD1LNdWB_register_Asm_32, ARM_INS_VLD1: vld1 */ + { 0 } + }, + + { /* ARM_VLD1LNdWB_register_Asm_8, ARM_INS_VLD1: vld1 */ + { 0 } + }, + + { /* ARM_VLD2LNdAsm_16, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNdAsm_32, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNdAsm_8, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNdWB_fixed_Asm_16, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNdWB_fixed_Asm_32, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNdWB_fixed_Asm_8, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNdWB_register_Asm_16, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNdWB_register_Asm_32, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNdWB_register_Asm_8, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNqAsm_16, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNqAsm_32, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNqWB_fixed_Asm_16, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNqWB_fixed_Asm_32, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNqWB_register_Asm_16, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD2LNqWB_register_Asm_32, ARM_INS_VLD2: vld2 */ + { 0 } + }, + + { /* ARM_VLD3DUPdAsm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPdAsm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPdAsm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPdWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPdWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPdWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPdWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPdWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPdWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPqAsm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPqAsm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPqAsm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPqWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPqWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPqWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPqWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPqWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3DUPqWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNdAsm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNdAsm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNdAsm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNdWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNdWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNdWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNdWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNdWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNdWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNqAsm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNqAsm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNqWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNqWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNqWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3LNqWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3dAsm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3dAsm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3dAsm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3dWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3dWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3dWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3dWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3dWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3dWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3qAsm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3qAsm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3qAsm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3qWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3qWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3qWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3qWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3qWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD3qWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } + }, + + { /* ARM_VLD4DUPdAsm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPdAsm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPdAsm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPdWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPdWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPdWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPdWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPdWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPdWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPqAsm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPqAsm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPqAsm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPqWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPqWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPqWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPqWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPqWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4DUPqWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNdAsm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNdAsm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNdAsm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNdWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNdWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNdWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNdWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNdWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNdWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNqAsm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNqAsm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNqWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNqWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNqWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4LNqWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4dAsm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4dAsm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4dAsm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4dWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4dWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4dWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4dWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4dWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4dWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4qAsm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4qAsm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4qAsm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4qWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4qWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4qWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4qWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4qWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VLD4qWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } + }, + + { /* ARM_VST1LNdAsm_16, ARM_INS_VST1: vst1 */ + { 0 } + }, + + { /* ARM_VST1LNdAsm_32, ARM_INS_VST1: vst1 */ + { 0 } + }, + + { /* ARM_VST1LNdAsm_8, ARM_INS_VST1: vst1 */ + { 0 } + }, + + { /* ARM_VST1LNdWB_fixed_Asm_16, ARM_INS_VST1: vst1 */ + { 0 } + }, + + { /* ARM_VST1LNdWB_fixed_Asm_32, ARM_INS_VST1: vst1 */ + { 0 } + }, + + { /* ARM_VST1LNdWB_fixed_Asm_8, ARM_INS_VST1: vst1 */ + { 0 } + }, + + { /* ARM_VST1LNdWB_register_Asm_16, ARM_INS_VST1: vst1 */ + { 0 } + }, + + { /* ARM_VST1LNdWB_register_Asm_32, ARM_INS_VST1: vst1 */ + { 0 } + }, + + { /* ARM_VST1LNdWB_register_Asm_8, ARM_INS_VST1: vst1 */ + { 0 } + }, + + { /* ARM_VST2LNdAsm_16, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNdAsm_32, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNdAsm_8, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNdWB_fixed_Asm_16, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNdWB_fixed_Asm_32, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNdWB_fixed_Asm_8, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNdWB_register_Asm_16, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNdWB_register_Asm_32, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNdWB_register_Asm_8, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNqAsm_16, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNqAsm_32, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNqWB_fixed_Asm_16, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNqWB_fixed_Asm_32, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNqWB_register_Asm_16, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST2LNqWB_register_Asm_32, ARM_INS_VST2: vst2 */ + { 0 } + }, + + { /* ARM_VST3LNdAsm_16, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNdAsm_32, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNdAsm_8, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNdWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNdWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNdWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNdWB_register_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNdWB_register_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNdWB_register_Asm_8, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNqAsm_16, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNqAsm_32, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNqWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNqWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNqWB_register_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3LNqWB_register_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3dAsm_16, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3dAsm_32, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3dAsm_8, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3dWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3dWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3dWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3dWB_register_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3dWB_register_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3dWB_register_Asm_8, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3qAsm_16, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3qAsm_32, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3qAsm_8, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3qWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3qWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3qWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3qWB_register_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3qWB_register_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST3qWB_register_Asm_8, ARM_INS_VST3: vst3 */ + { 0 } + }, + + { /* ARM_VST4LNdAsm_16, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNdAsm_32, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNdAsm_8, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNdWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNdWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNdWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNdWB_register_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNdWB_register_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNdWB_register_Asm_8, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNqAsm_16, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNqAsm_32, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNqWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNqWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNqWB_register_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4LNqWB_register_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4dAsm_16, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4dAsm_32, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4dAsm_8, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4dWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4dWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4dWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4dWB_register_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4dWB_register_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4dWB_register_Asm_8, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4qAsm_16, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4qAsm_32, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4qAsm_8, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4qWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4qWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4qWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4qWB_register_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4qWB_register_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_VST4qWB_register_Asm_8, ARM_INS_VST4: vst4 */ + { 0 } + }, + + { /* ARM_t2LDRBpcrel, ARM_INS_LDRB: ldrb */ + { 0 } + }, + + { /* ARM_t2LDRConstPool, ARM_INS_LDR: ldr */ + { 0 } + }, + + { /* ARM_t2LDRHpcrel, ARM_INS_LDRH: ldrh */ + { 0 } + }, + + { /* ARM_t2LDRSBpcrel, ARM_INS_LDRSB: ldrsb */ + { 0 } + }, + + { /* ARM_t2LDRSHpcrel, ARM_INS_LDRSH: ldrsh */ + { 0 } + }, + + { /* ARM_t2LDRpcrel, ARM_INS_LDR: ldr */ + { 0 } + }, + + { /* ARM_t2MOVSsi, ARM_INS_MOVS: movs */ + { 0 } + }, + + { /* ARM_t2MOVSsr, ARM_INS_MOVS: movs */ + { 0 } + }, + + { /* ARM_t2MOVsi, ARM_INS_MOV: mov */ + { 0 } + }, + + { /* ARM_t2MOVsr, ARM_INS_MOV: mov */ + { 0 } + }, + + { /* ARM_tLDRConstPool, ARM_INS_LDR: ldr */ + { 0 } + }, + + { /* ARM_ADCri, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_ADCrr, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_ADCrsi, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_ADCrsr, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_ADDri, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_ADDrr, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_ADDrsi, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_ADDrsr, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_ADR, ARM_INS_ADR: adr */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_AESD, ARM_INS_AESD: aesd */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_AESE, ARM_INS_AESE: aese */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_AESIMC, ARM_INS_AESIMC: aesimc */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_AESMC, ARM_INS_AESMC: aesmc */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_ANDri, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_ANDrr, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_ANDrsi, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_ANDrsr, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_BFC, ARM_INS_BFC: bfc */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_BFI, ARM_INS_BFI: bfi */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_BICri, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_BICrr, ARM_INS_BIC: bic */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_BICrsi, ARM_INS_BIC: bic */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_BICrsr, ARM_INS_BIC: bic */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_BKPT, ARM_INS_BKPT: bkpt */ + { 0 } + }, + + { /* ARM_BL, ARM_INS_BL: bl */ + { 0 } + }, + + { /* ARM_BLX, ARM_INS_BLX: blx */ + { CS_AC_READ, 0 } + }, + + { /* ARM_BLX_pred, ARM_INS_BLX: blx */ + { CS_AC_READ, 0 } + }, + + { /* ARM_BLXi, ARM_INS_BLX: blx */ + { 0 } + }, + + { /* ARM_BL_pred, ARM_INS_BL: bl */ + { 0 } + }, + + { /* ARM_BX, ARM_INS_BX: bx */ + { CS_AC_READ, 0 } + }, + + { /* ARM_BXJ, ARM_INS_BXJ: bxj */ + { CS_AC_READ, 0 } + }, + + { /* ARM_BX_RET, ARM_INS_BX: bx */ + { 0 } + }, + + { /* ARM_BX_pred, ARM_INS_BX: bx */ + { CS_AC_READ, 0 } + }, + + { /* ARM_Bcc, ARM_INS_B: b */ + { 0 } + }, + + { /* ARM_CDP, ARM_INS_CDP: cdp */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0 } + }, + + { /* ARM_CDP2, ARM_INS_CDP2: cdp2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0 } + }, + + { /* ARM_CLREX, ARM_INS_CLREX: clrex */ + { 0 } + }, + + { /* ARM_CLZ, ARM_INS_CLZ: clz */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_CMNri, ARM_INS_CMN: cmn */ + { CS_AC_READ, 0 } + }, + + { /* ARM_CMNzrr, ARM_INS_CMN: cmn */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_CMNzrsi, ARM_INS_CMN: cmn */ + { CS_AC_READ, 0 } + }, + + { /* ARM_CMNzrsr, ARM_INS_CMN: cmn */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_CMPri, ARM_INS_CMN: cmn */ + { CS_AC_READ, 0 } + }, + + { /* ARM_CMPrr, ARM_INS_CMP: cmp */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_CMPrsi, ARM_INS_CMP: cmp */ + { CS_AC_READ, 0 } + }, + + { /* ARM_CMPrsr, ARM_INS_CMP: cmp */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_CPS1p, ARM_INS_CPS: cps */ + { 0 } + }, + + { /* ARM_CPS2p, ARM_INS_CPS: cps */ + { 0 } + }, + + { /* ARM_CPS3p, ARM_INS_CPS: cps */ + { 0 } + }, + + { /* ARM_CRC32B, ARM_INS_CRC32B: crc32b */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_CRC32CB, ARM_INS_CRC32CB: crc32cb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_CRC32CH, ARM_INS_CRC32CH: crc32ch */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_CRC32CW, ARM_INS_CRC32CW: crc32cw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_CRC32H, ARM_INS_CRC32H: crc32h */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_CRC32W, ARM_INS_CRC32W: crc32w */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_DBG, ARM_INS_DBG: dbg */ + { 0 } + }, + + { /* ARM_DMB, ARM_INS_DMB: dmb */ + { 0 } + }, + + { /* ARM_DSB, ARM_INS_DFB: dfb */ + { 0 } + }, + + { /* ARM_EORri, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_EORrr, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_EORrsi, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_EORrsr, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_ERET, ARM_INS_ERET: eret */ + { 0 } + }, + + { /* ARM_FCONSTD, ARM_INS_FCONSTD: fconstd */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_FCONSTH, ARM_INS_VMOV: vmov */ + { 0 } + }, + + { /* ARM_FCONSTS, ARM_INS_FCONSTS: fconsts */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX: fldmdbx */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_FLDMXIA, ARM_INS_FLDMIAX: fldmiax */ + { CS_AC_READ, 0 } + }, + + { /* ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX: fldmiax */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_FMSTAT, ARM_INS_FMSTAT: fmstat */ + { 0 } + }, + + { /* ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX: fstmdbx */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_FSTMXIA, ARM_INS_FSTMIAX: fstmiax */ + { CS_AC_READ, 0 } + }, + + { /* ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX: fstmiax */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_HINT, ARM_INS_CSDB: csdb */ + { 0 } + }, + + { /* ARM_HLT, ARM_INS_HLT: hlt */ + { 0 } + }, + + { /* ARM_HVC, ARM_INS_HVC: hvc */ + { 0 } + }, + + { /* ARM_ISB, ARM_INS_ISB: isb */ + { 0 } + }, + + { /* ARM_LDA, ARM_INS_LDA: lda */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDAB, ARM_INS_LDAB: ldab */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDAEX, ARM_INS_LDAEX: ldaex */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDAEXB, ARM_INS_LDAEXB: ldaexb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDAEXD, ARM_INS_LDAEXD: ldaexd */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDAEXH, ARM_INS_LDAEXH: ldaexh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDAH, ARM_INS_LDAH: ldah */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDC2_OFFSET, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDC2_OPTION, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDC2_POST, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDC2_PRE, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDC_OFFSET, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDC_OPTION, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDC_POST, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDC_PRE, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDMDA, ARM_INS_LDMDA: ldmda */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_LDMDA_UPD, ARM_INS_LDMDA: ldmda */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_LDMDB, ARM_INS_LDMDB: ldmdb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_LDMDB_UPD, ARM_INS_LDMDB: ldmdb */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_LDMIA, ARM_INS_LDM: ldm */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_LDMIA_UPD, ARM_INS_LDM: ldm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_LDMIB, ARM_INS_LDMIB: ldmib */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_LDMIB_UPD, ARM_INS_LDMIB: ldmib */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_LDRBT_POST_IMM, ARM_INS_LDRBT: ldrbt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRBT_POST_REG, ARM_INS_LDRBT: ldrbt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRB_POST_IMM, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRB_POST_REG, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRB_PRE_IMM, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRB_PRE_REG, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRBi12, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRBrs, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRD, ARM_INS_LDRD: ldrd */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_LDRD_POST, ARM_INS_LDRD: ldrd */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRD_PRE, ARM_INS_LDRD: ldrd */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_LDREX, ARM_INS_LDREX: ldrex */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDREXB, ARM_INS_LDREXB: ldrexb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDREXD, ARM_INS_LDREXD: ldrexd */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDREXH, ARM_INS_LDREXH: ldrexh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRH, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_LDRHTi, ARM_INS_LDRHT: ldrht */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRHTr, ARM_INS_LDRHT: ldrht */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDRH_POST, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRH_PRE, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_LDRSB, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_LDRSBTi, ARM_INS_LDRSBT: ldrsbt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRSBTr, ARM_INS_LDRSBT: ldrsbt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDRSB_POST, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRSB_PRE, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_LDRSH, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_LDRSHTi, ARM_INS_LDRSHT: ldrsht */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRSHTr, ARM_INS_LDRSHT: ldrsht */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_LDRSH_POST, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRSH_PRE, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_LDRT_POST_IMM, ARM_INS_LDRT: ldrt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRT_POST_REG, ARM_INS_LDRT: ldrt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDR_POST_IMM, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDR_POST_REG, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDR_PRE_IMM, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDR_PRE_REG, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRcp, ARM_INS_LDR: ldr${p} $rt $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRi12, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_LDRrs, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_MCR, ARM_INS_MCR: mcr */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0 } + }, + + { /* ARM_MCR2, ARM_INS_MCR2: mcr2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0 } + }, + + { /* ARM_MCRR, ARM_INS_MCRR: mcrr */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_MLA, ARM_INS_MLA: mla */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_MLS, ARM_INS_MLS: mls */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_MOVPCLR, ARM_INS_MOV: mov */ + { 0 } + }, + + { /* ARM_MOVTi16, ARM_INS_MOVT: movt */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_MOVi, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_MOVi16, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_MOVr, ARM_INS_MOV: mov */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_MOVr_TC, ARM_INS_MOV: mov */ + { 0 } + }, + + { /* ARM_MOVsi, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_MOVsr, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_MRC, ARM_INS_MRC: mrc */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0 } + }, + + { /* ARM_MRC2, ARM_INS_MRC2: mrc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0 } + }, + + { /* ARM_MRRC, ARM_INS_MRRC: mrrc */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_MRS, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_MRSbanked, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_MRSsys, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_MSR, ARM_INS_MSR: msr */ + { CS_AC_READ, 0 } + }, + + { /* ARM_MSRbanked, ARM_INS_MSR: msr */ + { CS_AC_READ, 0 } + }, + + { /* ARM_MSRi, ARM_INS_MSR: msr */ + { 0 } + }, + + { /* ARM_MUL, ARM_INS_MUL: mul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_MVNi, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_MVNr, ARM_INS_MVN: mvn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_MVNsi, ARM_INS_MVN: mvn */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_MVNsr, ARM_INS_MVN: mvn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_ORRri, ARM_INS_ORR: orr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_ORRrr, ARM_INS_ORR: orr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_ORRrsi, ARM_INS_ORR: orr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_ORRrsr, ARM_INS_ORR: orr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_PKHBT, ARM_INS_PKHBT: pkhbt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_PKHTB, ARM_INS_PKHTB: pkhtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_PLDWi12, ARM_INS_PLDW: pldw */ + { CS_AC_READ, 0 } + }, + + { /* ARM_PLDWrs, ARM_INS_PLDW: pldw */ + { CS_AC_READ, 0 } + }, + + { /* ARM_PLDi12, ARM_INS_PLD: pld */ + { CS_AC_READ, 0 } + }, + + { /* ARM_PLDrs, ARM_INS_PLD: pld */ + { CS_AC_READ, 0 } + }, + + { /* ARM_PLIi12, ARM_INS_PLI: pli */ + { CS_AC_READ, 0 } + }, + + { /* ARM_PLIrs, ARM_INS_PLI: pli */ + { CS_AC_READ, 0 } + }, + + { /* ARM_QADD, ARM_INS_QADD: qadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_QADD16, ARM_INS_QADD16: qadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_QADD8, ARM_INS_QADD8: qadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_QASX, ARM_INS_QASX: qasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_QDADD, ARM_INS_QDADD: qdadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_QDSUB, ARM_INS_QDSUB: qdsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_QSAX, ARM_INS_QSAX: qsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_QSUB, ARM_INS_QSUB: qsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_QSUB16, ARM_INS_QSUB16: qsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_QSUB8, ARM_INS_QSUB8: qsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_RBIT, ARM_INS_RBIT: rbit */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_REV, ARM_INS_REV: rev */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_REV16, ARM_INS_REV16: rev16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_REVSH, ARM_INS_REVSH: revsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_RFEDA, ARM_INS_RFEDA: rfeda */ + { CS_AC_READ, 0 } + }, + + { /* ARM_RFEDA_UPD, ARM_INS_RFEDA: rfeda */ + { CS_AC_READ, 0 } + }, + + { /* ARM_RFEDB, ARM_INS_RFEDB: rfedb */ + { CS_AC_READ, 0 } + }, + + { /* ARM_RFEDB_UPD, ARM_INS_RFEDB: rfedb */ + { CS_AC_READ, 0 } + }, + + { /* ARM_RFEIA, ARM_INS_RFEIA: rfeia */ + { CS_AC_READ, 0 } + }, + + { /* ARM_RFEIA_UPD, ARM_INS_RFEIA: rfeia */ + { CS_AC_READ, 0 } + }, + + { /* ARM_RFEIB, ARM_INS_RFEIB: rfeib */ + { CS_AC_READ, 0 } + }, + + { /* ARM_RFEIB_UPD, ARM_INS_RFEIB: rfeib */ + { CS_AC_READ, 0 } + }, + + { /* ARM_RSBri, ARM_INS_NEG: neg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_RSBrr, ARM_INS_RSB: rsb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_RSBrsi, ARM_INS_RSB: rsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_RSBrsr, ARM_INS_RSB: rsb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_RSCri, ARM_INS_RSC: rsc */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_RSCrr, ARM_INS_RSC: rsc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_RSCrsi, ARM_INS_RSC: rsc */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_RSCrsr, ARM_INS_RSC: rsc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SADD16, ARM_INS_SADD16: sadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SADD8, ARM_INS_SADD8: sadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SASX, ARM_INS_SASX: sasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SBCri, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SBCrr, ARM_INS_SBC: sbc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SBCrsi, ARM_INS_SBC: sbc */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SBCrsr, ARM_INS_SBC: sbc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SBFX, ARM_INS_SBFX: sbfx */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SDIV, ARM_INS_SDIV: sdiv */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SEL, ARM_INS_SEL: sel */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SETEND, ARM_INS_SETEND: setend */ + { 0 } + }, + + { /* ARM_SETPAN, ARM_INS_SETPAN: setpan */ + { 0 } + }, + + { /* ARM_SHA1C, ARM_INS_SHA1C: sha1c */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SHA1H, ARM_INS_SHA1H: sha1h */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SHA1M, ARM_INS_SHA1M: sha1m */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SHA1P, ARM_INS_SHA1P: sha1p */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SHA1SU0, ARM_INS_SHA1SU0: sha1su0 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SHA1SU1, ARM_INS_SHA1SU1: sha1su1 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SHA256H, ARM_INS_SHA256H: sha256h */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SHA256H2, ARM_INS_SHA256H2: sha256h2 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SHA256SU0, ARM_INS_SHA256SU0: sha256su0 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SHA256SU1, ARM_INS_SHA256SU1: sha256su1 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SHADD16, ARM_INS_SHADD16: shadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SHADD8, ARM_INS_SHADD8: shadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SHASX, ARM_INS_SHASX: shasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SHSAX, ARM_INS_SHSAX: shsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SHSUB8, ARM_INS_SHSUB8: shsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMC, ARM_INS_SMC: smc */ + { 0 } + }, + + { /* ARM_SMLABB, ARM_INS_SMLABB: smlabb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLABT, ARM_INS_SMLABT: smlabt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLAD, ARM_INS_SMLAD: smlad */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLADX, ARM_INS_SMLADX: smladx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLAL, ARM_INS_SMLAL: smlal */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLALBB, ARM_INS_SMLALBB: smlalbb */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLALBT, ARM_INS_SMLALBT: smlalbt */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLALD, ARM_INS_SMLALD: smlald */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLALDX, ARM_INS_SMLALDX: smlaldx */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLALTB, ARM_INS_SMLALTB: smlaltb */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLALTT, ARM_INS_SMLALTT: smlaltt */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLATB, ARM_INS_SMLATB: smlatb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLATT, ARM_INS_SMLATT: smlatt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLSD, ARM_INS_SMLSD: smlsd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMLSLDX, ARM_INS_SMLSLDX: smlsldx */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMMLA, ARM_INS_SMMLA: smmla */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMMLAR, ARM_INS_SMMLAR: smmlar */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMMLS, ARM_INS_SMMLS: smmls */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMMLSR, ARM_INS_SMMLSR: smmlsr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMMUL, ARM_INS_SMMUL: smmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMMULR, ARM_INS_SMMULR: smmulr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMUAD, ARM_INS_SMUAD: smuad */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMUADX, ARM_INS_SMUADX: smuadx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMULBB, ARM_INS_SMULBB: smulbb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMULBT, ARM_INS_SMULBT: smulbt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMULL, ARM_INS_SMULL: smull */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMULTB, ARM_INS_SMULTB: smultb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMULTT, ARM_INS_SMULTT: smultt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMULWB, ARM_INS_SMULWB: smulwb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMULWT, ARM_INS_SMULWT: smulwt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMUSD, ARM_INS_SMUSD: smusd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SRSDA, ARM_INS_SRSDA: srsda */ + { 0 } + }, + + { /* ARM_SRSDA_UPD, ARM_INS_SRSDA: srsda */ + { 0 } + }, + + { /* ARM_SRSDB, ARM_INS_SRSDB: srsdb */ + { 0 } + }, + + { /* ARM_SRSDB_UPD, ARM_INS_SRSDB: srsdb */ + { 0 } + }, + + { /* ARM_SRSIA, ARM_INS_SRSIA: srsia */ + { 0 } + }, + + { /* ARM_SRSIA_UPD, ARM_INS_SRSIA: srsia */ + { 0 } + }, + + { /* ARM_SRSIB, ARM_INS_SRSIB: srsib */ + { 0 } + }, + + { /* ARM_SRSIB_UPD, ARM_INS_SRSIB: srsib */ + { 0 } + }, + + { /* ARM_SSAT, ARM_INS_SSAT: ssat */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_SSAT16, ARM_INS_SSAT16: ssat16 */ + { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } + }, + + { /* ARM_SSAX, ARM_INS_SSAX: ssax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SSUB16, ARM_INS_SSUB16: ssub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SSUB8, ARM_INS_SSUB8: ssub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STC2L_OFFSET, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STC2L_OPTION, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STC2L_POST, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STC2L_PRE, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STC2_OFFSET, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STC2_OPTION, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STC2_POST, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STC2_PRE, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STCL_OPTION, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STCL_POST, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STCL_PRE, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STC_OFFSET, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STC_OPTION, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STC_POST, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STC_PRE, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STL, ARM_INS_STL: stl */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STLB, ARM_INS_STLB: stlb */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STLEX, ARM_INS_STLEX: stlex */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STLEXB, ARM_INS_STLEXB: stlexb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STLEXD, ARM_INS_STLEXD: stlexd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STLEXH, ARM_INS_STLEXH: stlexh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STLH, ARM_INS_STLH: stlh */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STMDA, ARM_INS_STMDA: stmda */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STMDA_UPD, ARM_INS_STMDA: stmda */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_STMDB, ARM_INS_STMDB: stmdb */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STMDB_UPD, ARM_INS_PUSH: push */ + { CS_AC_READ, 0 } + }, + + { /* ARM_STMIA, ARM_INS_STM: stm */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STMIA_UPD, ARM_INS_STM: stm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_STMIB, ARM_INS_STMIB: stmib */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STMIB_UPD, ARM_INS_STMIB: stmib */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_STRBT_POST_IMM, ARM_INS_STRBT: strbt */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STRBT_POST_REG, ARM_INS_STRBT: strbt */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STRB_POST_IMM, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STRB_POST_REG, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STRB_PRE_IMM, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STRB_PRE_REG, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STRBi12, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STRBrs, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STRD, ARM_INS_STRD: strd */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STRD_POST, ARM_INS_STRD: strd */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STRD_PRE, ARM_INS_STRD: strd */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STREX, ARM_INS_STREX: strex */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STREXB, ARM_INS_STREXB: strexb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STREXD, ARM_INS_STREXD: strexd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STREXH, ARM_INS_STREXH: strexh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STRH, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STRHTi, ARM_INS_STRHT: strht */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STRHTr, ARM_INS_STRHT: strht */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STRH_POST, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_STRH_PRE, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STRT_POST_IMM, ARM_INS_STRT: strt */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STRT_POST_REG, ARM_INS_STRT: strt */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STR_POST_IMM, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STR_POST_REG, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STR_PRE_IMM, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STR_PRE_REG, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STRi12, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_STRrs, ARM_INS_STR: str */ + { CS_AC_READ, 0 } + }, + + { /* ARM_SUBri, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SUBrr, ARM_INS_SUB: sub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SUBrsi, ARM_INS_SUB: sub */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SUBrsr, ARM_INS_SUB: sub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SVC, ARM_INS_SVC: svc */ + { 0 } + }, + + { /* ARM_SWP, ARM_INS_SWP: swp */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SWPB, ARM_INS_SWPB: swpb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_SXTAB, ARM_INS_SXTAB: sxtab */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SXTAB16, ARM_INS_SXTAB16: sxtab16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SXTAH, ARM_INS_SXTAH: sxtah */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SXTB, ARM_INS_SXTB: sxtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SXTB16, ARM_INS_SXTB16: sxtb16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_SXTH, ARM_INS_SXTH: sxth */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_TEQri, ARM_INS_TEQ: teq */ + { CS_AC_READ, 0 } + }, + + { /* ARM_TEQrr, ARM_INS_TEQ: teq */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_TEQrsi, ARM_INS_TEQ: teq */ + { CS_AC_READ, 0 } + }, + + { /* ARM_TEQrsr, ARM_INS_TEQ: teq */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_TRAP, ARM_INS_TRAP: trap */ + { 0 } + }, + + { /* ARM_TRAPNaCl, ARM_INS_TRAP: trap */ + { 0 } + }, + + { /* ARM_TSB, ARM_INS_TSB: tsb */ + { 0 } + }, + + { /* ARM_TSTri, ARM_INS_TST: tst */ + { CS_AC_READ, 0 } + }, + + { /* ARM_TSTrr, ARM_INS_TST: tst */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_TSTrsi, ARM_INS_TST: tst */ + { CS_AC_READ, 0 } + }, + + { /* ARM_TSTrsr, ARM_INS_TST: tst */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UADD16, ARM_INS_UADD16: uadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UADD8, ARM_INS_UADD8: uadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UASX, ARM_INS_UASX: uasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UBFX, ARM_INS_UBFX: ubfx */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_UDF, ARM_INS_UDF: udf */ + { 0 } + }, + + { /* ARM_UDIV, ARM_INS_UDIV: udiv */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UHADD16, ARM_INS_UHADD16: uhadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UHADD8, ARM_INS_UHADD8: uhadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UHASX, ARM_INS_UHASX: uhasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UHSAX, ARM_INS_UHSAX: uhsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UHSUB16, ARM_INS_UHSUB16: uhsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UHSUB8, ARM_INS_UHSUB8: uhsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UMAAL, ARM_INS_UMAAL: umaal */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UMLAL, ARM_INS_UMLAL: umlal */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UMULL, ARM_INS_UMULL: umull */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UQADD16, ARM_INS_UQADD16: uqadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UQADD8, ARM_INS_UQADD8: uqadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UQASX, ARM_INS_UQASX: uqasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UQSAX, ARM_INS_UQSAX: uqsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UQSUB16, ARM_INS_UQSUB16: uqsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UQSUB8, ARM_INS_UQSUB8: uqsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_USAD8, ARM_INS_USAD8: usad8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_USADA8, ARM_INS_USADA8: usada8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_USAT, ARM_INS_USAT: usat */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_USAT16, ARM_INS_USAT16: usat16 */ + { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } + }, + + { /* ARM_USAX, ARM_INS_USAX: usax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_USUB16, ARM_INS_USUB16: usub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_USUB8, ARM_INS_USUB8: usub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_UXTAB, ARM_INS_UXTAB: uxtab */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_UXTAB16, ARM_INS_UXTAB16: uxtab16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_UXTAH, ARM_INS_UXTAH: uxtah */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_UXTB, ARM_INS_UXTB: uxtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_UXTB16, ARM_INS_UXTB16: uxtb16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_UXTH, ARM_INS_UXTH: uxth */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VABALsv2i64, ARM_INS_VABAL: vabal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABALsv4i32, ARM_INS_VABAL: vabal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABALsv8i16, ARM_INS_VABAL: vabal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABALuv2i64, ARM_INS_VABAL: vabal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABALuv4i32, ARM_INS_VABAL: vabal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABALuv8i16, ARM_INS_VABAL: vabal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABAsv16i8, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABAsv2i32, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABAsv4i16, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABAsv4i32, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABAsv8i16, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABAsv8i8, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABAuv16i8, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABAuv2i32, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABAuv4i16, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABAuv4i32, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABAuv8i16, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABAuv8i8, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDLsv2i64, ARM_INS_VABDL: vabdl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDLsv4i32, ARM_INS_VABDL: vabdl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDLsv8i16, ARM_INS_VABDL: vabdl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDLuv2i64, ARM_INS_VABDL: vabdl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDLuv4i32, ARM_INS_VABDL: vabdl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDLuv8i16, ARM_INS_VABDL: vabdl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDfd, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDfq, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDhd, ARM_INS_VABD: vabd */ + { 0 } + }, + + { /* ARM_VABDhq, ARM_INS_VABD: vabd */ + { 0 } + }, + + { /* ARM_VABDsv16i8, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDsv2i32, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDsv4i16, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDsv4i32, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDsv8i16, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDsv8i8, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDuv16i8, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDuv2i32, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDuv4i16, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDuv4i32, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDuv8i16, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABDuv8i8, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VABSD, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VABSH, ARM_INS_VABS: vabs */ + { 0 } + }, + + { /* ARM_VABSS, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VABSfd, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VABSfq, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VABShd, ARM_INS_VABS: vabs */ + { 0 } + }, + + { /* ARM_VABShq, ARM_INS_VABS: vabs */ + { 0 } + }, + + { /* ARM_VABSv16i8, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VABSv2i32, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VABSv4i16, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VABSv4i32, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VABSv8i16, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VABSv8i8, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VACGEfd, ARM_INS_VACGE: vacge */ + { 0 } + }, + + { /* ARM_VACGEfq, ARM_INS_VACGE: vacge */ + { 0 } + }, + + { /* ARM_VACGEhd, ARM_INS_VACGE: vacge */ + { 0 } + }, + + { /* ARM_VACGEhq, ARM_INS_VACGE: vacge */ + { 0 } + }, + + { /* ARM_VACGTfd, ARM_INS_VACGT: vacgt */ + { 0 } + }, + + { /* ARM_VACGTfq, ARM_INS_VACGT: vacgt */ + { 0 } + }, + + { /* ARM_VACGThd, ARM_INS_VACGT: vacgt */ + { 0 } + }, + + { /* ARM_VACGThq, ARM_INS_VACGT: vacgt */ + { 0 } + }, + + { /* ARM_VADDD, ARM_INS_FADDD: faddd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDH, ARM_INS_VADD: vadd */ + { 0 } + }, + + { /* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDLsv2i64, ARM_INS_VADDL: vaddl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDLsv4i32, ARM_INS_VADDL: vaddl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDLsv8i16, ARM_INS_VADDL: vaddl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDLuv2i64, ARM_INS_VADDL: vaddl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDLuv4i32, ARM_INS_VADDL: vaddl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDLuv8i16, ARM_INS_VADDL: vaddl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDS, ARM_INS_FADDS: fadds */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDWsv2i64, ARM_INS_VADDW: vaddw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDWsv4i32, ARM_INS_VADDW: vaddw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDWsv8i16, ARM_INS_VADDW: vaddw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDWuv2i64, ARM_INS_VADDW: vaddw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDWuv4i32, ARM_INS_VADDW: vaddw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDWuv8i16, ARM_INS_VADDW: vaddw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDfd, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDfq, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDhd, ARM_INS_VADD: vadd */ + { 0 } + }, + + { /* ARM_VADDhq, ARM_INS_VADD: vadd */ + { 0 } + }, + + { /* ARM_VADDv16i8, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDv1i64, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDv2i32, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDv2i64, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDv4i16, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDv4i32, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDv8i16, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VADDv8i8, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VANDd, ARM_INS_VAND: vand */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VANDq, ARM_INS_VAND: vand */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VBICd, ARM_INS_VBIC: vbic */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VBICiv2i32, ARM_INS_VAND: vand */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VBICiv4i16, ARM_INS_VAND: vand */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VBICiv4i32, ARM_INS_VAND: vand */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VBICiv8i16, ARM_INS_VAND: vand */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VBICq, ARM_INS_VBIC: vbic */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VBIFd, ARM_INS_VBIF: vbif */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VBIFq, ARM_INS_VBIF: vbif */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VBITd, ARM_INS_VBIT: vbit */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VBITq, ARM_INS_VBIT: vbit */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VBSLd, ARM_INS_VBSL: vbsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VBSLq, ARM_INS_VBSL: vbsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCADDv2f32, ARM_INS_VCADD: vcadd */ + { 0 } + }, + + { /* ARM_VCADDv4f16, ARM_INS_VCADD: vcadd */ + { 0 } + }, + + { /* ARM_VCADDv4f32, ARM_INS_VCADD: vcadd */ + { 0 } + }, + + { /* ARM_VCADDv8f16, ARM_INS_VCADD: vcadd */ + { 0 } + }, + + { /* ARM_VCEQfd, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQfq, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQhd, ARM_INS_VCEQ: vceq */ + { 0 } + }, + + { /* ARM_VCEQhq, ARM_INS_VCEQ: vceq */ + { 0 } + }, + + { /* ARM_VCEQv16i8, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQv2i32, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQv4i16, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQv4i32, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQv8i16, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQv8i8, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQzv16i8, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQzv2f32, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQzv2i32, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQzv4f16, ARM_INS_VCEQ: vceq */ + { 0 } + }, + + { /* ARM_VCEQzv4f32, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQzv4i16, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQzv4i32, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQzv8f16, ARM_INS_VCEQ: vceq */ + { 0 } + }, + + { /* ARM_VCEQzv8i16, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCEQzv8i8, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEfd, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEfq, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEhd, ARM_INS_VCGE: vcge */ + { 0 } + }, + + { /* ARM_VCGEhq, ARM_INS_VCGE: vcge */ + { 0 } + }, + + { /* ARM_VCGEsv16i8, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEsv2i32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEsv4i16, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEsv4i32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEsv8i16, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEsv8i8, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEuv16i8, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEuv2i32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEuv4i16, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEuv4i32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEuv8i16, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEuv8i8, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEzv16i8, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEzv2f32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEzv2i32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEzv4f16, ARM_INS_VCGE: vcge */ + { 0 } + }, + + { /* ARM_VCGEzv4f32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEzv4i16, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEzv4i32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEzv8f16, ARM_INS_VCGE: vcge */ + { 0 } + }, + + { /* ARM_VCGEzv8i16, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGEzv8i8, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTfd, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTfq, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGThd, ARM_INS_VCGT: vcgt */ + { 0 } + }, + + { /* ARM_VCGThq, ARM_INS_VCGT: vcgt */ + { 0 } + }, + + { /* ARM_VCGTsv16i8, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTsv2i32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTsv4i16, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTsv4i32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTsv8i16, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTsv8i8, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTuv16i8, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTuv2i32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTuv4i16, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTuv4i32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTuv8i16, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTuv8i8, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTzv16i8, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTzv2f32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTzv2i32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTzv4f16, ARM_INS_VCGT: vcgt */ + { 0 } + }, + + { /* ARM_VCGTzv4f32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTzv4i16, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTzv4i32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTzv8f16, ARM_INS_VCGT: vcgt */ + { 0 } + }, + + { /* ARM_VCGTzv8i16, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCGTzv8i8, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLEzv16i8, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLEzv2f32, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLEzv2i32, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLEzv4f16, ARM_INS_VCLE: vcle */ + { 0 } + }, + + { /* ARM_VCLEzv4f32, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLEzv4i16, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLEzv4i32, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLEzv8f16, ARM_INS_VCLE: vcle */ + { 0 } + }, + + { /* ARM_VCLEzv8i16, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLEzv8i8, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLSv16i8, ARM_INS_VCLS: vcls */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLSv2i32, ARM_INS_VCLS: vcls */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLSv4i16, ARM_INS_VCLS: vcls */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLSv4i32, ARM_INS_VCLS: vcls */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLSv8i16, ARM_INS_VCLS: vcls */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLSv8i8, ARM_INS_VCLS: vcls */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLTzv16i8, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLTzv2f32, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLTzv2i32, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLTzv4f16, ARM_INS_VCLT: vclt */ + { 0 } + }, + + { /* ARM_VCLTzv4f32, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLTzv4i16, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLTzv4i32, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLTzv8f16, ARM_INS_VCLT: vclt */ + { 0 } + }, + + { /* ARM_VCLTzv8i16, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLTzv8i8, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLZv16i8, ARM_INS_VCLZ: vclz */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLZv2i32, ARM_INS_VCLZ: vclz */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLZv4i16, ARM_INS_VCLZ: vclz */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLZv4i32, ARM_INS_VCLZ: vclz */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLZv8i16, ARM_INS_VCLZ: vclz */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCLZv8i8, ARM_INS_VCLZ: vclz */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCMLAv2f32, ARM_INS_VCMLA: vcmla */ + { 0 } + }, + + { /* ARM_VCMLAv2f32_indexed, ARM_INS_VCMLA: vcmla */ + { 0 } + }, + + { /* ARM_VCMLAv4f16, ARM_INS_VCMLA: vcmla */ + { 0 } + }, + + { /* ARM_VCMLAv4f16_indexed, ARM_INS_VCMLA: vcmla */ + { 0 } + }, + + { /* ARM_VCMLAv4f32, ARM_INS_VCMLA: vcmla */ + { 0 } + }, + + { /* ARM_VCMLAv4f32_indexed, ARM_INS_VCMLA: vcmla */ + { 0 } + }, + + { /* ARM_VCMLAv8f16, ARM_INS_VCMLA: vcmla */ + { 0 } + }, + + { /* ARM_VCMLAv8f16_indexed, ARM_INS_VCMLA: vcmla */ + { 0 } + }, + + { /* ARM_VCMPD, ARM_INS_VCMP: vcmp */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCMPED, ARM_INS_VCMPE: vcmpe */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCMPEH, ARM_INS_VCMPE: vcmpe */ + { 0 } + }, + + { /* ARM_VCMPES, ARM_INS_VCMPE: vcmpe */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCMPEZD, ARM_INS_VCMPE: vcmpe */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VCMPEZH, ARM_INS_VCMPE: vcmpe */ + { 0 } + }, + + { /* ARM_VCMPEZS, ARM_INS_VCMPE: vcmpe */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VCMPH, ARM_INS_VCMP: vcmp */ + { 0 } + }, + + { /* ARM_VCMPS, ARM_INS_VCMP: vcmp */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VCMPZD, ARM_INS_FCMPZD: fcmpzd */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VCMPZH, ARM_INS_VCMP: vcmp */ + { 0 } + }, + + { /* ARM_VCMPZS, ARM_INS_FCMPZS: fcmpzs */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VCNTd, ARM_INS_VCNT: vcnt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCNTq, ARM_INS_VCNT: vcnt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTANSDf, ARM_INS_VCVTA: vcvta */ + { 0 } + }, + + { /* ARM_VCVTANSDh, ARM_INS_VCVTA: vcvta */ + { 0 } + }, + + { /* ARM_VCVTANSQf, ARM_INS_VCVTA: vcvta */ + { 0 } + }, + + { /* ARM_VCVTANSQh, ARM_INS_VCVTA: vcvta */ + { 0 } + }, + + { /* ARM_VCVTANUDf, ARM_INS_VCVTA: vcvta */ + { 0 } + }, + + { /* ARM_VCVTANUDh, ARM_INS_VCVTA: vcvta */ + { 0 } + }, + + { /* ARM_VCVTANUQf, ARM_INS_VCVTA: vcvta */ + { 0 } + }, + + { /* ARM_VCVTANUQh, ARM_INS_VCVTA: vcvta */ + { 0 } + }, + + { /* ARM_VCVTASD, ARM_INS_VCVTA: vcvta */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTASH, ARM_INS_VCVTA: vcvta */ + { 0 } + }, + + { /* ARM_VCVTASS, ARM_INS_VCVTA: vcvta */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTAUD, ARM_INS_VCVTA: vcvta */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTAUH, ARM_INS_VCVTA: vcvta */ + { 0 } + }, + + { /* ARM_VCVTAUS, ARM_INS_VCVTA: vcvta */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTBDH, ARM_INS_VCVTB: vcvtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTBHD, ARM_INS_VCVTB: vcvtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTBHS, ARM_INS_VCVTB: vcvtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTBSH, ARM_INS_VCVTB: vcvtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTDS, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTMNSDf, ARM_INS_VCVTM: vcvtm */ + { 0 } + }, + + { /* ARM_VCVTMNSDh, ARM_INS_VCVTM: vcvtm */ + { 0 } + }, + + { /* ARM_VCVTMNSQf, ARM_INS_VCVTM: vcvtm */ + { 0 } + }, + + { /* ARM_VCVTMNSQh, ARM_INS_VCVTM: vcvtm */ + { 0 } + }, + + { /* ARM_VCVTMNUDf, ARM_INS_VCVTM: vcvtm */ + { 0 } + }, + + { /* ARM_VCVTMNUDh, ARM_INS_VCVTM: vcvtm */ + { 0 } + }, + + { /* ARM_VCVTMNUQf, ARM_INS_VCVTM: vcvtm */ + { 0 } + }, + + { /* ARM_VCVTMNUQh, ARM_INS_VCVTM: vcvtm */ + { 0 } + }, + + { /* ARM_VCVTMSD, ARM_INS_VCVTM: vcvtm */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTMSH, ARM_INS_VCVTM: vcvtm */ + { 0 } + }, + + { /* ARM_VCVTMSS, ARM_INS_VCVTM: vcvtm */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTMUD, ARM_INS_VCVTM: vcvtm */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTMUH, ARM_INS_VCVTM: vcvtm */ + { 0 } + }, + + { /* ARM_VCVTMUS, ARM_INS_VCVTM: vcvtm */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTNNSDf, ARM_INS_VCVTN: vcvtn */ + { 0 } + }, + + { /* ARM_VCVTNNSDh, ARM_INS_VCVTN: vcvtn */ + { 0 } + }, + + { /* ARM_VCVTNNSQf, ARM_INS_VCVTN: vcvtn */ + { 0 } + }, + + { /* ARM_VCVTNNSQh, ARM_INS_VCVTN: vcvtn */ + { 0 } + }, + + { /* ARM_VCVTNNUDf, ARM_INS_VCVTN: vcvtn */ + { 0 } + }, + + { /* ARM_VCVTNNUDh, ARM_INS_VCVTN: vcvtn */ + { 0 } + }, + + { /* ARM_VCVTNNUQf, ARM_INS_VCVTN: vcvtn */ + { 0 } + }, + + { /* ARM_VCVTNNUQh, ARM_INS_VCVTN: vcvtn */ + { 0 } + }, + + { /* ARM_VCVTNSD, ARM_INS_VCVTN: vcvtn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTNSH, ARM_INS_VCVTN: vcvtn */ + { 0 } + }, + + { /* ARM_VCVTNSS, ARM_INS_VCVTN: vcvtn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTNUD, ARM_INS_VCVTN: vcvtn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTNUH, ARM_INS_VCVTN: vcvtn */ + { 0 } + }, + + { /* ARM_VCVTNUS, ARM_INS_VCVTN: vcvtn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTPNSDf, ARM_INS_VCVTP: vcvtp */ + { 0 } + }, + + { /* ARM_VCVTPNSDh, ARM_INS_VCVTP: vcvtp */ + { 0 } + }, + + { /* ARM_VCVTPNSQf, ARM_INS_VCVTP: vcvtp */ + { 0 } + }, + + { /* ARM_VCVTPNSQh, ARM_INS_VCVTP: vcvtp */ + { 0 } + }, + + { /* ARM_VCVTPNUDf, ARM_INS_VCVTP: vcvtp */ + { 0 } + }, + + { /* ARM_VCVTPNUDh, ARM_INS_VCVTP: vcvtp */ + { 0 } + }, + + { /* ARM_VCVTPNUQf, ARM_INS_VCVTP: vcvtp */ + { 0 } + }, + + { /* ARM_VCVTPNUQh, ARM_INS_VCVTP: vcvtp */ + { 0 } + }, + + { /* ARM_VCVTPSD, ARM_INS_VCVTP: vcvtp */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTPSH, ARM_INS_VCVTP: vcvtp */ + { 0 } + }, + + { /* ARM_VCVTPSS, ARM_INS_VCVTP: vcvtp */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTPUD, ARM_INS_VCVTP: vcvtp */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTPUH, ARM_INS_VCVTP: vcvtp */ + { 0 } + }, + + { /* ARM_VCVTPUS, ARM_INS_VCVTP: vcvtp */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTSD, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTTDH, ARM_INS_VCVTT: vcvtt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTTHD, ARM_INS_VCVTT: vcvtt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTTHS, ARM_INS_VCVTT: vcvtt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTTSH, ARM_INS_VCVTT: vcvtt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTf2h, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTf2sd, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTf2sq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTf2ud, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTf2uq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTf2xsd, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTf2xsq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTf2xud, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTf2xuq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTh2f, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTh2sd, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTh2sq, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTh2ud, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTh2uq, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTh2xsd, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTh2xsq, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTh2xud, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTh2xuq, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTs2fd, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTs2fq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTs2hd, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTs2hq, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTu2fd, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTu2fq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTu2hd, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTu2hq, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTxs2fd, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTxs2fq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTxs2hd, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTxs2hq, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTxu2fd, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTxu2fq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VCVTxu2hd, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VCVTxu2hq, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VDIVD, ARM_INS_VDIV: vdiv */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VDIVH, ARM_INS_VDIV: vdiv */ + { 0 } + }, + + { /* ARM_VDIVS, ARM_INS_VDIV: vdiv */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VDUP16d, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VDUP16q, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VDUP32d, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VDUP32q, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VDUP8d, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VDUP8q, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VDUPLN16d, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VDUPLN16q, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VDUPLN32d, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VDUPLN32q, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VDUPLN8d, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VDUPLN8q, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VEORd, ARM_INS_VEOR: veor */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VEORq, ARM_INS_VEOR: veor */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VEXTd16, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VEXTd32, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VEXTd8, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VEXTq16, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VEXTq32, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VEXTq64, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VEXTq8, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VFMAD, ARM_INS_VFMA: vfma */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VFMAH, ARM_INS_VFMA: vfma */ + { 0 } + }, + + { /* ARM_VFMAS, ARM_INS_VFMA: vfma */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VFMAfd, ARM_INS_VFMA: vfma */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VFMAfq, ARM_INS_VFMA: vfma */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VFMAhd, ARM_INS_VFMA: vfma */ + { 0 } + }, + + { /* ARM_VFMAhq, ARM_INS_VFMA: vfma */ + { 0 } + }, + + { /* ARM_VFMSD, ARM_INS_VFMS: vfms */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VFMSH, ARM_INS_VFMS: vfms */ + { 0 } + }, + + { /* ARM_VFMSS, ARM_INS_VFMS: vfms */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VFMSfd, ARM_INS_VFMS: vfms */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VFMSfq, ARM_INS_VFMS: vfms */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VFMShd, ARM_INS_VFMS: vfms */ + { 0 } + }, + + { /* ARM_VFMShq, ARM_INS_VFMS: vfms */ + { 0 } + }, + + { /* ARM_VFNMAD, ARM_INS_VFNMA: vfnma */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VFNMAH, ARM_INS_VFNMA: vfnma */ + { 0 } + }, + + { /* ARM_VFNMAS, ARM_INS_VFNMA: vfnma */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VFNMSD, ARM_INS_VFNMS: vfnms */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VFNMSH, ARM_INS_VFNMS: vfnms */ + { 0 } + }, + + { /* ARM_VFNMSS, ARM_INS_VFNMS: vfnms */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VGETLNi32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VGETLNs16, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VGETLNs8, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VGETLNu16, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VGETLNu8, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VHADDsv16i8, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHADDsv2i32, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHADDsv4i16, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHADDsv4i32, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHADDsv8i16, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHADDsv8i8, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHADDuv16i8, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHADDuv2i32, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHADDuv4i16, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHADDuv4i32, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHADDuv8i16, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHADDuv8i8, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHSUBsv16i8, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHSUBsv2i32, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHSUBsv4i16, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHSUBsv4i32, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHSUBsv8i16, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHSUBsv8i8, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHSUBuv16i8, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHSUBuv2i32, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHSUBuv4i16, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHSUBuv4i32, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHSUBuv8i16, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VHSUBuv8i8, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VINSH, ARM_INS_VINS: vins */ + { 0 } + }, + + { /* ARM_VJCVT, ARM_INS_VJCVT: vjcvt */ + { 0 } + }, + + { /* ARM_VLD1DUPd16, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPd16wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPd32, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPd32wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPd8, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPd8wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPq16, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPq16wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPq32, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPq32wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPq8, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1DUPq8wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1LNd16, ARM_INS_VLD1: vld1 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1LNd16_UPD, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD1LNd32, ARM_INS_VLD1: vld1 */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD1LNd32_UPD, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD1LNd8, ARM_INS_VLD1: vld1 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1LNd8_UPD, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD1d16, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d16Q, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d16Qwb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d16T, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d16Twb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d16Twb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d16wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d16wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d32, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d32Q, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d32Qwb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d32T, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d32Twb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d32Twb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d32wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d32wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d64, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d64Q, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d64Qwb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d64T, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d64Twb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d64Twb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d64wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d64wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d8, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d8Q, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d8Qwb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d8T, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d8Twb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d8Twb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d8wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1d8wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1q16, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1q16wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1q16wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1q32, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1q32wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1q32wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1q64, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1q64wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1q64wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1q8, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1q8wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD1q8wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd16, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd16wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd16x2, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd32, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd32wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd32x2, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd8, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd8wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd8x2, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2LNd16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2LNd16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD2LNd32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2LNd32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD2LNd8, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane] $dst2[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2LNd8_UPD, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD2LNq16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2LNq16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD2LNq32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2LNq32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD2b16, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2b16wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2b16wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2b32, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2b32wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2b32wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2b8, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2b8wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2b8wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2d16, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2d16wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2d16wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2d32, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2d32wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2d32wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2d8, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2d8wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2d8wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2q16, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2q16wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2q16wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2q32, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2q32wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2q32wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2q8, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2q8wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD2q8wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3DUPq8, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3DUPq8_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3LNd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3LNd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD3LNd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3LNd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD3LNd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3LNd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD3LNq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3LNq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD3LNq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3LNq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD3d16, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3d16_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD3d32, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3d32_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD3d8, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3d8_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD3q16, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3q16_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD3q32, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3q32_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD3q8, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD3q8_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD4DUPd16, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4DUPd16_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4DUPd32, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4DUPd32_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4DUPd8, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4DUPd8_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4DUPq16, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4DUPq16_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4DUPq32, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4DUPq32_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4DUPq8, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4DUPq8_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4LNd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4LNd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD4LNd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4LNd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD4LNd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4LNd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD4LNq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4LNq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD4LNq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4LNq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD4d16, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4d16_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD4d32, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4d32_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD4d8, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4d8_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD4q16, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4q16_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD4q32, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4q32_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLD4q8, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VLD4q8_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VLDMDDB_UPD, ARM_INS_VLDMDB: vldmdb */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VLDMDIA, ARM_INS_VLDMIA: vldmia */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VLDMDIA_UPD, ARM_INS_VLDMIA: vldmia */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VLDMSDB_UPD, ARM_INS_VLDMDB: vldmdb */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VLDMSIA, ARM_INS_VLDMIA: vldmia */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VLDMSIA_UPD, ARM_INS_VLDMIA: vldmia */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VLDRD, ARM_INS_VLDR: vldr */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VLDRH, ARM_INS_VLDR: vldr */ + { 0 } + }, + + { /* ARM_VLDRS, ARM_INS_VLDR: vldr */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VLLDM, ARM_INS_VLLDM: vlldm */ + { 0 } + }, + + { /* ARM_VLSTM, ARM_INS_VLSTM: vlstm */ + { 0 } + }, + + { /* ARM_VMAXNMD, ARM_INS_VMAXNM: vmaxnm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXNMH, ARM_INS_VMAXNM: vmaxnm */ + { 0 } + }, + + { /* ARM_VMAXNMNDf, ARM_INS_VMAXNM: vmaxnm */ + { 0 } + }, + + { /* ARM_VMAXNMNDh, ARM_INS_VMAXNM: vmaxnm */ + { 0 } + }, + + { /* ARM_VMAXNMNQf, ARM_INS_VMAXNM: vmaxnm */ + { 0 } + }, + + { /* ARM_VMAXNMNQh, ARM_INS_VMAXNM: vmaxnm */ + { 0 } + }, + + { /* ARM_VMAXNMS, ARM_INS_VMAXNM: vmaxnm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXfd, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXfq, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXhd, ARM_INS_VMAX: vmax */ + { 0 } + }, + + { /* ARM_VMAXhq, ARM_INS_VMAX: vmax */ + { 0 } + }, + + { /* ARM_VMAXsv16i8, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXsv2i32, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXsv4i16, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXsv4i32, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXsv8i16, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXsv8i8, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXuv16i8, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXuv2i32, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXuv4i16, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXuv4i32, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXuv8i16, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMAXuv8i8, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINNMD, ARM_INS_VMINNM: vminnm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINNMH, ARM_INS_VMINNM: vminnm */ + { 0 } + }, + + { /* ARM_VMINNMNDf, ARM_INS_VMINNM: vminnm */ + { 0 } + }, + + { /* ARM_VMINNMNDh, ARM_INS_VMINNM: vminnm */ + { 0 } + }, + + { /* ARM_VMINNMNQf, ARM_INS_VMINNM: vminnm */ + { 0 } + }, + + { /* ARM_VMINNMNQh, ARM_INS_VMINNM: vminnm */ + { 0 } + }, + + { /* ARM_VMINNMS, ARM_INS_VMINNM: vminnm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINfd, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINfq, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINhd, ARM_INS_VMIN: vmin */ + { 0 } + }, + + { /* ARM_VMINhq, ARM_INS_VMIN: vmin */ + { 0 } + }, + + { /* ARM_VMINsv16i8, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINsv2i32, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINsv4i16, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINsv4i32, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINsv8i16, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINsv8i8, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINuv16i8, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINuv2i32, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINuv4i16, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINuv4i32, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINuv8i16, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMINuv8i8, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAD, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAH, ARM_INS_VMLA: vmla */ + { 0 } + }, + + { /* ARM_VMLALslsv2i32, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLALslsv4i16, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLALsluv2i32, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLALsluv4i16, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLALsv2i64, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLALsv4i32, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLALsv8i16, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLALuv2i64, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLALuv4i32, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLALuv8i16, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAS, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAfd, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAfq, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAhd, ARM_INS_VMLA: vmla */ + { 0 } + }, + + { /* ARM_VMLAhq, ARM_INS_VMLA: vmla */ + { 0 } + }, + + { /* ARM_VMLAslfd, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAslfq, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAslhd, ARM_INS_VMLA: vmla */ + { 0 } + }, + + { /* ARM_VMLAslhq, ARM_INS_VMLA: vmla */ + { 0 } + }, + + { /* ARM_VMLAslv2i32, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAslv4i16, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAslv4i32, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAslv8i16, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAv16i8, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAv2i32, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAv4i16, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAv4i32, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAv8i16, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLAv8i8, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSD, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSH, ARM_INS_VMLS: vmls */ + { 0 } + }, + + { /* ARM_VMLSLslsv2i32, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSLslsv4i16, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSLsluv2i32, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSLsluv4i16, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSLsv2i64, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSLsv4i32, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSLsv8i16, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSLuv2i64, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSLuv4i32, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSLuv8i16, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSS, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSfd, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSfq, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLShd, ARM_INS_VMLS: vmls */ + { 0 } + }, + + { /* ARM_VMLShq, ARM_INS_VMLS: vmls */ + { 0 } + }, + + { /* ARM_VMLSslfd, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSslfq, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSslhd, ARM_INS_VMLS: vmls */ + { 0 } + }, + + { /* ARM_VMLSslhq, ARM_INS_VMLS: vmls */ + { 0 } + }, + + { /* ARM_VMLSslv2i32, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSslv4i16, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSslv4i32, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSslv8i16, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSv16i8, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSv2i32, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSv4i16, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSv4i32, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSv8i16, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMLSv8i8, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVD, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVDRR, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVH, ARM_INS_VMOVX: vmovx */ + { 0 } + }, + + { /* ARM_VMOVHR, ARM_INS_VMOV: vmov */ + { 0 } + }, + + { /* ARM_VMOVLsv2i64, ARM_INS_VMOVL: vmovl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVLsv4i32, ARM_INS_VMOVL: vmovl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVLsv8i16, ARM_INS_VMOVL: vmovl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVLuv2i64, ARM_INS_VMOVL: vmovl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVLuv4i32, ARM_INS_VMOVL: vmovl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVLuv8i16, ARM_INS_VMOVL: vmovl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVNv2i32, ARM_INS_VMOVN: vmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVNv4i16, ARM_INS_VMOVN: vmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVNv8i8, ARM_INS_VMOVN: vmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVRH, ARM_INS_VMOV: vmov */ + { 0 } + }, + + { /* ARM_VMOVRRD, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVRRS, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVRS, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVS, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVSR, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVSRR, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMOVv16i8, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMOVv1i64, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMOVv2f32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMOVv2i32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMOVv2i64, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMOVv4f32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMOVv4i16, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMOVv4i32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMOVv8i16, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMOVv8i8, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMRS, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMRS_FPEXC, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMRS_FPINST, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMRS_FPINST2, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMRS_FPSID, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMRS_MVFR0, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMRS_MVFR1, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMRS_MVFR2, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMSR, ARM_INS_VMSR: vmsr */ + { CS_AC_IGNORE, CS_AC_READ, 0 } + }, + + { /* ARM_VMSR_FPEXC, ARM_INS_VMSR: vmsr */ + { CS_AC_IGNORE, CS_AC_READ, 0 } + }, + + { /* ARM_VMSR_FPINST, ARM_INS_VMSR: vmsr */ + { CS_AC_IGNORE, CS_AC_READ, 0 } + }, + + { /* ARM_VMSR_FPINST2, ARM_INS_VMSR: vmsr */ + { CS_AC_IGNORE, CS_AC_READ, 0 } + }, + + { /* ARM_VMSR_FPSID, ARM_INS_VMSR: vmsr */ + { CS_AC_IGNORE, CS_AC_READ, 0 } + }, + + { /* ARM_VMULD, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULH, ARM_INS_VMUL: vmul */ + { 0 } + }, + + { /* ARM_VMULLp64, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULLp8, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULLslsv2i32, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMULLslsv4i16, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMULLsluv2i32, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMULLsluv4i16, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMULLsv2i64, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULLsv4i32, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULLsv8i16, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULLuv2i64, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULLuv4i32, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULLuv8i16, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULS, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULfd, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULfq, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULhd, ARM_INS_VMUL: vmul */ + { 0 } + }, + + { /* ARM_VMULhq, ARM_INS_VMUL: vmul */ + { 0 } + }, + + { /* ARM_VMULpd, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULpq, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULslfd, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMULslfq, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMULslhd, ARM_INS_VMUL: vmul */ + { 0 } + }, + + { /* ARM_VMULslhq, ARM_INS_VMUL: vmul */ + { 0 } + }, + + { /* ARM_VMULslv2i32, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMULslv4i16, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMULslv4i32, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMULslv8i16, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMULv16i8, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULv2i32, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULv4i16, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULv4i32, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULv8i16, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMULv8i8, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VMVNd, ARM_INS_VMVN: vmvn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMVNq, ARM_INS_VMVN: vmvn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VMVNv2i32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMVNv4i16, ARM_INS_VMVN: vmvn */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMVNv4i32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VMVNv8i16, ARM_INS_VMVN: vmvn */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_VNEGD, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VNEGH, ARM_INS_VNEG: vneg */ + { 0 } + }, + + { /* ARM_VNEGS, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VNEGf32q, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VNEGfd, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VNEGhd, ARM_INS_VNEG: vneg */ + { 0 } + }, + + { /* ARM_VNEGhq, ARM_INS_VNEG: vneg */ + { 0 } + }, + + { /* ARM_VNEGs16d, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VNEGs16q, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VNEGs32d, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VNEGs32q, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VNEGs8d, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VNEGs8q, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VNMLAD, ARM_INS_VNMLA: vnmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VNMLAH, ARM_INS_VNMLA: vnmla */ + { 0 } + }, + + { /* ARM_VNMLAS, ARM_INS_VNMLA: vnmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VNMLSD, ARM_INS_VNMLS: vnmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VNMLSH, ARM_INS_VNMLS: vnmls */ + { 0 } + }, + + { /* ARM_VNMLSS, ARM_INS_VNMLS: vnmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VNMULD, ARM_INS_VNMUL: vnmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VNMULH, ARM_INS_VNMUL: vnmul */ + { 0 } + }, + + { /* ARM_VNMULS, ARM_INS_VNMUL: vnmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VORNd, ARM_INS_VORN: vorn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VORNq, ARM_INS_VORN: vorn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VORRd, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VORRiv2i32, ARM_INS_VORR: vorr */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VORRiv4i16, ARM_INS_VORR: vorr */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VORRiv4i32, ARM_INS_VORR: vorr */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VORRiv8i16, ARM_INS_VORR: vorr */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VORRq, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPADALsv16i8, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADALsv2i32, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADALsv4i16, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADALsv4i32, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADALsv8i16, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADALsv8i8, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADALuv16i8, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADALuv2i32, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADALuv4i16, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADALuv4i32, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADALuv8i16, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADALuv8i8, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDLsv16i8, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDLsv2i32, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDLsv4i16, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDLsv4i32, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDLsv8i16, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDLsv8i8, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDLuv16i8, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDLuv2i32, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDLuv4i16, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDLuv4i32, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDLuv8i16, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDLuv8i8, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDf, ARM_INS_VPADD: vpadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDh, ARM_INS_VPADD: vpadd */ + { 0 } + }, + + { /* ARM_VPADDi16, ARM_INS_VPADD: vpadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDi32, ARM_INS_VPADD: vpadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPADDi8, ARM_INS_VPADD: vpadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMAXf, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMAXh, ARM_INS_VPMAX: vpmax */ + { 0 } + }, + + { /* ARM_VPMAXs16, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMAXs32, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMAXs8, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMAXu16, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMAXu32, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMAXu8, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMINf, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMINh, ARM_INS_VPMIN: vpmin */ + { 0 } + }, + + { /* ARM_VPMINs16, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMINs32, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMINs8, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMINu16, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMINu32, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VPMINu8, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQABSv16i8, ARM_INS_VQABS: vqabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQABSv2i32, ARM_INS_VQABS: vqabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQABSv4i16, ARM_INS_VQABS: vqabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQABSv4i32, ARM_INS_VQABS: vqabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQABSv8i16, ARM_INS_VQABS: vqabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQABSv8i8, ARM_INS_VQABS: vqabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDsv16i8, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDsv1i64, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDsv2i32, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDsv2i64, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDsv4i16, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDsv4i32, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDsv8i16, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDsv8i8, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDuv16i8, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDuv1i64, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDuv2i32, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDuv2i64, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDuv4i16, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDuv4i32, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDuv8i16, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQADDuv8i8, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL: vqdmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL: vqdmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMLALv2i64, ARM_INS_VQDMLAL: vqdmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMLALv4i32, ARM_INS_VQDMLAL: vqdmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL: vqdmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL: vqdmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL: vqdmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL: vqdmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMULHslv2i32, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMULHslv4i16, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMULHslv4i32, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMULHslv8i16, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMULHv2i32, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMULHv4i16, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMULHv4i32, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMULHv8i16, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMULLslv2i32, ARM_INS_VQDMULL: vqdmull */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMULLslv4i16, ARM_INS_VQDMULL: vqdmull */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMULLv2i64, ARM_INS_VQDMULL: vqdmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQDMULLv4i32, ARM_INS_VQDMULL: vqdmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN: vqmovun */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN: vqmovun */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN: vqmovun */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQMOVNsv2i32, ARM_INS_VQMOVN: vqmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQMOVNsv4i16, ARM_INS_VQMOVN: vqmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQMOVNsv8i8, ARM_INS_VQMOVN: vqmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQMOVNuv2i32, ARM_INS_VQMOVN: vqmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQMOVNuv4i16, ARM_INS_VQMOVN: vqmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQMOVNuv8i8, ARM_INS_VQMOVN: vqmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQNEGv16i8, ARM_INS_VQNEG: vqneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQNEGv2i32, ARM_INS_VQNEG: vqneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQNEGv4i16, ARM_INS_VQNEG: vqneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQNEGv4i32, ARM_INS_VQNEG: vqneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQNEGv8i16, ARM_INS_VQNEG: vqneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQNEGv8i8, ARM_INS_VQNEG: vqneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRDMLAHslv2i32, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } + }, + + { /* ARM_VQRDMLAHslv4i16, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } + }, + + { /* ARM_VQRDMLAHslv4i32, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } + }, + + { /* ARM_VQRDMLAHslv8i16, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } + }, + + { /* ARM_VQRDMLAHv2i32, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } + }, + + { /* ARM_VQRDMLAHv4i16, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } + }, + + { /* ARM_VQRDMLAHv4i32, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } + }, + + { /* ARM_VQRDMLAHv8i16, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } + }, + + { /* ARM_VQRDMLSHslv2i32, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } + }, + + { /* ARM_VQRDMLSHslv4i16, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } + }, + + { /* ARM_VQRDMLSHslv4i32, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } + }, + + { /* ARM_VQRDMLSHslv8i16, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } + }, + + { /* ARM_VQRDMLSHv2i32, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } + }, + + { /* ARM_VQRDMLSHv4i16, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } + }, + + { /* ARM_VQRDMLSHv4i32, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } + }, + + { /* ARM_VQRDMLSHv8i16, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } + }, + + { /* ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLsv16i8, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLsv1i64, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLsv2i32, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLsv2i64, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLsv4i16, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLsv4i32, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLsv8i16, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLsv8i8, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLuv16i8, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLuv1i64, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLuv2i32, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLuv2i64, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLuv4i16, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLuv4i32, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLuv8i16, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHLuv8i8, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN: vqrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN: vqrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN: vqrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN: vqrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN: vqrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN: vqrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN: vqrshrun */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN: vqrshrun */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN: vqrshrun */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsuv16i8, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsuv1i64, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsuv2i32, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsuv2i64, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsuv4i16, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsuv4i32, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsuv8i16, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsuv8i8, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsv2i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsv2i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsv4i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsv4i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsv8i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLsv8i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuiv16i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuiv1i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuiv2i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuiv2i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuiv4i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuiv4i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuiv8i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuiv8i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuv16i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuv1i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuv2i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuv2i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuv4i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuv4i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuv8i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHLuv8i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN: vqshrun */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN: vqshrun */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN: vqshrun */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBsv16i8, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBsv1i64, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBsv2i32, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBsv2i64, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBsv4i16, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBsv4i32, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBsv8i16, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBsv8i8, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBuv16i8, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBuv1i64, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBuv2i32, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBuv2i64, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBuv4i16, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBuv4i32, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBuv8i16, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VQSUBuv8i8, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRECPEhd, ARM_INS_VRECPE: vrecpe */ + { 0 } + }, + + { /* ARM_VRECPEhq, ARM_INS_VRECPE: vrecpe */ + { 0 } + }, + + { /* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRECPSfd, ARM_INS_VRECPS: vrecps */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRECPSfq, ARM_INS_VRECPS: vrecps */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRECPShd, ARM_INS_VRECPS: vrecps */ + { 0 } + }, + + { /* ARM_VRECPShq, ARM_INS_VRECPS: vrecps */ + { 0 } + }, + + { /* ARM_VREV16d8, ARM_INS_VREV16: vrev16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VREV16q8, ARM_INS_VREV16: vrev16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VREV32d16, ARM_INS_VREV32: vrev32 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VREV32d8, ARM_INS_VREV32: vrev32 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VREV32q16, ARM_INS_VREV32: vrev32 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VREV32q8, ARM_INS_VREV32: vrev32 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VREV64d16, ARM_INS_VREV64: vrev64 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VREV64d32, ARM_INS_VREV64: vrev64 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VREV64d8, ARM_INS_VREV64: vrev64 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VREV64q16, ARM_INS_VREV64: vrev64 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VREV64q32, ARM_INS_VREV64: vrev64 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VREV64q8, ARM_INS_VREV64: vrev64 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRHADDsv16i8, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRHADDsv2i32, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRHADDsv4i16, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRHADDsv4i32, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRHADDsv8i16, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRHADDsv8i8, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRHADDuv16i8, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRHADDuv2i32, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRHADDuv4i16, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRHADDuv4i32, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRHADDuv8i16, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRHADDuv8i8, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTAD, ARM_INS_VRINTA: vrinta */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTAH, ARM_INS_VRINTA: vrinta */ + { 0 } + }, + + { /* ARM_VRINTANDf, ARM_INS_VRINTA: vrinta */ + { 0 } + }, + + { /* ARM_VRINTANDh, ARM_INS_VRINTA: vrinta */ + { 0 } + }, + + { /* ARM_VRINTANQf, ARM_INS_VRINTA: vrinta */ + { 0 } + }, + + { /* ARM_VRINTANQh, ARM_INS_VRINTA: vrinta */ + { 0 } + }, + + { /* ARM_VRINTAS, ARM_INS_VRINTA: vrinta */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTMD, ARM_INS_VRINTM: vrintm */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTMH, ARM_INS_VRINTM: vrintm */ + { 0 } + }, + + { /* ARM_VRINTMNDf, ARM_INS_VRINTM: vrintm */ + { 0 } + }, + + { /* ARM_VRINTMNDh, ARM_INS_VRINTM: vrintm */ + { 0 } + }, + + { /* ARM_VRINTMNQf, ARM_INS_VRINTM: vrintm */ + { 0 } + }, + + { /* ARM_VRINTMNQh, ARM_INS_VRINTM: vrintm */ + { 0 } + }, + + { /* ARM_VRINTMS, ARM_INS_VRINTM: vrintm */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTND, ARM_INS_VRINTN: vrintn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTNH, ARM_INS_VRINTN: vrintn */ + { 0 } + }, + + { /* ARM_VRINTNNDf, ARM_INS_VRINTN: vrintn */ + { 0 } + }, + + { /* ARM_VRINTNNDh, ARM_INS_VRINTN: vrintn */ + { 0 } + }, + + { /* ARM_VRINTNNQf, ARM_INS_VRINTN: vrintn */ + { 0 } + }, + + { /* ARM_VRINTNNQh, ARM_INS_VRINTN: vrintn */ + { 0 } + }, + + { /* ARM_VRINTNS, ARM_INS_VRINTN: vrintn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTPD, ARM_INS_VRINTP: vrintp */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTPH, ARM_INS_VRINTP: vrintp */ + { 0 } + }, + + { /* ARM_VRINTPNDf, ARM_INS_VRINTP: vrintp */ + { 0 } + }, + + { /* ARM_VRINTPNDh, ARM_INS_VRINTP: vrintp */ + { 0 } + }, + + { /* ARM_VRINTPNQf, ARM_INS_VRINTP: vrintp */ + { 0 } + }, + + { /* ARM_VRINTPNQh, ARM_INS_VRINTP: vrintp */ + { 0 } + }, + + { /* ARM_VRINTPS, ARM_INS_VRINTP: vrintp */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTRD, ARM_INS_VRINTR: vrintr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTRH, ARM_INS_VRINTR: vrintr */ + { 0 } + }, + + { /* ARM_VRINTRS, ARM_INS_VRINTR: vrintr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTXD, ARM_INS_VRINTX: vrintx */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTXH, ARM_INS_VRINTX: vrintx */ + { 0 } + }, + + { /* ARM_VRINTXNDf, ARM_INS_VRINTX: vrintx */ + { 0 } + }, + + { /* ARM_VRINTXNDh, ARM_INS_VRINTX: vrintx */ + { 0 } + }, + + { /* ARM_VRINTXNQf, ARM_INS_VRINTX: vrintx */ + { 0 } + }, + + { /* ARM_VRINTXNQh, ARM_INS_VRINTX: vrintx */ + { 0 } + }, + + { /* ARM_VRINTXS, ARM_INS_VRINTX: vrintx */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTZD, ARM_INS_VRINTZ: vrintz */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRINTZH, ARM_INS_VRINTZ: vrintz */ + { 0 } + }, + + { /* ARM_VRINTZNDf, ARM_INS_VRINTZ: vrintz */ + { 0 } + }, + + { /* ARM_VRINTZNDh, ARM_INS_VRINTZ: vrintz */ + { 0 } + }, + + { /* ARM_VRINTZNQf, ARM_INS_VRINTZ: vrintz */ + { 0 } + }, + + { /* ARM_VRINTZNQh, ARM_INS_VRINTZ: vrintz */ + { 0 } + }, + + { /* ARM_VRINTZS, ARM_INS_VRINTZ: vrintz */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLuv2i32, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLuv2i64, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLuv4i16, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLuv4i32, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLuv8i16, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHLuv8i8, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRNv2i32, ARM_INS_VRSHRN: vrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRNv4i16, ARM_INS_VRSHRN: vrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRNv8i8, ARM_INS_VRSHRN: vrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRsv16i8, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRsv1i64, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRsv2i32, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRsv2i64, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRsv4i16, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRsv4i32, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRsv8i16, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRsv8i8, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRuv16i8, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRuv1i64, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRuv2i32, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRuv2i64, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRuv4i16, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRuv4i32, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRuv8i16, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSHRuv8i8, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSQRTEd, ARM_INS_VRSQRTE: vrsqrte */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSQRTEfd, ARM_INS_VRSQRTE: vrsqrte */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSQRTEfq, ARM_INS_VRSQRTE: vrsqrte */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSQRTEhd, ARM_INS_VRSQRTE: vrsqrte */ + { 0 } + }, + + { /* ARM_VRSQRTEhq, ARM_INS_VRSQRTE: vrsqrte */ + { 0 } + }, + + { /* ARM_VRSQRTEq, ARM_INS_VRSQRTE: vrsqrte */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSQRTSfd, ARM_INS_VRSQRTS: vrsqrts */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSQRTSfq, ARM_INS_VRSQRTS: vrsqrts */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSQRTShd, ARM_INS_VRSQRTS: vrsqrts */ + { 0 } + }, + + { /* ARM_VRSQRTShq, ARM_INS_VRSQRTS: vrsqrts */ + { 0 } + }, + + { /* ARM_VRSRAsv16i8, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAsv1i64, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAsv2i32, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAsv2i64, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAsv4i16, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAsv4i32, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAsv8i16, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAsv8i8, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAuv16i8, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAuv1i64, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAuv2i32, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAuv2i64, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAuv4i16, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAuv4i32, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAuv8i16, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSRAuv8i8, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN: vrsubhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN: vrsubhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN: vrsubhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSDOTD, ARM_INS_VSDOT: vsdot */ + { 0 } + }, + + { /* ARM_VSDOTDI, ARM_INS_VSDOT: vsdot */ + { 0 } + }, + + { /* ARM_VSDOTQ, ARM_INS_VSDOT: vsdot */ + { 0 } + }, + + { /* ARM_VSDOTQI, ARM_INS_VSDOT: vsdot */ + { 0 } + }, + + { /* ARM_VSELEQD, ARM_INS_VSELEQ: vseleq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSELEQH, ARM_INS_VSELEQ: vseleq */ + { 0 } + }, + + { /* ARM_VSELEQS, ARM_INS_VSELEQ: vseleq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSELGED, ARM_INS_VSELGE: vselge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSELGEH, ARM_INS_VSELGE: vselge */ + { 0 } + }, + + { /* ARM_VSELGES, ARM_INS_VSELGE: vselge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSELGTD, ARM_INS_VSELGT: vselgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSELGTH, ARM_INS_VSELGT: vselgt */ + { 0 } + }, + + { /* ARM_VSELGTS, ARM_INS_VSELGT: vselgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSELVSD, ARM_INS_VSELVS: vselvs */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSELVSH, ARM_INS_VSELVS: vselvs */ + { 0 } + }, + + { /* ARM_VSELVSS, ARM_INS_VSELVS: vselvs */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSETLNi16, ARM_INS_VMOV: vmov */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSETLNi32, ARM_INS_FMDHR: fmdhr */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSETLNi8, ARM_INS_VMOV: vmov */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLLi16, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLLi32, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLLi8, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLLsv2i64, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLLsv4i32, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLLsv8i16, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLLuv2i64, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLLuv4i32, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLLuv8i16, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLiv16i8, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLiv1i64, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLiv2i32, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLiv2i64, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLiv4i16, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLiv4i32, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLiv8i16, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLiv8i8, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLsv16i8, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLsv1i64, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLsv2i32, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLsv2i64, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLsv4i16, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLsv4i32, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLsv8i16, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLsv8i8, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLuv16i8, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLuv1i64, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLuv2i32, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLuv2i64, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLuv4i16, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLuv4i32, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLuv8i16, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHLuv8i8, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRNv2i32, ARM_INS_VSHRN: vshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRNv4i16, ARM_INS_VSHRN: vshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRNv8i8, ARM_INS_VSHRN: vshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRuv2i32, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRuv2i64, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRuv4i16, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRuv4i32, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRuv8i16, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHRuv8i8, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSHTOD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VSHTOH, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VSHTOS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VSITOD, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSITOH, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VSITOS, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSLIv16i8, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSLIv1i64, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSLIv2i32, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSLIv2i64, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSLIv4i16, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSLIv4i32, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSLIv8i16, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSLIv8i8, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSLTOD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VSLTOH, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VSLTOS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VSQRTD, ARM_INS_VSQRT: vsqrt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSQRTH, ARM_INS_VSQRT: vsqrt */ + { 0 } + }, + + { /* ARM_VSQRTS, ARM_INS_VSQRT: vsqrt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAsv16i8, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAsv1i64, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAsv2i32, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAsv2i64, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAsv4i16, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAsv4i32, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAsv8i16, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAsv8i8, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAuv16i8, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAuv1i64, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAuv2i32, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAuv2i64, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAuv4i16, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAuv4i32, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAuv8i16, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRAuv8i8, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRIv16i8, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRIv1i64, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRIv2i32, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRIv2i64, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRIv4i16, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRIv4i32, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRIv8i16, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VSRIv8i8, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VST1LNd16, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1LNd16_UPD, ARM_INS_VST1: vst1 */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VST1LNd32, ARM_INS_VST1: vst1 */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VST1LNd32_UPD, ARM_INS_VST1: vst1 */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VST1LNd8, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1LNd8_UPD, ARM_INS_VST1: vst1 */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VST1d16, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d16Q, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d16Qwb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d16Qwb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d16T, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d16Twb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d16Twb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d16wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d16wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d32, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d32Q, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d32Qwb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d32Qwb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d32T, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d32Twb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d32Twb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d32wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d32wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d64, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d64Q, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d64Qwb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d64Qwb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d64T, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d64Twb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d64Twb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d64wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d64wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d8, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d8Q, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d8Qwb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d8Qwb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d8T, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d8Twb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d8Twb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d8wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1d8wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1q16, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1q16wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1q16wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1q32, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1q32wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1q32wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1q64, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1q64wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1q64wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1q8, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1q8wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST1q8wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2LNd16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2LNd16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2LNd32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2LNd32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2LNd8, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane] $src2[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2LNd8_UPD, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane] $src2[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2LNq16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2LNq16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2LNq32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2LNq32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2b16, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2b16wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2b16wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2b32, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2b32wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2b32wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2b8, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2b8wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2b8wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2d16, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2d16wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2d16wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2d32, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2d32wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2d32wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2d8, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2d8wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2d8wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2q16, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2q16wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2q16wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2q32, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2q32wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2q32wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2q8, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2q8wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST2q8wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3LNd16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3LNd16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3LNd32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3LNd32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3LNd8, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3LNd8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3LNq16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3LNq16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3LNq32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3LNq32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3d16, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3d16_UPD, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3d32, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3d32_UPD, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3d8, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3d8_UPD, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3q16, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3q16_UPD, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3q32, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3q32_UPD, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3q8, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST3q8_UPD, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4LNd16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4LNd16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4LNd32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4LNd32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4LNd8, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4LNd8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4LNq16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4LNq16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4LNq32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4LNq32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4d16, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4d16_UPD, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4d32, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4d32_UPD, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4d8, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4d8_UPD, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4q16, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4q16_UPD, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4q32, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4q32_UPD, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4q8, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VST4q8_UPD, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSTMDDB_UPD, ARM_INS_VPUSH: vpush */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VSTMDIA, ARM_INS_VSTMIA: vstmia */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VSTMDIA_UPD, ARM_INS_VSTMIA: vstmia */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VSTMSDB_UPD, ARM_INS_VPUSH: vpush */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VSTMSIA, ARM_INS_VSTMIA: vstmia */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VSTMSIA_UPD, ARM_INS_VSTMIA: vstmia */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VSTRD, ARM_INS_VSTR: vstr */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VSTRH, ARM_INS_VSTR: vstr */ + { 0 } + }, + + { /* ARM_VSTRS, ARM_INS_VSTR: vstr */ + { CS_AC_READ, 0 } + }, + + { /* ARM_VSUBD, ARM_INS_FSUBD: fsubd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBH, ARM_INS_VSUB: vsub */ + { 0 } + }, + + { /* ARM_VSUBHNv2i32, ARM_INS_VSUBHN: vsubhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBHNv4i16, ARM_INS_VSUBHN: vsubhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBHNv8i8, ARM_INS_VSUBHN: vsubhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBLsv2i64, ARM_INS_VSUBL: vsubl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBLsv4i32, ARM_INS_VSUBL: vsubl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBLsv8i16, ARM_INS_VSUBL: vsubl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBLuv2i64, ARM_INS_VSUBL: vsubl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBLuv4i32, ARM_INS_VSUBL: vsubl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBLuv8i16, ARM_INS_VSUBL: vsubl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBS, ARM_INS_FSUBS: fsubs */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBWsv2i64, ARM_INS_VSUBW: vsubw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBWsv4i32, ARM_INS_VSUBW: vsubw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBWsv8i16, ARM_INS_VSUBW: vsubw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBWuv2i64, ARM_INS_VSUBW: vsubw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBWuv4i32, ARM_INS_VSUBW: vsubw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBWuv8i16, ARM_INS_VSUBW: vsubw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBfd, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBfq, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBhd, ARM_INS_VSUB: vsub */ + { 0 } + }, + + { /* ARM_VSUBhq, ARM_INS_VSUB: vsub */ + { 0 } + }, + + { /* ARM_VSUBv16i8, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBv1i64, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBv2i32, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBv2i64, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBv4i16, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBv4i32, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBv8i16, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSUBv8i8, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VSWPd, ARM_INS_VSWP: vswp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VSWPq, ARM_INS_VSWP: vswp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VTBL1, ARM_INS_VTBL: vtbl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTBL2, ARM_INS_VTBL: vtbl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTBL3, ARM_INS_VTBL: vtbl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTBL4, ARM_INS_VTBL: vtbl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTBX1, ARM_INS_VTBX: vtbx */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTBX2, ARM_INS_VTBX: vtbx */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTBX3, ARM_INS_VTBX: vtbx */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTBX4, ARM_INS_VTBX: vtbx */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTOSHD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VTOSHH, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VTOSHS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VTOSIRD, ARM_INS_VCVTR: vcvtr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VTOSIRH, ARM_INS_VCVTR: vcvtr */ + { 0 } + }, + + { /* ARM_VTOSIRS, ARM_INS_VCVTR: vcvtr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VTOSIZD, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VTOSIZH, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VTOSIZS, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VTOSLD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VTOSLH, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VTOSLS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VTOUHD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VTOUHH, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VTOUHS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VTOUIRD, ARM_INS_VCVTR: vcvtr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VTOUIRH, ARM_INS_VCVTR: vcvtr */ + { 0 } + }, + + { /* ARM_VTOUIRS, ARM_INS_VCVTR: vcvtr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VTOUIZD, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VTOUIZH, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VTOUIZS, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VTOULD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VTOULH, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VTOULS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VTRNd16, ARM_INS_VTRN: vtrn */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VTRNd32, ARM_INS_VTRN: vtrn */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VTRNd8, ARM_INS_VTRN: vtrn */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VTRNq16, ARM_INS_VTRN: vtrn */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VTRNq32, ARM_INS_VTRN: vtrn */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VTRNq8, ARM_INS_VTRN: vtrn */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VTSTv16i8, ARM_INS_VTST: vtst */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTSTv2i32, ARM_INS_VTST: vtst */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTSTv4i16, ARM_INS_VTST: vtst */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTSTv4i32, ARM_INS_VTST: vtst */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTSTv8i16, ARM_INS_VTST: vtst */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VTSTv8i8, ARM_INS_VTST: vtst */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_VUDOTD, ARM_INS_VUDOT: vudot */ + { 0 } + }, + + { /* ARM_VUDOTDI, ARM_INS_VUDOT: vudot */ + { 0 } + }, + + { /* ARM_VUDOTQ, ARM_INS_VUDOT: vudot */ + { 0 } + }, + + { /* ARM_VUDOTQI, ARM_INS_VUDOT: vudot */ + { 0 } + }, + + { /* ARM_VUHTOD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VUHTOH, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VUHTOS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VUITOD, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VUITOH, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VUITOS, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_VULTOD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VULTOH, ARM_INS_VCVT: vcvt */ + { 0 } + }, + + { /* ARM_VULTOS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_VUZPd16, ARM_INS_VUZP: vuzp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VUZPd8, ARM_INS_VUZP: vuzp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VUZPq16, ARM_INS_VUZP: vuzp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VUZPq32, ARM_INS_VUZP: vuzp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VUZPq8, ARM_INS_VUZP: vuzp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VZIPd16, ARM_INS_VZIP: vzip */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VZIPd8, ARM_INS_VZIP: vzip */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VZIPq16, ARM_INS_VZIP: vzip */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VZIPq32, ARM_INS_VZIP: vzip */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_VZIPq8, ARM_INS_VZIP: vzip */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_sysLDMDA, ARM_INS_LDMDA: ldmda */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_sysLDMDA_UPD, ARM_INS_LDMDA: ldmda */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_sysLDMDB, ARM_INS_LDMDB: ldmdb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_sysLDMDB_UPD, ARM_INS_LDMDB: ldmdb */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_sysLDMIA, ARM_INS_LDM: ldm */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_sysLDMIA_UPD, ARM_INS_LDM: ldm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_sysLDMIB, ARM_INS_LDMIB: ldmib */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_sysLDMIB_UPD, ARM_INS_LDMIB: ldmib */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_sysSTMDA, ARM_INS_STMDA: stmda */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_sysSTMDA_UPD, ARM_INS_STMDA: stmda */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_sysSTMDB, ARM_INS_STMDB: stmdb */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_sysSTMDB_UPD, ARM_INS_STMDB: stmdb */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_sysSTMIA, ARM_INS_STM: stm */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_sysSTMIA_UPD, ARM_INS_STM: stm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_sysSTMIB, ARM_INS_STMIB: stmib */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_sysSTMIB_UPD, ARM_INS_STMIB: stmib */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2ADCri, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2ADCrr, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2ADCrs, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2ADDri, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2ADDri12, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2ADDrr, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2ADDrs, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2ADR, ARM_INS_ADD: add */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2ANDri, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2ANDrr, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2ANDrs, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2ASRri, ARM_INS_ASR: asr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2ASRrr, ARM_INS_ASR: asr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2B, ARM_INS_B: b */ + { 0 } + }, + + { /* ARM_t2BFC, ARM_INS_BFC: bfc */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_t2BFI, ARM_INS_BFI: bfi */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2BICri, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2BICrr, ARM_INS_BIC: bic */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2BICrs, ARM_INS_BIC: bic */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2BXJ, ARM_INS_BXJ: bxj */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2Bcc, ARM_INS_B: b */ + { 0 } + }, + + { /* ARM_t2CDP, ARM_INS_CDP: cdp */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0 } + }, + + { /* ARM_t2CDP2, ARM_INS_CDP2: cdp2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0 } + }, + + { /* ARM_t2CLREX, ARM_INS_CLREX: clrex */ + { 0 } + }, + + { /* ARM_t2CLZ, ARM_INS_CLZ: clz */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2CMNri, ARM_INS_CMN: cmn */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2CMNzrr, ARM_INS_CMN: cmn */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2CMNzrs, ARM_INS_CMN: cmn */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2CMPri, ARM_INS_CMN: cmn */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2CMPrr, ARM_INS_CMP: cmp */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2CMPrs, ARM_INS_CMP: cmp */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2CPS1p, ARM_INS_CPS: cps */ + { 0 } + }, + + { /* ARM_t2CPS2p, ARM_INS_CPS: cps */ + { 0 } + }, + + { /* ARM_t2CPS3p, ARM_INS_CPS: cps */ + { 0 } + }, + + { /* ARM_t2CRC32B, ARM_INS_CRC32B: crc32b */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2CRC32CB, ARM_INS_CRC32CB: crc32cb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2CRC32CH, ARM_INS_CRC32CH: crc32ch */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2CRC32CW, ARM_INS_CRC32CW: crc32cw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2CRC32H, ARM_INS_CRC32H: crc32h */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2CRC32W, ARM_INS_CRC32W: crc32w */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2DBG, ARM_INS_DBG: dbg */ + { 0 } + }, + + { /* ARM_t2DCPS1, ARM_INS_DCPS1: dcps1 */ + { 0 } + }, + + { /* ARM_t2DCPS2, ARM_INS_DCPS2: dcps2 */ + { 0 } + }, + + { /* ARM_t2DCPS3, ARM_INS_DCPS3: dcps3 */ + { 0 } + }, + + { /* ARM_t2DMB, ARM_INS_DMB: dmb */ + { 0 } + }, + + { /* ARM_t2DSB, ARM_INS_DFB: dfb */ + { 0 } + }, + + { /* ARM_t2EORri, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2EORrr, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2EORrs, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2HINT, ARM_INS_CSDB: csdb */ + { 0 } + }, + + { /* ARM_t2HVC, ARM_INS_HVC: hvc */ + { 0 } + }, + + { /* ARM_t2ISB, ARM_INS_ISB: isb */ + { 0 } + }, + + { /* ARM_t2IT, ARM_INS_IT: it */ + { 0 } + }, + + { /* ARM_t2LDA, ARM_INS_LDA: lda */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDAB, ARM_INS_LDAB: ldab */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDAEX, ARM_INS_LDAEX: ldaex */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDAEXB, ARM_INS_LDAEXB: ldaexb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDAEXD, ARM_INS_LDAEXD: ldaexd */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDAEXH, ARM_INS_LDAEXH: ldaexh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDAH, ARM_INS_LDAH: ldah */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDC2L_OPTION, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDC2L_POST, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDC2L_PRE, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDC2_OFFSET, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDC2_OPTION, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDC2_POST, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDC2_PRE, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDC_OFFSET, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDC_OPTION, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDC_POST, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDC_PRE, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDMDB, ARM_INS_LDMDB: ldmdb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDMDB_UPD, ARM_INS_LDMDB: ldmdb */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDMIA, ARM_INS_LDM: ldm */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDMIA_UPD, ARM_INS_LDM: ldm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRBT, ARM_INS_LDRBT: ldrbt */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRB_POST, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRB_PRE, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRBi12, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRBi8, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRBpci, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRBs, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRD_POST, ARM_INS_LDRD: ldrd */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRD_PRE, ARM_INS_LDRD: ldrd */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRDi8, ARM_INS_LDRD: ldrd */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDREX, ARM_INS_LDREX: ldrex */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDREXB, ARM_INS_LDREXB: ldrexb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDREXD, ARM_INS_LDREXD: ldrexd */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDREXH, ARM_INS_LDREXH: ldrexh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRHT, ARM_INS_LDRHT: ldrht */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRH_POST, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRH_PRE, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRHi12, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRHi8, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRHpci, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRHs, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRSBT, ARM_INS_LDRSBT: ldrsbt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRSB_POST, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRSB_PRE, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRSBi12, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRSBi8, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRSBpci, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRSBs, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRSHT, ARM_INS_LDRSHT: ldrsht */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRSH_POST, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRSH_PRE, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRSHi12, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRSHi8, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRSHpci, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRSHs, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LDRT, ARM_INS_LDRT: ldrt */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDR_POST, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDR_PRE, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRi12, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRi8, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRpci, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2LDRs, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LSLri, ARM_INS_LSL: lsl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LSLrr, ARM_INS_LSL: lsl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2LSRri, ARM_INS_LSR: lsr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2LSRrr, ARM_INS_LSR: lsr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2MCR, ARM_INS_MCR: mcr */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0 } + }, + + { /* ARM_t2MCR2, ARM_INS_MCR2: mcr2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0 } + }, + + { /* ARM_t2MCRR, ARM_INS_MCRR: mcrr */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2MCRR2, ARM_INS_MCRR2: mcrr2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2MLA, ARM_INS_MLA: mla */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2MLS, ARM_INS_MLS: mls */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2MOVTi16, ARM_INS_MOVT: movt */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_t2MOVi, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2MOVi16, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2MOVr, ARM_INS_LSL: lsl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2MOVsra_flag, ARM_INS_ASR: asrs${p}.w $rd $rm #1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2MOVsrl_flag, ARM_INS_LSR: lsrs${p}.w $rd $rm #1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2MRC, ARM_INS_MRC: mrc */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0 } + }, + + { /* ARM_t2MRC2, ARM_INS_MRC2: mrc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0 } + }, + + { /* ARM_t2MRRC, ARM_INS_MRRC: mrrc */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2MRRC2, ARM_INS_MRRC2: mrrc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2MRS_AR, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2MRS_M, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2MRSbanked, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2MRSsys_AR, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2MSR_AR, ARM_INS_MSR: msr */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2MSR_M, ARM_INS_MSR: msr */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2MSRbanked, ARM_INS_MSR: msr */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2MUL, ARM_INS_MUL: mul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2MVNi, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2MVNr, ARM_INS_MVN: mvn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2MVNs, ARM_INS_MVN: mvn */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2ORNri, ARM_INS_ORN: orn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2ORNrr, ARM_INS_ORN: orn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2ORNrs, ARM_INS_ORN: orn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2ORRri, ARM_INS_ORN: orn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2ORRrr, ARM_INS_ORR: orr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2ORRrs, ARM_INS_ORR: orr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2PKHBT, ARM_INS_PKHBT: pkhbt */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2PKHTB, ARM_INS_PKHTB: pkhtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2PLDWi12, ARM_INS_PLDW: pldw */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2PLDWi8, ARM_INS_PLDW: pldw */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2PLDWs, ARM_INS_PLDW: pldw */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2PLDi12, ARM_INS_PLD: pld */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2PLDi8, ARM_INS_PLD: pld */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2PLDpci, ARM_INS_PLD: pld */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2PLDs, ARM_INS_PLD: pld */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2PLIi12, ARM_INS_PLI: pli */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2PLIi8, ARM_INS_PLI: pli */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2PLIpci, ARM_INS_PLI: pli */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2PLIs, ARM_INS_PLI: pli */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2QADD, ARM_INS_QADD: qadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2QADD16, ARM_INS_QADD16: qadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2QADD8, ARM_INS_QADD8: qadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2QASX, ARM_INS_QASX: qasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2QDADD, ARM_INS_QDADD: qdadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2QDSUB, ARM_INS_QDSUB: qdsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2QSAX, ARM_INS_QSAX: qsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2QSUB, ARM_INS_QSUB: qsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2QSUB16, ARM_INS_QSUB16: qsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2QSUB8, ARM_INS_QSUB8: qsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2RBIT, ARM_INS_RBIT: rbit */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2REV, ARM_INS_REV: rev */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2REV16, ARM_INS_REV16: rev16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2REVSH, ARM_INS_REVSH: revsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2RFEDB, ARM_INS_RFEDB: rfedb */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2RFEDBW, ARM_INS_RFEDB: rfedb */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2RFEIA, ARM_INS_RFEIA: rfeia */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2RFEIAW, ARM_INS_RFEIA: rfeia */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2RORri, ARM_INS_ROR: ror */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2RORrr, ARM_INS_ROR: ror */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2RRX, ARM_INS_RRX: rrx */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2RSBri, ARM_INS_NEG: neg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2RSBrr, ARM_INS_RSB: rsb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2RSBrs, ARM_INS_RSB: rsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SADD16, ARM_INS_SADD16: sadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SADD8, ARM_INS_SADD8: sadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SASX, ARM_INS_SASX: sasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SBCri, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SBCrr, ARM_INS_SBC: sbc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SBCrs, ARM_INS_SBC: sbc */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SBFX, ARM_INS_SBFX: sbfx */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SDIV, ARM_INS_SDIV: sdiv */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SEL, ARM_INS_SEL: sel */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SETPAN, ARM_INS_SETPAN: setpan */ + { 0 } + }, + + { /* ARM_t2SG, ARM_INS_SG: sg */ + { 0 } + }, + + { /* ARM_t2SHADD16, ARM_INS_SHADD16: shadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SHADD8, ARM_INS_SHADD8: shadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SHASX, ARM_INS_SHASX: shasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SHSAX, ARM_INS_SHSAX: shsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SHSUB16, ARM_INS_SHSUB16: shsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SHSUB8, ARM_INS_SHSUB8: shsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMC, ARM_INS_SMC: smc */ + { 0 } + }, + + { /* ARM_t2SMLABB, ARM_INS_SMLABB: smlabb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLABT, ARM_INS_SMLABT: smlabt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLAD, ARM_INS_SMLAD: smlad */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLADX, ARM_INS_SMLADX: smladx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLAL, ARM_INS_SMLAL: smlal */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLALBB, ARM_INS_SMLALBB: smlalbb */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLALBT, ARM_INS_SMLALBT: smlalbt */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLALD, ARM_INS_SMLALD: smlald */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLALDX, ARM_INS_SMLALDX: smlaldx */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLALTB, ARM_INS_SMLALTB: smlaltb */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLALTT, ARM_INS_SMLALTT: smlaltt */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLATB, ARM_INS_SMLATB: smlatb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLATT, ARM_INS_SMLATT: smlatt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLAWB, ARM_INS_SMLAWB: smlawb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLAWT, ARM_INS_SMLAWT: smlawt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLSD, ARM_INS_SMLSD: smlsd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLSDX, ARM_INS_SMLSDX: smlsdx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLSLD, ARM_INS_SMLSLD: smlsld */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMLSLDX, ARM_INS_SMLSLDX: smlsldx */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMMLA, ARM_INS_SMMLA: smmla */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMMLAR, ARM_INS_SMMLAR: smmlar */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMMLS, ARM_INS_SMMLS: smmls */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMMLSR, ARM_INS_SMMLSR: smmlsr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMMUL, ARM_INS_SMMUL: smmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMMULR, ARM_INS_SMMULR: smmulr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMUADX, ARM_INS_SMUADX: smuadx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMULBB, ARM_INS_SMULBB: smulbb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMULBT, ARM_INS_SMULBT: smulbt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMULL, ARM_INS_SMULL: smull */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMULTB, ARM_INS_SMULTB: smultb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMULTT, ARM_INS_SMULTT: smultt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMULWB, ARM_INS_SMULWB: smulwb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMULWT, ARM_INS_SMULWT: smulwt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMUSD, ARM_INS_SMUSD: smusd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SMUSDX, ARM_INS_SMUSDX: smusdx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SRSDB, ARM_INS_SRSDB: srsdb */ + { 0 } + }, + + { /* ARM_t2SRSDB_UPD, ARM_INS_SRSDB: srsdb */ + { 0 } + }, + + { /* ARM_t2SRSIA, ARM_INS_SRSIA: srsia */ + { 0 } + }, + + { /* ARM_t2SRSIA_UPD, ARM_INS_SRSIA: srsia */ + { 0 } + }, + + { /* ARM_t2SSAT, ARM_INS_SSAT: ssat */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2SSAT16, ARM_INS_SSAT16: ssat16 */ + { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SSAX, ARM_INS_SSAX: ssax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SSUB16, ARM_INS_SSUB16: ssub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SSUB8, ARM_INS_SSUB8: ssub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STC2L_OFFSET, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STC2L_OPTION, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STC2L_POST, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STC2L_PRE, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STC2_OFFSET, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STC2_OPTION, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STC2_POST, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STC2_PRE, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STCL_POST, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STCL_PRE, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STC_OFFSET, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STC_OPTION, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STC_POST, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STC_PRE, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STL, ARM_INS_STL: stl */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STLB, ARM_INS_STLB: stlb */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STLEX, ARM_INS_STLEX: stlex */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STLEXB, ARM_INS_STLEXB: stlexb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STLEXD, ARM_INS_STLEXD: stlexd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STLEXH, ARM_INS_STLEXH: stlexh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STLH, ARM_INS_STLH: stlh */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STMDB, ARM_INS_STMDB: stmdb */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STMDB_UPD, ARM_INS_PUSH: push */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STMIA, ARM_INS_STM: stm */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STMIA_UPD, ARM_INS_STM: stm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2STRBT, ARM_INS_STRBT: strbt */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRB_POST, ARM_INS_STRB: strb */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2STRB_PRE, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRBi12, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRBi8, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRBs, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRD_POST, ARM_INS_STRD: strd */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STRD_PRE, ARM_INS_STRD: strd */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STRDi8, ARM_INS_STRD: strd */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STREX, ARM_INS_STREX: strex */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2STREXB, ARM_INS_STREXB: strexb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STREXD, ARM_INS_STREXD: strexd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STREXH, ARM_INS_STREXH: strexh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2STRHT, ARM_INS_STRHT: strht */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRH_POST, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRH_PRE, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRHi12, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRHi8, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRHs, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRT, ARM_INS_STRT: strt */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STR_POST, ARM_INS_STR: str */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2STR_PRE, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRi12, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRi8, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2STRs, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_t2SUBS_PC_LR, ARM_INS_ERET: eret */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SUBri, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SUBri12, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SUBrr, ARM_INS_SUB: sub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2SUBrs, ARM_INS_SUB: sub */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SXTAB, ARM_INS_SXTAB: sxtab */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SXTAB16, ARM_INS_SXTAB16: sxtab16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SXTAH, ARM_INS_SXTAH: sxtah */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SXTB, ARM_INS_SXTB: sxtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SXTB16, ARM_INS_SXTB16: sxtb16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2SXTH, ARM_INS_SXTH: sxth */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2TBB, ARM_INS_TBB: tbb */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2TBH, ARM_INS_TBH: tbh */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2TEQri, ARM_INS_TEQ: teq */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2TEQrr, ARM_INS_TEQ: teq */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2TEQrs, ARM_INS_TEQ: teq */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2TSB, ARM_INS_TSB: tsb */ + { 0 } + }, + + { /* ARM_t2TSTri, ARM_INS_TST: tst */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2TSTrr, ARM_INS_TST: tst */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2TSTrs, ARM_INS_TST: tst */ + { CS_AC_READ, 0 } + }, + + { /* ARM_t2TT, ARM_INS_TT: tt */ + { 0 } + }, + + { /* ARM_t2TTA, ARM_INS_TTA: tta */ + { 0 } + }, + + { /* ARM_t2TTAT, ARM_INS_TTAT: ttat */ + { 0 } + }, + + { /* ARM_t2TTT, ARM_INS_TTT: ttt */ + { 0 } + }, + + { /* ARM_t2UADD16, ARM_INS_UADD16: uadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UADD8, ARM_INS_UADD8: uadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UASX, ARM_INS_UASX: uasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UBFX, ARM_INS_UBFX: ubfx */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2UDF, ARM_INS_UDF: udf */ + { 0 } + }, + + { /* ARM_t2UDIV, ARM_INS_UDIV: udiv */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UHADD16, ARM_INS_UHADD16: uhadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UHADD8, ARM_INS_UHADD8: uhadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UHASX, ARM_INS_UHASX: uhasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UHSAX, ARM_INS_UHSAX: uhsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UHSUB16, ARM_INS_UHSUB16: uhsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UHSUB8, ARM_INS_UHSUB8: uhsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UMAAL, ARM_INS_UMAAL: umaal */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UMLAL, ARM_INS_UMLAL: umlal */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UMULL, ARM_INS_UMULL: umull */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UQADD16, ARM_INS_UQADD16: uqadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UQADD8, ARM_INS_UQADD8: uqadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UQASX, ARM_INS_UQASX: uqasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UQSAX, ARM_INS_UQSAX: uqsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UQSUB16, ARM_INS_UQSUB16: uqsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UQSUB8, ARM_INS_UQSUB8: uqsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2USAD8, ARM_INS_USAD8: usad8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2USADA8, ARM_INS_USADA8: usada8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2USAT, ARM_INS_USAT: usat */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_t2USAT16, ARM_INS_USAT16: usat16 */ + { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } + }, + + { /* ARM_t2USAX, ARM_INS_USAX: usax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2USUB16, ARM_INS_USUB16: usub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2USUB8, ARM_INS_USUB8: usub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_t2UXTAB, ARM_INS_UXTAB: uxtab */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2UXTAB16, ARM_INS_UXTAB16: uxtab16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2UXTAH, ARM_INS_UXTAH: uxtah */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2UXTB, ARM_INS_UXTB: uxtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2UXTB16, ARM_INS_UXTB16: uxtb16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_t2UXTH, ARM_INS_UXTH: uxth */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tADC, ARM_INS_ADC: adc */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tADDhirr, ARM_INS_ADD: add */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tADDi3, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tADDi8, ARM_INS_ADD: add */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_tADDrSP, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_tADDrSPi, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tADDrr, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_tADDspi, ARM_INS_ADD: add */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_tADDspr, ARM_INS_ADD: add */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tADR, ARM_INS_ADR: adr */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_tAND, ARM_INS_AND: and */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tASRri, ARM_INS_ASR: asr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tASRrr, ARM_INS_ASR: asr */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tB, ARM_INS_B: b */ + { 0 } + }, + + { /* ARM_tBIC, ARM_INS_BIC: bic */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tBKPT, ARM_INS_BKPT: bkpt */ + { 0 } + }, + + { /* ARM_tBL, ARM_INS_BL: bl */ + { 0 } + }, + + { /* ARM_tBLXNSr, ARM_INS_BLXNS: blxns */ + { 0 } + }, + + { /* ARM_tBLXi, ARM_INS_BLX: blx */ + { 0 } + }, + + { /* ARM_tBLXr, ARM_INS_BLX: blx */ + { CS_AC_READ, 0 } + }, + + { /* ARM_tBX, ARM_INS_BX: bx */ + { CS_AC_READ, 0 } + }, + + { /* ARM_tBXNS, ARM_INS_BXNS: bxns */ + { 0 } + }, + + { /* ARM_tBcc, ARM_INS_B: b */ + { 0 } + }, + + { /* ARM_tCBNZ, ARM_INS_CBNZ: cbnz */ + { CS_AC_READ, 0 } + }, + + { /* ARM_tCBZ, ARM_INS_CBZ: cbz */ + { CS_AC_READ, 0 } + }, + + { /* ARM_tCMNz, ARM_INS_CMN: cmn */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_tCMPhir, ARM_INS_CMP: cmp */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_tCMPi8, ARM_INS_CMP: cmp */ + { CS_AC_READ, 0 } + }, + + { /* ARM_tCMPr, ARM_INS_CMP: cmp */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_tCPS, ARM_INS_CPS: cps */ + { 0 } + }, + + { /* ARM_tEOR, ARM_INS_EOR: eor */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tHINT, ARM_INS_HINT: hint */ + { 0 } + }, + + { /* ARM_tHLT, ARM_INS_HLT: hlt */ + { 0 } + }, + + { /* ARM_tLDMIA, ARM_INS_LDM: ldm */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_tLDRBi, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_tLDRBr, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_tLDRHi, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_tLDRHr, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_tLDRSB, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_tLDRSH, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_tLDRi, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tLDRpci, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tLDRr, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tLDRspi, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tLSLri, ARM_INS_LSL: lsl */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tLSLrr, ARM_INS_LSL: lsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tLSRri, ARM_INS_LSR: lsr */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tLSRrr, ARM_INS_LSR: lsr */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tMOVSr, ARM_INS_MOVS: movs */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tMOVi8, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_tMOVr, ARM_INS_MOV: mov */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tMUL, ARM_INS_MUL: mul */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_tMVN, ARM_INS_MVN: mvn */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tORR, ARM_INS_ORR: orr */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tPOP, ARM_INS_POP: pop */ + { CS_AC_WRITE, 0 } + }, + + { /* ARM_tPUSH, ARM_INS_PUSH: push */ + { CS_AC_READ, 0 } + }, + + { /* ARM_tREV, ARM_INS_REV: rev */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tREV16, ARM_INS_REV16: rev16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tREVSH, ARM_INS_REVSH: revsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tROR, ARM_INS_ROR: ror */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tRSB, ARM_INS_NEG: neg */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tSBC, ARM_INS_SBC: sbc */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tSETEND, ARM_INS_SETEND: setend */ + { 0 } + }, + + { /* ARM_tSTMIA_UPD, ARM_INS_STM: stm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tSTRBi, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_tSTRBr, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_tSTRHi, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_tSTRHr, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_tSTRi, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_tSTRr, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_tSTRspi, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } + }, + + { /* ARM_tSUBi3, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tSUBi8, ARM_INS_ADD: add */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_tSUBrr, ARM_INS_SUB: sub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_tSUBspi, ARM_INS_ADD: add */ + { CS_AC_READ | CS_AC_WRITE, 0 } + }, + + { /* ARM_tSVC, ARM_INS_SVC: svc */ + { 0 } + }, + + { /* ARM_tSXTB, ARM_INS_SXTB: sxtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tSXTH, ARM_INS_SXTH: sxth */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tTRAP, ARM_INS_TRAP: trap */ + { 0 } + }, + + { /* ARM_tTST, ARM_INS_TST: tst */ + { CS_AC_READ, CS_AC_READ, 0 } + }, + + { /* ARM_tUDF, ARM_INS_UDF: udf */ + { 0 } + }, + + { /* ARM_tUXTB, ARM_INS_UXTB: uxtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, + + { /* ARM_tUXTH, ARM_INS_UXTH: uxth */ + { CS_AC_WRITE, CS_AC_READ, 0 } + }, diff --git a/thirdparty/capstone/arch/ARM/ARMModule.c b/thirdparty/capstone/arch/ARM/ARMModule.c new file mode 100644 index 0000000..4fe4042 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMModule.c @@ -0,0 +1,52 @@ +/* Capstone Disassembly Engine */ +/* By Dang Hoang Vu 2013 */ + +#include "capstone/capstone.h" +#ifdef CAPSTONE_HAS_ARM + +#include "ARMModule.h" +#include "../../MCRegisterInfo.h" +#include "../../cs_priv.h" +#include "ARMInstPrinter.h" +#include "ARMMapping.h" + +cs_err ARM_global_init(cs_struct *ud) +{ + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); + + ARM_init_mri(mri); + + ud->printer = ARM_printer; + ud->printer_info = mri; + ud->reg_name = ARM_reg_name; + ud->insn_id = ARM_get_insn_id; + ud->insn_name = ARM_insn_name; + ud->group_name = ARM_group_name; + ud->post_printer = NULL; +#ifndef CAPSTONE_DIET + ud->reg_access = ARM_reg_access; +#endif + + ud->disasm = ARM_getInstruction; + + return CS_ERR_OK; +} + +cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + switch (type) { + case CS_OPT_MODE: + handle->mode = (cs_mode)value; + break; + case CS_OPT_SYNTAX: + handle->syntax |= (int)value; + break; + default: + break; + } + + return CS_ERR_OK; +} + +#endif diff --git a/thirdparty/capstone/arch/ARM/ARMModule.h b/thirdparty/capstone/arch/ARM/ARMModule.h new file mode 100644 index 0000000..f844972 --- /dev/null +++ b/thirdparty/capstone/arch/ARM/ARMModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer , 2018 */ + +#ifndef CS_ARM_MODULE_H +#define CS_ARM_MODULE_H + +#include "../../utils.h" + +cs_err ARM_global_init(cs_struct *ud); +cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/thirdparty/capstone/arch/X86/X86ATTInstPrinter.c b/thirdparty/capstone/arch/X86/X86ATTInstPrinter.c new file mode 100644 index 0000000..6bff620 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86ATTInstPrinter.c @@ -0,0 +1,1000 @@ +//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file includes code for rendering MCInst instances as AT&T-style +// assembly. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +// this code is only relevant when DIET mode is disable +#if defined(CAPSTONE_HAS_X86) && !defined(CAPSTONE_DIET) && !defined(CAPSTONE_X86_ATT_DISABLE) + +#ifdef _MSC_VER +#pragma warning(disable:4996) // disable MSVC's warning on strncpy() +#pragma warning(disable:28719) // disable MSVC's warning on strncpy() +#endif + +#if !defined(CAPSTONE_HAS_OSXKERNEL) +#include +#endif +#include + +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#include +#else +#include +#include +#endif + +#include + +#include "../../utils.h" +#include "../../MCInst.h" +#include "../../SStream.h" +#include "../../MCRegisterInfo.h" +#include "X86Mapping.h" +#include "X86BaseInfo.h" +#include "X86InstPrinterCommon.h" + +#define GET_INSTRINFO_ENUM +#ifdef CAPSTONE_X86_REDUCE +#include "X86GenInstrInfo_reduce.inc" +#else +#include "X86GenInstrInfo.inc" +#endif + +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" + +static void printMemReference(MCInst *MI, unsigned Op, SStream *O); +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); + + +static void set_mem_access(MCInst *MI, bool status) +{ + if (MI->csh->detail_opt != CS_OPT_ON) + return; + + MI->csh->doing_mem = status; + if (!status) + // done, create the next operand slot + MI->flat_insn->detail->x86.op_count++; +} + +static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) +{ + switch(MI->csh->mode) { + case CS_MODE_16: + switch(MI->flat_insn->id) { + default: + MI->x86opsize = 2; + break; + case X86_INS_LJMP: + case X86_INS_LCALL: + MI->x86opsize = 4; + break; + case X86_INS_SGDT: + case X86_INS_SIDT: + case X86_INS_LGDT: + case X86_INS_LIDT: + MI->x86opsize = 6; + break; + } + break; + case CS_MODE_32: + switch(MI->flat_insn->id) { + default: + MI->x86opsize = 4; + break; + case X86_INS_LJMP: + case X86_INS_JMP: + case X86_INS_LCALL: + case X86_INS_SGDT: + case X86_INS_SIDT: + case X86_INS_LGDT: + case X86_INS_LIDT: + MI->x86opsize = 6; + break; + } + break; + case CS_MODE_64: + switch(MI->flat_insn->id) { + default: + MI->x86opsize = 8; + break; + case X86_INS_LJMP: + case X86_INS_LCALL: + case X86_INS_SGDT: + case X86_INS_SIDT: + case X86_INS_LGDT: + case X86_INS_LIDT: + MI->x86opsize = 10; + break; + } + break; + default: // never reach + break; + } + + printMemReference(MI, OpNo, O); +} + +static void printi8mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 1; + printMemReference(MI, OpNo, O); +} + +static void printi16mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 2; + + printMemReference(MI, OpNo, O); +} + +static void printi32mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 4; + + printMemReference(MI, OpNo, O); +} + +static void printi64mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 8; + printMemReference(MI, OpNo, O); +} + +static void printi128mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 16; + printMemReference(MI, OpNo, O); +} + +static void printi512mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 64; + printMemReference(MI, OpNo, O); +} + +#ifndef CAPSTONE_X86_REDUCE +static void printi256mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 32; + printMemReference(MI, OpNo, O); +} + +static void printf32mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + switch(MCInst_getOpcode(MI)) { + default: + MI->x86opsize = 4; + break; + case X86_FSTENVm: + case X86_FLDENVm: + // TODO: fix this in tablegen instead + switch(MI->csh->mode) { + default: // never reach + break; + case CS_MODE_16: + MI->x86opsize = 14; + break; + case CS_MODE_32: + case CS_MODE_64: + MI->x86opsize = 28; + break; + } + break; + } + + printMemReference(MI, OpNo, O); +} + +static void printf64mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 8; + printMemReference(MI, OpNo, O); +} + +static void printf80mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 10; + printMemReference(MI, OpNo, O); +} + +static void printf128mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 16; + printMemReference(MI, OpNo, O); +} + +static void printf256mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 32; + printMemReference(MI, OpNo, O); +} + +static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 64; + printMemReference(MI, OpNo, O); +} + +#endif + +static void printRegName(SStream *OS, unsigned RegNo); + +// local printOperand, without updating public operands +static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + if (MCOperand_isReg(Op)) { + printRegName(O, MCOperand_getReg(Op)); + } else if (MCOperand_isImm(Op)) { + uint8_t encsize; + uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize); + + // Print X86 immediates as signed values. + int64_t imm = MCOperand_getImm(Op); + if (imm < 0) { + if (MI->csh->imm_unsigned) { + if (opsize) { + switch(opsize) { + default: + break; + case 1: + imm &= 0xff; + break; + case 2: + imm &= 0xffff; + break; + case 4: + imm &= 0xffffffff; + break; + } + } + + SStream_concat(O, "$0x%"PRIx64, imm); + } else { + if (imm < -HEX_THRESHOLD) + SStream_concat(O, "$-0x%"PRIx64, -imm); + else + SStream_concat(O, "$-%"PRIu64, -imm); + } + } else { + if (imm > HEX_THRESHOLD) + SStream_concat(O, "$0x%"PRIx64, imm); + else + SStream_concat(O, "$%"PRIu64, imm); + } + } +} + +// convert Intel access info to AT&T access info +static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags) +{ + uint8_t count, i; + const uint8_t *arr = X86_get_op_access(h, id, eflags); + + // initialize access + memset(access, 0, CS_X86_MAXIMUM_OPERAND_SIZE * sizeof(access[0])); + if (!arr) { + return; + } + + // find the non-zero last entry + for(count = 0; arr[count]; count++); + + if (count == 0) + return; + + // copy in reverse order this access array from Intel syntax -> AT&T syntax + count--; + for(i = 0; i <= count && ((count - i) < CS_X86_MAXIMUM_OPERAND_SIZE) && i < CS_X86_MAXIMUM_OPERAND_SIZE; i++) { + if (arr[count - i] != CS_AC_IGNORE) + access[i] = arr[count - i]; + else + access[i] = 0; + } +} + +static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O) +{ + MCOperand *SegReg; + int reg; + + if (MI->csh->detail_opt) { + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; + + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; + } + + SegReg = MCInst_getOperand(MI, Op+1); + reg = MCOperand_getReg(SegReg); + // If this has a segment register, print it. + if (reg) { + _printOperand(MI, Op + 1, O); + SStream_concat0(O, ":"); + + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); + } + } + + SStream_concat0(O, "("); + set_mem_access(MI, true); + + printOperand(MI, Op, O); + + SStream_concat0(O, ")"); + set_mem_access(MI, false); +} + +static void printDstIdx(MCInst *MI, unsigned Op, SStream *O) +{ + if (MI->csh->detail_opt) { + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; + + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; + } + + // DI accesses are always ES-based on non-64bit mode + if (MI->csh->mode != CS_MODE_64) { + SStream_concat0(O, "%es:("); + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES; + } + } else + SStream_concat0(O, "("); + + set_mem_access(MI, true); + + printOperand(MI, Op, O); + + SStream_concat0(O, ")"); + set_mem_access(MI, false); +} + +static void printSrcIdx8(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 1; + printSrcIdx(MI, OpNo, O); +} + +static void printSrcIdx16(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 2; + printSrcIdx(MI, OpNo, O); +} + +static void printSrcIdx32(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 4; + printSrcIdx(MI, OpNo, O); +} + +static void printSrcIdx64(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 8; + printSrcIdx(MI, OpNo, O); +} + +static void printDstIdx8(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 1; + printDstIdx(MI, OpNo, O); +} + +static void printDstIdx16(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 2; + printDstIdx(MI, OpNo, O); +} + +static void printDstIdx32(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 4; + printDstIdx(MI, OpNo, O); +} + +static void printDstIdx64(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 8; + printDstIdx(MI, OpNo, O); +} + +static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) +{ + MCOperand *DispSpec = MCInst_getOperand(MI, Op); + MCOperand *SegReg = MCInst_getOperand(MI, Op+1); + int reg; + + if (MI->csh->detail_opt) { + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; + + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; + } + + // If this has a segment register, print it. + reg = MCOperand_getReg(SegReg); + if (reg) { + _printOperand(MI, Op + 1, O); + SStream_concat0(O, ":"); + + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); + } + } + + if (MCOperand_isImm(DispSpec)) { + int64_t imm = MCOperand_getImm(DispSpec); + if (MI->csh->detail_opt) + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; + if (imm < 0) { + SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm); + } else { + if (imm > HEX_THRESHOLD) + SStream_concat(O, "0x%"PRIx64, imm); + else + SStream_concat(O, "%"PRIu64, imm); + } + } + + if (MI->csh->detail_opt) + MI->flat_insn->detail->x86.op_count++; +} + +static void printU8Imm(MCInst *MI, unsigned Op, SStream *O) +{ + uint8_t val = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0xff; + + if (val > HEX_THRESHOLD) + SStream_concat(O, "$0x%x", val); + else + SStream_concat(O, "$%u", val); + + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = val; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = 1; + MI->flat_insn->detail->x86.op_count++; + } +} + +static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 1; + printMemOffset(MI, OpNo, O); +} + +static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 2; + printMemOffset(MI, OpNo, O); +} + +static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 4; + printMemOffset(MI, OpNo, O); +} + +static void printMemOffs64(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 8; + printMemOffset(MI, OpNo, O); +} + +/// printPCRelImm - This is used to print an immediate value that ends up +/// being encoded as a pc-relative value (e.g. for jumps and calls). These +/// print slightly differently than normal immediates. For example, a $ is not +/// emitted. +static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + if (MCOperand_isImm(Op)) { + int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; + + // truncate imm for non-64bit + if (MI->csh->mode != CS_MODE_64) { + imm = imm & 0xffffffff; + } + + if (imm < 0) { + SStream_concat(O, "0x%"PRIx64, imm); + } else { + if (imm > HEX_THRESHOLD) + SStream_concat(O, "0x%"PRIx64, imm); + else + SStream_concat(O, "%"PRIu64, imm); + } + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; + MI->has_imm = true; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; + MI->flat_insn->detail->x86.op_count++; + } + } +} + +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + if (MCOperand_isReg(Op)) { + unsigned int reg = MCOperand_getReg(Op); + printRegName(O, reg); + if (MI->csh->detail_opt) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(reg); + } else { + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = X86_register_map(reg); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[X86_register_map(reg)]; + + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; + + MI->flat_insn->detail->x86.op_count++; + } + } + } else if (MCOperand_isImm(Op)) { + // Print X86 immediates as signed values. + uint8_t encsize; + int64_t imm = MCOperand_getImm(Op); + uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize); + + if (opsize == 1) // print 1 byte immediate in positive form + imm = imm & 0xff; + + switch(MI->flat_insn->id) { + default: + if (imm >= 0) { + if (imm > HEX_THRESHOLD) + SStream_concat(O, "$0x%"PRIx64, imm); + else + SStream_concat(O, "$%"PRIu64, imm); + } else { + if (MI->csh->imm_unsigned) { + if (opsize) { + switch(opsize) { + default: + break; + case 1: + imm &= 0xff; + break; + case 2: + imm &= 0xffff; + break; + case 4: + imm &= 0xffffffff; + break; + } + } + + SStream_concat(O, "$0x%"PRIx64, imm); + } else { + if (imm == 0x8000000000000000LL) // imm == -imm + SStream_concat0(O, "$0x8000000000000000"); + else if (imm < -HEX_THRESHOLD) + SStream_concat(O, "$-0x%"PRIx64, -imm); + else + SStream_concat(O, "$-%"PRIu64, -imm); + } + } + break; + + case X86_INS_MOVABS: + case X86_INS_MOV: + // do not print number in negative form + if (imm > HEX_THRESHOLD) + SStream_concat(O, "$0x%"PRIx64, imm); + else + SStream_concat(O, "$%"PRIu64, imm); + break; + + case X86_INS_IN: + case X86_INS_OUT: + case X86_INS_INT: + // do not print number in negative form + imm = imm & 0xff; + if (imm >= 0 && imm <= HEX_THRESHOLD) + SStream_concat(O, "$%u", imm); + else { + SStream_concat(O, "$0x%x", imm); + } + break; + + case X86_INS_LCALL: + case X86_INS_LJMP: + case X86_INS_JMP: + // always print address in positive form + if (OpNo == 1) { // selector is ptr16 + imm = imm & 0xffff; + opsize = 2; + } else + opsize = 4; + SStream_concat(O, "$0x%"PRIx64, imm); + break; + + case X86_INS_AND: + case X86_INS_OR: + case X86_INS_XOR: + // do not print number in negative form + if (imm >= 0 && imm <= HEX_THRESHOLD) + SStream_concat(O, "$%u", imm); + else { + imm = arch_masks[opsize? opsize : MI->imm_size] & imm; + SStream_concat(O, "$0x%"PRIx64, imm); + } + break; + + case X86_INS_RET: + case X86_INS_RETF: + // RET imm16 + if (imm >= 0 && imm <= HEX_THRESHOLD) + SStream_concat(O, "$%u", imm); + else { + imm = 0xffff & imm; + SStream_concat(O, "$0x%x", imm); + } + break; + } + + if (MI->csh->detail_opt) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; + } else { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; + MI->has_imm = true; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; + + if (opsize > 0) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize; + MI->flat_insn->detail->x86.encoding.imm_size = encsize; + } else if (MI->op1_size > 0) + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->op1_size; + else + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; + + MI->flat_insn->detail->x86.op_count++; + } + } + } +} + +static void printMemReference(MCInst *MI, unsigned Op, SStream *O) +{ + MCOperand *BaseReg = MCInst_getOperand(MI, Op + X86_AddrBaseReg); + MCOperand *IndexReg = MCInst_getOperand(MI, Op + X86_AddrIndexReg); + MCOperand *DispSpec = MCInst_getOperand(MI, Op + X86_AddrDisp); + MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg); + uint64_t ScaleVal; + int segreg; + int64_t DispVal = 1; + + if (MI->csh->detail_opt) { + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(MCOperand_getReg(BaseReg)); + if (MCOperand_getReg(IndexReg) != X86_EIZ) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_register_map(MCOperand_getReg(IndexReg)); + } + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; + + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; + } + + // If this has a segment register, print it. + segreg = MCOperand_getReg(SegReg); + if (segreg) { + _printOperand(MI, Op + X86_AddrSegmentReg, O); + SStream_concat0(O, ":"); + + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(segreg); + } + } + + if (MCOperand_isImm(DispSpec)) { + DispVal = MCOperand_getImm(DispSpec); + if (MI->csh->detail_opt) + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal; + if (DispVal) { + if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { + printInt64(O, DispVal); + } else { + // only immediate as address of memory + if (DispVal < 0) { + SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); + } else { + if (DispVal > HEX_THRESHOLD) + SStream_concat(O, "0x%"PRIx64, DispVal); + else + SStream_concat(O, "%"PRIu64, DispVal); + } + } + } + } + + if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { + SStream_concat0(O, "("); + + if (MCOperand_getReg(BaseReg)) + _printOperand(MI, Op + X86_AddrBaseReg, O); + + if (MCOperand_getReg(IndexReg) && MCOperand_getReg(IndexReg) != X86_EIZ) { + SStream_concat0(O, ", "); + _printOperand(MI, Op + X86_AddrIndexReg, O); + ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op + X86_AddrScaleAmt)); + if (MI->csh->detail_opt) + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal; + if (ScaleVal != 1) { + SStream_concat(O, ", %u", ScaleVal); + } + } + + SStream_concat0(O, ")"); + } else { + if (!DispVal) + SStream_concat0(O, "0"); + } + + if (MI->csh->detail_opt) + MI->flat_insn->detail->x86.op_count++; +} + +static void printanymem(MCInst *MI, unsigned OpNo, SStream *O) +{ + switch(MI->Opcode) { + default: break; + case X86_LEA16r: + MI->x86opsize = 2; + break; + case X86_LEA32r: + case X86_LEA64_32r: + MI->x86opsize = 4; + break; + case X86_LEA64r: + MI->x86opsize = 8; + break; +#ifndef CAPSTONE_X86_REDUCE + case X86_BNDCL32rm: + case X86_BNDCN32rm: + case X86_BNDCU32rm: + case X86_BNDSTXmr: + case X86_BNDLDXrm: + case X86_BNDCL64rm: + case X86_BNDCN64rm: + case X86_BNDCU64rm: + MI->x86opsize = 16; + break; +#endif + } + + printMemReference(MI, OpNo, O); +} + +#include "X86InstPrinter.h" + +// Include the auto-generated portion of the assembly writer. +#ifdef CAPSTONE_X86_REDUCE +#include "X86GenAsmWriter_reduce.inc" +#else +#include "X86GenAsmWriter.inc" +#endif + +#include "X86GenRegisterName.inc" + +static void printRegName(SStream *OS, unsigned RegNo) +{ + SStream_concat(OS, "%%%s", getRegisterName(RegNo)); +} + +void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info) +{ + x86_reg reg, reg2; + enum cs_ac_type access1, access2; + int i; + + // perhaps this instruction does not need printer + if (MI->assembly[0]) { + strncpy(OS->buffer, MI->assembly, sizeof(OS->buffer)); + return; + } + + // Output CALLpcrel32 as "callq" in 64-bit mode. + // In Intel annotation it's always emitted as "call". + // + // TODO: Probably this hack should be redesigned via InstAlias in + // InstrInfo.td as soon as Requires clause is supported properly + // for InstAlias. + if (MI->csh->mode == CS_MODE_64 && MCInst_getOpcode(MI) == X86_CALLpcrel32) { + SStream_concat0(OS, "callq\t"); + MCInst_setOpcodePub(MI, X86_INS_CALL); + printPCRelImm(MI, 0, OS); + return; + } + + X86_lockrep(MI, OS); + printInstruction(MI, OS); + + if (MI->has_imm) { + // if op_count > 1, then this operand's size is taken from the destination op + if (MI->flat_insn->detail->x86.op_count > 1) { + if (MI->flat_insn->id != X86_INS_LCALL && MI->flat_insn->id != X86_INS_LJMP && MI->flat_insn->id != X86_INS_JMP) { + for (i = 0; i < MI->flat_insn->detail->x86.op_count; i++) { + if (MI->flat_insn->detail->x86.operands[i].type == X86_OP_IMM) + MI->flat_insn->detail->x86.operands[i].size = + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].size; + } + } + } else + MI->flat_insn->detail->x86.operands[0].size = MI->imm_size; + } + + if (MI->csh->detail_opt) { + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE] = {0}; + + // some instructions need to supply immediate 1 in the first op + switch(MCInst_getOpcode(MI)) { + default: + break; + case X86_SHL8r1: + case X86_SHL16r1: + case X86_SHL32r1: + case X86_SHL64r1: + case X86_SAL8r1: + case X86_SAL16r1: + case X86_SAL32r1: + case X86_SAL64r1: + case X86_SHR8r1: + case X86_SHR16r1: + case X86_SHR32r1: + case X86_SHR64r1: + case X86_SAR8r1: + case X86_SAR16r1: + case X86_SAR32r1: + case X86_SAR64r1: + case X86_RCL8r1: + case X86_RCL16r1: + case X86_RCL32r1: + case X86_RCL64r1: + case X86_RCR8r1: + case X86_RCR16r1: + case X86_RCR32r1: + case X86_RCR64r1: + case X86_ROL8r1: + case X86_ROL16r1: + case X86_ROL32r1: + case X86_ROL64r1: + case X86_ROR8r1: + case X86_ROR16r1: + case X86_ROR32r1: + case X86_ROR64r1: + case X86_SHL8m1: + case X86_SHL16m1: + case X86_SHL32m1: + case X86_SHL64m1: + case X86_SAL8m1: + case X86_SAL16m1: + case X86_SAL32m1: + case X86_SAL64m1: + case X86_SHR8m1: + case X86_SHR16m1: + case X86_SHR32m1: + case X86_SHR64m1: + case X86_SAR8m1: + case X86_SAR16m1: + case X86_SAR32m1: + case X86_SAR64m1: + case X86_RCL8m1: + case X86_RCL16m1: + case X86_RCL32m1: + case X86_RCL64m1: + case X86_RCR8m1: + case X86_RCR16m1: + case X86_RCR32m1: + case X86_RCR64m1: + case X86_ROL8m1: + case X86_ROL16m1: + case X86_ROL32m1: + case X86_ROL64m1: + case X86_ROR8m1: + case X86_ROR16m1: + case X86_ROR32m1: + case X86_ROR64m1: + // shift all the ops right to leave 1st slot for this new register op + memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), + sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); + MI->flat_insn->detail->x86.operands[0].type = X86_OP_IMM; + MI->flat_insn->detail->x86.operands[0].imm = 1; + MI->flat_insn->detail->x86.operands[0].size = 1; + MI->flat_insn->detail->x86.op_count++; + } + + // special instruction needs to supply register op + // first op can be embedded in the asm by llvm. + // so we have to add the missing register as the first operand + + //printf(">>> opcode = %u\n", MCInst_getOpcode(MI)); + + reg = X86_insn_reg_att(MCInst_getOpcode(MI), &access1); + if (reg) { + // shift all the ops right to leave 1st slot for this new register op + memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), + sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); + MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; + MI->flat_insn->detail->x86.operands[0].reg = reg; + MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; + MI->flat_insn->detail->x86.operands[0].access = access1; + + MI->flat_insn->detail->x86.op_count++; + } else { + if (X86_insn_reg_att2(MCInst_getOpcode(MI), ®, &access1, ®2, &access2)) { + + MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; + MI->flat_insn->detail->x86.operands[0].reg = reg; + MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; + MI->flat_insn->detail->x86.operands[0].access = access1; + MI->flat_insn->detail->x86.operands[1].type = X86_OP_REG; + MI->flat_insn->detail->x86.operands[1].reg = reg2; + MI->flat_insn->detail->x86.operands[1].size = MI->csh->regsize_map[reg2]; + MI->flat_insn->detail->x86.operands[1].access = access2; + MI->flat_insn->detail->x86.op_count = 2; + } + } + +#ifndef CAPSTONE_DIET + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[0].access = access[0]; + MI->flat_insn->detail->x86.operands[1].access = access[1]; +#endif + } +} + +#endif diff --git a/thirdparty/capstone/arch/X86/X86BaseInfo.h b/thirdparty/capstone/arch/X86/X86BaseInfo.h new file mode 100644 index 0000000..88314c7 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86BaseInfo.h @@ -0,0 +1,50 @@ +//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains small standalone helper functions and enum definitions for +// the X86 target useful for the compiler back-end and the MC libraries. +// As such, it deliberately does not include references to LLVM core +// code gen types, passes, etc.. +// +//===----------------------------------------------------------------------===// + +#ifndef CS_X86_BASEINFO_H +#define CS_X86_BASEINFO_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +// Enums for memory operand decoding. Each memory operand is represented with +// a 5 operand sequence in the form: +// [BaseReg, ScaleAmt, IndexReg, Disp, Segment] +// These enums help decode this. +enum { + X86_AddrBaseReg = 0, + X86_AddrScaleAmt = 1, + X86_AddrIndexReg = 2, + X86_AddrDisp = 3, + + /// AddrSegmentReg - The operand # of the segment in the memory operand. + X86_AddrSegmentReg = 4, + + /// AddrNumOperands - Total number of operands in a memory reference. + X86_AddrNumOperands = 5 +}; + +enum IPREFIXES { + X86_IP_NO_PREFIX = 0, + X86_IP_HAS_OP_SIZE = 1, + X86_IP_HAS_AD_SIZE = 2, + X86_IP_HAS_REPEAT_NE = 4, + X86_IP_HAS_REPEAT = 8, + X86_IP_HAS_LOCK = 16, + X86_IP_HAS_NOTRACK = 64 +}; + +#endif diff --git a/thirdparty/capstone/arch/X86/X86Disassembler.c b/thirdparty/capstone/arch/X86/X86Disassembler.c new file mode 100644 index 0000000..79a756f --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86Disassembler.c @@ -0,0 +1,1033 @@ +//===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file is part of the X86 Disassembler. +// It contains code to translate the data produced by the decoder into +// MCInsts. +// +// The X86 disassembler is a table-driven disassembler for the 16-, 32-, and +// 64-bit X86 instruction sets. The main decode sequence for an assembly +// instruction in this disassembler is: +// +// 1. Read the prefix bytes and determine the attributes of the instruction. +// These attributes, recorded in enum attributeBits +// (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM +// provides a mapping from bitmasks to contexts, which are represented by +// enum InstructionContext (ibid.). +// +// 2. Read the opcode, and determine what kind of opcode it is. The +// disassembler distinguishes four kinds of opcodes, which are enumerated in +// OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte +// (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a +// (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context. +// +// 3. Depending on the opcode type, look in one of four ClassDecision structures +// (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which +// OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get +// a ModRMDecision (ibid.). +// +// 4. Some instructions, such as escape opcodes or extended opcodes, or even +// instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the +// ModR/M byte to complete decode. The ModRMDecision's type is an entry from +// ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the +// ModR/M byte is required and how to interpret it. +// +// 5. After resolving the ModRMDecision, the disassembler has a unique ID +// of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in +// INSTRUCTIONS_SYM yields the name of the instruction and the encodings and +// meanings of its operands. +// +// 6. For each operand, its encoding is an entry from OperandEncoding +// (X86DisassemblerDecoderCommon.h) and its type is an entry from +// OperandType (ibid.). The encoding indicates how to read it from the +// instruction; the type indicates how to interpret the value once it has +// been read. For example, a register operand could be stored in the R/M +// field of the ModR/M byte, the REG field of the ModR/M byte, or added to +// the main opcode. This is orthogonal from its meaning (an GPR or an XMM +// register, for instance). Given this information, the operands can be +// extracted and interpreted. +// +// 7. As the last step, the disassembler translates the instruction information +// and operands into a format understandable by the client - in this case, an +// MCInst for use by the MC infrastructure. +// +// The disassembler is broken broadly into two parts: the table emitter that +// emits the instruction decode tables discussed above during compilation, and +// the disassembler itself. The table emitter is documented in more detail in +// utils/TableGen/X86DisassemblerEmitter.h. +// +// X86Disassembler.cpp contains the code responsible for step 7, and for +// invoking the decoder to execute steps 1-6. +// X86DisassemblerDecoderCommon.h contains the definitions needed by both the +// table emitter and the disassembler. +// X86DisassemblerDecoder.h contains the public interface of the decoder, +// factored out into C for possible use by other projects. +// X86DisassemblerDecoder.c contains the source code of the decoder, which is +// responsible for steps 1-6. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +#ifdef CAPSTONE_HAS_X86 + +#ifdef _MSC_VER +#pragma warning(disable:4996) // disable MSVC's warning on strncpy() +#pragma warning(disable:28719) // disable MSVC's warning on strncpy() +#endif + +#include + +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#endif + +#include + +#include "../../cs_priv.h" + +#include "X86BaseInfo.h" +#include "X86Disassembler.h" +#include "X86DisassemblerDecoderCommon.h" +#include "X86DisassemblerDecoder.h" +#include "../../MCInst.h" +#include "../../utils.h" +#include "X86Mapping.h" + +#define GET_REGINFO_ENUM +#define GET_REGINFO_MC_DESC +#include "X86GenRegisterInfo.inc" + +#define GET_INSTRINFO_ENUM +#ifdef CAPSTONE_X86_REDUCE +#include "X86GenInstrInfo_reduce.inc" +#else +#include "X86GenInstrInfo.inc" +#endif + +// Fill-ins to make the compiler happy. These constants are never actually +// assigned; they are just filler to make an automatically-generated switch +// statement work. +enum { + X86_BX_SI = 500, + X86_BX_DI = 501, + X86_BP_SI = 502, + X86_BP_DI = 503, + X86_sib = 504, + X86_sib64 = 505 +}; + +// +// Private code that translates from struct InternalInstructions to MCInsts. +// + +/// translateRegister - Translates an internal register to the appropriate LLVM +/// register, and appends it as an operand to an MCInst. +/// +/// @param mcInst - The MCInst to append to. +/// @param reg - The Reg to append. +static void translateRegister(MCInst *mcInst, Reg reg) +{ +#define ENTRY(x) X86_##x, + static const uint16_t llvmRegnums[] = { + ALL_REGS + 0 + }; +#undef ENTRY + + uint16_t llvmRegnum = llvmRegnums[reg]; + MCOperand_CreateReg0(mcInst, llvmRegnum); +} + +static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { + 0, // SEG_OVERRIDE_NONE + X86_CS, + X86_SS, + X86_DS, + X86_ES, + X86_FS, + X86_GS +}; + +/// translateSrcIndex - Appends a source index operand to an MCInst. +/// +/// @param mcInst - The MCInst to append to. +/// @param insn - The internal instruction. +static bool translateSrcIndex(MCInst *mcInst, InternalInstruction *insn) +{ + unsigned baseRegNo; + + if (insn->mode == MODE_64BIT) + baseRegNo = insn->hasAdSize ? X86_ESI : X86_RSI; + else if (insn->mode == MODE_32BIT) + baseRegNo = insn->hasAdSize ? X86_SI : X86_ESI; + else { + // assert(insn->mode == MODE_16BIT); + baseRegNo = insn->hasAdSize ? X86_ESI : X86_SI; + } + + MCOperand_CreateReg0(mcInst, baseRegNo); + + MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); + + return false; +} + +/// translateDstIndex - Appends a destination index operand to an MCInst. +/// +/// @param mcInst - The MCInst to append to. +/// @param insn - The internal instruction. +static bool translateDstIndex(MCInst *mcInst, InternalInstruction *insn) +{ + unsigned baseRegNo; + + if (insn->mode == MODE_64BIT) + baseRegNo = insn->hasAdSize ? X86_EDI : X86_RDI; + else if (insn->mode == MODE_32BIT) + baseRegNo = insn->hasAdSize ? X86_DI : X86_EDI; + else { + // assert(insn->mode == MODE_16BIT); + baseRegNo = insn->hasAdSize ? X86_EDI : X86_DI; + } + + MCOperand_CreateReg0(mcInst, baseRegNo); + + return false; +} + +/// translateImmediate - Appends an immediate operand to an MCInst. +/// +/// @param mcInst - The MCInst to append to. +/// @param immediate - The immediate value to append. +/// @param operand - The operand, as stored in the descriptor table. +/// @param insn - The internal instruction. +static void translateImmediate(MCInst *mcInst, uint64_t immediate, + const OperandSpecifier *operand, InternalInstruction *insn) +{ + OperandType type; + + type = (OperandType)operand->type; + if (type == TYPE_REL) { + //isBranch = true; + //pcrel = insn->startLocation + insn->immediateOffset + insn->immediateSize; + switch (operand->encoding) { + default: + break; + case ENCODING_Iv: + switch (insn->displacementSize) { + default: + break; + case 1: + if(immediate & 0x80) + immediate |= ~(0xffull); + break; + case 2: + if(immediate & 0x8000) + immediate |= ~(0xffffull); + break; + case 4: + if(immediate & 0x80000000) + immediate |= ~(0xffffffffull); + break; + case 8: + break; + } + break; + case ENCODING_IB: + if (immediate & 0x80) + immediate |= ~(0xffull); + break; + case ENCODING_IW: + if (immediate & 0x8000) + immediate |= ~(0xffffull); + break; + case ENCODING_ID: + if (immediate & 0x80000000) + immediate |= ~(0xffffffffull); + break; + } + } // By default sign-extend all X86 immediates based on their encoding. + else if (type == TYPE_IMM) { + switch (operand->encoding) { + default: + break; + case ENCODING_IB: + if(immediate & 0x80) + immediate |= ~(0xffull); + break; + case ENCODING_IW: + if(immediate & 0x8000) + immediate |= ~(0xffffull); + break; + case ENCODING_ID: + if(immediate & 0x80000000) + immediate |= ~(0xffffffffull); + break; + case ENCODING_IO: + break; + } + } else if (type == TYPE_IMM3) { +#ifndef CAPSTONE_X86_REDUCE + // Check for immediates that printSSECC can't handle. + if (immediate >= 8) { + unsigned NewOpc = 0; + + switch (MCInst_getOpcode(mcInst)) { + default: break; // never reach + case X86_CMPPDrmi: NewOpc = X86_CMPPDrmi_alt; break; + case X86_CMPPDrri: NewOpc = X86_CMPPDrri_alt; break; + case X86_CMPPSrmi: NewOpc = X86_CMPPSrmi_alt; break; + case X86_CMPPSrri: NewOpc = X86_CMPPSrri_alt; break; + case X86_CMPSDrm: NewOpc = X86_CMPSDrm_alt; break; + case X86_CMPSDrr: NewOpc = X86_CMPSDrr_alt; break; + case X86_CMPSSrm: NewOpc = X86_CMPSSrm_alt; break; + case X86_CMPSSrr: NewOpc = X86_CMPSSrr_alt; break; + case X86_VPCOMBri: NewOpc = X86_VPCOMBri_alt; break; + case X86_VPCOMBmi: NewOpc = X86_VPCOMBmi_alt; break; + case X86_VPCOMWri: NewOpc = X86_VPCOMWri_alt; break; + case X86_VPCOMWmi: NewOpc = X86_VPCOMWmi_alt; break; + case X86_VPCOMDri: NewOpc = X86_VPCOMDri_alt; break; + case X86_VPCOMDmi: NewOpc = X86_VPCOMDmi_alt; break; + case X86_VPCOMQri: NewOpc = X86_VPCOMQri_alt; break; + case X86_VPCOMQmi: NewOpc = X86_VPCOMQmi_alt; break; + case X86_VPCOMUBri: NewOpc = X86_VPCOMUBri_alt; break; + case X86_VPCOMUBmi: NewOpc = X86_VPCOMUBmi_alt; break; + case X86_VPCOMUWri: NewOpc = X86_VPCOMUWri_alt; break; + case X86_VPCOMUWmi: NewOpc = X86_VPCOMUWmi_alt; break; + case X86_VPCOMUDri: NewOpc = X86_VPCOMUDri_alt; break; + case X86_VPCOMUDmi: NewOpc = X86_VPCOMUDmi_alt; break; + case X86_VPCOMUQri: NewOpc = X86_VPCOMUQri_alt; break; + case X86_VPCOMUQmi: NewOpc = X86_VPCOMUQmi_alt; break; + } + + // Switch opcode to the one that doesn't get special printing. + if (NewOpc != 0) { + MCInst_setOpcode(mcInst, NewOpc); + } + } +#endif + } else if (type == TYPE_IMM5) { +#ifndef CAPSTONE_X86_REDUCE + // Check for immediates that printAVXCC can't handle. + if (immediate >= 32) { + unsigned NewOpc = 0; + + switch (MCInst_getOpcode(mcInst)) { + default: break; // unexpected opcode + case X86_VCMPPDrmi: NewOpc = X86_VCMPPDrmi_alt; break; + case X86_VCMPPDrri: NewOpc = X86_VCMPPDrri_alt; break; + case X86_VCMPPSrmi: NewOpc = X86_VCMPPSrmi_alt; break; + case X86_VCMPPSrri: NewOpc = X86_VCMPPSrri_alt; break; + case X86_VCMPSDrm: NewOpc = X86_VCMPSDrm_alt; break; + case X86_VCMPSDrr: NewOpc = X86_VCMPSDrr_alt; break; + case X86_VCMPSSrm: NewOpc = X86_VCMPSSrm_alt; break; + case X86_VCMPSSrr: NewOpc = X86_VCMPSSrr_alt; break; + case X86_VCMPPDYrmi: NewOpc = X86_VCMPPDYrmi_alt; break; + case X86_VCMPPDYrri: NewOpc = X86_VCMPPDYrri_alt; break; + case X86_VCMPPSYrmi: NewOpc = X86_VCMPPSYrmi_alt; break; + case X86_VCMPPSYrri: NewOpc = X86_VCMPPSYrri_alt; break; + case X86_VCMPPDZrmi: NewOpc = X86_VCMPPDZrmi_alt; break; + case X86_VCMPPDZrri: NewOpc = X86_VCMPPDZrri_alt; break; + case X86_VCMPPDZrrib: NewOpc = X86_VCMPPDZrrib_alt; break; + case X86_VCMPPSZrmi: NewOpc = X86_VCMPPSZrmi_alt; break; + case X86_VCMPPSZrri: NewOpc = X86_VCMPPSZrri_alt; break; + case X86_VCMPPSZrrib: NewOpc = X86_VCMPPSZrrib_alt; break; + case X86_VCMPPDZ128rmi: NewOpc = X86_VCMPPDZ128rmi_alt; break; + case X86_VCMPPDZ128rri: NewOpc = X86_VCMPPDZ128rri_alt; break; + case X86_VCMPPSZ128rmi: NewOpc = X86_VCMPPSZ128rmi_alt; break; + case X86_VCMPPSZ128rri: NewOpc = X86_VCMPPSZ128rri_alt; break; + case X86_VCMPPDZ256rmi: NewOpc = X86_VCMPPDZ256rmi_alt; break; + case X86_VCMPPDZ256rri: NewOpc = X86_VCMPPDZ256rri_alt; break; + case X86_VCMPPSZ256rmi: NewOpc = X86_VCMPPSZ256rmi_alt; break; + case X86_VCMPPSZ256rri: NewOpc = X86_VCMPPSZ256rri_alt; break; + case X86_VCMPSDZrm_Int: NewOpc = X86_VCMPSDZrmi_alt; break; + case X86_VCMPSDZrr_Int: NewOpc = X86_VCMPSDZrri_alt; break; + case X86_VCMPSDZrrb_Int: NewOpc = X86_VCMPSDZrrb_alt; break; + case X86_VCMPSSZrm_Int: NewOpc = X86_VCMPSSZrmi_alt; break; + case X86_VCMPSSZrr_Int: NewOpc = X86_VCMPSSZrri_alt; break; + case X86_VCMPSSZrrb_Int: NewOpc = X86_VCMPSSZrrb_alt; break; + } + + // Switch opcode to the one that doesn't get special printing. + if (NewOpc != 0) { + MCInst_setOpcode(mcInst, NewOpc); + } + } +#endif + } else if (type == TYPE_AVX512ICC) { +#ifndef CAPSTONE_X86_REDUCE + if (immediate >= 8 || ((immediate & 0x3) == 3)) { + unsigned NewOpc = 0; + switch (MCInst_getOpcode(mcInst)) { + default: // llvm_unreachable("unexpected opcode"); + case X86_VPCMPBZ128rmi: NewOpc = X86_VPCMPBZ128rmi_alt; break; + case X86_VPCMPBZ128rmik: NewOpc = X86_VPCMPBZ128rmik_alt; break; + case X86_VPCMPBZ128rri: NewOpc = X86_VPCMPBZ128rri_alt; break; + case X86_VPCMPBZ128rrik: NewOpc = X86_VPCMPBZ128rrik_alt; break; + case X86_VPCMPBZ256rmi: NewOpc = X86_VPCMPBZ256rmi_alt; break; + case X86_VPCMPBZ256rmik: NewOpc = X86_VPCMPBZ256rmik_alt; break; + case X86_VPCMPBZ256rri: NewOpc = X86_VPCMPBZ256rri_alt; break; + case X86_VPCMPBZ256rrik: NewOpc = X86_VPCMPBZ256rrik_alt; break; + case X86_VPCMPBZrmi: NewOpc = X86_VPCMPBZrmi_alt; break; + case X86_VPCMPBZrmik: NewOpc = X86_VPCMPBZrmik_alt; break; + case X86_VPCMPBZrri: NewOpc = X86_VPCMPBZrri_alt; break; + case X86_VPCMPBZrrik: NewOpc = X86_VPCMPBZrrik_alt; break; + case X86_VPCMPDZ128rmi: NewOpc = X86_VPCMPDZ128rmi_alt; break; + case X86_VPCMPDZ128rmib: NewOpc = X86_VPCMPDZ128rmib_alt; break; + case X86_VPCMPDZ128rmibk: NewOpc = X86_VPCMPDZ128rmibk_alt; break; + case X86_VPCMPDZ128rmik: NewOpc = X86_VPCMPDZ128rmik_alt; break; + case X86_VPCMPDZ128rri: NewOpc = X86_VPCMPDZ128rri_alt; break; + case X86_VPCMPDZ128rrik: NewOpc = X86_VPCMPDZ128rrik_alt; break; + case X86_VPCMPDZ256rmi: NewOpc = X86_VPCMPDZ256rmi_alt; break; + case X86_VPCMPDZ256rmib: NewOpc = X86_VPCMPDZ256rmib_alt; break; + case X86_VPCMPDZ256rmibk: NewOpc = X86_VPCMPDZ256rmibk_alt; break; + case X86_VPCMPDZ256rmik: NewOpc = X86_VPCMPDZ256rmik_alt; break; + case X86_VPCMPDZ256rri: NewOpc = X86_VPCMPDZ256rri_alt; break; + case X86_VPCMPDZ256rrik: NewOpc = X86_VPCMPDZ256rrik_alt; break; + case X86_VPCMPDZrmi: NewOpc = X86_VPCMPDZrmi_alt; break; + case X86_VPCMPDZrmib: NewOpc = X86_VPCMPDZrmib_alt; break; + case X86_VPCMPDZrmibk: NewOpc = X86_VPCMPDZrmibk_alt; break; + case X86_VPCMPDZrmik: NewOpc = X86_VPCMPDZrmik_alt; break; + case X86_VPCMPDZrri: NewOpc = X86_VPCMPDZrri_alt; break; + case X86_VPCMPDZrrik: NewOpc = X86_VPCMPDZrrik_alt; break; + case X86_VPCMPQZ128rmi: NewOpc = X86_VPCMPQZ128rmi_alt; break; + case X86_VPCMPQZ128rmib: NewOpc = X86_VPCMPQZ128rmib_alt; break; + case X86_VPCMPQZ128rmibk: NewOpc = X86_VPCMPQZ128rmibk_alt; break; + case X86_VPCMPQZ128rmik: NewOpc = X86_VPCMPQZ128rmik_alt; break; + case X86_VPCMPQZ128rri: NewOpc = X86_VPCMPQZ128rri_alt; break; + case X86_VPCMPQZ128rrik: NewOpc = X86_VPCMPQZ128rrik_alt; break; + case X86_VPCMPQZ256rmi: NewOpc = X86_VPCMPQZ256rmi_alt; break; + case X86_VPCMPQZ256rmib: NewOpc = X86_VPCMPQZ256rmib_alt; break; + case X86_VPCMPQZ256rmibk: NewOpc = X86_VPCMPQZ256rmibk_alt; break; + case X86_VPCMPQZ256rmik: NewOpc = X86_VPCMPQZ256rmik_alt; break; + case X86_VPCMPQZ256rri: NewOpc = X86_VPCMPQZ256rri_alt; break; + case X86_VPCMPQZ256rrik: NewOpc = X86_VPCMPQZ256rrik_alt; break; + case X86_VPCMPQZrmi: NewOpc = X86_VPCMPQZrmi_alt; break; + case X86_VPCMPQZrmib: NewOpc = X86_VPCMPQZrmib_alt; break; + case X86_VPCMPQZrmibk: NewOpc = X86_VPCMPQZrmibk_alt; break; + case X86_VPCMPQZrmik: NewOpc = X86_VPCMPQZrmik_alt; break; + case X86_VPCMPQZrri: NewOpc = X86_VPCMPQZrri_alt; break; + case X86_VPCMPQZrrik: NewOpc = X86_VPCMPQZrrik_alt; break; + case X86_VPCMPUBZ128rmi: NewOpc = X86_VPCMPUBZ128rmi_alt; break; + case X86_VPCMPUBZ128rmik: NewOpc = X86_VPCMPUBZ128rmik_alt; break; + case X86_VPCMPUBZ128rri: NewOpc = X86_VPCMPUBZ128rri_alt; break; + case X86_VPCMPUBZ128rrik: NewOpc = X86_VPCMPUBZ128rrik_alt; break; + case X86_VPCMPUBZ256rmi: NewOpc = X86_VPCMPUBZ256rmi_alt; break; + case X86_VPCMPUBZ256rmik: NewOpc = X86_VPCMPUBZ256rmik_alt; break; + case X86_VPCMPUBZ256rri: NewOpc = X86_VPCMPUBZ256rri_alt; break; + case X86_VPCMPUBZ256rrik: NewOpc = X86_VPCMPUBZ256rrik_alt; break; + case X86_VPCMPUBZrmi: NewOpc = X86_VPCMPUBZrmi_alt; break; + case X86_VPCMPUBZrmik: NewOpc = X86_VPCMPUBZrmik_alt; break; + case X86_VPCMPUBZrri: NewOpc = X86_VPCMPUBZrri_alt; break; + case X86_VPCMPUBZrrik: NewOpc = X86_VPCMPUBZrrik_alt; break; + case X86_VPCMPUDZ128rmi: NewOpc = X86_VPCMPUDZ128rmi_alt; break; + case X86_VPCMPUDZ128rmib: NewOpc = X86_VPCMPUDZ128rmib_alt; break; + case X86_VPCMPUDZ128rmibk: NewOpc = X86_VPCMPUDZ128rmibk_alt; break; + case X86_VPCMPUDZ128rmik: NewOpc = X86_VPCMPUDZ128rmik_alt; break; + case X86_VPCMPUDZ128rri: NewOpc = X86_VPCMPUDZ128rri_alt; break; + case X86_VPCMPUDZ128rrik: NewOpc = X86_VPCMPUDZ128rrik_alt; break; + case X86_VPCMPUDZ256rmi: NewOpc = X86_VPCMPUDZ256rmi_alt; break; + case X86_VPCMPUDZ256rmib: NewOpc = X86_VPCMPUDZ256rmib_alt; break; + case X86_VPCMPUDZ256rmibk: NewOpc = X86_VPCMPUDZ256rmibk_alt; break; + case X86_VPCMPUDZ256rmik: NewOpc = X86_VPCMPUDZ256rmik_alt; break; + case X86_VPCMPUDZ256rri: NewOpc = X86_VPCMPUDZ256rri_alt; break; + case X86_VPCMPUDZ256rrik: NewOpc = X86_VPCMPUDZ256rrik_alt; break; + case X86_VPCMPUDZrmi: NewOpc = X86_VPCMPUDZrmi_alt; break; + case X86_VPCMPUDZrmib: NewOpc = X86_VPCMPUDZrmib_alt; break; + case X86_VPCMPUDZrmibk: NewOpc = X86_VPCMPUDZrmibk_alt; break; + case X86_VPCMPUDZrmik: NewOpc = X86_VPCMPUDZrmik_alt; break; + case X86_VPCMPUDZrri: NewOpc = X86_VPCMPUDZrri_alt; break; + case X86_VPCMPUDZrrik: NewOpc = X86_VPCMPUDZrrik_alt; break; + case X86_VPCMPUQZ128rmi: NewOpc = X86_VPCMPUQZ128rmi_alt; break; + case X86_VPCMPUQZ128rmib: NewOpc = X86_VPCMPUQZ128rmib_alt; break; + case X86_VPCMPUQZ128rmibk: NewOpc = X86_VPCMPUQZ128rmibk_alt; break; + case X86_VPCMPUQZ128rmik: NewOpc = X86_VPCMPUQZ128rmik_alt; break; + case X86_VPCMPUQZ128rri: NewOpc = X86_VPCMPUQZ128rri_alt; break; + case X86_VPCMPUQZ128rrik: NewOpc = X86_VPCMPUQZ128rrik_alt; break; + case X86_VPCMPUQZ256rmi: NewOpc = X86_VPCMPUQZ256rmi_alt; break; + case X86_VPCMPUQZ256rmib: NewOpc = X86_VPCMPUQZ256rmib_alt; break; + case X86_VPCMPUQZ256rmibk: NewOpc = X86_VPCMPUQZ256rmibk_alt; break; + case X86_VPCMPUQZ256rmik: NewOpc = X86_VPCMPUQZ256rmik_alt; break; + case X86_VPCMPUQZ256rri: NewOpc = X86_VPCMPUQZ256rri_alt; break; + case X86_VPCMPUQZ256rrik: NewOpc = X86_VPCMPUQZ256rrik_alt; break; + case X86_VPCMPUQZrmi: NewOpc = X86_VPCMPUQZrmi_alt; break; + case X86_VPCMPUQZrmib: NewOpc = X86_VPCMPUQZrmib_alt; break; + case X86_VPCMPUQZrmibk: NewOpc = X86_VPCMPUQZrmibk_alt; break; + case X86_VPCMPUQZrmik: NewOpc = X86_VPCMPUQZrmik_alt; break; + case X86_VPCMPUQZrri: NewOpc = X86_VPCMPUQZrri_alt; break; + case X86_VPCMPUQZrrik: NewOpc = X86_VPCMPUQZrrik_alt; break; + case X86_VPCMPUWZ128rmi: NewOpc = X86_VPCMPUWZ128rmi_alt; break; + case X86_VPCMPUWZ128rmik: NewOpc = X86_VPCMPUWZ128rmik_alt; break; + case X86_VPCMPUWZ128rri: NewOpc = X86_VPCMPUWZ128rri_alt; break; + case X86_VPCMPUWZ128rrik: NewOpc = X86_VPCMPUWZ128rrik_alt; break; + case X86_VPCMPUWZ256rmi: NewOpc = X86_VPCMPUWZ256rmi_alt; break; + case X86_VPCMPUWZ256rmik: NewOpc = X86_VPCMPUWZ256rmik_alt; break; + case X86_VPCMPUWZ256rri: NewOpc = X86_VPCMPUWZ256rri_alt; break; + case X86_VPCMPUWZ256rrik: NewOpc = X86_VPCMPUWZ256rrik_alt; break; + case X86_VPCMPUWZrmi: NewOpc = X86_VPCMPUWZrmi_alt; break; + case X86_VPCMPUWZrmik: NewOpc = X86_VPCMPUWZrmik_alt; break; + case X86_VPCMPUWZrri: NewOpc = X86_VPCMPUWZrri_alt; break; + case X86_VPCMPUWZrrik: NewOpc = X86_VPCMPUWZrrik_alt; break; + case X86_VPCMPWZ128rmi: NewOpc = X86_VPCMPWZ128rmi_alt; break; + case X86_VPCMPWZ128rmik: NewOpc = X86_VPCMPWZ128rmik_alt; break; + case X86_VPCMPWZ128rri: NewOpc = X86_VPCMPWZ128rri_alt; break; + case X86_VPCMPWZ128rrik: NewOpc = X86_VPCMPWZ128rrik_alt; break; + case X86_VPCMPWZ256rmi: NewOpc = X86_VPCMPWZ256rmi_alt; break; + case X86_VPCMPWZ256rmik: NewOpc = X86_VPCMPWZ256rmik_alt; break; + case X86_VPCMPWZ256rri: NewOpc = X86_VPCMPWZ256rri_alt; break; + case X86_VPCMPWZ256rrik: NewOpc = X86_VPCMPWZ256rrik_alt; break; + case X86_VPCMPWZrmi: NewOpc = X86_VPCMPWZrmi_alt; break; + case X86_VPCMPWZrmik: NewOpc = X86_VPCMPWZrmik_alt; break; + case X86_VPCMPWZrri: NewOpc = X86_VPCMPWZrri_alt; break; + case X86_VPCMPWZrrik: NewOpc = X86_VPCMPWZrrik_alt; break; + } + + // Switch opcode to the one that doesn't get special printing. + if (NewOpc != 0) { + MCInst_setOpcode(mcInst, NewOpc); + } + } +#endif + } + + switch (type) { + case TYPE_XMM: + MCOperand_CreateReg0(mcInst, X86_XMM0 + ((uint32_t)immediate >> 4)); + return; + case TYPE_YMM: + MCOperand_CreateReg0(mcInst, X86_YMM0 + ((uint32_t)immediate >> 4)); + return; + case TYPE_ZMM: + MCOperand_CreateReg0(mcInst, X86_ZMM0 + ((uint32_t)immediate >> 4)); + return; + default: + // operand is 64 bits wide. Do nothing. + break; + } + + MCOperand_CreateImm0(mcInst, immediate); + + if (type == TYPE_MOFFS) { + MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); + } +} + +/// translateRMRegister - Translates a register stored in the R/M field of the +/// ModR/M byte to its LLVM equivalent and appends it to an MCInst. +/// @param mcInst - The MCInst to append to. +/// @param insn - The internal instruction to extract the R/M field +/// from. +/// @return - 0 on success; -1 otherwise +static bool translateRMRegister(MCInst *mcInst, InternalInstruction *insn) +{ + if (insn->eaBase == EA_BASE_sib || insn->eaBase == EA_BASE_sib64) { + //debug("A R/M register operand may not have a SIB byte"); + return true; + } + + switch (insn->eaBase) { + case EA_BASE_NONE: + //debug("EA_BASE_NONE for ModR/M base"); + return true; +#define ENTRY(x) case EA_BASE_##x: + ALL_EA_BASES +#undef ENTRY + //debug("A R/M register operand may not have a base; " + // "the operand must be a register."); + return true; +#define ENTRY(x) \ + case EA_REG_##x: \ + MCOperand_CreateReg0(mcInst, X86_##x); break; + ALL_REGS +#undef ENTRY + default: + //debug("Unexpected EA base register"); + return true; + } + + return false; +} + +/// translateRMMemory - Translates a memory operand stored in the Mod and R/M +/// fields of an internal instruction (and possibly its SIB byte) to a memory +/// operand in LLVM's format, and appends it to an MCInst. +/// +/// @param mcInst - The MCInst to append to. +/// @param insn - The instruction to extract Mod, R/M, and SIB fields +/// from. +/// @return - 0 on success; nonzero otherwise +static bool translateRMMemory(MCInst *mcInst, InternalInstruction *insn) +{ + // Addresses in an MCInst are represented as five operands: + // 1. basereg (register) The R/M base, or (if there is a SIB) the + // SIB base + // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified + // scale amount + // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) + // the index (which is multiplied by the + // scale amount) + // 4. displacement (immediate) 0, or the displacement if there is one + // 5. segmentreg (register) x86_registerNONE for now, but could be set + // if we have segment overrides + int scaleAmount, indexReg; + + if (insn->eaBase == EA_BASE_sib || insn->eaBase == EA_BASE_sib64) { + if (insn->sibBase != SIB_BASE_NONE) { + switch (insn->sibBase) { +#define ENTRY(x) \ + case SIB_BASE_##x: \ + MCOperand_CreateReg0(mcInst, X86_##x); break; + ALL_SIB_BASES +#undef ENTRY + default: + //debug("Unexpected sibBase"); + return true; + } + } else { + MCOperand_CreateReg0(mcInst, 0); + } + + if (insn->sibIndex != SIB_INDEX_NONE) { + switch (insn->sibIndex) { + default: + //debug("Unexpected sibIndex"); + return true; +#define ENTRY(x) \ + case SIB_INDEX_##x: \ + indexReg = X86_##x; break; + EA_BASES_32BIT + EA_BASES_64BIT + REGS_XMM + REGS_YMM + REGS_ZMM +#undef ENTRY + } + } else { + // Use EIZ/RIZ for a few ambiguous cases where the SIB byte is present, + // but no index is used and modrm alone should have been enough. + // -No base register in 32-bit mode. In 64-bit mode this is used to + // avoid rip-relative addressing. + // -Any base register used other than ESP/RSP/R12D/R12. Using these as a + // base always requires a SIB byte. + // -A scale other than 1 is used. + if (insn->sibScale != 1 || + (insn->sibBase == SIB_BASE_NONE && insn->mode != MODE_64BIT) || + (insn->sibBase != SIB_BASE_NONE && + insn->sibBase != SIB_BASE_ESP && insn->sibBase != SIB_BASE_RSP && + insn->sibBase != SIB_BASE_R12D && insn->sibBase != SIB_BASE_R12)) { + indexReg = insn->addressSize == 4? X86_EIZ : X86_RIZ; + } else + indexReg = 0; + } + + scaleAmount = insn->sibScale; + } else { + switch (insn->eaBase) { + case EA_BASE_NONE: + if (insn->eaDisplacement == EA_DISP_NONE) { + //debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); + return true; + } + if (insn->mode == MODE_64BIT) { + if (insn->prefix3 == 0x67) // address-size prefix overrides RIP relative addressing + MCOperand_CreateReg0(mcInst, X86_EIP); + else + // Section 2.2.1.6 + MCOperand_CreateReg0(mcInst, insn->addressSize == 4 ? X86_EIP : X86_RIP); + } else { + MCOperand_CreateReg0(mcInst, 0); + } + + indexReg = 0; + break; + case EA_BASE_BX_SI: + MCOperand_CreateReg0(mcInst, X86_BX); + indexReg = X86_SI; + break; + case EA_BASE_BX_DI: + MCOperand_CreateReg0(mcInst, X86_BX); + indexReg = X86_DI; + break; + case EA_BASE_BP_SI: + MCOperand_CreateReg0(mcInst, X86_BP); + indexReg = X86_SI; + break; + case EA_BASE_BP_DI: + MCOperand_CreateReg0(mcInst, X86_BP); + indexReg = X86_DI; + break; + default: + indexReg = 0; + switch (insn->eaBase) { + default: + //debug("Unexpected eaBase"); + return true; + // Here, we will use the fill-ins defined above. However, + // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and + // sib and sib64 were handled in the top-level if, so they're only + // placeholders to keep the compiler happy. +#define ENTRY(x) \ + case EA_BASE_##x: \ + MCOperand_CreateReg0(mcInst, X86_##x); break; + ALL_EA_BASES +#undef ENTRY +#define ENTRY(x) case EA_REG_##x: + ALL_REGS +#undef ENTRY + //debug("A R/M memory operand may not be a register; " + // "the base field must be a base."); + return true; + } + } + + scaleAmount = 1; + } + + MCOperand_CreateImm0(mcInst, scaleAmount); + MCOperand_CreateReg0(mcInst, indexReg); + MCOperand_CreateImm0(mcInst, insn->displacement); + + MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); + + return false; +} + +/// translateRM - Translates an operand stored in the R/M (and possibly SIB) +/// byte of an instruction to LLVM form, and appends it to an MCInst. +/// +/// @param mcInst - The MCInst to append to. +/// @param operand - The operand, as stored in the descriptor table. +/// @param insn - The instruction to extract Mod, R/M, and SIB fields +/// from. +/// @return - 0 on success; nonzero otherwise +static bool translateRM(MCInst *mcInst, const OperandSpecifier *operand, + InternalInstruction *insn) +{ + switch (operand->type) { + default: + //debug("Unexpected type for a R/M operand"); + return true; + case TYPE_R8: + case TYPE_R16: + case TYPE_R32: + case TYPE_R64: + case TYPE_Rv: + case TYPE_MM64: + case TYPE_XMM: + case TYPE_YMM: + case TYPE_ZMM: + case TYPE_VK: + case TYPE_DEBUGREG: + case TYPE_CONTROLREG: + case TYPE_BNDR: + return translateRMRegister(mcInst, insn); + case TYPE_M: + case TYPE_MVSIBX: + case TYPE_MVSIBY: + case TYPE_MVSIBZ: + return translateRMMemory(mcInst, insn); + } +} + +/// translateFPRegister - Translates a stack position on the FPU stack to its +/// LLVM form, and appends it to an MCInst. +/// +/// @param mcInst - The MCInst to append to. +/// @param stackPos - The stack position to translate. +static void translateFPRegister(MCInst *mcInst, uint8_t stackPos) +{ + MCOperand_CreateReg0(mcInst, X86_ST0 + stackPos); +} + +/// translateMaskRegister - Translates a 3-bit mask register number to +/// LLVM form, and appends it to an MCInst. +/// +/// @param mcInst - The MCInst to append to. +/// @param maskRegNum - Number of mask register from 0 to 7. +/// @return - false on success; true otherwise. +static bool translateMaskRegister(MCInst *mcInst, uint8_t maskRegNum) +{ + if (maskRegNum >= 8) { + // debug("Invalid mask register number"); + return true; + } + + MCOperand_CreateReg0(mcInst, X86_K0 + maskRegNum); + + return false; +} + +/// translateOperand - Translates an operand stored in an internal instruction +/// to LLVM's format and appends it to an MCInst. +/// +/// @param mcInst - The MCInst to append to. +/// @param operand - The operand, as stored in the descriptor table. +/// @param insn - The internal instruction. +/// @return - false on success; true otherwise. +static bool translateOperand(MCInst *mcInst, const OperandSpecifier *operand, InternalInstruction *insn) +{ + switch (operand->encoding) { + case ENCODING_REG: + translateRegister(mcInst, insn->reg); + return false; + case ENCODING_WRITEMASK: + return translateMaskRegister(mcInst, insn->writemask); + CASE_ENCODING_RM: + CASE_ENCODING_VSIB: + return translateRM(mcInst, operand, insn); + case ENCODING_IB: + case ENCODING_IW: + case ENCODING_ID: + case ENCODING_IO: + case ENCODING_Iv: + case ENCODING_Ia: + translateImmediate(mcInst, insn->immediates[insn->numImmediatesTranslated++], operand, insn); + return false; + case ENCODING_IRC: + MCOperand_CreateImm0(mcInst, insn->RC); + return false; + case ENCODING_SI: + return translateSrcIndex(mcInst, insn); + case ENCODING_DI: + return translateDstIndex(mcInst, insn); + case ENCODING_RB: + case ENCODING_RW: + case ENCODING_RD: + case ENCODING_RO: + case ENCODING_Rv: + translateRegister(mcInst, insn->opcodeRegister); + return false; + case ENCODING_FP: + translateFPRegister(mcInst, insn->modRM & 7); + return false; + case ENCODING_VVVV: + translateRegister(mcInst, insn->vvvv); + return false; + case ENCODING_DUP: + return translateOperand(mcInst, &insn->operands[operand->type - TYPE_DUP0], insn); + default: + //debug("Unhandled operand encoding during translation"); + return true; + } +} + +static bool translateInstruction(MCInst *mcInst, InternalInstruction *insn) +{ + int index; + + if (!insn->spec) { + //debug("Instruction has no specification"); + return true; + } + + MCInst_clear(mcInst); + MCInst_setOpcode(mcInst, insn->instructionID); + + // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3 + // prefix bytes should be disassembled as xrelease and xacquire then set the + // opcode to those instead of the rep and repne opcodes. +#ifndef CAPSTONE_X86_REDUCE + if (insn->xAcquireRelease) { + if (MCInst_getOpcode(mcInst) == X86_REP_PREFIX) + MCInst_setOpcode(mcInst, X86_XRELEASE_PREFIX); + else if (MCInst_getOpcode(mcInst) == X86_REPNE_PREFIX) + MCInst_setOpcode(mcInst, X86_XACQUIRE_PREFIX); + } +#endif + + insn->numImmediatesTranslated = 0; + + for (index = 0; index < X86_MAX_OPERANDS; ++index) { + if (insn->operands[index].encoding != ENCODING_NONE) { + if (translateOperand(mcInst, &insn->operands[index], insn)) { + return true; + } + } + } + + return false; +} + +static int reader(const struct reader_info *info, uint8_t *byte, uint64_t address) +{ + if (address - info->offset >= info->size) + // out of buffer range + return -1; + + *byte = info->code[address - info->offset]; + + return 0; +} + +// copy x86 detail information from internal structure to public structure +static void update_pub_insn(cs_insn *pub, InternalInstruction *inter) +{ + if (inter->vectorExtensionType != 0) { + memcpy(pub->detail->x86.opcode, inter->vectorExtensionPrefix, sizeof(pub->detail->x86.opcode)); + } else { + if (inter->twoByteEscape) { + if (inter->threeByteEscape) { + pub->detail->x86.opcode[0] = inter->twoByteEscape; + pub->detail->x86.opcode[1] = inter->threeByteEscape; + pub->detail->x86.opcode[2] = inter->opcode; + } else { + pub->detail->x86.opcode[0] = inter->twoByteEscape; + pub->detail->x86.opcode[1] = inter->opcode; + } + } else { + pub->detail->x86.opcode[0] = inter->opcode; + } + } + + pub->detail->x86.rex = inter->rexPrefix; + + pub->detail->x86.addr_size = inter->addressSize; + + pub->detail->x86.modrm = inter->orgModRM; + pub->detail->x86.encoding.modrm_offset = inter->modRMOffset; + + pub->detail->x86.sib = inter->sib; + pub->detail->x86.sib_index = x86_map_sib_index(inter->sibIndex); + pub->detail->x86.sib_scale = inter->sibScale; + pub->detail->x86.sib_base = x86_map_sib_base(inter->sibBase); + + pub->detail->x86.disp = inter->displacement; + if (inter->consumedDisplacement) { + pub->detail->x86.encoding.disp_offset = inter->displacementOffset; + pub->detail->x86.encoding.disp_size = inter->displacementSize; + } + + pub->detail->x86.encoding.imm_offset = inter->immediateOffset; + if (pub->detail->x86.encoding.imm_size == 0 && inter->immediateOffset != 0) + pub->detail->x86.encoding.imm_size = inter->immediateSize; +} + +void X86_init(MCRegisterInfo *MRI) +{ + // InitMCRegisterInfo(), X86GenRegisterInfo.inc + // RI->InitMCRegisterInfo(X86RegDesc, 277, + // RA, PC, + // X86MCRegisterClasses, 86, + // X86RegUnitRoots, 162, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, + // X86RegClassStrings, + // X86SubRegIdxLists, 9, + // X86SubRegIdxRanges, X86RegEncodingTable); + /* + InitMCRegisterInfo(X86RegDesc, 234, + RA, PC, + X86MCRegisterClasses, 79, + X86RegUnitRoots, 119, X86RegDiffLists, X86RegStrings, + X86SubRegIdxLists, 7, + X86SubRegIdxRanges, X86RegEncodingTable); + */ + + MCRegisterInfo_InitMCRegisterInfo(MRI, X86RegDesc, 277, + 0, 0, + X86MCRegisterClasses, 86, + 0, 0, X86RegDiffLists, 0, + X86SubRegIdxLists, 9, + 0); +} + +// Public interface for the disassembler +bool X86_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *_info) +{ + cs_struct *handle = (cs_struct *)(uintptr_t)ud; + InternalInstruction insn = { 0 }; + struct reader_info info; + int ret; + bool result; + + info.code = code; + info.size = code_len; + info.offset = address; + + if (instr->flat_insn->detail) { + // instr->flat_insn->detail initialization: 3 alternatives + + // 1. The whole structure, this is how it's done in other arch disassemblers + // Probably overkill since cs_detail is huge because of the 36 operands of ARM + + //memset(instr->flat_insn->detail, 0, sizeof(cs_detail)); + + // 2. Only the part relevant to x86 + memset(instr->flat_insn->detail, 0, offsetof(cs_detail, x86) + sizeof(cs_x86)); + + // 3. The relevant part except for x86.operands + // sizeof(cs_x86) is 0x1c0, sizeof(x86.operands) is 0x180 + // marginally faster, should be okay since x86.op_count is set to 0 + + //memset(instr->flat_insn->detail, 0, offsetof(cs_detail, x86)+offsetof(cs_x86, operands)); + } + + if (handle->mode & CS_MODE_16) + ret = decodeInstruction(&insn, + reader, &info, + address, + MODE_16BIT); + else if (handle->mode & CS_MODE_32) + ret = decodeInstruction(&insn, + reader, &info, + address, + MODE_32BIT); + else + ret = decodeInstruction(&insn, + reader, &info, + address, + MODE_64BIT); + + if (ret) { + // *size = (uint16_t)(insn.readerCursor - address); + return false; + } else { + *size = (uint16_t)insn.length; + + result = (!translateInstruction(instr, &insn)) ? true : false; + if (result) { + unsigned Flags = X86_IP_NO_PREFIX; + instr->imm_size = insn.immSize; + + // copy all prefixes + instr->x86_prefix[0] = insn.prefix0; + instr->x86_prefix[1] = insn.prefix1; + instr->x86_prefix[2] = insn.prefix2; + instr->x86_prefix[3] = insn.prefix3; + instr->xAcquireRelease = insn.xAcquireRelease; + + if (handle->detail_opt) { + update_pub_insn(instr->flat_insn, &insn); + } + + if (insn.hasAdSize) + Flags |= X86_IP_HAS_AD_SIZE; + + if (!insn.mandatoryPrefix) { + if (insn.hasOpSize) + Flags |= X86_IP_HAS_OP_SIZE; + + if (insn.repeatPrefix == 0xf2) + Flags |= X86_IP_HAS_REPEAT_NE; + else if (insn.repeatPrefix == 0xf3 && + // It should not be 'pause' f3 90 + insn.opcode != 0x90) + Flags |= X86_IP_HAS_REPEAT; + if (insn.hasLockPrefix) + Flags |= X86_IP_HAS_LOCK; + } + + instr->flags = Flags; + } + + return result; + } +} + +#endif diff --git a/thirdparty/capstone/arch/X86/X86Disassembler.h b/thirdparty/capstone/arch/X86/X86Disassembler.h new file mode 100644 index 0000000..80876bc --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86Disassembler.h @@ -0,0 +1,28 @@ +//===-- X86Disassembler.h - Disassembler for x86 and x86_64 -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +#ifndef CS_X86_DISASSEMBLER_H +#define CS_X86_DISASSEMBLER_H + +#include "capstone/capstone.h" + +#include "../../MCInst.h" + +#include "../../MCRegisterInfo.h" +#include "X86DisassemblerDecoderCommon.h" + +bool X86_getInstruction(csh handle, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info); + +void X86_init(MCRegisterInfo *MRI); + +#endif diff --git a/thirdparty/capstone/arch/X86/X86DisassemblerDecoder.c b/thirdparty/capstone/arch/X86/X86DisassemblerDecoder.c new file mode 100644 index 0000000..95ac06f --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86DisassemblerDecoder.c @@ -0,0 +1,2358 @@ +/*===-- X86DisassemblerDecoder.c - Disassembler decoder ------------*- C -*-===* + * + * The LLVM Compiler Infrastructure + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + * + *===----------------------------------------------------------------------===* + * + * This file is part of the X86 Disassembler. + * It contains the implementation of the instruction decoder. + * Documentation for the disassembler can be found in X86Disassembler.h. + * + *===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +#ifdef CAPSTONE_HAS_X86 + +#include /* for va_*() */ +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#else +#include /* for exit() */ +#endif + +#include + +#include "../../cs_priv.h" +#include "../../utils.h" + +#include "X86DisassemblerDecoder.h" +#include "X86Mapping.h" + +/// Specifies whether a ModR/M byte is needed and (if so) which +/// instruction each possible value of the ModR/M byte corresponds to. Once +/// this information is known, we have narrowed down to a single instruction. +struct ModRMDecision { + uint8_t modrm_type; + uint16_t instructionIDs; +}; + +/// Specifies which set of ModR/M->instruction tables to look at +/// given a particular opcode. +struct OpcodeDecision { + struct ModRMDecision modRMDecisions[256]; +}; + +/// Specifies which opcode->instruction tables to look at given +/// a particular context (set of attributes). Since there are many possible +/// contexts, the decoder first uses CONTEXTS_SYM to determine which context +/// applies given a specific set of attributes. Hence there are only IC_max +/// entries in this table, rather than 2^(ATTR_max). +struct ContextDecision { + struct OpcodeDecision opcodeDecisions[IC_max]; +}; + +#ifdef CAPSTONE_X86_REDUCE +#include "X86GenDisassemblerTables_reduce.inc" +#include "X86GenDisassemblerTables_reduce2.inc" +#include "X86Lookup16_reduce.inc" +#else +#include "X86GenDisassemblerTables.inc" +#include "X86GenDisassemblerTables2.inc" +#include "X86Lookup16.inc" +#endif + +/* + * contextForAttrs - Client for the instruction context table. Takes a set of + * attributes and returns the appropriate decode context. + * + * @param attrMask - Attributes, from the enumeration attributeBits. + * @return - The InstructionContext to use when looking up an + * an instruction with these attributes. + */ +static InstructionContext contextForAttrs(uint16_t attrMask) +{ + return CONTEXTS_SYM[attrMask]; +} + +/* + * modRMRequired - Reads the appropriate instruction table to determine whether + * the ModR/M byte is required to decode a particular instruction. + * + * @param type - The opcode type (i.e., how many bytes it has). + * @param insnContext - The context for the instruction, as returned by + * contextForAttrs. + * @param opcode - The last byte of the instruction's opcode, not counting + * ModR/M extensions and escapes. + * @return - true if the ModR/M byte is required, false otherwise. + */ +static int modRMRequired(OpcodeType type, + InstructionContext insnContext, + uint16_t opcode) +{ + const struct OpcodeDecision *decision = NULL; + const uint8_t *indextable = NULL; + unsigned int index; + + switch (type) { + default: break; + case ONEBYTE: + decision = ONEBYTE_SYM; + indextable = index_x86DisassemblerOneByteOpcodes; + break; + case TWOBYTE: + decision = TWOBYTE_SYM; + indextable = index_x86DisassemblerTwoByteOpcodes; + break; + case THREEBYTE_38: + decision = THREEBYTE38_SYM; + indextable = index_x86DisassemblerThreeByte38Opcodes; + break; + case THREEBYTE_3A: + decision = THREEBYTE3A_SYM; + indextable = index_x86DisassemblerThreeByte3AOpcodes; + break; +#ifndef CAPSTONE_X86_REDUCE + case XOP8_MAP: + decision = XOP8_MAP_SYM; + indextable = index_x86DisassemblerXOP8Opcodes; + break; + case XOP9_MAP: + decision = XOP9_MAP_SYM; + indextable = index_x86DisassemblerXOP9Opcodes; + break; + case XOPA_MAP: + decision = XOPA_MAP_SYM; + indextable = index_x86DisassemblerXOPAOpcodes; + break; + case THREEDNOW_MAP: + // 3DNow instructions always have ModRM byte + return true; +#endif + } + + // return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].modrm_type != MODRM_ONEENTRY; + index = indextable[insnContext]; + if (index) + return decision[index - 1].modRMDecisions[opcode].modrm_type != MODRM_ONEENTRY; + else + return false; +} + +/* + * decode - Reads the appropriate instruction table to obtain the unique ID of + * an instruction. + * + * @param type - See modRMRequired(). + * @param insnContext - See modRMRequired(). + * @param opcode - See modRMRequired(). + * @param modRM - The ModR/M byte if required, or any value if not. + * @return - The UID of the instruction, or 0 on failure. + */ +static InstrUID decode(OpcodeType type, + InstructionContext insnContext, + uint8_t opcode, + uint8_t modRM) +{ + const struct ModRMDecision *dec = NULL; + unsigned int index; + static const struct OpcodeDecision emptyDecision = { 0 }; + + switch (type) { + default: break; // never reach + case ONEBYTE: + // dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + index = index_x86DisassemblerOneByteOpcodes[insnContext]; + if (index) + dec = &ONEBYTE_SYM[index - 1].modRMDecisions[opcode]; + else + dec = &emptyDecision.modRMDecisions[opcode]; + break; + case TWOBYTE: + //dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + index = index_x86DisassemblerTwoByteOpcodes[insnContext]; + if (index) + dec = &TWOBYTE_SYM[index - 1].modRMDecisions[opcode]; + else + dec = &emptyDecision.modRMDecisions[opcode]; + break; + case THREEBYTE_38: + // dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + index = index_x86DisassemblerThreeByte38Opcodes[insnContext]; + if (index) + dec = &THREEBYTE38_SYM[index - 1].modRMDecisions[opcode]; + else + dec = &emptyDecision.modRMDecisions[opcode]; + break; + case THREEBYTE_3A: + //dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + index = index_x86DisassemblerThreeByte3AOpcodes[insnContext]; + if (index) + dec = &THREEBYTE3A_SYM[index - 1].modRMDecisions[opcode]; + else + dec = &emptyDecision.modRMDecisions[opcode]; + break; +#ifndef CAPSTONE_X86_REDUCE + case XOP8_MAP: + // dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + index = index_x86DisassemblerXOP8Opcodes[insnContext]; + if (index) + dec = &XOP8_MAP_SYM[index - 1].modRMDecisions[opcode]; + else + dec = &emptyDecision.modRMDecisions[opcode]; + break; + case XOP9_MAP: + // dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + index = index_x86DisassemblerXOP9Opcodes[insnContext]; + if (index) + dec = &XOP9_MAP_SYM[index - 1].modRMDecisions[opcode]; + else + dec = &emptyDecision.modRMDecisions[opcode]; + break; + case XOPA_MAP: + // dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + index = index_x86DisassemblerXOPAOpcodes[insnContext]; + if (index) + dec = &XOPA_MAP_SYM[index - 1].modRMDecisions[opcode]; + else + dec = &emptyDecision.modRMDecisions[opcode]; + break; + case THREEDNOW_MAP: + // dec = &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + index = index_x86Disassembler3DNowOpcodes[insnContext]; + if (index) + dec = &THREEDNOW_MAP_SYM[index - 1].modRMDecisions[opcode]; + else + dec = &emptyDecision.modRMDecisions[opcode]; + break; +#endif + } + + switch (dec->modrm_type) { + default: + // debug("Corrupt table! Unknown modrm_type"); + return 0; + case MODRM_ONEENTRY: + return modRMTable[dec->instructionIDs]; + case MODRM_SPLITRM: + if (modFromModRM(modRM) == 0x3) + return modRMTable[dec->instructionIDs + 1]; + return modRMTable[dec->instructionIDs]; + case MODRM_SPLITREG: + if (modFromModRM(modRM) == 0x3) + return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3) + 8]; + return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)]; + case MODRM_SPLITMISC: + if (modFromModRM(modRM) == 0x3) + return modRMTable[dec->instructionIDs+(modRM & 0x3f) + 8]; + return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)]; + case MODRM_FULL: + return modRMTable[dec->instructionIDs+modRM]; + } +} + +/* + * specifierForUID - Given a UID, returns the name and operand specification for + * that instruction. + * + * @param uid - The unique ID for the instruction. This should be returned by + * decode(); specifierForUID will not check bounds. + * @return - A pointer to the specification for that instruction. + */ +static const struct InstructionSpecifier *specifierForUID(InstrUID uid) +{ + return &INSTRUCTIONS_SYM[uid]; +} + +/* + * consumeByte - Uses the reader function provided by the user to consume one + * byte from the instruction's memory and advance the cursor. + * + * @param insn - The instruction with the reader function to use. The cursor + * for this instruction is advanced. + * @param byte - A pointer to a pre-allocated memory buffer to be populated + * with the data read. + * @return - 0 if the read was successful; nonzero otherwise. + */ +static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) +{ + int ret = insn->reader(insn->readerArg, byte, insn->readerCursor); + + if (!ret) + ++(insn->readerCursor); + + return ret; +} + +/* + * lookAtByte - Like consumeByte, but does not advance the cursor. + * + * @param insn - See consumeByte(). + * @param byte - See consumeByte(). + * @return - See consumeByte(). + */ +static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) +{ + return insn->reader(insn->readerArg, byte, insn->readerCursor); +} + +static void unconsumeByte(struct InternalInstruction* insn) +{ + insn->readerCursor--; +} + +#define CONSUME_FUNC(name, type) \ + static int name(struct InternalInstruction* insn, type* ptr) { \ + type combined = 0; \ + unsigned offset; \ + for (offset = 0; offset < sizeof(type); ++offset) { \ + uint8_t byte; \ + int ret = insn->reader(insn->readerArg, \ + &byte, \ + insn->readerCursor + offset); \ + if (ret) \ + return ret; \ + combined = combined | ((uint64_t)byte << (offset * 8)); \ + } \ + *ptr = combined; \ + insn->readerCursor += sizeof(type); \ + return 0; \ + } + +/* + * consume* - Use the reader function provided by the user to consume data + * values of various sizes from the instruction's memory and advance the + * cursor appropriately. These readers perform endian conversion. + * + * @param insn - See consumeByte(). + * @param ptr - A pointer to a pre-allocated memory of appropriate size to + * be populated with the data read. + * @return - See consumeByte(). + */ +CONSUME_FUNC(consumeInt8, int8_t) +CONSUME_FUNC(consumeInt16, int16_t) +CONSUME_FUNC(consumeInt32, int32_t) +CONSUME_FUNC(consumeUInt16, uint16_t) +CONSUME_FUNC(consumeUInt32, uint32_t) +CONSUME_FUNC(consumeUInt64, uint64_t) + +static bool isREX(struct InternalInstruction *insn, uint8_t prefix) +{ + if (insn->mode == MODE_64BIT) + return prefix >= 0x40 && prefix <= 0x4f; + + return false; +} + +/* + * setPrefixPresent - Marks that a particular prefix is present as mandatory + * + * @param insn - The instruction to be marked as having the prefix. + * @param prefix - The prefix that is present. + */ +static void setPrefixPresent(struct InternalInstruction *insn, uint8_t prefix) +{ + uint8_t nextByte; + + switch (prefix) { + case 0xf0: // LOCK + insn->hasLockPrefix = true; + insn->repeatPrefix = 0; + break; + + case 0xf2: // REPNE/REPNZ + case 0xf3: // REP or REPE/REPZ + if (lookAtByte(insn, &nextByte)) + break; + // TODO: + // 1. There could be several 0x66 + // 2. if (nextByte == 0x66) and nextNextByte != 0x0f then + // it's not mandatory prefix + // 3. if (nextByte >= 0x40 && nextByte <= 0x4f) it's REX and we need + // 0x0f exactly after it to be mandatory prefix + if (isREX(insn, nextByte) || nextByte == 0x0f || nextByte == 0x66) + // The last of 0xf2 /0xf3 is mandatory prefix + insn->mandatoryPrefix = prefix; + + insn->repeatPrefix = prefix; + insn->hasLockPrefix = false; + break; + + case 0x66: + if (lookAtByte(insn, &nextByte)) + break; + // 0x66 can't overwrite existing mandatory prefix and should be ignored + if (!insn->mandatoryPrefix && (nextByte == 0x0f || isREX(insn, nextByte))) + insn->mandatoryPrefix = prefix; + break; + } +} + +/* + * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the + * instruction as having them. Also sets the instruction's default operand, + * address, and other relevant data sizes to report operands correctly. + * + * @param insn - The instruction whose prefixes are to be read. + * @return - 0 if the instruction could be read until the end of the prefix + * bytes, and no prefixes conflicted; nonzero otherwise. + */ +static int readPrefixes(struct InternalInstruction* insn) +{ + bool isPrefix = true; + uint8_t byte = 0; + uint8_t nextByte; + + while (isPrefix) { + if (insn->mode == MODE_64BIT) { + // eliminate consecutive redundant REX bytes in front + if (consumeByte(insn, &byte)) + return -1; + + if ((byte & 0xf0) == 0x40) { + while(true) { + if (lookAtByte(insn, &byte)) // out of input code + return -1; + if ((byte & 0xf0) == 0x40) { + // another REX prefix, but we only remember the last one + if (consumeByte(insn, &byte)) + return -1; + } else + break; + } + + // recover the last REX byte if next byte is not a legacy prefix + switch (byte) { + case 0xf2: /* REPNE/REPNZ */ + case 0xf3: /* REP or REPE/REPZ */ + case 0xf0: /* LOCK */ + case 0x2e: /* CS segment override -OR- Branch not taken */ + case 0x36: /* SS segment override -OR- Branch taken */ + case 0x3e: /* DS segment override */ + case 0x26: /* ES segment override */ + case 0x64: /* FS segment override */ + case 0x65: /* GS segment override */ + case 0x66: /* Operand-size override */ + case 0x67: /* Address-size override */ + break; + default: /* Not a prefix byte */ + unconsumeByte(insn); + break; + } + } else { + unconsumeByte(insn); + } + } + + /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */ + if (consumeByte(insn, &byte)) + return -1; + + if (insn->readerCursor - 1 == insn->startLocation + && (byte == 0xf2 || byte == 0xf3)) { + // prefix requires next byte + if (lookAtByte(insn, &nextByte)) + return -1; + + /* + * If the byte is 0xf2 or 0xf3, and any of the following conditions are + * met: + * - it is followed by a LOCK (0xf0) prefix + * - it is followed by an xchg instruction + * then it should be disassembled as a xacquire/xrelease not repne/rep. + */ + if (((nextByte == 0xf0) || + ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90))) { + insn->xAcquireRelease = byte; + } + + /* + * Also if the byte is 0xf3, and the following condition is met: + * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or + * "mov mem, imm" (opcode 0xc6/0xc7) instructions. + * then it should be disassembled as an xrelease not rep. + */ + if (byte == 0xf3 && (nextByte == 0x88 || nextByte == 0x89 || + nextByte == 0xc6 || nextByte == 0xc7)) { + insn->xAcquireRelease = byte; + } + + if (isREX(insn, nextByte)) { + uint8_t nnextByte; + + // Go to REX prefix after the current one + if (consumeByte(insn, &nnextByte)) + return -1; + + // We should be able to read next byte after REX prefix + if (lookAtByte(insn, &nnextByte)) + return -1; + + unconsumeByte(insn); + } + } + + switch (byte) { + case 0xf0: /* LOCK */ + case 0xf2: /* REPNE/REPNZ */ + case 0xf3: /* REP or REPE/REPZ */ + // only accept the last prefix + setPrefixPresent(insn, byte); + insn->prefix0 = byte; + break; + + case 0x2e: /* CS segment override -OR- Branch not taken */ + case 0x36: /* SS segment override -OR- Branch taken */ + case 0x3e: /* DS segment override */ + case 0x26: /* ES segment override */ + case 0x64: /* FS segment override */ + case 0x65: /* GS segment override */ + switch (byte) { + case 0x2e: + insn->segmentOverride = SEG_OVERRIDE_CS; + insn->prefix1 = byte; + break; + case 0x36: + insn->segmentOverride = SEG_OVERRIDE_SS; + insn->prefix1 = byte; + break; + case 0x3e: + insn->segmentOverride = SEG_OVERRIDE_DS; + insn->prefix1 = byte; + break; + case 0x26: + insn->segmentOverride = SEG_OVERRIDE_ES; + insn->prefix1 = byte; + break; + case 0x64: + insn->segmentOverride = SEG_OVERRIDE_FS; + insn->prefix1 = byte; + break; + case 0x65: + insn->segmentOverride = SEG_OVERRIDE_GS; + insn->prefix1 = byte; + break; + default: + // debug("Unhandled override"); + return -1; + } + setPrefixPresent(insn, byte); + break; + + case 0x66: /* Operand-size override */ + insn->hasOpSize = true; + setPrefixPresent(insn, byte); + insn->prefix2 = byte; + break; + + case 0x67: /* Address-size override */ + insn->hasAdSize = true; + setPrefixPresent(insn, byte); + insn->prefix3 = byte; + break; + default: /* Not a prefix byte */ + isPrefix = false; + break; + } + } + + insn->vectorExtensionType = TYPE_NO_VEX_XOP; + + if (byte == 0x62) { + uint8_t byte1, byte2; + + if (consumeByte(insn, &byte1)) { + // dbgprintf(insn, "Couldn't read second byte of EVEX prefix"); + return -1; + } + + if (lookAtByte(insn, &byte2)) { + // dbgprintf(insn, "Couldn't read third byte of EVEX prefix"); + unconsumeByte(insn); /* unconsume byte1 */ + unconsumeByte(insn); /* unconsume byte */ + } else { + if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) && + ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) { + insn->vectorExtensionType = TYPE_EVEX; + } else { + unconsumeByte(insn); /* unconsume byte1 */ + unconsumeByte(insn); /* unconsume byte */ + } + } + + if (insn->vectorExtensionType == TYPE_EVEX) { + insn->vectorExtensionPrefix[0] = byte; + insn->vectorExtensionPrefix[1] = byte1; + if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) { + // dbgprintf(insn, "Couldn't read third byte of EVEX prefix"); + return -1; + } + + if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) { + // dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix"); + return -1; + } + + /* We simulate the REX prefix for simplicity's sake */ + if (insn->mode == MODE_64BIT) { + insn->rexPrefix = 0x40 + | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3) + | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2) + | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1) + | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0); + } + + // dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx", + // insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1], + // insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]); + } + } else if (byte == 0xc4) { + uint8_t byte1; + + if (lookAtByte(insn, &byte1)) { + // dbgprintf(insn, "Couldn't read second byte of VEX"); + return -1; + } + + if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) + insn->vectorExtensionType = TYPE_VEX_3B; + else + unconsumeByte(insn); + + if (insn->vectorExtensionType == TYPE_VEX_3B) { + insn->vectorExtensionPrefix[0] = byte; + consumeByte(insn, &insn->vectorExtensionPrefix[1]); + consumeByte(insn, &insn->vectorExtensionPrefix[2]); + + /* We simulate the REX prefix for simplicity's sake */ + if (insn->mode == MODE_64BIT) + insn->rexPrefix = 0x40 + | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3) + | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2) + | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1) + | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0); + + // dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx", + // insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1], + // insn->vectorExtensionPrefix[2]); + } + } else if (byte == 0xc5) { + uint8_t byte1; + + if (lookAtByte(insn, &byte1)) { + // dbgprintf(insn, "Couldn't read second byte of VEX"); + return -1; + } + + if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) + insn->vectorExtensionType = TYPE_VEX_2B; + else + unconsumeByte(insn); + + if (insn->vectorExtensionType == TYPE_VEX_2B) { + insn->vectorExtensionPrefix[0] = byte; + consumeByte(insn, &insn->vectorExtensionPrefix[1]); + + if (insn->mode == MODE_64BIT) + insn->rexPrefix = 0x40 + | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2); + + switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) { + default: + break; + case VEX_PREFIX_66: + insn->hasOpSize = true; + break; + } + + // dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx", + // insn->vectorExtensionPrefix[0], + // insn->vectorExtensionPrefix[1]); + } + } else if (byte == 0x8f) { + uint8_t byte1; + + if (lookAtByte(insn, &byte1)) { + // dbgprintf(insn, "Couldn't read second byte of XOP"); + return -1; + } + + if ((byte1 & 0x38) != 0x0) /* 0 in these 3 bits is a POP instruction. */ + insn->vectorExtensionType = TYPE_XOP; + else + unconsumeByte(insn); + + if (insn->vectorExtensionType == TYPE_XOP) { + insn->vectorExtensionPrefix[0] = byte; + consumeByte(insn, &insn->vectorExtensionPrefix[1]); + consumeByte(insn, &insn->vectorExtensionPrefix[2]); + + /* We simulate the REX prefix for simplicity's sake */ + if (insn->mode == MODE_64BIT) + insn->rexPrefix = 0x40 + | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3) + | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2) + | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1) + | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0); + + switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) { + default: + break; + case VEX_PREFIX_66: + insn->hasOpSize = true; + break; + } + + // dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx", + // insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1], + // insn->vectorExtensionPrefix[2]); + } + } else if (isREX(insn, byte)) { + if (lookAtByte(insn, &nextByte)) + return -1; + + insn->rexPrefix = byte; + // dbgprintf(insn, "Found REX prefix 0x%hhx", byte); + } else + unconsumeByte(insn); + + if (insn->mode == MODE_16BIT) { + insn->registerSize = (insn->hasOpSize ? 4 : 2); + insn->addressSize = (insn->hasAdSize ? 4 : 2); + insn->displacementSize = (insn->hasAdSize ? 4 : 2); + insn->immediateSize = (insn->hasOpSize ? 4 : 2); + insn->immSize = (insn->hasOpSize ? 4 : 2); + } else if (insn->mode == MODE_32BIT) { + insn->registerSize = (insn->hasOpSize ? 2 : 4); + insn->addressSize = (insn->hasAdSize ? 2 : 4); + insn->displacementSize = (insn->hasAdSize ? 2 : 4); + insn->immediateSize = (insn->hasOpSize ? 2 : 4); + insn->immSize = (insn->hasOpSize ? 2 : 4); + } else if (insn->mode == MODE_64BIT) { + if (insn->rexPrefix && wFromREX(insn->rexPrefix)) { + insn->registerSize = 8; + insn->addressSize = (insn->hasAdSize ? 4 : 8); + insn->displacementSize = 4; + insn->immediateSize = 4; + insn->immSize = 4; + } else { + insn->registerSize = (insn->hasOpSize ? 2 : 4); + insn->addressSize = (insn->hasAdSize ? 4 : 8); + insn->displacementSize = (insn->hasOpSize ? 2 : 4); + insn->immediateSize = (insn->hasOpSize ? 2 : 4); + insn->immSize = (insn->hasOpSize ? 4 : 8); + } + } + + return 0; +} + +static int readModRM(struct InternalInstruction* insn); + +/* + * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of + * extended or escape opcodes). + * + * @param insn - The instruction whose opcode is to be read. + * @return - 0 if the opcode could be read successfully; nonzero otherwise. + */ +static int readOpcode(struct InternalInstruction* insn) +{ + uint8_t current; + + // dbgprintf(insn, "readOpcode()"); + + insn->opcodeType = ONEBYTE; + + if (insn->vectorExtensionType == TYPE_EVEX) { + switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) { + default: + // dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)", + // mmFromEVEX2of4(insn->vectorExtensionPrefix[1])); + return -1; + case VEX_LOB_0F: + insn->opcodeType = TWOBYTE; + return consumeByte(insn, &insn->opcode); + case VEX_LOB_0F38: + insn->opcodeType = THREEBYTE_38; + return consumeByte(insn, &insn->opcode); + case VEX_LOB_0F3A: + insn->opcodeType = THREEBYTE_3A; + return consumeByte(insn, &insn->opcode); + } + } else if (insn->vectorExtensionType == TYPE_VEX_3B) { + switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) { + default: + // dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", + // mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])); + return -1; + case VEX_LOB_0F: + //insn->twoByteEscape = 0x0f; + insn->opcodeType = TWOBYTE; + return consumeByte(insn, &insn->opcode); + case VEX_LOB_0F38: + //insn->twoByteEscape = 0x0f; + insn->opcodeType = THREEBYTE_38; + return consumeByte(insn, &insn->opcode); + case VEX_LOB_0F3A: + //insn->twoByteEscape = 0x0f; + insn->opcodeType = THREEBYTE_3A; + return consumeByte(insn, &insn->opcode); + } + } else if (insn->vectorExtensionType == TYPE_VEX_2B) { + //insn->twoByteEscape = 0x0f; + insn->opcodeType = TWOBYTE; + return consumeByte(insn, &insn->opcode); + } else if (insn->vectorExtensionType == TYPE_XOP) { + switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) { + default: + // dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", + // mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])); + return -1; + case XOP_MAP_SELECT_8: + insn->opcodeType = XOP8_MAP; + return consumeByte(insn, &insn->opcode); + case XOP_MAP_SELECT_9: + insn->opcodeType = XOP9_MAP; + return consumeByte(insn, &insn->opcode); + case XOP_MAP_SELECT_A: + insn->opcodeType = XOPA_MAP; + return consumeByte(insn, &insn->opcode); + } + } + + if (consumeByte(insn, ¤t)) + return -1; + + // save this first byte for MOVcr, MOVdr, MOVrc, MOVrd + insn->firstByte = current; + + if (current == 0x0f) { + // dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current); + insn->twoByteEscape = current; + + if (consumeByte(insn, ¤t)) + return -1; + + if (current == 0x38) { + // dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); + if (consumeByte(insn, ¤t)) + return -1; + + insn->opcodeType = THREEBYTE_38; + } else if (current == 0x3a) { + // dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); + if (consumeByte(insn, ¤t)) + return -1; + + insn->opcodeType = THREEBYTE_3A; + } else if (current == 0x0f) { + // dbgprintf(insn, "Found a 3dnow escape prefix (0x%hhx)", current); + // Consume operands before the opcode to comply with the 3DNow encoding + if (readModRM(insn)) + return -1; + + if (consumeByte(insn, ¤t)) + return -1; + + insn->opcodeType = THREEDNOW_MAP; + } else { + // dbgprintf(insn, "Didn't find a three-byte escape prefix"); + insn->opcodeType = TWOBYTE; + } + } else if (insn->mandatoryPrefix) + // The opcode with mandatory prefix must start with opcode escape. + // If not it's legacy repeat prefix + insn->mandatoryPrefix = 0; + + /* + * At this point we have consumed the full opcode. + * Anything we consume from here on must be unconsumed. + */ + + insn->opcode = current; + + return 0; +} + +// Hacky for FEMMS +#define GET_INSTRINFO_ENUM +#ifndef CAPSTONE_X86_REDUCE +#include "X86GenInstrInfo.inc" +#else +#include "X86GenInstrInfo_reduce.inc" +#endif + +/* + * getIDWithAttrMask - Determines the ID of an instruction, consuming + * the ModR/M byte as appropriate for extended and escape opcodes, + * and using a supplied attribute mask. + * + * @param instructionID - A pointer whose target is filled in with the ID of the + * instruction. + * @param insn - The instruction whose ID is to be determined. + * @param attrMask - The attribute mask to search. + * @return - 0 if the ModR/M could be read when needed or was not + * needed; nonzero otherwise. + */ +static int getIDWithAttrMask(uint16_t *instructionID, + struct InternalInstruction* insn, + uint16_t attrMask) +{ + bool hasModRMExtension; + + InstructionContext instructionClass = contextForAttrs(attrMask); + + hasModRMExtension = modRMRequired(insn->opcodeType, + instructionClass, + insn->opcode); + + if (hasModRMExtension) { + if (readModRM(insn)) + return -1; + + *instructionID = decode(insn->opcodeType, + instructionClass, + insn->opcode, + insn->modRM); + } else { + *instructionID = decode(insn->opcodeType, + instructionClass, + insn->opcode, + 0); + } + + return 0; +} + +/* + * is16BitEquivalent - Determines whether two instruction names refer to + * equivalent instructions but one is 16-bit whereas the other is not. + * + * @param orig - The instruction ID that is not 16-bit + * @param equiv - The instruction ID that is 16-bit + */ +static bool is16BitEquivalent(unsigned orig, unsigned equiv) +{ + size_t i; + uint16_t idx; + + if ((idx = x86_16_bit_eq_lookup[orig]) != 0) { + for (i = idx - 1; i < ARR_SIZE(x86_16_bit_eq_tbl) && x86_16_bit_eq_tbl[i].first == orig; i++) { + if (x86_16_bit_eq_tbl[i].second == equiv) + return true; + } + } + + return false; +} + +/* + * is64Bit - Determines whether this instruction is a 64-bit instruction. + * + * @param name - The instruction that is not 16-bit + */ +static bool is64Bit(uint16_t id) +{ + unsigned int i = find_insn(id); + if (i != -1) { + return insns[i].is64bit; + } + + // not found?? + return false; +} + +/* + * getID - Determines the ID of an instruction, consuming the ModR/M byte as + * appropriate for extended and escape opcodes. Determines the attributes and + * context for the instruction before doing so. + * + * @param insn - The instruction whose ID is to be determined. + * @return - 0 if the ModR/M could be read when needed or was not needed; + * nonzero otherwise. + */ +static int getID(struct InternalInstruction *insn) +{ + uint16_t attrMask; + uint16_t instructionID; + + attrMask = ATTR_NONE; + + if (insn->mode == MODE_64BIT) + attrMask |= ATTR_64BIT; + + if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) { + attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX; + + if (insn->vectorExtensionType == TYPE_EVEX) { + switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) { + case VEX_PREFIX_66: + attrMask |= ATTR_OPSIZE; + break; + case VEX_PREFIX_F3: + attrMask |= ATTR_XS; + break; + case VEX_PREFIX_F2: + attrMask |= ATTR_XD; + break; + } + + if (zFromEVEX4of4(insn->vectorExtensionPrefix[3])) + attrMask |= ATTR_EVEXKZ; + if (bFromEVEX4of4(insn->vectorExtensionPrefix[3])) + attrMask |= ATTR_EVEXB; + if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])) + attrMask |= ATTR_EVEXK; + if (lFromEVEX4of4(insn->vectorExtensionPrefix[3])) + attrMask |= ATTR_EVEXL; + if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3])) + attrMask |= ATTR_EVEXL2; + } else if (insn->vectorExtensionType == TYPE_VEX_3B) { + switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) { + case VEX_PREFIX_66: + attrMask |= ATTR_OPSIZE; + break; + case VEX_PREFIX_F3: + attrMask |= ATTR_XS; + break; + case VEX_PREFIX_F2: + attrMask |= ATTR_XD; + break; + } + + if (lFromVEX3of3(insn->vectorExtensionPrefix[2])) + attrMask |= ATTR_VEXL; + } else if (insn->vectorExtensionType == TYPE_VEX_2B) { + switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) { + case VEX_PREFIX_66: + attrMask |= ATTR_OPSIZE; + break; + case VEX_PREFIX_F3: + attrMask |= ATTR_XS; + break; + case VEX_PREFIX_F2: + attrMask |= ATTR_XD; + break; + } + + if (lFromVEX2of2(insn->vectorExtensionPrefix[1])) + attrMask |= ATTR_VEXL; + } else if (insn->vectorExtensionType == TYPE_XOP) { + switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) { + case VEX_PREFIX_66: + attrMask |= ATTR_OPSIZE; + break; + case VEX_PREFIX_F3: + attrMask |= ATTR_XS; + break; + case VEX_PREFIX_F2: + attrMask |= ATTR_XD; + break; + } + + if (lFromXOP3of3(insn->vectorExtensionPrefix[2])) + attrMask |= ATTR_VEXL; + } else { + return -1; + } + } else if (!insn->mandatoryPrefix) { + // If we don't have mandatory prefix we should use legacy prefixes here + if (insn->hasOpSize && (insn->mode != MODE_16BIT)) + attrMask |= ATTR_OPSIZE; + if (insn->hasAdSize) + attrMask |= ATTR_ADSIZE; + if (insn->opcodeType == ONEBYTE) { + if (insn->repeatPrefix == 0xf3 && (insn->opcode == 0x90)) + // Special support for PAUSE + attrMask |= ATTR_XS; + } else { + if (insn->repeatPrefix == 0xf2) + attrMask |= ATTR_XD; + else if (insn->repeatPrefix == 0xf3) + attrMask |= ATTR_XS; + } + } else { + switch (insn->mandatoryPrefix) { + case 0xf2: + attrMask |= ATTR_XD; + break; + case 0xf3: + attrMask |= ATTR_XS; + break; + case 0x66: + if (insn->mode != MODE_16BIT) + attrMask |= ATTR_OPSIZE; + break; + case 0x67: + attrMask |= ATTR_ADSIZE; + break; + } + + } + + if (insn->rexPrefix & 0x08) { + attrMask |= ATTR_REXW; + attrMask &= ~ATTR_ADSIZE; + } + + /* + * JCXZ/JECXZ need special handling for 16-bit mode because the meaning + * of the AdSize prefix is inverted w.r.t. 32-bit mode. + */ + if (insn->mode == MODE_16BIT && insn->opcodeType == ONEBYTE && + insn->opcode == 0xE3) + attrMask ^= ATTR_ADSIZE; + + /* + * In 64-bit mode all f64 superscripted opcodes ignore opcode size prefix + * CALL/JMP/JCC instructions need to ignore 0x66 and consume 4 bytes + */ + if ((insn->mode == MODE_64BIT) && insn->hasOpSize) { + switch (insn->opcode) { + case 0xE8: + case 0xE9: + // Take care of psubsb and other mmx instructions. + if (insn->opcodeType == ONEBYTE) { + attrMask ^= ATTR_OPSIZE; + insn->immediateSize = 4; + insn->displacementSize = 4; + } + break; + case 0x82: + case 0x83: + case 0x84: + case 0x85: + case 0x86: + case 0x87: + case 0x88: + case 0x89: + case 0x8A: + case 0x8B: + case 0x8C: + case 0x8D: + case 0x8E: + case 0x8F: + // Take care of lea and three byte ops. + if (insn->opcodeType == TWOBYTE) { + attrMask ^= ATTR_OPSIZE; + insn->immediateSize = 4; + insn->displacementSize = 4; + } + break; + } + } + + /* The following clauses compensate for limitations of the tables. */ + if (insn->mode != MODE_64BIT && + insn->vectorExtensionType != TYPE_NO_VEX_XOP) { + if (getIDWithAttrMask(&instructionID, insn, attrMask)) { + return -1; + } + + /* + * The tables can't distinguish between cases where the W-bit is used to + * select register size and cases where it's a required part of the opcode. + */ + if ((insn->vectorExtensionType == TYPE_EVEX && + wFromEVEX3of4(insn->vectorExtensionPrefix[2])) || + (insn->vectorExtensionType == TYPE_VEX_3B && + wFromVEX3of3(insn->vectorExtensionPrefix[2])) || + (insn->vectorExtensionType == TYPE_XOP && + wFromXOP3of3(insn->vectorExtensionPrefix[2]))) { + uint16_t instructionIDWithREXW; + + if (getIDWithAttrMask(&instructionIDWithREXW, + insn, attrMask | ATTR_REXW)) { + insn->instructionID = instructionID; + insn->spec = specifierForUID(instructionID); + return 0; + } + + // If not a 64-bit instruction. Switch the opcode. + if (!is64Bit(instructionIDWithREXW)) { + insn->instructionID = instructionIDWithREXW; + insn->spec = specifierForUID(instructionIDWithREXW); + + return 0; + } + } + } + + /* + * Absolute moves, umonitor, and movdir64b need special handling. + * -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are + * inverted w.r.t. + * -For 32-bit mode we need to ensure the ADSIZE prefix is observed in + * any position. + */ + if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) || + (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) || + (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8)) { + /* Make sure we observed the prefixes in any position. */ + if (insn->hasAdSize) + attrMask |= ATTR_ADSIZE; + + if (insn->hasOpSize) + attrMask |= ATTR_OPSIZE; + + /* In 16-bit, invert the attributes. */ + if (insn->mode == MODE_16BIT) { + attrMask ^= ATTR_ADSIZE; + + /* The OpSize attribute is only valid with the absolute moves. */ + if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) + attrMask ^= ATTR_OPSIZE; + } + + if (getIDWithAttrMask(&instructionID, insn, attrMask)) { + return -1; + } + + insn->instructionID = instructionID; + insn->spec = specifierForUID(instructionID); + + return 0; + } + if (getIDWithAttrMask(&instructionID, insn, attrMask)) { + return -1; + } + + if ((insn->mode == MODE_16BIT || insn->hasOpSize) && + !(attrMask & ATTR_OPSIZE)) { + /* + * The instruction tables make no distinction between instructions that + * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a + * particular spot (i.e., many MMX operations). In general we're + * conservative, but in the specific case where OpSize is present but not + * in the right place we check if there's a 16-bit operation. + */ + const struct InstructionSpecifier *spec; + uint16_t instructionIDWithOpsize; + + spec = specifierForUID(instructionID); + + if (getIDWithAttrMask(&instructionIDWithOpsize, + insn, + attrMask | ATTR_OPSIZE)) { + /* + * ModRM required with OpSize but not present; give up and return version + * without OpSize set + */ + insn->instructionID = instructionID; + insn->spec = spec; + + return 0; + } + + if (is16BitEquivalent(instructionID, instructionIDWithOpsize) && + (insn->mode == MODE_16BIT) ^ insn->hasOpSize) { + insn->instructionID = instructionIDWithOpsize; + insn->spec = specifierForUID(instructionIDWithOpsize); + } else { + insn->instructionID = instructionID; + insn->spec = spec; + } + + return 0; + } + + if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 && + insn->rexPrefix & 0x01) { + /* + * NOOP shouldn't decode as NOOP if REX.b is set. Instead + * it should decode as XCHG %r8, %eax. + */ + const struct InstructionSpecifier *spec; + uint16_t instructionIDWithNewOpcode; + const struct InstructionSpecifier *specWithNewOpcode; + + spec = specifierForUID(instructionID); + + /* Borrow opcode from one of the other XCHGar opcodes */ + insn->opcode = 0x91; + + if (getIDWithAttrMask(&instructionIDWithNewOpcode, insn, attrMask)) { + insn->opcode = 0x90; + + insn->instructionID = instructionID; + insn->spec = spec; + + return 0; + } + + specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode); + + /* Change back */ + insn->opcode = 0x90; + + insn->instructionID = instructionIDWithNewOpcode; + insn->spec = specWithNewOpcode; + + return 0; + } + + insn->instructionID = instructionID; + insn->spec = specifierForUID(insn->instructionID); + + return 0; +} + +/* + * readSIB - Consumes the SIB byte to determine addressing information for an + * instruction. + * + * @param insn - The instruction whose SIB byte is to be read. + * @return - 0 if the SIB byte was successfully read; nonzero otherwise. + */ +static int readSIB(struct InternalInstruction* insn) +{ + SIBBase sibBaseBase = SIB_BASE_NONE; + uint8_t index, base; + + // dbgprintf(insn, "readSIB()"); + + if (insn->consumedSIB) + return 0; + + insn->consumedSIB = true; + + switch (insn->addressSize) { + case 2: + // dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode"); + return -1; + case 4: + insn->sibIndexBase = SIB_INDEX_EAX; + sibBaseBase = SIB_BASE_EAX; + break; + case 8: + insn->sibIndexBase = SIB_INDEX_RAX; + sibBaseBase = SIB_BASE_RAX; + break; + } + + if (consumeByte(insn, &insn->sib)) + return -1; + + index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3); + + if (index == 0x4) { + insn->sibIndex = SIB_INDEX_NONE; + } else { + insn->sibIndex = (SIBIndex)(insn->sibIndexBase + index); + } + + insn->sibScale = 1 << scaleFromSIB(insn->sib); + + base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3); + + switch (base) { + case 0x5: + case 0xd: + switch (modFromModRM(insn->modRM)) { + case 0x0: + insn->eaDisplacement = EA_DISP_32; + insn->sibBase = SIB_BASE_NONE; + break; + case 0x1: + insn->eaDisplacement = EA_DISP_8; + insn->sibBase = (SIBBase)(sibBaseBase + base); + break; + case 0x2: + insn->eaDisplacement = EA_DISP_32; + insn->sibBase = (SIBBase)(sibBaseBase + base); + break; + case 0x3: + // debug("Cannot have Mod = 0b11 and a SIB byte"); + return -1; + } + break; + default: + insn->sibBase = (SIBBase)(sibBaseBase + base); + break; + } + + return 0; +} + +/* + * readDisplacement - Consumes the displacement of an instruction. + * + * @param insn - The instruction whose displacement is to be read. + * @return - 0 if the displacement byte was successfully read; nonzero + * otherwise. + */ +static int readDisplacement(struct InternalInstruction* insn) +{ + int8_t d8; + int16_t d16; + int32_t d32; + + // dbgprintf(insn, "readDisplacement()"); + + if (insn->consumedDisplacement) + return 0; + + insn->consumedDisplacement = true; + insn->displacementOffset = insn->readerCursor - insn->startLocation; + + switch (insn->eaDisplacement) { + case EA_DISP_NONE: + insn->consumedDisplacement = false; + break; + case EA_DISP_8: + if (consumeInt8(insn, &d8)) + return -1; + insn->displacement = d8; + break; + case EA_DISP_16: + if (consumeInt16(insn, &d16)) + return -1; + insn->displacement = d16; + break; + case EA_DISP_32: + if (consumeInt32(insn, &d32)) + return -1; + insn->displacement = d32; + break; + } + + + return 0; +} + +/* + * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and + * displacement) for an instruction and interprets it. + * + * @param insn - The instruction whose addressing information is to be read. + * @return - 0 if the information was successfully read; nonzero otherwise. + */ +static int readModRM(struct InternalInstruction* insn) +{ + uint8_t mod, rm, reg, evexrm; + + // dbgprintf(insn, "readModRM()"); + + if (insn->consumedModRM) + return 0; + + insn->modRMOffset = (uint8_t)(insn->readerCursor - insn->startLocation); + + if (consumeByte(insn, &insn->modRM)) + return -1; + + insn->consumedModRM = true; + + // save original ModRM for later reference + insn->orgModRM = insn->modRM; + + // handle MOVcr, MOVdr, MOVrc, MOVrd by pretending they have MRM.mod = 3 + if ((insn->firstByte == 0x0f && insn->opcodeType == TWOBYTE) && + (insn->opcode >= 0x20 && insn->opcode <= 0x23 )) + insn->modRM |= 0xC0; + + mod = modFromModRM(insn->modRM); + rm = rmFromModRM(insn->modRM); + reg = regFromModRM(insn->modRM); + + /* + * This goes by insn->registerSize to pick the correct register, which messes + * up if we're using (say) XMM or 8-bit register operands. That gets fixed in + * fixupReg(). + */ + switch (insn->registerSize) { + case 2: + insn->regBase = MODRM_REG_AX; + insn->eaRegBase = EA_REG_AX; + break; + case 4: + insn->regBase = MODRM_REG_EAX; + insn->eaRegBase = EA_REG_EAX; + break; + case 8: + insn->regBase = MODRM_REG_RAX; + insn->eaRegBase = EA_REG_RAX; + break; + } + + reg |= rFromREX(insn->rexPrefix) << 3; + rm |= bFromREX(insn->rexPrefix) << 3; + + evexrm = 0; + if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT) { + reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4; + evexrm = xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4; + } + + insn->reg = (Reg)(insn->regBase + reg); + + switch (insn->addressSize) { + case 2: { + EABase eaBaseBase = EA_BASE_BX_SI; + + switch (mod) { + case 0x0: + if (rm == 0x6) { + insn->eaBase = EA_BASE_NONE; + insn->eaDisplacement = EA_DISP_16; + if (readDisplacement(insn)) + return -1; + } else { + insn->eaBase = (EABase)(eaBaseBase + rm); + insn->eaDisplacement = EA_DISP_NONE; + } + break; + case 0x1: + insn->eaBase = (EABase)(eaBaseBase + rm); + insn->eaDisplacement = EA_DISP_8; + insn->displacementSize = 1; + if (readDisplacement(insn)) + return -1; + break; + case 0x2: + insn->eaBase = (EABase)(eaBaseBase + rm); + insn->eaDisplacement = EA_DISP_16; + if (readDisplacement(insn)) + return -1; + break; + case 0x3: + insn->eaBase = (EABase)(insn->eaRegBase + rm); + if (readDisplacement(insn)) + return -1; + break; + } + break; + } + + case 4: + case 8: { + EABase eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX); + + switch (mod) { + default: break; + case 0x0: + insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */ + // In determining whether RIP-relative mode is used (rm=5), + // or whether a SIB byte is present (rm=4), + // the extension bits (REX.b and EVEX.x) are ignored. + switch (rm & 7) { + case 0x4: // SIB byte is present + insn->eaBase = (insn->addressSize == 4 ? + EA_BASE_sib : EA_BASE_sib64); + if (readSIB(insn) || readDisplacement(insn)) + return -1; + break; + case 0x5: // RIP-relative + insn->eaBase = EA_BASE_NONE; + insn->eaDisplacement = EA_DISP_32; + if (readDisplacement(insn)) + return -1; + break; + default: + insn->eaBase = (EABase)(eaBaseBase + rm); + break; + } + break; + case 0x1: + insn->displacementSize = 1; + /* FALLTHROUGH */ + case 0x2: + insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32); + switch (rm & 7) { + case 0x4: // SIB byte is present + insn->eaBase = EA_BASE_sib; + if (readSIB(insn) || readDisplacement(insn)) + return -1; + break; + default: + insn->eaBase = (EABase)(eaBaseBase + rm); + if (readDisplacement(insn)) + return -1; + break; + } + break; + case 0x3: + insn->eaDisplacement = EA_DISP_NONE; + insn->eaBase = (EABase)(insn->eaRegBase + rm + evexrm); + break; + } + + break; + } + } /* switch (insn->addressSize) */ + + return 0; +} + +#define GENERIC_FIXUP_FUNC(name, base, prefix, mask) \ + static uint16_t name(struct InternalInstruction *insn, \ + OperandType type, \ + uint8_t index, \ + uint8_t *valid) { \ + *valid = 1; \ + switch (type) { \ + default: \ + *valid = 0; \ + return 0; \ + case TYPE_Rv: \ + return base + index; \ + case TYPE_R8: \ + index &= mask; \ + if (index > 0xf) \ + *valid = 0; \ + if (insn->rexPrefix && \ + index >= 4 && index <= 7) { \ + return prefix##_SPL + (index - 4); \ + } else { \ + return prefix##_AL + index; \ + } \ + case TYPE_R16: \ + index &= mask; \ + if (index > 0xf) \ + *valid = 0; \ + return prefix##_AX + index; \ + case TYPE_R32: \ + index &= mask; \ + if (index > 0xf) \ + *valid = 0; \ + return prefix##_EAX + index; \ + case TYPE_R64: \ + index &= mask; \ + if (index > 0xf) \ + *valid = 0; \ + return prefix##_RAX + index; \ + case TYPE_ZMM: \ + return prefix##_ZMM0 + index; \ + case TYPE_YMM: \ + return prefix##_YMM0 + index; \ + case TYPE_XMM: \ + return prefix##_XMM0 + index; \ + case TYPE_VK: \ + index &= 0xf; \ + if (index > 7) \ + *valid = 0; \ + return prefix##_K0 + index; \ + case TYPE_MM64: \ + return prefix##_MM0 + (index & 0x7); \ + case TYPE_SEGMENTREG: \ + if ((index & 7) > 5) \ + *valid = 0; \ + return prefix##_ES + (index & 7); \ + case TYPE_DEBUGREG: \ + return prefix##_DR0 + index; \ + case TYPE_CONTROLREG: \ + return prefix##_CR0 + index; \ + case TYPE_BNDR: \ + if (index > 3) \ + *valid = 0; \ + return prefix##_BND0 + index; \ + case TYPE_MVSIBX: \ + return prefix##_XMM0 + index; \ + case TYPE_MVSIBY: \ + return prefix##_YMM0 + index; \ + case TYPE_MVSIBZ: \ + return prefix##_ZMM0 + index; \ + } \ + } + +/* + * fixup*Value - Consults an operand type to determine the meaning of the + * reg or R/M field. If the operand is an XMM operand, for example, an + * operand would be XMM0 instead of AX, which readModRM() would otherwise + * misinterpret it as. + * + * @param insn - The instruction containing the operand. + * @param type - The operand type. + * @param index - The existing value of the field as reported by readModRM(). + * @param valid - The address of a uint8_t. The target is set to 1 if the + * field is valid for the register class; 0 if not. + * @return - The proper value. + */ +GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG, 0x1f) +GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG, 0xf) + +/* + * fixupReg - Consults an operand specifier to determine which of the + * fixup*Value functions to use in correcting readModRM()'ss interpretation. + * + * @param insn - See fixup*Value(). + * @param op - The operand specifier. + * @return - 0 if fixup was successful; -1 if the register returned was + * invalid for its class. + */ +static int fixupReg(struct InternalInstruction *insn, + const struct OperandSpecifier *op) +{ + uint8_t valid; + + switch ((OperandEncoding)op->encoding) { + default: + // debug("Expected a REG or R/M encoding in fixupReg"); + return -1; + case ENCODING_VVVV: + insn->vvvv = (Reg)fixupRegValue(insn, + (OperandType)op->type, + insn->vvvv, + &valid); + if (!valid) + return -1; + break; + case ENCODING_REG: + insn->reg = (Reg)fixupRegValue(insn, + (OperandType)op->type, + insn->reg - insn->regBase, + &valid); + if (!valid) + return -1; + break; + CASE_ENCODING_RM: + if (insn->eaBase >= insn->eaRegBase) { + insn->eaBase = (EABase)fixupRMValue(insn, + (OperandType)op->type, + insn->eaBase - insn->eaRegBase, + &valid); + if (!valid) + return -1; + } + break; + } + + return 0; +} + +/* + * readOpcodeRegister - Reads an operand from the opcode field of an + * instruction and interprets it appropriately given the operand width. + * Handles AddRegFrm instructions. + * + * @param insn - the instruction whose opcode field is to be read. + * @param size - The width (in bytes) of the register being specified. + * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means + * RAX. + * @return - 0 on success; nonzero otherwise. + */ +static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) +{ + if (size == 0) + size = insn->registerSize; + + switch (size) { + case 1: + insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3) + | (insn->opcode & 7))); + if (insn->rexPrefix && + insn->opcodeRegister >= MODRM_REG_AL + 0x4 && + insn->opcodeRegister < MODRM_REG_AL + 0x8) { + insn->opcodeRegister = (Reg)(MODRM_REG_SPL + + (insn->opcodeRegister - MODRM_REG_AL - 4)); + } + + break; + case 2: + insn->opcodeRegister = (Reg)(MODRM_REG_AX + + ((bFromREX(insn->rexPrefix) << 3) + | (insn->opcode & 7))); + break; + case 4: + insn->opcodeRegister = (Reg)(MODRM_REG_EAX + + ((bFromREX(insn->rexPrefix) << 3) + | (insn->opcode & 7))); + break; + case 8: + insn->opcodeRegister = (Reg)(MODRM_REG_RAX + + ((bFromREX(insn->rexPrefix) << 3) + | (insn->opcode & 7))); + break; + } + + return 0; +} + +/* + * readImmediate - Consumes an immediate operand from an instruction, given the + * desired operand size. + * + * @param insn - The instruction whose operand is to be read. + * @param size - The width (in bytes) of the operand. + * @return - 0 if the immediate was successfully consumed; nonzero + * otherwise. + */ +static int readImmediate(struct InternalInstruction* insn, uint8_t size) +{ + uint8_t imm8; + uint16_t imm16; + uint32_t imm32; + uint64_t imm64; + + if (insn->numImmediatesConsumed == 2) { + // debug("Already consumed two immediates"); + return -1; + } + + if (size == 0) + size = insn->immediateSize; + else + insn->immediateSize = size; + + insn->immediateOffset = insn->readerCursor - insn->startLocation; + + switch (size) { + case 1: + if (consumeByte(insn, &imm8)) + return -1; + + insn->immediates[insn->numImmediatesConsumed] = imm8; + break; + case 2: + if (consumeUInt16(insn, &imm16)) + return -1; + + insn->immediates[insn->numImmediatesConsumed] = imm16; + break; + case 4: + if (consumeUInt32(insn, &imm32)) + return -1; + + insn->immediates[insn->numImmediatesConsumed] = imm32; + break; + case 8: + if (consumeUInt64(insn, &imm64)) + return -1; + insn->immediates[insn->numImmediatesConsumed] = imm64; + break; + } + + insn->numImmediatesConsumed++; + + return 0; +} + +/* + * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix. + * + * @param insn - The instruction whose operand is to be read. + * @return - 0 if the vvvv was successfully consumed; nonzero + * otherwise. + */ +static int readVVVV(struct InternalInstruction* insn) +{ + int vvvv; + + if (insn->vectorExtensionType == TYPE_EVEX) + vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 | + vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2])); + else if (insn->vectorExtensionType == TYPE_VEX_3B) + vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]); + else if (insn->vectorExtensionType == TYPE_VEX_2B) + vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]); + else if (insn->vectorExtensionType == TYPE_XOP) + vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]); + else + return -1; + + if (insn->mode != MODE_64BIT) + vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later. + + insn->vvvv = (Reg)vvvv; + + return 0; +} + +/* + * readMaskRegister - Reads an mask register from the opcode field of an + * instruction. + * + * @param insn - The instruction whose opcode field is to be read. + * @return - 0 on success; nonzero otherwise. + */ +static int readMaskRegister(struct InternalInstruction* insn) +{ + if (insn->vectorExtensionType != TYPE_EVEX) + return -1; + + insn->writemask = (Reg)(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])); + + return 0; +} + +/* + * readOperands - Consults the specifier for an instruction and consumes all + * operands for that instruction, interpreting them as it goes. + * + * @param insn - The instruction whose operands are to be read and interpreted. + * @return - 0 if all operands could be read; nonzero otherwise. + */ +static int readOperands(struct InternalInstruction* insn) +{ + int hasVVVV, needVVVV; + int sawRegImm = 0; + int i; + + /* If non-zero vvvv specified, need to make sure one of the operands + uses it. */ + hasVVVV = !readVVVV(insn); + needVVVV = hasVVVV && (insn->vvvv != 0); + + for (i = 0; i < X86_MAX_OPERANDS; ++i) { + const OperandSpecifier *op = &x86OperandSets[insn->spec->operands][i]; + switch (op->encoding) { + case ENCODING_NONE: + case ENCODING_SI: + case ENCODING_DI: + break; + + CASE_ENCODING_VSIB: + // VSIB can use the V2 bit so check only the other bits. + if (needVVVV) + needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0); + + if (readModRM(insn)) + return -1; + + // Reject if SIB wasn't used. + if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64) + return -1; + + // If sibIndex was set to SIB_INDEX_NONE, index offset is 4. + if (insn->sibIndex == SIB_INDEX_NONE) + insn->sibIndex = (SIBIndex)(insn->sibIndexBase + 4); + + // If EVEX.v2 is set this is one of the 16-31 registers. + if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT && + v2FromEVEX4of4(insn->vectorExtensionPrefix[3])) + insn->sibIndex = (SIBIndex)(insn->sibIndex + 16); + + // Adjust the index register to the correct size. + switch (op->type) { + default: + // debug("Unhandled VSIB index type"); + return -1; + case TYPE_MVSIBX: + insn->sibIndex = (SIBIndex)(SIB_INDEX_XMM0 + + (insn->sibIndex - insn->sibIndexBase)); + break; + case TYPE_MVSIBY: + insn->sibIndex = (SIBIndex)(SIB_INDEX_YMM0 + + (insn->sibIndex - insn->sibIndexBase)); + break; + case TYPE_MVSIBZ: + insn->sibIndex = (SIBIndex)(SIB_INDEX_ZMM0 + + (insn->sibIndex - insn->sibIndexBase)); + break; + } + + // Apply the AVX512 compressed displacement scaling factor. + if (op->encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) + insn->displacement *= 1 << (op->encoding - ENCODING_VSIB); + break; + + case ENCODING_REG: + CASE_ENCODING_RM: + if (readModRM(insn)) + return -1; + + if (fixupReg(insn, op)) + return -1; + + // Apply the AVX512 compressed displacement scaling factor. + if (op->encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) + insn->displacement *= 1 << (op->encoding - ENCODING_RM); + break; + + case ENCODING_IB: + if (sawRegImm) { + /* Saw a register immediate so don't read again and instead split the + previous immediate. FIXME: This is a hack. */ + insn->immediates[insn->numImmediatesConsumed] = + insn->immediates[insn->numImmediatesConsumed - 1] & 0xf; + ++insn->numImmediatesConsumed; + break; + } + if (readImmediate(insn, 1)) + return -1; + if (op->type == TYPE_XMM || op->type == TYPE_YMM) + sawRegImm = 1; + break; + + case ENCODING_IW: + if (readImmediate(insn, 2)) + return -1; + break; + + case ENCODING_ID: + if (readImmediate(insn, 4)) + return -1; + break; + + case ENCODING_IO: + if (readImmediate(insn, 8)) + return -1; + break; + + case ENCODING_Iv: + if (readImmediate(insn, insn->immediateSize)) + return -1; + break; + + case ENCODING_Ia: + if (readImmediate(insn, insn->addressSize)) + return -1; + /* Direct memory-offset (moffset) immediate will get mapped + to memory operand later. We want the encoding info to + reflect that as well. */ + insn->displacementOffset = insn->immediateOffset; + insn->consumedDisplacement = true; + insn->displacementSize = insn->immediateSize; + insn->displacement = insn->immediates[insn->numImmediatesConsumed - 1]; + insn->immediateOffset = 0; + insn->immediateSize = 0; + break; + + case ENCODING_IRC: + insn->RC = (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 1) | + lFromEVEX4of4(insn->vectorExtensionPrefix[3]); + break; + + case ENCODING_RB: + if (readOpcodeRegister(insn, 1)) + return -1; + break; + + case ENCODING_RW: + if (readOpcodeRegister(insn, 2)) + return -1; + break; + + case ENCODING_RD: + if (readOpcodeRegister(insn, 4)) + return -1; + break; + + case ENCODING_RO: + if (readOpcodeRegister(insn, 8)) + return -1; + break; + + case ENCODING_Rv: + if (readOpcodeRegister(insn, 0)) + return -1; + break; + + case ENCODING_FP: + break; + + case ENCODING_VVVV: + if (!hasVVVV) + return -1; + + needVVVV = 0; /* Mark that we have found a VVVV operand. */ + + if (insn->mode != MODE_64BIT) + insn->vvvv = (Reg)(insn->vvvv & 0x7); + + if (fixupReg(insn, op)) + return -1; + break; + + case ENCODING_WRITEMASK: + if (readMaskRegister(insn)) + return -1; + break; + + case ENCODING_DUP: + break; + + default: + // dbgprintf(insn, "Encountered an operand with an unknown encoding."); + return -1; + } + } + + /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */ + if (needVVVV) + return -1; + + return 0; +} + +// return True if instruction is illegal to use with prefixes +// This also check & fix the isPrefixNN when a prefix is irrelevant. +static bool checkPrefix(struct InternalInstruction *insn) +{ + // LOCK prefix + if (insn->hasLockPrefix) { + switch(insn->instructionID) { + default: + // invalid LOCK + return true; + + // nop dword [rax] + case X86_NOOPL: + + // DEC + case X86_DEC16m: + case X86_DEC32m: + case X86_DEC64m: + case X86_DEC8m: + + // ADC + case X86_ADC16mi: + case X86_ADC16mi8: + case X86_ADC16mr: + case X86_ADC32mi: + case X86_ADC32mi8: + case X86_ADC32mr: + case X86_ADC64mi32: + case X86_ADC64mi8: + case X86_ADC64mr: + case X86_ADC8mi: + case X86_ADC8mi8: + case X86_ADC8mr: + case X86_ADC8rm: + case X86_ADC16rm: + case X86_ADC32rm: + case X86_ADC64rm: + + // ADD + case X86_ADD16mi: + case X86_ADD16mi8: + case X86_ADD16mr: + case X86_ADD32mi: + case X86_ADD32mi8: + case X86_ADD32mr: + case X86_ADD64mi32: + case X86_ADD64mi8: + case X86_ADD64mr: + case X86_ADD8mi: + case X86_ADD8mi8: + case X86_ADD8mr: + case X86_ADD8rm: + case X86_ADD16rm: + case X86_ADD32rm: + case X86_ADD64rm: + + // AND + case X86_AND16mi: + case X86_AND16mi8: + case X86_AND16mr: + case X86_AND32mi: + case X86_AND32mi8: + case X86_AND32mr: + case X86_AND64mi32: + case X86_AND64mi8: + case X86_AND64mr: + case X86_AND8mi: + case X86_AND8mi8: + case X86_AND8mr: + case X86_AND8rm: + case X86_AND16rm: + case X86_AND32rm: + case X86_AND64rm: + + // BTC + case X86_BTC16mi8: + case X86_BTC16mr: + case X86_BTC32mi8: + case X86_BTC32mr: + case X86_BTC64mi8: + case X86_BTC64mr: + + // BTR + case X86_BTR16mi8: + case X86_BTR16mr: + case X86_BTR32mi8: + case X86_BTR32mr: + case X86_BTR64mi8: + case X86_BTR64mr: + + // BTS + case X86_BTS16mi8: + case X86_BTS16mr: + case X86_BTS32mi8: + case X86_BTS32mr: + case X86_BTS64mi8: + case X86_BTS64mr: + + // CMPXCHG + case X86_CMPXCHG16B: + case X86_CMPXCHG16rm: + case X86_CMPXCHG32rm: + case X86_CMPXCHG64rm: + case X86_CMPXCHG8rm: + case X86_CMPXCHG8B: + + // INC + case X86_INC16m: + case X86_INC32m: + case X86_INC64m: + case X86_INC8m: + + // NEG + case X86_NEG16m: + case X86_NEG32m: + case X86_NEG64m: + case X86_NEG8m: + + // NOT + case X86_NOT16m: + case X86_NOT32m: + case X86_NOT64m: + case X86_NOT8m: + + // OR + case X86_OR16mi: + case X86_OR16mi8: + case X86_OR16mr: + case X86_OR32mi: + case X86_OR32mi8: + case X86_OR32mr: + case X86_OR64mi32: + case X86_OR64mi8: + case X86_OR64mr: + case X86_OR8mi8: + case X86_OR8mi: + case X86_OR8mr: + case X86_OR8rm: + case X86_OR16rm: + case X86_OR32rm: + case X86_OR64rm: + + // SBB + case X86_SBB16mi: + case X86_SBB16mi8: + case X86_SBB16mr: + case X86_SBB32mi: + case X86_SBB32mi8: + case X86_SBB32mr: + case X86_SBB64mi32: + case X86_SBB64mi8: + case X86_SBB64mr: + case X86_SBB8mi: + case X86_SBB8mi8: + case X86_SBB8mr: + + // SUB + case X86_SUB16mi: + case X86_SUB16mi8: + case X86_SUB16mr: + case X86_SUB32mi: + case X86_SUB32mi8: + case X86_SUB32mr: + case X86_SUB64mi32: + case X86_SUB64mi8: + case X86_SUB64mr: + case X86_SUB8mi8: + case X86_SUB8mi: + case X86_SUB8mr: + case X86_SUB8rm: + case X86_SUB16rm: + case X86_SUB32rm: + case X86_SUB64rm: + + // XADD + case X86_XADD16rm: + case X86_XADD32rm: + case X86_XADD64rm: + case X86_XADD8rm: + + // XCHG + case X86_XCHG16rm: + case X86_XCHG32rm: + case X86_XCHG64rm: + case X86_XCHG8rm: + + // XOR + case X86_XOR16mi: + case X86_XOR16mi8: + case X86_XOR16mr: + case X86_XOR32mi: + case X86_XOR32mi8: + case X86_XOR32mr: + case X86_XOR64mi32: + case X86_XOR64mi8: + case X86_XOR64mr: + case X86_XOR8mi8: + case X86_XOR8mi: + case X86_XOR8mr: + case X86_XOR8rm: + case X86_XOR16rm: + case X86_XOR32rm: + case X86_XOR64rm: + + // this instruction can be used with LOCK prefix + return false; + } + } + +#if 0 + // REPNE prefix + if (insn->repeatPrefix) { + // 0xf2 can be a part of instruction encoding, but not really a prefix. + // In such a case, clear it. + if (insn->twoByteEscape == 0x0f) { + insn->prefix0 = 0; + } + } +#endif + + // no invalid prefixes + return false; +} + +/* + * decodeInstruction - Reads and interprets a full instruction provided by the + * user. + * + * @param insn - A pointer to the instruction to be populated. Must be + * pre-allocated. + * @param reader - The function to be used to read the instruction's bytes. + * @param readerArg - A generic argument to be passed to the reader to store + * any internal state. + * @param startLoc - The address (in the reader's address space) of the first + * byte in the instruction. + * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to + * decode the instruction in. + * @return - 0 if instruction is valid; nonzero if not. + */ +int decodeInstruction(struct InternalInstruction *insn, + byteReader_t reader, + const void *readerArg, + uint64_t startLoc, + DisassemblerMode mode) +{ + insn->reader = reader; + insn->readerArg = readerArg; + insn->startLocation = startLoc; + insn->readerCursor = startLoc; + insn->mode = mode; + insn->numImmediatesConsumed = 0; + + if (readPrefixes(insn) || + readOpcode(insn) || + getID(insn) || + insn->instructionID == 0 || + checkPrefix(insn) || + readOperands(insn)) + return -1; + + insn->length = (size_t)(insn->readerCursor - insn->startLocation); + + // instruction length must be <= 15 to be valid + if (insn->length > 15) + return -1; + + if (insn->operandSize == 0) + insn->operandSize = insn->registerSize; + + insn->operands = &x86OperandSets[insn->spec->operands][0]; + + return 0; +} + +#endif + diff --git a/thirdparty/capstone/arch/X86/X86DisassemblerDecoder.h b/thirdparty/capstone/arch/X86/X86DisassemblerDecoder.h new file mode 100644 index 0000000..86e5f4c --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86DisassemblerDecoder.h @@ -0,0 +1,725 @@ +/*===-- X86DisassemblerDecoderInternal.h - Disassembler decoder ---*- C -*-===* + * + * The LLVM Compiler Infrastructure + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + * + *===----------------------------------------------------------------------===* + * + * This file is part of the X86 Disassembler. + * It contains the public interface of the instruction decoder. + * Documentation for the disassembler can be found in X86Disassembler.h. + * + *===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +#ifndef CS_X86_DISASSEMBLERDECODER_H +#define CS_X86_DISASSEMBLERDECODER_H + +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#else +#include +#endif + +#include "X86DisassemblerDecoderCommon.h" + +/* + * Accessor functions for various fields of an Intel instruction + */ +#define modFromModRM(modRM) (((modRM) & 0xc0) >> 6) +#define regFromModRM(modRM) (((modRM) & 0x38) >> 3) +#define rmFromModRM(modRM) ((modRM) & 0x7) +#define scaleFromSIB(sib) (((sib) & 0xc0) >> 6) +#define indexFromSIB(sib) (((sib) & 0x38) >> 3) +#define baseFromSIB(sib) ((sib) & 0x7) +#define wFromREX(rex) (((rex) & 0x8) >> 3) +#define rFromREX(rex) (((rex) & 0x4) >> 2) +#define xFromREX(rex) (((rex) & 0x2) >> 1) +#define bFromREX(rex) ((rex) & 0x1) + +#define rFromEVEX2of4(evex) (((~(evex)) & 0x80) >> 7) +#define xFromEVEX2of4(evex) (((~(evex)) & 0x40) >> 6) +#define bFromEVEX2of4(evex) (((~(evex)) & 0x20) >> 5) +#define r2FromEVEX2of4(evex) (((~(evex)) & 0x10) >> 4) +#define mmFromEVEX2of4(evex) ((evex) & 0x3) +#define wFromEVEX3of4(evex) (((evex) & 0x80) >> 7) +#define vvvvFromEVEX3of4(evex) (((~(evex)) & 0x78) >> 3) +#define ppFromEVEX3of4(evex) ((evex) & 0x3) +#define zFromEVEX4of4(evex) (((evex) & 0x80) >> 7) +#define l2FromEVEX4of4(evex) (((evex) & 0x40) >> 6) +#define lFromEVEX4of4(evex) (((evex) & 0x20) >> 5) +#define bFromEVEX4of4(evex) (((evex) & 0x10) >> 4) +#define v2FromEVEX4of4(evex) (((~evex) & 0x8) >> 3) +#define aaaFromEVEX4of4(evex) ((evex) & 0x7) + +#define rFromVEX2of3(vex) (((~(vex)) & 0x80) >> 7) +#define xFromVEX2of3(vex) (((~(vex)) & 0x40) >> 6) +#define bFromVEX2of3(vex) (((~(vex)) & 0x20) >> 5) +#define mmmmmFromVEX2of3(vex) ((vex) & 0x1f) +#define wFromVEX3of3(vex) (((vex) & 0x80) >> 7) +#define vvvvFromVEX3of3(vex) (((~(vex)) & 0x78) >> 3) +#define lFromVEX3of3(vex) (((vex) & 0x4) >> 2) +#define ppFromVEX3of3(vex) ((vex) & 0x3) + +#define rFromVEX2of2(vex) (((~(vex)) & 0x80) >> 7) +#define vvvvFromVEX2of2(vex) (((~(vex)) & 0x78) >> 3) +#define lFromVEX2of2(vex) (((vex) & 0x4) >> 2) +#define ppFromVEX2of2(vex) ((vex) & 0x3) + +#define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7) +#define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6) +#define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5) +#define mmmmmFromXOP2of3(xop) ((xop) & 0x1f) +#define wFromXOP3of3(xop) (((xop) & 0x80) >> 7) +#define vvvvFromXOP3of3(vex) (((~(vex)) & 0x78) >> 3) +#define lFromXOP3of3(xop) (((xop) & 0x4) >> 2) +#define ppFromXOP3of3(xop) ((xop) & 0x3) + +/* + * These enums represent Intel registers for use by the decoder. + */ + +#define REGS_8BIT \ + ENTRY(AL) \ + ENTRY(CL) \ + ENTRY(DL) \ + ENTRY(BL) \ + ENTRY(AH) \ + ENTRY(CH) \ + ENTRY(DH) \ + ENTRY(BH) \ + ENTRY(R8B) \ + ENTRY(R9B) \ + ENTRY(R10B) \ + ENTRY(R11B) \ + ENTRY(R12B) \ + ENTRY(R13B) \ + ENTRY(R14B) \ + ENTRY(R15B) \ + ENTRY(SPL) \ + ENTRY(BPL) \ + ENTRY(SIL) \ + ENTRY(DIL) + +#define EA_BASES_16BIT \ + ENTRY(BX_SI) \ + ENTRY(BX_DI) \ + ENTRY(BP_SI) \ + ENTRY(BP_DI) \ + ENTRY(SI) \ + ENTRY(DI) \ + ENTRY(BP) \ + ENTRY(BX) \ + ENTRY(R8W) \ + ENTRY(R9W) \ + ENTRY(R10W) \ + ENTRY(R11W) \ + ENTRY(R12W) \ + ENTRY(R13W) \ + ENTRY(R14W) \ + ENTRY(R15W) + +#define REGS_16BIT \ + ENTRY(AX) \ + ENTRY(CX) \ + ENTRY(DX) \ + ENTRY(BX) \ + ENTRY(SP) \ + ENTRY(BP) \ + ENTRY(SI) \ + ENTRY(DI) \ + ENTRY(R8W) \ + ENTRY(R9W) \ + ENTRY(R10W) \ + ENTRY(R11W) \ + ENTRY(R12W) \ + ENTRY(R13W) \ + ENTRY(R14W) \ + ENTRY(R15W) + +#define EA_BASES_32BIT \ + ENTRY(EAX) \ + ENTRY(ECX) \ + ENTRY(EDX) \ + ENTRY(EBX) \ + ENTRY(sib) \ + ENTRY(EBP) \ + ENTRY(ESI) \ + ENTRY(EDI) \ + ENTRY(R8D) \ + ENTRY(R9D) \ + ENTRY(R10D) \ + ENTRY(R11D) \ + ENTRY(R12D) \ + ENTRY(R13D) \ + ENTRY(R14D) \ + ENTRY(R15D) + +#define REGS_32BIT \ + ENTRY(EAX) \ + ENTRY(ECX) \ + ENTRY(EDX) \ + ENTRY(EBX) \ + ENTRY(ESP) \ + ENTRY(EBP) \ + ENTRY(ESI) \ + ENTRY(EDI) \ + ENTRY(R8D) \ + ENTRY(R9D) \ + ENTRY(R10D) \ + ENTRY(R11D) \ + ENTRY(R12D) \ + ENTRY(R13D) \ + ENTRY(R14D) \ + ENTRY(R15D) + +#define EA_BASES_64BIT \ + ENTRY(RAX) \ + ENTRY(RCX) \ + ENTRY(RDX) \ + ENTRY(RBX) \ + ENTRY(sib64) \ + ENTRY(RBP) \ + ENTRY(RSI) \ + ENTRY(RDI) \ + ENTRY(R8) \ + ENTRY(R9) \ + ENTRY(R10) \ + ENTRY(R11) \ + ENTRY(R12) \ + ENTRY(R13) \ + ENTRY(R14) \ + ENTRY(R15) + +#define REGS_64BIT \ + ENTRY(RAX) \ + ENTRY(RCX) \ + ENTRY(RDX) \ + ENTRY(RBX) \ + ENTRY(RSP) \ + ENTRY(RBP) \ + ENTRY(RSI) \ + ENTRY(RDI) \ + ENTRY(R8) \ + ENTRY(R9) \ + ENTRY(R10) \ + ENTRY(R11) \ + ENTRY(R12) \ + ENTRY(R13) \ + ENTRY(R14) \ + ENTRY(R15) + +#define REGS_MMX \ + ENTRY(MM0) \ + ENTRY(MM1) \ + ENTRY(MM2) \ + ENTRY(MM3) \ + ENTRY(MM4) \ + ENTRY(MM5) \ + ENTRY(MM6) \ + ENTRY(MM7) + +#define REGS_XMM \ + ENTRY(XMM0) \ + ENTRY(XMM1) \ + ENTRY(XMM2) \ + ENTRY(XMM3) \ + ENTRY(XMM4) \ + ENTRY(XMM5) \ + ENTRY(XMM6) \ + ENTRY(XMM7) \ + ENTRY(XMM8) \ + ENTRY(XMM9) \ + ENTRY(XMM10) \ + ENTRY(XMM11) \ + ENTRY(XMM12) \ + ENTRY(XMM13) \ + ENTRY(XMM14) \ + ENTRY(XMM15) \ + ENTRY(XMM16) \ + ENTRY(XMM17) \ + ENTRY(XMM18) \ + ENTRY(XMM19) \ + ENTRY(XMM20) \ + ENTRY(XMM21) \ + ENTRY(XMM22) \ + ENTRY(XMM23) \ + ENTRY(XMM24) \ + ENTRY(XMM25) \ + ENTRY(XMM26) \ + ENTRY(XMM27) \ + ENTRY(XMM28) \ + ENTRY(XMM29) \ + ENTRY(XMM30) \ + ENTRY(XMM31) + + +#define REGS_YMM \ + ENTRY(YMM0) \ + ENTRY(YMM1) \ + ENTRY(YMM2) \ + ENTRY(YMM3) \ + ENTRY(YMM4) \ + ENTRY(YMM5) \ + ENTRY(YMM6) \ + ENTRY(YMM7) \ + ENTRY(YMM8) \ + ENTRY(YMM9) \ + ENTRY(YMM10) \ + ENTRY(YMM11) \ + ENTRY(YMM12) \ + ENTRY(YMM13) \ + ENTRY(YMM14) \ + ENTRY(YMM15) \ + ENTRY(YMM16) \ + ENTRY(YMM17) \ + ENTRY(YMM18) \ + ENTRY(YMM19) \ + ENTRY(YMM20) \ + ENTRY(YMM21) \ + ENTRY(YMM22) \ + ENTRY(YMM23) \ + ENTRY(YMM24) \ + ENTRY(YMM25) \ + ENTRY(YMM26) \ + ENTRY(YMM27) \ + ENTRY(YMM28) \ + ENTRY(YMM29) \ + ENTRY(YMM30) \ + ENTRY(YMM31) + +#define REGS_ZMM \ + ENTRY(ZMM0) \ + ENTRY(ZMM1) \ + ENTRY(ZMM2) \ + ENTRY(ZMM3) \ + ENTRY(ZMM4) \ + ENTRY(ZMM5) \ + ENTRY(ZMM6) \ + ENTRY(ZMM7) \ + ENTRY(ZMM8) \ + ENTRY(ZMM9) \ + ENTRY(ZMM10) \ + ENTRY(ZMM11) \ + ENTRY(ZMM12) \ + ENTRY(ZMM13) \ + ENTRY(ZMM14) \ + ENTRY(ZMM15) \ + ENTRY(ZMM16) \ + ENTRY(ZMM17) \ + ENTRY(ZMM18) \ + ENTRY(ZMM19) \ + ENTRY(ZMM20) \ + ENTRY(ZMM21) \ + ENTRY(ZMM22) \ + ENTRY(ZMM23) \ + ENTRY(ZMM24) \ + ENTRY(ZMM25) \ + ENTRY(ZMM26) \ + ENTRY(ZMM27) \ + ENTRY(ZMM28) \ + ENTRY(ZMM29) \ + ENTRY(ZMM30) \ + ENTRY(ZMM31) + +#define REGS_MASKS \ + ENTRY(K0) \ + ENTRY(K1) \ + ENTRY(K2) \ + ENTRY(K3) \ + ENTRY(K4) \ + ENTRY(K5) \ + ENTRY(K6) \ + ENTRY(K7) + +#define REGS_SEGMENT \ + ENTRY(ES) \ + ENTRY(CS) \ + ENTRY(SS) \ + ENTRY(DS) \ + ENTRY(FS) \ + ENTRY(GS) + +#define REGS_DEBUG \ + ENTRY(DR0) \ + ENTRY(DR1) \ + ENTRY(DR2) \ + ENTRY(DR3) \ + ENTRY(DR4) \ + ENTRY(DR5) \ + ENTRY(DR6) \ + ENTRY(DR7) \ + ENTRY(DR8) \ + ENTRY(DR9) \ + ENTRY(DR10) \ + ENTRY(DR11) \ + ENTRY(DR12) \ + ENTRY(DR13) \ + ENTRY(DR14) \ + ENTRY(DR15) + +#define REGS_CONTROL \ + ENTRY(CR0) \ + ENTRY(CR1) \ + ENTRY(CR2) \ + ENTRY(CR3) \ + ENTRY(CR4) \ + ENTRY(CR5) \ + ENTRY(CR6) \ + ENTRY(CR7) \ + ENTRY(CR8) \ + ENTRY(CR9) \ + ENTRY(CR10) \ + ENTRY(CR11) \ + ENTRY(CR12) \ + ENTRY(CR13) \ + ENTRY(CR14) \ + ENTRY(CR15) + +#define REGS_BOUND \ + ENTRY(BND0) \ + ENTRY(BND1) \ + ENTRY(BND2) \ + ENTRY(BND3) + +#define ALL_EA_BASES \ + EA_BASES_16BIT \ + EA_BASES_32BIT \ + EA_BASES_64BIT + +#define ALL_SIB_BASES \ + REGS_32BIT \ + REGS_64BIT + +#define ALL_REGS \ + REGS_8BIT \ + REGS_16BIT \ + REGS_32BIT \ + REGS_64BIT \ + REGS_MMX \ + REGS_XMM \ + REGS_YMM \ + REGS_ZMM \ + REGS_MASKS \ + REGS_SEGMENT \ + REGS_DEBUG \ + REGS_CONTROL \ + REGS_BOUND \ + ENTRY(RIP) + +/* + * EABase - All possible values of the base field for effective-address + * computations, a.k.a. the Mod and R/M fields of the ModR/M byte. We + * distinguish between bases (EA_BASE_*) and registers that just happen to be + * referred to when Mod == 0b11 (EA_REG_*). + */ +typedef enum { + EA_BASE_NONE, +#define ENTRY(x) EA_BASE_##x, + ALL_EA_BASES +#undef ENTRY +#define ENTRY(x) EA_REG_##x, + ALL_REGS +#undef ENTRY + EA_max +} EABase; + +/* + * SIBIndex - All possible values of the SIB index field. + * Borrows entries from ALL_EA_BASES with the special case that + * sib is synonymous with NONE. + * Vector SIB: index can be XMM or YMM. + */ +typedef enum { + SIB_INDEX_NONE, +#define ENTRY(x) SIB_INDEX_##x, + ALL_EA_BASES + REGS_XMM + REGS_YMM + REGS_ZMM +#undef ENTRY + SIB_INDEX_max +} SIBIndex; + +/* + * SIBBase - All possible values of the SIB base field. + */ +typedef enum { + SIB_BASE_NONE, +#define ENTRY(x) SIB_BASE_##x, + ALL_SIB_BASES +#undef ENTRY + SIB_BASE_max +} SIBBase; + +/* + * EADisplacement - Possible displacement types for effective-address + * computations. + */ +typedef enum { + EA_DISP_NONE, + EA_DISP_8, + EA_DISP_16, + EA_DISP_32 +} EADisplacement; + +/* + * Reg - All possible values of the reg field in the ModR/M byte. + */ +typedef enum { +#define ENTRY(x) MODRM_REG_##x, + ALL_REGS +#undef ENTRY + MODRM_REG_max +} Reg; + +/* + * SegmentOverride - All possible segment overrides. + */ +typedef enum { + SEG_OVERRIDE_NONE, + SEG_OVERRIDE_CS, + SEG_OVERRIDE_SS, + SEG_OVERRIDE_DS, + SEG_OVERRIDE_ES, + SEG_OVERRIDE_FS, + SEG_OVERRIDE_GS, + SEG_OVERRIDE_max +} SegmentOverride; + +/* + * VEXLeadingOpcodeByte - Possible values for the VEX.m-mmmm field + */ +typedef enum { + VEX_LOB_0F = 0x1, + VEX_LOB_0F38 = 0x2, + VEX_LOB_0F3A = 0x3 +} VEXLeadingOpcodeByte; + +typedef enum { + XOP_MAP_SELECT_8 = 0x8, + XOP_MAP_SELECT_9 = 0x9, + XOP_MAP_SELECT_A = 0xA +} XOPMapSelect; + +/* + * VEXPrefixCode - Possible values for the VEX.pp/EVEX.pp field + */ +typedef enum { + VEX_PREFIX_NONE = 0x0, + VEX_PREFIX_66 = 0x1, + VEX_PREFIX_F3 = 0x2, + VEX_PREFIX_F2 = 0x3 +} VEXPrefixCode; + +typedef enum { + TYPE_NO_VEX_XOP = 0x0, + TYPE_VEX_2B = 0x1, + TYPE_VEX_3B = 0x2, + TYPE_EVEX = 0x3, + TYPE_XOP = 0x4 +} VectorExtensionType; + +struct reader_info { + const uint8_t *code; + uint64_t size; + uint64_t offset; +}; + +/* + * byteReader_t - Type for the byte reader that the consumer must provide to + * the decoder. Reads a single byte from the instruction's address space. + * @param arg - A baton that the consumer can associate with any internal + * state that it needs. + * @param byte - A pointer to a single byte in memory that should be set to + * contain the value at address. + * @param address - The address in the instruction's address space that should + * be read from. + * @return - -1 if the byte cannot be read for any reason; 0 otherwise. + */ +typedef int (*byteReader_t)(const struct reader_info *arg, uint8_t* byte, uint64_t address); + +/// The specification for how to extract and interpret a full instruction and +/// its operands. +struct InstructionSpecifier { +#ifdef CAPSTONE_X86_REDUCE + uint8_t operands; +#else + uint16_t operands; +#endif +}; + +/* + * The x86 internal instruction, which is produced by the decoder. + */ +typedef struct InternalInstruction { + // from here, all members must be initialized to ZERO to work properly + uint8_t operandSize; + uint8_t prefix0, prefix1, prefix2, prefix3; + /* The value of the REX prefix, if present */ + uint8_t rexPrefix; + /* The segment override type */ + SegmentOverride segmentOverride; + bool consumedModRM; + uint8_t orgModRM; // save original modRM because we will modify modRM + /* The SIB byte, used for more complex 32- or 64-bit memory operands */ + bool consumedSIB; + uint8_t sib; + /* The displacement, used for memory operands */ + bool consumedDisplacement; + int64_t displacement; + /* The value of the two-byte escape prefix (usually 0x0f) */ + uint8_t twoByteEscape; + /* The value of the three-byte escape prefix (usually 0x38 or 0x3a) */ + uint8_t threeByteEscape; + /* SIB state */ + SIBIndex sibIndexBase; + SIBIndex sibIndex; + uint8_t sibScale; + SIBBase sibBase; + + // Embedded rounding control. + uint8_t RC; + + uint8_t numImmediatesConsumed; + /* 0xf2 or 0xf3 is xacquire or xrelease */ + uint8_t xAcquireRelease; + + // Address-size override + bool hasAdSize; + // Operand-size override + bool hasOpSize; + // Lock prefix + bool hasLockPrefix; + // The repeat prefix if any + uint8_t repeatPrefix; + + // The possible mandatory prefix + uint8_t mandatoryPrefix; + + /* The value of the vector extension prefix(EVEX/VEX/XOP), if present */ + uint8_t vectorExtensionPrefix[4]; + + /* Offsets from the start of the instruction to the pieces of data, which is + needed to find relocation entries for adding symbolic operands */ + uint8_t displacementOffset; + uint8_t immediateOffset; + uint8_t modRMOffset; + + // end-of-zero-members + + /* Reader interface (C) */ + byteReader_t reader; + + /* Opaque value passed to the reader */ + const void* readerArg; + /* The address of the next byte to read via the reader */ + uint64_t readerCursor; + + /* General instruction information */ + + /* The mode to disassemble for (64-bit, protected, real) */ + DisassemblerMode mode; + /* The start of the instruction, usable with the reader */ + uint64_t startLocation; + /* The length of the instruction, in bytes */ + size_t length; + + /* Prefix state */ + + /* The type of the vector extension prefix */ + VectorExtensionType vectorExtensionType; + + /* Sizes of various critical pieces of data, in bytes */ + uint8_t registerSize; + uint8_t addressSize; + uint8_t displacementSize; + uint8_t immediateSize; + + uint8_t immSize; // immediate size for X86_OP_IMM operand + + /* opcode state */ + + /* The last byte of the opcode, not counting any ModR/M extension */ + uint8_t opcode; + + /* decode state */ + + /* The type of opcode, used for indexing into the array of decode tables */ + OpcodeType opcodeType; + /* The instruction ID, extracted from the decode table */ + uint16_t instructionID; + /* The specifier for the instruction, from the instruction info table */ + const struct InstructionSpecifier *spec; + + /* state for additional bytes, consumed during operand decode. Pattern: + consumed___ indicates that the byte was already consumed and does not + need to be consumed again */ + + /* The VEX.vvvv field, which contains a third register operand for some AVX + instructions */ + Reg vvvv; + + /* The writemask for AVX-512 instructions which is contained in EVEX.aaa */ + Reg writemask; + + /* The ModR/M byte, which contains most register operands and some portion of + all memory operands */ + uint8_t modRM; + + // special data to handle MOVcr, MOVdr, MOVrc, MOVrd + uint8_t firstByte; // save the first byte in stream + + /* Immediates. There can be two in some cases */ + uint8_t numImmediatesTranslated; + uint64_t immediates[2]; + + /* A register or immediate operand encoded into the opcode */ + Reg opcodeRegister; + + /* Portions of the ModR/M byte */ + + /* These fields determine the allowable values for the ModR/M fields, which + depend on operand and address widths */ + EABase eaRegBase; + Reg regBase; + + /* The Mod and R/M fields can encode a base for an effective address, or a + register. These are separated into two fields here */ + EABase eaBase; + EADisplacement eaDisplacement; + /* The reg field always encodes a register */ + Reg reg; + + const struct OperandSpecifier *operands; +} InternalInstruction; + +/* decodeInstruction - Decode one instruction and store the decoding results in + * a buffer provided by the consumer. + * @param insn - The buffer to store the instruction in. Allocated by the + * consumer. + * @param reader - The byteReader_t for the bytes to be read. + * @param readerArg - An argument to pass to the reader for storing context + * specific to the consumer. May be NULL. + * @param logger - The dlog_t to be used in printing status messages from the + * disassembler. May be NULL. + * @param loggerArg - An argument to pass to the logger for storing context + * specific to the logger. May be NULL. + * @param startLoc - The address (in the reader's address space) of the first + * byte in the instruction. + * @param mode - The mode (16-bit, 32-bit, 64-bit) to decode in. + * @return - Nonzero if there was an error during decode, 0 otherwise. + */ +int decodeInstruction(struct InternalInstruction* insn, + byteReader_t reader, + const void* readerArg, + uint64_t startLoc, + DisassemblerMode mode); + +//const char *x86DisassemblerGetInstrName(unsigned Opcode, const void *mii); + +#endif diff --git a/thirdparty/capstone/arch/X86/X86DisassemblerDecoderCommon.h b/thirdparty/capstone/arch/X86/X86DisassemblerDecoderCommon.h new file mode 100644 index 0000000..edf68aa --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86DisassemblerDecoderCommon.h @@ -0,0 +1,483 @@ +/*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===* + * + * The LLVM Compiler Infrastructure + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + * + *===----------------------------------------------------------------------===* + * + * This file is part of the X86 Disassembler. + * It contains common definitions used by both the disassembler and the table + * generator. + * Documentation for the disassembler can be found in X86Disassembler.h. + * + *===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/* + * This header file provides those definitions that need to be shared between + * the decoder and the table generator in a C-friendly manner. + */ + +#ifndef CS_X86_DISASSEMBLERDECODERCOMMON_H +#define CS_X86_DISASSEMBLERDECODERCOMMON_H + +#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers +#define CONTEXTS_SYM x86DisassemblerContexts +#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes +#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes +#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes +#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes +#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes +#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes +#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes +#define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes + + +/* + * Attributes of an instruction that must be known before the opcode can be + * processed correctly. Most of these indicate the presence of particular + * prefixes, but ATTR_64BIT is simply an attribute of the decoding context. + */ +#define ATTRIBUTE_BITS \ + ENUM_ENTRY(ATTR_NONE, 0x00) \ + ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \ + ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \ + ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \ + ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \ + ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \ + ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \ + ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \ + ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \ + ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \ + ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \ + ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \ + ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \ + ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \ + ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13)) + +#define ENUM_ENTRY(n, v) n = v, +enum attributeBits { + ATTRIBUTE_BITS + ATTR_max +}; +#undef ENUM_ENTRY + +/* + * Combinations of the above attributes that are relevant to instruction + * decode. Although other combinations are possible, they can be reduced to + * these without affecting the ultimately decoded instruction. + */ + +// Class name Rank Rationale for rank assignment +#define INSTRUCTION_CONTEXTS \ + ENUM_ENTRY(IC, 0, "says nothing about the instruction") \ + ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \ + "64-bit mode but no more") \ + ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \ + "operands change width") \ + ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \ + "operands change width") \ + ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \ + ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \ + "but not the operands") \ + ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \ + "but not the operands") \ + ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \ + "operands change width") \ + ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \ + "operands change width") \ + ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \ + "operands change width") \ + ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \ + "operands change width") \ + ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\ + "change width; overrides IC_OPSIZE") \ + ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \ + "prefix") \ + ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \ + ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \ + ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, "Just as meaningful as IC_OPSIZE/" \ + "IC_ADSIZE") \ + ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is " \ + "secondary") \ + ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \ + ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \ + ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \ + ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \ + ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \ + ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different " \ + "opcode") \ + ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as " \ + "IC_64BIT_REXW_XS") \ + ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, "The Dynamic Duo! Prefer over all " \ + "else because this changes most " \ + "operands' meaning") \ + ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \ + ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \ + ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \ + ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \ + ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \ + ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \ + ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \ + ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \ + ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \ + ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\ + ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\ + ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \ + ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \ + ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \ + ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \ + ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \ + ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \ + ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \ + ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \ + ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \ + ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \ + ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \ + ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \ + ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \ + ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\ + ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\ + ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \ + ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \ + ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \ + ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \ + ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \ + ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\ + ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\ + ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \ + ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \ + ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \ + ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \ + ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \ + ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \ + ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \ + ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \ + ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \ + ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \ + ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \ + ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \ + ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\ + ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\ + ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \ + ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \ + ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \ + ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \ + ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \ + ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\ + ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\ + ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \ + ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \ + ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \ + ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \ + ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \ + ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \ + ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \ + ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \ + ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \ + ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \ + ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \ + ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \ + ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\ + ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\ + ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \ + ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \ + ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \ + ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \ + ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \ + ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\ + ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\ + ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \ + ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \ + ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \ + ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \ + ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \ + ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \ + ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \ + ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \ + ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \ + ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \ + ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \ + ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \ + ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\ + ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\ + ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \ + ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \ + ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \ + ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \ + ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \ + ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\ + ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\ + ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \ + ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \ + ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \ + ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \ + ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \ + ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \ + ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \ + ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \ + ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \ + ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \ + ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \ + ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \ + ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\ + ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\ + ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \ + ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \ + ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \ + ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \ + ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \ + ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\ + ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\ + ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \ + ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \ + ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \ + ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \ + ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \ + ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \ + ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \ + ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \ + ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \ + ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \ + ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \ + ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \ + ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\ + ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\ + ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \ + ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \ + ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \ + ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \ + ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \ + ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\ + ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\ + ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \ + ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \ + ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \ + ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \ + ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize") + +#define ENUM_ENTRY(n, r, d) n, +typedef enum { + INSTRUCTION_CONTEXTS + IC_max +} InstructionContext; +#undef ENUM_ENTRY + +/* + * Opcode types, which determine which decode table to use, both in the Intel + * manual and also for the decoder. + */ +typedef enum { + ONEBYTE = 0, + TWOBYTE = 1, + THREEBYTE_38 = 2, + THREEBYTE_3A = 3, + XOP8_MAP = 4, + XOP9_MAP = 5, + XOPA_MAP = 6, + THREEDNOW_MAP = 7 +} OpcodeType; + +/* + * The following structs are used for the hierarchical decode table. After + * determining the instruction's class (i.e., which IC_* constant applies to + * it), the decoder reads the opcode. Some instructions require specific + * values of the ModR/M byte, so the ModR/M byte indexes into the final table. + * + * If a ModR/M byte is not required, "required" is left unset, and the values + * for each instructionID are identical. + */ + +typedef uint16_t InstrUID; + +/* + * ModRMDecisionType - describes the type of ModR/M decision, allowing the + * consumer to determine the number of entries in it. + * + * MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded + * instruction is the same. + * MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode + * corresponds to one instruction; otherwise, it corresponds to + * a different instruction. + * MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte + * divided by 8 is used to select instruction; otherwise, each + * value of the ModR/M byte could correspond to a different + * instruction. + * MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This + corresponds to instructions that use reg field as opcode + * MODRM_FULL - Potentially, each value of the ModR/M byte could correspond + * to a different instruction. + */ + +#define MODRMTYPES \ + ENUM_ENTRY(MODRM_ONEENTRY) \ +ENUM_ENTRY(MODRM_SPLITRM) \ +ENUM_ENTRY(MODRM_SPLITMISC) \ +ENUM_ENTRY(MODRM_SPLITREG) \ +ENUM_ENTRY(MODRM_FULL) + +#define ENUM_ENTRY(n) n, +typedef enum { + MODRMTYPES + MODRM_max +} ModRMDecisionType; +#undef ENUM_ENTRY + +#define CASE_ENCODING_RM \ + case ENCODING_RM: \ + case ENCODING_RM_CD2: \ + case ENCODING_RM_CD4: \ + case ENCODING_RM_CD8: \ + case ENCODING_RM_CD16: \ + case ENCODING_RM_CD32: \ + case ENCODING_RM_CD64 + +#define CASE_ENCODING_VSIB \ + case ENCODING_VSIB: \ + case ENCODING_VSIB_CD2: \ + case ENCODING_VSIB_CD4: \ + case ENCODING_VSIB_CD8: \ + case ENCODING_VSIB_CD16: \ + case ENCODING_VSIB_CD32: \ + case ENCODING_VSIB_CD64 + +// Physical encodings of instruction operands. + +#define ENCODINGS \ +ENUM_ENTRY(ENCODING_NONE, "") \ +ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \ +ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \ +ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \ +ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \ +ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \ +ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \ +ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \ +ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \ +ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \ +ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \ +ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \ +ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \ +ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16") \ +ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32") \ +ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64") \ +ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \ +ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \ +ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \ +ENUM_ENTRY(ENCODING_IW, "2-byte") \ +ENUM_ENTRY(ENCODING_ID, "4-byte") \ +ENUM_ENTRY(ENCODING_IO, "8-byte") \ +ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \ + "the opcode byte") \ +ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \ +ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \ +ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \ +ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \ + "byte.") \ +ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \ +ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \ +ENUM_ENTRY(ENCODING_IRC, "Immediate for static rounding control") \ +ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \ + "opcode byte") \ +ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \ + "in type") \ +ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \ +ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes") + +#define ENUM_ENTRY(n, d) n, +typedef enum { + ENCODINGS + ENCODING_max +} OperandEncoding; +#undef ENUM_ENTRY + +/* + * Semantic interpretations of instruction operands. + */ +#define TYPES \ + ENUM_ENTRY(TYPE_NONE, "") \ + ENUM_ENTRY(TYPE_REL, "immediate address") \ + ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ + ENUM_ENTRY(TYPE_R16, "2-byte") \ + ENUM_ENTRY(TYPE_R32, "4-byte") \ + ENUM_ENTRY(TYPE_R64, "8-byte") \ + ENUM_ENTRY(TYPE_IMM, "immediate operand") \ + ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \ + ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \ + ENUM_ENTRY(TYPE_AVX512ICC, "1-byte immediate operand for AVX512 icmp") \ + ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \ + ENUM_ENTRY(TYPE_M, "Memory operand") \ + ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \ + ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \ + ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \ + ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \ + ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \ + ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \ + ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ + ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \ + ENUM_ENTRY(TYPE_XMM, "16-byte") \ + ENUM_ENTRY(TYPE_YMM, "32-byte") \ + ENUM_ENTRY(TYPE_ZMM, "64-byte") \ + ENUM_ENTRY(TYPE_VK, "mask register") \ + ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ + ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ + ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ + ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \ + \ + ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ + ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ + ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ + ENUM_ENTRY(TYPE_DUP1, "operand 1") \ + ENUM_ENTRY(TYPE_DUP2, "operand 2") \ + ENUM_ENTRY(TYPE_DUP3, "operand 3") \ + ENUM_ENTRY(TYPE_DUP4, "operand 4") \ + +#define ENUM_ENTRY(n, d) n, +typedef enum { + TYPES + TYPE_max +} OperandType; +#undef ENUM_ENTRY + +/* + * The specification for how to extract and interpret one operand. + */ +typedef struct OperandSpecifier { + uint8_t encoding; + uint8_t type; +} OperandSpecifier; + +#define X86_MAX_OPERANDS 6 + +/* + * Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode + * are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, + * respectively. + */ +typedef enum { + MODE_16BIT, + MODE_32BIT, + MODE_64BIT +} DisassemblerMode; + +#endif diff --git a/thirdparty/capstone/arch/X86/X86GenAsmWriter.inc b/thirdparty/capstone/arch/X86/X86GenAsmWriter.inc new file mode 100644 index 0000000..2c1bf4a --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenAsmWriter.inc @@ -0,0 +1,49199 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) +{ +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '0', 9, 0, + /* 12 */ 's', 'h', 'a', '1', 'm', 's', 'g', '1', 9, 0, + /* 22 */ 's', 'h', 'a', '2', '5', '6', 'm', 's', 'g', '1', 9, 0, + /* 34 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '1', 9, 0, + /* 46 */ 'p', 'f', 'r', 'c', 'p', 'i', 't', '1', 9, 0, + /* 56 */ 'p', 'f', 'r', 's', 'q', 'i', 't', '1', 9, 0, + /* 66 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'w', 't', '1', 9, 0, + /* 79 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', '3', '2', 9, 0, + /* 90 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '3', '2', 9, 0, + /* 101 */ 's', 'h', 'a', '1', 'm', 's', 'g', '2', 9, 0, + /* 111 */ 's', 'h', 'a', '2', '5', '6', 'm', 's', 'g', '2', 9, 0, + /* 123 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '2', 9, 0, + /* 135 */ 'p', 'f', 'r', 'c', 'p', 'i', 't', '2', 9, 0, + /* 145 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '3', '2', 'x', '2', 9, 0, + /* 162 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '2', 9, 0, + /* 179 */ 'v', 's', 'h', 'u', 'f', 'f', '6', '4', 'x', '2', 9, 0, + /* 191 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '6', '4', 'x', '2', 9, 0, + /* 206 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '6', '4', 'x', '2', 9, 0, + /* 220 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '6', '4', 'x', '2', 9, 0, + /* 237 */ 'v', 's', 'h', 'u', 'f', 'i', '6', '4', 'x', '2', 9, 0, + /* 249 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '6', '4', 'x', '2', 9, 0, + /* 264 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '6', '4', 'x', '2', 9, 0, + /* 278 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '6', '4', 'x', '2', 9, 0, + /* 295 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', '6', '4', 9, 0, + /* 306 */ 'x', 's', 'a', 'v', 'e', 'c', '6', '4', 9, 0, + /* 316 */ 'f', 'x', 's', 'a', 'v', 'e', '6', '4', 9, 0, + /* 326 */ 'f', 'x', 'r', 's', 't', 'o', 'r', '6', '4', 9, 0, + /* 337 */ 'x', 's', 'a', 'v', 'e', 's', '6', '4', 9, 0, + /* 347 */ 'x', 'r', 's', 't', 'o', 'r', 's', '6', '4', 9, 0, + /* 358 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', '6', '4', 9, 0, + /* 370 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '6', '4', 9, 0, + /* 381 */ 's', 'h', 'a', '1', 'r', 'n', 'd', 's', '4', 9, 0, + /* 392 */ 'v', 's', 'h', 'u', 'f', 'f', '3', '2', 'x', '4', 9, 0, + /* 404 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '3', '2', 'x', '4', 9, 0, + /* 419 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '3', '2', 'x', '4', 9, 0, + /* 433 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '3', '2', 'x', '4', 9, 0, + /* 450 */ 'v', 's', 'h', 'u', 'f', 'i', '3', '2', 'x', '4', 9, 0, + /* 462 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '3', '2', 'x', '4', 9, 0, + /* 477 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '3', '2', 'x', '4', 9, 0, + /* 491 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '4', 9, 0, + /* 508 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '6', '4', 'x', '4', 9, 0, + /* 523 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '6', '4', 'x', '4', 9, 0, + /* 537 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '6', '4', 'x', '4', 9, 0, + /* 554 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '6', '4', 'x', '4', 9, 0, + /* 569 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '6', '4', 'x', '4', 9, 0, + /* 583 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '6', '4', 'x', '4', 9, 0, + /* 600 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '1', '6', 9, 0, + /* 611 */ 'v', 'p', 'e', 'r', 'm', '2', 'f', '1', '2', '8', 9, 0, + /* 623 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '1', '2', '8', 9, 0, + /* 637 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '1', '2', '8', 9, 0, + /* 650 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '1', '2', '8', 9, 0, + /* 666 */ 'v', 'p', 'e', 'r', 'm', '2', 'i', '1', '2', '8', 9, 0, + /* 678 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '1', '2', '8', 9, 0, + /* 692 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '1', '2', '8', 9, 0, + /* 705 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '1', '2', '8', 9, 0, + /* 721 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '8', 9, 0, + /* 731 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '3', '2', 'x', '8', 9, 0, + /* 746 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '3', '2', 'x', '8', 9, 0, + /* 760 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '3', '2', 'x', '8', 9, 0, + /* 777 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '3', '2', 'x', '8', 9, 0, + /* 792 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '3', '2', 'x', '8', 9, 0, + /* 806 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '8', 9, 0, + /* 823 */ 'j', 'a', 9, 0, + /* 827 */ 'v', 'm', 'o', 'v', 'n', 't', 'd', 'q', 'a', 9, 0, + /* 838 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', 9, 0, + /* 847 */ 's', 'e', 't', 'a', 9, 0, + /* 853 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'n', 't', 'a', 9, 0, + /* 866 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, + /* 874 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'b', 9, 0, + /* 884 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'b', 9, 0, + /* 894 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'b', 9, 0, + /* 904 */ 'm', 'o', 'v', 'd', 'i', 'r', '6', '4', 'b', 9, 0, + /* 915 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0, + /* 927 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '8', 'b', 9, 0, + /* 938 */ 'v', 'p', 's', 'h', 'a', 'b', 9, 0, + /* 946 */ 's', 'b', 'b', 'b', 9, 0, + /* 952 */ 'v', 'p', 's', 'u', 'b', 'b', 9, 0, + /* 960 */ 'a', 'd', 'c', 'b', 9, 0, + /* 966 */ 'd', 'e', 'c', 'b', 9, 0, + /* 972 */ 'i', 'n', 'c', 'b', 9, 0, + /* 978 */ 'l', 'l', 'w', 'p', 'c', 'b', 9, 0, + /* 986 */ 's', 'l', 'w', 'p', 'c', 'b', 9, 0, + /* 994 */ 'k', 'a', 'd', 'd', 'b', 9, 0, + /* 1001 */ 'v', 'p', 'a', 'd', 'd', 'b', 9, 0, + /* 1009 */ 'x', 'a', 'd', 'd', 'b', 9, 0, + /* 1016 */ 'k', 'a', 'n', 'd', 'b', 9, 0, + /* 1023 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'b', 9, 0, + /* 1034 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'd', 'b', 9, 0, + /* 1045 */ 'v', 'p', 'm', 'o', 'v', 's', 'd', 'b', 9, 0, + /* 1055 */ 'v', 'p', 'm', 'o', 'v', 'd', 'b', 9, 0, + /* 1064 */ 'v', 'p', 's', 'h', 'u', 'f', 'b', 9, 0, + /* 1073 */ 'n', 'e', 'g', 'b', 9, 0, + /* 1079 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'b', 9, 0, + /* 1089 */ 'v', 'p', 'a', 'v', 'g', 'b', 9, 0, + /* 1097 */ 'j', 'b', 9, 0, + /* 1101 */ 'v', 'p', 'm', 'o', 'v', 'm', 's', 'k', 'b', 9, 0, + /* 1112 */ 's', 'a', 'l', 'b', 9, 0, + /* 1118 */ 'r', 'c', 'l', 'b', 9, 0, + /* 1124 */ 'v', 'p', 's', 'h', 'l', 'b', 9, 0, + /* 1132 */ 'r', 'o', 'l', 'b', 9, 0, + /* 1138 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'b', 9, 0, + /* 1148 */ 'v', 'g', 'f', '2', 'p', '8', 'm', 'u', 'l', 'b', 9, 0, + /* 1160 */ 'i', 'm', 'u', 'l', 'b', 9, 0, + /* 1167 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'b', 9, 0, + /* 1178 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'b', 9, 0, + /* 1189 */ 'v', 'p', 'c', 'o', 'm', 'b', 9, 0, + /* 1197 */ 'v', 'p', 's', 'h', 'u', 'f', 'b', 'i', 't', 'q', 'm', 'b', 9, 0, + /* 1211 */ 'v', 'p', 'e', 'r', 'm', 'b', 9, 0, + /* 1219 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'b', 9, 0, + /* 1229 */ 'k', 'a', 'n', 'd', 'n', 'b', 9, 0, + /* 1237 */ 'v', 'p', 's', 'i', 'g', 'n', 'b', 9, 0, + /* 1246 */ 'i', 'n', 'b', 9, 0, + /* 1251 */ 'f', 'c', 'm', 'o', 'v', 'n', 'b', 9, 0, + /* 1260 */ 'v', 'p', 'c', 'm', 'p', 'b', 9, 0, + /* 1268 */ 'v', 'g', 'f', '2', 'p', '8', 'a', 'f', 'f', 'i', 'n', 'e', 'q', 'b', 9, 0, + /* 1284 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'b', 9, 0, + /* 1294 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'b', 9, 0, + /* 1305 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'b', 9, 0, + /* 1315 */ 'v', 'p', 'm', 'u', 'l', 't', 'i', 's', 'h', 'i', 'f', 't', 'q', 'b', 9, 0, + /* 1331 */ 'v', 'g', 'f', '2', 'p', '8', 'a', 'f', 'f', 'i', 'n', 'e', 'i', 'n', 'v', 'q', 'b', 9, 0, + /* 1350 */ 'v', 'p', 'm', 'o', 'v', 'q', 'b', 9, 0, + /* 1359 */ 's', 'a', 'r', 'b', 9, 0, + /* 1365 */ 'r', 'c', 'r', 'b', 9, 0, + /* 1371 */ 's', 'h', 'r', 'b', 9, 0, + /* 1377 */ 'k', 'o', 'r', 'b', 9, 0, + /* 1383 */ 'k', 'x', 'n', 'o', 'r', 'b', 9, 0, + /* 1391 */ 'r', 'o', 'r', 'b', 9, 0, + /* 1397 */ 'k', 'x', 'o', 'r', 'b', 9, 0, + /* 1404 */ 'v', 'p', 'i', 'n', 's', 'r', 'b', 9, 0, + /* 1413 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'b', 9, 0, + /* 1423 */ 'v', 'p', 'e', 'x', 't', 'r', 'b', 9, 0, + /* 1432 */ 's', 'c', 'a', 's', 'b', 9, 0, + /* 1439 */ 'v', 'p', 'a', 'b', 's', 'b', 9, 0, + /* 1447 */ 'm', 'o', 'v', 'a', 'b', 's', 'b', 9, 0, + /* 1456 */ 'v', 'p', 's', 'u', 'b', 's', 'b', 9, 0, + /* 1465 */ 'v', 'p', 'a', 'd', 'd', 's', 'b', 9, 0, + /* 1474 */ 'l', 'o', 'd', 's', 'b', 9, 0, + /* 1481 */ 'v', 'p', 'm', 'i', 'n', 's', 'b', 9, 0, + /* 1490 */ 'c', 'm', 'p', 's', 'b', 9, 0, + /* 1497 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'b', 9, 0, + /* 1510 */ 'o', 'u', 't', 's', 'b', 9, 0, + /* 1517 */ 'v', 'p', 's', 'u', 'b', 'u', 's', 'b', 9, 0, + /* 1527 */ 'v', 'p', 'a', 'd', 'd', 'u', 's', 'b', 9, 0, + /* 1537 */ 'p', 'a', 'v', 'g', 'u', 's', 'b', 9, 0, + /* 1546 */ 'm', 'o', 'v', 's', 'b', 9, 0, + /* 1553 */ 'v', 'p', 'm', 'a', 'x', 's', 'b', 9, 0, + /* 1562 */ 's', 'e', 't', 'b', 9, 0, + /* 1568 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'b', 9, 0, + /* 1578 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'b', 9, 0, + /* 1588 */ 'k', 'n', 'o', 't', 'b', 9, 0, + /* 1595 */ 'v', 'p', 'r', 'o', 't', 'b', 9, 0, + /* 1603 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'b', 9, 0, + /* 1617 */ 'k', 't', 'e', 's', 't', 'b', 9, 0, + /* 1625 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'b', 9, 0, + /* 1635 */ 'v', 'p', 'c', 'o', 'm', 'u', 'b', 9, 0, + /* 1644 */ 'v', 'p', 'm', 'i', 'n', 'u', 'b', 9, 0, + /* 1653 */ 'v', 'p', 'c', 'm', 'p', 'u', 'b', 9, 0, + /* 1662 */ 'p', 'f', 's', 'u', 'b', 9, 0, + /* 1669 */ 'v', 'p', 'm', 'a', 'x', 'u', 'b', 9, 0, + /* 1678 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'v', 'b', 9, 0, + /* 1689 */ 'i', 'd', 'i', 'v', 'b', 9, 0, + /* 1696 */ 'f', 'c', 'm', 'o', 'v', 'b', 9, 0, + /* 1704 */ 'k', 'm', 'o', 'v', 'b', 9, 0, + /* 1711 */ 'c', 'l', 'w', 'b', 9, 0, + /* 1717 */ 'v', 'p', 'a', 'c', 'k', 's', 's', 'w', 'b', 9, 0, + /* 1728 */ 'v', 'p', 'a', 'c', 'k', 'u', 's', 'w', 'b', 9, 0, + /* 1739 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'w', 'b', 9, 0, + /* 1750 */ 'v', 'p', 'm', 'o', 'v', 's', 'w', 'b', 9, 0, + /* 1760 */ 'v', 'p', 'm', 'o', 'v', 'w', 'b', 9, 0, + /* 1769 */ 'p', 'f', 'a', 'c', 'c', 9, 0, + /* 1776 */ 'p', 'f', 'n', 'a', 'c', 'c', 9, 0, + /* 1784 */ 'p', 'f', 'p', 'n', 'a', 'c', 'c', 9, 0, + /* 1793 */ 'v', 'a', 'e', 's', 'd', 'e', 'c', 9, 0, + /* 1802 */ 'x', 's', 'a', 'v', 'e', 'c', 9, 0, + /* 1810 */ 'v', 'a', 'e', 's', 'i', 'm', 'c', 9, 0, + /* 1819 */ 'v', 'a', 'e', 's', 'e', 'n', 'c', 9, 0, + /* 1828 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'd', 9, 0, + /* 1838 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'd', 9, 0, + /* 1848 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'd', 9, 0, + /* 1858 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'm', 'w', '2', 'd', 9, 0, + /* 1875 */ 'a', 'a', 'd', 9, 0, + /* 1880 */ 'v', 'p', 's', 'h', 'a', 'd', 9, 0, + /* 1888 */ 'v', 'p', 's', 'r', 'a', 'd', 9, 0, + /* 1896 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'd', 9, 0, + /* 1906 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'd', 9, 0, + /* 1917 */ 'v', 'p', 'h', 's', 'u', 'b', 'd', 9, 0, + /* 1926 */ 'v', 'p', 's', 'u', 'b', 'd', 9, 0, + /* 1934 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'd', 9, 0, + /* 1945 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'd', 9, 0, + /* 1956 */ 'p', 'f', 'a', 'd', 'd', 9, 0, + /* 1963 */ 'v', 'p', 'h', 'a', 'd', 'd', 'd', 9, 0, + /* 1972 */ 'k', 'a', 'd', 'd', 'd', 9, 0, + /* 1979 */ 'v', 'p', 'a', 'd', 'd', 'd', 9, 0, + /* 1987 */ 'v', 'p', 's', 'h', 'l', 'd', 'd', 9, 0, + /* 1996 */ 'k', 'a', 'n', 'd', 'd', 9, 0, + /* 2003 */ 'v', 'p', 'a', 'n', 'd', 'd', 9, 0, + /* 2011 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'd', 9, 0, + /* 2022 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'd', 9, 0, + /* 2032 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'd', 9, 0, + /* 2044 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'd', 9, 0, + /* 2057 */ 'v', 'p', 's', 'h', 'r', 'd', 'd', 9, 0, + /* 2066 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'd', 9, 0, + /* 2076 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'd', 9, 0, + /* 2087 */ 'p', 'i', '2', 'f', 'd', 9, 0, + /* 2094 */ 'v', 'p', 's', 'h', 'u', 'f', 'd', 9, 0, + /* 2103 */ 'v', 'p', 't', 'e', 'r', 'n', 'l', 'o', 'g', 'd', 9, 0, + /* 2115 */ 'p', 'f', '2', 'i', 'd', 9, 0, + /* 2122 */ 'i', 'n', 'v', 'p', 'c', 'i', 'd', 9, 0, + /* 2131 */ 'r', 'd', 'p', 'i', 'd', 9, 0, + /* 2138 */ 'i', 'n', 'v', 'v', 'p', 'i', 'd', 9, 0, + /* 2147 */ 'f', 'l', 'd', 9, 0, + /* 2152 */ 'v', 'p', 's', 'h', 'l', 'd', 9, 0, + /* 2160 */ 'v', 'p', 's', 'l', 'l', 'd', 9, 0, + /* 2168 */ 'v', 'p', 'm', 'u', 'l', 'l', 'd', 9, 0, + /* 2177 */ 'v', 'p', 'r', 'o', 'l', 'd', 9, 0, + /* 2185 */ 'v', 'p', 's', 'r', 'l', 'd', 9, 0, + /* 2193 */ 'v', 'm', 'p', 't', 'r', 'l', 'd', 9, 0, + /* 2202 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'd', 9, 0, + /* 2212 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'd', 9, 0, + /* 2223 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'd', 9, 0, + /* 2234 */ 'v', 'p', 'c', 'o', 'm', 'd', 9, 0, + /* 2242 */ 'v', 'p', 'e', 'r', 'm', 'd', 9, 0, + /* 2250 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'd', 9, 0, + /* 2260 */ 'v', 'p', 'a', 'n', 'd', 9, 0, + /* 2267 */ 'k', 'a', 'n', 'd', 'n', 'd', 9, 0, + /* 2275 */ 'v', 'p', 'a', 'n', 'd', 'n', 'd', 9, 0, + /* 2284 */ 'v', 'a', 'l', 'i', 'g', 'n', 'd', 9, 0, + /* 2293 */ 'v', 'p', 's', 'i', 'g', 'n', 'd', 9, 0, + /* 2302 */ 'b', 'o', 'u', 'n', 'd', 9, 0, + /* 2309 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, + /* 2325 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, + /* 2338 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, + /* 2352 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, + /* 2368 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, + /* 2381 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, + /* 2395 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, + /* 2411 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, + /* 2424 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, + /* 2438 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, + /* 2454 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, + /* 2467 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, + /* 2481 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'p', 'd', 9, 0, + /* 2492 */ 'c', 'v', 't', 'p', 'i', '2', 'p', 'd', 9, 0, + /* 2502 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', '2', 'p', 'd', 9, 0, + /* 2514 */ 'v', 'e', 'x', 'p', '2', 'p', 'd', 9, 0, + /* 2523 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 'd', 9, 0, + /* 2534 */ 'v', 'c', 'v', 't', 'u', 'd', 'q', '2', 'p', 'd', 9, 0, + /* 2546 */ 'v', 'c', 'v', 't', 'q', 'q', '2', 'p', 'd', 9, 0, + /* 2557 */ 'v', 'c', 'v', 't', 'u', 'q', 'q', '2', 'p', 'd', 9, 0, + /* 2569 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'd', 9, 0, + /* 2580 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'p', 'd', 9, 0, + /* 2591 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, + /* 2607 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, + /* 2620 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, + /* 2634 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, + /* 2650 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, + /* 2663 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, + /* 2677 */ 'v', 'r', 'c', 'p', '1', '4', 'p', 'd', 9, 0, + /* 2687 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 'p', 'd', 9, 0, + /* 2699 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 'd', 9, 0, + /* 2709 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 'd', 9, 0, + /* 2721 */ 'v', 'm', 'o', 'v', 'a', 'p', 'd', 9, 0, + /* 2730 */ 'p', 's', 'w', 'a', 'p', 'd', 9, 0, + /* 2738 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', 'p', 'd', 9, 0, + /* 2751 */ 'v', 'a', 'd', 'd', 's', 'u', 'b', 'p', 'd', 9, 0, + /* 2762 */ 'v', 'h', 's', 'u', 'b', 'p', 'd', 9, 0, + /* 2771 */ 'v', 'f', 'm', 's', 'u', 'b', 'p', 'd', 9, 0, + /* 2781 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 'p', 'd', 9, 0, + /* 2792 */ 'v', 's', 'u', 'b', 'p', 'd', 9, 0, + /* 2800 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'd', 'p', 'd', 9, 0, + /* 2815 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'd', 'p', 'd', 9, 0, + /* 2831 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'd', 'p', 'd', 9, 0, + /* 2846 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'd', 'p', 'd', 9, 0, + /* 2862 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', 'p', 'd', 9, 0, + /* 2875 */ 'v', 'h', 'a', 'd', 'd', 'p', 'd', 9, 0, + /* 2884 */ 'v', 'f', 'm', 'a', 'd', 'd', 'p', 'd', 9, 0, + /* 2894 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 'd', 9, 0, + /* 2905 */ 'v', 'a', 'd', 'd', 'p', 'd', 9, 0, + /* 2913 */ 'v', 'e', 'x', 'p', 'a', 'n', 'd', 'p', 'd', 9, 0, + /* 2924 */ 'v', 'a', 'n', 'd', 'p', 'd', 9, 0, + /* 2932 */ 'v', 'b', 'l', 'e', 'n', 'd', 'p', 'd', 9, 0, + /* 2942 */ 'v', 'r', 'o', 'u', 'n', 'd', 'p', 'd', 9, 0, + /* 2952 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 'd', 9, 0, + /* 2964 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'p', 'd', 9, 0, + /* 2977 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 'p', 'd', 9, 0, + /* 2988 */ 'v', 'r', 'a', 'n', 'g', 'e', 'p', 'd', 9, 0, + /* 2998 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 'p', 'd', 9, 0, + /* 3011 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 'p', 'd', 9, 0, + /* 3022 */ 'v', 's', 'h', 'u', 'f', 'p', 'd', 9, 0, + /* 3031 */ 'v', 'u', 'n', 'p', 'c', 'k', 'h', 'p', 'd', 9, 0, + /* 3042 */ 'v', 'm', 'o', 'v', 'h', 'p', 'd', 9, 0, + /* 3051 */ 'v', 'm', 'o', 'v', 'm', 's', 'k', 'p', 'd', 9, 0, + /* 3062 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 'd', 9, 0, + /* 3073 */ 'v', 'u', 'n', 'p', 'c', 'k', 'l', 'p', 'd', 9, 0, + /* 3084 */ 'v', 'm', 'u', 'l', 'p', 'd', 9, 0, + /* 3092 */ 'v', 'm', 'o', 'v', 'l', 'p', 'd', 9, 0, + /* 3101 */ 'v', 'p', 'c', 'm', 'p', 'd', 9, 0, + /* 3109 */ 'v', 'b', 'l', 'e', 'n', 'd', 'm', 'p', 'd', 9, 0, + /* 3120 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 'p', 'd', 9, 0, + /* 3133 */ 'v', 'p', 'e', 'r', 'm', 'p', 'd', 9, 0, + /* 3142 */ 'v', 'a', 'n', 'd', 'n', 'p', 'd', 9, 0, + /* 3151 */ 'v', 'm', 'i', 'n', 'p', 'd', 9, 0, + /* 3159 */ 'v', 'd', 'p', 'p', 'd', 9, 0, + /* 3166 */ 'v', 'c', 'm', 'p', 'p', 'd', 9, 0, + /* 3174 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 'p', 'd', 9, 0, + /* 3185 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'q', 'p', 'd', 9, 0, + /* 3200 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'q', 'p', 'd', 9, 0, + /* 3216 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'q', 'p', 'd', 9, 0, + /* 3231 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'q', 'p', 'd', 9, 0, + /* 3247 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 'd', 9, 0, + /* 3259 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'p', 'd', 9, 0, + /* 3272 */ 'v', 'o', 'r', 'p', 'd', 9, 0, + /* 3279 */ 'v', 'x', 'o', 'r', 'p', 'd', 9, 0, + /* 3287 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 'd', 9, 0, + /* 3299 */ 'i', 'n', 'c', 's', 's', 'p', 'd', 9, 0, + /* 3308 */ 'r', 'd', 's', 's', 'p', 'd', 9, 0, + /* 3316 */ 'v', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'p', 'd', 9, 0, + /* 3329 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 'p', 'd', 9, 0, + /* 3341 */ 'v', 'm', 'o', 'v', 'n', 't', 'p', 'd', 9, 0, + /* 3351 */ 'v', 's', 'q', 'r', 't', 'p', 'd', 9, 0, + /* 3360 */ 'v', 't', 'e', 's', 't', 'p', 'd', 9, 0, + /* 3369 */ 'v', 'm', 'o', 'v', 'u', 'p', 'd', 9, 0, + /* 3378 */ 'v', 'b', 'l', 'e', 'n', 'd', 'v', 'p', 'd', 9, 0, + /* 3389 */ 'v', 'd', 'i', 'v', 'p', 'd', 9, 0, + /* 3397 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'p', 'd', 9, 0, + /* 3409 */ 'v', 'm', 'a', 'x', 'p', 'd', 9, 0, + /* 3417 */ 'v', 'f', 'r', 'c', 'z', 'p', 'd', 9, 0, + /* 3426 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'd', 9, 0, + /* 3436 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'd', 9, 0, + /* 3448 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'd', 9, 0, + /* 3461 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'd', 9, 0, + /* 3472 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'd', 9, 0, + /* 3482 */ 'v', 'p', 'm', 'o', 'v', 'q', 'd', 9, 0, + /* 3491 */ 'k', 'o', 'r', 'd', 9, 0, + /* 3497 */ 'k', 'x', 'n', 'o', 'r', 'd', 9, 0, + /* 3505 */ 'v', 'p', 'o', 'r', 'd', 9, 0, + /* 3512 */ 'v', 'p', 'r', 'o', 'r', 'd', 9, 0, + /* 3520 */ 'k', 'x', 'o', 'r', 'd', 9, 0, + /* 3527 */ 'v', 'p', 'x', 'o', 'r', 'd', 9, 0, + /* 3535 */ 'v', 'p', 'i', 'n', 's', 'r', 'd', 9, 0, + /* 3544 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'd', 9, 0, + /* 3554 */ 'v', 'p', 'e', 'x', 't', 'r', 'd', 9, 0, + /* 3563 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 's', 'd', 9, 0, + /* 3576 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 's', 'd', 9, 0, + /* 3590 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 'd', 9, 0, + /* 3603 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 'd', 9, 0, + /* 3617 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 's', 'd', 9, 0, + /* 3630 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 's', 'd', 9, 0, + /* 3644 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 'd', 9, 0, + /* 3657 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 'd', 9, 0, + /* 3671 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'd', 9, 0, + /* 3682 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 9, 0, + /* 3695 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 9, 0, + /* 3709 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 9, 0, + /* 3722 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 9, 0, + /* 3736 */ 'v', 'r', 'c', 'p', '1', '4', 's', 'd', 9, 0, + /* 3746 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 's', 'd', 9, 0, + /* 3758 */ 'v', 'r', 'c', 'p', '2', '8', 's', 'd', 9, 0, + /* 3768 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 'd', 9, 0, + /* 3780 */ 'v', 'p', 'a', 'b', 's', 'd', 9, 0, + /* 3788 */ 'v', 'f', 'm', 's', 'u', 'b', 's', 'd', 9, 0, + /* 3798 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 'd', 9, 0, + /* 3809 */ 'v', 's', 'u', 'b', 's', 'd', 9, 0, + /* 3817 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'd', 9, 0, + /* 3827 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 'd', 9, 0, + /* 3838 */ 'v', 'a', 'd', 'd', 's', 'd', 9, 0, + /* 3846 */ 'v', 'r', 'o', 'u', 'n', 'd', 's', 'd', 9, 0, + /* 3856 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 's', 'd', 9, 0, + /* 3867 */ 'v', 'r', 'a', 'n', 'g', 'e', 's', 'd', 9, 0, + /* 3877 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 's', 'd', 9, 0, + /* 3890 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 's', 'd', 9, 0, + /* 3901 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 'd', 9, 0, + /* 3911 */ 'v', 'c', 'o', 'm', 'i', 's', 'd', 9, 0, + /* 3920 */ 'v', 'm', 'u', 'l', 's', 'd', 9, 0, + /* 3928 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 's', 'd', 9, 0, + /* 3941 */ 'v', 'p', 'm', 'i', 'n', 's', 'd', 9, 0, + /* 3950 */ 'v', 'm', 'i', 'n', 's', 'd', 9, 0, + /* 3958 */ 'v', 'c', 'm', 'p', 's', 'd', 9, 0, + /* 3966 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 's', 'd', 9, 0, + /* 3977 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'd', 9, 0, + /* 3990 */ 'w', 'r', 's', 's', 'd', 9, 0, + /* 3997 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 's', 'd', 9, 0, + /* 4009 */ 'w', 'r', 'u', 's', 's', 'd', 9, 0, + /* 4017 */ 'v', 'p', '4', 'd', 'p', 'w', 's', 's', 'd', 9, 0, + /* 4028 */ 'v', 'p', 'd', 'p', 'w', 's', 's', 'd', 9, 0, + /* 4038 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 's', 'd', 9, 0, + /* 4050 */ 'm', 'o', 'v', 'n', 't', 's', 'd', 9, 0, + /* 4059 */ 'v', 's', 'q', 'r', 't', 's', 'd', 9, 0, + /* 4068 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 'd', 9, 0, + /* 4082 */ 'v', 'p', 'd', 'p', 'b', 'u', 's', 'd', 9, 0, + /* 4092 */ 'v', 'd', 'i', 'v', 's', 'd', 9, 0, + /* 4100 */ 'v', 'm', 'o', 'v', 's', 'd', 9, 0, + /* 4108 */ 'v', 'p', 'm', 'a', 'x', 's', 'd', 9, 0, + /* 4117 */ 'v', 'm', 'a', 'x', 's', 'd', 9, 0, + /* 4125 */ 'v', 'f', 'r', 'c', 'z', 's', 'd', 9, 0, + /* 4134 */ 'v', 'p', 'c', 'o', 'n', 'f', 'l', 'i', 'c', 't', 'd', 9, 0, + /* 4147 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'd', 9, 0, + /* 4157 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'd', 9, 0, + /* 4167 */ 'v', 'p', 'l', 'z', 'c', 'n', 't', 'd', 9, 0, + /* 4177 */ 'k', 'n', 'o', 't', 'd', 9, 0, + /* 4184 */ 'v', 'p', 'r', 'o', 't', 'd', 9, 0, + /* 4192 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'd', 9, 0, + /* 4206 */ 'k', 't', 'e', 's', 't', 'd', 9, 0, + /* 4214 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'd', 9, 0, + /* 4224 */ 'v', 'p', 'c', 'o', 'm', 'u', 'd', 9, 0, + /* 4233 */ 'v', 'p', 'm', 'i', 'n', 'u', 'd', 9, 0, + /* 4242 */ 'v', 'p', 'c', 'm', 'p', 'u', 'd', 9, 0, + /* 4251 */ 'v', 'p', 'm', 'a', 'x', 'u', 'd', 9, 0, + /* 4260 */ 'v', 'p', 's', 'r', 'a', 'v', 'd', 9, 0, + /* 4269 */ 'v', 'p', 's', 'h', 'l', 'd', 'v', 'd', 9, 0, + /* 4279 */ 'v', 'p', 's', 'h', 'r', 'd', 'v', 'd', 9, 0, + /* 4289 */ 'v', 'p', 's', 'l', 'l', 'v', 'd', 9, 0, + /* 4298 */ 'v', 'p', 'r', 'o', 'l', 'v', 'd', 9, 0, + /* 4307 */ 'v', 'p', 's', 'r', 'l', 'v', 'd', 9, 0, + /* 4316 */ 'v', 'p', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'd', 9, 0, + /* 4328 */ 'v', 'm', 'o', 'v', 'd', 9, 0, + /* 4335 */ 'v', 'p', 'r', 'o', 'r', 'v', 'd', 9, 0, + /* 4344 */ 'v', 'p', 'h', 's', 'u', 'b', 'w', 'd', 9, 0, + /* 4354 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 'd', 9, 0, + /* 4364 */ 'v', 'p', 'm', 'a', 'd', 'd', 'w', 'd', 9, 0, + /* 4374 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'w', 'd', 9, 0, + /* 4386 */ 'k', 'u', 'n', 'p', 'c', 'k', 'w', 'd', 9, 0, + /* 4396 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'w', 'd', 9, 0, + /* 4408 */ 'v', 'p', 'm', 'a', 'c', 's', 'w', 'd', 9, 0, + /* 4418 */ 'v', 'p', 'm', 'a', 'd', 'c', 's', 'w', 'd', 9, 0, + /* 4429 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'w', 'd', 9, 0, + /* 4440 */ 'v', 'p', 'm', 'a', 'd', 'c', 's', 's', 'w', 'd', 9, 0, + /* 4452 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'w', 'd', 9, 0, + /* 4463 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'd', 9, 0, + /* 4474 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'd', 9, 0, + /* 4485 */ 'j', 'a', 'e', 9, 0, + /* 4490 */ 's', 'e', 't', 'a', 'e', 9, 0, + /* 4497 */ 'j', 'b', 'e', 9, 0, + /* 4502 */ 'f', 'c', 'm', 'o', 'v', 'n', 'b', 'e', 9, 0, + /* 4512 */ 's', 'e', 't', 'b', 'e', 9, 0, + /* 4519 */ 'f', 'c', 'm', 'o', 'v', 'b', 'e', 9, 0, + /* 4528 */ 'f', 'f', 'r', 'e', 'e', 9, 0, + /* 4535 */ 'j', 'g', 'e', 9, 0, + /* 4540 */ 'p', 'f', 'c', 'm', 'p', 'g', 'e', 9, 0, + /* 4549 */ 's', 'e', 't', 'g', 'e', 9, 0, + /* 4556 */ 'j', 'e', 9, 0, + /* 4560 */ 'j', 'l', 'e', 9, 0, + /* 4565 */ 's', 'e', 't', 'l', 'e', 9, 0, + /* 4572 */ 'j', 'n', 'e', 9, 0, + /* 4577 */ 'l', 'o', 'o', 'p', 'n', 'e', 9, 0, + /* 4585 */ 's', 'e', 't', 'n', 'e', 9, 0, + /* 4592 */ 'f', 'c', 'm', 'o', 'v', 'n', 'e', 9, 0, + /* 4601 */ 'l', 'o', 'o', 'p', 'e', 9, 0, + /* 4608 */ 't', 'p', 'a', 'u', 's', 'e', 9, 0, + /* 4616 */ 's', 'e', 't', 'e', 9, 0, + /* 4622 */ 'c', 'l', 'd', 'e', 'm', 'o', 't', 'e', 9, 0, + /* 4632 */ 's', 'h', 'a', '1', 'n', 'e', 'x', 't', 'e', 9, 0, + /* 4643 */ 'f', 'n', 's', 'a', 'v', 'e', 9, 0, + /* 4651 */ 'f', 'x', 's', 'a', 'v', 'e', 9, 0, + /* 4659 */ 'f', 'c', 'm', 'o', 'v', 'e', 9, 0, + /* 4667 */ 'j', 'g', 9, 0, + /* 4671 */ 'i', 'n', 'v', 'l', 'p', 'g', 9, 0, + /* 4679 */ 's', 'e', 't', 'g', 9, 0, + /* 4685 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 9, 0, + /* 4695 */ 'f', 'x', 'c', 'h', 9, 0, + /* 4701 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'h', 9, 0, + /* 4712 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'q', 'h', 9, 0, + /* 4723 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'q', 'h', 9, 0, + /* 4735 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 9, 0, + /* 4744 */ 'f', 'c', 'o', 'm', 'i', 9, 0, + /* 4751 */ 'f', 'u', 'c', 'o', 'm', 'i', 9, 0, + /* 4759 */ 'c', 'v', 't', 't', 'p', 'd', '2', 'p', 'i', 9, 0, + /* 4770 */ 'c', 'v', 't', 'p', 'd', '2', 'p', 'i', 9, 0, + /* 4780 */ 'c', 'v', 't', 't', 'p', 's', '2', 'p', 'i', 9, 0, + /* 4791 */ 'c', 'v', 't', 'p', 's', '2', 'p', 'i', 9, 0, + /* 4801 */ 'f', 'c', 'o', 'm', 'p', 'i', 9, 0, + /* 4809 */ 'f', 'u', 'c', 'o', 'm', 'p', 'i', 9, 0, + /* 4818 */ 'm', 'o', 'v', 'd', 'i', 'r', 'i', 9, 0, + /* 4827 */ 'v', 'p', 'c', 'm', 'p', 'e', 's', 't', 'r', 'i', 9, 0, + /* 4839 */ 'v', 'p', 'c', 'm', 'p', 'i', 's', 't', 'r', 'i', 9, 0, + /* 4851 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 's', 'i', 9, 0, + /* 4863 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 'i', 9, 0, + /* 4874 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 's', 'i', 9, 0, + /* 4886 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'i', 9, 0, + /* 4897 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 'u', 's', 'i', 9, 0, + /* 4910 */ 'v', 'c', 'v', 't', 's', 'd', '2', 'u', 's', 'i', 9, 0, + /* 4922 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 'u', 's', 'i', 9, 0, + /* 4935 */ 'v', 'c', 'v', 't', 's', 's', '2', 'u', 's', 'i', 9, 0, + /* 4947 */ 'b', 'n', 'd', 'm', 'k', 9, 0, + /* 4954 */ 'c', 'r', 'c', '3', '2', 'l', 9, 0, + /* 4962 */ 'l', 'e', 'a', 'l', 9, 0, + /* 4968 */ 'c', 'm', 'o', 'v', 'a', 'l', 9, 0, + /* 4976 */ 'l', 'w', 'p', 'v', 'a', 'l', 9, 0, + /* 4984 */ 's', 'b', 'b', 'l', 9, 0, + /* 4990 */ 'm', 'o', 'v', 's', 'b', 'l', 9, 0, + /* 4998 */ 'f', 's', 'u', 'b', 'l', 9, 0, + /* 5005 */ 'f', 'i', 's', 'u', 'b', 'l', 9, 0, + /* 5013 */ 'c', 'm', 'o', 'v', 'b', 'l', 9, 0, + /* 5021 */ 'm', 'o', 'v', 'z', 'b', 'l', 9, 0, + /* 5029 */ 'a', 'd', 'c', 'l', 9, 0, + /* 5035 */ 'b', 'n', 'd', 'c', 'l', 9, 0, + /* 5042 */ 'd', 'e', 'c', 'l', 9, 0, + /* 5048 */ 'b', 'l', 'c', 'i', 'c', 'l', 9, 0, + /* 5056 */ 'b', 'l', 's', 'i', 'c', 'l', 9, 0, + /* 5064 */ 't', '1', 'm', 's', 'k', 'c', 'l', 9, 0, + /* 5073 */ 'i', 'n', 'c', 'l', 9, 0, + /* 5079 */ 'b', 't', 'c', 'l', 9, 0, + /* 5085 */ 'v', 'm', 'r', 'e', 'a', 'd', 'l', 9, 0, + /* 5094 */ 'f', 'a', 'd', 'd', 'l', 9, 0, + /* 5101 */ 'f', 'i', 'a', 'd', 'd', 'l', 9, 0, + /* 5109 */ 'x', 'a', 'd', 'd', 'l', 9, 0, + /* 5116 */ 'r', 'd', 's', 'e', 'e', 'd', 'l', 9, 0, + /* 5125 */ 'f', 'l', 'd', 'l', 9, 0, + /* 5131 */ 's', 'h', 'l', 'd', 'l', 9, 0, + /* 5138 */ 'f', 'i', 'l', 'd', 'l', 9, 0, + /* 5145 */ 'r', 'd', 'r', 'a', 'n', 'd', 'l', 9, 0, + /* 5154 */ 's', 'h', 'r', 'd', 'l', 9, 0, + /* 5161 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 'd', 'l', 9, 0, + /* 5173 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 'd', 'l', 9, 0, + /* 5186 */ 'c', 'm', 'o', 'v', 'a', 'e', 'l', 9, 0, + /* 5195 */ 'c', 'm', 'o', 'v', 'b', 'e', 'l', 9, 0, + /* 5204 */ 'c', 'm', 'o', 'v', 'g', 'e', 'l', 9, 0, + /* 5213 */ 'c', 'm', 'o', 'v', 'l', 'e', 'l', 9, 0, + /* 5222 */ 'c', 'm', 'o', 'v', 'n', 'e', 'l', 9, 0, + /* 5231 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 'l', 9, 0, + /* 5242 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 'l', 9, 0, + /* 5253 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 'l', 9, 0, + /* 5264 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 'l', 9, 0, + /* 5275 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 'l', 9, 0, + /* 5285 */ 'p', 't', 'w', 'r', 'i', 't', 'e', 'l', 9, 0, + /* 5295 */ 'c', 'm', 'o', 'v', 'e', 'l', 9, 0, + /* 5303 */ 'b', 's', 'f', 'l', 9, 0, + /* 5309 */ 'n', 'e', 'g', 'l', 9, 0, + /* 5315 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'l', 9, 0, + /* 5325 */ 'c', 'm', 'o', 'v', 'g', 'l', 9, 0, + /* 5333 */ 'p', 'u', 's', 'h', 'l', 9, 0, + /* 5340 */ 'b', 'l', 'c', 'i', 'l', 9, 0, + /* 5347 */ 'b', 'z', 'h', 'i', 'l', 9, 0, + /* 5354 */ 'b', 'l', 's', 'i', 'l', 9, 0, + /* 5361 */ 'm', 'o', 'v', 'n', 't', 'i', 'l', 9, 0, + /* 5370 */ 'j', 'l', 9, 0, + /* 5374 */ 'b', 'l', 'c', 'm', 's', 'k', 'l', 9, 0, + /* 5383 */ 'b', 'l', 's', 'm', 's', 'k', 'l', 9, 0, + /* 5392 */ 't', 'z', 'm', 's', 'k', 'l', 9, 0, + /* 5400 */ 's', 'a', 'l', 'l', 9, 0, + /* 5406 */ 'r', 'c', 'l', 'l', 9, 0, + /* 5412 */ 'f', 'i', 'l', 'd', 'l', 'l', 9, 0, + /* 5420 */ 's', 'h', 'l', 'l', 9, 0, + /* 5426 */ 'l', 'c', 'a', 'l', 'l', 'l', 9, 0, + /* 5434 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 'l', 9, 0, + /* 5444 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 'l', 9, 0, + /* 5454 */ 'r', 'o', 'l', 'l', 9, 0, + /* 5460 */ 'f', 'i', 's', 't', 'p', 'l', 'l', 9, 0, + /* 5469 */ 'f', 'i', 's', 't', 't', 'p', 'l', 'l', 9, 0, + /* 5479 */ 'l', 's', 'l', 'l', 9, 0, + /* 5485 */ 'f', 'm', 'u', 'l', 'l', 9, 0, + /* 5492 */ 'f', 'i', 'm', 'u', 'l', 'l', 9, 0, + /* 5500 */ 'c', 'm', 'o', 'v', 'l', 'l', 9, 0, + /* 5508 */ 'f', 'c', 'o', 'm', 'l', 9, 0, + /* 5515 */ 'f', 'i', 'c', 'o', 'm', 'l', 9, 0, + /* 5523 */ 'a', 'n', 'd', 'n', 'l', 9, 0, + /* 5530 */ 'i', 'n', 'l', 9, 0, + /* 5535 */ 'c', 'm', 'o', 'v', 'n', 'o', 'l', 9, 0, + /* 5544 */ 'c', 'm', 'o', 'v', 'o', 'l', 9, 0, + /* 5552 */ 'b', 's', 'w', 'a', 'p', 'l', 9, 0, + /* 5560 */ 'p', 'd', 'e', 'p', 'l', 9, 0, + /* 5567 */ 'c', 'm', 'p', 'l', 9, 0, + /* 5573 */ 'l', 'j', 'm', 'p', 'l', 9, 0, + /* 5580 */ 'f', 'c', 'o', 'm', 'p', 'l', 9, 0, + /* 5588 */ 'f', 'i', 'c', 'o', 'm', 'p', 'l', 9, 0, + /* 5597 */ 'c', 'm', 'o', 'v', 'n', 'p', 'l', 9, 0, + /* 5606 */ 'n', 'o', 'p', 'l', 9, 0, + /* 5612 */ 'p', 'o', 'p', 'l', 9, 0, + /* 5618 */ 'a', 'r', 'p', 'l', 9, 0, + /* 5624 */ 'f', 's', 't', 'p', 'l', 9, 0, + /* 5631 */ 'f', 'i', 's', 't', 'p', 'l', 9, 0, + /* 5639 */ 'f', 'i', 's', 't', 't', 'p', 'l', 9, 0, + /* 5648 */ 'c', 'm', 'o', 'v', 'p', 'l', 9, 0, + /* 5656 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'q', 'l', 9, 0, + /* 5667 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'q', 'l', 9, 0, + /* 5679 */ 'l', 'a', 'r', 'l', 9, 0, + /* 5685 */ 's', 'a', 'r', 'l', 9, 0, + /* 5691 */ 'f', 's', 'u', 'b', 'r', 'l', 9, 0, + /* 5699 */ 'f', 'i', 's', 'u', 'b', 'r', 'l', 9, 0, + /* 5708 */ 'r', 'c', 'r', 'l', 9, 0, + /* 5714 */ 's', 'h', 'r', 'l', 9, 0, + /* 5720 */ 'r', 'o', 'r', 'l', 9, 0, + /* 5726 */ 'x', 'o', 'r', 'l', 9, 0, + /* 5732 */ 'b', 's', 'r', 'l', 9, 0, + /* 5738 */ 'b', 'l', 's', 'r', 'l', 9, 0, + /* 5745 */ 'b', 't', 'r', 'l', 9, 0, + /* 5751 */ 's', 't', 'r', 'l', 9, 0, + /* 5757 */ 'b', 'e', 'x', 't', 'r', 'l', 9, 0, + /* 5765 */ 'f', 'd', 'i', 'v', 'r', 'l', 9, 0, + /* 5773 */ 'f', 'i', 'd', 'i', 'v', 'r', 'l', 9, 0, + /* 5782 */ 's', 'c', 'a', 's', 'l', 9, 0, + /* 5789 */ 'm', 'o', 'v', 'a', 'b', 's', 'l', 9, 0, + /* 5798 */ 'b', 'l', 'c', 's', 'l', 9, 0, + /* 5805 */ 'l', 'd', 's', 'l', 9, 0, + /* 5811 */ 'l', 'o', 'd', 's', 'l', 9, 0, + /* 5818 */ 'l', 'e', 's', 'l', 9, 0, + /* 5824 */ 'l', 'f', 's', 'l', 9, 0, + /* 5830 */ 'l', 'g', 's', 'l', 9, 0, + /* 5836 */ 'c', 'm', 'o', 'v', 'n', 's', 'l', 9, 0, + /* 5845 */ 'c', 'm', 'p', 's', 'l', 9, 0, + /* 5852 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 's', 'l', 9, 0, + /* 5865 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 's', 'l', 9, 0, + /* 5877 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 's', 'l', 9, 0, + /* 5890 */ 'l', 's', 's', 'l', 9, 0, + /* 5896 */ 'b', 't', 's', 'l', 9, 0, + /* 5902 */ 'o', 'u', 't', 's', 'l', 9, 0, + /* 5909 */ 'c', 'm', 'o', 'v', 's', 'l', 9, 0, + /* 5917 */ 'b', 't', 'l', 9, 0, + /* 5922 */ 'l', 'g', 'd', 't', 'l', 9, 0, + /* 5929 */ 's', 'g', 'd', 't', 'l', 9, 0, + /* 5936 */ 'l', 'i', 'd', 't', 'l', 9, 0, + /* 5943 */ 's', 'i', 'd', 't', 'l', 9, 0, + /* 5950 */ 's', 'l', 'd', 't', 'l', 9, 0, + /* 5957 */ 'l', 'r', 'e', 't', 'l', 9, 0, + /* 5964 */ 's', 'e', 't', 'l', 9, 0, + /* 5970 */ 'p', 'o', 'p', 'c', 'n', 't', 'l', 9, 0, + /* 5979 */ 'l', 'z', 'c', 'n', 't', 'l', 9, 0, + /* 5987 */ 't', 'z', 'c', 'n', 't', 'l', 9, 0, + /* 5995 */ 'n', 'o', 't', 'l', 9, 0, + /* 6001 */ 't', 'e', 's', 't', 'l', 9, 0, + /* 6008 */ 'f', 's', 't', 'l', 9, 0, + /* 6014 */ 'f', 'i', 's', 't', 'l', 9, 0, + /* 6021 */ 'p', 'e', 'x', 't', 'l', 9, 0, + /* 6028 */ 'p', 'f', 'm', 'u', 'l', 9, 0, + /* 6035 */ 'f', 'd', 'i', 'v', 'l', 9, 0, + /* 6042 */ 'f', 'i', 'd', 'i', 'v', 'l', 9, 0, + /* 6050 */ 'm', 'o', 'v', 'l', 9, 0, + /* 6056 */ 's', 'm', 's', 'w', 'l', 9, 0, + /* 6063 */ 'm', 'o', 'v', 's', 'w', 'l', 9, 0, + /* 6071 */ 'm', 'o', 'v', 'z', 'w', 'l', 9, 0, + /* 6079 */ 'a', 'd', 'c', 'x', 'l', 9, 0, + /* 6086 */ 's', 'h', 'l', 'x', 'l', 9, 0, + /* 6093 */ 'm', 'u', 'l', 'x', 'l', 9, 0, + /* 6100 */ 'a', 'd', 'o', 'x', 'l', 9, 0, + /* 6107 */ 's', 'a', 'r', 'x', 'l', 9, 0, + /* 6114 */ 's', 'h', 'r', 'x', 'l', 9, 0, + /* 6121 */ 'r', 'o', 'r', 'x', 'l', 9, 0, + /* 6128 */ 'v', 'p', 'm', 'o', 'v', 'b', '2', 'm', 9, 0, + /* 6138 */ 'v', 'p', 'm', 'o', 'v', 'd', '2', 'm', 9, 0, + /* 6148 */ 'v', 'p', 'm', 'o', 'v', 'q', '2', 'm', 9, 0, + /* 6158 */ 'v', 'p', 'm', 'o', 'v', 'w', '2', 'm', 9, 0, + /* 6168 */ 'a', 'a', 'm', 9, 0, + /* 6173 */ 'f', 'c', 'o', 'm', 9, 0, + /* 6179 */ 'f', 'u', 'c', 'o', 'm', 9, 0, + /* 6186 */ 'v', 'p', 'p', 'e', 'r', 'm', 9, 0, + /* 6194 */ 'v', 'p', 'c', 'm', 'p', 'e', 's', 't', 'r', 'm', 9, 0, + /* 6206 */ 'v', 'p', 'c', 'm', 'p', 'i', 's', 't', 'r', 'm', 9, 0, + /* 6218 */ 'b', 'n', 'd', 'c', 'n', 9, 0, + /* 6225 */ 'v', 'p', 'a', 'n', 'd', 'n', 9, 0, + /* 6233 */ 'x', 'b', 'e', 'g', 'i', 'n', 9, 0, + /* 6241 */ 'p', 'f', 'm', 'i', 'n', 9, 0, + /* 6248 */ 'v', 'm', 'x', 'o', 'n', 9, 0, + /* 6255 */ 'j', 'o', 9, 0, + /* 6259 */ 'j', 'n', 'o', 9, 0, + /* 6264 */ 's', 'e', 't', 'n', 'o', 9, 0, + /* 6271 */ 's', 'e', 't', 'o', 9, 0, + /* 6277 */ 'f', 's', 'u', 'b', 'p', 9, 0, + /* 6284 */ 'p', 'f', 'r', 'c', 'p', 9, 0, + /* 6291 */ 'f', 'a', 'd', 'd', 'p', 9, 0, + /* 6298 */ 'f', 'f', 'r', 'e', 'e', 'p', 9, 0, + /* 6306 */ 'j', 'p', 9, 0, + /* 6310 */ 'f', 'm', 'u', 'l', 'p', 9, 0, + /* 6317 */ 'j', 'm', 'p', 9, 0, + /* 6322 */ 'f', 'c', 'o', 'm', 'p', 9, 0, + /* 6329 */ 'f', 'u', 'c', 'o', 'm', 'p', 9, 0, + /* 6337 */ 'j', 'n', 'p', 9, 0, + /* 6342 */ 's', 'e', 't', 'n', 'p', 9, 0, + /* 6349 */ 'n', 'o', 'p', 9, 0, + /* 6354 */ 'l', 'o', 'o', 'p', 9, 0, + /* 6360 */ 'f', 's', 'u', 'b', 'r', 'p', 9, 0, + /* 6368 */ 'f', 'd', 'i', 'v', 'r', 'p', 9, 0, + /* 6376 */ 'r', 's', 't', 'o', 'r', 's', 's', 'p', 9, 0, + /* 6386 */ 's', 'e', 't', 'p', 9, 0, + /* 6392 */ 'f', 's', 't', 'p', 9, 0, + /* 6398 */ 'v', 'm', 'o', 'v', 'd', 'd', 'u', 'p', 9, 0, + /* 6408 */ 'v', 'm', 'o', 'v', 's', 'h', 'd', 'u', 'p', 9, 0, + /* 6419 */ 'v', 'm', 'o', 'v', 's', 'l', 'd', 'u', 'p', 9, 0, + /* 6430 */ 'f', 'd', 'i', 'v', 'p', 9, 0, + /* 6437 */ 'c', 'r', 'c', '3', '2', 'q', 9, 0, + /* 6445 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'm', 'b', '2', 'q', 9, 0, + /* 6462 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'q', 9, 0, + /* 6472 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'q', 9, 0, + /* 6482 */ 'm', 'o', 'v', 'd', 'q', '2', 'q', 9, 0, + /* 6491 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'q', 9, 0, + /* 6501 */ 'l', 'e', 'a', 'q', 9, 0, + /* 6507 */ 'v', 'p', 's', 'h', 'a', 'q', 9, 0, + /* 6515 */ 'v', 'p', 's', 'r', 'a', 'q', 9, 0, + /* 6523 */ 'c', 'm', 'o', 'v', 'a', 'q', 9, 0, + /* 6531 */ 's', 'b', 'b', 'q', 9, 0, + /* 6537 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'q', 9, 0, + /* 6547 */ 'm', 'o', 'v', 's', 'b', 'q', 9, 0, + /* 6555 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'q', 9, 0, + /* 6566 */ 'v', 'p', 's', 'u', 'b', 'q', 9, 0, + /* 6574 */ 'c', 'm', 'o', 'v', 'b', 'q', 9, 0, + /* 6582 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'q', 9, 0, + /* 6593 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'q', 9, 0, + /* 6604 */ 'm', 'o', 'v', 'z', 'b', 'q', 9, 0, + /* 6612 */ 'a', 'd', 'c', 'q', 9, 0, + /* 6618 */ 'd', 'e', 'c', 'q', 9, 0, + /* 6624 */ 'b', 'l', 'c', 'i', 'c', 'q', 9, 0, + /* 6632 */ 'b', 'l', 's', 'i', 'c', 'q', 9, 0, + /* 6640 */ 't', '1', 'm', 's', 'k', 'c', 'q', 9, 0, + /* 6649 */ 'i', 'n', 'c', 'q', 9, 0, + /* 6655 */ 'b', 't', 'c', 'q', 9, 0, + /* 6661 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 9, 0, + /* 6673 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 9, 0, + /* 6684 */ 'm', 'o', 'v', 'q', '2', 'd', 'q', 9, 0, + /* 6693 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'd', 'q', 9, 0, + /* 6705 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'd', 'q', 9, 0, + /* 6716 */ 'v', 'm', 'r', 'e', 'a', 'd', 'q', 9, 0, + /* 6725 */ 'v', 'p', 'h', 's', 'u', 'b', 'd', 'q', 9, 0, + /* 6735 */ 'k', 'a', 'd', 'd', 'q', 9, 0, + /* 6742 */ 'v', 'p', 'a', 'd', 'd', 'q', 9, 0, + /* 6750 */ 'x', 'a', 'd', 'd', 'q', 9, 0, + /* 6757 */ 'v', 'p', 'h', 'a', 'd', 'd', 'd', 'q', 9, 0, + /* 6767 */ 'r', 'd', 's', 'e', 'e', 'd', 'q', 9, 0, + /* 6776 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'd', 'q', 9, 0, + /* 6788 */ 'k', 'u', 'n', 'p', 'c', 'k', 'd', 'q', 9, 0, + /* 6798 */ 'v', 'p', 's', 'h', 'l', 'd', 'q', 9, 0, + /* 6807 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'd', 'q', 9, 0, + /* 6819 */ 'v', 'p', 's', 'l', 'l', 'd', 'q', 9, 0, + /* 6828 */ 'v', 'p', 's', 'r', 'l', 'd', 'q', 9, 0, + /* 6837 */ 'v', 'p', 'm', 'u', 'l', 'd', 'q', 9, 0, + /* 6846 */ 'k', 'a', 'n', 'd', 'q', 9, 0, + /* 6853 */ 'v', 'p', 'a', 'n', 'd', 'q', 9, 0, + /* 6861 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'q', 9, 0, + /* 6872 */ 'r', 'd', 'r', 'a', 'n', 'd', 'q', 9, 0, + /* 6881 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 'd', 'q', 9, 0, + /* 6894 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'q', 'd', 'q', 9, 0, + /* 6907 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'q', 'd', 'q', 9, 0, + /* 6920 */ 'v', 'p', 'c', 'l', 'm', 'u', 'l', 'q', 'd', 'q', 9, 0, + /* 6932 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'q', 9, 0, + /* 6944 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'q', 9, 0, + /* 6957 */ 'v', 'p', 's', 'h', 'r', 'd', 'q', 9, 0, + /* 6966 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 'd', 'q', 9, 0, + /* 6978 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 'd', 'q', 9, 0, + /* 6991 */ 'v', 'm', 'o', 'v', 'n', 't', 'd', 'q', 9, 0, + /* 7001 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'd', 'q', 9, 0, + /* 7014 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'u', 'd', 'q', 9, 0, + /* 7026 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'u', 'd', 'q', 9, 0, + /* 7039 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'u', 'd', 'q', 9, 0, + /* 7051 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'd', 'q', 9, 0, + /* 7062 */ 'v', 'p', 'm', 'u', 'l', 'u', 'd', 'q', 9, 0, + /* 7072 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'd', 'q', 9, 0, + /* 7083 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'd', 'q', 9, 0, + /* 7094 */ 'c', 'm', 'o', 'v', 'a', 'e', 'q', 9, 0, + /* 7103 */ 'c', 'm', 'o', 'v', 'b', 'e', 'q', 9, 0, + /* 7112 */ 'c', 'm', 'o', 'v', 'g', 'e', 'q', 9, 0, + /* 7121 */ 'c', 'm', 'o', 'v', 'l', 'e', 'q', 9, 0, + /* 7130 */ 'c', 'm', 'o', 'v', 'n', 'e', 'q', 9, 0, + /* 7139 */ 'p', 'f', 'c', 'm', 'p', 'e', 'q', 9, 0, + /* 7148 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 'q', 9, 0, + /* 7159 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 'q', 9, 0, + /* 7170 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 'q', 9, 0, + /* 7181 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 'q', 9, 0, + /* 7192 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 'q', 9, 0, + /* 7202 */ 'p', 't', 'w', 'r', 'i', 't', 'e', 'q', 9, 0, + /* 7212 */ 'c', 'm', 'o', 'v', 'e', 'q', 9, 0, + /* 7220 */ 'b', 's', 'f', 'q', 9, 0, + /* 7226 */ 'n', 'e', 'g', 'q', 9, 0, + /* 7232 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'q', 9, 0, + /* 7242 */ 'v', 'p', 't', 'e', 'r', 'n', 'l', 'o', 'g', 'q', 9, 0, + /* 7254 */ 'c', 'm', 'o', 'v', 'g', 'q', 9, 0, + /* 7262 */ 'p', 'u', 's', 'h', 'q', 9, 0, + /* 7269 */ 'b', 'l', 'c', 'i', 'q', 9, 0, + /* 7276 */ 'b', 'z', 'h', 'i', 'q', 9, 0, + /* 7283 */ 'b', 'l', 's', 'i', 'q', 9, 0, + /* 7290 */ 'm', 'o', 'v', 'n', 't', 'i', 'q', 9, 0, + /* 7299 */ 'b', 'l', 'c', 'm', 's', 'k', 'q', 9, 0, + /* 7308 */ 'b', 'l', 's', 'm', 's', 'k', 'q', 9, 0, + /* 7317 */ 't', 'z', 'm', 's', 'k', 'q', 9, 0, + /* 7325 */ 's', 'a', 'l', 'q', 9, 0, + /* 7331 */ 'r', 'c', 'l', 'q', 9, 0, + /* 7337 */ 'v', 'p', 's', 'h', 'l', 'q', 9, 0, + /* 7345 */ 'c', 'a', 'l', 'l', 'q', 9, 0, + /* 7352 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 'q', 9, 0, + /* 7362 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 'q', 9, 0, + /* 7372 */ 'v', 'p', 's', 'l', 'l', 'q', 9, 0, + /* 7380 */ 'v', 'p', 'm', 'u', 'l', 'l', 'q', 9, 0, + /* 7389 */ 'v', 'p', 'r', 'o', 'l', 'q', 9, 0, + /* 7397 */ 'v', 'p', 's', 'r', 'l', 'q', 9, 0, + /* 7405 */ 'l', 's', 'l', 'q', 9, 0, + /* 7411 */ 'm', 'o', 'v', 's', 'l', 'q', 9, 0, + /* 7419 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'q', 9, 0, + /* 7429 */ 'i', 'm', 'u', 'l', 'q', 9, 0, + /* 7436 */ 'c', 'm', 'o', 'v', 'l', 'q', 9, 0, + /* 7444 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'q', 9, 0, + /* 7455 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'q', 9, 0, + /* 7466 */ 'v', 'p', 'c', 'o', 'm', 'q', 9, 0, + /* 7474 */ 'v', 'p', 'e', 'r', 'm', 'q', 9, 0, + /* 7482 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'q', 9, 0, + /* 7492 */ 'k', 'a', 'n', 'd', 'n', 'q', 9, 0, + /* 7500 */ 'v', 'p', 'a', 'n', 'd', 'n', 'q', 9, 0, + /* 7509 */ 'v', 'a', 'l', 'i', 'g', 'n', 'q', 9, 0, + /* 7518 */ 'c', 'm', 'o', 'v', 'n', 'o', 'q', 9, 0, + /* 7527 */ 'c', 'm', 'o', 'v', 'o', 'q', 9, 0, + /* 7535 */ 'b', 's', 'w', 'a', 'p', 'q', 9, 0, + /* 7543 */ 'p', 'd', 'e', 'p', 'q', 9, 0, + /* 7550 */ 'v', 'p', 'c', 'm', 'p', 'q', 9, 0, + /* 7558 */ 'c', 'm', 'o', 'v', 'n', 'p', 'q', 9, 0, + /* 7567 */ 'n', 'o', 'p', 'q', 9, 0, + /* 7573 */ 'p', 'o', 'p', 'q', 9, 0, + /* 7579 */ 'i', 'n', 'c', 's', 's', 'p', 'q', 9, 0, + /* 7588 */ 'r', 'd', 's', 's', 'p', 'q', 9, 0, + /* 7596 */ 'c', 'm', 'o', 'v', 'p', 'q', 9, 0, + /* 7604 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'q', 'q', 9, 0, + /* 7616 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'q', 'q', 9, 0, + /* 7627 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'q', 'q', 9, 0, + /* 7639 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'q', 'q', 9, 0, + /* 7650 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'q', 9, 0, + /* 7660 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'q', 9, 0, + /* 7672 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'q', 9, 0, + /* 7685 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'q', 'q', 9, 0, + /* 7698 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'u', 'q', 'q', 9, 0, + /* 7710 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'u', 'q', 'q', 9, 0, + /* 7723 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'u', 'q', 'q', 9, 0, + /* 7735 */ 'l', 'a', 'r', 'q', 9, 0, + /* 7741 */ 's', 'a', 'r', 'q', 9, 0, + /* 7747 */ 'r', 'c', 'r', 'q', 9, 0, + /* 7753 */ 's', 'h', 'r', 'q', 9, 0, + /* 7759 */ 'k', 'o', 'r', 'q', 9, 0, + /* 7765 */ 'k', 'x', 'n', 'o', 'r', 'q', 9, 0, + /* 7773 */ 'v', 'p', 'o', 'r', 'q', 9, 0, + /* 7780 */ 'v', 'p', 'r', 'o', 'r', 'q', 9, 0, + /* 7788 */ 'k', 'x', 'o', 'r', 'q', 9, 0, + /* 7795 */ 'v', 'p', 'x', 'o', 'r', 'q', 9, 0, + /* 7803 */ 'b', 's', 'r', 'q', 9, 0, + /* 7809 */ 'b', 'l', 's', 'r', 'q', 9, 0, + /* 7816 */ 'v', 'p', 'i', 'n', 's', 'r', 'q', 9, 0, + /* 7825 */ 'b', 't', 'r', 'q', 9, 0, + /* 7831 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'q', 9, 0, + /* 7841 */ 's', 't', 'r', 'q', 9, 0, + /* 7847 */ 'b', 'e', 'x', 't', 'r', 'q', 9, 0, + /* 7855 */ 'v', 'p', 'e', 'x', 't', 'r', 'q', 9, 0, + /* 7864 */ 's', 'c', 'a', 's', 'q', 9, 0, + /* 7871 */ 'v', 'p', 'a', 'b', 's', 'q', 9, 0, + /* 7879 */ 'm', 'o', 'v', 'a', 'b', 's', 'q', 9, 0, + /* 7888 */ 'b', 'l', 'c', 's', 'q', 9, 0, + /* 7895 */ 'l', 'o', 'd', 's', 'q', 9, 0, + /* 7902 */ 'l', 'f', 's', 'q', 9, 0, + /* 7908 */ 'v', 'p', 'm', 'i', 'n', 's', 'q', 9, 0, + /* 7917 */ 'c', 'm', 'o', 'v', 'n', 's', 'q', 9, 0, + /* 7926 */ 'c', 'm', 'p', 's', 'q', 9, 0, + /* 7933 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 's', 'q', 9, 0, + /* 7945 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 's', 'q', 9, 0, + /* 7958 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'q', 9, 0, + /* 7971 */ 'l', 's', 's', 'q', 9, 0, + /* 7977 */ 'w', 'r', 's', 's', 'q', 9, 0, + /* 7984 */ 'w', 'r', 'u', 's', 's', 'q', 9, 0, + /* 7992 */ 'b', 't', 's', 'q', 9, 0, + /* 7998 */ 'c', 'm', 'o', 'v', 's', 'q', 9, 0, + /* 8006 */ 'v', 'p', 'm', 'a', 'x', 's', 'q', 9, 0, + /* 8015 */ 'b', 't', 'q', 9, 0, + /* 8020 */ 'v', 'p', 'c', 'o', 'n', 'f', 'l', 'i', 'c', 't', 'q', 9, 0, + /* 8033 */ 'l', 'g', 'd', 't', 'q', 9, 0, + /* 8040 */ 's', 'g', 'd', 't', 'q', 9, 0, + /* 8047 */ 'l', 'i', 'd', 't', 'q', 9, 0, + /* 8054 */ 's', 'i', 'd', 't', 'q', 9, 0, + /* 8061 */ 's', 'l', 'd', 't', 'q', 9, 0, + /* 8068 */ 'l', 'r', 'e', 't', 'q', 9, 0, + /* 8075 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'q', 9, 0, + /* 8085 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'q', 9, 0, + /* 8095 */ 'v', 'p', 'l', 'z', 'c', 'n', 't', 'q', 9, 0, + /* 8105 */ 't', 'z', 'c', 'n', 't', 'q', 9, 0, + /* 8113 */ 'm', 'o', 'v', 'n', 't', 'q', 9, 0, + /* 8121 */ 'k', 'n', 'o', 't', 'q', 9, 0, + /* 8128 */ 'v', 'p', 'r', 'o', 't', 'q', 9, 0, + /* 8136 */ 'i', 'n', 's', 'e', 'r', 't', 'q', 9, 0, + /* 8145 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'q', 9, 0, + /* 8159 */ 'k', 't', 'e', 's', 't', 'q', 9, 0, + /* 8167 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'q', 9, 0, + /* 8177 */ 'p', 'e', 'x', 't', 'q', 9, 0, + /* 8184 */ 'v', 'p', 'm', 'a', 'd', 'd', '5', '2', 'h', 'u', 'q', 9, 0, + /* 8197 */ 'v', 'p', 'm', 'a', 'd', 'd', '5', '2', 'l', 'u', 'q', 9, 0, + /* 8210 */ 'v', 'p', 'c', 'o', 'm', 'u', 'q', 9, 0, + /* 8219 */ 'v', 'p', 'm', 'i', 'n', 'u', 'q', 9, 0, + /* 8228 */ 'v', 'p', 'c', 'm', 'p', 'u', 'q', 9, 0, + /* 8237 */ 'v', 'p', 'm', 'a', 'x', 'u', 'q', 9, 0, + /* 8246 */ 'v', 'p', 's', 'r', 'a', 'v', 'q', 9, 0, + /* 8255 */ 'v', 'p', 's', 'h', 'l', 'd', 'v', 'q', 9, 0, + /* 8265 */ 'v', 'p', 's', 'h', 'r', 'd', 'v', 'q', 9, 0, + /* 8275 */ 'i', 'd', 'i', 'v', 'q', 9, 0, + /* 8282 */ 'v', 'p', 's', 'l', 'l', 'v', 'q', 9, 0, + /* 8291 */ 'v', 'p', 'r', 'o', 'l', 'v', 'q', 9, 0, + /* 8300 */ 'v', 'p', 's', 'r', 'l', 'v', 'q', 9, 0, + /* 8309 */ 'v', 'p', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'q', 9, 0, + /* 8321 */ 'v', 'm', 'o', 'v', 'q', 9, 0, + /* 8328 */ 'v', 'p', 'r', 'o', 'r', 'v', 'q', 9, 0, + /* 8337 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 'q', 9, 0, + /* 8347 */ 's', 'm', 's', 'w', 'q', 9, 0, + /* 8354 */ 'm', 'o', 'v', 's', 'w', 'q', 9, 0, + /* 8362 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'w', 'q', 9, 0, + /* 8373 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'q', 9, 0, + /* 8384 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'q', 9, 0, + /* 8395 */ 'm', 'o', 'v', 'z', 'w', 'q', 9, 0, + /* 8403 */ 'a', 'd', 'c', 'x', 'q', 9, 0, + /* 8410 */ 's', 'h', 'l', 'x', 'q', 9, 0, + /* 8417 */ 'm', 'u', 'l', 'x', 'q', 9, 0, + /* 8424 */ 'a', 'd', 'o', 'x', 'q', 9, 0, + /* 8431 */ 's', 'a', 'r', 'x', 'q', 9, 0, + /* 8438 */ 's', 'h', 'r', 'x', 'q', 9, 0, + /* 8445 */ 'r', 'o', 'r', 'x', 'q', 9, 0, + /* 8452 */ 'v', 'm', 'c', 'l', 'e', 'a', 'r', 9, 0, + /* 8461 */ 'p', 'f', 's', 'u', 'b', 'r', 9, 0, + /* 8469 */ 'e', 'n', 't', 'e', 'r', 9, 0, + /* 8476 */ 'v', 'p', 'a', 'l', 'i', 'g', 'n', 'r', 9, 0, + /* 8486 */ 'v', 'p', 'o', 'r', 9, 0, + /* 8492 */ 'u', 'm', 'o', 'n', 'i', 't', 'o', 'r', 9, 0, + /* 8502 */ 'f', 'r', 's', 't', 'o', 'r', 9, 0, + /* 8510 */ 'f', 'x', 'r', 's', 't', 'o', 'r', 9, 0, + /* 8519 */ 'v', 'p', 'x', 'o', 'r', 9, 0, + /* 8526 */ 'v', 'e', 'r', 'r', 9, 0, + /* 8532 */ 'v', 'l', 'd', 'm', 'x', 'c', 's', 'r', 9, 0, + /* 8542 */ 'v', 's', 't', 'm', 'x', 'c', 's', 'r', 9, 0, + /* 8552 */ 'f', 'd', 'i', 'v', 'r', 9, 0, + /* 8559 */ 'f', 's', 'u', 'b', 's', 9, 0, + /* 8566 */ 'f', 'i', 's', 'u', 'b', 's', 9, 0, + /* 8574 */ 'f', 'a', 'd', 'd', 's', 9, 0, + /* 8581 */ 'f', 'i', 'a', 'd', 'd', 's', 9, 0, + /* 8589 */ 'f', 'l', 'd', 's', 9, 0, + /* 8595 */ 'f', 'i', 'l', 'd', 's', 9, 0, + /* 8602 */ 'v', 'p', '4', 'd', 'p', 'w', 's', 's', 'd', 's', 9, 0, + /* 8614 */ 'v', 'p', 'd', 'p', 'w', 's', 's', 'd', 's', 9, 0, + /* 8625 */ 'v', 'p', 'd', 'p', 'b', 'u', 's', 'd', 's', 9, 0, + /* 8636 */ 'x', 's', 'a', 'v', 'e', 's', 9, 0, + /* 8644 */ 'l', 'g', 's', 9, 0, + /* 8649 */ 'j', 's', 9, 0, + /* 8653 */ 'f', 'm', 'u', 'l', 's', 9, 0, + /* 8660 */ 'f', 'i', 'm', 'u', 'l', 's', 9, 0, + /* 8668 */ 'f', 'c', 'o', 'm', 's', 9, 0, + /* 8675 */ 'f', 'i', 'c', 'o', 'm', 's', 9, 0, + /* 8683 */ 'l', 'w', 'p', 'i', 'n', 's', 9, 0, + /* 8691 */ 'j', 'n', 's', 9, 0, + /* 8696 */ 's', 'e', 't', 'n', 's', 9, 0, + /* 8703 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '3', '1', 'p', 's', 9, 0, + /* 8719 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 's', 9, 0, + /* 8732 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 's', 9, 0, + /* 8746 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '3', '1', 'p', 's', 9, 0, + /* 8762 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 's', 9, 0, + /* 8775 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 's', 9, 0, + /* 8789 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 's', 9, 0, + /* 8805 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 's', 9, 0, + /* 8818 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 's', 9, 0, + /* 8832 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, + /* 8848 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, + /* 8861 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, + /* 8875 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 9, 0, + /* 8886 */ 'v', 'c', 'v', 't', 'p', 'h', '2', 'p', 's', 9, 0, + /* 8897 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'p', 's', 9, 0, + /* 8908 */ 'c', 'v', 't', 'p', 'i', '2', 'p', 's', 9, 0, + /* 8918 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', '2', 'p', 's', 9, 0, + /* 8930 */ 'v', 'e', 'x', 'p', '2', 'p', 's', 9, 0, + /* 8939 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 's', 9, 0, + /* 8950 */ 'v', 'c', 'v', 't', 'u', 'd', 'q', '2', 'p', 's', 9, 0, + /* 8962 */ 'v', 'c', 'v', 't', 'q', 'q', '2', 'p', 's', 9, 0, + /* 8973 */ 'v', 'c', 'v', 't', 'u', 'q', 'q', '2', 'p', 's', 9, 0, + /* 8985 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'p', 's', 9, 0, + /* 8996 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, + /* 9012 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, + /* 9025 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, + /* 9039 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, + /* 9055 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, + /* 9068 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, + /* 9082 */ 'v', 'r', 'c', 'p', '1', '4', 'p', 's', 9, 0, + /* 9092 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 'p', 's', 9, 0, + /* 9104 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 's', 9, 0, + /* 9114 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 's', 9, 0, + /* 9126 */ 'v', 'm', 'o', 'v', 'a', 'p', 's', 9, 0, + /* 9135 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', 'p', 's', 9, 0, + /* 9148 */ 'v', 'a', 'd', 'd', 's', 'u', 'b', 'p', 's', 9, 0, + /* 9159 */ 'v', 'h', 's', 'u', 'b', 'p', 's', 9, 0, + /* 9168 */ 'v', 'f', 'm', 's', 'u', 'b', 'p', 's', 9, 0, + /* 9178 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 'p', 's', 9, 0, + /* 9189 */ 'v', 's', 'u', 'b', 'p', 's', 9, 0, + /* 9197 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'd', 'p', 's', 9, 0, + /* 9212 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'd', 'p', 's', 9, 0, + /* 9228 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'd', 'p', 's', 9, 0, + /* 9243 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'd', 'p', 's', 9, 0, + /* 9259 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 9272 */ 'v', 'h', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 9281 */ 'v', '4', 'f', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 9292 */ 'v', 'f', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 9302 */ 'v', '4', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 9314 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 9325 */ 'v', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 9333 */ 'v', 'e', 'x', 'p', 'a', 'n', 'd', 'p', 's', 9, 0, + /* 9344 */ 'v', 'a', 'n', 'd', 'p', 's', 9, 0, + /* 9352 */ 'v', 'b', 'l', 'e', 'n', 'd', 'p', 's', 9, 0, + /* 9362 */ 'v', 'r', 'o', 'u', 'n', 'd', 'p', 's', 9, 0, + /* 9372 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 's', 9, 0, + /* 9384 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'p', 's', 9, 0, + /* 9397 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 'p', 's', 9, 0, + /* 9408 */ 'v', 'r', 'a', 'n', 'g', 'e', 'p', 's', 9, 0, + /* 9418 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 'p', 's', 9, 0, + /* 9431 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 'p', 's', 9, 0, + /* 9442 */ 'v', 's', 'h', 'u', 'f', 'p', 's', 9, 0, + /* 9451 */ 'v', 'u', 'n', 'p', 'c', 'k', 'h', 'p', 's', 9, 0, + /* 9462 */ 'v', 'm', 'o', 'v', 'l', 'h', 'p', 's', 9, 0, + /* 9472 */ 'v', 'm', 'o', 'v', 'h', 'p', 's', 9, 0, + /* 9481 */ 'v', 'm', 'o', 'v', 'm', 's', 'k', 'p', 's', 9, 0, + /* 9492 */ 'v', 'm', 'o', 'v', 'h', 'l', 'p', 's', 9, 0, + /* 9502 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 's', 9, 0, + /* 9513 */ 'v', 'u', 'n', 'p', 'c', 'k', 'l', 'p', 's', 9, 0, + /* 9524 */ 'v', 'm', 'u', 'l', 'p', 's', 9, 0, + /* 9532 */ 'v', 'm', 'o', 'v', 'l', 'p', 's', 9, 0, + /* 9541 */ 'v', 'b', 'l', 'e', 'n', 'd', 'm', 'p', 's', 9, 0, + /* 9552 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 'p', 's', 9, 0, + /* 9565 */ 'f', 'c', 'o', 'm', 'p', 's', 9, 0, + /* 9573 */ 'f', 'i', 'c', 'o', 'm', 'p', 's', 9, 0, + /* 9582 */ 'v', 'p', 'e', 'r', 'm', 'p', 's', 9, 0, + /* 9591 */ 'v', 'a', 'n', 'd', 'n', 'p', 's', 9, 0, + /* 9600 */ 'v', 'm', 'i', 'n', 'p', 's', 9, 0, + /* 9608 */ 'v', 'r', 'c', 'p', 'p', 's', 9, 0, + /* 9616 */ 'v', 'd', 'p', 'p', 's', 9, 0, + /* 9623 */ 'v', 'c', 'm', 'p', 'p', 's', 9, 0, + /* 9631 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 'p', 's', 9, 0, + /* 9642 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'q', 'p', 's', 9, 0, + /* 9657 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'q', 'p', 's', 9, 0, + /* 9673 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'q', 'p', 's', 9, 0, + /* 9688 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'q', 'p', 's', 9, 0, + /* 9704 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 's', 9, 0, + /* 9716 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'p', 's', 9, 0, + /* 9729 */ 'v', 'o', 'r', 'p', 's', 9, 0, + /* 9736 */ 'v', 'x', 'o', 'r', 'p', 's', 9, 0, + /* 9744 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 's', 9, 0, + /* 9756 */ 'v', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'p', 's', 9, 0, + /* 9769 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'p', 's', 9, 0, + /* 9781 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 'p', 's', 9, 0, + /* 9793 */ 'v', 'm', 'o', 'v', 'n', 't', 'p', 's', 9, 0, + /* 9803 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'p', 's', 9, 0, + /* 9814 */ 'v', 'r', 's', 'q', 'r', 't', 'p', 's', 9, 0, + /* 9824 */ 'v', 's', 'q', 'r', 't', 'p', 's', 9, 0, + /* 9833 */ 'v', 't', 'e', 's', 't', 'p', 's', 9, 0, + /* 9842 */ 'f', 's', 't', 'p', 's', 9, 0, + /* 9849 */ 'f', 'i', 's', 't', 'p', 's', 9, 0, + /* 9857 */ 'f', 'i', 's', 't', 't', 'p', 's', 9, 0, + /* 9866 */ 'v', 'm', 'o', 'v', 'u', 'p', 's', 9, 0, + /* 9875 */ 'v', 'b', 'l', 'e', 'n', 'd', 'v', 'p', 's', 9, 0, + /* 9886 */ 'v', 'd', 'i', 'v', 'p', 's', 9, 0, + /* 9894 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'p', 's', 9, 0, + /* 9906 */ 'v', 'm', 'a', 'x', 'p', 's', 9, 0, + /* 9914 */ 'v', 'f', 'r', 'c', 'z', 'p', 's', 9, 0, + /* 9923 */ 'f', 's', 'u', 'b', 'r', 's', 9, 0, + /* 9931 */ 'f', 'i', 's', 'u', 'b', 'r', 's', 9, 0, + /* 9940 */ 'x', 'r', 's', 't', 'o', 'r', 's', 9, 0, + /* 9949 */ 'f', 'd', 'i', 'v', 'r', 's', 9, 0, + /* 9957 */ 'f', 'i', 'd', 'i', 'v', 'r', 's', 9, 0, + /* 9966 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 's', 's', 9, 0, + /* 9979 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 's', 's', 9, 0, + /* 9993 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 's', 9, 0, + /* 10006 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 's', 9, 0, + /* 10020 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 's', 's', 9, 0, + /* 10033 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 's', 's', 9, 0, + /* 10047 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 's', 9, 0, + /* 10060 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 's', 9, 0, + /* 10074 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 's', 9, 0, + /* 10085 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 9, 0, + /* 10098 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 9, 0, + /* 10112 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 9, 0, + /* 10125 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 9, 0, + /* 10139 */ 'v', 'r', 'c', 'p', '1', '4', 's', 's', 9, 0, + /* 10149 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 's', 's', 9, 0, + /* 10161 */ 'v', 'r', 'c', 'p', '2', '8', 's', 's', 9, 0, + /* 10171 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 's', 9, 0, + /* 10183 */ 'v', 'f', 'm', 's', 'u', 'b', 's', 's', 9, 0, + /* 10193 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 's', 9, 0, + /* 10204 */ 'v', 's', 'u', 'b', 's', 's', 9, 0, + /* 10212 */ 'v', '4', 'f', 'm', 'a', 'd', 'd', 's', 's', 9, 0, + /* 10223 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 's', 9, 0, + /* 10233 */ 'v', '4', 'f', 'n', 'm', 'a', 'd', 'd', 's', 's', 9, 0, + /* 10245 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 's', 9, 0, + /* 10256 */ 'v', 'a', 'd', 'd', 's', 's', 9, 0, + /* 10264 */ 'v', 'r', 'o', 'u', 'n', 'd', 's', 's', 9, 0, + /* 10274 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 's', 's', 9, 0, + /* 10285 */ 'v', 'r', 'a', 'n', 'g', 'e', 's', 's', 9, 0, + /* 10295 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 's', 's', 9, 0, + /* 10308 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 's', 's', 9, 0, + /* 10319 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 's', 9, 0, + /* 10329 */ 'v', 'c', 'o', 'm', 'i', 's', 's', 9, 0, + /* 10338 */ 'v', 'm', 'u', 'l', 's', 's', 9, 0, + /* 10346 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 's', 's', 9, 0, + /* 10359 */ 'v', 'm', 'i', 'n', 's', 's', 9, 0, + /* 10367 */ 'v', 'r', 'c', 'p', 's', 's', 9, 0, + /* 10375 */ 'v', 'c', 'm', 'p', 's', 's', 9, 0, + /* 10383 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 's', 's', 9, 0, + /* 10394 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 's', 's', 9, 0, + /* 10406 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 's', 's', 9, 0, + /* 10418 */ 'm', 'o', 'v', 'n', 't', 's', 's', 9, 0, + /* 10427 */ 'v', 'r', 's', 'q', 'r', 't', 's', 's', 9, 0, + /* 10437 */ 'v', 's', 'q', 'r', 't', 's', 's', 9, 0, + /* 10446 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 's', 9, 0, + /* 10460 */ 'v', 'd', 'i', 'v', 's', 's', 9, 0, + /* 10468 */ 'v', 'm', 'o', 'v', 's', 's', 9, 0, + /* 10476 */ 'v', 'm', 'a', 'x', 's', 's', 9, 0, + /* 10484 */ 'v', 'f', 'r', 'c', 'z', 's', 's', 9, 0, + /* 10493 */ 's', 'e', 't', 's', 9, 0, + /* 10499 */ 'f', 's', 't', 's', 9, 0, + /* 10505 */ 'f', 'i', 's', 't', 's', 9, 0, + /* 10512 */ 'f', 'd', 'i', 'v', 's', 9, 0, + /* 10519 */ 'f', 'i', 'd', 'i', 'v', 's', 9, 0, + /* 10527 */ 'f', 'l', 'd', 't', 9, 0, + /* 10533 */ 'p', 'f', 'c', 'm', 'p', 'g', 't', 9, 0, + /* 10542 */ 'u', 'm', 'w', 'a', 'i', 't', 9, 0, + /* 10550 */ 'i', 'n', 't', 9, 0, + /* 10555 */ 'i', 'n', 'v', 'e', 'p', 't', 9, 0, + /* 10563 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 9, 0, + /* 10573 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 'o', 'p', 't', 9, 0, + /* 10585 */ 'f', 's', 't', 'p', 't', 9, 0, + /* 10592 */ 'x', 'a', 'b', 'o', 'r', 't', 9, 0, + /* 10600 */ 'p', 'f', 'r', 's', 'q', 'r', 't', 9, 0, + /* 10609 */ 'v', 'a', 'e', 's', 'd', 'e', 'c', 'l', 'a', 's', 't', 9, 0, + /* 10622 */ 'v', 'a', 'e', 's', 'e', 'n', 'c', 'l', 'a', 's', 't', 9, 0, + /* 10635 */ 'v', 'p', 't', 'e', 's', 't', 9, 0, + /* 10643 */ 'f', 's', 't', 9, 0, + /* 10648 */ 'v', 'a', 'e', 's', 'k', 'e', 'y', 'g', 'e', 'n', 'a', 's', 's', 'i', 's', 't', 9, 0, + /* 10666 */ 'v', 'm', 'p', 't', 'r', 's', 't', 9, 0, + /* 10675 */ 'b', 'n', 'd', 'c', 'u', 9, 0, + /* 10682 */ 'f', 'c', 'm', 'o', 'v', 'n', 'u', 9, 0, + /* 10691 */ 'v', 'l', 'd', 'd', 'q', 'u', 9, 0, + /* 10699 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'd', 'q', 'u', 9, 0, + /* 10712 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', 9, 0, + /* 10721 */ 'f', 'c', 'm', 'o', 'v', 'u', 9, 0, + /* 10729 */ 'f', 'd', 'i', 'v', 9, 0, + /* 10735 */ 'f', 'l', 'd', 'e', 'n', 'v', 9, 0, + /* 10743 */ 'f', 'n', 's', 't', 'e', 'n', 'v', 9, 0, + /* 10752 */ 'v', 'p', 'c', 'm', 'o', 'v', 9, 0, + /* 10760 */ 'b', 'n', 'd', 'm', 'o', 'v', 9, 0, + /* 10768 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, + /* 10776 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'w', 9, 0, + /* 10786 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'w', 9, 0, + /* 10796 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'w', 9, 0, + /* 10806 */ 'l', 'e', 'a', 'w', 9, 0, + /* 10812 */ 'v', 'p', 's', 'h', 'a', 'w', 9, 0, + /* 10820 */ 'v', 'p', 's', 'r', 'a', 'w', 9, 0, + /* 10828 */ 'c', 'm', 'o', 'v', 'a', 'w', 9, 0, + /* 10836 */ 's', 'b', 'b', 'w', 9, 0, + /* 10842 */ 'v', 'p', 'h', 's', 'u', 'b', 'b', 'w', 9, 0, + /* 10852 */ 'v', 'd', 'b', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, + /* 10863 */ 'v', 'm', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, + /* 10873 */ 'v', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, + /* 10882 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'w', 9, 0, + /* 10892 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'b', 'w', 9, 0, + /* 10904 */ 'k', 'u', 'n', 'p', 'c', 'k', 'b', 'w', 9, 0, + /* 10914 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'b', 'w', 9, 0, + /* 10926 */ 'm', 'o', 'v', 's', 'b', 'w', 9, 0, + /* 10934 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'w', 9, 0, + /* 10945 */ 'v', 'p', 'h', 's', 'u', 'b', 'w', 9, 0, + /* 10954 */ 'v', 'p', 's', 'u', 'b', 'w', 9, 0, + /* 10962 */ 'c', 'm', 'o', 'v', 'b', 'w', 9, 0, + /* 10970 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'w', 9, 0, + /* 10981 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'w', 9, 0, + /* 10992 */ 'm', 'o', 'v', 'z', 'b', 'w', 9, 0, + /* 11000 */ 'a', 'd', 'c', 'w', 9, 0, + /* 11006 */ 'f', 'l', 'd', 'c', 'w', 9, 0, + /* 11013 */ 'd', 'e', 'c', 'w', 9, 0, + /* 11019 */ 'i', 'n', 'c', 'w', 9, 0, + /* 11025 */ 'b', 't', 'c', 'w', 9, 0, + /* 11031 */ 'f', 'n', 's', 't', 'c', 'w', 9, 0, + /* 11039 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 9, 0, + /* 11048 */ 'k', 'a', 'd', 'd', 'w', 9, 0, + /* 11055 */ 'v', 'p', 'a', 'd', 'd', 'w', 9, 0, + /* 11063 */ 'x', 'a', 'd', 'd', 'w', 9, 0, + /* 11070 */ 'r', 'd', 's', 'e', 'e', 'd', 'w', 9, 0, + /* 11079 */ 'v', 'p', 's', 'h', 'l', 'd', 'w', 9, 0, + /* 11088 */ 'k', 'a', 'n', 'd', 'w', 9, 0, + /* 11095 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'w', 9, 0, + /* 11106 */ 'r', 'd', 'r', 'a', 'n', 'd', 'w', 9, 0, + /* 11115 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'w', 9, 0, + /* 11125 */ 'v', 'p', 's', 'h', 'r', 'd', 'w', 9, 0, + /* 11134 */ 'v', 'p', 'a', 'c', 'k', 's', 's', 'd', 'w', 9, 0, + /* 11145 */ 'v', 'p', 'a', 'c', 'k', 'u', 's', 'd', 'w', 9, 0, + /* 11156 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'd', 'w', 9, 0, + /* 11167 */ 'v', 'p', 'm', 'o', 'v', 's', 'd', 'w', 9, 0, + /* 11177 */ 'v', 'p', 'm', 'o', 'v', 'd', 'w', 9, 0, + /* 11186 */ 'c', 'm', 'o', 'v', 'a', 'e', 'w', 9, 0, + /* 11195 */ 'c', 'm', 'o', 'v', 'b', 'e', 'w', 9, 0, + /* 11204 */ 'c', 'm', 'o', 'v', 'g', 'e', 'w', 9, 0, + /* 11213 */ 'c', 'm', 'o', 'v', 'l', 'e', 'w', 9, 0, + /* 11222 */ 'c', 'm', 'o', 'v', 'n', 'e', 'w', 9, 0, + /* 11231 */ 'c', 'm', 'o', 'v', 'e', 'w', 9, 0, + /* 11239 */ 'p', 'i', '2', 'f', 'w', 9, 0, + /* 11246 */ 'b', 's', 'f', 'w', 9, 0, + /* 11252 */ 'p', 's', 'h', 'u', 'f', 'w', 9, 0, + /* 11260 */ 'n', 'e', 'g', 'w', 9, 0, + /* 11266 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'w', 9, 0, + /* 11276 */ 'v', 'p', 'a', 'v', 'g', 'w', 9, 0, + /* 11284 */ 'c', 'm', 'o', 'v', 'g', 'w', 9, 0, + /* 11292 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'w', 9, 0, + /* 11303 */ 'v', 'p', 's', 'h', 'u', 'f', 'h', 'w', 9, 0, + /* 11313 */ 'v', 'p', 'm', 'u', 'l', 'h', 'w', 9, 0, + /* 11322 */ 'p', 'u', 's', 'h', 'w', 9, 0, + /* 11329 */ 'p', 'f', '2', 'i', 'w', 9, 0, + /* 11336 */ 's', 'a', 'l', 'w', 9, 0, + /* 11342 */ 'r', 'c', 'l', 'w', 9, 0, + /* 11348 */ 'v', 'p', 's', 'h', 'u', 'f', 'l', 'w', 9, 0, + /* 11358 */ 'v', 'p', 's', 'h', 'l', 'w', 9, 0, + /* 11366 */ 'l', 'c', 'a', 'l', 'l', 'w', 9, 0, + /* 11374 */ 'v', 'p', 's', 'l', 'l', 'w', 9, 0, + /* 11382 */ 'v', 'p', 'm', 'u', 'l', 'l', 'w', 9, 0, + /* 11391 */ 'r', 'o', 'l', 'w', 9, 0, + /* 11397 */ 'v', 'p', 's', 'r', 'l', 'w', 9, 0, + /* 11405 */ 'l', 's', 'l', 'w', 9, 0, + /* 11411 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'w', 9, 0, + /* 11421 */ 'i', 'm', 'u', 'l', 'w', 9, 0, + /* 11428 */ 'c', 'm', 'o', 'v', 'l', 'w', 9, 0, + /* 11436 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'w', 9, 0, + /* 11447 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'w', 9, 0, + /* 11458 */ 'v', 'p', 'c', 'o', 'm', 'w', 9, 0, + /* 11466 */ 'v', 'p', 'e', 'r', 'm', 'w', 9, 0, + /* 11474 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'w', 9, 0, + /* 11484 */ 'k', 'a', 'n', 'd', 'n', 'w', 9, 0, + /* 11492 */ 'v', 'p', 's', 'i', 'g', 'n', 'w', 9, 0, + /* 11501 */ 'i', 'n', 'w', 9, 0, + /* 11506 */ 'c', 'm', 'o', 'v', 'n', 'o', 'w', 9, 0, + /* 11515 */ 'c', 'm', 'o', 'v', 'o', 'w', 9, 0, + /* 11523 */ 'b', 's', 'w', 'a', 'p', 'w', 9, 0, + /* 11531 */ 'v', 'p', 'c', 'm', 'p', 'w', 9, 0, + /* 11539 */ 'l', 'j', 'm', 'p', 'w', 9, 0, + /* 11546 */ 'c', 'm', 'o', 'v', 'n', 'p', 'w', 9, 0, + /* 11555 */ 'n', 'o', 'p', 'w', 9, 0, + /* 11561 */ 'p', 'o', 'p', 'w', 9, 0, + /* 11567 */ 'c', 'm', 'o', 'v', 'p', 'w', 9, 0, + /* 11575 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'w', 9, 0, + /* 11585 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'w', 9, 0, + /* 11596 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'w', 9, 0, + /* 11606 */ 'v', 'p', 'm', 'o', 'v', 'q', 'w', 9, 0, + /* 11615 */ 'l', 'a', 'r', 'w', 9, 0, + /* 11621 */ 's', 'a', 'r', 'w', 9, 0, + /* 11627 */ 'r', 'c', 'r', 'w', 9, 0, + /* 11633 */ 'v', 'e', 'r', 'w', 9, 0, + /* 11639 */ 'p', 'm', 'u', 'l', 'h', 'r', 'w', 9, 0, + /* 11648 */ 's', 'h', 'r', 'w', 9, 0, + /* 11654 */ 'k', 'o', 'r', 'w', 9, 0, + /* 11660 */ 'k', 'x', 'n', 'o', 'r', 'w', 9, 0, + /* 11668 */ 'r', 'o', 'r', 'w', 9, 0, + /* 11674 */ 'k', 'x', 'o', 'r', 'w', 9, 0, + /* 11681 */ 'b', 's', 'r', 'w', 9, 0, + /* 11687 */ 'v', 'p', 'i', 'n', 's', 'r', 'w', 9, 0, + /* 11696 */ 'b', 't', 'r', 'w', 9, 0, + /* 11702 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'w', 9, 0, + /* 11712 */ 'l', 't', 'r', 'w', 9, 0, + /* 11718 */ 's', 't', 'r', 'w', 9, 0, + /* 11724 */ 'v', 'p', 'e', 'x', 't', 'r', 'w', 9, 0, + /* 11733 */ 's', 'c', 'a', 's', 'w', 9, 0, + /* 11740 */ 'v', 'p', 'a', 'b', 's', 'w', 9, 0, + /* 11748 */ 'm', 'o', 'v', 'a', 'b', 's', 'w', 9, 0, + /* 11757 */ 'v', 'p', 'm', 'a', 'd', 'd', 'u', 'b', 's', 'w', 9, 0, + /* 11769 */ 'v', 'p', 'h', 's', 'u', 'b', 's', 'w', 9, 0, + /* 11779 */ 'v', 'p', 's', 'u', 'b', 's', 'w', 9, 0, + /* 11788 */ 'v', 'p', 'h', 'a', 'd', 'd', 's', 'w', 9, 0, + /* 11798 */ 'v', 'p', 'a', 'd', 'd', 's', 'w', 9, 0, + /* 11807 */ 'l', 'd', 's', 'w', 9, 0, + /* 11813 */ 'l', 'o', 'd', 's', 'w', 9, 0, + /* 11820 */ 'l', 'e', 's', 'w', 9, 0, + /* 11826 */ 'l', 'f', 's', 'w', 9, 0, + /* 11832 */ 'l', 'g', 's', 'w', 9, 0, + /* 11838 */ 'v', 'p', 'm', 'i', 'n', 's', 'w', 9, 0, + /* 11847 */ 'c', 'm', 'o', 'v', 'n', 's', 'w', 9, 0, + /* 11856 */ 'c', 'm', 'p', 's', 'w', 9, 0, + /* 11863 */ 'v', 'p', 'm', 'u', 'l', 'h', 'r', 's', 'w', 9, 0, + /* 11874 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'w', 9, 0, + /* 11887 */ 'l', 's', 's', 'w', 9, 0, + /* 11893 */ 'b', 't', 's', 'w', 9, 0, + /* 11899 */ 'f', 'n', 's', 't', 's', 'w', 9, 0, + /* 11907 */ 'o', 'u', 't', 's', 'w', 9, 0, + /* 11914 */ 'v', 'p', 's', 'u', 'b', 'u', 's', 'w', 9, 0, + /* 11924 */ 'v', 'p', 'a', 'd', 'd', 'u', 's', 'w', 9, 0, + /* 11934 */ 'c', 'm', 'o', 'v', 's', 'w', 9, 0, + /* 11942 */ 'v', 'p', 'm', 'a', 'x', 's', 'w', 9, 0, + /* 11951 */ 'b', 't', 'w', 9, 0, + /* 11956 */ 'l', 'g', 'd', 't', 'w', 9, 0, + /* 11963 */ 's', 'g', 'd', 't', 'w', 9, 0, + /* 11970 */ 'l', 'i', 'd', 't', 'w', 9, 0, + /* 11977 */ 's', 'i', 'd', 't', 'w', 9, 0, + /* 11984 */ 'l', 'l', 'd', 't', 'w', 9, 0, + /* 11991 */ 's', 'l', 'd', 't', 'w', 9, 0, + /* 11998 */ 'l', 'r', 'e', 't', 'w', 9, 0, + /* 12005 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'w', 9, 0, + /* 12015 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'w', 9, 0, + /* 12025 */ 'l', 'z', 'c', 'n', 't', 'w', 9, 0, + /* 12033 */ 't', 'z', 'c', 'n', 't', 'w', 9, 0, + /* 12041 */ 'k', 'n', 'o', 't', 'w', 9, 0, + /* 12048 */ 'v', 'p', 'r', 'o', 't', 'w', 9, 0, + /* 12056 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'w', 9, 0, + /* 12070 */ 'k', 't', 'e', 's', 't', 'w', 9, 0, + /* 12078 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'w', 9, 0, + /* 12088 */ 'v', 'p', 'm', 'u', 'l', 'h', 'u', 'w', 9, 0, + /* 12098 */ 'v', 'p', 'c', 'o', 'm', 'u', 'w', 9, 0, + /* 12107 */ 'v', 'p', 'm', 'i', 'n', 'u', 'w', 9, 0, + /* 12116 */ 'v', 'p', 'c', 'm', 'p', 'u', 'w', 9, 0, + /* 12125 */ 'v', 'p', 'h', 'm', 'i', 'n', 'p', 'o', 's', 'u', 'w', 9, 0, + /* 12138 */ 'v', 'p', 'm', 'a', 'x', 'u', 'w', 9, 0, + /* 12147 */ 'v', 'p', 's', 'r', 'a', 'v', 'w', 9, 0, + /* 12156 */ 'v', 'p', 's', 'h', 'l', 'd', 'v', 'w', 9, 0, + /* 12166 */ 'v', 'p', 's', 'h', 'r', 'd', 'v', 'w', 9, 0, + /* 12176 */ 'i', 'd', 'i', 'v', 'w', 9, 0, + /* 12183 */ 'v', 'p', 's', 'l', 'l', 'v', 'w', 9, 0, + /* 12192 */ 'v', 'p', 's', 'r', 'l', 'v', 'w', 9, 0, + /* 12201 */ 'k', 'm', 'o', 'v', 'w', 9, 0, + /* 12208 */ 'v', 'p', 'm', 'a', 'c', 's', 'w', 'w', 9, 0, + /* 12218 */ 'l', 'm', 's', 'w', 'w', 9, 0, + /* 12225 */ 's', 'm', 's', 'w', 'w', 9, 0, + /* 12232 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'w', 'w', 9, 0, + /* 12243 */ 'm', 'o', 'v', 's', 'w', 'w', 9, 0, + /* 12251 */ 'm', 'o', 'v', 'z', 'w', 'w', 9, 0, + /* 12259 */ 'p', 'f', 'm', 'a', 'x', 9, 0, + /* 12266 */ 'b', 'n', 'd', 'l', 'd', 'x', 9, 0, + /* 12274 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 'd', 'x', 9, 0, + /* 12287 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 'x', 9, 0, + /* 12300 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 'x', 9, 0, + /* 12312 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'd', 'q', 'x', 9, 0, + /* 12326 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'u', 'd', 'q', 'x', 9, 0, + /* 12339 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 'x', 9, 0, + /* 12351 */ 'v', 'c', 'v', 't', 'q', 'q', '2', 'p', 's', 'x', 9, 0, + /* 12363 */ 'v', 'c', 'v', 't', 'u', 'q', 'q', '2', 'p', 's', 'x', 9, 0, + /* 12376 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 's', 'x', 9, 0, + /* 12389 */ 'b', 'n', 'd', 's', 't', 'x', 9, 0, + /* 12397 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 'd', 'y', 9, 0, + /* 12410 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 'y', 9, 0, + /* 12423 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 'y', 9, 0, + /* 12435 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'd', 'q', 'y', 9, 0, + /* 12449 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'u', 'd', 'q', 'y', 9, 0, + /* 12462 */ 'c', 'l', 'r', 's', 's', 'b', 's', 'y', 9, 0, + /* 12472 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 'y', 9, 0, + /* 12484 */ 'v', 'c', 'v', 't', 'q', 'q', '2', 'p', 's', 'y', 9, 0, + /* 12496 */ 'v', 'c', 'v', 't', 'u', 'q', 'q', '2', 'p', 's', 'y', 9, 0, + /* 12509 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 's', 'y', 9, 0, + /* 12522 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 'd', 'z', 9, 0, + /* 12535 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 's', 'z', 9, 0, + /* 12548 */ 'j', 'e', 'c', 'x', 'z', 9, 0, + /* 12555 */ 'j', 'c', 'x', 'z', 9, 0, + /* 12561 */ 'j', 'r', 'c', 'x', 'z', 9, 0, + /* 12568 */ 'f', 's', 'u', 'b', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, + /* 12582 */ 'f', 'a', 'd', 'd', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, + /* 12596 */ 'f', 's', 't', 'p', 'n', 'c', 'e', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, + /* 12613 */ 'f', 'm', 'u', 'l', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, + /* 12627 */ 'f', 's', 'u', 'b', 'r', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, + /* 12642 */ 'f', 'd', 'i', 'v', 'r', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, + /* 12657 */ 'f', 'd', 'i', 'v', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, + /* 12671 */ 's', 'h', 'a', '2', '5', '6', 'r', 'n', 'd', 's', '2', 9, '%', 'x', 'm', 'm', '0', ',', 32, 0, + /* 12691 */ 'p', 'b', 'l', 'e', 'n', 'd', 'v', 'b', 9, '%', 'x', 'm', 'm', '0', ',', 32, 0, + /* 12708 */ 'b', 'l', 'e', 'n', 'd', 'v', 'p', 'd', 9, '%', 'x', 'm', 'm', '0', ',', 32, 0, + /* 12725 */ 'b', 'l', 'e', 'n', 'd', 'v', 'p', 's', 9, '%', 'x', 'm', 'm', '0', ',', 32, 0, + /* 12742 */ 's', 'a', 'l', 'b', 9, '$', '1', ',', 32, 0, + /* 12752 */ 'r', 'c', 'l', 'b', 9, '$', '1', ',', 32, 0, + /* 12762 */ 's', 'h', 'l', 'b', 9, '$', '1', ',', 32, 0, + /* 12772 */ 'r', 'o', 'l', 'b', 9, '$', '1', ',', 32, 0, + /* 12782 */ 's', 'a', 'r', 'b', 9, '$', '1', ',', 32, 0, + /* 12792 */ 'r', 'c', 'r', 'b', 9, '$', '1', ',', 32, 0, + /* 12802 */ 's', 'h', 'r', 'b', 9, '$', '1', ',', 32, 0, + /* 12812 */ 'r', 'o', 'r', 'b', 9, '$', '1', ',', 32, 0, + /* 12822 */ 's', 'a', 'l', 'l', 9, '$', '1', ',', 32, 0, + /* 12832 */ 'r', 'c', 'l', 'l', 9, '$', '1', ',', 32, 0, + /* 12842 */ 's', 'h', 'l', 'l', 9, '$', '1', ',', 32, 0, + /* 12852 */ 'r', 'o', 'l', 'l', 9, '$', '1', ',', 32, 0, + /* 12862 */ 's', 'a', 'r', 'l', 9, '$', '1', ',', 32, 0, + /* 12872 */ 'r', 'c', 'r', 'l', 9, '$', '1', ',', 32, 0, + /* 12882 */ 's', 'h', 'r', 'l', 9, '$', '1', ',', 32, 0, + /* 12892 */ 'r', 'o', 'r', 'l', 9, '$', '1', ',', 32, 0, + /* 12902 */ 's', 'a', 'l', 'q', 9, '$', '1', ',', 32, 0, + /* 12912 */ 'r', 'c', 'l', 'q', 9, '$', '1', ',', 32, 0, + /* 12922 */ 's', 'h', 'l', 'q', 9, '$', '1', ',', 32, 0, + /* 12932 */ 'r', 'o', 'l', 'q', 9, '$', '1', ',', 32, 0, + /* 12942 */ 's', 'a', 'r', 'q', 9, '$', '1', ',', 32, 0, + /* 12952 */ 'r', 'c', 'r', 'q', 9, '$', '1', ',', 32, 0, + /* 12962 */ 's', 'h', 'r', 'q', 9, '$', '1', ',', 32, 0, + /* 12972 */ 'r', 'o', 'r', 'q', 9, '$', '1', ',', 32, 0, + /* 12982 */ 's', 'a', 'l', 'w', 9, '$', '1', ',', 32, 0, + /* 12992 */ 'r', 'c', 'l', 'w', 9, '$', '1', ',', 32, 0, + /* 13002 */ 's', 'h', 'l', 'w', 9, '$', '1', ',', 32, 0, + /* 13012 */ 'r', 'o', 'l', 'w', 9, '$', '1', ',', 32, 0, + /* 13022 */ 's', 'a', 'r', 'w', 9, '$', '1', ',', 32, 0, + /* 13032 */ 'r', 'c', 'r', 'w', 9, '$', '1', ',', 32, 0, + /* 13042 */ 's', 'h', 'r', 'w', 9, '$', '1', ',', 32, 0, + /* 13052 */ 'r', 'o', 'r', 'w', 9, '$', '1', ',', 32, 0, + /* 13062 */ 'm', 'o', 'v', 'a', 'b', 's', 'b', 9, '%', 'a', 'l', ',', 32, 0, + /* 13076 */ 's', 't', 'o', 's', 'b', 9, '%', 'a', 'l', ',', 32, 0, + /* 13088 */ 'o', 'u', 't', 'b', 9, '%', 'a', 'l', ',', 32, 0, + /* 13099 */ 'm', 'o', 'v', 'b', 9, '%', 'a', 'l', ',', 32, 0, + /* 13110 */ 's', 'a', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 13121 */ 'r', 'c', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 13132 */ 's', 'h', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 13143 */ 'r', 'o', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 13154 */ 's', 'a', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 13165 */ 'r', 'c', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 13176 */ 's', 'h', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 13187 */ 'r', 'o', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 13198 */ 's', 'h', 'l', 'd', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 13210 */ 's', 'h', 'r', 'd', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 13222 */ 's', 'a', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 13233 */ 'r', 'c', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 13244 */ 's', 'h', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 13255 */ 'r', 'o', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 13266 */ 's', 'a', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 13277 */ 'r', 'c', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 13288 */ 's', 'h', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 13299 */ 'r', 'o', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 13310 */ 's', 'h', 'l', 'd', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 13322 */ 's', 'h', 'r', 'd', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 13334 */ 's', 'a', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 13345 */ 'r', 'c', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 13356 */ 's', 'h', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 13367 */ 'r', 'o', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 13378 */ 's', 'a', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 13389 */ 'r', 'c', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 13400 */ 's', 'h', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 13411 */ 'r', 'o', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 13422 */ 's', 'h', 'l', 'd', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 13434 */ 's', 'h', 'r', 'd', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 13446 */ 's', 'a', 'l', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 13457 */ 'r', 'c', 'l', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 13468 */ 's', 'h', 'l', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 13479 */ 'r', 'o', 'l', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 13490 */ 's', 'a', 'r', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 13501 */ 'r', 'c', 'r', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 13512 */ 's', 'h', 'r', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 13523 */ 'r', 'o', 'r', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 13534 */ 'x', 'c', 'h', 'g', 'w', 9, '%', 'a', 'x', ',', 32, 0, + /* 13546 */ 'm', 'o', 'v', 'a', 'b', 's', 'w', 9, '%', 'a', 'x', ',', 32, 0, + /* 13560 */ 's', 't', 'o', 's', 'w', 9, '%', 'a', 'x', ',', 32, 0, + /* 13572 */ 'o', 'u', 't', 'w', 9, '%', 'a', 'x', ',', 32, 0, + /* 13583 */ 'm', 'o', 'v', 'w', 9, '%', 'a', 'x', ',', 32, 0, + /* 13594 */ 'x', 'c', 'h', 'g', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, + /* 13607 */ 'm', 'o', 'v', 'a', 'b', 's', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, + /* 13622 */ 's', 't', 'o', 's', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, + /* 13635 */ 'o', 'u', 't', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, + /* 13647 */ 'm', 'o', 'v', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, + /* 13659 */ 'x', 'c', 'h', 'g', 'q', 9, '%', 'r', 'a', 'x', ',', 32, 0, + /* 13672 */ 'm', 'o', 'v', 'a', 'b', 's', 'q', 9, '%', 'r', 'a', 'x', ',', 32, 0, + /* 13687 */ 's', 't', 'o', 's', 'q', 9, '%', 'r', 'a', 'x', ',', 32, 0, + /* 13700 */ 'm', 'o', 'v', 'q', 9, '%', 'r', 'a', 'x', ',', 32, 0, + /* 13712 */ 'i', 'n', 's', 'b', 9, '%', 'd', 'x', ',', 32, 0, + /* 13723 */ 'i', 'n', 's', 'l', 9, '%', 'd', 'x', ',', 32, 0, + /* 13734 */ 'i', 'n', 's', 'w', 9, '%', 'd', 'x', ',', 32, 0, + /* 13745 */ 'v', 'e', 'x', 'p', '2', 'p', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13761 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13779 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13796 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13815 */ 'v', 'm', 'i', 'n', 'p', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13830 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 'p', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13848 */ 'v', 'm', 'a', 'x', 'p', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13863 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13881 */ 'v', 'r', 'c', 'p', '2', '8', 's', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13898 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13917 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13934 */ 'v', 'c', 'o', 'm', 'i', 's', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13950 */ 'v', 'm', 'i', 'n', 's', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13965 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 's', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13983 */ 'v', 'm', 'a', 'x', 's', 'd', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 13998 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 's', 'i', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14017 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 's', 'i', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14036 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 'u', 's', 'i', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14056 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 'u', 's', 'i', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14076 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14095 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'd', 'q', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14114 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'd', 'q', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14134 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'u', 'd', 'q', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14154 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'q', 'q', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14173 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'q', 'q', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14192 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'q', 'q', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14212 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'u', 'q', 'q', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14232 */ 'v', 'c', 'v', 't', 'p', 'h', '2', 'p', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14250 */ 'v', 'e', 'x', 'p', '2', 'p', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14266 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14283 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14302 */ 'v', 'm', 'i', 'n', 'p', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14317 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 'p', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14335 */ 'v', 'm', 'a', 'x', 'p', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14350 */ 'v', 'r', 'c', 'p', '2', '8', 's', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14367 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14386 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14403 */ 'v', 'c', 'o', 'm', 'i', 's', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14419 */ 'v', 'm', 'i', 'n', 's', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14434 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 's', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14452 */ 'v', 'm', 'a', 'x', 's', 's', 9, '{', 's', 'a', 'e', '}', ',', 32, 0, + /* 14467 */ 'f', 'b', 'l', 'd', 9, 't', 'b', 'y', 't', 'e', 32, 'p', 't', 'r', 32, 0, + /* 14483 */ 'f', 'b', 's', 't', 'p', 9, 't', 'b', 'y', 't', 'e', 32, 'p', 't', 'r', 32, 0, + /* 14500 */ 'l', 'c', 'a', 'l', 'l', 'l', 9, '*', 0, + /* 14509 */ 'l', 'j', 'm', 'p', 'l', 9, '*', 0, + /* 14517 */ 'l', 'c', 'a', 'l', 'l', 'q', 9, '*', 0, + /* 14526 */ 'l', 'j', 'm', 'p', 'q', 9, '*', 0, + /* 14534 */ 'l', 'c', 'a', 'l', 'l', 'w', 9, '*', 0, + /* 14543 */ 'l', 'j', 'm', 'p', 'w', 9, '*', 0, + /* 14551 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, + /* 14582 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 14606 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 14631 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, + /* 14654 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, + /* 14677 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, + /* 14699 */ 'u', 'd', '0', 0, + /* 14703 */ 'x', 's', 'h', 'a', '1', 0, + /* 14709 */ 'f', 'l', 'd', '1', 0, + /* 14714 */ 'u', 'd', '1', 0, + /* 14718 */ 'f', 'p', 'r', 'e', 'm', '1', 0, + /* 14725 */ 'f', '2', 'x', 'm', '1', 0, + /* 14731 */ 'f', 'y', 'l', '2', 'x', 'p', '1', 0, + /* 14739 */ 'i', 'n', 't', '1', 0, + /* 14744 */ 'e', 'n', 'd', 'b', 'r', '3', '2', 0, + /* 14752 */ 'u', 'd', '2', 0, + /* 14756 */ 'f', 'l', 'd', 'l', 'g', '2', 0, + /* 14763 */ 'f', 'l', 'd', 'l', 'n', '2', 0, + /* 14770 */ 'i', 'n', 't', '3', 0, + /* 14775 */ 'e', 'n', 'd', 'b', 'r', '6', '4', 0, + /* 14783 */ 'r', 'e', 'x', '6', '4', 0, + /* 14789 */ 'd', 'a', 't', 'a', '1', '6', 0, + /* 14796 */ 'x', 's', 'h', 'a', '2', '5', '6', 0, + /* 14804 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 14817 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 14824 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 14834 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, + /* 14844 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 14859 */ 'a', 'a', 'a', 0, + /* 14863 */ 'd', 'a', 'a', 0, + /* 14867 */ 'x', 'c', 'r', 'y', 'p', 't', 'e', 'c', 'b', 0, + /* 14877 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'f', 'b', 0, + /* 14887 */ 'x', 'c', 'r', 'y', 'p', 't', 'o', 'f', 'b', 0, + /* 14897 */ 'x', 'l', 'a', 't', 'b', 0, + /* 14903 */ 'c', 'l', 'a', 'c', 0, + /* 14908 */ 's', 't', 'a', 'c', 0, + /* 14913 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'b', 'c', 0, + /* 14923 */ 'g', 'e', 't', 's', 'e', 'c', 0, + /* 14930 */ 's', 'a', 'l', 'c', 0, + /* 14935 */ 'c', 'l', 'c', 0, + /* 14939 */ 'c', 'm', 'c', 0, + /* 14943 */ 'r', 'd', 'p', 'm', 'c', 0, + /* 14949 */ 'v', 'm', 'f', 'u', 'n', 'c', 0, + /* 14956 */ 'r', 'd', 't', 's', 'c', 0, + /* 14962 */ 's', 't', 'c', 0, + /* 14966 */ 'c', 'p', 'u', 'i', 'd', 0, + /* 14972 */ 'c', 'l', 'd', 0, + /* 14976 */ 'x', 'e', 'n', 'd', 0, + /* 14981 */ 'c', 'l', 't', 'd', 0, + /* 14986 */ 's', 't', 'd', 0, + /* 14990 */ 'c', 'w', 't', 'd', 0, + /* 14995 */ 'w', 'b', 'i', 'n', 'v', 'd', 0, + /* 15002 */ 'w', 'b', 'n', 'o', 'i', 'n', 'v', 'd', 0, + /* 15011 */ 'f', 'l', 'd', 'l', '2', 'e', 0, + /* 15018 */ 'l', 'f', 'e', 'n', 'c', 'e', 0, + /* 15025 */ 'm', 'f', 'e', 'n', 'c', 'e', 0, + /* 15032 */ 's', 'f', 'e', 'n', 'c', 'e', 0, + /* 15039 */ 'f', 's', 'c', 'a', 'l', 'e', 0, + /* 15046 */ 'v', 'm', 'r', 'e', 's', 'u', 'm', 'e', 0, + /* 15055 */ 'r', 'e', 'p', 'n', 'e', 0, + /* 15061 */ 'x', 'a', 'c', 'q', 'u', 'i', 'r', 'e', 0, + /* 15070 */ 'x', 's', 't', 'o', 'r', 'e', 0, + /* 15077 */ 'x', 'r', 'e', 'l', 'e', 'a', 's', 'e', 0, + /* 15086 */ 'p', 'a', 'u', 's', 'e', 0, + /* 15092 */ 'l', 'e', 'a', 'v', 'e', 0, + /* 15098 */ 'v', 'm', 'x', 'o', 'f', 'f', 0, + /* 15105 */ 'l', 'a', 'h', 'f', 0, + /* 15110 */ 's', 'a', 'h', 'f', 0, + /* 15115 */ 'p', 'c', 'o', 'n', 'f', 'i', 'g', 0, + /* 15123 */ 'v', 'm', 'l', 'a', 'u', 'n', 'c', 'h', 0, + /* 15132 */ 'c', 'l', 'g', 'i', 0, + /* 15137 */ 's', 't', 'g', 'i', 0, + /* 15142 */ 'c', 'l', 'i', 0, + /* 15146 */ 'f', 'l', 'd', 'p', 'i', 0, + /* 15152 */ 's', 't', 'i', 0, + /* 15156 */ 'l', 'o', 'c', 'k', 0, + /* 15161 */ 'i', 'n', 'b', 9, '%', 'd', 'x', ',', 32, '%', 'a', 'l', 0, + /* 15174 */ 'p', 'u', 's', 'h', 'a', 'l', 0, + /* 15181 */ 'p', 'o', 'p', 'a', 'l', 0, + /* 15187 */ 'p', 'u', 's', 'h', 'f', 'l', 0, + /* 15194 */ 'p', 'o', 'p', 'f', 'l', 0, + /* 15200 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, + /* 15214 */ 'v', 'm', 'm', 'c', 'a', 'l', 'l', 0, + /* 15222 */ 'v', 'm', 'c', 'a', 'l', 'l', 0, + /* 15229 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 0, + /* 15237 */ 'v', 'z', 'e', 'r', 'o', 'a', 'l', 'l', 0, + /* 15246 */ 'i', 'r', 'e', 't', 'l', 0, + /* 15252 */ 'l', 'r', 'e', 't', 'l', 0, + /* 15258 */ 's', 'y', 's', 'r', 'e', 't', 'l', 0, + /* 15266 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'l', 0, + /* 15275 */ 'c', 'w', 't', 'l', 0, + /* 15280 */ 'm', 'o', 'n', 't', 'm', 'u', 'l', 0, + /* 15288 */ 'f', 'x', 'a', 'm', 0, + /* 15293 */ 'f', 'p', 'r', 'e', 'm', 0, + /* 15299 */ 'v', 'p', 'c', 'o', 'm', 0, + /* 15305 */ 'f', 's', 'e', 't', 'p', 'm', 0, + /* 15312 */ 'r', 's', 'm', 0, + /* 15316 */ 'f', 'p', 'a', 't', 'a', 'n', 0, + /* 15323 */ 'f', 'p', 't', 'a', 'n', 0, + /* 15329 */ 'f', 's', 'i', 'n', 0, + /* 15334 */ 'c', 'l', 'z', 'e', 'r', 'o', 0, + /* 15341 */ 'i', 'n', 't', 'o', 0, + /* 15346 */ 'c', 'q', 't', 'o', 0, + /* 15351 */ 'r', 'd', 't', 's', 'c', 'p', 0, + /* 15358 */ 'r', 'e', 'p', 0, + /* 15362 */ 'v', 'p', 'c', 'm', 'p', 0, + /* 15368 */ 'v', 'c', 'm', 'p', 0, + /* 15373 */ 'f', 'e', 'n', 'i', '8', '0', '8', '7', '_', 'n', 'o', 'p', 0, + /* 15386 */ 'f', 'd', 'i', 's', 'i', '8', '0', '8', '7', '_', 'n', 'o', 'p', 0, + /* 15400 */ 'f', 'n', 'o', 'p', 0, + /* 15405 */ 'f', 'c', 'o', 'm', 'p', 'p', 0, + /* 15412 */ 'f', 'u', 'c', 'o', 'm', 'p', 'p', 0, + /* 15420 */ 's', 'a', 'v', 'e', 'p', 'r', 'e', 'v', 's', 's', 'p', 0, + /* 15432 */ 'f', 'd', 'e', 'c', 's', 't', 'p', 0, + /* 15440 */ 'f', 'i', 'n', 'c', 's', 't', 'p', 0, + /* 15448 */ 'p', 'u', 's', 'h', 'f', 'q', 0, + /* 15455 */ 'p', 'o', 'p', 'f', 'q', 0, + /* 15461 */ 'i', 'r', 'e', 't', 'q', 0, + /* 15467 */ 'l', 'r', 'e', 't', 'q', 0, + /* 15473 */ 's', 'y', 's', 'r', 'e', 't', 'q', 0, + /* 15481 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'q', 0, + /* 15490 */ 'c', 'l', 't', 'q', 0, + /* 15495 */ 'v', 'z', 'e', 'r', 'o', 'u', 'p', 'p', 'e', 'r', 0, + /* 15506 */ 's', 'y', 's', 'e', 'n', 't', 'e', 'r', 0, + /* 15515 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 0, + /* 15523 */ 'r', 'd', 'm', 's', 'r', 0, + /* 15529 */ 'w', 'r', 'm', 's', 'r', 0, + /* 15535 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 't', 'r', 0, + /* 15545 */ 'a', 'a', 's', 0, + /* 15549 */ 'd', 'a', 's', 0, + /* 15553 */ 'f', 'a', 'b', 's', 0, + /* 15558 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'c', 's', 0, + /* 15568 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'c', 's', 0, + /* 15578 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'd', 's', 0, + /* 15588 */ 'p', 'o', 'p', 'l', 9, '%', 'd', 's', 0, + /* 15597 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'd', 's', 0, + /* 15607 */ 'p', 'o', 'p', 'w', 9, '%', 'd', 's', 0, + /* 15616 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'e', 's', 0, + /* 15626 */ 'p', 'o', 'p', 'l', 9, '%', 'e', 's', 0, + /* 15635 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'e', 's', 0, + /* 15645 */ 'p', 'o', 'p', 'w', 9, '%', 'e', 's', 0, + /* 15654 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'f', 's', 0, + /* 15664 */ 'p', 'o', 'p', 'l', 9, '%', 'f', 's', 0, + /* 15673 */ 'p', 'u', 's', 'h', 'q', 9, '%', 'f', 's', 0, + /* 15683 */ 'p', 'o', 'p', 'q', 9, '%', 'f', 's', 0, + /* 15692 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'f', 's', 0, + /* 15702 */ 'p', 'o', 'p', 'w', 9, '%', 'f', 's', 0, + /* 15711 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'g', 's', 0, + /* 15721 */ 'p', 'o', 'p', 'l', 9, '%', 'g', 's', 0, + /* 15730 */ 'p', 'u', 's', 'h', 'q', 9, '%', 'g', 's', 0, + /* 15740 */ 'p', 'o', 'p', 'q', 9, '%', 'g', 's', 0, + /* 15749 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'g', 's', 0, + /* 15759 */ 'p', 'o', 'p', 'w', 9, '%', 'g', 's', 0, + /* 15768 */ 's', 'w', 'a', 'p', 'g', 's', 0, + /* 15775 */ 'f', 'c', 'h', 's', 0, + /* 15780 */ 'e', 'n', 'c', 'l', 's', 0, + /* 15786 */ 'f', 'e', 'm', 'm', 's', 0, + /* 15792 */ 'f', 'c', 'o', 's', 0, + /* 15797 */ 'f', 's', 'i', 'n', 'c', 'o', 's', 0, + /* 15805 */ 'p', 'u', 's', 'h', 'l', 9, '%', 's', 's', 0, + /* 15815 */ 'p', 'o', 'p', 'l', 9, '%', 's', 's', 0, + /* 15824 */ 'p', 'u', 's', 'h', 'w', 9, '%', 's', 's', 0, + /* 15834 */ 'p', 'o', 'p', 'w', 9, '%', 's', 's', 0, + /* 15843 */ 'c', 'l', 't', 's', 0, + /* 15848 */ 'f', 'l', 'd', 'l', '2', 't', 0, + /* 15855 */ 'f', 'x', 't', 'r', 'a', 'c', 't', 0, + /* 15863 */ 'm', 'w', 'a', 'i', 't', 0, + /* 15869 */ 'f', 'n', 'i', 'n', 'i', 't', 0, + /* 15876 */ 'h', 'l', 't', 0, + /* 15880 */ 'f', 'r', 'n', 'd', 'i', 'n', 't', 0, + /* 15888 */ 'f', 's', 'q', 'r', 't', 0, + /* 15894 */ 'x', 't', 'e', 's', 't', 0, + /* 15900 */ 'f', 't', 's', 't', 0, + /* 15905 */ 'e', 'n', 'c', 'l', 'u', 0, + /* 15911 */ 'r', 'd', 'p', 'k', 'r', 'u', 0, + /* 15918 */ 'w', 'r', 'p', 'k', 'r', 'u', 0, + /* 15925 */ 'x', 'g', 'e', 't', 'b', 'v', 0, + /* 15932 */ 'x', 's', 'e', 't', 'b', 'v', 0, + /* 15939 */ 'e', 'n', 'c', 'l', 'v', 0, + /* 15945 */ 'p', 'u', 's', 'h', 'a', 'w', 0, + /* 15952 */ 'p', 'o', 'p', 'a', 'w', 0, + /* 15958 */ 'p', 'u', 's', 'h', 'f', 'w', 0, + /* 15965 */ 'p', 'o', 'p', 'f', 'w', 0, + /* 15971 */ 'c', 'b', 't', 'w', 0, + /* 15976 */ 'i', 'r', 'e', 't', 'w', 0, + /* 15982 */ 'l', 'r', 'e', 't', 'w', 0, + /* 15988 */ 'f', 'y', 'l', '2', 'x', 0, + /* 15994 */ 'f', 'n', 's', 't', 's', 'w', 9, '%', 'a', 'x', 0, + /* 16005 */ 'i', 'n', 'w', 9, '%', 'd', 'x', ',', 32, '%', 'a', 'x', 0, + /* 16018 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, '%', 'e', 'a', 'x', 0, + /* 16030 */ 'v', 'm', 's', 'a', 'v', 'e', 9, '%', 'e', 'a', 'x', 0, + /* 16042 */ 'v', 'm', 'r', 'u', 'n', 9, '%', 'e', 'a', 'x', 0, + /* 16053 */ 's', 'k', 'i', 'n', 'i', 't', 9, '%', 'e', 'a', 'x', 0, + /* 16065 */ 'i', 'n', 'l', 9, '%', 'd', 'x', ',', 32, '%', 'e', 'a', 'x', 0, + /* 16079 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, '%', 'r', 'a', 'x', 0, + /* 16091 */ 'v', 'm', 's', 'a', 'v', 'e', 9, '%', 'r', 'a', 'x', 0, + /* 16103 */ 'v', 'm', 'r', 'u', 'n', 9, '%', 'r', 'a', 'x', 0, + /* 16114 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, '%', 'e', 'a', 'x', ',', 32, '%', 'e', 'c', 'x', 0, + /* 16133 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, '%', 'r', 'a', 'x', ',', 32, '%', 'e', 'c', 'x', 0, + /* 16152 */ 'o', 'u', 't', 'b', 9, '%', 'a', 'l', ',', 32, '%', 'd', 'x', 0, + /* 16166 */ 'o', 'u', 't', 'w', 9, '%', 'a', 'x', ',', 32, '%', 'd', 'x', 0, + /* 16180 */ 'o', 'u', 't', 'l', 9, '%', 'e', 'a', 'x', ',', 32, '%', 'd', 'x', 0, + /* 16195 */ 'f', 'n', 'c', 'l', 'e', 'x', 0, + /* 16202 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 'x', 0, + /* 16211 */ 'm', 'w', 'a', 'i', 't', 'x', 0, + /* 16218 */ 's', 'e', 't', 's', 's', 'b', 's', 'y', 0, + /* 16227 */ 'f', 'l', 'd', 'z', 0, + }; +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 14825U, // DBG_VALUE + 14835U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 14818U, // BUNDLE + 14845U, // LIFETIME_START + 14805U, // LIFETIME_END + 0U, // STACKMAP + 15201U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 14632U, // PATCHABLE_FUNCTION_ENTER + 14552U, // PATCHABLE_RET + 14678U, // PATCHABLE_FUNCTION_EXIT + 14655U, // PATCHABLE_TAIL_CALL + 14607U, // PATCHABLE_EVENT_CALL + 14583U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // AVX1_SETALLONES + 0U, // AVX2_SETALLONES + 0U, // AVX512_128_SET0 + 0U, // AVX512_256_SET0 + 0U, // AVX512_512_SET0 + 0U, // AVX512_512_SETALLONES + 0U, // AVX512_512_SEXT_MASK_32 + 0U, // AVX512_512_SEXT_MASK_64 + 0U, // AVX512_FsFLD0SD + 0U, // AVX512_FsFLD0SS + 0U, // AVX_SET0 + 0U, // KSET0D + 0U, // KSET0Q + 0U, // KSET0W + 0U, // KSET1D + 0U, // KSET1Q + 0U, // KSET1W + 0U, // MMX_SET0 + 0U, // V_SET0 + 0U, // V_SETALLONES + 14860U, // AAA + 18260U, // AAD8i8 + 22553U, // AAM8i8 + 15546U, // AAS + 15554U, // ABS_F + 0U, // ABS_Fp32 + 0U, // ABS_Fp64 + 0U, // ABS_Fp80 + 2124537U, // ADC16i16 + 4238073U, // ADC16mi + 4238073U, // ADC16mi8 + 4238073U, // ADC16mr + 6351609U, // ADC16ri + 6351609U, // ADC16ri8 + 6367993U, // ADC16rm + 6351609U, // ADC16rr + 8448761U, // ADC16rr_REV + 10507174U, // ADC32i32 + 12620710U, // ADC32mi + 12620710U, // ADC32mi8 + 12620710U, // ADC32mr + 6345638U, // ADC32ri + 6345638U, // ADC32ri8 + 283202470U, // ADC32rm + 6345638U, // ADC32rr + 8442790U, // ADC32rr_REV + 16800213U, // ADC64i32 + 18913749U, // ADC64mi32 + 18913749U, // ADC64mi8 + 18913749U, // ADC64mr + 6347221U, // ADC64ri32 + 6347221U, // ADC64ri8 + 283220437U, // ADC64rm + 6347221U, // ADC64rr + 8444373U, // ADC64rr_REV + 20988865U, // ADC8i8 + 23102401U, // ADC8mi + 23102401U, // ADC8mi8 + 23102401U, // ADC8mr + 6341569U, // ADC8ri + 6341569U, // ADC8ri8 + 6407105U, // ADC8rm + 6341569U, // ADC8rr + 8438721U, // ADC8rr_REV + 551638976U, // ADCX32rm + 8443840U, // ADCX32rr + 551657684U, // ADCX64rm + 8446164U, // ADCX64rr + 2124579U, // ADD16i16 + 4238115U, // ADD16mi + 4238115U, // ADD16mi8 + 4238115U, // ADD16mr + 6351651U, // ADD16ri + 6351651U, // ADD16ri8 + 6368035U, // ADD16rm + 6351651U, // ADD16rr + 8448803U, // ADD16rr_REV + 10507240U, // ADD32i32 + 12620776U, // ADD32mi + 12620776U, // ADD32mi8 + 12620776U, // ADD32mr + 6345704U, // ADD32ri + 6345704U, // ADD32ri8 + 283202536U, // ADD32rm + 6345704U, // ADD32rr + 8442856U, // ADD32rr_REV + 16800337U, // ADD64i32 + 18913873U, // ADD64mi32 + 18913873U, // ADD64mi8 + 18913873U, // ADD64mr + 6347345U, // ADD64ri32 + 6347345U, // ADD64ri8 + 283220561U, // ADD64rm + 6347345U, // ADD64rr + 8444497U, // ADD64rr_REV + 20988900U, // ADD8i8 + 23102436U, // ADD8mi + 23102436U, // ADD8mi8 + 23102436U, // ADD8mr + 6341604U, // ADD8ri + 6341604U, // ADD8ri8 + 6407140U, // ADD8rm + 6341604U, // ADD8rr + 8438756U, // ADD8rr_REV + 8522549U, // ADDPDrm + 8440629U, // ADDPDrr + 8528946U, // ADDPSrm + 8447026U, // ADDPSrr + 551702253U, // ADDSDrm + 551702253U, // ADDSDrm_Int + 8441581U, // ADDSDrr + 8441581U, // ADDSDrr_Int + 551725033U, // ADDSSrm + 551725033U, // ADDSSrm_Int + 8447977U, // ADDSSrr + 8447977U, // ADDSSrr_Int + 8522422U, // ADDSUBPDrm + 8440502U, // ADDSUBPDrr + 8528819U, // ADDSUBPSrm + 8446899U, // ADDSUBPSrr + 188799U, // ADD_F32m + 201703U, // ADD_F64m + 221574U, // ADD_FI16m + 234478U, // ADD_FI32m + 22676U, // ADD_FPrST0 + 18342U, // ADD_FST0r + 0U, // ADD_Fp32 + 0U, // ADD_Fp32m + 0U, // ADD_Fp64 + 0U, // ADD_Fp64m + 0U, // ADD_Fp64m32 + 0U, // ADD_Fp80 + 0U, // ADD_Fp80m32 + 0U, // ADD_Fp80m64 + 0U, // ADD_FpI16m32 + 0U, // ADD_FpI16m64 + 0U, // ADD_FpI16m80 + 0U, // ADD_FpI32m32 + 0U, // ADD_FpI32m64 + 0U, // ADD_FpI32m80 + 28967U, // ADD_FrST0 + 551638997U, // ADOX32rm + 8443861U, // ADOX32rr + 551657705U, // ADOX64rm + 8446185U, // ADOX64rr + 8644979U, // AESDECLASTrm + 8448371U, // AESDECLASTrr + 8636163U, // AESDECrm + 8439555U, // AESDECrr + 8644992U, // AESENCLASTrm + 8448384U, // AESENCLASTrr + 8636189U, // AESENCrm + 8439581U, // AESENCrr + 263956U, // AESIMCrm + 551831316U, // AESIMCrr + 830777754U, // AESKEYGENASSIST128rm + 283437466U, // AESKEYGENASSIST128rr + 2124626U, // AND16i16 + 4238162U, // AND16mi + 4238162U, // AND16mi8 + 4238162U, // AND16mr + 6351698U, // AND16ri + 6351698U, // AND16ri8 + 6368082U, // AND16rm + 6351698U, // AND16rr + 8448850U, // AND16rr_REV + 10507293U, // AND32i32 + 12620829U, // AND32mi + 12620829U, // AND32mi8 + 12620829U, // AND32mr + 6345757U, // AND32ri + 6345757U, // AND32ri8 + 283202589U, // AND32rm + 6345757U, // AND32rr + 8442909U, // AND32rr_REV + 16800448U, // AND64i32 + 18913984U, // AND64mi32 + 18913984U, // AND64mi8 + 18913984U, // AND64mr + 6347456U, // AND64ri32 + 6347456U, // AND64ri8 + 283220672U, // AND64rm + 6347456U, // AND64rr + 8444608U, // AND64rr_REV + 20988922U, // AND8i8 + 23102458U, // AND8mi + 23102458U, // AND8mi8 + 23102458U, // AND8mr + 6341626U, // AND8ri + 6341626U, // AND8ri8 + 6407162U, // AND8rm + 6341626U, // AND8rr + 8438778U, // AND8rr_REV + 283202964U, // ANDN32rm + 811652500U, // ANDN32rr + 283221318U, // ANDN64rm + 811654470U, // ANDN64rr + 8522824U, // ANDNPDrm + 8440904U, // ANDNPDrr + 8529273U, // ANDNPSrm + 8447353U, // ANDNPSrr + 8522598U, // ANDPDrm + 8440678U, // ANDPDrr + 8529018U, // ANDPSrm + 8447098U, // ANDPSrr + 4232691U, // ARPL16mr + 551835123U, // ARPL16rr + 832902782U, // BEXTR32rm + 811652734U, // BEXTR32rr + 835002024U, // BEXTR64rm + 811654824U, // BEXTR64rr + 832902782U, // BEXTRI32mi + 811652734U, // BEXTRI32ri + 835002024U, // BEXTRI64mi + 811654824U, // BEXTRI64ri + 551900475U, // BLCFILL32rm + 551834939U, // BLCFILL32rr + 551918777U, // BLCFILL64rm + 551836857U, // BLCFILL64rr + 551900381U, // BLCI32rm + 551834845U, // BLCI32rr + 551918694U, // BLCI64rm + 551836774U, // BLCI64rr + 551900089U, // BLCIC32rm + 551834553U, // BLCIC32rr + 551918049U, // BLCIC64rm + 551836129U, // BLCIC64rr + 551900415U, // BLCMSK32rm + 551834879U, // BLCMSK32rr + 551918724U, // BLCMSK64rm + 551836804U, // BLCMSK64rr + 551900839U, // BLCS32rm + 551835303U, // BLCS32rr + 551919313U, // BLCS64rm + 551837393U, // BLCS64rr + 568707958U, // BLENDPDrmi + 1088818038U, // BLENDPDrri + 568714378U, // BLENDPSrmi + 1088824458U, // BLENDPSrri + 8532389U, // BLENDVPDrm0 + 8450469U, // BLENDVPDrr0 + 8532406U, // BLENDVPSrm0 + 8450486U, // BLENDVPSrr0 + 551900485U, // BLSFILL32rm + 551834949U, // BLSFILL32rr + 551918787U, // BLSFILL64rm + 551836867U, // BLSFILL64rr + 551900395U, // BLSI32rm + 551834859U, // BLSI32rr + 551918708U, // BLSI64rm + 551836788U, // BLSI64rr + 551900097U, // BLSIC32rm + 551834561U, // BLSIC32rr + 551918057U, // BLSIC64rm + 551836137U, // BLSIC64rr + 551900424U, // BLSMSK32rm + 551834888U, // BLSMSK32rr + 551918733U, // BLSMSK64rm + 551836813U, // BLSMSK64rr + 551900779U, // BLSR32rm + 551835243U, // BLSR32rr + 551919234U, // BLSR64rm + 551837314U, // BLSR64rr + 414636U, // BNDCL32rm + 551834540U, // BNDCL32rr + 414636U, // BNDCL64rm + 551834540U, // BNDCL64rr + 415819U, // BNDCN32rm + 551835723U, // BNDCN32rr + 415819U, // BNDCN64rm + 551835723U, // BNDCN64rr + 420276U, // BNDCU32rm + 551840180U, // BNDCU32rr + 420276U, // BNDCU64rm + 551840180U, // BNDCU64rr + 421867U, // BNDLDXrm + 414548U, // BNDMK32rm + 414548U, // BNDMK64rm + 18917897U, // BNDMOV32mr + 551922185U, // BNDMOV32rm + 33597961U, // BNDMOV64mr + 272905U, // BNDMOV64rm + 551840265U, // BNDMOVrr + 551840265U, // BNDMOVrr_REV + 35696742U, // BNDSTXmr + 1356876031U, // BOUNDS16rm + 1625311487U, // BOUNDS32rm + 437231U, // BSF16rm + 551840751U, // BSF16rr + 551900344U, // BSF32rm + 551834808U, // BSF32rr + 551918645U, // BSF64rm + 551836725U, // BSF64rr + 437666U, // BSR16rm + 551841186U, // BSR16rr + 551900773U, // BSR32rm + 551835237U, // BSR32rr + 551919228U, // BSR64rm + 551837308U, // BSR64rr + 27908U, // BSWAP16r_BAD + 21937U, // BSWAP32r + 23920U, // BSWAP64r + 4239024U, // BT16mi8 + 4239024U, // BT16mr + 551841456U, // BT16ri8 + 551841456U, // BT16rr + 12621598U, // BT32mi8 + 12621598U, // BT32mr + 551835422U, // BT32ri8 + 551835422U, // BT32rr + 18915152U, // BT64mi8 + 18915152U, // BT64mr + 551837520U, // BT64ri8 + 551837520U, // BT64rr + 4238098U, // BTC16mi8 + 4238098U, // BTC16mr + 6351634U, // BTC16ri8 + 6351634U, // BTC16rr + 12620760U, // BTC32mi8 + 12620760U, // BTC32mr + 6345688U, // BTC32ri8 + 6345688U, // BTC32rr + 18913792U, // BTC64mi8 + 18913792U, // BTC64mr + 6347264U, // BTC64ri8 + 6347264U, // BTC64rr + 4238769U, // BTR16mi8 + 4238769U, // BTR16mr + 6352305U, // BTR16ri8 + 6352305U, // BTR16rr + 12621426U, // BTR32mi8 + 12621426U, // BTR32mr + 6346354U, // BTR32ri8 + 6346354U, // BTR32rr + 18914962U, // BTR64mi8 + 18914962U, // BTR64mr + 6348434U, // BTR64ri8 + 6348434U, // BTR64rr + 4238966U, // BTS16mi8 + 4238966U, // BTS16mr + 6352502U, // BTS16ri8 + 6352502U, // BTS16rr + 12621577U, // BTS32mi8 + 12621577U, // BTS32mr + 6346505U, // BTS32ri8 + 6346505U, // BTS32rr + 18915129U, // BTS64mi8 + 18915129U, // BTS64mr + 6348601U, // BTS64ri8 + 6348601U, // BTS64rr + 832902372U, // BZHI32rm + 811652324U, // BZHI32rr + 835001453U, // BZHI64rm + 811654253U, // BZHI64rr + 227528U, // CALL16m + 227528U, // CALL16m_NT + 30920U, // CALL16r + 30920U, // CALL16r_NT + 243878U, // CALL32m + 243878U, // CALL32m_NT + 30886U, // CALL32r + 30886U, // CALL32r_NT + 456887U, // CALL64m + 456887U, // CALL64m_NT + 466098U, // CALL64pcrel32 + 30903U, // CALL64r + 30903U, // CALL64r_NT + 470120U, // CALLpcrel16 + 464180U, // CALLpcrel32 + 15972U, // CBW + 14982U, // CDQ + 15491U, // CDQE + 15776U, // CHS_F + 0U, // CHS_Fp32 + 0U, // CHS_Fp64 + 0U, // CHS_Fp80 + 14904U, // CLAC + 14936U, // CLC + 14973U, // CLD + 479759U, // CLDEMOTE + 479872U, // CLFLUSH + 485710U, // CLFLUSHOPT + 15133U, // CLGI + 15143U, // CLI + 241839U, // CLRSSBSY + 15844U, // CLTS + 476848U, // CLWB + 15335U, // CLZEROr + 14940U, // CMC + 8464973U, // CMOVA16rm + 8448589U, // CMOVA16rr + 551637865U, // CMOVA32rm + 8442729U, // CMOVA32rr + 551655804U, // CMOVA64rm + 8444284U, // CMOVA64rr + 8465331U, // CMOVAE16rm + 8448947U, // CMOVAE16rr + 551638083U, // CMOVAE32rm + 8442947U, // CMOVAE32rr + 551656375U, // CMOVAE64rm + 8444855U, // CMOVAE64rr + 8465107U, // CMOVB16rm + 8448723U, // CMOVB16rr + 551637910U, // CMOVB32rm + 8442774U, // CMOVB32rr + 551655855U, // CMOVB64rm + 8444335U, // CMOVB64rr + 8465340U, // CMOVBE16rm + 8448956U, // CMOVBE16rr + 551638092U, // CMOVBE32rm + 8442956U, // CMOVBE32rr + 551656384U, // CMOVBE64rm + 8444864U, // CMOVBE64rr + 37769640U, // CMOVBE_F + 0U, // CMOVBE_Fp32 + 0U, // CMOVBE_Fp64 + 0U, // CMOVBE_Fp80 + 37766817U, // CMOVB_F + 0U, // CMOVB_Fp32 + 0U, // CMOVB_Fp64 + 0U, // CMOVB_Fp80 + 8465376U, // CMOVE16rm + 8448992U, // CMOVE16rr + 551638192U, // CMOVE32rm + 8443056U, // CMOVE32rr + 551656493U, // CMOVE64rm + 8444973U, // CMOVE64rr + 37769780U, // CMOVE_F + 0U, // CMOVE_Fp32 + 0U, // CMOVE_Fp64 + 0U, // CMOVE_Fp80 + 8465429U, // CMOVG16rm + 8449045U, // CMOVG16rr + 551638222U, // CMOVG32rm + 8443086U, // CMOVG32rr + 551656535U, // CMOVG64rm + 8445015U, // CMOVG64rr + 8465349U, // CMOVGE16rm + 8448965U, // CMOVGE16rr + 551638101U, // CMOVGE32rm + 8442965U, // CMOVGE32rr + 551656393U, // CMOVGE64rm + 8444873U, // CMOVGE64rr + 8465573U, // CMOVL16rm + 8449189U, // CMOVL16rr + 551638397U, // CMOVL32rm + 8443261U, // CMOVL32rr + 551656717U, // CMOVL64rm + 8445197U, // CMOVL64rr + 8465358U, // CMOVLE16rm + 8448974U, // CMOVLE16rr + 551638110U, // CMOVLE32rm + 8442974U, // CMOVLE32rr + 551656402U, // CMOVLE64rm + 8444882U, // CMOVLE64rr + 37769623U, // CMOVNBE_F + 0U, // CMOVNBE_Fp32 + 0U, // CMOVNBE_Fp64 + 0U, // CMOVNBE_Fp80 + 37766372U, // CMOVNB_F + 0U, // CMOVNB_Fp32 + 0U, // CMOVNB_Fp64 + 0U, // CMOVNB_Fp80 + 8465367U, // CMOVNE16rm + 8448983U, // CMOVNE16rr + 551638119U, // CMOVNE32rm + 8442983U, // CMOVNE32rr + 551656411U, // CMOVNE64rm + 8444891U, // CMOVNE64rr + 37769713U, // CMOVNE_F + 0U, // CMOVNE_Fp32 + 0U, // CMOVNE_Fp64 + 0U, // CMOVNE_Fp80 + 8465651U, // CMOVNO16rm + 8449267U, // CMOVNO16rr + 551638432U, // CMOVNO32rm + 8443296U, // CMOVNO32rr + 551656799U, // CMOVNO64rm + 8445279U, // CMOVNO64rr + 8465691U, // CMOVNP16rm + 8449307U, // CMOVNP16rr + 551638494U, // CMOVNP32rm + 8443358U, // CMOVNP32rr + 551656839U, // CMOVNP64rm + 8445319U, // CMOVNP64rr + 37775803U, // CMOVNP_F + 0U, // CMOVNP_Fp32 + 0U, // CMOVNP_Fp64 + 0U, // CMOVNP_Fp80 + 8465992U, // CMOVNS16rm + 8449608U, // CMOVNS16rr + 551638733U, // CMOVNS32rm + 8443597U, // CMOVNS32rr + 551657198U, // CMOVNS64rm + 8445678U, // CMOVNS64rr + 8465660U, // CMOVO16rm + 8449276U, // CMOVO16rr + 551638441U, // CMOVO32rm + 8443305U, // CMOVO32rr + 551656808U, // CMOVO64rm + 8445288U, // CMOVO64rr + 8465712U, // CMOVP16rm + 8449328U, // CMOVP16rr + 551638545U, // CMOVP32rm + 8443409U, // CMOVP32rr + 551656877U, // CMOVP64rm + 8445357U, // CMOVP64rr + 37775842U, // CMOVP_F + 0U, // CMOVP_Fp32 + 0U, // CMOVP_Fp64 + 0U, // CMOVP_Fp80 + 8466079U, // CMOVS16rm + 8449695U, // CMOVS16rr + 551638806U, // CMOVS32rm + 8443670U, // CMOVS32rr + 551657279U, // CMOVS64rm + 8445759U, // CMOVS64rr + 2125070U, // CMP16i16 + 4238606U, // CMP16mi + 4238606U, // CMP16mi8 + 4238606U, // CMP16mr + 551841038U, // CMP16ri + 551841038U, // CMP16ri8 + 437518U, // CMP16rm + 551841038U, // CMP16rr + 551841038U, // CMP16rr_REV + 10507712U, // CMP32i32 + 12621248U, // CMP32mi + 12621248U, // CMP32mi8 + 12621248U, // CMP32mr + 551835072U, // CMP32ri + 551835072U, // CMP32ri8 + 551900608U, // CMP32rm + 551835072U, // CMP32rr + 551835072U, // CMP32rr_REV + 16801153U, // CMP64i32 + 18914689U, // CMP64mi32 + 18914689U, // CMP64mi8 + 18914689U, // CMP64mr + 551837057U, // CMP64ri32 + 551837057U, // CMP64ri8 + 551918977U, // CMP64rm + 551837057U, // CMP64rr + 551837057U, // CMP64rr_REV + 20989167U, // CMP8i8 + 23102703U, // CMP8mi + 23102703U, // CMP8mi8 + 23102703U, // CMP8mr + 551830767U, // CMP8ri + 551830767U, // CMP8ri8 + 492783U, // CMP8rm + 551830767U, // CMP8rr + 551830767U, // CMP8rr_REV + 1919417349U, // CMPPDrmi + 568708192U, // CMPPDrmi_alt + 1114127365U, // CMPPDrri + 1088818272U, // CMPPDrri_alt + 1921514501U, // CMPPSrmi + 568714649U, // CMPPSrmi_alt + 1116224517U, // CMPPSrri + 1088824729U, // CMPPSrri_alt + 2162705875U, // CMPSB + 2460482565U, // CMPSDrm + 2460482565U, // CMPSDrm_Int + 851824504U, // CMPSDrm_alt + 1118321669U, // CMPSDrr + 1118321669U, // CMPSDrr_Int + 1088819064U, // CMPSDrr_alt + 2699597526U, // CMPSL + 2968051447U, // CMPSQ + 3269983237U, // CMPSSrm + 3269983237U, // CMPSSrm_Int + 856025225U, // CMPSSrm_alt + 1122515973U, // CMPSSrr + 1122515973U, // CMPSSrr_Int + 1088825481U, // CMPSSrr_alt + 3504942673U, // CMPSW + 607124U, // CMPXCHG16B + 4238339U, // CMPXCHG16rm + 551840771U, // CMPXCHG16rr + 12620996U, // CMPXCHG32rm + 551834820U, // CMPXCHG32rr + 18914369U, // CMPXCHG64rm + 551836737U, // CMPXCHG64rr + 443296U, // CMPXCHG8B + 23102520U, // CMPXCHG8rm + 551830584U, // CMPXCHG8rr + 552177472U, // COMISDrm + 552177472U, // COMISDrm_Int + 551833408U, // COMISDrr + 551833408U, // COMISDrr_Int + 552200274U, // COMISSrm + 552200274U, // COMISSrm_Int + 551839826U, // COMISSrr + 551839826U, // COMISSrr_Int + 22707U, // COMP_FST0r + 21186U, // COM_FIPr + 21129U, // COM_FIr + 22558U, // COM_FST0r + 15793U, // COS_F + 0U, // COS_Fp32 + 0U, // COS_Fp64 + 0U, // COS_Fp80 + 14967U, // CPUID + 15347U, // CQO + 6367761U, // CRC32r32m16 + 283202395U, // CRC32r32m32 + 6407011U, // CRC32r32m8 + 6351377U, // CRC32r32r16 + 6345563U, // CRC32r32r32 + 6341475U, // CRC32r32r8 + 283220262U, // CRC32r64m64 + 6407011U, // CRC32r64m8 + 6347046U, // CRC32r64r64 + 6341475U, // CRC32r64r8 + 551913949U, // CVTDQ2PDrm + 551832029U, // CVTDQ2PDrr + 271085U, // CVTDQ2PSrm + 551838445U, // CVTDQ2PSrr + 662035U, // CVTPD2DQrm + 551836179U, // CVTPD2DQrr + 664237U, // CVTPD2PSrm + 551838381U, // CVTPD2PSrr + 662067U, // CVTPS2DQrm + 551836211U, // CVTPS2DQrr + 552176139U, // CVTPS2PDrm + 551832075U, // CVTPS2PDrr + 552178433U, // CVTSD2SI64rm_Int + 551834369U, // CVTSD2SI64rr_Int + 552178433U, // CVTSD2SIrm_Int + 551834369U, // CVTSD2SIrr_Int + 552183644U, // CVTSD2SSrm + 551708508U, // CVTSD2SSrm_Int + 551839580U, // CVTSD2SSrr + 8447836U, // CVTSD2SSrr_Int + 551900203U, // CVTSI2SDrm + 551638059U, // CVTSI2SDrm_Int + 551834667U, // CVTSI2SDrr + 8442923U, // CVTSI2SDrr_Int + 551900907U, // CVTSI2SSrm + 551638763U, // CVTSI2SSrm_Int + 551835371U, // CVTSI2SSrr + 8443627U, // CVTSI2SSrr_Int + 551918392U, // CVTSI642SDrm + 551656248U, // CVTSI642SDrm_Int + 551836472U, // CVTSI642SDrr + 8444728U, // CVTSI642SDrr_Int + 551919359U, // CVTSI642SSrm + 551657215U, // CVTSI642SSrm_Int + 551837439U, // CVTSI642SSrr + 8445695U, // CVTSI642SSrr_Int + 552193625U, // CVTSS2SDrm + 551718489U, // CVTSS2SDrm_Int + 551833177U, // CVTSS2SDrr + 8441433U, // CVTSS2SDrr_Int + 552194840U, // CVTSS2SI64rm_Int + 551834392U, // CVTSS2SI64rr_Int + 552194840U, // CVTSS2SIrm_Int + 551834392U, // CVTSS2SIrr_Int + 662023U, // CVTTPD2DQrm + 551836167U, // CVTTPD2DQrr + 662055U, // CVTTPS2DQrm + 551836199U, // CVTTPS2DQrr + 552178421U, // CVTTSD2SI64rm + 552178421U, // CVTTSD2SI64rm_Int + 551834357U, // CVTTSD2SI64rr + 551834357U, // CVTTSD2SI64rr_Int + 552178421U, // CVTTSD2SIrm + 552178421U, // CVTTSD2SIrm_Int + 551834357U, // CVTTSD2SIrr + 551834357U, // CVTTSD2SIrr_Int + 552194828U, // CVTTSS2SI64rm + 552194828U, // CVTTSS2SI64rm_Int + 551834380U, // CVTTSS2SI64rr + 551834380U, // CVTTSS2SI64rr_Int + 552194828U, // CVTTSS2SIrm + 552194828U, // CVTTSS2SIrm_Int + 551834380U, // CVTTSS2SIrr + 551834380U, // CVTTSS2SIrr_Int + 14991U, // CWD + 15276U, // CWDE + 14864U, // DAA + 15550U, // DAS + 14790U, // DATA16_PREFIX + 224006U, // DEC16m + 27398U, // DEC16r + 27398U, // DEC16r_alt + 234419U, // DEC32m + 21427U, // DEC32r + 21427U, // DEC32r_alt + 448987U, // DEC64m + 23003U, // DEC64r + 476103U, // DEC8m + 17351U, // DEC8r + 225170U, // DIV16m + 28562U, // DIV16r + 235413U, // DIV32m + 22421U, // DIV32r + 450645U, // DIV64m + 24661U, // DIV64r + 476827U, // DIV8m + 18075U, // DIV8r + 8523071U, // DIVPDrm + 8441151U, // DIVPDrr + 8529568U, // DIVPSrm + 8447648U, // DIVPSrr + 190174U, // DIVR_F32m + 202374U, // DIVR_F64m + 222950U, // DIVR_FI16m + 235150U, // DIVR_FI32m + 22815U, // DIVR_FPrST0 + 24937U, // DIVR_FST0r + 0U, // DIVR_Fp32m + 0U, // DIVR_Fp64m + 0U, // DIVR_Fp64m32 + 0U, // DIVR_Fp80m32 + 0U, // DIVR_Fp80m64 + 0U, // DIVR_FpI16m32 + 0U, // DIVR_FpI16m64 + 0U, // DIVR_FpI16m80 + 0U, // DIVR_FpI32m32 + 0U, // DIVR_FpI32m64 + 0U, // DIVR_FpI32m80 + 29042U, // DIVR_FrST0 + 551702526U, // DIVSDrm + 551702526U, // DIVSDrm_Int + 8441854U, // DIVSDrr + 8441854U, // DIVSDrr_Int + 551725278U, // DIVSSrm + 551725278U, // DIVSSrm_Int + 8448222U, // DIVSSrr + 8448222U, // DIVSSrr_Int + 190737U, // DIV_F32m + 202644U, // DIV_F64m + 223512U, // DIV_FI16m + 235419U, // DIV_FI32m + 22753U, // DIV_FPrST0 + 27114U, // DIV_FST0r + 0U, // DIV_Fp32 + 0U, // DIV_Fp32m + 0U, // DIV_Fp64 + 0U, // DIV_Fp64m + 0U, // DIV_Fp64m32 + 0U, // DIV_Fp80 + 0U, // DIV_Fp80m32 + 0U, // DIV_Fp80m64 + 0U, // DIV_FpI16m32 + 0U, // DIV_FpI16m64 + 0U, // DIV_FpI16m80 + 0U, // DIV_FpI32m32 + 0U, // DIV_FpI32m64 + 0U, // DIV_FpI32m80 + 29027U, // DIV_FrST0 + 568708185U, // DPPDrmi + 1088818265U, // DPPDrri + 568714642U, // DPPSrmi + 1088824722U, // DPPSrri + 15781U, // ENCLS + 15906U, // ENCLU + 15940U, // ENCLV + 14745U, // ENDBR32 + 14776U, // ENDBR64 + 283140374U, // ENTER + 3810829867U, // EXTRACTPSmr + 283436587U, // EXTRACTPSrr + 6348457U, // EXTRQ + 4041612969U, // EXTRQI + 14726U, // F2XM1 + 551840871U, // FARCALL16i + 686279U, // FARCALL16m + 551834931U, // FARCALL32i + 686245U, // FARCALL32m + 686262U, // FARCALL64 + 54816020U, // FARJMP16i + 686288U, // FARJMP16m + 54810054U, // FARJMP32i + 686254U, // FARJMP32m + 686271U, // FARJMP64 + 702596U, // FBLDm + 702612U, // FBSTPm + 188893U, // FCOM32m + 202117U, // FCOM64m + 189790U, // FCOMP32m + 202189U, // FCOMP64m + 15406U, // FCOMPP + 15433U, // FDECSTP + 15387U, // FDISI8087_NOP + 15787U, // FEMMS + 15374U, // FENI8087_NOP + 20913U, // FFREE + 22683U, // FFREEP + 221668U, // FICOM16m + 234892U, // FICOM32m + 222566U, // FICOMP16m + 234965U, // FICOMP32m + 15441U, // FINCSTP + 223999U, // FLDCW16m + 190960U, // FLDENVm + 15012U, // FLDL2E + 15849U, // FLDL2T + 14757U, // FLDLG2 + 14764U, // FLDLN2 + 15147U, // FLDPI + 16196U, // FNCLEX + 15870U, // FNINIT + 15401U, // FNOP + 224024U, // FNSTCW16m + 15995U, // FNSTSW16r + 224892U, // FNSTSWm + 15317U, // FPATAN + 28981U, // FPNCEST0r + 15294U, // FPREM + 14719U, // FPREM1 + 15324U, // FPTAN + 15881U, // FRNDINT + 188727U, // FRSTORm + 184868U, // FSAVEm + 15040U, // FSCALE + 15306U, // FSETPM + 15798U, // FSINCOS + 190968U, // FSTENVm + 15289U, // FXAM + 680255U, // FXRSTOR + 672071U, // FXRSTOR64 + 676396U, // FXSAVE + 672061U, // FXSAVE64 + 15856U, // FXTRACT + 15989U, // FYL2X + 14732U, // FYL2XP1 + 14924U, // GETSEC + 593872181U, // GF2P8AFFINEINVQBrmi + 1088816437U, // GF2P8AFFINEINVQBrri + 593872118U, // GF2P8AFFINEQBrmi + 1088816374U, // GF2P8AFFINEQBrri + 8635518U, // GF2P8MULBrm + 8438910U, // GF2P8MULBrr + 8522557U, // HADDPDrm + 8440637U, // HADDPDrr + 8528954U, // HADDPSrm + 8447034U, // HADDPSrr + 15877U, // HLT + 8522444U, // HSUBPDrm + 8440524U, // HSUBPDrr + 8528841U, // HSUBPSrm + 8446921U, // HSUBPSrr + 225169U, // IDIV16m + 28561U, // IDIV16r + 235420U, // IDIV32m + 22428U, // IDIV32r + 450644U, // IDIV64m + 24660U, // IDIV64r + 476826U, // IDIV8m + 18074U, // IDIV8r + 221588U, // ILD_F16m + 234515U, // ILD_F32m + 447781U, // ILD_F64m + 0U, // ILD_Fp16m32 + 0U, // ILD_Fp16m64 + 0U, // ILD_Fp16m80 + 0U, // ILD_Fp32m32 + 0U, // ILD_Fp32m64 + 0U, // ILD_Fp32m80 + 0U, // ILD_Fp64m32 + 0U, // ILD_Fp64m64 + 0U, // ILD_Fp64m80 + 224414U, // IMUL16m + 27806U, // IMUL16r + 8465566U, // IMUL16rm + 59059358U, // IMUL16rmi + 59059358U, // IMUL16rmi8 + 8449182U, // IMUL16rr + 811658398U, // IMUL16rri + 811658398U, // IMUL16rri8 + 234870U, // IMUL32m + 21878U, // IMUL32r + 551638390U, // IMUL32rm + 832902518U, // IMUL32rmi + 832902518U, // IMUL32rmi8 + 8443254U, // IMUL32rr + 811652470U, // IMUL32rri + 811652470U, // IMUL32rri8 + 449798U, // IMUL64m + 23814U, // IMUL64r + 551656710U, // IMUL64rm + 835001606U, // IMUL64rmi32 + 835001606U, // IMUL64rmi8 + 8445190U, // IMUL64rr + 811654406U, // IMUL64rri32 + 811654406U, // IMUL64rri8 + 476297U, // IMUL8m + 17545U, // IMUL8r + 2813166U, // IN16ri + 16006U, // IN16rr + 11195803U, // IN32ri + 16066U, // IN32rr + 21677279U, // IN8ri + 15162U, // IN8rr + 224012U, // INC16m + 27404U, // INC16r + 27404U, // INC16r_alt + 234450U, // INC32m + 21458U, // INC32r + 21458U, // INC32r_alt + 449018U, // INC64m + 23034U, // INC64r + 476109U, // INC8m + 17357U, // INC8r + 19684U, // INCSSPD + 23964U, // INCSSPQ + 554385U, // INSB + 856024653U, // INSERTPSrm + 1088824909U, // INSERTPSrr + 6348745U, // INSERTQ + 15409097U, // INSERTQI + 570780U, // INSL + 603559U, // INSW + 715063U, // INT + 14740U, // INT1 + 14771U, // INT3 + 15342U, // INTO + 14998U, // INVD + 272700U, // INVEPT32 + 272700U, // INVEPT64 + 479808U, // INVLPG + 16115U, // INVLPGA32 + 16134U, // INVLPGA64 + 264267U, // INVPCID32 + 264267U, // INVPCID64 + 264283U, // INVVPID32 + 264283U, // INVVPID64 + 15977U, // IRET16 + 15247U, // IRET32 + 15462U, // IRET64 + 222850U, // ISTT_FP16m + 235016U, // ISTT_FP32m + 447838U, // ISTT_FP64m + 0U, // ISTT_Fp16m32 + 0U, // ISTT_Fp16m64 + 0U, // ISTT_Fp16m80 + 0U, // ISTT_Fp32m32 + 0U, // ISTT_Fp32m64 + 0U, // ISTT_Fp32m80 + 0U, // ISTT_Fp64m32 + 0U, // ISTT_Fp64m64 + 0U, // ISTT_Fp64m80 + 223498U, // IST_F16m + 235391U, // IST_F32m + 222842U, // IST_FP16m + 235008U, // IST_FP32m + 447829U, // IST_FP64m + 0U, // IST_Fp16m32 + 0U, // IST_Fp16m64 + 0U, // IST_Fp16m80 + 0U, // IST_Fp32m32 + 0U, // IST_Fp32m64 + 0U, // IST_Fp32m80 + 0U, // IST_Fp64m32 + 0U, // IST_Fp64m64 + 0U, // IST_Fp64m80 + 463238U, // JAE_1 + 463238U, // JAE_2 + 463238U, // JAE_4 + 459576U, // JA_1 + 459576U, // JA_2 + 459576U, // JA_4 + 463250U, // JBE_1 + 463250U, // JBE_2 + 463250U, // JBE_4 + 459850U, // JB_1 + 459850U, // JB_2 + 459850U, // JB_4 + 471308U, // JCXZ + 471301U, // JECXZ + 463309U, // JE_1 + 463309U, // JE_2 + 463309U, // JE_4 + 463288U, // JGE_1 + 463288U, // JGE_2 + 463288U, // JGE_4 + 463420U, // JG_1 + 463420U, // JG_2 + 463420U, // JG_4 + 463313U, // JLE_1 + 463313U, // JLE_2 + 463313U, // JLE_4 + 464123U, // JL_1 + 464123U, // JL_2 + 464123U, // JL_4 + 227537U, // JMP16m + 227537U, // JMP16m_NT + 30929U, // JMP16r + 30929U, // JMP16r_NT + 243887U, // JMP32m + 243887U, // JMP32m_NT + 30895U, // JMP32r + 30895U, // JMP32r_NT + 456896U, // JMP64m + 456896U, // JMP64m_NT + 30912U, // JMP64r + 30912U, // JMP64r_NT + 465070U, // JMP_1 + 465070U, // JMP_2 + 465070U, // JMP_4 + 463325U, // JNE_1 + 463325U, // JNE_2 + 463325U, // JNE_4 + 465012U, // JNO_1 + 465012U, // JNO_2 + 465012U, // JNO_4 + 465090U, // JNP_1 + 465090U, // JNP_2 + 465090U, // JNP_4 + 467444U, // JNS_1 + 467444U, // JNS_2 + 467444U, // JNS_4 + 465008U, // JO_1 + 465008U, // JO_2 + 465008U, // JO_4 + 465059U, // JP_1 + 465059U, // JP_2 + 465059U, // JP_4 + 471314U, // JRCXZ + 467402U, // JS_1 + 467402U, // JS_2 + 467402U, // JS_4 + 811647971U, // KADDBrr + 811648949U, // KADDDrr + 811653712U, // KADDQrr + 811658025U, // KADDWrr + 811647993U, // KANDBrr + 811648973U, // KANDDrr + 811648206U, // KANDNBrr + 811649244U, // KANDNDrr + 811654469U, // KANDNQrr + 811658461U, // KANDNWrr + 811653823U, // KANDQrr + 811658065U, // KANDWrr + 551831209U, // KMOVBkk + 493225U, // KMOVBkm + 551831209U, // KMOVBkr + 23103145U, // KMOVBmk + 551831209U, // KMOVBrk + 551833826U, // KMOVDkk + 551899362U, // KMOVDkm + 551833826U, // KMOVDkr + 12620002U, // KMOVDmk + 551833826U, // KMOVDrk + 551837819U, // KMOVQkk + 551919739U, // KMOVQkm + 551837819U, // KMOVQkr + 18915451U, // KMOVQmk + 551837819U, // KMOVQrk + 551841706U, // KMOVWkk + 438186U, // KMOVWkm + 551841706U, // KMOVWkr + 4239274U, // KMOVWmk + 551841706U, // KMOVWrk + 551831093U, // KNOTBrr + 551833682U, // KNOTDrr + 551837626U, // KNOTQrr + 551841546U, // KNOTWrr + 811648354U, // KORBrr + 811650468U, // KORDrr + 811654736U, // KORQrr + 551831130U, // KORTESTBrr + 551833719U, // KORTESTDrr + 551837672U, // KORTESTQrr + 551841583U, // KORTESTWrr + 811658631U, // KORWrr + 283427955U, // KSHIFTLBri + 283429019U, // KSHIFTLDri + 283434236U, // KSHIFTLQri + 283438228U, // KSHIFTLWri + 283428230U, // KSHIFTRBri + 283430361U, // KSHIFTRDri + 283434648U, // KSHIFTRQri + 283438519U, // KSHIFTRWri + 551831122U, // KTESTBrr + 551833711U, // KTESTDrr + 551837664U, // KTESTQrr + 551841575U, // KTESTWrr + 811657881U, // KUNPCKBWrr + 811653765U, // KUNPCKDQrr + 811651363U, // KUNPCKWDrr + 811648360U, // KXNORBrr + 811650474U, // KXNORDrr + 811654742U, // KXNORQrr + 811658637U, // KXNORWrr + 811648374U, // KXORBrr + 811650497U, // KXORDrr + 811654765U, // KXORQrr + 811658651U, // KXORWrr + 15106U, // LAHF + 437600U, // LAR16rm + 551841120U, // LAR16rr + 431664U, // LAR32rm + 551835184U, // LAR32rr + 433720U, // LAR64rm + 551837240U, // LAR64rr + 272837U, // LDDQUrm + 237910U, // LDMXCSR + 749088U, // LDS16rm + 743086U, // LDS32rm + 16228U, // LD_F0 + 14710U, // LD_F1 + 188814U, // LD_F32m + 201734U, // LD_F64m + 698656U, // LD_F80m + 0U, // LD_Fp032 + 0U, // LD_Fp064 + 0U, // LD_Fp080 + 0U, // LD_Fp132 + 0U, // LD_Fp164 + 0U, // LD_Fp180 + 0U, // LD_Fp32m + 0U, // LD_Fp32m64 + 0U, // LD_Fp32m80 + 0U, // LD_Fp64m + 0U, // LD_Fp64m80 + 0U, // LD_Fp80m + 18532U, // LD_Frr + 420407U, // LEA16r + 414563U, // LEA32r + 414563U, // LEA64_32r + 416102U, // LEA64r + 15093U, // LEAVE + 15093U, // LEAVE64 + 749101U, // LES16rm + 743099U, // LES32rm + 15019U, // LFENCE + 749107U, // LFS16rm + 743105U, // LFS32rm + 745183U, // LFS64rm + 683701U, // LGDT16m + 677667U, // LGDT32m + 679778U, // LGDT64m + 749113U, // LGS16rm + 743111U, // LGS32rm + 745925U, // LGS64rm + 683715U, // LIDT16m + 677681U, // LIDT32m + 679792U, // LIDT64m + 224977U, // LLDT16m + 28369U, // LLDT16r + 17363U, // LLWPCB + 17363U, // LLWPCB64 + 225211U, // LMSW16m + 28603U, // LMSW16r + 15157U, // LOCK_PREFIX + 21726659U, // LODSB + 11261620U, // LODSL + 794328U, // LODSQ + 2911782U, // LODSW + 465107U, // LOOP + 463354U, // LOOPE + 463330U, // LOOPNE + 22342U, // LRETIL + 24453U, // LRETIQ + 28383U, // LRETIW + 15253U, // LRETL + 15468U, // LRETQ + 15983U, // LRETW + 437390U, // LSL16rm + 551840910U, // LSL16rr + 431464U, // LSL32rm + 551834984U, // LSL32rr + 433390U, // LSL64rm + 551836910U, // LSL64rr + 749168U, // LSS16rm + 743171U, // LSS32rm + 745252U, // LSS64rm + 224705U, // LTRm + 28097U, // LTRr + 832905708U, // LWPINS32rmi + 811655660U, // LWPINS32rri + 832905708U, // LWPINS64rmi + 811655660U, // LWPINS64rri + 832902001U, // LWPVAL32rmi + 811651953U, // LWPVAL32rri + 832902001U, // LWPVAL64rmi + 811651953U, // LWPVAL64rri + 438010U, // LZCNT16rm + 551841530U, // LZCNT16rr + 551901020U, // LZCNT32rm + 551835484U, // LZCNT32rr + 551919522U, // LZCNT64rm + 551837602U, // LZCNT64rr + 551840205U, // MASKMOVDQU + 551840205U, // MASKMOVDQU64 + 8523091U, // MAXCPDrm + 8441171U, // MAXCPDrr + 8529588U, // MAXCPSrm + 8447668U, // MAXCPSrr + 551702543U, // MAXCSDrm + 8441871U, // MAXCSDrr + 551725294U, // MAXCSSrm + 8448238U, // MAXCSSrr + 8523091U, // MAXPDrm + 8441171U, // MAXPDrr + 8529588U, // MAXPSrm + 8447668U, // MAXPSrr + 551702543U, // MAXSDrm + 551702543U, // MAXSDrm_Int + 8441871U, // MAXSDrr + 8441871U, // MAXSDrr_Int + 551725294U, // MAXSSrm + 551725294U, // MAXSSrm_Int + 8448238U, // MAXSSrr + 8448238U, // MAXSSrr_Int + 15026U, // MFENCE + 8522833U, // MINCPDrm + 8440913U, // MINCPDrr + 8529282U, // MINCPSrm + 8447362U, // MINCPSrr + 551702376U, // MINCSDrm + 8441704U, // MINCSDrr + 551725177U, // MINCSSrm + 8448121U, // MINCSSrr + 8522833U, // MINPDrm + 8440913U, // MINPDrr + 8529282U, // MINPSrm + 8447362U, // MINPSrr + 551702376U, // MINSDrm + 551702376U, // MINSDrm_Int + 8441704U, // MINSDrr + 8441704U, // MINSDrr_Int + 551725177U, // MINSSrm + 551725177U, // MINSSrm_Int + 8448121U, // MINSSrr + 8448121U, // MINSSrr_Int + 660131U, // MMX_CVTPD2PIirm + 551834275U, // MMX_CVTPD2PIirr + 551913917U, // MMX_CVTPI2PDirm + 551831997U, // MMX_CVTPI2PDirr + 551658189U, // MMX_CVTPI2PSirm + 8446669U, // MMX_CVTPI2PSirr + 552178360U, // MMX_CVTPS2PIirm + 551834296U, // MMX_CVTPS2PIirr + 660120U, // MMX_CVTTPD2PIirm + 551834264U, // MMX_CVTTPD2PIirr + 552178349U, // MMX_CVTTPS2PIirm + 551834285U, // MMX_CVTTPS2PIirr + 15788U, // MMX_EMMS + 551837816U, // MMX_MASKMOVQ + 551837816U, // MMX_MASKMOVQ64 + 18915452U, // MMX_MOVD64from64rm + 551837820U, // MMX_MOVD64from64rr + 551833827U, // MMX_MOVD64grr + 12620003U, // MMX_MOVD64mr + 551899363U, // MMX_MOVD64rm + 551833827U, // MMX_MOVD64rr + 551919740U, // MMX_MOVD64to64rm + 551837820U, // MMX_MOVD64to64rr + 551835987U, // MMX_MOVDQ2Qrr + 551835987U, // MMX_MOVFR642Qrr + 18915250U, // MMX_MOVNTQmr + 551836189U, // MMX_MOVQ2DQrr + 551836189U, // MMX_MOVQ2FR64rr + 18915452U, // MMX_MOVQ64mr + 551919740U, // MMX_MOVQ64rm + 551837820U, // MMX_MOVQ64rr + 551837820U, // MMX_MOVQ64rr_REV + 551912865U, // MMX_PABSBrm + 551830945U, // MMX_PABSBrr + 551915206U, // MMX_PABSDrm + 551833286U, // MMX_PABSDrr + 551923166U, // MMX_PABSWrm + 551841246U, // MMX_PABSWrr + 551660416U, // MMX_PACKSSDWirm + 8448896U, // MMX_PACKSSDWirr + 551650999U, // MMX_PACKSSWBirm + 8439479U, // MMX_PACKSSWBirr + 551651010U, // MMX_PACKUSWBirm + 8439490U, // MMX_PACKUSWBirr + 551650283U, // MMX_PADDBirm + 8438763U, // MMX_PADDBirr + 551651261U, // MMX_PADDDirm + 8439741U, // MMX_PADDDirr + 551656024U, // MMX_PADDQirm + 8444504U, // MMX_PADDQirr + 551650747U, // MMX_PADDSBirm + 8439227U, // MMX_PADDSBirr + 551661080U, // MMX_PADDSWirm + 8449560U, // MMX_PADDSWirr + 551650809U, // MMX_PADDUSBirm + 8439289U, // MMX_PADDUSBirr + 551661206U, // MMX_PADDUSWirm + 8449686U, // MMX_PADDUSWirr + 551660337U, // MMX_PADDWirm + 8448817U, // MMX_PADDWirr + 866509086U, // MMX_PALIGNRrmi + 1088823582U, // MMX_PALIGNRrri + 551655507U, // MMX_PANDNirm + 8443987U, // MMX_PANDNirr + 551651542U, // MMX_PANDirm + 8440022U, // MMX_PANDirr + 551650371U, // MMX_PAVGBirm + 8438851U, // MMX_PAVGBirr + 551660558U, // MMX_PAVGWirm + 8449038U, // MMX_PAVGWirr + 551650566U, // MMX_PCMPEQBirm + 8439046U, // MMX_PCMPEQBirr + 551652708U, // MMX_PCMPEQDirm + 8441188U, // MMX_PCMPEQDirr + 551660857U, // MMX_PCMPEQWirm + 8449337U, // MMX_PCMPEQWirr + 551650850U, // MMX_PCMPGTBirm + 8439330U, // MMX_PCMPGTBirr + 551653429U, // MMX_PCMPGTDirm + 8441909U, // MMX_PCMPGTDirr + 551661287U, // MMX_PCMPGTWirm + 8449767U, // MMX_PCMPGTWirr + 283438542U, // MMX_PEXTRWrr + 551651245U, // MMX_PHADDDrm + 8439725U, // MMX_PHADDDrr + 551661070U, // MMX_PHADDSWrm + 8449550U, // MMX_PHADDSWrr + 551660321U, // MMX_PHADDWrm + 8448801U, // MMX_PHADDWrr + 551651199U, // MMX_PHSUBDrm + 8439679U, // MMX_PHSUBDrr + 551661051U, // MMX_PHSUBSWrm + 8449531U, // MMX_PHSUBSWrr + 551660227U, // MMX_PHSUBWrm + 8448707U, // MMX_PHSUBWrr + 600173993U, // MMX_PINSRWrm + 1088826793U, // MMX_PINSRWrr + 551661039U, // MMX_PMADDUBSWrm + 8449519U, // MMX_PMADDUBSWrr + 551653646U, // MMX_PMADDWDirm + 8442126U, // MMX_PMADDWDirr + 551661224U, // MMX_PMAXSWirm + 8449704U, // MMX_PMAXSWirr + 551650951U, // MMX_PMAXUBirm + 8439431U, // MMX_PMAXUBirr + 551661120U, // MMX_PMINSWirm + 8449600U, // MMX_PMINSWirr + 551650926U, // MMX_PMINUBirm + 8439406U, // MMX_PMINUBirr + 551830607U, // MMX_PMOVMSKBrr + 551661145U, // MMX_PMULHRSWrm + 8449625U, // MMX_PMULHRSWrr + 551661370U, // MMX_PMULHUWirm + 8449850U, // MMX_PMULHUWirr + 551660595U, // MMX_PMULHWirm + 8449075U, // MMX_PMULHWirr + 551660664U, // MMX_PMULLWirm + 8449144U, // MMX_PMULLWirr + 551656344U, // MMX_PMULUDQirm + 8444824U, // MMX_PMULUDQirr + 551657768U, // MMX_PORirm + 8446248U, // MMX_PORirr + 551660136U, // MMX_PSADBWirm + 8448616U, // MMX_PSADBWirr + 551650346U, // MMX_PSHUFBrm + 8438826U, // MMX_PSHUFBrr + 834972661U, // MMX_PSHUFWmi + 283438069U, // MMX_PSHUFWri + 551650519U, // MMX_PSIGNBrm + 8438999U, // MMX_PSIGNBrr + 551651575U, // MMX_PSIGNDrm + 8440055U, // MMX_PSIGNDrr + 551660774U, // MMX_PSIGNWrm + 8449254U, // MMX_PSIGNWrr + 551864434U, // MMX_PSLLDri + 551651442U, // MMX_PSLLDrm + 8439922U, // MMX_PSLLDrr + 551869646U, // MMX_PSLLQri + 551656654U, // MMX_PSLLQrm + 8445134U, // MMX_PSLLQrr + 551873648U, // MMX_PSLLWri + 551660656U, // MMX_PSLLWrm + 8449136U, // MMX_PSLLWrr + 551864162U, // MMX_PSRADri + 551651170U, // MMX_PSRADrm + 8439650U, // MMX_PSRADrr + 551873094U, // MMX_PSRAWri + 551660102U, // MMX_PSRAWrm + 8448582U, // MMX_PSRAWrr + 551864459U, // MMX_PSRLDri + 551651467U, // MMX_PSRLDrm + 8439947U, // MMX_PSRLDrr + 551869671U, // MMX_PSRLQri + 551656679U, // MMX_PSRLQrm + 8445159U, // MMX_PSRLQrr + 551873671U, // MMX_PSRLWri + 551660679U, // MMX_PSRLWrm + 8449159U, // MMX_PSRLWrr + 551650234U, // MMX_PSUBBirm + 8438714U, // MMX_PSUBBirr + 551651208U, // MMX_PSUBDirm + 8439688U, // MMX_PSUBDirr + 551655848U, // MMX_PSUBQirm + 8444328U, // MMX_PSUBQirr + 551650738U, // MMX_PSUBSBirm + 8439218U, // MMX_PSUBSBirr + 551661061U, // MMX_PSUBSWirm + 8449541U, // MMX_PSUBSWirr + 551650799U, // MMX_PSUBUSBirm + 8439279U, // MMX_PSUBUSBirr + 551661196U, // MMX_PSUBUSWirm + 8449676U, // MMX_PSUBUSWirr + 551660236U, // MMX_PSUBWirm + 8448716U, // MMX_PSUBWirr + 551660174U, // MMX_PUNPCKHBWirm + 8448654U, // MMX_PUNPCKHBWirr + 551656058U, // MMX_PUNPCKHDQirm + 8444538U, // MMX_PUNPCKHDQirr + 551653656U, // MMX_PUNPCKHWDirm + 8442136U, // MMX_PUNPCKHWDirr + 551643812U, // MMX_PUNPCKLBWirm + 8448676U, // MMX_PUNPCKLBWirr + 551639705U, // MMX_PUNPCKLDQirm + 8444569U, // MMX_PUNPCKLDQirr + 551637294U, // MMX_PUNPCKLWDirm + 8442158U, // MMX_PUNPCKLWDirr + 551657801U, // MMX_PXORirm + 8446281U, // MMX_PXORirr + 16203U, // MONITORXrrr + 15516U, // MONITORrrr + 15281U, // MONTMUL + 2928555U, // MOV16ao16 + 2928555U, // MOV16ao32 + 2928101U, // MOV16ao64 + 4239275U, // MOV16mi + 4239275U, // MOV16mr + 4239275U, // MOV16ms + 832784U, // MOV16o16a + 832784U, // MOV16o32a + 832747U, // MOV16o64a + 551841707U, // MOV16ri + 551841707U, // MOV16ri_alt + 438187U, // MOV16rm + 551841707U, // MOV16rr + 551841707U, // MOV16rr_REV + 551841707U, // MOV16rs + 438187U, // MOV16sm + 551841707U, // MOV16sr + 11327395U, // MOV32ao16 + 11327395U, // MOV32ao32 + 11327134U, // MOV32ao64 + 551835555U, // MOV32cr + 551835555U, // MOV32dr + 12621731U, // MOV32mi + 12621731U, // MOV32mr + 849232U, // MOV32o16a + 849232U, // MOV32o32a + 849192U, // MOV32o64a + 551835555U, // MOV32rc + 551835555U, // MOV32rd + 551835555U, // MOV32ri + 551835555U, // MOV32ri_alt + 551901091U, // MOV32rm + 551835555U, // MOV32rr + 551835555U, // MOV32rr_REV + 551835555U, // MOV32rs + 551835555U, // MOV32sr + 17637500U, // MOV64ao32 + 17637064U, // MOV64ao64 + 551837820U, // MOV64cr + 551837820U, // MOV64dr + 18915452U, // MOV64mi32 + 18915452U, // MOV64mr + 865669U, // MOV64o32a + 865641U, // MOV64o64a + 551837820U, // MOV64rc + 551837820U, // MOV64rd + 551837384U, // MOV64ri + 551837820U, // MOV64ri32 + 551919740U, // MOV64rm + 551837820U, // MOV64rr + 551837820U, // MOV64rr_REV + 551837820U, // MOV64rs + 551837820U, // MOV64sr + 551919740U, // MOV64toPQIrm + 551837820U, // MOV64toPQIrr + 551919740U, // MOV64toSDrm + 551837820U, // MOV64toSDrr + 21841571U, // MOV8ao16 + 21841571U, // MOV8ao32 + 21841320U, // MOV8ao64 + 23103139U, // MOV8mi + 23103139U, // MOV8mr + 23103139U, // MOV8mr_NOREX + 881452U, // MOV8o16a + 881452U, // MOV8o32a + 881415U, // MOV8o64a + 551831203U, // MOV8ri + 551831203U, // MOV8ri_alt + 493219U, // MOV8rm + 493219U, // MOV8rm_NOREX + 551831203U, // MOV8rr + 551831203U, // MOV8rr_NOREX + 551831203U, // MOV8rr_REV + 65047203U, // MOVAPDmr + 658083U, // MOVAPDrm + 551832227U, // MOVAPDrr + 551832227U, // MOVAPDrr_REV + 65053608U, // MOVAPSmr + 664488U, // MOVAPSrm + 551838632U, // MOVAPSrr + 551838632U, // MOVAPSrr_REV + 4238269U, // MOVBE16mr + 437181U, // MOVBE16rm + 12620877U, // MOVBE32mr + 551900237U, // MOVBE32rm + 18914241U, // MOVBE64mr + 551918529U, // MOVBE64rm + 552179968U, // MOVDDUPrm + 551835904U, // MOVDDUPrr + 551899363U, // MOVDI2PDIrm + 551833827U, // MOVDI2PDIrr + 551899363U, // MOVDI2SSrm + 551833827U, // MOVDI2SSrr + 552436617U, // MOVDIR64B16 + 552436617U, // MOVDIR64B32 + 552436617U, // MOVDIR64B64 + 12620499U, // MOVDIRI32 + 18911955U, // MOVDIRI64 + 33588040U, // MOVDQAmr + 262984U, // MOVDQArm + 551830344U, // MOVDQArr + 551830344U, // MOVDQArr_REV + 33597905U, // MOVDQUmr + 272849U, // MOVDQUrm + 551840209U, // MOVDQUrr + 551840209U, // MOVDQUrr_REV + 8447254U, // MOVHLPSrr + 67144676U, // MOVHPDmr + 551701476U, // MOVHPDrm + 67151106U, // MOVHPSmr + 551707906U, // MOVHPSrm + 8447224U, // MOVLHPSrr + 67144726U, // MOVLPDmr + 551701526U, // MOVLPDrm + 67151166U, // MOVLPSmr + 551707966U, // MOVLPSrm + 551832557U, // MOVMSKPDrr + 551838987U, // MOVMSKPSrr + 262973U, // MOVNTDQArm + 65051473U, // MOVNTDQmr + 18914427U, // MOVNTI_64mr + 12621042U, // MOVNTImr + 65047823U, // MOVNTPDmr + 65054275U, // MOVNTPSmr + 67145683U, // MOVNTSD + 69249203U, // MOVNTSS + 12620003U, // MOVPDI2DImr + 551833827U, // MOVPDI2DIrr + 18915452U, // MOVPQI2QImr + 551837820U, // MOVPQI2QIrr + 18915452U, // MOVPQIto64mr + 551837820U, // MOVPQIto64rr + 551919740U, // MOVQI2PQIrm + 902667U, // MOVSB + 67145734U, // MOVSDmr + 552177670U, // MOVSDrm + 8441862U, // MOVSDrr + 8441862U, // MOVSDrr_REV + 18915452U, // MOVSDto64mr + 551837820U, // MOVSDto64rr + 661770U, // MOVSHDUPrm + 551835914U, // MOVSHDUPrr + 923415U, // MOVSL + 661781U, // MOVSLDUPrm + 551835925U, // MOVSLDUPrr + 941888U, // MOVSQ + 12620003U, // MOVSS2DImr + 551833827U, // MOVSS2DIrr + 69249254U, // MOVSSmr + 552200422U, // MOVSSrm + 8448230U, // MOVSSrr + 8448230U, // MOVSSrr_REV + 962208U, // MOVSW + 438228U, // MOVSX16rm16 + 502447U, // MOVSX16rm8 + 551841748U, // MOVSX16rr16 + 551840431U, // MOVSX16rr8 + 432048U, // MOVSX32rm16 + 496511U, // MOVSX32rm8 + 496511U, // MOVSX32rm8_NOREX + 551835568U, // MOVSX32rr16 + 551834495U, // MOVSX32rr8 + 551834495U, // MOVSX32rr8_NOREX + 434339U, // MOVSX64rm16 + 551902452U, // MOVSX64rm32 + 498068U, // MOVSX64rm8 + 551837859U, // MOVSX64rr16 + 551836916U, // MOVSX64rr32 + 551836052U, // MOVSX64rr8 + 65047851U, // MOVUPDmr + 658731U, // MOVUPDrm + 551832875U, // MOVUPDrr + 551832875U, // MOVUPDrr_REV + 65054348U, // MOVUPSmr + 665228U, // MOVUPSrm + 551839372U, // MOVUPSrr + 551839372U, // MOVUPSrr_REV + 551837820U, // MOVZPQILo2PQIrr + 438236U, // MOVZX16rm16 + 502513U, // MOVZX16rm8 + 551841756U, // MOVZX16rr16 + 551840497U, // MOVZX16rr8 + 432056U, // MOVZX32rm16 + 496542U, // MOVZX32rm8 + 496542U, // MOVZX32rm8_NOREX + 551835576U, // MOVZX32rr16 + 551834526U, // MOVZX32rr8 + 551834526U, // MOVZX32rr8_NOREX + 434380U, // MOVZX64rm16 + 498125U, // MOVZX64rm8 + 551837900U, // MOVZX64rr16 + 551836109U, // MOVZX64rr8 + 593881713U, // MPSADBWrmi + 1088825969U, // MPSADBWrri + 224415U, // MUL16m + 27807U, // MUL16r + 234863U, // MUL32m + 21871U, // MUL32r + 449799U, // MUL64m + 23815U, // MUL64r + 476291U, // MUL8m + 17539U, // MUL8r + 8522766U, // MULPDrm + 8440846U, // MULPDrr + 8529206U, // MULPSrm + 8447286U, // MULPSrr + 551702354U, // MULSDrm + 551702354U, // MULSDrm_Int + 8441682U, // MULSDrr + 8441682U, // MULSDrr_Int + 551725156U, // MULSSrm + 551725156U, // MULSSrm_Int + 8448100U, // MULSSrr + 8448100U, // MULSSrr_Int + 283203534U, // MULX32rm + 811653070U, // MULX32rr + 283222242U, // MULX64rm + 811655394U, // MULX64rr + 188878U, // MUL_F32m + 202094U, // MUL_F64m + 221653U, // MUL_FI16m + 234869U, // MUL_FI32m + 22695U, // MUL_FPrST0 + 22414U, // MUL_FST0r + 0U, // MUL_Fp32 + 0U, // MUL_Fp32m + 0U, // MUL_Fp64 + 0U, // MUL_Fp64m + 0U, // MUL_Fp64m32 + 0U, // MUL_Fp80 + 0U, // MUL_Fp80m32 + 0U, // MUL_Fp80m64 + 0U, // MUL_FpI16m32 + 0U, // MUL_FpI16m64 + 0U, // MUL_FpI16m80 + 0U, // MUL_FpI32m32 + 0U, // MUL_FpI32m64 + 0U, // MUL_FpI32m80 + 28998U, // MUL_FrST0 + 16212U, // MWAITXrrr + 15864U, // MWAITrr + 224253U, // NEG16m + 27645U, // NEG16r + 234686U, // NEG32m + 21694U, // NEG32r + 449595U, // NEG64m + 23611U, // NEG64r + 476210U, // NEG8m + 17458U, // NEG8r + 15383U, // NOOP + 224548U, // NOOP18_16m4 + 224548U, // NOOP18_16m5 + 224548U, // NOOP18_16m6 + 224548U, // NOOP18_16m7 + 27940U, // NOOP18_16r4 + 27940U, // NOOP18_16r5 + 27940U, // NOOP18_16r6 + 27940U, // NOOP18_16r7 + 234983U, // NOOP18_m4 + 234983U, // NOOP18_m5 + 234983U, // NOOP18_m6 + 234983U, // NOOP18_m7 + 21991U, // NOOP18_r4 + 21991U, // NOOP18_r5 + 21991U, // NOOP18_r6 + 21991U, // NOOP18_r7 + 283138254U, // NOOP19rr + 234983U, // NOOPL + 234983U, // NOOPL_19 + 234983U, // NOOPL_1d + 234983U, // NOOPL_1e + 21991U, // NOOPLr + 449936U, // NOOPQ + 23952U, // NOOPQr + 224548U, // NOOPW + 224548U, // NOOPW_19 + 224548U, // NOOPW_1c + 224548U, // NOOPW_1d + 224548U, // NOOPW_1e + 27940U, // NOOPWr + 225035U, // NOT16m + 28427U, // NOT16r + 235372U, // NOT32m + 22380U, // NOT32r + 450491U, // NOT64m + 24507U, // NOT64r + 476726U, // NOT8m + 17974U, // NOT8r + 2125192U, // OR16i16 + 4238728U, // OR16mi + 4238728U, // OR16mi8 + 4238728U, // OR16mr + 6352264U, // OR16ri + 6352264U, // OR16ri8 + 6368648U, // OR16rm + 6352264U, // OR16rr + 8449416U, // OR16rr_REV + 10507866U, // OR32i32 + 12621402U, // OR32mi + 12621402U, // OR32mi8 + 12621402U, // OR32mr + 6346330U, // OR32ri + 6346330U, // OR32ri8 + 283203162U, // OR32rm + 6346330U, // OR32rr + 8443482U, // OR32rr_REV + 16801361U, // OR64i32 + 18914897U, // OR64mi32 + 18914897U, // OR64mi8 + 18914897U, // OR64mr + 6348369U, // OR64ri32 + 6348369U, // OR64ri8 + 283221585U, // OR64rm + 6348369U, // OR64rr + 8445521U, // OR64rr_REV + 20989283U, // OR8i8 + 23102819U, // OR8mi + 23102819U, // OR8mi8 + 23102819U, // OR8mr + 6341987U, // OR8ri + 6341987U, // OR8ri8 + 6407523U, // OR8rm + 6341987U, // OR8rr + 8439139U, // OR8rr_REV + 8522954U, // ORPDrm + 8441034U, // ORPDrr + 8529411U, // ORPSrm + 8447491U, // ORPSrr + 718085U, // OUT16ir + 16167U, // OUT16rr + 718148U, // OUT32ir + 16181U, // OUT32rr + 717601U, // OUT8ir + 16153U, // OUT8rr + 72058343U, // OUTSB + 72079119U, // OUTSL + 72117892U, // OUTSW + 263585U, // PABSBrm + 551830945U, // PABSBrr + 265926U, // PABSDrm + 551833286U, // PABSDrr + 273886U, // PABSWrm + 551841246U, // PABSWrr + 8645504U, // PACKSSDWrm + 8448896U, // PACKSSDWrr + 8636087U, // PACKSSWBrm + 8439479U, // PACKSSWBrr + 8645515U, // PACKUSDWrm + 8448907U, // PACKUSDWrr + 8636098U, // PACKUSWBrm + 8439490U, // PACKUSWBrr + 8635371U, // PADDBrm + 8438763U, // PADDBrr + 8636349U, // PADDDrm + 8439741U, // PADDDrr + 8641112U, // PADDQrm + 8444504U, // PADDQrr + 8635835U, // PADDSBrm + 8439227U, // PADDSBrr + 8646168U, // PADDSWrm + 8449560U, // PADDSWrr + 8635897U, // PADDUSBrm + 8439289U, // PADDUSBrr + 8646294U, // PADDUSWrm + 8449686U, // PADDUSWrr + 8645425U, // PADDWrm + 8448817U, // PADDWrr + 593879326U, // PALIGNRrmi + 1088823582U, // PALIGNRrri + 8640595U, // PANDNrm + 8443987U, // PANDNrr + 8636630U, // PANDrm + 8440022U, // PANDrr + 15087U, // PAUSE + 8635459U, // PAVGBrm + 8438851U, // PAVGBrr + 551650818U, // PAVGUSBrm + 8439298U, // PAVGUSBrr + 8645646U, // PAVGWrm + 8449038U, // PAVGWrr + 8647060U, // PBLENDVBrm0 + 8450452U, // PBLENDVBrr0 + 593881965U, // PBLENDWrmi + 1088826221U, // PBLENDWrri + 593877770U, // PCLMULQDQrm + 1088822026U, // PCLMULQDQrr + 8635654U, // PCMPEQBrm + 8439046U, // PCMPEQBrr + 8637796U, // PCMPEQDrm + 8441188U, // PCMPEQDrr + 8642020U, // PCMPEQQrm + 8445412U, // PCMPEQQrr + 8645945U, // PCMPEQWrm + 8449337U, // PCMPEQWrr + 830771933U, // PCMPESTRIrm + 283431645U, // PCMPESTRIrr + 830773300U, // PCMPESTRMrm + 283433012U, // PCMPESTRMrr + 8635938U, // PCMPGTBrm + 8439330U, // PCMPGTBrr + 8638517U, // PCMPGTDrm + 8441909U, // PCMPGTDrr + 8642445U, // PCMPGTQrm + 8445837U, // PCMPGTQrr + 8646375U, // PCMPGTWrm + 8449767U, // PCMPGTWrr + 830771945U, // PCMPISTRIrm + 283431657U, // PCMPISTRIrr + 830773312U, // PCMPISTRMrm + 283433024U, // PCMPISTRMrr + 15116U, // PCONFIG + 283203001U, // PDEP32rm + 811652537U, // PDEP32rr + 283221368U, // PDEP64rm + 811654520U, // PDEP64rr + 283203462U, // PEXT32rm + 811652998U, // PEXT32rr + 283222002U, // PEXT64rm + 811655154U, // PEXT64rr + 321160593U, // PEXTRBmr + 283428241U, // PEXTRBrr + 589598180U, // PEXTRDmr + 283430372U, // PEXTRDrr + 858037937U, // PEXTRQmr + 283434673U, // PEXTRQrr + 1126477262U, // PEXTRWmr + 283438542U, // PEXTRWrr + 283438542U, // PEXTRWrr_REV + 551913540U, // PF2IDrm + 551831620U, // PF2IDrr + 551922754U, // PF2IWrm + 551840834U, // PF2IWrr + 551651050U, // PFACCrm + 8439530U, // PFACCrr + 551651237U, // PFADDrm + 8439717U, // PFADDrr + 551656420U, // PFCMPEQrm + 8444900U, // PFCMPEQrr + 551653821U, // PFCMPGErm + 8442301U, // PFCMPGErr + 551659814U, // PFCMPGTrm + 8448294U, // PFCMPGTrr + 551661540U, // PFMAXrm + 8450020U, // PFMAXrr + 551655522U, // PFMINrm + 8444002U, // PFMINrr + 551655309U, // PFMULrm + 8443789U, // PFMULrr + 551651057U, // PFNACCrm + 8439537U, // PFNACCrr + 551651065U, // PFPNACCrm + 8439545U, // PFPNACCrr + 551649327U, // PFRCPIT1rm + 8437807U, // PFRCPIT1rr + 551649416U, // PFRCPIT2rm + 8437896U, // PFRCPIT2rr + 551917709U, // PFRCPrm + 551835789U, // PFRCPrr + 551649337U, // PFRSQIT1rm + 8437817U, // PFRSQIT1rr + 551922025U, // PFRSQRTrm + 551840105U, // PFRSQRTrr + 551657742U, // PFSUBRrm + 8446222U, // PFSUBRrr + 551650943U, // PFSUBrm + 8439423U, // PFSUBrr + 8636333U, // PHADDDrm + 8439725U, // PHADDDrr + 8646158U, // PHADDSWrm + 8449550U, // PHADDSWrr + 8645409U, // PHADDWrm + 8448801U, // PHADDWrr + 274271U, // PHMINPOSUWrm + 551841631U, // PHMINPOSUWrr + 8636287U, // PHSUBDrm + 8439679U, // PHSUBDrr + 8646139U, // PHSUBSWrm + 8449531U, // PHSUBSWrr + 8645315U, // PHSUBWrm + 8448707U, // PHSUBWrr + 551913512U, // PI2FDrm + 551831592U, // PI2FDrr + 551922664U, // PI2FWrm + 551840744U, // PI2FWrr + 879084926U, // PINSRBrm + 1088816510U, // PINSRBrr + 881184209U, // PINSRDrm + 1088818641U, // PINSRDrr + 866508426U, // PINSRQrm + 1088822922U, // PINSRQrr + 600173993U, // PINSRWrm + 1088826793U, // PINSRWrr + 8646127U, // PMADDUBSWrm + 8449519U, // PMADDUBSWrr + 8638734U, // PMADDWDrm + 8442126U, // PMADDWDrr + 8635923U, // PMAXSBrm + 8439315U, // PMAXSBrr + 8638478U, // PMAXSDrm + 8441870U, // PMAXSDrr + 8646312U, // PMAXSWrm + 8449704U, // PMAXSWrr + 8636039U, // PMAXUBrm + 8439431U, // PMAXUBrr + 8638621U, // PMAXUDrm + 8442013U, // PMAXUDrr + 8646508U, // PMAXUWrm + 8449900U, // PMAXUWrr + 8635851U, // PMINSBrm + 8439243U, // PMINSBrr + 8638311U, // PMINSDrm + 8441703U, // PMINSDrr + 8646208U, // PMINSWrm + 8449600U, // PMINSWrr + 8636014U, // PMINUBrm + 8439406U, // PMINUBrr + 8638603U, // PMINUDrm + 8441995U, // PMINUDrr + 8646477U, // PMINUWrm + 8449869U, // PMINUWrr + 551830607U, // PMOVMSKBrr + 551896976U, // PMOVSXBDrm + 551831440U, // PMOVSXBDrr + 432568U, // PMOVSXBQrm + 551836088U, // PMOVSXBQrr + 551922396U, // PMOVSXBWrm + 551840476U, // PMOVSXBWrr + 551918498U, // PMOVSXDQrm + 551836578U, // PMOVSXDQrr + 551915889U, // PMOVSXWDrm + 551833969U, // PMOVSXWDrr + 551903415U, // PMOVSXWQrm + 551837879U, // PMOVSXWQrr + 551896987U, // PMOVZXBDrm + 551831451U, // PMOVZXBDrr + 432579U, // PMOVZXBQrm + 551836099U, // PMOVZXBQrr + 551922407U, // PMOVZXBWrm + 551840487U, // PMOVZXBWrr + 551918509U, // PMOVZXDQrm + 551836589U, // PMOVZXDQrr + 551915900U, // PMOVZXWDrm + 551833980U, // PMOVZXWDrr + 551903426U, // PMOVZXWQrm + 551837890U, // PMOVZXWQrr + 8641207U, // PMULDQrm + 8444599U, // PMULDQrr + 8646233U, // PMULHRSWrm + 8449625U, // PMULHRSWrr + 551660920U, // PMULHRWrm + 8449400U, // PMULHRWrr + 8646458U, // PMULHUWrm + 8449850U, // PMULHUWrr + 8645683U, // PMULHWrm + 8449075U, // PMULHWrr + 8636538U, // PMULLDrm + 8439930U, // PMULLDrr + 8645752U, // PMULLWrm + 8449144U, // PMULLWrr + 8641432U, // PMULUDQrm + 8444824U, // PMULUDQrr + 27946U, // POP16r + 224554U, // POP16rmm + 27946U, // POP16rmr + 21997U, // POP32r + 234989U, // POP32rmm + 21997U, // POP32rmr + 23958U, // POP64r + 449942U, // POP64rmm + 23958U, // POP64rmr + 15953U, // POPA16 + 15182U, // POPA32 + 438001U, // POPCNT16rm + 551841521U, // POPCNT16rr + 551901011U, // POPCNT32rm + 551835475U, // POPCNT32rr + 551919511U, // POPCNT64rm + 551837591U, // POPCNT64rr + 15608U, // POPDS16 + 15589U, // POPDS32 + 15646U, // POPES16 + 15627U, // POPES32 + 15966U, // POPF16 + 15195U, // POPF32 + 15456U, // POPF64 + 15703U, // POPFS16 + 15665U, // POPFS32 + 15684U, // POPFS64 + 15760U, // POPGS16 + 15722U, // POPGS32 + 15741U, // POPGS64 + 15835U, // POPSS16 + 15816U, // POPSS32 + 8642856U, // PORrm + 8446248U, // PORrr + 479822U, // PREFETCH + 475990U, // PREFETCHNTA + 475137U, // PREFETCHT0 + 475171U, // PREFETCHT1 + 475260U, // PREFETCHT2 + 486429U, // PREFETCHW + 475203U, // PREFETCHWT1 + 8645224U, // PSADBWrm + 8448616U, // PSADBWrr + 8635434U, // PSHUFBrm + 8438826U, // PSHUFBrr + 830769200U, // PSHUFDmi + 283428912U, // PSHUFDri + 830778409U, // PSHUFHWmi + 283438121U, // PSHUFHWri + 830778454U, // PSHUFLWmi + 283438166U, // PSHUFLWri + 8635607U, // PSIGNBrm + 8438999U, // PSIGNBrr + 8636663U, // PSIGNDrm + 8440055U, // PSIGNDrr + 8645862U, // PSIGNWrm + 8449254U, // PSIGNWrr + 551869093U, // PSLLDQri + 551864434U, // PSLLDri + 8636530U, // PSLLDrm + 8439922U, // PSLLDrr + 551869646U, // PSLLQri + 8641742U, // PSLLQrm + 8445134U, // PSLLQrr + 551873648U, // PSLLWri + 8645744U, // PSLLWrm + 8449136U, // PSLLWrr + 551864162U, // PSRADri + 8636258U, // PSRADrm + 8439650U, // PSRADrr + 551873094U, // PSRAWri + 8645190U, // PSRAWrm + 8448582U, // PSRAWrr + 551869102U, // PSRLDQri + 551864459U, // PSRLDri + 8636555U, // PSRLDrm + 8439947U, // PSRLDrr + 551869671U, // PSRLQri + 8641767U, // PSRLQrm + 8445159U, // PSRLQrr + 551873671U, // PSRLWri + 8645767U, // PSRLWrm + 8449159U, // PSRLWrr + 8635322U, // PSUBBrm + 8438714U, // PSUBBrr + 8636296U, // PSUBDrm + 8439688U, // PSUBDrr + 8640936U, // PSUBQrm + 8444328U, // PSUBQrr + 8635826U, // PSUBSBrm + 8439218U, // PSUBSBrr + 8646149U, // PSUBSWrm + 8449541U, // PSUBSWrr + 8635887U, // PSUBUSBrm + 8439279U, // PSUBUSBrr + 8646284U, // PSUBUSWrm + 8449676U, // PSUBUSWrr + 8645324U, // PSUBWrm + 8448716U, // PSUBWrr + 551914155U, // PSWAPDrm + 551832235U, // PSWAPDrr + 665997U, // PTESTrm + 551840141U, // PTESTrr + 449571U, // PTWRITE64m + 23587U, // PTWRITE64r + 234662U, // PTWRITEm + 21670U, // PTWRITEr + 8645262U, // PUNPCKHBWrm + 8448654U, // PUNPCKHBWrr + 8641146U, // PUNPCKHDQrm + 8444538U, // PUNPCKHDQrr + 8641264U, // PUNPCKHQDQrm + 8444656U, // PUNPCKHQDQrr + 8638744U, // PUNPCKHWDrm + 8442136U, // PUNPCKHWDrr + 8645284U, // PUNPCKLBWrm + 8448676U, // PUNPCKLBWrr + 8641177U, // PUNPCKLDQrm + 8444569U, // PUNPCKLDQrr + 8641277U, // PUNPCKLQDQrm + 8444669U, // PUNPCKLQDQrr + 8638766U, // PUNPCKLWDrm + 8442158U, // PUNPCKLWDrr + 27707U, // PUSH16i8 + 27707U, // PUSH16r + 224315U, // PUSH16rmm + 27707U, // PUSH16rmr + 21718U, // PUSH32i8 + 21718U, // PUSH32r + 234710U, // PUSH32rmm + 21718U, // PUSH32rmr + 23647U, // PUSH64i32 + 23647U, // PUSH64i8 + 23647U, // PUSH64r + 449631U, // PUSH64rmm + 23647U, // PUSH64rmr + 15946U, // PUSHA16 + 15175U, // PUSHA32 + 15569U, // PUSHCS16 + 15559U, // PUSHCS32 + 15598U, // PUSHDS16 + 15579U, // PUSHDS32 + 15636U, // PUSHES16 + 15617U, // PUSHES32 + 15959U, // PUSHF16 + 15188U, // PUSHF32 + 15449U, // PUSHF64 + 15693U, // PUSHFS16 + 15655U, // PUSHFS32 + 15674U, // PUSHFS64 + 15750U, // PUSHGS16 + 15712U, // PUSHGS32 + 15731U, // PUSHGS64 + 15825U, // PUSHSS16 + 15806U, // PUSHSS32 + 27707U, // PUSHi16 + 21718U, // PUSHi32 + 8642889U, // PXORrm + 8446281U, // PXORrr + 224335U, // RCL16m1 + 226450U, // RCL16mCL + 1089399887U, // RCL16mi + 29377U, // RCL16r1 + 29842U, // RCL16rCL + 551873615U, // RCL16ri + 234783U, // RCL32m1 + 242610U, // RCL32mCL + 552523039U, // RCL32mi + 29217U, // RCL32r1 + 29618U, // RCL32rCL + 551867679U, // RCL32ri + 449700U, // RCL64m1 + 455714U, // RCL64mCL + 820960420U, // RCL64mi + 29297U, // RCL64r1 + 29730U, // RCL64rCL + 551869604U, // RCL64ri + 476255U, // RCL8m1 + 488258U, // RCL8mCL + 284083295U, // RCL8mi + 29137U, // RCL8r1 + 29506U, // RCL8rCL + 551863391U, // RCL8ri + 664970U, // RCPPSm + 551839114U, // RCPPSr + 552200321U, // RCPSSm + 551725185U, // RCPSSm_Int + 551839873U, // RCPSSr + 8448129U, // RCPSSr_Int + 226025U, // RCR16m1 + 226494U, // RCR16mCL + 1089400172U, // RCR16mi + 29417U, // RCR16r1 + 29886U, // RCR16rCL + 551873900U, // RCR16ri + 242249U, // RCR32m1 + 242654U, // RCR32mCL + 552523341U, // RCR32mi + 29257U, // RCR32r1 + 29662U, // RCR32rCL + 551867981U, // RCR32ri + 455321U, // RCR64m1 + 455758U, // RCR64mCL + 820960836U, // RCR64mi + 29337U, // RCR64r1 + 29774U, // RCR64rCL + 551870020U, // RCR64ri + 487929U, // RCR8m1 + 488302U, // RCR8mCL + 284083542U, // RCR8mi + 29177U, // RCR8r1 + 29550U, // RCR8rCL + 551863638U, // RCR8ri + 21616U, // RDFSBASE + 23533U, // RDFSBASE64 + 21638U, // RDGSBASE + 23555U, // RDGSBASE64 + 15524U, // RDMSR + 18516U, // RDPID32 + 18516U, // RDPID64 + 15912U, // RDPKRUr + 14944U, // RDPMC + 27491U, // RDRAND16r + 21530U, // RDRAND32r + 23257U, // RDRAND64r + 27455U, // RDSEED16r + 21501U, // RDSEED32r + 23152U, // RDSEED64r + 19693U, // RDSSPD + 23973U, // RDSSPQ + 14957U, // RDTSC + 15352U, // RDTSCP + 15056U, // REPNE_PREFIX + 15359U, // REP_PREFIX + 22343U, // RETIL + 24454U, // RETIQ + 28384U, // RETIW + 15248U, // RETL + 15463U, // RETQ + 15978U, // RETW + 14784U, // REX64_PREFIX + 224384U, // ROL16m1 + 226472U, // ROL16mCL + 1089399936U, // ROL16mi + 29397U, // ROL16r1 + 29864U, // ROL16rCL + 551873664U, // ROL16ri + 234831U, // ROL32m1 + 242632U, // ROL32mCL + 552523087U, // ROL32mi + 29237U, // ROL32r1 + 29640U, // ROL32rCL + 551867727U, // ROL32ri + 449760U, // ROL64m1 + 455736U, // ROL64mCL + 820960480U, // ROL64mi + 29317U, // ROL64r1 + 29752U, // ROL64rCL + 551869664U, // ROL64ri + 476269U, // ROL8m1 + 488280U, // ROL8mCL + 284083309U, // ROL8mi + 29157U, // ROL8r1 + 29528U, // ROL8rCL + 551863405U, // ROL8ri + 224661U, // ROR16m1 + 226516U, // ROR16mCL + 1089400213U, // ROR16mi + 29437U, // ROR16r1 + 29908U, // ROR16rCL + 551873941U, // ROR16ri + 235097U, // ROR32m1 + 242676U, // ROR32mCL + 552523353U, // ROR32mi + 29277U, // ROR32r1 + 29684U, // ROR32rCL + 551867993U, // ROR32ri + 450151U, // ROR64m1 + 455780U, // ROR64mCL + 820960871U, // ROR64mi + 29357U, // ROR64r1 + 29796U, // ROR64rCL + 551870055U, // ROR64ri + 476528U, // ROR8m1 + 488324U, // ROR8mCL + 284083568U, // ROR8mi + 29197U, // ROR8r1 + 29572U, // ROR8rCL + 551863664U, // ROR8ri + 832870378U, // RORX32mi + 283432938U, // RORX32ri + 834969854U, // RORX64mi + 283435262U, // RORX64ri + 77892480U, // ROUNDPDm + 283429760U, // ROUNDPDr + 77898900U, // ROUNDPSm + 283436180U, // ROUNDPSr + 885296904U, // ROUNDSDm + 851824392U, // ROUNDSDm_Int + 283430664U, // ROUNDSDr + 1088818952U, // ROUNDSDr_Int + 887400474U, // ROUNDSSm + 856025114U, // ROUNDSSm_Int + 283437082U, // ROUNDSSr + 1088825370U, // ROUNDSSr_Int + 15313U, // RSM + 665176U, // RSQRTPSm + 551839320U, // RSQRTPSr + 552200381U, // RSQRTSSm + 551725245U, // RSQRTSSm_Int + 551839933U, // RSQRTSSr + 8448189U, // RSQRTSSr_Int + 235753U, // RSTORSSP + 15111U, // SAHF + 224329U, // SAL16m1 + 226439U, // SAL16mCL + 4238409U, // SAL16mi + 29367U, // SAL16r1 + 29831U, // SAL16rCL + 8449097U, // SAL16ri + 234777U, // SAL32m1 + 242599U, // SAL32mCL + 12621081U, // SAL32mi + 29207U, // SAL32r1 + 29607U, // SAL32rCL + 8443161U, // SAL32ri + 449694U, // SAL64m1 + 455703U, // SAL64mCL + 18914462U, // SAL64mi + 29287U, // SAL64r1 + 29719U, // SAL64rCL + 8445086U, // SAL64ri + 476249U, // SAL8m1 + 488247U, // SAL8mCL + 23102553U, // SAL8mi + 29127U, // SAL8r1 + 29495U, // SAL8rCL + 8438873U, // SAL8ri + 14931U, // SALC + 224614U, // SAR16m1 + 226483U, // SAR16mCL + 1089400166U, // SAR16mi + 29407U, // SAR16r1 + 29875U, // SAR16rCL + 551873894U, // SAR16ri + 235062U, // SAR32m1 + 242643U, // SAR32mCL + 552523318U, // SAR32mi + 29247U, // SAR32r1 + 29651U, // SAR32rCL + 551867958U, // SAR32ri + 450110U, // SAR64m1 + 455747U, // SAR64mCL + 820960830U, // SAR64mi + 29327U, // SAR64r1 + 29763U, // SAR64rCL + 551870014U, // SAR64ri + 476496U, // SAR8m1 + 488291U, // SAR8mCL + 284083536U, // SAR8mi + 29167U, // SAR8r1 + 29539U, // SAR8rCL + 551863632U, // SAR8ri + 832903132U, // SARX32rm + 811653084U, // SARX32rr + 835002608U, // SARX64rm + 811655408U, // SARX64rr + 15421U, // SAVEPREVSSP + 2124373U, // SBB16i16 + 4237909U, // SBB16mi + 4237909U, // SBB16mi8 + 4237909U, // SBB16mr + 6351445U, // SBB16ri + 6351445U, // SBB16ri8 + 6367829U, // SBB16rm + 6351445U, // SBB16rr + 8448597U, // SBB16rr_REV + 10507129U, // SBB32i32 + 12620665U, // SBB32mi + 12620665U, // SBB32mi8 + 12620665U, // SBB32mr + 6345593U, // SBB32ri + 6345593U, // SBB32ri8 + 283202425U, // SBB32rm + 6345593U, // SBB32rr + 8442745U, // SBB32rr_REV + 16800132U, // SBB64i32 + 18913668U, // SBB64mi32 + 18913668U, // SBB64mi8 + 18913668U, // SBB64mr + 6347140U, // SBB64ri32 + 6347140U, // SBB64ri8 + 283220356U, // SBB64rm + 6347140U, // SBB64rr + 8444292U, // SBB64rr_REV + 20988851U, // SBB8i8 + 23102387U, // SBB8mi + 23102387U, // SBB8mi8 + 23102387U, // SBB8mr + 6341555U, // SBB8ri + 6341555U, // SBB8ri8 + 6407091U, // SBB8rm + 6341555U, // SBB8rr + 8438707U, // SBB8rr_REV + 21513625U, // SCASB + 11048599U, // SCASL + 17358521U, // SCASQ + 2698710U, // SCASW + 479627U, // SETAEm + 20875U, // SETAEr + 475984U, // SETAm + 17232U, // SETAr + 479649U, // SETBEm + 20897U, // SETBEr + 476699U, // SETBm + 17947U, // SETBr + 479753U, // SETEm + 21001U, // SETEr + 479686U, // SETGEm + 20934U, // SETGEr + 479816U, // SETGm + 21064U, // SETGr + 479702U, // SETLEm + 20950U, // SETLEr + 481101U, // SETLm + 22349U, // SETLr + 479722U, // SETNEm + 20970U, // SETNEr + 481401U, // SETNOm + 22649U, // SETNOr + 481479U, // SETNPm + 22727U, // SETNPr + 483833U, // SETNSm + 25081U, // SETNSr + 481408U, // SETOm + 22656U, // SETOr + 481523U, // SETPm + 22771U, // SETPr + 16219U, // SETSSBSY + 485630U, // SETSm + 26878U, // SETSr + 15033U, // SFENCE + 683708U, // SGDT16m + 677674U, // SGDT32m + 679785U, // SGDT64m + 8634381U, // SHA1MSG1rm + 8437773U, // SHA1MSG1rr + 8634470U, // SHA1MSG2rm + 8437862U, // SHA1MSG2rr + 8639001U, // SHA1NEXTErm + 8442393U, // SHA1NEXTErr + 593871230U, // SHA1RNDS4rmi + 1088815486U, // SHA1RNDS4rri + 8634391U, // SHA256MSG1rm + 8437783U, // SHA256MSG1rr + 8634480U, // SHA256MSG2rm + 8437872U, // SHA256MSG2rr + 8647040U, // SHA256RNDS2rm + 8450432U, // SHA256RNDS2rr + 224353U, // SHL16m1 + 226461U, // SHL16mCL + 1089399905U, // SHL16mi + 29387U, // SHL16r1 + 29853U, // SHL16rCL + 551873633U, // SHL16ri + 234797U, // SHL32m1 + 242621U, // SHL32mCL + 552523053U, // SHL32mi + 29227U, // SHL32r1 + 29629U, // SHL32rCL + 551867693U, // SHL32ri + 449708U, // SHL64m1 + 455725U, // SHL64mCL + 820960428U, // SHL64mi + 29307U, // SHL64r1 + 29741U, // SHL64rCL + 551869612U, // SHL64ri + 476263U, // SHL8m1 + 488269U, // SHL8mCL + 284083303U, // SHL8mi + 29147U, // SHL8r1 + 29517U, // SHL8rCL + 551863399U, // SHL8ri + 4240495U, // SHLD16mrCL + 1126476618U, // SHLD16mri8 + 8451183U, // SHLD16rrCL + 1088826186U, // SHLD16rri8 + 12628879U, // SHLD32mrCL + 589599756U, // SHLD32mri8 + 8450959U, // SHLD32rrCL + 1088820236U, // SHLD32rri8 + 18920447U, // SHLD64mrCL + 858036881U, // SHLD64mri8 + 8451071U, // SHLD64rrCL + 1088821905U, // SHLD64rri8 + 832903111U, // SHLX32rm + 811653063U, // SHLX32rr + 835002587U, // SHLX64rm + 811655387U, // SHLX64rr + 224641U, // SHR16m1 + 226505U, // SHR16mCL + 1089400193U, // SHR16mi + 29427U, // SHR16r1 + 29897U, // SHR16rCL + 551873921U, // SHR16ri + 235091U, // SHR32m1 + 242665U, // SHR32mCL + 552523347U, // SHR32mi + 29267U, // SHR32r1 + 29673U, // SHR32rCL + 551867987U, // SHR32ri + 450122U, // SHR64m1 + 455769U, // SHR64mCL + 820960842U, // SHR64mi + 29347U, // SHR64r1 + 29785U, // SHR64rCL + 551870026U, // SHR64ri + 476508U, // SHR8m1 + 488313U, // SHR8mCL + 284083548U, // SHR8mi + 29187U, // SHR8r1 + 29561U, // SHR8rCL + 551863644U, // SHR8ri + 4240507U, // SHRD16mrCL + 1126476664U, // SHRD16mri8 + 8451195U, // SHRD16rrCL + 1088826232U, // SHRD16rri8 + 12628891U, // SHRD32mrCL + 589599779U, // SHRD32mri8 + 8450971U, // SHRD32rrCL + 1088820259U, // SHRD32rri8 + 18920459U, // SHRD64mrCL + 858037040U, // SHRD64mri8 + 8451083U, // SHRD64rrCL + 1088822064U, // SHRD64rri8 + 832903139U, // SHRX32rm + 811653091U, // SHRX32rr + 835002615U, // SHRX64rm + 811655415U, // SHRX64rr + 568708048U, // SHUFPDrmi + 1088818128U, // SHUFPDrri + 568714468U, // SHUFPSrmi + 1088824548U, // SHUFPSrri + 683722U, // SIDT16m + 677688U, // SIDT32m + 679799U, // SIDT64m + 15330U, // SIN_F + 0U, // SIN_Fp32 + 0U, // SIN_Fp64 + 0U, // SIN_Fp80 + 16054U, // SKINIT + 224984U, // SLDT16m + 28376U, // SLDT16r + 22335U, // SLDT32r + 24446U, // SLDT64r + 17371U, // SLWPCB + 17371U, // SLWPCB64 + 225218U, // SMSW16m + 28610U, // SMSW16r + 22441U, // SMSW32r + 24732U, // SMSW64r + 658713U, // SQRTPDm + 551832857U, // SQRTPDr + 665177U, // SQRTPSm + 551839321U, // SQRTPSr + 552177629U, // SQRTSDm + 551702493U, // SQRTSDm_Int + 551833565U, // SQRTSDr + 8441821U, // SQRTSDr_Int + 552200382U, // SQRTSSm + 551725246U, // SQRTSSm_Int + 551839934U, // SQRTSSr + 8448190U, // SQRTSSr_Int + 15889U, // SQRT_F + 0U, // SQRT_Fp32 + 0U, // SQRT_Fp64 + 0U, // SQRT_Fp80 + 14909U, // STAC + 14963U, // STC + 14987U, // STD + 15138U, // STGI + 15153U, // STI + 237920U, // STMXCSR + 553749U, // STOSB + 570679U, // STOSL + 587128U, // STOSQ + 603385U, // STOSW + 28103U, // STR16r + 22136U, // STR32r + 24226U, // STR64r + 224711U, // STRm + 190724U, // ST_F32m + 202617U, // ST_F64m + 190067U, // ST_FP32m + 202233U, // ST_FP64m + 698714U, // ST_FP80m + 22777U, // ST_FPrr + 0U, // ST_Fp32m + 0U, // ST_Fp64m + 0U, // ST_Fp64m32 + 0U, // ST_Fp80m32 + 0U, // ST_Fp80m64 + 0U, // ST_FpP32m + 0U, // ST_FpP64m + 0U, // ST_FpP64m32 + 0U, // ST_FpP80m + 0U, // ST_FpP80m32 + 0U, // ST_FpP80m64 + 27028U, // ST_Frr + 2124485U, // SUB16i16 + 4238021U, // SUB16mi + 4238021U, // SUB16mi8 + 4238021U, // SUB16mr + 6351557U, // SUB16ri + 6351557U, // SUB16ri8 + 6367941U, // SUB16rm + 6351557U, // SUB16rr + 8448709U, // SUB16rr_REV + 10507144U, // SUB32i32 + 12620680U, // SUB32mi + 12620680U, // SUB32mi8 + 12620680U, // SUB32mr + 6345608U, // SUB32ri + 6345608U, // SUB32ri8 + 283202440U, // SUB32rm + 6345608U, // SUB32rr + 8442760U, // SUB32rr_REV + 16800169U, // SUB64i32 + 18913705U, // SUB64mi32 + 18913705U, // SUB64mi8 + 18913705U, // SUB64mr + 6347177U, // SUB64ri32 + 6347177U, // SUB64ri8 + 283220393U, // SUB64rm + 6347177U, // SUB64rr + 8444329U, // SUB64rr_REV + 20988859U, // SUB8i8 + 23102395U, // SUB8mi + 23102395U, // SUB8mi8 + 23102395U, // SUB8mr + 6341563U, // SUB8ri + 6341563U, // SUB8ri8 + 6407099U, // SUB8rm + 6341563U, // SUB8rr + 8438715U, // SUB8rr_REV + 8522425U, // SUBPDrm + 8440505U, // SUBPDrr + 8528822U, // SUBPSrm + 8446902U, // SUBPSrr + 190148U, // SUBR_F32m + 202300U, // SUBR_F64m + 222924U, // SUBR_FI16m + 235076U, // SUBR_FI32m + 22662U, // SUBR_FPrST0 + 24847U, // SUBR_FST0r + 0U, // SUBR_Fp32m + 0U, // SUBR_Fp64m + 0U, // SUBR_Fp64m32 + 0U, // SUBR_Fp80m32 + 0U, // SUBR_Fp80m64 + 0U, // SUBR_FpI16m32 + 0U, // SUBR_FpI16m64 + 0U, // SUBR_FpI16m80 + 0U, // SUBR_FpI32m32 + 0U, // SUBR_FpI32m64 + 0U, // SUBR_FpI32m80 + 28953U, // SUBR_FrST0 + 551702224U, // SUBSDrm + 551702224U, // SUBSDrm_Int + 8441552U, // SUBSDrr + 8441552U, // SUBSDrr_Int + 551725003U, // SUBSSrm + 551725003U, // SUBSSrm_Int + 8447947U, // SUBSSrr + 8447947U, // SUBSSrr_Int + 188784U, // SUB_F32m + 201607U, // SUB_F64m + 221559U, // SUB_FI16m + 234382U, // SUB_FI32m + 22745U, // SUB_FPrST0 + 18048U, // SUB_FST0r + 0U, // SUB_Fp32 + 0U, // SUB_Fp32m + 0U, // SUB_Fp64 + 0U, // SUB_Fp64m + 0U, // SUB_Fp64m32 + 0U, // SUB_Fp80 + 0U, // SUB_Fp80m32 + 0U, // SUB_Fp80m64 + 0U, // SUB_FpI16m32 + 0U, // SUB_FpI16m64 + 0U, // SUB_FpI16m80 + 0U, // SUB_FpI32m32 + 0U, // SUB_FpI32m64 + 0U, // SUB_FpI32m80 + 29012U, // SUB_FrST0 + 15769U, // SWAPGS + 15230U, // SYSCALL + 15507U, // SYSENTER + 15267U, // SYSEXIT + 15482U, // SYSEXIT64 + 15259U, // SYSRET + 15474U, // SYSRET64 + 551900105U, // T1MSKC32rm + 551834569U, // T1MSKC32rr + 551918065U, // T1MSKC64rm + 551836145U, // T1MSKC64rr + 2125608U, // TEST16i16 + 4239144U, // TEST16mi + 4239144U, // TEST16mi_alt + 4239144U, // TEST16mr + 551841576U, // TEST16ri + 551841576U, // TEST16ri_alt + 551841576U, // TEST16rr + 10508146U, // TEST32i32 + 12621682U, // TEST32mi + 12621682U, // TEST32mi_alt + 12621682U, // TEST32mr + 551835506U, // TEST32ri + 551835506U, // TEST32ri_alt + 551835506U, // TEST32rr + 16801761U, // TEST64i32 + 18915297U, // TEST64mi32 + 18915297U, // TEST64mi32_alt + 18915297U, // TEST64mr + 551837665U, // TEST64ri32 + 551837665U, // TEST64ri32_alt + 551837665U, // TEST64rr + 20989523U, // TEST8i8 + 23103059U, // TEST8mi + 23103059U, // TEST8mi_alt + 23103059U, // TEST8mr + 551831123U, // TEST8ri + 551831123U, // TEST8ri_alt + 551831123U, // TEST8rr + 20993U, // TPAUSE + 15901U, // TST_F + 0U, // TST_Fp32 + 0U, // TST_Fp64 + 0U, // TST_Fp80 + 438018U, // TZCNT16rm + 551841538U, // TZCNT16rr + 551901028U, // TZCNT32rm + 551835492U, // TZCNT32rr + 551919530U, // TZCNT64rm + 551837610U, // TZCNT64rr + 551900433U, // TZMSK32rm + 551834897U, // TZMSK32rr + 551918742U, // TZMSK64rm + 551836822U, // TZMSK64rr + 552177471U, // UCOMISDrm + 552177471U, // UCOMISDrm_Int + 551833407U, // UCOMISDrr + 551833407U, // UCOMISDrr_Int + 552200273U, // UCOMISSrm + 552200273U, // UCOMISSrm_Int + 551839825U, // UCOMISSrr + 551839825U, // UCOMISSrr_Int + 21194U, // UCOM_FIPr + 21136U, // UCOM_FIr + 15413U, // UCOM_FPPr + 22714U, // UCOM_FPr + 0U, // UCOM_FpIr32 + 0U, // UCOM_FpIr64 + 0U, // UCOM_FpIr80 + 0U, // UCOM_Fpr32 + 0U, // UCOM_Fpr64 + 0U, // UCOM_Fpr80 + 22564U, // UCOM_Fr + 14700U, // UD0 + 14715U, // UD1 + 14753U, // UD2 + 24877U, // UMONITOR16 + 24877U, // UMONITOR32 + 24877U, // UMONITOR64 + 26927U, // UMWAIT + 8522713U, // UNPCKHPDrm + 8440793U, // UNPCKHPDrr + 8529133U, // UNPCKHPSrm + 8447213U, // UNPCKHPSrr + 8522755U, // UNPCKLPDrm + 8440835U, // UNPCKLPDrr + 8529195U, // UNPCKLPSrm + 8447275U, // UNPCKLPSrr + 890184770U, // V4FMADDPSrm + 86991938U, // V4FMADDPSrmk + 89089090U, // V4FMADDPSrmkz + 890185701U, // V4FMADDSSrm + 86992869U, // V4FMADDSSrmk + 89090021U, // V4FMADDSSrmkz + 890184791U, // V4FNMADDPSrm + 86991959U, // V4FNMADDPSrmk + 89089111U, // V4FNMADDPSrmkz + 890185722U, // V4FNMADDSSrm + 86992890U, // V4FNMADDSSrmk + 89090042U, // V4FNMADDSSrmkz + 812616538U, // VADDPDYrm + 811649882U, // VADDPDYrr + 811731802U, // VADDPDZ128rm + 358763354U, // VADDPDZ128rmb + 1433389914U, // VADDPDZ128rmbk + 1164970842U, // VADDPDZ128rmbkz + 86985562U, // VADDPDZ128rmk + 890178394U, // VADDPDZ128rmkz + 811649882U, // VADDPDZ128rr + 87051098U, // VADDPDZ128rrk + 890276698U, // VADDPDZ128rrkz + 812616538U, // VADDPDZ256rm + 360860506U, // VADDPDZ256rmb + 1435487066U, // VADDPDZ256rmbk + 1167067994U, // VADDPDZ256rmbkz + 87083866U, // VADDPDZ256rmk + 890309466U, // VADDPDZ256rmkz + 811649882U, // VADDPDZ256rr + 87051098U, // VADDPDZ256rrk + 890276698U, // VADDPDZ256rrkz + 812731226U, // VADDPDZrm + 362957658U, // VADDPDZrmb + 1437584218U, // VADDPDZrmbk + 1169165146U, // VADDPDZrmbkz + 87133018U, // VADDPDZrmk + 890358618U, // VADDPDZrmkz + 811649882U, // VADDPDZrr + 812780378U, // VADDPDZrrb + 87182170U, // VADDPDZrrbk + 890407770U, // VADDPDZrrbkz + 87051098U, // VADDPDZrrk + 890276698U, // VADDPDZrrkz + 811731802U, // VADDPDrm + 811649882U, // VADDPDrr + 812622958U, // VADDPSYrm + 811656302U, // VADDPSYrr + 811738222U, // VADDPSZ128rm + 360883310U, // VADDPSZ128rmb + 1435690094U, // VADDPSZ128rmbk + 1167271022U, // VADDPSZ128rmbkz + 86991982U, // VADDPSZ128rmk + 890184814U, // VADDPSZ128rmkz + 811656302U, // VADDPSZ128rr + 87057518U, // VADDPSZ128rrk + 890283118U, // VADDPSZ128rrkz + 812622958U, // VADDPSZ256rm + 362980462U, // VADDPSZ256rmb + 1437787246U, // VADDPSZ256rmbk + 1169368174U, // VADDPSZ256rmbkz + 87090286U, // VADDPSZ256rmk + 890315886U, // VADDPSZ256rmkz + 811656302U, // VADDPSZ256rr + 87057518U, // VADDPSZ256rrk + 890283118U, // VADDPSZ256rrkz + 812737646U, // VADDPSZrm + 365077614U, // VADDPSZrmb + 1439884398U, // VADDPSZrmbk + 1171465326U, // VADDPSZrmbkz + 87139438U, // VADDPSZrmk + 890365038U, // VADDPSZrmkz + 811656302U, // VADDPSZrr + 812786798U, // VADDPSZrrb + 87188590U, // VADDPSZrrbk + 890414190U, // VADDPSZrrbkz + 87057518U, // VADDPSZrrk + 890283118U, // VADDPSZrrkz + 811738222U, // VADDPSrm + 811656302U, // VADDPSrr + 283266815U, // VADDSDZrm + 283266815U, // VADDSDZrm_Int + 1357893375U, // VADDSDZrm_Intk + 1089474303U, // VADDSDZrm_Intkz + 811650815U, // VADDSDZrr + 811650815U, // VADDSDZrr_Int + 87052031U, // VADDSDZrr_Intk + 890277631U, // VADDSDZrr_Intkz + 812781311U, // VADDSDZrrb_Int + 87183103U, // VADDSDZrrb_Intk + 890408703U, // VADDSDZrrb_Intkz + 283266815U, // VADDSDrm + 283266815U, // VADDSDrm_Int + 811650815U, // VADDSDrr + 811650815U, // VADDSDrr_Int + 283289617U, // VADDSSZrm + 283289617U, // VADDSSZrm_Int + 1358096401U, // VADDSSZrm_Intk + 1089677329U, // VADDSSZrm_Intkz + 811657233U, // VADDSSZrr + 811657233U, // VADDSSZrr_Int + 87058449U, // VADDSSZrr_Intk + 890284049U, // VADDSSZrr_Intkz + 812787729U, // VADDSSZrrb_Int + 87189521U, // VADDSSZrrb_Intk + 890415121U, // VADDSSZrrb_Intkz + 283289617U, // VADDSSrm + 283289617U, // VADDSSrm_Int + 811657233U, // VADDSSrr + 811657233U, // VADDSSrr_Int + 812616384U, // VADDSUBPDYrm + 811649728U, // VADDSUBPDYrr + 811731648U, // VADDSUBPDrm + 811649728U, // VADDSUBPDrr + 812622781U, // VADDSUBPSYrm + 811656125U, // VADDSUBPSYrr + 811738045U, // VADDSUBPSrm + 811656125U, // VADDSUBPSrr + 812870002U, // VAESDECLASTYrm + 811657586U, // VAESDECLASTYrr + 811854194U, // VAESDECLASTZ128rm + 811657586U, // VAESDECLASTZ128rr + 812870002U, // VAESDECLASTZ256rm + 811657586U, // VAESDECLASTZ256rr + 812886386U, // VAESDECLASTZrm + 811657586U, // VAESDECLASTZrr + 811854194U, // VAESDECLASTrm + 811657586U, // VAESDECLASTrr + 812861186U, // VAESDECYrm + 811648770U, // VAESDECYrr + 811845378U, // VAESDECZ128rm + 811648770U, // VAESDECZ128rr + 812861186U, // VAESDECZ256rm + 811648770U, // VAESDECZ256rr + 812877570U, // VAESDECZrm + 811648770U, // VAESDECZrr + 811845378U, // VAESDECrm + 811648770U, // VAESDECrr + 812870015U, // VAESENCLASTYrm + 811657599U, // VAESENCLASTYrr + 811854207U, // VAESENCLASTZ128rm + 811657599U, // VAESENCLASTZ128rr + 812870015U, // VAESENCLASTZ256rm + 811657599U, // VAESENCLASTZ256rr + 812886399U, // VAESENCLASTZrm + 811657599U, // VAESENCLASTZrr + 811854207U, // VAESENCLASTrm + 811657599U, // VAESENCLASTrr + 812861212U, // VAESENCYrm + 811648796U, // VAESENCYrr + 811845404U, // VAESENCZ128rm + 811648796U, // VAESENCZ128rr + 812861212U, // VAESENCZ256rm + 811648796U, // VAESENCZ256rr + 812877596U, // VAESENCZrm + 811648796U, // VAESENCZrr + 811845404U, // VAESENCrm + 811648796U, // VAESENCrr + 263955U, // VAESIMCrm + 551831315U, // VAESIMCrr + 830777753U, // VAESKEYGENASSIST128rm + 283437465U, // VAESKEYGENASSIST128rr + 1686489325U, // VALIGNDZ128rmbi + 1710475501U, // VALIGNDZ128rmbik + 1712589037U, // VALIGNDZ128rmbikz + 325437677U, // VALIGNDZ128rmi + 1983105261U, // VALIGNDZ128rmik + 1179912429U, // VALIGNDZ128rmikz + 1088817389U, // VALIGNDZ128rri + 2163132653U, // VALIGNDZ128rrik + 1357580525U, // VALIGNDZ128rrikz + 2491795693U, // VALIGNDZ256rmbi + 2515781869U, // VALIGNDZ256rmbik + 2517895405U, // VALIGNDZ256rmbikz + 375769325U, // VALIGNDZ256rmi + 1989396717U, // VALIGNDZ256rmik + 1186203885U, // VALIGNDZ256rmikz + 1088817389U, // VALIGNDZ256rri + 2163132653U, // VALIGNDZ256rrik + 1357580525U, // VALIGNDZ256rrikz + 2760231149U, // VALIGNDZrmbi + 2784217325U, // VALIGNDZrmbik + 2786330861U, // VALIGNDZrmbikz + 382060781U, // VALIGNDZrmi + 1995688173U, // VALIGNDZrmik + 1192495341U, // VALIGNDZrmikz + 1088817389U, // VALIGNDZrri + 2163132653U, // VALIGNDZrrik + 1357580525U, // VALIGNDZrrikz + 3013991766U, // VALIGNQZ128rmbi + 3073629526U, // VALIGNQZ128rmbik + 3075743062U, // VALIGNQZ128rmbikz + 325442902U, // VALIGNQZ128rmi + 1983110486U, // VALIGNQZ128rmik + 1179917654U, // VALIGNQZ128rmikz + 1088822614U, // VALIGNQZ128rri + 2163137878U, // VALIGNQZ128rrik + 1357585750U, // VALIGNQZ128rrikz + 1671814486U, // VALIGNQZ256rmbi + 1731452246U, // VALIGNQZ256rmbik + 1733565782U, // VALIGNQZ256rmbikz + 375774550U, // VALIGNQZ256rmi + 1989401942U, // VALIGNQZ256rmik + 1186209110U, // VALIGNQZ256rmikz + 1088822614U, // VALIGNQZ256rri + 2163137878U, // VALIGNQZ256rrik + 1357585750U, // VALIGNQZ256rrikz + 2477120854U, // VALIGNQZrmbi + 2536758614U, // VALIGNQZrmbik + 2538872150U, // VALIGNQZrmbikz + 382066006U, // VALIGNQZrmi + 1995693398U, // VALIGNQZrmik + 1192500566U, // VALIGNQZrmikz + 1088822614U, // VALIGNQZrri + 2163137878U, // VALIGNQZrrik + 1357585750U, // VALIGNQZrrikz + 812616775U, // VANDNPDYrm + 811650119U, // VANDNPDYrr + 811732039U, // VANDNPDZ128rm + 358763591U, // VANDNPDZ128rmb + 1433390151U, // VANDNPDZ128rmbk + 1164971079U, // VANDNPDZ128rmbkz + 86985799U, // VANDNPDZ128rmk + 890178631U, // VANDNPDZ128rmkz + 811650119U, // VANDNPDZ128rr + 87051335U, // VANDNPDZ128rrk + 890276935U, // VANDNPDZ128rrkz + 812616775U, // VANDNPDZ256rm + 360860743U, // VANDNPDZ256rmb + 1435487303U, // VANDNPDZ256rmbk + 1167068231U, // VANDNPDZ256rmbkz + 87084103U, // VANDNPDZ256rmk + 890309703U, // VANDNPDZ256rmkz + 811650119U, // VANDNPDZ256rr + 87051335U, // VANDNPDZ256rrk + 890276935U, // VANDNPDZ256rrkz + 812731463U, // VANDNPDZrm + 362957895U, // VANDNPDZrmb + 1437584455U, // VANDNPDZrmbk + 1169165383U, // VANDNPDZrmbkz + 87133255U, // VANDNPDZrmk + 890358855U, // VANDNPDZrmkz + 811650119U, // VANDNPDZrr + 87051335U, // VANDNPDZrrk + 890276935U, // VANDNPDZrrkz + 811732039U, // VANDNPDrm + 811650119U, // VANDNPDrr + 812623224U, // VANDNPSYrm + 811656568U, // VANDNPSYrr + 811738488U, // VANDNPSZ128rm + 360883576U, // VANDNPSZ128rmb + 1435690360U, // VANDNPSZ128rmbk + 1167271288U, // VANDNPSZ128rmbkz + 86992248U, // VANDNPSZ128rmk + 890185080U, // VANDNPSZ128rmkz + 811656568U, // VANDNPSZ128rr + 87057784U, // VANDNPSZ128rrk + 890283384U, // VANDNPSZ128rrkz + 812623224U, // VANDNPSZ256rm + 362980728U, // VANDNPSZ256rmb + 1437787512U, // VANDNPSZ256rmbk + 1169368440U, // VANDNPSZ256rmbkz + 87090552U, // VANDNPSZ256rmk + 890316152U, // VANDNPSZ256rmkz + 811656568U, // VANDNPSZ256rr + 87057784U, // VANDNPSZ256rrk + 890283384U, // VANDNPSZ256rrkz + 812737912U, // VANDNPSZrm + 365077880U, // VANDNPSZrmb + 1439884664U, // VANDNPSZrmbk + 1171465592U, // VANDNPSZrmbkz + 87139704U, // VANDNPSZrmk + 890365304U, // VANDNPSZrmkz + 811656568U, // VANDNPSZrr + 87057784U, // VANDNPSZrrk + 890283384U, // VANDNPSZrrkz + 811738488U, // VANDNPSrm + 811656568U, // VANDNPSrr + 812616557U, // VANDPDYrm + 811649901U, // VANDPDYrr + 811731821U, // VANDPDZ128rm + 358763373U, // VANDPDZ128rmb + 1433389933U, // VANDPDZ128rmbk + 1164970861U, // VANDPDZ128rmbkz + 86985581U, // VANDPDZ128rmk + 890178413U, // VANDPDZ128rmkz + 811649901U, // VANDPDZ128rr + 87051117U, // VANDPDZ128rrk + 890276717U, // VANDPDZ128rrkz + 812616557U, // VANDPDZ256rm + 360860525U, // VANDPDZ256rmb + 1435487085U, // VANDPDZ256rmbk + 1167068013U, // VANDPDZ256rmbkz + 87083885U, // VANDPDZ256rmk + 890309485U, // VANDPDZ256rmkz + 811649901U, // VANDPDZ256rr + 87051117U, // VANDPDZ256rrk + 890276717U, // VANDPDZ256rrkz + 812731245U, // VANDPDZrm + 362957677U, // VANDPDZrmb + 1437584237U, // VANDPDZrmbk + 1169165165U, // VANDPDZrmbkz + 87133037U, // VANDPDZrmk + 890358637U, // VANDPDZrmkz + 811649901U, // VANDPDZrr + 87051117U, // VANDPDZrrk + 890276717U, // VANDPDZrrkz + 811731821U, // VANDPDrm + 811649901U, // VANDPDrr + 812622977U, // VANDPSYrm + 811656321U, // VANDPSYrr + 811738241U, // VANDPSZ128rm + 360883329U, // VANDPSZ128rmb + 1435690113U, // VANDPSZ128rmbk + 1167271041U, // VANDPSZ128rmbkz + 86992001U, // VANDPSZ128rmk + 890184833U, // VANDPSZ128rmkz + 811656321U, // VANDPSZ128rr + 87057537U, // VANDPSZ128rrk + 890283137U, // VANDPSZ128rrkz + 812622977U, // VANDPSZ256rm + 362980481U, // VANDPSZ256rmb + 1437787265U, // VANDPSZ256rmbk + 1169368193U, // VANDPSZ256rmbkz + 87090305U, // VANDPSZ256rmk + 890315905U, // VANDPSZ256rmkz + 811656321U, // VANDPSZ256rr + 87057537U, // VANDPSZ256rrk + 890283137U, // VANDPSZ256rrkz + 812737665U, // VANDPSZrm + 365077633U, // VANDPSZrmb + 1439884417U, // VANDPSZrmbk + 1171465345U, // VANDPSZrmbkz + 87139457U, // VANDPSZrmk + 890365057U, // VANDPSZrmkz + 811656321U, // VANDPSZrr + 87057537U, // VANDPSZrrk + 890283137U, // VANDPSZrrkz + 811738241U, // VANDPSrm + 811656321U, // VANDPSrr + 811732006U, // VBLENDMPDZ128rm + 358763558U, // VBLENDMPDZ128rmb + 1164971046U, // VBLENDMPDZ128rmbk + 1164971046U, // VBLENDMPDZ128rmbkz + 890178598U, // VBLENDMPDZ128rmk + 890178598U, // VBLENDMPDZ128rmkz + 811650086U, // VBLENDMPDZ128rr + 890276902U, // VBLENDMPDZ128rrk + 890276902U, // VBLENDMPDZ128rrkz + 812616742U, // VBLENDMPDZ256rm + 360860710U, // VBLENDMPDZ256rmb + 1167068198U, // VBLENDMPDZ256rmbk + 1167068198U, // VBLENDMPDZ256rmbkz + 890309670U, // VBLENDMPDZ256rmk + 890309670U, // VBLENDMPDZ256rmkz + 811650086U, // VBLENDMPDZ256rr + 890276902U, // VBLENDMPDZ256rrk + 890276902U, // VBLENDMPDZ256rrkz + 812731430U, // VBLENDMPDZrm + 362957862U, // VBLENDMPDZrmb + 1169165350U, // VBLENDMPDZrmbk + 1169165350U, // VBLENDMPDZrmbkz + 890358822U, // VBLENDMPDZrmk + 890358822U, // VBLENDMPDZrmkz + 811650086U, // VBLENDMPDZrr + 890276902U, // VBLENDMPDZrrk + 890276902U, // VBLENDMPDZrrkz + 811738438U, // VBLENDMPSZ128rm + 360883526U, // VBLENDMPSZ128rmb + 1167271238U, // VBLENDMPSZ128rmbk + 1167271238U, // VBLENDMPSZ128rmbkz + 890185030U, // VBLENDMPSZ128rmk + 890185030U, // VBLENDMPSZ128rmkz + 811656518U, // VBLENDMPSZ128rr + 890283334U, // VBLENDMPSZ128rrk + 890283334U, // VBLENDMPSZ128rrkz + 812623174U, // VBLENDMPSZ256rm + 362980678U, // VBLENDMPSZ256rmb + 1169368390U, // VBLENDMPSZ256rmbk + 1169368390U, // VBLENDMPSZ256rmbkz + 890316102U, // VBLENDMPSZ256rmk + 890316102U, // VBLENDMPSZ256rmkz + 811656518U, // VBLENDMPSZ256rr + 890283334U, // VBLENDMPSZ256rrk + 890283334U, // VBLENDMPSZ256rrkz + 812737862U, // VBLENDMPSZrm + 365077830U, // VBLENDMPSZrmb + 1171465542U, // VBLENDMPSZrmbk + 1171465542U, // VBLENDMPSZrmbkz + 890365254U, // VBLENDMPSZrmk + 890365254U, // VBLENDMPSZrmkz + 811656518U, // VBLENDMPSZrr + 890283334U, // VBLENDMPSZrrk + 890283334U, // VBLENDMPSZrrkz + 392547189U, // VBLENDPDYrmi + 1088818037U, // VBLENDPDYrri + 300272501U, // VBLENDPDrmi + 1088818037U, // VBLENDPDrri + 392553609U, // VBLENDPSYrmi + 1088824457U, // VBLENDPSYrri + 300278921U, // VBLENDPSrmi + 1088824457U, // VBLENDPSrri + 393497907U, // VBLENDVPDYrm + 890277171U, // VBLENDVPDYrr + 301223219U, // VBLENDVPDrm + 890277171U, // VBLENDVPDrr + 393504404U, // VBLENDVPSYrm + 890283668U, // VBLENDVPSYrr + 301229716U, // VBLENDVPSrm + 890283668U, // VBLENDVPSrr + 656011U, // VBROADCASTF128 + 552173714U, // VBROADCASTF32X2Z256m + 552599698U, // VBROADCASTF32X2Z256mk + 551698578U, // VBROADCASTF32X2Z256mkz + 551829650U, // VBROADCASTF32X2Z256r + 3230695570U, // VBROADCASTF32X2Z256rk + 3229663378U, // VBROADCASTF32X2Z256rkz + 552173714U, // VBROADCASTF32X2Zm + 552599698U, // VBROADCASTF32X2Zmk + 551698578U, // VBROADCASTF32X2Zmkz + 551829650U, // VBROADCASTF32X2Zr + 3230695570U, // VBROADCASTF32X2Zrk + 3229663378U, // VBROADCASTF32X2Zrkz + 655794U, // VBROADCASTF32X4Z256rm + 3230597554U, // VBROADCASTF32X4Z256rmk + 3229745586U, // VBROADCASTF32X4Z256rmkz + 655794U, // VBROADCASTF32X4rm + 3230597554U, // VBROADCASTF32X4rmk + 3229745586U, // VBROADCASTF32X4rmkz + 1344249U, // VBROADCASTF32X8rm + 3230728953U, // VBROADCASTF32X8rmk + 3230630649U, // VBROADCASTF32X8rmkz + 655581U, // VBROADCASTF64X2Z128rm + 3230597341U, // VBROADCASTF64X2Z128rmk + 3229745373U, // VBROADCASTF64X2Z128rmkz + 655581U, // VBROADCASTF64X2rm + 3230597341U, // VBROADCASTF64X2rmk + 3229745373U, // VBROADCASTF64X2rmkz + 1344026U, // VBROADCASTF64X4rm + 3230728730U, // VBROADCASTF64X4rmk + 3230630426U, // VBROADCASTF64X4rmkz + 262850U, // VBROADCASTI128 + 551911587U, // VBROADCASTI32X2Z128m + 552911011U, // VBROADCASTI32X2Z128mk + 551649443U, // VBROADCASTI32X2Z128mkz + 551829667U, // VBROADCASTI32X2Z128r + 3230695587U, // VBROADCASTI32X2Z128rk + 3229663395U, // VBROADCASTI32X2Z128rkz + 551911587U, // VBROADCASTI32X2Z256m + 552911011U, // VBROADCASTI32X2Z256mk + 551649443U, // VBROADCASTI32X2Z256mkz + 551829667U, // VBROADCASTI32X2Z256r + 3230695587U, // VBROADCASTI32X2Z256rk + 3229663395U, // VBROADCASTI32X2Z256rkz + 551911587U, // VBROADCASTI32X2Zm + 552911011U, // VBROADCASTI32X2Zmk + 551649443U, // VBROADCASTI32X2Zmkz + 551829667U, // VBROADCASTI32X2Zr + 3230695587U, // VBROADCASTI32X2Zrk + 3229663395U, // VBROADCASTI32X2Zrkz + 262636U, // VBROADCASTI32X4Z256rm + 3230990828U, // VBROADCASTI32X4Z256rmk + 3229860332U, // VBROADCASTI32X4Z256rmkz + 262636U, // VBROADCASTI32X4rm + 3230990828U, // VBROADCASTI32X4rmk + 3229860332U, // VBROADCASTI32X4rmkz + 552944423U, // VBROADCASTI32X8rm + 3231023911U, // VBROADCASTI32X8rmk + 3230876455U, // VBROADCASTI32X8rmkz + 262423U, // VBROADCASTI64X2Z128rm + 3230990615U, // VBROADCASTI64X2Z128rmk + 3229860119U, // VBROADCASTI64X2Z128rmkz + 262423U, // VBROADCASTI64X2rm + 3230990615U, // VBROADCASTI64X2rmk + 3229860119U, // VBROADCASTI64X2rmkz + 552944200U, // VBROADCASTI64X4rm + 3231023688U, // VBROADCASTI64X4rmk + 3230876232U, // VBROADCASTI64X4rmkz + 552177637U, // VBROADCASTSDYrm + 551833573U, // VBROADCASTSDYrr + 552177637U, // VBROADCASTSDZ256m + 552603621U, // VBROADCASTSDZ256mk + 551702501U, // VBROADCASTSDZ256mkz + 551833573U, // VBROADCASTSDZ256r + 3230699493U, // VBROADCASTSDZ256rk + 3229667301U, // VBROADCASTSDZ256rkz + 552177637U, // VBROADCASTSDZm + 552603621U, // VBROADCASTSDZmk + 551702501U, // VBROADCASTSDZmkz + 551833573U, // VBROADCASTSDZr + 3230699493U, // VBROADCASTSDZrk + 3229667301U, // VBROADCASTSDZrkz + 552200399U, // VBROADCASTSSYrm + 551839951U, // VBROADCASTSSYrr + 552200399U, // VBROADCASTSSZ128m + 552806607U, // VBROADCASTSSZ128mk + 551725263U, // VBROADCASTSSZ128mkz + 551839951U, // VBROADCASTSSZ128r + 3230705871U, // VBROADCASTSSZ128rk + 3229673679U, // VBROADCASTSSZ128rkz + 552200399U, // VBROADCASTSSZ256m + 552806607U, // VBROADCASTSSZ256mk + 551725263U, // VBROADCASTSSZ256mkz + 551839951U, // VBROADCASTSSZ256r + 3230705871U, // VBROADCASTSSZ256rk + 3229673679U, // VBROADCASTSSZ256rkz + 552200399U, // VBROADCASTSSZm + 552806607U, // VBROADCASTSSZmk + 551725263U, // VBROADCASTSSZmkz + 551839951U, // VBROADCASTSSZr + 3230705871U, // VBROADCASTSSZrk + 3229673679U, // VBROADCASTSSZrkz + 552200399U, // VBROADCASTSSrm + 551839951U, // VBROADCASTSSrr + 3530030089U, // VCMPPDYrmi + 392547423U, // VCMPPDYrmi_alt + 1114127369U, // VCMPPDYrri + 1088818271U, // VCMPPDYrri_alt + 2456288265U, // VCMPPDZ128rmbi + 2999307359U, // VCMPPDZ128rmbi_alt + 3079933023U, // VCMPPDZ128rmbi_altk + 3799383049U, // VCMPPDZ128rmbik + 1919417353U, // VCMPPDZ128rmi + 300272735U, // VCMPPDZ128rmi_alt + 1202981983U, // VCMPPDZ128rmi_altk + 4067818505U, // VCMPPDZ128rmik + 1114127369U, // VCMPPDZ128rri + 1088818271U, // VCMPPDZ128rri_alt + 1357581407U, // VCMPPDZ128rri_altk + 1383480329U, // VCMPPDZ128rrik + 2456288265U, // VCMPPDZ256rmbi + 1657130079U, // VCMPPDZ256rmbi_alt + 1737755743U, // VCMPPDZ256rmbi_altk + 3799383049U, // VCMPPDZ256rmbik + 3530030089U, // VCMPPDZ256rmi + 392547423U, // VCMPPDZ256rmi_alt + 1205079135U, // VCMPPDZ256rmi_altk + 41286665U, // VCMPPDZ256rmik + 1114127369U, // VCMPPDZ256rri + 1088818271U, // VCMPPDZ256rri_alt + 1357581407U, // VCMPPDZ256rri_altk + 1383480329U, // VCMPPDZ256rrik + 2456288265U, // VCMPPDZrmbi + 2462436447U, // VCMPPDZrmbi_alt + 2543062111U, // VCMPPDZrmbi_altk + 3799383049U, // VCMPPDZrmbik + 308804617U, // VCMPPDZrmi + 400936031U, // VCMPPDZrmi_alt + 1209273439U, // VCMPPDZrmi_altk + 578157577U, // VCMPPDZrmik + 1114127369U, // VCMPPDZrri + 1088818271U, // VCMPPDZrri_alt + 1357581407U, // VCMPPDZrri_altk + 1210596361U, // VCMPPDZrrib + 1212550239U, // VCMPPDZrrib_alt + 1481313375U, // VCMPPDZrrib_altk + 1479949321U, // VCMPPDZrribk + 1383480329U, // VCMPPDZrrik + 1919417353U, // VCMPPDrmi + 300272735U, // VCMPPDrmi_alt + 1114127369U, // VCMPPDrri + 1088818271U, // VCMPPDrri_alt + 3532127241U, // VCMPPSYrmi + 392553880U, // VCMPPSYrmi_alt + 1116224521U, // VCMPPSYrri + 1088824728U, // VCMPPSYrri_alt + 3263691785U, // VCMPPSZ128rmbi + 1661330840U, // VCMPPSZ128rmbi_alt + 1752442264U, // VCMPPSZ128rmbi_altk + 848690185U, // VCMPPSZ128rmbik + 1921514505U, // VCMPPSZ128rmi + 300279192U, // VCMPPSZ128rmi_alt + 1202988440U, // VCMPPSZ128rmi_altk + 4069915657U, // VCMPPSZ128rmik + 1116224521U, // VCMPPSZ128rri + 1088824728U, // VCMPPSZ128rri_alt + 1357587864U, // VCMPPSZ128rri_altk + 1385577481U, // VCMPPSZ128rrik + 3263691785U, // VCMPPSZ256rmbi + 2466637208U, // VCMPPSZ256rmbi_alt + 2557748632U, // VCMPPSZ256rmbi_altk + 848690185U, // VCMPPSZ256rmbik + 3532127241U, // VCMPPSZ256rmi + 392553880U, // VCMPPSZ256rmi_alt + 1205085592U, // VCMPPSZ256rmi_altk + 43383817U, // VCMPPSZ256rmik + 1116224521U, // VCMPPSZ256rri + 1088824728U, // VCMPPSZ256rri_alt + 1357587864U, // VCMPPSZ256rri_altk + 1385577481U, // VCMPPSZ256rrik + 3263691785U, // VCMPPSZrmbi + 2735072664U, // VCMPPSZrmbi_alt + 2826184088U, // VCMPPSZrmbi_altk + 848690185U, // VCMPPSZrmbik + 310901769U, // VCMPPSZrmi + 400942488U, // VCMPPSZrmi_alt + 1209279896U, // VCMPPSZrmi_altk + 580254729U, // VCMPPSZrmik + 1116224521U, // VCMPPSZrri + 1088824728U, // VCMPPSZrri_alt + 1357587864U, // VCMPPSZrri_altk + 1216887817U, // VCMPPSZrrib + 1212556696U, // VCMPPSZrrib_alt + 1481319832U, // VCMPPSZrrib_altk + 1486240777U, // VCMPPSZrribk + 1385577481U, // VCMPPSZrrik + 1921514505U, // VCMPPSrmi + 300279192U, // VCMPPSrmi_alt + 1116224521U, // VCMPPSrri + 1088824728U, // VCMPPSrri_alt + 2460482569U, // VCMPSDZrm + 2460482569U, // VCMPSDZrm_Int + 3803577353U, // VCMPSDZrm_Intk + 851824503U, // VCMPSDZrmi_alt + 932450167U, // VCMPSDZrmi_altk + 1118321673U, // VCMPSDZrr + 1118321673U, // VCMPSDZrr_Int + 1387674633U, // VCMPSDZrr_Intk + 1218984969U, // VCMPSDZrrb_Int + 1488337929U, // VCMPSDZrrb_Intk + 1212551031U, // VCMPSDZrrb_alt + 1481314167U, // VCMPSDZrrb_altk + 1088819063U, // VCMPSDZrri_alt + 1357582199U, // VCMPSDZrri_altk + 2460482569U, // VCMPSDrm + 2460482569U, // VCMPSDrm_Int + 851824503U, // VCMPSDrm_alt + 1118321673U, // VCMPSDrr + 1118321673U, // VCMPSDrr_Int + 1088819063U, // VCMPSDrr_alt + 3269983241U, // VCMPSSZrm + 3269983241U, // VCMPSSZrm_Int + 854981641U, // VCMPSSZrm_Intk + 856025224U, // VCMPSSZrmi_alt + 947136648U, // VCMPSSZrmi_altk + 1122515977U, // VCMPSSZrr + 1122515977U, // VCMPSSZrr_Int + 1391868937U, // VCMPSSZrr_Intk + 1221082121U, // VCMPSSZrrb_Int + 1490435081U, // VCMPSSZrrb_Intk + 1212557448U, // VCMPSSZrrb_alt + 1481320584U, // VCMPSSZrrb_altk + 1088825480U, // VCMPSSZrri_alt + 1357588616U, // VCMPSSZrri_altk + 3269983241U, // VCMPSSrm + 3269983241U, // VCMPSSrm_Int + 856025224U, // VCMPSSrm_alt + 1122515977U, // VCMPSSrr + 1122515977U, // VCMPSSrr_Int + 1088825480U, // VCMPSSrr_alt + 552177480U, // VCOMISDZrm + 552177480U, // VCOMISDZrm_Int + 551833416U, // VCOMISDZrr + 551833416U, // VCOMISDZrr_Int + 551843439U, // VCOMISDZrrb + 552177480U, // VCOMISDrm + 552177480U, // VCOMISDrm_Int + 551833416U, // VCOMISDrr + 551833416U, // VCOMISDrr_Int + 552200282U, // VCOMISSZrm + 552200282U, // VCOMISSZrm_Int + 551839834U, // VCOMISSZrr + 551839834U, // VCOMISSZrr_Int + 551843908U, // VCOMISSZrrb + 552200282U, // VCOMISSrm + 552200282U, // VCOMISSrm_Int + 551839834U, // VCOMISSrr + 551839834U, // VCOMISSrr_Int + 65047797U, // VCOMPRESSPDZ128mr + 3286568181U, // VCOMPRESSPDZ128mrk + 551832821U, // VCOMPRESSPDZ128rr + 3230698741U, // VCOMPRESSPDZ128rrk + 3229666549U, // VCOMPRESSPDZ128rrkz + 148933877U, // VCOMPRESSPDZ256mr + 3370454261U, // VCOMPRESSPDZ256mrk + 551832821U, // VCOMPRESSPDZ256rr + 3230698741U, // VCOMPRESSPDZ256rrk + 3229666549U, // VCOMPRESSPDZ256rrkz + 151031029U, // VCOMPRESSPDZmr + 3372551413U, // VCOMPRESSPDZmrk + 551832821U, // VCOMPRESSPDZrr + 3230698741U, // VCOMPRESSPDZrrk + 3229666549U, // VCOMPRESSPDZrrkz + 65054237U, // VCOMPRESSPSZ128mr + 3286574621U, // VCOMPRESSPSZ128mrk + 551839261U, // VCOMPRESSPSZ128rr + 3230705181U, // VCOMPRESSPSZ128rrk + 3229672989U, // VCOMPRESSPSZ128rrkz + 148940317U, // VCOMPRESSPSZ256mr + 3370460701U, // VCOMPRESSPSZ256mrk + 551839261U, // VCOMPRESSPSZ256rr + 3230705181U, // VCOMPRESSPSZ256rrk + 3229672989U, // VCOMPRESSPSZ256rrkz + 151037469U, // VCOMPRESSPSZmr + 3372557853U, // VCOMPRESSPSZmrk + 551839261U, // VCOMPRESSPSZrr + 3230705181U, // VCOMPRESSPSZrrk + 3229672989U, // VCOMPRESSPSZrrkz + 264668U, // VCVTDQ2PDYrm + 551832028U, // VCVTDQ2PDYrr + 551913948U, // VCVTDQ2PDZ128rm + 627395036U, // VCVTDQ2PDZ128rmb + 628509148U, // VCVTDQ2PDZ128rmbk + 627132892U, // VCVTDQ2PDZ128rmbkz + 552913372U, // VCVTDQ2PDZ128rmk + 551651804U, // VCVTDQ2PDZ128rmkz + 551832028U, // VCVTDQ2PDZ128rr + 3230697948U, // VCVTDQ2PDZ128rrk + 3229665756U, // VCVTDQ2PDZ128rrkz + 264668U, // VCVTDQ2PDZ256rm + 629492188U, // VCVTDQ2PDZ256rmb + 630606300U, // VCVTDQ2PDZ256rmbk + 629230044U, // VCVTDQ2PDZ256rmbkz + 3230992860U, // VCVTDQ2PDZ256rmk + 3229862364U, // VCVTDQ2PDZ256rmkz + 551832028U, // VCVTDQ2PDZ256rr + 3230697948U, // VCVTDQ2PDZ256rrk + 3229665756U, // VCVTDQ2PDZ256rrkz + 552946140U, // VCVTDQ2PDZrm + 631589340U, // VCVTDQ2PDZrmb + 632703452U, // VCVTDQ2PDZrmbk + 631327196U, // VCVTDQ2PDZrmbkz + 3231025628U, // VCVTDQ2PDZrmk + 3230878172U, // VCVTDQ2PDZrmkz + 551832028U, // VCVTDQ2PDZrr + 3230697948U, // VCVTDQ2PDZrrk + 3229665756U, // VCVTDQ2PDZrrkz + 551913948U, // VCVTDQ2PDrm + 551832028U, // VCVTDQ2PDrr + 552952556U, // VCVTDQ2PSYrm + 551838444U, // VCVTDQ2PSYrr + 271084U, // VCVTDQ2PSZ128rm + 629498604U, // VCVTDQ2PSZ128rmb + 630612716U, // VCVTDQ2PSZ128rmbk + 629236460U, // VCVTDQ2PSZ128rmbkz + 3230999276U, // VCVTDQ2PSZ128rmk + 3229868780U, // VCVTDQ2PSZ128rmkz + 551838444U, // VCVTDQ2PSZ128rr + 3230704364U, // VCVTDQ2PSZ128rrk + 3229672172U, // VCVTDQ2PSZ128rrkz + 552952556U, // VCVTDQ2PSZ256rm + 631595756U, // VCVTDQ2PSZ256rmb + 632709868U, // VCVTDQ2PSZ256rmbk + 631333612U, // VCVTDQ2PSZ256rmbkz + 3231032044U, // VCVTDQ2PSZ256rmk + 3230884588U, // VCVTDQ2PSZ256rmkz + 551838444U, // VCVTDQ2PSZ256rr + 3230704364U, // VCVTDQ2PSZ256rrk + 3229672172U, // VCVTDQ2PSZ256rrkz + 552444652U, // VCVTDQ2PSZrm + 633692908U, // VCVTDQ2PSZrmb + 634807020U, // VCVTDQ2PSZrmbk + 633430764U, // VCVTDQ2PSZrmbkz + 3231097580U, // VCVTDQ2PSZrmk + 3230900972U, // VCVTDQ2PSZrmkz + 551838444U, // VCVTDQ2PSZrr + 1499884U, // VCVTDQ2PSZrrb + 3230835436U, // VCVTDQ2PSZrrbk + 3230802668U, // VCVTDQ2PSZrrbkz + 3230704364U, // VCVTDQ2PSZrrk + 3229672172U, // VCVTDQ2PSZrrkz + 271084U, // VCVTDQ2PSrm + 551838444U, // VCVTDQ2PSrr + 1355912U, // VCVTPD2DQYrm + 551836178U, // VCVTPD2DQYrr + 667661U, // VCVTPD2DQZ128rm + 627677714U, // VCVTPD2DQZ128rmb + 628103698U, // VCVTPD2DQZ128rmbk + 627202578U, // VCVTPD2DQZ128rmbkz + 3230609421U, // VCVTPD2DQZ128rmk + 3229757453U, // VCVTPD2DQZ128rmkz + 551836178U, // VCVTPD2DQZ128rr + 3230702098U, // VCVTPD2DQZ128rrk + 3229669906U, // VCVTPD2DQZ128rrkz + 1355912U, // VCVTPD2DQZ256rm + 629774866U, // VCVTPD2DQZ256rmb + 630200850U, // VCVTPD2DQZ256rmbk + 629299730U, // VCVTPD2DQZ256rmbkz + 3230740616U, // VCVTPD2DQZ256rmk + 3230642312U, // VCVTPD2DQZ256rmkz + 551836178U, // VCVTPD2DQZ256rr + 3230702098U, // VCVTPD2DQZ256rrk + 3229669906U, // VCVTPD2DQZ256rrkz + 1514002U, // VCVTPD2DQZrm + 631872018U, // VCVTPD2DQZrmb + 632298002U, // VCVTPD2DQZrmbk + 631396882U, // VCVTPD2DQZrmbkz + 3230784018U, // VCVTPD2DQZrmk + 3230751250U, // VCVTPD2DQZrmkz + 551836178U, // VCVTPD2DQZrr + 1497618U, // VCVTPD2DQZrrb + 3230833170U, // VCVTPD2DQZrrbk + 3230800402U, // VCVTPD2DQZrrbkz + 3230702098U, // VCVTPD2DQZrrk + 3229669906U, // VCVTPD2DQZrrkz + 667661U, // VCVTPD2DQrm + 551836178U, // VCVTPD2DQrr + 1355961U, // VCVTPD2PSYrm + 551838380U, // VCVTPD2PSYrr + 667700U, // VCVTPD2PSZ128rm + 627679916U, // VCVTPD2PSZ128rmb + 628105900U, // VCVTPD2PSZ128rmbk + 627204780U, // VCVTPD2PSZ128rmbkz + 3230609460U, // VCVTPD2PSZ128rmk + 3229757492U, // VCVTPD2PSZ128rmkz + 551838380U, // VCVTPD2PSZ128rr + 3230704300U, // VCVTPD2PSZ128rrk + 3229672108U, // VCVTPD2PSZ128rrkz + 1355961U, // VCVTPD2PSZ256rm + 629777068U, // VCVTPD2PSZ256rmb + 630203052U, // VCVTPD2PSZ256rmbk + 629301932U, // VCVTPD2PSZ256rmbkz + 3230740665U, // VCVTPD2PSZ256rmk + 3230642361U, // VCVTPD2PSZ256rmkz + 551838380U, // VCVTPD2PSZ256rr + 3230704300U, // VCVTPD2PSZ256rrk + 3229672108U, // VCVTPD2PSZ256rrkz + 1516204U, // VCVTPD2PSZrm + 631874220U, // VCVTPD2PSZrmb + 632300204U, // VCVTPD2PSZrmbk + 631399084U, // VCVTPD2PSZrmbkz + 3230786220U, // VCVTPD2PSZrmk + 3230753452U, // VCVTPD2PSZrmkz + 551838380U, // VCVTPD2PSZrr + 1499820U, // VCVTPD2PSZrrb + 3230835372U, // VCVTPD2PSZrrbk + 3230802604U, // VCVTPD2PSZrrbkz + 3230704300U, // VCVTPD2PSZrrk + 3229672108U, // VCVTPD2PSZrrkz + 667700U, // VCVTPD2PSrm + 551838380U, // VCVTPD2PSrr + 662977U, // VCVTPD2QQZ128rm + 627678657U, // VCVTPD2QQZ128rmb + 628104641U, // VCVTPD2QQZ128rmbk + 627203521U, // VCVTPD2QQZ128rmbkz + 3230604737U, // VCVTPD2QQZ128rmk + 3229752769U, // VCVTPD2QQZ128rmkz + 551837121U, // VCVTPD2QQZ128rr + 3230703041U, // VCVTPD2QQZ128rrk + 3229670849U, // VCVTPD2QQZ128rrkz + 1351105U, // VCVTPD2QQZ256rm + 629775809U, // VCVTPD2QQZ256rmb + 630201793U, // VCVTPD2QQZ256rmbk + 629300673U, // VCVTPD2QQZ256rmbkz + 3230735809U, // VCVTPD2QQZ256rmk + 3230637505U, // VCVTPD2QQZ256rmkz + 551837121U, // VCVTPD2QQZ256rr + 3230703041U, // VCVTPD2QQZ256rrk + 3229670849U, // VCVTPD2QQZ256rrkz + 1514945U, // VCVTPD2QQZrm + 631872961U, // VCVTPD2QQZrmb + 632298945U, // VCVTPD2QQZrmbk + 631397825U, // VCVTPD2QQZrmbkz + 3230784961U, // VCVTPD2QQZrmk + 3230752193U, // VCVTPD2QQZrmkz + 551837121U, // VCVTPD2QQZrr + 1498561U, // VCVTPD2QQZrrb + 3230834113U, // VCVTPD2QQZrrbk + 3230801345U, // VCVTPD2QQZrrbkz + 3230703041U, // VCVTPD2QQZrrk + 3229670849U, // VCVTPD2QQZrrkz + 667687U, // VCVTPD2UDQZ128rm + 627678055U, // VCVTPD2UDQZ128rmb + 628104039U, // VCVTPD2UDQZ128rmbk + 627202919U, // VCVTPD2UDQZ128rmbkz + 3230609447U, // VCVTPD2UDQZ128rmk + 3229757479U, // VCVTPD2UDQZ128rmkz + 551836519U, // VCVTPD2UDQZ128rr + 3230702439U, // VCVTPD2UDQZ128rrk + 3229670247U, // VCVTPD2UDQZ128rrkz + 1355938U, // VCVTPD2UDQZ256rm + 629775207U, // VCVTPD2UDQZ256rmb + 630201191U, // VCVTPD2UDQZ256rmbk + 629300071U, // VCVTPD2UDQZ256rmbkz + 3230740642U, // VCVTPD2UDQZ256rmk + 3230642338U, // VCVTPD2UDQZ256rmkz + 551836519U, // VCVTPD2UDQZ256rr + 3230702439U, // VCVTPD2UDQZ256rrk + 3229670247U, // VCVTPD2UDQZ256rrkz + 1514343U, // VCVTPD2UDQZrm + 631872359U, // VCVTPD2UDQZrmb + 632298343U, // VCVTPD2UDQZrmbk + 631397223U, // VCVTPD2UDQZrmbkz + 3230784359U, // VCVTPD2UDQZrmk + 3230751591U, // VCVTPD2UDQZrmkz + 551836519U, // VCVTPD2UDQZrr + 1497959U, // VCVTPD2UDQZrrb + 3230833511U, // VCVTPD2UDQZrrbk + 3230800743U, // VCVTPD2UDQZrrbkz + 3230702439U, // VCVTPD2UDQZrrk + 3229670247U, // VCVTPD2UDQZrrkz + 663059U, // VCVTPD2UQQZ128rm + 627678739U, // VCVTPD2UQQZ128rmb + 628104723U, // VCVTPD2UQQZ128rmbk + 627203603U, // VCVTPD2UQQZ128rmbkz + 3230604819U, // VCVTPD2UQQZ128rmk + 3229752851U, // VCVTPD2UQQZ128rmkz + 551837203U, // VCVTPD2UQQZ128rr + 3230703123U, // VCVTPD2UQQZ128rrk + 3229670931U, // VCVTPD2UQQZ128rrkz + 1351187U, // VCVTPD2UQQZ256rm + 629775891U, // VCVTPD2UQQZ256rmb + 630201875U, // VCVTPD2UQQZ256rmbk + 629300755U, // VCVTPD2UQQZ256rmbkz + 3230735891U, // VCVTPD2UQQZ256rmk + 3230637587U, // VCVTPD2UQQZ256rmkz + 551837203U, // VCVTPD2UQQZ256rr + 3230703123U, // VCVTPD2UQQZ256rrk + 3229670931U, // VCVTPD2UQQZ256rrkz + 1515027U, // VCVTPD2UQQZrm + 631873043U, // VCVTPD2UQQZrmb + 632299027U, // VCVTPD2UQQZrmbk + 631397907U, // VCVTPD2UQQZrmbkz + 3230785043U, // VCVTPD2UQQZrmk + 3230752275U, // VCVTPD2UQQZrmkz + 551837203U, // VCVTPD2UQQZrr + 1498643U, // VCVTPD2UQQZrrb + 3230834195U, // VCVTPD2UQQZrrbk + 3230801427U, // VCVTPD2UQQZrrbkz + 3230703123U, // VCVTPD2UQQZrrk + 3229670931U, // VCVTPD2UQQZrrkz + 664247U, // VCVTPH2PSYrm + 551838391U, // VCVTPH2PSYrr + 552182455U, // VCVTPH2PSZ128rm + 552608439U, // VCVTPH2PSZ128rmk + 551707319U, // VCVTPH2PSZ128rmkz + 551838391U, // VCVTPH2PSZ128rr + 3230704311U, // VCVTPH2PSZ128rrk + 3229672119U, // VCVTPH2PSZ128rrkz + 664247U, // VCVTPH2PSZ256rm + 3230606007U, // VCVTPH2PSZ256rmk + 3229754039U, // VCVTPH2PSZ256rmkz + 551838391U, // VCVTPH2PSZ256rr + 3230704311U, // VCVTPH2PSZ256rrk + 3229672119U, // VCVTPH2PSZ256rrkz + 1352375U, // VCVTPH2PSZrm + 3230737079U, // VCVTPH2PSZrmk + 3230638775U, // VCVTPH2PSZrmkz + 551838391U, // VCVTPH2PSZrr + 551843737U, // VCVTPH2PSZrrb + 3230709657U, // VCVTPH2PSZrrbk + 3229677465U, // VCVTPH2PSZrrbkz + 3230704311U, // VCVTPH2PSZrrk + 3229672119U, // VCVTPH2PSZrrkz + 552182455U, // VCVTPH2PSrm + 551838391U, // VCVTPH2PSrr + 1350194U, // VCVTPS2DQYrm + 551836210U, // VCVTPS2DQYrr + 662066U, // VCVTPS2DQZ128rm + 629791282U, // VCVTPS2DQZ128rmb + 630397490U, // VCVTPS2DQZ128rmbk + 629316146U, // VCVTPS2DQZ128rmbkz + 3230603826U, // VCVTPS2DQZ128rmk + 3229751858U, // VCVTPS2DQZ128rmkz + 551836210U, // VCVTPS2DQZ128rr + 3230702130U, // VCVTPS2DQZ128rrk + 3229669938U, // VCVTPS2DQZ128rrkz + 1350194U, // VCVTPS2DQZ256rm + 631888434U, // VCVTPS2DQZ256rmb + 632494642U, // VCVTPS2DQZ256rmbk + 631413298U, // VCVTPS2DQZ256rmbkz + 3230734898U, // VCVTPS2DQZ256rmk + 3230636594U, // VCVTPS2DQZ256rmkz + 551836210U, // VCVTPS2DQZ256rr + 3230702130U, // VCVTPS2DQZ256rrk + 3229669938U, // VCVTPS2DQZ256rrkz + 1514034U, // VCVTPS2DQZrm + 633985586U, // VCVTPS2DQZrmb + 634591794U, // VCVTPS2DQZrmbk + 633510450U, // VCVTPS2DQZrmbkz + 3230784050U, // VCVTPS2DQZrmk + 3230751282U, // VCVTPS2DQZrmkz + 551836210U, // VCVTPS2DQZrr + 1497650U, // VCVTPS2DQZrrb + 3230833202U, // VCVTPS2DQZrrbk + 3230800434U, // VCVTPS2DQZrrbkz + 3230702130U, // VCVTPS2DQZrrk + 3229669938U, // VCVTPS2DQZrrkz + 662066U, // VCVTPS2DQrm + 551836210U, // VCVTPS2DQrr + 657930U, // VCVTPS2PDYrm + 551832074U, // VCVTPS2PDYrr + 552176138U, // VCVTPS2PDZ128rm + 627689994U, // VCVTPS2PDZ128rmb + 628296202U, // VCVTPS2PDZ128rmbk + 627214858U, // VCVTPS2PDZ128rmbkz + 552602122U, // VCVTPS2PDZ128rmk + 551701002U, // VCVTPS2PDZ128rmkz + 551832074U, // VCVTPS2PDZ128rr + 3230697994U, // VCVTPS2PDZ128rrk + 3229665802U, // VCVTPS2PDZ128rrkz + 657930U, // VCVTPS2PDZ256rm + 629787146U, // VCVTPS2PDZ256rmb + 630393354U, // VCVTPS2PDZ256rmbk + 629312010U, // VCVTPS2PDZ256rmbkz + 3230599690U, // VCVTPS2PDZ256rmk + 3229747722U, // VCVTPS2PDZ256rmkz + 551832074U, // VCVTPS2PDZ256rr + 3230697994U, // VCVTPS2PDZ256rrk + 3229665802U, // VCVTPS2PDZ256rrkz + 1346058U, // VCVTPS2PDZrm + 631884298U, // VCVTPS2PDZrmb + 632490506U, // VCVTPS2PDZrmbk + 631409162U, // VCVTPS2PDZrmbkz + 3230730762U, // VCVTPS2PDZrmk + 3230632458U, // VCVTPS2PDZrmkz + 551832074U, // VCVTPS2PDZrr + 551843266U, // VCVTPS2PDZrrb + 3230709186U, // VCVTPS2PDZrrbk + 3229676994U, // VCVTPS2PDZrrbkz + 3230697994U, // VCVTPS2PDZrrk + 3229665802U, // VCVTPS2PDZrrkz + 552176138U, // VCVTPS2PDrm + 551832074U, // VCVTPS2PDrr + 1126470238U, // VCVTPS2PHYmr + 283431518U, // VCVTPS2PHYrr + 1394905694U, // VCVTPS2PHZ128mr + 1495650910U, // VCVTPS2PHZ128mrk + 283431518U, // VCVTPS2PHZ128rr + 1357582942U, // VCVTPS2PHZ128rrk + 1088819806U, // VCVTPS2PHZ128rrkz + 1126470238U, // VCVTPS2PHZ256mr + 1227215454U, // VCVTPS2PHZ256mrk + 283431518U, // VCVTPS2PHZ256rr + 1357582942U, // VCVTPS2PHZ256rrk + 1088819806U, // VCVTPS2PHZ256rrkz + 1663341150U, // VCVTPS2PHZmr + 1764086366U, // VCVTPS2PHZmrk + 283431518U, // VCVTPS2PHZrr + 407163486U, // VCVTPS2PHZrrb + 1481314910U, // VCVTPS2PHZrrbk + 1212551774U, // VCVTPS2PHZrrbkz + 1357582942U, // VCVTPS2PHZrrk + 1088819806U, // VCVTPS2PHZrrkz + 1394905694U, // VCVTPS2PHmr + 283431518U, // VCVTPS2PHrr + 552181208U, // VCVTPS2QQZ128rm + 627695064U, // VCVTPS2QQZ128rmb + 628301272U, // VCVTPS2QQZ128rmbk + 627219928U, // VCVTPS2QQZ128rmbkz + 552607192U, // VCVTPS2QQZ128rmk + 551706072U, // VCVTPS2QQZ128rmkz + 551837144U, // VCVTPS2QQZ128rr + 3230703064U, // VCVTPS2QQZ128rrk + 3229670872U, // VCVTPS2QQZ128rrkz + 663000U, // VCVTPS2QQZ256rm + 629792216U, // VCVTPS2QQZ256rmb + 630398424U, // VCVTPS2QQZ256rmbk + 629317080U, // VCVTPS2QQZ256rmbkz + 3230604760U, // VCVTPS2QQZ256rmk + 3229752792U, // VCVTPS2QQZ256rmkz + 551837144U, // VCVTPS2QQZ256rr + 3230703064U, // VCVTPS2QQZ256rrk + 3229670872U, // VCVTPS2QQZ256rrkz + 1351128U, // VCVTPS2QQZrm + 631889368U, // VCVTPS2QQZrmb + 632495576U, // VCVTPS2QQZrmbk + 631414232U, // VCVTPS2QQZrmbkz + 3230735832U, // VCVTPS2QQZrmk + 3230637528U, // VCVTPS2QQZrmkz + 551837144U, // VCVTPS2QQZrr + 1498584U, // VCVTPS2QQZrrb + 3230834136U, // VCVTPS2QQZrrbk + 3230801368U, // VCVTPS2QQZrrbkz + 3230703064U, // VCVTPS2QQZrrk + 3229670872U, // VCVTPS2QQZrrkz + 662400U, // VCVTPS2UDQZ128rm + 629791616U, // VCVTPS2UDQZ128rmb + 630397824U, // VCVTPS2UDQZ128rmbk + 629316480U, // VCVTPS2UDQZ128rmbkz + 3230604160U, // VCVTPS2UDQZ128rmk + 3229752192U, // VCVTPS2UDQZ128rmkz + 551836544U, // VCVTPS2UDQZ128rr + 3230702464U, // VCVTPS2UDQZ128rrk + 3229670272U, // VCVTPS2UDQZ128rrkz + 1350528U, // VCVTPS2UDQZ256rm + 631888768U, // VCVTPS2UDQZ256rmb + 632494976U, // VCVTPS2UDQZ256rmbk + 631413632U, // VCVTPS2UDQZ256rmbkz + 3230735232U, // VCVTPS2UDQZ256rmk + 3230636928U, // VCVTPS2UDQZ256rmkz + 551836544U, // VCVTPS2UDQZ256rr + 3230702464U, // VCVTPS2UDQZ256rrk + 3229670272U, // VCVTPS2UDQZ256rrkz + 1514368U, // VCVTPS2UDQZrm + 633985920U, // VCVTPS2UDQZrmb + 634592128U, // VCVTPS2UDQZrmbk + 633510784U, // VCVTPS2UDQZrmbkz + 3230784384U, // VCVTPS2UDQZrmk + 3230751616U, // VCVTPS2UDQZrmkz + 551836544U, // VCVTPS2UDQZrr + 1497984U, // VCVTPS2UDQZrrb + 3230833536U, // VCVTPS2UDQZrrbk + 3230800768U, // VCVTPS2UDQZrrbkz + 3230702464U, // VCVTPS2UDQZrrk + 3229670272U, // VCVTPS2UDQZrrkz + 552181292U, // VCVTPS2UQQZ128rm + 627695148U, // VCVTPS2UQQZ128rmb + 628301356U, // VCVTPS2UQQZ128rmbk + 627220012U, // VCVTPS2UQQZ128rmbkz + 552607276U, // VCVTPS2UQQZ128rmk + 551706156U, // VCVTPS2UQQZ128rmkz + 551837228U, // VCVTPS2UQQZ128rr + 3230703148U, // VCVTPS2UQQZ128rrk + 3229670956U, // VCVTPS2UQQZ128rrkz + 663084U, // VCVTPS2UQQZ256rm + 629792300U, // VCVTPS2UQQZ256rmb + 630398508U, // VCVTPS2UQQZ256rmbk + 629317164U, // VCVTPS2UQQZ256rmbkz + 3230604844U, // VCVTPS2UQQZ256rmk + 3229752876U, // VCVTPS2UQQZ256rmkz + 551837228U, // VCVTPS2UQQZ256rr + 3230703148U, // VCVTPS2UQQZ256rrk + 3229670956U, // VCVTPS2UQQZ256rrkz + 1351212U, // VCVTPS2UQQZrm + 631889452U, // VCVTPS2UQQZrmb + 632495660U, // VCVTPS2UQQZrmbk + 631414316U, // VCVTPS2UQQZrmbkz + 3230735916U, // VCVTPS2UQQZrmk + 3230637612U, // VCVTPS2UQQZrmkz + 551837228U, // VCVTPS2UQQZrr + 1498668U, // VCVTPS2UQQZrrb + 3230834220U, // VCVTPS2UQQZrrbk + 3230801452U, // VCVTPS2UQQZrrbkz + 3230703148U, // VCVTPS2UQQZrrk + 3229670956U, // VCVTPS2UQQZrrkz + 264691U, // VCVTQQ2PDZ128rm + 627411443U, // VCVTQQ2PDZ128rmb + 628410867U, // VCVTQQ2PDZ128rmbk + 627149299U, // VCVTQQ2PDZ128rmbkz + 3230992883U, // VCVTQQ2PDZ128rmk + 3229862387U, // VCVTQQ2PDZ128rmkz + 551832051U, // VCVTQQ2PDZ128rr + 3230697971U, // VCVTQQ2PDZ128rrk + 3229665779U, // VCVTQQ2PDZ128rrkz + 552946163U, // VCVTQQ2PDZ256rm + 629508595U, // VCVTQQ2PDZ256rmb + 630508019U, // VCVTQQ2PDZ256rmbk + 629246451U, // VCVTQQ2PDZ256rmbkz + 3231025651U, // VCVTQQ2PDZ256rmk + 3230878195U, // VCVTQQ2PDZ256rmkz + 551832051U, // VCVTQQ2PDZ256rr + 3230697971U, // VCVTQQ2PDZ256rrk + 3229665779U, // VCVTQQ2PDZ256rrkz + 552438259U, // VCVTQQ2PDZrm + 631605747U, // VCVTQQ2PDZrmb + 632605171U, // VCVTQQ2PDZrmbk + 631343603U, // VCVTQQ2PDZrmbkz + 3231091187U, // VCVTQQ2PDZrmk + 3230894579U, // VCVTQQ2PDZrmkz + 551832051U, // VCVTQQ2PDZrr + 1493491U, // VCVTQQ2PDZrrb + 3230829043U, // VCVTQQ2PDZrrbk + 3230796275U, // VCVTQQ2PDZrrbkz + 3230697971U, // VCVTQQ2PDZrrk + 3229665779U, // VCVTQQ2PDZrrkz + 274496U, // VCVTQQ2PSZ128rm + 627417859U, // VCVTQQ2PSZ128rmb + 628417283U, // VCVTQQ2PSZ128rmbk + 627155715U, // VCVTQQ2PSZ128rmbkz + 3231002688U, // VCVTQQ2PSZ128rmk + 3229872192U, // VCVTQQ2PSZ128rmkz + 551838467U, // VCVTQQ2PSZ128rr + 3230704387U, // VCVTQQ2PSZ128rrk + 3229672195U, // VCVTQQ2PSZ128rrkz + 552956101U, // VCVTQQ2PSZ256rm + 629515011U, // VCVTQQ2PSZ256rmb + 630514435U, // VCVTQQ2PSZ256rmbk + 629252867U, // VCVTQQ2PSZ256rmbkz + 3231035589U, // VCVTQQ2PSZ256rmk + 3230888133U, // VCVTQQ2PSZ256rmkz + 551838467U, // VCVTQQ2PSZ256rr + 3230704387U, // VCVTQQ2PSZ256rrk + 3229672195U, // VCVTQQ2PSZ256rrkz + 552444675U, // VCVTQQ2PSZrm + 631612163U, // VCVTQQ2PSZrmb + 632611587U, // VCVTQQ2PSZrmbk + 631350019U, // VCVTQQ2PSZrmbkz + 3231097603U, // VCVTQQ2PSZrmk + 3230900995U, // VCVTQQ2PSZrmkz + 551838467U, // VCVTQQ2PSZrr + 1499907U, // VCVTQQ2PSZrrb + 3230835459U, // VCVTQQ2PSZrrbk + 3230802691U, // VCVTQQ2PSZrrbkz + 3230704387U, // VCVTQQ2PSZrrk + 3229672195U, // VCVTQQ2PSZrrkz + 552178432U, // VCVTSD2SI64Zrm_Int + 551834368U, // VCVTSD2SI64Zrr_Int + 1495808U, // VCVTSD2SI64Zrrb_Int + 552178432U, // VCVTSD2SI64rm_Int + 551834368U, // VCVTSD2SI64rr_Int + 552178432U, // VCVTSD2SIZrm_Int + 551834368U, // VCVTSD2SIZrr_Int + 1495808U, // VCVTSD2SIZrrb_Int + 552178432U, // VCVTSD2SIrm_Int + 551834368U, // VCVTSD2SIrr_Int + 283273051U, // VCVTSD2SSZrm + 283273051U, // VCVTSD2SSZrm_Int + 1357899611U, // VCVTSD2SSZrm_Intk + 1089480539U, // VCVTSD2SSZrm_Intkz + 811657051U, // VCVTSD2SSZrr + 811657051U, // VCVTSD2SSZrr_Int + 87058267U, // VCVTSD2SSZrr_Intk + 890283867U, // VCVTSD2SSZrr_Intkz + 812787547U, // VCVTSD2SSZrrb_Int + 87189339U, // VCVTSD2SSZrrb_Intk + 890414939U, // VCVTSD2SSZrrb_Intkz + 283273051U, // VCVTSD2SSrm + 283273051U, // VCVTSD2SSrm_Int + 811657051U, // VCVTSD2SSrr + 811657051U, // VCVTSD2SSrr_Int + 552178479U, // VCVTSD2USI64Zrm_Int + 551834415U, // VCVTSD2USI64Zrr_Int + 1495855U, // VCVTSD2USI64Zrrb_Int + 552178479U, // VCVTSD2USIZrm_Int + 551834415U, // VCVTSD2USIZrr_Int + 1495855U, // VCVTSD2USIZrrb_Int + 283202602U, // VCVTSI2SDZrm + 283202602U, // VCVTSI2SDZrm_Int + 811652138U, // VCVTSI2SDZrr + 811652138U, // VCVTSI2SDZrr_Int + 155243562U, // VCVTSI2SDZrrb_Int + 283202602U, // VCVTSI2SDrm + 283202602U, // VCVTSI2SDrm_Int + 811652138U, // VCVTSI2SDrr + 811652138U, // VCVTSI2SDrr_Int + 283203306U, // VCVTSI2SSZrm + 283203306U, // VCVTSI2SSZrm_Int + 811652842U, // VCVTSI2SSZrr + 811652842U, // VCVTSI2SSZrr_Int + 155244266U, // VCVTSI2SSZrrb_Int + 283203306U, // VCVTSI2SSrm + 283203306U, // VCVTSI2SSrm_Int + 811652842U, // VCVTSI2SSrr + 811652842U, // VCVTSI2SSrr_Int + 283220791U, // VCVTSI642SDZrm + 283220791U, // VCVTSI642SDZrm_Int + 811653943U, // VCVTSI642SDZrr + 811653943U, // VCVTSI642SDZrr_Int + 155245367U, // VCVTSI642SDZrrb_Int + 283220791U, // VCVTSI642SDrm + 283220791U, // VCVTSI642SDrm_Int + 811653943U, // VCVTSI642SDrr + 811653943U, // VCVTSI642SDrr_Int + 283221758U, // VCVTSI642SSZrm + 283221758U, // VCVTSI642SSZrm_Int + 811654910U, // VCVTSI642SSZrr + 811654910U, // VCVTSI642SSZrr_Int + 155246334U, // VCVTSI642SSZrrb_Int + 283221758U, // VCVTSI642SSrm + 283221758U, // VCVTSI642SSrm_Int + 811654910U, // VCVTSI642SSrr + 811654910U, // VCVTSI642SSrr_Int + 283283032U, // VCVTSS2SDZrm + 283283032U, // VCVTSS2SDZrm_Int + 1358089816U, // VCVTSS2SDZrm_Intk + 1089670744U, // VCVTSS2SDZrm_Intkz + 811650648U, // VCVTSS2SDZrr + 811650648U, // VCVTSS2SDZrr_Int + 87051864U, // VCVTSS2SDZrr_Intk + 890277464U, // VCVTSS2SDZrr_Intkz + 811660840U, // VCVTSS2SDZrrb_Int + 87062056U, // VCVTSS2SDZrrb_Intk + 890287656U, // VCVTSS2SDZrrb_Intkz + 283283032U, // VCVTSS2SDrm + 283283032U, // VCVTSS2SDrm_Int + 811650648U, // VCVTSS2SDrr + 811650648U, // VCVTSS2SDrr_Int + 552194839U, // VCVTSS2SI64Zrm_Int + 551834391U, // VCVTSS2SI64Zrr_Int + 1495831U, // VCVTSS2SI64Zrrb_Int + 552194839U, // VCVTSS2SI64rm_Int + 551834391U, // VCVTSS2SI64rr_Int + 552194839U, // VCVTSS2SIZrm_Int + 551834391U, // VCVTSS2SIZrr_Int + 1495831U, // VCVTSS2SIZrrb_Int + 552194839U, // VCVTSS2SIrm_Int + 551834391U, // VCVTSS2SIrr_Int + 552194888U, // VCVTSS2USI64Zrm_Int + 551834440U, // VCVTSS2USI64Zrr_Int + 1495880U, // VCVTSS2USI64Zrrb_Int + 552194888U, // VCVTSS2USIZrm_Int + 551834440U, // VCVTSS2USIZrr_Int + 1495880U, // VCVTSS2USIZrrb_Int + 1355899U, // VCVTTPD2DQYrm + 551836166U, // VCVTTPD2DQYrr + 667648U, // VCVTTPD2DQZ128rm + 627677702U, // VCVTTPD2DQZ128rmb + 628103686U, // VCVTTPD2DQZ128rmbk + 627202566U, // VCVTTPD2DQZ128rmbkz + 3230609408U, // VCVTTPD2DQZ128rmk + 3229757440U, // VCVTTPD2DQZ128rmkz + 551836166U, // VCVTTPD2DQZ128rr + 3230702086U, // VCVTTPD2DQZ128rrk + 3229669894U, // VCVTTPD2DQZ128rrkz + 1355899U, // VCVTTPD2DQZ256rm + 629774854U, // VCVTTPD2DQZ256rmb + 630200838U, // VCVTTPD2DQZ256rmbk + 629299718U, // VCVTTPD2DQZ256rmbkz + 3230740603U, // VCVTTPD2DQZ256rmk + 3230642299U, // VCVTTPD2DQZ256rmkz + 551836166U, // VCVTTPD2DQZ256rr + 3230702086U, // VCVTTPD2DQZ256rrk + 3229669894U, // VCVTTPD2DQZ256rrkz + 1513990U, // VCVTTPD2DQZrm + 631872006U, // VCVTTPD2DQZrmb + 632297990U, // VCVTTPD2DQZrmbk + 631396870U, // VCVTTPD2DQZrmbkz + 3230784006U, // VCVTTPD2DQZrmk + 3230751238U, // VCVTTPD2DQZrmkz + 551836166U, // VCVTTPD2DQZrr + 551843581U, // VCVTTPD2DQZrrb + 3230709501U, // VCVTTPD2DQZrrbk + 3229677309U, // VCVTTPD2DQZrrbkz + 3230702086U, // VCVTTPD2DQZrrk + 3229669894U, // VCVTTPD2DQZrrkz + 667648U, // VCVTTPD2DQrm + 551836166U, // VCVTTPD2DQrr + 662965U, // VCVTTPD2QQZ128rm + 627678645U, // VCVTTPD2QQZ128rmb + 628104629U, // VCVTTPD2QQZ128rmbk + 627203509U, // VCVTTPD2QQZ128rmbkz + 3230604725U, // VCVTTPD2QQZ128rmk + 3229752757U, // VCVTTPD2QQZ128rmkz + 551837109U, // VCVTTPD2QQZ128rr + 3230703029U, // VCVTTPD2QQZ128rrk + 3229670837U, // VCVTTPD2QQZ128rrkz + 1351093U, // VCVTTPD2QQZ256rm + 629775797U, // VCVTTPD2QQZ256rmb + 630201781U, // VCVTTPD2QQZ256rmbk + 629300661U, // VCVTTPD2QQZ256rmbkz + 3230735797U, // VCVTTPD2QQZ256rmk + 3230637493U, // VCVTTPD2QQZ256rmkz + 551837109U, // VCVTTPD2QQZ256rr + 3230703029U, // VCVTTPD2QQZ256rrk + 3229670837U, // VCVTTPD2QQZ256rrkz + 1514933U, // VCVTTPD2QQZrm + 631872949U, // VCVTTPD2QQZrmb + 632298933U, // VCVTTPD2QQZrmbk + 631397813U, // VCVTTPD2QQZrmbkz + 3230784949U, // VCVTTPD2QQZrmk + 3230752181U, // VCVTTPD2QQZrmkz + 551837109U, // VCVTTPD2QQZrr + 551843659U, // VCVTTPD2QQZrrb + 3230709579U, // VCVTTPD2QQZrrbk + 3229677387U, // VCVTTPD2QQZrrbkz + 3230703029U, // VCVTTPD2QQZrrk + 3229670837U, // VCVTTPD2QQZrrkz + 667673U, // VCVTTPD2UDQZ128rm + 627678042U, // VCVTTPD2UDQZ128rmb + 628104026U, // VCVTTPD2UDQZ128rmbk + 627202906U, // VCVTTPD2UDQZ128rmbkz + 3230609433U, // VCVTTPD2UDQZ128rmk + 3229757465U, // VCVTTPD2UDQZ128rmkz + 551836506U, // VCVTTPD2UDQZ128rr + 3230702426U, // VCVTTPD2UDQZ128rrk + 3229670234U, // VCVTTPD2UDQZ128rrkz + 1355924U, // VCVTTPD2UDQZ256rm + 629775194U, // VCVTTPD2UDQZ256rmb + 630201178U, // VCVTTPD2UDQZ256rmbk + 629300058U, // VCVTTPD2UDQZ256rmbkz + 3230740628U, // VCVTTPD2UDQZ256rmk + 3230642324U, // VCVTTPD2UDQZ256rmkz + 551836506U, // VCVTTPD2UDQZ256rr + 3230702426U, // VCVTTPD2UDQZ256rrk + 3229670234U, // VCVTTPD2UDQZ256rrkz + 1514330U, // VCVTTPD2UDQZrm + 631872346U, // VCVTTPD2UDQZrmb + 632298330U, // VCVTTPD2UDQZrmbk + 631397210U, // VCVTTPD2UDQZrmbkz + 3230784346U, // VCVTTPD2UDQZrmk + 3230751578U, // VCVTTPD2UDQZrmkz + 551836506U, // VCVTTPD2UDQZrr + 551843619U, // VCVTTPD2UDQZrrb + 3230709539U, // VCVTTPD2UDQZrrbk + 3229677347U, // VCVTTPD2UDQZrrbkz + 3230702426U, // VCVTTPD2UDQZrrk + 3229670234U, // VCVTTPD2UDQZrrkz + 663046U, // VCVTTPD2UQQZ128rm + 627678726U, // VCVTTPD2UQQZ128rmb + 628104710U, // VCVTTPD2UQQZ128rmbk + 627203590U, // VCVTTPD2UQQZ128rmbkz + 3230604806U, // VCVTTPD2UQQZ128rmk + 3229752838U, // VCVTTPD2UQQZ128rmkz + 551837190U, // VCVTTPD2UQQZ128rr + 3230703110U, // VCVTTPD2UQQZ128rrk + 3229670918U, // VCVTTPD2UQQZ128rrkz + 1351174U, // VCVTTPD2UQQZ256rm + 629775878U, // VCVTTPD2UQQZ256rmb + 630201862U, // VCVTTPD2UQQZ256rmbk + 629300742U, // VCVTTPD2UQQZ256rmbkz + 3230735878U, // VCVTTPD2UQQZ256rmk + 3230637574U, // VCVTTPD2UQQZ256rmkz + 551837190U, // VCVTTPD2UQQZ256rr + 3230703110U, // VCVTTPD2UQQZ256rrk + 3229670918U, // VCVTTPD2UQQZ256rrkz + 1515014U, // VCVTTPD2UQQZrm + 631873030U, // VCVTTPD2UQQZrmb + 632299014U, // VCVTTPD2UQQZrmbk + 631397894U, // VCVTTPD2UQQZrmbkz + 3230785030U, // VCVTTPD2UQQZrmk + 3230752262U, // VCVTTPD2UQQZrmkz + 551837190U, // VCVTTPD2UQQZrr + 551843697U, // VCVTTPD2UQQZrrb + 3230709617U, // VCVTTPD2UQQZrrbk + 3229677425U, // VCVTTPD2UQQZrrbkz + 3230703110U, // VCVTTPD2UQQZrrk + 3229670918U, // VCVTTPD2UQQZrrkz + 1350182U, // VCVTTPS2DQYrm + 551836198U, // VCVTTPS2DQYrr + 662054U, // VCVTTPS2DQZ128rm + 629791270U, // VCVTTPS2DQZ128rmb + 630397478U, // VCVTTPS2DQZ128rmbk + 629316134U, // VCVTTPS2DQZ128rmbkz + 3230603814U, // VCVTTPS2DQZ128rmk + 3229751846U, // VCVTTPS2DQZ128rmkz + 551836198U, // VCVTTPS2DQZ128rr + 3230702118U, // VCVTTPS2DQZ128rrk + 3229669926U, // VCVTTPS2DQZ128rrkz + 1350182U, // VCVTTPS2DQZ256rm + 631888422U, // VCVTTPS2DQZ256rmb + 632494630U, // VCVTTPS2DQZ256rmbk + 631413286U, // VCVTTPS2DQZ256rmbkz + 3230734886U, // VCVTTPS2DQZ256rmk + 3230636582U, // VCVTTPS2DQZ256rmkz + 551836198U, // VCVTTPS2DQZ256rr + 3230702118U, // VCVTTPS2DQZ256rrk + 3229669926U, // VCVTTPS2DQZ256rrkz + 1514022U, // VCVTTPS2DQZrm + 633985574U, // VCVTTPS2DQZrmb + 634591782U, // VCVTTPS2DQZrmbk + 633510438U, // VCVTTPS2DQZrmbkz + 3230784038U, // VCVTTPS2DQZrmk + 3230751270U, // VCVTTPS2DQZrmkz + 551836198U, // VCVTTPS2DQZrr + 551843600U, // VCVTTPS2DQZrrb + 3230709520U, // VCVTTPS2DQZrrbk + 3229677328U, // VCVTTPS2DQZrrbkz + 3230702118U, // VCVTTPS2DQZrrk + 3229669926U, // VCVTTPS2DQZrrkz + 662054U, // VCVTTPS2DQrm + 551836198U, // VCVTTPS2DQrr + 552181196U, // VCVTTPS2QQZ128rm + 627695052U, // VCVTTPS2QQZ128rmb + 628301260U, // VCVTTPS2QQZ128rmbk + 627219916U, // VCVTTPS2QQZ128rmbkz + 552607180U, // VCVTTPS2QQZ128rmk + 551706060U, // VCVTTPS2QQZ128rmkz + 551837132U, // VCVTTPS2QQZ128rr + 3230703052U, // VCVTTPS2QQZ128rrk + 3229670860U, // VCVTTPS2QQZ128rrkz + 662988U, // VCVTTPS2QQZ256rm + 629792204U, // VCVTTPS2QQZ256rmb + 630398412U, // VCVTTPS2QQZ256rmbk + 629317068U, // VCVTTPS2QQZ256rmbkz + 3230604748U, // VCVTTPS2QQZ256rmk + 3229752780U, // VCVTTPS2QQZ256rmkz + 551837132U, // VCVTTPS2QQZ256rr + 3230703052U, // VCVTTPS2QQZ256rrk + 3229670860U, // VCVTTPS2QQZ256rrkz + 1351116U, // VCVTTPS2QQZrm + 631889356U, // VCVTTPS2QQZrmb + 632495564U, // VCVTTPS2QQZrmbk + 631414220U, // VCVTTPS2QQZrmbkz + 3230735820U, // VCVTTPS2QQZrmk + 3230637516U, // VCVTTPS2QQZrmkz + 551837132U, // VCVTTPS2QQZrr + 551843678U, // VCVTTPS2QQZrrb + 3230709598U, // VCVTTPS2QQZrrbk + 3229677406U, // VCVTTPS2QQZrrbkz + 3230703052U, // VCVTTPS2QQZrrk + 3229670860U, // VCVTTPS2QQZrrkz + 662387U, // VCVTTPS2UDQZ128rm + 629791603U, // VCVTTPS2UDQZ128rmb + 630397811U, // VCVTTPS2UDQZ128rmbk + 629316467U, // VCVTTPS2UDQZ128rmbkz + 3230604147U, // VCVTTPS2UDQZ128rmk + 3229752179U, // VCVTTPS2UDQZ128rmkz + 551836531U, // VCVTTPS2UDQZ128rr + 3230702451U, // VCVTTPS2UDQZ128rrk + 3229670259U, // VCVTTPS2UDQZ128rrkz + 1350515U, // VCVTTPS2UDQZ256rm + 631888755U, // VCVTTPS2UDQZ256rmb + 632494963U, // VCVTTPS2UDQZ256rmbk + 631413619U, // VCVTTPS2UDQZ256rmbkz + 3230735219U, // VCVTTPS2UDQZ256rmk + 3230636915U, // VCVTTPS2UDQZ256rmkz + 551836531U, // VCVTTPS2UDQZ256rr + 3230702451U, // VCVTTPS2UDQZ256rrk + 3229670259U, // VCVTTPS2UDQZ256rrkz + 1514355U, // VCVTTPS2UDQZrm + 633985907U, // VCVTTPS2UDQZrmb + 634592115U, // VCVTTPS2UDQZrmbk + 633510771U, // VCVTTPS2UDQZrmbkz + 3230784371U, // VCVTTPS2UDQZrmk + 3230751603U, // VCVTTPS2UDQZrmkz + 551836531U, // VCVTTPS2UDQZrr + 551843639U, // VCVTTPS2UDQZrrb + 3230709559U, // VCVTTPS2UDQZrrbk + 3229677367U, // VCVTTPS2UDQZrrbkz + 3230702451U, // VCVTTPS2UDQZrrk + 3229670259U, // VCVTTPS2UDQZrrkz + 552181279U, // VCVTTPS2UQQZ128rm + 627695135U, // VCVTTPS2UQQZ128rmb + 628301343U, // VCVTTPS2UQQZ128rmbk + 627219999U, // VCVTTPS2UQQZ128rmbkz + 552607263U, // VCVTTPS2UQQZ128rmk + 551706143U, // VCVTTPS2UQQZ128rmkz + 551837215U, // VCVTTPS2UQQZ128rr + 3230703135U, // VCVTTPS2UQQZ128rrk + 3229670943U, // VCVTTPS2UQQZ128rrkz + 663071U, // VCVTTPS2UQQZ256rm + 629792287U, // VCVTTPS2UQQZ256rmb + 630398495U, // VCVTTPS2UQQZ256rmbk + 629317151U, // VCVTTPS2UQQZ256rmbkz + 3230604831U, // VCVTTPS2UQQZ256rmk + 3229752863U, // VCVTTPS2UQQZ256rmkz + 551837215U, // VCVTTPS2UQQZ256rr + 3230703135U, // VCVTTPS2UQQZ256rrk + 3229670943U, // VCVTTPS2UQQZ256rrkz + 1351199U, // VCVTTPS2UQQZrm + 631889439U, // VCVTTPS2UQQZrmb + 632495647U, // VCVTTPS2UQQZrmbk + 631414303U, // VCVTTPS2UQQZrmbkz + 3230735903U, // VCVTTPS2UQQZrmk + 3230637599U, // VCVTTPS2UQQZrmkz + 551837215U, // VCVTTPS2UQQZrr + 551843717U, // VCVTTPS2UQQZrrb + 3230709637U, // VCVTTPS2UQQZrrbk + 3229677445U, // VCVTTPS2UQQZrrbkz + 3230703135U, // VCVTTPS2UQQZrrk + 3229670943U, // VCVTTPS2UQQZrrkz + 552178420U, // VCVTTSD2SI64Zrm + 552178420U, // VCVTTSD2SI64Zrm_Int + 551834356U, // VCVTTSD2SI64Zrr + 551834356U, // VCVTTSD2SI64Zrr_Int + 551843503U, // VCVTTSD2SI64Zrrb_Int + 552178420U, // VCVTTSD2SI64rm + 552178420U, // VCVTTSD2SI64rm_Int + 551834356U, // VCVTTSD2SI64rr + 551834356U, // VCVTTSD2SI64rr_Int + 552178420U, // VCVTTSD2SIZrm + 552178420U, // VCVTTSD2SIZrm_Int + 551834356U, // VCVTTSD2SIZrr + 551834356U, // VCVTTSD2SIZrr_Int + 551843503U, // VCVTTSD2SIZrrb_Int + 552178420U, // VCVTTSD2SIrm + 552178420U, // VCVTTSD2SIrm_Int + 551834356U, // VCVTTSD2SIrr + 551834356U, // VCVTTSD2SIrr_Int + 552178466U, // VCVTTSD2USI64Zrm + 552178466U, // VCVTTSD2USI64Zrm_Int + 551834402U, // VCVTTSD2USI64Zrr + 551834402U, // VCVTTSD2USI64Zrr_Int + 551843541U, // VCVTTSD2USI64Zrrb_Int + 552178466U, // VCVTTSD2USIZrm + 552178466U, // VCVTTSD2USIZrm_Int + 551834402U, // VCVTTSD2USIZrr + 551834402U, // VCVTTSD2USIZrr_Int + 551843541U, // VCVTTSD2USIZrrb_Int + 552194827U, // VCVTTSS2SI64Zrm + 552194827U, // VCVTTSS2SI64Zrm_Int + 551834379U, // VCVTTSS2SI64Zrr + 551834379U, // VCVTTSS2SI64Zrr_Int + 551843522U, // VCVTTSS2SI64Zrrb_Int + 552194827U, // VCVTTSS2SI64rm + 552194827U, // VCVTTSS2SI64rm_Int + 551834379U, // VCVTTSS2SI64rr + 551834379U, // VCVTTSS2SI64rr_Int + 552194827U, // VCVTTSS2SIZrm + 552194827U, // VCVTTSS2SIZrm_Int + 551834379U, // VCVTTSS2SIZrr + 551834379U, // VCVTTSS2SIZrr_Int + 551843522U, // VCVTTSS2SIZrrb_Int + 552194827U, // VCVTTSS2SIrm + 552194827U, // VCVTTSS2SIrm_Int + 551834379U, // VCVTTSS2SIrr + 551834379U, // VCVTTSS2SIrr_Int + 552194875U, // VCVTTSS2USI64Zrm + 552194875U, // VCVTTSS2USI64Zrm_Int + 551834427U, // VCVTTSS2USI64Zrr + 551834427U, // VCVTTSS2USI64Zrr_Int + 551843561U, // VCVTTSS2USI64Zrrb_Int + 552194875U, // VCVTTSS2USIZrm + 552194875U, // VCVTTSS2USIZrm_Int + 551834427U, // VCVTTSS2USIZrr + 551834427U, // VCVTTSS2USIZrr_Int + 551843561U, // VCVTTSS2USIZrrb_Int + 551913959U, // VCVTUDQ2PDZ128rm + 627395047U, // VCVTUDQ2PDZ128rmb + 628509159U, // VCVTUDQ2PDZ128rmbk + 627132903U, // VCVTUDQ2PDZ128rmbkz + 552913383U, // VCVTUDQ2PDZ128rmk + 551651815U, // VCVTUDQ2PDZ128rmkz + 551832039U, // VCVTUDQ2PDZ128rr + 3230697959U, // VCVTUDQ2PDZ128rrk + 3229665767U, // VCVTUDQ2PDZ128rrkz + 264679U, // VCVTUDQ2PDZ256rm + 629492199U, // VCVTUDQ2PDZ256rmb + 630606311U, // VCVTUDQ2PDZ256rmbk + 629230055U, // VCVTUDQ2PDZ256rmbkz + 3230992871U, // VCVTUDQ2PDZ256rmk + 3229862375U, // VCVTUDQ2PDZ256rmkz + 551832039U, // VCVTUDQ2PDZ256rr + 3230697959U, // VCVTUDQ2PDZ256rrk + 3229665767U, // VCVTUDQ2PDZ256rrkz + 552946151U, // VCVTUDQ2PDZrm + 631589351U, // VCVTUDQ2PDZrmb + 632703463U, // VCVTUDQ2PDZrmbk + 631327207U, // VCVTUDQ2PDZrmbkz + 3231025639U, // VCVTUDQ2PDZrmk + 3230878183U, // VCVTUDQ2PDZrmkz + 551832039U, // VCVTUDQ2PDZrr + 3230697959U, // VCVTUDQ2PDZrrk + 3229665767U, // VCVTUDQ2PDZrrkz + 271095U, // VCVTUDQ2PSZ128rm + 629498615U, // VCVTUDQ2PSZ128rmb + 630612727U, // VCVTUDQ2PSZ128rmbk + 629236471U, // VCVTUDQ2PSZ128rmbkz + 3230999287U, // VCVTUDQ2PSZ128rmk + 3229868791U, // VCVTUDQ2PSZ128rmkz + 551838455U, // VCVTUDQ2PSZ128rr + 3230704375U, // VCVTUDQ2PSZ128rrk + 3229672183U, // VCVTUDQ2PSZ128rrkz + 552952567U, // VCVTUDQ2PSZ256rm + 631595767U, // VCVTUDQ2PSZ256rmb + 632709879U, // VCVTUDQ2PSZ256rmbk + 631333623U, // VCVTUDQ2PSZ256rmbkz + 3231032055U, // VCVTUDQ2PSZ256rmk + 3230884599U, // VCVTUDQ2PSZ256rmkz + 551838455U, // VCVTUDQ2PSZ256rr + 3230704375U, // VCVTUDQ2PSZ256rrk + 3229672183U, // VCVTUDQ2PSZ256rrkz + 552444663U, // VCVTUDQ2PSZrm + 633692919U, // VCVTUDQ2PSZrmb + 634807031U, // VCVTUDQ2PSZrmbk + 633430775U, // VCVTUDQ2PSZrmbkz + 3231097591U, // VCVTUDQ2PSZrmk + 3230900983U, // VCVTUDQ2PSZrmkz + 551838455U, // VCVTUDQ2PSZrr + 1499895U, // VCVTUDQ2PSZrrb + 3230835447U, // VCVTUDQ2PSZrrbk + 3230802679U, // VCVTUDQ2PSZrrbkz + 3230704375U, // VCVTUDQ2PSZrrk + 3229672183U, // VCVTUDQ2PSZrrkz + 264702U, // VCVTUQQ2PDZ128rm + 627411454U, // VCVTUQQ2PDZ128rmb + 628410878U, // VCVTUQQ2PDZ128rmbk + 627149310U, // VCVTUQQ2PDZ128rmbkz + 3230992894U, // VCVTUQQ2PDZ128rmk + 3229862398U, // VCVTUQQ2PDZ128rmkz + 551832062U, // VCVTUQQ2PDZ128rr + 3230697982U, // VCVTUQQ2PDZ128rrk + 3229665790U, // VCVTUQQ2PDZ128rrkz + 552946174U, // VCVTUQQ2PDZ256rm + 629508606U, // VCVTUQQ2PDZ256rmb + 630508030U, // VCVTUQQ2PDZ256rmbk + 629246462U, // VCVTUQQ2PDZ256rmbkz + 3231025662U, // VCVTUQQ2PDZ256rmk + 3230878206U, // VCVTUQQ2PDZ256rmkz + 551832062U, // VCVTUQQ2PDZ256rr + 3230697982U, // VCVTUQQ2PDZ256rrk + 3229665790U, // VCVTUQQ2PDZ256rrkz + 552438270U, // VCVTUQQ2PDZrm + 631605758U, // VCVTUQQ2PDZrmb + 632605182U, // VCVTUQQ2PDZrmbk + 631343614U, // VCVTUQQ2PDZrmbkz + 3231091198U, // VCVTUQQ2PDZrmk + 3230894590U, // VCVTUQQ2PDZrmkz + 551832062U, // VCVTUQQ2PDZrr + 1493502U, // VCVTUQQ2PDZrrb + 3230829054U, // VCVTUQQ2PDZrrbk + 3230796286U, // VCVTUQQ2PDZrrbkz + 3230697982U, // VCVTUQQ2PDZrrk + 3229665790U, // VCVTUQQ2PDZrrkz + 274508U, // VCVTUQQ2PSZ128rm + 627417870U, // VCVTUQQ2PSZ128rmb + 628417294U, // VCVTUQQ2PSZ128rmbk + 627155726U, // VCVTUQQ2PSZ128rmbkz + 3231002700U, // VCVTUQQ2PSZ128rmk + 3229872204U, // VCVTUQQ2PSZ128rmkz + 551838478U, // VCVTUQQ2PSZ128rr + 3230704398U, // VCVTUQQ2PSZ128rrk + 3229672206U, // VCVTUQQ2PSZ128rrkz + 552956113U, // VCVTUQQ2PSZ256rm + 629515022U, // VCVTUQQ2PSZ256rmb + 630514446U, // VCVTUQQ2PSZ256rmbk + 629252878U, // VCVTUQQ2PSZ256rmbkz + 3231035601U, // VCVTUQQ2PSZ256rmk + 3230888145U, // VCVTUQQ2PSZ256rmkz + 551838478U, // VCVTUQQ2PSZ256rr + 3230704398U, // VCVTUQQ2PSZ256rrk + 3229672206U, // VCVTUQQ2PSZ256rrkz + 552444686U, // VCVTUQQ2PSZrm + 631612174U, // VCVTUQQ2PSZrmb + 632611598U, // VCVTUQQ2PSZrmbk + 631350030U, // VCVTUQQ2PSZrmbkz + 3231097614U, // VCVTUQQ2PSZrmk + 3230901006U, // VCVTUQQ2PSZrmkz + 551838478U, // VCVTUQQ2PSZrr + 1499918U, // VCVTUQQ2PSZrrb + 3230835470U, // VCVTUQQ2PSZrrbk + 3230802702U, // VCVTUQQ2PSZrrbkz + 3230704398U, // VCVTUQQ2PSZrrk + 3229672206U, // VCVTUQQ2PSZrrkz + 283202614U, // VCVTUSI2SDZrm + 283202614U, // VCVTUSI2SDZrm_Int + 811652150U, // VCVTUSI2SDZrr + 811652150U, // VCVTUSI2SDZrr_Int + 283203318U, // VCVTUSI2SSZrm + 283203318U, // VCVTUSI2SSZrm_Int + 811652854U, // VCVTUSI2SSZrr + 811652854U, // VCVTUSI2SSZrr_Int + 155244278U, // VCVTUSI2SSZrrb_Int + 283220803U, // VCVTUSI642SDZrm + 283220803U, // VCVTUSI642SDZrm_Int + 811653955U, // VCVTUSI642SDZrr + 811653955U, // VCVTUSI642SDZrr_Int + 155245379U, // VCVTUSI642SDZrrb_Int + 283221770U, // VCVTUSI642SSZrm + 283221770U, // VCVTUSI642SSZrm_Int + 811654922U, // VCVTUSI642SSZrr + 811654922U, // VCVTUSI642SSZrr_Int + 155246346U, // VCVTUSI642SSZrrb_Int + 325446245U, // VDBPSADBWZ128rmi + 1983113829U, // VDBPSADBWZ128rmik + 1179920997U, // VDBPSADBWZ128rmikz + 1088825957U, // VDBPSADBWZ128rri + 2163141221U, // VDBPSADBWZ128rrik + 1357589093U, // VDBPSADBWZ128rrikz + 375777893U, // VDBPSADBWZ256rmi + 1989405285U, // VDBPSADBWZ256rmik + 1186212453U, // VDBPSADBWZ256rmikz + 1088825957U, // VDBPSADBWZ256rri + 2163141221U, // VDBPSADBWZ256rrik + 1357589093U, // VDBPSADBWZ256rrikz + 382069349U, // VDBPSADBWZrmi + 1995696741U, // VDBPSADBWZrmik + 1192503909U, // VDBPSADBWZrmikz + 1088825957U, // VDBPSADBWZrri + 2163141221U, // VDBPSADBWZrrik + 1357589093U, // VDBPSADBWZrrikz + 812617022U, // VDIVPDYrm + 811650366U, // VDIVPDYrr + 811732286U, // VDIVPDZ128rm + 358763838U, // VDIVPDZ128rmb + 1433390398U, // VDIVPDZ128rmbk + 1164971326U, // VDIVPDZ128rmbkz + 86986046U, // VDIVPDZ128rmk + 890178878U, // VDIVPDZ128rmkz + 811650366U, // VDIVPDZ128rr + 87051582U, // VDIVPDZ128rrk + 890277182U, // VDIVPDZ128rrkz + 812617022U, // VDIVPDZ256rm + 360860990U, // VDIVPDZ256rmb + 1435487550U, // VDIVPDZ256rmbk + 1167068478U, // VDIVPDZ256rmbkz + 87084350U, // VDIVPDZ256rmk + 890309950U, // VDIVPDZ256rmkz + 811650366U, // VDIVPDZ256rr + 87051582U, // VDIVPDZ256rrk + 890277182U, // VDIVPDZ256rrkz + 812731710U, // VDIVPDZrm + 362958142U, // VDIVPDZrmb + 1437584702U, // VDIVPDZrmbk + 1169165630U, // VDIVPDZrmbkz + 87133502U, // VDIVPDZrmk + 890359102U, // VDIVPDZrmkz + 811650366U, // VDIVPDZrr + 812780862U, // VDIVPDZrrb + 87182654U, // VDIVPDZrrbk + 890408254U, // VDIVPDZrrbkz + 87051582U, // VDIVPDZrrk + 890277182U, // VDIVPDZrrkz + 811732286U, // VDIVPDrm + 811650366U, // VDIVPDrr + 812623519U, // VDIVPSYrm + 811656863U, // VDIVPSYrr + 811738783U, // VDIVPSZ128rm + 360883871U, // VDIVPSZ128rmb + 1435690655U, // VDIVPSZ128rmbk + 1167271583U, // VDIVPSZ128rmbkz + 86992543U, // VDIVPSZ128rmk + 890185375U, // VDIVPSZ128rmkz + 811656863U, // VDIVPSZ128rr + 87058079U, // VDIVPSZ128rrk + 890283679U, // VDIVPSZ128rrkz + 812623519U, // VDIVPSZ256rm + 362981023U, // VDIVPSZ256rmb + 1437787807U, // VDIVPSZ256rmbk + 1169368735U, // VDIVPSZ256rmbkz + 87090847U, // VDIVPSZ256rmk + 890316447U, // VDIVPSZ256rmkz + 811656863U, // VDIVPSZ256rr + 87058079U, // VDIVPSZ256rrk + 890283679U, // VDIVPSZ256rrkz + 812738207U, // VDIVPSZrm + 365078175U, // VDIVPSZrmb + 1439884959U, // VDIVPSZrmbk + 1171465887U, // VDIVPSZrmbkz + 87139999U, // VDIVPSZrmk + 890365599U, // VDIVPSZrmkz + 811656863U, // VDIVPSZrr + 812787359U, // VDIVPSZrrb + 87189151U, // VDIVPSZrrbk + 890414751U, // VDIVPSZrrbkz + 87058079U, // VDIVPSZrrk + 890283679U, // VDIVPSZrrkz + 811738783U, // VDIVPSrm + 811656863U, // VDIVPSrr + 283267069U, // VDIVSDZrm + 283267069U, // VDIVSDZrm_Int + 1357893629U, // VDIVSDZrm_Intk + 1089474557U, // VDIVSDZrm_Intkz + 811651069U, // VDIVSDZrr + 811651069U, // VDIVSDZrr_Int + 87052285U, // VDIVSDZrr_Intk + 890277885U, // VDIVSDZrr_Intkz + 812781565U, // VDIVSDZrrb_Int + 87183357U, // VDIVSDZrrb_Intk + 890408957U, // VDIVSDZrrb_Intkz + 283267069U, // VDIVSDrm + 283267069U, // VDIVSDrm_Int + 811651069U, // VDIVSDrr + 811651069U, // VDIVSDrr_Int + 283289821U, // VDIVSSZrm + 283289821U, // VDIVSSZrm_Int + 1358096605U, // VDIVSSZrm_Intk + 1089677533U, // VDIVSSZrm_Intkz + 811657437U, // VDIVSSZrr + 811657437U, // VDIVSSZrr_Int + 87058653U, // VDIVSSZrr_Intk + 890284253U, // VDIVSSZrr_Intkz + 812787933U, // VDIVSSZrrb_Int + 87189725U, // VDIVSSZrrb_Intk + 890415325U, // VDIVSSZrrb_Intkz + 283289821U, // VDIVSSrm + 283289821U, // VDIVSSrm_Int + 811657437U, // VDIVSSrr + 811657437U, // VDIVSSrr_Int + 300272728U, // VDPPDrmi + 1088818264U, // VDPPDrri + 375776657U, // VDPPSYrmi + 1088824721U, // VDPPSYrri + 300279185U, // VDPPSrmi + 1088824721U, // VDPPSrri + 221519U, // VERRm + 24911U, // VERRr + 224626U, // VERWm + 28018U, // VERWr + 1509843U, // VEXP2PDZm + 631867859U, // VEXP2PDZmb + 632293843U, // VEXP2PDZmbk + 631392723U, // VEXP2PDZmbkz + 3230779859U, // VEXP2PDZmk + 3230747091U, // VEXP2PDZmkz + 551832019U, // VEXP2PDZr + 551843250U, // VEXP2PDZrb + 3230709170U, // VEXP2PDZrbk + 3229676978U, // VEXP2PDZrbkz + 3230697939U, // VEXP2PDZrk + 3229665747U, // VEXP2PDZrkz + 1516259U, // VEXP2PSZm + 633987811U, // VEXP2PSZmb + 634594019U, // VEXP2PSZmbk + 633512675U, // VEXP2PSZmbkz + 3230786275U, // VEXP2PSZmk + 3230753507U, // VEXP2PSZmkz + 551838435U, // VEXP2PSZr + 551843755U, // VEXP2PSZrb + 3230709675U, // VEXP2PSZrbk + 3229677483U, // VEXP2PSZrbkz + 3230704355U, // VEXP2PSZrk + 3229672163U, // VEXP2PSZrkz + 658274U, // VEXPANDPDZ128rm + 3230600034U, // VEXPANDPDZ128rmk + 3229748066U, // VEXPANDPDZ128rmkz + 551832418U, // VEXPANDPDZ128rr + 3230698338U, // VEXPANDPDZ128rrk + 3229666146U, // VEXPANDPDZ128rrkz + 1346402U, // VEXPANDPDZ256rm + 3230731106U, // VEXPANDPDZ256rmk + 3230632802U, // VEXPANDPDZ256rmkz + 551832418U, // VEXPANDPDZ256rr + 3230698338U, // VEXPANDPDZ256rrk + 3229666146U, // VEXPANDPDZ256rrkz + 1510242U, // VEXPANDPDZrm + 3230780258U, // VEXPANDPDZrmk + 3230747490U, // VEXPANDPDZrmkz + 551832418U, // VEXPANDPDZrr + 3230698338U, // VEXPANDPDZrrk + 3229666146U, // VEXPANDPDZrrkz + 664694U, // VEXPANDPSZ128rm + 3230606454U, // VEXPANDPSZ128rmk + 3229754486U, // VEXPANDPSZ128rmkz + 551838838U, // VEXPANDPSZ128rr + 3230704758U, // VEXPANDPSZ128rrk + 3229672566U, // VEXPANDPSZ128rrkz + 1352822U, // VEXPANDPSZ256rm + 3230737526U, // VEXPANDPSZ256rmk + 3230639222U, // VEXPANDPSZ256rmkz + 551838838U, // VEXPANDPSZ256rr + 3230704758U, // VEXPANDPSZ256rrk + 3229672566U, // VEXPANDPSZ256rrkz + 1516662U, // VEXPANDPSZrm + 3230786678U, // VEXPANDPSZrmk + 3230753910U, // VEXPANDPSZrmkz + 551838838U, // VEXPANDPSZrr + 3230704758U, // VEXPANDPSZrrk + 3229672566U, // VEXPANDPSZrrkz + 1126466160U, // VEXTRACTF128mr + 283427440U, // VEXTRACTF128rr + 1126465941U, // VEXTRACTF32x4Z256mr + 1227211157U, // VEXTRACTF32x4Z256mrk + 283427221U, // VEXTRACTF32x4Z256rr + 1357578645U, // VEXTRACTF32x4Z256rrk + 1088815509U, // VEXTRACTF32x4Z256rrkz + 1126465941U, // VEXTRACTF32x4Zmr + 1227211157U, // VEXTRACTF32x4Zmrk + 283427221U, // VEXTRACTF32x4Zrr + 1357578645U, // VEXTRACTF32x4Zrrk + 1088815509U, // VEXTRACTF32x4Zrrkz + 1663337180U, // VEXTRACTF32x8Zmr + 1764082396U, // VEXTRACTF32x8Zmrk + 283427548U, // VEXTRACTF32x8Zrr + 1357578972U, // VEXTRACTF32x8Zrrk + 1088815836U, // VEXTRACTF32x8Zrrkz + 1126465728U, // VEXTRACTF64x2Z256mr + 1227210944U, // VEXTRACTF64x2Z256mrk + 283427008U, // VEXTRACTF64x2Z256rr + 1357578432U, // VEXTRACTF64x2Z256rrk + 1088815296U, // VEXTRACTF64x2Z256rrkz + 1126465728U, // VEXTRACTF64x2Zmr + 1227210944U, // VEXTRACTF64x2Zmrk + 283427008U, // VEXTRACTF64x2Zrr + 1357578432U, // VEXTRACTF64x2Zrrk + 1088815296U, // VEXTRACTF64x2Zrrkz + 1663336957U, // VEXTRACTF64x4Zmr + 1764082173U, // VEXTRACTF64x4Zmrk + 283427325U, // VEXTRACTF64x4Zrr + 1357578749U, // VEXTRACTF64x4Zrrk + 1088815613U, // VEXTRACTF64x4Zrrkz + 1931772583U, // VEXTRACTI128mr + 283427495U, // VEXTRACTI128rr + 1931772367U, // VEXTRACTI32x4Z256mr + 2032517583U, // VEXTRACTI32x4Z256mrk + 283427279U, // VEXTRACTI32x4Z256rr + 1357578703U, // VEXTRACTI32x4Z256rrk + 1088815567U, // VEXTRACTI32x4Z256rrkz + 1931772367U, // VEXTRACTI32x4Zmr + 2032517583U, // VEXTRACTI32x4Zmrk + 283427279U, // VEXTRACTI32x4Zrr + 1357578703U, // VEXTRACTI32x4Zrrk + 1088815567U, // VEXTRACTI32x4Zrrkz + 2200208138U, // VEXTRACTI32x8Zmr + 2300953354U, // VEXTRACTI32x8Zmrk + 283427594U, // VEXTRACTI32x8Zrr + 1357579018U, // VEXTRACTI32x8Zrrk + 1088815882U, // VEXTRACTI32x8Zrrkz + 1931772154U, // VEXTRACTI64x2Z256mr + 2032517370U, // VEXTRACTI64x2Z256mrk + 283427066U, // VEXTRACTI64x2Z256rr + 1357578490U, // VEXTRACTI64x2Z256rrk + 1088815354U, // VEXTRACTI64x2Z256rrkz + 1931772154U, // VEXTRACTI64x2Zmr + 2032517370U, // VEXTRACTI64x2Zmrk + 283427066U, // VEXTRACTI64x2Zrr + 1357578490U, // VEXTRACTI64x2Zrrk + 1088815354U, // VEXTRACTI64x2Zrrkz + 2200207915U, // VEXTRACTI64x4Zmr + 2300953131U, // VEXTRACTI64x4Zmrk + 283427371U, // VEXTRACTI64x4Zrr + 1357578795U, // VEXTRACTI64x4Zrrk + 1088815659U, // VEXTRACTI64x4Zrrkz + 3810829866U, // VEXTRACTPSZmr + 283436586U, // VEXTRACTPSZrr + 3810829866U, // VEXTRACTPSmr + 283436586U, // VEXTRACTPSrr + 3079932977U, // VFIXUPIMMPDZ128rmbi + 3111373873U, // VFIXUPIMMPDZ128rmbik + 3111373873U, // VFIXUPIMMPDZ128rmbikz + 1202981937U, // VFIXUPIMMPDZ128rmi + 2039729201U, // VFIXUPIMMPDZ128rmik + 2576600113U, // VFIXUPIMMPDZ128rmikz + 1357581361U, // VFIXUPIMMPDZ128rri + 2163133489U, // VFIXUPIMMPDZ128rrik + 2163133489U, // VFIXUPIMMPDZ128rrikz + 1737755697U, // VFIXUPIMMPDZ256rmbi + 1769196593U, // VFIXUPIMMPDZ256rmbik + 1769196593U, // VFIXUPIMMPDZ256rmbikz + 1205079089U, // VFIXUPIMMPDZ256rmi + 2041826353U, // VFIXUPIMMPDZ256rmik + 2578697265U, // VFIXUPIMMPDZ256rmikz + 1357581361U, // VFIXUPIMMPDZ256rri + 2163133489U, // VFIXUPIMMPDZ256rrik + 2163133489U, // VFIXUPIMMPDZ256rrikz + 2543062065U, // VFIXUPIMMPDZrmbi + 2574502961U, // VFIXUPIMMPDZrmbik + 2574502961U, // VFIXUPIMMPDZrmbikz + 1209273393U, // VFIXUPIMMPDZrmi + 2043923505U, // VFIXUPIMMPDZrmik + 2580794417U, // VFIXUPIMMPDZrmikz + 1357581361U, // VFIXUPIMMPDZrri + 1481313329U, // VFIXUPIMMPDZrrib + 2286865457U, // VFIXUPIMMPDZrribk + 2286865457U, // VFIXUPIMMPDZrribkz + 2163133489U, // VFIXUPIMMPDZrrik + 2163133489U, // VFIXUPIMMPDZrrikz + 1752442193U, // VFIXUPIMMPSZ128rmbi + 1777591633U, // VFIXUPIMMPSZ128rmbik + 1777591633U, // VFIXUPIMMPSZ128rmbikz + 1202988369U, // VFIXUPIMMPSZ128rmi + 2039735633U, // VFIXUPIMMPSZ128rmik + 2576606545U, // VFIXUPIMMPSZ128rmikz + 1357587793U, // VFIXUPIMMPSZ128rri + 2163139921U, // VFIXUPIMMPSZ128rrik + 2163139921U, // VFIXUPIMMPSZ128rrikz + 2557748561U, // VFIXUPIMMPSZ256rmbi + 2582898001U, // VFIXUPIMMPSZ256rmbik + 2582898001U, // VFIXUPIMMPSZ256rmbikz + 1205085521U, // VFIXUPIMMPSZ256rmi + 2041832785U, // VFIXUPIMMPSZ256rmik + 2578703697U, // VFIXUPIMMPSZ256rmikz + 1357587793U, // VFIXUPIMMPSZ256rri + 2163139921U, // VFIXUPIMMPSZ256rrik + 2163139921U, // VFIXUPIMMPSZ256rrikz + 2826184017U, // VFIXUPIMMPSZrmbi + 2851333457U, // VFIXUPIMMPSZrmbik + 2851333457U, // VFIXUPIMMPSZrmbikz + 1209279825U, // VFIXUPIMMPSZrmi + 2043929937U, // VFIXUPIMMPSZrmik + 2580800849U, // VFIXUPIMMPSZrmikz + 1357587793U, // VFIXUPIMMPSZrri + 1481319761U, // VFIXUPIMMPSZrrib + 2286871889U, // VFIXUPIMMPSZrribk + 2286871889U, // VFIXUPIMMPSZrribkz + 2163139921U, // VFIXUPIMMPSZrrik + 2163139921U, // VFIXUPIMMPSZrrikz + 932450137U, // VFIXUPIMMSDZrmi + 963891033U, // VFIXUPIMMSDZrmik + 963891033U, // VFIXUPIMMSDZrmikz + 1357582169U, // VFIXUPIMMSDZrri + 1481314137U, // VFIXUPIMMSDZrrib + 2286866265U, // VFIXUPIMMSDZrribk + 2286866265U, // VFIXUPIMMSDZrribkz + 2163134297U, // VFIXUPIMMSDZrrik + 2163134297U, // VFIXUPIMMSDZrrikz + 947136619U, // VFIXUPIMMSSZrmi + 972286059U, // VFIXUPIMMSSZrmik + 972286059U, // VFIXUPIMMSSZrmikz + 1357588587U, // VFIXUPIMMSSZrri + 1481320555U, // VFIXUPIMMSSZrrib + 2286872683U, // VFIXUPIMMSSZrribk + 2286872683U, // VFIXUPIMMSSZrribkz + 2163140715U, // VFIXUPIMMSSZrrik + 2163140715U, // VFIXUPIMMSSZrrikz + 890309015U, // VFMADD132PDYm + 890276247U, // VFMADD132PDYr + 890177943U, // VFMADD132PDZ128m + 1164970391U, // VFMADD132PDZ128mb + 1433389463U, // VFMADD132PDZ128mbk + 1433389463U, // VFMADD132PDZ128mbkz + 86985111U, // VFMADD132PDZ128mk + 89082263U, // VFMADD132PDZ128mkz + 890276247U, // VFMADD132PDZ128r + 87050647U, // VFMADD132PDZ128rk + 89147799U, // VFMADD132PDZ128rkz + 890309015U, // VFMADD132PDZ256m + 1167067543U, // VFMADD132PDZ256mb + 1435486615U, // VFMADD132PDZ256mbk + 1435486615U, // VFMADD132PDZ256mbkz + 87083415U, // VFMADD132PDZ256mk + 89180567U, // VFMADD132PDZ256mkz + 890276247U, // VFMADD132PDZ256r + 87050647U, // VFMADD132PDZ256rk + 89147799U, // VFMADD132PDZ256rkz + 890358167U, // VFMADD132PDZm + 1169164695U, // VFMADD132PDZmb + 1437583767U, // VFMADD132PDZmbk + 1437583767U, // VFMADD132PDZmbkz + 87132567U, // VFMADD132PDZmk + 89229719U, // VFMADD132PDZmkz + 890276247U, // VFMADD132PDZr + 890407319U, // VFMADD132PDZrb + 87181719U, // VFMADD132PDZrbk + 89278871U, // VFMADD132PDZrbkz + 87050647U, // VFMADD132PDZrk + 89147799U, // VFMADD132PDZrkz + 890177943U, // VFMADD132PDm + 890276247U, // VFMADD132PDr + 890315409U, // VFMADD132PSYm + 890282641U, // VFMADD132PSYr + 890184337U, // VFMADD132PSZ128m + 1167270545U, // VFMADD132PSZ128mb + 1435689617U, // VFMADD132PSZ128mbk + 1435689617U, // VFMADD132PSZ128mbkz + 86991505U, // VFMADD132PSZ128mk + 89088657U, // VFMADD132PSZ128mkz + 890282641U, // VFMADD132PSZ128r + 87057041U, // VFMADD132PSZ128rk + 89154193U, // VFMADD132PSZ128rkz + 890315409U, // VFMADD132PSZ256m + 1169367697U, // VFMADD132PSZ256mb + 1437786769U, // VFMADD132PSZ256mbk + 1437786769U, // VFMADD132PSZ256mbkz + 87089809U, // VFMADD132PSZ256mk + 89186961U, // VFMADD132PSZ256mkz + 890282641U, // VFMADD132PSZ256r + 87057041U, // VFMADD132PSZ256rk + 89154193U, // VFMADD132PSZ256rkz + 890364561U, // VFMADD132PSZm + 1171464849U, // VFMADD132PSZmb + 1439883921U, // VFMADD132PSZmbk + 1439883921U, // VFMADD132PSZmbkz + 87138961U, // VFMADD132PSZmk + 89236113U, // VFMADD132PSZmkz + 890282641U, // VFMADD132PSZr + 890413713U, // VFMADD132PSZrb + 87188113U, // VFMADD132PSZrbk + 89285265U, // VFMADD132PSZrbkz + 87057041U, // VFMADD132PSZrk + 89154193U, // VFMADD132PSZrkz + 890184337U, // VFMADD132PSm + 890282641U, // VFMADD132PSr + 1089474109U, // VFMADD132SDZm + 1089474109U, // VFMADD132SDZm_Int + 1357893181U, // VFMADD132SDZm_Intk + 1357893181U, // VFMADD132SDZm_Intkz + 890277437U, // VFMADD132SDZr + 890277437U, // VFMADD132SDZr_Int + 87051837U, // VFMADD132SDZr_Intk + 89148989U, // VFMADD132SDZr_Intkz + 890277437U, // VFMADD132SDZrb + 890408509U, // VFMADD132SDZrb_Int + 87182909U, // VFMADD132SDZrb_Intk + 89280061U, // VFMADD132SDZrb_Intkz + 1089474109U, // VFMADD132SDm + 1089474109U, // VFMADD132SDm_Int + 890277437U, // VFMADD132SDr + 890277437U, // VFMADD132SDr_Int + 1089677120U, // VFMADD132SSZm + 1089677120U, // VFMADD132SSZm_Int + 1358096192U, // VFMADD132SSZm_Intk + 1358096192U, // VFMADD132SSZm_Intkz + 890283840U, // VFMADD132SSZr + 890283840U, // VFMADD132SSZr_Int + 87058240U, // VFMADD132SSZr_Intk + 89155392U, // VFMADD132SSZr_Intkz + 890283840U, // VFMADD132SSZrb + 890414912U, // VFMADD132SSZrb_Int + 87189312U, // VFMADD132SSZrb_Intk + 89286464U, // VFMADD132SSZrb_Intkz + 1089677120U, // VFMADD132SSm + 1089677120U, // VFMADD132SSm_Int + 890283840U, // VFMADD132SSr + 890283840U, // VFMADD132SSr_Int + 890309211U, // VFMADD213PDYm + 890276443U, // VFMADD213PDYr + 890178139U, // VFMADD213PDZ128m + 1164970587U, // VFMADD213PDZ128mb + 1433389659U, // VFMADD213PDZ128mbk + 1433389659U, // VFMADD213PDZ128mbkz + 86985307U, // VFMADD213PDZ128mk + 89082459U, // VFMADD213PDZ128mkz + 890276443U, // VFMADD213PDZ128r + 87050843U, // VFMADD213PDZ128rk + 89147995U, // VFMADD213PDZ128rkz + 890309211U, // VFMADD213PDZ256m + 1167067739U, // VFMADD213PDZ256mb + 1435486811U, // VFMADD213PDZ256mbk + 1435486811U, // VFMADD213PDZ256mbkz + 87083611U, // VFMADD213PDZ256mk + 89180763U, // VFMADD213PDZ256mkz + 890276443U, // VFMADD213PDZ256r + 87050843U, // VFMADD213PDZ256rk + 89147995U, // VFMADD213PDZ256rkz + 890358363U, // VFMADD213PDZm + 1169164891U, // VFMADD213PDZmb + 1437583963U, // VFMADD213PDZmbk + 1437583963U, // VFMADD213PDZmbkz + 87132763U, // VFMADD213PDZmk + 89229915U, // VFMADD213PDZmkz + 890276443U, // VFMADD213PDZr + 890407515U, // VFMADD213PDZrb + 87181915U, // VFMADD213PDZrbk + 89279067U, // VFMADD213PDZrbkz + 87050843U, // VFMADD213PDZrk + 89147995U, // VFMADD213PDZrkz + 890178139U, // VFMADD213PDm + 890276443U, // VFMADD213PDr + 890315616U, // VFMADD213PSYm + 890282848U, // VFMADD213PSYr + 890184544U, // VFMADD213PSZ128m + 1167270752U, // VFMADD213PSZ128mb + 1435689824U, // VFMADD213PSZ128mbk + 1435689824U, // VFMADD213PSZ128mbkz + 86991712U, // VFMADD213PSZ128mk + 89088864U, // VFMADD213PSZ128mkz + 890282848U, // VFMADD213PSZ128r + 87057248U, // VFMADD213PSZ128rk + 89154400U, // VFMADD213PSZ128rkz + 890315616U, // VFMADD213PSZ256m + 1169367904U, // VFMADD213PSZ256mb + 1437786976U, // VFMADD213PSZ256mbk + 1437786976U, // VFMADD213PSZ256mbkz + 87090016U, // VFMADD213PSZ256mk + 89187168U, // VFMADD213PSZ256mkz + 890282848U, // VFMADD213PSZ256r + 87057248U, // VFMADD213PSZ256rk + 89154400U, // VFMADD213PSZ256rkz + 890364768U, // VFMADD213PSZm + 1171465056U, // VFMADD213PSZmb + 1439884128U, // VFMADD213PSZmbk + 1439884128U, // VFMADD213PSZmbkz + 87139168U, // VFMADD213PSZmk + 89236320U, // VFMADD213PSZmkz + 890282848U, // VFMADD213PSZr + 890413920U, // VFMADD213PSZrb + 87188320U, // VFMADD213PSZrbk + 89285472U, // VFMADD213PSZrbkz + 87057248U, // VFMADD213PSZrk + 89154400U, // VFMADD213PSZrkz + 890184544U, // VFMADD213PSm + 890282848U, // VFMADD213PSr + 1089474174U, // VFMADD213SDZm + 1089474174U, // VFMADD213SDZm_Int + 1357893246U, // VFMADD213SDZm_Intk + 1357893246U, // VFMADD213SDZm_Intkz + 890277502U, // VFMADD213SDZr + 890277502U, // VFMADD213SDZr_Int + 87051902U, // VFMADD213SDZr_Intk + 89149054U, // VFMADD213SDZr_Intkz + 890277502U, // VFMADD213SDZrb + 890408574U, // VFMADD213SDZrb_Int + 87182974U, // VFMADD213SDZrb_Intk + 89280126U, // VFMADD213SDZrb_Intkz + 1089474174U, // VFMADD213SDm + 1089474174U, // VFMADD213SDm_Int + 890277502U, // VFMADD213SDr + 890277502U, // VFMADD213SDr_Int + 1089677185U, // VFMADD213SSZm + 1089677185U, // VFMADD213SSZm_Int + 1358096257U, // VFMADD213SSZm_Intk + 1358096257U, // VFMADD213SSZm_Intkz + 890283905U, // VFMADD213SSZr + 890283905U, // VFMADD213SSZr_Int + 87058305U, // VFMADD213SSZr_Intk + 89155457U, // VFMADD213SSZr_Intkz + 890283905U, // VFMADD213SSZrb + 890414977U, // VFMADD213SSZrb_Int + 87189377U, // VFMADD213SSZrb_Intk + 89286529U, // VFMADD213SSZrb_Intkz + 1089677185U, // VFMADD213SSm + 1089677185U, // VFMADD213SSm_Int + 890283905U, // VFMADD213SSr + 890283905U, // VFMADD213SSr_Int + 890308929U, // VFMADD231PDYm + 890276161U, // VFMADD231PDYr + 890177857U, // VFMADD231PDZ128m + 1164970305U, // VFMADD231PDZ128mb + 1433389377U, // VFMADD231PDZ128mbk + 1433389377U, // VFMADD231PDZ128mbkz + 86985025U, // VFMADD231PDZ128mk + 89082177U, // VFMADD231PDZ128mkz + 890276161U, // VFMADD231PDZ128r + 87050561U, // VFMADD231PDZ128rk + 89147713U, // VFMADD231PDZ128rkz + 890308929U, // VFMADD231PDZ256m + 1167067457U, // VFMADD231PDZ256mb + 1435486529U, // VFMADD231PDZ256mbk + 1435486529U, // VFMADD231PDZ256mbkz + 87083329U, // VFMADD231PDZ256mk + 89180481U, // VFMADD231PDZ256mkz + 890276161U, // VFMADD231PDZ256r + 87050561U, // VFMADD231PDZ256rk + 89147713U, // VFMADD231PDZ256rkz + 890358081U, // VFMADD231PDZm + 1169164609U, // VFMADD231PDZmb + 1437583681U, // VFMADD231PDZmbk + 1437583681U, // VFMADD231PDZmbkz + 87132481U, // VFMADD231PDZmk + 89229633U, // VFMADD231PDZmkz + 890276161U, // VFMADD231PDZr + 890407233U, // VFMADD231PDZrb + 87181633U, // VFMADD231PDZrbk + 89278785U, // VFMADD231PDZrbkz + 87050561U, // VFMADD231PDZrk + 89147713U, // VFMADD231PDZrkz + 890177857U, // VFMADD231PDm + 890276161U, // VFMADD231PDr + 890315323U, // VFMADD231PSYm + 890282555U, // VFMADD231PSYr + 890184251U, // VFMADD231PSZ128m + 1167270459U, // VFMADD231PSZ128mb + 1435689531U, // VFMADD231PSZ128mbk + 1435689531U, // VFMADD231PSZ128mbkz + 86991419U, // VFMADD231PSZ128mk + 89088571U, // VFMADD231PSZ128mkz + 890282555U, // VFMADD231PSZ128r + 87056955U, // VFMADD231PSZ128rk + 89154107U, // VFMADD231PSZ128rkz + 890315323U, // VFMADD231PSZ256m + 1169367611U, // VFMADD231PSZ256mb + 1437786683U, // VFMADD231PSZ256mbk + 1437786683U, // VFMADD231PSZ256mbkz + 87089723U, // VFMADD231PSZ256mk + 89186875U, // VFMADD231PSZ256mkz + 890282555U, // VFMADD231PSZ256r + 87056955U, // VFMADD231PSZ256rk + 89154107U, // VFMADD231PSZ256rkz + 890364475U, // VFMADD231PSZm + 1171464763U, // VFMADD231PSZmb + 1439883835U, // VFMADD231PSZmbk + 1439883835U, // VFMADD231PSZmbkz + 87138875U, // VFMADD231PSZmk + 89236027U, // VFMADD231PSZmkz + 890282555U, // VFMADD231PSZr + 890413627U, // VFMADD231PSZrb + 87188027U, // VFMADD231PSZrbk + 89285179U, // VFMADD231PSZrbkz + 87056955U, // VFMADD231PSZrk + 89154107U, // VFMADD231PSZrkz + 890184251U, // VFMADD231PSm + 890282555U, // VFMADD231PSr + 1089474055U, // VFMADD231SDZm + 1089474055U, // VFMADD231SDZm_Int + 1357893127U, // VFMADD231SDZm_Intk + 1357893127U, // VFMADD231SDZm_Intkz + 890277383U, // VFMADD231SDZr + 890277383U, // VFMADD231SDZr_Int + 87051783U, // VFMADD231SDZr_Intk + 89148935U, // VFMADD231SDZr_Intkz + 890277383U, // VFMADD231SDZrb + 890408455U, // VFMADD231SDZrb_Int + 87182855U, // VFMADD231SDZrb_Intk + 89280007U, // VFMADD231SDZrb_Intkz + 1089474055U, // VFMADD231SDm + 1089474055U, // VFMADD231SDm_Int + 890277383U, // VFMADD231SDr + 890277383U, // VFMADD231SDr_Int + 1089677066U, // VFMADD231SSZm + 1089677066U, // VFMADD231SSZm_Int + 1358096138U, // VFMADD231SSZm_Intk + 1358096138U, // VFMADD231SSZm_Intkz + 890283786U, // VFMADD231SSZr + 890283786U, // VFMADD231SSZr_Int + 87058186U, // VFMADD231SSZr_Intk + 89155338U, // VFMADD231SSZr_Intkz + 890283786U, // VFMADD231SSZrb + 890414858U, // VFMADD231SSZrb_Int + 87189258U, // VFMADD231SSZrb_Intk + 89286410U, // VFMADD231SSZrb_Intkz + 1089677066U, // VFMADD231SSm + 1089677066U, // VFMADD231SSm_Int + 890283786U, // VFMADD231SSr + 890283786U, // VFMADD231SSr_Int + 393497413U, // VFMADDPD4Ymr + 890309445U, // VFMADDPD4Yrm + 890276677U, // VFMADDPD4Yrr + 890276677U, // VFMADDPD4Yrr_REV + 301222725U, // VFMADDPD4mr + 890178373U, // VFMADDPD4rm + 890276677U, // VFMADDPD4rr + 890276677U, // VFMADDPD4rr_REV + 393503821U, // VFMADDPS4Ymr + 890315853U, // VFMADDPS4Yrm + 890283085U, // VFMADDPS4Yrr + 890283085U, // VFMADDPS4Yrr_REV + 301229133U, // VFMADDPS4mr + 890184781U, // VFMADDPS4rm + 890283085U, // VFMADDPS4rr + 890283085U, // VFMADDPS4rr_REV + 852774634U, // VFMADDSD4mr + 852774634U, // VFMADDSD4mr_Int + 1089474282U, // VFMADDSD4rm + 1089474282U, // VFMADDSD4rm_Int + 890277610U, // VFMADDSD4rr + 890277610U, // VFMADDSD4rr_Int + 890277610U, // VFMADDSD4rr_Int_REV + 890277610U, // VFMADDSD4rr_REV + 856975344U, // VFMADDSS4mr + 856975344U, // VFMADDSS4mr_Int + 1089677296U, // VFMADDSS4rm + 1089677296U, // VFMADDSS4rm_Int + 890284016U, // VFMADDSS4rr + 890284016U, // VFMADDSS4rr_Int + 890284016U, // VFMADDSS4rr_Int_REV + 890284016U, // VFMADDSS4rr_REV + 890308956U, // VFMADDSUB132PDYm + 890276188U, // VFMADDSUB132PDYr + 890177884U, // VFMADDSUB132PDZ128m + 1164970332U, // VFMADDSUB132PDZ128mb + 1433389404U, // VFMADDSUB132PDZ128mbk + 1433389404U, // VFMADDSUB132PDZ128mbkz + 86985052U, // VFMADDSUB132PDZ128mk + 89082204U, // VFMADDSUB132PDZ128mkz + 890276188U, // VFMADDSUB132PDZ128r + 87050588U, // VFMADDSUB132PDZ128rk + 89147740U, // VFMADDSUB132PDZ128rkz + 890308956U, // VFMADDSUB132PDZ256m + 1167067484U, // VFMADDSUB132PDZ256mb + 1435486556U, // VFMADDSUB132PDZ256mbk + 1435486556U, // VFMADDSUB132PDZ256mbkz + 87083356U, // VFMADDSUB132PDZ256mk + 89180508U, // VFMADDSUB132PDZ256mkz + 890276188U, // VFMADDSUB132PDZ256r + 87050588U, // VFMADDSUB132PDZ256rk + 89147740U, // VFMADDSUB132PDZ256rkz + 890358108U, // VFMADDSUB132PDZm + 1169164636U, // VFMADDSUB132PDZmb + 1437583708U, // VFMADDSUB132PDZmbk + 1437583708U, // VFMADDSUB132PDZmbkz + 87132508U, // VFMADDSUB132PDZmk + 89229660U, // VFMADDSUB132PDZmkz + 890276188U, // VFMADDSUB132PDZr + 890407260U, // VFMADDSUB132PDZrb + 87181660U, // VFMADDSUB132PDZrbk + 89278812U, // VFMADDSUB132PDZrbkz + 87050588U, // VFMADDSUB132PDZrk + 89147740U, // VFMADDSUB132PDZrkz + 890177884U, // VFMADDSUB132PDm + 890276188U, // VFMADDSUB132PDr + 890315350U, // VFMADDSUB132PSYm + 890282582U, // VFMADDSUB132PSYr + 890184278U, // VFMADDSUB132PSZ128m + 1167270486U, // VFMADDSUB132PSZ128mb + 1435689558U, // VFMADDSUB132PSZ128mbk + 1435689558U, // VFMADDSUB132PSZ128mbkz + 86991446U, // VFMADDSUB132PSZ128mk + 89088598U, // VFMADDSUB132PSZ128mkz + 890282582U, // VFMADDSUB132PSZ128r + 87056982U, // VFMADDSUB132PSZ128rk + 89154134U, // VFMADDSUB132PSZ128rkz + 890315350U, // VFMADDSUB132PSZ256m + 1169367638U, // VFMADDSUB132PSZ256mb + 1437786710U, // VFMADDSUB132PSZ256mbk + 1437786710U, // VFMADDSUB132PSZ256mbkz + 87089750U, // VFMADDSUB132PSZ256mk + 89186902U, // VFMADDSUB132PSZ256mkz + 890282582U, // VFMADDSUB132PSZ256r + 87056982U, // VFMADDSUB132PSZ256rk + 89154134U, // VFMADDSUB132PSZ256rkz + 890364502U, // VFMADDSUB132PSZm + 1171464790U, // VFMADDSUB132PSZmb + 1439883862U, // VFMADDSUB132PSZmbk + 1439883862U, // VFMADDSUB132PSZmbkz + 87138902U, // VFMADDSUB132PSZmk + 89236054U, // VFMADDSUB132PSZmkz + 890282582U, // VFMADDSUB132PSZr + 890413654U, // VFMADDSUB132PSZrb + 87188054U, // VFMADDSUB132PSZrbk + 89285206U, // VFMADDSUB132PSZrbkz + 87056982U, // VFMADDSUB132PSZrk + 89154134U, // VFMADDSUB132PSZrkz + 890184278U, // VFMADDSUB132PSm + 890282582U, // VFMADDSUB132PSr + 890309152U, // VFMADDSUB213PDYm + 890276384U, // VFMADDSUB213PDYr + 890178080U, // VFMADDSUB213PDZ128m + 1164970528U, // VFMADDSUB213PDZ128mb + 1433389600U, // VFMADDSUB213PDZ128mbk + 1433389600U, // VFMADDSUB213PDZ128mbkz + 86985248U, // VFMADDSUB213PDZ128mk + 89082400U, // VFMADDSUB213PDZ128mkz + 890276384U, // VFMADDSUB213PDZ128r + 87050784U, // VFMADDSUB213PDZ128rk + 89147936U, // VFMADDSUB213PDZ128rkz + 890309152U, // VFMADDSUB213PDZ256m + 1167067680U, // VFMADDSUB213PDZ256mb + 1435486752U, // VFMADDSUB213PDZ256mbk + 1435486752U, // VFMADDSUB213PDZ256mbkz + 87083552U, // VFMADDSUB213PDZ256mk + 89180704U, // VFMADDSUB213PDZ256mkz + 890276384U, // VFMADDSUB213PDZ256r + 87050784U, // VFMADDSUB213PDZ256rk + 89147936U, // VFMADDSUB213PDZ256rkz + 890358304U, // VFMADDSUB213PDZm + 1169164832U, // VFMADDSUB213PDZmb + 1437583904U, // VFMADDSUB213PDZmbk + 1437583904U, // VFMADDSUB213PDZmbkz + 87132704U, // VFMADDSUB213PDZmk + 89229856U, // VFMADDSUB213PDZmkz + 890276384U, // VFMADDSUB213PDZr + 890407456U, // VFMADDSUB213PDZrb + 87181856U, // VFMADDSUB213PDZrbk + 89279008U, // VFMADDSUB213PDZrbkz + 87050784U, // VFMADDSUB213PDZrk + 89147936U, // VFMADDSUB213PDZrkz + 890178080U, // VFMADDSUB213PDm + 890276384U, // VFMADDSUB213PDr + 890315557U, // VFMADDSUB213PSYm + 890282789U, // VFMADDSUB213PSYr + 890184485U, // VFMADDSUB213PSZ128m + 1167270693U, // VFMADDSUB213PSZ128mb + 1435689765U, // VFMADDSUB213PSZ128mbk + 1435689765U, // VFMADDSUB213PSZ128mbkz + 86991653U, // VFMADDSUB213PSZ128mk + 89088805U, // VFMADDSUB213PSZ128mkz + 890282789U, // VFMADDSUB213PSZ128r + 87057189U, // VFMADDSUB213PSZ128rk + 89154341U, // VFMADDSUB213PSZ128rkz + 890315557U, // VFMADDSUB213PSZ256m + 1169367845U, // VFMADDSUB213PSZ256mb + 1437786917U, // VFMADDSUB213PSZ256mbk + 1437786917U, // VFMADDSUB213PSZ256mbkz + 87089957U, // VFMADDSUB213PSZ256mk + 89187109U, // VFMADDSUB213PSZ256mkz + 890282789U, // VFMADDSUB213PSZ256r + 87057189U, // VFMADDSUB213PSZ256rk + 89154341U, // VFMADDSUB213PSZ256rkz + 890364709U, // VFMADDSUB213PSZm + 1171464997U, // VFMADDSUB213PSZmb + 1439884069U, // VFMADDSUB213PSZmbk + 1439884069U, // VFMADDSUB213PSZmbkz + 87139109U, // VFMADDSUB213PSZmk + 89236261U, // VFMADDSUB213PSZmkz + 890282789U, // VFMADDSUB213PSZr + 890413861U, // VFMADDSUB213PSZrb + 87188261U, // VFMADDSUB213PSZrbk + 89285413U, // VFMADDSUB213PSZrbkz + 87057189U, // VFMADDSUB213PSZrk + 89154341U, // VFMADDSUB213PSZrkz + 890184485U, // VFMADDSUB213PSm + 890282789U, // VFMADDSUB213PSr + 890308870U, // VFMADDSUB231PDYm + 890276102U, // VFMADDSUB231PDYr + 890177798U, // VFMADDSUB231PDZ128m + 1164970246U, // VFMADDSUB231PDZ128mb + 1433389318U, // VFMADDSUB231PDZ128mbk + 1433389318U, // VFMADDSUB231PDZ128mbkz + 86984966U, // VFMADDSUB231PDZ128mk + 89082118U, // VFMADDSUB231PDZ128mkz + 890276102U, // VFMADDSUB231PDZ128r + 87050502U, // VFMADDSUB231PDZ128rk + 89147654U, // VFMADDSUB231PDZ128rkz + 890308870U, // VFMADDSUB231PDZ256m + 1167067398U, // VFMADDSUB231PDZ256mb + 1435486470U, // VFMADDSUB231PDZ256mbk + 1435486470U, // VFMADDSUB231PDZ256mbkz + 87083270U, // VFMADDSUB231PDZ256mk + 89180422U, // VFMADDSUB231PDZ256mkz + 890276102U, // VFMADDSUB231PDZ256r + 87050502U, // VFMADDSUB231PDZ256rk + 89147654U, // VFMADDSUB231PDZ256rkz + 890358022U, // VFMADDSUB231PDZm + 1169164550U, // VFMADDSUB231PDZmb + 1437583622U, // VFMADDSUB231PDZmbk + 1437583622U, // VFMADDSUB231PDZmbkz + 87132422U, // VFMADDSUB231PDZmk + 89229574U, // VFMADDSUB231PDZmkz + 890276102U, // VFMADDSUB231PDZr + 890407174U, // VFMADDSUB231PDZrb + 87181574U, // VFMADDSUB231PDZrbk + 89278726U, // VFMADDSUB231PDZrbkz + 87050502U, // VFMADDSUB231PDZrk + 89147654U, // VFMADDSUB231PDZrkz + 890177798U, // VFMADDSUB231PDm + 890276102U, // VFMADDSUB231PDr + 890315264U, // VFMADDSUB231PSYm + 890282496U, // VFMADDSUB231PSYr + 890184192U, // VFMADDSUB231PSZ128m + 1167270400U, // VFMADDSUB231PSZ128mb + 1435689472U, // VFMADDSUB231PSZ128mbk + 1435689472U, // VFMADDSUB231PSZ128mbkz + 86991360U, // VFMADDSUB231PSZ128mk + 89088512U, // VFMADDSUB231PSZ128mkz + 890282496U, // VFMADDSUB231PSZ128r + 87056896U, // VFMADDSUB231PSZ128rk + 89154048U, // VFMADDSUB231PSZ128rkz + 890315264U, // VFMADDSUB231PSZ256m + 1169367552U, // VFMADDSUB231PSZ256mb + 1437786624U, // VFMADDSUB231PSZ256mbk + 1437786624U, // VFMADDSUB231PSZ256mbkz + 87089664U, // VFMADDSUB231PSZ256mk + 89186816U, // VFMADDSUB231PSZ256mkz + 890282496U, // VFMADDSUB231PSZ256r + 87056896U, // VFMADDSUB231PSZ256rk + 89154048U, // VFMADDSUB231PSZ256rkz + 890364416U, // VFMADDSUB231PSZm + 1171464704U, // VFMADDSUB231PSZmb + 1439883776U, // VFMADDSUB231PSZmbk + 1439883776U, // VFMADDSUB231PSZmbkz + 87138816U, // VFMADDSUB231PSZmk + 89235968U, // VFMADDSUB231PSZmkz + 890282496U, // VFMADDSUB231PSZr + 890413568U, // VFMADDSUB231PSZrb + 87187968U, // VFMADDSUB231PSZrbk + 89285120U, // VFMADDSUB231PSZrbkz + 87056896U, // VFMADDSUB231PSZrk + 89154048U, // VFMADDSUB231PSZrkz + 890184192U, // VFMADDSUB231PSm + 890282496U, // VFMADDSUB231PSr + 393497267U, // VFMADDSUBPD4Ymr + 890309299U, // VFMADDSUBPD4Yrm + 890276531U, // VFMADDSUBPD4Yrr + 890276531U, // VFMADDSUBPD4Yrr_REV + 301222579U, // VFMADDSUBPD4mr + 890178227U, // VFMADDSUBPD4rm + 890276531U, // VFMADDSUBPD4rr + 890276531U, // VFMADDSUBPD4rr_REV + 393503664U, // VFMADDSUBPS4Ymr + 890315696U, // VFMADDSUBPS4Yrm + 890282928U, // VFMADDSUBPS4Yrr + 890282928U, // VFMADDSUBPS4Yrr_REV + 301228976U, // VFMADDSUBPS4mr + 890184624U, // VFMADDSUBPS4rm + 890282928U, // VFMADDSUBPS4rr + 890282928U, // VFMADDSUBPS4rr_REV + 890308972U, // VFMSUB132PDYm + 890276204U, // VFMSUB132PDYr + 890177900U, // VFMSUB132PDZ128m + 1164970348U, // VFMSUB132PDZ128mb + 1433389420U, // VFMSUB132PDZ128mbk + 1433389420U, // VFMSUB132PDZ128mbkz + 86985068U, // VFMSUB132PDZ128mk + 89082220U, // VFMSUB132PDZ128mkz + 890276204U, // VFMSUB132PDZ128r + 87050604U, // VFMSUB132PDZ128rk + 89147756U, // VFMSUB132PDZ128rkz + 890308972U, // VFMSUB132PDZ256m + 1167067500U, // VFMSUB132PDZ256mb + 1435486572U, // VFMSUB132PDZ256mbk + 1435486572U, // VFMSUB132PDZ256mbkz + 87083372U, // VFMSUB132PDZ256mk + 89180524U, // VFMSUB132PDZ256mkz + 890276204U, // VFMSUB132PDZ256r + 87050604U, // VFMSUB132PDZ256rk + 89147756U, // VFMSUB132PDZ256rkz + 890358124U, // VFMSUB132PDZm + 1169164652U, // VFMSUB132PDZmb + 1437583724U, // VFMSUB132PDZmbk + 1437583724U, // VFMSUB132PDZmbkz + 87132524U, // VFMSUB132PDZmk + 89229676U, // VFMSUB132PDZmkz + 890276204U, // VFMSUB132PDZr + 890407276U, // VFMSUB132PDZrb + 87181676U, // VFMSUB132PDZrbk + 89278828U, // VFMSUB132PDZrbkz + 87050604U, // VFMSUB132PDZrk + 89147756U, // VFMSUB132PDZrkz + 890177900U, // VFMSUB132PDm + 890276204U, // VFMSUB132PDr + 890315366U, // VFMSUB132PSYm + 890282598U, // VFMSUB132PSYr + 890184294U, // VFMSUB132PSZ128m + 1167270502U, // VFMSUB132PSZ128mb + 1435689574U, // VFMSUB132PSZ128mbk + 1435689574U, // VFMSUB132PSZ128mbkz + 86991462U, // VFMSUB132PSZ128mk + 89088614U, // VFMSUB132PSZ128mkz + 890282598U, // VFMSUB132PSZ128r + 87056998U, // VFMSUB132PSZ128rk + 89154150U, // VFMSUB132PSZ128rkz + 890315366U, // VFMSUB132PSZ256m + 1169367654U, // VFMSUB132PSZ256mb + 1437786726U, // VFMSUB132PSZ256mbk + 1437786726U, // VFMSUB132PSZ256mbkz + 87089766U, // VFMSUB132PSZ256mk + 89186918U, // VFMSUB132PSZ256mkz + 890282598U, // VFMSUB132PSZ256r + 87056998U, // VFMSUB132PSZ256rk + 89154150U, // VFMSUB132PSZ256rkz + 890364518U, // VFMSUB132PSZm + 1171464806U, // VFMSUB132PSZmb + 1439883878U, // VFMSUB132PSZmbk + 1439883878U, // VFMSUB132PSZmbkz + 87138918U, // VFMSUB132PSZmk + 89236070U, // VFMSUB132PSZmkz + 890282598U, // VFMSUB132PSZr + 890413670U, // VFMSUB132PSZrb + 87188070U, // VFMSUB132PSZrbk + 89285222U, // VFMSUB132PSZrbkz + 87056998U, // VFMSUB132PSZrk + 89154150U, // VFMSUB132PSZrkz + 890184294U, // VFMSUB132PSm + 890282598U, // VFMSUB132PSr + 1089474082U, // VFMSUB132SDZm + 1089474082U, // VFMSUB132SDZm_Int + 1357893154U, // VFMSUB132SDZm_Intk + 1357893154U, // VFMSUB132SDZm_Intkz + 890277410U, // VFMSUB132SDZr + 890277410U, // VFMSUB132SDZr_Int + 87051810U, // VFMSUB132SDZr_Intk + 89148962U, // VFMSUB132SDZr_Intkz + 890277410U, // VFMSUB132SDZrb + 890408482U, // VFMSUB132SDZrb_Int + 87182882U, // VFMSUB132SDZrb_Intk + 89280034U, // VFMSUB132SDZrb_Intkz + 1089474082U, // VFMSUB132SDm + 1089474082U, // VFMSUB132SDm_Int + 890277410U, // VFMSUB132SDr + 890277410U, // VFMSUB132SDr_Int + 1089677093U, // VFMSUB132SSZm + 1089677093U, // VFMSUB132SSZm_Int + 1358096165U, // VFMSUB132SSZm_Intk + 1358096165U, // VFMSUB132SSZm_Intkz + 890283813U, // VFMSUB132SSZr + 890283813U, // VFMSUB132SSZr_Int + 87058213U, // VFMSUB132SSZr_Intk + 89155365U, // VFMSUB132SSZr_Intkz + 890283813U, // VFMSUB132SSZrb + 890414885U, // VFMSUB132SSZrb_Int + 87189285U, // VFMSUB132SSZrb_Intk + 89286437U, // VFMSUB132SSZrb_Intkz + 1089677093U, // VFMSUB132SSm + 1089677093U, // VFMSUB132SSm_Int + 890283813U, // VFMSUB132SSr + 890283813U, // VFMSUB132SSr_Int + 890309168U, // VFMSUB213PDYm + 890276400U, // VFMSUB213PDYr + 890178096U, // VFMSUB213PDZ128m + 1164970544U, // VFMSUB213PDZ128mb + 1433389616U, // VFMSUB213PDZ128mbk + 1433389616U, // VFMSUB213PDZ128mbkz + 86985264U, // VFMSUB213PDZ128mk + 89082416U, // VFMSUB213PDZ128mkz + 890276400U, // VFMSUB213PDZ128r + 87050800U, // VFMSUB213PDZ128rk + 89147952U, // VFMSUB213PDZ128rkz + 890309168U, // VFMSUB213PDZ256m + 1167067696U, // VFMSUB213PDZ256mb + 1435486768U, // VFMSUB213PDZ256mbk + 1435486768U, // VFMSUB213PDZ256mbkz + 87083568U, // VFMSUB213PDZ256mk + 89180720U, // VFMSUB213PDZ256mkz + 890276400U, // VFMSUB213PDZ256r + 87050800U, // VFMSUB213PDZ256rk + 89147952U, // VFMSUB213PDZ256rkz + 890358320U, // VFMSUB213PDZm + 1169164848U, // VFMSUB213PDZmb + 1437583920U, // VFMSUB213PDZmbk + 1437583920U, // VFMSUB213PDZmbkz + 87132720U, // VFMSUB213PDZmk + 89229872U, // VFMSUB213PDZmkz + 890276400U, // VFMSUB213PDZr + 890407472U, // VFMSUB213PDZrb + 87181872U, // VFMSUB213PDZrbk + 89279024U, // VFMSUB213PDZrbkz + 87050800U, // VFMSUB213PDZrk + 89147952U, // VFMSUB213PDZrkz + 890178096U, // VFMSUB213PDm + 890276400U, // VFMSUB213PDr + 890315573U, // VFMSUB213PSYm + 890282805U, // VFMSUB213PSYr + 890184501U, // VFMSUB213PSZ128m + 1167270709U, // VFMSUB213PSZ128mb + 1435689781U, // VFMSUB213PSZ128mbk + 1435689781U, // VFMSUB213PSZ128mbkz + 86991669U, // VFMSUB213PSZ128mk + 89088821U, // VFMSUB213PSZ128mkz + 890282805U, // VFMSUB213PSZ128r + 87057205U, // VFMSUB213PSZ128rk + 89154357U, // VFMSUB213PSZ128rkz + 890315573U, // VFMSUB213PSZ256m + 1169367861U, // VFMSUB213PSZ256mb + 1437786933U, // VFMSUB213PSZ256mbk + 1437786933U, // VFMSUB213PSZ256mbkz + 87089973U, // VFMSUB213PSZ256mk + 89187125U, // VFMSUB213PSZ256mkz + 890282805U, // VFMSUB213PSZ256r + 87057205U, // VFMSUB213PSZ256rk + 89154357U, // VFMSUB213PSZ256rkz + 890364725U, // VFMSUB213PSZm + 1171465013U, // VFMSUB213PSZmb + 1439884085U, // VFMSUB213PSZmbk + 1439884085U, // VFMSUB213PSZmbkz + 87139125U, // VFMSUB213PSZmk + 89236277U, // VFMSUB213PSZmkz + 890282805U, // VFMSUB213PSZr + 890413877U, // VFMSUB213PSZrb + 87188277U, // VFMSUB213PSZrbk + 89285429U, // VFMSUB213PSZrbkz + 87057205U, // VFMSUB213PSZrk + 89154357U, // VFMSUB213PSZrkz + 890184501U, // VFMSUB213PSm + 890282805U, // VFMSUB213PSr + 1089474147U, // VFMSUB213SDZm + 1089474147U, // VFMSUB213SDZm_Int + 1357893219U, // VFMSUB213SDZm_Intk + 1357893219U, // VFMSUB213SDZm_Intkz + 890277475U, // VFMSUB213SDZr + 890277475U, // VFMSUB213SDZr_Int + 87051875U, // VFMSUB213SDZr_Intk + 89149027U, // VFMSUB213SDZr_Intkz + 890277475U, // VFMSUB213SDZrb + 890408547U, // VFMSUB213SDZrb_Int + 87182947U, // VFMSUB213SDZrb_Intk + 89280099U, // VFMSUB213SDZrb_Intkz + 1089474147U, // VFMSUB213SDm + 1089474147U, // VFMSUB213SDm_Int + 890277475U, // VFMSUB213SDr + 890277475U, // VFMSUB213SDr_Int + 1089677158U, // VFMSUB213SSZm + 1089677158U, // VFMSUB213SSZm_Int + 1358096230U, // VFMSUB213SSZm_Intk + 1358096230U, // VFMSUB213SSZm_Intkz + 890283878U, // VFMSUB213SSZr + 890283878U, // VFMSUB213SSZr_Int + 87058278U, // VFMSUB213SSZr_Intk + 89155430U, // VFMSUB213SSZr_Intkz + 890283878U, // VFMSUB213SSZrb + 890414950U, // VFMSUB213SSZrb_Int + 87189350U, // VFMSUB213SSZrb_Intk + 89286502U, // VFMSUB213SSZrb_Intkz + 1089677158U, // VFMSUB213SSm + 1089677158U, // VFMSUB213SSm_Int + 890283878U, // VFMSUB213SSr + 890283878U, // VFMSUB213SSr_Int + 890308886U, // VFMSUB231PDYm + 890276118U, // VFMSUB231PDYr + 890177814U, // VFMSUB231PDZ128m + 1164970262U, // VFMSUB231PDZ128mb + 1433389334U, // VFMSUB231PDZ128mbk + 1433389334U, // VFMSUB231PDZ128mbkz + 86984982U, // VFMSUB231PDZ128mk + 89082134U, // VFMSUB231PDZ128mkz + 890276118U, // VFMSUB231PDZ128r + 87050518U, // VFMSUB231PDZ128rk + 89147670U, // VFMSUB231PDZ128rkz + 890308886U, // VFMSUB231PDZ256m + 1167067414U, // VFMSUB231PDZ256mb + 1435486486U, // VFMSUB231PDZ256mbk + 1435486486U, // VFMSUB231PDZ256mbkz + 87083286U, // VFMSUB231PDZ256mk + 89180438U, // VFMSUB231PDZ256mkz + 890276118U, // VFMSUB231PDZ256r + 87050518U, // VFMSUB231PDZ256rk + 89147670U, // VFMSUB231PDZ256rkz + 890358038U, // VFMSUB231PDZm + 1169164566U, // VFMSUB231PDZmb + 1437583638U, // VFMSUB231PDZmbk + 1437583638U, // VFMSUB231PDZmbkz + 87132438U, // VFMSUB231PDZmk + 89229590U, // VFMSUB231PDZmkz + 890276118U, // VFMSUB231PDZr + 890407190U, // VFMSUB231PDZrb + 87181590U, // VFMSUB231PDZrbk + 89278742U, // VFMSUB231PDZrbkz + 87050518U, // VFMSUB231PDZrk + 89147670U, // VFMSUB231PDZrkz + 890177814U, // VFMSUB231PDm + 890276118U, // VFMSUB231PDr + 890315280U, // VFMSUB231PSYm + 890282512U, // VFMSUB231PSYr + 890184208U, // VFMSUB231PSZ128m + 1167270416U, // VFMSUB231PSZ128mb + 1435689488U, // VFMSUB231PSZ128mbk + 1435689488U, // VFMSUB231PSZ128mbkz + 86991376U, // VFMSUB231PSZ128mk + 89088528U, // VFMSUB231PSZ128mkz + 890282512U, // VFMSUB231PSZ128r + 87056912U, // VFMSUB231PSZ128rk + 89154064U, // VFMSUB231PSZ128rkz + 890315280U, // VFMSUB231PSZ256m + 1169367568U, // VFMSUB231PSZ256mb + 1437786640U, // VFMSUB231PSZ256mbk + 1437786640U, // VFMSUB231PSZ256mbkz + 87089680U, // VFMSUB231PSZ256mk + 89186832U, // VFMSUB231PSZ256mkz + 890282512U, // VFMSUB231PSZ256r + 87056912U, // VFMSUB231PSZ256rk + 89154064U, // VFMSUB231PSZ256rkz + 890364432U, // VFMSUB231PSZm + 1171464720U, // VFMSUB231PSZmb + 1439883792U, // VFMSUB231PSZmbk + 1439883792U, // VFMSUB231PSZmbkz + 87138832U, // VFMSUB231PSZmk + 89235984U, // VFMSUB231PSZmkz + 890282512U, // VFMSUB231PSZr + 890413584U, // VFMSUB231PSZrb + 87187984U, // VFMSUB231PSZrbk + 89285136U, // VFMSUB231PSZrbkz + 87056912U, // VFMSUB231PSZrk + 89154064U, // VFMSUB231PSZrkz + 890184208U, // VFMSUB231PSm + 890282512U, // VFMSUB231PSr + 1089474028U, // VFMSUB231SDZm + 1089474028U, // VFMSUB231SDZm_Int + 1357893100U, // VFMSUB231SDZm_Intk + 1357893100U, // VFMSUB231SDZm_Intkz + 890277356U, // VFMSUB231SDZr + 890277356U, // VFMSUB231SDZr_Int + 87051756U, // VFMSUB231SDZr_Intk + 89148908U, // VFMSUB231SDZr_Intkz + 890277356U, // VFMSUB231SDZrb + 890408428U, // VFMSUB231SDZrb_Int + 87182828U, // VFMSUB231SDZrb_Intk + 89279980U, // VFMSUB231SDZrb_Intkz + 1089474028U, // VFMSUB231SDm + 1089474028U, // VFMSUB231SDm_Int + 890277356U, // VFMSUB231SDr + 890277356U, // VFMSUB231SDr_Int + 1089677039U, // VFMSUB231SSZm + 1089677039U, // VFMSUB231SSZm_Int + 1358096111U, // VFMSUB231SSZm_Intk + 1358096111U, // VFMSUB231SSZm_Intkz + 890283759U, // VFMSUB231SSZr + 890283759U, // VFMSUB231SSZr_Int + 87058159U, // VFMSUB231SSZr_Intk + 89155311U, // VFMSUB231SSZr_Intkz + 890283759U, // VFMSUB231SSZrb + 890414831U, // VFMSUB231SSZrb_Int + 87189231U, // VFMSUB231SSZrb_Intk + 89286383U, // VFMSUB231SSZrb_Intkz + 1089677039U, // VFMSUB231SSm + 1089677039U, // VFMSUB231SSm_Int + 890283759U, // VFMSUB231SSr + 890283759U, // VFMSUB231SSr_Int + 890308999U, // VFMSUBADD132PDYm + 890276231U, // VFMSUBADD132PDYr + 890177927U, // VFMSUBADD132PDZ128m + 1164970375U, // VFMSUBADD132PDZ128mb + 1433389447U, // VFMSUBADD132PDZ128mbk + 1433389447U, // VFMSUBADD132PDZ128mbkz + 86985095U, // VFMSUBADD132PDZ128mk + 89082247U, // VFMSUBADD132PDZ128mkz + 890276231U, // VFMSUBADD132PDZ128r + 87050631U, // VFMSUBADD132PDZ128rk + 89147783U, // VFMSUBADD132PDZ128rkz + 890308999U, // VFMSUBADD132PDZ256m + 1167067527U, // VFMSUBADD132PDZ256mb + 1435486599U, // VFMSUBADD132PDZ256mbk + 1435486599U, // VFMSUBADD132PDZ256mbkz + 87083399U, // VFMSUBADD132PDZ256mk + 89180551U, // VFMSUBADD132PDZ256mkz + 890276231U, // VFMSUBADD132PDZ256r + 87050631U, // VFMSUBADD132PDZ256rk + 89147783U, // VFMSUBADD132PDZ256rkz + 890358151U, // VFMSUBADD132PDZm + 1169164679U, // VFMSUBADD132PDZmb + 1437583751U, // VFMSUBADD132PDZmbk + 1437583751U, // VFMSUBADD132PDZmbkz + 87132551U, // VFMSUBADD132PDZmk + 89229703U, // VFMSUBADD132PDZmkz + 890276231U, // VFMSUBADD132PDZr + 890407303U, // VFMSUBADD132PDZrb + 87181703U, // VFMSUBADD132PDZrbk + 89278855U, // VFMSUBADD132PDZrbkz + 87050631U, // VFMSUBADD132PDZrk + 89147783U, // VFMSUBADD132PDZrkz + 890177927U, // VFMSUBADD132PDm + 890276231U, // VFMSUBADD132PDr + 890315393U, // VFMSUBADD132PSYm + 890282625U, // VFMSUBADD132PSYr + 890184321U, // VFMSUBADD132PSZ128m + 1167270529U, // VFMSUBADD132PSZ128mb + 1435689601U, // VFMSUBADD132PSZ128mbk + 1435689601U, // VFMSUBADD132PSZ128mbkz + 86991489U, // VFMSUBADD132PSZ128mk + 89088641U, // VFMSUBADD132PSZ128mkz + 890282625U, // VFMSUBADD132PSZ128r + 87057025U, // VFMSUBADD132PSZ128rk + 89154177U, // VFMSUBADD132PSZ128rkz + 890315393U, // VFMSUBADD132PSZ256m + 1169367681U, // VFMSUBADD132PSZ256mb + 1437786753U, // VFMSUBADD132PSZ256mbk + 1437786753U, // VFMSUBADD132PSZ256mbkz + 87089793U, // VFMSUBADD132PSZ256mk + 89186945U, // VFMSUBADD132PSZ256mkz + 890282625U, // VFMSUBADD132PSZ256r + 87057025U, // VFMSUBADD132PSZ256rk + 89154177U, // VFMSUBADD132PSZ256rkz + 890364545U, // VFMSUBADD132PSZm + 1171464833U, // VFMSUBADD132PSZmb + 1439883905U, // VFMSUBADD132PSZmbk + 1439883905U, // VFMSUBADD132PSZmbkz + 87138945U, // VFMSUBADD132PSZmk + 89236097U, // VFMSUBADD132PSZmkz + 890282625U, // VFMSUBADD132PSZr + 890413697U, // VFMSUBADD132PSZrb + 87188097U, // VFMSUBADD132PSZrbk + 89285249U, // VFMSUBADD132PSZrbkz + 87057025U, // VFMSUBADD132PSZrk + 89154177U, // VFMSUBADD132PSZrkz + 890184321U, // VFMSUBADD132PSm + 890282625U, // VFMSUBADD132PSr + 890309195U, // VFMSUBADD213PDYm + 890276427U, // VFMSUBADD213PDYr + 890178123U, // VFMSUBADD213PDZ128m + 1164970571U, // VFMSUBADD213PDZ128mb + 1433389643U, // VFMSUBADD213PDZ128mbk + 1433389643U, // VFMSUBADD213PDZ128mbkz + 86985291U, // VFMSUBADD213PDZ128mk + 89082443U, // VFMSUBADD213PDZ128mkz + 890276427U, // VFMSUBADD213PDZ128r + 87050827U, // VFMSUBADD213PDZ128rk + 89147979U, // VFMSUBADD213PDZ128rkz + 890309195U, // VFMSUBADD213PDZ256m + 1167067723U, // VFMSUBADD213PDZ256mb + 1435486795U, // VFMSUBADD213PDZ256mbk + 1435486795U, // VFMSUBADD213PDZ256mbkz + 87083595U, // VFMSUBADD213PDZ256mk + 89180747U, // VFMSUBADD213PDZ256mkz + 890276427U, // VFMSUBADD213PDZ256r + 87050827U, // VFMSUBADD213PDZ256rk + 89147979U, // VFMSUBADD213PDZ256rkz + 890358347U, // VFMSUBADD213PDZm + 1169164875U, // VFMSUBADD213PDZmb + 1437583947U, // VFMSUBADD213PDZmbk + 1437583947U, // VFMSUBADD213PDZmbkz + 87132747U, // VFMSUBADD213PDZmk + 89229899U, // VFMSUBADD213PDZmkz + 890276427U, // VFMSUBADD213PDZr + 890407499U, // VFMSUBADD213PDZrb + 87181899U, // VFMSUBADD213PDZrbk + 89279051U, // VFMSUBADD213PDZrbkz + 87050827U, // VFMSUBADD213PDZrk + 89147979U, // VFMSUBADD213PDZrkz + 890178123U, // VFMSUBADD213PDm + 890276427U, // VFMSUBADD213PDr + 890315600U, // VFMSUBADD213PSYm + 890282832U, // VFMSUBADD213PSYr + 890184528U, // VFMSUBADD213PSZ128m + 1167270736U, // VFMSUBADD213PSZ128mb + 1435689808U, // VFMSUBADD213PSZ128mbk + 1435689808U, // VFMSUBADD213PSZ128mbkz + 86991696U, // VFMSUBADD213PSZ128mk + 89088848U, // VFMSUBADD213PSZ128mkz + 890282832U, // VFMSUBADD213PSZ128r + 87057232U, // VFMSUBADD213PSZ128rk + 89154384U, // VFMSUBADD213PSZ128rkz + 890315600U, // VFMSUBADD213PSZ256m + 1169367888U, // VFMSUBADD213PSZ256mb + 1437786960U, // VFMSUBADD213PSZ256mbk + 1437786960U, // VFMSUBADD213PSZ256mbkz + 87090000U, // VFMSUBADD213PSZ256mk + 89187152U, // VFMSUBADD213PSZ256mkz + 890282832U, // VFMSUBADD213PSZ256r + 87057232U, // VFMSUBADD213PSZ256rk + 89154384U, // VFMSUBADD213PSZ256rkz + 890364752U, // VFMSUBADD213PSZm + 1171465040U, // VFMSUBADD213PSZmb + 1439884112U, // VFMSUBADD213PSZmbk + 1439884112U, // VFMSUBADD213PSZmbkz + 87139152U, // VFMSUBADD213PSZmk + 89236304U, // VFMSUBADD213PSZmkz + 890282832U, // VFMSUBADD213PSZr + 890413904U, // VFMSUBADD213PSZrb + 87188304U, // VFMSUBADD213PSZrbk + 89285456U, // VFMSUBADD213PSZrbkz + 87057232U, // VFMSUBADD213PSZrk + 89154384U, // VFMSUBADD213PSZrkz + 890184528U, // VFMSUBADD213PSm + 890282832U, // VFMSUBADD213PSr + 890308913U, // VFMSUBADD231PDYm + 890276145U, // VFMSUBADD231PDYr + 890177841U, // VFMSUBADD231PDZ128m + 1164970289U, // VFMSUBADD231PDZ128mb + 1433389361U, // VFMSUBADD231PDZ128mbk + 1433389361U, // VFMSUBADD231PDZ128mbkz + 86985009U, // VFMSUBADD231PDZ128mk + 89082161U, // VFMSUBADD231PDZ128mkz + 890276145U, // VFMSUBADD231PDZ128r + 87050545U, // VFMSUBADD231PDZ128rk + 89147697U, // VFMSUBADD231PDZ128rkz + 890308913U, // VFMSUBADD231PDZ256m + 1167067441U, // VFMSUBADD231PDZ256mb + 1435486513U, // VFMSUBADD231PDZ256mbk + 1435486513U, // VFMSUBADD231PDZ256mbkz + 87083313U, // VFMSUBADD231PDZ256mk + 89180465U, // VFMSUBADD231PDZ256mkz + 890276145U, // VFMSUBADD231PDZ256r + 87050545U, // VFMSUBADD231PDZ256rk + 89147697U, // VFMSUBADD231PDZ256rkz + 890358065U, // VFMSUBADD231PDZm + 1169164593U, // VFMSUBADD231PDZmb + 1437583665U, // VFMSUBADD231PDZmbk + 1437583665U, // VFMSUBADD231PDZmbkz + 87132465U, // VFMSUBADD231PDZmk + 89229617U, // VFMSUBADD231PDZmkz + 890276145U, // VFMSUBADD231PDZr + 890407217U, // VFMSUBADD231PDZrb + 87181617U, // VFMSUBADD231PDZrbk + 89278769U, // VFMSUBADD231PDZrbkz + 87050545U, // VFMSUBADD231PDZrk + 89147697U, // VFMSUBADD231PDZrkz + 890177841U, // VFMSUBADD231PDm + 890276145U, // VFMSUBADD231PDr + 890315307U, // VFMSUBADD231PSYm + 890282539U, // VFMSUBADD231PSYr + 890184235U, // VFMSUBADD231PSZ128m + 1167270443U, // VFMSUBADD231PSZ128mb + 1435689515U, // VFMSUBADD231PSZ128mbk + 1435689515U, // VFMSUBADD231PSZ128mbkz + 86991403U, // VFMSUBADD231PSZ128mk + 89088555U, // VFMSUBADD231PSZ128mkz + 890282539U, // VFMSUBADD231PSZ128r + 87056939U, // VFMSUBADD231PSZ128rk + 89154091U, // VFMSUBADD231PSZ128rkz + 890315307U, // VFMSUBADD231PSZ256m + 1169367595U, // VFMSUBADD231PSZ256mb + 1437786667U, // VFMSUBADD231PSZ256mbk + 1437786667U, // VFMSUBADD231PSZ256mbkz + 87089707U, // VFMSUBADD231PSZ256mk + 89186859U, // VFMSUBADD231PSZ256mkz + 890282539U, // VFMSUBADD231PSZ256r + 87056939U, // VFMSUBADD231PSZ256rk + 89154091U, // VFMSUBADD231PSZ256rkz + 890364459U, // VFMSUBADD231PSZm + 1171464747U, // VFMSUBADD231PSZmb + 1439883819U, // VFMSUBADD231PSZmbk + 1439883819U, // VFMSUBADD231PSZmbkz + 87138859U, // VFMSUBADD231PSZmk + 89236011U, // VFMSUBADD231PSZmkz + 890282539U, // VFMSUBADD231PSZr + 890413611U, // VFMSUBADD231PSZrb + 87188011U, // VFMSUBADD231PSZrbk + 89285163U, // VFMSUBADD231PSZrbkz + 87056939U, // VFMSUBADD231PSZrk + 89154091U, // VFMSUBADD231PSZrkz + 890184235U, // VFMSUBADD231PSm + 890282539U, // VFMSUBADD231PSr + 393497391U, // VFMSUBADDPD4Ymr + 890309423U, // VFMSUBADDPD4Yrm + 890276655U, // VFMSUBADDPD4Yrr + 890276655U, // VFMSUBADDPD4Yrr_REV + 301222703U, // VFMSUBADDPD4mr + 890178351U, // VFMSUBADDPD4rm + 890276655U, // VFMSUBADDPD4rr + 890276655U, // VFMSUBADDPD4rr_REV + 393503788U, // VFMSUBADDPS4Ymr + 890315820U, // VFMSUBADDPS4Yrm + 890283052U, // VFMSUBADDPS4Yrr + 890283052U, // VFMSUBADDPS4Yrr_REV + 301229100U, // VFMSUBADDPS4mr + 890184748U, // VFMSUBADDPS4rm + 890283052U, // VFMSUBADDPS4rr + 890283052U, // VFMSUBADDPS4rr_REV + 393497300U, // VFMSUBPD4Ymr + 890309332U, // VFMSUBPD4Yrm + 890276564U, // VFMSUBPD4Yrr + 890276564U, // VFMSUBPD4Yrr_REV + 301222612U, // VFMSUBPD4mr + 890178260U, // VFMSUBPD4rm + 890276564U, // VFMSUBPD4rr + 890276564U, // VFMSUBPD4rr_REV + 393503697U, // VFMSUBPS4Ymr + 890315729U, // VFMSUBPS4Yrm + 890282961U, // VFMSUBPS4Yrr + 890282961U, // VFMSUBPS4Yrr_REV + 301229009U, // VFMSUBPS4mr + 890184657U, // VFMSUBPS4rm + 890282961U, // VFMSUBPS4rr + 890282961U, // VFMSUBPS4rr_REV + 852774605U, // VFMSUBSD4mr + 852774605U, // VFMSUBSD4mr_Int + 1089474253U, // VFMSUBSD4rm + 1089474253U, // VFMSUBSD4rm_Int + 890277581U, // VFMSUBSD4rr + 890277581U, // VFMSUBSD4rr_Int + 890277581U, // VFMSUBSD4rr_Int_REV + 890277581U, // VFMSUBSD4rr_REV + 856975304U, // VFMSUBSS4mr + 856975304U, // VFMSUBSS4mr_Int + 1089677256U, // VFMSUBSS4rm + 1089677256U, // VFMSUBSS4rm_Int + 890283976U, // VFMSUBSS4rr + 890283976U, // VFMSUBSS4rr_Int + 890283976U, // VFMSUBSS4rr_Int_REV + 890283976U, // VFMSUBSS4rr_REV + 890309028U, // VFNMADD132PDYm + 890276260U, // VFNMADD132PDYr + 890177956U, // VFNMADD132PDZ128m + 1164970404U, // VFNMADD132PDZ128mb + 1433389476U, // VFNMADD132PDZ128mbk + 1433389476U, // VFNMADD132PDZ128mbkz + 86985124U, // VFNMADD132PDZ128mk + 89082276U, // VFNMADD132PDZ128mkz + 890276260U, // VFNMADD132PDZ128r + 87050660U, // VFNMADD132PDZ128rk + 89147812U, // VFNMADD132PDZ128rkz + 890309028U, // VFNMADD132PDZ256m + 1167067556U, // VFNMADD132PDZ256mb + 1435486628U, // VFNMADD132PDZ256mbk + 1435486628U, // VFNMADD132PDZ256mbkz + 87083428U, // VFNMADD132PDZ256mk + 89180580U, // VFNMADD132PDZ256mkz + 890276260U, // VFNMADD132PDZ256r + 87050660U, // VFNMADD132PDZ256rk + 89147812U, // VFNMADD132PDZ256rkz + 890358180U, // VFNMADD132PDZm + 1169164708U, // VFNMADD132PDZmb + 1437583780U, // VFNMADD132PDZmbk + 1437583780U, // VFNMADD132PDZmbkz + 87132580U, // VFNMADD132PDZmk + 89229732U, // VFNMADD132PDZmkz + 890276260U, // VFNMADD132PDZr + 890407332U, // VFNMADD132PDZrb + 87181732U, // VFNMADD132PDZrbk + 89278884U, // VFNMADD132PDZrbkz + 87050660U, // VFNMADD132PDZrk + 89147812U, // VFNMADD132PDZrkz + 890177956U, // VFNMADD132PDm + 890276260U, // VFNMADD132PDr + 890315422U, // VFNMADD132PSYm + 890282654U, // VFNMADD132PSYr + 890184350U, // VFNMADD132PSZ128m + 1167270558U, // VFNMADD132PSZ128mb + 1435689630U, // VFNMADD132PSZ128mbk + 1435689630U, // VFNMADD132PSZ128mbkz + 86991518U, // VFNMADD132PSZ128mk + 89088670U, // VFNMADD132PSZ128mkz + 890282654U, // VFNMADD132PSZ128r + 87057054U, // VFNMADD132PSZ128rk + 89154206U, // VFNMADD132PSZ128rkz + 890315422U, // VFNMADD132PSZ256m + 1169367710U, // VFNMADD132PSZ256mb + 1437786782U, // VFNMADD132PSZ256mbk + 1437786782U, // VFNMADD132PSZ256mbkz + 87089822U, // VFNMADD132PSZ256mk + 89186974U, // VFNMADD132PSZ256mkz + 890282654U, // VFNMADD132PSZ256r + 87057054U, // VFNMADD132PSZ256rk + 89154206U, // VFNMADD132PSZ256rkz + 890364574U, // VFNMADD132PSZm + 1171464862U, // VFNMADD132PSZmb + 1439883934U, // VFNMADD132PSZmbk + 1439883934U, // VFNMADD132PSZmbkz + 87138974U, // VFNMADD132PSZmk + 89236126U, // VFNMADD132PSZmkz + 890282654U, // VFNMADD132PSZr + 890413726U, // VFNMADD132PSZrb + 87188126U, // VFNMADD132PSZrbk + 89285278U, // VFNMADD132PSZrbkz + 87057054U, // VFNMADD132PSZrk + 89154206U, // VFNMADD132PSZrkz + 890184350U, // VFNMADD132PSm + 890282654U, // VFNMADD132PSr + 1089474122U, // VFNMADD132SDZm + 1089474122U, // VFNMADD132SDZm_Int + 1357893194U, // VFNMADD132SDZm_Intk + 1357893194U, // VFNMADD132SDZm_Intkz + 890277450U, // VFNMADD132SDZr + 890277450U, // VFNMADD132SDZr_Int + 87051850U, // VFNMADD132SDZr_Intk + 89149002U, // VFNMADD132SDZr_Intkz + 890277450U, // VFNMADD132SDZrb + 890408522U, // VFNMADD132SDZrb_Int + 87182922U, // VFNMADD132SDZrb_Intk + 89280074U, // VFNMADD132SDZrb_Intkz + 1089474122U, // VFNMADD132SDm + 1089474122U, // VFNMADD132SDm_Int + 890277450U, // VFNMADD132SDr + 890277450U, // VFNMADD132SDr_Int + 1089677133U, // VFNMADD132SSZm + 1089677133U, // VFNMADD132SSZm_Int + 1358096205U, // VFNMADD132SSZm_Intk + 1358096205U, // VFNMADD132SSZm_Intkz + 890283853U, // VFNMADD132SSZr + 890283853U, // VFNMADD132SSZr_Int + 87058253U, // VFNMADD132SSZr_Intk + 89155405U, // VFNMADD132SSZr_Intkz + 890283853U, // VFNMADD132SSZrb + 890414925U, // VFNMADD132SSZrb_Int + 87189325U, // VFNMADD132SSZrb_Intk + 89286477U, // VFNMADD132SSZrb_Intkz + 1089677133U, // VFNMADD132SSm + 1089677133U, // VFNMADD132SSm_Int + 890283853U, // VFNMADD132SSr + 890283853U, // VFNMADD132SSr_Int + 890309224U, // VFNMADD213PDYm + 890276456U, // VFNMADD213PDYr + 890178152U, // VFNMADD213PDZ128m + 1164970600U, // VFNMADD213PDZ128mb + 1433389672U, // VFNMADD213PDZ128mbk + 1433389672U, // VFNMADD213PDZ128mbkz + 86985320U, // VFNMADD213PDZ128mk + 89082472U, // VFNMADD213PDZ128mkz + 890276456U, // VFNMADD213PDZ128r + 87050856U, // VFNMADD213PDZ128rk + 89148008U, // VFNMADD213PDZ128rkz + 890309224U, // VFNMADD213PDZ256m + 1167067752U, // VFNMADD213PDZ256mb + 1435486824U, // VFNMADD213PDZ256mbk + 1435486824U, // VFNMADD213PDZ256mbkz + 87083624U, // VFNMADD213PDZ256mk + 89180776U, // VFNMADD213PDZ256mkz + 890276456U, // VFNMADD213PDZ256r + 87050856U, // VFNMADD213PDZ256rk + 89148008U, // VFNMADD213PDZ256rkz + 890358376U, // VFNMADD213PDZm + 1169164904U, // VFNMADD213PDZmb + 1437583976U, // VFNMADD213PDZmbk + 1437583976U, // VFNMADD213PDZmbkz + 87132776U, // VFNMADD213PDZmk + 89229928U, // VFNMADD213PDZmkz + 890276456U, // VFNMADD213PDZr + 890407528U, // VFNMADD213PDZrb + 87181928U, // VFNMADD213PDZrbk + 89279080U, // VFNMADD213PDZrbkz + 87050856U, // VFNMADD213PDZrk + 89148008U, // VFNMADD213PDZrkz + 890178152U, // VFNMADD213PDm + 890276456U, // VFNMADD213PDr + 890315629U, // VFNMADD213PSYm + 890282861U, // VFNMADD213PSYr + 890184557U, // VFNMADD213PSZ128m + 1167270765U, // VFNMADD213PSZ128mb + 1435689837U, // VFNMADD213PSZ128mbk + 1435689837U, // VFNMADD213PSZ128mbkz + 86991725U, // VFNMADD213PSZ128mk + 89088877U, // VFNMADD213PSZ128mkz + 890282861U, // VFNMADD213PSZ128r + 87057261U, // VFNMADD213PSZ128rk + 89154413U, // VFNMADD213PSZ128rkz + 890315629U, // VFNMADD213PSZ256m + 1169367917U, // VFNMADD213PSZ256mb + 1437786989U, // VFNMADD213PSZ256mbk + 1437786989U, // VFNMADD213PSZ256mbkz + 87090029U, // VFNMADD213PSZ256mk + 89187181U, // VFNMADD213PSZ256mkz + 890282861U, // VFNMADD213PSZ256r + 87057261U, // VFNMADD213PSZ256rk + 89154413U, // VFNMADD213PSZ256rkz + 890364781U, // VFNMADD213PSZm + 1171465069U, // VFNMADD213PSZmb + 1439884141U, // VFNMADD213PSZmbk + 1439884141U, // VFNMADD213PSZmbkz + 87139181U, // VFNMADD213PSZmk + 89236333U, // VFNMADD213PSZmkz + 890282861U, // VFNMADD213PSZr + 890413933U, // VFNMADD213PSZrb + 87188333U, // VFNMADD213PSZrbk + 89285485U, // VFNMADD213PSZrbkz + 87057261U, // VFNMADD213PSZrk + 89154413U, // VFNMADD213PSZrkz + 890184557U, // VFNMADD213PSm + 890282861U, // VFNMADD213PSr + 1089474187U, // VFNMADD213SDZm + 1089474187U, // VFNMADD213SDZm_Int + 1357893259U, // VFNMADD213SDZm_Intk + 1357893259U, // VFNMADD213SDZm_Intkz + 890277515U, // VFNMADD213SDZr + 890277515U, // VFNMADD213SDZr_Int + 87051915U, // VFNMADD213SDZr_Intk + 89149067U, // VFNMADD213SDZr_Intkz + 890277515U, // VFNMADD213SDZrb + 890408587U, // VFNMADD213SDZrb_Int + 87182987U, // VFNMADD213SDZrb_Intk + 89280139U, // VFNMADD213SDZrb_Intkz + 1089474187U, // VFNMADD213SDm + 1089474187U, // VFNMADD213SDm_Int + 890277515U, // VFNMADD213SDr + 890277515U, // VFNMADD213SDr_Int + 1089677198U, // VFNMADD213SSZm + 1089677198U, // VFNMADD213SSZm_Int + 1358096270U, // VFNMADD213SSZm_Intk + 1358096270U, // VFNMADD213SSZm_Intkz + 890283918U, // VFNMADD213SSZr + 890283918U, // VFNMADD213SSZr_Int + 87058318U, // VFNMADD213SSZr_Intk + 89155470U, // VFNMADD213SSZr_Intkz + 890283918U, // VFNMADD213SSZrb + 890414990U, // VFNMADD213SSZrb_Int + 87189390U, // VFNMADD213SSZrb_Intk + 89286542U, // VFNMADD213SSZrb_Intkz + 1089677198U, // VFNMADD213SSm + 1089677198U, // VFNMADD213SSm_Int + 890283918U, // VFNMADD213SSr + 890283918U, // VFNMADD213SSr_Int + 890308942U, // VFNMADD231PDYm + 890276174U, // VFNMADD231PDYr + 890177870U, // VFNMADD231PDZ128m + 1164970318U, // VFNMADD231PDZ128mb + 1433389390U, // VFNMADD231PDZ128mbk + 1433389390U, // VFNMADD231PDZ128mbkz + 86985038U, // VFNMADD231PDZ128mk + 89082190U, // VFNMADD231PDZ128mkz + 890276174U, // VFNMADD231PDZ128r + 87050574U, // VFNMADD231PDZ128rk + 89147726U, // VFNMADD231PDZ128rkz + 890308942U, // VFNMADD231PDZ256m + 1167067470U, // VFNMADD231PDZ256mb + 1435486542U, // VFNMADD231PDZ256mbk + 1435486542U, // VFNMADD231PDZ256mbkz + 87083342U, // VFNMADD231PDZ256mk + 89180494U, // VFNMADD231PDZ256mkz + 890276174U, // VFNMADD231PDZ256r + 87050574U, // VFNMADD231PDZ256rk + 89147726U, // VFNMADD231PDZ256rkz + 890358094U, // VFNMADD231PDZm + 1169164622U, // VFNMADD231PDZmb + 1437583694U, // VFNMADD231PDZmbk + 1437583694U, // VFNMADD231PDZmbkz + 87132494U, // VFNMADD231PDZmk + 89229646U, // VFNMADD231PDZmkz + 890276174U, // VFNMADD231PDZr + 890407246U, // VFNMADD231PDZrb + 87181646U, // VFNMADD231PDZrbk + 89278798U, // VFNMADD231PDZrbkz + 87050574U, // VFNMADD231PDZrk + 89147726U, // VFNMADD231PDZrkz + 890177870U, // VFNMADD231PDm + 890276174U, // VFNMADD231PDr + 890315336U, // VFNMADD231PSYm + 890282568U, // VFNMADD231PSYr + 890184264U, // VFNMADD231PSZ128m + 1167270472U, // VFNMADD231PSZ128mb + 1435689544U, // VFNMADD231PSZ128mbk + 1435689544U, // VFNMADD231PSZ128mbkz + 86991432U, // VFNMADD231PSZ128mk + 89088584U, // VFNMADD231PSZ128mkz + 890282568U, // VFNMADD231PSZ128r + 87056968U, // VFNMADD231PSZ128rk + 89154120U, // VFNMADD231PSZ128rkz + 890315336U, // VFNMADD231PSZ256m + 1169367624U, // VFNMADD231PSZ256mb + 1437786696U, // VFNMADD231PSZ256mbk + 1437786696U, // VFNMADD231PSZ256mbkz + 87089736U, // VFNMADD231PSZ256mk + 89186888U, // VFNMADD231PSZ256mkz + 890282568U, // VFNMADD231PSZ256r + 87056968U, // VFNMADD231PSZ256rk + 89154120U, // VFNMADD231PSZ256rkz + 890364488U, // VFNMADD231PSZm + 1171464776U, // VFNMADD231PSZmb + 1439883848U, // VFNMADD231PSZmbk + 1439883848U, // VFNMADD231PSZmbkz + 87138888U, // VFNMADD231PSZmk + 89236040U, // VFNMADD231PSZmkz + 890282568U, // VFNMADD231PSZr + 890413640U, // VFNMADD231PSZrb + 87188040U, // VFNMADD231PSZrbk + 89285192U, // VFNMADD231PSZrbkz + 87056968U, // VFNMADD231PSZrk + 89154120U, // VFNMADD231PSZrkz + 890184264U, // VFNMADD231PSm + 890282568U, // VFNMADD231PSr + 1089474068U, // VFNMADD231SDZm + 1089474068U, // VFNMADD231SDZm_Int + 1357893140U, // VFNMADD231SDZm_Intk + 1357893140U, // VFNMADD231SDZm_Intkz + 890277396U, // VFNMADD231SDZr + 890277396U, // VFNMADD231SDZr_Int + 87051796U, // VFNMADD231SDZr_Intk + 89148948U, // VFNMADD231SDZr_Intkz + 890277396U, // VFNMADD231SDZrb + 890408468U, // VFNMADD231SDZrb_Int + 87182868U, // VFNMADD231SDZrb_Intk + 89280020U, // VFNMADD231SDZrb_Intkz + 1089474068U, // VFNMADD231SDm + 1089474068U, // VFNMADD231SDm_Int + 890277396U, // VFNMADD231SDr + 890277396U, // VFNMADD231SDr_Int + 1089677079U, // VFNMADD231SSZm + 1089677079U, // VFNMADD231SSZm_Int + 1358096151U, // VFNMADD231SSZm_Intk + 1358096151U, // VFNMADD231SSZm_Intkz + 890283799U, // VFNMADD231SSZr + 890283799U, // VFNMADD231SSZr_Int + 87058199U, // VFNMADD231SSZr_Intk + 89155351U, // VFNMADD231SSZr_Intkz + 890283799U, // VFNMADD231SSZrb + 890414871U, // VFNMADD231SSZrb_Int + 87189271U, // VFNMADD231SSZrb_Intk + 89286423U, // VFNMADD231SSZrb_Intkz + 1089677079U, // VFNMADD231SSm + 1089677079U, // VFNMADD231SSm_Int + 890283799U, // VFNMADD231SSr + 890283799U, // VFNMADD231SSr_Int + 393497423U, // VFNMADDPD4Ymr + 890309455U, // VFNMADDPD4Yrm + 890276687U, // VFNMADDPD4Yrr + 890276687U, // VFNMADDPD4Yrr_REV + 301222735U, // VFNMADDPD4mr + 890178383U, // VFNMADDPD4rm + 890276687U, // VFNMADDPD4rr + 890276687U, // VFNMADDPD4rr_REV + 393503843U, // VFNMADDPS4Ymr + 890315875U, // VFNMADDPS4Yrm + 890283107U, // VFNMADDPS4Yrr + 890283107U, // VFNMADDPS4Yrr_REV + 301229155U, // VFNMADDPS4mr + 890184803U, // VFNMADDPS4rm + 890283107U, // VFNMADDPS4rr + 890283107U, // VFNMADDPS4rr_REV + 852774644U, // VFNMADDSD4mr + 852774644U, // VFNMADDSD4mr_Int + 1089474292U, // VFNMADDSD4rm + 1089474292U, // VFNMADDSD4rm_Int + 890277620U, // VFNMADDSD4rr + 890277620U, // VFNMADDSD4rr_Int + 890277620U, // VFNMADDSD4rr_Int_REV + 890277620U, // VFNMADDSD4rr_REV + 856975366U, // VFNMADDSS4mr + 856975366U, // VFNMADDSS4mr_Int + 1089677318U, // VFNMADDSS4rm + 1089677318U, // VFNMADDSS4rm_Int + 890284038U, // VFNMADDSS4rr + 890284038U, // VFNMADDSS4rr_Int + 890284038U, // VFNMADDSS4rr_Int_REV + 890284038U, // VFNMADDSS4rr_REV + 890308985U, // VFNMSUB132PDYm + 890276217U, // VFNMSUB132PDYr + 890177913U, // VFNMSUB132PDZ128m + 1164970361U, // VFNMSUB132PDZ128mb + 1433389433U, // VFNMSUB132PDZ128mbk + 1433389433U, // VFNMSUB132PDZ128mbkz + 86985081U, // VFNMSUB132PDZ128mk + 89082233U, // VFNMSUB132PDZ128mkz + 890276217U, // VFNMSUB132PDZ128r + 87050617U, // VFNMSUB132PDZ128rk + 89147769U, // VFNMSUB132PDZ128rkz + 890308985U, // VFNMSUB132PDZ256m + 1167067513U, // VFNMSUB132PDZ256mb + 1435486585U, // VFNMSUB132PDZ256mbk + 1435486585U, // VFNMSUB132PDZ256mbkz + 87083385U, // VFNMSUB132PDZ256mk + 89180537U, // VFNMSUB132PDZ256mkz + 890276217U, // VFNMSUB132PDZ256r + 87050617U, // VFNMSUB132PDZ256rk + 89147769U, // VFNMSUB132PDZ256rkz + 890358137U, // VFNMSUB132PDZm + 1169164665U, // VFNMSUB132PDZmb + 1437583737U, // VFNMSUB132PDZmbk + 1437583737U, // VFNMSUB132PDZmbkz + 87132537U, // VFNMSUB132PDZmk + 89229689U, // VFNMSUB132PDZmkz + 890276217U, // VFNMSUB132PDZr + 890407289U, // VFNMSUB132PDZrb + 87181689U, // VFNMSUB132PDZrbk + 89278841U, // VFNMSUB132PDZrbkz + 87050617U, // VFNMSUB132PDZrk + 89147769U, // VFNMSUB132PDZrkz + 890177913U, // VFNMSUB132PDm + 890276217U, // VFNMSUB132PDr + 890315379U, // VFNMSUB132PSYm + 890282611U, // VFNMSUB132PSYr + 890184307U, // VFNMSUB132PSZ128m + 1167270515U, // VFNMSUB132PSZ128mb + 1435689587U, // VFNMSUB132PSZ128mbk + 1435689587U, // VFNMSUB132PSZ128mbkz + 86991475U, // VFNMSUB132PSZ128mk + 89088627U, // VFNMSUB132PSZ128mkz + 890282611U, // VFNMSUB132PSZ128r + 87057011U, // VFNMSUB132PSZ128rk + 89154163U, // VFNMSUB132PSZ128rkz + 890315379U, // VFNMSUB132PSZ256m + 1169367667U, // VFNMSUB132PSZ256mb + 1437786739U, // VFNMSUB132PSZ256mbk + 1437786739U, // VFNMSUB132PSZ256mbkz + 87089779U, // VFNMSUB132PSZ256mk + 89186931U, // VFNMSUB132PSZ256mkz + 890282611U, // VFNMSUB132PSZ256r + 87057011U, // VFNMSUB132PSZ256rk + 89154163U, // VFNMSUB132PSZ256rkz + 890364531U, // VFNMSUB132PSZm + 1171464819U, // VFNMSUB132PSZmb + 1439883891U, // VFNMSUB132PSZmbk + 1439883891U, // VFNMSUB132PSZmbkz + 87138931U, // VFNMSUB132PSZmk + 89236083U, // VFNMSUB132PSZmkz + 890282611U, // VFNMSUB132PSZr + 890413683U, // VFNMSUB132PSZrb + 87188083U, // VFNMSUB132PSZrbk + 89285235U, // VFNMSUB132PSZrbkz + 87057011U, // VFNMSUB132PSZrk + 89154163U, // VFNMSUB132PSZrkz + 890184307U, // VFNMSUB132PSm + 890282611U, // VFNMSUB132PSr + 1089474095U, // VFNMSUB132SDZm + 1089474095U, // VFNMSUB132SDZm_Int + 1357893167U, // VFNMSUB132SDZm_Intk + 1357893167U, // VFNMSUB132SDZm_Intkz + 890277423U, // VFNMSUB132SDZr + 890277423U, // VFNMSUB132SDZr_Int + 87051823U, // VFNMSUB132SDZr_Intk + 89148975U, // VFNMSUB132SDZr_Intkz + 890277423U, // VFNMSUB132SDZrb + 890408495U, // VFNMSUB132SDZrb_Int + 87182895U, // VFNMSUB132SDZrb_Intk + 89280047U, // VFNMSUB132SDZrb_Intkz + 1089474095U, // VFNMSUB132SDm + 1089474095U, // VFNMSUB132SDm_Int + 890277423U, // VFNMSUB132SDr + 890277423U, // VFNMSUB132SDr_Int + 1089677106U, // VFNMSUB132SSZm + 1089677106U, // VFNMSUB132SSZm_Int + 1358096178U, // VFNMSUB132SSZm_Intk + 1358096178U, // VFNMSUB132SSZm_Intkz + 890283826U, // VFNMSUB132SSZr + 890283826U, // VFNMSUB132SSZr_Int + 87058226U, // VFNMSUB132SSZr_Intk + 89155378U, // VFNMSUB132SSZr_Intkz + 890283826U, // VFNMSUB132SSZrb + 890414898U, // VFNMSUB132SSZrb_Int + 87189298U, // VFNMSUB132SSZrb_Intk + 89286450U, // VFNMSUB132SSZrb_Intkz + 1089677106U, // VFNMSUB132SSm + 1089677106U, // VFNMSUB132SSm_Int + 890283826U, // VFNMSUB132SSr + 890283826U, // VFNMSUB132SSr_Int + 890309181U, // VFNMSUB213PDYm + 890276413U, // VFNMSUB213PDYr + 890178109U, // VFNMSUB213PDZ128m + 1164970557U, // VFNMSUB213PDZ128mb + 1433389629U, // VFNMSUB213PDZ128mbk + 1433389629U, // VFNMSUB213PDZ128mbkz + 86985277U, // VFNMSUB213PDZ128mk + 89082429U, // VFNMSUB213PDZ128mkz + 890276413U, // VFNMSUB213PDZ128r + 87050813U, // VFNMSUB213PDZ128rk + 89147965U, // VFNMSUB213PDZ128rkz + 890309181U, // VFNMSUB213PDZ256m + 1167067709U, // VFNMSUB213PDZ256mb + 1435486781U, // VFNMSUB213PDZ256mbk + 1435486781U, // VFNMSUB213PDZ256mbkz + 87083581U, // VFNMSUB213PDZ256mk + 89180733U, // VFNMSUB213PDZ256mkz + 890276413U, // VFNMSUB213PDZ256r + 87050813U, // VFNMSUB213PDZ256rk + 89147965U, // VFNMSUB213PDZ256rkz + 890358333U, // VFNMSUB213PDZm + 1169164861U, // VFNMSUB213PDZmb + 1437583933U, // VFNMSUB213PDZmbk + 1437583933U, // VFNMSUB213PDZmbkz + 87132733U, // VFNMSUB213PDZmk + 89229885U, // VFNMSUB213PDZmkz + 890276413U, // VFNMSUB213PDZr + 890407485U, // VFNMSUB213PDZrb + 87181885U, // VFNMSUB213PDZrbk + 89279037U, // VFNMSUB213PDZrbkz + 87050813U, // VFNMSUB213PDZrk + 89147965U, // VFNMSUB213PDZrkz + 890178109U, // VFNMSUB213PDm + 890276413U, // VFNMSUB213PDr + 890315586U, // VFNMSUB213PSYm + 890282818U, // VFNMSUB213PSYr + 890184514U, // VFNMSUB213PSZ128m + 1167270722U, // VFNMSUB213PSZ128mb + 1435689794U, // VFNMSUB213PSZ128mbk + 1435689794U, // VFNMSUB213PSZ128mbkz + 86991682U, // VFNMSUB213PSZ128mk + 89088834U, // VFNMSUB213PSZ128mkz + 890282818U, // VFNMSUB213PSZ128r + 87057218U, // VFNMSUB213PSZ128rk + 89154370U, // VFNMSUB213PSZ128rkz + 890315586U, // VFNMSUB213PSZ256m + 1169367874U, // VFNMSUB213PSZ256mb + 1437786946U, // VFNMSUB213PSZ256mbk + 1437786946U, // VFNMSUB213PSZ256mbkz + 87089986U, // VFNMSUB213PSZ256mk + 89187138U, // VFNMSUB213PSZ256mkz + 890282818U, // VFNMSUB213PSZ256r + 87057218U, // VFNMSUB213PSZ256rk + 89154370U, // VFNMSUB213PSZ256rkz + 890364738U, // VFNMSUB213PSZm + 1171465026U, // VFNMSUB213PSZmb + 1439884098U, // VFNMSUB213PSZmbk + 1439884098U, // VFNMSUB213PSZmbkz + 87139138U, // VFNMSUB213PSZmk + 89236290U, // VFNMSUB213PSZmkz + 890282818U, // VFNMSUB213PSZr + 890413890U, // VFNMSUB213PSZrb + 87188290U, // VFNMSUB213PSZrbk + 89285442U, // VFNMSUB213PSZrbkz + 87057218U, // VFNMSUB213PSZrk + 89154370U, // VFNMSUB213PSZrkz + 890184514U, // VFNMSUB213PSm + 890282818U, // VFNMSUB213PSr + 1089474160U, // VFNMSUB213SDZm + 1089474160U, // VFNMSUB213SDZm_Int + 1357893232U, // VFNMSUB213SDZm_Intk + 1357893232U, // VFNMSUB213SDZm_Intkz + 890277488U, // VFNMSUB213SDZr + 890277488U, // VFNMSUB213SDZr_Int + 87051888U, // VFNMSUB213SDZr_Intk + 89149040U, // VFNMSUB213SDZr_Intkz + 890277488U, // VFNMSUB213SDZrb + 890408560U, // VFNMSUB213SDZrb_Int + 87182960U, // VFNMSUB213SDZrb_Intk + 89280112U, // VFNMSUB213SDZrb_Intkz + 1089474160U, // VFNMSUB213SDm + 1089474160U, // VFNMSUB213SDm_Int + 890277488U, // VFNMSUB213SDr + 890277488U, // VFNMSUB213SDr_Int + 1089677171U, // VFNMSUB213SSZm + 1089677171U, // VFNMSUB213SSZm_Int + 1358096243U, // VFNMSUB213SSZm_Intk + 1358096243U, // VFNMSUB213SSZm_Intkz + 890283891U, // VFNMSUB213SSZr + 890283891U, // VFNMSUB213SSZr_Int + 87058291U, // VFNMSUB213SSZr_Intk + 89155443U, // VFNMSUB213SSZr_Intkz + 890283891U, // VFNMSUB213SSZrb + 890414963U, // VFNMSUB213SSZrb_Int + 87189363U, // VFNMSUB213SSZrb_Intk + 89286515U, // VFNMSUB213SSZrb_Intkz + 1089677171U, // VFNMSUB213SSm + 1089677171U, // VFNMSUB213SSm_Int + 890283891U, // VFNMSUB213SSr + 890283891U, // VFNMSUB213SSr_Int + 890308899U, // VFNMSUB231PDYm + 890276131U, // VFNMSUB231PDYr + 890177827U, // VFNMSUB231PDZ128m + 1164970275U, // VFNMSUB231PDZ128mb + 1433389347U, // VFNMSUB231PDZ128mbk + 1433389347U, // VFNMSUB231PDZ128mbkz + 86984995U, // VFNMSUB231PDZ128mk + 89082147U, // VFNMSUB231PDZ128mkz + 890276131U, // VFNMSUB231PDZ128r + 87050531U, // VFNMSUB231PDZ128rk + 89147683U, // VFNMSUB231PDZ128rkz + 890308899U, // VFNMSUB231PDZ256m + 1167067427U, // VFNMSUB231PDZ256mb + 1435486499U, // VFNMSUB231PDZ256mbk + 1435486499U, // VFNMSUB231PDZ256mbkz + 87083299U, // VFNMSUB231PDZ256mk + 89180451U, // VFNMSUB231PDZ256mkz + 890276131U, // VFNMSUB231PDZ256r + 87050531U, // VFNMSUB231PDZ256rk + 89147683U, // VFNMSUB231PDZ256rkz + 890358051U, // VFNMSUB231PDZm + 1169164579U, // VFNMSUB231PDZmb + 1437583651U, // VFNMSUB231PDZmbk + 1437583651U, // VFNMSUB231PDZmbkz + 87132451U, // VFNMSUB231PDZmk + 89229603U, // VFNMSUB231PDZmkz + 890276131U, // VFNMSUB231PDZr + 890407203U, // VFNMSUB231PDZrb + 87181603U, // VFNMSUB231PDZrbk + 89278755U, // VFNMSUB231PDZrbkz + 87050531U, // VFNMSUB231PDZrk + 89147683U, // VFNMSUB231PDZrkz + 890177827U, // VFNMSUB231PDm + 890276131U, // VFNMSUB231PDr + 890315293U, // VFNMSUB231PSYm + 890282525U, // VFNMSUB231PSYr + 890184221U, // VFNMSUB231PSZ128m + 1167270429U, // VFNMSUB231PSZ128mb + 1435689501U, // VFNMSUB231PSZ128mbk + 1435689501U, // VFNMSUB231PSZ128mbkz + 86991389U, // VFNMSUB231PSZ128mk + 89088541U, // VFNMSUB231PSZ128mkz + 890282525U, // VFNMSUB231PSZ128r + 87056925U, // VFNMSUB231PSZ128rk + 89154077U, // VFNMSUB231PSZ128rkz + 890315293U, // VFNMSUB231PSZ256m + 1169367581U, // VFNMSUB231PSZ256mb + 1437786653U, // VFNMSUB231PSZ256mbk + 1437786653U, // VFNMSUB231PSZ256mbkz + 87089693U, // VFNMSUB231PSZ256mk + 89186845U, // VFNMSUB231PSZ256mkz + 890282525U, // VFNMSUB231PSZ256r + 87056925U, // VFNMSUB231PSZ256rk + 89154077U, // VFNMSUB231PSZ256rkz + 890364445U, // VFNMSUB231PSZm + 1171464733U, // VFNMSUB231PSZmb + 1439883805U, // VFNMSUB231PSZmbk + 1439883805U, // VFNMSUB231PSZmbkz + 87138845U, // VFNMSUB231PSZmk + 89235997U, // VFNMSUB231PSZmkz + 890282525U, // VFNMSUB231PSZr + 890413597U, // VFNMSUB231PSZrb + 87187997U, // VFNMSUB231PSZrbk + 89285149U, // VFNMSUB231PSZrbkz + 87056925U, // VFNMSUB231PSZrk + 89154077U, // VFNMSUB231PSZrkz + 890184221U, // VFNMSUB231PSm + 890282525U, // VFNMSUB231PSr + 1089474041U, // VFNMSUB231SDZm + 1089474041U, // VFNMSUB231SDZm_Int + 1357893113U, // VFNMSUB231SDZm_Intk + 1357893113U, // VFNMSUB231SDZm_Intkz + 890277369U, // VFNMSUB231SDZr + 890277369U, // VFNMSUB231SDZr_Int + 87051769U, // VFNMSUB231SDZr_Intk + 89148921U, // VFNMSUB231SDZr_Intkz + 890277369U, // VFNMSUB231SDZrb + 890408441U, // VFNMSUB231SDZrb_Int + 87182841U, // VFNMSUB231SDZrb_Intk + 89279993U, // VFNMSUB231SDZrb_Intkz + 1089474041U, // VFNMSUB231SDm + 1089474041U, // VFNMSUB231SDm_Int + 890277369U, // VFNMSUB231SDr + 890277369U, // VFNMSUB231SDr_Int + 1089677052U, // VFNMSUB231SSZm + 1089677052U, // VFNMSUB231SSZm_Int + 1358096124U, // VFNMSUB231SSZm_Intk + 1358096124U, // VFNMSUB231SSZm_Intkz + 890283772U, // VFNMSUB231SSZr + 890283772U, // VFNMSUB231SSZr_Int + 87058172U, // VFNMSUB231SSZr_Intk + 89155324U, // VFNMSUB231SSZr_Intkz + 890283772U, // VFNMSUB231SSZrb + 890414844U, // VFNMSUB231SSZrb_Int + 87189244U, // VFNMSUB231SSZrb_Intk + 89286396U, // VFNMSUB231SSZrb_Intkz + 1089677052U, // VFNMSUB231SSm + 1089677052U, // VFNMSUB231SSm_Int + 890283772U, // VFNMSUB231SSr + 890283772U, // VFNMSUB231SSr_Int + 393497310U, // VFNMSUBPD4Ymr + 890309342U, // VFNMSUBPD4Yrm + 890276574U, // VFNMSUBPD4Yrr + 890276574U, // VFNMSUBPD4Yrr_REV + 301222622U, // VFNMSUBPD4mr + 890178270U, // VFNMSUBPD4rm + 890276574U, // VFNMSUBPD4rr + 890276574U, // VFNMSUBPD4rr_REV + 393503707U, // VFNMSUBPS4Ymr + 890315739U, // VFNMSUBPS4Yrm + 890282971U, // VFNMSUBPS4Yrr + 890282971U, // VFNMSUBPS4Yrr_REV + 301229019U, // VFNMSUBPS4mr + 890184667U, // VFNMSUBPS4rm + 890282971U, // VFNMSUBPS4rr + 890282971U, // VFNMSUBPS4rr_REV + 852774615U, // VFNMSUBSD4mr + 852774615U, // VFNMSUBSD4mr_Int + 1089474263U, // VFNMSUBSD4rm + 1089474263U, // VFNMSUBSD4rm_Int + 890277591U, // VFNMSUBSD4rr + 890277591U, // VFNMSUBSD4rr_Int + 890277591U, // VFNMSUBSD4rr_Int_REV + 890277591U, // VFNMSUBSD4rr_REV + 856975314U, // VFNMSUBSS4mr + 856975314U, // VFNMSUBSS4mr_Int + 1089677266U, // VFNMSUBSS4rm + 1089677266U, // VFNMSUBSS4rm_Int + 890283986U, // VFNMSUBSS4rr + 890283986U, // VFNMSUBSS4rr_Int + 890283986U, // VFNMSUBSS4rr_Int_REV + 890283986U, // VFNMSUBSS4rr_REV + 77901811U, // VFPCLASSPDZ128rm + 3032783586U, // VFPCLASSPDZ128rmb + 2999311074U, // VFPCLASSPDZ128rmbk + 568717299U, // VFPCLASSPDZ128rmk + 283430104U, // VFPCLASSPDZ128rr + 1088818392U, // VFPCLASSPDZ128rrk + 168079470U, // VFPCLASSPDZ256rm + 1690606306U, // VFPCLASSPDZ256rmb + 1657133794U, // VFPCLASSPDZ256rmbk + 660992110U, // VFPCLASSPDZ256rmk + 283430104U, // VFPCLASSPDZ256rr + 1088818392U, // VFPCLASSPDZ256rrk + 170176747U, // VFPCLASSPDZrm + 2495912674U, // VFPCLASSPDZrmb + 2462440162U, // VFPCLASSPDZrmbk + 669380843U, // VFPCLASSPDZrmk + 283430104U, // VFPCLASSPDZrr + 1088818392U, // VFPCLASSPDZrrk + 77901913U, // VFPCLASSPSZ128rm + 1692702429U, // VFPCLASSPSZ128rmb + 1661327069U, // VFPCLASSPSZ128rmbk + 568717401U, // VFPCLASSPSZ128rmk + 283436561U, // VFPCLASSPSZ128rr + 1088824849U, // VFPCLASSPSZ128rrk + 168079582U, // VFPCLASSPSZ256rm + 2498008797U, // VFPCLASSPSZ256rmb + 2466633437U, // VFPCLASSPSZ256rmbk + 660992222U, // VFPCLASSPSZ256rmk + 283436561U, // VFPCLASSPSZ256rr + 1088824849U, // VFPCLASSPSZ256rrk + 170176760U, // VFPCLASSPSZrm + 2766444253U, // VFPCLASSPSZrmb + 2735068893U, // VFPCLASSPSZrmbk + 669380856U, // VFPCLASSPSZrmk + 283436561U, // VFPCLASSPSZrr + 1088824849U, // VFPCLASSPSZrrk + 885297054U, // VFPCLASSSDZrm + 851824542U, // VFPCLASSSDZrmk + 283430814U, // VFPCLASSSDZrr + 1088819102U, // VFPCLASSSDZrrk + 887400603U, // VFPCLASSSSZrm + 856025243U, // VFPCLASSSSZrmk + 283437211U, // VFPCLASSSSZrr + 1088825499U, // VFPCLASSSSZrrk + 1346906U, // VFRCZPDYrm + 551832922U, // VFRCZPDYrr + 658778U, // VFRCZPDrm + 551832922U, // VFRCZPDrr + 1353403U, // VFRCZPSYrm + 551839419U, // VFRCZPSYrr + 665275U, // VFRCZPSrm + 551839419U, // VFRCZPSrr + 552177694U, // VFRCZSDrm + 551833630U, // VFRCZSDrr + 552200437U, // VFRCZSSrm + 551839989U, // VFRCZSSrr + 649546633U, // VGATHERDPDYrm + 3231157129U, // VGATHERDPDZ128rm + 3231173513U, // VGATHERDPDZ256rm + 3231189897U, // VGATHERDPDZrm + 643255177U, // VGATHERDPDrm + 649553053U, // VGATHERDPSYrm + 3231163549U, // VGATHERDPSZ128rm + 3231179933U, // VGATHERDPSZ256rm + 3231196317U, // VGATHERDPSZrm + 643261597U, // VGATHERDPSrm + 172854001U, // VGATHERPF0DPDm + 172860398U, // VGATHERPF0DPSm + 172854386U, // VGATHERPF0QPDm + 173368747U, // VGATHERPF0QPSm + 172854032U, // VGATHERPF1DPDm + 172860429U, // VGATHERPF1DPSm + 172854417U, // VGATHERPF1QPDm + 173368778U, // VGATHERPF1QPSm + 649546928U, // VGATHERQPDYrm + 3231157424U, // VGATHERQPDZ128rm + 3231173808U, // VGATHERQPDZ256rm + 3231190192U, // VGATHERQPDZrm + 643255472U, // VGATHERQPDrm + 643261929U, // VGATHERQPSYrm + 553149929U, // VGATHERQPSZ128rm + 3231163881U, // VGATHERQPSZ256rm + 3231180265U, // VGATHERQPSZrm + 928474601U, // VGATHERQPSrm + 658535U, // VGETEXPPDZ128m + 627674215U, // VGETEXPPDZ128mb + 628100199U, // VGETEXPPDZ128mbk + 627199079U, // VGETEXPPDZ128mbkz + 3230600295U, // VGETEXPPDZ128mk + 3229748327U, // VGETEXPPDZ128mkz + 551832679U, // VGETEXPPDZ128r + 3230698599U, // VGETEXPPDZ128rk + 3229666407U, // VGETEXPPDZ128rkz + 1346663U, // VGETEXPPDZ256m + 629771367U, // VGETEXPPDZ256mb + 630197351U, // VGETEXPPDZ256mbk + 629296231U, // VGETEXPPDZ256mbkz + 3230731367U, // VGETEXPPDZ256mk + 3230633063U, // VGETEXPPDZ256mkz + 551832679U, // VGETEXPPDZ256r + 3230698599U, // VGETEXPPDZ256rk + 3229666407U, // VGETEXPPDZ256rkz + 1510503U, // VGETEXPPDZm + 631868519U, // VGETEXPPDZmb + 632294503U, // VGETEXPPDZmbk + 631393383U, // VGETEXPPDZmbkz + 3230780519U, // VGETEXPPDZmk + 3230747751U, // VGETEXPPDZmkz + 551832679U, // VGETEXPPDZr + 551843335U, // VGETEXPPDZrb + 3230709255U, // VGETEXPPDZrbk + 3229677063U, // VGETEXPPDZrbkz + 3230698599U, // VGETEXPPDZrk + 3229666407U, // VGETEXPPDZrkz + 664992U, // VGETEXPPSZ128m + 629794208U, // VGETEXPPSZ128mb + 630400416U, // VGETEXPPSZ128mbk + 629319072U, // VGETEXPPSZ128mbkz + 3230606752U, // VGETEXPPSZ128mk + 3229754784U, // VGETEXPPSZ128mkz + 551839136U, // VGETEXPPSZ128r + 3230705056U, // VGETEXPPSZ128rk + 3229672864U, // VGETEXPPSZ128rkz + 1353120U, // VGETEXPPSZ256m + 631891360U, // VGETEXPPSZ256mb + 632497568U, // VGETEXPPSZ256mbk + 631416224U, // VGETEXPPSZ256mbkz + 3230737824U, // VGETEXPPSZ256mk + 3230639520U, // VGETEXPPSZ256mkz + 551839136U, // VGETEXPPSZ256r + 3230705056U, // VGETEXPPSZ256rk + 3229672864U, // VGETEXPPSZ256rkz + 1516960U, // VGETEXPPSZm + 633988512U, // VGETEXPPSZmb + 634594720U, // VGETEXPPSZmbk + 633513376U, // VGETEXPPSZmbkz + 3230786976U, // VGETEXPPSZmk + 3230754208U, // VGETEXPPSZmkz + 551839136U, // VGETEXPPSZr + 551843822U, // VGETEXPPSZrb + 3230709742U, // VGETEXPPSZrbk + 3229677550U, // VGETEXPPSZrbkz + 3230705056U, // VGETEXPPSZrk + 3229672864U, // VGETEXPPSZrkz + 283266943U, // VGETEXPSDZm + 1357893503U, // VGETEXPSDZmk + 1089474431U, // VGETEXPSDZmkz + 811650943U, // VGETEXPSDZr + 811660942U, // VGETEXPSDZrb + 87062158U, // VGETEXPSDZrbk + 890287758U, // VGETEXPSDZrbkz + 87052159U, // VGETEXPSDZrk + 890277759U, // VGETEXPSDZrkz + 283289744U, // VGETEXPSSZm + 1358096528U, // VGETEXPSSZmk + 1089677456U, // VGETEXPSSZmkz + 811657360U, // VGETEXPSSZr + 811661411U, // VGETEXPSSZrb + 87062627U, // VGETEXPSSZrbk + 890288227U, // VGETEXPSSZrbkz + 87058576U, // VGETEXPSSZrk + 890284176U, // VGETEXPSSZrkz + 3032780034U, // VGETMANTPDZ128rmbi + 3079933186U, // VGETMANTPDZ128rmbik + 2999307522U, // VGETMANTPDZ128rmbikz + 77892866U, // VGETMANTPDZ128rmi + 666111234U, // VGETMANTPDZ128rmik + 568708354U, // VGETMANTPDZ128rmikz + 283430146U, // VGETMANTPDZ128rri + 1357581570U, // VGETMANTPDZ128rrik + 1088818434U, // VGETMANTPDZ128rrikz + 1690602754U, // VGETMANTPDZ256rmbi + 1737755906U, // VGETMANTPDZ256rmbik + 1657130242U, // VGETMANTPDZ256rmbikz + 168070402U, // VGETMANTPDZ256rmi + 668208386U, // VGETMANTPDZ256rmik + 660983042U, // VGETMANTPDZ256rmikz + 283430146U, // VGETMANTPDZ256rri + 1357581570U, // VGETMANTPDZ256rrik + 1088818434U, // VGETMANTPDZ256rrikz + 2495909122U, // VGETMANTPDZrmbi + 2543062274U, // VGETMANTPDZrmbik + 2462436610U, // VGETMANTPDZrmbikz + 170167554U, // VGETMANTPDZrmi + 672402690U, // VGETMANTPDZrmik + 669371650U, // VGETMANTPDZrmikz + 283430146U, // VGETMANTPDZrri + 407162114U, // VGETMANTPDZrrib + 1481313538U, // VGETMANTPDZrribk + 1212550402U, // VGETMANTPDZrribkz + 1357581570U, // VGETMANTPDZrrik + 1088818434U, // VGETMANTPDZrrikz + 1692706358U, // VGETMANTPSZ128rmbi + 1752442422U, // VGETMANTPSZ128rmbik + 1661330998U, // VGETMANTPSZ128rmbikz + 77899318U, // VGETMANTPSZ128rmi + 666117686U, // VGETMANTPSZ128rmik + 568714806U, // VGETMANTPSZ128rmikz + 283436598U, // VGETMANTPSZ128rri + 1357588022U, // VGETMANTPSZ128rrik + 1088824886U, // VGETMANTPSZ128rrikz + 2498012726U, // VGETMANTPSZ256rmbi + 2557748790U, // VGETMANTPSZ256rmbik + 2466637366U, // VGETMANTPSZ256rmbikz + 168076854U, // VGETMANTPSZ256rmi + 668214838U, // VGETMANTPSZ256rmik + 660989494U, // VGETMANTPSZ256rmikz + 283436598U, // VGETMANTPSZ256rri + 1357588022U, // VGETMANTPSZ256rrik + 1088824886U, // VGETMANTPSZ256rrikz + 2766448182U, // VGETMANTPSZrmbi + 2826184246U, // VGETMANTPSZrmbik + 2735072822U, // VGETMANTPSZrmbikz + 170174006U, // VGETMANTPSZrmi + 672409142U, // VGETMANTPSZrmik + 669378102U, // VGETMANTPSZrmikz + 283436598U, // VGETMANTPSZrri + 407168566U, // VGETMANTPSZrrib + 1481319990U, // VGETMANTPSZrribk + 1212556854U, // VGETMANTPSZrribkz + 1357588022U, // VGETMANTPSZrrik + 1088824886U, // VGETMANTPSZrrikz + 851824583U, // VGETMANTSDZrmi + 963891143U, // VGETMANTSDZrmik + 932450247U, // VGETMANTSDZrmikz + 1088819143U, // VGETMANTSDZrri + 1212551111U, // VGETMANTSDZrrib + 2286866375U, // VGETMANTSDZrribk + 1481314247U, // VGETMANTSDZrribkz + 2163134407U, // VGETMANTSDZrrik + 1357582279U, // VGETMANTSDZrrikz + 856025255U, // VGETMANTSSZrmi + 972286119U, // VGETMANTSSZrmik + 947136679U, // VGETMANTSSZrmikz + 1088825511U, // VGETMANTSSZrri + 1212557479U, // VGETMANTSSZrrib + 2286872743U, // VGETMANTSSZrribk + 1481320615U, // VGETMANTSSZrribkz + 2163140775U, // VGETMANTSSZrrik + 1357588647U, // VGETMANTSSZrrikz + 375768372U, // VGF2P8AFFINEINVQBYrmi + 1088816436U, // VGF2P8AFFINEINVQBYrri + 3026568500U, // VGF2P8AFFINEINVQBZ128rmbi + 3128149300U, // VGF2P8AFFINEINVQBZ128rmbik + 3130262836U, // VGF2P8AFFINEINVQBZ128rmbikz + 325436724U, // VGF2P8AFFINEINVQBZ128rmi + 1983104308U, // VGF2P8AFFINEINVQBZ128rmik + 1179911476U, // VGF2P8AFFINEINVQBZ128rmikz + 1088816436U, // VGF2P8AFFINEINVQBZ128rri + 2163131700U, // VGF2P8AFFINEINVQBZ128rrik + 1357579572U, // VGF2P8AFFINEINVQBZ128rrikz + 1684391220U, // VGF2P8AFFINEINVQBZ256rmbi + 1785972020U, // VGF2P8AFFINEINVQBZ256rmbik + 1788085556U, // VGF2P8AFFINEINVQBZ256rmbikz + 375768372U, // VGF2P8AFFINEINVQBZ256rmi + 1989395764U, // VGF2P8AFFINEINVQBZ256rmik + 1186202932U, // VGF2P8AFFINEINVQBZ256rmikz + 1088816436U, // VGF2P8AFFINEINVQBZ256rri + 2163131700U, // VGF2P8AFFINEINVQBZ256rrik + 1357579572U, // VGF2P8AFFINEINVQBZ256rrikz + 2489697588U, // VGF2P8AFFINEINVQBZrmbi + 2591278388U, // VGF2P8AFFINEINVQBZrmbik + 2593391924U, // VGF2P8AFFINEINVQBZrmbikz + 382059828U, // VGF2P8AFFINEINVQBZrmi + 1995687220U, // VGF2P8AFFINEINVQBZrmik + 1192494388U, // VGF2P8AFFINEINVQBZrmikz + 1088816436U, // VGF2P8AFFINEINVQBZrri + 2163131700U, // VGF2P8AFFINEINVQBZrrik + 1357579572U, // VGF2P8AFFINEINVQBZrrikz + 325436724U, // VGF2P8AFFINEINVQBrmi + 1088816436U, // VGF2P8AFFINEINVQBrri + 375768309U, // VGF2P8AFFINEQBYrmi + 1088816373U, // VGF2P8AFFINEQBYrri + 3026568437U, // VGF2P8AFFINEQBZ128rmbi + 3128149237U, // VGF2P8AFFINEQBZ128rmbik + 3130262773U, // VGF2P8AFFINEQBZ128rmbikz + 325436661U, // VGF2P8AFFINEQBZ128rmi + 1983104245U, // VGF2P8AFFINEQBZ128rmik + 1179911413U, // VGF2P8AFFINEQBZ128rmikz + 1088816373U, // VGF2P8AFFINEQBZ128rri + 2163131637U, // VGF2P8AFFINEQBZ128rrik + 1357579509U, // VGF2P8AFFINEQBZ128rrikz + 1684391157U, // VGF2P8AFFINEQBZ256rmbi + 1785971957U, // VGF2P8AFFINEQBZ256rmbik + 1788085493U, // VGF2P8AFFINEQBZ256rmbikz + 375768309U, // VGF2P8AFFINEQBZ256rmi + 1989395701U, // VGF2P8AFFINEQBZ256rmik + 1186202869U, // VGF2P8AFFINEQBZ256rmikz + 1088816373U, // VGF2P8AFFINEQBZ256rri + 2163131637U, // VGF2P8AFFINEQBZ256rrik + 1357579509U, // VGF2P8AFFINEQBZ256rrikz + 2489697525U, // VGF2P8AFFINEQBZrmbi + 2591278325U, // VGF2P8AFFINEQBZrmbik + 2593391861U, // VGF2P8AFFINEQBZrmbikz + 382059765U, // VGF2P8AFFINEQBZrmi + 1995687157U, // VGF2P8AFFINEQBZrmik + 1192494325U, // VGF2P8AFFINEQBZrmikz + 1088816373U, // VGF2P8AFFINEQBZrri + 2163131637U, // VGF2P8AFFINEQBZrrik + 1357579509U, // VGF2P8AFFINEQBZrrikz + 325436661U, // VGF2P8AFFINEQBrmi + 1088816373U, // VGF2P8AFFINEQBrri + 812860541U, // VGF2P8MULBYrm + 811648125U, // VGF2P8MULBYrr + 811844733U, // VGF2P8MULBZ128rm + 985105533U, // VGF2P8MULBZ128rmk + 890569853U, // VGF2P8MULBZ128rmkz + 811648125U, // VGF2P8MULBZ128rr + 87049341U, // VGF2P8MULBZ128rrk + 890274941U, // VGF2P8MULBZ128rrkz + 812860541U, // VGF2P8MULBZ256rm + 985121917U, // VGF2P8MULBZ256rmk + 890602621U, // VGF2P8MULBZ256rmkz + 811648125U, // VGF2P8MULBZ256rr + 87049341U, // VGF2P8MULBZ256rrk + 890274941U, // VGF2P8MULBZ256rrkz + 812876925U, // VGF2P8MULBZrm + 985138301U, // VGF2P8MULBZrmk + 890668157U, // VGF2P8MULBZrmkz + 811648125U, // VGF2P8MULBZrr + 87049341U, // VGF2P8MULBZrrk + 890274941U, // VGF2P8MULBZrrkz + 811844733U, // VGF2P8MULBrm + 811648125U, // VGF2P8MULBrr + 812616508U, // VHADDPDYrm + 811649852U, // VHADDPDYrr + 811731772U, // VHADDPDrm + 811649852U, // VHADDPDrr + 812622905U, // VHADDPSYrm + 811656249U, // VHADDPSYrr + 811738169U, // VHADDPSrm + 811656249U, // VHADDPSrr + 812616395U, // VHSUBPDYrm + 811649739U, // VHSUBPDYrr + 811731659U, // VHSUBPDrm + 811649739U, // VHSUBPDrr + 812622792U, // VHSUBPSYrm + 811656136U, // VHSUBPSYrr + 811738056U, // VHSUBPSrm + 811656136U, // VHSUBPSrr + 300270206U, // VINSERTF128rm + 1088815742U, // VINSERTF128rr + 300269988U, // VINSERTF32x4Z256rm + 2039726500U, // VINSERTF32x4Z256rmk + 1202979236U, // VINSERTF32x4Z256rmkz + 1088815524U, // VINSERTF32x4Z256rr + 2163130788U, // VINSERTF32x4Z256rrk + 1357578660U, // VINSERTF32x4Z256rrkz + 300269988U, // VINSERTF32x4Zrm + 2039726500U, // VINSERTF32x4Zrmk + 1202979236U, // VINSERTF32x4Zrmkz + 1088815524U, // VINSERTF32x4Zrr + 2163130788U, // VINSERTF32x4Zrrk + 1357578660U, // VINSERTF32x4Zrrkz + 392545003U, // VINSERTF32x8Zrm + 2041823979U, // VINSERTF32x8Zrmk + 1205076715U, // VINSERTF32x8Zrmkz + 1088815851U, // VINSERTF32x8Zrr + 2163131115U, // VINSERTF32x8Zrrk + 1357578987U, // VINSERTF32x8Zrrkz + 300269775U, // VINSERTF64x2Z256rm + 2039726287U, // VINSERTF64x2Z256rmk + 1202979023U, // VINSERTF64x2Z256rmkz + 1088815311U, // VINSERTF64x2Z256rr + 2163130575U, // VINSERTF64x2Z256rrk + 1357578447U, // VINSERTF64x2Z256rrkz + 300269775U, // VINSERTF64x2Zrm + 2039726287U, // VINSERTF64x2Zrmk + 1202979023U, // VINSERTF64x2Zrmkz + 1088815311U, // VINSERTF64x2Zrr + 2163130575U, // VINSERTF64x2Zrrk + 1357578447U, // VINSERTF64x2Zrrkz + 392544780U, // VINSERTF64x4Zrm + 2041823756U, // VINSERTF64x4Zrmk + 1205076492U, // VINSERTF64x4Zrmkz + 1088815628U, // VINSERTF64x4Zrr + 2163130892U, // VINSERTF64x4Zrrk + 1357578764U, // VINSERTF64x4Zrrkz + 325436085U, // VINSERTI128rm + 1088815797U, // VINSERTI128rr + 325435870U, // VINSERTI32x4Z256rm + 1983103454U, // VINSERTI32x4Z256rmk + 1179910622U, // VINSERTI32x4Z256rmkz + 1088815582U, // VINSERTI32x4Z256rr + 2163130846U, // VINSERTI32x4Z256rrk + 1357578718U, // VINSERTI32x4Z256rrkz + 325435870U, // VINSERTI32x4Zrm + 1983103454U, // VINSERTI32x4Zrmk + 1179910622U, // VINSERTI32x4Zrmkz + 1088815582U, // VINSERTI32x4Zrr + 2163130846U, // VINSERTI32x4Zrrk + 1357578718U, // VINSERTI32x4Zrrkz + 375767833U, // VINSERTI32x8Zrm + 1989395225U, // VINSERTI32x8Zrmk + 1186202393U, // VINSERTI32x8Zrmkz + 1088815897U, // VINSERTI32x8Zrr + 2163131161U, // VINSERTI32x8Zrrk + 1357579033U, // VINSERTI32x8Zrrkz + 325435657U, // VINSERTI64x2Z256rm + 1983103241U, // VINSERTI64x2Z256rmk + 1179910409U, // VINSERTI64x2Z256rmkz + 1088815369U, // VINSERTI64x2Z256rr + 2163130633U, // VINSERTI64x2Z256rrk + 1357578505U, // VINSERTI64x2Z256rrkz + 325435657U, // VINSERTI64x2Zrm + 1983103241U, // VINSERTI64x2Zrmk + 1179910409U, // VINSERTI64x2Zrmkz + 1088815369U, // VINSERTI64x2Zrr + 2163130633U, // VINSERTI64x2Zrrk + 1357578505U, // VINSERTI64x2Zrrkz + 375767610U, // VINSERTI64x4Zrm + 1989395002U, // VINSERTI64x4Zrmk + 1186202170U, // VINSERTI64x4Zrmkz + 1088815674U, // VINSERTI64x4Zrr + 2163130938U, // VINSERTI64x4Zrrk + 1357578810U, // VINSERTI64x4Zrrkz + 856024652U, // VINSERTPSZrm + 1088824908U, // VINSERTPSZrr + 856024652U, // VINSERTPSrm + 1088824908U, // VINSERTPSrr + 552954308U, // VLDDQUYrm + 272836U, // VLDDQUrm + 237909U, // VLDMXCSR + 551840204U, // VMASKMOVDQU + 551840204U, // VMASKMOVDQU64 + 1663372614U, // VMASKMOVPDYmr + 812617030U, // VMASKMOVPDYrm + 1126501702U, // VMASKMOVPDmr + 811732294U, // VMASKMOVPDrm + 1663379111U, // VMASKMOVPSYmr + 812623527U, // VMASKMOVPSYrm + 1126508199U, // VMASKMOVPSmr + 811738791U, // VMASKMOVPSrm + 812617042U, // VMAXCPDYrm + 811650386U, // VMAXCPDYrr + 811732306U, // VMAXCPDZ128rm + 358763858U, // VMAXCPDZ128rmb + 1433390418U, // VMAXCPDZ128rmbk + 1164971346U, // VMAXCPDZ128rmbkz + 86986066U, // VMAXCPDZ128rmk + 890178898U, // VMAXCPDZ128rmkz + 811650386U, // VMAXCPDZ128rr + 87051602U, // VMAXCPDZ128rrk + 890277202U, // VMAXCPDZ128rrkz + 812617042U, // VMAXCPDZ256rm + 360861010U, // VMAXCPDZ256rmb + 1435487570U, // VMAXCPDZ256rmbk + 1167068498U, // VMAXCPDZ256rmbkz + 87084370U, // VMAXCPDZ256rmk + 890309970U, // VMAXCPDZ256rmkz + 811650386U, // VMAXCPDZ256rr + 87051602U, // VMAXCPDZ256rrk + 890277202U, // VMAXCPDZ256rrkz + 812731730U, // VMAXCPDZrm + 362958162U, // VMAXCPDZrmb + 1437584722U, // VMAXCPDZrmbk + 1169165650U, // VMAXCPDZrmbkz + 87133522U, // VMAXCPDZrmk + 890359122U, // VMAXCPDZrmkz + 811650386U, // VMAXCPDZrr + 87051602U, // VMAXCPDZrrk + 890277202U, // VMAXCPDZrrkz + 811732306U, // VMAXCPDrm + 811650386U, // VMAXCPDrr + 812623539U, // VMAXCPSYrm + 811656883U, // VMAXCPSYrr + 811738803U, // VMAXCPSZ128rm + 360883891U, // VMAXCPSZ128rmb + 1435690675U, // VMAXCPSZ128rmbk + 1167271603U, // VMAXCPSZ128rmbkz + 86992563U, // VMAXCPSZ128rmk + 890185395U, // VMAXCPSZ128rmkz + 811656883U, // VMAXCPSZ128rr + 87058099U, // VMAXCPSZ128rrk + 890283699U, // VMAXCPSZ128rrkz + 812623539U, // VMAXCPSZ256rm + 362981043U, // VMAXCPSZ256rmb + 1437787827U, // VMAXCPSZ256rmbk + 1169368755U, // VMAXCPSZ256rmbkz + 87090867U, // VMAXCPSZ256rmk + 890316467U, // VMAXCPSZ256rmkz + 811656883U, // VMAXCPSZ256rr + 87058099U, // VMAXCPSZ256rrk + 890283699U, // VMAXCPSZ256rrkz + 812738227U, // VMAXCPSZrm + 365078195U, // VMAXCPSZrmb + 1439884979U, // VMAXCPSZrmbk + 1171465907U, // VMAXCPSZrmbkz + 87140019U, // VMAXCPSZrmk + 890365619U, // VMAXCPSZrmkz + 811656883U, // VMAXCPSZrr + 87058099U, // VMAXCPSZrrk + 890283699U, // VMAXCPSZrrkz + 811738803U, // VMAXCPSrm + 811656883U, // VMAXCPSrr + 283267094U, // VMAXCSDZrm + 811651094U, // VMAXCSDZrr + 283267094U, // VMAXCSDrm + 811651094U, // VMAXCSDrr + 283289837U, // VMAXCSSZrm + 811657453U, // VMAXCSSZrr + 283289837U, // VMAXCSSrm + 811657453U, // VMAXCSSrr + 812617042U, // VMAXPDYrm + 811650386U, // VMAXPDYrr + 811732306U, // VMAXPDZ128rm + 358763858U, // VMAXPDZ128rmb + 1433390418U, // VMAXPDZ128rmbk + 1164971346U, // VMAXPDZ128rmbkz + 86986066U, // VMAXPDZ128rmk + 890178898U, // VMAXPDZ128rmkz + 811650386U, // VMAXPDZ128rr + 87051602U, // VMAXPDZ128rrk + 890277202U, // VMAXPDZ128rrkz + 812617042U, // VMAXPDZ256rm + 360861010U, // VMAXPDZ256rmb + 1435487570U, // VMAXPDZ256rmbk + 1167068498U, // VMAXPDZ256rmbkz + 87084370U, // VMAXPDZ256rmk + 890309970U, // VMAXPDZ256rmkz + 811650386U, // VMAXPDZ256rr + 87051602U, // VMAXPDZ256rrk + 890277202U, // VMAXPDZ256rrkz + 812731730U, // VMAXPDZrm + 362958162U, // VMAXPDZrmb + 1437584722U, // VMAXPDZrmbk + 1169165650U, // VMAXPDZrmbkz + 87133522U, // VMAXPDZrmk + 890359122U, // VMAXPDZrmkz + 811650386U, // VMAXPDZrr + 811660825U, // VMAXPDZrrb + 87062041U, // VMAXPDZrrbk + 890287641U, // VMAXPDZrrbkz + 87051602U, // VMAXPDZrrk + 890277202U, // VMAXPDZrrkz + 811732306U, // VMAXPDrm + 811650386U, // VMAXPDrr + 812623539U, // VMAXPSYrm + 811656883U, // VMAXPSYrr + 811738803U, // VMAXPSZ128rm + 360883891U, // VMAXPSZ128rmb + 1435690675U, // VMAXPSZ128rmbk + 1167271603U, // VMAXPSZ128rmbkz + 86992563U, // VMAXPSZ128rmk + 890185395U, // VMAXPSZ128rmkz + 811656883U, // VMAXPSZ128rr + 87058099U, // VMAXPSZ128rrk + 890283699U, // VMAXPSZ128rrkz + 812623539U, // VMAXPSZ256rm + 362981043U, // VMAXPSZ256rmb + 1437787827U, // VMAXPSZ256rmbk + 1169368755U, // VMAXPSZ256rmbkz + 87090867U, // VMAXPSZ256rmk + 890316467U, // VMAXPSZ256rmkz + 811656883U, // VMAXPSZ256rr + 87058099U, // VMAXPSZ256rrk + 890283699U, // VMAXPSZ256rrkz + 812738227U, // VMAXPSZrm + 365078195U, // VMAXPSZrmb + 1439884979U, // VMAXPSZrmbk + 1171465907U, // VMAXPSZrmbkz + 87140019U, // VMAXPSZrmk + 890365619U, // VMAXPSZrmkz + 811656883U, // VMAXPSZrr + 811661312U, // VMAXPSZrrb + 87062528U, // VMAXPSZrrbk + 890288128U, // VMAXPSZrrbkz + 87058099U, // VMAXPSZrrk + 890283699U, // VMAXPSZrrkz + 811738803U, // VMAXPSrm + 811656883U, // VMAXPSrr + 283267094U, // VMAXSDZrm + 283267094U, // VMAXSDZrm_Int + 1357893654U, // VMAXSDZrm_Intk + 1089474582U, // VMAXSDZrm_Intkz + 811651094U, // VMAXSDZrr + 811651094U, // VMAXSDZrr_Int + 87052310U, // VMAXSDZrr_Intk + 890277910U, // VMAXSDZrr_Intkz + 811660960U, // VMAXSDZrrb_Int + 87062176U, // VMAXSDZrrb_Intk + 890287776U, // VMAXSDZrrb_Intkz + 283267094U, // VMAXSDrm + 283267094U, // VMAXSDrm_Int + 811651094U, // VMAXSDrr + 811651094U, // VMAXSDrr_Int + 283289837U, // VMAXSSZrm + 283289837U, // VMAXSSZrm_Int + 1358096621U, // VMAXSSZrm_Intk + 1089677549U, // VMAXSSZrm_Intkz + 811657453U, // VMAXSSZrr + 811657453U, // VMAXSSZrr_Int + 87058669U, // VMAXSSZrr_Intk + 890284269U, // VMAXSSZrr_Intkz + 811661429U, // VMAXSSZrrb_Int + 87062645U, // VMAXSSZrrb_Intk + 890288245U, // VMAXSSZrrb_Intkz + 283289837U, // VMAXSSrm + 283289837U, // VMAXSSrm_Int + 811657453U, // VMAXSSrr + 811657453U, // VMAXSSrr_Int + 15223U, // VMCALL + 450821U, // VMCLEARm + 14950U, // VMFUNC + 812616784U, // VMINCPDYrm + 811650128U, // VMINCPDYrr + 811732048U, // VMINCPDZ128rm + 358763600U, // VMINCPDZ128rmb + 1433390160U, // VMINCPDZ128rmbk + 1164971088U, // VMINCPDZ128rmbkz + 86985808U, // VMINCPDZ128rmk + 890178640U, // VMINCPDZ128rmkz + 811650128U, // VMINCPDZ128rr + 87051344U, // VMINCPDZ128rrk + 890276944U, // VMINCPDZ128rrkz + 812616784U, // VMINCPDZ256rm + 360860752U, // VMINCPDZ256rmb + 1435487312U, // VMINCPDZ256rmbk + 1167068240U, // VMINCPDZ256rmbkz + 87084112U, // VMINCPDZ256rmk + 890309712U, // VMINCPDZ256rmkz + 811650128U, // VMINCPDZ256rr + 87051344U, // VMINCPDZ256rrk + 890276944U, // VMINCPDZ256rrkz + 812731472U, // VMINCPDZrm + 362957904U, // VMINCPDZrmb + 1437584464U, // VMINCPDZrmbk + 1169165392U, // VMINCPDZrmbkz + 87133264U, // VMINCPDZrmk + 890358864U, // VMINCPDZrmkz + 811650128U, // VMINCPDZrr + 87051344U, // VMINCPDZrrk + 890276944U, // VMINCPDZrrkz + 811732048U, // VMINCPDrm + 811650128U, // VMINCPDrr + 812623233U, // VMINCPSYrm + 811656577U, // VMINCPSYrr + 811738497U, // VMINCPSZ128rm + 360883585U, // VMINCPSZ128rmb + 1435690369U, // VMINCPSZ128rmbk + 1167271297U, // VMINCPSZ128rmbkz + 86992257U, // VMINCPSZ128rmk + 890185089U, // VMINCPSZ128rmkz + 811656577U, // VMINCPSZ128rr + 87057793U, // VMINCPSZ128rrk + 890283393U, // VMINCPSZ128rrkz + 812623233U, // VMINCPSZ256rm + 362980737U, // VMINCPSZ256rmb + 1437787521U, // VMINCPSZ256rmbk + 1169368449U, // VMINCPSZ256rmbkz + 87090561U, // VMINCPSZ256rmk + 890316161U, // VMINCPSZ256rmkz + 811656577U, // VMINCPSZ256rr + 87057793U, // VMINCPSZ256rrk + 890283393U, // VMINCPSZ256rrkz + 812737921U, // VMINCPSZrm + 365077889U, // VMINCPSZrmb + 1439884673U, // VMINCPSZrmbk + 1171465601U, // VMINCPSZrmbkz + 87139713U, // VMINCPSZrmk + 890365313U, // VMINCPSZrmkz + 811656577U, // VMINCPSZrr + 87057793U, // VMINCPSZrrk + 890283393U, // VMINCPSZrrkz + 811738497U, // VMINCPSrm + 811656577U, // VMINCPSrr + 283266927U, // VMINCSDZrm + 811650927U, // VMINCSDZrr + 283266927U, // VMINCSDrm + 811650927U, // VMINCSDrr + 283289720U, // VMINCSSZrm + 811657336U, // VMINCSSZrr + 283289720U, // VMINCSSrm + 811657336U, // VMINCSSrr + 812616784U, // VMINPDYrm + 811650128U, // VMINPDYrr + 811732048U, // VMINPDZ128rm + 358763600U, // VMINPDZ128rmb + 1433390160U, // VMINPDZ128rmbk + 1164971088U, // VMINPDZ128rmbkz + 86985808U, // VMINPDZ128rmk + 890178640U, // VMINPDZ128rmkz + 811650128U, // VMINPDZ128rr + 87051344U, // VMINPDZ128rrk + 890276944U, // VMINPDZ128rrkz + 812616784U, // VMINPDZ256rm + 360860752U, // VMINPDZ256rmb + 1435487312U, // VMINPDZ256rmbk + 1167068240U, // VMINPDZ256rmbkz + 87084112U, // VMINPDZ256rmk + 890309712U, // VMINPDZ256rmkz + 811650128U, // VMINPDZ256rr + 87051344U, // VMINPDZ256rrk + 890276944U, // VMINPDZ256rrkz + 812731472U, // VMINPDZrm + 362957904U, // VMINPDZrmb + 1437584464U, // VMINPDZrmbk + 1169165392U, // VMINPDZrmbkz + 87133264U, // VMINPDZrmk + 890358864U, // VMINPDZrmkz + 811650128U, // VMINPDZrr + 811660792U, // VMINPDZrrb + 87062008U, // VMINPDZrrbk + 890287608U, // VMINPDZrrbkz + 87051344U, // VMINPDZrrk + 890276944U, // VMINPDZrrkz + 811732048U, // VMINPDrm + 811650128U, // VMINPDrr + 812623233U, // VMINPSYrm + 811656577U, // VMINPSYrr + 811738497U, // VMINPSZ128rm + 360883585U, // VMINPSZ128rmb + 1435690369U, // VMINPSZ128rmbk + 1167271297U, // VMINPSZ128rmbkz + 86992257U, // VMINPSZ128rmk + 890185089U, // VMINPSZ128rmkz + 811656577U, // VMINPSZ128rr + 87057793U, // VMINPSZ128rrk + 890283393U, // VMINPSZ128rrkz + 812623233U, // VMINPSZ256rm + 362980737U, // VMINPSZ256rmb + 1437787521U, // VMINPSZ256rmbk + 1169368449U, // VMINPSZ256rmbkz + 87090561U, // VMINPSZ256rmk + 890316161U, // VMINPSZ256rmkz + 811656577U, // VMINPSZ256rr + 87057793U, // VMINPSZ256rrk + 890283393U, // VMINPSZ256rrkz + 812737921U, // VMINPSZrm + 365077889U, // VMINPSZrmb + 1439884673U, // VMINPSZrmbk + 1171465601U, // VMINPSZrmbkz + 87139713U, // VMINPSZrmk + 890365313U, // VMINPSZrmkz + 811656577U, // VMINPSZrr + 811661279U, // VMINPSZrrb + 87062495U, // VMINPSZrrbk + 890288095U, // VMINPSZrrbkz + 87057793U, // VMINPSZrrk + 890283393U, // VMINPSZrrkz + 811738497U, // VMINPSrm + 811656577U, // VMINPSrr + 283266927U, // VMINSDZrm + 283266927U, // VMINSDZrm_Int + 1357893487U, // VMINSDZrm_Intk + 1089474415U, // VMINSDZrm_Intkz + 811650927U, // VMINSDZrr + 811650927U, // VMINSDZrr_Int + 87052143U, // VMINSDZrr_Intk + 890277743U, // VMINSDZrr_Intkz + 811660927U, // VMINSDZrrb_Int + 87062143U, // VMINSDZrrb_Intk + 890287743U, // VMINSDZrrb_Intkz + 283266927U, // VMINSDrm + 283266927U, // VMINSDrm_Int + 811650927U, // VMINSDrr + 811650927U, // VMINSDrr_Int + 283289720U, // VMINSSZrm + 283289720U, // VMINSSZrm_Int + 1358096504U, // VMINSSZrm_Intk + 1089677432U, // VMINSSZrm_Intkz + 811657336U, // VMINSSZrr + 811657336U, // VMINSSZrr_Int + 87058552U, // VMINSSZrr_Intk + 890284152U, // VMINSSZrr_Intkz + 811661396U, // VMINSSZrrb_Int + 87062612U, // VMINSSZrrb_Intk + 890288212U, // VMINSSZrrb_Intkz + 283289720U, // VMINSSrm + 283289720U, // VMINSSrm_Int + 811657336U, // VMINSSrr + 811657336U, // VMINSSrr_Int + 15124U, // VMLAUNCH + 16019U, // VMLOAD32 + 16080U, // VMLOAD64 + 15215U, // VMMCALL + 551919746U, // VMOV64toPQIZrm + 551837826U, // VMOV64toPQIZrr + 551919746U, // VMOV64toPQIrm + 551837826U, // VMOV64toPQIrr + 551919746U, // VMOV64toSDZrm + 551837826U, // VMOV64toSDZrr + 551919746U, // VMOV64toSDrm + 551837826U, // VMOV64toSDrr + 148933282U, // VMOVAPDYmr + 1346210U, // VMOVAPDYrm + 551832226U, // VMOVAPDYrr + 551832226U, // VMOVAPDYrr_REV + 65047202U, // VMOVAPDZ128mr + 3286567586U, // VMOVAPDZ128mrk + 658082U, // VMOVAPDZ128rm + 3230599842U, // VMOVAPDZ128rmk + 3229747874U, // VMOVAPDZ128rmkz + 551832226U, // VMOVAPDZ128rr + 551832226U, // VMOVAPDZ128rr_REV + 3230698146U, // VMOVAPDZ128rrk + 3229665954U, // VMOVAPDZ128rrk_REV + 3229665954U, // VMOVAPDZ128rrkz + 3229665954U, // VMOVAPDZ128rrkz_REV + 148933282U, // VMOVAPDZ256mr + 3370453666U, // VMOVAPDZ256mrk + 1346210U, // VMOVAPDZ256rm + 3230730914U, // VMOVAPDZ256rmk + 3230632610U, // VMOVAPDZ256rmkz + 551832226U, // VMOVAPDZ256rr + 551832226U, // VMOVAPDZ256rr_REV + 3230698146U, // VMOVAPDZ256rrk + 3229665954U, // VMOVAPDZ256rrk_REV + 3229665954U, // VMOVAPDZ256rrkz + 3229665954U, // VMOVAPDZ256rrkz_REV + 151030434U, // VMOVAPDZmr + 3372550818U, // VMOVAPDZmrk + 1510050U, // VMOVAPDZrm + 3230780066U, // VMOVAPDZrmk + 3230747298U, // VMOVAPDZrmkz + 551832226U, // VMOVAPDZrr + 551832226U, // VMOVAPDZrr_REV + 3230698146U, // VMOVAPDZrrk + 3229665954U, // VMOVAPDZrrk_REV + 3229665954U, // VMOVAPDZrrkz + 3229665954U, // VMOVAPDZrrkz_REV + 65047202U, // VMOVAPDmr + 658082U, // VMOVAPDrm + 551832226U, // VMOVAPDrr + 551832226U, // VMOVAPDrr_REV + 148939687U, // VMOVAPSYmr + 1352615U, // VMOVAPSYrm + 551838631U, // VMOVAPSYrr + 551838631U, // VMOVAPSYrr_REV + 65053607U, // VMOVAPSZ128mr + 3286573991U, // VMOVAPSZ128mrk + 664487U, // VMOVAPSZ128rm + 3230606247U, // VMOVAPSZ128rmk + 3229754279U, // VMOVAPSZ128rmkz + 551838631U, // VMOVAPSZ128rr + 551838631U, // VMOVAPSZ128rr_REV + 3230704551U, // VMOVAPSZ128rrk + 3229672359U, // VMOVAPSZ128rrk_REV + 3229672359U, // VMOVAPSZ128rrkz + 3229672359U, // VMOVAPSZ128rrkz_REV + 148939687U, // VMOVAPSZ256mr + 3370460071U, // VMOVAPSZ256mrk + 1352615U, // VMOVAPSZ256rm + 3230737319U, // VMOVAPSZ256rmk + 3230639015U, // VMOVAPSZ256rmkz + 551838631U, // VMOVAPSZ256rr + 551838631U, // VMOVAPSZ256rr_REV + 3230704551U, // VMOVAPSZ256rrk + 3229672359U, // VMOVAPSZ256rrk_REV + 3229672359U, // VMOVAPSZ256rrkz + 3229672359U, // VMOVAPSZ256rrkz_REV + 151036839U, // VMOVAPSZmr + 3372557223U, // VMOVAPSZmrk + 1516455U, // VMOVAPSZrm + 3230786471U, // VMOVAPSZrmk + 3230753703U, // VMOVAPSZrmkz + 551838631U, // VMOVAPSZrr + 551838631U, // VMOVAPSZrr_REV + 3230704551U, // VMOVAPSZrrk + 3229672359U, // VMOVAPSZrrk_REV + 3229672359U, // VMOVAPSZrrkz + 3229672359U, // VMOVAPSZrrkz_REV + 65053607U, // VMOVAPSmr + 664487U, // VMOVAPSrm + 551838631U, // VMOVAPSrr + 551838631U, // VMOVAPSrr_REV + 1349887U, // VMOVDDUPYrm + 551835903U, // VMOVDDUPYrr + 552179967U, // VMOVDDUPZ128rm + 552605951U, // VMOVDDUPZ128rmk + 551704831U, // VMOVDDUPZ128rmkz + 551835903U, // VMOVDDUPZ128rr + 3230701823U, // VMOVDDUPZ128rrk + 3229669631U, // VMOVDDUPZ128rrkz + 1349887U, // VMOVDDUPZ256rm + 3230734591U, // VMOVDDUPZ256rmk + 3230636287U, // VMOVDDUPZ256rmkz + 551835903U, // VMOVDDUPZ256rr + 3230701823U, // VMOVDDUPZ256rrk + 3229669631U, // VMOVDDUPZ256rrkz + 1513727U, // VMOVDDUPZrm + 3230783743U, // VMOVDDUPZrmk + 3230750975U, // VMOVDDUPZrmkz + 551835903U, // VMOVDDUPZrr + 3230701823U, // VMOVDDUPZrrk + 3229669631U, // VMOVDDUPZrrkz + 552179967U, // VMOVDDUPrm + 551835903U, // VMOVDDUPrr + 551899369U, // VMOVDI2PDIZrm + 551833833U, // VMOVDI2PDIZrr + 551899369U, // VMOVDI2PDIrm + 551833833U, // VMOVDI2PDIrr + 551899369U, // VMOVDI2SSZrm + 551833833U, // VMOVDI2SSZrr + 551899369U, // VMOVDI2SSrm + 551833833U, // VMOVDI2SSrr + 33587280U, // VMOVDQA32Z128mr + 3255107664U, // VMOVDQA32Z128mrk + 262224U, // VMOVDQA32Z128rm + 3230990416U, // VMOVDQA32Z128rmk + 3229859920U, // VMOVDQA32Z128rmkz + 551829584U, // VMOVDQA32Z128rr + 551829584U, // VMOVDQA32Z128rr_REV + 3230695504U, // VMOVDQA32Z128rrk + 3229663312U, // VMOVDQA32Z128rrk_REV + 3229663312U, // VMOVDQA32Z128rrkz + 3229663312U, // VMOVDQA32Z128rrkz_REV + 180387920U, // VMOVDQA32Z256mr + 3401908304U, // VMOVDQA32Z256mrk + 552943696U, // VMOVDQA32Z256rm + 3231023184U, // VMOVDQA32Z256rmk + 3230875728U, // VMOVDQA32Z256rmkz + 551829584U, // VMOVDQA32Z256rr + 551829584U, // VMOVDQA32Z256rr_REV + 3230695504U, // VMOVDQA32Z256rrk + 3229663312U, // VMOVDQA32Z256rrk_REV + 3229663312U, // VMOVDQA32Z256rrkz + 3229663312U, // VMOVDQA32Z256rrkz_REV + 182485072U, // VMOVDQA32Zmr + 3404005456U, // VMOVDQA32Zmrk + 552435792U, // VMOVDQA32Zrm + 3231088720U, // VMOVDQA32Zrmk + 3230892112U, // VMOVDQA32Zrmkz + 551829584U, // VMOVDQA32Zrr + 551829584U, // VMOVDQA32Zrr_REV + 3230695504U, // VMOVDQA32Zrrk + 3229663312U, // VMOVDQA32Zrrk_REV + 3229663312U, // VMOVDQA32Zrrkz + 3229663312U, // VMOVDQA32Zrrkz_REV + 33587496U, // VMOVDQA64Z128mr + 3255107880U, // VMOVDQA64Z128mrk + 262440U, // VMOVDQA64Z128rm + 3230990632U, // VMOVDQA64Z128rmk + 3229860136U, // VMOVDQA64Z128rmkz + 551829800U, // VMOVDQA64Z128rr + 551829800U, // VMOVDQA64Z128rr_REV + 3230695720U, // VMOVDQA64Z128rrk + 3229663528U, // VMOVDQA64Z128rrk_REV + 3229663528U, // VMOVDQA64Z128rrkz + 3229663528U, // VMOVDQA64Z128rrkz_REV + 180388136U, // VMOVDQA64Z256mr + 3401908520U, // VMOVDQA64Z256mrk + 552943912U, // VMOVDQA64Z256rm + 3231023400U, // VMOVDQA64Z256rmk + 3230875944U, // VMOVDQA64Z256rmkz + 551829800U, // VMOVDQA64Z256rr + 551829800U, // VMOVDQA64Z256rr_REV + 3230695720U, // VMOVDQA64Z256rrk + 3229663528U, // VMOVDQA64Z256rrk_REV + 3229663528U, // VMOVDQA64Z256rrkz + 3229663528U, // VMOVDQA64Z256rrkz_REV + 182485288U, // VMOVDQA64Zmr + 3404005672U, // VMOVDQA64Zmrk + 552436008U, // VMOVDQA64Zrm + 3231088936U, // VMOVDQA64Zrmk + 3230892328U, // VMOVDQA64Zrmkz + 551829800U, // VMOVDQA64Zrr + 551829800U, // VMOVDQA64Zrr_REV + 3230695720U, // VMOVDQA64Zrrk + 3229663528U, // VMOVDQA64Zrrk_REV + 3229663528U, // VMOVDQA64Zrrkz + 3229663528U, // VMOVDQA64Zrrkz_REV + 180388679U, // VMOVDQAYmr + 552944455U, // VMOVDQAYrm + 551830343U, // VMOVDQAYrr + 551830343U, // VMOVDQAYrr_REV + 33588039U, // VMOVDQAmr + 262983U, // VMOVDQArm + 551830343U, // VMOVDQArr + 551830343U, // VMOVDQArr_REV + 33587801U, // VMOVDQU16Z128mr + 3255108185U, // VMOVDQU16Z128mrk + 262745U, // VMOVDQU16Z128rm + 3230990937U, // VMOVDQU16Z128rmk + 3229860441U, // VMOVDQU16Z128rmkz + 551830105U, // VMOVDQU16Z128rr + 551830105U, // VMOVDQU16Z128rr_REV + 3230696025U, // VMOVDQU16Z128rrk + 3229663833U, // VMOVDQU16Z128rrk_REV + 3229663833U, // VMOVDQU16Z128rrkz + 3229663833U, // VMOVDQU16Z128rrkz_REV + 180388441U, // VMOVDQU16Z256mr + 3401908825U, // VMOVDQU16Z256mrk + 552944217U, // VMOVDQU16Z256rm + 3231023705U, // VMOVDQU16Z256rmk + 3230876249U, // VMOVDQU16Z256rmkz + 551830105U, // VMOVDQU16Z256rr + 551830105U, // VMOVDQU16Z256rr_REV + 3230696025U, // VMOVDQU16Z256rrk + 3229663833U, // VMOVDQU16Z256rrk_REV + 3229663833U, // VMOVDQU16Z256rrkz + 3229663833U, // VMOVDQU16Z256rrkz_REV + 182485593U, // VMOVDQU16Zmr + 3404005977U, // VMOVDQU16Zmrk + 552436313U, // VMOVDQU16Zrm + 3231089241U, // VMOVDQU16Zrmk + 3230892633U, // VMOVDQU16Zrmkz + 551830105U, // VMOVDQU16Zrr + 551830105U, // VMOVDQU16Zrr_REV + 3230696025U, // VMOVDQU16Zrrk + 3229663833U, // VMOVDQU16Zrrk_REV + 3229663833U, // VMOVDQU16Zrrkz + 3229663833U, // VMOVDQU16Zrrkz_REV + 33587291U, // VMOVDQU32Z128mr + 3255107675U, // VMOVDQU32Z128mrk + 262235U, // VMOVDQU32Z128rm + 3230990427U, // VMOVDQU32Z128rmk + 3229859931U, // VMOVDQU32Z128rmkz + 551829595U, // VMOVDQU32Z128rr + 551829595U, // VMOVDQU32Z128rr_REV + 3230695515U, // VMOVDQU32Z128rrk + 3229663323U, // VMOVDQU32Z128rrk_REV + 3229663323U, // VMOVDQU32Z128rrkz + 3229663323U, // VMOVDQU32Z128rrkz_REV + 180387931U, // VMOVDQU32Z256mr + 3401908315U, // VMOVDQU32Z256mrk + 552943707U, // VMOVDQU32Z256rm + 3231023195U, // VMOVDQU32Z256rmk + 3230875739U, // VMOVDQU32Z256rmkz + 551829595U, // VMOVDQU32Z256rr + 551829595U, // VMOVDQU32Z256rr_REV + 3230695515U, // VMOVDQU32Z256rrk + 3229663323U, // VMOVDQU32Z256rrk_REV + 3229663323U, // VMOVDQU32Z256rrkz + 3229663323U, // VMOVDQU32Z256rrkz_REV + 182485083U, // VMOVDQU32Zmr + 3404005467U, // VMOVDQU32Zmrk + 552435803U, // VMOVDQU32Zrm + 3231088731U, // VMOVDQU32Zrmk + 3230892123U, // VMOVDQU32Zrmkz + 551829595U, // VMOVDQU32Zrr + 551829595U, // VMOVDQU32Zrr_REV + 3230695515U, // VMOVDQU32Zrrk + 3229663323U, // VMOVDQU32Zrrk_REV + 3229663323U, // VMOVDQU32Zrrkz + 3229663323U, // VMOVDQU32Zrrkz_REV + 33587571U, // VMOVDQU64Z128mr + 3255107955U, // VMOVDQU64Z128mrk + 262515U, // VMOVDQU64Z128rm + 3230990707U, // VMOVDQU64Z128rmk + 3229860211U, // VMOVDQU64Z128rmkz + 551829875U, // VMOVDQU64Z128rr + 551829875U, // VMOVDQU64Z128rr_REV + 3230695795U, // VMOVDQU64Z128rrk + 3229663603U, // VMOVDQU64Z128rrk_REV + 3229663603U, // VMOVDQU64Z128rrkz + 3229663603U, // VMOVDQU64Z128rrkz_REV + 180388211U, // VMOVDQU64Z256mr + 3401908595U, // VMOVDQU64Z256mrk + 552943987U, // VMOVDQU64Z256rm + 3231023475U, // VMOVDQU64Z256rmk + 3230876019U, // VMOVDQU64Z256rmkz + 551829875U, // VMOVDQU64Z256rr + 551829875U, // VMOVDQU64Z256rr_REV + 3230695795U, // VMOVDQU64Z256rrk + 3229663603U, // VMOVDQU64Z256rrk_REV + 3229663603U, // VMOVDQU64Z256rrkz + 3229663603U, // VMOVDQU64Z256rrkz_REV + 182485363U, // VMOVDQU64Zmr + 3404005747U, // VMOVDQU64Zmrk + 552436083U, // VMOVDQU64Zrm + 3231089011U, // VMOVDQU64Zrmk + 3230892403U, // VMOVDQU64Zrmkz + 551829875U, // VMOVDQU64Zrr + 551829875U, // VMOVDQU64Zrr_REV + 3230695795U, // VMOVDQU64Zrrk + 3229663603U, // VMOVDQU64Zrrk_REV + 3229663603U, // VMOVDQU64Zrrkz + 3229663603U, // VMOVDQU64Zrrkz_REV + 33587922U, // VMOVDQU8Z128mr + 3255108306U, // VMOVDQU8Z128mrk + 262866U, // VMOVDQU8Z128rm + 3230991058U, // VMOVDQU8Z128rmk + 3229860562U, // VMOVDQU8Z128rmkz + 551830226U, // VMOVDQU8Z128rr + 551830226U, // VMOVDQU8Z128rr_REV + 3230696146U, // VMOVDQU8Z128rrk + 3229663954U, // VMOVDQU8Z128rrk_REV + 3229663954U, // VMOVDQU8Z128rrkz + 3229663954U, // VMOVDQU8Z128rrkz_REV + 180388562U, // VMOVDQU8Z256mr + 3401908946U, // VMOVDQU8Z256mrk + 552944338U, // VMOVDQU8Z256rm + 3231023826U, // VMOVDQU8Z256rmk + 3230876370U, // VMOVDQU8Z256rmkz + 551830226U, // VMOVDQU8Z256rr + 551830226U, // VMOVDQU8Z256rr_REV + 3230696146U, // VMOVDQU8Z256rrk + 3229663954U, // VMOVDQU8Z256rrk_REV + 3229663954U, // VMOVDQU8Z256rrkz + 3229663954U, // VMOVDQU8Z256rrkz_REV + 182485714U, // VMOVDQU8Zmr + 3404006098U, // VMOVDQU8Zmrk + 552436434U, // VMOVDQU8Zrm + 3231089362U, // VMOVDQU8Zrmk + 3230892754U, // VMOVDQU8Zrmkz + 551830226U, // VMOVDQU8Zrr + 551830226U, // VMOVDQU8Zrr_REV + 3230696146U, // VMOVDQU8Zrrk + 3229663954U, // VMOVDQU8Zrrk_REV + 3229663954U, // VMOVDQU8Zrrkz + 3229663954U, // VMOVDQU8Zrrkz_REV + 180398553U, // VMOVDQUYmr + 552954329U, // VMOVDQUYrm + 551840217U, // VMOVDQUYrr + 551840217U, // VMOVDQUYrr_REV + 33597913U, // VMOVDQUmr + 272857U, // VMOVDQUrm + 551840217U, // VMOVDQUrr + 551840217U, // VMOVDQUrr_REV + 811656469U, // VMOVHLPSZrr + 811656469U, // VMOVHLPSrr + 67144675U, // VMOVHPDZ128mr + 283266019U, // VMOVHPDZ128rm + 67144675U, // VMOVHPDmr + 283266019U, // VMOVHPDrm + 67151105U, // VMOVHPSZ128mr + 283272449U, // VMOVHPSZ128rm + 67151105U, // VMOVHPSmr + 283272449U, // VMOVHPSrm + 811656439U, // VMOVLHPSZrr + 811656439U, // VMOVLHPSrr + 67144725U, // VMOVLPDZ128mr + 283266069U, // VMOVLPDZ128rm + 67144725U, // VMOVLPDmr + 283266069U, // VMOVLPDrm + 67151165U, // VMOVLPSZ128mr + 283272509U, // VMOVLPSZ128rm + 67151165U, // VMOVLPSmr + 283272509U, // VMOVLPSrm + 551832556U, // VMOVMSKPDYrr + 551832556U, // VMOVMSKPDrr + 551838986U, // VMOVMSKPSYrr + 551838986U, // VMOVMSKPSrr + 552944444U, // VMOVNTDQAYrm + 262972U, // VMOVNTDQAZ128rm + 552944444U, // VMOVNTDQAZ256rm + 552436540U, // VMOVNTDQAZrm + 262972U, // VMOVNTDQArm + 180394832U, // VMOVNTDQYmr + 33594192U, // VMOVNTDQZ128mr + 180394832U, // VMOVNTDQZ256mr + 182491984U, // VMOVNTDQZmr + 33594192U, // VMOVNTDQmr + 148933902U, // VMOVNTPDYmr + 65047822U, // VMOVNTPDZ128mr + 148933902U, // VMOVNTPDZ256mr + 151031054U, // VMOVNTPDZmr + 65047822U, // VMOVNTPDmr + 148940354U, // VMOVNTPSYmr + 65054274U, // VMOVNTPSZ128mr + 148940354U, // VMOVNTPSZ256mr + 151037506U, // VMOVNTPSZmr + 65054274U, // VMOVNTPSmr + 12620009U, // VMOVPDI2DIZmr + 551833833U, // VMOVPDI2DIZrr + 12620009U, // VMOVPDI2DImr + 551833833U, // VMOVPDI2DIrr + 18915458U, // VMOVPQI2QIZmr + 551837826U, // VMOVPQI2QIZrr + 18915458U, // VMOVPQI2QImr + 551837826U, // VMOVPQI2QIrr + 18915458U, // VMOVPQIto64Zmr + 551837826U, // VMOVPQIto64Zrr + 18915458U, // VMOVPQIto64mr + 551837826U, // VMOVPQIto64rr + 551919746U, // VMOVQI2PQIZrm + 551919746U, // VMOVQI2PQIrm + 67145733U, // VMOVSDZmr + 3288666117U, // VMOVSDZmrk + 552177669U, // VMOVSDZrm + 552603653U, // VMOVSDZrmk + 551702533U, // VMOVSDZrmkz + 811651077U, // VMOVSDZrr + 811651077U, // VMOVSDZrr_REV + 87052293U, // VMOVSDZrrk + 87052293U, // VMOVSDZrrk_REV + 890277893U, // VMOVSDZrrkz + 890277893U, // VMOVSDZrrkz_REV + 67145733U, // VMOVSDmr + 552177669U, // VMOVSDrm + 811651077U, // VMOVSDrr + 811651077U, // VMOVSDrr_REV + 18915458U, // VMOVSDto64Zmr + 551837826U, // VMOVSDto64Zrr + 18915458U, // VMOVSDto64mr + 551837826U, // VMOVSDto64rr + 1349897U, // VMOVSHDUPYrm + 551835913U, // VMOVSHDUPYrr + 661769U, // VMOVSHDUPZ128rm + 3230603529U, // VMOVSHDUPZ128rmk + 3229751561U, // VMOVSHDUPZ128rmkz + 551835913U, // VMOVSHDUPZ128rr + 3230701833U, // VMOVSHDUPZ128rrk + 3229669641U, // VMOVSHDUPZ128rrkz + 1349897U, // VMOVSHDUPZ256rm + 3230734601U, // VMOVSHDUPZ256rmk + 3230636297U, // VMOVSHDUPZ256rmkz + 551835913U, // VMOVSHDUPZ256rr + 3230701833U, // VMOVSHDUPZ256rrk + 3229669641U, // VMOVSHDUPZ256rrkz + 1513737U, // VMOVSHDUPZrm + 3230783753U, // VMOVSHDUPZrmk + 3230750985U, // VMOVSHDUPZrmkz + 551835913U, // VMOVSHDUPZrr + 3230701833U, // VMOVSHDUPZrrk + 3229669641U, // VMOVSHDUPZrrkz + 661769U, // VMOVSHDUPrm + 551835913U, // VMOVSHDUPrr + 1349908U, // VMOVSLDUPYrm + 551835924U, // VMOVSLDUPYrr + 661780U, // VMOVSLDUPZ128rm + 3230603540U, // VMOVSLDUPZ128rmk + 3229751572U, // VMOVSLDUPZ128rmkz + 551835924U, // VMOVSLDUPZ128rr + 3230701844U, // VMOVSLDUPZ128rrk + 3229669652U, // VMOVSLDUPZ128rrkz + 1349908U, // VMOVSLDUPZ256rm + 3230734612U, // VMOVSLDUPZ256rmk + 3230636308U, // VMOVSLDUPZ256rmkz + 551835924U, // VMOVSLDUPZ256rr + 3230701844U, // VMOVSLDUPZ256rrk + 3229669652U, // VMOVSLDUPZ256rrkz + 1513748U, // VMOVSLDUPZrm + 3230783764U, // VMOVSLDUPZrmk + 3230750996U, // VMOVSLDUPZrmkz + 551835924U, // VMOVSLDUPZrr + 3230701844U, // VMOVSLDUPZrrk + 3229669652U, // VMOVSLDUPZrrkz + 661780U, // VMOVSLDUPrm + 551835924U, // VMOVSLDUPrr + 12620009U, // VMOVSS2DIZmr + 551833833U, // VMOVSS2DIZrr + 12620009U, // VMOVSS2DImr + 551833833U, // VMOVSS2DIrr + 69249253U, // VMOVSSZmr + 3290769637U, // VMOVSSZmrk + 552200421U, // VMOVSSZrm + 552806629U, // VMOVSSZrmk + 551725285U, // VMOVSSZrmkz + 811657445U, // VMOVSSZrr + 811657445U, // VMOVSSZrr_REV + 87058661U, // VMOVSSZrrk + 87058661U, // VMOVSSZrrk_REV + 890284261U, // VMOVSSZrrkz + 890284261U, // VMOVSSZrrkz_REV + 69249253U, // VMOVSSmr + 552200421U, // VMOVSSrm + 811657445U, // VMOVSSrr + 811657445U, // VMOVSSrr_REV + 148933930U, // VMOVUPDYmr + 1346858U, // VMOVUPDYrm + 551832874U, // VMOVUPDYrr + 551832874U, // VMOVUPDYrr_REV + 65047850U, // VMOVUPDZ128mr + 3286568234U, // VMOVUPDZ128mrk + 658730U, // VMOVUPDZ128rm + 3230600490U, // VMOVUPDZ128rmk + 3229748522U, // VMOVUPDZ128rmkz + 551832874U, // VMOVUPDZ128rr + 551832874U, // VMOVUPDZ128rr_REV + 3230698794U, // VMOVUPDZ128rrk + 3229666602U, // VMOVUPDZ128rrk_REV + 3229666602U, // VMOVUPDZ128rrkz + 3229666602U, // VMOVUPDZ128rrkz_REV + 148933930U, // VMOVUPDZ256mr + 3370454314U, // VMOVUPDZ256mrk + 1346858U, // VMOVUPDZ256rm + 3230731562U, // VMOVUPDZ256rmk + 3230633258U, // VMOVUPDZ256rmkz + 551832874U, // VMOVUPDZ256rr + 551832874U, // VMOVUPDZ256rr_REV + 3230698794U, // VMOVUPDZ256rrk + 3229666602U, // VMOVUPDZ256rrk_REV + 3229666602U, // VMOVUPDZ256rrkz + 3229666602U, // VMOVUPDZ256rrkz_REV + 151031082U, // VMOVUPDZmr + 3372551466U, // VMOVUPDZmrk + 1510698U, // VMOVUPDZrm + 3230780714U, // VMOVUPDZrmk + 3230747946U, // VMOVUPDZrmkz + 551832874U, // VMOVUPDZrr + 551832874U, // VMOVUPDZrr_REV + 3230698794U, // VMOVUPDZrrk + 3229666602U, // VMOVUPDZrrk_REV + 3229666602U, // VMOVUPDZrrkz + 3229666602U, // VMOVUPDZrrkz_REV + 65047850U, // VMOVUPDmr + 658730U, // VMOVUPDrm + 551832874U, // VMOVUPDrr + 551832874U, // VMOVUPDrr_REV + 148940427U, // VMOVUPSYmr + 1353355U, // VMOVUPSYrm + 551839371U, // VMOVUPSYrr + 551839371U, // VMOVUPSYrr_REV + 65054347U, // VMOVUPSZ128mr + 3286574731U, // VMOVUPSZ128mrk + 665227U, // VMOVUPSZ128rm + 3230606987U, // VMOVUPSZ128rmk + 3229755019U, // VMOVUPSZ128rmkz + 551839371U, // VMOVUPSZ128rr + 551839371U, // VMOVUPSZ128rr_REV + 3230705291U, // VMOVUPSZ128rrk + 3229673099U, // VMOVUPSZ128rrk_REV + 3229673099U, // VMOVUPSZ128rrkz + 3229673099U, // VMOVUPSZ128rrkz_REV + 148940427U, // VMOVUPSZ256mr + 3370460811U, // VMOVUPSZ256mrk + 1353355U, // VMOVUPSZ256rm + 3230738059U, // VMOVUPSZ256rmk + 3230639755U, // VMOVUPSZ256rmkz + 551839371U, // VMOVUPSZ256rr + 551839371U, // VMOVUPSZ256rr_REV + 3230705291U, // VMOVUPSZ256rrk + 3229673099U, // VMOVUPSZ256rrk_REV + 3229673099U, // VMOVUPSZ256rrkz + 3229673099U, // VMOVUPSZ256rrkz_REV + 151037579U, // VMOVUPSZmr + 3372557963U, // VMOVUPSZmrk + 1517195U, // VMOVUPSZrm + 3230787211U, // VMOVUPSZrmk + 3230754443U, // VMOVUPSZrmkz + 551839371U, // VMOVUPSZrr + 551839371U, // VMOVUPSZrr_REV + 3230705291U, // VMOVUPSZrrk + 3229673099U, // VMOVUPSZrrk_REV + 3229673099U, // VMOVUPSZrrkz + 3229673099U, // VMOVUPSZrrkz_REV + 65054347U, // VMOVUPSmr + 665227U, // VMOVUPSrm + 551839371U, // VMOVUPSrr + 551839371U, // VMOVUPSrr_REV + 551837826U, // VMOVZPQILo2PQIZrr + 551837826U, // VMOVZPQILo2PQIrr + 375777904U, // VMPSADBWYrmi + 1088825968U, // VMPSADBWYrri + 325446256U, // VMPSADBWrmi + 1088825968U, // VMPSADBWrri + 444562U, // VMPTRLDm + 453035U, // VMPTRSTm + 12620766U, // VMREAD32mr + 551834590U, // VMREAD32rr + 18913853U, // VMREAD64mr + 551836221U, // VMREAD64rr + 15047U, // VMRESUME + 16043U, // VMRUN32 + 16104U, // VMRUN64 + 16031U, // VMSAVE32 + 16092U, // VMSAVE64 + 812616717U, // VMULPDYrm + 811650061U, // VMULPDYrr + 811731981U, // VMULPDZ128rm + 358763533U, // VMULPDZ128rmb + 1433390093U, // VMULPDZ128rmbk + 1164971021U, // VMULPDZ128rmbkz + 86985741U, // VMULPDZ128rmk + 890178573U, // VMULPDZ128rmkz + 811650061U, // VMULPDZ128rr + 87051277U, // VMULPDZ128rrk + 890276877U, // VMULPDZ128rrkz + 812616717U, // VMULPDZ256rm + 360860685U, // VMULPDZ256rmb + 1435487245U, // VMULPDZ256rmbk + 1167068173U, // VMULPDZ256rmbkz + 87084045U, // VMULPDZ256rmk + 890309645U, // VMULPDZ256rmkz + 811650061U, // VMULPDZ256rr + 87051277U, // VMULPDZ256rrk + 890276877U, // VMULPDZ256rrkz + 812731405U, // VMULPDZrm + 362957837U, // VMULPDZrmb + 1437584397U, // VMULPDZrmbk + 1169165325U, // VMULPDZrmbkz + 87133197U, // VMULPDZrmk + 890358797U, // VMULPDZrmkz + 811650061U, // VMULPDZrr + 812780557U, // VMULPDZrrb + 87182349U, // VMULPDZrrbk + 890407949U, // VMULPDZrrbkz + 87051277U, // VMULPDZrrk + 890276877U, // VMULPDZrrkz + 811731981U, // VMULPDrm + 811650061U, // VMULPDrr + 812623157U, // VMULPSYrm + 811656501U, // VMULPSYrr + 811738421U, // VMULPSZ128rm + 360883509U, // VMULPSZ128rmb + 1435690293U, // VMULPSZ128rmbk + 1167271221U, // VMULPSZ128rmbkz + 86992181U, // VMULPSZ128rmk + 890185013U, // VMULPSZ128rmkz + 811656501U, // VMULPSZ128rr + 87057717U, // VMULPSZ128rrk + 890283317U, // VMULPSZ128rrkz + 812623157U, // VMULPSZ256rm + 362980661U, // VMULPSZ256rmb + 1437787445U, // VMULPSZ256rmbk + 1169368373U, // VMULPSZ256rmbkz + 87090485U, // VMULPSZ256rmk + 890316085U, // VMULPSZ256rmkz + 811656501U, // VMULPSZ256rr + 87057717U, // VMULPSZ256rrk + 890283317U, // VMULPSZ256rrkz + 812737845U, // VMULPSZrm + 365077813U, // VMULPSZrmb + 1439884597U, // VMULPSZrmbk + 1171465525U, // VMULPSZrmbkz + 87139637U, // VMULPSZrmk + 890365237U, // VMULPSZrmkz + 811656501U, // VMULPSZrr + 812786997U, // VMULPSZrrb + 87188789U, // VMULPSZrrbk + 890414389U, // VMULPSZrrbkz + 87057717U, // VMULPSZrrk + 890283317U, // VMULPSZrrkz + 811738421U, // VMULPSrm + 811656501U, // VMULPSrr + 283266897U, // VMULSDZrm + 283266897U, // VMULSDZrm_Int + 1357893457U, // VMULSDZrm_Intk + 1089474385U, // VMULSDZrm_Intkz + 811650897U, // VMULSDZrr + 811650897U, // VMULSDZrr_Int + 87052113U, // VMULSDZrr_Intk + 890277713U, // VMULSDZrr_Intkz + 812781393U, // VMULSDZrrb_Int + 87183185U, // VMULSDZrrb_Intk + 890408785U, // VMULSDZrrb_Intkz + 283266897U, // VMULSDrm + 283266897U, // VMULSDrm_Int + 811650897U, // VMULSDrr + 811650897U, // VMULSDrr_Int + 283289699U, // VMULSSZrm + 283289699U, // VMULSSZrm_Int + 1358096483U, // VMULSSZrm_Intk + 1089677411U, // VMULSSZrm_Intkz + 811657315U, // VMULSSZrr + 811657315U, // VMULSSZrr_Int + 87058531U, // VMULSSZrr_Intk + 890284131U, // VMULSSZrr_Intkz + 812787811U, // VMULSSZrrb_Int + 87189603U, // VMULSSZrrb_Intk + 890415203U, // VMULSSZrrb_Intkz + 283289699U, // VMULSSrm + 283289699U, // VMULSSrm_Int + 811657315U, // VMULSSrr + 811657315U, // VMULSSrr_Int + 551900316U, // VMWRITE32rm + 551834780U, // VMWRITE32rr + 551918617U, // VMWRITE64rm + 551836697U, // VMWRITE64rr + 15099U, // VMXOFF + 448617U, // VMXON + 812616905U, // VORPDYrm + 811650249U, // VORPDYrr + 811732169U, // VORPDZ128rm + 358763721U, // VORPDZ128rmb + 1433390281U, // VORPDZ128rmbk + 1164971209U, // VORPDZ128rmbkz + 86985929U, // VORPDZ128rmk + 890178761U, // VORPDZ128rmkz + 811650249U, // VORPDZ128rr + 87051465U, // VORPDZ128rrk + 890277065U, // VORPDZ128rrkz + 812616905U, // VORPDZ256rm + 360860873U, // VORPDZ256rmb + 1435487433U, // VORPDZ256rmbk + 1167068361U, // VORPDZ256rmbkz + 87084233U, // VORPDZ256rmk + 890309833U, // VORPDZ256rmkz + 811650249U, // VORPDZ256rr + 87051465U, // VORPDZ256rrk + 890277065U, // VORPDZ256rrkz + 812731593U, // VORPDZrm + 362958025U, // VORPDZrmb + 1437584585U, // VORPDZrmbk + 1169165513U, // VORPDZrmbkz + 87133385U, // VORPDZrmk + 890358985U, // VORPDZrmkz + 811650249U, // VORPDZrr + 87051465U, // VORPDZrrk + 890277065U, // VORPDZrrkz + 811732169U, // VORPDrm + 811650249U, // VORPDrr + 812623362U, // VORPSYrm + 811656706U, // VORPSYrr + 811738626U, // VORPSZ128rm + 360883714U, // VORPSZ128rmb + 1435690498U, // VORPSZ128rmbk + 1167271426U, // VORPSZ128rmbkz + 86992386U, // VORPSZ128rmk + 890185218U, // VORPSZ128rmkz + 811656706U, // VORPSZ128rr + 87057922U, // VORPSZ128rrk + 890283522U, // VORPSZ128rrkz + 812623362U, // VORPSZ256rm + 362980866U, // VORPSZ256rmb + 1437787650U, // VORPSZ256rmbk + 1169368578U, // VORPSZ256rmbkz + 87090690U, // VORPSZ256rmk + 890316290U, // VORPSZ256rmkz + 811656706U, // VORPSZ256rr + 87057922U, // VORPSZ256rrk + 890283522U, // VORPSZ256rrkz + 812738050U, // VORPSZrm + 365078018U, // VORPSZrmb + 1439884802U, // VORPSZrmbk + 1171465730U, // VORPSZrmbkz + 87139842U, // VORPSZrmk + 890365442U, // VORPSZrmkz + 811656706U, // VORPSZrr + 87057922U, // VORPSZrrk + 890283522U, // VORPSZrrkz + 811738626U, // VORPSrm + 811656706U, // VORPSrr + 890184091U, // VP4DPWSSDSrm + 86991259U, // VP4DPWSSDSrmk + 89088411U, // VP4DPWSSDSrmkz + 890179506U, // VP4DPWSSDrm + 86986674U, // VP4DPWSSDrmk + 89083826U, // VP4DPWSSDrmkz + 552945056U, // VPABSBYrm + 551830944U, // VPABSBYrr + 263584U, // VPABSBZ128rm + 3230991776U, // VPABSBZ128rmk + 3229861280U, // VPABSBZ128rmkz + 551830944U, // VPABSBZ128rr + 3230696864U, // VPABSBZ128rrk + 3229664672U, // VPABSBZ128rrkz + 552945056U, // VPABSBZ256rm + 3231024544U, // VPABSBZ256rmk + 3230877088U, // VPABSBZ256rmkz + 551830944U, // VPABSBZ256rr + 3230696864U, // VPABSBZ256rrk + 3229664672U, // VPABSBZ256rrkz + 552437152U, // VPABSBZrm + 3231090080U, // VPABSBZrmk + 3230893472U, // VPABSBZrmkz + 551830944U, // VPABSBZrr + 3230696864U, // VPABSBZrrk + 3229664672U, // VPABSBZrrkz + 263584U, // VPABSBrm + 551830944U, // VPABSBrr + 552947397U, // VPABSDYrm + 551833285U, // VPABSDYrr + 265925U, // VPABSDZ128rm + 629493445U, // VPABSDZ128rmb + 630607557U, // VPABSDZ128rmbk + 629231301U, // VPABSDZ128rmbkz + 3230994117U, // VPABSDZ128rmk + 3229863621U, // VPABSDZ128rmkz + 551833285U, // VPABSDZ128rr + 3230699205U, // VPABSDZ128rrk + 3229667013U, // VPABSDZ128rrkz + 552947397U, // VPABSDZ256rm + 631590597U, // VPABSDZ256rmb + 632704709U, // VPABSDZ256rmbk + 631328453U, // VPABSDZ256rmbkz + 3231026885U, // VPABSDZ256rmk + 3230879429U, // VPABSDZ256rmkz + 551833285U, // VPABSDZ256rr + 3230699205U, // VPABSDZ256rrk + 3229667013U, // VPABSDZ256rrkz + 552439493U, // VPABSDZrm + 633687749U, // VPABSDZrmb + 634801861U, // VPABSDZrmbk + 633425605U, // VPABSDZrmbkz + 3231092421U, // VPABSDZrmk + 3230895813U, // VPABSDZrmkz + 551833285U, // VPABSDZrr + 3230699205U, // VPABSDZrrk + 3229667013U, // VPABSDZrrkz + 265925U, // VPABSDrm + 551833285U, // VPABSDrr + 270016U, // VPABSQZ128rm + 627416768U, // VPABSQZ128rmb + 628416192U, // VPABSQZ128rmbk + 627154624U, // VPABSQZ128rmbkz + 3230998208U, // VPABSQZ128rmk + 3229867712U, // VPABSQZ128rmkz + 551837376U, // VPABSQZ128rr + 3230703296U, // VPABSQZ128rrk + 3229671104U, // VPABSQZ128rrkz + 552951488U, // VPABSQZ256rm + 629513920U, // VPABSQZ256rmb + 630513344U, // VPABSQZ256rmbk + 629251776U, // VPABSQZ256rmbkz + 3231030976U, // VPABSQZ256rmk + 3230883520U, // VPABSQZ256rmkz + 551837376U, // VPABSQZ256rr + 3230703296U, // VPABSQZ256rrk + 3229671104U, // VPABSQZ256rrkz + 552443584U, // VPABSQZrm + 631611072U, // VPABSQZrmb + 632610496U, // VPABSQZrmbk + 631348928U, // VPABSQZrmbkz + 3231096512U, // VPABSQZrmk + 3230899904U, // VPABSQZrmkz + 551837376U, // VPABSQZrr + 3230703296U, // VPABSQZrrk + 3229671104U, // VPABSQZrrkz + 552955357U, // VPABSWYrm + 551841245U, // VPABSWYrr + 273885U, // VPABSWZ128rm + 3231002077U, // VPABSWZ128rmk + 3229871581U, // VPABSWZ128rmkz + 551841245U, // VPABSWZ128rr + 3230707165U, // VPABSWZ128rrk + 3229674973U, // VPABSWZ128rrkz + 552955357U, // VPABSWZ256rm + 3231034845U, // VPABSWZ256rmk + 3230887389U, // VPABSWZ256rmkz + 551841245U, // VPABSWZ256rr + 3230707165U, // VPABSWZ256rrk + 3229674973U, // VPABSWZ256rrkz + 552447453U, // VPABSWZrm + 3231100381U, // VPABSWZrmk + 3230903773U, // VPABSWZrmkz + 551841245U, // VPABSWZrr + 3230707165U, // VPABSWZrrk + 3229674973U, // VPABSWZrrkz + 273885U, // VPABSWrm + 551841245U, // VPABSWrr + 812870527U, // VPACKSSDWYrm + 811658111U, // VPACKSSDWYrr + 811854719U, // VPACKSSDWZ128rm + 360803199U, // VPACKSSDWZ128rmb + 1436068735U, // VPACKSSDWZ128rmbk + 1167485823U, // VPACKSSDWZ128rmbkz + 985115519U, // VPACKSSDWZ128rmk + 890579839U, // VPACKSSDWZ128rmkz + 811658111U, // VPACKSSDWZ128rr + 87059327U, // VPACKSSDWZ128rrk + 890284927U, // VPACKSSDWZ128rrkz + 812870527U, // VPACKSSDWZ256rm + 362900351U, // VPACKSSDWZ256rmb + 1438165887U, // VPACKSSDWZ256rmbk + 1169582975U, // VPACKSSDWZ256rmbkz + 985131903U, // VPACKSSDWZ256rmk + 890612607U, // VPACKSSDWZ256rmkz + 811658111U, // VPACKSSDWZ256rr + 87059327U, // VPACKSSDWZ256rrk + 890284927U, // VPACKSSDWZ256rrkz + 812886911U, // VPACKSSDWZrm + 364997503U, // VPACKSSDWZrmb + 1440263039U, // VPACKSSDWZrmbk + 1171680127U, // VPACKSSDWZrmbkz + 985148287U, // VPACKSSDWZrmk + 890678143U, // VPACKSSDWZrmkz + 811658111U, // VPACKSSDWZrr + 87059327U, // VPACKSSDWZrrk + 890284927U, // VPACKSSDWZrrkz + 811854719U, // VPACKSSDWrm + 811658111U, // VPACKSSDWrr + 812861110U, // VPACKSSWBYrm + 811648694U, // VPACKSSWBYrr + 811845302U, // VPACKSSWBZ128rm + 985106102U, // VPACKSSWBZ128rmk + 890570422U, // VPACKSSWBZ128rmkz + 811648694U, // VPACKSSWBZ128rr + 87049910U, // VPACKSSWBZ128rrk + 890275510U, // VPACKSSWBZ128rrkz + 812861110U, // VPACKSSWBZ256rm + 985122486U, // VPACKSSWBZ256rmk + 890603190U, // VPACKSSWBZ256rmkz + 811648694U, // VPACKSSWBZ256rr + 87049910U, // VPACKSSWBZ256rrk + 890275510U, // VPACKSSWBZ256rrkz + 812877494U, // VPACKSSWBZrm + 985138870U, // VPACKSSWBZrmk + 890668726U, // VPACKSSWBZrmkz + 811648694U, // VPACKSSWBZrr + 87049910U, // VPACKSSWBZrrk + 890275510U, // VPACKSSWBZrrkz + 811845302U, // VPACKSSWBrm + 811648694U, // VPACKSSWBrr + 812870538U, // VPACKUSDWYrm + 811658122U, // VPACKUSDWYrr + 811854730U, // VPACKUSDWZ128rm + 360803210U, // VPACKUSDWZ128rmb + 1436068746U, // VPACKUSDWZ128rmbk + 1167485834U, // VPACKUSDWZ128rmbkz + 985115530U, // VPACKUSDWZ128rmk + 890579850U, // VPACKUSDWZ128rmkz + 811658122U, // VPACKUSDWZ128rr + 87059338U, // VPACKUSDWZ128rrk + 890284938U, // VPACKUSDWZ128rrkz + 812870538U, // VPACKUSDWZ256rm + 362900362U, // VPACKUSDWZ256rmb + 1438165898U, // VPACKUSDWZ256rmbk + 1169582986U, // VPACKUSDWZ256rmbkz + 985131914U, // VPACKUSDWZ256rmk + 890612618U, // VPACKUSDWZ256rmkz + 811658122U, // VPACKUSDWZ256rr + 87059338U, // VPACKUSDWZ256rrk + 890284938U, // VPACKUSDWZ256rrkz + 812886922U, // VPACKUSDWZrm + 364997514U, // VPACKUSDWZrmb + 1440263050U, // VPACKUSDWZrmbk + 1171680138U, // VPACKUSDWZrmbkz + 985148298U, // VPACKUSDWZrmk + 890678154U, // VPACKUSDWZrmkz + 811658122U, // VPACKUSDWZrr + 87059338U, // VPACKUSDWZrrk + 890284938U, // VPACKUSDWZrrkz + 811854730U, // VPACKUSDWrm + 811658122U, // VPACKUSDWrr + 812861121U, // VPACKUSWBYrm + 811648705U, // VPACKUSWBYrr + 811845313U, // VPACKUSWBZ128rm + 985106113U, // VPACKUSWBZ128rmk + 890570433U, // VPACKUSWBZ128rmkz + 811648705U, // VPACKUSWBZ128rr + 87049921U, // VPACKUSWBZ128rrk + 890275521U, // VPACKUSWBZ128rrkz + 812861121U, // VPACKUSWBZ256rm + 985122497U, // VPACKUSWBZ256rmk + 890603201U, // VPACKUSWBZ256rmkz + 811648705U, // VPACKUSWBZ256rr + 87049921U, // VPACKUSWBZ256rrk + 890275521U, // VPACKUSWBZ256rrkz + 812877505U, // VPACKUSWBZrm + 985138881U, // VPACKUSWBZrmk + 890668737U, // VPACKUSWBZrmkz + 811648705U, // VPACKUSWBZrr + 87049921U, // VPACKUSWBZrrk + 890275521U, // VPACKUSWBZrrkz + 811845313U, // VPACKUSWBrm + 811648705U, // VPACKUSWBrr + 812860394U, // VPADDBYrm + 811647978U, // VPADDBYrr + 811844586U, // VPADDBZ128rm + 985105386U, // VPADDBZ128rmk + 890569706U, // VPADDBZ128rmkz + 811647978U, // VPADDBZ128rr + 87049194U, // VPADDBZ128rrk + 890274794U, // VPADDBZ128rrkz + 812860394U, // VPADDBZ256rm + 985121770U, // VPADDBZ256rmk + 890602474U, // VPADDBZ256rmkz + 811647978U, // VPADDBZ256rr + 87049194U, // VPADDBZ256rrk + 890274794U, // VPADDBZ256rrkz + 812876778U, // VPADDBZrm + 985138154U, // VPADDBZrmk + 890668010U, // VPADDBZrmkz + 811647978U, // VPADDBZrr + 87049194U, // VPADDBZrrk + 890274794U, // VPADDBZrrkz + 811844586U, // VPADDBrm + 811647978U, // VPADDBrr + 812861372U, // VPADDDYrm + 811648956U, // VPADDDYrr + 811845564U, // VPADDDZ128rm + 360794044U, // VPADDDZ128rmb + 1436059580U, // VPADDDZ128rmbk + 1167476668U, // VPADDDZ128rmbkz + 985106364U, // VPADDDZ128rmk + 890570684U, // VPADDDZ128rmkz + 811648956U, // VPADDDZ128rr + 87050172U, // VPADDDZ128rrk + 890275772U, // VPADDDZ128rrkz + 812861372U, // VPADDDZ256rm + 362891196U, // VPADDDZ256rmb + 1438156732U, // VPADDDZ256rmbk + 1169573820U, // VPADDDZ256rmbkz + 985122748U, // VPADDDZ256rmk + 890603452U, // VPADDDZ256rmkz + 811648956U, // VPADDDZ256rr + 87050172U, // VPADDDZ256rrk + 890275772U, // VPADDDZ256rrkz + 812877756U, // VPADDDZrm + 364988348U, // VPADDDZrmb + 1440253884U, // VPADDDZrmbk + 1171670972U, // VPADDDZrmbkz + 985139132U, // VPADDDZrmk + 890668988U, // VPADDDZrmkz + 811648956U, // VPADDDZrr + 87050172U, // VPADDDZrrk + 890275772U, // VPADDDZrrkz + 811845564U, // VPADDDrm + 811648956U, // VPADDDrr + 812866135U, // VPADDQYrm + 811653719U, // VPADDQYrr + 811850327U, // VPADDQZ128rm + 358718039U, // VPADDQZ128rmb + 1433950807U, // VPADDQZ128rmbk + 1165285975U, // VPADDQZ128rmbkz + 985111127U, // VPADDQZ128rmk + 890575447U, // VPADDQZ128rmkz + 811653719U, // VPADDQZ128rr + 87054935U, // VPADDQZ128rrk + 890280535U, // VPADDQZ128rrkz + 812866135U, // VPADDQZ256rm + 360815191U, // VPADDQZ256rmb + 1436047959U, // VPADDQZ256rmbk + 1167383127U, // VPADDQZ256rmbkz + 985127511U, // VPADDQZ256rmk + 890608215U, // VPADDQZ256rmkz + 811653719U, // VPADDQZ256rr + 87054935U, // VPADDQZ256rrk + 890280535U, // VPADDQZ256rrkz + 812882519U, // VPADDQZrm + 362912343U, // VPADDQZrmb + 1438145111U, // VPADDQZrmbk + 1169480279U, // VPADDQZrmbkz + 985143895U, // VPADDQZrmk + 890673751U, // VPADDQZrmkz + 811653719U, // VPADDQZrr + 87054935U, // VPADDQZrrk + 890280535U, // VPADDQZrrkz + 811850327U, // VPADDQrm + 811653719U, // VPADDQrr + 812860858U, // VPADDSBYrm + 811648442U, // VPADDSBYrr + 811845050U, // VPADDSBZ128rm + 985105850U, // VPADDSBZ128rmk + 890570170U, // VPADDSBZ128rmkz + 811648442U, // VPADDSBZ128rr + 87049658U, // VPADDSBZ128rrk + 890275258U, // VPADDSBZ128rrkz + 812860858U, // VPADDSBZ256rm + 985122234U, // VPADDSBZ256rmk + 890602938U, // VPADDSBZ256rmkz + 811648442U, // VPADDSBZ256rr + 87049658U, // VPADDSBZ256rrk + 890275258U, // VPADDSBZ256rrkz + 812877242U, // VPADDSBZrm + 985138618U, // VPADDSBZrmk + 890668474U, // VPADDSBZrmkz + 811648442U, // VPADDSBZrr + 87049658U, // VPADDSBZrrk + 890275258U, // VPADDSBZrrkz + 811845050U, // VPADDSBrm + 811648442U, // VPADDSBrr + 812871191U, // VPADDSWYrm + 811658775U, // VPADDSWYrr + 811855383U, // VPADDSWZ128rm + 985116183U, // VPADDSWZ128rmk + 890580503U, // VPADDSWZ128rmkz + 811658775U, // VPADDSWZ128rr + 87059991U, // VPADDSWZ128rrk + 890285591U, // VPADDSWZ128rrkz + 812871191U, // VPADDSWZ256rm + 985132567U, // VPADDSWZ256rmk + 890613271U, // VPADDSWZ256rmkz + 811658775U, // VPADDSWZ256rr + 87059991U, // VPADDSWZ256rrk + 890285591U, // VPADDSWZ256rrkz + 812887575U, // VPADDSWZrm + 985148951U, // VPADDSWZrmk + 890678807U, // VPADDSWZrmkz + 811658775U, // VPADDSWZrr + 87059991U, // VPADDSWZrrk + 890285591U, // VPADDSWZrrkz + 811855383U, // VPADDSWrm + 811658775U, // VPADDSWrr + 812860920U, // VPADDUSBYrm + 811648504U, // VPADDUSBYrr + 811845112U, // VPADDUSBZ128rm + 985105912U, // VPADDUSBZ128rmk + 890570232U, // VPADDUSBZ128rmkz + 811648504U, // VPADDUSBZ128rr + 87049720U, // VPADDUSBZ128rrk + 890275320U, // VPADDUSBZ128rrkz + 812860920U, // VPADDUSBZ256rm + 985122296U, // VPADDUSBZ256rmk + 890603000U, // VPADDUSBZ256rmkz + 811648504U, // VPADDUSBZ256rr + 87049720U, // VPADDUSBZ256rrk + 890275320U, // VPADDUSBZ256rrkz + 812877304U, // VPADDUSBZrm + 985138680U, // VPADDUSBZrmk + 890668536U, // VPADDUSBZrmkz + 811648504U, // VPADDUSBZrr + 87049720U, // VPADDUSBZrrk + 890275320U, // VPADDUSBZrrkz + 811845112U, // VPADDUSBrm + 811648504U, // VPADDUSBrr + 812871317U, // VPADDUSWYrm + 811658901U, // VPADDUSWYrr + 811855509U, // VPADDUSWZ128rm + 985116309U, // VPADDUSWZ128rmk + 890580629U, // VPADDUSWZ128rmkz + 811658901U, // VPADDUSWZ128rr + 87060117U, // VPADDUSWZ128rrk + 890285717U, // VPADDUSWZ128rrkz + 812871317U, // VPADDUSWZ256rm + 985132693U, // VPADDUSWZ256rmk + 890613397U, // VPADDUSWZ256rmkz + 811658901U, // VPADDUSWZ256rr + 87060117U, // VPADDUSWZ256rrk + 890285717U, // VPADDUSWZ256rrkz + 812887701U, // VPADDUSWZrm + 985149077U, // VPADDUSWZrmk + 890678933U, // VPADDUSWZrmkz + 811658901U, // VPADDUSWZrr + 87060117U, // VPADDUSWZrrk + 890285717U, // VPADDUSWZrrkz + 811855509U, // VPADDUSWrm + 811658901U, // VPADDUSWrr + 812870448U, // VPADDWYrm + 811658032U, // VPADDWYrr + 811854640U, // VPADDWZ128rm + 985115440U, // VPADDWZ128rmk + 890579760U, // VPADDWZ128rmkz + 811658032U, // VPADDWZ128rr + 87059248U, // VPADDWZ128rrk + 890284848U, // VPADDWZ128rrkz + 812870448U, // VPADDWZ256rm + 985131824U, // VPADDWZ256rmk + 890612528U, // VPADDWZ256rmkz + 811658032U, // VPADDWZ256rr + 87059248U, // VPADDWZ256rrk + 890284848U, // VPADDWZ256rrkz + 812886832U, // VPADDWZrm + 985148208U, // VPADDWZrmk + 890678064U, // VPADDWZrmkz + 811658032U, // VPADDWZrr + 87059248U, // VPADDWZrrk + 890284848U, // VPADDWZrrkz + 811854640U, // VPADDWrm + 811658032U, // VPADDWrr + 375775517U, // VPALIGNRYrmi + 1088823581U, // VPALIGNRYrri + 325443869U, // VPALIGNRZ128rmi + 1983111453U, // VPALIGNRZ128rmik + 1179918621U, // VPALIGNRZ128rmikz + 1088823581U, // VPALIGNRZ128rri + 2163138845U, // VPALIGNRZ128rrik + 1357586717U, // VPALIGNRZ128rrikz + 375775517U, // VPALIGNRZ256rmi + 1989402909U, // VPALIGNRZ256rmik + 1186210077U, // VPALIGNRZ256rmikz + 1088823581U, // VPALIGNRZ256rri + 2163138845U, // VPALIGNRZ256rrik + 1357586717U, // VPALIGNRZ256rrikz + 382066973U, // VPALIGNRZrmi + 1995694365U, // VPALIGNRZrmik + 1192501533U, // VPALIGNRZrmikz + 1088823581U, // VPALIGNRZrri + 2163138845U, // VPALIGNRZrrik + 1357586717U, // VPALIGNRZrrikz + 325443869U, // VPALIGNRrmi + 1088823581U, // VPALIGNRrri + 811845588U, // VPANDDZ128rm + 360794068U, // VPANDDZ128rmb + 1436059604U, // VPANDDZ128rmbk + 1167476692U, // VPANDDZ128rmbkz + 985106388U, // VPANDDZ128rmk + 890570708U, // VPANDDZ128rmkz + 811648980U, // VPANDDZ128rr + 87050196U, // VPANDDZ128rrk + 890275796U, // VPANDDZ128rrkz + 812861396U, // VPANDDZ256rm + 362891220U, // VPANDDZ256rmb + 1438156756U, // VPANDDZ256rmbk + 1169573844U, // VPANDDZ256rmbkz + 985122772U, // VPANDDZ256rmk + 890603476U, // VPANDDZ256rmkz + 811648980U, // VPANDDZ256rr + 87050196U, // VPANDDZ256rrk + 890275796U, // VPANDDZ256rrkz + 812877780U, // VPANDDZrm + 364988372U, // VPANDDZrmb + 1440253908U, // VPANDDZrmbk + 1171670996U, // VPANDDZrmbkz + 985139156U, // VPANDDZrmk + 890669012U, // VPANDDZrmkz + 811648980U, // VPANDDZrr + 87050196U, // VPANDDZrrk + 890275796U, // VPANDDZrrkz + 811845860U, // VPANDNDZ128rm + 360794340U, // VPANDNDZ128rmb + 1436059876U, // VPANDNDZ128rmbk + 1167476964U, // VPANDNDZ128rmbkz + 985106660U, // VPANDNDZ128rmk + 890570980U, // VPANDNDZ128rmkz + 811649252U, // VPANDNDZ128rr + 87050468U, // VPANDNDZ128rrk + 890276068U, // VPANDNDZ128rrkz + 812861668U, // VPANDNDZ256rm + 362891492U, // VPANDNDZ256rmb + 1438157028U, // VPANDNDZ256rmbk + 1169574116U, // VPANDNDZ256rmbkz + 985123044U, // VPANDNDZ256rmk + 890603748U, // VPANDNDZ256rmkz + 811649252U, // VPANDNDZ256rr + 87050468U, // VPANDNDZ256rrk + 890276068U, // VPANDNDZ256rrkz + 812878052U, // VPANDNDZrm + 364988644U, // VPANDNDZrmb + 1440254180U, // VPANDNDZrmbk + 1171671268U, // VPANDNDZrmbkz + 985139428U, // VPANDNDZrmk + 890669284U, // VPANDNDZrmkz + 811649252U, // VPANDNDZrr + 87050468U, // VPANDNDZrrk + 890276068U, // VPANDNDZrrkz + 811851085U, // VPANDNQZ128rm + 358718797U, // VPANDNQZ128rmb + 1433951565U, // VPANDNQZ128rmbk + 1165286733U, // VPANDNQZ128rmbkz + 985111885U, // VPANDNQZ128rmk + 890576205U, // VPANDNQZ128rmkz + 811654477U, // VPANDNQZ128rr + 87055693U, // VPANDNQZ128rrk + 890281293U, // VPANDNQZ128rrkz + 812866893U, // VPANDNQZ256rm + 360815949U, // VPANDNQZ256rmb + 1436048717U, // VPANDNQZ256rmbk + 1167383885U, // VPANDNQZ256rmbkz + 985128269U, // VPANDNQZ256rmk + 890608973U, // VPANDNQZ256rmkz + 811654477U, // VPANDNQZ256rr + 87055693U, // VPANDNQZ256rrk + 890281293U, // VPANDNQZ256rrkz + 812883277U, // VPANDNQZrm + 362913101U, // VPANDNQZrmb + 1438145869U, // VPANDNQZrmbk + 1169481037U, // VPANDNQZrmbkz + 985144653U, // VPANDNQZrmk + 890674509U, // VPANDNQZrmkz + 811654477U, // VPANDNQZrr + 87055693U, // VPANDNQZrrk + 890281293U, // VPANDNQZrrkz + 812865618U, // VPANDNYrm + 811653202U, // VPANDNYrr + 811849810U, // VPANDNrm + 811653202U, // VPANDNrr + 811850438U, // VPANDQZ128rm + 358718150U, // VPANDQZ128rmb + 1433950918U, // VPANDQZ128rmbk + 1165286086U, // VPANDQZ128rmbkz + 985111238U, // VPANDQZ128rmk + 890575558U, // VPANDQZ128rmkz + 811653830U, // VPANDQZ128rr + 87055046U, // VPANDQZ128rrk + 890280646U, // VPANDQZ128rrkz + 812866246U, // VPANDQZ256rm + 360815302U, // VPANDQZ256rmb + 1436048070U, // VPANDQZ256rmbk + 1167383238U, // VPANDQZ256rmbkz + 985127622U, // VPANDQZ256rmk + 890608326U, // VPANDQZ256rmkz + 811653830U, // VPANDQZ256rr + 87055046U, // VPANDQZ256rrk + 890280646U, // VPANDQZ256rrkz + 812882630U, // VPANDQZrm + 362912454U, // VPANDQZrmb + 1438145222U, // VPANDQZrmbk + 1169480390U, // VPANDQZrmbkz + 985144006U, // VPANDQZrmk + 890673862U, // VPANDQZrmkz + 811653830U, // VPANDQZrr + 87055046U, // VPANDQZrrk + 890280646U, // VPANDQZrrkz + 812861653U, // VPANDYrm + 811649237U, // VPANDYrr + 811845845U, // VPANDrm + 811649237U, // VPANDrr + 812860482U, // VPAVGBYrm + 811648066U, // VPAVGBYrr + 811844674U, // VPAVGBZ128rm + 985105474U, // VPAVGBZ128rmk + 890569794U, // VPAVGBZ128rmkz + 811648066U, // VPAVGBZ128rr + 87049282U, // VPAVGBZ128rrk + 890274882U, // VPAVGBZ128rrkz + 812860482U, // VPAVGBZ256rm + 985121858U, // VPAVGBZ256rmk + 890602562U, // VPAVGBZ256rmkz + 811648066U, // VPAVGBZ256rr + 87049282U, // VPAVGBZ256rrk + 890274882U, // VPAVGBZ256rrkz + 812876866U, // VPAVGBZrm + 985138242U, // VPAVGBZrmk + 890668098U, // VPAVGBZrmkz + 811648066U, // VPAVGBZrr + 87049282U, // VPAVGBZrrk + 890274882U, // VPAVGBZrrkz + 811844674U, // VPAVGBrm + 811648066U, // VPAVGBrr + 812870669U, // VPAVGWYrm + 811658253U, // VPAVGWYrr + 811854861U, // VPAVGWZ128rm + 985115661U, // VPAVGWZ128rmk + 890579981U, // VPAVGWZ128rmkz + 811658253U, // VPAVGWZ128rr + 87059469U, // VPAVGWZ128rrk + 890285069U, // VPAVGWZ128rrkz + 812870669U, // VPAVGWZ256rm + 985132045U, // VPAVGWZ256rmk + 890612749U, // VPAVGWZ256rmkz + 811658253U, // VPAVGWZ256rr + 87059469U, // VPAVGWZ256rrk + 890285069U, // VPAVGWZ256rrkz + 812887053U, // VPAVGWZrm + 985148429U, // VPAVGWZrmk + 890678285U, // VPAVGWZrmkz + 811658253U, // VPAVGWZrr + 87059469U, // VPAVGWZrrk + 890285069U, // VPAVGWZrrkz + 811854861U, // VPAVGWrm + 811658253U, // VPAVGWrr + 375769063U, // VPBLENDDYrmi + 1088817127U, // VPBLENDDYrri + 325437415U, // VPBLENDDrmi + 1088817127U, // VPBLENDDrri + 811844752U, // VPBLENDMBZ128rm + 890569872U, // VPBLENDMBZ128rmk + 890569872U, // VPBLENDMBZ128rmkz + 811648144U, // VPBLENDMBZ128rr + 890274960U, // VPBLENDMBZ128rrk + 890274960U, // VPBLENDMBZ128rrkz + 812860560U, // VPBLENDMBZ256rm + 890602640U, // VPBLENDMBZ256rmk + 890602640U, // VPBLENDMBZ256rmkz + 811648144U, // VPBLENDMBZ256rr + 890274960U, // VPBLENDMBZ256rrk + 890274960U, // VPBLENDMBZ256rrkz + 812876944U, // VPBLENDMBZrm + 890668176U, // VPBLENDMBZrmk + 890668176U, // VPBLENDMBZrmkz + 811648144U, // VPBLENDMBZrr + 890274960U, // VPBLENDMBZrrk + 890274960U, // VPBLENDMBZrrkz + 811845797U, // VPBLENDMDZ128rm + 360794277U, // VPBLENDMDZ128rmb + 1167476901U, // VPBLENDMDZ128rmbk + 1167476901U, // VPBLENDMDZ128rmbkz + 890570917U, // VPBLENDMDZ128rmk + 890570917U, // VPBLENDMDZ128rmkz + 811649189U, // VPBLENDMDZ128rr + 890276005U, // VPBLENDMDZ128rrk + 890276005U, // VPBLENDMDZ128rrkz + 812861605U, // VPBLENDMDZ256rm + 362891429U, // VPBLENDMDZ256rmb + 1169574053U, // VPBLENDMDZ256rmbk + 1169574053U, // VPBLENDMDZ256rmbkz + 890603685U, // VPBLENDMDZ256rmk + 890603685U, // VPBLENDMDZ256rmkz + 811649189U, // VPBLENDMDZ256rr + 890276005U, // VPBLENDMDZ256rrk + 890276005U, // VPBLENDMDZ256rrkz + 812877989U, // VPBLENDMDZrm + 364988581U, // VPBLENDMDZrmb + 1171671205U, // VPBLENDMDZrmbk + 1171671205U, // VPBLENDMDZrmbkz + 890669221U, // VPBLENDMDZrmk + 890669221U, // VPBLENDMDZrmkz + 811649189U, // VPBLENDMDZrr + 890276005U, // VPBLENDMDZrrk + 890276005U, // VPBLENDMDZrrkz + 811851029U, // VPBLENDMQZ128rm + 358718741U, // VPBLENDMQZ128rmb + 1165286677U, // VPBLENDMQZ128rmbk + 1165286677U, // VPBLENDMQZ128rmbkz + 890576149U, // VPBLENDMQZ128rmk + 890576149U, // VPBLENDMQZ128rmkz + 811654421U, // VPBLENDMQZ128rr + 890281237U, // VPBLENDMQZ128rrk + 890281237U, // VPBLENDMQZ128rrkz + 812866837U, // VPBLENDMQZ256rm + 360815893U, // VPBLENDMQZ256rmb + 1167383829U, // VPBLENDMQZ256rmbk + 1167383829U, // VPBLENDMQZ256rmbkz + 890608917U, // VPBLENDMQZ256rmk + 890608917U, // VPBLENDMQZ256rmkz + 811654421U, // VPBLENDMQZ256rr + 890281237U, // VPBLENDMQZ256rrk + 890281237U, // VPBLENDMQZ256rrkz + 812883221U, // VPBLENDMQZrm + 362913045U, // VPBLENDMQZrmb + 1169480981U, // VPBLENDMQZrmbk + 1169480981U, // VPBLENDMQZrmbkz + 890674453U, // VPBLENDMQZrmk + 890674453U, // VPBLENDMQZrmkz + 811654421U, // VPBLENDMQZrr + 890281237U, // VPBLENDMQZrrk + 890281237U, // VPBLENDMQZrrkz + 811855021U, // VPBLENDMWZ128rm + 890580141U, // VPBLENDMWZ128rmk + 890580141U, // VPBLENDMWZ128rmkz + 811658413U, // VPBLENDMWZ128rr + 890285229U, // VPBLENDMWZ128rrk + 890285229U, // VPBLENDMWZ128rrkz + 812870829U, // VPBLENDMWZ256rm + 890612909U, // VPBLENDMWZ256rmk + 890612909U, // VPBLENDMWZ256rmkz + 811658413U, // VPBLENDMWZ256rr + 890285229U, // VPBLENDMWZ256rrk + 890285229U, // VPBLENDMWZ256rrkz + 812887213U, // VPBLENDMWZrm + 890678445U, // VPBLENDMWZrmk + 890678445U, // VPBLENDMWZrmkz + 811658413U, // VPBLENDMWZrr + 890285229U, // VPBLENDMWZrrk + 890285229U, // VPBLENDMWZrrkz + 376718991U, // VPBLENDVBYrm + 890275471U, // VPBLENDVBYrr + 326387343U, // VPBLENDVBrm + 890275471U, // VPBLENDVBrr + 375778156U, // VPBLENDWYrmi + 1088826220U, // VPBLENDWYrri + 325446508U, // VPBLENDWrmi + 1088826220U, // VPBLENDWrri + 493124U, // VPBROADCASTBYrm + 551831108U, // VPBROADCASTBYrr + 493124U, // VPBROADCASTBZ128m + 1623620U, // VPBROADCASTBZ128mk + 3229730372U, // VPBROADCASTBZ128mkz + 551831108U, // VPBROADCASTBZ128r + 3230697028U, // VPBROADCASTBZ128rk + 3229664836U, // VPBROADCASTBZ128rkz + 493124U, // VPBROADCASTBZ256m + 1623620U, // VPBROADCASTBZ256mk + 3229730372U, // VPBROADCASTBZ256mkz + 551831108U, // VPBROADCASTBZ256r + 3230697028U, // VPBROADCASTBZ256rk + 3229664836U, // VPBROADCASTBZ256rkz + 493124U, // VPBROADCASTBZm + 1623620U, // VPBROADCASTBZmk + 3229730372U, // VPBROADCASTBZmkz + 551831108U, // VPBROADCASTBZr + 3230697028U, // VPBROADCASTBZrk + 3229664836U, // VPBROADCASTBZrkz + 551831108U, // VPBROADCASTBrZ128r + 3230697028U, // VPBROADCASTBrZ128rk + 3229664836U, // VPBROADCASTBrZ128rkz + 551831108U, // VPBROADCASTBrZ256r + 3230697028U, // VPBROADCASTBrZ256rk + 3229664836U, // VPBROADCASTBrZ256rkz + 551831108U, // VPBROADCASTBrZr + 3230697028U, // VPBROADCASTBrZrk + 3229664836U, // VPBROADCASTBrZrkz + 493124U, // VPBROADCASTBrm + 551831108U, // VPBROADCASTBrr + 551899233U, // VPBROADCASTDYrm + 551833697U, // VPBROADCASTDYrr + 551899233U, // VPBROADCASTDZ128m + 553013345U, // VPBROADCASTDZ128mk + 551637089U, // VPBROADCASTDZ128mkz + 551833697U, // VPBROADCASTDZ128r + 3230699617U, // VPBROADCASTDZ128rk + 3229667425U, // VPBROADCASTDZ128rkz + 551899233U, // VPBROADCASTDZ256m + 553013345U, // VPBROADCASTDZ256mk + 551637089U, // VPBROADCASTDZ256mkz + 551833697U, // VPBROADCASTDZ256r + 3230699617U, // VPBROADCASTDZ256rk + 3229667425U, // VPBROADCASTDZ256rkz + 551899233U, // VPBROADCASTDZm + 553013345U, // VPBROADCASTDZmk + 551637089U, // VPBROADCASTDZmkz + 551833697U, // VPBROADCASTDZr + 3230699617U, // VPBROADCASTDZrk + 3229667425U, // VPBROADCASTDZrkz + 551833697U, // VPBROADCASTDrZ128r + 3230699617U, // VPBROADCASTDrZ128rk + 3229667425U, // VPBROADCASTDrZ128rkz + 551833697U, // VPBROADCASTDrZ256r + 3230699617U, // VPBROADCASTDrZ256rk + 3229667425U, // VPBROADCASTDrZ256rkz + 551833697U, // VPBROADCASTDrZr + 3230699617U, // VPBROADCASTDrZrk + 3229667425U, // VPBROADCASTDrZrkz + 551899233U, // VPBROADCASTDrm + 551833697U, // VPBROADCASTDrr + 551835950U, // VPBROADCASTMB2QZ128rr + 551835950U, // VPBROADCASTMB2QZ256rr + 551835950U, // VPBROADCASTMB2QZrr + 551831363U, // VPBROADCASTMW2DZ128rr + 551831363U, // VPBROADCASTMW2DZ256rr + 551831363U, // VPBROADCASTMW2DZrr + 551919570U, // VPBROADCASTQYrm + 551837650U, // VPBROADCASTQYrr + 551919570U, // VPBROADCASTQZ128m + 552918994U, // VPBROADCASTQZ128mk + 551657426U, // VPBROADCASTQZ128mkz + 551837650U, // VPBROADCASTQZ128r + 3230703570U, // VPBROADCASTQZ128rk + 3229671378U, // VPBROADCASTQZ128rkz + 551919570U, // VPBROADCASTQZ256m + 552918994U, // VPBROADCASTQZ256mk + 551657426U, // VPBROADCASTQZ256mkz + 551837650U, // VPBROADCASTQZ256r + 3230703570U, // VPBROADCASTQZ256rk + 3229671378U, // VPBROADCASTQZ256rkz + 551919570U, // VPBROADCASTQZm + 552918994U, // VPBROADCASTQZmk + 551657426U, // VPBROADCASTQZmkz + 551837650U, // VPBROADCASTQZr + 3230703570U, // VPBROADCASTQZrk + 3229671378U, // VPBROADCASTQZrkz + 551837650U, // VPBROADCASTQrZ128r + 3230703570U, // VPBROADCASTQrZ128rk + 3229671378U, // VPBROADCASTQrZ128rkz + 551837650U, // VPBROADCASTQrZ256r + 3230703570U, // VPBROADCASTQrZ256rk + 3229671378U, // VPBROADCASTQrZ256rkz + 551837650U, // VPBROADCASTQrZr + 3230703570U, // VPBROADCASTQrZrk + 3229671378U, // VPBROADCASTQrZrkz + 551919570U, // VPBROADCASTQrm + 551837650U, // VPBROADCASTQrr + 438041U, // VPBROADCASTWYrm + 551841561U, // VPBROADCASTWYrr + 438041U, // VPBROADCASTWZ128m + 1650457U, // VPBROADCASTWZ128mk + 3229691673U, // VPBROADCASTWZ128mkz + 551841561U, // VPBROADCASTWZ128r + 3230707481U, // VPBROADCASTWZ128rk + 3229675289U, // VPBROADCASTWZ128rkz + 438041U, // VPBROADCASTWZ256m + 1650457U, // VPBROADCASTWZ256mk + 3229691673U, // VPBROADCASTWZ256mkz + 551841561U, // VPBROADCASTWZ256r + 3230707481U, // VPBROADCASTWZ256rk + 3229675289U, // VPBROADCASTWZ256rkz + 438041U, // VPBROADCASTWZm + 1650457U, // VPBROADCASTWZmk + 3229691673U, // VPBROADCASTWZmkz + 551841561U, // VPBROADCASTWZr + 3230707481U, // VPBROADCASTWZrk + 3229675289U, // VPBROADCASTWZrkz + 551841561U, // VPBROADCASTWrZ128r + 3230707481U, // VPBROADCASTWrZ128rk + 3229675289U, // VPBROADCASTWrZ128rkz + 551841561U, // VPBROADCASTWrZ256r + 3230707481U, // VPBROADCASTWrZ256rk + 3229675289U, // VPBROADCASTWrZ256rkz + 551841561U, // VPBROADCASTWrZr + 3230707481U, // VPBROADCASTWrZrk + 3229675289U, // VPBROADCASTWrZrkz + 438041U, // VPBROADCASTWrm + 551841561U, // VPBROADCASTWrr + 375773961U, // VPCLMULQDQYrm + 1088822025U, // VPCLMULQDQYrr + 325442313U, // VPCLMULQDQZ128rm + 1088822025U, // VPCLMULQDQZ128rr + 375773961U, // VPCLMULQDQZ256rm + 1088822025U, // VPCLMULQDQZ256rr + 382065417U, // VPCLMULQDQZrm + 1088822025U, // VPCLMULQDQZrr + 325442313U, // VPCLMULQDQrm + 1088822025U, // VPCLMULQDQrr + 376728065U, // VPCMOVYrmr + 890612225U, // VPCMOVYrrm + 890284545U, // VPCMOVYrrr + 890284545U, // VPCMOVYrrr_REV + 326396417U, // VPCMOVrmr + 890579457U, // VPCMOVrrm + 890284545U, // VPCMOVrrr + 890284545U, // VPCMOVrrr_REV + 2869427203U, // VPCMPBZ128rmi + 325436653U, // VPCMPBZ128rmi_alt + 3138780163U, // VPCMPBZ128rmik + 1179911405U, // VPCMPBZ128rmik_alt + 1258830851U, // VPCMPBZ128rri + 1088816365U, // VPCMPBZ128rri_alt + 1528183811U, // VPCMPBZ128rrik + 1357579501U, // VPCMPBZ128rrik_alt + 3406298115U, // VPCMPBZ256rmi + 375768301U, // VPCMPBZ256rmi_alt + 3675651075U, // VPCMPBZ256rmik + 1186202861U, // VPCMPBZ256rmik_alt + 1258830851U, // VPCMPBZ256rri + 1088816365U, // VPCMPBZ256rri_alt + 1528183811U, // VPCMPBZ256rrik + 1357579501U, // VPCMPBZ256rrik_alt + 3943169027U, // VPCMPBZrmi + 382059757U, // VPCMPBZrmi_alt + 4212521987U, // VPCMPBZrmik + 1192494317U, // VPCMPBZrmik_alt + 1258830851U, // VPCMPBZrri + 1088816365U, // VPCMPBZrri_alt + 1528183811U, // VPCMPBZrrik + 1357579501U, // VPCMPBZrrik_alt + 2871524355U, // VPCMPDZ128rmi + 325438494U, // VPCMPDZ128rmi_alt + 187169795U, // VPCMPDZ128rmib + 1686490142U, // VPCMPDZ128rmib_alt + 456522755U, // VPCMPDZ128rmibk + 1712589854U, // VPCMPDZ128rmibk_alt + 3140877315U, // VPCMPDZ128rmik + 1179913246U, // VPCMPDZ128rmik_alt + 1260928003U, // VPCMPDZ128rri + 1088818206U, // VPCMPDZ128rri_alt + 1530280963U, // VPCMPDZ128rrik + 1357581342U, // VPCMPDZ128rrik_alt + 3408395267U, // VPCMPDZ256rmi + 375770142U, // VPCMPDZ256rmi_alt + 187169795U, // VPCMPDZ256rmib + 2491796510U, // VPCMPDZ256rmib_alt + 456522755U, // VPCMPDZ256rmibk + 2517896222U, // VPCMPDZ256rmibk_alt + 3677748227U, // VPCMPDZ256rmik + 1186204702U, // VPCMPDZ256rmik_alt + 1260928003U, // VPCMPDZ256rri + 1088818206U, // VPCMPDZ256rri_alt + 1530280963U, // VPCMPDZ256rrik + 1357581342U, // VPCMPDZ256rrik_alt + 3945266179U, // VPCMPDZrmi + 382061598U, // VPCMPDZrmi_alt + 187169795U, // VPCMPDZrmib + 2760231966U, // VPCMPDZrmib_alt + 456522755U, // VPCMPDZrmibk + 2786331678U, // VPCMPDZrmibk_alt + 4214619139U, // VPCMPDZrmik + 1192496158U, // VPCMPDZrmik_alt + 1260928003U, // VPCMPDZrri + 1088818206U, // VPCMPDZrri_alt + 1530280963U, // VPCMPDZrrik + 1357581342U, // VPCMPDZrrik_alt + 812860677U, // VPCMPEQBYrm + 811648261U, // VPCMPEQBYrr + 811844869U, // VPCMPEQBZ128rm + 890569989U, // VPCMPEQBZ128rmk + 811648261U, // VPCMPEQBZ128rr + 890275077U, // VPCMPEQBZ128rrk + 812860677U, // VPCMPEQBZ256rm + 890602757U, // VPCMPEQBZ256rmk + 811648261U, // VPCMPEQBZ256rr + 890275077U, // VPCMPEQBZ256rrk + 812877061U, // VPCMPEQBZrm + 890668293U, // VPCMPEQBZrmk + 811648261U, // VPCMPEQBZrr + 890275077U, // VPCMPEQBZrrk + 811844869U, // VPCMPEQBrm + 811648261U, // VPCMPEQBrr + 812862819U, // VPCMPEQDYrm + 811650403U, // VPCMPEQDYrr + 811847011U, // VPCMPEQDZ128rm + 360795491U, // VPCMPEQDZ128rmb + 1167478115U, // VPCMPEQDZ128rmbk + 890572131U, // VPCMPEQDZ128rmk + 811650403U, // VPCMPEQDZ128rr + 890277219U, // VPCMPEQDZ128rrk + 812862819U, // VPCMPEQDZ256rm + 362892643U, // VPCMPEQDZ256rmb + 1169575267U, // VPCMPEQDZ256rmbk + 890604899U, // VPCMPEQDZ256rmk + 811650403U, // VPCMPEQDZ256rr + 890277219U, // VPCMPEQDZ256rrk + 812879203U, // VPCMPEQDZrm + 364989795U, // VPCMPEQDZrmb + 1171672419U, // VPCMPEQDZrmbk + 890670435U, // VPCMPEQDZrmk + 811650403U, // VPCMPEQDZrr + 890277219U, // VPCMPEQDZrrk + 811847011U, // VPCMPEQDrm + 811650403U, // VPCMPEQDrr + 812867043U, // VPCMPEQQYrm + 811654627U, // VPCMPEQQYrr + 811851235U, // VPCMPEQQZ128rm + 358718947U, // VPCMPEQQZ128rmb + 1165286883U, // VPCMPEQQZ128rmbk + 890576355U, // VPCMPEQQZ128rmk + 811654627U, // VPCMPEQQZ128rr + 890281443U, // VPCMPEQQZ128rrk + 812867043U, // VPCMPEQQZ256rm + 360816099U, // VPCMPEQQZ256rmb + 1167384035U, // VPCMPEQQZ256rmbk + 890609123U, // VPCMPEQQZ256rmk + 811654627U, // VPCMPEQQZ256rr + 890281443U, // VPCMPEQQZ256rrk + 812883427U, // VPCMPEQQZrm + 362913251U, // VPCMPEQQZrmb + 1169481187U, // VPCMPEQQZrmbk + 890674659U, // VPCMPEQQZrmk + 811654627U, // VPCMPEQQZrr + 890281443U, // VPCMPEQQZrrk + 811851235U, // VPCMPEQQrm + 811654627U, // VPCMPEQQrr + 812870968U, // VPCMPEQWYrm + 811658552U, // VPCMPEQWYrr + 811855160U, // VPCMPEQWZ128rm + 890580280U, // VPCMPEQWZ128rmk + 811658552U, // VPCMPEQWZ128rr + 890285368U, // VPCMPEQWZ128rrk + 812870968U, // VPCMPEQWZ256rm + 890613048U, // VPCMPEQWZ256rmk + 811658552U, // VPCMPEQWZ256rr + 890285368U, // VPCMPEQWZ256rrk + 812887352U, // VPCMPEQWZrm + 890678584U, // VPCMPEQWZrmk + 811658552U, // VPCMPEQWZrr + 890285368U, // VPCMPEQWZrrk + 811855160U, // VPCMPEQWrm + 811658552U, // VPCMPEQWrr + 830771932U, // VPCMPESTRIrm + 283431644U, // VPCMPESTRIrr + 830773299U, // VPCMPESTRMrm + 283433011U, // VPCMPESTRMrr + 812860961U, // VPCMPGTBYrm + 811648545U, // VPCMPGTBYrr + 811845153U, // VPCMPGTBZ128rm + 890570273U, // VPCMPGTBZ128rmk + 811648545U, // VPCMPGTBZ128rr + 890275361U, // VPCMPGTBZ128rrk + 812860961U, // VPCMPGTBZ256rm + 890603041U, // VPCMPGTBZ256rmk + 811648545U, // VPCMPGTBZ256rr + 890275361U, // VPCMPGTBZ256rrk + 812877345U, // VPCMPGTBZrm + 890668577U, // VPCMPGTBZrmk + 811648545U, // VPCMPGTBZrr + 890275361U, // VPCMPGTBZrrk + 811845153U, // VPCMPGTBrm + 811648545U, // VPCMPGTBrr + 812863540U, // VPCMPGTDYrm + 811651124U, // VPCMPGTDYrr + 811847732U, // VPCMPGTDZ128rm + 360796212U, // VPCMPGTDZ128rmb + 1167478836U, // VPCMPGTDZ128rmbk + 890572852U, // VPCMPGTDZ128rmk + 811651124U, // VPCMPGTDZ128rr + 890277940U, // VPCMPGTDZ128rrk + 812863540U, // VPCMPGTDZ256rm + 362893364U, // VPCMPGTDZ256rmb + 1169575988U, // VPCMPGTDZ256rmbk + 890605620U, // VPCMPGTDZ256rmk + 811651124U, // VPCMPGTDZ256rr + 890277940U, // VPCMPGTDZ256rrk + 812879924U, // VPCMPGTDZrm + 364990516U, // VPCMPGTDZrmb + 1171673140U, // VPCMPGTDZrmbk + 890671156U, // VPCMPGTDZrmk + 811651124U, // VPCMPGTDZrr + 890277940U, // VPCMPGTDZrrk + 811847732U, // VPCMPGTDrm + 811651124U, // VPCMPGTDrr + 812867468U, // VPCMPGTQYrm + 811655052U, // VPCMPGTQYrr + 811851660U, // VPCMPGTQZ128rm + 358719372U, // VPCMPGTQZ128rmb + 1165287308U, // VPCMPGTQZ128rmbk + 890576780U, // VPCMPGTQZ128rmk + 811655052U, // VPCMPGTQZ128rr + 890281868U, // VPCMPGTQZ128rrk + 812867468U, // VPCMPGTQZ256rm + 360816524U, // VPCMPGTQZ256rmb + 1167384460U, // VPCMPGTQZ256rmbk + 890609548U, // VPCMPGTQZ256rmk + 811655052U, // VPCMPGTQZ256rr + 890281868U, // VPCMPGTQZ256rrk + 812883852U, // VPCMPGTQZrm + 362913676U, // VPCMPGTQZrmb + 1169481612U, // VPCMPGTQZrmbk + 890675084U, // VPCMPGTQZrmk + 811655052U, // VPCMPGTQZrr + 890281868U, // VPCMPGTQZrrk + 811851660U, // VPCMPGTQrm + 811655052U, // VPCMPGTQrr + 812871398U, // VPCMPGTWYrm + 811658982U, // VPCMPGTWYrr + 811855590U, // VPCMPGTWZ128rm + 890580710U, // VPCMPGTWZ128rmk + 811658982U, // VPCMPGTWZ128rr + 890285798U, // VPCMPGTWZ128rrk + 812871398U, // VPCMPGTWZ256rm + 890613478U, // VPCMPGTWZ256rmk + 811658982U, // VPCMPGTWZ256rr + 890285798U, // VPCMPGTWZ256rrk + 812887782U, // VPCMPGTWZrm + 890679014U, // VPCMPGTWZrmk + 811658982U, // VPCMPGTWZrr + 890285798U, // VPCMPGTWZrrk + 811855590U, // VPCMPGTWrm + 811658982U, // VPCMPGTWrr + 830771944U, // VPCMPISTRIrm + 283431656U, // VPCMPISTRIrr + 830773311U, // VPCMPISTRMrm + 283433023U, // VPCMPISTRMrr + 2873621507U, // VPCMPQZ128rmi + 325442943U, // VPCMPQZ128rmi_alt + 726137859U, // VPCMPQZ128rmib + 3013991807U, // VPCMPQZ128rmib_alt + 995490819U, // VPCMPQZ128rmibk + 3075743103U, // VPCMPQZ128rmibk_alt + 3142974467U, // VPCMPQZ128rmik + 1179917695U, // VPCMPQZ128rmik_alt + 1263025155U, // VPCMPQZ128rri + 1088822655U, // VPCMPQZ128rri_alt + 1532378115U, // VPCMPQZ128rrik + 1357585791U, // VPCMPQZ128rrik_alt + 3410492419U, // VPCMPQZ256rmi + 375774591U, // VPCMPQZ256rmi_alt + 726137859U, // VPCMPQZ256rmib + 1671814527U, // VPCMPQZ256rmib_alt + 995490819U, // VPCMPQZ256rmibk + 1733565823U, // VPCMPQZ256rmibk_alt + 3679845379U, // VPCMPQZ256rmik + 1186209151U, // VPCMPQZ256rmik_alt + 1263025155U, // VPCMPQZ256rri + 1088822655U, // VPCMPQZ256rri_alt + 1532378115U, // VPCMPQZ256rrik + 1357585791U, // VPCMPQZ256rrik_alt + 3947363331U, // VPCMPQZrmi + 382066047U, // VPCMPQZrmi_alt + 726137859U, // VPCMPQZrmib + 2477120895U, // VPCMPQZrmib_alt + 995490819U, // VPCMPQZrmibk + 2538872191U, // VPCMPQZrmibk_alt + 4216716291U, // VPCMPQZrmik + 1192500607U, // VPCMPQZrmik_alt + 1263025155U, // VPCMPQZrri + 1088822655U, // VPCMPQZrri_alt + 1532378115U, // VPCMPQZrrik + 1357585791U, // VPCMPQZrrik_alt + 2875718659U, // VPCMPUBZ128rmi + 325437046U, // VPCMPUBZ128rmi_alt + 3145071619U, // VPCMPUBZ128rmik + 1179911798U, // VPCMPUBZ128rmik_alt + 1265122307U, // VPCMPUBZ128rri + 1088816758U, // VPCMPUBZ128rri_alt + 1534475267U, // VPCMPUBZ128rrik + 1357579894U, // VPCMPUBZ128rrik_alt + 3412589571U, // VPCMPUBZ256rmi + 375768694U, // VPCMPUBZ256rmi_alt + 3681942531U, // VPCMPUBZ256rmik + 1186203254U, // VPCMPUBZ256rmik_alt + 1265122307U, // VPCMPUBZ256rri + 1088816758U, // VPCMPUBZ256rri_alt + 1534475267U, // VPCMPUBZ256rrik + 1357579894U, // VPCMPUBZ256rrik_alt + 3949460483U, // VPCMPUBZrmi + 382060150U, // VPCMPUBZrmi_alt + 4218813443U, // VPCMPUBZrmik + 1192494710U, // VPCMPUBZrmik_alt + 1265122307U, // VPCMPUBZrri + 1088816758U, // VPCMPUBZrri_alt + 1534475267U, // VPCMPUBZrrik + 1357579894U, // VPCMPUBZrrik_alt + 2877815811U, // VPCMPUDZ128rmi + 325439635U, // VPCMPUDZ128rmi_alt + 193461251U, // VPCMPUDZ128rmib + 1686491283U, // VPCMPUDZ128rmib_alt + 462814211U, // VPCMPUDZ128rmibk + 1712590995U, // VPCMPUDZ128rmibk_alt + 3147168771U, // VPCMPUDZ128rmik + 1179914387U, // VPCMPUDZ128rmik_alt + 1267219459U, // VPCMPUDZ128rri + 1088819347U, // VPCMPUDZ128rri_alt + 1536572419U, // VPCMPUDZ128rrik + 1357582483U, // VPCMPUDZ128rrik_alt + 3414686723U, // VPCMPUDZ256rmi + 375771283U, // VPCMPUDZ256rmi_alt + 193461251U, // VPCMPUDZ256rmib + 2491797651U, // VPCMPUDZ256rmib_alt + 462814211U, // VPCMPUDZ256rmibk + 2517897363U, // VPCMPUDZ256rmibk_alt + 3684039683U, // VPCMPUDZ256rmik + 1186205843U, // VPCMPUDZ256rmik_alt + 1267219459U, // VPCMPUDZ256rri + 1088819347U, // VPCMPUDZ256rri_alt + 1536572419U, // VPCMPUDZ256rrik + 1357582483U, // VPCMPUDZ256rrik_alt + 3951557635U, // VPCMPUDZrmi + 382062739U, // VPCMPUDZrmi_alt + 193461251U, // VPCMPUDZrmib + 2760233107U, // VPCMPUDZrmib_alt + 462814211U, // VPCMPUDZrmibk + 2786332819U, // VPCMPUDZrmibk_alt + 4220910595U, // VPCMPUDZrmik + 1192497299U, // VPCMPUDZrmik_alt + 1267219459U, // VPCMPUDZrri + 1088819347U, // VPCMPUDZrri_alt + 1536572419U, // VPCMPUDZrrik + 1357582483U, // VPCMPUDZrrik_alt + 2879912963U, // VPCMPUQZ128rmi + 325443621U, // VPCMPUQZ128rmi_alt + 732429315U, // VPCMPUQZ128rmib + 3013992485U, // VPCMPUQZ128rmib_alt + 1001782275U, // VPCMPUQZ128rmibk + 3075743781U, // VPCMPUQZ128rmibk_alt + 3149265923U, // VPCMPUQZ128rmik + 1179918373U, // VPCMPUQZ128rmik_alt + 1269316611U, // VPCMPUQZ128rri + 1088823333U, // VPCMPUQZ128rri_alt + 1538669571U, // VPCMPUQZ128rrik + 1357586469U, // VPCMPUQZ128rrik_alt + 3416783875U, // VPCMPUQZ256rmi + 375775269U, // VPCMPUQZ256rmi_alt + 732429315U, // VPCMPUQZ256rmib + 1671815205U, // VPCMPUQZ256rmib_alt + 1001782275U, // VPCMPUQZ256rmibk + 1733566501U, // VPCMPUQZ256rmibk_alt + 3686136835U, // VPCMPUQZ256rmik + 1186209829U, // VPCMPUQZ256rmik_alt + 1269316611U, // VPCMPUQZ256rri + 1088823333U, // VPCMPUQZ256rri_alt + 1538669571U, // VPCMPUQZ256rrik + 1357586469U, // VPCMPUQZ256rrik_alt + 3953654787U, // VPCMPUQZrmi + 382066725U, // VPCMPUQZrmi_alt + 732429315U, // VPCMPUQZrmib + 2477121573U, // VPCMPUQZrmib_alt + 1001782275U, // VPCMPUQZrmibk + 2538872869U, // VPCMPUQZrmibk_alt + 4223007747U, // VPCMPUQZrmik + 1192501285U, // VPCMPUQZrmik_alt + 1269316611U, // VPCMPUQZrri + 1088823333U, // VPCMPUQZrri_alt + 1538669571U, // VPCMPUQZrrik + 1357586469U, // VPCMPUQZrrik_alt + 2882010115U, // VPCMPUWZ128rmi + 325447509U, // VPCMPUWZ128rmi_alt + 3151363075U, // VPCMPUWZ128rmik + 1179922261U, // VPCMPUWZ128rmik_alt + 1271413763U, // VPCMPUWZ128rri + 1088827221U, // VPCMPUWZ128rri_alt + 1540766723U, // VPCMPUWZ128rrik + 1357590357U, // VPCMPUWZ128rrik_alt + 3418881027U, // VPCMPUWZ256rmi + 375779157U, // VPCMPUWZ256rmi_alt + 3688233987U, // VPCMPUWZ256rmik + 1186213717U, // VPCMPUWZ256rmik_alt + 1271413763U, // VPCMPUWZ256rri + 1088827221U, // VPCMPUWZ256rri_alt + 1540766723U, // VPCMPUWZ256rrik + 1357590357U, // VPCMPUWZ256rrik_alt + 3955751939U, // VPCMPUWZrmi + 382070613U, // VPCMPUWZrmi_alt + 4225104899U, // VPCMPUWZrmik + 1192505173U, // VPCMPUWZrmik_alt + 1271413763U, // VPCMPUWZrri + 1088827221U, // VPCMPUWZrri_alt + 1540766723U, // VPCMPUWZrrik + 1357590357U, // VPCMPUWZrrik_alt + 2884107267U, // VPCMPWZ128rmi + 325446924U, // VPCMPWZ128rmi_alt + 3153460227U, // VPCMPWZ128rmik + 1179921676U, // VPCMPWZ128rmik_alt + 1273510915U, // VPCMPWZ128rri + 1088826636U, // VPCMPWZ128rri_alt + 1542863875U, // VPCMPWZ128rrik + 1357589772U, // VPCMPWZ128rrik_alt + 3420978179U, // VPCMPWZ256rmi + 375778572U, // VPCMPWZ256rmi_alt + 3690331139U, // VPCMPWZ256rmik + 1186213132U, // VPCMPWZ256rmik_alt + 1273510915U, // VPCMPWZ256rri + 1088826636U, // VPCMPWZ256rri_alt + 1542863875U, // VPCMPWZ256rrik + 1357589772U, // VPCMPWZ256rrik_alt + 3957849091U, // VPCMPWZrmi + 382070028U, // VPCMPWZrmi_alt + 4227202051U, // VPCMPWZrmik + 1192504588U, // VPCMPWZrmik_alt + 1273510915U, // VPCMPWZrri + 1088826636U, // VPCMPWZrri_alt + 1542863875U, // VPCMPWZrrik + 1357589772U, // VPCMPWZrrik_alt + 2870574020U, // VPCOMBmi + 325436582U, // VPCOMBmi_alt + 1259977668U, // VPCOMBri + 1088816294U, // VPCOMBri_alt + 2872671172U, // VPCOMDmi + 325437627U, // VPCOMDmi_alt + 1262074820U, // VPCOMDri + 1088817339U, // VPCOMDri_alt + 33588698U, // VPCOMPRESSBZ128mr + 3255109082U, // VPCOMPRESSBZ128mrk + 551831002U, // VPCOMPRESSBZ128rr + 3230696922U, // VPCOMPRESSBZ128rrk + 3229664730U, // VPCOMPRESSBZ128rrkz + 180389338U, // VPCOMPRESSBZ256mr + 3401909722U, // VPCOMPRESSBZ256mrk + 551831002U, // VPCOMPRESSBZ256rr + 3230696922U, // VPCOMPRESSBZ256rrk + 3229664730U, // VPCOMPRESSBZ256rrkz + 182486490U, // VPCOMPRESSBZmr + 3404006874U, // VPCOMPRESSBZmrk + 551831002U, // VPCOMPRESSBZrr + 3230696922U, // VPCOMPRESSBZrrk + 3229664730U, // VPCOMPRESSBZrrkz + 33591178U, // VPCOMPRESSDZ128mr + 3255111562U, // VPCOMPRESSDZ128mrk + 551833482U, // VPCOMPRESSDZ128rr + 3230699402U, // VPCOMPRESSDZ128rrk + 3229667210U, // VPCOMPRESSDZ128rrkz + 180391818U, // VPCOMPRESSDZ256mr + 3401912202U, // VPCOMPRESSDZ256mrk + 551833482U, // VPCOMPRESSDZ256rr + 3230699402U, // VPCOMPRESSDZ256rrk + 3229667210U, // VPCOMPRESSDZ256rrkz + 182488970U, // VPCOMPRESSDZmr + 3404009354U, // VPCOMPRESSDZmrk + 551833482U, // VPCOMPRESSDZrr + 3230699402U, // VPCOMPRESSDZrrk + 3229667210U, // VPCOMPRESSDZrrkz + 33595159U, // VPCOMPRESSQZ128mr + 3255115543U, // VPCOMPRESSQZ128mrk + 551837463U, // VPCOMPRESSQZ128rr + 3230703383U, // VPCOMPRESSQZ128rrk + 3229671191U, // VPCOMPRESSQZ128rrkz + 180395799U, // VPCOMPRESSQZ256mr + 3401916183U, // VPCOMPRESSQZ256mrk + 551837463U, // VPCOMPRESSQZ256rr + 3230703383U, // VPCOMPRESSQZ256rrk + 3229671191U, // VPCOMPRESSQZ256rrkz + 182492951U, // VPCOMPRESSQZmr + 3404013335U, // VPCOMPRESSQZmrk + 551837463U, // VPCOMPRESSQZrr + 3230703383U, // VPCOMPRESSQZrrk + 3229671191U, // VPCOMPRESSQZrrkz + 33599075U, // VPCOMPRESSWZ128mr + 3255119459U, // VPCOMPRESSWZ128mrk + 551841379U, // VPCOMPRESSWZ128rr + 3230707299U, // VPCOMPRESSWZ128rrk + 3229675107U, // VPCOMPRESSWZ128rrkz + 180399715U, // VPCOMPRESSWZ256mr + 3401920099U, // VPCOMPRESSWZ256mrk + 551841379U, // VPCOMPRESSWZ256rr + 3230707299U, // VPCOMPRESSWZ256rrk + 3229675107U, // VPCOMPRESSWZ256rrkz + 182496867U, // VPCOMPRESSWZmr + 3404017251U, // VPCOMPRESSWZmrk + 551841379U, // VPCOMPRESSWZrr + 3230707299U, // VPCOMPRESSWZrrk + 3229675107U, // VPCOMPRESSWZrrkz + 2874768324U, // VPCOMQmi + 325442859U, // VPCOMQmi_alt + 1264171972U, // VPCOMQri + 1088822571U, // VPCOMQri_alt + 2876865476U, // VPCOMUBmi + 325437028U, // VPCOMUBmi_alt + 1266269124U, // VPCOMUBri + 1088816740U, // VPCOMUBri_alt + 2878962628U, // VPCOMUDmi + 325439617U, // VPCOMUDmi_alt + 1268366276U, // VPCOMUDri + 1088819329U, // VPCOMUDri_alt + 2881059780U, // VPCOMUQmi + 325443603U, // VPCOMUQmi_alt + 1270463428U, // VPCOMUQri + 1088823315U, // VPCOMUQri_alt + 2883156932U, // VPCOMUWmi + 325447491U, // VPCOMUWmi_alt + 1272560580U, // VPCOMUWri + 1088827203U, // VPCOMUWri_alt + 2885254084U, // VPCOMWmi + 325446851U, // VPCOMWmi_alt + 1274657732U, // VPCOMWri + 1088826563U, // VPCOMWri_alt + 266279U, // VPCONFLICTDZ128rm + 629493799U, // VPCONFLICTDZ128rmb + 630607911U, // VPCONFLICTDZ128rmbk + 629231655U, // VPCONFLICTDZ128rmbkz + 3230994471U, // VPCONFLICTDZ128rmk + 3229863975U, // VPCONFLICTDZ128rmkz + 551833639U, // VPCONFLICTDZ128rr + 3230699559U, // VPCONFLICTDZ128rrk + 3229667367U, // VPCONFLICTDZ128rrkz + 552947751U, // VPCONFLICTDZ256rm + 631590951U, // VPCONFLICTDZ256rmb + 632705063U, // VPCONFLICTDZ256rmbk + 631328807U, // VPCONFLICTDZ256rmbkz + 3231027239U, // VPCONFLICTDZ256rmk + 3230879783U, // VPCONFLICTDZ256rmkz + 551833639U, // VPCONFLICTDZ256rr + 3230699559U, // VPCONFLICTDZ256rrk + 3229667367U, // VPCONFLICTDZ256rrkz + 552439847U, // VPCONFLICTDZrm + 633688103U, // VPCONFLICTDZrmb + 634802215U, // VPCONFLICTDZrmbk + 633425959U, // VPCONFLICTDZrmbkz + 3231092775U, // VPCONFLICTDZrmk + 3230896167U, // VPCONFLICTDZrmkz + 551833639U, // VPCONFLICTDZrr + 3230699559U, // VPCONFLICTDZrrk + 3229667367U, // VPCONFLICTDZrrkz + 270165U, // VPCONFLICTQZ128rm + 627416917U, // VPCONFLICTQZ128rmb + 628416341U, // VPCONFLICTQZ128rmbk + 627154773U, // VPCONFLICTQZ128rmbkz + 3230998357U, // VPCONFLICTQZ128rmk + 3229867861U, // VPCONFLICTQZ128rmkz + 551837525U, // VPCONFLICTQZ128rr + 3230703445U, // VPCONFLICTQZ128rrk + 3229671253U, // VPCONFLICTQZ128rrkz + 552951637U, // VPCONFLICTQZ256rm + 629514069U, // VPCONFLICTQZ256rmb + 630513493U, // VPCONFLICTQZ256rmbk + 629251925U, // VPCONFLICTQZ256rmbkz + 3231031125U, // VPCONFLICTQZ256rmk + 3230883669U, // VPCONFLICTQZ256rmkz + 551837525U, // VPCONFLICTQZ256rr + 3230703445U, // VPCONFLICTQZ256rrk + 3229671253U, // VPCONFLICTQZ256rrkz + 552443733U, // VPCONFLICTQZrm + 631611221U, // VPCONFLICTQZrmb + 632610645U, // VPCONFLICTQZrmbk + 631349077U, // VPCONFLICTQZrmbkz + 3231096661U, // VPCONFLICTQZrmk + 3230900053U, // VPCONFLICTQZrmkz + 551837525U, // VPCONFLICTQZrr + 3230703445U, // VPCONFLICTQZrrk + 3229671253U, // VPCONFLICTQZrrkz + 890577330U, // VPDPBUSDSZ128m + 1167483314U, // VPDPBUSDSZ128mb + 1436066226U, // VPDPBUSDSZ128mbk + 1436066226U, // VPDPBUSDSZ128mbkz + 985113010U, // VPDPBUSDSZ128mk + 985113010U, // VPDPBUSDSZ128mkz + 890282418U, // VPDPBUSDSZ128r + 87056818U, // VPDPBUSDSZ128rk + 89153970U, // VPDPBUSDSZ128rkz + 890610098U, // VPDPBUSDSZ256m + 1169580466U, // VPDPBUSDSZ256mb + 1438163378U, // VPDPBUSDSZ256mbk + 1438163378U, // VPDPBUSDSZ256mbkz + 985129394U, // VPDPBUSDSZ256mk + 985129394U, // VPDPBUSDSZ256mkz + 890282418U, // VPDPBUSDSZ256r + 87056818U, // VPDPBUSDSZ256rk + 89153970U, // VPDPBUSDSZ256rkz + 890675634U, // VPDPBUSDSZm + 1171677618U, // VPDPBUSDSZmb + 1440260530U, // VPDPBUSDSZmbk + 1440260530U, // VPDPBUSDSZmbkz + 985145778U, // VPDPBUSDSZmk + 985145778U, // VPDPBUSDSZmkz + 890282418U, // VPDPBUSDSZr + 87056818U, // VPDPBUSDSZrk + 89153970U, // VPDPBUSDSZrkz + 890572787U, // VPDPBUSDZ128m + 1167478771U, // VPDPBUSDZ128mb + 1436061683U, // VPDPBUSDZ128mbk + 1436061683U, // VPDPBUSDZ128mbkz + 985108467U, // VPDPBUSDZ128mk + 985108467U, // VPDPBUSDZ128mkz + 890277875U, // VPDPBUSDZ128r + 87052275U, // VPDPBUSDZ128rk + 89149427U, // VPDPBUSDZ128rkz + 890605555U, // VPDPBUSDZ256m + 1169575923U, // VPDPBUSDZ256mb + 1438158835U, // VPDPBUSDZ256mbk + 1438158835U, // VPDPBUSDZ256mbkz + 985124851U, // VPDPBUSDZ256mk + 985124851U, // VPDPBUSDZ256mkz + 890277875U, // VPDPBUSDZ256r + 87052275U, // VPDPBUSDZ256rk + 89149427U, // VPDPBUSDZ256rkz + 890671091U, // VPDPBUSDZm + 1171673075U, // VPDPBUSDZmb + 1440255987U, // VPDPBUSDZmbk + 1440255987U, // VPDPBUSDZmbkz + 985141235U, // VPDPBUSDZmk + 985141235U, // VPDPBUSDZmkz + 890277875U, // VPDPBUSDZr + 87052275U, // VPDPBUSDZrk + 89149427U, // VPDPBUSDZrkz + 890577319U, // VPDPWSSDSZ128m + 1167483303U, // VPDPWSSDSZ128mb + 1436066215U, // VPDPWSSDSZ128mbk + 1436066215U, // VPDPWSSDSZ128mbkz + 985112999U, // VPDPWSSDSZ128mk + 985112999U, // VPDPWSSDSZ128mkz + 890282407U, // VPDPWSSDSZ128r + 87056807U, // VPDPWSSDSZ128rk + 89153959U, // VPDPWSSDSZ128rkz + 890610087U, // VPDPWSSDSZ256m + 1169580455U, // VPDPWSSDSZ256mb + 1438163367U, // VPDPWSSDSZ256mbk + 1438163367U, // VPDPWSSDSZ256mbkz + 985129383U, // VPDPWSSDSZ256mk + 985129383U, // VPDPWSSDSZ256mkz + 890282407U, // VPDPWSSDSZ256r + 87056807U, // VPDPWSSDSZ256rk + 89153959U, // VPDPWSSDSZ256rkz + 890675623U, // VPDPWSSDSZm + 1171677607U, // VPDPWSSDSZmb + 1440260519U, // VPDPWSSDSZmbk + 1440260519U, // VPDPWSSDSZmbkz + 985145767U, // VPDPWSSDSZmk + 985145767U, // VPDPWSSDSZmkz + 890282407U, // VPDPWSSDSZr + 87056807U, // VPDPWSSDSZrk + 89153959U, // VPDPWSSDSZrkz + 890572733U, // VPDPWSSDZ128m + 1167478717U, // VPDPWSSDZ128mb + 1436061629U, // VPDPWSSDZ128mbk + 1436061629U, // VPDPWSSDZ128mbkz + 985108413U, // VPDPWSSDZ128mk + 985108413U, // VPDPWSSDZ128mkz + 890277821U, // VPDPWSSDZ128r + 87052221U, // VPDPWSSDZ128rk + 89149373U, // VPDPWSSDZ128rkz + 890605501U, // VPDPWSSDZ256m + 1169575869U, // VPDPWSSDZ256mb + 1438158781U, // VPDPWSSDZ256mbk + 1438158781U, // VPDPWSSDZ256mbkz + 985124797U, // VPDPWSSDZ256mk + 985124797U, // VPDPWSSDZ256mkz + 890277821U, // VPDPWSSDZ256r + 87052221U, // VPDPWSSDZ256rk + 89149373U, // VPDPWSSDZ256rkz + 890671037U, // VPDPWSSDZm + 1171673021U, // VPDPWSSDZmb + 1440255933U, // VPDPWSSDZmbk + 1440255933U, // VPDPWSSDZmbkz + 985141181U, // VPDPWSSDZmk + 985141181U, // VPDPWSSDZmkz + 890277821U, // VPDPWSSDZr + 87052221U, // VPDPWSSDZrk + 89149373U, // VPDPWSSDZrkz + 392544868U, // VPERM2F128rm + 1088815716U, // VPERM2F128rr + 392544923U, // VPERM2I128rm + 1088815771U, // VPERM2I128rr + 811844796U, // VPERMBZ128rm + 985105596U, // VPERMBZ128rmk + 890569916U, // VPERMBZ128rmkz + 811648188U, // VPERMBZ128rr + 87049404U, // VPERMBZ128rrk + 890275004U, // VPERMBZ128rrkz + 812860604U, // VPERMBZ256rm + 985121980U, // VPERMBZ256rmk + 890602684U, // VPERMBZ256rmkz + 811648188U, // VPERMBZ256rr + 87049404U, // VPERMBZ256rrk + 890275004U, // VPERMBZ256rrkz + 812876988U, // VPERMBZrm + 985138364U, // VPERMBZrmk + 890668220U, // VPERMBZrmkz + 811648188U, // VPERMBZrr + 87049404U, // VPERMBZrrk + 890275004U, // VPERMBZrrkz + 812861635U, // VPERMDYrm + 811649219U, // VPERMDYrr + 812861635U, // VPERMDZ256rm + 362891459U, // VPERMDZ256rmb + 1438156995U, // VPERMDZ256rmbk + 1169574083U, // VPERMDZ256rmbkz + 985123011U, // VPERMDZ256rmk + 890603715U, // VPERMDZ256rmkz + 811649219U, // VPERMDZ256rr + 87050435U, // VPERMDZ256rrk + 890276035U, // VPERMDZ256rrkz + 812878019U, // VPERMDZrm + 364988611U, // VPERMDZrmb + 1440254147U, // VPERMDZrmbk + 1171671235U, // VPERMDZrmbkz + 985139395U, // VPERMDZrmk + 890669251U, // VPERMDZrmkz + 811649219U, // VPERMDZrr + 87050435U, // VPERMDZrrk + 890276035U, // VPERMDZrrkz + 890569579U, // VPERMI2B128rm + 985105259U, // VPERMI2B128rmk + 985105259U, // VPERMI2B128rmkz + 890274667U, // VPERMI2B128rr + 87049067U, // VPERMI2B128rrk + 89146219U, // VPERMI2B128rrkz + 890602347U, // VPERMI2B256rm + 985121643U, // VPERMI2B256rmk + 985121643U, // VPERMI2B256rmkz + 890274667U, // VPERMI2B256rr + 87049067U, // VPERMI2B256rrk + 89146219U, // VPERMI2B256rrkz + 890667883U, // VPERMI2Brm + 985138027U, // VPERMI2Brmk + 985138027U, // VPERMI2Brmkz + 890274667U, // VPERMI2Brr + 87049067U, // VPERMI2Brrk + 89146219U, // VPERMI2Brrkz + 890570533U, // VPERMI2D128rm + 1167476517U, // VPERMI2D128rmb + 1436059429U, // VPERMI2D128rmbk + 1436059429U, // VPERMI2D128rmbkz + 985106213U, // VPERMI2D128rmk + 985106213U, // VPERMI2D128rmkz + 890275621U, // VPERMI2D128rr + 87050021U, // VPERMI2D128rrk + 89147173U, // VPERMI2D128rrkz + 890603301U, // VPERMI2D256rm + 1169573669U, // VPERMI2D256rmb + 1438156581U, // VPERMI2D256rmbk + 1438156581U, // VPERMI2D256rmbkz + 985122597U, // VPERMI2D256rmk + 985122597U, // VPERMI2D256rmkz + 890275621U, // VPERMI2D256rr + 87050021U, // VPERMI2D256rrk + 89147173U, // VPERMI2D256rrkz + 890668837U, // VPERMI2Drm + 1171670821U, // VPERMI2Drmb + 1440253733U, // VPERMI2Drmbk + 1440253733U, // VPERMI2Drmbkz + 985138981U, // VPERMI2Drmk + 985138981U, // VPERMI2Drmkz + 890275621U, // VPERMI2Drr + 87050021U, // VPERMI2Drrk + 89147173U, // VPERMI2Drrkz + 890177970U, // VPERMI2PD128rm + 1164970418U, // VPERMI2PD128rmb + 1433389490U, // VPERMI2PD128rmbk + 1433389490U, // VPERMI2PD128rmbkz + 86985138U, // VPERMI2PD128rmk + 89082290U, // VPERMI2PD128rmkz + 890276274U, // VPERMI2PD128rr + 87050674U, // VPERMI2PD128rrk + 89147826U, // VPERMI2PD128rrkz + 890309042U, // VPERMI2PD256rm + 1167067570U, // VPERMI2PD256rmb + 1435486642U, // VPERMI2PD256rmbk + 1435486642U, // VPERMI2PD256rmbkz + 87083442U, // VPERMI2PD256rmk + 89180594U, // VPERMI2PD256rmkz + 890276274U, // VPERMI2PD256rr + 87050674U, // VPERMI2PD256rrk + 89147826U, // VPERMI2PD256rrkz + 890358194U, // VPERMI2PDrm + 1169164722U, // VPERMI2PDrmb + 1437583794U, // VPERMI2PDrmbk + 1437583794U, // VPERMI2PDrmbkz + 87132594U, // VPERMI2PDrmk + 89229746U, // VPERMI2PDrmkz + 890276274U, // VPERMI2PDrr + 87050674U, // VPERMI2PDrrk + 89147826U, // VPERMI2PDrrkz + 890184386U, // VPERMI2PS128rm + 1167270594U, // VPERMI2PS128rmb + 1435689666U, // VPERMI2PS128rmbk + 1435689666U, // VPERMI2PS128rmbkz + 86991554U, // VPERMI2PS128rmk + 89088706U, // VPERMI2PS128rmkz + 890282690U, // VPERMI2PS128rr + 87057090U, // VPERMI2PS128rrk + 89154242U, // VPERMI2PS128rrkz + 890315458U, // VPERMI2PS256rm + 1169367746U, // VPERMI2PS256rmb + 1437786818U, // VPERMI2PS256rmbk + 1437786818U, // VPERMI2PS256rmbkz + 87089858U, // VPERMI2PS256rmk + 89187010U, // VPERMI2PS256rmkz + 890282690U, // VPERMI2PS256rr + 87057090U, // VPERMI2PS256rrk + 89154242U, // VPERMI2PS256rrkz + 890364610U, // VPERMI2PSrm + 1171464898U, // VPERMI2PSrmb + 1439883970U, // VPERMI2PSrmbk + 1439883970U, // VPERMI2PSrmbkz + 87139010U, // VPERMI2PSrmk + 89236162U, // VPERMI2PSrmkz + 890282690U, // VPERMI2PSrr + 87057090U, // VPERMI2PSrrk + 89154242U, // VPERMI2PSrrkz + 890575167U, // VPERMI2Q128rm + 1165285695U, // VPERMI2Q128rmb + 1433950527U, // VPERMI2Q128rmbk + 1433950527U, // VPERMI2Q128rmbkz + 985110847U, // VPERMI2Q128rmk + 985110847U, // VPERMI2Q128rmkz + 890280255U, // VPERMI2Q128rr + 87054655U, // VPERMI2Q128rrk + 89151807U, // VPERMI2Q128rrkz + 890607935U, // VPERMI2Q256rm + 1167382847U, // VPERMI2Q256rmb + 1436047679U, // VPERMI2Q256rmbk + 1436047679U, // VPERMI2Q256rmbkz + 985127231U, // VPERMI2Q256rmk + 985127231U, // VPERMI2Q256rmkz + 890280255U, // VPERMI2Q256rr + 87054655U, // VPERMI2Q256rrk + 89151807U, // VPERMI2Q256rrkz + 890673471U, // VPERMI2Qrm + 1169479999U, // VPERMI2Qrmb + 1438144831U, // VPERMI2Qrmbk + 1438144831U, // VPERMI2Qrmbkz + 985143615U, // VPERMI2Qrmk + 985143615U, // VPERMI2Qrmkz + 890280255U, // VPERMI2Qrr + 87054655U, // VPERMI2Qrrk + 89151807U, // VPERMI2Qrrkz + 890579481U, // VPERMI2W128rm + 985115161U, // VPERMI2W128rmk + 985115161U, // VPERMI2W128rmkz + 890284569U, // VPERMI2W128rr + 87058969U, // VPERMI2W128rrk + 89156121U, // VPERMI2W128rrkz + 890612249U, // VPERMI2W256rm + 985131545U, // VPERMI2W256rmk + 985131545U, // VPERMI2W256rmkz + 890284569U, // VPERMI2W256rr + 87058969U, // VPERMI2W256rrk + 89156121U, // VPERMI2W256rrkz + 890677785U, // VPERMI2Wrm + 985147929U, // VPERMI2Wrmk + 985147929U, // VPERMI2Wrmkz + 890284569U, // VPERMI2Wrr + 87058969U, // VPERMI2Wrrk + 89156121U, // VPERMI2Wrrkz + 3692300743U, // VPERMIL2PDYmr + 1186204103U, // VPERMIL2PDYrm + 1357580743U, // VPERMIL2PDYrr + 1357580743U, // VPERMIL2PDYrr_REV + 2081688007U, // VPERMIL2PDmr + 1179912647U, // VPERMIL2PDrm + 1357580743U, // VPERMIL2PDrr + 1357580743U, // VPERMIL2PDrr_REV + 3692307159U, // VPERMIL2PSYmr + 1186210519U, // VPERMIL2PSYrm + 1357587159U, // VPERMIL2PSYrr + 1357587159U, // VPERMIL2PSYrr_REV + 2081694423U, // VPERMIL2PSmr + 1179919063U, // VPERMIL2PSrm + 1357587159U, // VPERMIL2PSrr + 1357587159U, // VPERMIL2PSrr_REV + 168070135U, // VPERMILPDYmi + 283429879U, // VPERMILPDYri + 812862455U, // VPERMILPDYrm + 811650039U, // VPERMILPDYrr + 3032779767U, // VPERMILPDZ128mbi + 3079932919U, // VPERMILPDZ128mbik + 2999307255U, // VPERMILPDZ128mbikz + 77892599U, // VPERMILPDZ128mi + 666110967U, // VPERMILPDZ128mik + 568708087U, // VPERMILPDZ128mikz + 283429879U, // VPERMILPDZ128ri + 1357581303U, // VPERMILPDZ128rik + 1088818167U, // VPERMILPDZ128rikz + 811846647U, // VPERMILPDZ128rm + 358763511U, // VPERMILPDZ128rmb + 1433390071U, // VPERMILPDZ128rmbk + 1164970999U, // VPERMILPDZ128rmbkz + 985107447U, // VPERMILPDZ128rmk + 890571767U, // VPERMILPDZ128rmkz + 811650039U, // VPERMILPDZ128rr + 87051255U, // VPERMILPDZ128rrk + 890276855U, // VPERMILPDZ128rrkz + 1690602487U, // VPERMILPDZ256mbi + 1737755639U, // VPERMILPDZ256mbik + 1657129975U, // VPERMILPDZ256mbikz + 168070135U, // VPERMILPDZ256mi + 668208119U, // VPERMILPDZ256mik + 660982775U, // VPERMILPDZ256mikz + 283429879U, // VPERMILPDZ256ri + 1357581303U, // VPERMILPDZ256rik + 1088818167U, // VPERMILPDZ256rikz + 812862455U, // VPERMILPDZ256rm + 360860663U, // VPERMILPDZ256rmb + 1435487223U, // VPERMILPDZ256rmbk + 1167068151U, // VPERMILPDZ256rmbkz + 985123831U, // VPERMILPDZ256rmk + 890604535U, // VPERMILPDZ256rmkz + 811650039U, // VPERMILPDZ256rr + 87051255U, // VPERMILPDZ256rrk + 890276855U, // VPERMILPDZ256rrkz + 2495908855U, // VPERMILPDZmbi + 2543062007U, // VPERMILPDZmbik + 2462436343U, // VPERMILPDZmbikz + 170167287U, // VPERMILPDZmi + 672402423U, // VPERMILPDZmik + 669371383U, // VPERMILPDZmikz + 283429879U, // VPERMILPDZri + 1357581303U, // VPERMILPDZrik + 1088818167U, // VPERMILPDZrikz + 812878839U, // VPERMILPDZrm + 362957815U, // VPERMILPDZrmb + 1437584375U, // VPERMILPDZrmbk + 1169165303U, // VPERMILPDZrmbkz + 985140215U, // VPERMILPDZrmk + 890670071U, // VPERMILPDZrmkz + 811650039U, // VPERMILPDZrr + 87051255U, // VPERMILPDZrrk + 890276855U, // VPERMILPDZrrkz + 77892599U, // VPERMILPDmi + 283429879U, // VPERMILPDri + 811846647U, // VPERMILPDrm + 811650039U, // VPERMILPDrr + 168076575U, // VPERMILPSYmi + 283436319U, // VPERMILPSYri + 812868895U, // VPERMILPSYrm + 811656479U, // VPERMILPSYrr + 1692706079U, // VPERMILPSZ128mbi + 1752442143U, // VPERMILPSZ128mbik + 1661330719U, // VPERMILPSZ128mbikz + 77899039U, // VPERMILPSZ128mi + 666117407U, // VPERMILPSZ128mik + 568714527U, // VPERMILPSZ128mikz + 283436319U, // VPERMILPSZ128ri + 1357587743U, // VPERMILPSZ128rik + 1088824607U, // VPERMILPSZ128rikz + 811853087U, // VPERMILPSZ128rm + 360883487U, // VPERMILPSZ128rmb + 1435690271U, // VPERMILPSZ128rmbk + 1167271199U, // VPERMILPSZ128rmbkz + 985113887U, // VPERMILPSZ128rmk + 890578207U, // VPERMILPSZ128rmkz + 811656479U, // VPERMILPSZ128rr + 87057695U, // VPERMILPSZ128rrk + 890283295U, // VPERMILPSZ128rrkz + 2498012447U, // VPERMILPSZ256mbi + 2557748511U, // VPERMILPSZ256mbik + 2466637087U, // VPERMILPSZ256mbikz + 168076575U, // VPERMILPSZ256mi + 668214559U, // VPERMILPSZ256mik + 660989215U, // VPERMILPSZ256mikz + 283436319U, // VPERMILPSZ256ri + 1357587743U, // VPERMILPSZ256rik + 1088824607U, // VPERMILPSZ256rikz + 812868895U, // VPERMILPSZ256rm + 362980639U, // VPERMILPSZ256rmb + 1437787423U, // VPERMILPSZ256rmbk + 1169368351U, // VPERMILPSZ256rmbkz + 985130271U, // VPERMILPSZ256rmk + 890610975U, // VPERMILPSZ256rmkz + 811656479U, // VPERMILPSZ256rr + 87057695U, // VPERMILPSZ256rrk + 890283295U, // VPERMILPSZ256rrkz + 2766447903U, // VPERMILPSZmbi + 2826183967U, // VPERMILPSZmbik + 2735072543U, // VPERMILPSZmbikz + 170173727U, // VPERMILPSZmi + 672408863U, // VPERMILPSZmik + 669377823U, // VPERMILPSZmikz + 283436319U, // VPERMILPSZri + 1357587743U, // VPERMILPSZrik + 1088824607U, // VPERMILPSZrikz + 812885279U, // VPERMILPSZrm + 365077791U, // VPERMILPSZrmb + 1439884575U, // VPERMILPSZrmbk + 1171465503U, // VPERMILPSZrmbkz + 985146655U, // VPERMILPSZrmk + 890676511U, // VPERMILPSZrmkz + 811656479U, // VPERMILPSZrr + 87057695U, // VPERMILPSZrrk + 890283295U, // VPERMILPSZrrkz + 77899039U, // VPERMILPSmi + 283436319U, // VPERMILPSri + 811853087U, // VPERMILPSrm + 811656479U, // VPERMILPSrr + 168070206U, // VPERMPDYmi + 283429950U, // VPERMPDYri + 1690602558U, // VPERMPDZ256mbi + 1737755710U, // VPERMPDZ256mbik + 1657130046U, // VPERMPDZ256mbikz + 168070206U, // VPERMPDZ256mi + 668208190U, // VPERMPDZ256mik + 660982846U, // VPERMPDZ256mikz + 283429950U, // VPERMPDZ256ri + 1357581374U, // VPERMPDZ256rik + 1088818238U, // VPERMPDZ256rikz + 812616766U, // VPERMPDZ256rm + 360860734U, // VPERMPDZ256rmb + 1435487294U, // VPERMPDZ256rmbk + 1167068222U, // VPERMPDZ256rmbkz + 87084094U, // VPERMPDZ256rmk + 890309694U, // VPERMPDZ256rmkz + 811650110U, // VPERMPDZ256rr + 87051326U, // VPERMPDZ256rrk + 890276926U, // VPERMPDZ256rrkz + 2495908926U, // VPERMPDZmbi + 2543062078U, // VPERMPDZmbik + 2462436414U, // VPERMPDZmbikz + 170167358U, // VPERMPDZmi + 672402494U, // VPERMPDZmik + 669371454U, // VPERMPDZmikz + 283429950U, // VPERMPDZri + 1357581374U, // VPERMPDZrik + 1088818238U, // VPERMPDZrikz + 812731454U, // VPERMPDZrm + 362957886U, // VPERMPDZrmb + 1437584446U, // VPERMPDZrmbk + 1169165374U, // VPERMPDZrmbkz + 87133246U, // VPERMPDZrmk + 890358846U, // VPERMPDZrmkz + 811650110U, // VPERMPDZrr + 87051326U, // VPERMPDZrrk + 890276926U, // VPERMPDZrrkz + 812623215U, // VPERMPSYrm + 811656559U, // VPERMPSYrr + 812623215U, // VPERMPSZ256rm + 362980719U, // VPERMPSZ256rmb + 1437787503U, // VPERMPSZ256rmbk + 1169368431U, // VPERMPSZ256rmbkz + 87090543U, // VPERMPSZ256rmk + 890316143U, // VPERMPSZ256rmkz + 811656559U, // VPERMPSZ256rr + 87057775U, // VPERMPSZ256rrk + 890283375U, // VPERMPSZ256rrkz + 812737903U, // VPERMPSZrm + 365077871U, // VPERMPSZrmb + 1439884655U, // VPERMPSZrmbk + 1171465583U, // VPERMPSZrmbkz + 87139695U, // VPERMPSZrmk + 890365295U, // VPERMPSZrmkz + 811656559U, // VPERMPSZrr + 87057775U, // VPERMPSZrrk + 890283375U, // VPERMPSZrrkz + 1009032499U, // VPERMQYmi + 283434291U, // VPERMQYri + 1640275251U, // VPERMQZ256mbi + 1733565747U, // VPERMQZ256mbik + 1671814451U, // VPERMQZ256mbikz + 1009032499U, // VPERMQZ256mi + 649338163U, // VPERMQZ256mik + 644209971U, // VPERMQZ256mikz + 283434291U, // VPERMQZ256ri + 1357585715U, // VPERMQZ256rik + 1088822579U, // VPERMQZ256rikz + 812866867U, // VPERMQZ256rm + 360815923U, // VPERMQZ256rmb + 1436048691U, // VPERMQZ256rmbk + 1167383859U, // VPERMQZ256rmbkz + 985128243U, // VPERMQZ256rmk + 890608947U, // VPERMQZ256rmkz + 811654451U, // VPERMQZ256rr + 87055667U, // VPERMQZ256rrk + 890281267U, // VPERMQZ256rrkz + 2445581619U, // VPERMQZmbi + 2538872115U, // VPERMQZmbik + 2477120819U, // VPERMQZmbikz + 1011129651U, // VPERMQZmi + 655629619U, // VPERMQZmik + 650501427U, // VPERMQZmikz + 283434291U, // VPERMQZri + 1357585715U, // VPERMQZrik + 1088822579U, // VPERMQZrikz + 812883251U, // VPERMQZrm + 362913075U, // VPERMQZrmb + 1438145843U, // VPERMQZrmbk + 1169481011U, // VPERMQZrmbkz + 985144627U, // VPERMQZrmk + 890674483U, // VPERMQZrmkz + 811654451U, // VPERMQZrr + 87055667U, // VPERMQZrrk + 890281267U, // VPERMQZrrkz + 890569599U, // VPERMT2B128rm + 985105279U, // VPERMT2B128rmk + 985105279U, // VPERMT2B128rmkz + 890274687U, // VPERMT2B128rr + 87049087U, // VPERMT2B128rrk + 89146239U, // VPERMT2B128rrkz + 890602367U, // VPERMT2B256rm + 985121663U, // VPERMT2B256rmk + 985121663U, // VPERMT2B256rmkz + 890274687U, // VPERMT2B256rr + 87049087U, // VPERMT2B256rrk + 89146239U, // VPERMT2B256rrkz + 890667903U, // VPERMT2Brm + 985138047U, // VPERMT2Brmk + 985138047U, // VPERMT2Brmkz + 890274687U, // VPERMT2Brr + 87049087U, // VPERMT2Brrk + 89146239U, // VPERMT2Brrkz + 890570553U, // VPERMT2D128rm + 1167476537U, // VPERMT2D128rmb + 1436059449U, // VPERMT2D128rmbk + 1436059449U, // VPERMT2D128rmbkz + 985106233U, // VPERMT2D128rmk + 985106233U, // VPERMT2D128rmkz + 890275641U, // VPERMT2D128rr + 87050041U, // VPERMT2D128rrk + 89147193U, // VPERMT2D128rrkz + 890603321U, // VPERMT2D256rm + 1169573689U, // VPERMT2D256rmb + 1438156601U, // VPERMT2D256rmbk + 1438156601U, // VPERMT2D256rmbkz + 985122617U, // VPERMT2D256rmk + 985122617U, // VPERMT2D256rmkz + 890275641U, // VPERMT2D256rr + 87050041U, // VPERMT2D256rrk + 89147193U, // VPERMT2D256rrkz + 890668857U, // VPERMT2Drm + 1171670841U, // VPERMT2Drmb + 1440253753U, // VPERMT2Drmbk + 1440253753U, // VPERMT2Drmbkz + 985139001U, // VPERMT2Drmk + 985139001U, // VPERMT2Drmkz + 890275641U, // VPERMT2Drr + 87050041U, // VPERMT2Drrk + 89147193U, // VPERMT2Drrkz + 890178069U, // VPERMT2PD128rm + 1164970517U, // VPERMT2PD128rmb + 1433389589U, // VPERMT2PD128rmbk + 1433389589U, // VPERMT2PD128rmbkz + 86985237U, // VPERMT2PD128rmk + 89082389U, // VPERMT2PD128rmkz + 890276373U, // VPERMT2PD128rr + 87050773U, // VPERMT2PD128rrk + 89147925U, // VPERMT2PD128rrkz + 890309141U, // VPERMT2PD256rm + 1167067669U, // VPERMT2PD256rmb + 1435486741U, // VPERMT2PD256rmbk + 1435486741U, // VPERMT2PD256rmbkz + 87083541U, // VPERMT2PD256rmk + 89180693U, // VPERMT2PD256rmkz + 890276373U, // VPERMT2PD256rr + 87050773U, // VPERMT2PD256rrk + 89147925U, // VPERMT2PD256rrkz + 890358293U, // VPERMT2PDrm + 1169164821U, // VPERMT2PDrmb + 1437583893U, // VPERMT2PDrmbk + 1437583893U, // VPERMT2PDrmbkz + 87132693U, // VPERMT2PDrmk + 89229845U, // VPERMT2PDrmkz + 890276373U, // VPERMT2PDrr + 87050773U, // VPERMT2PDrrk + 89147925U, // VPERMT2PDrrkz + 890184474U, // VPERMT2PS128rm + 1167270682U, // VPERMT2PS128rmb + 1435689754U, // VPERMT2PS128rmbk + 1435689754U, // VPERMT2PS128rmbkz + 86991642U, // VPERMT2PS128rmk + 89088794U, // VPERMT2PS128rmkz + 890282778U, // VPERMT2PS128rr + 87057178U, // VPERMT2PS128rrk + 89154330U, // VPERMT2PS128rrkz + 890315546U, // VPERMT2PS256rm + 1169367834U, // VPERMT2PS256rmb + 1437786906U, // VPERMT2PS256rmbk + 1437786906U, // VPERMT2PS256rmbkz + 87089946U, // VPERMT2PS256rmk + 89187098U, // VPERMT2PS256rmkz + 890282778U, // VPERMT2PS256rr + 87057178U, // VPERMT2PS256rrk + 89154330U, // VPERMT2PS256rrkz + 890364698U, // VPERMT2PSrm + 1171464986U, // VPERMT2PSrmb + 1439884058U, // VPERMT2PSrmbk + 1439884058U, // VPERMT2PSrmbkz + 87139098U, // VPERMT2PSrmk + 89236250U, // VPERMT2PSrmkz + 890282778U, // VPERMT2PSrr + 87057178U, // VPERMT2PSrrk + 89154330U, // VPERMT2PSrrkz + 890575196U, // VPERMT2Q128rm + 1165285724U, // VPERMT2Q128rmb + 1433950556U, // VPERMT2Q128rmbk + 1433950556U, // VPERMT2Q128rmbkz + 985110876U, // VPERMT2Q128rmk + 985110876U, // VPERMT2Q128rmkz + 890280284U, // VPERMT2Q128rr + 87054684U, // VPERMT2Q128rrk + 89151836U, // VPERMT2Q128rrkz + 890607964U, // VPERMT2Q256rm + 1167382876U, // VPERMT2Q256rmb + 1436047708U, // VPERMT2Q256rmbk + 1436047708U, // VPERMT2Q256rmbkz + 985127260U, // VPERMT2Q256rmk + 985127260U, // VPERMT2Q256rmkz + 890280284U, // VPERMT2Q256rr + 87054684U, // VPERMT2Q256rrk + 89151836U, // VPERMT2Q256rrkz + 890673500U, // VPERMT2Qrm + 1169480028U, // VPERMT2Qrmb + 1438144860U, // VPERMT2Qrmbk + 1438144860U, // VPERMT2Qrmbkz + 985143644U, // VPERMT2Qrmk + 985143644U, // VPERMT2Qrmkz + 890280284U, // VPERMT2Qrr + 87054684U, // VPERMT2Qrrk + 89151836U, // VPERMT2Qrrkz + 890579501U, // VPERMT2W128rm + 985115181U, // VPERMT2W128rmk + 985115181U, // VPERMT2W128rmkz + 890284589U, // VPERMT2W128rr + 87058989U, // VPERMT2W128rrk + 89156141U, // VPERMT2W128rrkz + 890612269U, // VPERMT2W256rm + 985131565U, // VPERMT2W256rmk + 985131565U, // VPERMT2W256rmkz + 890284589U, // VPERMT2W256rr + 87058989U, // VPERMT2W256rrk + 89156141U, // VPERMT2W256rrkz + 890677805U, // VPERMT2Wrm + 985147949U, // VPERMT2Wrmk + 985147949U, // VPERMT2Wrmkz + 890284589U, // VPERMT2Wrr + 87058989U, // VPERMT2Wrrk + 89156141U, // VPERMT2Wrrkz + 811855051U, // VPERMWZ128rm + 985115851U, // VPERMWZ128rmk + 890580171U, // VPERMWZ128rmkz + 811658443U, // VPERMWZ128rr + 87059659U, // VPERMWZ128rrk + 890285259U, // VPERMWZ128rrkz + 812870859U, // VPERMWZ256rm + 985132235U, // VPERMWZ256rmk + 890612939U, // VPERMWZ256rmkz + 811658443U, // VPERMWZ256rr + 87059659U, // VPERMWZ256rrk + 890285259U, // VPERMWZ256rrkz + 812887243U, // VPERMWZrm + 985148619U, // VPERMWZrmk + 890678475U, // VPERMWZrmkz + 811658443U, // VPERMWZrr + 87059659U, // VPERMWZrrk + 890285259U, // VPERMWZrrkz + 263168U, // VPEXPANDBZ128rm + 3230991360U, // VPEXPANDBZ128rmk + 3229860864U, // VPEXPANDBZ128rmkz + 551830528U, // VPEXPANDBZ128rr + 3230696448U, // VPEXPANDBZ128rrk + 3229664256U, // VPEXPANDBZ128rrkz + 552944640U, // VPEXPANDBZ256rm + 3231024128U, // VPEXPANDBZ256rmk + 3230876672U, // VPEXPANDBZ256rmkz + 551830528U, // VPEXPANDBZ256rr + 3230696448U, // VPEXPANDBZ256rrk + 3229664256U, // VPEXPANDBZ256rrkz + 552436736U, // VPEXPANDBZrm + 3231089664U, // VPEXPANDBZrmk + 3230893056U, // VPEXPANDBZrmkz + 551830528U, // VPEXPANDBZrr + 3230696448U, // VPEXPANDBZrrk + 3229664256U, // VPEXPANDBZrrkz + 264156U, // VPEXPANDDZ128rm + 3230992348U, // VPEXPANDDZ128rmk + 3229861852U, // VPEXPANDDZ128rmkz + 551831516U, // VPEXPANDDZ128rr + 3230697436U, // VPEXPANDDZ128rrk + 3229665244U, // VPEXPANDDZ128rrkz + 552945628U, // VPEXPANDDZ256rm + 3231025116U, // VPEXPANDDZ256rmk + 3230877660U, // VPEXPANDDZ256rmkz + 551831516U, // VPEXPANDDZ256rr + 3230697436U, // VPEXPANDDZ256rrk + 3229665244U, // VPEXPANDDZ256rrkz + 552437724U, // VPEXPANDDZrm + 3231090652U, // VPEXPANDDZrmk + 3230894044U, // VPEXPANDDZrmkz + 551831516U, // VPEXPANDDZrr + 3230697436U, // VPEXPANDDZrrk + 3229665244U, // VPEXPANDDZrrkz + 269006U, // VPEXPANDQZ128rm + 3230997198U, // VPEXPANDQZ128rmk + 3229866702U, // VPEXPANDQZ128rmkz + 551836366U, // VPEXPANDQZ128rr + 3230702286U, // VPEXPANDQZ128rrk + 3229670094U, // VPEXPANDQZ128rrkz + 552950478U, // VPEXPANDQZ256rm + 3231029966U, // VPEXPANDQZ256rmk + 3230882510U, // VPEXPANDQZ256rmkz + 551836366U, // VPEXPANDQZ256rr + 3230702286U, // VPEXPANDQZ256rrk + 3229670094U, // VPEXPANDQZ256rrkz + 552442574U, // VPEXPANDQZrm + 3231095502U, // VPEXPANDQZrmk + 3230898894U, // VPEXPANDQZrmkz + 551836366U, // VPEXPANDQZrr + 3230702286U, // VPEXPANDQZrrk + 3229670094U, // VPEXPANDQZrrkz + 273240U, // VPEXPANDWZ128rm + 3231001432U, // VPEXPANDWZ128rmk + 3229870936U, // VPEXPANDWZ128rmkz + 551840600U, // VPEXPANDWZ128rr + 3230706520U, // VPEXPANDWZ128rrk + 3229674328U, // VPEXPANDWZ128rrkz + 552954712U, // VPEXPANDWZ256rm + 3231034200U, // VPEXPANDWZ256rmk + 3230886744U, // VPEXPANDWZ256rmkz + 551840600U, // VPEXPANDWZ256rr + 3230706520U, // VPEXPANDWZ256rrk + 3229674328U, // VPEXPANDWZ256rrkz + 552446808U, // VPEXPANDWZrm + 3231099736U, // VPEXPANDWZrmk + 3230903128U, // VPEXPANDWZrmkz + 551840600U, // VPEXPANDWZrr + 3230706520U, // VPEXPANDWZrrk + 3229674328U, // VPEXPANDWZrrkz + 321160592U, // VPEXTRBZmr + 283428240U, // VPEXTRBZrr + 321160592U, // VPEXTRBmr + 283428240U, // VPEXTRBrr + 589598179U, // VPEXTRDZmr + 283430371U, // VPEXTRDZrr + 589598179U, // VPEXTRDmr + 283430371U, // VPEXTRDrr + 858037936U, // VPEXTRQZmr + 283434672U, // VPEXTRQZrr + 858037936U, // VPEXTRQmr + 283434672U, // VPEXTRQrr + 1126477261U, // VPEXTRWZmr + 283438541U, // VPEXTRWZrr + 283438541U, // VPEXTRWZrr_REV + 1126477261U, // VPEXTRWmr + 283438541U, // VPEXTRWrr + 283438541U, // VPEXTRWrr_REV + 649545713U, // VPGATHERDDYrm + 3231156209U, // VPGATHERDDZ128rm + 3231172593U, // VPGATHERDDZ256rm + 3231188977U, // VPGATHERDDZrm + 643254257U, // VPGATHERDDrm + 649550613U, // VPGATHERDQYrm + 3231161109U, // VPGATHERDQZ128rm + 3231177493U, // VPGATHERDQZ256rm + 3231193877U, // VPGATHERDQZrm + 643259157U, // VPGATHERDQrm + 643255661U, // VPGATHERQDYrm + 553143661U, // VPGATHERQDZ128rm + 3231157613U, // VPGATHERQDZ256rm + 3231173997U, // VPGATHERQDZrm + 928468333U, // VPGATHERQDrm + 649551341U, // VPGATHERQQYrm + 3231161837U, // VPGATHERQQZ128rm + 3231178221U, // VPGATHERQQZ256rm + 3231194605U, // VPGATHERQQZrm + 643259885U, // VPGATHERQQrm + 264041U, // VPHADDBDrm + 551831401U, // VPHADDBDrr + 268682U, // VPHADDBQrm + 551836042U, // VPHADDBQrr + 273027U, // VPHADDBWrm + 551840387U, // VPHADDBWrr + 268902U, // VPHADDDQrm + 551836262U, // VPHADDDQrr + 812861356U, // VPHADDDYrm + 811648940U, // VPHADDDYrr + 811845548U, // VPHADDDrm + 811648940U, // VPHADDDrr + 812871181U, // VPHADDSWYrm + 811658765U, // VPHADDSWYrr + 811855373U, // VPHADDSWrm + 811658765U, // VPHADDSWrr + 264051U, // VPHADDUBDrm + 551831411U, // VPHADDUBDrr + 268700U, // VPHADDUBQrm + 551836060U, // VPHADDUBQrr + 273079U, // VPHADDUBWrm + 551840439U, // VPHADDUBWrr + 269196U, // VPHADDUDQrm + 551836556U, // VPHADDUDQrr + 266597U, // VPHADDUWDrm + 551833957U, // VPHADDUWDrr + 270507U, // VPHADDUWQrm + 551837867U, // VPHADDUWQrr + 266499U, // VPHADDWDrm + 551833859U, // VPHADDWDrr + 270482U, // VPHADDWQrm + 551837842U, // VPHADDWQrr + 812870432U, // VPHADDWYrm + 811658016U, // VPHADDWYrr + 811854624U, // VPHADDWrm + 811658016U, // VPHADDWrr + 274270U, // VPHMINPOSUWrm + 551841630U, // VPHMINPOSUWrr + 272987U, // VPHSUBBWrm + 551840347U, // VPHSUBBWrr + 268870U, // VPHSUBDQrm + 551836230U, // VPHSUBDQrr + 812861310U, // VPHSUBDYrm + 811648894U, // VPHSUBDYrr + 811845502U, // VPHSUBDrm + 811648894U, // VPHSUBDrr + 812871162U, // VPHSUBSWYrm + 811658746U, // VPHSUBSWYrr + 811855354U, // VPHSUBSWrm + 811658746U, // VPHSUBSWrr + 266489U, // VPHSUBWDrm + 551833849U, // VPHSUBWDrr + 812870338U, // VPHSUBWYrm + 811657922U, // VPHSUBWYrr + 811854530U, // VPHSUBWrm + 811657922U, // VPHSUBWrr + 879084925U, // VPINSRBZrm + 1088816509U, // VPINSRBZrr + 879084925U, // VPINSRBrm + 1088816509U, // VPINSRBrr + 881184208U, // VPINSRDZrm + 1088818640U, // VPINSRDZrr + 881184208U, // VPINSRDrm + 1088818640U, // VPINSRDrr + 866508425U, // VPINSRQZrm + 1088822921U, // VPINSRQZrr + 866508425U, // VPINSRQrm + 1088822921U, // VPINSRQrr + 331738536U, // VPINSRWZrm + 1088826792U, // VPINSRWZrr + 331738536U, // VPINSRWrm + 1088826792U, // VPINSRWrr + 266312U, // VPLZCNTDZ128rm + 629493832U, // VPLZCNTDZ128rmb + 630607944U, // VPLZCNTDZ128rmbk + 629231688U, // VPLZCNTDZ128rmbkz + 3230994504U, // VPLZCNTDZ128rmk + 3229864008U, // VPLZCNTDZ128rmkz + 551833672U, // VPLZCNTDZ128rr + 3230699592U, // VPLZCNTDZ128rrk + 3229667400U, // VPLZCNTDZ128rrkz + 552947784U, // VPLZCNTDZ256rm + 631590984U, // VPLZCNTDZ256rmb + 632705096U, // VPLZCNTDZ256rmbk + 631328840U, // VPLZCNTDZ256rmbkz + 3231027272U, // VPLZCNTDZ256rmk + 3230879816U, // VPLZCNTDZ256rmkz + 551833672U, // VPLZCNTDZ256rr + 3230699592U, // VPLZCNTDZ256rrk + 3229667400U, // VPLZCNTDZ256rrkz + 552439880U, // VPLZCNTDZrm + 633688136U, // VPLZCNTDZrmb + 634802248U, // VPLZCNTDZrmbk + 633425992U, // VPLZCNTDZrmbkz + 3231092808U, // VPLZCNTDZrmk + 3230896200U, // VPLZCNTDZrmkz + 551833672U, // VPLZCNTDZrr + 3230699592U, // VPLZCNTDZrrk + 3229667400U, // VPLZCNTDZrrkz + 270240U, // VPLZCNTQZ128rm + 627416992U, // VPLZCNTQZ128rmb + 628416416U, // VPLZCNTQZ128rmbk + 627154848U, // VPLZCNTQZ128rmbkz + 3230998432U, // VPLZCNTQZ128rmk + 3229867936U, // VPLZCNTQZ128rmkz + 551837600U, // VPLZCNTQZ128rr + 3230703520U, // VPLZCNTQZ128rrk + 3229671328U, // VPLZCNTQZ128rrkz + 552951712U, // VPLZCNTQZ256rm + 629514144U, // VPLZCNTQZ256rmb + 630513568U, // VPLZCNTQZ256rmbk + 629252000U, // VPLZCNTQZ256rmbkz + 3231031200U, // VPLZCNTQZ256rmk + 3230883744U, // VPLZCNTQZ256rmkz + 551837600U, // VPLZCNTQZ256rr + 3230703520U, // VPLZCNTQZ256rrk + 3229671328U, // VPLZCNTQZ256rrkz + 552443808U, // VPLZCNTQZrm + 631611296U, // VPLZCNTQZrmb + 632610720U, // VPLZCNTQZrmbk + 631349152U, // VPLZCNTQZrmbkz + 3231096736U, // VPLZCNTQZrmk + 3230900128U, // VPLZCNTQZrmkz + 551837600U, // VPLZCNTQZrr + 3230703520U, // VPLZCNTQZrrk + 3229671328U, // VPLZCNTQZrrkz + 326387731U, // VPMACSDDrm + 890275859U, // VPMACSDDrr + 326390377U, // VPMACSDQHrm + 890278505U, // VPMACSDQHrr + 326391321U, // VPMACSDQLrm + 890279449U, // VPMACSDQLrr + 326387741U, // VPMACSSDDrm + 890275869U, // VPMACSSDDrr + 326390388U, // VPMACSSDQHrm + 890278516U, // VPMACSSDQHrr + 326391332U, // VPMACSSDQLrm + 890279460U, // VPMACSSDQLrr + 326390094U, // VPMACSSWDrm + 890278222U, // VPMACSSWDrr + 326397897U, // VPMACSSWWrm + 890286025U, // VPMACSSWWrr + 326390073U, // VPMACSWDrm + 890278201U, // VPMACSWDrr + 326397873U, // VPMACSWWrm + 890286001U, // VPMACSWWrr + 326390105U, // VPMADCSSWDrm + 890278233U, // VPMADCSSWDrr + 326390083U, // VPMADCSWDrm + 890278211U, // VPMADCSWDrr + 890576889U, // VPMADD52HUQZ128m + 1165287417U, // VPMADD52HUQZ128mb + 1433952249U, // VPMADD52HUQZ128mbk + 1433952249U, // VPMADD52HUQZ128mbkz + 985112569U, // VPMADD52HUQZ128mk + 985112569U, // VPMADD52HUQZ128mkz + 890281977U, // VPMADD52HUQZ128r + 87056377U, // VPMADD52HUQZ128rk + 89153529U, // VPMADD52HUQZ128rkz + 890609657U, // VPMADD52HUQZ256m + 1167384569U, // VPMADD52HUQZ256mb + 1436049401U, // VPMADD52HUQZ256mbk + 1436049401U, // VPMADD52HUQZ256mbkz + 985128953U, // VPMADD52HUQZ256mk + 985128953U, // VPMADD52HUQZ256mkz + 890281977U, // VPMADD52HUQZ256r + 87056377U, // VPMADD52HUQZ256rk + 89153529U, // VPMADD52HUQZ256rkz + 890675193U, // VPMADD52HUQZm + 1169481721U, // VPMADD52HUQZmb + 1438146553U, // VPMADD52HUQZmbk + 1438146553U, // VPMADD52HUQZmbkz + 985145337U, // VPMADD52HUQZmk + 985145337U, // VPMADD52HUQZmkz + 890281977U, // VPMADD52HUQZr + 87056377U, // VPMADD52HUQZrk + 89153529U, // VPMADD52HUQZrkz + 890576902U, // VPMADD52LUQZ128m + 1165287430U, // VPMADD52LUQZ128mb + 1433952262U, // VPMADD52LUQZ128mbk + 1433952262U, // VPMADD52LUQZ128mbkz + 985112582U, // VPMADD52LUQZ128mk + 985112582U, // VPMADD52LUQZ128mkz + 890281990U, // VPMADD52LUQZ128r + 87056390U, // VPMADD52LUQZ128rk + 89153542U, // VPMADD52LUQZ128rkz + 890609670U, // VPMADD52LUQZ256m + 1167384582U, // VPMADD52LUQZ256mb + 1436049414U, // VPMADD52LUQZ256mbk + 1436049414U, // VPMADD52LUQZ256mbkz + 985128966U, // VPMADD52LUQZ256mk + 985128966U, // VPMADD52LUQZ256mkz + 890281990U, // VPMADD52LUQZ256r + 87056390U, // VPMADD52LUQZ256rk + 89153542U, // VPMADD52LUQZ256rkz + 890675206U, // VPMADD52LUQZm + 1169481734U, // VPMADD52LUQZmb + 1438146566U, // VPMADD52LUQZmbk + 1438146566U, // VPMADD52LUQZmbkz + 985145350U, // VPMADD52LUQZmk + 985145350U, // VPMADD52LUQZmkz + 890281990U, // VPMADD52LUQZr + 87056390U, // VPMADD52LUQZrk + 89153542U, // VPMADD52LUQZrkz + 812871150U, // VPMADDUBSWYrm + 811658734U, // VPMADDUBSWYrr + 811855342U, // VPMADDUBSWZ128rm + 985116142U, // VPMADDUBSWZ128rmk + 890580462U, // VPMADDUBSWZ128rmkz + 811658734U, // VPMADDUBSWZ128rr + 87059950U, // VPMADDUBSWZ128rrk + 890285550U, // VPMADDUBSWZ128rrkz + 812871150U, // VPMADDUBSWZ256rm + 985132526U, // VPMADDUBSWZ256rmk + 890613230U, // VPMADDUBSWZ256rmkz + 811658734U, // VPMADDUBSWZ256rr + 87059950U, // VPMADDUBSWZ256rrk + 890285550U, // VPMADDUBSWZ256rrkz + 812887534U, // VPMADDUBSWZrm + 985148910U, // VPMADDUBSWZrmk + 890678766U, // VPMADDUBSWZrmkz + 811658734U, // VPMADDUBSWZrr + 87059950U, // VPMADDUBSWZrrk + 890285550U, // VPMADDUBSWZrrkz + 811855342U, // VPMADDUBSWrm + 811658734U, // VPMADDUBSWrr + 812863757U, // VPMADDWDYrm + 811651341U, // VPMADDWDYrr + 811847949U, // VPMADDWDZ128rm + 985108749U, // VPMADDWDZ128rmk + 890573069U, // VPMADDWDZ128rmkz + 811651341U, // VPMADDWDZ128rr + 87052557U, // VPMADDWDZ128rrk + 890278157U, // VPMADDWDZ128rrkz + 812863757U, // VPMADDWDZ256rm + 985125133U, // VPMADDWDZ256rmk + 890605837U, // VPMADDWDZ256rmkz + 811651341U, // VPMADDWDZ256rr + 87052557U, // VPMADDWDZ256rrk + 890278157U, // VPMADDWDZ256rrkz + 812880141U, // VPMADDWDZrm + 985141517U, // VPMADDWDZrmk + 890671373U, // VPMADDWDZrmkz + 811651341U, // VPMADDWDZrr + 87052557U, // VPMADDWDZrrk + 890278157U, // VPMADDWDZrrkz + 811847949U, // VPMADDWDrm + 811651341U, // VPMADDWDrr + 2200244445U, // VPMASKMOVDYmr + 812863709U, // VPMASKMOVDYrm + 1931808989U, // VPMASKMOVDmr + 811847901U, // VPMASKMOVDrm + 2200248438U, // VPMASKMOVQYmr + 812867702U, // VPMASKMOVQYrm + 1931812982U, // VPMASKMOVQmr + 811851894U, // VPMASKMOVQrm + 812860946U, // VPMAXSBYrm + 811648530U, // VPMAXSBYrr + 811845138U, // VPMAXSBZ128rm + 985105938U, // VPMAXSBZ128rmk + 890570258U, // VPMAXSBZ128rmkz + 811648530U, // VPMAXSBZ128rr + 87049746U, // VPMAXSBZ128rrk + 890275346U, // VPMAXSBZ128rrkz + 812860946U, // VPMAXSBZ256rm + 985122322U, // VPMAXSBZ256rmk + 890603026U, // VPMAXSBZ256rmkz + 811648530U, // VPMAXSBZ256rr + 87049746U, // VPMAXSBZ256rrk + 890275346U, // VPMAXSBZ256rrkz + 812877330U, // VPMAXSBZrm + 985138706U, // VPMAXSBZrmk + 890668562U, // VPMAXSBZrmkz + 811648530U, // VPMAXSBZrr + 87049746U, // VPMAXSBZrrk + 890275346U, // VPMAXSBZrrkz + 811845138U, // VPMAXSBrm + 811648530U, // VPMAXSBrr + 812863501U, // VPMAXSDYrm + 811651085U, // VPMAXSDYrr + 811847693U, // VPMAXSDZ128rm + 360796173U, // VPMAXSDZ128rmb + 1436061709U, // VPMAXSDZ128rmbk + 1167478797U, // VPMAXSDZ128rmbkz + 985108493U, // VPMAXSDZ128rmk + 890572813U, // VPMAXSDZ128rmkz + 811651085U, // VPMAXSDZ128rr + 87052301U, // VPMAXSDZ128rrk + 890277901U, // VPMAXSDZ128rrkz + 812863501U, // VPMAXSDZ256rm + 362893325U, // VPMAXSDZ256rmb + 1438158861U, // VPMAXSDZ256rmbk + 1169575949U, // VPMAXSDZ256rmbkz + 985124877U, // VPMAXSDZ256rmk + 890605581U, // VPMAXSDZ256rmkz + 811651085U, // VPMAXSDZ256rr + 87052301U, // VPMAXSDZ256rrk + 890277901U, // VPMAXSDZ256rrkz + 812879885U, // VPMAXSDZrm + 364990477U, // VPMAXSDZrmb + 1440256013U, // VPMAXSDZrmbk + 1171673101U, // VPMAXSDZrmbkz + 985141261U, // VPMAXSDZrmk + 890671117U, // VPMAXSDZrmkz + 811651085U, // VPMAXSDZrr + 87052301U, // VPMAXSDZrrk + 890277901U, // VPMAXSDZrrkz + 811847693U, // VPMAXSDrm + 811651085U, // VPMAXSDrr + 811851591U, // VPMAXSQZ128rm + 358719303U, // VPMAXSQZ128rmb + 1433952071U, // VPMAXSQZ128rmbk + 1165287239U, // VPMAXSQZ128rmbkz + 985112391U, // VPMAXSQZ128rmk + 890576711U, // VPMAXSQZ128rmkz + 811654983U, // VPMAXSQZ128rr + 87056199U, // VPMAXSQZ128rrk + 890281799U, // VPMAXSQZ128rrkz + 812867399U, // VPMAXSQZ256rm + 360816455U, // VPMAXSQZ256rmb + 1436049223U, // VPMAXSQZ256rmbk + 1167384391U, // VPMAXSQZ256rmbkz + 985128775U, // VPMAXSQZ256rmk + 890609479U, // VPMAXSQZ256rmkz + 811654983U, // VPMAXSQZ256rr + 87056199U, // VPMAXSQZ256rrk + 890281799U, // VPMAXSQZ256rrkz + 812883783U, // VPMAXSQZrm + 362913607U, // VPMAXSQZrmb + 1438146375U, // VPMAXSQZrmbk + 1169481543U, // VPMAXSQZrmbkz + 985145159U, // VPMAXSQZrmk + 890675015U, // VPMAXSQZrmkz + 811654983U, // VPMAXSQZrr + 87056199U, // VPMAXSQZrrk + 890281799U, // VPMAXSQZrrkz + 812871335U, // VPMAXSWYrm + 811658919U, // VPMAXSWYrr + 811855527U, // VPMAXSWZ128rm + 985116327U, // VPMAXSWZ128rmk + 890580647U, // VPMAXSWZ128rmkz + 811658919U, // VPMAXSWZ128rr + 87060135U, // VPMAXSWZ128rrk + 890285735U, // VPMAXSWZ128rrkz + 812871335U, // VPMAXSWZ256rm + 985132711U, // VPMAXSWZ256rmk + 890613415U, // VPMAXSWZ256rmkz + 811658919U, // VPMAXSWZ256rr + 87060135U, // VPMAXSWZ256rrk + 890285735U, // VPMAXSWZ256rrkz + 812887719U, // VPMAXSWZrm + 985149095U, // VPMAXSWZrmk + 890678951U, // VPMAXSWZrmkz + 811658919U, // VPMAXSWZrr + 87060135U, // VPMAXSWZrrk + 890285735U, // VPMAXSWZrrkz + 811855527U, // VPMAXSWrm + 811658919U, // VPMAXSWrr + 812861062U, // VPMAXUBYrm + 811648646U, // VPMAXUBYrr + 811845254U, // VPMAXUBZ128rm + 985106054U, // VPMAXUBZ128rmk + 890570374U, // VPMAXUBZ128rmkz + 811648646U, // VPMAXUBZ128rr + 87049862U, // VPMAXUBZ128rrk + 890275462U, // VPMAXUBZ128rrkz + 812861062U, // VPMAXUBZ256rm + 985122438U, // VPMAXUBZ256rmk + 890603142U, // VPMAXUBZ256rmkz + 811648646U, // VPMAXUBZ256rr + 87049862U, // VPMAXUBZ256rrk + 890275462U, // VPMAXUBZ256rrkz + 812877446U, // VPMAXUBZrm + 985138822U, // VPMAXUBZrmk + 890668678U, // VPMAXUBZrmkz + 811648646U, // VPMAXUBZrr + 87049862U, // VPMAXUBZrrk + 890275462U, // VPMAXUBZrrkz + 811845254U, // VPMAXUBrm + 811648646U, // VPMAXUBrr + 812863644U, // VPMAXUDYrm + 811651228U, // VPMAXUDYrr + 811847836U, // VPMAXUDZ128rm + 360796316U, // VPMAXUDZ128rmb + 1436061852U, // VPMAXUDZ128rmbk + 1167478940U, // VPMAXUDZ128rmbkz + 985108636U, // VPMAXUDZ128rmk + 890572956U, // VPMAXUDZ128rmkz + 811651228U, // VPMAXUDZ128rr + 87052444U, // VPMAXUDZ128rrk + 890278044U, // VPMAXUDZ128rrkz + 812863644U, // VPMAXUDZ256rm + 362893468U, // VPMAXUDZ256rmb + 1438159004U, // VPMAXUDZ256rmbk + 1169576092U, // VPMAXUDZ256rmbkz + 985125020U, // VPMAXUDZ256rmk + 890605724U, // VPMAXUDZ256rmkz + 811651228U, // VPMAXUDZ256rr + 87052444U, // VPMAXUDZ256rrk + 890278044U, // VPMAXUDZ256rrkz + 812880028U, // VPMAXUDZrm + 364990620U, // VPMAXUDZrmb + 1440256156U, // VPMAXUDZrmbk + 1171673244U, // VPMAXUDZrmbkz + 985141404U, // VPMAXUDZrmk + 890671260U, // VPMAXUDZrmkz + 811651228U, // VPMAXUDZrr + 87052444U, // VPMAXUDZrrk + 890278044U, // VPMAXUDZrrkz + 811847836U, // VPMAXUDrm + 811651228U, // VPMAXUDrr + 811851822U, // VPMAXUQZ128rm + 358719534U, // VPMAXUQZ128rmb + 1433952302U, // VPMAXUQZ128rmbk + 1165287470U, // VPMAXUQZ128rmbkz + 985112622U, // VPMAXUQZ128rmk + 890576942U, // VPMAXUQZ128rmkz + 811655214U, // VPMAXUQZ128rr + 87056430U, // VPMAXUQZ128rrk + 890282030U, // VPMAXUQZ128rrkz + 812867630U, // VPMAXUQZ256rm + 360816686U, // VPMAXUQZ256rmb + 1436049454U, // VPMAXUQZ256rmbk + 1167384622U, // VPMAXUQZ256rmbkz + 985129006U, // VPMAXUQZ256rmk + 890609710U, // VPMAXUQZ256rmkz + 811655214U, // VPMAXUQZ256rr + 87056430U, // VPMAXUQZ256rrk + 890282030U, // VPMAXUQZ256rrkz + 812884014U, // VPMAXUQZrm + 362913838U, // VPMAXUQZrmb + 1438146606U, // VPMAXUQZrmbk + 1169481774U, // VPMAXUQZrmbkz + 985145390U, // VPMAXUQZrmk + 890675246U, // VPMAXUQZrmkz + 811655214U, // VPMAXUQZrr + 87056430U, // VPMAXUQZrrk + 890282030U, // VPMAXUQZrrkz + 812871531U, // VPMAXUWYrm + 811659115U, // VPMAXUWYrr + 811855723U, // VPMAXUWZ128rm + 985116523U, // VPMAXUWZ128rmk + 890580843U, // VPMAXUWZ128rmkz + 811659115U, // VPMAXUWZ128rr + 87060331U, // VPMAXUWZ128rrk + 890285931U, // VPMAXUWZ128rrkz + 812871531U, // VPMAXUWZ256rm + 985132907U, // VPMAXUWZ256rmk + 890613611U, // VPMAXUWZ256rmkz + 811659115U, // VPMAXUWZ256rr + 87060331U, // VPMAXUWZ256rrk + 890285931U, // VPMAXUWZ256rrkz + 812887915U, // VPMAXUWZrm + 985149291U, // VPMAXUWZrmk + 890679147U, // VPMAXUWZrmkz + 811659115U, // VPMAXUWZrr + 87060331U, // VPMAXUWZrrk + 890285931U, // VPMAXUWZrrkz + 811855723U, // VPMAXUWrm + 811659115U, // VPMAXUWrr + 812860874U, // VPMINSBYrm + 811648458U, // VPMINSBYrr + 811845066U, // VPMINSBZ128rm + 985105866U, // VPMINSBZ128rmk + 890570186U, // VPMINSBZ128rmkz + 811648458U, // VPMINSBZ128rr + 87049674U, // VPMINSBZ128rrk + 890275274U, // VPMINSBZ128rrkz + 812860874U, // VPMINSBZ256rm + 985122250U, // VPMINSBZ256rmk + 890602954U, // VPMINSBZ256rmkz + 811648458U, // VPMINSBZ256rr + 87049674U, // VPMINSBZ256rrk + 890275274U, // VPMINSBZ256rrkz + 812877258U, // VPMINSBZrm + 985138634U, // VPMINSBZrmk + 890668490U, // VPMINSBZrmkz + 811648458U, // VPMINSBZrr + 87049674U, // VPMINSBZrrk + 890275274U, // VPMINSBZrrkz + 811845066U, // VPMINSBrm + 811648458U, // VPMINSBrr + 812863334U, // VPMINSDYrm + 811650918U, // VPMINSDYrr + 811847526U, // VPMINSDZ128rm + 360796006U, // VPMINSDZ128rmb + 1436061542U, // VPMINSDZ128rmbk + 1167478630U, // VPMINSDZ128rmbkz + 985108326U, // VPMINSDZ128rmk + 890572646U, // VPMINSDZ128rmkz + 811650918U, // VPMINSDZ128rr + 87052134U, // VPMINSDZ128rrk + 890277734U, // VPMINSDZ128rrkz + 812863334U, // VPMINSDZ256rm + 362893158U, // VPMINSDZ256rmb + 1438158694U, // VPMINSDZ256rmbk + 1169575782U, // VPMINSDZ256rmbkz + 985124710U, // VPMINSDZ256rmk + 890605414U, // VPMINSDZ256rmkz + 811650918U, // VPMINSDZ256rr + 87052134U, // VPMINSDZ256rrk + 890277734U, // VPMINSDZ256rrkz + 812879718U, // VPMINSDZrm + 364990310U, // VPMINSDZrmb + 1440255846U, // VPMINSDZrmbk + 1171672934U, // VPMINSDZrmbkz + 985141094U, // VPMINSDZrmk + 890670950U, // VPMINSDZrmkz + 811650918U, // VPMINSDZrr + 87052134U, // VPMINSDZrrk + 890277734U, // VPMINSDZrrkz + 811847526U, // VPMINSDrm + 811650918U, // VPMINSDrr + 811851493U, // VPMINSQZ128rm + 358719205U, // VPMINSQZ128rmb + 1433951973U, // VPMINSQZ128rmbk + 1165287141U, // VPMINSQZ128rmbkz + 985112293U, // VPMINSQZ128rmk + 890576613U, // VPMINSQZ128rmkz + 811654885U, // VPMINSQZ128rr + 87056101U, // VPMINSQZ128rrk + 890281701U, // VPMINSQZ128rrkz + 812867301U, // VPMINSQZ256rm + 360816357U, // VPMINSQZ256rmb + 1436049125U, // VPMINSQZ256rmbk + 1167384293U, // VPMINSQZ256rmbkz + 985128677U, // VPMINSQZ256rmk + 890609381U, // VPMINSQZ256rmkz + 811654885U, // VPMINSQZ256rr + 87056101U, // VPMINSQZ256rrk + 890281701U, // VPMINSQZ256rrkz + 812883685U, // VPMINSQZrm + 362913509U, // VPMINSQZrmb + 1438146277U, // VPMINSQZrmbk + 1169481445U, // VPMINSQZrmbkz + 985145061U, // VPMINSQZrmk + 890674917U, // VPMINSQZrmkz + 811654885U, // VPMINSQZrr + 87056101U, // VPMINSQZrrk + 890281701U, // VPMINSQZrrkz + 812871231U, // VPMINSWYrm + 811658815U, // VPMINSWYrr + 811855423U, // VPMINSWZ128rm + 985116223U, // VPMINSWZ128rmk + 890580543U, // VPMINSWZ128rmkz + 811658815U, // VPMINSWZ128rr + 87060031U, // VPMINSWZ128rrk + 890285631U, // VPMINSWZ128rrkz + 812871231U, // VPMINSWZ256rm + 985132607U, // VPMINSWZ256rmk + 890613311U, // VPMINSWZ256rmkz + 811658815U, // VPMINSWZ256rr + 87060031U, // VPMINSWZ256rrk + 890285631U, // VPMINSWZ256rrkz + 812887615U, // VPMINSWZrm + 985148991U, // VPMINSWZrmk + 890678847U, // VPMINSWZrmkz + 811658815U, // VPMINSWZrr + 87060031U, // VPMINSWZrrk + 890285631U, // VPMINSWZrrkz + 811855423U, // VPMINSWrm + 811658815U, // VPMINSWrr + 812861037U, // VPMINUBYrm + 811648621U, // VPMINUBYrr + 811845229U, // VPMINUBZ128rm + 985106029U, // VPMINUBZ128rmk + 890570349U, // VPMINUBZ128rmkz + 811648621U, // VPMINUBZ128rr + 87049837U, // VPMINUBZ128rrk + 890275437U, // VPMINUBZ128rrkz + 812861037U, // VPMINUBZ256rm + 985122413U, // VPMINUBZ256rmk + 890603117U, // VPMINUBZ256rmkz + 811648621U, // VPMINUBZ256rr + 87049837U, // VPMINUBZ256rrk + 890275437U, // VPMINUBZ256rrkz + 812877421U, // VPMINUBZrm + 985138797U, // VPMINUBZrmk + 890668653U, // VPMINUBZrmkz + 811648621U, // VPMINUBZrr + 87049837U, // VPMINUBZrrk + 890275437U, // VPMINUBZrrkz + 811845229U, // VPMINUBrm + 811648621U, // VPMINUBrr + 812863626U, // VPMINUDYrm + 811651210U, // VPMINUDYrr + 811847818U, // VPMINUDZ128rm + 360796298U, // VPMINUDZ128rmb + 1436061834U, // VPMINUDZ128rmbk + 1167478922U, // VPMINUDZ128rmbkz + 985108618U, // VPMINUDZ128rmk + 890572938U, // VPMINUDZ128rmkz + 811651210U, // VPMINUDZ128rr + 87052426U, // VPMINUDZ128rrk + 890278026U, // VPMINUDZ128rrkz + 812863626U, // VPMINUDZ256rm + 362893450U, // VPMINUDZ256rmb + 1438158986U, // VPMINUDZ256rmbk + 1169576074U, // VPMINUDZ256rmbkz + 985125002U, // VPMINUDZ256rmk + 890605706U, // VPMINUDZ256rmkz + 811651210U, // VPMINUDZ256rr + 87052426U, // VPMINUDZ256rrk + 890278026U, // VPMINUDZ256rrkz + 812880010U, // VPMINUDZrm + 364990602U, // VPMINUDZrmb + 1440256138U, // VPMINUDZrmbk + 1171673226U, // VPMINUDZrmbkz + 985141386U, // VPMINUDZrmk + 890671242U, // VPMINUDZrmkz + 811651210U, // VPMINUDZrr + 87052426U, // VPMINUDZrrk + 890278026U, // VPMINUDZrrkz + 811847818U, // VPMINUDrm + 811651210U, // VPMINUDrr + 811851804U, // VPMINUQZ128rm + 358719516U, // VPMINUQZ128rmb + 1433952284U, // VPMINUQZ128rmbk + 1165287452U, // VPMINUQZ128rmbkz + 985112604U, // VPMINUQZ128rmk + 890576924U, // VPMINUQZ128rmkz + 811655196U, // VPMINUQZ128rr + 87056412U, // VPMINUQZ128rrk + 890282012U, // VPMINUQZ128rrkz + 812867612U, // VPMINUQZ256rm + 360816668U, // VPMINUQZ256rmb + 1436049436U, // VPMINUQZ256rmbk + 1167384604U, // VPMINUQZ256rmbkz + 985128988U, // VPMINUQZ256rmk + 890609692U, // VPMINUQZ256rmkz + 811655196U, // VPMINUQZ256rr + 87056412U, // VPMINUQZ256rrk + 890282012U, // VPMINUQZ256rrkz + 812883996U, // VPMINUQZrm + 362913820U, // VPMINUQZrmb + 1438146588U, // VPMINUQZrmbk + 1169481756U, // VPMINUQZrmbkz + 985145372U, // VPMINUQZrmk + 890675228U, // VPMINUQZrmkz + 811655196U, // VPMINUQZrr + 87056412U, // VPMINUQZrrk + 890282012U, // VPMINUQZrrkz + 812871500U, // VPMINUWYrm + 811659084U, // VPMINUWYrr + 811855692U, // VPMINUWZ128rm + 985116492U, // VPMINUWZ128rmk + 890580812U, // VPMINUWZ128rmkz + 811659084U, // VPMINUWZ128rr + 87060300U, // VPMINUWZ128rrk + 890285900U, // VPMINUWZ128rrkz + 812871500U, // VPMINUWZ256rm + 985132876U, // VPMINUWZ256rmk + 890613580U, // VPMINUWZ256rmkz + 811659084U, // VPMINUWZ256rr + 87060300U, // VPMINUWZ256rrk + 890285900U, // VPMINUWZ256rrkz + 812887884U, // VPMINUWZrm + 985149260U, // VPMINUWZrmk + 890679116U, // VPMINUWZrmkz + 811659084U, // VPMINUWZrr + 87060300U, // VPMINUWZrrk + 890285900U, // VPMINUWZrrkz + 811855692U, // VPMINUWrm + 811659084U, // VPMINUWrr + 551835633U, // VPMOVB2MZ128rr + 551835633U, // VPMOVB2MZ256rr + 551835633U, // VPMOVB2MZrr + 551835643U, // VPMOVD2MZ128rr + 551835643U, // VPMOVD2MZ256rr + 551835643U, // VPMOVD2MZrr + 12616736U, // VPMOVDBZ128mr + 3234137120U, // VPMOVDBZ128mrk + 551830560U, // VPMOVDBZ128rr + 3230696480U, // VPMOVDBZ128rrk + 3229664288U, // VPMOVDBZ128rrkz + 18908192U, // VPMOVDBZ256mr + 3240428576U, // VPMOVDBZ256mrk + 551830560U, // VPMOVDBZ256rr + 3230696480U, // VPMOVDBZ256rrk + 3229664288U, // VPMOVDBZ256rrkz + 33588256U, // VPMOVDBZmr + 3255108640U, // VPMOVDBZmrk + 551830560U, // VPMOVDBZrr + 3230696480U, // VPMOVDBZrrk + 3229664288U, // VPMOVDBZrrkz + 18918314U, // VPMOVDWZ128mr + 3240438698U, // VPMOVDWZ128mrk + 551840682U, // VPMOVDWZ128rr + 3230706602U, // VPMOVDWZ128rrk + 3229674410U, // VPMOVDWZ128rrkz + 33598378U, // VPMOVDWZ256mr + 3255118762U, // VPMOVDWZ256mrk + 551840682U, // VPMOVDWZ256rr + 3230706602U, // VPMOVDWZ256rrk + 3229674410U, // VPMOVDWZ256rrkz + 180399018U, // VPMOVDWZmr + 3401919402U, // VPMOVDWZmrk + 551840682U, // VPMOVDWZrr + 3230706602U, // VPMOVDWZrrk + 3229674410U, // VPMOVDWZrrkz + 551830389U, // VPMOVM2BZ128rr + 551830389U, // VPMOVM2BZ256rr + 551830389U, // VPMOVM2BZrr + 551831343U, // VPMOVM2DZ128rr + 551831343U, // VPMOVM2DZ256rr + 551831343U, // VPMOVM2DZrr + 551835977U, // VPMOVM2QZ128rr + 551835977U, // VPMOVM2QZ256rr + 551835977U, // VPMOVM2QZrr + 551840291U, // VPMOVM2WZ128rr + 551840291U, // VPMOVM2WZ256rr + 551840291U, // VPMOVM2WZrr + 551830606U, // VPMOVMSKBYrr + 551830606U, // VPMOVMSKBrr + 551835653U, // VPMOVQ2MZ128rr + 551835653U, // VPMOVQ2MZ256rr + 551835653U, // VPMOVQ2MZrr + 4228423U, // VPMOVQBZ128mr + 3225748807U, // VPMOVQBZ128mrk + 551830855U, // VPMOVQBZ128rr + 3230696775U, // VPMOVQBZ128rrk + 3229664583U, // VPMOVQBZ128rrkz + 12617031U, // VPMOVQBZ256mr + 3234137415U, // VPMOVQBZ256mrk + 551830855U, // VPMOVQBZ256rr + 3230696775U, // VPMOVQBZ256rrk + 3229664583U, // VPMOVQBZ256rrkz + 18908487U, // VPMOVQBZmr + 3240428871U, // VPMOVQBZmrk + 551830855U, // VPMOVQBZrr + 3230696775U, // VPMOVQBZrrk + 3229664583U, // VPMOVQBZrrkz + 18910619U, // VPMOVQDZ128mr + 3240431003U, // VPMOVQDZ128mrk + 551832987U, // VPMOVQDZ128rr + 3230698907U, // VPMOVQDZ128rrk + 3229666715U, // VPMOVQDZ128rrkz + 33590683U, // VPMOVQDZ256mr + 3255111067U, // VPMOVQDZ256mrk + 551832987U, // VPMOVQDZ256rr + 3230698907U, // VPMOVQDZ256rrk + 3229666715U, // VPMOVQDZ256rrkz + 180391323U, // VPMOVQDZmr + 3401911707U, // VPMOVQDZmrk + 551832987U, // VPMOVQDZrr + 3230698907U, // VPMOVQDZrrk + 3229666715U, // VPMOVQDZrrkz + 12627287U, // VPMOVQWZ128mr + 3234147671U, // VPMOVQWZ128mrk + 551841111U, // VPMOVQWZ128rr + 3230707031U, // VPMOVQWZ128rrk + 3229674839U, // VPMOVQWZ128rrkz + 18918743U, // VPMOVQWZ256mr + 3240439127U, // VPMOVQWZ256mrk + 551841111U, // VPMOVQWZ256rr + 3230707031U, // VPMOVQWZ256rrk + 3229674839U, // VPMOVQWZ256rrkz + 33598807U, // VPMOVQWZmr + 3255119191U, // VPMOVQWZmrk + 551841111U, // VPMOVQWZrr + 3230707031U, // VPMOVQWZrrk + 3229674839U, // VPMOVQWZrrkz + 12616726U, // VPMOVSDBZ128mr + 3234137110U, // VPMOVSDBZ128mrk + 551830550U, // VPMOVSDBZ128rr + 3230696470U, // VPMOVSDBZ128rrk + 3229664278U, // VPMOVSDBZ128rrkz + 18908182U, // VPMOVSDBZ256mr + 3240428566U, // VPMOVSDBZ256mrk + 551830550U, // VPMOVSDBZ256rr + 3230696470U, // VPMOVSDBZ256rrk + 3229664278U, // VPMOVSDBZ256rrkz + 33588246U, // VPMOVSDBZmr + 3255108630U, // VPMOVSDBZmrk + 551830550U, // VPMOVSDBZrr + 3230696470U, // VPMOVSDBZrrk + 3229664278U, // VPMOVSDBZrrkz + 18918304U, // VPMOVSDWZ128mr + 3240438688U, // VPMOVSDWZ128mrk + 551840672U, // VPMOVSDWZ128rr + 3230706592U, // VPMOVSDWZ128rrk + 3229674400U, // VPMOVSDWZ128rrkz + 33598368U, // VPMOVSDWZ256mr + 3255118752U, // VPMOVSDWZ256mrk + 551840672U, // VPMOVSDWZ256rr + 3230706592U, // VPMOVSDWZ256rrk + 3229674400U, // VPMOVSDWZ256rrkz + 180399008U, // VPMOVSDWZmr + 3401919392U, // VPMOVSDWZmrk + 551840672U, // VPMOVSDWZrr + 3230706592U, // VPMOVSDWZrrk + 3229674400U, // VPMOVSDWZrrkz + 4228378U, // VPMOVSQBZ128mr + 3225748762U, // VPMOVSQBZ128mrk + 551830810U, // VPMOVSQBZ128rr + 3230696730U, // VPMOVSQBZ128rrk + 3229664538U, // VPMOVSQBZ128rrkz + 12616986U, // VPMOVSQBZ256mr + 3234137370U, // VPMOVSQBZ256mrk + 551830810U, // VPMOVSQBZ256rr + 3230696730U, // VPMOVSQBZ256rrk + 3229664538U, // VPMOVSQBZ256rrkz + 18908442U, // VPMOVSQBZmr + 3240428826U, // VPMOVSQBZmrk + 551830810U, // VPMOVSQBZrr + 3230696730U, // VPMOVSQBZrrk + 3229664538U, // VPMOVSQBZrrkz + 18910609U, // VPMOVSQDZ128mr + 3240430993U, // VPMOVSQDZ128mrk + 551832977U, // VPMOVSQDZ128rr + 3230698897U, // VPMOVSQDZ128rrk + 3229666705U, // VPMOVSQDZ128rrkz + 33590673U, // VPMOVSQDZ256mr + 3255111057U, // VPMOVSQDZ256mrk + 551832977U, // VPMOVSQDZ256rr + 3230698897U, // VPMOVSQDZ256rrk + 3229666705U, // VPMOVSQDZ256rrkz + 180391313U, // VPMOVSQDZmr + 3401911697U, // VPMOVSQDZmrk + 551832977U, // VPMOVSQDZrr + 3230698897U, // VPMOVSQDZrrk + 3229666705U, // VPMOVSQDZrrkz + 12627277U, // VPMOVSQWZ128mr + 3234147661U, // VPMOVSQWZ128mrk + 551841101U, // VPMOVSQWZ128rr + 3230707021U, // VPMOVSQWZ128rrk + 3229674829U, // VPMOVSQWZ128rrkz + 18918733U, // VPMOVSQWZ256mr + 3240439117U, // VPMOVSQWZ256mrk + 551841101U, // VPMOVSQWZ256rr + 3230707021U, // VPMOVSQWZ256rrk + 3229674829U, // VPMOVSQWZ256rrkz + 33598797U, // VPMOVSQWZmr + 3255119181U, // VPMOVSQWZmrk + 551841101U, // VPMOVSQWZrr + 3230707021U, // VPMOVSQWZrrk + 3229674829U, // VPMOVSQWZrrkz + 18908887U, // VPMOVSWBZ128mr + 3240429271U, // VPMOVSWBZ128mrk + 551831255U, // VPMOVSWBZ128rr + 3230697175U, // VPMOVSWBZ128rrk + 3229664983U, // VPMOVSWBZ128rrkz + 33588951U, // VPMOVSWBZ256mr + 3255109335U, // VPMOVSWBZ256mrk + 551831255U, // VPMOVSWBZ256rr + 3230697175U, // VPMOVSWBZ256rrk + 3229664983U, // VPMOVSWBZ256rrkz + 180389591U, // VPMOVSWBZmr + 3401909975U, // VPMOVSWBZmrk + 551831255U, // VPMOVSWBZrr + 3230697175U, // VPMOVSWBZrrk + 3229664983U, // VPMOVSWBZrrkz + 551913359U, // VPMOVSXBDYrm + 551831439U, // VPMOVSXBDYrr + 551896975U, // VPMOVSXBDZ128rm + 553011087U, // VPMOVSXBDZ128rmk + 551634831U, // VPMOVSXBDZ128rmkz + 551831439U, // VPMOVSXBDZ128rr + 3230697359U, // VPMOVSXBDZ128rrk + 3229665167U, // VPMOVSXBDZ128rrkz + 551913359U, // VPMOVSXBDZ256rm + 552912783U, // VPMOVSXBDZ256rmk + 551651215U, // VPMOVSXBDZ256rmkz + 551831439U, // VPMOVSXBDZ256rr + 3230697359U, // VPMOVSXBDZ256rrk + 3229665167U, // VPMOVSXBDZ256rrkz + 264079U, // VPMOVSXBDZrm + 3230992271U, // VPMOVSXBDZrmk + 3229861775U, // VPMOVSXBDZrmkz + 551831439U, // VPMOVSXBDZrr + 3230697359U, // VPMOVSXBDZrrk + 3229665167U, // VPMOVSXBDZrrkz + 551896975U, // VPMOVSXBDrm + 551831439U, // VPMOVSXBDrr + 551901623U, // VPMOVSXBQYrm + 551836087U, // VPMOVSXBQYrr + 432567U, // VPMOVSXBQZ128rm + 1644983U, // VPMOVSXBQZ128rmk + 3229686199U, // VPMOVSXBQZ128rmkz + 551836087U, // VPMOVSXBQZ128rr + 3230702007U, // VPMOVSXBQZ128rrk + 3229669815U, // VPMOVSXBQZ128rrkz + 551901623U, // VPMOVSXBQZ256rm + 553015735U, // VPMOVSXBQZ256rmk + 551639479U, // VPMOVSXBQZ256rmkz + 551836087U, // VPMOVSXBQZ256rr + 3230702007U, // VPMOVSXBQZ256rrk + 3229669815U, // VPMOVSXBQZ256rrkz + 551918007U, // VPMOVSXBQZrm + 552917431U, // VPMOVSXBQZrmk + 551655863U, // VPMOVSXBQZrmkz + 551836087U, // VPMOVSXBQZrr + 3230702007U, // VPMOVSXBQZrrk + 3229669815U, // VPMOVSXBQZrrkz + 432567U, // VPMOVSXBQrm + 551836087U, // VPMOVSXBQrr + 273115U, // VPMOVSXBWYrm + 551840475U, // VPMOVSXBWYrr + 551922395U, // VPMOVSXBWZ128rm + 552921819U, // VPMOVSXBWZ128rmk + 551660251U, // VPMOVSXBWZ128rmkz + 551840475U, // VPMOVSXBWZ128rr + 3230706395U, // VPMOVSXBWZ128rrk + 3229674203U, // VPMOVSXBWZ128rrkz + 273115U, // VPMOVSXBWZ256rm + 3231001307U, // VPMOVSXBWZ256rmk + 3229870811U, // VPMOVSXBWZ256rmkz + 551840475U, // VPMOVSXBWZ256rr + 3230706395U, // VPMOVSXBWZ256rrk + 3229674203U, // VPMOVSXBWZ256rrkz + 552954587U, // VPMOVSXBWZrm + 3231034075U, // VPMOVSXBWZrmk + 3230886619U, // VPMOVSXBWZrmkz + 551840475U, // VPMOVSXBWZrr + 3230706395U, // VPMOVSXBWZrrk + 3229674203U, // VPMOVSXBWZrrkz + 551922395U, // VPMOVSXBWrm + 551840475U, // VPMOVSXBWrr + 269217U, // VPMOVSXDQYrm + 551836577U, // VPMOVSXDQYrr + 551918497U, // VPMOVSXDQZ128rm + 552917921U, // VPMOVSXDQZ128rmk + 551656353U, // VPMOVSXDQZ128rmkz + 551836577U, // VPMOVSXDQZ128rr + 3230702497U, // VPMOVSXDQZ128rrk + 3229670305U, // VPMOVSXDQZ128rrkz + 269217U, // VPMOVSXDQZ256rm + 3230997409U, // VPMOVSXDQZ256rmk + 3229866913U, // VPMOVSXDQZ256rmkz + 551836577U, // VPMOVSXDQZ256rr + 3230702497U, // VPMOVSXDQZ256rrk + 3229670305U, // VPMOVSXDQZ256rrkz + 552950689U, // VPMOVSXDQZrm + 3231030177U, // VPMOVSXDQZrmk + 3230882721U, // VPMOVSXDQZrmkz + 551836577U, // VPMOVSXDQZrr + 3230702497U, // VPMOVSXDQZrrk + 3229670305U, // VPMOVSXDQZrrkz + 551918497U, // VPMOVSXDQrm + 551836577U, // VPMOVSXDQrr + 266608U, // VPMOVSXWDYrm + 551833968U, // VPMOVSXWDYrr + 551915888U, // VPMOVSXWDZ128rm + 552915312U, // VPMOVSXWDZ128rmk + 551653744U, // VPMOVSXWDZ128rmkz + 551833968U, // VPMOVSXWDZ128rr + 3230699888U, // VPMOVSXWDZ128rrk + 3229667696U, // VPMOVSXWDZ128rrkz + 266608U, // VPMOVSXWDZ256rm + 3230994800U, // VPMOVSXWDZ256rmk + 3229864304U, // VPMOVSXWDZ256rmkz + 551833968U, // VPMOVSXWDZ256rr + 3230699888U, // VPMOVSXWDZ256rrk + 3229667696U, // VPMOVSXWDZ256rrkz + 552948080U, // VPMOVSXWDZrm + 3231027568U, // VPMOVSXWDZrmk + 3230880112U, // VPMOVSXWDZrmkz + 551833968U, // VPMOVSXWDZrr + 3230699888U, // VPMOVSXWDZrrk + 3229667696U, // VPMOVSXWDZrrkz + 551915888U, // VPMOVSXWDrm + 551833968U, // VPMOVSXWDrr + 551919798U, // VPMOVSXWQYrm + 551837878U, // VPMOVSXWQYrr + 551903414U, // VPMOVSXWQZ128rm + 553017526U, // VPMOVSXWQZ128rmk + 551641270U, // VPMOVSXWQZ128rmkz + 551837878U, // VPMOVSXWQZ128rr + 3230703798U, // VPMOVSXWQZ128rrk + 3229671606U, // VPMOVSXWQZ128rrkz + 551919798U, // VPMOVSXWQZ256rm + 552919222U, // VPMOVSXWQZ256rmk + 551657654U, // VPMOVSXWQZ256rmkz + 551837878U, // VPMOVSXWQZ256rr + 3230703798U, // VPMOVSXWQZ256rrk + 3229671606U, // VPMOVSXWQZ256rrkz + 270518U, // VPMOVSXWQZrm + 3230998710U, // VPMOVSXWQZrmk + 3229868214U, // VPMOVSXWQZrmkz + 551837878U, // VPMOVSXWQZrr + 3230703798U, // VPMOVSXWQZrrk + 3229671606U, // VPMOVSXWQZrrkz + 551903414U, // VPMOVSXWQrm + 551837878U, // VPMOVSXWQrr + 12616715U, // VPMOVUSDBZ128mr + 3234137099U, // VPMOVUSDBZ128mrk + 551830539U, // VPMOVUSDBZ128rr + 3230696459U, // VPMOVUSDBZ128rrk + 3229664267U, // VPMOVUSDBZ128rrkz + 18908171U, // VPMOVUSDBZ256mr + 3240428555U, // VPMOVUSDBZ256mrk + 551830539U, // VPMOVUSDBZ256rr + 3230696459U, // VPMOVUSDBZ256rrk + 3229664267U, // VPMOVUSDBZ256rrkz + 33588235U, // VPMOVUSDBZmr + 3255108619U, // VPMOVUSDBZmrk + 551830539U, // VPMOVUSDBZrr + 3230696459U, // VPMOVUSDBZrrk + 3229664267U, // VPMOVUSDBZrrkz + 18918293U, // VPMOVUSDWZ128mr + 3240438677U, // VPMOVUSDWZ128mrk + 551840661U, // VPMOVUSDWZ128rr + 3230706581U, // VPMOVUSDWZ128rrk + 3229674389U, // VPMOVUSDWZ128rrkz + 33598357U, // VPMOVUSDWZ256mr + 3255118741U, // VPMOVUSDWZ256mrk + 551840661U, // VPMOVUSDWZ256rr + 3230706581U, // VPMOVUSDWZ256rrk + 3229674389U, // VPMOVUSDWZ256rrkz + 180398997U, // VPMOVUSDWZmr + 3401919381U, // VPMOVUSDWZmrk + 551840661U, // VPMOVUSDWZrr + 3230706581U, // VPMOVUSDWZrrk + 3229674389U, // VPMOVUSDWZrrkz + 4228367U, // VPMOVUSQBZ128mr + 3225748751U, // VPMOVUSQBZ128mrk + 551830799U, // VPMOVUSQBZ128rr + 3230696719U, // VPMOVUSQBZ128rrk + 3229664527U, // VPMOVUSQBZ128rrkz + 12616975U, // VPMOVUSQBZ256mr + 3234137359U, // VPMOVUSQBZ256mrk + 551830799U, // VPMOVUSQBZ256rr + 3230696719U, // VPMOVUSQBZ256rrk + 3229664527U, // VPMOVUSQBZ256rrkz + 18908431U, // VPMOVUSQBZmr + 3240428815U, // VPMOVUSQBZmrk + 551830799U, // VPMOVUSQBZrr + 3230696719U, // VPMOVUSQBZrrk + 3229664527U, // VPMOVUSQBZrrkz + 18910598U, // VPMOVUSQDZ128mr + 3240430982U, // VPMOVUSQDZ128mrk + 551832966U, // VPMOVUSQDZ128rr + 3230698886U, // VPMOVUSQDZ128rrk + 3229666694U, // VPMOVUSQDZ128rrkz + 33590662U, // VPMOVUSQDZ256mr + 3255111046U, // VPMOVUSQDZ256mrk + 551832966U, // VPMOVUSQDZ256rr + 3230698886U, // VPMOVUSQDZ256rrk + 3229666694U, // VPMOVUSQDZ256rrkz + 180391302U, // VPMOVUSQDZmr + 3401911686U, // VPMOVUSQDZmrk + 551832966U, // VPMOVUSQDZrr + 3230698886U, // VPMOVUSQDZrrk + 3229666694U, // VPMOVUSQDZrrkz + 12627266U, // VPMOVUSQWZ128mr + 3234147650U, // VPMOVUSQWZ128mrk + 551841090U, // VPMOVUSQWZ128rr + 3230707010U, // VPMOVUSQWZ128rrk + 3229674818U, // VPMOVUSQWZ128rrkz + 18918722U, // VPMOVUSQWZ256mr + 3240439106U, // VPMOVUSQWZ256mrk + 551841090U, // VPMOVUSQWZ256rr + 3230707010U, // VPMOVUSQWZ256rrk + 3229674818U, // VPMOVUSQWZ256rrkz + 33598786U, // VPMOVUSQWZmr + 3255119170U, // VPMOVUSQWZmrk + 551841090U, // VPMOVUSQWZrr + 3230707010U, // VPMOVUSQWZrrk + 3229674818U, // VPMOVUSQWZrrkz + 18908876U, // VPMOVUSWBZ128mr + 3240429260U, // VPMOVUSWBZ128mrk + 551831244U, // VPMOVUSWBZ128rr + 3230697164U, // VPMOVUSWBZ128rrk + 3229664972U, // VPMOVUSWBZ128rrkz + 33588940U, // VPMOVUSWBZ256mr + 3255109324U, // VPMOVUSWBZ256mrk + 551831244U, // VPMOVUSWBZ256rr + 3230697164U, // VPMOVUSWBZ256rrk + 3229664972U, // VPMOVUSWBZ256rrkz + 180389580U, // VPMOVUSWBZmr + 3401909964U, // VPMOVUSWBZmrk + 551831244U, // VPMOVUSWBZrr + 3230697164U, // VPMOVUSWBZrrk + 3229664972U, // VPMOVUSWBZrrkz + 551835663U, // VPMOVW2MZ128rr + 551835663U, // VPMOVW2MZ256rr + 551835663U, // VPMOVW2MZrr + 18908897U, // VPMOVWBZ128mr + 3240429281U, // VPMOVWBZ128mrk + 551831265U, // VPMOVWBZ128rr + 3230697185U, // VPMOVWBZ128rrk + 3229664993U, // VPMOVWBZ128rrkz + 33588961U, // VPMOVWBZ256mr + 3255109345U, // VPMOVWBZ256mrk + 551831265U, // VPMOVWBZ256rr + 3230697185U, // VPMOVWBZ256rrk + 3229664993U, // VPMOVWBZ256rrkz + 180389601U, // VPMOVWBZmr + 3401909985U, // VPMOVWBZmrk + 551831265U, // VPMOVWBZrr + 3230697185U, // VPMOVWBZrrk + 3229664993U, // VPMOVWBZrrkz + 551913370U, // VPMOVZXBDYrm + 551831450U, // VPMOVZXBDYrr + 551896986U, // VPMOVZXBDZ128rm + 553011098U, // VPMOVZXBDZ128rmk + 551634842U, // VPMOVZXBDZ128rmkz + 551831450U, // VPMOVZXBDZ128rr + 3230697370U, // VPMOVZXBDZ128rrk + 3229665178U, // VPMOVZXBDZ128rrkz + 551913370U, // VPMOVZXBDZ256rm + 552912794U, // VPMOVZXBDZ256rmk + 551651226U, // VPMOVZXBDZ256rmkz + 551831450U, // VPMOVZXBDZ256rr + 3230697370U, // VPMOVZXBDZ256rrk + 3229665178U, // VPMOVZXBDZ256rrkz + 264090U, // VPMOVZXBDZrm + 3230992282U, // VPMOVZXBDZrmk + 3229861786U, // VPMOVZXBDZrmkz + 551831450U, // VPMOVZXBDZrr + 3230697370U, // VPMOVZXBDZrrk + 3229665178U, // VPMOVZXBDZrrkz + 551896986U, // VPMOVZXBDrm + 551831450U, // VPMOVZXBDrr + 551901634U, // VPMOVZXBQYrm + 551836098U, // VPMOVZXBQYrr + 432578U, // VPMOVZXBQZ128rm + 1644994U, // VPMOVZXBQZ128rmk + 3229686210U, // VPMOVZXBQZ128rmkz + 551836098U, // VPMOVZXBQZ128rr + 3230702018U, // VPMOVZXBQZ128rrk + 3229669826U, // VPMOVZXBQZ128rrkz + 551901634U, // VPMOVZXBQZ256rm + 553015746U, // VPMOVZXBQZ256rmk + 551639490U, // VPMOVZXBQZ256rmkz + 551836098U, // VPMOVZXBQZ256rr + 3230702018U, // VPMOVZXBQZ256rrk + 3229669826U, // VPMOVZXBQZ256rrkz + 551918018U, // VPMOVZXBQZrm + 552917442U, // VPMOVZXBQZrmk + 551655874U, // VPMOVZXBQZrmkz + 551836098U, // VPMOVZXBQZrr + 3230702018U, // VPMOVZXBQZrrk + 3229669826U, // VPMOVZXBQZrrkz + 432578U, // VPMOVZXBQrm + 551836098U, // VPMOVZXBQrr + 273126U, // VPMOVZXBWYrm + 551840486U, // VPMOVZXBWYrr + 551922406U, // VPMOVZXBWZ128rm + 552921830U, // VPMOVZXBWZ128rmk + 551660262U, // VPMOVZXBWZ128rmkz + 551840486U, // VPMOVZXBWZ128rr + 3230706406U, // VPMOVZXBWZ128rrk + 3229674214U, // VPMOVZXBWZ128rrkz + 273126U, // VPMOVZXBWZ256rm + 3231001318U, // VPMOVZXBWZ256rmk + 3229870822U, // VPMOVZXBWZ256rmkz + 551840486U, // VPMOVZXBWZ256rr + 3230706406U, // VPMOVZXBWZ256rrk + 3229674214U, // VPMOVZXBWZ256rrkz + 552954598U, // VPMOVZXBWZrm + 3231034086U, // VPMOVZXBWZrmk + 3230886630U, // VPMOVZXBWZrmkz + 551840486U, // VPMOVZXBWZrr + 3230706406U, // VPMOVZXBWZrrk + 3229674214U, // VPMOVZXBWZrrkz + 551922406U, // VPMOVZXBWrm + 551840486U, // VPMOVZXBWrr + 269228U, // VPMOVZXDQYrm + 551836588U, // VPMOVZXDQYrr + 551918508U, // VPMOVZXDQZ128rm + 552917932U, // VPMOVZXDQZ128rmk + 551656364U, // VPMOVZXDQZ128rmkz + 551836588U, // VPMOVZXDQZ128rr + 3230702508U, // VPMOVZXDQZ128rrk + 3229670316U, // VPMOVZXDQZ128rrkz + 269228U, // VPMOVZXDQZ256rm + 3230997420U, // VPMOVZXDQZ256rmk + 3229866924U, // VPMOVZXDQZ256rmkz + 551836588U, // VPMOVZXDQZ256rr + 3230702508U, // VPMOVZXDQZ256rrk + 3229670316U, // VPMOVZXDQZ256rrkz + 552950700U, // VPMOVZXDQZrm + 3231030188U, // VPMOVZXDQZrmk + 3230882732U, // VPMOVZXDQZrmkz + 551836588U, // VPMOVZXDQZrr + 3230702508U, // VPMOVZXDQZrrk + 3229670316U, // VPMOVZXDQZrrkz + 551918508U, // VPMOVZXDQrm + 551836588U, // VPMOVZXDQrr + 266619U, // VPMOVZXWDYrm + 551833979U, // VPMOVZXWDYrr + 551915899U, // VPMOVZXWDZ128rm + 552915323U, // VPMOVZXWDZ128rmk + 551653755U, // VPMOVZXWDZ128rmkz + 551833979U, // VPMOVZXWDZ128rr + 3230699899U, // VPMOVZXWDZ128rrk + 3229667707U, // VPMOVZXWDZ128rrkz + 266619U, // VPMOVZXWDZ256rm + 3230994811U, // VPMOVZXWDZ256rmk + 3229864315U, // VPMOVZXWDZ256rmkz + 551833979U, // VPMOVZXWDZ256rr + 3230699899U, // VPMOVZXWDZ256rrk + 3229667707U, // VPMOVZXWDZ256rrkz + 552948091U, // VPMOVZXWDZrm + 3231027579U, // VPMOVZXWDZrmk + 3230880123U, // VPMOVZXWDZrmkz + 551833979U, // VPMOVZXWDZrr + 3230699899U, // VPMOVZXWDZrrk + 3229667707U, // VPMOVZXWDZrrkz + 551915899U, // VPMOVZXWDrm + 551833979U, // VPMOVZXWDrr + 551919809U, // VPMOVZXWQYrm + 551837889U, // VPMOVZXWQYrr + 551903425U, // VPMOVZXWQZ128rm + 553017537U, // VPMOVZXWQZ128rmk + 551641281U, // VPMOVZXWQZ128rmkz + 551837889U, // VPMOVZXWQZ128rr + 3230703809U, // VPMOVZXWQZ128rrk + 3229671617U, // VPMOVZXWQZ128rrkz + 551919809U, // VPMOVZXWQZ256rm + 552919233U, // VPMOVZXWQZ256rmk + 551657665U, // VPMOVZXWQZ256rmkz + 551837889U, // VPMOVZXWQZ256rr + 3230703809U, // VPMOVZXWQZ256rrk + 3229671617U, // VPMOVZXWQZ256rrkz + 270529U, // VPMOVZXWQZrm + 3230998721U, // VPMOVZXWQZrmk + 3229868225U, // VPMOVZXWQZrmkz + 551837889U, // VPMOVZXWQZrr + 3230703809U, // VPMOVZXWQZrrk + 3229671617U, // VPMOVZXWQZrrkz + 551903425U, // VPMOVZXWQrm + 551837889U, // VPMOVZXWQrr + 812866230U, // VPMULDQYrm + 811653814U, // VPMULDQYrr + 811850422U, // VPMULDQZ128rm + 358718134U, // VPMULDQZ128rmb + 1433950902U, // VPMULDQZ128rmbk + 1165286070U, // VPMULDQZ128rmbkz + 985111222U, // VPMULDQZ128rmk + 890575542U, // VPMULDQZ128rmkz + 811653814U, // VPMULDQZ128rr + 87055030U, // VPMULDQZ128rrk + 890280630U, // VPMULDQZ128rrkz + 812866230U, // VPMULDQZ256rm + 360815286U, // VPMULDQZ256rmb + 1436048054U, // VPMULDQZ256rmbk + 1167383222U, // VPMULDQZ256rmbkz + 985127606U, // VPMULDQZ256rmk + 890608310U, // VPMULDQZ256rmkz + 811653814U, // VPMULDQZ256rr + 87055030U, // VPMULDQZ256rrk + 890280630U, // VPMULDQZ256rrkz + 812882614U, // VPMULDQZrm + 362912438U, // VPMULDQZrmb + 1438145206U, // VPMULDQZrmbk + 1169480374U, // VPMULDQZrmbkz + 985143990U, // VPMULDQZrmk + 890673846U, // VPMULDQZrmkz + 811653814U, // VPMULDQZrr + 87055030U, // VPMULDQZrrk + 890280630U, // VPMULDQZrrkz + 811850422U, // VPMULDQrm + 811653814U, // VPMULDQrr + 812871256U, // VPMULHRSWYrm + 811658840U, // VPMULHRSWYrr + 811855448U, // VPMULHRSWZ128rm + 985116248U, // VPMULHRSWZ128rmk + 890580568U, // VPMULHRSWZ128rmkz + 811658840U, // VPMULHRSWZ128rr + 87060056U, // VPMULHRSWZ128rrk + 890285656U, // VPMULHRSWZ128rrkz + 812871256U, // VPMULHRSWZ256rm + 985132632U, // VPMULHRSWZ256rmk + 890613336U, // VPMULHRSWZ256rmkz + 811658840U, // VPMULHRSWZ256rr + 87060056U, // VPMULHRSWZ256rrk + 890285656U, // VPMULHRSWZ256rrkz + 812887640U, // VPMULHRSWZrm + 985149016U, // VPMULHRSWZrmk + 890678872U, // VPMULHRSWZrmkz + 811658840U, // VPMULHRSWZrr + 87060056U, // VPMULHRSWZrrk + 890285656U, // VPMULHRSWZrrkz + 811855448U, // VPMULHRSWrm + 811658840U, // VPMULHRSWrr + 812871481U, // VPMULHUWYrm + 811659065U, // VPMULHUWYrr + 811855673U, // VPMULHUWZ128rm + 985116473U, // VPMULHUWZ128rmk + 890580793U, // VPMULHUWZ128rmkz + 811659065U, // VPMULHUWZ128rr + 87060281U, // VPMULHUWZ128rrk + 890285881U, // VPMULHUWZ128rrkz + 812871481U, // VPMULHUWZ256rm + 985132857U, // VPMULHUWZ256rmk + 890613561U, // VPMULHUWZ256rmkz + 811659065U, // VPMULHUWZ256rr + 87060281U, // VPMULHUWZ256rrk + 890285881U, // VPMULHUWZ256rrkz + 812887865U, // VPMULHUWZrm + 985149241U, // VPMULHUWZrmk + 890679097U, // VPMULHUWZrmkz + 811659065U, // VPMULHUWZrr + 87060281U, // VPMULHUWZrrk + 890285881U, // VPMULHUWZrrkz + 811855673U, // VPMULHUWrm + 811659065U, // VPMULHUWrr + 812870706U, // VPMULHWYrm + 811658290U, // VPMULHWYrr + 811854898U, // VPMULHWZ128rm + 985115698U, // VPMULHWZ128rmk + 890580018U, // VPMULHWZ128rmkz + 811658290U, // VPMULHWZ128rr + 87059506U, // VPMULHWZ128rrk + 890285106U, // VPMULHWZ128rrkz + 812870706U, // VPMULHWZ256rm + 985132082U, // VPMULHWZ256rmk + 890612786U, // VPMULHWZ256rmkz + 811658290U, // VPMULHWZ256rr + 87059506U, // VPMULHWZ256rrk + 890285106U, // VPMULHWZ256rrkz + 812887090U, // VPMULHWZrm + 985148466U, // VPMULHWZrmk + 890678322U, // VPMULHWZrmkz + 811658290U, // VPMULHWZrr + 87059506U, // VPMULHWZrrk + 890285106U, // VPMULHWZrrkz + 811854898U, // VPMULHWrm + 811658290U, // VPMULHWrr + 812861561U, // VPMULLDYrm + 811649145U, // VPMULLDYrr + 811845753U, // VPMULLDZ128rm + 360794233U, // VPMULLDZ128rmb + 1436059769U, // VPMULLDZ128rmbk + 1167476857U, // VPMULLDZ128rmbkz + 985106553U, // VPMULLDZ128rmk + 890570873U, // VPMULLDZ128rmkz + 811649145U, // VPMULLDZ128rr + 87050361U, // VPMULLDZ128rrk + 890275961U, // VPMULLDZ128rrkz + 812861561U, // VPMULLDZ256rm + 362891385U, // VPMULLDZ256rmb + 1438156921U, // VPMULLDZ256rmbk + 1169574009U, // VPMULLDZ256rmbkz + 985122937U, // VPMULLDZ256rmk + 890603641U, // VPMULLDZ256rmkz + 811649145U, // VPMULLDZ256rr + 87050361U, // VPMULLDZ256rrk + 890275961U, // VPMULLDZ256rrkz + 812877945U, // VPMULLDZrm + 364988537U, // VPMULLDZrmb + 1440254073U, // VPMULLDZrmbk + 1171671161U, // VPMULLDZrmbkz + 985139321U, // VPMULLDZrmk + 890669177U, // VPMULLDZrmkz + 811649145U, // VPMULLDZrr + 87050361U, // VPMULLDZrrk + 890275961U, // VPMULLDZrrkz + 811845753U, // VPMULLDrm + 811649145U, // VPMULLDrr + 811850965U, // VPMULLQZ128rm + 358718677U, // VPMULLQZ128rmb + 1433951445U, // VPMULLQZ128rmbk + 1165286613U, // VPMULLQZ128rmbkz + 985111765U, // VPMULLQZ128rmk + 890576085U, // VPMULLQZ128rmkz + 811654357U, // VPMULLQZ128rr + 87055573U, // VPMULLQZ128rrk + 890281173U, // VPMULLQZ128rrkz + 812866773U, // VPMULLQZ256rm + 360815829U, // VPMULLQZ256rmb + 1436048597U, // VPMULLQZ256rmbk + 1167383765U, // VPMULLQZ256rmbkz + 985128149U, // VPMULLQZ256rmk + 890608853U, // VPMULLQZ256rmkz + 811654357U, // VPMULLQZ256rr + 87055573U, // VPMULLQZ256rrk + 890281173U, // VPMULLQZ256rrkz + 812883157U, // VPMULLQZrm + 362912981U, // VPMULLQZrmb + 1438145749U, // VPMULLQZrmbk + 1169480917U, // VPMULLQZrmbkz + 985144533U, // VPMULLQZrmk + 890674389U, // VPMULLQZrmkz + 811654357U, // VPMULLQZrr + 87055573U, // VPMULLQZrrk + 890281173U, // VPMULLQZrrkz + 812870775U, // VPMULLWYrm + 811658359U, // VPMULLWYrr + 811854967U, // VPMULLWZ128rm + 985115767U, // VPMULLWZ128rmk + 890580087U, // VPMULLWZ128rmkz + 811658359U, // VPMULLWZ128rr + 87059575U, // VPMULLWZ128rrk + 890285175U, // VPMULLWZ128rrkz + 812870775U, // VPMULLWZ256rm + 985132151U, // VPMULLWZ256rmk + 890612855U, // VPMULLWZ256rmkz + 811658359U, // VPMULLWZ256rr + 87059575U, // VPMULLWZ256rrk + 890285175U, // VPMULLWZ256rrkz + 812887159U, // VPMULLWZrm + 985148535U, // VPMULLWZrmk + 890678391U, // VPMULLWZrmkz + 811658359U, // VPMULLWZrr + 87059575U, // VPMULLWZrrk + 890285175U, // VPMULLWZrrkz + 811854967U, // VPMULLWrm + 811658359U, // VPMULLWrr + 811844900U, // VPMULTISHIFTQBZ128rm + 358712612U, // VPMULTISHIFTQBZ128rmb + 1433945380U, // VPMULTISHIFTQBZ128rmbk + 1165280548U, // VPMULTISHIFTQBZ128rmbkz + 985105700U, // VPMULTISHIFTQBZ128rmk + 890570020U, // VPMULTISHIFTQBZ128rmkz + 811648292U, // VPMULTISHIFTQBZ128rr + 87049508U, // VPMULTISHIFTQBZ128rrk + 890275108U, // VPMULTISHIFTQBZ128rrkz + 812860708U, // VPMULTISHIFTQBZ256rm + 360809764U, // VPMULTISHIFTQBZ256rmb + 1436042532U, // VPMULTISHIFTQBZ256rmbk + 1167377700U, // VPMULTISHIFTQBZ256rmbkz + 985122084U, // VPMULTISHIFTQBZ256rmk + 890602788U, // VPMULTISHIFTQBZ256rmkz + 811648292U, // VPMULTISHIFTQBZ256rr + 87049508U, // VPMULTISHIFTQBZ256rrk + 890275108U, // VPMULTISHIFTQBZ256rrkz + 812877092U, // VPMULTISHIFTQBZrm + 362906916U, // VPMULTISHIFTQBZrmb + 1438139684U, // VPMULTISHIFTQBZrmbk + 1169474852U, // VPMULTISHIFTQBZrmbkz + 985138468U, // VPMULTISHIFTQBZrmk + 890668324U, // VPMULTISHIFTQBZrmkz + 811648292U, // VPMULTISHIFTQBZrr + 87049508U, // VPMULTISHIFTQBZrrk + 890275108U, // VPMULTISHIFTQBZrrkz + 812866455U, // VPMULUDQYrm + 811654039U, // VPMULUDQYrr + 811850647U, // VPMULUDQZ128rm + 358718359U, // VPMULUDQZ128rmb + 1433951127U, // VPMULUDQZ128rmbk + 1165286295U, // VPMULUDQZ128rmbkz + 985111447U, // VPMULUDQZ128rmk + 890575767U, // VPMULUDQZ128rmkz + 811654039U, // VPMULUDQZ128rr + 87055255U, // VPMULUDQZ128rrk + 890280855U, // VPMULUDQZ128rrkz + 812866455U, // VPMULUDQZ256rm + 360815511U, // VPMULUDQZ256rmb + 1436048279U, // VPMULUDQZ256rmbk + 1167383447U, // VPMULUDQZ256rmbkz + 985127831U, // VPMULUDQZ256rmk + 890608535U, // VPMULUDQZ256rmkz + 811654039U, // VPMULUDQZ256rr + 87055255U, // VPMULUDQZ256rrk + 890280855U, // VPMULUDQZ256rrkz + 812882839U, // VPMULUDQZrm + 362912663U, // VPMULUDQZrmb + 1438145431U, // VPMULUDQZrmbk + 1169480599U, // VPMULUDQZrmbkz + 985144215U, // VPMULUDQZrmk + 890674071U, // VPMULUDQZrmkz + 811654039U, // VPMULUDQZrr + 87055255U, // VPMULUDQZrrk + 890280855U, // VPMULUDQZrrkz + 811850647U, // VPMULUDQrm + 811654039U, // VPMULUDQrr + 263723U, // VPOPCNTBZ128rm + 3230991915U, // VPOPCNTBZ128rmk + 3229861419U, // VPOPCNTBZ128rmkz + 551831083U, // VPOPCNTBZ128rr + 3230697003U, // VPOPCNTBZ128rrk + 3229664811U, // VPOPCNTBZ128rrkz + 552945195U, // VPOPCNTBZ256rm + 3231024683U, // VPOPCNTBZ256rmk + 3230877227U, // VPOPCNTBZ256rmkz + 551831083U, // VPOPCNTBZ256rr + 3230697003U, // VPOPCNTBZ256rrk + 3229664811U, // VPOPCNTBZ256rrkz + 552437291U, // VPOPCNTBZrm + 3231090219U, // VPOPCNTBZrmk + 3230893611U, // VPOPCNTBZrmkz + 551831083U, // VPOPCNTBZrr + 3230697003U, // VPOPCNTBZrrk + 3229664811U, // VPOPCNTBZrrkz + 266302U, // VPOPCNTDZ128rm + 629493822U, // VPOPCNTDZ128rmb + 630607934U, // VPOPCNTDZ128rmbk + 629231678U, // VPOPCNTDZ128rmbkz + 3230994494U, // VPOPCNTDZ128rmk + 3229863998U, // VPOPCNTDZ128rmkz + 551833662U, // VPOPCNTDZ128rr + 3230699582U, // VPOPCNTDZ128rrk + 3229667390U, // VPOPCNTDZ128rrkz + 552947774U, // VPOPCNTDZ256rm + 631590974U, // VPOPCNTDZ256rmb + 632705086U, // VPOPCNTDZ256rmbk + 631328830U, // VPOPCNTDZ256rmbkz + 3231027262U, // VPOPCNTDZ256rmk + 3230879806U, // VPOPCNTDZ256rmkz + 551833662U, // VPOPCNTDZ256rr + 3230699582U, // VPOPCNTDZ256rrk + 3229667390U, // VPOPCNTDZ256rrkz + 552439870U, // VPOPCNTDZrm + 633688126U, // VPOPCNTDZrmb + 634802238U, // VPOPCNTDZrmbk + 633425982U, // VPOPCNTDZrmbkz + 3231092798U, // VPOPCNTDZrmk + 3230896190U, // VPOPCNTDZrmkz + 551833662U, // VPOPCNTDZrr + 3230699582U, // VPOPCNTDZrrk + 3229667390U, // VPOPCNTDZrrkz + 270230U, // VPOPCNTQZ128rm + 627416982U, // VPOPCNTQZ128rmb + 628416406U, // VPOPCNTQZ128rmbk + 627154838U, // VPOPCNTQZ128rmbkz + 3230998422U, // VPOPCNTQZ128rmk + 3229867926U, // VPOPCNTQZ128rmkz + 551837590U, // VPOPCNTQZ128rr + 3230703510U, // VPOPCNTQZ128rrk + 3229671318U, // VPOPCNTQZ128rrkz + 552951702U, // VPOPCNTQZ256rm + 629514134U, // VPOPCNTQZ256rmb + 630513558U, // VPOPCNTQZ256rmbk + 629251990U, // VPOPCNTQZ256rmbkz + 3231031190U, // VPOPCNTQZ256rmk + 3230883734U, // VPOPCNTQZ256rmkz + 551837590U, // VPOPCNTQZ256rr + 3230703510U, // VPOPCNTQZ256rrk + 3229671318U, // VPOPCNTQZ256rrkz + 552443798U, // VPOPCNTQZrm + 631611286U, // VPOPCNTQZrmb + 632610710U, // VPOPCNTQZrmbk + 631349142U, // VPOPCNTQZrmbkz + 3231096726U, // VPOPCNTQZrmk + 3230900118U, // VPOPCNTQZrmkz + 551837590U, // VPOPCNTQZrr + 3230703510U, // VPOPCNTQZrrk + 3229671318U, // VPOPCNTQZrrkz + 274160U, // VPOPCNTWZ128rm + 3231002352U, // VPOPCNTWZ128rmk + 3229871856U, // VPOPCNTWZ128rmkz + 551841520U, // VPOPCNTWZ128rr + 3230707440U, // VPOPCNTWZ128rrk + 3229675248U, // VPOPCNTWZ128rrkz + 552955632U, // VPOPCNTWZ256rm + 3231035120U, // VPOPCNTWZ256rmk + 3230887664U, // VPOPCNTWZ256rmkz + 551841520U, // VPOPCNTWZ256rr + 3230707440U, // VPOPCNTWZ256rrk + 3229675248U, // VPOPCNTWZ256rrkz + 552447728U, // VPOPCNTWZrm + 3231100656U, // VPOPCNTWZrmk + 3230904048U, // VPOPCNTWZrmkz + 551841520U, // VPOPCNTWZrr + 3230707440U, // VPOPCNTWZrrk + 3229675248U, // VPOPCNTWZrrkz + 811847090U, // VPORDZ128rm + 360795570U, // VPORDZ128rmb + 1436061106U, // VPORDZ128rmbk + 1167478194U, // VPORDZ128rmbkz + 985107890U, // VPORDZ128rmk + 890572210U, // VPORDZ128rmkz + 811650482U, // VPORDZ128rr + 87051698U, // VPORDZ128rrk + 890277298U, // VPORDZ128rrkz + 812862898U, // VPORDZ256rm + 362892722U, // VPORDZ256rmb + 1438158258U, // VPORDZ256rmbk + 1169575346U, // VPORDZ256rmbkz + 985124274U, // VPORDZ256rmk + 890604978U, // VPORDZ256rmkz + 811650482U, // VPORDZ256rr + 87051698U, // VPORDZ256rrk + 890277298U, // VPORDZ256rrkz + 812879282U, // VPORDZrm + 364989874U, // VPORDZrmb + 1440255410U, // VPORDZrmbk + 1171672498U, // VPORDZrmbkz + 985140658U, // VPORDZrmk + 890670514U, // VPORDZrmkz + 811650482U, // VPORDZrr + 87051698U, // VPORDZrrk + 890277298U, // VPORDZrrkz + 811851358U, // VPORQZ128rm + 358719070U, // VPORQZ128rmb + 1433951838U, // VPORQZ128rmbk + 1165287006U, // VPORQZ128rmbkz + 985112158U, // VPORQZ128rmk + 890576478U, // VPORQZ128rmkz + 811654750U, // VPORQZ128rr + 87055966U, // VPORQZ128rrk + 890281566U, // VPORQZ128rrkz + 812867166U, // VPORQZ256rm + 360816222U, // VPORQZ256rmb + 1436048990U, // VPORQZ256rmbk + 1167384158U, // VPORQZ256rmbkz + 985128542U, // VPORQZ256rmk + 890609246U, // VPORQZ256rmkz + 811654750U, // VPORQZ256rr + 87055966U, // VPORQZ256rrk + 890281566U, // VPORQZ256rrkz + 812883550U, // VPORQZrm + 362913374U, // VPORQZrmb + 1438146142U, // VPORQZrmbk + 1169481310U, // VPORQZrmbkz + 985144926U, // VPORQZrmk + 890674782U, // VPORQZrmkz + 811654750U, // VPORQZrr + 87055966U, // VPORQZrrk + 890281566U, // VPORQZrrkz + 812867879U, // VPORYrm + 811655463U, // VPORYrr + 811852071U, // VPORrm + 811655463U, // VPORrr + 326391851U, // VPPERMrmr + 890574891U, // VPPERMrrm + 890279979U, // VPPERMrrr + 890279979U, // VPPERMrrr_REV + 1638172802U, // VPROLDZ128mbi + 1712588930U, // VPROLDZ128mbik + 1686489218U, // VPROLDZ128mbikz + 830769282U, // VPROLDZ128mi + 643041410U, // VPROLDZ128mik + 593873026U, // VPROLDZ128mikz + 283428994U, // VPROLDZ128ri + 1357580418U, // VPROLDZ128rik + 1088817282U, // VPROLDZ128rikz + 2443479170U, // VPROLDZ256mbi + 2517895298U, // VPROLDZ256mbik + 2491795586U, // VPROLDZ256mbikz + 1009027202U, // VPROLDZ256mi + 649332866U, // VPROLDZ256mik + 644204674U, // VPROLDZ256mikz + 283428994U, // VPROLDZ256ri + 1357580418U, // VPROLDZ256rik + 1088817282U, // VPROLDZ256rikz + 2711914626U, // VPROLDZmbi + 2786330754U, // VPROLDZmbik + 2760231042U, // VPROLDZmbikz + 1011124354U, // VPROLDZmi + 655624322U, // VPROLDZmik + 650496130U, // VPROLDZmikz + 283428994U, // VPROLDZri + 1357580418U, // VPROLDZrik + 1088817282U, // VPROLDZrikz + 2982452446U, // VPROLQZ128mbi + 3075742942U, // VPROLQZ128mbik + 3013991646U, // VPROLQZ128mbikz + 830774494U, // VPROLQZ128mi + 643046622U, // VPROLQZ128mik + 593878238U, // VPROLQZ128mikz + 283434206U, // VPROLQZ128ri + 1357585630U, // VPROLQZ128rik + 1088822494U, // VPROLQZ128rikz + 1640275166U, // VPROLQZ256mbi + 1733565662U, // VPROLQZ256mbik + 1671814366U, // VPROLQZ256mbikz + 1009032414U, // VPROLQZ256mi + 649338078U, // VPROLQZ256mik + 644209886U, // VPROLQZ256mikz + 283434206U, // VPROLQZ256ri + 1357585630U, // VPROLQZ256rik + 1088822494U, // VPROLQZ256rikz + 2445581534U, // VPROLQZmbi + 2538872030U, // VPROLQZmbik + 2477120734U, // VPROLQZmbikz + 1011129566U, // VPROLQZmi + 655629534U, // VPROLQZmik + 650501342U, // VPROLQZmikz + 283434206U, // VPROLQZri + 1357585630U, // VPROLQZrik + 1088822494U, // VPROLQZrikz + 811847883U, // VPROLVDZ128rm + 360796363U, // VPROLVDZ128rmb + 1436061899U, // VPROLVDZ128rmbk + 1167478987U, // VPROLVDZ128rmbkz + 985108683U, // VPROLVDZ128rmk + 890573003U, // VPROLVDZ128rmkz + 811651275U, // VPROLVDZ128rr + 87052491U, // VPROLVDZ128rrk + 890278091U, // VPROLVDZ128rrkz + 812863691U, // VPROLVDZ256rm + 362893515U, // VPROLVDZ256rmb + 1438159051U, // VPROLVDZ256rmbk + 1169576139U, // VPROLVDZ256rmbkz + 985125067U, // VPROLVDZ256rmk + 890605771U, // VPROLVDZ256rmkz + 811651275U, // VPROLVDZ256rr + 87052491U, // VPROLVDZ256rrk + 890278091U, // VPROLVDZ256rrkz + 812880075U, // VPROLVDZrm + 364990667U, // VPROLVDZrmb + 1440256203U, // VPROLVDZrmbk + 1171673291U, // VPROLVDZrmbkz + 985141451U, // VPROLVDZrmk + 890671307U, // VPROLVDZrmkz + 811651275U, // VPROLVDZrr + 87052491U, // VPROLVDZrrk + 890278091U, // VPROLVDZrrkz + 811851876U, // VPROLVQZ128rm + 358719588U, // VPROLVQZ128rmb + 1433952356U, // VPROLVQZ128rmbk + 1165287524U, // VPROLVQZ128rmbkz + 985112676U, // VPROLVQZ128rmk + 890576996U, // VPROLVQZ128rmkz + 811655268U, // VPROLVQZ128rr + 87056484U, // VPROLVQZ128rrk + 890282084U, // VPROLVQZ128rrkz + 812867684U, // VPROLVQZ256rm + 360816740U, // VPROLVQZ256rmb + 1436049508U, // VPROLVQZ256rmbk + 1167384676U, // VPROLVQZ256rmbkz + 985129060U, // VPROLVQZ256rmk + 890609764U, // VPROLVQZ256rmkz + 811655268U, // VPROLVQZ256rr + 87056484U, // VPROLVQZ256rrk + 890282084U, // VPROLVQZ256rrkz + 812884068U, // VPROLVQZrm + 362913892U, // VPROLVQZrmb + 1438146660U, // VPROLVQZrmbk + 1169481828U, // VPROLVQZrmbkz + 985145444U, // VPROLVQZrmk + 890675300U, // VPROLVQZrmkz + 811655268U, // VPROLVQZrr + 87056484U, // VPROLVQZrrk + 890282084U, // VPROLVQZrrkz + 1638174137U, // VPRORDZ128mbi + 1712590265U, // VPRORDZ128mbik + 1686490553U, // VPRORDZ128mbikz + 830770617U, // VPRORDZ128mi + 643042745U, // VPRORDZ128mik + 593874361U, // VPRORDZ128mikz + 283430329U, // VPRORDZ128ri + 1357581753U, // VPRORDZ128rik + 1088818617U, // VPRORDZ128rikz + 2443480505U, // VPRORDZ256mbi + 2517896633U, // VPRORDZ256mbik + 2491796921U, // VPRORDZ256mbikz + 1009028537U, // VPRORDZ256mi + 649334201U, // VPRORDZ256mik + 644206009U, // VPRORDZ256mikz + 283430329U, // VPRORDZ256ri + 1357581753U, // VPRORDZ256rik + 1088818617U, // VPRORDZ256rikz + 2711915961U, // VPRORDZmbi + 2786332089U, // VPRORDZmbik + 2760232377U, // VPRORDZmbikz + 1011125689U, // VPRORDZmi + 655625657U, // VPRORDZmik + 650497465U, // VPRORDZmikz + 283430329U, // VPRORDZri + 1357581753U, // VPRORDZrik + 1088818617U, // VPRORDZrikz + 2982452837U, // VPRORQZ128mbi + 3075743333U, // VPRORQZ128mbik + 3013992037U, // VPRORQZ128mbikz + 830774885U, // VPRORQZ128mi + 643047013U, // VPRORQZ128mik + 593878629U, // VPRORQZ128mikz + 283434597U, // VPRORQZ128ri + 1357586021U, // VPRORQZ128rik + 1088822885U, // VPRORQZ128rikz + 1640275557U, // VPRORQZ256mbi + 1733566053U, // VPRORQZ256mbik + 1671814757U, // VPRORQZ256mbikz + 1009032805U, // VPRORQZ256mi + 649338469U, // VPRORQZ256mik + 644210277U, // VPRORQZ256mikz + 283434597U, // VPRORQZ256ri + 1357586021U, // VPRORQZ256rik + 1088822885U, // VPRORQZ256rikz + 2445581925U, // VPRORQZmbi + 2538872421U, // VPRORQZmbik + 2477121125U, // VPRORQZmbikz + 1011129957U, // VPRORQZmi + 655629925U, // VPRORQZmik + 650501733U, // VPRORQZmikz + 283434597U, // VPRORQZri + 1357586021U, // VPRORQZrik + 1088822885U, // VPRORQZrikz + 811847920U, // VPRORVDZ128rm + 360796400U, // VPRORVDZ128rmb + 1436061936U, // VPRORVDZ128rmbk + 1167479024U, // VPRORVDZ128rmbkz + 985108720U, // VPRORVDZ128rmk + 890573040U, // VPRORVDZ128rmkz + 811651312U, // VPRORVDZ128rr + 87052528U, // VPRORVDZ128rrk + 890278128U, // VPRORVDZ128rrkz + 812863728U, // VPRORVDZ256rm + 362893552U, // VPRORVDZ256rmb + 1438159088U, // VPRORVDZ256rmbk + 1169576176U, // VPRORVDZ256rmbkz + 985125104U, // VPRORVDZ256rmk + 890605808U, // VPRORVDZ256rmkz + 811651312U, // VPRORVDZ256rr + 87052528U, // VPRORVDZ256rrk + 890278128U, // VPRORVDZ256rrkz + 812880112U, // VPRORVDZrm + 364990704U, // VPRORVDZrmb + 1440256240U, // VPRORVDZrmbk + 1171673328U, // VPRORVDZrmbkz + 985141488U, // VPRORVDZrmk + 890671344U, // VPRORVDZrmkz + 811651312U, // VPRORVDZrr + 87052528U, // VPRORVDZrrk + 890278128U, // VPRORVDZrrkz + 811851913U, // VPRORVQZ128rm + 358719625U, // VPRORVQZ128rmb + 1433952393U, // VPRORVQZ128rmbk + 1165287561U, // VPRORVQZ128rmbkz + 985112713U, // VPRORVQZ128rmk + 890577033U, // VPRORVQZ128rmkz + 811655305U, // VPRORVQZ128rr + 87056521U, // VPRORVQZ128rrk + 890282121U, // VPRORVQZ128rrkz + 812867721U, // VPRORVQZ256rm + 360816777U, // VPRORVQZ256rmb + 1436049545U, // VPRORVQZ256rmbk + 1167384713U, // VPRORVQZ256rmbkz + 985129097U, // VPRORVQZ256rmk + 890609801U, // VPRORVQZ256rmkz + 811655305U, // VPRORVQZ256rr + 87056521U, // VPRORVQZ256rrk + 890282121U, // VPRORVQZ256rrkz + 812884105U, // VPRORVQZrm + 362913929U, // VPRORVQZrmb + 1438146697U, // VPRORVQZrmbk + 1169481865U, // VPRORVQZrmbkz + 985145481U, // VPRORVQZrmk + 890675337U, // VPRORVQZrmkz + 811655305U, // VPRORVQZrr + 87056521U, // VPRORVQZrrk + 890282121U, // VPRORVQZrrkz + 830768700U, // VPROTBmi + 830801468U, // VPROTBmr + 283428412U, // VPROTBri + 811845180U, // VPROTBrm + 811648572U, // VPROTBrr + 811648572U, // VPROTBrr_REV + 830771289U, // VPROTDmi + 830804057U, // VPROTDmr + 283431001U, // VPROTDri + 811847769U, // VPROTDrm + 811651161U, // VPROTDrr + 811651161U, // VPROTDrr_REV + 830775233U, // VPROTQmi + 830808001U, // VPROTQmr + 283434945U, // VPROTQri + 811851713U, // VPROTQrm + 811655105U, // VPROTQrr + 811655105U, // VPROTQrr_REV + 830779153U, // VPROTWmi + 830811921U, // VPROTWmr + 283438865U, // VPROTWri + 811855633U, // VPROTWrm + 811659025U, // VPROTWrr + 811659025U, // VPROTWrr_REV + 812870266U, // VPSADBWYrm + 811657850U, // VPSADBWYrr + 811854458U, // VPSADBWZ128rm + 811657850U, // VPSADBWZ128rr + 812870266U, // VPSADBWZ256rm + 811657850U, // VPSADBWZ256rr + 812886650U, // VPSADBWZrm + 811657850U, // VPSADBWZrr + 811854458U, // VPSADBWrm + 811657850U, // VPSADBWrr + 3247720445U, // VPSCATTERDDZ128mr + 3425978365U, // VPSCATTERDDZ256mr + 3428075517U, // VPSCATTERDDZmr + 3247725345U, // VPSCATTERDQZ128mr + 3425983265U, // VPSCATTERDQZ256mr + 3428080417U, // VPSCATTERDQZmr + 3251916153U, // VPSCATTERQDZ128mr + 3247721849U, // VPSCATTERQDZ256mr + 3425979769U, // VPSCATTERQDZmr + 3247726073U, // VPSCATTERQQZ128mr + 3425983993U, // VPSCATTERQQZ256mr + 3428081145U, // VPSCATTERQQZmr + 830800811U, // VPSHABmr + 811844523U, // VPSHABrm + 811647915U, // VPSHABrr + 811647915U, // VPSHABrr_REV + 830801753U, // VPSHADmr + 811845465U, // VPSHADrm + 811648857U, // VPSHADrr + 811648857U, // VPSHADrr_REV + 830806380U, // VPSHAQmr + 811850092U, // VPSHAQrm + 811653484U, // VPSHAQrr + 811653484U, // VPSHAQrr_REV + 830810685U, // VPSHAWmr + 811854397U, // VPSHAWrm + 811657789U, // VPSHAWrr + 811657789U, // VPSHAWrr_REV + 830800997U, // VPSHLBmr + 811844709U, // VPSHLBrm + 811648101U, // VPSHLBrr + 811648101U, // VPSHLBrr_REV + 1686489028U, // VPSHLDDZ128rmbi + 1710475204U, // VPSHLDDZ128rmbik + 1712588740U, // VPSHLDDZ128rmbikz + 325437380U, // VPSHLDDZ128rmi + 1983104964U, // VPSHLDDZ128rmik + 1179912132U, // VPSHLDDZ128rmikz + 1088817092U, // VPSHLDDZ128rri + 2163132356U, // VPSHLDDZ128rrik + 1357580228U, // VPSHLDDZ128rrikz + 2491795396U, // VPSHLDDZ256rmbi + 2515781572U, // VPSHLDDZ256rmbik + 2517895108U, // VPSHLDDZ256rmbikz + 375769028U, // VPSHLDDZ256rmi + 1989396420U, // VPSHLDDZ256rmik + 1186203588U, // VPSHLDDZ256rmikz + 1088817092U, // VPSHLDDZ256rri + 2163132356U, // VPSHLDDZ256rrik + 1357580228U, // VPSHLDDZ256rrikz + 2760230852U, // VPSHLDDZrmbi + 2784217028U, // VPSHLDDZrmbik + 2786330564U, // VPSHLDDZrmbikz + 382060484U, // VPSHLDDZrmi + 1995687876U, // VPSHLDDZrmik + 1192495044U, // VPSHLDDZrmikz + 1088817092U, // VPSHLDDZrri + 2163132356U, // VPSHLDDZrrik + 1357580228U, // VPSHLDDZrrikz + 3013991055U, // VPSHLDQZ128rmbi + 3073628815U, // VPSHLDQZ128rmbik + 3075742351U, // VPSHLDQZ128rmbikz + 325442191U, // VPSHLDQZ128rmi + 1983109775U, // VPSHLDQZ128rmik + 1179916943U, // VPSHLDQZ128rmikz + 1088821903U, // VPSHLDQZ128rri + 2163137167U, // VPSHLDQZ128rrik + 1357585039U, // VPSHLDQZ128rrikz + 1671813775U, // VPSHLDQZ256rmbi + 1731451535U, // VPSHLDQZ256rmbik + 1733565071U, // VPSHLDQZ256rmbikz + 375773839U, // VPSHLDQZ256rmi + 1989401231U, // VPSHLDQZ256rmik + 1186208399U, // VPSHLDQZ256rmikz + 1088821903U, // VPSHLDQZ256rri + 2163137167U, // VPSHLDQZ256rrik + 1357585039U, // VPSHLDQZ256rrikz + 2477120143U, // VPSHLDQZrmbi + 2536757903U, // VPSHLDQZrmbik + 2538871439U, // VPSHLDQZrmbikz + 382065295U, // VPSHLDQZrmi + 1995692687U, // VPSHLDQZrmik + 1192499855U, // VPSHLDQZrmikz + 1088821903U, // VPSHLDQZrri + 2163137167U, // VPSHLDQZrrik + 1357585039U, // VPSHLDQZrrikz + 890572974U, // VPSHLDVDZ128m + 1167478958U, // VPSHLDVDZ128mb + 1436061870U, // VPSHLDVDZ128mbk + 1436061870U, // VPSHLDVDZ128mbkz + 985108654U, // VPSHLDVDZ128mk + 985108654U, // VPSHLDVDZ128mkz + 890278062U, // VPSHLDVDZ128r + 87052462U, // VPSHLDVDZ128rk + 89149614U, // VPSHLDVDZ128rkz + 890605742U, // VPSHLDVDZ256m + 1169576110U, // VPSHLDVDZ256mb + 1438159022U, // VPSHLDVDZ256mbk + 1438159022U, // VPSHLDVDZ256mbkz + 985125038U, // VPSHLDVDZ256mk + 985125038U, // VPSHLDVDZ256mkz + 890278062U, // VPSHLDVDZ256r + 87052462U, // VPSHLDVDZ256rk + 89149614U, // VPSHLDVDZ256rkz + 890671278U, // VPSHLDVDZm + 1171673262U, // VPSHLDVDZmb + 1440256174U, // VPSHLDVDZmbk + 1440256174U, // VPSHLDVDZmbkz + 985141422U, // VPSHLDVDZmk + 985141422U, // VPSHLDVDZmkz + 890278062U, // VPSHLDVDZr + 87052462U, // VPSHLDVDZrk + 89149614U, // VPSHLDVDZrkz + 890576960U, // VPSHLDVQZ128m + 1165287488U, // VPSHLDVQZ128mb + 1433952320U, // VPSHLDVQZ128mbk + 1433952320U, // VPSHLDVQZ128mbkz + 985112640U, // VPSHLDVQZ128mk + 985112640U, // VPSHLDVQZ128mkz + 890282048U, // VPSHLDVQZ128r + 87056448U, // VPSHLDVQZ128rk + 89153600U, // VPSHLDVQZ128rkz + 890609728U, // VPSHLDVQZ256m + 1167384640U, // VPSHLDVQZ256mb + 1436049472U, // VPSHLDVQZ256mbk + 1436049472U, // VPSHLDVQZ256mbkz + 985129024U, // VPSHLDVQZ256mk + 985129024U, // VPSHLDVQZ256mkz + 890282048U, // VPSHLDVQZ256r + 87056448U, // VPSHLDVQZ256rk + 89153600U, // VPSHLDVQZ256rkz + 890675264U, // VPSHLDVQZm + 1169481792U, // VPSHLDVQZmb + 1438146624U, // VPSHLDVQZmbk + 1438146624U, // VPSHLDVQZmbkz + 985145408U, // VPSHLDVQZmk + 985145408U, // VPSHLDVQZmkz + 890282048U, // VPSHLDVQZr + 87056448U, // VPSHLDVQZrk + 89153600U, // VPSHLDVQZrkz + 890580861U, // VPSHLDVWZ128m + 985116541U, // VPSHLDVWZ128mk + 985116541U, // VPSHLDVWZ128mkz + 890285949U, // VPSHLDVWZ128r + 87060349U, // VPSHLDVWZ128rk + 89157501U, // VPSHLDVWZ128rkz + 890613629U, // VPSHLDVWZ256m + 985132925U, // VPSHLDVWZ256mk + 985132925U, // VPSHLDVWZ256mkz + 890285949U, // VPSHLDVWZ256r + 87060349U, // VPSHLDVWZ256rk + 89157501U, // VPSHLDVWZ256rkz + 890679165U, // VPSHLDVWZm + 985149309U, // VPSHLDVWZmk + 985149309U, // VPSHLDVWZmkz + 890285949U, // VPSHLDVWZr + 87060349U, // VPSHLDVWZrk + 89157501U, // VPSHLDVWZrkz + 325446472U, // VPSHLDWZ128rmi + 1983114056U, // VPSHLDWZ128rmik + 1179921224U, // VPSHLDWZ128rmikz + 1088826184U, // VPSHLDWZ128rri + 2163141448U, // VPSHLDWZ128rrik + 1357589320U, // VPSHLDWZ128rrikz + 375778120U, // VPSHLDWZ256rmi + 1989405512U, // VPSHLDWZ256rmik + 1186212680U, // VPSHLDWZ256rmikz + 1088826184U, // VPSHLDWZ256rri + 2163141448U, // VPSHLDWZ256rrik + 1357589320U, // VPSHLDWZ256rrikz + 382069576U, // VPSHLDWZrmi + 1995696968U, // VPSHLDWZrmik + 1192504136U, // VPSHLDWZrmikz + 1088826184U, // VPSHLDWZrri + 2163141448U, // VPSHLDWZrrik + 1357589320U, // VPSHLDWZrrikz + 830802025U, // VPSHLDmr + 811845737U, // VPSHLDrm + 811649129U, // VPSHLDrr + 811649129U, // VPSHLDrr_REV + 830807210U, // VPSHLQmr + 811850922U, // VPSHLQrm + 811654314U, // VPSHLQrr + 811654314U, // VPSHLQrr_REV + 830811231U, // VPSHLWmr + 811854943U, // VPSHLWrm + 811658335U, // VPSHLWrr + 811658335U, // VPSHLWrr_REV + 1686489098U, // VPSHRDDZ128rmbi + 1710475274U, // VPSHRDDZ128rmbik + 1712588810U, // VPSHRDDZ128rmbikz + 325437450U, // VPSHRDDZ128rmi + 1983105034U, // VPSHRDDZ128rmik + 1179912202U, // VPSHRDDZ128rmikz + 1088817162U, // VPSHRDDZ128rri + 2163132426U, // VPSHRDDZ128rrik + 1357580298U, // VPSHRDDZ128rrikz + 2491795466U, // VPSHRDDZ256rmbi + 2515781642U, // VPSHRDDZ256rmbik + 2517895178U, // VPSHRDDZ256rmbikz + 375769098U, // VPSHRDDZ256rmi + 1989396490U, // VPSHRDDZ256rmik + 1186203658U, // VPSHRDDZ256rmikz + 1088817162U, // VPSHRDDZ256rri + 2163132426U, // VPSHRDDZ256rrik + 1357580298U, // VPSHRDDZ256rrikz + 2760230922U, // VPSHRDDZrmbi + 2784217098U, // VPSHRDDZrmbik + 2786330634U, // VPSHRDDZrmbikz + 382060554U, // VPSHRDDZrmi + 1995687946U, // VPSHRDDZrmik + 1192495114U, // VPSHRDDZrmikz + 1088817162U, // VPSHRDDZrri + 2163132426U, // VPSHRDDZrrik + 1357580298U, // VPSHRDDZrrikz + 3013991214U, // VPSHRDQZ128rmbi + 3073628974U, // VPSHRDQZ128rmbik + 3075742510U, // VPSHRDQZ128rmbikz + 325442350U, // VPSHRDQZ128rmi + 1983109934U, // VPSHRDQZ128rmik + 1179917102U, // VPSHRDQZ128rmikz + 1088822062U, // VPSHRDQZ128rri + 2163137326U, // VPSHRDQZ128rrik + 1357585198U, // VPSHRDQZ128rrikz + 1671813934U, // VPSHRDQZ256rmbi + 1731451694U, // VPSHRDQZ256rmbik + 1733565230U, // VPSHRDQZ256rmbikz + 375773998U, // VPSHRDQZ256rmi + 1989401390U, // VPSHRDQZ256rmik + 1186208558U, // VPSHRDQZ256rmikz + 1088822062U, // VPSHRDQZ256rri + 2163137326U, // VPSHRDQZ256rrik + 1357585198U, // VPSHRDQZ256rrikz + 2477120302U, // VPSHRDQZrmbi + 2536758062U, // VPSHRDQZrmbik + 2538871598U, // VPSHRDQZrmbikz + 382065454U, // VPSHRDQZrmi + 1995692846U, // VPSHRDQZrmik + 1192500014U, // VPSHRDQZrmikz + 1088822062U, // VPSHRDQZrri + 2163137326U, // VPSHRDQZrrik + 1357585198U, // VPSHRDQZrrikz + 890572984U, // VPSHRDVDZ128m + 1167478968U, // VPSHRDVDZ128mb + 1436061880U, // VPSHRDVDZ128mbk + 1436061880U, // VPSHRDVDZ128mbkz + 985108664U, // VPSHRDVDZ128mk + 985108664U, // VPSHRDVDZ128mkz + 890278072U, // VPSHRDVDZ128r + 87052472U, // VPSHRDVDZ128rk + 89149624U, // VPSHRDVDZ128rkz + 890605752U, // VPSHRDVDZ256m + 1169576120U, // VPSHRDVDZ256mb + 1438159032U, // VPSHRDVDZ256mbk + 1438159032U, // VPSHRDVDZ256mbkz + 985125048U, // VPSHRDVDZ256mk + 985125048U, // VPSHRDVDZ256mkz + 890278072U, // VPSHRDVDZ256r + 87052472U, // VPSHRDVDZ256rk + 89149624U, // VPSHRDVDZ256rkz + 890671288U, // VPSHRDVDZm + 1171673272U, // VPSHRDVDZmb + 1440256184U, // VPSHRDVDZmbk + 1440256184U, // VPSHRDVDZmbkz + 985141432U, // VPSHRDVDZmk + 985141432U, // VPSHRDVDZmkz + 890278072U, // VPSHRDVDZr + 87052472U, // VPSHRDVDZrk + 89149624U, // VPSHRDVDZrkz + 890576970U, // VPSHRDVQZ128m + 1165287498U, // VPSHRDVQZ128mb + 1433952330U, // VPSHRDVQZ128mbk + 1433952330U, // VPSHRDVQZ128mbkz + 985112650U, // VPSHRDVQZ128mk + 985112650U, // VPSHRDVQZ128mkz + 890282058U, // VPSHRDVQZ128r + 87056458U, // VPSHRDVQZ128rk + 89153610U, // VPSHRDVQZ128rkz + 890609738U, // VPSHRDVQZ256m + 1167384650U, // VPSHRDVQZ256mb + 1436049482U, // VPSHRDVQZ256mbk + 1436049482U, // VPSHRDVQZ256mbkz + 985129034U, // VPSHRDVQZ256mk + 985129034U, // VPSHRDVQZ256mkz + 890282058U, // VPSHRDVQZ256r + 87056458U, // VPSHRDVQZ256rk + 89153610U, // VPSHRDVQZ256rkz + 890675274U, // VPSHRDVQZm + 1169481802U, // VPSHRDVQZmb + 1438146634U, // VPSHRDVQZmbk + 1438146634U, // VPSHRDVQZmbkz + 985145418U, // VPSHRDVQZmk + 985145418U, // VPSHRDVQZmkz + 890282058U, // VPSHRDVQZr + 87056458U, // VPSHRDVQZrk + 89153610U, // VPSHRDVQZrkz + 890580871U, // VPSHRDVWZ128m + 985116551U, // VPSHRDVWZ128mk + 985116551U, // VPSHRDVWZ128mkz + 890285959U, // VPSHRDVWZ128r + 87060359U, // VPSHRDVWZ128rk + 89157511U, // VPSHRDVWZ128rkz + 890613639U, // VPSHRDVWZ256m + 985132935U, // VPSHRDVWZ256mk + 985132935U, // VPSHRDVWZ256mkz + 890285959U, // VPSHRDVWZ256r + 87060359U, // VPSHRDVWZ256rk + 89157511U, // VPSHRDVWZ256rkz + 890679175U, // VPSHRDVWZm + 985149319U, // VPSHRDVWZmk + 985149319U, // VPSHRDVWZmkz + 890285959U, // VPSHRDVWZr + 87060359U, // VPSHRDVWZrk + 89157511U, // VPSHRDVWZrkz + 325446518U, // VPSHRDWZ128rmi + 1983114102U, // VPSHRDWZ128rmik + 1179921270U, // VPSHRDWZ128rmikz + 1088826230U, // VPSHRDWZ128rri + 2163141494U, // VPSHRDWZ128rrik + 1357589366U, // VPSHRDWZ128rrikz + 375778166U, // VPSHRDWZ256rmi + 1989405558U, // VPSHRDWZ256rmik + 1186212726U, // VPSHRDWZ256rmikz + 1088826230U, // VPSHRDWZ256rri + 2163141494U, // VPSHRDWZ256rrik + 1357589366U, // VPSHRDWZ256rrikz + 382069622U, // VPSHRDWZrmi + 1995697014U, // VPSHRDWZrmik + 1192504182U, // VPSHRDWZrmikz + 1088826230U, // VPSHRDWZrri + 2163141494U, // VPSHRDWZrrik + 1357589366U, // VPSHRDWZrrikz + 811844782U, // VPSHUFBITQMBZ128rm + 890569902U, // VPSHUFBITQMBZ128rmk + 811648174U, // VPSHUFBITQMBZ128rr + 890274990U, // VPSHUFBITQMBZ128rrk + 812860590U, // VPSHUFBITQMBZ256rm + 890602670U, // VPSHUFBITQMBZ256rmk + 811648174U, // VPSHUFBITQMBZ256rr + 890274990U, // VPSHUFBITQMBZ256rrk + 812876974U, // VPSHUFBITQMBZrm + 890668206U, // VPSHUFBITQMBZrmk + 811648174U, // VPSHUFBITQMBZrr + 890274990U, // VPSHUFBITQMBZrrk + 812860457U, // VPSHUFBYrm + 811648041U, // VPSHUFBYrr + 811844649U, // VPSHUFBZ128rm + 985105449U, // VPSHUFBZ128rmk + 890569769U, // VPSHUFBZ128rmkz + 811648041U, // VPSHUFBZ128rr + 87049257U, // VPSHUFBZ128rrk + 890274857U, // VPSHUFBZ128rrkz + 812860457U, // VPSHUFBZ256rm + 985121833U, // VPSHUFBZ256rmk + 890602537U, // VPSHUFBZ256rmkz + 811648041U, // VPSHUFBZ256rr + 87049257U, // VPSHUFBZ256rrk + 890274857U, // VPSHUFBZ256rrkz + 812876841U, // VPSHUFBZrm + 985138217U, // VPSHUFBZrmk + 890668073U, // VPSHUFBZrmkz + 811648041U, // VPSHUFBZrr + 87049257U, // VPSHUFBZrrk + 890274857U, // VPSHUFBZrrkz + 811844649U, // VPSHUFBrm + 811648041U, // VPSHUFBrr + 1009027119U, // VPSHUFDYmi + 283428911U, // VPSHUFDYri + 1638172719U, // VPSHUFDZ128mbi + 1712588847U, // VPSHUFDZ128mbik + 1686489135U, // VPSHUFDZ128mbikz + 830769199U, // VPSHUFDZ128mi + 643041327U, // VPSHUFDZ128mik + 593872943U, // VPSHUFDZ128mikz + 283428911U, // VPSHUFDZ128ri + 1357580335U, // VPSHUFDZ128rik + 1088817199U, // VPSHUFDZ128rikz + 2443479087U, // VPSHUFDZ256mbi + 2517895215U, // VPSHUFDZ256mbik + 2491795503U, // VPSHUFDZ256mbikz + 1009027119U, // VPSHUFDZ256mi + 649332783U, // VPSHUFDZ256mik + 644204591U, // VPSHUFDZ256mikz + 283428911U, // VPSHUFDZ256ri + 1357580335U, // VPSHUFDZ256rik + 1088817199U, // VPSHUFDZ256rikz + 2711914543U, // VPSHUFDZmbi + 2786330671U, // VPSHUFDZmbik + 2760230959U, // VPSHUFDZmbikz + 1011124271U, // VPSHUFDZmi + 655624239U, // VPSHUFDZmik + 650496047U, // VPSHUFDZmikz + 283428911U, // VPSHUFDZri + 1357580335U, // VPSHUFDZrik + 1088817199U, // VPSHUFDZrikz + 830769199U, // VPSHUFDmi + 283428911U, // VPSHUFDri + 1009036328U, // VPSHUFHWYmi + 283438120U, // VPSHUFHWYri + 830778408U, // VPSHUFHWZ128mi + 643050536U, // VPSHUFHWZ128mik + 593882152U, // VPSHUFHWZ128mikz + 283438120U, // VPSHUFHWZ128ri + 1357589544U, // VPSHUFHWZ128rik + 1088826408U, // VPSHUFHWZ128rikz + 1009036328U, // VPSHUFHWZ256mi + 649341992U, // VPSHUFHWZ256mik + 644213800U, // VPSHUFHWZ256mikz + 283438120U, // VPSHUFHWZ256ri + 1357589544U, // VPSHUFHWZ256rik + 1088826408U, // VPSHUFHWZ256rikz + 1011133480U, // VPSHUFHWZmi + 655633448U, // VPSHUFHWZmik + 650505256U, // VPSHUFHWZmikz + 283438120U, // VPSHUFHWZri + 1357589544U, // VPSHUFHWZrik + 1088826408U, // VPSHUFHWZrikz + 830778408U, // VPSHUFHWmi + 283438120U, // VPSHUFHWri + 1009036373U, // VPSHUFLWYmi + 283438165U, // VPSHUFLWYri + 830778453U, // VPSHUFLWZ128mi + 643050581U, // VPSHUFLWZ128mik + 593882197U, // VPSHUFLWZ128mikz + 283438165U, // VPSHUFLWZ128ri + 1357589589U, // VPSHUFLWZ128rik + 1088826453U, // VPSHUFLWZ128rikz + 1009036373U, // VPSHUFLWZ256mi + 649342037U, // VPSHUFLWZ256mik + 644213845U, // VPSHUFLWZ256mikz + 283438165U, // VPSHUFLWZ256ri + 1357589589U, // VPSHUFLWZ256rik + 1088826453U, // VPSHUFLWZ256rikz + 1011133525U, // VPSHUFLWZmi + 655633493U, // VPSHUFLWZmik + 650505301U, // VPSHUFLWZmikz + 283438165U, // VPSHUFLWZri + 1357589589U, // VPSHUFLWZrik + 1088826453U, // VPSHUFLWZrikz + 830778453U, // VPSHUFLWmi + 283438165U, // VPSHUFLWri + 812860630U, // VPSIGNBYrm + 811648214U, // VPSIGNBYrr + 811844822U, // VPSIGNBrm + 811648214U, // VPSIGNBrr + 812861686U, // VPSIGNDYrm + 811649270U, // VPSIGNDYrr + 811845878U, // VPSIGNDrm + 811649270U, // VPSIGNDrr + 812870885U, // VPSIGNWYrm + 811658469U, // VPSIGNWYrr + 811855077U, // VPSIGNWrm + 811658469U, // VPSIGNWrr + 283433636U, // VPSLLDQYri + 830773924U, // VPSLLDQZ128rm + 283433636U, // VPSLLDQZ128rr + 1009031844U, // VPSLLDQZ256rm + 283433636U, // VPSLLDQZ256rr + 1011128996U, // VPSLLDQZrm + 283433636U, // VPSLLDQZrr + 283433636U, // VPSLLDQri + 283428977U, // VPSLLDYri + 811845745U, // VPSLLDYrm + 811649137U, // VPSLLDYrr + 1638172785U, // VPSLLDZ128mbi + 1712588913U, // VPSLLDZ128mbik + 1686489201U, // VPSLLDZ128mbikz + 830769265U, // VPSLLDZ128mi + 643041393U, // VPSLLDZ128mik + 593873009U, // VPSLLDZ128mikz + 283428977U, // VPSLLDZ128ri + 1357580401U, // VPSLLDZ128rik + 1088817265U, // VPSLLDZ128rikz + 811845745U, // VPSLLDZ128rm + 985106545U, // VPSLLDZ128rmk + 890570865U, // VPSLLDZ128rmkz + 811649137U, // VPSLLDZ128rr + 87050353U, // VPSLLDZ128rrk + 890275953U, // VPSLLDZ128rrkz + 2443479153U, // VPSLLDZ256mbi + 2517895281U, // VPSLLDZ256mbik + 2491795569U, // VPSLLDZ256mbikz + 1009027185U, // VPSLLDZ256mi + 649332849U, // VPSLLDZ256mik + 644204657U, // VPSLLDZ256mikz + 283428977U, // VPSLLDZ256ri + 1357580401U, // VPSLLDZ256rik + 1088817265U, // VPSLLDZ256rikz + 811845745U, // VPSLLDZ256rm + 985106545U, // VPSLLDZ256rmk + 890570865U, // VPSLLDZ256rmkz + 811649137U, // VPSLLDZ256rr + 87050353U, // VPSLLDZ256rrk + 890275953U, // VPSLLDZ256rrkz + 2711914609U, // VPSLLDZmbi + 2786330737U, // VPSLLDZmbik + 2760231025U, // VPSLLDZmbikz + 1011124337U, // VPSLLDZmi + 655624305U, // VPSLLDZmik + 650496113U, // VPSLLDZmikz + 283428977U, // VPSLLDZri + 1357580401U, // VPSLLDZrik + 1088817265U, // VPSLLDZrikz + 811845745U, // VPSLLDZrm + 985106545U, // VPSLLDZrmk + 890570865U, // VPSLLDZrmkz + 811649137U, // VPSLLDZrr + 87050353U, // VPSLLDZrrk + 890275953U, // VPSLLDZrrkz + 283428977U, // VPSLLDri + 811845745U, // VPSLLDrm + 811649137U, // VPSLLDrr + 283434189U, // VPSLLQYri + 811850957U, // VPSLLQYrm + 811654349U, // VPSLLQYrr + 2982452429U, // VPSLLQZ128mbi + 3075742925U, // VPSLLQZ128mbik + 3013991629U, // VPSLLQZ128mbikz + 830774477U, // VPSLLQZ128mi + 643046605U, // VPSLLQZ128mik + 593878221U, // VPSLLQZ128mikz + 283434189U, // VPSLLQZ128ri + 1357585613U, // VPSLLQZ128rik + 1088822477U, // VPSLLQZ128rikz + 811850957U, // VPSLLQZ128rm + 985111757U, // VPSLLQZ128rmk + 890576077U, // VPSLLQZ128rmkz + 811654349U, // VPSLLQZ128rr + 87055565U, // VPSLLQZ128rrk + 890281165U, // VPSLLQZ128rrkz + 1640275149U, // VPSLLQZ256mbi + 1733565645U, // VPSLLQZ256mbik + 1671814349U, // VPSLLQZ256mbikz + 1009032397U, // VPSLLQZ256mi + 649338061U, // VPSLLQZ256mik + 644209869U, // VPSLLQZ256mikz + 283434189U, // VPSLLQZ256ri + 1357585613U, // VPSLLQZ256rik + 1088822477U, // VPSLLQZ256rikz + 811850957U, // VPSLLQZ256rm + 985111757U, // VPSLLQZ256rmk + 890576077U, // VPSLLQZ256rmkz + 811654349U, // VPSLLQZ256rr + 87055565U, // VPSLLQZ256rrk + 890281165U, // VPSLLQZ256rrkz + 2445581517U, // VPSLLQZmbi + 2538872013U, // VPSLLQZmbik + 2477120717U, // VPSLLQZmbikz + 1011129549U, // VPSLLQZmi + 655629517U, // VPSLLQZmik + 650501325U, // VPSLLQZmikz + 283434189U, // VPSLLQZri + 1357585613U, // VPSLLQZrik + 1088822477U, // VPSLLQZrikz + 811850957U, // VPSLLQZrm + 985111757U, // VPSLLQZrmk + 890576077U, // VPSLLQZrmkz + 811654349U, // VPSLLQZrr + 87055565U, // VPSLLQZrrk + 890281165U, // VPSLLQZrrkz + 283434189U, // VPSLLQri + 811850957U, // VPSLLQrm + 811654349U, // VPSLLQrr + 812863682U, // VPSLLVDYrm + 811651266U, // VPSLLVDYrr + 811847874U, // VPSLLVDZ128rm + 360796354U, // VPSLLVDZ128rmb + 1436061890U, // VPSLLVDZ128rmbk + 1167478978U, // VPSLLVDZ128rmbkz + 985108674U, // VPSLLVDZ128rmk + 890572994U, // VPSLLVDZ128rmkz + 811651266U, // VPSLLVDZ128rr + 87052482U, // VPSLLVDZ128rrk + 890278082U, // VPSLLVDZ128rrkz + 812863682U, // VPSLLVDZ256rm + 362893506U, // VPSLLVDZ256rmb + 1438159042U, // VPSLLVDZ256rmbk + 1169576130U, // VPSLLVDZ256rmbkz + 985125058U, // VPSLLVDZ256rmk + 890605762U, // VPSLLVDZ256rmkz + 811651266U, // VPSLLVDZ256rr + 87052482U, // VPSLLVDZ256rrk + 890278082U, // VPSLLVDZ256rrkz + 812880066U, // VPSLLVDZrm + 364990658U, // VPSLLVDZrmb + 1440256194U, // VPSLLVDZrmbk + 1171673282U, // VPSLLVDZrmbkz + 985141442U, // VPSLLVDZrmk + 890671298U, // VPSLLVDZrmkz + 811651266U, // VPSLLVDZrr + 87052482U, // VPSLLVDZrrk + 890278082U, // VPSLLVDZrrkz + 811847874U, // VPSLLVDrm + 811651266U, // VPSLLVDrr + 812867675U, // VPSLLVQYrm + 811655259U, // VPSLLVQYrr + 811851867U, // VPSLLVQZ128rm + 358719579U, // VPSLLVQZ128rmb + 1433952347U, // VPSLLVQZ128rmbk + 1165287515U, // VPSLLVQZ128rmbkz + 985112667U, // VPSLLVQZ128rmk + 890576987U, // VPSLLVQZ128rmkz + 811655259U, // VPSLLVQZ128rr + 87056475U, // VPSLLVQZ128rrk + 890282075U, // VPSLLVQZ128rrkz + 812867675U, // VPSLLVQZ256rm + 360816731U, // VPSLLVQZ256rmb + 1436049499U, // VPSLLVQZ256rmbk + 1167384667U, // VPSLLVQZ256rmbkz + 985129051U, // VPSLLVQZ256rmk + 890609755U, // VPSLLVQZ256rmkz + 811655259U, // VPSLLVQZ256rr + 87056475U, // VPSLLVQZ256rrk + 890282075U, // VPSLLVQZ256rrkz + 812884059U, // VPSLLVQZrm + 362913883U, // VPSLLVQZrmb + 1438146651U, // VPSLLVQZrmbk + 1169481819U, // VPSLLVQZrmbkz + 985145435U, // VPSLLVQZrmk + 890675291U, // VPSLLVQZrmkz + 811655259U, // VPSLLVQZrr + 87056475U, // VPSLLVQZrrk + 890282075U, // VPSLLVQZrrkz + 811851867U, // VPSLLVQrm + 811655259U, // VPSLLVQrr + 811855768U, // VPSLLVWZ128rm + 985116568U, // VPSLLVWZ128rmk + 890580888U, // VPSLLVWZ128rmkz + 811659160U, // VPSLLVWZ128rr + 87060376U, // VPSLLVWZ128rrk + 890285976U, // VPSLLVWZ128rrkz + 812871576U, // VPSLLVWZ256rm + 985132952U, // VPSLLVWZ256rmk + 890613656U, // VPSLLVWZ256rmkz + 811659160U, // VPSLLVWZ256rr + 87060376U, // VPSLLVWZ256rrk + 890285976U, // VPSLLVWZ256rrkz + 812887960U, // VPSLLVWZrm + 985149336U, // VPSLLVWZrmk + 890679192U, // VPSLLVWZrmkz + 811659160U, // VPSLLVWZrr + 87060376U, // VPSLLVWZrrk + 890285976U, // VPSLLVWZrrkz + 283438191U, // VPSLLWYri + 811854959U, // VPSLLWYrm + 811658351U, // VPSLLWYrr + 830778479U, // VPSLLWZ128mi + 643050607U, // VPSLLWZ128mik + 593882223U, // VPSLLWZ128mikz + 283438191U, // VPSLLWZ128ri + 1357589615U, // VPSLLWZ128rik + 1088826479U, // VPSLLWZ128rikz + 811854959U, // VPSLLWZ128rm + 985115759U, // VPSLLWZ128rmk + 890580079U, // VPSLLWZ128rmkz + 811658351U, // VPSLLWZ128rr + 87059567U, // VPSLLWZ128rrk + 890285167U, // VPSLLWZ128rrkz + 1009036399U, // VPSLLWZ256mi + 649342063U, // VPSLLWZ256mik + 644213871U, // VPSLLWZ256mikz + 283438191U, // VPSLLWZ256ri + 1357589615U, // VPSLLWZ256rik + 1088826479U, // VPSLLWZ256rikz + 811854959U, // VPSLLWZ256rm + 985115759U, // VPSLLWZ256rmk + 890580079U, // VPSLLWZ256rmkz + 811658351U, // VPSLLWZ256rr + 87059567U, // VPSLLWZ256rrk + 890285167U, // VPSLLWZ256rrkz + 1011133551U, // VPSLLWZmi + 655633519U, // VPSLLWZmik + 650505327U, // VPSLLWZmikz + 283438191U, // VPSLLWZri + 1357589615U, // VPSLLWZrik + 1088826479U, // VPSLLWZrikz + 811854959U, // VPSLLWZrm + 985115759U, // VPSLLWZrmk + 890580079U, // VPSLLWZrmkz + 811658351U, // VPSLLWZrr + 87059567U, // VPSLLWZrrk + 890285167U, // VPSLLWZrrkz + 283438191U, // VPSLLWri + 811854959U, // VPSLLWrm + 811658351U, // VPSLLWrr + 283428705U, // VPSRADYri + 811845473U, // VPSRADYrm + 811648865U, // VPSRADYrr + 1638172513U, // VPSRADZ128mbi + 1712588641U, // VPSRADZ128mbik + 1686488929U, // VPSRADZ128mbikz + 830768993U, // VPSRADZ128mi + 643041121U, // VPSRADZ128mik + 593872737U, // VPSRADZ128mikz + 283428705U, // VPSRADZ128ri + 1357580129U, // VPSRADZ128rik + 1088816993U, // VPSRADZ128rikz + 811845473U, // VPSRADZ128rm + 985106273U, // VPSRADZ128rmk + 890570593U, // VPSRADZ128rmkz + 811648865U, // VPSRADZ128rr + 87050081U, // VPSRADZ128rrk + 890275681U, // VPSRADZ128rrkz + 2443478881U, // VPSRADZ256mbi + 2517895009U, // VPSRADZ256mbik + 2491795297U, // VPSRADZ256mbikz + 1009026913U, // VPSRADZ256mi + 649332577U, // VPSRADZ256mik + 644204385U, // VPSRADZ256mikz + 283428705U, // VPSRADZ256ri + 1357580129U, // VPSRADZ256rik + 1088816993U, // VPSRADZ256rikz + 811845473U, // VPSRADZ256rm + 985106273U, // VPSRADZ256rmk + 890570593U, // VPSRADZ256rmkz + 811648865U, // VPSRADZ256rr + 87050081U, // VPSRADZ256rrk + 890275681U, // VPSRADZ256rrkz + 2711914337U, // VPSRADZmbi + 2786330465U, // VPSRADZmbik + 2760230753U, // VPSRADZmbikz + 1011124065U, // VPSRADZmi + 655624033U, // VPSRADZmik + 650495841U, // VPSRADZmikz + 283428705U, // VPSRADZri + 1357580129U, // VPSRADZrik + 1088816993U, // VPSRADZrikz + 811845473U, // VPSRADZrm + 985106273U, // VPSRADZrmk + 890570593U, // VPSRADZrmkz + 811648865U, // VPSRADZrr + 87050081U, // VPSRADZrrk + 890275681U, // VPSRADZrrkz + 283428705U, // VPSRADri + 811845473U, // VPSRADrm + 811648865U, // VPSRADrr + 2982451572U, // VPSRAQZ128mbi + 3075742068U, // VPSRAQZ128mbik + 3013990772U, // VPSRAQZ128mbikz + 830773620U, // VPSRAQZ128mi + 643045748U, // VPSRAQZ128mik + 593877364U, // VPSRAQZ128mikz + 283433332U, // VPSRAQZ128ri + 1357584756U, // VPSRAQZ128rik + 1088821620U, // VPSRAQZ128rikz + 811850100U, // VPSRAQZ128rm + 985110900U, // VPSRAQZ128rmk + 890575220U, // VPSRAQZ128rmkz + 811653492U, // VPSRAQZ128rr + 87054708U, // VPSRAQZ128rrk + 890280308U, // VPSRAQZ128rrkz + 1640274292U, // VPSRAQZ256mbi + 1733564788U, // VPSRAQZ256mbik + 1671813492U, // VPSRAQZ256mbikz + 1009031540U, // VPSRAQZ256mi + 649337204U, // VPSRAQZ256mik + 644209012U, // VPSRAQZ256mikz + 283433332U, // VPSRAQZ256ri + 1357584756U, // VPSRAQZ256rik + 1088821620U, // VPSRAQZ256rikz + 811850100U, // VPSRAQZ256rm + 985110900U, // VPSRAQZ256rmk + 890575220U, // VPSRAQZ256rmkz + 811653492U, // VPSRAQZ256rr + 87054708U, // VPSRAQZ256rrk + 890280308U, // VPSRAQZ256rrkz + 2445580660U, // VPSRAQZmbi + 2538871156U, // VPSRAQZmbik + 2477119860U, // VPSRAQZmbikz + 1011128692U, // VPSRAQZmi + 655628660U, // VPSRAQZmik + 650500468U, // VPSRAQZmikz + 283433332U, // VPSRAQZri + 1357584756U, // VPSRAQZrik + 1088821620U, // VPSRAQZrikz + 811850100U, // VPSRAQZrm + 985110900U, // VPSRAQZrmk + 890575220U, // VPSRAQZrmkz + 811653492U, // VPSRAQZrr + 87054708U, // VPSRAQZrrk + 890280308U, // VPSRAQZrrkz + 812863653U, // VPSRAVDYrm + 811651237U, // VPSRAVDYrr + 811847845U, // VPSRAVDZ128rm + 360796325U, // VPSRAVDZ128rmb + 1436061861U, // VPSRAVDZ128rmbk + 1167478949U, // VPSRAVDZ128rmbkz + 985108645U, // VPSRAVDZ128rmk + 890572965U, // VPSRAVDZ128rmkz + 811651237U, // VPSRAVDZ128rr + 87052453U, // VPSRAVDZ128rrk + 890278053U, // VPSRAVDZ128rrkz + 812863653U, // VPSRAVDZ256rm + 362893477U, // VPSRAVDZ256rmb + 1438159013U, // VPSRAVDZ256rmbk + 1169576101U, // VPSRAVDZ256rmbkz + 985125029U, // VPSRAVDZ256rmk + 890605733U, // VPSRAVDZ256rmkz + 811651237U, // VPSRAVDZ256rr + 87052453U, // VPSRAVDZ256rrk + 890278053U, // VPSRAVDZ256rrkz + 812880037U, // VPSRAVDZrm + 364990629U, // VPSRAVDZrmb + 1440256165U, // VPSRAVDZrmbk + 1171673253U, // VPSRAVDZrmbkz + 985141413U, // VPSRAVDZrmk + 890671269U, // VPSRAVDZrmkz + 811651237U, // VPSRAVDZrr + 87052453U, // VPSRAVDZrrk + 890278053U, // VPSRAVDZrrkz + 811847845U, // VPSRAVDrm + 811651237U, // VPSRAVDrr + 811851831U, // VPSRAVQZ128rm + 358719543U, // VPSRAVQZ128rmb + 1433952311U, // VPSRAVQZ128rmbk + 1165287479U, // VPSRAVQZ128rmbkz + 985112631U, // VPSRAVQZ128rmk + 890576951U, // VPSRAVQZ128rmkz + 811655223U, // VPSRAVQZ128rr + 87056439U, // VPSRAVQZ128rrk + 890282039U, // VPSRAVQZ128rrkz + 812867639U, // VPSRAVQZ256rm + 360816695U, // VPSRAVQZ256rmb + 1436049463U, // VPSRAVQZ256rmbk + 1167384631U, // VPSRAVQZ256rmbkz + 985129015U, // VPSRAVQZ256rmk + 890609719U, // VPSRAVQZ256rmkz + 811655223U, // VPSRAVQZ256rr + 87056439U, // VPSRAVQZ256rrk + 890282039U, // VPSRAVQZ256rrkz + 812884023U, // VPSRAVQZrm + 362913847U, // VPSRAVQZrmb + 1438146615U, // VPSRAVQZrmbk + 1169481783U, // VPSRAVQZrmbkz + 985145399U, // VPSRAVQZrmk + 890675255U, // VPSRAVQZrmkz + 811655223U, // VPSRAVQZrr + 87056439U, // VPSRAVQZrrk + 890282039U, // VPSRAVQZrrkz + 811855732U, // VPSRAVWZ128rm + 985116532U, // VPSRAVWZ128rmk + 890580852U, // VPSRAVWZ128rmkz + 811659124U, // VPSRAVWZ128rr + 87060340U, // VPSRAVWZ128rrk + 890285940U, // VPSRAVWZ128rrkz + 812871540U, // VPSRAVWZ256rm + 985132916U, // VPSRAVWZ256rmk + 890613620U, // VPSRAVWZ256rmkz + 811659124U, // VPSRAVWZ256rr + 87060340U, // VPSRAVWZ256rrk + 890285940U, // VPSRAVWZ256rrkz + 812887924U, // VPSRAVWZrm + 985149300U, // VPSRAVWZrmk + 890679156U, // VPSRAVWZrmkz + 811659124U, // VPSRAVWZrr + 87060340U, // VPSRAVWZrrk + 890285940U, // VPSRAVWZrrkz + 283437637U, // VPSRAWYri + 811854405U, // VPSRAWYrm + 811657797U, // VPSRAWYrr + 830777925U, // VPSRAWZ128mi + 643050053U, // VPSRAWZ128mik + 593881669U, // VPSRAWZ128mikz + 283437637U, // VPSRAWZ128ri + 1357589061U, // VPSRAWZ128rik + 1088825925U, // VPSRAWZ128rikz + 811854405U, // VPSRAWZ128rm + 985115205U, // VPSRAWZ128rmk + 890579525U, // VPSRAWZ128rmkz + 811657797U, // VPSRAWZ128rr + 87059013U, // VPSRAWZ128rrk + 890284613U, // VPSRAWZ128rrkz + 1009035845U, // VPSRAWZ256mi + 649341509U, // VPSRAWZ256mik + 644213317U, // VPSRAWZ256mikz + 283437637U, // VPSRAWZ256ri + 1357589061U, // VPSRAWZ256rik + 1088825925U, // VPSRAWZ256rikz + 811854405U, // VPSRAWZ256rm + 985115205U, // VPSRAWZ256rmk + 890579525U, // VPSRAWZ256rmkz + 811657797U, // VPSRAWZ256rr + 87059013U, // VPSRAWZ256rrk + 890284613U, // VPSRAWZ256rrkz + 1011132997U, // VPSRAWZmi + 655632965U, // VPSRAWZmik + 650504773U, // VPSRAWZmikz + 283437637U, // VPSRAWZri + 1357589061U, // VPSRAWZrik + 1088825925U, // VPSRAWZrikz + 811854405U, // VPSRAWZrm + 985115205U, // VPSRAWZrmk + 890579525U, // VPSRAWZrmkz + 811657797U, // VPSRAWZrr + 87059013U, // VPSRAWZrrk + 890284613U, // VPSRAWZrrkz + 283437637U, // VPSRAWri + 811854405U, // VPSRAWrm + 811657797U, // VPSRAWrr + 283433645U, // VPSRLDQYri + 830773933U, // VPSRLDQZ128rm + 283433645U, // VPSRLDQZ128rr + 1009031853U, // VPSRLDQZ256rm + 283433645U, // VPSRLDQZ256rr + 1011129005U, // VPSRLDQZrm + 283433645U, // VPSRLDQZrr + 283433645U, // VPSRLDQri + 283429002U, // VPSRLDYri + 811845770U, // VPSRLDYrm + 811649162U, // VPSRLDYrr + 1638172810U, // VPSRLDZ128mbi + 1712588938U, // VPSRLDZ128mbik + 1686489226U, // VPSRLDZ128mbikz + 830769290U, // VPSRLDZ128mi + 643041418U, // VPSRLDZ128mik + 593873034U, // VPSRLDZ128mikz + 283429002U, // VPSRLDZ128ri + 1357580426U, // VPSRLDZ128rik + 1088817290U, // VPSRLDZ128rikz + 811845770U, // VPSRLDZ128rm + 985106570U, // VPSRLDZ128rmk + 890570890U, // VPSRLDZ128rmkz + 811649162U, // VPSRLDZ128rr + 87050378U, // VPSRLDZ128rrk + 890275978U, // VPSRLDZ128rrkz + 2443479178U, // VPSRLDZ256mbi + 2517895306U, // VPSRLDZ256mbik + 2491795594U, // VPSRLDZ256mbikz + 1009027210U, // VPSRLDZ256mi + 649332874U, // VPSRLDZ256mik + 644204682U, // VPSRLDZ256mikz + 283429002U, // VPSRLDZ256ri + 1357580426U, // VPSRLDZ256rik + 1088817290U, // VPSRLDZ256rikz + 811845770U, // VPSRLDZ256rm + 985106570U, // VPSRLDZ256rmk + 890570890U, // VPSRLDZ256rmkz + 811649162U, // VPSRLDZ256rr + 87050378U, // VPSRLDZ256rrk + 890275978U, // VPSRLDZ256rrkz + 2711914634U, // VPSRLDZmbi + 2786330762U, // VPSRLDZmbik + 2760231050U, // VPSRLDZmbikz + 1011124362U, // VPSRLDZmi + 655624330U, // VPSRLDZmik + 650496138U, // VPSRLDZmikz + 283429002U, // VPSRLDZri + 1357580426U, // VPSRLDZrik + 1088817290U, // VPSRLDZrikz + 811845770U, // VPSRLDZrm + 985106570U, // VPSRLDZrmk + 890570890U, // VPSRLDZrmkz + 811649162U, // VPSRLDZrr + 87050378U, // VPSRLDZrrk + 890275978U, // VPSRLDZrrkz + 283429002U, // VPSRLDri + 811845770U, // VPSRLDrm + 811649162U, // VPSRLDrr + 283434214U, // VPSRLQYri + 811850982U, // VPSRLQYrm + 811654374U, // VPSRLQYrr + 2982452454U, // VPSRLQZ128mbi + 3075742950U, // VPSRLQZ128mbik + 3013991654U, // VPSRLQZ128mbikz + 830774502U, // VPSRLQZ128mi + 643046630U, // VPSRLQZ128mik + 593878246U, // VPSRLQZ128mikz + 283434214U, // VPSRLQZ128ri + 1357585638U, // VPSRLQZ128rik + 1088822502U, // VPSRLQZ128rikz + 811850982U, // VPSRLQZ128rm + 985111782U, // VPSRLQZ128rmk + 890576102U, // VPSRLQZ128rmkz + 811654374U, // VPSRLQZ128rr + 87055590U, // VPSRLQZ128rrk + 890281190U, // VPSRLQZ128rrkz + 1640275174U, // VPSRLQZ256mbi + 1733565670U, // VPSRLQZ256mbik + 1671814374U, // VPSRLQZ256mbikz + 1009032422U, // VPSRLQZ256mi + 649338086U, // VPSRLQZ256mik + 644209894U, // VPSRLQZ256mikz + 283434214U, // VPSRLQZ256ri + 1357585638U, // VPSRLQZ256rik + 1088822502U, // VPSRLQZ256rikz + 811850982U, // VPSRLQZ256rm + 985111782U, // VPSRLQZ256rmk + 890576102U, // VPSRLQZ256rmkz + 811654374U, // VPSRLQZ256rr + 87055590U, // VPSRLQZ256rrk + 890281190U, // VPSRLQZ256rrkz + 2445581542U, // VPSRLQZmbi + 2538872038U, // VPSRLQZmbik + 2477120742U, // VPSRLQZmbikz + 1011129574U, // VPSRLQZmi + 655629542U, // VPSRLQZmik + 650501350U, // VPSRLQZmikz + 283434214U, // VPSRLQZri + 1357585638U, // VPSRLQZrik + 1088822502U, // VPSRLQZrikz + 811850982U, // VPSRLQZrm + 985111782U, // VPSRLQZrmk + 890576102U, // VPSRLQZrmkz + 811654374U, // VPSRLQZrr + 87055590U, // VPSRLQZrrk + 890281190U, // VPSRLQZrrkz + 283434214U, // VPSRLQri + 811850982U, // VPSRLQrm + 811654374U, // VPSRLQrr + 812863700U, // VPSRLVDYrm + 811651284U, // VPSRLVDYrr + 811847892U, // VPSRLVDZ128rm + 360796372U, // VPSRLVDZ128rmb + 1436061908U, // VPSRLVDZ128rmbk + 1167478996U, // VPSRLVDZ128rmbkz + 985108692U, // VPSRLVDZ128rmk + 890573012U, // VPSRLVDZ128rmkz + 811651284U, // VPSRLVDZ128rr + 87052500U, // VPSRLVDZ128rrk + 890278100U, // VPSRLVDZ128rrkz + 812863700U, // VPSRLVDZ256rm + 362893524U, // VPSRLVDZ256rmb + 1438159060U, // VPSRLVDZ256rmbk + 1169576148U, // VPSRLVDZ256rmbkz + 985125076U, // VPSRLVDZ256rmk + 890605780U, // VPSRLVDZ256rmkz + 811651284U, // VPSRLVDZ256rr + 87052500U, // VPSRLVDZ256rrk + 890278100U, // VPSRLVDZ256rrkz + 812880084U, // VPSRLVDZrm + 364990676U, // VPSRLVDZrmb + 1440256212U, // VPSRLVDZrmbk + 1171673300U, // VPSRLVDZrmbkz + 985141460U, // VPSRLVDZrmk + 890671316U, // VPSRLVDZrmkz + 811651284U, // VPSRLVDZrr + 87052500U, // VPSRLVDZrrk + 890278100U, // VPSRLVDZrrkz + 811847892U, // VPSRLVDrm + 811651284U, // VPSRLVDrr + 812867693U, // VPSRLVQYrm + 811655277U, // VPSRLVQYrr + 811851885U, // VPSRLVQZ128rm + 358719597U, // VPSRLVQZ128rmb + 1433952365U, // VPSRLVQZ128rmbk + 1165287533U, // VPSRLVQZ128rmbkz + 985112685U, // VPSRLVQZ128rmk + 890577005U, // VPSRLVQZ128rmkz + 811655277U, // VPSRLVQZ128rr + 87056493U, // VPSRLVQZ128rrk + 890282093U, // VPSRLVQZ128rrkz + 812867693U, // VPSRLVQZ256rm + 360816749U, // VPSRLVQZ256rmb + 1436049517U, // VPSRLVQZ256rmbk + 1167384685U, // VPSRLVQZ256rmbkz + 985129069U, // VPSRLVQZ256rmk + 890609773U, // VPSRLVQZ256rmkz + 811655277U, // VPSRLVQZ256rr + 87056493U, // VPSRLVQZ256rrk + 890282093U, // VPSRLVQZ256rrkz + 812884077U, // VPSRLVQZrm + 362913901U, // VPSRLVQZrmb + 1438146669U, // VPSRLVQZrmbk + 1169481837U, // VPSRLVQZrmbkz + 985145453U, // VPSRLVQZrmk + 890675309U, // VPSRLVQZrmkz + 811655277U, // VPSRLVQZrr + 87056493U, // VPSRLVQZrrk + 890282093U, // VPSRLVQZrrkz + 811851885U, // VPSRLVQrm + 811655277U, // VPSRLVQrr + 811855777U, // VPSRLVWZ128rm + 985116577U, // VPSRLVWZ128rmk + 890580897U, // VPSRLVWZ128rmkz + 811659169U, // VPSRLVWZ128rr + 87060385U, // VPSRLVWZ128rrk + 890285985U, // VPSRLVWZ128rrkz + 812871585U, // VPSRLVWZ256rm + 985132961U, // VPSRLVWZ256rmk + 890613665U, // VPSRLVWZ256rmkz + 811659169U, // VPSRLVWZ256rr + 87060385U, // VPSRLVWZ256rrk + 890285985U, // VPSRLVWZ256rrkz + 812887969U, // VPSRLVWZrm + 985149345U, // VPSRLVWZrmk + 890679201U, // VPSRLVWZrmkz + 811659169U, // VPSRLVWZrr + 87060385U, // VPSRLVWZrrk + 890285985U, // VPSRLVWZrrkz + 283438214U, // VPSRLWYri + 811854982U, // VPSRLWYrm + 811658374U, // VPSRLWYrr + 830778502U, // VPSRLWZ128mi + 643050630U, // VPSRLWZ128mik + 593882246U, // VPSRLWZ128mikz + 283438214U, // VPSRLWZ128ri + 1357589638U, // VPSRLWZ128rik + 1088826502U, // VPSRLWZ128rikz + 811854982U, // VPSRLWZ128rm + 985115782U, // VPSRLWZ128rmk + 890580102U, // VPSRLWZ128rmkz + 811658374U, // VPSRLWZ128rr + 87059590U, // VPSRLWZ128rrk + 890285190U, // VPSRLWZ128rrkz + 1009036422U, // VPSRLWZ256mi + 649342086U, // VPSRLWZ256mik + 644213894U, // VPSRLWZ256mikz + 283438214U, // VPSRLWZ256ri + 1357589638U, // VPSRLWZ256rik + 1088826502U, // VPSRLWZ256rikz + 811854982U, // VPSRLWZ256rm + 985115782U, // VPSRLWZ256rmk + 890580102U, // VPSRLWZ256rmkz + 811658374U, // VPSRLWZ256rr + 87059590U, // VPSRLWZ256rrk + 890285190U, // VPSRLWZ256rrkz + 1011133574U, // VPSRLWZmi + 655633542U, // VPSRLWZmik + 650505350U, // VPSRLWZmikz + 283438214U, // VPSRLWZri + 1357589638U, // VPSRLWZrik + 1088826502U, // VPSRLWZrikz + 811854982U, // VPSRLWZrm + 985115782U, // VPSRLWZrmk + 890580102U, // VPSRLWZrmkz + 811658374U, // VPSRLWZrr + 87059590U, // VPSRLWZrrk + 890285190U, // VPSRLWZrrkz + 283438214U, // VPSRLWri + 811854982U, // VPSRLWrm + 811658374U, // VPSRLWrr + 812860345U, // VPSUBBYrm + 811647929U, // VPSUBBYrr + 811844537U, // VPSUBBZ128rm + 985105337U, // VPSUBBZ128rmk + 890569657U, // VPSUBBZ128rmkz + 811647929U, // VPSUBBZ128rr + 87049145U, // VPSUBBZ128rrk + 890274745U, // VPSUBBZ128rrkz + 812860345U, // VPSUBBZ256rm + 985121721U, // VPSUBBZ256rmk + 890602425U, // VPSUBBZ256rmkz + 811647929U, // VPSUBBZ256rr + 87049145U, // VPSUBBZ256rrk + 890274745U, // VPSUBBZ256rrkz + 812876729U, // VPSUBBZrm + 985138105U, // VPSUBBZrmk + 890667961U, // VPSUBBZrmkz + 811647929U, // VPSUBBZrr + 87049145U, // VPSUBBZrrk + 890274745U, // VPSUBBZrrkz + 811844537U, // VPSUBBrm + 811647929U, // VPSUBBrr + 812861319U, // VPSUBDYrm + 811648903U, // VPSUBDYrr + 811845511U, // VPSUBDZ128rm + 360793991U, // VPSUBDZ128rmb + 1436059527U, // VPSUBDZ128rmbk + 1167476615U, // VPSUBDZ128rmbkz + 985106311U, // VPSUBDZ128rmk + 890570631U, // VPSUBDZ128rmkz + 811648903U, // VPSUBDZ128rr + 87050119U, // VPSUBDZ128rrk + 890275719U, // VPSUBDZ128rrkz + 812861319U, // VPSUBDZ256rm + 362891143U, // VPSUBDZ256rmb + 1438156679U, // VPSUBDZ256rmbk + 1169573767U, // VPSUBDZ256rmbkz + 985122695U, // VPSUBDZ256rmk + 890603399U, // VPSUBDZ256rmkz + 811648903U, // VPSUBDZ256rr + 87050119U, // VPSUBDZ256rrk + 890275719U, // VPSUBDZ256rrkz + 812877703U, // VPSUBDZrm + 364988295U, // VPSUBDZrmb + 1440253831U, // VPSUBDZrmbk + 1171670919U, // VPSUBDZrmbkz + 985139079U, // VPSUBDZrmk + 890668935U, // VPSUBDZrmkz + 811648903U, // VPSUBDZrr + 87050119U, // VPSUBDZrrk + 890275719U, // VPSUBDZrrkz + 811845511U, // VPSUBDrm + 811648903U, // VPSUBDrr + 812865959U, // VPSUBQYrm + 811653543U, // VPSUBQYrr + 811850151U, // VPSUBQZ128rm + 358717863U, // VPSUBQZ128rmb + 1433950631U, // VPSUBQZ128rmbk + 1165285799U, // VPSUBQZ128rmbkz + 985110951U, // VPSUBQZ128rmk + 890575271U, // VPSUBQZ128rmkz + 811653543U, // VPSUBQZ128rr + 87054759U, // VPSUBQZ128rrk + 890280359U, // VPSUBQZ128rrkz + 812865959U, // VPSUBQZ256rm + 360815015U, // VPSUBQZ256rmb + 1436047783U, // VPSUBQZ256rmbk + 1167382951U, // VPSUBQZ256rmbkz + 985127335U, // VPSUBQZ256rmk + 890608039U, // VPSUBQZ256rmkz + 811653543U, // VPSUBQZ256rr + 87054759U, // VPSUBQZ256rrk + 890280359U, // VPSUBQZ256rrkz + 812882343U, // VPSUBQZrm + 362912167U, // VPSUBQZrmb + 1438144935U, // VPSUBQZrmbk + 1169480103U, // VPSUBQZrmbkz + 985143719U, // VPSUBQZrmk + 890673575U, // VPSUBQZrmkz + 811653543U, // VPSUBQZrr + 87054759U, // VPSUBQZrrk + 890280359U, // VPSUBQZrrkz + 811850151U, // VPSUBQrm + 811653543U, // VPSUBQrr + 812860849U, // VPSUBSBYrm + 811648433U, // VPSUBSBYrr + 811845041U, // VPSUBSBZ128rm + 985105841U, // VPSUBSBZ128rmk + 890570161U, // VPSUBSBZ128rmkz + 811648433U, // VPSUBSBZ128rr + 87049649U, // VPSUBSBZ128rrk + 890275249U, // VPSUBSBZ128rrkz + 812860849U, // VPSUBSBZ256rm + 985122225U, // VPSUBSBZ256rmk + 890602929U, // VPSUBSBZ256rmkz + 811648433U, // VPSUBSBZ256rr + 87049649U, // VPSUBSBZ256rrk + 890275249U, // VPSUBSBZ256rrkz + 812877233U, // VPSUBSBZrm + 985138609U, // VPSUBSBZrmk + 890668465U, // VPSUBSBZrmkz + 811648433U, // VPSUBSBZrr + 87049649U, // VPSUBSBZrrk + 890275249U, // VPSUBSBZrrkz + 811845041U, // VPSUBSBrm + 811648433U, // VPSUBSBrr + 812871172U, // VPSUBSWYrm + 811658756U, // VPSUBSWYrr + 811855364U, // VPSUBSWZ128rm + 985116164U, // VPSUBSWZ128rmk + 890580484U, // VPSUBSWZ128rmkz + 811658756U, // VPSUBSWZ128rr + 87059972U, // VPSUBSWZ128rrk + 890285572U, // VPSUBSWZ128rrkz + 812871172U, // VPSUBSWZ256rm + 985132548U, // VPSUBSWZ256rmk + 890613252U, // VPSUBSWZ256rmkz + 811658756U, // VPSUBSWZ256rr + 87059972U, // VPSUBSWZ256rrk + 890285572U, // VPSUBSWZ256rrkz + 812887556U, // VPSUBSWZrm + 985148932U, // VPSUBSWZrmk + 890678788U, // VPSUBSWZrmkz + 811658756U, // VPSUBSWZrr + 87059972U, // VPSUBSWZrrk + 890285572U, // VPSUBSWZrrkz + 811855364U, // VPSUBSWrm + 811658756U, // VPSUBSWrr + 812860910U, // VPSUBUSBYrm + 811648494U, // VPSUBUSBYrr + 811845102U, // VPSUBUSBZ128rm + 985105902U, // VPSUBUSBZ128rmk + 890570222U, // VPSUBUSBZ128rmkz + 811648494U, // VPSUBUSBZ128rr + 87049710U, // VPSUBUSBZ128rrk + 890275310U, // VPSUBUSBZ128rrkz + 812860910U, // VPSUBUSBZ256rm + 985122286U, // VPSUBUSBZ256rmk + 890602990U, // VPSUBUSBZ256rmkz + 811648494U, // VPSUBUSBZ256rr + 87049710U, // VPSUBUSBZ256rrk + 890275310U, // VPSUBUSBZ256rrkz + 812877294U, // VPSUBUSBZrm + 985138670U, // VPSUBUSBZrmk + 890668526U, // VPSUBUSBZrmkz + 811648494U, // VPSUBUSBZrr + 87049710U, // VPSUBUSBZrrk + 890275310U, // VPSUBUSBZrrkz + 811845102U, // VPSUBUSBrm + 811648494U, // VPSUBUSBrr + 812871307U, // VPSUBUSWYrm + 811658891U, // VPSUBUSWYrr + 811855499U, // VPSUBUSWZ128rm + 985116299U, // VPSUBUSWZ128rmk + 890580619U, // VPSUBUSWZ128rmkz + 811658891U, // VPSUBUSWZ128rr + 87060107U, // VPSUBUSWZ128rrk + 890285707U, // VPSUBUSWZ128rrkz + 812871307U, // VPSUBUSWZ256rm + 985132683U, // VPSUBUSWZ256rmk + 890613387U, // VPSUBUSWZ256rmkz + 811658891U, // VPSUBUSWZ256rr + 87060107U, // VPSUBUSWZ256rrk + 890285707U, // VPSUBUSWZ256rrkz + 812887691U, // VPSUBUSWZrm + 985149067U, // VPSUBUSWZrmk + 890678923U, // VPSUBUSWZrmkz + 811658891U, // VPSUBUSWZrr + 87060107U, // VPSUBUSWZrrk + 890285707U, // VPSUBUSWZrrkz + 811855499U, // VPSUBUSWrm + 811658891U, // VPSUBUSWrr + 812870347U, // VPSUBWYrm + 811657931U, // VPSUBWYrr + 811854539U, // VPSUBWZ128rm + 985115339U, // VPSUBWZ128rmk + 890579659U, // VPSUBWZ128rmkz + 811657931U, // VPSUBWZ128rr + 87059147U, // VPSUBWZ128rrk + 890284747U, // VPSUBWZ128rrkz + 812870347U, // VPSUBWZ256rm + 985131723U, // VPSUBWZ256rmk + 890612427U, // VPSUBWZ256rmkz + 811657931U, // VPSUBWZ256rr + 87059147U, // VPSUBWZ256rrk + 890284747U, // VPSUBWZ256rrkz + 812886731U, // VPSUBWZrm + 985148107U, // VPSUBWZrmk + 890677963U, // VPSUBWZrmkz + 811657931U, // VPSUBWZrr + 87059147U, // VPSUBWZrrk + 890284747U, // VPSUBWZrrkz + 811854539U, // VPSUBWrm + 811657931U, // VPSUBWrr + 1712588856U, // VPTERNLOGDZ128rmbi + 1710475320U, // VPTERNLOGDZ128rmbik + 1710475320U, // VPTERNLOGDZ128rmbikz + 1179912248U, // VPTERNLOGDZ128rmi + 1983105080U, // VPTERNLOGDZ128rmik + 2519975992U, // VPTERNLOGDZ128rmikz + 1357580344U, // VPTERNLOGDZ128rri + 2163132472U, // VPTERNLOGDZ128rrik + 2163132472U, // VPTERNLOGDZ128rrikz + 2517895224U, // VPTERNLOGDZ256rmbi + 2515781688U, // VPTERNLOGDZ256rmbik + 2515781688U, // VPTERNLOGDZ256rmbikz + 1186203704U, // VPTERNLOGDZ256rmi + 1989396536U, // VPTERNLOGDZ256rmik + 2526267448U, // VPTERNLOGDZ256rmikz + 1357580344U, // VPTERNLOGDZ256rri + 2163132472U, // VPTERNLOGDZ256rrik + 2163132472U, // VPTERNLOGDZ256rrikz + 2786330680U, // VPTERNLOGDZrmbi + 2784217144U, // VPTERNLOGDZrmbik + 2784217144U, // VPTERNLOGDZrmbikz + 1192495160U, // VPTERNLOGDZrmi + 1995687992U, // VPTERNLOGDZrmik + 2532558904U, // VPTERNLOGDZrmikz + 1357580344U, // VPTERNLOGDZrri + 2163132472U, // VPTERNLOGDZrrik + 2163132472U, // VPTERNLOGDZrrikz + 3075742795U, // VPTERNLOGQZ128rmbi + 3073629259U, // VPTERNLOGQZ128rmbik + 3073629259U, // VPTERNLOGQZ128rmbikz + 1179917387U, // VPTERNLOGQZ128rmi + 1983110219U, // VPTERNLOGQZ128rmik + 2519981131U, // VPTERNLOGQZ128rmikz + 1357585483U, // VPTERNLOGQZ128rri + 2163137611U, // VPTERNLOGQZ128rrik + 2163137611U, // VPTERNLOGQZ128rrikz + 1733565515U, // VPTERNLOGQZ256rmbi + 1731451979U, // VPTERNLOGQZ256rmbik + 1731451979U, // VPTERNLOGQZ256rmbikz + 1186208843U, // VPTERNLOGQZ256rmi + 1989401675U, // VPTERNLOGQZ256rmik + 2526272587U, // VPTERNLOGQZ256rmikz + 1357585483U, // VPTERNLOGQZ256rri + 2163137611U, // VPTERNLOGQZ256rrik + 2163137611U, // VPTERNLOGQZ256rrikz + 2538871883U, // VPTERNLOGQZrmbi + 2536758347U, // VPTERNLOGQZrmbik + 2536758347U, // VPTERNLOGQZrmbikz + 1192500299U, // VPTERNLOGQZrmi + 1995693131U, // VPTERNLOGQZrmik + 2532564043U, // VPTERNLOGQZrmikz + 1357585483U, // VPTERNLOGQZrri + 2163137611U, // VPTERNLOGQZrrik + 2163137611U, // VPTERNLOGQZrrikz + 811844804U, // VPTESTMBZ128rm + 890569924U, // VPTESTMBZ128rmk + 811648196U, // VPTESTMBZ128rr + 890275012U, // VPTESTMBZ128rrk + 812860612U, // VPTESTMBZ256rm + 890602692U, // VPTESTMBZ256rmk + 811648196U, // VPTESTMBZ256rr + 890275012U, // VPTESTMBZ256rrk + 812876996U, // VPTESTMBZrm + 890668228U, // VPTESTMBZrmk + 811648196U, // VPTESTMBZrr + 890275012U, // VPTESTMBZrrk + 811845835U, // VPTESTMDZ128rm + 360794315U, // VPTESTMDZ128rmb + 1167476939U, // VPTESTMDZ128rmbk + 890570955U, // VPTESTMDZ128rmk + 811649227U, // VPTESTMDZ128rr + 890276043U, // VPTESTMDZ128rrk + 812861643U, // VPTESTMDZ256rm + 362891467U, // VPTESTMDZ256rmb + 1169574091U, // VPTESTMDZ256rmbk + 890603723U, // VPTESTMDZ256rmk + 811649227U, // VPTESTMDZ256rr + 890276043U, // VPTESTMDZ256rrk + 812878027U, // VPTESTMDZrm + 364988619U, // VPTESTMDZrmb + 1171671243U, // VPTESTMDZrmbk + 890669259U, // VPTESTMDZrmk + 811649227U, // VPTESTMDZrr + 890276043U, // VPTESTMDZrrk + 811851067U, // VPTESTMQZ128rm + 358718779U, // VPTESTMQZ128rmb + 1165286715U, // VPTESTMQZ128rmbk + 890576187U, // VPTESTMQZ128rmk + 811654459U, // VPTESTMQZ128rr + 890281275U, // VPTESTMQZ128rrk + 812866875U, // VPTESTMQZ256rm + 360815931U, // VPTESTMQZ256rmb + 1167383867U, // VPTESTMQZ256rmbk + 890608955U, // VPTESTMQZ256rmk + 811654459U, // VPTESTMQZ256rr + 890281275U, // VPTESTMQZ256rrk + 812883259U, // VPTESTMQZrm + 362913083U, // VPTESTMQZrmb + 1169481019U, // VPTESTMQZrmbk + 890674491U, // VPTESTMQZrmk + 811654459U, // VPTESTMQZrr + 890281275U, // VPTESTMQZrrk + 811855059U, // VPTESTMWZ128rm + 890580179U, // VPTESTMWZ128rmk + 811658451U, // VPTESTMWZ128rr + 890285267U, // VPTESTMWZ128rrk + 812870867U, // VPTESTMWZ256rm + 890612947U, // VPTESTMWZ256rmk + 811658451U, // VPTESTMWZ256rr + 890285267U, // VPTESTMWZ256rrk + 812887251U, // VPTESTMWZrm + 890678483U, // VPTESTMWZrmk + 811658451U, // VPTESTMWZrr + 890285267U, // VPTESTMWZrrk + 811844763U, // VPTESTNMBZ128rm + 890569883U, // VPTESTNMBZ128rmk + 811648155U, // VPTESTNMBZ128rr + 890274971U, // VPTESTNMBZ128rrk + 812860571U, // VPTESTNMBZ256rm + 890602651U, // VPTESTNMBZ256rmk + 811648155U, // VPTESTNMBZ256rr + 890274971U, // VPTESTNMBZ256rrk + 812876955U, // VPTESTNMBZrm + 890668187U, // VPTESTNMBZrmk + 811648155U, // VPTESTNMBZrr + 890274971U, // VPTESTNMBZrrk + 811845808U, // VPTESTNMDZ128rm + 360794288U, // VPTESTNMDZ128rmb + 1167476912U, // VPTESTNMDZ128rmbk + 890570928U, // VPTESTNMDZ128rmk + 811649200U, // VPTESTNMDZ128rr + 890276016U, // VPTESTNMDZ128rrk + 812861616U, // VPTESTNMDZ256rm + 362891440U, // VPTESTNMDZ256rmb + 1169574064U, // VPTESTNMDZ256rmbk + 890603696U, // VPTESTNMDZ256rmk + 811649200U, // VPTESTNMDZ256rr + 890276016U, // VPTESTNMDZ256rrk + 812878000U, // VPTESTNMDZrm + 364988592U, // VPTESTNMDZrmb + 1171671216U, // VPTESTNMDZrmbk + 890669232U, // VPTESTNMDZrmk + 811649200U, // VPTESTNMDZrr + 890276016U, // VPTESTNMDZrrk + 811851040U, // VPTESTNMQZ128rm + 358718752U, // VPTESTNMQZ128rmb + 1165286688U, // VPTESTNMQZ128rmbk + 890576160U, // VPTESTNMQZ128rmk + 811654432U, // VPTESTNMQZ128rr + 890281248U, // VPTESTNMQZ128rrk + 812866848U, // VPTESTNMQZ256rm + 360815904U, // VPTESTNMQZ256rmb + 1167383840U, // VPTESTNMQZ256rmbk + 890608928U, // VPTESTNMQZ256rmk + 811654432U, // VPTESTNMQZ256rr + 890281248U, // VPTESTNMQZ256rrk + 812883232U, // VPTESTNMQZrm + 362913056U, // VPTESTNMQZrmb + 1169480992U, // VPTESTNMQZrmbk + 890674464U, // VPTESTNMQZrmk + 811654432U, // VPTESTNMQZrr + 890281248U, // VPTESTNMQZrrk + 811855032U, // VPTESTNMWZ128rm + 890580152U, // VPTESTNMWZ128rmk + 811658424U, // VPTESTNMWZ128rr + 890285240U, // VPTESTNMWZ128rrk + 812870840U, // VPTESTNMWZ256rm + 890612920U, // VPTESTNMWZ256rmk + 811658424U, // VPTESTNMWZ256rr + 890285240U, // VPTESTNMWZ256rrk + 812887224U, // VPTESTNMWZrm + 890678456U, // VPTESTNMWZrmk + 811658424U, // VPTESTNMWZrr + 890285240U, // VPTESTNMWZrrk + 552954252U, // VPTESTYrm + 551840140U, // VPTESTYrr + 665996U, // VPTESTrm + 551840140U, // VPTESTrr + 812870285U, // VPUNPCKHBWYrm + 811657869U, // VPUNPCKHBWYrr + 811854477U, // VPUNPCKHBWZ128rm + 985115277U, // VPUNPCKHBWZ128rmk + 890579597U, // VPUNPCKHBWZ128rmkz + 811657869U, // VPUNPCKHBWZ128rr + 87059085U, // VPUNPCKHBWZ128rrk + 890284685U, // VPUNPCKHBWZ128rrkz + 812870285U, // VPUNPCKHBWZ256rm + 985131661U, // VPUNPCKHBWZ256rmk + 890612365U, // VPUNPCKHBWZ256rmkz + 811657869U, // VPUNPCKHBWZ256rr + 87059085U, // VPUNPCKHBWZ256rrk + 890284685U, // VPUNPCKHBWZ256rrkz + 812886669U, // VPUNPCKHBWZrm + 985148045U, // VPUNPCKHBWZrmk + 890677901U, // VPUNPCKHBWZrmkz + 811657869U, // VPUNPCKHBWZrr + 87059085U, // VPUNPCKHBWZrrk + 890284685U, // VPUNPCKHBWZrrkz + 811854477U, // VPUNPCKHBWrm + 811657869U, // VPUNPCKHBWrr + 812866169U, // VPUNPCKHDQYrm + 811653753U, // VPUNPCKHDQYrr + 811850361U, // VPUNPCKHDQZ128rm + 360798841U, // VPUNPCKHDQZ128rmb + 1436064377U, // VPUNPCKHDQZ128rmbk + 1167481465U, // VPUNPCKHDQZ128rmbkz + 985111161U, // VPUNPCKHDQZ128rmk + 890575481U, // VPUNPCKHDQZ128rmkz + 811653753U, // VPUNPCKHDQZ128rr + 87054969U, // VPUNPCKHDQZ128rrk + 890280569U, // VPUNPCKHDQZ128rrkz + 812866169U, // VPUNPCKHDQZ256rm + 362895993U, // VPUNPCKHDQZ256rmb + 1438161529U, // VPUNPCKHDQZ256rmbk + 1169578617U, // VPUNPCKHDQZ256rmbkz + 985127545U, // VPUNPCKHDQZ256rmk + 890608249U, // VPUNPCKHDQZ256rmkz + 811653753U, // VPUNPCKHDQZ256rr + 87054969U, // VPUNPCKHDQZ256rrk + 890280569U, // VPUNPCKHDQZ256rrkz + 812882553U, // VPUNPCKHDQZrm + 364993145U, // VPUNPCKHDQZrmb + 1440258681U, // VPUNPCKHDQZrmbk + 1171675769U, // VPUNPCKHDQZrmbkz + 985143929U, // VPUNPCKHDQZrmk + 890673785U, // VPUNPCKHDQZrmkz + 811653753U, // VPUNPCKHDQZrr + 87054969U, // VPUNPCKHDQZrrk + 890280569U, // VPUNPCKHDQZrrkz + 811850361U, // VPUNPCKHDQrm + 811653753U, // VPUNPCKHDQrr + 812866287U, // VPUNPCKHQDQYrm + 811653871U, // VPUNPCKHQDQYrr + 811850479U, // VPUNPCKHQDQZ128rm + 358718191U, // VPUNPCKHQDQZ128rmb + 1433950959U, // VPUNPCKHQDQZ128rmbk + 1165286127U, // VPUNPCKHQDQZ128rmbkz + 985111279U, // VPUNPCKHQDQZ128rmk + 890575599U, // VPUNPCKHQDQZ128rmkz + 811653871U, // VPUNPCKHQDQZ128rr + 87055087U, // VPUNPCKHQDQZ128rrk + 890280687U, // VPUNPCKHQDQZ128rrkz + 812866287U, // VPUNPCKHQDQZ256rm + 360815343U, // VPUNPCKHQDQZ256rmb + 1436048111U, // VPUNPCKHQDQZ256rmbk + 1167383279U, // VPUNPCKHQDQZ256rmbkz + 985127663U, // VPUNPCKHQDQZ256rmk + 890608367U, // VPUNPCKHQDQZ256rmkz + 811653871U, // VPUNPCKHQDQZ256rr + 87055087U, // VPUNPCKHQDQZ256rrk + 890280687U, // VPUNPCKHQDQZ256rrkz + 812882671U, // VPUNPCKHQDQZrm + 362912495U, // VPUNPCKHQDQZrmb + 1438145263U, // VPUNPCKHQDQZrmbk + 1169480431U, // VPUNPCKHQDQZrmbkz + 985144047U, // VPUNPCKHQDQZrmk + 890673903U, // VPUNPCKHQDQZrmkz + 811653871U, // VPUNPCKHQDQZrr + 87055087U, // VPUNPCKHQDQZrrk + 890280687U, // VPUNPCKHQDQZrrkz + 811850479U, // VPUNPCKHQDQrm + 811653871U, // VPUNPCKHQDQrr + 812863767U, // VPUNPCKHWDYrm + 811651351U, // VPUNPCKHWDYrr + 811847959U, // VPUNPCKHWDZ128rm + 985108759U, // VPUNPCKHWDZ128rmk + 890573079U, // VPUNPCKHWDZ128rmkz + 811651351U, // VPUNPCKHWDZ128rr + 87052567U, // VPUNPCKHWDZ128rrk + 890278167U, // VPUNPCKHWDZ128rrkz + 812863767U, // VPUNPCKHWDZ256rm + 985125143U, // VPUNPCKHWDZ256rmk + 890605847U, // VPUNPCKHWDZ256rmkz + 811651351U, // VPUNPCKHWDZ256rr + 87052567U, // VPUNPCKHWDZ256rrk + 890278167U, // VPUNPCKHWDZ256rrkz + 812880151U, // VPUNPCKHWDZrm + 985141527U, // VPUNPCKHWDZrmk + 890671383U, // VPUNPCKHWDZrmkz + 811651351U, // VPUNPCKHWDZrr + 87052567U, // VPUNPCKHWDZrrk + 890278167U, // VPUNPCKHWDZrrkz + 811847959U, // VPUNPCKHWDrm + 811651351U, // VPUNPCKHWDrr + 812870307U, // VPUNPCKLBWYrm + 811657891U, // VPUNPCKLBWYrr + 811854499U, // VPUNPCKLBWZ128rm + 985115299U, // VPUNPCKLBWZ128rmk + 890579619U, // VPUNPCKLBWZ128rmkz + 811657891U, // VPUNPCKLBWZ128rr + 87059107U, // VPUNPCKLBWZ128rrk + 890284707U, // VPUNPCKLBWZ128rrkz + 812870307U, // VPUNPCKLBWZ256rm + 985131683U, // VPUNPCKLBWZ256rmk + 890612387U, // VPUNPCKLBWZ256rmkz + 811657891U, // VPUNPCKLBWZ256rr + 87059107U, // VPUNPCKLBWZ256rrk + 890284707U, // VPUNPCKLBWZ256rrkz + 812886691U, // VPUNPCKLBWZrm + 985148067U, // VPUNPCKLBWZrmk + 890677923U, // VPUNPCKLBWZrmkz + 811657891U, // VPUNPCKLBWZrr + 87059107U, // VPUNPCKLBWZrrk + 890284707U, // VPUNPCKLBWZrrkz + 811854499U, // VPUNPCKLBWrm + 811657891U, // VPUNPCKLBWrr + 812866200U, // VPUNPCKLDQYrm + 811653784U, // VPUNPCKLDQYrr + 811850392U, // VPUNPCKLDQZ128rm + 360798872U, // VPUNPCKLDQZ128rmb + 1436064408U, // VPUNPCKLDQZ128rmbk + 1167481496U, // VPUNPCKLDQZ128rmbkz + 985111192U, // VPUNPCKLDQZ128rmk + 890575512U, // VPUNPCKLDQZ128rmkz + 811653784U, // VPUNPCKLDQZ128rr + 87055000U, // VPUNPCKLDQZ128rrk + 890280600U, // VPUNPCKLDQZ128rrkz + 812866200U, // VPUNPCKLDQZ256rm + 362896024U, // VPUNPCKLDQZ256rmb + 1438161560U, // VPUNPCKLDQZ256rmbk + 1169578648U, // VPUNPCKLDQZ256rmbkz + 985127576U, // VPUNPCKLDQZ256rmk + 890608280U, // VPUNPCKLDQZ256rmkz + 811653784U, // VPUNPCKLDQZ256rr + 87055000U, // VPUNPCKLDQZ256rrk + 890280600U, // VPUNPCKLDQZ256rrkz + 812882584U, // VPUNPCKLDQZrm + 364993176U, // VPUNPCKLDQZrmb + 1440258712U, // VPUNPCKLDQZrmbk + 1171675800U, // VPUNPCKLDQZrmbkz + 985143960U, // VPUNPCKLDQZrmk + 890673816U, // VPUNPCKLDQZrmkz + 811653784U, // VPUNPCKLDQZrr + 87055000U, // VPUNPCKLDQZrrk + 890280600U, // VPUNPCKLDQZrrkz + 811850392U, // VPUNPCKLDQrm + 811653784U, // VPUNPCKLDQrr + 812866300U, // VPUNPCKLQDQYrm + 811653884U, // VPUNPCKLQDQYrr + 811850492U, // VPUNPCKLQDQZ128rm + 358718204U, // VPUNPCKLQDQZ128rmb + 1433950972U, // VPUNPCKLQDQZ128rmbk + 1165286140U, // VPUNPCKLQDQZ128rmbkz + 985111292U, // VPUNPCKLQDQZ128rmk + 890575612U, // VPUNPCKLQDQZ128rmkz + 811653884U, // VPUNPCKLQDQZ128rr + 87055100U, // VPUNPCKLQDQZ128rrk + 890280700U, // VPUNPCKLQDQZ128rrkz + 812866300U, // VPUNPCKLQDQZ256rm + 360815356U, // VPUNPCKLQDQZ256rmb + 1436048124U, // VPUNPCKLQDQZ256rmbk + 1167383292U, // VPUNPCKLQDQZ256rmbkz + 985127676U, // VPUNPCKLQDQZ256rmk + 890608380U, // VPUNPCKLQDQZ256rmkz + 811653884U, // VPUNPCKLQDQZ256rr + 87055100U, // VPUNPCKLQDQZ256rrk + 890280700U, // VPUNPCKLQDQZ256rrkz + 812882684U, // VPUNPCKLQDQZrm + 362912508U, // VPUNPCKLQDQZrmb + 1438145276U, // VPUNPCKLQDQZrmbk + 1169480444U, // VPUNPCKLQDQZrmbkz + 985144060U, // VPUNPCKLQDQZrmk + 890673916U, // VPUNPCKLQDQZrmkz + 811653884U, // VPUNPCKLQDQZrr + 87055100U, // VPUNPCKLQDQZrrk + 890280700U, // VPUNPCKLQDQZrrkz + 811850492U, // VPUNPCKLQDQrm + 811653884U, // VPUNPCKLQDQrr + 812863789U, // VPUNPCKLWDYrm + 811651373U, // VPUNPCKLWDYrr + 811847981U, // VPUNPCKLWDZ128rm + 985108781U, // VPUNPCKLWDZ128rmk + 890573101U, // VPUNPCKLWDZ128rmkz + 811651373U, // VPUNPCKLWDZ128rr + 87052589U, // VPUNPCKLWDZ128rrk + 890278189U, // VPUNPCKLWDZ128rrkz + 812863789U, // VPUNPCKLWDZ256rm + 985125165U, // VPUNPCKLWDZ256rmk + 890605869U, // VPUNPCKLWDZ256rmkz + 811651373U, // VPUNPCKLWDZ256rr + 87052589U, // VPUNPCKLWDZ256rrk + 890278189U, // VPUNPCKLWDZ256rrkz + 812880173U, // VPUNPCKLWDZrm + 985141549U, // VPUNPCKLWDZrmk + 890671405U, // VPUNPCKLWDZrmkz + 811651373U, // VPUNPCKLWDZrr + 87052589U, // VPUNPCKLWDZrrk + 890278189U, // VPUNPCKLWDZrrkz + 811847981U, // VPUNPCKLWDrm + 811651373U, // VPUNPCKLWDrr + 811847112U, // VPXORDZ128rm + 360795592U, // VPXORDZ128rmb + 1436061128U, // VPXORDZ128rmbk + 1167478216U, // VPXORDZ128rmbkz + 985107912U, // VPXORDZ128rmk + 890572232U, // VPXORDZ128rmkz + 811650504U, // VPXORDZ128rr + 87051720U, // VPXORDZ128rrk + 890277320U, // VPXORDZ128rrkz + 812862920U, // VPXORDZ256rm + 362892744U, // VPXORDZ256rmb + 1438158280U, // VPXORDZ256rmbk + 1169575368U, // VPXORDZ256rmbkz + 985124296U, // VPXORDZ256rmk + 890605000U, // VPXORDZ256rmkz + 811650504U, // VPXORDZ256rr + 87051720U, // VPXORDZ256rrk + 890277320U, // VPXORDZ256rrkz + 812879304U, // VPXORDZrm + 364989896U, // VPXORDZrmb + 1440255432U, // VPXORDZrmbk + 1171672520U, // VPXORDZrmbkz + 985140680U, // VPXORDZrmk + 890670536U, // VPXORDZrmkz + 811650504U, // VPXORDZrr + 87051720U, // VPXORDZrrk + 890277320U, // VPXORDZrrkz + 811851380U, // VPXORQZ128rm + 358719092U, // VPXORQZ128rmb + 1433951860U, // VPXORQZ128rmbk + 1165287028U, // VPXORQZ128rmbkz + 985112180U, // VPXORQZ128rmk + 890576500U, // VPXORQZ128rmkz + 811654772U, // VPXORQZ128rr + 87055988U, // VPXORQZ128rrk + 890281588U, // VPXORQZ128rrkz + 812867188U, // VPXORQZ256rm + 360816244U, // VPXORQZ256rmb + 1436049012U, // VPXORQZ256rmbk + 1167384180U, // VPXORQZ256rmbkz + 985128564U, // VPXORQZ256rmk + 890609268U, // VPXORQZ256rmkz + 811654772U, // VPXORQZ256rr + 87055988U, // VPXORQZ256rrk + 890281588U, // VPXORQZ256rrkz + 812883572U, // VPXORQZrm + 362913396U, // VPXORQZrmb + 1438146164U, // VPXORQZrmbk + 1169481332U, // VPXORQZrmbkz + 985144948U, // VPXORQZrmk + 890674804U, // VPXORQZrmkz + 811654772U, // VPXORQZrr + 87055988U, // VPXORQZrrk + 890281588U, // VPXORQZrrkz + 812867912U, // VPXORYrm + 811655496U, // VPXORYrr + 811852104U, // VPXORrm + 811655496U, // VPXORrr + 2999307181U, // VRANGEPDZ128rmbi + 3111373741U, // VRANGEPDZ128rmbik + 3079932845U, // VRANGEPDZ128rmbikz + 300272557U, // VRANGEPDZ128rmi + 2039729069U, // VRANGEPDZ128rmik + 1202981805U, // VRANGEPDZ128rmikz + 1088818093U, // VRANGEPDZ128rri + 2163133357U, // VRANGEPDZ128rrik + 1357581229U, // VRANGEPDZ128rrikz + 1657129901U, // VRANGEPDZ256rmbi + 1769196461U, // VRANGEPDZ256rmbik + 1737755565U, // VRANGEPDZ256rmbikz + 392547245U, // VRANGEPDZ256rmi + 2041826221U, // VRANGEPDZ256rmik + 1205078957U, // VRANGEPDZ256rmikz + 1088818093U, // VRANGEPDZ256rri + 2163133357U, // VRANGEPDZ256rrik + 1357581229U, // VRANGEPDZ256rrikz + 2462436269U, // VRANGEPDZrmbi + 2574502829U, // VRANGEPDZrmbik + 2543061933U, // VRANGEPDZrmbikz + 400935853U, // VRANGEPDZrmi + 2043923373U, // VRANGEPDZrmik + 1209273261U, // VRANGEPDZrmikz + 1088818093U, // VRANGEPDZrri + 1212550061U, // VRANGEPDZrrib + 2286865325U, // VRANGEPDZrribk + 1481313197U, // VRANGEPDZrribkz + 2163133357U, // VRANGEPDZrrik + 1357581229U, // VRANGEPDZrrikz + 1661330625U, // VRANGEPSZ128rmbi + 1777591489U, // VRANGEPSZ128rmbik + 1752442049U, // VRANGEPSZ128rmbikz + 300278977U, // VRANGEPSZ128rmi + 2039735489U, // VRANGEPSZ128rmik + 1202988225U, // VRANGEPSZ128rmikz + 1088824513U, // VRANGEPSZ128rri + 2163139777U, // VRANGEPSZ128rrik + 1357587649U, // VRANGEPSZ128rrikz + 2466636993U, // VRANGEPSZ256rmbi + 2582897857U, // VRANGEPSZ256rmbik + 2557748417U, // VRANGEPSZ256rmbikz + 392553665U, // VRANGEPSZ256rmi + 2041832641U, // VRANGEPSZ256rmik + 1205085377U, // VRANGEPSZ256rmikz + 1088824513U, // VRANGEPSZ256rri + 2163139777U, // VRANGEPSZ256rrik + 1357587649U, // VRANGEPSZ256rrikz + 2735072449U, // VRANGEPSZrmbi + 2851333313U, // VRANGEPSZrmbik + 2826183873U, // VRANGEPSZrmbikz + 400942273U, // VRANGEPSZrmi + 2043929793U, // VRANGEPSZrmik + 1209279681U, // VRANGEPSZrmikz + 1088824513U, // VRANGEPSZrri + 1212556481U, // VRANGEPSZrrib + 2286871745U, // VRANGEPSZrribk + 1481319617U, // VRANGEPSZrribkz + 2163139777U, // VRANGEPSZrrik + 1357587649U, // VRANGEPSZrrikz + 851824412U, // VRANGESDZrmi + 963890972U, // VRANGESDZrmik + 932450076U, // VRANGESDZrmikz + 1088818972U, // VRANGESDZrri + 1212550940U, // VRANGESDZrrib + 2286866204U, // VRANGESDZrribk + 1481314076U, // VRANGESDZrribkz + 2163134236U, // VRANGESDZrrik + 1357582108U, // VRANGESDZrrikz + 856025134U, // VRANGESSZrmi + 972285998U, // VRANGESSZrmik + 947136558U, // VRANGESSZrmikz + 1088825390U, // VRANGESSZrri + 1212557358U, // VRANGESSZrrib + 2286872622U, // VRANGESSZrribk + 1481320494U, // VRANGESSZrribkz + 2163140654U, // VRANGESSZrrik + 1357588526U, // VRANGESSZrrikz + 658038U, // VRCP14PDZ128m + 627673718U, // VRCP14PDZ128mb + 628099702U, // VRCP14PDZ128mbk + 627198582U, // VRCP14PDZ128mbkz + 3230599798U, // VRCP14PDZ128mk + 3229747830U, // VRCP14PDZ128mkz + 551832182U, // VRCP14PDZ128r + 3230698102U, // VRCP14PDZ128rk + 3229665910U, // VRCP14PDZ128rkz + 1346166U, // VRCP14PDZ256m + 629770870U, // VRCP14PDZ256mb + 630196854U, // VRCP14PDZ256mbk + 629295734U, // VRCP14PDZ256mbkz + 3230730870U, // VRCP14PDZ256mk + 3230632566U, // VRCP14PDZ256mkz + 551832182U, // VRCP14PDZ256r + 3230698102U, // VRCP14PDZ256rk + 3229665910U, // VRCP14PDZ256rkz + 1510006U, // VRCP14PDZm + 631868022U, // VRCP14PDZmb + 632294006U, // VRCP14PDZmbk + 631392886U, // VRCP14PDZmbkz + 3230780022U, // VRCP14PDZmk + 3230747254U, // VRCP14PDZmkz + 551832182U, // VRCP14PDZr + 3230698102U, // VRCP14PDZrk + 3229665910U, // VRCP14PDZrkz + 664443U, // VRCP14PSZ128m + 629793659U, // VRCP14PSZ128mb + 630399867U, // VRCP14PSZ128mbk + 629318523U, // VRCP14PSZ128mbkz + 3230606203U, // VRCP14PSZ128mk + 3229754235U, // VRCP14PSZ128mkz + 551838587U, // VRCP14PSZ128r + 3230704507U, // VRCP14PSZ128rk + 3229672315U, // VRCP14PSZ128rkz + 1352571U, // VRCP14PSZ256m + 631890811U, // VRCP14PSZ256mb + 632497019U, // VRCP14PSZ256mbk + 631415675U, // VRCP14PSZ256mbkz + 3230737275U, // VRCP14PSZ256mk + 3230638971U, // VRCP14PSZ256mkz + 551838587U, // VRCP14PSZ256r + 3230704507U, // VRCP14PSZ256rk + 3229672315U, // VRCP14PSZ256rkz + 1516411U, // VRCP14PSZm + 633987963U, // VRCP14PSZmb + 634594171U, // VRCP14PSZmbk + 633512827U, // VRCP14PSZmbkz + 3230786427U, // VRCP14PSZmk + 3230753659U, // VRCP14PSZmkz + 551838587U, // VRCP14PSZr + 3230704507U, // VRCP14PSZrk + 3229672315U, // VRCP14PSZrkz + 283266713U, // VRCP14SDZrm + 1357893273U, // VRCP14SDZrmk + 1089474201U, // VRCP14SDZrmkz + 811650713U, // VRCP14SDZrr + 87051929U, // VRCP14SDZrrk + 890277529U, // VRCP14SDZrrkz + 283289500U, // VRCP14SSZrm + 1358096284U, // VRCP14SSZrmk + 1089677212U, // VRCP14SSZrmkz + 811657116U, // VRCP14SSZrr + 87058332U, // VRCP14SSZrrk + 890283932U, // VRCP14SSZrrkz + 1510028U, // VRCP28PDZm + 631868044U, // VRCP28PDZmb + 632294028U, // VRCP28PDZmbk + 631392908U, // VRCP28PDZmbkz + 3230780044U, // VRCP28PDZmk + 3230747276U, // VRCP28PDZmkz + 551832204U, // VRCP28PDZr + 551843284U, // VRCP28PDZrb + 3230709204U, // VRCP28PDZrbk + 3229677012U, // VRCP28PDZrbkz + 3230698124U, // VRCP28PDZrk + 3229665932U, // VRCP28PDZrkz + 1516433U, // VRCP28PSZm + 633987985U, // VRCP28PSZmb + 634594193U, // VRCP28PSZmbk + 633512849U, // VRCP28PSZmbkz + 3230786449U, // VRCP28PSZmk + 3230753681U, // VRCP28PSZmkz + 551838609U, // VRCP28PSZr + 551843771U, // VRCP28PSZrb + 3230709691U, // VRCP28PSZrbk + 3229677499U, // VRCP28PSZrbkz + 3230704529U, // VRCP28PSZrk + 3229672337U, // VRCP28PSZrkz + 283266735U, // VRCP28SDZm + 1357893295U, // VRCP28SDZmk + 1089474223U, // VRCP28SDZmkz + 811650735U, // VRCP28SDZr + 811660858U, // VRCP28SDZrb + 87062074U, // VRCP28SDZrbk + 890287674U, // VRCP28SDZrbkz + 87051951U, // VRCP28SDZrk + 890277551U, // VRCP28SDZrkz + 283289522U, // VRCP28SSZm + 1358096306U, // VRCP28SSZmk + 1089677234U, // VRCP28SSZmkz + 811657138U, // VRCP28SSZr + 811661327U, // VRCP28SSZrb + 87062543U, // VRCP28SSZrbk + 890288143U, // VRCP28SSZrbkz + 87058354U, // VRCP28SSZrk + 890283954U, // VRCP28SSZrkz + 1353097U, // VRCPPSYm + 551839113U, // VRCPPSYr + 664969U, // VRCPPSm + 551839113U, // VRCPPSr + 283289728U, // VRCPSSm + 283289728U, // VRCPSSm_Int + 811657344U, // VRCPSSr + 811657344U, // VRCPSSr_Int + 3032779682U, // VREDUCEPDZ128rmbi + 3079932834U, // VREDUCEPDZ128rmbik + 2999307170U, // VREDUCEPDZ128rmbikz + 77892514U, // VREDUCEPDZ128rmi + 666110882U, // VREDUCEPDZ128rmik + 568708002U, // VREDUCEPDZ128rmikz + 283429794U, // VREDUCEPDZ128rri + 1357581218U, // VREDUCEPDZ128rrik + 1088818082U, // VREDUCEPDZ128rrikz + 1690602402U, // VREDUCEPDZ256rmbi + 1737755554U, // VREDUCEPDZ256rmbik + 1657129890U, // VREDUCEPDZ256rmbikz + 168070050U, // VREDUCEPDZ256rmi + 668208034U, // VREDUCEPDZ256rmik + 660982690U, // VREDUCEPDZ256rmikz + 283429794U, // VREDUCEPDZ256rri + 1357581218U, // VREDUCEPDZ256rrik + 1088818082U, // VREDUCEPDZ256rrikz + 2495908770U, // VREDUCEPDZrmbi + 2543061922U, // VREDUCEPDZrmbik + 2462436258U, // VREDUCEPDZrmbikz + 170167202U, // VREDUCEPDZrmi + 672402338U, // VREDUCEPDZrmik + 669371298U, // VREDUCEPDZrmikz + 283429794U, // VREDUCEPDZrri + 407161762U, // VREDUCEPDZrrib + 1481313186U, // VREDUCEPDZrribk + 1212550050U, // VREDUCEPDZrribkz + 1357581218U, // VREDUCEPDZrrik + 1088818082U, // VREDUCEPDZrrikz + 1692705974U, // VREDUCEPSZ128rmbi + 1752442038U, // VREDUCEPSZ128rmbik + 1661330614U, // VREDUCEPSZ128rmbikz + 77898934U, // VREDUCEPSZ128rmi + 666117302U, // VREDUCEPSZ128rmik + 568714422U, // VREDUCEPSZ128rmikz + 283436214U, // VREDUCEPSZ128rri + 1357587638U, // VREDUCEPSZ128rrik + 1088824502U, // VREDUCEPSZ128rrikz + 2498012342U, // VREDUCEPSZ256rmbi + 2557748406U, // VREDUCEPSZ256rmbik + 2466636982U, // VREDUCEPSZ256rmbikz + 168076470U, // VREDUCEPSZ256rmi + 668214454U, // VREDUCEPSZ256rmik + 660989110U, // VREDUCEPSZ256rmikz + 283436214U, // VREDUCEPSZ256rri + 1357587638U, // VREDUCEPSZ256rrik + 1088824502U, // VREDUCEPSZ256rrikz + 2766447798U, // VREDUCEPSZrmbi + 2826183862U, // VREDUCEPSZrmbik + 2735072438U, // VREDUCEPSZrmbikz + 170173622U, // VREDUCEPSZrmi + 672408758U, // VREDUCEPSZrmik + 669377718U, // VREDUCEPSZrmikz + 283436214U, // VREDUCEPSZrri + 407168182U, // VREDUCEPSZrrib + 1481319606U, // VREDUCEPSZrribk + 1212556470U, // VREDUCEPSZrribkz + 1357587638U, // VREDUCEPSZrrik + 1088824502U, // VREDUCEPSZrrikz + 851824401U, // VREDUCESDZrmi + 963890961U, // VREDUCESDZrmik + 932450065U, // VREDUCESDZrmikz + 1088818961U, // VREDUCESDZrri + 1212550929U, // VREDUCESDZrrib + 2286866193U, // VREDUCESDZrribk + 1481314065U, // VREDUCESDZrribkz + 2163134225U, // VREDUCESDZrrik + 1357582097U, // VREDUCESDZrrikz + 856025123U, // VREDUCESSZrmi + 972285987U, // VREDUCESSZrmik + 947136547U, // VREDUCESSZrmikz + 1088825379U, // VREDUCESSZrri + 1212557347U, // VREDUCESSZrrib + 2286872611U, // VREDUCESSZrribk + 1481320483U, // VREDUCESSZrribkz + 2163140643U, // VREDUCESSZrrik + 1357588515U, // VREDUCESSZrrikz + 3032779703U, // VRNDSCALEPDZ128rmbi + 3079932855U, // VRNDSCALEPDZ128rmbik + 2999307191U, // VRNDSCALEPDZ128rmbikz + 77892535U, // VRNDSCALEPDZ128rmi + 666110903U, // VRNDSCALEPDZ128rmik + 568708023U, // VRNDSCALEPDZ128rmikz + 283429815U, // VRNDSCALEPDZ128rri + 1357581239U, // VRNDSCALEPDZ128rrik + 1088818103U, // VRNDSCALEPDZ128rrikz + 1690602423U, // VRNDSCALEPDZ256rmbi + 1737755575U, // VRNDSCALEPDZ256rmbik + 1657129911U, // VRNDSCALEPDZ256rmbikz + 168070071U, // VRNDSCALEPDZ256rmi + 668208055U, // VRNDSCALEPDZ256rmik + 660982711U, // VRNDSCALEPDZ256rmikz + 283429815U, // VRNDSCALEPDZ256rri + 1357581239U, // VRNDSCALEPDZ256rrik + 1088818103U, // VRNDSCALEPDZ256rrikz + 2495908791U, // VRNDSCALEPDZrmbi + 2543061943U, // VRNDSCALEPDZrmbik + 2462436279U, // VRNDSCALEPDZrmbikz + 170167223U, // VRNDSCALEPDZrmi + 672402359U, // VRNDSCALEPDZrmik + 669371319U, // VRNDSCALEPDZrmikz + 283429815U, // VRNDSCALEPDZrri + 407161783U, // VRNDSCALEPDZrrib + 1481313207U, // VRNDSCALEPDZrribk + 1212550071U, // VRNDSCALEPDZrribkz + 1357581239U, // VRNDSCALEPDZrrik + 1088818103U, // VRNDSCALEPDZrrikz + 1692705995U, // VRNDSCALEPSZ128rmbi + 1752442059U, // VRNDSCALEPSZ128rmbik + 1661330635U, // VRNDSCALEPSZ128rmbikz + 77898955U, // VRNDSCALEPSZ128rmi + 666117323U, // VRNDSCALEPSZ128rmik + 568714443U, // VRNDSCALEPSZ128rmikz + 283436235U, // VRNDSCALEPSZ128rri + 1357587659U, // VRNDSCALEPSZ128rrik + 1088824523U, // VRNDSCALEPSZ128rrikz + 2498012363U, // VRNDSCALEPSZ256rmbi + 2557748427U, // VRNDSCALEPSZ256rmbik + 2466637003U, // VRNDSCALEPSZ256rmbikz + 168076491U, // VRNDSCALEPSZ256rmi + 668214475U, // VRNDSCALEPSZ256rmik + 660989131U, // VRNDSCALEPSZ256rmikz + 283436235U, // VRNDSCALEPSZ256rri + 1357587659U, // VRNDSCALEPSZ256rrik + 1088824523U, // VRNDSCALEPSZ256rrikz + 2766447819U, // VRNDSCALEPSZrmbi + 2826183883U, // VRNDSCALEPSZrmbik + 2735072459U, // VRNDSCALEPSZrmbikz + 170173643U, // VRNDSCALEPSZrmi + 672408779U, // VRNDSCALEPSZrmik + 669377739U, // VRNDSCALEPSZrmikz + 283436235U, // VRNDSCALEPSZrri + 407168203U, // VRNDSCALEPSZrrib + 1481319627U, // VRNDSCALEPSZrribk + 1212556491U, // VRNDSCALEPSZrribkz + 1357587659U, // VRNDSCALEPSZrrik + 1088824523U, // VRNDSCALEPSZrrikz + 851824422U, // VRNDSCALESDZm + 851824422U, // VRNDSCALESDZm_Int + 963890982U, // VRNDSCALESDZm_Intk + 932450086U, // VRNDSCALESDZm_Intkz + 1088818982U, // VRNDSCALESDZr + 1088818982U, // VRNDSCALESDZr_Int + 2163134246U, // VRNDSCALESDZr_Intk + 1357582118U, // VRNDSCALESDZr_Intkz + 1212550950U, // VRNDSCALESDZrb_Int + 2286866214U, // VRNDSCALESDZrb_Intk + 1481314086U, // VRNDSCALESDZrb_Intkz + 856025144U, // VRNDSCALESSZm + 856025144U, // VRNDSCALESSZm_Int + 972286008U, // VRNDSCALESSZm_Intk + 947136568U, // VRNDSCALESSZm_Intkz + 1088825400U, // VRNDSCALESSZr + 1088825400U, // VRNDSCALESSZr_Int + 2163140664U, // VRNDSCALESSZr_Intk + 1357588536U, // VRNDSCALESSZr_Intkz + 1212557368U, // VRNDSCALESSZrb_Int + 2286872632U, // VRNDSCALESSZrb_Intk + 1481320504U, // VRNDSCALESSZrb_Intkz + 168070015U, // VROUNDPDYm + 283429759U, // VROUNDPDYr + 77892479U, // VROUNDPDm + 283429759U, // VROUNDPDr + 168076435U, // VROUNDPSYm + 283436179U, // VROUNDPSYr + 77898899U, // VROUNDPSm + 283436179U, // VROUNDPSr + 851824391U, // VROUNDSDm + 851824391U, // VROUNDSDm_Int + 1088818951U, // VROUNDSDr + 1088818951U, // VROUNDSDr_Int + 856025113U, // VROUNDSSm + 856025113U, // VROUNDSSm_Int + 1088825369U, // VROUNDSSr + 1088825369U, // VROUNDSSr_Int + 658048U, // VRSQRT14PDZ128m + 627673728U, // VRSQRT14PDZ128mb + 628099712U, // VRSQRT14PDZ128mbk + 627198592U, // VRSQRT14PDZ128mbkz + 3230599808U, // VRSQRT14PDZ128mk + 3229747840U, // VRSQRT14PDZ128mkz + 551832192U, // VRSQRT14PDZ128r + 3230698112U, // VRSQRT14PDZ128rk + 3229665920U, // VRSQRT14PDZ128rkz + 1346176U, // VRSQRT14PDZ256m + 629770880U, // VRSQRT14PDZ256mb + 630196864U, // VRSQRT14PDZ256mbk + 629295744U, // VRSQRT14PDZ256mbkz + 3230730880U, // VRSQRT14PDZ256mk + 3230632576U, // VRSQRT14PDZ256mkz + 551832192U, // VRSQRT14PDZ256r + 3230698112U, // VRSQRT14PDZ256rk + 3229665920U, // VRSQRT14PDZ256rkz + 1510016U, // VRSQRT14PDZm + 631868032U, // VRSQRT14PDZmb + 632294016U, // VRSQRT14PDZmbk + 631392896U, // VRSQRT14PDZmbkz + 3230780032U, // VRSQRT14PDZmk + 3230747264U, // VRSQRT14PDZmkz + 551832192U, // VRSQRT14PDZr + 3230698112U, // VRSQRT14PDZrk + 3229665920U, // VRSQRT14PDZrkz + 664453U, // VRSQRT14PSZ128m + 629793669U, // VRSQRT14PSZ128mb + 630399877U, // VRSQRT14PSZ128mbk + 629318533U, // VRSQRT14PSZ128mbkz + 3230606213U, // VRSQRT14PSZ128mk + 3229754245U, // VRSQRT14PSZ128mkz + 551838597U, // VRSQRT14PSZ128r + 3230704517U, // VRSQRT14PSZ128rk + 3229672325U, // VRSQRT14PSZ128rkz + 1352581U, // VRSQRT14PSZ256m + 631890821U, // VRSQRT14PSZ256mb + 632497029U, // VRSQRT14PSZ256mbk + 631415685U, // VRSQRT14PSZ256mbkz + 3230737285U, // VRSQRT14PSZ256mk + 3230638981U, // VRSQRT14PSZ256mkz + 551838597U, // VRSQRT14PSZ256r + 3230704517U, // VRSQRT14PSZ256rk + 3229672325U, // VRSQRT14PSZ256rkz + 1516421U, // VRSQRT14PSZm + 633987973U, // VRSQRT14PSZmb + 634594181U, // VRSQRT14PSZmbk + 633512837U, // VRSQRT14PSZmbkz + 3230786437U, // VRSQRT14PSZmk + 3230753669U, // VRSQRT14PSZmkz + 551838597U, // VRSQRT14PSZr + 3230704517U, // VRSQRT14PSZrk + 3229672325U, // VRSQRT14PSZrkz + 283266723U, // VRSQRT14SDZrm + 1357893283U, // VRSQRT14SDZrmk + 1089474211U, // VRSQRT14SDZrmkz + 811650723U, // VRSQRT14SDZrr + 87051939U, // VRSQRT14SDZrrk + 890277539U, // VRSQRT14SDZrrkz + 283289510U, // VRSQRT14SSZrm + 1358096294U, // VRSQRT14SSZrmk + 1089677222U, // VRSQRT14SSZrmkz + 811657126U, // VRSQRT14SSZrr + 87058342U, // VRSQRT14SSZrrk + 890283942U, // VRSQRT14SSZrrkz + 1510038U, // VRSQRT28PDZm + 631868054U, // VRSQRT28PDZmb + 632294038U, // VRSQRT28PDZmbk + 631392918U, // VRSQRT28PDZmbkz + 3230780054U, // VRSQRT28PDZmk + 3230747286U, // VRSQRT28PDZmkz + 551832214U, // VRSQRT28PDZr + 551843301U, // VRSQRT28PDZrb + 3230709221U, // VRSQRT28PDZrbk + 3229677029U, // VRSQRT28PDZrbkz + 3230698134U, // VRSQRT28PDZrk + 3229665942U, // VRSQRT28PDZrkz + 1516443U, // VRSQRT28PSZm + 633987995U, // VRSQRT28PSZmb + 634594203U, // VRSQRT28PSZmbk + 633512859U, // VRSQRT28PSZmbkz + 3230786459U, // VRSQRT28PSZmk + 3230753691U, // VRSQRT28PSZmkz + 551838619U, // VRSQRT28PSZr + 551843788U, // VRSQRT28PSZrb + 3230709708U, // VRSQRT28PSZrbk + 3229677516U, // VRSQRT28PSZrbkz + 3230704539U, // VRSQRT28PSZrk + 3229672347U, // VRSQRT28PSZrkz + 283266745U, // VRSQRT28SDZm + 1357893305U, // VRSQRT28SDZmk + 1089474233U, // VRSQRT28SDZmkz + 811650745U, // VRSQRT28SDZr + 811660875U, // VRSQRT28SDZrb + 87062091U, // VRSQRT28SDZrbk + 890287691U, // VRSQRT28SDZrbkz + 87051961U, // VRSQRT28SDZrk + 890277561U, // VRSQRT28SDZrkz + 283289532U, // VRSQRT28SSZm + 1358096316U, // VRSQRT28SSZmk + 1089677244U, // VRSQRT28SSZmkz + 811657148U, // VRSQRT28SSZr + 811661344U, // VRSQRT28SSZrb + 87062560U, // VRSQRT28SSZrbk + 890288160U, // VRSQRT28SSZrbkz + 87058364U, // VRSQRT28SSZrk + 890283964U, // VRSQRT28SSZrkz + 1353303U, // VRSQRTPSYm + 551839319U, // VRSQRTPSYr + 665175U, // VRSQRTPSm + 551839319U, // VRSQRTPSr + 283289788U, // VRSQRTSSm + 283289788U, // VRSQRTSSm_Int + 811657404U, // VRSQRTSSr + 811657404U, // VRSQRTSSr_Int + 811731908U, // VSCALEFPDZ128rm + 358763460U, // VSCALEFPDZ128rmb + 1433390020U, // VSCALEFPDZ128rmbk + 1164970948U, // VSCALEFPDZ128rmbkz + 86985668U, // VSCALEFPDZ128rmk + 890178500U, // VSCALEFPDZ128rmkz + 811649988U, // VSCALEFPDZ128rr + 87051204U, // VSCALEFPDZ128rrk + 890276804U, // VSCALEFPDZ128rrkz + 812616644U, // VSCALEFPDZ256rm + 360860612U, // VSCALEFPDZ256rmb + 1435487172U, // VSCALEFPDZ256rmbk + 1167068100U, // VSCALEFPDZ256rmbkz + 87083972U, // VSCALEFPDZ256rmk + 890309572U, // VSCALEFPDZ256rmkz + 811649988U, // VSCALEFPDZ256rr + 87051204U, // VSCALEFPDZ256rrk + 890276804U, // VSCALEFPDZ256rrkz + 812731332U, // VSCALEFPDZrm + 362957764U, // VSCALEFPDZrmb + 1437584324U, // VSCALEFPDZrmbk + 1169165252U, // VSCALEFPDZrmbkz + 87133124U, // VSCALEFPDZrmk + 890358724U, // VSCALEFPDZrmkz + 811649988U, // VSCALEFPDZrr + 812780484U, // VSCALEFPDZrrb + 87182276U, // VSCALEFPDZrrbk + 890407876U, // VSCALEFPDZrrbkz + 87051204U, // VSCALEFPDZrrk + 890276804U, // VSCALEFPDZrrkz + 811738328U, // VSCALEFPSZ128rm + 360883416U, // VSCALEFPSZ128rmb + 1435690200U, // VSCALEFPSZ128rmbk + 1167271128U, // VSCALEFPSZ128rmbkz + 86992088U, // VSCALEFPSZ128rmk + 890184920U, // VSCALEFPSZ128rmkz + 811656408U, // VSCALEFPSZ128rr + 87057624U, // VSCALEFPSZ128rrk + 890283224U, // VSCALEFPSZ128rrkz + 812623064U, // VSCALEFPSZ256rm + 362980568U, // VSCALEFPSZ256rmb + 1437787352U, // VSCALEFPSZ256rmbk + 1169368280U, // VSCALEFPSZ256rmbkz + 87090392U, // VSCALEFPSZ256rmk + 890315992U, // VSCALEFPSZ256rmkz + 811656408U, // VSCALEFPSZ256rr + 87057624U, // VSCALEFPSZ256rrk + 890283224U, // VSCALEFPSZ256rrkz + 812737752U, // VSCALEFPSZrm + 365077720U, // VSCALEFPSZrmb + 1439884504U, // VSCALEFPSZrmbk + 1171465432U, // VSCALEFPSZrmbkz + 87139544U, // VSCALEFPSZrmk + 890365144U, // VSCALEFPSZrmkz + 811656408U, // VSCALEFPSZrr + 812786904U, // VSCALEFPSZrrb + 87188696U, // VSCALEFPSZrrbk + 890414296U, // VSCALEFPSZrrbkz + 87057624U, // VSCALEFPSZrrk + 890283224U, // VSCALEFPSZrrkz + 283266867U, // VSCALEFSDZrm + 1357893427U, // VSCALEFSDZrmk + 1089474355U, // VSCALEFSDZrmkz + 811650867U, // VSCALEFSDZrr + 812781363U, // VSCALEFSDZrrb_Int + 87183155U, // VSCALEFSDZrrb_Intk + 890408755U, // VSCALEFSDZrrb_Intkz + 87052083U, // VSCALEFSDZrrk + 890277683U, // VSCALEFSDZrrkz + 283289669U, // VSCALEFSSZrm + 1358096453U, // VSCALEFSSZrmk + 1089677381U, // VSCALEFSSZrmkz + 811657285U, // VSCALEFSSZrr + 812787781U, // VSCALEFSSZrrb_Int + 87189573U, // VSCALEFSSZrrb_Intk + 890415173U, // VSCALEFSSZrrb_Intkz + 87058501U, // VSCALEFSSZrrk + 890284101U, // VSCALEFSSZrrkz + 3247721365U, // VSCATTERDPDZ128mr + 3425979285U, // VSCATTERDPDZ256mr + 3428076437U, // VSCATTERDPDZmr + 3247727785U, // VSCATTERDPSZ128mr + 3425985705U, // VSCATTERDPSZ256mr + 3428082857U, // VSCATTERDPSZmr + 172854016U, // VSCATTERPF0DPDm + 172860413U, // VSCATTERPF0DPSm + 172854401U, // VSCATTERPF0QPDm + 173368762U, // VSCATTERPF0QPSm + 172854047U, // VSCATTERPF1DPDm + 172860444U, // VSCATTERPF1DPSm + 172854432U, // VSCATTERPF1QPDm + 173368793U, // VSCATTERPF1QPSm + 3247721660U, // VSCATTERQPDZ128mr + 3425979580U, // VSCATTERQPDZ256mr + 3428076732U, // VSCATTERQPDZmr + 3251922421U, // VSCATTERQPSZ128mr + 3247728117U, // VSCATTERQPSZ256mr + 3425986037U, // VSCATTERQPSZmr + 2466627977U, // VSHUFF32X4Z256rmbi + 2582888841U, // VSHUFF32X4Z256rmbik + 2557739401U, // VSHUFF32X4Z256rmbikz + 392544649U, // VSHUFF32X4Z256rmi + 2041823625U, // VSHUFF32X4Z256rmik + 1205076361U, // VSHUFF32X4Z256rmikz + 1088815497U, // VSHUFF32X4Z256rri + 2163130761U, // VSHUFF32X4Z256rrik + 1357578633U, // VSHUFF32X4Z256rrikz + 2735063433U, // VSHUFF32X4Zrmbi + 2851324297U, // VSHUFF32X4Zrmbik + 2826174857U, // VSHUFF32X4Zrmbikz + 400933257U, // VSHUFF32X4Zrmi + 2043920777U, // VSHUFF32X4Zrmik + 1209270665U, // VSHUFF32X4Zrmikz + 1088815497U, // VSHUFF32X4Zrri + 2163130761U, // VSHUFF32X4Zrrik + 1357578633U, // VSHUFF32X4Zrrikz + 1657127092U, // VSHUFF64X2Z256rmbi + 1769193652U, // VSHUFF64X2Z256rmbik + 1737752756U, // VSHUFF64X2Z256rmbikz + 392544436U, // VSHUFF64X2Z256rmi + 2041823412U, // VSHUFF64X2Z256rmik + 1205076148U, // VSHUFF64X2Z256rmikz + 1088815284U, // VSHUFF64X2Z256rri + 2163130548U, // VSHUFF64X2Z256rrik + 1357578420U, // VSHUFF64X2Z256rrikz + 2462433460U, // VSHUFF64X2Zrmbi + 2574500020U, // VSHUFF64X2Zrmbik + 2543059124U, // VSHUFF64X2Zrmbikz + 400933044U, // VSHUFF64X2Zrmi + 2043920564U, // VSHUFF64X2Zrmik + 1209270452U, // VSHUFF64X2Zrmikz + 1088815284U, // VSHUFF64X2Zrri + 2163130548U, // VSHUFF64X2Zrrik + 1357578420U, // VSHUFF64X2Zrrikz + 2491793859U, // VSHUFI32X4Z256rmbi + 2515780035U, // VSHUFI32X4Z256rmbik + 2517893571U, // VSHUFI32X4Z256rmbikz + 375767491U, // VSHUFI32X4Z256rmi + 1989394883U, // VSHUFI32X4Z256rmik + 1186202051U, // VSHUFI32X4Z256rmikz + 1088815555U, // VSHUFI32X4Z256rri + 2163130819U, // VSHUFI32X4Z256rrik + 1357578691U, // VSHUFI32X4Z256rrikz + 2760229315U, // VSHUFI32X4Zrmbi + 2784215491U, // VSHUFI32X4Zrmbik + 2786329027U, // VSHUFI32X4Zrmbikz + 382058947U, // VSHUFI32X4Zrmi + 1995686339U, // VSHUFI32X4Zrmik + 1192493507U, // VSHUFI32X4Zrmikz + 1088815555U, // VSHUFI32X4Zrri + 2163130819U, // VSHUFI32X4Zrrik + 1357578691U, // VSHUFI32X4Zrrikz + 1671807214U, // VSHUFI64X2Z256rmbi + 1731444974U, // VSHUFI64X2Z256rmbik + 1733558510U, // VSHUFI64X2Z256rmbikz + 375767278U, // VSHUFI64X2Z256rmi + 1989394670U, // VSHUFI64X2Z256rmik + 1186201838U, // VSHUFI64X2Z256rmikz + 1088815342U, // VSHUFI64X2Z256rri + 2163130606U, // VSHUFI64X2Z256rrik + 1357578478U, // VSHUFI64X2Z256rrikz + 2477113582U, // VSHUFI64X2Zrmbi + 2536751342U, // VSHUFI64X2Zrmbik + 2538864878U, // VSHUFI64X2Zrmbikz + 382058734U, // VSHUFI64X2Zrmi + 1995686126U, // VSHUFI64X2Zrmik + 1192493294U, // VSHUFI64X2Zrmikz + 1088815342U, // VSHUFI64X2Zrri + 2163130606U, // VSHUFI64X2Zrrik + 1357578478U, // VSHUFI64X2Zrrikz + 392547279U, // VSHUFPDYrmi + 1088818127U, // VSHUFPDYrri + 2999307215U, // VSHUFPDZ128rmbi + 3111373775U, // VSHUFPDZ128rmbik + 3079932879U, // VSHUFPDZ128rmbikz + 300272591U, // VSHUFPDZ128rmi + 2039729103U, // VSHUFPDZ128rmik + 1202981839U, // VSHUFPDZ128rmikz + 1088818127U, // VSHUFPDZ128rri + 2163133391U, // VSHUFPDZ128rrik + 1357581263U, // VSHUFPDZ128rrikz + 1657129935U, // VSHUFPDZ256rmbi + 1769196495U, // VSHUFPDZ256rmbik + 1737755599U, // VSHUFPDZ256rmbikz + 392547279U, // VSHUFPDZ256rmi + 2041826255U, // VSHUFPDZ256rmik + 1205078991U, // VSHUFPDZ256rmikz + 1088818127U, // VSHUFPDZ256rri + 2163133391U, // VSHUFPDZ256rrik + 1357581263U, // VSHUFPDZ256rrikz + 2462436303U, // VSHUFPDZrmbi + 2574502863U, // VSHUFPDZrmbik + 2543061967U, // VSHUFPDZrmbikz + 400935887U, // VSHUFPDZrmi + 2043923407U, // VSHUFPDZrmik + 1209273295U, // VSHUFPDZrmikz + 1088818127U, // VSHUFPDZrri + 2163133391U, // VSHUFPDZrrik + 1357581263U, // VSHUFPDZrrikz + 300272591U, // VSHUFPDrmi + 1088818127U, // VSHUFPDrri + 392553699U, // VSHUFPSYrmi + 1088824547U, // VSHUFPSYrri + 1661330659U, // VSHUFPSZ128rmbi + 1777591523U, // VSHUFPSZ128rmbik + 1752442083U, // VSHUFPSZ128rmbikz + 300279011U, // VSHUFPSZ128rmi + 2039735523U, // VSHUFPSZ128rmik + 1202988259U, // VSHUFPSZ128rmikz + 1088824547U, // VSHUFPSZ128rri + 2163139811U, // VSHUFPSZ128rrik + 1357587683U, // VSHUFPSZ128rrikz + 2466637027U, // VSHUFPSZ256rmbi + 2582897891U, // VSHUFPSZ256rmbik + 2557748451U, // VSHUFPSZ256rmbikz + 392553699U, // VSHUFPSZ256rmi + 2041832675U, // VSHUFPSZ256rmik + 1205085411U, // VSHUFPSZ256rmikz + 1088824547U, // VSHUFPSZ256rri + 2163139811U, // VSHUFPSZ256rrik + 1357587683U, // VSHUFPSZ256rrikz + 2735072483U, // VSHUFPSZrmbi + 2851333347U, // VSHUFPSZrmbik + 2826183907U, // VSHUFPSZrmbikz + 400942307U, // VSHUFPSZrmi + 2043929827U, // VSHUFPSZrmik + 1209279715U, // VSHUFPSZrmikz + 1088824547U, // VSHUFPSZrri + 2163139811U, // VSHUFPSZrrik + 1357587683U, // VSHUFPSZrrikz + 300279011U, // VSHUFPSrmi + 1088824547U, // VSHUFPSrri + 1346840U, // VSQRTPDYm + 551832856U, // VSQRTPDYr + 658712U, // VSQRTPDZ128m + 627674392U, // VSQRTPDZ128mb + 628100376U, // VSQRTPDZ128mbk + 627199256U, // VSQRTPDZ128mbkz + 3230600472U, // VSQRTPDZ128mk + 3229748504U, // VSQRTPDZ128mkz + 551832856U, // VSQRTPDZ128r + 3230698776U, // VSQRTPDZ128rk + 3229666584U, // VSQRTPDZ128rkz + 1346840U, // VSQRTPDZ256m + 629771544U, // VSQRTPDZ256mb + 630197528U, // VSQRTPDZ256mbk + 629296408U, // VSQRTPDZ256mbkz + 3230731544U, // VSQRTPDZ256mk + 3230633240U, // VSQRTPDZ256mkz + 551832856U, // VSQRTPDZ256r + 3230698776U, // VSQRTPDZ256rk + 3229666584U, // VSQRTPDZ256rkz + 1510680U, // VSQRTPDZm + 631868696U, // VSQRTPDZmb + 632294680U, // VSQRTPDZmbk + 631393560U, // VSQRTPDZmbkz + 3230780696U, // VSQRTPDZmk + 3230747928U, // VSQRTPDZmkz + 551832856U, // VSQRTPDZr + 1494296U, // VSQRTPDZrb + 3230829848U, // VSQRTPDZrbk + 3230797080U, // VSQRTPDZrbkz + 3230698776U, // VSQRTPDZrk + 3229666584U, // VSQRTPDZrkz + 658712U, // VSQRTPDm + 551832856U, // VSQRTPDr + 1353313U, // VSQRTPSYm + 551839329U, // VSQRTPSYr + 665185U, // VSQRTPSZ128m + 629794401U, // VSQRTPSZ128mb + 630400609U, // VSQRTPSZ128mbk + 629319265U, // VSQRTPSZ128mbkz + 3230606945U, // VSQRTPSZ128mk + 3229754977U, // VSQRTPSZ128mkz + 551839329U, // VSQRTPSZ128r + 3230705249U, // VSQRTPSZ128rk + 3229673057U, // VSQRTPSZ128rkz + 1353313U, // VSQRTPSZ256m + 631891553U, // VSQRTPSZ256mb + 632497761U, // VSQRTPSZ256mbk + 631416417U, // VSQRTPSZ256mbkz + 3230738017U, // VSQRTPSZ256mk + 3230639713U, // VSQRTPSZ256mkz + 551839329U, // VSQRTPSZ256r + 3230705249U, // VSQRTPSZ256rk + 3229673057U, // VSQRTPSZ256rkz + 1517153U, // VSQRTPSZm + 633988705U, // VSQRTPSZmb + 634594913U, // VSQRTPSZmbk + 633513569U, // VSQRTPSZmbkz + 3230787169U, // VSQRTPSZmk + 3230754401U, // VSQRTPSZmkz + 551839329U, // VSQRTPSZr + 1500769U, // VSQRTPSZrb + 3230836321U, // VSQRTPSZrbk + 3230803553U, // VSQRTPSZrbkz + 3230705249U, // VSQRTPSZrk + 3229673057U, // VSQRTPSZrkz + 665185U, // VSQRTPSm + 551839329U, // VSQRTPSr + 283267036U, // VSQRTSDZm + 283267036U, // VSQRTSDZm_Int + 1357893596U, // VSQRTSDZm_Intk + 1089474524U, // VSQRTSDZm_Intkz + 811651036U, // VSQRTSDZr + 811651036U, // VSQRTSDZr_Int + 87052252U, // VSQRTSDZr_Intk + 890277852U, // VSQRTSDZr_Intkz + 812781532U, // VSQRTSDZrb_Int + 87183324U, // VSQRTSDZrb_Intk + 890408924U, // VSQRTSDZrb_Intkz + 283267036U, // VSQRTSDm + 283267036U, // VSQRTSDm_Int + 811651036U, // VSQRTSDr + 811651036U, // VSQRTSDr_Int + 283289798U, // VSQRTSSZm + 283289798U, // VSQRTSSZm_Int + 1358096582U, // VSQRTSSZm_Intk + 1089677510U, // VSQRTSSZm_Intkz + 811657414U, // VSQRTSSZr + 811657414U, // VSQRTSSZr_Int + 87058630U, // VSQRTSSZr_Intk + 890284230U, // VSQRTSSZr_Intkz + 812787910U, // VSQRTSSZrb_Int + 87189702U, // VSQRTSSZrb_Intk + 890415302U, // VSQRTSSZrb_Intkz + 283289798U, // VSQRTSSm + 283289798U, // VSQRTSSm_Int + 811657414U, // VSQRTSSr + 811657414U, // VSQRTSSr_Int + 237919U, // VSTMXCSR + 812616425U, // VSUBPDYrm + 811649769U, // VSUBPDYrr + 811731689U, // VSUBPDZ128rm + 358763241U, // VSUBPDZ128rmb + 1433389801U, // VSUBPDZ128rmbk + 1164970729U, // VSUBPDZ128rmbkz + 86985449U, // VSUBPDZ128rmk + 890178281U, // VSUBPDZ128rmkz + 811649769U, // VSUBPDZ128rr + 87050985U, // VSUBPDZ128rrk + 890276585U, // VSUBPDZ128rrkz + 812616425U, // VSUBPDZ256rm + 360860393U, // VSUBPDZ256rmb + 1435486953U, // VSUBPDZ256rmbk + 1167067881U, // VSUBPDZ256rmbkz + 87083753U, // VSUBPDZ256rmk + 890309353U, // VSUBPDZ256rmkz + 811649769U, // VSUBPDZ256rr + 87050985U, // VSUBPDZ256rrk + 890276585U, // VSUBPDZ256rrkz + 812731113U, // VSUBPDZrm + 362957545U, // VSUBPDZrmb + 1437584105U, // VSUBPDZrmbk + 1169165033U, // VSUBPDZrmbkz + 87132905U, // VSUBPDZrmk + 890358505U, // VSUBPDZrmkz + 811649769U, // VSUBPDZrr + 812780265U, // VSUBPDZrrb + 87182057U, // VSUBPDZrrbk + 890407657U, // VSUBPDZrrbkz + 87050985U, // VSUBPDZrrk + 890276585U, // VSUBPDZrrkz + 811731689U, // VSUBPDrm + 811649769U, // VSUBPDrr + 812622822U, // VSUBPSYrm + 811656166U, // VSUBPSYrr + 811738086U, // VSUBPSZ128rm + 360883174U, // VSUBPSZ128rmb + 1435689958U, // VSUBPSZ128rmbk + 1167270886U, // VSUBPSZ128rmbkz + 86991846U, // VSUBPSZ128rmk + 890184678U, // VSUBPSZ128rmkz + 811656166U, // VSUBPSZ128rr + 87057382U, // VSUBPSZ128rrk + 890282982U, // VSUBPSZ128rrkz + 812622822U, // VSUBPSZ256rm + 362980326U, // VSUBPSZ256rmb + 1437787110U, // VSUBPSZ256rmbk + 1169368038U, // VSUBPSZ256rmbkz + 87090150U, // VSUBPSZ256rmk + 890315750U, // VSUBPSZ256rmkz + 811656166U, // VSUBPSZ256rr + 87057382U, // VSUBPSZ256rrk + 890282982U, // VSUBPSZ256rrkz + 812737510U, // VSUBPSZrm + 365077478U, // VSUBPSZrmb + 1439884262U, // VSUBPSZrmbk + 1171465190U, // VSUBPSZrmbkz + 87139302U, // VSUBPSZrmk + 890364902U, // VSUBPSZrmkz + 811656166U, // VSUBPSZrr + 812786662U, // VSUBPSZrrb + 87188454U, // VSUBPSZrrbk + 890414054U, // VSUBPSZrrbkz + 87057382U, // VSUBPSZrrk + 890282982U, // VSUBPSZrrkz + 811738086U, // VSUBPSrm + 811656166U, // VSUBPSrr + 283266786U, // VSUBSDZrm + 283266786U, // VSUBSDZrm_Int + 1357893346U, // VSUBSDZrm_Intk + 1089474274U, // VSUBSDZrm_Intkz + 811650786U, // VSUBSDZrr + 811650786U, // VSUBSDZrr_Int + 87052002U, // VSUBSDZrr_Intk + 890277602U, // VSUBSDZrr_Intkz + 812781282U, // VSUBSDZrrb_Int + 87183074U, // VSUBSDZrrb_Intk + 890408674U, // VSUBSDZrrb_Intkz + 283266786U, // VSUBSDrm + 283266786U, // VSUBSDrm_Int + 811650786U, // VSUBSDrr + 811650786U, // VSUBSDrr_Int + 283289565U, // VSUBSSZrm + 283289565U, // VSUBSSZrm_Int + 1358096349U, // VSUBSSZrm_Intk + 1089677277U, // VSUBSSZrm_Intkz + 811657181U, // VSUBSSZrr + 811657181U, // VSUBSSZrr_Int + 87058397U, // VSUBSSZrr_Intk + 890283997U, // VSUBSSZrr_Intkz + 812787677U, // VSUBSSZrrb_Int + 87189469U, // VSUBSSZrrb_Intk + 890415069U, // VSUBSSZrrb_Intkz + 283289565U, // VSUBSSrm + 283289565U, // VSUBSSrm_Int + 811657181U, // VSUBSSrr + 811657181U, // VSUBSSrr_Int + 1346849U, // VTESTPDYrm + 551832865U, // VTESTPDYrr + 658721U, // VTESTPDrm + 551832865U, // VTESTPDrr + 1353322U, // VTESTPSYrm + 551839338U, // VTESTPSYrr + 665194U, // VTESTPSrm + 551839338U, // VTESTPSrr + 552177470U, // VUCOMISDZrm + 552177470U, // VUCOMISDZrm_Int + 551833406U, // VUCOMISDZrr + 551833406U, // VUCOMISDZrr_Int + 551843422U, // VUCOMISDZrrb + 552177470U, // VUCOMISDrm + 552177470U, // VUCOMISDrm_Int + 551833406U, // VUCOMISDrr + 551833406U, // VUCOMISDrr_Int + 552200272U, // VUCOMISSZrm + 552200272U, // VUCOMISSZrm_Int + 551839824U, // VUCOMISSZrr + 551839824U, // VUCOMISSZrr_Int + 551843891U, // VUCOMISSZrrb + 552200272U, // VUCOMISSrm + 552200272U, // VUCOMISSrm_Int + 551839824U, // VUCOMISSrr + 551839824U, // VUCOMISSrr_Int + 812616664U, // VUNPCKHPDYrm + 811650008U, // VUNPCKHPDYrr + 811731928U, // VUNPCKHPDZ128rm + 358763480U, // VUNPCKHPDZ128rmb + 1433390040U, // VUNPCKHPDZ128rmbk + 1164970968U, // VUNPCKHPDZ128rmbkz + 86985688U, // VUNPCKHPDZ128rmk + 890178520U, // VUNPCKHPDZ128rmkz + 811650008U, // VUNPCKHPDZ128rr + 87051224U, // VUNPCKHPDZ128rrk + 890276824U, // VUNPCKHPDZ128rrkz + 812616664U, // VUNPCKHPDZ256rm + 360860632U, // VUNPCKHPDZ256rmb + 1435487192U, // VUNPCKHPDZ256rmbk + 1167068120U, // VUNPCKHPDZ256rmbkz + 87083992U, // VUNPCKHPDZ256rmk + 890309592U, // VUNPCKHPDZ256rmkz + 811650008U, // VUNPCKHPDZ256rr + 87051224U, // VUNPCKHPDZ256rrk + 890276824U, // VUNPCKHPDZ256rrkz + 812731352U, // VUNPCKHPDZrm + 362957784U, // VUNPCKHPDZrmb + 1437584344U, // VUNPCKHPDZrmbk + 1169165272U, // VUNPCKHPDZrmbkz + 87133144U, // VUNPCKHPDZrmk + 890358744U, // VUNPCKHPDZrmkz + 811650008U, // VUNPCKHPDZrr + 87051224U, // VUNPCKHPDZrrk + 890276824U, // VUNPCKHPDZrrkz + 811731928U, // VUNPCKHPDrm + 811650008U, // VUNPCKHPDrr + 812623084U, // VUNPCKHPSYrm + 811656428U, // VUNPCKHPSYrr + 811738348U, // VUNPCKHPSZ128rm + 360883436U, // VUNPCKHPSZ128rmb + 1435690220U, // VUNPCKHPSZ128rmbk + 1167271148U, // VUNPCKHPSZ128rmbkz + 86992108U, // VUNPCKHPSZ128rmk + 890184940U, // VUNPCKHPSZ128rmkz + 811656428U, // VUNPCKHPSZ128rr + 87057644U, // VUNPCKHPSZ128rrk + 890283244U, // VUNPCKHPSZ128rrkz + 812623084U, // VUNPCKHPSZ256rm + 362980588U, // VUNPCKHPSZ256rmb + 1437787372U, // VUNPCKHPSZ256rmbk + 1169368300U, // VUNPCKHPSZ256rmbkz + 87090412U, // VUNPCKHPSZ256rmk + 890316012U, // VUNPCKHPSZ256rmkz + 811656428U, // VUNPCKHPSZ256rr + 87057644U, // VUNPCKHPSZ256rrk + 890283244U, // VUNPCKHPSZ256rrkz + 812737772U, // VUNPCKHPSZrm + 365077740U, // VUNPCKHPSZrmb + 1439884524U, // VUNPCKHPSZrmbk + 1171465452U, // VUNPCKHPSZrmbkz + 87139564U, // VUNPCKHPSZrmk + 890365164U, // VUNPCKHPSZrmkz + 811656428U, // VUNPCKHPSZrr + 87057644U, // VUNPCKHPSZrrk + 890283244U, // VUNPCKHPSZrrkz + 811738348U, // VUNPCKHPSrm + 811656428U, // VUNPCKHPSrr + 812616706U, // VUNPCKLPDYrm + 811650050U, // VUNPCKLPDYrr + 811731970U, // VUNPCKLPDZ128rm + 358763522U, // VUNPCKLPDZ128rmb + 1433390082U, // VUNPCKLPDZ128rmbk + 1164971010U, // VUNPCKLPDZ128rmbkz + 86985730U, // VUNPCKLPDZ128rmk + 890178562U, // VUNPCKLPDZ128rmkz + 811650050U, // VUNPCKLPDZ128rr + 87051266U, // VUNPCKLPDZ128rrk + 890276866U, // VUNPCKLPDZ128rrkz + 812616706U, // VUNPCKLPDZ256rm + 360860674U, // VUNPCKLPDZ256rmb + 1435487234U, // VUNPCKLPDZ256rmbk + 1167068162U, // VUNPCKLPDZ256rmbkz + 87084034U, // VUNPCKLPDZ256rmk + 890309634U, // VUNPCKLPDZ256rmkz + 811650050U, // VUNPCKLPDZ256rr + 87051266U, // VUNPCKLPDZ256rrk + 890276866U, // VUNPCKLPDZ256rrkz + 812731394U, // VUNPCKLPDZrm + 362957826U, // VUNPCKLPDZrmb + 1437584386U, // VUNPCKLPDZrmbk + 1169165314U, // VUNPCKLPDZrmbkz + 87133186U, // VUNPCKLPDZrmk + 890358786U, // VUNPCKLPDZrmkz + 811650050U, // VUNPCKLPDZrr + 87051266U, // VUNPCKLPDZrrk + 890276866U, // VUNPCKLPDZrrkz + 811731970U, // VUNPCKLPDrm + 811650050U, // VUNPCKLPDrr + 812623146U, // VUNPCKLPSYrm + 811656490U, // VUNPCKLPSYrr + 811738410U, // VUNPCKLPSZ128rm + 360883498U, // VUNPCKLPSZ128rmb + 1435690282U, // VUNPCKLPSZ128rmbk + 1167271210U, // VUNPCKLPSZ128rmbkz + 86992170U, // VUNPCKLPSZ128rmk + 890185002U, // VUNPCKLPSZ128rmkz + 811656490U, // VUNPCKLPSZ128rr + 87057706U, // VUNPCKLPSZ128rrk + 890283306U, // VUNPCKLPSZ128rrkz + 812623146U, // VUNPCKLPSZ256rm + 362980650U, // VUNPCKLPSZ256rmb + 1437787434U, // VUNPCKLPSZ256rmbk + 1169368362U, // VUNPCKLPSZ256rmbkz + 87090474U, // VUNPCKLPSZ256rmk + 890316074U, // VUNPCKLPSZ256rmkz + 811656490U, // VUNPCKLPSZ256rr + 87057706U, // VUNPCKLPSZ256rrk + 890283306U, // VUNPCKLPSZ256rrkz + 812737834U, // VUNPCKLPSZrm + 365077802U, // VUNPCKLPSZrmb + 1439884586U, // VUNPCKLPSZrmbk + 1171465514U, // VUNPCKLPSZrmbkz + 87139626U, // VUNPCKLPSZrmk + 890365226U, // VUNPCKLPSZrmkz + 811656490U, // VUNPCKLPSZrr + 87057706U, // VUNPCKLPSZrrk + 890283306U, // VUNPCKLPSZrrkz + 811738410U, // VUNPCKLPSrm + 811656490U, // VUNPCKLPSrr + 812616912U, // VXORPDYrm + 811650256U, // VXORPDYrr + 811732176U, // VXORPDZ128rm + 358763728U, // VXORPDZ128rmb + 1433390288U, // VXORPDZ128rmbk + 1164971216U, // VXORPDZ128rmbkz + 86985936U, // VXORPDZ128rmk + 890178768U, // VXORPDZ128rmkz + 811650256U, // VXORPDZ128rr + 87051472U, // VXORPDZ128rrk + 890277072U, // VXORPDZ128rrkz + 812616912U, // VXORPDZ256rm + 360860880U, // VXORPDZ256rmb + 1435487440U, // VXORPDZ256rmbk + 1167068368U, // VXORPDZ256rmbkz + 87084240U, // VXORPDZ256rmk + 890309840U, // VXORPDZ256rmkz + 811650256U, // VXORPDZ256rr + 87051472U, // VXORPDZ256rrk + 890277072U, // VXORPDZ256rrkz + 812731600U, // VXORPDZrm + 362958032U, // VXORPDZrmb + 1437584592U, // VXORPDZrmbk + 1169165520U, // VXORPDZrmbkz + 87133392U, // VXORPDZrmk + 890358992U, // VXORPDZrmkz + 811650256U, // VXORPDZrr + 87051472U, // VXORPDZrrk + 890277072U, // VXORPDZrrkz + 811732176U, // VXORPDrm + 811650256U, // VXORPDrr + 812623369U, // VXORPSYrm + 811656713U, // VXORPSYrr + 811738633U, // VXORPSZ128rm + 360883721U, // VXORPSZ128rmb + 1435690505U, // VXORPSZ128rmbk + 1167271433U, // VXORPSZ128rmbkz + 86992393U, // VXORPSZ128rmk + 890185225U, // VXORPSZ128rmkz + 811656713U, // VXORPSZ128rr + 87057929U, // VXORPSZ128rrk + 890283529U, // VXORPSZ128rrkz + 812623369U, // VXORPSZ256rm + 362980873U, // VXORPSZ256rmb + 1437787657U, // VXORPSZ256rmbk + 1169368585U, // VXORPSZ256rmbkz + 87090697U, // VXORPSZ256rmk + 890316297U, // VXORPSZ256rmkz + 811656713U, // VXORPSZ256rr + 87057929U, // VXORPSZ256rrk + 890283529U, // VXORPSZ256rrkz + 812738057U, // VXORPSZrm + 365078025U, // VXORPSZrmb + 1439884809U, // VXORPSZrmbk + 1171465737U, // VXORPSZrmbkz + 87139849U, // VXORPSZrmk + 890365449U, // VXORPSZrmkz + 811656713U, // VXORPSZrr + 87057929U, // VXORPSZrrk + 890283529U, // VXORPSZrrkz + 811738633U, // VXORPSrm + 811656713U, // VXORPSrr + 15238U, // VZEROALL + 15496U, // VZEROUPPER + 15865U, // WAIT + 14996U, // WBINVD + 15003U, // WBNOINVD + 21627U, // WRFSBASE + 23544U, // WRFSBASE64 + 21649U, // WRGSBASE + 23566U, // WRGSBASE64 + 15530U, // WRMSR + 15919U, // WRPKRUr + 12619671U, // WRSSD + 18915114U, // WRSSQ + 12619690U, // WRUSSD + 18915121U, // WRUSSQ + 26977U, // XABORT + 15062U, // XACQUIRE_PREFIX + 1088711480U, // XADD16rm + 84978488U, // XADD16rr + 14963702U, // XADD32rm + 84972534U, // XADD32rr + 551836255U, // XADD64rm + 84974175U, // XADD64rr + 1357136882U, // XADD8rm + 84968434U, // XADD8rr + 464986U, // XBEGIN_2 + 464986U, // XBEGIN_4 + 292063U, // XCHG16ar + 1088711686U, // XCHG16rm + 178318342U, // XCHG16rr + 292123U, // XCHG32ar + 14963911U, // XCHG32rm + 178312391U, // XCHG32rr + 292188U, // XCHG64ar + 551836740U, // XCHG64rm + 178314308U, // XCHG64rr + 1357136955U, // XCHG8rm + 178308155U, // XCHG8rr + 21080U, // XCH_F + 14914U, // XCRYPTCBC + 14878U, // XCRYPTCFB + 15536U, // XCRYPTCTR + 14868U, // XCRYPTECB + 14888U, // XCRYPTOFB + 14977U, // XEND + 15926U, // XGETBV + 14898U, // XLAT + 2125212U, // XOR16i16 + 4238748U, // XOR16mi + 4238748U, // XOR16mi8 + 4238748U, // XOR16mr + 6352284U, // XOR16ri + 6352284U, // XOR16ri8 + 6368668U, // XOR16rm + 6352284U, // XOR16rr + 8449436U, // XOR16rr_REV + 10507871U, // XOR32i32 + 12621407U, // XOR32mi + 12621407U, // XOR32mi8 + 12621407U, // XOR32mr + 6346335U, // XOR32ri + 6346335U, // XOR32ri8 + 283203167U, // XOR32rm + 6346335U, // XOR32rr + 8443487U, // XOR32rr_REV + 16801390U, // XOR64i32 + 18914926U, // XOR64mi32 + 18914926U, // XOR64mi8 + 18914926U, // XOR64mr + 6348398U, // XOR64ri32 + 6348398U, // XOR64ri8 + 283221614U, // XOR64rm + 6348398U, // XOR64rr + 8445550U, // XOR64rr_REV + 20989303U, // XOR8i8 + 23102839U, // XOR8mi + 23102839U, // XOR8mi8 + 23102839U, // XOR8mr + 6342007U, // XOR8ri + 6342007U, // XOR8ri8 + 6407543U, // XOR8rm + 6342007U, // XOR8rr + 8439159U, // XOR8rr_REV + 8522961U, // XORPDrm + 8441041U, // XORPDrr + 8529418U, // XORPSrm + 8447498U, // XORPSrr + 15078U, // XRELEASE_PREFIX + 680256U, // XRSTOR + 672072U, // XRSTOR64 + 681685U, // XRSTORS + 672092U, // XRSTORS64 + 676397U, // XSAVE + 672062U, // XSAVE64 + 673547U, // XSAVEC + 672051U, // XSAVEC64 + 682308U, // XSAVEOPT + 672103U, // XSAVEOPT64 + 680381U, // XSAVES + 672082U, // XSAVES64 + 15933U, // XSETBV + 14704U, // XSHA1 + 14797U, // XSHA256 + 15071U, // XSTORE + 15895U, // XTEST + }; + + static const uint16_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // AVX1_SETALLONES + 0U, // AVX2_SETALLONES + 0U, // AVX512_128_SET0 + 0U, // AVX512_256_SET0 + 0U, // AVX512_512_SET0 + 0U, // AVX512_512_SETALLONES + 0U, // AVX512_512_SEXT_MASK_32 + 0U, // AVX512_512_SEXT_MASK_64 + 0U, // AVX512_FsFLD0SD + 0U, // AVX512_FsFLD0SS + 0U, // AVX_SET0 + 0U, // KSET0D + 0U, // KSET0Q + 0U, // KSET0W + 0U, // KSET1D + 0U, // KSET1Q + 0U, // KSET1W + 0U, // MMX_SET0 + 0U, // V_SET0 + 0U, // V_SETALLONES + 0U, // AAA + 0U, // AAD8i8 + 0U, // AAM8i8 + 0U, // AAS + 0U, // ABS_F + 0U, // ABS_Fp32 + 0U, // ABS_Fp64 + 0U, // ABS_Fp80 + 0U, // ADC16i16 + 0U, // ADC16mi + 0U, // ADC16mi8 + 0U, // ADC16mr + 0U, // ADC16ri + 0U, // ADC16ri8 + 0U, // ADC16rm + 0U, // ADC16rr + 0U, // ADC16rr_REV + 0U, // ADC32i32 + 0U, // ADC32mi + 0U, // ADC32mi8 + 0U, // ADC32mr + 0U, // ADC32ri + 0U, // ADC32ri8 + 0U, // ADC32rm + 0U, // ADC32rr + 0U, // ADC32rr_REV + 0U, // ADC64i32 + 0U, // ADC64mi32 + 0U, // ADC64mi8 + 0U, // ADC64mr + 0U, // ADC64ri32 + 0U, // ADC64ri8 + 0U, // ADC64rm + 0U, // ADC64rr + 0U, // ADC64rr_REV + 0U, // ADC8i8 + 0U, // ADC8mi + 0U, // ADC8mi8 + 0U, // ADC8mr + 0U, // ADC8ri + 0U, // ADC8ri8 + 0U, // ADC8rm + 0U, // ADC8rr + 0U, // ADC8rr_REV + 0U, // ADCX32rm + 0U, // ADCX32rr + 0U, // ADCX64rm + 0U, // ADCX64rr + 0U, // ADD16i16 + 0U, // ADD16mi + 0U, // ADD16mi8 + 0U, // ADD16mr + 0U, // ADD16ri + 0U, // ADD16ri8 + 0U, // ADD16rm + 0U, // ADD16rr + 0U, // ADD16rr_REV + 0U, // ADD32i32 + 0U, // ADD32mi + 0U, // ADD32mi8 + 0U, // ADD32mr + 0U, // ADD32ri + 0U, // ADD32ri8 + 0U, // ADD32rm + 0U, // ADD32rr + 0U, // ADD32rr_REV + 0U, // ADD64i32 + 0U, // ADD64mi32 + 0U, // ADD64mi8 + 0U, // ADD64mr + 0U, // ADD64ri32 + 0U, // ADD64ri8 + 0U, // ADD64rm + 0U, // ADD64rr + 0U, // ADD64rr_REV + 0U, // ADD8i8 + 0U, // ADD8mi + 0U, // ADD8mi8 + 0U, // ADD8mr + 0U, // ADD8ri + 0U, // ADD8ri8 + 0U, // ADD8rm + 0U, // ADD8rr + 0U, // ADD8rr_REV + 0U, // ADDPDrm + 0U, // ADDPDrr + 0U, // ADDPSrm + 0U, // ADDPSrr + 0U, // ADDSDrm + 0U, // ADDSDrm_Int + 0U, // ADDSDrr + 0U, // ADDSDrr_Int + 0U, // ADDSSrm + 0U, // ADDSSrm_Int + 0U, // ADDSSrr + 0U, // ADDSSrr_Int + 0U, // ADDSUBPDrm + 0U, // ADDSUBPDrr + 0U, // ADDSUBPSrm + 0U, // ADDSUBPSrr + 0U, // ADD_F32m + 0U, // ADD_F64m + 0U, // ADD_FI16m + 0U, // ADD_FI32m + 0U, // ADD_FPrST0 + 0U, // ADD_FST0r + 0U, // ADD_Fp32 + 0U, // ADD_Fp32m + 0U, // ADD_Fp64 + 0U, // ADD_Fp64m + 0U, // ADD_Fp64m32 + 0U, // ADD_Fp80 + 0U, // ADD_Fp80m32 + 0U, // ADD_Fp80m64 + 0U, // ADD_FpI16m32 + 0U, // ADD_FpI16m64 + 0U, // ADD_FpI16m80 + 0U, // ADD_FpI32m32 + 0U, // ADD_FpI32m64 + 0U, // ADD_FpI32m80 + 0U, // ADD_FrST0 + 0U, // ADOX32rm + 0U, // ADOX32rr + 0U, // ADOX64rm + 0U, // ADOX64rr + 0U, // AESDECLASTrm + 0U, // AESDECLASTrr + 0U, // AESDECrm + 0U, // AESDECrr + 0U, // AESENCLASTrm + 0U, // AESENCLASTrr + 0U, // AESENCrm + 0U, // AESENCrr + 0U, // AESIMCrm + 0U, // AESIMCrr + 4U, // AESKEYGENASSIST128rm + 72U, // AESKEYGENASSIST128rr + 0U, // AND16i16 + 0U, // AND16mi + 0U, // AND16mi8 + 0U, // AND16mr + 0U, // AND16ri + 0U, // AND16ri8 + 0U, // AND16rm + 0U, // AND16rr + 0U, // AND16rr_REV + 0U, // AND32i32 + 0U, // AND32mi + 0U, // AND32mi8 + 0U, // AND32mr + 0U, // AND32ri + 0U, // AND32ri8 + 0U, // AND32rm + 0U, // AND32rr + 0U, // AND32rr_REV + 0U, // AND64i32 + 0U, // AND64mi32 + 0U, // AND64mi8 + 0U, // AND64mr + 0U, // AND64ri32 + 0U, // AND64ri8 + 0U, // AND64rm + 0U, // AND64rr + 0U, // AND64rr_REV + 0U, // AND8i8 + 0U, // AND8mi + 0U, // AND8mi8 + 0U, // AND8mr + 0U, // AND8ri + 0U, // AND8ri8 + 0U, // AND8rm + 0U, // AND8rr + 0U, // AND8rr_REV + 72U, // ANDN32rm + 4U, // ANDN32rr + 72U, // ANDN64rm + 4U, // ANDN64rr + 0U, // ANDNPDrm + 0U, // ANDNPDrr + 0U, // ANDNPSrm + 0U, // ANDNPSrr + 0U, // ANDPDrm + 0U, // ANDPDrr + 0U, // ANDPSrm + 0U, // ANDPSrr + 0U, // ARPL16mr + 0U, // ARPL16rr + 4U, // BEXTR32rm + 4U, // BEXTR32rr + 4U, // BEXTR64rm + 4U, // BEXTR64rr + 4U, // BEXTRI32mi + 4U, // BEXTRI32ri + 4U, // BEXTRI64mi + 4U, // BEXTRI64ri + 0U, // BLCFILL32rm + 0U, // BLCFILL32rr + 0U, // BLCFILL64rm + 0U, // BLCFILL64rr + 0U, // BLCI32rm + 0U, // BLCI32rr + 0U, // BLCI64rm + 0U, // BLCI64rr + 0U, // BLCIC32rm + 0U, // BLCIC32rr + 0U, // BLCIC64rm + 0U, // BLCIC64rr + 0U, // BLCMSK32rm + 0U, // BLCMSK32rr + 0U, // BLCMSK64rm + 0U, // BLCMSK64rr + 0U, // BLCS32rm + 0U, // BLCS32rr + 0U, // BLCS64rm + 0U, // BLCS64rr + 0U, // BLENDPDrmi + 4U, // BLENDPDrri + 0U, // BLENDPSrmi + 4U, // BLENDPSrri + 0U, // BLENDVPDrm0 + 0U, // BLENDVPDrr0 + 0U, // BLENDVPSrm0 + 0U, // BLENDVPSrr0 + 0U, // BLSFILL32rm + 0U, // BLSFILL32rr + 0U, // BLSFILL64rm + 0U, // BLSFILL64rr + 0U, // BLSI32rm + 0U, // BLSI32rr + 0U, // BLSI64rm + 0U, // BLSI64rr + 0U, // BLSIC32rm + 0U, // BLSIC32rr + 0U, // BLSIC64rm + 0U, // BLSIC64rr + 0U, // BLSMSK32rm + 0U, // BLSMSK32rr + 0U, // BLSMSK64rm + 0U, // BLSMSK64rr + 0U, // BLSR32rm + 0U, // BLSR32rr + 0U, // BLSR64rm + 0U, // BLSR64rr + 0U, // BNDCL32rm + 0U, // BNDCL32rr + 0U, // BNDCL64rm + 0U, // BNDCL64rr + 0U, // BNDCN32rm + 0U, // BNDCN32rr + 0U, // BNDCN64rm + 0U, // BNDCN64rr + 0U, // BNDCU32rm + 0U, // BNDCU32rr + 0U, // BNDCU64rm + 0U, // BNDCU64rr + 0U, // BNDLDXrm + 0U, // BNDMK32rm + 0U, // BNDMK64rm + 0U, // BNDMOV32mr + 0U, // BNDMOV32rm + 0U, // BNDMOV64mr + 0U, // BNDMOV64rm + 0U, // BNDMOVrr + 0U, // BNDMOVrr_REV + 0U, // BNDSTXmr + 0U, // BOUNDS16rm + 0U, // BOUNDS32rm + 0U, // BSF16rm + 0U, // BSF16rr + 0U, // BSF32rm + 0U, // BSF32rr + 0U, // BSF64rm + 0U, // BSF64rr + 0U, // BSR16rm + 0U, // BSR16rr + 0U, // BSR32rm + 0U, // BSR32rr + 0U, // BSR64rm + 0U, // BSR64rr + 0U, // BSWAP16r_BAD + 0U, // BSWAP32r + 0U, // BSWAP64r + 0U, // BT16mi8 + 0U, // BT16mr + 0U, // BT16ri8 + 0U, // BT16rr + 0U, // BT32mi8 + 0U, // BT32mr + 0U, // BT32ri8 + 0U, // BT32rr + 0U, // BT64mi8 + 0U, // BT64mr + 0U, // BT64ri8 + 0U, // BT64rr + 0U, // BTC16mi8 + 0U, // BTC16mr + 0U, // BTC16ri8 + 0U, // BTC16rr + 0U, // BTC32mi8 + 0U, // BTC32mr + 0U, // BTC32ri8 + 0U, // BTC32rr + 0U, // BTC64mi8 + 0U, // BTC64mr + 0U, // BTC64ri8 + 0U, // BTC64rr + 0U, // BTR16mi8 + 0U, // BTR16mr + 0U, // BTR16ri8 + 0U, // BTR16rr + 0U, // BTR32mi8 + 0U, // BTR32mr + 0U, // BTR32ri8 + 0U, // BTR32rr + 0U, // BTR64mi8 + 0U, // BTR64mr + 0U, // BTR64ri8 + 0U, // BTR64rr + 0U, // BTS16mi8 + 0U, // BTS16mr + 0U, // BTS16ri8 + 0U, // BTS16rr + 0U, // BTS32mi8 + 0U, // BTS32mr + 0U, // BTS32ri8 + 0U, // BTS32rr + 0U, // BTS64mi8 + 0U, // BTS64mr + 0U, // BTS64ri8 + 0U, // BTS64rr + 4U, // BZHI32rm + 4U, // BZHI32rr + 4U, // BZHI64rm + 4U, // BZHI64rr + 0U, // CALL16m + 0U, // CALL16m_NT + 0U, // CALL16r + 0U, // CALL16r_NT + 0U, // CALL32m + 0U, // CALL32m_NT + 0U, // CALL32r + 0U, // CALL32r_NT + 0U, // CALL64m + 0U, // CALL64m_NT + 0U, // CALL64pcrel32 + 0U, // CALL64r + 0U, // CALL64r_NT + 0U, // CALLpcrel16 + 0U, // CALLpcrel32 + 0U, // CBW + 0U, // CDQ + 0U, // CDQE + 0U, // CHS_F + 0U, // CHS_Fp32 + 0U, // CHS_Fp64 + 0U, // CHS_Fp80 + 0U, // CLAC + 0U, // CLC + 0U, // CLD + 0U, // CLDEMOTE + 0U, // CLFLUSH + 0U, // CLFLUSHOPT + 0U, // CLGI + 0U, // CLI + 0U, // CLRSSBSY + 0U, // CLTS + 0U, // CLWB + 0U, // CLZEROr + 0U, // CMC + 0U, // CMOVA16rm + 0U, // CMOVA16rr + 0U, // CMOVA32rm + 0U, // CMOVA32rr + 0U, // CMOVA64rm + 0U, // CMOVA64rr + 0U, // CMOVAE16rm + 0U, // CMOVAE16rr + 0U, // CMOVAE32rm + 0U, // CMOVAE32rr + 0U, // CMOVAE64rm + 0U, // CMOVAE64rr + 0U, // CMOVB16rm + 0U, // CMOVB16rr + 0U, // CMOVB32rm + 0U, // CMOVB32rr + 0U, // CMOVB64rm + 0U, // CMOVB64rr + 0U, // CMOVBE16rm + 0U, // CMOVBE16rr + 0U, // CMOVBE32rm + 0U, // CMOVBE32rr + 0U, // CMOVBE64rm + 0U, // CMOVBE64rr + 0U, // CMOVBE_F + 0U, // CMOVBE_Fp32 + 0U, // CMOVBE_Fp64 + 0U, // CMOVBE_Fp80 + 0U, // CMOVB_F + 0U, // CMOVB_Fp32 + 0U, // CMOVB_Fp64 + 0U, // CMOVB_Fp80 + 0U, // CMOVE16rm + 0U, // CMOVE16rr + 0U, // CMOVE32rm + 0U, // CMOVE32rr + 0U, // CMOVE64rm + 0U, // CMOVE64rr + 0U, // CMOVE_F + 0U, // CMOVE_Fp32 + 0U, // CMOVE_Fp64 + 0U, // CMOVE_Fp80 + 0U, // CMOVG16rm + 0U, // CMOVG16rr + 0U, // CMOVG32rm + 0U, // CMOVG32rr + 0U, // CMOVG64rm + 0U, // CMOVG64rr + 0U, // CMOVGE16rm + 0U, // CMOVGE16rr + 0U, // CMOVGE32rm + 0U, // CMOVGE32rr + 0U, // CMOVGE64rm + 0U, // CMOVGE64rr + 0U, // CMOVL16rm + 0U, // CMOVL16rr + 0U, // CMOVL32rm + 0U, // CMOVL32rr + 0U, // CMOVL64rm + 0U, // CMOVL64rr + 0U, // CMOVLE16rm + 0U, // CMOVLE16rr + 0U, // CMOVLE32rm + 0U, // CMOVLE32rr + 0U, // CMOVLE64rm + 0U, // CMOVLE64rr + 0U, // CMOVNBE_F + 0U, // CMOVNBE_Fp32 + 0U, // CMOVNBE_Fp64 + 0U, // CMOVNBE_Fp80 + 0U, // CMOVNB_F + 0U, // CMOVNB_Fp32 + 0U, // CMOVNB_Fp64 + 0U, // CMOVNB_Fp80 + 0U, // CMOVNE16rm + 0U, // CMOVNE16rr + 0U, // CMOVNE32rm + 0U, // CMOVNE32rr + 0U, // CMOVNE64rm + 0U, // CMOVNE64rr + 0U, // CMOVNE_F + 0U, // CMOVNE_Fp32 + 0U, // CMOVNE_Fp64 + 0U, // CMOVNE_Fp80 + 0U, // CMOVNO16rm + 0U, // CMOVNO16rr + 0U, // CMOVNO32rm + 0U, // CMOVNO32rr + 0U, // CMOVNO64rm + 0U, // CMOVNO64rr + 0U, // CMOVNP16rm + 0U, // CMOVNP16rr + 0U, // CMOVNP32rm + 0U, // CMOVNP32rr + 0U, // CMOVNP64rm + 0U, // CMOVNP64rr + 0U, // CMOVNP_F + 0U, // CMOVNP_Fp32 + 0U, // CMOVNP_Fp64 + 0U, // CMOVNP_Fp80 + 0U, // CMOVNS16rm + 0U, // CMOVNS16rr + 0U, // CMOVNS32rm + 0U, // CMOVNS32rr + 0U, // CMOVNS64rm + 0U, // CMOVNS64rr + 0U, // CMOVO16rm + 0U, // CMOVO16rr + 0U, // CMOVO32rm + 0U, // CMOVO32rr + 0U, // CMOVO64rm + 0U, // CMOVO64rr + 0U, // CMOVP16rm + 0U, // CMOVP16rr + 0U, // CMOVP32rm + 0U, // CMOVP32rr + 0U, // CMOVP64rm + 0U, // CMOVP64rr + 0U, // CMOVP_F + 0U, // CMOVP_Fp32 + 0U, // CMOVP_Fp64 + 0U, // CMOVP_Fp80 + 0U, // CMOVS16rm + 0U, // CMOVS16rr + 0U, // CMOVS32rm + 0U, // CMOVS32rr + 0U, // CMOVS64rm + 0U, // CMOVS64rr + 0U, // CMP16i16 + 0U, // CMP16mi + 0U, // CMP16mi8 + 0U, // CMP16mr + 0U, // CMP16ri + 0U, // CMP16ri8 + 0U, // CMP16rm + 0U, // CMP16rr + 0U, // CMP16rr_REV + 0U, // CMP32i32 + 0U, // CMP32mi + 0U, // CMP32mi8 + 0U, // CMP32mr + 0U, // CMP32ri + 0U, // CMP32ri8 + 0U, // CMP32rm + 0U, // CMP32rr + 0U, // CMP32rr_REV + 0U, // CMP64i32 + 0U, // CMP64mi32 + 0U, // CMP64mi8 + 0U, // CMP64mr + 0U, // CMP64ri32 + 0U, // CMP64ri8 + 0U, // CMP64rm + 0U, // CMP64rr + 0U, // CMP64rr_REV + 0U, // CMP8i8 + 0U, // CMP8mi + 0U, // CMP8mi8 + 0U, // CMP8mr + 0U, // CMP8ri + 0U, // CMP8ri8 + 0U, // CMP8rm + 0U, // CMP8rr + 0U, // CMP8rr_REV + 4U, // CMPPDrmi + 0U, // CMPPDrmi_alt + 4U, // CMPPDrri + 4U, // CMPPDrri_alt + 4U, // CMPPSrmi + 0U, // CMPPSrmi_alt + 4U, // CMPPSrri + 4U, // CMPPSrri_alt + 0U, // CMPSB + 72U, // CMPSDrm + 72U, // CMPSDrm_Int + 4U, // CMPSDrm_alt + 4U, // CMPSDrr + 4U, // CMPSDrr_Int + 4U, // CMPSDrr_alt + 0U, // CMPSL + 0U, // CMPSQ + 72U, // CMPSSrm + 72U, // CMPSSrm_Int + 4U, // CMPSSrm_alt + 4U, // CMPSSrr + 4U, // CMPSSrr_Int + 4U, // CMPSSrr_alt + 0U, // CMPSW + 0U, // CMPXCHG16B + 0U, // CMPXCHG16rm + 0U, // CMPXCHG16rr + 0U, // CMPXCHG32rm + 0U, // CMPXCHG32rr + 0U, // CMPXCHG64rm + 0U, // CMPXCHG64rr + 0U, // CMPXCHG8B + 0U, // CMPXCHG8rm + 0U, // CMPXCHG8rr + 0U, // COMISDrm + 0U, // COMISDrm_Int + 0U, // COMISDrr + 0U, // COMISDrr_Int + 0U, // COMISSrm + 0U, // COMISSrm_Int + 0U, // COMISSrr + 0U, // COMISSrr_Int + 0U, // COMP_FST0r + 0U, // COM_FIPr + 0U, // COM_FIr + 0U, // COM_FST0r + 0U, // COS_F + 0U, // COS_Fp32 + 0U, // COS_Fp64 + 0U, // COS_Fp80 + 0U, // CPUID + 0U, // CQO + 0U, // CRC32r32m16 + 0U, // CRC32r32m32 + 0U, // CRC32r32m8 + 0U, // CRC32r32r16 + 0U, // CRC32r32r32 + 0U, // CRC32r32r8 + 0U, // CRC32r64m64 + 0U, // CRC32r64m8 + 0U, // CRC32r64r64 + 0U, // CRC32r64r8 + 0U, // CVTDQ2PDrm + 0U, // CVTDQ2PDrr + 0U, // CVTDQ2PSrm + 0U, // CVTDQ2PSrr + 0U, // CVTPD2DQrm + 0U, // CVTPD2DQrr + 0U, // CVTPD2PSrm + 0U, // CVTPD2PSrr + 0U, // CVTPS2DQrm + 0U, // CVTPS2DQrr + 0U, // CVTPS2PDrm + 0U, // CVTPS2PDrr + 0U, // CVTSD2SI64rm_Int + 0U, // CVTSD2SI64rr_Int + 0U, // CVTSD2SIrm_Int + 0U, // CVTSD2SIrr_Int + 0U, // CVTSD2SSrm + 0U, // CVTSD2SSrm_Int + 0U, // CVTSD2SSrr + 0U, // CVTSD2SSrr_Int + 0U, // CVTSI2SDrm + 0U, // CVTSI2SDrm_Int + 0U, // CVTSI2SDrr + 0U, // CVTSI2SDrr_Int + 0U, // CVTSI2SSrm + 0U, // CVTSI2SSrm_Int + 0U, // CVTSI2SSrr + 0U, // CVTSI2SSrr_Int + 0U, // CVTSI642SDrm + 0U, // CVTSI642SDrm_Int + 0U, // CVTSI642SDrr + 0U, // CVTSI642SDrr_Int + 0U, // CVTSI642SSrm + 0U, // CVTSI642SSrm_Int + 0U, // CVTSI642SSrr + 0U, // CVTSI642SSrr_Int + 0U, // CVTSS2SDrm + 0U, // CVTSS2SDrm_Int + 0U, // CVTSS2SDrr + 0U, // CVTSS2SDrr_Int + 0U, // CVTSS2SI64rm_Int + 0U, // CVTSS2SI64rr_Int + 0U, // CVTSS2SIrm_Int + 0U, // CVTSS2SIrr_Int + 0U, // CVTTPD2DQrm + 0U, // CVTTPD2DQrr + 0U, // CVTTPS2DQrm + 0U, // CVTTPS2DQrr + 0U, // CVTTSD2SI64rm + 0U, // CVTTSD2SI64rm_Int + 0U, // CVTTSD2SI64rr + 0U, // CVTTSD2SI64rr_Int + 0U, // CVTTSD2SIrm + 0U, // CVTTSD2SIrm_Int + 0U, // CVTTSD2SIrr + 0U, // CVTTSD2SIrr_Int + 0U, // CVTTSS2SI64rm + 0U, // CVTTSS2SI64rm_Int + 0U, // CVTTSS2SI64rr + 0U, // CVTTSS2SI64rr_Int + 0U, // CVTTSS2SIrm + 0U, // CVTTSS2SIrm_Int + 0U, // CVTTSS2SIrr + 0U, // CVTTSS2SIrr_Int + 0U, // CWD + 0U, // CWDE + 0U, // DAA + 0U, // DAS + 0U, // DATA16_PREFIX + 0U, // DEC16m + 0U, // DEC16r + 0U, // DEC16r_alt + 0U, // DEC32m + 0U, // DEC32r + 0U, // DEC32r_alt + 0U, // DEC64m + 0U, // DEC64r + 0U, // DEC8m + 0U, // DEC8r + 0U, // DIV16m + 0U, // DIV16r + 0U, // DIV32m + 0U, // DIV32r + 0U, // DIV64m + 0U, // DIV64r + 0U, // DIV8m + 0U, // DIV8r + 0U, // DIVPDrm + 0U, // DIVPDrr + 0U, // DIVPSrm + 0U, // DIVPSrr + 0U, // DIVR_F32m + 0U, // DIVR_F64m + 0U, // DIVR_FI16m + 0U, // DIVR_FI32m + 0U, // DIVR_FPrST0 + 0U, // DIVR_FST0r + 0U, // DIVR_Fp32m + 0U, // DIVR_Fp64m + 0U, // DIVR_Fp64m32 + 0U, // DIVR_Fp80m32 + 0U, // DIVR_Fp80m64 + 0U, // DIVR_FpI16m32 + 0U, // DIVR_FpI16m64 + 0U, // DIVR_FpI16m80 + 0U, // DIVR_FpI32m32 + 0U, // DIVR_FpI32m64 + 0U, // DIVR_FpI32m80 + 0U, // DIVR_FrST0 + 0U, // DIVSDrm + 0U, // DIVSDrm_Int + 0U, // DIVSDrr + 0U, // DIVSDrr_Int + 0U, // DIVSSrm + 0U, // DIVSSrm_Int + 0U, // DIVSSrr + 0U, // DIVSSrr_Int + 0U, // DIV_F32m + 0U, // DIV_F64m + 0U, // DIV_FI16m + 0U, // DIV_FI32m + 0U, // DIV_FPrST0 + 0U, // DIV_FST0r + 0U, // DIV_Fp32 + 0U, // DIV_Fp32m + 0U, // DIV_Fp64 + 0U, // DIV_Fp64m + 0U, // DIV_Fp64m32 + 0U, // DIV_Fp80 + 0U, // DIV_Fp80m32 + 0U, // DIV_Fp80m64 + 0U, // DIV_FpI16m32 + 0U, // DIV_FpI16m64 + 0U, // DIV_FpI16m80 + 0U, // DIV_FpI32m32 + 0U, // DIV_FpI32m64 + 0U, // DIV_FpI32m80 + 0U, // DIV_FrST0 + 0U, // DPPDrmi + 4U, // DPPDrri + 0U, // DPPSrmi + 4U, // DPPSrri + 0U, // ENCLS + 0U, // ENCLU + 0U, // ENCLV + 0U, // ENDBR32 + 0U, // ENDBR64 + 0U, // ENTER + 0U, // EXTRACTPSmr + 72U, // EXTRACTPSrr + 0U, // EXTRQ + 0U, // EXTRQI + 0U, // F2XM1 + 0U, // FARCALL16i + 0U, // FARCALL16m + 0U, // FARCALL32i + 0U, // FARCALL32m + 0U, // FARCALL64 + 0U, // FARJMP16i + 0U, // FARJMP16m + 0U, // FARJMP32i + 0U, // FARJMP32m + 0U, // FARJMP64 + 0U, // FBLDm + 0U, // FBSTPm + 0U, // FCOM32m + 0U, // FCOM64m + 0U, // FCOMP32m + 0U, // FCOMP64m + 0U, // FCOMPP + 0U, // FDECSTP + 0U, // FDISI8087_NOP + 0U, // FEMMS + 0U, // FENI8087_NOP + 0U, // FFREE + 0U, // FFREEP + 0U, // FICOM16m + 0U, // FICOM32m + 0U, // FICOMP16m + 0U, // FICOMP32m + 0U, // FINCSTP + 0U, // FLDCW16m + 0U, // FLDENVm + 0U, // FLDL2E + 0U, // FLDL2T + 0U, // FLDLG2 + 0U, // FLDLN2 + 0U, // FLDPI + 0U, // FNCLEX + 0U, // FNINIT + 0U, // FNOP + 0U, // FNSTCW16m + 0U, // FNSTSW16r + 0U, // FNSTSWm + 0U, // FPATAN + 0U, // FPNCEST0r + 0U, // FPREM + 0U, // FPREM1 + 0U, // FPTAN + 0U, // FRNDINT + 0U, // FRSTORm + 0U, // FSAVEm + 0U, // FSCALE + 0U, // FSETPM + 0U, // FSINCOS + 0U, // FSTENVm + 0U, // FXAM + 0U, // FXRSTOR + 0U, // FXRSTOR64 + 0U, // FXSAVE + 0U, // FXSAVE64 + 0U, // FXTRACT + 0U, // FYL2X + 0U, // FYL2XP1 + 0U, // GETSEC + 0U, // GF2P8AFFINEINVQBrmi + 4U, // GF2P8AFFINEINVQBrri + 0U, // GF2P8AFFINEQBrmi + 4U, // GF2P8AFFINEQBrri + 0U, // GF2P8MULBrm + 0U, // GF2P8MULBrr + 0U, // HADDPDrm + 0U, // HADDPDrr + 0U, // HADDPSrm + 0U, // HADDPSrr + 0U, // HLT + 0U, // HSUBPDrm + 0U, // HSUBPDrr + 0U, // HSUBPSrm + 0U, // HSUBPSrr + 0U, // IDIV16m + 0U, // IDIV16r + 0U, // IDIV32m + 0U, // IDIV32r + 0U, // IDIV64m + 0U, // IDIV64r + 0U, // IDIV8m + 0U, // IDIV8r + 0U, // ILD_F16m + 0U, // ILD_F32m + 0U, // ILD_F64m + 0U, // ILD_Fp16m32 + 0U, // ILD_Fp16m64 + 0U, // ILD_Fp16m80 + 0U, // ILD_Fp32m32 + 0U, // ILD_Fp32m64 + 0U, // ILD_Fp32m80 + 0U, // ILD_Fp64m32 + 0U, // ILD_Fp64m64 + 0U, // ILD_Fp64m80 + 0U, // IMUL16m + 0U, // IMUL16r + 0U, // IMUL16rm + 0U, // IMUL16rmi + 0U, // IMUL16rmi8 + 0U, // IMUL16rr + 4U, // IMUL16rri + 4U, // IMUL16rri8 + 0U, // IMUL32m + 0U, // IMUL32r + 0U, // IMUL32rm + 4U, // IMUL32rmi + 4U, // IMUL32rmi8 + 0U, // IMUL32rr + 4U, // IMUL32rri + 4U, // IMUL32rri8 + 0U, // IMUL64m + 0U, // IMUL64r + 0U, // IMUL64rm + 4U, // IMUL64rmi32 + 4U, // IMUL64rmi8 + 0U, // IMUL64rr + 4U, // IMUL64rri32 + 4U, // IMUL64rri8 + 0U, // IMUL8m + 0U, // IMUL8r + 0U, // IN16ri + 0U, // IN16rr + 0U, // IN32ri + 0U, // IN32rr + 0U, // IN8ri + 0U, // IN8rr + 0U, // INC16m + 0U, // INC16r + 0U, // INC16r_alt + 0U, // INC32m + 0U, // INC32r + 0U, // INC32r_alt + 0U, // INC64m + 0U, // INC64r + 0U, // INC8m + 0U, // INC8r + 0U, // INCSSPD + 0U, // INCSSPQ + 0U, // INSB + 4U, // INSERTPSrm + 4U, // INSERTPSrr + 0U, // INSERTQ + 1U, // INSERTQI + 0U, // INSL + 0U, // INSW + 0U, // INT + 0U, // INT1 + 0U, // INT3 + 0U, // INTO + 0U, // INVD + 0U, // INVEPT32 + 0U, // INVEPT64 + 0U, // INVLPG + 0U, // INVLPGA32 + 0U, // INVLPGA64 + 0U, // INVPCID32 + 0U, // INVPCID64 + 0U, // INVVPID32 + 0U, // INVVPID64 + 0U, // IRET16 + 0U, // IRET32 + 0U, // IRET64 + 0U, // ISTT_FP16m + 0U, // ISTT_FP32m + 0U, // ISTT_FP64m + 0U, // ISTT_Fp16m32 + 0U, // ISTT_Fp16m64 + 0U, // ISTT_Fp16m80 + 0U, // ISTT_Fp32m32 + 0U, // ISTT_Fp32m64 + 0U, // ISTT_Fp32m80 + 0U, // ISTT_Fp64m32 + 0U, // ISTT_Fp64m64 + 0U, // ISTT_Fp64m80 + 0U, // IST_F16m + 0U, // IST_F32m + 0U, // IST_FP16m + 0U, // IST_FP32m + 0U, // IST_FP64m + 0U, // IST_Fp16m32 + 0U, // IST_Fp16m64 + 0U, // IST_Fp16m80 + 0U, // IST_Fp32m32 + 0U, // IST_Fp32m64 + 0U, // IST_Fp32m80 + 0U, // IST_Fp64m32 + 0U, // IST_Fp64m64 + 0U, // IST_Fp64m80 + 0U, // JAE_1 + 0U, // JAE_2 + 0U, // JAE_4 + 0U, // JA_1 + 0U, // JA_2 + 0U, // JA_4 + 0U, // JBE_1 + 0U, // JBE_2 + 0U, // JBE_4 + 0U, // JB_1 + 0U, // JB_2 + 0U, // JB_4 + 0U, // JCXZ + 0U, // JECXZ + 0U, // JE_1 + 0U, // JE_2 + 0U, // JE_4 + 0U, // JGE_1 + 0U, // JGE_2 + 0U, // JGE_4 + 0U, // JG_1 + 0U, // JG_2 + 0U, // JG_4 + 0U, // JLE_1 + 0U, // JLE_2 + 0U, // JLE_4 + 0U, // JL_1 + 0U, // JL_2 + 0U, // JL_4 + 0U, // JMP16m + 0U, // JMP16m_NT + 0U, // JMP16r + 0U, // JMP16r_NT + 0U, // JMP32m + 0U, // JMP32m_NT + 0U, // JMP32r + 0U, // JMP32r_NT + 0U, // JMP64m + 0U, // JMP64m_NT + 0U, // JMP64r + 0U, // JMP64r_NT + 0U, // JMP_1 + 0U, // JMP_2 + 0U, // JMP_4 + 0U, // JNE_1 + 0U, // JNE_2 + 0U, // JNE_4 + 0U, // JNO_1 + 0U, // JNO_2 + 0U, // JNO_4 + 0U, // JNP_1 + 0U, // JNP_2 + 0U, // JNP_4 + 0U, // JNS_1 + 0U, // JNS_2 + 0U, // JNS_4 + 0U, // JO_1 + 0U, // JO_2 + 0U, // JO_4 + 0U, // JP_1 + 0U, // JP_2 + 0U, // JP_4 + 0U, // JRCXZ + 0U, // JS_1 + 0U, // JS_2 + 0U, // JS_4 + 4U, // KADDBrr + 4U, // KADDDrr + 4U, // KADDQrr + 4U, // KADDWrr + 4U, // KANDBrr + 4U, // KANDDrr + 4U, // KANDNBrr + 4U, // KANDNDrr + 4U, // KANDNQrr + 4U, // KANDNWrr + 4U, // KANDQrr + 4U, // KANDWrr + 0U, // KMOVBkk + 0U, // KMOVBkm + 0U, // KMOVBkr + 0U, // KMOVBmk + 0U, // KMOVBrk + 0U, // KMOVDkk + 0U, // KMOVDkm + 0U, // KMOVDkr + 0U, // KMOVDmk + 0U, // KMOVDrk + 0U, // KMOVQkk + 0U, // KMOVQkm + 0U, // KMOVQkr + 0U, // KMOVQmk + 0U, // KMOVQrk + 0U, // KMOVWkk + 0U, // KMOVWkm + 0U, // KMOVWkr + 0U, // KMOVWmk + 0U, // KMOVWrk + 0U, // KNOTBrr + 0U, // KNOTDrr + 0U, // KNOTQrr + 0U, // KNOTWrr + 4U, // KORBrr + 4U, // KORDrr + 4U, // KORQrr + 0U, // KORTESTBrr + 0U, // KORTESTDrr + 0U, // KORTESTQrr + 0U, // KORTESTWrr + 4U, // KORWrr + 72U, // KSHIFTLBri + 72U, // KSHIFTLDri + 72U, // KSHIFTLQri + 72U, // KSHIFTLWri + 72U, // KSHIFTRBri + 72U, // KSHIFTRDri + 72U, // KSHIFTRQri + 72U, // KSHIFTRWri + 0U, // KTESTBrr + 0U, // KTESTDrr + 0U, // KTESTQrr + 0U, // KTESTWrr + 4U, // KUNPCKBWrr + 4U, // KUNPCKDQrr + 4U, // KUNPCKWDrr + 4U, // KXNORBrr + 4U, // KXNORDrr + 4U, // KXNORQrr + 4U, // KXNORWrr + 4U, // KXORBrr + 4U, // KXORDrr + 4U, // KXORQrr + 4U, // KXORWrr + 0U, // LAHF + 0U, // LAR16rm + 0U, // LAR16rr + 0U, // LAR32rm + 0U, // LAR32rr + 0U, // LAR64rm + 0U, // LAR64rr + 0U, // LDDQUrm + 0U, // LDMXCSR + 0U, // LDS16rm + 0U, // LDS32rm + 0U, // LD_F0 + 0U, // LD_F1 + 0U, // LD_F32m + 0U, // LD_F64m + 0U, // LD_F80m + 0U, // LD_Fp032 + 0U, // LD_Fp064 + 0U, // LD_Fp080 + 0U, // LD_Fp132 + 0U, // LD_Fp164 + 0U, // LD_Fp180 + 0U, // LD_Fp32m + 0U, // LD_Fp32m64 + 0U, // LD_Fp32m80 + 0U, // LD_Fp64m + 0U, // LD_Fp64m80 + 0U, // LD_Fp80m + 0U, // LD_Frr + 0U, // LEA16r + 0U, // LEA32r + 0U, // LEA64_32r + 0U, // LEA64r + 0U, // LEAVE + 0U, // LEAVE64 + 0U, // LES16rm + 0U, // LES32rm + 0U, // LFENCE + 0U, // LFS16rm + 0U, // LFS32rm + 0U, // LFS64rm + 0U, // LGDT16m + 0U, // LGDT32m + 0U, // LGDT64m + 0U, // LGS16rm + 0U, // LGS32rm + 0U, // LGS64rm + 0U, // LIDT16m + 0U, // LIDT32m + 0U, // LIDT64m + 0U, // LLDT16m + 0U, // LLDT16r + 0U, // LLWPCB + 0U, // LLWPCB64 + 0U, // LMSW16m + 0U, // LMSW16r + 0U, // LOCK_PREFIX + 0U, // LODSB + 0U, // LODSL + 0U, // LODSQ + 0U, // LODSW + 0U, // LOOP + 0U, // LOOPE + 0U, // LOOPNE + 0U, // LRETIL + 0U, // LRETIQ + 0U, // LRETIW + 0U, // LRETL + 0U, // LRETQ + 0U, // LRETW + 0U, // LSL16rm + 0U, // LSL16rr + 0U, // LSL32rm + 0U, // LSL32rr + 0U, // LSL64rm + 0U, // LSL64rr + 0U, // LSS16rm + 0U, // LSS32rm + 0U, // LSS64rm + 0U, // LTRm + 0U, // LTRr + 4U, // LWPINS32rmi + 4U, // LWPINS32rri + 4U, // LWPINS64rmi + 4U, // LWPINS64rri + 4U, // LWPVAL32rmi + 4U, // LWPVAL32rri + 4U, // LWPVAL64rmi + 4U, // LWPVAL64rri + 0U, // LZCNT16rm + 0U, // LZCNT16rr + 0U, // LZCNT32rm + 0U, // LZCNT32rr + 0U, // LZCNT64rm + 0U, // LZCNT64rr + 0U, // MASKMOVDQU + 0U, // MASKMOVDQU64 + 0U, // MAXCPDrm + 0U, // MAXCPDrr + 0U, // MAXCPSrm + 0U, // MAXCPSrr + 0U, // MAXCSDrm + 0U, // MAXCSDrr + 0U, // MAXCSSrm + 0U, // MAXCSSrr + 0U, // MAXPDrm + 0U, // MAXPDrr + 0U, // MAXPSrm + 0U, // MAXPSrr + 0U, // MAXSDrm + 0U, // MAXSDrm_Int + 0U, // MAXSDrr + 0U, // MAXSDrr_Int + 0U, // MAXSSrm + 0U, // MAXSSrm_Int + 0U, // MAXSSrr + 0U, // MAXSSrr_Int + 0U, // MFENCE + 0U, // MINCPDrm + 0U, // MINCPDrr + 0U, // MINCPSrm + 0U, // MINCPSrr + 0U, // MINCSDrm + 0U, // MINCSDrr + 0U, // MINCSSrm + 0U, // MINCSSrr + 0U, // MINPDrm + 0U, // MINPDrr + 0U, // MINPSrm + 0U, // MINPSrr + 0U, // MINSDrm + 0U, // MINSDrm_Int + 0U, // MINSDrr + 0U, // MINSDrr_Int + 0U, // MINSSrm + 0U, // MINSSrm_Int + 0U, // MINSSrr + 0U, // MINSSrr_Int + 0U, // MMX_CVTPD2PIirm + 0U, // MMX_CVTPD2PIirr + 0U, // MMX_CVTPI2PDirm + 0U, // MMX_CVTPI2PDirr + 0U, // MMX_CVTPI2PSirm + 0U, // MMX_CVTPI2PSirr + 0U, // MMX_CVTPS2PIirm + 0U, // MMX_CVTPS2PIirr + 0U, // MMX_CVTTPD2PIirm + 0U, // MMX_CVTTPD2PIirr + 0U, // MMX_CVTTPS2PIirm + 0U, // MMX_CVTTPS2PIirr + 0U, // MMX_EMMS + 0U, // MMX_MASKMOVQ + 0U, // MMX_MASKMOVQ64 + 0U, // MMX_MOVD64from64rm + 0U, // MMX_MOVD64from64rr + 0U, // MMX_MOVD64grr + 0U, // MMX_MOVD64mr + 0U, // MMX_MOVD64rm + 0U, // MMX_MOVD64rr + 0U, // MMX_MOVD64to64rm + 0U, // MMX_MOVD64to64rr + 0U, // MMX_MOVDQ2Qrr + 0U, // MMX_MOVFR642Qrr + 0U, // MMX_MOVNTQmr + 0U, // MMX_MOVQ2DQrr + 0U, // MMX_MOVQ2FR64rr + 0U, // MMX_MOVQ64mr + 0U, // MMX_MOVQ64rm + 0U, // MMX_MOVQ64rr + 0U, // MMX_MOVQ64rr_REV + 0U, // MMX_PABSBrm + 0U, // MMX_PABSBrr + 0U, // MMX_PABSDrm + 0U, // MMX_PABSDrr + 0U, // MMX_PABSWrm + 0U, // MMX_PABSWrr + 0U, // MMX_PACKSSDWirm + 0U, // MMX_PACKSSDWirr + 0U, // MMX_PACKSSWBirm + 0U, // MMX_PACKSSWBirr + 0U, // MMX_PACKUSWBirm + 0U, // MMX_PACKUSWBirr + 0U, // MMX_PADDBirm + 0U, // MMX_PADDBirr + 0U, // MMX_PADDDirm + 0U, // MMX_PADDDirr + 0U, // MMX_PADDQirm + 0U, // MMX_PADDQirr + 0U, // MMX_PADDSBirm + 0U, // MMX_PADDSBirr + 0U, // MMX_PADDSWirm + 0U, // MMX_PADDSWirr + 0U, // MMX_PADDUSBirm + 0U, // MMX_PADDUSBirr + 0U, // MMX_PADDUSWirm + 0U, // MMX_PADDUSWirr + 0U, // MMX_PADDWirm + 0U, // MMX_PADDWirr + 4U, // MMX_PALIGNRrmi + 4U, // MMX_PALIGNRrri + 0U, // MMX_PANDNirm + 0U, // MMX_PANDNirr + 0U, // MMX_PANDirm + 0U, // MMX_PANDirr + 0U, // MMX_PAVGBirm + 0U, // MMX_PAVGBirr + 0U, // MMX_PAVGWirm + 0U, // MMX_PAVGWirr + 0U, // MMX_PCMPEQBirm + 0U, // MMX_PCMPEQBirr + 0U, // MMX_PCMPEQDirm + 0U, // MMX_PCMPEQDirr + 0U, // MMX_PCMPEQWirm + 0U, // MMX_PCMPEQWirr + 0U, // MMX_PCMPGTBirm + 0U, // MMX_PCMPGTBirr + 0U, // MMX_PCMPGTDirm + 0U, // MMX_PCMPGTDirr + 0U, // MMX_PCMPGTWirm + 0U, // MMX_PCMPGTWirr + 72U, // MMX_PEXTRWrr + 0U, // MMX_PHADDDrm + 0U, // MMX_PHADDDrr + 0U, // MMX_PHADDSWrm + 0U, // MMX_PHADDSWrr + 0U, // MMX_PHADDWrm + 0U, // MMX_PHADDWrr + 0U, // MMX_PHSUBDrm + 0U, // MMX_PHSUBDrr + 0U, // MMX_PHSUBSWrm + 0U, // MMX_PHSUBSWrr + 0U, // MMX_PHSUBWrm + 0U, // MMX_PHSUBWrr + 0U, // MMX_PINSRWrm + 4U, // MMX_PINSRWrr + 0U, // MMX_PMADDUBSWrm + 0U, // MMX_PMADDUBSWrr + 0U, // MMX_PMADDWDirm + 0U, // MMX_PMADDWDirr + 0U, // MMX_PMAXSWirm + 0U, // MMX_PMAXSWirr + 0U, // MMX_PMAXUBirm + 0U, // MMX_PMAXUBirr + 0U, // MMX_PMINSWirm + 0U, // MMX_PMINSWirr + 0U, // MMX_PMINUBirm + 0U, // MMX_PMINUBirr + 0U, // MMX_PMOVMSKBrr + 0U, // MMX_PMULHRSWrm + 0U, // MMX_PMULHRSWrr + 0U, // MMX_PMULHUWirm + 0U, // MMX_PMULHUWirr + 0U, // MMX_PMULHWirm + 0U, // MMX_PMULHWirr + 0U, // MMX_PMULLWirm + 0U, // MMX_PMULLWirr + 0U, // MMX_PMULUDQirm + 0U, // MMX_PMULUDQirr + 0U, // MMX_PORirm + 0U, // MMX_PORirr + 0U, // MMX_PSADBWirm + 0U, // MMX_PSADBWirr + 0U, // MMX_PSHUFBrm + 0U, // MMX_PSHUFBrr + 4U, // MMX_PSHUFWmi + 72U, // MMX_PSHUFWri + 0U, // MMX_PSIGNBrm + 0U, // MMX_PSIGNBrr + 0U, // MMX_PSIGNDrm + 0U, // MMX_PSIGNDrr + 0U, // MMX_PSIGNWrm + 0U, // MMX_PSIGNWrr + 0U, // MMX_PSLLDri + 0U, // MMX_PSLLDrm + 0U, // MMX_PSLLDrr + 0U, // MMX_PSLLQri + 0U, // MMX_PSLLQrm + 0U, // MMX_PSLLQrr + 0U, // MMX_PSLLWri + 0U, // MMX_PSLLWrm + 0U, // MMX_PSLLWrr + 0U, // MMX_PSRADri + 0U, // MMX_PSRADrm + 0U, // MMX_PSRADrr + 0U, // MMX_PSRAWri + 0U, // MMX_PSRAWrm + 0U, // MMX_PSRAWrr + 0U, // MMX_PSRLDri + 0U, // MMX_PSRLDrm + 0U, // MMX_PSRLDrr + 0U, // MMX_PSRLQri + 0U, // MMX_PSRLQrm + 0U, // MMX_PSRLQrr + 0U, // MMX_PSRLWri + 0U, // MMX_PSRLWrm + 0U, // MMX_PSRLWrr + 0U, // MMX_PSUBBirm + 0U, // MMX_PSUBBirr + 0U, // MMX_PSUBDirm + 0U, // MMX_PSUBDirr + 0U, // MMX_PSUBQirm + 0U, // MMX_PSUBQirr + 0U, // MMX_PSUBSBirm + 0U, // MMX_PSUBSBirr + 0U, // MMX_PSUBSWirm + 0U, // MMX_PSUBSWirr + 0U, // MMX_PSUBUSBirm + 0U, // MMX_PSUBUSBirr + 0U, // MMX_PSUBUSWirm + 0U, // MMX_PSUBUSWirr + 0U, // MMX_PSUBWirm + 0U, // MMX_PSUBWirr + 0U, // MMX_PUNPCKHBWirm + 0U, // MMX_PUNPCKHBWirr + 0U, // MMX_PUNPCKHDQirm + 0U, // MMX_PUNPCKHDQirr + 0U, // MMX_PUNPCKHWDirm + 0U, // MMX_PUNPCKHWDirr + 0U, // MMX_PUNPCKLBWirm + 0U, // MMX_PUNPCKLBWirr + 0U, // MMX_PUNPCKLDQirm + 0U, // MMX_PUNPCKLDQirr + 0U, // MMX_PUNPCKLWDirm + 0U, // MMX_PUNPCKLWDirr + 0U, // MMX_PXORirm + 0U, // MMX_PXORirr + 0U, // MONITORXrrr + 0U, // MONITORrrr + 0U, // MONTMUL + 0U, // MOV16ao16 + 0U, // MOV16ao32 + 0U, // MOV16ao64 + 0U, // MOV16mi + 0U, // MOV16mr + 0U, // MOV16ms + 0U, // MOV16o16a + 0U, // MOV16o32a + 0U, // MOV16o64a + 0U, // MOV16ri + 0U, // MOV16ri_alt + 0U, // MOV16rm + 0U, // MOV16rr + 0U, // MOV16rr_REV + 0U, // MOV16rs + 0U, // MOV16sm + 0U, // MOV16sr + 0U, // MOV32ao16 + 0U, // MOV32ao32 + 0U, // MOV32ao64 + 0U, // MOV32cr + 0U, // MOV32dr + 0U, // MOV32mi + 0U, // MOV32mr + 0U, // MOV32o16a + 0U, // MOV32o32a + 0U, // MOV32o64a + 0U, // MOV32rc + 0U, // MOV32rd + 0U, // MOV32ri + 0U, // MOV32ri_alt + 0U, // MOV32rm + 0U, // MOV32rr + 0U, // MOV32rr_REV + 0U, // MOV32rs + 0U, // MOV32sr + 0U, // MOV64ao32 + 0U, // MOV64ao64 + 0U, // MOV64cr + 0U, // MOV64dr + 0U, // MOV64mi32 + 0U, // MOV64mr + 0U, // MOV64o32a + 0U, // MOV64o64a + 0U, // MOV64rc + 0U, // MOV64rd + 0U, // MOV64ri + 0U, // MOV64ri32 + 0U, // MOV64rm + 0U, // MOV64rr + 0U, // MOV64rr_REV + 0U, // MOV64rs + 0U, // MOV64sr + 0U, // MOV64toPQIrm + 0U, // MOV64toPQIrr + 0U, // MOV64toSDrm + 0U, // MOV64toSDrr + 0U, // MOV8ao16 + 0U, // MOV8ao32 + 0U, // MOV8ao64 + 0U, // MOV8mi + 0U, // MOV8mr + 0U, // MOV8mr_NOREX + 0U, // MOV8o16a + 0U, // MOV8o32a + 0U, // MOV8o64a + 0U, // MOV8ri + 0U, // MOV8ri_alt + 0U, // MOV8rm + 0U, // MOV8rm_NOREX + 0U, // MOV8rr + 0U, // MOV8rr_NOREX + 0U, // MOV8rr_REV + 0U, // MOVAPDmr + 0U, // MOVAPDrm + 0U, // MOVAPDrr + 0U, // MOVAPDrr_REV + 0U, // MOVAPSmr + 0U, // MOVAPSrm + 0U, // MOVAPSrr + 0U, // MOVAPSrr_REV + 0U, // MOVBE16mr + 0U, // MOVBE16rm + 0U, // MOVBE32mr + 0U, // MOVBE32rm + 0U, // MOVBE64mr + 0U, // MOVBE64rm + 0U, // MOVDDUPrm + 0U, // MOVDDUPrr + 0U, // MOVDI2PDIrm + 0U, // MOVDI2PDIrr + 0U, // MOVDI2SSrm + 0U, // MOVDI2SSrr + 0U, // MOVDIR64B16 + 0U, // MOVDIR64B32 + 0U, // MOVDIR64B64 + 0U, // MOVDIRI32 + 0U, // MOVDIRI64 + 0U, // MOVDQAmr + 0U, // MOVDQArm + 0U, // MOVDQArr + 0U, // MOVDQArr_REV + 0U, // MOVDQUmr + 0U, // MOVDQUrm + 0U, // MOVDQUrr + 0U, // MOVDQUrr_REV + 0U, // MOVHLPSrr + 0U, // MOVHPDmr + 0U, // MOVHPDrm + 0U, // MOVHPSmr + 0U, // MOVHPSrm + 0U, // MOVLHPSrr + 0U, // MOVLPDmr + 0U, // MOVLPDrm + 0U, // MOVLPSmr + 0U, // MOVLPSrm + 0U, // MOVMSKPDrr + 0U, // MOVMSKPSrr + 0U, // MOVNTDQArm + 0U, // MOVNTDQmr + 0U, // MOVNTI_64mr + 0U, // MOVNTImr + 0U, // MOVNTPDmr + 0U, // MOVNTPSmr + 0U, // MOVNTSD + 0U, // MOVNTSS + 0U, // MOVPDI2DImr + 0U, // MOVPDI2DIrr + 0U, // MOVPQI2QImr + 0U, // MOVPQI2QIrr + 0U, // MOVPQIto64mr + 0U, // MOVPQIto64rr + 0U, // MOVQI2PQIrm + 0U, // MOVSB + 0U, // MOVSDmr + 0U, // MOVSDrm + 0U, // MOVSDrr + 0U, // MOVSDrr_REV + 0U, // MOVSDto64mr + 0U, // MOVSDto64rr + 0U, // MOVSHDUPrm + 0U, // MOVSHDUPrr + 0U, // MOVSL + 0U, // MOVSLDUPrm + 0U, // MOVSLDUPrr + 0U, // MOVSQ + 0U, // MOVSS2DImr + 0U, // MOVSS2DIrr + 0U, // MOVSSmr + 0U, // MOVSSrm + 0U, // MOVSSrr + 0U, // MOVSSrr_REV + 0U, // MOVSW + 0U, // MOVSX16rm16 + 0U, // MOVSX16rm8 + 0U, // MOVSX16rr16 + 0U, // MOVSX16rr8 + 0U, // MOVSX32rm16 + 0U, // MOVSX32rm8 + 0U, // MOVSX32rm8_NOREX + 0U, // MOVSX32rr16 + 0U, // MOVSX32rr8 + 0U, // MOVSX32rr8_NOREX + 0U, // MOVSX64rm16 + 0U, // MOVSX64rm32 + 0U, // MOVSX64rm8 + 0U, // MOVSX64rr16 + 0U, // MOVSX64rr32 + 0U, // MOVSX64rr8 + 0U, // MOVUPDmr + 0U, // MOVUPDrm + 0U, // MOVUPDrr + 0U, // MOVUPDrr_REV + 0U, // MOVUPSmr + 0U, // MOVUPSrm + 0U, // MOVUPSrr + 0U, // MOVUPSrr_REV + 0U, // MOVZPQILo2PQIrr + 0U, // MOVZX16rm16 + 0U, // MOVZX16rm8 + 0U, // MOVZX16rr16 + 0U, // MOVZX16rr8 + 0U, // MOVZX32rm16 + 0U, // MOVZX32rm8 + 0U, // MOVZX32rm8_NOREX + 0U, // MOVZX32rr16 + 0U, // MOVZX32rr8 + 0U, // MOVZX32rr8_NOREX + 0U, // MOVZX64rm16 + 0U, // MOVZX64rm8 + 0U, // MOVZX64rr16 + 0U, // MOVZX64rr8 + 0U, // MPSADBWrmi + 4U, // MPSADBWrri + 0U, // MUL16m + 0U, // MUL16r + 0U, // MUL32m + 0U, // MUL32r + 0U, // MUL64m + 0U, // MUL64r + 0U, // MUL8m + 0U, // MUL8r + 0U, // MULPDrm + 0U, // MULPDrr + 0U, // MULPSrm + 0U, // MULPSrr + 0U, // MULSDrm + 0U, // MULSDrm_Int + 0U, // MULSDrr + 0U, // MULSDrr_Int + 0U, // MULSSrm + 0U, // MULSSrm_Int + 0U, // MULSSrr + 0U, // MULSSrr_Int + 72U, // MULX32rm + 4U, // MULX32rr + 72U, // MULX64rm + 4U, // MULX64rr + 0U, // MUL_F32m + 0U, // MUL_F64m + 0U, // MUL_FI16m + 0U, // MUL_FI32m + 0U, // MUL_FPrST0 + 0U, // MUL_FST0r + 0U, // MUL_Fp32 + 0U, // MUL_Fp32m + 0U, // MUL_Fp64 + 0U, // MUL_Fp64m + 0U, // MUL_Fp64m32 + 0U, // MUL_Fp80 + 0U, // MUL_Fp80m32 + 0U, // MUL_Fp80m64 + 0U, // MUL_FpI16m32 + 0U, // MUL_FpI16m64 + 0U, // MUL_FpI16m80 + 0U, // MUL_FpI32m32 + 0U, // MUL_FpI32m64 + 0U, // MUL_FpI32m80 + 0U, // MUL_FrST0 + 0U, // MWAITXrrr + 0U, // MWAITrr + 0U, // NEG16m + 0U, // NEG16r + 0U, // NEG32m + 0U, // NEG32r + 0U, // NEG64m + 0U, // NEG64r + 0U, // NEG8m + 0U, // NEG8r + 0U, // NOOP + 0U, // NOOP18_16m4 + 0U, // NOOP18_16m5 + 0U, // NOOP18_16m6 + 0U, // NOOP18_16m7 + 0U, // NOOP18_16r4 + 0U, // NOOP18_16r5 + 0U, // NOOP18_16r6 + 0U, // NOOP18_16r7 + 0U, // NOOP18_m4 + 0U, // NOOP18_m5 + 0U, // NOOP18_m6 + 0U, // NOOP18_m7 + 0U, // NOOP18_r4 + 0U, // NOOP18_r5 + 0U, // NOOP18_r6 + 0U, // NOOP18_r7 + 0U, // NOOP19rr + 0U, // NOOPL + 0U, // NOOPL_19 + 0U, // NOOPL_1d + 0U, // NOOPL_1e + 0U, // NOOPLr + 0U, // NOOPQ + 0U, // NOOPQr + 0U, // NOOPW + 0U, // NOOPW_19 + 0U, // NOOPW_1c + 0U, // NOOPW_1d + 0U, // NOOPW_1e + 0U, // NOOPWr + 0U, // NOT16m + 0U, // NOT16r + 0U, // NOT32m + 0U, // NOT32r + 0U, // NOT64m + 0U, // NOT64r + 0U, // NOT8m + 0U, // NOT8r + 0U, // OR16i16 + 0U, // OR16mi + 0U, // OR16mi8 + 0U, // OR16mr + 0U, // OR16ri + 0U, // OR16ri8 + 0U, // OR16rm + 0U, // OR16rr + 0U, // OR16rr_REV + 0U, // OR32i32 + 0U, // OR32mi + 0U, // OR32mi8 + 0U, // OR32mr + 0U, // OR32ri + 0U, // OR32ri8 + 0U, // OR32rm + 0U, // OR32rr + 0U, // OR32rr_REV + 0U, // OR64i32 + 0U, // OR64mi32 + 0U, // OR64mi8 + 0U, // OR64mr + 0U, // OR64ri32 + 0U, // OR64ri8 + 0U, // OR64rm + 0U, // OR64rr + 0U, // OR64rr_REV + 0U, // OR8i8 + 0U, // OR8mi + 0U, // OR8mi8 + 0U, // OR8mr + 0U, // OR8ri + 0U, // OR8ri8 + 0U, // OR8rm + 0U, // OR8rr + 0U, // OR8rr_REV + 0U, // ORPDrm + 0U, // ORPDrr + 0U, // ORPSrm + 0U, // ORPSrr + 0U, // OUT16ir + 0U, // OUT16rr + 0U, // OUT32ir + 0U, // OUT32rr + 0U, // OUT8ir + 0U, // OUT8rr + 0U, // OUTSB + 0U, // OUTSL + 0U, // OUTSW + 0U, // PABSBrm + 0U, // PABSBrr + 0U, // PABSDrm + 0U, // PABSDrr + 0U, // PABSWrm + 0U, // PABSWrr + 0U, // PACKSSDWrm + 0U, // PACKSSDWrr + 0U, // PACKSSWBrm + 0U, // PACKSSWBrr + 0U, // PACKUSDWrm + 0U, // PACKUSDWrr + 0U, // PACKUSWBrm + 0U, // PACKUSWBrr + 0U, // PADDBrm + 0U, // PADDBrr + 0U, // PADDDrm + 0U, // PADDDrr + 0U, // PADDQrm + 0U, // PADDQrr + 0U, // PADDSBrm + 0U, // PADDSBrr + 0U, // PADDSWrm + 0U, // PADDSWrr + 0U, // PADDUSBrm + 0U, // PADDUSBrr + 0U, // PADDUSWrm + 0U, // PADDUSWrr + 0U, // PADDWrm + 0U, // PADDWrr + 0U, // PALIGNRrmi + 4U, // PALIGNRrri + 0U, // PANDNrm + 0U, // PANDNrr + 0U, // PANDrm + 0U, // PANDrr + 0U, // PAUSE + 0U, // PAVGBrm + 0U, // PAVGBrr + 0U, // PAVGUSBrm + 0U, // PAVGUSBrr + 0U, // PAVGWrm + 0U, // PAVGWrr + 0U, // PBLENDVBrm0 + 0U, // PBLENDVBrr0 + 0U, // PBLENDWrmi + 4U, // PBLENDWrri + 0U, // PCLMULQDQrm + 4U, // PCLMULQDQrr + 0U, // PCMPEQBrm + 0U, // PCMPEQBrr + 0U, // PCMPEQDrm + 0U, // PCMPEQDrr + 0U, // PCMPEQQrm + 0U, // PCMPEQQrr + 0U, // PCMPEQWrm + 0U, // PCMPEQWrr + 4U, // PCMPESTRIrm + 72U, // PCMPESTRIrr + 4U, // PCMPESTRMrm + 72U, // PCMPESTRMrr + 0U, // PCMPGTBrm + 0U, // PCMPGTBrr + 0U, // PCMPGTDrm + 0U, // PCMPGTDrr + 0U, // PCMPGTQrm + 0U, // PCMPGTQrr + 0U, // PCMPGTWrm + 0U, // PCMPGTWrr + 4U, // PCMPISTRIrm + 72U, // PCMPISTRIrr + 4U, // PCMPISTRMrm + 72U, // PCMPISTRMrr + 0U, // PCONFIG + 72U, // PDEP32rm + 4U, // PDEP32rr + 72U, // PDEP64rm + 4U, // PDEP64rr + 72U, // PEXT32rm + 4U, // PEXT32rr + 72U, // PEXT64rm + 4U, // PEXT64rr + 1U, // PEXTRBmr + 72U, // PEXTRBrr + 1U, // PEXTRDmr + 72U, // PEXTRDrr + 1U, // PEXTRQmr + 72U, // PEXTRQrr + 1U, // PEXTRWmr + 72U, // PEXTRWrr + 72U, // PEXTRWrr_REV + 0U, // PF2IDrm + 0U, // PF2IDrr + 0U, // PF2IWrm + 0U, // PF2IWrr + 0U, // PFACCrm + 0U, // PFACCrr + 0U, // PFADDrm + 0U, // PFADDrr + 0U, // PFCMPEQrm + 0U, // PFCMPEQrr + 0U, // PFCMPGErm + 0U, // PFCMPGErr + 0U, // PFCMPGTrm + 0U, // PFCMPGTrr + 0U, // PFMAXrm + 0U, // PFMAXrr + 0U, // PFMINrm + 0U, // PFMINrr + 0U, // PFMULrm + 0U, // PFMULrr + 0U, // PFNACCrm + 0U, // PFNACCrr + 0U, // PFPNACCrm + 0U, // PFPNACCrr + 0U, // PFRCPIT1rm + 0U, // PFRCPIT1rr + 0U, // PFRCPIT2rm + 0U, // PFRCPIT2rr + 0U, // PFRCPrm + 0U, // PFRCPrr + 0U, // PFRSQIT1rm + 0U, // PFRSQIT1rr + 0U, // PFRSQRTrm + 0U, // PFRSQRTrr + 0U, // PFSUBRrm + 0U, // PFSUBRrr + 0U, // PFSUBrm + 0U, // PFSUBrr + 0U, // PHADDDrm + 0U, // PHADDDrr + 0U, // PHADDSWrm + 0U, // PHADDSWrr + 0U, // PHADDWrm + 0U, // PHADDWrr + 0U, // PHMINPOSUWrm + 0U, // PHMINPOSUWrr + 0U, // PHSUBDrm + 0U, // PHSUBDrr + 0U, // PHSUBSWrm + 0U, // PHSUBSWrr + 0U, // PHSUBWrm + 0U, // PHSUBWrr + 0U, // PI2FDrm + 0U, // PI2FDrr + 0U, // PI2FWrm + 0U, // PI2FWrr + 4U, // PINSRBrm + 4U, // PINSRBrr + 4U, // PINSRDrm + 4U, // PINSRDrr + 4U, // PINSRQrm + 4U, // PINSRQrr + 0U, // PINSRWrm + 4U, // PINSRWrr + 0U, // PMADDUBSWrm + 0U, // PMADDUBSWrr + 0U, // PMADDWDrm + 0U, // PMADDWDrr + 0U, // PMAXSBrm + 0U, // PMAXSBrr + 0U, // PMAXSDrm + 0U, // PMAXSDrr + 0U, // PMAXSWrm + 0U, // PMAXSWrr + 0U, // PMAXUBrm + 0U, // PMAXUBrr + 0U, // PMAXUDrm + 0U, // PMAXUDrr + 0U, // PMAXUWrm + 0U, // PMAXUWrr + 0U, // PMINSBrm + 0U, // PMINSBrr + 0U, // PMINSDrm + 0U, // PMINSDrr + 0U, // PMINSWrm + 0U, // PMINSWrr + 0U, // PMINUBrm + 0U, // PMINUBrr + 0U, // PMINUDrm + 0U, // PMINUDrr + 0U, // PMINUWrm + 0U, // PMINUWrr + 0U, // PMOVMSKBrr + 0U, // PMOVSXBDrm + 0U, // PMOVSXBDrr + 0U, // PMOVSXBQrm + 0U, // PMOVSXBQrr + 0U, // PMOVSXBWrm + 0U, // PMOVSXBWrr + 0U, // PMOVSXDQrm + 0U, // PMOVSXDQrr + 0U, // PMOVSXWDrm + 0U, // PMOVSXWDrr + 0U, // PMOVSXWQrm + 0U, // PMOVSXWQrr + 0U, // PMOVZXBDrm + 0U, // PMOVZXBDrr + 0U, // PMOVZXBQrm + 0U, // PMOVZXBQrr + 0U, // PMOVZXBWrm + 0U, // PMOVZXBWrr + 0U, // PMOVZXDQrm + 0U, // PMOVZXDQrr + 0U, // PMOVZXWDrm + 0U, // PMOVZXWDrr + 0U, // PMOVZXWQrm + 0U, // PMOVZXWQrr + 0U, // PMULDQrm + 0U, // PMULDQrr + 0U, // PMULHRSWrm + 0U, // PMULHRSWrr + 0U, // PMULHRWrm + 0U, // PMULHRWrr + 0U, // PMULHUWrm + 0U, // PMULHUWrr + 0U, // PMULHWrm + 0U, // PMULHWrr + 0U, // PMULLDrm + 0U, // PMULLDrr + 0U, // PMULLWrm + 0U, // PMULLWrr + 0U, // PMULUDQrm + 0U, // PMULUDQrr + 0U, // POP16r + 0U, // POP16rmm + 0U, // POP16rmr + 0U, // POP32r + 0U, // POP32rmm + 0U, // POP32rmr + 0U, // POP64r + 0U, // POP64rmm + 0U, // POP64rmr + 0U, // POPA16 + 0U, // POPA32 + 0U, // POPCNT16rm + 0U, // POPCNT16rr + 0U, // POPCNT32rm + 0U, // POPCNT32rr + 0U, // POPCNT64rm + 0U, // POPCNT64rr + 0U, // POPDS16 + 0U, // POPDS32 + 0U, // POPES16 + 0U, // POPES32 + 0U, // POPF16 + 0U, // POPF32 + 0U, // POPF64 + 0U, // POPFS16 + 0U, // POPFS32 + 0U, // POPFS64 + 0U, // POPGS16 + 0U, // POPGS32 + 0U, // POPGS64 + 0U, // POPSS16 + 0U, // POPSS32 + 0U, // PORrm + 0U, // PORrr + 0U, // PREFETCH + 0U, // PREFETCHNTA + 0U, // PREFETCHT0 + 0U, // PREFETCHT1 + 0U, // PREFETCHT2 + 0U, // PREFETCHW + 0U, // PREFETCHWT1 + 0U, // PSADBWrm + 0U, // PSADBWrr + 0U, // PSHUFBrm + 0U, // PSHUFBrr + 4U, // PSHUFDmi + 72U, // PSHUFDri + 4U, // PSHUFHWmi + 72U, // PSHUFHWri + 4U, // PSHUFLWmi + 72U, // PSHUFLWri + 0U, // PSIGNBrm + 0U, // PSIGNBrr + 0U, // PSIGNDrm + 0U, // PSIGNDrr + 0U, // PSIGNWrm + 0U, // PSIGNWrr + 0U, // PSLLDQri + 0U, // PSLLDri + 0U, // PSLLDrm + 0U, // PSLLDrr + 0U, // PSLLQri + 0U, // PSLLQrm + 0U, // PSLLQrr + 0U, // PSLLWri + 0U, // PSLLWrm + 0U, // PSLLWrr + 0U, // PSRADri + 0U, // PSRADrm + 0U, // PSRADrr + 0U, // PSRAWri + 0U, // PSRAWrm + 0U, // PSRAWrr + 0U, // PSRLDQri + 0U, // PSRLDri + 0U, // PSRLDrm + 0U, // PSRLDrr + 0U, // PSRLQri + 0U, // PSRLQrm + 0U, // PSRLQrr + 0U, // PSRLWri + 0U, // PSRLWrm + 0U, // PSRLWrr + 0U, // PSUBBrm + 0U, // PSUBBrr + 0U, // PSUBDrm + 0U, // PSUBDrr + 0U, // PSUBQrm + 0U, // PSUBQrr + 0U, // PSUBSBrm + 0U, // PSUBSBrr + 0U, // PSUBSWrm + 0U, // PSUBSWrr + 0U, // PSUBUSBrm + 0U, // PSUBUSBrr + 0U, // PSUBUSWrm + 0U, // PSUBUSWrr + 0U, // PSUBWrm + 0U, // PSUBWrr + 0U, // PSWAPDrm + 0U, // PSWAPDrr + 0U, // PTESTrm + 0U, // PTESTrr + 0U, // PTWRITE64m + 0U, // PTWRITE64r + 0U, // PTWRITEm + 0U, // PTWRITEr + 0U, // PUNPCKHBWrm + 0U, // PUNPCKHBWrr + 0U, // PUNPCKHDQrm + 0U, // PUNPCKHDQrr + 0U, // PUNPCKHQDQrm + 0U, // PUNPCKHQDQrr + 0U, // PUNPCKHWDrm + 0U, // PUNPCKHWDrr + 0U, // PUNPCKLBWrm + 0U, // PUNPCKLBWrr + 0U, // PUNPCKLDQrm + 0U, // PUNPCKLDQrr + 0U, // PUNPCKLQDQrm + 0U, // PUNPCKLQDQrr + 0U, // PUNPCKLWDrm + 0U, // PUNPCKLWDrr + 0U, // PUSH16i8 + 0U, // PUSH16r + 0U, // PUSH16rmm + 0U, // PUSH16rmr + 0U, // PUSH32i8 + 0U, // PUSH32r + 0U, // PUSH32rmm + 0U, // PUSH32rmr + 0U, // PUSH64i32 + 0U, // PUSH64i8 + 0U, // PUSH64r + 0U, // PUSH64rmm + 0U, // PUSH64rmr + 0U, // PUSHA16 + 0U, // PUSHA32 + 0U, // PUSHCS16 + 0U, // PUSHCS32 + 0U, // PUSHDS16 + 0U, // PUSHDS32 + 0U, // PUSHES16 + 0U, // PUSHES32 + 0U, // PUSHF16 + 0U, // PUSHF32 + 0U, // PUSHF64 + 0U, // PUSHFS16 + 0U, // PUSHFS32 + 0U, // PUSHFS64 + 0U, // PUSHGS16 + 0U, // PUSHGS32 + 0U, // PUSHGS64 + 0U, // PUSHSS16 + 0U, // PUSHSS32 + 0U, // PUSHi16 + 0U, // PUSHi32 + 0U, // PXORrm + 0U, // PXORrr + 0U, // RCL16m1 + 0U, // RCL16mCL + 1U, // RCL16mi + 0U, // RCL16r1 + 0U, // RCL16rCL + 0U, // RCL16ri + 0U, // RCL32m1 + 0U, // RCL32mCL + 1U, // RCL32mi + 0U, // RCL32r1 + 0U, // RCL32rCL + 0U, // RCL32ri + 0U, // RCL64m1 + 0U, // RCL64mCL + 1U, // RCL64mi + 0U, // RCL64r1 + 0U, // RCL64rCL + 0U, // RCL64ri + 0U, // RCL8m1 + 0U, // RCL8mCL + 1U, // RCL8mi + 0U, // RCL8r1 + 0U, // RCL8rCL + 0U, // RCL8ri + 0U, // RCPPSm + 0U, // RCPPSr + 0U, // RCPSSm + 0U, // RCPSSm_Int + 0U, // RCPSSr + 0U, // RCPSSr_Int + 0U, // RCR16m1 + 0U, // RCR16mCL + 1U, // RCR16mi + 0U, // RCR16r1 + 0U, // RCR16rCL + 0U, // RCR16ri + 0U, // RCR32m1 + 0U, // RCR32mCL + 1U, // RCR32mi + 0U, // RCR32r1 + 0U, // RCR32rCL + 0U, // RCR32ri + 0U, // RCR64m1 + 0U, // RCR64mCL + 1U, // RCR64mi + 0U, // RCR64r1 + 0U, // RCR64rCL + 0U, // RCR64ri + 0U, // RCR8m1 + 0U, // RCR8mCL + 1U, // RCR8mi + 0U, // RCR8r1 + 0U, // RCR8rCL + 0U, // RCR8ri + 0U, // RDFSBASE + 0U, // RDFSBASE64 + 0U, // RDGSBASE + 0U, // RDGSBASE64 + 0U, // RDMSR + 0U, // RDPID32 + 0U, // RDPID64 + 0U, // RDPKRUr + 0U, // RDPMC + 0U, // RDRAND16r + 0U, // RDRAND32r + 0U, // RDRAND64r + 0U, // RDSEED16r + 0U, // RDSEED32r + 0U, // RDSEED64r + 0U, // RDSSPD + 0U, // RDSSPQ + 0U, // RDTSC + 0U, // RDTSCP + 0U, // REPNE_PREFIX + 0U, // REP_PREFIX + 0U, // RETIL + 0U, // RETIQ + 0U, // RETIW + 0U, // RETL + 0U, // RETQ + 0U, // RETW + 0U, // REX64_PREFIX + 0U, // ROL16m1 + 0U, // ROL16mCL + 1U, // ROL16mi + 0U, // ROL16r1 + 0U, // ROL16rCL + 0U, // ROL16ri + 0U, // ROL32m1 + 0U, // ROL32mCL + 1U, // ROL32mi + 0U, // ROL32r1 + 0U, // ROL32rCL + 0U, // ROL32ri + 0U, // ROL64m1 + 0U, // ROL64mCL + 1U, // ROL64mi + 0U, // ROL64r1 + 0U, // ROL64rCL + 0U, // ROL64ri + 0U, // ROL8m1 + 0U, // ROL8mCL + 1U, // ROL8mi + 0U, // ROL8r1 + 0U, // ROL8rCL + 0U, // ROL8ri + 0U, // ROR16m1 + 0U, // ROR16mCL + 1U, // ROR16mi + 0U, // ROR16r1 + 0U, // ROR16rCL + 0U, // ROR16ri + 0U, // ROR32m1 + 0U, // ROR32mCL + 1U, // ROR32mi + 0U, // ROR32r1 + 0U, // ROR32rCL + 0U, // ROR32ri + 0U, // ROR64m1 + 0U, // ROR64mCL + 1U, // ROR64mi + 0U, // ROR64r1 + 0U, // ROR64rCL + 0U, // ROR64ri + 0U, // ROR8m1 + 0U, // ROR8mCL + 1U, // ROR8mi + 0U, // ROR8r1 + 0U, // ROR8rCL + 0U, // ROR8ri + 4U, // RORX32mi + 72U, // RORX32ri + 4U, // RORX64mi + 72U, // RORX64ri + 0U, // ROUNDPDm + 72U, // ROUNDPDr + 0U, // ROUNDPSm + 72U, // ROUNDPSr + 4U, // ROUNDSDm + 4U, // ROUNDSDm_Int + 72U, // ROUNDSDr + 4U, // ROUNDSDr_Int + 4U, // ROUNDSSm + 4U, // ROUNDSSm_Int + 72U, // ROUNDSSr + 4U, // ROUNDSSr_Int + 0U, // RSM + 0U, // RSQRTPSm + 0U, // RSQRTPSr + 0U, // RSQRTSSm + 0U, // RSQRTSSm_Int + 0U, // RSQRTSSr + 0U, // RSQRTSSr_Int + 0U, // RSTORSSP + 0U, // SAHF + 0U, // SAL16m1 + 0U, // SAL16mCL + 0U, // SAL16mi + 0U, // SAL16r1 + 0U, // SAL16rCL + 0U, // SAL16ri + 0U, // SAL32m1 + 0U, // SAL32mCL + 0U, // SAL32mi + 0U, // SAL32r1 + 0U, // SAL32rCL + 0U, // SAL32ri + 0U, // SAL64m1 + 0U, // SAL64mCL + 0U, // SAL64mi + 0U, // SAL64r1 + 0U, // SAL64rCL + 0U, // SAL64ri + 0U, // SAL8m1 + 0U, // SAL8mCL + 0U, // SAL8mi + 0U, // SAL8r1 + 0U, // SAL8rCL + 0U, // SAL8ri + 0U, // SALC + 0U, // SAR16m1 + 0U, // SAR16mCL + 1U, // SAR16mi + 0U, // SAR16r1 + 0U, // SAR16rCL + 0U, // SAR16ri + 0U, // SAR32m1 + 0U, // SAR32mCL + 1U, // SAR32mi + 0U, // SAR32r1 + 0U, // SAR32rCL + 0U, // SAR32ri + 0U, // SAR64m1 + 0U, // SAR64mCL + 1U, // SAR64mi + 0U, // SAR64r1 + 0U, // SAR64rCL + 0U, // SAR64ri + 0U, // SAR8m1 + 0U, // SAR8mCL + 1U, // SAR8mi + 0U, // SAR8r1 + 0U, // SAR8rCL + 0U, // SAR8ri + 4U, // SARX32rm + 4U, // SARX32rr + 4U, // SARX64rm + 4U, // SARX64rr + 0U, // SAVEPREVSSP + 0U, // SBB16i16 + 0U, // SBB16mi + 0U, // SBB16mi8 + 0U, // SBB16mr + 0U, // SBB16ri + 0U, // SBB16ri8 + 0U, // SBB16rm + 0U, // SBB16rr + 0U, // SBB16rr_REV + 0U, // SBB32i32 + 0U, // SBB32mi + 0U, // SBB32mi8 + 0U, // SBB32mr + 0U, // SBB32ri + 0U, // SBB32ri8 + 0U, // SBB32rm + 0U, // SBB32rr + 0U, // SBB32rr_REV + 0U, // SBB64i32 + 0U, // SBB64mi32 + 0U, // SBB64mi8 + 0U, // SBB64mr + 0U, // SBB64ri32 + 0U, // SBB64ri8 + 0U, // SBB64rm + 0U, // SBB64rr + 0U, // SBB64rr_REV + 0U, // SBB8i8 + 0U, // SBB8mi + 0U, // SBB8mi8 + 0U, // SBB8mr + 0U, // SBB8ri + 0U, // SBB8ri8 + 0U, // SBB8rm + 0U, // SBB8rr + 0U, // SBB8rr_REV + 0U, // SCASB + 0U, // SCASL + 0U, // SCASQ + 0U, // SCASW + 0U, // SETAEm + 0U, // SETAEr + 0U, // SETAm + 0U, // SETAr + 0U, // SETBEm + 0U, // SETBEr + 0U, // SETBm + 0U, // SETBr + 0U, // SETEm + 0U, // SETEr + 0U, // SETGEm + 0U, // SETGEr + 0U, // SETGm + 0U, // SETGr + 0U, // SETLEm + 0U, // SETLEr + 0U, // SETLm + 0U, // SETLr + 0U, // SETNEm + 0U, // SETNEr + 0U, // SETNOm + 0U, // SETNOr + 0U, // SETNPm + 0U, // SETNPr + 0U, // SETNSm + 0U, // SETNSr + 0U, // SETOm + 0U, // SETOr + 0U, // SETPm + 0U, // SETPr + 0U, // SETSSBSY + 0U, // SETSm + 0U, // SETSr + 0U, // SFENCE + 0U, // SGDT16m + 0U, // SGDT32m + 0U, // SGDT64m + 0U, // SHA1MSG1rm + 0U, // SHA1MSG1rr + 0U, // SHA1MSG2rm + 0U, // SHA1MSG2rr + 0U, // SHA1NEXTErm + 0U, // SHA1NEXTErr + 0U, // SHA1RNDS4rmi + 4U, // SHA1RNDS4rri + 0U, // SHA256MSG1rm + 0U, // SHA256MSG1rr + 0U, // SHA256MSG2rm + 0U, // SHA256MSG2rr + 0U, // SHA256RNDS2rm + 0U, // SHA256RNDS2rr + 0U, // SHL16m1 + 0U, // SHL16mCL + 1U, // SHL16mi + 0U, // SHL16r1 + 0U, // SHL16rCL + 0U, // SHL16ri + 0U, // SHL32m1 + 0U, // SHL32mCL + 1U, // SHL32mi + 0U, // SHL32r1 + 0U, // SHL32rCL + 0U, // SHL32ri + 0U, // SHL64m1 + 0U, // SHL64mCL + 1U, // SHL64mi + 0U, // SHL64r1 + 0U, // SHL64rCL + 0U, // SHL64ri + 0U, // SHL8m1 + 0U, // SHL8mCL + 1U, // SHL8mi + 0U, // SHL8r1 + 0U, // SHL8rCL + 0U, // SHL8ri + 0U, // SHLD16mrCL + 1U, // SHLD16mri8 + 0U, // SHLD16rrCL + 4U, // SHLD16rri8 + 0U, // SHLD32mrCL + 1U, // SHLD32mri8 + 0U, // SHLD32rrCL + 4U, // SHLD32rri8 + 0U, // SHLD64mrCL + 1U, // SHLD64mri8 + 0U, // SHLD64rrCL + 4U, // SHLD64rri8 + 4U, // SHLX32rm + 4U, // SHLX32rr + 4U, // SHLX64rm + 4U, // SHLX64rr + 0U, // SHR16m1 + 0U, // SHR16mCL + 1U, // SHR16mi + 0U, // SHR16r1 + 0U, // SHR16rCL + 0U, // SHR16ri + 0U, // SHR32m1 + 0U, // SHR32mCL + 1U, // SHR32mi + 0U, // SHR32r1 + 0U, // SHR32rCL + 0U, // SHR32ri + 0U, // SHR64m1 + 0U, // SHR64mCL + 1U, // SHR64mi + 0U, // SHR64r1 + 0U, // SHR64rCL + 0U, // SHR64ri + 0U, // SHR8m1 + 0U, // SHR8mCL + 1U, // SHR8mi + 0U, // SHR8r1 + 0U, // SHR8rCL + 0U, // SHR8ri + 0U, // SHRD16mrCL + 1U, // SHRD16mri8 + 0U, // SHRD16rrCL + 4U, // SHRD16rri8 + 0U, // SHRD32mrCL + 1U, // SHRD32mri8 + 0U, // SHRD32rrCL + 4U, // SHRD32rri8 + 0U, // SHRD64mrCL + 1U, // SHRD64mri8 + 0U, // SHRD64rrCL + 4U, // SHRD64rri8 + 4U, // SHRX32rm + 4U, // SHRX32rr + 4U, // SHRX64rm + 4U, // SHRX64rr + 0U, // SHUFPDrmi + 4U, // SHUFPDrri + 0U, // SHUFPSrmi + 4U, // SHUFPSrri + 0U, // SIDT16m + 0U, // SIDT32m + 0U, // SIDT64m + 0U, // SIN_F + 0U, // SIN_Fp32 + 0U, // SIN_Fp64 + 0U, // SIN_Fp80 + 0U, // SKINIT + 0U, // SLDT16m + 0U, // SLDT16r + 0U, // SLDT32r + 0U, // SLDT64r + 0U, // SLWPCB + 0U, // SLWPCB64 + 0U, // SMSW16m + 0U, // SMSW16r + 0U, // SMSW32r + 0U, // SMSW64r + 0U, // SQRTPDm + 0U, // SQRTPDr + 0U, // SQRTPSm + 0U, // SQRTPSr + 0U, // SQRTSDm + 0U, // SQRTSDm_Int + 0U, // SQRTSDr + 0U, // SQRTSDr_Int + 0U, // SQRTSSm + 0U, // SQRTSSm_Int + 0U, // SQRTSSr + 0U, // SQRTSSr_Int + 0U, // SQRT_F + 0U, // SQRT_Fp32 + 0U, // SQRT_Fp64 + 0U, // SQRT_Fp80 + 0U, // STAC + 0U, // STC + 0U, // STD + 0U, // STGI + 0U, // STI + 0U, // STMXCSR + 0U, // STOSB + 0U, // STOSL + 0U, // STOSQ + 0U, // STOSW + 0U, // STR16r + 0U, // STR32r + 0U, // STR64r + 0U, // STRm + 0U, // ST_F32m + 0U, // ST_F64m + 0U, // ST_FP32m + 0U, // ST_FP64m + 0U, // ST_FP80m + 0U, // ST_FPrr + 0U, // ST_Fp32m + 0U, // ST_Fp64m + 0U, // ST_Fp64m32 + 0U, // ST_Fp80m32 + 0U, // ST_Fp80m64 + 0U, // ST_FpP32m + 0U, // ST_FpP64m + 0U, // ST_FpP64m32 + 0U, // ST_FpP80m + 0U, // ST_FpP80m32 + 0U, // ST_FpP80m64 + 0U, // ST_Frr + 0U, // SUB16i16 + 0U, // SUB16mi + 0U, // SUB16mi8 + 0U, // SUB16mr + 0U, // SUB16ri + 0U, // SUB16ri8 + 0U, // SUB16rm + 0U, // SUB16rr + 0U, // SUB16rr_REV + 0U, // SUB32i32 + 0U, // SUB32mi + 0U, // SUB32mi8 + 0U, // SUB32mr + 0U, // SUB32ri + 0U, // SUB32ri8 + 0U, // SUB32rm + 0U, // SUB32rr + 0U, // SUB32rr_REV + 0U, // SUB64i32 + 0U, // SUB64mi32 + 0U, // SUB64mi8 + 0U, // SUB64mr + 0U, // SUB64ri32 + 0U, // SUB64ri8 + 0U, // SUB64rm + 0U, // SUB64rr + 0U, // SUB64rr_REV + 0U, // SUB8i8 + 0U, // SUB8mi + 0U, // SUB8mi8 + 0U, // SUB8mr + 0U, // SUB8ri + 0U, // SUB8ri8 + 0U, // SUB8rm + 0U, // SUB8rr + 0U, // SUB8rr_REV + 0U, // SUBPDrm + 0U, // SUBPDrr + 0U, // SUBPSrm + 0U, // SUBPSrr + 0U, // SUBR_F32m + 0U, // SUBR_F64m + 0U, // SUBR_FI16m + 0U, // SUBR_FI32m + 0U, // SUBR_FPrST0 + 0U, // SUBR_FST0r + 0U, // SUBR_Fp32m + 0U, // SUBR_Fp64m + 0U, // SUBR_Fp64m32 + 0U, // SUBR_Fp80m32 + 0U, // SUBR_Fp80m64 + 0U, // SUBR_FpI16m32 + 0U, // SUBR_FpI16m64 + 0U, // SUBR_FpI16m80 + 0U, // SUBR_FpI32m32 + 0U, // SUBR_FpI32m64 + 0U, // SUBR_FpI32m80 + 0U, // SUBR_FrST0 + 0U, // SUBSDrm + 0U, // SUBSDrm_Int + 0U, // SUBSDrr + 0U, // SUBSDrr_Int + 0U, // SUBSSrm + 0U, // SUBSSrm_Int + 0U, // SUBSSrr + 0U, // SUBSSrr_Int + 0U, // SUB_F32m + 0U, // SUB_F64m + 0U, // SUB_FI16m + 0U, // SUB_FI32m + 0U, // SUB_FPrST0 + 0U, // SUB_FST0r + 0U, // SUB_Fp32 + 0U, // SUB_Fp32m + 0U, // SUB_Fp64 + 0U, // SUB_Fp64m + 0U, // SUB_Fp64m32 + 0U, // SUB_Fp80 + 0U, // SUB_Fp80m32 + 0U, // SUB_Fp80m64 + 0U, // SUB_FpI16m32 + 0U, // SUB_FpI16m64 + 0U, // SUB_FpI16m80 + 0U, // SUB_FpI32m32 + 0U, // SUB_FpI32m64 + 0U, // SUB_FpI32m80 + 0U, // SUB_FrST0 + 0U, // SWAPGS + 0U, // SYSCALL + 0U, // SYSENTER + 0U, // SYSEXIT + 0U, // SYSEXIT64 + 0U, // SYSRET + 0U, // SYSRET64 + 0U, // T1MSKC32rm + 0U, // T1MSKC32rr + 0U, // T1MSKC64rm + 0U, // T1MSKC64rr + 0U, // TEST16i16 + 0U, // TEST16mi + 0U, // TEST16mi_alt + 0U, // TEST16mr + 0U, // TEST16ri + 0U, // TEST16ri_alt + 0U, // TEST16rr + 0U, // TEST32i32 + 0U, // TEST32mi + 0U, // TEST32mi_alt + 0U, // TEST32mr + 0U, // TEST32ri + 0U, // TEST32ri_alt + 0U, // TEST32rr + 0U, // TEST64i32 + 0U, // TEST64mi32 + 0U, // TEST64mi32_alt + 0U, // TEST64mr + 0U, // TEST64ri32 + 0U, // TEST64ri32_alt + 0U, // TEST64rr + 0U, // TEST8i8 + 0U, // TEST8mi + 0U, // TEST8mi_alt + 0U, // TEST8mr + 0U, // TEST8ri + 0U, // TEST8ri_alt + 0U, // TEST8rr + 0U, // TPAUSE + 0U, // TST_F + 0U, // TST_Fp32 + 0U, // TST_Fp64 + 0U, // TST_Fp80 + 0U, // TZCNT16rm + 0U, // TZCNT16rr + 0U, // TZCNT32rm + 0U, // TZCNT32rr + 0U, // TZCNT64rm + 0U, // TZCNT64rr + 0U, // TZMSK32rm + 0U, // TZMSK32rr + 0U, // TZMSK64rm + 0U, // TZMSK64rr + 0U, // UCOMISDrm + 0U, // UCOMISDrm_Int + 0U, // UCOMISDrr + 0U, // UCOMISDrr_Int + 0U, // UCOMISSrm + 0U, // UCOMISSrm_Int + 0U, // UCOMISSrr + 0U, // UCOMISSrr_Int + 0U, // UCOM_FIPr + 0U, // UCOM_FIr + 0U, // UCOM_FPPr + 0U, // UCOM_FPr + 0U, // UCOM_FpIr32 + 0U, // UCOM_FpIr64 + 0U, // UCOM_FpIr80 + 0U, // UCOM_Fpr32 + 0U, // UCOM_Fpr64 + 0U, // UCOM_Fpr80 + 0U, // UCOM_Fr + 0U, // UD0 + 0U, // UD1 + 0U, // UD2 + 0U, // UMONITOR16 + 0U, // UMONITOR32 + 0U, // UMONITOR64 + 0U, // UMWAIT + 0U, // UNPCKHPDrm + 0U, // UNPCKHPDrr + 0U, // UNPCKHPSrm + 0U, // UNPCKHPSrr + 0U, // UNPCKLPDrm + 0U, // UNPCKLPDrr + 0U, // UNPCKLPSrm + 0U, // UNPCKLPSrr + 4U, // V4FMADDPSrm + 0U, // V4FMADDPSrmk + 0U, // V4FMADDPSrmkz + 4U, // V4FMADDSSrm + 0U, // V4FMADDSSrmk + 0U, // V4FMADDSSrmkz + 4U, // V4FNMADDPSrm + 0U, // V4FNMADDPSrmk + 0U, // V4FNMADDPSrmkz + 4U, // V4FNMADDSSrm + 0U, // V4FNMADDSSrmk + 0U, // V4FNMADDSSrmkz + 4U, // VADDPDYrm + 4U, // VADDPDYrr + 4U, // VADDPDZ128rm + 72U, // VADDPDZ128rmb + 133U, // VADDPDZ128rmbk + 9348U, // VADDPDZ128rmbkz + 0U, // VADDPDZ128rmk + 9348U, // VADDPDZ128rmkz + 4U, // VADDPDZ128rr + 0U, // VADDPDZ128rrk + 9348U, // VADDPDZ128rrkz + 4U, // VADDPDZ256rm + 72U, // VADDPDZ256rmb + 133U, // VADDPDZ256rmbk + 9348U, // VADDPDZ256rmbkz + 0U, // VADDPDZ256rmk + 9348U, // VADDPDZ256rmkz + 4U, // VADDPDZ256rr + 0U, // VADDPDZ256rrk + 9348U, // VADDPDZ256rrkz + 4U, // VADDPDZrm + 72U, // VADDPDZrmb + 133U, // VADDPDZrmbk + 9348U, // VADDPDZrmbkz + 0U, // VADDPDZrmk + 9348U, // VADDPDZrmkz + 4U, // VADDPDZrr + 4U, // VADDPDZrrb + 0U, // VADDPDZrrbk + 9348U, // VADDPDZrrbkz + 0U, // VADDPDZrrk + 9348U, // VADDPDZrrkz + 4U, // VADDPDrm + 4U, // VADDPDrr + 4U, // VADDPSYrm + 4U, // VADDPSYrr + 4U, // VADDPSZ128rm + 72U, // VADDPSZ128rmb + 133U, // VADDPSZ128rmbk + 9348U, // VADDPSZ128rmbkz + 0U, // VADDPSZ128rmk + 9348U, // VADDPSZ128rmkz + 4U, // VADDPSZ128rr + 0U, // VADDPSZ128rrk + 9348U, // VADDPSZ128rrkz + 4U, // VADDPSZ256rm + 72U, // VADDPSZ256rmb + 133U, // VADDPSZ256rmbk + 9348U, // VADDPSZ256rmbkz + 0U, // VADDPSZ256rmk + 9348U, // VADDPSZ256rmkz + 4U, // VADDPSZ256rr + 0U, // VADDPSZ256rrk + 9348U, // VADDPSZ256rrkz + 4U, // VADDPSZrm + 72U, // VADDPSZrmb + 133U, // VADDPSZrmbk + 9348U, // VADDPSZrmbkz + 0U, // VADDPSZrmk + 9348U, // VADDPSZrmkz + 4U, // VADDPSZrr + 4U, // VADDPSZrrb + 0U, // VADDPSZrrbk + 9348U, // VADDPSZrrbkz + 0U, // VADDPSZrrk + 9348U, // VADDPSZrrkz + 4U, // VADDPSrm + 4U, // VADDPSrr + 72U, // VADDSDZrm + 72U, // VADDSDZrm_Int + 133U, // VADDSDZrm_Intk + 9348U, // VADDSDZrm_Intkz + 4U, // VADDSDZrr + 4U, // VADDSDZrr_Int + 0U, // VADDSDZrr_Intk + 9348U, // VADDSDZrr_Intkz + 4U, // VADDSDZrrb_Int + 0U, // VADDSDZrrb_Intk + 9348U, // VADDSDZrrb_Intkz + 72U, // VADDSDrm + 72U, // VADDSDrm_Int + 4U, // VADDSDrr + 4U, // VADDSDrr_Int + 72U, // VADDSSZrm + 72U, // VADDSSZrm_Int + 133U, // VADDSSZrm_Intk + 9348U, // VADDSSZrm_Intkz + 4U, // VADDSSZrr + 4U, // VADDSSZrr_Int + 0U, // VADDSSZrr_Intk + 9348U, // VADDSSZrr_Intkz + 4U, // VADDSSZrrb_Int + 0U, // VADDSSZrrb_Intk + 9348U, // VADDSSZrrb_Intkz + 72U, // VADDSSrm + 72U, // VADDSSrm_Int + 4U, // VADDSSrr + 4U, // VADDSSrr_Int + 4U, // VADDSUBPDYrm + 4U, // VADDSUBPDYrr + 4U, // VADDSUBPDrm + 4U, // VADDSUBPDrr + 4U, // VADDSUBPSYrm + 4U, // VADDSUBPSYrr + 4U, // VADDSUBPSrm + 4U, // VADDSUBPSrr + 4U, // VAESDECLASTYrm + 4U, // VAESDECLASTYrr + 4U, // VAESDECLASTZ128rm + 4U, // VAESDECLASTZ128rr + 4U, // VAESDECLASTZ256rm + 4U, // VAESDECLASTZ256rr + 4U, // VAESDECLASTZrm + 4U, // VAESDECLASTZrr + 4U, // VAESDECLASTrm + 4U, // VAESDECLASTrr + 4U, // VAESDECYrm + 4U, // VAESDECYrr + 4U, // VAESDECZ128rm + 4U, // VAESDECZ128rr + 4U, // VAESDECZ256rm + 4U, // VAESDECZ256rr + 4U, // VAESDECZrm + 4U, // VAESDECZrr + 4U, // VAESDECrm + 4U, // VAESDECrr + 4U, // VAESENCLASTYrm + 4U, // VAESENCLASTYrr + 4U, // VAESENCLASTZ128rm + 4U, // VAESENCLASTZ128rr + 4U, // VAESENCLASTZ256rm + 4U, // VAESENCLASTZ256rr + 4U, // VAESENCLASTZrm + 4U, // VAESENCLASTZrr + 4U, // VAESENCLASTrm + 4U, // VAESENCLASTrr + 4U, // VAESENCYrm + 4U, // VAESENCYrr + 4U, // VAESENCZ128rm + 4U, // VAESENCZ128rr + 4U, // VAESENCZ256rm + 4U, // VAESENCZ256rr + 4U, // VAESENCZrm + 4U, // VAESENCZrr + 4U, // VAESENCrm + 4U, // VAESENCrr + 0U, // VAESIMCrm + 0U, // VAESIMCrr + 4U, // VAESKEYGENASSIST128rm + 72U, // VAESKEYGENASSIST128rr + 18637U, // VALIGNDZ128rmbi + 26833U, // VALIGNDZ128rmbik + 26837U, // VALIGNDZ128rmbikz + 72U, // VALIGNDZ128rmi + 1U, // VALIGNDZ128rmik + 9348U, // VALIGNDZ128rmikz + 18636U, // VALIGNDZ128rri + 25U, // VALIGNDZ128rrik + 26837U, // VALIGNDZ128rrikz + 18637U, // VALIGNDZ256rmbi + 26833U, // VALIGNDZ256rmbik + 26837U, // VALIGNDZ256rmbikz + 72U, // VALIGNDZ256rmi + 1U, // VALIGNDZ256rmik + 9348U, // VALIGNDZ256rmikz + 18636U, // VALIGNDZ256rri + 25U, // VALIGNDZ256rrik + 26837U, // VALIGNDZ256rrikz + 18637U, // VALIGNDZrmbi + 26833U, // VALIGNDZrmbik + 26837U, // VALIGNDZrmbikz + 72U, // VALIGNDZrmi + 1U, // VALIGNDZrmik + 9348U, // VALIGNDZrmikz + 18636U, // VALIGNDZrri + 25U, // VALIGNDZrrik + 26837U, // VALIGNDZrrikz + 18637U, // VALIGNQZ128rmbi + 26833U, // VALIGNQZ128rmbik + 26837U, // VALIGNQZ128rmbikz + 72U, // VALIGNQZ128rmi + 1U, // VALIGNQZ128rmik + 9348U, // VALIGNQZ128rmikz + 18636U, // VALIGNQZ128rri + 25U, // VALIGNQZ128rrik + 26837U, // VALIGNQZ128rrikz + 18637U, // VALIGNQZ256rmbi + 26833U, // VALIGNQZ256rmbik + 26837U, // VALIGNQZ256rmbikz + 72U, // VALIGNQZ256rmi + 1U, // VALIGNQZ256rmik + 9348U, // VALIGNQZ256rmikz + 18636U, // VALIGNQZ256rri + 25U, // VALIGNQZ256rrik + 26837U, // VALIGNQZ256rrikz + 18637U, // VALIGNQZrmbi + 26833U, // VALIGNQZrmbik + 26837U, // VALIGNQZrmbikz + 72U, // VALIGNQZrmi + 1U, // VALIGNQZrmik + 9348U, // VALIGNQZrmikz + 18636U, // VALIGNQZrri + 25U, // VALIGNQZrrik + 26837U, // VALIGNQZrrikz + 4U, // VANDNPDYrm + 4U, // VANDNPDYrr + 4U, // VANDNPDZ128rm + 72U, // VANDNPDZ128rmb + 133U, // VANDNPDZ128rmbk + 9348U, // VANDNPDZ128rmbkz + 0U, // VANDNPDZ128rmk + 9348U, // VANDNPDZ128rmkz + 4U, // VANDNPDZ128rr + 0U, // VANDNPDZ128rrk + 9348U, // VANDNPDZ128rrkz + 4U, // VANDNPDZ256rm + 72U, // VANDNPDZ256rmb + 133U, // VANDNPDZ256rmbk + 9348U, // VANDNPDZ256rmbkz + 0U, // VANDNPDZ256rmk + 9348U, // VANDNPDZ256rmkz + 4U, // VANDNPDZ256rr + 0U, // VANDNPDZ256rrk + 9348U, // VANDNPDZ256rrkz + 4U, // VANDNPDZrm + 72U, // VANDNPDZrmb + 133U, // VANDNPDZrmbk + 9348U, // VANDNPDZrmbkz + 0U, // VANDNPDZrmk + 9348U, // VANDNPDZrmkz + 4U, // VANDNPDZrr + 0U, // VANDNPDZrrk + 9348U, // VANDNPDZrrkz + 4U, // VANDNPDrm + 4U, // VANDNPDrr + 4U, // VANDNPSYrm + 4U, // VANDNPSYrr + 4U, // VANDNPSZ128rm + 72U, // VANDNPSZ128rmb + 133U, // VANDNPSZ128rmbk + 9348U, // VANDNPSZ128rmbkz + 0U, // VANDNPSZ128rmk + 9348U, // VANDNPSZ128rmkz + 4U, // VANDNPSZ128rr + 0U, // VANDNPSZ128rrk + 9348U, // VANDNPSZ128rrkz + 4U, // VANDNPSZ256rm + 72U, // VANDNPSZ256rmb + 133U, // VANDNPSZ256rmbk + 9348U, // VANDNPSZ256rmbkz + 0U, // VANDNPSZ256rmk + 9348U, // VANDNPSZ256rmkz + 4U, // VANDNPSZ256rr + 0U, // VANDNPSZ256rrk + 9348U, // VANDNPSZ256rrkz + 4U, // VANDNPSZrm + 72U, // VANDNPSZrmb + 133U, // VANDNPSZrmbk + 9348U, // VANDNPSZrmbkz + 0U, // VANDNPSZrmk + 9348U, // VANDNPSZrmkz + 4U, // VANDNPSZrr + 0U, // VANDNPSZrrk + 9348U, // VANDNPSZrrkz + 4U, // VANDNPSrm + 4U, // VANDNPSrr + 4U, // VANDPDYrm + 4U, // VANDPDYrr + 4U, // VANDPDZ128rm + 72U, // VANDPDZ128rmb + 133U, // VANDPDZ128rmbk + 9348U, // VANDPDZ128rmbkz + 0U, // VANDPDZ128rmk + 9348U, // VANDPDZ128rmkz + 4U, // VANDPDZ128rr + 0U, // VANDPDZ128rrk + 9348U, // VANDPDZ128rrkz + 4U, // VANDPDZ256rm + 72U, // VANDPDZ256rmb + 133U, // VANDPDZ256rmbk + 9348U, // VANDPDZ256rmbkz + 0U, // VANDPDZ256rmk + 9348U, // VANDPDZ256rmkz + 4U, // VANDPDZ256rr + 0U, // VANDPDZ256rrk + 9348U, // VANDPDZ256rrkz + 4U, // VANDPDZrm + 72U, // VANDPDZrmb + 133U, // VANDPDZrmbk + 9348U, // VANDPDZrmbkz + 0U, // VANDPDZrmk + 9348U, // VANDPDZrmkz + 4U, // VANDPDZrr + 0U, // VANDPDZrrk + 9348U, // VANDPDZrrkz + 4U, // VANDPDrm + 4U, // VANDPDrr + 4U, // VANDPSYrm + 4U, // VANDPSYrr + 4U, // VANDPSZ128rm + 72U, // VANDPSZ128rmb + 133U, // VANDPSZ128rmbk + 9348U, // VANDPSZ128rmbkz + 0U, // VANDPSZ128rmk + 9348U, // VANDPSZ128rmkz + 4U, // VANDPSZ128rr + 0U, // VANDPSZ128rrk + 9348U, // VANDPSZ128rrkz + 4U, // VANDPSZ256rm + 72U, // VANDPSZ256rmb + 133U, // VANDPSZ256rmbk + 9348U, // VANDPSZ256rmbkz + 0U, // VANDPSZ256rmk + 9348U, // VANDPSZ256rmkz + 4U, // VANDPSZ256rr + 0U, // VANDPSZ256rrk + 9348U, // VANDPSZ256rrkz + 4U, // VANDPSZrm + 72U, // VANDPSZrmb + 133U, // VANDPSZrmbk + 9348U, // VANDPSZrmbkz + 0U, // VANDPSZrmk + 9348U, // VANDPSZrmkz + 4U, // VANDPSZrr + 0U, // VANDPSZrrk + 9348U, // VANDPSZrrkz + 4U, // VANDPSrm + 4U, // VANDPSrr + 4U, // VBLENDMPDZ128rm + 72U, // VBLENDMPDZ128rmb + 1156U, // VBLENDMPDZ128rmbk + 9348U, // VBLENDMPDZ128rmbkz + 1156U, // VBLENDMPDZ128rmk + 9348U, // VBLENDMPDZ128rmkz + 4U, // VBLENDMPDZ128rr + 1156U, // VBLENDMPDZ128rrk + 9348U, // VBLENDMPDZ128rrkz + 4U, // VBLENDMPDZ256rm + 72U, // VBLENDMPDZ256rmb + 1156U, // VBLENDMPDZ256rmbk + 9348U, // VBLENDMPDZ256rmbkz + 1156U, // VBLENDMPDZ256rmk + 9348U, // VBLENDMPDZ256rmkz + 4U, // VBLENDMPDZ256rr + 1156U, // VBLENDMPDZ256rrk + 9348U, // VBLENDMPDZ256rrkz + 4U, // VBLENDMPDZrm + 72U, // VBLENDMPDZrmb + 1156U, // VBLENDMPDZrmbk + 9348U, // VBLENDMPDZrmbkz + 1156U, // VBLENDMPDZrmk + 9348U, // VBLENDMPDZrmkz + 4U, // VBLENDMPDZrr + 1156U, // VBLENDMPDZrrk + 9348U, // VBLENDMPDZrrkz + 4U, // VBLENDMPSZ128rm + 72U, // VBLENDMPSZ128rmb + 1156U, // VBLENDMPSZ128rmbk + 9348U, // VBLENDMPSZ128rmbkz + 1156U, // VBLENDMPSZ128rmk + 9348U, // VBLENDMPSZ128rmkz + 4U, // VBLENDMPSZ128rr + 1156U, // VBLENDMPSZ128rrk + 9348U, // VBLENDMPSZ128rrkz + 4U, // VBLENDMPSZ256rm + 72U, // VBLENDMPSZ256rmb + 1156U, // VBLENDMPSZ256rmbk + 9348U, // VBLENDMPSZ256rmbkz + 1156U, // VBLENDMPSZ256rmk + 9348U, // VBLENDMPSZ256rmkz + 4U, // VBLENDMPSZ256rr + 1156U, // VBLENDMPSZ256rrk + 9348U, // VBLENDMPSZ256rrkz + 4U, // VBLENDMPSZrm + 72U, // VBLENDMPSZrmb + 1156U, // VBLENDMPSZrmbk + 9348U, // VBLENDMPSZrmbkz + 1156U, // VBLENDMPSZrmk + 9348U, // VBLENDMPSZrmkz + 4U, // VBLENDMPSZrr + 1156U, // VBLENDMPSZrrk + 9348U, // VBLENDMPSZrrkz + 72U, // VBLENDPDYrmi + 18636U, // VBLENDPDYrri + 72U, // VBLENDPDrmi + 18636U, // VBLENDPDrri + 72U, // VBLENDPSYrmi + 18636U, // VBLENDPSYrri + 72U, // VBLENDPSrmi + 18636U, // VBLENDPSrri + 72U, // VBLENDVPDYrm + 18636U, // VBLENDVPDYrr + 72U, // VBLENDVPDrm + 18636U, // VBLENDVPDrr + 72U, // VBLENDVPSYrm + 18636U, // VBLENDVPSYrr + 72U, // VBLENDVPSrm + 18636U, // VBLENDVPSrr + 0U, // VBROADCASTF128 + 0U, // VBROADCASTF32X2Z256m + 3356U, // VBROADCASTF32X2Z256mk + 4444U, // VBROADCASTF32X2Z256mkz + 0U, // VBROADCASTF32X2Z256r + 405U, // VBROADCASTF32X2Z256rk + 461U, // VBROADCASTF32X2Z256rkz + 0U, // VBROADCASTF32X2Zm + 3356U, // VBROADCASTF32X2Zmk + 4444U, // VBROADCASTF32X2Zmkz + 0U, // VBROADCASTF32X2Zr + 405U, // VBROADCASTF32X2Zrk + 461U, // VBROADCASTF32X2Zrkz + 0U, // VBROADCASTF32X4Z256rm + 405U, // VBROADCASTF32X4Z256rmk + 461U, // VBROADCASTF32X4Z256rmkz + 0U, // VBROADCASTF32X4rm + 405U, // VBROADCASTF32X4rmk + 461U, // VBROADCASTF32X4rmkz + 0U, // VBROADCASTF32X8rm + 405U, // VBROADCASTF32X8rmk + 461U, // VBROADCASTF32X8rmkz + 0U, // VBROADCASTF64X2Z128rm + 405U, // VBROADCASTF64X2Z128rmk + 461U, // VBROADCASTF64X2Z128rmkz + 0U, // VBROADCASTF64X2rm + 405U, // VBROADCASTF64X2rmk + 461U, // VBROADCASTF64X2rmkz + 0U, // VBROADCASTF64X4rm + 405U, // VBROADCASTF64X4rmk + 461U, // VBROADCASTF64X4rmkz + 0U, // VBROADCASTI128 + 0U, // VBROADCASTI32X2Z128m + 3356U, // VBROADCASTI32X2Z128mk + 4444U, // VBROADCASTI32X2Z128mkz + 0U, // VBROADCASTI32X2Z128r + 405U, // VBROADCASTI32X2Z128rk + 461U, // VBROADCASTI32X2Z128rkz + 0U, // VBROADCASTI32X2Z256m + 3356U, // VBROADCASTI32X2Z256mk + 4444U, // VBROADCASTI32X2Z256mkz + 0U, // VBROADCASTI32X2Z256r + 405U, // VBROADCASTI32X2Z256rk + 461U, // VBROADCASTI32X2Z256rkz + 0U, // VBROADCASTI32X2Zm + 3356U, // VBROADCASTI32X2Zmk + 4444U, // VBROADCASTI32X2Zmkz + 0U, // VBROADCASTI32X2Zr + 405U, // VBROADCASTI32X2Zrk + 461U, // VBROADCASTI32X2Zrkz + 0U, // VBROADCASTI32X4Z256rm + 405U, // VBROADCASTI32X4Z256rmk + 461U, // VBROADCASTI32X4Z256rmkz + 0U, // VBROADCASTI32X4rm + 405U, // VBROADCASTI32X4rmk + 461U, // VBROADCASTI32X4rmkz + 0U, // VBROADCASTI32X8rm + 405U, // VBROADCASTI32X8rmk + 461U, // VBROADCASTI32X8rmkz + 0U, // VBROADCASTI64X2Z128rm + 405U, // VBROADCASTI64X2Z128rmk + 461U, // VBROADCASTI64X2Z128rmkz + 0U, // VBROADCASTI64X2rm + 405U, // VBROADCASTI64X2rmk + 461U, // VBROADCASTI64X2rmkz + 0U, // VBROADCASTI64X4rm + 405U, // VBROADCASTI64X4rmk + 461U, // VBROADCASTI64X4rmkz + 0U, // VBROADCASTSDYrm + 0U, // VBROADCASTSDYrr + 0U, // VBROADCASTSDZ256m + 3356U, // VBROADCASTSDZ256mk + 4444U, // VBROADCASTSDZ256mkz + 0U, // VBROADCASTSDZ256r + 405U, // VBROADCASTSDZ256rk + 461U, // VBROADCASTSDZ256rkz + 0U, // VBROADCASTSDZm + 3356U, // VBROADCASTSDZmk + 4444U, // VBROADCASTSDZmkz + 0U, // VBROADCASTSDZr + 405U, // VBROADCASTSDZrk + 461U, // VBROADCASTSDZrkz + 0U, // VBROADCASTSSYrm + 0U, // VBROADCASTSSYrr + 0U, // VBROADCASTSSZ128m + 3356U, // VBROADCASTSSZ128mk + 4444U, // VBROADCASTSSZ128mkz + 0U, // VBROADCASTSSZ128r + 405U, // VBROADCASTSSZ128rk + 461U, // VBROADCASTSSZ128rkz + 0U, // VBROADCASTSSZ256m + 3356U, // VBROADCASTSSZ256mk + 4444U, // VBROADCASTSSZ256mkz + 0U, // VBROADCASTSSZ256r + 405U, // VBROADCASTSSZ256rk + 461U, // VBROADCASTSSZ256rkz + 0U, // VBROADCASTSSZm + 3356U, // VBROADCASTSSZmk + 4444U, // VBROADCASTSSZmkz + 0U, // VBROADCASTSSZr + 405U, // VBROADCASTSSZrk + 461U, // VBROADCASTSSZrkz + 0U, // VBROADCASTSSrm + 0U, // VBROADCASTSSrr + 1U, // VCMPPDYrmi + 72U, // VCMPPDYrmi_alt + 18636U, // VCMPPDYrri + 18636U, // VCMPPDYrri_alt + 21856U, // VCMPPDZ128rmbi + 18637U, // VCMPPDZ128rmbi_alt + 26837U, // VCMPPDZ128rmbi_altk + 29985U, // VCMPPDZ128rmbik + 18636U, // VCMPPDZ128rmi + 72U, // VCMPPDZ128rmi_alt + 1156U, // VCMPPDZ128rmi_altk + 1U, // VCMPPDZ128rmik + 18636U, // VCMPPDZ128rri + 18636U, // VCMPPDZ128rri_alt + 26837U, // VCMPPDZ128rri_altk + 26837U, // VCMPPDZ128rrik + 21860U, // VCMPPDZ256rmbi + 18637U, // VCMPPDZ256rmbi_alt + 26837U, // VCMPPDZ256rmbi_altk + 29989U, // VCMPPDZ256rmbik + 1U, // VCMPPDZ256rmi + 72U, // VCMPPDZ256rmi_alt + 1156U, // VCMPPDZ256rmi_altk + 2U, // VCMPPDZ256rmik + 18636U, // VCMPPDZ256rri + 18636U, // VCMPPDZ256rri_alt + 26837U, // VCMPPDZ256rri_altk + 26837U, // VCMPPDZ256rrik + 21864U, // VCMPPDZrmbi + 18637U, // VCMPPDZrmbi_alt + 26837U, // VCMPPDZrmbi_altk + 29993U, // VCMPPDZrmbik + 2U, // VCMPPDZrmi + 72U, // VCMPPDZrmi_alt + 1156U, // VCMPPDZrmi_altk + 2U, // VCMPPDZrmik + 18636U, // VCMPPDZrri + 18636U, // VCMPPDZrri_alt + 26837U, // VCMPPDZrri_altk + 18636U, // VCMPPDZrrib + 18636U, // VCMPPDZrrib_alt + 26837U, // VCMPPDZrrib_altk + 26837U, // VCMPPDZrribk + 26837U, // VCMPPDZrrik + 18636U, // VCMPPDrmi + 72U, // VCMPPDrmi_alt + 18636U, // VCMPPDrri + 18636U, // VCMPPDrri_alt + 1U, // VCMPPSYrmi + 72U, // VCMPPSYrmi_alt + 18636U, // VCMPPSYrri + 18636U, // VCMPPSYrri_alt + 21860U, // VCMPPSZ128rmbi + 18637U, // VCMPPSZ128rmbi_alt + 26837U, // VCMPPSZ128rmbi_altk + 29990U, // VCMPPSZ128rmbik + 18636U, // VCMPPSZ128rmi + 72U, // VCMPPSZ128rmi_alt + 1156U, // VCMPPSZ128rmi_altk + 1U, // VCMPPSZ128rmik + 18636U, // VCMPPSZ128rri + 18636U, // VCMPPSZ128rri_alt + 26837U, // VCMPPSZ128rri_altk + 26837U, // VCMPPSZ128rrik + 21864U, // VCMPPSZ256rmbi + 18637U, // VCMPPSZ256rmbi_alt + 26837U, // VCMPPSZ256rmbi_altk + 29994U, // VCMPPSZ256rmbik + 1U, // VCMPPSZ256rmi + 72U, // VCMPPSZ256rmi_alt + 1156U, // VCMPPSZ256rmi_altk + 2U, // VCMPPSZ256rmik + 18636U, // VCMPPSZ256rri + 18636U, // VCMPPSZ256rri_alt + 26837U, // VCMPPSZ256rri_altk + 26837U, // VCMPPSZ256rrik + 21868U, // VCMPPSZrmbi + 18637U, // VCMPPSZrmbi_alt + 26837U, // VCMPPSZrmbi_altk + 29998U, // VCMPPSZrmbik + 2U, // VCMPPSZrmi + 72U, // VCMPPSZrmi_alt + 1156U, // VCMPPSZrmi_altk + 2U, // VCMPPSZrmik + 18636U, // VCMPPSZrri + 18636U, // VCMPPSZrri_alt + 26837U, // VCMPPSZrri_altk + 18636U, // VCMPPSZrrib + 18636U, // VCMPPSZrrib_alt + 26837U, // VCMPPSZrrib_altk + 26837U, // VCMPPSZrribk + 26837U, // VCMPPSZrrik + 18636U, // VCMPPSrmi + 72U, // VCMPPSrmi_alt + 18636U, // VCMPPSrri + 18636U, // VCMPPSrri_alt + 21832U, // VCMPSDZrm + 21832U, // VCMPSDZrm_Int + 29961U, // VCMPSDZrm_Intk + 18636U, // VCMPSDZrmi_alt + 26836U, // VCMPSDZrmi_altk + 18636U, // VCMPSDZrr + 18636U, // VCMPSDZrr_Int + 26837U, // VCMPSDZrr_Intk + 18636U, // VCMPSDZrrb_Int + 26837U, // VCMPSDZrrb_Intk + 18636U, // VCMPSDZrrb_alt + 26837U, // VCMPSDZrrb_altk + 18636U, // VCMPSDZrri_alt + 26837U, // VCMPSDZrri_altk + 21832U, // VCMPSDrm + 21832U, // VCMPSDrm_Int + 18636U, // VCMPSDrm_alt + 18636U, // VCMPSDrr + 18636U, // VCMPSDrr_Int + 18636U, // VCMPSDrr_alt + 21832U, // VCMPSSZrm + 21832U, // VCMPSSZrm_Int + 29962U, // VCMPSSZrm_Intk + 18636U, // VCMPSSZrmi_alt + 26836U, // VCMPSSZrmi_altk + 18636U, // VCMPSSZrr + 18636U, // VCMPSSZrr_Int + 26837U, // VCMPSSZrr_Intk + 18636U, // VCMPSSZrrb_Int + 26837U, // VCMPSSZrrb_Intk + 18636U, // VCMPSSZrrb_alt + 26837U, // VCMPSSZrrb_altk + 18636U, // VCMPSSZrri_alt + 26837U, // VCMPSSZrri_altk + 21832U, // VCMPSSrm + 21832U, // VCMPSSrm_Int + 18636U, // VCMPSSrm_alt + 18636U, // VCMPSSrr + 18636U, // VCMPSSrr_Int + 18636U, // VCMPSSrr_alt + 0U, // VCOMISDZrm + 0U, // VCOMISDZrm_Int + 0U, // VCOMISDZrr + 0U, // VCOMISDZrr_Int + 0U, // VCOMISDZrrb + 0U, // VCOMISDrm + 0U, // VCOMISDrm_Int + 0U, // VCOMISDrr + 0U, // VCOMISDrr_Int + 0U, // VCOMISSZrm + 0U, // VCOMISSZrm_Int + 0U, // VCOMISSZrr + 0U, // VCOMISSZrr_Int + 0U, // VCOMISSZrrb + 0U, // VCOMISSrm + 0U, // VCOMISSrm_Int + 0U, // VCOMISSrr + 0U, // VCOMISSrr_Int + 0U, // VCOMPRESSPDZ128mr + 49U, // VCOMPRESSPDZ128mrk + 0U, // VCOMPRESSPDZ128rr + 405U, // VCOMPRESSPDZ128rrk + 461U, // VCOMPRESSPDZ128rrkz + 0U, // VCOMPRESSPDZ256mr + 49U, // VCOMPRESSPDZ256mrk + 0U, // VCOMPRESSPDZ256rr + 405U, // VCOMPRESSPDZ256rrk + 461U, // VCOMPRESSPDZ256rrkz + 0U, // VCOMPRESSPDZmr + 49U, // VCOMPRESSPDZmrk + 0U, // VCOMPRESSPDZrr + 405U, // VCOMPRESSPDZrrk + 461U, // VCOMPRESSPDZrrkz + 0U, // VCOMPRESSPSZ128mr + 49U, // VCOMPRESSPSZ128mrk + 0U, // VCOMPRESSPSZ128rr + 405U, // VCOMPRESSPSZ128rrk + 461U, // VCOMPRESSPSZ128rrkz + 0U, // VCOMPRESSPSZ256mr + 49U, // VCOMPRESSPSZ256mrk + 0U, // VCOMPRESSPSZ256rr + 405U, // VCOMPRESSPSZ256rrk + 461U, // VCOMPRESSPSZ256rrkz + 0U, // VCOMPRESSPSZmr + 49U, // VCOMPRESSPSZmrk + 0U, // VCOMPRESSPSZrr + 405U, // VCOMPRESSPSZrrk + 461U, // VCOMPRESSPSZrrkz + 0U, // VCVTDQ2PDYrm + 0U, // VCVTDQ2PDYrr + 0U, // VCVTDQ2PDZ128rm + 0U, // VCVTDQ2PDZ128rmb + 3356U, // VCVTDQ2PDZ128rmbk + 4444U, // VCVTDQ2PDZ128rmbkz + 3356U, // VCVTDQ2PDZ128rmk + 4444U, // VCVTDQ2PDZ128rmkz + 0U, // VCVTDQ2PDZ128rr + 405U, // VCVTDQ2PDZ128rrk + 461U, // VCVTDQ2PDZ128rrkz + 0U, // VCVTDQ2PDZ256rm + 0U, // VCVTDQ2PDZ256rmb + 3356U, // VCVTDQ2PDZ256rmbk + 4444U, // VCVTDQ2PDZ256rmbkz + 405U, // VCVTDQ2PDZ256rmk + 461U, // VCVTDQ2PDZ256rmkz + 0U, // VCVTDQ2PDZ256rr + 405U, // VCVTDQ2PDZ256rrk + 461U, // VCVTDQ2PDZ256rrkz + 0U, // VCVTDQ2PDZrm + 0U, // VCVTDQ2PDZrmb + 3356U, // VCVTDQ2PDZrmbk + 4444U, // VCVTDQ2PDZrmbkz + 405U, // VCVTDQ2PDZrmk + 461U, // VCVTDQ2PDZrmkz + 0U, // VCVTDQ2PDZrr + 405U, // VCVTDQ2PDZrrk + 461U, // VCVTDQ2PDZrrkz + 0U, // VCVTDQ2PDrm + 0U, // VCVTDQ2PDrr + 0U, // VCVTDQ2PSYrm + 0U, // VCVTDQ2PSYrr + 0U, // VCVTDQ2PSZ128rm + 0U, // VCVTDQ2PSZ128rmb + 3356U, // VCVTDQ2PSZ128rmbk + 4444U, // VCVTDQ2PSZ128rmbkz + 405U, // VCVTDQ2PSZ128rmk + 461U, // VCVTDQ2PSZ128rmkz + 0U, // VCVTDQ2PSZ128rr + 405U, // VCVTDQ2PSZ128rrk + 461U, // VCVTDQ2PSZ128rrkz + 0U, // VCVTDQ2PSZ256rm + 0U, // VCVTDQ2PSZ256rmb + 3356U, // VCVTDQ2PSZ256rmbk + 4444U, // VCVTDQ2PSZ256rmbkz + 405U, // VCVTDQ2PSZ256rmk + 461U, // VCVTDQ2PSZ256rmkz + 0U, // VCVTDQ2PSZ256rr + 405U, // VCVTDQ2PSZ256rrk + 461U, // VCVTDQ2PSZ256rrkz + 0U, // VCVTDQ2PSZrm + 0U, // VCVTDQ2PSZrmb + 3356U, // VCVTDQ2PSZrmbk + 4444U, // VCVTDQ2PSZrmbkz + 405U, // VCVTDQ2PSZrmk + 461U, // VCVTDQ2PSZrmkz + 0U, // VCVTDQ2PSZrr + 0U, // VCVTDQ2PSZrrb + 405U, // VCVTDQ2PSZrrbk + 461U, // VCVTDQ2PSZrrbkz + 405U, // VCVTDQ2PSZrrk + 461U, // VCVTDQ2PSZrrkz + 0U, // VCVTDQ2PSrm + 0U, // VCVTDQ2PSrr + 0U, // VCVTPD2DQYrm + 0U, // VCVTPD2DQYrr + 0U, // VCVTPD2DQZ128rm + 0U, // VCVTPD2DQZ128rmb + 3356U, // VCVTPD2DQZ128rmbk + 4444U, // VCVTPD2DQZ128rmbkz + 405U, // VCVTPD2DQZ128rmk + 461U, // VCVTPD2DQZ128rmkz + 0U, // VCVTPD2DQZ128rr + 405U, // VCVTPD2DQZ128rrk + 461U, // VCVTPD2DQZ128rrkz + 0U, // VCVTPD2DQZ256rm + 0U, // VCVTPD2DQZ256rmb + 3356U, // VCVTPD2DQZ256rmbk + 4444U, // VCVTPD2DQZ256rmbkz + 405U, // VCVTPD2DQZ256rmk + 461U, // VCVTPD2DQZ256rmkz + 0U, // VCVTPD2DQZ256rr + 405U, // VCVTPD2DQZ256rrk + 461U, // VCVTPD2DQZ256rrkz + 0U, // VCVTPD2DQZrm + 0U, // VCVTPD2DQZrmb + 3356U, // VCVTPD2DQZrmbk + 4444U, // VCVTPD2DQZrmbkz + 405U, // VCVTPD2DQZrmk + 461U, // VCVTPD2DQZrmkz + 0U, // VCVTPD2DQZrr + 0U, // VCVTPD2DQZrrb + 405U, // VCVTPD2DQZrrbk + 461U, // VCVTPD2DQZrrbkz + 405U, // VCVTPD2DQZrrk + 461U, // VCVTPD2DQZrrkz + 0U, // VCVTPD2DQrm + 0U, // VCVTPD2DQrr + 0U, // VCVTPD2PSYrm + 0U, // VCVTPD2PSYrr + 0U, // VCVTPD2PSZ128rm + 0U, // VCVTPD2PSZ128rmb + 3356U, // VCVTPD2PSZ128rmbk + 4444U, // VCVTPD2PSZ128rmbkz + 405U, // VCVTPD2PSZ128rmk + 461U, // VCVTPD2PSZ128rmkz + 0U, // VCVTPD2PSZ128rr + 405U, // VCVTPD2PSZ128rrk + 461U, // VCVTPD2PSZ128rrkz + 0U, // VCVTPD2PSZ256rm + 0U, // VCVTPD2PSZ256rmb + 3356U, // VCVTPD2PSZ256rmbk + 4444U, // VCVTPD2PSZ256rmbkz + 405U, // VCVTPD2PSZ256rmk + 461U, // VCVTPD2PSZ256rmkz + 0U, // VCVTPD2PSZ256rr + 405U, // VCVTPD2PSZ256rrk + 461U, // VCVTPD2PSZ256rrkz + 0U, // VCVTPD2PSZrm + 0U, // VCVTPD2PSZrmb + 3356U, // VCVTPD2PSZrmbk + 4444U, // VCVTPD2PSZrmbkz + 405U, // VCVTPD2PSZrmk + 461U, // VCVTPD2PSZrmkz + 0U, // VCVTPD2PSZrr + 0U, // VCVTPD2PSZrrb + 405U, // VCVTPD2PSZrrbk + 461U, // VCVTPD2PSZrrbkz + 405U, // VCVTPD2PSZrrk + 461U, // VCVTPD2PSZrrkz + 0U, // VCVTPD2PSrm + 0U, // VCVTPD2PSrr + 0U, // VCVTPD2QQZ128rm + 0U, // VCVTPD2QQZ128rmb + 3356U, // VCVTPD2QQZ128rmbk + 4444U, // VCVTPD2QQZ128rmbkz + 405U, // VCVTPD2QQZ128rmk + 461U, // VCVTPD2QQZ128rmkz + 0U, // VCVTPD2QQZ128rr + 405U, // VCVTPD2QQZ128rrk + 461U, // VCVTPD2QQZ128rrkz + 0U, // VCVTPD2QQZ256rm + 0U, // VCVTPD2QQZ256rmb + 3356U, // VCVTPD2QQZ256rmbk + 4444U, // VCVTPD2QQZ256rmbkz + 405U, // VCVTPD2QQZ256rmk + 461U, // VCVTPD2QQZ256rmkz + 0U, // VCVTPD2QQZ256rr + 405U, // VCVTPD2QQZ256rrk + 461U, // VCVTPD2QQZ256rrkz + 0U, // VCVTPD2QQZrm + 0U, // VCVTPD2QQZrmb + 3356U, // VCVTPD2QQZrmbk + 4444U, // VCVTPD2QQZrmbkz + 405U, // VCVTPD2QQZrmk + 461U, // VCVTPD2QQZrmkz + 0U, // VCVTPD2QQZrr + 0U, // VCVTPD2QQZrrb + 405U, // VCVTPD2QQZrrbk + 461U, // VCVTPD2QQZrrbkz + 405U, // VCVTPD2QQZrrk + 461U, // VCVTPD2QQZrrkz + 0U, // VCVTPD2UDQZ128rm + 0U, // VCVTPD2UDQZ128rmb + 3356U, // VCVTPD2UDQZ128rmbk + 4444U, // VCVTPD2UDQZ128rmbkz + 405U, // VCVTPD2UDQZ128rmk + 461U, // VCVTPD2UDQZ128rmkz + 0U, // VCVTPD2UDQZ128rr + 405U, // VCVTPD2UDQZ128rrk + 461U, // VCVTPD2UDQZ128rrkz + 0U, // VCVTPD2UDQZ256rm + 0U, // VCVTPD2UDQZ256rmb + 3356U, // VCVTPD2UDQZ256rmbk + 4444U, // VCVTPD2UDQZ256rmbkz + 405U, // VCVTPD2UDQZ256rmk + 461U, // VCVTPD2UDQZ256rmkz + 0U, // VCVTPD2UDQZ256rr + 405U, // VCVTPD2UDQZ256rrk + 461U, // VCVTPD2UDQZ256rrkz + 0U, // VCVTPD2UDQZrm + 0U, // VCVTPD2UDQZrmb + 3356U, // VCVTPD2UDQZrmbk + 4444U, // VCVTPD2UDQZrmbkz + 405U, // VCVTPD2UDQZrmk + 461U, // VCVTPD2UDQZrmkz + 0U, // VCVTPD2UDQZrr + 0U, // VCVTPD2UDQZrrb + 405U, // VCVTPD2UDQZrrbk + 461U, // VCVTPD2UDQZrrbkz + 405U, // VCVTPD2UDQZrrk + 461U, // VCVTPD2UDQZrrkz + 0U, // VCVTPD2UQQZ128rm + 0U, // VCVTPD2UQQZ128rmb + 3356U, // VCVTPD2UQQZ128rmbk + 4444U, // VCVTPD2UQQZ128rmbkz + 405U, // VCVTPD2UQQZ128rmk + 461U, // VCVTPD2UQQZ128rmkz + 0U, // VCVTPD2UQQZ128rr + 405U, // VCVTPD2UQQZ128rrk + 461U, // VCVTPD2UQQZ128rrkz + 0U, // VCVTPD2UQQZ256rm + 0U, // VCVTPD2UQQZ256rmb + 3356U, // VCVTPD2UQQZ256rmbk + 4444U, // VCVTPD2UQQZ256rmbkz + 405U, // VCVTPD2UQQZ256rmk + 461U, // VCVTPD2UQQZ256rmkz + 0U, // VCVTPD2UQQZ256rr + 405U, // VCVTPD2UQQZ256rrk + 461U, // VCVTPD2UQQZ256rrkz + 0U, // VCVTPD2UQQZrm + 0U, // VCVTPD2UQQZrmb + 3356U, // VCVTPD2UQQZrmbk + 4444U, // VCVTPD2UQQZrmbkz + 405U, // VCVTPD2UQQZrmk + 461U, // VCVTPD2UQQZrmkz + 0U, // VCVTPD2UQQZrr + 0U, // VCVTPD2UQQZrrb + 405U, // VCVTPD2UQQZrrbk + 461U, // VCVTPD2UQQZrrbkz + 405U, // VCVTPD2UQQZrrk + 461U, // VCVTPD2UQQZrrkz + 0U, // VCVTPH2PSYrm + 0U, // VCVTPH2PSYrr + 0U, // VCVTPH2PSZ128rm + 3356U, // VCVTPH2PSZ128rmk + 4444U, // VCVTPH2PSZ128rmkz + 0U, // VCVTPH2PSZ128rr + 405U, // VCVTPH2PSZ128rrk + 461U, // VCVTPH2PSZ128rrkz + 0U, // VCVTPH2PSZ256rm + 405U, // VCVTPH2PSZ256rmk + 461U, // VCVTPH2PSZ256rmkz + 0U, // VCVTPH2PSZ256rr + 405U, // VCVTPH2PSZ256rrk + 461U, // VCVTPH2PSZ256rrkz + 0U, // VCVTPH2PSZrm + 405U, // VCVTPH2PSZrmk + 461U, // VCVTPH2PSZrmkz + 0U, // VCVTPH2PSZrr + 0U, // VCVTPH2PSZrrb + 405U, // VCVTPH2PSZrrbk + 461U, // VCVTPH2PSZrrbkz + 405U, // VCVTPH2PSZrrk + 461U, // VCVTPH2PSZrrkz + 0U, // VCVTPH2PSrm + 0U, // VCVTPH2PSrr + 0U, // VCVTPS2DQYrm + 0U, // VCVTPS2DQYrr + 0U, // VCVTPS2DQZ128rm + 0U, // VCVTPS2DQZ128rmb + 3356U, // VCVTPS2DQZ128rmbk + 4444U, // VCVTPS2DQZ128rmbkz + 405U, // VCVTPS2DQZ128rmk + 461U, // VCVTPS2DQZ128rmkz + 0U, // VCVTPS2DQZ128rr + 405U, // VCVTPS2DQZ128rrk + 461U, // VCVTPS2DQZ128rrkz + 0U, // VCVTPS2DQZ256rm + 0U, // VCVTPS2DQZ256rmb + 3356U, // VCVTPS2DQZ256rmbk + 4444U, // VCVTPS2DQZ256rmbkz + 405U, // VCVTPS2DQZ256rmk + 461U, // VCVTPS2DQZ256rmkz + 0U, // VCVTPS2DQZ256rr + 405U, // VCVTPS2DQZ256rrk + 461U, // VCVTPS2DQZ256rrkz + 0U, // VCVTPS2DQZrm + 0U, // VCVTPS2DQZrmb + 3356U, // VCVTPS2DQZrmbk + 4444U, // VCVTPS2DQZrmbkz + 405U, // VCVTPS2DQZrmk + 461U, // VCVTPS2DQZrmkz + 0U, // VCVTPS2DQZrr + 0U, // VCVTPS2DQZrrb + 405U, // VCVTPS2DQZrrbk + 461U, // VCVTPS2DQZrrbkz + 405U, // VCVTPS2DQZrrk + 461U, // VCVTPS2DQZrrkz + 0U, // VCVTPS2DQrm + 0U, // VCVTPS2DQrr + 0U, // VCVTPS2PDYrm + 0U, // VCVTPS2PDYrr + 0U, // VCVTPS2PDZ128rm + 0U, // VCVTPS2PDZ128rmb + 3356U, // VCVTPS2PDZ128rmbk + 4444U, // VCVTPS2PDZ128rmbkz + 3356U, // VCVTPS2PDZ128rmk + 4444U, // VCVTPS2PDZ128rmkz + 0U, // VCVTPS2PDZ128rr + 405U, // VCVTPS2PDZ128rrk + 461U, // VCVTPS2PDZ128rrkz + 0U, // VCVTPS2PDZ256rm + 0U, // VCVTPS2PDZ256rmb + 3356U, // VCVTPS2PDZ256rmbk + 4444U, // VCVTPS2PDZ256rmbkz + 405U, // VCVTPS2PDZ256rmk + 461U, // VCVTPS2PDZ256rmkz + 0U, // VCVTPS2PDZ256rr + 405U, // VCVTPS2PDZ256rrk + 461U, // VCVTPS2PDZ256rrkz + 0U, // VCVTPS2PDZrm + 0U, // VCVTPS2PDZrmb + 3356U, // VCVTPS2PDZrmbk + 4444U, // VCVTPS2PDZrmbkz + 405U, // VCVTPS2PDZrmk + 461U, // VCVTPS2PDZrmkz + 0U, // VCVTPS2PDZrr + 0U, // VCVTPS2PDZrrb + 405U, // VCVTPS2PDZrrbk + 461U, // VCVTPS2PDZrrbkz + 405U, // VCVTPS2PDZrrk + 461U, // VCVTPS2PDZrrkz + 0U, // VCVTPS2PDrm + 0U, // VCVTPS2PDrr + 2U, // VCVTPS2PHYmr + 72U, // VCVTPS2PHYrr + 2U, // VCVTPS2PHZ128mr + 542U, // VCVTPS2PHZ128mrk + 72U, // VCVTPS2PHZ128rr + 133U, // VCVTPS2PHZ128rrk + 9348U, // VCVTPS2PHZ128rrkz + 2U, // VCVTPS2PHZ256mr + 542U, // VCVTPS2PHZ256mrk + 72U, // VCVTPS2PHZ256rr + 133U, // VCVTPS2PHZ256rrk + 9348U, // VCVTPS2PHZ256rrkz + 2U, // VCVTPS2PHZmr + 542U, // VCVTPS2PHZmrk + 72U, // VCVTPS2PHZrr + 72U, // VCVTPS2PHZrrb + 133U, // VCVTPS2PHZrrbk + 9348U, // VCVTPS2PHZrrbkz + 133U, // VCVTPS2PHZrrk + 9348U, // VCVTPS2PHZrrkz + 2U, // VCVTPS2PHmr + 72U, // VCVTPS2PHrr + 0U, // VCVTPS2QQZ128rm + 0U, // VCVTPS2QQZ128rmb + 3356U, // VCVTPS2QQZ128rmbk + 4444U, // VCVTPS2QQZ128rmbkz + 3356U, // VCVTPS2QQZ128rmk + 4444U, // VCVTPS2QQZ128rmkz + 0U, // VCVTPS2QQZ128rr + 405U, // VCVTPS2QQZ128rrk + 461U, // VCVTPS2QQZ128rrkz + 0U, // VCVTPS2QQZ256rm + 0U, // VCVTPS2QQZ256rmb + 3356U, // VCVTPS2QQZ256rmbk + 4444U, // VCVTPS2QQZ256rmbkz + 405U, // VCVTPS2QQZ256rmk + 461U, // VCVTPS2QQZ256rmkz + 0U, // VCVTPS2QQZ256rr + 405U, // VCVTPS2QQZ256rrk + 461U, // VCVTPS2QQZ256rrkz + 0U, // VCVTPS2QQZrm + 0U, // VCVTPS2QQZrmb + 3356U, // VCVTPS2QQZrmbk + 4444U, // VCVTPS2QQZrmbkz + 405U, // VCVTPS2QQZrmk + 461U, // VCVTPS2QQZrmkz + 0U, // VCVTPS2QQZrr + 0U, // VCVTPS2QQZrrb + 405U, // VCVTPS2QQZrrbk + 461U, // VCVTPS2QQZrrbkz + 405U, // VCVTPS2QQZrrk + 461U, // VCVTPS2QQZrrkz + 0U, // VCVTPS2UDQZ128rm + 0U, // VCVTPS2UDQZ128rmb + 3356U, // VCVTPS2UDQZ128rmbk + 4444U, // VCVTPS2UDQZ128rmbkz + 405U, // VCVTPS2UDQZ128rmk + 461U, // VCVTPS2UDQZ128rmkz + 0U, // VCVTPS2UDQZ128rr + 405U, // VCVTPS2UDQZ128rrk + 461U, // VCVTPS2UDQZ128rrkz + 0U, // VCVTPS2UDQZ256rm + 0U, // VCVTPS2UDQZ256rmb + 3356U, // VCVTPS2UDQZ256rmbk + 4444U, // VCVTPS2UDQZ256rmbkz + 405U, // VCVTPS2UDQZ256rmk + 461U, // VCVTPS2UDQZ256rmkz + 0U, // VCVTPS2UDQZ256rr + 405U, // VCVTPS2UDQZ256rrk + 461U, // VCVTPS2UDQZ256rrkz + 0U, // VCVTPS2UDQZrm + 0U, // VCVTPS2UDQZrmb + 3356U, // VCVTPS2UDQZrmbk + 4444U, // VCVTPS2UDQZrmbkz + 405U, // VCVTPS2UDQZrmk + 461U, // VCVTPS2UDQZrmkz + 0U, // VCVTPS2UDQZrr + 0U, // VCVTPS2UDQZrrb + 405U, // VCVTPS2UDQZrrbk + 461U, // VCVTPS2UDQZrrbkz + 405U, // VCVTPS2UDQZrrk + 461U, // VCVTPS2UDQZrrkz + 0U, // VCVTPS2UQQZ128rm + 0U, // VCVTPS2UQQZ128rmb + 3356U, // VCVTPS2UQQZ128rmbk + 4444U, // VCVTPS2UQQZ128rmbkz + 3356U, // VCVTPS2UQQZ128rmk + 4444U, // VCVTPS2UQQZ128rmkz + 0U, // VCVTPS2UQQZ128rr + 405U, // VCVTPS2UQQZ128rrk + 461U, // VCVTPS2UQQZ128rrkz + 0U, // VCVTPS2UQQZ256rm + 0U, // VCVTPS2UQQZ256rmb + 3356U, // VCVTPS2UQQZ256rmbk + 4444U, // VCVTPS2UQQZ256rmbkz + 405U, // VCVTPS2UQQZ256rmk + 461U, // VCVTPS2UQQZ256rmkz + 0U, // VCVTPS2UQQZ256rr + 405U, // VCVTPS2UQQZ256rrk + 461U, // VCVTPS2UQQZ256rrkz + 0U, // VCVTPS2UQQZrm + 0U, // VCVTPS2UQQZrmb + 3356U, // VCVTPS2UQQZrmbk + 4444U, // VCVTPS2UQQZrmbkz + 405U, // VCVTPS2UQQZrmk + 461U, // VCVTPS2UQQZrmkz + 0U, // VCVTPS2UQQZrr + 0U, // VCVTPS2UQQZrrb + 405U, // VCVTPS2UQQZrrbk + 461U, // VCVTPS2UQQZrrbkz + 405U, // VCVTPS2UQQZrrk + 461U, // VCVTPS2UQQZrrkz + 0U, // VCVTQQ2PDZ128rm + 0U, // VCVTQQ2PDZ128rmb + 3356U, // VCVTQQ2PDZ128rmbk + 4444U, // VCVTQQ2PDZ128rmbkz + 405U, // VCVTQQ2PDZ128rmk + 461U, // VCVTQQ2PDZ128rmkz + 0U, // VCVTQQ2PDZ128rr + 405U, // VCVTQQ2PDZ128rrk + 461U, // VCVTQQ2PDZ128rrkz + 0U, // VCVTQQ2PDZ256rm + 0U, // VCVTQQ2PDZ256rmb + 3356U, // VCVTQQ2PDZ256rmbk + 4444U, // VCVTQQ2PDZ256rmbkz + 405U, // VCVTQQ2PDZ256rmk + 461U, // VCVTQQ2PDZ256rmkz + 0U, // VCVTQQ2PDZ256rr + 405U, // VCVTQQ2PDZ256rrk + 461U, // VCVTQQ2PDZ256rrkz + 0U, // VCVTQQ2PDZrm + 0U, // VCVTQQ2PDZrmb + 3356U, // VCVTQQ2PDZrmbk + 4444U, // VCVTQQ2PDZrmbkz + 405U, // VCVTQQ2PDZrmk + 461U, // VCVTQQ2PDZrmkz + 0U, // VCVTQQ2PDZrr + 0U, // VCVTQQ2PDZrrb + 405U, // VCVTQQ2PDZrrbk + 461U, // VCVTQQ2PDZrrbkz + 405U, // VCVTQQ2PDZrrk + 461U, // VCVTQQ2PDZrrkz + 0U, // VCVTQQ2PSZ128rm + 0U, // VCVTQQ2PSZ128rmb + 3356U, // VCVTQQ2PSZ128rmbk + 4444U, // VCVTQQ2PSZ128rmbkz + 405U, // VCVTQQ2PSZ128rmk + 461U, // VCVTQQ2PSZ128rmkz + 0U, // VCVTQQ2PSZ128rr + 405U, // VCVTQQ2PSZ128rrk + 461U, // VCVTQQ2PSZ128rrkz + 0U, // VCVTQQ2PSZ256rm + 0U, // VCVTQQ2PSZ256rmb + 3356U, // VCVTQQ2PSZ256rmbk + 4444U, // VCVTQQ2PSZ256rmbkz + 405U, // VCVTQQ2PSZ256rmk + 461U, // VCVTQQ2PSZ256rmkz + 0U, // VCVTQQ2PSZ256rr + 405U, // VCVTQQ2PSZ256rrk + 461U, // VCVTQQ2PSZ256rrkz + 0U, // VCVTQQ2PSZrm + 0U, // VCVTQQ2PSZrmb + 3356U, // VCVTQQ2PSZrmbk + 4444U, // VCVTQQ2PSZrmbkz + 405U, // VCVTQQ2PSZrmk + 461U, // VCVTQQ2PSZrmkz + 0U, // VCVTQQ2PSZrr + 0U, // VCVTQQ2PSZrrb + 405U, // VCVTQQ2PSZrrbk + 461U, // VCVTQQ2PSZrrbkz + 405U, // VCVTQQ2PSZrrk + 461U, // VCVTQQ2PSZrrkz + 0U, // VCVTSD2SI64Zrm_Int + 0U, // VCVTSD2SI64Zrr_Int + 0U, // VCVTSD2SI64Zrrb_Int + 0U, // VCVTSD2SI64rm_Int + 0U, // VCVTSD2SI64rr_Int + 0U, // VCVTSD2SIZrm_Int + 0U, // VCVTSD2SIZrr_Int + 0U, // VCVTSD2SIZrrb_Int + 0U, // VCVTSD2SIrm_Int + 0U, // VCVTSD2SIrr_Int + 72U, // VCVTSD2SSZrm + 72U, // VCVTSD2SSZrm_Int + 133U, // VCVTSD2SSZrm_Intk + 9348U, // VCVTSD2SSZrm_Intkz + 4U, // VCVTSD2SSZrr + 4U, // VCVTSD2SSZrr_Int + 0U, // VCVTSD2SSZrr_Intk + 9348U, // VCVTSD2SSZrr_Intkz + 4U, // VCVTSD2SSZrrb_Int + 0U, // VCVTSD2SSZrrb_Intk + 9348U, // VCVTSD2SSZrrb_Intkz + 72U, // VCVTSD2SSrm + 72U, // VCVTSD2SSrm_Int + 4U, // VCVTSD2SSrr + 4U, // VCVTSD2SSrr_Int + 0U, // VCVTSD2USI64Zrm_Int + 0U, // VCVTSD2USI64Zrr_Int + 0U, // VCVTSD2USI64Zrrb_Int + 0U, // VCVTSD2USIZrm_Int + 0U, // VCVTSD2USIZrr_Int + 0U, // VCVTSD2USIZrrb_Int + 72U, // VCVTSI2SDZrm + 72U, // VCVTSI2SDZrm_Int + 4U, // VCVTSI2SDZrr + 4U, // VCVTSI2SDZrr_Int + 0U, // VCVTSI2SDZrrb_Int + 72U, // VCVTSI2SDrm + 72U, // VCVTSI2SDrm_Int + 4U, // VCVTSI2SDrr + 4U, // VCVTSI2SDrr_Int + 72U, // VCVTSI2SSZrm + 72U, // VCVTSI2SSZrm_Int + 4U, // VCVTSI2SSZrr + 4U, // VCVTSI2SSZrr_Int + 0U, // VCVTSI2SSZrrb_Int + 72U, // VCVTSI2SSrm + 72U, // VCVTSI2SSrm_Int + 4U, // VCVTSI2SSrr + 4U, // VCVTSI2SSrr_Int + 72U, // VCVTSI642SDZrm + 72U, // VCVTSI642SDZrm_Int + 4U, // VCVTSI642SDZrr + 4U, // VCVTSI642SDZrr_Int + 0U, // VCVTSI642SDZrrb_Int + 72U, // VCVTSI642SDrm + 72U, // VCVTSI642SDrm_Int + 4U, // VCVTSI642SDrr + 4U, // VCVTSI642SDrr_Int + 72U, // VCVTSI642SSZrm + 72U, // VCVTSI642SSZrm_Int + 4U, // VCVTSI642SSZrr + 4U, // VCVTSI642SSZrr_Int + 0U, // VCVTSI642SSZrrb_Int + 72U, // VCVTSI642SSrm + 72U, // VCVTSI642SSrm_Int + 4U, // VCVTSI642SSrr + 4U, // VCVTSI642SSrr_Int + 72U, // VCVTSS2SDZrm + 72U, // VCVTSS2SDZrm_Int + 133U, // VCVTSS2SDZrm_Intk + 9348U, // VCVTSS2SDZrm_Intkz + 4U, // VCVTSS2SDZrr + 4U, // VCVTSS2SDZrr_Int + 0U, // VCVTSS2SDZrr_Intk + 9348U, // VCVTSS2SDZrr_Intkz + 4U, // VCVTSS2SDZrrb_Int + 0U, // VCVTSS2SDZrrb_Intk + 9348U, // VCVTSS2SDZrrb_Intkz + 72U, // VCVTSS2SDrm + 72U, // VCVTSS2SDrm_Int + 4U, // VCVTSS2SDrr + 4U, // VCVTSS2SDrr_Int + 0U, // VCVTSS2SI64Zrm_Int + 0U, // VCVTSS2SI64Zrr_Int + 0U, // VCVTSS2SI64Zrrb_Int + 0U, // VCVTSS2SI64rm_Int + 0U, // VCVTSS2SI64rr_Int + 0U, // VCVTSS2SIZrm_Int + 0U, // VCVTSS2SIZrr_Int + 0U, // VCVTSS2SIZrrb_Int + 0U, // VCVTSS2SIrm_Int + 0U, // VCVTSS2SIrr_Int + 0U, // VCVTSS2USI64Zrm_Int + 0U, // VCVTSS2USI64Zrr_Int + 0U, // VCVTSS2USI64Zrrb_Int + 0U, // VCVTSS2USIZrm_Int + 0U, // VCVTSS2USIZrr_Int + 0U, // VCVTSS2USIZrrb_Int + 0U, // VCVTTPD2DQYrm + 0U, // VCVTTPD2DQYrr + 0U, // VCVTTPD2DQZ128rm + 0U, // VCVTTPD2DQZ128rmb + 3356U, // VCVTTPD2DQZ128rmbk + 4444U, // VCVTTPD2DQZ128rmbkz + 405U, // VCVTTPD2DQZ128rmk + 461U, // VCVTTPD2DQZ128rmkz + 0U, // VCVTTPD2DQZ128rr + 405U, // VCVTTPD2DQZ128rrk + 461U, // VCVTTPD2DQZ128rrkz + 0U, // VCVTTPD2DQZ256rm + 0U, // VCVTTPD2DQZ256rmb + 3356U, // VCVTTPD2DQZ256rmbk + 4444U, // VCVTTPD2DQZ256rmbkz + 405U, // VCVTTPD2DQZ256rmk + 461U, // VCVTTPD2DQZ256rmkz + 0U, // VCVTTPD2DQZ256rr + 405U, // VCVTTPD2DQZ256rrk + 461U, // VCVTTPD2DQZ256rrkz + 0U, // VCVTTPD2DQZrm + 0U, // VCVTTPD2DQZrmb + 3356U, // VCVTTPD2DQZrmbk + 4444U, // VCVTTPD2DQZrmbkz + 405U, // VCVTTPD2DQZrmk + 461U, // VCVTTPD2DQZrmkz + 0U, // VCVTTPD2DQZrr + 0U, // VCVTTPD2DQZrrb + 405U, // VCVTTPD2DQZrrbk + 461U, // VCVTTPD2DQZrrbkz + 405U, // VCVTTPD2DQZrrk + 461U, // VCVTTPD2DQZrrkz + 0U, // VCVTTPD2DQrm + 0U, // VCVTTPD2DQrr + 0U, // VCVTTPD2QQZ128rm + 0U, // VCVTTPD2QQZ128rmb + 3356U, // VCVTTPD2QQZ128rmbk + 4444U, // VCVTTPD2QQZ128rmbkz + 405U, // VCVTTPD2QQZ128rmk + 461U, // VCVTTPD2QQZ128rmkz + 0U, // VCVTTPD2QQZ128rr + 405U, // VCVTTPD2QQZ128rrk + 461U, // VCVTTPD2QQZ128rrkz + 0U, // VCVTTPD2QQZ256rm + 0U, // VCVTTPD2QQZ256rmb + 3356U, // VCVTTPD2QQZ256rmbk + 4444U, // VCVTTPD2QQZ256rmbkz + 405U, // VCVTTPD2QQZ256rmk + 461U, // VCVTTPD2QQZ256rmkz + 0U, // VCVTTPD2QQZ256rr + 405U, // VCVTTPD2QQZ256rrk + 461U, // VCVTTPD2QQZ256rrkz + 0U, // VCVTTPD2QQZrm + 0U, // VCVTTPD2QQZrmb + 3356U, // VCVTTPD2QQZrmbk + 4444U, // VCVTTPD2QQZrmbkz + 405U, // VCVTTPD2QQZrmk + 461U, // VCVTTPD2QQZrmkz + 0U, // VCVTTPD2QQZrr + 0U, // VCVTTPD2QQZrrb + 405U, // VCVTTPD2QQZrrbk + 461U, // VCVTTPD2QQZrrbkz + 405U, // VCVTTPD2QQZrrk + 461U, // VCVTTPD2QQZrrkz + 0U, // VCVTTPD2UDQZ128rm + 0U, // VCVTTPD2UDQZ128rmb + 3356U, // VCVTTPD2UDQZ128rmbk + 4444U, // VCVTTPD2UDQZ128rmbkz + 405U, // VCVTTPD2UDQZ128rmk + 461U, // VCVTTPD2UDQZ128rmkz + 0U, // VCVTTPD2UDQZ128rr + 405U, // VCVTTPD2UDQZ128rrk + 461U, // VCVTTPD2UDQZ128rrkz + 0U, // VCVTTPD2UDQZ256rm + 0U, // VCVTTPD2UDQZ256rmb + 3356U, // VCVTTPD2UDQZ256rmbk + 4444U, // VCVTTPD2UDQZ256rmbkz + 405U, // VCVTTPD2UDQZ256rmk + 461U, // VCVTTPD2UDQZ256rmkz + 0U, // VCVTTPD2UDQZ256rr + 405U, // VCVTTPD2UDQZ256rrk + 461U, // VCVTTPD2UDQZ256rrkz + 0U, // VCVTTPD2UDQZrm + 0U, // VCVTTPD2UDQZrmb + 3356U, // VCVTTPD2UDQZrmbk + 4444U, // VCVTTPD2UDQZrmbkz + 405U, // VCVTTPD2UDQZrmk + 461U, // VCVTTPD2UDQZrmkz + 0U, // VCVTTPD2UDQZrr + 0U, // VCVTTPD2UDQZrrb + 405U, // VCVTTPD2UDQZrrbk + 461U, // VCVTTPD2UDQZrrbkz + 405U, // VCVTTPD2UDQZrrk + 461U, // VCVTTPD2UDQZrrkz + 0U, // VCVTTPD2UQQZ128rm + 0U, // VCVTTPD2UQQZ128rmb + 3356U, // VCVTTPD2UQQZ128rmbk + 4444U, // VCVTTPD2UQQZ128rmbkz + 405U, // VCVTTPD2UQQZ128rmk + 461U, // VCVTTPD2UQQZ128rmkz + 0U, // VCVTTPD2UQQZ128rr + 405U, // VCVTTPD2UQQZ128rrk + 461U, // VCVTTPD2UQQZ128rrkz + 0U, // VCVTTPD2UQQZ256rm + 0U, // VCVTTPD2UQQZ256rmb + 3356U, // VCVTTPD2UQQZ256rmbk + 4444U, // VCVTTPD2UQQZ256rmbkz + 405U, // VCVTTPD2UQQZ256rmk + 461U, // VCVTTPD2UQQZ256rmkz + 0U, // VCVTTPD2UQQZ256rr + 405U, // VCVTTPD2UQQZ256rrk + 461U, // VCVTTPD2UQQZ256rrkz + 0U, // VCVTTPD2UQQZrm + 0U, // VCVTTPD2UQQZrmb + 3356U, // VCVTTPD2UQQZrmbk + 4444U, // VCVTTPD2UQQZrmbkz + 405U, // VCVTTPD2UQQZrmk + 461U, // VCVTTPD2UQQZrmkz + 0U, // VCVTTPD2UQQZrr + 0U, // VCVTTPD2UQQZrrb + 405U, // VCVTTPD2UQQZrrbk + 461U, // VCVTTPD2UQQZrrbkz + 405U, // VCVTTPD2UQQZrrk + 461U, // VCVTTPD2UQQZrrkz + 0U, // VCVTTPS2DQYrm + 0U, // VCVTTPS2DQYrr + 0U, // VCVTTPS2DQZ128rm + 0U, // VCVTTPS2DQZ128rmb + 3356U, // VCVTTPS2DQZ128rmbk + 4444U, // VCVTTPS2DQZ128rmbkz + 405U, // VCVTTPS2DQZ128rmk + 461U, // VCVTTPS2DQZ128rmkz + 0U, // VCVTTPS2DQZ128rr + 405U, // VCVTTPS2DQZ128rrk + 461U, // VCVTTPS2DQZ128rrkz + 0U, // VCVTTPS2DQZ256rm + 0U, // VCVTTPS2DQZ256rmb + 3356U, // VCVTTPS2DQZ256rmbk + 4444U, // VCVTTPS2DQZ256rmbkz + 405U, // VCVTTPS2DQZ256rmk + 461U, // VCVTTPS2DQZ256rmkz + 0U, // VCVTTPS2DQZ256rr + 405U, // VCVTTPS2DQZ256rrk + 461U, // VCVTTPS2DQZ256rrkz + 0U, // VCVTTPS2DQZrm + 0U, // VCVTTPS2DQZrmb + 3356U, // VCVTTPS2DQZrmbk + 4444U, // VCVTTPS2DQZrmbkz + 405U, // VCVTTPS2DQZrmk + 461U, // VCVTTPS2DQZrmkz + 0U, // VCVTTPS2DQZrr + 0U, // VCVTTPS2DQZrrb + 405U, // VCVTTPS2DQZrrbk + 461U, // VCVTTPS2DQZrrbkz + 405U, // VCVTTPS2DQZrrk + 461U, // VCVTTPS2DQZrrkz + 0U, // VCVTTPS2DQrm + 0U, // VCVTTPS2DQrr + 0U, // VCVTTPS2QQZ128rm + 0U, // VCVTTPS2QQZ128rmb + 3356U, // VCVTTPS2QQZ128rmbk + 4444U, // VCVTTPS2QQZ128rmbkz + 3356U, // VCVTTPS2QQZ128rmk + 4444U, // VCVTTPS2QQZ128rmkz + 0U, // VCVTTPS2QQZ128rr + 405U, // VCVTTPS2QQZ128rrk + 461U, // VCVTTPS2QQZ128rrkz + 0U, // VCVTTPS2QQZ256rm + 0U, // VCVTTPS2QQZ256rmb + 3356U, // VCVTTPS2QQZ256rmbk + 4444U, // VCVTTPS2QQZ256rmbkz + 405U, // VCVTTPS2QQZ256rmk + 461U, // VCVTTPS2QQZ256rmkz + 0U, // VCVTTPS2QQZ256rr + 405U, // VCVTTPS2QQZ256rrk + 461U, // VCVTTPS2QQZ256rrkz + 0U, // VCVTTPS2QQZrm + 0U, // VCVTTPS2QQZrmb + 3356U, // VCVTTPS2QQZrmbk + 4444U, // VCVTTPS2QQZrmbkz + 405U, // VCVTTPS2QQZrmk + 461U, // VCVTTPS2QQZrmkz + 0U, // VCVTTPS2QQZrr + 0U, // VCVTTPS2QQZrrb + 405U, // VCVTTPS2QQZrrbk + 461U, // VCVTTPS2QQZrrbkz + 405U, // VCVTTPS2QQZrrk + 461U, // VCVTTPS2QQZrrkz + 0U, // VCVTTPS2UDQZ128rm + 0U, // VCVTTPS2UDQZ128rmb + 3356U, // VCVTTPS2UDQZ128rmbk + 4444U, // VCVTTPS2UDQZ128rmbkz + 405U, // VCVTTPS2UDQZ128rmk + 461U, // VCVTTPS2UDQZ128rmkz + 0U, // VCVTTPS2UDQZ128rr + 405U, // VCVTTPS2UDQZ128rrk + 461U, // VCVTTPS2UDQZ128rrkz + 0U, // VCVTTPS2UDQZ256rm + 0U, // VCVTTPS2UDQZ256rmb + 3356U, // VCVTTPS2UDQZ256rmbk + 4444U, // VCVTTPS2UDQZ256rmbkz + 405U, // VCVTTPS2UDQZ256rmk + 461U, // VCVTTPS2UDQZ256rmkz + 0U, // VCVTTPS2UDQZ256rr + 405U, // VCVTTPS2UDQZ256rrk + 461U, // VCVTTPS2UDQZ256rrkz + 0U, // VCVTTPS2UDQZrm + 0U, // VCVTTPS2UDQZrmb + 3356U, // VCVTTPS2UDQZrmbk + 4444U, // VCVTTPS2UDQZrmbkz + 405U, // VCVTTPS2UDQZrmk + 461U, // VCVTTPS2UDQZrmkz + 0U, // VCVTTPS2UDQZrr + 0U, // VCVTTPS2UDQZrrb + 405U, // VCVTTPS2UDQZrrbk + 461U, // VCVTTPS2UDQZrrbkz + 405U, // VCVTTPS2UDQZrrk + 461U, // VCVTTPS2UDQZrrkz + 0U, // VCVTTPS2UQQZ128rm + 0U, // VCVTTPS2UQQZ128rmb + 3356U, // VCVTTPS2UQQZ128rmbk + 4444U, // VCVTTPS2UQQZ128rmbkz + 3356U, // VCVTTPS2UQQZ128rmk + 4444U, // VCVTTPS2UQQZ128rmkz + 0U, // VCVTTPS2UQQZ128rr + 405U, // VCVTTPS2UQQZ128rrk + 461U, // VCVTTPS2UQQZ128rrkz + 0U, // VCVTTPS2UQQZ256rm + 0U, // VCVTTPS2UQQZ256rmb + 3356U, // VCVTTPS2UQQZ256rmbk + 4444U, // VCVTTPS2UQQZ256rmbkz + 405U, // VCVTTPS2UQQZ256rmk + 461U, // VCVTTPS2UQQZ256rmkz + 0U, // VCVTTPS2UQQZ256rr + 405U, // VCVTTPS2UQQZ256rrk + 461U, // VCVTTPS2UQQZ256rrkz + 0U, // VCVTTPS2UQQZrm + 0U, // VCVTTPS2UQQZrmb + 3356U, // VCVTTPS2UQQZrmbk + 4444U, // VCVTTPS2UQQZrmbkz + 405U, // VCVTTPS2UQQZrmk + 461U, // VCVTTPS2UQQZrmkz + 0U, // VCVTTPS2UQQZrr + 0U, // VCVTTPS2UQQZrrb + 405U, // VCVTTPS2UQQZrrbk + 461U, // VCVTTPS2UQQZrrbkz + 405U, // VCVTTPS2UQQZrrk + 461U, // VCVTTPS2UQQZrrkz + 0U, // VCVTTSD2SI64Zrm + 0U, // VCVTTSD2SI64Zrm_Int + 0U, // VCVTTSD2SI64Zrr + 0U, // VCVTTSD2SI64Zrr_Int + 0U, // VCVTTSD2SI64Zrrb_Int + 0U, // VCVTTSD2SI64rm + 0U, // VCVTTSD2SI64rm_Int + 0U, // VCVTTSD2SI64rr + 0U, // VCVTTSD2SI64rr_Int + 0U, // VCVTTSD2SIZrm + 0U, // VCVTTSD2SIZrm_Int + 0U, // VCVTTSD2SIZrr + 0U, // VCVTTSD2SIZrr_Int + 0U, // VCVTTSD2SIZrrb_Int + 0U, // VCVTTSD2SIrm + 0U, // VCVTTSD2SIrm_Int + 0U, // VCVTTSD2SIrr + 0U, // VCVTTSD2SIrr_Int + 0U, // VCVTTSD2USI64Zrm + 0U, // VCVTTSD2USI64Zrm_Int + 0U, // VCVTTSD2USI64Zrr + 0U, // VCVTTSD2USI64Zrr_Int + 0U, // VCVTTSD2USI64Zrrb_Int + 0U, // VCVTTSD2USIZrm + 0U, // VCVTTSD2USIZrm_Int + 0U, // VCVTTSD2USIZrr + 0U, // VCVTTSD2USIZrr_Int + 0U, // VCVTTSD2USIZrrb_Int + 0U, // VCVTTSS2SI64Zrm + 0U, // VCVTTSS2SI64Zrm_Int + 0U, // VCVTTSS2SI64Zrr + 0U, // VCVTTSS2SI64Zrr_Int + 0U, // VCVTTSS2SI64Zrrb_Int + 0U, // VCVTTSS2SI64rm + 0U, // VCVTTSS2SI64rm_Int + 0U, // VCVTTSS2SI64rr + 0U, // VCVTTSS2SI64rr_Int + 0U, // VCVTTSS2SIZrm + 0U, // VCVTTSS2SIZrm_Int + 0U, // VCVTTSS2SIZrr + 0U, // VCVTTSS2SIZrr_Int + 0U, // VCVTTSS2SIZrrb_Int + 0U, // VCVTTSS2SIrm + 0U, // VCVTTSS2SIrm_Int + 0U, // VCVTTSS2SIrr + 0U, // VCVTTSS2SIrr_Int + 0U, // VCVTTSS2USI64Zrm + 0U, // VCVTTSS2USI64Zrm_Int + 0U, // VCVTTSS2USI64Zrr + 0U, // VCVTTSS2USI64Zrr_Int + 0U, // VCVTTSS2USI64Zrrb_Int + 0U, // VCVTTSS2USIZrm + 0U, // VCVTTSS2USIZrm_Int + 0U, // VCVTTSS2USIZrr + 0U, // VCVTTSS2USIZrr_Int + 0U, // VCVTTSS2USIZrrb_Int + 0U, // VCVTUDQ2PDZ128rm + 0U, // VCVTUDQ2PDZ128rmb + 3356U, // VCVTUDQ2PDZ128rmbk + 4444U, // VCVTUDQ2PDZ128rmbkz + 3356U, // VCVTUDQ2PDZ128rmk + 4444U, // VCVTUDQ2PDZ128rmkz + 0U, // VCVTUDQ2PDZ128rr + 405U, // VCVTUDQ2PDZ128rrk + 461U, // VCVTUDQ2PDZ128rrkz + 0U, // VCVTUDQ2PDZ256rm + 0U, // VCVTUDQ2PDZ256rmb + 3356U, // VCVTUDQ2PDZ256rmbk + 4444U, // VCVTUDQ2PDZ256rmbkz + 405U, // VCVTUDQ2PDZ256rmk + 461U, // VCVTUDQ2PDZ256rmkz + 0U, // VCVTUDQ2PDZ256rr + 405U, // VCVTUDQ2PDZ256rrk + 461U, // VCVTUDQ2PDZ256rrkz + 0U, // VCVTUDQ2PDZrm + 0U, // VCVTUDQ2PDZrmb + 3356U, // VCVTUDQ2PDZrmbk + 4444U, // VCVTUDQ2PDZrmbkz + 405U, // VCVTUDQ2PDZrmk + 461U, // VCVTUDQ2PDZrmkz + 0U, // VCVTUDQ2PDZrr + 405U, // VCVTUDQ2PDZrrk + 461U, // VCVTUDQ2PDZrrkz + 0U, // VCVTUDQ2PSZ128rm + 0U, // VCVTUDQ2PSZ128rmb + 3356U, // VCVTUDQ2PSZ128rmbk + 4444U, // VCVTUDQ2PSZ128rmbkz + 405U, // VCVTUDQ2PSZ128rmk + 461U, // VCVTUDQ2PSZ128rmkz + 0U, // VCVTUDQ2PSZ128rr + 405U, // VCVTUDQ2PSZ128rrk + 461U, // VCVTUDQ2PSZ128rrkz + 0U, // VCVTUDQ2PSZ256rm + 0U, // VCVTUDQ2PSZ256rmb + 3356U, // VCVTUDQ2PSZ256rmbk + 4444U, // VCVTUDQ2PSZ256rmbkz + 405U, // VCVTUDQ2PSZ256rmk + 461U, // VCVTUDQ2PSZ256rmkz + 0U, // VCVTUDQ2PSZ256rr + 405U, // VCVTUDQ2PSZ256rrk + 461U, // VCVTUDQ2PSZ256rrkz + 0U, // VCVTUDQ2PSZrm + 0U, // VCVTUDQ2PSZrmb + 3356U, // VCVTUDQ2PSZrmbk + 4444U, // VCVTUDQ2PSZrmbkz + 405U, // VCVTUDQ2PSZrmk + 461U, // VCVTUDQ2PSZrmkz + 0U, // VCVTUDQ2PSZrr + 0U, // VCVTUDQ2PSZrrb + 405U, // VCVTUDQ2PSZrrbk + 461U, // VCVTUDQ2PSZrrbkz + 405U, // VCVTUDQ2PSZrrk + 461U, // VCVTUDQ2PSZrrkz + 0U, // VCVTUQQ2PDZ128rm + 0U, // VCVTUQQ2PDZ128rmb + 3356U, // VCVTUQQ2PDZ128rmbk + 4444U, // VCVTUQQ2PDZ128rmbkz + 405U, // VCVTUQQ2PDZ128rmk + 461U, // VCVTUQQ2PDZ128rmkz + 0U, // VCVTUQQ2PDZ128rr + 405U, // VCVTUQQ2PDZ128rrk + 461U, // VCVTUQQ2PDZ128rrkz + 0U, // VCVTUQQ2PDZ256rm + 0U, // VCVTUQQ2PDZ256rmb + 3356U, // VCVTUQQ2PDZ256rmbk + 4444U, // VCVTUQQ2PDZ256rmbkz + 405U, // VCVTUQQ2PDZ256rmk + 461U, // VCVTUQQ2PDZ256rmkz + 0U, // VCVTUQQ2PDZ256rr + 405U, // VCVTUQQ2PDZ256rrk + 461U, // VCVTUQQ2PDZ256rrkz + 0U, // VCVTUQQ2PDZrm + 0U, // VCVTUQQ2PDZrmb + 3356U, // VCVTUQQ2PDZrmbk + 4444U, // VCVTUQQ2PDZrmbkz + 405U, // VCVTUQQ2PDZrmk + 461U, // VCVTUQQ2PDZrmkz + 0U, // VCVTUQQ2PDZrr + 0U, // VCVTUQQ2PDZrrb + 405U, // VCVTUQQ2PDZrrbk + 461U, // VCVTUQQ2PDZrrbkz + 405U, // VCVTUQQ2PDZrrk + 461U, // VCVTUQQ2PDZrrkz + 0U, // VCVTUQQ2PSZ128rm + 0U, // VCVTUQQ2PSZ128rmb + 3356U, // VCVTUQQ2PSZ128rmbk + 4444U, // VCVTUQQ2PSZ128rmbkz + 405U, // VCVTUQQ2PSZ128rmk + 461U, // VCVTUQQ2PSZ128rmkz + 0U, // VCVTUQQ2PSZ128rr + 405U, // VCVTUQQ2PSZ128rrk + 461U, // VCVTUQQ2PSZ128rrkz + 0U, // VCVTUQQ2PSZ256rm + 0U, // VCVTUQQ2PSZ256rmb + 3356U, // VCVTUQQ2PSZ256rmbk + 4444U, // VCVTUQQ2PSZ256rmbkz + 405U, // VCVTUQQ2PSZ256rmk + 461U, // VCVTUQQ2PSZ256rmkz + 0U, // VCVTUQQ2PSZ256rr + 405U, // VCVTUQQ2PSZ256rrk + 461U, // VCVTUQQ2PSZ256rrkz + 0U, // VCVTUQQ2PSZrm + 0U, // VCVTUQQ2PSZrmb + 3356U, // VCVTUQQ2PSZrmbk + 4444U, // VCVTUQQ2PSZrmbkz + 405U, // VCVTUQQ2PSZrmk + 461U, // VCVTUQQ2PSZrmkz + 0U, // VCVTUQQ2PSZrr + 0U, // VCVTUQQ2PSZrrb + 405U, // VCVTUQQ2PSZrrbk + 461U, // VCVTUQQ2PSZrrbkz + 405U, // VCVTUQQ2PSZrrk + 461U, // VCVTUQQ2PSZrrkz + 72U, // VCVTUSI2SDZrm + 72U, // VCVTUSI2SDZrm_Int + 4U, // VCVTUSI2SDZrr + 4U, // VCVTUSI2SDZrr_Int + 72U, // VCVTUSI2SSZrm + 72U, // VCVTUSI2SSZrm_Int + 4U, // VCVTUSI2SSZrr + 4U, // VCVTUSI2SSZrr_Int + 0U, // VCVTUSI2SSZrrb_Int + 72U, // VCVTUSI642SDZrm + 72U, // VCVTUSI642SDZrm_Int + 4U, // VCVTUSI642SDZrr + 4U, // VCVTUSI642SDZrr_Int + 0U, // VCVTUSI642SDZrrb_Int + 72U, // VCVTUSI642SSZrm + 72U, // VCVTUSI642SSZrm_Int + 4U, // VCVTUSI642SSZrr + 4U, // VCVTUSI642SSZrr_Int + 0U, // VCVTUSI642SSZrrb_Int + 72U, // VDBPSADBWZ128rmi + 1U, // VDBPSADBWZ128rmik + 9348U, // VDBPSADBWZ128rmikz + 18636U, // VDBPSADBWZ128rri + 25U, // VDBPSADBWZ128rrik + 26837U, // VDBPSADBWZ128rrikz + 72U, // VDBPSADBWZ256rmi + 1U, // VDBPSADBWZ256rmik + 9348U, // VDBPSADBWZ256rmikz + 18636U, // VDBPSADBWZ256rri + 25U, // VDBPSADBWZ256rrik + 26837U, // VDBPSADBWZ256rrikz + 72U, // VDBPSADBWZrmi + 1U, // VDBPSADBWZrmik + 9348U, // VDBPSADBWZrmikz + 18636U, // VDBPSADBWZrri + 25U, // VDBPSADBWZrrik + 26837U, // VDBPSADBWZrrikz + 4U, // VDIVPDYrm + 4U, // VDIVPDYrr + 4U, // VDIVPDZ128rm + 72U, // VDIVPDZ128rmb + 133U, // VDIVPDZ128rmbk + 9348U, // VDIVPDZ128rmbkz + 0U, // VDIVPDZ128rmk + 9348U, // VDIVPDZ128rmkz + 4U, // VDIVPDZ128rr + 0U, // VDIVPDZ128rrk + 9348U, // VDIVPDZ128rrkz + 4U, // VDIVPDZ256rm + 72U, // VDIVPDZ256rmb + 133U, // VDIVPDZ256rmbk + 9348U, // VDIVPDZ256rmbkz + 0U, // VDIVPDZ256rmk + 9348U, // VDIVPDZ256rmkz + 4U, // VDIVPDZ256rr + 0U, // VDIVPDZ256rrk + 9348U, // VDIVPDZ256rrkz + 4U, // VDIVPDZrm + 72U, // VDIVPDZrmb + 133U, // VDIVPDZrmbk + 9348U, // VDIVPDZrmbkz + 0U, // VDIVPDZrmk + 9348U, // VDIVPDZrmkz + 4U, // VDIVPDZrr + 4U, // VDIVPDZrrb + 0U, // VDIVPDZrrbk + 9348U, // VDIVPDZrrbkz + 0U, // VDIVPDZrrk + 9348U, // VDIVPDZrrkz + 4U, // VDIVPDrm + 4U, // VDIVPDrr + 4U, // VDIVPSYrm + 4U, // VDIVPSYrr + 4U, // VDIVPSZ128rm + 72U, // VDIVPSZ128rmb + 133U, // VDIVPSZ128rmbk + 9348U, // VDIVPSZ128rmbkz + 0U, // VDIVPSZ128rmk + 9348U, // VDIVPSZ128rmkz + 4U, // VDIVPSZ128rr + 0U, // VDIVPSZ128rrk + 9348U, // VDIVPSZ128rrkz + 4U, // VDIVPSZ256rm + 72U, // VDIVPSZ256rmb + 133U, // VDIVPSZ256rmbk + 9348U, // VDIVPSZ256rmbkz + 0U, // VDIVPSZ256rmk + 9348U, // VDIVPSZ256rmkz + 4U, // VDIVPSZ256rr + 0U, // VDIVPSZ256rrk + 9348U, // VDIVPSZ256rrkz + 4U, // VDIVPSZrm + 72U, // VDIVPSZrmb + 133U, // VDIVPSZrmbk + 9348U, // VDIVPSZrmbkz + 0U, // VDIVPSZrmk + 9348U, // VDIVPSZrmkz + 4U, // VDIVPSZrr + 4U, // VDIVPSZrrb + 0U, // VDIVPSZrrbk + 9348U, // VDIVPSZrrbkz + 0U, // VDIVPSZrrk + 9348U, // VDIVPSZrrkz + 4U, // VDIVPSrm + 4U, // VDIVPSrr + 72U, // VDIVSDZrm + 72U, // VDIVSDZrm_Int + 133U, // VDIVSDZrm_Intk + 9348U, // VDIVSDZrm_Intkz + 4U, // VDIVSDZrr + 4U, // VDIVSDZrr_Int + 0U, // VDIVSDZrr_Intk + 9348U, // VDIVSDZrr_Intkz + 4U, // VDIVSDZrrb_Int + 0U, // VDIVSDZrrb_Intk + 9348U, // VDIVSDZrrb_Intkz + 72U, // VDIVSDrm + 72U, // VDIVSDrm_Int + 4U, // VDIVSDrr + 4U, // VDIVSDrr_Int + 72U, // VDIVSSZrm + 72U, // VDIVSSZrm_Int + 133U, // VDIVSSZrm_Intk + 9348U, // VDIVSSZrm_Intkz + 4U, // VDIVSSZrr + 4U, // VDIVSSZrr_Int + 0U, // VDIVSSZrr_Intk + 9348U, // VDIVSSZrr_Intkz + 4U, // VDIVSSZrrb_Int + 0U, // VDIVSSZrrb_Intk + 9348U, // VDIVSSZrrb_Intkz + 72U, // VDIVSSrm + 72U, // VDIVSSrm_Int + 4U, // VDIVSSrr + 4U, // VDIVSSrr_Int + 72U, // VDPPDrmi + 18636U, // VDPPDrri + 72U, // VDPPSYrmi + 18636U, // VDPPSYrri + 72U, // VDPPSrmi + 18636U, // VDPPSrri + 0U, // VERRm + 0U, // VERRr + 0U, // VERWm + 0U, // VERWr + 0U, // VEXP2PDZm + 0U, // VEXP2PDZmb + 3356U, // VEXP2PDZmbk + 4444U, // VEXP2PDZmbkz + 405U, // VEXP2PDZmk + 461U, // VEXP2PDZmkz + 0U, // VEXP2PDZr + 0U, // VEXP2PDZrb + 405U, // VEXP2PDZrbk + 461U, // VEXP2PDZrbkz + 405U, // VEXP2PDZrk + 461U, // VEXP2PDZrkz + 0U, // VEXP2PSZm + 0U, // VEXP2PSZmb + 3356U, // VEXP2PSZmbk + 4444U, // VEXP2PSZmbkz + 405U, // VEXP2PSZmk + 461U, // VEXP2PSZmkz + 0U, // VEXP2PSZr + 0U, // VEXP2PSZrb + 405U, // VEXP2PSZrbk + 461U, // VEXP2PSZrbkz + 405U, // VEXP2PSZrk + 461U, // VEXP2PSZrkz + 0U, // VEXPANDPDZ128rm + 405U, // VEXPANDPDZ128rmk + 461U, // VEXPANDPDZ128rmkz + 0U, // VEXPANDPDZ128rr + 405U, // VEXPANDPDZ128rrk + 461U, // VEXPANDPDZ128rrkz + 0U, // VEXPANDPDZ256rm + 405U, // VEXPANDPDZ256rmk + 461U, // VEXPANDPDZ256rmkz + 0U, // VEXPANDPDZ256rr + 405U, // VEXPANDPDZ256rrk + 461U, // VEXPANDPDZ256rrkz + 0U, // VEXPANDPDZrm + 405U, // VEXPANDPDZrmk + 461U, // VEXPANDPDZrmkz + 0U, // VEXPANDPDZrr + 405U, // VEXPANDPDZrrk + 461U, // VEXPANDPDZrrkz + 0U, // VEXPANDPSZ128rm + 405U, // VEXPANDPSZ128rmk + 461U, // VEXPANDPSZ128rmkz + 0U, // VEXPANDPSZ128rr + 405U, // VEXPANDPSZ128rrk + 461U, // VEXPANDPSZ128rrkz + 0U, // VEXPANDPSZ256rm + 405U, // VEXPANDPSZ256rmk + 461U, // VEXPANDPSZ256rmkz + 0U, // VEXPANDPSZ256rr + 405U, // VEXPANDPSZ256rrk + 461U, // VEXPANDPSZ256rrkz + 0U, // VEXPANDPSZrm + 405U, // VEXPANDPSZrmk + 461U, // VEXPANDPSZrmkz + 0U, // VEXPANDPSZrr + 405U, // VEXPANDPSZrrk + 461U, // VEXPANDPSZrrkz + 2U, // VEXTRACTF128mr + 72U, // VEXTRACTF128rr + 2U, // VEXTRACTF32x4Z256mr + 542U, // VEXTRACTF32x4Z256mrk + 72U, // VEXTRACTF32x4Z256rr + 133U, // VEXTRACTF32x4Z256rrk + 9348U, // VEXTRACTF32x4Z256rrkz + 2U, // VEXTRACTF32x4Zmr + 542U, // VEXTRACTF32x4Zmrk + 72U, // VEXTRACTF32x4Zrr + 133U, // VEXTRACTF32x4Zrrk + 9348U, // VEXTRACTF32x4Zrrkz + 2U, // VEXTRACTF32x8Zmr + 542U, // VEXTRACTF32x8Zmrk + 72U, // VEXTRACTF32x8Zrr + 133U, // VEXTRACTF32x8Zrrk + 9348U, // VEXTRACTF32x8Zrrkz + 2U, // VEXTRACTF64x2Z256mr + 542U, // VEXTRACTF64x2Z256mrk + 72U, // VEXTRACTF64x2Z256rr + 133U, // VEXTRACTF64x2Z256rrk + 9348U, // VEXTRACTF64x2Z256rrkz + 2U, // VEXTRACTF64x2Zmr + 542U, // VEXTRACTF64x2Zmrk + 72U, // VEXTRACTF64x2Zrr + 133U, // VEXTRACTF64x2Zrrk + 9348U, // VEXTRACTF64x2Zrrkz + 2U, // VEXTRACTF64x4Zmr + 542U, // VEXTRACTF64x4Zmrk + 72U, // VEXTRACTF64x4Zrr + 133U, // VEXTRACTF64x4Zrrk + 9348U, // VEXTRACTF64x4Zrrkz + 2U, // VEXTRACTI128mr + 72U, // VEXTRACTI128rr + 2U, // VEXTRACTI32x4Z256mr + 542U, // VEXTRACTI32x4Z256mrk + 72U, // VEXTRACTI32x4Z256rr + 133U, // VEXTRACTI32x4Z256rrk + 9348U, // VEXTRACTI32x4Z256rrkz + 2U, // VEXTRACTI32x4Zmr + 542U, // VEXTRACTI32x4Zmrk + 72U, // VEXTRACTI32x4Zrr + 133U, // VEXTRACTI32x4Zrrk + 9348U, // VEXTRACTI32x4Zrrkz + 2U, // VEXTRACTI32x8Zmr + 542U, // VEXTRACTI32x8Zmrk + 72U, // VEXTRACTI32x8Zrr + 133U, // VEXTRACTI32x8Zrrk + 9348U, // VEXTRACTI32x8Zrrkz + 2U, // VEXTRACTI64x2Z256mr + 542U, // VEXTRACTI64x2Z256mrk + 72U, // VEXTRACTI64x2Z256rr + 133U, // VEXTRACTI64x2Z256rrk + 9348U, // VEXTRACTI64x2Z256rrkz + 2U, // VEXTRACTI64x2Zmr + 542U, // VEXTRACTI64x2Zmrk + 72U, // VEXTRACTI64x2Zrr + 133U, // VEXTRACTI64x2Zrrk + 9348U, // VEXTRACTI64x2Zrrkz + 2U, // VEXTRACTI64x4Zmr + 542U, // VEXTRACTI64x4Zmrk + 72U, // VEXTRACTI64x4Zrr + 133U, // VEXTRACTI64x4Zrrk + 9348U, // VEXTRACTI64x4Zrrkz + 0U, // VEXTRACTPSZmr + 72U, // VEXTRACTPSZrr + 0U, // VEXTRACTPSmr + 72U, // VEXTRACTPSrr + 18645U, // VFIXUPIMMPDZ128rmbi + 26833U, // VFIXUPIMMPDZ128rmbik + 26833U, // VFIXUPIMMPDZ128rmbikz + 4U, // VFIXUPIMMPDZ128rmi + 1U, // VFIXUPIMMPDZ128rmik + 2U, // VFIXUPIMMPDZ128rmikz + 18645U, // VFIXUPIMMPDZ128rri + 25U, // VFIXUPIMMPDZ128rrik + 53U, // VFIXUPIMMPDZ128rrikz + 18645U, // VFIXUPIMMPDZ256rmbi + 26833U, // VFIXUPIMMPDZ256rmbik + 26833U, // VFIXUPIMMPDZ256rmbikz + 4U, // VFIXUPIMMPDZ256rmi + 1U, // VFIXUPIMMPDZ256rmik + 2U, // VFIXUPIMMPDZ256rmikz + 18645U, // VFIXUPIMMPDZ256rri + 25U, // VFIXUPIMMPDZ256rrik + 53U, // VFIXUPIMMPDZ256rrikz + 18645U, // VFIXUPIMMPDZrmbi + 26833U, // VFIXUPIMMPDZrmbik + 26833U, // VFIXUPIMMPDZrmbikz + 4U, // VFIXUPIMMPDZrmi + 1U, // VFIXUPIMMPDZrmik + 2U, // VFIXUPIMMPDZrmikz + 18645U, // VFIXUPIMMPDZrri + 18645U, // VFIXUPIMMPDZrrib + 25U, // VFIXUPIMMPDZrribk + 53U, // VFIXUPIMMPDZrribkz + 25U, // VFIXUPIMMPDZrrik + 53U, // VFIXUPIMMPDZrrikz + 18645U, // VFIXUPIMMPSZ128rmbi + 26833U, // VFIXUPIMMPSZ128rmbik + 26833U, // VFIXUPIMMPSZ128rmbikz + 4U, // VFIXUPIMMPSZ128rmi + 1U, // VFIXUPIMMPSZ128rmik + 2U, // VFIXUPIMMPSZ128rmikz + 18645U, // VFIXUPIMMPSZ128rri + 25U, // VFIXUPIMMPSZ128rrik + 53U, // VFIXUPIMMPSZ128rrikz + 18645U, // VFIXUPIMMPSZ256rmbi + 26833U, // VFIXUPIMMPSZ256rmbik + 26833U, // VFIXUPIMMPSZ256rmbikz + 4U, // VFIXUPIMMPSZ256rmi + 1U, // VFIXUPIMMPSZ256rmik + 2U, // VFIXUPIMMPSZ256rmikz + 18645U, // VFIXUPIMMPSZ256rri + 25U, // VFIXUPIMMPSZ256rrik + 53U, // VFIXUPIMMPSZ256rrikz + 18645U, // VFIXUPIMMPSZrmbi + 26833U, // VFIXUPIMMPSZrmbik + 26833U, // VFIXUPIMMPSZrmbikz + 4U, // VFIXUPIMMPSZrmi + 1U, // VFIXUPIMMPSZrmik + 2U, // VFIXUPIMMPSZrmikz + 18645U, // VFIXUPIMMPSZrri + 18645U, // VFIXUPIMMPSZrrib + 25U, // VFIXUPIMMPSZrribk + 53U, // VFIXUPIMMPSZrribkz + 25U, // VFIXUPIMMPSZrrik + 53U, // VFIXUPIMMPSZrrikz + 18644U, // VFIXUPIMMSDZrmi + 26832U, // VFIXUPIMMSDZrmik + 26832U, // VFIXUPIMMSDZrmikz + 18645U, // VFIXUPIMMSDZrri + 18645U, // VFIXUPIMMSDZrrib + 25U, // VFIXUPIMMSDZrribk + 53U, // VFIXUPIMMSDZrribkz + 25U, // VFIXUPIMMSDZrrik + 53U, // VFIXUPIMMSDZrrikz + 18644U, // VFIXUPIMMSSZrmi + 26832U, // VFIXUPIMMSSZrmik + 26832U, // VFIXUPIMMSSZrmikz + 18645U, // VFIXUPIMMSSZrri + 18645U, // VFIXUPIMMSSZrrib + 25U, // VFIXUPIMMSSZrribk + 53U, // VFIXUPIMMSSZrribkz + 25U, // VFIXUPIMMSSZrrik + 53U, // VFIXUPIMMSSZrrikz + 4U, // VFMADD132PDYm + 4U, // VFMADD132PDYr + 4U, // VFMADD132PDZ128m + 4U, // VFMADD132PDZ128mb + 133U, // VFMADD132PDZ128mbk + 8325U, // VFMADD132PDZ128mbkz + 0U, // VFMADD132PDZ128mk + 0U, // VFMADD132PDZ128mkz + 4U, // VFMADD132PDZ128r + 0U, // VFMADD132PDZ128rk + 0U, // VFMADD132PDZ128rkz + 4U, // VFMADD132PDZ256m + 4U, // VFMADD132PDZ256mb + 133U, // VFMADD132PDZ256mbk + 8325U, // VFMADD132PDZ256mbkz + 0U, // VFMADD132PDZ256mk + 0U, // VFMADD132PDZ256mkz + 4U, // VFMADD132PDZ256r + 0U, // VFMADD132PDZ256rk + 0U, // VFMADD132PDZ256rkz + 4U, // VFMADD132PDZm + 4U, // VFMADD132PDZmb + 133U, // VFMADD132PDZmbk + 8325U, // VFMADD132PDZmbkz + 0U, // VFMADD132PDZmk + 0U, // VFMADD132PDZmkz + 4U, // VFMADD132PDZr + 4U, // VFMADD132PDZrb + 0U, // VFMADD132PDZrbk + 0U, // VFMADD132PDZrbkz + 0U, // VFMADD132PDZrk + 0U, // VFMADD132PDZrkz + 4U, // VFMADD132PDm + 4U, // VFMADD132PDr + 4U, // VFMADD132PSYm + 4U, // VFMADD132PSYr + 4U, // VFMADD132PSZ128m + 4U, // VFMADD132PSZ128mb + 133U, // VFMADD132PSZ128mbk + 8325U, // VFMADD132PSZ128mbkz + 0U, // VFMADD132PSZ128mk + 0U, // VFMADD132PSZ128mkz + 4U, // VFMADD132PSZ128r + 0U, // VFMADD132PSZ128rk + 0U, // VFMADD132PSZ128rkz + 4U, // VFMADD132PSZ256m + 4U, // VFMADD132PSZ256mb + 133U, // VFMADD132PSZ256mbk + 8325U, // VFMADD132PSZ256mbkz + 0U, // VFMADD132PSZ256mk + 0U, // VFMADD132PSZ256mkz + 4U, // VFMADD132PSZ256r + 0U, // VFMADD132PSZ256rk + 0U, // VFMADD132PSZ256rkz + 4U, // VFMADD132PSZm + 4U, // VFMADD132PSZmb + 133U, // VFMADD132PSZmbk + 8325U, // VFMADD132PSZmbkz + 0U, // VFMADD132PSZmk + 0U, // VFMADD132PSZmkz + 4U, // VFMADD132PSZr + 4U, // VFMADD132PSZrb + 0U, // VFMADD132PSZrbk + 0U, // VFMADD132PSZrbkz + 0U, // VFMADD132PSZrk + 0U, // VFMADD132PSZrkz + 4U, // VFMADD132PSm + 4U, // VFMADD132PSr + 4U, // VFMADD132SDZm + 4U, // VFMADD132SDZm_Int + 133U, // VFMADD132SDZm_Intk + 8325U, // VFMADD132SDZm_Intkz + 4U, // VFMADD132SDZr + 4U, // VFMADD132SDZr_Int + 0U, // VFMADD132SDZr_Intk + 0U, // VFMADD132SDZr_Intkz + 4U, // VFMADD132SDZrb + 4U, // VFMADD132SDZrb_Int + 0U, // VFMADD132SDZrb_Intk + 0U, // VFMADD132SDZrb_Intkz + 4U, // VFMADD132SDm + 4U, // VFMADD132SDm_Int + 4U, // VFMADD132SDr + 4U, // VFMADD132SDr_Int + 4U, // VFMADD132SSZm + 4U, // VFMADD132SSZm_Int + 133U, // VFMADD132SSZm_Intk + 8325U, // VFMADD132SSZm_Intkz + 4U, // VFMADD132SSZr + 4U, // VFMADD132SSZr_Int + 0U, // VFMADD132SSZr_Intk + 0U, // VFMADD132SSZr_Intkz + 4U, // VFMADD132SSZrb + 4U, // VFMADD132SSZrb_Int + 0U, // VFMADD132SSZrb_Intk + 0U, // VFMADD132SSZrb_Intkz + 4U, // VFMADD132SSm + 4U, // VFMADD132SSm_Int + 4U, // VFMADD132SSr + 4U, // VFMADD132SSr_Int + 4U, // VFMADD213PDYm + 4U, // VFMADD213PDYr + 4U, // VFMADD213PDZ128m + 4U, // VFMADD213PDZ128mb + 133U, // VFMADD213PDZ128mbk + 8325U, // VFMADD213PDZ128mbkz + 0U, // VFMADD213PDZ128mk + 0U, // VFMADD213PDZ128mkz + 4U, // VFMADD213PDZ128r + 0U, // VFMADD213PDZ128rk + 0U, // VFMADD213PDZ128rkz + 4U, // VFMADD213PDZ256m + 4U, // VFMADD213PDZ256mb + 133U, // VFMADD213PDZ256mbk + 8325U, // VFMADD213PDZ256mbkz + 0U, // VFMADD213PDZ256mk + 0U, // VFMADD213PDZ256mkz + 4U, // VFMADD213PDZ256r + 0U, // VFMADD213PDZ256rk + 0U, // VFMADD213PDZ256rkz + 4U, // VFMADD213PDZm + 4U, // VFMADD213PDZmb + 133U, // VFMADD213PDZmbk + 8325U, // VFMADD213PDZmbkz + 0U, // VFMADD213PDZmk + 0U, // VFMADD213PDZmkz + 4U, // VFMADD213PDZr + 4U, // VFMADD213PDZrb + 0U, // VFMADD213PDZrbk + 0U, // VFMADD213PDZrbkz + 0U, // VFMADD213PDZrk + 0U, // VFMADD213PDZrkz + 4U, // VFMADD213PDm + 4U, // VFMADD213PDr + 4U, // VFMADD213PSYm + 4U, // VFMADD213PSYr + 4U, // VFMADD213PSZ128m + 4U, // VFMADD213PSZ128mb + 133U, // VFMADD213PSZ128mbk + 8325U, // VFMADD213PSZ128mbkz + 0U, // VFMADD213PSZ128mk + 0U, // VFMADD213PSZ128mkz + 4U, // VFMADD213PSZ128r + 0U, // VFMADD213PSZ128rk + 0U, // VFMADD213PSZ128rkz + 4U, // VFMADD213PSZ256m + 4U, // VFMADD213PSZ256mb + 133U, // VFMADD213PSZ256mbk + 8325U, // VFMADD213PSZ256mbkz + 0U, // VFMADD213PSZ256mk + 0U, // VFMADD213PSZ256mkz + 4U, // VFMADD213PSZ256r + 0U, // VFMADD213PSZ256rk + 0U, // VFMADD213PSZ256rkz + 4U, // VFMADD213PSZm + 4U, // VFMADD213PSZmb + 133U, // VFMADD213PSZmbk + 8325U, // VFMADD213PSZmbkz + 0U, // VFMADD213PSZmk + 0U, // VFMADD213PSZmkz + 4U, // VFMADD213PSZr + 4U, // VFMADD213PSZrb + 0U, // VFMADD213PSZrbk + 0U, // VFMADD213PSZrbkz + 0U, // VFMADD213PSZrk + 0U, // VFMADD213PSZrkz + 4U, // VFMADD213PSm + 4U, // VFMADD213PSr + 4U, // VFMADD213SDZm + 4U, // VFMADD213SDZm_Int + 133U, // VFMADD213SDZm_Intk + 8325U, // VFMADD213SDZm_Intkz + 4U, // VFMADD213SDZr + 4U, // VFMADD213SDZr_Int + 0U, // VFMADD213SDZr_Intk + 0U, // VFMADD213SDZr_Intkz + 4U, // VFMADD213SDZrb + 4U, // VFMADD213SDZrb_Int + 0U, // VFMADD213SDZrb_Intk + 0U, // VFMADD213SDZrb_Intkz + 4U, // VFMADD213SDm + 4U, // VFMADD213SDm_Int + 4U, // VFMADD213SDr + 4U, // VFMADD213SDr_Int + 4U, // VFMADD213SSZm + 4U, // VFMADD213SSZm_Int + 133U, // VFMADD213SSZm_Intk + 8325U, // VFMADD213SSZm_Intkz + 4U, // VFMADD213SSZr + 4U, // VFMADD213SSZr_Int + 0U, // VFMADD213SSZr_Intk + 0U, // VFMADD213SSZr_Intkz + 4U, // VFMADD213SSZrb + 4U, // VFMADD213SSZrb_Int + 0U, // VFMADD213SSZrb_Intk + 0U, // VFMADD213SSZrb_Intkz + 4U, // VFMADD213SSm + 4U, // VFMADD213SSm_Int + 4U, // VFMADD213SSr + 4U, // VFMADD213SSr_Int + 4U, // VFMADD231PDYm + 4U, // VFMADD231PDYr + 4U, // VFMADD231PDZ128m + 4U, // VFMADD231PDZ128mb + 133U, // VFMADD231PDZ128mbk + 8325U, // VFMADD231PDZ128mbkz + 0U, // VFMADD231PDZ128mk + 0U, // VFMADD231PDZ128mkz + 4U, // VFMADD231PDZ128r + 0U, // VFMADD231PDZ128rk + 0U, // VFMADD231PDZ128rkz + 4U, // VFMADD231PDZ256m + 4U, // VFMADD231PDZ256mb + 133U, // VFMADD231PDZ256mbk + 8325U, // VFMADD231PDZ256mbkz + 0U, // VFMADD231PDZ256mk + 0U, // VFMADD231PDZ256mkz + 4U, // VFMADD231PDZ256r + 0U, // VFMADD231PDZ256rk + 0U, // VFMADD231PDZ256rkz + 4U, // VFMADD231PDZm + 4U, // VFMADD231PDZmb + 133U, // VFMADD231PDZmbk + 8325U, // VFMADD231PDZmbkz + 0U, // VFMADD231PDZmk + 0U, // VFMADD231PDZmkz + 4U, // VFMADD231PDZr + 4U, // VFMADD231PDZrb + 0U, // VFMADD231PDZrbk + 0U, // VFMADD231PDZrbkz + 0U, // VFMADD231PDZrk + 0U, // VFMADD231PDZrkz + 4U, // VFMADD231PDm + 4U, // VFMADD231PDr + 4U, // VFMADD231PSYm + 4U, // VFMADD231PSYr + 4U, // VFMADD231PSZ128m + 4U, // VFMADD231PSZ128mb + 133U, // VFMADD231PSZ128mbk + 8325U, // VFMADD231PSZ128mbkz + 0U, // VFMADD231PSZ128mk + 0U, // VFMADD231PSZ128mkz + 4U, // VFMADD231PSZ128r + 0U, // VFMADD231PSZ128rk + 0U, // VFMADD231PSZ128rkz + 4U, // VFMADD231PSZ256m + 4U, // VFMADD231PSZ256mb + 133U, // VFMADD231PSZ256mbk + 8325U, // VFMADD231PSZ256mbkz + 0U, // VFMADD231PSZ256mk + 0U, // VFMADD231PSZ256mkz + 4U, // VFMADD231PSZ256r + 0U, // VFMADD231PSZ256rk + 0U, // VFMADD231PSZ256rkz + 4U, // VFMADD231PSZm + 4U, // VFMADD231PSZmb + 133U, // VFMADD231PSZmbk + 8325U, // VFMADD231PSZmbkz + 0U, // VFMADD231PSZmk + 0U, // VFMADD231PSZmkz + 4U, // VFMADD231PSZr + 4U, // VFMADD231PSZrb + 0U, // VFMADD231PSZrbk + 0U, // VFMADD231PSZrbkz + 0U, // VFMADD231PSZrk + 0U, // VFMADD231PSZrkz + 4U, // VFMADD231PSm + 4U, // VFMADD231PSr + 4U, // VFMADD231SDZm + 4U, // VFMADD231SDZm_Int + 133U, // VFMADD231SDZm_Intk + 8325U, // VFMADD231SDZm_Intkz + 4U, // VFMADD231SDZr + 4U, // VFMADD231SDZr_Int + 0U, // VFMADD231SDZr_Intk + 0U, // VFMADD231SDZr_Intkz + 4U, // VFMADD231SDZrb + 4U, // VFMADD231SDZrb_Int + 0U, // VFMADD231SDZrb_Intk + 0U, // VFMADD231SDZrb_Intkz + 4U, // VFMADD231SDm + 4U, // VFMADD231SDm_Int + 4U, // VFMADD231SDr + 4U, // VFMADD231SDr_Int + 4U, // VFMADD231SSZm + 4U, // VFMADD231SSZm_Int + 133U, // VFMADD231SSZm_Intk + 8325U, // VFMADD231SSZm_Intkz + 4U, // VFMADD231SSZr + 4U, // VFMADD231SSZr_Int + 0U, // VFMADD231SSZr_Intk + 0U, // VFMADD231SSZr_Intkz + 4U, // VFMADD231SSZrb + 4U, // VFMADD231SSZrb_Int + 0U, // VFMADD231SSZrb_Intk + 0U, // VFMADD231SSZrb_Intkz + 4U, // VFMADD231SSm + 4U, // VFMADD231SSm_Int + 4U, // VFMADD231SSr + 4U, // VFMADD231SSr_Int + 72U, // VFMADDPD4Ymr + 18636U, // VFMADDPD4Yrm + 18636U, // VFMADDPD4Yrr + 18636U, // VFMADDPD4Yrr_REV + 72U, // VFMADDPD4mr + 18636U, // VFMADDPD4rm + 18636U, // VFMADDPD4rr + 18636U, // VFMADDPD4rr_REV + 72U, // VFMADDPS4Ymr + 18636U, // VFMADDPS4Yrm + 18636U, // VFMADDPS4Yrr + 18636U, // VFMADDPS4Yrr_REV + 72U, // VFMADDPS4mr + 18636U, // VFMADDPS4rm + 18636U, // VFMADDPS4rr + 18636U, // VFMADDPS4rr_REV + 18636U, // VFMADDSD4mr + 18636U, // VFMADDSD4mr_Int + 18636U, // VFMADDSD4rm + 18636U, // VFMADDSD4rm_Int + 18636U, // VFMADDSD4rr + 18636U, // VFMADDSD4rr_Int + 18636U, // VFMADDSD4rr_Int_REV + 18636U, // VFMADDSD4rr_REV + 18636U, // VFMADDSS4mr + 18636U, // VFMADDSS4mr_Int + 18636U, // VFMADDSS4rm + 18636U, // VFMADDSS4rm_Int + 18636U, // VFMADDSS4rr + 18636U, // VFMADDSS4rr_Int + 18636U, // VFMADDSS4rr_Int_REV + 18636U, // VFMADDSS4rr_REV + 4U, // VFMADDSUB132PDYm + 4U, // VFMADDSUB132PDYr + 4U, // VFMADDSUB132PDZ128m + 4U, // VFMADDSUB132PDZ128mb + 133U, // VFMADDSUB132PDZ128mbk + 8325U, // VFMADDSUB132PDZ128mbkz + 0U, // VFMADDSUB132PDZ128mk + 0U, // VFMADDSUB132PDZ128mkz + 4U, // VFMADDSUB132PDZ128r + 0U, // VFMADDSUB132PDZ128rk + 0U, // VFMADDSUB132PDZ128rkz + 4U, // VFMADDSUB132PDZ256m + 4U, // VFMADDSUB132PDZ256mb + 133U, // VFMADDSUB132PDZ256mbk + 8325U, // VFMADDSUB132PDZ256mbkz + 0U, // VFMADDSUB132PDZ256mk + 0U, // VFMADDSUB132PDZ256mkz + 4U, // VFMADDSUB132PDZ256r + 0U, // VFMADDSUB132PDZ256rk + 0U, // VFMADDSUB132PDZ256rkz + 4U, // VFMADDSUB132PDZm + 4U, // VFMADDSUB132PDZmb + 133U, // VFMADDSUB132PDZmbk + 8325U, // VFMADDSUB132PDZmbkz + 0U, // VFMADDSUB132PDZmk + 0U, // VFMADDSUB132PDZmkz + 4U, // VFMADDSUB132PDZr + 4U, // VFMADDSUB132PDZrb + 0U, // VFMADDSUB132PDZrbk + 0U, // VFMADDSUB132PDZrbkz + 0U, // VFMADDSUB132PDZrk + 0U, // VFMADDSUB132PDZrkz + 4U, // VFMADDSUB132PDm + 4U, // VFMADDSUB132PDr + 4U, // VFMADDSUB132PSYm + 4U, // VFMADDSUB132PSYr + 4U, // VFMADDSUB132PSZ128m + 4U, // VFMADDSUB132PSZ128mb + 133U, // VFMADDSUB132PSZ128mbk + 8325U, // VFMADDSUB132PSZ128mbkz + 0U, // VFMADDSUB132PSZ128mk + 0U, // VFMADDSUB132PSZ128mkz + 4U, // VFMADDSUB132PSZ128r + 0U, // VFMADDSUB132PSZ128rk + 0U, // VFMADDSUB132PSZ128rkz + 4U, // VFMADDSUB132PSZ256m + 4U, // VFMADDSUB132PSZ256mb + 133U, // VFMADDSUB132PSZ256mbk + 8325U, // VFMADDSUB132PSZ256mbkz + 0U, // VFMADDSUB132PSZ256mk + 0U, // VFMADDSUB132PSZ256mkz + 4U, // VFMADDSUB132PSZ256r + 0U, // VFMADDSUB132PSZ256rk + 0U, // VFMADDSUB132PSZ256rkz + 4U, // VFMADDSUB132PSZm + 4U, // VFMADDSUB132PSZmb + 133U, // VFMADDSUB132PSZmbk + 8325U, // VFMADDSUB132PSZmbkz + 0U, // VFMADDSUB132PSZmk + 0U, // VFMADDSUB132PSZmkz + 4U, // VFMADDSUB132PSZr + 4U, // VFMADDSUB132PSZrb + 0U, // VFMADDSUB132PSZrbk + 0U, // VFMADDSUB132PSZrbkz + 0U, // VFMADDSUB132PSZrk + 0U, // VFMADDSUB132PSZrkz + 4U, // VFMADDSUB132PSm + 4U, // VFMADDSUB132PSr + 4U, // VFMADDSUB213PDYm + 4U, // VFMADDSUB213PDYr + 4U, // VFMADDSUB213PDZ128m + 4U, // VFMADDSUB213PDZ128mb + 133U, // VFMADDSUB213PDZ128mbk + 8325U, // VFMADDSUB213PDZ128mbkz + 0U, // VFMADDSUB213PDZ128mk + 0U, // VFMADDSUB213PDZ128mkz + 4U, // VFMADDSUB213PDZ128r + 0U, // VFMADDSUB213PDZ128rk + 0U, // VFMADDSUB213PDZ128rkz + 4U, // VFMADDSUB213PDZ256m + 4U, // VFMADDSUB213PDZ256mb + 133U, // VFMADDSUB213PDZ256mbk + 8325U, // VFMADDSUB213PDZ256mbkz + 0U, // VFMADDSUB213PDZ256mk + 0U, // VFMADDSUB213PDZ256mkz + 4U, // VFMADDSUB213PDZ256r + 0U, // VFMADDSUB213PDZ256rk + 0U, // VFMADDSUB213PDZ256rkz + 4U, // VFMADDSUB213PDZm + 4U, // VFMADDSUB213PDZmb + 133U, // VFMADDSUB213PDZmbk + 8325U, // VFMADDSUB213PDZmbkz + 0U, // VFMADDSUB213PDZmk + 0U, // VFMADDSUB213PDZmkz + 4U, // VFMADDSUB213PDZr + 4U, // VFMADDSUB213PDZrb + 0U, // VFMADDSUB213PDZrbk + 0U, // VFMADDSUB213PDZrbkz + 0U, // VFMADDSUB213PDZrk + 0U, // VFMADDSUB213PDZrkz + 4U, // VFMADDSUB213PDm + 4U, // VFMADDSUB213PDr + 4U, // VFMADDSUB213PSYm + 4U, // VFMADDSUB213PSYr + 4U, // VFMADDSUB213PSZ128m + 4U, // VFMADDSUB213PSZ128mb + 133U, // VFMADDSUB213PSZ128mbk + 8325U, // VFMADDSUB213PSZ128mbkz + 0U, // VFMADDSUB213PSZ128mk + 0U, // VFMADDSUB213PSZ128mkz + 4U, // VFMADDSUB213PSZ128r + 0U, // VFMADDSUB213PSZ128rk + 0U, // VFMADDSUB213PSZ128rkz + 4U, // VFMADDSUB213PSZ256m + 4U, // VFMADDSUB213PSZ256mb + 133U, // VFMADDSUB213PSZ256mbk + 8325U, // VFMADDSUB213PSZ256mbkz + 0U, // VFMADDSUB213PSZ256mk + 0U, // VFMADDSUB213PSZ256mkz + 4U, // VFMADDSUB213PSZ256r + 0U, // VFMADDSUB213PSZ256rk + 0U, // VFMADDSUB213PSZ256rkz + 4U, // VFMADDSUB213PSZm + 4U, // VFMADDSUB213PSZmb + 133U, // VFMADDSUB213PSZmbk + 8325U, // VFMADDSUB213PSZmbkz + 0U, // VFMADDSUB213PSZmk + 0U, // VFMADDSUB213PSZmkz + 4U, // VFMADDSUB213PSZr + 4U, // VFMADDSUB213PSZrb + 0U, // VFMADDSUB213PSZrbk + 0U, // VFMADDSUB213PSZrbkz + 0U, // VFMADDSUB213PSZrk + 0U, // VFMADDSUB213PSZrkz + 4U, // VFMADDSUB213PSm + 4U, // VFMADDSUB213PSr + 4U, // VFMADDSUB231PDYm + 4U, // VFMADDSUB231PDYr + 4U, // VFMADDSUB231PDZ128m + 4U, // VFMADDSUB231PDZ128mb + 133U, // VFMADDSUB231PDZ128mbk + 8325U, // VFMADDSUB231PDZ128mbkz + 0U, // VFMADDSUB231PDZ128mk + 0U, // VFMADDSUB231PDZ128mkz + 4U, // VFMADDSUB231PDZ128r + 0U, // VFMADDSUB231PDZ128rk + 0U, // VFMADDSUB231PDZ128rkz + 4U, // VFMADDSUB231PDZ256m + 4U, // VFMADDSUB231PDZ256mb + 133U, // VFMADDSUB231PDZ256mbk + 8325U, // VFMADDSUB231PDZ256mbkz + 0U, // VFMADDSUB231PDZ256mk + 0U, // VFMADDSUB231PDZ256mkz + 4U, // VFMADDSUB231PDZ256r + 0U, // VFMADDSUB231PDZ256rk + 0U, // VFMADDSUB231PDZ256rkz + 4U, // VFMADDSUB231PDZm + 4U, // VFMADDSUB231PDZmb + 133U, // VFMADDSUB231PDZmbk + 8325U, // VFMADDSUB231PDZmbkz + 0U, // VFMADDSUB231PDZmk + 0U, // VFMADDSUB231PDZmkz + 4U, // VFMADDSUB231PDZr + 4U, // VFMADDSUB231PDZrb + 0U, // VFMADDSUB231PDZrbk + 0U, // VFMADDSUB231PDZrbkz + 0U, // VFMADDSUB231PDZrk + 0U, // VFMADDSUB231PDZrkz + 4U, // VFMADDSUB231PDm + 4U, // VFMADDSUB231PDr + 4U, // VFMADDSUB231PSYm + 4U, // VFMADDSUB231PSYr + 4U, // VFMADDSUB231PSZ128m + 4U, // VFMADDSUB231PSZ128mb + 133U, // VFMADDSUB231PSZ128mbk + 8325U, // VFMADDSUB231PSZ128mbkz + 0U, // VFMADDSUB231PSZ128mk + 0U, // VFMADDSUB231PSZ128mkz + 4U, // VFMADDSUB231PSZ128r + 0U, // VFMADDSUB231PSZ128rk + 0U, // VFMADDSUB231PSZ128rkz + 4U, // VFMADDSUB231PSZ256m + 4U, // VFMADDSUB231PSZ256mb + 133U, // VFMADDSUB231PSZ256mbk + 8325U, // VFMADDSUB231PSZ256mbkz + 0U, // VFMADDSUB231PSZ256mk + 0U, // VFMADDSUB231PSZ256mkz + 4U, // VFMADDSUB231PSZ256r + 0U, // VFMADDSUB231PSZ256rk + 0U, // VFMADDSUB231PSZ256rkz + 4U, // VFMADDSUB231PSZm + 4U, // VFMADDSUB231PSZmb + 133U, // VFMADDSUB231PSZmbk + 8325U, // VFMADDSUB231PSZmbkz + 0U, // VFMADDSUB231PSZmk + 0U, // VFMADDSUB231PSZmkz + 4U, // VFMADDSUB231PSZr + 4U, // VFMADDSUB231PSZrb + 0U, // VFMADDSUB231PSZrbk + 0U, // VFMADDSUB231PSZrbkz + 0U, // VFMADDSUB231PSZrk + 0U, // VFMADDSUB231PSZrkz + 4U, // VFMADDSUB231PSm + 4U, // VFMADDSUB231PSr + 72U, // VFMADDSUBPD4Ymr + 18636U, // VFMADDSUBPD4Yrm + 18636U, // VFMADDSUBPD4Yrr + 18636U, // VFMADDSUBPD4Yrr_REV + 72U, // VFMADDSUBPD4mr + 18636U, // VFMADDSUBPD4rm + 18636U, // VFMADDSUBPD4rr + 18636U, // VFMADDSUBPD4rr_REV + 72U, // VFMADDSUBPS4Ymr + 18636U, // VFMADDSUBPS4Yrm + 18636U, // VFMADDSUBPS4Yrr + 18636U, // VFMADDSUBPS4Yrr_REV + 72U, // VFMADDSUBPS4mr + 18636U, // VFMADDSUBPS4rm + 18636U, // VFMADDSUBPS4rr + 18636U, // VFMADDSUBPS4rr_REV + 4U, // VFMSUB132PDYm + 4U, // VFMSUB132PDYr + 4U, // VFMSUB132PDZ128m + 4U, // VFMSUB132PDZ128mb + 133U, // VFMSUB132PDZ128mbk + 8325U, // VFMSUB132PDZ128mbkz + 0U, // VFMSUB132PDZ128mk + 0U, // VFMSUB132PDZ128mkz + 4U, // VFMSUB132PDZ128r + 0U, // VFMSUB132PDZ128rk + 0U, // VFMSUB132PDZ128rkz + 4U, // VFMSUB132PDZ256m + 4U, // VFMSUB132PDZ256mb + 133U, // VFMSUB132PDZ256mbk + 8325U, // VFMSUB132PDZ256mbkz + 0U, // VFMSUB132PDZ256mk + 0U, // VFMSUB132PDZ256mkz + 4U, // VFMSUB132PDZ256r + 0U, // VFMSUB132PDZ256rk + 0U, // VFMSUB132PDZ256rkz + 4U, // VFMSUB132PDZm + 4U, // VFMSUB132PDZmb + 133U, // VFMSUB132PDZmbk + 8325U, // VFMSUB132PDZmbkz + 0U, // VFMSUB132PDZmk + 0U, // VFMSUB132PDZmkz + 4U, // VFMSUB132PDZr + 4U, // VFMSUB132PDZrb + 0U, // VFMSUB132PDZrbk + 0U, // VFMSUB132PDZrbkz + 0U, // VFMSUB132PDZrk + 0U, // VFMSUB132PDZrkz + 4U, // VFMSUB132PDm + 4U, // VFMSUB132PDr + 4U, // VFMSUB132PSYm + 4U, // VFMSUB132PSYr + 4U, // VFMSUB132PSZ128m + 4U, // VFMSUB132PSZ128mb + 133U, // VFMSUB132PSZ128mbk + 8325U, // VFMSUB132PSZ128mbkz + 0U, // VFMSUB132PSZ128mk + 0U, // VFMSUB132PSZ128mkz + 4U, // VFMSUB132PSZ128r + 0U, // VFMSUB132PSZ128rk + 0U, // VFMSUB132PSZ128rkz + 4U, // VFMSUB132PSZ256m + 4U, // VFMSUB132PSZ256mb + 133U, // VFMSUB132PSZ256mbk + 8325U, // VFMSUB132PSZ256mbkz + 0U, // VFMSUB132PSZ256mk + 0U, // VFMSUB132PSZ256mkz + 4U, // VFMSUB132PSZ256r + 0U, // VFMSUB132PSZ256rk + 0U, // VFMSUB132PSZ256rkz + 4U, // VFMSUB132PSZm + 4U, // VFMSUB132PSZmb + 133U, // VFMSUB132PSZmbk + 8325U, // VFMSUB132PSZmbkz + 0U, // VFMSUB132PSZmk + 0U, // VFMSUB132PSZmkz + 4U, // VFMSUB132PSZr + 4U, // VFMSUB132PSZrb + 0U, // VFMSUB132PSZrbk + 0U, // VFMSUB132PSZrbkz + 0U, // VFMSUB132PSZrk + 0U, // VFMSUB132PSZrkz + 4U, // VFMSUB132PSm + 4U, // VFMSUB132PSr + 4U, // VFMSUB132SDZm + 4U, // VFMSUB132SDZm_Int + 133U, // VFMSUB132SDZm_Intk + 8325U, // VFMSUB132SDZm_Intkz + 4U, // VFMSUB132SDZr + 4U, // VFMSUB132SDZr_Int + 0U, // VFMSUB132SDZr_Intk + 0U, // VFMSUB132SDZr_Intkz + 4U, // VFMSUB132SDZrb + 4U, // VFMSUB132SDZrb_Int + 0U, // VFMSUB132SDZrb_Intk + 0U, // VFMSUB132SDZrb_Intkz + 4U, // VFMSUB132SDm + 4U, // VFMSUB132SDm_Int + 4U, // VFMSUB132SDr + 4U, // VFMSUB132SDr_Int + 4U, // VFMSUB132SSZm + 4U, // VFMSUB132SSZm_Int + 133U, // VFMSUB132SSZm_Intk + 8325U, // VFMSUB132SSZm_Intkz + 4U, // VFMSUB132SSZr + 4U, // VFMSUB132SSZr_Int + 0U, // VFMSUB132SSZr_Intk + 0U, // VFMSUB132SSZr_Intkz + 4U, // VFMSUB132SSZrb + 4U, // VFMSUB132SSZrb_Int + 0U, // VFMSUB132SSZrb_Intk + 0U, // VFMSUB132SSZrb_Intkz + 4U, // VFMSUB132SSm + 4U, // VFMSUB132SSm_Int + 4U, // VFMSUB132SSr + 4U, // VFMSUB132SSr_Int + 4U, // VFMSUB213PDYm + 4U, // VFMSUB213PDYr + 4U, // VFMSUB213PDZ128m + 4U, // VFMSUB213PDZ128mb + 133U, // VFMSUB213PDZ128mbk + 8325U, // VFMSUB213PDZ128mbkz + 0U, // VFMSUB213PDZ128mk + 0U, // VFMSUB213PDZ128mkz + 4U, // VFMSUB213PDZ128r + 0U, // VFMSUB213PDZ128rk + 0U, // VFMSUB213PDZ128rkz + 4U, // VFMSUB213PDZ256m + 4U, // VFMSUB213PDZ256mb + 133U, // VFMSUB213PDZ256mbk + 8325U, // VFMSUB213PDZ256mbkz + 0U, // VFMSUB213PDZ256mk + 0U, // VFMSUB213PDZ256mkz + 4U, // VFMSUB213PDZ256r + 0U, // VFMSUB213PDZ256rk + 0U, // VFMSUB213PDZ256rkz + 4U, // VFMSUB213PDZm + 4U, // VFMSUB213PDZmb + 133U, // VFMSUB213PDZmbk + 8325U, // VFMSUB213PDZmbkz + 0U, // VFMSUB213PDZmk + 0U, // VFMSUB213PDZmkz + 4U, // VFMSUB213PDZr + 4U, // VFMSUB213PDZrb + 0U, // VFMSUB213PDZrbk + 0U, // VFMSUB213PDZrbkz + 0U, // VFMSUB213PDZrk + 0U, // VFMSUB213PDZrkz + 4U, // VFMSUB213PDm + 4U, // VFMSUB213PDr + 4U, // VFMSUB213PSYm + 4U, // VFMSUB213PSYr + 4U, // VFMSUB213PSZ128m + 4U, // VFMSUB213PSZ128mb + 133U, // VFMSUB213PSZ128mbk + 8325U, // VFMSUB213PSZ128mbkz + 0U, // VFMSUB213PSZ128mk + 0U, // VFMSUB213PSZ128mkz + 4U, // VFMSUB213PSZ128r + 0U, // VFMSUB213PSZ128rk + 0U, // VFMSUB213PSZ128rkz + 4U, // VFMSUB213PSZ256m + 4U, // VFMSUB213PSZ256mb + 133U, // VFMSUB213PSZ256mbk + 8325U, // VFMSUB213PSZ256mbkz + 0U, // VFMSUB213PSZ256mk + 0U, // VFMSUB213PSZ256mkz + 4U, // VFMSUB213PSZ256r + 0U, // VFMSUB213PSZ256rk + 0U, // VFMSUB213PSZ256rkz + 4U, // VFMSUB213PSZm + 4U, // VFMSUB213PSZmb + 133U, // VFMSUB213PSZmbk + 8325U, // VFMSUB213PSZmbkz + 0U, // VFMSUB213PSZmk + 0U, // VFMSUB213PSZmkz + 4U, // VFMSUB213PSZr + 4U, // VFMSUB213PSZrb + 0U, // VFMSUB213PSZrbk + 0U, // VFMSUB213PSZrbkz + 0U, // VFMSUB213PSZrk + 0U, // VFMSUB213PSZrkz + 4U, // VFMSUB213PSm + 4U, // VFMSUB213PSr + 4U, // VFMSUB213SDZm + 4U, // VFMSUB213SDZm_Int + 133U, // VFMSUB213SDZm_Intk + 8325U, // VFMSUB213SDZm_Intkz + 4U, // VFMSUB213SDZr + 4U, // VFMSUB213SDZr_Int + 0U, // VFMSUB213SDZr_Intk + 0U, // VFMSUB213SDZr_Intkz + 4U, // VFMSUB213SDZrb + 4U, // VFMSUB213SDZrb_Int + 0U, // VFMSUB213SDZrb_Intk + 0U, // VFMSUB213SDZrb_Intkz + 4U, // VFMSUB213SDm + 4U, // VFMSUB213SDm_Int + 4U, // VFMSUB213SDr + 4U, // VFMSUB213SDr_Int + 4U, // VFMSUB213SSZm + 4U, // VFMSUB213SSZm_Int + 133U, // VFMSUB213SSZm_Intk + 8325U, // VFMSUB213SSZm_Intkz + 4U, // VFMSUB213SSZr + 4U, // VFMSUB213SSZr_Int + 0U, // VFMSUB213SSZr_Intk + 0U, // VFMSUB213SSZr_Intkz + 4U, // VFMSUB213SSZrb + 4U, // VFMSUB213SSZrb_Int + 0U, // VFMSUB213SSZrb_Intk + 0U, // VFMSUB213SSZrb_Intkz + 4U, // VFMSUB213SSm + 4U, // VFMSUB213SSm_Int + 4U, // VFMSUB213SSr + 4U, // VFMSUB213SSr_Int + 4U, // VFMSUB231PDYm + 4U, // VFMSUB231PDYr + 4U, // VFMSUB231PDZ128m + 4U, // VFMSUB231PDZ128mb + 133U, // VFMSUB231PDZ128mbk + 8325U, // VFMSUB231PDZ128mbkz + 0U, // VFMSUB231PDZ128mk + 0U, // VFMSUB231PDZ128mkz + 4U, // VFMSUB231PDZ128r + 0U, // VFMSUB231PDZ128rk + 0U, // VFMSUB231PDZ128rkz + 4U, // VFMSUB231PDZ256m + 4U, // VFMSUB231PDZ256mb + 133U, // VFMSUB231PDZ256mbk + 8325U, // VFMSUB231PDZ256mbkz + 0U, // VFMSUB231PDZ256mk + 0U, // VFMSUB231PDZ256mkz + 4U, // VFMSUB231PDZ256r + 0U, // VFMSUB231PDZ256rk + 0U, // VFMSUB231PDZ256rkz + 4U, // VFMSUB231PDZm + 4U, // VFMSUB231PDZmb + 133U, // VFMSUB231PDZmbk + 8325U, // VFMSUB231PDZmbkz + 0U, // VFMSUB231PDZmk + 0U, // VFMSUB231PDZmkz + 4U, // VFMSUB231PDZr + 4U, // VFMSUB231PDZrb + 0U, // VFMSUB231PDZrbk + 0U, // VFMSUB231PDZrbkz + 0U, // VFMSUB231PDZrk + 0U, // VFMSUB231PDZrkz + 4U, // VFMSUB231PDm + 4U, // VFMSUB231PDr + 4U, // VFMSUB231PSYm + 4U, // VFMSUB231PSYr + 4U, // VFMSUB231PSZ128m + 4U, // VFMSUB231PSZ128mb + 133U, // VFMSUB231PSZ128mbk + 8325U, // VFMSUB231PSZ128mbkz + 0U, // VFMSUB231PSZ128mk + 0U, // VFMSUB231PSZ128mkz + 4U, // VFMSUB231PSZ128r + 0U, // VFMSUB231PSZ128rk + 0U, // VFMSUB231PSZ128rkz + 4U, // VFMSUB231PSZ256m + 4U, // VFMSUB231PSZ256mb + 133U, // VFMSUB231PSZ256mbk + 8325U, // VFMSUB231PSZ256mbkz + 0U, // VFMSUB231PSZ256mk + 0U, // VFMSUB231PSZ256mkz + 4U, // VFMSUB231PSZ256r + 0U, // VFMSUB231PSZ256rk + 0U, // VFMSUB231PSZ256rkz + 4U, // VFMSUB231PSZm + 4U, // VFMSUB231PSZmb + 133U, // VFMSUB231PSZmbk + 8325U, // VFMSUB231PSZmbkz + 0U, // VFMSUB231PSZmk + 0U, // VFMSUB231PSZmkz + 4U, // VFMSUB231PSZr + 4U, // VFMSUB231PSZrb + 0U, // VFMSUB231PSZrbk + 0U, // VFMSUB231PSZrbkz + 0U, // VFMSUB231PSZrk + 0U, // VFMSUB231PSZrkz + 4U, // VFMSUB231PSm + 4U, // VFMSUB231PSr + 4U, // VFMSUB231SDZm + 4U, // VFMSUB231SDZm_Int + 133U, // VFMSUB231SDZm_Intk + 8325U, // VFMSUB231SDZm_Intkz + 4U, // VFMSUB231SDZr + 4U, // VFMSUB231SDZr_Int + 0U, // VFMSUB231SDZr_Intk + 0U, // VFMSUB231SDZr_Intkz + 4U, // VFMSUB231SDZrb + 4U, // VFMSUB231SDZrb_Int + 0U, // VFMSUB231SDZrb_Intk + 0U, // VFMSUB231SDZrb_Intkz + 4U, // VFMSUB231SDm + 4U, // VFMSUB231SDm_Int + 4U, // VFMSUB231SDr + 4U, // VFMSUB231SDr_Int + 4U, // VFMSUB231SSZm + 4U, // VFMSUB231SSZm_Int + 133U, // VFMSUB231SSZm_Intk + 8325U, // VFMSUB231SSZm_Intkz + 4U, // VFMSUB231SSZr + 4U, // VFMSUB231SSZr_Int + 0U, // VFMSUB231SSZr_Intk + 0U, // VFMSUB231SSZr_Intkz + 4U, // VFMSUB231SSZrb + 4U, // VFMSUB231SSZrb_Int + 0U, // VFMSUB231SSZrb_Intk + 0U, // VFMSUB231SSZrb_Intkz + 4U, // VFMSUB231SSm + 4U, // VFMSUB231SSm_Int + 4U, // VFMSUB231SSr + 4U, // VFMSUB231SSr_Int + 4U, // VFMSUBADD132PDYm + 4U, // VFMSUBADD132PDYr + 4U, // VFMSUBADD132PDZ128m + 4U, // VFMSUBADD132PDZ128mb + 133U, // VFMSUBADD132PDZ128mbk + 8325U, // VFMSUBADD132PDZ128mbkz + 0U, // VFMSUBADD132PDZ128mk + 0U, // VFMSUBADD132PDZ128mkz + 4U, // VFMSUBADD132PDZ128r + 0U, // VFMSUBADD132PDZ128rk + 0U, // VFMSUBADD132PDZ128rkz + 4U, // VFMSUBADD132PDZ256m + 4U, // VFMSUBADD132PDZ256mb + 133U, // VFMSUBADD132PDZ256mbk + 8325U, // VFMSUBADD132PDZ256mbkz + 0U, // VFMSUBADD132PDZ256mk + 0U, // VFMSUBADD132PDZ256mkz + 4U, // VFMSUBADD132PDZ256r + 0U, // VFMSUBADD132PDZ256rk + 0U, // VFMSUBADD132PDZ256rkz + 4U, // VFMSUBADD132PDZm + 4U, // VFMSUBADD132PDZmb + 133U, // VFMSUBADD132PDZmbk + 8325U, // VFMSUBADD132PDZmbkz + 0U, // VFMSUBADD132PDZmk + 0U, // VFMSUBADD132PDZmkz + 4U, // VFMSUBADD132PDZr + 4U, // VFMSUBADD132PDZrb + 0U, // VFMSUBADD132PDZrbk + 0U, // VFMSUBADD132PDZrbkz + 0U, // VFMSUBADD132PDZrk + 0U, // VFMSUBADD132PDZrkz + 4U, // VFMSUBADD132PDm + 4U, // VFMSUBADD132PDr + 4U, // VFMSUBADD132PSYm + 4U, // VFMSUBADD132PSYr + 4U, // VFMSUBADD132PSZ128m + 4U, // VFMSUBADD132PSZ128mb + 133U, // VFMSUBADD132PSZ128mbk + 8325U, // VFMSUBADD132PSZ128mbkz + 0U, // VFMSUBADD132PSZ128mk + 0U, // VFMSUBADD132PSZ128mkz + 4U, // VFMSUBADD132PSZ128r + 0U, // VFMSUBADD132PSZ128rk + 0U, // VFMSUBADD132PSZ128rkz + 4U, // VFMSUBADD132PSZ256m + 4U, // VFMSUBADD132PSZ256mb + 133U, // VFMSUBADD132PSZ256mbk + 8325U, // VFMSUBADD132PSZ256mbkz + 0U, // VFMSUBADD132PSZ256mk + 0U, // VFMSUBADD132PSZ256mkz + 4U, // VFMSUBADD132PSZ256r + 0U, // VFMSUBADD132PSZ256rk + 0U, // VFMSUBADD132PSZ256rkz + 4U, // VFMSUBADD132PSZm + 4U, // VFMSUBADD132PSZmb + 133U, // VFMSUBADD132PSZmbk + 8325U, // VFMSUBADD132PSZmbkz + 0U, // VFMSUBADD132PSZmk + 0U, // VFMSUBADD132PSZmkz + 4U, // VFMSUBADD132PSZr + 4U, // VFMSUBADD132PSZrb + 0U, // VFMSUBADD132PSZrbk + 0U, // VFMSUBADD132PSZrbkz + 0U, // VFMSUBADD132PSZrk + 0U, // VFMSUBADD132PSZrkz + 4U, // VFMSUBADD132PSm + 4U, // VFMSUBADD132PSr + 4U, // VFMSUBADD213PDYm + 4U, // VFMSUBADD213PDYr + 4U, // VFMSUBADD213PDZ128m + 4U, // VFMSUBADD213PDZ128mb + 133U, // VFMSUBADD213PDZ128mbk + 8325U, // VFMSUBADD213PDZ128mbkz + 0U, // VFMSUBADD213PDZ128mk + 0U, // VFMSUBADD213PDZ128mkz + 4U, // VFMSUBADD213PDZ128r + 0U, // VFMSUBADD213PDZ128rk + 0U, // VFMSUBADD213PDZ128rkz + 4U, // VFMSUBADD213PDZ256m + 4U, // VFMSUBADD213PDZ256mb + 133U, // VFMSUBADD213PDZ256mbk + 8325U, // VFMSUBADD213PDZ256mbkz + 0U, // VFMSUBADD213PDZ256mk + 0U, // VFMSUBADD213PDZ256mkz + 4U, // VFMSUBADD213PDZ256r + 0U, // VFMSUBADD213PDZ256rk + 0U, // VFMSUBADD213PDZ256rkz + 4U, // VFMSUBADD213PDZm + 4U, // VFMSUBADD213PDZmb + 133U, // VFMSUBADD213PDZmbk + 8325U, // VFMSUBADD213PDZmbkz + 0U, // VFMSUBADD213PDZmk + 0U, // VFMSUBADD213PDZmkz + 4U, // VFMSUBADD213PDZr + 4U, // VFMSUBADD213PDZrb + 0U, // VFMSUBADD213PDZrbk + 0U, // VFMSUBADD213PDZrbkz + 0U, // VFMSUBADD213PDZrk + 0U, // VFMSUBADD213PDZrkz + 4U, // VFMSUBADD213PDm + 4U, // VFMSUBADD213PDr + 4U, // VFMSUBADD213PSYm + 4U, // VFMSUBADD213PSYr + 4U, // VFMSUBADD213PSZ128m + 4U, // VFMSUBADD213PSZ128mb + 133U, // VFMSUBADD213PSZ128mbk + 8325U, // VFMSUBADD213PSZ128mbkz + 0U, // VFMSUBADD213PSZ128mk + 0U, // VFMSUBADD213PSZ128mkz + 4U, // VFMSUBADD213PSZ128r + 0U, // VFMSUBADD213PSZ128rk + 0U, // VFMSUBADD213PSZ128rkz + 4U, // VFMSUBADD213PSZ256m + 4U, // VFMSUBADD213PSZ256mb + 133U, // VFMSUBADD213PSZ256mbk + 8325U, // VFMSUBADD213PSZ256mbkz + 0U, // VFMSUBADD213PSZ256mk + 0U, // VFMSUBADD213PSZ256mkz + 4U, // VFMSUBADD213PSZ256r + 0U, // VFMSUBADD213PSZ256rk + 0U, // VFMSUBADD213PSZ256rkz + 4U, // VFMSUBADD213PSZm + 4U, // VFMSUBADD213PSZmb + 133U, // VFMSUBADD213PSZmbk + 8325U, // VFMSUBADD213PSZmbkz + 0U, // VFMSUBADD213PSZmk + 0U, // VFMSUBADD213PSZmkz + 4U, // VFMSUBADD213PSZr + 4U, // VFMSUBADD213PSZrb + 0U, // VFMSUBADD213PSZrbk + 0U, // VFMSUBADD213PSZrbkz + 0U, // VFMSUBADD213PSZrk + 0U, // VFMSUBADD213PSZrkz + 4U, // VFMSUBADD213PSm + 4U, // VFMSUBADD213PSr + 4U, // VFMSUBADD231PDYm + 4U, // VFMSUBADD231PDYr + 4U, // VFMSUBADD231PDZ128m + 4U, // VFMSUBADD231PDZ128mb + 133U, // VFMSUBADD231PDZ128mbk + 8325U, // VFMSUBADD231PDZ128mbkz + 0U, // VFMSUBADD231PDZ128mk + 0U, // VFMSUBADD231PDZ128mkz + 4U, // VFMSUBADD231PDZ128r + 0U, // VFMSUBADD231PDZ128rk + 0U, // VFMSUBADD231PDZ128rkz + 4U, // VFMSUBADD231PDZ256m + 4U, // VFMSUBADD231PDZ256mb + 133U, // VFMSUBADD231PDZ256mbk + 8325U, // VFMSUBADD231PDZ256mbkz + 0U, // VFMSUBADD231PDZ256mk + 0U, // VFMSUBADD231PDZ256mkz + 4U, // VFMSUBADD231PDZ256r + 0U, // VFMSUBADD231PDZ256rk + 0U, // VFMSUBADD231PDZ256rkz + 4U, // VFMSUBADD231PDZm + 4U, // VFMSUBADD231PDZmb + 133U, // VFMSUBADD231PDZmbk + 8325U, // VFMSUBADD231PDZmbkz + 0U, // VFMSUBADD231PDZmk + 0U, // VFMSUBADD231PDZmkz + 4U, // VFMSUBADD231PDZr + 4U, // VFMSUBADD231PDZrb + 0U, // VFMSUBADD231PDZrbk + 0U, // VFMSUBADD231PDZrbkz + 0U, // VFMSUBADD231PDZrk + 0U, // VFMSUBADD231PDZrkz + 4U, // VFMSUBADD231PDm + 4U, // VFMSUBADD231PDr + 4U, // VFMSUBADD231PSYm + 4U, // VFMSUBADD231PSYr + 4U, // VFMSUBADD231PSZ128m + 4U, // VFMSUBADD231PSZ128mb + 133U, // VFMSUBADD231PSZ128mbk + 8325U, // VFMSUBADD231PSZ128mbkz + 0U, // VFMSUBADD231PSZ128mk + 0U, // VFMSUBADD231PSZ128mkz + 4U, // VFMSUBADD231PSZ128r + 0U, // VFMSUBADD231PSZ128rk + 0U, // VFMSUBADD231PSZ128rkz + 4U, // VFMSUBADD231PSZ256m + 4U, // VFMSUBADD231PSZ256mb + 133U, // VFMSUBADD231PSZ256mbk + 8325U, // VFMSUBADD231PSZ256mbkz + 0U, // VFMSUBADD231PSZ256mk + 0U, // VFMSUBADD231PSZ256mkz + 4U, // VFMSUBADD231PSZ256r + 0U, // VFMSUBADD231PSZ256rk + 0U, // VFMSUBADD231PSZ256rkz + 4U, // VFMSUBADD231PSZm + 4U, // VFMSUBADD231PSZmb + 133U, // VFMSUBADD231PSZmbk + 8325U, // VFMSUBADD231PSZmbkz + 0U, // VFMSUBADD231PSZmk + 0U, // VFMSUBADD231PSZmkz + 4U, // VFMSUBADD231PSZr + 4U, // VFMSUBADD231PSZrb + 0U, // VFMSUBADD231PSZrbk + 0U, // VFMSUBADD231PSZrbkz + 0U, // VFMSUBADD231PSZrk + 0U, // VFMSUBADD231PSZrkz + 4U, // VFMSUBADD231PSm + 4U, // VFMSUBADD231PSr + 72U, // VFMSUBADDPD4Ymr + 18636U, // VFMSUBADDPD4Yrm + 18636U, // VFMSUBADDPD4Yrr + 18636U, // VFMSUBADDPD4Yrr_REV + 72U, // VFMSUBADDPD4mr + 18636U, // VFMSUBADDPD4rm + 18636U, // VFMSUBADDPD4rr + 18636U, // VFMSUBADDPD4rr_REV + 72U, // VFMSUBADDPS4Ymr + 18636U, // VFMSUBADDPS4Yrm + 18636U, // VFMSUBADDPS4Yrr + 18636U, // VFMSUBADDPS4Yrr_REV + 72U, // VFMSUBADDPS4mr + 18636U, // VFMSUBADDPS4rm + 18636U, // VFMSUBADDPS4rr + 18636U, // VFMSUBADDPS4rr_REV + 72U, // VFMSUBPD4Ymr + 18636U, // VFMSUBPD4Yrm + 18636U, // VFMSUBPD4Yrr + 18636U, // VFMSUBPD4Yrr_REV + 72U, // VFMSUBPD4mr + 18636U, // VFMSUBPD4rm + 18636U, // VFMSUBPD4rr + 18636U, // VFMSUBPD4rr_REV + 72U, // VFMSUBPS4Ymr + 18636U, // VFMSUBPS4Yrm + 18636U, // VFMSUBPS4Yrr + 18636U, // VFMSUBPS4Yrr_REV + 72U, // VFMSUBPS4mr + 18636U, // VFMSUBPS4rm + 18636U, // VFMSUBPS4rr + 18636U, // VFMSUBPS4rr_REV + 18636U, // VFMSUBSD4mr + 18636U, // VFMSUBSD4mr_Int + 18636U, // VFMSUBSD4rm + 18636U, // VFMSUBSD4rm_Int + 18636U, // VFMSUBSD4rr + 18636U, // VFMSUBSD4rr_Int + 18636U, // VFMSUBSD4rr_Int_REV + 18636U, // VFMSUBSD4rr_REV + 18636U, // VFMSUBSS4mr + 18636U, // VFMSUBSS4mr_Int + 18636U, // VFMSUBSS4rm + 18636U, // VFMSUBSS4rm_Int + 18636U, // VFMSUBSS4rr + 18636U, // VFMSUBSS4rr_Int + 18636U, // VFMSUBSS4rr_Int_REV + 18636U, // VFMSUBSS4rr_REV + 4U, // VFNMADD132PDYm + 4U, // VFNMADD132PDYr + 4U, // VFNMADD132PDZ128m + 4U, // VFNMADD132PDZ128mb + 133U, // VFNMADD132PDZ128mbk + 8325U, // VFNMADD132PDZ128mbkz + 0U, // VFNMADD132PDZ128mk + 0U, // VFNMADD132PDZ128mkz + 4U, // VFNMADD132PDZ128r + 0U, // VFNMADD132PDZ128rk + 0U, // VFNMADD132PDZ128rkz + 4U, // VFNMADD132PDZ256m + 4U, // VFNMADD132PDZ256mb + 133U, // VFNMADD132PDZ256mbk + 8325U, // VFNMADD132PDZ256mbkz + 0U, // VFNMADD132PDZ256mk + 0U, // VFNMADD132PDZ256mkz + 4U, // VFNMADD132PDZ256r + 0U, // VFNMADD132PDZ256rk + 0U, // VFNMADD132PDZ256rkz + 4U, // VFNMADD132PDZm + 4U, // VFNMADD132PDZmb + 133U, // VFNMADD132PDZmbk + 8325U, // VFNMADD132PDZmbkz + 0U, // VFNMADD132PDZmk + 0U, // VFNMADD132PDZmkz + 4U, // VFNMADD132PDZr + 4U, // VFNMADD132PDZrb + 0U, // VFNMADD132PDZrbk + 0U, // VFNMADD132PDZrbkz + 0U, // VFNMADD132PDZrk + 0U, // VFNMADD132PDZrkz + 4U, // VFNMADD132PDm + 4U, // VFNMADD132PDr + 4U, // VFNMADD132PSYm + 4U, // VFNMADD132PSYr + 4U, // VFNMADD132PSZ128m + 4U, // VFNMADD132PSZ128mb + 133U, // VFNMADD132PSZ128mbk + 8325U, // VFNMADD132PSZ128mbkz + 0U, // VFNMADD132PSZ128mk + 0U, // VFNMADD132PSZ128mkz + 4U, // VFNMADD132PSZ128r + 0U, // VFNMADD132PSZ128rk + 0U, // VFNMADD132PSZ128rkz + 4U, // VFNMADD132PSZ256m + 4U, // VFNMADD132PSZ256mb + 133U, // VFNMADD132PSZ256mbk + 8325U, // VFNMADD132PSZ256mbkz + 0U, // VFNMADD132PSZ256mk + 0U, // VFNMADD132PSZ256mkz + 4U, // VFNMADD132PSZ256r + 0U, // VFNMADD132PSZ256rk + 0U, // VFNMADD132PSZ256rkz + 4U, // VFNMADD132PSZm + 4U, // VFNMADD132PSZmb + 133U, // VFNMADD132PSZmbk + 8325U, // VFNMADD132PSZmbkz + 0U, // VFNMADD132PSZmk + 0U, // VFNMADD132PSZmkz + 4U, // VFNMADD132PSZr + 4U, // VFNMADD132PSZrb + 0U, // VFNMADD132PSZrbk + 0U, // VFNMADD132PSZrbkz + 0U, // VFNMADD132PSZrk + 0U, // VFNMADD132PSZrkz + 4U, // VFNMADD132PSm + 4U, // VFNMADD132PSr + 4U, // VFNMADD132SDZm + 4U, // VFNMADD132SDZm_Int + 133U, // VFNMADD132SDZm_Intk + 8325U, // VFNMADD132SDZm_Intkz + 4U, // VFNMADD132SDZr + 4U, // VFNMADD132SDZr_Int + 0U, // VFNMADD132SDZr_Intk + 0U, // VFNMADD132SDZr_Intkz + 4U, // VFNMADD132SDZrb + 4U, // VFNMADD132SDZrb_Int + 0U, // VFNMADD132SDZrb_Intk + 0U, // VFNMADD132SDZrb_Intkz + 4U, // VFNMADD132SDm + 4U, // VFNMADD132SDm_Int + 4U, // VFNMADD132SDr + 4U, // VFNMADD132SDr_Int + 4U, // VFNMADD132SSZm + 4U, // VFNMADD132SSZm_Int + 133U, // VFNMADD132SSZm_Intk + 8325U, // VFNMADD132SSZm_Intkz + 4U, // VFNMADD132SSZr + 4U, // VFNMADD132SSZr_Int + 0U, // VFNMADD132SSZr_Intk + 0U, // VFNMADD132SSZr_Intkz + 4U, // VFNMADD132SSZrb + 4U, // VFNMADD132SSZrb_Int + 0U, // VFNMADD132SSZrb_Intk + 0U, // VFNMADD132SSZrb_Intkz + 4U, // VFNMADD132SSm + 4U, // VFNMADD132SSm_Int + 4U, // VFNMADD132SSr + 4U, // VFNMADD132SSr_Int + 4U, // VFNMADD213PDYm + 4U, // VFNMADD213PDYr + 4U, // VFNMADD213PDZ128m + 4U, // VFNMADD213PDZ128mb + 133U, // VFNMADD213PDZ128mbk + 8325U, // VFNMADD213PDZ128mbkz + 0U, // VFNMADD213PDZ128mk + 0U, // VFNMADD213PDZ128mkz + 4U, // VFNMADD213PDZ128r + 0U, // VFNMADD213PDZ128rk + 0U, // VFNMADD213PDZ128rkz + 4U, // VFNMADD213PDZ256m + 4U, // VFNMADD213PDZ256mb + 133U, // VFNMADD213PDZ256mbk + 8325U, // VFNMADD213PDZ256mbkz + 0U, // VFNMADD213PDZ256mk + 0U, // VFNMADD213PDZ256mkz + 4U, // VFNMADD213PDZ256r + 0U, // VFNMADD213PDZ256rk + 0U, // VFNMADD213PDZ256rkz + 4U, // VFNMADD213PDZm + 4U, // VFNMADD213PDZmb + 133U, // VFNMADD213PDZmbk + 8325U, // VFNMADD213PDZmbkz + 0U, // VFNMADD213PDZmk + 0U, // VFNMADD213PDZmkz + 4U, // VFNMADD213PDZr + 4U, // VFNMADD213PDZrb + 0U, // VFNMADD213PDZrbk + 0U, // VFNMADD213PDZrbkz + 0U, // VFNMADD213PDZrk + 0U, // VFNMADD213PDZrkz + 4U, // VFNMADD213PDm + 4U, // VFNMADD213PDr + 4U, // VFNMADD213PSYm + 4U, // VFNMADD213PSYr + 4U, // VFNMADD213PSZ128m + 4U, // VFNMADD213PSZ128mb + 133U, // VFNMADD213PSZ128mbk + 8325U, // VFNMADD213PSZ128mbkz + 0U, // VFNMADD213PSZ128mk + 0U, // VFNMADD213PSZ128mkz + 4U, // VFNMADD213PSZ128r + 0U, // VFNMADD213PSZ128rk + 0U, // VFNMADD213PSZ128rkz + 4U, // VFNMADD213PSZ256m + 4U, // VFNMADD213PSZ256mb + 133U, // VFNMADD213PSZ256mbk + 8325U, // VFNMADD213PSZ256mbkz + 0U, // VFNMADD213PSZ256mk + 0U, // VFNMADD213PSZ256mkz + 4U, // VFNMADD213PSZ256r + 0U, // VFNMADD213PSZ256rk + 0U, // VFNMADD213PSZ256rkz + 4U, // VFNMADD213PSZm + 4U, // VFNMADD213PSZmb + 133U, // VFNMADD213PSZmbk + 8325U, // VFNMADD213PSZmbkz + 0U, // VFNMADD213PSZmk + 0U, // VFNMADD213PSZmkz + 4U, // VFNMADD213PSZr + 4U, // VFNMADD213PSZrb + 0U, // VFNMADD213PSZrbk + 0U, // VFNMADD213PSZrbkz + 0U, // VFNMADD213PSZrk + 0U, // VFNMADD213PSZrkz + 4U, // VFNMADD213PSm + 4U, // VFNMADD213PSr + 4U, // VFNMADD213SDZm + 4U, // VFNMADD213SDZm_Int + 133U, // VFNMADD213SDZm_Intk + 8325U, // VFNMADD213SDZm_Intkz + 4U, // VFNMADD213SDZr + 4U, // VFNMADD213SDZr_Int + 0U, // VFNMADD213SDZr_Intk + 0U, // VFNMADD213SDZr_Intkz + 4U, // VFNMADD213SDZrb + 4U, // VFNMADD213SDZrb_Int + 0U, // VFNMADD213SDZrb_Intk + 0U, // VFNMADD213SDZrb_Intkz + 4U, // VFNMADD213SDm + 4U, // VFNMADD213SDm_Int + 4U, // VFNMADD213SDr + 4U, // VFNMADD213SDr_Int + 4U, // VFNMADD213SSZm + 4U, // VFNMADD213SSZm_Int + 133U, // VFNMADD213SSZm_Intk + 8325U, // VFNMADD213SSZm_Intkz + 4U, // VFNMADD213SSZr + 4U, // VFNMADD213SSZr_Int + 0U, // VFNMADD213SSZr_Intk + 0U, // VFNMADD213SSZr_Intkz + 4U, // VFNMADD213SSZrb + 4U, // VFNMADD213SSZrb_Int + 0U, // VFNMADD213SSZrb_Intk + 0U, // VFNMADD213SSZrb_Intkz + 4U, // VFNMADD213SSm + 4U, // VFNMADD213SSm_Int + 4U, // VFNMADD213SSr + 4U, // VFNMADD213SSr_Int + 4U, // VFNMADD231PDYm + 4U, // VFNMADD231PDYr + 4U, // VFNMADD231PDZ128m + 4U, // VFNMADD231PDZ128mb + 133U, // VFNMADD231PDZ128mbk + 8325U, // VFNMADD231PDZ128mbkz + 0U, // VFNMADD231PDZ128mk + 0U, // VFNMADD231PDZ128mkz + 4U, // VFNMADD231PDZ128r + 0U, // VFNMADD231PDZ128rk + 0U, // VFNMADD231PDZ128rkz + 4U, // VFNMADD231PDZ256m + 4U, // VFNMADD231PDZ256mb + 133U, // VFNMADD231PDZ256mbk + 8325U, // VFNMADD231PDZ256mbkz + 0U, // VFNMADD231PDZ256mk + 0U, // VFNMADD231PDZ256mkz + 4U, // VFNMADD231PDZ256r + 0U, // VFNMADD231PDZ256rk + 0U, // VFNMADD231PDZ256rkz + 4U, // VFNMADD231PDZm + 4U, // VFNMADD231PDZmb + 133U, // VFNMADD231PDZmbk + 8325U, // VFNMADD231PDZmbkz + 0U, // VFNMADD231PDZmk + 0U, // VFNMADD231PDZmkz + 4U, // VFNMADD231PDZr + 4U, // VFNMADD231PDZrb + 0U, // VFNMADD231PDZrbk + 0U, // VFNMADD231PDZrbkz + 0U, // VFNMADD231PDZrk + 0U, // VFNMADD231PDZrkz + 4U, // VFNMADD231PDm + 4U, // VFNMADD231PDr + 4U, // VFNMADD231PSYm + 4U, // VFNMADD231PSYr + 4U, // VFNMADD231PSZ128m + 4U, // VFNMADD231PSZ128mb + 133U, // VFNMADD231PSZ128mbk + 8325U, // VFNMADD231PSZ128mbkz + 0U, // VFNMADD231PSZ128mk + 0U, // VFNMADD231PSZ128mkz + 4U, // VFNMADD231PSZ128r + 0U, // VFNMADD231PSZ128rk + 0U, // VFNMADD231PSZ128rkz + 4U, // VFNMADD231PSZ256m + 4U, // VFNMADD231PSZ256mb + 133U, // VFNMADD231PSZ256mbk + 8325U, // VFNMADD231PSZ256mbkz + 0U, // VFNMADD231PSZ256mk + 0U, // VFNMADD231PSZ256mkz + 4U, // VFNMADD231PSZ256r + 0U, // VFNMADD231PSZ256rk + 0U, // VFNMADD231PSZ256rkz + 4U, // VFNMADD231PSZm + 4U, // VFNMADD231PSZmb + 133U, // VFNMADD231PSZmbk + 8325U, // VFNMADD231PSZmbkz + 0U, // VFNMADD231PSZmk + 0U, // VFNMADD231PSZmkz + 4U, // VFNMADD231PSZr + 4U, // VFNMADD231PSZrb + 0U, // VFNMADD231PSZrbk + 0U, // VFNMADD231PSZrbkz + 0U, // VFNMADD231PSZrk + 0U, // VFNMADD231PSZrkz + 4U, // VFNMADD231PSm + 4U, // VFNMADD231PSr + 4U, // VFNMADD231SDZm + 4U, // VFNMADD231SDZm_Int + 133U, // VFNMADD231SDZm_Intk + 8325U, // VFNMADD231SDZm_Intkz + 4U, // VFNMADD231SDZr + 4U, // VFNMADD231SDZr_Int + 0U, // VFNMADD231SDZr_Intk + 0U, // VFNMADD231SDZr_Intkz + 4U, // VFNMADD231SDZrb + 4U, // VFNMADD231SDZrb_Int + 0U, // VFNMADD231SDZrb_Intk + 0U, // VFNMADD231SDZrb_Intkz + 4U, // VFNMADD231SDm + 4U, // VFNMADD231SDm_Int + 4U, // VFNMADD231SDr + 4U, // VFNMADD231SDr_Int + 4U, // VFNMADD231SSZm + 4U, // VFNMADD231SSZm_Int + 133U, // VFNMADD231SSZm_Intk + 8325U, // VFNMADD231SSZm_Intkz + 4U, // VFNMADD231SSZr + 4U, // VFNMADD231SSZr_Int + 0U, // VFNMADD231SSZr_Intk + 0U, // VFNMADD231SSZr_Intkz + 4U, // VFNMADD231SSZrb + 4U, // VFNMADD231SSZrb_Int + 0U, // VFNMADD231SSZrb_Intk + 0U, // VFNMADD231SSZrb_Intkz + 4U, // VFNMADD231SSm + 4U, // VFNMADD231SSm_Int + 4U, // VFNMADD231SSr + 4U, // VFNMADD231SSr_Int + 72U, // VFNMADDPD4Ymr + 18636U, // VFNMADDPD4Yrm + 18636U, // VFNMADDPD4Yrr + 18636U, // VFNMADDPD4Yrr_REV + 72U, // VFNMADDPD4mr + 18636U, // VFNMADDPD4rm + 18636U, // VFNMADDPD4rr + 18636U, // VFNMADDPD4rr_REV + 72U, // VFNMADDPS4Ymr + 18636U, // VFNMADDPS4Yrm + 18636U, // VFNMADDPS4Yrr + 18636U, // VFNMADDPS4Yrr_REV + 72U, // VFNMADDPS4mr + 18636U, // VFNMADDPS4rm + 18636U, // VFNMADDPS4rr + 18636U, // VFNMADDPS4rr_REV + 18636U, // VFNMADDSD4mr + 18636U, // VFNMADDSD4mr_Int + 18636U, // VFNMADDSD4rm + 18636U, // VFNMADDSD4rm_Int + 18636U, // VFNMADDSD4rr + 18636U, // VFNMADDSD4rr_Int + 18636U, // VFNMADDSD4rr_Int_REV + 18636U, // VFNMADDSD4rr_REV + 18636U, // VFNMADDSS4mr + 18636U, // VFNMADDSS4mr_Int + 18636U, // VFNMADDSS4rm + 18636U, // VFNMADDSS4rm_Int + 18636U, // VFNMADDSS4rr + 18636U, // VFNMADDSS4rr_Int + 18636U, // VFNMADDSS4rr_Int_REV + 18636U, // VFNMADDSS4rr_REV + 4U, // VFNMSUB132PDYm + 4U, // VFNMSUB132PDYr + 4U, // VFNMSUB132PDZ128m + 4U, // VFNMSUB132PDZ128mb + 133U, // VFNMSUB132PDZ128mbk + 8325U, // VFNMSUB132PDZ128mbkz + 0U, // VFNMSUB132PDZ128mk + 0U, // VFNMSUB132PDZ128mkz + 4U, // VFNMSUB132PDZ128r + 0U, // VFNMSUB132PDZ128rk + 0U, // VFNMSUB132PDZ128rkz + 4U, // VFNMSUB132PDZ256m + 4U, // VFNMSUB132PDZ256mb + 133U, // VFNMSUB132PDZ256mbk + 8325U, // VFNMSUB132PDZ256mbkz + 0U, // VFNMSUB132PDZ256mk + 0U, // VFNMSUB132PDZ256mkz + 4U, // VFNMSUB132PDZ256r + 0U, // VFNMSUB132PDZ256rk + 0U, // VFNMSUB132PDZ256rkz + 4U, // VFNMSUB132PDZm + 4U, // VFNMSUB132PDZmb + 133U, // VFNMSUB132PDZmbk + 8325U, // VFNMSUB132PDZmbkz + 0U, // VFNMSUB132PDZmk + 0U, // VFNMSUB132PDZmkz + 4U, // VFNMSUB132PDZr + 4U, // VFNMSUB132PDZrb + 0U, // VFNMSUB132PDZrbk + 0U, // VFNMSUB132PDZrbkz + 0U, // VFNMSUB132PDZrk + 0U, // VFNMSUB132PDZrkz + 4U, // VFNMSUB132PDm + 4U, // VFNMSUB132PDr + 4U, // VFNMSUB132PSYm + 4U, // VFNMSUB132PSYr + 4U, // VFNMSUB132PSZ128m + 4U, // VFNMSUB132PSZ128mb + 133U, // VFNMSUB132PSZ128mbk + 8325U, // VFNMSUB132PSZ128mbkz + 0U, // VFNMSUB132PSZ128mk + 0U, // VFNMSUB132PSZ128mkz + 4U, // VFNMSUB132PSZ128r + 0U, // VFNMSUB132PSZ128rk + 0U, // VFNMSUB132PSZ128rkz + 4U, // VFNMSUB132PSZ256m + 4U, // VFNMSUB132PSZ256mb + 133U, // VFNMSUB132PSZ256mbk + 8325U, // VFNMSUB132PSZ256mbkz + 0U, // VFNMSUB132PSZ256mk + 0U, // VFNMSUB132PSZ256mkz + 4U, // VFNMSUB132PSZ256r + 0U, // VFNMSUB132PSZ256rk + 0U, // VFNMSUB132PSZ256rkz + 4U, // VFNMSUB132PSZm + 4U, // VFNMSUB132PSZmb + 133U, // VFNMSUB132PSZmbk + 8325U, // VFNMSUB132PSZmbkz + 0U, // VFNMSUB132PSZmk + 0U, // VFNMSUB132PSZmkz + 4U, // VFNMSUB132PSZr + 4U, // VFNMSUB132PSZrb + 0U, // VFNMSUB132PSZrbk + 0U, // VFNMSUB132PSZrbkz + 0U, // VFNMSUB132PSZrk + 0U, // VFNMSUB132PSZrkz + 4U, // VFNMSUB132PSm + 4U, // VFNMSUB132PSr + 4U, // VFNMSUB132SDZm + 4U, // VFNMSUB132SDZm_Int + 133U, // VFNMSUB132SDZm_Intk + 8325U, // VFNMSUB132SDZm_Intkz + 4U, // VFNMSUB132SDZr + 4U, // VFNMSUB132SDZr_Int + 0U, // VFNMSUB132SDZr_Intk + 0U, // VFNMSUB132SDZr_Intkz + 4U, // VFNMSUB132SDZrb + 4U, // VFNMSUB132SDZrb_Int + 0U, // VFNMSUB132SDZrb_Intk + 0U, // VFNMSUB132SDZrb_Intkz + 4U, // VFNMSUB132SDm + 4U, // VFNMSUB132SDm_Int + 4U, // VFNMSUB132SDr + 4U, // VFNMSUB132SDr_Int + 4U, // VFNMSUB132SSZm + 4U, // VFNMSUB132SSZm_Int + 133U, // VFNMSUB132SSZm_Intk + 8325U, // VFNMSUB132SSZm_Intkz + 4U, // VFNMSUB132SSZr + 4U, // VFNMSUB132SSZr_Int + 0U, // VFNMSUB132SSZr_Intk + 0U, // VFNMSUB132SSZr_Intkz + 4U, // VFNMSUB132SSZrb + 4U, // VFNMSUB132SSZrb_Int + 0U, // VFNMSUB132SSZrb_Intk + 0U, // VFNMSUB132SSZrb_Intkz + 4U, // VFNMSUB132SSm + 4U, // VFNMSUB132SSm_Int + 4U, // VFNMSUB132SSr + 4U, // VFNMSUB132SSr_Int + 4U, // VFNMSUB213PDYm + 4U, // VFNMSUB213PDYr + 4U, // VFNMSUB213PDZ128m + 4U, // VFNMSUB213PDZ128mb + 133U, // VFNMSUB213PDZ128mbk + 8325U, // VFNMSUB213PDZ128mbkz + 0U, // VFNMSUB213PDZ128mk + 0U, // VFNMSUB213PDZ128mkz + 4U, // VFNMSUB213PDZ128r + 0U, // VFNMSUB213PDZ128rk + 0U, // VFNMSUB213PDZ128rkz + 4U, // VFNMSUB213PDZ256m + 4U, // VFNMSUB213PDZ256mb + 133U, // VFNMSUB213PDZ256mbk + 8325U, // VFNMSUB213PDZ256mbkz + 0U, // VFNMSUB213PDZ256mk + 0U, // VFNMSUB213PDZ256mkz + 4U, // VFNMSUB213PDZ256r + 0U, // VFNMSUB213PDZ256rk + 0U, // VFNMSUB213PDZ256rkz + 4U, // VFNMSUB213PDZm + 4U, // VFNMSUB213PDZmb + 133U, // VFNMSUB213PDZmbk + 8325U, // VFNMSUB213PDZmbkz + 0U, // VFNMSUB213PDZmk + 0U, // VFNMSUB213PDZmkz + 4U, // VFNMSUB213PDZr + 4U, // VFNMSUB213PDZrb + 0U, // VFNMSUB213PDZrbk + 0U, // VFNMSUB213PDZrbkz + 0U, // VFNMSUB213PDZrk + 0U, // VFNMSUB213PDZrkz + 4U, // VFNMSUB213PDm + 4U, // VFNMSUB213PDr + 4U, // VFNMSUB213PSYm + 4U, // VFNMSUB213PSYr + 4U, // VFNMSUB213PSZ128m + 4U, // VFNMSUB213PSZ128mb + 133U, // VFNMSUB213PSZ128mbk + 8325U, // VFNMSUB213PSZ128mbkz + 0U, // VFNMSUB213PSZ128mk + 0U, // VFNMSUB213PSZ128mkz + 4U, // VFNMSUB213PSZ128r + 0U, // VFNMSUB213PSZ128rk + 0U, // VFNMSUB213PSZ128rkz + 4U, // VFNMSUB213PSZ256m + 4U, // VFNMSUB213PSZ256mb + 133U, // VFNMSUB213PSZ256mbk + 8325U, // VFNMSUB213PSZ256mbkz + 0U, // VFNMSUB213PSZ256mk + 0U, // VFNMSUB213PSZ256mkz + 4U, // VFNMSUB213PSZ256r + 0U, // VFNMSUB213PSZ256rk + 0U, // VFNMSUB213PSZ256rkz + 4U, // VFNMSUB213PSZm + 4U, // VFNMSUB213PSZmb + 133U, // VFNMSUB213PSZmbk + 8325U, // VFNMSUB213PSZmbkz + 0U, // VFNMSUB213PSZmk + 0U, // VFNMSUB213PSZmkz + 4U, // VFNMSUB213PSZr + 4U, // VFNMSUB213PSZrb + 0U, // VFNMSUB213PSZrbk + 0U, // VFNMSUB213PSZrbkz + 0U, // VFNMSUB213PSZrk + 0U, // VFNMSUB213PSZrkz + 4U, // VFNMSUB213PSm + 4U, // VFNMSUB213PSr + 4U, // VFNMSUB213SDZm + 4U, // VFNMSUB213SDZm_Int + 133U, // VFNMSUB213SDZm_Intk + 8325U, // VFNMSUB213SDZm_Intkz + 4U, // VFNMSUB213SDZr + 4U, // VFNMSUB213SDZr_Int + 0U, // VFNMSUB213SDZr_Intk + 0U, // VFNMSUB213SDZr_Intkz + 4U, // VFNMSUB213SDZrb + 4U, // VFNMSUB213SDZrb_Int + 0U, // VFNMSUB213SDZrb_Intk + 0U, // VFNMSUB213SDZrb_Intkz + 4U, // VFNMSUB213SDm + 4U, // VFNMSUB213SDm_Int + 4U, // VFNMSUB213SDr + 4U, // VFNMSUB213SDr_Int + 4U, // VFNMSUB213SSZm + 4U, // VFNMSUB213SSZm_Int + 133U, // VFNMSUB213SSZm_Intk + 8325U, // VFNMSUB213SSZm_Intkz + 4U, // VFNMSUB213SSZr + 4U, // VFNMSUB213SSZr_Int + 0U, // VFNMSUB213SSZr_Intk + 0U, // VFNMSUB213SSZr_Intkz + 4U, // VFNMSUB213SSZrb + 4U, // VFNMSUB213SSZrb_Int + 0U, // VFNMSUB213SSZrb_Intk + 0U, // VFNMSUB213SSZrb_Intkz + 4U, // VFNMSUB213SSm + 4U, // VFNMSUB213SSm_Int + 4U, // VFNMSUB213SSr + 4U, // VFNMSUB213SSr_Int + 4U, // VFNMSUB231PDYm + 4U, // VFNMSUB231PDYr + 4U, // VFNMSUB231PDZ128m + 4U, // VFNMSUB231PDZ128mb + 133U, // VFNMSUB231PDZ128mbk + 8325U, // VFNMSUB231PDZ128mbkz + 0U, // VFNMSUB231PDZ128mk + 0U, // VFNMSUB231PDZ128mkz + 4U, // VFNMSUB231PDZ128r + 0U, // VFNMSUB231PDZ128rk + 0U, // VFNMSUB231PDZ128rkz + 4U, // VFNMSUB231PDZ256m + 4U, // VFNMSUB231PDZ256mb + 133U, // VFNMSUB231PDZ256mbk + 8325U, // VFNMSUB231PDZ256mbkz + 0U, // VFNMSUB231PDZ256mk + 0U, // VFNMSUB231PDZ256mkz + 4U, // VFNMSUB231PDZ256r + 0U, // VFNMSUB231PDZ256rk + 0U, // VFNMSUB231PDZ256rkz + 4U, // VFNMSUB231PDZm + 4U, // VFNMSUB231PDZmb + 133U, // VFNMSUB231PDZmbk + 8325U, // VFNMSUB231PDZmbkz + 0U, // VFNMSUB231PDZmk + 0U, // VFNMSUB231PDZmkz + 4U, // VFNMSUB231PDZr + 4U, // VFNMSUB231PDZrb + 0U, // VFNMSUB231PDZrbk + 0U, // VFNMSUB231PDZrbkz + 0U, // VFNMSUB231PDZrk + 0U, // VFNMSUB231PDZrkz + 4U, // VFNMSUB231PDm + 4U, // VFNMSUB231PDr + 4U, // VFNMSUB231PSYm + 4U, // VFNMSUB231PSYr + 4U, // VFNMSUB231PSZ128m + 4U, // VFNMSUB231PSZ128mb + 133U, // VFNMSUB231PSZ128mbk + 8325U, // VFNMSUB231PSZ128mbkz + 0U, // VFNMSUB231PSZ128mk + 0U, // VFNMSUB231PSZ128mkz + 4U, // VFNMSUB231PSZ128r + 0U, // VFNMSUB231PSZ128rk + 0U, // VFNMSUB231PSZ128rkz + 4U, // VFNMSUB231PSZ256m + 4U, // VFNMSUB231PSZ256mb + 133U, // VFNMSUB231PSZ256mbk + 8325U, // VFNMSUB231PSZ256mbkz + 0U, // VFNMSUB231PSZ256mk + 0U, // VFNMSUB231PSZ256mkz + 4U, // VFNMSUB231PSZ256r + 0U, // VFNMSUB231PSZ256rk + 0U, // VFNMSUB231PSZ256rkz + 4U, // VFNMSUB231PSZm + 4U, // VFNMSUB231PSZmb + 133U, // VFNMSUB231PSZmbk + 8325U, // VFNMSUB231PSZmbkz + 0U, // VFNMSUB231PSZmk + 0U, // VFNMSUB231PSZmkz + 4U, // VFNMSUB231PSZr + 4U, // VFNMSUB231PSZrb + 0U, // VFNMSUB231PSZrbk + 0U, // VFNMSUB231PSZrbkz + 0U, // VFNMSUB231PSZrk + 0U, // VFNMSUB231PSZrkz + 4U, // VFNMSUB231PSm + 4U, // VFNMSUB231PSr + 4U, // VFNMSUB231SDZm + 4U, // VFNMSUB231SDZm_Int + 133U, // VFNMSUB231SDZm_Intk + 8325U, // VFNMSUB231SDZm_Intkz + 4U, // VFNMSUB231SDZr + 4U, // VFNMSUB231SDZr_Int + 0U, // VFNMSUB231SDZr_Intk + 0U, // VFNMSUB231SDZr_Intkz + 4U, // VFNMSUB231SDZrb + 4U, // VFNMSUB231SDZrb_Int + 0U, // VFNMSUB231SDZrb_Intk + 0U, // VFNMSUB231SDZrb_Intkz + 4U, // VFNMSUB231SDm + 4U, // VFNMSUB231SDm_Int + 4U, // VFNMSUB231SDr + 4U, // VFNMSUB231SDr_Int + 4U, // VFNMSUB231SSZm + 4U, // VFNMSUB231SSZm_Int + 133U, // VFNMSUB231SSZm_Intk + 8325U, // VFNMSUB231SSZm_Intkz + 4U, // VFNMSUB231SSZr + 4U, // VFNMSUB231SSZr_Int + 0U, // VFNMSUB231SSZr_Intk + 0U, // VFNMSUB231SSZr_Intkz + 4U, // VFNMSUB231SSZrb + 4U, // VFNMSUB231SSZrb_Int + 0U, // VFNMSUB231SSZrb_Intk + 0U, // VFNMSUB231SSZrb_Intkz + 4U, // VFNMSUB231SSm + 4U, // VFNMSUB231SSm_Int + 4U, // VFNMSUB231SSr + 4U, // VFNMSUB231SSr_Int + 72U, // VFNMSUBPD4Ymr + 18636U, // VFNMSUBPD4Yrm + 18636U, // VFNMSUBPD4Yrr + 18636U, // VFNMSUBPD4Yrr_REV + 72U, // VFNMSUBPD4mr + 18636U, // VFNMSUBPD4rm + 18636U, // VFNMSUBPD4rr + 18636U, // VFNMSUBPD4rr_REV + 72U, // VFNMSUBPS4Ymr + 18636U, // VFNMSUBPS4Yrm + 18636U, // VFNMSUBPS4Yrr + 18636U, // VFNMSUBPS4Yrr_REV + 72U, // VFNMSUBPS4mr + 18636U, // VFNMSUBPS4rm + 18636U, // VFNMSUBPS4rr + 18636U, // VFNMSUBPS4rr_REV + 18636U, // VFNMSUBSD4mr + 18636U, // VFNMSUBSD4mr_Int + 18636U, // VFNMSUBSD4rm + 18636U, // VFNMSUBSD4rm_Int + 18636U, // VFNMSUBSD4rr + 18636U, // VFNMSUBSD4rr_Int + 18636U, // VFNMSUBSD4rr_Int_REV + 18636U, // VFNMSUBSD4rr_REV + 18636U, // VFNMSUBSS4mr + 18636U, // VFNMSUBSS4mr_Int + 18636U, // VFNMSUBSS4rm + 18636U, // VFNMSUBSS4rm_Int + 18636U, // VFNMSUBSS4rr + 18636U, // VFNMSUBSS4rr_Int + 18636U, // VFNMSUBSS4rr_Int_REV + 18636U, // VFNMSUBSS4rr_REV + 0U, // VFPCLASSPDZ128rm + 5U, // VFPCLASSPDZ128rmb + 1157U, // VFPCLASSPDZ128rmbk + 3420U, // VFPCLASSPDZ128rmk + 72U, // VFPCLASSPDZ128rr + 1156U, // VFPCLASSPDZ128rrk + 0U, // VFPCLASSPDZ256rm + 5U, // VFPCLASSPDZ256rmb + 1157U, // VFPCLASSPDZ256rmbk + 3420U, // VFPCLASSPDZ256rmk + 72U, // VFPCLASSPDZ256rr + 1156U, // VFPCLASSPDZ256rrk + 0U, // VFPCLASSPDZrm + 5U, // VFPCLASSPDZrmb + 1157U, // VFPCLASSPDZrmbk + 3420U, // VFPCLASSPDZrmk + 72U, // VFPCLASSPDZrr + 1156U, // VFPCLASSPDZrrk + 0U, // VFPCLASSPSZ128rm + 5U, // VFPCLASSPSZ128rmb + 1157U, // VFPCLASSPSZ128rmbk + 3420U, // VFPCLASSPSZ128rmk + 72U, // VFPCLASSPSZ128rr + 1156U, // VFPCLASSPSZ128rrk + 0U, // VFPCLASSPSZ256rm + 5U, // VFPCLASSPSZ256rmb + 1157U, // VFPCLASSPSZ256rmbk + 3420U, // VFPCLASSPSZ256rmk + 72U, // VFPCLASSPSZ256rr + 1156U, // VFPCLASSPSZ256rrk + 0U, // VFPCLASSPSZrm + 5U, // VFPCLASSPSZrmb + 1157U, // VFPCLASSPSZrmbk + 3420U, // VFPCLASSPSZrmk + 72U, // VFPCLASSPSZrr + 1156U, // VFPCLASSPSZrrk + 4U, // VFPCLASSSDZrm + 1156U, // VFPCLASSSDZrmk + 72U, // VFPCLASSSDZrr + 1156U, // VFPCLASSSDZrrk + 4U, // VFPCLASSSSZrm + 1156U, // VFPCLASSSSZrmk + 72U, // VFPCLASSSSZrr + 1156U, // VFPCLASSSSZrrk + 0U, // VFRCZPDYrm + 0U, // VFRCZPDYrr + 0U, // VFRCZPDrm + 0U, // VFRCZPDrr + 0U, // VFRCZPSYrm + 0U, // VFRCZPSYrr + 0U, // VFRCZPSrm + 0U, // VFRCZPSrr + 0U, // VFRCZSDrm + 0U, // VFRCZSDrr + 0U, // VFRCZSSrm + 0U, // VFRCZSSrr + 0U, // VGATHERDPDYrm + 401U, // VGATHERDPDZ128rm + 401U, // VGATHERDPDZ256rm + 401U, // VGATHERDPDZrm + 0U, // VGATHERDPDrm + 0U, // VGATHERDPSYrm + 401U, // VGATHERDPSZ128rm + 401U, // VGATHERDPSZ256rm + 401U, // VGATHERDPSZrm + 0U, // VGATHERDPSrm + 0U, // VGATHERPF0DPDm + 0U, // VGATHERPF0DPSm + 0U, // VGATHERPF0QPDm + 0U, // VGATHERPF0QPSm + 0U, // VGATHERPF1DPDm + 0U, // VGATHERPF1DPSm + 0U, // VGATHERPF1QPDm + 0U, // VGATHERPF1QPSm + 0U, // VGATHERQPDYrm + 401U, // VGATHERQPDZ128rm + 401U, // VGATHERQPDZ256rm + 401U, // VGATHERQPDZrm + 0U, // VGATHERQPDrm + 0U, // VGATHERQPSYrm + 604U, // VGATHERQPSZ128rm + 401U, // VGATHERQPSZ256rm + 401U, // VGATHERQPSZrm + 4U, // VGATHERQPSrm + 0U, // VGETEXPPDZ128m + 0U, // VGETEXPPDZ128mb + 3356U, // VGETEXPPDZ128mbk + 4444U, // VGETEXPPDZ128mbkz + 405U, // VGETEXPPDZ128mk + 461U, // VGETEXPPDZ128mkz + 0U, // VGETEXPPDZ128r + 405U, // VGETEXPPDZ128rk + 461U, // VGETEXPPDZ128rkz + 0U, // VGETEXPPDZ256m + 0U, // VGETEXPPDZ256mb + 3356U, // VGETEXPPDZ256mbk + 4444U, // VGETEXPPDZ256mbkz + 405U, // VGETEXPPDZ256mk + 461U, // VGETEXPPDZ256mkz + 0U, // VGETEXPPDZ256r + 405U, // VGETEXPPDZ256rk + 461U, // VGETEXPPDZ256rkz + 0U, // VGETEXPPDZm + 0U, // VGETEXPPDZmb + 3356U, // VGETEXPPDZmbk + 4444U, // VGETEXPPDZmbkz + 405U, // VGETEXPPDZmk + 461U, // VGETEXPPDZmkz + 0U, // VGETEXPPDZr + 0U, // VGETEXPPDZrb + 405U, // VGETEXPPDZrbk + 461U, // VGETEXPPDZrbkz + 405U, // VGETEXPPDZrk + 461U, // VGETEXPPDZrkz + 0U, // VGETEXPPSZ128m + 0U, // VGETEXPPSZ128mb + 3356U, // VGETEXPPSZ128mbk + 4444U, // VGETEXPPSZ128mbkz + 405U, // VGETEXPPSZ128mk + 461U, // VGETEXPPSZ128mkz + 0U, // VGETEXPPSZ128r + 405U, // VGETEXPPSZ128rk + 461U, // VGETEXPPSZ128rkz + 0U, // VGETEXPPSZ256m + 0U, // VGETEXPPSZ256mb + 3356U, // VGETEXPPSZ256mbk + 4444U, // VGETEXPPSZ256mbkz + 405U, // VGETEXPPSZ256mk + 461U, // VGETEXPPSZ256mkz + 0U, // VGETEXPPSZ256r + 405U, // VGETEXPPSZ256rk + 461U, // VGETEXPPSZ256rkz + 0U, // VGETEXPPSZm + 0U, // VGETEXPPSZmb + 3356U, // VGETEXPPSZmbk + 4444U, // VGETEXPPSZmbkz + 405U, // VGETEXPPSZmk + 461U, // VGETEXPPSZmkz + 0U, // VGETEXPPSZr + 0U, // VGETEXPPSZrb + 405U, // VGETEXPPSZrbk + 461U, // VGETEXPPSZrbkz + 405U, // VGETEXPPSZrk + 461U, // VGETEXPPSZrkz + 72U, // VGETEXPSDZm + 133U, // VGETEXPSDZmk + 9348U, // VGETEXPSDZmkz + 4U, // VGETEXPSDZr + 4U, // VGETEXPSDZrb + 0U, // VGETEXPSDZrbk + 9348U, // VGETEXPSDZrbkz + 0U, // VGETEXPSDZrk + 9348U, // VGETEXPSDZrkz + 72U, // VGETEXPSSZm + 133U, // VGETEXPSSZmk + 9348U, // VGETEXPSSZmkz + 4U, // VGETEXPSSZr + 4U, // VGETEXPSSZrb + 0U, // VGETEXPSSZrbk + 9348U, // VGETEXPSSZrbkz + 0U, // VGETEXPSSZrk + 9348U, // VGETEXPSSZrkz + 5U, // VGETMANTPDZ128rmbi + 133U, // VGETMANTPDZ128rmbik + 9349U, // VGETMANTPDZ128rmbikz + 0U, // VGETMANTPDZ128rmi + 3356U, // VGETMANTPDZ128rmik + 4444U, // VGETMANTPDZ128rmikz + 72U, // VGETMANTPDZ128rri + 133U, // VGETMANTPDZ128rrik + 9348U, // VGETMANTPDZ128rrikz + 5U, // VGETMANTPDZ256rmbi + 133U, // VGETMANTPDZ256rmbik + 9349U, // VGETMANTPDZ256rmbikz + 0U, // VGETMANTPDZ256rmi + 3356U, // VGETMANTPDZ256rmik + 4444U, // VGETMANTPDZ256rmikz + 72U, // VGETMANTPDZ256rri + 133U, // VGETMANTPDZ256rrik + 9348U, // VGETMANTPDZ256rrikz + 5U, // VGETMANTPDZrmbi + 133U, // VGETMANTPDZrmbik + 9349U, // VGETMANTPDZrmbikz + 0U, // VGETMANTPDZrmi + 3356U, // VGETMANTPDZrmik + 4444U, // VGETMANTPDZrmikz + 72U, // VGETMANTPDZrri + 72U, // VGETMANTPDZrrib + 133U, // VGETMANTPDZrribk + 9348U, // VGETMANTPDZrribkz + 133U, // VGETMANTPDZrrik + 9348U, // VGETMANTPDZrrikz + 5U, // VGETMANTPSZ128rmbi + 133U, // VGETMANTPSZ128rmbik + 9349U, // VGETMANTPSZ128rmbikz + 0U, // VGETMANTPSZ128rmi + 3356U, // VGETMANTPSZ128rmik + 4444U, // VGETMANTPSZ128rmikz + 72U, // VGETMANTPSZ128rri + 133U, // VGETMANTPSZ128rrik + 9348U, // VGETMANTPSZ128rrikz + 5U, // VGETMANTPSZ256rmbi + 133U, // VGETMANTPSZ256rmbik + 9349U, // VGETMANTPSZ256rmbikz + 0U, // VGETMANTPSZ256rmi + 3356U, // VGETMANTPSZ256rmik + 4444U, // VGETMANTPSZ256rmikz + 72U, // VGETMANTPSZ256rri + 133U, // VGETMANTPSZ256rrik + 9348U, // VGETMANTPSZ256rrikz + 5U, // VGETMANTPSZrmbi + 133U, // VGETMANTPSZrmbik + 9349U, // VGETMANTPSZrmbikz + 0U, // VGETMANTPSZrmi + 3356U, // VGETMANTPSZrmik + 4444U, // VGETMANTPSZrmikz + 72U, // VGETMANTPSZrri + 72U, // VGETMANTPSZrrib + 133U, // VGETMANTPSZrribk + 9348U, // VGETMANTPSZrribkz + 133U, // VGETMANTPSZrrik + 9348U, // VGETMANTPSZrrikz + 18636U, // VGETMANTSDZrmi + 26832U, // VGETMANTSDZrmik + 26836U, // VGETMANTSDZrmikz + 18636U, // VGETMANTSDZrri + 18636U, // VGETMANTSDZrrib + 25U, // VGETMANTSDZrribk + 26837U, // VGETMANTSDZrribkz + 25U, // VGETMANTSDZrrik + 26837U, // VGETMANTSDZrrikz + 18636U, // VGETMANTSSZrmi + 26832U, // VGETMANTSSZrmik + 26836U, // VGETMANTSSZrmikz + 18636U, // VGETMANTSSZrri + 18636U, // VGETMANTSSZrrib + 25U, // VGETMANTSSZrribk + 26837U, // VGETMANTSSZrribkz + 25U, // VGETMANTSSZrrik + 26837U, // VGETMANTSSZrrikz + 72U, // VGF2P8AFFINEINVQBYrmi + 18636U, // VGF2P8AFFINEINVQBYrri + 18637U, // VGF2P8AFFINEINVQBZ128rmbi + 26833U, // VGF2P8AFFINEINVQBZ128rmbik + 26837U, // VGF2P8AFFINEINVQBZ128rmbikz + 72U, // VGF2P8AFFINEINVQBZ128rmi + 1U, // VGF2P8AFFINEINVQBZ128rmik + 9348U, // VGF2P8AFFINEINVQBZ128rmikz + 18636U, // VGF2P8AFFINEINVQBZ128rri + 25U, // VGF2P8AFFINEINVQBZ128rrik + 26837U, // VGF2P8AFFINEINVQBZ128rrikz + 18637U, // VGF2P8AFFINEINVQBZ256rmbi + 26833U, // VGF2P8AFFINEINVQBZ256rmbik + 26837U, // VGF2P8AFFINEINVQBZ256rmbikz + 72U, // VGF2P8AFFINEINVQBZ256rmi + 1U, // VGF2P8AFFINEINVQBZ256rmik + 9348U, // VGF2P8AFFINEINVQBZ256rmikz + 18636U, // VGF2P8AFFINEINVQBZ256rri + 25U, // VGF2P8AFFINEINVQBZ256rrik + 26837U, // VGF2P8AFFINEINVQBZ256rrikz + 18637U, // VGF2P8AFFINEINVQBZrmbi + 26833U, // VGF2P8AFFINEINVQBZrmbik + 26837U, // VGF2P8AFFINEINVQBZrmbikz + 72U, // VGF2P8AFFINEINVQBZrmi + 1U, // VGF2P8AFFINEINVQBZrmik + 9348U, // VGF2P8AFFINEINVQBZrmikz + 18636U, // VGF2P8AFFINEINVQBZrri + 25U, // VGF2P8AFFINEINVQBZrrik + 26837U, // VGF2P8AFFINEINVQBZrrikz + 72U, // VGF2P8AFFINEINVQBrmi + 18636U, // VGF2P8AFFINEINVQBrri + 72U, // VGF2P8AFFINEQBYrmi + 18636U, // VGF2P8AFFINEQBYrri + 18637U, // VGF2P8AFFINEQBZ128rmbi + 26833U, // VGF2P8AFFINEQBZ128rmbik + 26837U, // VGF2P8AFFINEQBZ128rmbikz + 72U, // VGF2P8AFFINEQBZ128rmi + 1U, // VGF2P8AFFINEQBZ128rmik + 9348U, // VGF2P8AFFINEQBZ128rmikz + 18636U, // VGF2P8AFFINEQBZ128rri + 25U, // VGF2P8AFFINEQBZ128rrik + 26837U, // VGF2P8AFFINEQBZ128rrikz + 18637U, // VGF2P8AFFINEQBZ256rmbi + 26833U, // VGF2P8AFFINEQBZ256rmbik + 26837U, // VGF2P8AFFINEQBZ256rmbikz + 72U, // VGF2P8AFFINEQBZ256rmi + 1U, // VGF2P8AFFINEQBZ256rmik + 9348U, // VGF2P8AFFINEQBZ256rmikz + 18636U, // VGF2P8AFFINEQBZ256rri + 25U, // VGF2P8AFFINEQBZ256rrik + 26837U, // VGF2P8AFFINEQBZ256rrikz + 18637U, // VGF2P8AFFINEQBZrmbi + 26833U, // VGF2P8AFFINEQBZrmbik + 26837U, // VGF2P8AFFINEQBZrmbikz + 72U, // VGF2P8AFFINEQBZrmi + 1U, // VGF2P8AFFINEQBZrmik + 9348U, // VGF2P8AFFINEQBZrmikz + 18636U, // VGF2P8AFFINEQBZrri + 25U, // VGF2P8AFFINEQBZrrik + 26837U, // VGF2P8AFFINEQBZrrikz + 72U, // VGF2P8AFFINEQBrmi + 18636U, // VGF2P8AFFINEQBrri + 4U, // VGF2P8MULBYrm + 4U, // VGF2P8MULBYrr + 4U, // VGF2P8MULBZ128rm + 132U, // VGF2P8MULBZ128rmk + 9348U, // VGF2P8MULBZ128rmkz + 4U, // VGF2P8MULBZ128rr + 0U, // VGF2P8MULBZ128rrk + 9348U, // VGF2P8MULBZ128rrkz + 4U, // VGF2P8MULBZ256rm + 132U, // VGF2P8MULBZ256rmk + 9348U, // VGF2P8MULBZ256rmkz + 4U, // VGF2P8MULBZ256rr + 0U, // VGF2P8MULBZ256rrk + 9348U, // VGF2P8MULBZ256rrkz + 4U, // VGF2P8MULBZrm + 132U, // VGF2P8MULBZrmk + 9348U, // VGF2P8MULBZrmkz + 4U, // VGF2P8MULBZrr + 0U, // VGF2P8MULBZrrk + 9348U, // VGF2P8MULBZrrkz + 4U, // VGF2P8MULBrm + 4U, // VGF2P8MULBrr + 4U, // VHADDPDYrm + 4U, // VHADDPDYrr + 4U, // VHADDPDrm + 4U, // VHADDPDrr + 4U, // VHADDPSYrm + 4U, // VHADDPSYrr + 4U, // VHADDPSrm + 4U, // VHADDPSrr + 4U, // VHSUBPDYrm + 4U, // VHSUBPDYrr + 4U, // VHSUBPDrm + 4U, // VHSUBPDrr + 4U, // VHSUBPSYrm + 4U, // VHSUBPSYrr + 4U, // VHSUBPSrm + 4U, // VHSUBPSrr + 72U, // VINSERTF128rm + 18636U, // VINSERTF128rr + 72U, // VINSERTF32x4Z256rm + 1U, // VINSERTF32x4Z256rmk + 9348U, // VINSERTF32x4Z256rmkz + 18636U, // VINSERTF32x4Z256rr + 25U, // VINSERTF32x4Z256rrk + 26837U, // VINSERTF32x4Z256rrkz + 72U, // VINSERTF32x4Zrm + 1U, // VINSERTF32x4Zrmk + 9348U, // VINSERTF32x4Zrmkz + 18636U, // VINSERTF32x4Zrr + 25U, // VINSERTF32x4Zrrk + 26837U, // VINSERTF32x4Zrrkz + 72U, // VINSERTF32x8Zrm + 1U, // VINSERTF32x8Zrmk + 9348U, // VINSERTF32x8Zrmkz + 18636U, // VINSERTF32x8Zrr + 25U, // VINSERTF32x8Zrrk + 26837U, // VINSERTF32x8Zrrkz + 72U, // VINSERTF64x2Z256rm + 1U, // VINSERTF64x2Z256rmk + 9348U, // VINSERTF64x2Z256rmkz + 18636U, // VINSERTF64x2Z256rr + 25U, // VINSERTF64x2Z256rrk + 26837U, // VINSERTF64x2Z256rrkz + 72U, // VINSERTF64x2Zrm + 1U, // VINSERTF64x2Zrmk + 9348U, // VINSERTF64x2Zrmkz + 18636U, // VINSERTF64x2Zrr + 25U, // VINSERTF64x2Zrrk + 26837U, // VINSERTF64x2Zrrkz + 72U, // VINSERTF64x4Zrm + 1U, // VINSERTF64x4Zrmk + 9348U, // VINSERTF64x4Zrmkz + 18636U, // VINSERTF64x4Zrr + 25U, // VINSERTF64x4Zrrk + 26837U, // VINSERTF64x4Zrrkz + 72U, // VINSERTI128rm + 18636U, // VINSERTI128rr + 72U, // VINSERTI32x4Z256rm + 1U, // VINSERTI32x4Z256rmk + 9348U, // VINSERTI32x4Z256rmkz + 18636U, // VINSERTI32x4Z256rr + 25U, // VINSERTI32x4Z256rrk + 26837U, // VINSERTI32x4Z256rrkz + 72U, // VINSERTI32x4Zrm + 1U, // VINSERTI32x4Zrmk + 9348U, // VINSERTI32x4Zrmkz + 18636U, // VINSERTI32x4Zrr + 25U, // VINSERTI32x4Zrrk + 26837U, // VINSERTI32x4Zrrkz + 72U, // VINSERTI32x8Zrm + 1U, // VINSERTI32x8Zrmk + 9348U, // VINSERTI32x8Zrmkz + 18636U, // VINSERTI32x8Zrr + 25U, // VINSERTI32x8Zrrk + 26837U, // VINSERTI32x8Zrrkz + 72U, // VINSERTI64x2Z256rm + 1U, // VINSERTI64x2Z256rmk + 9348U, // VINSERTI64x2Z256rmkz + 18636U, // VINSERTI64x2Z256rr + 25U, // VINSERTI64x2Z256rrk + 26837U, // VINSERTI64x2Z256rrkz + 72U, // VINSERTI64x2Zrm + 1U, // VINSERTI64x2Zrmk + 9348U, // VINSERTI64x2Zrmkz + 18636U, // VINSERTI64x2Zrr + 25U, // VINSERTI64x2Zrrk + 26837U, // VINSERTI64x2Zrrkz + 72U, // VINSERTI64x4Zrm + 1U, // VINSERTI64x4Zrmk + 9348U, // VINSERTI64x4Zrmkz + 18636U, // VINSERTI64x4Zrr + 25U, // VINSERTI64x4Zrrk + 26837U, // VINSERTI64x4Zrrkz + 18636U, // VINSERTPSZrm + 18636U, // VINSERTPSZrr + 18636U, // VINSERTPSrm + 18636U, // VINSERTPSrr + 0U, // VLDDQUYrm + 0U, // VLDDQUrm + 0U, // VLDMXCSR + 0U, // VMASKMOVDQU + 0U, // VMASKMOVDQU64 + 2U, // VMASKMOVPDYmr + 4U, // VMASKMOVPDYrm + 2U, // VMASKMOVPDmr + 4U, // VMASKMOVPDrm + 2U, // VMASKMOVPSYmr + 4U, // VMASKMOVPSYrm + 2U, // VMASKMOVPSmr + 4U, // VMASKMOVPSrm + 4U, // VMAXCPDYrm + 4U, // VMAXCPDYrr + 4U, // VMAXCPDZ128rm + 72U, // VMAXCPDZ128rmb + 133U, // VMAXCPDZ128rmbk + 9348U, // VMAXCPDZ128rmbkz + 0U, // VMAXCPDZ128rmk + 9348U, // VMAXCPDZ128rmkz + 4U, // VMAXCPDZ128rr + 0U, // VMAXCPDZ128rrk + 9348U, // VMAXCPDZ128rrkz + 4U, // VMAXCPDZ256rm + 72U, // VMAXCPDZ256rmb + 133U, // VMAXCPDZ256rmbk + 9348U, // VMAXCPDZ256rmbkz + 0U, // VMAXCPDZ256rmk + 9348U, // VMAXCPDZ256rmkz + 4U, // VMAXCPDZ256rr + 0U, // VMAXCPDZ256rrk + 9348U, // VMAXCPDZ256rrkz + 4U, // VMAXCPDZrm + 72U, // VMAXCPDZrmb + 133U, // VMAXCPDZrmbk + 9348U, // VMAXCPDZrmbkz + 0U, // VMAXCPDZrmk + 9348U, // VMAXCPDZrmkz + 4U, // VMAXCPDZrr + 0U, // VMAXCPDZrrk + 9348U, // VMAXCPDZrrkz + 4U, // VMAXCPDrm + 4U, // VMAXCPDrr + 4U, // VMAXCPSYrm + 4U, // VMAXCPSYrr + 4U, // VMAXCPSZ128rm + 72U, // VMAXCPSZ128rmb + 133U, // VMAXCPSZ128rmbk + 9348U, // VMAXCPSZ128rmbkz + 0U, // VMAXCPSZ128rmk + 9348U, // VMAXCPSZ128rmkz + 4U, // VMAXCPSZ128rr + 0U, // VMAXCPSZ128rrk + 9348U, // VMAXCPSZ128rrkz + 4U, // VMAXCPSZ256rm + 72U, // VMAXCPSZ256rmb + 133U, // VMAXCPSZ256rmbk + 9348U, // VMAXCPSZ256rmbkz + 0U, // VMAXCPSZ256rmk + 9348U, // VMAXCPSZ256rmkz + 4U, // VMAXCPSZ256rr + 0U, // VMAXCPSZ256rrk + 9348U, // VMAXCPSZ256rrkz + 4U, // VMAXCPSZrm + 72U, // VMAXCPSZrmb + 133U, // VMAXCPSZrmbk + 9348U, // VMAXCPSZrmbkz + 0U, // VMAXCPSZrmk + 9348U, // VMAXCPSZrmkz + 4U, // VMAXCPSZrr + 0U, // VMAXCPSZrrk + 9348U, // VMAXCPSZrrkz + 4U, // VMAXCPSrm + 4U, // VMAXCPSrr + 72U, // VMAXCSDZrm + 4U, // VMAXCSDZrr + 72U, // VMAXCSDrm + 4U, // VMAXCSDrr + 72U, // VMAXCSSZrm + 4U, // VMAXCSSZrr + 72U, // VMAXCSSrm + 4U, // VMAXCSSrr + 4U, // VMAXPDYrm + 4U, // VMAXPDYrr + 4U, // VMAXPDZ128rm + 72U, // VMAXPDZ128rmb + 133U, // VMAXPDZ128rmbk + 9348U, // VMAXPDZ128rmbkz + 0U, // VMAXPDZ128rmk + 9348U, // VMAXPDZ128rmkz + 4U, // VMAXPDZ128rr + 0U, // VMAXPDZ128rrk + 9348U, // VMAXPDZ128rrkz + 4U, // VMAXPDZ256rm + 72U, // VMAXPDZ256rmb + 133U, // VMAXPDZ256rmbk + 9348U, // VMAXPDZ256rmbkz + 0U, // VMAXPDZ256rmk + 9348U, // VMAXPDZ256rmkz + 4U, // VMAXPDZ256rr + 0U, // VMAXPDZ256rrk + 9348U, // VMAXPDZ256rrkz + 4U, // VMAXPDZrm + 72U, // VMAXPDZrmb + 133U, // VMAXPDZrmbk + 9348U, // VMAXPDZrmbkz + 0U, // VMAXPDZrmk + 9348U, // VMAXPDZrmkz + 4U, // VMAXPDZrr + 4U, // VMAXPDZrrb + 0U, // VMAXPDZrrbk + 9348U, // VMAXPDZrrbkz + 0U, // VMAXPDZrrk + 9348U, // VMAXPDZrrkz + 4U, // VMAXPDrm + 4U, // VMAXPDrr + 4U, // VMAXPSYrm + 4U, // VMAXPSYrr + 4U, // VMAXPSZ128rm + 72U, // VMAXPSZ128rmb + 133U, // VMAXPSZ128rmbk + 9348U, // VMAXPSZ128rmbkz + 0U, // VMAXPSZ128rmk + 9348U, // VMAXPSZ128rmkz + 4U, // VMAXPSZ128rr + 0U, // VMAXPSZ128rrk + 9348U, // VMAXPSZ128rrkz + 4U, // VMAXPSZ256rm + 72U, // VMAXPSZ256rmb + 133U, // VMAXPSZ256rmbk + 9348U, // VMAXPSZ256rmbkz + 0U, // VMAXPSZ256rmk + 9348U, // VMAXPSZ256rmkz + 4U, // VMAXPSZ256rr + 0U, // VMAXPSZ256rrk + 9348U, // VMAXPSZ256rrkz + 4U, // VMAXPSZrm + 72U, // VMAXPSZrmb + 133U, // VMAXPSZrmbk + 9348U, // VMAXPSZrmbkz + 0U, // VMAXPSZrmk + 9348U, // VMAXPSZrmkz + 4U, // VMAXPSZrr + 4U, // VMAXPSZrrb + 0U, // VMAXPSZrrbk + 9348U, // VMAXPSZrrbkz + 0U, // VMAXPSZrrk + 9348U, // VMAXPSZrrkz + 4U, // VMAXPSrm + 4U, // VMAXPSrr + 72U, // VMAXSDZrm + 72U, // VMAXSDZrm_Int + 133U, // VMAXSDZrm_Intk + 9348U, // VMAXSDZrm_Intkz + 4U, // VMAXSDZrr + 4U, // VMAXSDZrr_Int + 0U, // VMAXSDZrr_Intk + 9348U, // VMAXSDZrr_Intkz + 4U, // VMAXSDZrrb_Int + 0U, // VMAXSDZrrb_Intk + 9348U, // VMAXSDZrrb_Intkz + 72U, // VMAXSDrm + 72U, // VMAXSDrm_Int + 4U, // VMAXSDrr + 4U, // VMAXSDrr_Int + 72U, // VMAXSSZrm + 72U, // VMAXSSZrm_Int + 133U, // VMAXSSZrm_Intk + 9348U, // VMAXSSZrm_Intkz + 4U, // VMAXSSZrr + 4U, // VMAXSSZrr_Int + 0U, // VMAXSSZrr_Intk + 9348U, // VMAXSSZrr_Intkz + 4U, // VMAXSSZrrb_Int + 0U, // VMAXSSZrrb_Intk + 9348U, // VMAXSSZrrb_Intkz + 72U, // VMAXSSrm + 72U, // VMAXSSrm_Int + 4U, // VMAXSSrr + 4U, // VMAXSSrr_Int + 0U, // VMCALL + 0U, // VMCLEARm + 0U, // VMFUNC + 4U, // VMINCPDYrm + 4U, // VMINCPDYrr + 4U, // VMINCPDZ128rm + 72U, // VMINCPDZ128rmb + 133U, // VMINCPDZ128rmbk + 9348U, // VMINCPDZ128rmbkz + 0U, // VMINCPDZ128rmk + 9348U, // VMINCPDZ128rmkz + 4U, // VMINCPDZ128rr + 0U, // VMINCPDZ128rrk + 9348U, // VMINCPDZ128rrkz + 4U, // VMINCPDZ256rm + 72U, // VMINCPDZ256rmb + 133U, // VMINCPDZ256rmbk + 9348U, // VMINCPDZ256rmbkz + 0U, // VMINCPDZ256rmk + 9348U, // VMINCPDZ256rmkz + 4U, // VMINCPDZ256rr + 0U, // VMINCPDZ256rrk + 9348U, // VMINCPDZ256rrkz + 4U, // VMINCPDZrm + 72U, // VMINCPDZrmb + 133U, // VMINCPDZrmbk + 9348U, // VMINCPDZrmbkz + 0U, // VMINCPDZrmk + 9348U, // VMINCPDZrmkz + 4U, // VMINCPDZrr + 0U, // VMINCPDZrrk + 9348U, // VMINCPDZrrkz + 4U, // VMINCPDrm + 4U, // VMINCPDrr + 4U, // VMINCPSYrm + 4U, // VMINCPSYrr + 4U, // VMINCPSZ128rm + 72U, // VMINCPSZ128rmb + 133U, // VMINCPSZ128rmbk + 9348U, // VMINCPSZ128rmbkz + 0U, // VMINCPSZ128rmk + 9348U, // VMINCPSZ128rmkz + 4U, // VMINCPSZ128rr + 0U, // VMINCPSZ128rrk + 9348U, // VMINCPSZ128rrkz + 4U, // VMINCPSZ256rm + 72U, // VMINCPSZ256rmb + 133U, // VMINCPSZ256rmbk + 9348U, // VMINCPSZ256rmbkz + 0U, // VMINCPSZ256rmk + 9348U, // VMINCPSZ256rmkz + 4U, // VMINCPSZ256rr + 0U, // VMINCPSZ256rrk + 9348U, // VMINCPSZ256rrkz + 4U, // VMINCPSZrm + 72U, // VMINCPSZrmb + 133U, // VMINCPSZrmbk + 9348U, // VMINCPSZrmbkz + 0U, // VMINCPSZrmk + 9348U, // VMINCPSZrmkz + 4U, // VMINCPSZrr + 0U, // VMINCPSZrrk + 9348U, // VMINCPSZrrkz + 4U, // VMINCPSrm + 4U, // VMINCPSrr + 72U, // VMINCSDZrm + 4U, // VMINCSDZrr + 72U, // VMINCSDrm + 4U, // VMINCSDrr + 72U, // VMINCSSZrm + 4U, // VMINCSSZrr + 72U, // VMINCSSrm + 4U, // VMINCSSrr + 4U, // VMINPDYrm + 4U, // VMINPDYrr + 4U, // VMINPDZ128rm + 72U, // VMINPDZ128rmb + 133U, // VMINPDZ128rmbk + 9348U, // VMINPDZ128rmbkz + 0U, // VMINPDZ128rmk + 9348U, // VMINPDZ128rmkz + 4U, // VMINPDZ128rr + 0U, // VMINPDZ128rrk + 9348U, // VMINPDZ128rrkz + 4U, // VMINPDZ256rm + 72U, // VMINPDZ256rmb + 133U, // VMINPDZ256rmbk + 9348U, // VMINPDZ256rmbkz + 0U, // VMINPDZ256rmk + 9348U, // VMINPDZ256rmkz + 4U, // VMINPDZ256rr + 0U, // VMINPDZ256rrk + 9348U, // VMINPDZ256rrkz + 4U, // VMINPDZrm + 72U, // VMINPDZrmb + 133U, // VMINPDZrmbk + 9348U, // VMINPDZrmbkz + 0U, // VMINPDZrmk + 9348U, // VMINPDZrmkz + 4U, // VMINPDZrr + 4U, // VMINPDZrrb + 0U, // VMINPDZrrbk + 9348U, // VMINPDZrrbkz + 0U, // VMINPDZrrk + 9348U, // VMINPDZrrkz + 4U, // VMINPDrm + 4U, // VMINPDrr + 4U, // VMINPSYrm + 4U, // VMINPSYrr + 4U, // VMINPSZ128rm + 72U, // VMINPSZ128rmb + 133U, // VMINPSZ128rmbk + 9348U, // VMINPSZ128rmbkz + 0U, // VMINPSZ128rmk + 9348U, // VMINPSZ128rmkz + 4U, // VMINPSZ128rr + 0U, // VMINPSZ128rrk + 9348U, // VMINPSZ128rrkz + 4U, // VMINPSZ256rm + 72U, // VMINPSZ256rmb + 133U, // VMINPSZ256rmbk + 9348U, // VMINPSZ256rmbkz + 0U, // VMINPSZ256rmk + 9348U, // VMINPSZ256rmkz + 4U, // VMINPSZ256rr + 0U, // VMINPSZ256rrk + 9348U, // VMINPSZ256rrkz + 4U, // VMINPSZrm + 72U, // VMINPSZrmb + 133U, // VMINPSZrmbk + 9348U, // VMINPSZrmbkz + 0U, // VMINPSZrmk + 9348U, // VMINPSZrmkz + 4U, // VMINPSZrr + 4U, // VMINPSZrrb + 0U, // VMINPSZrrbk + 9348U, // VMINPSZrrbkz + 0U, // VMINPSZrrk + 9348U, // VMINPSZrrkz + 4U, // VMINPSrm + 4U, // VMINPSrr + 72U, // VMINSDZrm + 72U, // VMINSDZrm_Int + 133U, // VMINSDZrm_Intk + 9348U, // VMINSDZrm_Intkz + 4U, // VMINSDZrr + 4U, // VMINSDZrr_Int + 0U, // VMINSDZrr_Intk + 9348U, // VMINSDZrr_Intkz + 4U, // VMINSDZrrb_Int + 0U, // VMINSDZrrb_Intk + 9348U, // VMINSDZrrb_Intkz + 72U, // VMINSDrm + 72U, // VMINSDrm_Int + 4U, // VMINSDrr + 4U, // VMINSDrr_Int + 72U, // VMINSSZrm + 72U, // VMINSSZrm_Int + 133U, // VMINSSZrm_Intk + 9348U, // VMINSSZrm_Intkz + 4U, // VMINSSZrr + 4U, // VMINSSZrr_Int + 0U, // VMINSSZrr_Intk + 9348U, // VMINSSZrr_Intkz + 4U, // VMINSSZrrb_Int + 0U, // VMINSSZrrb_Intk + 9348U, // VMINSSZrrb_Intkz + 72U, // VMINSSrm + 72U, // VMINSSrm_Int + 4U, // VMINSSrr + 4U, // VMINSSrr_Int + 0U, // VMLAUNCH + 0U, // VMLOAD32 + 0U, // VMLOAD64 + 0U, // VMMCALL + 0U, // VMOV64toPQIZrm + 0U, // VMOV64toPQIZrr + 0U, // VMOV64toPQIrm + 0U, // VMOV64toPQIrr + 0U, // VMOV64toSDZrm + 0U, // VMOV64toSDZrr + 0U, // VMOV64toSDrm + 0U, // VMOV64toSDrr + 0U, // VMOVAPDYmr + 0U, // VMOVAPDYrm + 0U, // VMOVAPDYrr + 0U, // VMOVAPDYrr_REV + 0U, // VMOVAPDZ128mr + 49U, // VMOVAPDZ128mrk + 0U, // VMOVAPDZ128rm + 405U, // VMOVAPDZ128rmk + 461U, // VMOVAPDZ128rmkz + 0U, // VMOVAPDZ128rr + 0U, // VMOVAPDZ128rr_REV + 405U, // VMOVAPDZ128rrk + 397U, // VMOVAPDZ128rrk_REV + 461U, // VMOVAPDZ128rrkz + 461U, // VMOVAPDZ128rrkz_REV + 0U, // VMOVAPDZ256mr + 49U, // VMOVAPDZ256mrk + 0U, // VMOVAPDZ256rm + 405U, // VMOVAPDZ256rmk + 461U, // VMOVAPDZ256rmkz + 0U, // VMOVAPDZ256rr + 0U, // VMOVAPDZ256rr_REV + 405U, // VMOVAPDZ256rrk + 397U, // VMOVAPDZ256rrk_REV + 461U, // VMOVAPDZ256rrkz + 461U, // VMOVAPDZ256rrkz_REV + 0U, // VMOVAPDZmr + 49U, // VMOVAPDZmrk + 0U, // VMOVAPDZrm + 405U, // VMOVAPDZrmk + 461U, // VMOVAPDZrmkz + 0U, // VMOVAPDZrr + 0U, // VMOVAPDZrr_REV + 405U, // VMOVAPDZrrk + 397U, // VMOVAPDZrrk_REV + 461U, // VMOVAPDZrrkz + 461U, // VMOVAPDZrrkz_REV + 0U, // VMOVAPDmr + 0U, // VMOVAPDrm + 0U, // VMOVAPDrr + 0U, // VMOVAPDrr_REV + 0U, // VMOVAPSYmr + 0U, // VMOVAPSYrm + 0U, // VMOVAPSYrr + 0U, // VMOVAPSYrr_REV + 0U, // VMOVAPSZ128mr + 49U, // VMOVAPSZ128mrk + 0U, // VMOVAPSZ128rm + 405U, // VMOVAPSZ128rmk + 461U, // VMOVAPSZ128rmkz + 0U, // VMOVAPSZ128rr + 0U, // VMOVAPSZ128rr_REV + 405U, // VMOVAPSZ128rrk + 397U, // VMOVAPSZ128rrk_REV + 461U, // VMOVAPSZ128rrkz + 461U, // VMOVAPSZ128rrkz_REV + 0U, // VMOVAPSZ256mr + 49U, // VMOVAPSZ256mrk + 0U, // VMOVAPSZ256rm + 405U, // VMOVAPSZ256rmk + 461U, // VMOVAPSZ256rmkz + 0U, // VMOVAPSZ256rr + 0U, // VMOVAPSZ256rr_REV + 405U, // VMOVAPSZ256rrk + 397U, // VMOVAPSZ256rrk_REV + 461U, // VMOVAPSZ256rrkz + 461U, // VMOVAPSZ256rrkz_REV + 0U, // VMOVAPSZmr + 49U, // VMOVAPSZmrk + 0U, // VMOVAPSZrm + 405U, // VMOVAPSZrmk + 461U, // VMOVAPSZrmkz + 0U, // VMOVAPSZrr + 0U, // VMOVAPSZrr_REV + 405U, // VMOVAPSZrrk + 397U, // VMOVAPSZrrk_REV + 461U, // VMOVAPSZrrkz + 461U, // VMOVAPSZrrkz_REV + 0U, // VMOVAPSmr + 0U, // VMOVAPSrm + 0U, // VMOVAPSrr + 0U, // VMOVAPSrr_REV + 0U, // VMOVDDUPYrm + 0U, // VMOVDDUPYrr + 0U, // VMOVDDUPZ128rm + 3356U, // VMOVDDUPZ128rmk + 4444U, // VMOVDDUPZ128rmkz + 0U, // VMOVDDUPZ128rr + 405U, // VMOVDDUPZ128rrk + 461U, // VMOVDDUPZ128rrkz + 0U, // VMOVDDUPZ256rm + 405U, // VMOVDDUPZ256rmk + 461U, // VMOVDDUPZ256rmkz + 0U, // VMOVDDUPZ256rr + 405U, // VMOVDDUPZ256rrk + 461U, // VMOVDDUPZ256rrkz + 0U, // VMOVDDUPZrm + 405U, // VMOVDDUPZrmk + 461U, // VMOVDDUPZrmkz + 0U, // VMOVDDUPZrr + 405U, // VMOVDDUPZrrk + 461U, // VMOVDDUPZrrkz + 0U, // VMOVDDUPrm + 0U, // VMOVDDUPrr + 0U, // VMOVDI2PDIZrm + 0U, // VMOVDI2PDIZrr + 0U, // VMOVDI2PDIrm + 0U, // VMOVDI2PDIrr + 0U, // VMOVDI2SSZrm + 0U, // VMOVDI2SSZrr + 0U, // VMOVDI2SSrm + 0U, // VMOVDI2SSrr + 0U, // VMOVDQA32Z128mr + 49U, // VMOVDQA32Z128mrk + 0U, // VMOVDQA32Z128rm + 405U, // VMOVDQA32Z128rmk + 461U, // VMOVDQA32Z128rmkz + 0U, // VMOVDQA32Z128rr + 0U, // VMOVDQA32Z128rr_REV + 405U, // VMOVDQA32Z128rrk + 397U, // VMOVDQA32Z128rrk_REV + 461U, // VMOVDQA32Z128rrkz + 461U, // VMOVDQA32Z128rrkz_REV + 0U, // VMOVDQA32Z256mr + 49U, // VMOVDQA32Z256mrk + 0U, // VMOVDQA32Z256rm + 405U, // VMOVDQA32Z256rmk + 461U, // VMOVDQA32Z256rmkz + 0U, // VMOVDQA32Z256rr + 0U, // VMOVDQA32Z256rr_REV + 405U, // VMOVDQA32Z256rrk + 397U, // VMOVDQA32Z256rrk_REV + 461U, // VMOVDQA32Z256rrkz + 461U, // VMOVDQA32Z256rrkz_REV + 0U, // VMOVDQA32Zmr + 49U, // VMOVDQA32Zmrk + 0U, // VMOVDQA32Zrm + 405U, // VMOVDQA32Zrmk + 461U, // VMOVDQA32Zrmkz + 0U, // VMOVDQA32Zrr + 0U, // VMOVDQA32Zrr_REV + 405U, // VMOVDQA32Zrrk + 397U, // VMOVDQA32Zrrk_REV + 461U, // VMOVDQA32Zrrkz + 461U, // VMOVDQA32Zrrkz_REV + 0U, // VMOVDQA64Z128mr + 49U, // VMOVDQA64Z128mrk + 0U, // VMOVDQA64Z128rm + 405U, // VMOVDQA64Z128rmk + 461U, // VMOVDQA64Z128rmkz + 0U, // VMOVDQA64Z128rr + 0U, // VMOVDQA64Z128rr_REV + 405U, // VMOVDQA64Z128rrk + 397U, // VMOVDQA64Z128rrk_REV + 461U, // VMOVDQA64Z128rrkz + 461U, // VMOVDQA64Z128rrkz_REV + 0U, // VMOVDQA64Z256mr + 49U, // VMOVDQA64Z256mrk + 0U, // VMOVDQA64Z256rm + 405U, // VMOVDQA64Z256rmk + 461U, // VMOVDQA64Z256rmkz + 0U, // VMOVDQA64Z256rr + 0U, // VMOVDQA64Z256rr_REV + 405U, // VMOVDQA64Z256rrk + 397U, // VMOVDQA64Z256rrk_REV + 461U, // VMOVDQA64Z256rrkz + 461U, // VMOVDQA64Z256rrkz_REV + 0U, // VMOVDQA64Zmr + 49U, // VMOVDQA64Zmrk + 0U, // VMOVDQA64Zrm + 405U, // VMOVDQA64Zrmk + 461U, // VMOVDQA64Zrmkz + 0U, // VMOVDQA64Zrr + 0U, // VMOVDQA64Zrr_REV + 405U, // VMOVDQA64Zrrk + 397U, // VMOVDQA64Zrrk_REV + 461U, // VMOVDQA64Zrrkz + 461U, // VMOVDQA64Zrrkz_REV + 0U, // VMOVDQAYmr + 0U, // VMOVDQAYrm + 0U, // VMOVDQAYrr + 0U, // VMOVDQAYrr_REV + 0U, // VMOVDQAmr + 0U, // VMOVDQArm + 0U, // VMOVDQArr + 0U, // VMOVDQArr_REV + 0U, // VMOVDQU16Z128mr + 49U, // VMOVDQU16Z128mrk + 0U, // VMOVDQU16Z128rm + 405U, // VMOVDQU16Z128rmk + 461U, // VMOVDQU16Z128rmkz + 0U, // VMOVDQU16Z128rr + 0U, // VMOVDQU16Z128rr_REV + 405U, // VMOVDQU16Z128rrk + 397U, // VMOVDQU16Z128rrk_REV + 461U, // VMOVDQU16Z128rrkz + 461U, // VMOVDQU16Z128rrkz_REV + 0U, // VMOVDQU16Z256mr + 49U, // VMOVDQU16Z256mrk + 0U, // VMOVDQU16Z256rm + 405U, // VMOVDQU16Z256rmk + 461U, // VMOVDQU16Z256rmkz + 0U, // VMOVDQU16Z256rr + 0U, // VMOVDQU16Z256rr_REV + 405U, // VMOVDQU16Z256rrk + 397U, // VMOVDQU16Z256rrk_REV + 461U, // VMOVDQU16Z256rrkz + 461U, // VMOVDQU16Z256rrkz_REV + 0U, // VMOVDQU16Zmr + 49U, // VMOVDQU16Zmrk + 0U, // VMOVDQU16Zrm + 405U, // VMOVDQU16Zrmk + 461U, // VMOVDQU16Zrmkz + 0U, // VMOVDQU16Zrr + 0U, // VMOVDQU16Zrr_REV + 405U, // VMOVDQU16Zrrk + 397U, // VMOVDQU16Zrrk_REV + 461U, // VMOVDQU16Zrrkz + 461U, // VMOVDQU16Zrrkz_REV + 0U, // VMOVDQU32Z128mr + 49U, // VMOVDQU32Z128mrk + 0U, // VMOVDQU32Z128rm + 405U, // VMOVDQU32Z128rmk + 461U, // VMOVDQU32Z128rmkz + 0U, // VMOVDQU32Z128rr + 0U, // VMOVDQU32Z128rr_REV + 405U, // VMOVDQU32Z128rrk + 397U, // VMOVDQU32Z128rrk_REV + 461U, // VMOVDQU32Z128rrkz + 461U, // VMOVDQU32Z128rrkz_REV + 0U, // VMOVDQU32Z256mr + 49U, // VMOVDQU32Z256mrk + 0U, // VMOVDQU32Z256rm + 405U, // VMOVDQU32Z256rmk + 461U, // VMOVDQU32Z256rmkz + 0U, // VMOVDQU32Z256rr + 0U, // VMOVDQU32Z256rr_REV + 405U, // VMOVDQU32Z256rrk + 397U, // VMOVDQU32Z256rrk_REV + 461U, // VMOVDQU32Z256rrkz + 461U, // VMOVDQU32Z256rrkz_REV + 0U, // VMOVDQU32Zmr + 49U, // VMOVDQU32Zmrk + 0U, // VMOVDQU32Zrm + 405U, // VMOVDQU32Zrmk + 461U, // VMOVDQU32Zrmkz + 0U, // VMOVDQU32Zrr + 0U, // VMOVDQU32Zrr_REV + 405U, // VMOVDQU32Zrrk + 397U, // VMOVDQU32Zrrk_REV + 461U, // VMOVDQU32Zrrkz + 461U, // VMOVDQU32Zrrkz_REV + 0U, // VMOVDQU64Z128mr + 49U, // VMOVDQU64Z128mrk + 0U, // VMOVDQU64Z128rm + 405U, // VMOVDQU64Z128rmk + 461U, // VMOVDQU64Z128rmkz + 0U, // VMOVDQU64Z128rr + 0U, // VMOVDQU64Z128rr_REV + 405U, // VMOVDQU64Z128rrk + 397U, // VMOVDQU64Z128rrk_REV + 461U, // VMOVDQU64Z128rrkz + 461U, // VMOVDQU64Z128rrkz_REV + 0U, // VMOVDQU64Z256mr + 49U, // VMOVDQU64Z256mrk + 0U, // VMOVDQU64Z256rm + 405U, // VMOVDQU64Z256rmk + 461U, // VMOVDQU64Z256rmkz + 0U, // VMOVDQU64Z256rr + 0U, // VMOVDQU64Z256rr_REV + 405U, // VMOVDQU64Z256rrk + 397U, // VMOVDQU64Z256rrk_REV + 461U, // VMOVDQU64Z256rrkz + 461U, // VMOVDQU64Z256rrkz_REV + 0U, // VMOVDQU64Zmr + 49U, // VMOVDQU64Zmrk + 0U, // VMOVDQU64Zrm + 405U, // VMOVDQU64Zrmk + 461U, // VMOVDQU64Zrmkz + 0U, // VMOVDQU64Zrr + 0U, // VMOVDQU64Zrr_REV + 405U, // VMOVDQU64Zrrk + 397U, // VMOVDQU64Zrrk_REV + 461U, // VMOVDQU64Zrrkz + 461U, // VMOVDQU64Zrrkz_REV + 0U, // VMOVDQU8Z128mr + 49U, // VMOVDQU8Z128mrk + 0U, // VMOVDQU8Z128rm + 405U, // VMOVDQU8Z128rmk + 461U, // VMOVDQU8Z128rmkz + 0U, // VMOVDQU8Z128rr + 0U, // VMOVDQU8Z128rr_REV + 405U, // VMOVDQU8Z128rrk + 397U, // VMOVDQU8Z128rrk_REV + 461U, // VMOVDQU8Z128rrkz + 461U, // VMOVDQU8Z128rrkz_REV + 0U, // VMOVDQU8Z256mr + 49U, // VMOVDQU8Z256mrk + 0U, // VMOVDQU8Z256rm + 405U, // VMOVDQU8Z256rmk + 461U, // VMOVDQU8Z256rmkz + 0U, // VMOVDQU8Z256rr + 0U, // VMOVDQU8Z256rr_REV + 405U, // VMOVDQU8Z256rrk + 397U, // VMOVDQU8Z256rrk_REV + 461U, // VMOVDQU8Z256rrkz + 461U, // VMOVDQU8Z256rrkz_REV + 0U, // VMOVDQU8Zmr + 49U, // VMOVDQU8Zmrk + 0U, // VMOVDQU8Zrm + 405U, // VMOVDQU8Zrmk + 461U, // VMOVDQU8Zrmkz + 0U, // VMOVDQU8Zrr + 0U, // VMOVDQU8Zrr_REV + 405U, // VMOVDQU8Zrrk + 397U, // VMOVDQU8Zrrk_REV + 461U, // VMOVDQU8Zrrkz + 461U, // VMOVDQU8Zrrkz_REV + 0U, // VMOVDQUYmr + 0U, // VMOVDQUYrm + 0U, // VMOVDQUYrr + 0U, // VMOVDQUYrr_REV + 0U, // VMOVDQUmr + 0U, // VMOVDQUrm + 0U, // VMOVDQUrr + 0U, // VMOVDQUrr_REV + 4U, // VMOVHLPSZrr + 4U, // VMOVHLPSrr + 0U, // VMOVHPDZ128mr + 72U, // VMOVHPDZ128rm + 0U, // VMOVHPDmr + 72U, // VMOVHPDrm + 0U, // VMOVHPSZ128mr + 72U, // VMOVHPSZ128rm + 0U, // VMOVHPSmr + 72U, // VMOVHPSrm + 4U, // VMOVLHPSZrr + 4U, // VMOVLHPSrr + 0U, // VMOVLPDZ128mr + 72U, // VMOVLPDZ128rm + 0U, // VMOVLPDmr + 72U, // VMOVLPDrm + 0U, // VMOVLPSZ128mr + 72U, // VMOVLPSZ128rm + 0U, // VMOVLPSmr + 72U, // VMOVLPSrm + 0U, // VMOVMSKPDYrr + 0U, // VMOVMSKPDrr + 0U, // VMOVMSKPSYrr + 0U, // VMOVMSKPSrr + 0U, // VMOVNTDQAYrm + 0U, // VMOVNTDQAZ128rm + 0U, // VMOVNTDQAZ256rm + 0U, // VMOVNTDQAZrm + 0U, // VMOVNTDQArm + 0U, // VMOVNTDQYmr + 0U, // VMOVNTDQZ128mr + 0U, // VMOVNTDQZ256mr + 0U, // VMOVNTDQZmr + 0U, // VMOVNTDQmr + 0U, // VMOVNTPDYmr + 0U, // VMOVNTPDZ128mr + 0U, // VMOVNTPDZ256mr + 0U, // VMOVNTPDZmr + 0U, // VMOVNTPDmr + 0U, // VMOVNTPSYmr + 0U, // VMOVNTPSZ128mr + 0U, // VMOVNTPSZ256mr + 0U, // VMOVNTPSZmr + 0U, // VMOVNTPSmr + 0U, // VMOVPDI2DIZmr + 0U, // VMOVPDI2DIZrr + 0U, // VMOVPDI2DImr + 0U, // VMOVPDI2DIrr + 0U, // VMOVPQI2QIZmr + 0U, // VMOVPQI2QIZrr + 0U, // VMOVPQI2QImr + 0U, // VMOVPQI2QIrr + 0U, // VMOVPQIto64Zmr + 0U, // VMOVPQIto64Zrr + 0U, // VMOVPQIto64mr + 0U, // VMOVPQIto64rr + 0U, // VMOVQI2PQIZrm + 0U, // VMOVQI2PQIrm + 0U, // VMOVSDZmr + 49U, // VMOVSDZmrk + 0U, // VMOVSDZrm + 3356U, // VMOVSDZrmk + 4444U, // VMOVSDZrmkz + 4U, // VMOVSDZrr + 4U, // VMOVSDZrr_REV + 0U, // VMOVSDZrrk + 0U, // VMOVSDZrrk_REV + 9348U, // VMOVSDZrrkz + 9348U, // VMOVSDZrrkz_REV + 0U, // VMOVSDmr + 0U, // VMOVSDrm + 4U, // VMOVSDrr + 4U, // VMOVSDrr_REV + 0U, // VMOVSDto64Zmr + 0U, // VMOVSDto64Zrr + 0U, // VMOVSDto64mr + 0U, // VMOVSDto64rr + 0U, // VMOVSHDUPYrm + 0U, // VMOVSHDUPYrr + 0U, // VMOVSHDUPZ128rm + 405U, // VMOVSHDUPZ128rmk + 461U, // VMOVSHDUPZ128rmkz + 0U, // VMOVSHDUPZ128rr + 405U, // VMOVSHDUPZ128rrk + 461U, // VMOVSHDUPZ128rrkz + 0U, // VMOVSHDUPZ256rm + 405U, // VMOVSHDUPZ256rmk + 461U, // VMOVSHDUPZ256rmkz + 0U, // VMOVSHDUPZ256rr + 405U, // VMOVSHDUPZ256rrk + 461U, // VMOVSHDUPZ256rrkz + 0U, // VMOVSHDUPZrm + 405U, // VMOVSHDUPZrmk + 461U, // VMOVSHDUPZrmkz + 0U, // VMOVSHDUPZrr + 405U, // VMOVSHDUPZrrk + 461U, // VMOVSHDUPZrrkz + 0U, // VMOVSHDUPrm + 0U, // VMOVSHDUPrr + 0U, // VMOVSLDUPYrm + 0U, // VMOVSLDUPYrr + 0U, // VMOVSLDUPZ128rm + 405U, // VMOVSLDUPZ128rmk + 461U, // VMOVSLDUPZ128rmkz + 0U, // VMOVSLDUPZ128rr + 405U, // VMOVSLDUPZ128rrk + 461U, // VMOVSLDUPZ128rrkz + 0U, // VMOVSLDUPZ256rm + 405U, // VMOVSLDUPZ256rmk + 461U, // VMOVSLDUPZ256rmkz + 0U, // VMOVSLDUPZ256rr + 405U, // VMOVSLDUPZ256rrk + 461U, // VMOVSLDUPZ256rrkz + 0U, // VMOVSLDUPZrm + 405U, // VMOVSLDUPZrmk + 461U, // VMOVSLDUPZrmkz + 0U, // VMOVSLDUPZrr + 405U, // VMOVSLDUPZrrk + 461U, // VMOVSLDUPZrrkz + 0U, // VMOVSLDUPrm + 0U, // VMOVSLDUPrr + 0U, // VMOVSS2DIZmr + 0U, // VMOVSS2DIZrr + 0U, // VMOVSS2DImr + 0U, // VMOVSS2DIrr + 0U, // VMOVSSZmr + 49U, // VMOVSSZmrk + 0U, // VMOVSSZrm + 3356U, // VMOVSSZrmk + 4444U, // VMOVSSZrmkz + 4U, // VMOVSSZrr + 4U, // VMOVSSZrr_REV + 0U, // VMOVSSZrrk + 0U, // VMOVSSZrrk_REV + 9348U, // VMOVSSZrrkz + 9348U, // VMOVSSZrrkz_REV + 0U, // VMOVSSmr + 0U, // VMOVSSrm + 4U, // VMOVSSrr + 4U, // VMOVSSrr_REV + 0U, // VMOVUPDYmr + 0U, // VMOVUPDYrm + 0U, // VMOVUPDYrr + 0U, // VMOVUPDYrr_REV + 0U, // VMOVUPDZ128mr + 49U, // VMOVUPDZ128mrk + 0U, // VMOVUPDZ128rm + 405U, // VMOVUPDZ128rmk + 461U, // VMOVUPDZ128rmkz + 0U, // VMOVUPDZ128rr + 0U, // VMOVUPDZ128rr_REV + 405U, // VMOVUPDZ128rrk + 397U, // VMOVUPDZ128rrk_REV + 461U, // VMOVUPDZ128rrkz + 461U, // VMOVUPDZ128rrkz_REV + 0U, // VMOVUPDZ256mr + 49U, // VMOVUPDZ256mrk + 0U, // VMOVUPDZ256rm + 405U, // VMOVUPDZ256rmk + 461U, // VMOVUPDZ256rmkz + 0U, // VMOVUPDZ256rr + 0U, // VMOVUPDZ256rr_REV + 405U, // VMOVUPDZ256rrk + 397U, // VMOVUPDZ256rrk_REV + 461U, // VMOVUPDZ256rrkz + 461U, // VMOVUPDZ256rrkz_REV + 0U, // VMOVUPDZmr + 49U, // VMOVUPDZmrk + 0U, // VMOVUPDZrm + 405U, // VMOVUPDZrmk + 461U, // VMOVUPDZrmkz + 0U, // VMOVUPDZrr + 0U, // VMOVUPDZrr_REV + 405U, // VMOVUPDZrrk + 397U, // VMOVUPDZrrk_REV + 461U, // VMOVUPDZrrkz + 461U, // VMOVUPDZrrkz_REV + 0U, // VMOVUPDmr + 0U, // VMOVUPDrm + 0U, // VMOVUPDrr + 0U, // VMOVUPDrr_REV + 0U, // VMOVUPSYmr + 0U, // VMOVUPSYrm + 0U, // VMOVUPSYrr + 0U, // VMOVUPSYrr_REV + 0U, // VMOVUPSZ128mr + 49U, // VMOVUPSZ128mrk + 0U, // VMOVUPSZ128rm + 405U, // VMOVUPSZ128rmk + 461U, // VMOVUPSZ128rmkz + 0U, // VMOVUPSZ128rr + 0U, // VMOVUPSZ128rr_REV + 405U, // VMOVUPSZ128rrk + 397U, // VMOVUPSZ128rrk_REV + 461U, // VMOVUPSZ128rrkz + 461U, // VMOVUPSZ128rrkz_REV + 0U, // VMOVUPSZ256mr + 49U, // VMOVUPSZ256mrk + 0U, // VMOVUPSZ256rm + 405U, // VMOVUPSZ256rmk + 461U, // VMOVUPSZ256rmkz + 0U, // VMOVUPSZ256rr + 0U, // VMOVUPSZ256rr_REV + 405U, // VMOVUPSZ256rrk + 397U, // VMOVUPSZ256rrk_REV + 461U, // VMOVUPSZ256rrkz + 461U, // VMOVUPSZ256rrkz_REV + 0U, // VMOVUPSZmr + 49U, // VMOVUPSZmrk + 0U, // VMOVUPSZrm + 405U, // VMOVUPSZrmk + 461U, // VMOVUPSZrmkz + 0U, // VMOVUPSZrr + 0U, // VMOVUPSZrr_REV + 405U, // VMOVUPSZrrk + 397U, // VMOVUPSZrrk_REV + 461U, // VMOVUPSZrrkz + 461U, // VMOVUPSZrrkz_REV + 0U, // VMOVUPSmr + 0U, // VMOVUPSrm + 0U, // VMOVUPSrr + 0U, // VMOVUPSrr_REV + 0U, // VMOVZPQILo2PQIZrr + 0U, // VMOVZPQILo2PQIrr + 72U, // VMPSADBWYrmi + 18636U, // VMPSADBWYrri + 72U, // VMPSADBWrmi + 18636U, // VMPSADBWrri + 0U, // VMPTRLDm + 0U, // VMPTRSTm + 0U, // VMREAD32mr + 0U, // VMREAD32rr + 0U, // VMREAD64mr + 0U, // VMREAD64rr + 0U, // VMRESUME + 0U, // VMRUN32 + 0U, // VMRUN64 + 0U, // VMSAVE32 + 0U, // VMSAVE64 + 4U, // VMULPDYrm + 4U, // VMULPDYrr + 4U, // VMULPDZ128rm + 72U, // VMULPDZ128rmb + 133U, // VMULPDZ128rmbk + 9348U, // VMULPDZ128rmbkz + 0U, // VMULPDZ128rmk + 9348U, // VMULPDZ128rmkz + 4U, // VMULPDZ128rr + 0U, // VMULPDZ128rrk + 9348U, // VMULPDZ128rrkz + 4U, // VMULPDZ256rm + 72U, // VMULPDZ256rmb + 133U, // VMULPDZ256rmbk + 9348U, // VMULPDZ256rmbkz + 0U, // VMULPDZ256rmk + 9348U, // VMULPDZ256rmkz + 4U, // VMULPDZ256rr + 0U, // VMULPDZ256rrk + 9348U, // VMULPDZ256rrkz + 4U, // VMULPDZrm + 72U, // VMULPDZrmb + 133U, // VMULPDZrmbk + 9348U, // VMULPDZrmbkz + 0U, // VMULPDZrmk + 9348U, // VMULPDZrmkz + 4U, // VMULPDZrr + 4U, // VMULPDZrrb + 0U, // VMULPDZrrbk + 9348U, // VMULPDZrrbkz + 0U, // VMULPDZrrk + 9348U, // VMULPDZrrkz + 4U, // VMULPDrm + 4U, // VMULPDrr + 4U, // VMULPSYrm + 4U, // VMULPSYrr + 4U, // VMULPSZ128rm + 72U, // VMULPSZ128rmb + 133U, // VMULPSZ128rmbk + 9348U, // VMULPSZ128rmbkz + 0U, // VMULPSZ128rmk + 9348U, // VMULPSZ128rmkz + 4U, // VMULPSZ128rr + 0U, // VMULPSZ128rrk + 9348U, // VMULPSZ128rrkz + 4U, // VMULPSZ256rm + 72U, // VMULPSZ256rmb + 133U, // VMULPSZ256rmbk + 9348U, // VMULPSZ256rmbkz + 0U, // VMULPSZ256rmk + 9348U, // VMULPSZ256rmkz + 4U, // VMULPSZ256rr + 0U, // VMULPSZ256rrk + 9348U, // VMULPSZ256rrkz + 4U, // VMULPSZrm + 72U, // VMULPSZrmb + 133U, // VMULPSZrmbk + 9348U, // VMULPSZrmbkz + 0U, // VMULPSZrmk + 9348U, // VMULPSZrmkz + 4U, // VMULPSZrr + 4U, // VMULPSZrrb + 0U, // VMULPSZrrbk + 9348U, // VMULPSZrrbkz + 0U, // VMULPSZrrk + 9348U, // VMULPSZrrkz + 4U, // VMULPSrm + 4U, // VMULPSrr + 72U, // VMULSDZrm + 72U, // VMULSDZrm_Int + 133U, // VMULSDZrm_Intk + 9348U, // VMULSDZrm_Intkz + 4U, // VMULSDZrr + 4U, // VMULSDZrr_Int + 0U, // VMULSDZrr_Intk + 9348U, // VMULSDZrr_Intkz + 4U, // VMULSDZrrb_Int + 0U, // VMULSDZrrb_Intk + 9348U, // VMULSDZrrb_Intkz + 72U, // VMULSDrm + 72U, // VMULSDrm_Int + 4U, // VMULSDrr + 4U, // VMULSDrr_Int + 72U, // VMULSSZrm + 72U, // VMULSSZrm_Int + 133U, // VMULSSZrm_Intk + 9348U, // VMULSSZrm_Intkz + 4U, // VMULSSZrr + 4U, // VMULSSZrr_Int + 0U, // VMULSSZrr_Intk + 9348U, // VMULSSZrr_Intkz + 4U, // VMULSSZrrb_Int + 0U, // VMULSSZrrb_Intk + 9348U, // VMULSSZrrb_Intkz + 72U, // VMULSSrm + 72U, // VMULSSrm_Int + 4U, // VMULSSrr + 4U, // VMULSSrr_Int + 0U, // VMWRITE32rm + 0U, // VMWRITE32rr + 0U, // VMWRITE64rm + 0U, // VMWRITE64rr + 0U, // VMXOFF + 0U, // VMXON + 4U, // VORPDYrm + 4U, // VORPDYrr + 4U, // VORPDZ128rm + 72U, // VORPDZ128rmb + 133U, // VORPDZ128rmbk + 9348U, // VORPDZ128rmbkz + 0U, // VORPDZ128rmk + 9348U, // VORPDZ128rmkz + 4U, // VORPDZ128rr + 0U, // VORPDZ128rrk + 9348U, // VORPDZ128rrkz + 4U, // VORPDZ256rm + 72U, // VORPDZ256rmb + 133U, // VORPDZ256rmbk + 9348U, // VORPDZ256rmbkz + 0U, // VORPDZ256rmk + 9348U, // VORPDZ256rmkz + 4U, // VORPDZ256rr + 0U, // VORPDZ256rrk + 9348U, // VORPDZ256rrkz + 4U, // VORPDZrm + 72U, // VORPDZrmb + 133U, // VORPDZrmbk + 9348U, // VORPDZrmbkz + 0U, // VORPDZrmk + 9348U, // VORPDZrmkz + 4U, // VORPDZrr + 0U, // VORPDZrrk + 9348U, // VORPDZrrkz + 4U, // VORPDrm + 4U, // VORPDrr + 4U, // VORPSYrm + 4U, // VORPSYrr + 4U, // VORPSZ128rm + 72U, // VORPSZ128rmb + 133U, // VORPSZ128rmbk + 9348U, // VORPSZ128rmbkz + 0U, // VORPSZ128rmk + 9348U, // VORPSZ128rmkz + 4U, // VORPSZ128rr + 0U, // VORPSZ128rrk + 9348U, // VORPSZ128rrkz + 4U, // VORPSZ256rm + 72U, // VORPSZ256rmb + 133U, // VORPSZ256rmbk + 9348U, // VORPSZ256rmbkz + 0U, // VORPSZ256rmk + 9348U, // VORPSZ256rmkz + 4U, // VORPSZ256rr + 0U, // VORPSZ256rrk + 9348U, // VORPSZ256rrkz + 4U, // VORPSZrm + 72U, // VORPSZrmb + 133U, // VORPSZrmbk + 9348U, // VORPSZrmbkz + 0U, // VORPSZrmk + 9348U, // VORPSZrmkz + 4U, // VORPSZrr + 0U, // VORPSZrrk + 9348U, // VORPSZrrkz + 4U, // VORPSrm + 4U, // VORPSrr + 4U, // VP4DPWSSDSrm + 0U, // VP4DPWSSDSrmk + 0U, // VP4DPWSSDSrmkz + 4U, // VP4DPWSSDrm + 0U, // VP4DPWSSDrmk + 0U, // VP4DPWSSDrmkz + 0U, // VPABSBYrm + 0U, // VPABSBYrr + 0U, // VPABSBZ128rm + 405U, // VPABSBZ128rmk + 461U, // VPABSBZ128rmkz + 0U, // VPABSBZ128rr + 405U, // VPABSBZ128rrk + 461U, // VPABSBZ128rrkz + 0U, // VPABSBZ256rm + 405U, // VPABSBZ256rmk + 461U, // VPABSBZ256rmkz + 0U, // VPABSBZ256rr + 405U, // VPABSBZ256rrk + 461U, // VPABSBZ256rrkz + 0U, // VPABSBZrm + 405U, // VPABSBZrmk + 461U, // VPABSBZrmkz + 0U, // VPABSBZrr + 405U, // VPABSBZrrk + 461U, // VPABSBZrrkz + 0U, // VPABSBrm + 0U, // VPABSBrr + 0U, // VPABSDYrm + 0U, // VPABSDYrr + 0U, // VPABSDZ128rm + 0U, // VPABSDZ128rmb + 3356U, // VPABSDZ128rmbk + 4444U, // VPABSDZ128rmbkz + 405U, // VPABSDZ128rmk + 461U, // VPABSDZ128rmkz + 0U, // VPABSDZ128rr + 405U, // VPABSDZ128rrk + 461U, // VPABSDZ128rrkz + 0U, // VPABSDZ256rm + 0U, // VPABSDZ256rmb + 3356U, // VPABSDZ256rmbk + 4444U, // VPABSDZ256rmbkz + 405U, // VPABSDZ256rmk + 461U, // VPABSDZ256rmkz + 0U, // VPABSDZ256rr + 405U, // VPABSDZ256rrk + 461U, // VPABSDZ256rrkz + 0U, // VPABSDZrm + 0U, // VPABSDZrmb + 3356U, // VPABSDZrmbk + 4444U, // VPABSDZrmbkz + 405U, // VPABSDZrmk + 461U, // VPABSDZrmkz + 0U, // VPABSDZrr + 405U, // VPABSDZrrk + 461U, // VPABSDZrrkz + 0U, // VPABSDrm + 0U, // VPABSDrr + 0U, // VPABSQZ128rm + 0U, // VPABSQZ128rmb + 3356U, // VPABSQZ128rmbk + 4444U, // VPABSQZ128rmbkz + 405U, // VPABSQZ128rmk + 461U, // VPABSQZ128rmkz + 0U, // VPABSQZ128rr + 405U, // VPABSQZ128rrk + 461U, // VPABSQZ128rrkz + 0U, // VPABSQZ256rm + 0U, // VPABSQZ256rmb + 3356U, // VPABSQZ256rmbk + 4444U, // VPABSQZ256rmbkz + 405U, // VPABSQZ256rmk + 461U, // VPABSQZ256rmkz + 0U, // VPABSQZ256rr + 405U, // VPABSQZ256rrk + 461U, // VPABSQZ256rrkz + 0U, // VPABSQZrm + 0U, // VPABSQZrmb + 3356U, // VPABSQZrmbk + 4444U, // VPABSQZrmbkz + 405U, // VPABSQZrmk + 461U, // VPABSQZrmkz + 0U, // VPABSQZrr + 405U, // VPABSQZrrk + 461U, // VPABSQZrrkz + 0U, // VPABSWYrm + 0U, // VPABSWYrr + 0U, // VPABSWZ128rm + 405U, // VPABSWZ128rmk + 461U, // VPABSWZ128rmkz + 0U, // VPABSWZ128rr + 405U, // VPABSWZ128rrk + 461U, // VPABSWZ128rrkz + 0U, // VPABSWZ256rm + 405U, // VPABSWZ256rmk + 461U, // VPABSWZ256rmkz + 0U, // VPABSWZ256rr + 405U, // VPABSWZ256rrk + 461U, // VPABSWZ256rrkz + 0U, // VPABSWZrm + 405U, // VPABSWZrmk + 461U, // VPABSWZrmkz + 0U, // VPABSWZrr + 405U, // VPABSWZrrk + 461U, // VPABSWZrrkz + 0U, // VPABSWrm + 0U, // VPABSWrr + 4U, // VPACKSSDWYrm + 4U, // VPACKSSDWYrr + 4U, // VPACKSSDWZ128rm + 72U, // VPACKSSDWZ128rmb + 133U, // VPACKSSDWZ128rmbk + 9348U, // VPACKSSDWZ128rmbkz + 132U, // VPACKSSDWZ128rmk + 9348U, // VPACKSSDWZ128rmkz + 4U, // VPACKSSDWZ128rr + 0U, // VPACKSSDWZ128rrk + 9348U, // VPACKSSDWZ128rrkz + 4U, // VPACKSSDWZ256rm + 72U, // VPACKSSDWZ256rmb + 133U, // VPACKSSDWZ256rmbk + 9348U, // VPACKSSDWZ256rmbkz + 132U, // VPACKSSDWZ256rmk + 9348U, // VPACKSSDWZ256rmkz + 4U, // VPACKSSDWZ256rr + 0U, // VPACKSSDWZ256rrk + 9348U, // VPACKSSDWZ256rrkz + 4U, // VPACKSSDWZrm + 72U, // VPACKSSDWZrmb + 133U, // VPACKSSDWZrmbk + 9348U, // VPACKSSDWZrmbkz + 132U, // VPACKSSDWZrmk + 9348U, // VPACKSSDWZrmkz + 4U, // VPACKSSDWZrr + 0U, // VPACKSSDWZrrk + 9348U, // VPACKSSDWZrrkz + 4U, // VPACKSSDWrm + 4U, // VPACKSSDWrr + 4U, // VPACKSSWBYrm + 4U, // VPACKSSWBYrr + 4U, // VPACKSSWBZ128rm + 132U, // VPACKSSWBZ128rmk + 9348U, // VPACKSSWBZ128rmkz + 4U, // VPACKSSWBZ128rr + 0U, // VPACKSSWBZ128rrk + 9348U, // VPACKSSWBZ128rrkz + 4U, // VPACKSSWBZ256rm + 132U, // VPACKSSWBZ256rmk + 9348U, // VPACKSSWBZ256rmkz + 4U, // VPACKSSWBZ256rr + 0U, // VPACKSSWBZ256rrk + 9348U, // VPACKSSWBZ256rrkz + 4U, // VPACKSSWBZrm + 132U, // VPACKSSWBZrmk + 9348U, // VPACKSSWBZrmkz + 4U, // VPACKSSWBZrr + 0U, // VPACKSSWBZrrk + 9348U, // VPACKSSWBZrrkz + 4U, // VPACKSSWBrm + 4U, // VPACKSSWBrr + 4U, // VPACKUSDWYrm + 4U, // VPACKUSDWYrr + 4U, // VPACKUSDWZ128rm + 72U, // VPACKUSDWZ128rmb + 133U, // VPACKUSDWZ128rmbk + 9348U, // VPACKUSDWZ128rmbkz + 132U, // VPACKUSDWZ128rmk + 9348U, // VPACKUSDWZ128rmkz + 4U, // VPACKUSDWZ128rr + 0U, // VPACKUSDWZ128rrk + 9348U, // VPACKUSDWZ128rrkz + 4U, // VPACKUSDWZ256rm + 72U, // VPACKUSDWZ256rmb + 133U, // VPACKUSDWZ256rmbk + 9348U, // VPACKUSDWZ256rmbkz + 132U, // VPACKUSDWZ256rmk + 9348U, // VPACKUSDWZ256rmkz + 4U, // VPACKUSDWZ256rr + 0U, // VPACKUSDWZ256rrk + 9348U, // VPACKUSDWZ256rrkz + 4U, // VPACKUSDWZrm + 72U, // VPACKUSDWZrmb + 133U, // VPACKUSDWZrmbk + 9348U, // VPACKUSDWZrmbkz + 132U, // VPACKUSDWZrmk + 9348U, // VPACKUSDWZrmkz + 4U, // VPACKUSDWZrr + 0U, // VPACKUSDWZrrk + 9348U, // VPACKUSDWZrrkz + 4U, // VPACKUSDWrm + 4U, // VPACKUSDWrr + 4U, // VPACKUSWBYrm + 4U, // VPACKUSWBYrr + 4U, // VPACKUSWBZ128rm + 132U, // VPACKUSWBZ128rmk + 9348U, // VPACKUSWBZ128rmkz + 4U, // VPACKUSWBZ128rr + 0U, // VPACKUSWBZ128rrk + 9348U, // VPACKUSWBZ128rrkz + 4U, // VPACKUSWBZ256rm + 132U, // VPACKUSWBZ256rmk + 9348U, // VPACKUSWBZ256rmkz + 4U, // VPACKUSWBZ256rr + 0U, // VPACKUSWBZ256rrk + 9348U, // VPACKUSWBZ256rrkz + 4U, // VPACKUSWBZrm + 132U, // VPACKUSWBZrmk + 9348U, // VPACKUSWBZrmkz + 4U, // VPACKUSWBZrr + 0U, // VPACKUSWBZrrk + 9348U, // VPACKUSWBZrrkz + 4U, // VPACKUSWBrm + 4U, // VPACKUSWBrr + 4U, // VPADDBYrm + 4U, // VPADDBYrr + 4U, // VPADDBZ128rm + 132U, // VPADDBZ128rmk + 9348U, // VPADDBZ128rmkz + 4U, // VPADDBZ128rr + 0U, // VPADDBZ128rrk + 9348U, // VPADDBZ128rrkz + 4U, // VPADDBZ256rm + 132U, // VPADDBZ256rmk + 9348U, // VPADDBZ256rmkz + 4U, // VPADDBZ256rr + 0U, // VPADDBZ256rrk + 9348U, // VPADDBZ256rrkz + 4U, // VPADDBZrm + 132U, // VPADDBZrmk + 9348U, // VPADDBZrmkz + 4U, // VPADDBZrr + 0U, // VPADDBZrrk + 9348U, // VPADDBZrrkz + 4U, // VPADDBrm + 4U, // VPADDBrr + 4U, // VPADDDYrm + 4U, // VPADDDYrr + 4U, // VPADDDZ128rm + 72U, // VPADDDZ128rmb + 133U, // VPADDDZ128rmbk + 9348U, // VPADDDZ128rmbkz + 132U, // VPADDDZ128rmk + 9348U, // VPADDDZ128rmkz + 4U, // VPADDDZ128rr + 0U, // VPADDDZ128rrk + 9348U, // VPADDDZ128rrkz + 4U, // VPADDDZ256rm + 72U, // VPADDDZ256rmb + 133U, // VPADDDZ256rmbk + 9348U, // VPADDDZ256rmbkz + 132U, // VPADDDZ256rmk + 9348U, // VPADDDZ256rmkz + 4U, // VPADDDZ256rr + 0U, // VPADDDZ256rrk + 9348U, // VPADDDZ256rrkz + 4U, // VPADDDZrm + 72U, // VPADDDZrmb + 133U, // VPADDDZrmbk + 9348U, // VPADDDZrmbkz + 132U, // VPADDDZrmk + 9348U, // VPADDDZrmkz + 4U, // VPADDDZrr + 0U, // VPADDDZrrk + 9348U, // VPADDDZrrkz + 4U, // VPADDDrm + 4U, // VPADDDrr + 4U, // VPADDQYrm + 4U, // VPADDQYrr + 4U, // VPADDQZ128rm + 72U, // VPADDQZ128rmb + 133U, // VPADDQZ128rmbk + 9348U, // VPADDQZ128rmbkz + 132U, // VPADDQZ128rmk + 9348U, // VPADDQZ128rmkz + 4U, // VPADDQZ128rr + 0U, // VPADDQZ128rrk + 9348U, // VPADDQZ128rrkz + 4U, // VPADDQZ256rm + 72U, // VPADDQZ256rmb + 133U, // VPADDQZ256rmbk + 9348U, // VPADDQZ256rmbkz + 132U, // VPADDQZ256rmk + 9348U, // VPADDQZ256rmkz + 4U, // VPADDQZ256rr + 0U, // VPADDQZ256rrk + 9348U, // VPADDQZ256rrkz + 4U, // VPADDQZrm + 72U, // VPADDQZrmb + 133U, // VPADDQZrmbk + 9348U, // VPADDQZrmbkz + 132U, // VPADDQZrmk + 9348U, // VPADDQZrmkz + 4U, // VPADDQZrr + 0U, // VPADDQZrrk + 9348U, // VPADDQZrrkz + 4U, // VPADDQrm + 4U, // VPADDQrr + 4U, // VPADDSBYrm + 4U, // VPADDSBYrr + 4U, // VPADDSBZ128rm + 132U, // VPADDSBZ128rmk + 9348U, // VPADDSBZ128rmkz + 4U, // VPADDSBZ128rr + 0U, // VPADDSBZ128rrk + 9348U, // VPADDSBZ128rrkz + 4U, // VPADDSBZ256rm + 132U, // VPADDSBZ256rmk + 9348U, // VPADDSBZ256rmkz + 4U, // VPADDSBZ256rr + 0U, // VPADDSBZ256rrk + 9348U, // VPADDSBZ256rrkz + 4U, // VPADDSBZrm + 132U, // VPADDSBZrmk + 9348U, // VPADDSBZrmkz + 4U, // VPADDSBZrr + 0U, // VPADDSBZrrk + 9348U, // VPADDSBZrrkz + 4U, // VPADDSBrm + 4U, // VPADDSBrr + 4U, // VPADDSWYrm + 4U, // VPADDSWYrr + 4U, // VPADDSWZ128rm + 132U, // VPADDSWZ128rmk + 9348U, // VPADDSWZ128rmkz + 4U, // VPADDSWZ128rr + 0U, // VPADDSWZ128rrk + 9348U, // VPADDSWZ128rrkz + 4U, // VPADDSWZ256rm + 132U, // VPADDSWZ256rmk + 9348U, // VPADDSWZ256rmkz + 4U, // VPADDSWZ256rr + 0U, // VPADDSWZ256rrk + 9348U, // VPADDSWZ256rrkz + 4U, // VPADDSWZrm + 132U, // VPADDSWZrmk + 9348U, // VPADDSWZrmkz + 4U, // VPADDSWZrr + 0U, // VPADDSWZrrk + 9348U, // VPADDSWZrrkz + 4U, // VPADDSWrm + 4U, // VPADDSWrr + 4U, // VPADDUSBYrm + 4U, // VPADDUSBYrr + 4U, // VPADDUSBZ128rm + 132U, // VPADDUSBZ128rmk + 9348U, // VPADDUSBZ128rmkz + 4U, // VPADDUSBZ128rr + 0U, // VPADDUSBZ128rrk + 9348U, // VPADDUSBZ128rrkz + 4U, // VPADDUSBZ256rm + 132U, // VPADDUSBZ256rmk + 9348U, // VPADDUSBZ256rmkz + 4U, // VPADDUSBZ256rr + 0U, // VPADDUSBZ256rrk + 9348U, // VPADDUSBZ256rrkz + 4U, // VPADDUSBZrm + 132U, // VPADDUSBZrmk + 9348U, // VPADDUSBZrmkz + 4U, // VPADDUSBZrr + 0U, // VPADDUSBZrrk + 9348U, // VPADDUSBZrrkz + 4U, // VPADDUSBrm + 4U, // VPADDUSBrr + 4U, // VPADDUSWYrm + 4U, // VPADDUSWYrr + 4U, // VPADDUSWZ128rm + 132U, // VPADDUSWZ128rmk + 9348U, // VPADDUSWZ128rmkz + 4U, // VPADDUSWZ128rr + 0U, // VPADDUSWZ128rrk + 9348U, // VPADDUSWZ128rrkz + 4U, // VPADDUSWZ256rm + 132U, // VPADDUSWZ256rmk + 9348U, // VPADDUSWZ256rmkz + 4U, // VPADDUSWZ256rr + 0U, // VPADDUSWZ256rrk + 9348U, // VPADDUSWZ256rrkz + 4U, // VPADDUSWZrm + 132U, // VPADDUSWZrmk + 9348U, // VPADDUSWZrmkz + 4U, // VPADDUSWZrr + 0U, // VPADDUSWZrrk + 9348U, // VPADDUSWZrrkz + 4U, // VPADDUSWrm + 4U, // VPADDUSWrr + 4U, // VPADDWYrm + 4U, // VPADDWYrr + 4U, // VPADDWZ128rm + 132U, // VPADDWZ128rmk + 9348U, // VPADDWZ128rmkz + 4U, // VPADDWZ128rr + 0U, // VPADDWZ128rrk + 9348U, // VPADDWZ128rrkz + 4U, // VPADDWZ256rm + 132U, // VPADDWZ256rmk + 9348U, // VPADDWZ256rmkz + 4U, // VPADDWZ256rr + 0U, // VPADDWZ256rrk + 9348U, // VPADDWZ256rrkz + 4U, // VPADDWZrm + 132U, // VPADDWZrmk + 9348U, // VPADDWZrmkz + 4U, // VPADDWZrr + 0U, // VPADDWZrrk + 9348U, // VPADDWZrrkz + 4U, // VPADDWrm + 4U, // VPADDWrr + 72U, // VPALIGNRYrmi + 18636U, // VPALIGNRYrri + 72U, // VPALIGNRZ128rmi + 1U, // VPALIGNRZ128rmik + 9348U, // VPALIGNRZ128rmikz + 18636U, // VPALIGNRZ128rri + 25U, // VPALIGNRZ128rrik + 26837U, // VPALIGNRZ128rrikz + 72U, // VPALIGNRZ256rmi + 1U, // VPALIGNRZ256rmik + 9348U, // VPALIGNRZ256rmikz + 18636U, // VPALIGNRZ256rri + 25U, // VPALIGNRZ256rrik + 26837U, // VPALIGNRZ256rrikz + 72U, // VPALIGNRZrmi + 1U, // VPALIGNRZrmik + 9348U, // VPALIGNRZrmikz + 18636U, // VPALIGNRZrri + 25U, // VPALIGNRZrrik + 26837U, // VPALIGNRZrrikz + 72U, // VPALIGNRrmi + 18636U, // VPALIGNRrri + 4U, // VPANDDZ128rm + 72U, // VPANDDZ128rmb + 133U, // VPANDDZ128rmbk + 9348U, // VPANDDZ128rmbkz + 132U, // VPANDDZ128rmk + 9348U, // VPANDDZ128rmkz + 4U, // VPANDDZ128rr + 0U, // VPANDDZ128rrk + 9348U, // VPANDDZ128rrkz + 4U, // VPANDDZ256rm + 72U, // VPANDDZ256rmb + 133U, // VPANDDZ256rmbk + 9348U, // VPANDDZ256rmbkz + 132U, // VPANDDZ256rmk + 9348U, // VPANDDZ256rmkz + 4U, // VPANDDZ256rr + 0U, // VPANDDZ256rrk + 9348U, // VPANDDZ256rrkz + 4U, // VPANDDZrm + 72U, // VPANDDZrmb + 133U, // VPANDDZrmbk + 9348U, // VPANDDZrmbkz + 132U, // VPANDDZrmk + 9348U, // VPANDDZrmkz + 4U, // VPANDDZrr + 0U, // VPANDDZrrk + 9348U, // VPANDDZrrkz + 4U, // VPANDNDZ128rm + 72U, // VPANDNDZ128rmb + 133U, // VPANDNDZ128rmbk + 9348U, // VPANDNDZ128rmbkz + 132U, // VPANDNDZ128rmk + 9348U, // VPANDNDZ128rmkz + 4U, // VPANDNDZ128rr + 0U, // VPANDNDZ128rrk + 9348U, // VPANDNDZ128rrkz + 4U, // VPANDNDZ256rm + 72U, // VPANDNDZ256rmb + 133U, // VPANDNDZ256rmbk + 9348U, // VPANDNDZ256rmbkz + 132U, // VPANDNDZ256rmk + 9348U, // VPANDNDZ256rmkz + 4U, // VPANDNDZ256rr + 0U, // VPANDNDZ256rrk + 9348U, // VPANDNDZ256rrkz + 4U, // VPANDNDZrm + 72U, // VPANDNDZrmb + 133U, // VPANDNDZrmbk + 9348U, // VPANDNDZrmbkz + 132U, // VPANDNDZrmk + 9348U, // VPANDNDZrmkz + 4U, // VPANDNDZrr + 0U, // VPANDNDZrrk + 9348U, // VPANDNDZrrkz + 4U, // VPANDNQZ128rm + 72U, // VPANDNQZ128rmb + 133U, // VPANDNQZ128rmbk + 9348U, // VPANDNQZ128rmbkz + 132U, // VPANDNQZ128rmk + 9348U, // VPANDNQZ128rmkz + 4U, // VPANDNQZ128rr + 0U, // VPANDNQZ128rrk + 9348U, // VPANDNQZ128rrkz + 4U, // VPANDNQZ256rm + 72U, // VPANDNQZ256rmb + 133U, // VPANDNQZ256rmbk + 9348U, // VPANDNQZ256rmbkz + 132U, // VPANDNQZ256rmk + 9348U, // VPANDNQZ256rmkz + 4U, // VPANDNQZ256rr + 0U, // VPANDNQZ256rrk + 9348U, // VPANDNQZ256rrkz + 4U, // VPANDNQZrm + 72U, // VPANDNQZrmb + 133U, // VPANDNQZrmbk + 9348U, // VPANDNQZrmbkz + 132U, // VPANDNQZrmk + 9348U, // VPANDNQZrmkz + 4U, // VPANDNQZrr + 0U, // VPANDNQZrrk + 9348U, // VPANDNQZrrkz + 4U, // VPANDNYrm + 4U, // VPANDNYrr + 4U, // VPANDNrm + 4U, // VPANDNrr + 4U, // VPANDQZ128rm + 72U, // VPANDQZ128rmb + 133U, // VPANDQZ128rmbk + 9348U, // VPANDQZ128rmbkz + 132U, // VPANDQZ128rmk + 9348U, // VPANDQZ128rmkz + 4U, // VPANDQZ128rr + 0U, // VPANDQZ128rrk + 9348U, // VPANDQZ128rrkz + 4U, // VPANDQZ256rm + 72U, // VPANDQZ256rmb + 133U, // VPANDQZ256rmbk + 9348U, // VPANDQZ256rmbkz + 132U, // VPANDQZ256rmk + 9348U, // VPANDQZ256rmkz + 4U, // VPANDQZ256rr + 0U, // VPANDQZ256rrk + 9348U, // VPANDQZ256rrkz + 4U, // VPANDQZrm + 72U, // VPANDQZrmb + 133U, // VPANDQZrmbk + 9348U, // VPANDQZrmbkz + 132U, // VPANDQZrmk + 9348U, // VPANDQZrmkz + 4U, // VPANDQZrr + 0U, // VPANDQZrrk + 9348U, // VPANDQZrrkz + 4U, // VPANDYrm + 4U, // VPANDYrr + 4U, // VPANDrm + 4U, // VPANDrr + 4U, // VPAVGBYrm + 4U, // VPAVGBYrr + 4U, // VPAVGBZ128rm + 132U, // VPAVGBZ128rmk + 9348U, // VPAVGBZ128rmkz + 4U, // VPAVGBZ128rr + 0U, // VPAVGBZ128rrk + 9348U, // VPAVGBZ128rrkz + 4U, // VPAVGBZ256rm + 132U, // VPAVGBZ256rmk + 9348U, // VPAVGBZ256rmkz + 4U, // VPAVGBZ256rr + 0U, // VPAVGBZ256rrk + 9348U, // VPAVGBZ256rrkz + 4U, // VPAVGBZrm + 132U, // VPAVGBZrmk + 9348U, // VPAVGBZrmkz + 4U, // VPAVGBZrr + 0U, // VPAVGBZrrk + 9348U, // VPAVGBZrrkz + 4U, // VPAVGBrm + 4U, // VPAVGBrr + 4U, // VPAVGWYrm + 4U, // VPAVGWYrr + 4U, // VPAVGWZ128rm + 132U, // VPAVGWZ128rmk + 9348U, // VPAVGWZ128rmkz + 4U, // VPAVGWZ128rr + 0U, // VPAVGWZ128rrk + 9348U, // VPAVGWZ128rrkz + 4U, // VPAVGWZ256rm + 132U, // VPAVGWZ256rmk + 9348U, // VPAVGWZ256rmkz + 4U, // VPAVGWZ256rr + 0U, // VPAVGWZ256rrk + 9348U, // VPAVGWZ256rrkz + 4U, // VPAVGWZrm + 132U, // VPAVGWZrmk + 9348U, // VPAVGWZrmkz + 4U, // VPAVGWZrr + 0U, // VPAVGWZrrk + 9348U, // VPAVGWZrrkz + 4U, // VPAVGWrm + 4U, // VPAVGWrr + 72U, // VPBLENDDYrmi + 18636U, // VPBLENDDYrri + 72U, // VPBLENDDrmi + 18636U, // VPBLENDDrri + 4U, // VPBLENDMBZ128rm + 1156U, // VPBLENDMBZ128rmk + 9348U, // VPBLENDMBZ128rmkz + 4U, // VPBLENDMBZ128rr + 1156U, // VPBLENDMBZ128rrk + 9348U, // VPBLENDMBZ128rrkz + 4U, // VPBLENDMBZ256rm + 1156U, // VPBLENDMBZ256rmk + 9348U, // VPBLENDMBZ256rmkz + 4U, // VPBLENDMBZ256rr + 1156U, // VPBLENDMBZ256rrk + 9348U, // VPBLENDMBZ256rrkz + 4U, // VPBLENDMBZrm + 1156U, // VPBLENDMBZrmk + 9348U, // VPBLENDMBZrmkz + 4U, // VPBLENDMBZrr + 1156U, // VPBLENDMBZrrk + 9348U, // VPBLENDMBZrrkz + 4U, // VPBLENDMDZ128rm + 72U, // VPBLENDMDZ128rmb + 1156U, // VPBLENDMDZ128rmbk + 9348U, // VPBLENDMDZ128rmbkz + 1156U, // VPBLENDMDZ128rmk + 9348U, // VPBLENDMDZ128rmkz + 4U, // VPBLENDMDZ128rr + 1156U, // VPBLENDMDZ128rrk + 9348U, // VPBLENDMDZ128rrkz + 4U, // VPBLENDMDZ256rm + 72U, // VPBLENDMDZ256rmb + 1156U, // VPBLENDMDZ256rmbk + 9348U, // VPBLENDMDZ256rmbkz + 1156U, // VPBLENDMDZ256rmk + 9348U, // VPBLENDMDZ256rmkz + 4U, // VPBLENDMDZ256rr + 1156U, // VPBLENDMDZ256rrk + 9348U, // VPBLENDMDZ256rrkz + 4U, // VPBLENDMDZrm + 72U, // VPBLENDMDZrmb + 1156U, // VPBLENDMDZrmbk + 9348U, // VPBLENDMDZrmbkz + 1156U, // VPBLENDMDZrmk + 9348U, // VPBLENDMDZrmkz + 4U, // VPBLENDMDZrr + 1156U, // VPBLENDMDZrrk + 9348U, // VPBLENDMDZrrkz + 4U, // VPBLENDMQZ128rm + 72U, // VPBLENDMQZ128rmb + 1156U, // VPBLENDMQZ128rmbk + 9348U, // VPBLENDMQZ128rmbkz + 1156U, // VPBLENDMQZ128rmk + 9348U, // VPBLENDMQZ128rmkz + 4U, // VPBLENDMQZ128rr + 1156U, // VPBLENDMQZ128rrk + 9348U, // VPBLENDMQZ128rrkz + 4U, // VPBLENDMQZ256rm + 72U, // VPBLENDMQZ256rmb + 1156U, // VPBLENDMQZ256rmbk + 9348U, // VPBLENDMQZ256rmbkz + 1156U, // VPBLENDMQZ256rmk + 9348U, // VPBLENDMQZ256rmkz + 4U, // VPBLENDMQZ256rr + 1156U, // VPBLENDMQZ256rrk + 9348U, // VPBLENDMQZ256rrkz + 4U, // VPBLENDMQZrm + 72U, // VPBLENDMQZrmb + 1156U, // VPBLENDMQZrmbk + 9348U, // VPBLENDMQZrmbkz + 1156U, // VPBLENDMQZrmk + 9348U, // VPBLENDMQZrmkz + 4U, // VPBLENDMQZrr + 1156U, // VPBLENDMQZrrk + 9348U, // VPBLENDMQZrrkz + 4U, // VPBLENDMWZ128rm + 1156U, // VPBLENDMWZ128rmk + 9348U, // VPBLENDMWZ128rmkz + 4U, // VPBLENDMWZ128rr + 1156U, // VPBLENDMWZ128rrk + 9348U, // VPBLENDMWZ128rrkz + 4U, // VPBLENDMWZ256rm + 1156U, // VPBLENDMWZ256rmk + 9348U, // VPBLENDMWZ256rmkz + 4U, // VPBLENDMWZ256rr + 1156U, // VPBLENDMWZ256rrk + 9348U, // VPBLENDMWZ256rrkz + 4U, // VPBLENDMWZrm + 1156U, // VPBLENDMWZrmk + 9348U, // VPBLENDMWZrmkz + 4U, // VPBLENDMWZrr + 1156U, // VPBLENDMWZrrk + 9348U, // VPBLENDMWZrrkz + 72U, // VPBLENDVBYrm + 18636U, // VPBLENDVBYrr + 72U, // VPBLENDVBrm + 18636U, // VPBLENDVBrr + 72U, // VPBLENDWYrmi + 18636U, // VPBLENDWYrri + 72U, // VPBLENDWrmi + 18636U, // VPBLENDWrri + 0U, // VPBROADCASTBYrm + 0U, // VPBROADCASTBYrr + 0U, // VPBROADCASTBZ128m + 0U, // VPBROADCASTBZ128mk + 461U, // VPBROADCASTBZ128mkz + 0U, // VPBROADCASTBZ128r + 405U, // VPBROADCASTBZ128rk + 461U, // VPBROADCASTBZ128rkz + 0U, // VPBROADCASTBZ256m + 0U, // VPBROADCASTBZ256mk + 461U, // VPBROADCASTBZ256mkz + 0U, // VPBROADCASTBZ256r + 405U, // VPBROADCASTBZ256rk + 461U, // VPBROADCASTBZ256rkz + 0U, // VPBROADCASTBZm + 0U, // VPBROADCASTBZmk + 461U, // VPBROADCASTBZmkz + 0U, // VPBROADCASTBZr + 405U, // VPBROADCASTBZrk + 461U, // VPBROADCASTBZrkz + 0U, // VPBROADCASTBrZ128r + 405U, // VPBROADCASTBrZ128rk + 461U, // VPBROADCASTBrZ128rkz + 0U, // VPBROADCASTBrZ256r + 405U, // VPBROADCASTBrZ256rk + 461U, // VPBROADCASTBrZ256rkz + 0U, // VPBROADCASTBrZr + 405U, // VPBROADCASTBrZrk + 461U, // VPBROADCASTBrZrkz + 0U, // VPBROADCASTBrm + 0U, // VPBROADCASTBrr + 0U, // VPBROADCASTDYrm + 0U, // VPBROADCASTDYrr + 0U, // VPBROADCASTDZ128m + 3356U, // VPBROADCASTDZ128mk + 4444U, // VPBROADCASTDZ128mkz + 0U, // VPBROADCASTDZ128r + 405U, // VPBROADCASTDZ128rk + 461U, // VPBROADCASTDZ128rkz + 0U, // VPBROADCASTDZ256m + 3356U, // VPBROADCASTDZ256mk + 4444U, // VPBROADCASTDZ256mkz + 0U, // VPBROADCASTDZ256r + 405U, // VPBROADCASTDZ256rk + 461U, // VPBROADCASTDZ256rkz + 0U, // VPBROADCASTDZm + 3356U, // VPBROADCASTDZmk + 4444U, // VPBROADCASTDZmkz + 0U, // VPBROADCASTDZr + 405U, // VPBROADCASTDZrk + 461U, // VPBROADCASTDZrkz + 0U, // VPBROADCASTDrZ128r + 405U, // VPBROADCASTDrZ128rk + 461U, // VPBROADCASTDrZ128rkz + 0U, // VPBROADCASTDrZ256r + 405U, // VPBROADCASTDrZ256rk + 461U, // VPBROADCASTDrZ256rkz + 0U, // VPBROADCASTDrZr + 405U, // VPBROADCASTDrZrk + 461U, // VPBROADCASTDrZrkz + 0U, // VPBROADCASTDrm + 0U, // VPBROADCASTDrr + 0U, // VPBROADCASTMB2QZ128rr + 0U, // VPBROADCASTMB2QZ256rr + 0U, // VPBROADCASTMB2QZrr + 0U, // VPBROADCASTMW2DZ128rr + 0U, // VPBROADCASTMW2DZ256rr + 0U, // VPBROADCASTMW2DZrr + 0U, // VPBROADCASTQYrm + 0U, // VPBROADCASTQYrr + 0U, // VPBROADCASTQZ128m + 3356U, // VPBROADCASTQZ128mk + 4444U, // VPBROADCASTQZ128mkz + 0U, // VPBROADCASTQZ128r + 405U, // VPBROADCASTQZ128rk + 461U, // VPBROADCASTQZ128rkz + 0U, // VPBROADCASTQZ256m + 3356U, // VPBROADCASTQZ256mk + 4444U, // VPBROADCASTQZ256mkz + 0U, // VPBROADCASTQZ256r + 405U, // VPBROADCASTQZ256rk + 461U, // VPBROADCASTQZ256rkz + 0U, // VPBROADCASTQZm + 3356U, // VPBROADCASTQZmk + 4444U, // VPBROADCASTQZmkz + 0U, // VPBROADCASTQZr + 405U, // VPBROADCASTQZrk + 461U, // VPBROADCASTQZrkz + 0U, // VPBROADCASTQrZ128r + 405U, // VPBROADCASTQrZ128rk + 461U, // VPBROADCASTQrZ128rkz + 0U, // VPBROADCASTQrZ256r + 405U, // VPBROADCASTQrZ256rk + 461U, // VPBROADCASTQrZ256rkz + 0U, // VPBROADCASTQrZr + 405U, // VPBROADCASTQrZrk + 461U, // VPBROADCASTQrZrkz + 0U, // VPBROADCASTQrm + 0U, // VPBROADCASTQrr + 0U, // VPBROADCASTWYrm + 0U, // VPBROADCASTWYrr + 0U, // VPBROADCASTWZ128m + 0U, // VPBROADCASTWZ128mk + 461U, // VPBROADCASTWZ128mkz + 0U, // VPBROADCASTWZ128r + 405U, // VPBROADCASTWZ128rk + 461U, // VPBROADCASTWZ128rkz + 0U, // VPBROADCASTWZ256m + 0U, // VPBROADCASTWZ256mk + 461U, // VPBROADCASTWZ256mkz + 0U, // VPBROADCASTWZ256r + 405U, // VPBROADCASTWZ256rk + 461U, // VPBROADCASTWZ256rkz + 0U, // VPBROADCASTWZm + 0U, // VPBROADCASTWZmk + 461U, // VPBROADCASTWZmkz + 0U, // VPBROADCASTWZr + 405U, // VPBROADCASTWZrk + 461U, // VPBROADCASTWZrkz + 0U, // VPBROADCASTWrZ128r + 405U, // VPBROADCASTWrZ128rk + 461U, // VPBROADCASTWrZ128rkz + 0U, // VPBROADCASTWrZ256r + 405U, // VPBROADCASTWrZ256rk + 461U, // VPBROADCASTWrZ256rkz + 0U, // VPBROADCASTWrZr + 405U, // VPBROADCASTWrZrk + 461U, // VPBROADCASTWrZrkz + 0U, // VPBROADCASTWrm + 0U, // VPBROADCASTWrr + 72U, // VPCLMULQDQYrm + 18636U, // VPCLMULQDQYrr + 72U, // VPCLMULQDQZ128rm + 18636U, // VPCLMULQDQZ128rr + 72U, // VPCLMULQDQZ256rm + 18636U, // VPCLMULQDQZ256rr + 72U, // VPCLMULQDQZrm + 18636U, // VPCLMULQDQZrr + 72U, // VPCLMULQDQrm + 18636U, // VPCLMULQDQrr + 72U, // VPCMOVYrmr + 18636U, // VPCMOVYrrm + 18636U, // VPCMOVYrrr + 18636U, // VPCMOVYrrr_REV + 72U, // VPCMOVrmr + 18636U, // VPCMOVrrm + 18636U, // VPCMOVrrr + 18636U, // VPCMOVrrr_REV + 2U, // VPCMPBZ128rmi + 72U, // VPCMPBZ128rmi_alt + 2U, // VPCMPBZ128rmik + 1156U, // VPCMPBZ128rmik_alt + 18636U, // VPCMPBZ128rri + 18636U, // VPCMPBZ128rri_alt + 26837U, // VPCMPBZ128rrik + 26837U, // VPCMPBZ128rrik_alt + 2U, // VPCMPBZ256rmi + 72U, // VPCMPBZ256rmi_alt + 2U, // VPCMPBZ256rmik + 1156U, // VPCMPBZ256rmik_alt + 18636U, // VPCMPBZ256rri + 18636U, // VPCMPBZ256rri_alt + 26837U, // VPCMPBZ256rrik + 26837U, // VPCMPBZ256rrik_alt + 2U, // VPCMPBZrmi + 72U, // VPCMPBZrmi_alt + 2U, // VPCMPBZrmik + 1156U, // VPCMPBZrmik_alt + 18636U, // VPCMPBZrri + 18636U, // VPCMPBZrri_alt + 26837U, // VPCMPBZrrik + 26837U, // VPCMPBZrrik_alt + 2U, // VPCMPDZ128rmi + 72U, // VPCMPDZ128rmi_alt + 21863U, // VPCMPDZ128rmib + 18637U, // VPCMPDZ128rmib_alt + 29991U, // VPCMPDZ128rmibk + 26837U, // VPCMPDZ128rmibk_alt + 2U, // VPCMPDZ128rmik + 1156U, // VPCMPDZ128rmik_alt + 18636U, // VPCMPDZ128rri + 18636U, // VPCMPDZ128rri_alt + 26837U, // VPCMPDZ128rrik + 26837U, // VPCMPDZ128rrik_alt + 2U, // VPCMPDZ256rmi + 72U, // VPCMPDZ256rmi_alt + 21867U, // VPCMPDZ256rmib + 18637U, // VPCMPDZ256rmib_alt + 29995U, // VPCMPDZ256rmibk + 26837U, // VPCMPDZ256rmibk_alt + 2U, // VPCMPDZ256rmik + 1156U, // VPCMPDZ256rmik_alt + 18636U, // VPCMPDZ256rri + 18636U, // VPCMPDZ256rri_alt + 26837U, // VPCMPDZ256rrik + 26837U, // VPCMPDZ256rrik_alt + 2U, // VPCMPDZrmi + 72U, // VPCMPDZrmi_alt + 21871U, // VPCMPDZrmib + 18637U, // VPCMPDZrmib_alt + 29999U, // VPCMPDZrmibk + 26837U, // VPCMPDZrmibk_alt + 2U, // VPCMPDZrmik + 1156U, // VPCMPDZrmik_alt + 18636U, // VPCMPDZrri + 18636U, // VPCMPDZrri_alt + 26837U, // VPCMPDZrrik + 26837U, // VPCMPDZrrik_alt + 4U, // VPCMPEQBYrm + 4U, // VPCMPEQBYrr + 4U, // VPCMPEQBZ128rm + 1156U, // VPCMPEQBZ128rmk + 4U, // VPCMPEQBZ128rr + 1156U, // VPCMPEQBZ128rrk + 4U, // VPCMPEQBZ256rm + 1156U, // VPCMPEQBZ256rmk + 4U, // VPCMPEQBZ256rr + 1156U, // VPCMPEQBZ256rrk + 4U, // VPCMPEQBZrm + 1156U, // VPCMPEQBZrmk + 4U, // VPCMPEQBZrr + 1156U, // VPCMPEQBZrrk + 4U, // VPCMPEQBrm + 4U, // VPCMPEQBrr + 4U, // VPCMPEQDYrm + 4U, // VPCMPEQDYrr + 4U, // VPCMPEQDZ128rm + 72U, // VPCMPEQDZ128rmb + 1156U, // VPCMPEQDZ128rmbk + 1156U, // VPCMPEQDZ128rmk + 4U, // VPCMPEQDZ128rr + 1156U, // VPCMPEQDZ128rrk + 4U, // VPCMPEQDZ256rm + 72U, // VPCMPEQDZ256rmb + 1156U, // VPCMPEQDZ256rmbk + 1156U, // VPCMPEQDZ256rmk + 4U, // VPCMPEQDZ256rr + 1156U, // VPCMPEQDZ256rrk + 4U, // VPCMPEQDZrm + 72U, // VPCMPEQDZrmb + 1156U, // VPCMPEQDZrmbk + 1156U, // VPCMPEQDZrmk + 4U, // VPCMPEQDZrr + 1156U, // VPCMPEQDZrrk + 4U, // VPCMPEQDrm + 4U, // VPCMPEQDrr + 4U, // VPCMPEQQYrm + 4U, // VPCMPEQQYrr + 4U, // VPCMPEQQZ128rm + 72U, // VPCMPEQQZ128rmb + 1156U, // VPCMPEQQZ128rmbk + 1156U, // VPCMPEQQZ128rmk + 4U, // VPCMPEQQZ128rr + 1156U, // VPCMPEQQZ128rrk + 4U, // VPCMPEQQZ256rm + 72U, // VPCMPEQQZ256rmb + 1156U, // VPCMPEQQZ256rmbk + 1156U, // VPCMPEQQZ256rmk + 4U, // VPCMPEQQZ256rr + 1156U, // VPCMPEQQZ256rrk + 4U, // VPCMPEQQZrm + 72U, // VPCMPEQQZrmb + 1156U, // VPCMPEQQZrmbk + 1156U, // VPCMPEQQZrmk + 4U, // VPCMPEQQZrr + 1156U, // VPCMPEQQZrrk + 4U, // VPCMPEQQrm + 4U, // VPCMPEQQrr + 4U, // VPCMPEQWYrm + 4U, // VPCMPEQWYrr + 4U, // VPCMPEQWZ128rm + 1156U, // VPCMPEQWZ128rmk + 4U, // VPCMPEQWZ128rr + 1156U, // VPCMPEQWZ128rrk + 4U, // VPCMPEQWZ256rm + 1156U, // VPCMPEQWZ256rmk + 4U, // VPCMPEQWZ256rr + 1156U, // VPCMPEQWZ256rrk + 4U, // VPCMPEQWZrm + 1156U, // VPCMPEQWZrmk + 4U, // VPCMPEQWZrr + 1156U, // VPCMPEQWZrrk + 4U, // VPCMPEQWrm + 4U, // VPCMPEQWrr + 4U, // VPCMPESTRIrm + 72U, // VPCMPESTRIrr + 4U, // VPCMPESTRMrm + 72U, // VPCMPESTRMrr + 4U, // VPCMPGTBYrm + 4U, // VPCMPGTBYrr + 4U, // VPCMPGTBZ128rm + 1156U, // VPCMPGTBZ128rmk + 4U, // VPCMPGTBZ128rr + 1156U, // VPCMPGTBZ128rrk + 4U, // VPCMPGTBZ256rm + 1156U, // VPCMPGTBZ256rmk + 4U, // VPCMPGTBZ256rr + 1156U, // VPCMPGTBZ256rrk + 4U, // VPCMPGTBZrm + 1156U, // VPCMPGTBZrmk + 4U, // VPCMPGTBZrr + 1156U, // VPCMPGTBZrrk + 4U, // VPCMPGTBrm + 4U, // VPCMPGTBrr + 4U, // VPCMPGTDYrm + 4U, // VPCMPGTDYrr + 4U, // VPCMPGTDZ128rm + 72U, // VPCMPGTDZ128rmb + 1156U, // VPCMPGTDZ128rmbk + 1156U, // VPCMPGTDZ128rmk + 4U, // VPCMPGTDZ128rr + 1156U, // VPCMPGTDZ128rrk + 4U, // VPCMPGTDZ256rm + 72U, // VPCMPGTDZ256rmb + 1156U, // VPCMPGTDZ256rmbk + 1156U, // VPCMPGTDZ256rmk + 4U, // VPCMPGTDZ256rr + 1156U, // VPCMPGTDZ256rrk + 4U, // VPCMPGTDZrm + 72U, // VPCMPGTDZrmb + 1156U, // VPCMPGTDZrmbk + 1156U, // VPCMPGTDZrmk + 4U, // VPCMPGTDZrr + 1156U, // VPCMPGTDZrrk + 4U, // VPCMPGTDrm + 4U, // VPCMPGTDrr + 4U, // VPCMPGTQYrm + 4U, // VPCMPGTQYrr + 4U, // VPCMPGTQZ128rm + 72U, // VPCMPGTQZ128rmb + 1156U, // VPCMPGTQZ128rmbk + 1156U, // VPCMPGTQZ128rmk + 4U, // VPCMPGTQZ128rr + 1156U, // VPCMPGTQZ128rrk + 4U, // VPCMPGTQZ256rm + 72U, // VPCMPGTQZ256rmb + 1156U, // VPCMPGTQZ256rmbk + 1156U, // VPCMPGTQZ256rmk + 4U, // VPCMPGTQZ256rr + 1156U, // VPCMPGTQZ256rrk + 4U, // VPCMPGTQZrm + 72U, // VPCMPGTQZrmb + 1156U, // VPCMPGTQZrmbk + 1156U, // VPCMPGTQZrmk + 4U, // VPCMPGTQZrr + 1156U, // VPCMPGTQZrrk + 4U, // VPCMPGTQrm + 4U, // VPCMPGTQrr + 4U, // VPCMPGTWYrm + 4U, // VPCMPGTWYrr + 4U, // VPCMPGTWZ128rm + 1156U, // VPCMPGTWZ128rmk + 4U, // VPCMPGTWZ128rr + 1156U, // VPCMPGTWZ128rrk + 4U, // VPCMPGTWZ256rm + 1156U, // VPCMPGTWZ256rmk + 4U, // VPCMPGTWZ256rr + 1156U, // VPCMPGTWZ256rrk + 4U, // VPCMPGTWZrm + 1156U, // VPCMPGTWZrmk + 4U, // VPCMPGTWZrr + 1156U, // VPCMPGTWZrrk + 4U, // VPCMPGTWrm + 4U, // VPCMPGTWrr + 4U, // VPCMPISTRIrm + 72U, // VPCMPISTRIrr + 4U, // VPCMPISTRMrm + 72U, // VPCMPISTRMrr + 2U, // VPCMPQZ128rmi + 72U, // VPCMPQZ128rmi_alt + 21859U, // VPCMPQZ128rmib + 18637U, // VPCMPQZ128rmib_alt + 29987U, // VPCMPQZ128rmibk + 26837U, // VPCMPQZ128rmibk_alt + 2U, // VPCMPQZ128rmik + 1156U, // VPCMPQZ128rmik_alt + 18636U, // VPCMPQZ128rri + 18636U, // VPCMPQZ128rri_alt + 26837U, // VPCMPQZ128rrik + 26837U, // VPCMPQZ128rrik_alt + 2U, // VPCMPQZ256rmi + 72U, // VPCMPQZ256rmi_alt + 21863U, // VPCMPQZ256rmib + 18637U, // VPCMPQZ256rmib_alt + 29991U, // VPCMPQZ256rmibk + 26837U, // VPCMPQZ256rmibk_alt + 2U, // VPCMPQZ256rmik + 1156U, // VPCMPQZ256rmik_alt + 18636U, // VPCMPQZ256rri + 18636U, // VPCMPQZ256rri_alt + 26837U, // VPCMPQZ256rrik + 26837U, // VPCMPQZ256rrik_alt + 2U, // VPCMPQZrmi + 72U, // VPCMPQZrmi_alt + 21867U, // VPCMPQZrmib + 18637U, // VPCMPQZrmib_alt + 29995U, // VPCMPQZrmibk + 26837U, // VPCMPQZrmibk_alt + 2U, // VPCMPQZrmik + 1156U, // VPCMPQZrmik_alt + 18636U, // VPCMPQZrri + 18636U, // VPCMPQZrri_alt + 26837U, // VPCMPQZrrik + 26837U, // VPCMPQZrrik_alt + 2U, // VPCMPUBZ128rmi + 72U, // VPCMPUBZ128rmi_alt + 2U, // VPCMPUBZ128rmik + 1156U, // VPCMPUBZ128rmik_alt + 18636U, // VPCMPUBZ128rri + 18636U, // VPCMPUBZ128rri_alt + 26837U, // VPCMPUBZ128rrik + 26837U, // VPCMPUBZ128rrik_alt + 2U, // VPCMPUBZ256rmi + 72U, // VPCMPUBZ256rmi_alt + 2U, // VPCMPUBZ256rmik + 1156U, // VPCMPUBZ256rmik_alt + 18636U, // VPCMPUBZ256rri + 18636U, // VPCMPUBZ256rri_alt + 26837U, // VPCMPUBZ256rrik + 26837U, // VPCMPUBZ256rrik_alt + 2U, // VPCMPUBZrmi + 72U, // VPCMPUBZrmi_alt + 2U, // VPCMPUBZrmik + 1156U, // VPCMPUBZrmik_alt + 18636U, // VPCMPUBZrri + 18636U, // VPCMPUBZrri_alt + 26837U, // VPCMPUBZrrik + 26837U, // VPCMPUBZrrik_alt + 2U, // VPCMPUDZ128rmi + 72U, // VPCMPUDZ128rmi_alt + 21863U, // VPCMPUDZ128rmib + 18637U, // VPCMPUDZ128rmib_alt + 29991U, // VPCMPUDZ128rmibk + 26837U, // VPCMPUDZ128rmibk_alt + 2U, // VPCMPUDZ128rmik + 1156U, // VPCMPUDZ128rmik_alt + 18636U, // VPCMPUDZ128rri + 18636U, // VPCMPUDZ128rri_alt + 26837U, // VPCMPUDZ128rrik + 26837U, // VPCMPUDZ128rrik_alt + 2U, // VPCMPUDZ256rmi + 72U, // VPCMPUDZ256rmi_alt + 21867U, // VPCMPUDZ256rmib + 18637U, // VPCMPUDZ256rmib_alt + 29995U, // VPCMPUDZ256rmibk + 26837U, // VPCMPUDZ256rmibk_alt + 2U, // VPCMPUDZ256rmik + 1156U, // VPCMPUDZ256rmik_alt + 18636U, // VPCMPUDZ256rri + 18636U, // VPCMPUDZ256rri_alt + 26837U, // VPCMPUDZ256rrik + 26837U, // VPCMPUDZ256rrik_alt + 2U, // VPCMPUDZrmi + 72U, // VPCMPUDZrmi_alt + 21871U, // VPCMPUDZrmib + 18637U, // VPCMPUDZrmib_alt + 29999U, // VPCMPUDZrmibk + 26837U, // VPCMPUDZrmibk_alt + 2U, // VPCMPUDZrmik + 1156U, // VPCMPUDZrmik_alt + 18636U, // VPCMPUDZrri + 18636U, // VPCMPUDZrri_alt + 26837U, // VPCMPUDZrrik + 26837U, // VPCMPUDZrrik_alt + 2U, // VPCMPUQZ128rmi + 72U, // VPCMPUQZ128rmi_alt + 21859U, // VPCMPUQZ128rmib + 18637U, // VPCMPUQZ128rmib_alt + 29987U, // VPCMPUQZ128rmibk + 26837U, // VPCMPUQZ128rmibk_alt + 2U, // VPCMPUQZ128rmik + 1156U, // VPCMPUQZ128rmik_alt + 18636U, // VPCMPUQZ128rri + 18636U, // VPCMPUQZ128rri_alt + 26837U, // VPCMPUQZ128rrik + 26837U, // VPCMPUQZ128rrik_alt + 2U, // VPCMPUQZ256rmi + 72U, // VPCMPUQZ256rmi_alt + 21863U, // VPCMPUQZ256rmib + 18637U, // VPCMPUQZ256rmib_alt + 29991U, // VPCMPUQZ256rmibk + 26837U, // VPCMPUQZ256rmibk_alt + 2U, // VPCMPUQZ256rmik + 1156U, // VPCMPUQZ256rmik_alt + 18636U, // VPCMPUQZ256rri + 18636U, // VPCMPUQZ256rri_alt + 26837U, // VPCMPUQZ256rrik + 26837U, // VPCMPUQZ256rrik_alt + 2U, // VPCMPUQZrmi + 72U, // VPCMPUQZrmi_alt + 21867U, // VPCMPUQZrmib + 18637U, // VPCMPUQZrmib_alt + 29995U, // VPCMPUQZrmibk + 26837U, // VPCMPUQZrmibk_alt + 2U, // VPCMPUQZrmik + 1156U, // VPCMPUQZrmik_alt + 18636U, // VPCMPUQZrri + 18636U, // VPCMPUQZrri_alt + 26837U, // VPCMPUQZrrik + 26837U, // VPCMPUQZrrik_alt + 2U, // VPCMPUWZ128rmi + 72U, // VPCMPUWZ128rmi_alt + 2U, // VPCMPUWZ128rmik + 1156U, // VPCMPUWZ128rmik_alt + 18636U, // VPCMPUWZ128rri + 18636U, // VPCMPUWZ128rri_alt + 26837U, // VPCMPUWZ128rrik + 26837U, // VPCMPUWZ128rrik_alt + 2U, // VPCMPUWZ256rmi + 72U, // VPCMPUWZ256rmi_alt + 2U, // VPCMPUWZ256rmik + 1156U, // VPCMPUWZ256rmik_alt + 18636U, // VPCMPUWZ256rri + 18636U, // VPCMPUWZ256rri_alt + 26837U, // VPCMPUWZ256rrik + 26837U, // VPCMPUWZ256rrik_alt + 2U, // VPCMPUWZrmi + 72U, // VPCMPUWZrmi_alt + 2U, // VPCMPUWZrmik + 1156U, // VPCMPUWZrmik_alt + 18636U, // VPCMPUWZrri + 18636U, // VPCMPUWZrri_alt + 26837U, // VPCMPUWZrrik + 26837U, // VPCMPUWZrrik_alt + 2U, // VPCMPWZ128rmi + 72U, // VPCMPWZ128rmi_alt + 2U, // VPCMPWZ128rmik + 1156U, // VPCMPWZ128rmik_alt + 18636U, // VPCMPWZ128rri + 18636U, // VPCMPWZ128rri_alt + 26837U, // VPCMPWZ128rrik + 26837U, // VPCMPWZ128rrik_alt + 2U, // VPCMPWZ256rmi + 72U, // VPCMPWZ256rmi_alt + 2U, // VPCMPWZ256rmik + 1156U, // VPCMPWZ256rmik_alt + 18636U, // VPCMPWZ256rri + 18636U, // VPCMPWZ256rri_alt + 26837U, // VPCMPWZ256rrik + 26837U, // VPCMPWZ256rrik_alt + 2U, // VPCMPWZrmi + 72U, // VPCMPWZrmi_alt + 2U, // VPCMPWZrmik + 1156U, // VPCMPWZrmik_alt + 18636U, // VPCMPWZrri + 18636U, // VPCMPWZrri_alt + 26837U, // VPCMPWZrrik + 26837U, // VPCMPWZrrik_alt + 2U, // VPCOMBmi + 72U, // VPCOMBmi_alt + 18636U, // VPCOMBri + 18636U, // VPCOMBri_alt + 2U, // VPCOMDmi + 72U, // VPCOMDmi_alt + 18636U, // VPCOMDri + 18636U, // VPCOMDri_alt + 0U, // VPCOMPRESSBZ128mr + 49U, // VPCOMPRESSBZ128mrk + 0U, // VPCOMPRESSBZ128rr + 405U, // VPCOMPRESSBZ128rrk + 461U, // VPCOMPRESSBZ128rrkz + 0U, // VPCOMPRESSBZ256mr + 49U, // VPCOMPRESSBZ256mrk + 0U, // VPCOMPRESSBZ256rr + 405U, // VPCOMPRESSBZ256rrk + 461U, // VPCOMPRESSBZ256rrkz + 0U, // VPCOMPRESSBZmr + 49U, // VPCOMPRESSBZmrk + 0U, // VPCOMPRESSBZrr + 405U, // VPCOMPRESSBZrrk + 461U, // VPCOMPRESSBZrrkz + 0U, // VPCOMPRESSDZ128mr + 49U, // VPCOMPRESSDZ128mrk + 0U, // VPCOMPRESSDZ128rr + 405U, // VPCOMPRESSDZ128rrk + 461U, // VPCOMPRESSDZ128rrkz + 0U, // VPCOMPRESSDZ256mr + 49U, // VPCOMPRESSDZ256mrk + 0U, // VPCOMPRESSDZ256rr + 405U, // VPCOMPRESSDZ256rrk + 461U, // VPCOMPRESSDZ256rrkz + 0U, // VPCOMPRESSDZmr + 49U, // VPCOMPRESSDZmrk + 0U, // VPCOMPRESSDZrr + 405U, // VPCOMPRESSDZrrk + 461U, // VPCOMPRESSDZrrkz + 0U, // VPCOMPRESSQZ128mr + 49U, // VPCOMPRESSQZ128mrk + 0U, // VPCOMPRESSQZ128rr + 405U, // VPCOMPRESSQZ128rrk + 461U, // VPCOMPRESSQZ128rrkz + 0U, // VPCOMPRESSQZ256mr + 49U, // VPCOMPRESSQZ256mrk + 0U, // VPCOMPRESSQZ256rr + 405U, // VPCOMPRESSQZ256rrk + 461U, // VPCOMPRESSQZ256rrkz + 0U, // VPCOMPRESSQZmr + 49U, // VPCOMPRESSQZmrk + 0U, // VPCOMPRESSQZrr + 405U, // VPCOMPRESSQZrrk + 461U, // VPCOMPRESSQZrrkz + 0U, // VPCOMPRESSWZ128mr + 49U, // VPCOMPRESSWZ128mrk + 0U, // VPCOMPRESSWZ128rr + 405U, // VPCOMPRESSWZ128rrk + 461U, // VPCOMPRESSWZ128rrkz + 0U, // VPCOMPRESSWZ256mr + 49U, // VPCOMPRESSWZ256mrk + 0U, // VPCOMPRESSWZ256rr + 405U, // VPCOMPRESSWZ256rrk + 461U, // VPCOMPRESSWZ256rrkz + 0U, // VPCOMPRESSWZmr + 49U, // VPCOMPRESSWZmrk + 0U, // VPCOMPRESSWZrr + 405U, // VPCOMPRESSWZrrk + 461U, // VPCOMPRESSWZrrkz + 2U, // VPCOMQmi + 72U, // VPCOMQmi_alt + 18636U, // VPCOMQri + 18636U, // VPCOMQri_alt + 2U, // VPCOMUBmi + 72U, // VPCOMUBmi_alt + 18636U, // VPCOMUBri + 18636U, // VPCOMUBri_alt + 2U, // VPCOMUDmi + 72U, // VPCOMUDmi_alt + 18636U, // VPCOMUDri + 18636U, // VPCOMUDri_alt + 2U, // VPCOMUQmi + 72U, // VPCOMUQmi_alt + 18636U, // VPCOMUQri + 18636U, // VPCOMUQri_alt + 2U, // VPCOMUWmi + 72U, // VPCOMUWmi_alt + 18636U, // VPCOMUWri + 18636U, // VPCOMUWri_alt + 2U, // VPCOMWmi + 72U, // VPCOMWmi_alt + 18636U, // VPCOMWri + 18636U, // VPCOMWri_alt + 0U, // VPCONFLICTDZ128rm + 0U, // VPCONFLICTDZ128rmb + 3356U, // VPCONFLICTDZ128rmbk + 4444U, // VPCONFLICTDZ128rmbkz + 405U, // VPCONFLICTDZ128rmk + 461U, // VPCONFLICTDZ128rmkz + 0U, // VPCONFLICTDZ128rr + 405U, // VPCONFLICTDZ128rrk + 461U, // VPCONFLICTDZ128rrkz + 0U, // VPCONFLICTDZ256rm + 0U, // VPCONFLICTDZ256rmb + 3356U, // VPCONFLICTDZ256rmbk + 4444U, // VPCONFLICTDZ256rmbkz + 405U, // VPCONFLICTDZ256rmk + 461U, // VPCONFLICTDZ256rmkz + 0U, // VPCONFLICTDZ256rr + 405U, // VPCONFLICTDZ256rrk + 461U, // VPCONFLICTDZ256rrkz + 0U, // VPCONFLICTDZrm + 0U, // VPCONFLICTDZrmb + 3356U, // VPCONFLICTDZrmbk + 4444U, // VPCONFLICTDZrmbkz + 405U, // VPCONFLICTDZrmk + 461U, // VPCONFLICTDZrmkz + 0U, // VPCONFLICTDZrr + 405U, // VPCONFLICTDZrrk + 461U, // VPCONFLICTDZrrkz + 0U, // VPCONFLICTQZ128rm + 0U, // VPCONFLICTQZ128rmb + 3356U, // VPCONFLICTQZ128rmbk + 4444U, // VPCONFLICTQZ128rmbkz + 405U, // VPCONFLICTQZ128rmk + 461U, // VPCONFLICTQZ128rmkz + 0U, // VPCONFLICTQZ128rr + 405U, // VPCONFLICTQZ128rrk + 461U, // VPCONFLICTQZ128rrkz + 0U, // VPCONFLICTQZ256rm + 0U, // VPCONFLICTQZ256rmb + 3356U, // VPCONFLICTQZ256rmbk + 4444U, // VPCONFLICTQZ256rmbkz + 405U, // VPCONFLICTQZ256rmk + 461U, // VPCONFLICTQZ256rmkz + 0U, // VPCONFLICTQZ256rr + 405U, // VPCONFLICTQZ256rrk + 461U, // VPCONFLICTQZ256rrkz + 0U, // VPCONFLICTQZrm + 0U, // VPCONFLICTQZrmb + 3356U, // VPCONFLICTQZrmbk + 4444U, // VPCONFLICTQZrmbkz + 405U, // VPCONFLICTQZrmk + 461U, // VPCONFLICTQZrmkz + 0U, // VPCONFLICTQZrr + 405U, // VPCONFLICTQZrrk + 461U, // VPCONFLICTQZrrkz + 4U, // VPDPBUSDSZ128m + 4U, // VPDPBUSDSZ128mb + 133U, // VPDPBUSDSZ128mbk + 8325U, // VPDPBUSDSZ128mbkz + 132U, // VPDPBUSDSZ128mk + 8324U, // VPDPBUSDSZ128mkz + 4U, // VPDPBUSDSZ128r + 0U, // VPDPBUSDSZ128rk + 0U, // VPDPBUSDSZ128rkz + 4U, // VPDPBUSDSZ256m + 4U, // VPDPBUSDSZ256mb + 133U, // VPDPBUSDSZ256mbk + 8325U, // VPDPBUSDSZ256mbkz + 132U, // VPDPBUSDSZ256mk + 8324U, // VPDPBUSDSZ256mkz + 4U, // VPDPBUSDSZ256r + 0U, // VPDPBUSDSZ256rk + 0U, // VPDPBUSDSZ256rkz + 4U, // VPDPBUSDSZm + 4U, // VPDPBUSDSZmb + 133U, // VPDPBUSDSZmbk + 8325U, // VPDPBUSDSZmbkz + 132U, // VPDPBUSDSZmk + 8324U, // VPDPBUSDSZmkz + 4U, // VPDPBUSDSZr + 0U, // VPDPBUSDSZrk + 0U, // VPDPBUSDSZrkz + 4U, // VPDPBUSDZ128m + 4U, // VPDPBUSDZ128mb + 133U, // VPDPBUSDZ128mbk + 8325U, // VPDPBUSDZ128mbkz + 132U, // VPDPBUSDZ128mk + 8324U, // VPDPBUSDZ128mkz + 4U, // VPDPBUSDZ128r + 0U, // VPDPBUSDZ128rk + 0U, // VPDPBUSDZ128rkz + 4U, // VPDPBUSDZ256m + 4U, // VPDPBUSDZ256mb + 133U, // VPDPBUSDZ256mbk + 8325U, // VPDPBUSDZ256mbkz + 132U, // VPDPBUSDZ256mk + 8324U, // VPDPBUSDZ256mkz + 4U, // VPDPBUSDZ256r + 0U, // VPDPBUSDZ256rk + 0U, // VPDPBUSDZ256rkz + 4U, // VPDPBUSDZm + 4U, // VPDPBUSDZmb + 133U, // VPDPBUSDZmbk + 8325U, // VPDPBUSDZmbkz + 132U, // VPDPBUSDZmk + 8324U, // VPDPBUSDZmkz + 4U, // VPDPBUSDZr + 0U, // VPDPBUSDZrk + 0U, // VPDPBUSDZrkz + 4U, // VPDPWSSDSZ128m + 4U, // VPDPWSSDSZ128mb + 133U, // VPDPWSSDSZ128mbk + 8325U, // VPDPWSSDSZ128mbkz + 132U, // VPDPWSSDSZ128mk + 8324U, // VPDPWSSDSZ128mkz + 4U, // VPDPWSSDSZ128r + 0U, // VPDPWSSDSZ128rk + 0U, // VPDPWSSDSZ128rkz + 4U, // VPDPWSSDSZ256m + 4U, // VPDPWSSDSZ256mb + 133U, // VPDPWSSDSZ256mbk + 8325U, // VPDPWSSDSZ256mbkz + 132U, // VPDPWSSDSZ256mk + 8324U, // VPDPWSSDSZ256mkz + 4U, // VPDPWSSDSZ256r + 0U, // VPDPWSSDSZ256rk + 0U, // VPDPWSSDSZ256rkz + 4U, // VPDPWSSDSZm + 4U, // VPDPWSSDSZmb + 133U, // VPDPWSSDSZmbk + 8325U, // VPDPWSSDSZmbkz + 132U, // VPDPWSSDSZmk + 8324U, // VPDPWSSDSZmkz + 4U, // VPDPWSSDSZr + 0U, // VPDPWSSDSZrk + 0U, // VPDPWSSDSZrkz + 4U, // VPDPWSSDZ128m + 4U, // VPDPWSSDZ128mb + 133U, // VPDPWSSDZ128mbk + 8325U, // VPDPWSSDZ128mbkz + 132U, // VPDPWSSDZ128mk + 8324U, // VPDPWSSDZ128mkz + 4U, // VPDPWSSDZ128r + 0U, // VPDPWSSDZ128rk + 0U, // VPDPWSSDZ128rkz + 4U, // VPDPWSSDZ256m + 4U, // VPDPWSSDZ256mb + 133U, // VPDPWSSDZ256mbk + 8325U, // VPDPWSSDZ256mbkz + 132U, // VPDPWSSDZ256mk + 8324U, // VPDPWSSDZ256mkz + 4U, // VPDPWSSDZ256r + 0U, // VPDPWSSDZ256rk + 0U, // VPDPWSSDZ256rkz + 4U, // VPDPWSSDZm + 4U, // VPDPWSSDZmb + 133U, // VPDPWSSDZmbk + 8325U, // VPDPWSSDZmbkz + 132U, // VPDPWSSDZmk + 8324U, // VPDPWSSDZmkz + 4U, // VPDPWSSDZr + 0U, // VPDPWSSDZrk + 0U, // VPDPWSSDZrkz + 72U, // VPERM2F128rm + 18636U, // VPERM2F128rr + 72U, // VPERM2I128rm + 18636U, // VPERM2I128rr + 4U, // VPERMBZ128rm + 132U, // VPERMBZ128rmk + 9348U, // VPERMBZ128rmkz + 4U, // VPERMBZ128rr + 0U, // VPERMBZ128rrk + 9348U, // VPERMBZ128rrkz + 4U, // VPERMBZ256rm + 132U, // VPERMBZ256rmk + 9348U, // VPERMBZ256rmkz + 4U, // VPERMBZ256rr + 0U, // VPERMBZ256rrk + 9348U, // VPERMBZ256rrkz + 4U, // VPERMBZrm + 132U, // VPERMBZrmk + 9348U, // VPERMBZrmkz + 4U, // VPERMBZrr + 0U, // VPERMBZrrk + 9348U, // VPERMBZrrkz + 4U, // VPERMDYrm + 4U, // VPERMDYrr + 4U, // VPERMDZ256rm + 72U, // VPERMDZ256rmb + 133U, // VPERMDZ256rmbk + 9348U, // VPERMDZ256rmbkz + 132U, // VPERMDZ256rmk + 9348U, // VPERMDZ256rmkz + 4U, // VPERMDZ256rr + 0U, // VPERMDZ256rrk + 9348U, // VPERMDZ256rrkz + 4U, // VPERMDZrm + 72U, // VPERMDZrmb + 133U, // VPERMDZrmbk + 9348U, // VPERMDZrmbkz + 132U, // VPERMDZrmk + 9348U, // VPERMDZrmkz + 4U, // VPERMDZrr + 0U, // VPERMDZrrk + 9348U, // VPERMDZrrkz + 4U, // VPERMI2B128rm + 132U, // VPERMI2B128rmk + 8324U, // VPERMI2B128rmkz + 4U, // VPERMI2B128rr + 0U, // VPERMI2B128rrk + 0U, // VPERMI2B128rrkz + 4U, // VPERMI2B256rm + 132U, // VPERMI2B256rmk + 8324U, // VPERMI2B256rmkz + 4U, // VPERMI2B256rr + 0U, // VPERMI2B256rrk + 0U, // VPERMI2B256rrkz + 4U, // VPERMI2Brm + 132U, // VPERMI2Brmk + 8324U, // VPERMI2Brmkz + 4U, // VPERMI2Brr + 0U, // VPERMI2Brrk + 0U, // VPERMI2Brrkz + 4U, // VPERMI2D128rm + 4U, // VPERMI2D128rmb + 133U, // VPERMI2D128rmbk + 8325U, // VPERMI2D128rmbkz + 132U, // VPERMI2D128rmk + 8324U, // VPERMI2D128rmkz + 4U, // VPERMI2D128rr + 0U, // VPERMI2D128rrk + 0U, // VPERMI2D128rrkz + 4U, // VPERMI2D256rm + 4U, // VPERMI2D256rmb + 133U, // VPERMI2D256rmbk + 8325U, // VPERMI2D256rmbkz + 132U, // VPERMI2D256rmk + 8324U, // VPERMI2D256rmkz + 4U, // VPERMI2D256rr + 0U, // VPERMI2D256rrk + 0U, // VPERMI2D256rrkz + 4U, // VPERMI2Drm + 4U, // VPERMI2Drmb + 133U, // VPERMI2Drmbk + 8325U, // VPERMI2Drmbkz + 132U, // VPERMI2Drmk + 8324U, // VPERMI2Drmkz + 4U, // VPERMI2Drr + 0U, // VPERMI2Drrk + 0U, // VPERMI2Drrkz + 4U, // VPERMI2PD128rm + 4U, // VPERMI2PD128rmb + 133U, // VPERMI2PD128rmbk + 8325U, // VPERMI2PD128rmbkz + 0U, // VPERMI2PD128rmk + 0U, // VPERMI2PD128rmkz + 4U, // VPERMI2PD128rr + 0U, // VPERMI2PD128rrk + 0U, // VPERMI2PD128rrkz + 4U, // VPERMI2PD256rm + 4U, // VPERMI2PD256rmb + 133U, // VPERMI2PD256rmbk + 8325U, // VPERMI2PD256rmbkz + 0U, // VPERMI2PD256rmk + 0U, // VPERMI2PD256rmkz + 4U, // VPERMI2PD256rr + 0U, // VPERMI2PD256rrk + 0U, // VPERMI2PD256rrkz + 4U, // VPERMI2PDrm + 4U, // VPERMI2PDrmb + 133U, // VPERMI2PDrmbk + 8325U, // VPERMI2PDrmbkz + 0U, // VPERMI2PDrmk + 0U, // VPERMI2PDrmkz + 4U, // VPERMI2PDrr + 0U, // VPERMI2PDrrk + 0U, // VPERMI2PDrrkz + 4U, // VPERMI2PS128rm + 4U, // VPERMI2PS128rmb + 133U, // VPERMI2PS128rmbk + 8325U, // VPERMI2PS128rmbkz + 0U, // VPERMI2PS128rmk + 0U, // VPERMI2PS128rmkz + 4U, // VPERMI2PS128rr + 0U, // VPERMI2PS128rrk + 0U, // VPERMI2PS128rrkz + 4U, // VPERMI2PS256rm + 4U, // VPERMI2PS256rmb + 133U, // VPERMI2PS256rmbk + 8325U, // VPERMI2PS256rmbkz + 0U, // VPERMI2PS256rmk + 0U, // VPERMI2PS256rmkz + 4U, // VPERMI2PS256rr + 0U, // VPERMI2PS256rrk + 0U, // VPERMI2PS256rrkz + 4U, // VPERMI2PSrm + 4U, // VPERMI2PSrmb + 133U, // VPERMI2PSrmbk + 8325U, // VPERMI2PSrmbkz + 0U, // VPERMI2PSrmk + 0U, // VPERMI2PSrmkz + 4U, // VPERMI2PSrr + 0U, // VPERMI2PSrrk + 0U, // VPERMI2PSrrkz + 4U, // VPERMI2Q128rm + 4U, // VPERMI2Q128rmb + 133U, // VPERMI2Q128rmbk + 8325U, // VPERMI2Q128rmbkz + 132U, // VPERMI2Q128rmk + 8324U, // VPERMI2Q128rmkz + 4U, // VPERMI2Q128rr + 0U, // VPERMI2Q128rrk + 0U, // VPERMI2Q128rrkz + 4U, // VPERMI2Q256rm + 4U, // VPERMI2Q256rmb + 133U, // VPERMI2Q256rmbk + 8325U, // VPERMI2Q256rmbkz + 132U, // VPERMI2Q256rmk + 8324U, // VPERMI2Q256rmkz + 4U, // VPERMI2Q256rr + 0U, // VPERMI2Q256rrk + 0U, // VPERMI2Q256rrkz + 4U, // VPERMI2Qrm + 4U, // VPERMI2Qrmb + 133U, // VPERMI2Qrmbk + 8325U, // VPERMI2Qrmbkz + 132U, // VPERMI2Qrmk + 8324U, // VPERMI2Qrmkz + 4U, // VPERMI2Qrr + 0U, // VPERMI2Qrrk + 0U, // VPERMI2Qrrkz + 4U, // VPERMI2W128rm + 132U, // VPERMI2W128rmk + 8324U, // VPERMI2W128rmkz + 4U, // VPERMI2W128rr + 0U, // VPERMI2W128rrk + 0U, // VPERMI2W128rrkz + 4U, // VPERMI2W256rm + 132U, // VPERMI2W256rmk + 8324U, // VPERMI2W256rmkz + 4U, // VPERMI2W256rr + 0U, // VPERMI2W256rrk + 0U, // VPERMI2W256rrkz + 4U, // VPERMI2Wrm + 132U, // VPERMI2Wrmk + 8324U, // VPERMI2Wrmkz + 4U, // VPERMI2Wrr + 0U, // VPERMI2Wrrk + 0U, // VPERMI2Wrrkz + 1U, // VPERMIL2PDYmr + 18636U, // VPERMIL2PDYrm + 34005U, // VPERMIL2PDYrr + 34005U, // VPERMIL2PDYrr_REV + 18636U, // VPERMIL2PDmr + 18636U, // VPERMIL2PDrm + 34005U, // VPERMIL2PDrr + 34005U, // VPERMIL2PDrr_REV + 1U, // VPERMIL2PSYmr + 18636U, // VPERMIL2PSYrm + 34005U, // VPERMIL2PSYrr + 34005U, // VPERMIL2PSYrr_REV + 18636U, // VPERMIL2PSmr + 18636U, // VPERMIL2PSrm + 34005U, // VPERMIL2PSrr + 34005U, // VPERMIL2PSrr_REV + 0U, // VPERMILPDYmi + 72U, // VPERMILPDYri + 4U, // VPERMILPDYrm + 4U, // VPERMILPDYrr + 5U, // VPERMILPDZ128mbi + 133U, // VPERMILPDZ128mbik + 9349U, // VPERMILPDZ128mbikz + 0U, // VPERMILPDZ128mi + 3356U, // VPERMILPDZ128mik + 4444U, // VPERMILPDZ128mikz + 72U, // VPERMILPDZ128ri + 133U, // VPERMILPDZ128rik + 9348U, // VPERMILPDZ128rikz + 4U, // VPERMILPDZ128rm + 72U, // VPERMILPDZ128rmb + 133U, // VPERMILPDZ128rmbk + 9348U, // VPERMILPDZ128rmbkz + 132U, // VPERMILPDZ128rmk + 9348U, // VPERMILPDZ128rmkz + 4U, // VPERMILPDZ128rr + 0U, // VPERMILPDZ128rrk + 9348U, // VPERMILPDZ128rrkz + 5U, // VPERMILPDZ256mbi + 133U, // VPERMILPDZ256mbik + 9349U, // VPERMILPDZ256mbikz + 0U, // VPERMILPDZ256mi + 3356U, // VPERMILPDZ256mik + 4444U, // VPERMILPDZ256mikz + 72U, // VPERMILPDZ256ri + 133U, // VPERMILPDZ256rik + 9348U, // VPERMILPDZ256rikz + 4U, // VPERMILPDZ256rm + 72U, // VPERMILPDZ256rmb + 133U, // VPERMILPDZ256rmbk + 9348U, // VPERMILPDZ256rmbkz + 132U, // VPERMILPDZ256rmk + 9348U, // VPERMILPDZ256rmkz + 4U, // VPERMILPDZ256rr + 0U, // VPERMILPDZ256rrk + 9348U, // VPERMILPDZ256rrkz + 5U, // VPERMILPDZmbi + 133U, // VPERMILPDZmbik + 9349U, // VPERMILPDZmbikz + 0U, // VPERMILPDZmi + 3356U, // VPERMILPDZmik + 4444U, // VPERMILPDZmikz + 72U, // VPERMILPDZri + 133U, // VPERMILPDZrik + 9348U, // VPERMILPDZrikz + 4U, // VPERMILPDZrm + 72U, // VPERMILPDZrmb + 133U, // VPERMILPDZrmbk + 9348U, // VPERMILPDZrmbkz + 132U, // VPERMILPDZrmk + 9348U, // VPERMILPDZrmkz + 4U, // VPERMILPDZrr + 0U, // VPERMILPDZrrk + 9348U, // VPERMILPDZrrkz + 0U, // VPERMILPDmi + 72U, // VPERMILPDri + 4U, // VPERMILPDrm + 4U, // VPERMILPDrr + 0U, // VPERMILPSYmi + 72U, // VPERMILPSYri + 4U, // VPERMILPSYrm + 4U, // VPERMILPSYrr + 5U, // VPERMILPSZ128mbi + 133U, // VPERMILPSZ128mbik + 9349U, // VPERMILPSZ128mbikz + 0U, // VPERMILPSZ128mi + 3356U, // VPERMILPSZ128mik + 4444U, // VPERMILPSZ128mikz + 72U, // VPERMILPSZ128ri + 133U, // VPERMILPSZ128rik + 9348U, // VPERMILPSZ128rikz + 4U, // VPERMILPSZ128rm + 72U, // VPERMILPSZ128rmb + 133U, // VPERMILPSZ128rmbk + 9348U, // VPERMILPSZ128rmbkz + 132U, // VPERMILPSZ128rmk + 9348U, // VPERMILPSZ128rmkz + 4U, // VPERMILPSZ128rr + 0U, // VPERMILPSZ128rrk + 9348U, // VPERMILPSZ128rrkz + 5U, // VPERMILPSZ256mbi + 133U, // VPERMILPSZ256mbik + 9349U, // VPERMILPSZ256mbikz + 0U, // VPERMILPSZ256mi + 3356U, // VPERMILPSZ256mik + 4444U, // VPERMILPSZ256mikz + 72U, // VPERMILPSZ256ri + 133U, // VPERMILPSZ256rik + 9348U, // VPERMILPSZ256rikz + 4U, // VPERMILPSZ256rm + 72U, // VPERMILPSZ256rmb + 133U, // VPERMILPSZ256rmbk + 9348U, // VPERMILPSZ256rmbkz + 132U, // VPERMILPSZ256rmk + 9348U, // VPERMILPSZ256rmkz + 4U, // VPERMILPSZ256rr + 0U, // VPERMILPSZ256rrk + 9348U, // VPERMILPSZ256rrkz + 5U, // VPERMILPSZmbi + 133U, // VPERMILPSZmbik + 9349U, // VPERMILPSZmbikz + 0U, // VPERMILPSZmi + 3356U, // VPERMILPSZmik + 4444U, // VPERMILPSZmikz + 72U, // VPERMILPSZri + 133U, // VPERMILPSZrik + 9348U, // VPERMILPSZrikz + 4U, // VPERMILPSZrm + 72U, // VPERMILPSZrmb + 133U, // VPERMILPSZrmbk + 9348U, // VPERMILPSZrmbkz + 132U, // VPERMILPSZrmk + 9348U, // VPERMILPSZrmkz + 4U, // VPERMILPSZrr + 0U, // VPERMILPSZrrk + 9348U, // VPERMILPSZrrkz + 0U, // VPERMILPSmi + 72U, // VPERMILPSri + 4U, // VPERMILPSrm + 4U, // VPERMILPSrr + 0U, // VPERMPDYmi + 72U, // VPERMPDYri + 5U, // VPERMPDZ256mbi + 133U, // VPERMPDZ256mbik + 9349U, // VPERMPDZ256mbikz + 0U, // VPERMPDZ256mi + 3356U, // VPERMPDZ256mik + 4444U, // VPERMPDZ256mikz + 72U, // VPERMPDZ256ri + 133U, // VPERMPDZ256rik + 9348U, // VPERMPDZ256rikz + 4U, // VPERMPDZ256rm + 72U, // VPERMPDZ256rmb + 133U, // VPERMPDZ256rmbk + 9348U, // VPERMPDZ256rmbkz + 0U, // VPERMPDZ256rmk + 9348U, // VPERMPDZ256rmkz + 4U, // VPERMPDZ256rr + 0U, // VPERMPDZ256rrk + 9348U, // VPERMPDZ256rrkz + 5U, // VPERMPDZmbi + 133U, // VPERMPDZmbik + 9349U, // VPERMPDZmbikz + 0U, // VPERMPDZmi + 3356U, // VPERMPDZmik + 4444U, // VPERMPDZmikz + 72U, // VPERMPDZri + 133U, // VPERMPDZrik + 9348U, // VPERMPDZrikz + 4U, // VPERMPDZrm + 72U, // VPERMPDZrmb + 133U, // VPERMPDZrmbk + 9348U, // VPERMPDZrmbkz + 0U, // VPERMPDZrmk + 9348U, // VPERMPDZrmkz + 4U, // VPERMPDZrr + 0U, // VPERMPDZrrk + 9348U, // VPERMPDZrrkz + 4U, // VPERMPSYrm + 4U, // VPERMPSYrr + 4U, // VPERMPSZ256rm + 72U, // VPERMPSZ256rmb + 133U, // VPERMPSZ256rmbk + 9348U, // VPERMPSZ256rmbkz + 0U, // VPERMPSZ256rmk + 9348U, // VPERMPSZ256rmkz + 4U, // VPERMPSZ256rr + 0U, // VPERMPSZ256rrk + 9348U, // VPERMPSZ256rrkz + 4U, // VPERMPSZrm + 72U, // VPERMPSZrmb + 133U, // VPERMPSZrmbk + 9348U, // VPERMPSZrmbkz + 0U, // VPERMPSZrmk + 9348U, // VPERMPSZrmkz + 4U, // VPERMPSZrr + 0U, // VPERMPSZrrk + 9348U, // VPERMPSZrrkz + 4U, // VPERMQYmi + 72U, // VPERMQYri + 5U, // VPERMQZ256mbi + 133U, // VPERMQZ256mbik + 9349U, // VPERMQZ256mbikz + 4U, // VPERMQZ256mi + 3356U, // VPERMQZ256mik + 4444U, // VPERMQZ256mikz + 72U, // VPERMQZ256ri + 133U, // VPERMQZ256rik + 9348U, // VPERMQZ256rikz + 4U, // VPERMQZ256rm + 72U, // VPERMQZ256rmb + 133U, // VPERMQZ256rmbk + 9348U, // VPERMQZ256rmbkz + 132U, // VPERMQZ256rmk + 9348U, // VPERMQZ256rmkz + 4U, // VPERMQZ256rr + 0U, // VPERMQZ256rrk + 9348U, // VPERMQZ256rrkz + 5U, // VPERMQZmbi + 133U, // VPERMQZmbik + 9349U, // VPERMQZmbikz + 4U, // VPERMQZmi + 3356U, // VPERMQZmik + 4444U, // VPERMQZmikz + 72U, // VPERMQZri + 133U, // VPERMQZrik + 9348U, // VPERMQZrikz + 4U, // VPERMQZrm + 72U, // VPERMQZrmb + 133U, // VPERMQZrmbk + 9348U, // VPERMQZrmbkz + 132U, // VPERMQZrmk + 9348U, // VPERMQZrmkz + 4U, // VPERMQZrr + 0U, // VPERMQZrrk + 9348U, // VPERMQZrrkz + 4U, // VPERMT2B128rm + 132U, // VPERMT2B128rmk + 8324U, // VPERMT2B128rmkz + 4U, // VPERMT2B128rr + 0U, // VPERMT2B128rrk + 0U, // VPERMT2B128rrkz + 4U, // VPERMT2B256rm + 132U, // VPERMT2B256rmk + 8324U, // VPERMT2B256rmkz + 4U, // VPERMT2B256rr + 0U, // VPERMT2B256rrk + 0U, // VPERMT2B256rrkz + 4U, // VPERMT2Brm + 132U, // VPERMT2Brmk + 8324U, // VPERMT2Brmkz + 4U, // VPERMT2Brr + 0U, // VPERMT2Brrk + 0U, // VPERMT2Brrkz + 4U, // VPERMT2D128rm + 4U, // VPERMT2D128rmb + 133U, // VPERMT2D128rmbk + 8325U, // VPERMT2D128rmbkz + 132U, // VPERMT2D128rmk + 8324U, // VPERMT2D128rmkz + 4U, // VPERMT2D128rr + 0U, // VPERMT2D128rrk + 0U, // VPERMT2D128rrkz + 4U, // VPERMT2D256rm + 4U, // VPERMT2D256rmb + 133U, // VPERMT2D256rmbk + 8325U, // VPERMT2D256rmbkz + 132U, // VPERMT2D256rmk + 8324U, // VPERMT2D256rmkz + 4U, // VPERMT2D256rr + 0U, // VPERMT2D256rrk + 0U, // VPERMT2D256rrkz + 4U, // VPERMT2Drm + 4U, // VPERMT2Drmb + 133U, // VPERMT2Drmbk + 8325U, // VPERMT2Drmbkz + 132U, // VPERMT2Drmk + 8324U, // VPERMT2Drmkz + 4U, // VPERMT2Drr + 0U, // VPERMT2Drrk + 0U, // VPERMT2Drrkz + 4U, // VPERMT2PD128rm + 4U, // VPERMT2PD128rmb + 133U, // VPERMT2PD128rmbk + 8325U, // VPERMT2PD128rmbkz + 0U, // VPERMT2PD128rmk + 0U, // VPERMT2PD128rmkz + 4U, // VPERMT2PD128rr + 0U, // VPERMT2PD128rrk + 0U, // VPERMT2PD128rrkz + 4U, // VPERMT2PD256rm + 4U, // VPERMT2PD256rmb + 133U, // VPERMT2PD256rmbk + 8325U, // VPERMT2PD256rmbkz + 0U, // VPERMT2PD256rmk + 0U, // VPERMT2PD256rmkz + 4U, // VPERMT2PD256rr + 0U, // VPERMT2PD256rrk + 0U, // VPERMT2PD256rrkz + 4U, // VPERMT2PDrm + 4U, // VPERMT2PDrmb + 133U, // VPERMT2PDrmbk + 8325U, // VPERMT2PDrmbkz + 0U, // VPERMT2PDrmk + 0U, // VPERMT2PDrmkz + 4U, // VPERMT2PDrr + 0U, // VPERMT2PDrrk + 0U, // VPERMT2PDrrkz + 4U, // VPERMT2PS128rm + 4U, // VPERMT2PS128rmb + 133U, // VPERMT2PS128rmbk + 8325U, // VPERMT2PS128rmbkz + 0U, // VPERMT2PS128rmk + 0U, // VPERMT2PS128rmkz + 4U, // VPERMT2PS128rr + 0U, // VPERMT2PS128rrk + 0U, // VPERMT2PS128rrkz + 4U, // VPERMT2PS256rm + 4U, // VPERMT2PS256rmb + 133U, // VPERMT2PS256rmbk + 8325U, // VPERMT2PS256rmbkz + 0U, // VPERMT2PS256rmk + 0U, // VPERMT2PS256rmkz + 4U, // VPERMT2PS256rr + 0U, // VPERMT2PS256rrk + 0U, // VPERMT2PS256rrkz + 4U, // VPERMT2PSrm + 4U, // VPERMT2PSrmb + 133U, // VPERMT2PSrmbk + 8325U, // VPERMT2PSrmbkz + 0U, // VPERMT2PSrmk + 0U, // VPERMT2PSrmkz + 4U, // VPERMT2PSrr + 0U, // VPERMT2PSrrk + 0U, // VPERMT2PSrrkz + 4U, // VPERMT2Q128rm + 4U, // VPERMT2Q128rmb + 133U, // VPERMT2Q128rmbk + 8325U, // VPERMT2Q128rmbkz + 132U, // VPERMT2Q128rmk + 8324U, // VPERMT2Q128rmkz + 4U, // VPERMT2Q128rr + 0U, // VPERMT2Q128rrk + 0U, // VPERMT2Q128rrkz + 4U, // VPERMT2Q256rm + 4U, // VPERMT2Q256rmb + 133U, // VPERMT2Q256rmbk + 8325U, // VPERMT2Q256rmbkz + 132U, // VPERMT2Q256rmk + 8324U, // VPERMT2Q256rmkz + 4U, // VPERMT2Q256rr + 0U, // VPERMT2Q256rrk + 0U, // VPERMT2Q256rrkz + 4U, // VPERMT2Qrm + 4U, // VPERMT2Qrmb + 133U, // VPERMT2Qrmbk + 8325U, // VPERMT2Qrmbkz + 132U, // VPERMT2Qrmk + 8324U, // VPERMT2Qrmkz + 4U, // VPERMT2Qrr + 0U, // VPERMT2Qrrk + 0U, // VPERMT2Qrrkz + 4U, // VPERMT2W128rm + 132U, // VPERMT2W128rmk + 8324U, // VPERMT2W128rmkz + 4U, // VPERMT2W128rr + 0U, // VPERMT2W128rrk + 0U, // VPERMT2W128rrkz + 4U, // VPERMT2W256rm + 132U, // VPERMT2W256rmk + 8324U, // VPERMT2W256rmkz + 4U, // VPERMT2W256rr + 0U, // VPERMT2W256rrk + 0U, // VPERMT2W256rrkz + 4U, // VPERMT2Wrm + 132U, // VPERMT2Wrmk + 8324U, // VPERMT2Wrmkz + 4U, // VPERMT2Wrr + 0U, // VPERMT2Wrrk + 0U, // VPERMT2Wrrkz + 4U, // VPERMWZ128rm + 132U, // VPERMWZ128rmk + 9348U, // VPERMWZ128rmkz + 4U, // VPERMWZ128rr + 0U, // VPERMWZ128rrk + 9348U, // VPERMWZ128rrkz + 4U, // VPERMWZ256rm + 132U, // VPERMWZ256rmk + 9348U, // VPERMWZ256rmkz + 4U, // VPERMWZ256rr + 0U, // VPERMWZ256rrk + 9348U, // VPERMWZ256rrkz + 4U, // VPERMWZrm + 132U, // VPERMWZrmk + 9348U, // VPERMWZrmkz + 4U, // VPERMWZrr + 0U, // VPERMWZrrk + 9348U, // VPERMWZrrkz + 0U, // VPEXPANDBZ128rm + 405U, // VPEXPANDBZ128rmk + 461U, // VPEXPANDBZ128rmkz + 0U, // VPEXPANDBZ128rr + 405U, // VPEXPANDBZ128rrk + 461U, // VPEXPANDBZ128rrkz + 0U, // VPEXPANDBZ256rm + 405U, // VPEXPANDBZ256rmk + 461U, // VPEXPANDBZ256rmkz + 0U, // VPEXPANDBZ256rr + 405U, // VPEXPANDBZ256rrk + 461U, // VPEXPANDBZ256rrkz + 0U, // VPEXPANDBZrm + 405U, // VPEXPANDBZrmk + 461U, // VPEXPANDBZrmkz + 0U, // VPEXPANDBZrr + 405U, // VPEXPANDBZrrk + 461U, // VPEXPANDBZrrkz + 0U, // VPEXPANDDZ128rm + 405U, // VPEXPANDDZ128rmk + 461U, // VPEXPANDDZ128rmkz + 0U, // VPEXPANDDZ128rr + 405U, // VPEXPANDDZ128rrk + 461U, // VPEXPANDDZ128rrkz + 0U, // VPEXPANDDZ256rm + 405U, // VPEXPANDDZ256rmk + 461U, // VPEXPANDDZ256rmkz + 0U, // VPEXPANDDZ256rr + 405U, // VPEXPANDDZ256rrk + 461U, // VPEXPANDDZ256rrkz + 0U, // VPEXPANDDZrm + 405U, // VPEXPANDDZrmk + 461U, // VPEXPANDDZrmkz + 0U, // VPEXPANDDZrr + 405U, // VPEXPANDDZrrk + 461U, // VPEXPANDDZrrkz + 0U, // VPEXPANDQZ128rm + 405U, // VPEXPANDQZ128rmk + 461U, // VPEXPANDQZ128rmkz + 0U, // VPEXPANDQZ128rr + 405U, // VPEXPANDQZ128rrk + 461U, // VPEXPANDQZ128rrkz + 0U, // VPEXPANDQZ256rm + 405U, // VPEXPANDQZ256rmk + 461U, // VPEXPANDQZ256rmkz + 0U, // VPEXPANDQZ256rr + 405U, // VPEXPANDQZ256rrk + 461U, // VPEXPANDQZ256rrkz + 0U, // VPEXPANDQZrm + 405U, // VPEXPANDQZrmk + 461U, // VPEXPANDQZrmkz + 0U, // VPEXPANDQZrr + 405U, // VPEXPANDQZrrk + 461U, // VPEXPANDQZrrkz + 0U, // VPEXPANDWZ128rm + 405U, // VPEXPANDWZ128rmk + 461U, // VPEXPANDWZ128rmkz + 0U, // VPEXPANDWZ128rr + 405U, // VPEXPANDWZ128rrk + 461U, // VPEXPANDWZ128rrkz + 0U, // VPEXPANDWZ256rm + 405U, // VPEXPANDWZ256rmk + 461U, // VPEXPANDWZ256rmkz + 0U, // VPEXPANDWZ256rr + 405U, // VPEXPANDWZ256rrk + 461U, // VPEXPANDWZ256rrkz + 0U, // VPEXPANDWZrm + 405U, // VPEXPANDWZrmk + 461U, // VPEXPANDWZrmkz + 0U, // VPEXPANDWZrr + 405U, // VPEXPANDWZrrk + 461U, // VPEXPANDWZrrkz + 1U, // VPEXTRBZmr + 72U, // VPEXTRBZrr + 1U, // VPEXTRBmr + 72U, // VPEXTRBrr + 1U, // VPEXTRDZmr + 72U, // VPEXTRDZrr + 1U, // VPEXTRDmr + 72U, // VPEXTRDrr + 1U, // VPEXTRQZmr + 72U, // VPEXTRQZrr + 1U, // VPEXTRQmr + 72U, // VPEXTRQrr + 1U, // VPEXTRWZmr + 72U, // VPEXTRWZrr + 72U, // VPEXTRWZrr_REV + 1U, // VPEXTRWmr + 72U, // VPEXTRWrr + 72U, // VPEXTRWrr_REV + 0U, // VPGATHERDDYrm + 401U, // VPGATHERDDZ128rm + 401U, // VPGATHERDDZ256rm + 401U, // VPGATHERDDZrm + 0U, // VPGATHERDDrm + 0U, // VPGATHERDQYrm + 401U, // VPGATHERDQZ128rm + 401U, // VPGATHERDQZ256rm + 401U, // VPGATHERDQZrm + 0U, // VPGATHERDQrm + 0U, // VPGATHERQDYrm + 604U, // VPGATHERQDZ128rm + 401U, // VPGATHERQDZ256rm + 401U, // VPGATHERQDZrm + 4U, // VPGATHERQDrm + 0U, // VPGATHERQQYrm + 401U, // VPGATHERQQZ128rm + 401U, // VPGATHERQQZ256rm + 401U, // VPGATHERQQZrm + 0U, // VPGATHERQQrm + 0U, // VPHADDBDrm + 0U, // VPHADDBDrr + 0U, // VPHADDBQrm + 0U, // VPHADDBQrr + 0U, // VPHADDBWrm + 0U, // VPHADDBWrr + 0U, // VPHADDDQrm + 0U, // VPHADDDQrr + 4U, // VPHADDDYrm + 4U, // VPHADDDYrr + 4U, // VPHADDDrm + 4U, // VPHADDDrr + 4U, // VPHADDSWYrm + 4U, // VPHADDSWYrr + 4U, // VPHADDSWrm + 4U, // VPHADDSWrr + 0U, // VPHADDUBDrm + 0U, // VPHADDUBDrr + 0U, // VPHADDUBQrm + 0U, // VPHADDUBQrr + 0U, // VPHADDUBWrm + 0U, // VPHADDUBWrr + 0U, // VPHADDUDQrm + 0U, // VPHADDUDQrr + 0U, // VPHADDUWDrm + 0U, // VPHADDUWDrr + 0U, // VPHADDUWQrm + 0U, // VPHADDUWQrr + 0U, // VPHADDWDrm + 0U, // VPHADDWDrr + 0U, // VPHADDWQrm + 0U, // VPHADDWQrr + 4U, // VPHADDWYrm + 4U, // VPHADDWYrr + 4U, // VPHADDWrm + 4U, // VPHADDWrr + 0U, // VPHMINPOSUWrm + 0U, // VPHMINPOSUWrr + 0U, // VPHSUBBWrm + 0U, // VPHSUBBWrr + 0U, // VPHSUBDQrm + 0U, // VPHSUBDQrr + 4U, // VPHSUBDYrm + 4U, // VPHSUBDYrr + 4U, // VPHSUBDrm + 4U, // VPHSUBDrr + 4U, // VPHSUBSWYrm + 4U, // VPHSUBSWYrr + 4U, // VPHSUBSWrm + 4U, // VPHSUBSWrr + 0U, // VPHSUBWDrm + 0U, // VPHSUBWDrr + 4U, // VPHSUBWYrm + 4U, // VPHSUBWYrr + 4U, // VPHSUBWrm + 4U, // VPHSUBWrr + 18636U, // VPINSRBZrm + 18636U, // VPINSRBZrr + 18636U, // VPINSRBrm + 18636U, // VPINSRBrr + 18636U, // VPINSRDZrm + 18636U, // VPINSRDZrr + 18636U, // VPINSRDrm + 18636U, // VPINSRDrr + 18636U, // VPINSRQZrm + 18636U, // VPINSRQZrr + 18636U, // VPINSRQrm + 18636U, // VPINSRQrr + 72U, // VPINSRWZrm + 18636U, // VPINSRWZrr + 72U, // VPINSRWrm + 18636U, // VPINSRWrr + 0U, // VPLZCNTDZ128rm + 0U, // VPLZCNTDZ128rmb + 3356U, // VPLZCNTDZ128rmbk + 4444U, // VPLZCNTDZ128rmbkz + 405U, // VPLZCNTDZ128rmk + 461U, // VPLZCNTDZ128rmkz + 0U, // VPLZCNTDZ128rr + 405U, // VPLZCNTDZ128rrk + 461U, // VPLZCNTDZ128rrkz + 0U, // VPLZCNTDZ256rm + 0U, // VPLZCNTDZ256rmb + 3356U, // VPLZCNTDZ256rmbk + 4444U, // VPLZCNTDZ256rmbkz + 405U, // VPLZCNTDZ256rmk + 461U, // VPLZCNTDZ256rmkz + 0U, // VPLZCNTDZ256rr + 405U, // VPLZCNTDZ256rrk + 461U, // VPLZCNTDZ256rrkz + 0U, // VPLZCNTDZrm + 0U, // VPLZCNTDZrmb + 3356U, // VPLZCNTDZrmbk + 4444U, // VPLZCNTDZrmbkz + 405U, // VPLZCNTDZrmk + 461U, // VPLZCNTDZrmkz + 0U, // VPLZCNTDZrr + 405U, // VPLZCNTDZrrk + 461U, // VPLZCNTDZrrkz + 0U, // VPLZCNTQZ128rm + 0U, // VPLZCNTQZ128rmb + 3356U, // VPLZCNTQZ128rmbk + 4444U, // VPLZCNTQZ128rmbkz + 405U, // VPLZCNTQZ128rmk + 461U, // VPLZCNTQZ128rmkz + 0U, // VPLZCNTQZ128rr + 405U, // VPLZCNTQZ128rrk + 461U, // VPLZCNTQZ128rrkz + 0U, // VPLZCNTQZ256rm + 0U, // VPLZCNTQZ256rmb + 3356U, // VPLZCNTQZ256rmbk + 4444U, // VPLZCNTQZ256rmbkz + 405U, // VPLZCNTQZ256rmk + 461U, // VPLZCNTQZ256rmkz + 0U, // VPLZCNTQZ256rr + 405U, // VPLZCNTQZ256rrk + 461U, // VPLZCNTQZ256rrkz + 0U, // VPLZCNTQZrm + 0U, // VPLZCNTQZrmb + 3356U, // VPLZCNTQZrmbk + 4444U, // VPLZCNTQZrmbkz + 405U, // VPLZCNTQZrmk + 461U, // VPLZCNTQZrmkz + 0U, // VPLZCNTQZrr + 405U, // VPLZCNTQZrrk + 461U, // VPLZCNTQZrrkz + 72U, // VPMACSDDrm + 18636U, // VPMACSDDrr + 72U, // VPMACSDQHrm + 18636U, // VPMACSDQHrr + 72U, // VPMACSDQLrm + 18636U, // VPMACSDQLrr + 72U, // VPMACSSDDrm + 18636U, // VPMACSSDDrr + 72U, // VPMACSSDQHrm + 18636U, // VPMACSSDQHrr + 72U, // VPMACSSDQLrm + 18636U, // VPMACSSDQLrr + 72U, // VPMACSSWDrm + 18636U, // VPMACSSWDrr + 72U, // VPMACSSWWrm + 18636U, // VPMACSSWWrr + 72U, // VPMACSWDrm + 18636U, // VPMACSWDrr + 72U, // VPMACSWWrm + 18636U, // VPMACSWWrr + 72U, // VPMADCSSWDrm + 18636U, // VPMADCSSWDrr + 72U, // VPMADCSWDrm + 18636U, // VPMADCSWDrr + 4U, // VPMADD52HUQZ128m + 4U, // VPMADD52HUQZ128mb + 133U, // VPMADD52HUQZ128mbk + 8325U, // VPMADD52HUQZ128mbkz + 132U, // VPMADD52HUQZ128mk + 8324U, // VPMADD52HUQZ128mkz + 4U, // VPMADD52HUQZ128r + 0U, // VPMADD52HUQZ128rk + 0U, // VPMADD52HUQZ128rkz + 4U, // VPMADD52HUQZ256m + 4U, // VPMADD52HUQZ256mb + 133U, // VPMADD52HUQZ256mbk + 8325U, // VPMADD52HUQZ256mbkz + 132U, // VPMADD52HUQZ256mk + 8324U, // VPMADD52HUQZ256mkz + 4U, // VPMADD52HUQZ256r + 0U, // VPMADD52HUQZ256rk + 0U, // VPMADD52HUQZ256rkz + 4U, // VPMADD52HUQZm + 4U, // VPMADD52HUQZmb + 133U, // VPMADD52HUQZmbk + 8325U, // VPMADD52HUQZmbkz + 132U, // VPMADD52HUQZmk + 8324U, // VPMADD52HUQZmkz + 4U, // VPMADD52HUQZr + 0U, // VPMADD52HUQZrk + 0U, // VPMADD52HUQZrkz + 4U, // VPMADD52LUQZ128m + 4U, // VPMADD52LUQZ128mb + 133U, // VPMADD52LUQZ128mbk + 8325U, // VPMADD52LUQZ128mbkz + 132U, // VPMADD52LUQZ128mk + 8324U, // VPMADD52LUQZ128mkz + 4U, // VPMADD52LUQZ128r + 0U, // VPMADD52LUQZ128rk + 0U, // VPMADD52LUQZ128rkz + 4U, // VPMADD52LUQZ256m + 4U, // VPMADD52LUQZ256mb + 133U, // VPMADD52LUQZ256mbk + 8325U, // VPMADD52LUQZ256mbkz + 132U, // VPMADD52LUQZ256mk + 8324U, // VPMADD52LUQZ256mkz + 4U, // VPMADD52LUQZ256r + 0U, // VPMADD52LUQZ256rk + 0U, // VPMADD52LUQZ256rkz + 4U, // VPMADD52LUQZm + 4U, // VPMADD52LUQZmb + 133U, // VPMADD52LUQZmbk + 8325U, // VPMADD52LUQZmbkz + 132U, // VPMADD52LUQZmk + 8324U, // VPMADD52LUQZmkz + 4U, // VPMADD52LUQZr + 0U, // VPMADD52LUQZrk + 0U, // VPMADD52LUQZrkz + 4U, // VPMADDUBSWYrm + 4U, // VPMADDUBSWYrr + 4U, // VPMADDUBSWZ128rm + 132U, // VPMADDUBSWZ128rmk + 9348U, // VPMADDUBSWZ128rmkz + 4U, // VPMADDUBSWZ128rr + 0U, // VPMADDUBSWZ128rrk + 9348U, // VPMADDUBSWZ128rrkz + 4U, // VPMADDUBSWZ256rm + 132U, // VPMADDUBSWZ256rmk + 9348U, // VPMADDUBSWZ256rmkz + 4U, // VPMADDUBSWZ256rr + 0U, // VPMADDUBSWZ256rrk + 9348U, // VPMADDUBSWZ256rrkz + 4U, // VPMADDUBSWZrm + 132U, // VPMADDUBSWZrmk + 9348U, // VPMADDUBSWZrmkz + 4U, // VPMADDUBSWZrr + 0U, // VPMADDUBSWZrrk + 9348U, // VPMADDUBSWZrrkz + 4U, // VPMADDUBSWrm + 4U, // VPMADDUBSWrr + 4U, // VPMADDWDYrm + 4U, // VPMADDWDYrr + 4U, // VPMADDWDZ128rm + 132U, // VPMADDWDZ128rmk + 9348U, // VPMADDWDZ128rmkz + 4U, // VPMADDWDZ128rr + 0U, // VPMADDWDZ128rrk + 9348U, // VPMADDWDZ128rrkz + 4U, // VPMADDWDZ256rm + 132U, // VPMADDWDZ256rmk + 9348U, // VPMADDWDZ256rmkz + 4U, // VPMADDWDZ256rr + 0U, // VPMADDWDZ256rrk + 9348U, // VPMADDWDZ256rrkz + 4U, // VPMADDWDZrm + 132U, // VPMADDWDZrmk + 9348U, // VPMADDWDZrmkz + 4U, // VPMADDWDZrr + 0U, // VPMADDWDZrrk + 9348U, // VPMADDWDZrrkz + 4U, // VPMADDWDrm + 4U, // VPMADDWDrr + 2U, // VPMASKMOVDYmr + 4U, // VPMASKMOVDYrm + 2U, // VPMASKMOVDmr + 4U, // VPMASKMOVDrm + 2U, // VPMASKMOVQYmr + 4U, // VPMASKMOVQYrm + 2U, // VPMASKMOVQmr + 4U, // VPMASKMOVQrm + 4U, // VPMAXSBYrm + 4U, // VPMAXSBYrr + 4U, // VPMAXSBZ128rm + 132U, // VPMAXSBZ128rmk + 9348U, // VPMAXSBZ128rmkz + 4U, // VPMAXSBZ128rr + 0U, // VPMAXSBZ128rrk + 9348U, // VPMAXSBZ128rrkz + 4U, // VPMAXSBZ256rm + 132U, // VPMAXSBZ256rmk + 9348U, // VPMAXSBZ256rmkz + 4U, // VPMAXSBZ256rr + 0U, // VPMAXSBZ256rrk + 9348U, // VPMAXSBZ256rrkz + 4U, // VPMAXSBZrm + 132U, // VPMAXSBZrmk + 9348U, // VPMAXSBZrmkz + 4U, // VPMAXSBZrr + 0U, // VPMAXSBZrrk + 9348U, // VPMAXSBZrrkz + 4U, // VPMAXSBrm + 4U, // VPMAXSBrr + 4U, // VPMAXSDYrm + 4U, // VPMAXSDYrr + 4U, // VPMAXSDZ128rm + 72U, // VPMAXSDZ128rmb + 133U, // VPMAXSDZ128rmbk + 9348U, // VPMAXSDZ128rmbkz + 132U, // VPMAXSDZ128rmk + 9348U, // VPMAXSDZ128rmkz + 4U, // VPMAXSDZ128rr + 0U, // VPMAXSDZ128rrk + 9348U, // VPMAXSDZ128rrkz + 4U, // VPMAXSDZ256rm + 72U, // VPMAXSDZ256rmb + 133U, // VPMAXSDZ256rmbk + 9348U, // VPMAXSDZ256rmbkz + 132U, // VPMAXSDZ256rmk + 9348U, // VPMAXSDZ256rmkz + 4U, // VPMAXSDZ256rr + 0U, // VPMAXSDZ256rrk + 9348U, // VPMAXSDZ256rrkz + 4U, // VPMAXSDZrm + 72U, // VPMAXSDZrmb + 133U, // VPMAXSDZrmbk + 9348U, // VPMAXSDZrmbkz + 132U, // VPMAXSDZrmk + 9348U, // VPMAXSDZrmkz + 4U, // VPMAXSDZrr + 0U, // VPMAXSDZrrk + 9348U, // VPMAXSDZrrkz + 4U, // VPMAXSDrm + 4U, // VPMAXSDrr + 4U, // VPMAXSQZ128rm + 72U, // VPMAXSQZ128rmb + 133U, // VPMAXSQZ128rmbk + 9348U, // VPMAXSQZ128rmbkz + 132U, // VPMAXSQZ128rmk + 9348U, // VPMAXSQZ128rmkz + 4U, // VPMAXSQZ128rr + 0U, // VPMAXSQZ128rrk + 9348U, // VPMAXSQZ128rrkz + 4U, // VPMAXSQZ256rm + 72U, // VPMAXSQZ256rmb + 133U, // VPMAXSQZ256rmbk + 9348U, // VPMAXSQZ256rmbkz + 132U, // VPMAXSQZ256rmk + 9348U, // VPMAXSQZ256rmkz + 4U, // VPMAXSQZ256rr + 0U, // VPMAXSQZ256rrk + 9348U, // VPMAXSQZ256rrkz + 4U, // VPMAXSQZrm + 72U, // VPMAXSQZrmb + 133U, // VPMAXSQZrmbk + 9348U, // VPMAXSQZrmbkz + 132U, // VPMAXSQZrmk + 9348U, // VPMAXSQZrmkz + 4U, // VPMAXSQZrr + 0U, // VPMAXSQZrrk + 9348U, // VPMAXSQZrrkz + 4U, // VPMAXSWYrm + 4U, // VPMAXSWYrr + 4U, // VPMAXSWZ128rm + 132U, // VPMAXSWZ128rmk + 9348U, // VPMAXSWZ128rmkz + 4U, // VPMAXSWZ128rr + 0U, // VPMAXSWZ128rrk + 9348U, // VPMAXSWZ128rrkz + 4U, // VPMAXSWZ256rm + 132U, // VPMAXSWZ256rmk + 9348U, // VPMAXSWZ256rmkz + 4U, // VPMAXSWZ256rr + 0U, // VPMAXSWZ256rrk + 9348U, // VPMAXSWZ256rrkz + 4U, // VPMAXSWZrm + 132U, // VPMAXSWZrmk + 9348U, // VPMAXSWZrmkz + 4U, // VPMAXSWZrr + 0U, // VPMAXSWZrrk + 9348U, // VPMAXSWZrrkz + 4U, // VPMAXSWrm + 4U, // VPMAXSWrr + 4U, // VPMAXUBYrm + 4U, // VPMAXUBYrr + 4U, // VPMAXUBZ128rm + 132U, // VPMAXUBZ128rmk + 9348U, // VPMAXUBZ128rmkz + 4U, // VPMAXUBZ128rr + 0U, // VPMAXUBZ128rrk + 9348U, // VPMAXUBZ128rrkz + 4U, // VPMAXUBZ256rm + 132U, // VPMAXUBZ256rmk + 9348U, // VPMAXUBZ256rmkz + 4U, // VPMAXUBZ256rr + 0U, // VPMAXUBZ256rrk + 9348U, // VPMAXUBZ256rrkz + 4U, // VPMAXUBZrm + 132U, // VPMAXUBZrmk + 9348U, // VPMAXUBZrmkz + 4U, // VPMAXUBZrr + 0U, // VPMAXUBZrrk + 9348U, // VPMAXUBZrrkz + 4U, // VPMAXUBrm + 4U, // VPMAXUBrr + 4U, // VPMAXUDYrm + 4U, // VPMAXUDYrr + 4U, // VPMAXUDZ128rm + 72U, // VPMAXUDZ128rmb + 133U, // VPMAXUDZ128rmbk + 9348U, // VPMAXUDZ128rmbkz + 132U, // VPMAXUDZ128rmk + 9348U, // VPMAXUDZ128rmkz + 4U, // VPMAXUDZ128rr + 0U, // VPMAXUDZ128rrk + 9348U, // VPMAXUDZ128rrkz + 4U, // VPMAXUDZ256rm + 72U, // VPMAXUDZ256rmb + 133U, // VPMAXUDZ256rmbk + 9348U, // VPMAXUDZ256rmbkz + 132U, // VPMAXUDZ256rmk + 9348U, // VPMAXUDZ256rmkz + 4U, // VPMAXUDZ256rr + 0U, // VPMAXUDZ256rrk + 9348U, // VPMAXUDZ256rrkz + 4U, // VPMAXUDZrm + 72U, // VPMAXUDZrmb + 133U, // VPMAXUDZrmbk + 9348U, // VPMAXUDZrmbkz + 132U, // VPMAXUDZrmk + 9348U, // VPMAXUDZrmkz + 4U, // VPMAXUDZrr + 0U, // VPMAXUDZrrk + 9348U, // VPMAXUDZrrkz + 4U, // VPMAXUDrm + 4U, // VPMAXUDrr + 4U, // VPMAXUQZ128rm + 72U, // VPMAXUQZ128rmb + 133U, // VPMAXUQZ128rmbk + 9348U, // VPMAXUQZ128rmbkz + 132U, // VPMAXUQZ128rmk + 9348U, // VPMAXUQZ128rmkz + 4U, // VPMAXUQZ128rr + 0U, // VPMAXUQZ128rrk + 9348U, // VPMAXUQZ128rrkz + 4U, // VPMAXUQZ256rm + 72U, // VPMAXUQZ256rmb + 133U, // VPMAXUQZ256rmbk + 9348U, // VPMAXUQZ256rmbkz + 132U, // VPMAXUQZ256rmk + 9348U, // VPMAXUQZ256rmkz + 4U, // VPMAXUQZ256rr + 0U, // VPMAXUQZ256rrk + 9348U, // VPMAXUQZ256rrkz + 4U, // VPMAXUQZrm + 72U, // VPMAXUQZrmb + 133U, // VPMAXUQZrmbk + 9348U, // VPMAXUQZrmbkz + 132U, // VPMAXUQZrmk + 9348U, // VPMAXUQZrmkz + 4U, // VPMAXUQZrr + 0U, // VPMAXUQZrrk + 9348U, // VPMAXUQZrrkz + 4U, // VPMAXUWYrm + 4U, // VPMAXUWYrr + 4U, // VPMAXUWZ128rm + 132U, // VPMAXUWZ128rmk + 9348U, // VPMAXUWZ128rmkz + 4U, // VPMAXUWZ128rr + 0U, // VPMAXUWZ128rrk + 9348U, // VPMAXUWZ128rrkz + 4U, // VPMAXUWZ256rm + 132U, // VPMAXUWZ256rmk + 9348U, // VPMAXUWZ256rmkz + 4U, // VPMAXUWZ256rr + 0U, // VPMAXUWZ256rrk + 9348U, // VPMAXUWZ256rrkz + 4U, // VPMAXUWZrm + 132U, // VPMAXUWZrmk + 9348U, // VPMAXUWZrmkz + 4U, // VPMAXUWZrr + 0U, // VPMAXUWZrrk + 9348U, // VPMAXUWZrrkz + 4U, // VPMAXUWrm + 4U, // VPMAXUWrr + 4U, // VPMINSBYrm + 4U, // VPMINSBYrr + 4U, // VPMINSBZ128rm + 132U, // VPMINSBZ128rmk + 9348U, // VPMINSBZ128rmkz + 4U, // VPMINSBZ128rr + 0U, // VPMINSBZ128rrk + 9348U, // VPMINSBZ128rrkz + 4U, // VPMINSBZ256rm + 132U, // VPMINSBZ256rmk + 9348U, // VPMINSBZ256rmkz + 4U, // VPMINSBZ256rr + 0U, // VPMINSBZ256rrk + 9348U, // VPMINSBZ256rrkz + 4U, // VPMINSBZrm + 132U, // VPMINSBZrmk + 9348U, // VPMINSBZrmkz + 4U, // VPMINSBZrr + 0U, // VPMINSBZrrk + 9348U, // VPMINSBZrrkz + 4U, // VPMINSBrm + 4U, // VPMINSBrr + 4U, // VPMINSDYrm + 4U, // VPMINSDYrr + 4U, // VPMINSDZ128rm + 72U, // VPMINSDZ128rmb + 133U, // VPMINSDZ128rmbk + 9348U, // VPMINSDZ128rmbkz + 132U, // VPMINSDZ128rmk + 9348U, // VPMINSDZ128rmkz + 4U, // VPMINSDZ128rr + 0U, // VPMINSDZ128rrk + 9348U, // VPMINSDZ128rrkz + 4U, // VPMINSDZ256rm + 72U, // VPMINSDZ256rmb + 133U, // VPMINSDZ256rmbk + 9348U, // VPMINSDZ256rmbkz + 132U, // VPMINSDZ256rmk + 9348U, // VPMINSDZ256rmkz + 4U, // VPMINSDZ256rr + 0U, // VPMINSDZ256rrk + 9348U, // VPMINSDZ256rrkz + 4U, // VPMINSDZrm + 72U, // VPMINSDZrmb + 133U, // VPMINSDZrmbk + 9348U, // VPMINSDZrmbkz + 132U, // VPMINSDZrmk + 9348U, // VPMINSDZrmkz + 4U, // VPMINSDZrr + 0U, // VPMINSDZrrk + 9348U, // VPMINSDZrrkz + 4U, // VPMINSDrm + 4U, // VPMINSDrr + 4U, // VPMINSQZ128rm + 72U, // VPMINSQZ128rmb + 133U, // VPMINSQZ128rmbk + 9348U, // VPMINSQZ128rmbkz + 132U, // VPMINSQZ128rmk + 9348U, // VPMINSQZ128rmkz + 4U, // VPMINSQZ128rr + 0U, // VPMINSQZ128rrk + 9348U, // VPMINSQZ128rrkz + 4U, // VPMINSQZ256rm + 72U, // VPMINSQZ256rmb + 133U, // VPMINSQZ256rmbk + 9348U, // VPMINSQZ256rmbkz + 132U, // VPMINSQZ256rmk + 9348U, // VPMINSQZ256rmkz + 4U, // VPMINSQZ256rr + 0U, // VPMINSQZ256rrk + 9348U, // VPMINSQZ256rrkz + 4U, // VPMINSQZrm + 72U, // VPMINSQZrmb + 133U, // VPMINSQZrmbk + 9348U, // VPMINSQZrmbkz + 132U, // VPMINSQZrmk + 9348U, // VPMINSQZrmkz + 4U, // VPMINSQZrr + 0U, // VPMINSQZrrk + 9348U, // VPMINSQZrrkz + 4U, // VPMINSWYrm + 4U, // VPMINSWYrr + 4U, // VPMINSWZ128rm + 132U, // VPMINSWZ128rmk + 9348U, // VPMINSWZ128rmkz + 4U, // VPMINSWZ128rr + 0U, // VPMINSWZ128rrk + 9348U, // VPMINSWZ128rrkz + 4U, // VPMINSWZ256rm + 132U, // VPMINSWZ256rmk + 9348U, // VPMINSWZ256rmkz + 4U, // VPMINSWZ256rr + 0U, // VPMINSWZ256rrk + 9348U, // VPMINSWZ256rrkz + 4U, // VPMINSWZrm + 132U, // VPMINSWZrmk + 9348U, // VPMINSWZrmkz + 4U, // VPMINSWZrr + 0U, // VPMINSWZrrk + 9348U, // VPMINSWZrrkz + 4U, // VPMINSWrm + 4U, // VPMINSWrr + 4U, // VPMINUBYrm + 4U, // VPMINUBYrr + 4U, // VPMINUBZ128rm + 132U, // VPMINUBZ128rmk + 9348U, // VPMINUBZ128rmkz + 4U, // VPMINUBZ128rr + 0U, // VPMINUBZ128rrk + 9348U, // VPMINUBZ128rrkz + 4U, // VPMINUBZ256rm + 132U, // VPMINUBZ256rmk + 9348U, // VPMINUBZ256rmkz + 4U, // VPMINUBZ256rr + 0U, // VPMINUBZ256rrk + 9348U, // VPMINUBZ256rrkz + 4U, // VPMINUBZrm + 132U, // VPMINUBZrmk + 9348U, // VPMINUBZrmkz + 4U, // VPMINUBZrr + 0U, // VPMINUBZrrk + 9348U, // VPMINUBZrrkz + 4U, // VPMINUBrm + 4U, // VPMINUBrr + 4U, // VPMINUDYrm + 4U, // VPMINUDYrr + 4U, // VPMINUDZ128rm + 72U, // VPMINUDZ128rmb + 133U, // VPMINUDZ128rmbk + 9348U, // VPMINUDZ128rmbkz + 132U, // VPMINUDZ128rmk + 9348U, // VPMINUDZ128rmkz + 4U, // VPMINUDZ128rr + 0U, // VPMINUDZ128rrk + 9348U, // VPMINUDZ128rrkz + 4U, // VPMINUDZ256rm + 72U, // VPMINUDZ256rmb + 133U, // VPMINUDZ256rmbk + 9348U, // VPMINUDZ256rmbkz + 132U, // VPMINUDZ256rmk + 9348U, // VPMINUDZ256rmkz + 4U, // VPMINUDZ256rr + 0U, // VPMINUDZ256rrk + 9348U, // VPMINUDZ256rrkz + 4U, // VPMINUDZrm + 72U, // VPMINUDZrmb + 133U, // VPMINUDZrmbk + 9348U, // VPMINUDZrmbkz + 132U, // VPMINUDZrmk + 9348U, // VPMINUDZrmkz + 4U, // VPMINUDZrr + 0U, // VPMINUDZrrk + 9348U, // VPMINUDZrrkz + 4U, // VPMINUDrm + 4U, // VPMINUDrr + 4U, // VPMINUQZ128rm + 72U, // VPMINUQZ128rmb + 133U, // VPMINUQZ128rmbk + 9348U, // VPMINUQZ128rmbkz + 132U, // VPMINUQZ128rmk + 9348U, // VPMINUQZ128rmkz + 4U, // VPMINUQZ128rr + 0U, // VPMINUQZ128rrk + 9348U, // VPMINUQZ128rrkz + 4U, // VPMINUQZ256rm + 72U, // VPMINUQZ256rmb + 133U, // VPMINUQZ256rmbk + 9348U, // VPMINUQZ256rmbkz + 132U, // VPMINUQZ256rmk + 9348U, // VPMINUQZ256rmkz + 4U, // VPMINUQZ256rr + 0U, // VPMINUQZ256rrk + 9348U, // VPMINUQZ256rrkz + 4U, // VPMINUQZrm + 72U, // VPMINUQZrmb + 133U, // VPMINUQZrmbk + 9348U, // VPMINUQZrmbkz + 132U, // VPMINUQZrmk + 9348U, // VPMINUQZrmkz + 4U, // VPMINUQZrr + 0U, // VPMINUQZrrk + 9348U, // VPMINUQZrrkz + 4U, // VPMINUWYrm + 4U, // VPMINUWYrr + 4U, // VPMINUWZ128rm + 132U, // VPMINUWZ128rmk + 9348U, // VPMINUWZ128rmkz + 4U, // VPMINUWZ128rr + 0U, // VPMINUWZ128rrk + 9348U, // VPMINUWZ128rrkz + 4U, // VPMINUWZ256rm + 132U, // VPMINUWZ256rmk + 9348U, // VPMINUWZ256rmkz + 4U, // VPMINUWZ256rr + 0U, // VPMINUWZ256rrk + 9348U, // VPMINUWZ256rrkz + 4U, // VPMINUWZrm + 132U, // VPMINUWZrmk + 9348U, // VPMINUWZrmkz + 4U, // VPMINUWZrr + 0U, // VPMINUWZrrk + 9348U, // VPMINUWZrrkz + 4U, // VPMINUWrm + 4U, // VPMINUWrr + 0U, // VPMOVB2MZ128rr + 0U, // VPMOVB2MZ256rr + 0U, // VPMOVB2MZrr + 0U, // VPMOVD2MZ128rr + 0U, // VPMOVD2MZ256rr + 0U, // VPMOVD2MZrr + 0U, // VPMOVDBZ128mr + 49U, // VPMOVDBZ128mrk + 0U, // VPMOVDBZ128rr + 405U, // VPMOVDBZ128rrk + 461U, // VPMOVDBZ128rrkz + 0U, // VPMOVDBZ256mr + 49U, // VPMOVDBZ256mrk + 0U, // VPMOVDBZ256rr + 405U, // VPMOVDBZ256rrk + 461U, // VPMOVDBZ256rrkz + 0U, // VPMOVDBZmr + 49U, // VPMOVDBZmrk + 0U, // VPMOVDBZrr + 405U, // VPMOVDBZrrk + 461U, // VPMOVDBZrrkz + 0U, // VPMOVDWZ128mr + 49U, // VPMOVDWZ128mrk + 0U, // VPMOVDWZ128rr + 405U, // VPMOVDWZ128rrk + 461U, // VPMOVDWZ128rrkz + 0U, // VPMOVDWZ256mr + 49U, // VPMOVDWZ256mrk + 0U, // VPMOVDWZ256rr + 405U, // VPMOVDWZ256rrk + 461U, // VPMOVDWZ256rrkz + 0U, // VPMOVDWZmr + 49U, // VPMOVDWZmrk + 0U, // VPMOVDWZrr + 405U, // VPMOVDWZrrk + 461U, // VPMOVDWZrrkz + 0U, // VPMOVM2BZ128rr + 0U, // VPMOVM2BZ256rr + 0U, // VPMOVM2BZrr + 0U, // VPMOVM2DZ128rr + 0U, // VPMOVM2DZ256rr + 0U, // VPMOVM2DZrr + 0U, // VPMOVM2QZ128rr + 0U, // VPMOVM2QZ256rr + 0U, // VPMOVM2QZrr + 0U, // VPMOVM2WZ128rr + 0U, // VPMOVM2WZ256rr + 0U, // VPMOVM2WZrr + 0U, // VPMOVMSKBYrr + 0U, // VPMOVMSKBrr + 0U, // VPMOVQ2MZ128rr + 0U, // VPMOVQ2MZ256rr + 0U, // VPMOVQ2MZrr + 0U, // VPMOVQBZ128mr + 49U, // VPMOVQBZ128mrk + 0U, // VPMOVQBZ128rr + 405U, // VPMOVQBZ128rrk + 461U, // VPMOVQBZ128rrkz + 0U, // VPMOVQBZ256mr + 49U, // VPMOVQBZ256mrk + 0U, // VPMOVQBZ256rr + 405U, // VPMOVQBZ256rrk + 461U, // VPMOVQBZ256rrkz + 0U, // VPMOVQBZmr + 49U, // VPMOVQBZmrk + 0U, // VPMOVQBZrr + 405U, // VPMOVQBZrrk + 461U, // VPMOVQBZrrkz + 0U, // VPMOVQDZ128mr + 49U, // VPMOVQDZ128mrk + 0U, // VPMOVQDZ128rr + 405U, // VPMOVQDZ128rrk + 461U, // VPMOVQDZ128rrkz + 0U, // VPMOVQDZ256mr + 49U, // VPMOVQDZ256mrk + 0U, // VPMOVQDZ256rr + 405U, // VPMOVQDZ256rrk + 461U, // VPMOVQDZ256rrkz + 0U, // VPMOVQDZmr + 49U, // VPMOVQDZmrk + 0U, // VPMOVQDZrr + 405U, // VPMOVQDZrrk + 461U, // VPMOVQDZrrkz + 0U, // VPMOVQWZ128mr + 49U, // VPMOVQWZ128mrk + 0U, // VPMOVQWZ128rr + 405U, // VPMOVQWZ128rrk + 461U, // VPMOVQWZ128rrkz + 0U, // VPMOVQWZ256mr + 49U, // VPMOVQWZ256mrk + 0U, // VPMOVQWZ256rr + 405U, // VPMOVQWZ256rrk + 461U, // VPMOVQWZ256rrkz + 0U, // VPMOVQWZmr + 49U, // VPMOVQWZmrk + 0U, // VPMOVQWZrr + 405U, // VPMOVQWZrrk + 461U, // VPMOVQWZrrkz + 0U, // VPMOVSDBZ128mr + 49U, // VPMOVSDBZ128mrk + 0U, // VPMOVSDBZ128rr + 405U, // VPMOVSDBZ128rrk + 461U, // VPMOVSDBZ128rrkz + 0U, // VPMOVSDBZ256mr + 49U, // VPMOVSDBZ256mrk + 0U, // VPMOVSDBZ256rr + 405U, // VPMOVSDBZ256rrk + 461U, // VPMOVSDBZ256rrkz + 0U, // VPMOVSDBZmr + 49U, // VPMOVSDBZmrk + 0U, // VPMOVSDBZrr + 405U, // VPMOVSDBZrrk + 461U, // VPMOVSDBZrrkz + 0U, // VPMOVSDWZ128mr + 49U, // VPMOVSDWZ128mrk + 0U, // VPMOVSDWZ128rr + 405U, // VPMOVSDWZ128rrk + 461U, // VPMOVSDWZ128rrkz + 0U, // VPMOVSDWZ256mr + 49U, // VPMOVSDWZ256mrk + 0U, // VPMOVSDWZ256rr + 405U, // VPMOVSDWZ256rrk + 461U, // VPMOVSDWZ256rrkz + 0U, // VPMOVSDWZmr + 49U, // VPMOVSDWZmrk + 0U, // VPMOVSDWZrr + 405U, // VPMOVSDWZrrk + 461U, // VPMOVSDWZrrkz + 0U, // VPMOVSQBZ128mr + 49U, // VPMOVSQBZ128mrk + 0U, // VPMOVSQBZ128rr + 405U, // VPMOVSQBZ128rrk + 461U, // VPMOVSQBZ128rrkz + 0U, // VPMOVSQBZ256mr + 49U, // VPMOVSQBZ256mrk + 0U, // VPMOVSQBZ256rr + 405U, // VPMOVSQBZ256rrk + 461U, // VPMOVSQBZ256rrkz + 0U, // VPMOVSQBZmr + 49U, // VPMOVSQBZmrk + 0U, // VPMOVSQBZrr + 405U, // VPMOVSQBZrrk + 461U, // VPMOVSQBZrrkz + 0U, // VPMOVSQDZ128mr + 49U, // VPMOVSQDZ128mrk + 0U, // VPMOVSQDZ128rr + 405U, // VPMOVSQDZ128rrk + 461U, // VPMOVSQDZ128rrkz + 0U, // VPMOVSQDZ256mr + 49U, // VPMOVSQDZ256mrk + 0U, // VPMOVSQDZ256rr + 405U, // VPMOVSQDZ256rrk + 461U, // VPMOVSQDZ256rrkz + 0U, // VPMOVSQDZmr + 49U, // VPMOVSQDZmrk + 0U, // VPMOVSQDZrr + 405U, // VPMOVSQDZrrk + 461U, // VPMOVSQDZrrkz + 0U, // VPMOVSQWZ128mr + 49U, // VPMOVSQWZ128mrk + 0U, // VPMOVSQWZ128rr + 405U, // VPMOVSQWZ128rrk + 461U, // VPMOVSQWZ128rrkz + 0U, // VPMOVSQWZ256mr + 49U, // VPMOVSQWZ256mrk + 0U, // VPMOVSQWZ256rr + 405U, // VPMOVSQWZ256rrk + 461U, // VPMOVSQWZ256rrkz + 0U, // VPMOVSQWZmr + 49U, // VPMOVSQWZmrk + 0U, // VPMOVSQWZrr + 405U, // VPMOVSQWZrrk + 461U, // VPMOVSQWZrrkz + 0U, // VPMOVSWBZ128mr + 49U, // VPMOVSWBZ128mrk + 0U, // VPMOVSWBZ128rr + 405U, // VPMOVSWBZ128rrk + 461U, // VPMOVSWBZ128rrkz + 0U, // VPMOVSWBZ256mr + 49U, // VPMOVSWBZ256mrk + 0U, // VPMOVSWBZ256rr + 405U, // VPMOVSWBZ256rrk + 461U, // VPMOVSWBZ256rrkz + 0U, // VPMOVSWBZmr + 49U, // VPMOVSWBZmrk + 0U, // VPMOVSWBZrr + 405U, // VPMOVSWBZrrk + 461U, // VPMOVSWBZrrkz + 0U, // VPMOVSXBDYrm + 0U, // VPMOVSXBDYrr + 0U, // VPMOVSXBDZ128rm + 3356U, // VPMOVSXBDZ128rmk + 4444U, // VPMOVSXBDZ128rmkz + 0U, // VPMOVSXBDZ128rr + 405U, // VPMOVSXBDZ128rrk + 461U, // VPMOVSXBDZ128rrkz + 0U, // VPMOVSXBDZ256rm + 3356U, // VPMOVSXBDZ256rmk + 4444U, // VPMOVSXBDZ256rmkz + 0U, // VPMOVSXBDZ256rr + 405U, // VPMOVSXBDZ256rrk + 461U, // VPMOVSXBDZ256rrkz + 0U, // VPMOVSXBDZrm + 405U, // VPMOVSXBDZrmk + 461U, // VPMOVSXBDZrmkz + 0U, // VPMOVSXBDZrr + 405U, // VPMOVSXBDZrrk + 461U, // VPMOVSXBDZrrkz + 0U, // VPMOVSXBDrm + 0U, // VPMOVSXBDrr + 0U, // VPMOVSXBQYrm + 0U, // VPMOVSXBQYrr + 0U, // VPMOVSXBQZ128rm + 0U, // VPMOVSXBQZ128rmk + 461U, // VPMOVSXBQZ128rmkz + 0U, // VPMOVSXBQZ128rr + 405U, // VPMOVSXBQZ128rrk + 461U, // VPMOVSXBQZ128rrkz + 0U, // VPMOVSXBQZ256rm + 3356U, // VPMOVSXBQZ256rmk + 4444U, // VPMOVSXBQZ256rmkz + 0U, // VPMOVSXBQZ256rr + 405U, // VPMOVSXBQZ256rrk + 461U, // VPMOVSXBQZ256rrkz + 0U, // VPMOVSXBQZrm + 3356U, // VPMOVSXBQZrmk + 4444U, // VPMOVSXBQZrmkz + 0U, // VPMOVSXBQZrr + 405U, // VPMOVSXBQZrrk + 461U, // VPMOVSXBQZrrkz + 0U, // VPMOVSXBQrm + 0U, // VPMOVSXBQrr + 0U, // VPMOVSXBWYrm + 0U, // VPMOVSXBWYrr + 0U, // VPMOVSXBWZ128rm + 3356U, // VPMOVSXBWZ128rmk + 4444U, // VPMOVSXBWZ128rmkz + 0U, // VPMOVSXBWZ128rr + 405U, // VPMOVSXBWZ128rrk + 461U, // VPMOVSXBWZ128rrkz + 0U, // VPMOVSXBWZ256rm + 405U, // VPMOVSXBWZ256rmk + 461U, // VPMOVSXBWZ256rmkz + 0U, // VPMOVSXBWZ256rr + 405U, // VPMOVSXBWZ256rrk + 461U, // VPMOVSXBWZ256rrkz + 0U, // VPMOVSXBWZrm + 405U, // VPMOVSXBWZrmk + 461U, // VPMOVSXBWZrmkz + 0U, // VPMOVSXBWZrr + 405U, // VPMOVSXBWZrrk + 461U, // VPMOVSXBWZrrkz + 0U, // VPMOVSXBWrm + 0U, // VPMOVSXBWrr + 0U, // VPMOVSXDQYrm + 0U, // VPMOVSXDQYrr + 0U, // VPMOVSXDQZ128rm + 3356U, // VPMOVSXDQZ128rmk + 4444U, // VPMOVSXDQZ128rmkz + 0U, // VPMOVSXDQZ128rr + 405U, // VPMOVSXDQZ128rrk + 461U, // VPMOVSXDQZ128rrkz + 0U, // VPMOVSXDQZ256rm + 405U, // VPMOVSXDQZ256rmk + 461U, // VPMOVSXDQZ256rmkz + 0U, // VPMOVSXDQZ256rr + 405U, // VPMOVSXDQZ256rrk + 461U, // VPMOVSXDQZ256rrkz + 0U, // VPMOVSXDQZrm + 405U, // VPMOVSXDQZrmk + 461U, // VPMOVSXDQZrmkz + 0U, // VPMOVSXDQZrr + 405U, // VPMOVSXDQZrrk + 461U, // VPMOVSXDQZrrkz + 0U, // VPMOVSXDQrm + 0U, // VPMOVSXDQrr + 0U, // VPMOVSXWDYrm + 0U, // VPMOVSXWDYrr + 0U, // VPMOVSXWDZ128rm + 3356U, // VPMOVSXWDZ128rmk + 4444U, // VPMOVSXWDZ128rmkz + 0U, // VPMOVSXWDZ128rr + 405U, // VPMOVSXWDZ128rrk + 461U, // VPMOVSXWDZ128rrkz + 0U, // VPMOVSXWDZ256rm + 405U, // VPMOVSXWDZ256rmk + 461U, // VPMOVSXWDZ256rmkz + 0U, // VPMOVSXWDZ256rr + 405U, // VPMOVSXWDZ256rrk + 461U, // VPMOVSXWDZ256rrkz + 0U, // VPMOVSXWDZrm + 405U, // VPMOVSXWDZrmk + 461U, // VPMOVSXWDZrmkz + 0U, // VPMOVSXWDZrr + 405U, // VPMOVSXWDZrrk + 461U, // VPMOVSXWDZrrkz + 0U, // VPMOVSXWDrm + 0U, // VPMOVSXWDrr + 0U, // VPMOVSXWQYrm + 0U, // VPMOVSXWQYrr + 0U, // VPMOVSXWQZ128rm + 3356U, // VPMOVSXWQZ128rmk + 4444U, // VPMOVSXWQZ128rmkz + 0U, // VPMOVSXWQZ128rr + 405U, // VPMOVSXWQZ128rrk + 461U, // VPMOVSXWQZ128rrkz + 0U, // VPMOVSXWQZ256rm + 3356U, // VPMOVSXWQZ256rmk + 4444U, // VPMOVSXWQZ256rmkz + 0U, // VPMOVSXWQZ256rr + 405U, // VPMOVSXWQZ256rrk + 461U, // VPMOVSXWQZ256rrkz + 0U, // VPMOVSXWQZrm + 405U, // VPMOVSXWQZrmk + 461U, // VPMOVSXWQZrmkz + 0U, // VPMOVSXWQZrr + 405U, // VPMOVSXWQZrrk + 461U, // VPMOVSXWQZrrkz + 0U, // VPMOVSXWQrm + 0U, // VPMOVSXWQrr + 0U, // VPMOVUSDBZ128mr + 49U, // VPMOVUSDBZ128mrk + 0U, // VPMOVUSDBZ128rr + 405U, // VPMOVUSDBZ128rrk + 461U, // VPMOVUSDBZ128rrkz + 0U, // VPMOVUSDBZ256mr + 49U, // VPMOVUSDBZ256mrk + 0U, // VPMOVUSDBZ256rr + 405U, // VPMOVUSDBZ256rrk + 461U, // VPMOVUSDBZ256rrkz + 0U, // VPMOVUSDBZmr + 49U, // VPMOVUSDBZmrk + 0U, // VPMOVUSDBZrr + 405U, // VPMOVUSDBZrrk + 461U, // VPMOVUSDBZrrkz + 0U, // VPMOVUSDWZ128mr + 49U, // VPMOVUSDWZ128mrk + 0U, // VPMOVUSDWZ128rr + 405U, // VPMOVUSDWZ128rrk + 461U, // VPMOVUSDWZ128rrkz + 0U, // VPMOVUSDWZ256mr + 49U, // VPMOVUSDWZ256mrk + 0U, // VPMOVUSDWZ256rr + 405U, // VPMOVUSDWZ256rrk + 461U, // VPMOVUSDWZ256rrkz + 0U, // VPMOVUSDWZmr + 49U, // VPMOVUSDWZmrk + 0U, // VPMOVUSDWZrr + 405U, // VPMOVUSDWZrrk + 461U, // VPMOVUSDWZrrkz + 0U, // VPMOVUSQBZ128mr + 49U, // VPMOVUSQBZ128mrk + 0U, // VPMOVUSQBZ128rr + 405U, // VPMOVUSQBZ128rrk + 461U, // VPMOVUSQBZ128rrkz + 0U, // VPMOVUSQBZ256mr + 49U, // VPMOVUSQBZ256mrk + 0U, // VPMOVUSQBZ256rr + 405U, // VPMOVUSQBZ256rrk + 461U, // VPMOVUSQBZ256rrkz + 0U, // VPMOVUSQBZmr + 49U, // VPMOVUSQBZmrk + 0U, // VPMOVUSQBZrr + 405U, // VPMOVUSQBZrrk + 461U, // VPMOVUSQBZrrkz + 0U, // VPMOVUSQDZ128mr + 49U, // VPMOVUSQDZ128mrk + 0U, // VPMOVUSQDZ128rr + 405U, // VPMOVUSQDZ128rrk + 461U, // VPMOVUSQDZ128rrkz + 0U, // VPMOVUSQDZ256mr + 49U, // VPMOVUSQDZ256mrk + 0U, // VPMOVUSQDZ256rr + 405U, // VPMOVUSQDZ256rrk + 461U, // VPMOVUSQDZ256rrkz + 0U, // VPMOVUSQDZmr + 49U, // VPMOVUSQDZmrk + 0U, // VPMOVUSQDZrr + 405U, // VPMOVUSQDZrrk + 461U, // VPMOVUSQDZrrkz + 0U, // VPMOVUSQWZ128mr + 49U, // VPMOVUSQWZ128mrk + 0U, // VPMOVUSQWZ128rr + 405U, // VPMOVUSQWZ128rrk + 461U, // VPMOVUSQWZ128rrkz + 0U, // VPMOVUSQWZ256mr + 49U, // VPMOVUSQWZ256mrk + 0U, // VPMOVUSQWZ256rr + 405U, // VPMOVUSQWZ256rrk + 461U, // VPMOVUSQWZ256rrkz + 0U, // VPMOVUSQWZmr + 49U, // VPMOVUSQWZmrk + 0U, // VPMOVUSQWZrr + 405U, // VPMOVUSQWZrrk + 461U, // VPMOVUSQWZrrkz + 0U, // VPMOVUSWBZ128mr + 49U, // VPMOVUSWBZ128mrk + 0U, // VPMOVUSWBZ128rr + 405U, // VPMOVUSWBZ128rrk + 461U, // VPMOVUSWBZ128rrkz + 0U, // VPMOVUSWBZ256mr + 49U, // VPMOVUSWBZ256mrk + 0U, // VPMOVUSWBZ256rr + 405U, // VPMOVUSWBZ256rrk + 461U, // VPMOVUSWBZ256rrkz + 0U, // VPMOVUSWBZmr + 49U, // VPMOVUSWBZmrk + 0U, // VPMOVUSWBZrr + 405U, // VPMOVUSWBZrrk + 461U, // VPMOVUSWBZrrkz + 0U, // VPMOVW2MZ128rr + 0U, // VPMOVW2MZ256rr + 0U, // VPMOVW2MZrr + 0U, // VPMOVWBZ128mr + 49U, // VPMOVWBZ128mrk + 0U, // VPMOVWBZ128rr + 405U, // VPMOVWBZ128rrk + 461U, // VPMOVWBZ128rrkz + 0U, // VPMOVWBZ256mr + 49U, // VPMOVWBZ256mrk + 0U, // VPMOVWBZ256rr + 405U, // VPMOVWBZ256rrk + 461U, // VPMOVWBZ256rrkz + 0U, // VPMOVWBZmr + 49U, // VPMOVWBZmrk + 0U, // VPMOVWBZrr + 405U, // VPMOVWBZrrk + 461U, // VPMOVWBZrrkz + 0U, // VPMOVZXBDYrm + 0U, // VPMOVZXBDYrr + 0U, // VPMOVZXBDZ128rm + 3356U, // VPMOVZXBDZ128rmk + 4444U, // VPMOVZXBDZ128rmkz + 0U, // VPMOVZXBDZ128rr + 405U, // VPMOVZXBDZ128rrk + 461U, // VPMOVZXBDZ128rrkz + 0U, // VPMOVZXBDZ256rm + 3356U, // VPMOVZXBDZ256rmk + 4444U, // VPMOVZXBDZ256rmkz + 0U, // VPMOVZXBDZ256rr + 405U, // VPMOVZXBDZ256rrk + 461U, // VPMOVZXBDZ256rrkz + 0U, // VPMOVZXBDZrm + 405U, // VPMOVZXBDZrmk + 461U, // VPMOVZXBDZrmkz + 0U, // VPMOVZXBDZrr + 405U, // VPMOVZXBDZrrk + 461U, // VPMOVZXBDZrrkz + 0U, // VPMOVZXBDrm + 0U, // VPMOVZXBDrr + 0U, // VPMOVZXBQYrm + 0U, // VPMOVZXBQYrr + 0U, // VPMOVZXBQZ128rm + 0U, // VPMOVZXBQZ128rmk + 461U, // VPMOVZXBQZ128rmkz + 0U, // VPMOVZXBQZ128rr + 405U, // VPMOVZXBQZ128rrk + 461U, // VPMOVZXBQZ128rrkz + 0U, // VPMOVZXBQZ256rm + 3356U, // VPMOVZXBQZ256rmk + 4444U, // VPMOVZXBQZ256rmkz + 0U, // VPMOVZXBQZ256rr + 405U, // VPMOVZXBQZ256rrk + 461U, // VPMOVZXBQZ256rrkz + 0U, // VPMOVZXBQZrm + 3356U, // VPMOVZXBQZrmk + 4444U, // VPMOVZXBQZrmkz + 0U, // VPMOVZXBQZrr + 405U, // VPMOVZXBQZrrk + 461U, // VPMOVZXBQZrrkz + 0U, // VPMOVZXBQrm + 0U, // VPMOVZXBQrr + 0U, // VPMOVZXBWYrm + 0U, // VPMOVZXBWYrr + 0U, // VPMOVZXBWZ128rm + 3356U, // VPMOVZXBWZ128rmk + 4444U, // VPMOVZXBWZ128rmkz + 0U, // VPMOVZXBWZ128rr + 405U, // VPMOVZXBWZ128rrk + 461U, // VPMOVZXBWZ128rrkz + 0U, // VPMOVZXBWZ256rm + 405U, // VPMOVZXBWZ256rmk + 461U, // VPMOVZXBWZ256rmkz + 0U, // VPMOVZXBWZ256rr + 405U, // VPMOVZXBWZ256rrk + 461U, // VPMOVZXBWZ256rrkz + 0U, // VPMOVZXBWZrm + 405U, // VPMOVZXBWZrmk + 461U, // VPMOVZXBWZrmkz + 0U, // VPMOVZXBWZrr + 405U, // VPMOVZXBWZrrk + 461U, // VPMOVZXBWZrrkz + 0U, // VPMOVZXBWrm + 0U, // VPMOVZXBWrr + 0U, // VPMOVZXDQYrm + 0U, // VPMOVZXDQYrr + 0U, // VPMOVZXDQZ128rm + 3356U, // VPMOVZXDQZ128rmk + 4444U, // VPMOVZXDQZ128rmkz + 0U, // VPMOVZXDQZ128rr + 405U, // VPMOVZXDQZ128rrk + 461U, // VPMOVZXDQZ128rrkz + 0U, // VPMOVZXDQZ256rm + 405U, // VPMOVZXDQZ256rmk + 461U, // VPMOVZXDQZ256rmkz + 0U, // VPMOVZXDQZ256rr + 405U, // VPMOVZXDQZ256rrk + 461U, // VPMOVZXDQZ256rrkz + 0U, // VPMOVZXDQZrm + 405U, // VPMOVZXDQZrmk + 461U, // VPMOVZXDQZrmkz + 0U, // VPMOVZXDQZrr + 405U, // VPMOVZXDQZrrk + 461U, // VPMOVZXDQZrrkz + 0U, // VPMOVZXDQrm + 0U, // VPMOVZXDQrr + 0U, // VPMOVZXWDYrm + 0U, // VPMOVZXWDYrr + 0U, // VPMOVZXWDZ128rm + 3356U, // VPMOVZXWDZ128rmk + 4444U, // VPMOVZXWDZ128rmkz + 0U, // VPMOVZXWDZ128rr + 405U, // VPMOVZXWDZ128rrk + 461U, // VPMOVZXWDZ128rrkz + 0U, // VPMOVZXWDZ256rm + 405U, // VPMOVZXWDZ256rmk + 461U, // VPMOVZXWDZ256rmkz + 0U, // VPMOVZXWDZ256rr + 405U, // VPMOVZXWDZ256rrk + 461U, // VPMOVZXWDZ256rrkz + 0U, // VPMOVZXWDZrm + 405U, // VPMOVZXWDZrmk + 461U, // VPMOVZXWDZrmkz + 0U, // VPMOVZXWDZrr + 405U, // VPMOVZXWDZrrk + 461U, // VPMOVZXWDZrrkz + 0U, // VPMOVZXWDrm + 0U, // VPMOVZXWDrr + 0U, // VPMOVZXWQYrm + 0U, // VPMOVZXWQYrr + 0U, // VPMOVZXWQZ128rm + 3356U, // VPMOVZXWQZ128rmk + 4444U, // VPMOVZXWQZ128rmkz + 0U, // VPMOVZXWQZ128rr + 405U, // VPMOVZXWQZ128rrk + 461U, // VPMOVZXWQZ128rrkz + 0U, // VPMOVZXWQZ256rm + 3356U, // VPMOVZXWQZ256rmk + 4444U, // VPMOVZXWQZ256rmkz + 0U, // VPMOVZXWQZ256rr + 405U, // VPMOVZXWQZ256rrk + 461U, // VPMOVZXWQZ256rrkz + 0U, // VPMOVZXWQZrm + 405U, // VPMOVZXWQZrmk + 461U, // VPMOVZXWQZrmkz + 0U, // VPMOVZXWQZrr + 405U, // VPMOVZXWQZrrk + 461U, // VPMOVZXWQZrrkz + 0U, // VPMOVZXWQrm + 0U, // VPMOVZXWQrr + 4U, // VPMULDQYrm + 4U, // VPMULDQYrr + 4U, // VPMULDQZ128rm + 72U, // VPMULDQZ128rmb + 133U, // VPMULDQZ128rmbk + 9348U, // VPMULDQZ128rmbkz + 132U, // VPMULDQZ128rmk + 9348U, // VPMULDQZ128rmkz + 4U, // VPMULDQZ128rr + 0U, // VPMULDQZ128rrk + 9348U, // VPMULDQZ128rrkz + 4U, // VPMULDQZ256rm + 72U, // VPMULDQZ256rmb + 133U, // VPMULDQZ256rmbk + 9348U, // VPMULDQZ256rmbkz + 132U, // VPMULDQZ256rmk + 9348U, // VPMULDQZ256rmkz + 4U, // VPMULDQZ256rr + 0U, // VPMULDQZ256rrk + 9348U, // VPMULDQZ256rrkz + 4U, // VPMULDQZrm + 72U, // VPMULDQZrmb + 133U, // VPMULDQZrmbk + 9348U, // VPMULDQZrmbkz + 132U, // VPMULDQZrmk + 9348U, // VPMULDQZrmkz + 4U, // VPMULDQZrr + 0U, // VPMULDQZrrk + 9348U, // VPMULDQZrrkz + 4U, // VPMULDQrm + 4U, // VPMULDQrr + 4U, // VPMULHRSWYrm + 4U, // VPMULHRSWYrr + 4U, // VPMULHRSWZ128rm + 132U, // VPMULHRSWZ128rmk + 9348U, // VPMULHRSWZ128rmkz + 4U, // VPMULHRSWZ128rr + 0U, // VPMULHRSWZ128rrk + 9348U, // VPMULHRSWZ128rrkz + 4U, // VPMULHRSWZ256rm + 132U, // VPMULHRSWZ256rmk + 9348U, // VPMULHRSWZ256rmkz + 4U, // VPMULHRSWZ256rr + 0U, // VPMULHRSWZ256rrk + 9348U, // VPMULHRSWZ256rrkz + 4U, // VPMULHRSWZrm + 132U, // VPMULHRSWZrmk + 9348U, // VPMULHRSWZrmkz + 4U, // VPMULHRSWZrr + 0U, // VPMULHRSWZrrk + 9348U, // VPMULHRSWZrrkz + 4U, // VPMULHRSWrm + 4U, // VPMULHRSWrr + 4U, // VPMULHUWYrm + 4U, // VPMULHUWYrr + 4U, // VPMULHUWZ128rm + 132U, // VPMULHUWZ128rmk + 9348U, // VPMULHUWZ128rmkz + 4U, // VPMULHUWZ128rr + 0U, // VPMULHUWZ128rrk + 9348U, // VPMULHUWZ128rrkz + 4U, // VPMULHUWZ256rm + 132U, // VPMULHUWZ256rmk + 9348U, // VPMULHUWZ256rmkz + 4U, // VPMULHUWZ256rr + 0U, // VPMULHUWZ256rrk + 9348U, // VPMULHUWZ256rrkz + 4U, // VPMULHUWZrm + 132U, // VPMULHUWZrmk + 9348U, // VPMULHUWZrmkz + 4U, // VPMULHUWZrr + 0U, // VPMULHUWZrrk + 9348U, // VPMULHUWZrrkz + 4U, // VPMULHUWrm + 4U, // VPMULHUWrr + 4U, // VPMULHWYrm + 4U, // VPMULHWYrr + 4U, // VPMULHWZ128rm + 132U, // VPMULHWZ128rmk + 9348U, // VPMULHWZ128rmkz + 4U, // VPMULHWZ128rr + 0U, // VPMULHWZ128rrk + 9348U, // VPMULHWZ128rrkz + 4U, // VPMULHWZ256rm + 132U, // VPMULHWZ256rmk + 9348U, // VPMULHWZ256rmkz + 4U, // VPMULHWZ256rr + 0U, // VPMULHWZ256rrk + 9348U, // VPMULHWZ256rrkz + 4U, // VPMULHWZrm + 132U, // VPMULHWZrmk + 9348U, // VPMULHWZrmkz + 4U, // VPMULHWZrr + 0U, // VPMULHWZrrk + 9348U, // VPMULHWZrrkz + 4U, // VPMULHWrm + 4U, // VPMULHWrr + 4U, // VPMULLDYrm + 4U, // VPMULLDYrr + 4U, // VPMULLDZ128rm + 72U, // VPMULLDZ128rmb + 133U, // VPMULLDZ128rmbk + 9348U, // VPMULLDZ128rmbkz + 132U, // VPMULLDZ128rmk + 9348U, // VPMULLDZ128rmkz + 4U, // VPMULLDZ128rr + 0U, // VPMULLDZ128rrk + 9348U, // VPMULLDZ128rrkz + 4U, // VPMULLDZ256rm + 72U, // VPMULLDZ256rmb + 133U, // VPMULLDZ256rmbk + 9348U, // VPMULLDZ256rmbkz + 132U, // VPMULLDZ256rmk + 9348U, // VPMULLDZ256rmkz + 4U, // VPMULLDZ256rr + 0U, // VPMULLDZ256rrk + 9348U, // VPMULLDZ256rrkz + 4U, // VPMULLDZrm + 72U, // VPMULLDZrmb + 133U, // VPMULLDZrmbk + 9348U, // VPMULLDZrmbkz + 132U, // VPMULLDZrmk + 9348U, // VPMULLDZrmkz + 4U, // VPMULLDZrr + 0U, // VPMULLDZrrk + 9348U, // VPMULLDZrrkz + 4U, // VPMULLDrm + 4U, // VPMULLDrr + 4U, // VPMULLQZ128rm + 72U, // VPMULLQZ128rmb + 133U, // VPMULLQZ128rmbk + 9348U, // VPMULLQZ128rmbkz + 132U, // VPMULLQZ128rmk + 9348U, // VPMULLQZ128rmkz + 4U, // VPMULLQZ128rr + 0U, // VPMULLQZ128rrk + 9348U, // VPMULLQZ128rrkz + 4U, // VPMULLQZ256rm + 72U, // VPMULLQZ256rmb + 133U, // VPMULLQZ256rmbk + 9348U, // VPMULLQZ256rmbkz + 132U, // VPMULLQZ256rmk + 9348U, // VPMULLQZ256rmkz + 4U, // VPMULLQZ256rr + 0U, // VPMULLQZ256rrk + 9348U, // VPMULLQZ256rrkz + 4U, // VPMULLQZrm + 72U, // VPMULLQZrmb + 133U, // VPMULLQZrmbk + 9348U, // VPMULLQZrmbkz + 132U, // VPMULLQZrmk + 9348U, // VPMULLQZrmkz + 4U, // VPMULLQZrr + 0U, // VPMULLQZrrk + 9348U, // VPMULLQZrrkz + 4U, // VPMULLWYrm + 4U, // VPMULLWYrr + 4U, // VPMULLWZ128rm + 132U, // VPMULLWZ128rmk + 9348U, // VPMULLWZ128rmkz + 4U, // VPMULLWZ128rr + 0U, // VPMULLWZ128rrk + 9348U, // VPMULLWZ128rrkz + 4U, // VPMULLWZ256rm + 132U, // VPMULLWZ256rmk + 9348U, // VPMULLWZ256rmkz + 4U, // VPMULLWZ256rr + 0U, // VPMULLWZ256rrk + 9348U, // VPMULLWZ256rrkz + 4U, // VPMULLWZrm + 132U, // VPMULLWZrmk + 9348U, // VPMULLWZrmkz + 4U, // VPMULLWZrr + 0U, // VPMULLWZrrk + 9348U, // VPMULLWZrrkz + 4U, // VPMULLWrm + 4U, // VPMULLWrr + 4U, // VPMULTISHIFTQBZ128rm + 72U, // VPMULTISHIFTQBZ128rmb + 133U, // VPMULTISHIFTQBZ128rmbk + 9348U, // VPMULTISHIFTQBZ128rmbkz + 132U, // VPMULTISHIFTQBZ128rmk + 9348U, // VPMULTISHIFTQBZ128rmkz + 4U, // VPMULTISHIFTQBZ128rr + 0U, // VPMULTISHIFTQBZ128rrk + 9348U, // VPMULTISHIFTQBZ128rrkz + 4U, // VPMULTISHIFTQBZ256rm + 72U, // VPMULTISHIFTQBZ256rmb + 133U, // VPMULTISHIFTQBZ256rmbk + 9348U, // VPMULTISHIFTQBZ256rmbkz + 132U, // VPMULTISHIFTQBZ256rmk + 9348U, // VPMULTISHIFTQBZ256rmkz + 4U, // VPMULTISHIFTQBZ256rr + 0U, // VPMULTISHIFTQBZ256rrk + 9348U, // VPMULTISHIFTQBZ256rrkz + 4U, // VPMULTISHIFTQBZrm + 72U, // VPMULTISHIFTQBZrmb + 133U, // VPMULTISHIFTQBZrmbk + 9348U, // VPMULTISHIFTQBZrmbkz + 132U, // VPMULTISHIFTQBZrmk + 9348U, // VPMULTISHIFTQBZrmkz + 4U, // VPMULTISHIFTQBZrr + 0U, // VPMULTISHIFTQBZrrk + 9348U, // VPMULTISHIFTQBZrrkz + 4U, // VPMULUDQYrm + 4U, // VPMULUDQYrr + 4U, // VPMULUDQZ128rm + 72U, // VPMULUDQZ128rmb + 133U, // VPMULUDQZ128rmbk + 9348U, // VPMULUDQZ128rmbkz + 132U, // VPMULUDQZ128rmk + 9348U, // VPMULUDQZ128rmkz + 4U, // VPMULUDQZ128rr + 0U, // VPMULUDQZ128rrk + 9348U, // VPMULUDQZ128rrkz + 4U, // VPMULUDQZ256rm + 72U, // VPMULUDQZ256rmb + 133U, // VPMULUDQZ256rmbk + 9348U, // VPMULUDQZ256rmbkz + 132U, // VPMULUDQZ256rmk + 9348U, // VPMULUDQZ256rmkz + 4U, // VPMULUDQZ256rr + 0U, // VPMULUDQZ256rrk + 9348U, // VPMULUDQZ256rrkz + 4U, // VPMULUDQZrm + 72U, // VPMULUDQZrmb + 133U, // VPMULUDQZrmbk + 9348U, // VPMULUDQZrmbkz + 132U, // VPMULUDQZrmk + 9348U, // VPMULUDQZrmkz + 4U, // VPMULUDQZrr + 0U, // VPMULUDQZrrk + 9348U, // VPMULUDQZrrkz + 4U, // VPMULUDQrm + 4U, // VPMULUDQrr + 0U, // VPOPCNTBZ128rm + 405U, // VPOPCNTBZ128rmk + 461U, // VPOPCNTBZ128rmkz + 0U, // VPOPCNTBZ128rr + 405U, // VPOPCNTBZ128rrk + 461U, // VPOPCNTBZ128rrkz + 0U, // VPOPCNTBZ256rm + 405U, // VPOPCNTBZ256rmk + 461U, // VPOPCNTBZ256rmkz + 0U, // VPOPCNTBZ256rr + 405U, // VPOPCNTBZ256rrk + 461U, // VPOPCNTBZ256rrkz + 0U, // VPOPCNTBZrm + 405U, // VPOPCNTBZrmk + 461U, // VPOPCNTBZrmkz + 0U, // VPOPCNTBZrr + 405U, // VPOPCNTBZrrk + 461U, // VPOPCNTBZrrkz + 0U, // VPOPCNTDZ128rm + 0U, // VPOPCNTDZ128rmb + 3356U, // VPOPCNTDZ128rmbk + 4444U, // VPOPCNTDZ128rmbkz + 405U, // VPOPCNTDZ128rmk + 461U, // VPOPCNTDZ128rmkz + 0U, // VPOPCNTDZ128rr + 405U, // VPOPCNTDZ128rrk + 461U, // VPOPCNTDZ128rrkz + 0U, // VPOPCNTDZ256rm + 0U, // VPOPCNTDZ256rmb + 3356U, // VPOPCNTDZ256rmbk + 4444U, // VPOPCNTDZ256rmbkz + 405U, // VPOPCNTDZ256rmk + 461U, // VPOPCNTDZ256rmkz + 0U, // VPOPCNTDZ256rr + 405U, // VPOPCNTDZ256rrk + 461U, // VPOPCNTDZ256rrkz + 0U, // VPOPCNTDZrm + 0U, // VPOPCNTDZrmb + 3356U, // VPOPCNTDZrmbk + 4444U, // VPOPCNTDZrmbkz + 405U, // VPOPCNTDZrmk + 461U, // VPOPCNTDZrmkz + 0U, // VPOPCNTDZrr + 405U, // VPOPCNTDZrrk + 461U, // VPOPCNTDZrrkz + 0U, // VPOPCNTQZ128rm + 0U, // VPOPCNTQZ128rmb + 3356U, // VPOPCNTQZ128rmbk + 4444U, // VPOPCNTQZ128rmbkz + 405U, // VPOPCNTQZ128rmk + 461U, // VPOPCNTQZ128rmkz + 0U, // VPOPCNTQZ128rr + 405U, // VPOPCNTQZ128rrk + 461U, // VPOPCNTQZ128rrkz + 0U, // VPOPCNTQZ256rm + 0U, // VPOPCNTQZ256rmb + 3356U, // VPOPCNTQZ256rmbk + 4444U, // VPOPCNTQZ256rmbkz + 405U, // VPOPCNTQZ256rmk + 461U, // VPOPCNTQZ256rmkz + 0U, // VPOPCNTQZ256rr + 405U, // VPOPCNTQZ256rrk + 461U, // VPOPCNTQZ256rrkz + 0U, // VPOPCNTQZrm + 0U, // VPOPCNTQZrmb + 3356U, // VPOPCNTQZrmbk + 4444U, // VPOPCNTQZrmbkz + 405U, // VPOPCNTQZrmk + 461U, // VPOPCNTQZrmkz + 0U, // VPOPCNTQZrr + 405U, // VPOPCNTQZrrk + 461U, // VPOPCNTQZrrkz + 0U, // VPOPCNTWZ128rm + 405U, // VPOPCNTWZ128rmk + 461U, // VPOPCNTWZ128rmkz + 0U, // VPOPCNTWZ128rr + 405U, // VPOPCNTWZ128rrk + 461U, // VPOPCNTWZ128rrkz + 0U, // VPOPCNTWZ256rm + 405U, // VPOPCNTWZ256rmk + 461U, // VPOPCNTWZ256rmkz + 0U, // VPOPCNTWZ256rr + 405U, // VPOPCNTWZ256rrk + 461U, // VPOPCNTWZ256rrkz + 0U, // VPOPCNTWZrm + 405U, // VPOPCNTWZrmk + 461U, // VPOPCNTWZrmkz + 0U, // VPOPCNTWZrr + 405U, // VPOPCNTWZrrk + 461U, // VPOPCNTWZrrkz + 4U, // VPORDZ128rm + 72U, // VPORDZ128rmb + 133U, // VPORDZ128rmbk + 9348U, // VPORDZ128rmbkz + 132U, // VPORDZ128rmk + 9348U, // VPORDZ128rmkz + 4U, // VPORDZ128rr + 0U, // VPORDZ128rrk + 9348U, // VPORDZ128rrkz + 4U, // VPORDZ256rm + 72U, // VPORDZ256rmb + 133U, // VPORDZ256rmbk + 9348U, // VPORDZ256rmbkz + 132U, // VPORDZ256rmk + 9348U, // VPORDZ256rmkz + 4U, // VPORDZ256rr + 0U, // VPORDZ256rrk + 9348U, // VPORDZ256rrkz + 4U, // VPORDZrm + 72U, // VPORDZrmb + 133U, // VPORDZrmbk + 9348U, // VPORDZrmbkz + 132U, // VPORDZrmk + 9348U, // VPORDZrmkz + 4U, // VPORDZrr + 0U, // VPORDZrrk + 9348U, // VPORDZrrkz + 4U, // VPORQZ128rm + 72U, // VPORQZ128rmb + 133U, // VPORQZ128rmbk + 9348U, // VPORQZ128rmbkz + 132U, // VPORQZ128rmk + 9348U, // VPORQZ128rmkz + 4U, // VPORQZ128rr + 0U, // VPORQZ128rrk + 9348U, // VPORQZ128rrkz + 4U, // VPORQZ256rm + 72U, // VPORQZ256rmb + 133U, // VPORQZ256rmbk + 9348U, // VPORQZ256rmbkz + 132U, // VPORQZ256rmk + 9348U, // VPORQZ256rmkz + 4U, // VPORQZ256rr + 0U, // VPORQZ256rrk + 9348U, // VPORQZ256rrkz + 4U, // VPORQZrm + 72U, // VPORQZrmb + 133U, // VPORQZrmbk + 9348U, // VPORQZrmbkz + 132U, // VPORQZrmk + 9348U, // VPORQZrmkz + 4U, // VPORQZrr + 0U, // VPORQZrrk + 9348U, // VPORQZrrkz + 4U, // VPORYrm + 4U, // VPORYrr + 4U, // VPORrm + 4U, // VPORrr + 72U, // VPPERMrmr + 18636U, // VPPERMrrm + 18636U, // VPPERMrrr + 18636U, // VPPERMrrr_REV + 5U, // VPROLDZ128mbi + 133U, // VPROLDZ128mbik + 9349U, // VPROLDZ128mbikz + 4U, // VPROLDZ128mi + 3356U, // VPROLDZ128mik + 4444U, // VPROLDZ128mikz + 72U, // VPROLDZ128ri + 133U, // VPROLDZ128rik + 9348U, // VPROLDZ128rikz + 5U, // VPROLDZ256mbi + 133U, // VPROLDZ256mbik + 9349U, // VPROLDZ256mbikz + 4U, // VPROLDZ256mi + 3356U, // VPROLDZ256mik + 4444U, // VPROLDZ256mikz + 72U, // VPROLDZ256ri + 133U, // VPROLDZ256rik + 9348U, // VPROLDZ256rikz + 5U, // VPROLDZmbi + 133U, // VPROLDZmbik + 9349U, // VPROLDZmbikz + 4U, // VPROLDZmi + 3356U, // VPROLDZmik + 4444U, // VPROLDZmikz + 72U, // VPROLDZri + 133U, // VPROLDZrik + 9348U, // VPROLDZrikz + 5U, // VPROLQZ128mbi + 133U, // VPROLQZ128mbik + 9349U, // VPROLQZ128mbikz + 4U, // VPROLQZ128mi + 3356U, // VPROLQZ128mik + 4444U, // VPROLQZ128mikz + 72U, // VPROLQZ128ri + 133U, // VPROLQZ128rik + 9348U, // VPROLQZ128rikz + 5U, // VPROLQZ256mbi + 133U, // VPROLQZ256mbik + 9349U, // VPROLQZ256mbikz + 4U, // VPROLQZ256mi + 3356U, // VPROLQZ256mik + 4444U, // VPROLQZ256mikz + 72U, // VPROLQZ256ri + 133U, // VPROLQZ256rik + 9348U, // VPROLQZ256rikz + 5U, // VPROLQZmbi + 133U, // VPROLQZmbik + 9349U, // VPROLQZmbikz + 4U, // VPROLQZmi + 3356U, // VPROLQZmik + 4444U, // VPROLQZmikz + 72U, // VPROLQZri + 133U, // VPROLQZrik + 9348U, // VPROLQZrikz + 4U, // VPROLVDZ128rm + 72U, // VPROLVDZ128rmb + 133U, // VPROLVDZ128rmbk + 9348U, // VPROLVDZ128rmbkz + 132U, // VPROLVDZ128rmk + 9348U, // VPROLVDZ128rmkz + 4U, // VPROLVDZ128rr + 0U, // VPROLVDZ128rrk + 9348U, // VPROLVDZ128rrkz + 4U, // VPROLVDZ256rm + 72U, // VPROLVDZ256rmb + 133U, // VPROLVDZ256rmbk + 9348U, // VPROLVDZ256rmbkz + 132U, // VPROLVDZ256rmk + 9348U, // VPROLVDZ256rmkz + 4U, // VPROLVDZ256rr + 0U, // VPROLVDZ256rrk + 9348U, // VPROLVDZ256rrkz + 4U, // VPROLVDZrm + 72U, // VPROLVDZrmb + 133U, // VPROLVDZrmbk + 9348U, // VPROLVDZrmbkz + 132U, // VPROLVDZrmk + 9348U, // VPROLVDZrmkz + 4U, // VPROLVDZrr + 0U, // VPROLVDZrrk + 9348U, // VPROLVDZrrkz + 4U, // VPROLVQZ128rm + 72U, // VPROLVQZ128rmb + 133U, // VPROLVQZ128rmbk + 9348U, // VPROLVQZ128rmbkz + 132U, // VPROLVQZ128rmk + 9348U, // VPROLVQZ128rmkz + 4U, // VPROLVQZ128rr + 0U, // VPROLVQZ128rrk + 9348U, // VPROLVQZ128rrkz + 4U, // VPROLVQZ256rm + 72U, // VPROLVQZ256rmb + 133U, // VPROLVQZ256rmbk + 9348U, // VPROLVQZ256rmbkz + 132U, // VPROLVQZ256rmk + 9348U, // VPROLVQZ256rmkz + 4U, // VPROLVQZ256rr + 0U, // VPROLVQZ256rrk + 9348U, // VPROLVQZ256rrkz + 4U, // VPROLVQZrm + 72U, // VPROLVQZrmb + 133U, // VPROLVQZrmbk + 9348U, // VPROLVQZrmbkz + 132U, // VPROLVQZrmk + 9348U, // VPROLVQZrmkz + 4U, // VPROLVQZrr + 0U, // VPROLVQZrrk + 9348U, // VPROLVQZrrkz + 5U, // VPRORDZ128mbi + 133U, // VPRORDZ128mbik + 9349U, // VPRORDZ128mbikz + 4U, // VPRORDZ128mi + 3356U, // VPRORDZ128mik + 4444U, // VPRORDZ128mikz + 72U, // VPRORDZ128ri + 133U, // VPRORDZ128rik + 9348U, // VPRORDZ128rikz + 5U, // VPRORDZ256mbi + 133U, // VPRORDZ256mbik + 9349U, // VPRORDZ256mbikz + 4U, // VPRORDZ256mi + 3356U, // VPRORDZ256mik + 4444U, // VPRORDZ256mikz + 72U, // VPRORDZ256ri + 133U, // VPRORDZ256rik + 9348U, // VPRORDZ256rikz + 5U, // VPRORDZmbi + 133U, // VPRORDZmbik + 9349U, // VPRORDZmbikz + 4U, // VPRORDZmi + 3356U, // VPRORDZmik + 4444U, // VPRORDZmikz + 72U, // VPRORDZri + 133U, // VPRORDZrik + 9348U, // VPRORDZrikz + 5U, // VPRORQZ128mbi + 133U, // VPRORQZ128mbik + 9349U, // VPRORQZ128mbikz + 4U, // VPRORQZ128mi + 3356U, // VPRORQZ128mik + 4444U, // VPRORQZ128mikz + 72U, // VPRORQZ128ri + 133U, // VPRORQZ128rik + 9348U, // VPRORQZ128rikz + 5U, // VPRORQZ256mbi + 133U, // VPRORQZ256mbik + 9349U, // VPRORQZ256mbikz + 4U, // VPRORQZ256mi + 3356U, // VPRORQZ256mik + 4444U, // VPRORQZ256mikz + 72U, // VPRORQZ256ri + 133U, // VPRORQZ256rik + 9348U, // VPRORQZ256rikz + 5U, // VPRORQZmbi + 133U, // VPRORQZmbik + 9349U, // VPRORQZmbikz + 4U, // VPRORQZmi + 3356U, // VPRORQZmik + 4444U, // VPRORQZmikz + 72U, // VPRORQZri + 133U, // VPRORQZrik + 9348U, // VPRORQZrikz + 4U, // VPRORVDZ128rm + 72U, // VPRORVDZ128rmb + 133U, // VPRORVDZ128rmbk + 9348U, // VPRORVDZ128rmbkz + 132U, // VPRORVDZ128rmk + 9348U, // VPRORVDZ128rmkz + 4U, // VPRORVDZ128rr + 0U, // VPRORVDZ128rrk + 9348U, // VPRORVDZ128rrkz + 4U, // VPRORVDZ256rm + 72U, // VPRORVDZ256rmb + 133U, // VPRORVDZ256rmbk + 9348U, // VPRORVDZ256rmbkz + 132U, // VPRORVDZ256rmk + 9348U, // VPRORVDZ256rmkz + 4U, // VPRORVDZ256rr + 0U, // VPRORVDZ256rrk + 9348U, // VPRORVDZ256rrkz + 4U, // VPRORVDZrm + 72U, // VPRORVDZrmb + 133U, // VPRORVDZrmbk + 9348U, // VPRORVDZrmbkz + 132U, // VPRORVDZrmk + 9348U, // VPRORVDZrmkz + 4U, // VPRORVDZrr + 0U, // VPRORVDZrrk + 9348U, // VPRORVDZrrkz + 4U, // VPRORVQZ128rm + 72U, // VPRORVQZ128rmb + 133U, // VPRORVQZ128rmbk + 9348U, // VPRORVQZ128rmbkz + 132U, // VPRORVQZ128rmk + 9348U, // VPRORVQZ128rmkz + 4U, // VPRORVQZ128rr + 0U, // VPRORVQZ128rrk + 9348U, // VPRORVQZ128rrkz + 4U, // VPRORVQZ256rm + 72U, // VPRORVQZ256rmb + 133U, // VPRORVQZ256rmbk + 9348U, // VPRORVQZ256rmbkz + 132U, // VPRORVQZ256rmk + 9348U, // VPRORVQZ256rmkz + 4U, // VPRORVQZ256rr + 0U, // VPRORVQZ256rrk + 9348U, // VPRORVQZ256rrkz + 4U, // VPRORVQZrm + 72U, // VPRORVQZrmb + 133U, // VPRORVQZrmbk + 9348U, // VPRORVQZrmbkz + 132U, // VPRORVQZrmk + 9348U, // VPRORVQZrmkz + 4U, // VPRORVQZrr + 0U, // VPRORVQZrrk + 9348U, // VPRORVQZrrkz + 4U, // VPROTBmi + 4U, // VPROTBmr + 72U, // VPROTBri + 4U, // VPROTBrm + 4U, // VPROTBrr + 4U, // VPROTBrr_REV + 4U, // VPROTDmi + 4U, // VPROTDmr + 72U, // VPROTDri + 4U, // VPROTDrm + 4U, // VPROTDrr + 4U, // VPROTDrr_REV + 4U, // VPROTQmi + 4U, // VPROTQmr + 72U, // VPROTQri + 4U, // VPROTQrm + 4U, // VPROTQrr + 4U, // VPROTQrr_REV + 4U, // VPROTWmi + 4U, // VPROTWmr + 72U, // VPROTWri + 4U, // VPROTWrm + 4U, // VPROTWrr + 4U, // VPROTWrr_REV + 4U, // VPSADBWYrm + 4U, // VPSADBWYrr + 4U, // VPSADBWZ128rm + 4U, // VPSADBWZ128rr + 4U, // VPSADBWZ256rm + 4U, // VPSADBWZ256rr + 4U, // VPSADBWZrm + 4U, // VPSADBWZrr + 4U, // VPSADBWrm + 4U, // VPSADBWrr + 57U, // VPSCATTERDDZ128mr + 57U, // VPSCATTERDDZ256mr + 57U, // VPSCATTERDDZmr + 57U, // VPSCATTERDQZ128mr + 57U, // VPSCATTERDQZ256mr + 57U, // VPSCATTERDQZmr + 57U, // VPSCATTERQDZ128mr + 57U, // VPSCATTERQDZ256mr + 57U, // VPSCATTERQDZmr + 57U, // VPSCATTERQQZ128mr + 57U, // VPSCATTERQQZ256mr + 57U, // VPSCATTERQQZmr + 4U, // VPSHABmr + 4U, // VPSHABrm + 4U, // VPSHABrr + 4U, // VPSHABrr_REV + 4U, // VPSHADmr + 4U, // VPSHADrm + 4U, // VPSHADrr + 4U, // VPSHADrr_REV + 4U, // VPSHAQmr + 4U, // VPSHAQrm + 4U, // VPSHAQrr + 4U, // VPSHAQrr_REV + 4U, // VPSHAWmr + 4U, // VPSHAWrm + 4U, // VPSHAWrr + 4U, // VPSHAWrr_REV + 4U, // VPSHLBmr + 4U, // VPSHLBrm + 4U, // VPSHLBrr + 4U, // VPSHLBrr_REV + 18637U, // VPSHLDDZ128rmbi + 26833U, // VPSHLDDZ128rmbik + 26837U, // VPSHLDDZ128rmbikz + 72U, // VPSHLDDZ128rmi + 1U, // VPSHLDDZ128rmik + 9348U, // VPSHLDDZ128rmikz + 18636U, // VPSHLDDZ128rri + 25U, // VPSHLDDZ128rrik + 26837U, // VPSHLDDZ128rrikz + 18637U, // VPSHLDDZ256rmbi + 26833U, // VPSHLDDZ256rmbik + 26837U, // VPSHLDDZ256rmbikz + 72U, // VPSHLDDZ256rmi + 1U, // VPSHLDDZ256rmik + 9348U, // VPSHLDDZ256rmikz + 18636U, // VPSHLDDZ256rri + 25U, // VPSHLDDZ256rrik + 26837U, // VPSHLDDZ256rrikz + 18637U, // VPSHLDDZrmbi + 26833U, // VPSHLDDZrmbik + 26837U, // VPSHLDDZrmbikz + 72U, // VPSHLDDZrmi + 1U, // VPSHLDDZrmik + 9348U, // VPSHLDDZrmikz + 18636U, // VPSHLDDZrri + 25U, // VPSHLDDZrrik + 26837U, // VPSHLDDZrrikz + 18637U, // VPSHLDQZ128rmbi + 26833U, // VPSHLDQZ128rmbik + 26837U, // VPSHLDQZ128rmbikz + 72U, // VPSHLDQZ128rmi + 1U, // VPSHLDQZ128rmik + 9348U, // VPSHLDQZ128rmikz + 18636U, // VPSHLDQZ128rri + 25U, // VPSHLDQZ128rrik + 26837U, // VPSHLDQZ128rrikz + 18637U, // VPSHLDQZ256rmbi + 26833U, // VPSHLDQZ256rmbik + 26837U, // VPSHLDQZ256rmbikz + 72U, // VPSHLDQZ256rmi + 1U, // VPSHLDQZ256rmik + 9348U, // VPSHLDQZ256rmikz + 18636U, // VPSHLDQZ256rri + 25U, // VPSHLDQZ256rrik + 26837U, // VPSHLDQZ256rrikz + 18637U, // VPSHLDQZrmbi + 26833U, // VPSHLDQZrmbik + 26837U, // VPSHLDQZrmbikz + 72U, // VPSHLDQZrmi + 1U, // VPSHLDQZrmik + 9348U, // VPSHLDQZrmikz + 18636U, // VPSHLDQZrri + 25U, // VPSHLDQZrrik + 26837U, // VPSHLDQZrrikz + 4U, // VPSHLDVDZ128m + 4U, // VPSHLDVDZ128mb + 133U, // VPSHLDVDZ128mbk + 8325U, // VPSHLDVDZ128mbkz + 132U, // VPSHLDVDZ128mk + 8324U, // VPSHLDVDZ128mkz + 4U, // VPSHLDVDZ128r + 0U, // VPSHLDVDZ128rk + 0U, // VPSHLDVDZ128rkz + 4U, // VPSHLDVDZ256m + 4U, // VPSHLDVDZ256mb + 133U, // VPSHLDVDZ256mbk + 8325U, // VPSHLDVDZ256mbkz + 132U, // VPSHLDVDZ256mk + 8324U, // VPSHLDVDZ256mkz + 4U, // VPSHLDVDZ256r + 0U, // VPSHLDVDZ256rk + 0U, // VPSHLDVDZ256rkz + 4U, // VPSHLDVDZm + 4U, // VPSHLDVDZmb + 133U, // VPSHLDVDZmbk + 8325U, // VPSHLDVDZmbkz + 132U, // VPSHLDVDZmk + 8324U, // VPSHLDVDZmkz + 4U, // VPSHLDVDZr + 0U, // VPSHLDVDZrk + 0U, // VPSHLDVDZrkz + 4U, // VPSHLDVQZ128m + 4U, // VPSHLDVQZ128mb + 133U, // VPSHLDVQZ128mbk + 8325U, // VPSHLDVQZ128mbkz + 132U, // VPSHLDVQZ128mk + 8324U, // VPSHLDVQZ128mkz + 4U, // VPSHLDVQZ128r + 0U, // VPSHLDVQZ128rk + 0U, // VPSHLDVQZ128rkz + 4U, // VPSHLDVQZ256m + 4U, // VPSHLDVQZ256mb + 133U, // VPSHLDVQZ256mbk + 8325U, // VPSHLDVQZ256mbkz + 132U, // VPSHLDVQZ256mk + 8324U, // VPSHLDVQZ256mkz + 4U, // VPSHLDVQZ256r + 0U, // VPSHLDVQZ256rk + 0U, // VPSHLDVQZ256rkz + 4U, // VPSHLDVQZm + 4U, // VPSHLDVQZmb + 133U, // VPSHLDVQZmbk + 8325U, // VPSHLDVQZmbkz + 132U, // VPSHLDVQZmk + 8324U, // VPSHLDVQZmkz + 4U, // VPSHLDVQZr + 0U, // VPSHLDVQZrk + 0U, // VPSHLDVQZrkz + 4U, // VPSHLDVWZ128m + 132U, // VPSHLDVWZ128mk + 8324U, // VPSHLDVWZ128mkz + 4U, // VPSHLDVWZ128r + 0U, // VPSHLDVWZ128rk + 0U, // VPSHLDVWZ128rkz + 4U, // VPSHLDVWZ256m + 132U, // VPSHLDVWZ256mk + 8324U, // VPSHLDVWZ256mkz + 4U, // VPSHLDVWZ256r + 0U, // VPSHLDVWZ256rk + 0U, // VPSHLDVWZ256rkz + 4U, // VPSHLDVWZm + 132U, // VPSHLDVWZmk + 8324U, // VPSHLDVWZmkz + 4U, // VPSHLDVWZr + 0U, // VPSHLDVWZrk + 0U, // VPSHLDVWZrkz + 72U, // VPSHLDWZ128rmi + 1U, // VPSHLDWZ128rmik + 9348U, // VPSHLDWZ128rmikz + 18636U, // VPSHLDWZ128rri + 25U, // VPSHLDWZ128rrik + 26837U, // VPSHLDWZ128rrikz + 72U, // VPSHLDWZ256rmi + 1U, // VPSHLDWZ256rmik + 9348U, // VPSHLDWZ256rmikz + 18636U, // VPSHLDWZ256rri + 25U, // VPSHLDWZ256rrik + 26837U, // VPSHLDWZ256rrikz + 72U, // VPSHLDWZrmi + 1U, // VPSHLDWZrmik + 9348U, // VPSHLDWZrmikz + 18636U, // VPSHLDWZrri + 25U, // VPSHLDWZrrik + 26837U, // VPSHLDWZrrikz + 4U, // VPSHLDmr + 4U, // VPSHLDrm + 4U, // VPSHLDrr + 4U, // VPSHLDrr_REV + 4U, // VPSHLQmr + 4U, // VPSHLQrm + 4U, // VPSHLQrr + 4U, // VPSHLQrr_REV + 4U, // VPSHLWmr + 4U, // VPSHLWrm + 4U, // VPSHLWrr + 4U, // VPSHLWrr_REV + 18637U, // VPSHRDDZ128rmbi + 26833U, // VPSHRDDZ128rmbik + 26837U, // VPSHRDDZ128rmbikz + 72U, // VPSHRDDZ128rmi + 1U, // VPSHRDDZ128rmik + 9348U, // VPSHRDDZ128rmikz + 18636U, // VPSHRDDZ128rri + 25U, // VPSHRDDZ128rrik + 26837U, // VPSHRDDZ128rrikz + 18637U, // VPSHRDDZ256rmbi + 26833U, // VPSHRDDZ256rmbik + 26837U, // VPSHRDDZ256rmbikz + 72U, // VPSHRDDZ256rmi + 1U, // VPSHRDDZ256rmik + 9348U, // VPSHRDDZ256rmikz + 18636U, // VPSHRDDZ256rri + 25U, // VPSHRDDZ256rrik + 26837U, // VPSHRDDZ256rrikz + 18637U, // VPSHRDDZrmbi + 26833U, // VPSHRDDZrmbik + 26837U, // VPSHRDDZrmbikz + 72U, // VPSHRDDZrmi + 1U, // VPSHRDDZrmik + 9348U, // VPSHRDDZrmikz + 18636U, // VPSHRDDZrri + 25U, // VPSHRDDZrrik + 26837U, // VPSHRDDZrrikz + 18637U, // VPSHRDQZ128rmbi + 26833U, // VPSHRDQZ128rmbik + 26837U, // VPSHRDQZ128rmbikz + 72U, // VPSHRDQZ128rmi + 1U, // VPSHRDQZ128rmik + 9348U, // VPSHRDQZ128rmikz + 18636U, // VPSHRDQZ128rri + 25U, // VPSHRDQZ128rrik + 26837U, // VPSHRDQZ128rrikz + 18637U, // VPSHRDQZ256rmbi + 26833U, // VPSHRDQZ256rmbik + 26837U, // VPSHRDQZ256rmbikz + 72U, // VPSHRDQZ256rmi + 1U, // VPSHRDQZ256rmik + 9348U, // VPSHRDQZ256rmikz + 18636U, // VPSHRDQZ256rri + 25U, // VPSHRDQZ256rrik + 26837U, // VPSHRDQZ256rrikz + 18637U, // VPSHRDQZrmbi + 26833U, // VPSHRDQZrmbik + 26837U, // VPSHRDQZrmbikz + 72U, // VPSHRDQZrmi + 1U, // VPSHRDQZrmik + 9348U, // VPSHRDQZrmikz + 18636U, // VPSHRDQZrri + 25U, // VPSHRDQZrrik + 26837U, // VPSHRDQZrrikz + 4U, // VPSHRDVDZ128m + 4U, // VPSHRDVDZ128mb + 133U, // VPSHRDVDZ128mbk + 8325U, // VPSHRDVDZ128mbkz + 132U, // VPSHRDVDZ128mk + 8324U, // VPSHRDVDZ128mkz + 4U, // VPSHRDVDZ128r + 0U, // VPSHRDVDZ128rk + 0U, // VPSHRDVDZ128rkz + 4U, // VPSHRDVDZ256m + 4U, // VPSHRDVDZ256mb + 133U, // VPSHRDVDZ256mbk + 8325U, // VPSHRDVDZ256mbkz + 132U, // VPSHRDVDZ256mk + 8324U, // VPSHRDVDZ256mkz + 4U, // VPSHRDVDZ256r + 0U, // VPSHRDVDZ256rk + 0U, // VPSHRDVDZ256rkz + 4U, // VPSHRDVDZm + 4U, // VPSHRDVDZmb + 133U, // VPSHRDVDZmbk + 8325U, // VPSHRDVDZmbkz + 132U, // VPSHRDVDZmk + 8324U, // VPSHRDVDZmkz + 4U, // VPSHRDVDZr + 0U, // VPSHRDVDZrk + 0U, // VPSHRDVDZrkz + 4U, // VPSHRDVQZ128m + 4U, // VPSHRDVQZ128mb + 133U, // VPSHRDVQZ128mbk + 8325U, // VPSHRDVQZ128mbkz + 132U, // VPSHRDVQZ128mk + 8324U, // VPSHRDVQZ128mkz + 4U, // VPSHRDVQZ128r + 0U, // VPSHRDVQZ128rk + 0U, // VPSHRDVQZ128rkz + 4U, // VPSHRDVQZ256m + 4U, // VPSHRDVQZ256mb + 133U, // VPSHRDVQZ256mbk + 8325U, // VPSHRDVQZ256mbkz + 132U, // VPSHRDVQZ256mk + 8324U, // VPSHRDVQZ256mkz + 4U, // VPSHRDVQZ256r + 0U, // VPSHRDVQZ256rk + 0U, // VPSHRDVQZ256rkz + 4U, // VPSHRDVQZm + 4U, // VPSHRDVQZmb + 133U, // VPSHRDVQZmbk + 8325U, // VPSHRDVQZmbkz + 132U, // VPSHRDVQZmk + 8324U, // VPSHRDVQZmkz + 4U, // VPSHRDVQZr + 0U, // VPSHRDVQZrk + 0U, // VPSHRDVQZrkz + 4U, // VPSHRDVWZ128m + 132U, // VPSHRDVWZ128mk + 8324U, // VPSHRDVWZ128mkz + 4U, // VPSHRDVWZ128r + 0U, // VPSHRDVWZ128rk + 0U, // VPSHRDVWZ128rkz + 4U, // VPSHRDVWZ256m + 132U, // VPSHRDVWZ256mk + 8324U, // VPSHRDVWZ256mkz + 4U, // VPSHRDVWZ256r + 0U, // VPSHRDVWZ256rk + 0U, // VPSHRDVWZ256rkz + 4U, // VPSHRDVWZm + 132U, // VPSHRDVWZmk + 8324U, // VPSHRDVWZmkz + 4U, // VPSHRDVWZr + 0U, // VPSHRDVWZrk + 0U, // VPSHRDVWZrkz + 72U, // VPSHRDWZ128rmi + 1U, // VPSHRDWZ128rmik + 9348U, // VPSHRDWZ128rmikz + 18636U, // VPSHRDWZ128rri + 25U, // VPSHRDWZ128rrik + 26837U, // VPSHRDWZ128rrikz + 72U, // VPSHRDWZ256rmi + 1U, // VPSHRDWZ256rmik + 9348U, // VPSHRDWZ256rmikz + 18636U, // VPSHRDWZ256rri + 25U, // VPSHRDWZ256rrik + 26837U, // VPSHRDWZ256rrikz + 72U, // VPSHRDWZrmi + 1U, // VPSHRDWZrmik + 9348U, // VPSHRDWZrmikz + 18636U, // VPSHRDWZrri + 25U, // VPSHRDWZrrik + 26837U, // VPSHRDWZrrikz + 4U, // VPSHUFBITQMBZ128rm + 1156U, // VPSHUFBITQMBZ128rmk + 4U, // VPSHUFBITQMBZ128rr + 1156U, // VPSHUFBITQMBZ128rrk + 4U, // VPSHUFBITQMBZ256rm + 1156U, // VPSHUFBITQMBZ256rmk + 4U, // VPSHUFBITQMBZ256rr + 1156U, // VPSHUFBITQMBZ256rrk + 4U, // VPSHUFBITQMBZrm + 1156U, // VPSHUFBITQMBZrmk + 4U, // VPSHUFBITQMBZrr + 1156U, // VPSHUFBITQMBZrrk + 4U, // VPSHUFBYrm + 4U, // VPSHUFBYrr + 4U, // VPSHUFBZ128rm + 132U, // VPSHUFBZ128rmk + 9348U, // VPSHUFBZ128rmkz + 4U, // VPSHUFBZ128rr + 0U, // VPSHUFBZ128rrk + 9348U, // VPSHUFBZ128rrkz + 4U, // VPSHUFBZ256rm + 132U, // VPSHUFBZ256rmk + 9348U, // VPSHUFBZ256rmkz + 4U, // VPSHUFBZ256rr + 0U, // VPSHUFBZ256rrk + 9348U, // VPSHUFBZ256rrkz + 4U, // VPSHUFBZrm + 132U, // VPSHUFBZrmk + 9348U, // VPSHUFBZrmkz + 4U, // VPSHUFBZrr + 0U, // VPSHUFBZrrk + 9348U, // VPSHUFBZrrkz + 4U, // VPSHUFBrm + 4U, // VPSHUFBrr + 4U, // VPSHUFDYmi + 72U, // VPSHUFDYri + 5U, // VPSHUFDZ128mbi + 133U, // VPSHUFDZ128mbik + 9349U, // VPSHUFDZ128mbikz + 4U, // VPSHUFDZ128mi + 3356U, // VPSHUFDZ128mik + 4444U, // VPSHUFDZ128mikz + 72U, // VPSHUFDZ128ri + 133U, // VPSHUFDZ128rik + 9348U, // VPSHUFDZ128rikz + 5U, // VPSHUFDZ256mbi + 133U, // VPSHUFDZ256mbik + 9349U, // VPSHUFDZ256mbikz + 4U, // VPSHUFDZ256mi + 3356U, // VPSHUFDZ256mik + 4444U, // VPSHUFDZ256mikz + 72U, // VPSHUFDZ256ri + 133U, // VPSHUFDZ256rik + 9348U, // VPSHUFDZ256rikz + 5U, // VPSHUFDZmbi + 133U, // VPSHUFDZmbik + 9349U, // VPSHUFDZmbikz + 4U, // VPSHUFDZmi + 3356U, // VPSHUFDZmik + 4444U, // VPSHUFDZmikz + 72U, // VPSHUFDZri + 133U, // VPSHUFDZrik + 9348U, // VPSHUFDZrikz + 4U, // VPSHUFDmi + 72U, // VPSHUFDri + 4U, // VPSHUFHWYmi + 72U, // VPSHUFHWYri + 4U, // VPSHUFHWZ128mi + 3356U, // VPSHUFHWZ128mik + 4444U, // VPSHUFHWZ128mikz + 72U, // VPSHUFHWZ128ri + 133U, // VPSHUFHWZ128rik + 9348U, // VPSHUFHWZ128rikz + 4U, // VPSHUFHWZ256mi + 3356U, // VPSHUFHWZ256mik + 4444U, // VPSHUFHWZ256mikz + 72U, // VPSHUFHWZ256ri + 133U, // VPSHUFHWZ256rik + 9348U, // VPSHUFHWZ256rikz + 4U, // VPSHUFHWZmi + 3356U, // VPSHUFHWZmik + 4444U, // VPSHUFHWZmikz + 72U, // VPSHUFHWZri + 133U, // VPSHUFHWZrik + 9348U, // VPSHUFHWZrikz + 4U, // VPSHUFHWmi + 72U, // VPSHUFHWri + 4U, // VPSHUFLWYmi + 72U, // VPSHUFLWYri + 4U, // VPSHUFLWZ128mi + 3356U, // VPSHUFLWZ128mik + 4444U, // VPSHUFLWZ128mikz + 72U, // VPSHUFLWZ128ri + 133U, // VPSHUFLWZ128rik + 9348U, // VPSHUFLWZ128rikz + 4U, // VPSHUFLWZ256mi + 3356U, // VPSHUFLWZ256mik + 4444U, // VPSHUFLWZ256mikz + 72U, // VPSHUFLWZ256ri + 133U, // VPSHUFLWZ256rik + 9348U, // VPSHUFLWZ256rikz + 4U, // VPSHUFLWZmi + 3356U, // VPSHUFLWZmik + 4444U, // VPSHUFLWZmikz + 72U, // VPSHUFLWZri + 133U, // VPSHUFLWZrik + 9348U, // VPSHUFLWZrikz + 4U, // VPSHUFLWmi + 72U, // VPSHUFLWri + 4U, // VPSIGNBYrm + 4U, // VPSIGNBYrr + 4U, // VPSIGNBrm + 4U, // VPSIGNBrr + 4U, // VPSIGNDYrm + 4U, // VPSIGNDYrr + 4U, // VPSIGNDrm + 4U, // VPSIGNDrr + 4U, // VPSIGNWYrm + 4U, // VPSIGNWYrr + 4U, // VPSIGNWrm + 4U, // VPSIGNWrr + 72U, // VPSLLDQYri + 4U, // VPSLLDQZ128rm + 72U, // VPSLLDQZ128rr + 4U, // VPSLLDQZ256rm + 72U, // VPSLLDQZ256rr + 4U, // VPSLLDQZrm + 72U, // VPSLLDQZrr + 72U, // VPSLLDQri + 72U, // VPSLLDYri + 4U, // VPSLLDYrm + 4U, // VPSLLDYrr + 5U, // VPSLLDZ128mbi + 133U, // VPSLLDZ128mbik + 9349U, // VPSLLDZ128mbikz + 4U, // VPSLLDZ128mi + 3356U, // VPSLLDZ128mik + 4444U, // VPSLLDZ128mikz + 72U, // VPSLLDZ128ri + 133U, // VPSLLDZ128rik + 9348U, // VPSLLDZ128rikz + 4U, // VPSLLDZ128rm + 132U, // VPSLLDZ128rmk + 9348U, // VPSLLDZ128rmkz + 4U, // VPSLLDZ128rr + 0U, // VPSLLDZ128rrk + 9348U, // VPSLLDZ128rrkz + 5U, // VPSLLDZ256mbi + 133U, // VPSLLDZ256mbik + 9349U, // VPSLLDZ256mbikz + 4U, // VPSLLDZ256mi + 3356U, // VPSLLDZ256mik + 4444U, // VPSLLDZ256mikz + 72U, // VPSLLDZ256ri + 133U, // VPSLLDZ256rik + 9348U, // VPSLLDZ256rikz + 4U, // VPSLLDZ256rm + 132U, // VPSLLDZ256rmk + 9348U, // VPSLLDZ256rmkz + 4U, // VPSLLDZ256rr + 0U, // VPSLLDZ256rrk + 9348U, // VPSLLDZ256rrkz + 5U, // VPSLLDZmbi + 133U, // VPSLLDZmbik + 9349U, // VPSLLDZmbikz + 4U, // VPSLLDZmi + 3356U, // VPSLLDZmik + 4444U, // VPSLLDZmikz + 72U, // VPSLLDZri + 133U, // VPSLLDZrik + 9348U, // VPSLLDZrikz + 4U, // VPSLLDZrm + 132U, // VPSLLDZrmk + 9348U, // VPSLLDZrmkz + 4U, // VPSLLDZrr + 0U, // VPSLLDZrrk + 9348U, // VPSLLDZrrkz + 72U, // VPSLLDri + 4U, // VPSLLDrm + 4U, // VPSLLDrr + 72U, // VPSLLQYri + 4U, // VPSLLQYrm + 4U, // VPSLLQYrr + 5U, // VPSLLQZ128mbi + 133U, // VPSLLQZ128mbik + 9349U, // VPSLLQZ128mbikz + 4U, // VPSLLQZ128mi + 3356U, // VPSLLQZ128mik + 4444U, // VPSLLQZ128mikz + 72U, // VPSLLQZ128ri + 133U, // VPSLLQZ128rik + 9348U, // VPSLLQZ128rikz + 4U, // VPSLLQZ128rm + 132U, // VPSLLQZ128rmk + 9348U, // VPSLLQZ128rmkz + 4U, // VPSLLQZ128rr + 0U, // VPSLLQZ128rrk + 9348U, // VPSLLQZ128rrkz + 5U, // VPSLLQZ256mbi + 133U, // VPSLLQZ256mbik + 9349U, // VPSLLQZ256mbikz + 4U, // VPSLLQZ256mi + 3356U, // VPSLLQZ256mik + 4444U, // VPSLLQZ256mikz + 72U, // VPSLLQZ256ri + 133U, // VPSLLQZ256rik + 9348U, // VPSLLQZ256rikz + 4U, // VPSLLQZ256rm + 132U, // VPSLLQZ256rmk + 9348U, // VPSLLQZ256rmkz + 4U, // VPSLLQZ256rr + 0U, // VPSLLQZ256rrk + 9348U, // VPSLLQZ256rrkz + 5U, // VPSLLQZmbi + 133U, // VPSLLQZmbik + 9349U, // VPSLLQZmbikz + 4U, // VPSLLQZmi + 3356U, // VPSLLQZmik + 4444U, // VPSLLQZmikz + 72U, // VPSLLQZri + 133U, // VPSLLQZrik + 9348U, // VPSLLQZrikz + 4U, // VPSLLQZrm + 132U, // VPSLLQZrmk + 9348U, // VPSLLQZrmkz + 4U, // VPSLLQZrr + 0U, // VPSLLQZrrk + 9348U, // VPSLLQZrrkz + 72U, // VPSLLQri + 4U, // VPSLLQrm + 4U, // VPSLLQrr + 4U, // VPSLLVDYrm + 4U, // VPSLLVDYrr + 4U, // VPSLLVDZ128rm + 72U, // VPSLLVDZ128rmb + 133U, // VPSLLVDZ128rmbk + 9348U, // VPSLLVDZ128rmbkz + 132U, // VPSLLVDZ128rmk + 9348U, // VPSLLVDZ128rmkz + 4U, // VPSLLVDZ128rr + 0U, // VPSLLVDZ128rrk + 9348U, // VPSLLVDZ128rrkz + 4U, // VPSLLVDZ256rm + 72U, // VPSLLVDZ256rmb + 133U, // VPSLLVDZ256rmbk + 9348U, // VPSLLVDZ256rmbkz + 132U, // VPSLLVDZ256rmk + 9348U, // VPSLLVDZ256rmkz + 4U, // VPSLLVDZ256rr + 0U, // VPSLLVDZ256rrk + 9348U, // VPSLLVDZ256rrkz + 4U, // VPSLLVDZrm + 72U, // VPSLLVDZrmb + 133U, // VPSLLVDZrmbk + 9348U, // VPSLLVDZrmbkz + 132U, // VPSLLVDZrmk + 9348U, // VPSLLVDZrmkz + 4U, // VPSLLVDZrr + 0U, // VPSLLVDZrrk + 9348U, // VPSLLVDZrrkz + 4U, // VPSLLVDrm + 4U, // VPSLLVDrr + 4U, // VPSLLVQYrm + 4U, // VPSLLVQYrr + 4U, // VPSLLVQZ128rm + 72U, // VPSLLVQZ128rmb + 133U, // VPSLLVQZ128rmbk + 9348U, // VPSLLVQZ128rmbkz + 132U, // VPSLLVQZ128rmk + 9348U, // VPSLLVQZ128rmkz + 4U, // VPSLLVQZ128rr + 0U, // VPSLLVQZ128rrk + 9348U, // VPSLLVQZ128rrkz + 4U, // VPSLLVQZ256rm + 72U, // VPSLLVQZ256rmb + 133U, // VPSLLVQZ256rmbk + 9348U, // VPSLLVQZ256rmbkz + 132U, // VPSLLVQZ256rmk + 9348U, // VPSLLVQZ256rmkz + 4U, // VPSLLVQZ256rr + 0U, // VPSLLVQZ256rrk + 9348U, // VPSLLVQZ256rrkz + 4U, // VPSLLVQZrm + 72U, // VPSLLVQZrmb + 133U, // VPSLLVQZrmbk + 9348U, // VPSLLVQZrmbkz + 132U, // VPSLLVQZrmk + 9348U, // VPSLLVQZrmkz + 4U, // VPSLLVQZrr + 0U, // VPSLLVQZrrk + 9348U, // VPSLLVQZrrkz + 4U, // VPSLLVQrm + 4U, // VPSLLVQrr + 4U, // VPSLLVWZ128rm + 132U, // VPSLLVWZ128rmk + 9348U, // VPSLLVWZ128rmkz + 4U, // VPSLLVWZ128rr + 0U, // VPSLLVWZ128rrk + 9348U, // VPSLLVWZ128rrkz + 4U, // VPSLLVWZ256rm + 132U, // VPSLLVWZ256rmk + 9348U, // VPSLLVWZ256rmkz + 4U, // VPSLLVWZ256rr + 0U, // VPSLLVWZ256rrk + 9348U, // VPSLLVWZ256rrkz + 4U, // VPSLLVWZrm + 132U, // VPSLLVWZrmk + 9348U, // VPSLLVWZrmkz + 4U, // VPSLLVWZrr + 0U, // VPSLLVWZrrk + 9348U, // VPSLLVWZrrkz + 72U, // VPSLLWYri + 4U, // VPSLLWYrm + 4U, // VPSLLWYrr + 4U, // VPSLLWZ128mi + 3356U, // VPSLLWZ128mik + 4444U, // VPSLLWZ128mikz + 72U, // VPSLLWZ128ri + 133U, // VPSLLWZ128rik + 9348U, // VPSLLWZ128rikz + 4U, // VPSLLWZ128rm + 132U, // VPSLLWZ128rmk + 9348U, // VPSLLWZ128rmkz + 4U, // VPSLLWZ128rr + 0U, // VPSLLWZ128rrk + 9348U, // VPSLLWZ128rrkz + 4U, // VPSLLWZ256mi + 3356U, // VPSLLWZ256mik + 4444U, // VPSLLWZ256mikz + 72U, // VPSLLWZ256ri + 133U, // VPSLLWZ256rik + 9348U, // VPSLLWZ256rikz + 4U, // VPSLLWZ256rm + 132U, // VPSLLWZ256rmk + 9348U, // VPSLLWZ256rmkz + 4U, // VPSLLWZ256rr + 0U, // VPSLLWZ256rrk + 9348U, // VPSLLWZ256rrkz + 4U, // VPSLLWZmi + 3356U, // VPSLLWZmik + 4444U, // VPSLLWZmikz + 72U, // VPSLLWZri + 133U, // VPSLLWZrik + 9348U, // VPSLLWZrikz + 4U, // VPSLLWZrm + 132U, // VPSLLWZrmk + 9348U, // VPSLLWZrmkz + 4U, // VPSLLWZrr + 0U, // VPSLLWZrrk + 9348U, // VPSLLWZrrkz + 72U, // VPSLLWri + 4U, // VPSLLWrm + 4U, // VPSLLWrr + 72U, // VPSRADYri + 4U, // VPSRADYrm + 4U, // VPSRADYrr + 5U, // VPSRADZ128mbi + 133U, // VPSRADZ128mbik + 9349U, // VPSRADZ128mbikz + 4U, // VPSRADZ128mi + 3356U, // VPSRADZ128mik + 4444U, // VPSRADZ128mikz + 72U, // VPSRADZ128ri + 133U, // VPSRADZ128rik + 9348U, // VPSRADZ128rikz + 4U, // VPSRADZ128rm + 132U, // VPSRADZ128rmk + 9348U, // VPSRADZ128rmkz + 4U, // VPSRADZ128rr + 0U, // VPSRADZ128rrk + 9348U, // VPSRADZ128rrkz + 5U, // VPSRADZ256mbi + 133U, // VPSRADZ256mbik + 9349U, // VPSRADZ256mbikz + 4U, // VPSRADZ256mi + 3356U, // VPSRADZ256mik + 4444U, // VPSRADZ256mikz + 72U, // VPSRADZ256ri + 133U, // VPSRADZ256rik + 9348U, // VPSRADZ256rikz + 4U, // VPSRADZ256rm + 132U, // VPSRADZ256rmk + 9348U, // VPSRADZ256rmkz + 4U, // VPSRADZ256rr + 0U, // VPSRADZ256rrk + 9348U, // VPSRADZ256rrkz + 5U, // VPSRADZmbi + 133U, // VPSRADZmbik + 9349U, // VPSRADZmbikz + 4U, // VPSRADZmi + 3356U, // VPSRADZmik + 4444U, // VPSRADZmikz + 72U, // VPSRADZri + 133U, // VPSRADZrik + 9348U, // VPSRADZrikz + 4U, // VPSRADZrm + 132U, // VPSRADZrmk + 9348U, // VPSRADZrmkz + 4U, // VPSRADZrr + 0U, // VPSRADZrrk + 9348U, // VPSRADZrrkz + 72U, // VPSRADri + 4U, // VPSRADrm + 4U, // VPSRADrr + 5U, // VPSRAQZ128mbi + 133U, // VPSRAQZ128mbik + 9349U, // VPSRAQZ128mbikz + 4U, // VPSRAQZ128mi + 3356U, // VPSRAQZ128mik + 4444U, // VPSRAQZ128mikz + 72U, // VPSRAQZ128ri + 133U, // VPSRAQZ128rik + 9348U, // VPSRAQZ128rikz + 4U, // VPSRAQZ128rm + 132U, // VPSRAQZ128rmk + 9348U, // VPSRAQZ128rmkz + 4U, // VPSRAQZ128rr + 0U, // VPSRAQZ128rrk + 9348U, // VPSRAQZ128rrkz + 5U, // VPSRAQZ256mbi + 133U, // VPSRAQZ256mbik + 9349U, // VPSRAQZ256mbikz + 4U, // VPSRAQZ256mi + 3356U, // VPSRAQZ256mik + 4444U, // VPSRAQZ256mikz + 72U, // VPSRAQZ256ri + 133U, // VPSRAQZ256rik + 9348U, // VPSRAQZ256rikz + 4U, // VPSRAQZ256rm + 132U, // VPSRAQZ256rmk + 9348U, // VPSRAQZ256rmkz + 4U, // VPSRAQZ256rr + 0U, // VPSRAQZ256rrk + 9348U, // VPSRAQZ256rrkz + 5U, // VPSRAQZmbi + 133U, // VPSRAQZmbik + 9349U, // VPSRAQZmbikz + 4U, // VPSRAQZmi + 3356U, // VPSRAQZmik + 4444U, // VPSRAQZmikz + 72U, // VPSRAQZri + 133U, // VPSRAQZrik + 9348U, // VPSRAQZrikz + 4U, // VPSRAQZrm + 132U, // VPSRAQZrmk + 9348U, // VPSRAQZrmkz + 4U, // VPSRAQZrr + 0U, // VPSRAQZrrk + 9348U, // VPSRAQZrrkz + 4U, // VPSRAVDYrm + 4U, // VPSRAVDYrr + 4U, // VPSRAVDZ128rm + 72U, // VPSRAVDZ128rmb + 133U, // VPSRAVDZ128rmbk + 9348U, // VPSRAVDZ128rmbkz + 132U, // VPSRAVDZ128rmk + 9348U, // VPSRAVDZ128rmkz + 4U, // VPSRAVDZ128rr + 0U, // VPSRAVDZ128rrk + 9348U, // VPSRAVDZ128rrkz + 4U, // VPSRAVDZ256rm + 72U, // VPSRAVDZ256rmb + 133U, // VPSRAVDZ256rmbk + 9348U, // VPSRAVDZ256rmbkz + 132U, // VPSRAVDZ256rmk + 9348U, // VPSRAVDZ256rmkz + 4U, // VPSRAVDZ256rr + 0U, // VPSRAVDZ256rrk + 9348U, // VPSRAVDZ256rrkz + 4U, // VPSRAVDZrm + 72U, // VPSRAVDZrmb + 133U, // VPSRAVDZrmbk + 9348U, // VPSRAVDZrmbkz + 132U, // VPSRAVDZrmk + 9348U, // VPSRAVDZrmkz + 4U, // VPSRAVDZrr + 0U, // VPSRAVDZrrk + 9348U, // VPSRAVDZrrkz + 4U, // VPSRAVDrm + 4U, // VPSRAVDrr + 4U, // VPSRAVQZ128rm + 72U, // VPSRAVQZ128rmb + 133U, // VPSRAVQZ128rmbk + 9348U, // VPSRAVQZ128rmbkz + 132U, // VPSRAVQZ128rmk + 9348U, // VPSRAVQZ128rmkz + 4U, // VPSRAVQZ128rr + 0U, // VPSRAVQZ128rrk + 9348U, // VPSRAVQZ128rrkz + 4U, // VPSRAVQZ256rm + 72U, // VPSRAVQZ256rmb + 133U, // VPSRAVQZ256rmbk + 9348U, // VPSRAVQZ256rmbkz + 132U, // VPSRAVQZ256rmk + 9348U, // VPSRAVQZ256rmkz + 4U, // VPSRAVQZ256rr + 0U, // VPSRAVQZ256rrk + 9348U, // VPSRAVQZ256rrkz + 4U, // VPSRAVQZrm + 72U, // VPSRAVQZrmb + 133U, // VPSRAVQZrmbk + 9348U, // VPSRAVQZrmbkz + 132U, // VPSRAVQZrmk + 9348U, // VPSRAVQZrmkz + 4U, // VPSRAVQZrr + 0U, // VPSRAVQZrrk + 9348U, // VPSRAVQZrrkz + 4U, // VPSRAVWZ128rm + 132U, // VPSRAVWZ128rmk + 9348U, // VPSRAVWZ128rmkz + 4U, // VPSRAVWZ128rr + 0U, // VPSRAVWZ128rrk + 9348U, // VPSRAVWZ128rrkz + 4U, // VPSRAVWZ256rm + 132U, // VPSRAVWZ256rmk + 9348U, // VPSRAVWZ256rmkz + 4U, // VPSRAVWZ256rr + 0U, // VPSRAVWZ256rrk + 9348U, // VPSRAVWZ256rrkz + 4U, // VPSRAVWZrm + 132U, // VPSRAVWZrmk + 9348U, // VPSRAVWZrmkz + 4U, // VPSRAVWZrr + 0U, // VPSRAVWZrrk + 9348U, // VPSRAVWZrrkz + 72U, // VPSRAWYri + 4U, // VPSRAWYrm + 4U, // VPSRAWYrr + 4U, // VPSRAWZ128mi + 3356U, // VPSRAWZ128mik + 4444U, // VPSRAWZ128mikz + 72U, // VPSRAWZ128ri + 133U, // VPSRAWZ128rik + 9348U, // VPSRAWZ128rikz + 4U, // VPSRAWZ128rm + 132U, // VPSRAWZ128rmk + 9348U, // VPSRAWZ128rmkz + 4U, // VPSRAWZ128rr + 0U, // VPSRAWZ128rrk + 9348U, // VPSRAWZ128rrkz + 4U, // VPSRAWZ256mi + 3356U, // VPSRAWZ256mik + 4444U, // VPSRAWZ256mikz + 72U, // VPSRAWZ256ri + 133U, // VPSRAWZ256rik + 9348U, // VPSRAWZ256rikz + 4U, // VPSRAWZ256rm + 132U, // VPSRAWZ256rmk + 9348U, // VPSRAWZ256rmkz + 4U, // VPSRAWZ256rr + 0U, // VPSRAWZ256rrk + 9348U, // VPSRAWZ256rrkz + 4U, // VPSRAWZmi + 3356U, // VPSRAWZmik + 4444U, // VPSRAWZmikz + 72U, // VPSRAWZri + 133U, // VPSRAWZrik + 9348U, // VPSRAWZrikz + 4U, // VPSRAWZrm + 132U, // VPSRAWZrmk + 9348U, // VPSRAWZrmkz + 4U, // VPSRAWZrr + 0U, // VPSRAWZrrk + 9348U, // VPSRAWZrrkz + 72U, // VPSRAWri + 4U, // VPSRAWrm + 4U, // VPSRAWrr + 72U, // VPSRLDQYri + 4U, // VPSRLDQZ128rm + 72U, // VPSRLDQZ128rr + 4U, // VPSRLDQZ256rm + 72U, // VPSRLDQZ256rr + 4U, // VPSRLDQZrm + 72U, // VPSRLDQZrr + 72U, // VPSRLDQri + 72U, // VPSRLDYri + 4U, // VPSRLDYrm + 4U, // VPSRLDYrr + 5U, // VPSRLDZ128mbi + 133U, // VPSRLDZ128mbik + 9349U, // VPSRLDZ128mbikz + 4U, // VPSRLDZ128mi + 3356U, // VPSRLDZ128mik + 4444U, // VPSRLDZ128mikz + 72U, // VPSRLDZ128ri + 133U, // VPSRLDZ128rik + 9348U, // VPSRLDZ128rikz + 4U, // VPSRLDZ128rm + 132U, // VPSRLDZ128rmk + 9348U, // VPSRLDZ128rmkz + 4U, // VPSRLDZ128rr + 0U, // VPSRLDZ128rrk + 9348U, // VPSRLDZ128rrkz + 5U, // VPSRLDZ256mbi + 133U, // VPSRLDZ256mbik + 9349U, // VPSRLDZ256mbikz + 4U, // VPSRLDZ256mi + 3356U, // VPSRLDZ256mik + 4444U, // VPSRLDZ256mikz + 72U, // VPSRLDZ256ri + 133U, // VPSRLDZ256rik + 9348U, // VPSRLDZ256rikz + 4U, // VPSRLDZ256rm + 132U, // VPSRLDZ256rmk + 9348U, // VPSRLDZ256rmkz + 4U, // VPSRLDZ256rr + 0U, // VPSRLDZ256rrk + 9348U, // VPSRLDZ256rrkz + 5U, // VPSRLDZmbi + 133U, // VPSRLDZmbik + 9349U, // VPSRLDZmbikz + 4U, // VPSRLDZmi + 3356U, // VPSRLDZmik + 4444U, // VPSRLDZmikz + 72U, // VPSRLDZri + 133U, // VPSRLDZrik + 9348U, // VPSRLDZrikz + 4U, // VPSRLDZrm + 132U, // VPSRLDZrmk + 9348U, // VPSRLDZrmkz + 4U, // VPSRLDZrr + 0U, // VPSRLDZrrk + 9348U, // VPSRLDZrrkz + 72U, // VPSRLDri + 4U, // VPSRLDrm + 4U, // VPSRLDrr + 72U, // VPSRLQYri + 4U, // VPSRLQYrm + 4U, // VPSRLQYrr + 5U, // VPSRLQZ128mbi + 133U, // VPSRLQZ128mbik + 9349U, // VPSRLQZ128mbikz + 4U, // VPSRLQZ128mi + 3356U, // VPSRLQZ128mik + 4444U, // VPSRLQZ128mikz + 72U, // VPSRLQZ128ri + 133U, // VPSRLQZ128rik + 9348U, // VPSRLQZ128rikz + 4U, // VPSRLQZ128rm + 132U, // VPSRLQZ128rmk + 9348U, // VPSRLQZ128rmkz + 4U, // VPSRLQZ128rr + 0U, // VPSRLQZ128rrk + 9348U, // VPSRLQZ128rrkz + 5U, // VPSRLQZ256mbi + 133U, // VPSRLQZ256mbik + 9349U, // VPSRLQZ256mbikz + 4U, // VPSRLQZ256mi + 3356U, // VPSRLQZ256mik + 4444U, // VPSRLQZ256mikz + 72U, // VPSRLQZ256ri + 133U, // VPSRLQZ256rik + 9348U, // VPSRLQZ256rikz + 4U, // VPSRLQZ256rm + 132U, // VPSRLQZ256rmk + 9348U, // VPSRLQZ256rmkz + 4U, // VPSRLQZ256rr + 0U, // VPSRLQZ256rrk + 9348U, // VPSRLQZ256rrkz + 5U, // VPSRLQZmbi + 133U, // VPSRLQZmbik + 9349U, // VPSRLQZmbikz + 4U, // VPSRLQZmi + 3356U, // VPSRLQZmik + 4444U, // VPSRLQZmikz + 72U, // VPSRLQZri + 133U, // VPSRLQZrik + 9348U, // VPSRLQZrikz + 4U, // VPSRLQZrm + 132U, // VPSRLQZrmk + 9348U, // VPSRLQZrmkz + 4U, // VPSRLQZrr + 0U, // VPSRLQZrrk + 9348U, // VPSRLQZrrkz + 72U, // VPSRLQri + 4U, // VPSRLQrm + 4U, // VPSRLQrr + 4U, // VPSRLVDYrm + 4U, // VPSRLVDYrr + 4U, // VPSRLVDZ128rm + 72U, // VPSRLVDZ128rmb + 133U, // VPSRLVDZ128rmbk + 9348U, // VPSRLVDZ128rmbkz + 132U, // VPSRLVDZ128rmk + 9348U, // VPSRLVDZ128rmkz + 4U, // VPSRLVDZ128rr + 0U, // VPSRLVDZ128rrk + 9348U, // VPSRLVDZ128rrkz + 4U, // VPSRLVDZ256rm + 72U, // VPSRLVDZ256rmb + 133U, // VPSRLVDZ256rmbk + 9348U, // VPSRLVDZ256rmbkz + 132U, // VPSRLVDZ256rmk + 9348U, // VPSRLVDZ256rmkz + 4U, // VPSRLVDZ256rr + 0U, // VPSRLVDZ256rrk + 9348U, // VPSRLVDZ256rrkz + 4U, // VPSRLVDZrm + 72U, // VPSRLVDZrmb + 133U, // VPSRLVDZrmbk + 9348U, // VPSRLVDZrmbkz + 132U, // VPSRLVDZrmk + 9348U, // VPSRLVDZrmkz + 4U, // VPSRLVDZrr + 0U, // VPSRLVDZrrk + 9348U, // VPSRLVDZrrkz + 4U, // VPSRLVDrm + 4U, // VPSRLVDrr + 4U, // VPSRLVQYrm + 4U, // VPSRLVQYrr + 4U, // VPSRLVQZ128rm + 72U, // VPSRLVQZ128rmb + 133U, // VPSRLVQZ128rmbk + 9348U, // VPSRLVQZ128rmbkz + 132U, // VPSRLVQZ128rmk + 9348U, // VPSRLVQZ128rmkz + 4U, // VPSRLVQZ128rr + 0U, // VPSRLVQZ128rrk + 9348U, // VPSRLVQZ128rrkz + 4U, // VPSRLVQZ256rm + 72U, // VPSRLVQZ256rmb + 133U, // VPSRLVQZ256rmbk + 9348U, // VPSRLVQZ256rmbkz + 132U, // VPSRLVQZ256rmk + 9348U, // VPSRLVQZ256rmkz + 4U, // VPSRLVQZ256rr + 0U, // VPSRLVQZ256rrk + 9348U, // VPSRLVQZ256rrkz + 4U, // VPSRLVQZrm + 72U, // VPSRLVQZrmb + 133U, // VPSRLVQZrmbk + 9348U, // VPSRLVQZrmbkz + 132U, // VPSRLVQZrmk + 9348U, // VPSRLVQZrmkz + 4U, // VPSRLVQZrr + 0U, // VPSRLVQZrrk + 9348U, // VPSRLVQZrrkz + 4U, // VPSRLVQrm + 4U, // VPSRLVQrr + 4U, // VPSRLVWZ128rm + 132U, // VPSRLVWZ128rmk + 9348U, // VPSRLVWZ128rmkz + 4U, // VPSRLVWZ128rr + 0U, // VPSRLVWZ128rrk + 9348U, // VPSRLVWZ128rrkz + 4U, // VPSRLVWZ256rm + 132U, // VPSRLVWZ256rmk + 9348U, // VPSRLVWZ256rmkz + 4U, // VPSRLVWZ256rr + 0U, // VPSRLVWZ256rrk + 9348U, // VPSRLVWZ256rrkz + 4U, // VPSRLVWZrm + 132U, // VPSRLVWZrmk + 9348U, // VPSRLVWZrmkz + 4U, // VPSRLVWZrr + 0U, // VPSRLVWZrrk + 9348U, // VPSRLVWZrrkz + 72U, // VPSRLWYri + 4U, // VPSRLWYrm + 4U, // VPSRLWYrr + 4U, // VPSRLWZ128mi + 3356U, // VPSRLWZ128mik + 4444U, // VPSRLWZ128mikz + 72U, // VPSRLWZ128ri + 133U, // VPSRLWZ128rik + 9348U, // VPSRLWZ128rikz + 4U, // VPSRLWZ128rm + 132U, // VPSRLWZ128rmk + 9348U, // VPSRLWZ128rmkz + 4U, // VPSRLWZ128rr + 0U, // VPSRLWZ128rrk + 9348U, // VPSRLWZ128rrkz + 4U, // VPSRLWZ256mi + 3356U, // VPSRLWZ256mik + 4444U, // VPSRLWZ256mikz + 72U, // VPSRLWZ256ri + 133U, // VPSRLWZ256rik + 9348U, // VPSRLWZ256rikz + 4U, // VPSRLWZ256rm + 132U, // VPSRLWZ256rmk + 9348U, // VPSRLWZ256rmkz + 4U, // VPSRLWZ256rr + 0U, // VPSRLWZ256rrk + 9348U, // VPSRLWZ256rrkz + 4U, // VPSRLWZmi + 3356U, // VPSRLWZmik + 4444U, // VPSRLWZmikz + 72U, // VPSRLWZri + 133U, // VPSRLWZrik + 9348U, // VPSRLWZrikz + 4U, // VPSRLWZrm + 132U, // VPSRLWZrmk + 9348U, // VPSRLWZrmkz + 4U, // VPSRLWZrr + 0U, // VPSRLWZrrk + 9348U, // VPSRLWZrrkz + 72U, // VPSRLWri + 4U, // VPSRLWrm + 4U, // VPSRLWrr + 4U, // VPSUBBYrm + 4U, // VPSUBBYrr + 4U, // VPSUBBZ128rm + 132U, // VPSUBBZ128rmk + 9348U, // VPSUBBZ128rmkz + 4U, // VPSUBBZ128rr + 0U, // VPSUBBZ128rrk + 9348U, // VPSUBBZ128rrkz + 4U, // VPSUBBZ256rm + 132U, // VPSUBBZ256rmk + 9348U, // VPSUBBZ256rmkz + 4U, // VPSUBBZ256rr + 0U, // VPSUBBZ256rrk + 9348U, // VPSUBBZ256rrkz + 4U, // VPSUBBZrm + 132U, // VPSUBBZrmk + 9348U, // VPSUBBZrmkz + 4U, // VPSUBBZrr + 0U, // VPSUBBZrrk + 9348U, // VPSUBBZrrkz + 4U, // VPSUBBrm + 4U, // VPSUBBrr + 4U, // VPSUBDYrm + 4U, // VPSUBDYrr + 4U, // VPSUBDZ128rm + 72U, // VPSUBDZ128rmb + 133U, // VPSUBDZ128rmbk + 9348U, // VPSUBDZ128rmbkz + 132U, // VPSUBDZ128rmk + 9348U, // VPSUBDZ128rmkz + 4U, // VPSUBDZ128rr + 0U, // VPSUBDZ128rrk + 9348U, // VPSUBDZ128rrkz + 4U, // VPSUBDZ256rm + 72U, // VPSUBDZ256rmb + 133U, // VPSUBDZ256rmbk + 9348U, // VPSUBDZ256rmbkz + 132U, // VPSUBDZ256rmk + 9348U, // VPSUBDZ256rmkz + 4U, // VPSUBDZ256rr + 0U, // VPSUBDZ256rrk + 9348U, // VPSUBDZ256rrkz + 4U, // VPSUBDZrm + 72U, // VPSUBDZrmb + 133U, // VPSUBDZrmbk + 9348U, // VPSUBDZrmbkz + 132U, // VPSUBDZrmk + 9348U, // VPSUBDZrmkz + 4U, // VPSUBDZrr + 0U, // VPSUBDZrrk + 9348U, // VPSUBDZrrkz + 4U, // VPSUBDrm + 4U, // VPSUBDrr + 4U, // VPSUBQYrm + 4U, // VPSUBQYrr + 4U, // VPSUBQZ128rm + 72U, // VPSUBQZ128rmb + 133U, // VPSUBQZ128rmbk + 9348U, // VPSUBQZ128rmbkz + 132U, // VPSUBQZ128rmk + 9348U, // VPSUBQZ128rmkz + 4U, // VPSUBQZ128rr + 0U, // VPSUBQZ128rrk + 9348U, // VPSUBQZ128rrkz + 4U, // VPSUBQZ256rm + 72U, // VPSUBQZ256rmb + 133U, // VPSUBQZ256rmbk + 9348U, // VPSUBQZ256rmbkz + 132U, // VPSUBQZ256rmk + 9348U, // VPSUBQZ256rmkz + 4U, // VPSUBQZ256rr + 0U, // VPSUBQZ256rrk + 9348U, // VPSUBQZ256rrkz + 4U, // VPSUBQZrm + 72U, // VPSUBQZrmb + 133U, // VPSUBQZrmbk + 9348U, // VPSUBQZrmbkz + 132U, // VPSUBQZrmk + 9348U, // VPSUBQZrmkz + 4U, // VPSUBQZrr + 0U, // VPSUBQZrrk + 9348U, // VPSUBQZrrkz + 4U, // VPSUBQrm + 4U, // VPSUBQrr + 4U, // VPSUBSBYrm + 4U, // VPSUBSBYrr + 4U, // VPSUBSBZ128rm + 132U, // VPSUBSBZ128rmk + 9348U, // VPSUBSBZ128rmkz + 4U, // VPSUBSBZ128rr + 0U, // VPSUBSBZ128rrk + 9348U, // VPSUBSBZ128rrkz + 4U, // VPSUBSBZ256rm + 132U, // VPSUBSBZ256rmk + 9348U, // VPSUBSBZ256rmkz + 4U, // VPSUBSBZ256rr + 0U, // VPSUBSBZ256rrk + 9348U, // VPSUBSBZ256rrkz + 4U, // VPSUBSBZrm + 132U, // VPSUBSBZrmk + 9348U, // VPSUBSBZrmkz + 4U, // VPSUBSBZrr + 0U, // VPSUBSBZrrk + 9348U, // VPSUBSBZrrkz + 4U, // VPSUBSBrm + 4U, // VPSUBSBrr + 4U, // VPSUBSWYrm + 4U, // VPSUBSWYrr + 4U, // VPSUBSWZ128rm + 132U, // VPSUBSWZ128rmk + 9348U, // VPSUBSWZ128rmkz + 4U, // VPSUBSWZ128rr + 0U, // VPSUBSWZ128rrk + 9348U, // VPSUBSWZ128rrkz + 4U, // VPSUBSWZ256rm + 132U, // VPSUBSWZ256rmk + 9348U, // VPSUBSWZ256rmkz + 4U, // VPSUBSWZ256rr + 0U, // VPSUBSWZ256rrk + 9348U, // VPSUBSWZ256rrkz + 4U, // VPSUBSWZrm + 132U, // VPSUBSWZrmk + 9348U, // VPSUBSWZrmkz + 4U, // VPSUBSWZrr + 0U, // VPSUBSWZrrk + 9348U, // VPSUBSWZrrkz + 4U, // VPSUBSWrm + 4U, // VPSUBSWrr + 4U, // VPSUBUSBYrm + 4U, // VPSUBUSBYrr + 4U, // VPSUBUSBZ128rm + 132U, // VPSUBUSBZ128rmk + 9348U, // VPSUBUSBZ128rmkz + 4U, // VPSUBUSBZ128rr + 0U, // VPSUBUSBZ128rrk + 9348U, // VPSUBUSBZ128rrkz + 4U, // VPSUBUSBZ256rm + 132U, // VPSUBUSBZ256rmk + 9348U, // VPSUBUSBZ256rmkz + 4U, // VPSUBUSBZ256rr + 0U, // VPSUBUSBZ256rrk + 9348U, // VPSUBUSBZ256rrkz + 4U, // VPSUBUSBZrm + 132U, // VPSUBUSBZrmk + 9348U, // VPSUBUSBZrmkz + 4U, // VPSUBUSBZrr + 0U, // VPSUBUSBZrrk + 9348U, // VPSUBUSBZrrkz + 4U, // VPSUBUSBrm + 4U, // VPSUBUSBrr + 4U, // VPSUBUSWYrm + 4U, // VPSUBUSWYrr + 4U, // VPSUBUSWZ128rm + 132U, // VPSUBUSWZ128rmk + 9348U, // VPSUBUSWZ128rmkz + 4U, // VPSUBUSWZ128rr + 0U, // VPSUBUSWZ128rrk + 9348U, // VPSUBUSWZ128rrkz + 4U, // VPSUBUSWZ256rm + 132U, // VPSUBUSWZ256rmk + 9348U, // VPSUBUSWZ256rmkz + 4U, // VPSUBUSWZ256rr + 0U, // VPSUBUSWZ256rrk + 9348U, // VPSUBUSWZ256rrkz + 4U, // VPSUBUSWZrm + 132U, // VPSUBUSWZrmk + 9348U, // VPSUBUSWZrmkz + 4U, // VPSUBUSWZrr + 0U, // VPSUBUSWZrrk + 9348U, // VPSUBUSWZrrkz + 4U, // VPSUBUSWrm + 4U, // VPSUBUSWrr + 4U, // VPSUBWYrm + 4U, // VPSUBWYrr + 4U, // VPSUBWZ128rm + 132U, // VPSUBWZ128rmk + 9348U, // VPSUBWZ128rmkz + 4U, // VPSUBWZ128rr + 0U, // VPSUBWZ128rrk + 9348U, // VPSUBWZ128rrkz + 4U, // VPSUBWZ256rm + 132U, // VPSUBWZ256rmk + 9348U, // VPSUBWZ256rmkz + 4U, // VPSUBWZ256rr + 0U, // VPSUBWZ256rrk + 9348U, // VPSUBWZ256rrkz + 4U, // VPSUBWZrm + 132U, // VPSUBWZrmk + 9348U, // VPSUBWZrmkz + 4U, // VPSUBWZrr + 0U, // VPSUBWZrrk + 9348U, // VPSUBWZrrkz + 4U, // VPSUBWrm + 4U, // VPSUBWrr + 18645U, // VPTERNLOGDZ128rmbi + 26833U, // VPTERNLOGDZ128rmbik + 26833U, // VPTERNLOGDZ128rmbikz + 4U, // VPTERNLOGDZ128rmi + 1U, // VPTERNLOGDZ128rmik + 2U, // VPTERNLOGDZ128rmikz + 18645U, // VPTERNLOGDZ128rri + 25U, // VPTERNLOGDZ128rrik + 53U, // VPTERNLOGDZ128rrikz + 18645U, // VPTERNLOGDZ256rmbi + 26833U, // VPTERNLOGDZ256rmbik + 26833U, // VPTERNLOGDZ256rmbikz + 4U, // VPTERNLOGDZ256rmi + 1U, // VPTERNLOGDZ256rmik + 2U, // VPTERNLOGDZ256rmikz + 18645U, // VPTERNLOGDZ256rri + 25U, // VPTERNLOGDZ256rrik + 53U, // VPTERNLOGDZ256rrikz + 18645U, // VPTERNLOGDZrmbi + 26833U, // VPTERNLOGDZrmbik + 26833U, // VPTERNLOGDZrmbikz + 4U, // VPTERNLOGDZrmi + 1U, // VPTERNLOGDZrmik + 2U, // VPTERNLOGDZrmikz + 18645U, // VPTERNLOGDZrri + 25U, // VPTERNLOGDZrrik + 53U, // VPTERNLOGDZrrikz + 18645U, // VPTERNLOGQZ128rmbi + 26833U, // VPTERNLOGQZ128rmbik + 26833U, // VPTERNLOGQZ128rmbikz + 4U, // VPTERNLOGQZ128rmi + 1U, // VPTERNLOGQZ128rmik + 2U, // VPTERNLOGQZ128rmikz + 18645U, // VPTERNLOGQZ128rri + 25U, // VPTERNLOGQZ128rrik + 53U, // VPTERNLOGQZ128rrikz + 18645U, // VPTERNLOGQZ256rmbi + 26833U, // VPTERNLOGQZ256rmbik + 26833U, // VPTERNLOGQZ256rmbikz + 4U, // VPTERNLOGQZ256rmi + 1U, // VPTERNLOGQZ256rmik + 2U, // VPTERNLOGQZ256rmikz + 18645U, // VPTERNLOGQZ256rri + 25U, // VPTERNLOGQZ256rrik + 53U, // VPTERNLOGQZ256rrikz + 18645U, // VPTERNLOGQZrmbi + 26833U, // VPTERNLOGQZrmbik + 26833U, // VPTERNLOGQZrmbikz + 4U, // VPTERNLOGQZrmi + 1U, // VPTERNLOGQZrmik + 2U, // VPTERNLOGQZrmikz + 18645U, // VPTERNLOGQZrri + 25U, // VPTERNLOGQZrrik + 53U, // VPTERNLOGQZrrikz + 4U, // VPTESTMBZ128rm + 1156U, // VPTESTMBZ128rmk + 4U, // VPTESTMBZ128rr + 1156U, // VPTESTMBZ128rrk + 4U, // VPTESTMBZ256rm + 1156U, // VPTESTMBZ256rmk + 4U, // VPTESTMBZ256rr + 1156U, // VPTESTMBZ256rrk + 4U, // VPTESTMBZrm + 1156U, // VPTESTMBZrmk + 4U, // VPTESTMBZrr + 1156U, // VPTESTMBZrrk + 4U, // VPTESTMDZ128rm + 72U, // VPTESTMDZ128rmb + 1156U, // VPTESTMDZ128rmbk + 1156U, // VPTESTMDZ128rmk + 4U, // VPTESTMDZ128rr + 1156U, // VPTESTMDZ128rrk + 4U, // VPTESTMDZ256rm + 72U, // VPTESTMDZ256rmb + 1156U, // VPTESTMDZ256rmbk + 1156U, // VPTESTMDZ256rmk + 4U, // VPTESTMDZ256rr + 1156U, // VPTESTMDZ256rrk + 4U, // VPTESTMDZrm + 72U, // VPTESTMDZrmb + 1156U, // VPTESTMDZrmbk + 1156U, // VPTESTMDZrmk + 4U, // VPTESTMDZrr + 1156U, // VPTESTMDZrrk + 4U, // VPTESTMQZ128rm + 72U, // VPTESTMQZ128rmb + 1156U, // VPTESTMQZ128rmbk + 1156U, // VPTESTMQZ128rmk + 4U, // VPTESTMQZ128rr + 1156U, // VPTESTMQZ128rrk + 4U, // VPTESTMQZ256rm + 72U, // VPTESTMQZ256rmb + 1156U, // VPTESTMQZ256rmbk + 1156U, // VPTESTMQZ256rmk + 4U, // VPTESTMQZ256rr + 1156U, // VPTESTMQZ256rrk + 4U, // VPTESTMQZrm + 72U, // VPTESTMQZrmb + 1156U, // VPTESTMQZrmbk + 1156U, // VPTESTMQZrmk + 4U, // VPTESTMQZrr + 1156U, // VPTESTMQZrrk + 4U, // VPTESTMWZ128rm + 1156U, // VPTESTMWZ128rmk + 4U, // VPTESTMWZ128rr + 1156U, // VPTESTMWZ128rrk + 4U, // VPTESTMWZ256rm + 1156U, // VPTESTMWZ256rmk + 4U, // VPTESTMWZ256rr + 1156U, // VPTESTMWZ256rrk + 4U, // VPTESTMWZrm + 1156U, // VPTESTMWZrmk + 4U, // VPTESTMWZrr + 1156U, // VPTESTMWZrrk + 4U, // VPTESTNMBZ128rm + 1156U, // VPTESTNMBZ128rmk + 4U, // VPTESTNMBZ128rr + 1156U, // VPTESTNMBZ128rrk + 4U, // VPTESTNMBZ256rm + 1156U, // VPTESTNMBZ256rmk + 4U, // VPTESTNMBZ256rr + 1156U, // VPTESTNMBZ256rrk + 4U, // VPTESTNMBZrm + 1156U, // VPTESTNMBZrmk + 4U, // VPTESTNMBZrr + 1156U, // VPTESTNMBZrrk + 4U, // VPTESTNMDZ128rm + 72U, // VPTESTNMDZ128rmb + 1156U, // VPTESTNMDZ128rmbk + 1156U, // VPTESTNMDZ128rmk + 4U, // VPTESTNMDZ128rr + 1156U, // VPTESTNMDZ128rrk + 4U, // VPTESTNMDZ256rm + 72U, // VPTESTNMDZ256rmb + 1156U, // VPTESTNMDZ256rmbk + 1156U, // VPTESTNMDZ256rmk + 4U, // VPTESTNMDZ256rr + 1156U, // VPTESTNMDZ256rrk + 4U, // VPTESTNMDZrm + 72U, // VPTESTNMDZrmb + 1156U, // VPTESTNMDZrmbk + 1156U, // VPTESTNMDZrmk + 4U, // VPTESTNMDZrr + 1156U, // VPTESTNMDZrrk + 4U, // VPTESTNMQZ128rm + 72U, // VPTESTNMQZ128rmb + 1156U, // VPTESTNMQZ128rmbk + 1156U, // VPTESTNMQZ128rmk + 4U, // VPTESTNMQZ128rr + 1156U, // VPTESTNMQZ128rrk + 4U, // VPTESTNMQZ256rm + 72U, // VPTESTNMQZ256rmb + 1156U, // VPTESTNMQZ256rmbk + 1156U, // VPTESTNMQZ256rmk + 4U, // VPTESTNMQZ256rr + 1156U, // VPTESTNMQZ256rrk + 4U, // VPTESTNMQZrm + 72U, // VPTESTNMQZrmb + 1156U, // VPTESTNMQZrmbk + 1156U, // VPTESTNMQZrmk + 4U, // VPTESTNMQZrr + 1156U, // VPTESTNMQZrrk + 4U, // VPTESTNMWZ128rm + 1156U, // VPTESTNMWZ128rmk + 4U, // VPTESTNMWZ128rr + 1156U, // VPTESTNMWZ128rrk + 4U, // VPTESTNMWZ256rm + 1156U, // VPTESTNMWZ256rmk + 4U, // VPTESTNMWZ256rr + 1156U, // VPTESTNMWZ256rrk + 4U, // VPTESTNMWZrm + 1156U, // VPTESTNMWZrmk + 4U, // VPTESTNMWZrr + 1156U, // VPTESTNMWZrrk + 0U, // VPTESTYrm + 0U, // VPTESTYrr + 0U, // VPTESTrm + 0U, // VPTESTrr + 4U, // VPUNPCKHBWYrm + 4U, // VPUNPCKHBWYrr + 4U, // VPUNPCKHBWZ128rm + 132U, // VPUNPCKHBWZ128rmk + 9348U, // VPUNPCKHBWZ128rmkz + 4U, // VPUNPCKHBWZ128rr + 0U, // VPUNPCKHBWZ128rrk + 9348U, // VPUNPCKHBWZ128rrkz + 4U, // VPUNPCKHBWZ256rm + 132U, // VPUNPCKHBWZ256rmk + 9348U, // VPUNPCKHBWZ256rmkz + 4U, // VPUNPCKHBWZ256rr + 0U, // VPUNPCKHBWZ256rrk + 9348U, // VPUNPCKHBWZ256rrkz + 4U, // VPUNPCKHBWZrm + 132U, // VPUNPCKHBWZrmk + 9348U, // VPUNPCKHBWZrmkz + 4U, // VPUNPCKHBWZrr + 0U, // VPUNPCKHBWZrrk + 9348U, // VPUNPCKHBWZrrkz + 4U, // VPUNPCKHBWrm + 4U, // VPUNPCKHBWrr + 4U, // VPUNPCKHDQYrm + 4U, // VPUNPCKHDQYrr + 4U, // VPUNPCKHDQZ128rm + 72U, // VPUNPCKHDQZ128rmb + 133U, // VPUNPCKHDQZ128rmbk + 9348U, // VPUNPCKHDQZ128rmbkz + 132U, // VPUNPCKHDQZ128rmk + 9348U, // VPUNPCKHDQZ128rmkz + 4U, // VPUNPCKHDQZ128rr + 0U, // VPUNPCKHDQZ128rrk + 9348U, // VPUNPCKHDQZ128rrkz + 4U, // VPUNPCKHDQZ256rm + 72U, // VPUNPCKHDQZ256rmb + 133U, // VPUNPCKHDQZ256rmbk + 9348U, // VPUNPCKHDQZ256rmbkz + 132U, // VPUNPCKHDQZ256rmk + 9348U, // VPUNPCKHDQZ256rmkz + 4U, // VPUNPCKHDQZ256rr + 0U, // VPUNPCKHDQZ256rrk + 9348U, // VPUNPCKHDQZ256rrkz + 4U, // VPUNPCKHDQZrm + 72U, // VPUNPCKHDQZrmb + 133U, // VPUNPCKHDQZrmbk + 9348U, // VPUNPCKHDQZrmbkz + 132U, // VPUNPCKHDQZrmk + 9348U, // VPUNPCKHDQZrmkz + 4U, // VPUNPCKHDQZrr + 0U, // VPUNPCKHDQZrrk + 9348U, // VPUNPCKHDQZrrkz + 4U, // VPUNPCKHDQrm + 4U, // VPUNPCKHDQrr + 4U, // VPUNPCKHQDQYrm + 4U, // VPUNPCKHQDQYrr + 4U, // VPUNPCKHQDQZ128rm + 72U, // VPUNPCKHQDQZ128rmb + 133U, // VPUNPCKHQDQZ128rmbk + 9348U, // VPUNPCKHQDQZ128rmbkz + 132U, // VPUNPCKHQDQZ128rmk + 9348U, // VPUNPCKHQDQZ128rmkz + 4U, // VPUNPCKHQDQZ128rr + 0U, // VPUNPCKHQDQZ128rrk + 9348U, // VPUNPCKHQDQZ128rrkz + 4U, // VPUNPCKHQDQZ256rm + 72U, // VPUNPCKHQDQZ256rmb + 133U, // VPUNPCKHQDQZ256rmbk + 9348U, // VPUNPCKHQDQZ256rmbkz + 132U, // VPUNPCKHQDQZ256rmk + 9348U, // VPUNPCKHQDQZ256rmkz + 4U, // VPUNPCKHQDQZ256rr + 0U, // VPUNPCKHQDQZ256rrk + 9348U, // VPUNPCKHQDQZ256rrkz + 4U, // VPUNPCKHQDQZrm + 72U, // VPUNPCKHQDQZrmb + 133U, // VPUNPCKHQDQZrmbk + 9348U, // VPUNPCKHQDQZrmbkz + 132U, // VPUNPCKHQDQZrmk + 9348U, // VPUNPCKHQDQZrmkz + 4U, // VPUNPCKHQDQZrr + 0U, // VPUNPCKHQDQZrrk + 9348U, // VPUNPCKHQDQZrrkz + 4U, // VPUNPCKHQDQrm + 4U, // VPUNPCKHQDQrr + 4U, // VPUNPCKHWDYrm + 4U, // VPUNPCKHWDYrr + 4U, // VPUNPCKHWDZ128rm + 132U, // VPUNPCKHWDZ128rmk + 9348U, // VPUNPCKHWDZ128rmkz + 4U, // VPUNPCKHWDZ128rr + 0U, // VPUNPCKHWDZ128rrk + 9348U, // VPUNPCKHWDZ128rrkz + 4U, // VPUNPCKHWDZ256rm + 132U, // VPUNPCKHWDZ256rmk + 9348U, // VPUNPCKHWDZ256rmkz + 4U, // VPUNPCKHWDZ256rr + 0U, // VPUNPCKHWDZ256rrk + 9348U, // VPUNPCKHWDZ256rrkz + 4U, // VPUNPCKHWDZrm + 132U, // VPUNPCKHWDZrmk + 9348U, // VPUNPCKHWDZrmkz + 4U, // VPUNPCKHWDZrr + 0U, // VPUNPCKHWDZrrk + 9348U, // VPUNPCKHWDZrrkz + 4U, // VPUNPCKHWDrm + 4U, // VPUNPCKHWDrr + 4U, // VPUNPCKLBWYrm + 4U, // VPUNPCKLBWYrr + 4U, // VPUNPCKLBWZ128rm + 132U, // VPUNPCKLBWZ128rmk + 9348U, // VPUNPCKLBWZ128rmkz + 4U, // VPUNPCKLBWZ128rr + 0U, // VPUNPCKLBWZ128rrk + 9348U, // VPUNPCKLBWZ128rrkz + 4U, // VPUNPCKLBWZ256rm + 132U, // VPUNPCKLBWZ256rmk + 9348U, // VPUNPCKLBWZ256rmkz + 4U, // VPUNPCKLBWZ256rr + 0U, // VPUNPCKLBWZ256rrk + 9348U, // VPUNPCKLBWZ256rrkz + 4U, // VPUNPCKLBWZrm + 132U, // VPUNPCKLBWZrmk + 9348U, // VPUNPCKLBWZrmkz + 4U, // VPUNPCKLBWZrr + 0U, // VPUNPCKLBWZrrk + 9348U, // VPUNPCKLBWZrrkz + 4U, // VPUNPCKLBWrm + 4U, // VPUNPCKLBWrr + 4U, // VPUNPCKLDQYrm + 4U, // VPUNPCKLDQYrr + 4U, // VPUNPCKLDQZ128rm + 72U, // VPUNPCKLDQZ128rmb + 133U, // VPUNPCKLDQZ128rmbk + 9348U, // VPUNPCKLDQZ128rmbkz + 132U, // VPUNPCKLDQZ128rmk + 9348U, // VPUNPCKLDQZ128rmkz + 4U, // VPUNPCKLDQZ128rr + 0U, // VPUNPCKLDQZ128rrk + 9348U, // VPUNPCKLDQZ128rrkz + 4U, // VPUNPCKLDQZ256rm + 72U, // VPUNPCKLDQZ256rmb + 133U, // VPUNPCKLDQZ256rmbk + 9348U, // VPUNPCKLDQZ256rmbkz + 132U, // VPUNPCKLDQZ256rmk + 9348U, // VPUNPCKLDQZ256rmkz + 4U, // VPUNPCKLDQZ256rr + 0U, // VPUNPCKLDQZ256rrk + 9348U, // VPUNPCKLDQZ256rrkz + 4U, // VPUNPCKLDQZrm + 72U, // VPUNPCKLDQZrmb + 133U, // VPUNPCKLDQZrmbk + 9348U, // VPUNPCKLDQZrmbkz + 132U, // VPUNPCKLDQZrmk + 9348U, // VPUNPCKLDQZrmkz + 4U, // VPUNPCKLDQZrr + 0U, // VPUNPCKLDQZrrk + 9348U, // VPUNPCKLDQZrrkz + 4U, // VPUNPCKLDQrm + 4U, // VPUNPCKLDQrr + 4U, // VPUNPCKLQDQYrm + 4U, // VPUNPCKLQDQYrr + 4U, // VPUNPCKLQDQZ128rm + 72U, // VPUNPCKLQDQZ128rmb + 133U, // VPUNPCKLQDQZ128rmbk + 9348U, // VPUNPCKLQDQZ128rmbkz + 132U, // VPUNPCKLQDQZ128rmk + 9348U, // VPUNPCKLQDQZ128rmkz + 4U, // VPUNPCKLQDQZ128rr + 0U, // VPUNPCKLQDQZ128rrk + 9348U, // VPUNPCKLQDQZ128rrkz + 4U, // VPUNPCKLQDQZ256rm + 72U, // VPUNPCKLQDQZ256rmb + 133U, // VPUNPCKLQDQZ256rmbk + 9348U, // VPUNPCKLQDQZ256rmbkz + 132U, // VPUNPCKLQDQZ256rmk + 9348U, // VPUNPCKLQDQZ256rmkz + 4U, // VPUNPCKLQDQZ256rr + 0U, // VPUNPCKLQDQZ256rrk + 9348U, // VPUNPCKLQDQZ256rrkz + 4U, // VPUNPCKLQDQZrm + 72U, // VPUNPCKLQDQZrmb + 133U, // VPUNPCKLQDQZrmbk + 9348U, // VPUNPCKLQDQZrmbkz + 132U, // VPUNPCKLQDQZrmk + 9348U, // VPUNPCKLQDQZrmkz + 4U, // VPUNPCKLQDQZrr + 0U, // VPUNPCKLQDQZrrk + 9348U, // VPUNPCKLQDQZrrkz + 4U, // VPUNPCKLQDQrm + 4U, // VPUNPCKLQDQrr + 4U, // VPUNPCKLWDYrm + 4U, // VPUNPCKLWDYrr + 4U, // VPUNPCKLWDZ128rm + 132U, // VPUNPCKLWDZ128rmk + 9348U, // VPUNPCKLWDZ128rmkz + 4U, // VPUNPCKLWDZ128rr + 0U, // VPUNPCKLWDZ128rrk + 9348U, // VPUNPCKLWDZ128rrkz + 4U, // VPUNPCKLWDZ256rm + 132U, // VPUNPCKLWDZ256rmk + 9348U, // VPUNPCKLWDZ256rmkz + 4U, // VPUNPCKLWDZ256rr + 0U, // VPUNPCKLWDZ256rrk + 9348U, // VPUNPCKLWDZ256rrkz + 4U, // VPUNPCKLWDZrm + 132U, // VPUNPCKLWDZrmk + 9348U, // VPUNPCKLWDZrmkz + 4U, // VPUNPCKLWDZrr + 0U, // VPUNPCKLWDZrrk + 9348U, // VPUNPCKLWDZrrkz + 4U, // VPUNPCKLWDrm + 4U, // VPUNPCKLWDrr + 4U, // VPXORDZ128rm + 72U, // VPXORDZ128rmb + 133U, // VPXORDZ128rmbk + 9348U, // VPXORDZ128rmbkz + 132U, // VPXORDZ128rmk + 9348U, // VPXORDZ128rmkz + 4U, // VPXORDZ128rr + 0U, // VPXORDZ128rrk + 9348U, // VPXORDZ128rrkz + 4U, // VPXORDZ256rm + 72U, // VPXORDZ256rmb + 133U, // VPXORDZ256rmbk + 9348U, // VPXORDZ256rmbkz + 132U, // VPXORDZ256rmk + 9348U, // VPXORDZ256rmkz + 4U, // VPXORDZ256rr + 0U, // VPXORDZ256rrk + 9348U, // VPXORDZ256rrkz + 4U, // VPXORDZrm + 72U, // VPXORDZrmb + 133U, // VPXORDZrmbk + 9348U, // VPXORDZrmbkz + 132U, // VPXORDZrmk + 9348U, // VPXORDZrmkz + 4U, // VPXORDZrr + 0U, // VPXORDZrrk + 9348U, // VPXORDZrrkz + 4U, // VPXORQZ128rm + 72U, // VPXORQZ128rmb + 133U, // VPXORQZ128rmbk + 9348U, // VPXORQZ128rmbkz + 132U, // VPXORQZ128rmk + 9348U, // VPXORQZ128rmkz + 4U, // VPXORQZ128rr + 0U, // VPXORQZ128rrk + 9348U, // VPXORQZ128rrkz + 4U, // VPXORQZ256rm + 72U, // VPXORQZ256rmb + 133U, // VPXORQZ256rmbk + 9348U, // VPXORQZ256rmbkz + 132U, // VPXORQZ256rmk + 9348U, // VPXORQZ256rmkz + 4U, // VPXORQZ256rr + 0U, // VPXORQZ256rrk + 9348U, // VPXORQZ256rrkz + 4U, // VPXORQZrm + 72U, // VPXORQZrmb + 133U, // VPXORQZrmbk + 9348U, // VPXORQZrmbkz + 132U, // VPXORQZrmk + 9348U, // VPXORQZrmkz + 4U, // VPXORQZrr + 0U, // VPXORQZrrk + 9348U, // VPXORQZrrkz + 4U, // VPXORYrm + 4U, // VPXORYrr + 4U, // VPXORrm + 4U, // VPXORrr + 18637U, // VRANGEPDZ128rmbi + 26833U, // VRANGEPDZ128rmbik + 26837U, // VRANGEPDZ128rmbikz + 72U, // VRANGEPDZ128rmi + 1U, // VRANGEPDZ128rmik + 9348U, // VRANGEPDZ128rmikz + 18636U, // VRANGEPDZ128rri + 25U, // VRANGEPDZ128rrik + 26837U, // VRANGEPDZ128rrikz + 18637U, // VRANGEPDZ256rmbi + 26833U, // VRANGEPDZ256rmbik + 26837U, // VRANGEPDZ256rmbikz + 72U, // VRANGEPDZ256rmi + 1U, // VRANGEPDZ256rmik + 9348U, // VRANGEPDZ256rmikz + 18636U, // VRANGEPDZ256rri + 25U, // VRANGEPDZ256rrik + 26837U, // VRANGEPDZ256rrikz + 18637U, // VRANGEPDZrmbi + 26833U, // VRANGEPDZrmbik + 26837U, // VRANGEPDZrmbikz + 72U, // VRANGEPDZrmi + 1U, // VRANGEPDZrmik + 9348U, // VRANGEPDZrmikz + 18636U, // VRANGEPDZrri + 18636U, // VRANGEPDZrrib + 25U, // VRANGEPDZrribk + 26837U, // VRANGEPDZrribkz + 25U, // VRANGEPDZrrik + 26837U, // VRANGEPDZrrikz + 18637U, // VRANGEPSZ128rmbi + 26833U, // VRANGEPSZ128rmbik + 26837U, // VRANGEPSZ128rmbikz + 72U, // VRANGEPSZ128rmi + 1U, // VRANGEPSZ128rmik + 9348U, // VRANGEPSZ128rmikz + 18636U, // VRANGEPSZ128rri + 25U, // VRANGEPSZ128rrik + 26837U, // VRANGEPSZ128rrikz + 18637U, // VRANGEPSZ256rmbi + 26833U, // VRANGEPSZ256rmbik + 26837U, // VRANGEPSZ256rmbikz + 72U, // VRANGEPSZ256rmi + 1U, // VRANGEPSZ256rmik + 9348U, // VRANGEPSZ256rmikz + 18636U, // VRANGEPSZ256rri + 25U, // VRANGEPSZ256rrik + 26837U, // VRANGEPSZ256rrikz + 18637U, // VRANGEPSZrmbi + 26833U, // VRANGEPSZrmbik + 26837U, // VRANGEPSZrmbikz + 72U, // VRANGEPSZrmi + 1U, // VRANGEPSZrmik + 9348U, // VRANGEPSZrmikz + 18636U, // VRANGEPSZrri + 18636U, // VRANGEPSZrrib + 25U, // VRANGEPSZrribk + 26837U, // VRANGEPSZrribkz + 25U, // VRANGEPSZrrik + 26837U, // VRANGEPSZrrikz + 18636U, // VRANGESDZrmi + 26832U, // VRANGESDZrmik + 26836U, // VRANGESDZrmikz + 18636U, // VRANGESDZrri + 18636U, // VRANGESDZrrib + 25U, // VRANGESDZrribk + 26837U, // VRANGESDZrribkz + 25U, // VRANGESDZrrik + 26837U, // VRANGESDZrrikz + 18636U, // VRANGESSZrmi + 26832U, // VRANGESSZrmik + 26836U, // VRANGESSZrmikz + 18636U, // VRANGESSZrri + 18636U, // VRANGESSZrrib + 25U, // VRANGESSZrribk + 26837U, // VRANGESSZrribkz + 25U, // VRANGESSZrrik + 26837U, // VRANGESSZrrikz + 0U, // VRCP14PDZ128m + 0U, // VRCP14PDZ128mb + 3356U, // VRCP14PDZ128mbk + 4444U, // VRCP14PDZ128mbkz + 405U, // VRCP14PDZ128mk + 461U, // VRCP14PDZ128mkz + 0U, // VRCP14PDZ128r + 405U, // VRCP14PDZ128rk + 461U, // VRCP14PDZ128rkz + 0U, // VRCP14PDZ256m + 0U, // VRCP14PDZ256mb + 3356U, // VRCP14PDZ256mbk + 4444U, // VRCP14PDZ256mbkz + 405U, // VRCP14PDZ256mk + 461U, // VRCP14PDZ256mkz + 0U, // VRCP14PDZ256r + 405U, // VRCP14PDZ256rk + 461U, // VRCP14PDZ256rkz + 0U, // VRCP14PDZm + 0U, // VRCP14PDZmb + 3356U, // VRCP14PDZmbk + 4444U, // VRCP14PDZmbkz + 405U, // VRCP14PDZmk + 461U, // VRCP14PDZmkz + 0U, // VRCP14PDZr + 405U, // VRCP14PDZrk + 461U, // VRCP14PDZrkz + 0U, // VRCP14PSZ128m + 0U, // VRCP14PSZ128mb + 3356U, // VRCP14PSZ128mbk + 4444U, // VRCP14PSZ128mbkz + 405U, // VRCP14PSZ128mk + 461U, // VRCP14PSZ128mkz + 0U, // VRCP14PSZ128r + 405U, // VRCP14PSZ128rk + 461U, // VRCP14PSZ128rkz + 0U, // VRCP14PSZ256m + 0U, // VRCP14PSZ256mb + 3356U, // VRCP14PSZ256mbk + 4444U, // VRCP14PSZ256mbkz + 405U, // VRCP14PSZ256mk + 461U, // VRCP14PSZ256mkz + 0U, // VRCP14PSZ256r + 405U, // VRCP14PSZ256rk + 461U, // VRCP14PSZ256rkz + 0U, // VRCP14PSZm + 0U, // VRCP14PSZmb + 3356U, // VRCP14PSZmbk + 4444U, // VRCP14PSZmbkz + 405U, // VRCP14PSZmk + 461U, // VRCP14PSZmkz + 0U, // VRCP14PSZr + 405U, // VRCP14PSZrk + 461U, // VRCP14PSZrkz + 72U, // VRCP14SDZrm + 133U, // VRCP14SDZrmk + 9348U, // VRCP14SDZrmkz + 4U, // VRCP14SDZrr + 0U, // VRCP14SDZrrk + 9348U, // VRCP14SDZrrkz + 72U, // VRCP14SSZrm + 133U, // VRCP14SSZrmk + 9348U, // VRCP14SSZrmkz + 4U, // VRCP14SSZrr + 0U, // VRCP14SSZrrk + 9348U, // VRCP14SSZrrkz + 0U, // VRCP28PDZm + 0U, // VRCP28PDZmb + 3356U, // VRCP28PDZmbk + 4444U, // VRCP28PDZmbkz + 405U, // VRCP28PDZmk + 461U, // VRCP28PDZmkz + 0U, // VRCP28PDZr + 0U, // VRCP28PDZrb + 405U, // VRCP28PDZrbk + 461U, // VRCP28PDZrbkz + 405U, // VRCP28PDZrk + 461U, // VRCP28PDZrkz + 0U, // VRCP28PSZm + 0U, // VRCP28PSZmb + 3356U, // VRCP28PSZmbk + 4444U, // VRCP28PSZmbkz + 405U, // VRCP28PSZmk + 461U, // VRCP28PSZmkz + 0U, // VRCP28PSZr + 0U, // VRCP28PSZrb + 405U, // VRCP28PSZrbk + 461U, // VRCP28PSZrbkz + 405U, // VRCP28PSZrk + 461U, // VRCP28PSZrkz + 72U, // VRCP28SDZm + 133U, // VRCP28SDZmk + 9348U, // VRCP28SDZmkz + 4U, // VRCP28SDZr + 4U, // VRCP28SDZrb + 0U, // VRCP28SDZrbk + 9348U, // VRCP28SDZrbkz + 0U, // VRCP28SDZrk + 9348U, // VRCP28SDZrkz + 72U, // VRCP28SSZm + 133U, // VRCP28SSZmk + 9348U, // VRCP28SSZmkz + 4U, // VRCP28SSZr + 4U, // VRCP28SSZrb + 0U, // VRCP28SSZrbk + 9348U, // VRCP28SSZrbkz + 0U, // VRCP28SSZrk + 9348U, // VRCP28SSZrkz + 0U, // VRCPPSYm + 0U, // VRCPPSYr + 0U, // VRCPPSm + 0U, // VRCPPSr + 72U, // VRCPSSm + 72U, // VRCPSSm_Int + 4U, // VRCPSSr + 4U, // VRCPSSr_Int + 5U, // VREDUCEPDZ128rmbi + 133U, // VREDUCEPDZ128rmbik + 9349U, // VREDUCEPDZ128rmbikz + 0U, // VREDUCEPDZ128rmi + 3356U, // VREDUCEPDZ128rmik + 4444U, // VREDUCEPDZ128rmikz + 72U, // VREDUCEPDZ128rri + 133U, // VREDUCEPDZ128rrik + 9348U, // VREDUCEPDZ128rrikz + 5U, // VREDUCEPDZ256rmbi + 133U, // VREDUCEPDZ256rmbik + 9349U, // VREDUCEPDZ256rmbikz + 0U, // VREDUCEPDZ256rmi + 3356U, // VREDUCEPDZ256rmik + 4444U, // VREDUCEPDZ256rmikz + 72U, // VREDUCEPDZ256rri + 133U, // VREDUCEPDZ256rrik + 9348U, // VREDUCEPDZ256rrikz + 5U, // VREDUCEPDZrmbi + 133U, // VREDUCEPDZrmbik + 9349U, // VREDUCEPDZrmbikz + 0U, // VREDUCEPDZrmi + 3356U, // VREDUCEPDZrmik + 4444U, // VREDUCEPDZrmikz + 72U, // VREDUCEPDZrri + 72U, // VREDUCEPDZrrib + 133U, // VREDUCEPDZrribk + 9348U, // VREDUCEPDZrribkz + 133U, // VREDUCEPDZrrik + 9348U, // VREDUCEPDZrrikz + 5U, // VREDUCEPSZ128rmbi + 133U, // VREDUCEPSZ128rmbik + 9349U, // VREDUCEPSZ128rmbikz + 0U, // VREDUCEPSZ128rmi + 3356U, // VREDUCEPSZ128rmik + 4444U, // VREDUCEPSZ128rmikz + 72U, // VREDUCEPSZ128rri + 133U, // VREDUCEPSZ128rrik + 9348U, // VREDUCEPSZ128rrikz + 5U, // VREDUCEPSZ256rmbi + 133U, // VREDUCEPSZ256rmbik + 9349U, // VREDUCEPSZ256rmbikz + 0U, // VREDUCEPSZ256rmi + 3356U, // VREDUCEPSZ256rmik + 4444U, // VREDUCEPSZ256rmikz + 72U, // VREDUCEPSZ256rri + 133U, // VREDUCEPSZ256rrik + 9348U, // VREDUCEPSZ256rrikz + 5U, // VREDUCEPSZrmbi + 133U, // VREDUCEPSZrmbik + 9349U, // VREDUCEPSZrmbikz + 0U, // VREDUCEPSZrmi + 3356U, // VREDUCEPSZrmik + 4444U, // VREDUCEPSZrmikz + 72U, // VREDUCEPSZrri + 72U, // VREDUCEPSZrrib + 133U, // VREDUCEPSZrribk + 9348U, // VREDUCEPSZrribkz + 133U, // VREDUCEPSZrrik + 9348U, // VREDUCEPSZrrikz + 18636U, // VREDUCESDZrmi + 26832U, // VREDUCESDZrmik + 26836U, // VREDUCESDZrmikz + 18636U, // VREDUCESDZrri + 18636U, // VREDUCESDZrrib + 25U, // VREDUCESDZrribk + 26837U, // VREDUCESDZrribkz + 25U, // VREDUCESDZrrik + 26837U, // VREDUCESDZrrikz + 18636U, // VREDUCESSZrmi + 26832U, // VREDUCESSZrmik + 26836U, // VREDUCESSZrmikz + 18636U, // VREDUCESSZrri + 18636U, // VREDUCESSZrrib + 25U, // VREDUCESSZrribk + 26837U, // VREDUCESSZrribkz + 25U, // VREDUCESSZrrik + 26837U, // VREDUCESSZrrikz + 5U, // VRNDSCALEPDZ128rmbi + 133U, // VRNDSCALEPDZ128rmbik + 9349U, // VRNDSCALEPDZ128rmbikz + 0U, // VRNDSCALEPDZ128rmi + 3356U, // VRNDSCALEPDZ128rmik + 4444U, // VRNDSCALEPDZ128rmikz + 72U, // VRNDSCALEPDZ128rri + 133U, // VRNDSCALEPDZ128rrik + 9348U, // VRNDSCALEPDZ128rrikz + 5U, // VRNDSCALEPDZ256rmbi + 133U, // VRNDSCALEPDZ256rmbik + 9349U, // VRNDSCALEPDZ256rmbikz + 0U, // VRNDSCALEPDZ256rmi + 3356U, // VRNDSCALEPDZ256rmik + 4444U, // VRNDSCALEPDZ256rmikz + 72U, // VRNDSCALEPDZ256rri + 133U, // VRNDSCALEPDZ256rrik + 9348U, // VRNDSCALEPDZ256rrikz + 5U, // VRNDSCALEPDZrmbi + 133U, // VRNDSCALEPDZrmbik + 9349U, // VRNDSCALEPDZrmbikz + 0U, // VRNDSCALEPDZrmi + 3356U, // VRNDSCALEPDZrmik + 4444U, // VRNDSCALEPDZrmikz + 72U, // VRNDSCALEPDZrri + 72U, // VRNDSCALEPDZrrib + 133U, // VRNDSCALEPDZrribk + 9348U, // VRNDSCALEPDZrribkz + 133U, // VRNDSCALEPDZrrik + 9348U, // VRNDSCALEPDZrrikz + 5U, // VRNDSCALEPSZ128rmbi + 133U, // VRNDSCALEPSZ128rmbik + 9349U, // VRNDSCALEPSZ128rmbikz + 0U, // VRNDSCALEPSZ128rmi + 3356U, // VRNDSCALEPSZ128rmik + 4444U, // VRNDSCALEPSZ128rmikz + 72U, // VRNDSCALEPSZ128rri + 133U, // VRNDSCALEPSZ128rrik + 9348U, // VRNDSCALEPSZ128rrikz + 5U, // VRNDSCALEPSZ256rmbi + 133U, // VRNDSCALEPSZ256rmbik + 9349U, // VRNDSCALEPSZ256rmbikz + 0U, // VRNDSCALEPSZ256rmi + 3356U, // VRNDSCALEPSZ256rmik + 4444U, // VRNDSCALEPSZ256rmikz + 72U, // VRNDSCALEPSZ256rri + 133U, // VRNDSCALEPSZ256rrik + 9348U, // VRNDSCALEPSZ256rrikz + 5U, // VRNDSCALEPSZrmbi + 133U, // VRNDSCALEPSZrmbik + 9349U, // VRNDSCALEPSZrmbikz + 0U, // VRNDSCALEPSZrmi + 3356U, // VRNDSCALEPSZrmik + 4444U, // VRNDSCALEPSZrmikz + 72U, // VRNDSCALEPSZrri + 72U, // VRNDSCALEPSZrrib + 133U, // VRNDSCALEPSZrribk + 9348U, // VRNDSCALEPSZrribkz + 133U, // VRNDSCALEPSZrrik + 9348U, // VRNDSCALEPSZrrikz + 18636U, // VRNDSCALESDZm + 18636U, // VRNDSCALESDZm_Int + 26832U, // VRNDSCALESDZm_Intk + 26836U, // VRNDSCALESDZm_Intkz + 18636U, // VRNDSCALESDZr + 18636U, // VRNDSCALESDZr_Int + 25U, // VRNDSCALESDZr_Intk + 26837U, // VRNDSCALESDZr_Intkz + 18636U, // VRNDSCALESDZrb_Int + 25U, // VRNDSCALESDZrb_Intk + 26837U, // VRNDSCALESDZrb_Intkz + 18636U, // VRNDSCALESSZm + 18636U, // VRNDSCALESSZm_Int + 26832U, // VRNDSCALESSZm_Intk + 26836U, // VRNDSCALESSZm_Intkz + 18636U, // VRNDSCALESSZr + 18636U, // VRNDSCALESSZr_Int + 25U, // VRNDSCALESSZr_Intk + 26837U, // VRNDSCALESSZr_Intkz + 18636U, // VRNDSCALESSZrb_Int + 25U, // VRNDSCALESSZrb_Intk + 26837U, // VRNDSCALESSZrb_Intkz + 0U, // VROUNDPDYm + 72U, // VROUNDPDYr + 0U, // VROUNDPDm + 72U, // VROUNDPDr + 0U, // VROUNDPSYm + 72U, // VROUNDPSYr + 0U, // VROUNDPSm + 72U, // VROUNDPSr + 18636U, // VROUNDSDm + 18636U, // VROUNDSDm_Int + 18636U, // VROUNDSDr + 18636U, // VROUNDSDr_Int + 18636U, // VROUNDSSm + 18636U, // VROUNDSSm_Int + 18636U, // VROUNDSSr + 18636U, // VROUNDSSr_Int + 0U, // VRSQRT14PDZ128m + 0U, // VRSQRT14PDZ128mb + 3356U, // VRSQRT14PDZ128mbk + 4444U, // VRSQRT14PDZ128mbkz + 405U, // VRSQRT14PDZ128mk + 461U, // VRSQRT14PDZ128mkz + 0U, // VRSQRT14PDZ128r + 405U, // VRSQRT14PDZ128rk + 461U, // VRSQRT14PDZ128rkz + 0U, // VRSQRT14PDZ256m + 0U, // VRSQRT14PDZ256mb + 3356U, // VRSQRT14PDZ256mbk + 4444U, // VRSQRT14PDZ256mbkz + 405U, // VRSQRT14PDZ256mk + 461U, // VRSQRT14PDZ256mkz + 0U, // VRSQRT14PDZ256r + 405U, // VRSQRT14PDZ256rk + 461U, // VRSQRT14PDZ256rkz + 0U, // VRSQRT14PDZm + 0U, // VRSQRT14PDZmb + 3356U, // VRSQRT14PDZmbk + 4444U, // VRSQRT14PDZmbkz + 405U, // VRSQRT14PDZmk + 461U, // VRSQRT14PDZmkz + 0U, // VRSQRT14PDZr + 405U, // VRSQRT14PDZrk + 461U, // VRSQRT14PDZrkz + 0U, // VRSQRT14PSZ128m + 0U, // VRSQRT14PSZ128mb + 3356U, // VRSQRT14PSZ128mbk + 4444U, // VRSQRT14PSZ128mbkz + 405U, // VRSQRT14PSZ128mk + 461U, // VRSQRT14PSZ128mkz + 0U, // VRSQRT14PSZ128r + 405U, // VRSQRT14PSZ128rk + 461U, // VRSQRT14PSZ128rkz + 0U, // VRSQRT14PSZ256m + 0U, // VRSQRT14PSZ256mb + 3356U, // VRSQRT14PSZ256mbk + 4444U, // VRSQRT14PSZ256mbkz + 405U, // VRSQRT14PSZ256mk + 461U, // VRSQRT14PSZ256mkz + 0U, // VRSQRT14PSZ256r + 405U, // VRSQRT14PSZ256rk + 461U, // VRSQRT14PSZ256rkz + 0U, // VRSQRT14PSZm + 0U, // VRSQRT14PSZmb + 3356U, // VRSQRT14PSZmbk + 4444U, // VRSQRT14PSZmbkz + 405U, // VRSQRT14PSZmk + 461U, // VRSQRT14PSZmkz + 0U, // VRSQRT14PSZr + 405U, // VRSQRT14PSZrk + 461U, // VRSQRT14PSZrkz + 72U, // VRSQRT14SDZrm + 133U, // VRSQRT14SDZrmk + 9348U, // VRSQRT14SDZrmkz + 4U, // VRSQRT14SDZrr + 0U, // VRSQRT14SDZrrk + 9348U, // VRSQRT14SDZrrkz + 72U, // VRSQRT14SSZrm + 133U, // VRSQRT14SSZrmk + 9348U, // VRSQRT14SSZrmkz + 4U, // VRSQRT14SSZrr + 0U, // VRSQRT14SSZrrk + 9348U, // VRSQRT14SSZrrkz + 0U, // VRSQRT28PDZm + 0U, // VRSQRT28PDZmb + 3356U, // VRSQRT28PDZmbk + 4444U, // VRSQRT28PDZmbkz + 405U, // VRSQRT28PDZmk + 461U, // VRSQRT28PDZmkz + 0U, // VRSQRT28PDZr + 0U, // VRSQRT28PDZrb + 405U, // VRSQRT28PDZrbk + 461U, // VRSQRT28PDZrbkz + 405U, // VRSQRT28PDZrk + 461U, // VRSQRT28PDZrkz + 0U, // VRSQRT28PSZm + 0U, // VRSQRT28PSZmb + 3356U, // VRSQRT28PSZmbk + 4444U, // VRSQRT28PSZmbkz + 405U, // VRSQRT28PSZmk + 461U, // VRSQRT28PSZmkz + 0U, // VRSQRT28PSZr + 0U, // VRSQRT28PSZrb + 405U, // VRSQRT28PSZrbk + 461U, // VRSQRT28PSZrbkz + 405U, // VRSQRT28PSZrk + 461U, // VRSQRT28PSZrkz + 72U, // VRSQRT28SDZm + 133U, // VRSQRT28SDZmk + 9348U, // VRSQRT28SDZmkz + 4U, // VRSQRT28SDZr + 4U, // VRSQRT28SDZrb + 0U, // VRSQRT28SDZrbk + 9348U, // VRSQRT28SDZrbkz + 0U, // VRSQRT28SDZrk + 9348U, // VRSQRT28SDZrkz + 72U, // VRSQRT28SSZm + 133U, // VRSQRT28SSZmk + 9348U, // VRSQRT28SSZmkz + 4U, // VRSQRT28SSZr + 4U, // VRSQRT28SSZrb + 0U, // VRSQRT28SSZrbk + 9348U, // VRSQRT28SSZrbkz + 0U, // VRSQRT28SSZrk + 9348U, // VRSQRT28SSZrkz + 0U, // VRSQRTPSYm + 0U, // VRSQRTPSYr + 0U, // VRSQRTPSm + 0U, // VRSQRTPSr + 72U, // VRSQRTSSm + 72U, // VRSQRTSSm_Int + 4U, // VRSQRTSSr + 4U, // VRSQRTSSr_Int + 4U, // VSCALEFPDZ128rm + 72U, // VSCALEFPDZ128rmb + 133U, // VSCALEFPDZ128rmbk + 9348U, // VSCALEFPDZ128rmbkz + 0U, // VSCALEFPDZ128rmk + 9348U, // VSCALEFPDZ128rmkz + 4U, // VSCALEFPDZ128rr + 0U, // VSCALEFPDZ128rrk + 9348U, // VSCALEFPDZ128rrkz + 4U, // VSCALEFPDZ256rm + 72U, // VSCALEFPDZ256rmb + 133U, // VSCALEFPDZ256rmbk + 9348U, // VSCALEFPDZ256rmbkz + 0U, // VSCALEFPDZ256rmk + 9348U, // VSCALEFPDZ256rmkz + 4U, // VSCALEFPDZ256rr + 0U, // VSCALEFPDZ256rrk + 9348U, // VSCALEFPDZ256rrkz + 4U, // VSCALEFPDZrm + 72U, // VSCALEFPDZrmb + 133U, // VSCALEFPDZrmbk + 9348U, // VSCALEFPDZrmbkz + 0U, // VSCALEFPDZrmk + 9348U, // VSCALEFPDZrmkz + 4U, // VSCALEFPDZrr + 4U, // VSCALEFPDZrrb + 0U, // VSCALEFPDZrrbk + 9348U, // VSCALEFPDZrrbkz + 0U, // VSCALEFPDZrrk + 9348U, // VSCALEFPDZrrkz + 4U, // VSCALEFPSZ128rm + 72U, // VSCALEFPSZ128rmb + 133U, // VSCALEFPSZ128rmbk + 9348U, // VSCALEFPSZ128rmbkz + 0U, // VSCALEFPSZ128rmk + 9348U, // VSCALEFPSZ128rmkz + 4U, // VSCALEFPSZ128rr + 0U, // VSCALEFPSZ128rrk + 9348U, // VSCALEFPSZ128rrkz + 4U, // VSCALEFPSZ256rm + 72U, // VSCALEFPSZ256rmb + 133U, // VSCALEFPSZ256rmbk + 9348U, // VSCALEFPSZ256rmbkz + 0U, // VSCALEFPSZ256rmk + 9348U, // VSCALEFPSZ256rmkz + 4U, // VSCALEFPSZ256rr + 0U, // VSCALEFPSZ256rrk + 9348U, // VSCALEFPSZ256rrkz + 4U, // VSCALEFPSZrm + 72U, // VSCALEFPSZrmb + 133U, // VSCALEFPSZrmbk + 9348U, // VSCALEFPSZrmbkz + 0U, // VSCALEFPSZrmk + 9348U, // VSCALEFPSZrmkz + 4U, // VSCALEFPSZrr + 4U, // VSCALEFPSZrrb + 0U, // VSCALEFPSZrrbk + 9348U, // VSCALEFPSZrrbkz + 0U, // VSCALEFPSZrrk + 9348U, // VSCALEFPSZrrkz + 72U, // VSCALEFSDZrm + 133U, // VSCALEFSDZrmk + 9348U, // VSCALEFSDZrmkz + 4U, // VSCALEFSDZrr + 4U, // VSCALEFSDZrrb_Int + 0U, // VSCALEFSDZrrb_Intk + 9348U, // VSCALEFSDZrrb_Intkz + 0U, // VSCALEFSDZrrk + 9348U, // VSCALEFSDZrrkz + 72U, // VSCALEFSSZrm + 133U, // VSCALEFSSZrmk + 9348U, // VSCALEFSSZrmkz + 4U, // VSCALEFSSZrr + 4U, // VSCALEFSSZrrb_Int + 0U, // VSCALEFSSZrrb_Intk + 9348U, // VSCALEFSSZrrb_Intkz + 0U, // VSCALEFSSZrrk + 9348U, // VSCALEFSSZrrkz + 57U, // VSCATTERDPDZ128mr + 57U, // VSCATTERDPDZ256mr + 57U, // VSCATTERDPDZmr + 57U, // VSCATTERDPSZ128mr + 57U, // VSCATTERDPSZ256mr + 57U, // VSCATTERDPSZmr + 0U, // VSCATTERPF0DPDm + 0U, // VSCATTERPF0DPSm + 0U, // VSCATTERPF0QPDm + 0U, // VSCATTERPF0QPSm + 0U, // VSCATTERPF1DPDm + 0U, // VSCATTERPF1DPSm + 0U, // VSCATTERPF1QPDm + 0U, // VSCATTERPF1QPSm + 57U, // VSCATTERQPDZ128mr + 57U, // VSCATTERQPDZ256mr + 57U, // VSCATTERQPDZmr + 57U, // VSCATTERQPSZ128mr + 57U, // VSCATTERQPSZ256mr + 57U, // VSCATTERQPSZmr + 18637U, // VSHUFF32X4Z256rmbi + 26833U, // VSHUFF32X4Z256rmbik + 26837U, // VSHUFF32X4Z256rmbikz + 72U, // VSHUFF32X4Z256rmi + 1U, // VSHUFF32X4Z256rmik + 9348U, // VSHUFF32X4Z256rmikz + 18636U, // VSHUFF32X4Z256rri + 25U, // VSHUFF32X4Z256rrik + 26837U, // VSHUFF32X4Z256rrikz + 18637U, // VSHUFF32X4Zrmbi + 26833U, // VSHUFF32X4Zrmbik + 26837U, // VSHUFF32X4Zrmbikz + 72U, // VSHUFF32X4Zrmi + 1U, // VSHUFF32X4Zrmik + 9348U, // VSHUFF32X4Zrmikz + 18636U, // VSHUFF32X4Zrri + 25U, // VSHUFF32X4Zrrik + 26837U, // VSHUFF32X4Zrrikz + 18637U, // VSHUFF64X2Z256rmbi + 26833U, // VSHUFF64X2Z256rmbik + 26837U, // VSHUFF64X2Z256rmbikz + 72U, // VSHUFF64X2Z256rmi + 1U, // VSHUFF64X2Z256rmik + 9348U, // VSHUFF64X2Z256rmikz + 18636U, // VSHUFF64X2Z256rri + 25U, // VSHUFF64X2Z256rrik + 26837U, // VSHUFF64X2Z256rrikz + 18637U, // VSHUFF64X2Zrmbi + 26833U, // VSHUFF64X2Zrmbik + 26837U, // VSHUFF64X2Zrmbikz + 72U, // VSHUFF64X2Zrmi + 1U, // VSHUFF64X2Zrmik + 9348U, // VSHUFF64X2Zrmikz + 18636U, // VSHUFF64X2Zrri + 25U, // VSHUFF64X2Zrrik + 26837U, // VSHUFF64X2Zrrikz + 18637U, // VSHUFI32X4Z256rmbi + 26833U, // VSHUFI32X4Z256rmbik + 26837U, // VSHUFI32X4Z256rmbikz + 72U, // VSHUFI32X4Z256rmi + 1U, // VSHUFI32X4Z256rmik + 9348U, // VSHUFI32X4Z256rmikz + 18636U, // VSHUFI32X4Z256rri + 25U, // VSHUFI32X4Z256rrik + 26837U, // VSHUFI32X4Z256rrikz + 18637U, // VSHUFI32X4Zrmbi + 26833U, // VSHUFI32X4Zrmbik + 26837U, // VSHUFI32X4Zrmbikz + 72U, // VSHUFI32X4Zrmi + 1U, // VSHUFI32X4Zrmik + 9348U, // VSHUFI32X4Zrmikz + 18636U, // VSHUFI32X4Zrri + 25U, // VSHUFI32X4Zrrik + 26837U, // VSHUFI32X4Zrrikz + 18637U, // VSHUFI64X2Z256rmbi + 26833U, // VSHUFI64X2Z256rmbik + 26837U, // VSHUFI64X2Z256rmbikz + 72U, // VSHUFI64X2Z256rmi + 1U, // VSHUFI64X2Z256rmik + 9348U, // VSHUFI64X2Z256rmikz + 18636U, // VSHUFI64X2Z256rri + 25U, // VSHUFI64X2Z256rrik + 26837U, // VSHUFI64X2Z256rrikz + 18637U, // VSHUFI64X2Zrmbi + 26833U, // VSHUFI64X2Zrmbik + 26837U, // VSHUFI64X2Zrmbikz + 72U, // VSHUFI64X2Zrmi + 1U, // VSHUFI64X2Zrmik + 9348U, // VSHUFI64X2Zrmikz + 18636U, // VSHUFI64X2Zrri + 25U, // VSHUFI64X2Zrrik + 26837U, // VSHUFI64X2Zrrikz + 72U, // VSHUFPDYrmi + 18636U, // VSHUFPDYrri + 18637U, // VSHUFPDZ128rmbi + 26833U, // VSHUFPDZ128rmbik + 26837U, // VSHUFPDZ128rmbikz + 72U, // VSHUFPDZ128rmi + 1U, // VSHUFPDZ128rmik + 9348U, // VSHUFPDZ128rmikz + 18636U, // VSHUFPDZ128rri + 25U, // VSHUFPDZ128rrik + 26837U, // VSHUFPDZ128rrikz + 18637U, // VSHUFPDZ256rmbi + 26833U, // VSHUFPDZ256rmbik + 26837U, // VSHUFPDZ256rmbikz + 72U, // VSHUFPDZ256rmi + 1U, // VSHUFPDZ256rmik + 9348U, // VSHUFPDZ256rmikz + 18636U, // VSHUFPDZ256rri + 25U, // VSHUFPDZ256rrik + 26837U, // VSHUFPDZ256rrikz + 18637U, // VSHUFPDZrmbi + 26833U, // VSHUFPDZrmbik + 26837U, // VSHUFPDZrmbikz + 72U, // VSHUFPDZrmi + 1U, // VSHUFPDZrmik + 9348U, // VSHUFPDZrmikz + 18636U, // VSHUFPDZrri + 25U, // VSHUFPDZrrik + 26837U, // VSHUFPDZrrikz + 72U, // VSHUFPDrmi + 18636U, // VSHUFPDrri + 72U, // VSHUFPSYrmi + 18636U, // VSHUFPSYrri + 18637U, // VSHUFPSZ128rmbi + 26833U, // VSHUFPSZ128rmbik + 26837U, // VSHUFPSZ128rmbikz + 72U, // VSHUFPSZ128rmi + 1U, // VSHUFPSZ128rmik + 9348U, // VSHUFPSZ128rmikz + 18636U, // VSHUFPSZ128rri + 25U, // VSHUFPSZ128rrik + 26837U, // VSHUFPSZ128rrikz + 18637U, // VSHUFPSZ256rmbi + 26833U, // VSHUFPSZ256rmbik + 26837U, // VSHUFPSZ256rmbikz + 72U, // VSHUFPSZ256rmi + 1U, // VSHUFPSZ256rmik + 9348U, // VSHUFPSZ256rmikz + 18636U, // VSHUFPSZ256rri + 25U, // VSHUFPSZ256rrik + 26837U, // VSHUFPSZ256rrikz + 18637U, // VSHUFPSZrmbi + 26833U, // VSHUFPSZrmbik + 26837U, // VSHUFPSZrmbikz + 72U, // VSHUFPSZrmi + 1U, // VSHUFPSZrmik + 9348U, // VSHUFPSZrmikz + 18636U, // VSHUFPSZrri + 25U, // VSHUFPSZrrik + 26837U, // VSHUFPSZrrikz + 72U, // VSHUFPSrmi + 18636U, // VSHUFPSrri + 0U, // VSQRTPDYm + 0U, // VSQRTPDYr + 0U, // VSQRTPDZ128m + 0U, // VSQRTPDZ128mb + 3356U, // VSQRTPDZ128mbk + 4444U, // VSQRTPDZ128mbkz + 405U, // VSQRTPDZ128mk + 461U, // VSQRTPDZ128mkz + 0U, // VSQRTPDZ128r + 405U, // VSQRTPDZ128rk + 461U, // VSQRTPDZ128rkz + 0U, // VSQRTPDZ256m + 0U, // VSQRTPDZ256mb + 3356U, // VSQRTPDZ256mbk + 4444U, // VSQRTPDZ256mbkz + 405U, // VSQRTPDZ256mk + 461U, // VSQRTPDZ256mkz + 0U, // VSQRTPDZ256r + 405U, // VSQRTPDZ256rk + 461U, // VSQRTPDZ256rkz + 0U, // VSQRTPDZm + 0U, // VSQRTPDZmb + 3356U, // VSQRTPDZmbk + 4444U, // VSQRTPDZmbkz + 405U, // VSQRTPDZmk + 461U, // VSQRTPDZmkz + 0U, // VSQRTPDZr + 0U, // VSQRTPDZrb + 405U, // VSQRTPDZrbk + 461U, // VSQRTPDZrbkz + 405U, // VSQRTPDZrk + 461U, // VSQRTPDZrkz + 0U, // VSQRTPDm + 0U, // VSQRTPDr + 0U, // VSQRTPSYm + 0U, // VSQRTPSYr + 0U, // VSQRTPSZ128m + 0U, // VSQRTPSZ128mb + 3356U, // VSQRTPSZ128mbk + 4444U, // VSQRTPSZ128mbkz + 405U, // VSQRTPSZ128mk + 461U, // VSQRTPSZ128mkz + 0U, // VSQRTPSZ128r + 405U, // VSQRTPSZ128rk + 461U, // VSQRTPSZ128rkz + 0U, // VSQRTPSZ256m + 0U, // VSQRTPSZ256mb + 3356U, // VSQRTPSZ256mbk + 4444U, // VSQRTPSZ256mbkz + 405U, // VSQRTPSZ256mk + 461U, // VSQRTPSZ256mkz + 0U, // VSQRTPSZ256r + 405U, // VSQRTPSZ256rk + 461U, // VSQRTPSZ256rkz + 0U, // VSQRTPSZm + 0U, // VSQRTPSZmb + 3356U, // VSQRTPSZmbk + 4444U, // VSQRTPSZmbkz + 405U, // VSQRTPSZmk + 461U, // VSQRTPSZmkz + 0U, // VSQRTPSZr + 0U, // VSQRTPSZrb + 405U, // VSQRTPSZrbk + 461U, // VSQRTPSZrbkz + 405U, // VSQRTPSZrk + 461U, // VSQRTPSZrkz + 0U, // VSQRTPSm + 0U, // VSQRTPSr + 72U, // VSQRTSDZm + 72U, // VSQRTSDZm_Int + 133U, // VSQRTSDZm_Intk + 9348U, // VSQRTSDZm_Intkz + 4U, // VSQRTSDZr + 4U, // VSQRTSDZr_Int + 0U, // VSQRTSDZr_Intk + 9348U, // VSQRTSDZr_Intkz + 4U, // VSQRTSDZrb_Int + 0U, // VSQRTSDZrb_Intk + 9348U, // VSQRTSDZrb_Intkz + 72U, // VSQRTSDm + 72U, // VSQRTSDm_Int + 4U, // VSQRTSDr + 4U, // VSQRTSDr_Int + 72U, // VSQRTSSZm + 72U, // VSQRTSSZm_Int + 133U, // VSQRTSSZm_Intk + 9348U, // VSQRTSSZm_Intkz + 4U, // VSQRTSSZr + 4U, // VSQRTSSZr_Int + 0U, // VSQRTSSZr_Intk + 9348U, // VSQRTSSZr_Intkz + 4U, // VSQRTSSZrb_Int + 0U, // VSQRTSSZrb_Intk + 9348U, // VSQRTSSZrb_Intkz + 72U, // VSQRTSSm + 72U, // VSQRTSSm_Int + 4U, // VSQRTSSr + 4U, // VSQRTSSr_Int + 0U, // VSTMXCSR + 4U, // VSUBPDYrm + 4U, // VSUBPDYrr + 4U, // VSUBPDZ128rm + 72U, // VSUBPDZ128rmb + 133U, // VSUBPDZ128rmbk + 9348U, // VSUBPDZ128rmbkz + 0U, // VSUBPDZ128rmk + 9348U, // VSUBPDZ128rmkz + 4U, // VSUBPDZ128rr + 0U, // VSUBPDZ128rrk + 9348U, // VSUBPDZ128rrkz + 4U, // VSUBPDZ256rm + 72U, // VSUBPDZ256rmb + 133U, // VSUBPDZ256rmbk + 9348U, // VSUBPDZ256rmbkz + 0U, // VSUBPDZ256rmk + 9348U, // VSUBPDZ256rmkz + 4U, // VSUBPDZ256rr + 0U, // VSUBPDZ256rrk + 9348U, // VSUBPDZ256rrkz + 4U, // VSUBPDZrm + 72U, // VSUBPDZrmb + 133U, // VSUBPDZrmbk + 9348U, // VSUBPDZrmbkz + 0U, // VSUBPDZrmk + 9348U, // VSUBPDZrmkz + 4U, // VSUBPDZrr + 4U, // VSUBPDZrrb + 0U, // VSUBPDZrrbk + 9348U, // VSUBPDZrrbkz + 0U, // VSUBPDZrrk + 9348U, // VSUBPDZrrkz + 4U, // VSUBPDrm + 4U, // VSUBPDrr + 4U, // VSUBPSYrm + 4U, // VSUBPSYrr + 4U, // VSUBPSZ128rm + 72U, // VSUBPSZ128rmb + 133U, // VSUBPSZ128rmbk + 9348U, // VSUBPSZ128rmbkz + 0U, // VSUBPSZ128rmk + 9348U, // VSUBPSZ128rmkz + 4U, // VSUBPSZ128rr + 0U, // VSUBPSZ128rrk + 9348U, // VSUBPSZ128rrkz + 4U, // VSUBPSZ256rm + 72U, // VSUBPSZ256rmb + 133U, // VSUBPSZ256rmbk + 9348U, // VSUBPSZ256rmbkz + 0U, // VSUBPSZ256rmk + 9348U, // VSUBPSZ256rmkz + 4U, // VSUBPSZ256rr + 0U, // VSUBPSZ256rrk + 9348U, // VSUBPSZ256rrkz + 4U, // VSUBPSZrm + 72U, // VSUBPSZrmb + 133U, // VSUBPSZrmbk + 9348U, // VSUBPSZrmbkz + 0U, // VSUBPSZrmk + 9348U, // VSUBPSZrmkz + 4U, // VSUBPSZrr + 4U, // VSUBPSZrrb + 0U, // VSUBPSZrrbk + 9348U, // VSUBPSZrrbkz + 0U, // VSUBPSZrrk + 9348U, // VSUBPSZrrkz + 4U, // VSUBPSrm + 4U, // VSUBPSrr + 72U, // VSUBSDZrm + 72U, // VSUBSDZrm_Int + 133U, // VSUBSDZrm_Intk + 9348U, // VSUBSDZrm_Intkz + 4U, // VSUBSDZrr + 4U, // VSUBSDZrr_Int + 0U, // VSUBSDZrr_Intk + 9348U, // VSUBSDZrr_Intkz + 4U, // VSUBSDZrrb_Int + 0U, // VSUBSDZrrb_Intk + 9348U, // VSUBSDZrrb_Intkz + 72U, // VSUBSDrm + 72U, // VSUBSDrm_Int + 4U, // VSUBSDrr + 4U, // VSUBSDrr_Int + 72U, // VSUBSSZrm + 72U, // VSUBSSZrm_Int + 133U, // VSUBSSZrm_Intk + 9348U, // VSUBSSZrm_Intkz + 4U, // VSUBSSZrr + 4U, // VSUBSSZrr_Int + 0U, // VSUBSSZrr_Intk + 9348U, // VSUBSSZrr_Intkz + 4U, // VSUBSSZrrb_Int + 0U, // VSUBSSZrrb_Intk + 9348U, // VSUBSSZrrb_Intkz + 72U, // VSUBSSrm + 72U, // VSUBSSrm_Int + 4U, // VSUBSSrr + 4U, // VSUBSSrr_Int + 0U, // VTESTPDYrm + 0U, // VTESTPDYrr + 0U, // VTESTPDrm + 0U, // VTESTPDrr + 0U, // VTESTPSYrm + 0U, // VTESTPSYrr + 0U, // VTESTPSrm + 0U, // VTESTPSrr + 0U, // VUCOMISDZrm + 0U, // VUCOMISDZrm_Int + 0U, // VUCOMISDZrr + 0U, // VUCOMISDZrr_Int + 0U, // VUCOMISDZrrb + 0U, // VUCOMISDrm + 0U, // VUCOMISDrm_Int + 0U, // VUCOMISDrr + 0U, // VUCOMISDrr_Int + 0U, // VUCOMISSZrm + 0U, // VUCOMISSZrm_Int + 0U, // VUCOMISSZrr + 0U, // VUCOMISSZrr_Int + 0U, // VUCOMISSZrrb + 0U, // VUCOMISSrm + 0U, // VUCOMISSrm_Int + 0U, // VUCOMISSrr + 0U, // VUCOMISSrr_Int + 4U, // VUNPCKHPDYrm + 4U, // VUNPCKHPDYrr + 4U, // VUNPCKHPDZ128rm + 72U, // VUNPCKHPDZ128rmb + 133U, // VUNPCKHPDZ128rmbk + 9348U, // VUNPCKHPDZ128rmbkz + 0U, // VUNPCKHPDZ128rmk + 9348U, // VUNPCKHPDZ128rmkz + 4U, // VUNPCKHPDZ128rr + 0U, // VUNPCKHPDZ128rrk + 9348U, // VUNPCKHPDZ128rrkz + 4U, // VUNPCKHPDZ256rm + 72U, // VUNPCKHPDZ256rmb + 133U, // VUNPCKHPDZ256rmbk + 9348U, // VUNPCKHPDZ256rmbkz + 0U, // VUNPCKHPDZ256rmk + 9348U, // VUNPCKHPDZ256rmkz + 4U, // VUNPCKHPDZ256rr + 0U, // VUNPCKHPDZ256rrk + 9348U, // VUNPCKHPDZ256rrkz + 4U, // VUNPCKHPDZrm + 72U, // VUNPCKHPDZrmb + 133U, // VUNPCKHPDZrmbk + 9348U, // VUNPCKHPDZrmbkz + 0U, // VUNPCKHPDZrmk + 9348U, // VUNPCKHPDZrmkz + 4U, // VUNPCKHPDZrr + 0U, // VUNPCKHPDZrrk + 9348U, // VUNPCKHPDZrrkz + 4U, // VUNPCKHPDrm + 4U, // VUNPCKHPDrr + 4U, // VUNPCKHPSYrm + 4U, // VUNPCKHPSYrr + 4U, // VUNPCKHPSZ128rm + 72U, // VUNPCKHPSZ128rmb + 133U, // VUNPCKHPSZ128rmbk + 9348U, // VUNPCKHPSZ128rmbkz + 0U, // VUNPCKHPSZ128rmk + 9348U, // VUNPCKHPSZ128rmkz + 4U, // VUNPCKHPSZ128rr + 0U, // VUNPCKHPSZ128rrk + 9348U, // VUNPCKHPSZ128rrkz + 4U, // VUNPCKHPSZ256rm + 72U, // VUNPCKHPSZ256rmb + 133U, // VUNPCKHPSZ256rmbk + 9348U, // VUNPCKHPSZ256rmbkz + 0U, // VUNPCKHPSZ256rmk + 9348U, // VUNPCKHPSZ256rmkz + 4U, // VUNPCKHPSZ256rr + 0U, // VUNPCKHPSZ256rrk + 9348U, // VUNPCKHPSZ256rrkz + 4U, // VUNPCKHPSZrm + 72U, // VUNPCKHPSZrmb + 133U, // VUNPCKHPSZrmbk + 9348U, // VUNPCKHPSZrmbkz + 0U, // VUNPCKHPSZrmk + 9348U, // VUNPCKHPSZrmkz + 4U, // VUNPCKHPSZrr + 0U, // VUNPCKHPSZrrk + 9348U, // VUNPCKHPSZrrkz + 4U, // VUNPCKHPSrm + 4U, // VUNPCKHPSrr + 4U, // VUNPCKLPDYrm + 4U, // VUNPCKLPDYrr + 4U, // VUNPCKLPDZ128rm + 72U, // VUNPCKLPDZ128rmb + 133U, // VUNPCKLPDZ128rmbk + 9348U, // VUNPCKLPDZ128rmbkz + 0U, // VUNPCKLPDZ128rmk + 9348U, // VUNPCKLPDZ128rmkz + 4U, // VUNPCKLPDZ128rr + 0U, // VUNPCKLPDZ128rrk + 9348U, // VUNPCKLPDZ128rrkz + 4U, // VUNPCKLPDZ256rm + 72U, // VUNPCKLPDZ256rmb + 133U, // VUNPCKLPDZ256rmbk + 9348U, // VUNPCKLPDZ256rmbkz + 0U, // VUNPCKLPDZ256rmk + 9348U, // VUNPCKLPDZ256rmkz + 4U, // VUNPCKLPDZ256rr + 0U, // VUNPCKLPDZ256rrk + 9348U, // VUNPCKLPDZ256rrkz + 4U, // VUNPCKLPDZrm + 72U, // VUNPCKLPDZrmb + 133U, // VUNPCKLPDZrmbk + 9348U, // VUNPCKLPDZrmbkz + 0U, // VUNPCKLPDZrmk + 9348U, // VUNPCKLPDZrmkz + 4U, // VUNPCKLPDZrr + 0U, // VUNPCKLPDZrrk + 9348U, // VUNPCKLPDZrrkz + 4U, // VUNPCKLPDrm + 4U, // VUNPCKLPDrr + 4U, // VUNPCKLPSYrm + 4U, // VUNPCKLPSYrr + 4U, // VUNPCKLPSZ128rm + 72U, // VUNPCKLPSZ128rmb + 133U, // VUNPCKLPSZ128rmbk + 9348U, // VUNPCKLPSZ128rmbkz + 0U, // VUNPCKLPSZ128rmk + 9348U, // VUNPCKLPSZ128rmkz + 4U, // VUNPCKLPSZ128rr + 0U, // VUNPCKLPSZ128rrk + 9348U, // VUNPCKLPSZ128rrkz + 4U, // VUNPCKLPSZ256rm + 72U, // VUNPCKLPSZ256rmb + 133U, // VUNPCKLPSZ256rmbk + 9348U, // VUNPCKLPSZ256rmbkz + 0U, // VUNPCKLPSZ256rmk + 9348U, // VUNPCKLPSZ256rmkz + 4U, // VUNPCKLPSZ256rr + 0U, // VUNPCKLPSZ256rrk + 9348U, // VUNPCKLPSZ256rrkz + 4U, // VUNPCKLPSZrm + 72U, // VUNPCKLPSZrmb + 133U, // VUNPCKLPSZrmbk + 9348U, // VUNPCKLPSZrmbkz + 0U, // VUNPCKLPSZrmk + 9348U, // VUNPCKLPSZrmkz + 4U, // VUNPCKLPSZrr + 0U, // VUNPCKLPSZrrk + 9348U, // VUNPCKLPSZrrkz + 4U, // VUNPCKLPSrm + 4U, // VUNPCKLPSrr + 4U, // VXORPDYrm + 4U, // VXORPDYrr + 4U, // VXORPDZ128rm + 72U, // VXORPDZ128rmb + 133U, // VXORPDZ128rmbk + 9348U, // VXORPDZ128rmbkz + 0U, // VXORPDZ128rmk + 9348U, // VXORPDZ128rmkz + 4U, // VXORPDZ128rr + 0U, // VXORPDZ128rrk + 9348U, // VXORPDZ128rrkz + 4U, // VXORPDZ256rm + 72U, // VXORPDZ256rmb + 133U, // VXORPDZ256rmbk + 9348U, // VXORPDZ256rmbkz + 0U, // VXORPDZ256rmk + 9348U, // VXORPDZ256rmkz + 4U, // VXORPDZ256rr + 0U, // VXORPDZ256rrk + 9348U, // VXORPDZ256rrkz + 4U, // VXORPDZrm + 72U, // VXORPDZrmb + 133U, // VXORPDZrmbk + 9348U, // VXORPDZrmbkz + 0U, // VXORPDZrmk + 9348U, // VXORPDZrmkz + 4U, // VXORPDZrr + 0U, // VXORPDZrrk + 9348U, // VXORPDZrrkz + 4U, // VXORPDrm + 4U, // VXORPDrr + 4U, // VXORPSYrm + 4U, // VXORPSYrr + 4U, // VXORPSZ128rm + 72U, // VXORPSZ128rmb + 133U, // VXORPSZ128rmbk + 9348U, // VXORPSZ128rmbkz + 0U, // VXORPSZ128rmk + 9348U, // VXORPSZ128rmkz + 4U, // VXORPSZ128rr + 0U, // VXORPSZ128rrk + 9348U, // VXORPSZ128rrkz + 4U, // VXORPSZ256rm + 72U, // VXORPSZ256rmb + 133U, // VXORPSZ256rmbk + 9348U, // VXORPSZ256rmbkz + 0U, // VXORPSZ256rmk + 9348U, // VXORPSZ256rmkz + 4U, // VXORPSZ256rr + 0U, // VXORPSZ256rrk + 9348U, // VXORPSZ256rrkz + 4U, // VXORPSZrm + 72U, // VXORPSZrmb + 133U, // VXORPSZrmbk + 9348U, // VXORPSZrmbkz + 0U, // VXORPSZrmk + 9348U, // VXORPSZrmkz + 4U, // VXORPSZrr + 0U, // VXORPSZrrk + 9348U, // VXORPSZrrkz + 4U, // VXORPSrm + 4U, // VXORPSrr + 0U, // VZEROALL + 0U, // VZEROUPPER + 0U, // WAIT + 0U, // WBINVD + 0U, // WBNOINVD + 0U, // WRFSBASE + 0U, // WRFSBASE64 + 0U, // WRGSBASE + 0U, // WRGSBASE64 + 0U, // WRMSR + 0U, // WRPKRUr + 0U, // WRSSD + 0U, // WRSSQ + 0U, // WRUSSD + 0U, // WRUSSQ + 0U, // XABORT + 0U, // XACQUIRE_PREFIX + 3U, // XADD16rm + 0U, // XADD16rr + 3U, // XADD32rm + 0U, // XADD32rr + 3U, // XADD64rm + 0U, // XADD64rr + 3U, // XADD8rm + 0U, // XADD8rr + 0U, // XBEGIN_2 + 0U, // XBEGIN_4 + 0U, // XCHG16ar + 3U, // XCHG16rm + 0U, // XCHG16rr + 0U, // XCHG32ar + 3U, // XCHG32rm + 0U, // XCHG32rr + 0U, // XCHG64ar + 3U, // XCHG64rm + 0U, // XCHG64rr + 3U, // XCHG8rm + 0U, // XCHG8rr + 0U, // XCH_F + 0U, // XCRYPTCBC + 0U, // XCRYPTCFB + 0U, // XCRYPTCTR + 0U, // XCRYPTECB + 0U, // XCRYPTOFB + 0U, // XEND + 0U, // XGETBV + 0U, // XLAT + 0U, // XOR16i16 + 0U, // XOR16mi + 0U, // XOR16mi8 + 0U, // XOR16mr + 0U, // XOR16ri + 0U, // XOR16ri8 + 0U, // XOR16rm + 0U, // XOR16rr + 0U, // XOR16rr_REV + 0U, // XOR32i32 + 0U, // XOR32mi + 0U, // XOR32mi8 + 0U, // XOR32mr + 0U, // XOR32ri + 0U, // XOR32ri8 + 0U, // XOR32rm + 0U, // XOR32rr + 0U, // XOR32rr_REV + 0U, // XOR64i32 + 0U, // XOR64mi32 + 0U, // XOR64mi8 + 0U, // XOR64mr + 0U, // XOR64ri32 + 0U, // XOR64ri8 + 0U, // XOR64rm + 0U, // XOR64rr + 0U, // XOR64rr_REV + 0U, // XOR8i8 + 0U, // XOR8mi + 0U, // XOR8mi8 + 0U, // XOR8mr + 0U, // XOR8ri + 0U, // XOR8ri8 + 0U, // XOR8rm + 0U, // XOR8rr + 0U, // XOR8rr_REV + 0U, // XORPDrm + 0U, // XORPDrr + 0U, // XORPSrm + 0U, // XORPSrr + 0U, // XRELEASE_PREFIX + 0U, // XRSTOR + 0U, // XRSTOR64 + 0U, // XRSTORS + 0U, // XRSTORS64 + 0U, // XSAVE + 0U, // XSAVE64 + 0U, // XSAVEC + 0U, // XSAVEC64 + 0U, // XSAVEOPT + 0U, // XSAVEOPT64 + 0U, // XSAVES + 0U, // XSAVES64 + 0U, // XSETBV + 0U, // XSHA1 + 0U, // XSHA256 + 0U, // XSTORE + 0U, // XTEST + }; + + static const uint8_t OpInfo2[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // AVX1_SETALLONES + 0U, // AVX2_SETALLONES + 0U, // AVX512_128_SET0 + 0U, // AVX512_256_SET0 + 0U, // AVX512_512_SET0 + 0U, // AVX512_512_SETALLONES + 0U, // AVX512_512_SEXT_MASK_32 + 0U, // AVX512_512_SEXT_MASK_64 + 0U, // AVX512_FsFLD0SD + 0U, // AVX512_FsFLD0SS + 0U, // AVX_SET0 + 0U, // KSET0D + 0U, // KSET0Q + 0U, // KSET0W + 0U, // KSET1D + 0U, // KSET1Q + 0U, // KSET1W + 0U, // MMX_SET0 + 0U, // V_SET0 + 0U, // V_SETALLONES + 0U, // AAA + 0U, // AAD8i8 + 0U, // AAM8i8 + 0U, // AAS + 0U, // ABS_F + 0U, // ABS_Fp32 + 0U, // ABS_Fp64 + 0U, // ABS_Fp80 + 0U, // ADC16i16 + 0U, // ADC16mi + 0U, // ADC16mi8 + 0U, // ADC16mr + 0U, // ADC16ri + 0U, // ADC16ri8 + 0U, // ADC16rm + 0U, // ADC16rr + 0U, // ADC16rr_REV + 0U, // ADC32i32 + 0U, // ADC32mi + 0U, // ADC32mi8 + 0U, // ADC32mr + 0U, // ADC32ri + 0U, // ADC32ri8 + 0U, // ADC32rm + 0U, // ADC32rr + 0U, // ADC32rr_REV + 0U, // ADC64i32 + 0U, // ADC64mi32 + 0U, // ADC64mi8 + 0U, // ADC64mr + 0U, // ADC64ri32 + 0U, // ADC64ri8 + 0U, // ADC64rm + 0U, // ADC64rr + 0U, // ADC64rr_REV + 0U, // ADC8i8 + 0U, // ADC8mi + 0U, // ADC8mi8 + 0U, // ADC8mr + 0U, // ADC8ri + 0U, // ADC8ri8 + 0U, // ADC8rm + 0U, // ADC8rr + 0U, // ADC8rr_REV + 0U, // ADCX32rm + 0U, // ADCX32rr + 0U, // ADCX64rm + 0U, // ADCX64rr + 0U, // ADD16i16 + 0U, // ADD16mi + 0U, // ADD16mi8 + 0U, // ADD16mr + 0U, // ADD16ri + 0U, // ADD16ri8 + 0U, // ADD16rm + 0U, // ADD16rr + 0U, // ADD16rr_REV + 0U, // ADD32i32 + 0U, // ADD32mi + 0U, // ADD32mi8 + 0U, // ADD32mr + 0U, // ADD32ri + 0U, // ADD32ri8 + 0U, // ADD32rm + 0U, // ADD32rr + 0U, // ADD32rr_REV + 0U, // ADD64i32 + 0U, // ADD64mi32 + 0U, // ADD64mi8 + 0U, // ADD64mr + 0U, // ADD64ri32 + 0U, // ADD64ri8 + 0U, // ADD64rm + 0U, // ADD64rr + 0U, // ADD64rr_REV + 0U, // ADD8i8 + 0U, // ADD8mi + 0U, // ADD8mi8 + 0U, // ADD8mr + 0U, // ADD8ri + 0U, // ADD8ri8 + 0U, // ADD8rm + 0U, // ADD8rr + 0U, // ADD8rr_REV + 0U, // ADDPDrm + 0U, // ADDPDrr + 0U, // ADDPSrm + 0U, // ADDPSrr + 0U, // ADDSDrm + 0U, // ADDSDrm_Int + 0U, // ADDSDrr + 0U, // ADDSDrr_Int + 0U, // ADDSSrm + 0U, // ADDSSrm_Int + 0U, // ADDSSrr + 0U, // ADDSSrr_Int + 0U, // ADDSUBPDrm + 0U, // ADDSUBPDrr + 0U, // ADDSUBPSrm + 0U, // ADDSUBPSrr + 0U, // ADD_F32m + 0U, // ADD_F64m + 0U, // ADD_FI16m + 0U, // ADD_FI32m + 0U, // ADD_FPrST0 + 0U, // ADD_FST0r + 0U, // ADD_Fp32 + 0U, // ADD_Fp32m + 0U, // ADD_Fp64 + 0U, // ADD_Fp64m + 0U, // ADD_Fp64m32 + 0U, // ADD_Fp80 + 0U, // ADD_Fp80m32 + 0U, // ADD_Fp80m64 + 0U, // ADD_FpI16m32 + 0U, // ADD_FpI16m64 + 0U, // ADD_FpI16m80 + 0U, // ADD_FpI32m32 + 0U, // ADD_FpI32m64 + 0U, // ADD_FpI32m80 + 0U, // ADD_FrST0 + 0U, // ADOX32rm + 0U, // ADOX32rr + 0U, // ADOX64rm + 0U, // ADOX64rr + 0U, // AESDECLASTrm + 0U, // AESDECLASTrr + 0U, // AESDECrm + 0U, // AESDECrr + 0U, // AESENCLASTrm + 0U, // AESENCLASTrr + 0U, // AESENCrm + 0U, // AESENCrr + 0U, // AESIMCrm + 0U, // AESIMCrr + 0U, // AESKEYGENASSIST128rm + 0U, // AESKEYGENASSIST128rr + 0U, // AND16i16 + 0U, // AND16mi + 0U, // AND16mi8 + 0U, // AND16mr + 0U, // AND16ri + 0U, // AND16ri8 + 0U, // AND16rm + 0U, // AND16rr + 0U, // AND16rr_REV + 0U, // AND32i32 + 0U, // AND32mi + 0U, // AND32mi8 + 0U, // AND32mr + 0U, // AND32ri + 0U, // AND32ri8 + 0U, // AND32rm + 0U, // AND32rr + 0U, // AND32rr_REV + 0U, // AND64i32 + 0U, // AND64mi32 + 0U, // AND64mi8 + 0U, // AND64mr + 0U, // AND64ri32 + 0U, // AND64ri8 + 0U, // AND64rm + 0U, // AND64rr + 0U, // AND64rr_REV + 0U, // AND8i8 + 0U, // AND8mi + 0U, // AND8mi8 + 0U, // AND8mr + 0U, // AND8ri + 0U, // AND8ri8 + 0U, // AND8rm + 0U, // AND8rr + 0U, // AND8rr_REV + 0U, // ANDN32rm + 0U, // ANDN32rr + 0U, // ANDN64rm + 0U, // ANDN64rr + 0U, // ANDNPDrm + 0U, // ANDNPDrr + 0U, // ANDNPSrm + 0U, // ANDNPSrr + 0U, // ANDPDrm + 0U, // ANDPDrr + 0U, // ANDPSrm + 0U, // ANDPSrr + 0U, // ARPL16mr + 0U, // ARPL16rr + 0U, // BEXTR32rm + 0U, // BEXTR32rr + 0U, // BEXTR64rm + 0U, // BEXTR64rr + 0U, // BEXTRI32mi + 0U, // BEXTRI32ri + 0U, // BEXTRI64mi + 0U, // BEXTRI64ri + 0U, // BLCFILL32rm + 0U, // BLCFILL32rr + 0U, // BLCFILL64rm + 0U, // BLCFILL64rr + 0U, // BLCI32rm + 0U, // BLCI32rr + 0U, // BLCI64rm + 0U, // BLCI64rr + 0U, // BLCIC32rm + 0U, // BLCIC32rr + 0U, // BLCIC64rm + 0U, // BLCIC64rr + 0U, // BLCMSK32rm + 0U, // BLCMSK32rr + 0U, // BLCMSK64rm + 0U, // BLCMSK64rr + 0U, // BLCS32rm + 0U, // BLCS32rr + 0U, // BLCS64rm + 0U, // BLCS64rr + 0U, // BLENDPDrmi + 0U, // BLENDPDrri + 0U, // BLENDPSrmi + 0U, // BLENDPSrri + 0U, // BLENDVPDrm0 + 0U, // BLENDVPDrr0 + 0U, // BLENDVPSrm0 + 0U, // BLENDVPSrr0 + 0U, // BLSFILL32rm + 0U, // BLSFILL32rr + 0U, // BLSFILL64rm + 0U, // BLSFILL64rr + 0U, // BLSI32rm + 0U, // BLSI32rr + 0U, // BLSI64rm + 0U, // BLSI64rr + 0U, // BLSIC32rm + 0U, // BLSIC32rr + 0U, // BLSIC64rm + 0U, // BLSIC64rr + 0U, // BLSMSK32rm + 0U, // BLSMSK32rr + 0U, // BLSMSK64rm + 0U, // BLSMSK64rr + 0U, // BLSR32rm + 0U, // BLSR32rr + 0U, // BLSR64rm + 0U, // BLSR64rr + 0U, // BNDCL32rm + 0U, // BNDCL32rr + 0U, // BNDCL64rm + 0U, // BNDCL64rr + 0U, // BNDCN32rm + 0U, // BNDCN32rr + 0U, // BNDCN64rm + 0U, // BNDCN64rr + 0U, // BNDCU32rm + 0U, // BNDCU32rr + 0U, // BNDCU64rm + 0U, // BNDCU64rr + 0U, // BNDLDXrm + 0U, // BNDMK32rm + 0U, // BNDMK64rm + 0U, // BNDMOV32mr + 0U, // BNDMOV32rm + 0U, // BNDMOV64mr + 0U, // BNDMOV64rm + 0U, // BNDMOVrr + 0U, // BNDMOVrr_REV + 0U, // BNDSTXmr + 0U, // BOUNDS16rm + 0U, // BOUNDS32rm + 0U, // BSF16rm + 0U, // BSF16rr + 0U, // BSF32rm + 0U, // BSF32rr + 0U, // BSF64rm + 0U, // BSF64rr + 0U, // BSR16rm + 0U, // BSR16rr + 0U, // BSR32rm + 0U, // BSR32rr + 0U, // BSR64rm + 0U, // BSR64rr + 0U, // BSWAP16r_BAD + 0U, // BSWAP32r + 0U, // BSWAP64r + 0U, // BT16mi8 + 0U, // BT16mr + 0U, // BT16ri8 + 0U, // BT16rr + 0U, // BT32mi8 + 0U, // BT32mr + 0U, // BT32ri8 + 0U, // BT32rr + 0U, // BT64mi8 + 0U, // BT64mr + 0U, // BT64ri8 + 0U, // BT64rr + 0U, // BTC16mi8 + 0U, // BTC16mr + 0U, // BTC16ri8 + 0U, // BTC16rr + 0U, // BTC32mi8 + 0U, // BTC32mr + 0U, // BTC32ri8 + 0U, // BTC32rr + 0U, // BTC64mi8 + 0U, // BTC64mr + 0U, // BTC64ri8 + 0U, // BTC64rr + 0U, // BTR16mi8 + 0U, // BTR16mr + 0U, // BTR16ri8 + 0U, // BTR16rr + 0U, // BTR32mi8 + 0U, // BTR32mr + 0U, // BTR32ri8 + 0U, // BTR32rr + 0U, // BTR64mi8 + 0U, // BTR64mr + 0U, // BTR64ri8 + 0U, // BTR64rr + 0U, // BTS16mi8 + 0U, // BTS16mr + 0U, // BTS16ri8 + 0U, // BTS16rr + 0U, // BTS32mi8 + 0U, // BTS32mr + 0U, // BTS32ri8 + 0U, // BTS32rr + 0U, // BTS64mi8 + 0U, // BTS64mr + 0U, // BTS64ri8 + 0U, // BTS64rr + 0U, // BZHI32rm + 0U, // BZHI32rr + 0U, // BZHI64rm + 0U, // BZHI64rr + 0U, // CALL16m + 0U, // CALL16m_NT + 0U, // CALL16r + 0U, // CALL16r_NT + 0U, // CALL32m + 0U, // CALL32m_NT + 0U, // CALL32r + 0U, // CALL32r_NT + 0U, // CALL64m + 0U, // CALL64m_NT + 0U, // CALL64pcrel32 + 0U, // CALL64r + 0U, // CALL64r_NT + 0U, // CALLpcrel16 + 0U, // CALLpcrel32 + 0U, // CBW + 0U, // CDQ + 0U, // CDQE + 0U, // CHS_F + 0U, // CHS_Fp32 + 0U, // CHS_Fp64 + 0U, // CHS_Fp80 + 0U, // CLAC + 0U, // CLC + 0U, // CLD + 0U, // CLDEMOTE + 0U, // CLFLUSH + 0U, // CLFLUSHOPT + 0U, // CLGI + 0U, // CLI + 0U, // CLRSSBSY + 0U, // CLTS + 0U, // CLWB + 0U, // CLZEROr + 0U, // CMC + 0U, // CMOVA16rm + 0U, // CMOVA16rr + 0U, // CMOVA32rm + 0U, // CMOVA32rr + 0U, // CMOVA64rm + 0U, // CMOVA64rr + 0U, // CMOVAE16rm + 0U, // CMOVAE16rr + 0U, // CMOVAE32rm + 0U, // CMOVAE32rr + 0U, // CMOVAE64rm + 0U, // CMOVAE64rr + 0U, // CMOVB16rm + 0U, // CMOVB16rr + 0U, // CMOVB32rm + 0U, // CMOVB32rr + 0U, // CMOVB64rm + 0U, // CMOVB64rr + 0U, // CMOVBE16rm + 0U, // CMOVBE16rr + 0U, // CMOVBE32rm + 0U, // CMOVBE32rr + 0U, // CMOVBE64rm + 0U, // CMOVBE64rr + 0U, // CMOVBE_F + 0U, // CMOVBE_Fp32 + 0U, // CMOVBE_Fp64 + 0U, // CMOVBE_Fp80 + 0U, // CMOVB_F + 0U, // CMOVB_Fp32 + 0U, // CMOVB_Fp64 + 0U, // CMOVB_Fp80 + 0U, // CMOVE16rm + 0U, // CMOVE16rr + 0U, // CMOVE32rm + 0U, // CMOVE32rr + 0U, // CMOVE64rm + 0U, // CMOVE64rr + 0U, // CMOVE_F + 0U, // CMOVE_Fp32 + 0U, // CMOVE_Fp64 + 0U, // CMOVE_Fp80 + 0U, // CMOVG16rm + 0U, // CMOVG16rr + 0U, // CMOVG32rm + 0U, // CMOVG32rr + 0U, // CMOVG64rm + 0U, // CMOVG64rr + 0U, // CMOVGE16rm + 0U, // CMOVGE16rr + 0U, // CMOVGE32rm + 0U, // CMOVGE32rr + 0U, // CMOVGE64rm + 0U, // CMOVGE64rr + 0U, // CMOVL16rm + 0U, // CMOVL16rr + 0U, // CMOVL32rm + 0U, // CMOVL32rr + 0U, // CMOVL64rm + 0U, // CMOVL64rr + 0U, // CMOVLE16rm + 0U, // CMOVLE16rr + 0U, // CMOVLE32rm + 0U, // CMOVLE32rr + 0U, // CMOVLE64rm + 0U, // CMOVLE64rr + 0U, // CMOVNBE_F + 0U, // CMOVNBE_Fp32 + 0U, // CMOVNBE_Fp64 + 0U, // CMOVNBE_Fp80 + 0U, // CMOVNB_F + 0U, // CMOVNB_Fp32 + 0U, // CMOVNB_Fp64 + 0U, // CMOVNB_Fp80 + 0U, // CMOVNE16rm + 0U, // CMOVNE16rr + 0U, // CMOVNE32rm + 0U, // CMOVNE32rr + 0U, // CMOVNE64rm + 0U, // CMOVNE64rr + 0U, // CMOVNE_F + 0U, // CMOVNE_Fp32 + 0U, // CMOVNE_Fp64 + 0U, // CMOVNE_Fp80 + 0U, // CMOVNO16rm + 0U, // CMOVNO16rr + 0U, // CMOVNO32rm + 0U, // CMOVNO32rr + 0U, // CMOVNO64rm + 0U, // CMOVNO64rr + 0U, // CMOVNP16rm + 0U, // CMOVNP16rr + 0U, // CMOVNP32rm + 0U, // CMOVNP32rr + 0U, // CMOVNP64rm + 0U, // CMOVNP64rr + 0U, // CMOVNP_F + 0U, // CMOVNP_Fp32 + 0U, // CMOVNP_Fp64 + 0U, // CMOVNP_Fp80 + 0U, // CMOVNS16rm + 0U, // CMOVNS16rr + 0U, // CMOVNS32rm + 0U, // CMOVNS32rr + 0U, // CMOVNS64rm + 0U, // CMOVNS64rr + 0U, // CMOVO16rm + 0U, // CMOVO16rr + 0U, // CMOVO32rm + 0U, // CMOVO32rr + 0U, // CMOVO64rm + 0U, // CMOVO64rr + 0U, // CMOVP16rm + 0U, // CMOVP16rr + 0U, // CMOVP32rm + 0U, // CMOVP32rr + 0U, // CMOVP64rm + 0U, // CMOVP64rr + 0U, // CMOVP_F + 0U, // CMOVP_Fp32 + 0U, // CMOVP_Fp64 + 0U, // CMOVP_Fp80 + 0U, // CMOVS16rm + 0U, // CMOVS16rr + 0U, // CMOVS32rm + 0U, // CMOVS32rr + 0U, // CMOVS64rm + 0U, // CMOVS64rr + 0U, // CMP16i16 + 0U, // CMP16mi + 0U, // CMP16mi8 + 0U, // CMP16mr + 0U, // CMP16ri + 0U, // CMP16ri8 + 0U, // CMP16rm + 0U, // CMP16rr + 0U, // CMP16rr_REV + 0U, // CMP32i32 + 0U, // CMP32mi + 0U, // CMP32mi8 + 0U, // CMP32mr + 0U, // CMP32ri + 0U, // CMP32ri8 + 0U, // CMP32rm + 0U, // CMP32rr + 0U, // CMP32rr_REV + 0U, // CMP64i32 + 0U, // CMP64mi32 + 0U, // CMP64mi8 + 0U, // CMP64mr + 0U, // CMP64ri32 + 0U, // CMP64ri8 + 0U, // CMP64rm + 0U, // CMP64rr + 0U, // CMP64rr_REV + 0U, // CMP8i8 + 0U, // CMP8mi + 0U, // CMP8mi8 + 0U, // CMP8mr + 0U, // CMP8ri + 0U, // CMP8ri8 + 0U, // CMP8rm + 0U, // CMP8rr + 0U, // CMP8rr_REV + 0U, // CMPPDrmi + 0U, // CMPPDrmi_alt + 0U, // CMPPDrri + 0U, // CMPPDrri_alt + 0U, // CMPPSrmi + 0U, // CMPPSrmi_alt + 0U, // CMPPSrri + 0U, // CMPPSrri_alt + 0U, // CMPSB + 0U, // CMPSDrm + 0U, // CMPSDrm_Int + 0U, // CMPSDrm_alt + 0U, // CMPSDrr + 0U, // CMPSDrr_Int + 0U, // CMPSDrr_alt + 0U, // CMPSL + 0U, // CMPSQ + 0U, // CMPSSrm + 0U, // CMPSSrm_Int + 0U, // CMPSSrm_alt + 0U, // CMPSSrr + 0U, // CMPSSrr_Int + 0U, // CMPSSrr_alt + 0U, // CMPSW + 0U, // CMPXCHG16B + 0U, // CMPXCHG16rm + 0U, // CMPXCHG16rr + 0U, // CMPXCHG32rm + 0U, // CMPXCHG32rr + 0U, // CMPXCHG64rm + 0U, // CMPXCHG64rr + 0U, // CMPXCHG8B + 0U, // CMPXCHG8rm + 0U, // CMPXCHG8rr + 0U, // COMISDrm + 0U, // COMISDrm_Int + 0U, // COMISDrr + 0U, // COMISDrr_Int + 0U, // COMISSrm + 0U, // COMISSrm_Int + 0U, // COMISSrr + 0U, // COMISSrr_Int + 0U, // COMP_FST0r + 0U, // COM_FIPr + 0U, // COM_FIr + 0U, // COM_FST0r + 0U, // COS_F + 0U, // COS_Fp32 + 0U, // COS_Fp64 + 0U, // COS_Fp80 + 0U, // CPUID + 0U, // CQO + 0U, // CRC32r32m16 + 0U, // CRC32r32m32 + 0U, // CRC32r32m8 + 0U, // CRC32r32r16 + 0U, // CRC32r32r32 + 0U, // CRC32r32r8 + 0U, // CRC32r64m64 + 0U, // CRC32r64m8 + 0U, // CRC32r64r64 + 0U, // CRC32r64r8 + 0U, // CVTDQ2PDrm + 0U, // CVTDQ2PDrr + 0U, // CVTDQ2PSrm + 0U, // CVTDQ2PSrr + 0U, // CVTPD2DQrm + 0U, // CVTPD2DQrr + 0U, // CVTPD2PSrm + 0U, // CVTPD2PSrr + 0U, // CVTPS2DQrm + 0U, // CVTPS2DQrr + 0U, // CVTPS2PDrm + 0U, // CVTPS2PDrr + 0U, // CVTSD2SI64rm_Int + 0U, // CVTSD2SI64rr_Int + 0U, // CVTSD2SIrm_Int + 0U, // CVTSD2SIrr_Int + 0U, // CVTSD2SSrm + 0U, // CVTSD2SSrm_Int + 0U, // CVTSD2SSrr + 0U, // CVTSD2SSrr_Int + 0U, // CVTSI2SDrm + 0U, // CVTSI2SDrm_Int + 0U, // CVTSI2SDrr + 0U, // CVTSI2SDrr_Int + 0U, // CVTSI2SSrm + 0U, // CVTSI2SSrm_Int + 0U, // CVTSI2SSrr + 0U, // CVTSI2SSrr_Int + 0U, // CVTSI642SDrm + 0U, // CVTSI642SDrm_Int + 0U, // CVTSI642SDrr + 0U, // CVTSI642SDrr_Int + 0U, // CVTSI642SSrm + 0U, // CVTSI642SSrm_Int + 0U, // CVTSI642SSrr + 0U, // CVTSI642SSrr_Int + 0U, // CVTSS2SDrm + 0U, // CVTSS2SDrm_Int + 0U, // CVTSS2SDrr + 0U, // CVTSS2SDrr_Int + 0U, // CVTSS2SI64rm_Int + 0U, // CVTSS2SI64rr_Int + 0U, // CVTSS2SIrm_Int + 0U, // CVTSS2SIrr_Int + 0U, // CVTTPD2DQrm + 0U, // CVTTPD2DQrr + 0U, // CVTTPS2DQrm + 0U, // CVTTPS2DQrr + 0U, // CVTTSD2SI64rm + 0U, // CVTTSD2SI64rm_Int + 0U, // CVTTSD2SI64rr + 0U, // CVTTSD2SI64rr_Int + 0U, // CVTTSD2SIrm + 0U, // CVTTSD2SIrm_Int + 0U, // CVTTSD2SIrr + 0U, // CVTTSD2SIrr_Int + 0U, // CVTTSS2SI64rm + 0U, // CVTTSS2SI64rm_Int + 0U, // CVTTSS2SI64rr + 0U, // CVTTSS2SI64rr_Int + 0U, // CVTTSS2SIrm + 0U, // CVTTSS2SIrm_Int + 0U, // CVTTSS2SIrr + 0U, // CVTTSS2SIrr_Int + 0U, // CWD + 0U, // CWDE + 0U, // DAA + 0U, // DAS + 0U, // DATA16_PREFIX + 0U, // DEC16m + 0U, // DEC16r + 0U, // DEC16r_alt + 0U, // DEC32m + 0U, // DEC32r + 0U, // DEC32r_alt + 0U, // DEC64m + 0U, // DEC64r + 0U, // DEC8m + 0U, // DEC8r + 0U, // DIV16m + 0U, // DIV16r + 0U, // DIV32m + 0U, // DIV32r + 0U, // DIV64m + 0U, // DIV64r + 0U, // DIV8m + 0U, // DIV8r + 0U, // DIVPDrm + 0U, // DIVPDrr + 0U, // DIVPSrm + 0U, // DIVPSrr + 0U, // DIVR_F32m + 0U, // DIVR_F64m + 0U, // DIVR_FI16m + 0U, // DIVR_FI32m + 0U, // DIVR_FPrST0 + 0U, // DIVR_FST0r + 0U, // DIVR_Fp32m + 0U, // DIVR_Fp64m + 0U, // DIVR_Fp64m32 + 0U, // DIVR_Fp80m32 + 0U, // DIVR_Fp80m64 + 0U, // DIVR_FpI16m32 + 0U, // DIVR_FpI16m64 + 0U, // DIVR_FpI16m80 + 0U, // DIVR_FpI32m32 + 0U, // DIVR_FpI32m64 + 0U, // DIVR_FpI32m80 + 0U, // DIVR_FrST0 + 0U, // DIVSDrm + 0U, // DIVSDrm_Int + 0U, // DIVSDrr + 0U, // DIVSDrr_Int + 0U, // DIVSSrm + 0U, // DIVSSrm_Int + 0U, // DIVSSrr + 0U, // DIVSSrr_Int + 0U, // DIV_F32m + 0U, // DIV_F64m + 0U, // DIV_FI16m + 0U, // DIV_FI32m + 0U, // DIV_FPrST0 + 0U, // DIV_FST0r + 0U, // DIV_Fp32 + 0U, // DIV_Fp32m + 0U, // DIV_Fp64 + 0U, // DIV_Fp64m + 0U, // DIV_Fp64m32 + 0U, // DIV_Fp80 + 0U, // DIV_Fp80m32 + 0U, // DIV_Fp80m64 + 0U, // DIV_FpI16m32 + 0U, // DIV_FpI16m64 + 0U, // DIV_FpI16m80 + 0U, // DIV_FpI32m32 + 0U, // DIV_FpI32m64 + 0U, // DIV_FpI32m80 + 0U, // DIV_FrST0 + 0U, // DPPDrmi + 0U, // DPPDrri + 0U, // DPPSrmi + 0U, // DPPSrri + 0U, // ENCLS + 0U, // ENCLU + 0U, // ENCLV + 0U, // ENDBR32 + 0U, // ENDBR64 + 0U, // ENTER + 0U, // EXTRACTPSmr + 0U, // EXTRACTPSrr + 0U, // EXTRQ + 0U, // EXTRQI + 0U, // F2XM1 + 0U, // FARCALL16i + 0U, // FARCALL16m + 0U, // FARCALL32i + 0U, // FARCALL32m + 0U, // FARCALL64 + 0U, // FARJMP16i + 0U, // FARJMP16m + 0U, // FARJMP32i + 0U, // FARJMP32m + 0U, // FARJMP64 + 0U, // FBLDm + 0U, // FBSTPm + 0U, // FCOM32m + 0U, // FCOM64m + 0U, // FCOMP32m + 0U, // FCOMP64m + 0U, // FCOMPP + 0U, // FDECSTP + 0U, // FDISI8087_NOP + 0U, // FEMMS + 0U, // FENI8087_NOP + 0U, // FFREE + 0U, // FFREEP + 0U, // FICOM16m + 0U, // FICOM32m + 0U, // FICOMP16m + 0U, // FICOMP32m + 0U, // FINCSTP + 0U, // FLDCW16m + 0U, // FLDENVm + 0U, // FLDL2E + 0U, // FLDL2T + 0U, // FLDLG2 + 0U, // FLDLN2 + 0U, // FLDPI + 0U, // FNCLEX + 0U, // FNINIT + 0U, // FNOP + 0U, // FNSTCW16m + 0U, // FNSTSW16r + 0U, // FNSTSWm + 0U, // FPATAN + 0U, // FPNCEST0r + 0U, // FPREM + 0U, // FPREM1 + 0U, // FPTAN + 0U, // FRNDINT + 0U, // FRSTORm + 0U, // FSAVEm + 0U, // FSCALE + 0U, // FSETPM + 0U, // FSINCOS + 0U, // FSTENVm + 0U, // FXAM + 0U, // FXRSTOR + 0U, // FXRSTOR64 + 0U, // FXSAVE + 0U, // FXSAVE64 + 0U, // FXTRACT + 0U, // FYL2X + 0U, // FYL2XP1 + 0U, // GETSEC + 0U, // GF2P8AFFINEINVQBrmi + 0U, // GF2P8AFFINEINVQBrri + 0U, // GF2P8AFFINEQBrmi + 0U, // GF2P8AFFINEQBrri + 0U, // GF2P8MULBrm + 0U, // GF2P8MULBrr + 0U, // HADDPDrm + 0U, // HADDPDrr + 0U, // HADDPSrm + 0U, // HADDPSrr + 0U, // HLT + 0U, // HSUBPDrm + 0U, // HSUBPDrr + 0U, // HSUBPSrm + 0U, // HSUBPSrr + 0U, // IDIV16m + 0U, // IDIV16r + 0U, // IDIV32m + 0U, // IDIV32r + 0U, // IDIV64m + 0U, // IDIV64r + 0U, // IDIV8m + 0U, // IDIV8r + 0U, // ILD_F16m + 0U, // ILD_F32m + 0U, // ILD_F64m + 0U, // ILD_Fp16m32 + 0U, // ILD_Fp16m64 + 0U, // ILD_Fp16m80 + 0U, // ILD_Fp32m32 + 0U, // ILD_Fp32m64 + 0U, // ILD_Fp32m80 + 0U, // ILD_Fp64m32 + 0U, // ILD_Fp64m64 + 0U, // ILD_Fp64m80 + 0U, // IMUL16m + 0U, // IMUL16r + 0U, // IMUL16rm + 0U, // IMUL16rmi + 0U, // IMUL16rmi8 + 0U, // IMUL16rr + 0U, // IMUL16rri + 0U, // IMUL16rri8 + 0U, // IMUL32m + 0U, // IMUL32r + 0U, // IMUL32rm + 0U, // IMUL32rmi + 0U, // IMUL32rmi8 + 0U, // IMUL32rr + 0U, // IMUL32rri + 0U, // IMUL32rri8 + 0U, // IMUL64m + 0U, // IMUL64r + 0U, // IMUL64rm + 0U, // IMUL64rmi32 + 0U, // IMUL64rmi8 + 0U, // IMUL64rr + 0U, // IMUL64rri32 + 0U, // IMUL64rri8 + 0U, // IMUL8m + 0U, // IMUL8r + 0U, // IN16ri + 0U, // IN16rr + 0U, // IN32ri + 0U, // IN32rr + 0U, // IN8ri + 0U, // IN8rr + 0U, // INC16m + 0U, // INC16r + 0U, // INC16r_alt + 0U, // INC32m + 0U, // INC32r + 0U, // INC32r_alt + 0U, // INC64m + 0U, // INC64r + 0U, // INC8m + 0U, // INC8r + 0U, // INCSSPD + 0U, // INCSSPQ + 0U, // INSB + 0U, // INSERTPSrm + 0U, // INSERTPSrr + 0U, // INSERTQ + 0U, // INSERTQI + 0U, // INSL + 0U, // INSW + 0U, // INT + 0U, // INT1 + 0U, // INT3 + 0U, // INTO + 0U, // INVD + 0U, // INVEPT32 + 0U, // INVEPT64 + 0U, // INVLPG + 0U, // INVLPGA32 + 0U, // INVLPGA64 + 0U, // INVPCID32 + 0U, // INVPCID64 + 0U, // INVVPID32 + 0U, // INVVPID64 + 0U, // IRET16 + 0U, // IRET32 + 0U, // IRET64 + 0U, // ISTT_FP16m + 0U, // ISTT_FP32m + 0U, // ISTT_FP64m + 0U, // ISTT_Fp16m32 + 0U, // ISTT_Fp16m64 + 0U, // ISTT_Fp16m80 + 0U, // ISTT_Fp32m32 + 0U, // ISTT_Fp32m64 + 0U, // ISTT_Fp32m80 + 0U, // ISTT_Fp64m32 + 0U, // ISTT_Fp64m64 + 0U, // ISTT_Fp64m80 + 0U, // IST_F16m + 0U, // IST_F32m + 0U, // IST_FP16m + 0U, // IST_FP32m + 0U, // IST_FP64m + 0U, // IST_Fp16m32 + 0U, // IST_Fp16m64 + 0U, // IST_Fp16m80 + 0U, // IST_Fp32m32 + 0U, // IST_Fp32m64 + 0U, // IST_Fp32m80 + 0U, // IST_Fp64m32 + 0U, // IST_Fp64m64 + 0U, // IST_Fp64m80 + 0U, // JAE_1 + 0U, // JAE_2 + 0U, // JAE_4 + 0U, // JA_1 + 0U, // JA_2 + 0U, // JA_4 + 0U, // JBE_1 + 0U, // JBE_2 + 0U, // JBE_4 + 0U, // JB_1 + 0U, // JB_2 + 0U, // JB_4 + 0U, // JCXZ + 0U, // JECXZ + 0U, // JE_1 + 0U, // JE_2 + 0U, // JE_4 + 0U, // JGE_1 + 0U, // JGE_2 + 0U, // JGE_4 + 0U, // JG_1 + 0U, // JG_2 + 0U, // JG_4 + 0U, // JLE_1 + 0U, // JLE_2 + 0U, // JLE_4 + 0U, // JL_1 + 0U, // JL_2 + 0U, // JL_4 + 0U, // JMP16m + 0U, // JMP16m_NT + 0U, // JMP16r + 0U, // JMP16r_NT + 0U, // JMP32m + 0U, // JMP32m_NT + 0U, // JMP32r + 0U, // JMP32r_NT + 0U, // JMP64m + 0U, // JMP64m_NT + 0U, // JMP64r + 0U, // JMP64r_NT + 0U, // JMP_1 + 0U, // JMP_2 + 0U, // JMP_4 + 0U, // JNE_1 + 0U, // JNE_2 + 0U, // JNE_4 + 0U, // JNO_1 + 0U, // JNO_2 + 0U, // JNO_4 + 0U, // JNP_1 + 0U, // JNP_2 + 0U, // JNP_4 + 0U, // JNS_1 + 0U, // JNS_2 + 0U, // JNS_4 + 0U, // JO_1 + 0U, // JO_2 + 0U, // JO_4 + 0U, // JP_1 + 0U, // JP_2 + 0U, // JP_4 + 0U, // JRCXZ + 0U, // JS_1 + 0U, // JS_2 + 0U, // JS_4 + 0U, // KADDBrr + 0U, // KADDDrr + 0U, // KADDQrr + 0U, // KADDWrr + 0U, // KANDBrr + 0U, // KANDDrr + 0U, // KANDNBrr + 0U, // KANDNDrr + 0U, // KANDNQrr + 0U, // KANDNWrr + 0U, // KANDQrr + 0U, // KANDWrr + 0U, // KMOVBkk + 0U, // KMOVBkm + 0U, // KMOVBkr + 0U, // KMOVBmk + 0U, // KMOVBrk + 0U, // KMOVDkk + 0U, // KMOVDkm + 0U, // KMOVDkr + 0U, // KMOVDmk + 0U, // KMOVDrk + 0U, // KMOVQkk + 0U, // KMOVQkm + 0U, // KMOVQkr + 0U, // KMOVQmk + 0U, // KMOVQrk + 0U, // KMOVWkk + 0U, // KMOVWkm + 0U, // KMOVWkr + 0U, // KMOVWmk + 0U, // KMOVWrk + 0U, // KNOTBrr + 0U, // KNOTDrr + 0U, // KNOTQrr + 0U, // KNOTWrr + 0U, // KORBrr + 0U, // KORDrr + 0U, // KORQrr + 0U, // KORTESTBrr + 0U, // KORTESTDrr + 0U, // KORTESTQrr + 0U, // KORTESTWrr + 0U, // KORWrr + 0U, // KSHIFTLBri + 0U, // KSHIFTLDri + 0U, // KSHIFTLQri + 0U, // KSHIFTLWri + 0U, // KSHIFTRBri + 0U, // KSHIFTRDri + 0U, // KSHIFTRQri + 0U, // KSHIFTRWri + 0U, // KTESTBrr + 0U, // KTESTDrr + 0U, // KTESTQrr + 0U, // KTESTWrr + 0U, // KUNPCKBWrr + 0U, // KUNPCKDQrr + 0U, // KUNPCKWDrr + 0U, // KXNORBrr + 0U, // KXNORDrr + 0U, // KXNORQrr + 0U, // KXNORWrr + 0U, // KXORBrr + 0U, // KXORDrr + 0U, // KXORQrr + 0U, // KXORWrr + 0U, // LAHF + 0U, // LAR16rm + 0U, // LAR16rr + 0U, // LAR32rm + 0U, // LAR32rr + 0U, // LAR64rm + 0U, // LAR64rr + 0U, // LDDQUrm + 0U, // LDMXCSR + 0U, // LDS16rm + 0U, // LDS32rm + 0U, // LD_F0 + 0U, // LD_F1 + 0U, // LD_F32m + 0U, // LD_F64m + 0U, // LD_F80m + 0U, // LD_Fp032 + 0U, // LD_Fp064 + 0U, // LD_Fp080 + 0U, // LD_Fp132 + 0U, // LD_Fp164 + 0U, // LD_Fp180 + 0U, // LD_Fp32m + 0U, // LD_Fp32m64 + 0U, // LD_Fp32m80 + 0U, // LD_Fp64m + 0U, // LD_Fp64m80 + 0U, // LD_Fp80m + 0U, // LD_Frr + 0U, // LEA16r + 0U, // LEA32r + 0U, // LEA64_32r + 0U, // LEA64r + 0U, // LEAVE + 0U, // LEAVE64 + 0U, // LES16rm + 0U, // LES32rm + 0U, // LFENCE + 0U, // LFS16rm + 0U, // LFS32rm + 0U, // LFS64rm + 0U, // LGDT16m + 0U, // LGDT32m + 0U, // LGDT64m + 0U, // LGS16rm + 0U, // LGS32rm + 0U, // LGS64rm + 0U, // LIDT16m + 0U, // LIDT32m + 0U, // LIDT64m + 0U, // LLDT16m + 0U, // LLDT16r + 0U, // LLWPCB + 0U, // LLWPCB64 + 0U, // LMSW16m + 0U, // LMSW16r + 0U, // LOCK_PREFIX + 0U, // LODSB + 0U, // LODSL + 0U, // LODSQ + 0U, // LODSW + 0U, // LOOP + 0U, // LOOPE + 0U, // LOOPNE + 0U, // LRETIL + 0U, // LRETIQ + 0U, // LRETIW + 0U, // LRETL + 0U, // LRETQ + 0U, // LRETW + 0U, // LSL16rm + 0U, // LSL16rr + 0U, // LSL32rm + 0U, // LSL32rr + 0U, // LSL64rm + 0U, // LSL64rr + 0U, // LSS16rm + 0U, // LSS32rm + 0U, // LSS64rm + 0U, // LTRm + 0U, // LTRr + 0U, // LWPINS32rmi + 0U, // LWPINS32rri + 0U, // LWPINS64rmi + 0U, // LWPINS64rri + 0U, // LWPVAL32rmi + 0U, // LWPVAL32rri + 0U, // LWPVAL64rmi + 0U, // LWPVAL64rri + 0U, // LZCNT16rm + 0U, // LZCNT16rr + 0U, // LZCNT32rm + 0U, // LZCNT32rr + 0U, // LZCNT64rm + 0U, // LZCNT64rr + 0U, // MASKMOVDQU + 0U, // MASKMOVDQU64 + 0U, // MAXCPDrm + 0U, // MAXCPDrr + 0U, // MAXCPSrm + 0U, // MAXCPSrr + 0U, // MAXCSDrm + 0U, // MAXCSDrr + 0U, // MAXCSSrm + 0U, // MAXCSSrr + 0U, // MAXPDrm + 0U, // MAXPDrr + 0U, // MAXPSrm + 0U, // MAXPSrr + 0U, // MAXSDrm + 0U, // MAXSDrm_Int + 0U, // MAXSDrr + 0U, // MAXSDrr_Int + 0U, // MAXSSrm + 0U, // MAXSSrm_Int + 0U, // MAXSSrr + 0U, // MAXSSrr_Int + 0U, // MFENCE + 0U, // MINCPDrm + 0U, // MINCPDrr + 0U, // MINCPSrm + 0U, // MINCPSrr + 0U, // MINCSDrm + 0U, // MINCSDrr + 0U, // MINCSSrm + 0U, // MINCSSrr + 0U, // MINPDrm + 0U, // MINPDrr + 0U, // MINPSrm + 0U, // MINPSrr + 0U, // MINSDrm + 0U, // MINSDrm_Int + 0U, // MINSDrr + 0U, // MINSDrr_Int + 0U, // MINSSrm + 0U, // MINSSrm_Int + 0U, // MINSSrr + 0U, // MINSSrr_Int + 0U, // MMX_CVTPD2PIirm + 0U, // MMX_CVTPD2PIirr + 0U, // MMX_CVTPI2PDirm + 0U, // MMX_CVTPI2PDirr + 0U, // MMX_CVTPI2PSirm + 0U, // MMX_CVTPI2PSirr + 0U, // MMX_CVTPS2PIirm + 0U, // MMX_CVTPS2PIirr + 0U, // MMX_CVTTPD2PIirm + 0U, // MMX_CVTTPD2PIirr + 0U, // MMX_CVTTPS2PIirm + 0U, // MMX_CVTTPS2PIirr + 0U, // MMX_EMMS + 0U, // MMX_MASKMOVQ + 0U, // MMX_MASKMOVQ64 + 0U, // MMX_MOVD64from64rm + 0U, // MMX_MOVD64from64rr + 0U, // MMX_MOVD64grr + 0U, // MMX_MOVD64mr + 0U, // MMX_MOVD64rm + 0U, // MMX_MOVD64rr + 0U, // MMX_MOVD64to64rm + 0U, // MMX_MOVD64to64rr + 0U, // MMX_MOVDQ2Qrr + 0U, // MMX_MOVFR642Qrr + 0U, // MMX_MOVNTQmr + 0U, // MMX_MOVQ2DQrr + 0U, // MMX_MOVQ2FR64rr + 0U, // MMX_MOVQ64mr + 0U, // MMX_MOVQ64rm + 0U, // MMX_MOVQ64rr + 0U, // MMX_MOVQ64rr_REV + 0U, // MMX_PABSBrm + 0U, // MMX_PABSBrr + 0U, // MMX_PABSDrm + 0U, // MMX_PABSDrr + 0U, // MMX_PABSWrm + 0U, // MMX_PABSWrr + 0U, // MMX_PACKSSDWirm + 0U, // MMX_PACKSSDWirr + 0U, // MMX_PACKSSWBirm + 0U, // MMX_PACKSSWBirr + 0U, // MMX_PACKUSWBirm + 0U, // MMX_PACKUSWBirr + 0U, // MMX_PADDBirm + 0U, // MMX_PADDBirr + 0U, // MMX_PADDDirm + 0U, // MMX_PADDDirr + 0U, // MMX_PADDQirm + 0U, // MMX_PADDQirr + 0U, // MMX_PADDSBirm + 0U, // MMX_PADDSBirr + 0U, // MMX_PADDSWirm + 0U, // MMX_PADDSWirr + 0U, // MMX_PADDUSBirm + 0U, // MMX_PADDUSBirr + 0U, // MMX_PADDUSWirm + 0U, // MMX_PADDUSWirr + 0U, // MMX_PADDWirm + 0U, // MMX_PADDWirr + 0U, // MMX_PALIGNRrmi + 0U, // MMX_PALIGNRrri + 0U, // MMX_PANDNirm + 0U, // MMX_PANDNirr + 0U, // MMX_PANDirm + 0U, // MMX_PANDirr + 0U, // MMX_PAVGBirm + 0U, // MMX_PAVGBirr + 0U, // MMX_PAVGWirm + 0U, // MMX_PAVGWirr + 0U, // MMX_PCMPEQBirm + 0U, // MMX_PCMPEQBirr + 0U, // MMX_PCMPEQDirm + 0U, // MMX_PCMPEQDirr + 0U, // MMX_PCMPEQWirm + 0U, // MMX_PCMPEQWirr + 0U, // MMX_PCMPGTBirm + 0U, // MMX_PCMPGTBirr + 0U, // MMX_PCMPGTDirm + 0U, // MMX_PCMPGTDirr + 0U, // MMX_PCMPGTWirm + 0U, // MMX_PCMPGTWirr + 0U, // MMX_PEXTRWrr + 0U, // MMX_PHADDDrm + 0U, // MMX_PHADDDrr + 0U, // MMX_PHADDSWrm + 0U, // MMX_PHADDSWrr + 0U, // MMX_PHADDWrm + 0U, // MMX_PHADDWrr + 0U, // MMX_PHSUBDrm + 0U, // MMX_PHSUBDrr + 0U, // MMX_PHSUBSWrm + 0U, // MMX_PHSUBSWrr + 0U, // MMX_PHSUBWrm + 0U, // MMX_PHSUBWrr + 0U, // MMX_PINSRWrm + 0U, // MMX_PINSRWrr + 0U, // MMX_PMADDUBSWrm + 0U, // MMX_PMADDUBSWrr + 0U, // MMX_PMADDWDirm + 0U, // MMX_PMADDWDirr + 0U, // MMX_PMAXSWirm + 0U, // MMX_PMAXSWirr + 0U, // MMX_PMAXUBirm + 0U, // MMX_PMAXUBirr + 0U, // MMX_PMINSWirm + 0U, // MMX_PMINSWirr + 0U, // MMX_PMINUBirm + 0U, // MMX_PMINUBirr + 0U, // MMX_PMOVMSKBrr + 0U, // MMX_PMULHRSWrm + 0U, // MMX_PMULHRSWrr + 0U, // MMX_PMULHUWirm + 0U, // MMX_PMULHUWirr + 0U, // MMX_PMULHWirm + 0U, // MMX_PMULHWirr + 0U, // MMX_PMULLWirm + 0U, // MMX_PMULLWirr + 0U, // MMX_PMULUDQirm + 0U, // MMX_PMULUDQirr + 0U, // MMX_PORirm + 0U, // MMX_PORirr + 0U, // MMX_PSADBWirm + 0U, // MMX_PSADBWirr + 0U, // MMX_PSHUFBrm + 0U, // MMX_PSHUFBrr + 0U, // MMX_PSHUFWmi + 0U, // MMX_PSHUFWri + 0U, // MMX_PSIGNBrm + 0U, // MMX_PSIGNBrr + 0U, // MMX_PSIGNDrm + 0U, // MMX_PSIGNDrr + 0U, // MMX_PSIGNWrm + 0U, // MMX_PSIGNWrr + 0U, // MMX_PSLLDri + 0U, // MMX_PSLLDrm + 0U, // MMX_PSLLDrr + 0U, // MMX_PSLLQri + 0U, // MMX_PSLLQrm + 0U, // MMX_PSLLQrr + 0U, // MMX_PSLLWri + 0U, // MMX_PSLLWrm + 0U, // MMX_PSLLWrr + 0U, // MMX_PSRADri + 0U, // MMX_PSRADrm + 0U, // MMX_PSRADrr + 0U, // MMX_PSRAWri + 0U, // MMX_PSRAWrm + 0U, // MMX_PSRAWrr + 0U, // MMX_PSRLDri + 0U, // MMX_PSRLDrm + 0U, // MMX_PSRLDrr + 0U, // MMX_PSRLQri + 0U, // MMX_PSRLQrm + 0U, // MMX_PSRLQrr + 0U, // MMX_PSRLWri + 0U, // MMX_PSRLWrm + 0U, // MMX_PSRLWrr + 0U, // MMX_PSUBBirm + 0U, // MMX_PSUBBirr + 0U, // MMX_PSUBDirm + 0U, // MMX_PSUBDirr + 0U, // MMX_PSUBQirm + 0U, // MMX_PSUBQirr + 0U, // MMX_PSUBSBirm + 0U, // MMX_PSUBSBirr + 0U, // MMX_PSUBSWirm + 0U, // MMX_PSUBSWirr + 0U, // MMX_PSUBUSBirm + 0U, // MMX_PSUBUSBirr + 0U, // MMX_PSUBUSWirm + 0U, // MMX_PSUBUSWirr + 0U, // MMX_PSUBWirm + 0U, // MMX_PSUBWirr + 0U, // MMX_PUNPCKHBWirm + 0U, // MMX_PUNPCKHBWirr + 0U, // MMX_PUNPCKHDQirm + 0U, // MMX_PUNPCKHDQirr + 0U, // MMX_PUNPCKHWDirm + 0U, // MMX_PUNPCKHWDirr + 0U, // MMX_PUNPCKLBWirm + 0U, // MMX_PUNPCKLBWirr + 0U, // MMX_PUNPCKLDQirm + 0U, // MMX_PUNPCKLDQirr + 0U, // MMX_PUNPCKLWDirm + 0U, // MMX_PUNPCKLWDirr + 0U, // MMX_PXORirm + 0U, // MMX_PXORirr + 0U, // MONITORXrrr + 0U, // MONITORrrr + 0U, // MONTMUL + 0U, // MOV16ao16 + 0U, // MOV16ao32 + 0U, // MOV16ao64 + 0U, // MOV16mi + 0U, // MOV16mr + 0U, // MOV16ms + 0U, // MOV16o16a + 0U, // MOV16o32a + 0U, // MOV16o64a + 0U, // MOV16ri + 0U, // MOV16ri_alt + 0U, // MOV16rm + 0U, // MOV16rr + 0U, // MOV16rr_REV + 0U, // MOV16rs + 0U, // MOV16sm + 0U, // MOV16sr + 0U, // MOV32ao16 + 0U, // MOV32ao32 + 0U, // MOV32ao64 + 0U, // MOV32cr + 0U, // MOV32dr + 0U, // MOV32mi + 0U, // MOV32mr + 0U, // MOV32o16a + 0U, // MOV32o32a + 0U, // MOV32o64a + 0U, // MOV32rc + 0U, // MOV32rd + 0U, // MOV32ri + 0U, // MOV32ri_alt + 0U, // MOV32rm + 0U, // MOV32rr + 0U, // MOV32rr_REV + 0U, // MOV32rs + 0U, // MOV32sr + 0U, // MOV64ao32 + 0U, // MOV64ao64 + 0U, // MOV64cr + 0U, // MOV64dr + 0U, // MOV64mi32 + 0U, // MOV64mr + 0U, // MOV64o32a + 0U, // MOV64o64a + 0U, // MOV64rc + 0U, // MOV64rd + 0U, // MOV64ri + 0U, // MOV64ri32 + 0U, // MOV64rm + 0U, // MOV64rr + 0U, // MOV64rr_REV + 0U, // MOV64rs + 0U, // MOV64sr + 0U, // MOV64toPQIrm + 0U, // MOV64toPQIrr + 0U, // MOV64toSDrm + 0U, // MOV64toSDrr + 0U, // MOV8ao16 + 0U, // MOV8ao32 + 0U, // MOV8ao64 + 0U, // MOV8mi + 0U, // MOV8mr + 0U, // MOV8mr_NOREX + 0U, // MOV8o16a + 0U, // MOV8o32a + 0U, // MOV8o64a + 0U, // MOV8ri + 0U, // MOV8ri_alt + 0U, // MOV8rm + 0U, // MOV8rm_NOREX + 0U, // MOV8rr + 0U, // MOV8rr_NOREX + 0U, // MOV8rr_REV + 0U, // MOVAPDmr + 0U, // MOVAPDrm + 0U, // MOVAPDrr + 0U, // MOVAPDrr_REV + 0U, // MOVAPSmr + 0U, // MOVAPSrm + 0U, // MOVAPSrr + 0U, // MOVAPSrr_REV + 0U, // MOVBE16mr + 0U, // MOVBE16rm + 0U, // MOVBE32mr + 0U, // MOVBE32rm + 0U, // MOVBE64mr + 0U, // MOVBE64rm + 0U, // MOVDDUPrm + 0U, // MOVDDUPrr + 0U, // MOVDI2PDIrm + 0U, // MOVDI2PDIrr + 0U, // MOVDI2SSrm + 0U, // MOVDI2SSrr + 0U, // MOVDIR64B16 + 0U, // MOVDIR64B32 + 0U, // MOVDIR64B64 + 0U, // MOVDIRI32 + 0U, // MOVDIRI64 + 0U, // MOVDQAmr + 0U, // MOVDQArm + 0U, // MOVDQArr + 0U, // MOVDQArr_REV + 0U, // MOVDQUmr + 0U, // MOVDQUrm + 0U, // MOVDQUrr + 0U, // MOVDQUrr_REV + 0U, // MOVHLPSrr + 0U, // MOVHPDmr + 0U, // MOVHPDrm + 0U, // MOVHPSmr + 0U, // MOVHPSrm + 0U, // MOVLHPSrr + 0U, // MOVLPDmr + 0U, // MOVLPDrm + 0U, // MOVLPSmr + 0U, // MOVLPSrm + 0U, // MOVMSKPDrr + 0U, // MOVMSKPSrr + 0U, // MOVNTDQArm + 0U, // MOVNTDQmr + 0U, // MOVNTI_64mr + 0U, // MOVNTImr + 0U, // MOVNTPDmr + 0U, // MOVNTPSmr + 0U, // MOVNTSD + 0U, // MOVNTSS + 0U, // MOVPDI2DImr + 0U, // MOVPDI2DIrr + 0U, // MOVPQI2QImr + 0U, // MOVPQI2QIrr + 0U, // MOVPQIto64mr + 0U, // MOVPQIto64rr + 0U, // MOVQI2PQIrm + 0U, // MOVSB + 0U, // MOVSDmr + 0U, // MOVSDrm + 0U, // MOVSDrr + 0U, // MOVSDrr_REV + 0U, // MOVSDto64mr + 0U, // MOVSDto64rr + 0U, // MOVSHDUPrm + 0U, // MOVSHDUPrr + 0U, // MOVSL + 0U, // MOVSLDUPrm + 0U, // MOVSLDUPrr + 0U, // MOVSQ + 0U, // MOVSS2DImr + 0U, // MOVSS2DIrr + 0U, // MOVSSmr + 0U, // MOVSSrm + 0U, // MOVSSrr + 0U, // MOVSSrr_REV + 0U, // MOVSW + 0U, // MOVSX16rm16 + 0U, // MOVSX16rm8 + 0U, // MOVSX16rr16 + 0U, // MOVSX16rr8 + 0U, // MOVSX32rm16 + 0U, // MOVSX32rm8 + 0U, // MOVSX32rm8_NOREX + 0U, // MOVSX32rr16 + 0U, // MOVSX32rr8 + 0U, // MOVSX32rr8_NOREX + 0U, // MOVSX64rm16 + 0U, // MOVSX64rm32 + 0U, // MOVSX64rm8 + 0U, // MOVSX64rr16 + 0U, // MOVSX64rr32 + 0U, // MOVSX64rr8 + 0U, // MOVUPDmr + 0U, // MOVUPDrm + 0U, // MOVUPDrr + 0U, // MOVUPDrr_REV + 0U, // MOVUPSmr + 0U, // MOVUPSrm + 0U, // MOVUPSrr + 0U, // MOVUPSrr_REV + 0U, // MOVZPQILo2PQIrr + 0U, // MOVZX16rm16 + 0U, // MOVZX16rm8 + 0U, // MOVZX16rr16 + 0U, // MOVZX16rr8 + 0U, // MOVZX32rm16 + 0U, // MOVZX32rm8 + 0U, // MOVZX32rm8_NOREX + 0U, // MOVZX32rr16 + 0U, // MOVZX32rr8 + 0U, // MOVZX32rr8_NOREX + 0U, // MOVZX64rm16 + 0U, // MOVZX64rm8 + 0U, // MOVZX64rr16 + 0U, // MOVZX64rr8 + 0U, // MPSADBWrmi + 0U, // MPSADBWrri + 0U, // MUL16m + 0U, // MUL16r + 0U, // MUL32m + 0U, // MUL32r + 0U, // MUL64m + 0U, // MUL64r + 0U, // MUL8m + 0U, // MUL8r + 0U, // MULPDrm + 0U, // MULPDrr + 0U, // MULPSrm + 0U, // MULPSrr + 0U, // MULSDrm + 0U, // MULSDrm_Int + 0U, // MULSDrr + 0U, // MULSDrr_Int + 0U, // MULSSrm + 0U, // MULSSrm_Int + 0U, // MULSSrr + 0U, // MULSSrr_Int + 0U, // MULX32rm + 0U, // MULX32rr + 0U, // MULX64rm + 0U, // MULX64rr + 0U, // MUL_F32m + 0U, // MUL_F64m + 0U, // MUL_FI16m + 0U, // MUL_FI32m + 0U, // MUL_FPrST0 + 0U, // MUL_FST0r + 0U, // MUL_Fp32 + 0U, // MUL_Fp32m + 0U, // MUL_Fp64 + 0U, // MUL_Fp64m + 0U, // MUL_Fp64m32 + 0U, // MUL_Fp80 + 0U, // MUL_Fp80m32 + 0U, // MUL_Fp80m64 + 0U, // MUL_FpI16m32 + 0U, // MUL_FpI16m64 + 0U, // MUL_FpI16m80 + 0U, // MUL_FpI32m32 + 0U, // MUL_FpI32m64 + 0U, // MUL_FpI32m80 + 0U, // MUL_FrST0 + 0U, // MWAITXrrr + 0U, // MWAITrr + 0U, // NEG16m + 0U, // NEG16r + 0U, // NEG32m + 0U, // NEG32r + 0U, // NEG64m + 0U, // NEG64r + 0U, // NEG8m + 0U, // NEG8r + 0U, // NOOP + 0U, // NOOP18_16m4 + 0U, // NOOP18_16m5 + 0U, // NOOP18_16m6 + 0U, // NOOP18_16m7 + 0U, // NOOP18_16r4 + 0U, // NOOP18_16r5 + 0U, // NOOP18_16r6 + 0U, // NOOP18_16r7 + 0U, // NOOP18_m4 + 0U, // NOOP18_m5 + 0U, // NOOP18_m6 + 0U, // NOOP18_m7 + 0U, // NOOP18_r4 + 0U, // NOOP18_r5 + 0U, // NOOP18_r6 + 0U, // NOOP18_r7 + 0U, // NOOP19rr + 0U, // NOOPL + 0U, // NOOPL_19 + 0U, // NOOPL_1d + 0U, // NOOPL_1e + 0U, // NOOPLr + 0U, // NOOPQ + 0U, // NOOPQr + 0U, // NOOPW + 0U, // NOOPW_19 + 0U, // NOOPW_1c + 0U, // NOOPW_1d + 0U, // NOOPW_1e + 0U, // NOOPWr + 0U, // NOT16m + 0U, // NOT16r + 0U, // NOT32m + 0U, // NOT32r + 0U, // NOT64m + 0U, // NOT64r + 0U, // NOT8m + 0U, // NOT8r + 0U, // OR16i16 + 0U, // OR16mi + 0U, // OR16mi8 + 0U, // OR16mr + 0U, // OR16ri + 0U, // OR16ri8 + 0U, // OR16rm + 0U, // OR16rr + 0U, // OR16rr_REV + 0U, // OR32i32 + 0U, // OR32mi + 0U, // OR32mi8 + 0U, // OR32mr + 0U, // OR32ri + 0U, // OR32ri8 + 0U, // OR32rm + 0U, // OR32rr + 0U, // OR32rr_REV + 0U, // OR64i32 + 0U, // OR64mi32 + 0U, // OR64mi8 + 0U, // OR64mr + 0U, // OR64ri32 + 0U, // OR64ri8 + 0U, // OR64rm + 0U, // OR64rr + 0U, // OR64rr_REV + 0U, // OR8i8 + 0U, // OR8mi + 0U, // OR8mi8 + 0U, // OR8mr + 0U, // OR8ri + 0U, // OR8ri8 + 0U, // OR8rm + 0U, // OR8rr + 0U, // OR8rr_REV + 0U, // ORPDrm + 0U, // ORPDrr + 0U, // ORPSrm + 0U, // ORPSrr + 0U, // OUT16ir + 0U, // OUT16rr + 0U, // OUT32ir + 0U, // OUT32rr + 0U, // OUT8ir + 0U, // OUT8rr + 0U, // OUTSB + 0U, // OUTSL + 0U, // OUTSW + 0U, // PABSBrm + 0U, // PABSBrr + 0U, // PABSDrm + 0U, // PABSDrr + 0U, // PABSWrm + 0U, // PABSWrr + 0U, // PACKSSDWrm + 0U, // PACKSSDWrr + 0U, // PACKSSWBrm + 0U, // PACKSSWBrr + 0U, // PACKUSDWrm + 0U, // PACKUSDWrr + 0U, // PACKUSWBrm + 0U, // PACKUSWBrr + 0U, // PADDBrm + 0U, // PADDBrr + 0U, // PADDDrm + 0U, // PADDDrr + 0U, // PADDQrm + 0U, // PADDQrr + 0U, // PADDSBrm + 0U, // PADDSBrr + 0U, // PADDSWrm + 0U, // PADDSWrr + 0U, // PADDUSBrm + 0U, // PADDUSBrr + 0U, // PADDUSWrm + 0U, // PADDUSWrr + 0U, // PADDWrm + 0U, // PADDWrr + 0U, // PALIGNRrmi + 0U, // PALIGNRrri + 0U, // PANDNrm + 0U, // PANDNrr + 0U, // PANDrm + 0U, // PANDrr + 0U, // PAUSE + 0U, // PAVGBrm + 0U, // PAVGBrr + 0U, // PAVGUSBrm + 0U, // PAVGUSBrr + 0U, // PAVGWrm + 0U, // PAVGWrr + 0U, // PBLENDVBrm0 + 0U, // PBLENDVBrr0 + 0U, // PBLENDWrmi + 0U, // PBLENDWrri + 0U, // PCLMULQDQrm + 0U, // PCLMULQDQrr + 0U, // PCMPEQBrm + 0U, // PCMPEQBrr + 0U, // PCMPEQDrm + 0U, // PCMPEQDrr + 0U, // PCMPEQQrm + 0U, // PCMPEQQrr + 0U, // PCMPEQWrm + 0U, // PCMPEQWrr + 0U, // PCMPESTRIrm + 0U, // PCMPESTRIrr + 0U, // PCMPESTRMrm + 0U, // PCMPESTRMrr + 0U, // PCMPGTBrm + 0U, // PCMPGTBrr + 0U, // PCMPGTDrm + 0U, // PCMPGTDrr + 0U, // PCMPGTQrm + 0U, // PCMPGTQrr + 0U, // PCMPGTWrm + 0U, // PCMPGTWrr + 0U, // PCMPISTRIrm + 0U, // PCMPISTRIrr + 0U, // PCMPISTRMrm + 0U, // PCMPISTRMrr + 0U, // PCONFIG + 0U, // PDEP32rm + 0U, // PDEP32rr + 0U, // PDEP64rm + 0U, // PDEP64rr + 0U, // PEXT32rm + 0U, // PEXT32rr + 0U, // PEXT64rm + 0U, // PEXT64rr + 0U, // PEXTRBmr + 0U, // PEXTRBrr + 0U, // PEXTRDmr + 0U, // PEXTRDrr + 0U, // PEXTRQmr + 0U, // PEXTRQrr + 0U, // PEXTRWmr + 0U, // PEXTRWrr + 0U, // PEXTRWrr_REV + 0U, // PF2IDrm + 0U, // PF2IDrr + 0U, // PF2IWrm + 0U, // PF2IWrr + 0U, // PFACCrm + 0U, // PFACCrr + 0U, // PFADDrm + 0U, // PFADDrr + 0U, // PFCMPEQrm + 0U, // PFCMPEQrr + 0U, // PFCMPGErm + 0U, // PFCMPGErr + 0U, // PFCMPGTrm + 0U, // PFCMPGTrr + 0U, // PFMAXrm + 0U, // PFMAXrr + 0U, // PFMINrm + 0U, // PFMINrr + 0U, // PFMULrm + 0U, // PFMULrr + 0U, // PFNACCrm + 0U, // PFNACCrr + 0U, // PFPNACCrm + 0U, // PFPNACCrr + 0U, // PFRCPIT1rm + 0U, // PFRCPIT1rr + 0U, // PFRCPIT2rm + 0U, // PFRCPIT2rr + 0U, // PFRCPrm + 0U, // PFRCPrr + 0U, // PFRSQIT1rm + 0U, // PFRSQIT1rr + 0U, // PFRSQRTrm + 0U, // PFRSQRTrr + 0U, // PFSUBRrm + 0U, // PFSUBRrr + 0U, // PFSUBrm + 0U, // PFSUBrr + 0U, // PHADDDrm + 0U, // PHADDDrr + 0U, // PHADDSWrm + 0U, // PHADDSWrr + 0U, // PHADDWrm + 0U, // PHADDWrr + 0U, // PHMINPOSUWrm + 0U, // PHMINPOSUWrr + 0U, // PHSUBDrm + 0U, // PHSUBDrr + 0U, // PHSUBSWrm + 0U, // PHSUBSWrr + 0U, // PHSUBWrm + 0U, // PHSUBWrr + 0U, // PI2FDrm + 0U, // PI2FDrr + 0U, // PI2FWrm + 0U, // PI2FWrr + 0U, // PINSRBrm + 0U, // PINSRBrr + 0U, // PINSRDrm + 0U, // PINSRDrr + 0U, // PINSRQrm + 0U, // PINSRQrr + 0U, // PINSRWrm + 0U, // PINSRWrr + 0U, // PMADDUBSWrm + 0U, // PMADDUBSWrr + 0U, // PMADDWDrm + 0U, // PMADDWDrr + 0U, // PMAXSBrm + 0U, // PMAXSBrr + 0U, // PMAXSDrm + 0U, // PMAXSDrr + 0U, // PMAXSWrm + 0U, // PMAXSWrr + 0U, // PMAXUBrm + 0U, // PMAXUBrr + 0U, // PMAXUDrm + 0U, // PMAXUDrr + 0U, // PMAXUWrm + 0U, // PMAXUWrr + 0U, // PMINSBrm + 0U, // PMINSBrr + 0U, // PMINSDrm + 0U, // PMINSDrr + 0U, // PMINSWrm + 0U, // PMINSWrr + 0U, // PMINUBrm + 0U, // PMINUBrr + 0U, // PMINUDrm + 0U, // PMINUDrr + 0U, // PMINUWrm + 0U, // PMINUWrr + 0U, // PMOVMSKBrr + 0U, // PMOVSXBDrm + 0U, // PMOVSXBDrr + 0U, // PMOVSXBQrm + 0U, // PMOVSXBQrr + 0U, // PMOVSXBWrm + 0U, // PMOVSXBWrr + 0U, // PMOVSXDQrm + 0U, // PMOVSXDQrr + 0U, // PMOVSXWDrm + 0U, // PMOVSXWDrr + 0U, // PMOVSXWQrm + 0U, // PMOVSXWQrr + 0U, // PMOVZXBDrm + 0U, // PMOVZXBDrr + 0U, // PMOVZXBQrm + 0U, // PMOVZXBQrr + 0U, // PMOVZXBWrm + 0U, // PMOVZXBWrr + 0U, // PMOVZXDQrm + 0U, // PMOVZXDQrr + 0U, // PMOVZXWDrm + 0U, // PMOVZXWDrr + 0U, // PMOVZXWQrm + 0U, // PMOVZXWQrr + 0U, // PMULDQrm + 0U, // PMULDQrr + 0U, // PMULHRSWrm + 0U, // PMULHRSWrr + 0U, // PMULHRWrm + 0U, // PMULHRWrr + 0U, // PMULHUWrm + 0U, // PMULHUWrr + 0U, // PMULHWrm + 0U, // PMULHWrr + 0U, // PMULLDrm + 0U, // PMULLDrr + 0U, // PMULLWrm + 0U, // PMULLWrr + 0U, // PMULUDQrm + 0U, // PMULUDQrr + 0U, // POP16r + 0U, // POP16rmm + 0U, // POP16rmr + 0U, // POP32r + 0U, // POP32rmm + 0U, // POP32rmr + 0U, // POP64r + 0U, // POP64rmm + 0U, // POP64rmr + 0U, // POPA16 + 0U, // POPA32 + 0U, // POPCNT16rm + 0U, // POPCNT16rr + 0U, // POPCNT32rm + 0U, // POPCNT32rr + 0U, // POPCNT64rm + 0U, // POPCNT64rr + 0U, // POPDS16 + 0U, // POPDS32 + 0U, // POPES16 + 0U, // POPES32 + 0U, // POPF16 + 0U, // POPF32 + 0U, // POPF64 + 0U, // POPFS16 + 0U, // POPFS32 + 0U, // POPFS64 + 0U, // POPGS16 + 0U, // POPGS32 + 0U, // POPGS64 + 0U, // POPSS16 + 0U, // POPSS32 + 0U, // PORrm + 0U, // PORrr + 0U, // PREFETCH + 0U, // PREFETCHNTA + 0U, // PREFETCHT0 + 0U, // PREFETCHT1 + 0U, // PREFETCHT2 + 0U, // PREFETCHW + 0U, // PREFETCHWT1 + 0U, // PSADBWrm + 0U, // PSADBWrr + 0U, // PSHUFBrm + 0U, // PSHUFBrr + 0U, // PSHUFDmi + 0U, // PSHUFDri + 0U, // PSHUFHWmi + 0U, // PSHUFHWri + 0U, // PSHUFLWmi + 0U, // PSHUFLWri + 0U, // PSIGNBrm + 0U, // PSIGNBrr + 0U, // PSIGNDrm + 0U, // PSIGNDrr + 0U, // PSIGNWrm + 0U, // PSIGNWrr + 0U, // PSLLDQri + 0U, // PSLLDri + 0U, // PSLLDrm + 0U, // PSLLDrr + 0U, // PSLLQri + 0U, // PSLLQrm + 0U, // PSLLQrr + 0U, // PSLLWri + 0U, // PSLLWrm + 0U, // PSLLWrr + 0U, // PSRADri + 0U, // PSRADrm + 0U, // PSRADrr + 0U, // PSRAWri + 0U, // PSRAWrm + 0U, // PSRAWrr + 0U, // PSRLDQri + 0U, // PSRLDri + 0U, // PSRLDrm + 0U, // PSRLDrr + 0U, // PSRLQri + 0U, // PSRLQrm + 0U, // PSRLQrr + 0U, // PSRLWri + 0U, // PSRLWrm + 0U, // PSRLWrr + 0U, // PSUBBrm + 0U, // PSUBBrr + 0U, // PSUBDrm + 0U, // PSUBDrr + 0U, // PSUBQrm + 0U, // PSUBQrr + 0U, // PSUBSBrm + 0U, // PSUBSBrr + 0U, // PSUBSWrm + 0U, // PSUBSWrr + 0U, // PSUBUSBrm + 0U, // PSUBUSBrr + 0U, // PSUBUSWrm + 0U, // PSUBUSWrr + 0U, // PSUBWrm + 0U, // PSUBWrr + 0U, // PSWAPDrm + 0U, // PSWAPDrr + 0U, // PTESTrm + 0U, // PTESTrr + 0U, // PTWRITE64m + 0U, // PTWRITE64r + 0U, // PTWRITEm + 0U, // PTWRITEr + 0U, // PUNPCKHBWrm + 0U, // PUNPCKHBWrr + 0U, // PUNPCKHDQrm + 0U, // PUNPCKHDQrr + 0U, // PUNPCKHQDQrm + 0U, // PUNPCKHQDQrr + 0U, // PUNPCKHWDrm + 0U, // PUNPCKHWDrr + 0U, // PUNPCKLBWrm + 0U, // PUNPCKLBWrr + 0U, // PUNPCKLDQrm + 0U, // PUNPCKLDQrr + 0U, // PUNPCKLQDQrm + 0U, // PUNPCKLQDQrr + 0U, // PUNPCKLWDrm + 0U, // PUNPCKLWDrr + 0U, // PUSH16i8 + 0U, // PUSH16r + 0U, // PUSH16rmm + 0U, // PUSH16rmr + 0U, // PUSH32i8 + 0U, // PUSH32r + 0U, // PUSH32rmm + 0U, // PUSH32rmr + 0U, // PUSH64i32 + 0U, // PUSH64i8 + 0U, // PUSH64r + 0U, // PUSH64rmm + 0U, // PUSH64rmr + 0U, // PUSHA16 + 0U, // PUSHA32 + 0U, // PUSHCS16 + 0U, // PUSHCS32 + 0U, // PUSHDS16 + 0U, // PUSHDS32 + 0U, // PUSHES16 + 0U, // PUSHES32 + 0U, // PUSHF16 + 0U, // PUSHF32 + 0U, // PUSHF64 + 0U, // PUSHFS16 + 0U, // PUSHFS32 + 0U, // PUSHFS64 + 0U, // PUSHGS16 + 0U, // PUSHGS32 + 0U, // PUSHGS64 + 0U, // PUSHSS16 + 0U, // PUSHSS32 + 0U, // PUSHi16 + 0U, // PUSHi32 + 0U, // PXORrm + 0U, // PXORrr + 0U, // RCL16m1 + 0U, // RCL16mCL + 0U, // RCL16mi + 0U, // RCL16r1 + 0U, // RCL16rCL + 0U, // RCL16ri + 0U, // RCL32m1 + 0U, // RCL32mCL + 0U, // RCL32mi + 0U, // RCL32r1 + 0U, // RCL32rCL + 0U, // RCL32ri + 0U, // RCL64m1 + 0U, // RCL64mCL + 0U, // RCL64mi + 0U, // RCL64r1 + 0U, // RCL64rCL + 0U, // RCL64ri + 0U, // RCL8m1 + 0U, // RCL8mCL + 0U, // RCL8mi + 0U, // RCL8r1 + 0U, // RCL8rCL + 0U, // RCL8ri + 0U, // RCPPSm + 0U, // RCPPSr + 0U, // RCPSSm + 0U, // RCPSSm_Int + 0U, // RCPSSr + 0U, // RCPSSr_Int + 0U, // RCR16m1 + 0U, // RCR16mCL + 0U, // RCR16mi + 0U, // RCR16r1 + 0U, // RCR16rCL + 0U, // RCR16ri + 0U, // RCR32m1 + 0U, // RCR32mCL + 0U, // RCR32mi + 0U, // RCR32r1 + 0U, // RCR32rCL + 0U, // RCR32ri + 0U, // RCR64m1 + 0U, // RCR64mCL + 0U, // RCR64mi + 0U, // RCR64r1 + 0U, // RCR64rCL + 0U, // RCR64ri + 0U, // RCR8m1 + 0U, // RCR8mCL + 0U, // RCR8mi + 0U, // RCR8r1 + 0U, // RCR8rCL + 0U, // RCR8ri + 0U, // RDFSBASE + 0U, // RDFSBASE64 + 0U, // RDGSBASE + 0U, // RDGSBASE64 + 0U, // RDMSR + 0U, // RDPID32 + 0U, // RDPID64 + 0U, // RDPKRUr + 0U, // RDPMC + 0U, // RDRAND16r + 0U, // RDRAND32r + 0U, // RDRAND64r + 0U, // RDSEED16r + 0U, // RDSEED32r + 0U, // RDSEED64r + 0U, // RDSSPD + 0U, // RDSSPQ + 0U, // RDTSC + 0U, // RDTSCP + 0U, // REPNE_PREFIX + 0U, // REP_PREFIX + 0U, // RETIL + 0U, // RETIQ + 0U, // RETIW + 0U, // RETL + 0U, // RETQ + 0U, // RETW + 0U, // REX64_PREFIX + 0U, // ROL16m1 + 0U, // ROL16mCL + 0U, // ROL16mi + 0U, // ROL16r1 + 0U, // ROL16rCL + 0U, // ROL16ri + 0U, // ROL32m1 + 0U, // ROL32mCL + 0U, // ROL32mi + 0U, // ROL32r1 + 0U, // ROL32rCL + 0U, // ROL32ri + 0U, // ROL64m1 + 0U, // ROL64mCL + 0U, // ROL64mi + 0U, // ROL64r1 + 0U, // ROL64rCL + 0U, // ROL64ri + 0U, // ROL8m1 + 0U, // ROL8mCL + 0U, // ROL8mi + 0U, // ROL8r1 + 0U, // ROL8rCL + 0U, // ROL8ri + 0U, // ROR16m1 + 0U, // ROR16mCL + 0U, // ROR16mi + 0U, // ROR16r1 + 0U, // ROR16rCL + 0U, // ROR16ri + 0U, // ROR32m1 + 0U, // ROR32mCL + 0U, // ROR32mi + 0U, // ROR32r1 + 0U, // ROR32rCL + 0U, // ROR32ri + 0U, // ROR64m1 + 0U, // ROR64mCL + 0U, // ROR64mi + 0U, // ROR64r1 + 0U, // ROR64rCL + 0U, // ROR64ri + 0U, // ROR8m1 + 0U, // ROR8mCL + 0U, // ROR8mi + 0U, // ROR8r1 + 0U, // ROR8rCL + 0U, // ROR8ri + 0U, // RORX32mi + 0U, // RORX32ri + 0U, // RORX64mi + 0U, // RORX64ri + 0U, // ROUNDPDm + 0U, // ROUNDPDr + 0U, // ROUNDPSm + 0U, // ROUNDPSr + 0U, // ROUNDSDm + 0U, // ROUNDSDm_Int + 0U, // ROUNDSDr + 0U, // ROUNDSDr_Int + 0U, // ROUNDSSm + 0U, // ROUNDSSm_Int + 0U, // ROUNDSSr + 0U, // ROUNDSSr_Int + 0U, // RSM + 0U, // RSQRTPSm + 0U, // RSQRTPSr + 0U, // RSQRTSSm + 0U, // RSQRTSSm_Int + 0U, // RSQRTSSr + 0U, // RSQRTSSr_Int + 0U, // RSTORSSP + 0U, // SAHF + 0U, // SAL16m1 + 0U, // SAL16mCL + 0U, // SAL16mi + 0U, // SAL16r1 + 0U, // SAL16rCL + 0U, // SAL16ri + 0U, // SAL32m1 + 0U, // SAL32mCL + 0U, // SAL32mi + 0U, // SAL32r1 + 0U, // SAL32rCL + 0U, // SAL32ri + 0U, // SAL64m1 + 0U, // SAL64mCL + 0U, // SAL64mi + 0U, // SAL64r1 + 0U, // SAL64rCL + 0U, // SAL64ri + 0U, // SAL8m1 + 0U, // SAL8mCL + 0U, // SAL8mi + 0U, // SAL8r1 + 0U, // SAL8rCL + 0U, // SAL8ri + 0U, // SALC + 0U, // SAR16m1 + 0U, // SAR16mCL + 0U, // SAR16mi + 0U, // SAR16r1 + 0U, // SAR16rCL + 0U, // SAR16ri + 0U, // SAR32m1 + 0U, // SAR32mCL + 0U, // SAR32mi + 0U, // SAR32r1 + 0U, // SAR32rCL + 0U, // SAR32ri + 0U, // SAR64m1 + 0U, // SAR64mCL + 0U, // SAR64mi + 0U, // SAR64r1 + 0U, // SAR64rCL + 0U, // SAR64ri + 0U, // SAR8m1 + 0U, // SAR8mCL + 0U, // SAR8mi + 0U, // SAR8r1 + 0U, // SAR8rCL + 0U, // SAR8ri + 0U, // SARX32rm + 0U, // SARX32rr + 0U, // SARX64rm + 0U, // SARX64rr + 0U, // SAVEPREVSSP + 0U, // SBB16i16 + 0U, // SBB16mi + 0U, // SBB16mi8 + 0U, // SBB16mr + 0U, // SBB16ri + 0U, // SBB16ri8 + 0U, // SBB16rm + 0U, // SBB16rr + 0U, // SBB16rr_REV + 0U, // SBB32i32 + 0U, // SBB32mi + 0U, // SBB32mi8 + 0U, // SBB32mr + 0U, // SBB32ri + 0U, // SBB32ri8 + 0U, // SBB32rm + 0U, // SBB32rr + 0U, // SBB32rr_REV + 0U, // SBB64i32 + 0U, // SBB64mi32 + 0U, // SBB64mi8 + 0U, // SBB64mr + 0U, // SBB64ri32 + 0U, // SBB64ri8 + 0U, // SBB64rm + 0U, // SBB64rr + 0U, // SBB64rr_REV + 0U, // SBB8i8 + 0U, // SBB8mi + 0U, // SBB8mi8 + 0U, // SBB8mr + 0U, // SBB8ri + 0U, // SBB8ri8 + 0U, // SBB8rm + 0U, // SBB8rr + 0U, // SBB8rr_REV + 0U, // SCASB + 0U, // SCASL + 0U, // SCASQ + 0U, // SCASW + 0U, // SETAEm + 0U, // SETAEr + 0U, // SETAm + 0U, // SETAr + 0U, // SETBEm + 0U, // SETBEr + 0U, // SETBm + 0U, // SETBr + 0U, // SETEm + 0U, // SETEr + 0U, // SETGEm + 0U, // SETGEr + 0U, // SETGm + 0U, // SETGr + 0U, // SETLEm + 0U, // SETLEr + 0U, // SETLm + 0U, // SETLr + 0U, // SETNEm + 0U, // SETNEr + 0U, // SETNOm + 0U, // SETNOr + 0U, // SETNPm + 0U, // SETNPr + 0U, // SETNSm + 0U, // SETNSr + 0U, // SETOm + 0U, // SETOr + 0U, // SETPm + 0U, // SETPr + 0U, // SETSSBSY + 0U, // SETSm + 0U, // SETSr + 0U, // SFENCE + 0U, // SGDT16m + 0U, // SGDT32m + 0U, // SGDT64m + 0U, // SHA1MSG1rm + 0U, // SHA1MSG1rr + 0U, // SHA1MSG2rm + 0U, // SHA1MSG2rr + 0U, // SHA1NEXTErm + 0U, // SHA1NEXTErr + 0U, // SHA1RNDS4rmi + 0U, // SHA1RNDS4rri + 0U, // SHA256MSG1rm + 0U, // SHA256MSG1rr + 0U, // SHA256MSG2rm + 0U, // SHA256MSG2rr + 0U, // SHA256RNDS2rm + 0U, // SHA256RNDS2rr + 0U, // SHL16m1 + 0U, // SHL16mCL + 0U, // SHL16mi + 0U, // SHL16r1 + 0U, // SHL16rCL + 0U, // SHL16ri + 0U, // SHL32m1 + 0U, // SHL32mCL + 0U, // SHL32mi + 0U, // SHL32r1 + 0U, // SHL32rCL + 0U, // SHL32ri + 0U, // SHL64m1 + 0U, // SHL64mCL + 0U, // SHL64mi + 0U, // SHL64r1 + 0U, // SHL64rCL + 0U, // SHL64ri + 0U, // SHL8m1 + 0U, // SHL8mCL + 0U, // SHL8mi + 0U, // SHL8r1 + 0U, // SHL8rCL + 0U, // SHL8ri + 0U, // SHLD16mrCL + 0U, // SHLD16mri8 + 0U, // SHLD16rrCL + 0U, // SHLD16rri8 + 0U, // SHLD32mrCL + 0U, // SHLD32mri8 + 0U, // SHLD32rrCL + 0U, // SHLD32rri8 + 0U, // SHLD64mrCL + 0U, // SHLD64mri8 + 0U, // SHLD64rrCL + 0U, // SHLD64rri8 + 0U, // SHLX32rm + 0U, // SHLX32rr + 0U, // SHLX64rm + 0U, // SHLX64rr + 0U, // SHR16m1 + 0U, // SHR16mCL + 0U, // SHR16mi + 0U, // SHR16r1 + 0U, // SHR16rCL + 0U, // SHR16ri + 0U, // SHR32m1 + 0U, // SHR32mCL + 0U, // SHR32mi + 0U, // SHR32r1 + 0U, // SHR32rCL + 0U, // SHR32ri + 0U, // SHR64m1 + 0U, // SHR64mCL + 0U, // SHR64mi + 0U, // SHR64r1 + 0U, // SHR64rCL + 0U, // SHR64ri + 0U, // SHR8m1 + 0U, // SHR8mCL + 0U, // SHR8mi + 0U, // SHR8r1 + 0U, // SHR8rCL + 0U, // SHR8ri + 0U, // SHRD16mrCL + 0U, // SHRD16mri8 + 0U, // SHRD16rrCL + 0U, // SHRD16rri8 + 0U, // SHRD32mrCL + 0U, // SHRD32mri8 + 0U, // SHRD32rrCL + 0U, // SHRD32rri8 + 0U, // SHRD64mrCL + 0U, // SHRD64mri8 + 0U, // SHRD64rrCL + 0U, // SHRD64rri8 + 0U, // SHRX32rm + 0U, // SHRX32rr + 0U, // SHRX64rm + 0U, // SHRX64rr + 0U, // SHUFPDrmi + 0U, // SHUFPDrri + 0U, // SHUFPSrmi + 0U, // SHUFPSrri + 0U, // SIDT16m + 0U, // SIDT32m + 0U, // SIDT64m + 0U, // SIN_F + 0U, // SIN_Fp32 + 0U, // SIN_Fp64 + 0U, // SIN_Fp80 + 0U, // SKINIT + 0U, // SLDT16m + 0U, // SLDT16r + 0U, // SLDT32r + 0U, // SLDT64r + 0U, // SLWPCB + 0U, // SLWPCB64 + 0U, // SMSW16m + 0U, // SMSW16r + 0U, // SMSW32r + 0U, // SMSW64r + 0U, // SQRTPDm + 0U, // SQRTPDr + 0U, // SQRTPSm + 0U, // SQRTPSr + 0U, // SQRTSDm + 0U, // SQRTSDm_Int + 0U, // SQRTSDr + 0U, // SQRTSDr_Int + 0U, // SQRTSSm + 0U, // SQRTSSm_Int + 0U, // SQRTSSr + 0U, // SQRTSSr_Int + 0U, // SQRT_F + 0U, // SQRT_Fp32 + 0U, // SQRT_Fp64 + 0U, // SQRT_Fp80 + 0U, // STAC + 0U, // STC + 0U, // STD + 0U, // STGI + 0U, // STI + 0U, // STMXCSR + 0U, // STOSB + 0U, // STOSL + 0U, // STOSQ + 0U, // STOSW + 0U, // STR16r + 0U, // STR32r + 0U, // STR64r + 0U, // STRm + 0U, // ST_F32m + 0U, // ST_F64m + 0U, // ST_FP32m + 0U, // ST_FP64m + 0U, // ST_FP80m + 0U, // ST_FPrr + 0U, // ST_Fp32m + 0U, // ST_Fp64m + 0U, // ST_Fp64m32 + 0U, // ST_Fp80m32 + 0U, // ST_Fp80m64 + 0U, // ST_FpP32m + 0U, // ST_FpP64m + 0U, // ST_FpP64m32 + 0U, // ST_FpP80m + 0U, // ST_FpP80m32 + 0U, // ST_FpP80m64 + 0U, // ST_Frr + 0U, // SUB16i16 + 0U, // SUB16mi + 0U, // SUB16mi8 + 0U, // SUB16mr + 0U, // SUB16ri + 0U, // SUB16ri8 + 0U, // SUB16rm + 0U, // SUB16rr + 0U, // SUB16rr_REV + 0U, // SUB32i32 + 0U, // SUB32mi + 0U, // SUB32mi8 + 0U, // SUB32mr + 0U, // SUB32ri + 0U, // SUB32ri8 + 0U, // SUB32rm + 0U, // SUB32rr + 0U, // SUB32rr_REV + 0U, // SUB64i32 + 0U, // SUB64mi32 + 0U, // SUB64mi8 + 0U, // SUB64mr + 0U, // SUB64ri32 + 0U, // SUB64ri8 + 0U, // SUB64rm + 0U, // SUB64rr + 0U, // SUB64rr_REV + 0U, // SUB8i8 + 0U, // SUB8mi + 0U, // SUB8mi8 + 0U, // SUB8mr + 0U, // SUB8ri + 0U, // SUB8ri8 + 0U, // SUB8rm + 0U, // SUB8rr + 0U, // SUB8rr_REV + 0U, // SUBPDrm + 0U, // SUBPDrr + 0U, // SUBPSrm + 0U, // SUBPSrr + 0U, // SUBR_F32m + 0U, // SUBR_F64m + 0U, // SUBR_FI16m + 0U, // SUBR_FI32m + 0U, // SUBR_FPrST0 + 0U, // SUBR_FST0r + 0U, // SUBR_Fp32m + 0U, // SUBR_Fp64m + 0U, // SUBR_Fp64m32 + 0U, // SUBR_Fp80m32 + 0U, // SUBR_Fp80m64 + 0U, // SUBR_FpI16m32 + 0U, // SUBR_FpI16m64 + 0U, // SUBR_FpI16m80 + 0U, // SUBR_FpI32m32 + 0U, // SUBR_FpI32m64 + 0U, // SUBR_FpI32m80 + 0U, // SUBR_FrST0 + 0U, // SUBSDrm + 0U, // SUBSDrm_Int + 0U, // SUBSDrr + 0U, // SUBSDrr_Int + 0U, // SUBSSrm + 0U, // SUBSSrm_Int + 0U, // SUBSSrr + 0U, // SUBSSrr_Int + 0U, // SUB_F32m + 0U, // SUB_F64m + 0U, // SUB_FI16m + 0U, // SUB_FI32m + 0U, // SUB_FPrST0 + 0U, // SUB_FST0r + 0U, // SUB_Fp32 + 0U, // SUB_Fp32m + 0U, // SUB_Fp64 + 0U, // SUB_Fp64m + 0U, // SUB_Fp64m32 + 0U, // SUB_Fp80 + 0U, // SUB_Fp80m32 + 0U, // SUB_Fp80m64 + 0U, // SUB_FpI16m32 + 0U, // SUB_FpI16m64 + 0U, // SUB_FpI16m80 + 0U, // SUB_FpI32m32 + 0U, // SUB_FpI32m64 + 0U, // SUB_FpI32m80 + 0U, // SUB_FrST0 + 0U, // SWAPGS + 0U, // SYSCALL + 0U, // SYSENTER + 0U, // SYSEXIT + 0U, // SYSEXIT64 + 0U, // SYSRET + 0U, // SYSRET64 + 0U, // T1MSKC32rm + 0U, // T1MSKC32rr + 0U, // T1MSKC64rm + 0U, // T1MSKC64rr + 0U, // TEST16i16 + 0U, // TEST16mi + 0U, // TEST16mi_alt + 0U, // TEST16mr + 0U, // TEST16ri + 0U, // TEST16ri_alt + 0U, // TEST16rr + 0U, // TEST32i32 + 0U, // TEST32mi + 0U, // TEST32mi_alt + 0U, // TEST32mr + 0U, // TEST32ri + 0U, // TEST32ri_alt + 0U, // TEST32rr + 0U, // TEST64i32 + 0U, // TEST64mi32 + 0U, // TEST64mi32_alt + 0U, // TEST64mr + 0U, // TEST64ri32 + 0U, // TEST64ri32_alt + 0U, // TEST64rr + 0U, // TEST8i8 + 0U, // TEST8mi + 0U, // TEST8mi_alt + 0U, // TEST8mr + 0U, // TEST8ri + 0U, // TEST8ri_alt + 0U, // TEST8rr + 0U, // TPAUSE + 0U, // TST_F + 0U, // TST_Fp32 + 0U, // TST_Fp64 + 0U, // TST_Fp80 + 0U, // TZCNT16rm + 0U, // TZCNT16rr + 0U, // TZCNT32rm + 0U, // TZCNT32rr + 0U, // TZCNT64rm + 0U, // TZCNT64rr + 0U, // TZMSK32rm + 0U, // TZMSK32rr + 0U, // TZMSK64rm + 0U, // TZMSK64rr + 0U, // UCOMISDrm + 0U, // UCOMISDrm_Int + 0U, // UCOMISDrr + 0U, // UCOMISDrr_Int + 0U, // UCOMISSrm + 0U, // UCOMISSrm_Int + 0U, // UCOMISSrr + 0U, // UCOMISSrr_Int + 0U, // UCOM_FIPr + 0U, // UCOM_FIr + 0U, // UCOM_FPPr + 0U, // UCOM_FPr + 0U, // UCOM_FpIr32 + 0U, // UCOM_FpIr64 + 0U, // UCOM_FpIr80 + 0U, // UCOM_Fpr32 + 0U, // UCOM_Fpr64 + 0U, // UCOM_Fpr80 + 0U, // UCOM_Fr + 0U, // UD0 + 0U, // UD1 + 0U, // UD2 + 0U, // UMONITOR16 + 0U, // UMONITOR32 + 0U, // UMONITOR64 + 0U, // UMWAIT + 0U, // UNPCKHPDrm + 0U, // UNPCKHPDrr + 0U, // UNPCKHPSrm + 0U, // UNPCKHPSrr + 0U, // UNPCKLPDrm + 0U, // UNPCKLPDrr + 0U, // UNPCKLPSrm + 0U, // UNPCKLPSrr + 0U, // V4FMADDPSrm + 0U, // V4FMADDPSrmk + 0U, // V4FMADDPSrmkz + 0U, // V4FMADDSSrm + 0U, // V4FMADDSSrmk + 0U, // V4FMADDSSrmkz + 0U, // V4FNMADDPSrm + 0U, // V4FNMADDPSrmk + 0U, // V4FNMADDPSrmkz + 0U, // V4FNMADDSSrm + 0U, // V4FNMADDSSrmk + 0U, // V4FNMADDSSrmkz + 0U, // VADDPDYrm + 0U, // VADDPDYrr + 0U, // VADDPDZ128rm + 0U, // VADDPDZ128rmb + 0U, // VADDPDZ128rmbk + 0U, // VADDPDZ128rmbkz + 0U, // VADDPDZ128rmk + 0U, // VADDPDZ128rmkz + 0U, // VADDPDZ128rr + 0U, // VADDPDZ128rrk + 0U, // VADDPDZ128rrkz + 0U, // VADDPDZ256rm + 0U, // VADDPDZ256rmb + 0U, // VADDPDZ256rmbk + 0U, // VADDPDZ256rmbkz + 0U, // VADDPDZ256rmk + 0U, // VADDPDZ256rmkz + 0U, // VADDPDZ256rr + 0U, // VADDPDZ256rrk + 0U, // VADDPDZ256rrkz + 0U, // VADDPDZrm + 0U, // VADDPDZrmb + 0U, // VADDPDZrmbk + 0U, // VADDPDZrmbkz + 0U, // VADDPDZrmk + 0U, // VADDPDZrmkz + 0U, // VADDPDZrr + 0U, // VADDPDZrrb + 0U, // VADDPDZrrbk + 0U, // VADDPDZrrbkz + 0U, // VADDPDZrrk + 0U, // VADDPDZrrkz + 0U, // VADDPDrm + 0U, // VADDPDrr + 0U, // VADDPSYrm + 0U, // VADDPSYrr + 0U, // VADDPSZ128rm + 0U, // VADDPSZ128rmb + 0U, // VADDPSZ128rmbk + 0U, // VADDPSZ128rmbkz + 0U, // VADDPSZ128rmk + 0U, // VADDPSZ128rmkz + 0U, // VADDPSZ128rr + 0U, // VADDPSZ128rrk + 0U, // VADDPSZ128rrkz + 0U, // VADDPSZ256rm + 0U, // VADDPSZ256rmb + 0U, // VADDPSZ256rmbk + 0U, // VADDPSZ256rmbkz + 0U, // VADDPSZ256rmk + 0U, // VADDPSZ256rmkz + 0U, // VADDPSZ256rr + 0U, // VADDPSZ256rrk + 0U, // VADDPSZ256rrkz + 0U, // VADDPSZrm + 0U, // VADDPSZrmb + 0U, // VADDPSZrmbk + 0U, // VADDPSZrmbkz + 0U, // VADDPSZrmk + 0U, // VADDPSZrmkz + 0U, // VADDPSZrr + 0U, // VADDPSZrrb + 0U, // VADDPSZrrbk + 0U, // VADDPSZrrbkz + 0U, // VADDPSZrrk + 0U, // VADDPSZrrkz + 0U, // VADDPSrm + 0U, // VADDPSrr + 0U, // VADDSDZrm + 0U, // VADDSDZrm_Int + 0U, // VADDSDZrm_Intk + 0U, // VADDSDZrm_Intkz + 0U, // VADDSDZrr + 0U, // VADDSDZrr_Int + 0U, // VADDSDZrr_Intk + 0U, // VADDSDZrr_Intkz + 0U, // VADDSDZrrb_Int + 0U, // VADDSDZrrb_Intk + 0U, // VADDSDZrrb_Intkz + 0U, // VADDSDrm + 0U, // VADDSDrm_Int + 0U, // VADDSDrr + 0U, // VADDSDrr_Int + 0U, // VADDSSZrm + 0U, // VADDSSZrm_Int + 0U, // VADDSSZrm_Intk + 0U, // VADDSSZrm_Intkz + 0U, // VADDSSZrr + 0U, // VADDSSZrr_Int + 0U, // VADDSSZrr_Intk + 0U, // VADDSSZrr_Intkz + 0U, // VADDSSZrrb_Int + 0U, // VADDSSZrrb_Intk + 0U, // VADDSSZrrb_Intkz + 0U, // VADDSSrm + 0U, // VADDSSrm_Int + 0U, // VADDSSrr + 0U, // VADDSSrr_Int + 0U, // VADDSUBPDYrm + 0U, // VADDSUBPDYrr + 0U, // VADDSUBPDrm + 0U, // VADDSUBPDrr + 0U, // VADDSUBPSYrm + 0U, // VADDSUBPSYrr + 0U, // VADDSUBPSrm + 0U, // VADDSUBPSrr + 0U, // VAESDECLASTYrm + 0U, // VAESDECLASTYrr + 0U, // VAESDECLASTZ128rm + 0U, // VAESDECLASTZ128rr + 0U, // VAESDECLASTZ256rm + 0U, // VAESDECLASTZ256rr + 0U, // VAESDECLASTZrm + 0U, // VAESDECLASTZrr + 0U, // VAESDECLASTrm + 0U, // VAESDECLASTrr + 0U, // VAESDECYrm + 0U, // VAESDECYrr + 0U, // VAESDECZ128rm + 0U, // VAESDECZ128rr + 0U, // VAESDECZ256rm + 0U, // VAESDECZ256rr + 0U, // VAESDECZrm + 0U, // VAESDECZrr + 0U, // VAESDECrm + 0U, // VAESDECrr + 0U, // VAESENCLASTYrm + 0U, // VAESENCLASTYrr + 0U, // VAESENCLASTZ128rm + 0U, // VAESENCLASTZ128rr + 0U, // VAESENCLASTZ256rm + 0U, // VAESENCLASTZ256rr + 0U, // VAESENCLASTZrm + 0U, // VAESENCLASTZrr + 0U, // VAESENCLASTrm + 0U, // VAESENCLASTrr + 0U, // VAESENCYrm + 0U, // VAESENCYrr + 0U, // VAESENCZ128rm + 0U, // VAESENCZ128rr + 0U, // VAESENCZ256rm + 0U, // VAESENCZ256rr + 0U, // VAESENCZrm + 0U, // VAESENCZrr + 0U, // VAESENCrm + 0U, // VAESENCrr + 0U, // VAESIMCrm + 0U, // VAESIMCrr + 0U, // VAESKEYGENASSIST128rm + 0U, // VAESKEYGENASSIST128rr + 0U, // VALIGNDZ128rmbi + 0U, // VALIGNDZ128rmbik + 3U, // VALIGNDZ128rmbikz + 0U, // VALIGNDZ128rmi + 0U, // VALIGNDZ128rmik + 0U, // VALIGNDZ128rmikz + 0U, // VALIGNDZ128rri + 0U, // VALIGNDZ128rrik + 3U, // VALIGNDZ128rrikz + 0U, // VALIGNDZ256rmbi + 0U, // VALIGNDZ256rmbik + 3U, // VALIGNDZ256rmbikz + 0U, // VALIGNDZ256rmi + 0U, // VALIGNDZ256rmik + 0U, // VALIGNDZ256rmikz + 0U, // VALIGNDZ256rri + 0U, // VALIGNDZ256rrik + 3U, // VALIGNDZ256rrikz + 0U, // VALIGNDZrmbi + 0U, // VALIGNDZrmbik + 3U, // VALIGNDZrmbikz + 0U, // VALIGNDZrmi + 0U, // VALIGNDZrmik + 0U, // VALIGNDZrmikz + 0U, // VALIGNDZrri + 0U, // VALIGNDZrrik + 3U, // VALIGNDZrrikz + 0U, // VALIGNQZ128rmbi + 0U, // VALIGNQZ128rmbik + 3U, // VALIGNQZ128rmbikz + 0U, // VALIGNQZ128rmi + 0U, // VALIGNQZ128rmik + 0U, // VALIGNQZ128rmikz + 0U, // VALIGNQZ128rri + 0U, // VALIGNQZ128rrik + 3U, // VALIGNQZ128rrikz + 0U, // VALIGNQZ256rmbi + 0U, // VALIGNQZ256rmbik + 3U, // VALIGNQZ256rmbikz + 0U, // VALIGNQZ256rmi + 0U, // VALIGNQZ256rmik + 0U, // VALIGNQZ256rmikz + 0U, // VALIGNQZ256rri + 0U, // VALIGNQZ256rrik + 3U, // VALIGNQZ256rrikz + 0U, // VALIGNQZrmbi + 0U, // VALIGNQZrmbik + 3U, // VALIGNQZrmbikz + 0U, // VALIGNQZrmi + 0U, // VALIGNQZrmik + 0U, // VALIGNQZrmikz + 0U, // VALIGNQZrri + 0U, // VALIGNQZrrik + 3U, // VALIGNQZrrikz + 0U, // VANDNPDYrm + 0U, // VANDNPDYrr + 0U, // VANDNPDZ128rm + 0U, // VANDNPDZ128rmb + 0U, // VANDNPDZ128rmbk + 0U, // VANDNPDZ128rmbkz + 0U, // VANDNPDZ128rmk + 0U, // VANDNPDZ128rmkz + 0U, // VANDNPDZ128rr + 0U, // VANDNPDZ128rrk + 0U, // VANDNPDZ128rrkz + 0U, // VANDNPDZ256rm + 0U, // VANDNPDZ256rmb + 0U, // VANDNPDZ256rmbk + 0U, // VANDNPDZ256rmbkz + 0U, // VANDNPDZ256rmk + 0U, // VANDNPDZ256rmkz + 0U, // VANDNPDZ256rr + 0U, // VANDNPDZ256rrk + 0U, // VANDNPDZ256rrkz + 0U, // VANDNPDZrm + 0U, // VANDNPDZrmb + 0U, // VANDNPDZrmbk + 0U, // VANDNPDZrmbkz + 0U, // VANDNPDZrmk + 0U, // VANDNPDZrmkz + 0U, // VANDNPDZrr + 0U, // VANDNPDZrrk + 0U, // VANDNPDZrrkz + 0U, // VANDNPDrm + 0U, // VANDNPDrr + 0U, // VANDNPSYrm + 0U, // VANDNPSYrr + 0U, // VANDNPSZ128rm + 0U, // VANDNPSZ128rmb + 0U, // VANDNPSZ128rmbk + 0U, // VANDNPSZ128rmbkz + 0U, // VANDNPSZ128rmk + 0U, // VANDNPSZ128rmkz + 0U, // VANDNPSZ128rr + 0U, // VANDNPSZ128rrk + 0U, // VANDNPSZ128rrkz + 0U, // VANDNPSZ256rm + 0U, // VANDNPSZ256rmb + 0U, // VANDNPSZ256rmbk + 0U, // VANDNPSZ256rmbkz + 0U, // VANDNPSZ256rmk + 0U, // VANDNPSZ256rmkz + 0U, // VANDNPSZ256rr + 0U, // VANDNPSZ256rrk + 0U, // VANDNPSZ256rrkz + 0U, // VANDNPSZrm + 0U, // VANDNPSZrmb + 0U, // VANDNPSZrmbk + 0U, // VANDNPSZrmbkz + 0U, // VANDNPSZrmk + 0U, // VANDNPSZrmkz + 0U, // VANDNPSZrr + 0U, // VANDNPSZrrk + 0U, // VANDNPSZrrkz + 0U, // VANDNPSrm + 0U, // VANDNPSrr + 0U, // VANDPDYrm + 0U, // VANDPDYrr + 0U, // VANDPDZ128rm + 0U, // VANDPDZ128rmb + 0U, // VANDPDZ128rmbk + 0U, // VANDPDZ128rmbkz + 0U, // VANDPDZ128rmk + 0U, // VANDPDZ128rmkz + 0U, // VANDPDZ128rr + 0U, // VANDPDZ128rrk + 0U, // VANDPDZ128rrkz + 0U, // VANDPDZ256rm + 0U, // VANDPDZ256rmb + 0U, // VANDPDZ256rmbk + 0U, // VANDPDZ256rmbkz + 0U, // VANDPDZ256rmk + 0U, // VANDPDZ256rmkz + 0U, // VANDPDZ256rr + 0U, // VANDPDZ256rrk + 0U, // VANDPDZ256rrkz + 0U, // VANDPDZrm + 0U, // VANDPDZrmb + 0U, // VANDPDZrmbk + 0U, // VANDPDZrmbkz + 0U, // VANDPDZrmk + 0U, // VANDPDZrmkz + 0U, // VANDPDZrr + 0U, // VANDPDZrrk + 0U, // VANDPDZrrkz + 0U, // VANDPDrm + 0U, // VANDPDrr + 0U, // VANDPSYrm + 0U, // VANDPSYrr + 0U, // VANDPSZ128rm + 0U, // VANDPSZ128rmb + 0U, // VANDPSZ128rmbk + 0U, // VANDPSZ128rmbkz + 0U, // VANDPSZ128rmk + 0U, // VANDPSZ128rmkz + 0U, // VANDPSZ128rr + 0U, // VANDPSZ128rrk + 0U, // VANDPSZ128rrkz + 0U, // VANDPSZ256rm + 0U, // VANDPSZ256rmb + 0U, // VANDPSZ256rmbk + 0U, // VANDPSZ256rmbkz + 0U, // VANDPSZ256rmk + 0U, // VANDPSZ256rmkz + 0U, // VANDPSZ256rr + 0U, // VANDPSZ256rrk + 0U, // VANDPSZ256rrkz + 0U, // VANDPSZrm + 0U, // VANDPSZrmb + 0U, // VANDPSZrmbk + 0U, // VANDPSZrmbkz + 0U, // VANDPSZrmk + 0U, // VANDPSZrmkz + 0U, // VANDPSZrr + 0U, // VANDPSZrrk + 0U, // VANDPSZrrkz + 0U, // VANDPSrm + 0U, // VANDPSrr + 0U, // VBLENDMPDZ128rm + 0U, // VBLENDMPDZ128rmb + 0U, // VBLENDMPDZ128rmbk + 0U, // VBLENDMPDZ128rmbkz + 0U, // VBLENDMPDZ128rmk + 0U, // VBLENDMPDZ128rmkz + 0U, // VBLENDMPDZ128rr + 0U, // VBLENDMPDZ128rrk + 0U, // VBLENDMPDZ128rrkz + 0U, // VBLENDMPDZ256rm + 0U, // VBLENDMPDZ256rmb + 0U, // VBLENDMPDZ256rmbk + 0U, // VBLENDMPDZ256rmbkz + 0U, // VBLENDMPDZ256rmk + 0U, // VBLENDMPDZ256rmkz + 0U, // VBLENDMPDZ256rr + 0U, // VBLENDMPDZ256rrk + 0U, // VBLENDMPDZ256rrkz + 0U, // VBLENDMPDZrm + 0U, // VBLENDMPDZrmb + 0U, // VBLENDMPDZrmbk + 0U, // VBLENDMPDZrmbkz + 0U, // VBLENDMPDZrmk + 0U, // VBLENDMPDZrmkz + 0U, // VBLENDMPDZrr + 0U, // VBLENDMPDZrrk + 0U, // VBLENDMPDZrrkz + 0U, // VBLENDMPSZ128rm + 0U, // VBLENDMPSZ128rmb + 0U, // VBLENDMPSZ128rmbk + 0U, // VBLENDMPSZ128rmbkz + 0U, // VBLENDMPSZ128rmk + 0U, // VBLENDMPSZ128rmkz + 0U, // VBLENDMPSZ128rr + 0U, // VBLENDMPSZ128rrk + 0U, // VBLENDMPSZ128rrkz + 0U, // VBLENDMPSZ256rm + 0U, // VBLENDMPSZ256rmb + 0U, // VBLENDMPSZ256rmbk + 0U, // VBLENDMPSZ256rmbkz + 0U, // VBLENDMPSZ256rmk + 0U, // VBLENDMPSZ256rmkz + 0U, // VBLENDMPSZ256rr + 0U, // VBLENDMPSZ256rrk + 0U, // VBLENDMPSZ256rrkz + 0U, // VBLENDMPSZrm + 0U, // VBLENDMPSZrmb + 0U, // VBLENDMPSZrmbk + 0U, // VBLENDMPSZrmbkz + 0U, // VBLENDMPSZrmk + 0U, // VBLENDMPSZrmkz + 0U, // VBLENDMPSZrr + 0U, // VBLENDMPSZrrk + 0U, // VBLENDMPSZrrkz + 0U, // VBLENDPDYrmi + 0U, // VBLENDPDYrri + 0U, // VBLENDPDrmi + 0U, // VBLENDPDrri + 0U, // VBLENDPSYrmi + 0U, // VBLENDPSYrri + 0U, // VBLENDPSrmi + 0U, // VBLENDPSrri + 0U, // VBLENDVPDYrm + 0U, // VBLENDVPDYrr + 0U, // VBLENDVPDrm + 0U, // VBLENDVPDrr + 0U, // VBLENDVPSYrm + 0U, // VBLENDVPSYrr + 0U, // VBLENDVPSrm + 0U, // VBLENDVPSrr + 0U, // VBROADCASTF128 + 0U, // VBROADCASTF32X2Z256m + 0U, // VBROADCASTF32X2Z256mk + 0U, // VBROADCASTF32X2Z256mkz + 0U, // VBROADCASTF32X2Z256r + 0U, // VBROADCASTF32X2Z256rk + 0U, // VBROADCASTF32X2Z256rkz + 0U, // VBROADCASTF32X2Zm + 0U, // VBROADCASTF32X2Zmk + 0U, // VBROADCASTF32X2Zmkz + 0U, // VBROADCASTF32X2Zr + 0U, // VBROADCASTF32X2Zrk + 0U, // VBROADCASTF32X2Zrkz + 0U, // VBROADCASTF32X4Z256rm + 0U, // VBROADCASTF32X4Z256rmk + 0U, // VBROADCASTF32X4Z256rmkz + 0U, // VBROADCASTF32X4rm + 0U, // VBROADCASTF32X4rmk + 0U, // VBROADCASTF32X4rmkz + 0U, // VBROADCASTF32X8rm + 0U, // VBROADCASTF32X8rmk + 0U, // VBROADCASTF32X8rmkz + 0U, // VBROADCASTF64X2Z128rm + 0U, // VBROADCASTF64X2Z128rmk + 0U, // VBROADCASTF64X2Z128rmkz + 0U, // VBROADCASTF64X2rm + 0U, // VBROADCASTF64X2rmk + 0U, // VBROADCASTF64X2rmkz + 0U, // VBROADCASTF64X4rm + 0U, // VBROADCASTF64X4rmk + 0U, // VBROADCASTF64X4rmkz + 0U, // VBROADCASTI128 + 0U, // VBROADCASTI32X2Z128m + 0U, // VBROADCASTI32X2Z128mk + 0U, // VBROADCASTI32X2Z128mkz + 0U, // VBROADCASTI32X2Z128r + 0U, // VBROADCASTI32X2Z128rk + 0U, // VBROADCASTI32X2Z128rkz + 0U, // VBROADCASTI32X2Z256m + 0U, // VBROADCASTI32X2Z256mk + 0U, // VBROADCASTI32X2Z256mkz + 0U, // VBROADCASTI32X2Z256r + 0U, // VBROADCASTI32X2Z256rk + 0U, // VBROADCASTI32X2Z256rkz + 0U, // VBROADCASTI32X2Zm + 0U, // VBROADCASTI32X2Zmk + 0U, // VBROADCASTI32X2Zmkz + 0U, // VBROADCASTI32X2Zr + 0U, // VBROADCASTI32X2Zrk + 0U, // VBROADCASTI32X2Zrkz + 0U, // VBROADCASTI32X4Z256rm + 0U, // VBROADCASTI32X4Z256rmk + 0U, // VBROADCASTI32X4Z256rmkz + 0U, // VBROADCASTI32X4rm + 0U, // VBROADCASTI32X4rmk + 0U, // VBROADCASTI32X4rmkz + 0U, // VBROADCASTI32X8rm + 0U, // VBROADCASTI32X8rmk + 0U, // VBROADCASTI32X8rmkz + 0U, // VBROADCASTI64X2Z128rm + 0U, // VBROADCASTI64X2Z128rmk + 0U, // VBROADCASTI64X2Z128rmkz + 0U, // VBROADCASTI64X2rm + 0U, // VBROADCASTI64X2rmk + 0U, // VBROADCASTI64X2rmkz + 0U, // VBROADCASTI64X4rm + 0U, // VBROADCASTI64X4rmk + 0U, // VBROADCASTI64X4rmkz + 0U, // VBROADCASTSDYrm + 0U, // VBROADCASTSDYrr + 0U, // VBROADCASTSDZ256m + 0U, // VBROADCASTSDZ256mk + 0U, // VBROADCASTSDZ256mkz + 0U, // VBROADCASTSDZ256r + 0U, // VBROADCASTSDZ256rk + 0U, // VBROADCASTSDZ256rkz + 0U, // VBROADCASTSDZm + 0U, // VBROADCASTSDZmk + 0U, // VBROADCASTSDZmkz + 0U, // VBROADCASTSDZr + 0U, // VBROADCASTSDZrk + 0U, // VBROADCASTSDZrkz + 0U, // VBROADCASTSSYrm + 0U, // VBROADCASTSSYrr + 0U, // VBROADCASTSSZ128m + 0U, // VBROADCASTSSZ128mk + 0U, // VBROADCASTSSZ128mkz + 0U, // VBROADCASTSSZ128r + 0U, // VBROADCASTSSZ128rk + 0U, // VBROADCASTSSZ128rkz + 0U, // VBROADCASTSSZ256m + 0U, // VBROADCASTSSZ256mk + 0U, // VBROADCASTSSZ256mkz + 0U, // VBROADCASTSSZ256r + 0U, // VBROADCASTSSZ256rk + 0U, // VBROADCASTSSZ256rkz + 0U, // VBROADCASTSSZm + 0U, // VBROADCASTSSZmk + 0U, // VBROADCASTSSZmkz + 0U, // VBROADCASTSSZr + 0U, // VBROADCASTSSZrk + 0U, // VBROADCASTSSZrkz + 0U, // VBROADCASTSSrm + 0U, // VBROADCASTSSrr + 0U, // VCMPPDYrmi + 0U, // VCMPPDYrmi_alt + 0U, // VCMPPDYrri + 0U, // VCMPPDYrri_alt + 0U, // VCMPPDZ128rmbi + 0U, // VCMPPDZ128rmbi_alt + 1U, // VCMPPDZ128rmbi_altk + 1U, // VCMPPDZ128rmbik + 0U, // VCMPPDZ128rmi + 0U, // VCMPPDZ128rmi_alt + 0U, // VCMPPDZ128rmi_altk + 0U, // VCMPPDZ128rmik + 0U, // VCMPPDZ128rri + 0U, // VCMPPDZ128rri_alt + 1U, // VCMPPDZ128rri_altk + 1U, // VCMPPDZ128rrik + 0U, // VCMPPDZ256rmbi + 0U, // VCMPPDZ256rmbi_alt + 1U, // VCMPPDZ256rmbi_altk + 1U, // VCMPPDZ256rmbik + 0U, // VCMPPDZ256rmi + 0U, // VCMPPDZ256rmi_alt + 0U, // VCMPPDZ256rmi_altk + 0U, // VCMPPDZ256rmik + 0U, // VCMPPDZ256rri + 0U, // VCMPPDZ256rri_alt + 1U, // VCMPPDZ256rri_altk + 1U, // VCMPPDZ256rrik + 0U, // VCMPPDZrmbi + 0U, // VCMPPDZrmbi_alt + 1U, // VCMPPDZrmbi_altk + 1U, // VCMPPDZrmbik + 0U, // VCMPPDZrmi + 0U, // VCMPPDZrmi_alt + 0U, // VCMPPDZrmi_altk + 0U, // VCMPPDZrmik + 0U, // VCMPPDZrri + 0U, // VCMPPDZrri_alt + 1U, // VCMPPDZrri_altk + 0U, // VCMPPDZrrib + 0U, // VCMPPDZrrib_alt + 1U, // VCMPPDZrrib_altk + 1U, // VCMPPDZrribk + 1U, // VCMPPDZrrik + 0U, // VCMPPDrmi + 0U, // VCMPPDrmi_alt + 0U, // VCMPPDrri + 0U, // VCMPPDrri_alt + 0U, // VCMPPSYrmi + 0U, // VCMPPSYrmi_alt + 0U, // VCMPPSYrri + 0U, // VCMPPSYrri_alt + 0U, // VCMPPSZ128rmbi + 0U, // VCMPPSZ128rmbi_alt + 1U, // VCMPPSZ128rmbi_altk + 1U, // VCMPPSZ128rmbik + 0U, // VCMPPSZ128rmi + 0U, // VCMPPSZ128rmi_alt + 0U, // VCMPPSZ128rmi_altk + 0U, // VCMPPSZ128rmik + 0U, // VCMPPSZ128rri + 0U, // VCMPPSZ128rri_alt + 1U, // VCMPPSZ128rri_altk + 1U, // VCMPPSZ128rrik + 0U, // VCMPPSZ256rmbi + 0U, // VCMPPSZ256rmbi_alt + 1U, // VCMPPSZ256rmbi_altk + 1U, // VCMPPSZ256rmbik + 0U, // VCMPPSZ256rmi + 0U, // VCMPPSZ256rmi_alt + 0U, // VCMPPSZ256rmi_altk + 0U, // VCMPPSZ256rmik + 0U, // VCMPPSZ256rri + 0U, // VCMPPSZ256rri_alt + 1U, // VCMPPSZ256rri_altk + 1U, // VCMPPSZ256rrik + 0U, // VCMPPSZrmbi + 0U, // VCMPPSZrmbi_alt + 1U, // VCMPPSZrmbi_altk + 1U, // VCMPPSZrmbik + 0U, // VCMPPSZrmi + 0U, // VCMPPSZrmi_alt + 0U, // VCMPPSZrmi_altk + 0U, // VCMPPSZrmik + 0U, // VCMPPSZrri + 0U, // VCMPPSZrri_alt + 1U, // VCMPPSZrri_altk + 0U, // VCMPPSZrrib + 0U, // VCMPPSZrrib_alt + 1U, // VCMPPSZrrib_altk + 1U, // VCMPPSZrribk + 1U, // VCMPPSZrrik + 0U, // VCMPPSrmi + 0U, // VCMPPSrmi_alt + 0U, // VCMPPSrri + 0U, // VCMPPSrri_alt + 0U, // VCMPSDZrm + 0U, // VCMPSDZrm_Int + 1U, // VCMPSDZrm_Intk + 0U, // VCMPSDZrmi_alt + 1U, // VCMPSDZrmi_altk + 0U, // VCMPSDZrr + 0U, // VCMPSDZrr_Int + 1U, // VCMPSDZrr_Intk + 0U, // VCMPSDZrrb_Int + 1U, // VCMPSDZrrb_Intk + 0U, // VCMPSDZrrb_alt + 1U, // VCMPSDZrrb_altk + 0U, // VCMPSDZrri_alt + 1U, // VCMPSDZrri_altk + 0U, // VCMPSDrm + 0U, // VCMPSDrm_Int + 0U, // VCMPSDrm_alt + 0U, // VCMPSDrr + 0U, // VCMPSDrr_Int + 0U, // VCMPSDrr_alt + 0U, // VCMPSSZrm + 0U, // VCMPSSZrm_Int + 1U, // VCMPSSZrm_Intk + 0U, // VCMPSSZrmi_alt + 1U, // VCMPSSZrmi_altk + 0U, // VCMPSSZrr + 0U, // VCMPSSZrr_Int + 1U, // VCMPSSZrr_Intk + 0U, // VCMPSSZrrb_Int + 1U, // VCMPSSZrrb_Intk + 0U, // VCMPSSZrrb_alt + 1U, // VCMPSSZrrb_altk + 0U, // VCMPSSZrri_alt + 1U, // VCMPSSZrri_altk + 0U, // VCMPSSrm + 0U, // VCMPSSrm_Int + 0U, // VCMPSSrm_alt + 0U, // VCMPSSrr + 0U, // VCMPSSrr_Int + 0U, // VCMPSSrr_alt + 0U, // VCOMISDZrm + 0U, // VCOMISDZrm_Int + 0U, // VCOMISDZrr + 0U, // VCOMISDZrr_Int + 0U, // VCOMISDZrrb + 0U, // VCOMISDrm + 0U, // VCOMISDrm_Int + 0U, // VCOMISDrr + 0U, // VCOMISDrr_Int + 0U, // VCOMISSZrm + 0U, // VCOMISSZrm_Int + 0U, // VCOMISSZrr + 0U, // VCOMISSZrr_Int + 0U, // VCOMISSZrrb + 0U, // VCOMISSrm + 0U, // VCOMISSrm_Int + 0U, // VCOMISSrr + 0U, // VCOMISSrr_Int + 0U, // VCOMPRESSPDZ128mr + 0U, // VCOMPRESSPDZ128mrk + 0U, // VCOMPRESSPDZ128rr + 0U, // VCOMPRESSPDZ128rrk + 0U, // VCOMPRESSPDZ128rrkz + 0U, // VCOMPRESSPDZ256mr + 0U, // VCOMPRESSPDZ256mrk + 0U, // VCOMPRESSPDZ256rr + 0U, // VCOMPRESSPDZ256rrk + 0U, // VCOMPRESSPDZ256rrkz + 0U, // VCOMPRESSPDZmr + 0U, // VCOMPRESSPDZmrk + 0U, // VCOMPRESSPDZrr + 0U, // VCOMPRESSPDZrrk + 0U, // VCOMPRESSPDZrrkz + 0U, // VCOMPRESSPSZ128mr + 0U, // VCOMPRESSPSZ128mrk + 0U, // VCOMPRESSPSZ128rr + 0U, // VCOMPRESSPSZ128rrk + 0U, // VCOMPRESSPSZ128rrkz + 0U, // VCOMPRESSPSZ256mr + 0U, // VCOMPRESSPSZ256mrk + 0U, // VCOMPRESSPSZ256rr + 0U, // VCOMPRESSPSZ256rrk + 0U, // VCOMPRESSPSZ256rrkz + 0U, // VCOMPRESSPSZmr + 0U, // VCOMPRESSPSZmrk + 0U, // VCOMPRESSPSZrr + 0U, // VCOMPRESSPSZrrk + 0U, // VCOMPRESSPSZrrkz + 0U, // VCVTDQ2PDYrm + 0U, // VCVTDQ2PDYrr + 0U, // VCVTDQ2PDZ128rm + 0U, // VCVTDQ2PDZ128rmb + 0U, // VCVTDQ2PDZ128rmbk + 0U, // VCVTDQ2PDZ128rmbkz + 0U, // VCVTDQ2PDZ128rmk + 0U, // VCVTDQ2PDZ128rmkz + 0U, // VCVTDQ2PDZ128rr + 0U, // VCVTDQ2PDZ128rrk + 0U, // VCVTDQ2PDZ128rrkz + 0U, // VCVTDQ2PDZ256rm + 0U, // VCVTDQ2PDZ256rmb + 0U, // VCVTDQ2PDZ256rmbk + 0U, // VCVTDQ2PDZ256rmbkz + 0U, // VCVTDQ2PDZ256rmk + 0U, // VCVTDQ2PDZ256rmkz + 0U, // VCVTDQ2PDZ256rr + 0U, // VCVTDQ2PDZ256rrk + 0U, // VCVTDQ2PDZ256rrkz + 0U, // VCVTDQ2PDZrm + 0U, // VCVTDQ2PDZrmb + 0U, // VCVTDQ2PDZrmbk + 0U, // VCVTDQ2PDZrmbkz + 0U, // VCVTDQ2PDZrmk + 0U, // VCVTDQ2PDZrmkz + 0U, // VCVTDQ2PDZrr + 0U, // VCVTDQ2PDZrrk + 0U, // VCVTDQ2PDZrrkz + 0U, // VCVTDQ2PDrm + 0U, // VCVTDQ2PDrr + 0U, // VCVTDQ2PSYrm + 0U, // VCVTDQ2PSYrr + 0U, // VCVTDQ2PSZ128rm + 0U, // VCVTDQ2PSZ128rmb + 0U, // VCVTDQ2PSZ128rmbk + 0U, // VCVTDQ2PSZ128rmbkz + 0U, // VCVTDQ2PSZ128rmk + 0U, // VCVTDQ2PSZ128rmkz + 0U, // VCVTDQ2PSZ128rr + 0U, // VCVTDQ2PSZ128rrk + 0U, // VCVTDQ2PSZ128rrkz + 0U, // VCVTDQ2PSZ256rm + 0U, // VCVTDQ2PSZ256rmb + 0U, // VCVTDQ2PSZ256rmbk + 0U, // VCVTDQ2PSZ256rmbkz + 0U, // VCVTDQ2PSZ256rmk + 0U, // VCVTDQ2PSZ256rmkz + 0U, // VCVTDQ2PSZ256rr + 0U, // VCVTDQ2PSZ256rrk + 0U, // VCVTDQ2PSZ256rrkz + 0U, // VCVTDQ2PSZrm + 0U, // VCVTDQ2PSZrmb + 0U, // VCVTDQ2PSZrmbk + 0U, // VCVTDQ2PSZrmbkz + 0U, // VCVTDQ2PSZrmk + 0U, // VCVTDQ2PSZrmkz + 0U, // VCVTDQ2PSZrr + 0U, // VCVTDQ2PSZrrb + 0U, // VCVTDQ2PSZrrbk + 0U, // VCVTDQ2PSZrrbkz + 0U, // VCVTDQ2PSZrrk + 0U, // VCVTDQ2PSZrrkz + 0U, // VCVTDQ2PSrm + 0U, // VCVTDQ2PSrr + 0U, // VCVTPD2DQYrm + 0U, // VCVTPD2DQYrr + 0U, // VCVTPD2DQZ128rm + 0U, // VCVTPD2DQZ128rmb + 0U, // VCVTPD2DQZ128rmbk + 0U, // VCVTPD2DQZ128rmbkz + 0U, // VCVTPD2DQZ128rmk + 0U, // VCVTPD2DQZ128rmkz + 0U, // VCVTPD2DQZ128rr + 0U, // VCVTPD2DQZ128rrk + 0U, // VCVTPD2DQZ128rrkz + 0U, // VCVTPD2DQZ256rm + 0U, // VCVTPD2DQZ256rmb + 0U, // VCVTPD2DQZ256rmbk + 0U, // VCVTPD2DQZ256rmbkz + 0U, // VCVTPD2DQZ256rmk + 0U, // VCVTPD2DQZ256rmkz + 0U, // VCVTPD2DQZ256rr + 0U, // VCVTPD2DQZ256rrk + 0U, // VCVTPD2DQZ256rrkz + 0U, // VCVTPD2DQZrm + 0U, // VCVTPD2DQZrmb + 0U, // VCVTPD2DQZrmbk + 0U, // VCVTPD2DQZrmbkz + 0U, // VCVTPD2DQZrmk + 0U, // VCVTPD2DQZrmkz + 0U, // VCVTPD2DQZrr + 0U, // VCVTPD2DQZrrb + 0U, // VCVTPD2DQZrrbk + 0U, // VCVTPD2DQZrrbkz + 0U, // VCVTPD2DQZrrk + 0U, // VCVTPD2DQZrrkz + 0U, // VCVTPD2DQrm + 0U, // VCVTPD2DQrr + 0U, // VCVTPD2PSYrm + 0U, // VCVTPD2PSYrr + 0U, // VCVTPD2PSZ128rm + 0U, // VCVTPD2PSZ128rmb + 0U, // VCVTPD2PSZ128rmbk + 0U, // VCVTPD2PSZ128rmbkz + 0U, // VCVTPD2PSZ128rmk + 0U, // VCVTPD2PSZ128rmkz + 0U, // VCVTPD2PSZ128rr + 0U, // VCVTPD2PSZ128rrk + 0U, // VCVTPD2PSZ128rrkz + 0U, // VCVTPD2PSZ256rm + 0U, // VCVTPD2PSZ256rmb + 0U, // VCVTPD2PSZ256rmbk + 0U, // VCVTPD2PSZ256rmbkz + 0U, // VCVTPD2PSZ256rmk + 0U, // VCVTPD2PSZ256rmkz + 0U, // VCVTPD2PSZ256rr + 0U, // VCVTPD2PSZ256rrk + 0U, // VCVTPD2PSZ256rrkz + 0U, // VCVTPD2PSZrm + 0U, // VCVTPD2PSZrmb + 0U, // VCVTPD2PSZrmbk + 0U, // VCVTPD2PSZrmbkz + 0U, // VCVTPD2PSZrmk + 0U, // VCVTPD2PSZrmkz + 0U, // VCVTPD2PSZrr + 0U, // VCVTPD2PSZrrb + 0U, // VCVTPD2PSZrrbk + 0U, // VCVTPD2PSZrrbkz + 0U, // VCVTPD2PSZrrk + 0U, // VCVTPD2PSZrrkz + 0U, // VCVTPD2PSrm + 0U, // VCVTPD2PSrr + 0U, // VCVTPD2QQZ128rm + 0U, // VCVTPD2QQZ128rmb + 0U, // VCVTPD2QQZ128rmbk + 0U, // VCVTPD2QQZ128rmbkz + 0U, // VCVTPD2QQZ128rmk + 0U, // VCVTPD2QQZ128rmkz + 0U, // VCVTPD2QQZ128rr + 0U, // VCVTPD2QQZ128rrk + 0U, // VCVTPD2QQZ128rrkz + 0U, // VCVTPD2QQZ256rm + 0U, // VCVTPD2QQZ256rmb + 0U, // VCVTPD2QQZ256rmbk + 0U, // VCVTPD2QQZ256rmbkz + 0U, // VCVTPD2QQZ256rmk + 0U, // VCVTPD2QQZ256rmkz + 0U, // VCVTPD2QQZ256rr + 0U, // VCVTPD2QQZ256rrk + 0U, // VCVTPD2QQZ256rrkz + 0U, // VCVTPD2QQZrm + 0U, // VCVTPD2QQZrmb + 0U, // VCVTPD2QQZrmbk + 0U, // VCVTPD2QQZrmbkz + 0U, // VCVTPD2QQZrmk + 0U, // VCVTPD2QQZrmkz + 0U, // VCVTPD2QQZrr + 0U, // VCVTPD2QQZrrb + 0U, // VCVTPD2QQZrrbk + 0U, // VCVTPD2QQZrrbkz + 0U, // VCVTPD2QQZrrk + 0U, // VCVTPD2QQZrrkz + 0U, // VCVTPD2UDQZ128rm + 0U, // VCVTPD2UDQZ128rmb + 0U, // VCVTPD2UDQZ128rmbk + 0U, // VCVTPD2UDQZ128rmbkz + 0U, // VCVTPD2UDQZ128rmk + 0U, // VCVTPD2UDQZ128rmkz + 0U, // VCVTPD2UDQZ128rr + 0U, // VCVTPD2UDQZ128rrk + 0U, // VCVTPD2UDQZ128rrkz + 0U, // VCVTPD2UDQZ256rm + 0U, // VCVTPD2UDQZ256rmb + 0U, // VCVTPD2UDQZ256rmbk + 0U, // VCVTPD2UDQZ256rmbkz + 0U, // VCVTPD2UDQZ256rmk + 0U, // VCVTPD2UDQZ256rmkz + 0U, // VCVTPD2UDQZ256rr + 0U, // VCVTPD2UDQZ256rrk + 0U, // VCVTPD2UDQZ256rrkz + 0U, // VCVTPD2UDQZrm + 0U, // VCVTPD2UDQZrmb + 0U, // VCVTPD2UDQZrmbk + 0U, // VCVTPD2UDQZrmbkz + 0U, // VCVTPD2UDQZrmk + 0U, // VCVTPD2UDQZrmkz + 0U, // VCVTPD2UDQZrr + 0U, // VCVTPD2UDQZrrb + 0U, // VCVTPD2UDQZrrbk + 0U, // VCVTPD2UDQZrrbkz + 0U, // VCVTPD2UDQZrrk + 0U, // VCVTPD2UDQZrrkz + 0U, // VCVTPD2UQQZ128rm + 0U, // VCVTPD2UQQZ128rmb + 0U, // VCVTPD2UQQZ128rmbk + 0U, // VCVTPD2UQQZ128rmbkz + 0U, // VCVTPD2UQQZ128rmk + 0U, // VCVTPD2UQQZ128rmkz + 0U, // VCVTPD2UQQZ128rr + 0U, // VCVTPD2UQQZ128rrk + 0U, // VCVTPD2UQQZ128rrkz + 0U, // VCVTPD2UQQZ256rm + 0U, // VCVTPD2UQQZ256rmb + 0U, // VCVTPD2UQQZ256rmbk + 0U, // VCVTPD2UQQZ256rmbkz + 0U, // VCVTPD2UQQZ256rmk + 0U, // VCVTPD2UQQZ256rmkz + 0U, // VCVTPD2UQQZ256rr + 0U, // VCVTPD2UQQZ256rrk + 0U, // VCVTPD2UQQZ256rrkz + 0U, // VCVTPD2UQQZrm + 0U, // VCVTPD2UQQZrmb + 0U, // VCVTPD2UQQZrmbk + 0U, // VCVTPD2UQQZrmbkz + 0U, // VCVTPD2UQQZrmk + 0U, // VCVTPD2UQQZrmkz + 0U, // VCVTPD2UQQZrr + 0U, // VCVTPD2UQQZrrb + 0U, // VCVTPD2UQQZrrbk + 0U, // VCVTPD2UQQZrrbkz + 0U, // VCVTPD2UQQZrrk + 0U, // VCVTPD2UQQZrrkz + 0U, // VCVTPH2PSYrm + 0U, // VCVTPH2PSYrr + 0U, // VCVTPH2PSZ128rm + 0U, // VCVTPH2PSZ128rmk + 0U, // VCVTPH2PSZ128rmkz + 0U, // VCVTPH2PSZ128rr + 0U, // VCVTPH2PSZ128rrk + 0U, // VCVTPH2PSZ128rrkz + 0U, // VCVTPH2PSZ256rm + 0U, // VCVTPH2PSZ256rmk + 0U, // VCVTPH2PSZ256rmkz + 0U, // VCVTPH2PSZ256rr + 0U, // VCVTPH2PSZ256rrk + 0U, // VCVTPH2PSZ256rrkz + 0U, // VCVTPH2PSZrm + 0U, // VCVTPH2PSZrmk + 0U, // VCVTPH2PSZrmkz + 0U, // VCVTPH2PSZrr + 0U, // VCVTPH2PSZrrb + 0U, // VCVTPH2PSZrrbk + 0U, // VCVTPH2PSZrrbkz + 0U, // VCVTPH2PSZrrk + 0U, // VCVTPH2PSZrrkz + 0U, // VCVTPH2PSrm + 0U, // VCVTPH2PSrr + 0U, // VCVTPS2DQYrm + 0U, // VCVTPS2DQYrr + 0U, // VCVTPS2DQZ128rm + 0U, // VCVTPS2DQZ128rmb + 0U, // VCVTPS2DQZ128rmbk + 0U, // VCVTPS2DQZ128rmbkz + 0U, // VCVTPS2DQZ128rmk + 0U, // VCVTPS2DQZ128rmkz + 0U, // VCVTPS2DQZ128rr + 0U, // VCVTPS2DQZ128rrk + 0U, // VCVTPS2DQZ128rrkz + 0U, // VCVTPS2DQZ256rm + 0U, // VCVTPS2DQZ256rmb + 0U, // VCVTPS2DQZ256rmbk + 0U, // VCVTPS2DQZ256rmbkz + 0U, // VCVTPS2DQZ256rmk + 0U, // VCVTPS2DQZ256rmkz + 0U, // VCVTPS2DQZ256rr + 0U, // VCVTPS2DQZ256rrk + 0U, // VCVTPS2DQZ256rrkz + 0U, // VCVTPS2DQZrm + 0U, // VCVTPS2DQZrmb + 0U, // VCVTPS2DQZrmbk + 0U, // VCVTPS2DQZrmbkz + 0U, // VCVTPS2DQZrmk + 0U, // VCVTPS2DQZrmkz + 0U, // VCVTPS2DQZrr + 0U, // VCVTPS2DQZrrb + 0U, // VCVTPS2DQZrrbk + 0U, // VCVTPS2DQZrrbkz + 0U, // VCVTPS2DQZrrk + 0U, // VCVTPS2DQZrrkz + 0U, // VCVTPS2DQrm + 0U, // VCVTPS2DQrr + 0U, // VCVTPS2PDYrm + 0U, // VCVTPS2PDYrr + 0U, // VCVTPS2PDZ128rm + 0U, // VCVTPS2PDZ128rmb + 0U, // VCVTPS2PDZ128rmbk + 0U, // VCVTPS2PDZ128rmbkz + 0U, // VCVTPS2PDZ128rmk + 0U, // VCVTPS2PDZ128rmkz + 0U, // VCVTPS2PDZ128rr + 0U, // VCVTPS2PDZ128rrk + 0U, // VCVTPS2PDZ128rrkz + 0U, // VCVTPS2PDZ256rm + 0U, // VCVTPS2PDZ256rmb + 0U, // VCVTPS2PDZ256rmbk + 0U, // VCVTPS2PDZ256rmbkz + 0U, // VCVTPS2PDZ256rmk + 0U, // VCVTPS2PDZ256rmkz + 0U, // VCVTPS2PDZ256rr + 0U, // VCVTPS2PDZ256rrk + 0U, // VCVTPS2PDZ256rrkz + 0U, // VCVTPS2PDZrm + 0U, // VCVTPS2PDZrmb + 0U, // VCVTPS2PDZrmbk + 0U, // VCVTPS2PDZrmbkz + 0U, // VCVTPS2PDZrmk + 0U, // VCVTPS2PDZrmkz + 0U, // VCVTPS2PDZrr + 0U, // VCVTPS2PDZrrb + 0U, // VCVTPS2PDZrrbk + 0U, // VCVTPS2PDZrrbkz + 0U, // VCVTPS2PDZrrk + 0U, // VCVTPS2PDZrrkz + 0U, // VCVTPS2PDrm + 0U, // VCVTPS2PDrr + 0U, // VCVTPS2PHYmr + 0U, // VCVTPS2PHYrr + 0U, // VCVTPS2PHZ128mr + 0U, // VCVTPS2PHZ128mrk + 0U, // VCVTPS2PHZ128rr + 0U, // VCVTPS2PHZ128rrk + 0U, // VCVTPS2PHZ128rrkz + 0U, // VCVTPS2PHZ256mr + 0U, // VCVTPS2PHZ256mrk + 0U, // VCVTPS2PHZ256rr + 0U, // VCVTPS2PHZ256rrk + 0U, // VCVTPS2PHZ256rrkz + 0U, // VCVTPS2PHZmr + 0U, // VCVTPS2PHZmrk + 0U, // VCVTPS2PHZrr + 0U, // VCVTPS2PHZrrb + 0U, // VCVTPS2PHZrrbk + 0U, // VCVTPS2PHZrrbkz + 0U, // VCVTPS2PHZrrk + 0U, // VCVTPS2PHZrrkz + 0U, // VCVTPS2PHmr + 0U, // VCVTPS2PHrr + 0U, // VCVTPS2QQZ128rm + 0U, // VCVTPS2QQZ128rmb + 0U, // VCVTPS2QQZ128rmbk + 0U, // VCVTPS2QQZ128rmbkz + 0U, // VCVTPS2QQZ128rmk + 0U, // VCVTPS2QQZ128rmkz + 0U, // VCVTPS2QQZ128rr + 0U, // VCVTPS2QQZ128rrk + 0U, // VCVTPS2QQZ128rrkz + 0U, // VCVTPS2QQZ256rm + 0U, // VCVTPS2QQZ256rmb + 0U, // VCVTPS2QQZ256rmbk + 0U, // VCVTPS2QQZ256rmbkz + 0U, // VCVTPS2QQZ256rmk + 0U, // VCVTPS2QQZ256rmkz + 0U, // VCVTPS2QQZ256rr + 0U, // VCVTPS2QQZ256rrk + 0U, // VCVTPS2QQZ256rrkz + 0U, // VCVTPS2QQZrm + 0U, // VCVTPS2QQZrmb + 0U, // VCVTPS2QQZrmbk + 0U, // VCVTPS2QQZrmbkz + 0U, // VCVTPS2QQZrmk + 0U, // VCVTPS2QQZrmkz + 0U, // VCVTPS2QQZrr + 0U, // VCVTPS2QQZrrb + 0U, // VCVTPS2QQZrrbk + 0U, // VCVTPS2QQZrrbkz + 0U, // VCVTPS2QQZrrk + 0U, // VCVTPS2QQZrrkz + 0U, // VCVTPS2UDQZ128rm + 0U, // VCVTPS2UDQZ128rmb + 0U, // VCVTPS2UDQZ128rmbk + 0U, // VCVTPS2UDQZ128rmbkz + 0U, // VCVTPS2UDQZ128rmk + 0U, // VCVTPS2UDQZ128rmkz + 0U, // VCVTPS2UDQZ128rr + 0U, // VCVTPS2UDQZ128rrk + 0U, // VCVTPS2UDQZ128rrkz + 0U, // VCVTPS2UDQZ256rm + 0U, // VCVTPS2UDQZ256rmb + 0U, // VCVTPS2UDQZ256rmbk + 0U, // VCVTPS2UDQZ256rmbkz + 0U, // VCVTPS2UDQZ256rmk + 0U, // VCVTPS2UDQZ256rmkz + 0U, // VCVTPS2UDQZ256rr + 0U, // VCVTPS2UDQZ256rrk + 0U, // VCVTPS2UDQZ256rrkz + 0U, // VCVTPS2UDQZrm + 0U, // VCVTPS2UDQZrmb + 0U, // VCVTPS2UDQZrmbk + 0U, // VCVTPS2UDQZrmbkz + 0U, // VCVTPS2UDQZrmk + 0U, // VCVTPS2UDQZrmkz + 0U, // VCVTPS2UDQZrr + 0U, // VCVTPS2UDQZrrb + 0U, // VCVTPS2UDQZrrbk + 0U, // VCVTPS2UDQZrrbkz + 0U, // VCVTPS2UDQZrrk + 0U, // VCVTPS2UDQZrrkz + 0U, // VCVTPS2UQQZ128rm + 0U, // VCVTPS2UQQZ128rmb + 0U, // VCVTPS2UQQZ128rmbk + 0U, // VCVTPS2UQQZ128rmbkz + 0U, // VCVTPS2UQQZ128rmk + 0U, // VCVTPS2UQQZ128rmkz + 0U, // VCVTPS2UQQZ128rr + 0U, // VCVTPS2UQQZ128rrk + 0U, // VCVTPS2UQQZ128rrkz + 0U, // VCVTPS2UQQZ256rm + 0U, // VCVTPS2UQQZ256rmb + 0U, // VCVTPS2UQQZ256rmbk + 0U, // VCVTPS2UQQZ256rmbkz + 0U, // VCVTPS2UQQZ256rmk + 0U, // VCVTPS2UQQZ256rmkz + 0U, // VCVTPS2UQQZ256rr + 0U, // VCVTPS2UQQZ256rrk + 0U, // VCVTPS2UQQZ256rrkz + 0U, // VCVTPS2UQQZrm + 0U, // VCVTPS2UQQZrmb + 0U, // VCVTPS2UQQZrmbk + 0U, // VCVTPS2UQQZrmbkz + 0U, // VCVTPS2UQQZrmk + 0U, // VCVTPS2UQQZrmkz + 0U, // VCVTPS2UQQZrr + 0U, // VCVTPS2UQQZrrb + 0U, // VCVTPS2UQQZrrbk + 0U, // VCVTPS2UQQZrrbkz + 0U, // VCVTPS2UQQZrrk + 0U, // VCVTPS2UQQZrrkz + 0U, // VCVTQQ2PDZ128rm + 0U, // VCVTQQ2PDZ128rmb + 0U, // VCVTQQ2PDZ128rmbk + 0U, // VCVTQQ2PDZ128rmbkz + 0U, // VCVTQQ2PDZ128rmk + 0U, // VCVTQQ2PDZ128rmkz + 0U, // VCVTQQ2PDZ128rr + 0U, // VCVTQQ2PDZ128rrk + 0U, // VCVTQQ2PDZ128rrkz + 0U, // VCVTQQ2PDZ256rm + 0U, // VCVTQQ2PDZ256rmb + 0U, // VCVTQQ2PDZ256rmbk + 0U, // VCVTQQ2PDZ256rmbkz + 0U, // VCVTQQ2PDZ256rmk + 0U, // VCVTQQ2PDZ256rmkz + 0U, // VCVTQQ2PDZ256rr + 0U, // VCVTQQ2PDZ256rrk + 0U, // VCVTQQ2PDZ256rrkz + 0U, // VCVTQQ2PDZrm + 0U, // VCVTQQ2PDZrmb + 0U, // VCVTQQ2PDZrmbk + 0U, // VCVTQQ2PDZrmbkz + 0U, // VCVTQQ2PDZrmk + 0U, // VCVTQQ2PDZrmkz + 0U, // VCVTQQ2PDZrr + 0U, // VCVTQQ2PDZrrb + 0U, // VCVTQQ2PDZrrbk + 0U, // VCVTQQ2PDZrrbkz + 0U, // VCVTQQ2PDZrrk + 0U, // VCVTQQ2PDZrrkz + 0U, // VCVTQQ2PSZ128rm + 0U, // VCVTQQ2PSZ128rmb + 0U, // VCVTQQ2PSZ128rmbk + 0U, // VCVTQQ2PSZ128rmbkz + 0U, // VCVTQQ2PSZ128rmk + 0U, // VCVTQQ2PSZ128rmkz + 0U, // VCVTQQ2PSZ128rr + 0U, // VCVTQQ2PSZ128rrk + 0U, // VCVTQQ2PSZ128rrkz + 0U, // VCVTQQ2PSZ256rm + 0U, // VCVTQQ2PSZ256rmb + 0U, // VCVTQQ2PSZ256rmbk + 0U, // VCVTQQ2PSZ256rmbkz + 0U, // VCVTQQ2PSZ256rmk + 0U, // VCVTQQ2PSZ256rmkz + 0U, // VCVTQQ2PSZ256rr + 0U, // VCVTQQ2PSZ256rrk + 0U, // VCVTQQ2PSZ256rrkz + 0U, // VCVTQQ2PSZrm + 0U, // VCVTQQ2PSZrmb + 0U, // VCVTQQ2PSZrmbk + 0U, // VCVTQQ2PSZrmbkz + 0U, // VCVTQQ2PSZrmk + 0U, // VCVTQQ2PSZrmkz + 0U, // VCVTQQ2PSZrr + 0U, // VCVTQQ2PSZrrb + 0U, // VCVTQQ2PSZrrbk + 0U, // VCVTQQ2PSZrrbkz + 0U, // VCVTQQ2PSZrrk + 0U, // VCVTQQ2PSZrrkz + 0U, // VCVTSD2SI64Zrm_Int + 0U, // VCVTSD2SI64Zrr_Int + 0U, // VCVTSD2SI64Zrrb_Int + 0U, // VCVTSD2SI64rm_Int + 0U, // VCVTSD2SI64rr_Int + 0U, // VCVTSD2SIZrm_Int + 0U, // VCVTSD2SIZrr_Int + 0U, // VCVTSD2SIZrrb_Int + 0U, // VCVTSD2SIrm_Int + 0U, // VCVTSD2SIrr_Int + 0U, // VCVTSD2SSZrm + 0U, // VCVTSD2SSZrm_Int + 0U, // VCVTSD2SSZrm_Intk + 0U, // VCVTSD2SSZrm_Intkz + 0U, // VCVTSD2SSZrr + 0U, // VCVTSD2SSZrr_Int + 0U, // VCVTSD2SSZrr_Intk + 0U, // VCVTSD2SSZrr_Intkz + 0U, // VCVTSD2SSZrrb_Int + 0U, // VCVTSD2SSZrrb_Intk + 0U, // VCVTSD2SSZrrb_Intkz + 0U, // VCVTSD2SSrm + 0U, // VCVTSD2SSrm_Int + 0U, // VCVTSD2SSrr + 0U, // VCVTSD2SSrr_Int + 0U, // VCVTSD2USI64Zrm_Int + 0U, // VCVTSD2USI64Zrr_Int + 0U, // VCVTSD2USI64Zrrb_Int + 0U, // VCVTSD2USIZrm_Int + 0U, // VCVTSD2USIZrr_Int + 0U, // VCVTSD2USIZrrb_Int + 0U, // VCVTSI2SDZrm + 0U, // VCVTSI2SDZrm_Int + 0U, // VCVTSI2SDZrr + 0U, // VCVTSI2SDZrr_Int + 0U, // VCVTSI2SDZrrb_Int + 0U, // VCVTSI2SDrm + 0U, // VCVTSI2SDrm_Int + 0U, // VCVTSI2SDrr + 0U, // VCVTSI2SDrr_Int + 0U, // VCVTSI2SSZrm + 0U, // VCVTSI2SSZrm_Int + 0U, // VCVTSI2SSZrr + 0U, // VCVTSI2SSZrr_Int + 0U, // VCVTSI2SSZrrb_Int + 0U, // VCVTSI2SSrm + 0U, // VCVTSI2SSrm_Int + 0U, // VCVTSI2SSrr + 0U, // VCVTSI2SSrr_Int + 0U, // VCVTSI642SDZrm + 0U, // VCVTSI642SDZrm_Int + 0U, // VCVTSI642SDZrr + 0U, // VCVTSI642SDZrr_Int + 0U, // VCVTSI642SDZrrb_Int + 0U, // VCVTSI642SDrm + 0U, // VCVTSI642SDrm_Int + 0U, // VCVTSI642SDrr + 0U, // VCVTSI642SDrr_Int + 0U, // VCVTSI642SSZrm + 0U, // VCVTSI642SSZrm_Int + 0U, // VCVTSI642SSZrr + 0U, // VCVTSI642SSZrr_Int + 0U, // VCVTSI642SSZrrb_Int + 0U, // VCVTSI642SSrm + 0U, // VCVTSI642SSrm_Int + 0U, // VCVTSI642SSrr + 0U, // VCVTSI642SSrr_Int + 0U, // VCVTSS2SDZrm + 0U, // VCVTSS2SDZrm_Int + 0U, // VCVTSS2SDZrm_Intk + 0U, // VCVTSS2SDZrm_Intkz + 0U, // VCVTSS2SDZrr + 0U, // VCVTSS2SDZrr_Int + 0U, // VCVTSS2SDZrr_Intk + 0U, // VCVTSS2SDZrr_Intkz + 0U, // VCVTSS2SDZrrb_Int + 0U, // VCVTSS2SDZrrb_Intk + 0U, // VCVTSS2SDZrrb_Intkz + 0U, // VCVTSS2SDrm + 0U, // VCVTSS2SDrm_Int + 0U, // VCVTSS2SDrr + 0U, // VCVTSS2SDrr_Int + 0U, // VCVTSS2SI64Zrm_Int + 0U, // VCVTSS2SI64Zrr_Int + 0U, // VCVTSS2SI64Zrrb_Int + 0U, // VCVTSS2SI64rm_Int + 0U, // VCVTSS2SI64rr_Int + 0U, // VCVTSS2SIZrm_Int + 0U, // VCVTSS2SIZrr_Int + 0U, // VCVTSS2SIZrrb_Int + 0U, // VCVTSS2SIrm_Int + 0U, // VCVTSS2SIrr_Int + 0U, // VCVTSS2USI64Zrm_Int + 0U, // VCVTSS2USI64Zrr_Int + 0U, // VCVTSS2USI64Zrrb_Int + 0U, // VCVTSS2USIZrm_Int + 0U, // VCVTSS2USIZrr_Int + 0U, // VCVTSS2USIZrrb_Int + 0U, // VCVTTPD2DQYrm + 0U, // VCVTTPD2DQYrr + 0U, // VCVTTPD2DQZ128rm + 0U, // VCVTTPD2DQZ128rmb + 0U, // VCVTTPD2DQZ128rmbk + 0U, // VCVTTPD2DQZ128rmbkz + 0U, // VCVTTPD2DQZ128rmk + 0U, // VCVTTPD2DQZ128rmkz + 0U, // VCVTTPD2DQZ128rr + 0U, // VCVTTPD2DQZ128rrk + 0U, // VCVTTPD2DQZ128rrkz + 0U, // VCVTTPD2DQZ256rm + 0U, // VCVTTPD2DQZ256rmb + 0U, // VCVTTPD2DQZ256rmbk + 0U, // VCVTTPD2DQZ256rmbkz + 0U, // VCVTTPD2DQZ256rmk + 0U, // VCVTTPD2DQZ256rmkz + 0U, // VCVTTPD2DQZ256rr + 0U, // VCVTTPD2DQZ256rrk + 0U, // VCVTTPD2DQZ256rrkz + 0U, // VCVTTPD2DQZrm + 0U, // VCVTTPD2DQZrmb + 0U, // VCVTTPD2DQZrmbk + 0U, // VCVTTPD2DQZrmbkz + 0U, // VCVTTPD2DQZrmk + 0U, // VCVTTPD2DQZrmkz + 0U, // VCVTTPD2DQZrr + 0U, // VCVTTPD2DQZrrb + 0U, // VCVTTPD2DQZrrbk + 0U, // VCVTTPD2DQZrrbkz + 0U, // VCVTTPD2DQZrrk + 0U, // VCVTTPD2DQZrrkz + 0U, // VCVTTPD2DQrm + 0U, // VCVTTPD2DQrr + 0U, // VCVTTPD2QQZ128rm + 0U, // VCVTTPD2QQZ128rmb + 0U, // VCVTTPD2QQZ128rmbk + 0U, // VCVTTPD2QQZ128rmbkz + 0U, // VCVTTPD2QQZ128rmk + 0U, // VCVTTPD2QQZ128rmkz + 0U, // VCVTTPD2QQZ128rr + 0U, // VCVTTPD2QQZ128rrk + 0U, // VCVTTPD2QQZ128rrkz + 0U, // VCVTTPD2QQZ256rm + 0U, // VCVTTPD2QQZ256rmb + 0U, // VCVTTPD2QQZ256rmbk + 0U, // VCVTTPD2QQZ256rmbkz + 0U, // VCVTTPD2QQZ256rmk + 0U, // VCVTTPD2QQZ256rmkz + 0U, // VCVTTPD2QQZ256rr + 0U, // VCVTTPD2QQZ256rrk + 0U, // VCVTTPD2QQZ256rrkz + 0U, // VCVTTPD2QQZrm + 0U, // VCVTTPD2QQZrmb + 0U, // VCVTTPD2QQZrmbk + 0U, // VCVTTPD2QQZrmbkz + 0U, // VCVTTPD2QQZrmk + 0U, // VCVTTPD2QQZrmkz + 0U, // VCVTTPD2QQZrr + 0U, // VCVTTPD2QQZrrb + 0U, // VCVTTPD2QQZrrbk + 0U, // VCVTTPD2QQZrrbkz + 0U, // VCVTTPD2QQZrrk + 0U, // VCVTTPD2QQZrrkz + 0U, // VCVTTPD2UDQZ128rm + 0U, // VCVTTPD2UDQZ128rmb + 0U, // VCVTTPD2UDQZ128rmbk + 0U, // VCVTTPD2UDQZ128rmbkz + 0U, // VCVTTPD2UDQZ128rmk + 0U, // VCVTTPD2UDQZ128rmkz + 0U, // VCVTTPD2UDQZ128rr + 0U, // VCVTTPD2UDQZ128rrk + 0U, // VCVTTPD2UDQZ128rrkz + 0U, // VCVTTPD2UDQZ256rm + 0U, // VCVTTPD2UDQZ256rmb + 0U, // VCVTTPD2UDQZ256rmbk + 0U, // VCVTTPD2UDQZ256rmbkz + 0U, // VCVTTPD2UDQZ256rmk + 0U, // VCVTTPD2UDQZ256rmkz + 0U, // VCVTTPD2UDQZ256rr + 0U, // VCVTTPD2UDQZ256rrk + 0U, // VCVTTPD2UDQZ256rrkz + 0U, // VCVTTPD2UDQZrm + 0U, // VCVTTPD2UDQZrmb + 0U, // VCVTTPD2UDQZrmbk + 0U, // VCVTTPD2UDQZrmbkz + 0U, // VCVTTPD2UDQZrmk + 0U, // VCVTTPD2UDQZrmkz + 0U, // VCVTTPD2UDQZrr + 0U, // VCVTTPD2UDQZrrb + 0U, // VCVTTPD2UDQZrrbk + 0U, // VCVTTPD2UDQZrrbkz + 0U, // VCVTTPD2UDQZrrk + 0U, // VCVTTPD2UDQZrrkz + 0U, // VCVTTPD2UQQZ128rm + 0U, // VCVTTPD2UQQZ128rmb + 0U, // VCVTTPD2UQQZ128rmbk + 0U, // VCVTTPD2UQQZ128rmbkz + 0U, // VCVTTPD2UQQZ128rmk + 0U, // VCVTTPD2UQQZ128rmkz + 0U, // VCVTTPD2UQQZ128rr + 0U, // VCVTTPD2UQQZ128rrk + 0U, // VCVTTPD2UQQZ128rrkz + 0U, // VCVTTPD2UQQZ256rm + 0U, // VCVTTPD2UQQZ256rmb + 0U, // VCVTTPD2UQQZ256rmbk + 0U, // VCVTTPD2UQQZ256rmbkz + 0U, // VCVTTPD2UQQZ256rmk + 0U, // VCVTTPD2UQQZ256rmkz + 0U, // VCVTTPD2UQQZ256rr + 0U, // VCVTTPD2UQQZ256rrk + 0U, // VCVTTPD2UQQZ256rrkz + 0U, // VCVTTPD2UQQZrm + 0U, // VCVTTPD2UQQZrmb + 0U, // VCVTTPD2UQQZrmbk + 0U, // VCVTTPD2UQQZrmbkz + 0U, // VCVTTPD2UQQZrmk + 0U, // VCVTTPD2UQQZrmkz + 0U, // VCVTTPD2UQQZrr + 0U, // VCVTTPD2UQQZrrb + 0U, // VCVTTPD2UQQZrrbk + 0U, // VCVTTPD2UQQZrrbkz + 0U, // VCVTTPD2UQQZrrk + 0U, // VCVTTPD2UQQZrrkz + 0U, // VCVTTPS2DQYrm + 0U, // VCVTTPS2DQYrr + 0U, // VCVTTPS2DQZ128rm + 0U, // VCVTTPS2DQZ128rmb + 0U, // VCVTTPS2DQZ128rmbk + 0U, // VCVTTPS2DQZ128rmbkz + 0U, // VCVTTPS2DQZ128rmk + 0U, // VCVTTPS2DQZ128rmkz + 0U, // VCVTTPS2DQZ128rr + 0U, // VCVTTPS2DQZ128rrk + 0U, // VCVTTPS2DQZ128rrkz + 0U, // VCVTTPS2DQZ256rm + 0U, // VCVTTPS2DQZ256rmb + 0U, // VCVTTPS2DQZ256rmbk + 0U, // VCVTTPS2DQZ256rmbkz + 0U, // VCVTTPS2DQZ256rmk + 0U, // VCVTTPS2DQZ256rmkz + 0U, // VCVTTPS2DQZ256rr + 0U, // VCVTTPS2DQZ256rrk + 0U, // VCVTTPS2DQZ256rrkz + 0U, // VCVTTPS2DQZrm + 0U, // VCVTTPS2DQZrmb + 0U, // VCVTTPS2DQZrmbk + 0U, // VCVTTPS2DQZrmbkz + 0U, // VCVTTPS2DQZrmk + 0U, // VCVTTPS2DQZrmkz + 0U, // VCVTTPS2DQZrr + 0U, // VCVTTPS2DQZrrb + 0U, // VCVTTPS2DQZrrbk + 0U, // VCVTTPS2DQZrrbkz + 0U, // VCVTTPS2DQZrrk + 0U, // VCVTTPS2DQZrrkz + 0U, // VCVTTPS2DQrm + 0U, // VCVTTPS2DQrr + 0U, // VCVTTPS2QQZ128rm + 0U, // VCVTTPS2QQZ128rmb + 0U, // VCVTTPS2QQZ128rmbk + 0U, // VCVTTPS2QQZ128rmbkz + 0U, // VCVTTPS2QQZ128rmk + 0U, // VCVTTPS2QQZ128rmkz + 0U, // VCVTTPS2QQZ128rr + 0U, // VCVTTPS2QQZ128rrk + 0U, // VCVTTPS2QQZ128rrkz + 0U, // VCVTTPS2QQZ256rm + 0U, // VCVTTPS2QQZ256rmb + 0U, // VCVTTPS2QQZ256rmbk + 0U, // VCVTTPS2QQZ256rmbkz + 0U, // VCVTTPS2QQZ256rmk + 0U, // VCVTTPS2QQZ256rmkz + 0U, // VCVTTPS2QQZ256rr + 0U, // VCVTTPS2QQZ256rrk + 0U, // VCVTTPS2QQZ256rrkz + 0U, // VCVTTPS2QQZrm + 0U, // VCVTTPS2QQZrmb + 0U, // VCVTTPS2QQZrmbk + 0U, // VCVTTPS2QQZrmbkz + 0U, // VCVTTPS2QQZrmk + 0U, // VCVTTPS2QQZrmkz + 0U, // VCVTTPS2QQZrr + 0U, // VCVTTPS2QQZrrb + 0U, // VCVTTPS2QQZrrbk + 0U, // VCVTTPS2QQZrrbkz + 0U, // VCVTTPS2QQZrrk + 0U, // VCVTTPS2QQZrrkz + 0U, // VCVTTPS2UDQZ128rm + 0U, // VCVTTPS2UDQZ128rmb + 0U, // VCVTTPS2UDQZ128rmbk + 0U, // VCVTTPS2UDQZ128rmbkz + 0U, // VCVTTPS2UDQZ128rmk + 0U, // VCVTTPS2UDQZ128rmkz + 0U, // VCVTTPS2UDQZ128rr + 0U, // VCVTTPS2UDQZ128rrk + 0U, // VCVTTPS2UDQZ128rrkz + 0U, // VCVTTPS2UDQZ256rm + 0U, // VCVTTPS2UDQZ256rmb + 0U, // VCVTTPS2UDQZ256rmbk + 0U, // VCVTTPS2UDQZ256rmbkz + 0U, // VCVTTPS2UDQZ256rmk + 0U, // VCVTTPS2UDQZ256rmkz + 0U, // VCVTTPS2UDQZ256rr + 0U, // VCVTTPS2UDQZ256rrk + 0U, // VCVTTPS2UDQZ256rrkz + 0U, // VCVTTPS2UDQZrm + 0U, // VCVTTPS2UDQZrmb + 0U, // VCVTTPS2UDQZrmbk + 0U, // VCVTTPS2UDQZrmbkz + 0U, // VCVTTPS2UDQZrmk + 0U, // VCVTTPS2UDQZrmkz + 0U, // VCVTTPS2UDQZrr + 0U, // VCVTTPS2UDQZrrb + 0U, // VCVTTPS2UDQZrrbk + 0U, // VCVTTPS2UDQZrrbkz + 0U, // VCVTTPS2UDQZrrk + 0U, // VCVTTPS2UDQZrrkz + 0U, // VCVTTPS2UQQZ128rm + 0U, // VCVTTPS2UQQZ128rmb + 0U, // VCVTTPS2UQQZ128rmbk + 0U, // VCVTTPS2UQQZ128rmbkz + 0U, // VCVTTPS2UQQZ128rmk + 0U, // VCVTTPS2UQQZ128rmkz + 0U, // VCVTTPS2UQQZ128rr + 0U, // VCVTTPS2UQQZ128rrk + 0U, // VCVTTPS2UQQZ128rrkz + 0U, // VCVTTPS2UQQZ256rm + 0U, // VCVTTPS2UQQZ256rmb + 0U, // VCVTTPS2UQQZ256rmbk + 0U, // VCVTTPS2UQQZ256rmbkz + 0U, // VCVTTPS2UQQZ256rmk + 0U, // VCVTTPS2UQQZ256rmkz + 0U, // VCVTTPS2UQQZ256rr + 0U, // VCVTTPS2UQQZ256rrk + 0U, // VCVTTPS2UQQZ256rrkz + 0U, // VCVTTPS2UQQZrm + 0U, // VCVTTPS2UQQZrmb + 0U, // VCVTTPS2UQQZrmbk + 0U, // VCVTTPS2UQQZrmbkz + 0U, // VCVTTPS2UQQZrmk + 0U, // VCVTTPS2UQQZrmkz + 0U, // VCVTTPS2UQQZrr + 0U, // VCVTTPS2UQQZrrb + 0U, // VCVTTPS2UQQZrrbk + 0U, // VCVTTPS2UQQZrrbkz + 0U, // VCVTTPS2UQQZrrk + 0U, // VCVTTPS2UQQZrrkz + 0U, // VCVTTSD2SI64Zrm + 0U, // VCVTTSD2SI64Zrm_Int + 0U, // VCVTTSD2SI64Zrr + 0U, // VCVTTSD2SI64Zrr_Int + 0U, // VCVTTSD2SI64Zrrb_Int + 0U, // VCVTTSD2SI64rm + 0U, // VCVTTSD2SI64rm_Int + 0U, // VCVTTSD2SI64rr + 0U, // VCVTTSD2SI64rr_Int + 0U, // VCVTTSD2SIZrm + 0U, // VCVTTSD2SIZrm_Int + 0U, // VCVTTSD2SIZrr + 0U, // VCVTTSD2SIZrr_Int + 0U, // VCVTTSD2SIZrrb_Int + 0U, // VCVTTSD2SIrm + 0U, // VCVTTSD2SIrm_Int + 0U, // VCVTTSD2SIrr + 0U, // VCVTTSD2SIrr_Int + 0U, // VCVTTSD2USI64Zrm + 0U, // VCVTTSD2USI64Zrm_Int + 0U, // VCVTTSD2USI64Zrr + 0U, // VCVTTSD2USI64Zrr_Int + 0U, // VCVTTSD2USI64Zrrb_Int + 0U, // VCVTTSD2USIZrm + 0U, // VCVTTSD2USIZrm_Int + 0U, // VCVTTSD2USIZrr + 0U, // VCVTTSD2USIZrr_Int + 0U, // VCVTTSD2USIZrrb_Int + 0U, // VCVTTSS2SI64Zrm + 0U, // VCVTTSS2SI64Zrm_Int + 0U, // VCVTTSS2SI64Zrr + 0U, // VCVTTSS2SI64Zrr_Int + 0U, // VCVTTSS2SI64Zrrb_Int + 0U, // VCVTTSS2SI64rm + 0U, // VCVTTSS2SI64rm_Int + 0U, // VCVTTSS2SI64rr + 0U, // VCVTTSS2SI64rr_Int + 0U, // VCVTTSS2SIZrm + 0U, // VCVTTSS2SIZrm_Int + 0U, // VCVTTSS2SIZrr + 0U, // VCVTTSS2SIZrr_Int + 0U, // VCVTTSS2SIZrrb_Int + 0U, // VCVTTSS2SIrm + 0U, // VCVTTSS2SIrm_Int + 0U, // VCVTTSS2SIrr + 0U, // VCVTTSS2SIrr_Int + 0U, // VCVTTSS2USI64Zrm + 0U, // VCVTTSS2USI64Zrm_Int + 0U, // VCVTTSS2USI64Zrr + 0U, // VCVTTSS2USI64Zrr_Int + 0U, // VCVTTSS2USI64Zrrb_Int + 0U, // VCVTTSS2USIZrm + 0U, // VCVTTSS2USIZrm_Int + 0U, // VCVTTSS2USIZrr + 0U, // VCVTTSS2USIZrr_Int + 0U, // VCVTTSS2USIZrrb_Int + 0U, // VCVTUDQ2PDZ128rm + 0U, // VCVTUDQ2PDZ128rmb + 0U, // VCVTUDQ2PDZ128rmbk + 0U, // VCVTUDQ2PDZ128rmbkz + 0U, // VCVTUDQ2PDZ128rmk + 0U, // VCVTUDQ2PDZ128rmkz + 0U, // VCVTUDQ2PDZ128rr + 0U, // VCVTUDQ2PDZ128rrk + 0U, // VCVTUDQ2PDZ128rrkz + 0U, // VCVTUDQ2PDZ256rm + 0U, // VCVTUDQ2PDZ256rmb + 0U, // VCVTUDQ2PDZ256rmbk + 0U, // VCVTUDQ2PDZ256rmbkz + 0U, // VCVTUDQ2PDZ256rmk + 0U, // VCVTUDQ2PDZ256rmkz + 0U, // VCVTUDQ2PDZ256rr + 0U, // VCVTUDQ2PDZ256rrk + 0U, // VCVTUDQ2PDZ256rrkz + 0U, // VCVTUDQ2PDZrm + 0U, // VCVTUDQ2PDZrmb + 0U, // VCVTUDQ2PDZrmbk + 0U, // VCVTUDQ2PDZrmbkz + 0U, // VCVTUDQ2PDZrmk + 0U, // VCVTUDQ2PDZrmkz + 0U, // VCVTUDQ2PDZrr + 0U, // VCVTUDQ2PDZrrk + 0U, // VCVTUDQ2PDZrrkz + 0U, // VCVTUDQ2PSZ128rm + 0U, // VCVTUDQ2PSZ128rmb + 0U, // VCVTUDQ2PSZ128rmbk + 0U, // VCVTUDQ2PSZ128rmbkz + 0U, // VCVTUDQ2PSZ128rmk + 0U, // VCVTUDQ2PSZ128rmkz + 0U, // VCVTUDQ2PSZ128rr + 0U, // VCVTUDQ2PSZ128rrk + 0U, // VCVTUDQ2PSZ128rrkz + 0U, // VCVTUDQ2PSZ256rm + 0U, // VCVTUDQ2PSZ256rmb + 0U, // VCVTUDQ2PSZ256rmbk + 0U, // VCVTUDQ2PSZ256rmbkz + 0U, // VCVTUDQ2PSZ256rmk + 0U, // VCVTUDQ2PSZ256rmkz + 0U, // VCVTUDQ2PSZ256rr + 0U, // VCVTUDQ2PSZ256rrk + 0U, // VCVTUDQ2PSZ256rrkz + 0U, // VCVTUDQ2PSZrm + 0U, // VCVTUDQ2PSZrmb + 0U, // VCVTUDQ2PSZrmbk + 0U, // VCVTUDQ2PSZrmbkz + 0U, // VCVTUDQ2PSZrmk + 0U, // VCVTUDQ2PSZrmkz + 0U, // VCVTUDQ2PSZrr + 0U, // VCVTUDQ2PSZrrb + 0U, // VCVTUDQ2PSZrrbk + 0U, // VCVTUDQ2PSZrrbkz + 0U, // VCVTUDQ2PSZrrk + 0U, // VCVTUDQ2PSZrrkz + 0U, // VCVTUQQ2PDZ128rm + 0U, // VCVTUQQ2PDZ128rmb + 0U, // VCVTUQQ2PDZ128rmbk + 0U, // VCVTUQQ2PDZ128rmbkz + 0U, // VCVTUQQ2PDZ128rmk + 0U, // VCVTUQQ2PDZ128rmkz + 0U, // VCVTUQQ2PDZ128rr + 0U, // VCVTUQQ2PDZ128rrk + 0U, // VCVTUQQ2PDZ128rrkz + 0U, // VCVTUQQ2PDZ256rm + 0U, // VCVTUQQ2PDZ256rmb + 0U, // VCVTUQQ2PDZ256rmbk + 0U, // VCVTUQQ2PDZ256rmbkz + 0U, // VCVTUQQ2PDZ256rmk + 0U, // VCVTUQQ2PDZ256rmkz + 0U, // VCVTUQQ2PDZ256rr + 0U, // VCVTUQQ2PDZ256rrk + 0U, // VCVTUQQ2PDZ256rrkz + 0U, // VCVTUQQ2PDZrm + 0U, // VCVTUQQ2PDZrmb + 0U, // VCVTUQQ2PDZrmbk + 0U, // VCVTUQQ2PDZrmbkz + 0U, // VCVTUQQ2PDZrmk + 0U, // VCVTUQQ2PDZrmkz + 0U, // VCVTUQQ2PDZrr + 0U, // VCVTUQQ2PDZrrb + 0U, // VCVTUQQ2PDZrrbk + 0U, // VCVTUQQ2PDZrrbkz + 0U, // VCVTUQQ2PDZrrk + 0U, // VCVTUQQ2PDZrrkz + 0U, // VCVTUQQ2PSZ128rm + 0U, // VCVTUQQ2PSZ128rmb + 0U, // VCVTUQQ2PSZ128rmbk + 0U, // VCVTUQQ2PSZ128rmbkz + 0U, // VCVTUQQ2PSZ128rmk + 0U, // VCVTUQQ2PSZ128rmkz + 0U, // VCVTUQQ2PSZ128rr + 0U, // VCVTUQQ2PSZ128rrk + 0U, // VCVTUQQ2PSZ128rrkz + 0U, // VCVTUQQ2PSZ256rm + 0U, // VCVTUQQ2PSZ256rmb + 0U, // VCVTUQQ2PSZ256rmbk + 0U, // VCVTUQQ2PSZ256rmbkz + 0U, // VCVTUQQ2PSZ256rmk + 0U, // VCVTUQQ2PSZ256rmkz + 0U, // VCVTUQQ2PSZ256rr + 0U, // VCVTUQQ2PSZ256rrk + 0U, // VCVTUQQ2PSZ256rrkz + 0U, // VCVTUQQ2PSZrm + 0U, // VCVTUQQ2PSZrmb + 0U, // VCVTUQQ2PSZrmbk + 0U, // VCVTUQQ2PSZrmbkz + 0U, // VCVTUQQ2PSZrmk + 0U, // VCVTUQQ2PSZrmkz + 0U, // VCVTUQQ2PSZrr + 0U, // VCVTUQQ2PSZrrb + 0U, // VCVTUQQ2PSZrrbk + 0U, // VCVTUQQ2PSZrrbkz + 0U, // VCVTUQQ2PSZrrk + 0U, // VCVTUQQ2PSZrrkz + 0U, // VCVTUSI2SDZrm + 0U, // VCVTUSI2SDZrm_Int + 0U, // VCVTUSI2SDZrr + 0U, // VCVTUSI2SDZrr_Int + 0U, // VCVTUSI2SSZrm + 0U, // VCVTUSI2SSZrm_Int + 0U, // VCVTUSI2SSZrr + 0U, // VCVTUSI2SSZrr_Int + 0U, // VCVTUSI2SSZrrb_Int + 0U, // VCVTUSI642SDZrm + 0U, // VCVTUSI642SDZrm_Int + 0U, // VCVTUSI642SDZrr + 0U, // VCVTUSI642SDZrr_Int + 0U, // VCVTUSI642SDZrrb_Int + 0U, // VCVTUSI642SSZrm + 0U, // VCVTUSI642SSZrm_Int + 0U, // VCVTUSI642SSZrr + 0U, // VCVTUSI642SSZrr_Int + 0U, // VCVTUSI642SSZrrb_Int + 0U, // VDBPSADBWZ128rmi + 0U, // VDBPSADBWZ128rmik + 0U, // VDBPSADBWZ128rmikz + 0U, // VDBPSADBWZ128rri + 0U, // VDBPSADBWZ128rrik + 3U, // VDBPSADBWZ128rrikz + 0U, // VDBPSADBWZ256rmi + 0U, // VDBPSADBWZ256rmik + 0U, // VDBPSADBWZ256rmikz + 0U, // VDBPSADBWZ256rri + 0U, // VDBPSADBWZ256rrik + 3U, // VDBPSADBWZ256rrikz + 0U, // VDBPSADBWZrmi + 0U, // VDBPSADBWZrmik + 0U, // VDBPSADBWZrmikz + 0U, // VDBPSADBWZrri + 0U, // VDBPSADBWZrrik + 3U, // VDBPSADBWZrrikz + 0U, // VDIVPDYrm + 0U, // VDIVPDYrr + 0U, // VDIVPDZ128rm + 0U, // VDIVPDZ128rmb + 0U, // VDIVPDZ128rmbk + 0U, // VDIVPDZ128rmbkz + 0U, // VDIVPDZ128rmk + 0U, // VDIVPDZ128rmkz + 0U, // VDIVPDZ128rr + 0U, // VDIVPDZ128rrk + 0U, // VDIVPDZ128rrkz + 0U, // VDIVPDZ256rm + 0U, // VDIVPDZ256rmb + 0U, // VDIVPDZ256rmbk + 0U, // VDIVPDZ256rmbkz + 0U, // VDIVPDZ256rmk + 0U, // VDIVPDZ256rmkz + 0U, // VDIVPDZ256rr + 0U, // VDIVPDZ256rrk + 0U, // VDIVPDZ256rrkz + 0U, // VDIVPDZrm + 0U, // VDIVPDZrmb + 0U, // VDIVPDZrmbk + 0U, // VDIVPDZrmbkz + 0U, // VDIVPDZrmk + 0U, // VDIVPDZrmkz + 0U, // VDIVPDZrr + 0U, // VDIVPDZrrb + 0U, // VDIVPDZrrbk + 0U, // VDIVPDZrrbkz + 0U, // VDIVPDZrrk + 0U, // VDIVPDZrrkz + 0U, // VDIVPDrm + 0U, // VDIVPDrr + 0U, // VDIVPSYrm + 0U, // VDIVPSYrr + 0U, // VDIVPSZ128rm + 0U, // VDIVPSZ128rmb + 0U, // VDIVPSZ128rmbk + 0U, // VDIVPSZ128rmbkz + 0U, // VDIVPSZ128rmk + 0U, // VDIVPSZ128rmkz + 0U, // VDIVPSZ128rr + 0U, // VDIVPSZ128rrk + 0U, // VDIVPSZ128rrkz + 0U, // VDIVPSZ256rm + 0U, // VDIVPSZ256rmb + 0U, // VDIVPSZ256rmbk + 0U, // VDIVPSZ256rmbkz + 0U, // VDIVPSZ256rmk + 0U, // VDIVPSZ256rmkz + 0U, // VDIVPSZ256rr + 0U, // VDIVPSZ256rrk + 0U, // VDIVPSZ256rrkz + 0U, // VDIVPSZrm + 0U, // VDIVPSZrmb + 0U, // VDIVPSZrmbk + 0U, // VDIVPSZrmbkz + 0U, // VDIVPSZrmk + 0U, // VDIVPSZrmkz + 0U, // VDIVPSZrr + 0U, // VDIVPSZrrb + 0U, // VDIVPSZrrbk + 0U, // VDIVPSZrrbkz + 0U, // VDIVPSZrrk + 0U, // VDIVPSZrrkz + 0U, // VDIVPSrm + 0U, // VDIVPSrr + 0U, // VDIVSDZrm + 0U, // VDIVSDZrm_Int + 0U, // VDIVSDZrm_Intk + 0U, // VDIVSDZrm_Intkz + 0U, // VDIVSDZrr + 0U, // VDIVSDZrr_Int + 0U, // VDIVSDZrr_Intk + 0U, // VDIVSDZrr_Intkz + 0U, // VDIVSDZrrb_Int + 0U, // VDIVSDZrrb_Intk + 0U, // VDIVSDZrrb_Intkz + 0U, // VDIVSDrm + 0U, // VDIVSDrm_Int + 0U, // VDIVSDrr + 0U, // VDIVSDrr_Int + 0U, // VDIVSSZrm + 0U, // VDIVSSZrm_Int + 0U, // VDIVSSZrm_Intk + 0U, // VDIVSSZrm_Intkz + 0U, // VDIVSSZrr + 0U, // VDIVSSZrr_Int + 0U, // VDIVSSZrr_Intk + 0U, // VDIVSSZrr_Intkz + 0U, // VDIVSSZrrb_Int + 0U, // VDIVSSZrrb_Intk + 0U, // VDIVSSZrrb_Intkz + 0U, // VDIVSSrm + 0U, // VDIVSSrm_Int + 0U, // VDIVSSrr + 0U, // VDIVSSrr_Int + 0U, // VDPPDrmi + 0U, // VDPPDrri + 0U, // VDPPSYrmi + 0U, // VDPPSYrri + 0U, // VDPPSrmi + 0U, // VDPPSrri + 0U, // VERRm + 0U, // VERRr + 0U, // VERWm + 0U, // VERWr + 0U, // VEXP2PDZm + 0U, // VEXP2PDZmb + 0U, // VEXP2PDZmbk + 0U, // VEXP2PDZmbkz + 0U, // VEXP2PDZmk + 0U, // VEXP2PDZmkz + 0U, // VEXP2PDZr + 0U, // VEXP2PDZrb + 0U, // VEXP2PDZrbk + 0U, // VEXP2PDZrbkz + 0U, // VEXP2PDZrk + 0U, // VEXP2PDZrkz + 0U, // VEXP2PSZm + 0U, // VEXP2PSZmb + 0U, // VEXP2PSZmbk + 0U, // VEXP2PSZmbkz + 0U, // VEXP2PSZmk + 0U, // VEXP2PSZmkz + 0U, // VEXP2PSZr + 0U, // VEXP2PSZrb + 0U, // VEXP2PSZrbk + 0U, // VEXP2PSZrbkz + 0U, // VEXP2PSZrk + 0U, // VEXP2PSZrkz + 0U, // VEXPANDPDZ128rm + 0U, // VEXPANDPDZ128rmk + 0U, // VEXPANDPDZ128rmkz + 0U, // VEXPANDPDZ128rr + 0U, // VEXPANDPDZ128rrk + 0U, // VEXPANDPDZ128rrkz + 0U, // VEXPANDPDZ256rm + 0U, // VEXPANDPDZ256rmk + 0U, // VEXPANDPDZ256rmkz + 0U, // VEXPANDPDZ256rr + 0U, // VEXPANDPDZ256rrk + 0U, // VEXPANDPDZ256rrkz + 0U, // VEXPANDPDZrm + 0U, // VEXPANDPDZrmk + 0U, // VEXPANDPDZrmkz + 0U, // VEXPANDPDZrr + 0U, // VEXPANDPDZrrk + 0U, // VEXPANDPDZrrkz + 0U, // VEXPANDPSZ128rm + 0U, // VEXPANDPSZ128rmk + 0U, // VEXPANDPSZ128rmkz + 0U, // VEXPANDPSZ128rr + 0U, // VEXPANDPSZ128rrk + 0U, // VEXPANDPSZ128rrkz + 0U, // VEXPANDPSZ256rm + 0U, // VEXPANDPSZ256rmk + 0U, // VEXPANDPSZ256rmkz + 0U, // VEXPANDPSZ256rr + 0U, // VEXPANDPSZ256rrk + 0U, // VEXPANDPSZ256rrkz + 0U, // VEXPANDPSZrm + 0U, // VEXPANDPSZrmk + 0U, // VEXPANDPSZrmkz + 0U, // VEXPANDPSZrr + 0U, // VEXPANDPSZrrk + 0U, // VEXPANDPSZrrkz + 0U, // VEXTRACTF128mr + 0U, // VEXTRACTF128rr + 0U, // VEXTRACTF32x4Z256mr + 0U, // VEXTRACTF32x4Z256mrk + 0U, // VEXTRACTF32x4Z256rr + 0U, // VEXTRACTF32x4Z256rrk + 0U, // VEXTRACTF32x4Z256rrkz + 0U, // VEXTRACTF32x4Zmr + 0U, // VEXTRACTF32x4Zmrk + 0U, // VEXTRACTF32x4Zrr + 0U, // VEXTRACTF32x4Zrrk + 0U, // VEXTRACTF32x4Zrrkz + 0U, // VEXTRACTF32x8Zmr + 0U, // VEXTRACTF32x8Zmrk + 0U, // VEXTRACTF32x8Zrr + 0U, // VEXTRACTF32x8Zrrk + 0U, // VEXTRACTF32x8Zrrkz + 0U, // VEXTRACTF64x2Z256mr + 0U, // VEXTRACTF64x2Z256mrk + 0U, // VEXTRACTF64x2Z256rr + 0U, // VEXTRACTF64x2Z256rrk + 0U, // VEXTRACTF64x2Z256rrkz + 0U, // VEXTRACTF64x2Zmr + 0U, // VEXTRACTF64x2Zmrk + 0U, // VEXTRACTF64x2Zrr + 0U, // VEXTRACTF64x2Zrrk + 0U, // VEXTRACTF64x2Zrrkz + 0U, // VEXTRACTF64x4Zmr + 0U, // VEXTRACTF64x4Zmrk + 0U, // VEXTRACTF64x4Zrr + 0U, // VEXTRACTF64x4Zrrk + 0U, // VEXTRACTF64x4Zrrkz + 0U, // VEXTRACTI128mr + 0U, // VEXTRACTI128rr + 0U, // VEXTRACTI32x4Z256mr + 0U, // VEXTRACTI32x4Z256mrk + 0U, // VEXTRACTI32x4Z256rr + 0U, // VEXTRACTI32x4Z256rrk + 0U, // VEXTRACTI32x4Z256rrkz + 0U, // VEXTRACTI32x4Zmr + 0U, // VEXTRACTI32x4Zmrk + 0U, // VEXTRACTI32x4Zrr + 0U, // VEXTRACTI32x4Zrrk + 0U, // VEXTRACTI32x4Zrrkz + 0U, // VEXTRACTI32x8Zmr + 0U, // VEXTRACTI32x8Zmrk + 0U, // VEXTRACTI32x8Zrr + 0U, // VEXTRACTI32x8Zrrk + 0U, // VEXTRACTI32x8Zrrkz + 0U, // VEXTRACTI64x2Z256mr + 0U, // VEXTRACTI64x2Z256mrk + 0U, // VEXTRACTI64x2Z256rr + 0U, // VEXTRACTI64x2Z256rrk + 0U, // VEXTRACTI64x2Z256rrkz + 0U, // VEXTRACTI64x2Zmr + 0U, // VEXTRACTI64x2Zmrk + 0U, // VEXTRACTI64x2Zrr + 0U, // VEXTRACTI64x2Zrrk + 0U, // VEXTRACTI64x2Zrrkz + 0U, // VEXTRACTI64x4Zmr + 0U, // VEXTRACTI64x4Zmrk + 0U, // VEXTRACTI64x4Zrr + 0U, // VEXTRACTI64x4Zrrk + 0U, // VEXTRACTI64x4Zrrkz + 0U, // VEXTRACTPSZmr + 0U, // VEXTRACTPSZrr + 0U, // VEXTRACTPSmr + 0U, // VEXTRACTPSrr + 0U, // VFIXUPIMMPDZ128rmbi + 0U, // VFIXUPIMMPDZ128rmbik + 2U, // VFIXUPIMMPDZ128rmbikz + 0U, // VFIXUPIMMPDZ128rmi + 0U, // VFIXUPIMMPDZ128rmik + 0U, // VFIXUPIMMPDZ128rmikz + 0U, // VFIXUPIMMPDZ128rri + 0U, // VFIXUPIMMPDZ128rrik + 0U, // VFIXUPIMMPDZ128rrikz + 0U, // VFIXUPIMMPDZ256rmbi + 0U, // VFIXUPIMMPDZ256rmbik + 2U, // VFIXUPIMMPDZ256rmbikz + 0U, // VFIXUPIMMPDZ256rmi + 0U, // VFIXUPIMMPDZ256rmik + 0U, // VFIXUPIMMPDZ256rmikz + 0U, // VFIXUPIMMPDZ256rri + 0U, // VFIXUPIMMPDZ256rrik + 0U, // VFIXUPIMMPDZ256rrikz + 0U, // VFIXUPIMMPDZrmbi + 0U, // VFIXUPIMMPDZrmbik + 2U, // VFIXUPIMMPDZrmbikz + 0U, // VFIXUPIMMPDZrmi + 0U, // VFIXUPIMMPDZrmik + 0U, // VFIXUPIMMPDZrmikz + 0U, // VFIXUPIMMPDZrri + 0U, // VFIXUPIMMPDZrrib + 0U, // VFIXUPIMMPDZrribk + 0U, // VFIXUPIMMPDZrribkz + 0U, // VFIXUPIMMPDZrrik + 0U, // VFIXUPIMMPDZrrikz + 0U, // VFIXUPIMMPSZ128rmbi + 0U, // VFIXUPIMMPSZ128rmbik + 2U, // VFIXUPIMMPSZ128rmbikz + 0U, // VFIXUPIMMPSZ128rmi + 0U, // VFIXUPIMMPSZ128rmik + 0U, // VFIXUPIMMPSZ128rmikz + 0U, // VFIXUPIMMPSZ128rri + 0U, // VFIXUPIMMPSZ128rrik + 0U, // VFIXUPIMMPSZ128rrikz + 0U, // VFIXUPIMMPSZ256rmbi + 0U, // VFIXUPIMMPSZ256rmbik + 2U, // VFIXUPIMMPSZ256rmbikz + 0U, // VFIXUPIMMPSZ256rmi + 0U, // VFIXUPIMMPSZ256rmik + 0U, // VFIXUPIMMPSZ256rmikz + 0U, // VFIXUPIMMPSZ256rri + 0U, // VFIXUPIMMPSZ256rrik + 0U, // VFIXUPIMMPSZ256rrikz + 0U, // VFIXUPIMMPSZrmbi + 0U, // VFIXUPIMMPSZrmbik + 2U, // VFIXUPIMMPSZrmbikz + 0U, // VFIXUPIMMPSZrmi + 0U, // VFIXUPIMMPSZrmik + 0U, // VFIXUPIMMPSZrmikz + 0U, // VFIXUPIMMPSZrri + 0U, // VFIXUPIMMPSZrrib + 0U, // VFIXUPIMMPSZrribk + 0U, // VFIXUPIMMPSZrribkz + 0U, // VFIXUPIMMPSZrrik + 0U, // VFIXUPIMMPSZrrikz + 0U, // VFIXUPIMMSDZrmi + 0U, // VFIXUPIMMSDZrmik + 2U, // VFIXUPIMMSDZrmikz + 0U, // VFIXUPIMMSDZrri + 0U, // VFIXUPIMMSDZrrib + 0U, // VFIXUPIMMSDZrribk + 0U, // VFIXUPIMMSDZrribkz + 0U, // VFIXUPIMMSDZrrik + 0U, // VFIXUPIMMSDZrrikz + 0U, // VFIXUPIMMSSZrmi + 0U, // VFIXUPIMMSSZrmik + 2U, // VFIXUPIMMSSZrmikz + 0U, // VFIXUPIMMSSZrri + 0U, // VFIXUPIMMSSZrrib + 0U, // VFIXUPIMMSSZrribk + 0U, // VFIXUPIMMSSZrribkz + 0U, // VFIXUPIMMSSZrrik + 0U, // VFIXUPIMMSSZrrikz + 0U, // VFMADD132PDYm + 0U, // VFMADD132PDYr + 0U, // VFMADD132PDZ128m + 0U, // VFMADD132PDZ128mb + 0U, // VFMADD132PDZ128mbk + 0U, // VFMADD132PDZ128mbkz + 0U, // VFMADD132PDZ128mk + 0U, // VFMADD132PDZ128mkz + 0U, // VFMADD132PDZ128r + 0U, // VFMADD132PDZ128rk + 0U, // VFMADD132PDZ128rkz + 0U, // VFMADD132PDZ256m + 0U, // VFMADD132PDZ256mb + 0U, // VFMADD132PDZ256mbk + 0U, // VFMADD132PDZ256mbkz + 0U, // VFMADD132PDZ256mk + 0U, // VFMADD132PDZ256mkz + 0U, // VFMADD132PDZ256r + 0U, // VFMADD132PDZ256rk + 0U, // VFMADD132PDZ256rkz + 0U, // VFMADD132PDZm + 0U, // VFMADD132PDZmb + 0U, // VFMADD132PDZmbk + 0U, // VFMADD132PDZmbkz + 0U, // VFMADD132PDZmk + 0U, // VFMADD132PDZmkz + 0U, // VFMADD132PDZr + 0U, // VFMADD132PDZrb + 0U, // VFMADD132PDZrbk + 0U, // VFMADD132PDZrbkz + 0U, // VFMADD132PDZrk + 0U, // VFMADD132PDZrkz + 0U, // VFMADD132PDm + 0U, // VFMADD132PDr + 0U, // VFMADD132PSYm + 0U, // VFMADD132PSYr + 0U, // VFMADD132PSZ128m + 0U, // VFMADD132PSZ128mb + 0U, // VFMADD132PSZ128mbk + 0U, // VFMADD132PSZ128mbkz + 0U, // VFMADD132PSZ128mk + 0U, // VFMADD132PSZ128mkz + 0U, // VFMADD132PSZ128r + 0U, // VFMADD132PSZ128rk + 0U, // VFMADD132PSZ128rkz + 0U, // VFMADD132PSZ256m + 0U, // VFMADD132PSZ256mb + 0U, // VFMADD132PSZ256mbk + 0U, // VFMADD132PSZ256mbkz + 0U, // VFMADD132PSZ256mk + 0U, // VFMADD132PSZ256mkz + 0U, // VFMADD132PSZ256r + 0U, // VFMADD132PSZ256rk + 0U, // VFMADD132PSZ256rkz + 0U, // VFMADD132PSZm + 0U, // VFMADD132PSZmb + 0U, // VFMADD132PSZmbk + 0U, // VFMADD132PSZmbkz + 0U, // VFMADD132PSZmk + 0U, // VFMADD132PSZmkz + 0U, // VFMADD132PSZr + 0U, // VFMADD132PSZrb + 0U, // VFMADD132PSZrbk + 0U, // VFMADD132PSZrbkz + 0U, // VFMADD132PSZrk + 0U, // VFMADD132PSZrkz + 0U, // VFMADD132PSm + 0U, // VFMADD132PSr + 0U, // VFMADD132SDZm + 0U, // VFMADD132SDZm_Int + 0U, // VFMADD132SDZm_Intk + 0U, // VFMADD132SDZm_Intkz + 0U, // VFMADD132SDZr + 0U, // VFMADD132SDZr_Int + 0U, // VFMADD132SDZr_Intk + 0U, // VFMADD132SDZr_Intkz + 0U, // VFMADD132SDZrb + 0U, // VFMADD132SDZrb_Int + 0U, // VFMADD132SDZrb_Intk + 0U, // VFMADD132SDZrb_Intkz + 0U, // VFMADD132SDm + 0U, // VFMADD132SDm_Int + 0U, // VFMADD132SDr + 0U, // VFMADD132SDr_Int + 0U, // VFMADD132SSZm + 0U, // VFMADD132SSZm_Int + 0U, // VFMADD132SSZm_Intk + 0U, // VFMADD132SSZm_Intkz + 0U, // VFMADD132SSZr + 0U, // VFMADD132SSZr_Int + 0U, // VFMADD132SSZr_Intk + 0U, // VFMADD132SSZr_Intkz + 0U, // VFMADD132SSZrb + 0U, // VFMADD132SSZrb_Int + 0U, // VFMADD132SSZrb_Intk + 0U, // VFMADD132SSZrb_Intkz + 0U, // VFMADD132SSm + 0U, // VFMADD132SSm_Int + 0U, // VFMADD132SSr + 0U, // VFMADD132SSr_Int + 0U, // VFMADD213PDYm + 0U, // VFMADD213PDYr + 0U, // VFMADD213PDZ128m + 0U, // VFMADD213PDZ128mb + 0U, // VFMADD213PDZ128mbk + 0U, // VFMADD213PDZ128mbkz + 0U, // VFMADD213PDZ128mk + 0U, // VFMADD213PDZ128mkz + 0U, // VFMADD213PDZ128r + 0U, // VFMADD213PDZ128rk + 0U, // VFMADD213PDZ128rkz + 0U, // VFMADD213PDZ256m + 0U, // VFMADD213PDZ256mb + 0U, // VFMADD213PDZ256mbk + 0U, // VFMADD213PDZ256mbkz + 0U, // VFMADD213PDZ256mk + 0U, // VFMADD213PDZ256mkz + 0U, // VFMADD213PDZ256r + 0U, // VFMADD213PDZ256rk + 0U, // VFMADD213PDZ256rkz + 0U, // VFMADD213PDZm + 0U, // VFMADD213PDZmb + 0U, // VFMADD213PDZmbk + 0U, // VFMADD213PDZmbkz + 0U, // VFMADD213PDZmk + 0U, // VFMADD213PDZmkz + 0U, // VFMADD213PDZr + 0U, // VFMADD213PDZrb + 0U, // VFMADD213PDZrbk + 0U, // VFMADD213PDZrbkz + 0U, // VFMADD213PDZrk + 0U, // VFMADD213PDZrkz + 0U, // VFMADD213PDm + 0U, // VFMADD213PDr + 0U, // VFMADD213PSYm + 0U, // VFMADD213PSYr + 0U, // VFMADD213PSZ128m + 0U, // VFMADD213PSZ128mb + 0U, // VFMADD213PSZ128mbk + 0U, // VFMADD213PSZ128mbkz + 0U, // VFMADD213PSZ128mk + 0U, // VFMADD213PSZ128mkz + 0U, // VFMADD213PSZ128r + 0U, // VFMADD213PSZ128rk + 0U, // VFMADD213PSZ128rkz + 0U, // VFMADD213PSZ256m + 0U, // VFMADD213PSZ256mb + 0U, // VFMADD213PSZ256mbk + 0U, // VFMADD213PSZ256mbkz + 0U, // VFMADD213PSZ256mk + 0U, // VFMADD213PSZ256mkz + 0U, // VFMADD213PSZ256r + 0U, // VFMADD213PSZ256rk + 0U, // VFMADD213PSZ256rkz + 0U, // VFMADD213PSZm + 0U, // VFMADD213PSZmb + 0U, // VFMADD213PSZmbk + 0U, // VFMADD213PSZmbkz + 0U, // VFMADD213PSZmk + 0U, // VFMADD213PSZmkz + 0U, // VFMADD213PSZr + 0U, // VFMADD213PSZrb + 0U, // VFMADD213PSZrbk + 0U, // VFMADD213PSZrbkz + 0U, // VFMADD213PSZrk + 0U, // VFMADD213PSZrkz + 0U, // VFMADD213PSm + 0U, // VFMADD213PSr + 0U, // VFMADD213SDZm + 0U, // VFMADD213SDZm_Int + 0U, // VFMADD213SDZm_Intk + 0U, // VFMADD213SDZm_Intkz + 0U, // VFMADD213SDZr + 0U, // VFMADD213SDZr_Int + 0U, // VFMADD213SDZr_Intk + 0U, // VFMADD213SDZr_Intkz + 0U, // VFMADD213SDZrb + 0U, // VFMADD213SDZrb_Int + 0U, // VFMADD213SDZrb_Intk + 0U, // VFMADD213SDZrb_Intkz + 0U, // VFMADD213SDm + 0U, // VFMADD213SDm_Int + 0U, // VFMADD213SDr + 0U, // VFMADD213SDr_Int + 0U, // VFMADD213SSZm + 0U, // VFMADD213SSZm_Int + 0U, // VFMADD213SSZm_Intk + 0U, // VFMADD213SSZm_Intkz + 0U, // VFMADD213SSZr + 0U, // VFMADD213SSZr_Int + 0U, // VFMADD213SSZr_Intk + 0U, // VFMADD213SSZr_Intkz + 0U, // VFMADD213SSZrb + 0U, // VFMADD213SSZrb_Int + 0U, // VFMADD213SSZrb_Intk + 0U, // VFMADD213SSZrb_Intkz + 0U, // VFMADD213SSm + 0U, // VFMADD213SSm_Int + 0U, // VFMADD213SSr + 0U, // VFMADD213SSr_Int + 0U, // VFMADD231PDYm + 0U, // VFMADD231PDYr + 0U, // VFMADD231PDZ128m + 0U, // VFMADD231PDZ128mb + 0U, // VFMADD231PDZ128mbk + 0U, // VFMADD231PDZ128mbkz + 0U, // VFMADD231PDZ128mk + 0U, // VFMADD231PDZ128mkz + 0U, // VFMADD231PDZ128r + 0U, // VFMADD231PDZ128rk + 0U, // VFMADD231PDZ128rkz + 0U, // VFMADD231PDZ256m + 0U, // VFMADD231PDZ256mb + 0U, // VFMADD231PDZ256mbk + 0U, // VFMADD231PDZ256mbkz + 0U, // VFMADD231PDZ256mk + 0U, // VFMADD231PDZ256mkz + 0U, // VFMADD231PDZ256r + 0U, // VFMADD231PDZ256rk + 0U, // VFMADD231PDZ256rkz + 0U, // VFMADD231PDZm + 0U, // VFMADD231PDZmb + 0U, // VFMADD231PDZmbk + 0U, // VFMADD231PDZmbkz + 0U, // VFMADD231PDZmk + 0U, // VFMADD231PDZmkz + 0U, // VFMADD231PDZr + 0U, // VFMADD231PDZrb + 0U, // VFMADD231PDZrbk + 0U, // VFMADD231PDZrbkz + 0U, // VFMADD231PDZrk + 0U, // VFMADD231PDZrkz + 0U, // VFMADD231PDm + 0U, // VFMADD231PDr + 0U, // VFMADD231PSYm + 0U, // VFMADD231PSYr + 0U, // VFMADD231PSZ128m + 0U, // VFMADD231PSZ128mb + 0U, // VFMADD231PSZ128mbk + 0U, // VFMADD231PSZ128mbkz + 0U, // VFMADD231PSZ128mk + 0U, // VFMADD231PSZ128mkz + 0U, // VFMADD231PSZ128r + 0U, // VFMADD231PSZ128rk + 0U, // VFMADD231PSZ128rkz + 0U, // VFMADD231PSZ256m + 0U, // VFMADD231PSZ256mb + 0U, // VFMADD231PSZ256mbk + 0U, // VFMADD231PSZ256mbkz + 0U, // VFMADD231PSZ256mk + 0U, // VFMADD231PSZ256mkz + 0U, // VFMADD231PSZ256r + 0U, // VFMADD231PSZ256rk + 0U, // VFMADD231PSZ256rkz + 0U, // VFMADD231PSZm + 0U, // VFMADD231PSZmb + 0U, // VFMADD231PSZmbk + 0U, // VFMADD231PSZmbkz + 0U, // VFMADD231PSZmk + 0U, // VFMADD231PSZmkz + 0U, // VFMADD231PSZr + 0U, // VFMADD231PSZrb + 0U, // VFMADD231PSZrbk + 0U, // VFMADD231PSZrbkz + 0U, // VFMADD231PSZrk + 0U, // VFMADD231PSZrkz + 0U, // VFMADD231PSm + 0U, // VFMADD231PSr + 0U, // VFMADD231SDZm + 0U, // VFMADD231SDZm_Int + 0U, // VFMADD231SDZm_Intk + 0U, // VFMADD231SDZm_Intkz + 0U, // VFMADD231SDZr + 0U, // VFMADD231SDZr_Int + 0U, // VFMADD231SDZr_Intk + 0U, // VFMADD231SDZr_Intkz + 0U, // VFMADD231SDZrb + 0U, // VFMADD231SDZrb_Int + 0U, // VFMADD231SDZrb_Intk + 0U, // VFMADD231SDZrb_Intkz + 0U, // VFMADD231SDm + 0U, // VFMADD231SDm_Int + 0U, // VFMADD231SDr + 0U, // VFMADD231SDr_Int + 0U, // VFMADD231SSZm + 0U, // VFMADD231SSZm_Int + 0U, // VFMADD231SSZm_Intk + 0U, // VFMADD231SSZm_Intkz + 0U, // VFMADD231SSZr + 0U, // VFMADD231SSZr_Int + 0U, // VFMADD231SSZr_Intk + 0U, // VFMADD231SSZr_Intkz + 0U, // VFMADD231SSZrb + 0U, // VFMADD231SSZrb_Int + 0U, // VFMADD231SSZrb_Intk + 0U, // VFMADD231SSZrb_Intkz + 0U, // VFMADD231SSm + 0U, // VFMADD231SSm_Int + 0U, // VFMADD231SSr + 0U, // VFMADD231SSr_Int + 0U, // VFMADDPD4Ymr + 0U, // VFMADDPD4Yrm + 0U, // VFMADDPD4Yrr + 0U, // VFMADDPD4Yrr_REV + 0U, // VFMADDPD4mr + 0U, // VFMADDPD4rm + 0U, // VFMADDPD4rr + 0U, // VFMADDPD4rr_REV + 0U, // VFMADDPS4Ymr + 0U, // VFMADDPS4Yrm + 0U, // VFMADDPS4Yrr + 0U, // VFMADDPS4Yrr_REV + 0U, // VFMADDPS4mr + 0U, // VFMADDPS4rm + 0U, // VFMADDPS4rr + 0U, // VFMADDPS4rr_REV + 0U, // VFMADDSD4mr + 0U, // VFMADDSD4mr_Int + 0U, // VFMADDSD4rm + 0U, // VFMADDSD4rm_Int + 0U, // VFMADDSD4rr + 0U, // VFMADDSD4rr_Int + 0U, // VFMADDSD4rr_Int_REV + 0U, // VFMADDSD4rr_REV + 0U, // VFMADDSS4mr + 0U, // VFMADDSS4mr_Int + 0U, // VFMADDSS4rm + 0U, // VFMADDSS4rm_Int + 0U, // VFMADDSS4rr + 0U, // VFMADDSS4rr_Int + 0U, // VFMADDSS4rr_Int_REV + 0U, // VFMADDSS4rr_REV + 0U, // VFMADDSUB132PDYm + 0U, // VFMADDSUB132PDYr + 0U, // VFMADDSUB132PDZ128m + 0U, // VFMADDSUB132PDZ128mb + 0U, // VFMADDSUB132PDZ128mbk + 0U, // VFMADDSUB132PDZ128mbkz + 0U, // VFMADDSUB132PDZ128mk + 0U, // VFMADDSUB132PDZ128mkz + 0U, // VFMADDSUB132PDZ128r + 0U, // VFMADDSUB132PDZ128rk + 0U, // VFMADDSUB132PDZ128rkz + 0U, // VFMADDSUB132PDZ256m + 0U, // VFMADDSUB132PDZ256mb + 0U, // VFMADDSUB132PDZ256mbk + 0U, // VFMADDSUB132PDZ256mbkz + 0U, // VFMADDSUB132PDZ256mk + 0U, // VFMADDSUB132PDZ256mkz + 0U, // VFMADDSUB132PDZ256r + 0U, // VFMADDSUB132PDZ256rk + 0U, // VFMADDSUB132PDZ256rkz + 0U, // VFMADDSUB132PDZm + 0U, // VFMADDSUB132PDZmb + 0U, // VFMADDSUB132PDZmbk + 0U, // VFMADDSUB132PDZmbkz + 0U, // VFMADDSUB132PDZmk + 0U, // VFMADDSUB132PDZmkz + 0U, // VFMADDSUB132PDZr + 0U, // VFMADDSUB132PDZrb + 0U, // VFMADDSUB132PDZrbk + 0U, // VFMADDSUB132PDZrbkz + 0U, // VFMADDSUB132PDZrk + 0U, // VFMADDSUB132PDZrkz + 0U, // VFMADDSUB132PDm + 0U, // VFMADDSUB132PDr + 0U, // VFMADDSUB132PSYm + 0U, // VFMADDSUB132PSYr + 0U, // VFMADDSUB132PSZ128m + 0U, // VFMADDSUB132PSZ128mb + 0U, // VFMADDSUB132PSZ128mbk + 0U, // VFMADDSUB132PSZ128mbkz + 0U, // VFMADDSUB132PSZ128mk + 0U, // VFMADDSUB132PSZ128mkz + 0U, // VFMADDSUB132PSZ128r + 0U, // VFMADDSUB132PSZ128rk + 0U, // VFMADDSUB132PSZ128rkz + 0U, // VFMADDSUB132PSZ256m + 0U, // VFMADDSUB132PSZ256mb + 0U, // VFMADDSUB132PSZ256mbk + 0U, // VFMADDSUB132PSZ256mbkz + 0U, // VFMADDSUB132PSZ256mk + 0U, // VFMADDSUB132PSZ256mkz + 0U, // VFMADDSUB132PSZ256r + 0U, // VFMADDSUB132PSZ256rk + 0U, // VFMADDSUB132PSZ256rkz + 0U, // VFMADDSUB132PSZm + 0U, // VFMADDSUB132PSZmb + 0U, // VFMADDSUB132PSZmbk + 0U, // VFMADDSUB132PSZmbkz + 0U, // VFMADDSUB132PSZmk + 0U, // VFMADDSUB132PSZmkz + 0U, // VFMADDSUB132PSZr + 0U, // VFMADDSUB132PSZrb + 0U, // VFMADDSUB132PSZrbk + 0U, // VFMADDSUB132PSZrbkz + 0U, // VFMADDSUB132PSZrk + 0U, // VFMADDSUB132PSZrkz + 0U, // VFMADDSUB132PSm + 0U, // VFMADDSUB132PSr + 0U, // VFMADDSUB213PDYm + 0U, // VFMADDSUB213PDYr + 0U, // VFMADDSUB213PDZ128m + 0U, // VFMADDSUB213PDZ128mb + 0U, // VFMADDSUB213PDZ128mbk + 0U, // VFMADDSUB213PDZ128mbkz + 0U, // VFMADDSUB213PDZ128mk + 0U, // VFMADDSUB213PDZ128mkz + 0U, // VFMADDSUB213PDZ128r + 0U, // VFMADDSUB213PDZ128rk + 0U, // VFMADDSUB213PDZ128rkz + 0U, // VFMADDSUB213PDZ256m + 0U, // VFMADDSUB213PDZ256mb + 0U, // VFMADDSUB213PDZ256mbk + 0U, // VFMADDSUB213PDZ256mbkz + 0U, // VFMADDSUB213PDZ256mk + 0U, // VFMADDSUB213PDZ256mkz + 0U, // VFMADDSUB213PDZ256r + 0U, // VFMADDSUB213PDZ256rk + 0U, // VFMADDSUB213PDZ256rkz + 0U, // VFMADDSUB213PDZm + 0U, // VFMADDSUB213PDZmb + 0U, // VFMADDSUB213PDZmbk + 0U, // VFMADDSUB213PDZmbkz + 0U, // VFMADDSUB213PDZmk + 0U, // VFMADDSUB213PDZmkz + 0U, // VFMADDSUB213PDZr + 0U, // VFMADDSUB213PDZrb + 0U, // VFMADDSUB213PDZrbk + 0U, // VFMADDSUB213PDZrbkz + 0U, // VFMADDSUB213PDZrk + 0U, // VFMADDSUB213PDZrkz + 0U, // VFMADDSUB213PDm + 0U, // VFMADDSUB213PDr + 0U, // VFMADDSUB213PSYm + 0U, // VFMADDSUB213PSYr + 0U, // VFMADDSUB213PSZ128m + 0U, // VFMADDSUB213PSZ128mb + 0U, // VFMADDSUB213PSZ128mbk + 0U, // VFMADDSUB213PSZ128mbkz + 0U, // VFMADDSUB213PSZ128mk + 0U, // VFMADDSUB213PSZ128mkz + 0U, // VFMADDSUB213PSZ128r + 0U, // VFMADDSUB213PSZ128rk + 0U, // VFMADDSUB213PSZ128rkz + 0U, // VFMADDSUB213PSZ256m + 0U, // VFMADDSUB213PSZ256mb + 0U, // VFMADDSUB213PSZ256mbk + 0U, // VFMADDSUB213PSZ256mbkz + 0U, // VFMADDSUB213PSZ256mk + 0U, // VFMADDSUB213PSZ256mkz + 0U, // VFMADDSUB213PSZ256r + 0U, // VFMADDSUB213PSZ256rk + 0U, // VFMADDSUB213PSZ256rkz + 0U, // VFMADDSUB213PSZm + 0U, // VFMADDSUB213PSZmb + 0U, // VFMADDSUB213PSZmbk + 0U, // VFMADDSUB213PSZmbkz + 0U, // VFMADDSUB213PSZmk + 0U, // VFMADDSUB213PSZmkz + 0U, // VFMADDSUB213PSZr + 0U, // VFMADDSUB213PSZrb + 0U, // VFMADDSUB213PSZrbk + 0U, // VFMADDSUB213PSZrbkz + 0U, // VFMADDSUB213PSZrk + 0U, // VFMADDSUB213PSZrkz + 0U, // VFMADDSUB213PSm + 0U, // VFMADDSUB213PSr + 0U, // VFMADDSUB231PDYm + 0U, // VFMADDSUB231PDYr + 0U, // VFMADDSUB231PDZ128m + 0U, // VFMADDSUB231PDZ128mb + 0U, // VFMADDSUB231PDZ128mbk + 0U, // VFMADDSUB231PDZ128mbkz + 0U, // VFMADDSUB231PDZ128mk + 0U, // VFMADDSUB231PDZ128mkz + 0U, // VFMADDSUB231PDZ128r + 0U, // VFMADDSUB231PDZ128rk + 0U, // VFMADDSUB231PDZ128rkz + 0U, // VFMADDSUB231PDZ256m + 0U, // VFMADDSUB231PDZ256mb + 0U, // VFMADDSUB231PDZ256mbk + 0U, // VFMADDSUB231PDZ256mbkz + 0U, // VFMADDSUB231PDZ256mk + 0U, // VFMADDSUB231PDZ256mkz + 0U, // VFMADDSUB231PDZ256r + 0U, // VFMADDSUB231PDZ256rk + 0U, // VFMADDSUB231PDZ256rkz + 0U, // VFMADDSUB231PDZm + 0U, // VFMADDSUB231PDZmb + 0U, // VFMADDSUB231PDZmbk + 0U, // VFMADDSUB231PDZmbkz + 0U, // VFMADDSUB231PDZmk + 0U, // VFMADDSUB231PDZmkz + 0U, // VFMADDSUB231PDZr + 0U, // VFMADDSUB231PDZrb + 0U, // VFMADDSUB231PDZrbk + 0U, // VFMADDSUB231PDZrbkz + 0U, // VFMADDSUB231PDZrk + 0U, // VFMADDSUB231PDZrkz + 0U, // VFMADDSUB231PDm + 0U, // VFMADDSUB231PDr + 0U, // VFMADDSUB231PSYm + 0U, // VFMADDSUB231PSYr + 0U, // VFMADDSUB231PSZ128m + 0U, // VFMADDSUB231PSZ128mb + 0U, // VFMADDSUB231PSZ128mbk + 0U, // VFMADDSUB231PSZ128mbkz + 0U, // VFMADDSUB231PSZ128mk + 0U, // VFMADDSUB231PSZ128mkz + 0U, // VFMADDSUB231PSZ128r + 0U, // VFMADDSUB231PSZ128rk + 0U, // VFMADDSUB231PSZ128rkz + 0U, // VFMADDSUB231PSZ256m + 0U, // VFMADDSUB231PSZ256mb + 0U, // VFMADDSUB231PSZ256mbk + 0U, // VFMADDSUB231PSZ256mbkz + 0U, // VFMADDSUB231PSZ256mk + 0U, // VFMADDSUB231PSZ256mkz + 0U, // VFMADDSUB231PSZ256r + 0U, // VFMADDSUB231PSZ256rk + 0U, // VFMADDSUB231PSZ256rkz + 0U, // VFMADDSUB231PSZm + 0U, // VFMADDSUB231PSZmb + 0U, // VFMADDSUB231PSZmbk + 0U, // VFMADDSUB231PSZmbkz + 0U, // VFMADDSUB231PSZmk + 0U, // VFMADDSUB231PSZmkz + 0U, // VFMADDSUB231PSZr + 0U, // VFMADDSUB231PSZrb + 0U, // VFMADDSUB231PSZrbk + 0U, // VFMADDSUB231PSZrbkz + 0U, // VFMADDSUB231PSZrk + 0U, // VFMADDSUB231PSZrkz + 0U, // VFMADDSUB231PSm + 0U, // VFMADDSUB231PSr + 0U, // VFMADDSUBPD4Ymr + 0U, // VFMADDSUBPD4Yrm + 0U, // VFMADDSUBPD4Yrr + 0U, // VFMADDSUBPD4Yrr_REV + 0U, // VFMADDSUBPD4mr + 0U, // VFMADDSUBPD4rm + 0U, // VFMADDSUBPD4rr + 0U, // VFMADDSUBPD4rr_REV + 0U, // VFMADDSUBPS4Ymr + 0U, // VFMADDSUBPS4Yrm + 0U, // VFMADDSUBPS4Yrr + 0U, // VFMADDSUBPS4Yrr_REV + 0U, // VFMADDSUBPS4mr + 0U, // VFMADDSUBPS4rm + 0U, // VFMADDSUBPS4rr + 0U, // VFMADDSUBPS4rr_REV + 0U, // VFMSUB132PDYm + 0U, // VFMSUB132PDYr + 0U, // VFMSUB132PDZ128m + 0U, // VFMSUB132PDZ128mb + 0U, // VFMSUB132PDZ128mbk + 0U, // VFMSUB132PDZ128mbkz + 0U, // VFMSUB132PDZ128mk + 0U, // VFMSUB132PDZ128mkz + 0U, // VFMSUB132PDZ128r + 0U, // VFMSUB132PDZ128rk + 0U, // VFMSUB132PDZ128rkz + 0U, // VFMSUB132PDZ256m + 0U, // VFMSUB132PDZ256mb + 0U, // VFMSUB132PDZ256mbk + 0U, // VFMSUB132PDZ256mbkz + 0U, // VFMSUB132PDZ256mk + 0U, // VFMSUB132PDZ256mkz + 0U, // VFMSUB132PDZ256r + 0U, // VFMSUB132PDZ256rk + 0U, // VFMSUB132PDZ256rkz + 0U, // VFMSUB132PDZm + 0U, // VFMSUB132PDZmb + 0U, // VFMSUB132PDZmbk + 0U, // VFMSUB132PDZmbkz + 0U, // VFMSUB132PDZmk + 0U, // VFMSUB132PDZmkz + 0U, // VFMSUB132PDZr + 0U, // VFMSUB132PDZrb + 0U, // VFMSUB132PDZrbk + 0U, // VFMSUB132PDZrbkz + 0U, // VFMSUB132PDZrk + 0U, // VFMSUB132PDZrkz + 0U, // VFMSUB132PDm + 0U, // VFMSUB132PDr + 0U, // VFMSUB132PSYm + 0U, // VFMSUB132PSYr + 0U, // VFMSUB132PSZ128m + 0U, // VFMSUB132PSZ128mb + 0U, // VFMSUB132PSZ128mbk + 0U, // VFMSUB132PSZ128mbkz + 0U, // VFMSUB132PSZ128mk + 0U, // VFMSUB132PSZ128mkz + 0U, // VFMSUB132PSZ128r + 0U, // VFMSUB132PSZ128rk + 0U, // VFMSUB132PSZ128rkz + 0U, // VFMSUB132PSZ256m + 0U, // VFMSUB132PSZ256mb + 0U, // VFMSUB132PSZ256mbk + 0U, // VFMSUB132PSZ256mbkz + 0U, // VFMSUB132PSZ256mk + 0U, // VFMSUB132PSZ256mkz + 0U, // VFMSUB132PSZ256r + 0U, // VFMSUB132PSZ256rk + 0U, // VFMSUB132PSZ256rkz + 0U, // VFMSUB132PSZm + 0U, // VFMSUB132PSZmb + 0U, // VFMSUB132PSZmbk + 0U, // VFMSUB132PSZmbkz + 0U, // VFMSUB132PSZmk + 0U, // VFMSUB132PSZmkz + 0U, // VFMSUB132PSZr + 0U, // VFMSUB132PSZrb + 0U, // VFMSUB132PSZrbk + 0U, // VFMSUB132PSZrbkz + 0U, // VFMSUB132PSZrk + 0U, // VFMSUB132PSZrkz + 0U, // VFMSUB132PSm + 0U, // VFMSUB132PSr + 0U, // VFMSUB132SDZm + 0U, // VFMSUB132SDZm_Int + 0U, // VFMSUB132SDZm_Intk + 0U, // VFMSUB132SDZm_Intkz + 0U, // VFMSUB132SDZr + 0U, // VFMSUB132SDZr_Int + 0U, // VFMSUB132SDZr_Intk + 0U, // VFMSUB132SDZr_Intkz + 0U, // VFMSUB132SDZrb + 0U, // VFMSUB132SDZrb_Int + 0U, // VFMSUB132SDZrb_Intk + 0U, // VFMSUB132SDZrb_Intkz + 0U, // VFMSUB132SDm + 0U, // VFMSUB132SDm_Int + 0U, // VFMSUB132SDr + 0U, // VFMSUB132SDr_Int + 0U, // VFMSUB132SSZm + 0U, // VFMSUB132SSZm_Int + 0U, // VFMSUB132SSZm_Intk + 0U, // VFMSUB132SSZm_Intkz + 0U, // VFMSUB132SSZr + 0U, // VFMSUB132SSZr_Int + 0U, // VFMSUB132SSZr_Intk + 0U, // VFMSUB132SSZr_Intkz + 0U, // VFMSUB132SSZrb + 0U, // VFMSUB132SSZrb_Int + 0U, // VFMSUB132SSZrb_Intk + 0U, // VFMSUB132SSZrb_Intkz + 0U, // VFMSUB132SSm + 0U, // VFMSUB132SSm_Int + 0U, // VFMSUB132SSr + 0U, // VFMSUB132SSr_Int + 0U, // VFMSUB213PDYm + 0U, // VFMSUB213PDYr + 0U, // VFMSUB213PDZ128m + 0U, // VFMSUB213PDZ128mb + 0U, // VFMSUB213PDZ128mbk + 0U, // VFMSUB213PDZ128mbkz + 0U, // VFMSUB213PDZ128mk + 0U, // VFMSUB213PDZ128mkz + 0U, // VFMSUB213PDZ128r + 0U, // VFMSUB213PDZ128rk + 0U, // VFMSUB213PDZ128rkz + 0U, // VFMSUB213PDZ256m + 0U, // VFMSUB213PDZ256mb + 0U, // VFMSUB213PDZ256mbk + 0U, // VFMSUB213PDZ256mbkz + 0U, // VFMSUB213PDZ256mk + 0U, // VFMSUB213PDZ256mkz + 0U, // VFMSUB213PDZ256r + 0U, // VFMSUB213PDZ256rk + 0U, // VFMSUB213PDZ256rkz + 0U, // VFMSUB213PDZm + 0U, // VFMSUB213PDZmb + 0U, // VFMSUB213PDZmbk + 0U, // VFMSUB213PDZmbkz + 0U, // VFMSUB213PDZmk + 0U, // VFMSUB213PDZmkz + 0U, // VFMSUB213PDZr + 0U, // VFMSUB213PDZrb + 0U, // VFMSUB213PDZrbk + 0U, // VFMSUB213PDZrbkz + 0U, // VFMSUB213PDZrk + 0U, // VFMSUB213PDZrkz + 0U, // VFMSUB213PDm + 0U, // VFMSUB213PDr + 0U, // VFMSUB213PSYm + 0U, // VFMSUB213PSYr + 0U, // VFMSUB213PSZ128m + 0U, // VFMSUB213PSZ128mb + 0U, // VFMSUB213PSZ128mbk + 0U, // VFMSUB213PSZ128mbkz + 0U, // VFMSUB213PSZ128mk + 0U, // VFMSUB213PSZ128mkz + 0U, // VFMSUB213PSZ128r + 0U, // VFMSUB213PSZ128rk + 0U, // VFMSUB213PSZ128rkz + 0U, // VFMSUB213PSZ256m + 0U, // VFMSUB213PSZ256mb + 0U, // VFMSUB213PSZ256mbk + 0U, // VFMSUB213PSZ256mbkz + 0U, // VFMSUB213PSZ256mk + 0U, // VFMSUB213PSZ256mkz + 0U, // VFMSUB213PSZ256r + 0U, // VFMSUB213PSZ256rk + 0U, // VFMSUB213PSZ256rkz + 0U, // VFMSUB213PSZm + 0U, // VFMSUB213PSZmb + 0U, // VFMSUB213PSZmbk + 0U, // VFMSUB213PSZmbkz + 0U, // VFMSUB213PSZmk + 0U, // VFMSUB213PSZmkz + 0U, // VFMSUB213PSZr + 0U, // VFMSUB213PSZrb + 0U, // VFMSUB213PSZrbk + 0U, // VFMSUB213PSZrbkz + 0U, // VFMSUB213PSZrk + 0U, // VFMSUB213PSZrkz + 0U, // VFMSUB213PSm + 0U, // VFMSUB213PSr + 0U, // VFMSUB213SDZm + 0U, // VFMSUB213SDZm_Int + 0U, // VFMSUB213SDZm_Intk + 0U, // VFMSUB213SDZm_Intkz + 0U, // VFMSUB213SDZr + 0U, // VFMSUB213SDZr_Int + 0U, // VFMSUB213SDZr_Intk + 0U, // VFMSUB213SDZr_Intkz + 0U, // VFMSUB213SDZrb + 0U, // VFMSUB213SDZrb_Int + 0U, // VFMSUB213SDZrb_Intk + 0U, // VFMSUB213SDZrb_Intkz + 0U, // VFMSUB213SDm + 0U, // VFMSUB213SDm_Int + 0U, // VFMSUB213SDr + 0U, // VFMSUB213SDr_Int + 0U, // VFMSUB213SSZm + 0U, // VFMSUB213SSZm_Int + 0U, // VFMSUB213SSZm_Intk + 0U, // VFMSUB213SSZm_Intkz + 0U, // VFMSUB213SSZr + 0U, // VFMSUB213SSZr_Int + 0U, // VFMSUB213SSZr_Intk + 0U, // VFMSUB213SSZr_Intkz + 0U, // VFMSUB213SSZrb + 0U, // VFMSUB213SSZrb_Int + 0U, // VFMSUB213SSZrb_Intk + 0U, // VFMSUB213SSZrb_Intkz + 0U, // VFMSUB213SSm + 0U, // VFMSUB213SSm_Int + 0U, // VFMSUB213SSr + 0U, // VFMSUB213SSr_Int + 0U, // VFMSUB231PDYm + 0U, // VFMSUB231PDYr + 0U, // VFMSUB231PDZ128m + 0U, // VFMSUB231PDZ128mb + 0U, // VFMSUB231PDZ128mbk + 0U, // VFMSUB231PDZ128mbkz + 0U, // VFMSUB231PDZ128mk + 0U, // VFMSUB231PDZ128mkz + 0U, // VFMSUB231PDZ128r + 0U, // VFMSUB231PDZ128rk + 0U, // VFMSUB231PDZ128rkz + 0U, // VFMSUB231PDZ256m + 0U, // VFMSUB231PDZ256mb + 0U, // VFMSUB231PDZ256mbk + 0U, // VFMSUB231PDZ256mbkz + 0U, // VFMSUB231PDZ256mk + 0U, // VFMSUB231PDZ256mkz + 0U, // VFMSUB231PDZ256r + 0U, // VFMSUB231PDZ256rk + 0U, // VFMSUB231PDZ256rkz + 0U, // VFMSUB231PDZm + 0U, // VFMSUB231PDZmb + 0U, // VFMSUB231PDZmbk + 0U, // VFMSUB231PDZmbkz + 0U, // VFMSUB231PDZmk + 0U, // VFMSUB231PDZmkz + 0U, // VFMSUB231PDZr + 0U, // VFMSUB231PDZrb + 0U, // VFMSUB231PDZrbk + 0U, // VFMSUB231PDZrbkz + 0U, // VFMSUB231PDZrk + 0U, // VFMSUB231PDZrkz + 0U, // VFMSUB231PDm + 0U, // VFMSUB231PDr + 0U, // VFMSUB231PSYm + 0U, // VFMSUB231PSYr + 0U, // VFMSUB231PSZ128m + 0U, // VFMSUB231PSZ128mb + 0U, // VFMSUB231PSZ128mbk + 0U, // VFMSUB231PSZ128mbkz + 0U, // VFMSUB231PSZ128mk + 0U, // VFMSUB231PSZ128mkz + 0U, // VFMSUB231PSZ128r + 0U, // VFMSUB231PSZ128rk + 0U, // VFMSUB231PSZ128rkz + 0U, // VFMSUB231PSZ256m + 0U, // VFMSUB231PSZ256mb + 0U, // VFMSUB231PSZ256mbk + 0U, // VFMSUB231PSZ256mbkz + 0U, // VFMSUB231PSZ256mk + 0U, // VFMSUB231PSZ256mkz + 0U, // VFMSUB231PSZ256r + 0U, // VFMSUB231PSZ256rk + 0U, // VFMSUB231PSZ256rkz + 0U, // VFMSUB231PSZm + 0U, // VFMSUB231PSZmb + 0U, // VFMSUB231PSZmbk + 0U, // VFMSUB231PSZmbkz + 0U, // VFMSUB231PSZmk + 0U, // VFMSUB231PSZmkz + 0U, // VFMSUB231PSZr + 0U, // VFMSUB231PSZrb + 0U, // VFMSUB231PSZrbk + 0U, // VFMSUB231PSZrbkz + 0U, // VFMSUB231PSZrk + 0U, // VFMSUB231PSZrkz + 0U, // VFMSUB231PSm + 0U, // VFMSUB231PSr + 0U, // VFMSUB231SDZm + 0U, // VFMSUB231SDZm_Int + 0U, // VFMSUB231SDZm_Intk + 0U, // VFMSUB231SDZm_Intkz + 0U, // VFMSUB231SDZr + 0U, // VFMSUB231SDZr_Int + 0U, // VFMSUB231SDZr_Intk + 0U, // VFMSUB231SDZr_Intkz + 0U, // VFMSUB231SDZrb + 0U, // VFMSUB231SDZrb_Int + 0U, // VFMSUB231SDZrb_Intk + 0U, // VFMSUB231SDZrb_Intkz + 0U, // VFMSUB231SDm + 0U, // VFMSUB231SDm_Int + 0U, // VFMSUB231SDr + 0U, // VFMSUB231SDr_Int + 0U, // VFMSUB231SSZm + 0U, // VFMSUB231SSZm_Int + 0U, // VFMSUB231SSZm_Intk + 0U, // VFMSUB231SSZm_Intkz + 0U, // VFMSUB231SSZr + 0U, // VFMSUB231SSZr_Int + 0U, // VFMSUB231SSZr_Intk + 0U, // VFMSUB231SSZr_Intkz + 0U, // VFMSUB231SSZrb + 0U, // VFMSUB231SSZrb_Int + 0U, // VFMSUB231SSZrb_Intk + 0U, // VFMSUB231SSZrb_Intkz + 0U, // VFMSUB231SSm + 0U, // VFMSUB231SSm_Int + 0U, // VFMSUB231SSr + 0U, // VFMSUB231SSr_Int + 0U, // VFMSUBADD132PDYm + 0U, // VFMSUBADD132PDYr + 0U, // VFMSUBADD132PDZ128m + 0U, // VFMSUBADD132PDZ128mb + 0U, // VFMSUBADD132PDZ128mbk + 0U, // VFMSUBADD132PDZ128mbkz + 0U, // VFMSUBADD132PDZ128mk + 0U, // VFMSUBADD132PDZ128mkz + 0U, // VFMSUBADD132PDZ128r + 0U, // VFMSUBADD132PDZ128rk + 0U, // VFMSUBADD132PDZ128rkz + 0U, // VFMSUBADD132PDZ256m + 0U, // VFMSUBADD132PDZ256mb + 0U, // VFMSUBADD132PDZ256mbk + 0U, // VFMSUBADD132PDZ256mbkz + 0U, // VFMSUBADD132PDZ256mk + 0U, // VFMSUBADD132PDZ256mkz + 0U, // VFMSUBADD132PDZ256r + 0U, // VFMSUBADD132PDZ256rk + 0U, // VFMSUBADD132PDZ256rkz + 0U, // VFMSUBADD132PDZm + 0U, // VFMSUBADD132PDZmb + 0U, // VFMSUBADD132PDZmbk + 0U, // VFMSUBADD132PDZmbkz + 0U, // VFMSUBADD132PDZmk + 0U, // VFMSUBADD132PDZmkz + 0U, // VFMSUBADD132PDZr + 0U, // VFMSUBADD132PDZrb + 0U, // VFMSUBADD132PDZrbk + 0U, // VFMSUBADD132PDZrbkz + 0U, // VFMSUBADD132PDZrk + 0U, // VFMSUBADD132PDZrkz + 0U, // VFMSUBADD132PDm + 0U, // VFMSUBADD132PDr + 0U, // VFMSUBADD132PSYm + 0U, // VFMSUBADD132PSYr + 0U, // VFMSUBADD132PSZ128m + 0U, // VFMSUBADD132PSZ128mb + 0U, // VFMSUBADD132PSZ128mbk + 0U, // VFMSUBADD132PSZ128mbkz + 0U, // VFMSUBADD132PSZ128mk + 0U, // VFMSUBADD132PSZ128mkz + 0U, // VFMSUBADD132PSZ128r + 0U, // VFMSUBADD132PSZ128rk + 0U, // VFMSUBADD132PSZ128rkz + 0U, // VFMSUBADD132PSZ256m + 0U, // VFMSUBADD132PSZ256mb + 0U, // VFMSUBADD132PSZ256mbk + 0U, // VFMSUBADD132PSZ256mbkz + 0U, // VFMSUBADD132PSZ256mk + 0U, // VFMSUBADD132PSZ256mkz + 0U, // VFMSUBADD132PSZ256r + 0U, // VFMSUBADD132PSZ256rk + 0U, // VFMSUBADD132PSZ256rkz + 0U, // VFMSUBADD132PSZm + 0U, // VFMSUBADD132PSZmb + 0U, // VFMSUBADD132PSZmbk + 0U, // VFMSUBADD132PSZmbkz + 0U, // VFMSUBADD132PSZmk + 0U, // VFMSUBADD132PSZmkz + 0U, // VFMSUBADD132PSZr + 0U, // VFMSUBADD132PSZrb + 0U, // VFMSUBADD132PSZrbk + 0U, // VFMSUBADD132PSZrbkz + 0U, // VFMSUBADD132PSZrk + 0U, // VFMSUBADD132PSZrkz + 0U, // VFMSUBADD132PSm + 0U, // VFMSUBADD132PSr + 0U, // VFMSUBADD213PDYm + 0U, // VFMSUBADD213PDYr + 0U, // VFMSUBADD213PDZ128m + 0U, // VFMSUBADD213PDZ128mb + 0U, // VFMSUBADD213PDZ128mbk + 0U, // VFMSUBADD213PDZ128mbkz + 0U, // VFMSUBADD213PDZ128mk + 0U, // VFMSUBADD213PDZ128mkz + 0U, // VFMSUBADD213PDZ128r + 0U, // VFMSUBADD213PDZ128rk + 0U, // VFMSUBADD213PDZ128rkz + 0U, // VFMSUBADD213PDZ256m + 0U, // VFMSUBADD213PDZ256mb + 0U, // VFMSUBADD213PDZ256mbk + 0U, // VFMSUBADD213PDZ256mbkz + 0U, // VFMSUBADD213PDZ256mk + 0U, // VFMSUBADD213PDZ256mkz + 0U, // VFMSUBADD213PDZ256r + 0U, // VFMSUBADD213PDZ256rk + 0U, // VFMSUBADD213PDZ256rkz + 0U, // VFMSUBADD213PDZm + 0U, // VFMSUBADD213PDZmb + 0U, // VFMSUBADD213PDZmbk + 0U, // VFMSUBADD213PDZmbkz + 0U, // VFMSUBADD213PDZmk + 0U, // VFMSUBADD213PDZmkz + 0U, // VFMSUBADD213PDZr + 0U, // VFMSUBADD213PDZrb + 0U, // VFMSUBADD213PDZrbk + 0U, // VFMSUBADD213PDZrbkz + 0U, // VFMSUBADD213PDZrk + 0U, // VFMSUBADD213PDZrkz + 0U, // VFMSUBADD213PDm + 0U, // VFMSUBADD213PDr + 0U, // VFMSUBADD213PSYm + 0U, // VFMSUBADD213PSYr + 0U, // VFMSUBADD213PSZ128m + 0U, // VFMSUBADD213PSZ128mb + 0U, // VFMSUBADD213PSZ128mbk + 0U, // VFMSUBADD213PSZ128mbkz + 0U, // VFMSUBADD213PSZ128mk + 0U, // VFMSUBADD213PSZ128mkz + 0U, // VFMSUBADD213PSZ128r + 0U, // VFMSUBADD213PSZ128rk + 0U, // VFMSUBADD213PSZ128rkz + 0U, // VFMSUBADD213PSZ256m + 0U, // VFMSUBADD213PSZ256mb + 0U, // VFMSUBADD213PSZ256mbk + 0U, // VFMSUBADD213PSZ256mbkz + 0U, // VFMSUBADD213PSZ256mk + 0U, // VFMSUBADD213PSZ256mkz + 0U, // VFMSUBADD213PSZ256r + 0U, // VFMSUBADD213PSZ256rk + 0U, // VFMSUBADD213PSZ256rkz + 0U, // VFMSUBADD213PSZm + 0U, // VFMSUBADD213PSZmb + 0U, // VFMSUBADD213PSZmbk + 0U, // VFMSUBADD213PSZmbkz + 0U, // VFMSUBADD213PSZmk + 0U, // VFMSUBADD213PSZmkz + 0U, // VFMSUBADD213PSZr + 0U, // VFMSUBADD213PSZrb + 0U, // VFMSUBADD213PSZrbk + 0U, // VFMSUBADD213PSZrbkz + 0U, // VFMSUBADD213PSZrk + 0U, // VFMSUBADD213PSZrkz + 0U, // VFMSUBADD213PSm + 0U, // VFMSUBADD213PSr + 0U, // VFMSUBADD231PDYm + 0U, // VFMSUBADD231PDYr + 0U, // VFMSUBADD231PDZ128m + 0U, // VFMSUBADD231PDZ128mb + 0U, // VFMSUBADD231PDZ128mbk + 0U, // VFMSUBADD231PDZ128mbkz + 0U, // VFMSUBADD231PDZ128mk + 0U, // VFMSUBADD231PDZ128mkz + 0U, // VFMSUBADD231PDZ128r + 0U, // VFMSUBADD231PDZ128rk + 0U, // VFMSUBADD231PDZ128rkz + 0U, // VFMSUBADD231PDZ256m + 0U, // VFMSUBADD231PDZ256mb + 0U, // VFMSUBADD231PDZ256mbk + 0U, // VFMSUBADD231PDZ256mbkz + 0U, // VFMSUBADD231PDZ256mk + 0U, // VFMSUBADD231PDZ256mkz + 0U, // VFMSUBADD231PDZ256r + 0U, // VFMSUBADD231PDZ256rk + 0U, // VFMSUBADD231PDZ256rkz + 0U, // VFMSUBADD231PDZm + 0U, // VFMSUBADD231PDZmb + 0U, // VFMSUBADD231PDZmbk + 0U, // VFMSUBADD231PDZmbkz + 0U, // VFMSUBADD231PDZmk + 0U, // VFMSUBADD231PDZmkz + 0U, // VFMSUBADD231PDZr + 0U, // VFMSUBADD231PDZrb + 0U, // VFMSUBADD231PDZrbk + 0U, // VFMSUBADD231PDZrbkz + 0U, // VFMSUBADD231PDZrk + 0U, // VFMSUBADD231PDZrkz + 0U, // VFMSUBADD231PDm + 0U, // VFMSUBADD231PDr + 0U, // VFMSUBADD231PSYm + 0U, // VFMSUBADD231PSYr + 0U, // VFMSUBADD231PSZ128m + 0U, // VFMSUBADD231PSZ128mb + 0U, // VFMSUBADD231PSZ128mbk + 0U, // VFMSUBADD231PSZ128mbkz + 0U, // VFMSUBADD231PSZ128mk + 0U, // VFMSUBADD231PSZ128mkz + 0U, // VFMSUBADD231PSZ128r + 0U, // VFMSUBADD231PSZ128rk + 0U, // VFMSUBADD231PSZ128rkz + 0U, // VFMSUBADD231PSZ256m + 0U, // VFMSUBADD231PSZ256mb + 0U, // VFMSUBADD231PSZ256mbk + 0U, // VFMSUBADD231PSZ256mbkz + 0U, // VFMSUBADD231PSZ256mk + 0U, // VFMSUBADD231PSZ256mkz + 0U, // VFMSUBADD231PSZ256r + 0U, // VFMSUBADD231PSZ256rk + 0U, // VFMSUBADD231PSZ256rkz + 0U, // VFMSUBADD231PSZm + 0U, // VFMSUBADD231PSZmb + 0U, // VFMSUBADD231PSZmbk + 0U, // VFMSUBADD231PSZmbkz + 0U, // VFMSUBADD231PSZmk + 0U, // VFMSUBADD231PSZmkz + 0U, // VFMSUBADD231PSZr + 0U, // VFMSUBADD231PSZrb + 0U, // VFMSUBADD231PSZrbk + 0U, // VFMSUBADD231PSZrbkz + 0U, // VFMSUBADD231PSZrk + 0U, // VFMSUBADD231PSZrkz + 0U, // VFMSUBADD231PSm + 0U, // VFMSUBADD231PSr + 0U, // VFMSUBADDPD4Ymr + 0U, // VFMSUBADDPD4Yrm + 0U, // VFMSUBADDPD4Yrr + 0U, // VFMSUBADDPD4Yrr_REV + 0U, // VFMSUBADDPD4mr + 0U, // VFMSUBADDPD4rm + 0U, // VFMSUBADDPD4rr + 0U, // VFMSUBADDPD4rr_REV + 0U, // VFMSUBADDPS4Ymr + 0U, // VFMSUBADDPS4Yrm + 0U, // VFMSUBADDPS4Yrr + 0U, // VFMSUBADDPS4Yrr_REV + 0U, // VFMSUBADDPS4mr + 0U, // VFMSUBADDPS4rm + 0U, // VFMSUBADDPS4rr + 0U, // VFMSUBADDPS4rr_REV + 0U, // VFMSUBPD4Ymr + 0U, // VFMSUBPD4Yrm + 0U, // VFMSUBPD4Yrr + 0U, // VFMSUBPD4Yrr_REV + 0U, // VFMSUBPD4mr + 0U, // VFMSUBPD4rm + 0U, // VFMSUBPD4rr + 0U, // VFMSUBPD4rr_REV + 0U, // VFMSUBPS4Ymr + 0U, // VFMSUBPS4Yrm + 0U, // VFMSUBPS4Yrr + 0U, // VFMSUBPS4Yrr_REV + 0U, // VFMSUBPS4mr + 0U, // VFMSUBPS4rm + 0U, // VFMSUBPS4rr + 0U, // VFMSUBPS4rr_REV + 0U, // VFMSUBSD4mr + 0U, // VFMSUBSD4mr_Int + 0U, // VFMSUBSD4rm + 0U, // VFMSUBSD4rm_Int + 0U, // VFMSUBSD4rr + 0U, // VFMSUBSD4rr_Int + 0U, // VFMSUBSD4rr_Int_REV + 0U, // VFMSUBSD4rr_REV + 0U, // VFMSUBSS4mr + 0U, // VFMSUBSS4mr_Int + 0U, // VFMSUBSS4rm + 0U, // VFMSUBSS4rm_Int + 0U, // VFMSUBSS4rr + 0U, // VFMSUBSS4rr_Int + 0U, // VFMSUBSS4rr_Int_REV + 0U, // VFMSUBSS4rr_REV + 0U, // VFNMADD132PDYm + 0U, // VFNMADD132PDYr + 0U, // VFNMADD132PDZ128m + 0U, // VFNMADD132PDZ128mb + 0U, // VFNMADD132PDZ128mbk + 0U, // VFNMADD132PDZ128mbkz + 0U, // VFNMADD132PDZ128mk + 0U, // VFNMADD132PDZ128mkz + 0U, // VFNMADD132PDZ128r + 0U, // VFNMADD132PDZ128rk + 0U, // VFNMADD132PDZ128rkz + 0U, // VFNMADD132PDZ256m + 0U, // VFNMADD132PDZ256mb + 0U, // VFNMADD132PDZ256mbk + 0U, // VFNMADD132PDZ256mbkz + 0U, // VFNMADD132PDZ256mk + 0U, // VFNMADD132PDZ256mkz + 0U, // VFNMADD132PDZ256r + 0U, // VFNMADD132PDZ256rk + 0U, // VFNMADD132PDZ256rkz + 0U, // VFNMADD132PDZm + 0U, // VFNMADD132PDZmb + 0U, // VFNMADD132PDZmbk + 0U, // VFNMADD132PDZmbkz + 0U, // VFNMADD132PDZmk + 0U, // VFNMADD132PDZmkz + 0U, // VFNMADD132PDZr + 0U, // VFNMADD132PDZrb + 0U, // VFNMADD132PDZrbk + 0U, // VFNMADD132PDZrbkz + 0U, // VFNMADD132PDZrk + 0U, // VFNMADD132PDZrkz + 0U, // VFNMADD132PDm + 0U, // VFNMADD132PDr + 0U, // VFNMADD132PSYm + 0U, // VFNMADD132PSYr + 0U, // VFNMADD132PSZ128m + 0U, // VFNMADD132PSZ128mb + 0U, // VFNMADD132PSZ128mbk + 0U, // VFNMADD132PSZ128mbkz + 0U, // VFNMADD132PSZ128mk + 0U, // VFNMADD132PSZ128mkz + 0U, // VFNMADD132PSZ128r + 0U, // VFNMADD132PSZ128rk + 0U, // VFNMADD132PSZ128rkz + 0U, // VFNMADD132PSZ256m + 0U, // VFNMADD132PSZ256mb + 0U, // VFNMADD132PSZ256mbk + 0U, // VFNMADD132PSZ256mbkz + 0U, // VFNMADD132PSZ256mk + 0U, // VFNMADD132PSZ256mkz + 0U, // VFNMADD132PSZ256r + 0U, // VFNMADD132PSZ256rk + 0U, // VFNMADD132PSZ256rkz + 0U, // VFNMADD132PSZm + 0U, // VFNMADD132PSZmb + 0U, // VFNMADD132PSZmbk + 0U, // VFNMADD132PSZmbkz + 0U, // VFNMADD132PSZmk + 0U, // VFNMADD132PSZmkz + 0U, // VFNMADD132PSZr + 0U, // VFNMADD132PSZrb + 0U, // VFNMADD132PSZrbk + 0U, // VFNMADD132PSZrbkz + 0U, // VFNMADD132PSZrk + 0U, // VFNMADD132PSZrkz + 0U, // VFNMADD132PSm + 0U, // VFNMADD132PSr + 0U, // VFNMADD132SDZm + 0U, // VFNMADD132SDZm_Int + 0U, // VFNMADD132SDZm_Intk + 0U, // VFNMADD132SDZm_Intkz + 0U, // VFNMADD132SDZr + 0U, // VFNMADD132SDZr_Int + 0U, // VFNMADD132SDZr_Intk + 0U, // VFNMADD132SDZr_Intkz + 0U, // VFNMADD132SDZrb + 0U, // VFNMADD132SDZrb_Int + 0U, // VFNMADD132SDZrb_Intk + 0U, // VFNMADD132SDZrb_Intkz + 0U, // VFNMADD132SDm + 0U, // VFNMADD132SDm_Int + 0U, // VFNMADD132SDr + 0U, // VFNMADD132SDr_Int + 0U, // VFNMADD132SSZm + 0U, // VFNMADD132SSZm_Int + 0U, // VFNMADD132SSZm_Intk + 0U, // VFNMADD132SSZm_Intkz + 0U, // VFNMADD132SSZr + 0U, // VFNMADD132SSZr_Int + 0U, // VFNMADD132SSZr_Intk + 0U, // VFNMADD132SSZr_Intkz + 0U, // VFNMADD132SSZrb + 0U, // VFNMADD132SSZrb_Int + 0U, // VFNMADD132SSZrb_Intk + 0U, // VFNMADD132SSZrb_Intkz + 0U, // VFNMADD132SSm + 0U, // VFNMADD132SSm_Int + 0U, // VFNMADD132SSr + 0U, // VFNMADD132SSr_Int + 0U, // VFNMADD213PDYm + 0U, // VFNMADD213PDYr + 0U, // VFNMADD213PDZ128m + 0U, // VFNMADD213PDZ128mb + 0U, // VFNMADD213PDZ128mbk + 0U, // VFNMADD213PDZ128mbkz + 0U, // VFNMADD213PDZ128mk + 0U, // VFNMADD213PDZ128mkz + 0U, // VFNMADD213PDZ128r + 0U, // VFNMADD213PDZ128rk + 0U, // VFNMADD213PDZ128rkz + 0U, // VFNMADD213PDZ256m + 0U, // VFNMADD213PDZ256mb + 0U, // VFNMADD213PDZ256mbk + 0U, // VFNMADD213PDZ256mbkz + 0U, // VFNMADD213PDZ256mk + 0U, // VFNMADD213PDZ256mkz + 0U, // VFNMADD213PDZ256r + 0U, // VFNMADD213PDZ256rk + 0U, // VFNMADD213PDZ256rkz + 0U, // VFNMADD213PDZm + 0U, // VFNMADD213PDZmb + 0U, // VFNMADD213PDZmbk + 0U, // VFNMADD213PDZmbkz + 0U, // VFNMADD213PDZmk + 0U, // VFNMADD213PDZmkz + 0U, // VFNMADD213PDZr + 0U, // VFNMADD213PDZrb + 0U, // VFNMADD213PDZrbk + 0U, // VFNMADD213PDZrbkz + 0U, // VFNMADD213PDZrk + 0U, // VFNMADD213PDZrkz + 0U, // VFNMADD213PDm + 0U, // VFNMADD213PDr + 0U, // VFNMADD213PSYm + 0U, // VFNMADD213PSYr + 0U, // VFNMADD213PSZ128m + 0U, // VFNMADD213PSZ128mb + 0U, // VFNMADD213PSZ128mbk + 0U, // VFNMADD213PSZ128mbkz + 0U, // VFNMADD213PSZ128mk + 0U, // VFNMADD213PSZ128mkz + 0U, // VFNMADD213PSZ128r + 0U, // VFNMADD213PSZ128rk + 0U, // VFNMADD213PSZ128rkz + 0U, // VFNMADD213PSZ256m + 0U, // VFNMADD213PSZ256mb + 0U, // VFNMADD213PSZ256mbk + 0U, // VFNMADD213PSZ256mbkz + 0U, // VFNMADD213PSZ256mk + 0U, // VFNMADD213PSZ256mkz + 0U, // VFNMADD213PSZ256r + 0U, // VFNMADD213PSZ256rk + 0U, // VFNMADD213PSZ256rkz + 0U, // VFNMADD213PSZm + 0U, // VFNMADD213PSZmb + 0U, // VFNMADD213PSZmbk + 0U, // VFNMADD213PSZmbkz + 0U, // VFNMADD213PSZmk + 0U, // VFNMADD213PSZmkz + 0U, // VFNMADD213PSZr + 0U, // VFNMADD213PSZrb + 0U, // VFNMADD213PSZrbk + 0U, // VFNMADD213PSZrbkz + 0U, // VFNMADD213PSZrk + 0U, // VFNMADD213PSZrkz + 0U, // VFNMADD213PSm + 0U, // VFNMADD213PSr + 0U, // VFNMADD213SDZm + 0U, // VFNMADD213SDZm_Int + 0U, // VFNMADD213SDZm_Intk + 0U, // VFNMADD213SDZm_Intkz + 0U, // VFNMADD213SDZr + 0U, // VFNMADD213SDZr_Int + 0U, // VFNMADD213SDZr_Intk + 0U, // VFNMADD213SDZr_Intkz + 0U, // VFNMADD213SDZrb + 0U, // VFNMADD213SDZrb_Int + 0U, // VFNMADD213SDZrb_Intk + 0U, // VFNMADD213SDZrb_Intkz + 0U, // VFNMADD213SDm + 0U, // VFNMADD213SDm_Int + 0U, // VFNMADD213SDr + 0U, // VFNMADD213SDr_Int + 0U, // VFNMADD213SSZm + 0U, // VFNMADD213SSZm_Int + 0U, // VFNMADD213SSZm_Intk + 0U, // VFNMADD213SSZm_Intkz + 0U, // VFNMADD213SSZr + 0U, // VFNMADD213SSZr_Int + 0U, // VFNMADD213SSZr_Intk + 0U, // VFNMADD213SSZr_Intkz + 0U, // VFNMADD213SSZrb + 0U, // VFNMADD213SSZrb_Int + 0U, // VFNMADD213SSZrb_Intk + 0U, // VFNMADD213SSZrb_Intkz + 0U, // VFNMADD213SSm + 0U, // VFNMADD213SSm_Int + 0U, // VFNMADD213SSr + 0U, // VFNMADD213SSr_Int + 0U, // VFNMADD231PDYm + 0U, // VFNMADD231PDYr + 0U, // VFNMADD231PDZ128m + 0U, // VFNMADD231PDZ128mb + 0U, // VFNMADD231PDZ128mbk + 0U, // VFNMADD231PDZ128mbkz + 0U, // VFNMADD231PDZ128mk + 0U, // VFNMADD231PDZ128mkz + 0U, // VFNMADD231PDZ128r + 0U, // VFNMADD231PDZ128rk + 0U, // VFNMADD231PDZ128rkz + 0U, // VFNMADD231PDZ256m + 0U, // VFNMADD231PDZ256mb + 0U, // VFNMADD231PDZ256mbk + 0U, // VFNMADD231PDZ256mbkz + 0U, // VFNMADD231PDZ256mk + 0U, // VFNMADD231PDZ256mkz + 0U, // VFNMADD231PDZ256r + 0U, // VFNMADD231PDZ256rk + 0U, // VFNMADD231PDZ256rkz + 0U, // VFNMADD231PDZm + 0U, // VFNMADD231PDZmb + 0U, // VFNMADD231PDZmbk + 0U, // VFNMADD231PDZmbkz + 0U, // VFNMADD231PDZmk + 0U, // VFNMADD231PDZmkz + 0U, // VFNMADD231PDZr + 0U, // VFNMADD231PDZrb + 0U, // VFNMADD231PDZrbk + 0U, // VFNMADD231PDZrbkz + 0U, // VFNMADD231PDZrk + 0U, // VFNMADD231PDZrkz + 0U, // VFNMADD231PDm + 0U, // VFNMADD231PDr + 0U, // VFNMADD231PSYm + 0U, // VFNMADD231PSYr + 0U, // VFNMADD231PSZ128m + 0U, // VFNMADD231PSZ128mb + 0U, // VFNMADD231PSZ128mbk + 0U, // VFNMADD231PSZ128mbkz + 0U, // VFNMADD231PSZ128mk + 0U, // VFNMADD231PSZ128mkz + 0U, // VFNMADD231PSZ128r + 0U, // VFNMADD231PSZ128rk + 0U, // VFNMADD231PSZ128rkz + 0U, // VFNMADD231PSZ256m + 0U, // VFNMADD231PSZ256mb + 0U, // VFNMADD231PSZ256mbk + 0U, // VFNMADD231PSZ256mbkz + 0U, // VFNMADD231PSZ256mk + 0U, // VFNMADD231PSZ256mkz + 0U, // VFNMADD231PSZ256r + 0U, // VFNMADD231PSZ256rk + 0U, // VFNMADD231PSZ256rkz + 0U, // VFNMADD231PSZm + 0U, // VFNMADD231PSZmb + 0U, // VFNMADD231PSZmbk + 0U, // VFNMADD231PSZmbkz + 0U, // VFNMADD231PSZmk + 0U, // VFNMADD231PSZmkz + 0U, // VFNMADD231PSZr + 0U, // VFNMADD231PSZrb + 0U, // VFNMADD231PSZrbk + 0U, // VFNMADD231PSZrbkz + 0U, // VFNMADD231PSZrk + 0U, // VFNMADD231PSZrkz + 0U, // VFNMADD231PSm + 0U, // VFNMADD231PSr + 0U, // VFNMADD231SDZm + 0U, // VFNMADD231SDZm_Int + 0U, // VFNMADD231SDZm_Intk + 0U, // VFNMADD231SDZm_Intkz + 0U, // VFNMADD231SDZr + 0U, // VFNMADD231SDZr_Int + 0U, // VFNMADD231SDZr_Intk + 0U, // VFNMADD231SDZr_Intkz + 0U, // VFNMADD231SDZrb + 0U, // VFNMADD231SDZrb_Int + 0U, // VFNMADD231SDZrb_Intk + 0U, // VFNMADD231SDZrb_Intkz + 0U, // VFNMADD231SDm + 0U, // VFNMADD231SDm_Int + 0U, // VFNMADD231SDr + 0U, // VFNMADD231SDr_Int + 0U, // VFNMADD231SSZm + 0U, // VFNMADD231SSZm_Int + 0U, // VFNMADD231SSZm_Intk + 0U, // VFNMADD231SSZm_Intkz + 0U, // VFNMADD231SSZr + 0U, // VFNMADD231SSZr_Int + 0U, // VFNMADD231SSZr_Intk + 0U, // VFNMADD231SSZr_Intkz + 0U, // VFNMADD231SSZrb + 0U, // VFNMADD231SSZrb_Int + 0U, // VFNMADD231SSZrb_Intk + 0U, // VFNMADD231SSZrb_Intkz + 0U, // VFNMADD231SSm + 0U, // VFNMADD231SSm_Int + 0U, // VFNMADD231SSr + 0U, // VFNMADD231SSr_Int + 0U, // VFNMADDPD4Ymr + 0U, // VFNMADDPD4Yrm + 0U, // VFNMADDPD4Yrr + 0U, // VFNMADDPD4Yrr_REV + 0U, // VFNMADDPD4mr + 0U, // VFNMADDPD4rm + 0U, // VFNMADDPD4rr + 0U, // VFNMADDPD4rr_REV + 0U, // VFNMADDPS4Ymr + 0U, // VFNMADDPS4Yrm + 0U, // VFNMADDPS4Yrr + 0U, // VFNMADDPS4Yrr_REV + 0U, // VFNMADDPS4mr + 0U, // VFNMADDPS4rm + 0U, // VFNMADDPS4rr + 0U, // VFNMADDPS4rr_REV + 0U, // VFNMADDSD4mr + 0U, // VFNMADDSD4mr_Int + 0U, // VFNMADDSD4rm + 0U, // VFNMADDSD4rm_Int + 0U, // VFNMADDSD4rr + 0U, // VFNMADDSD4rr_Int + 0U, // VFNMADDSD4rr_Int_REV + 0U, // VFNMADDSD4rr_REV + 0U, // VFNMADDSS4mr + 0U, // VFNMADDSS4mr_Int + 0U, // VFNMADDSS4rm + 0U, // VFNMADDSS4rm_Int + 0U, // VFNMADDSS4rr + 0U, // VFNMADDSS4rr_Int + 0U, // VFNMADDSS4rr_Int_REV + 0U, // VFNMADDSS4rr_REV + 0U, // VFNMSUB132PDYm + 0U, // VFNMSUB132PDYr + 0U, // VFNMSUB132PDZ128m + 0U, // VFNMSUB132PDZ128mb + 0U, // VFNMSUB132PDZ128mbk + 0U, // VFNMSUB132PDZ128mbkz + 0U, // VFNMSUB132PDZ128mk + 0U, // VFNMSUB132PDZ128mkz + 0U, // VFNMSUB132PDZ128r + 0U, // VFNMSUB132PDZ128rk + 0U, // VFNMSUB132PDZ128rkz + 0U, // VFNMSUB132PDZ256m + 0U, // VFNMSUB132PDZ256mb + 0U, // VFNMSUB132PDZ256mbk + 0U, // VFNMSUB132PDZ256mbkz + 0U, // VFNMSUB132PDZ256mk + 0U, // VFNMSUB132PDZ256mkz + 0U, // VFNMSUB132PDZ256r + 0U, // VFNMSUB132PDZ256rk + 0U, // VFNMSUB132PDZ256rkz + 0U, // VFNMSUB132PDZm + 0U, // VFNMSUB132PDZmb + 0U, // VFNMSUB132PDZmbk + 0U, // VFNMSUB132PDZmbkz + 0U, // VFNMSUB132PDZmk + 0U, // VFNMSUB132PDZmkz + 0U, // VFNMSUB132PDZr + 0U, // VFNMSUB132PDZrb + 0U, // VFNMSUB132PDZrbk + 0U, // VFNMSUB132PDZrbkz + 0U, // VFNMSUB132PDZrk + 0U, // VFNMSUB132PDZrkz + 0U, // VFNMSUB132PDm + 0U, // VFNMSUB132PDr + 0U, // VFNMSUB132PSYm + 0U, // VFNMSUB132PSYr + 0U, // VFNMSUB132PSZ128m + 0U, // VFNMSUB132PSZ128mb + 0U, // VFNMSUB132PSZ128mbk + 0U, // VFNMSUB132PSZ128mbkz + 0U, // VFNMSUB132PSZ128mk + 0U, // VFNMSUB132PSZ128mkz + 0U, // VFNMSUB132PSZ128r + 0U, // VFNMSUB132PSZ128rk + 0U, // VFNMSUB132PSZ128rkz + 0U, // VFNMSUB132PSZ256m + 0U, // VFNMSUB132PSZ256mb + 0U, // VFNMSUB132PSZ256mbk + 0U, // VFNMSUB132PSZ256mbkz + 0U, // VFNMSUB132PSZ256mk + 0U, // VFNMSUB132PSZ256mkz + 0U, // VFNMSUB132PSZ256r + 0U, // VFNMSUB132PSZ256rk + 0U, // VFNMSUB132PSZ256rkz + 0U, // VFNMSUB132PSZm + 0U, // VFNMSUB132PSZmb + 0U, // VFNMSUB132PSZmbk + 0U, // VFNMSUB132PSZmbkz + 0U, // VFNMSUB132PSZmk + 0U, // VFNMSUB132PSZmkz + 0U, // VFNMSUB132PSZr + 0U, // VFNMSUB132PSZrb + 0U, // VFNMSUB132PSZrbk + 0U, // VFNMSUB132PSZrbkz + 0U, // VFNMSUB132PSZrk + 0U, // VFNMSUB132PSZrkz + 0U, // VFNMSUB132PSm + 0U, // VFNMSUB132PSr + 0U, // VFNMSUB132SDZm + 0U, // VFNMSUB132SDZm_Int + 0U, // VFNMSUB132SDZm_Intk + 0U, // VFNMSUB132SDZm_Intkz + 0U, // VFNMSUB132SDZr + 0U, // VFNMSUB132SDZr_Int + 0U, // VFNMSUB132SDZr_Intk + 0U, // VFNMSUB132SDZr_Intkz + 0U, // VFNMSUB132SDZrb + 0U, // VFNMSUB132SDZrb_Int + 0U, // VFNMSUB132SDZrb_Intk + 0U, // VFNMSUB132SDZrb_Intkz + 0U, // VFNMSUB132SDm + 0U, // VFNMSUB132SDm_Int + 0U, // VFNMSUB132SDr + 0U, // VFNMSUB132SDr_Int + 0U, // VFNMSUB132SSZm + 0U, // VFNMSUB132SSZm_Int + 0U, // VFNMSUB132SSZm_Intk + 0U, // VFNMSUB132SSZm_Intkz + 0U, // VFNMSUB132SSZr + 0U, // VFNMSUB132SSZr_Int + 0U, // VFNMSUB132SSZr_Intk + 0U, // VFNMSUB132SSZr_Intkz + 0U, // VFNMSUB132SSZrb + 0U, // VFNMSUB132SSZrb_Int + 0U, // VFNMSUB132SSZrb_Intk + 0U, // VFNMSUB132SSZrb_Intkz + 0U, // VFNMSUB132SSm + 0U, // VFNMSUB132SSm_Int + 0U, // VFNMSUB132SSr + 0U, // VFNMSUB132SSr_Int + 0U, // VFNMSUB213PDYm + 0U, // VFNMSUB213PDYr + 0U, // VFNMSUB213PDZ128m + 0U, // VFNMSUB213PDZ128mb + 0U, // VFNMSUB213PDZ128mbk + 0U, // VFNMSUB213PDZ128mbkz + 0U, // VFNMSUB213PDZ128mk + 0U, // VFNMSUB213PDZ128mkz + 0U, // VFNMSUB213PDZ128r + 0U, // VFNMSUB213PDZ128rk + 0U, // VFNMSUB213PDZ128rkz + 0U, // VFNMSUB213PDZ256m + 0U, // VFNMSUB213PDZ256mb + 0U, // VFNMSUB213PDZ256mbk + 0U, // VFNMSUB213PDZ256mbkz + 0U, // VFNMSUB213PDZ256mk + 0U, // VFNMSUB213PDZ256mkz + 0U, // VFNMSUB213PDZ256r + 0U, // VFNMSUB213PDZ256rk + 0U, // VFNMSUB213PDZ256rkz + 0U, // VFNMSUB213PDZm + 0U, // VFNMSUB213PDZmb + 0U, // VFNMSUB213PDZmbk + 0U, // VFNMSUB213PDZmbkz + 0U, // VFNMSUB213PDZmk + 0U, // VFNMSUB213PDZmkz + 0U, // VFNMSUB213PDZr + 0U, // VFNMSUB213PDZrb + 0U, // VFNMSUB213PDZrbk + 0U, // VFNMSUB213PDZrbkz + 0U, // VFNMSUB213PDZrk + 0U, // VFNMSUB213PDZrkz + 0U, // VFNMSUB213PDm + 0U, // VFNMSUB213PDr + 0U, // VFNMSUB213PSYm + 0U, // VFNMSUB213PSYr + 0U, // VFNMSUB213PSZ128m + 0U, // VFNMSUB213PSZ128mb + 0U, // VFNMSUB213PSZ128mbk + 0U, // VFNMSUB213PSZ128mbkz + 0U, // VFNMSUB213PSZ128mk + 0U, // VFNMSUB213PSZ128mkz + 0U, // VFNMSUB213PSZ128r + 0U, // VFNMSUB213PSZ128rk + 0U, // VFNMSUB213PSZ128rkz + 0U, // VFNMSUB213PSZ256m + 0U, // VFNMSUB213PSZ256mb + 0U, // VFNMSUB213PSZ256mbk + 0U, // VFNMSUB213PSZ256mbkz + 0U, // VFNMSUB213PSZ256mk + 0U, // VFNMSUB213PSZ256mkz + 0U, // VFNMSUB213PSZ256r + 0U, // VFNMSUB213PSZ256rk + 0U, // VFNMSUB213PSZ256rkz + 0U, // VFNMSUB213PSZm + 0U, // VFNMSUB213PSZmb + 0U, // VFNMSUB213PSZmbk + 0U, // VFNMSUB213PSZmbkz + 0U, // VFNMSUB213PSZmk + 0U, // VFNMSUB213PSZmkz + 0U, // VFNMSUB213PSZr + 0U, // VFNMSUB213PSZrb + 0U, // VFNMSUB213PSZrbk + 0U, // VFNMSUB213PSZrbkz + 0U, // VFNMSUB213PSZrk + 0U, // VFNMSUB213PSZrkz + 0U, // VFNMSUB213PSm + 0U, // VFNMSUB213PSr + 0U, // VFNMSUB213SDZm + 0U, // VFNMSUB213SDZm_Int + 0U, // VFNMSUB213SDZm_Intk + 0U, // VFNMSUB213SDZm_Intkz + 0U, // VFNMSUB213SDZr + 0U, // VFNMSUB213SDZr_Int + 0U, // VFNMSUB213SDZr_Intk + 0U, // VFNMSUB213SDZr_Intkz + 0U, // VFNMSUB213SDZrb + 0U, // VFNMSUB213SDZrb_Int + 0U, // VFNMSUB213SDZrb_Intk + 0U, // VFNMSUB213SDZrb_Intkz + 0U, // VFNMSUB213SDm + 0U, // VFNMSUB213SDm_Int + 0U, // VFNMSUB213SDr + 0U, // VFNMSUB213SDr_Int + 0U, // VFNMSUB213SSZm + 0U, // VFNMSUB213SSZm_Int + 0U, // VFNMSUB213SSZm_Intk + 0U, // VFNMSUB213SSZm_Intkz + 0U, // VFNMSUB213SSZr + 0U, // VFNMSUB213SSZr_Int + 0U, // VFNMSUB213SSZr_Intk + 0U, // VFNMSUB213SSZr_Intkz + 0U, // VFNMSUB213SSZrb + 0U, // VFNMSUB213SSZrb_Int + 0U, // VFNMSUB213SSZrb_Intk + 0U, // VFNMSUB213SSZrb_Intkz + 0U, // VFNMSUB213SSm + 0U, // VFNMSUB213SSm_Int + 0U, // VFNMSUB213SSr + 0U, // VFNMSUB213SSr_Int + 0U, // VFNMSUB231PDYm + 0U, // VFNMSUB231PDYr + 0U, // VFNMSUB231PDZ128m + 0U, // VFNMSUB231PDZ128mb + 0U, // VFNMSUB231PDZ128mbk + 0U, // VFNMSUB231PDZ128mbkz + 0U, // VFNMSUB231PDZ128mk + 0U, // VFNMSUB231PDZ128mkz + 0U, // VFNMSUB231PDZ128r + 0U, // VFNMSUB231PDZ128rk + 0U, // VFNMSUB231PDZ128rkz + 0U, // VFNMSUB231PDZ256m + 0U, // VFNMSUB231PDZ256mb + 0U, // VFNMSUB231PDZ256mbk + 0U, // VFNMSUB231PDZ256mbkz + 0U, // VFNMSUB231PDZ256mk + 0U, // VFNMSUB231PDZ256mkz + 0U, // VFNMSUB231PDZ256r + 0U, // VFNMSUB231PDZ256rk + 0U, // VFNMSUB231PDZ256rkz + 0U, // VFNMSUB231PDZm + 0U, // VFNMSUB231PDZmb + 0U, // VFNMSUB231PDZmbk + 0U, // VFNMSUB231PDZmbkz + 0U, // VFNMSUB231PDZmk + 0U, // VFNMSUB231PDZmkz + 0U, // VFNMSUB231PDZr + 0U, // VFNMSUB231PDZrb + 0U, // VFNMSUB231PDZrbk + 0U, // VFNMSUB231PDZrbkz + 0U, // VFNMSUB231PDZrk + 0U, // VFNMSUB231PDZrkz + 0U, // VFNMSUB231PDm + 0U, // VFNMSUB231PDr + 0U, // VFNMSUB231PSYm + 0U, // VFNMSUB231PSYr + 0U, // VFNMSUB231PSZ128m + 0U, // VFNMSUB231PSZ128mb + 0U, // VFNMSUB231PSZ128mbk + 0U, // VFNMSUB231PSZ128mbkz + 0U, // VFNMSUB231PSZ128mk + 0U, // VFNMSUB231PSZ128mkz + 0U, // VFNMSUB231PSZ128r + 0U, // VFNMSUB231PSZ128rk + 0U, // VFNMSUB231PSZ128rkz + 0U, // VFNMSUB231PSZ256m + 0U, // VFNMSUB231PSZ256mb + 0U, // VFNMSUB231PSZ256mbk + 0U, // VFNMSUB231PSZ256mbkz + 0U, // VFNMSUB231PSZ256mk + 0U, // VFNMSUB231PSZ256mkz + 0U, // VFNMSUB231PSZ256r + 0U, // VFNMSUB231PSZ256rk + 0U, // VFNMSUB231PSZ256rkz + 0U, // VFNMSUB231PSZm + 0U, // VFNMSUB231PSZmb + 0U, // VFNMSUB231PSZmbk + 0U, // VFNMSUB231PSZmbkz + 0U, // VFNMSUB231PSZmk + 0U, // VFNMSUB231PSZmkz + 0U, // VFNMSUB231PSZr + 0U, // VFNMSUB231PSZrb + 0U, // VFNMSUB231PSZrbk + 0U, // VFNMSUB231PSZrbkz + 0U, // VFNMSUB231PSZrk + 0U, // VFNMSUB231PSZrkz + 0U, // VFNMSUB231PSm + 0U, // VFNMSUB231PSr + 0U, // VFNMSUB231SDZm + 0U, // VFNMSUB231SDZm_Int + 0U, // VFNMSUB231SDZm_Intk + 0U, // VFNMSUB231SDZm_Intkz + 0U, // VFNMSUB231SDZr + 0U, // VFNMSUB231SDZr_Int + 0U, // VFNMSUB231SDZr_Intk + 0U, // VFNMSUB231SDZr_Intkz + 0U, // VFNMSUB231SDZrb + 0U, // VFNMSUB231SDZrb_Int + 0U, // VFNMSUB231SDZrb_Intk + 0U, // VFNMSUB231SDZrb_Intkz + 0U, // VFNMSUB231SDm + 0U, // VFNMSUB231SDm_Int + 0U, // VFNMSUB231SDr + 0U, // VFNMSUB231SDr_Int + 0U, // VFNMSUB231SSZm + 0U, // VFNMSUB231SSZm_Int + 0U, // VFNMSUB231SSZm_Intk + 0U, // VFNMSUB231SSZm_Intkz + 0U, // VFNMSUB231SSZr + 0U, // VFNMSUB231SSZr_Int + 0U, // VFNMSUB231SSZr_Intk + 0U, // VFNMSUB231SSZr_Intkz + 0U, // VFNMSUB231SSZrb + 0U, // VFNMSUB231SSZrb_Int + 0U, // VFNMSUB231SSZrb_Intk + 0U, // VFNMSUB231SSZrb_Intkz + 0U, // VFNMSUB231SSm + 0U, // VFNMSUB231SSm_Int + 0U, // VFNMSUB231SSr + 0U, // VFNMSUB231SSr_Int + 0U, // VFNMSUBPD4Ymr + 0U, // VFNMSUBPD4Yrm + 0U, // VFNMSUBPD4Yrr + 0U, // VFNMSUBPD4Yrr_REV + 0U, // VFNMSUBPD4mr + 0U, // VFNMSUBPD4rm + 0U, // VFNMSUBPD4rr + 0U, // VFNMSUBPD4rr_REV + 0U, // VFNMSUBPS4Ymr + 0U, // VFNMSUBPS4Yrm + 0U, // VFNMSUBPS4Yrr + 0U, // VFNMSUBPS4Yrr_REV + 0U, // VFNMSUBPS4mr + 0U, // VFNMSUBPS4rm + 0U, // VFNMSUBPS4rr + 0U, // VFNMSUBPS4rr_REV + 0U, // VFNMSUBSD4mr + 0U, // VFNMSUBSD4mr_Int + 0U, // VFNMSUBSD4rm + 0U, // VFNMSUBSD4rm_Int + 0U, // VFNMSUBSD4rr + 0U, // VFNMSUBSD4rr_Int + 0U, // VFNMSUBSD4rr_Int_REV + 0U, // VFNMSUBSD4rr_REV + 0U, // VFNMSUBSS4mr + 0U, // VFNMSUBSS4mr_Int + 0U, // VFNMSUBSS4rm + 0U, // VFNMSUBSS4rm_Int + 0U, // VFNMSUBSS4rr + 0U, // VFNMSUBSS4rr_Int + 0U, // VFNMSUBSS4rr_Int_REV + 0U, // VFNMSUBSS4rr_REV + 0U, // VFPCLASSPDZ128rm + 0U, // VFPCLASSPDZ128rmb + 0U, // VFPCLASSPDZ128rmbk + 0U, // VFPCLASSPDZ128rmk + 0U, // VFPCLASSPDZ128rr + 0U, // VFPCLASSPDZ128rrk + 0U, // VFPCLASSPDZ256rm + 0U, // VFPCLASSPDZ256rmb + 0U, // VFPCLASSPDZ256rmbk + 0U, // VFPCLASSPDZ256rmk + 0U, // VFPCLASSPDZ256rr + 0U, // VFPCLASSPDZ256rrk + 0U, // VFPCLASSPDZrm + 0U, // VFPCLASSPDZrmb + 0U, // VFPCLASSPDZrmbk + 0U, // VFPCLASSPDZrmk + 0U, // VFPCLASSPDZrr + 0U, // VFPCLASSPDZrrk + 0U, // VFPCLASSPSZ128rm + 0U, // VFPCLASSPSZ128rmb + 0U, // VFPCLASSPSZ128rmbk + 0U, // VFPCLASSPSZ128rmk + 0U, // VFPCLASSPSZ128rr + 0U, // VFPCLASSPSZ128rrk + 0U, // VFPCLASSPSZ256rm + 0U, // VFPCLASSPSZ256rmb + 0U, // VFPCLASSPSZ256rmbk + 0U, // VFPCLASSPSZ256rmk + 0U, // VFPCLASSPSZ256rr + 0U, // VFPCLASSPSZ256rrk + 0U, // VFPCLASSPSZrm + 0U, // VFPCLASSPSZrmb + 0U, // VFPCLASSPSZrmbk + 0U, // VFPCLASSPSZrmk + 0U, // VFPCLASSPSZrr + 0U, // VFPCLASSPSZrrk + 0U, // VFPCLASSSDZrm + 0U, // VFPCLASSSDZrmk + 0U, // VFPCLASSSDZrr + 0U, // VFPCLASSSDZrrk + 0U, // VFPCLASSSSZrm + 0U, // VFPCLASSSSZrmk + 0U, // VFPCLASSSSZrr + 0U, // VFPCLASSSSZrrk + 0U, // VFRCZPDYrm + 0U, // VFRCZPDYrr + 0U, // VFRCZPDrm + 0U, // VFRCZPDrr + 0U, // VFRCZPSYrm + 0U, // VFRCZPSYrr + 0U, // VFRCZPSrm + 0U, // VFRCZPSrr + 0U, // VFRCZSDrm + 0U, // VFRCZSDrr + 0U, // VFRCZSSrm + 0U, // VFRCZSSrr + 0U, // VGATHERDPDYrm + 0U, // VGATHERDPDZ128rm + 0U, // VGATHERDPDZ256rm + 0U, // VGATHERDPDZrm + 0U, // VGATHERDPDrm + 0U, // VGATHERDPSYrm + 0U, // VGATHERDPSZ128rm + 0U, // VGATHERDPSZ256rm + 0U, // VGATHERDPSZrm + 0U, // VGATHERDPSrm + 0U, // VGATHERPF0DPDm + 0U, // VGATHERPF0DPSm + 0U, // VGATHERPF0QPDm + 0U, // VGATHERPF0QPSm + 0U, // VGATHERPF1DPDm + 0U, // VGATHERPF1DPSm + 0U, // VGATHERPF1QPDm + 0U, // VGATHERPF1QPSm + 0U, // VGATHERQPDYrm + 0U, // VGATHERQPDZ128rm + 0U, // VGATHERQPDZ256rm + 0U, // VGATHERQPDZrm + 0U, // VGATHERQPDrm + 0U, // VGATHERQPSYrm + 0U, // VGATHERQPSZ128rm + 0U, // VGATHERQPSZ256rm + 0U, // VGATHERQPSZrm + 0U, // VGATHERQPSrm + 0U, // VGETEXPPDZ128m + 0U, // VGETEXPPDZ128mb + 0U, // VGETEXPPDZ128mbk + 0U, // VGETEXPPDZ128mbkz + 0U, // VGETEXPPDZ128mk + 0U, // VGETEXPPDZ128mkz + 0U, // VGETEXPPDZ128r + 0U, // VGETEXPPDZ128rk + 0U, // VGETEXPPDZ128rkz + 0U, // VGETEXPPDZ256m + 0U, // VGETEXPPDZ256mb + 0U, // VGETEXPPDZ256mbk + 0U, // VGETEXPPDZ256mbkz + 0U, // VGETEXPPDZ256mk + 0U, // VGETEXPPDZ256mkz + 0U, // VGETEXPPDZ256r + 0U, // VGETEXPPDZ256rk + 0U, // VGETEXPPDZ256rkz + 0U, // VGETEXPPDZm + 0U, // VGETEXPPDZmb + 0U, // VGETEXPPDZmbk + 0U, // VGETEXPPDZmbkz + 0U, // VGETEXPPDZmk + 0U, // VGETEXPPDZmkz + 0U, // VGETEXPPDZr + 0U, // VGETEXPPDZrb + 0U, // VGETEXPPDZrbk + 0U, // VGETEXPPDZrbkz + 0U, // VGETEXPPDZrk + 0U, // VGETEXPPDZrkz + 0U, // VGETEXPPSZ128m + 0U, // VGETEXPPSZ128mb + 0U, // VGETEXPPSZ128mbk + 0U, // VGETEXPPSZ128mbkz + 0U, // VGETEXPPSZ128mk + 0U, // VGETEXPPSZ128mkz + 0U, // VGETEXPPSZ128r + 0U, // VGETEXPPSZ128rk + 0U, // VGETEXPPSZ128rkz + 0U, // VGETEXPPSZ256m + 0U, // VGETEXPPSZ256mb + 0U, // VGETEXPPSZ256mbk + 0U, // VGETEXPPSZ256mbkz + 0U, // VGETEXPPSZ256mk + 0U, // VGETEXPPSZ256mkz + 0U, // VGETEXPPSZ256r + 0U, // VGETEXPPSZ256rk + 0U, // VGETEXPPSZ256rkz + 0U, // VGETEXPPSZm + 0U, // VGETEXPPSZmb + 0U, // VGETEXPPSZmbk + 0U, // VGETEXPPSZmbkz + 0U, // VGETEXPPSZmk + 0U, // VGETEXPPSZmkz + 0U, // VGETEXPPSZr + 0U, // VGETEXPPSZrb + 0U, // VGETEXPPSZrbk + 0U, // VGETEXPPSZrbkz + 0U, // VGETEXPPSZrk + 0U, // VGETEXPPSZrkz + 0U, // VGETEXPSDZm + 0U, // VGETEXPSDZmk + 0U, // VGETEXPSDZmkz + 0U, // VGETEXPSDZr + 0U, // VGETEXPSDZrb + 0U, // VGETEXPSDZrbk + 0U, // VGETEXPSDZrbkz + 0U, // VGETEXPSDZrk + 0U, // VGETEXPSDZrkz + 0U, // VGETEXPSSZm + 0U, // VGETEXPSSZmk + 0U, // VGETEXPSSZmkz + 0U, // VGETEXPSSZr + 0U, // VGETEXPSSZrb + 0U, // VGETEXPSSZrbk + 0U, // VGETEXPSSZrbkz + 0U, // VGETEXPSSZrk + 0U, // VGETEXPSSZrkz + 0U, // VGETMANTPDZ128rmbi + 0U, // VGETMANTPDZ128rmbik + 0U, // VGETMANTPDZ128rmbikz + 0U, // VGETMANTPDZ128rmi + 0U, // VGETMANTPDZ128rmik + 0U, // VGETMANTPDZ128rmikz + 0U, // VGETMANTPDZ128rri + 0U, // VGETMANTPDZ128rrik + 0U, // VGETMANTPDZ128rrikz + 0U, // VGETMANTPDZ256rmbi + 0U, // VGETMANTPDZ256rmbik + 0U, // VGETMANTPDZ256rmbikz + 0U, // VGETMANTPDZ256rmi + 0U, // VGETMANTPDZ256rmik + 0U, // VGETMANTPDZ256rmikz + 0U, // VGETMANTPDZ256rri + 0U, // VGETMANTPDZ256rrik + 0U, // VGETMANTPDZ256rrikz + 0U, // VGETMANTPDZrmbi + 0U, // VGETMANTPDZrmbik + 0U, // VGETMANTPDZrmbikz + 0U, // VGETMANTPDZrmi + 0U, // VGETMANTPDZrmik + 0U, // VGETMANTPDZrmikz + 0U, // VGETMANTPDZrri + 0U, // VGETMANTPDZrrib + 0U, // VGETMANTPDZrribk + 0U, // VGETMANTPDZrribkz + 0U, // VGETMANTPDZrrik + 0U, // VGETMANTPDZrrikz + 0U, // VGETMANTPSZ128rmbi + 0U, // VGETMANTPSZ128rmbik + 0U, // VGETMANTPSZ128rmbikz + 0U, // VGETMANTPSZ128rmi + 0U, // VGETMANTPSZ128rmik + 0U, // VGETMANTPSZ128rmikz + 0U, // VGETMANTPSZ128rri + 0U, // VGETMANTPSZ128rrik + 0U, // VGETMANTPSZ128rrikz + 0U, // VGETMANTPSZ256rmbi + 0U, // VGETMANTPSZ256rmbik + 0U, // VGETMANTPSZ256rmbikz + 0U, // VGETMANTPSZ256rmi + 0U, // VGETMANTPSZ256rmik + 0U, // VGETMANTPSZ256rmikz + 0U, // VGETMANTPSZ256rri + 0U, // VGETMANTPSZ256rrik + 0U, // VGETMANTPSZ256rrikz + 0U, // VGETMANTPSZrmbi + 0U, // VGETMANTPSZrmbik + 0U, // VGETMANTPSZrmbikz + 0U, // VGETMANTPSZrmi + 0U, // VGETMANTPSZrmik + 0U, // VGETMANTPSZrmikz + 0U, // VGETMANTPSZrri + 0U, // VGETMANTPSZrrib + 0U, // VGETMANTPSZrribk + 0U, // VGETMANTPSZrribkz + 0U, // VGETMANTPSZrrik + 0U, // VGETMANTPSZrrikz + 0U, // VGETMANTSDZrmi + 0U, // VGETMANTSDZrmik + 3U, // VGETMANTSDZrmikz + 0U, // VGETMANTSDZrri + 0U, // VGETMANTSDZrrib + 0U, // VGETMANTSDZrribk + 3U, // VGETMANTSDZrribkz + 0U, // VGETMANTSDZrrik + 3U, // VGETMANTSDZrrikz + 0U, // VGETMANTSSZrmi + 0U, // VGETMANTSSZrmik + 3U, // VGETMANTSSZrmikz + 0U, // VGETMANTSSZrri + 0U, // VGETMANTSSZrrib + 0U, // VGETMANTSSZrribk + 3U, // VGETMANTSSZrribkz + 0U, // VGETMANTSSZrrik + 3U, // VGETMANTSSZrrikz + 0U, // VGF2P8AFFINEINVQBYrmi + 0U, // VGF2P8AFFINEINVQBYrri + 0U, // VGF2P8AFFINEINVQBZ128rmbi + 0U, // VGF2P8AFFINEINVQBZ128rmbik + 3U, // VGF2P8AFFINEINVQBZ128rmbikz + 0U, // VGF2P8AFFINEINVQBZ128rmi + 0U, // VGF2P8AFFINEINVQBZ128rmik + 0U, // VGF2P8AFFINEINVQBZ128rmikz + 0U, // VGF2P8AFFINEINVQBZ128rri + 0U, // VGF2P8AFFINEINVQBZ128rrik + 3U, // VGF2P8AFFINEINVQBZ128rrikz + 0U, // VGF2P8AFFINEINVQBZ256rmbi + 0U, // VGF2P8AFFINEINVQBZ256rmbik + 3U, // VGF2P8AFFINEINVQBZ256rmbikz + 0U, // VGF2P8AFFINEINVQBZ256rmi + 0U, // VGF2P8AFFINEINVQBZ256rmik + 0U, // VGF2P8AFFINEINVQBZ256rmikz + 0U, // VGF2P8AFFINEINVQBZ256rri + 0U, // VGF2P8AFFINEINVQBZ256rrik + 3U, // VGF2P8AFFINEINVQBZ256rrikz + 0U, // VGF2P8AFFINEINVQBZrmbi + 0U, // VGF2P8AFFINEINVQBZrmbik + 3U, // VGF2P8AFFINEINVQBZrmbikz + 0U, // VGF2P8AFFINEINVQBZrmi + 0U, // VGF2P8AFFINEINVQBZrmik + 0U, // VGF2P8AFFINEINVQBZrmikz + 0U, // VGF2P8AFFINEINVQBZrri + 0U, // VGF2P8AFFINEINVQBZrrik + 3U, // VGF2P8AFFINEINVQBZrrikz + 0U, // VGF2P8AFFINEINVQBrmi + 0U, // VGF2P8AFFINEINVQBrri + 0U, // VGF2P8AFFINEQBYrmi + 0U, // VGF2P8AFFINEQBYrri + 0U, // VGF2P8AFFINEQBZ128rmbi + 0U, // VGF2P8AFFINEQBZ128rmbik + 3U, // VGF2P8AFFINEQBZ128rmbikz + 0U, // VGF2P8AFFINEQBZ128rmi + 0U, // VGF2P8AFFINEQBZ128rmik + 0U, // VGF2P8AFFINEQBZ128rmikz + 0U, // VGF2P8AFFINEQBZ128rri + 0U, // VGF2P8AFFINEQBZ128rrik + 3U, // VGF2P8AFFINEQBZ128rrikz + 0U, // VGF2P8AFFINEQBZ256rmbi + 0U, // VGF2P8AFFINEQBZ256rmbik + 3U, // VGF2P8AFFINEQBZ256rmbikz + 0U, // VGF2P8AFFINEQBZ256rmi + 0U, // VGF2P8AFFINEQBZ256rmik + 0U, // VGF2P8AFFINEQBZ256rmikz + 0U, // VGF2P8AFFINEQBZ256rri + 0U, // VGF2P8AFFINEQBZ256rrik + 3U, // VGF2P8AFFINEQBZ256rrikz + 0U, // VGF2P8AFFINEQBZrmbi + 0U, // VGF2P8AFFINEQBZrmbik + 3U, // VGF2P8AFFINEQBZrmbikz + 0U, // VGF2P8AFFINEQBZrmi + 0U, // VGF2P8AFFINEQBZrmik + 0U, // VGF2P8AFFINEQBZrmikz + 0U, // VGF2P8AFFINEQBZrri + 0U, // VGF2P8AFFINEQBZrrik + 3U, // VGF2P8AFFINEQBZrrikz + 0U, // VGF2P8AFFINEQBrmi + 0U, // VGF2P8AFFINEQBrri + 0U, // VGF2P8MULBYrm + 0U, // VGF2P8MULBYrr + 0U, // VGF2P8MULBZ128rm + 0U, // VGF2P8MULBZ128rmk + 0U, // VGF2P8MULBZ128rmkz + 0U, // VGF2P8MULBZ128rr + 0U, // VGF2P8MULBZ128rrk + 0U, // VGF2P8MULBZ128rrkz + 0U, // VGF2P8MULBZ256rm + 0U, // VGF2P8MULBZ256rmk + 0U, // VGF2P8MULBZ256rmkz + 0U, // VGF2P8MULBZ256rr + 0U, // VGF2P8MULBZ256rrk + 0U, // VGF2P8MULBZ256rrkz + 0U, // VGF2P8MULBZrm + 0U, // VGF2P8MULBZrmk + 0U, // VGF2P8MULBZrmkz + 0U, // VGF2P8MULBZrr + 0U, // VGF2P8MULBZrrk + 0U, // VGF2P8MULBZrrkz + 0U, // VGF2P8MULBrm + 0U, // VGF2P8MULBrr + 0U, // VHADDPDYrm + 0U, // VHADDPDYrr + 0U, // VHADDPDrm + 0U, // VHADDPDrr + 0U, // VHADDPSYrm + 0U, // VHADDPSYrr + 0U, // VHADDPSrm + 0U, // VHADDPSrr + 0U, // VHSUBPDYrm + 0U, // VHSUBPDYrr + 0U, // VHSUBPDrm + 0U, // VHSUBPDrr + 0U, // VHSUBPSYrm + 0U, // VHSUBPSYrr + 0U, // VHSUBPSrm + 0U, // VHSUBPSrr + 0U, // VINSERTF128rm + 0U, // VINSERTF128rr + 0U, // VINSERTF32x4Z256rm + 0U, // VINSERTF32x4Z256rmk + 0U, // VINSERTF32x4Z256rmkz + 0U, // VINSERTF32x4Z256rr + 0U, // VINSERTF32x4Z256rrk + 3U, // VINSERTF32x4Z256rrkz + 0U, // VINSERTF32x4Zrm + 0U, // VINSERTF32x4Zrmk + 0U, // VINSERTF32x4Zrmkz + 0U, // VINSERTF32x4Zrr + 0U, // VINSERTF32x4Zrrk + 3U, // VINSERTF32x4Zrrkz + 0U, // VINSERTF32x8Zrm + 0U, // VINSERTF32x8Zrmk + 0U, // VINSERTF32x8Zrmkz + 0U, // VINSERTF32x8Zrr + 0U, // VINSERTF32x8Zrrk + 3U, // VINSERTF32x8Zrrkz + 0U, // VINSERTF64x2Z256rm + 0U, // VINSERTF64x2Z256rmk + 0U, // VINSERTF64x2Z256rmkz + 0U, // VINSERTF64x2Z256rr + 0U, // VINSERTF64x2Z256rrk + 3U, // VINSERTF64x2Z256rrkz + 0U, // VINSERTF64x2Zrm + 0U, // VINSERTF64x2Zrmk + 0U, // VINSERTF64x2Zrmkz + 0U, // VINSERTF64x2Zrr + 0U, // VINSERTF64x2Zrrk + 3U, // VINSERTF64x2Zrrkz + 0U, // VINSERTF64x4Zrm + 0U, // VINSERTF64x4Zrmk + 0U, // VINSERTF64x4Zrmkz + 0U, // VINSERTF64x4Zrr + 0U, // VINSERTF64x4Zrrk + 3U, // VINSERTF64x4Zrrkz + 0U, // VINSERTI128rm + 0U, // VINSERTI128rr + 0U, // VINSERTI32x4Z256rm + 0U, // VINSERTI32x4Z256rmk + 0U, // VINSERTI32x4Z256rmkz + 0U, // VINSERTI32x4Z256rr + 0U, // VINSERTI32x4Z256rrk + 3U, // VINSERTI32x4Z256rrkz + 0U, // VINSERTI32x4Zrm + 0U, // VINSERTI32x4Zrmk + 0U, // VINSERTI32x4Zrmkz + 0U, // VINSERTI32x4Zrr + 0U, // VINSERTI32x4Zrrk + 3U, // VINSERTI32x4Zrrkz + 0U, // VINSERTI32x8Zrm + 0U, // VINSERTI32x8Zrmk + 0U, // VINSERTI32x8Zrmkz + 0U, // VINSERTI32x8Zrr + 0U, // VINSERTI32x8Zrrk + 3U, // VINSERTI32x8Zrrkz + 0U, // VINSERTI64x2Z256rm + 0U, // VINSERTI64x2Z256rmk + 0U, // VINSERTI64x2Z256rmkz + 0U, // VINSERTI64x2Z256rr + 0U, // VINSERTI64x2Z256rrk + 3U, // VINSERTI64x2Z256rrkz + 0U, // VINSERTI64x2Zrm + 0U, // VINSERTI64x2Zrmk + 0U, // VINSERTI64x2Zrmkz + 0U, // VINSERTI64x2Zrr + 0U, // VINSERTI64x2Zrrk + 3U, // VINSERTI64x2Zrrkz + 0U, // VINSERTI64x4Zrm + 0U, // VINSERTI64x4Zrmk + 0U, // VINSERTI64x4Zrmkz + 0U, // VINSERTI64x4Zrr + 0U, // VINSERTI64x4Zrrk + 3U, // VINSERTI64x4Zrrkz + 0U, // VINSERTPSZrm + 0U, // VINSERTPSZrr + 0U, // VINSERTPSrm + 0U, // VINSERTPSrr + 0U, // VLDDQUYrm + 0U, // VLDDQUrm + 0U, // VLDMXCSR + 0U, // VMASKMOVDQU + 0U, // VMASKMOVDQU64 + 0U, // VMASKMOVPDYmr + 0U, // VMASKMOVPDYrm + 0U, // VMASKMOVPDmr + 0U, // VMASKMOVPDrm + 0U, // VMASKMOVPSYmr + 0U, // VMASKMOVPSYrm + 0U, // VMASKMOVPSmr + 0U, // VMASKMOVPSrm + 0U, // VMAXCPDYrm + 0U, // VMAXCPDYrr + 0U, // VMAXCPDZ128rm + 0U, // VMAXCPDZ128rmb + 0U, // VMAXCPDZ128rmbk + 0U, // VMAXCPDZ128rmbkz + 0U, // VMAXCPDZ128rmk + 0U, // VMAXCPDZ128rmkz + 0U, // VMAXCPDZ128rr + 0U, // VMAXCPDZ128rrk + 0U, // VMAXCPDZ128rrkz + 0U, // VMAXCPDZ256rm + 0U, // VMAXCPDZ256rmb + 0U, // VMAXCPDZ256rmbk + 0U, // VMAXCPDZ256rmbkz + 0U, // VMAXCPDZ256rmk + 0U, // VMAXCPDZ256rmkz + 0U, // VMAXCPDZ256rr + 0U, // VMAXCPDZ256rrk + 0U, // VMAXCPDZ256rrkz + 0U, // VMAXCPDZrm + 0U, // VMAXCPDZrmb + 0U, // VMAXCPDZrmbk + 0U, // VMAXCPDZrmbkz + 0U, // VMAXCPDZrmk + 0U, // VMAXCPDZrmkz + 0U, // VMAXCPDZrr + 0U, // VMAXCPDZrrk + 0U, // VMAXCPDZrrkz + 0U, // VMAXCPDrm + 0U, // VMAXCPDrr + 0U, // VMAXCPSYrm + 0U, // VMAXCPSYrr + 0U, // VMAXCPSZ128rm + 0U, // VMAXCPSZ128rmb + 0U, // VMAXCPSZ128rmbk + 0U, // VMAXCPSZ128rmbkz + 0U, // VMAXCPSZ128rmk + 0U, // VMAXCPSZ128rmkz + 0U, // VMAXCPSZ128rr + 0U, // VMAXCPSZ128rrk + 0U, // VMAXCPSZ128rrkz + 0U, // VMAXCPSZ256rm + 0U, // VMAXCPSZ256rmb + 0U, // VMAXCPSZ256rmbk + 0U, // VMAXCPSZ256rmbkz + 0U, // VMAXCPSZ256rmk + 0U, // VMAXCPSZ256rmkz + 0U, // VMAXCPSZ256rr + 0U, // VMAXCPSZ256rrk + 0U, // VMAXCPSZ256rrkz + 0U, // VMAXCPSZrm + 0U, // VMAXCPSZrmb + 0U, // VMAXCPSZrmbk + 0U, // VMAXCPSZrmbkz + 0U, // VMAXCPSZrmk + 0U, // VMAXCPSZrmkz + 0U, // VMAXCPSZrr + 0U, // VMAXCPSZrrk + 0U, // VMAXCPSZrrkz + 0U, // VMAXCPSrm + 0U, // VMAXCPSrr + 0U, // VMAXCSDZrm + 0U, // VMAXCSDZrr + 0U, // VMAXCSDrm + 0U, // VMAXCSDrr + 0U, // VMAXCSSZrm + 0U, // VMAXCSSZrr + 0U, // VMAXCSSrm + 0U, // VMAXCSSrr + 0U, // VMAXPDYrm + 0U, // VMAXPDYrr + 0U, // VMAXPDZ128rm + 0U, // VMAXPDZ128rmb + 0U, // VMAXPDZ128rmbk + 0U, // VMAXPDZ128rmbkz + 0U, // VMAXPDZ128rmk + 0U, // VMAXPDZ128rmkz + 0U, // VMAXPDZ128rr + 0U, // VMAXPDZ128rrk + 0U, // VMAXPDZ128rrkz + 0U, // VMAXPDZ256rm + 0U, // VMAXPDZ256rmb + 0U, // VMAXPDZ256rmbk + 0U, // VMAXPDZ256rmbkz + 0U, // VMAXPDZ256rmk + 0U, // VMAXPDZ256rmkz + 0U, // VMAXPDZ256rr + 0U, // VMAXPDZ256rrk + 0U, // VMAXPDZ256rrkz + 0U, // VMAXPDZrm + 0U, // VMAXPDZrmb + 0U, // VMAXPDZrmbk + 0U, // VMAXPDZrmbkz + 0U, // VMAXPDZrmk + 0U, // VMAXPDZrmkz + 0U, // VMAXPDZrr + 0U, // VMAXPDZrrb + 0U, // VMAXPDZrrbk + 0U, // VMAXPDZrrbkz + 0U, // VMAXPDZrrk + 0U, // VMAXPDZrrkz + 0U, // VMAXPDrm + 0U, // VMAXPDrr + 0U, // VMAXPSYrm + 0U, // VMAXPSYrr + 0U, // VMAXPSZ128rm + 0U, // VMAXPSZ128rmb + 0U, // VMAXPSZ128rmbk + 0U, // VMAXPSZ128rmbkz + 0U, // VMAXPSZ128rmk + 0U, // VMAXPSZ128rmkz + 0U, // VMAXPSZ128rr + 0U, // VMAXPSZ128rrk + 0U, // VMAXPSZ128rrkz + 0U, // VMAXPSZ256rm + 0U, // VMAXPSZ256rmb + 0U, // VMAXPSZ256rmbk + 0U, // VMAXPSZ256rmbkz + 0U, // VMAXPSZ256rmk + 0U, // VMAXPSZ256rmkz + 0U, // VMAXPSZ256rr + 0U, // VMAXPSZ256rrk + 0U, // VMAXPSZ256rrkz + 0U, // VMAXPSZrm + 0U, // VMAXPSZrmb + 0U, // VMAXPSZrmbk + 0U, // VMAXPSZrmbkz + 0U, // VMAXPSZrmk + 0U, // VMAXPSZrmkz + 0U, // VMAXPSZrr + 0U, // VMAXPSZrrb + 0U, // VMAXPSZrrbk + 0U, // VMAXPSZrrbkz + 0U, // VMAXPSZrrk + 0U, // VMAXPSZrrkz + 0U, // VMAXPSrm + 0U, // VMAXPSrr + 0U, // VMAXSDZrm + 0U, // VMAXSDZrm_Int + 0U, // VMAXSDZrm_Intk + 0U, // VMAXSDZrm_Intkz + 0U, // VMAXSDZrr + 0U, // VMAXSDZrr_Int + 0U, // VMAXSDZrr_Intk + 0U, // VMAXSDZrr_Intkz + 0U, // VMAXSDZrrb_Int + 0U, // VMAXSDZrrb_Intk + 0U, // VMAXSDZrrb_Intkz + 0U, // VMAXSDrm + 0U, // VMAXSDrm_Int + 0U, // VMAXSDrr + 0U, // VMAXSDrr_Int + 0U, // VMAXSSZrm + 0U, // VMAXSSZrm_Int + 0U, // VMAXSSZrm_Intk + 0U, // VMAXSSZrm_Intkz + 0U, // VMAXSSZrr + 0U, // VMAXSSZrr_Int + 0U, // VMAXSSZrr_Intk + 0U, // VMAXSSZrr_Intkz + 0U, // VMAXSSZrrb_Int + 0U, // VMAXSSZrrb_Intk + 0U, // VMAXSSZrrb_Intkz + 0U, // VMAXSSrm + 0U, // VMAXSSrm_Int + 0U, // VMAXSSrr + 0U, // VMAXSSrr_Int + 0U, // VMCALL + 0U, // VMCLEARm + 0U, // VMFUNC + 0U, // VMINCPDYrm + 0U, // VMINCPDYrr + 0U, // VMINCPDZ128rm + 0U, // VMINCPDZ128rmb + 0U, // VMINCPDZ128rmbk + 0U, // VMINCPDZ128rmbkz + 0U, // VMINCPDZ128rmk + 0U, // VMINCPDZ128rmkz + 0U, // VMINCPDZ128rr + 0U, // VMINCPDZ128rrk + 0U, // VMINCPDZ128rrkz + 0U, // VMINCPDZ256rm + 0U, // VMINCPDZ256rmb + 0U, // VMINCPDZ256rmbk + 0U, // VMINCPDZ256rmbkz + 0U, // VMINCPDZ256rmk + 0U, // VMINCPDZ256rmkz + 0U, // VMINCPDZ256rr + 0U, // VMINCPDZ256rrk + 0U, // VMINCPDZ256rrkz + 0U, // VMINCPDZrm + 0U, // VMINCPDZrmb + 0U, // VMINCPDZrmbk + 0U, // VMINCPDZrmbkz + 0U, // VMINCPDZrmk + 0U, // VMINCPDZrmkz + 0U, // VMINCPDZrr + 0U, // VMINCPDZrrk + 0U, // VMINCPDZrrkz + 0U, // VMINCPDrm + 0U, // VMINCPDrr + 0U, // VMINCPSYrm + 0U, // VMINCPSYrr + 0U, // VMINCPSZ128rm + 0U, // VMINCPSZ128rmb + 0U, // VMINCPSZ128rmbk + 0U, // VMINCPSZ128rmbkz + 0U, // VMINCPSZ128rmk + 0U, // VMINCPSZ128rmkz + 0U, // VMINCPSZ128rr + 0U, // VMINCPSZ128rrk + 0U, // VMINCPSZ128rrkz + 0U, // VMINCPSZ256rm + 0U, // VMINCPSZ256rmb + 0U, // VMINCPSZ256rmbk + 0U, // VMINCPSZ256rmbkz + 0U, // VMINCPSZ256rmk + 0U, // VMINCPSZ256rmkz + 0U, // VMINCPSZ256rr + 0U, // VMINCPSZ256rrk + 0U, // VMINCPSZ256rrkz + 0U, // VMINCPSZrm + 0U, // VMINCPSZrmb + 0U, // VMINCPSZrmbk + 0U, // VMINCPSZrmbkz + 0U, // VMINCPSZrmk + 0U, // VMINCPSZrmkz + 0U, // VMINCPSZrr + 0U, // VMINCPSZrrk + 0U, // VMINCPSZrrkz + 0U, // VMINCPSrm + 0U, // VMINCPSrr + 0U, // VMINCSDZrm + 0U, // VMINCSDZrr + 0U, // VMINCSDrm + 0U, // VMINCSDrr + 0U, // VMINCSSZrm + 0U, // VMINCSSZrr + 0U, // VMINCSSrm + 0U, // VMINCSSrr + 0U, // VMINPDYrm + 0U, // VMINPDYrr + 0U, // VMINPDZ128rm + 0U, // VMINPDZ128rmb + 0U, // VMINPDZ128rmbk + 0U, // VMINPDZ128rmbkz + 0U, // VMINPDZ128rmk + 0U, // VMINPDZ128rmkz + 0U, // VMINPDZ128rr + 0U, // VMINPDZ128rrk + 0U, // VMINPDZ128rrkz + 0U, // VMINPDZ256rm + 0U, // VMINPDZ256rmb + 0U, // VMINPDZ256rmbk + 0U, // VMINPDZ256rmbkz + 0U, // VMINPDZ256rmk + 0U, // VMINPDZ256rmkz + 0U, // VMINPDZ256rr + 0U, // VMINPDZ256rrk + 0U, // VMINPDZ256rrkz + 0U, // VMINPDZrm + 0U, // VMINPDZrmb + 0U, // VMINPDZrmbk + 0U, // VMINPDZrmbkz + 0U, // VMINPDZrmk + 0U, // VMINPDZrmkz + 0U, // VMINPDZrr + 0U, // VMINPDZrrb + 0U, // VMINPDZrrbk + 0U, // VMINPDZrrbkz + 0U, // VMINPDZrrk + 0U, // VMINPDZrrkz + 0U, // VMINPDrm + 0U, // VMINPDrr + 0U, // VMINPSYrm + 0U, // VMINPSYrr + 0U, // VMINPSZ128rm + 0U, // VMINPSZ128rmb + 0U, // VMINPSZ128rmbk + 0U, // VMINPSZ128rmbkz + 0U, // VMINPSZ128rmk + 0U, // VMINPSZ128rmkz + 0U, // VMINPSZ128rr + 0U, // VMINPSZ128rrk + 0U, // VMINPSZ128rrkz + 0U, // VMINPSZ256rm + 0U, // VMINPSZ256rmb + 0U, // VMINPSZ256rmbk + 0U, // VMINPSZ256rmbkz + 0U, // VMINPSZ256rmk + 0U, // VMINPSZ256rmkz + 0U, // VMINPSZ256rr + 0U, // VMINPSZ256rrk + 0U, // VMINPSZ256rrkz + 0U, // VMINPSZrm + 0U, // VMINPSZrmb + 0U, // VMINPSZrmbk + 0U, // VMINPSZrmbkz + 0U, // VMINPSZrmk + 0U, // VMINPSZrmkz + 0U, // VMINPSZrr + 0U, // VMINPSZrrb + 0U, // VMINPSZrrbk + 0U, // VMINPSZrrbkz + 0U, // VMINPSZrrk + 0U, // VMINPSZrrkz + 0U, // VMINPSrm + 0U, // VMINPSrr + 0U, // VMINSDZrm + 0U, // VMINSDZrm_Int + 0U, // VMINSDZrm_Intk + 0U, // VMINSDZrm_Intkz + 0U, // VMINSDZrr + 0U, // VMINSDZrr_Int + 0U, // VMINSDZrr_Intk + 0U, // VMINSDZrr_Intkz + 0U, // VMINSDZrrb_Int + 0U, // VMINSDZrrb_Intk + 0U, // VMINSDZrrb_Intkz + 0U, // VMINSDrm + 0U, // VMINSDrm_Int + 0U, // VMINSDrr + 0U, // VMINSDrr_Int + 0U, // VMINSSZrm + 0U, // VMINSSZrm_Int + 0U, // VMINSSZrm_Intk + 0U, // VMINSSZrm_Intkz + 0U, // VMINSSZrr + 0U, // VMINSSZrr_Int + 0U, // VMINSSZrr_Intk + 0U, // VMINSSZrr_Intkz + 0U, // VMINSSZrrb_Int + 0U, // VMINSSZrrb_Intk + 0U, // VMINSSZrrb_Intkz + 0U, // VMINSSrm + 0U, // VMINSSrm_Int + 0U, // VMINSSrr + 0U, // VMINSSrr_Int + 0U, // VMLAUNCH + 0U, // VMLOAD32 + 0U, // VMLOAD64 + 0U, // VMMCALL + 0U, // VMOV64toPQIZrm + 0U, // VMOV64toPQIZrr + 0U, // VMOV64toPQIrm + 0U, // VMOV64toPQIrr + 0U, // VMOV64toSDZrm + 0U, // VMOV64toSDZrr + 0U, // VMOV64toSDrm + 0U, // VMOV64toSDrr + 0U, // VMOVAPDYmr + 0U, // VMOVAPDYrm + 0U, // VMOVAPDYrr + 0U, // VMOVAPDYrr_REV + 0U, // VMOVAPDZ128mr + 0U, // VMOVAPDZ128mrk + 0U, // VMOVAPDZ128rm + 0U, // VMOVAPDZ128rmk + 0U, // VMOVAPDZ128rmkz + 0U, // VMOVAPDZ128rr + 0U, // VMOVAPDZ128rr_REV + 0U, // VMOVAPDZ128rrk + 0U, // VMOVAPDZ128rrk_REV + 0U, // VMOVAPDZ128rrkz + 0U, // VMOVAPDZ128rrkz_REV + 0U, // VMOVAPDZ256mr + 0U, // VMOVAPDZ256mrk + 0U, // VMOVAPDZ256rm + 0U, // VMOVAPDZ256rmk + 0U, // VMOVAPDZ256rmkz + 0U, // VMOVAPDZ256rr + 0U, // VMOVAPDZ256rr_REV + 0U, // VMOVAPDZ256rrk + 0U, // VMOVAPDZ256rrk_REV + 0U, // VMOVAPDZ256rrkz + 0U, // VMOVAPDZ256rrkz_REV + 0U, // VMOVAPDZmr + 0U, // VMOVAPDZmrk + 0U, // VMOVAPDZrm + 0U, // VMOVAPDZrmk + 0U, // VMOVAPDZrmkz + 0U, // VMOVAPDZrr + 0U, // VMOVAPDZrr_REV + 0U, // VMOVAPDZrrk + 0U, // VMOVAPDZrrk_REV + 0U, // VMOVAPDZrrkz + 0U, // VMOVAPDZrrkz_REV + 0U, // VMOVAPDmr + 0U, // VMOVAPDrm + 0U, // VMOVAPDrr + 0U, // VMOVAPDrr_REV + 0U, // VMOVAPSYmr + 0U, // VMOVAPSYrm + 0U, // VMOVAPSYrr + 0U, // VMOVAPSYrr_REV + 0U, // VMOVAPSZ128mr + 0U, // VMOVAPSZ128mrk + 0U, // VMOVAPSZ128rm + 0U, // VMOVAPSZ128rmk + 0U, // VMOVAPSZ128rmkz + 0U, // VMOVAPSZ128rr + 0U, // VMOVAPSZ128rr_REV + 0U, // VMOVAPSZ128rrk + 0U, // VMOVAPSZ128rrk_REV + 0U, // VMOVAPSZ128rrkz + 0U, // VMOVAPSZ128rrkz_REV + 0U, // VMOVAPSZ256mr + 0U, // VMOVAPSZ256mrk + 0U, // VMOVAPSZ256rm + 0U, // VMOVAPSZ256rmk + 0U, // VMOVAPSZ256rmkz + 0U, // VMOVAPSZ256rr + 0U, // VMOVAPSZ256rr_REV + 0U, // VMOVAPSZ256rrk + 0U, // VMOVAPSZ256rrk_REV + 0U, // VMOVAPSZ256rrkz + 0U, // VMOVAPSZ256rrkz_REV + 0U, // VMOVAPSZmr + 0U, // VMOVAPSZmrk + 0U, // VMOVAPSZrm + 0U, // VMOVAPSZrmk + 0U, // VMOVAPSZrmkz + 0U, // VMOVAPSZrr + 0U, // VMOVAPSZrr_REV + 0U, // VMOVAPSZrrk + 0U, // VMOVAPSZrrk_REV + 0U, // VMOVAPSZrrkz + 0U, // VMOVAPSZrrkz_REV + 0U, // VMOVAPSmr + 0U, // VMOVAPSrm + 0U, // VMOVAPSrr + 0U, // VMOVAPSrr_REV + 0U, // VMOVDDUPYrm + 0U, // VMOVDDUPYrr + 0U, // VMOVDDUPZ128rm + 0U, // VMOVDDUPZ128rmk + 0U, // VMOVDDUPZ128rmkz + 0U, // VMOVDDUPZ128rr + 0U, // VMOVDDUPZ128rrk + 0U, // VMOVDDUPZ128rrkz + 0U, // VMOVDDUPZ256rm + 0U, // VMOVDDUPZ256rmk + 0U, // VMOVDDUPZ256rmkz + 0U, // VMOVDDUPZ256rr + 0U, // VMOVDDUPZ256rrk + 0U, // VMOVDDUPZ256rrkz + 0U, // VMOVDDUPZrm + 0U, // VMOVDDUPZrmk + 0U, // VMOVDDUPZrmkz + 0U, // VMOVDDUPZrr + 0U, // VMOVDDUPZrrk + 0U, // VMOVDDUPZrrkz + 0U, // VMOVDDUPrm + 0U, // VMOVDDUPrr + 0U, // VMOVDI2PDIZrm + 0U, // VMOVDI2PDIZrr + 0U, // VMOVDI2PDIrm + 0U, // VMOVDI2PDIrr + 0U, // VMOVDI2SSZrm + 0U, // VMOVDI2SSZrr + 0U, // VMOVDI2SSrm + 0U, // VMOVDI2SSrr + 0U, // VMOVDQA32Z128mr + 0U, // VMOVDQA32Z128mrk + 0U, // VMOVDQA32Z128rm + 0U, // VMOVDQA32Z128rmk + 0U, // VMOVDQA32Z128rmkz + 0U, // VMOVDQA32Z128rr + 0U, // VMOVDQA32Z128rr_REV + 0U, // VMOVDQA32Z128rrk + 0U, // VMOVDQA32Z128rrk_REV + 0U, // VMOVDQA32Z128rrkz + 0U, // VMOVDQA32Z128rrkz_REV + 0U, // VMOVDQA32Z256mr + 0U, // VMOVDQA32Z256mrk + 0U, // VMOVDQA32Z256rm + 0U, // VMOVDQA32Z256rmk + 0U, // VMOVDQA32Z256rmkz + 0U, // VMOVDQA32Z256rr + 0U, // VMOVDQA32Z256rr_REV + 0U, // VMOVDQA32Z256rrk + 0U, // VMOVDQA32Z256rrk_REV + 0U, // VMOVDQA32Z256rrkz + 0U, // VMOVDQA32Z256rrkz_REV + 0U, // VMOVDQA32Zmr + 0U, // VMOVDQA32Zmrk + 0U, // VMOVDQA32Zrm + 0U, // VMOVDQA32Zrmk + 0U, // VMOVDQA32Zrmkz + 0U, // VMOVDQA32Zrr + 0U, // VMOVDQA32Zrr_REV + 0U, // VMOVDQA32Zrrk + 0U, // VMOVDQA32Zrrk_REV + 0U, // VMOVDQA32Zrrkz + 0U, // VMOVDQA32Zrrkz_REV + 0U, // VMOVDQA64Z128mr + 0U, // VMOVDQA64Z128mrk + 0U, // VMOVDQA64Z128rm + 0U, // VMOVDQA64Z128rmk + 0U, // VMOVDQA64Z128rmkz + 0U, // VMOVDQA64Z128rr + 0U, // VMOVDQA64Z128rr_REV + 0U, // VMOVDQA64Z128rrk + 0U, // VMOVDQA64Z128rrk_REV + 0U, // VMOVDQA64Z128rrkz + 0U, // VMOVDQA64Z128rrkz_REV + 0U, // VMOVDQA64Z256mr + 0U, // VMOVDQA64Z256mrk + 0U, // VMOVDQA64Z256rm + 0U, // VMOVDQA64Z256rmk + 0U, // VMOVDQA64Z256rmkz + 0U, // VMOVDQA64Z256rr + 0U, // VMOVDQA64Z256rr_REV + 0U, // VMOVDQA64Z256rrk + 0U, // VMOVDQA64Z256rrk_REV + 0U, // VMOVDQA64Z256rrkz + 0U, // VMOVDQA64Z256rrkz_REV + 0U, // VMOVDQA64Zmr + 0U, // VMOVDQA64Zmrk + 0U, // VMOVDQA64Zrm + 0U, // VMOVDQA64Zrmk + 0U, // VMOVDQA64Zrmkz + 0U, // VMOVDQA64Zrr + 0U, // VMOVDQA64Zrr_REV + 0U, // VMOVDQA64Zrrk + 0U, // VMOVDQA64Zrrk_REV + 0U, // VMOVDQA64Zrrkz + 0U, // VMOVDQA64Zrrkz_REV + 0U, // VMOVDQAYmr + 0U, // VMOVDQAYrm + 0U, // VMOVDQAYrr + 0U, // VMOVDQAYrr_REV + 0U, // VMOVDQAmr + 0U, // VMOVDQArm + 0U, // VMOVDQArr + 0U, // VMOVDQArr_REV + 0U, // VMOVDQU16Z128mr + 0U, // VMOVDQU16Z128mrk + 0U, // VMOVDQU16Z128rm + 0U, // VMOVDQU16Z128rmk + 0U, // VMOVDQU16Z128rmkz + 0U, // VMOVDQU16Z128rr + 0U, // VMOVDQU16Z128rr_REV + 0U, // VMOVDQU16Z128rrk + 0U, // VMOVDQU16Z128rrk_REV + 0U, // VMOVDQU16Z128rrkz + 0U, // VMOVDQU16Z128rrkz_REV + 0U, // VMOVDQU16Z256mr + 0U, // VMOVDQU16Z256mrk + 0U, // VMOVDQU16Z256rm + 0U, // VMOVDQU16Z256rmk + 0U, // VMOVDQU16Z256rmkz + 0U, // VMOVDQU16Z256rr + 0U, // VMOVDQU16Z256rr_REV + 0U, // VMOVDQU16Z256rrk + 0U, // VMOVDQU16Z256rrk_REV + 0U, // VMOVDQU16Z256rrkz + 0U, // VMOVDQU16Z256rrkz_REV + 0U, // VMOVDQU16Zmr + 0U, // VMOVDQU16Zmrk + 0U, // VMOVDQU16Zrm + 0U, // VMOVDQU16Zrmk + 0U, // VMOVDQU16Zrmkz + 0U, // VMOVDQU16Zrr + 0U, // VMOVDQU16Zrr_REV + 0U, // VMOVDQU16Zrrk + 0U, // VMOVDQU16Zrrk_REV + 0U, // VMOVDQU16Zrrkz + 0U, // VMOVDQU16Zrrkz_REV + 0U, // VMOVDQU32Z128mr + 0U, // VMOVDQU32Z128mrk + 0U, // VMOVDQU32Z128rm + 0U, // VMOVDQU32Z128rmk + 0U, // VMOVDQU32Z128rmkz + 0U, // VMOVDQU32Z128rr + 0U, // VMOVDQU32Z128rr_REV + 0U, // VMOVDQU32Z128rrk + 0U, // VMOVDQU32Z128rrk_REV + 0U, // VMOVDQU32Z128rrkz + 0U, // VMOVDQU32Z128rrkz_REV + 0U, // VMOVDQU32Z256mr + 0U, // VMOVDQU32Z256mrk + 0U, // VMOVDQU32Z256rm + 0U, // VMOVDQU32Z256rmk + 0U, // VMOVDQU32Z256rmkz + 0U, // VMOVDQU32Z256rr + 0U, // VMOVDQU32Z256rr_REV + 0U, // VMOVDQU32Z256rrk + 0U, // VMOVDQU32Z256rrk_REV + 0U, // VMOVDQU32Z256rrkz + 0U, // VMOVDQU32Z256rrkz_REV + 0U, // VMOVDQU32Zmr + 0U, // VMOVDQU32Zmrk + 0U, // VMOVDQU32Zrm + 0U, // VMOVDQU32Zrmk + 0U, // VMOVDQU32Zrmkz + 0U, // VMOVDQU32Zrr + 0U, // VMOVDQU32Zrr_REV + 0U, // VMOVDQU32Zrrk + 0U, // VMOVDQU32Zrrk_REV + 0U, // VMOVDQU32Zrrkz + 0U, // VMOVDQU32Zrrkz_REV + 0U, // VMOVDQU64Z128mr + 0U, // VMOVDQU64Z128mrk + 0U, // VMOVDQU64Z128rm + 0U, // VMOVDQU64Z128rmk + 0U, // VMOVDQU64Z128rmkz + 0U, // VMOVDQU64Z128rr + 0U, // VMOVDQU64Z128rr_REV + 0U, // VMOVDQU64Z128rrk + 0U, // VMOVDQU64Z128rrk_REV + 0U, // VMOVDQU64Z128rrkz + 0U, // VMOVDQU64Z128rrkz_REV + 0U, // VMOVDQU64Z256mr + 0U, // VMOVDQU64Z256mrk + 0U, // VMOVDQU64Z256rm + 0U, // VMOVDQU64Z256rmk + 0U, // VMOVDQU64Z256rmkz + 0U, // VMOVDQU64Z256rr + 0U, // VMOVDQU64Z256rr_REV + 0U, // VMOVDQU64Z256rrk + 0U, // VMOVDQU64Z256rrk_REV + 0U, // VMOVDQU64Z256rrkz + 0U, // VMOVDQU64Z256rrkz_REV + 0U, // VMOVDQU64Zmr + 0U, // VMOVDQU64Zmrk + 0U, // VMOVDQU64Zrm + 0U, // VMOVDQU64Zrmk + 0U, // VMOVDQU64Zrmkz + 0U, // VMOVDQU64Zrr + 0U, // VMOVDQU64Zrr_REV + 0U, // VMOVDQU64Zrrk + 0U, // VMOVDQU64Zrrk_REV + 0U, // VMOVDQU64Zrrkz + 0U, // VMOVDQU64Zrrkz_REV + 0U, // VMOVDQU8Z128mr + 0U, // VMOVDQU8Z128mrk + 0U, // VMOVDQU8Z128rm + 0U, // VMOVDQU8Z128rmk + 0U, // VMOVDQU8Z128rmkz + 0U, // VMOVDQU8Z128rr + 0U, // VMOVDQU8Z128rr_REV + 0U, // VMOVDQU8Z128rrk + 0U, // VMOVDQU8Z128rrk_REV + 0U, // VMOVDQU8Z128rrkz + 0U, // VMOVDQU8Z128rrkz_REV + 0U, // VMOVDQU8Z256mr + 0U, // VMOVDQU8Z256mrk + 0U, // VMOVDQU8Z256rm + 0U, // VMOVDQU8Z256rmk + 0U, // VMOVDQU8Z256rmkz + 0U, // VMOVDQU8Z256rr + 0U, // VMOVDQU8Z256rr_REV + 0U, // VMOVDQU8Z256rrk + 0U, // VMOVDQU8Z256rrk_REV + 0U, // VMOVDQU8Z256rrkz + 0U, // VMOVDQU8Z256rrkz_REV + 0U, // VMOVDQU8Zmr + 0U, // VMOVDQU8Zmrk + 0U, // VMOVDQU8Zrm + 0U, // VMOVDQU8Zrmk + 0U, // VMOVDQU8Zrmkz + 0U, // VMOVDQU8Zrr + 0U, // VMOVDQU8Zrr_REV + 0U, // VMOVDQU8Zrrk + 0U, // VMOVDQU8Zrrk_REV + 0U, // VMOVDQU8Zrrkz + 0U, // VMOVDQU8Zrrkz_REV + 0U, // VMOVDQUYmr + 0U, // VMOVDQUYrm + 0U, // VMOVDQUYrr + 0U, // VMOVDQUYrr_REV + 0U, // VMOVDQUmr + 0U, // VMOVDQUrm + 0U, // VMOVDQUrr + 0U, // VMOVDQUrr_REV + 0U, // VMOVHLPSZrr + 0U, // VMOVHLPSrr + 0U, // VMOVHPDZ128mr + 0U, // VMOVHPDZ128rm + 0U, // VMOVHPDmr + 0U, // VMOVHPDrm + 0U, // VMOVHPSZ128mr + 0U, // VMOVHPSZ128rm + 0U, // VMOVHPSmr + 0U, // VMOVHPSrm + 0U, // VMOVLHPSZrr + 0U, // VMOVLHPSrr + 0U, // VMOVLPDZ128mr + 0U, // VMOVLPDZ128rm + 0U, // VMOVLPDmr + 0U, // VMOVLPDrm + 0U, // VMOVLPSZ128mr + 0U, // VMOVLPSZ128rm + 0U, // VMOVLPSmr + 0U, // VMOVLPSrm + 0U, // VMOVMSKPDYrr + 0U, // VMOVMSKPDrr + 0U, // VMOVMSKPSYrr + 0U, // VMOVMSKPSrr + 0U, // VMOVNTDQAYrm + 0U, // VMOVNTDQAZ128rm + 0U, // VMOVNTDQAZ256rm + 0U, // VMOVNTDQAZrm + 0U, // VMOVNTDQArm + 0U, // VMOVNTDQYmr + 0U, // VMOVNTDQZ128mr + 0U, // VMOVNTDQZ256mr + 0U, // VMOVNTDQZmr + 0U, // VMOVNTDQmr + 0U, // VMOVNTPDYmr + 0U, // VMOVNTPDZ128mr + 0U, // VMOVNTPDZ256mr + 0U, // VMOVNTPDZmr + 0U, // VMOVNTPDmr + 0U, // VMOVNTPSYmr + 0U, // VMOVNTPSZ128mr + 0U, // VMOVNTPSZ256mr + 0U, // VMOVNTPSZmr + 0U, // VMOVNTPSmr + 0U, // VMOVPDI2DIZmr + 0U, // VMOVPDI2DIZrr + 0U, // VMOVPDI2DImr + 0U, // VMOVPDI2DIrr + 0U, // VMOVPQI2QIZmr + 0U, // VMOVPQI2QIZrr + 0U, // VMOVPQI2QImr + 0U, // VMOVPQI2QIrr + 0U, // VMOVPQIto64Zmr + 0U, // VMOVPQIto64Zrr + 0U, // VMOVPQIto64mr + 0U, // VMOVPQIto64rr + 0U, // VMOVQI2PQIZrm + 0U, // VMOVQI2PQIrm + 0U, // VMOVSDZmr + 0U, // VMOVSDZmrk + 0U, // VMOVSDZrm + 0U, // VMOVSDZrmk + 0U, // VMOVSDZrmkz + 0U, // VMOVSDZrr + 0U, // VMOVSDZrr_REV + 0U, // VMOVSDZrrk + 0U, // VMOVSDZrrk_REV + 0U, // VMOVSDZrrkz + 0U, // VMOVSDZrrkz_REV + 0U, // VMOVSDmr + 0U, // VMOVSDrm + 0U, // VMOVSDrr + 0U, // VMOVSDrr_REV + 0U, // VMOVSDto64Zmr + 0U, // VMOVSDto64Zrr + 0U, // VMOVSDto64mr + 0U, // VMOVSDto64rr + 0U, // VMOVSHDUPYrm + 0U, // VMOVSHDUPYrr + 0U, // VMOVSHDUPZ128rm + 0U, // VMOVSHDUPZ128rmk + 0U, // VMOVSHDUPZ128rmkz + 0U, // VMOVSHDUPZ128rr + 0U, // VMOVSHDUPZ128rrk + 0U, // VMOVSHDUPZ128rrkz + 0U, // VMOVSHDUPZ256rm + 0U, // VMOVSHDUPZ256rmk + 0U, // VMOVSHDUPZ256rmkz + 0U, // VMOVSHDUPZ256rr + 0U, // VMOVSHDUPZ256rrk + 0U, // VMOVSHDUPZ256rrkz + 0U, // VMOVSHDUPZrm + 0U, // VMOVSHDUPZrmk + 0U, // VMOVSHDUPZrmkz + 0U, // VMOVSHDUPZrr + 0U, // VMOVSHDUPZrrk + 0U, // VMOVSHDUPZrrkz + 0U, // VMOVSHDUPrm + 0U, // VMOVSHDUPrr + 0U, // VMOVSLDUPYrm + 0U, // VMOVSLDUPYrr + 0U, // VMOVSLDUPZ128rm + 0U, // VMOVSLDUPZ128rmk + 0U, // VMOVSLDUPZ128rmkz + 0U, // VMOVSLDUPZ128rr + 0U, // VMOVSLDUPZ128rrk + 0U, // VMOVSLDUPZ128rrkz + 0U, // VMOVSLDUPZ256rm + 0U, // VMOVSLDUPZ256rmk + 0U, // VMOVSLDUPZ256rmkz + 0U, // VMOVSLDUPZ256rr + 0U, // VMOVSLDUPZ256rrk + 0U, // VMOVSLDUPZ256rrkz + 0U, // VMOVSLDUPZrm + 0U, // VMOVSLDUPZrmk + 0U, // VMOVSLDUPZrmkz + 0U, // VMOVSLDUPZrr + 0U, // VMOVSLDUPZrrk + 0U, // VMOVSLDUPZrrkz + 0U, // VMOVSLDUPrm + 0U, // VMOVSLDUPrr + 0U, // VMOVSS2DIZmr + 0U, // VMOVSS2DIZrr + 0U, // VMOVSS2DImr + 0U, // VMOVSS2DIrr + 0U, // VMOVSSZmr + 0U, // VMOVSSZmrk + 0U, // VMOVSSZrm + 0U, // VMOVSSZrmk + 0U, // VMOVSSZrmkz + 0U, // VMOVSSZrr + 0U, // VMOVSSZrr_REV + 0U, // VMOVSSZrrk + 0U, // VMOVSSZrrk_REV + 0U, // VMOVSSZrrkz + 0U, // VMOVSSZrrkz_REV + 0U, // VMOVSSmr + 0U, // VMOVSSrm + 0U, // VMOVSSrr + 0U, // VMOVSSrr_REV + 0U, // VMOVUPDYmr + 0U, // VMOVUPDYrm + 0U, // VMOVUPDYrr + 0U, // VMOVUPDYrr_REV + 0U, // VMOVUPDZ128mr + 0U, // VMOVUPDZ128mrk + 0U, // VMOVUPDZ128rm + 0U, // VMOVUPDZ128rmk + 0U, // VMOVUPDZ128rmkz + 0U, // VMOVUPDZ128rr + 0U, // VMOVUPDZ128rr_REV + 0U, // VMOVUPDZ128rrk + 0U, // VMOVUPDZ128rrk_REV + 0U, // VMOVUPDZ128rrkz + 0U, // VMOVUPDZ128rrkz_REV + 0U, // VMOVUPDZ256mr + 0U, // VMOVUPDZ256mrk + 0U, // VMOVUPDZ256rm + 0U, // VMOVUPDZ256rmk + 0U, // VMOVUPDZ256rmkz + 0U, // VMOVUPDZ256rr + 0U, // VMOVUPDZ256rr_REV + 0U, // VMOVUPDZ256rrk + 0U, // VMOVUPDZ256rrk_REV + 0U, // VMOVUPDZ256rrkz + 0U, // VMOVUPDZ256rrkz_REV + 0U, // VMOVUPDZmr + 0U, // VMOVUPDZmrk + 0U, // VMOVUPDZrm + 0U, // VMOVUPDZrmk + 0U, // VMOVUPDZrmkz + 0U, // VMOVUPDZrr + 0U, // VMOVUPDZrr_REV + 0U, // VMOVUPDZrrk + 0U, // VMOVUPDZrrk_REV + 0U, // VMOVUPDZrrkz + 0U, // VMOVUPDZrrkz_REV + 0U, // VMOVUPDmr + 0U, // VMOVUPDrm + 0U, // VMOVUPDrr + 0U, // VMOVUPDrr_REV + 0U, // VMOVUPSYmr + 0U, // VMOVUPSYrm + 0U, // VMOVUPSYrr + 0U, // VMOVUPSYrr_REV + 0U, // VMOVUPSZ128mr + 0U, // VMOVUPSZ128mrk + 0U, // VMOVUPSZ128rm + 0U, // VMOVUPSZ128rmk + 0U, // VMOVUPSZ128rmkz + 0U, // VMOVUPSZ128rr + 0U, // VMOVUPSZ128rr_REV + 0U, // VMOVUPSZ128rrk + 0U, // VMOVUPSZ128rrk_REV + 0U, // VMOVUPSZ128rrkz + 0U, // VMOVUPSZ128rrkz_REV + 0U, // VMOVUPSZ256mr + 0U, // VMOVUPSZ256mrk + 0U, // VMOVUPSZ256rm + 0U, // VMOVUPSZ256rmk + 0U, // VMOVUPSZ256rmkz + 0U, // VMOVUPSZ256rr + 0U, // VMOVUPSZ256rr_REV + 0U, // VMOVUPSZ256rrk + 0U, // VMOVUPSZ256rrk_REV + 0U, // VMOVUPSZ256rrkz + 0U, // VMOVUPSZ256rrkz_REV + 0U, // VMOVUPSZmr + 0U, // VMOVUPSZmrk + 0U, // VMOVUPSZrm + 0U, // VMOVUPSZrmk + 0U, // VMOVUPSZrmkz + 0U, // VMOVUPSZrr + 0U, // VMOVUPSZrr_REV + 0U, // VMOVUPSZrrk + 0U, // VMOVUPSZrrk_REV + 0U, // VMOVUPSZrrkz + 0U, // VMOVUPSZrrkz_REV + 0U, // VMOVUPSmr + 0U, // VMOVUPSrm + 0U, // VMOVUPSrr + 0U, // VMOVUPSrr_REV + 0U, // VMOVZPQILo2PQIZrr + 0U, // VMOVZPQILo2PQIrr + 0U, // VMPSADBWYrmi + 0U, // VMPSADBWYrri + 0U, // VMPSADBWrmi + 0U, // VMPSADBWrri + 0U, // VMPTRLDm + 0U, // VMPTRSTm + 0U, // VMREAD32mr + 0U, // VMREAD32rr + 0U, // VMREAD64mr + 0U, // VMREAD64rr + 0U, // VMRESUME + 0U, // VMRUN32 + 0U, // VMRUN64 + 0U, // VMSAVE32 + 0U, // VMSAVE64 + 0U, // VMULPDYrm + 0U, // VMULPDYrr + 0U, // VMULPDZ128rm + 0U, // VMULPDZ128rmb + 0U, // VMULPDZ128rmbk + 0U, // VMULPDZ128rmbkz + 0U, // VMULPDZ128rmk + 0U, // VMULPDZ128rmkz + 0U, // VMULPDZ128rr + 0U, // VMULPDZ128rrk + 0U, // VMULPDZ128rrkz + 0U, // VMULPDZ256rm + 0U, // VMULPDZ256rmb + 0U, // VMULPDZ256rmbk + 0U, // VMULPDZ256rmbkz + 0U, // VMULPDZ256rmk + 0U, // VMULPDZ256rmkz + 0U, // VMULPDZ256rr + 0U, // VMULPDZ256rrk + 0U, // VMULPDZ256rrkz + 0U, // VMULPDZrm + 0U, // VMULPDZrmb + 0U, // VMULPDZrmbk + 0U, // VMULPDZrmbkz + 0U, // VMULPDZrmk + 0U, // VMULPDZrmkz + 0U, // VMULPDZrr + 0U, // VMULPDZrrb + 0U, // VMULPDZrrbk + 0U, // VMULPDZrrbkz + 0U, // VMULPDZrrk + 0U, // VMULPDZrrkz + 0U, // VMULPDrm + 0U, // VMULPDrr + 0U, // VMULPSYrm + 0U, // VMULPSYrr + 0U, // VMULPSZ128rm + 0U, // VMULPSZ128rmb + 0U, // VMULPSZ128rmbk + 0U, // VMULPSZ128rmbkz + 0U, // VMULPSZ128rmk + 0U, // VMULPSZ128rmkz + 0U, // VMULPSZ128rr + 0U, // VMULPSZ128rrk + 0U, // VMULPSZ128rrkz + 0U, // VMULPSZ256rm + 0U, // VMULPSZ256rmb + 0U, // VMULPSZ256rmbk + 0U, // VMULPSZ256rmbkz + 0U, // VMULPSZ256rmk + 0U, // VMULPSZ256rmkz + 0U, // VMULPSZ256rr + 0U, // VMULPSZ256rrk + 0U, // VMULPSZ256rrkz + 0U, // VMULPSZrm + 0U, // VMULPSZrmb + 0U, // VMULPSZrmbk + 0U, // VMULPSZrmbkz + 0U, // VMULPSZrmk + 0U, // VMULPSZrmkz + 0U, // VMULPSZrr + 0U, // VMULPSZrrb + 0U, // VMULPSZrrbk + 0U, // VMULPSZrrbkz + 0U, // VMULPSZrrk + 0U, // VMULPSZrrkz + 0U, // VMULPSrm + 0U, // VMULPSrr + 0U, // VMULSDZrm + 0U, // VMULSDZrm_Int + 0U, // VMULSDZrm_Intk + 0U, // VMULSDZrm_Intkz + 0U, // VMULSDZrr + 0U, // VMULSDZrr_Int + 0U, // VMULSDZrr_Intk + 0U, // VMULSDZrr_Intkz + 0U, // VMULSDZrrb_Int + 0U, // VMULSDZrrb_Intk + 0U, // VMULSDZrrb_Intkz + 0U, // VMULSDrm + 0U, // VMULSDrm_Int + 0U, // VMULSDrr + 0U, // VMULSDrr_Int + 0U, // VMULSSZrm + 0U, // VMULSSZrm_Int + 0U, // VMULSSZrm_Intk + 0U, // VMULSSZrm_Intkz + 0U, // VMULSSZrr + 0U, // VMULSSZrr_Int + 0U, // VMULSSZrr_Intk + 0U, // VMULSSZrr_Intkz + 0U, // VMULSSZrrb_Int + 0U, // VMULSSZrrb_Intk + 0U, // VMULSSZrrb_Intkz + 0U, // VMULSSrm + 0U, // VMULSSrm_Int + 0U, // VMULSSrr + 0U, // VMULSSrr_Int + 0U, // VMWRITE32rm + 0U, // VMWRITE32rr + 0U, // VMWRITE64rm + 0U, // VMWRITE64rr + 0U, // VMXOFF + 0U, // VMXON + 0U, // VORPDYrm + 0U, // VORPDYrr + 0U, // VORPDZ128rm + 0U, // VORPDZ128rmb + 0U, // VORPDZ128rmbk + 0U, // VORPDZ128rmbkz + 0U, // VORPDZ128rmk + 0U, // VORPDZ128rmkz + 0U, // VORPDZ128rr + 0U, // VORPDZ128rrk + 0U, // VORPDZ128rrkz + 0U, // VORPDZ256rm + 0U, // VORPDZ256rmb + 0U, // VORPDZ256rmbk + 0U, // VORPDZ256rmbkz + 0U, // VORPDZ256rmk + 0U, // VORPDZ256rmkz + 0U, // VORPDZ256rr + 0U, // VORPDZ256rrk + 0U, // VORPDZ256rrkz + 0U, // VORPDZrm + 0U, // VORPDZrmb + 0U, // VORPDZrmbk + 0U, // VORPDZrmbkz + 0U, // VORPDZrmk + 0U, // VORPDZrmkz + 0U, // VORPDZrr + 0U, // VORPDZrrk + 0U, // VORPDZrrkz + 0U, // VORPDrm + 0U, // VORPDrr + 0U, // VORPSYrm + 0U, // VORPSYrr + 0U, // VORPSZ128rm + 0U, // VORPSZ128rmb + 0U, // VORPSZ128rmbk + 0U, // VORPSZ128rmbkz + 0U, // VORPSZ128rmk + 0U, // VORPSZ128rmkz + 0U, // VORPSZ128rr + 0U, // VORPSZ128rrk + 0U, // VORPSZ128rrkz + 0U, // VORPSZ256rm + 0U, // VORPSZ256rmb + 0U, // VORPSZ256rmbk + 0U, // VORPSZ256rmbkz + 0U, // VORPSZ256rmk + 0U, // VORPSZ256rmkz + 0U, // VORPSZ256rr + 0U, // VORPSZ256rrk + 0U, // VORPSZ256rrkz + 0U, // VORPSZrm + 0U, // VORPSZrmb + 0U, // VORPSZrmbk + 0U, // VORPSZrmbkz + 0U, // VORPSZrmk + 0U, // VORPSZrmkz + 0U, // VORPSZrr + 0U, // VORPSZrrk + 0U, // VORPSZrrkz + 0U, // VORPSrm + 0U, // VORPSrr + 0U, // VP4DPWSSDSrm + 0U, // VP4DPWSSDSrmk + 0U, // VP4DPWSSDSrmkz + 0U, // VP4DPWSSDrm + 0U, // VP4DPWSSDrmk + 0U, // VP4DPWSSDrmkz + 0U, // VPABSBYrm + 0U, // VPABSBYrr + 0U, // VPABSBZ128rm + 0U, // VPABSBZ128rmk + 0U, // VPABSBZ128rmkz + 0U, // VPABSBZ128rr + 0U, // VPABSBZ128rrk + 0U, // VPABSBZ128rrkz + 0U, // VPABSBZ256rm + 0U, // VPABSBZ256rmk + 0U, // VPABSBZ256rmkz + 0U, // VPABSBZ256rr + 0U, // VPABSBZ256rrk + 0U, // VPABSBZ256rrkz + 0U, // VPABSBZrm + 0U, // VPABSBZrmk + 0U, // VPABSBZrmkz + 0U, // VPABSBZrr + 0U, // VPABSBZrrk + 0U, // VPABSBZrrkz + 0U, // VPABSBrm + 0U, // VPABSBrr + 0U, // VPABSDYrm + 0U, // VPABSDYrr + 0U, // VPABSDZ128rm + 0U, // VPABSDZ128rmb + 0U, // VPABSDZ128rmbk + 0U, // VPABSDZ128rmbkz + 0U, // VPABSDZ128rmk + 0U, // VPABSDZ128rmkz + 0U, // VPABSDZ128rr + 0U, // VPABSDZ128rrk + 0U, // VPABSDZ128rrkz + 0U, // VPABSDZ256rm + 0U, // VPABSDZ256rmb + 0U, // VPABSDZ256rmbk + 0U, // VPABSDZ256rmbkz + 0U, // VPABSDZ256rmk + 0U, // VPABSDZ256rmkz + 0U, // VPABSDZ256rr + 0U, // VPABSDZ256rrk + 0U, // VPABSDZ256rrkz + 0U, // VPABSDZrm + 0U, // VPABSDZrmb + 0U, // VPABSDZrmbk + 0U, // VPABSDZrmbkz + 0U, // VPABSDZrmk + 0U, // VPABSDZrmkz + 0U, // VPABSDZrr + 0U, // VPABSDZrrk + 0U, // VPABSDZrrkz + 0U, // VPABSDrm + 0U, // VPABSDrr + 0U, // VPABSQZ128rm + 0U, // VPABSQZ128rmb + 0U, // VPABSQZ128rmbk + 0U, // VPABSQZ128rmbkz + 0U, // VPABSQZ128rmk + 0U, // VPABSQZ128rmkz + 0U, // VPABSQZ128rr + 0U, // VPABSQZ128rrk + 0U, // VPABSQZ128rrkz + 0U, // VPABSQZ256rm + 0U, // VPABSQZ256rmb + 0U, // VPABSQZ256rmbk + 0U, // VPABSQZ256rmbkz + 0U, // VPABSQZ256rmk + 0U, // VPABSQZ256rmkz + 0U, // VPABSQZ256rr + 0U, // VPABSQZ256rrk + 0U, // VPABSQZ256rrkz + 0U, // VPABSQZrm + 0U, // VPABSQZrmb + 0U, // VPABSQZrmbk + 0U, // VPABSQZrmbkz + 0U, // VPABSQZrmk + 0U, // VPABSQZrmkz + 0U, // VPABSQZrr + 0U, // VPABSQZrrk + 0U, // VPABSQZrrkz + 0U, // VPABSWYrm + 0U, // VPABSWYrr + 0U, // VPABSWZ128rm + 0U, // VPABSWZ128rmk + 0U, // VPABSWZ128rmkz + 0U, // VPABSWZ128rr + 0U, // VPABSWZ128rrk + 0U, // VPABSWZ128rrkz + 0U, // VPABSWZ256rm + 0U, // VPABSWZ256rmk + 0U, // VPABSWZ256rmkz + 0U, // VPABSWZ256rr + 0U, // VPABSWZ256rrk + 0U, // VPABSWZ256rrkz + 0U, // VPABSWZrm + 0U, // VPABSWZrmk + 0U, // VPABSWZrmkz + 0U, // VPABSWZrr + 0U, // VPABSWZrrk + 0U, // VPABSWZrrkz + 0U, // VPABSWrm + 0U, // VPABSWrr + 0U, // VPACKSSDWYrm + 0U, // VPACKSSDWYrr + 0U, // VPACKSSDWZ128rm + 0U, // VPACKSSDWZ128rmb + 0U, // VPACKSSDWZ128rmbk + 0U, // VPACKSSDWZ128rmbkz + 0U, // VPACKSSDWZ128rmk + 0U, // VPACKSSDWZ128rmkz + 0U, // VPACKSSDWZ128rr + 0U, // VPACKSSDWZ128rrk + 0U, // VPACKSSDWZ128rrkz + 0U, // VPACKSSDWZ256rm + 0U, // VPACKSSDWZ256rmb + 0U, // VPACKSSDWZ256rmbk + 0U, // VPACKSSDWZ256rmbkz + 0U, // VPACKSSDWZ256rmk + 0U, // VPACKSSDWZ256rmkz + 0U, // VPACKSSDWZ256rr + 0U, // VPACKSSDWZ256rrk + 0U, // VPACKSSDWZ256rrkz + 0U, // VPACKSSDWZrm + 0U, // VPACKSSDWZrmb + 0U, // VPACKSSDWZrmbk + 0U, // VPACKSSDWZrmbkz + 0U, // VPACKSSDWZrmk + 0U, // VPACKSSDWZrmkz + 0U, // VPACKSSDWZrr + 0U, // VPACKSSDWZrrk + 0U, // VPACKSSDWZrrkz + 0U, // VPACKSSDWrm + 0U, // VPACKSSDWrr + 0U, // VPACKSSWBYrm + 0U, // VPACKSSWBYrr + 0U, // VPACKSSWBZ128rm + 0U, // VPACKSSWBZ128rmk + 0U, // VPACKSSWBZ128rmkz + 0U, // VPACKSSWBZ128rr + 0U, // VPACKSSWBZ128rrk + 0U, // VPACKSSWBZ128rrkz + 0U, // VPACKSSWBZ256rm + 0U, // VPACKSSWBZ256rmk + 0U, // VPACKSSWBZ256rmkz + 0U, // VPACKSSWBZ256rr + 0U, // VPACKSSWBZ256rrk + 0U, // VPACKSSWBZ256rrkz + 0U, // VPACKSSWBZrm + 0U, // VPACKSSWBZrmk + 0U, // VPACKSSWBZrmkz + 0U, // VPACKSSWBZrr + 0U, // VPACKSSWBZrrk + 0U, // VPACKSSWBZrrkz + 0U, // VPACKSSWBrm + 0U, // VPACKSSWBrr + 0U, // VPACKUSDWYrm + 0U, // VPACKUSDWYrr + 0U, // VPACKUSDWZ128rm + 0U, // VPACKUSDWZ128rmb + 0U, // VPACKUSDWZ128rmbk + 0U, // VPACKUSDWZ128rmbkz + 0U, // VPACKUSDWZ128rmk + 0U, // VPACKUSDWZ128rmkz + 0U, // VPACKUSDWZ128rr + 0U, // VPACKUSDWZ128rrk + 0U, // VPACKUSDWZ128rrkz + 0U, // VPACKUSDWZ256rm + 0U, // VPACKUSDWZ256rmb + 0U, // VPACKUSDWZ256rmbk + 0U, // VPACKUSDWZ256rmbkz + 0U, // VPACKUSDWZ256rmk + 0U, // VPACKUSDWZ256rmkz + 0U, // VPACKUSDWZ256rr + 0U, // VPACKUSDWZ256rrk + 0U, // VPACKUSDWZ256rrkz + 0U, // VPACKUSDWZrm + 0U, // VPACKUSDWZrmb + 0U, // VPACKUSDWZrmbk + 0U, // VPACKUSDWZrmbkz + 0U, // VPACKUSDWZrmk + 0U, // VPACKUSDWZrmkz + 0U, // VPACKUSDWZrr + 0U, // VPACKUSDWZrrk + 0U, // VPACKUSDWZrrkz + 0U, // VPACKUSDWrm + 0U, // VPACKUSDWrr + 0U, // VPACKUSWBYrm + 0U, // VPACKUSWBYrr + 0U, // VPACKUSWBZ128rm + 0U, // VPACKUSWBZ128rmk + 0U, // VPACKUSWBZ128rmkz + 0U, // VPACKUSWBZ128rr + 0U, // VPACKUSWBZ128rrk + 0U, // VPACKUSWBZ128rrkz + 0U, // VPACKUSWBZ256rm + 0U, // VPACKUSWBZ256rmk + 0U, // VPACKUSWBZ256rmkz + 0U, // VPACKUSWBZ256rr + 0U, // VPACKUSWBZ256rrk + 0U, // VPACKUSWBZ256rrkz + 0U, // VPACKUSWBZrm + 0U, // VPACKUSWBZrmk + 0U, // VPACKUSWBZrmkz + 0U, // VPACKUSWBZrr + 0U, // VPACKUSWBZrrk + 0U, // VPACKUSWBZrrkz + 0U, // VPACKUSWBrm + 0U, // VPACKUSWBrr + 0U, // VPADDBYrm + 0U, // VPADDBYrr + 0U, // VPADDBZ128rm + 0U, // VPADDBZ128rmk + 0U, // VPADDBZ128rmkz + 0U, // VPADDBZ128rr + 0U, // VPADDBZ128rrk + 0U, // VPADDBZ128rrkz + 0U, // VPADDBZ256rm + 0U, // VPADDBZ256rmk + 0U, // VPADDBZ256rmkz + 0U, // VPADDBZ256rr + 0U, // VPADDBZ256rrk + 0U, // VPADDBZ256rrkz + 0U, // VPADDBZrm + 0U, // VPADDBZrmk + 0U, // VPADDBZrmkz + 0U, // VPADDBZrr + 0U, // VPADDBZrrk + 0U, // VPADDBZrrkz + 0U, // VPADDBrm + 0U, // VPADDBrr + 0U, // VPADDDYrm + 0U, // VPADDDYrr + 0U, // VPADDDZ128rm + 0U, // VPADDDZ128rmb + 0U, // VPADDDZ128rmbk + 0U, // VPADDDZ128rmbkz + 0U, // VPADDDZ128rmk + 0U, // VPADDDZ128rmkz + 0U, // VPADDDZ128rr + 0U, // VPADDDZ128rrk + 0U, // VPADDDZ128rrkz + 0U, // VPADDDZ256rm + 0U, // VPADDDZ256rmb + 0U, // VPADDDZ256rmbk + 0U, // VPADDDZ256rmbkz + 0U, // VPADDDZ256rmk + 0U, // VPADDDZ256rmkz + 0U, // VPADDDZ256rr + 0U, // VPADDDZ256rrk + 0U, // VPADDDZ256rrkz + 0U, // VPADDDZrm + 0U, // VPADDDZrmb + 0U, // VPADDDZrmbk + 0U, // VPADDDZrmbkz + 0U, // VPADDDZrmk + 0U, // VPADDDZrmkz + 0U, // VPADDDZrr + 0U, // VPADDDZrrk + 0U, // VPADDDZrrkz + 0U, // VPADDDrm + 0U, // VPADDDrr + 0U, // VPADDQYrm + 0U, // VPADDQYrr + 0U, // VPADDQZ128rm + 0U, // VPADDQZ128rmb + 0U, // VPADDQZ128rmbk + 0U, // VPADDQZ128rmbkz + 0U, // VPADDQZ128rmk + 0U, // VPADDQZ128rmkz + 0U, // VPADDQZ128rr + 0U, // VPADDQZ128rrk + 0U, // VPADDQZ128rrkz + 0U, // VPADDQZ256rm + 0U, // VPADDQZ256rmb + 0U, // VPADDQZ256rmbk + 0U, // VPADDQZ256rmbkz + 0U, // VPADDQZ256rmk + 0U, // VPADDQZ256rmkz + 0U, // VPADDQZ256rr + 0U, // VPADDQZ256rrk + 0U, // VPADDQZ256rrkz + 0U, // VPADDQZrm + 0U, // VPADDQZrmb + 0U, // VPADDQZrmbk + 0U, // VPADDQZrmbkz + 0U, // VPADDQZrmk + 0U, // VPADDQZrmkz + 0U, // VPADDQZrr + 0U, // VPADDQZrrk + 0U, // VPADDQZrrkz + 0U, // VPADDQrm + 0U, // VPADDQrr + 0U, // VPADDSBYrm + 0U, // VPADDSBYrr + 0U, // VPADDSBZ128rm + 0U, // VPADDSBZ128rmk + 0U, // VPADDSBZ128rmkz + 0U, // VPADDSBZ128rr + 0U, // VPADDSBZ128rrk + 0U, // VPADDSBZ128rrkz + 0U, // VPADDSBZ256rm + 0U, // VPADDSBZ256rmk + 0U, // VPADDSBZ256rmkz + 0U, // VPADDSBZ256rr + 0U, // VPADDSBZ256rrk + 0U, // VPADDSBZ256rrkz + 0U, // VPADDSBZrm + 0U, // VPADDSBZrmk + 0U, // VPADDSBZrmkz + 0U, // VPADDSBZrr + 0U, // VPADDSBZrrk + 0U, // VPADDSBZrrkz + 0U, // VPADDSBrm + 0U, // VPADDSBrr + 0U, // VPADDSWYrm + 0U, // VPADDSWYrr + 0U, // VPADDSWZ128rm + 0U, // VPADDSWZ128rmk + 0U, // VPADDSWZ128rmkz + 0U, // VPADDSWZ128rr + 0U, // VPADDSWZ128rrk + 0U, // VPADDSWZ128rrkz + 0U, // VPADDSWZ256rm + 0U, // VPADDSWZ256rmk + 0U, // VPADDSWZ256rmkz + 0U, // VPADDSWZ256rr + 0U, // VPADDSWZ256rrk + 0U, // VPADDSWZ256rrkz + 0U, // VPADDSWZrm + 0U, // VPADDSWZrmk + 0U, // VPADDSWZrmkz + 0U, // VPADDSWZrr + 0U, // VPADDSWZrrk + 0U, // VPADDSWZrrkz + 0U, // VPADDSWrm + 0U, // VPADDSWrr + 0U, // VPADDUSBYrm + 0U, // VPADDUSBYrr + 0U, // VPADDUSBZ128rm + 0U, // VPADDUSBZ128rmk + 0U, // VPADDUSBZ128rmkz + 0U, // VPADDUSBZ128rr + 0U, // VPADDUSBZ128rrk + 0U, // VPADDUSBZ128rrkz + 0U, // VPADDUSBZ256rm + 0U, // VPADDUSBZ256rmk + 0U, // VPADDUSBZ256rmkz + 0U, // VPADDUSBZ256rr + 0U, // VPADDUSBZ256rrk + 0U, // VPADDUSBZ256rrkz + 0U, // VPADDUSBZrm + 0U, // VPADDUSBZrmk + 0U, // VPADDUSBZrmkz + 0U, // VPADDUSBZrr + 0U, // VPADDUSBZrrk + 0U, // VPADDUSBZrrkz + 0U, // VPADDUSBrm + 0U, // VPADDUSBrr + 0U, // VPADDUSWYrm + 0U, // VPADDUSWYrr + 0U, // VPADDUSWZ128rm + 0U, // VPADDUSWZ128rmk + 0U, // VPADDUSWZ128rmkz + 0U, // VPADDUSWZ128rr + 0U, // VPADDUSWZ128rrk + 0U, // VPADDUSWZ128rrkz + 0U, // VPADDUSWZ256rm + 0U, // VPADDUSWZ256rmk + 0U, // VPADDUSWZ256rmkz + 0U, // VPADDUSWZ256rr + 0U, // VPADDUSWZ256rrk + 0U, // VPADDUSWZ256rrkz + 0U, // VPADDUSWZrm + 0U, // VPADDUSWZrmk + 0U, // VPADDUSWZrmkz + 0U, // VPADDUSWZrr + 0U, // VPADDUSWZrrk + 0U, // VPADDUSWZrrkz + 0U, // VPADDUSWrm + 0U, // VPADDUSWrr + 0U, // VPADDWYrm + 0U, // VPADDWYrr + 0U, // VPADDWZ128rm + 0U, // VPADDWZ128rmk + 0U, // VPADDWZ128rmkz + 0U, // VPADDWZ128rr + 0U, // VPADDWZ128rrk + 0U, // VPADDWZ128rrkz + 0U, // VPADDWZ256rm + 0U, // VPADDWZ256rmk + 0U, // VPADDWZ256rmkz + 0U, // VPADDWZ256rr + 0U, // VPADDWZ256rrk + 0U, // VPADDWZ256rrkz + 0U, // VPADDWZrm + 0U, // VPADDWZrmk + 0U, // VPADDWZrmkz + 0U, // VPADDWZrr + 0U, // VPADDWZrrk + 0U, // VPADDWZrrkz + 0U, // VPADDWrm + 0U, // VPADDWrr + 0U, // VPALIGNRYrmi + 0U, // VPALIGNRYrri + 0U, // VPALIGNRZ128rmi + 0U, // VPALIGNRZ128rmik + 0U, // VPALIGNRZ128rmikz + 0U, // VPALIGNRZ128rri + 0U, // VPALIGNRZ128rrik + 3U, // VPALIGNRZ128rrikz + 0U, // VPALIGNRZ256rmi + 0U, // VPALIGNRZ256rmik + 0U, // VPALIGNRZ256rmikz + 0U, // VPALIGNRZ256rri + 0U, // VPALIGNRZ256rrik + 3U, // VPALIGNRZ256rrikz + 0U, // VPALIGNRZrmi + 0U, // VPALIGNRZrmik + 0U, // VPALIGNRZrmikz + 0U, // VPALIGNRZrri + 0U, // VPALIGNRZrrik + 3U, // VPALIGNRZrrikz + 0U, // VPALIGNRrmi + 0U, // VPALIGNRrri + 0U, // VPANDDZ128rm + 0U, // VPANDDZ128rmb + 0U, // VPANDDZ128rmbk + 0U, // VPANDDZ128rmbkz + 0U, // VPANDDZ128rmk + 0U, // VPANDDZ128rmkz + 0U, // VPANDDZ128rr + 0U, // VPANDDZ128rrk + 0U, // VPANDDZ128rrkz + 0U, // VPANDDZ256rm + 0U, // VPANDDZ256rmb + 0U, // VPANDDZ256rmbk + 0U, // VPANDDZ256rmbkz + 0U, // VPANDDZ256rmk + 0U, // VPANDDZ256rmkz + 0U, // VPANDDZ256rr + 0U, // VPANDDZ256rrk + 0U, // VPANDDZ256rrkz + 0U, // VPANDDZrm + 0U, // VPANDDZrmb + 0U, // VPANDDZrmbk + 0U, // VPANDDZrmbkz + 0U, // VPANDDZrmk + 0U, // VPANDDZrmkz + 0U, // VPANDDZrr + 0U, // VPANDDZrrk + 0U, // VPANDDZrrkz + 0U, // VPANDNDZ128rm + 0U, // VPANDNDZ128rmb + 0U, // VPANDNDZ128rmbk + 0U, // VPANDNDZ128rmbkz + 0U, // VPANDNDZ128rmk + 0U, // VPANDNDZ128rmkz + 0U, // VPANDNDZ128rr + 0U, // VPANDNDZ128rrk + 0U, // VPANDNDZ128rrkz + 0U, // VPANDNDZ256rm + 0U, // VPANDNDZ256rmb + 0U, // VPANDNDZ256rmbk + 0U, // VPANDNDZ256rmbkz + 0U, // VPANDNDZ256rmk + 0U, // VPANDNDZ256rmkz + 0U, // VPANDNDZ256rr + 0U, // VPANDNDZ256rrk + 0U, // VPANDNDZ256rrkz + 0U, // VPANDNDZrm + 0U, // VPANDNDZrmb + 0U, // VPANDNDZrmbk + 0U, // VPANDNDZrmbkz + 0U, // VPANDNDZrmk + 0U, // VPANDNDZrmkz + 0U, // VPANDNDZrr + 0U, // VPANDNDZrrk + 0U, // VPANDNDZrrkz + 0U, // VPANDNQZ128rm + 0U, // VPANDNQZ128rmb + 0U, // VPANDNQZ128rmbk + 0U, // VPANDNQZ128rmbkz + 0U, // VPANDNQZ128rmk + 0U, // VPANDNQZ128rmkz + 0U, // VPANDNQZ128rr + 0U, // VPANDNQZ128rrk + 0U, // VPANDNQZ128rrkz + 0U, // VPANDNQZ256rm + 0U, // VPANDNQZ256rmb + 0U, // VPANDNQZ256rmbk + 0U, // VPANDNQZ256rmbkz + 0U, // VPANDNQZ256rmk + 0U, // VPANDNQZ256rmkz + 0U, // VPANDNQZ256rr + 0U, // VPANDNQZ256rrk + 0U, // VPANDNQZ256rrkz + 0U, // VPANDNQZrm + 0U, // VPANDNQZrmb + 0U, // VPANDNQZrmbk + 0U, // VPANDNQZrmbkz + 0U, // VPANDNQZrmk + 0U, // VPANDNQZrmkz + 0U, // VPANDNQZrr + 0U, // VPANDNQZrrk + 0U, // VPANDNQZrrkz + 0U, // VPANDNYrm + 0U, // VPANDNYrr + 0U, // VPANDNrm + 0U, // VPANDNrr + 0U, // VPANDQZ128rm + 0U, // VPANDQZ128rmb + 0U, // VPANDQZ128rmbk + 0U, // VPANDQZ128rmbkz + 0U, // VPANDQZ128rmk + 0U, // VPANDQZ128rmkz + 0U, // VPANDQZ128rr + 0U, // VPANDQZ128rrk + 0U, // VPANDQZ128rrkz + 0U, // VPANDQZ256rm + 0U, // VPANDQZ256rmb + 0U, // VPANDQZ256rmbk + 0U, // VPANDQZ256rmbkz + 0U, // VPANDQZ256rmk + 0U, // VPANDQZ256rmkz + 0U, // VPANDQZ256rr + 0U, // VPANDQZ256rrk + 0U, // VPANDQZ256rrkz + 0U, // VPANDQZrm + 0U, // VPANDQZrmb + 0U, // VPANDQZrmbk + 0U, // VPANDQZrmbkz + 0U, // VPANDQZrmk + 0U, // VPANDQZrmkz + 0U, // VPANDQZrr + 0U, // VPANDQZrrk + 0U, // VPANDQZrrkz + 0U, // VPANDYrm + 0U, // VPANDYrr + 0U, // VPANDrm + 0U, // VPANDrr + 0U, // VPAVGBYrm + 0U, // VPAVGBYrr + 0U, // VPAVGBZ128rm + 0U, // VPAVGBZ128rmk + 0U, // VPAVGBZ128rmkz + 0U, // VPAVGBZ128rr + 0U, // VPAVGBZ128rrk + 0U, // VPAVGBZ128rrkz + 0U, // VPAVGBZ256rm + 0U, // VPAVGBZ256rmk + 0U, // VPAVGBZ256rmkz + 0U, // VPAVGBZ256rr + 0U, // VPAVGBZ256rrk + 0U, // VPAVGBZ256rrkz + 0U, // VPAVGBZrm + 0U, // VPAVGBZrmk + 0U, // VPAVGBZrmkz + 0U, // VPAVGBZrr + 0U, // VPAVGBZrrk + 0U, // VPAVGBZrrkz + 0U, // VPAVGBrm + 0U, // VPAVGBrr + 0U, // VPAVGWYrm + 0U, // VPAVGWYrr + 0U, // VPAVGWZ128rm + 0U, // VPAVGWZ128rmk + 0U, // VPAVGWZ128rmkz + 0U, // VPAVGWZ128rr + 0U, // VPAVGWZ128rrk + 0U, // VPAVGWZ128rrkz + 0U, // VPAVGWZ256rm + 0U, // VPAVGWZ256rmk + 0U, // VPAVGWZ256rmkz + 0U, // VPAVGWZ256rr + 0U, // VPAVGWZ256rrk + 0U, // VPAVGWZ256rrkz + 0U, // VPAVGWZrm + 0U, // VPAVGWZrmk + 0U, // VPAVGWZrmkz + 0U, // VPAVGWZrr + 0U, // VPAVGWZrrk + 0U, // VPAVGWZrrkz + 0U, // VPAVGWrm + 0U, // VPAVGWrr + 0U, // VPBLENDDYrmi + 0U, // VPBLENDDYrri + 0U, // VPBLENDDrmi + 0U, // VPBLENDDrri + 0U, // VPBLENDMBZ128rm + 0U, // VPBLENDMBZ128rmk + 0U, // VPBLENDMBZ128rmkz + 0U, // VPBLENDMBZ128rr + 0U, // VPBLENDMBZ128rrk + 0U, // VPBLENDMBZ128rrkz + 0U, // VPBLENDMBZ256rm + 0U, // VPBLENDMBZ256rmk + 0U, // VPBLENDMBZ256rmkz + 0U, // VPBLENDMBZ256rr + 0U, // VPBLENDMBZ256rrk + 0U, // VPBLENDMBZ256rrkz + 0U, // VPBLENDMBZrm + 0U, // VPBLENDMBZrmk + 0U, // VPBLENDMBZrmkz + 0U, // VPBLENDMBZrr + 0U, // VPBLENDMBZrrk + 0U, // VPBLENDMBZrrkz + 0U, // VPBLENDMDZ128rm + 0U, // VPBLENDMDZ128rmb + 0U, // VPBLENDMDZ128rmbk + 0U, // VPBLENDMDZ128rmbkz + 0U, // VPBLENDMDZ128rmk + 0U, // VPBLENDMDZ128rmkz + 0U, // VPBLENDMDZ128rr + 0U, // VPBLENDMDZ128rrk + 0U, // VPBLENDMDZ128rrkz + 0U, // VPBLENDMDZ256rm + 0U, // VPBLENDMDZ256rmb + 0U, // VPBLENDMDZ256rmbk + 0U, // VPBLENDMDZ256rmbkz + 0U, // VPBLENDMDZ256rmk + 0U, // VPBLENDMDZ256rmkz + 0U, // VPBLENDMDZ256rr + 0U, // VPBLENDMDZ256rrk + 0U, // VPBLENDMDZ256rrkz + 0U, // VPBLENDMDZrm + 0U, // VPBLENDMDZrmb + 0U, // VPBLENDMDZrmbk + 0U, // VPBLENDMDZrmbkz + 0U, // VPBLENDMDZrmk + 0U, // VPBLENDMDZrmkz + 0U, // VPBLENDMDZrr + 0U, // VPBLENDMDZrrk + 0U, // VPBLENDMDZrrkz + 0U, // VPBLENDMQZ128rm + 0U, // VPBLENDMQZ128rmb + 0U, // VPBLENDMQZ128rmbk + 0U, // VPBLENDMQZ128rmbkz + 0U, // VPBLENDMQZ128rmk + 0U, // VPBLENDMQZ128rmkz + 0U, // VPBLENDMQZ128rr + 0U, // VPBLENDMQZ128rrk + 0U, // VPBLENDMQZ128rrkz + 0U, // VPBLENDMQZ256rm + 0U, // VPBLENDMQZ256rmb + 0U, // VPBLENDMQZ256rmbk + 0U, // VPBLENDMQZ256rmbkz + 0U, // VPBLENDMQZ256rmk + 0U, // VPBLENDMQZ256rmkz + 0U, // VPBLENDMQZ256rr + 0U, // VPBLENDMQZ256rrk + 0U, // VPBLENDMQZ256rrkz + 0U, // VPBLENDMQZrm + 0U, // VPBLENDMQZrmb + 0U, // VPBLENDMQZrmbk + 0U, // VPBLENDMQZrmbkz + 0U, // VPBLENDMQZrmk + 0U, // VPBLENDMQZrmkz + 0U, // VPBLENDMQZrr + 0U, // VPBLENDMQZrrk + 0U, // VPBLENDMQZrrkz + 0U, // VPBLENDMWZ128rm + 0U, // VPBLENDMWZ128rmk + 0U, // VPBLENDMWZ128rmkz + 0U, // VPBLENDMWZ128rr + 0U, // VPBLENDMWZ128rrk + 0U, // VPBLENDMWZ128rrkz + 0U, // VPBLENDMWZ256rm + 0U, // VPBLENDMWZ256rmk + 0U, // VPBLENDMWZ256rmkz + 0U, // VPBLENDMWZ256rr + 0U, // VPBLENDMWZ256rrk + 0U, // VPBLENDMWZ256rrkz + 0U, // VPBLENDMWZrm + 0U, // VPBLENDMWZrmk + 0U, // VPBLENDMWZrmkz + 0U, // VPBLENDMWZrr + 0U, // VPBLENDMWZrrk + 0U, // VPBLENDMWZrrkz + 0U, // VPBLENDVBYrm + 0U, // VPBLENDVBYrr + 0U, // VPBLENDVBrm + 0U, // VPBLENDVBrr + 0U, // VPBLENDWYrmi + 0U, // VPBLENDWYrri + 0U, // VPBLENDWrmi + 0U, // VPBLENDWrri + 0U, // VPBROADCASTBYrm + 0U, // VPBROADCASTBYrr + 0U, // VPBROADCASTBZ128m + 0U, // VPBROADCASTBZ128mk + 0U, // VPBROADCASTBZ128mkz + 0U, // VPBROADCASTBZ128r + 0U, // VPBROADCASTBZ128rk + 0U, // VPBROADCASTBZ128rkz + 0U, // VPBROADCASTBZ256m + 0U, // VPBROADCASTBZ256mk + 0U, // VPBROADCASTBZ256mkz + 0U, // VPBROADCASTBZ256r + 0U, // VPBROADCASTBZ256rk + 0U, // VPBROADCASTBZ256rkz + 0U, // VPBROADCASTBZm + 0U, // VPBROADCASTBZmk + 0U, // VPBROADCASTBZmkz + 0U, // VPBROADCASTBZr + 0U, // VPBROADCASTBZrk + 0U, // VPBROADCASTBZrkz + 0U, // VPBROADCASTBrZ128r + 0U, // VPBROADCASTBrZ128rk + 0U, // VPBROADCASTBrZ128rkz + 0U, // VPBROADCASTBrZ256r + 0U, // VPBROADCASTBrZ256rk + 0U, // VPBROADCASTBrZ256rkz + 0U, // VPBROADCASTBrZr + 0U, // VPBROADCASTBrZrk + 0U, // VPBROADCASTBrZrkz + 0U, // VPBROADCASTBrm + 0U, // VPBROADCASTBrr + 0U, // VPBROADCASTDYrm + 0U, // VPBROADCASTDYrr + 0U, // VPBROADCASTDZ128m + 0U, // VPBROADCASTDZ128mk + 0U, // VPBROADCASTDZ128mkz + 0U, // VPBROADCASTDZ128r + 0U, // VPBROADCASTDZ128rk + 0U, // VPBROADCASTDZ128rkz + 0U, // VPBROADCASTDZ256m + 0U, // VPBROADCASTDZ256mk + 0U, // VPBROADCASTDZ256mkz + 0U, // VPBROADCASTDZ256r + 0U, // VPBROADCASTDZ256rk + 0U, // VPBROADCASTDZ256rkz + 0U, // VPBROADCASTDZm + 0U, // VPBROADCASTDZmk + 0U, // VPBROADCASTDZmkz + 0U, // VPBROADCASTDZr + 0U, // VPBROADCASTDZrk + 0U, // VPBROADCASTDZrkz + 0U, // VPBROADCASTDrZ128r + 0U, // VPBROADCASTDrZ128rk + 0U, // VPBROADCASTDrZ128rkz + 0U, // VPBROADCASTDrZ256r + 0U, // VPBROADCASTDrZ256rk + 0U, // VPBROADCASTDrZ256rkz + 0U, // VPBROADCASTDrZr + 0U, // VPBROADCASTDrZrk + 0U, // VPBROADCASTDrZrkz + 0U, // VPBROADCASTDrm + 0U, // VPBROADCASTDrr + 0U, // VPBROADCASTMB2QZ128rr + 0U, // VPBROADCASTMB2QZ256rr + 0U, // VPBROADCASTMB2QZrr + 0U, // VPBROADCASTMW2DZ128rr + 0U, // VPBROADCASTMW2DZ256rr + 0U, // VPBROADCASTMW2DZrr + 0U, // VPBROADCASTQYrm + 0U, // VPBROADCASTQYrr + 0U, // VPBROADCASTQZ128m + 0U, // VPBROADCASTQZ128mk + 0U, // VPBROADCASTQZ128mkz + 0U, // VPBROADCASTQZ128r + 0U, // VPBROADCASTQZ128rk + 0U, // VPBROADCASTQZ128rkz + 0U, // VPBROADCASTQZ256m + 0U, // VPBROADCASTQZ256mk + 0U, // VPBROADCASTQZ256mkz + 0U, // VPBROADCASTQZ256r + 0U, // VPBROADCASTQZ256rk + 0U, // VPBROADCASTQZ256rkz + 0U, // VPBROADCASTQZm + 0U, // VPBROADCASTQZmk + 0U, // VPBROADCASTQZmkz + 0U, // VPBROADCASTQZr + 0U, // VPBROADCASTQZrk + 0U, // VPBROADCASTQZrkz + 0U, // VPBROADCASTQrZ128r + 0U, // VPBROADCASTQrZ128rk + 0U, // VPBROADCASTQrZ128rkz + 0U, // VPBROADCASTQrZ256r + 0U, // VPBROADCASTQrZ256rk + 0U, // VPBROADCASTQrZ256rkz + 0U, // VPBROADCASTQrZr + 0U, // VPBROADCASTQrZrk + 0U, // VPBROADCASTQrZrkz + 0U, // VPBROADCASTQrm + 0U, // VPBROADCASTQrr + 0U, // VPBROADCASTWYrm + 0U, // VPBROADCASTWYrr + 0U, // VPBROADCASTWZ128m + 0U, // VPBROADCASTWZ128mk + 0U, // VPBROADCASTWZ128mkz + 0U, // VPBROADCASTWZ128r + 0U, // VPBROADCASTWZ128rk + 0U, // VPBROADCASTWZ128rkz + 0U, // VPBROADCASTWZ256m + 0U, // VPBROADCASTWZ256mk + 0U, // VPBROADCASTWZ256mkz + 0U, // VPBROADCASTWZ256r + 0U, // VPBROADCASTWZ256rk + 0U, // VPBROADCASTWZ256rkz + 0U, // VPBROADCASTWZm + 0U, // VPBROADCASTWZmk + 0U, // VPBROADCASTWZmkz + 0U, // VPBROADCASTWZr + 0U, // VPBROADCASTWZrk + 0U, // VPBROADCASTWZrkz + 0U, // VPBROADCASTWrZ128r + 0U, // VPBROADCASTWrZ128rk + 0U, // VPBROADCASTWrZ128rkz + 0U, // VPBROADCASTWrZ256r + 0U, // VPBROADCASTWrZ256rk + 0U, // VPBROADCASTWrZ256rkz + 0U, // VPBROADCASTWrZr + 0U, // VPBROADCASTWrZrk + 0U, // VPBROADCASTWrZrkz + 0U, // VPBROADCASTWrm + 0U, // VPBROADCASTWrr + 0U, // VPCLMULQDQYrm + 0U, // VPCLMULQDQYrr + 0U, // VPCLMULQDQZ128rm + 0U, // VPCLMULQDQZ128rr + 0U, // VPCLMULQDQZ256rm + 0U, // VPCLMULQDQZ256rr + 0U, // VPCLMULQDQZrm + 0U, // VPCLMULQDQZrr + 0U, // VPCLMULQDQrm + 0U, // VPCLMULQDQrr + 0U, // VPCMOVYrmr + 0U, // VPCMOVYrrm + 0U, // VPCMOVYrrr + 0U, // VPCMOVYrrr_REV + 0U, // VPCMOVrmr + 0U, // VPCMOVrrm + 0U, // VPCMOVrrr + 0U, // VPCMOVrrr_REV + 0U, // VPCMPBZ128rmi + 0U, // VPCMPBZ128rmi_alt + 0U, // VPCMPBZ128rmik + 0U, // VPCMPBZ128rmik_alt + 0U, // VPCMPBZ128rri + 0U, // VPCMPBZ128rri_alt + 1U, // VPCMPBZ128rrik + 1U, // VPCMPBZ128rrik_alt + 0U, // VPCMPBZ256rmi + 0U, // VPCMPBZ256rmi_alt + 0U, // VPCMPBZ256rmik + 0U, // VPCMPBZ256rmik_alt + 0U, // VPCMPBZ256rri + 0U, // VPCMPBZ256rri_alt + 1U, // VPCMPBZ256rrik + 1U, // VPCMPBZ256rrik_alt + 0U, // VPCMPBZrmi + 0U, // VPCMPBZrmi_alt + 0U, // VPCMPBZrmik + 0U, // VPCMPBZrmik_alt + 0U, // VPCMPBZrri + 0U, // VPCMPBZrri_alt + 1U, // VPCMPBZrrik + 1U, // VPCMPBZrrik_alt + 0U, // VPCMPDZ128rmi + 0U, // VPCMPDZ128rmi_alt + 0U, // VPCMPDZ128rmib + 0U, // VPCMPDZ128rmib_alt + 1U, // VPCMPDZ128rmibk + 1U, // VPCMPDZ128rmibk_alt + 0U, // VPCMPDZ128rmik + 0U, // VPCMPDZ128rmik_alt + 0U, // VPCMPDZ128rri + 0U, // VPCMPDZ128rri_alt + 1U, // VPCMPDZ128rrik + 1U, // VPCMPDZ128rrik_alt + 0U, // VPCMPDZ256rmi + 0U, // VPCMPDZ256rmi_alt + 0U, // VPCMPDZ256rmib + 0U, // VPCMPDZ256rmib_alt + 1U, // VPCMPDZ256rmibk + 1U, // VPCMPDZ256rmibk_alt + 0U, // VPCMPDZ256rmik + 0U, // VPCMPDZ256rmik_alt + 0U, // VPCMPDZ256rri + 0U, // VPCMPDZ256rri_alt + 1U, // VPCMPDZ256rrik + 1U, // VPCMPDZ256rrik_alt + 0U, // VPCMPDZrmi + 0U, // VPCMPDZrmi_alt + 0U, // VPCMPDZrmib + 0U, // VPCMPDZrmib_alt + 1U, // VPCMPDZrmibk + 1U, // VPCMPDZrmibk_alt + 0U, // VPCMPDZrmik + 0U, // VPCMPDZrmik_alt + 0U, // VPCMPDZrri + 0U, // VPCMPDZrri_alt + 1U, // VPCMPDZrrik + 1U, // VPCMPDZrrik_alt + 0U, // VPCMPEQBYrm + 0U, // VPCMPEQBYrr + 0U, // VPCMPEQBZ128rm + 0U, // VPCMPEQBZ128rmk + 0U, // VPCMPEQBZ128rr + 0U, // VPCMPEQBZ128rrk + 0U, // VPCMPEQBZ256rm + 0U, // VPCMPEQBZ256rmk + 0U, // VPCMPEQBZ256rr + 0U, // VPCMPEQBZ256rrk + 0U, // VPCMPEQBZrm + 0U, // VPCMPEQBZrmk + 0U, // VPCMPEQBZrr + 0U, // VPCMPEQBZrrk + 0U, // VPCMPEQBrm + 0U, // VPCMPEQBrr + 0U, // VPCMPEQDYrm + 0U, // VPCMPEQDYrr + 0U, // VPCMPEQDZ128rm + 0U, // VPCMPEQDZ128rmb + 0U, // VPCMPEQDZ128rmbk + 0U, // VPCMPEQDZ128rmk + 0U, // VPCMPEQDZ128rr + 0U, // VPCMPEQDZ128rrk + 0U, // VPCMPEQDZ256rm + 0U, // VPCMPEQDZ256rmb + 0U, // VPCMPEQDZ256rmbk + 0U, // VPCMPEQDZ256rmk + 0U, // VPCMPEQDZ256rr + 0U, // VPCMPEQDZ256rrk + 0U, // VPCMPEQDZrm + 0U, // VPCMPEQDZrmb + 0U, // VPCMPEQDZrmbk + 0U, // VPCMPEQDZrmk + 0U, // VPCMPEQDZrr + 0U, // VPCMPEQDZrrk + 0U, // VPCMPEQDrm + 0U, // VPCMPEQDrr + 0U, // VPCMPEQQYrm + 0U, // VPCMPEQQYrr + 0U, // VPCMPEQQZ128rm + 0U, // VPCMPEQQZ128rmb + 0U, // VPCMPEQQZ128rmbk + 0U, // VPCMPEQQZ128rmk + 0U, // VPCMPEQQZ128rr + 0U, // VPCMPEQQZ128rrk + 0U, // VPCMPEQQZ256rm + 0U, // VPCMPEQQZ256rmb + 0U, // VPCMPEQQZ256rmbk + 0U, // VPCMPEQQZ256rmk + 0U, // VPCMPEQQZ256rr + 0U, // VPCMPEQQZ256rrk + 0U, // VPCMPEQQZrm + 0U, // VPCMPEQQZrmb + 0U, // VPCMPEQQZrmbk + 0U, // VPCMPEQQZrmk + 0U, // VPCMPEQQZrr + 0U, // VPCMPEQQZrrk + 0U, // VPCMPEQQrm + 0U, // VPCMPEQQrr + 0U, // VPCMPEQWYrm + 0U, // VPCMPEQWYrr + 0U, // VPCMPEQWZ128rm + 0U, // VPCMPEQWZ128rmk + 0U, // VPCMPEQWZ128rr + 0U, // VPCMPEQWZ128rrk + 0U, // VPCMPEQWZ256rm + 0U, // VPCMPEQWZ256rmk + 0U, // VPCMPEQWZ256rr + 0U, // VPCMPEQWZ256rrk + 0U, // VPCMPEQWZrm + 0U, // VPCMPEQWZrmk + 0U, // VPCMPEQWZrr + 0U, // VPCMPEQWZrrk + 0U, // VPCMPEQWrm + 0U, // VPCMPEQWrr + 0U, // VPCMPESTRIrm + 0U, // VPCMPESTRIrr + 0U, // VPCMPESTRMrm + 0U, // VPCMPESTRMrr + 0U, // VPCMPGTBYrm + 0U, // VPCMPGTBYrr + 0U, // VPCMPGTBZ128rm + 0U, // VPCMPGTBZ128rmk + 0U, // VPCMPGTBZ128rr + 0U, // VPCMPGTBZ128rrk + 0U, // VPCMPGTBZ256rm + 0U, // VPCMPGTBZ256rmk + 0U, // VPCMPGTBZ256rr + 0U, // VPCMPGTBZ256rrk + 0U, // VPCMPGTBZrm + 0U, // VPCMPGTBZrmk + 0U, // VPCMPGTBZrr + 0U, // VPCMPGTBZrrk + 0U, // VPCMPGTBrm + 0U, // VPCMPGTBrr + 0U, // VPCMPGTDYrm + 0U, // VPCMPGTDYrr + 0U, // VPCMPGTDZ128rm + 0U, // VPCMPGTDZ128rmb + 0U, // VPCMPGTDZ128rmbk + 0U, // VPCMPGTDZ128rmk + 0U, // VPCMPGTDZ128rr + 0U, // VPCMPGTDZ128rrk + 0U, // VPCMPGTDZ256rm + 0U, // VPCMPGTDZ256rmb + 0U, // VPCMPGTDZ256rmbk + 0U, // VPCMPGTDZ256rmk + 0U, // VPCMPGTDZ256rr + 0U, // VPCMPGTDZ256rrk + 0U, // VPCMPGTDZrm + 0U, // VPCMPGTDZrmb + 0U, // VPCMPGTDZrmbk + 0U, // VPCMPGTDZrmk + 0U, // VPCMPGTDZrr + 0U, // VPCMPGTDZrrk + 0U, // VPCMPGTDrm + 0U, // VPCMPGTDrr + 0U, // VPCMPGTQYrm + 0U, // VPCMPGTQYrr + 0U, // VPCMPGTQZ128rm + 0U, // VPCMPGTQZ128rmb + 0U, // VPCMPGTQZ128rmbk + 0U, // VPCMPGTQZ128rmk + 0U, // VPCMPGTQZ128rr + 0U, // VPCMPGTQZ128rrk + 0U, // VPCMPGTQZ256rm + 0U, // VPCMPGTQZ256rmb + 0U, // VPCMPGTQZ256rmbk + 0U, // VPCMPGTQZ256rmk + 0U, // VPCMPGTQZ256rr + 0U, // VPCMPGTQZ256rrk + 0U, // VPCMPGTQZrm + 0U, // VPCMPGTQZrmb + 0U, // VPCMPGTQZrmbk + 0U, // VPCMPGTQZrmk + 0U, // VPCMPGTQZrr + 0U, // VPCMPGTQZrrk + 0U, // VPCMPGTQrm + 0U, // VPCMPGTQrr + 0U, // VPCMPGTWYrm + 0U, // VPCMPGTWYrr + 0U, // VPCMPGTWZ128rm + 0U, // VPCMPGTWZ128rmk + 0U, // VPCMPGTWZ128rr + 0U, // VPCMPGTWZ128rrk + 0U, // VPCMPGTWZ256rm + 0U, // VPCMPGTWZ256rmk + 0U, // VPCMPGTWZ256rr + 0U, // VPCMPGTWZ256rrk + 0U, // VPCMPGTWZrm + 0U, // VPCMPGTWZrmk + 0U, // VPCMPGTWZrr + 0U, // VPCMPGTWZrrk + 0U, // VPCMPGTWrm + 0U, // VPCMPGTWrr + 0U, // VPCMPISTRIrm + 0U, // VPCMPISTRIrr + 0U, // VPCMPISTRMrm + 0U, // VPCMPISTRMrr + 0U, // VPCMPQZ128rmi + 0U, // VPCMPQZ128rmi_alt + 0U, // VPCMPQZ128rmib + 0U, // VPCMPQZ128rmib_alt + 1U, // VPCMPQZ128rmibk + 1U, // VPCMPQZ128rmibk_alt + 0U, // VPCMPQZ128rmik + 0U, // VPCMPQZ128rmik_alt + 0U, // VPCMPQZ128rri + 0U, // VPCMPQZ128rri_alt + 1U, // VPCMPQZ128rrik + 1U, // VPCMPQZ128rrik_alt + 0U, // VPCMPQZ256rmi + 0U, // VPCMPQZ256rmi_alt + 0U, // VPCMPQZ256rmib + 0U, // VPCMPQZ256rmib_alt + 1U, // VPCMPQZ256rmibk + 1U, // VPCMPQZ256rmibk_alt + 0U, // VPCMPQZ256rmik + 0U, // VPCMPQZ256rmik_alt + 0U, // VPCMPQZ256rri + 0U, // VPCMPQZ256rri_alt + 1U, // VPCMPQZ256rrik + 1U, // VPCMPQZ256rrik_alt + 0U, // VPCMPQZrmi + 0U, // VPCMPQZrmi_alt + 0U, // VPCMPQZrmib + 0U, // VPCMPQZrmib_alt + 1U, // VPCMPQZrmibk + 1U, // VPCMPQZrmibk_alt + 0U, // VPCMPQZrmik + 0U, // VPCMPQZrmik_alt + 0U, // VPCMPQZrri + 0U, // VPCMPQZrri_alt + 1U, // VPCMPQZrrik + 1U, // VPCMPQZrrik_alt + 0U, // VPCMPUBZ128rmi + 0U, // VPCMPUBZ128rmi_alt + 0U, // VPCMPUBZ128rmik + 0U, // VPCMPUBZ128rmik_alt + 0U, // VPCMPUBZ128rri + 0U, // VPCMPUBZ128rri_alt + 1U, // VPCMPUBZ128rrik + 1U, // VPCMPUBZ128rrik_alt + 0U, // VPCMPUBZ256rmi + 0U, // VPCMPUBZ256rmi_alt + 0U, // VPCMPUBZ256rmik + 0U, // VPCMPUBZ256rmik_alt + 0U, // VPCMPUBZ256rri + 0U, // VPCMPUBZ256rri_alt + 1U, // VPCMPUBZ256rrik + 1U, // VPCMPUBZ256rrik_alt + 0U, // VPCMPUBZrmi + 0U, // VPCMPUBZrmi_alt + 0U, // VPCMPUBZrmik + 0U, // VPCMPUBZrmik_alt + 0U, // VPCMPUBZrri + 0U, // VPCMPUBZrri_alt + 1U, // VPCMPUBZrrik + 1U, // VPCMPUBZrrik_alt + 0U, // VPCMPUDZ128rmi + 0U, // VPCMPUDZ128rmi_alt + 0U, // VPCMPUDZ128rmib + 0U, // VPCMPUDZ128rmib_alt + 1U, // VPCMPUDZ128rmibk + 1U, // VPCMPUDZ128rmibk_alt + 0U, // VPCMPUDZ128rmik + 0U, // VPCMPUDZ128rmik_alt + 0U, // VPCMPUDZ128rri + 0U, // VPCMPUDZ128rri_alt + 1U, // VPCMPUDZ128rrik + 1U, // VPCMPUDZ128rrik_alt + 0U, // VPCMPUDZ256rmi + 0U, // VPCMPUDZ256rmi_alt + 0U, // VPCMPUDZ256rmib + 0U, // VPCMPUDZ256rmib_alt + 1U, // VPCMPUDZ256rmibk + 1U, // VPCMPUDZ256rmibk_alt + 0U, // VPCMPUDZ256rmik + 0U, // VPCMPUDZ256rmik_alt + 0U, // VPCMPUDZ256rri + 0U, // VPCMPUDZ256rri_alt + 1U, // VPCMPUDZ256rrik + 1U, // VPCMPUDZ256rrik_alt + 0U, // VPCMPUDZrmi + 0U, // VPCMPUDZrmi_alt + 0U, // VPCMPUDZrmib + 0U, // VPCMPUDZrmib_alt + 1U, // VPCMPUDZrmibk + 1U, // VPCMPUDZrmibk_alt + 0U, // VPCMPUDZrmik + 0U, // VPCMPUDZrmik_alt + 0U, // VPCMPUDZrri + 0U, // VPCMPUDZrri_alt + 1U, // VPCMPUDZrrik + 1U, // VPCMPUDZrrik_alt + 0U, // VPCMPUQZ128rmi + 0U, // VPCMPUQZ128rmi_alt + 0U, // VPCMPUQZ128rmib + 0U, // VPCMPUQZ128rmib_alt + 1U, // VPCMPUQZ128rmibk + 1U, // VPCMPUQZ128rmibk_alt + 0U, // VPCMPUQZ128rmik + 0U, // VPCMPUQZ128rmik_alt + 0U, // VPCMPUQZ128rri + 0U, // VPCMPUQZ128rri_alt + 1U, // VPCMPUQZ128rrik + 1U, // VPCMPUQZ128rrik_alt + 0U, // VPCMPUQZ256rmi + 0U, // VPCMPUQZ256rmi_alt + 0U, // VPCMPUQZ256rmib + 0U, // VPCMPUQZ256rmib_alt + 1U, // VPCMPUQZ256rmibk + 1U, // VPCMPUQZ256rmibk_alt + 0U, // VPCMPUQZ256rmik + 0U, // VPCMPUQZ256rmik_alt + 0U, // VPCMPUQZ256rri + 0U, // VPCMPUQZ256rri_alt + 1U, // VPCMPUQZ256rrik + 1U, // VPCMPUQZ256rrik_alt + 0U, // VPCMPUQZrmi + 0U, // VPCMPUQZrmi_alt + 0U, // VPCMPUQZrmib + 0U, // VPCMPUQZrmib_alt + 1U, // VPCMPUQZrmibk + 1U, // VPCMPUQZrmibk_alt + 0U, // VPCMPUQZrmik + 0U, // VPCMPUQZrmik_alt + 0U, // VPCMPUQZrri + 0U, // VPCMPUQZrri_alt + 1U, // VPCMPUQZrrik + 1U, // VPCMPUQZrrik_alt + 0U, // VPCMPUWZ128rmi + 0U, // VPCMPUWZ128rmi_alt + 0U, // VPCMPUWZ128rmik + 0U, // VPCMPUWZ128rmik_alt + 0U, // VPCMPUWZ128rri + 0U, // VPCMPUWZ128rri_alt + 1U, // VPCMPUWZ128rrik + 1U, // VPCMPUWZ128rrik_alt + 0U, // VPCMPUWZ256rmi + 0U, // VPCMPUWZ256rmi_alt + 0U, // VPCMPUWZ256rmik + 0U, // VPCMPUWZ256rmik_alt + 0U, // VPCMPUWZ256rri + 0U, // VPCMPUWZ256rri_alt + 1U, // VPCMPUWZ256rrik + 1U, // VPCMPUWZ256rrik_alt + 0U, // VPCMPUWZrmi + 0U, // VPCMPUWZrmi_alt + 0U, // VPCMPUWZrmik + 0U, // VPCMPUWZrmik_alt + 0U, // VPCMPUWZrri + 0U, // VPCMPUWZrri_alt + 1U, // VPCMPUWZrrik + 1U, // VPCMPUWZrrik_alt + 0U, // VPCMPWZ128rmi + 0U, // VPCMPWZ128rmi_alt + 0U, // VPCMPWZ128rmik + 0U, // VPCMPWZ128rmik_alt + 0U, // VPCMPWZ128rri + 0U, // VPCMPWZ128rri_alt + 1U, // VPCMPWZ128rrik + 1U, // VPCMPWZ128rrik_alt + 0U, // VPCMPWZ256rmi + 0U, // VPCMPWZ256rmi_alt + 0U, // VPCMPWZ256rmik + 0U, // VPCMPWZ256rmik_alt + 0U, // VPCMPWZ256rri + 0U, // VPCMPWZ256rri_alt + 1U, // VPCMPWZ256rrik + 1U, // VPCMPWZ256rrik_alt + 0U, // VPCMPWZrmi + 0U, // VPCMPWZrmi_alt + 0U, // VPCMPWZrmik + 0U, // VPCMPWZrmik_alt + 0U, // VPCMPWZrri + 0U, // VPCMPWZrri_alt + 1U, // VPCMPWZrrik + 1U, // VPCMPWZrrik_alt + 0U, // VPCOMBmi + 0U, // VPCOMBmi_alt + 0U, // VPCOMBri + 0U, // VPCOMBri_alt + 0U, // VPCOMDmi + 0U, // VPCOMDmi_alt + 0U, // VPCOMDri + 0U, // VPCOMDri_alt + 0U, // VPCOMPRESSBZ128mr + 0U, // VPCOMPRESSBZ128mrk + 0U, // VPCOMPRESSBZ128rr + 0U, // VPCOMPRESSBZ128rrk + 0U, // VPCOMPRESSBZ128rrkz + 0U, // VPCOMPRESSBZ256mr + 0U, // VPCOMPRESSBZ256mrk + 0U, // VPCOMPRESSBZ256rr + 0U, // VPCOMPRESSBZ256rrk + 0U, // VPCOMPRESSBZ256rrkz + 0U, // VPCOMPRESSBZmr + 0U, // VPCOMPRESSBZmrk + 0U, // VPCOMPRESSBZrr + 0U, // VPCOMPRESSBZrrk + 0U, // VPCOMPRESSBZrrkz + 0U, // VPCOMPRESSDZ128mr + 0U, // VPCOMPRESSDZ128mrk + 0U, // VPCOMPRESSDZ128rr + 0U, // VPCOMPRESSDZ128rrk + 0U, // VPCOMPRESSDZ128rrkz + 0U, // VPCOMPRESSDZ256mr + 0U, // VPCOMPRESSDZ256mrk + 0U, // VPCOMPRESSDZ256rr + 0U, // VPCOMPRESSDZ256rrk + 0U, // VPCOMPRESSDZ256rrkz + 0U, // VPCOMPRESSDZmr + 0U, // VPCOMPRESSDZmrk + 0U, // VPCOMPRESSDZrr + 0U, // VPCOMPRESSDZrrk + 0U, // VPCOMPRESSDZrrkz + 0U, // VPCOMPRESSQZ128mr + 0U, // VPCOMPRESSQZ128mrk + 0U, // VPCOMPRESSQZ128rr + 0U, // VPCOMPRESSQZ128rrk + 0U, // VPCOMPRESSQZ128rrkz + 0U, // VPCOMPRESSQZ256mr + 0U, // VPCOMPRESSQZ256mrk + 0U, // VPCOMPRESSQZ256rr + 0U, // VPCOMPRESSQZ256rrk + 0U, // VPCOMPRESSQZ256rrkz + 0U, // VPCOMPRESSQZmr + 0U, // VPCOMPRESSQZmrk + 0U, // VPCOMPRESSQZrr + 0U, // VPCOMPRESSQZrrk + 0U, // VPCOMPRESSQZrrkz + 0U, // VPCOMPRESSWZ128mr + 0U, // VPCOMPRESSWZ128mrk + 0U, // VPCOMPRESSWZ128rr + 0U, // VPCOMPRESSWZ128rrk + 0U, // VPCOMPRESSWZ128rrkz + 0U, // VPCOMPRESSWZ256mr + 0U, // VPCOMPRESSWZ256mrk + 0U, // VPCOMPRESSWZ256rr + 0U, // VPCOMPRESSWZ256rrk + 0U, // VPCOMPRESSWZ256rrkz + 0U, // VPCOMPRESSWZmr + 0U, // VPCOMPRESSWZmrk + 0U, // VPCOMPRESSWZrr + 0U, // VPCOMPRESSWZrrk + 0U, // VPCOMPRESSWZrrkz + 0U, // VPCOMQmi + 0U, // VPCOMQmi_alt + 0U, // VPCOMQri + 0U, // VPCOMQri_alt + 0U, // VPCOMUBmi + 0U, // VPCOMUBmi_alt + 0U, // VPCOMUBri + 0U, // VPCOMUBri_alt + 0U, // VPCOMUDmi + 0U, // VPCOMUDmi_alt + 0U, // VPCOMUDri + 0U, // VPCOMUDri_alt + 0U, // VPCOMUQmi + 0U, // VPCOMUQmi_alt + 0U, // VPCOMUQri + 0U, // VPCOMUQri_alt + 0U, // VPCOMUWmi + 0U, // VPCOMUWmi_alt + 0U, // VPCOMUWri + 0U, // VPCOMUWri_alt + 0U, // VPCOMWmi + 0U, // VPCOMWmi_alt + 0U, // VPCOMWri + 0U, // VPCOMWri_alt + 0U, // VPCONFLICTDZ128rm + 0U, // VPCONFLICTDZ128rmb + 0U, // VPCONFLICTDZ128rmbk + 0U, // VPCONFLICTDZ128rmbkz + 0U, // VPCONFLICTDZ128rmk + 0U, // VPCONFLICTDZ128rmkz + 0U, // VPCONFLICTDZ128rr + 0U, // VPCONFLICTDZ128rrk + 0U, // VPCONFLICTDZ128rrkz + 0U, // VPCONFLICTDZ256rm + 0U, // VPCONFLICTDZ256rmb + 0U, // VPCONFLICTDZ256rmbk + 0U, // VPCONFLICTDZ256rmbkz + 0U, // VPCONFLICTDZ256rmk + 0U, // VPCONFLICTDZ256rmkz + 0U, // VPCONFLICTDZ256rr + 0U, // VPCONFLICTDZ256rrk + 0U, // VPCONFLICTDZ256rrkz + 0U, // VPCONFLICTDZrm + 0U, // VPCONFLICTDZrmb + 0U, // VPCONFLICTDZrmbk + 0U, // VPCONFLICTDZrmbkz + 0U, // VPCONFLICTDZrmk + 0U, // VPCONFLICTDZrmkz + 0U, // VPCONFLICTDZrr + 0U, // VPCONFLICTDZrrk + 0U, // VPCONFLICTDZrrkz + 0U, // VPCONFLICTQZ128rm + 0U, // VPCONFLICTQZ128rmb + 0U, // VPCONFLICTQZ128rmbk + 0U, // VPCONFLICTQZ128rmbkz + 0U, // VPCONFLICTQZ128rmk + 0U, // VPCONFLICTQZ128rmkz + 0U, // VPCONFLICTQZ128rr + 0U, // VPCONFLICTQZ128rrk + 0U, // VPCONFLICTQZ128rrkz + 0U, // VPCONFLICTQZ256rm + 0U, // VPCONFLICTQZ256rmb + 0U, // VPCONFLICTQZ256rmbk + 0U, // VPCONFLICTQZ256rmbkz + 0U, // VPCONFLICTQZ256rmk + 0U, // VPCONFLICTQZ256rmkz + 0U, // VPCONFLICTQZ256rr + 0U, // VPCONFLICTQZ256rrk + 0U, // VPCONFLICTQZ256rrkz + 0U, // VPCONFLICTQZrm + 0U, // VPCONFLICTQZrmb + 0U, // VPCONFLICTQZrmbk + 0U, // VPCONFLICTQZrmbkz + 0U, // VPCONFLICTQZrmk + 0U, // VPCONFLICTQZrmkz + 0U, // VPCONFLICTQZrr + 0U, // VPCONFLICTQZrrk + 0U, // VPCONFLICTQZrrkz + 0U, // VPDPBUSDSZ128m + 0U, // VPDPBUSDSZ128mb + 0U, // VPDPBUSDSZ128mbk + 0U, // VPDPBUSDSZ128mbkz + 0U, // VPDPBUSDSZ128mk + 0U, // VPDPBUSDSZ128mkz + 0U, // VPDPBUSDSZ128r + 0U, // VPDPBUSDSZ128rk + 0U, // VPDPBUSDSZ128rkz + 0U, // VPDPBUSDSZ256m + 0U, // VPDPBUSDSZ256mb + 0U, // VPDPBUSDSZ256mbk + 0U, // VPDPBUSDSZ256mbkz + 0U, // VPDPBUSDSZ256mk + 0U, // VPDPBUSDSZ256mkz + 0U, // VPDPBUSDSZ256r + 0U, // VPDPBUSDSZ256rk + 0U, // VPDPBUSDSZ256rkz + 0U, // VPDPBUSDSZm + 0U, // VPDPBUSDSZmb + 0U, // VPDPBUSDSZmbk + 0U, // VPDPBUSDSZmbkz + 0U, // VPDPBUSDSZmk + 0U, // VPDPBUSDSZmkz + 0U, // VPDPBUSDSZr + 0U, // VPDPBUSDSZrk + 0U, // VPDPBUSDSZrkz + 0U, // VPDPBUSDZ128m + 0U, // VPDPBUSDZ128mb + 0U, // VPDPBUSDZ128mbk + 0U, // VPDPBUSDZ128mbkz + 0U, // VPDPBUSDZ128mk + 0U, // VPDPBUSDZ128mkz + 0U, // VPDPBUSDZ128r + 0U, // VPDPBUSDZ128rk + 0U, // VPDPBUSDZ128rkz + 0U, // VPDPBUSDZ256m + 0U, // VPDPBUSDZ256mb + 0U, // VPDPBUSDZ256mbk + 0U, // VPDPBUSDZ256mbkz + 0U, // VPDPBUSDZ256mk + 0U, // VPDPBUSDZ256mkz + 0U, // VPDPBUSDZ256r + 0U, // VPDPBUSDZ256rk + 0U, // VPDPBUSDZ256rkz + 0U, // VPDPBUSDZm + 0U, // VPDPBUSDZmb + 0U, // VPDPBUSDZmbk + 0U, // VPDPBUSDZmbkz + 0U, // VPDPBUSDZmk + 0U, // VPDPBUSDZmkz + 0U, // VPDPBUSDZr + 0U, // VPDPBUSDZrk + 0U, // VPDPBUSDZrkz + 0U, // VPDPWSSDSZ128m + 0U, // VPDPWSSDSZ128mb + 0U, // VPDPWSSDSZ128mbk + 0U, // VPDPWSSDSZ128mbkz + 0U, // VPDPWSSDSZ128mk + 0U, // VPDPWSSDSZ128mkz + 0U, // VPDPWSSDSZ128r + 0U, // VPDPWSSDSZ128rk + 0U, // VPDPWSSDSZ128rkz + 0U, // VPDPWSSDSZ256m + 0U, // VPDPWSSDSZ256mb + 0U, // VPDPWSSDSZ256mbk + 0U, // VPDPWSSDSZ256mbkz + 0U, // VPDPWSSDSZ256mk + 0U, // VPDPWSSDSZ256mkz + 0U, // VPDPWSSDSZ256r + 0U, // VPDPWSSDSZ256rk + 0U, // VPDPWSSDSZ256rkz + 0U, // VPDPWSSDSZm + 0U, // VPDPWSSDSZmb + 0U, // VPDPWSSDSZmbk + 0U, // VPDPWSSDSZmbkz + 0U, // VPDPWSSDSZmk + 0U, // VPDPWSSDSZmkz + 0U, // VPDPWSSDSZr + 0U, // VPDPWSSDSZrk + 0U, // VPDPWSSDSZrkz + 0U, // VPDPWSSDZ128m + 0U, // VPDPWSSDZ128mb + 0U, // VPDPWSSDZ128mbk + 0U, // VPDPWSSDZ128mbkz + 0U, // VPDPWSSDZ128mk + 0U, // VPDPWSSDZ128mkz + 0U, // VPDPWSSDZ128r + 0U, // VPDPWSSDZ128rk + 0U, // VPDPWSSDZ128rkz + 0U, // VPDPWSSDZ256m + 0U, // VPDPWSSDZ256mb + 0U, // VPDPWSSDZ256mbk + 0U, // VPDPWSSDZ256mbkz + 0U, // VPDPWSSDZ256mk + 0U, // VPDPWSSDZ256mkz + 0U, // VPDPWSSDZ256r + 0U, // VPDPWSSDZ256rk + 0U, // VPDPWSSDZ256rkz + 0U, // VPDPWSSDZm + 0U, // VPDPWSSDZmb + 0U, // VPDPWSSDZmbk + 0U, // VPDPWSSDZmbkz + 0U, // VPDPWSSDZmk + 0U, // VPDPWSSDZmkz + 0U, // VPDPWSSDZr + 0U, // VPDPWSSDZrk + 0U, // VPDPWSSDZrkz + 0U, // VPERM2F128rm + 0U, // VPERM2F128rr + 0U, // VPERM2I128rm + 0U, // VPERM2I128rr + 0U, // VPERMBZ128rm + 0U, // VPERMBZ128rmk + 0U, // VPERMBZ128rmkz + 0U, // VPERMBZ128rr + 0U, // VPERMBZ128rrk + 0U, // VPERMBZ128rrkz + 0U, // VPERMBZ256rm + 0U, // VPERMBZ256rmk + 0U, // VPERMBZ256rmkz + 0U, // VPERMBZ256rr + 0U, // VPERMBZ256rrk + 0U, // VPERMBZ256rrkz + 0U, // VPERMBZrm + 0U, // VPERMBZrmk + 0U, // VPERMBZrmkz + 0U, // VPERMBZrr + 0U, // VPERMBZrrk + 0U, // VPERMBZrrkz + 0U, // VPERMDYrm + 0U, // VPERMDYrr + 0U, // VPERMDZ256rm + 0U, // VPERMDZ256rmb + 0U, // VPERMDZ256rmbk + 0U, // VPERMDZ256rmbkz + 0U, // VPERMDZ256rmk + 0U, // VPERMDZ256rmkz + 0U, // VPERMDZ256rr + 0U, // VPERMDZ256rrk + 0U, // VPERMDZ256rrkz + 0U, // VPERMDZrm + 0U, // VPERMDZrmb + 0U, // VPERMDZrmbk + 0U, // VPERMDZrmbkz + 0U, // VPERMDZrmk + 0U, // VPERMDZrmkz + 0U, // VPERMDZrr + 0U, // VPERMDZrrk + 0U, // VPERMDZrrkz + 0U, // VPERMI2B128rm + 0U, // VPERMI2B128rmk + 0U, // VPERMI2B128rmkz + 0U, // VPERMI2B128rr + 0U, // VPERMI2B128rrk + 0U, // VPERMI2B128rrkz + 0U, // VPERMI2B256rm + 0U, // VPERMI2B256rmk + 0U, // VPERMI2B256rmkz + 0U, // VPERMI2B256rr + 0U, // VPERMI2B256rrk + 0U, // VPERMI2B256rrkz + 0U, // VPERMI2Brm + 0U, // VPERMI2Brmk + 0U, // VPERMI2Brmkz + 0U, // VPERMI2Brr + 0U, // VPERMI2Brrk + 0U, // VPERMI2Brrkz + 0U, // VPERMI2D128rm + 0U, // VPERMI2D128rmb + 0U, // VPERMI2D128rmbk + 0U, // VPERMI2D128rmbkz + 0U, // VPERMI2D128rmk + 0U, // VPERMI2D128rmkz + 0U, // VPERMI2D128rr + 0U, // VPERMI2D128rrk + 0U, // VPERMI2D128rrkz + 0U, // VPERMI2D256rm + 0U, // VPERMI2D256rmb + 0U, // VPERMI2D256rmbk + 0U, // VPERMI2D256rmbkz + 0U, // VPERMI2D256rmk + 0U, // VPERMI2D256rmkz + 0U, // VPERMI2D256rr + 0U, // VPERMI2D256rrk + 0U, // VPERMI2D256rrkz + 0U, // VPERMI2Drm + 0U, // VPERMI2Drmb + 0U, // VPERMI2Drmbk + 0U, // VPERMI2Drmbkz + 0U, // VPERMI2Drmk + 0U, // VPERMI2Drmkz + 0U, // VPERMI2Drr + 0U, // VPERMI2Drrk + 0U, // VPERMI2Drrkz + 0U, // VPERMI2PD128rm + 0U, // VPERMI2PD128rmb + 0U, // VPERMI2PD128rmbk + 0U, // VPERMI2PD128rmbkz + 0U, // VPERMI2PD128rmk + 0U, // VPERMI2PD128rmkz + 0U, // VPERMI2PD128rr + 0U, // VPERMI2PD128rrk + 0U, // VPERMI2PD128rrkz + 0U, // VPERMI2PD256rm + 0U, // VPERMI2PD256rmb + 0U, // VPERMI2PD256rmbk + 0U, // VPERMI2PD256rmbkz + 0U, // VPERMI2PD256rmk + 0U, // VPERMI2PD256rmkz + 0U, // VPERMI2PD256rr + 0U, // VPERMI2PD256rrk + 0U, // VPERMI2PD256rrkz + 0U, // VPERMI2PDrm + 0U, // VPERMI2PDrmb + 0U, // VPERMI2PDrmbk + 0U, // VPERMI2PDrmbkz + 0U, // VPERMI2PDrmk + 0U, // VPERMI2PDrmkz + 0U, // VPERMI2PDrr + 0U, // VPERMI2PDrrk + 0U, // VPERMI2PDrrkz + 0U, // VPERMI2PS128rm + 0U, // VPERMI2PS128rmb + 0U, // VPERMI2PS128rmbk + 0U, // VPERMI2PS128rmbkz + 0U, // VPERMI2PS128rmk + 0U, // VPERMI2PS128rmkz + 0U, // VPERMI2PS128rr + 0U, // VPERMI2PS128rrk + 0U, // VPERMI2PS128rrkz + 0U, // VPERMI2PS256rm + 0U, // VPERMI2PS256rmb + 0U, // VPERMI2PS256rmbk + 0U, // VPERMI2PS256rmbkz + 0U, // VPERMI2PS256rmk + 0U, // VPERMI2PS256rmkz + 0U, // VPERMI2PS256rr + 0U, // VPERMI2PS256rrk + 0U, // VPERMI2PS256rrkz + 0U, // VPERMI2PSrm + 0U, // VPERMI2PSrmb + 0U, // VPERMI2PSrmbk + 0U, // VPERMI2PSrmbkz + 0U, // VPERMI2PSrmk + 0U, // VPERMI2PSrmkz + 0U, // VPERMI2PSrr + 0U, // VPERMI2PSrrk + 0U, // VPERMI2PSrrkz + 0U, // VPERMI2Q128rm + 0U, // VPERMI2Q128rmb + 0U, // VPERMI2Q128rmbk + 0U, // VPERMI2Q128rmbkz + 0U, // VPERMI2Q128rmk + 0U, // VPERMI2Q128rmkz + 0U, // VPERMI2Q128rr + 0U, // VPERMI2Q128rrk + 0U, // VPERMI2Q128rrkz + 0U, // VPERMI2Q256rm + 0U, // VPERMI2Q256rmb + 0U, // VPERMI2Q256rmbk + 0U, // VPERMI2Q256rmbkz + 0U, // VPERMI2Q256rmk + 0U, // VPERMI2Q256rmkz + 0U, // VPERMI2Q256rr + 0U, // VPERMI2Q256rrk + 0U, // VPERMI2Q256rrkz + 0U, // VPERMI2Qrm + 0U, // VPERMI2Qrmb + 0U, // VPERMI2Qrmbk + 0U, // VPERMI2Qrmbkz + 0U, // VPERMI2Qrmk + 0U, // VPERMI2Qrmkz + 0U, // VPERMI2Qrr + 0U, // VPERMI2Qrrk + 0U, // VPERMI2Qrrkz + 0U, // VPERMI2W128rm + 0U, // VPERMI2W128rmk + 0U, // VPERMI2W128rmkz + 0U, // VPERMI2W128rr + 0U, // VPERMI2W128rrk + 0U, // VPERMI2W128rrkz + 0U, // VPERMI2W256rm + 0U, // VPERMI2W256rmk + 0U, // VPERMI2W256rmkz + 0U, // VPERMI2W256rr + 0U, // VPERMI2W256rrk + 0U, // VPERMI2W256rrkz + 0U, // VPERMI2Wrm + 0U, // VPERMI2Wrmk + 0U, // VPERMI2Wrmkz + 0U, // VPERMI2Wrr + 0U, // VPERMI2Wrrk + 0U, // VPERMI2Wrrkz + 0U, // VPERMIL2PDYmr + 0U, // VPERMIL2PDYrm + 0U, // VPERMIL2PDYrr + 0U, // VPERMIL2PDYrr_REV + 0U, // VPERMIL2PDmr + 0U, // VPERMIL2PDrm + 0U, // VPERMIL2PDrr + 0U, // VPERMIL2PDrr_REV + 0U, // VPERMIL2PSYmr + 0U, // VPERMIL2PSYrm + 0U, // VPERMIL2PSYrr + 0U, // VPERMIL2PSYrr_REV + 0U, // VPERMIL2PSmr + 0U, // VPERMIL2PSrm + 0U, // VPERMIL2PSrr + 0U, // VPERMIL2PSrr_REV + 0U, // VPERMILPDYmi + 0U, // VPERMILPDYri + 0U, // VPERMILPDYrm + 0U, // VPERMILPDYrr + 0U, // VPERMILPDZ128mbi + 0U, // VPERMILPDZ128mbik + 0U, // VPERMILPDZ128mbikz + 0U, // VPERMILPDZ128mi + 0U, // VPERMILPDZ128mik + 0U, // VPERMILPDZ128mikz + 0U, // VPERMILPDZ128ri + 0U, // VPERMILPDZ128rik + 0U, // VPERMILPDZ128rikz + 0U, // VPERMILPDZ128rm + 0U, // VPERMILPDZ128rmb + 0U, // VPERMILPDZ128rmbk + 0U, // VPERMILPDZ128rmbkz + 0U, // VPERMILPDZ128rmk + 0U, // VPERMILPDZ128rmkz + 0U, // VPERMILPDZ128rr + 0U, // VPERMILPDZ128rrk + 0U, // VPERMILPDZ128rrkz + 0U, // VPERMILPDZ256mbi + 0U, // VPERMILPDZ256mbik + 0U, // VPERMILPDZ256mbikz + 0U, // VPERMILPDZ256mi + 0U, // VPERMILPDZ256mik + 0U, // VPERMILPDZ256mikz + 0U, // VPERMILPDZ256ri + 0U, // VPERMILPDZ256rik + 0U, // VPERMILPDZ256rikz + 0U, // VPERMILPDZ256rm + 0U, // VPERMILPDZ256rmb + 0U, // VPERMILPDZ256rmbk + 0U, // VPERMILPDZ256rmbkz + 0U, // VPERMILPDZ256rmk + 0U, // VPERMILPDZ256rmkz + 0U, // VPERMILPDZ256rr + 0U, // VPERMILPDZ256rrk + 0U, // VPERMILPDZ256rrkz + 0U, // VPERMILPDZmbi + 0U, // VPERMILPDZmbik + 0U, // VPERMILPDZmbikz + 0U, // VPERMILPDZmi + 0U, // VPERMILPDZmik + 0U, // VPERMILPDZmikz + 0U, // VPERMILPDZri + 0U, // VPERMILPDZrik + 0U, // VPERMILPDZrikz + 0U, // VPERMILPDZrm + 0U, // VPERMILPDZrmb + 0U, // VPERMILPDZrmbk + 0U, // VPERMILPDZrmbkz + 0U, // VPERMILPDZrmk + 0U, // VPERMILPDZrmkz + 0U, // VPERMILPDZrr + 0U, // VPERMILPDZrrk + 0U, // VPERMILPDZrrkz + 0U, // VPERMILPDmi + 0U, // VPERMILPDri + 0U, // VPERMILPDrm + 0U, // VPERMILPDrr + 0U, // VPERMILPSYmi + 0U, // VPERMILPSYri + 0U, // VPERMILPSYrm + 0U, // VPERMILPSYrr + 0U, // VPERMILPSZ128mbi + 0U, // VPERMILPSZ128mbik + 0U, // VPERMILPSZ128mbikz + 0U, // VPERMILPSZ128mi + 0U, // VPERMILPSZ128mik + 0U, // VPERMILPSZ128mikz + 0U, // VPERMILPSZ128ri + 0U, // VPERMILPSZ128rik + 0U, // VPERMILPSZ128rikz + 0U, // VPERMILPSZ128rm + 0U, // VPERMILPSZ128rmb + 0U, // VPERMILPSZ128rmbk + 0U, // VPERMILPSZ128rmbkz + 0U, // VPERMILPSZ128rmk + 0U, // VPERMILPSZ128rmkz + 0U, // VPERMILPSZ128rr + 0U, // VPERMILPSZ128rrk + 0U, // VPERMILPSZ128rrkz + 0U, // VPERMILPSZ256mbi + 0U, // VPERMILPSZ256mbik + 0U, // VPERMILPSZ256mbikz + 0U, // VPERMILPSZ256mi + 0U, // VPERMILPSZ256mik + 0U, // VPERMILPSZ256mikz + 0U, // VPERMILPSZ256ri + 0U, // VPERMILPSZ256rik + 0U, // VPERMILPSZ256rikz + 0U, // VPERMILPSZ256rm + 0U, // VPERMILPSZ256rmb + 0U, // VPERMILPSZ256rmbk + 0U, // VPERMILPSZ256rmbkz + 0U, // VPERMILPSZ256rmk + 0U, // VPERMILPSZ256rmkz + 0U, // VPERMILPSZ256rr + 0U, // VPERMILPSZ256rrk + 0U, // VPERMILPSZ256rrkz + 0U, // VPERMILPSZmbi + 0U, // VPERMILPSZmbik + 0U, // VPERMILPSZmbikz + 0U, // VPERMILPSZmi + 0U, // VPERMILPSZmik + 0U, // VPERMILPSZmikz + 0U, // VPERMILPSZri + 0U, // VPERMILPSZrik + 0U, // VPERMILPSZrikz + 0U, // VPERMILPSZrm + 0U, // VPERMILPSZrmb + 0U, // VPERMILPSZrmbk + 0U, // VPERMILPSZrmbkz + 0U, // VPERMILPSZrmk + 0U, // VPERMILPSZrmkz + 0U, // VPERMILPSZrr + 0U, // VPERMILPSZrrk + 0U, // VPERMILPSZrrkz + 0U, // VPERMILPSmi + 0U, // VPERMILPSri + 0U, // VPERMILPSrm + 0U, // VPERMILPSrr + 0U, // VPERMPDYmi + 0U, // VPERMPDYri + 0U, // VPERMPDZ256mbi + 0U, // VPERMPDZ256mbik + 0U, // VPERMPDZ256mbikz + 0U, // VPERMPDZ256mi + 0U, // VPERMPDZ256mik + 0U, // VPERMPDZ256mikz + 0U, // VPERMPDZ256ri + 0U, // VPERMPDZ256rik + 0U, // VPERMPDZ256rikz + 0U, // VPERMPDZ256rm + 0U, // VPERMPDZ256rmb + 0U, // VPERMPDZ256rmbk + 0U, // VPERMPDZ256rmbkz + 0U, // VPERMPDZ256rmk + 0U, // VPERMPDZ256rmkz + 0U, // VPERMPDZ256rr + 0U, // VPERMPDZ256rrk + 0U, // VPERMPDZ256rrkz + 0U, // VPERMPDZmbi + 0U, // VPERMPDZmbik + 0U, // VPERMPDZmbikz + 0U, // VPERMPDZmi + 0U, // VPERMPDZmik + 0U, // VPERMPDZmikz + 0U, // VPERMPDZri + 0U, // VPERMPDZrik + 0U, // VPERMPDZrikz + 0U, // VPERMPDZrm + 0U, // VPERMPDZrmb + 0U, // VPERMPDZrmbk + 0U, // VPERMPDZrmbkz + 0U, // VPERMPDZrmk + 0U, // VPERMPDZrmkz + 0U, // VPERMPDZrr + 0U, // VPERMPDZrrk + 0U, // VPERMPDZrrkz + 0U, // VPERMPSYrm + 0U, // VPERMPSYrr + 0U, // VPERMPSZ256rm + 0U, // VPERMPSZ256rmb + 0U, // VPERMPSZ256rmbk + 0U, // VPERMPSZ256rmbkz + 0U, // VPERMPSZ256rmk + 0U, // VPERMPSZ256rmkz + 0U, // VPERMPSZ256rr + 0U, // VPERMPSZ256rrk + 0U, // VPERMPSZ256rrkz + 0U, // VPERMPSZrm + 0U, // VPERMPSZrmb + 0U, // VPERMPSZrmbk + 0U, // VPERMPSZrmbkz + 0U, // VPERMPSZrmk + 0U, // VPERMPSZrmkz + 0U, // VPERMPSZrr + 0U, // VPERMPSZrrk + 0U, // VPERMPSZrrkz + 0U, // VPERMQYmi + 0U, // VPERMQYri + 0U, // VPERMQZ256mbi + 0U, // VPERMQZ256mbik + 0U, // VPERMQZ256mbikz + 0U, // VPERMQZ256mi + 0U, // VPERMQZ256mik + 0U, // VPERMQZ256mikz + 0U, // VPERMQZ256ri + 0U, // VPERMQZ256rik + 0U, // VPERMQZ256rikz + 0U, // VPERMQZ256rm + 0U, // VPERMQZ256rmb + 0U, // VPERMQZ256rmbk + 0U, // VPERMQZ256rmbkz + 0U, // VPERMQZ256rmk + 0U, // VPERMQZ256rmkz + 0U, // VPERMQZ256rr + 0U, // VPERMQZ256rrk + 0U, // VPERMQZ256rrkz + 0U, // VPERMQZmbi + 0U, // VPERMQZmbik + 0U, // VPERMQZmbikz + 0U, // VPERMQZmi + 0U, // VPERMQZmik + 0U, // VPERMQZmikz + 0U, // VPERMQZri + 0U, // VPERMQZrik + 0U, // VPERMQZrikz + 0U, // VPERMQZrm + 0U, // VPERMQZrmb + 0U, // VPERMQZrmbk + 0U, // VPERMQZrmbkz + 0U, // VPERMQZrmk + 0U, // VPERMQZrmkz + 0U, // VPERMQZrr + 0U, // VPERMQZrrk + 0U, // VPERMQZrrkz + 0U, // VPERMT2B128rm + 0U, // VPERMT2B128rmk + 0U, // VPERMT2B128rmkz + 0U, // VPERMT2B128rr + 0U, // VPERMT2B128rrk + 0U, // VPERMT2B128rrkz + 0U, // VPERMT2B256rm + 0U, // VPERMT2B256rmk + 0U, // VPERMT2B256rmkz + 0U, // VPERMT2B256rr + 0U, // VPERMT2B256rrk + 0U, // VPERMT2B256rrkz + 0U, // VPERMT2Brm + 0U, // VPERMT2Brmk + 0U, // VPERMT2Brmkz + 0U, // VPERMT2Brr + 0U, // VPERMT2Brrk + 0U, // VPERMT2Brrkz + 0U, // VPERMT2D128rm + 0U, // VPERMT2D128rmb + 0U, // VPERMT2D128rmbk + 0U, // VPERMT2D128rmbkz + 0U, // VPERMT2D128rmk + 0U, // VPERMT2D128rmkz + 0U, // VPERMT2D128rr + 0U, // VPERMT2D128rrk + 0U, // VPERMT2D128rrkz + 0U, // VPERMT2D256rm + 0U, // VPERMT2D256rmb + 0U, // VPERMT2D256rmbk + 0U, // VPERMT2D256rmbkz + 0U, // VPERMT2D256rmk + 0U, // VPERMT2D256rmkz + 0U, // VPERMT2D256rr + 0U, // VPERMT2D256rrk + 0U, // VPERMT2D256rrkz + 0U, // VPERMT2Drm + 0U, // VPERMT2Drmb + 0U, // VPERMT2Drmbk + 0U, // VPERMT2Drmbkz + 0U, // VPERMT2Drmk + 0U, // VPERMT2Drmkz + 0U, // VPERMT2Drr + 0U, // VPERMT2Drrk + 0U, // VPERMT2Drrkz + 0U, // VPERMT2PD128rm + 0U, // VPERMT2PD128rmb + 0U, // VPERMT2PD128rmbk + 0U, // VPERMT2PD128rmbkz + 0U, // VPERMT2PD128rmk + 0U, // VPERMT2PD128rmkz + 0U, // VPERMT2PD128rr + 0U, // VPERMT2PD128rrk + 0U, // VPERMT2PD128rrkz + 0U, // VPERMT2PD256rm + 0U, // VPERMT2PD256rmb + 0U, // VPERMT2PD256rmbk + 0U, // VPERMT2PD256rmbkz + 0U, // VPERMT2PD256rmk + 0U, // VPERMT2PD256rmkz + 0U, // VPERMT2PD256rr + 0U, // VPERMT2PD256rrk + 0U, // VPERMT2PD256rrkz + 0U, // VPERMT2PDrm + 0U, // VPERMT2PDrmb + 0U, // VPERMT2PDrmbk + 0U, // VPERMT2PDrmbkz + 0U, // VPERMT2PDrmk + 0U, // VPERMT2PDrmkz + 0U, // VPERMT2PDrr + 0U, // VPERMT2PDrrk + 0U, // VPERMT2PDrrkz + 0U, // VPERMT2PS128rm + 0U, // VPERMT2PS128rmb + 0U, // VPERMT2PS128rmbk + 0U, // VPERMT2PS128rmbkz + 0U, // VPERMT2PS128rmk + 0U, // VPERMT2PS128rmkz + 0U, // VPERMT2PS128rr + 0U, // VPERMT2PS128rrk + 0U, // VPERMT2PS128rrkz + 0U, // VPERMT2PS256rm + 0U, // VPERMT2PS256rmb + 0U, // VPERMT2PS256rmbk + 0U, // VPERMT2PS256rmbkz + 0U, // VPERMT2PS256rmk + 0U, // VPERMT2PS256rmkz + 0U, // VPERMT2PS256rr + 0U, // VPERMT2PS256rrk + 0U, // VPERMT2PS256rrkz + 0U, // VPERMT2PSrm + 0U, // VPERMT2PSrmb + 0U, // VPERMT2PSrmbk + 0U, // VPERMT2PSrmbkz + 0U, // VPERMT2PSrmk + 0U, // VPERMT2PSrmkz + 0U, // VPERMT2PSrr + 0U, // VPERMT2PSrrk + 0U, // VPERMT2PSrrkz + 0U, // VPERMT2Q128rm + 0U, // VPERMT2Q128rmb + 0U, // VPERMT2Q128rmbk + 0U, // VPERMT2Q128rmbkz + 0U, // VPERMT2Q128rmk + 0U, // VPERMT2Q128rmkz + 0U, // VPERMT2Q128rr + 0U, // VPERMT2Q128rrk + 0U, // VPERMT2Q128rrkz + 0U, // VPERMT2Q256rm + 0U, // VPERMT2Q256rmb + 0U, // VPERMT2Q256rmbk + 0U, // VPERMT2Q256rmbkz + 0U, // VPERMT2Q256rmk + 0U, // VPERMT2Q256rmkz + 0U, // VPERMT2Q256rr + 0U, // VPERMT2Q256rrk + 0U, // VPERMT2Q256rrkz + 0U, // VPERMT2Qrm + 0U, // VPERMT2Qrmb + 0U, // VPERMT2Qrmbk + 0U, // VPERMT2Qrmbkz + 0U, // VPERMT2Qrmk + 0U, // VPERMT2Qrmkz + 0U, // VPERMT2Qrr + 0U, // VPERMT2Qrrk + 0U, // VPERMT2Qrrkz + 0U, // VPERMT2W128rm + 0U, // VPERMT2W128rmk + 0U, // VPERMT2W128rmkz + 0U, // VPERMT2W128rr + 0U, // VPERMT2W128rrk + 0U, // VPERMT2W128rrkz + 0U, // VPERMT2W256rm + 0U, // VPERMT2W256rmk + 0U, // VPERMT2W256rmkz + 0U, // VPERMT2W256rr + 0U, // VPERMT2W256rrk + 0U, // VPERMT2W256rrkz + 0U, // VPERMT2Wrm + 0U, // VPERMT2Wrmk + 0U, // VPERMT2Wrmkz + 0U, // VPERMT2Wrr + 0U, // VPERMT2Wrrk + 0U, // VPERMT2Wrrkz + 0U, // VPERMWZ128rm + 0U, // VPERMWZ128rmk + 0U, // VPERMWZ128rmkz + 0U, // VPERMWZ128rr + 0U, // VPERMWZ128rrk + 0U, // VPERMWZ128rrkz + 0U, // VPERMWZ256rm + 0U, // VPERMWZ256rmk + 0U, // VPERMWZ256rmkz + 0U, // VPERMWZ256rr + 0U, // VPERMWZ256rrk + 0U, // VPERMWZ256rrkz + 0U, // VPERMWZrm + 0U, // VPERMWZrmk + 0U, // VPERMWZrmkz + 0U, // VPERMWZrr + 0U, // VPERMWZrrk + 0U, // VPERMWZrrkz + 0U, // VPEXPANDBZ128rm + 0U, // VPEXPANDBZ128rmk + 0U, // VPEXPANDBZ128rmkz + 0U, // VPEXPANDBZ128rr + 0U, // VPEXPANDBZ128rrk + 0U, // VPEXPANDBZ128rrkz + 0U, // VPEXPANDBZ256rm + 0U, // VPEXPANDBZ256rmk + 0U, // VPEXPANDBZ256rmkz + 0U, // VPEXPANDBZ256rr + 0U, // VPEXPANDBZ256rrk + 0U, // VPEXPANDBZ256rrkz + 0U, // VPEXPANDBZrm + 0U, // VPEXPANDBZrmk + 0U, // VPEXPANDBZrmkz + 0U, // VPEXPANDBZrr + 0U, // VPEXPANDBZrrk + 0U, // VPEXPANDBZrrkz + 0U, // VPEXPANDDZ128rm + 0U, // VPEXPANDDZ128rmk + 0U, // VPEXPANDDZ128rmkz + 0U, // VPEXPANDDZ128rr + 0U, // VPEXPANDDZ128rrk + 0U, // VPEXPANDDZ128rrkz + 0U, // VPEXPANDDZ256rm + 0U, // VPEXPANDDZ256rmk + 0U, // VPEXPANDDZ256rmkz + 0U, // VPEXPANDDZ256rr + 0U, // VPEXPANDDZ256rrk + 0U, // VPEXPANDDZ256rrkz + 0U, // VPEXPANDDZrm + 0U, // VPEXPANDDZrmk + 0U, // VPEXPANDDZrmkz + 0U, // VPEXPANDDZrr + 0U, // VPEXPANDDZrrk + 0U, // VPEXPANDDZrrkz + 0U, // VPEXPANDQZ128rm + 0U, // VPEXPANDQZ128rmk + 0U, // VPEXPANDQZ128rmkz + 0U, // VPEXPANDQZ128rr + 0U, // VPEXPANDQZ128rrk + 0U, // VPEXPANDQZ128rrkz + 0U, // VPEXPANDQZ256rm + 0U, // VPEXPANDQZ256rmk + 0U, // VPEXPANDQZ256rmkz + 0U, // VPEXPANDQZ256rr + 0U, // VPEXPANDQZ256rrk + 0U, // VPEXPANDQZ256rrkz + 0U, // VPEXPANDQZrm + 0U, // VPEXPANDQZrmk + 0U, // VPEXPANDQZrmkz + 0U, // VPEXPANDQZrr + 0U, // VPEXPANDQZrrk + 0U, // VPEXPANDQZrrkz + 0U, // VPEXPANDWZ128rm + 0U, // VPEXPANDWZ128rmk + 0U, // VPEXPANDWZ128rmkz + 0U, // VPEXPANDWZ128rr + 0U, // VPEXPANDWZ128rrk + 0U, // VPEXPANDWZ128rrkz + 0U, // VPEXPANDWZ256rm + 0U, // VPEXPANDWZ256rmk + 0U, // VPEXPANDWZ256rmkz + 0U, // VPEXPANDWZ256rr + 0U, // VPEXPANDWZ256rrk + 0U, // VPEXPANDWZ256rrkz + 0U, // VPEXPANDWZrm + 0U, // VPEXPANDWZrmk + 0U, // VPEXPANDWZrmkz + 0U, // VPEXPANDWZrr + 0U, // VPEXPANDWZrrk + 0U, // VPEXPANDWZrrkz + 0U, // VPEXTRBZmr + 0U, // VPEXTRBZrr + 0U, // VPEXTRBmr + 0U, // VPEXTRBrr + 0U, // VPEXTRDZmr + 0U, // VPEXTRDZrr + 0U, // VPEXTRDmr + 0U, // VPEXTRDrr + 0U, // VPEXTRQZmr + 0U, // VPEXTRQZrr + 0U, // VPEXTRQmr + 0U, // VPEXTRQrr + 0U, // VPEXTRWZmr + 0U, // VPEXTRWZrr + 0U, // VPEXTRWZrr_REV + 0U, // VPEXTRWmr + 0U, // VPEXTRWrr + 0U, // VPEXTRWrr_REV + 0U, // VPGATHERDDYrm + 0U, // VPGATHERDDZ128rm + 0U, // VPGATHERDDZ256rm + 0U, // VPGATHERDDZrm + 0U, // VPGATHERDDrm + 0U, // VPGATHERDQYrm + 0U, // VPGATHERDQZ128rm + 0U, // VPGATHERDQZ256rm + 0U, // VPGATHERDQZrm + 0U, // VPGATHERDQrm + 0U, // VPGATHERQDYrm + 0U, // VPGATHERQDZ128rm + 0U, // VPGATHERQDZ256rm + 0U, // VPGATHERQDZrm + 0U, // VPGATHERQDrm + 0U, // VPGATHERQQYrm + 0U, // VPGATHERQQZ128rm + 0U, // VPGATHERQQZ256rm + 0U, // VPGATHERQQZrm + 0U, // VPGATHERQQrm + 0U, // VPHADDBDrm + 0U, // VPHADDBDrr + 0U, // VPHADDBQrm + 0U, // VPHADDBQrr + 0U, // VPHADDBWrm + 0U, // VPHADDBWrr + 0U, // VPHADDDQrm + 0U, // VPHADDDQrr + 0U, // VPHADDDYrm + 0U, // VPHADDDYrr + 0U, // VPHADDDrm + 0U, // VPHADDDrr + 0U, // VPHADDSWYrm + 0U, // VPHADDSWYrr + 0U, // VPHADDSWrm + 0U, // VPHADDSWrr + 0U, // VPHADDUBDrm + 0U, // VPHADDUBDrr + 0U, // VPHADDUBQrm + 0U, // VPHADDUBQrr + 0U, // VPHADDUBWrm + 0U, // VPHADDUBWrr + 0U, // VPHADDUDQrm + 0U, // VPHADDUDQrr + 0U, // VPHADDUWDrm + 0U, // VPHADDUWDrr + 0U, // VPHADDUWQrm + 0U, // VPHADDUWQrr + 0U, // VPHADDWDrm + 0U, // VPHADDWDrr + 0U, // VPHADDWQrm + 0U, // VPHADDWQrr + 0U, // VPHADDWYrm + 0U, // VPHADDWYrr + 0U, // VPHADDWrm + 0U, // VPHADDWrr + 0U, // VPHMINPOSUWrm + 0U, // VPHMINPOSUWrr + 0U, // VPHSUBBWrm + 0U, // VPHSUBBWrr + 0U, // VPHSUBDQrm + 0U, // VPHSUBDQrr + 0U, // VPHSUBDYrm + 0U, // VPHSUBDYrr + 0U, // VPHSUBDrm + 0U, // VPHSUBDrr + 0U, // VPHSUBSWYrm + 0U, // VPHSUBSWYrr + 0U, // VPHSUBSWrm + 0U, // VPHSUBSWrr + 0U, // VPHSUBWDrm + 0U, // VPHSUBWDrr + 0U, // VPHSUBWYrm + 0U, // VPHSUBWYrr + 0U, // VPHSUBWrm + 0U, // VPHSUBWrr + 0U, // VPINSRBZrm + 0U, // VPINSRBZrr + 0U, // VPINSRBrm + 0U, // VPINSRBrr + 0U, // VPINSRDZrm + 0U, // VPINSRDZrr + 0U, // VPINSRDrm + 0U, // VPINSRDrr + 0U, // VPINSRQZrm + 0U, // VPINSRQZrr + 0U, // VPINSRQrm + 0U, // VPINSRQrr + 0U, // VPINSRWZrm + 0U, // VPINSRWZrr + 0U, // VPINSRWrm + 0U, // VPINSRWrr + 0U, // VPLZCNTDZ128rm + 0U, // VPLZCNTDZ128rmb + 0U, // VPLZCNTDZ128rmbk + 0U, // VPLZCNTDZ128rmbkz + 0U, // VPLZCNTDZ128rmk + 0U, // VPLZCNTDZ128rmkz + 0U, // VPLZCNTDZ128rr + 0U, // VPLZCNTDZ128rrk + 0U, // VPLZCNTDZ128rrkz + 0U, // VPLZCNTDZ256rm + 0U, // VPLZCNTDZ256rmb + 0U, // VPLZCNTDZ256rmbk + 0U, // VPLZCNTDZ256rmbkz + 0U, // VPLZCNTDZ256rmk + 0U, // VPLZCNTDZ256rmkz + 0U, // VPLZCNTDZ256rr + 0U, // VPLZCNTDZ256rrk + 0U, // VPLZCNTDZ256rrkz + 0U, // VPLZCNTDZrm + 0U, // VPLZCNTDZrmb + 0U, // VPLZCNTDZrmbk + 0U, // VPLZCNTDZrmbkz + 0U, // VPLZCNTDZrmk + 0U, // VPLZCNTDZrmkz + 0U, // VPLZCNTDZrr + 0U, // VPLZCNTDZrrk + 0U, // VPLZCNTDZrrkz + 0U, // VPLZCNTQZ128rm + 0U, // VPLZCNTQZ128rmb + 0U, // VPLZCNTQZ128rmbk + 0U, // VPLZCNTQZ128rmbkz + 0U, // VPLZCNTQZ128rmk + 0U, // VPLZCNTQZ128rmkz + 0U, // VPLZCNTQZ128rr + 0U, // VPLZCNTQZ128rrk + 0U, // VPLZCNTQZ128rrkz + 0U, // VPLZCNTQZ256rm + 0U, // VPLZCNTQZ256rmb + 0U, // VPLZCNTQZ256rmbk + 0U, // VPLZCNTQZ256rmbkz + 0U, // VPLZCNTQZ256rmk + 0U, // VPLZCNTQZ256rmkz + 0U, // VPLZCNTQZ256rr + 0U, // VPLZCNTQZ256rrk + 0U, // VPLZCNTQZ256rrkz + 0U, // VPLZCNTQZrm + 0U, // VPLZCNTQZrmb + 0U, // VPLZCNTQZrmbk + 0U, // VPLZCNTQZrmbkz + 0U, // VPLZCNTQZrmk + 0U, // VPLZCNTQZrmkz + 0U, // VPLZCNTQZrr + 0U, // VPLZCNTQZrrk + 0U, // VPLZCNTQZrrkz + 0U, // VPMACSDDrm + 0U, // VPMACSDDrr + 0U, // VPMACSDQHrm + 0U, // VPMACSDQHrr + 0U, // VPMACSDQLrm + 0U, // VPMACSDQLrr + 0U, // VPMACSSDDrm + 0U, // VPMACSSDDrr + 0U, // VPMACSSDQHrm + 0U, // VPMACSSDQHrr + 0U, // VPMACSSDQLrm + 0U, // VPMACSSDQLrr + 0U, // VPMACSSWDrm + 0U, // VPMACSSWDrr + 0U, // VPMACSSWWrm + 0U, // VPMACSSWWrr + 0U, // VPMACSWDrm + 0U, // VPMACSWDrr + 0U, // VPMACSWWrm + 0U, // VPMACSWWrr + 0U, // VPMADCSSWDrm + 0U, // VPMADCSSWDrr + 0U, // VPMADCSWDrm + 0U, // VPMADCSWDrr + 0U, // VPMADD52HUQZ128m + 0U, // VPMADD52HUQZ128mb + 0U, // VPMADD52HUQZ128mbk + 0U, // VPMADD52HUQZ128mbkz + 0U, // VPMADD52HUQZ128mk + 0U, // VPMADD52HUQZ128mkz + 0U, // VPMADD52HUQZ128r + 0U, // VPMADD52HUQZ128rk + 0U, // VPMADD52HUQZ128rkz + 0U, // VPMADD52HUQZ256m + 0U, // VPMADD52HUQZ256mb + 0U, // VPMADD52HUQZ256mbk + 0U, // VPMADD52HUQZ256mbkz + 0U, // VPMADD52HUQZ256mk + 0U, // VPMADD52HUQZ256mkz + 0U, // VPMADD52HUQZ256r + 0U, // VPMADD52HUQZ256rk + 0U, // VPMADD52HUQZ256rkz + 0U, // VPMADD52HUQZm + 0U, // VPMADD52HUQZmb + 0U, // VPMADD52HUQZmbk + 0U, // VPMADD52HUQZmbkz + 0U, // VPMADD52HUQZmk + 0U, // VPMADD52HUQZmkz + 0U, // VPMADD52HUQZr + 0U, // VPMADD52HUQZrk + 0U, // VPMADD52HUQZrkz + 0U, // VPMADD52LUQZ128m + 0U, // VPMADD52LUQZ128mb + 0U, // VPMADD52LUQZ128mbk + 0U, // VPMADD52LUQZ128mbkz + 0U, // VPMADD52LUQZ128mk + 0U, // VPMADD52LUQZ128mkz + 0U, // VPMADD52LUQZ128r + 0U, // VPMADD52LUQZ128rk + 0U, // VPMADD52LUQZ128rkz + 0U, // VPMADD52LUQZ256m + 0U, // VPMADD52LUQZ256mb + 0U, // VPMADD52LUQZ256mbk + 0U, // VPMADD52LUQZ256mbkz + 0U, // VPMADD52LUQZ256mk + 0U, // VPMADD52LUQZ256mkz + 0U, // VPMADD52LUQZ256r + 0U, // VPMADD52LUQZ256rk + 0U, // VPMADD52LUQZ256rkz + 0U, // VPMADD52LUQZm + 0U, // VPMADD52LUQZmb + 0U, // VPMADD52LUQZmbk + 0U, // VPMADD52LUQZmbkz + 0U, // VPMADD52LUQZmk + 0U, // VPMADD52LUQZmkz + 0U, // VPMADD52LUQZr + 0U, // VPMADD52LUQZrk + 0U, // VPMADD52LUQZrkz + 0U, // VPMADDUBSWYrm + 0U, // VPMADDUBSWYrr + 0U, // VPMADDUBSWZ128rm + 0U, // VPMADDUBSWZ128rmk + 0U, // VPMADDUBSWZ128rmkz + 0U, // VPMADDUBSWZ128rr + 0U, // VPMADDUBSWZ128rrk + 0U, // VPMADDUBSWZ128rrkz + 0U, // VPMADDUBSWZ256rm + 0U, // VPMADDUBSWZ256rmk + 0U, // VPMADDUBSWZ256rmkz + 0U, // VPMADDUBSWZ256rr + 0U, // VPMADDUBSWZ256rrk + 0U, // VPMADDUBSWZ256rrkz + 0U, // VPMADDUBSWZrm + 0U, // VPMADDUBSWZrmk + 0U, // VPMADDUBSWZrmkz + 0U, // VPMADDUBSWZrr + 0U, // VPMADDUBSWZrrk + 0U, // VPMADDUBSWZrrkz + 0U, // VPMADDUBSWrm + 0U, // VPMADDUBSWrr + 0U, // VPMADDWDYrm + 0U, // VPMADDWDYrr + 0U, // VPMADDWDZ128rm + 0U, // VPMADDWDZ128rmk + 0U, // VPMADDWDZ128rmkz + 0U, // VPMADDWDZ128rr + 0U, // VPMADDWDZ128rrk + 0U, // VPMADDWDZ128rrkz + 0U, // VPMADDWDZ256rm + 0U, // VPMADDWDZ256rmk + 0U, // VPMADDWDZ256rmkz + 0U, // VPMADDWDZ256rr + 0U, // VPMADDWDZ256rrk + 0U, // VPMADDWDZ256rrkz + 0U, // VPMADDWDZrm + 0U, // VPMADDWDZrmk + 0U, // VPMADDWDZrmkz + 0U, // VPMADDWDZrr + 0U, // VPMADDWDZrrk + 0U, // VPMADDWDZrrkz + 0U, // VPMADDWDrm + 0U, // VPMADDWDrr + 0U, // VPMASKMOVDYmr + 0U, // VPMASKMOVDYrm + 0U, // VPMASKMOVDmr + 0U, // VPMASKMOVDrm + 0U, // VPMASKMOVQYmr + 0U, // VPMASKMOVQYrm + 0U, // VPMASKMOVQmr + 0U, // VPMASKMOVQrm + 0U, // VPMAXSBYrm + 0U, // VPMAXSBYrr + 0U, // VPMAXSBZ128rm + 0U, // VPMAXSBZ128rmk + 0U, // VPMAXSBZ128rmkz + 0U, // VPMAXSBZ128rr + 0U, // VPMAXSBZ128rrk + 0U, // VPMAXSBZ128rrkz + 0U, // VPMAXSBZ256rm + 0U, // VPMAXSBZ256rmk + 0U, // VPMAXSBZ256rmkz + 0U, // VPMAXSBZ256rr + 0U, // VPMAXSBZ256rrk + 0U, // VPMAXSBZ256rrkz + 0U, // VPMAXSBZrm + 0U, // VPMAXSBZrmk + 0U, // VPMAXSBZrmkz + 0U, // VPMAXSBZrr + 0U, // VPMAXSBZrrk + 0U, // VPMAXSBZrrkz + 0U, // VPMAXSBrm + 0U, // VPMAXSBrr + 0U, // VPMAXSDYrm + 0U, // VPMAXSDYrr + 0U, // VPMAXSDZ128rm + 0U, // VPMAXSDZ128rmb + 0U, // VPMAXSDZ128rmbk + 0U, // VPMAXSDZ128rmbkz + 0U, // VPMAXSDZ128rmk + 0U, // VPMAXSDZ128rmkz + 0U, // VPMAXSDZ128rr + 0U, // VPMAXSDZ128rrk + 0U, // VPMAXSDZ128rrkz + 0U, // VPMAXSDZ256rm + 0U, // VPMAXSDZ256rmb + 0U, // VPMAXSDZ256rmbk + 0U, // VPMAXSDZ256rmbkz + 0U, // VPMAXSDZ256rmk + 0U, // VPMAXSDZ256rmkz + 0U, // VPMAXSDZ256rr + 0U, // VPMAXSDZ256rrk + 0U, // VPMAXSDZ256rrkz + 0U, // VPMAXSDZrm + 0U, // VPMAXSDZrmb + 0U, // VPMAXSDZrmbk + 0U, // VPMAXSDZrmbkz + 0U, // VPMAXSDZrmk + 0U, // VPMAXSDZrmkz + 0U, // VPMAXSDZrr + 0U, // VPMAXSDZrrk + 0U, // VPMAXSDZrrkz + 0U, // VPMAXSDrm + 0U, // VPMAXSDrr + 0U, // VPMAXSQZ128rm + 0U, // VPMAXSQZ128rmb + 0U, // VPMAXSQZ128rmbk + 0U, // VPMAXSQZ128rmbkz + 0U, // VPMAXSQZ128rmk + 0U, // VPMAXSQZ128rmkz + 0U, // VPMAXSQZ128rr + 0U, // VPMAXSQZ128rrk + 0U, // VPMAXSQZ128rrkz + 0U, // VPMAXSQZ256rm + 0U, // VPMAXSQZ256rmb + 0U, // VPMAXSQZ256rmbk + 0U, // VPMAXSQZ256rmbkz + 0U, // VPMAXSQZ256rmk + 0U, // VPMAXSQZ256rmkz + 0U, // VPMAXSQZ256rr + 0U, // VPMAXSQZ256rrk + 0U, // VPMAXSQZ256rrkz + 0U, // VPMAXSQZrm + 0U, // VPMAXSQZrmb + 0U, // VPMAXSQZrmbk + 0U, // VPMAXSQZrmbkz + 0U, // VPMAXSQZrmk + 0U, // VPMAXSQZrmkz + 0U, // VPMAXSQZrr + 0U, // VPMAXSQZrrk + 0U, // VPMAXSQZrrkz + 0U, // VPMAXSWYrm + 0U, // VPMAXSWYrr + 0U, // VPMAXSWZ128rm + 0U, // VPMAXSWZ128rmk + 0U, // VPMAXSWZ128rmkz + 0U, // VPMAXSWZ128rr + 0U, // VPMAXSWZ128rrk + 0U, // VPMAXSWZ128rrkz + 0U, // VPMAXSWZ256rm + 0U, // VPMAXSWZ256rmk + 0U, // VPMAXSWZ256rmkz + 0U, // VPMAXSWZ256rr + 0U, // VPMAXSWZ256rrk + 0U, // VPMAXSWZ256rrkz + 0U, // VPMAXSWZrm + 0U, // VPMAXSWZrmk + 0U, // VPMAXSWZrmkz + 0U, // VPMAXSWZrr + 0U, // VPMAXSWZrrk + 0U, // VPMAXSWZrrkz + 0U, // VPMAXSWrm + 0U, // VPMAXSWrr + 0U, // VPMAXUBYrm + 0U, // VPMAXUBYrr + 0U, // VPMAXUBZ128rm + 0U, // VPMAXUBZ128rmk + 0U, // VPMAXUBZ128rmkz + 0U, // VPMAXUBZ128rr + 0U, // VPMAXUBZ128rrk + 0U, // VPMAXUBZ128rrkz + 0U, // VPMAXUBZ256rm + 0U, // VPMAXUBZ256rmk + 0U, // VPMAXUBZ256rmkz + 0U, // VPMAXUBZ256rr + 0U, // VPMAXUBZ256rrk + 0U, // VPMAXUBZ256rrkz + 0U, // VPMAXUBZrm + 0U, // VPMAXUBZrmk + 0U, // VPMAXUBZrmkz + 0U, // VPMAXUBZrr + 0U, // VPMAXUBZrrk + 0U, // VPMAXUBZrrkz + 0U, // VPMAXUBrm + 0U, // VPMAXUBrr + 0U, // VPMAXUDYrm + 0U, // VPMAXUDYrr + 0U, // VPMAXUDZ128rm + 0U, // VPMAXUDZ128rmb + 0U, // VPMAXUDZ128rmbk + 0U, // VPMAXUDZ128rmbkz + 0U, // VPMAXUDZ128rmk + 0U, // VPMAXUDZ128rmkz + 0U, // VPMAXUDZ128rr + 0U, // VPMAXUDZ128rrk + 0U, // VPMAXUDZ128rrkz + 0U, // VPMAXUDZ256rm + 0U, // VPMAXUDZ256rmb + 0U, // VPMAXUDZ256rmbk + 0U, // VPMAXUDZ256rmbkz + 0U, // VPMAXUDZ256rmk + 0U, // VPMAXUDZ256rmkz + 0U, // VPMAXUDZ256rr + 0U, // VPMAXUDZ256rrk + 0U, // VPMAXUDZ256rrkz + 0U, // VPMAXUDZrm + 0U, // VPMAXUDZrmb + 0U, // VPMAXUDZrmbk + 0U, // VPMAXUDZrmbkz + 0U, // VPMAXUDZrmk + 0U, // VPMAXUDZrmkz + 0U, // VPMAXUDZrr + 0U, // VPMAXUDZrrk + 0U, // VPMAXUDZrrkz + 0U, // VPMAXUDrm + 0U, // VPMAXUDrr + 0U, // VPMAXUQZ128rm + 0U, // VPMAXUQZ128rmb + 0U, // VPMAXUQZ128rmbk + 0U, // VPMAXUQZ128rmbkz + 0U, // VPMAXUQZ128rmk + 0U, // VPMAXUQZ128rmkz + 0U, // VPMAXUQZ128rr + 0U, // VPMAXUQZ128rrk + 0U, // VPMAXUQZ128rrkz + 0U, // VPMAXUQZ256rm + 0U, // VPMAXUQZ256rmb + 0U, // VPMAXUQZ256rmbk + 0U, // VPMAXUQZ256rmbkz + 0U, // VPMAXUQZ256rmk + 0U, // VPMAXUQZ256rmkz + 0U, // VPMAXUQZ256rr + 0U, // VPMAXUQZ256rrk + 0U, // VPMAXUQZ256rrkz + 0U, // VPMAXUQZrm + 0U, // VPMAXUQZrmb + 0U, // VPMAXUQZrmbk + 0U, // VPMAXUQZrmbkz + 0U, // VPMAXUQZrmk + 0U, // VPMAXUQZrmkz + 0U, // VPMAXUQZrr + 0U, // VPMAXUQZrrk + 0U, // VPMAXUQZrrkz + 0U, // VPMAXUWYrm + 0U, // VPMAXUWYrr + 0U, // VPMAXUWZ128rm + 0U, // VPMAXUWZ128rmk + 0U, // VPMAXUWZ128rmkz + 0U, // VPMAXUWZ128rr + 0U, // VPMAXUWZ128rrk + 0U, // VPMAXUWZ128rrkz + 0U, // VPMAXUWZ256rm + 0U, // VPMAXUWZ256rmk + 0U, // VPMAXUWZ256rmkz + 0U, // VPMAXUWZ256rr + 0U, // VPMAXUWZ256rrk + 0U, // VPMAXUWZ256rrkz + 0U, // VPMAXUWZrm + 0U, // VPMAXUWZrmk + 0U, // VPMAXUWZrmkz + 0U, // VPMAXUWZrr + 0U, // VPMAXUWZrrk + 0U, // VPMAXUWZrrkz + 0U, // VPMAXUWrm + 0U, // VPMAXUWrr + 0U, // VPMINSBYrm + 0U, // VPMINSBYrr + 0U, // VPMINSBZ128rm + 0U, // VPMINSBZ128rmk + 0U, // VPMINSBZ128rmkz + 0U, // VPMINSBZ128rr + 0U, // VPMINSBZ128rrk + 0U, // VPMINSBZ128rrkz + 0U, // VPMINSBZ256rm + 0U, // VPMINSBZ256rmk + 0U, // VPMINSBZ256rmkz + 0U, // VPMINSBZ256rr + 0U, // VPMINSBZ256rrk + 0U, // VPMINSBZ256rrkz + 0U, // VPMINSBZrm + 0U, // VPMINSBZrmk + 0U, // VPMINSBZrmkz + 0U, // VPMINSBZrr + 0U, // VPMINSBZrrk + 0U, // VPMINSBZrrkz + 0U, // VPMINSBrm + 0U, // VPMINSBrr + 0U, // VPMINSDYrm + 0U, // VPMINSDYrr + 0U, // VPMINSDZ128rm + 0U, // VPMINSDZ128rmb + 0U, // VPMINSDZ128rmbk + 0U, // VPMINSDZ128rmbkz + 0U, // VPMINSDZ128rmk + 0U, // VPMINSDZ128rmkz + 0U, // VPMINSDZ128rr + 0U, // VPMINSDZ128rrk + 0U, // VPMINSDZ128rrkz + 0U, // VPMINSDZ256rm + 0U, // VPMINSDZ256rmb + 0U, // VPMINSDZ256rmbk + 0U, // VPMINSDZ256rmbkz + 0U, // VPMINSDZ256rmk + 0U, // VPMINSDZ256rmkz + 0U, // VPMINSDZ256rr + 0U, // VPMINSDZ256rrk + 0U, // VPMINSDZ256rrkz + 0U, // VPMINSDZrm + 0U, // VPMINSDZrmb + 0U, // VPMINSDZrmbk + 0U, // VPMINSDZrmbkz + 0U, // VPMINSDZrmk + 0U, // VPMINSDZrmkz + 0U, // VPMINSDZrr + 0U, // VPMINSDZrrk + 0U, // VPMINSDZrrkz + 0U, // VPMINSDrm + 0U, // VPMINSDrr + 0U, // VPMINSQZ128rm + 0U, // VPMINSQZ128rmb + 0U, // VPMINSQZ128rmbk + 0U, // VPMINSQZ128rmbkz + 0U, // VPMINSQZ128rmk + 0U, // VPMINSQZ128rmkz + 0U, // VPMINSQZ128rr + 0U, // VPMINSQZ128rrk + 0U, // VPMINSQZ128rrkz + 0U, // VPMINSQZ256rm + 0U, // VPMINSQZ256rmb + 0U, // VPMINSQZ256rmbk + 0U, // VPMINSQZ256rmbkz + 0U, // VPMINSQZ256rmk + 0U, // VPMINSQZ256rmkz + 0U, // VPMINSQZ256rr + 0U, // VPMINSQZ256rrk + 0U, // VPMINSQZ256rrkz + 0U, // VPMINSQZrm + 0U, // VPMINSQZrmb + 0U, // VPMINSQZrmbk + 0U, // VPMINSQZrmbkz + 0U, // VPMINSQZrmk + 0U, // VPMINSQZrmkz + 0U, // VPMINSQZrr + 0U, // VPMINSQZrrk + 0U, // VPMINSQZrrkz + 0U, // VPMINSWYrm + 0U, // VPMINSWYrr + 0U, // VPMINSWZ128rm + 0U, // VPMINSWZ128rmk + 0U, // VPMINSWZ128rmkz + 0U, // VPMINSWZ128rr + 0U, // VPMINSWZ128rrk + 0U, // VPMINSWZ128rrkz + 0U, // VPMINSWZ256rm + 0U, // VPMINSWZ256rmk + 0U, // VPMINSWZ256rmkz + 0U, // VPMINSWZ256rr + 0U, // VPMINSWZ256rrk + 0U, // VPMINSWZ256rrkz + 0U, // VPMINSWZrm + 0U, // VPMINSWZrmk + 0U, // VPMINSWZrmkz + 0U, // VPMINSWZrr + 0U, // VPMINSWZrrk + 0U, // VPMINSWZrrkz + 0U, // VPMINSWrm + 0U, // VPMINSWrr + 0U, // VPMINUBYrm + 0U, // VPMINUBYrr + 0U, // VPMINUBZ128rm + 0U, // VPMINUBZ128rmk + 0U, // VPMINUBZ128rmkz + 0U, // VPMINUBZ128rr + 0U, // VPMINUBZ128rrk + 0U, // VPMINUBZ128rrkz + 0U, // VPMINUBZ256rm + 0U, // VPMINUBZ256rmk + 0U, // VPMINUBZ256rmkz + 0U, // VPMINUBZ256rr + 0U, // VPMINUBZ256rrk + 0U, // VPMINUBZ256rrkz + 0U, // VPMINUBZrm + 0U, // VPMINUBZrmk + 0U, // VPMINUBZrmkz + 0U, // VPMINUBZrr + 0U, // VPMINUBZrrk + 0U, // VPMINUBZrrkz + 0U, // VPMINUBrm + 0U, // VPMINUBrr + 0U, // VPMINUDYrm + 0U, // VPMINUDYrr + 0U, // VPMINUDZ128rm + 0U, // VPMINUDZ128rmb + 0U, // VPMINUDZ128rmbk + 0U, // VPMINUDZ128rmbkz + 0U, // VPMINUDZ128rmk + 0U, // VPMINUDZ128rmkz + 0U, // VPMINUDZ128rr + 0U, // VPMINUDZ128rrk + 0U, // VPMINUDZ128rrkz + 0U, // VPMINUDZ256rm + 0U, // VPMINUDZ256rmb + 0U, // VPMINUDZ256rmbk + 0U, // VPMINUDZ256rmbkz + 0U, // VPMINUDZ256rmk + 0U, // VPMINUDZ256rmkz + 0U, // VPMINUDZ256rr + 0U, // VPMINUDZ256rrk + 0U, // VPMINUDZ256rrkz + 0U, // VPMINUDZrm + 0U, // VPMINUDZrmb + 0U, // VPMINUDZrmbk + 0U, // VPMINUDZrmbkz + 0U, // VPMINUDZrmk + 0U, // VPMINUDZrmkz + 0U, // VPMINUDZrr + 0U, // VPMINUDZrrk + 0U, // VPMINUDZrrkz + 0U, // VPMINUDrm + 0U, // VPMINUDrr + 0U, // VPMINUQZ128rm + 0U, // VPMINUQZ128rmb + 0U, // VPMINUQZ128rmbk + 0U, // VPMINUQZ128rmbkz + 0U, // VPMINUQZ128rmk + 0U, // VPMINUQZ128rmkz + 0U, // VPMINUQZ128rr + 0U, // VPMINUQZ128rrk + 0U, // VPMINUQZ128rrkz + 0U, // VPMINUQZ256rm + 0U, // VPMINUQZ256rmb + 0U, // VPMINUQZ256rmbk + 0U, // VPMINUQZ256rmbkz + 0U, // VPMINUQZ256rmk + 0U, // VPMINUQZ256rmkz + 0U, // VPMINUQZ256rr + 0U, // VPMINUQZ256rrk + 0U, // VPMINUQZ256rrkz + 0U, // VPMINUQZrm + 0U, // VPMINUQZrmb + 0U, // VPMINUQZrmbk + 0U, // VPMINUQZrmbkz + 0U, // VPMINUQZrmk + 0U, // VPMINUQZrmkz + 0U, // VPMINUQZrr + 0U, // VPMINUQZrrk + 0U, // VPMINUQZrrkz + 0U, // VPMINUWYrm + 0U, // VPMINUWYrr + 0U, // VPMINUWZ128rm + 0U, // VPMINUWZ128rmk + 0U, // VPMINUWZ128rmkz + 0U, // VPMINUWZ128rr + 0U, // VPMINUWZ128rrk + 0U, // VPMINUWZ128rrkz + 0U, // VPMINUWZ256rm + 0U, // VPMINUWZ256rmk + 0U, // VPMINUWZ256rmkz + 0U, // VPMINUWZ256rr + 0U, // VPMINUWZ256rrk + 0U, // VPMINUWZ256rrkz + 0U, // VPMINUWZrm + 0U, // VPMINUWZrmk + 0U, // VPMINUWZrmkz + 0U, // VPMINUWZrr + 0U, // VPMINUWZrrk + 0U, // VPMINUWZrrkz + 0U, // VPMINUWrm + 0U, // VPMINUWrr + 0U, // VPMOVB2MZ128rr + 0U, // VPMOVB2MZ256rr + 0U, // VPMOVB2MZrr + 0U, // VPMOVD2MZ128rr + 0U, // VPMOVD2MZ256rr + 0U, // VPMOVD2MZrr + 0U, // VPMOVDBZ128mr + 0U, // VPMOVDBZ128mrk + 0U, // VPMOVDBZ128rr + 0U, // VPMOVDBZ128rrk + 0U, // VPMOVDBZ128rrkz + 0U, // VPMOVDBZ256mr + 0U, // VPMOVDBZ256mrk + 0U, // VPMOVDBZ256rr + 0U, // VPMOVDBZ256rrk + 0U, // VPMOVDBZ256rrkz + 0U, // VPMOVDBZmr + 0U, // VPMOVDBZmrk + 0U, // VPMOVDBZrr + 0U, // VPMOVDBZrrk + 0U, // VPMOVDBZrrkz + 0U, // VPMOVDWZ128mr + 0U, // VPMOVDWZ128mrk + 0U, // VPMOVDWZ128rr + 0U, // VPMOVDWZ128rrk + 0U, // VPMOVDWZ128rrkz + 0U, // VPMOVDWZ256mr + 0U, // VPMOVDWZ256mrk + 0U, // VPMOVDWZ256rr + 0U, // VPMOVDWZ256rrk + 0U, // VPMOVDWZ256rrkz + 0U, // VPMOVDWZmr + 0U, // VPMOVDWZmrk + 0U, // VPMOVDWZrr + 0U, // VPMOVDWZrrk + 0U, // VPMOVDWZrrkz + 0U, // VPMOVM2BZ128rr + 0U, // VPMOVM2BZ256rr + 0U, // VPMOVM2BZrr + 0U, // VPMOVM2DZ128rr + 0U, // VPMOVM2DZ256rr + 0U, // VPMOVM2DZrr + 0U, // VPMOVM2QZ128rr + 0U, // VPMOVM2QZ256rr + 0U, // VPMOVM2QZrr + 0U, // VPMOVM2WZ128rr + 0U, // VPMOVM2WZ256rr + 0U, // VPMOVM2WZrr + 0U, // VPMOVMSKBYrr + 0U, // VPMOVMSKBrr + 0U, // VPMOVQ2MZ128rr + 0U, // VPMOVQ2MZ256rr + 0U, // VPMOVQ2MZrr + 0U, // VPMOVQBZ128mr + 0U, // VPMOVQBZ128mrk + 0U, // VPMOVQBZ128rr + 0U, // VPMOVQBZ128rrk + 0U, // VPMOVQBZ128rrkz + 0U, // VPMOVQBZ256mr + 0U, // VPMOVQBZ256mrk + 0U, // VPMOVQBZ256rr + 0U, // VPMOVQBZ256rrk + 0U, // VPMOVQBZ256rrkz + 0U, // VPMOVQBZmr + 0U, // VPMOVQBZmrk + 0U, // VPMOVQBZrr + 0U, // VPMOVQBZrrk + 0U, // VPMOVQBZrrkz + 0U, // VPMOVQDZ128mr + 0U, // VPMOVQDZ128mrk + 0U, // VPMOVQDZ128rr + 0U, // VPMOVQDZ128rrk + 0U, // VPMOVQDZ128rrkz + 0U, // VPMOVQDZ256mr + 0U, // VPMOVQDZ256mrk + 0U, // VPMOVQDZ256rr + 0U, // VPMOVQDZ256rrk + 0U, // VPMOVQDZ256rrkz + 0U, // VPMOVQDZmr + 0U, // VPMOVQDZmrk + 0U, // VPMOVQDZrr + 0U, // VPMOVQDZrrk + 0U, // VPMOVQDZrrkz + 0U, // VPMOVQWZ128mr + 0U, // VPMOVQWZ128mrk + 0U, // VPMOVQWZ128rr + 0U, // VPMOVQWZ128rrk + 0U, // VPMOVQWZ128rrkz + 0U, // VPMOVQWZ256mr + 0U, // VPMOVQWZ256mrk + 0U, // VPMOVQWZ256rr + 0U, // VPMOVQWZ256rrk + 0U, // VPMOVQWZ256rrkz + 0U, // VPMOVQWZmr + 0U, // VPMOVQWZmrk + 0U, // VPMOVQWZrr + 0U, // VPMOVQWZrrk + 0U, // VPMOVQWZrrkz + 0U, // VPMOVSDBZ128mr + 0U, // VPMOVSDBZ128mrk + 0U, // VPMOVSDBZ128rr + 0U, // VPMOVSDBZ128rrk + 0U, // VPMOVSDBZ128rrkz + 0U, // VPMOVSDBZ256mr + 0U, // VPMOVSDBZ256mrk + 0U, // VPMOVSDBZ256rr + 0U, // VPMOVSDBZ256rrk + 0U, // VPMOVSDBZ256rrkz + 0U, // VPMOVSDBZmr + 0U, // VPMOVSDBZmrk + 0U, // VPMOVSDBZrr + 0U, // VPMOVSDBZrrk + 0U, // VPMOVSDBZrrkz + 0U, // VPMOVSDWZ128mr + 0U, // VPMOVSDWZ128mrk + 0U, // VPMOVSDWZ128rr + 0U, // VPMOVSDWZ128rrk + 0U, // VPMOVSDWZ128rrkz + 0U, // VPMOVSDWZ256mr + 0U, // VPMOVSDWZ256mrk + 0U, // VPMOVSDWZ256rr + 0U, // VPMOVSDWZ256rrk + 0U, // VPMOVSDWZ256rrkz + 0U, // VPMOVSDWZmr + 0U, // VPMOVSDWZmrk + 0U, // VPMOVSDWZrr + 0U, // VPMOVSDWZrrk + 0U, // VPMOVSDWZrrkz + 0U, // VPMOVSQBZ128mr + 0U, // VPMOVSQBZ128mrk + 0U, // VPMOVSQBZ128rr + 0U, // VPMOVSQBZ128rrk + 0U, // VPMOVSQBZ128rrkz + 0U, // VPMOVSQBZ256mr + 0U, // VPMOVSQBZ256mrk + 0U, // VPMOVSQBZ256rr + 0U, // VPMOVSQBZ256rrk + 0U, // VPMOVSQBZ256rrkz + 0U, // VPMOVSQBZmr + 0U, // VPMOVSQBZmrk + 0U, // VPMOVSQBZrr + 0U, // VPMOVSQBZrrk + 0U, // VPMOVSQBZrrkz + 0U, // VPMOVSQDZ128mr + 0U, // VPMOVSQDZ128mrk + 0U, // VPMOVSQDZ128rr + 0U, // VPMOVSQDZ128rrk + 0U, // VPMOVSQDZ128rrkz + 0U, // VPMOVSQDZ256mr + 0U, // VPMOVSQDZ256mrk + 0U, // VPMOVSQDZ256rr + 0U, // VPMOVSQDZ256rrk + 0U, // VPMOVSQDZ256rrkz + 0U, // VPMOVSQDZmr + 0U, // VPMOVSQDZmrk + 0U, // VPMOVSQDZrr + 0U, // VPMOVSQDZrrk + 0U, // VPMOVSQDZrrkz + 0U, // VPMOVSQWZ128mr + 0U, // VPMOVSQWZ128mrk + 0U, // VPMOVSQWZ128rr + 0U, // VPMOVSQWZ128rrk + 0U, // VPMOVSQWZ128rrkz + 0U, // VPMOVSQWZ256mr + 0U, // VPMOVSQWZ256mrk + 0U, // VPMOVSQWZ256rr + 0U, // VPMOVSQWZ256rrk + 0U, // VPMOVSQWZ256rrkz + 0U, // VPMOVSQWZmr + 0U, // VPMOVSQWZmrk + 0U, // VPMOVSQWZrr + 0U, // VPMOVSQWZrrk + 0U, // VPMOVSQWZrrkz + 0U, // VPMOVSWBZ128mr + 0U, // VPMOVSWBZ128mrk + 0U, // VPMOVSWBZ128rr + 0U, // VPMOVSWBZ128rrk + 0U, // VPMOVSWBZ128rrkz + 0U, // VPMOVSWBZ256mr + 0U, // VPMOVSWBZ256mrk + 0U, // VPMOVSWBZ256rr + 0U, // VPMOVSWBZ256rrk + 0U, // VPMOVSWBZ256rrkz + 0U, // VPMOVSWBZmr + 0U, // VPMOVSWBZmrk + 0U, // VPMOVSWBZrr + 0U, // VPMOVSWBZrrk + 0U, // VPMOVSWBZrrkz + 0U, // VPMOVSXBDYrm + 0U, // VPMOVSXBDYrr + 0U, // VPMOVSXBDZ128rm + 0U, // VPMOVSXBDZ128rmk + 0U, // VPMOVSXBDZ128rmkz + 0U, // VPMOVSXBDZ128rr + 0U, // VPMOVSXBDZ128rrk + 0U, // VPMOVSXBDZ128rrkz + 0U, // VPMOVSXBDZ256rm + 0U, // VPMOVSXBDZ256rmk + 0U, // VPMOVSXBDZ256rmkz + 0U, // VPMOVSXBDZ256rr + 0U, // VPMOVSXBDZ256rrk + 0U, // VPMOVSXBDZ256rrkz + 0U, // VPMOVSXBDZrm + 0U, // VPMOVSXBDZrmk + 0U, // VPMOVSXBDZrmkz + 0U, // VPMOVSXBDZrr + 0U, // VPMOVSXBDZrrk + 0U, // VPMOVSXBDZrrkz + 0U, // VPMOVSXBDrm + 0U, // VPMOVSXBDrr + 0U, // VPMOVSXBQYrm + 0U, // VPMOVSXBQYrr + 0U, // VPMOVSXBQZ128rm + 0U, // VPMOVSXBQZ128rmk + 0U, // VPMOVSXBQZ128rmkz + 0U, // VPMOVSXBQZ128rr + 0U, // VPMOVSXBQZ128rrk + 0U, // VPMOVSXBQZ128rrkz + 0U, // VPMOVSXBQZ256rm + 0U, // VPMOVSXBQZ256rmk + 0U, // VPMOVSXBQZ256rmkz + 0U, // VPMOVSXBQZ256rr + 0U, // VPMOVSXBQZ256rrk + 0U, // VPMOVSXBQZ256rrkz + 0U, // VPMOVSXBQZrm + 0U, // VPMOVSXBQZrmk + 0U, // VPMOVSXBQZrmkz + 0U, // VPMOVSXBQZrr + 0U, // VPMOVSXBQZrrk + 0U, // VPMOVSXBQZrrkz + 0U, // VPMOVSXBQrm + 0U, // VPMOVSXBQrr + 0U, // VPMOVSXBWYrm + 0U, // VPMOVSXBWYrr + 0U, // VPMOVSXBWZ128rm + 0U, // VPMOVSXBWZ128rmk + 0U, // VPMOVSXBWZ128rmkz + 0U, // VPMOVSXBWZ128rr + 0U, // VPMOVSXBWZ128rrk + 0U, // VPMOVSXBWZ128rrkz + 0U, // VPMOVSXBWZ256rm + 0U, // VPMOVSXBWZ256rmk + 0U, // VPMOVSXBWZ256rmkz + 0U, // VPMOVSXBWZ256rr + 0U, // VPMOVSXBWZ256rrk + 0U, // VPMOVSXBWZ256rrkz + 0U, // VPMOVSXBWZrm + 0U, // VPMOVSXBWZrmk + 0U, // VPMOVSXBWZrmkz + 0U, // VPMOVSXBWZrr + 0U, // VPMOVSXBWZrrk + 0U, // VPMOVSXBWZrrkz + 0U, // VPMOVSXBWrm + 0U, // VPMOVSXBWrr + 0U, // VPMOVSXDQYrm + 0U, // VPMOVSXDQYrr + 0U, // VPMOVSXDQZ128rm + 0U, // VPMOVSXDQZ128rmk + 0U, // VPMOVSXDQZ128rmkz + 0U, // VPMOVSXDQZ128rr + 0U, // VPMOVSXDQZ128rrk + 0U, // VPMOVSXDQZ128rrkz + 0U, // VPMOVSXDQZ256rm + 0U, // VPMOVSXDQZ256rmk + 0U, // VPMOVSXDQZ256rmkz + 0U, // VPMOVSXDQZ256rr + 0U, // VPMOVSXDQZ256rrk + 0U, // VPMOVSXDQZ256rrkz + 0U, // VPMOVSXDQZrm + 0U, // VPMOVSXDQZrmk + 0U, // VPMOVSXDQZrmkz + 0U, // VPMOVSXDQZrr + 0U, // VPMOVSXDQZrrk + 0U, // VPMOVSXDQZrrkz + 0U, // VPMOVSXDQrm + 0U, // VPMOVSXDQrr + 0U, // VPMOVSXWDYrm + 0U, // VPMOVSXWDYrr + 0U, // VPMOVSXWDZ128rm + 0U, // VPMOVSXWDZ128rmk + 0U, // VPMOVSXWDZ128rmkz + 0U, // VPMOVSXWDZ128rr + 0U, // VPMOVSXWDZ128rrk + 0U, // VPMOVSXWDZ128rrkz + 0U, // VPMOVSXWDZ256rm + 0U, // VPMOVSXWDZ256rmk + 0U, // VPMOVSXWDZ256rmkz + 0U, // VPMOVSXWDZ256rr + 0U, // VPMOVSXWDZ256rrk + 0U, // VPMOVSXWDZ256rrkz + 0U, // VPMOVSXWDZrm + 0U, // VPMOVSXWDZrmk + 0U, // VPMOVSXWDZrmkz + 0U, // VPMOVSXWDZrr + 0U, // VPMOVSXWDZrrk + 0U, // VPMOVSXWDZrrkz + 0U, // VPMOVSXWDrm + 0U, // VPMOVSXWDrr + 0U, // VPMOVSXWQYrm + 0U, // VPMOVSXWQYrr + 0U, // VPMOVSXWQZ128rm + 0U, // VPMOVSXWQZ128rmk + 0U, // VPMOVSXWQZ128rmkz + 0U, // VPMOVSXWQZ128rr + 0U, // VPMOVSXWQZ128rrk + 0U, // VPMOVSXWQZ128rrkz + 0U, // VPMOVSXWQZ256rm + 0U, // VPMOVSXWQZ256rmk + 0U, // VPMOVSXWQZ256rmkz + 0U, // VPMOVSXWQZ256rr + 0U, // VPMOVSXWQZ256rrk + 0U, // VPMOVSXWQZ256rrkz + 0U, // VPMOVSXWQZrm + 0U, // VPMOVSXWQZrmk + 0U, // VPMOVSXWQZrmkz + 0U, // VPMOVSXWQZrr + 0U, // VPMOVSXWQZrrk + 0U, // VPMOVSXWQZrrkz + 0U, // VPMOVSXWQrm + 0U, // VPMOVSXWQrr + 0U, // VPMOVUSDBZ128mr + 0U, // VPMOVUSDBZ128mrk + 0U, // VPMOVUSDBZ128rr + 0U, // VPMOVUSDBZ128rrk + 0U, // VPMOVUSDBZ128rrkz + 0U, // VPMOVUSDBZ256mr + 0U, // VPMOVUSDBZ256mrk + 0U, // VPMOVUSDBZ256rr + 0U, // VPMOVUSDBZ256rrk + 0U, // VPMOVUSDBZ256rrkz + 0U, // VPMOVUSDBZmr + 0U, // VPMOVUSDBZmrk + 0U, // VPMOVUSDBZrr + 0U, // VPMOVUSDBZrrk + 0U, // VPMOVUSDBZrrkz + 0U, // VPMOVUSDWZ128mr + 0U, // VPMOVUSDWZ128mrk + 0U, // VPMOVUSDWZ128rr + 0U, // VPMOVUSDWZ128rrk + 0U, // VPMOVUSDWZ128rrkz + 0U, // VPMOVUSDWZ256mr + 0U, // VPMOVUSDWZ256mrk + 0U, // VPMOVUSDWZ256rr + 0U, // VPMOVUSDWZ256rrk + 0U, // VPMOVUSDWZ256rrkz + 0U, // VPMOVUSDWZmr + 0U, // VPMOVUSDWZmrk + 0U, // VPMOVUSDWZrr + 0U, // VPMOVUSDWZrrk + 0U, // VPMOVUSDWZrrkz + 0U, // VPMOVUSQBZ128mr + 0U, // VPMOVUSQBZ128mrk + 0U, // VPMOVUSQBZ128rr + 0U, // VPMOVUSQBZ128rrk + 0U, // VPMOVUSQBZ128rrkz + 0U, // VPMOVUSQBZ256mr + 0U, // VPMOVUSQBZ256mrk + 0U, // VPMOVUSQBZ256rr + 0U, // VPMOVUSQBZ256rrk + 0U, // VPMOVUSQBZ256rrkz + 0U, // VPMOVUSQBZmr + 0U, // VPMOVUSQBZmrk + 0U, // VPMOVUSQBZrr + 0U, // VPMOVUSQBZrrk + 0U, // VPMOVUSQBZrrkz + 0U, // VPMOVUSQDZ128mr + 0U, // VPMOVUSQDZ128mrk + 0U, // VPMOVUSQDZ128rr + 0U, // VPMOVUSQDZ128rrk + 0U, // VPMOVUSQDZ128rrkz + 0U, // VPMOVUSQDZ256mr + 0U, // VPMOVUSQDZ256mrk + 0U, // VPMOVUSQDZ256rr + 0U, // VPMOVUSQDZ256rrk + 0U, // VPMOVUSQDZ256rrkz + 0U, // VPMOVUSQDZmr + 0U, // VPMOVUSQDZmrk + 0U, // VPMOVUSQDZrr + 0U, // VPMOVUSQDZrrk + 0U, // VPMOVUSQDZrrkz + 0U, // VPMOVUSQWZ128mr + 0U, // VPMOVUSQWZ128mrk + 0U, // VPMOVUSQWZ128rr + 0U, // VPMOVUSQWZ128rrk + 0U, // VPMOVUSQWZ128rrkz + 0U, // VPMOVUSQWZ256mr + 0U, // VPMOVUSQWZ256mrk + 0U, // VPMOVUSQWZ256rr + 0U, // VPMOVUSQWZ256rrk + 0U, // VPMOVUSQWZ256rrkz + 0U, // VPMOVUSQWZmr + 0U, // VPMOVUSQWZmrk + 0U, // VPMOVUSQWZrr + 0U, // VPMOVUSQWZrrk + 0U, // VPMOVUSQWZrrkz + 0U, // VPMOVUSWBZ128mr + 0U, // VPMOVUSWBZ128mrk + 0U, // VPMOVUSWBZ128rr + 0U, // VPMOVUSWBZ128rrk + 0U, // VPMOVUSWBZ128rrkz + 0U, // VPMOVUSWBZ256mr + 0U, // VPMOVUSWBZ256mrk + 0U, // VPMOVUSWBZ256rr + 0U, // VPMOVUSWBZ256rrk + 0U, // VPMOVUSWBZ256rrkz + 0U, // VPMOVUSWBZmr + 0U, // VPMOVUSWBZmrk + 0U, // VPMOVUSWBZrr + 0U, // VPMOVUSWBZrrk + 0U, // VPMOVUSWBZrrkz + 0U, // VPMOVW2MZ128rr + 0U, // VPMOVW2MZ256rr + 0U, // VPMOVW2MZrr + 0U, // VPMOVWBZ128mr + 0U, // VPMOVWBZ128mrk + 0U, // VPMOVWBZ128rr + 0U, // VPMOVWBZ128rrk + 0U, // VPMOVWBZ128rrkz + 0U, // VPMOVWBZ256mr + 0U, // VPMOVWBZ256mrk + 0U, // VPMOVWBZ256rr + 0U, // VPMOVWBZ256rrk + 0U, // VPMOVWBZ256rrkz + 0U, // VPMOVWBZmr + 0U, // VPMOVWBZmrk + 0U, // VPMOVWBZrr + 0U, // VPMOVWBZrrk + 0U, // VPMOVWBZrrkz + 0U, // VPMOVZXBDYrm + 0U, // VPMOVZXBDYrr + 0U, // VPMOVZXBDZ128rm + 0U, // VPMOVZXBDZ128rmk + 0U, // VPMOVZXBDZ128rmkz + 0U, // VPMOVZXBDZ128rr + 0U, // VPMOVZXBDZ128rrk + 0U, // VPMOVZXBDZ128rrkz + 0U, // VPMOVZXBDZ256rm + 0U, // VPMOVZXBDZ256rmk + 0U, // VPMOVZXBDZ256rmkz + 0U, // VPMOVZXBDZ256rr + 0U, // VPMOVZXBDZ256rrk + 0U, // VPMOVZXBDZ256rrkz + 0U, // VPMOVZXBDZrm + 0U, // VPMOVZXBDZrmk + 0U, // VPMOVZXBDZrmkz + 0U, // VPMOVZXBDZrr + 0U, // VPMOVZXBDZrrk + 0U, // VPMOVZXBDZrrkz + 0U, // VPMOVZXBDrm + 0U, // VPMOVZXBDrr + 0U, // VPMOVZXBQYrm + 0U, // VPMOVZXBQYrr + 0U, // VPMOVZXBQZ128rm + 0U, // VPMOVZXBQZ128rmk + 0U, // VPMOVZXBQZ128rmkz + 0U, // VPMOVZXBQZ128rr + 0U, // VPMOVZXBQZ128rrk + 0U, // VPMOVZXBQZ128rrkz + 0U, // VPMOVZXBQZ256rm + 0U, // VPMOVZXBQZ256rmk + 0U, // VPMOVZXBQZ256rmkz + 0U, // VPMOVZXBQZ256rr + 0U, // VPMOVZXBQZ256rrk + 0U, // VPMOVZXBQZ256rrkz + 0U, // VPMOVZXBQZrm + 0U, // VPMOVZXBQZrmk + 0U, // VPMOVZXBQZrmkz + 0U, // VPMOVZXBQZrr + 0U, // VPMOVZXBQZrrk + 0U, // VPMOVZXBQZrrkz + 0U, // VPMOVZXBQrm + 0U, // VPMOVZXBQrr + 0U, // VPMOVZXBWYrm + 0U, // VPMOVZXBWYrr + 0U, // VPMOVZXBWZ128rm + 0U, // VPMOVZXBWZ128rmk + 0U, // VPMOVZXBWZ128rmkz + 0U, // VPMOVZXBWZ128rr + 0U, // VPMOVZXBWZ128rrk + 0U, // VPMOVZXBWZ128rrkz + 0U, // VPMOVZXBWZ256rm + 0U, // VPMOVZXBWZ256rmk + 0U, // VPMOVZXBWZ256rmkz + 0U, // VPMOVZXBWZ256rr + 0U, // VPMOVZXBWZ256rrk + 0U, // VPMOVZXBWZ256rrkz + 0U, // VPMOVZXBWZrm + 0U, // VPMOVZXBWZrmk + 0U, // VPMOVZXBWZrmkz + 0U, // VPMOVZXBWZrr + 0U, // VPMOVZXBWZrrk + 0U, // VPMOVZXBWZrrkz + 0U, // VPMOVZXBWrm + 0U, // VPMOVZXBWrr + 0U, // VPMOVZXDQYrm + 0U, // VPMOVZXDQYrr + 0U, // VPMOVZXDQZ128rm + 0U, // VPMOVZXDQZ128rmk + 0U, // VPMOVZXDQZ128rmkz + 0U, // VPMOVZXDQZ128rr + 0U, // VPMOVZXDQZ128rrk + 0U, // VPMOVZXDQZ128rrkz + 0U, // VPMOVZXDQZ256rm + 0U, // VPMOVZXDQZ256rmk + 0U, // VPMOVZXDQZ256rmkz + 0U, // VPMOVZXDQZ256rr + 0U, // VPMOVZXDQZ256rrk + 0U, // VPMOVZXDQZ256rrkz + 0U, // VPMOVZXDQZrm + 0U, // VPMOVZXDQZrmk + 0U, // VPMOVZXDQZrmkz + 0U, // VPMOVZXDQZrr + 0U, // VPMOVZXDQZrrk + 0U, // VPMOVZXDQZrrkz + 0U, // VPMOVZXDQrm + 0U, // VPMOVZXDQrr + 0U, // VPMOVZXWDYrm + 0U, // VPMOVZXWDYrr + 0U, // VPMOVZXWDZ128rm + 0U, // VPMOVZXWDZ128rmk + 0U, // VPMOVZXWDZ128rmkz + 0U, // VPMOVZXWDZ128rr + 0U, // VPMOVZXWDZ128rrk + 0U, // VPMOVZXWDZ128rrkz + 0U, // VPMOVZXWDZ256rm + 0U, // VPMOVZXWDZ256rmk + 0U, // VPMOVZXWDZ256rmkz + 0U, // VPMOVZXWDZ256rr + 0U, // VPMOVZXWDZ256rrk + 0U, // VPMOVZXWDZ256rrkz + 0U, // VPMOVZXWDZrm + 0U, // VPMOVZXWDZrmk + 0U, // VPMOVZXWDZrmkz + 0U, // VPMOVZXWDZrr + 0U, // VPMOVZXWDZrrk + 0U, // VPMOVZXWDZrrkz + 0U, // VPMOVZXWDrm + 0U, // VPMOVZXWDrr + 0U, // VPMOVZXWQYrm + 0U, // VPMOVZXWQYrr + 0U, // VPMOVZXWQZ128rm + 0U, // VPMOVZXWQZ128rmk + 0U, // VPMOVZXWQZ128rmkz + 0U, // VPMOVZXWQZ128rr + 0U, // VPMOVZXWQZ128rrk + 0U, // VPMOVZXWQZ128rrkz + 0U, // VPMOVZXWQZ256rm + 0U, // VPMOVZXWQZ256rmk + 0U, // VPMOVZXWQZ256rmkz + 0U, // VPMOVZXWQZ256rr + 0U, // VPMOVZXWQZ256rrk + 0U, // VPMOVZXWQZ256rrkz + 0U, // VPMOVZXWQZrm + 0U, // VPMOVZXWQZrmk + 0U, // VPMOVZXWQZrmkz + 0U, // VPMOVZXWQZrr + 0U, // VPMOVZXWQZrrk + 0U, // VPMOVZXWQZrrkz + 0U, // VPMOVZXWQrm + 0U, // VPMOVZXWQrr + 0U, // VPMULDQYrm + 0U, // VPMULDQYrr + 0U, // VPMULDQZ128rm + 0U, // VPMULDQZ128rmb + 0U, // VPMULDQZ128rmbk + 0U, // VPMULDQZ128rmbkz + 0U, // VPMULDQZ128rmk + 0U, // VPMULDQZ128rmkz + 0U, // VPMULDQZ128rr + 0U, // VPMULDQZ128rrk + 0U, // VPMULDQZ128rrkz + 0U, // VPMULDQZ256rm + 0U, // VPMULDQZ256rmb + 0U, // VPMULDQZ256rmbk + 0U, // VPMULDQZ256rmbkz + 0U, // VPMULDQZ256rmk + 0U, // VPMULDQZ256rmkz + 0U, // VPMULDQZ256rr + 0U, // VPMULDQZ256rrk + 0U, // VPMULDQZ256rrkz + 0U, // VPMULDQZrm + 0U, // VPMULDQZrmb + 0U, // VPMULDQZrmbk + 0U, // VPMULDQZrmbkz + 0U, // VPMULDQZrmk + 0U, // VPMULDQZrmkz + 0U, // VPMULDQZrr + 0U, // VPMULDQZrrk + 0U, // VPMULDQZrrkz + 0U, // VPMULDQrm + 0U, // VPMULDQrr + 0U, // VPMULHRSWYrm + 0U, // VPMULHRSWYrr + 0U, // VPMULHRSWZ128rm + 0U, // VPMULHRSWZ128rmk + 0U, // VPMULHRSWZ128rmkz + 0U, // VPMULHRSWZ128rr + 0U, // VPMULHRSWZ128rrk + 0U, // VPMULHRSWZ128rrkz + 0U, // VPMULHRSWZ256rm + 0U, // VPMULHRSWZ256rmk + 0U, // VPMULHRSWZ256rmkz + 0U, // VPMULHRSWZ256rr + 0U, // VPMULHRSWZ256rrk + 0U, // VPMULHRSWZ256rrkz + 0U, // VPMULHRSWZrm + 0U, // VPMULHRSWZrmk + 0U, // VPMULHRSWZrmkz + 0U, // VPMULHRSWZrr + 0U, // VPMULHRSWZrrk + 0U, // VPMULHRSWZrrkz + 0U, // VPMULHRSWrm + 0U, // VPMULHRSWrr + 0U, // VPMULHUWYrm + 0U, // VPMULHUWYrr + 0U, // VPMULHUWZ128rm + 0U, // VPMULHUWZ128rmk + 0U, // VPMULHUWZ128rmkz + 0U, // VPMULHUWZ128rr + 0U, // VPMULHUWZ128rrk + 0U, // VPMULHUWZ128rrkz + 0U, // VPMULHUWZ256rm + 0U, // VPMULHUWZ256rmk + 0U, // VPMULHUWZ256rmkz + 0U, // VPMULHUWZ256rr + 0U, // VPMULHUWZ256rrk + 0U, // VPMULHUWZ256rrkz + 0U, // VPMULHUWZrm + 0U, // VPMULHUWZrmk + 0U, // VPMULHUWZrmkz + 0U, // VPMULHUWZrr + 0U, // VPMULHUWZrrk + 0U, // VPMULHUWZrrkz + 0U, // VPMULHUWrm + 0U, // VPMULHUWrr + 0U, // VPMULHWYrm + 0U, // VPMULHWYrr + 0U, // VPMULHWZ128rm + 0U, // VPMULHWZ128rmk + 0U, // VPMULHWZ128rmkz + 0U, // VPMULHWZ128rr + 0U, // VPMULHWZ128rrk + 0U, // VPMULHWZ128rrkz + 0U, // VPMULHWZ256rm + 0U, // VPMULHWZ256rmk + 0U, // VPMULHWZ256rmkz + 0U, // VPMULHWZ256rr + 0U, // VPMULHWZ256rrk + 0U, // VPMULHWZ256rrkz + 0U, // VPMULHWZrm + 0U, // VPMULHWZrmk + 0U, // VPMULHWZrmkz + 0U, // VPMULHWZrr + 0U, // VPMULHWZrrk + 0U, // VPMULHWZrrkz + 0U, // VPMULHWrm + 0U, // VPMULHWrr + 0U, // VPMULLDYrm + 0U, // VPMULLDYrr + 0U, // VPMULLDZ128rm + 0U, // VPMULLDZ128rmb + 0U, // VPMULLDZ128rmbk + 0U, // VPMULLDZ128rmbkz + 0U, // VPMULLDZ128rmk + 0U, // VPMULLDZ128rmkz + 0U, // VPMULLDZ128rr + 0U, // VPMULLDZ128rrk + 0U, // VPMULLDZ128rrkz + 0U, // VPMULLDZ256rm + 0U, // VPMULLDZ256rmb + 0U, // VPMULLDZ256rmbk + 0U, // VPMULLDZ256rmbkz + 0U, // VPMULLDZ256rmk + 0U, // VPMULLDZ256rmkz + 0U, // VPMULLDZ256rr + 0U, // VPMULLDZ256rrk + 0U, // VPMULLDZ256rrkz + 0U, // VPMULLDZrm + 0U, // VPMULLDZrmb + 0U, // VPMULLDZrmbk + 0U, // VPMULLDZrmbkz + 0U, // VPMULLDZrmk + 0U, // VPMULLDZrmkz + 0U, // VPMULLDZrr + 0U, // VPMULLDZrrk + 0U, // VPMULLDZrrkz + 0U, // VPMULLDrm + 0U, // VPMULLDrr + 0U, // VPMULLQZ128rm + 0U, // VPMULLQZ128rmb + 0U, // VPMULLQZ128rmbk + 0U, // VPMULLQZ128rmbkz + 0U, // VPMULLQZ128rmk + 0U, // VPMULLQZ128rmkz + 0U, // VPMULLQZ128rr + 0U, // VPMULLQZ128rrk + 0U, // VPMULLQZ128rrkz + 0U, // VPMULLQZ256rm + 0U, // VPMULLQZ256rmb + 0U, // VPMULLQZ256rmbk + 0U, // VPMULLQZ256rmbkz + 0U, // VPMULLQZ256rmk + 0U, // VPMULLQZ256rmkz + 0U, // VPMULLQZ256rr + 0U, // VPMULLQZ256rrk + 0U, // VPMULLQZ256rrkz + 0U, // VPMULLQZrm + 0U, // VPMULLQZrmb + 0U, // VPMULLQZrmbk + 0U, // VPMULLQZrmbkz + 0U, // VPMULLQZrmk + 0U, // VPMULLQZrmkz + 0U, // VPMULLQZrr + 0U, // VPMULLQZrrk + 0U, // VPMULLQZrrkz + 0U, // VPMULLWYrm + 0U, // VPMULLWYrr + 0U, // VPMULLWZ128rm + 0U, // VPMULLWZ128rmk + 0U, // VPMULLWZ128rmkz + 0U, // VPMULLWZ128rr + 0U, // VPMULLWZ128rrk + 0U, // VPMULLWZ128rrkz + 0U, // VPMULLWZ256rm + 0U, // VPMULLWZ256rmk + 0U, // VPMULLWZ256rmkz + 0U, // VPMULLWZ256rr + 0U, // VPMULLWZ256rrk + 0U, // VPMULLWZ256rrkz + 0U, // VPMULLWZrm + 0U, // VPMULLWZrmk + 0U, // VPMULLWZrmkz + 0U, // VPMULLWZrr + 0U, // VPMULLWZrrk + 0U, // VPMULLWZrrkz + 0U, // VPMULLWrm + 0U, // VPMULLWrr + 0U, // VPMULTISHIFTQBZ128rm + 0U, // VPMULTISHIFTQBZ128rmb + 0U, // VPMULTISHIFTQBZ128rmbk + 0U, // VPMULTISHIFTQBZ128rmbkz + 0U, // VPMULTISHIFTQBZ128rmk + 0U, // VPMULTISHIFTQBZ128rmkz + 0U, // VPMULTISHIFTQBZ128rr + 0U, // VPMULTISHIFTQBZ128rrk + 0U, // VPMULTISHIFTQBZ128rrkz + 0U, // VPMULTISHIFTQBZ256rm + 0U, // VPMULTISHIFTQBZ256rmb + 0U, // VPMULTISHIFTQBZ256rmbk + 0U, // VPMULTISHIFTQBZ256rmbkz + 0U, // VPMULTISHIFTQBZ256rmk + 0U, // VPMULTISHIFTQBZ256rmkz + 0U, // VPMULTISHIFTQBZ256rr + 0U, // VPMULTISHIFTQBZ256rrk + 0U, // VPMULTISHIFTQBZ256rrkz + 0U, // VPMULTISHIFTQBZrm + 0U, // VPMULTISHIFTQBZrmb + 0U, // VPMULTISHIFTQBZrmbk + 0U, // VPMULTISHIFTQBZrmbkz + 0U, // VPMULTISHIFTQBZrmk + 0U, // VPMULTISHIFTQBZrmkz + 0U, // VPMULTISHIFTQBZrr + 0U, // VPMULTISHIFTQBZrrk + 0U, // VPMULTISHIFTQBZrrkz + 0U, // VPMULUDQYrm + 0U, // VPMULUDQYrr + 0U, // VPMULUDQZ128rm + 0U, // VPMULUDQZ128rmb + 0U, // VPMULUDQZ128rmbk + 0U, // VPMULUDQZ128rmbkz + 0U, // VPMULUDQZ128rmk + 0U, // VPMULUDQZ128rmkz + 0U, // VPMULUDQZ128rr + 0U, // VPMULUDQZ128rrk + 0U, // VPMULUDQZ128rrkz + 0U, // VPMULUDQZ256rm + 0U, // VPMULUDQZ256rmb + 0U, // VPMULUDQZ256rmbk + 0U, // VPMULUDQZ256rmbkz + 0U, // VPMULUDQZ256rmk + 0U, // VPMULUDQZ256rmkz + 0U, // VPMULUDQZ256rr + 0U, // VPMULUDQZ256rrk + 0U, // VPMULUDQZ256rrkz + 0U, // VPMULUDQZrm + 0U, // VPMULUDQZrmb + 0U, // VPMULUDQZrmbk + 0U, // VPMULUDQZrmbkz + 0U, // VPMULUDQZrmk + 0U, // VPMULUDQZrmkz + 0U, // VPMULUDQZrr + 0U, // VPMULUDQZrrk + 0U, // VPMULUDQZrrkz + 0U, // VPMULUDQrm + 0U, // VPMULUDQrr + 0U, // VPOPCNTBZ128rm + 0U, // VPOPCNTBZ128rmk + 0U, // VPOPCNTBZ128rmkz + 0U, // VPOPCNTBZ128rr + 0U, // VPOPCNTBZ128rrk + 0U, // VPOPCNTBZ128rrkz + 0U, // VPOPCNTBZ256rm + 0U, // VPOPCNTBZ256rmk + 0U, // VPOPCNTBZ256rmkz + 0U, // VPOPCNTBZ256rr + 0U, // VPOPCNTBZ256rrk + 0U, // VPOPCNTBZ256rrkz + 0U, // VPOPCNTBZrm + 0U, // VPOPCNTBZrmk + 0U, // VPOPCNTBZrmkz + 0U, // VPOPCNTBZrr + 0U, // VPOPCNTBZrrk + 0U, // VPOPCNTBZrrkz + 0U, // VPOPCNTDZ128rm + 0U, // VPOPCNTDZ128rmb + 0U, // VPOPCNTDZ128rmbk + 0U, // VPOPCNTDZ128rmbkz + 0U, // VPOPCNTDZ128rmk + 0U, // VPOPCNTDZ128rmkz + 0U, // VPOPCNTDZ128rr + 0U, // VPOPCNTDZ128rrk + 0U, // VPOPCNTDZ128rrkz + 0U, // VPOPCNTDZ256rm + 0U, // VPOPCNTDZ256rmb + 0U, // VPOPCNTDZ256rmbk + 0U, // VPOPCNTDZ256rmbkz + 0U, // VPOPCNTDZ256rmk + 0U, // VPOPCNTDZ256rmkz + 0U, // VPOPCNTDZ256rr + 0U, // VPOPCNTDZ256rrk + 0U, // VPOPCNTDZ256rrkz + 0U, // VPOPCNTDZrm + 0U, // VPOPCNTDZrmb + 0U, // VPOPCNTDZrmbk + 0U, // VPOPCNTDZrmbkz + 0U, // VPOPCNTDZrmk + 0U, // VPOPCNTDZrmkz + 0U, // VPOPCNTDZrr + 0U, // VPOPCNTDZrrk + 0U, // VPOPCNTDZrrkz + 0U, // VPOPCNTQZ128rm + 0U, // VPOPCNTQZ128rmb + 0U, // VPOPCNTQZ128rmbk + 0U, // VPOPCNTQZ128rmbkz + 0U, // VPOPCNTQZ128rmk + 0U, // VPOPCNTQZ128rmkz + 0U, // VPOPCNTQZ128rr + 0U, // VPOPCNTQZ128rrk + 0U, // VPOPCNTQZ128rrkz + 0U, // VPOPCNTQZ256rm + 0U, // VPOPCNTQZ256rmb + 0U, // VPOPCNTQZ256rmbk + 0U, // VPOPCNTQZ256rmbkz + 0U, // VPOPCNTQZ256rmk + 0U, // VPOPCNTQZ256rmkz + 0U, // VPOPCNTQZ256rr + 0U, // VPOPCNTQZ256rrk + 0U, // VPOPCNTQZ256rrkz + 0U, // VPOPCNTQZrm + 0U, // VPOPCNTQZrmb + 0U, // VPOPCNTQZrmbk + 0U, // VPOPCNTQZrmbkz + 0U, // VPOPCNTQZrmk + 0U, // VPOPCNTQZrmkz + 0U, // VPOPCNTQZrr + 0U, // VPOPCNTQZrrk + 0U, // VPOPCNTQZrrkz + 0U, // VPOPCNTWZ128rm + 0U, // VPOPCNTWZ128rmk + 0U, // VPOPCNTWZ128rmkz + 0U, // VPOPCNTWZ128rr + 0U, // VPOPCNTWZ128rrk + 0U, // VPOPCNTWZ128rrkz + 0U, // VPOPCNTWZ256rm + 0U, // VPOPCNTWZ256rmk + 0U, // VPOPCNTWZ256rmkz + 0U, // VPOPCNTWZ256rr + 0U, // VPOPCNTWZ256rrk + 0U, // VPOPCNTWZ256rrkz + 0U, // VPOPCNTWZrm + 0U, // VPOPCNTWZrmk + 0U, // VPOPCNTWZrmkz + 0U, // VPOPCNTWZrr + 0U, // VPOPCNTWZrrk + 0U, // VPOPCNTWZrrkz + 0U, // VPORDZ128rm + 0U, // VPORDZ128rmb + 0U, // VPORDZ128rmbk + 0U, // VPORDZ128rmbkz + 0U, // VPORDZ128rmk + 0U, // VPORDZ128rmkz + 0U, // VPORDZ128rr + 0U, // VPORDZ128rrk + 0U, // VPORDZ128rrkz + 0U, // VPORDZ256rm + 0U, // VPORDZ256rmb + 0U, // VPORDZ256rmbk + 0U, // VPORDZ256rmbkz + 0U, // VPORDZ256rmk + 0U, // VPORDZ256rmkz + 0U, // VPORDZ256rr + 0U, // VPORDZ256rrk + 0U, // VPORDZ256rrkz + 0U, // VPORDZrm + 0U, // VPORDZrmb + 0U, // VPORDZrmbk + 0U, // VPORDZrmbkz + 0U, // VPORDZrmk + 0U, // VPORDZrmkz + 0U, // VPORDZrr + 0U, // VPORDZrrk + 0U, // VPORDZrrkz + 0U, // VPORQZ128rm + 0U, // VPORQZ128rmb + 0U, // VPORQZ128rmbk + 0U, // VPORQZ128rmbkz + 0U, // VPORQZ128rmk + 0U, // VPORQZ128rmkz + 0U, // VPORQZ128rr + 0U, // VPORQZ128rrk + 0U, // VPORQZ128rrkz + 0U, // VPORQZ256rm + 0U, // VPORQZ256rmb + 0U, // VPORQZ256rmbk + 0U, // VPORQZ256rmbkz + 0U, // VPORQZ256rmk + 0U, // VPORQZ256rmkz + 0U, // VPORQZ256rr + 0U, // VPORQZ256rrk + 0U, // VPORQZ256rrkz + 0U, // VPORQZrm + 0U, // VPORQZrmb + 0U, // VPORQZrmbk + 0U, // VPORQZrmbkz + 0U, // VPORQZrmk + 0U, // VPORQZrmkz + 0U, // VPORQZrr + 0U, // VPORQZrrk + 0U, // VPORQZrrkz + 0U, // VPORYrm + 0U, // VPORYrr + 0U, // VPORrm + 0U, // VPORrr + 0U, // VPPERMrmr + 0U, // VPPERMrrm + 0U, // VPPERMrrr + 0U, // VPPERMrrr_REV + 0U, // VPROLDZ128mbi + 0U, // VPROLDZ128mbik + 0U, // VPROLDZ128mbikz + 0U, // VPROLDZ128mi + 0U, // VPROLDZ128mik + 0U, // VPROLDZ128mikz + 0U, // VPROLDZ128ri + 0U, // VPROLDZ128rik + 0U, // VPROLDZ128rikz + 0U, // VPROLDZ256mbi + 0U, // VPROLDZ256mbik + 0U, // VPROLDZ256mbikz + 0U, // VPROLDZ256mi + 0U, // VPROLDZ256mik + 0U, // VPROLDZ256mikz + 0U, // VPROLDZ256ri + 0U, // VPROLDZ256rik + 0U, // VPROLDZ256rikz + 0U, // VPROLDZmbi + 0U, // VPROLDZmbik + 0U, // VPROLDZmbikz + 0U, // VPROLDZmi + 0U, // VPROLDZmik + 0U, // VPROLDZmikz + 0U, // VPROLDZri + 0U, // VPROLDZrik + 0U, // VPROLDZrikz + 0U, // VPROLQZ128mbi + 0U, // VPROLQZ128mbik + 0U, // VPROLQZ128mbikz + 0U, // VPROLQZ128mi + 0U, // VPROLQZ128mik + 0U, // VPROLQZ128mikz + 0U, // VPROLQZ128ri + 0U, // VPROLQZ128rik + 0U, // VPROLQZ128rikz + 0U, // VPROLQZ256mbi + 0U, // VPROLQZ256mbik + 0U, // VPROLQZ256mbikz + 0U, // VPROLQZ256mi + 0U, // VPROLQZ256mik + 0U, // VPROLQZ256mikz + 0U, // VPROLQZ256ri + 0U, // VPROLQZ256rik + 0U, // VPROLQZ256rikz + 0U, // VPROLQZmbi + 0U, // VPROLQZmbik + 0U, // VPROLQZmbikz + 0U, // VPROLQZmi + 0U, // VPROLQZmik + 0U, // VPROLQZmikz + 0U, // VPROLQZri + 0U, // VPROLQZrik + 0U, // VPROLQZrikz + 0U, // VPROLVDZ128rm + 0U, // VPROLVDZ128rmb + 0U, // VPROLVDZ128rmbk + 0U, // VPROLVDZ128rmbkz + 0U, // VPROLVDZ128rmk + 0U, // VPROLVDZ128rmkz + 0U, // VPROLVDZ128rr + 0U, // VPROLVDZ128rrk + 0U, // VPROLVDZ128rrkz + 0U, // VPROLVDZ256rm + 0U, // VPROLVDZ256rmb + 0U, // VPROLVDZ256rmbk + 0U, // VPROLVDZ256rmbkz + 0U, // VPROLVDZ256rmk + 0U, // VPROLVDZ256rmkz + 0U, // VPROLVDZ256rr + 0U, // VPROLVDZ256rrk + 0U, // VPROLVDZ256rrkz + 0U, // VPROLVDZrm + 0U, // VPROLVDZrmb + 0U, // VPROLVDZrmbk + 0U, // VPROLVDZrmbkz + 0U, // VPROLVDZrmk + 0U, // VPROLVDZrmkz + 0U, // VPROLVDZrr + 0U, // VPROLVDZrrk + 0U, // VPROLVDZrrkz + 0U, // VPROLVQZ128rm + 0U, // VPROLVQZ128rmb + 0U, // VPROLVQZ128rmbk + 0U, // VPROLVQZ128rmbkz + 0U, // VPROLVQZ128rmk + 0U, // VPROLVQZ128rmkz + 0U, // VPROLVQZ128rr + 0U, // VPROLVQZ128rrk + 0U, // VPROLVQZ128rrkz + 0U, // VPROLVQZ256rm + 0U, // VPROLVQZ256rmb + 0U, // VPROLVQZ256rmbk + 0U, // VPROLVQZ256rmbkz + 0U, // VPROLVQZ256rmk + 0U, // VPROLVQZ256rmkz + 0U, // VPROLVQZ256rr + 0U, // VPROLVQZ256rrk + 0U, // VPROLVQZ256rrkz + 0U, // VPROLVQZrm + 0U, // VPROLVQZrmb + 0U, // VPROLVQZrmbk + 0U, // VPROLVQZrmbkz + 0U, // VPROLVQZrmk + 0U, // VPROLVQZrmkz + 0U, // VPROLVQZrr + 0U, // VPROLVQZrrk + 0U, // VPROLVQZrrkz + 0U, // VPRORDZ128mbi + 0U, // VPRORDZ128mbik + 0U, // VPRORDZ128mbikz + 0U, // VPRORDZ128mi + 0U, // VPRORDZ128mik + 0U, // VPRORDZ128mikz + 0U, // VPRORDZ128ri + 0U, // VPRORDZ128rik + 0U, // VPRORDZ128rikz + 0U, // VPRORDZ256mbi + 0U, // VPRORDZ256mbik + 0U, // VPRORDZ256mbikz + 0U, // VPRORDZ256mi + 0U, // VPRORDZ256mik + 0U, // VPRORDZ256mikz + 0U, // VPRORDZ256ri + 0U, // VPRORDZ256rik + 0U, // VPRORDZ256rikz + 0U, // VPRORDZmbi + 0U, // VPRORDZmbik + 0U, // VPRORDZmbikz + 0U, // VPRORDZmi + 0U, // VPRORDZmik + 0U, // VPRORDZmikz + 0U, // VPRORDZri + 0U, // VPRORDZrik + 0U, // VPRORDZrikz + 0U, // VPRORQZ128mbi + 0U, // VPRORQZ128mbik + 0U, // VPRORQZ128mbikz + 0U, // VPRORQZ128mi + 0U, // VPRORQZ128mik + 0U, // VPRORQZ128mikz + 0U, // VPRORQZ128ri + 0U, // VPRORQZ128rik + 0U, // VPRORQZ128rikz + 0U, // VPRORQZ256mbi + 0U, // VPRORQZ256mbik + 0U, // VPRORQZ256mbikz + 0U, // VPRORQZ256mi + 0U, // VPRORQZ256mik + 0U, // VPRORQZ256mikz + 0U, // VPRORQZ256ri + 0U, // VPRORQZ256rik + 0U, // VPRORQZ256rikz + 0U, // VPRORQZmbi + 0U, // VPRORQZmbik + 0U, // VPRORQZmbikz + 0U, // VPRORQZmi + 0U, // VPRORQZmik + 0U, // VPRORQZmikz + 0U, // VPRORQZri + 0U, // VPRORQZrik + 0U, // VPRORQZrikz + 0U, // VPRORVDZ128rm + 0U, // VPRORVDZ128rmb + 0U, // VPRORVDZ128rmbk + 0U, // VPRORVDZ128rmbkz + 0U, // VPRORVDZ128rmk + 0U, // VPRORVDZ128rmkz + 0U, // VPRORVDZ128rr + 0U, // VPRORVDZ128rrk + 0U, // VPRORVDZ128rrkz + 0U, // VPRORVDZ256rm + 0U, // VPRORVDZ256rmb + 0U, // VPRORVDZ256rmbk + 0U, // VPRORVDZ256rmbkz + 0U, // VPRORVDZ256rmk + 0U, // VPRORVDZ256rmkz + 0U, // VPRORVDZ256rr + 0U, // VPRORVDZ256rrk + 0U, // VPRORVDZ256rrkz + 0U, // VPRORVDZrm + 0U, // VPRORVDZrmb + 0U, // VPRORVDZrmbk + 0U, // VPRORVDZrmbkz + 0U, // VPRORVDZrmk + 0U, // VPRORVDZrmkz + 0U, // VPRORVDZrr + 0U, // VPRORVDZrrk + 0U, // VPRORVDZrrkz + 0U, // VPRORVQZ128rm + 0U, // VPRORVQZ128rmb + 0U, // VPRORVQZ128rmbk + 0U, // VPRORVQZ128rmbkz + 0U, // VPRORVQZ128rmk + 0U, // VPRORVQZ128rmkz + 0U, // VPRORVQZ128rr + 0U, // VPRORVQZ128rrk + 0U, // VPRORVQZ128rrkz + 0U, // VPRORVQZ256rm + 0U, // VPRORVQZ256rmb + 0U, // VPRORVQZ256rmbk + 0U, // VPRORVQZ256rmbkz + 0U, // VPRORVQZ256rmk + 0U, // VPRORVQZ256rmkz + 0U, // VPRORVQZ256rr + 0U, // VPRORVQZ256rrk + 0U, // VPRORVQZ256rrkz + 0U, // VPRORVQZrm + 0U, // VPRORVQZrmb + 0U, // VPRORVQZrmbk + 0U, // VPRORVQZrmbkz + 0U, // VPRORVQZrmk + 0U, // VPRORVQZrmkz + 0U, // VPRORVQZrr + 0U, // VPRORVQZrrk + 0U, // VPRORVQZrrkz + 0U, // VPROTBmi + 0U, // VPROTBmr + 0U, // VPROTBri + 0U, // VPROTBrm + 0U, // VPROTBrr + 0U, // VPROTBrr_REV + 0U, // VPROTDmi + 0U, // VPROTDmr + 0U, // VPROTDri + 0U, // VPROTDrm + 0U, // VPROTDrr + 0U, // VPROTDrr_REV + 0U, // VPROTQmi + 0U, // VPROTQmr + 0U, // VPROTQri + 0U, // VPROTQrm + 0U, // VPROTQrr + 0U, // VPROTQrr_REV + 0U, // VPROTWmi + 0U, // VPROTWmr + 0U, // VPROTWri + 0U, // VPROTWrm + 0U, // VPROTWrr + 0U, // VPROTWrr_REV + 0U, // VPSADBWYrm + 0U, // VPSADBWYrr + 0U, // VPSADBWZ128rm + 0U, // VPSADBWZ128rr + 0U, // VPSADBWZ256rm + 0U, // VPSADBWZ256rr + 0U, // VPSADBWZrm + 0U, // VPSADBWZrr + 0U, // VPSADBWrm + 0U, // VPSADBWrr + 0U, // VPSCATTERDDZ128mr + 0U, // VPSCATTERDDZ256mr + 0U, // VPSCATTERDDZmr + 0U, // VPSCATTERDQZ128mr + 0U, // VPSCATTERDQZ256mr + 0U, // VPSCATTERDQZmr + 0U, // VPSCATTERQDZ128mr + 0U, // VPSCATTERQDZ256mr + 0U, // VPSCATTERQDZmr + 0U, // VPSCATTERQQZ128mr + 0U, // VPSCATTERQQZ256mr + 0U, // VPSCATTERQQZmr + 0U, // VPSHABmr + 0U, // VPSHABrm + 0U, // VPSHABrr + 0U, // VPSHABrr_REV + 0U, // VPSHADmr + 0U, // VPSHADrm + 0U, // VPSHADrr + 0U, // VPSHADrr_REV + 0U, // VPSHAQmr + 0U, // VPSHAQrm + 0U, // VPSHAQrr + 0U, // VPSHAQrr_REV + 0U, // VPSHAWmr + 0U, // VPSHAWrm + 0U, // VPSHAWrr + 0U, // VPSHAWrr_REV + 0U, // VPSHLBmr + 0U, // VPSHLBrm + 0U, // VPSHLBrr + 0U, // VPSHLBrr_REV + 0U, // VPSHLDDZ128rmbi + 0U, // VPSHLDDZ128rmbik + 3U, // VPSHLDDZ128rmbikz + 0U, // VPSHLDDZ128rmi + 0U, // VPSHLDDZ128rmik + 0U, // VPSHLDDZ128rmikz + 0U, // VPSHLDDZ128rri + 0U, // VPSHLDDZ128rrik + 3U, // VPSHLDDZ128rrikz + 0U, // VPSHLDDZ256rmbi + 0U, // VPSHLDDZ256rmbik + 3U, // VPSHLDDZ256rmbikz + 0U, // VPSHLDDZ256rmi + 0U, // VPSHLDDZ256rmik + 0U, // VPSHLDDZ256rmikz + 0U, // VPSHLDDZ256rri + 0U, // VPSHLDDZ256rrik + 3U, // VPSHLDDZ256rrikz + 0U, // VPSHLDDZrmbi + 0U, // VPSHLDDZrmbik + 3U, // VPSHLDDZrmbikz + 0U, // VPSHLDDZrmi + 0U, // VPSHLDDZrmik + 0U, // VPSHLDDZrmikz + 0U, // VPSHLDDZrri + 0U, // VPSHLDDZrrik + 3U, // VPSHLDDZrrikz + 0U, // VPSHLDQZ128rmbi + 0U, // VPSHLDQZ128rmbik + 3U, // VPSHLDQZ128rmbikz + 0U, // VPSHLDQZ128rmi + 0U, // VPSHLDQZ128rmik + 0U, // VPSHLDQZ128rmikz + 0U, // VPSHLDQZ128rri + 0U, // VPSHLDQZ128rrik + 3U, // VPSHLDQZ128rrikz + 0U, // VPSHLDQZ256rmbi + 0U, // VPSHLDQZ256rmbik + 3U, // VPSHLDQZ256rmbikz + 0U, // VPSHLDQZ256rmi + 0U, // VPSHLDQZ256rmik + 0U, // VPSHLDQZ256rmikz + 0U, // VPSHLDQZ256rri + 0U, // VPSHLDQZ256rrik + 3U, // VPSHLDQZ256rrikz + 0U, // VPSHLDQZrmbi + 0U, // VPSHLDQZrmbik + 3U, // VPSHLDQZrmbikz + 0U, // VPSHLDQZrmi + 0U, // VPSHLDQZrmik + 0U, // VPSHLDQZrmikz + 0U, // VPSHLDQZrri + 0U, // VPSHLDQZrrik + 3U, // VPSHLDQZrrikz + 0U, // VPSHLDVDZ128m + 0U, // VPSHLDVDZ128mb + 0U, // VPSHLDVDZ128mbk + 0U, // VPSHLDVDZ128mbkz + 0U, // VPSHLDVDZ128mk + 0U, // VPSHLDVDZ128mkz + 0U, // VPSHLDVDZ128r + 0U, // VPSHLDVDZ128rk + 0U, // VPSHLDVDZ128rkz + 0U, // VPSHLDVDZ256m + 0U, // VPSHLDVDZ256mb + 0U, // VPSHLDVDZ256mbk + 0U, // VPSHLDVDZ256mbkz + 0U, // VPSHLDVDZ256mk + 0U, // VPSHLDVDZ256mkz + 0U, // VPSHLDVDZ256r + 0U, // VPSHLDVDZ256rk + 0U, // VPSHLDVDZ256rkz + 0U, // VPSHLDVDZm + 0U, // VPSHLDVDZmb + 0U, // VPSHLDVDZmbk + 0U, // VPSHLDVDZmbkz + 0U, // VPSHLDVDZmk + 0U, // VPSHLDVDZmkz + 0U, // VPSHLDVDZr + 0U, // VPSHLDVDZrk + 0U, // VPSHLDVDZrkz + 0U, // VPSHLDVQZ128m + 0U, // VPSHLDVQZ128mb + 0U, // VPSHLDVQZ128mbk + 0U, // VPSHLDVQZ128mbkz + 0U, // VPSHLDVQZ128mk + 0U, // VPSHLDVQZ128mkz + 0U, // VPSHLDVQZ128r + 0U, // VPSHLDVQZ128rk + 0U, // VPSHLDVQZ128rkz + 0U, // VPSHLDVQZ256m + 0U, // VPSHLDVQZ256mb + 0U, // VPSHLDVQZ256mbk + 0U, // VPSHLDVQZ256mbkz + 0U, // VPSHLDVQZ256mk + 0U, // VPSHLDVQZ256mkz + 0U, // VPSHLDVQZ256r + 0U, // VPSHLDVQZ256rk + 0U, // VPSHLDVQZ256rkz + 0U, // VPSHLDVQZm + 0U, // VPSHLDVQZmb + 0U, // VPSHLDVQZmbk + 0U, // VPSHLDVQZmbkz + 0U, // VPSHLDVQZmk + 0U, // VPSHLDVQZmkz + 0U, // VPSHLDVQZr + 0U, // VPSHLDVQZrk + 0U, // VPSHLDVQZrkz + 0U, // VPSHLDVWZ128m + 0U, // VPSHLDVWZ128mk + 0U, // VPSHLDVWZ128mkz + 0U, // VPSHLDVWZ128r + 0U, // VPSHLDVWZ128rk + 0U, // VPSHLDVWZ128rkz + 0U, // VPSHLDVWZ256m + 0U, // VPSHLDVWZ256mk + 0U, // VPSHLDVWZ256mkz + 0U, // VPSHLDVWZ256r + 0U, // VPSHLDVWZ256rk + 0U, // VPSHLDVWZ256rkz + 0U, // VPSHLDVWZm + 0U, // VPSHLDVWZmk + 0U, // VPSHLDVWZmkz + 0U, // VPSHLDVWZr + 0U, // VPSHLDVWZrk + 0U, // VPSHLDVWZrkz + 0U, // VPSHLDWZ128rmi + 0U, // VPSHLDWZ128rmik + 0U, // VPSHLDWZ128rmikz + 0U, // VPSHLDWZ128rri + 0U, // VPSHLDWZ128rrik + 3U, // VPSHLDWZ128rrikz + 0U, // VPSHLDWZ256rmi + 0U, // VPSHLDWZ256rmik + 0U, // VPSHLDWZ256rmikz + 0U, // VPSHLDWZ256rri + 0U, // VPSHLDWZ256rrik + 3U, // VPSHLDWZ256rrikz + 0U, // VPSHLDWZrmi + 0U, // VPSHLDWZrmik + 0U, // VPSHLDWZrmikz + 0U, // VPSHLDWZrri + 0U, // VPSHLDWZrrik + 3U, // VPSHLDWZrrikz + 0U, // VPSHLDmr + 0U, // VPSHLDrm + 0U, // VPSHLDrr + 0U, // VPSHLDrr_REV + 0U, // VPSHLQmr + 0U, // VPSHLQrm + 0U, // VPSHLQrr + 0U, // VPSHLQrr_REV + 0U, // VPSHLWmr + 0U, // VPSHLWrm + 0U, // VPSHLWrr + 0U, // VPSHLWrr_REV + 0U, // VPSHRDDZ128rmbi + 0U, // VPSHRDDZ128rmbik + 3U, // VPSHRDDZ128rmbikz + 0U, // VPSHRDDZ128rmi + 0U, // VPSHRDDZ128rmik + 0U, // VPSHRDDZ128rmikz + 0U, // VPSHRDDZ128rri + 0U, // VPSHRDDZ128rrik + 3U, // VPSHRDDZ128rrikz + 0U, // VPSHRDDZ256rmbi + 0U, // VPSHRDDZ256rmbik + 3U, // VPSHRDDZ256rmbikz + 0U, // VPSHRDDZ256rmi + 0U, // VPSHRDDZ256rmik + 0U, // VPSHRDDZ256rmikz + 0U, // VPSHRDDZ256rri + 0U, // VPSHRDDZ256rrik + 3U, // VPSHRDDZ256rrikz + 0U, // VPSHRDDZrmbi + 0U, // VPSHRDDZrmbik + 3U, // VPSHRDDZrmbikz + 0U, // VPSHRDDZrmi + 0U, // VPSHRDDZrmik + 0U, // VPSHRDDZrmikz + 0U, // VPSHRDDZrri + 0U, // VPSHRDDZrrik + 3U, // VPSHRDDZrrikz + 0U, // VPSHRDQZ128rmbi + 0U, // VPSHRDQZ128rmbik + 3U, // VPSHRDQZ128rmbikz + 0U, // VPSHRDQZ128rmi + 0U, // VPSHRDQZ128rmik + 0U, // VPSHRDQZ128rmikz + 0U, // VPSHRDQZ128rri + 0U, // VPSHRDQZ128rrik + 3U, // VPSHRDQZ128rrikz + 0U, // VPSHRDQZ256rmbi + 0U, // VPSHRDQZ256rmbik + 3U, // VPSHRDQZ256rmbikz + 0U, // VPSHRDQZ256rmi + 0U, // VPSHRDQZ256rmik + 0U, // VPSHRDQZ256rmikz + 0U, // VPSHRDQZ256rri + 0U, // VPSHRDQZ256rrik + 3U, // VPSHRDQZ256rrikz + 0U, // VPSHRDQZrmbi + 0U, // VPSHRDQZrmbik + 3U, // VPSHRDQZrmbikz + 0U, // VPSHRDQZrmi + 0U, // VPSHRDQZrmik + 0U, // VPSHRDQZrmikz + 0U, // VPSHRDQZrri + 0U, // VPSHRDQZrrik + 3U, // VPSHRDQZrrikz + 0U, // VPSHRDVDZ128m + 0U, // VPSHRDVDZ128mb + 0U, // VPSHRDVDZ128mbk + 0U, // VPSHRDVDZ128mbkz + 0U, // VPSHRDVDZ128mk + 0U, // VPSHRDVDZ128mkz + 0U, // VPSHRDVDZ128r + 0U, // VPSHRDVDZ128rk + 0U, // VPSHRDVDZ128rkz + 0U, // VPSHRDVDZ256m + 0U, // VPSHRDVDZ256mb + 0U, // VPSHRDVDZ256mbk + 0U, // VPSHRDVDZ256mbkz + 0U, // VPSHRDVDZ256mk + 0U, // VPSHRDVDZ256mkz + 0U, // VPSHRDVDZ256r + 0U, // VPSHRDVDZ256rk + 0U, // VPSHRDVDZ256rkz + 0U, // VPSHRDVDZm + 0U, // VPSHRDVDZmb + 0U, // VPSHRDVDZmbk + 0U, // VPSHRDVDZmbkz + 0U, // VPSHRDVDZmk + 0U, // VPSHRDVDZmkz + 0U, // VPSHRDVDZr + 0U, // VPSHRDVDZrk + 0U, // VPSHRDVDZrkz + 0U, // VPSHRDVQZ128m + 0U, // VPSHRDVQZ128mb + 0U, // VPSHRDVQZ128mbk + 0U, // VPSHRDVQZ128mbkz + 0U, // VPSHRDVQZ128mk + 0U, // VPSHRDVQZ128mkz + 0U, // VPSHRDVQZ128r + 0U, // VPSHRDVQZ128rk + 0U, // VPSHRDVQZ128rkz + 0U, // VPSHRDVQZ256m + 0U, // VPSHRDVQZ256mb + 0U, // VPSHRDVQZ256mbk + 0U, // VPSHRDVQZ256mbkz + 0U, // VPSHRDVQZ256mk + 0U, // VPSHRDVQZ256mkz + 0U, // VPSHRDVQZ256r + 0U, // VPSHRDVQZ256rk + 0U, // VPSHRDVQZ256rkz + 0U, // VPSHRDVQZm + 0U, // VPSHRDVQZmb + 0U, // VPSHRDVQZmbk + 0U, // VPSHRDVQZmbkz + 0U, // VPSHRDVQZmk + 0U, // VPSHRDVQZmkz + 0U, // VPSHRDVQZr + 0U, // VPSHRDVQZrk + 0U, // VPSHRDVQZrkz + 0U, // VPSHRDVWZ128m + 0U, // VPSHRDVWZ128mk + 0U, // VPSHRDVWZ128mkz + 0U, // VPSHRDVWZ128r + 0U, // VPSHRDVWZ128rk + 0U, // VPSHRDVWZ128rkz + 0U, // VPSHRDVWZ256m + 0U, // VPSHRDVWZ256mk + 0U, // VPSHRDVWZ256mkz + 0U, // VPSHRDVWZ256r + 0U, // VPSHRDVWZ256rk + 0U, // VPSHRDVWZ256rkz + 0U, // VPSHRDVWZm + 0U, // VPSHRDVWZmk + 0U, // VPSHRDVWZmkz + 0U, // VPSHRDVWZr + 0U, // VPSHRDVWZrk + 0U, // VPSHRDVWZrkz + 0U, // VPSHRDWZ128rmi + 0U, // VPSHRDWZ128rmik + 0U, // VPSHRDWZ128rmikz + 0U, // VPSHRDWZ128rri + 0U, // VPSHRDWZ128rrik + 3U, // VPSHRDWZ128rrikz + 0U, // VPSHRDWZ256rmi + 0U, // VPSHRDWZ256rmik + 0U, // VPSHRDWZ256rmikz + 0U, // VPSHRDWZ256rri + 0U, // VPSHRDWZ256rrik + 3U, // VPSHRDWZ256rrikz + 0U, // VPSHRDWZrmi + 0U, // VPSHRDWZrmik + 0U, // VPSHRDWZrmikz + 0U, // VPSHRDWZrri + 0U, // VPSHRDWZrrik + 3U, // VPSHRDWZrrikz + 0U, // VPSHUFBITQMBZ128rm + 0U, // VPSHUFBITQMBZ128rmk + 0U, // VPSHUFBITQMBZ128rr + 0U, // VPSHUFBITQMBZ128rrk + 0U, // VPSHUFBITQMBZ256rm + 0U, // VPSHUFBITQMBZ256rmk + 0U, // VPSHUFBITQMBZ256rr + 0U, // VPSHUFBITQMBZ256rrk + 0U, // VPSHUFBITQMBZrm + 0U, // VPSHUFBITQMBZrmk + 0U, // VPSHUFBITQMBZrr + 0U, // VPSHUFBITQMBZrrk + 0U, // VPSHUFBYrm + 0U, // VPSHUFBYrr + 0U, // VPSHUFBZ128rm + 0U, // VPSHUFBZ128rmk + 0U, // VPSHUFBZ128rmkz + 0U, // VPSHUFBZ128rr + 0U, // VPSHUFBZ128rrk + 0U, // VPSHUFBZ128rrkz + 0U, // VPSHUFBZ256rm + 0U, // VPSHUFBZ256rmk + 0U, // VPSHUFBZ256rmkz + 0U, // VPSHUFBZ256rr + 0U, // VPSHUFBZ256rrk + 0U, // VPSHUFBZ256rrkz + 0U, // VPSHUFBZrm + 0U, // VPSHUFBZrmk + 0U, // VPSHUFBZrmkz + 0U, // VPSHUFBZrr + 0U, // VPSHUFBZrrk + 0U, // VPSHUFBZrrkz + 0U, // VPSHUFBrm + 0U, // VPSHUFBrr + 0U, // VPSHUFDYmi + 0U, // VPSHUFDYri + 0U, // VPSHUFDZ128mbi + 0U, // VPSHUFDZ128mbik + 0U, // VPSHUFDZ128mbikz + 0U, // VPSHUFDZ128mi + 0U, // VPSHUFDZ128mik + 0U, // VPSHUFDZ128mikz + 0U, // VPSHUFDZ128ri + 0U, // VPSHUFDZ128rik + 0U, // VPSHUFDZ128rikz + 0U, // VPSHUFDZ256mbi + 0U, // VPSHUFDZ256mbik + 0U, // VPSHUFDZ256mbikz + 0U, // VPSHUFDZ256mi + 0U, // VPSHUFDZ256mik + 0U, // VPSHUFDZ256mikz + 0U, // VPSHUFDZ256ri + 0U, // VPSHUFDZ256rik + 0U, // VPSHUFDZ256rikz + 0U, // VPSHUFDZmbi + 0U, // VPSHUFDZmbik + 0U, // VPSHUFDZmbikz + 0U, // VPSHUFDZmi + 0U, // VPSHUFDZmik + 0U, // VPSHUFDZmikz + 0U, // VPSHUFDZri + 0U, // VPSHUFDZrik + 0U, // VPSHUFDZrikz + 0U, // VPSHUFDmi + 0U, // VPSHUFDri + 0U, // VPSHUFHWYmi + 0U, // VPSHUFHWYri + 0U, // VPSHUFHWZ128mi + 0U, // VPSHUFHWZ128mik + 0U, // VPSHUFHWZ128mikz + 0U, // VPSHUFHWZ128ri + 0U, // VPSHUFHWZ128rik + 0U, // VPSHUFHWZ128rikz + 0U, // VPSHUFHWZ256mi + 0U, // VPSHUFHWZ256mik + 0U, // VPSHUFHWZ256mikz + 0U, // VPSHUFHWZ256ri + 0U, // VPSHUFHWZ256rik + 0U, // VPSHUFHWZ256rikz + 0U, // VPSHUFHWZmi + 0U, // VPSHUFHWZmik + 0U, // VPSHUFHWZmikz + 0U, // VPSHUFHWZri + 0U, // VPSHUFHWZrik + 0U, // VPSHUFHWZrikz + 0U, // VPSHUFHWmi + 0U, // VPSHUFHWri + 0U, // VPSHUFLWYmi + 0U, // VPSHUFLWYri + 0U, // VPSHUFLWZ128mi + 0U, // VPSHUFLWZ128mik + 0U, // VPSHUFLWZ128mikz + 0U, // VPSHUFLWZ128ri + 0U, // VPSHUFLWZ128rik + 0U, // VPSHUFLWZ128rikz + 0U, // VPSHUFLWZ256mi + 0U, // VPSHUFLWZ256mik + 0U, // VPSHUFLWZ256mikz + 0U, // VPSHUFLWZ256ri + 0U, // VPSHUFLWZ256rik + 0U, // VPSHUFLWZ256rikz + 0U, // VPSHUFLWZmi + 0U, // VPSHUFLWZmik + 0U, // VPSHUFLWZmikz + 0U, // VPSHUFLWZri + 0U, // VPSHUFLWZrik + 0U, // VPSHUFLWZrikz + 0U, // VPSHUFLWmi + 0U, // VPSHUFLWri + 0U, // VPSIGNBYrm + 0U, // VPSIGNBYrr + 0U, // VPSIGNBrm + 0U, // VPSIGNBrr + 0U, // VPSIGNDYrm + 0U, // VPSIGNDYrr + 0U, // VPSIGNDrm + 0U, // VPSIGNDrr + 0U, // VPSIGNWYrm + 0U, // VPSIGNWYrr + 0U, // VPSIGNWrm + 0U, // VPSIGNWrr + 0U, // VPSLLDQYri + 0U, // VPSLLDQZ128rm + 0U, // VPSLLDQZ128rr + 0U, // VPSLLDQZ256rm + 0U, // VPSLLDQZ256rr + 0U, // VPSLLDQZrm + 0U, // VPSLLDQZrr + 0U, // VPSLLDQri + 0U, // VPSLLDYri + 0U, // VPSLLDYrm + 0U, // VPSLLDYrr + 0U, // VPSLLDZ128mbi + 0U, // VPSLLDZ128mbik + 0U, // VPSLLDZ128mbikz + 0U, // VPSLLDZ128mi + 0U, // VPSLLDZ128mik + 0U, // VPSLLDZ128mikz + 0U, // VPSLLDZ128ri + 0U, // VPSLLDZ128rik + 0U, // VPSLLDZ128rikz + 0U, // VPSLLDZ128rm + 0U, // VPSLLDZ128rmk + 0U, // VPSLLDZ128rmkz + 0U, // VPSLLDZ128rr + 0U, // VPSLLDZ128rrk + 0U, // VPSLLDZ128rrkz + 0U, // VPSLLDZ256mbi + 0U, // VPSLLDZ256mbik + 0U, // VPSLLDZ256mbikz + 0U, // VPSLLDZ256mi + 0U, // VPSLLDZ256mik + 0U, // VPSLLDZ256mikz + 0U, // VPSLLDZ256ri + 0U, // VPSLLDZ256rik + 0U, // VPSLLDZ256rikz + 0U, // VPSLLDZ256rm + 0U, // VPSLLDZ256rmk + 0U, // VPSLLDZ256rmkz + 0U, // VPSLLDZ256rr + 0U, // VPSLLDZ256rrk + 0U, // VPSLLDZ256rrkz + 0U, // VPSLLDZmbi + 0U, // VPSLLDZmbik + 0U, // VPSLLDZmbikz + 0U, // VPSLLDZmi + 0U, // VPSLLDZmik + 0U, // VPSLLDZmikz + 0U, // VPSLLDZri + 0U, // VPSLLDZrik + 0U, // VPSLLDZrikz + 0U, // VPSLLDZrm + 0U, // VPSLLDZrmk + 0U, // VPSLLDZrmkz + 0U, // VPSLLDZrr + 0U, // VPSLLDZrrk + 0U, // VPSLLDZrrkz + 0U, // VPSLLDri + 0U, // VPSLLDrm + 0U, // VPSLLDrr + 0U, // VPSLLQYri + 0U, // VPSLLQYrm + 0U, // VPSLLQYrr + 0U, // VPSLLQZ128mbi + 0U, // VPSLLQZ128mbik + 0U, // VPSLLQZ128mbikz + 0U, // VPSLLQZ128mi + 0U, // VPSLLQZ128mik + 0U, // VPSLLQZ128mikz + 0U, // VPSLLQZ128ri + 0U, // VPSLLQZ128rik + 0U, // VPSLLQZ128rikz + 0U, // VPSLLQZ128rm + 0U, // VPSLLQZ128rmk + 0U, // VPSLLQZ128rmkz + 0U, // VPSLLQZ128rr + 0U, // VPSLLQZ128rrk + 0U, // VPSLLQZ128rrkz + 0U, // VPSLLQZ256mbi + 0U, // VPSLLQZ256mbik + 0U, // VPSLLQZ256mbikz + 0U, // VPSLLQZ256mi + 0U, // VPSLLQZ256mik + 0U, // VPSLLQZ256mikz + 0U, // VPSLLQZ256ri + 0U, // VPSLLQZ256rik + 0U, // VPSLLQZ256rikz + 0U, // VPSLLQZ256rm + 0U, // VPSLLQZ256rmk + 0U, // VPSLLQZ256rmkz + 0U, // VPSLLQZ256rr + 0U, // VPSLLQZ256rrk + 0U, // VPSLLQZ256rrkz + 0U, // VPSLLQZmbi + 0U, // VPSLLQZmbik + 0U, // VPSLLQZmbikz + 0U, // VPSLLQZmi + 0U, // VPSLLQZmik + 0U, // VPSLLQZmikz + 0U, // VPSLLQZri + 0U, // VPSLLQZrik + 0U, // VPSLLQZrikz + 0U, // VPSLLQZrm + 0U, // VPSLLQZrmk + 0U, // VPSLLQZrmkz + 0U, // VPSLLQZrr + 0U, // VPSLLQZrrk + 0U, // VPSLLQZrrkz + 0U, // VPSLLQri + 0U, // VPSLLQrm + 0U, // VPSLLQrr + 0U, // VPSLLVDYrm + 0U, // VPSLLVDYrr + 0U, // VPSLLVDZ128rm + 0U, // VPSLLVDZ128rmb + 0U, // VPSLLVDZ128rmbk + 0U, // VPSLLVDZ128rmbkz + 0U, // VPSLLVDZ128rmk + 0U, // VPSLLVDZ128rmkz + 0U, // VPSLLVDZ128rr + 0U, // VPSLLVDZ128rrk + 0U, // VPSLLVDZ128rrkz + 0U, // VPSLLVDZ256rm + 0U, // VPSLLVDZ256rmb + 0U, // VPSLLVDZ256rmbk + 0U, // VPSLLVDZ256rmbkz + 0U, // VPSLLVDZ256rmk + 0U, // VPSLLVDZ256rmkz + 0U, // VPSLLVDZ256rr + 0U, // VPSLLVDZ256rrk + 0U, // VPSLLVDZ256rrkz + 0U, // VPSLLVDZrm + 0U, // VPSLLVDZrmb + 0U, // VPSLLVDZrmbk + 0U, // VPSLLVDZrmbkz + 0U, // VPSLLVDZrmk + 0U, // VPSLLVDZrmkz + 0U, // VPSLLVDZrr + 0U, // VPSLLVDZrrk + 0U, // VPSLLVDZrrkz + 0U, // VPSLLVDrm + 0U, // VPSLLVDrr + 0U, // VPSLLVQYrm + 0U, // VPSLLVQYrr + 0U, // VPSLLVQZ128rm + 0U, // VPSLLVQZ128rmb + 0U, // VPSLLVQZ128rmbk + 0U, // VPSLLVQZ128rmbkz + 0U, // VPSLLVQZ128rmk + 0U, // VPSLLVQZ128rmkz + 0U, // VPSLLVQZ128rr + 0U, // VPSLLVQZ128rrk + 0U, // VPSLLVQZ128rrkz + 0U, // VPSLLVQZ256rm + 0U, // VPSLLVQZ256rmb + 0U, // VPSLLVQZ256rmbk + 0U, // VPSLLVQZ256rmbkz + 0U, // VPSLLVQZ256rmk + 0U, // VPSLLVQZ256rmkz + 0U, // VPSLLVQZ256rr + 0U, // VPSLLVQZ256rrk + 0U, // VPSLLVQZ256rrkz + 0U, // VPSLLVQZrm + 0U, // VPSLLVQZrmb + 0U, // VPSLLVQZrmbk + 0U, // VPSLLVQZrmbkz + 0U, // VPSLLVQZrmk + 0U, // VPSLLVQZrmkz + 0U, // VPSLLVQZrr + 0U, // VPSLLVQZrrk + 0U, // VPSLLVQZrrkz + 0U, // VPSLLVQrm + 0U, // VPSLLVQrr + 0U, // VPSLLVWZ128rm + 0U, // VPSLLVWZ128rmk + 0U, // VPSLLVWZ128rmkz + 0U, // VPSLLVWZ128rr + 0U, // VPSLLVWZ128rrk + 0U, // VPSLLVWZ128rrkz + 0U, // VPSLLVWZ256rm + 0U, // VPSLLVWZ256rmk + 0U, // VPSLLVWZ256rmkz + 0U, // VPSLLVWZ256rr + 0U, // VPSLLVWZ256rrk + 0U, // VPSLLVWZ256rrkz + 0U, // VPSLLVWZrm + 0U, // VPSLLVWZrmk + 0U, // VPSLLVWZrmkz + 0U, // VPSLLVWZrr + 0U, // VPSLLVWZrrk + 0U, // VPSLLVWZrrkz + 0U, // VPSLLWYri + 0U, // VPSLLWYrm + 0U, // VPSLLWYrr + 0U, // VPSLLWZ128mi + 0U, // VPSLLWZ128mik + 0U, // VPSLLWZ128mikz + 0U, // VPSLLWZ128ri + 0U, // VPSLLWZ128rik + 0U, // VPSLLWZ128rikz + 0U, // VPSLLWZ128rm + 0U, // VPSLLWZ128rmk + 0U, // VPSLLWZ128rmkz + 0U, // VPSLLWZ128rr + 0U, // VPSLLWZ128rrk + 0U, // VPSLLWZ128rrkz + 0U, // VPSLLWZ256mi + 0U, // VPSLLWZ256mik + 0U, // VPSLLWZ256mikz + 0U, // VPSLLWZ256ri + 0U, // VPSLLWZ256rik + 0U, // VPSLLWZ256rikz + 0U, // VPSLLWZ256rm + 0U, // VPSLLWZ256rmk + 0U, // VPSLLWZ256rmkz + 0U, // VPSLLWZ256rr + 0U, // VPSLLWZ256rrk + 0U, // VPSLLWZ256rrkz + 0U, // VPSLLWZmi + 0U, // VPSLLWZmik + 0U, // VPSLLWZmikz + 0U, // VPSLLWZri + 0U, // VPSLLWZrik + 0U, // VPSLLWZrikz + 0U, // VPSLLWZrm + 0U, // VPSLLWZrmk + 0U, // VPSLLWZrmkz + 0U, // VPSLLWZrr + 0U, // VPSLLWZrrk + 0U, // VPSLLWZrrkz + 0U, // VPSLLWri + 0U, // VPSLLWrm + 0U, // VPSLLWrr + 0U, // VPSRADYri + 0U, // VPSRADYrm + 0U, // VPSRADYrr + 0U, // VPSRADZ128mbi + 0U, // VPSRADZ128mbik + 0U, // VPSRADZ128mbikz + 0U, // VPSRADZ128mi + 0U, // VPSRADZ128mik + 0U, // VPSRADZ128mikz + 0U, // VPSRADZ128ri + 0U, // VPSRADZ128rik + 0U, // VPSRADZ128rikz + 0U, // VPSRADZ128rm + 0U, // VPSRADZ128rmk + 0U, // VPSRADZ128rmkz + 0U, // VPSRADZ128rr + 0U, // VPSRADZ128rrk + 0U, // VPSRADZ128rrkz + 0U, // VPSRADZ256mbi + 0U, // VPSRADZ256mbik + 0U, // VPSRADZ256mbikz + 0U, // VPSRADZ256mi + 0U, // VPSRADZ256mik + 0U, // VPSRADZ256mikz + 0U, // VPSRADZ256ri + 0U, // VPSRADZ256rik + 0U, // VPSRADZ256rikz + 0U, // VPSRADZ256rm + 0U, // VPSRADZ256rmk + 0U, // VPSRADZ256rmkz + 0U, // VPSRADZ256rr + 0U, // VPSRADZ256rrk + 0U, // VPSRADZ256rrkz + 0U, // VPSRADZmbi + 0U, // VPSRADZmbik + 0U, // VPSRADZmbikz + 0U, // VPSRADZmi + 0U, // VPSRADZmik + 0U, // VPSRADZmikz + 0U, // VPSRADZri + 0U, // VPSRADZrik + 0U, // VPSRADZrikz + 0U, // VPSRADZrm + 0U, // VPSRADZrmk + 0U, // VPSRADZrmkz + 0U, // VPSRADZrr + 0U, // VPSRADZrrk + 0U, // VPSRADZrrkz + 0U, // VPSRADri + 0U, // VPSRADrm + 0U, // VPSRADrr + 0U, // VPSRAQZ128mbi + 0U, // VPSRAQZ128mbik + 0U, // VPSRAQZ128mbikz + 0U, // VPSRAQZ128mi + 0U, // VPSRAQZ128mik + 0U, // VPSRAQZ128mikz + 0U, // VPSRAQZ128ri + 0U, // VPSRAQZ128rik + 0U, // VPSRAQZ128rikz + 0U, // VPSRAQZ128rm + 0U, // VPSRAQZ128rmk + 0U, // VPSRAQZ128rmkz + 0U, // VPSRAQZ128rr + 0U, // VPSRAQZ128rrk + 0U, // VPSRAQZ128rrkz + 0U, // VPSRAQZ256mbi + 0U, // VPSRAQZ256mbik + 0U, // VPSRAQZ256mbikz + 0U, // VPSRAQZ256mi + 0U, // VPSRAQZ256mik + 0U, // VPSRAQZ256mikz + 0U, // VPSRAQZ256ri + 0U, // VPSRAQZ256rik + 0U, // VPSRAQZ256rikz + 0U, // VPSRAQZ256rm + 0U, // VPSRAQZ256rmk + 0U, // VPSRAQZ256rmkz + 0U, // VPSRAQZ256rr + 0U, // VPSRAQZ256rrk + 0U, // VPSRAQZ256rrkz + 0U, // VPSRAQZmbi + 0U, // VPSRAQZmbik + 0U, // VPSRAQZmbikz + 0U, // VPSRAQZmi + 0U, // VPSRAQZmik + 0U, // VPSRAQZmikz + 0U, // VPSRAQZri + 0U, // VPSRAQZrik + 0U, // VPSRAQZrikz + 0U, // VPSRAQZrm + 0U, // VPSRAQZrmk + 0U, // VPSRAQZrmkz + 0U, // VPSRAQZrr + 0U, // VPSRAQZrrk + 0U, // VPSRAQZrrkz + 0U, // VPSRAVDYrm + 0U, // VPSRAVDYrr + 0U, // VPSRAVDZ128rm + 0U, // VPSRAVDZ128rmb + 0U, // VPSRAVDZ128rmbk + 0U, // VPSRAVDZ128rmbkz + 0U, // VPSRAVDZ128rmk + 0U, // VPSRAVDZ128rmkz + 0U, // VPSRAVDZ128rr + 0U, // VPSRAVDZ128rrk + 0U, // VPSRAVDZ128rrkz + 0U, // VPSRAVDZ256rm + 0U, // VPSRAVDZ256rmb + 0U, // VPSRAVDZ256rmbk + 0U, // VPSRAVDZ256rmbkz + 0U, // VPSRAVDZ256rmk + 0U, // VPSRAVDZ256rmkz + 0U, // VPSRAVDZ256rr + 0U, // VPSRAVDZ256rrk + 0U, // VPSRAVDZ256rrkz + 0U, // VPSRAVDZrm + 0U, // VPSRAVDZrmb + 0U, // VPSRAVDZrmbk + 0U, // VPSRAVDZrmbkz + 0U, // VPSRAVDZrmk + 0U, // VPSRAVDZrmkz + 0U, // VPSRAVDZrr + 0U, // VPSRAVDZrrk + 0U, // VPSRAVDZrrkz + 0U, // VPSRAVDrm + 0U, // VPSRAVDrr + 0U, // VPSRAVQZ128rm + 0U, // VPSRAVQZ128rmb + 0U, // VPSRAVQZ128rmbk + 0U, // VPSRAVQZ128rmbkz + 0U, // VPSRAVQZ128rmk + 0U, // VPSRAVQZ128rmkz + 0U, // VPSRAVQZ128rr + 0U, // VPSRAVQZ128rrk + 0U, // VPSRAVQZ128rrkz + 0U, // VPSRAVQZ256rm + 0U, // VPSRAVQZ256rmb + 0U, // VPSRAVQZ256rmbk + 0U, // VPSRAVQZ256rmbkz + 0U, // VPSRAVQZ256rmk + 0U, // VPSRAVQZ256rmkz + 0U, // VPSRAVQZ256rr + 0U, // VPSRAVQZ256rrk + 0U, // VPSRAVQZ256rrkz + 0U, // VPSRAVQZrm + 0U, // VPSRAVQZrmb + 0U, // VPSRAVQZrmbk + 0U, // VPSRAVQZrmbkz + 0U, // VPSRAVQZrmk + 0U, // VPSRAVQZrmkz + 0U, // VPSRAVQZrr + 0U, // VPSRAVQZrrk + 0U, // VPSRAVQZrrkz + 0U, // VPSRAVWZ128rm + 0U, // VPSRAVWZ128rmk + 0U, // VPSRAVWZ128rmkz + 0U, // VPSRAVWZ128rr + 0U, // VPSRAVWZ128rrk + 0U, // VPSRAVWZ128rrkz + 0U, // VPSRAVWZ256rm + 0U, // VPSRAVWZ256rmk + 0U, // VPSRAVWZ256rmkz + 0U, // VPSRAVWZ256rr + 0U, // VPSRAVWZ256rrk + 0U, // VPSRAVWZ256rrkz + 0U, // VPSRAVWZrm + 0U, // VPSRAVWZrmk + 0U, // VPSRAVWZrmkz + 0U, // VPSRAVWZrr + 0U, // VPSRAVWZrrk + 0U, // VPSRAVWZrrkz + 0U, // VPSRAWYri + 0U, // VPSRAWYrm + 0U, // VPSRAWYrr + 0U, // VPSRAWZ128mi + 0U, // VPSRAWZ128mik + 0U, // VPSRAWZ128mikz + 0U, // VPSRAWZ128ri + 0U, // VPSRAWZ128rik + 0U, // VPSRAWZ128rikz + 0U, // VPSRAWZ128rm + 0U, // VPSRAWZ128rmk + 0U, // VPSRAWZ128rmkz + 0U, // VPSRAWZ128rr + 0U, // VPSRAWZ128rrk + 0U, // VPSRAWZ128rrkz + 0U, // VPSRAWZ256mi + 0U, // VPSRAWZ256mik + 0U, // VPSRAWZ256mikz + 0U, // VPSRAWZ256ri + 0U, // VPSRAWZ256rik + 0U, // VPSRAWZ256rikz + 0U, // VPSRAWZ256rm + 0U, // VPSRAWZ256rmk + 0U, // VPSRAWZ256rmkz + 0U, // VPSRAWZ256rr + 0U, // VPSRAWZ256rrk + 0U, // VPSRAWZ256rrkz + 0U, // VPSRAWZmi + 0U, // VPSRAWZmik + 0U, // VPSRAWZmikz + 0U, // VPSRAWZri + 0U, // VPSRAWZrik + 0U, // VPSRAWZrikz + 0U, // VPSRAWZrm + 0U, // VPSRAWZrmk + 0U, // VPSRAWZrmkz + 0U, // VPSRAWZrr + 0U, // VPSRAWZrrk + 0U, // VPSRAWZrrkz + 0U, // VPSRAWri + 0U, // VPSRAWrm + 0U, // VPSRAWrr + 0U, // VPSRLDQYri + 0U, // VPSRLDQZ128rm + 0U, // VPSRLDQZ128rr + 0U, // VPSRLDQZ256rm + 0U, // VPSRLDQZ256rr + 0U, // VPSRLDQZrm + 0U, // VPSRLDQZrr + 0U, // VPSRLDQri + 0U, // VPSRLDYri + 0U, // VPSRLDYrm + 0U, // VPSRLDYrr + 0U, // VPSRLDZ128mbi + 0U, // VPSRLDZ128mbik + 0U, // VPSRLDZ128mbikz + 0U, // VPSRLDZ128mi + 0U, // VPSRLDZ128mik + 0U, // VPSRLDZ128mikz + 0U, // VPSRLDZ128ri + 0U, // VPSRLDZ128rik + 0U, // VPSRLDZ128rikz + 0U, // VPSRLDZ128rm + 0U, // VPSRLDZ128rmk + 0U, // VPSRLDZ128rmkz + 0U, // VPSRLDZ128rr + 0U, // VPSRLDZ128rrk + 0U, // VPSRLDZ128rrkz + 0U, // VPSRLDZ256mbi + 0U, // VPSRLDZ256mbik + 0U, // VPSRLDZ256mbikz + 0U, // VPSRLDZ256mi + 0U, // VPSRLDZ256mik + 0U, // VPSRLDZ256mikz + 0U, // VPSRLDZ256ri + 0U, // VPSRLDZ256rik + 0U, // VPSRLDZ256rikz + 0U, // VPSRLDZ256rm + 0U, // VPSRLDZ256rmk + 0U, // VPSRLDZ256rmkz + 0U, // VPSRLDZ256rr + 0U, // VPSRLDZ256rrk + 0U, // VPSRLDZ256rrkz + 0U, // VPSRLDZmbi + 0U, // VPSRLDZmbik + 0U, // VPSRLDZmbikz + 0U, // VPSRLDZmi + 0U, // VPSRLDZmik + 0U, // VPSRLDZmikz + 0U, // VPSRLDZri + 0U, // VPSRLDZrik + 0U, // VPSRLDZrikz + 0U, // VPSRLDZrm + 0U, // VPSRLDZrmk + 0U, // VPSRLDZrmkz + 0U, // VPSRLDZrr + 0U, // VPSRLDZrrk + 0U, // VPSRLDZrrkz + 0U, // VPSRLDri + 0U, // VPSRLDrm + 0U, // VPSRLDrr + 0U, // VPSRLQYri + 0U, // VPSRLQYrm + 0U, // VPSRLQYrr + 0U, // VPSRLQZ128mbi + 0U, // VPSRLQZ128mbik + 0U, // VPSRLQZ128mbikz + 0U, // VPSRLQZ128mi + 0U, // VPSRLQZ128mik + 0U, // VPSRLQZ128mikz + 0U, // VPSRLQZ128ri + 0U, // VPSRLQZ128rik + 0U, // VPSRLQZ128rikz + 0U, // VPSRLQZ128rm + 0U, // VPSRLQZ128rmk + 0U, // VPSRLQZ128rmkz + 0U, // VPSRLQZ128rr + 0U, // VPSRLQZ128rrk + 0U, // VPSRLQZ128rrkz + 0U, // VPSRLQZ256mbi + 0U, // VPSRLQZ256mbik + 0U, // VPSRLQZ256mbikz + 0U, // VPSRLQZ256mi + 0U, // VPSRLQZ256mik + 0U, // VPSRLQZ256mikz + 0U, // VPSRLQZ256ri + 0U, // VPSRLQZ256rik + 0U, // VPSRLQZ256rikz + 0U, // VPSRLQZ256rm + 0U, // VPSRLQZ256rmk + 0U, // VPSRLQZ256rmkz + 0U, // VPSRLQZ256rr + 0U, // VPSRLQZ256rrk + 0U, // VPSRLQZ256rrkz + 0U, // VPSRLQZmbi + 0U, // VPSRLQZmbik + 0U, // VPSRLQZmbikz + 0U, // VPSRLQZmi + 0U, // VPSRLQZmik + 0U, // VPSRLQZmikz + 0U, // VPSRLQZri + 0U, // VPSRLQZrik + 0U, // VPSRLQZrikz + 0U, // VPSRLQZrm + 0U, // VPSRLQZrmk + 0U, // VPSRLQZrmkz + 0U, // VPSRLQZrr + 0U, // VPSRLQZrrk + 0U, // VPSRLQZrrkz + 0U, // VPSRLQri + 0U, // VPSRLQrm + 0U, // VPSRLQrr + 0U, // VPSRLVDYrm + 0U, // VPSRLVDYrr + 0U, // VPSRLVDZ128rm + 0U, // VPSRLVDZ128rmb + 0U, // VPSRLVDZ128rmbk + 0U, // VPSRLVDZ128rmbkz + 0U, // VPSRLVDZ128rmk + 0U, // VPSRLVDZ128rmkz + 0U, // VPSRLVDZ128rr + 0U, // VPSRLVDZ128rrk + 0U, // VPSRLVDZ128rrkz + 0U, // VPSRLVDZ256rm + 0U, // VPSRLVDZ256rmb + 0U, // VPSRLVDZ256rmbk + 0U, // VPSRLVDZ256rmbkz + 0U, // VPSRLVDZ256rmk + 0U, // VPSRLVDZ256rmkz + 0U, // VPSRLVDZ256rr + 0U, // VPSRLVDZ256rrk + 0U, // VPSRLVDZ256rrkz + 0U, // VPSRLVDZrm + 0U, // VPSRLVDZrmb + 0U, // VPSRLVDZrmbk + 0U, // VPSRLVDZrmbkz + 0U, // VPSRLVDZrmk + 0U, // VPSRLVDZrmkz + 0U, // VPSRLVDZrr + 0U, // VPSRLVDZrrk + 0U, // VPSRLVDZrrkz + 0U, // VPSRLVDrm + 0U, // VPSRLVDrr + 0U, // VPSRLVQYrm + 0U, // VPSRLVQYrr + 0U, // VPSRLVQZ128rm + 0U, // VPSRLVQZ128rmb + 0U, // VPSRLVQZ128rmbk + 0U, // VPSRLVQZ128rmbkz + 0U, // VPSRLVQZ128rmk + 0U, // VPSRLVQZ128rmkz + 0U, // VPSRLVQZ128rr + 0U, // VPSRLVQZ128rrk + 0U, // VPSRLVQZ128rrkz + 0U, // VPSRLVQZ256rm + 0U, // VPSRLVQZ256rmb + 0U, // VPSRLVQZ256rmbk + 0U, // VPSRLVQZ256rmbkz + 0U, // VPSRLVQZ256rmk + 0U, // VPSRLVQZ256rmkz + 0U, // VPSRLVQZ256rr + 0U, // VPSRLVQZ256rrk + 0U, // VPSRLVQZ256rrkz + 0U, // VPSRLVQZrm + 0U, // VPSRLVQZrmb + 0U, // VPSRLVQZrmbk + 0U, // VPSRLVQZrmbkz + 0U, // VPSRLVQZrmk + 0U, // VPSRLVQZrmkz + 0U, // VPSRLVQZrr + 0U, // VPSRLVQZrrk + 0U, // VPSRLVQZrrkz + 0U, // VPSRLVQrm + 0U, // VPSRLVQrr + 0U, // VPSRLVWZ128rm + 0U, // VPSRLVWZ128rmk + 0U, // VPSRLVWZ128rmkz + 0U, // VPSRLVWZ128rr + 0U, // VPSRLVWZ128rrk + 0U, // VPSRLVWZ128rrkz + 0U, // VPSRLVWZ256rm + 0U, // VPSRLVWZ256rmk + 0U, // VPSRLVWZ256rmkz + 0U, // VPSRLVWZ256rr + 0U, // VPSRLVWZ256rrk + 0U, // VPSRLVWZ256rrkz + 0U, // VPSRLVWZrm + 0U, // VPSRLVWZrmk + 0U, // VPSRLVWZrmkz + 0U, // VPSRLVWZrr + 0U, // VPSRLVWZrrk + 0U, // VPSRLVWZrrkz + 0U, // VPSRLWYri + 0U, // VPSRLWYrm + 0U, // VPSRLWYrr + 0U, // VPSRLWZ128mi + 0U, // VPSRLWZ128mik + 0U, // VPSRLWZ128mikz + 0U, // VPSRLWZ128ri + 0U, // VPSRLWZ128rik + 0U, // VPSRLWZ128rikz + 0U, // VPSRLWZ128rm + 0U, // VPSRLWZ128rmk + 0U, // VPSRLWZ128rmkz + 0U, // VPSRLWZ128rr + 0U, // VPSRLWZ128rrk + 0U, // VPSRLWZ128rrkz + 0U, // VPSRLWZ256mi + 0U, // VPSRLWZ256mik + 0U, // VPSRLWZ256mikz + 0U, // VPSRLWZ256ri + 0U, // VPSRLWZ256rik + 0U, // VPSRLWZ256rikz + 0U, // VPSRLWZ256rm + 0U, // VPSRLWZ256rmk + 0U, // VPSRLWZ256rmkz + 0U, // VPSRLWZ256rr + 0U, // VPSRLWZ256rrk + 0U, // VPSRLWZ256rrkz + 0U, // VPSRLWZmi + 0U, // VPSRLWZmik + 0U, // VPSRLWZmikz + 0U, // VPSRLWZri + 0U, // VPSRLWZrik + 0U, // VPSRLWZrikz + 0U, // VPSRLWZrm + 0U, // VPSRLWZrmk + 0U, // VPSRLWZrmkz + 0U, // VPSRLWZrr + 0U, // VPSRLWZrrk + 0U, // VPSRLWZrrkz + 0U, // VPSRLWri + 0U, // VPSRLWrm + 0U, // VPSRLWrr + 0U, // VPSUBBYrm + 0U, // VPSUBBYrr + 0U, // VPSUBBZ128rm + 0U, // VPSUBBZ128rmk + 0U, // VPSUBBZ128rmkz + 0U, // VPSUBBZ128rr + 0U, // VPSUBBZ128rrk + 0U, // VPSUBBZ128rrkz + 0U, // VPSUBBZ256rm + 0U, // VPSUBBZ256rmk + 0U, // VPSUBBZ256rmkz + 0U, // VPSUBBZ256rr + 0U, // VPSUBBZ256rrk + 0U, // VPSUBBZ256rrkz + 0U, // VPSUBBZrm + 0U, // VPSUBBZrmk + 0U, // VPSUBBZrmkz + 0U, // VPSUBBZrr + 0U, // VPSUBBZrrk + 0U, // VPSUBBZrrkz + 0U, // VPSUBBrm + 0U, // VPSUBBrr + 0U, // VPSUBDYrm + 0U, // VPSUBDYrr + 0U, // VPSUBDZ128rm + 0U, // VPSUBDZ128rmb + 0U, // VPSUBDZ128rmbk + 0U, // VPSUBDZ128rmbkz + 0U, // VPSUBDZ128rmk + 0U, // VPSUBDZ128rmkz + 0U, // VPSUBDZ128rr + 0U, // VPSUBDZ128rrk + 0U, // VPSUBDZ128rrkz + 0U, // VPSUBDZ256rm + 0U, // VPSUBDZ256rmb + 0U, // VPSUBDZ256rmbk + 0U, // VPSUBDZ256rmbkz + 0U, // VPSUBDZ256rmk + 0U, // VPSUBDZ256rmkz + 0U, // VPSUBDZ256rr + 0U, // VPSUBDZ256rrk + 0U, // VPSUBDZ256rrkz + 0U, // VPSUBDZrm + 0U, // VPSUBDZrmb + 0U, // VPSUBDZrmbk + 0U, // VPSUBDZrmbkz + 0U, // VPSUBDZrmk + 0U, // VPSUBDZrmkz + 0U, // VPSUBDZrr + 0U, // VPSUBDZrrk + 0U, // VPSUBDZrrkz + 0U, // VPSUBDrm + 0U, // VPSUBDrr + 0U, // VPSUBQYrm + 0U, // VPSUBQYrr + 0U, // VPSUBQZ128rm + 0U, // VPSUBQZ128rmb + 0U, // VPSUBQZ128rmbk + 0U, // VPSUBQZ128rmbkz + 0U, // VPSUBQZ128rmk + 0U, // VPSUBQZ128rmkz + 0U, // VPSUBQZ128rr + 0U, // VPSUBQZ128rrk + 0U, // VPSUBQZ128rrkz + 0U, // VPSUBQZ256rm + 0U, // VPSUBQZ256rmb + 0U, // VPSUBQZ256rmbk + 0U, // VPSUBQZ256rmbkz + 0U, // VPSUBQZ256rmk + 0U, // VPSUBQZ256rmkz + 0U, // VPSUBQZ256rr + 0U, // VPSUBQZ256rrk + 0U, // VPSUBQZ256rrkz + 0U, // VPSUBQZrm + 0U, // VPSUBQZrmb + 0U, // VPSUBQZrmbk + 0U, // VPSUBQZrmbkz + 0U, // VPSUBQZrmk + 0U, // VPSUBQZrmkz + 0U, // VPSUBQZrr + 0U, // VPSUBQZrrk + 0U, // VPSUBQZrrkz + 0U, // VPSUBQrm + 0U, // VPSUBQrr + 0U, // VPSUBSBYrm + 0U, // VPSUBSBYrr + 0U, // VPSUBSBZ128rm + 0U, // VPSUBSBZ128rmk + 0U, // VPSUBSBZ128rmkz + 0U, // VPSUBSBZ128rr + 0U, // VPSUBSBZ128rrk + 0U, // VPSUBSBZ128rrkz + 0U, // VPSUBSBZ256rm + 0U, // VPSUBSBZ256rmk + 0U, // VPSUBSBZ256rmkz + 0U, // VPSUBSBZ256rr + 0U, // VPSUBSBZ256rrk + 0U, // VPSUBSBZ256rrkz + 0U, // VPSUBSBZrm + 0U, // VPSUBSBZrmk + 0U, // VPSUBSBZrmkz + 0U, // VPSUBSBZrr + 0U, // VPSUBSBZrrk + 0U, // VPSUBSBZrrkz + 0U, // VPSUBSBrm + 0U, // VPSUBSBrr + 0U, // VPSUBSWYrm + 0U, // VPSUBSWYrr + 0U, // VPSUBSWZ128rm + 0U, // VPSUBSWZ128rmk + 0U, // VPSUBSWZ128rmkz + 0U, // VPSUBSWZ128rr + 0U, // VPSUBSWZ128rrk + 0U, // VPSUBSWZ128rrkz + 0U, // VPSUBSWZ256rm + 0U, // VPSUBSWZ256rmk + 0U, // VPSUBSWZ256rmkz + 0U, // VPSUBSWZ256rr + 0U, // VPSUBSWZ256rrk + 0U, // VPSUBSWZ256rrkz + 0U, // VPSUBSWZrm + 0U, // VPSUBSWZrmk + 0U, // VPSUBSWZrmkz + 0U, // VPSUBSWZrr + 0U, // VPSUBSWZrrk + 0U, // VPSUBSWZrrkz + 0U, // VPSUBSWrm + 0U, // VPSUBSWrr + 0U, // VPSUBUSBYrm + 0U, // VPSUBUSBYrr + 0U, // VPSUBUSBZ128rm + 0U, // VPSUBUSBZ128rmk + 0U, // VPSUBUSBZ128rmkz + 0U, // VPSUBUSBZ128rr + 0U, // VPSUBUSBZ128rrk + 0U, // VPSUBUSBZ128rrkz + 0U, // VPSUBUSBZ256rm + 0U, // VPSUBUSBZ256rmk + 0U, // VPSUBUSBZ256rmkz + 0U, // VPSUBUSBZ256rr + 0U, // VPSUBUSBZ256rrk + 0U, // VPSUBUSBZ256rrkz + 0U, // VPSUBUSBZrm + 0U, // VPSUBUSBZrmk + 0U, // VPSUBUSBZrmkz + 0U, // VPSUBUSBZrr + 0U, // VPSUBUSBZrrk + 0U, // VPSUBUSBZrrkz + 0U, // VPSUBUSBrm + 0U, // VPSUBUSBrr + 0U, // VPSUBUSWYrm + 0U, // VPSUBUSWYrr + 0U, // VPSUBUSWZ128rm + 0U, // VPSUBUSWZ128rmk + 0U, // VPSUBUSWZ128rmkz + 0U, // VPSUBUSWZ128rr + 0U, // VPSUBUSWZ128rrk + 0U, // VPSUBUSWZ128rrkz + 0U, // VPSUBUSWZ256rm + 0U, // VPSUBUSWZ256rmk + 0U, // VPSUBUSWZ256rmkz + 0U, // VPSUBUSWZ256rr + 0U, // VPSUBUSWZ256rrk + 0U, // VPSUBUSWZ256rrkz + 0U, // VPSUBUSWZrm + 0U, // VPSUBUSWZrmk + 0U, // VPSUBUSWZrmkz + 0U, // VPSUBUSWZrr + 0U, // VPSUBUSWZrrk + 0U, // VPSUBUSWZrrkz + 0U, // VPSUBUSWrm + 0U, // VPSUBUSWrr + 0U, // VPSUBWYrm + 0U, // VPSUBWYrr + 0U, // VPSUBWZ128rm + 0U, // VPSUBWZ128rmk + 0U, // VPSUBWZ128rmkz + 0U, // VPSUBWZ128rr + 0U, // VPSUBWZ128rrk + 0U, // VPSUBWZ128rrkz + 0U, // VPSUBWZ256rm + 0U, // VPSUBWZ256rmk + 0U, // VPSUBWZ256rmkz + 0U, // VPSUBWZ256rr + 0U, // VPSUBWZ256rrk + 0U, // VPSUBWZ256rrkz + 0U, // VPSUBWZrm + 0U, // VPSUBWZrmk + 0U, // VPSUBWZrmkz + 0U, // VPSUBWZrr + 0U, // VPSUBWZrrk + 0U, // VPSUBWZrrkz + 0U, // VPSUBWrm + 0U, // VPSUBWrr + 0U, // VPTERNLOGDZ128rmbi + 0U, // VPTERNLOGDZ128rmbik + 2U, // VPTERNLOGDZ128rmbikz + 0U, // VPTERNLOGDZ128rmi + 0U, // VPTERNLOGDZ128rmik + 0U, // VPTERNLOGDZ128rmikz + 0U, // VPTERNLOGDZ128rri + 0U, // VPTERNLOGDZ128rrik + 0U, // VPTERNLOGDZ128rrikz + 0U, // VPTERNLOGDZ256rmbi + 0U, // VPTERNLOGDZ256rmbik + 2U, // VPTERNLOGDZ256rmbikz + 0U, // VPTERNLOGDZ256rmi + 0U, // VPTERNLOGDZ256rmik + 0U, // VPTERNLOGDZ256rmikz + 0U, // VPTERNLOGDZ256rri + 0U, // VPTERNLOGDZ256rrik + 0U, // VPTERNLOGDZ256rrikz + 0U, // VPTERNLOGDZrmbi + 0U, // VPTERNLOGDZrmbik + 2U, // VPTERNLOGDZrmbikz + 0U, // VPTERNLOGDZrmi + 0U, // VPTERNLOGDZrmik + 0U, // VPTERNLOGDZrmikz + 0U, // VPTERNLOGDZrri + 0U, // VPTERNLOGDZrrik + 0U, // VPTERNLOGDZrrikz + 0U, // VPTERNLOGQZ128rmbi + 0U, // VPTERNLOGQZ128rmbik + 2U, // VPTERNLOGQZ128rmbikz + 0U, // VPTERNLOGQZ128rmi + 0U, // VPTERNLOGQZ128rmik + 0U, // VPTERNLOGQZ128rmikz + 0U, // VPTERNLOGQZ128rri + 0U, // VPTERNLOGQZ128rrik + 0U, // VPTERNLOGQZ128rrikz + 0U, // VPTERNLOGQZ256rmbi + 0U, // VPTERNLOGQZ256rmbik + 2U, // VPTERNLOGQZ256rmbikz + 0U, // VPTERNLOGQZ256rmi + 0U, // VPTERNLOGQZ256rmik + 0U, // VPTERNLOGQZ256rmikz + 0U, // VPTERNLOGQZ256rri + 0U, // VPTERNLOGQZ256rrik + 0U, // VPTERNLOGQZ256rrikz + 0U, // VPTERNLOGQZrmbi + 0U, // VPTERNLOGQZrmbik + 2U, // VPTERNLOGQZrmbikz + 0U, // VPTERNLOGQZrmi + 0U, // VPTERNLOGQZrmik + 0U, // VPTERNLOGQZrmikz + 0U, // VPTERNLOGQZrri + 0U, // VPTERNLOGQZrrik + 0U, // VPTERNLOGQZrrikz + 0U, // VPTESTMBZ128rm + 0U, // VPTESTMBZ128rmk + 0U, // VPTESTMBZ128rr + 0U, // VPTESTMBZ128rrk + 0U, // VPTESTMBZ256rm + 0U, // VPTESTMBZ256rmk + 0U, // VPTESTMBZ256rr + 0U, // VPTESTMBZ256rrk + 0U, // VPTESTMBZrm + 0U, // VPTESTMBZrmk + 0U, // VPTESTMBZrr + 0U, // VPTESTMBZrrk + 0U, // VPTESTMDZ128rm + 0U, // VPTESTMDZ128rmb + 0U, // VPTESTMDZ128rmbk + 0U, // VPTESTMDZ128rmk + 0U, // VPTESTMDZ128rr + 0U, // VPTESTMDZ128rrk + 0U, // VPTESTMDZ256rm + 0U, // VPTESTMDZ256rmb + 0U, // VPTESTMDZ256rmbk + 0U, // VPTESTMDZ256rmk + 0U, // VPTESTMDZ256rr + 0U, // VPTESTMDZ256rrk + 0U, // VPTESTMDZrm + 0U, // VPTESTMDZrmb + 0U, // VPTESTMDZrmbk + 0U, // VPTESTMDZrmk + 0U, // VPTESTMDZrr + 0U, // VPTESTMDZrrk + 0U, // VPTESTMQZ128rm + 0U, // VPTESTMQZ128rmb + 0U, // VPTESTMQZ128rmbk + 0U, // VPTESTMQZ128rmk + 0U, // VPTESTMQZ128rr + 0U, // VPTESTMQZ128rrk + 0U, // VPTESTMQZ256rm + 0U, // VPTESTMQZ256rmb + 0U, // VPTESTMQZ256rmbk + 0U, // VPTESTMQZ256rmk + 0U, // VPTESTMQZ256rr + 0U, // VPTESTMQZ256rrk + 0U, // VPTESTMQZrm + 0U, // VPTESTMQZrmb + 0U, // VPTESTMQZrmbk + 0U, // VPTESTMQZrmk + 0U, // VPTESTMQZrr + 0U, // VPTESTMQZrrk + 0U, // VPTESTMWZ128rm + 0U, // VPTESTMWZ128rmk + 0U, // VPTESTMWZ128rr + 0U, // VPTESTMWZ128rrk + 0U, // VPTESTMWZ256rm + 0U, // VPTESTMWZ256rmk + 0U, // VPTESTMWZ256rr + 0U, // VPTESTMWZ256rrk + 0U, // VPTESTMWZrm + 0U, // VPTESTMWZrmk + 0U, // VPTESTMWZrr + 0U, // VPTESTMWZrrk + 0U, // VPTESTNMBZ128rm + 0U, // VPTESTNMBZ128rmk + 0U, // VPTESTNMBZ128rr + 0U, // VPTESTNMBZ128rrk + 0U, // VPTESTNMBZ256rm + 0U, // VPTESTNMBZ256rmk + 0U, // VPTESTNMBZ256rr + 0U, // VPTESTNMBZ256rrk + 0U, // VPTESTNMBZrm + 0U, // VPTESTNMBZrmk + 0U, // VPTESTNMBZrr + 0U, // VPTESTNMBZrrk + 0U, // VPTESTNMDZ128rm + 0U, // VPTESTNMDZ128rmb + 0U, // VPTESTNMDZ128rmbk + 0U, // VPTESTNMDZ128rmk + 0U, // VPTESTNMDZ128rr + 0U, // VPTESTNMDZ128rrk + 0U, // VPTESTNMDZ256rm + 0U, // VPTESTNMDZ256rmb + 0U, // VPTESTNMDZ256rmbk + 0U, // VPTESTNMDZ256rmk + 0U, // VPTESTNMDZ256rr + 0U, // VPTESTNMDZ256rrk + 0U, // VPTESTNMDZrm + 0U, // VPTESTNMDZrmb + 0U, // VPTESTNMDZrmbk + 0U, // VPTESTNMDZrmk + 0U, // VPTESTNMDZrr + 0U, // VPTESTNMDZrrk + 0U, // VPTESTNMQZ128rm + 0U, // VPTESTNMQZ128rmb + 0U, // VPTESTNMQZ128rmbk + 0U, // VPTESTNMQZ128rmk + 0U, // VPTESTNMQZ128rr + 0U, // VPTESTNMQZ128rrk + 0U, // VPTESTNMQZ256rm + 0U, // VPTESTNMQZ256rmb + 0U, // VPTESTNMQZ256rmbk + 0U, // VPTESTNMQZ256rmk + 0U, // VPTESTNMQZ256rr + 0U, // VPTESTNMQZ256rrk + 0U, // VPTESTNMQZrm + 0U, // VPTESTNMQZrmb + 0U, // VPTESTNMQZrmbk + 0U, // VPTESTNMQZrmk + 0U, // VPTESTNMQZrr + 0U, // VPTESTNMQZrrk + 0U, // VPTESTNMWZ128rm + 0U, // VPTESTNMWZ128rmk + 0U, // VPTESTNMWZ128rr + 0U, // VPTESTNMWZ128rrk + 0U, // VPTESTNMWZ256rm + 0U, // VPTESTNMWZ256rmk + 0U, // VPTESTNMWZ256rr + 0U, // VPTESTNMWZ256rrk + 0U, // VPTESTNMWZrm + 0U, // VPTESTNMWZrmk + 0U, // VPTESTNMWZrr + 0U, // VPTESTNMWZrrk + 0U, // VPTESTYrm + 0U, // VPTESTYrr + 0U, // VPTESTrm + 0U, // VPTESTrr + 0U, // VPUNPCKHBWYrm + 0U, // VPUNPCKHBWYrr + 0U, // VPUNPCKHBWZ128rm + 0U, // VPUNPCKHBWZ128rmk + 0U, // VPUNPCKHBWZ128rmkz + 0U, // VPUNPCKHBWZ128rr + 0U, // VPUNPCKHBWZ128rrk + 0U, // VPUNPCKHBWZ128rrkz + 0U, // VPUNPCKHBWZ256rm + 0U, // VPUNPCKHBWZ256rmk + 0U, // VPUNPCKHBWZ256rmkz + 0U, // VPUNPCKHBWZ256rr + 0U, // VPUNPCKHBWZ256rrk + 0U, // VPUNPCKHBWZ256rrkz + 0U, // VPUNPCKHBWZrm + 0U, // VPUNPCKHBWZrmk + 0U, // VPUNPCKHBWZrmkz + 0U, // VPUNPCKHBWZrr + 0U, // VPUNPCKHBWZrrk + 0U, // VPUNPCKHBWZrrkz + 0U, // VPUNPCKHBWrm + 0U, // VPUNPCKHBWrr + 0U, // VPUNPCKHDQYrm + 0U, // VPUNPCKHDQYrr + 0U, // VPUNPCKHDQZ128rm + 0U, // VPUNPCKHDQZ128rmb + 0U, // VPUNPCKHDQZ128rmbk + 0U, // VPUNPCKHDQZ128rmbkz + 0U, // VPUNPCKHDQZ128rmk + 0U, // VPUNPCKHDQZ128rmkz + 0U, // VPUNPCKHDQZ128rr + 0U, // VPUNPCKHDQZ128rrk + 0U, // VPUNPCKHDQZ128rrkz + 0U, // VPUNPCKHDQZ256rm + 0U, // VPUNPCKHDQZ256rmb + 0U, // VPUNPCKHDQZ256rmbk + 0U, // VPUNPCKHDQZ256rmbkz + 0U, // VPUNPCKHDQZ256rmk + 0U, // VPUNPCKHDQZ256rmkz + 0U, // VPUNPCKHDQZ256rr + 0U, // VPUNPCKHDQZ256rrk + 0U, // VPUNPCKHDQZ256rrkz + 0U, // VPUNPCKHDQZrm + 0U, // VPUNPCKHDQZrmb + 0U, // VPUNPCKHDQZrmbk + 0U, // VPUNPCKHDQZrmbkz + 0U, // VPUNPCKHDQZrmk + 0U, // VPUNPCKHDQZrmkz + 0U, // VPUNPCKHDQZrr + 0U, // VPUNPCKHDQZrrk + 0U, // VPUNPCKHDQZrrkz + 0U, // VPUNPCKHDQrm + 0U, // VPUNPCKHDQrr + 0U, // VPUNPCKHQDQYrm + 0U, // VPUNPCKHQDQYrr + 0U, // VPUNPCKHQDQZ128rm + 0U, // VPUNPCKHQDQZ128rmb + 0U, // VPUNPCKHQDQZ128rmbk + 0U, // VPUNPCKHQDQZ128rmbkz + 0U, // VPUNPCKHQDQZ128rmk + 0U, // VPUNPCKHQDQZ128rmkz + 0U, // VPUNPCKHQDQZ128rr + 0U, // VPUNPCKHQDQZ128rrk + 0U, // VPUNPCKHQDQZ128rrkz + 0U, // VPUNPCKHQDQZ256rm + 0U, // VPUNPCKHQDQZ256rmb + 0U, // VPUNPCKHQDQZ256rmbk + 0U, // VPUNPCKHQDQZ256rmbkz + 0U, // VPUNPCKHQDQZ256rmk + 0U, // VPUNPCKHQDQZ256rmkz + 0U, // VPUNPCKHQDQZ256rr + 0U, // VPUNPCKHQDQZ256rrk + 0U, // VPUNPCKHQDQZ256rrkz + 0U, // VPUNPCKHQDQZrm + 0U, // VPUNPCKHQDQZrmb + 0U, // VPUNPCKHQDQZrmbk + 0U, // VPUNPCKHQDQZrmbkz + 0U, // VPUNPCKHQDQZrmk + 0U, // VPUNPCKHQDQZrmkz + 0U, // VPUNPCKHQDQZrr + 0U, // VPUNPCKHQDQZrrk + 0U, // VPUNPCKHQDQZrrkz + 0U, // VPUNPCKHQDQrm + 0U, // VPUNPCKHQDQrr + 0U, // VPUNPCKHWDYrm + 0U, // VPUNPCKHWDYrr + 0U, // VPUNPCKHWDZ128rm + 0U, // VPUNPCKHWDZ128rmk + 0U, // VPUNPCKHWDZ128rmkz + 0U, // VPUNPCKHWDZ128rr + 0U, // VPUNPCKHWDZ128rrk + 0U, // VPUNPCKHWDZ128rrkz + 0U, // VPUNPCKHWDZ256rm + 0U, // VPUNPCKHWDZ256rmk + 0U, // VPUNPCKHWDZ256rmkz + 0U, // VPUNPCKHWDZ256rr + 0U, // VPUNPCKHWDZ256rrk + 0U, // VPUNPCKHWDZ256rrkz + 0U, // VPUNPCKHWDZrm + 0U, // VPUNPCKHWDZrmk + 0U, // VPUNPCKHWDZrmkz + 0U, // VPUNPCKHWDZrr + 0U, // VPUNPCKHWDZrrk + 0U, // VPUNPCKHWDZrrkz + 0U, // VPUNPCKHWDrm + 0U, // VPUNPCKHWDrr + 0U, // VPUNPCKLBWYrm + 0U, // VPUNPCKLBWYrr + 0U, // VPUNPCKLBWZ128rm + 0U, // VPUNPCKLBWZ128rmk + 0U, // VPUNPCKLBWZ128rmkz + 0U, // VPUNPCKLBWZ128rr + 0U, // VPUNPCKLBWZ128rrk + 0U, // VPUNPCKLBWZ128rrkz + 0U, // VPUNPCKLBWZ256rm + 0U, // VPUNPCKLBWZ256rmk + 0U, // VPUNPCKLBWZ256rmkz + 0U, // VPUNPCKLBWZ256rr + 0U, // VPUNPCKLBWZ256rrk + 0U, // VPUNPCKLBWZ256rrkz + 0U, // VPUNPCKLBWZrm + 0U, // VPUNPCKLBWZrmk + 0U, // VPUNPCKLBWZrmkz + 0U, // VPUNPCKLBWZrr + 0U, // VPUNPCKLBWZrrk + 0U, // VPUNPCKLBWZrrkz + 0U, // VPUNPCKLBWrm + 0U, // VPUNPCKLBWrr + 0U, // VPUNPCKLDQYrm + 0U, // VPUNPCKLDQYrr + 0U, // VPUNPCKLDQZ128rm + 0U, // VPUNPCKLDQZ128rmb + 0U, // VPUNPCKLDQZ128rmbk + 0U, // VPUNPCKLDQZ128rmbkz + 0U, // VPUNPCKLDQZ128rmk + 0U, // VPUNPCKLDQZ128rmkz + 0U, // VPUNPCKLDQZ128rr + 0U, // VPUNPCKLDQZ128rrk + 0U, // VPUNPCKLDQZ128rrkz + 0U, // VPUNPCKLDQZ256rm + 0U, // VPUNPCKLDQZ256rmb + 0U, // VPUNPCKLDQZ256rmbk + 0U, // VPUNPCKLDQZ256rmbkz + 0U, // VPUNPCKLDQZ256rmk + 0U, // VPUNPCKLDQZ256rmkz + 0U, // VPUNPCKLDQZ256rr + 0U, // VPUNPCKLDQZ256rrk + 0U, // VPUNPCKLDQZ256rrkz + 0U, // VPUNPCKLDQZrm + 0U, // VPUNPCKLDQZrmb + 0U, // VPUNPCKLDQZrmbk + 0U, // VPUNPCKLDQZrmbkz + 0U, // VPUNPCKLDQZrmk + 0U, // VPUNPCKLDQZrmkz + 0U, // VPUNPCKLDQZrr + 0U, // VPUNPCKLDQZrrk + 0U, // VPUNPCKLDQZrrkz + 0U, // VPUNPCKLDQrm + 0U, // VPUNPCKLDQrr + 0U, // VPUNPCKLQDQYrm + 0U, // VPUNPCKLQDQYrr + 0U, // VPUNPCKLQDQZ128rm + 0U, // VPUNPCKLQDQZ128rmb + 0U, // VPUNPCKLQDQZ128rmbk + 0U, // VPUNPCKLQDQZ128rmbkz + 0U, // VPUNPCKLQDQZ128rmk + 0U, // VPUNPCKLQDQZ128rmkz + 0U, // VPUNPCKLQDQZ128rr + 0U, // VPUNPCKLQDQZ128rrk + 0U, // VPUNPCKLQDQZ128rrkz + 0U, // VPUNPCKLQDQZ256rm + 0U, // VPUNPCKLQDQZ256rmb + 0U, // VPUNPCKLQDQZ256rmbk + 0U, // VPUNPCKLQDQZ256rmbkz + 0U, // VPUNPCKLQDQZ256rmk + 0U, // VPUNPCKLQDQZ256rmkz + 0U, // VPUNPCKLQDQZ256rr + 0U, // VPUNPCKLQDQZ256rrk + 0U, // VPUNPCKLQDQZ256rrkz + 0U, // VPUNPCKLQDQZrm + 0U, // VPUNPCKLQDQZrmb + 0U, // VPUNPCKLQDQZrmbk + 0U, // VPUNPCKLQDQZrmbkz + 0U, // VPUNPCKLQDQZrmk + 0U, // VPUNPCKLQDQZrmkz + 0U, // VPUNPCKLQDQZrr + 0U, // VPUNPCKLQDQZrrk + 0U, // VPUNPCKLQDQZrrkz + 0U, // VPUNPCKLQDQrm + 0U, // VPUNPCKLQDQrr + 0U, // VPUNPCKLWDYrm + 0U, // VPUNPCKLWDYrr + 0U, // VPUNPCKLWDZ128rm + 0U, // VPUNPCKLWDZ128rmk + 0U, // VPUNPCKLWDZ128rmkz + 0U, // VPUNPCKLWDZ128rr + 0U, // VPUNPCKLWDZ128rrk + 0U, // VPUNPCKLWDZ128rrkz + 0U, // VPUNPCKLWDZ256rm + 0U, // VPUNPCKLWDZ256rmk + 0U, // VPUNPCKLWDZ256rmkz + 0U, // VPUNPCKLWDZ256rr + 0U, // VPUNPCKLWDZ256rrk + 0U, // VPUNPCKLWDZ256rrkz + 0U, // VPUNPCKLWDZrm + 0U, // VPUNPCKLWDZrmk + 0U, // VPUNPCKLWDZrmkz + 0U, // VPUNPCKLWDZrr + 0U, // VPUNPCKLWDZrrk + 0U, // VPUNPCKLWDZrrkz + 0U, // VPUNPCKLWDrm + 0U, // VPUNPCKLWDrr + 0U, // VPXORDZ128rm + 0U, // VPXORDZ128rmb + 0U, // VPXORDZ128rmbk + 0U, // VPXORDZ128rmbkz + 0U, // VPXORDZ128rmk + 0U, // VPXORDZ128rmkz + 0U, // VPXORDZ128rr + 0U, // VPXORDZ128rrk + 0U, // VPXORDZ128rrkz + 0U, // VPXORDZ256rm + 0U, // VPXORDZ256rmb + 0U, // VPXORDZ256rmbk + 0U, // VPXORDZ256rmbkz + 0U, // VPXORDZ256rmk + 0U, // VPXORDZ256rmkz + 0U, // VPXORDZ256rr + 0U, // VPXORDZ256rrk + 0U, // VPXORDZ256rrkz + 0U, // VPXORDZrm + 0U, // VPXORDZrmb + 0U, // VPXORDZrmbk + 0U, // VPXORDZrmbkz + 0U, // VPXORDZrmk + 0U, // VPXORDZrmkz + 0U, // VPXORDZrr + 0U, // VPXORDZrrk + 0U, // VPXORDZrrkz + 0U, // VPXORQZ128rm + 0U, // VPXORQZ128rmb + 0U, // VPXORQZ128rmbk + 0U, // VPXORQZ128rmbkz + 0U, // VPXORQZ128rmk + 0U, // VPXORQZ128rmkz + 0U, // VPXORQZ128rr + 0U, // VPXORQZ128rrk + 0U, // VPXORQZ128rrkz + 0U, // VPXORQZ256rm + 0U, // VPXORQZ256rmb + 0U, // VPXORQZ256rmbk + 0U, // VPXORQZ256rmbkz + 0U, // VPXORQZ256rmk + 0U, // VPXORQZ256rmkz + 0U, // VPXORQZ256rr + 0U, // VPXORQZ256rrk + 0U, // VPXORQZ256rrkz + 0U, // VPXORQZrm + 0U, // VPXORQZrmb + 0U, // VPXORQZrmbk + 0U, // VPXORQZrmbkz + 0U, // VPXORQZrmk + 0U, // VPXORQZrmkz + 0U, // VPXORQZrr + 0U, // VPXORQZrrk + 0U, // VPXORQZrrkz + 0U, // VPXORYrm + 0U, // VPXORYrr + 0U, // VPXORrm + 0U, // VPXORrr + 0U, // VRANGEPDZ128rmbi + 0U, // VRANGEPDZ128rmbik + 3U, // VRANGEPDZ128rmbikz + 0U, // VRANGEPDZ128rmi + 0U, // VRANGEPDZ128rmik + 0U, // VRANGEPDZ128rmikz + 0U, // VRANGEPDZ128rri + 0U, // VRANGEPDZ128rrik + 3U, // VRANGEPDZ128rrikz + 0U, // VRANGEPDZ256rmbi + 0U, // VRANGEPDZ256rmbik + 3U, // VRANGEPDZ256rmbikz + 0U, // VRANGEPDZ256rmi + 0U, // VRANGEPDZ256rmik + 0U, // VRANGEPDZ256rmikz + 0U, // VRANGEPDZ256rri + 0U, // VRANGEPDZ256rrik + 3U, // VRANGEPDZ256rrikz + 0U, // VRANGEPDZrmbi + 0U, // VRANGEPDZrmbik + 3U, // VRANGEPDZrmbikz + 0U, // VRANGEPDZrmi + 0U, // VRANGEPDZrmik + 0U, // VRANGEPDZrmikz + 0U, // VRANGEPDZrri + 0U, // VRANGEPDZrrib + 0U, // VRANGEPDZrribk + 3U, // VRANGEPDZrribkz + 0U, // VRANGEPDZrrik + 3U, // VRANGEPDZrrikz + 0U, // VRANGEPSZ128rmbi + 0U, // VRANGEPSZ128rmbik + 3U, // VRANGEPSZ128rmbikz + 0U, // VRANGEPSZ128rmi + 0U, // VRANGEPSZ128rmik + 0U, // VRANGEPSZ128rmikz + 0U, // VRANGEPSZ128rri + 0U, // VRANGEPSZ128rrik + 3U, // VRANGEPSZ128rrikz + 0U, // VRANGEPSZ256rmbi + 0U, // VRANGEPSZ256rmbik + 3U, // VRANGEPSZ256rmbikz + 0U, // VRANGEPSZ256rmi + 0U, // VRANGEPSZ256rmik + 0U, // VRANGEPSZ256rmikz + 0U, // VRANGEPSZ256rri + 0U, // VRANGEPSZ256rrik + 3U, // VRANGEPSZ256rrikz + 0U, // VRANGEPSZrmbi + 0U, // VRANGEPSZrmbik + 3U, // VRANGEPSZrmbikz + 0U, // VRANGEPSZrmi + 0U, // VRANGEPSZrmik + 0U, // VRANGEPSZrmikz + 0U, // VRANGEPSZrri + 0U, // VRANGEPSZrrib + 0U, // VRANGEPSZrribk + 3U, // VRANGEPSZrribkz + 0U, // VRANGEPSZrrik + 3U, // VRANGEPSZrrikz + 0U, // VRANGESDZrmi + 0U, // VRANGESDZrmik + 3U, // VRANGESDZrmikz + 0U, // VRANGESDZrri + 0U, // VRANGESDZrrib + 0U, // VRANGESDZrribk + 3U, // VRANGESDZrribkz + 0U, // VRANGESDZrrik + 3U, // VRANGESDZrrikz + 0U, // VRANGESSZrmi + 0U, // VRANGESSZrmik + 3U, // VRANGESSZrmikz + 0U, // VRANGESSZrri + 0U, // VRANGESSZrrib + 0U, // VRANGESSZrribk + 3U, // VRANGESSZrribkz + 0U, // VRANGESSZrrik + 3U, // VRANGESSZrrikz + 0U, // VRCP14PDZ128m + 0U, // VRCP14PDZ128mb + 0U, // VRCP14PDZ128mbk + 0U, // VRCP14PDZ128mbkz + 0U, // VRCP14PDZ128mk + 0U, // VRCP14PDZ128mkz + 0U, // VRCP14PDZ128r + 0U, // VRCP14PDZ128rk + 0U, // VRCP14PDZ128rkz + 0U, // VRCP14PDZ256m + 0U, // VRCP14PDZ256mb + 0U, // VRCP14PDZ256mbk + 0U, // VRCP14PDZ256mbkz + 0U, // VRCP14PDZ256mk + 0U, // VRCP14PDZ256mkz + 0U, // VRCP14PDZ256r + 0U, // VRCP14PDZ256rk + 0U, // VRCP14PDZ256rkz + 0U, // VRCP14PDZm + 0U, // VRCP14PDZmb + 0U, // VRCP14PDZmbk + 0U, // VRCP14PDZmbkz + 0U, // VRCP14PDZmk + 0U, // VRCP14PDZmkz + 0U, // VRCP14PDZr + 0U, // VRCP14PDZrk + 0U, // VRCP14PDZrkz + 0U, // VRCP14PSZ128m + 0U, // VRCP14PSZ128mb + 0U, // VRCP14PSZ128mbk + 0U, // VRCP14PSZ128mbkz + 0U, // VRCP14PSZ128mk + 0U, // VRCP14PSZ128mkz + 0U, // VRCP14PSZ128r + 0U, // VRCP14PSZ128rk + 0U, // VRCP14PSZ128rkz + 0U, // VRCP14PSZ256m + 0U, // VRCP14PSZ256mb + 0U, // VRCP14PSZ256mbk + 0U, // VRCP14PSZ256mbkz + 0U, // VRCP14PSZ256mk + 0U, // VRCP14PSZ256mkz + 0U, // VRCP14PSZ256r + 0U, // VRCP14PSZ256rk + 0U, // VRCP14PSZ256rkz + 0U, // VRCP14PSZm + 0U, // VRCP14PSZmb + 0U, // VRCP14PSZmbk + 0U, // VRCP14PSZmbkz + 0U, // VRCP14PSZmk + 0U, // VRCP14PSZmkz + 0U, // VRCP14PSZr + 0U, // VRCP14PSZrk + 0U, // VRCP14PSZrkz + 0U, // VRCP14SDZrm + 0U, // VRCP14SDZrmk + 0U, // VRCP14SDZrmkz + 0U, // VRCP14SDZrr + 0U, // VRCP14SDZrrk + 0U, // VRCP14SDZrrkz + 0U, // VRCP14SSZrm + 0U, // VRCP14SSZrmk + 0U, // VRCP14SSZrmkz + 0U, // VRCP14SSZrr + 0U, // VRCP14SSZrrk + 0U, // VRCP14SSZrrkz + 0U, // VRCP28PDZm + 0U, // VRCP28PDZmb + 0U, // VRCP28PDZmbk + 0U, // VRCP28PDZmbkz + 0U, // VRCP28PDZmk + 0U, // VRCP28PDZmkz + 0U, // VRCP28PDZr + 0U, // VRCP28PDZrb + 0U, // VRCP28PDZrbk + 0U, // VRCP28PDZrbkz + 0U, // VRCP28PDZrk + 0U, // VRCP28PDZrkz + 0U, // VRCP28PSZm + 0U, // VRCP28PSZmb + 0U, // VRCP28PSZmbk + 0U, // VRCP28PSZmbkz + 0U, // VRCP28PSZmk + 0U, // VRCP28PSZmkz + 0U, // VRCP28PSZr + 0U, // VRCP28PSZrb + 0U, // VRCP28PSZrbk + 0U, // VRCP28PSZrbkz + 0U, // VRCP28PSZrk + 0U, // VRCP28PSZrkz + 0U, // VRCP28SDZm + 0U, // VRCP28SDZmk + 0U, // VRCP28SDZmkz + 0U, // VRCP28SDZr + 0U, // VRCP28SDZrb + 0U, // VRCP28SDZrbk + 0U, // VRCP28SDZrbkz + 0U, // VRCP28SDZrk + 0U, // VRCP28SDZrkz + 0U, // VRCP28SSZm + 0U, // VRCP28SSZmk + 0U, // VRCP28SSZmkz + 0U, // VRCP28SSZr + 0U, // VRCP28SSZrb + 0U, // VRCP28SSZrbk + 0U, // VRCP28SSZrbkz + 0U, // VRCP28SSZrk + 0U, // VRCP28SSZrkz + 0U, // VRCPPSYm + 0U, // VRCPPSYr + 0U, // VRCPPSm + 0U, // VRCPPSr + 0U, // VRCPSSm + 0U, // VRCPSSm_Int + 0U, // VRCPSSr + 0U, // VRCPSSr_Int + 0U, // VREDUCEPDZ128rmbi + 0U, // VREDUCEPDZ128rmbik + 0U, // VREDUCEPDZ128rmbikz + 0U, // VREDUCEPDZ128rmi + 0U, // VREDUCEPDZ128rmik + 0U, // VREDUCEPDZ128rmikz + 0U, // VREDUCEPDZ128rri + 0U, // VREDUCEPDZ128rrik + 0U, // VREDUCEPDZ128rrikz + 0U, // VREDUCEPDZ256rmbi + 0U, // VREDUCEPDZ256rmbik + 0U, // VREDUCEPDZ256rmbikz + 0U, // VREDUCEPDZ256rmi + 0U, // VREDUCEPDZ256rmik + 0U, // VREDUCEPDZ256rmikz + 0U, // VREDUCEPDZ256rri + 0U, // VREDUCEPDZ256rrik + 0U, // VREDUCEPDZ256rrikz + 0U, // VREDUCEPDZrmbi + 0U, // VREDUCEPDZrmbik + 0U, // VREDUCEPDZrmbikz + 0U, // VREDUCEPDZrmi + 0U, // VREDUCEPDZrmik + 0U, // VREDUCEPDZrmikz + 0U, // VREDUCEPDZrri + 0U, // VREDUCEPDZrrib + 0U, // VREDUCEPDZrribk + 0U, // VREDUCEPDZrribkz + 0U, // VREDUCEPDZrrik + 0U, // VREDUCEPDZrrikz + 0U, // VREDUCEPSZ128rmbi + 0U, // VREDUCEPSZ128rmbik + 0U, // VREDUCEPSZ128rmbikz + 0U, // VREDUCEPSZ128rmi + 0U, // VREDUCEPSZ128rmik + 0U, // VREDUCEPSZ128rmikz + 0U, // VREDUCEPSZ128rri + 0U, // VREDUCEPSZ128rrik + 0U, // VREDUCEPSZ128rrikz + 0U, // VREDUCEPSZ256rmbi + 0U, // VREDUCEPSZ256rmbik + 0U, // VREDUCEPSZ256rmbikz + 0U, // VREDUCEPSZ256rmi + 0U, // VREDUCEPSZ256rmik + 0U, // VREDUCEPSZ256rmikz + 0U, // VREDUCEPSZ256rri + 0U, // VREDUCEPSZ256rrik + 0U, // VREDUCEPSZ256rrikz + 0U, // VREDUCEPSZrmbi + 0U, // VREDUCEPSZrmbik + 0U, // VREDUCEPSZrmbikz + 0U, // VREDUCEPSZrmi + 0U, // VREDUCEPSZrmik + 0U, // VREDUCEPSZrmikz + 0U, // VREDUCEPSZrri + 0U, // VREDUCEPSZrrib + 0U, // VREDUCEPSZrribk + 0U, // VREDUCEPSZrribkz + 0U, // VREDUCEPSZrrik + 0U, // VREDUCEPSZrrikz + 0U, // VREDUCESDZrmi + 0U, // VREDUCESDZrmik + 3U, // VREDUCESDZrmikz + 0U, // VREDUCESDZrri + 0U, // VREDUCESDZrrib + 0U, // VREDUCESDZrribk + 3U, // VREDUCESDZrribkz + 0U, // VREDUCESDZrrik + 3U, // VREDUCESDZrrikz + 0U, // VREDUCESSZrmi + 0U, // VREDUCESSZrmik + 3U, // VREDUCESSZrmikz + 0U, // VREDUCESSZrri + 0U, // VREDUCESSZrrib + 0U, // VREDUCESSZrribk + 3U, // VREDUCESSZrribkz + 0U, // VREDUCESSZrrik + 3U, // VREDUCESSZrrikz + 0U, // VRNDSCALEPDZ128rmbi + 0U, // VRNDSCALEPDZ128rmbik + 0U, // VRNDSCALEPDZ128rmbikz + 0U, // VRNDSCALEPDZ128rmi + 0U, // VRNDSCALEPDZ128rmik + 0U, // VRNDSCALEPDZ128rmikz + 0U, // VRNDSCALEPDZ128rri + 0U, // VRNDSCALEPDZ128rrik + 0U, // VRNDSCALEPDZ128rrikz + 0U, // VRNDSCALEPDZ256rmbi + 0U, // VRNDSCALEPDZ256rmbik + 0U, // VRNDSCALEPDZ256rmbikz + 0U, // VRNDSCALEPDZ256rmi + 0U, // VRNDSCALEPDZ256rmik + 0U, // VRNDSCALEPDZ256rmikz + 0U, // VRNDSCALEPDZ256rri + 0U, // VRNDSCALEPDZ256rrik + 0U, // VRNDSCALEPDZ256rrikz + 0U, // VRNDSCALEPDZrmbi + 0U, // VRNDSCALEPDZrmbik + 0U, // VRNDSCALEPDZrmbikz + 0U, // VRNDSCALEPDZrmi + 0U, // VRNDSCALEPDZrmik + 0U, // VRNDSCALEPDZrmikz + 0U, // VRNDSCALEPDZrri + 0U, // VRNDSCALEPDZrrib + 0U, // VRNDSCALEPDZrribk + 0U, // VRNDSCALEPDZrribkz + 0U, // VRNDSCALEPDZrrik + 0U, // VRNDSCALEPDZrrikz + 0U, // VRNDSCALEPSZ128rmbi + 0U, // VRNDSCALEPSZ128rmbik + 0U, // VRNDSCALEPSZ128rmbikz + 0U, // VRNDSCALEPSZ128rmi + 0U, // VRNDSCALEPSZ128rmik + 0U, // VRNDSCALEPSZ128rmikz + 0U, // VRNDSCALEPSZ128rri + 0U, // VRNDSCALEPSZ128rrik + 0U, // VRNDSCALEPSZ128rrikz + 0U, // VRNDSCALEPSZ256rmbi + 0U, // VRNDSCALEPSZ256rmbik + 0U, // VRNDSCALEPSZ256rmbikz + 0U, // VRNDSCALEPSZ256rmi + 0U, // VRNDSCALEPSZ256rmik + 0U, // VRNDSCALEPSZ256rmikz + 0U, // VRNDSCALEPSZ256rri + 0U, // VRNDSCALEPSZ256rrik + 0U, // VRNDSCALEPSZ256rrikz + 0U, // VRNDSCALEPSZrmbi + 0U, // VRNDSCALEPSZrmbik + 0U, // VRNDSCALEPSZrmbikz + 0U, // VRNDSCALEPSZrmi + 0U, // VRNDSCALEPSZrmik + 0U, // VRNDSCALEPSZrmikz + 0U, // VRNDSCALEPSZrri + 0U, // VRNDSCALEPSZrrib + 0U, // VRNDSCALEPSZrribk + 0U, // VRNDSCALEPSZrribkz + 0U, // VRNDSCALEPSZrrik + 0U, // VRNDSCALEPSZrrikz + 0U, // VRNDSCALESDZm + 0U, // VRNDSCALESDZm_Int + 0U, // VRNDSCALESDZm_Intk + 3U, // VRNDSCALESDZm_Intkz + 0U, // VRNDSCALESDZr + 0U, // VRNDSCALESDZr_Int + 0U, // VRNDSCALESDZr_Intk + 3U, // VRNDSCALESDZr_Intkz + 0U, // VRNDSCALESDZrb_Int + 0U, // VRNDSCALESDZrb_Intk + 3U, // VRNDSCALESDZrb_Intkz + 0U, // VRNDSCALESSZm + 0U, // VRNDSCALESSZm_Int + 0U, // VRNDSCALESSZm_Intk + 3U, // VRNDSCALESSZm_Intkz + 0U, // VRNDSCALESSZr + 0U, // VRNDSCALESSZr_Int + 0U, // VRNDSCALESSZr_Intk + 3U, // VRNDSCALESSZr_Intkz + 0U, // VRNDSCALESSZrb_Int + 0U, // VRNDSCALESSZrb_Intk + 3U, // VRNDSCALESSZrb_Intkz + 0U, // VROUNDPDYm + 0U, // VROUNDPDYr + 0U, // VROUNDPDm + 0U, // VROUNDPDr + 0U, // VROUNDPSYm + 0U, // VROUNDPSYr + 0U, // VROUNDPSm + 0U, // VROUNDPSr + 0U, // VROUNDSDm + 0U, // VROUNDSDm_Int + 0U, // VROUNDSDr + 0U, // VROUNDSDr_Int + 0U, // VROUNDSSm + 0U, // VROUNDSSm_Int + 0U, // VROUNDSSr + 0U, // VROUNDSSr_Int + 0U, // VRSQRT14PDZ128m + 0U, // VRSQRT14PDZ128mb + 0U, // VRSQRT14PDZ128mbk + 0U, // VRSQRT14PDZ128mbkz + 0U, // VRSQRT14PDZ128mk + 0U, // VRSQRT14PDZ128mkz + 0U, // VRSQRT14PDZ128r + 0U, // VRSQRT14PDZ128rk + 0U, // VRSQRT14PDZ128rkz + 0U, // VRSQRT14PDZ256m + 0U, // VRSQRT14PDZ256mb + 0U, // VRSQRT14PDZ256mbk + 0U, // VRSQRT14PDZ256mbkz + 0U, // VRSQRT14PDZ256mk + 0U, // VRSQRT14PDZ256mkz + 0U, // VRSQRT14PDZ256r + 0U, // VRSQRT14PDZ256rk + 0U, // VRSQRT14PDZ256rkz + 0U, // VRSQRT14PDZm + 0U, // VRSQRT14PDZmb + 0U, // VRSQRT14PDZmbk + 0U, // VRSQRT14PDZmbkz + 0U, // VRSQRT14PDZmk + 0U, // VRSQRT14PDZmkz + 0U, // VRSQRT14PDZr + 0U, // VRSQRT14PDZrk + 0U, // VRSQRT14PDZrkz + 0U, // VRSQRT14PSZ128m + 0U, // VRSQRT14PSZ128mb + 0U, // VRSQRT14PSZ128mbk + 0U, // VRSQRT14PSZ128mbkz + 0U, // VRSQRT14PSZ128mk + 0U, // VRSQRT14PSZ128mkz + 0U, // VRSQRT14PSZ128r + 0U, // VRSQRT14PSZ128rk + 0U, // VRSQRT14PSZ128rkz + 0U, // VRSQRT14PSZ256m + 0U, // VRSQRT14PSZ256mb + 0U, // VRSQRT14PSZ256mbk + 0U, // VRSQRT14PSZ256mbkz + 0U, // VRSQRT14PSZ256mk + 0U, // VRSQRT14PSZ256mkz + 0U, // VRSQRT14PSZ256r + 0U, // VRSQRT14PSZ256rk + 0U, // VRSQRT14PSZ256rkz + 0U, // VRSQRT14PSZm + 0U, // VRSQRT14PSZmb + 0U, // VRSQRT14PSZmbk + 0U, // VRSQRT14PSZmbkz + 0U, // VRSQRT14PSZmk + 0U, // VRSQRT14PSZmkz + 0U, // VRSQRT14PSZr + 0U, // VRSQRT14PSZrk + 0U, // VRSQRT14PSZrkz + 0U, // VRSQRT14SDZrm + 0U, // VRSQRT14SDZrmk + 0U, // VRSQRT14SDZrmkz + 0U, // VRSQRT14SDZrr + 0U, // VRSQRT14SDZrrk + 0U, // VRSQRT14SDZrrkz + 0U, // VRSQRT14SSZrm + 0U, // VRSQRT14SSZrmk + 0U, // VRSQRT14SSZrmkz + 0U, // VRSQRT14SSZrr + 0U, // VRSQRT14SSZrrk + 0U, // VRSQRT14SSZrrkz + 0U, // VRSQRT28PDZm + 0U, // VRSQRT28PDZmb + 0U, // VRSQRT28PDZmbk + 0U, // VRSQRT28PDZmbkz + 0U, // VRSQRT28PDZmk + 0U, // VRSQRT28PDZmkz + 0U, // VRSQRT28PDZr + 0U, // VRSQRT28PDZrb + 0U, // VRSQRT28PDZrbk + 0U, // VRSQRT28PDZrbkz + 0U, // VRSQRT28PDZrk + 0U, // VRSQRT28PDZrkz + 0U, // VRSQRT28PSZm + 0U, // VRSQRT28PSZmb + 0U, // VRSQRT28PSZmbk + 0U, // VRSQRT28PSZmbkz + 0U, // VRSQRT28PSZmk + 0U, // VRSQRT28PSZmkz + 0U, // VRSQRT28PSZr + 0U, // VRSQRT28PSZrb + 0U, // VRSQRT28PSZrbk + 0U, // VRSQRT28PSZrbkz + 0U, // VRSQRT28PSZrk + 0U, // VRSQRT28PSZrkz + 0U, // VRSQRT28SDZm + 0U, // VRSQRT28SDZmk + 0U, // VRSQRT28SDZmkz + 0U, // VRSQRT28SDZr + 0U, // VRSQRT28SDZrb + 0U, // VRSQRT28SDZrbk + 0U, // VRSQRT28SDZrbkz + 0U, // VRSQRT28SDZrk + 0U, // VRSQRT28SDZrkz + 0U, // VRSQRT28SSZm + 0U, // VRSQRT28SSZmk + 0U, // VRSQRT28SSZmkz + 0U, // VRSQRT28SSZr + 0U, // VRSQRT28SSZrb + 0U, // VRSQRT28SSZrbk + 0U, // VRSQRT28SSZrbkz + 0U, // VRSQRT28SSZrk + 0U, // VRSQRT28SSZrkz + 0U, // VRSQRTPSYm + 0U, // VRSQRTPSYr + 0U, // VRSQRTPSm + 0U, // VRSQRTPSr + 0U, // VRSQRTSSm + 0U, // VRSQRTSSm_Int + 0U, // VRSQRTSSr + 0U, // VRSQRTSSr_Int + 0U, // VSCALEFPDZ128rm + 0U, // VSCALEFPDZ128rmb + 0U, // VSCALEFPDZ128rmbk + 0U, // VSCALEFPDZ128rmbkz + 0U, // VSCALEFPDZ128rmk + 0U, // VSCALEFPDZ128rmkz + 0U, // VSCALEFPDZ128rr + 0U, // VSCALEFPDZ128rrk + 0U, // VSCALEFPDZ128rrkz + 0U, // VSCALEFPDZ256rm + 0U, // VSCALEFPDZ256rmb + 0U, // VSCALEFPDZ256rmbk + 0U, // VSCALEFPDZ256rmbkz + 0U, // VSCALEFPDZ256rmk + 0U, // VSCALEFPDZ256rmkz + 0U, // VSCALEFPDZ256rr + 0U, // VSCALEFPDZ256rrk + 0U, // VSCALEFPDZ256rrkz + 0U, // VSCALEFPDZrm + 0U, // VSCALEFPDZrmb + 0U, // VSCALEFPDZrmbk + 0U, // VSCALEFPDZrmbkz + 0U, // VSCALEFPDZrmk + 0U, // VSCALEFPDZrmkz + 0U, // VSCALEFPDZrr + 0U, // VSCALEFPDZrrb + 0U, // VSCALEFPDZrrbk + 0U, // VSCALEFPDZrrbkz + 0U, // VSCALEFPDZrrk + 0U, // VSCALEFPDZrrkz + 0U, // VSCALEFPSZ128rm + 0U, // VSCALEFPSZ128rmb + 0U, // VSCALEFPSZ128rmbk + 0U, // VSCALEFPSZ128rmbkz + 0U, // VSCALEFPSZ128rmk + 0U, // VSCALEFPSZ128rmkz + 0U, // VSCALEFPSZ128rr + 0U, // VSCALEFPSZ128rrk + 0U, // VSCALEFPSZ128rrkz + 0U, // VSCALEFPSZ256rm + 0U, // VSCALEFPSZ256rmb + 0U, // VSCALEFPSZ256rmbk + 0U, // VSCALEFPSZ256rmbkz + 0U, // VSCALEFPSZ256rmk + 0U, // VSCALEFPSZ256rmkz + 0U, // VSCALEFPSZ256rr + 0U, // VSCALEFPSZ256rrk + 0U, // VSCALEFPSZ256rrkz + 0U, // VSCALEFPSZrm + 0U, // VSCALEFPSZrmb + 0U, // VSCALEFPSZrmbk + 0U, // VSCALEFPSZrmbkz + 0U, // VSCALEFPSZrmk + 0U, // VSCALEFPSZrmkz + 0U, // VSCALEFPSZrr + 0U, // VSCALEFPSZrrb + 0U, // VSCALEFPSZrrbk + 0U, // VSCALEFPSZrrbkz + 0U, // VSCALEFPSZrrk + 0U, // VSCALEFPSZrrkz + 0U, // VSCALEFSDZrm + 0U, // VSCALEFSDZrmk + 0U, // VSCALEFSDZrmkz + 0U, // VSCALEFSDZrr + 0U, // VSCALEFSDZrrb_Int + 0U, // VSCALEFSDZrrb_Intk + 0U, // VSCALEFSDZrrb_Intkz + 0U, // VSCALEFSDZrrk + 0U, // VSCALEFSDZrrkz + 0U, // VSCALEFSSZrm + 0U, // VSCALEFSSZrmk + 0U, // VSCALEFSSZrmkz + 0U, // VSCALEFSSZrr + 0U, // VSCALEFSSZrrb_Int + 0U, // VSCALEFSSZrrb_Intk + 0U, // VSCALEFSSZrrb_Intkz + 0U, // VSCALEFSSZrrk + 0U, // VSCALEFSSZrrkz + 0U, // VSCATTERDPDZ128mr + 0U, // VSCATTERDPDZ256mr + 0U, // VSCATTERDPDZmr + 0U, // VSCATTERDPSZ128mr + 0U, // VSCATTERDPSZ256mr + 0U, // VSCATTERDPSZmr + 0U, // VSCATTERPF0DPDm + 0U, // VSCATTERPF0DPSm + 0U, // VSCATTERPF0QPDm + 0U, // VSCATTERPF0QPSm + 0U, // VSCATTERPF1DPDm + 0U, // VSCATTERPF1DPSm + 0U, // VSCATTERPF1QPDm + 0U, // VSCATTERPF1QPSm + 0U, // VSCATTERQPDZ128mr + 0U, // VSCATTERQPDZ256mr + 0U, // VSCATTERQPDZmr + 0U, // VSCATTERQPSZ128mr + 0U, // VSCATTERQPSZ256mr + 0U, // VSCATTERQPSZmr + 0U, // VSHUFF32X4Z256rmbi + 0U, // VSHUFF32X4Z256rmbik + 3U, // VSHUFF32X4Z256rmbikz + 0U, // VSHUFF32X4Z256rmi + 0U, // VSHUFF32X4Z256rmik + 0U, // VSHUFF32X4Z256rmikz + 0U, // VSHUFF32X4Z256rri + 0U, // VSHUFF32X4Z256rrik + 3U, // VSHUFF32X4Z256rrikz + 0U, // VSHUFF32X4Zrmbi + 0U, // VSHUFF32X4Zrmbik + 3U, // VSHUFF32X4Zrmbikz + 0U, // VSHUFF32X4Zrmi + 0U, // VSHUFF32X4Zrmik + 0U, // VSHUFF32X4Zrmikz + 0U, // VSHUFF32X4Zrri + 0U, // VSHUFF32X4Zrrik + 3U, // VSHUFF32X4Zrrikz + 0U, // VSHUFF64X2Z256rmbi + 0U, // VSHUFF64X2Z256rmbik + 3U, // VSHUFF64X2Z256rmbikz + 0U, // VSHUFF64X2Z256rmi + 0U, // VSHUFF64X2Z256rmik + 0U, // VSHUFF64X2Z256rmikz + 0U, // VSHUFF64X2Z256rri + 0U, // VSHUFF64X2Z256rrik + 3U, // VSHUFF64X2Z256rrikz + 0U, // VSHUFF64X2Zrmbi + 0U, // VSHUFF64X2Zrmbik + 3U, // VSHUFF64X2Zrmbikz + 0U, // VSHUFF64X2Zrmi + 0U, // VSHUFF64X2Zrmik + 0U, // VSHUFF64X2Zrmikz + 0U, // VSHUFF64X2Zrri + 0U, // VSHUFF64X2Zrrik + 3U, // VSHUFF64X2Zrrikz + 0U, // VSHUFI32X4Z256rmbi + 0U, // VSHUFI32X4Z256rmbik + 3U, // VSHUFI32X4Z256rmbikz + 0U, // VSHUFI32X4Z256rmi + 0U, // VSHUFI32X4Z256rmik + 0U, // VSHUFI32X4Z256rmikz + 0U, // VSHUFI32X4Z256rri + 0U, // VSHUFI32X4Z256rrik + 3U, // VSHUFI32X4Z256rrikz + 0U, // VSHUFI32X4Zrmbi + 0U, // VSHUFI32X4Zrmbik + 3U, // VSHUFI32X4Zrmbikz + 0U, // VSHUFI32X4Zrmi + 0U, // VSHUFI32X4Zrmik + 0U, // VSHUFI32X4Zrmikz + 0U, // VSHUFI32X4Zrri + 0U, // VSHUFI32X4Zrrik + 3U, // VSHUFI32X4Zrrikz + 0U, // VSHUFI64X2Z256rmbi + 0U, // VSHUFI64X2Z256rmbik + 3U, // VSHUFI64X2Z256rmbikz + 0U, // VSHUFI64X2Z256rmi + 0U, // VSHUFI64X2Z256rmik + 0U, // VSHUFI64X2Z256rmikz + 0U, // VSHUFI64X2Z256rri + 0U, // VSHUFI64X2Z256rrik + 3U, // VSHUFI64X2Z256rrikz + 0U, // VSHUFI64X2Zrmbi + 0U, // VSHUFI64X2Zrmbik + 3U, // VSHUFI64X2Zrmbikz + 0U, // VSHUFI64X2Zrmi + 0U, // VSHUFI64X2Zrmik + 0U, // VSHUFI64X2Zrmikz + 0U, // VSHUFI64X2Zrri + 0U, // VSHUFI64X2Zrrik + 3U, // VSHUFI64X2Zrrikz + 0U, // VSHUFPDYrmi + 0U, // VSHUFPDYrri + 0U, // VSHUFPDZ128rmbi + 0U, // VSHUFPDZ128rmbik + 3U, // VSHUFPDZ128rmbikz + 0U, // VSHUFPDZ128rmi + 0U, // VSHUFPDZ128rmik + 0U, // VSHUFPDZ128rmikz + 0U, // VSHUFPDZ128rri + 0U, // VSHUFPDZ128rrik + 3U, // VSHUFPDZ128rrikz + 0U, // VSHUFPDZ256rmbi + 0U, // VSHUFPDZ256rmbik + 3U, // VSHUFPDZ256rmbikz + 0U, // VSHUFPDZ256rmi + 0U, // VSHUFPDZ256rmik + 0U, // VSHUFPDZ256rmikz + 0U, // VSHUFPDZ256rri + 0U, // VSHUFPDZ256rrik + 3U, // VSHUFPDZ256rrikz + 0U, // VSHUFPDZrmbi + 0U, // VSHUFPDZrmbik + 3U, // VSHUFPDZrmbikz + 0U, // VSHUFPDZrmi + 0U, // VSHUFPDZrmik + 0U, // VSHUFPDZrmikz + 0U, // VSHUFPDZrri + 0U, // VSHUFPDZrrik + 3U, // VSHUFPDZrrikz + 0U, // VSHUFPDrmi + 0U, // VSHUFPDrri + 0U, // VSHUFPSYrmi + 0U, // VSHUFPSYrri + 0U, // VSHUFPSZ128rmbi + 0U, // VSHUFPSZ128rmbik + 3U, // VSHUFPSZ128rmbikz + 0U, // VSHUFPSZ128rmi + 0U, // VSHUFPSZ128rmik + 0U, // VSHUFPSZ128rmikz + 0U, // VSHUFPSZ128rri + 0U, // VSHUFPSZ128rrik + 3U, // VSHUFPSZ128rrikz + 0U, // VSHUFPSZ256rmbi + 0U, // VSHUFPSZ256rmbik + 3U, // VSHUFPSZ256rmbikz + 0U, // VSHUFPSZ256rmi + 0U, // VSHUFPSZ256rmik + 0U, // VSHUFPSZ256rmikz + 0U, // VSHUFPSZ256rri + 0U, // VSHUFPSZ256rrik + 3U, // VSHUFPSZ256rrikz + 0U, // VSHUFPSZrmbi + 0U, // VSHUFPSZrmbik + 3U, // VSHUFPSZrmbikz + 0U, // VSHUFPSZrmi + 0U, // VSHUFPSZrmik + 0U, // VSHUFPSZrmikz + 0U, // VSHUFPSZrri + 0U, // VSHUFPSZrrik + 3U, // VSHUFPSZrrikz + 0U, // VSHUFPSrmi + 0U, // VSHUFPSrri + 0U, // VSQRTPDYm + 0U, // VSQRTPDYr + 0U, // VSQRTPDZ128m + 0U, // VSQRTPDZ128mb + 0U, // VSQRTPDZ128mbk + 0U, // VSQRTPDZ128mbkz + 0U, // VSQRTPDZ128mk + 0U, // VSQRTPDZ128mkz + 0U, // VSQRTPDZ128r + 0U, // VSQRTPDZ128rk + 0U, // VSQRTPDZ128rkz + 0U, // VSQRTPDZ256m + 0U, // VSQRTPDZ256mb + 0U, // VSQRTPDZ256mbk + 0U, // VSQRTPDZ256mbkz + 0U, // VSQRTPDZ256mk + 0U, // VSQRTPDZ256mkz + 0U, // VSQRTPDZ256r + 0U, // VSQRTPDZ256rk + 0U, // VSQRTPDZ256rkz + 0U, // VSQRTPDZm + 0U, // VSQRTPDZmb + 0U, // VSQRTPDZmbk + 0U, // VSQRTPDZmbkz + 0U, // VSQRTPDZmk + 0U, // VSQRTPDZmkz + 0U, // VSQRTPDZr + 0U, // VSQRTPDZrb + 0U, // VSQRTPDZrbk + 0U, // VSQRTPDZrbkz + 0U, // VSQRTPDZrk + 0U, // VSQRTPDZrkz + 0U, // VSQRTPDm + 0U, // VSQRTPDr + 0U, // VSQRTPSYm + 0U, // VSQRTPSYr + 0U, // VSQRTPSZ128m + 0U, // VSQRTPSZ128mb + 0U, // VSQRTPSZ128mbk + 0U, // VSQRTPSZ128mbkz + 0U, // VSQRTPSZ128mk + 0U, // VSQRTPSZ128mkz + 0U, // VSQRTPSZ128r + 0U, // VSQRTPSZ128rk + 0U, // VSQRTPSZ128rkz + 0U, // VSQRTPSZ256m + 0U, // VSQRTPSZ256mb + 0U, // VSQRTPSZ256mbk + 0U, // VSQRTPSZ256mbkz + 0U, // VSQRTPSZ256mk + 0U, // VSQRTPSZ256mkz + 0U, // VSQRTPSZ256r + 0U, // VSQRTPSZ256rk + 0U, // VSQRTPSZ256rkz + 0U, // VSQRTPSZm + 0U, // VSQRTPSZmb + 0U, // VSQRTPSZmbk + 0U, // VSQRTPSZmbkz + 0U, // VSQRTPSZmk + 0U, // VSQRTPSZmkz + 0U, // VSQRTPSZr + 0U, // VSQRTPSZrb + 0U, // VSQRTPSZrbk + 0U, // VSQRTPSZrbkz + 0U, // VSQRTPSZrk + 0U, // VSQRTPSZrkz + 0U, // VSQRTPSm + 0U, // VSQRTPSr + 0U, // VSQRTSDZm + 0U, // VSQRTSDZm_Int + 0U, // VSQRTSDZm_Intk + 0U, // VSQRTSDZm_Intkz + 0U, // VSQRTSDZr + 0U, // VSQRTSDZr_Int + 0U, // VSQRTSDZr_Intk + 0U, // VSQRTSDZr_Intkz + 0U, // VSQRTSDZrb_Int + 0U, // VSQRTSDZrb_Intk + 0U, // VSQRTSDZrb_Intkz + 0U, // VSQRTSDm + 0U, // VSQRTSDm_Int + 0U, // VSQRTSDr + 0U, // VSQRTSDr_Int + 0U, // VSQRTSSZm + 0U, // VSQRTSSZm_Int + 0U, // VSQRTSSZm_Intk + 0U, // VSQRTSSZm_Intkz + 0U, // VSQRTSSZr + 0U, // VSQRTSSZr_Int + 0U, // VSQRTSSZr_Intk + 0U, // VSQRTSSZr_Intkz + 0U, // VSQRTSSZrb_Int + 0U, // VSQRTSSZrb_Intk + 0U, // VSQRTSSZrb_Intkz + 0U, // VSQRTSSm + 0U, // VSQRTSSm_Int + 0U, // VSQRTSSr + 0U, // VSQRTSSr_Int + 0U, // VSTMXCSR + 0U, // VSUBPDYrm + 0U, // VSUBPDYrr + 0U, // VSUBPDZ128rm + 0U, // VSUBPDZ128rmb + 0U, // VSUBPDZ128rmbk + 0U, // VSUBPDZ128rmbkz + 0U, // VSUBPDZ128rmk + 0U, // VSUBPDZ128rmkz + 0U, // VSUBPDZ128rr + 0U, // VSUBPDZ128rrk + 0U, // VSUBPDZ128rrkz + 0U, // VSUBPDZ256rm + 0U, // VSUBPDZ256rmb + 0U, // VSUBPDZ256rmbk + 0U, // VSUBPDZ256rmbkz + 0U, // VSUBPDZ256rmk + 0U, // VSUBPDZ256rmkz + 0U, // VSUBPDZ256rr + 0U, // VSUBPDZ256rrk + 0U, // VSUBPDZ256rrkz + 0U, // VSUBPDZrm + 0U, // VSUBPDZrmb + 0U, // VSUBPDZrmbk + 0U, // VSUBPDZrmbkz + 0U, // VSUBPDZrmk + 0U, // VSUBPDZrmkz + 0U, // VSUBPDZrr + 0U, // VSUBPDZrrb + 0U, // VSUBPDZrrbk + 0U, // VSUBPDZrrbkz + 0U, // VSUBPDZrrk + 0U, // VSUBPDZrrkz + 0U, // VSUBPDrm + 0U, // VSUBPDrr + 0U, // VSUBPSYrm + 0U, // VSUBPSYrr + 0U, // VSUBPSZ128rm + 0U, // VSUBPSZ128rmb + 0U, // VSUBPSZ128rmbk + 0U, // VSUBPSZ128rmbkz + 0U, // VSUBPSZ128rmk + 0U, // VSUBPSZ128rmkz + 0U, // VSUBPSZ128rr + 0U, // VSUBPSZ128rrk + 0U, // VSUBPSZ128rrkz + 0U, // VSUBPSZ256rm + 0U, // VSUBPSZ256rmb + 0U, // VSUBPSZ256rmbk + 0U, // VSUBPSZ256rmbkz + 0U, // VSUBPSZ256rmk + 0U, // VSUBPSZ256rmkz + 0U, // VSUBPSZ256rr + 0U, // VSUBPSZ256rrk + 0U, // VSUBPSZ256rrkz + 0U, // VSUBPSZrm + 0U, // VSUBPSZrmb + 0U, // VSUBPSZrmbk + 0U, // VSUBPSZrmbkz + 0U, // VSUBPSZrmk + 0U, // VSUBPSZrmkz + 0U, // VSUBPSZrr + 0U, // VSUBPSZrrb + 0U, // VSUBPSZrrbk + 0U, // VSUBPSZrrbkz + 0U, // VSUBPSZrrk + 0U, // VSUBPSZrrkz + 0U, // VSUBPSrm + 0U, // VSUBPSrr + 0U, // VSUBSDZrm + 0U, // VSUBSDZrm_Int + 0U, // VSUBSDZrm_Intk + 0U, // VSUBSDZrm_Intkz + 0U, // VSUBSDZrr + 0U, // VSUBSDZrr_Int + 0U, // VSUBSDZrr_Intk + 0U, // VSUBSDZrr_Intkz + 0U, // VSUBSDZrrb_Int + 0U, // VSUBSDZrrb_Intk + 0U, // VSUBSDZrrb_Intkz + 0U, // VSUBSDrm + 0U, // VSUBSDrm_Int + 0U, // VSUBSDrr + 0U, // VSUBSDrr_Int + 0U, // VSUBSSZrm + 0U, // VSUBSSZrm_Int + 0U, // VSUBSSZrm_Intk + 0U, // VSUBSSZrm_Intkz + 0U, // VSUBSSZrr + 0U, // VSUBSSZrr_Int + 0U, // VSUBSSZrr_Intk + 0U, // VSUBSSZrr_Intkz + 0U, // VSUBSSZrrb_Int + 0U, // VSUBSSZrrb_Intk + 0U, // VSUBSSZrrb_Intkz + 0U, // VSUBSSrm + 0U, // VSUBSSrm_Int + 0U, // VSUBSSrr + 0U, // VSUBSSrr_Int + 0U, // VTESTPDYrm + 0U, // VTESTPDYrr + 0U, // VTESTPDrm + 0U, // VTESTPDrr + 0U, // VTESTPSYrm + 0U, // VTESTPSYrr + 0U, // VTESTPSrm + 0U, // VTESTPSrr + 0U, // VUCOMISDZrm + 0U, // VUCOMISDZrm_Int + 0U, // VUCOMISDZrr + 0U, // VUCOMISDZrr_Int + 0U, // VUCOMISDZrrb + 0U, // VUCOMISDrm + 0U, // VUCOMISDrm_Int + 0U, // VUCOMISDrr + 0U, // VUCOMISDrr_Int + 0U, // VUCOMISSZrm + 0U, // VUCOMISSZrm_Int + 0U, // VUCOMISSZrr + 0U, // VUCOMISSZrr_Int + 0U, // VUCOMISSZrrb + 0U, // VUCOMISSrm + 0U, // VUCOMISSrm_Int + 0U, // VUCOMISSrr + 0U, // VUCOMISSrr_Int + 0U, // VUNPCKHPDYrm + 0U, // VUNPCKHPDYrr + 0U, // VUNPCKHPDZ128rm + 0U, // VUNPCKHPDZ128rmb + 0U, // VUNPCKHPDZ128rmbk + 0U, // VUNPCKHPDZ128rmbkz + 0U, // VUNPCKHPDZ128rmk + 0U, // VUNPCKHPDZ128rmkz + 0U, // VUNPCKHPDZ128rr + 0U, // VUNPCKHPDZ128rrk + 0U, // VUNPCKHPDZ128rrkz + 0U, // VUNPCKHPDZ256rm + 0U, // VUNPCKHPDZ256rmb + 0U, // VUNPCKHPDZ256rmbk + 0U, // VUNPCKHPDZ256rmbkz + 0U, // VUNPCKHPDZ256rmk + 0U, // VUNPCKHPDZ256rmkz + 0U, // VUNPCKHPDZ256rr + 0U, // VUNPCKHPDZ256rrk + 0U, // VUNPCKHPDZ256rrkz + 0U, // VUNPCKHPDZrm + 0U, // VUNPCKHPDZrmb + 0U, // VUNPCKHPDZrmbk + 0U, // VUNPCKHPDZrmbkz + 0U, // VUNPCKHPDZrmk + 0U, // VUNPCKHPDZrmkz + 0U, // VUNPCKHPDZrr + 0U, // VUNPCKHPDZrrk + 0U, // VUNPCKHPDZrrkz + 0U, // VUNPCKHPDrm + 0U, // VUNPCKHPDrr + 0U, // VUNPCKHPSYrm + 0U, // VUNPCKHPSYrr + 0U, // VUNPCKHPSZ128rm + 0U, // VUNPCKHPSZ128rmb + 0U, // VUNPCKHPSZ128rmbk + 0U, // VUNPCKHPSZ128rmbkz + 0U, // VUNPCKHPSZ128rmk + 0U, // VUNPCKHPSZ128rmkz + 0U, // VUNPCKHPSZ128rr + 0U, // VUNPCKHPSZ128rrk + 0U, // VUNPCKHPSZ128rrkz + 0U, // VUNPCKHPSZ256rm + 0U, // VUNPCKHPSZ256rmb + 0U, // VUNPCKHPSZ256rmbk + 0U, // VUNPCKHPSZ256rmbkz + 0U, // VUNPCKHPSZ256rmk + 0U, // VUNPCKHPSZ256rmkz + 0U, // VUNPCKHPSZ256rr + 0U, // VUNPCKHPSZ256rrk + 0U, // VUNPCKHPSZ256rrkz + 0U, // VUNPCKHPSZrm + 0U, // VUNPCKHPSZrmb + 0U, // VUNPCKHPSZrmbk + 0U, // VUNPCKHPSZrmbkz + 0U, // VUNPCKHPSZrmk + 0U, // VUNPCKHPSZrmkz + 0U, // VUNPCKHPSZrr + 0U, // VUNPCKHPSZrrk + 0U, // VUNPCKHPSZrrkz + 0U, // VUNPCKHPSrm + 0U, // VUNPCKHPSrr + 0U, // VUNPCKLPDYrm + 0U, // VUNPCKLPDYrr + 0U, // VUNPCKLPDZ128rm + 0U, // VUNPCKLPDZ128rmb + 0U, // VUNPCKLPDZ128rmbk + 0U, // VUNPCKLPDZ128rmbkz + 0U, // VUNPCKLPDZ128rmk + 0U, // VUNPCKLPDZ128rmkz + 0U, // VUNPCKLPDZ128rr + 0U, // VUNPCKLPDZ128rrk + 0U, // VUNPCKLPDZ128rrkz + 0U, // VUNPCKLPDZ256rm + 0U, // VUNPCKLPDZ256rmb + 0U, // VUNPCKLPDZ256rmbk + 0U, // VUNPCKLPDZ256rmbkz + 0U, // VUNPCKLPDZ256rmk + 0U, // VUNPCKLPDZ256rmkz + 0U, // VUNPCKLPDZ256rr + 0U, // VUNPCKLPDZ256rrk + 0U, // VUNPCKLPDZ256rrkz + 0U, // VUNPCKLPDZrm + 0U, // VUNPCKLPDZrmb + 0U, // VUNPCKLPDZrmbk + 0U, // VUNPCKLPDZrmbkz + 0U, // VUNPCKLPDZrmk + 0U, // VUNPCKLPDZrmkz + 0U, // VUNPCKLPDZrr + 0U, // VUNPCKLPDZrrk + 0U, // VUNPCKLPDZrrkz + 0U, // VUNPCKLPDrm + 0U, // VUNPCKLPDrr + 0U, // VUNPCKLPSYrm + 0U, // VUNPCKLPSYrr + 0U, // VUNPCKLPSZ128rm + 0U, // VUNPCKLPSZ128rmb + 0U, // VUNPCKLPSZ128rmbk + 0U, // VUNPCKLPSZ128rmbkz + 0U, // VUNPCKLPSZ128rmk + 0U, // VUNPCKLPSZ128rmkz + 0U, // VUNPCKLPSZ128rr + 0U, // VUNPCKLPSZ128rrk + 0U, // VUNPCKLPSZ128rrkz + 0U, // VUNPCKLPSZ256rm + 0U, // VUNPCKLPSZ256rmb + 0U, // VUNPCKLPSZ256rmbk + 0U, // VUNPCKLPSZ256rmbkz + 0U, // VUNPCKLPSZ256rmk + 0U, // VUNPCKLPSZ256rmkz + 0U, // VUNPCKLPSZ256rr + 0U, // VUNPCKLPSZ256rrk + 0U, // VUNPCKLPSZ256rrkz + 0U, // VUNPCKLPSZrm + 0U, // VUNPCKLPSZrmb + 0U, // VUNPCKLPSZrmbk + 0U, // VUNPCKLPSZrmbkz + 0U, // VUNPCKLPSZrmk + 0U, // VUNPCKLPSZrmkz + 0U, // VUNPCKLPSZrr + 0U, // VUNPCKLPSZrrk + 0U, // VUNPCKLPSZrrkz + 0U, // VUNPCKLPSrm + 0U, // VUNPCKLPSrr + 0U, // VXORPDYrm + 0U, // VXORPDYrr + 0U, // VXORPDZ128rm + 0U, // VXORPDZ128rmb + 0U, // VXORPDZ128rmbk + 0U, // VXORPDZ128rmbkz + 0U, // VXORPDZ128rmk + 0U, // VXORPDZ128rmkz + 0U, // VXORPDZ128rr + 0U, // VXORPDZ128rrk + 0U, // VXORPDZ128rrkz + 0U, // VXORPDZ256rm + 0U, // VXORPDZ256rmb + 0U, // VXORPDZ256rmbk + 0U, // VXORPDZ256rmbkz + 0U, // VXORPDZ256rmk + 0U, // VXORPDZ256rmkz + 0U, // VXORPDZ256rr + 0U, // VXORPDZ256rrk + 0U, // VXORPDZ256rrkz + 0U, // VXORPDZrm + 0U, // VXORPDZrmb + 0U, // VXORPDZrmbk + 0U, // VXORPDZrmbkz + 0U, // VXORPDZrmk + 0U, // VXORPDZrmkz + 0U, // VXORPDZrr + 0U, // VXORPDZrrk + 0U, // VXORPDZrrkz + 0U, // VXORPDrm + 0U, // VXORPDrr + 0U, // VXORPSYrm + 0U, // VXORPSYrr + 0U, // VXORPSZ128rm + 0U, // VXORPSZ128rmb + 0U, // VXORPSZ128rmbk + 0U, // VXORPSZ128rmbkz + 0U, // VXORPSZ128rmk + 0U, // VXORPSZ128rmkz + 0U, // VXORPSZ128rr + 0U, // VXORPSZ128rrk + 0U, // VXORPSZ128rrkz + 0U, // VXORPSZ256rm + 0U, // VXORPSZ256rmb + 0U, // VXORPSZ256rmbk + 0U, // VXORPSZ256rmbkz + 0U, // VXORPSZ256rmk + 0U, // VXORPSZ256rmkz + 0U, // VXORPSZ256rr + 0U, // VXORPSZ256rrk + 0U, // VXORPSZ256rrkz + 0U, // VXORPSZrm + 0U, // VXORPSZrmb + 0U, // VXORPSZrmbk + 0U, // VXORPSZrmbkz + 0U, // VXORPSZrmk + 0U, // VXORPSZrmkz + 0U, // VXORPSZrr + 0U, // VXORPSZrrk + 0U, // VXORPSZrrkz + 0U, // VXORPSrm + 0U, // VXORPSrr + 0U, // VZEROALL + 0U, // VZEROUPPER + 0U, // WAIT + 0U, // WBINVD + 0U, // WBNOINVD + 0U, // WRFSBASE + 0U, // WRFSBASE64 + 0U, // WRGSBASE + 0U, // WRGSBASE64 + 0U, // WRMSR + 0U, // WRPKRUr + 0U, // WRSSD + 0U, // WRSSQ + 0U, // WRUSSD + 0U, // WRUSSQ + 0U, // XABORT + 0U, // XACQUIRE_PREFIX + 0U, // XADD16rm + 0U, // XADD16rr + 0U, // XADD32rm + 0U, // XADD32rr + 0U, // XADD64rm + 0U, // XADD64rr + 0U, // XADD8rm + 0U, // XADD8rr + 0U, // XBEGIN_2 + 0U, // XBEGIN_4 + 0U, // XCHG16ar + 0U, // XCHG16rm + 0U, // XCHG16rr + 0U, // XCHG32ar + 0U, // XCHG32rm + 0U, // XCHG32rr + 0U, // XCHG64ar + 0U, // XCHG64rm + 0U, // XCHG64rr + 0U, // XCHG8rm + 0U, // XCHG8rr + 0U, // XCH_F + 0U, // XCRYPTCBC + 0U, // XCRYPTCFB + 0U, // XCRYPTCTR + 0U, // XCRYPTECB + 0U, // XCRYPTOFB + 0U, // XEND + 0U, // XGETBV + 0U, // XLAT + 0U, // XOR16i16 + 0U, // XOR16mi + 0U, // XOR16mi8 + 0U, // XOR16mr + 0U, // XOR16ri + 0U, // XOR16ri8 + 0U, // XOR16rm + 0U, // XOR16rr + 0U, // XOR16rr_REV + 0U, // XOR32i32 + 0U, // XOR32mi + 0U, // XOR32mi8 + 0U, // XOR32mr + 0U, // XOR32ri + 0U, // XOR32ri8 + 0U, // XOR32rm + 0U, // XOR32rr + 0U, // XOR32rr_REV + 0U, // XOR64i32 + 0U, // XOR64mi32 + 0U, // XOR64mi8 + 0U, // XOR64mr + 0U, // XOR64ri32 + 0U, // XOR64ri8 + 0U, // XOR64rm + 0U, // XOR64rr + 0U, // XOR64rr_REV + 0U, // XOR8i8 + 0U, // XOR8mi + 0U, // XOR8mi8 + 0U, // XOR8mr + 0U, // XOR8ri + 0U, // XOR8ri8 + 0U, // XOR8rm + 0U, // XOR8rr + 0U, // XOR8rr_REV + 0U, // XORPDrm + 0U, // XORPDrr + 0U, // XORPSrm + 0U, // XORPSrr + 0U, // XRELEASE_PREFIX + 0U, // XRSTOR + 0U, // XRSTOR64 + 0U, // XRSTORS + 0U, // XRSTORS64 + 0U, // XSAVE + 0U, // XSAVE64 + 0U, // XSAVEC + 0U, // XSAVEC64 + 0U, // XSAVEOPT + 0U, // XSAVEOPT64 + 0U, // XSAVES + 0U, // XSAVES64 + 0U, // XSETBV + 0U, // XSHA1 + 0U, // XSHA256 + 0U, // XSTORE + 0U, // XTEST + }; + + unsigned int opcode = MCInst_getOpcode(MI); + // printf("opcode = %u\n", opcode); + + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[opcode] << 0; + Bits |= (uint64_t)OpInfo1[opcode] << 32; + Bits |= (uint64_t)OpInfo2[opcode] << 48; + SStream_concat0(O, AsmStrs+(Bits & 16383)-1); + + + // Fragment 0 encoded into 7 bits for 103 unique commands. + // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 14) & 127)); + switch ((uint32_t)((Bits >> 14) & 127)) { + default: // unreachable + case 0: + // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... + return; + break; + case 1: + // AAD8i8, AAM8i8, ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i... + printOperand(MI, 0, O); + break; + case 2: + // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC... + printOperand(MI, 5, O); + SStream_concat0(O, ", "); + break; + case 3: + // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A... + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 4: + // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r... + printi16mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 5: + // ADC32rm, ADCX32rm, ADD32rm, ADOX32rm, AND32rm, ANDN32rm, CMOVA32rm, CM... + printi32mem(MI, 2, O); + break; + case 6: + // ADC64rm, ADCX64rm, ADD64rm, ADOX64rm, AND64rm, ANDN64rm, CMOVA64rm, CM... + printi64mem(MI, 2, O); + break; + case 7: + // ADC8rm, ADD8rm, AND8rm, CRC32r32m8, CRC32r64m8, OR8rm, SBB8rm, SUB8rm,... + printi8mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 8: + // ADDPDrm, ADDPSrm, ADDSUBPDrm, ADDSUBPSrm, ANDNPDrm, ANDNPSrm, ANDPDrm,... + printf128mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 9: + // ADDSDrm, ADDSDrm_Int, CVTSD2SSrm_Int, DIVSDrm, DIVSDrm_Int, MAXCSDrm, ... + printf64mem(MI, 2, O); + break; + case 10: + // ADDSSrm, ADDSSrm_Int, CVTSS2SDrm_Int, DIVSSrm, DIVSSrm_Int, MAXCSSrm, ... + printf32mem(MI, 2, O); + break; + case 11: + // ADD_F32m, DIVR_F32m, DIV_F32m, FCOM32m, FCOMP32m, FLDENVm, FRSTORm, FS... + printf32mem(MI, 0, O); + return; + break; + case 12: + // ADD_F64m, DIVR_F64m, DIV_F64m, FCOM64m, FCOMP64m, LD_F64m, MUL_F64m, S... + printf64mem(MI, 0, O); + return; + break; + case 13: + // ADD_FI16m, CALL16m, CALL16m_NT, DEC16m, DIV16m, DIVR_FI16m, DIV_FI16m,... + printi16mem(MI, 0, O); + return; + break; + case 14: + // ADD_FI32m, CALL32m, CALL32m_NT, CLRSSBSY, DEC32m, DIV32m, DIVR_FI32m, ... + printi32mem(MI, 0, O); + return; + break; + case 15: + // AESDECLASTrm, AESDECrm, AESENCLASTrm, AESENCrm, GF2P8MULBrm, PACKSSDWr... + printi128mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 16: + // AESIMCrm, BNDMOV64rm, CVTDQ2PSrm, INVEPT32, INVEPT64, INVPCID32, INVPC... + printi128mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 17: + // AESIMCrr, ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI64rr, BLCI... + printOperand(MI, 1, O); + break; + case 18: + // AESKEYGENASSIST128rm, EXTRACTPSmr, MMX_PSHUFWmi, PCMPESTRIrm, PCMPESTR... + printU8Imm(MI, 6, O); + SStream_concat0(O, ", "); + break; + case 19: + // AESKEYGENASSIST128rr, EXTRACTPSrr, KSHIFTLBri, KSHIFTLDri, KSHIFTLQri,... + printU8Imm(MI, 2, O); + break; + case 20: + // BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZHI32rm, BZHI64rm, IMUL... + printOperand(MI, 6, O); + SStream_concat0(O, ", "); + break; + case 21: + // BLCFILL32rm, BLCI32rm, BLCIC32rm, BLCMSK32rm, BLCS32rm, BLSFILL32rm, B... + printi32mem(MI, 1, O); + break; + case 22: + // BLCFILL64rm, BLCI64rm, BLCIC64rm, BLCMSK64rm, BLCS64rm, BLSFILL64rm, B... + printi64mem(MI, 1, O); + break; + case 23: + // BLENDPDrmi, BLENDPSrmi, CMPPDrmi_alt, CMPPSrmi_alt, CMPSDrm_alt, CMPSS... + printU8Imm(MI, 7, O); + SStream_concat0(O, ", "); + break; + case 24: + // BLENDPDrri, BLENDPSrri, CMPPDrri_alt, CMPPSrri_alt, CMPSDrr_alt, CMPSS... + printU8Imm(MI, 3, O); + break; + case 25: + // BNDCL32rm, BNDCL64rm, BNDCN32rm, BNDCN64rm, BNDCU32rm, BNDCU64rm, BNDL... + printanymem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 26: + // BSF16rm, BSR16rm, CMP16rm, KMOVWkm, LAR16rm, LAR32rm, LAR64rm, LSL16rm... + printi16mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 27: + // CALL64m, CALL64m_NT, CMPXCHG8B, DEC64m, DIV64m, IDIV64m, ILD_F64m, IMU... + printi64mem(MI, 0, O); + return; + break; + case 28: + // CALL64pcrel32, CALLpcrel16, CALLpcrel32, JAE_1, JAE_2, JAE_4, JA_1, JA... + printPCRelImm(MI, 0, O); + return; + break; + case 29: + // CLDEMOTE, CLFLUSH, CLFLUSHOPT, CLWB, DEC8m, DIV8m, IDIV8m, IMUL8m, INC... + printi8mem(MI, 0, O); + return; + break; + case 30: + // CMP8rm, KMOVBkm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX32... + printi8mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 31: + // CMPPDrmi, CMPPSrmi, CMPSDrm, CMPSDrm_Int, CMPSSrm, CMPSSrm_Int, VCMPPD... + printSSEAVXCC(MI, 7, O); + break; + case 32: + // CMPPDrri, CMPPSrri, CMPSDrr, CMPSDrr_Int, CMPSSrr, CMPSSrr_Int, VCMPPD... + printSSEAVXCC(MI, 3, O); + break; + case 33: + // CMPSB, INSB, SCASB, STOSB + printDstIdx8(MI, 0, O); + break; + case 34: + // CMPSL, INSL, SCASL, STOSL + printDstIdx32(MI, 0, O); + break; + case 35: + // CMPSQ, SCASQ, STOSQ + printDstIdx64(MI, 0, O); + break; + case 36: + // CMPSW, INSW, SCASW, STOSW + printDstIdx16(MI, 0, O); + break; + case 37: + // CMPXCHG16B + printi128mem(MI, 0, O); + return; + break; + case 38: + // COMISDrm, COMISDrm_Int, CVTPS2PDrm, CVTSD2SI64rm_Int, CVTSD2SIrm_Int, ... + printf64mem(MI, 1, O); + break; + case 39: + // COMISSrm, COMISSrm_Int, CVTSS2SDrm, CVTSS2SI64rm_Int, CVTSS2SIrm_Int, ... + printf32mem(MI, 1, O); + break; + case 40: + // CVTPD2DQrm, CVTPD2PSrm, CVTPS2DQrm, CVTTPD2DQrm, CVTTPS2DQrm, MMX_CVTP... + printf128mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 41: + // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, FXR... + printopaquemem(MI, 0, O); + return; + break; + case 42: + // FBLDm, FBSTPm, LD_F80m, ST_FP80m + printf80mem(MI, 0, O); + return; + break; + case 43: + // IN16ri, IN32ri, IN8ri, INT, OUT16ir, OUT32ir, OUT8ir + printU8Imm(MI, 0, O); + break; + case 44: + // INSERTQI, VALIGNDZ128rrikz, VALIGNDZ256rrikz, VALIGNDZrrikz, VALIGNQZ1... + printU8Imm(MI, 4, O); + break; + case 45: + // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm... + printopaquemem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 46: + // LODSB, OUTSB + printSrcIdx8(MI, 0, O); + break; + case 47: + // LODSL, OUTSL + printSrcIdx32(MI, 0, O); + break; + case 48: + // LODSQ + printSrcIdx64(MI, 0, O); + SStream_concat0(O, ", %rax"); + op_addReg(MI, X86_REG_RAX); + return; + break; + case 49: + // LODSW, OUTSW + printSrcIdx16(MI, 0, O); + break; + case 50: + // MOV16ao16, MOV16ao32, MOV16ao64, MOV16o16a, MOV16o32a, MOV16o64a + printMemOffs16(MI, 0, O); + break; + case 51: + // MOV32ao16, MOV32ao32, MOV32ao64, MOV32o16a, MOV32o32a, MOV32o64a + printMemOffs32(MI, 0, O); + break; + case 52: + // MOV64ao32, MOV64ao64, MOV64o32a, MOV64o64a + printMemOffs64(MI, 0, O); + break; + case 53: + // MOV8ao16, MOV8ao32, MOV8ao64, MOV8o16a, MOV8o32a, MOV8o64a + printMemOffs8(MI, 0, O); + break; + case 54: + // MOVDIR64B16, MOVDIR64B32, MOVDIR64B64, VCVTDQ2PSZrm, VCVTQQ2PDZrm, VCV... + printi512mem(MI, 1, O); + break; + case 55: + // MOVSB + printSrcIdx8(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx8(MI, 0, O); + return; + break; + case 56: + // MOVSL + printSrcIdx32(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx32(MI, 0, O); + return; + break; + case 57: + // MOVSQ + printSrcIdx64(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx64(MI, 0, O); + return; + break; + case 58: + // MOVSW + printSrcIdx16(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx16(MI, 0, O); + return; + break; + case 59: + // RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi, ... + printU8Imm(MI, 5, O); + break; + case 60: + // V4FMADDPSrm, V4FMADDSSrm, V4FNMADDPSrm, V4FNMADDSSrm, VADDPDZ128rmkz, ... + printf128mem(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 61: + // V4FMADDPSrmk, V4FMADDPSrmkz, V4FMADDSSrmk, V4FMADDSSrmkz, V4FNMADDPSrm... + printf128mem(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + break; + case 62: + // VADDPDYrm, VADDPDZ256rm, VADDPSYrm, VADDPSZ256rm, VADDSUBPDYrm, VADDSU... + printf256mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 63: + // VADDPDZ128rmbk, VADDPDZ256rmbk, VADDPDZrmbk, VADDSDZrm_Intk, VANDNPDZ1... + printf64mem(MI, 4, O); + break; + case 64: + // VADDPDZ128rmbkz, VADDPDZ256rmbkz, VADDPDZrmbkz, VADDSDZrm_Intkz, VANDN... + printf64mem(MI, 3, O); + break; + case 65: + // VADDPDZ128rrk, VADDPDZ256rrk, VADDPDZrrk, VADDPSZ128rrk, VADDPSZ256rrk... + printOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + break; + case 66: + // VADDPDZ128rrkz, VADDPDZ256rrkz, VADDPDZrrkz, VADDPSZ128rrkz, VADDPSZ25... + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 67: + // VADDPDZ256rmk, VADDPSZ256rmk, VANDNPDZ256rmk, VANDNPSZ256rmk, VANDPDZ2... + printf256mem(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + break; + case 68: + // VADDPDZ256rmkz, VADDPSZ256rmkz, VANDNPDZ256rmkz, VANDNPSZ256rmkz, VAND... + printf256mem(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 69: + // VADDPDZrm, VADDPSZrm, VANDNPDZrm, VANDNPSZrm, VANDPDZrm, VANDPSZrm, VB... + printf512mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 70: + // VADDPDZrmk, VADDPSZrmk, VANDNPDZrmk, VANDNPSZrmk, VANDPDZrmk, VANDPSZr... + printf512mem(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + break; + case 71: + // VADDPDZrmkz, VADDPSZrmkz, VANDNPDZrmkz, VANDNPSZrmkz, VANDPDZrmkz, VAN... + printf512mem(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 72: + // VADDPDZrrb, VADDPSZrrb, VADDSDZrrb_Int, VADDSSZrrb_Int, VCVTDQ2PSZrrbk... + printRoundingControl(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 73: + // VADDPDZrrbk, VADDPSZrrbk, VADDSDZrrb_Intk, VADDSSZrrb_Intk, VCVTSD2SSZ... + printRoundingControl(MI, 5, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + break; + case 74: + // VADDPDZrrbkz, VADDPSZrrbkz, VADDSDZrrb_Intkz, VADDSSZrrb_Intkz, VCVTDQ... + printRoundingControl(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 75: + // VADDPSZ128rmbk, VADDPSZ256rmbk, VADDPSZrmbk, VADDSSZrm_Intk, VANDNPSZ1... + printf32mem(MI, 4, O); + break; + case 76: + // VADDPSZ128rmbkz, VADDPSZ256rmbkz, VADDPSZrmbkz, VADDSSZrm_Intkz, VANDN... + printf32mem(MI, 3, O); + break; + case 77: + // VAESDECLASTYrm, VAESDECLASTZ256rm, VAESDECYrm, VAESDECZ256rm, VAESENCL... + printi256mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 78: + // VAESDECLASTZrm, VAESDECZrm, VAESENCLASTZrm, VAESENCZrm, VCVTDQ2PSZrmkz... + printi512mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 79: + // VALIGNDZ128rmbik, VALIGNDZ128rmik, VALIGNDZ256rmbik, VALIGNDZ256rmik, ... + printU8Imm(MI, 9, O); + SStream_concat0(O, ", "); + break; + case 80: + // VALIGNDZ128rmbikz, VALIGNDZ128rmikz, VALIGNDZ256rmbikz, VALIGNDZ256rmi... + printU8Imm(MI, 8, O); + SStream_concat0(O, ", "); + break; + case 81: + // VBLENDVPDYrm, VBLENDVPDrm, VBLENDVPSYrm, VBLENDVPSrm, VFMADDPD4Ymr, VF... + printOperand(MI, 7, O); + SStream_concat0(O, ", "); + break; + case 82: + // VBROADCASTF32X8rm, VBROADCASTF64X4rm, VCVTPD2DQYrm, VCVTPD2DQZ256rm, V... + printf256mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 83: + // VBROADCASTI32X2Z128mk, VBROADCASTI32X2Z256mk, VBROADCASTI32X2Zmk, VCVT... + printi64mem(MI, 3, O); + break; + case 84: + // VBROADCASTI32X4Z256rmk, VBROADCASTI32X4rmk, VBROADCASTI64X2Z128rmk, VB... + printi128mem(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 85: + // VBROADCASTI32X8rm, VBROADCASTI64X4rm, VCVTDQ2PDZrm, VCVTDQ2PSYrm, VCVT... + printi256mem(MI, 1, O); + break; + case 86: + // VBROADCASTI32X8rmk, VBROADCASTI64X4rmk, VCVTDQ2PDZrmk, VCVTDQ2PSZ256rm... + printi256mem(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 87: + // VCMPPDZ128rmbik, VCMPPDZ128rmik, VCMPPDZ256rmbik, VCMPPDZ256rmik, VCMP... + printSSEAVXCC(MI, 8, O); + break; + case 88: + // VCMPPDZ128rrik, VCMPPDZ256rrik, VCMPPDZrribk, VCMPPDZrrik, VCMPPSZ128r... + printSSEAVXCC(MI, 4, O); + break; + case 89: + // VCVTDQ2PDZ128rmbk, VCVTDQ2PDZ256rmbk, VCVTDQ2PDZrmbk, VCVTDQ2PSZ128rmb... + printi32mem(MI, 3, O); + break; + case 90: + // VCVTDQ2PSZrmk, VCVTQQ2PDZrmk, VCVTQQ2PSZrmk, VCVTUDQ2PSZrmk, VCVTUQQ2P... + printi512mem(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 91: + // VCVTDQ2PSZrrb, VCVTPD2DQZrrb, VCVTPD2PSZrrb, VCVTPD2QQZrrb, VCVTPD2UDQ... + printRoundingControl(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 92: + // VCVTPD2DQZrm, VCVTPD2PSZrm, VCVTPD2QQZrm, VCVTPD2UDQZrm, VCVTPD2UQQZrm... + printf512mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 93: + // VGATHERDPDYrm, VGATHERDPDrm, VGATHERDPSYrm, VGATHERDPSrm, VGATHERQPDYr... + printOperand(MI, 8, O); + SStream_concat0(O, ", "); + break; + case 94: + // VGATHERDPDZ128rm, VGATHERDPSZ128rm, VGATHERQPDZ128rm, VGATHERQPSZ256rm... + printi128mem(MI, 4, O); + SStream_concat0(O, ", "); + break; + case 95: + // VGATHERDPDZ256rm, VGATHERDPSZ256rm, VGATHERQPDZ256rm, VGATHERQPSZrm, V... + printi256mem(MI, 4, O); + SStream_concat0(O, ", "); + break; + case 96: + // VGATHERDPDZrm, VGATHERDPSZrm, VGATHERQPDZrm, VGF2P8MULBZrmk, VPACKSSDW... + printi512mem(MI, 4, O); + SStream_concat0(O, ", "); + break; + case 97: + // VGATHERQPSZ128rm, VPADDQZ128rmbk, VPADDQZ256rmbk, VPADDQZrmbk, VPANDNQ... + printi64mem(MI, 4, O); + break; + case 98: + // VPACKSSDWZ128rmbk, VPACKSSDWZ256rmbk, VPACKSSDWZrmbk, VPACKUSDWZ128rmb... + printi32mem(MI, 4, O); + break; + case 99: + // VPBROADCASTBZ128mk, VPBROADCASTBZ256mk, VPBROADCASTBZmk + printi8mem(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + SStream_concat0(O, "}"); + return; + break; + case 100: + // VPBROADCASTWZ128mk, VPBROADCASTWZ256mk, VPBROADCASTWZmk, VPMOVSXBQZ128... + printi16mem(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + SStream_concat0(O, "}"); + return; + break; + case 101: + // VPCOMBmi, VPCOMDmi, VPCOMQmi, VPCOMUBmi, VPCOMUDmi, VPCOMUQmi, VPCOMUW... + printXOPCC(MI, 7, O); + break; + case 102: + // VPCOMBri, VPCOMDri, VPCOMQri, VPCOMUBri, VPCOMUDri, VPCOMUQri, VPCOMUW... + printXOPCC(MI, 3, O); + break; + } + + + // Fragment 1 encoded into 7 bits for 99 unique commands. + // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 21) & 127)); + switch ((uint32_t)((Bits >> 21) & 127)) { + default: // unreachable + case 0: + // AAD8i8, AAM8i8, ADD_FPrST0, ADD_FST0r, ADD_FrST0, BSWAP16r_BAD, BSWAP3... + return; + break; + case 1: + // ADC16i16, ADD16i16, AND16i16, CMP16i16, IN16ri, LODSW, MOV16ao16, MOV1... + SStream_concat0(O, ", %ax"); + op_addReg(MI, X86_REG_AX); + return; + break; + case 2: + // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, AND16mi, AND16... + printi16mem(MI, 0, O); + break; + case 3: + // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rr, ADC64... + printOperand(MI, 1, O); + break; + case 4: + // ADC16rr_REV, ADC32rr_REV, ADC64rr_REV, ADC8rr_REV, ADCX32rr, ADCX64rr,... + printOperand(MI, 0, O); + break; + case 5: + // ADC32i32, ADD32i32, AND32i32, CMP32i32, IN32ri, LODSL, MOV32ao16, MOV3... + SStream_concat0(O, ", %eax"); + op_addReg(MI, X86_REG_EAX); + return; + break; + case 6: + // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, AND32mi, AND32... + printi32mem(MI, 0, O); + break; + case 7: + // ADC32rm, ADC64rm, ADCX32rm, ADCX64rm, ADD32rm, ADD64rm, ADDSDrm, ADDSD... + SStream_concat0(O, ", "); + break; + case 8: + // ADC64i32, ADD64i32, AND64i32, CMP64i32, MOV64ao32, MOV64ao64, OR64i32,... + SStream_concat0(O, ", %rax"); + op_addReg(MI, X86_REG_RAX); + return; + break; + case 9: + // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,... + printi64mem(MI, 0, O); + break; + case 10: + // ADC8i8, ADD8i8, AND8i8, CMP8i8, IN8ri, LODSB, MOV8ao16, MOV8ao32, MOV8... + SStream_concat0(O, ", %al"); + op_addReg(MI, X86_REG_AL); + return; + break; + case 11: + // ADC8mi, ADC8mi8, ADC8mr, ADD8mi, ADD8mi8, ADD8mr, AND8mi, AND8mi8, AND... + printi8mem(MI, 0, O); + return; + break; + case 12: + // AESKEYGENASSIST128rm, PCMPESTRIrm, PCMPESTRMrm, PCMPISTRIrm, PCMPISTRM... + printi128mem(MI, 1, O); + break; + case 13: + // BEXTR32rm, BEXTRI32mi, BZHI32rm, IMUL32rmi, IMUL32rmi8, LWPINS32rmi, L... + printi32mem(MI, 1, O); + break; + case 14: + // BEXTR64rm, BEXTRI64mi, BZHI64rm, IMUL64rmi32, IMUL64rmi8, MMX_PSHUFWmi... + printi64mem(MI, 1, O); + break; + case 15: + // BLENDPDrmi, BLENDPSrmi, CMPPDrmi_alt, CMPPSrmi_alt, DPPDrmi, DPPSrmi, ... + printf128mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 16: + // BNDMOV64mr, MOVDQAmr, MOVDQUmr, VMOVDQA32Z128mr, VMOVDQA32Z128mrk, VMO... + printi128mem(MI, 0, O); + break; + case 17: + // BNDSTXmr + printanymem(MI, 0, O); + return; + break; + case 18: + // CMOVBE_F, CMOVB_F, CMOVE_F, CMOVNBE_F, CMOVNB_F, CMOVNE_F, CMOVNP_F, C... + SStream_concat0(O, ", %st(0)"); + op_addReg(MI, X86_REG_ST0); + return; + break; + case 19: + // CMPPDrmi, CMPPDrri, VCMPPDYrmi, VCMPPDYrri, VCMPPDZ128rmbi, VCMPPDZ128... + SStream_concat0(O, "pd\t"); + break; + case 20: + // CMPPSrmi, CMPPSrri, VCMPPSYrmi, VCMPPSYrri, VCMPPSZ128rmbi, VCMPPSZ128... + SStream_concat0(O, "ps\t"); + break; + case 21: + // CMPSDrm, CMPSDrm_Int, CMPSDrr, CMPSDrr_Int, VCMPSDZrm, VCMPSDZrm_Int, ... + SStream_concat0(O, "sd\t"); + break; + case 22: + // CMPSDrm_alt, ROUNDSDm_Int, VCMPPDZ128rmbi_alt, VCMPPDZ256rmbi_alt, VCM... + printf64mem(MI, 2, O); + break; + case 23: + // CMPSSrm, CMPSSrm_Int, CMPSSrr, CMPSSrr_Int, VCMPSSZrm, VCMPSSZrm_Int, ... + SStream_concat0(O, "ss\t"); + break; + case 24: + // CMPSSrm_alt, INSERTPSrm, ROUNDSSm_Int, VCMPPSZ128rmbi_alt, VCMPPSZ256r... + printf32mem(MI, 2, O); + break; + case 25: + // EXTRACTPSmr, PEXTRBmr, PEXTRDmr, PEXTRQmr, PEXTRWmr, SHLD16mri8, SHLD3... + printOperand(MI, 5, O); + SStream_concat0(O, ", "); + break; + case 26: + // FARJMP16i, FARJMP32i + SStream_concat0(O, ":"); + printOperand(MI, 0, O); + return; + break; + case 27: + // GF2P8AFFINEINVQBrmi, GF2P8AFFINEQBrmi, MPSADBWrmi, PALIGNRrmi, PBLENDW... + printi128mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 28: + // IMUL16rmi, IMUL16rmi8 + printi16mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 29: + // MMX_PALIGNRrmi, PINSRQrm, VALIGNQZ128rmbi, VALIGNQZ256rmbi, VALIGNQZrm... + printi64mem(MI, 2, O); + break; + case 30: + // MMX_PINSRWrm, PINSRWrm, VPINSRWZrm, VPINSRWrm + printi16mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 31: + // MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVNTPDmr, MOVNTPSmr, MOVUPDmr, MOVUPSm... + printf128mem(MI, 0, O); + break; + case 32: + // MOVHPDmr, MOVHPSmr, MOVLPDmr, MOVLPSmr, MOVNTSD, MOVSDmr, VMOVHPDZ128m... + printf64mem(MI, 0, O); + break; + case 33: + // MOVNTSS, MOVSSmr, VMOVSSZmr, VMOVSSZmrk, VMOVSSmr + printf32mem(MI, 0, O); + break; + case 34: + // OUTSB, OUTSL, OUTSW + SStream_concat0(O, ", %dx"); + op_addReg(MI, X86_REG_DX); + return; + break; + case 35: + // PINSRBrm, VGF2P8AFFINEINVQBZ128rmbi, VGF2P8AFFINEINVQBZ256rmbi, VGF2P8... + printi8mem(MI, 2, O); + break; + case 36: + // PINSRDrm, VALIGNDZ128rmbi, VALIGNDZ256rmbi, VALIGNDZrmbi, VPCMPDZ128rm... + printi32mem(MI, 2, O); + break; + case 37: + // ROUNDPDm, ROUNDPSm, VFPCLASSPDZ128rm, VFPCLASSPSZ128rm, VGETMANTPDZ128... + printf128mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 38: + // ROUNDSDm, VFPCLASSPDZ128rmb, VFPCLASSPDZ256rmb, VFPCLASSPDZrmb, VFPCLA... + printf64mem(MI, 1, O); + break; + case 39: + // ROUNDSSm, VFPCLASSPSZ128rmb, VFPCLASSPSZ256rmb, VFPCLASSPSZrmb, VFPCLA... + printf32mem(MI, 1, O); + break; + case 40: + // V4FMADDPSrm, V4FMADDSSrm, V4FNMADDPSrm, V4FNMADDSSrm, VADDPDZ128rmkz, ... + printOperand(MI, 2, O); + break; + case 41: + // V4FMADDPSrmk, V4FMADDSSrmk, V4FNMADDPSrmk, V4FNMADDSSrmk, VADDPDZ128rm... + SStream_concat0(O, "}"); + return; + break; + case 42: + // V4FMADDPSrmkz, V4FMADDSSrmkz, V4FNMADDPSrmkz, V4FNMADDSSrmkz, VFMADD13... + SStream_concat0(O, "} {z}"); + op_addAvxZeroOpmask(MI); + return; + break; + case 43: + // VADDPDZ128rmb, VADDPDZ128rmbk, VADDPDZ128rmbkz, VANDNPDZ128rmb, VANDNP... + SStream_concat0(O, "{1to2}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_2); + break; + case 44: + // VADDPDZ256rmb, VADDPDZ256rmbk, VADDPDZ256rmbkz, VADDPSZ128rmb, VADDPSZ... + SStream_concat0(O, "{1to4}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_4); + break; + case 45: + // VADDPDZrmb, VADDPDZrmbk, VADDPDZrmbkz, VADDPSZ256rmb, VADDPSZ256rmbk, ... + SStream_concat0(O, "{1to8}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_8); + break; + case 46: + // VADDPSZrmb, VADDPSZrmbk, VADDPSZrmbkz, VANDNPSZrmb, VANDNPSZrmbk, VAND... + SStream_concat0(O, "{1to16}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_16); + break; + case 47: + // VALIGNDZ128rmbik, VALIGNDZ256rmbik, VALIGNDZrmbik, VPSHLDDZ128rmbik, V... + printi32mem(MI, 4, O); + break; + case 48: + // VALIGNDZ128rmbikz, VALIGNDZ256rmbikz, VALIGNDZrmbikz, VPCMPDZ128rmibk_... + printi32mem(MI, 3, O); + break; + case 49: + // VALIGNDZ128rmik, VALIGNQZ128rmik, VDBPSADBWZ128rmik, VGF2P8AFFINEINVQB... + printi128mem(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + break; + case 50: + // VALIGNDZ128rmikz, VALIGNQZ128rmikz, VDBPSADBWZ128rmikz, VGATHERDPDrm, ... + printi128mem(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 51: + // VALIGNDZ256rmi, VALIGNQZ256rmi, VDBPSADBWZ256rmi, VDPPSYrmi, VGF2P8AFF... + printi256mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 52: + // VALIGNDZ256rmik, VALIGNQZ256rmik, VDBPSADBWZ256rmik, VGF2P8AFFINEINVQB... + printi256mem(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + break; + case 53: + // VALIGNDZ256rmikz, VALIGNQZ256rmikz, VDBPSADBWZ256rmikz, VGATHERDPDYrm,... + printi256mem(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 54: + // VALIGNDZrmi, VALIGNQZrmi, VDBPSADBWZrmi, VGF2P8AFFINEINVQBZrmi, VGF2P8... + printi512mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 55: + // VALIGNDZrmik, VALIGNQZrmik, VDBPSADBWZrmik, VGF2P8AFFINEINVQBZrmik, VG... + printi512mem(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + break; + case 56: + // VALIGNDZrmikz, VALIGNQZrmikz, VDBPSADBWZrmikz, VGF2P8AFFINEINVQBZrmikz... + printi512mem(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 57: + // VALIGNQZ128rmbik, VALIGNQZ256rmbik, VALIGNQZrmbik, VPSHLDQZ128rmbik, V... + printi64mem(MI, 4, O); + break; + case 58: + // VALIGNQZ128rmbikz, VALIGNQZ256rmbikz, VALIGNQZrmbikz, VGATHERQPSrm, VP... + printi64mem(MI, 3, O); + break; + case 59: + // VBLENDPDYrmi, VBLENDPSYrmi, VBLENDVPDYrm, VBLENDVPSYrm, VCMPPDYrmi_alt... + printf256mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 60: + // VCMPPDZ128rmbi_altk, VCMPPDZ256rmbi_altk, VCMPPDZrmbi_altk, VCMPSDZrmi... + printf64mem(MI, 3, O); + break; + case 61: + // VCMPPDZ128rmi_altk, VCMPPSZ128rmi_altk, VFIXUPIMMPDZ128rmi, VFIXUPIMMP... + printf128mem(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 62: + // VCMPPDZ256rmi_altk, VCMPPSZ256rmi_altk, VFIXUPIMMPDZ256rmi, VFIXUPIMMP... + printf256mem(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 63: + // VCMPPDZrmi_alt, VCMPPSZrmi_alt, VFPCLASSPDZrmk, VFPCLASSPSZrmk, VGETMA... + printf512mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 64: + // VCMPPDZrmi_altk, VCMPPSZrmi_altk, VFIXUPIMMPDZrmi, VFIXUPIMMPSZrmi, VG... + printf512mem(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 65: + // VCMPPDZrrib, VCMPPDZrribk + SStream_concat0(O, "pd\t{sae}, "); + op_addAvxSae(MI); + break; + case 66: + // VCMPPDZrrib_alt, VCMPPDZrrib_altk, VCMPPSZrrib_alt, VCMPPSZrrib_altk, ... + SStream_concat0(O, ", {sae}, "); + op_addAvxSae(MI); + break; + case 67: + // VCMPPSZ128rmbi_altk, VCMPPSZ256rmbi_altk, VCMPPSZrmbi_altk, VCMPSSZrmi... + printf32mem(MI, 3, O); + break; + case 68: + // VCMPPSZrrib, VCMPPSZrribk + SStream_concat0(O, "ps\t{sae}, "); + op_addAvxSae(MI); + break; + case 69: + // VCMPSDZrrb_Int, VCMPSDZrrb_Intk + SStream_concat0(O, "sd\t{sae}, "); + op_addAvxSae(MI); + break; + case 70: + // VCMPSSZrrb_Int, VCMPSSZrrb_Intk + SStream_concat0(O, "ss\t{sae}, "); + op_addAvxSae(MI); + break; + case 71: + // VCOMPRESSPDZ256mr, VCOMPRESSPDZ256mrk, VCOMPRESSPSZ256mr, VCOMPRESSPSZ... + printf256mem(MI, 0, O); + break; + case 72: + // VCOMPRESSPDZmr, VCOMPRESSPDZmrk, VCOMPRESSPSZmr, VCOMPRESSPSZmrk, VMOV... + printf512mem(MI, 0, O); + break; + case 73: + // VCVTPS2PHZ128mrk, VCVTPS2PHZ256mrk, VCVTPS2PHZmrk, VEXTRACTF32x4Z256mr... + printOperand(MI, 6, O); + SStream_concat0(O, ", "); + break; + case 74: + // VCVTSI2SDZrrb_Int, VCVTSI2SSZrrb_Int, VCVTSI642SDZrrb_Int, VCVTSI642SS... + printRoundingControl(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 75: + // VFIXUPIMMPDZ128rmbik, VFIXUPIMMPDZ128rmbikz, VFIXUPIMMPDZ256rmbik, VFI... + printf64mem(MI, 4, O); + break; + case 76: + // VFIXUPIMMPDZ128rmik, VFIXUPIMMPDZ128rmikz, VFIXUPIMMPSZ128rmik, VFIXUP... + printf128mem(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + break; + case 77: + // VFIXUPIMMPDZ256rmik, VFIXUPIMMPDZ256rmikz, VFIXUPIMMPSZ256rmik, VFIXUP... + printf256mem(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + break; + case 78: + // VFIXUPIMMPDZrmik, VFIXUPIMMPDZrmikz, VFIXUPIMMPSZrmik, VFIXUPIMMPSZrmi... + printf512mem(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + break; + case 79: + // VFIXUPIMMPSZ128rmbik, VFIXUPIMMPSZ128rmbikz, VFIXUPIMMPSZ256rmbik, VFI... + printf32mem(MI, 4, O); + break; + case 80: + // VFPCLASSPDZ256rm, VFPCLASSPSZ256rm, VGETMANTPDZ256rmi, VGETMANTPSZ256r... + printf256mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 81: + // VFPCLASSPDZrm, VFPCLASSPSZrm, VGETMANTPDZrmi, VGETMANTPSZrmi, VPERMILP... + printf512mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 82: + // VGATHERPF0DPDm, VGATHERPF0DPSm, VGATHERPF0QPDm, VGATHERPF0QPSm, VGATHE... + SStream_concat0(O, " {"); + printOperand(MI, 0, O); + SStream_concat0(O, "}"); + return; + break; + case 83: + // VGF2P8AFFINEINVQBZ128rmbik, VGF2P8AFFINEINVQBZ256rmbik, VGF2P8AFFINEIN... + printi8mem(MI, 4, O); + break; + case 84: + // VGF2P8AFFINEINVQBZ128rmbikz, VGF2P8AFFINEINVQBZ256rmbikz, VGF2P8AFFINE... + printi8mem(MI, 3, O); + break; + case 85: + // VGF2P8MULBZ128rmk, VGF2P8MULBZ256rmk, VGF2P8MULBZrmk, VPACKSSDWZ128rmk... + printOperand(MI, 3, O); + break; + case 86: + // VMOVDQA32Z256mr, VMOVDQA32Z256mrk, VMOVDQA64Z256mr, VMOVDQA64Z256mrk, ... + printi256mem(MI, 0, O); + break; + case 87: + // VMOVDQA32Zmr, VMOVDQA32Zmrk, VMOVDQA64Zmr, VMOVDQA64Zmrk, VMOVDQU16Zmr... + printi512mem(MI, 0, O); + break; + case 88: + // VPCMPBZ128rmi, VPCMPBZ128rmik, VPCMPBZ128rri, VPCMPBZ128rrik, VPCMPBZ2... + SStream_concat0(O, "b\t"); + break; + case 89: + // VPCMPDZ128rmi, VPCMPDZ128rmib, VPCMPDZ128rmibk, VPCMPDZ128rmik, VPCMPD... + SStream_concat0(O, "d\t"); + break; + case 90: + // VPCMPQZ128rmi, VPCMPQZ128rmib, VPCMPQZ128rmibk, VPCMPQZ128rmik, VPCMPQ... + SStream_concat0(O, "q\t"); + break; + case 91: + // VPCMPUBZ128rmi, VPCMPUBZ128rmik, VPCMPUBZ128rri, VPCMPUBZ128rrik, VPCM... + SStream_concat0(O, "ub\t"); + break; + case 92: + // VPCMPUDZ128rmi, VPCMPUDZ128rmib, VPCMPUDZ128rmibk, VPCMPUDZ128rmik, VP... + SStream_concat0(O, "ud\t"); + break; + case 93: + // VPCMPUQZ128rmi, VPCMPUQZ128rmib, VPCMPUQZ128rmibk, VPCMPUQZ128rmik, VP... + SStream_concat0(O, "uq\t"); + break; + case 94: + // VPCMPUWZ128rmi, VPCMPUWZ128rmik, VPCMPUWZ128rri, VPCMPUWZ128rrik, VPCM... + SStream_concat0(O, "uw\t"); + break; + case 95: + // VPCMPWZ128rmi, VPCMPWZ128rmik, VPCMPWZ128rri, VPCMPWZ128rrik, VPCMPWZ2... + SStream_concat0(O, "w\t"); + break; + case 96: + // VPERMIL2PDYmr, VPERMIL2PDmr, VPERMIL2PSYmr, VPERMIL2PSmr + printOperand(MI, 7, O); + SStream_concat0(O, ", "); + break; + case 97: + // VPERMQYmi, VPERMQZ256mi, VPROLDZ256mi, VPROLQZ256mi, VPRORDZ256mi, VPR... + printi256mem(MI, 1, O); + break; + case 98: + // VPERMQZmi, VPROLDZmi, VPROLQZmi, VPRORDZmi, VPRORQZmi, VPSCATTERDDZmr,... + printi512mem(MI, 1, O); + break; + } + + + // Fragment 2 encoded into 6 bits for 54 unique commands. + // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 28) & 63)); + switch ((uint32_t)((Bits >> 28) & 63)) { + default: // unreachable + case 0: + // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16... + return; + break; + case 1: + // ADC32rm, ADC64rm, ADD32rm, ADD64rm, AESKEYGENASSIST128rr, AND32rm, AND... + printOperand(MI, 1, O); + break; + case 2: + // ADCX32rm, ADCX64rm, ADDSDrm, ADDSDrm_Int, ADDSSrm, ADDSSrm_Int, ADOX32... + printOperand(MI, 0, O); + break; + case 3: + // AESKEYGENASSIST128rm, ANDN32rr, ANDN64rr, BEXTR32rm, BEXTR32rr, BEXTR6... + SStream_concat0(O, ", "); + break; + case 4: + // BLENDPDrri, BLENDPSrri, CMPPDrri, CMPPDrri_alt, CMPPSrri, CMPPSrri_alt... + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 5: + // BOUNDS16rm + printi32mem(MI, 1, O); + return; + break; + case 6: + // BOUNDS32rm + printi64mem(MI, 1, O); + return; + break; + case 7: + // CMPPDrmi, CMPPSrmi, VCMPPDZ128rmi, VCMPPDrmi, VCMPPSZ128rmi, VCMPPSrmi... + printf128mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 8: + // CMPSB + printSrcIdx8(MI, 1, O); + return; + break; + case 9: + // CMPSDrm, CMPSDrm_Int, VCMPPDZ128rmbi, VCMPPDZ256rmbi, VCMPPDZrmbi, VCM... + printf64mem(MI, 2, O); + break; + case 10: + // CMPSL + printSrcIdx32(MI, 1, O); + return; + break; + case 11: + // CMPSQ + printSrcIdx64(MI, 1, O); + return; + break; + case 12: + // CMPSSrm, CMPSSrm_Int, VCMPPSZ128rmbi, VCMPPSZ256rmbi, VCMPPSZrmbi, VCM... + printf32mem(MI, 2, O); + break; + case 13: + // CMPSW + printSrcIdx16(MI, 1, O); + return; + break; + case 14: + // EXTRACTPSmr, VEXTRACTPSZmr, VEXTRACTPSmr + printf32mem(MI, 0, O); + return; + break; + case 15: + // EXTRQI + printU8Imm(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 16: + // INSERTQI + printU8Imm(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 17: + // PEXTRBmr, RCL8mi, RCR8mi, ROL8mi, ROR8mi, SAR8mi, SHL8mi, SHR8mi, VPEX... + printi8mem(MI, 0, O); + return; + break; + case 18: + // PEXTRDmr, RCL32mi, RCR32mi, ROL32mi, ROR32mi, SAR32mi, SHL32mi, SHLD32... + printi32mem(MI, 0, O); + return; + break; + case 19: + // PEXTRQmr, RCL64mi, RCR64mi, ROL64mi, ROR64mi, SAR64mi, SHL64mi, SHLD64... + printi64mem(MI, 0, O); + return; + break; + case 20: + // PEXTRWmr, RCL16mi, RCR16mi, ROL16mi, ROR16mi, SAR16mi, SHL16mi, SHLD16... + printi16mem(MI, 0, O); + return; + break; + case 21: + // VADDPDZ128rmbk, VADDPDZ256rmbk, VADDPDZrmbk, VADDPSZ128rmbk, VADDPSZ25... + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 22: + // VALIGNDZ128rmbi, VALIGNDZ128rmbik, VALIGNDZ128rmbikz, VALIGNQZ256rmbi,... + SStream_concat0(O, "{1to4}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_4); + break; + case 23: + // VALIGNDZ128rmik, VALIGNDZ256rmik, VALIGNDZrmik, VALIGNQZ128rmik, VALIG... + SStream_concat0(O, "}"); + return; + break; + case 24: + // VALIGNDZ128rrik, VALIGNDZ256rrik, VALIGNDZrrik, VALIGNQZ128rrik, VALIG... + printOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 2, O); + break; + case 25: + // VALIGNDZ256rmbi, VALIGNDZ256rmbik, VALIGNDZ256rmbikz, VALIGNQZrmbi, VA... + SStream_concat0(O, "{1to8}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_8); + break; + case 26: + // VALIGNDZrmbi, VALIGNDZrmbik, VALIGNDZrmbikz, VCMPPSZrmbi_alt, VCMPPSZr... + SStream_concat0(O, "{1to16}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_16); + break; + case 27: + // VALIGNQZ128rmbi, VALIGNQZ128rmbik, VALIGNQZ128rmbikz, VCMPPDZ128rmbi_a... + SStream_concat0(O, "{1to2}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_2); + break; + case 28: + // VBROADCASTF32X2Z256rk, VBROADCASTF32X2Z256rkz, VBROADCASTF32X2Zrk, VBR... + SStream_concat0(O, " {"); + break; + case 29: + // VCMPPDYrmi, VCMPPDZ256rmi, VCMPPSYrmi, VCMPPSZ256rmi, VPERMIL2PDYmr, V... + printf256mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 30: + // VCMPPDZ128rmbik, VCMPPDZ256rmbik, VCMPPDZrmbik, VCMPSDZrm_Intk + printf64mem(MI, 3, O); + break; + case 31: + // VCMPPDZ128rmik, VCMPPSZ128rmik + printf128mem(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 1, O); + SStream_concat0(O, "}"); + return; + break; + case 32: + // VCMPPDZ256rmik, VCMPPSZ256rmik + printf256mem(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 1, O); + SStream_concat0(O, "}"); + return; + break; + case 33: + // VCMPPDZrmi, VCMPPSZrmi + printf512mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 34: + // VCMPPDZrmik, VCMPPSZrmik + printf512mem(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 1, O); + SStream_concat0(O, "}"); + return; + break; + case 35: + // VCMPPSZ128rmbik, VCMPPSZ256rmbik, VCMPPSZrmbik, VCMPSSZrm_Intk + printf32mem(MI, 3, O); + break; + case 36: + // VCVTPS2PHYmr, VCVTPS2PHZ256mr, VCVTPS2PHZ256mrk, VEXTRACTF128mr, VEXTR... + printf128mem(MI, 0, O); + break; + case 37: + // VCVTPS2PHZ128mr, VCVTPS2PHZ128mrk, VCVTPS2PHmr + printf64mem(MI, 0, O); + break; + case 38: + // VCVTPS2PHZmr, VCVTPS2PHZmrk, VEXTRACTF32x8Zmr, VEXTRACTF32x8Zmrk, VEXT... + printf256mem(MI, 0, O); + break; + case 39: + // VEXTRACTI128mr, VEXTRACTI32x4Z256mr, VEXTRACTI32x4Z256mrk, VEXTRACTI32... + printi128mem(MI, 0, O); + break; + case 40: + // VEXTRACTI32x8Zmr, VEXTRACTI32x8Zmrk, VEXTRACTI64x4Zmr, VEXTRACTI64x4Zm... + printi256mem(MI, 0, O); + break; + case 41: + // VFIXUPIMMPDZ128rmikz, VFIXUPIMMPDZ256rmikz, VFIXUPIMMPDZrmikz, VFIXUPI... + SStream_concat0(O, "} {z}"); + op_addAvxZeroOpmask(MI); + return; + break; + case 42: + // VPCMPBZ128rmi, VPCMPDZ128rmi, VPCMPQZ128rmi, VPCMPUBZ128rmi, VPCMPUDZ1... + printi128mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 43: + // VPCMPBZ128rmik, VPCMPDZ128rmik, VPCMPQZ128rmik, VPCMPUBZ128rmik, VPCMP... + printi128mem(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 1, O); + SStream_concat0(O, "}"); + return; + break; + case 44: + // VPCMPBZ256rmi, VPCMPDZ256rmi, VPCMPQZ256rmi, VPCMPUBZ256rmi, VPCMPUDZ2... + printi256mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 45: + // VPCMPBZ256rmik, VPCMPDZ256rmik, VPCMPQZ256rmik, VPCMPUBZ256rmik, VPCMP... + printi256mem(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 1, O); + SStream_concat0(O, "}"); + return; + break; + case 46: + // VPCMPBZrmi, VPCMPDZrmi, VPCMPQZrmi, VPCMPUBZrmi, VPCMPUDZrmi, VPCMPUQZ... + printi512mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 47: + // VPCMPBZrmik, VPCMPDZrmik, VPCMPQZrmik, VPCMPUBZrmik, VPCMPUDZrmik, VPC... + printi512mem(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, " {"); + printOperand(MI, 1, O); + SStream_concat0(O, "}"); + return; + break; + case 48: + // VPCMPDZ128rmib, VPCMPDZ256rmib, VPCMPDZrmib, VPCMPUDZ128rmib, VPCMPUDZ... + printi32mem(MI, 2, O); + break; + case 49: + // VPCMPDZ128rmibk, VPCMPDZ256rmibk, VPCMPDZrmibk, VPCMPUDZ128rmibk, VPCM... + printi32mem(MI, 3, O); + break; + case 50: + // VPCMPQZ128rmib, VPCMPQZ256rmib, VPCMPQZrmib, VPCMPUQZ128rmib, VPCMPUQZ... + printi64mem(MI, 2, O); + break; + case 51: + // VPCMPQZ128rmibk, VPCMPQZ256rmibk, VPCMPQZrmibk, VPCMPUQZ128rmibk, VPCM... + printi64mem(MI, 3, O); + break; + case 52: + // XADD16rm, XCHG16rm + printi16mem(MI, 2, O); + return; + break; + case 53: + // XADD8rm, XCHG8rm + printi8mem(MI, 2, O); + return; + break; + } + + + // Fragment 3 encoded into 4 bits for 15 unique commands. + // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 34) & 15)); + switch ((uint32_t)((Bits >> 34) & 15)) { + default: // unreachable + case 0: + // ADC32rm, ADC64rm, ADCX32rm, ADCX64rm, ADD32rm, ADD64rm, ADDSDrm, ADDSD... + return; + break; + case 1: + // AESKEYGENASSIST128rm, ANDN32rr, ANDN64rr, BEXTR32rm, BEXTR32rr, BEXTR6... + printOperand(MI, 0, O); + break; + case 2: + // AESKEYGENASSIST128rr, ANDN32rm, ANDN64rm, CMPSDrm, CMPSDrm_Int, CMPSSr... + SStream_concat0(O, ", "); + break; + case 3: + // VALIGNDZ128rmbi, VALIGNDZ128rri, VALIGNDZ256rmbi, VALIGNDZ256rri, VALI... + printOperand(MI, 1, O); + break; + case 4: + // VALIGNDZ128rmbik, VALIGNDZ256rmbik, VALIGNDZrmbik, VALIGNQZ128rmbik, V... + printOperand(MI, 3, O); + break; + case 5: + // VALIGNDZ128rmbikz, VALIGNDZ128rrikz, VALIGNDZ256rmbikz, VALIGNDZ256rri... + printOperand(MI, 2, O); + break; + case 6: + // VALIGNDZ128rrik, VALIGNDZ256rrik, VALIGNDZrrik, VALIGNQZ128rrik, VALIG... + SStream_concat0(O, "}"); + return; + break; + case 7: + // VBROADCASTF32X2Z256mk, VBROADCASTF32X2Z256mkz, VBROADCASTF32X2Zmk, VBR... + SStream_concat0(O, " {"); + break; + case 8: + // VCMPPDZ128rmbi, VCMPPDZ128rmbik, VPCMPQZ128rmib, VPCMPQZ128rmibk, VPCM... + SStream_concat0(O, "{1to2}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_2); + break; + case 9: + // VCMPPDZ256rmbi, VCMPPDZ256rmbik, VCMPPSZ128rmbi, VCMPPSZ128rmbik, VPCM... + SStream_concat0(O, "{1to4}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_4); + break; + case 10: + // VCMPPDZrmbi, VCMPPDZrmbik, VCMPPSZ256rmbi, VCMPPSZ256rmbik, VPCMPDZ256... + SStream_concat0(O, "{1to8}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_8); + break; + case 11: + // VCMPPSZrmbi, VCMPPSZrmbik, VPCMPDZrmib, VPCMPDZrmibk, VPCMPUDZrmib, VP... + SStream_concat0(O, "{1to16}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_16); + break; + case 12: + // VCOMPRESSPDZ128mrk, VCOMPRESSPDZ256mrk, VCOMPRESSPDZmrk, VCOMPRESSPSZ1... + printOperand(MI, 5, O); + SStream_concat0(O, "}"); + return; + break; + case 13: + // VFIXUPIMMPDZ128rrikz, VFIXUPIMMPDZ256rrikz, VFIXUPIMMPDZrribkz, VFIXUP... + SStream_concat0(O, "} {z}"); + op_addAvxZeroOpmask(MI); + return; + break; + case 14: + // VPSCATTERDDZ128mr, VPSCATTERDDZ256mr, VPSCATTERDDZmr, VPSCATTERDQZ128m... + printOperand(MI, 6, O); + SStream_concat0(O, "}"); + return; + break; + } + + + // Fragment 4 encoded into 4 bits for 10 unique commands. + // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 38) & 15)); + switch ((uint32_t)((Bits >> 38) & 15)) { + default: // unreachable + case 0: + // AESKEYGENASSIST128rm, ANDN32rr, ANDN64rr, BEXTR32rm, BEXTR32rr, BEXTR6... + return; + break; + case 1: + // AESKEYGENASSIST128rr, ANDN32rm, ANDN64rm, CMPSDrm, CMPSDrm_Int, CMPSSr... + printOperand(MI, 0, O); + return; + break; + case 2: + // VADDPDZ128rmbk, VADDPDZ128rmbkz, VADDPDZ128rmkz, VADDPDZ128rrkz, VADDP... + SStream_concat0(O, " {"); + break; + case 3: + // VALIGNDZ128rmbi, VALIGNDZ128rmbik, VALIGNDZ128rmbikz, VALIGNDZ128rri, ... + SStream_concat0(O, ", "); + break; + case 4: + // VBROADCASTF32X2Z256mk, VBROADCASTF32X2Zmk, VBROADCASTI32X2Z128mk, VBRO... + printOperand(MI, 2, O); + break; + case 5: + // VBROADCASTF32X2Z256mkz, VBROADCASTF32X2Zmkz, VBROADCASTI32X2Z128mkz, V... + printOperand(MI, 1, O); + break; + case 6: + // VBROADCASTF32X2Z256rk, VBROADCASTF32X2Zrk, VBROADCASTF32X4Z256rmk, VBR... + SStream_concat0(O, "}"); + return; + break; + case 7: + // VBROADCASTF32X2Z256rkz, VBROADCASTF32X2Zrkz, VBROADCASTF32X4Z256rmkz, ... + SStream_concat0(O, "} {z}"); + op_addAvxZeroOpmask(MI); + return; + break; + case 8: + // VCVTPS2PHZ128mrk, VCVTPS2PHZ256mrk, VCVTPS2PHZmrk, VEXTRACTF32x4Z256mr... + printOperand(MI, 5, O); + SStream_concat0(O, "}"); + return; + break; + case 9: + // VGATHERQPSZ128rm, VPGATHERQDZ128rm + printOperand(MI, 3, O); + SStream_concat0(O, "}"); + return; + break; + } + + + // Fragment 5 encoded into 3 bits for 6 unique commands. + // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 42) & 7)); + switch ((uint32_t)((Bits >> 42) & 7)) { + default: // unreachable + case 0: + // VADDPDZ128rmbk, VADDPDZ256rmbk, VADDPDZrmbk, VADDPSZ128rmbk, VADDPSZ25... + printOperand(MI, 2, O); + break; + case 1: + // VADDPDZ128rmbkz, VADDPDZ128rmkz, VADDPDZ128rrkz, VADDPDZ256rmbkz, VADD... + printOperand(MI, 1, O); + break; + case 2: + // VALIGNDZ128rmbi, VALIGNDZ128rmbik, VALIGNDZ128rmbikz, VALIGNDZ128rri, ... + printOperand(MI, 0, O); + break; + case 3: + // VBROADCASTF32X2Z256mk, VBROADCASTF32X2Zmk, VBROADCASTI32X2Z128mk, VBRO... + SStream_concat0(O, "}"); + return; + break; + case 4: + // VBROADCASTF32X2Z256mkz, VBROADCASTF32X2Zmkz, VBROADCASTI32X2Z128mkz, V... + SStream_concat0(O, "} {z}"); + op_addAvxZeroOpmask(MI); + return; + break; + case 5: + // VCMPPDZ128rmbi, VCMPPDZ128rmbik, VCMPPDZ256rmbi, VCMPPDZ256rmbik, VCMP... + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + break; + } + + + // Fragment 6 encoded into 3 bits for 5 unique commands. + // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 45) & 7)); + switch ((uint32_t)((Bits >> 45) & 7)) { + default: // unreachable + case 0: + // VADDPDZ128rmbk, VADDPDZ256rmbk, VADDPDZrmbk, VADDPSZ128rmbk, VADDPSZ25... + SStream_concat0(O, "}"); + return; + break; + case 1: + // VADDPDZ128rmbkz, VADDPDZ128rmkz, VADDPDZ128rrkz, VADDPDZ256rmbkz, VADD... + SStream_concat0(O, "} {z}"); + op_addAvxZeroOpmask(MI); + return; + break; + case 2: + // VALIGNDZ128rmbi, VALIGNDZ128rri, VALIGNDZ256rmbi, VALIGNDZ256rri, VALI... + return; + break; + case 3: + // VALIGNDZ128rmbik, VALIGNDZ128rmbikz, VALIGNDZ128rrikz, VALIGNDZ256rmbi... + SStream_concat0(O, " {"); + break; + case 4: + // VPERMIL2PDYrr, VPERMIL2PDYrr_REV, VPERMIL2PDrr, VPERMIL2PDrr_REV, VPER... + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + } + + + // Fragment 7 encoded into 1 bits for 2 unique commands. + // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 48) & 1)); + if ((Bits >> 48) & 1) { + // VALIGNDZ128rmbikz, VALIGNDZ128rrikz, VALIGNDZ256rmbikz, VALIGNDZ256rri... + printOperand(MI, 1, O); + } else { + // VALIGNDZ128rmbik, VALIGNDZ256rmbik, VALIGNDZrmbik, VALIGNQZ128rmbik, V... + printOperand(MI, 2, O); + } + + + // Fragment 8 encoded into 1 bits for 2 unique commands. + // printf("Fragment 8: %"PRIu64"\n", ((Bits >> 49) & 1)); + if ((Bits >> 49) & 1) { + // VALIGNDZ128rmbikz, VALIGNDZ128rrikz, VALIGNDZ256rmbikz, VALIGNDZ256rri... + SStream_concat0(O, "} {z}"); + op_addAvxZeroOpmask(MI); + return; + } else { + // VALIGNDZ128rmbik, VALIGNDZ256rmbik, VALIGNDZrmbik, VALIGNQZ128rmbik, V... + SStream_concat0(O, "}"); + return; + } + +} + + + diff --git a/thirdparty/capstone/arch/X86/X86GenAsmWriter1.inc b/thirdparty/capstone/arch/X86/X86GenAsmWriter1.inc new file mode 100644 index 0000000..2b9c88f --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenAsmWriter1.inc @@ -0,0 +1,33196 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) +{ +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '0', 9, 0, + /* 12 */ 's', 'h', 'a', '1', 'm', 's', 'g', '1', 9, 0, + /* 22 */ 's', 'h', 'a', '2', '5', '6', 'm', 's', 'g', '1', 9, 0, + /* 34 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '1', 9, 0, + /* 46 */ 'p', 'f', 'r', 'c', 'p', 'i', 't', '1', 9, 0, + /* 56 */ 'p', 'f', 'r', 's', 'q', 'i', 't', '1', 9, 0, + /* 66 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'w', 't', '1', 9, 0, + /* 79 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', '3', '2', 9, 0, + /* 90 */ 'c', 'r', 'c', '3', '2', 9, 0, + /* 97 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '3', '2', 9, 0, + /* 108 */ 's', 'h', 'a', '1', 'm', 's', 'g', '2', 9, 0, + /* 118 */ 's', 'h', 'a', '2', '5', '6', 'm', 's', 'g', '2', 9, 0, + /* 130 */ 's', 'h', 'a', '2', '5', '6', 'r', 'n', 'd', 's', '2', 9, 0, + /* 143 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '2', 9, 0, + /* 155 */ 'p', 'f', 'r', 'c', 'p', 'i', 't', '2', 9, 0, + /* 165 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '3', '2', 'x', '2', 9, 0, + /* 182 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '2', 9, 0, + /* 199 */ 'v', 's', 'h', 'u', 'f', 'f', '6', '4', 'x', '2', 9, 0, + /* 211 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '6', '4', 'x', '2', 9, 0, + /* 226 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '6', '4', 'x', '2', 9, 0, + /* 240 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '6', '4', 'x', '2', 9, 0, + /* 257 */ 'v', 's', 'h', 'u', 'f', 'i', '6', '4', 'x', '2', 9, 0, + /* 269 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '6', '4', 'x', '2', 9, 0, + /* 284 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '6', '4', 'x', '2', 9, 0, + /* 298 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '6', '4', 'x', '2', 9, 0, + /* 315 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', '6', '4', 9, 0, + /* 326 */ 'x', 's', 'a', 'v', 'e', 'c', '6', '4', 9, 0, + /* 336 */ 'f', 'x', 's', 'a', 'v', 'e', '6', '4', 9, 0, + /* 346 */ 'f', 'x', 'r', 's', 't', 'o', 'r', '6', '4', 9, 0, + /* 357 */ 'x', 's', 'a', 'v', 'e', 's', '6', '4', 9, 0, + /* 367 */ 'x', 'r', 's', 't', 'o', 'r', 's', '6', '4', 9, 0, + /* 378 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', '6', '4', 9, 0, + /* 390 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '6', '4', 9, 0, + /* 401 */ 's', 'h', 'a', '1', 'r', 'n', 'd', 's', '4', 9, 0, + /* 412 */ 'v', 's', 'h', 'u', 'f', 'f', '3', '2', 'x', '4', 9, 0, + /* 424 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '3', '2', 'x', '4', 9, 0, + /* 439 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '3', '2', 'x', '4', 9, 0, + /* 453 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '3', '2', 'x', '4', 9, 0, + /* 470 */ 'v', 's', 'h', 'u', 'f', 'i', '3', '2', 'x', '4', 9, 0, + /* 482 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '3', '2', 'x', '4', 9, 0, + /* 497 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '3', '2', 'x', '4', 9, 0, + /* 511 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '4', 9, 0, + /* 528 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '6', '4', 'x', '4', 9, 0, + /* 543 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '6', '4', 'x', '4', 9, 0, + /* 557 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '6', '4', 'x', '4', 9, 0, + /* 574 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '6', '4', 'x', '4', 9, 0, + /* 589 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '6', '4', 'x', '4', 9, 0, + /* 603 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '6', '4', 'x', '4', 9, 0, + /* 620 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '1', '6', 9, 0, + /* 631 */ 'v', 'p', 'e', 'r', 'm', '2', 'f', '1', '2', '8', 9, 0, + /* 643 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '1', '2', '8', 9, 0, + /* 657 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '1', '2', '8', 9, 0, + /* 670 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '1', '2', '8', 9, 0, + /* 686 */ 'v', 'p', 'e', 'r', 'm', '2', 'i', '1', '2', '8', 9, 0, + /* 698 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '1', '2', '8', 9, 0, + /* 712 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '1', '2', '8', 9, 0, + /* 725 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '1', '2', '8', 9, 0, + /* 741 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '8', 9, 0, + /* 751 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '3', '2', 'x', '8', 9, 0, + /* 766 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '3', '2', 'x', '8', 9, 0, + /* 780 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '3', '2', 'x', '8', 9, 0, + /* 797 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '3', '2', 'x', '8', 9, 0, + /* 812 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '3', '2', 'x', '8', 9, 0, + /* 826 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '8', 9, 0, + /* 843 */ 'l', 'e', 'a', 9, 0, + /* 848 */ 'j', 'a', 9, 0, + /* 852 */ 'v', 'm', 'o', 'v', 'n', 't', 'd', 'q', 'a', 9, 0, + /* 863 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', 9, 0, + /* 872 */ 's', 'e', 't', 'a', 9, 0, + /* 878 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'n', 't', 'a', 9, 0, + /* 891 */ 'c', 'm', 'o', 'v', 'a', 9, 0, + /* 898 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'b', 9, 0, + /* 908 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'b', 9, 0, + /* 918 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'b', 9, 0, + /* 928 */ 'm', 'o', 'v', 'd', 'i', 'r', '6', '4', 'b', 9, 0, + /* 939 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0, + /* 951 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '8', 'b', 9, 0, + /* 962 */ 'v', 'p', 's', 'h', 'a', 'b', 9, 0, + /* 970 */ 's', 'b', 'b', 9, 0, + /* 975 */ 'v', 'p', 's', 'u', 'b', 'b', 9, 0, + /* 983 */ 'l', 'l', 'w', 'p', 'c', 'b', 9, 0, + /* 991 */ 's', 'l', 'w', 'p', 'c', 'b', 9, 0, + /* 999 */ 'k', 'a', 'd', 'd', 'b', 9, 0, + /* 1006 */ 'v', 'p', 'a', 'd', 'd', 'b', 9, 0, + /* 1014 */ 'k', 'a', 'n', 'd', 'b', 9, 0, + /* 1021 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'b', 9, 0, + /* 1032 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'd', 'b', 9, 0, + /* 1043 */ 'v', 'p', 'm', 'o', 'v', 's', 'd', 'b', 9, 0, + /* 1053 */ 'v', 'p', 'm', 'o', 'v', 'd', 'b', 9, 0, + /* 1062 */ 'v', 'p', 's', 'h', 'u', 'f', 'b', 9, 0, + /* 1071 */ 'v', 'p', 'a', 'v', 'g', 'b', 9, 0, + /* 1079 */ 'j', 'b', 9, 0, + /* 1083 */ 'v', 'p', 'm', 'o', 'v', 'm', 's', 'k', 'b', 9, 0, + /* 1094 */ 'v', 'p', 's', 'h', 'l', 'b', 9, 0, + /* 1102 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'b', 9, 0, + /* 1112 */ 'v', 'g', 'f', '2', 'p', '8', 'm', 'u', 'l', 'b', 9, 0, + /* 1124 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'b', 9, 0, + /* 1135 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'b', 9, 0, + /* 1146 */ 'v', 'p', 'c', 'o', 'm', 'b', 9, 0, + /* 1154 */ 'v', 'p', 's', 'h', 'u', 'f', 'b', 'i', 't', 'q', 'm', 'b', 9, 0, + /* 1168 */ 'v', 'p', 'e', 'r', 'm', 'b', 9, 0, + /* 1176 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'b', 9, 0, + /* 1186 */ 'k', 'a', 'n', 'd', 'n', 'b', 9, 0, + /* 1194 */ 'v', 'p', 's', 'i', 'g', 'n', 'b', 9, 0, + /* 1203 */ 'v', 'p', 'c', 'm', 'p', 'b', 9, 0, + /* 1211 */ 'v', 'g', 'f', '2', 'p', '8', 'a', 'f', 'f', 'i', 'n', 'e', 'q', 'b', 9, 0, + /* 1227 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'b', 9, 0, + /* 1237 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'b', 9, 0, + /* 1248 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'b', 9, 0, + /* 1258 */ 'v', 'p', 'm', 'u', 'l', 't', 'i', 's', 'h', 'i', 'f', 't', 'q', 'b', 9, 0, + /* 1274 */ 'v', 'g', 'f', '2', 'p', '8', 'a', 'f', 'f', 'i', 'n', 'e', 'i', 'n', 'v', 'q', 'b', 9, 0, + /* 1293 */ 'v', 'p', 'm', 'o', 'v', 'q', 'b', 9, 0, + /* 1302 */ 'k', 'o', 'r', 'b', 9, 0, + /* 1308 */ 'k', 'x', 'n', 'o', 'r', 'b', 9, 0, + /* 1316 */ 'k', 'x', 'o', 'r', 'b', 9, 0, + /* 1323 */ 'v', 'p', 'i', 'n', 's', 'r', 'b', 9, 0, + /* 1332 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'b', 9, 0, + /* 1342 */ 'v', 'p', 'e', 'x', 't', 'r', 'b', 9, 0, + /* 1351 */ 'v', 'p', 'a', 'b', 's', 'b', 9, 0, + /* 1359 */ 'v', 'p', 's', 'u', 'b', 's', 'b', 9, 0, + /* 1368 */ 'v', 'p', 'a', 'd', 'd', 's', 'b', 9, 0, + /* 1377 */ 'v', 'p', 'm', 'i', 'n', 's', 'b', 9, 0, + /* 1386 */ 's', 't', 'o', 's', 'b', 9, 0, + /* 1393 */ 'c', 'm', 'p', 's', 'b', 9, 0, + /* 1400 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'b', 9, 0, + /* 1413 */ 'v', 'p', 's', 'u', 'b', 'u', 's', 'b', 9, 0, + /* 1423 */ 'v', 'p', 'a', 'd', 'd', 'u', 's', 'b', 9, 0, + /* 1433 */ 'p', 'a', 'v', 'g', 'u', 's', 'b', 9, 0, + /* 1442 */ 'm', 'o', 'v', 's', 'b', 9, 0, + /* 1449 */ 'v', 'p', 'm', 'a', 'x', 's', 'b', 9, 0, + /* 1458 */ 's', 'e', 't', 'b', 9, 0, + /* 1464 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'b', 9, 0, + /* 1474 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'b', 9, 0, + /* 1484 */ 'k', 'n', 'o', 't', 'b', 9, 0, + /* 1491 */ 'v', 'p', 'r', 'o', 't', 'b', 9, 0, + /* 1499 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'b', 9, 0, + /* 1513 */ 'k', 't', 'e', 's', 't', 'b', 9, 0, + /* 1521 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'b', 9, 0, + /* 1531 */ 'v', 'p', 'c', 'o', 'm', 'u', 'b', 9, 0, + /* 1540 */ 'v', 'p', 'm', 'i', 'n', 'u', 'b', 9, 0, + /* 1549 */ 'v', 'p', 'c', 'm', 'p', 'u', 'b', 9, 0, + /* 1558 */ 'p', 'f', 's', 'u', 'b', 9, 0, + /* 1565 */ 'f', 'i', 's', 'u', 'b', 9, 0, + /* 1572 */ 'v', 'p', 'm', 'a', 'x', 'u', 'b', 9, 0, + /* 1581 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'v', 'b', 9, 0, + /* 1592 */ 'c', 'm', 'o', 'v', 'b', 9, 0, + /* 1599 */ 'k', 'm', 'o', 'v', 'b', 9, 0, + /* 1606 */ 'c', 'l', 'w', 'b', 9, 0, + /* 1612 */ 'v', 'p', 'a', 'c', 'k', 's', 's', 'w', 'b', 9, 0, + /* 1623 */ 'v', 'p', 'a', 'c', 'k', 'u', 's', 'w', 'b', 9, 0, + /* 1634 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'w', 'b', 9, 0, + /* 1645 */ 'v', 'p', 'm', 'o', 'v', 's', 'w', 'b', 9, 0, + /* 1655 */ 'v', 'p', 'm', 'o', 'v', 'w', 'b', 9, 0, + /* 1664 */ 'p', 'f', 'a', 'c', 'c', 9, 0, + /* 1671 */ 'p', 'f', 'n', 'a', 'c', 'c', 9, 0, + /* 1679 */ 'p', 'f', 'p', 'n', 'a', 'c', 'c', 9, 0, + /* 1688 */ 'a', 'd', 'c', 9, 0, + /* 1693 */ 'v', 'a', 'e', 's', 'd', 'e', 'c', 9, 0, + /* 1702 */ 'x', 's', 'a', 'v', 'e', 'c', 9, 0, + /* 1710 */ 'b', 'l', 'c', 'i', 'c', 9, 0, + /* 1717 */ 'b', 'l', 's', 'i', 'c', 9, 0, + /* 1724 */ 't', '1', 'm', 's', 'k', 'c', 9, 0, + /* 1732 */ 'v', 'a', 'e', 's', 'i', 'm', 'c', 9, 0, + /* 1741 */ 'v', 'a', 'e', 's', 'e', 'n', 'c', 9, 0, + /* 1750 */ 'i', 'n', 'c', 9, 0, + /* 1755 */ 'b', 't', 'c', 9, 0, + /* 1760 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'd', 9, 0, + /* 1770 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'd', 9, 0, + /* 1780 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'd', 9, 0, + /* 1790 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'm', 'w', '2', 'd', 9, 0, + /* 1807 */ 'a', 'a', 'd', 9, 0, + /* 1812 */ 'v', 'm', 'r', 'e', 'a', 'd', 9, 0, + /* 1820 */ 'v', 'p', 's', 'h', 'a', 'd', 9, 0, + /* 1828 */ 'v', 'p', 's', 'r', 'a', 'd', 9, 0, + /* 1836 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'd', 9, 0, + /* 1846 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'd', 9, 0, + /* 1857 */ 'v', 'p', 'h', 's', 'u', 'b', 'd', 9, 0, + /* 1866 */ 'v', 'p', 's', 'u', 'b', 'd', 9, 0, + /* 1874 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'd', 9, 0, + /* 1885 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'd', 9, 0, + /* 1896 */ 'p', 'f', 'a', 'd', 'd', 9, 0, + /* 1903 */ 'f', 'i', 'a', 'd', 'd', 9, 0, + /* 1910 */ 'x', 'a', 'd', 'd', 9, 0, + /* 1916 */ 'v', 'p', 'h', 'a', 'd', 'd', 'd', 9, 0, + /* 1925 */ 'k', 'a', 'd', 'd', 'd', 9, 0, + /* 1932 */ 'v', 'p', 'a', 'd', 'd', 'd', 9, 0, + /* 1940 */ 'v', 'p', 's', 'h', 'l', 'd', 'd', 9, 0, + /* 1949 */ 'k', 'a', 'n', 'd', 'd', 9, 0, + /* 1956 */ 'v', 'p', 'a', 'n', 'd', 'd', 9, 0, + /* 1964 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'd', 9, 0, + /* 1975 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'd', 9, 0, + /* 1985 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'd', 9, 0, + /* 1997 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'd', 9, 0, + /* 2010 */ 'v', 'p', 's', 'h', 'r', 'd', 'd', 9, 0, + /* 2019 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'd', 9, 0, + /* 2029 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'd', 9, 0, + /* 2040 */ 'r', 'd', 's', 'e', 'e', 'd', 9, 0, + /* 2048 */ 'p', 'i', '2', 'f', 'd', 9, 0, + /* 2055 */ 'v', 'p', 's', 'h', 'u', 'f', 'd', 9, 0, + /* 2064 */ 'v', 'p', 't', 'e', 'r', 'n', 'l', 'o', 'g', 'd', 9, 0, + /* 2076 */ 'p', 'f', '2', 'i', 'd', 9, 0, + /* 2083 */ 'i', 'n', 'v', 'p', 'c', 'i', 'd', 9, 0, + /* 2092 */ 'r', 'd', 'p', 'i', 'd', 9, 0, + /* 2099 */ 'i', 'n', 'v', 'v', 'p', 'i', 'd', 9, 0, + /* 2108 */ 'f', 'l', 'd', 9, 0, + /* 2113 */ 'v', 'p', 's', 'h', 'l', 'd', 9, 0, + /* 2121 */ 'f', 'i', 'l', 'd', 9, 0, + /* 2127 */ 'v', 'p', 's', 'l', 'l', 'd', 9, 0, + /* 2135 */ 'v', 'p', 'm', 'u', 'l', 'l', 'd', 9, 0, + /* 2144 */ 'v', 'p', 'r', 'o', 'l', 'd', 9, 0, + /* 2152 */ 'v', 'p', 's', 'r', 'l', 'd', 9, 0, + /* 2160 */ 'v', 'm', 'p', 't', 'r', 'l', 'd', 9, 0, + /* 2169 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'd', 9, 0, + /* 2179 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'd', 9, 0, + /* 2190 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'd', 9, 0, + /* 2201 */ 'v', 'p', 'c', 'o', 'm', 'd', 9, 0, + /* 2209 */ 'v', 'p', 'e', 'r', 'm', 'd', 9, 0, + /* 2217 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'd', 9, 0, + /* 2227 */ 'v', 'p', 'a', 'n', 'd', 9, 0, + /* 2234 */ 'r', 'd', 'r', 'a', 'n', 'd', 9, 0, + /* 2242 */ 'k', 'a', 'n', 'd', 'n', 'd', 9, 0, + /* 2250 */ 'v', 'p', 'a', 'n', 'd', 'n', 'd', 9, 0, + /* 2259 */ 'v', 'a', 'l', 'i', 'g', 'n', 'd', 9, 0, + /* 2268 */ 'v', 'p', 's', 'i', 'g', 'n', 'd', 9, 0, + /* 2277 */ 'b', 'o', 'u', 'n', 'd', 9, 0, + /* 2284 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, + /* 2300 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, + /* 2313 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, + /* 2327 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, + /* 2343 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, + /* 2356 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, + /* 2370 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, + /* 2386 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, + /* 2399 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, + /* 2413 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, + /* 2429 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, + /* 2442 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, + /* 2456 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'p', 'd', 9, 0, + /* 2467 */ 'c', 'v', 't', 'p', 'i', '2', 'p', 'd', 9, 0, + /* 2477 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', '2', 'p', 'd', 9, 0, + /* 2489 */ 'v', 'e', 'x', 'p', '2', 'p', 'd', 9, 0, + /* 2498 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 'd', 9, 0, + /* 2509 */ 'v', 'c', 'v', 't', 'u', 'd', 'q', '2', 'p', 'd', 9, 0, + /* 2521 */ 'v', 'c', 'v', 't', 'q', 'q', '2', 'p', 'd', 9, 0, + /* 2532 */ 'v', 'c', 'v', 't', 'u', 'q', 'q', '2', 'p', 'd', 9, 0, + /* 2544 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'd', 9, 0, + /* 2555 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'p', 'd', 9, 0, + /* 2566 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, + /* 2582 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, + /* 2595 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, + /* 2609 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, + /* 2625 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, + /* 2638 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, + /* 2652 */ 'v', 'r', 'c', 'p', '1', '4', 'p', 'd', 9, 0, + /* 2662 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 'p', 'd', 9, 0, + /* 2674 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 'd', 9, 0, + /* 2684 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 'd', 9, 0, + /* 2696 */ 'v', 'm', 'o', 'v', 'a', 'p', 'd', 9, 0, + /* 2705 */ 'p', 's', 'w', 'a', 'p', 'd', 9, 0, + /* 2713 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', 'p', 'd', 9, 0, + /* 2726 */ 'v', 'a', 'd', 'd', 's', 'u', 'b', 'p', 'd', 9, 0, + /* 2737 */ 'v', 'h', 's', 'u', 'b', 'p', 'd', 9, 0, + /* 2746 */ 'v', 'f', 'm', 's', 'u', 'b', 'p', 'd', 9, 0, + /* 2756 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 'p', 'd', 9, 0, + /* 2767 */ 'v', 's', 'u', 'b', 'p', 'd', 9, 0, + /* 2775 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', 'p', 'd', 9, 0, + /* 2788 */ 'v', 'h', 'a', 'd', 'd', 'p', 'd', 9, 0, + /* 2797 */ 'v', 'f', 'm', 'a', 'd', 'd', 'p', 'd', 9, 0, + /* 2807 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 'd', 9, 0, + /* 2818 */ 'v', 'a', 'd', 'd', 'p', 'd', 9, 0, + /* 2826 */ 'v', 'e', 'x', 'p', 'a', 'n', 'd', 'p', 'd', 9, 0, + /* 2837 */ 'v', 'a', 'n', 'd', 'p', 'd', 9, 0, + /* 2845 */ 'v', 'b', 'l', 'e', 'n', 'd', 'p', 'd', 9, 0, + /* 2855 */ 'v', 'r', 'o', 'u', 'n', 'd', 'p', 'd', 9, 0, + /* 2865 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 'd', 9, 0, + /* 2877 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'p', 'd', 9, 0, + /* 2890 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 'p', 'd', 9, 0, + /* 2901 */ 'v', 'r', 'a', 'n', 'g', 'e', 'p', 'd', 9, 0, + /* 2911 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 'p', 'd', 9, 0, + /* 2924 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 'p', 'd', 9, 0, + /* 2935 */ 'v', 's', 'h', 'u', 'f', 'p', 'd', 9, 0, + /* 2944 */ 'v', 'u', 'n', 'p', 'c', 'k', 'h', 'p', 'd', 9, 0, + /* 2955 */ 'v', 'm', 'o', 'v', 'h', 'p', 'd', 9, 0, + /* 2964 */ 'v', 'm', 'o', 'v', 'm', 's', 'k', 'p', 'd', 9, 0, + /* 2975 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 'd', 9, 0, + /* 2986 */ 'v', 'u', 'n', 'p', 'c', 'k', 'l', 'p', 'd', 9, 0, + /* 2997 */ 'v', 'm', 'u', 'l', 'p', 'd', 9, 0, + /* 3005 */ 'v', 'm', 'o', 'v', 'l', 'p', 'd', 9, 0, + /* 3014 */ 'v', 'p', 'c', 'm', 'p', 'd', 9, 0, + /* 3022 */ 'v', 'b', 'l', 'e', 'n', 'd', 'm', 'p', 'd', 9, 0, + /* 3033 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 'p', 'd', 9, 0, + /* 3046 */ 'v', 'p', 'e', 'r', 'm', 'p', 'd', 9, 0, + /* 3055 */ 'v', 'a', 'n', 'd', 'n', 'p', 'd', 9, 0, + /* 3064 */ 'v', 'm', 'i', 'n', 'p', 'd', 9, 0, + /* 3072 */ 'v', 'd', 'p', 'p', 'd', 9, 0, + /* 3079 */ 'v', 'c', 'm', 'p', 'p', 'd', 9, 0, + /* 3087 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 'p', 'd', 9, 0, + /* 3098 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 'd', 9, 0, + /* 3110 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'p', 'd', 9, 0, + /* 3123 */ 'v', 'o', 'r', 'p', 'd', 9, 0, + /* 3130 */ 'v', 'x', 'o', 'r', 'p', 'd', 9, 0, + /* 3138 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 'd', 9, 0, + /* 3150 */ 'i', 'n', 'c', 's', 's', 'p', 'd', 9, 0, + /* 3159 */ 'r', 'd', 's', 's', 'p', 'd', 9, 0, + /* 3167 */ 'v', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'p', 'd', 9, 0, + /* 3180 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 'p', 'd', 9, 0, + /* 3192 */ 'v', 'm', 'o', 'v', 'n', 't', 'p', 'd', 9, 0, + /* 3202 */ 'v', 's', 'q', 'r', 't', 'p', 'd', 9, 0, + /* 3211 */ 'v', 't', 'e', 's', 't', 'p', 'd', 9, 0, + /* 3220 */ 'v', 'm', 'o', 'v', 'u', 'p', 'd', 9, 0, + /* 3229 */ 'v', 'b', 'l', 'e', 'n', 'd', 'v', 'p', 'd', 9, 0, + /* 3240 */ 'v', 'd', 'i', 'v', 'p', 'd', 9, 0, + /* 3248 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'p', 'd', 9, 0, + /* 3260 */ 'v', 'm', 'a', 'x', 'p', 'd', 9, 0, + /* 3268 */ 'v', 'f', 'r', 'c', 'z', 'p', 'd', 9, 0, + /* 3277 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'd', 9, 0, + /* 3287 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'd', 9, 0, + /* 3299 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'd', 9, 0, + /* 3312 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'd', 9, 0, + /* 3323 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'd', 9, 0, + /* 3333 */ 'v', 'p', 'm', 'o', 'v', 'q', 'd', 9, 0, + /* 3342 */ 's', 'h', 'r', 'd', 9, 0, + /* 3348 */ 'k', 'o', 'r', 'd', 9, 0, + /* 3354 */ 'k', 'x', 'n', 'o', 'r', 'd', 9, 0, + /* 3362 */ 'v', 'p', 'o', 'r', 'd', 9, 0, + /* 3369 */ 'v', 'p', 'r', 'o', 'r', 'd', 9, 0, + /* 3377 */ 'k', 'x', 'o', 'r', 'd', 9, 0, + /* 3384 */ 'v', 'p', 'x', 'o', 'r', 'd', 9, 0, + /* 3392 */ 'v', 'p', 'i', 'n', 's', 'r', 'd', 9, 0, + /* 3401 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'd', 9, 0, + /* 3411 */ 'v', 'p', 'e', 'x', 't', 'r', 'd', 9, 0, + /* 3420 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 's', 'd', 9, 0, + /* 3433 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 's', 'd', 9, 0, + /* 3447 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 'd', 9, 0, + /* 3460 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 'd', 9, 0, + /* 3474 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 's', 'd', 9, 0, + /* 3487 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 's', 'd', 9, 0, + /* 3501 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 'd', 9, 0, + /* 3514 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 'd', 9, 0, + /* 3528 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 'd', 9, 0, + /* 3539 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 'd', 9, 0, + /* 3551 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'd', 9, 0, + /* 3562 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 9, 0, + /* 3575 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 9, 0, + /* 3589 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 9, 0, + /* 3602 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 9, 0, + /* 3616 */ 'v', 'r', 'c', 'p', '1', '4', 's', 'd', 9, 0, + /* 3626 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 's', 'd', 9, 0, + /* 3638 */ 'v', 'r', 'c', 'p', '2', '8', 's', 'd', 9, 0, + /* 3648 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 'd', 9, 0, + /* 3660 */ 'v', 'p', 'a', 'b', 's', 'd', 9, 0, + /* 3668 */ 'v', 'f', 'm', 's', 'u', 'b', 's', 'd', 9, 0, + /* 3678 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 'd', 9, 0, + /* 3689 */ 'v', 's', 'u', 'b', 's', 'd', 9, 0, + /* 3697 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'd', 9, 0, + /* 3707 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 'd', 9, 0, + /* 3718 */ 'v', 'a', 'd', 'd', 's', 'd', 9, 0, + /* 3726 */ 'v', 'r', 'o', 'u', 'n', 'd', 's', 'd', 9, 0, + /* 3736 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 's', 'd', 9, 0, + /* 3747 */ 'v', 'r', 'a', 'n', 'g', 'e', 's', 'd', 9, 0, + /* 3757 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 's', 'd', 9, 0, + /* 3770 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 's', 'd', 9, 0, + /* 3781 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 'd', 9, 0, + /* 3791 */ 'v', 'c', 'o', 'm', 'i', 's', 'd', 9, 0, + /* 3800 */ 'v', 'm', 'u', 'l', 's', 'd', 9, 0, + /* 3808 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 's', 'd', 9, 0, + /* 3821 */ 'v', 'p', 'm', 'i', 'n', 's', 'd', 9, 0, + /* 3830 */ 'v', 'm', 'i', 'n', 's', 'd', 9, 0, + /* 3838 */ 's', 't', 'o', 's', 'd', 9, 0, + /* 3845 */ 'v', 'c', 'm', 'p', 's', 'd', 9, 0, + /* 3853 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 's', 'd', 9, 0, + /* 3864 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'd', 9, 0, + /* 3877 */ 'w', 'r', 's', 's', 'd', 9, 0, + /* 3884 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 's', 'd', 9, 0, + /* 3896 */ 'w', 'r', 'u', 's', 's', 'd', 9, 0, + /* 3904 */ 'v', 'p', '4', 'd', 'p', 'w', 's', 's', 'd', 9, 0, + /* 3915 */ 'v', 'p', 'd', 'p', 'w', 's', 's', 'd', 9, 0, + /* 3925 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 's', 'd', 9, 0, + /* 3937 */ 'm', 'o', 'v', 'n', 't', 's', 'd', 9, 0, + /* 3946 */ 'v', 's', 'q', 'r', 't', 's', 'd', 9, 0, + /* 3955 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 'd', 9, 0, + /* 3969 */ 'v', 'p', 'd', 'p', 'b', 'u', 's', 'd', 9, 0, + /* 3979 */ 'v', 'd', 'i', 'v', 's', 'd', 9, 0, + /* 3987 */ 'v', 'm', 'o', 'v', 's', 'd', 9, 0, + /* 3995 */ 'v', 'p', 'm', 'a', 'x', 's', 'd', 9, 0, + /* 4004 */ 'v', 'm', 'a', 'x', 's', 'd', 9, 0, + /* 4012 */ 'v', 'f', 'r', 'c', 'z', 's', 'd', 9, 0, + /* 4021 */ 'v', 'p', 'c', 'o', 'n', 'f', 'l', 'i', 'c', 't', 'd', 9, 0, + /* 4034 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'd', 9, 0, + /* 4044 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'd', 9, 0, + /* 4054 */ 'v', 'p', 'l', 'z', 'c', 'n', 't', 'd', 9, 0, + /* 4064 */ 'k', 'n', 'o', 't', 'd', 9, 0, + /* 4071 */ 'v', 'p', 'r', 'o', 't', 'd', 9, 0, + /* 4079 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'd', 9, 0, + /* 4093 */ 'k', 't', 'e', 's', 't', 'd', 9, 0, + /* 4101 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'd', 9, 0, + /* 4111 */ 'v', 'p', 'c', 'o', 'm', 'u', 'd', 9, 0, + /* 4120 */ 'v', 'p', 'm', 'i', 'n', 'u', 'd', 9, 0, + /* 4129 */ 'v', 'p', 'c', 'm', 'p', 'u', 'd', 9, 0, + /* 4138 */ 'v', 'p', 'm', 'a', 'x', 'u', 'd', 9, 0, + /* 4147 */ 'v', 'p', 's', 'r', 'a', 'v', 'd', 9, 0, + /* 4156 */ 'v', 'p', 's', 'h', 'l', 'd', 'v', 'd', 9, 0, + /* 4166 */ 'v', 'p', 's', 'h', 'r', 'd', 'v', 'd', 9, 0, + /* 4176 */ 'v', 'p', 's', 'l', 'l', 'v', 'd', 9, 0, + /* 4185 */ 'v', 'p', 'r', 'o', 'l', 'v', 'd', 9, 0, + /* 4194 */ 'v', 'p', 's', 'r', 'l', 'v', 'd', 9, 0, + /* 4203 */ 'v', 'p', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'd', 9, 0, + /* 4215 */ 'v', 'm', 'o', 'v', 'd', 9, 0, + /* 4222 */ 'v', 'p', 'r', 'o', 'r', 'v', 'd', 9, 0, + /* 4231 */ 'v', 'p', 'h', 's', 'u', 'b', 'w', 'd', 9, 0, + /* 4241 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 'd', 9, 0, + /* 4251 */ 'v', 'p', 'm', 'a', 'd', 'd', 'w', 'd', 9, 0, + /* 4261 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'w', 'd', 9, 0, + /* 4273 */ 'k', 'u', 'n', 'p', 'c', 'k', 'w', 'd', 9, 0, + /* 4283 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'w', 'd', 9, 0, + /* 4295 */ 'v', 'p', 'm', 'a', 'c', 's', 'w', 'd', 9, 0, + /* 4305 */ 'v', 'p', 'm', 'a', 'd', 'c', 's', 'w', 'd', 9, 0, + /* 4316 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'w', 'd', 9, 0, + /* 4327 */ 'v', 'p', 'm', 'a', 'd', 'c', 's', 's', 'w', 'd', 9, 0, + /* 4339 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'w', 'd', 9, 0, + /* 4350 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'd', 9, 0, + /* 4361 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'd', 9, 0, + /* 4372 */ 'm', 'o', 'v', 's', 'x', 'd', 9, 0, + /* 4380 */ 'j', 'a', 'e', 9, 0, + /* 4385 */ 's', 'e', 't', 'a', 'e', 9, 0, + /* 4392 */ 'c', 'm', 'o', 'v', 'a', 'e', 9, 0, + /* 4400 */ 'j', 'b', 'e', 9, 0, + /* 4405 */ 's', 'e', 't', 'b', 'e', 9, 0, + /* 4412 */ 'c', 'm', 'o', 'v', 'b', 'e', 9, 0, + /* 4420 */ 'f', 's', 't', 'p', 'n', 'c', 'e', 9, 0, + /* 4429 */ 'f', 'f', 'r', 'e', 'e', 9, 0, + /* 4436 */ 'j', 'g', 'e', 9, 0, + /* 4441 */ 'p', 'f', 'c', 'm', 'p', 'g', 'e', 9, 0, + /* 4450 */ 's', 'e', 't', 'g', 'e', 9, 0, + /* 4457 */ 'c', 'm', 'o', 'v', 'g', 'e', 9, 0, + /* 4465 */ 'j', 'e', 9, 0, + /* 4469 */ 'j', 'l', 'e', 9, 0, + /* 4474 */ 's', 'e', 't', 'l', 'e', 9, 0, + /* 4481 */ 'c', 'm', 'o', 'v', 'l', 'e', 9, 0, + /* 4489 */ 'j', 'n', 'e', 9, 0, + /* 4494 */ 'l', 'o', 'o', 'p', 'n', 'e', 9, 0, + /* 4502 */ 's', 'e', 't', 'n', 'e', 9, 0, + /* 4509 */ 'c', 'm', 'o', 'v', 'n', 'e', 9, 0, + /* 4517 */ 'l', 'o', 'o', 'p', 'e', 9, 0, + /* 4524 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 9, 0, + /* 4534 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 9, 0, + /* 4544 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 9, 0, + /* 4554 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 9, 0, + /* 4564 */ 't', 'p', 'a', 'u', 's', 'e', 9, 0, + /* 4572 */ 's', 'e', 't', 'e', 9, 0, + /* 4578 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 9, 0, + /* 4587 */ 'p', 't', 'w', 'r', 'i', 't', 'e', 9, 0, + /* 4596 */ 'c', 'l', 'd', 'e', 'm', 'o', 't', 'e', 9, 0, + /* 4606 */ 's', 'h', 'a', '1', 'n', 'e', 'x', 't', 'e', 9, 0, + /* 4617 */ 'f', 'n', 's', 'a', 'v', 'e', 9, 0, + /* 4625 */ 'f', 'x', 's', 'a', 'v', 'e', 9, 0, + /* 4633 */ 'c', 'm', 'o', 'v', 'e', 9, 0, + /* 4640 */ 'b', 's', 'f', 9, 0, + /* 4645 */ 'r', 'e', 't', 'f', 9, 0, + /* 4651 */ 'n', 'e', 'g', 9, 0, + /* 4656 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 9, 0, + /* 4665 */ 'j', 'g', 9, 0, + /* 4669 */ 'i', 'n', 'v', 'l', 'p', 'g', 9, 0, + /* 4677 */ 's', 'e', 't', 'g', 9, 0, + /* 4683 */ 'c', 'm', 'o', 'v', 'g', 9, 0, + /* 4690 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 9, 0, + /* 4700 */ 'f', 'x', 'c', 'h', 9, 0, + /* 4706 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'h', 9, 0, + /* 4717 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'q', 'h', 9, 0, + /* 4728 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'q', 'h', 9, 0, + /* 4740 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 9, 0, + /* 4749 */ 'p', 'u', 's', 'h', 9, 0, + /* 4755 */ 'b', 'l', 'c', 'i', 9, 0, + /* 4761 */ 'b', 'z', 'h', 'i', 9, 0, + /* 4767 */ 'f', 'c', 'o', 'm', 'i', 9, 0, + /* 4774 */ 'f', 'u', 'c', 'o', 'm', 'i', 9, 0, + /* 4782 */ 'c', 'v', 't', 't', 'p', 'd', '2', 'p', 'i', 9, 0, + /* 4793 */ 'c', 'v', 't', 'p', 'd', '2', 'p', 'i', 9, 0, + /* 4803 */ 'c', 'v', 't', 't', 'p', 's', '2', 'p', 'i', 9, 0, + /* 4814 */ 'c', 'v', 't', 'p', 's', '2', 'p', 'i', 9, 0, + /* 4824 */ 'f', 'c', 'o', 'm', 'p', 'i', 9, 0, + /* 4832 */ 'f', 'u', 'c', 'o', 'm', 'p', 'i', 9, 0, + /* 4841 */ 'm', 'o', 'v', 'd', 'i', 'r', 'i', 9, 0, + /* 4850 */ 'v', 'p', 'c', 'm', 'p', 'e', 's', 't', 'r', 'i', 9, 0, + /* 4862 */ 'v', 'p', 'c', 'm', 'p', 'i', 's', 't', 'r', 'i', 9, 0, + /* 4874 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 's', 'i', 9, 0, + /* 4886 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 'i', 9, 0, + /* 4897 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 's', 'i', 9, 0, + /* 4909 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'i', 9, 0, + /* 4920 */ 'b', 'l', 's', 'i', 9, 0, + /* 4926 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 'u', 's', 'i', 9, 0, + /* 4939 */ 'v', 'c', 'v', 't', 's', 'd', '2', 'u', 's', 'i', 9, 0, + /* 4951 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 'u', 's', 'i', 9, 0, + /* 4964 */ 'v', 'c', 'v', 't', 's', 's', '2', 'u', 's', 'i', 9, 0, + /* 4976 */ 'm', 'o', 'v', 'n', 't', 'i', 9, 0, + /* 4984 */ 'b', 'n', 'd', 'm', 'k', 9, 0, + /* 4991 */ 'b', 'l', 'c', 'm', 's', 'k', 9, 0, + /* 4999 */ 'b', 'l', 's', 'm', 's', 'k', 9, 0, + /* 5007 */ 't', 'z', 'm', 's', 'k', 9, 0, + /* 5014 */ 's', 'a', 'l', 9, 0, + /* 5019 */ 'l', 'w', 'p', 'v', 'a', 'l', 9, 0, + /* 5027 */ 'b', 'n', 'd', 'c', 'l', 9, 0, + /* 5034 */ 'r', 'c', 'l', 9, 0, + /* 5039 */ 's', 'h', 'l', 9, 0, + /* 5044 */ 'j', 'l', 9, 0, + /* 5048 */ 'l', 'c', 'a', 'l', 'l', 9, 0, + /* 5055 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 9, 0, + /* 5064 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 9, 0, + /* 5073 */ 'r', 'o', 'l', 9, 0, + /* 5078 */ 'a', 'r', 'p', 'l', 9, 0, + /* 5084 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'q', 'l', 9, 0, + /* 5095 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'q', 'l', 9, 0, + /* 5107 */ 'l', 's', 'l', 9, 0, + /* 5112 */ 's', 'e', 't', 'l', 9, 0, + /* 5118 */ 'p', 'f', 'm', 'u', 'l', 9, 0, + /* 5125 */ 'f', 'i', 'm', 'u', 'l', 9, 0, + /* 5132 */ 'c', 'm', 'o', 'v', 'l', 9, 0, + /* 5139 */ 'v', 'p', 'm', 'o', 'v', 'b', '2', 'm', 9, 0, + /* 5149 */ 'v', 'p', 'm', 'o', 'v', 'd', '2', 'm', 9, 0, + /* 5159 */ 'v', 'p', 'm', 'o', 'v', 'q', '2', 'm', 9, 0, + /* 5169 */ 'v', 'p', 'm', 'o', 'v', 'w', '2', 'm', 9, 0, + /* 5179 */ 'a', 'a', 'm', 9, 0, + /* 5184 */ 'f', 'c', 'o', 'm', 9, 0, + /* 5190 */ 'f', 'i', 'c', 'o', 'm', 9, 0, + /* 5197 */ 'f', 'u', 'c', 'o', 'm', 9, 0, + /* 5204 */ 'v', 'p', 'p', 'e', 'r', 'm', 9, 0, + /* 5212 */ 'v', 'p', 'c', 'm', 'p', 'e', 's', 't', 'r', 'm', 9, 0, + /* 5224 */ 'v', 'p', 'c', 'm', 'p', 'i', 's', 't', 'r', 'm', 9, 0, + /* 5236 */ 'b', 'n', 'd', 'c', 'n', 9, 0, + /* 5243 */ 'v', 'p', 'a', 'n', 'd', 'n', 9, 0, + /* 5251 */ 'x', 'b', 'e', 'g', 'i', 'n', 9, 0, + /* 5259 */ 'p', 'f', 'm', 'i', 'n', 9, 0, + /* 5266 */ 'v', 'm', 'x', 'o', 'n', 9, 0, + /* 5273 */ 'j', 'o', 9, 0, + /* 5277 */ 'j', 'n', 'o', 9, 0, + /* 5282 */ 's', 'e', 't', 'n', 'o', 9, 0, + /* 5289 */ 'c', 'm', 'o', 'v', 'n', 'o', 9, 0, + /* 5297 */ 's', 'e', 't', 'o', 9, 0, + /* 5303 */ 'c', 'm', 'o', 'v', 'o', 9, 0, + /* 5310 */ 'b', 's', 'w', 'a', 'p', 9, 0, + /* 5317 */ 'f', 's', 'u', 'b', 'p', 9, 0, + /* 5324 */ 'p', 'f', 'r', 'c', 'p', 9, 0, + /* 5331 */ 'f', 'a', 'd', 'd', 'p', 9, 0, + /* 5338 */ 'p', 'd', 'e', 'p', 9, 0, + /* 5344 */ 'f', 'f', 'r', 'e', 'e', 'p', 9, 0, + /* 5352 */ 'j', 'p', 9, 0, + /* 5356 */ 'f', 'm', 'u', 'l', 'p', 9, 0, + /* 5363 */ 'c', 'm', 'p', 9, 0, + /* 5368 */ 'l', 'j', 'm', 'p', 9, 0, + /* 5374 */ 'f', 'c', 'o', 'm', 'p', 9, 0, + /* 5381 */ 'f', 'i', 'c', 'o', 'm', 'p', 9, 0, + /* 5389 */ 'f', 'u', 'c', 'o', 'm', 'p', 9, 0, + /* 5397 */ 'j', 'n', 'p', 9, 0, + /* 5402 */ 's', 'e', 't', 'n', 'p', 9, 0, + /* 5409 */ 'c', 'm', 'o', 'v', 'n', 'p', 9, 0, + /* 5417 */ 'n', 'o', 'p', 9, 0, + /* 5422 */ 'l', 'o', 'o', 'p', 9, 0, + /* 5428 */ 'p', 'o', 'p', 9, 0, + /* 5433 */ 'f', 's', 'u', 'b', 'r', 'p', 9, 0, + /* 5441 */ 'f', 'd', 'i', 'v', 'r', 'p', 9, 0, + /* 5449 */ 'r', 's', 't', 'o', 'r', 's', 's', 'p', 9, 0, + /* 5459 */ 's', 'e', 't', 'p', 9, 0, + /* 5465 */ 'f', 's', 't', 'p', 9, 0, + /* 5471 */ 'f', 'i', 's', 't', 'p', 9, 0, + /* 5478 */ 'f', 'i', 's', 't', 't', 'p', 9, 0, + /* 5486 */ 'v', 'm', 'o', 'v', 'd', 'd', 'u', 'p', 9, 0, + /* 5496 */ 'v', 'm', 'o', 'v', 's', 'h', 'd', 'u', 'p', 9, 0, + /* 5507 */ 'v', 'm', 'o', 'v', 's', 'l', 'd', 'u', 'p', 9, 0, + /* 5518 */ 'f', 'd', 'i', 'v', 'p', 9, 0, + /* 5525 */ 'c', 'm', 'o', 'v', 'p', 9, 0, + /* 5532 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'm', 'b', '2', 'q', 9, 0, + /* 5549 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'q', 9, 0, + /* 5559 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'q', 9, 0, + /* 5569 */ 'm', 'o', 'v', 'd', 'q', '2', 'q', 9, 0, + /* 5578 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'q', 9, 0, + /* 5588 */ 'v', 'p', 's', 'h', 'a', 'q', 9, 0, + /* 5596 */ 'v', 'p', 's', 'r', 'a', 'q', 9, 0, + /* 5604 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'q', 9, 0, + /* 5614 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'q', 9, 0, + /* 5625 */ 'v', 'p', 's', 'u', 'b', 'q', 9, 0, + /* 5633 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'q', 9, 0, + /* 5644 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'q', 9, 0, + /* 5655 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 9, 0, + /* 5667 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 9, 0, + /* 5678 */ 'm', 'o', 'v', 'q', '2', 'd', 'q', 9, 0, + /* 5687 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'd', 'q', 9, 0, + /* 5699 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'd', 'q', 9, 0, + /* 5710 */ 'v', 'p', 'h', 's', 'u', 'b', 'd', 'q', 9, 0, + /* 5720 */ 'k', 'a', 'd', 'd', 'q', 9, 0, + /* 5727 */ 'v', 'p', 'a', 'd', 'd', 'q', 9, 0, + /* 5735 */ 'v', 'p', 'h', 'a', 'd', 'd', 'd', 'q', 9, 0, + /* 5745 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'd', 'q', 9, 0, + /* 5757 */ 'k', 'u', 'n', 'p', 'c', 'k', 'd', 'q', 9, 0, + /* 5767 */ 'v', 'p', 's', 'h', 'l', 'd', 'q', 9, 0, + /* 5776 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'd', 'q', 9, 0, + /* 5788 */ 'v', 'p', 's', 'l', 'l', 'd', 'q', 9, 0, + /* 5797 */ 'v', 'p', 's', 'r', 'l', 'd', 'q', 9, 0, + /* 5806 */ 'v', 'p', 'm', 'u', 'l', 'd', 'q', 9, 0, + /* 5815 */ 'k', 'a', 'n', 'd', 'q', 9, 0, + /* 5822 */ 'v', 'p', 'a', 'n', 'd', 'q', 9, 0, + /* 5830 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'q', 9, 0, + /* 5841 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'q', 'd', 'q', 9, 0, + /* 5854 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'q', 'd', 'q', 9, 0, + /* 5867 */ 'v', 'p', 'c', 'l', 'm', 'u', 'l', 'q', 'd', 'q', 9, 0, + /* 5879 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'q', 9, 0, + /* 5891 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'q', 9, 0, + /* 5904 */ 'v', 'p', 's', 'h', 'r', 'd', 'q', 9, 0, + /* 5913 */ 'v', 'm', 'o', 'v', 'n', 't', 'd', 'q', 9, 0, + /* 5923 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'd', 'q', 9, 0, + /* 5936 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'u', 'd', 'q', 9, 0, + /* 5948 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'u', 'd', 'q', 9, 0, + /* 5961 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'u', 'd', 'q', 9, 0, + /* 5973 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'd', 'q', 9, 0, + /* 5984 */ 'v', 'p', 'm', 'u', 'l', 'u', 'd', 'q', 9, 0, + /* 5994 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'd', 'q', 9, 0, + /* 6005 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'd', 'q', 9, 0, + /* 6016 */ 'p', 'f', 'c', 'm', 'p', 'e', 'q', 9, 0, + /* 6025 */ 'r', 'e', 't', 'f', 'q', 9, 0, + /* 6032 */ 'v', 'p', 't', 'e', 'r', 'n', 'l', 'o', 'g', 'q', 9, 0, + /* 6044 */ 'v', 'p', 's', 'h', 'l', 'q', 9, 0, + /* 6052 */ 'v', 'p', 's', 'l', 'l', 'q', 9, 0, + /* 6060 */ 'v', 'p', 'm', 'u', 'l', 'l', 'q', 9, 0, + /* 6069 */ 'v', 'p', 'r', 'o', 'l', 'q', 9, 0, + /* 6077 */ 'v', 'p', 's', 'r', 'l', 'q', 9, 0, + /* 6085 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'q', 9, 0, + /* 6095 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'q', 9, 0, + /* 6106 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'q', 9, 0, + /* 6117 */ 'v', 'p', 'c', 'o', 'm', 'q', 9, 0, + /* 6125 */ 'v', 'p', 'e', 'r', 'm', 'q', 9, 0, + /* 6133 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'q', 9, 0, + /* 6143 */ 'k', 'a', 'n', 'd', 'n', 'q', 9, 0, + /* 6151 */ 'v', 'p', 'a', 'n', 'd', 'n', 'q', 9, 0, + /* 6160 */ 'v', 'a', 'l', 'i', 'g', 'n', 'q', 9, 0, + /* 6169 */ 'v', 'p', 'c', 'm', 'p', 'q', 9, 0, + /* 6177 */ 'i', 'n', 'c', 's', 's', 'p', 'q', 9, 0, + /* 6186 */ 'r', 'd', 's', 's', 'p', 'q', 9, 0, + /* 6194 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'q', 'q', 9, 0, + /* 6206 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'q', 'q', 9, 0, + /* 6217 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'q', 'q', 9, 0, + /* 6229 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'q', 'q', 9, 0, + /* 6240 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'q', 9, 0, + /* 6250 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'q', 9, 0, + /* 6262 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'q', 9, 0, + /* 6275 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'q', 'q', 9, 0, + /* 6288 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'u', 'q', 'q', 9, 0, + /* 6300 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'u', 'q', 'q', 9, 0, + /* 6313 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'u', 'q', 'q', 9, 0, + /* 6325 */ 'k', 'o', 'r', 'q', 9, 0, + /* 6331 */ 'k', 'x', 'n', 'o', 'r', 'q', 9, 0, + /* 6339 */ 'v', 'p', 'o', 'r', 'q', 9, 0, + /* 6346 */ 'v', 'p', 'r', 'o', 'r', 'q', 9, 0, + /* 6354 */ 'k', 'x', 'o', 'r', 'q', 9, 0, + /* 6361 */ 'v', 'p', 'x', 'o', 'r', 'q', 9, 0, + /* 6369 */ 'v', 'p', 'i', 'n', 's', 'r', 'q', 9, 0, + /* 6378 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'q', 9, 0, + /* 6388 */ 'v', 'p', 'e', 'x', 't', 'r', 'q', 9, 0, + /* 6397 */ 'v', 'p', 'a', 'b', 's', 'q', 9, 0, + /* 6405 */ 'v', 'p', 'm', 'i', 'n', 's', 'q', 9, 0, + /* 6414 */ 's', 't', 'o', 's', 'q', 9, 0, + /* 6421 */ 'c', 'm', 'p', 's', 'q', 9, 0, + /* 6428 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'q', 9, 0, + /* 6441 */ 'w', 'r', 's', 's', 'q', 9, 0, + /* 6448 */ 'w', 'r', 'u', 's', 's', 'q', 9, 0, + /* 6456 */ 'm', 'o', 'v', 's', 'q', 9, 0, + /* 6463 */ 'v', 'p', 'm', 'a', 'x', 's', 'q', 9, 0, + /* 6472 */ 'v', 'p', 'c', 'o', 'n', 'f', 'l', 'i', 'c', 't', 'q', 9, 0, + /* 6485 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'q', 9, 0, + /* 6495 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'q', 9, 0, + /* 6505 */ 'v', 'p', 'l', 'z', 'c', 'n', 't', 'q', 9, 0, + /* 6515 */ 'm', 'o', 'v', 'n', 't', 'q', 9, 0, + /* 6523 */ 'k', 'n', 'o', 't', 'q', 9, 0, + /* 6530 */ 'v', 'p', 'r', 'o', 't', 'q', 9, 0, + /* 6538 */ 'i', 'n', 's', 'e', 'r', 't', 'q', 9, 0, + /* 6547 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'q', 9, 0, + /* 6561 */ 'k', 't', 'e', 's', 't', 'q', 9, 0, + /* 6569 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'q', 9, 0, + /* 6579 */ 'v', 'p', 'm', 'a', 'd', 'd', '5', '2', 'h', 'u', 'q', 9, 0, + /* 6592 */ 'v', 'p', 'm', 'a', 'd', 'd', '5', '2', 'l', 'u', 'q', 9, 0, + /* 6605 */ 'v', 'p', 'c', 'o', 'm', 'u', 'q', 9, 0, + /* 6614 */ 'v', 'p', 'm', 'i', 'n', 'u', 'q', 9, 0, + /* 6623 */ 'v', 'p', 'c', 'm', 'p', 'u', 'q', 9, 0, + /* 6632 */ 'v', 'p', 'm', 'a', 'x', 'u', 'q', 9, 0, + /* 6641 */ 'v', 'p', 's', 'r', 'a', 'v', 'q', 9, 0, + /* 6650 */ 'v', 'p', 's', 'h', 'l', 'd', 'v', 'q', 9, 0, + /* 6660 */ 'v', 'p', 's', 'h', 'r', 'd', 'v', 'q', 9, 0, + /* 6670 */ 'v', 'p', 's', 'l', 'l', 'v', 'q', 9, 0, + /* 6679 */ 'v', 'p', 'r', 'o', 'l', 'v', 'q', 9, 0, + /* 6688 */ 'v', 'p', 's', 'r', 'l', 'v', 'q', 9, 0, + /* 6697 */ 'v', 'p', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'q', 9, 0, + /* 6709 */ 'v', 'm', 'o', 'v', 'q', 9, 0, + /* 6716 */ 'v', 'p', 'r', 'o', 'r', 'v', 'q', 9, 0, + /* 6725 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 'q', 9, 0, + /* 6735 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'w', 'q', 9, 0, + /* 6746 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'q', 9, 0, + /* 6757 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'q', 9, 0, + /* 6768 */ 'v', 'm', 'c', 'l', 'e', 'a', 'r', 9, 0, + /* 6777 */ 'l', 'a', 'r', 9, 0, + /* 6782 */ 's', 'a', 'r', 9, 0, + /* 6787 */ 'p', 'f', 's', 'u', 'b', 'r', 9, 0, + /* 6795 */ 'f', 'i', 's', 'u', 'b', 'r', 9, 0, + /* 6803 */ 'r', 'c', 'r', 9, 0, + /* 6808 */ 'e', 'n', 't', 'e', 'r', 9, 0, + /* 6815 */ 's', 'h', 'r', 9, 0, + /* 6820 */ 'v', 'p', 'a', 'l', 'i', 'g', 'n', 'r', 9, 0, + /* 6830 */ 'v', 'p', 'o', 'r', 9, 0, + /* 6836 */ 'r', 'o', 'r', 9, 0, + /* 6841 */ 'u', 'm', 'o', 'n', 'i', 't', 'o', 'r', 9, 0, + /* 6851 */ 'f', 'r', 's', 't', 'o', 'r', 9, 0, + /* 6859 */ 'f', 'x', 'r', 's', 't', 'o', 'r', 9, 0, + /* 6868 */ 'v', 'p', 'x', 'o', 'r', 9, 0, + /* 6875 */ 'v', 'e', 'r', 'r', 9, 0, + /* 6881 */ 'b', 's', 'r', 9, 0, + /* 6886 */ 'v', 'l', 'd', 'm', 'x', 'c', 's', 'r', 9, 0, + /* 6896 */ 'v', 's', 't', 'm', 'x', 'c', 's', 'r', 9, 0, + /* 6906 */ 'b', 'l', 's', 'r', 9, 0, + /* 6912 */ 'b', 't', 'r', 9, 0, + /* 6917 */ 'l', 't', 'r', 9, 0, + /* 6922 */ 's', 't', 'r', 9, 0, + /* 6927 */ 'b', 'e', 'x', 't', 'r', 9, 0, + /* 6934 */ 'f', 'd', 'i', 'v', 'r', 9, 0, + /* 6941 */ 'f', 'i', 'd', 'i', 'v', 'r', 9, 0, + /* 6949 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 0, + /* 6957 */ 'b', 'l', 'c', 's', 9, 0, + /* 6963 */ 'l', 'd', 's', 9, 0, + /* 6968 */ 'v', 'p', '4', 'd', 'p', 'w', 's', 's', 'd', 's', 9, 0, + /* 6980 */ 'v', 'p', 'd', 'p', 'w', 's', 's', 'd', 's', 9, 0, + /* 6991 */ 'v', 'p', 'd', 'p', 'b', 'u', 's', 'd', 's', 9, 0, + /* 7002 */ 'l', 'e', 's', 9, 0, + /* 7007 */ 'x', 's', 'a', 'v', 'e', 's', 9, 0, + /* 7015 */ 'l', 'f', 's', 9, 0, + /* 7020 */ 'l', 'g', 's', 9, 0, + /* 7025 */ 'j', 's', 9, 0, + /* 7029 */ 'l', 'w', 'p', 'i', 'n', 's', 9, 0, + /* 7037 */ 'j', 'n', 's', 9, 0, + /* 7042 */ 's', 'e', 't', 'n', 's', 9, 0, + /* 7049 */ 'c', 'm', 'o', 'v', 'n', 's', 9, 0, + /* 7057 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '3', '1', 'p', 's', 9, 0, + /* 7073 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 's', 9, 0, + /* 7086 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 's', 9, 0, + /* 7100 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '3', '1', 'p', 's', 9, 0, + /* 7116 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 's', 9, 0, + /* 7129 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 's', 9, 0, + /* 7143 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 's', 9, 0, + /* 7159 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 's', 9, 0, + /* 7172 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 's', 9, 0, + /* 7186 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, + /* 7202 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, + /* 7215 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, + /* 7229 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 9, 0, + /* 7240 */ 'v', 'c', 'v', 't', 'p', 'h', '2', 'p', 's', 9, 0, + /* 7251 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'p', 's', 9, 0, + /* 7262 */ 'c', 'v', 't', 'p', 'i', '2', 'p', 's', 9, 0, + /* 7272 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', '2', 'p', 's', 9, 0, + /* 7284 */ 'v', 'e', 'x', 'p', '2', 'p', 's', 9, 0, + /* 7293 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 's', 9, 0, + /* 7304 */ 'v', 'c', 'v', 't', 'u', 'd', 'q', '2', 'p', 's', 9, 0, + /* 7316 */ 'v', 'c', 'v', 't', 'q', 'q', '2', 'p', 's', 9, 0, + /* 7327 */ 'v', 'c', 'v', 't', 'u', 'q', 'q', '2', 'p', 's', 9, 0, + /* 7339 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'p', 's', 9, 0, + /* 7350 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, + /* 7366 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, + /* 7379 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, + /* 7393 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, + /* 7409 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, + /* 7422 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, + /* 7436 */ 'v', 'r', 'c', 'p', '1', '4', 'p', 's', 9, 0, + /* 7446 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 'p', 's', 9, 0, + /* 7458 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 's', 9, 0, + /* 7468 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 's', 9, 0, + /* 7480 */ 'v', 'm', 'o', 'v', 'a', 'p', 's', 9, 0, + /* 7489 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', 'p', 's', 9, 0, + /* 7502 */ 'v', 'a', 'd', 'd', 's', 'u', 'b', 'p', 's', 9, 0, + /* 7513 */ 'v', 'h', 's', 'u', 'b', 'p', 's', 9, 0, + /* 7522 */ 'v', 'f', 'm', 's', 'u', 'b', 'p', 's', 9, 0, + /* 7532 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 'p', 's', 9, 0, + /* 7543 */ 'v', 's', 'u', 'b', 'p', 's', 9, 0, + /* 7551 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 7564 */ 'v', 'h', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 7573 */ 'v', '4', 'f', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 7584 */ 'v', 'f', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 7594 */ 'v', '4', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 7606 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 7617 */ 'v', 'a', 'd', 'd', 'p', 's', 9, 0, + /* 7625 */ 'v', 'e', 'x', 'p', 'a', 'n', 'd', 'p', 's', 9, 0, + /* 7636 */ 'v', 'a', 'n', 'd', 'p', 's', 9, 0, + /* 7644 */ 'v', 'b', 'l', 'e', 'n', 'd', 'p', 's', 9, 0, + /* 7654 */ 'v', 'r', 'o', 'u', 'n', 'd', 'p', 's', 9, 0, + /* 7664 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 's', 9, 0, + /* 7676 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'p', 's', 9, 0, + /* 7689 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 'p', 's', 9, 0, + /* 7700 */ 'v', 'r', 'a', 'n', 'g', 'e', 'p', 's', 9, 0, + /* 7710 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 'p', 's', 9, 0, + /* 7723 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 'p', 's', 9, 0, + /* 7734 */ 'v', 's', 'h', 'u', 'f', 'p', 's', 9, 0, + /* 7743 */ 'v', 'u', 'n', 'p', 'c', 'k', 'h', 'p', 's', 9, 0, + /* 7754 */ 'v', 'm', 'o', 'v', 'l', 'h', 'p', 's', 9, 0, + /* 7764 */ 'v', 'm', 'o', 'v', 'h', 'p', 's', 9, 0, + /* 7773 */ 'v', 'm', 'o', 'v', 'm', 's', 'k', 'p', 's', 9, 0, + /* 7784 */ 'v', 'm', 'o', 'v', 'h', 'l', 'p', 's', 9, 0, + /* 7794 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 's', 9, 0, + /* 7805 */ 'v', 'u', 'n', 'p', 'c', 'k', 'l', 'p', 's', 9, 0, + /* 7816 */ 'v', 'm', 'u', 'l', 'p', 's', 9, 0, + /* 7824 */ 'v', 'm', 'o', 'v', 'l', 'p', 's', 9, 0, + /* 7833 */ 'v', 'b', 'l', 'e', 'n', 'd', 'm', 'p', 's', 9, 0, + /* 7844 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 'p', 's', 9, 0, + /* 7857 */ 'v', 'p', 'e', 'r', 'm', 'p', 's', 9, 0, + /* 7866 */ 'v', 'a', 'n', 'd', 'n', 'p', 's', 9, 0, + /* 7875 */ 'v', 'm', 'i', 'n', 'p', 's', 9, 0, + /* 7883 */ 'v', 'r', 'c', 'p', 'p', 's', 9, 0, + /* 7891 */ 'v', 'd', 'p', 'p', 's', 9, 0, + /* 7898 */ 'v', 'c', 'm', 'p', 'p', 's', 9, 0, + /* 7906 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 'p', 's', 9, 0, + /* 7917 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 's', 9, 0, + /* 7929 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'p', 's', 9, 0, + /* 7942 */ 'v', 'o', 'r', 'p', 's', 9, 0, + /* 7949 */ 'v', 'x', 'o', 'r', 'p', 's', 9, 0, + /* 7957 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 's', 9, 0, + /* 7969 */ 'v', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'p', 's', 9, 0, + /* 7982 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'p', 's', 9, 0, + /* 7994 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 'p', 's', 9, 0, + /* 8006 */ 'v', 'm', 'o', 'v', 'n', 't', 'p', 's', 9, 0, + /* 8016 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'p', 's', 9, 0, + /* 8027 */ 'v', 'r', 's', 'q', 'r', 't', 'p', 's', 9, 0, + /* 8037 */ 'v', 's', 'q', 'r', 't', 'p', 's', 9, 0, + /* 8046 */ 'v', 't', 'e', 's', 't', 'p', 's', 9, 0, + /* 8055 */ 'v', 'm', 'o', 'v', 'u', 'p', 's', 9, 0, + /* 8064 */ 'v', 'b', 'l', 'e', 'n', 'd', 'v', 'p', 's', 9, 0, + /* 8075 */ 'v', 'd', 'i', 'v', 'p', 's', 9, 0, + /* 8083 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'p', 's', 9, 0, + /* 8095 */ 'v', 'm', 'a', 'x', 'p', 's', 9, 0, + /* 8103 */ 'v', 'f', 'r', 'c', 'z', 'p', 's', 9, 0, + /* 8112 */ 'x', 'r', 's', 't', 'o', 'r', 's', 9, 0, + /* 8121 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 's', 's', 9, 0, + /* 8134 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 's', 's', 9, 0, + /* 8148 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 's', 9, 0, + /* 8161 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 's', 9, 0, + /* 8175 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 's', 's', 9, 0, + /* 8188 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 's', 's', 9, 0, + /* 8202 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 's', 9, 0, + /* 8215 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 's', 9, 0, + /* 8229 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 's', 9, 0, + /* 8240 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 's', 9, 0, + /* 8251 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 's', 9, 0, + /* 8263 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 9, 0, + /* 8276 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 9, 0, + /* 8290 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 9, 0, + /* 8303 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 9, 0, + /* 8317 */ 'v', 'r', 'c', 'p', '1', '4', 's', 's', 9, 0, + /* 8327 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 's', 's', 9, 0, + /* 8339 */ 'v', 'r', 'c', 'p', '2', '8', 's', 's', 9, 0, + /* 8349 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 's', 9, 0, + /* 8361 */ 'v', 'f', 'm', 's', 'u', 'b', 's', 's', 9, 0, + /* 8371 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 's', 9, 0, + /* 8382 */ 'v', 's', 'u', 'b', 's', 's', 9, 0, + /* 8390 */ 'v', '4', 'f', 'm', 'a', 'd', 'd', 's', 's', 9, 0, + /* 8401 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 's', 9, 0, + /* 8411 */ 'v', '4', 'f', 'n', 'm', 'a', 'd', 'd', 's', 's', 9, 0, + /* 8423 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 's', 9, 0, + /* 8434 */ 'v', 'a', 'd', 'd', 's', 's', 9, 0, + /* 8442 */ 'v', 'r', 'o', 'u', 'n', 'd', 's', 's', 9, 0, + /* 8452 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 's', 's', 9, 0, + /* 8463 */ 'v', 'r', 'a', 'n', 'g', 'e', 's', 's', 9, 0, + /* 8473 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 's', 's', 9, 0, + /* 8486 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 's', 's', 9, 0, + /* 8497 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 's', 9, 0, + /* 8507 */ 'v', 'c', 'o', 'm', 'i', 's', 's', 9, 0, + /* 8516 */ 'v', 'm', 'u', 'l', 's', 's', 9, 0, + /* 8524 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 's', 's', 9, 0, + /* 8537 */ 'v', 'm', 'i', 'n', 's', 's', 9, 0, + /* 8545 */ 'v', 'r', 'c', 'p', 's', 's', 9, 0, + /* 8553 */ 'v', 'c', 'm', 'p', 's', 's', 9, 0, + /* 8561 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 's', 's', 9, 0, + /* 8572 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 's', 's', 9, 0, + /* 8584 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 's', 's', 9, 0, + /* 8596 */ 'm', 'o', 'v', 'n', 't', 's', 's', 9, 0, + /* 8605 */ 'v', 'r', 's', 'q', 'r', 't', 's', 's', 9, 0, + /* 8615 */ 'v', 's', 'q', 'r', 't', 's', 's', 9, 0, + /* 8624 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 's', 9, 0, + /* 8638 */ 'v', 'd', 'i', 'v', 's', 's', 9, 0, + /* 8646 */ 'v', 'm', 'o', 'v', 's', 's', 9, 0, + /* 8654 */ 'v', 'm', 'a', 'x', 's', 's', 9, 0, + /* 8662 */ 'v', 'f', 'r', 'c', 'z', 's', 's', 9, 0, + /* 8671 */ 'b', 't', 's', 9, 0, + /* 8676 */ 's', 'e', 't', 's', 9, 0, + /* 8682 */ 'c', 'm', 'o', 'v', 's', 9, 0, + /* 8689 */ 'b', 't', 9, 0, + /* 8693 */ 'l', 'g', 'd', 't', 9, 0, + /* 8699 */ 's', 'g', 'd', 't', 9, 0, + /* 8705 */ 'l', 'i', 'd', 't', 9, 0, + /* 8711 */ 's', 'i', 'd', 't', 9, 0, + /* 8717 */ 'l', 'l', 'd', 't', 9, 0, + /* 8723 */ 's', 'l', 'd', 't', 9, 0, + /* 8729 */ 'r', 'e', 't', 9, 0, + /* 8734 */ 'p', 'f', 'c', 'm', 'p', 'g', 't', 9, 0, + /* 8743 */ 'u', 'm', 'w', 'a', 'i', 't', 9, 0, + /* 8751 */ 'p', 'o', 'p', 'c', 'n', 't', 9, 0, + /* 8759 */ 'l', 'z', 'c', 'n', 't', 9, 0, + /* 8766 */ 't', 'z', 'c', 'n', 't', 9, 0, + /* 8773 */ 'i', 'n', 't', 9, 0, + /* 8778 */ 'n', 'o', 't', 9, 0, + /* 8783 */ 'i', 'n', 'v', 'e', 'p', 't', 9, 0, + /* 8791 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 9, 0, + /* 8801 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 'o', 'p', 't', 9, 0, + /* 8813 */ 'x', 'a', 'b', 'o', 'r', 't', 9, 0, + /* 8821 */ 'p', 'f', 'r', 's', 'q', 'r', 't', 9, 0, + /* 8830 */ 'v', 'a', 'e', 's', 'd', 'e', 'c', 'l', 'a', 's', 't', 9, 0, + /* 8843 */ 'v', 'a', 'e', 's', 'e', 'n', 'c', 'l', 'a', 's', 't', 9, 0, + /* 8856 */ 'v', 'p', 't', 'e', 's', 't', 9, 0, + /* 8864 */ 'f', 's', 't', 9, 0, + /* 8869 */ 'f', 'i', 's', 't', 9, 0, + /* 8875 */ 'v', 'a', 'e', 's', 'k', 'e', 'y', 'g', 'e', 'n', 'a', 's', 's', 'i', 's', 't', 9, 0, + /* 8893 */ 'v', 'm', 'p', 't', 'r', 's', 't', 9, 0, + /* 8902 */ 'o', 'u', 't', 9, 0, + /* 8907 */ 'p', 'e', 'x', 't', 9, 0, + /* 8913 */ 'b', 'n', 'd', 'c', 'u', 9, 0, + /* 8920 */ 'v', 'l', 'd', 'd', 'q', 'u', 9, 0, + /* 8928 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'd', 'q', 'u', 9, 0, + /* 8941 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', 9, 0, + /* 8950 */ 'f', 'd', 'i', 'v', 9, 0, + /* 8956 */ 'f', 'i', 'd', 'i', 'v', 9, 0, + /* 8963 */ 'f', 'l', 'd', 'e', 'n', 'v', 9, 0, + /* 8971 */ 'f', 'n', 's', 't', 'e', 'n', 'v', 9, 0, + /* 8980 */ 'v', 'p', 'c', 'm', 'o', 'v', 9, 0, + /* 8988 */ 'b', 'n', 'd', 'm', 'o', 'v', 9, 0, + /* 8996 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'w', 9, 0, + /* 9006 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'w', 9, 0, + /* 9016 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'w', 9, 0, + /* 9026 */ 'v', 'p', 's', 'h', 'a', 'w', 9, 0, + /* 9034 */ 'v', 'p', 's', 'r', 'a', 'w', 9, 0, + /* 9042 */ 'v', 'p', 'h', 's', 'u', 'b', 'b', 'w', 9, 0, + /* 9052 */ 'v', 'd', 'b', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, + /* 9063 */ 'v', 'm', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, + /* 9073 */ 'v', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, + /* 9082 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'w', 9, 0, + /* 9092 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'b', 'w', 9, 0, + /* 9104 */ 'k', 'u', 'n', 'p', 'c', 'k', 'b', 'w', 9, 0, + /* 9114 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'b', 'w', 9, 0, + /* 9126 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'w', 9, 0, + /* 9137 */ 'v', 'p', 'h', 's', 'u', 'b', 'w', 9, 0, + /* 9146 */ 'v', 'p', 's', 'u', 'b', 'w', 9, 0, + /* 9154 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'w', 9, 0, + /* 9165 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'w', 9, 0, + /* 9176 */ 'f', 'l', 'd', 'c', 'w', 9, 0, + /* 9183 */ 'f', 'n', 's', 't', 'c', 'w', 9, 0, + /* 9191 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 9, 0, + /* 9200 */ 'k', 'a', 'd', 'd', 'w', 9, 0, + /* 9207 */ 'v', 'p', 'a', 'd', 'd', 'w', 9, 0, + /* 9215 */ 'v', 'p', 's', 'h', 'l', 'd', 'w', 9, 0, + /* 9224 */ 'k', 'a', 'n', 'd', 'w', 9, 0, + /* 9231 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'w', 9, 0, + /* 9242 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'w', 9, 0, + /* 9252 */ 'v', 'p', 's', 'h', 'r', 'd', 'w', 9, 0, + /* 9261 */ 'v', 'p', 'a', 'c', 'k', 's', 's', 'd', 'w', 9, 0, + /* 9272 */ 'v', 'p', 'a', 'c', 'k', 'u', 's', 'd', 'w', 9, 0, + /* 9283 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'd', 'w', 9, 0, + /* 9294 */ 'v', 'p', 'm', 'o', 'v', 's', 'd', 'w', 9, 0, + /* 9304 */ 'v', 'p', 'm', 'o', 'v', 'd', 'w', 9, 0, + /* 9313 */ 'p', 'i', '2', 'f', 'w', 9, 0, + /* 9320 */ 'p', 's', 'h', 'u', 'f', 'w', 9, 0, + /* 9328 */ 'v', 'p', 'a', 'v', 'g', 'w', 9, 0, + /* 9336 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'w', 9, 0, + /* 9347 */ 'v', 'p', 's', 'h', 'u', 'f', 'h', 'w', 9, 0, + /* 9357 */ 'v', 'p', 'm', 'u', 'l', 'h', 'w', 9, 0, + /* 9366 */ 'p', 'f', '2', 'i', 'w', 9, 0, + /* 9373 */ 'v', 'p', 's', 'h', 'u', 'f', 'l', 'w', 9, 0, + /* 9383 */ 'v', 'p', 's', 'h', 'l', 'w', 9, 0, + /* 9391 */ 'v', 'p', 's', 'l', 'l', 'w', 9, 0, + /* 9399 */ 'v', 'p', 'm', 'u', 'l', 'l', 'w', 9, 0, + /* 9408 */ 'v', 'p', 's', 'r', 'l', 'w', 9, 0, + /* 9416 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'w', 9, 0, + /* 9426 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'w', 9, 0, + /* 9437 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'w', 9, 0, + /* 9448 */ 'v', 'p', 'c', 'o', 'm', 'w', 9, 0, + /* 9456 */ 'v', 'p', 'e', 'r', 'm', 'w', 9, 0, + /* 9464 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'w', 9, 0, + /* 9474 */ 'k', 'a', 'n', 'd', 'n', 'w', 9, 0, + /* 9482 */ 'v', 'p', 's', 'i', 'g', 'n', 'w', 9, 0, + /* 9491 */ 'v', 'p', 'c', 'm', 'p', 'w', 9, 0, + /* 9499 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'w', 9, 0, + /* 9509 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'w', 9, 0, + /* 9520 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'w', 9, 0, + /* 9530 */ 'v', 'p', 'm', 'o', 'v', 'q', 'w', 9, 0, + /* 9539 */ 'v', 'e', 'r', 'w', 9, 0, + /* 9545 */ 'p', 'm', 'u', 'l', 'h', 'r', 'w', 9, 0, + /* 9554 */ 'k', 'o', 'r', 'w', 9, 0, + /* 9560 */ 'k', 'x', 'n', 'o', 'r', 'w', 9, 0, + /* 9568 */ 'k', 'x', 'o', 'r', 'w', 9, 0, + /* 9575 */ 'v', 'p', 'i', 'n', 's', 'r', 'w', 9, 0, + /* 9584 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'w', 9, 0, + /* 9594 */ 'v', 'p', 'e', 'x', 't', 'r', 'w', 9, 0, + /* 9603 */ 'v', 'p', 'a', 'b', 's', 'w', 9, 0, + /* 9611 */ 'v', 'p', 'm', 'a', 'd', 'd', 'u', 'b', 's', 'w', 9, 0, + /* 9623 */ 'v', 'p', 'h', 's', 'u', 'b', 's', 'w', 9, 0, + /* 9633 */ 'v', 'p', 's', 'u', 'b', 's', 'w', 9, 0, + /* 9642 */ 'v', 'p', 'h', 'a', 'd', 'd', 's', 'w', 9, 0, + /* 9652 */ 'v', 'p', 'a', 'd', 'd', 's', 'w', 9, 0, + /* 9661 */ 'l', 'm', 's', 'w', 9, 0, + /* 9667 */ 's', 'm', 's', 'w', 9, 0, + /* 9673 */ 'v', 'p', 'm', 'i', 'n', 's', 'w', 9, 0, + /* 9682 */ 's', 't', 'o', 's', 'w', 9, 0, + /* 9689 */ 'c', 'm', 'p', 's', 'w', 9, 0, + /* 9696 */ 'v', 'p', 'm', 'u', 'l', 'h', 'r', 's', 'w', 9, 0, + /* 9707 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'w', 9, 0, + /* 9720 */ 'f', 'n', 's', 't', 's', 'w', 9, 0, + /* 9728 */ 'v', 'p', 's', 'u', 'b', 'u', 's', 'w', 9, 0, + /* 9738 */ 'v', 'p', 'a', 'd', 'd', 'u', 's', 'w', 9, 0, + /* 9748 */ 'm', 'o', 'v', 's', 'w', 9, 0, + /* 9755 */ 'v', 'p', 'm', 'a', 'x', 's', 'w', 9, 0, + /* 9764 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'w', 9, 0, + /* 9774 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'w', 9, 0, + /* 9784 */ 'k', 'n', 'o', 't', 'w', 9, 0, + /* 9791 */ 'v', 'p', 'r', 'o', 't', 'w', 9, 0, + /* 9799 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'w', 9, 0, + /* 9813 */ 'k', 't', 'e', 's', 't', 'w', 9, 0, + /* 9821 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'w', 9, 0, + /* 9831 */ 'v', 'p', 'm', 'u', 'l', 'h', 'u', 'w', 9, 0, + /* 9841 */ 'v', 'p', 'c', 'o', 'm', 'u', 'w', 9, 0, + /* 9850 */ 'v', 'p', 'm', 'i', 'n', 'u', 'w', 9, 0, + /* 9859 */ 'v', 'p', 'c', 'm', 'p', 'u', 'w', 9, 0, + /* 9868 */ 'v', 'p', 'h', 'm', 'i', 'n', 'p', 'o', 's', 'u', 'w', 9, 0, + /* 9881 */ 'v', 'p', 'm', 'a', 'x', 'u', 'w', 9, 0, + /* 9890 */ 'v', 'p', 's', 'r', 'a', 'v', 'w', 9, 0, + /* 9899 */ 'v', 'p', 's', 'h', 'l', 'd', 'v', 'w', 9, 0, + /* 9909 */ 'v', 'p', 's', 'h', 'r', 'd', 'v', 'w', 9, 0, + /* 9919 */ 'v', 'p', 's', 'l', 'l', 'v', 'w', 9, 0, + /* 9928 */ 'v', 'p', 's', 'r', 'l', 'v', 'w', 9, 0, + /* 9937 */ 'k', 'm', 'o', 'v', 'w', 9, 0, + /* 9944 */ 'v', 'p', 'm', 'a', 'c', 's', 'w', 'w', 9, 0, + /* 9954 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'w', 'w', 9, 0, + /* 9965 */ 'p', 'f', 'm', 'a', 'x', 9, 0, + /* 9972 */ 'a', 'd', 'c', 'x', 9, 0, + /* 9978 */ 'b', 'n', 'd', 'l', 'd', 'x', 9, 0, + /* 9986 */ 's', 'h', 'l', 'x', 9, 0, + /* 9992 */ 'm', 'u', 'l', 'x', 9, 0, + /* 9998 */ 'a', 'd', 'o', 'x', 9, 0, + /* 10004 */ 's', 'a', 'r', 'x', 9, 0, + /* 10010 */ 's', 'h', 'r', 'x', 9, 0, + /* 10016 */ 'r', 'o', 'r', 'x', 9, 0, + /* 10022 */ 'm', 'o', 'v', 's', 'x', 9, 0, + /* 10029 */ 'b', 'n', 'd', 's', 't', 'x', 9, 0, + /* 10037 */ 'm', 'o', 'v', 'z', 'x', 9, 0, + /* 10044 */ 'c', 'l', 'r', 's', 's', 'b', 's', 'y', 9, 0, + /* 10054 */ 'j', 'e', 'c', 'x', 'z', 9, 0, + /* 10061 */ 'j', 'c', 'x', 'z', 9, 0, + /* 10067 */ 'j', 'r', 'c', 'x', 'z', 9, 0, + /* 10074 */ 'f', 'c', 'm', 'o', 'v', 'n', 'b', 9, 's', 't', '(', '0', ')', ',', 32, 0, + /* 10090 */ 'f', 'c', 'm', 'o', 'v', 'b', 9, 's', 't', '(', '0', ')', ',', 32, 0, + /* 10105 */ 'f', 'c', 'm', 'o', 'v', 'n', 'b', 'e', 9, 's', 't', '(', '0', ')', ',', 32, 0, + /* 10122 */ 'f', 'c', 'm', 'o', 'v', 'b', 'e', 9, 's', 't', '(', '0', ')', ',', 32, 0, + /* 10138 */ 'f', 'c', 'm', 'o', 'v', 'n', 'e', 9, 's', 't', '(', '0', ')', ',', 32, 0, + /* 10154 */ 'f', 'c', 'm', 'o', 'v', 'e', 9, 's', 't', '(', '0', ')', ',', 32, 0, + /* 10169 */ 'f', 'c', 'm', 'o', 'v', 'n', 'u', 9, 's', 't', '(', '0', ')', ',', 32, 0, + /* 10185 */ 'f', 'c', 'm', 'o', 'v', 'u', 9, 's', 't', '(', '0', ')', ',', 32, 0, + /* 10200 */ 's', 'b', 'b', 9, 'a', 'l', ',', 32, 0, + /* 10209 */ 's', 'c', 'a', 's', 'b', 9, 'a', 'l', ',', 32, 0, + /* 10220 */ 'l', 'o', 'd', 's', 'b', 9, 'a', 'l', ',', 32, 0, + /* 10231 */ 's', 'u', 'b', 9, 'a', 'l', ',', 32, 0, + /* 10240 */ 'a', 'd', 'c', 9, 'a', 'l', ',', 32, 0, + /* 10249 */ 'a', 'd', 'd', 9, 'a', 'l', ',', 32, 0, + /* 10258 */ 'a', 'n', 'd', 9, 'a', 'l', ',', 32, 0, + /* 10267 */ 'i', 'n', 9, 'a', 'l', ',', 32, 0, + /* 10275 */ 'c', 'm', 'p', 9, 'a', 'l', ',', 32, 0, + /* 10284 */ 'x', 'o', 'r', 9, 'a', 'l', ',', 32, 0, + /* 10293 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 'a', 'l', ',', 32, 0, + /* 10305 */ 't', 'e', 's', 't', 9, 'a', 'l', ',', 32, 0, + /* 10315 */ 'm', 'o', 'v', 9, 'a', 'l', ',', 32, 0, + /* 10324 */ 's', 'b', 'b', 9, 'a', 'x', ',', 32, 0, + /* 10333 */ 's', 'u', 'b', 9, 'a', 'x', ',', 32, 0, + /* 10342 */ 'a', 'd', 'c', 9, 'a', 'x', ',', 32, 0, + /* 10351 */ 'a', 'd', 'd', 9, 'a', 'x', ',', 32, 0, + /* 10360 */ 'a', 'n', 'd', 9, 'a', 'x', ',', 32, 0, + /* 10369 */ 'i', 'n', 9, 'a', 'x', ',', 32, 0, + /* 10377 */ 'c', 'm', 'p', 9, 'a', 'x', ',', 32, 0, + /* 10386 */ 'x', 'o', 'r', 9, 'a', 'x', ',', 32, 0, + /* 10395 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 'a', 'x', ',', 32, 0, + /* 10407 */ 't', 'e', 's', 't', 9, 'a', 'x', ',', 32, 0, + /* 10417 */ 'm', 'o', 'v', 9, 'a', 'x', ',', 32, 0, + /* 10426 */ 's', 'c', 'a', 's', 'w', 9, 'a', 'x', ',', 32, 0, + /* 10437 */ 'l', 'o', 'd', 's', 'w', 9, 'a', 'x', ',', 32, 0, + /* 10448 */ 's', 'b', 'b', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10458 */ 's', 'u', 'b', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10468 */ 'a', 'd', 'c', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10478 */ 'a', 'd', 'd', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10488 */ 'a', 'n', 'd', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10498 */ 's', 'c', 'a', 's', 'd', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10510 */ 'l', 'o', 'd', 's', 'd', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10522 */ 'i', 'n', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10531 */ 'c', 'm', 'p', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10541 */ 'x', 'o', 'r', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10551 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10564 */ 't', 'e', 's', 't', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10575 */ 'm', 'o', 'v', 9, 'e', 'a', 'x', ',', 32, 0, + /* 10585 */ 's', 'b', 'b', 9, 'r', 'a', 'x', ',', 32, 0, + /* 10595 */ 's', 'u', 'b', 9, 'r', 'a', 'x', ',', 32, 0, + /* 10605 */ 'a', 'd', 'c', 9, 'r', 'a', 'x', ',', 32, 0, + /* 10615 */ 'a', 'd', 'd', 9, 'r', 'a', 'x', ',', 32, 0, + /* 10625 */ 'a', 'n', 'd', 9, 'r', 'a', 'x', ',', 32, 0, + /* 10635 */ 'c', 'm', 'p', 9, 'r', 'a', 'x', ',', 32, 0, + /* 10645 */ 's', 'c', 'a', 's', 'q', 9, 'r', 'a', 'x', ',', 32, 0, + /* 10657 */ 'l', 'o', 'd', 's', 'q', 9, 'r', 'a', 'x', ',', 32, 0, + /* 10669 */ 'x', 'o', 'r', 9, 'r', 'a', 'x', ',', 32, 0, + /* 10679 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 'r', 'a', 'x', ',', 32, 0, + /* 10692 */ 't', 'e', 's', 't', 9, 'r', 'a', 'x', ',', 32, 0, + /* 10703 */ 'm', 'o', 'v', 9, 'r', 'a', 'x', ',', 32, 0, + /* 10713 */ 'o', 'u', 't', 's', 'b', 9, 'd', 'x', ',', 32, 0, + /* 10724 */ 'o', 'u', 't', 's', 'd', 9, 'd', 'x', ',', 32, 0, + /* 10735 */ 'o', 'u', 't', 's', 'w', 9, 'd', 'x', ',', 32, 0, + /* 10746 */ 'f', 'b', 'l', 'd', 9, 't', 'b', 'y', 't', 'e', 32, 'p', 't', 'r', 32, 0, + /* 10762 */ 'f', 'b', 's', 't', 'p', 9, 't', 'b', 'y', 't', 'e', 32, 'p', 't', 'r', 32, 0, + /* 10779 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, + /* 10810 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 10834 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 10859 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, + /* 10882 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, + /* 10905 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, + /* 10927 */ 'u', 'd', '0', 0, + /* 10931 */ 'x', 's', 'h', 'a', '1', 0, + /* 10937 */ 'f', 'l', 'd', '1', 0, + /* 10942 */ 'u', 'd', '1', 0, + /* 10946 */ 'f', 'p', 'r', 'e', 'm', '1', 0, + /* 10953 */ 'f', '2', 'x', 'm', '1', 0, + /* 10959 */ 'f', 'y', 'l', '2', 'x', 'p', '1', 0, + /* 10967 */ 'i', 'n', 't', '1', 0, + /* 10972 */ 'e', 'n', 'd', 'b', 'r', '3', '2', 0, + /* 10980 */ 'u', 'd', '2', 0, + /* 10984 */ 'f', 'l', 'd', 'l', 'g', '2', 0, + /* 10991 */ 'f', 'l', 'd', 'l', 'n', '2', 0, + /* 10998 */ 'i', 'n', 't', '3', 0, + /* 11003 */ 'e', 'n', 'd', 'b', 'r', '6', '4', 0, + /* 11011 */ 'r', 'e', 'x', '6', '4', 0, + /* 11017 */ 'd', 'a', 't', 'a', '1', '6', 0, + /* 11024 */ 'x', 's', 'h', 'a', '2', '5', '6', 0, + /* 11032 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 11045 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 11052 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 11062 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, + /* 11072 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 11087 */ 'a', 'a', 'a', 0, + /* 11091 */ 'd', 'a', 'a', 0, + /* 11095 */ 'x', 'c', 'r', 'y', 'p', 't', 'e', 'c', 'b', 0, + /* 11105 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'f', 'b', 0, + /* 11115 */ 'x', 'c', 'r', 'y', 'p', 't', 'o', 'f', 'b', 0, + /* 11125 */ 'x', 'l', 'a', 't', 'b', 0, + /* 11131 */ 'c', 'l', 'a', 'c', 0, + /* 11136 */ 's', 't', 'a', 'c', 0, + /* 11141 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'b', 'c', 0, + /* 11151 */ 'g', 'e', 't', 's', 'e', 'c', 0, + /* 11158 */ 's', 'a', 'l', 'c', 0, + /* 11163 */ 'c', 'l', 'c', 0, + /* 11167 */ 'c', 'm', 'c', 0, + /* 11171 */ 'r', 'd', 'p', 'm', 'c', 0, + /* 11177 */ 'v', 'm', 'f', 'u', 'n', 'c', 0, + /* 11184 */ 'r', 'd', 't', 's', 'c', 0, + /* 11190 */ 's', 't', 'c', 0, + /* 11194 */ 'p', 'u', 's', 'h', 'f', 'd', 0, + /* 11201 */ 'p', 'o', 'p', 'f', 'd', 0, + /* 11207 */ 'c', 'p', 'u', 'i', 'd', 0, + /* 11213 */ 'c', 'l', 'd', 0, + /* 11217 */ 'x', 'e', 'n', 'd', 0, + /* 11222 */ 'i', 'r', 'e', 't', 'd', 0, + /* 11228 */ 's', 't', 'd', 0, + /* 11232 */ 'w', 'b', 'i', 'n', 'v', 'd', 0, + /* 11239 */ 'w', 'b', 'n', 'o', 'i', 'n', 'v', 'd', 0, + /* 11248 */ 'c', 'w', 'd', 0, + /* 11252 */ 'f', 'l', 'd', 'l', '2', 'e', 0, + /* 11259 */ 'l', 'f', 'e', 'n', 'c', 'e', 0, + /* 11266 */ 'm', 'f', 'e', 'n', 'c', 'e', 0, + /* 11273 */ 's', 'f', 'e', 'n', 'c', 'e', 0, + /* 11280 */ 'c', 'w', 'd', 'e', 0, + /* 11285 */ 'f', 's', 'c', 'a', 'l', 'e', 0, + /* 11292 */ 'v', 'm', 'r', 'e', 's', 'u', 'm', 'e', 0, + /* 11301 */ 'r', 'e', 'p', 'n', 'e', 0, + /* 11307 */ 'c', 'd', 'q', 'e', 0, + /* 11312 */ 'x', 'a', 'c', 'q', 'u', 'i', 'r', 'e', 0, + /* 11321 */ 'x', 's', 't', 'o', 'r', 'e', 0, + /* 11328 */ 'x', 'r', 'e', 'l', 'e', 'a', 's', 'e', 0, + /* 11337 */ 'p', 'a', 'u', 's', 'e', 0, + /* 11343 */ 'l', 'e', 'a', 'v', 'e', 0, + /* 11349 */ 'v', 'm', 'x', 'o', 'f', 'f', 0, + /* 11356 */ 'l', 'a', 'h', 'f', 0, + /* 11361 */ 's', 'a', 'h', 'f', 0, + /* 11366 */ 'p', 'u', 's', 'h', 'f', 0, + /* 11372 */ 'p', 'o', 'p', 'f', 0, + /* 11377 */ 'r', 'e', 't', 'f', 0, + /* 11382 */ 'p', 'c', 'o', 'n', 'f', 'i', 'g', 0, + /* 11390 */ 'v', 'm', 'l', 'a', 'u', 'n', 'c', 'h', 0, + /* 11399 */ 'c', 'l', 'g', 'i', 0, + /* 11404 */ 's', 't', 'g', 'i', 0, + /* 11409 */ 'c', 'l', 'i', 0, + /* 11413 */ 'f', 'l', 'd', 'p', 'i', 0, + /* 11419 */ 's', 't', 'i', 0, + /* 11423 */ 'l', 'o', 'c', 'k', 0, + /* 11428 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'a', 'l', 0, + /* 11439 */ 'p', 'u', 's', 'h', 'a', 'l', 0, + /* 11446 */ 'p', 'o', 'p', 'a', 'l', 0, + /* 11452 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, + /* 11466 */ 'v', 'm', 'm', 'c', 'a', 'l', 'l', 0, + /* 11474 */ 'v', 'm', 'c', 'a', 'l', 'l', 0, + /* 11481 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 0, + /* 11489 */ 'v', 'z', 'e', 'r', 'o', 'a', 'l', 'l', 0, + /* 11498 */ 'm', 'o', 'n', 't', 'm', 'u', 'l', 0, + /* 11506 */ 'f', 'x', 'a', 'm', 0, + /* 11511 */ 'f', 'p', 'r', 'e', 'm', 0, + /* 11517 */ 'v', 'p', 'c', 'o', 'm', 0, + /* 11523 */ 'f', 's', 'e', 't', 'p', 'm', 0, + /* 11530 */ 'r', 's', 'm', 0, + /* 11534 */ 'f', 'p', 'a', 't', 'a', 'n', 0, + /* 11541 */ 'f', 'p', 't', 'a', 'n', 0, + /* 11547 */ 'f', 's', 'i', 'n', 0, + /* 11552 */ 'c', 'q', 'o', 0, + /* 11556 */ 'c', 'l', 'z', 'e', 'r', 'o', 0, + /* 11563 */ 'i', 'n', 't', 'o', 0, + /* 11568 */ 'r', 'd', 't', 's', 'c', 'p', 0, + /* 11575 */ 'r', 'e', 'p', 0, + /* 11579 */ 'v', 'p', 'c', 'm', 'p', 0, + /* 11585 */ 'v', 'c', 'm', 'p', 0, + /* 11590 */ 'f', 'e', 'n', 'i', '8', '0', '8', '7', '_', 'n', 'o', 'p', 0, + /* 11603 */ 'f', 'd', 'i', 's', 'i', '8', '0', '8', '7', '_', 'n', 'o', 'p', 0, + /* 11617 */ 'f', 'n', 'o', 'p', 0, + /* 11622 */ 'f', 'c', 'o', 'm', 'p', 'p', 0, + /* 11629 */ 'f', 'u', 'c', 'o', 'm', 'p', 'p', 0, + /* 11637 */ 's', 'a', 'v', 'e', 'p', 'r', 'e', 'v', 's', 's', 'p', 0, + /* 11649 */ 'f', 'd', 'e', 'c', 's', 't', 'p', 0, + /* 11657 */ 'f', 'i', 'n', 'c', 's', 't', 'p', 0, + /* 11665 */ 'c', 'd', 'q', 0, + /* 11669 */ 'p', 'u', 's', 'h', 'f', 'q', 0, + /* 11676 */ 'p', 'o', 'p', 'f', 'q', 0, + /* 11682 */ 'r', 'e', 't', 'f', 'q', 0, + /* 11688 */ 'i', 'r', 'e', 't', 'q', 0, + /* 11694 */ 's', 'y', 's', 'r', 'e', 't', 'q', 0, + /* 11702 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'q', 0, + /* 11711 */ 'v', 'z', 'e', 'r', 'o', 'u', 'p', 'p', 'e', 'r', 0, + /* 11722 */ 's', 'y', 's', 'e', 'n', 't', 'e', 'r', 0, + /* 11731 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 0, + /* 11739 */ 'r', 'd', 'm', 's', 'r', 0, + /* 11745 */ 'w', 'r', 'm', 's', 'r', 0, + /* 11751 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 't', 'r', 0, + /* 11761 */ 'a', 'a', 's', 0, + /* 11765 */ 'd', 'a', 's', 0, + /* 11769 */ 'f', 'a', 'b', 's', 0, + /* 11774 */ 'p', 'u', 's', 'h', 9, 'c', 's', 0, + /* 11782 */ 'p', 'u', 's', 'h', 9, 'd', 's', 0, + /* 11790 */ 'p', 'o', 'p', 9, 'd', 's', 0, + /* 11797 */ 'p', 'u', 's', 'h', 9, 'e', 's', 0, + /* 11805 */ 'p', 'o', 'p', 9, 'e', 's', 0, + /* 11812 */ 'p', 'u', 's', 'h', 9, 'f', 's', 0, + /* 11820 */ 'p', 'o', 'p', 9, 'f', 's', 0, + /* 11827 */ 'p', 'u', 's', 'h', 9, 'g', 's', 0, + /* 11835 */ 'p', 'o', 'p', 9, 'g', 's', 0, + /* 11842 */ 's', 'w', 'a', 'p', 'g', 's', 0, + /* 11849 */ 'f', 'c', 'h', 's', 0, + /* 11854 */ 'e', 'n', 'c', 'l', 's', 0, + /* 11860 */ 'f', 'e', 'm', 'm', 's', 0, + /* 11866 */ 'f', 'c', 'o', 's', 0, + /* 11871 */ 'f', 's', 'i', 'n', 'c', 'o', 's', 0, + /* 11879 */ 'p', 'u', 's', 'h', 9, 's', 's', 0, + /* 11887 */ 'p', 'o', 'p', 9, 's', 's', 0, + /* 11894 */ 'c', 'l', 't', 's', 0, + /* 11899 */ 'f', 'l', 'd', 'l', '2', 't', 0, + /* 11906 */ 'f', 'x', 't', 'r', 'a', 'c', 't', 0, + /* 11914 */ 'i', 'r', 'e', 't', 0, + /* 11919 */ 's', 'y', 's', 'r', 'e', 't', 0, + /* 11926 */ 'm', 'w', 'a', 'i', 't', 0, + /* 11932 */ 'f', 'n', 'i', 'n', 'i', 't', 0, + /* 11939 */ 's', 'y', 's', 'e', 'x', 'i', 't', 0, + /* 11947 */ 'h', 'l', 't', 0, + /* 11951 */ 'f', 'r', 'n', 'd', 'i', 'n', 't', 0, + /* 11959 */ 'f', 's', 'q', 'r', 't', 0, + /* 11965 */ 'x', 't', 'e', 's', 't', 0, + /* 11971 */ 'f', 't', 's', 't', 0, + /* 11976 */ 'e', 'n', 'c', 'l', 'u', 0, + /* 11982 */ 'r', 'd', 'p', 'k', 'r', 'u', 0, + /* 11989 */ 'w', 'r', 'p', 'k', 'r', 'u', 0, + /* 11996 */ 'x', 'g', 'e', 't', 'b', 'v', 0, + /* 12003 */ 'x', 's', 'e', 't', 'b', 'v', 0, + /* 12010 */ 'e', 'n', 'c', 'l', 'v', 0, + /* 12016 */ 'p', 'u', 's', 'h', 'a', 'w', 0, + /* 12023 */ 'p', 'o', 'p', 'a', 'w', 0, + /* 12029 */ 'c', 'b', 'w', 0, + /* 12033 */ 'f', 'y', 'l', '2', 'x', 0, + /* 12039 */ 'f', 'n', 's', 't', 's', 'w', 9, 'a', 'x', 0, + /* 12049 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'a', 'x', 0, + /* 12060 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, 'e', 'a', 'x', 0, + /* 12071 */ 'v', 'm', 's', 'a', 'v', 'e', 9, 'e', 'a', 'x', 0, + /* 12082 */ 'v', 'm', 'r', 'u', 'n', 9, 'e', 'a', 'x', 0, + /* 12092 */ 's', 'k', 'i', 'n', 'i', 't', 9, 'e', 'a', 'x', 0, + /* 12103 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'e', 'a', 'x', 0, + /* 12115 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, 'r', 'a', 'x', 0, + /* 12126 */ 'v', 'm', 's', 'a', 'v', 'e', 9, 'r', 'a', 'x', 0, + /* 12137 */ 'v', 'm', 'r', 'u', 'n', 9, 'r', 'a', 'x', 0, + /* 12147 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, 'e', 'a', 'x', ',', 32, 'e', 'c', 'x', 0, + /* 12164 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, 'r', 'a', 'x', ',', 32, 'e', 'c', 'x', 0, + /* 12181 */ 'i', 'n', 9, 'a', 'l', ',', 32, 'd', 'x', 0, + /* 12191 */ 'i', 'n', 9, 'a', 'x', ',', 32, 'd', 'x', 0, + /* 12201 */ 'i', 'n', 9, 'e', 'a', 'x', ',', 32, 'd', 'x', 0, + /* 12212 */ 'f', 'n', 'c', 'l', 'e', 'x', 0, + /* 12219 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 'x', 0, + /* 12228 */ 'm', 'w', 'a', 'i', 't', 'x', 0, + /* 12235 */ 's', 'e', 't', 's', 's', 'b', 's', 'y', 0, + /* 12244 */ 'f', 'l', 'd', 'z', 0, + /* 12249 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'd', 'p', 'd', 9, '{', 0, + /* 12265 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'd', 'p', 'd', 9, '{', 0, + /* 12282 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'd', 'p', 'd', 9, '{', 0, + /* 12298 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'd', 'p', 'd', 9, '{', 0, + /* 12315 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'q', 'p', 'd', 9, '{', 0, + /* 12331 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'q', 'p', 'd', 9, '{', 0, + /* 12348 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'q', 'p', 'd', 9, '{', 0, + /* 12364 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'q', 'p', 'd', 9, '{', 0, + /* 12381 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'd', 'p', 's', 9, '{', 0, + /* 12397 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'd', 'p', 's', 9, '{', 0, + /* 12414 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'd', 'p', 's', 9, '{', 0, + /* 12430 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'd', 'p', 's', 9, '{', 0, + /* 12447 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'q', 'p', 's', 9, '{', 0, + /* 12463 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'q', 'p', 's', 9, '{', 0, + /* 12480 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'q', 'p', 's', 9, '{', 0, + /* 12496 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'q', 'p', 's', 9, '{', 0, + }; +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 11053U, // DBG_VALUE + 11063U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 11046U, // BUNDLE + 11073U, // LIFETIME_START + 11033U, // LIFETIME_END + 0U, // STACKMAP + 11453U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 10860U, // PATCHABLE_FUNCTION_ENTER + 10780U, // PATCHABLE_RET + 10906U, // PATCHABLE_FUNCTION_EXIT + 10883U, // PATCHABLE_TAIL_CALL + 10835U, // PATCHABLE_EVENT_CALL + 10811U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // AVX1_SETALLONES + 0U, // AVX2_SETALLONES + 0U, // AVX512_128_SET0 + 0U, // AVX512_256_SET0 + 0U, // AVX512_512_SET0 + 0U, // AVX512_512_SETALLONES + 0U, // AVX512_512_SEXT_MASK_32 + 0U, // AVX512_512_SEXT_MASK_64 + 0U, // AVX512_FsFLD0SD + 0U, // AVX512_FsFLD0SS + 0U, // AVX_SET0 + 0U, // KSET0D + 0U, // KSET0Q + 0U, // KSET0W + 0U, // KSET1D + 0U, // KSET1Q + 0U, // KSET1W + 0U, // MMX_SET0 + 0U, // V_SET0 + 0U, // V_SETALLONES + 11088U, // AAA + 18192U, // AAD8i8 + 21564U, // AAM8i8 + 11762U, // AAS + 11770U, // ABS_F + 0U, // ABS_Fp32 + 0U, // ABS_Fp64 + 0U, // ABS_Fp80 + 26727U, // ADC16i16 + 1083033U, // ADC16mi + 1083033U, // ADC16mi8 + 1083033U, // ADC16mr + 34653849U, // ADC16ri + 34653849U, // ADC16ri8 + 68208281U, // ADC16rm + 34653849U, // ADC16rr + 34621081U, // ADC16rr_REV + 26853U, // ADC32i32 + 1115801U, // ADC32mi + 1115801U, // ADC32mi8 + 1115801U, // ADC32mr + 34653849U, // ADC32ri + 34653849U, // ADC32ri8 + 101762713U, // ADC32rm + 34653849U, // ADC32rr + 34621081U, // ADC32rr_REV + 26990U, // ADC64i32 + 1132185U, // ADC64mi32 + 1132185U, // ADC64mi8 + 1132185U, // ADC64mr + 34653849U, // ADC64ri32 + 34653849U, // ADC64ri8 + 135317145U, // ADC64rm + 34653849U, // ADC64rr + 34621081U, // ADC64rr_REV + 26625U, // ADC8i8 + 1148569U, // ADC8mi + 1148569U, // ADC8mi8 + 1148569U, // ADC8mr + 34653849U, // ADC8ri + 34653849U, // ADC8ri8 + 168871577U, // ADC8rm + 34653849U, // ADC8rr + 34621081U, // ADC8rr_REV + 101738229U, // ADCX32rm + 34629365U, // ADCX32rr + 135292661U, // ADCX64rm + 34629365U, // ADCX64rr + 26736U, // ADD16i16 + 1083243U, // ADD16mi + 1083243U, // ADD16mi8 + 1083243U, // ADD16mr + 34654059U, // ADD16ri + 34654059U, // ADD16ri8 + 68208491U, // ADD16rm + 34654059U, // ADD16rr + 34621291U, // ADD16rr_REV + 26863U, // ADD32i32 + 1116011U, // ADD32mi + 1116011U, // ADD32mi8 + 1116011U, // ADD32mr + 34654059U, // ADD32ri + 34654059U, // ADD32ri8 + 101762923U, // ADD32rm + 34654059U, // ADD32rr + 34621291U, // ADD32rr_REV + 27000U, // ADD64i32 + 1132395U, // ADD64mi32 + 1132395U, // ADD64mi8 + 1132395U, // ADD64mr + 34654059U, // ADD64ri32 + 34654059U, // ADD64ri8 + 135317355U, // ADD64rm + 34654059U, // ADD64rr + 34621291U, // ADD64rr_REV + 26634U, // ADD8i8 + 1148779U, // ADD8mi + 1148779U, // ADD8mi8 + 1148779U, // ADD8mr + 34654059U, // ADD8ri + 34654059U, // ADD8ri8 + 168871787U, // ADD8rm + 34654059U, // ADD8rr + 34621291U, // ADD8rr_REV + 202394334U, // ADDPDrm + 34622174U, // ADDPDrr + 202399110U, // ADDPSrm + 34626950U, // ADDPSrr + 235949685U, // ADDSDrm + 235949685U, // ADDSDrm_Int + 34623093U, // ADDSDrr + 34623093U, // ADDSDrr_Int + 269508811U, // ADDSSrm + 269508811U, // ADDSSrm_Int + 34627787U, // ADDSSrr + 34627787U, // ADDSSrr_Int + 202394269U, // ADDSUBPDrm + 34622109U, // ADDSUBPDrr + 202399045U, // ADDSUBPSrm + 34626885U, // ADDSUBPSrr + 116586U, // ADD_F32m + 132970U, // ADD_F64m + 34672U, // ADD_FI16m + 67440U, // ADD_FI32m + 21716U, // ADD_FPrST0 + 18282U, // ADD_FST0r + 0U, // ADD_Fp32 + 0U, // ADD_Fp32m + 0U, // ADD_Fp64 + 0U, // ADD_Fp64m + 0U, // ADD_Fp64m32 + 0U, // ADD_Fp80 + 0U, // ADD_Fp80m32 + 0U, // ADD_Fp80m64 + 0U, // ADD_FpI16m32 + 0U, // ADD_FpI16m64 + 0U, // ADD_FpI16m80 + 0U, // ADD_FpI32m32 + 0U, // ADD_FpI32m64 + 0U, // ADD_FpI32m80 + 2115434U, // ADD_FrST0 + 101738255U, // ADOX32rm + 34629391U, // ADOX32rr + 135292687U, // ADOX64rm + 34629391U, // ADOX64rr + 303063680U, // AESDECLASTrm + 34628224U, // AESDECLASTrr + 303056543U, // AESDECrm + 34621087U, // AESDECrr + 303063693U, // AESENCLASTrm + 34628237U, // AESENCLASTrr + 303056591U, // AESENCrm + 34621135U, // AESENCrr + 336611014U, // AESIMCrm + 370165446U, // AESIMCrr + 2484101805U, // AESKEYGENASSIST128rm + 2517656237U, // AESKEYGENASSIST128rr + 26745U, // AND16i16 + 1083574U, // AND16mi + 1083574U, // AND16mi8 + 1083574U, // AND16mr + 34654390U, // AND16ri + 34654390U, // AND16ri8 + 68208822U, // AND16rm + 34654390U, // AND16rr + 34621622U, // AND16rr_REV + 26873U, // AND32i32 + 1116342U, // AND32mi + 1116342U, // AND32mi8 + 1116342U, // AND32mr + 34654390U, // AND32ri + 34654390U, // AND32ri8 + 101763254U, // AND32rm + 34654390U, // AND32rr + 34621622U, // AND32rr_REV + 27010U, // AND64i32 + 1132726U, // AND64mi32 + 1132726U, // AND64mi8 + 1132726U, // AND64mr + 34654390U, // AND64ri32 + 34654390U, // AND64ri8 + 135317686U, // AND64rm + 34654390U, // AND64rr + 34621622U, // AND64rr_REV + 26643U, // AND8i8 + 1149110U, // AND8mi + 1149110U, // AND8mi8 + 1149110U, // AND8mr + 34654390U, // AND8ri + 34654390U, // AND8ri8 + 168872118U, // AND8rm + 34654390U, // AND8rr + 34621622U, // AND8rr_REV + 2517652606U, // ANDN32rm + 2517652606U, // ANDN32rr + 2517652606U, // ANDN64rm + 2517652606U, // ANDN64rr + 202394609U, // ANDNPDrm + 34622449U, // ANDNPDrr + 202399420U, // ANDNPSrm + 34627260U, // ANDNPSrr + 202394383U, // ANDPDrm + 34622223U, // ANDPDrr + 202399182U, // ANDPSrm + 34627022U, // ANDPSrr + 1086423U, // ARPL16mr + 370168791U, // ARPL16rr + 2551208720U, // BEXTR32rm + 2517654288U, // BEXTR32rr + 2584763152U, // BEXTR64rm + 2517654288U, // BEXTR64rr + 2551208720U, // BEXTRI32mi + 2517654288U, // BEXTRI32ri + 2584763152U, // BEXTRI64mi + 2517654288U, // BEXTRI64ri + 403723200U, // BLCFILL32rm + 370168768U, // BLCFILL32rr + 437277632U, // BLCFILL64rm + 370168768U, // BLCFILL64rr + 403722900U, // BLCI32rm + 370168468U, // BLCI32rr + 437277332U, // BLCI64rm + 370168468U, // BLCI64rr + 403719855U, // BLCIC32rm + 370165423U, // BLCIC32rr + 437274287U, // BLCIC64rm + 370165423U, // BLCIC64rr + 403723136U, // BLCMSK32rm + 370168704U, // BLCMSK32rr + 437277568U, // BLCMSK64rm + 370168704U, // BLCMSK64rr + 403725102U, // BLCS32rm + 370170670U, // BLCS32rr + 437279534U, // BLCS64rm + 370170670U, // BLCS64rr + 2349878047U, // BLENDPDrmi + 2182105887U, // BLENDPDrri + 2349882846U, // BLENDPSrmi + 2182110686U, // BLENDPSrri + 202394783U, // BLENDVPDrm0 + 34622623U, // BLENDVPDrr0 + 202399618U, // BLENDVPSrm0 + 34627458U, // BLENDVPSrr0 + 403723209U, // BLSFILL32rm + 370168777U, // BLSFILL32rr + 437277641U, // BLSFILL64rm + 370168777U, // BLSFILL64rr + 403723065U, // BLSI32rm + 370168633U, // BLSI32rr + 437277497U, // BLSI64rm + 370168633U, // BLSI64rr + 403719862U, // BLSIC32rm + 370165430U, // BLSIC32rr + 437274294U, // BLSIC64rm + 370165430U, // BLSIC64rr + 403723144U, // BLSMSK32rm + 370168712U, // BLSMSK32rr + 437277576U, // BLSMSK64rm + 370168712U, // BLSMSK64rr + 403725051U, // BLSR32rm + 370170619U, // BLSR32rr + 437279483U, // BLSR64rm + 370170619U, // BLSR64rr + 470832036U, // BNDCL32rm + 370168740U, // BNDCL32rr + 470832036U, // BNDCL64rm + 370168740U, // BNDCL64rr + 470832245U, // BNDCN32rm + 370168949U, // BNDCN32rr + 470832245U, // BNDCN64rm + 370168949U, // BNDCN64rr + 470835922U, // BNDCU32rm + 370172626U, // BNDCU32rr + 470835922U, // BNDCU64rm + 370172626U, // BNDCU64rr + 470836987U, // BNDLDXrm + 470831993U, // BNDMK32rm + 470831993U, // BNDMK64rm + 1139485U, // BNDMOV32mr + 437281565U, // BNDMOV32rm + 1205021U, // BNDMOV64mr + 336618269U, // BNDMOV64rm + 370172701U, // BNDMOVrr + 370172701U, // BNDMOVrr_REV + 173870U, // BNDSTXmr + 403720422U, // BOUNDS16rm + 437274854U, // BOUNDS32rm + 504386081U, // BSF16rm + 370168353U, // BSF16rr + 403722785U, // BSF32rm + 370168353U, // BSF32rr + 437277217U, // BSF64rm + 370168353U, // BSF64rr + 504388322U, // BSR16rm + 370170594U, // BSR16rr + 403725026U, // BSR32rm + 370170594U, // BSR32rr + 437279458U, // BSR64rm + 370170594U, // BSR64rr + 21695U, // BSWAP16r_BAD + 21695U, // BSWAP32r + 21695U, // BSWAP64r + 1090034U, // BT16mi8 + 1090034U, // BT16mr + 370172402U, // BT16ri8 + 370172402U, // BT16rr + 1122802U, // BT32mi8 + 1122802U, // BT32mr + 370172402U, // BT32ri8 + 370172402U, // BT32rr + 1139186U, // BT64mi8 + 1139186U, // BT64mr + 370172402U, // BT64ri8 + 370172402U, // BT64rr + 1083100U, // BTC16mi8 + 1083100U, // BTC16mr + 34653916U, // BTC16ri8 + 34653916U, // BTC16rr + 1115868U, // BTC32mi8 + 1115868U, // BTC32mr + 34653916U, // BTC32ri8 + 34653916U, // BTC32rr + 1132252U, // BTC64mi8 + 1132252U, // BTC64mr + 34653916U, // BTC64ri8 + 34653916U, // BTC64rr + 1088257U, // BTR16mi8 + 1088257U, // BTR16mr + 34659073U, // BTR16ri8 + 34659073U, // BTR16rr + 1121025U, // BTR32mi8 + 1121025U, // BTR32mr + 34659073U, // BTR32ri8 + 34659073U, // BTR32rr + 1137409U, // BTR64mi8 + 1137409U, // BTR64mr + 34659073U, // BTR64ri8 + 34659073U, // BTR64rr + 1090016U, // BTS16mi8 + 1090016U, // BTS16mr + 34660832U, // BTS16ri8 + 34660832U, // BTS16rr + 1122784U, // BTS32mi8 + 1122784U, // BTS32mr + 34660832U, // BTS32ri8 + 34660832U, // BTS32rr + 1139168U, // BTS64mi8 + 1139168U, // BTS64mr + 34660832U, // BTS64ri8 + 34660832U, // BTS64rr + 2551206554U, // BZHI32rm + 2517652122U, // BZHI32rr + 2584760986U, // BZHI64rm + 2517652122U, // BZHI64rr + 37818U, // CALL16m + 37818U, // CALL16m_NT + 21434U, // CALL16r + 21434U, // CALL16r_NT + 70586U, // CALL32m + 70586U, // CALL32m_NT + 21434U, // CALL32r + 21434U, // CALL32r_NT + 86970U, // CALL64m + 86970U, // CALL64m_NT + 185274U, // CALL64pcrel32 + 21434U, // CALL64r + 21434U, // CALL64r_NT + 185274U, // CALLpcrel16 + 185274U, // CALLpcrel32 + 12030U, // CBW + 11666U, // CDQ + 11308U, // CDQE + 11850U, // CHS_F + 0U, // CHS_Fp32 + 0U, // CHS_Fp64 + 0U, // CHS_Fp80 + 11132U, // CLAC + 11164U, // CLC + 11214U, // CLD + 102901U, // CLDEMOTE + 103045U, // CLFLUSH + 107106U, // CLFLUSHOPT + 11400U, // CLGI + 11410U, // CLI + 75581U, // CLRSSBSY + 11895U, // CLTS + 99911U, // CLWB + 11557U, // CLZEROr + 11168U, // CMC + 68174716U, // CMOVA16rm + 34620284U, // CMOVA16rr + 101729148U, // CMOVA32rm + 34620284U, // CMOVA32rr + 135283580U, // CMOVA64rm + 34620284U, // CMOVA64rr + 68178217U, // CMOVAE16rm + 34623785U, // CMOVAE16rr + 101732649U, // CMOVAE32rm + 34623785U, // CMOVAE32rr + 135287081U, // CMOVAE64rm + 34623785U, // CMOVAE64rr + 68175417U, // CMOVB16rm + 34620985U, // CMOVB16rr + 101729849U, // CMOVB32rm + 34620985U, // CMOVB32rr + 135284281U, // CMOVB64rm + 34620985U, // CMOVB64rr + 68178237U, // CMOVBE16rm + 34623805U, // CMOVBE16rr + 101732669U, // CMOVBE32rm + 34623805U, // CMOVBE32rr + 135287101U, // CMOVBE64rm + 34623805U, // CMOVBE64rr + 26507U, // CMOVBE_F + 0U, // CMOVBE_Fp32 + 0U, // CMOVBE_Fp64 + 0U, // CMOVBE_Fp80 + 26475U, // CMOVB_F + 0U, // CMOVB_Fp32 + 0U, // CMOVB_Fp64 + 0U, // CMOVB_Fp80 + 68178458U, // CMOVE16rm + 34624026U, // CMOVE16rr + 101732890U, // CMOVE32rm + 34624026U, // CMOVE32rr + 135287322U, // CMOVE64rm + 34624026U, // CMOVE64rr + 26539U, // CMOVE_F + 0U, // CMOVE_Fp32 + 0U, // CMOVE_Fp64 + 0U, // CMOVE_Fp80 + 68178508U, // CMOVG16rm + 34624076U, // CMOVG16rr + 101732940U, // CMOVG32rm + 34624076U, // CMOVG32rr + 135287372U, // CMOVG64rm + 34624076U, // CMOVG64rr + 68178282U, // CMOVGE16rm + 34623850U, // CMOVGE16rr + 101732714U, // CMOVGE32rm + 34623850U, // CMOVGE32rr + 135287146U, // CMOVGE64rm + 34623850U, // CMOVGE64rr + 68178957U, // CMOVL16rm + 34624525U, // CMOVL16rr + 101733389U, // CMOVL32rm + 34624525U, // CMOVL32rr + 135287821U, // CMOVL64rm + 34624525U, // CMOVL64rr + 68178306U, // CMOVLE16rm + 34623874U, // CMOVLE16rr + 101732738U, // CMOVLE32rm + 34623874U, // CMOVLE32rr + 135287170U, // CMOVLE64rm + 34623874U, // CMOVLE64rr + 26490U, // CMOVNBE_F + 0U, // CMOVNBE_Fp32 + 0U, // CMOVNBE_Fp64 + 0U, // CMOVNBE_Fp80 + 26459U, // CMOVNB_F + 0U, // CMOVNB_Fp32 + 0U, // CMOVNB_Fp64 + 0U, // CMOVNB_Fp80 + 68178334U, // CMOVNE16rm + 34623902U, // CMOVNE16rr + 101732766U, // CMOVNE32rm + 34623902U, // CMOVNE32rr + 135287198U, // CMOVNE64rm + 34623902U, // CMOVNE64rr + 26523U, // CMOVNE_F + 0U, // CMOVNE_Fp32 + 0U, // CMOVNE_Fp64 + 0U, // CMOVNE_Fp80 + 68179114U, // CMOVNO16rm + 34624682U, // CMOVNO16rr + 101733546U, // CMOVNO32rm + 34624682U, // CMOVNO32rr + 135287978U, // CMOVNO64rm + 34624682U, // CMOVNO64rr + 68179234U, // CMOVNP16rm + 34624802U, // CMOVNP16rr + 101733666U, // CMOVNP32rm + 34624802U, // CMOVNP32rr + 135288098U, // CMOVNP64rm + 34624802U, // CMOVNP64rr + 26554U, // CMOVNP_F + 0U, // CMOVNP_Fp32 + 0U, // CMOVNP_Fp64 + 0U, // CMOVNP_Fp80 + 68180874U, // CMOVNS16rm + 34626442U, // CMOVNS16rr + 101735306U, // CMOVNS32rm + 34626442U, // CMOVNS32rr + 135289738U, // CMOVNS64rm + 34626442U, // CMOVNS64rr + 68179128U, // CMOVO16rm + 34624696U, // CMOVO16rr + 101733560U, // CMOVO32rm + 34624696U, // CMOVO32rr + 135287992U, // CMOVO64rm + 34624696U, // CMOVO64rr + 68179350U, // CMOVP16rm + 34624918U, // CMOVP16rr + 101733782U, // CMOVP32rm + 34624918U, // CMOVP32rr + 135288214U, // CMOVP64rm + 34624918U, // CMOVP64rr + 26570U, // CMOVP_F + 0U, // CMOVP_Fp32 + 0U, // CMOVP_Fp64 + 0U, // CMOVP_Fp80 + 68182507U, // CMOVS16rm + 34628075U, // CMOVS16rr + 101736939U, // CMOVS32rm + 34628075U, // CMOVS32rr + 135291371U, // CMOVS64rm + 34628075U, // CMOVS64rr + 26762U, // CMP16i16 + 1086708U, // CMP16mi + 1086708U, // CMP16mi8 + 1086708U, // CMP16mr + 370169076U, // CMP16ri + 370169076U, // CMP16ri8 + 504386804U, // CMP16rm + 370169076U, // CMP16rr + 370169076U, // CMP16rr_REV + 26916U, // CMP32i32 + 1119476U, // CMP32mi + 1119476U, // CMP32mi8 + 1119476U, // CMP32mr + 370169076U, // CMP32ri + 370169076U, // CMP32ri8 + 403723508U, // CMP32rm + 370169076U, // CMP32rr + 370169076U, // CMP32rr_REV + 27020U, // CMP64i32 + 1135860U, // CMP64mi32 + 1135860U, // CMP64mi8 + 1135860U, // CMP64mr + 370169076U, // CMP64ri32 + 370169076U, // CMP64ri8 + 437277940U, // CMP64rm + 370169076U, // CMP64rr + 370169076U, // CMP64rr_REV + 26660U, // CMP8i8 + 1152244U, // CMP8mi + 1152244U, // CMP8mi8 + 1152244U, // CMP8mr + 370169076U, // CMP8ri + 370169076U, // CMP8ri8 + 537941236U, // CMP8rm + 370169076U, // CMP8rr + 370169076U, // CMP8rr_REV + 2721262910U, // CMPPDrmi + 2349878281U, // CMPPDrmi_alt + 573795646U, // CMPPDrri + 2182106121U, // CMPPDrri_alt + 2722311486U, // CMPPSrmi + 2349883100U, // CMPPSrmi_alt + 574844222U, // CMPPSrri + 2182110940U, // CMPPSrri_alt + 230770U, // CMPSB + 2723360062U, // CMPSDrm + 2723360062U, // CMPSDrm_Int + 2383433479U, // CMPSDrm_alt + 575892798U, // CMPSDrr + 575892798U, // CMPSDrr_Int + 2182106887U, // CMPSDrr_alt + 249607U, // CMPSL + 268566U, // CMPSQ + 576924990U, // CMPSSrm + 576924990U, // CMPSSrm_Int + 2416992619U, // CMPSSrm_alt + 576941374U, // CMPSSrr + 576941374U, // CMPSSrr_Int + 2182111595U, // CMPSSrr_alt + 288218U, // CMPSW + 148396U, // CMPXCHG16B + 1086001U, // CMPXCHG16rm + 370168369U, // CMPXCHG16rr + 1118769U, // CMPXCHG32rm + 370168369U, // CMPXCHG32rr + 1135153U, // CMPXCHG64rm + 370168369U, // CMPXCHG64rr + 82872U, // CMPXCHG8B + 1151537U, // CMPXCHG8rm + 370168369U, // CMPXCHG8rr + 605048520U, // COMISDrm + 605048520U, // COMISDrm_Int + 370167496U, // COMISDrr + 370167496U, // COMISDrr_Int + 638607668U, // COMISSrm + 638607668U, // COMISSrm_Int + 370172212U, // COMISSrr + 370172212U, // COMISSrr_Int + 21759U, // COMP_FST0r + 21209U, // COM_FIPr + 21152U, // COM_FIr + 21569U, // COM_FST0r + 11867U, // COS_F + 0U, // COS_Fp32 + 0U, // COS_Fp64 + 0U, // COS_Fp80 + 11208U, // CPUID + 11553U, // CQO + 68206683U, // CRC32r32m16 + 101761115U, // CRC32r32m32 + 168869979U, // CRC32r32m8 + 34652251U, // CRC32r32r16 + 34652251U, // CRC32r32r32 + 34652251U, // CRC32r32r8 + 135315547U, // CRC32r64m64 + 168869979U, // CRC32r64m8 + 34652251U, // CRC32r64r64 + 34652251U, // CRC32r64r8 + 437275076U, // CVTDQ2PDrm + 370166212U, // CVTDQ2PDrr + 336616575U, // CVTDQ2PSrm + 370171007U, // CVTDQ2PSrr + 672159269U, // CVTPD2DQrm + 370169381U, // CVTPD2DQrr + 672160831U, // CVTPD2PSrm + 370170943U, // CVTPD2PSrr + 672159301U, // CVTPS2DQrm + 370169413U, // CVTPS2DQrr + 605047282U, // CVTPS2PDrm + 370166258U, // CVTPS2PDrr + 605049624U, // CVTSD2SI64rm_Int + 370168600U, // CVTSD2SI64rr_Int + 605049624U, // CVTSD2SIrm_Int + 370168600U, // CVTSD2SIrr_Int + 605052967U, // CVTSD2SSrm + 235954215U, // CVTSD2SSrm_Int + 370171943U, // CVTSD2SSrr + 34627623U, // CVTSD2SSrr_Int + 403721674U, // CVTSI2SDrm + 101731786U, // CVTSI2SDrm_Int + 370167242U, // CVTSI2SDrr + 34622922U, // CVTSI2SDrr_Int + 403726386U, // CVTSI2SSrm + 101736498U, // CVTSI2SSrm_Int + 370171954U, // CVTSI2SSrr + 34627634U, // CVTSI2SSrr_Int + 437276106U, // CVTSI642SDrm + 135286218U, // CVTSI642SDrm_Int + 370167242U, // CVTSI642SDrr + 34622922U, // CVTSI642SDrr_Int + 437280818U, // CVTSI642SSrm + 135290930U, // CVTSI642SSrm_Int + 370171954U, // CVTSI642SSrr + 34627634U, // CVTSI642SSrr_Int + 638602721U, // CVTSS2SDrm + 269503969U, // CVTSS2SDrm_Int + 370167265U, // CVTSS2SDrr + 34622945U, // CVTSS2SDrr_Int + 638604079U, // CVTSS2SI64rm_Int + 370168623U, // CVTSS2SI64rr_Int + 638604079U, // CVTSS2SIrm_Int + 370168623U, // CVTSS2SIrr_Int + 672159257U, // CVTTPD2DQrm + 370169369U, // CVTTPD2DQrr + 672159289U, // CVTTPS2DQrm + 370169401U, // CVTTPS2DQrr + 605049612U, // CVTTSD2SI64rm + 605049612U, // CVTTSD2SI64rm_Int + 370168588U, // CVTTSD2SI64rr + 370168588U, // CVTTSD2SI64rr_Int + 605049612U, // CVTTSD2SIrm + 605049612U, // CVTTSD2SIrm_Int + 370168588U, // CVTTSD2SIrr + 370168588U, // CVTTSD2SIrr_Int + 638604067U, // CVTTSS2SI64rm + 638604067U, // CVTTSS2SI64rm_Int + 370168611U, // CVTTSS2SI64rr + 370168611U, // CVTTSS2SI64rr_Int + 638604067U, // CVTTSS2SIrm + 638604067U, // CVTTSS2SIrm_Int + 370168611U, // CVTTSS2SIrr + 370168611U, // CVTTSS2SIrr_Int + 11249U, // CWD + 11281U, // CWDE + 11092U, // DAA + 11766U, // DAS + 11018U, // DATA16_PREFIX + 34466U, // DEC16m + 18082U, // DEC16r + 18082U, // DEC16r_alt + 67234U, // DEC32m + 18082U, // DEC32r + 18082U, // DEC32r_alt + 83618U, // DEC64m + 18082U, // DEC64r + 100002U, // DEC8m + 18082U, // DEC8r + 41720U, // DIV16m + 25336U, // DIV16r + 74488U, // DIV32m + 25336U, // DIV32r + 90872U, // DIV64m + 25336U, // DIV64r + 107256U, // DIV8m + 25336U, // DIV8r + 202394794U, // DIVPDrm + 34622634U, // DIVPDrr + 202399629U, // DIVPSrm + 34627469U, // DIVPSrr + 121623U, // DIVR_F32m + 138007U, // DIVR_F64m + 39710U, // DIVR_FI16m + 72478U, // DIVR_FI32m + 21826U, // DIVR_FPrST0 + 23319U, // DIVR_FST0r + 0U, // DIVR_Fp32m + 0U, // DIVR_Fp64m + 0U, // DIVR_Fp64m32 + 0U, // DIVR_Fp80m32 + 0U, // DIVR_Fp80m64 + 0U, // DIVR_FpI16m32 + 0U, // DIVR_FpI16m64 + 0U, // DIVR_FpI16m80 + 0U, // DIVR_FpI32m32 + 0U, // DIVR_FpI32m64 + 0U, // DIVR_FpI32m80 + 2120471U, // DIVR_FrST0 + 235949965U, // DIVSDrm + 235949965U, // DIVSDrm_Int + 34623373U, // DIVSDrr + 34623373U, // DIVSDrr_Int + 269509056U, // DIVSSrm + 269509056U, // DIVSSrm_Int + 34628032U, // DIVSSrr + 34628032U, // DIVSSrr_Int + 123639U, // DIV_F32m + 140023U, // DIV_F64m + 41725U, // DIV_FI16m + 74493U, // DIV_FI32m + 21903U, // DIV_FPrST0 + 25335U, // DIV_FST0r + 0U, // DIV_Fp32 + 0U, // DIV_Fp32m + 0U, // DIV_Fp64 + 0U, // DIV_Fp64m + 0U, // DIV_Fp64m32 + 0U, // DIV_Fp80 + 0U, // DIV_Fp80m32 + 0U, // DIV_Fp80m64 + 0U, // DIV_FpI16m32 + 0U, // DIV_FpI16m64 + 0U, // DIV_FpI16m80 + 0U, // DIV_FpI32m32 + 0U, // DIV_FpI32m64 + 0U, // DIV_FpI32m80 + 2122487U, // DIV_FrST0 + 2349878274U, // DPPDrmi + 2182106114U, // DPPDrri + 2349883093U, // DPPSrmi + 2182110933U, // DPPSrri + 11855U, // ENCLS + 11977U, // ENCLU + 12011U, // ENCLV + 10973U, // ENDBR32 + 11004U, // ENDBR64 + 370170521U, // ENTER + 2148654896U, // EXTRACTPSmr + 2517655344U, // EXTRACTPSrr + 34658551U, // EXTRQ + 2853230839U, // EXTRQI + 10954U, // F2XM1 + 739300281U, // FARCALL16i + 299961U, // FARCALL16m + 739300281U, // FARCALL32i + 299962U, // FARCALL32m + 299961U, // FARCALL64 + 7394553U, // FARJMP16i + 300281U, // FARJMP16m + 7394553U, // FARJMP32i + 300282U, // FARJMP32m + 300281U, // FARJMP64 + 322043U, // FBLDm + 322059U, // FBSTPm + 119873U, // FCOM32m + 136257U, // FCOM64m + 120063U, // FCOMP32m + 136447U, // FCOMP64m + 11623U, // FCOMPP + 11650U, // FDECSTP + 11604U, // FDISI8087_NOP + 11861U, // FEMMS + 11591U, // FENI8087_NOP + 20814U, // FFREE + 21729U, // FFREEP + 37959U, // FICOM16m + 70727U, // FICOM32m + 38150U, // FICOMP16m + 70918U, // FICOMP32m + 11658U, // FINCSTP + 41945U, // FLDCW16m + 123652U, // FLDENVm + 11253U, // FLDL2E + 11900U, // FLDL2T + 10985U, // FLDLG2 + 10992U, // FLDLN2 + 11414U, // FLDPI + 12213U, // FNCLEX + 11933U, // FNINIT + 11618U, // FNOP + 41952U, // FNSTCW16m + 12040U, // FNSTSW16r + 42489U, // FNSTSWm + 11535U, // FPATAN + 2117957U, // FPNCEST0r + 11512U, // FPREM + 10947U, // FPREM1 + 11542U, // FPTAN + 11952U, // FRNDINT + 121540U, // FRSTORm + 119306U, // FSAVEm + 11286U, // FSCALE + 11524U, // FSETPM + 11872U, // FSINCOS + 123660U, // FSTENVm + 11507U, // FXAM + 301772U, // FXRSTOR + 295259U, // FXRSTOR64 + 299538U, // FXSAVE + 295249U, // FXSAVE64 + 11907U, // FXTRACT + 12034U, // FYL2X + 10960U, // FYL2XP1 + 11152U, // GETSEC + 2450539772U, // GF2P8AFFINEINVQBrmi + 2182104316U, // GF2P8AFFINEINVQBrri + 2450539709U, // GF2P8AFFINEQBrmi + 2182104253U, // GF2P8AFFINEQBrri + 303055962U, // GF2P8MULBrm + 34620506U, // GF2P8MULBrr + 202394342U, // HADDPDrm + 34622182U, // HADDPDrr + 202399118U, // HADDPSrm + 34626958U, // HADDPSrr + 11948U, // HLT + 202394291U, // HSUBPDrm + 34622131U, // HSUBPDrr + 202399067U, // HSUBPSrm + 34626907U, // HSUBPSrr + 41726U, // IDIV16m + 25342U, // IDIV16r + 74494U, // IDIV32m + 25342U, // IDIV32r + 90878U, // IDIV64m + 25342U, // IDIV64r + 107262U, // IDIV8m + 25342U, // IDIV8r + 34890U, // ILD_F16m + 67658U, // ILD_F32m + 84042U, // ILD_F64m + 0U, // ILD_Fp16m32 + 0U, // ILD_Fp16m64 + 0U, // ILD_Fp16m80 + 0U, // ILD_Fp32m32 + 0U, // ILD_Fp32m64 + 0U, // ILD_Fp32m80 + 0U, // ILD_Fp64m32 + 0U, // ILD_Fp64m64 + 0U, // ILD_Fp64m80 + 37895U, // IMUL16m + 21511U, // IMUL16r + 68178951U, // IMUL16rm + 2651870215U, // IMUL16rmi + 2651870215U, // IMUL16rmi8 + 34624519U, // IMUL16rr + 2517652487U, // IMUL16rri + 2517652487U, // IMUL16rri8 + 70663U, // IMUL32m + 21511U, // IMUL32r + 101733383U, // IMUL32rm + 2551206919U, // IMUL32rmi + 2551206919U, // IMUL32rmi8 + 34624519U, // IMUL32rr + 2517652487U, // IMUL32rri + 2517652487U, // IMUL32rri8 + 87047U, // IMUL64m + 21511U, // IMUL64r + 135287815U, // IMUL64rm + 2584761351U, // IMUL64rmi32 + 2584761351U, // IMUL64rmi8 + 34624519U, // IMUL64rr + 2517652487U, // IMUL64rri32 + 2517652487U, // IMUL64rri8 + 103431U, // IMUL8m + 21511U, // IMUL8r + 338050U, // IN16ri + 12192U, // IN16rr + 338203U, // IN32ri + 12202U, // IN32rr + 337948U, // IN8ri + 12182U, // IN8rr + 34519U, // INC16m + 18135U, // INC16r + 18135U, // INC16r_alt + 67287U, // INC32m + 18135U, // INC32r + 18135U, // INC32r_alt + 83671U, // INC64m + 18135U, // INC64r + 100055U, // INC8m + 18135U, // INC8r + 19535U, // INCSSPD + 22562U, // INCSSPQ + 8734053U, // INSB + 2416992082U, // INSERTPSrm + 2182111058U, // INSERTPSrr + 34658699U, // INSERTQ + 2182142347U, // INSERTQI + 8752881U, // INSL + 8775117U, // INSW + 336454U, // INT + 10968U, // INT1 + 10999U, // INT3 + 11564U, // INTO + 11235U, // INVD + 336618064U, // INVEPT32 + 336618064U, // INVEPT64 + 102974U, // INVLPG + 12148U, // INVLPGA32 + 12165U, // INVLPGA64 + 336611364U, // INVPCID32 + 336611364U, // INVPCID64 + 336611380U, // INVVPID32 + 336611380U, // INVVPID64 + 11915U, // IRET16 + 11223U, // IRET32 + 11689U, // IRET64 + 38247U, // ISTT_FP16m + 71015U, // ISTT_FP32m + 87399U, // ISTT_FP64m + 0U, // ISTT_Fp16m32 + 0U, // ISTT_Fp16m64 + 0U, // ISTT_Fp16m80 + 0U, // ISTT_Fp32m32 + 0U, // ISTT_Fp32m64 + 0U, // ISTT_Fp32m80 + 0U, // ISTT_Fp64m32 + 0U, // ISTT_Fp64m64 + 0U, // ISTT_Fp64m80 + 41638U, // IST_F16m + 74406U, // IST_F32m + 38240U, // IST_FP16m + 71008U, // IST_FP32m + 87392U, // IST_FP64m + 0U, // IST_Fp16m32 + 0U, // IST_Fp16m64 + 0U, // IST_Fp16m80 + 0U, // IST_Fp32m32 + 0U, // IST_Fp32m64 + 0U, // IST_Fp32m80 + 0U, // IST_Fp64m32 + 0U, // IST_Fp64m64 + 0U, // IST_Fp64m80 + 184605U, // JAE_1 + 184605U, // JAE_2 + 184605U, // JAE_4 + 181073U, // JA_1 + 181073U, // JA_2 + 181073U, // JA_4 + 184625U, // JBE_1 + 184625U, // JBE_2 + 184625U, // JBE_4 + 181304U, // JB_1 + 181304U, // JB_2 + 181304U, // JB_4 + 190286U, // JCXZ + 190279U, // JECXZ + 184690U, // JE_1 + 184690U, // JE_2 + 184690U, // JE_4 + 184661U, // JGE_1 + 184661U, // JGE_2 + 184661U, // JGE_4 + 184890U, // JG_1 + 184890U, // JG_2 + 184890U, // JG_4 + 184694U, // JLE_1 + 184694U, // JLE_2 + 184694U, // JLE_4 + 185269U, // JL_1 + 185269U, // JL_2 + 185269U, // JL_4 + 38138U, // JMP16m + 38138U, // JMP16m_NT + 21754U, // JMP16r + 21754U, // JMP16r_NT + 70906U, // JMP32m + 70906U, // JMP32m_NT + 21754U, // JMP32r + 21754U, // JMP32r_NT + 87290U, // JMP64m + 87290U, // JMP64m_NT + 21754U, // JMP64r + 21754U, // JMP64r_NT + 185594U, // JMP_1 + 185594U, // JMP_2 + 185594U, // JMP_4 + 184714U, // JNE_1 + 184714U, // JNE_2 + 184714U, // JNE_4 + 185502U, // JNO_1 + 185502U, // JNO_2 + 185502U, // JNO_4 + 185622U, // JNP_1 + 185622U, // JNP_2 + 185622U, // JNP_4 + 187262U, // JNS_1 + 187262U, // JNS_2 + 187262U, // JNS_4 + 185498U, // JO_1 + 185498U, // JO_2 + 185498U, // JO_4 + 185577U, // JP_1 + 185577U, // JP_2 + 185577U, // JP_4 + 190292U, // JRCXZ + 187250U, // JS_1 + 187250U, // JS_2 + 187250U, // JS_4 + 2517648360U, // KADDBrr + 2517649286U, // KADDDrr + 2517653081U, // KADDQrr + 2517656561U, // KADDWrr + 2517648375U, // KANDBrr + 2517649310U, // KANDDrr + 2517648547U, // KANDNBrr + 2517649603U, // KANDNDrr + 2517653504U, // KANDNQrr + 2517656835U, // KANDNWrr + 2517653176U, // KANDQrr + 2517656585U, // KANDWrr + 370165312U, // KMOVBkk + 537937472U, // KMOVBkm + 370165312U, // KMOVBkr + 1148480U, // KMOVBmk + 370165312U, // KMOVBrk + 370167921U, // KMOVDkk + 403722353U, // KMOVDkm + 370167921U, // KMOVDkr + 1118321U, // KMOVDmk + 370167921U, // KMOVDrk + 370170415U, // KMOVQkk + 437279279U, // KMOVQkm + 370170415U, // KMOVQkr + 1137199U, // KMOVQmk + 370170415U, // KMOVQrk + 370173650U, // KMOVWkk + 504391378U, // KMOVWkm + 370173650U, // KMOVWkr + 1091282U, // KMOVWmk + 370173650U, // KMOVWrk + 370165197U, // KNOTBrr + 370167777U, // KNOTDrr + 370170236U, // KNOTQrr + 370173497U, // KNOTWrr + 2517648663U, // KORBrr + 2517650709U, // KORDrr + 2517653686U, // KORQrr + 370165234U, // KORTESTBrr + 370167814U, // KORTESTDrr + 370170282U, // KORTESTQrr + 370173534U, // KORTESTWrr + 2517656915U, // KORWrr + 2517648463U, // KSHIFTLBri + 2517649530U, // KSHIFTLDri + 2517653446U, // KSHIFTLQri + 2517656777U, // KSHIFTLWri + 2517648693U, // KSHIFTRBri + 2517650762U, // KSHIFTRDri + 2517653739U, // KSHIFTRQri + 2517656945U, // KSHIFTRWri + 370165226U, // KTESTBrr + 370167806U, // KTESTDrr + 370170274U, // KTESTQrr + 370173526U, // KTESTWrr + 2517656465U, // KUNPCKBWrr + 2517653118U, // KUNPCKDQrr + 2517651634U, // KUNPCKWDrr + 2517648669U, // KXNORBrr + 2517650715U, // KXNORDrr + 2517653692U, // KXNORQrr + 2517656921U, // KXNORWrr + 2517648677U, // KXORBrr + 2517650738U, // KXORDrr + 2517653715U, // KXORQrr + 2517656929U, // KXORWrr + 11357U, // LAHF + 504388218U, // LAR16rm + 370170490U, // LAR16rr + 504388218U, // LAR32rm + 370170490U, // LAR32rr + 504388218U, // LAR64rm + 370170490U, // LAR64rr + 336618202U, // LDDQUrm + 72424U, // LDMXCSR + 772823860U, // LDS16rm + 772823860U, // LDS32rm + 12245U, // LD_F0 + 10938U, // LD_F1 + 116797U, // LD_F32m + 133181U, // LD_F64m + 313405U, // LD_F80m + 0U, // LD_Fp032 + 0U, // LD_Fp064 + 0U, // LD_Fp080 + 0U, // LD_Fp132 + 0U, // LD_Fp164 + 0U, // LD_Fp180 + 0U, // LD_Fp32m + 0U, // LD_Fp32m64 + 0U, // LD_Fp32m80 + 0U, // LD_Fp64m + 0U, // LD_Fp64m80 + 0U, // LD_Fp80m + 18493U, // LD_Frr + 470827852U, // LEA16r + 470827852U, // LEA32r + 470827852U, // LEA64_32r + 470827852U, // LEA64r + 11344U, // LEAVE + 11344U, // LEAVE64 + 772823899U, // LES16rm + 772823899U, // LES32rm + 11260U, // LFENCE + 772823912U, // LFS16rm + 772823912U, // LFS32rm + 772823912U, // LFS64rm + 303606U, // LGDT16m + 303606U, // LGDT32m + 303606U, // LGDT64m + 772823917U, // LGS16rm + 772823917U, // LGS32rm + 772823917U, // LGS64rm + 303618U, // LIDT16m + 303618U, // LIDT32m + 303618U, // LIDT64m + 41486U, // LLDT16m + 25102U, // LLDT16r + 17368U, // LLWPCB + 17368U, // LLWPCB64 + 42430U, // LMSW16m + 26046U, // LMSW16r + 11424U, // LOCK_PREFIX + 403437U, // LODSB + 420111U, // LODSL + 436642U, // LODSQ + 452806U, // LODSW + 185647U, // LOOP + 184742U, // LOOPE + 184719U, // LOOPNE + 21030U, // LRETIL + 22410U, // LRETIQ + 21030U, // LRETIW + 11378U, // LRETL + 11683U, // LRETQ + 11378U, // LRETW + 504386548U, // LSL16rm + 370168820U, // LSL16rr + 504386548U, // LSL32rm + 370168820U, // LSL32rr + 504386548U, // LSL64rm + 370168820U, // LSL64rr + 772825416U, // LSS16rm + 772825416U, // LSS32rm + 772825416U, // LSS64rm + 39686U, // LTRm + 23302U, // LTRr + 2551208822U, // LWPINS32rmi + 2517654390U, // LWPINS32rri + 2551208822U, // LWPINS64rmi + 2517654390U, // LWPINS64rri + 2551206812U, // LWPVAL32rmi + 2517652380U, // LWPVAL32rri + 2551206812U, // LWPVAL64rmi + 2517652380U, // LWPVAL64rri + 504390200U, // LZCNT16rm + 370172472U, // LZCNT16rr + 403726904U, // LZCNT32rm + 370172472U, // LZCNT32rr + 437281336U, // LZCNT64rm + 370172472U, // LZCNT64rr + 370172642U, // MASKMOVDQU + 370172642U, // MASKMOVDQU64 + 202394814U, // MAXCPDrm + 34622654U, // MAXCPDrr + 202399649U, // MAXCPSrm + 34627489U, // MAXCPSrr + 235949982U, // MAXCSDrm + 34623390U, // MAXCSDrr + 269509072U, // MAXCSSrm + 34628048U, // MAXCSSrr + 202394814U, // MAXPDrm + 34622654U, // MAXPDrr + 202399649U, // MAXPSrm + 34627489U, // MAXPSrr + 235949982U, // MAXSDrm + 235949982U, // MAXSDrm_Int + 34623390U, // MAXSDrr + 34623390U, // MAXSDrr_Int + 269509072U, // MAXSSrm + 269509072U, // MAXSSrm_Int + 34628048U, // MAXSSrr + 34628048U, // MAXSSrr_Int + 11267U, // MFENCE + 202394618U, // MINCPDrm + 34622458U, // MINCPDrr + 202399429U, // MINCPSrm + 34627269U, // MINCPSrr + 235949808U, // MINCSDrm + 34623216U, // MINCSDrr + 269508955U, // MINCSSrm + 34627931U, // MINCSSrr + 202394618U, // MINPDrm + 34622458U, // MINPDrr + 202399429U, // MINPSrm + 34627269U, // MINPSrr + 235949808U, // MINSDrm + 235949808U, // MINSDrm_Int + 34623216U, // MINSDrr + 34623216U, // MINSDrr_Int + 269508955U, // MINSSrm + 269508955U, // MINSSrm_Int + 34627931U, // MINSSrr + 34627931U, // MINSSrr_Int + 672158394U, // MMX_CVTPD2PIirm + 370168506U, // MMX_CVTPD2PIirr + 437275044U, // MMX_CVTPI2PDirm + 370166180U, // MMX_CVTPI2PDirr + 135289951U, // MMX_CVTPI2PSirm + 34626655U, // MMX_CVTPI2PSirr + 605049551U, // MMX_CVTPS2PIirm + 370168527U, // MMX_CVTPS2PIirr + 672158383U, // MMX_CVTTPD2PIirm + 370168495U, // MMX_CVTTPD2PIirr + 605049540U, // MMX_CVTTPS2PIirm + 370168516U, // MMX_CVTTPS2PIirr + 11862U, // MMX_EMMS + 370170412U, // MMX_MASKMOVQ + 370170412U, // MMX_MASKMOVQ64 + 1137200U, // MMX_MOVD64from64rm + 370170416U, // MMX_MOVD64from64rr + 370167922U, // MMX_MOVD64grr + 1118322U, // MMX_MOVD64mr + 403722354U, // MMX_MOVD64rm + 370167922U, // MMX_MOVD64rr + 437279280U, // MMX_MOVD64to64rm + 370170416U, // MMX_MOVD64to64rr + 370169282U, // MMX_MOVDQ2Qrr + 370169282U, // MMX_MOVFR642Qrr + 1137012U, // MMX_MOVNTQmr + 370169391U, // MMX_MOVQ2DQrr + 370169391U, // MMX_MOVQ2FR64rr + 1137200U, // MMX_MOVQ64mr + 437279280U, // MMX_MOVQ64rm + 370170416U, // MMX_MOVQ64rr + 370170416U, // MMX_MOVQ64rr_REV + 437273929U, // MMX_PABSBrm + 370165065U, // MMX_PABSBrr + 437276238U, // MMX_PABSDrm + 370167374U, // MMX_PABSDrr + 437282181U, // MMX_PABSWrm + 370173317U, // MMX_PABSWrr + 135291951U, // MMX_PACKSSDWirm + 34628655U, // MMX_PACKSSDWirr + 135284302U, // MMX_PACKSSWBirm + 34621006U, // MMX_PACKSSWBirr + 135284313U, // MMX_PACKUSWBirm + 34621017U, // MMX_PACKUSWBirr + 135283696U, // MMX_PADDBirm + 34620400U, // MMX_PADDBirr + 135284622U, // MMX_PADDDirm + 34621326U, // MMX_PADDDirr + 135288417U, // MMX_PADDQirm + 34625121U, // MMX_PADDQirr + 135284058U, // MMX_PADDSBirm + 34620762U, // MMX_PADDSBirr + 135292342U, // MMX_PADDSWirm + 34629046U, // MMX_PADDSWirr + 135284113U, // MMX_PADDUSBirm + 34620817U, // MMX_PADDUSBirr + 135292428U, // MMX_PADDUSWirm + 34629132U, // MMX_PADDUSWirr + 135291897U, // MMX_PADDWirm + 34628601U, // MMX_PADDWirr + 2282773158U, // MMX_PALIGNRrmi + 2182109862U, // MMX_PALIGNRrri + 135287933U, // MMX_PANDNirm + 34624637U, // MMX_PANDNirr + 135284917U, // MMX_PANDirm + 34621621U, // MMX_PANDirr + 135283761U, // MMX_PAVGBirm + 34620465U, // MMX_PAVGBirr + 135292018U, // MMX_PAVGWirm + 34628722U, // MMX_PAVGWirr + 135283917U, // MMX_PCMPEQBirm + 34620621U, // MMX_PCMPEQBirr + 135285967U, // MMX_PCMPEQDirm + 34622671U, // MMX_PCMPEQDirr + 135292189U, // MMX_PCMPEQWirm + 34628893U, // MMX_PCMPEQWirr + 135284154U, // MMX_PCMPGTBirm + 34620858U, // MMX_PCMPGTBirr + 135286724U, // MMX_PCMPGTDirm + 34623428U, // MMX_PCMPGTDirr + 135292454U, // MMX_PCMPGTWirm + 34629158U, // MMX_PCMPGTWirr + 2517656956U, // MMX_PEXTRWrr + 135284606U, // MMX_PHADDDrm + 34621310U, // MMX_PHADDDrr + 135292332U, // MMX_PHADDSWrm + 34629036U, // MMX_PHADDSWrr + 135291881U, // MMX_PHADDWrm + 34628585U, // MMX_PHADDWrr + 135284547U, // MMX_PHSUBDrm + 34621251U, // MMX_PHSUBDrr + 135292313U, // MMX_PHSUBSWrm + 34629017U, // MMX_PHSUBSWrr + 135291827U, // MMX_PHSUBWrm + 34628531U, // MMX_PHSUBWrr + 2215667049U, // MMX_PINSRWrm + 2182112617U, // MMX_PINSRWrr + 135292301U, // MMX_PMADDUBSWrm + 34629005U, // MMX_PMADDUBSWrr + 135286941U, // MMX_PMADDWDirm + 34623645U, // MMX_PMADDWDirr + 135292445U, // MMX_PMAXSWirm + 34629149U, // MMX_PMAXSWirr + 135284262U, // MMX_PMAXUBirm + 34620966U, // MMX_PMAXUBirr + 135292363U, // MMX_PMINSWirm + 34629067U, // MMX_PMINSWirr + 135284230U, // MMX_PMINUBirm + 34620934U, // MMX_PMINUBirr + 370164797U, // MMX_PMOVMSKBrr + 135292386U, // MMX_PMULHRSWrm + 34629090U, // MMX_PMULHRSWrr + 135292521U, // MMX_PMULHUWirm + 34629225U, // MMX_PMULHUWirr + 135292047U, // MMX_PMULHWirm + 34628751U, // MMX_PMULHWirr + 135292089U, // MMX_PMULLWirm + 34628793U, // MMX_PMULLWirr + 135288674U, // MMX_PMULUDQirm + 34625378U, // MMX_PMULUDQirr + 135289520U, // MMX_PORirm + 34626224U, // MMX_PORirr + 135291744U, // MMX_PSADBWirm + 34628448U, // MMX_PSADBWirr + 135283752U, // MMX_PSHUFBrm + 34620456U, // MMX_PSHUFBrr + 2584765545U, // MMX_PSHUFWmi + 2517656681U, // MMX_PSHUFWri + 135283884U, // MMX_PSIGNBrm + 34620588U, // MMX_PSIGNBrr + 135284958U, // MMX_PSIGNDrm + 34621662U, // MMX_PSIGNDrr + 135292172U, // MMX_PSIGNWrm + 34628876U, // MMX_PSIGNWrr + 705710161U, // MMX_PSLLDri + 135284817U, // MMX_PSLLDrm + 34621521U, // MMX_PSLLDrr + 705714086U, // MMX_PSLLQri + 135288742U, // MMX_PSLLQrm + 34625446U, // MMX_PSLLQrr + 705717425U, // MMX_PSLLWri + 135292081U, // MMX_PSLLWrm + 34628785U, // MMX_PSLLWrr + 705709862U, // MMX_PSRADri + 135284518U, // MMX_PSRADrm + 34621222U, // MMX_PSRADrr + 705717068U, // MMX_PSRAWri + 135291724U, // MMX_PSRAWrm + 34628428U, // MMX_PSRAWrr + 705710186U, // MMX_PSRLDri + 135284842U, // MMX_PSRLDrm + 34621546U, // MMX_PSRLDrr + 705714111U, // MMX_PSRLQri + 135288767U, // MMX_PSRLQrm + 34625471U, // MMX_PSRLQrr + 705717442U, // MMX_PSRLWri + 135292098U, // MMX_PSRLWrm + 34628802U, // MMX_PSRLWrr + 135283665U, // MMX_PSUBBirm + 34620369U, // MMX_PSUBBirr + 135284556U, // MMX_PSUBDirm + 34621260U, // MMX_PSUBDirr + 135288315U, // MMX_PSUBQirm + 34625019U, // MMX_PSUBQirr + 135284049U, // MMX_PSUBSBirm + 34620753U, // MMX_PSUBSBirr + 135292323U, // MMX_PSUBSWirm + 34629027U, // MMX_PSUBSWirr + 135284103U, // MMX_PSUBUSBirm + 34620807U, // MMX_PSUBUSBirr + 135292418U, // MMX_PSUBUSWirm + 34629122U, // MMX_PSUBUSWirr + 135291836U, // MMX_PSUBWirm + 34628540U, // MMX_PSUBWirr + 135291782U, // MMX_PUNPCKHBWirm + 34628486U, // MMX_PUNPCKHBWirr + 135288435U, // MMX_PUNPCKHDQirm + 34625139U, // MMX_PUNPCKHDQirr + 135286951U, // MMX_PUNPCKHWDirm + 34623655U, // MMX_PUNPCKHWDirr + 101737372U, // MMX_PUNPCKLBWirm + 34628508U, // MMX_PUNPCKLBWirr + 101734034U, // MMX_PUNPCKLDQirm + 34625170U, // MMX_PUNPCKLDQirr + 101732541U, // MMX_PUNPCKLWDirm + 34623677U, // MMX_PUNPCKLWDirr + 135289558U, // MMX_PXORirm + 34626262U, // MMX_PXORirr + 12220U, // MONITORXrrr + 11732U, // MONITORrrr + 11499U, // MONTMUL + 469170U, // MOV16ao16 + 469170U, // MOV16ao32 + 469148U, // MOV16ao64 + 1090328U, // MOV16mi + 1090328U, // MOV16mr + 1090328U, // MOV16ms + 9904920U, // MOV16o16a + 9904920U, // MOV16o32a + 9902886U, // MOV16o64a + 370172696U, // MOV16ri + 370172696U, // MOV16ri_alt + 504390424U, // MOV16rm + 370172696U, // MOV16rr + 370172696U, // MOV16rr_REV + 370172696U, // MOV16rs + 504390424U, // MOV16sm + 370172696U, // MOV16sr + 485712U, // MOV32ao16 + 485712U, // MOV32ao32 + 485688U, // MOV32ao64 + 370172696U, // MOV32cr + 370172696U, // MOV32dr + 1123096U, // MOV32mi + 1123096U, // MOV32mr + 10969880U, // MOV32o16a + 10969880U, // MOV32o32a + 10967846U, // MOV32o64a + 370172696U, // MOV32rc + 370172696U, // MOV32rd + 370172696U, // MOV32ri + 370172696U, // MOV32ri_alt + 403727128U, // MOV32rm + 370172696U, // MOV32rr + 370172696U, // MOV32rr_REV + 370172696U, // MOV32rs + 370172696U, // MOV32sr + 502224U, // MOV64ao32 + 502200U, // MOV64ao64 + 370172696U, // MOV64cr + 370172696U, // MOV64dr + 1139480U, // MOV64mi32 + 1139480U, // MOV64mr + 12034840U, // MOV64o32a + 12032806U, // MOV64o64a + 370172696U, // MOV64rc + 370172696U, // MOV64rd + 370170662U, // MOV64ri + 370172696U, // MOV64ri32 + 437281560U, // MOV64rm + 370172696U, // MOV64rr + 370172696U, // MOV64rr_REV + 370172696U, // MOV64rs + 370172696U, // MOV64sr + 437279280U, // MOV64toPQIrm + 370170416U, // MOV64toPQIrr + 437279280U, // MOV64toSDrm + 370170416U, // MOV64toSDrr + 518220U, // MOV8ao16 + 518220U, // MOV8ao32 + 518198U, // MOV8ao64 + 1155864U, // MOV8mi + 1155864U, // MOV8mr + 1155864U, // MOV8mr_NOREX + 13099800U, // MOV8o16a + 13099800U, // MOV8o32a + 13097766U, // MOV8o64a + 370172696U, // MOV8ri + 370172696U, // MOV8ri_alt + 537944856U, // MOV8rm + 537944856U, // MOV8rm_NOREX + 370172696U, // MOV8rr + 370172696U, // MOV8rr_NOREX + 370172696U, // MOV8rr_REV + 1575562U, // MOVAPDmr + 672156298U, // MOVAPDrm + 370166410U, // MOVAPDrr + 370166410U, // MOVAPDrr_REV + 1580346U, // MOVAPSmr + 672161082U, // MOVAPSrm + 370171194U, // MOVAPSrr + 370171194U, // MOVAPSrr_REV + 1085758U, // MOVBE16mr + 504385854U, // MOVBE16rm + 1118526U, // MOVBE32mr + 403722558U, // MOVBE32rm + 1134910U, // MOVBE64mr + 437276990U, // MOVBE64rm + 605050224U, // MOVDDUPrm + 370169200U, // MOVDDUPrr + 403722354U, // MOVDI2PDIrm + 370167922U, // MOVDI2PDIrr + 403722354U, // MOVDI2SSrm + 370167922U, // MOVDI2SSrr + 806372257U, // MOVDIR64B16 + 806372257U, // MOVDIR64B32 + 806372257U, // MOVDIR64B64 + 1118954U, // MOVDIRI32 + 1135338U, // MOVDIRI64 + 1196897U, // MOVDQAmr + 336610145U, // MOVDQArm + 370164577U, // MOVDQArr + 370164577U, // MOVDQArr_REV + 1204966U, // MOVDQUmr + 336618214U, // MOVDQUrm + 370172646U, // MOVDQUrr + 370172646U, // MOVDQUrr_REV + 34627178U, // MOVHLPSrr + 1182605U, // MOVHPDmr + 235948941U, // MOVHPDrm + 1187414U, // MOVHPSmr + 235953750U, // MOVHPSrm + 34627148U, // MOVLHPSrr + 1182655U, // MOVLPDmr + 235948991U, // MOVLPDrm + 1187474U, // MOVLPSmr + 235953810U, // MOVLPSrm + 370166678U, // MOVMSKPDrr + 370171487U, // MOVMSKPSrr + 336610134U, // MOVNTDQArm + 1578779U, // MOVNTDQmr + 1135473U, // MOVNTI_64mr + 1119089U, // MOVNTImr + 1576058U, // MOVNTPDmr + 1580872U, // MOVNTPSmr + 1183586U, // MOVNTSD + 1171861U, // MOVNTSS + 1118322U, // MOVPDI2DImr + 370167922U, // MOVPDI2DIrr + 1137200U, // MOVPQI2QImr + 370170416U, // MOVPQI2QIrr + 1137200U, // MOVPQIto64mr + 370170416U, // MOVPQIto64rr + 437279280U, // MOVQI2PQIrm + 840254883U, // MOVSB + 1183637U, // MOVSDmr + 605048725U, // MOVSDrm + 34623381U, // MOVSDrr + 34623381U, // MOVSDrr_REV + 1137200U, // MOVSDto64mr + 370170416U, // MOVSDto64rr + 672159098U, // MOVSHDUPrm + 370169210U, // MOVSHDUPrr + 873828245U, // MOVSL + 672159109U, // MOVSLDUPrm + 370169221U, // MOVSLDUPrr + 907565369U, // MOVSQ + 1118322U, // MOVSS2DImr + 370167922U, // MOVSS2DIrr + 1171912U, // MOVSSmr + 638607816U, // MOVSSrm + 34628040U, // MOVSSrr + 34628040U, // MOVSSrr_REV + 940959253U, // MOVSW + 504391463U, // MOVSX16rm16 + 537945895U, // MOVSX16rm8 + 370173735U, // MOVSX16rr16 + 370173735U, // MOVSX16rr8 + 504391463U, // MOVSX32rm16 + 537945895U, // MOVSX32rm8 + 537945895U, // MOVSX32rm8_NOREX + 370173735U, // MOVSX32rr16 + 370173735U, // MOVSX32rr8 + 370173735U, // MOVSX32rr8_NOREX + 504391463U, // MOVSX64rm16 + 403722517U, // MOVSX64rm32 + 537945895U, // MOVSX64rm8 + 370173735U, // MOVSX64rr16 + 370168085U, // MOVSX64rr32 + 370173735U, // MOVSX64rr8 + 1576086U, // MOVUPDmr + 672156822U, // MOVUPDrm + 370166934U, // MOVUPDrr + 370166934U, // MOVUPDrr_REV + 1580921U, // MOVUPSmr + 672161657U, // MOVUPSrm + 370171769U, // MOVUPSrr + 370171769U, // MOVUPSrr_REV + 370170416U, // MOVZPQILo2PQIrr + 504391478U, // MOVZX16rm16 + 537945910U, // MOVZX16rm8 + 370173750U, // MOVZX16rr16 + 370173750U, // MOVZX16rr8 + 504391478U, // MOVZX32rm16 + 537945910U, // MOVZX32rm8 + 537945910U, // MOVZX32rm8_NOREX + 370173750U, // MOVZX32rr16 + 370173750U, // MOVZX32rr8 + 370173750U, // MOVZX32rr8_NOREX + 504391478U, // MOVZX64rm16 + 537945910U, // MOVZX64rm8 + 370173750U, // MOVZX64rr16 + 370173750U, // MOVZX64rr8 + 2450547561U, // MPSADBWrmi + 2182112105U, // MPSADBWrri + 37889U, // MUL16m + 21505U, // MUL16r + 70657U, // MUL32m + 21505U, // MUL32r + 87041U, // MUL64m + 21505U, // MUL64r + 103425U, // MUL8m + 21505U, // MUL8r + 202394551U, // MULPDrm + 34622391U, // MULPDrr + 202399370U, // MULPSrm + 34627210U, // MULPSrr + 235949786U, // MULSDrm + 235949786U, // MULSDrm_Int + 34623194U, // MULSDrr + 34623194U, // MULSDrr_Int + 269508934U, // MULSSrm + 269508934U, // MULSSrm_Int + 34627910U, // MULSSrr + 34627910U, // MULSSrr_Int + 2517657353U, // MULX32rm + 2517657353U, // MULX32rr + 2517657353U, // MULX64rm + 2517657353U, // MULX64rr + 119808U, // MUL_F32m + 136192U, // MUL_F64m + 37894U, // MUL_FI16m + 70662U, // MUL_FI32m + 21741U, // MUL_FPrST0 + 21504U, // MUL_FST0r + 0U, // MUL_Fp32 + 0U, // MUL_Fp32m + 0U, // MUL_Fp64 + 0U, // MUL_Fp64m + 0U, // MUL_Fp64m32 + 0U, // MUL_Fp80 + 0U, // MUL_Fp80m32 + 0U, // MUL_Fp80m64 + 0U, // MUL_FpI16m32 + 0U, // MUL_FpI16m64 + 0U, // MUL_FpI16m80 + 0U, // MUL_FpI32m32 + 0U, // MUL_FpI32m64 + 0U, // MUL_FpI32m80 + 2118656U, // MUL_FrST0 + 12229U, // MWAITXrrr + 11927U, // MWAITrr + 37420U, // NEG16m + 21036U, // NEG16r + 70188U, // NEG32m + 21036U, // NEG32r + 86572U, // NEG64m + 21036U, // NEG64r + 102956U, // NEG8m + 21036U, // NEG8r + 11600U, // NOOP + 38186U, // NOOP18_16m4 + 38186U, // NOOP18_16m5 + 38186U, // NOOP18_16m6 + 38186U, // NOOP18_16m7 + 21802U, // NOOP18_16r4 + 21802U, // NOOP18_16r5 + 21802U, // NOOP18_16r6 + 21802U, // NOOP18_16r7 + 70954U, // NOOP18_m4 + 70954U, // NOOP18_m5 + 70954U, // NOOP18_m6 + 70954U, // NOOP18_m7 + 21802U, // NOOP18_r4 + 21802U, // NOOP18_r5 + 21802U, // NOOP18_r6 + 21802U, // NOOP18_r7 + 739300650U, // NOOP19rr + 70954U, // NOOPL + 70954U, // NOOPL_19 + 70954U, // NOOPL_1d + 70954U, // NOOPL_1e + 21802U, // NOOPLr + 87338U, // NOOPQ + 21802U, // NOOPQr + 38186U, // NOOPW + 38186U, // NOOPW_19 + 38186U, // NOOPW_1c + 38186U, // NOOPW_1d + 38186U, // NOOPW_1e + 21802U, // NOOPWr + 41547U, // NOT16m + 25163U, // NOT16r + 74315U, // NOT32m + 25163U, // NOT32r + 90699U, // NOT64m + 25163U, // NOT64r + 107083U, // NOT8m + 25163U, // NOT8r + 26772U, // OR16i16 + 1088177U, // OR16mi + 1088177U, // OR16mi8 + 1088177U, // OR16mr + 34658993U, // OR16ri + 34658993U, // OR16ri8 + 68213425U, // OR16rm + 34658993U, // OR16rr + 34626225U, // OR16rr_REV + 26927U, // OR32i32 + 1120945U, // OR32mi + 1120945U, // OR32mi8 + 1120945U, // OR32mr + 34658993U, // OR32ri + 34658993U, // OR32ri8 + 101767857U, // OR32rm + 34658993U, // OR32rr + 34626225U, // OR32rr_REV + 27055U, // OR64i32 + 1137329U, // OR64mi32 + 1137329U, // OR64mi8 + 1137329U, // OR64mr + 34658993U, // OR64ri32 + 34658993U, // OR64ri8 + 135322289U, // OR64rm + 34658993U, // OR64rr + 34626225U, // OR64rr_REV + 26670U, // OR8i8 + 1153713U, // OR8mi + 1153713U, // OR8mi8 + 1153713U, // OR8mr + 34658993U, // OR8ri + 34658993U, // OR8ri8 + 168876721U, // OR8rm + 34658993U, // OR8rr + 34626225U, // OR8rr_REV + 202394677U, // ORPDrm + 34622517U, // ORPDrr + 202399496U, // ORPSrm + 34627336U, // ORPSrr + 9773767U, // OUT16ir + 12050U, // OUT16rr + 10822343U, // OUT32ir + 12104U, // OUT32rr + 12919495U, // OUT8ir + 11429U, // OUT8rr + 403930U, // OUTSB + 420325U, // OUTSL + 453104U, // OUTSW + 336610633U, // PABSBrm + 370165065U, // PABSBrr + 336612942U, // PABSDrm + 370167374U, // PABSDrr + 336618885U, // PABSWrm + 370173317U, // PABSWrr + 303064111U, // PACKSSDWrm + 34628655U, // PACKSSDWrr + 303056462U, // PACKSSWBrm + 34621006U, // PACKSSWBrr + 303064122U, // PACKUSDWrm + 34628666U, // PACKUSDWrr + 303056473U, // PACKUSWBrm + 34621017U, // PACKUSWBrr + 303055856U, // PADDBrm + 34620400U, // PADDBrr + 303056782U, // PADDDrm + 34621326U, // PADDDrr + 303060577U, // PADDQrm + 34625121U, // PADDQrr + 303056218U, // PADDSBrm + 34620762U, // PADDSBrr + 303064502U, // PADDSWrm + 34629046U, // PADDSWrr + 303056273U, // PADDUSBrm + 34620817U, // PADDUSBrr + 303064588U, // PADDUSWrm + 34629132U, // PADDUSWrr + 303064057U, // PADDWrm + 34628601U, // PADDWrr + 2450545318U, // PALIGNRrmi + 2182109862U, // PALIGNRrri + 303060093U, // PANDNrm + 34624637U, // PANDNrr + 303057077U, // PANDrm + 34621621U, // PANDrr + 11338U, // PAUSE + 303055921U, // PAVGBrm + 34620465U, // PAVGBrr + 135284122U, // PAVGUSBrm + 34620826U, // PAVGUSBrr + 303064178U, // PAVGWrm + 34628722U, // PAVGWrr + 303056431U, // PBLENDVBrm0 + 34620975U, // PBLENDVBrr0 + 2450547740U, // PBLENDWrmi + 2182112284U, // PBLENDWrri + 2450544365U, // PCLMULQDQrm + 2182108909U, // PCLMULQDQrr + 303056077U, // PCMPEQBrm + 34620621U, // PCMPEQBrr + 303058127U, // PCMPEQDrm + 34622671U, // PCMPEQDrr + 303061090U, // PCMPEQQrm + 34625634U, // PCMPEQQrr + 303064349U, // PCMPEQWrm + 34628893U, // PCMPEQWrr + 2484097780U, // PCMPESTRIrm + 2517652212U, // PCMPESTRIrr + 2484098142U, // PCMPESTRMrm + 2517652574U, // PCMPESTRMrr + 303056314U, // PCMPGTBrm + 34620858U, // PCMPGTBrr + 303058884U, // PCMPGTDrm + 34623428U, // PCMPGTDrr + 303061335U, // PCMPGTQrm + 34625879U, // PCMPGTQrr + 303064614U, // PCMPGTWrm + 34629158U, // PCMPGTWrr + 2484097792U, // PCMPISTRIrm + 2517652224U, // PCMPISTRIrr + 2484098154U, // PCMPISTRMrm + 2517652586U, // PCMPISTRMrr + 11383U, // PCONFIG + 2517652699U, // PDEP32rm + 2517652699U, // PDEP32rr + 2517652699U, // PDEP64rm + 2517652699U, // PDEP64rr + 2517656268U, // PEXT32rm + 2517656268U, // PEXT32rr + 2517656268U, // PEXT64rm + 2517656268U, // PEXT64rr + 2148631872U, // PEXTRBmr + 2517648704U, // PEXTRBrr + 2148601173U, // PEXTRDmr + 2517650773U, // PEXTRDrr + 2148620534U, // PEXTRQmr + 2517653750U, // PEXTRQrr + 2148574588U, // PEXTRWmr + 2517656956U, // PEXTRWrr + 2517656956U, // PEXTRWrr_REV + 437274653U, // PF2IDrm + 370165789U, // PF2IDrr + 437281943U, // PF2IWrm + 370173079U, // PF2IWrr + 135284353U, // PFACCrm + 34621057U, // PFACCrr + 135284585U, // PFADDrm + 34621289U, // PFADDrr + 135288705U, // PFCMPEQrm + 34625409U, // PFCMPEQrr + 135287130U, // PFCMPGErm + 34623834U, // PFCMPGErr + 135291423U, // PFCMPGTrm + 34628127U, // PFCMPGTrr + 135292654U, // PFMAXrm + 34629358U, // PFMAXrr + 135287948U, // PFMINrm + 34624652U, // PFMINrr + 135287807U, // PFMULrm + 34624511U, // PFMULrr + 135284360U, // PFNACCrm + 34621064U, // PFNACCrr + 135284368U, // PFPNACCrm + 34621072U, // PFPNACCrr + 135282735U, // PFRCPIT1rm + 34619439U, // PFRCPIT1rr + 135282844U, // PFRCPIT2rm + 34619548U, // PFRCPIT2rr + 437277901U, // PFRCPrm + 370169037U, // PFRCPrr + 135282745U, // PFRSQIT1rm + 34619449U, // PFRSQIT1rr + 437281398U, // PFRSQRTrm + 370172534U, // PFRSQRTrr + 135289476U, // PFSUBRrm + 34626180U, // PFSUBRrr + 135284247U, // PFSUBrm + 34620951U, // PFSUBrr + 303056766U, // PHADDDrm + 34621310U, // PHADDDrr + 303064492U, // PHADDSWrm + 34629036U, // PHADDSWrr + 303064041U, // PHADDWrm + 34628585U, // PHADDWrr + 336619150U, // PHMINPOSUWrm + 370173582U, // PHMINPOSUWrr + 303056707U, // PHSUBDrm + 34621251U, // PHSUBDrr + 303064473U, // PHSUBSWrm + 34629017U, // PHSUBSWrr + 303063987U, // PHSUBWrm + 34628531U, // PHSUBWrr + 437274625U, // PI2FDrm + 370165761U, // PI2FDrr + 437281890U, // PI2FWrm + 370173026U, // PI2FWrr + 2316322093U, // PINSRBrm + 2182104365U, // PINSRBrr + 2249215298U, // PINSRDrm + 2182106434U, // PINSRDrr + 2282772707U, // PINSRQrm + 2182109411U, // PINSRQrr + 2215667049U, // PINSRWrm + 2182112617U, // PINSRWrr + 303064461U, // PMADDUBSWrm + 34629005U, // PMADDUBSWrr + 303059101U, // PMADDWDrm + 34623645U, // PMADDWDrr + 303056299U, // PMAXSBrm + 34620843U, // PMAXSBrr + 303058845U, // PMAXSDrm + 34623389U, // PMAXSDrr + 303064605U, // PMAXSWrm + 34629149U, // PMAXSWrr + 303056422U, // PMAXUBrm + 34620966U, // PMAXUBrr + 303058988U, // PMAXUDrm + 34623532U, // PMAXUDrr + 303064731U, // PMAXUWrm + 34629275U, // PMAXUWrr + 303056227U, // PMINSBrm + 34620771U, // PMINSBrr + 303058671U, // PMINSDrm + 34623215U, // PMINSDrr + 303064523U, // PMINSWrm + 34629067U, // PMINSWrr + 303056390U, // PMINUBrm + 34620934U, // PMINUBrr + 303058970U, // PMINUDrm + 34623514U, // PMINUDrr + 303064700U, // PMINUWrm + 34629244U, // PMINUWrr + 370164797U, // PMOVMSKBrr + 403720020U, // PMOVSXBDrm + 370165588U, // PMOVSXBDrr + 504387075U, // PMOVSXBQrm + 370169347U, // PMOVSXBQrr + 437281732U, // PMOVSXBWrm + 370172868U, // PMOVSXBWrr + 437278572U, // PMOVSXDQrm + 370169708U, // PMOVSXDQrr + 437276928U, // PMOVSXWDrm + 370168064U, // PMOVSXWDrr + 403724892U, // PMOVSXWQrm + 370170460U, // PMOVSXWQrr + 403720031U, // PMOVZXBDrm + 370165599U, // PMOVZXBDrr + 504387086U, // PMOVZXBQrm + 370169358U, // PMOVZXBQrr + 437281743U, // PMOVZXBWrm + 370172879U, // PMOVZXBWrr + 437278583U, // PMOVZXDQrm + 370169719U, // PMOVZXDQrr + 437276939U, // PMOVZXWDrm + 370168075U, // PMOVZXWDrr + 403724903U, // PMOVZXWQrm + 370170471U, // PMOVZXWQrr + 303060656U, // PMULDQrm + 34625200U, // PMULDQrr + 303064546U, // PMULHRSWrm + 34629090U, // PMULHRSWrr + 135292234U, // PMULHRWrm + 34628938U, // PMULHRWrr + 303064681U, // PMULHUWrm + 34629225U, // PMULHUWrr + 303064207U, // PMULHWrm + 34628751U, // PMULHWrr + 303056985U, // PMULLDrm + 34621529U, // PMULLDrr + 303064249U, // PMULLWrm + 34628793U, // PMULLWrr + 303060834U, // PMULUDQrm + 34625378U, // PMULUDQrr + 21813U, // POP16r + 38197U, // POP16rmm + 21813U, // POP16rmr + 21813U, // POP32r + 70965U, // POP32rmm + 21813U, // POP32rmr + 21813U, // POP64r + 87349U, // POP64rmm + 21813U, // POP64rmr + 12024U, // POPA16 + 11447U, // POPA32 + 504390192U, // POPCNT16rm + 370172464U, // POPCNT16rr + 403726896U, // POPCNT32rm + 370172464U, // POPCNT32rr + 437281328U, // POPCNT64rm + 370172464U, // POPCNT64rr + 11791U, // POPDS16 + 11791U, // POPDS32 + 11806U, // POPES16 + 11806U, // POPES32 + 11373U, // POPF16 + 11202U, // POPF32 + 11677U, // POPF64 + 11821U, // POPFS16 + 11821U, // POPFS32 + 11821U, // POPFS64 + 11836U, // POPGS16 + 11836U, // POPGS32 + 11836U, // POPGS64 + 11888U, // POPSS16 + 11888U, // POPSS32 + 303061680U, // PORrm + 34626224U, // PORrr + 102995U, // PREFETCH + 99183U, // PREFETCHNTA + 98305U, // PREFETCHT0 + 98339U, // PREFETCHT1 + 98448U, // PREFETCHT2 + 107641U, // PREFETCHW + 98371U, // PREFETCHWT1 + 303063904U, // PSADBWrm + 34628448U, // PSADBWrr + 303055912U, // PSHUFBrm + 34620456U, // PSHUFBrr + 2484094985U, // PSHUFDmi + 2517649417U, // PSHUFDri + 2484102277U, // PSHUFHWmi + 2517656709U, // PSHUFHWri + 2484102303U, // PSHUFLWmi + 2517656735U, // PSHUFLWri + 303056044U, // PSIGNBrm + 34620588U, // PSIGNBrr + 303057118U, // PSIGNDrm + 34621662U, // PSIGNDrr + 303064332U, // PSIGNWrm + 34628876U, // PSIGNWrr + 705713822U, // PSLLDQri + 705710161U, // PSLLDri + 303056977U, // PSLLDrm + 34621521U, // PSLLDrr + 705714086U, // PSLLQri + 303060902U, // PSLLQrm + 34625446U, // PSLLQrr + 705717425U, // PSLLWri + 303064241U, // PSLLWrm + 34628785U, // PSLLWrr + 705709862U, // PSRADri + 303056678U, // PSRADrm + 34621222U, // PSRADrr + 705717068U, // PSRAWri + 303063884U, // PSRAWrm + 34628428U, // PSRAWrr + 705713831U, // PSRLDQri + 705710186U, // PSRLDri + 303057002U, // PSRLDrm + 34621546U, // PSRLDrr + 705714111U, // PSRLQri + 303060927U, // PSRLQrm + 34625471U, // PSRLQrr + 705717442U, // PSRLWri + 303064258U, // PSRLWrm + 34628802U, // PSRLWrr + 303055825U, // PSUBBrm + 34620369U, // PSUBBrr + 303056716U, // PSUBDrm + 34621260U, // PSUBDrr + 303060475U, // PSUBQrm + 34625019U, // PSUBQrr + 303056209U, // PSUBSBrm + 34620753U, // PSUBSBrr + 303064483U, // PSUBSWrm + 34629027U, // PSUBSWrr + 303056263U, // PSUBUSBrm + 34620807U, // PSUBUSBrr + 303064578U, // PSUBUSWrm + 34629122U, // PSUBUSWrr + 303063996U, // PSUBWrm + 34628540U, // PSUBWrr + 437275282U, // PSWAPDrm + 370166418U, // PSWAPDrr + 672162458U, // PTESTrm + 370172570U, // PTESTrr + 86508U, // PTWRITE64m + 20972U, // PTWRITE64r + 70124U, // PTWRITEm + 20972U, // PTWRITEr + 303063942U, // PUNPCKHBWrm + 34628486U, // PUNPCKHBWrr + 303060595U, // PUNPCKHDQrm + 34625139U, // PUNPCKHDQrr + 303060691U, // PUNPCKHQDQrm + 34625235U, // PUNPCKHQDQrr + 303059111U, // PUNPCKHWDrm + 34623655U, // PUNPCKHWDrr + 303063964U, // PUNPCKLBWrm + 34628508U, // PUNPCKLBWrr + 303060626U, // PUNPCKLDQrm + 34625170U, // PUNPCKLDQrr + 303060704U, // PUNPCKLQDQrm + 34625248U, // PUNPCKLQDQrr + 303059133U, // PUNPCKLWDrm + 34623677U, // PUNPCKLWDrr + 21134U, // PUSH16i8 + 21134U, // PUSH16r + 37518U, // PUSH16rmm + 21134U, // PUSH16rmr + 21134U, // PUSH32i8 + 21134U, // PUSH32r + 70286U, // PUSH32rmm + 21134U, // PUSH32rmr + 21134U, // PUSH64i32 + 21134U, // PUSH64i8 + 21134U, // PUSH64r + 86670U, // PUSH64rmm + 21134U, // PUSH64rmr + 12017U, // PUSHA16 + 11440U, // PUSHA32 + 11775U, // PUSHCS16 + 11775U, // PUSHCS32 + 11783U, // PUSHDS16 + 11783U, // PUSHDS32 + 11798U, // PUSHES16 + 11798U, // PUSHES32 + 11367U, // PUSHF16 + 11195U, // PUSHF32 + 11670U, // PUSHF64 + 11813U, // PUSHFS16 + 11813U, // PUSHFS32 + 11813U, // PUSHFS64 + 11828U, // PUSHGS16 + 11828U, // PUSHGS32 + 11828U, // PUSHGS64 + 11880U, // PUSHSS16 + 11880U, // PUSHSS32 + 21134U, // PUSHi16 + 21134U, // PUSHi32 + 303061718U, // PXORrm + 34626262U, // PXORrr + 37803U, // RCL16m1 + 13669291U, // RCL16mCL + 974164907U, // RCL16mi + 14701483U, // RCL16r1 + 13652907U, // RCL16rCL + 705713067U, // RCL16ri + 70571U, // RCL32m1 + 13702059U, // RCL32mCL + 974197675U, // RCL32mi + 14701483U, // RCL32r1 + 13652907U, // RCL32rCL + 705713067U, // RCL32ri + 86955U, // RCL64m1 + 13718443U, // RCL64mCL + 974214059U, // RCL64mi + 14701483U, // RCL64r1 + 13652907U, // RCL64rCL + 705713067U, // RCL64ri + 103339U, // RCL8m1 + 13734827U, // RCL8mCL + 974230443U, // RCL8mi + 14701483U, // RCL8r1 + 13652907U, // RCL8rCL + 705713067U, // RCL8ri + 672161485U, // RCPPSm + 370171597U, // RCPPSr + 638607715U, // RCPSSm + 269508963U, // RCPSSm_Int + 370172259U, // RCPSSr + 34627939U, // RCPSSr_Int + 14719636U, // RCR16m1 + 13671060U, // RCR16mCL + 974166676U, // RCR16mi + 14703252U, // RCR16r1 + 13654676U, // RCR16rCL + 705714836U, // RCR16ri + 14752404U, // RCR32m1 + 13703828U, // RCR32mCL + 974199444U, // RCR32mi + 14703252U, // RCR32r1 + 13654676U, // RCR32rCL + 705714836U, // RCR32ri + 14768788U, // RCR64m1 + 13720212U, // RCR64mCL + 974215828U, // RCR64mi + 14703252U, // RCR64r1 + 13654676U, // RCR64rCL + 705714836U, // RCR64ri + 14785172U, // RCR8m1 + 13736596U, // RCR8mCL + 974232212U, // RCR8mi + 14703252U, // RCR8r1 + 13654676U, // RCR8rCL + 705714836U, // RCR8ri + 20909U, // RDFSBASE + 20909U, // RDFSBASE64 + 20929U, // RDGSBASE + 20929U, // RDGSBASE64 + 11740U, // RDMSR + 18477U, // RDPID32 + 18477U, // RDPID64 + 11983U, // RDPKRUr + 11172U, // RDPMC + 18619U, // RDRAND16r + 18619U, // RDRAND32r + 18619U, // RDRAND64r + 18425U, // RDSEED16r + 18425U, // RDSEED32r + 18425U, // RDSEED64r + 19544U, // RDSSPD + 22571U, // RDSSPQ + 11185U, // RDTSC + 11569U, // RDTSCP + 11302U, // REPNE_PREFIX + 11576U, // REP_PREFIX + 25114U, // RETIL + 25114U, // RETIQ + 25114U, // RETIW + 11916U, // RETL + 11916U, // RETQ + 11916U, // RETW + 11012U, // REX64_PREFIX + 14717906U, // ROL16m1 + 13669330U, // ROL16mCL + 974164946U, // ROL16mi + 14701522U, // ROL16r1 + 13652946U, // ROL16rCL + 705713106U, // ROL16ri + 14750674U, // ROL32m1 + 13702098U, // ROL32mCL + 974197714U, // ROL32mi + 14701522U, // ROL32r1 + 13652946U, // ROL32rCL + 705713106U, // ROL32ri + 14767058U, // ROL64m1 + 13718482U, // ROL64mCL + 974214098U, // ROL64mi + 14701522U, // ROL64r1 + 13652946U, // ROL64rCL + 705713106U, // ROL64ri + 14783442U, // ROL8m1 + 13734866U, // ROL8mCL + 974230482U, // ROL8mi + 14701522U, // ROL8r1 + 13652946U, // ROL8rCL + 705713106U, // ROL8ri + 14719669U, // ROR16m1 + 13671093U, // ROR16mCL + 974166709U, // ROR16mi + 14703285U, // ROR16r1 + 13654709U, // ROR16rCL + 705714869U, // ROR16ri + 14752437U, // ROR32m1 + 13703861U, // ROR32mCL + 974199477U, // ROR32mi + 14703285U, // ROR32r1 + 13654709U, // ROR32rCL + 705714869U, // ROR32ri + 14768821U, // ROR64m1 + 13720245U, // ROR64mCL + 974215861U, // ROR64mi + 14703285U, // ROR64r1 + 13654709U, // ROR64rCL + 705714869U, // ROR64ri + 14785205U, // ROR8m1 + 13736629U, // ROR8mCL + 974232245U, // ROR8mi + 14703285U, // ROR8r1 + 13654709U, // ROR8rCL + 705714869U, // ROR8ri + 2551211809U, // RORX32mi + 2517657377U, // RORX32ri + 2584766241U, // RORX64mi + 2517657377U, // RORX64ri + 2819640105U, // ROUNDPDm + 2517650217U, // ROUNDPDr + 2819644904U, // ROUNDPSm + 2517655016U, // ROUNDPSr + 2752532112U, // ROUNDSDm + 2383433360U, // ROUNDSDm_Int + 2517651088U, // ROUNDSDr + 2182106768U, // ROUNDSDr_Int + 2786091260U, // ROUNDSSm + 2416992508U, // ROUNDSSm_Int + 2517655804U, // ROUNDSSr + 2182111484U, // ROUNDSSr_Int + 11531U, // RSM + 672161629U, // RSQRTPSm + 370171741U, // RSQRTPSr + 638607775U, // RSQRTSSm + 269509023U, // RSQRTSSm_Int + 370172319U, // RSQRTSSr + 34627999U, // RSQRTSSr_Int + 70986U, // RSTORSSP + 11362U, // SAHF + 14717847U, // SAL16m1 + 13669271U, // SAL16mCL + 1086359U, // SAL16mi + 14701463U, // SAL16r1 + 13652887U, // SAL16rCL + 34624407U, // SAL16ri + 14750615U, // SAL32m1 + 13702039U, // SAL32mCL + 1119127U, // SAL32mi + 14701463U, // SAL32r1 + 13652887U, // SAL32rCL + 34624407U, // SAL32ri + 14766999U, // SAL64m1 + 13718423U, // SAL64mCL + 1135511U, // SAL64mi + 14701463U, // SAL64r1 + 13652887U, // SAL64rCL + 34624407U, // SAL64ri + 14783383U, // SAL8m1 + 13734807U, // SAL8mCL + 1151895U, // SAL8mi + 14701463U, // SAL8r1 + 13652887U, // SAL8rCL + 34624407U, // SAL8ri + 11159U, // SALC + 14719615U, // SAR16m1 + 13671039U, // SAR16mCL + 974166655U, // SAR16mi + 14703231U, // SAR16r1 + 13654655U, // SAR16rCL + 705714815U, // SAR16ri + 14752383U, // SAR32m1 + 13703807U, // SAR32mCL + 974199423U, // SAR32mi + 14703231U, // SAR32r1 + 13654655U, // SAR32rCL + 705714815U, // SAR32ri + 14768767U, // SAR64m1 + 13720191U, // SAR64mCL + 974215807U, // SAR64mi + 14703231U, // SAR64r1 + 13654655U, // SAR64rCL + 705714815U, // SAR64ri + 14785151U, // SAR8m1 + 13736575U, // SAR8mCL + 974232191U, // SAR8mi + 14703231U, // SAR8r1 + 13654655U, // SAR8rCL + 705714815U, // SAR8ri + 2551211797U, // SARX32rm + 2517657365U, // SARX32rr + 2584766229U, // SARX64rm + 2517657365U, // SARX64rr + 11638U, // SAVEPREVSSP + 26709U, // SBB16i16 + 1082315U, // SBB16mi + 1082315U, // SBB16mi8 + 1082315U, // SBB16mr + 34653131U, // SBB16ri + 34653131U, // SBB16ri8 + 68207563U, // SBB16rm + 34653131U, // SBB16rr + 34620363U, // SBB16rr_REV + 26833U, // SBB32i32 + 1115083U, // SBB32mi + 1115083U, // SBB32mi8 + 1115083U, // SBB32mr + 34653131U, // SBB32ri + 34653131U, // SBB32ri8 + 101761995U, // SBB32rm + 34653131U, // SBB32rr + 34620363U, // SBB32rr_REV + 26970U, // SBB64i32 + 1131467U, // SBB64mi32 + 1131467U, // SBB64mi8 + 1131467U, // SBB64mr + 34653131U, // SBB64ri32 + 34653131U, // SBB64ri8 + 135316427U, // SBB64rm + 34653131U, // SBB64rr + 34620363U, // SBB64rr_REV + 26585U, // SBB8i8 + 1147851U, // SBB8mi + 1147851U, // SBB8mi8 + 1147851U, // SBB8mr + 34653131U, // SBB8ri + 34653131U, // SBB8ri8 + 168870859U, // SBB8rm + 34653131U, // SBB8rr + 34620363U, // SBB8rr_REV + 354274U, // SCASB + 370947U, // SCASL + 551318U, // SCASQ + 387259U, // SCASW + 102690U, // SETAEm + 20770U, // SETAEr + 99177U, // SETAm + 17257U, // SETAr + 102710U, // SETBEm + 20790U, // SETBEr + 99763U, // SETBm + 17843U, // SETBr + 102877U, // SETEm + 20957U, // SETEr + 102755U, // SETGEm + 20835U, // SETGEr + 102982U, // SETGm + 21062U, // SETGr + 102779U, // SETLEm + 20859U, // SETLEr + 103417U, // SETLm + 21497U, // SETLr + 102807U, // SETNEm + 20887U, // SETNEr + 103587U, // SETNOm + 21667U, // SETNOr + 103707U, // SETNPm + 21787U, // SETNPr + 105347U, // SETNSm + 23427U, // SETNSr + 103602U, // SETOm + 21682U, // SETOr + 103764U, // SETPm + 21844U, // SETPr + 12236U, // SETSSBSY + 106981U, // SETSm + 25061U, // SETSr + 11274U, // SFENCE + 303612U, // SGDT16m + 303612U, // SGDT32m + 303612U, // SGDT64m + 303054861U, // SHA1MSG1rm + 34619405U, // SHA1MSG1rr + 303054957U, // SHA1MSG2rm + 34619501U, // SHA1MSG2rr + 303059455U, // SHA1NEXTErm + 34623999U, // SHA1NEXTErr + 2450538898U, // SHA1RNDS4rmi + 2182103442U, // SHA1RNDS4rri + 303054871U, // SHA256MSG1rm + 34619415U, // SHA256MSG1rr + 303054967U, // SHA256MSG2rm + 34619511U, // SHA256MSG2rr + 303054979U, // SHA256RNDS2rm + 34619523U, // SHA256RNDS2rr + 14717872U, // SHL16m1 + 13669296U, // SHL16mCL + 974164912U, // SHL16mi + 14701488U, // SHL16r1 + 13652912U, // SHL16rCL + 705713072U, // SHL16ri + 14750640U, // SHL32m1 + 13702064U, // SHL32mCL + 974197680U, // SHL32mi + 14701488U, // SHL32r1 + 13652912U, // SHL32rCL + 705713072U, // SHL32ri + 14767024U, // SHL64m1 + 13718448U, // SHL64mCL + 974214064U, // SHL64mi + 14701488U, // SHL64r1 + 13652912U, // SHL64rCL + 705713072U, // SHL64ri + 14783408U, // SHL8m1 + 13734832U, // SHL8mCL + 974230448U, // SHL8mi + 14701488U, // SHL8r1 + 13652912U, // SHL8rCL + 705713072U, // SHL8ri + 2148567108U, // SHLD16mrCL + 2148567108U, // SHLD16mri8 + 2182105156U, // SHLD16rrCL + 2182105156U, // SHLD16rri8 + 2148599876U, // SHLD32mrCL + 2148599876U, // SHLD32mri8 + 2182105156U, // SHLD32rrCL + 2182105156U, // SHLD32rri8 + 2148616260U, // SHLD64mrCL + 2148616260U, // SHLD64mri8 + 2182105156U, // SHLD64rrCL + 2182105156U, // SHLD64rri8 + 2551211779U, // SHLX32rm + 2517657347U, // SHLX32rr + 2584766211U, // SHLX64rm + 2517657347U, // SHLX64rr + 14719648U, // SHR16m1 + 13671072U, // SHR16mCL + 974166688U, // SHR16mi + 14703264U, // SHR16r1 + 13654688U, // SHR16rCL + 705714848U, // SHR16ri + 14752416U, // SHR32m1 + 13703840U, // SHR32mCL + 974199456U, // SHR32mi + 14703264U, // SHR32r1 + 13654688U, // SHR32rCL + 705714848U, // SHR32ri + 14768800U, // SHR64m1 + 13720224U, // SHR64mCL + 974215840U, // SHR64mi + 14703264U, // SHR64r1 + 13654688U, // SHR64rCL + 705714848U, // SHR64ri + 14785184U, // SHR8m1 + 13736608U, // SHR8mCL + 974232224U, // SHR8mi + 14703264U, // SHR8r1 + 13654688U, // SHR8rCL + 705714848U, // SHR8ri + 2148568335U, // SHRD16mrCL + 2148568335U, // SHRD16mri8 + 2182106383U, // SHRD16rrCL + 2182106383U, // SHRD16rri8 + 2148601103U, // SHRD32mrCL + 2148601103U, // SHRD32mri8 + 2182106383U, // SHRD32rrCL + 2182106383U, // SHRD32rri8 + 2148617487U, // SHRD64mrCL + 2148617487U, // SHRD64mri8 + 2182106383U, // SHRD64rrCL + 2182106383U, // SHRD64rri8 + 2551211803U, // SHRX32rm + 2517657371U, // SHRX32rr + 2584766235U, // SHRX64rm + 2517657371U, // SHRX64rr + 2349878137U, // SHUFPDrmi + 2182105977U, // SHUFPDrri + 2349882936U, // SHUFPSrmi + 2182110776U, // SHUFPSrri + 303624U, // SIDT16m + 303624U, // SIDT32m + 303624U, // SIDT64m + 11548U, // SIN_F + 0U, // SIN_Fp32 + 0U, // SIN_Fp64 + 0U, // SIN_Fp80 + 12093U, // SKINIT + 41492U, // SLDT16m + 25108U, // SLDT16r + 25108U, // SLDT32r + 25108U, // SLDT64r + 17376U, // SLWPCB + 17376U, // SLWPCB64 + 42436U, // SMSW16m + 26052U, // SMSW16r + 26052U, // SMSW32r + 26052U, // SMSW64r + 672156804U, // SQRTPDm + 370166916U, // SQRTPDr + 672161630U, // SQRTPSm + 370171742U, // SQRTPSr + 605048684U, // SQRTSDm + 235949932U, // SQRTSDm_Int + 370167660U, // SQRTSDr + 34623340U, // SQRTSDr_Int + 638607776U, // SQRTSSm + 269509024U, // SQRTSSm_Int + 370172320U, // SQRTSSr + 34628000U, // SQRTSSr_Int + 11960U, // SQRT_F + 0U, // SQRT_Fp32 + 0U, // SQRT_Fp64 + 0U, // SQRT_Fp80 + 11137U, // STAC + 11191U, // STC + 11229U, // STD + 11405U, // STGI + 11420U, // STI + 72434U, // STMXCSR + 12928363U, // STOSB + 10850047U, // STOSL + 12081423U, // STOSQ + 9823699U, // STOSW + 23307U, // STR16r + 23307U, // STR32r + 23307U, // STR64r + 39691U, // STRm + 123553U, // ST_F32m + 139937U, // ST_F64m + 120154U, // ST_FP32m + 136538U, // ST_FP64m + 316762U, // ST_FP80m + 21850U, // ST_FPrr + 0U, // ST_Fp32m + 0U, // ST_Fp64m + 0U, // ST_Fp64m32 + 0U, // ST_Fp80m32 + 0U, // ST_Fp80m64 + 0U, // ST_FpP32m + 0U, // ST_FpP64m + 0U, // ST_FpP64m32 + 0U, // ST_FpP80m + 0U, // ST_FpP80m32 + 0U, // ST_FpP80m64 + 25249U, // ST_Frr + 26718U, // SUB16i16 + 1082905U, // SUB16mi + 1082905U, // SUB16mi8 + 1082905U, // SUB16mr + 34653721U, // SUB16ri + 34653721U, // SUB16ri8 + 68208153U, // SUB16rm + 34653721U, // SUB16rr + 34620953U, // SUB16rr_REV + 26843U, // SUB32i32 + 1115673U, // SUB32mi + 1115673U, // SUB32mi8 + 1115673U, // SUB32mr + 34653721U, // SUB32ri + 34653721U, // SUB32ri8 + 101762585U, // SUB32rm + 34653721U, // SUB32rr + 34620953U, // SUB32rr_REV + 26980U, // SUB64i32 + 1132057U, // SUB64mi32 + 1132057U, // SUB64mi8 + 1132057U, // SUB64mr + 34653721U, // SUB64ri32 + 34653721U, // SUB64ri8 + 135317017U, // SUB64rm + 34653721U, // SUB64rr + 34620953U, // SUB64rr_REV + 26616U, // SUB8i8 + 1148441U, // SUB8mi + 1148441U, // SUB8mi8 + 1148441U, // SUB8mr + 34653721U, // SUB8ri + 34653721U, // SUB8ri8 + 168871449U, // SUB8rm + 34653721U, // SUB8rr + 34620953U, // SUB8rr_REV + 202394272U, // SUBPDrm + 34622112U, // SUBPDrr + 202399048U, // SUBPSrm + 34626888U, // SUBPSrr + 121477U, // SUBR_F32m + 137861U, // SUBR_F64m + 39564U, // SUBR_FI16m + 72332U, // SUBR_FI32m + 21818U, // SUBR_FPrST0 + 23173U, // SUBR_FST0r + 0U, // SUBR_Fp32m + 0U, // SUBR_Fp64m + 0U, // SUBR_Fp64m32 + 0U, // SUBR_Fp80m32 + 0U, // SUBR_Fp80m64 + 0U, // SUBR_FpI16m32 + 0U, // SUBR_FpI16m64 + 0U, // SUBR_FpI16m80 + 0U, // SUBR_FpI32m32 + 0U, // SUBR_FpI32m64 + 0U, // SUBR_FpI32m80 + 2120325U, // SUBR_FrST0 + 235949656U, // SUBSDrm + 235949656U, // SUBSDrm_Int + 34623064U, // SUBSDrr + 34623064U, // SUBSDrr_Int + 269508781U, // SUBSSrm + 269508781U, // SUBSSrm_Int + 34627757U, // SUBSSrr + 34627757U, // SUBSSrr_Int + 116248U, // SUB_F32m + 132632U, // SUB_F64m + 34334U, // SUB_FI16m + 67102U, // SUB_FI32m + 21702U, // SUB_FPrST0 + 17944U, // SUB_FST0r + 0U, // SUB_Fp32 + 0U, // SUB_Fp32m + 0U, // SUB_Fp64 + 0U, // SUB_Fp64m + 0U, // SUB_Fp64m32 + 0U, // SUB_Fp80 + 0U, // SUB_Fp80m32 + 0U, // SUB_Fp80m64 + 0U, // SUB_FpI16m32 + 0U, // SUB_FpI16m64 + 0U, // SUB_FpI16m80 + 0U, // SUB_FpI32m32 + 0U, // SUB_FpI32m64 + 0U, // SUB_FpI32m80 + 2115096U, // SUB_FrST0 + 11843U, // SWAPGS + 11482U, // SYSCALL + 11723U, // SYSENTER + 11940U, // SYSEXIT + 11703U, // SYSEXIT64 + 11920U, // SYSRET + 11695U, // SYSRET64 + 403719869U, // T1MSKC32rm + 370165437U, // T1MSKC32rr + 437274301U, // T1MSKC64rm + 370165437U, // T1MSKC64rr + 26792U, // TEST16i16 + 1090203U, // TEST16mi + 1090203U, // TEST16mi_alt + 1090203U, // TEST16mr + 370172571U, // TEST16ri + 370172571U, // TEST16ri_alt + 370172571U, // TEST16rr + 26949U, // TEST32i32 + 1122971U, // TEST32mi + 1122971U, // TEST32mi_alt + 1122971U, // TEST32mr + 370172571U, // TEST32ri + 370172571U, // TEST32ri_alt + 370172571U, // TEST32rr + 27077U, // TEST64i32 + 1139355U, // TEST64mi32 + 1139355U, // TEST64mi32_alt + 1139355U, // TEST64mr + 370172571U, // TEST64ri32 + 370172571U, // TEST64ri32_alt + 370172571U, // TEST64rr + 26690U, // TEST8i8 + 1155739U, // TEST8mi + 1155739U, // TEST8mi_alt + 1155739U, // TEST8mr + 370172571U, // TEST8ri + 370172571U, // TEST8ri_alt + 370172571U, // TEST8rr + 20949U, // TPAUSE + 11972U, // TST_F + 0U, // TST_Fp32 + 0U, // TST_Fp64 + 0U, // TST_Fp80 + 504390207U, // TZCNT16rm + 370172479U, // TZCNT16rr + 403726911U, // TZCNT32rm + 370172479U, // TZCNT32rr + 437281343U, // TZCNT64rm + 370172479U, // TZCNT64rr + 403723152U, // TZMSK32rm + 370168720U, // TZMSK32rr + 437277584U, // TZMSK64rm + 370168720U, // TZMSK64rr + 605048519U, // UCOMISDrm + 605048519U, // UCOMISDrm_Int + 370167495U, // UCOMISDrr + 370167495U, // UCOMISDrr_Int + 638607667U, // UCOMISSrm + 638607667U, // UCOMISSrm_Int + 370172211U, // UCOMISSrr + 370172211U, // UCOMISSrr_Int + 21217U, // UCOM_FIPr + 21159U, // UCOM_FIr + 11630U, // UCOM_FPPr + 21774U, // UCOM_FPr + 0U, // UCOM_FpIr32 + 0U, // UCOM_FpIr64 + 0U, // UCOM_FpIr80 + 0U, // UCOM_Fpr32 + 0U, // UCOM_Fpr64 + 0U, // UCOM_Fpr80 + 21582U, // UCOM_Fr + 10928U, // UD0 + 10943U, // UD1 + 10981U, // UD2 + 23226U, // UMONITOR16 + 23226U, // UMONITOR32 + 23226U, // UMONITOR64 + 25128U, // UMWAIT + 202394498U, // UNPCKHPDrm + 34622338U, // UNPCKHPDrr + 202399297U, // UNPCKHPSrm + 34627137U, // UNPCKHPSrr + 202394540U, // UNPCKLPDrm + 34622380U, // UNPCKLPDrr + 202399359U, // UNPCKLPSrm + 34627199U, // UNPCKLPSrr + 2182110614U, // V4FMADDPSrm + 49307030U, // V4FMADDPSrmk + 2196790678U, // V4FMADDPSrmkz + 2182111431U, // V4FMADDSSrm + 49307847U, // V4FMADDSSrmk + 2196791495U, // V4FMADDSSrmkz + 2182110635U, // V4FNMADDPSrm + 49307051U, // V4FNMADDPSrmk + 2196790699U, // V4FNMADDPSrmkz + 2182111452U, // V4FNMADDSSrm + 49307868U, // V4FNMADDSSrmk + 2196791516U, // V4FNMADDSSrmkz + 2517650179U, // VADDPDYrm + 2517650179U, // VADDPDYrr + 2517650179U, // VADDPDZ128rm + 2517650179U, // VADDPDZ128rmb + 49302275U, // VADDPDZ128rmbk + 2532330243U, // VADDPDZ128rmbkz + 49302275U, // VADDPDZ128rmk + 2532330243U, // VADDPDZ128rmkz + 2517650179U, // VADDPDZ128rr + 49302275U, // VADDPDZ128rrk + 2532330243U, // VADDPDZ128rrkz + 2517650179U, // VADDPDZ256rm + 2517650179U, // VADDPDZ256rmb + 49302275U, // VADDPDZ256rmbk + 2532330243U, // VADDPDZ256rmbkz + 49302275U, // VADDPDZ256rmk + 2532330243U, // VADDPDZ256rmkz + 2517650179U, // VADDPDZ256rr + 49302275U, // VADDPDZ256rrk + 2532330243U, // VADDPDZ256rrkz + 2517650179U, // VADDPDZrm + 2517650179U, // VADDPDZrmb + 49302275U, // VADDPDZrmbk + 2532330243U, // VADDPDZrmbkz + 49302275U, // VADDPDZrmk + 2532330243U, // VADDPDZrmkz + 2517650179U, // VADDPDZrr + 2517650179U, // VADDPDZrrb + 49302275U, // VADDPDZrrbk + 2532330243U, // VADDPDZrrbkz + 49302275U, // VADDPDZrrk + 2532330243U, // VADDPDZrrkz + 2517650179U, // VADDPDrm + 2517650179U, // VADDPDrr + 2517654978U, // VADDPSYrm + 2517654978U, // VADDPSYrr + 2517654978U, // VADDPSZ128rm + 2517654978U, // VADDPSZ128rmb + 49307074U, // VADDPSZ128rmbk + 2532335042U, // VADDPSZ128rmbkz + 49307074U, // VADDPSZ128rmk + 2532335042U, // VADDPSZ128rmkz + 2517654978U, // VADDPSZ128rr + 49307074U, // VADDPSZ128rrk + 2532335042U, // VADDPSZ128rrkz + 2517654978U, // VADDPSZ256rm + 2517654978U, // VADDPSZ256rmb + 49307074U, // VADDPSZ256rmbk + 2532335042U, // VADDPSZ256rmbkz + 49307074U, // VADDPSZ256rmk + 2532335042U, // VADDPSZ256rmkz + 2517654978U, // VADDPSZ256rr + 49307074U, // VADDPSZ256rrk + 2532335042U, // VADDPSZ256rrkz + 2517654978U, // VADDPSZrm + 2517654978U, // VADDPSZrmb + 49307074U, // VADDPSZrmbk + 2532335042U, // VADDPSZrmbkz + 49307074U, // VADDPSZrmk + 2532335042U, // VADDPSZrmkz + 2517654978U, // VADDPSZrr + 2517654978U, // VADDPSZrrb + 49307074U, // VADDPSZrrbk + 2532335042U, // VADDPSZrrbkz + 49307074U, // VADDPSZrrk + 2532335042U, // VADDPSZrrkz + 2517654978U, // VADDPSrm + 2517654978U, // VADDPSrr + 2517651079U, // VADDSDZrm + 2517651079U, // VADDSDZrm_Int + 49303175U, // VADDSDZrm_Intk + 2532331143U, // VADDSDZrm_Intkz + 2517651079U, // VADDSDZrr + 2517651079U, // VADDSDZrr_Int + 49303175U, // VADDSDZrr_Intk + 2532331143U, // VADDSDZrr_Intkz + 2517651079U, // VADDSDZrrb_Int + 49303175U, // VADDSDZrrb_Intk + 2532331143U, // VADDSDZrrb_Intkz + 2517651079U, // VADDSDrm + 2517651079U, // VADDSDrm_Int + 2517651079U, // VADDSDrr + 2517651079U, // VADDSDrr_Int + 2517655795U, // VADDSSZrm + 2517655795U, // VADDSSZrm_Int + 49307891U, // VADDSSZrm_Intk + 2532335859U, // VADDSSZrm_Intkz + 2517655795U, // VADDSSZrr + 2517655795U, // VADDSSZrr_Int + 49307891U, // VADDSSZrr_Intk + 2532335859U, // VADDSSZrr_Intkz + 2517655795U, // VADDSSZrrb_Int + 49307891U, // VADDSSZrrb_Intk + 2532335859U, // VADDSSZrrb_Intkz + 2517655795U, // VADDSSrm + 2517655795U, // VADDSSrm_Int + 2517655795U, // VADDSSrr + 2517655795U, // VADDSSrr_Int + 2517650087U, // VADDSUBPDYrm + 2517650087U, // VADDSUBPDYrr + 2517650087U, // VADDSUBPDrm + 2517650087U, // VADDSUBPDrr + 2517654863U, // VADDSUBPSYrm + 2517654863U, // VADDSUBPSYrr + 2517654863U, // VADDSUBPSrm + 2517654863U, // VADDSUBPSrr + 2517656191U, // VAESDECLASTYrm + 2517656191U, // VAESDECLASTYrr + 2517656191U, // VAESDECLASTZ128rm + 2517656191U, // VAESDECLASTZ128rr + 2517656191U, // VAESDECLASTZ256rm + 2517656191U, // VAESDECLASTZ256rr + 2517656191U, // VAESDECLASTZrm + 2517656191U, // VAESDECLASTZrr + 2517656191U, // VAESDECLASTrm + 2517656191U, // VAESDECLASTrr + 2517649054U, // VAESDECYrm + 2517649054U, // VAESDECYrr + 2517649054U, // VAESDECZ128rm + 2517649054U, // VAESDECZ128rr + 2517649054U, // VAESDECZ256rm + 2517649054U, // VAESDECZ256rr + 2517649054U, // VAESDECZrm + 2517649054U, // VAESDECZrr + 2517649054U, // VAESDECrm + 2517649054U, // VAESDECrr + 2517656204U, // VAESENCLASTYrm + 2517656204U, // VAESENCLASTYrr + 2517656204U, // VAESENCLASTZ128rm + 2517656204U, // VAESENCLASTZ128rr + 2517656204U, // VAESENCLASTZ256rm + 2517656204U, // VAESENCLASTZ256rr + 2517656204U, // VAESENCLASTZrm + 2517656204U, // VAESENCLASTZrr + 2517656204U, // VAESENCLASTrm + 2517656204U, // VAESENCLASTrr + 2517649102U, // VAESENCYrm + 2517649102U, // VAESENCYrr + 2517649102U, // VAESENCZ128rm + 2517649102U, // VAESENCZ128rr + 2517649102U, // VAESENCZ256rm + 2517649102U, // VAESENCZ256rr + 2517649102U, // VAESENCZrm + 2517649102U, // VAESENCZrr + 2517649102U, // VAESENCrm + 2517649102U, // VAESENCrr + 336611013U, // VAESIMCrm + 370165445U, // VAESIMCrr + 2484101804U, // VAESKEYGENASSIST128rm + 2517656236U, // VAESKEYGENASSIST128rr + 2517649620U, // VALIGNDZ128rmbi + 49301716U, // VALIGNDZ128rmbik + 2532329684U, // VALIGNDZ128rmbikz + 2517649620U, // VALIGNDZ128rmi + 49301716U, // VALIGNDZ128rmik + 2532329684U, // VALIGNDZ128rmikz + 2517649620U, // VALIGNDZ128rri + 49301716U, // VALIGNDZ128rrik + 2532329684U, // VALIGNDZ128rrikz + 2517649620U, // VALIGNDZ256rmbi + 49301716U, // VALIGNDZ256rmbik + 2532329684U, // VALIGNDZ256rmbikz + 2517649620U, // VALIGNDZ256rmi + 49301716U, // VALIGNDZ256rmik + 2532329684U, // VALIGNDZ256rmikz + 2517649620U, // VALIGNDZ256rri + 49301716U, // VALIGNDZ256rrik + 2532329684U, // VALIGNDZ256rrikz + 2517649620U, // VALIGNDZrmbi + 49301716U, // VALIGNDZrmbik + 2532329684U, // VALIGNDZrmbikz + 2517649620U, // VALIGNDZrmi + 49301716U, // VALIGNDZrmik + 2532329684U, // VALIGNDZrmikz + 2517649620U, // VALIGNDZrri + 49301716U, // VALIGNDZrrik + 2532329684U, // VALIGNDZrrikz + 2517653521U, // VALIGNQZ128rmbi + 49305617U, // VALIGNQZ128rmbik + 2532333585U, // VALIGNQZ128rmbikz + 2517653521U, // VALIGNQZ128rmi + 49305617U, // VALIGNQZ128rmik + 2532333585U, // VALIGNQZ128rmikz + 2517653521U, // VALIGNQZ128rri + 49305617U, // VALIGNQZ128rrik + 2532333585U, // VALIGNQZ128rrikz + 2517653521U, // VALIGNQZ256rmbi + 49305617U, // VALIGNQZ256rmbik + 2532333585U, // VALIGNQZ256rmbikz + 2517653521U, // VALIGNQZ256rmi + 49305617U, // VALIGNQZ256rmik + 2532333585U, // VALIGNQZ256rmikz + 2517653521U, // VALIGNQZ256rri + 49305617U, // VALIGNQZ256rrik + 2532333585U, // VALIGNQZ256rrikz + 2517653521U, // VALIGNQZrmbi + 49305617U, // VALIGNQZrmbik + 2532333585U, // VALIGNQZrmbikz + 2517653521U, // VALIGNQZrmi + 49305617U, // VALIGNQZrmik + 2532333585U, // VALIGNQZrmikz + 2517653521U, // VALIGNQZrri + 49305617U, // VALIGNQZrrik + 2532333585U, // VALIGNQZrrikz + 2517650416U, // VANDNPDYrm + 2517650416U, // VANDNPDYrr + 2517650416U, // VANDNPDZ128rm + 2517650416U, // VANDNPDZ128rmb + 49302512U, // VANDNPDZ128rmbk + 2532330480U, // VANDNPDZ128rmbkz + 49302512U, // VANDNPDZ128rmk + 2532330480U, // VANDNPDZ128rmkz + 2517650416U, // VANDNPDZ128rr + 49302512U, // VANDNPDZ128rrk + 2532330480U, // VANDNPDZ128rrkz + 2517650416U, // VANDNPDZ256rm + 2517650416U, // VANDNPDZ256rmb + 49302512U, // VANDNPDZ256rmbk + 2532330480U, // VANDNPDZ256rmbkz + 49302512U, // VANDNPDZ256rmk + 2532330480U, // VANDNPDZ256rmkz + 2517650416U, // VANDNPDZ256rr + 49302512U, // VANDNPDZ256rrk + 2532330480U, // VANDNPDZ256rrkz + 2517650416U, // VANDNPDZrm + 2517650416U, // VANDNPDZrmb + 49302512U, // VANDNPDZrmbk + 2532330480U, // VANDNPDZrmbkz + 49302512U, // VANDNPDZrmk + 2532330480U, // VANDNPDZrmkz + 2517650416U, // VANDNPDZrr + 49302512U, // VANDNPDZrrk + 2532330480U, // VANDNPDZrrkz + 2517650416U, // VANDNPDrm + 2517650416U, // VANDNPDrr + 2517655227U, // VANDNPSYrm + 2517655227U, // VANDNPSYrr + 2517655227U, // VANDNPSZ128rm + 2517655227U, // VANDNPSZ128rmb + 49307323U, // VANDNPSZ128rmbk + 2532335291U, // VANDNPSZ128rmbkz + 49307323U, // VANDNPSZ128rmk + 2532335291U, // VANDNPSZ128rmkz + 2517655227U, // VANDNPSZ128rr + 49307323U, // VANDNPSZ128rrk + 2532335291U, // VANDNPSZ128rrkz + 2517655227U, // VANDNPSZ256rm + 2517655227U, // VANDNPSZ256rmb + 49307323U, // VANDNPSZ256rmbk + 2532335291U, // VANDNPSZ256rmbkz + 49307323U, // VANDNPSZ256rmk + 2532335291U, // VANDNPSZ256rmkz + 2517655227U, // VANDNPSZ256rr + 49307323U, // VANDNPSZ256rrk + 2532335291U, // VANDNPSZ256rrkz + 2517655227U, // VANDNPSZrm + 2517655227U, // VANDNPSZrmb + 49307323U, // VANDNPSZrmbk + 2532335291U, // VANDNPSZrmbkz + 49307323U, // VANDNPSZrmk + 2532335291U, // VANDNPSZrmkz + 2517655227U, // VANDNPSZrr + 49307323U, // VANDNPSZrrk + 2532335291U, // VANDNPSZrrkz + 2517655227U, // VANDNPSrm + 2517655227U, // VANDNPSrr + 2517650198U, // VANDPDYrm + 2517650198U, // VANDPDYrr + 2517650198U, // VANDPDZ128rm + 2517650198U, // VANDPDZ128rmb + 49302294U, // VANDPDZ128rmbk + 2532330262U, // VANDPDZ128rmbkz + 49302294U, // VANDPDZ128rmk + 2532330262U, // VANDPDZ128rmkz + 2517650198U, // VANDPDZ128rr + 49302294U, // VANDPDZ128rrk + 2532330262U, // VANDPDZ128rrkz + 2517650198U, // VANDPDZ256rm + 2517650198U, // VANDPDZ256rmb + 49302294U, // VANDPDZ256rmbk + 2532330262U, // VANDPDZ256rmbkz + 49302294U, // VANDPDZ256rmk + 2532330262U, // VANDPDZ256rmkz + 2517650198U, // VANDPDZ256rr + 49302294U, // VANDPDZ256rrk + 2532330262U, // VANDPDZ256rrkz + 2517650198U, // VANDPDZrm + 2517650198U, // VANDPDZrmb + 49302294U, // VANDPDZrmbk + 2532330262U, // VANDPDZrmbkz + 49302294U, // VANDPDZrmk + 2532330262U, // VANDPDZrmkz + 2517650198U, // VANDPDZrr + 49302294U, // VANDPDZrrk + 2532330262U, // VANDPDZrrkz + 2517650198U, // VANDPDrm + 2517650198U, // VANDPDrr + 2517654997U, // VANDPSYrm + 2517654997U, // VANDPSYrr + 2517654997U, // VANDPSZ128rm + 2517654997U, // VANDPSZ128rmb + 49307093U, // VANDPSZ128rmbk + 2532335061U, // VANDPSZ128rmbkz + 49307093U, // VANDPSZ128rmk + 2532335061U, // VANDPSZ128rmkz + 2517654997U, // VANDPSZ128rr + 49307093U, // VANDPSZ128rrk + 2532335061U, // VANDPSZ128rrkz + 2517654997U, // VANDPSZ256rm + 2517654997U, // VANDPSZ256rmb + 49307093U, // VANDPSZ256rmbk + 2532335061U, // VANDPSZ256rmbkz + 49307093U, // VANDPSZ256rmk + 2532335061U, // VANDPSZ256rmkz + 2517654997U, // VANDPSZ256rr + 49307093U, // VANDPSZ256rrk + 2532335061U, // VANDPSZ256rrkz + 2517654997U, // VANDPSZrm + 2517654997U, // VANDPSZrmb + 49307093U, // VANDPSZrmbk + 2532335061U, // VANDPSZrmbkz + 49307093U, // VANDPSZrmk + 2532335061U, // VANDPSZrmkz + 2517654997U, // VANDPSZrr + 49307093U, // VANDPSZrrk + 2532335061U, // VANDPSZrrkz + 2517654997U, // VANDPSrm + 2517654997U, // VANDPSrr + 2517650383U, // VBLENDMPDZ128rm + 2517650383U, // VBLENDMPDZ128rmb + 384846799U, // VBLENDMPDZ128rmbk + 2532330447U, // VBLENDMPDZ128rmbkz + 384846799U, // VBLENDMPDZ128rmk + 2532330447U, // VBLENDMPDZ128rmkz + 2517650383U, // VBLENDMPDZ128rr + 384846799U, // VBLENDMPDZ128rrk + 2532330447U, // VBLENDMPDZ128rrkz + 2517650383U, // VBLENDMPDZ256rm + 2517650383U, // VBLENDMPDZ256rmb + 384846799U, // VBLENDMPDZ256rmbk + 2532330447U, // VBLENDMPDZ256rmbkz + 384846799U, // VBLENDMPDZ256rmk + 2532330447U, // VBLENDMPDZ256rmkz + 2517650383U, // VBLENDMPDZ256rr + 384846799U, // VBLENDMPDZ256rrk + 2532330447U, // VBLENDMPDZ256rrkz + 2517650383U, // VBLENDMPDZrm + 2517650383U, // VBLENDMPDZrmb + 384846799U, // VBLENDMPDZrmbk + 2532330447U, // VBLENDMPDZrmbkz + 384846799U, // VBLENDMPDZrmk + 2532330447U, // VBLENDMPDZrmkz + 2517650383U, // VBLENDMPDZrr + 384846799U, // VBLENDMPDZrrk + 2532330447U, // VBLENDMPDZrrkz + 2517655194U, // VBLENDMPSZ128rm + 2517655194U, // VBLENDMPSZ128rmb + 384851610U, // VBLENDMPSZ128rmbk + 2532335258U, // VBLENDMPSZ128rmbkz + 384851610U, // VBLENDMPSZ128rmk + 2532335258U, // VBLENDMPSZ128rmkz + 2517655194U, // VBLENDMPSZ128rr + 384851610U, // VBLENDMPSZ128rrk + 2532335258U, // VBLENDMPSZ128rrkz + 2517655194U, // VBLENDMPSZ256rm + 2517655194U, // VBLENDMPSZ256rmb + 384851610U, // VBLENDMPSZ256rmbk + 2532335258U, // VBLENDMPSZ256rmbkz + 384851610U, // VBLENDMPSZ256rmk + 2532335258U, // VBLENDMPSZ256rmkz + 2517655194U, // VBLENDMPSZ256rr + 384851610U, // VBLENDMPSZ256rrk + 2532335258U, // VBLENDMPSZ256rrkz + 2517655194U, // VBLENDMPSZrm + 2517655194U, // VBLENDMPSZrmb + 384851610U, // VBLENDMPSZrmbk + 2532335258U, // VBLENDMPSZrmbkz + 384851610U, // VBLENDMPSZrmk + 2532335258U, // VBLENDMPSZrmkz + 2517655194U, // VBLENDMPSZrr + 384851610U, // VBLENDMPSZrrk + 2532335258U, // VBLENDMPSZrrkz + 2517650206U, // VBLENDPDYrmi + 2517650206U, // VBLENDPDYrri + 2517650206U, // VBLENDPDrmi + 2517650206U, // VBLENDPDrri + 2517655005U, // VBLENDPSYrmi + 2517655005U, // VBLENDPSYrri + 2517655005U, // VBLENDPSrmi + 2517655005U, // VBLENDPSrri + 2517650590U, // VBLENDVPDYrm + 2517650590U, // VBLENDVPDYrr + 2517650590U, // VBLENDVPDrm + 2517650590U, // VBLENDVPDrr + 2517655425U, // VBLENDVPSYrm + 2517655425U, // VBLENDVPSYrr + 2517655425U, // VBLENDVPSrm + 2517655425U, // VBLENDVPSrr + 672154271U, // VBROADCASTF128 + 605044902U, // VBROADCASTF32X2Z256m + 49299622U, // VBROADCASTF32X2Z256mk + 2532327590U, // VBROADCASTF32X2Z256mkz + 370163878U, // VBROADCASTF32X2Z256r + 49299622U, // VBROADCASTF32X2Z256rk + 2532327590U, // VBROADCASTF32X2Z256rkz + 605044902U, // VBROADCASTF32X2Zm + 49299622U, // VBROADCASTF32X2Zmk + 2532327590U, // VBROADCASTF32X2Zmkz + 370163878U, // VBROADCASTF32X2Zr + 49299622U, // VBROADCASTF32X2Zrk + 2532327590U, // VBROADCASTF32X2Zrkz + 672154054U, // VBROADCASTF32X4Z256rm + 49299910U, // VBROADCASTF32X4Z256rmk + 2532327878U, // VBROADCASTF32X4Z256rmkz + 672154054U, // VBROADCASTF32X4rm + 49299910U, // VBROADCASTF32X4rmk + 2532327878U, // VBROADCASTF32X4rmkz + 1007698701U, // VBROADCASTF32X8rm + 49300237U, // VBROADCASTF32X8rmk + 2532328205U, // VBROADCASTF32X8rmkz + 672153841U, // VBROADCASTF64X2Z128rm + 49299697U, // VBROADCASTF64X2Z128rmk + 2532327665U, // VBROADCASTF64X2Z128rmkz + 672153841U, // VBROADCASTF64X2rm + 49299697U, // VBROADCASTF64X2rmk + 2532327665U, // VBROADCASTF64X2rmkz + 1007698478U, // VBROADCASTF64X4rm + 49300014U, // VBROADCASTF64X4rmk + 2532327982U, // VBROADCASTF64X4rmkz + 336610006U, // VBROADCASTI128 + 437272759U, // VBROADCASTI32X2Z128m + 49299639U, // VBROADCASTI32X2Z128mk + 2532327607U, // VBROADCASTI32X2Z128mkz + 370163895U, // VBROADCASTI32X2Z128r + 49299639U, // VBROADCASTI32X2Z128rk + 2532327607U, // VBROADCASTI32X2Z128rkz + 437272759U, // VBROADCASTI32X2Z256m + 49299639U, // VBROADCASTI32X2Z256mk + 2532327607U, // VBROADCASTI32X2Z256mkz + 370163895U, // VBROADCASTI32X2Z256r + 49299639U, // VBROADCASTI32X2Z256rk + 2532327607U, // VBROADCASTI32X2Z256rkz + 437272759U, // VBROADCASTI32X2Zm + 49299639U, // VBROADCASTI32X2Zmk + 2532327607U, // VBROADCASTI32X2Zmkz + 370163895U, // VBROADCASTI32X2Zr + 49299639U, // VBROADCASTI32X2Zrk + 2532327607U, // VBROADCASTI32X2Zrkz + 336609792U, // VBROADCASTI32X4Z256rm + 49299968U, // VBROADCASTI32X4Z256rmk + 2532327936U, // VBROADCASTI32X4Z256rmkz + 336609792U, // VBROADCASTI32X4rm + 49299968U, // VBROADCASTI32X4rmk + 2532327936U, // VBROADCASTI32X4rmkz + 1041253179U, // VBROADCASTI32X8rm + 49300283U, // VBROADCASTI32X8rmk + 2532328251U, // VBROADCASTI32X8rmkz + 336609579U, // VBROADCASTI64X2Z128rm + 49299755U, // VBROADCASTI64X2Z128rmk + 2532327723U, // VBROADCASTI64X2Z128rmkz + 336609579U, // VBROADCASTI64X2rm + 49299755U, // VBROADCASTI64X2rmk + 2532327723U, // VBROADCASTI64X2rmkz + 1041252956U, // VBROADCASTI64X4rm + 49300060U, // VBROADCASTI64X4rmk + 2532328028U, // VBROADCASTI64X4rmkz + 605048692U, // VBROADCASTSDYrm + 370167668U, // VBROADCASTSDYrr + 605048692U, // VBROADCASTSDZ256m + 49303412U, // VBROADCASTSDZ256mk + 2532331380U, // VBROADCASTSDZ256mkz + 370167668U, // VBROADCASTSDZ256r + 49303412U, // VBROADCASTSDZ256rk + 2532331380U, // VBROADCASTSDZ256rkz + 605048692U, // VBROADCASTSDZm + 49303412U, // VBROADCASTSDZmk + 2532331380U, // VBROADCASTSDZmkz + 370167668U, // VBROADCASTSDZr + 49303412U, // VBROADCASTSDZrk + 2532331380U, // VBROADCASTSDZrkz + 638607793U, // VBROADCASTSSYrm + 370172337U, // VBROADCASTSSYrr + 638607793U, // VBROADCASTSSZ128m + 49308081U, // VBROADCASTSSZ128mk + 2532336049U, // VBROADCASTSSZ128mkz + 370172337U, // VBROADCASTSSZ128r + 49308081U, // VBROADCASTSSZ128rk + 2532336049U, // VBROADCASTSSZ128rkz + 638607793U, // VBROADCASTSSZ256m + 49308081U, // VBROADCASTSSZ256mk + 2532336049U, // VBROADCASTSSZ256mkz + 370172337U, // VBROADCASTSSZ256r + 49308081U, // VBROADCASTSSZ256rk + 2532336049U, // VBROADCASTSSZ256rkz + 638607793U, // VBROADCASTSSZm + 49308081U, // VBROADCASTSSZmk + 2532336049U, // VBROADCASTSSZmkz + 370172337U, // VBROADCASTSSZr + 49308081U, // VBROADCASTSSZrk + 2532336049U, // VBROADCASTSSZrkz + 638607793U, // VBROADCASTSSrm + 370172337U, // VBROADCASTSSrr + 573779266U, // VCMPPDYrmi + 2517650440U, // VCMPPDYrmi_alt + 573795650U, // VCMPPDYrri + 2517650440U, // VCMPPDYrri_alt + 573779266U, // VCMPPDZ128rmbi + 2517650440U, // VCMPPDZ128rmbi_alt + 384846856U, // VCMPPDZ128rmbi_altk + 3224939842U, // VCMPPDZ128rmbik + 573779266U, // VCMPPDZ128rmi + 2517650440U, // VCMPPDZ128rmi_alt + 384846856U, // VCMPPDZ128rmi_altk + 1077456194U, // VCMPPDZ128rmik + 573795650U, // VCMPPDZ128rri + 2517650440U, // VCMPPDZ128rri_alt + 384846856U, // VCMPPDZ128rri_altk + 3224956226U, // VCMPPDZ128rrik + 573779266U, // VCMPPDZ256rmbi + 2517650440U, // VCMPPDZ256rmbi_alt + 384846856U, // VCMPPDZ256rmbi_altk + 3224939842U, // VCMPPDZ256rmbik + 573779266U, // VCMPPDZ256rmi + 2517650440U, // VCMPPDZ256rmi_alt + 384846856U, // VCMPPDZ256rmi_altk + 1077456194U, // VCMPPDZ256rmik + 573795650U, // VCMPPDZ256rri + 2517650440U, // VCMPPDZ256rri_alt + 384846856U, // VCMPPDZ256rri_altk + 3224956226U, // VCMPPDZ256rrik + 573779266U, // VCMPPDZrmbi + 2517650440U, // VCMPPDZrmbi_alt + 384846856U, // VCMPPDZrmbi_altk + 3224939842U, // VCMPPDZrmbik + 573779266U, // VCMPPDZrmi + 2517650440U, // VCMPPDZrmi_alt + 384846856U, // VCMPPDZrmi_altk + 3224939842U, // VCMPPDZrmik + 573795650U, // VCMPPDZrri + 2517650440U, // VCMPPDZrri_alt + 384846856U, // VCMPPDZrri_altk + 573795650U, // VCMPPDZrrib + 2517650440U, // VCMPPDZrrib_alt + 384846856U, // VCMPPDZrrib_altk + 3224956226U, // VCMPPDZrribk + 3224956226U, // VCMPPDZrrik + 573779266U, // VCMPPDrmi + 2517650440U, // VCMPPDrmi_alt + 573795650U, // VCMPPDrri + 2517650440U, // VCMPPDrri_alt + 574827842U, // VCMPPSYrmi + 2517655259U, // VCMPPSYrmi_alt + 574844226U, // VCMPPSYrri + 2517655259U, // VCMPPSYrri_alt + 574827842U, // VCMPPSZ128rmbi + 2517655259U, // VCMPPSZ128rmbi_alt + 384851675U, // VCMPPSZ128rmbi_altk + 1078504770U, // VCMPPSZ128rmbik + 574827842U, // VCMPPSZ128rmi + 2517655259U, // VCMPPSZ128rmi_alt + 384851675U, // VCMPPSZ128rmi_altk + 1078504770U, // VCMPPSZ128rmik + 574844226U, // VCMPPSZ128rri + 2517655259U, // VCMPPSZ128rri_alt + 384851675U, // VCMPPSZ128rri_altk + 3226004802U, // VCMPPSZ128rrik + 574827842U, // VCMPPSZ256rmbi + 2517655259U, // VCMPPSZ256rmbi_alt + 384851675U, // VCMPPSZ256rmbi_altk + 1078504770U, // VCMPPSZ256rmbik + 574827842U, // VCMPPSZ256rmi + 2517655259U, // VCMPPSZ256rmi_alt + 384851675U, // VCMPPSZ256rmi_altk + 1078504770U, // VCMPPSZ256rmik + 574844226U, // VCMPPSZ256rri + 2517655259U, // VCMPPSZ256rri_alt + 384851675U, // VCMPPSZ256rri_altk + 3226004802U, // VCMPPSZ256rrik + 574827842U, // VCMPPSZrmbi + 2517655259U, // VCMPPSZrmbi_alt + 384851675U, // VCMPPSZrmbi_altk + 1078504770U, // VCMPPSZrmbik + 574827842U, // VCMPPSZrmi + 2517655259U, // VCMPPSZrmi_alt + 384851675U, // VCMPPSZrmi_altk + 3225988418U, // VCMPPSZrmik + 574844226U, // VCMPPSZrri + 2517655259U, // VCMPPSZrri_alt + 384851675U, // VCMPPSZrri_altk + 574844226U, // VCMPPSZrrib + 2517655259U, // VCMPPSZrrib_alt + 384851675U, // VCMPPSZrrib_altk + 3226004802U, // VCMPPSZrribk + 3226004802U, // VCMPPSZrrik + 574827842U, // VCMPPSrmi + 2517655259U, // VCMPPSrmi_alt + 574844226U, // VCMPPSrri + 2517655259U, // VCMPPSrri_alt + 575876418U, // VCMPSDZrm + 575876418U, // VCMPSDZrm_Int + 3227036994U, // VCMPSDZrm_Intk + 2517651206U, // VCMPSDZrmi_alt + 384847622U, // VCMPSDZrmi_altk + 575892802U, // VCMPSDZrr + 575892802U, // VCMPSDZrr_Int + 3227053378U, // VCMPSDZrr_Intk + 575892802U, // VCMPSDZrrb_Int + 3227053378U, // VCMPSDZrrb_Intk + 2517651206U, // VCMPSDZrrb_alt + 384847622U, // VCMPSDZrrb_altk + 2517651206U, // VCMPSDZrri_alt + 384847622U, // VCMPSDZrri_altk + 575876418U, // VCMPSDrm + 575876418U, // VCMPSDrm_Int + 2517651206U, // VCMPSDrm_alt + 575892802U, // VCMPSDrr + 575892802U, // VCMPSDrr_Int + 2517651206U, // VCMPSDrr_alt + 576924994U, // VCMPSSZrm + 576924994U, // VCMPSSZrm_Int + 1080601922U, // VCMPSSZrm_Intk + 2517655914U, // VCMPSSZrmi_alt + 384852330U, // VCMPSSZrmi_altk + 576941378U, // VCMPSSZrr + 576941378U, // VCMPSSZrr_Int + 3228101954U, // VCMPSSZrr_Intk + 576941378U, // VCMPSSZrrb_Int + 3228101954U, // VCMPSSZrrb_Intk + 2517655914U, // VCMPSSZrrb_alt + 384852330U, // VCMPSSZrrb_altk + 2517655914U, // VCMPSSZrri_alt + 384852330U, // VCMPSSZrri_altk + 576924994U, // VCMPSSrm + 576924994U, // VCMPSSrm_Int + 2517655914U, // VCMPSSrm_alt + 576941378U, // VCMPSSrr + 576941378U, // VCMPSSrr_Int + 2517655914U, // VCMPSSrr_alt + 605048528U, // VCOMISDZrm + 605048528U, // VCOMISDZrm_Int + 370167504U, // VCOMISDZrr + 370167504U, // VCOMISDZrr_Int + 2517651152U, // VCOMISDZrrb + 605048528U, // VCOMISDrm + 605048528U, // VCOMISDrm_Int + 370167504U, // VCOMISDrr + 370167504U, // VCOMISDrr_Int + 638607676U, // VCOMISSZrm + 638607676U, // VCOMISSZrm_Int + 370172220U, // VCOMISSZrr + 370172220U, // VCOMISSZrr_Int + 2517655868U, // VCOMISSZrrb + 638607676U, // VCOMISSrm + 638607676U, // VCOMISSrm_Int + 370172220U, // VCOMISSrr + 370172220U, // VCOMISSrr_Int + 1576032U, // VCOMPRESSPDZ128mr + 16256096U, // VCOMPRESSPDZ128mrk + 370166880U, // VCOMPRESSPDZ128rr + 49302624U, // VCOMPRESSPDZ128rrk + 2532330592U, // VCOMPRESSPDZ128rrkz + 1641568U, // VCOMPRESSPDZ256mr + 16321632U, // VCOMPRESSPDZ256mrk + 370166880U, // VCOMPRESSPDZ256rr + 49302624U, // VCOMPRESSPDZ256rrk + 2532330592U, // VCOMPRESSPDZ256rrkz + 1657952U, // VCOMPRESSPDZmr + 16338016U, // VCOMPRESSPDZmrk + 370166880U, // VCOMPRESSPDZrr + 49302624U, // VCOMPRESSPDZrrk + 2532330592U, // VCOMPRESSPDZrrkz + 1580834U, // VCOMPRESSPSZ128mr + 16260898U, // VCOMPRESSPSZ128mrk + 370171682U, // VCOMPRESSPSZ128rr + 49307426U, // VCOMPRESSPSZ128rrk + 2532335394U, // VCOMPRESSPSZ128rrkz + 1646370U, // VCOMPRESSPSZ256mr + 16326434U, // VCOMPRESSPSZ256mrk + 370171682U, // VCOMPRESSPSZ256rr + 49307426U, // VCOMPRESSPSZ256rrk + 2532335394U, // VCOMPRESSPSZ256rrkz + 1662754U, // VCOMPRESSPSZmr + 16342818U, // VCOMPRESSPSZmrk + 370171682U, // VCOMPRESSPSZrr + 49307426U, // VCOMPRESSPSZrrk + 2532335394U, // VCOMPRESSPSZrrkz + 336611779U, // VCVTDQ2PDYrm + 370166211U, // VCVTDQ2PDYrr + 437275075U, // VCVTDQ2PDZ128rm + 403720643U, // VCVTDQ2PDZ128rmb + 49301955U, // VCVTDQ2PDZ128rmbk + 2532329923U, // VCVTDQ2PDZ128rmbkz + 49301955U, // VCVTDQ2PDZ128rmk + 2532329923U, // VCVTDQ2PDZ128rmkz + 370166211U, // VCVTDQ2PDZ128rr + 49301955U, // VCVTDQ2PDZ128rrk + 2532329923U, // VCVTDQ2PDZ128rrkz + 336611779U, // VCVTDQ2PDZ256rm + 2551204291U, // VCVTDQ2PDZ256rmb + 49301955U, // VCVTDQ2PDZ256rmbk + 2532329923U, // VCVTDQ2PDZ256rmbkz + 49301955U, // VCVTDQ2PDZ256rmk + 2532329923U, // VCVTDQ2PDZ256rmkz + 370166211U, // VCVTDQ2PDZ256rr + 49301955U, // VCVTDQ2PDZ256rrk + 2532329923U, // VCVTDQ2PDZ256rrkz + 1041254851U, // VCVTDQ2PDZrm + 403720643U, // VCVTDQ2PDZrmb + 49301955U, // VCVTDQ2PDZrmbk + 2532329923U, // VCVTDQ2PDZrmbkz + 49301955U, // VCVTDQ2PDZrmk + 2532329923U, // VCVTDQ2PDZrmkz + 370166211U, // VCVTDQ2PDZrr + 49301955U, // VCVTDQ2PDZrrk + 2532329923U, // VCVTDQ2PDZrrkz + 437275075U, // VCVTDQ2PDrm + 370166211U, // VCVTDQ2PDrr + 1041259646U, // VCVTDQ2PSYrm + 370171006U, // VCVTDQ2PSYrr + 336616574U, // VCVTDQ2PSZ128rm + 2551209086U, // VCVTDQ2PSZ128rmb + 49306750U, // VCVTDQ2PSZ128rmbk + 2532334718U, // VCVTDQ2PSZ128rmbkz + 49306750U, // VCVTDQ2PSZ128rmk + 2532334718U, // VCVTDQ2PSZ128rmkz + 370171006U, // VCVTDQ2PSZ128rr + 49306750U, // VCVTDQ2PSZ128rrk + 2532334718U, // VCVTDQ2PSZ128rrkz + 1041259646U, // VCVTDQ2PSZ256rm + 403725438U, // VCVTDQ2PSZ256rmb + 49306750U, // VCVTDQ2PSZ256rmbk + 2532334718U, // VCVTDQ2PSZ256rmbkz + 49306750U, // VCVTDQ2PSZ256rmk + 2532334718U, // VCVTDQ2PSZ256rmkz + 370171006U, // VCVTDQ2PSZ256rr + 49306750U, // VCVTDQ2PSZ256rrk + 2532334718U, // VCVTDQ2PSZ256rrkz + 806378622U, // VCVTDQ2PSZrm + 2551209086U, // VCVTDQ2PSZrmb + 49306750U, // VCVTDQ2PSZrmbk + 2532334718U, // VCVTDQ2PSZrmbkz + 49306750U, // VCVTDQ2PSZrmk + 2532334718U, // VCVTDQ2PSZrmkz + 370171006U, // VCVTDQ2PSZrr + 2517654654U, // VCVTDQ2PSZrrb + 49306750U, // VCVTDQ2PSZrrbk + 2532334718U, // VCVTDQ2PSZrrbkz + 49306750U, // VCVTDQ2PSZrrk + 2532334718U, // VCVTDQ2PSZrrkz + 336616574U, // VCVTDQ2PSrm + 370171006U, // VCVTDQ2PSrr + 1007703588U, // VCVTPD2DQYrm + 370169380U, // VCVTPD2DQYrr + 672159268U, // VCVTPD2DQZ128rm + 605050404U, // VCVTPD2DQZ128rmb + 49305124U, // VCVTPD2DQZ128rmbk + 2532333092U, // VCVTPD2DQZ128rmbkz + 49305124U, // VCVTPD2DQZ128rmk + 2532333092U, // VCVTPD2DQZ128rmkz + 370169380U, // VCVTPD2DQZ128rr + 49305124U, // VCVTPD2DQZ128rrk + 2532333092U, // VCVTPD2DQZ128rrkz + 1007703588U, // VCVTPD2DQZ256rm + 2752534052U, // VCVTPD2DQZ256rmb + 49305124U, // VCVTPD2DQZ256rmbk + 2532333092U, // VCVTPD2DQZ256rmbkz + 49305124U, // VCVTPD2DQZ256rmk + 2532333092U, // VCVTPD2DQZ256rmkz + 370169380U, // VCVTPD2DQZ256rr + 49305124U, // VCVTPD2DQZ256rrk + 2532333092U, // VCVTPD2DQZ256rrkz + 1108366884U, // VCVTPD2DQZrm + 605050404U, // VCVTPD2DQZrmb + 49305124U, // VCVTPD2DQZrmbk + 2532333092U, // VCVTPD2DQZrmbkz + 49305124U, // VCVTPD2DQZrmk + 2532333092U, // VCVTPD2DQZrmkz + 370169380U, // VCVTPD2DQZrr + 2517653028U, // VCVTPD2DQZrrb + 49305124U, // VCVTPD2DQZrrbk + 2532333092U, // VCVTPD2DQZrrbkz + 49305124U, // VCVTPD2DQZrrk + 2532333092U, // VCVTPD2DQZrrkz + 672159268U, // VCVTPD2DQrm + 370169380U, // VCVTPD2DQrr + 1007705150U, // VCVTPD2PSYrm + 370170942U, // VCVTPD2PSYrr + 672160830U, // VCVTPD2PSZ128rm + 605051966U, // VCVTPD2PSZ128rmb + 49306686U, // VCVTPD2PSZ128rmbk + 2532334654U, // VCVTPD2PSZ128rmbkz + 49306686U, // VCVTPD2PSZ128rmk + 2532334654U, // VCVTPD2PSZ128rmkz + 370170942U, // VCVTPD2PSZ128rr + 49306686U, // VCVTPD2PSZ128rrk + 2532334654U, // VCVTPD2PSZ128rrkz + 1007705150U, // VCVTPD2PSZ256rm + 2752535614U, // VCVTPD2PSZ256rmb + 49306686U, // VCVTPD2PSZ256rmbk + 2532334654U, // VCVTPD2PSZ256rmbkz + 49306686U, // VCVTPD2PSZ256rmk + 2532334654U, // VCVTPD2PSZ256rmkz + 370170942U, // VCVTPD2PSZ256rr + 49306686U, // VCVTPD2PSZ256rrk + 2532334654U, // VCVTPD2PSZ256rrkz + 1108368446U, // VCVTPD2PSZrm + 605051966U, // VCVTPD2PSZrmb + 49306686U, // VCVTPD2PSZrmbk + 2532334654U, // VCVTPD2PSZrmbkz + 49306686U, // VCVTPD2PSZrmk + 2532334654U, // VCVTPD2PSZrmkz + 370170942U, // VCVTPD2PSZrr + 2517654590U, // VCVTPD2PSZrrb + 49306686U, // VCVTPD2PSZrrbk + 2532334654U, // VCVTPD2PSZrrbkz + 49306686U, // VCVTPD2PSZrrk + 2532334654U, // VCVTPD2PSZrrkz + 672160830U, // VCVTPD2PSrm + 370170942U, // VCVTPD2PSrr + 672159807U, // VCVTPD2QQZ128rm + 605050943U, // VCVTPD2QQZ128rmb + 49305663U, // VCVTPD2QQZ128rmbk + 2532333631U, // VCVTPD2QQZ128rmbkz + 49305663U, // VCVTPD2QQZ128rmk + 2532333631U, // VCVTPD2QQZ128rmkz + 370169919U, // VCVTPD2QQZ128rr + 49305663U, // VCVTPD2QQZ128rrk + 2532333631U, // VCVTPD2QQZ128rrkz + 1007704127U, // VCVTPD2QQZ256rm + 2752534591U, // VCVTPD2QQZ256rmb + 49305663U, // VCVTPD2QQZ256rmbk + 2532333631U, // VCVTPD2QQZ256rmbkz + 49305663U, // VCVTPD2QQZ256rmk + 2532333631U, // VCVTPD2QQZ256rmkz + 370169919U, // VCVTPD2QQZ256rr + 49305663U, // VCVTPD2QQZ256rrk + 2532333631U, // VCVTPD2QQZ256rrkz + 1108367423U, // VCVTPD2QQZrm + 605050943U, // VCVTPD2QQZrmb + 49305663U, // VCVTPD2QQZrmbk + 2532333631U, // VCVTPD2QQZrmbkz + 49305663U, // VCVTPD2QQZrmk + 2532333631U, // VCVTPD2QQZrmkz + 370169919U, // VCVTPD2QQZrr + 2517653567U, // VCVTPD2QQZrrb + 49305663U, // VCVTPD2QQZrrbk + 2532333631U, // VCVTPD2QQZrrbkz + 49305663U, // VCVTPD2QQZrrk + 2532333631U, // VCVTPD2QQZrrkz + 672159537U, // VCVTPD2UDQZ128rm + 605050673U, // VCVTPD2UDQZ128rmb + 49305393U, // VCVTPD2UDQZ128rmbk + 2532333361U, // VCVTPD2UDQZ128rmbkz + 49305393U, // VCVTPD2UDQZ128rmk + 2532333361U, // VCVTPD2UDQZ128rmkz + 370169649U, // VCVTPD2UDQZ128rr + 49305393U, // VCVTPD2UDQZ128rrk + 2532333361U, // VCVTPD2UDQZ128rrkz + 1007703857U, // VCVTPD2UDQZ256rm + 2752534321U, // VCVTPD2UDQZ256rmb + 49305393U, // VCVTPD2UDQZ256rmbk + 2532333361U, // VCVTPD2UDQZ256rmbkz + 49305393U, // VCVTPD2UDQZ256rmk + 2532333361U, // VCVTPD2UDQZ256rmkz + 370169649U, // VCVTPD2UDQZ256rr + 49305393U, // VCVTPD2UDQZ256rrk + 2532333361U, // VCVTPD2UDQZ256rrkz + 1108367153U, // VCVTPD2UDQZrm + 605050673U, // VCVTPD2UDQZrmb + 49305393U, // VCVTPD2UDQZrmbk + 2532333361U, // VCVTPD2UDQZrmbkz + 49305393U, // VCVTPD2UDQZrmk + 2532333361U, // VCVTPD2UDQZrmkz + 370169649U, // VCVTPD2UDQZrr + 2517653297U, // VCVTPD2UDQZrrb + 49305393U, // VCVTPD2UDQZrrbk + 2532333361U, // VCVTPD2UDQZrrbkz + 49305393U, // VCVTPD2UDQZrrk + 2532333361U, // VCVTPD2UDQZrrkz + 672159889U, // VCVTPD2UQQZ128rm + 605051025U, // VCVTPD2UQQZ128rmb + 49305745U, // VCVTPD2UQQZ128rmbk + 2532333713U, // VCVTPD2UQQZ128rmbkz + 49305745U, // VCVTPD2UQQZ128rmk + 2532333713U, // VCVTPD2UQQZ128rmkz + 370170001U, // VCVTPD2UQQZ128rr + 49305745U, // VCVTPD2UQQZ128rrk + 2532333713U, // VCVTPD2UQQZ128rrkz + 1007704209U, // VCVTPD2UQQZ256rm + 2752534673U, // VCVTPD2UQQZ256rmb + 49305745U, // VCVTPD2UQQZ256rmbk + 2532333713U, // VCVTPD2UQQZ256rmbkz + 49305745U, // VCVTPD2UQQZ256rmk + 2532333713U, // VCVTPD2UQQZ256rmkz + 370170001U, // VCVTPD2UQQZ256rr + 49305745U, // VCVTPD2UQQZ256rrk + 2532333713U, // VCVTPD2UQQZ256rrkz + 1108367505U, // VCVTPD2UQQZrm + 605051025U, // VCVTPD2UQQZrmb + 49305745U, // VCVTPD2UQQZrmbk + 2532333713U, // VCVTPD2UQQZrmbkz + 49305745U, // VCVTPD2UQQZrmk + 2532333713U, // VCVTPD2UQQZrmkz + 370170001U, // VCVTPD2UQQZrr + 2517653649U, // VCVTPD2UQQZrrb + 49305745U, // VCVTPD2UQQZrrbk + 2532333713U, // VCVTPD2UQQZrrbkz + 49305745U, // VCVTPD2UQQZrrk + 2532333713U, // VCVTPD2UQQZrrkz + 672160841U, // VCVTPH2PSYrm + 370170953U, // VCVTPH2PSYrr + 605051977U, // VCVTPH2PSZ128rm + 49306697U, // VCVTPH2PSZ128rmk + 2532334665U, // VCVTPH2PSZ128rmkz + 370170953U, // VCVTPH2PSZ128rr + 49306697U, // VCVTPH2PSZ128rrk + 2532334665U, // VCVTPH2PSZ128rrkz + 672160841U, // VCVTPH2PSZ256rm + 49306697U, // VCVTPH2PSZ256rmk + 2532334665U, // VCVTPH2PSZ256rmkz + 370170953U, // VCVTPH2PSZ256rr + 49306697U, // VCVTPH2PSZ256rrk + 2532334665U, // VCVTPH2PSZ256rrkz + 1007705161U, // VCVTPH2PSZrm + 49306697U, // VCVTPH2PSZrmk + 2532334665U, // VCVTPH2PSZrmkz + 370170953U, // VCVTPH2PSZrr + 2517654601U, // VCVTPH2PSZrrb + 49306697U, // VCVTPH2PSZrrbk + 2532334665U, // VCVTPH2PSZrrbkz + 49306697U, // VCVTPH2PSZrrk + 2532334665U, // VCVTPH2PSZrrkz + 605051977U, // VCVTPH2PSrm + 370170953U, // VCVTPH2PSrr + 1007703620U, // VCVTPS2DQYrm + 370169412U, // VCVTPS2DQYrr + 672159300U, // VCVTPS2DQZ128rm + 2786088516U, // VCVTPS2DQZ128rmb + 49305156U, // VCVTPS2DQZ128rmbk + 2532333124U, // VCVTPS2DQZ128rmbkz + 49305156U, // VCVTPS2DQZ128rmk + 2532333124U, // VCVTPS2DQZ128rmkz + 370169412U, // VCVTPS2DQZ128rr + 49305156U, // VCVTPS2DQZ128rrk + 2532333124U, // VCVTPS2DQZ128rrkz + 1007703620U, // VCVTPS2DQZ256rm + 638604868U, // VCVTPS2DQZ256rmb + 49305156U, // VCVTPS2DQZ256rmbk + 2532333124U, // VCVTPS2DQZ256rmbkz + 49305156U, // VCVTPS2DQZ256rmk + 2532333124U, // VCVTPS2DQZ256rmkz + 370169412U, // VCVTPS2DQZ256rr + 49305156U, // VCVTPS2DQZ256rrk + 2532333124U, // VCVTPS2DQZ256rrkz + 1108366916U, // VCVTPS2DQZrm + 2786088516U, // VCVTPS2DQZrmb + 49305156U, // VCVTPS2DQZrmbk + 2532333124U, // VCVTPS2DQZrmbkz + 49305156U, // VCVTPS2DQZrmk + 2532333124U, // VCVTPS2DQZrmkz + 370169412U, // VCVTPS2DQZrr + 2517653060U, // VCVTPS2DQZrrb + 49305156U, // VCVTPS2DQZrrbk + 2532333124U, // VCVTPS2DQZrrbkz + 49305156U, // VCVTPS2DQZrrk + 2532333124U, // VCVTPS2DQZrrkz + 672159300U, // VCVTPS2DQrm + 370169412U, // VCVTPS2DQrr + 672156145U, // VCVTPS2PDYrm + 370166257U, // VCVTPS2PDYrr + 605047281U, // VCVTPS2PDZ128rm + 638601713U, // VCVTPS2PDZ128rmb + 49302001U, // VCVTPS2PDZ128rmbk + 2532329969U, // VCVTPS2PDZ128rmbkz + 49302001U, // VCVTPS2PDZ128rmk + 2532329969U, // VCVTPS2PDZ128rmkz + 370166257U, // VCVTPS2PDZ128rr + 49302001U, // VCVTPS2PDZ128rrk + 2532329969U, // VCVTPS2PDZ128rrkz + 672156145U, // VCVTPS2PDZ256rm + 2786085361U, // VCVTPS2PDZ256rmb + 49302001U, // VCVTPS2PDZ256rmbk + 2532329969U, // VCVTPS2PDZ256rmbkz + 49302001U, // VCVTPS2PDZ256rmk + 2532329969U, // VCVTPS2PDZ256rmkz + 370166257U, // VCVTPS2PDZ256rr + 49302001U, // VCVTPS2PDZ256rrk + 2532329969U, // VCVTPS2PDZ256rrkz + 1007700465U, // VCVTPS2PDZrm + 638601713U, // VCVTPS2PDZrmb + 49302001U, // VCVTPS2PDZrmbk + 2532329969U, // VCVTPS2PDZrmbkz + 49302001U, // VCVTPS2PDZrmk + 2532329969U, // VCVTPS2PDZrmkz + 370166257U, // VCVTPS2PDZrr + 2517649905U, // VCVTPS2PDZrrb + 49302001U, // VCVTPS2PDZrrbk + 2532329969U, // VCVTPS2PDZrrbkz + 49302001U, // VCVTPS2PDZrrk + 2532329969U, // VCVTPS2PDZrrkz + 605047281U, // VCVTPS2PDrm + 370166257U, // VCVTPS2PDrr + 2149061219U, // VCVTPS2PHYmr + 2517652067U, // VCVTPS2PHYrr + 2148668003U, // VCVTPS2PHZ128mr + 15864419U, // VCVTPS2PHZ128mrk + 2517652067U, // VCVTPS2PHZ128rr + 49304163U, // VCVTPS2PHZ128rrk + 2532332131U, // VCVTPS2PHZ128rrkz + 2149061219U, // VCVTPS2PHZ256mr + 16257635U, // VCVTPS2PHZ256mrk + 2517652067U, // VCVTPS2PHZ256rr + 49304163U, // VCVTPS2PHZ256rrk + 2532332131U, // VCVTPS2PHZ256rrkz + 2149126755U, // VCVTPS2PHZmr + 16323171U, // VCVTPS2PHZmrk + 2517652067U, // VCVTPS2PHZrr + 370168419U, // VCVTPS2PHZrrb + 49304163U, // VCVTPS2PHZrrbk + 2532332131U, // VCVTPS2PHZrrbkz + 49304163U, // VCVTPS2PHZrrk + 2532332131U, // VCVTPS2PHZrrkz + 2148668003U, // VCVTPS2PHmr + 2517652067U, // VCVTPS2PHrr + 605050966U, // VCVTPS2QQZ128rm + 638605398U, // VCVTPS2QQZ128rmb + 49305686U, // VCVTPS2QQZ128rmbk + 2532333654U, // VCVTPS2QQZ128rmbkz + 49305686U, // VCVTPS2QQZ128rmk + 2532333654U, // VCVTPS2QQZ128rmkz + 370169942U, // VCVTPS2QQZ128rr + 49305686U, // VCVTPS2QQZ128rrk + 2532333654U, // VCVTPS2QQZ128rrkz + 672159830U, // VCVTPS2QQZ256rm + 2786089046U, // VCVTPS2QQZ256rmb + 49305686U, // VCVTPS2QQZ256rmbk + 2532333654U, // VCVTPS2QQZ256rmbkz + 49305686U, // VCVTPS2QQZ256rmk + 2532333654U, // VCVTPS2QQZ256rmkz + 370169942U, // VCVTPS2QQZ256rr + 49305686U, // VCVTPS2QQZ256rrk + 2532333654U, // VCVTPS2QQZ256rrkz + 1007704150U, // VCVTPS2QQZrm + 638605398U, // VCVTPS2QQZrmb + 49305686U, // VCVTPS2QQZrmbk + 2532333654U, // VCVTPS2QQZrmbkz + 49305686U, // VCVTPS2QQZrmk + 2532333654U, // VCVTPS2QQZrmkz + 370169942U, // VCVTPS2QQZrr + 2517653590U, // VCVTPS2QQZrrb + 49305686U, // VCVTPS2QQZrrbk + 2532333654U, // VCVTPS2QQZrrbkz + 49305686U, // VCVTPS2QQZrrk + 2532333654U, // VCVTPS2QQZrrkz + 672159562U, // VCVTPS2UDQZ128rm + 2786088778U, // VCVTPS2UDQZ128rmb + 49305418U, // VCVTPS2UDQZ128rmbk + 2532333386U, // VCVTPS2UDQZ128rmbkz + 49305418U, // VCVTPS2UDQZ128rmk + 2532333386U, // VCVTPS2UDQZ128rmkz + 370169674U, // VCVTPS2UDQZ128rr + 49305418U, // VCVTPS2UDQZ128rrk + 2532333386U, // VCVTPS2UDQZ128rrkz + 1007703882U, // VCVTPS2UDQZ256rm + 638605130U, // VCVTPS2UDQZ256rmb + 49305418U, // VCVTPS2UDQZ256rmbk + 2532333386U, // VCVTPS2UDQZ256rmbkz + 49305418U, // VCVTPS2UDQZ256rmk + 2532333386U, // VCVTPS2UDQZ256rmkz + 370169674U, // VCVTPS2UDQZ256rr + 49305418U, // VCVTPS2UDQZ256rrk + 2532333386U, // VCVTPS2UDQZ256rrkz + 1108367178U, // VCVTPS2UDQZrm + 2786088778U, // VCVTPS2UDQZrmb + 49305418U, // VCVTPS2UDQZrmbk + 2532333386U, // VCVTPS2UDQZrmbkz + 49305418U, // VCVTPS2UDQZrmk + 2532333386U, // VCVTPS2UDQZrmkz + 370169674U, // VCVTPS2UDQZrr + 2517653322U, // VCVTPS2UDQZrrb + 49305418U, // VCVTPS2UDQZrrbk + 2532333386U, // VCVTPS2UDQZrrbkz + 49305418U, // VCVTPS2UDQZrrk + 2532333386U, // VCVTPS2UDQZrrkz + 605051050U, // VCVTPS2UQQZ128rm + 638605482U, // VCVTPS2UQQZ128rmb + 49305770U, // VCVTPS2UQQZ128rmbk + 2532333738U, // VCVTPS2UQQZ128rmbkz + 49305770U, // VCVTPS2UQQZ128rmk + 2532333738U, // VCVTPS2UQQZ128rmkz + 370170026U, // VCVTPS2UQQZ128rr + 49305770U, // VCVTPS2UQQZ128rrk + 2532333738U, // VCVTPS2UQQZ128rrkz + 672159914U, // VCVTPS2UQQZ256rm + 2786089130U, // VCVTPS2UQQZ256rmb + 49305770U, // VCVTPS2UQQZ256rmbk + 2532333738U, // VCVTPS2UQQZ256rmbkz + 49305770U, // VCVTPS2UQQZ256rmk + 2532333738U, // VCVTPS2UQQZ256rmkz + 370170026U, // VCVTPS2UQQZ256rr + 49305770U, // VCVTPS2UQQZ256rrk + 2532333738U, // VCVTPS2UQQZ256rrkz + 1007704234U, // VCVTPS2UQQZrm + 638605482U, // VCVTPS2UQQZrmb + 49305770U, // VCVTPS2UQQZrmbk + 2532333738U, // VCVTPS2UQQZrmbkz + 49305770U, // VCVTPS2UQQZrmk + 2532333738U, // VCVTPS2UQQZrmkz + 370170026U, // VCVTPS2UQQZrr + 2517653674U, // VCVTPS2UQQZrrb + 49305770U, // VCVTPS2UQQZrrbk + 2532333738U, // VCVTPS2UQQZrrbkz + 49305770U, // VCVTPS2UQQZrrk + 2532333738U, // VCVTPS2UQQZrrkz + 336611802U, // VCVTQQ2PDZ128rm + 437275098U, // VCVTQQ2PDZ128rmb + 49301978U, // VCVTQQ2PDZ128rmbk + 2532329946U, // VCVTQQ2PDZ128rmbkz + 49301978U, // VCVTQQ2PDZ128rmk + 2532329946U, // VCVTQQ2PDZ128rmkz + 370166234U, // VCVTQQ2PDZ128rr + 49301978U, // VCVTQQ2PDZ128rrk + 2532329946U, // VCVTQQ2PDZ128rrkz + 1041254874U, // VCVTQQ2PDZ256rm + 2584758746U, // VCVTQQ2PDZ256rmb + 49301978U, // VCVTQQ2PDZ256rmbk + 2532329946U, // VCVTQQ2PDZ256rmbkz + 49301978U, // VCVTQQ2PDZ256rmk + 2532329946U, // VCVTQQ2PDZ256rmkz + 370166234U, // VCVTQQ2PDZ256rr + 49301978U, // VCVTQQ2PDZ256rrk + 2532329946U, // VCVTQQ2PDZ256rrkz + 806373850U, // VCVTQQ2PDZrm + 437275098U, // VCVTQQ2PDZrmb + 49301978U, // VCVTQQ2PDZrmbk + 2532329946U, // VCVTQQ2PDZrmbkz + 49301978U, // VCVTQQ2PDZrmk + 2532329946U, // VCVTQQ2PDZrmkz + 370166234U, // VCVTQQ2PDZrr + 2517649882U, // VCVTQQ2PDZrrb + 49301978U, // VCVTQQ2PDZrrbk + 2532329946U, // VCVTQQ2PDZrrbkz + 49301978U, // VCVTQQ2PDZrrk + 2532329946U, // VCVTQQ2PDZrrkz + 336616597U, // VCVTQQ2PSZ128rm + 437279893U, // VCVTQQ2PSZ128rmb + 49306773U, // VCVTQQ2PSZ128rmbk + 2532334741U, // VCVTQQ2PSZ128rmbkz + 49306773U, // VCVTQQ2PSZ128rmk + 2532334741U, // VCVTQQ2PSZ128rmkz + 370171029U, // VCVTQQ2PSZ128rr + 49306773U, // VCVTQQ2PSZ128rrk + 2532334741U, // VCVTQQ2PSZ128rrkz + 1041259669U, // VCVTQQ2PSZ256rm + 2584763541U, // VCVTQQ2PSZ256rmb + 49306773U, // VCVTQQ2PSZ256rmbk + 2532334741U, // VCVTQQ2PSZ256rmbkz + 49306773U, // VCVTQQ2PSZ256rmk + 2532334741U, // VCVTQQ2PSZ256rmkz + 370171029U, // VCVTQQ2PSZ256rr + 49306773U, // VCVTQQ2PSZ256rrk + 2532334741U, // VCVTQQ2PSZ256rrkz + 806378645U, // VCVTQQ2PSZrm + 437279893U, // VCVTQQ2PSZrmb + 49306773U, // VCVTQQ2PSZrmbk + 2532334741U, // VCVTQQ2PSZrmbkz + 49306773U, // VCVTQQ2PSZrmk + 2532334741U, // VCVTQQ2PSZrmkz + 370171029U, // VCVTQQ2PSZrr + 2517654677U, // VCVTQQ2PSZrrb + 49306773U, // VCVTQQ2PSZrrbk + 2532334741U, // VCVTQQ2PSZrrbkz + 49306773U, // VCVTQQ2PSZrrk + 2532334741U, // VCVTQQ2PSZrrkz + 605049623U, // VCVTSD2SI64Zrm_Int + 370168599U, // VCVTSD2SI64Zrr_Int + 2517652247U, // VCVTSD2SI64Zrrb_Int + 605049623U, // VCVTSD2SI64rm_Int + 370168599U, // VCVTSD2SI64rr_Int + 605049623U, // VCVTSD2SIZrm_Int + 370168599U, // VCVTSD2SIZrr_Int + 2517652247U, // VCVTSD2SIZrrb_Int + 605049623U, // VCVTSD2SIrm_Int + 370168599U, // VCVTSD2SIrr_Int + 2517655590U, // VCVTSD2SSZrm + 2517655590U, // VCVTSD2SSZrm_Int + 49307686U, // VCVTSD2SSZrm_Intk + 2532335654U, // VCVTSD2SSZrm_Intkz + 2517655590U, // VCVTSD2SSZrr + 2517655590U, // VCVTSD2SSZrr_Int + 49307686U, // VCVTSD2SSZrr_Intk + 2532335654U, // VCVTSD2SSZrr_Intkz + 2517655590U, // VCVTSD2SSZrrb_Int + 49307686U, // VCVTSD2SSZrrb_Intk + 2532335654U, // VCVTSD2SSZrrb_Intkz + 2517655590U, // VCVTSD2SSrm + 2517655590U, // VCVTSD2SSrm_Int + 2517655590U, // VCVTSD2SSrr + 2517655590U, // VCVTSD2SSrr_Int + 605049676U, // VCVTSD2USI64Zrm_Int + 370168652U, // VCVTSD2USI64Zrr_Int + 2517652300U, // VCVTSD2USI64Zrrb_Int + 605049676U, // VCVTSD2USIZrm_Int + 370168652U, // VCVTSD2USIZrr_Int + 2517652300U, // VCVTSD2USIZrrb_Int + 2517650889U, // VCVTSI2SDZrm + 2517650889U, // VCVTSI2SDZrm_Int + 2517650889U, // VCVTSI2SDZrr + 2517650889U, // VCVTSI2SDZrr_Int + 2517650889U, // VCVTSI2SDZrrb_Int + 2517650889U, // VCVTSI2SDrm + 2517650889U, // VCVTSI2SDrm_Int + 2517650889U, // VCVTSI2SDrr + 2517650889U, // VCVTSI2SDrr_Int + 2517655601U, // VCVTSI2SSZrm + 2517655601U, // VCVTSI2SSZrm_Int + 2517655601U, // VCVTSI2SSZrr + 2517655601U, // VCVTSI2SSZrr_Int + 2517655601U, // VCVTSI2SSZrrb_Int + 2517655601U, // VCVTSI2SSrm + 2517655601U, // VCVTSI2SSrm_Int + 2517655601U, // VCVTSI2SSrr + 2517655601U, // VCVTSI2SSrr_Int + 2517650889U, // VCVTSI642SDZrm + 2517650889U, // VCVTSI642SDZrm_Int + 2517650889U, // VCVTSI642SDZrr + 2517650889U, // VCVTSI642SDZrr_Int + 2517650889U, // VCVTSI642SDZrrb_Int + 2517650889U, // VCVTSI642SDrm + 2517650889U, // VCVTSI642SDrm_Int + 2517650889U, // VCVTSI642SDrr + 2517650889U, // VCVTSI642SDrr_Int + 2517655601U, // VCVTSI642SSZrm + 2517655601U, // VCVTSI642SSZrm_Int + 2517655601U, // VCVTSI642SSZrr + 2517655601U, // VCVTSI642SSZrr_Int + 2517655601U, // VCVTSI642SSZrrb_Int + 2517655601U, // VCVTSI642SSrm + 2517655601U, // VCVTSI642SSrm_Int + 2517655601U, // VCVTSI642SSrr + 2517655601U, // VCVTSI642SSrr_Int + 2517650912U, // VCVTSS2SDZrm + 2517650912U, // VCVTSS2SDZrm_Int + 49303008U, // VCVTSS2SDZrm_Intk + 2532330976U, // VCVTSS2SDZrm_Intkz + 2517650912U, // VCVTSS2SDZrr + 2517650912U, // VCVTSS2SDZrr_Int + 49303008U, // VCVTSS2SDZrr_Intk + 2532330976U, // VCVTSS2SDZrr_Intkz + 2517650912U, // VCVTSS2SDZrrb_Int + 49303008U, // VCVTSS2SDZrrb_Intk + 2532330976U, // VCVTSS2SDZrrb_Intkz + 2517650912U, // VCVTSS2SDrm + 2517650912U, // VCVTSS2SDrm_Int + 2517650912U, // VCVTSS2SDrr + 2517650912U, // VCVTSS2SDrr_Int + 638604078U, // VCVTSS2SI64Zrm_Int + 370168622U, // VCVTSS2SI64Zrr_Int + 2517652270U, // VCVTSS2SI64Zrrb_Int + 638604078U, // VCVTSS2SI64rm_Int + 370168622U, // VCVTSS2SI64rr_Int + 638604078U, // VCVTSS2SIZrm_Int + 370168622U, // VCVTSS2SIZrr_Int + 2517652270U, // VCVTSS2SIZrrb_Int + 638604078U, // VCVTSS2SIrm_Int + 370168622U, // VCVTSS2SIrr_Int + 638604133U, // VCVTSS2USI64Zrm_Int + 370168677U, // VCVTSS2USI64Zrr_Int + 2517652325U, // VCVTSS2USI64Zrrb_Int + 638604133U, // VCVTSS2USIZrm_Int + 370168677U, // VCVTSS2USIZrr_Int + 2517652325U, // VCVTSS2USIZrrb_Int + 1007703576U, // VCVTTPD2DQYrm + 370169368U, // VCVTTPD2DQYrr + 672159256U, // VCVTTPD2DQZ128rm + 605050392U, // VCVTTPD2DQZ128rmb + 49305112U, // VCVTTPD2DQZ128rmbk + 2532333080U, // VCVTTPD2DQZ128rmbkz + 49305112U, // VCVTTPD2DQZ128rmk + 2532333080U, // VCVTTPD2DQZ128rmkz + 370169368U, // VCVTTPD2DQZ128rr + 49305112U, // VCVTTPD2DQZ128rrk + 2532333080U, // VCVTTPD2DQZ128rrkz + 1007703576U, // VCVTTPD2DQZ256rm + 2752534040U, // VCVTTPD2DQZ256rmb + 49305112U, // VCVTTPD2DQZ256rmbk + 2532333080U, // VCVTTPD2DQZ256rmbkz + 49305112U, // VCVTTPD2DQZ256rmk + 2532333080U, // VCVTTPD2DQZ256rmkz + 370169368U, // VCVTTPD2DQZ256rr + 49305112U, // VCVTTPD2DQZ256rrk + 2532333080U, // VCVTTPD2DQZ256rrkz + 1108366872U, // VCVTTPD2DQZrm + 605050392U, // VCVTTPD2DQZrmb + 49305112U, // VCVTTPD2DQZrmbk + 2532333080U, // VCVTTPD2DQZrmbkz + 49305112U, // VCVTTPD2DQZrmk + 2532333080U, // VCVTTPD2DQZrmkz + 370169368U, // VCVTTPD2DQZrr + 2517653016U, // VCVTTPD2DQZrrb + 49305112U, // VCVTTPD2DQZrrbk + 2532333080U, // VCVTTPD2DQZrrbkz + 49305112U, // VCVTTPD2DQZrrk + 2532333080U, // VCVTTPD2DQZrrkz + 672159256U, // VCVTTPD2DQrm + 370169368U, // VCVTTPD2DQrr + 672159795U, // VCVTTPD2QQZ128rm + 605050931U, // VCVTTPD2QQZ128rmb + 49305651U, // VCVTTPD2QQZ128rmbk + 2532333619U, // VCVTTPD2QQZ128rmbkz + 49305651U, // VCVTTPD2QQZ128rmk + 2532333619U, // VCVTTPD2QQZ128rmkz + 370169907U, // VCVTTPD2QQZ128rr + 49305651U, // VCVTTPD2QQZ128rrk + 2532333619U, // VCVTTPD2QQZ128rrkz + 1007704115U, // VCVTTPD2QQZ256rm + 2752534579U, // VCVTTPD2QQZ256rmb + 49305651U, // VCVTTPD2QQZ256rmbk + 2532333619U, // VCVTTPD2QQZ256rmbkz + 49305651U, // VCVTTPD2QQZ256rmk + 2532333619U, // VCVTTPD2QQZ256rmkz + 370169907U, // VCVTTPD2QQZ256rr + 49305651U, // VCVTTPD2QQZ256rrk + 2532333619U, // VCVTTPD2QQZ256rrkz + 1108367411U, // VCVTTPD2QQZrm + 605050931U, // VCVTTPD2QQZrmb + 49305651U, // VCVTTPD2QQZrmbk + 2532333619U, // VCVTTPD2QQZrmbkz + 49305651U, // VCVTTPD2QQZrmk + 2532333619U, // VCVTTPD2QQZrmkz + 370169907U, // VCVTTPD2QQZrr + 2517653555U, // VCVTTPD2QQZrrb + 49305651U, // VCVTTPD2QQZrrbk + 2532333619U, // VCVTTPD2QQZrrbkz + 49305651U, // VCVTTPD2QQZrrk + 2532333619U, // VCVTTPD2QQZrrkz + 672159524U, // VCVTTPD2UDQZ128rm + 605050660U, // VCVTTPD2UDQZ128rmb + 49305380U, // VCVTTPD2UDQZ128rmbk + 2532333348U, // VCVTTPD2UDQZ128rmbkz + 49305380U, // VCVTTPD2UDQZ128rmk + 2532333348U, // VCVTTPD2UDQZ128rmkz + 370169636U, // VCVTTPD2UDQZ128rr + 49305380U, // VCVTTPD2UDQZ128rrk + 2532333348U, // VCVTTPD2UDQZ128rrkz + 1007703844U, // VCVTTPD2UDQZ256rm + 2752534308U, // VCVTTPD2UDQZ256rmb + 49305380U, // VCVTTPD2UDQZ256rmbk + 2532333348U, // VCVTTPD2UDQZ256rmbkz + 49305380U, // VCVTTPD2UDQZ256rmk + 2532333348U, // VCVTTPD2UDQZ256rmkz + 370169636U, // VCVTTPD2UDQZ256rr + 49305380U, // VCVTTPD2UDQZ256rrk + 2532333348U, // VCVTTPD2UDQZ256rrkz + 1108367140U, // VCVTTPD2UDQZrm + 605050660U, // VCVTTPD2UDQZrmb + 49305380U, // VCVTTPD2UDQZrmbk + 2532333348U, // VCVTTPD2UDQZrmbkz + 49305380U, // VCVTTPD2UDQZrmk + 2532333348U, // VCVTTPD2UDQZrmkz + 370169636U, // VCVTTPD2UDQZrr + 2517653284U, // VCVTTPD2UDQZrrb + 49305380U, // VCVTTPD2UDQZrrbk + 2532333348U, // VCVTTPD2UDQZrrbkz + 49305380U, // VCVTTPD2UDQZrrk + 2532333348U, // VCVTTPD2UDQZrrkz + 672159876U, // VCVTTPD2UQQZ128rm + 605051012U, // VCVTTPD2UQQZ128rmb + 49305732U, // VCVTTPD2UQQZ128rmbk + 2532333700U, // VCVTTPD2UQQZ128rmbkz + 49305732U, // VCVTTPD2UQQZ128rmk + 2532333700U, // VCVTTPD2UQQZ128rmkz + 370169988U, // VCVTTPD2UQQZ128rr + 49305732U, // VCVTTPD2UQQZ128rrk + 2532333700U, // VCVTTPD2UQQZ128rrkz + 1007704196U, // VCVTTPD2UQQZ256rm + 2752534660U, // VCVTTPD2UQQZ256rmb + 49305732U, // VCVTTPD2UQQZ256rmbk + 2532333700U, // VCVTTPD2UQQZ256rmbkz + 49305732U, // VCVTTPD2UQQZ256rmk + 2532333700U, // VCVTTPD2UQQZ256rmkz + 370169988U, // VCVTTPD2UQQZ256rr + 49305732U, // VCVTTPD2UQQZ256rrk + 2532333700U, // VCVTTPD2UQQZ256rrkz + 1108367492U, // VCVTTPD2UQQZrm + 605051012U, // VCVTTPD2UQQZrmb + 49305732U, // VCVTTPD2UQQZrmbk + 2532333700U, // VCVTTPD2UQQZrmbkz + 49305732U, // VCVTTPD2UQQZrmk + 2532333700U, // VCVTTPD2UQQZrmkz + 370169988U, // VCVTTPD2UQQZrr + 2517653636U, // VCVTTPD2UQQZrrb + 49305732U, // VCVTTPD2UQQZrrbk + 2532333700U, // VCVTTPD2UQQZrrbkz + 49305732U, // VCVTTPD2UQQZrrk + 2532333700U, // VCVTTPD2UQQZrrkz + 1007703608U, // VCVTTPS2DQYrm + 370169400U, // VCVTTPS2DQYrr + 672159288U, // VCVTTPS2DQZ128rm + 2786088504U, // VCVTTPS2DQZ128rmb + 49305144U, // VCVTTPS2DQZ128rmbk + 2532333112U, // VCVTTPS2DQZ128rmbkz + 49305144U, // VCVTTPS2DQZ128rmk + 2532333112U, // VCVTTPS2DQZ128rmkz + 370169400U, // VCVTTPS2DQZ128rr + 49305144U, // VCVTTPS2DQZ128rrk + 2532333112U, // VCVTTPS2DQZ128rrkz + 1007703608U, // VCVTTPS2DQZ256rm + 638604856U, // VCVTTPS2DQZ256rmb + 49305144U, // VCVTTPS2DQZ256rmbk + 2532333112U, // VCVTTPS2DQZ256rmbkz + 49305144U, // VCVTTPS2DQZ256rmk + 2532333112U, // VCVTTPS2DQZ256rmkz + 370169400U, // VCVTTPS2DQZ256rr + 49305144U, // VCVTTPS2DQZ256rrk + 2532333112U, // VCVTTPS2DQZ256rrkz + 1108366904U, // VCVTTPS2DQZrm + 2786088504U, // VCVTTPS2DQZrmb + 49305144U, // VCVTTPS2DQZrmbk + 2532333112U, // VCVTTPS2DQZrmbkz + 49305144U, // VCVTTPS2DQZrmk + 2532333112U, // VCVTTPS2DQZrmkz + 370169400U, // VCVTTPS2DQZrr + 2517653048U, // VCVTTPS2DQZrrb + 49305144U, // VCVTTPS2DQZrrbk + 2532333112U, // VCVTTPS2DQZrrbkz + 49305144U, // VCVTTPS2DQZrrk + 2532333112U, // VCVTTPS2DQZrrkz + 672159288U, // VCVTTPS2DQrm + 370169400U, // VCVTTPS2DQrr + 605050954U, // VCVTTPS2QQZ128rm + 638605386U, // VCVTTPS2QQZ128rmb + 49305674U, // VCVTTPS2QQZ128rmbk + 2532333642U, // VCVTTPS2QQZ128rmbkz + 49305674U, // VCVTTPS2QQZ128rmk + 2532333642U, // VCVTTPS2QQZ128rmkz + 370169930U, // VCVTTPS2QQZ128rr + 49305674U, // VCVTTPS2QQZ128rrk + 2532333642U, // VCVTTPS2QQZ128rrkz + 672159818U, // VCVTTPS2QQZ256rm + 2786089034U, // VCVTTPS2QQZ256rmb + 49305674U, // VCVTTPS2QQZ256rmbk + 2532333642U, // VCVTTPS2QQZ256rmbkz + 49305674U, // VCVTTPS2QQZ256rmk + 2532333642U, // VCVTTPS2QQZ256rmkz + 370169930U, // VCVTTPS2QQZ256rr + 49305674U, // VCVTTPS2QQZ256rrk + 2532333642U, // VCVTTPS2QQZ256rrkz + 1007704138U, // VCVTTPS2QQZrm + 638605386U, // VCVTTPS2QQZrmb + 49305674U, // VCVTTPS2QQZrmbk + 2532333642U, // VCVTTPS2QQZrmbkz + 49305674U, // VCVTTPS2QQZrmk + 2532333642U, // VCVTTPS2QQZrmkz + 370169930U, // VCVTTPS2QQZrr + 2517653578U, // VCVTTPS2QQZrrb + 49305674U, // VCVTTPS2QQZrrbk + 2532333642U, // VCVTTPS2QQZrrbkz + 49305674U, // VCVTTPS2QQZrrk + 2532333642U, // VCVTTPS2QQZrrkz + 672159549U, // VCVTTPS2UDQZ128rm + 2786088765U, // VCVTTPS2UDQZ128rmb + 49305405U, // VCVTTPS2UDQZ128rmbk + 2532333373U, // VCVTTPS2UDQZ128rmbkz + 49305405U, // VCVTTPS2UDQZ128rmk + 2532333373U, // VCVTTPS2UDQZ128rmkz + 370169661U, // VCVTTPS2UDQZ128rr + 49305405U, // VCVTTPS2UDQZ128rrk + 2532333373U, // VCVTTPS2UDQZ128rrkz + 1007703869U, // VCVTTPS2UDQZ256rm + 638605117U, // VCVTTPS2UDQZ256rmb + 49305405U, // VCVTTPS2UDQZ256rmbk + 2532333373U, // VCVTTPS2UDQZ256rmbkz + 49305405U, // VCVTTPS2UDQZ256rmk + 2532333373U, // VCVTTPS2UDQZ256rmkz + 370169661U, // VCVTTPS2UDQZ256rr + 49305405U, // VCVTTPS2UDQZ256rrk + 2532333373U, // VCVTTPS2UDQZ256rrkz + 1108367165U, // VCVTTPS2UDQZrm + 2786088765U, // VCVTTPS2UDQZrmb + 49305405U, // VCVTTPS2UDQZrmbk + 2532333373U, // VCVTTPS2UDQZrmbkz + 49305405U, // VCVTTPS2UDQZrmk + 2532333373U, // VCVTTPS2UDQZrmkz + 370169661U, // VCVTTPS2UDQZrr + 2517653309U, // VCVTTPS2UDQZrrb + 49305405U, // VCVTTPS2UDQZrrbk + 2532333373U, // VCVTTPS2UDQZrrbkz + 49305405U, // VCVTTPS2UDQZrrk + 2532333373U, // VCVTTPS2UDQZrrkz + 605051037U, // VCVTTPS2UQQZ128rm + 638605469U, // VCVTTPS2UQQZ128rmb + 49305757U, // VCVTTPS2UQQZ128rmbk + 2532333725U, // VCVTTPS2UQQZ128rmbkz + 49305757U, // VCVTTPS2UQQZ128rmk + 2532333725U, // VCVTTPS2UQQZ128rmkz + 370170013U, // VCVTTPS2UQQZ128rr + 49305757U, // VCVTTPS2UQQZ128rrk + 2532333725U, // VCVTTPS2UQQZ128rrkz + 672159901U, // VCVTTPS2UQQZ256rm + 2786089117U, // VCVTTPS2UQQZ256rmb + 49305757U, // VCVTTPS2UQQZ256rmbk + 2532333725U, // VCVTTPS2UQQZ256rmbkz + 49305757U, // VCVTTPS2UQQZ256rmk + 2532333725U, // VCVTTPS2UQQZ256rmkz + 370170013U, // VCVTTPS2UQQZ256rr + 49305757U, // VCVTTPS2UQQZ256rrk + 2532333725U, // VCVTTPS2UQQZ256rrkz + 1007704221U, // VCVTTPS2UQQZrm + 638605469U, // VCVTTPS2UQQZrmb + 49305757U, // VCVTTPS2UQQZrmbk + 2532333725U, // VCVTTPS2UQQZrmbkz + 49305757U, // VCVTTPS2UQQZrmk + 2532333725U, // VCVTTPS2UQQZrmkz + 370170013U, // VCVTTPS2UQQZrr + 2517653661U, // VCVTTPS2UQQZrrb + 49305757U, // VCVTTPS2UQQZrrbk + 2532333725U, // VCVTTPS2UQQZrrbkz + 49305757U, // VCVTTPS2UQQZrrk + 2532333725U, // VCVTTPS2UQQZrrkz + 605049611U, // VCVTTSD2SI64Zrm + 605049611U, // VCVTTSD2SI64Zrm_Int + 370168587U, // VCVTTSD2SI64Zrr + 370168587U, // VCVTTSD2SI64Zrr_Int + 2517652235U, // VCVTTSD2SI64Zrrb_Int + 605049611U, // VCVTTSD2SI64rm + 605049611U, // VCVTTSD2SI64rm_Int + 370168587U, // VCVTTSD2SI64rr + 370168587U, // VCVTTSD2SI64rr_Int + 605049611U, // VCVTTSD2SIZrm + 605049611U, // VCVTTSD2SIZrm_Int + 370168587U, // VCVTTSD2SIZrr + 370168587U, // VCVTTSD2SIZrr_Int + 2517652235U, // VCVTTSD2SIZrrb_Int + 605049611U, // VCVTTSD2SIrm + 605049611U, // VCVTTSD2SIrm_Int + 370168587U, // VCVTTSD2SIrr + 370168587U, // VCVTTSD2SIrr_Int + 605049663U, // VCVTTSD2USI64Zrm + 605049663U, // VCVTTSD2USI64Zrm_Int + 370168639U, // VCVTTSD2USI64Zrr + 370168639U, // VCVTTSD2USI64Zrr_Int + 2517652287U, // VCVTTSD2USI64Zrrb_Int + 605049663U, // VCVTTSD2USIZrm + 605049663U, // VCVTTSD2USIZrm_Int + 370168639U, // VCVTTSD2USIZrr + 370168639U, // VCVTTSD2USIZrr_Int + 2517652287U, // VCVTTSD2USIZrrb_Int + 638604066U, // VCVTTSS2SI64Zrm + 638604066U, // VCVTTSS2SI64Zrm_Int + 370168610U, // VCVTTSS2SI64Zrr + 370168610U, // VCVTTSS2SI64Zrr_Int + 2517652258U, // VCVTTSS2SI64Zrrb_Int + 638604066U, // VCVTTSS2SI64rm + 638604066U, // VCVTTSS2SI64rm_Int + 370168610U, // VCVTTSS2SI64rr + 370168610U, // VCVTTSS2SI64rr_Int + 638604066U, // VCVTTSS2SIZrm + 638604066U, // VCVTTSS2SIZrm_Int + 370168610U, // VCVTTSS2SIZrr + 370168610U, // VCVTTSS2SIZrr_Int + 2517652258U, // VCVTTSS2SIZrrb_Int + 638604066U, // VCVTTSS2SIrm + 638604066U, // VCVTTSS2SIrm_Int + 370168610U, // VCVTTSS2SIrr + 370168610U, // VCVTTSS2SIrr_Int + 638604120U, // VCVTTSS2USI64Zrm + 638604120U, // VCVTTSS2USI64Zrm_Int + 370168664U, // VCVTTSS2USI64Zrr + 370168664U, // VCVTTSS2USI64Zrr_Int + 2517652312U, // VCVTTSS2USI64Zrrb_Int + 638604120U, // VCVTTSS2USIZrm + 638604120U, // VCVTTSS2USIZrm_Int + 370168664U, // VCVTTSS2USIZrr + 370168664U, // VCVTTSS2USIZrr_Int + 2517652312U, // VCVTTSS2USIZrrb_Int + 437275086U, // VCVTUDQ2PDZ128rm + 403720654U, // VCVTUDQ2PDZ128rmb + 49301966U, // VCVTUDQ2PDZ128rmbk + 2532329934U, // VCVTUDQ2PDZ128rmbkz + 49301966U, // VCVTUDQ2PDZ128rmk + 2532329934U, // VCVTUDQ2PDZ128rmkz + 370166222U, // VCVTUDQ2PDZ128rr + 49301966U, // VCVTUDQ2PDZ128rrk + 2532329934U, // VCVTUDQ2PDZ128rrkz + 336611790U, // VCVTUDQ2PDZ256rm + 2551204302U, // VCVTUDQ2PDZ256rmb + 49301966U, // VCVTUDQ2PDZ256rmbk + 2532329934U, // VCVTUDQ2PDZ256rmbkz + 49301966U, // VCVTUDQ2PDZ256rmk + 2532329934U, // VCVTUDQ2PDZ256rmkz + 370166222U, // VCVTUDQ2PDZ256rr + 49301966U, // VCVTUDQ2PDZ256rrk + 2532329934U, // VCVTUDQ2PDZ256rrkz + 1041254862U, // VCVTUDQ2PDZrm + 403720654U, // VCVTUDQ2PDZrmb + 49301966U, // VCVTUDQ2PDZrmbk + 2532329934U, // VCVTUDQ2PDZrmbkz + 49301966U, // VCVTUDQ2PDZrmk + 2532329934U, // VCVTUDQ2PDZrmkz + 370166222U, // VCVTUDQ2PDZrr + 49301966U, // VCVTUDQ2PDZrrk + 2532329934U, // VCVTUDQ2PDZrrkz + 336616585U, // VCVTUDQ2PSZ128rm + 2551209097U, // VCVTUDQ2PSZ128rmb + 49306761U, // VCVTUDQ2PSZ128rmbk + 2532334729U, // VCVTUDQ2PSZ128rmbkz + 49306761U, // VCVTUDQ2PSZ128rmk + 2532334729U, // VCVTUDQ2PSZ128rmkz + 370171017U, // VCVTUDQ2PSZ128rr + 49306761U, // VCVTUDQ2PSZ128rrk + 2532334729U, // VCVTUDQ2PSZ128rrkz + 1041259657U, // VCVTUDQ2PSZ256rm + 403725449U, // VCVTUDQ2PSZ256rmb + 49306761U, // VCVTUDQ2PSZ256rmbk + 2532334729U, // VCVTUDQ2PSZ256rmbkz + 49306761U, // VCVTUDQ2PSZ256rmk + 2532334729U, // VCVTUDQ2PSZ256rmkz + 370171017U, // VCVTUDQ2PSZ256rr + 49306761U, // VCVTUDQ2PSZ256rrk + 2532334729U, // VCVTUDQ2PSZ256rrkz + 806378633U, // VCVTUDQ2PSZrm + 2551209097U, // VCVTUDQ2PSZrmb + 49306761U, // VCVTUDQ2PSZrmbk + 2532334729U, // VCVTUDQ2PSZrmbkz + 49306761U, // VCVTUDQ2PSZrmk + 2532334729U, // VCVTUDQ2PSZrmkz + 370171017U, // VCVTUDQ2PSZrr + 2517654665U, // VCVTUDQ2PSZrrb + 49306761U, // VCVTUDQ2PSZrrbk + 2532334729U, // VCVTUDQ2PSZrrbkz + 49306761U, // VCVTUDQ2PSZrrk + 2532334729U, // VCVTUDQ2PSZrrkz + 336611813U, // VCVTUQQ2PDZ128rm + 437275109U, // VCVTUQQ2PDZ128rmb + 49301989U, // VCVTUQQ2PDZ128rmbk + 2532329957U, // VCVTUQQ2PDZ128rmbkz + 49301989U, // VCVTUQQ2PDZ128rmk + 2532329957U, // VCVTUQQ2PDZ128rmkz + 370166245U, // VCVTUQQ2PDZ128rr + 49301989U, // VCVTUQQ2PDZ128rrk + 2532329957U, // VCVTUQQ2PDZ128rrkz + 1041254885U, // VCVTUQQ2PDZ256rm + 2584758757U, // VCVTUQQ2PDZ256rmb + 49301989U, // VCVTUQQ2PDZ256rmbk + 2532329957U, // VCVTUQQ2PDZ256rmbkz + 49301989U, // VCVTUQQ2PDZ256rmk + 2532329957U, // VCVTUQQ2PDZ256rmkz + 370166245U, // VCVTUQQ2PDZ256rr + 49301989U, // VCVTUQQ2PDZ256rrk + 2532329957U, // VCVTUQQ2PDZ256rrkz + 806373861U, // VCVTUQQ2PDZrm + 437275109U, // VCVTUQQ2PDZrmb + 49301989U, // VCVTUQQ2PDZrmbk + 2532329957U, // VCVTUQQ2PDZrmbkz + 49301989U, // VCVTUQQ2PDZrmk + 2532329957U, // VCVTUQQ2PDZrmkz + 370166245U, // VCVTUQQ2PDZrr + 2517649893U, // VCVTUQQ2PDZrrb + 49301989U, // VCVTUQQ2PDZrrbk + 2532329957U, // VCVTUQQ2PDZrrbkz + 49301989U, // VCVTUQQ2PDZrrk + 2532329957U, // VCVTUQQ2PDZrrkz + 336616608U, // VCVTUQQ2PSZ128rm + 437279904U, // VCVTUQQ2PSZ128rmb + 49306784U, // VCVTUQQ2PSZ128rmbk + 2532334752U, // VCVTUQQ2PSZ128rmbkz + 49306784U, // VCVTUQQ2PSZ128rmk + 2532334752U, // VCVTUQQ2PSZ128rmkz + 370171040U, // VCVTUQQ2PSZ128rr + 49306784U, // VCVTUQQ2PSZ128rrk + 2532334752U, // VCVTUQQ2PSZ128rrkz + 1041259680U, // VCVTUQQ2PSZ256rm + 2584763552U, // VCVTUQQ2PSZ256rmb + 49306784U, // VCVTUQQ2PSZ256rmbk + 2532334752U, // VCVTUQQ2PSZ256rmbkz + 49306784U, // VCVTUQQ2PSZ256rmk + 2532334752U, // VCVTUQQ2PSZ256rmkz + 370171040U, // VCVTUQQ2PSZ256rr + 49306784U, // VCVTUQQ2PSZ256rrk + 2532334752U, // VCVTUQQ2PSZ256rrkz + 806378656U, // VCVTUQQ2PSZrm + 437279904U, // VCVTUQQ2PSZrmb + 49306784U, // VCVTUQQ2PSZrmbk + 2532334752U, // VCVTUQQ2PSZrmbkz + 49306784U, // VCVTUQQ2PSZrmk + 2532334752U, // VCVTUQQ2PSZrmkz + 370171040U, // VCVTUQQ2PSZrr + 2517654688U, // VCVTUQQ2PSZrrb + 49306784U, // VCVTUQQ2PSZrrbk + 2532334752U, // VCVTUQQ2PSZrrbkz + 49306784U, // VCVTUQQ2PSZrrk + 2532334752U, // VCVTUQQ2PSZrrkz + 2517650900U, // VCVTUSI2SDZrm + 2517650900U, // VCVTUSI2SDZrm_Int + 2517650900U, // VCVTUSI2SDZrr + 2517650900U, // VCVTUSI2SDZrr_Int + 2517655612U, // VCVTUSI2SSZrm + 2517655612U, // VCVTUSI2SSZrm_Int + 2517655612U, // VCVTUSI2SSZrr + 2517655612U, // VCVTUSI2SSZrr_Int + 2517655612U, // VCVTUSI2SSZrrb_Int + 2517650900U, // VCVTUSI642SDZrm + 2517650900U, // VCVTUSI642SDZrm_Int + 2517650900U, // VCVTUSI642SDZrr + 2517650900U, // VCVTUSI642SDZrr_Int + 2517650900U, // VCVTUSI642SDZrrb_Int + 2517655612U, // VCVTUSI642SSZrm + 2517655612U, // VCVTUSI642SSZrm_Int + 2517655612U, // VCVTUSI642SSZrr + 2517655612U, // VCVTUSI642SSZrr_Int + 2517655612U, // VCVTUSI642SSZrrb_Int + 2517656413U, // VDBPSADBWZ128rmi + 49308509U, // VDBPSADBWZ128rmik + 2532336477U, // VDBPSADBWZ128rmikz + 2517656413U, // VDBPSADBWZ128rri + 49308509U, // VDBPSADBWZ128rrik + 2532336477U, // VDBPSADBWZ128rrikz + 2517656413U, // VDBPSADBWZ256rmi + 49308509U, // VDBPSADBWZ256rmik + 2532336477U, // VDBPSADBWZ256rmikz + 2517656413U, // VDBPSADBWZ256rri + 49308509U, // VDBPSADBWZ256rrik + 2532336477U, // VDBPSADBWZ256rrikz + 2517656413U, // VDBPSADBWZrmi + 49308509U, // VDBPSADBWZrmik + 2532336477U, // VDBPSADBWZrmikz + 2517656413U, // VDBPSADBWZrri + 49308509U, // VDBPSADBWZrrik + 2532336477U, // VDBPSADBWZrrikz + 2517650601U, // VDIVPDYrm + 2517650601U, // VDIVPDYrr + 2517650601U, // VDIVPDZ128rm + 2517650601U, // VDIVPDZ128rmb + 49302697U, // VDIVPDZ128rmbk + 2532330665U, // VDIVPDZ128rmbkz + 49302697U, // VDIVPDZ128rmk + 2532330665U, // VDIVPDZ128rmkz + 2517650601U, // VDIVPDZ128rr + 49302697U, // VDIVPDZ128rrk + 2532330665U, // VDIVPDZ128rrkz + 2517650601U, // VDIVPDZ256rm + 2517650601U, // VDIVPDZ256rmb + 49302697U, // VDIVPDZ256rmbk + 2532330665U, // VDIVPDZ256rmbkz + 49302697U, // VDIVPDZ256rmk + 2532330665U, // VDIVPDZ256rmkz + 2517650601U, // VDIVPDZ256rr + 49302697U, // VDIVPDZ256rrk + 2532330665U, // VDIVPDZ256rrkz + 2517650601U, // VDIVPDZrm + 2517650601U, // VDIVPDZrmb + 49302697U, // VDIVPDZrmbk + 2532330665U, // VDIVPDZrmbkz + 49302697U, // VDIVPDZrmk + 2532330665U, // VDIVPDZrmkz + 2517650601U, // VDIVPDZrr + 2517650601U, // VDIVPDZrrb + 49302697U, // VDIVPDZrrbk + 2532330665U, // VDIVPDZrrbkz + 49302697U, // VDIVPDZrrk + 2532330665U, // VDIVPDZrrkz + 2517650601U, // VDIVPDrm + 2517650601U, // VDIVPDrr + 2517655436U, // VDIVPSYrm + 2517655436U, // VDIVPSYrr + 2517655436U, // VDIVPSZ128rm + 2517655436U, // VDIVPSZ128rmb + 49307532U, // VDIVPSZ128rmbk + 2532335500U, // VDIVPSZ128rmbkz + 49307532U, // VDIVPSZ128rmk + 2532335500U, // VDIVPSZ128rmkz + 2517655436U, // VDIVPSZ128rr + 49307532U, // VDIVPSZ128rrk + 2532335500U, // VDIVPSZ128rrkz + 2517655436U, // VDIVPSZ256rm + 2517655436U, // VDIVPSZ256rmb + 49307532U, // VDIVPSZ256rmbk + 2532335500U, // VDIVPSZ256rmbkz + 49307532U, // VDIVPSZ256rmk + 2532335500U, // VDIVPSZ256rmkz + 2517655436U, // VDIVPSZ256rr + 49307532U, // VDIVPSZ256rrk + 2532335500U, // VDIVPSZ256rrkz + 2517655436U, // VDIVPSZrm + 2517655436U, // VDIVPSZrmb + 49307532U, // VDIVPSZrmbk + 2532335500U, // VDIVPSZrmbkz + 49307532U, // VDIVPSZrmk + 2532335500U, // VDIVPSZrmkz + 2517655436U, // VDIVPSZrr + 2517655436U, // VDIVPSZrrb + 49307532U, // VDIVPSZrrbk + 2532335500U, // VDIVPSZrrbkz + 49307532U, // VDIVPSZrrk + 2532335500U, // VDIVPSZrrkz + 2517655436U, // VDIVPSrm + 2517655436U, // VDIVPSrr + 2517651340U, // VDIVSDZrm + 2517651340U, // VDIVSDZrm_Int + 49303436U, // VDIVSDZrm_Intk + 2532331404U, // VDIVSDZrm_Intkz + 2517651340U, // VDIVSDZrr + 2517651340U, // VDIVSDZrr_Int + 49303436U, // VDIVSDZrr_Intk + 2532331404U, // VDIVSDZrr_Intkz + 2517651340U, // VDIVSDZrrb_Int + 49303436U, // VDIVSDZrrb_Intk + 2532331404U, // VDIVSDZrrb_Intkz + 2517651340U, // VDIVSDrm + 2517651340U, // VDIVSDrm_Int + 2517651340U, // VDIVSDrr + 2517651340U, // VDIVSDrr_Int + 2517655999U, // VDIVSSZrm + 2517655999U, // VDIVSSZrm_Int + 49308095U, // VDIVSSZrm_Intk + 2532336063U, // VDIVSSZrm_Intkz + 2517655999U, // VDIVSSZrr + 2517655999U, // VDIVSSZrr_Int + 49308095U, // VDIVSSZrr_Intk + 2532336063U, // VDIVSSZrr_Intkz + 2517655999U, // VDIVSSZrrb_Int + 49308095U, // VDIVSSZrrb_Intk + 2532336063U, // VDIVSSZrrb_Intkz + 2517655999U, // VDIVSSrm + 2517655999U, // VDIVSSrm_Int + 2517655999U, // VDIVSSrr + 2517655999U, // VDIVSSrr_Int + 2517650433U, // VDPPDrmi + 2517650433U, // VDPPDrri + 2517655252U, // VDPPSYrmi + 2517655252U, // VDPPSYrri + 2517655252U, // VDPPSrmi + 2517655252U, // VDPPSrri + 39644U, // VERRm + 23260U, // VERRr + 42308U, // VERWm + 25924U, // VERWr + 1108363706U, // VEXP2PDZm + 605047226U, // VEXP2PDZmb + 49301946U, // VEXP2PDZmbk + 2532329914U, // VEXP2PDZmbkz + 49301946U, // VEXP2PDZmk + 2532329914U, // VEXP2PDZmkz + 370166202U, // VEXP2PDZr + 2517649850U, // VEXP2PDZrb + 49301946U, // VEXP2PDZrbk + 2532329914U, // VEXP2PDZrbkz + 49301946U, // VEXP2PDZrk + 2532329914U, // VEXP2PDZrkz + 1108368501U, // VEXP2PSZm + 2786090101U, // VEXP2PSZmb + 49306741U, // VEXP2PSZmbk + 2532334709U, // VEXP2PSZmbkz + 49306741U, // VEXP2PSZmk + 2532334709U, // VEXP2PSZmkz + 370170997U, // VEXP2PSZr + 2517654645U, // VEXP2PSZrb + 49306741U, // VEXP2PSZrbk + 2532334709U, // VEXP2PSZrbkz + 49306741U, // VEXP2PSZrk + 2532334709U, // VEXP2PSZrkz + 672156427U, // VEXPANDPDZ128rm + 49302283U, // VEXPANDPDZ128rmk + 2532330251U, // VEXPANDPDZ128rmkz + 370166539U, // VEXPANDPDZ128rr + 49302283U, // VEXPANDPDZ128rrk + 2532330251U, // VEXPANDPDZ128rrkz + 1007700747U, // VEXPANDPDZ256rm + 49302283U, // VEXPANDPDZ256rmk + 2532330251U, // VEXPANDPDZ256rmkz + 370166539U, // VEXPANDPDZ256rr + 49302283U, // VEXPANDPDZ256rrk + 2532330251U, // VEXPANDPDZ256rrkz + 1108364043U, // VEXPANDPDZrm + 49302283U, // VEXPANDPDZrmk + 2532330251U, // VEXPANDPDZrmkz + 370166539U, // VEXPANDPDZrr + 49302283U, // VEXPANDPDZrrk + 2532330251U, // VEXPANDPDZrrkz + 672161226U, // VEXPANDPSZ128rm + 49307082U, // VEXPANDPSZ128rmk + 2532335050U, // VEXPANDPSZ128rmkz + 370171338U, // VEXPANDPSZ128rr + 49307082U, // VEXPANDPSZ128rrk + 2532335050U, // VEXPANDPSZ128rrkz + 1007705546U, // VEXPANDPSZ256rm + 49307082U, // VEXPANDPSZ256rmk + 2532335050U, // VEXPANDPSZ256rmkz + 370171338U, // VEXPANDPSZ256rr + 49307082U, // VEXPANDPSZ256rrk + 2532335050U, // VEXPANDPSZ256rrkz + 1108368842U, // VEXPANDPSZrm + 49307082U, // VEXPANDPSZrmk + 2532335050U, // VEXPANDPSZrmkz + 370171338U, // VEXPANDPSZrr + 49307082U, // VEXPANDPSZrrk + 2532335050U, // VEXPANDPSZrrkz + 2149057156U, // VEXTRACTF128mr + 2517648004U, // VEXTRACTF128rr + 2149056937U, // VEXTRACTF32x4Z256mr + 16253353U, // VEXTRACTF32x4Z256mrk + 2517647785U, // VEXTRACTF32x4Z256rr + 49299881U, // VEXTRACTF32x4Z256rrk + 2532327849U, // VEXTRACTF32x4Z256rrkz + 2149056937U, // VEXTRACTF32x4Zmr + 16253353U, // VEXTRACTF32x4Zmrk + 2517647785U, // VEXTRACTF32x4Zrr + 49299881U, // VEXTRACTF32x4Zrrk + 2532327849U, // VEXTRACTF32x4Zrrkz + 2149122800U, // VEXTRACTF32x8Zmr + 16319216U, // VEXTRACTF32x8Zmrk + 2517648112U, // VEXTRACTF32x8Zrr + 49300208U, // VEXTRACTF32x8Zrrk + 2532328176U, // VEXTRACTF32x8Zrrkz + 2149056724U, // VEXTRACTF64x2Z256mr + 16253140U, // VEXTRACTF64x2Z256mrk + 2517647572U, // VEXTRACTF64x2Z256rr + 49299668U, // VEXTRACTF64x2Z256rrk + 2532327636U, // VEXTRACTF64x2Z256rrkz + 2149056724U, // VEXTRACTF64x2Zmr + 16253140U, // VEXTRACTF64x2Zmrk + 2517647572U, // VEXTRACTF64x2Zrr + 49299668U, // VEXTRACTF64x2Zrrk + 2532327636U, // VEXTRACTF64x2Zrrkz + 2149122577U, // VEXTRACTF64x4Zmr + 16318993U, // VEXTRACTF64x4Zmrk + 2517647889U, // VEXTRACTF64x4Zrr + 49299985U, // VEXTRACTF64x4Zrrk + 2532327953U, // VEXTRACTF64x4Zrrkz + 2148680379U, // VEXTRACTI128mr + 2517648059U, // VEXTRACTI128rr + 2148680163U, // VEXTRACTI32x4Z256mr + 15876579U, // VEXTRACTI32x4Z256mrk + 2517647843U, // VEXTRACTI32x4Z256rr + 49299939U, // VEXTRACTI32x4Z256rrk + 2532327907U, // VEXTRACTI32x4Z256rrkz + 2148680163U, // VEXTRACTI32x4Zmr + 15876579U, // VEXTRACTI32x4Zmrk + 2517647843U, // VEXTRACTI32x4Zrr + 49299939U, // VEXTRACTI32x4Zrrk + 2532327907U, // VEXTRACTI32x4Zrrkz + 2149155614U, // VEXTRACTI32x8Zmr + 16352030U, // VEXTRACTI32x8Zmrk + 2517648158U, // VEXTRACTI32x8Zrr + 49300254U, // VEXTRACTI32x8Zrrk + 2532328222U, // VEXTRACTI32x8Zrrkz + 2148679950U, // VEXTRACTI64x2Z256mr + 15876366U, // VEXTRACTI64x2Z256mrk + 2517647630U, // VEXTRACTI64x2Z256rr + 49299726U, // VEXTRACTI64x2Z256rrk + 2532327694U, // VEXTRACTI64x2Z256rrkz + 2148679950U, // VEXTRACTI64x2Zmr + 15876366U, // VEXTRACTI64x2Zmrk + 2517647630U, // VEXTRACTI64x2Zrr + 49299726U, // VEXTRACTI64x2Zrrk + 2532327694U, // VEXTRACTI64x2Zrrkz + 2149155391U, // VEXTRACTI64x4Zmr + 16351807U, // VEXTRACTI64x4Zmrk + 2517647935U, // VEXTRACTI64x4Zrr + 49300031U, // VEXTRACTI64x4Zrrk + 2532327999U, // VEXTRACTI64x4Zrrkz + 2148654895U, // VEXTRACTPSZmr + 2517655343U, // VEXTRACTPSZrr + 2148654895U, // VEXTRACTPSmr + 2517655343U, // VEXTRACTPSrr + 2182106074U, // VFIXUPIMMPDZ128rmbi + 49302490U, // VFIXUPIMMPDZ128rmbik + 2196786138U, // VFIXUPIMMPDZ128rmbikz + 2182106074U, // VFIXUPIMMPDZ128rmi + 49302490U, // VFIXUPIMMPDZ128rmik + 2196786138U, // VFIXUPIMMPDZ128rmikz + 2182106074U, // VFIXUPIMMPDZ128rri + 49302490U, // VFIXUPIMMPDZ128rrik + 2196786138U, // VFIXUPIMMPDZ128rrikz + 2182106074U, // VFIXUPIMMPDZ256rmbi + 49302490U, // VFIXUPIMMPDZ256rmbik + 2196786138U, // VFIXUPIMMPDZ256rmbikz + 2182106074U, // VFIXUPIMMPDZ256rmi + 49302490U, // VFIXUPIMMPDZ256rmik + 2196786138U, // VFIXUPIMMPDZ256rmikz + 2182106074U, // VFIXUPIMMPDZ256rri + 49302490U, // VFIXUPIMMPDZ256rrik + 2196786138U, // VFIXUPIMMPDZ256rrikz + 2182106074U, // VFIXUPIMMPDZrmbi + 49302490U, // VFIXUPIMMPDZrmbik + 2196786138U, // VFIXUPIMMPDZrmbikz + 2182106074U, // VFIXUPIMMPDZrmi + 49302490U, // VFIXUPIMMPDZrmik + 2196786138U, // VFIXUPIMMPDZrmikz + 2182106074U, // VFIXUPIMMPDZrri + 2182106074U, // VFIXUPIMMPDZrrib + 49302490U, // VFIXUPIMMPDZrribk + 2196786138U, // VFIXUPIMMPDZrribkz + 49302490U, // VFIXUPIMMPDZrrik + 2196786138U, // VFIXUPIMMPDZrrikz + 2182110885U, // VFIXUPIMMPSZ128rmbi + 49307301U, // VFIXUPIMMPSZ128rmbik + 2196790949U, // VFIXUPIMMPSZ128rmbikz + 2182110885U, // VFIXUPIMMPSZ128rmi + 49307301U, // VFIXUPIMMPSZ128rmik + 2196790949U, // VFIXUPIMMPSZ128rmikz + 2182110885U, // VFIXUPIMMPSZ128rri + 49307301U, // VFIXUPIMMPSZ128rrik + 2196790949U, // VFIXUPIMMPSZ128rrikz + 2182110885U, // VFIXUPIMMPSZ256rmbi + 49307301U, // VFIXUPIMMPSZ256rmbik + 2196790949U, // VFIXUPIMMPSZ256rmbikz + 2182110885U, // VFIXUPIMMPSZ256rmi + 49307301U, // VFIXUPIMMPSZ256rmik + 2196790949U, // VFIXUPIMMPSZ256rmikz + 2182110885U, // VFIXUPIMMPSZ256rri + 49307301U, // VFIXUPIMMPSZ256rrik + 2196790949U, // VFIXUPIMMPSZ256rrikz + 2182110885U, // VFIXUPIMMPSZrmbi + 49307301U, // VFIXUPIMMPSZrmbik + 2196790949U, // VFIXUPIMMPSZrmbikz + 2182110885U, // VFIXUPIMMPSZrmi + 49307301U, // VFIXUPIMMPSZrmik + 2196790949U, // VFIXUPIMMPSZrmikz + 2182110885U, // VFIXUPIMMPSZrri + 2182110885U, // VFIXUPIMMPSZrrib + 49307301U, // VFIXUPIMMPSZrribk + 2196790949U, // VFIXUPIMMPSZrribkz + 49307301U, // VFIXUPIMMPSZrrik + 2196790949U, // VFIXUPIMMPSZrrikz + 2182106849U, // VFIXUPIMMSDZrmi + 49303265U, // VFIXUPIMMSDZrmik + 2196786913U, // VFIXUPIMMSDZrmikz + 2182106849U, // VFIXUPIMMSDZrri + 2182106849U, // VFIXUPIMMSDZrrib + 49303265U, // VFIXUPIMMSDZrribk + 2196786913U, // VFIXUPIMMSDZrribkz + 49303265U, // VFIXUPIMMSDZrrik + 2196786913U, // VFIXUPIMMSDZrrikz + 2182111565U, // VFIXUPIMMSSZrmi + 49307981U, // VFIXUPIMMSSZrmik + 2196791629U, // VFIXUPIMMSSZrmikz + 2182111565U, // VFIXUPIMMSSZrri + 2182111565U, // VFIXUPIMMSSZrrib + 49307981U, // VFIXUPIMMSSZrribk + 2196791629U, // VFIXUPIMMSSZrribkz + 49307981U, // VFIXUPIMMSSZrrik + 2196791629U, // VFIXUPIMMSSZrrikz + 2182105470U, // VFMADD132PDYm + 2182105470U, // VFMADD132PDYr + 2182105470U, // VFMADD132PDZ128m + 2182105470U, // VFMADD132PDZ128mb + 49301886U, // VFMADD132PDZ128mbk + 2196785534U, // VFMADD132PDZ128mbkz + 49301886U, // VFMADD132PDZ128mk + 2196785534U, // VFMADD132PDZ128mkz + 2182105470U, // VFMADD132PDZ128r + 49301886U, // VFMADD132PDZ128rk + 2196785534U, // VFMADD132PDZ128rkz + 2182105470U, // VFMADD132PDZ256m + 2182105470U, // VFMADD132PDZ256mb + 49301886U, // VFMADD132PDZ256mbk + 2196785534U, // VFMADD132PDZ256mbkz + 49301886U, // VFMADD132PDZ256mk + 2196785534U, // VFMADD132PDZ256mkz + 2182105470U, // VFMADD132PDZ256r + 49301886U, // VFMADD132PDZ256rk + 2196785534U, // VFMADD132PDZ256rkz + 2182105470U, // VFMADD132PDZm + 2182105470U, // VFMADD132PDZmb + 49301886U, // VFMADD132PDZmbk + 2196785534U, // VFMADD132PDZmbkz + 49301886U, // VFMADD132PDZmk + 2196785534U, // VFMADD132PDZmkz + 2182105470U, // VFMADD132PDZr + 2182105470U, // VFMADD132PDZrb + 49301886U, // VFMADD132PDZrbk + 2196785534U, // VFMADD132PDZrbkz + 49301886U, // VFMADD132PDZrk + 2196785534U, // VFMADD132PDZrkz + 2182105470U, // VFMADD132PDm + 2182105470U, // VFMADD132PDr + 2182110243U, // VFMADD132PSYm + 2182110243U, // VFMADD132PSYr + 2182110243U, // VFMADD132PSZ128m + 2182110243U, // VFMADD132PSZ128mb + 49306659U, // VFMADD132PSZ128mbk + 2196790307U, // VFMADD132PSZ128mbkz + 49306659U, // VFMADD132PSZ128mk + 2196790307U, // VFMADD132PSZ128mkz + 2182110243U, // VFMADD132PSZ128r + 49306659U, // VFMADD132PSZ128rk + 2196790307U, // VFMADD132PSZ128rkz + 2182110243U, // VFMADD132PSZ256m + 2182110243U, // VFMADD132PSZ256mb + 49306659U, // VFMADD132PSZ256mbk + 2196790307U, // VFMADD132PSZ256mbkz + 49306659U, // VFMADD132PSZ256mk + 2196790307U, // VFMADD132PSZ256mkz + 2182110243U, // VFMADD132PSZ256r + 49306659U, // VFMADD132PSZ256rk + 2196790307U, // VFMADD132PSZ256rkz + 2182110243U, // VFMADD132PSZm + 2182110243U, // VFMADD132PSZmb + 49306659U, // VFMADD132PSZmbk + 2196790307U, // VFMADD132PSZmbkz + 49306659U, // VFMADD132PSZmk + 2196790307U, // VFMADD132PSZmkz + 2182110243U, // VFMADD132PSZr + 2182110243U, // VFMADD132PSZrb + 49306659U, // VFMADD132PSZrbk + 2196790307U, // VFMADD132PSZrbkz + 49306659U, // VFMADD132PSZrk + 2196790307U, // VFMADD132PSZrkz + 2182110243U, // VFMADD132PSm + 2182110243U, // VFMADD132PSr + 2182106542U, // VFMADD132SDZm + 2182106542U, // VFMADD132SDZm_Int + 49302958U, // VFMADD132SDZm_Intk + 2196786606U, // VFMADD132SDZm_Intkz + 2182106542U, // VFMADD132SDZr + 2182106542U, // VFMADD132SDZr_Int + 49302958U, // VFMADD132SDZr_Intk + 2196786606U, // VFMADD132SDZr_Intkz + 2182106542U, // VFMADD132SDZrb + 2182106542U, // VFMADD132SDZrb_Int + 49302958U, // VFMADD132SDZrb_Intk + 2196786606U, // VFMADD132SDZrb_Intkz + 2182106542U, // VFMADD132SDm + 2182106542U, // VFMADD132SDm_Int + 2182106542U, // VFMADD132SDr + 2182106542U, // VFMADD132SDr_Int + 2182111243U, // VFMADD132SSZm + 2182111243U, // VFMADD132SSZm_Int + 49307659U, // VFMADD132SSZm_Intk + 2196791307U, // VFMADD132SSZm_Intkz + 2182111243U, // VFMADD132SSZr + 2182111243U, // VFMADD132SSZr_Int + 49307659U, // VFMADD132SSZr_Intk + 2196791307U, // VFMADD132SSZr_Intkz + 2182111243U, // VFMADD132SSZrb + 2182111243U, // VFMADD132SSZrb_Int + 49307659U, // VFMADD132SSZrb_Intk + 2196791307U, // VFMADD132SSZrb_Intkz + 2182111243U, // VFMADD132SSm + 2182111243U, // VFMADD132SSm_Int + 2182111243U, // VFMADD132SSr + 2182111243U, // VFMADD132SSr_Int + 2182105666U, // VFMADD213PDYm + 2182105666U, // VFMADD213PDYr + 2182105666U, // VFMADD213PDZ128m + 2182105666U, // VFMADD213PDZ128mb + 49302082U, // VFMADD213PDZ128mbk + 2196785730U, // VFMADD213PDZ128mbkz + 49302082U, // VFMADD213PDZ128mk + 2196785730U, // VFMADD213PDZ128mkz + 2182105666U, // VFMADD213PDZ128r + 49302082U, // VFMADD213PDZ128rk + 2196785730U, // VFMADD213PDZ128rkz + 2182105666U, // VFMADD213PDZ256m + 2182105666U, // VFMADD213PDZ256mb + 49302082U, // VFMADD213PDZ256mbk + 2196785730U, // VFMADD213PDZ256mbkz + 49302082U, // VFMADD213PDZ256mk + 2196785730U, // VFMADD213PDZ256mkz + 2182105666U, // VFMADD213PDZ256r + 49302082U, // VFMADD213PDZ256rk + 2196785730U, // VFMADD213PDZ256rkz + 2182105666U, // VFMADD213PDZm + 2182105666U, // VFMADD213PDZmb + 49302082U, // VFMADD213PDZmbk + 2196785730U, // VFMADD213PDZmbkz + 49302082U, // VFMADD213PDZmk + 2196785730U, // VFMADD213PDZmkz + 2182105666U, // VFMADD213PDZr + 2182105666U, // VFMADD213PDZrb + 49302082U, // VFMADD213PDZrbk + 2196785730U, // VFMADD213PDZrbkz + 49302082U, // VFMADD213PDZrk + 2196785730U, // VFMADD213PDZrkz + 2182105666U, // VFMADD213PDm + 2182105666U, // VFMADD213PDr + 2182110450U, // VFMADD213PSYm + 2182110450U, // VFMADD213PSYr + 2182110450U, // VFMADD213PSZ128m + 2182110450U, // VFMADD213PSZ128mb + 49306866U, // VFMADD213PSZ128mbk + 2196790514U, // VFMADD213PSZ128mbkz + 49306866U, // VFMADD213PSZ128mk + 2196790514U, // VFMADD213PSZ128mkz + 2182110450U, // VFMADD213PSZ128r + 49306866U, // VFMADD213PSZ128rk + 2196790514U, // VFMADD213PSZ128rkz + 2182110450U, // VFMADD213PSZ256m + 2182110450U, // VFMADD213PSZ256mb + 49306866U, // VFMADD213PSZ256mbk + 2196790514U, // VFMADD213PSZ256mbkz + 49306866U, // VFMADD213PSZ256mk + 2196790514U, // VFMADD213PSZ256mkz + 2182110450U, // VFMADD213PSZ256r + 49306866U, // VFMADD213PSZ256rk + 2196790514U, // VFMADD213PSZ256rkz + 2182110450U, // VFMADD213PSZm + 2182110450U, // VFMADD213PSZmb + 49306866U, // VFMADD213PSZmbk + 2196790514U, // VFMADD213PSZmbkz + 49306866U, // VFMADD213PSZmk + 2196790514U, // VFMADD213PSZmkz + 2182110450U, // VFMADD213PSZr + 2182110450U, // VFMADD213PSZrb + 49306866U, // VFMADD213PSZrbk + 2196790514U, // VFMADD213PSZrbkz + 49306866U, // VFMADD213PSZrk + 2196790514U, // VFMADD213PSZrkz + 2182110450U, // VFMADD213PSm + 2182110450U, // VFMADD213PSr + 2182106630U, // VFMADD213SDZm + 2182106630U, // VFMADD213SDZm_Int + 49303046U, // VFMADD213SDZm_Intk + 2196786694U, // VFMADD213SDZm_Intkz + 2182106630U, // VFMADD213SDZr + 2182106630U, // VFMADD213SDZr_Int + 49303046U, // VFMADD213SDZr_Intk + 2196786694U, // VFMADD213SDZr_Intkz + 2182106630U, // VFMADD213SDZrb + 2182106630U, // VFMADD213SDZrb_Int + 49303046U, // VFMADD213SDZrb_Intk + 2196786694U, // VFMADD213SDZrb_Intkz + 2182106630U, // VFMADD213SDm + 2182106630U, // VFMADD213SDm_Int + 2182106630U, // VFMADD213SDr + 2182106630U, // VFMADD213SDr_Int + 2182111331U, // VFMADD213SSZm + 2182111331U, // VFMADD213SSZm_Int + 49307747U, // VFMADD213SSZm_Intk + 2196791395U, // VFMADD213SSZm_Intkz + 2182111331U, // VFMADD213SSZr + 2182111331U, // VFMADD213SSZr_Int + 49307747U, // VFMADD213SSZr_Intk + 2196791395U, // VFMADD213SSZr_Intkz + 2182111331U, // VFMADD213SSZrb + 2182111331U, // VFMADD213SSZrb_Int + 49307747U, // VFMADD213SSZrb_Intk + 2196791395U, // VFMADD213SSZrb_Intkz + 2182111331U, // VFMADD213SSm + 2182111331U, // VFMADD213SSm_Int + 2182111331U, // VFMADD213SSr + 2182111331U, // VFMADD213SSr_Int + 2182105384U, // VFMADD231PDYm + 2182105384U, // VFMADD231PDYr + 2182105384U, // VFMADD231PDZ128m + 2182105384U, // VFMADD231PDZ128mb + 49301800U, // VFMADD231PDZ128mbk + 2196785448U, // VFMADD231PDZ128mbkz + 49301800U, // VFMADD231PDZ128mk + 2196785448U, // VFMADD231PDZ128mkz + 2182105384U, // VFMADD231PDZ128r + 49301800U, // VFMADD231PDZ128rk + 2196785448U, // VFMADD231PDZ128rkz + 2182105384U, // VFMADD231PDZ256m + 2182105384U, // VFMADD231PDZ256mb + 49301800U, // VFMADD231PDZ256mbk + 2196785448U, // VFMADD231PDZ256mbkz + 49301800U, // VFMADD231PDZ256mk + 2196785448U, // VFMADD231PDZ256mkz + 2182105384U, // VFMADD231PDZ256r + 49301800U, // VFMADD231PDZ256rk + 2196785448U, // VFMADD231PDZ256rkz + 2182105384U, // VFMADD231PDZm + 2182105384U, // VFMADD231PDZmb + 49301800U, // VFMADD231PDZmbk + 2196785448U, // VFMADD231PDZmbkz + 49301800U, // VFMADD231PDZmk + 2196785448U, // VFMADD231PDZmkz + 2182105384U, // VFMADD231PDZr + 2182105384U, // VFMADD231PDZrb + 49301800U, // VFMADD231PDZrbk + 2196785448U, // VFMADD231PDZrbkz + 49301800U, // VFMADD231PDZrk + 2196785448U, // VFMADD231PDZrkz + 2182105384U, // VFMADD231PDm + 2182105384U, // VFMADD231PDr + 2182110157U, // VFMADD231PSYm + 2182110157U, // VFMADD231PSYr + 2182110157U, // VFMADD231PSZ128m + 2182110157U, // VFMADD231PSZ128mb + 49306573U, // VFMADD231PSZ128mbk + 2196790221U, // VFMADD231PSZ128mbkz + 49306573U, // VFMADD231PSZ128mk + 2196790221U, // VFMADD231PSZ128mkz + 2182110157U, // VFMADD231PSZ128r + 49306573U, // VFMADD231PSZ128rk + 2196790221U, // VFMADD231PSZ128rkz + 2182110157U, // VFMADD231PSZ256m + 2182110157U, // VFMADD231PSZ256mb + 49306573U, // VFMADD231PSZ256mbk + 2196790221U, // VFMADD231PSZ256mbkz + 49306573U, // VFMADD231PSZ256mk + 2196790221U, // VFMADD231PSZ256mkz + 2182110157U, // VFMADD231PSZ256r + 49306573U, // VFMADD231PSZ256rk + 2196790221U, // VFMADD231PSZ256rkz + 2182110157U, // VFMADD231PSZm + 2182110157U, // VFMADD231PSZmb + 49306573U, // VFMADD231PSZmbk + 2196790221U, // VFMADD231PSZmbkz + 49306573U, // VFMADD231PSZmk + 2196790221U, // VFMADD231PSZmkz + 2182110157U, // VFMADD231PSZr + 2182110157U, // VFMADD231PSZrb + 49306573U, // VFMADD231PSZrbk + 2196790221U, // VFMADD231PSZrbkz + 49306573U, // VFMADD231PSZrk + 2196790221U, // VFMADD231PSZrkz + 2182110157U, // VFMADD231PSm + 2182110157U, // VFMADD231PSr + 2182106488U, // VFMADD231SDZm + 2182106488U, // VFMADD231SDZm_Int + 49302904U, // VFMADD231SDZm_Intk + 2196786552U, // VFMADD231SDZm_Intkz + 2182106488U, // VFMADD231SDZr + 2182106488U, // VFMADD231SDZr_Int + 49302904U, // VFMADD231SDZr_Intk + 2196786552U, // VFMADD231SDZr_Intkz + 2182106488U, // VFMADD231SDZrb + 2182106488U, // VFMADD231SDZrb_Int + 49302904U, // VFMADD231SDZrb_Intk + 2196786552U, // VFMADD231SDZrb_Intkz + 2182106488U, // VFMADD231SDm + 2182106488U, // VFMADD231SDm_Int + 2182106488U, // VFMADD231SDr + 2182106488U, // VFMADD231SDr_Int + 2182111189U, // VFMADD231SSZm + 2182111189U, // VFMADD231SSZm_Int + 49307605U, // VFMADD231SSZm_Intk + 2196791253U, // VFMADD231SSZm_Intkz + 2182111189U, // VFMADD231SSZr + 2182111189U, // VFMADD231SSZr_Int + 49307605U, // VFMADD231SSZr_Intk + 2196791253U, // VFMADD231SSZr_Intkz + 2182111189U, // VFMADD231SSZrb + 2182111189U, // VFMADD231SSZrb_Int + 49307605U, // VFMADD231SSZrb_Intk + 2196791253U, // VFMADD231SSZrb_Intkz + 2182111189U, // VFMADD231SSm + 2182111189U, // VFMADD231SSm_Int + 2182111189U, // VFMADD231SSr + 2182111189U, // VFMADD231SSr_Int + 2517650158U, // VFMADDPD4Ymr + 2517650158U, // VFMADDPD4Yrm + 2517650158U, // VFMADDPD4Yrr + 2517650158U, // VFMADDPD4Yrr_REV + 2517650158U, // VFMADDPD4mr + 2517650158U, // VFMADDPD4rm + 2517650158U, // VFMADDPD4rr + 2517650158U, // VFMADDPD4rr_REV + 2517654945U, // VFMADDPS4Ymr + 2517654945U, // VFMADDPS4Yrm + 2517654945U, // VFMADDPS4Yrr + 2517654945U, // VFMADDPS4Yrr_REV + 2517654945U, // VFMADDPS4mr + 2517654945U, // VFMADDPS4rm + 2517654945U, // VFMADDPS4rr + 2517654945U, // VFMADDPS4rr_REV + 2517651058U, // VFMADDSD4mr + 2517651058U, // VFMADDSD4mr_Int + 2517651058U, // VFMADDSD4rm + 2517651058U, // VFMADDSD4rm_Int + 2517651058U, // VFMADDSD4rr + 2517651058U, // VFMADDSD4rr_Int + 2517651058U, // VFMADDSD4rr_Int_REV + 2517651058U, // VFMADDSD4rr_REV + 2517655762U, // VFMADDSS4mr + 2517655762U, // VFMADDSS4mr_Int + 2517655762U, // VFMADDSS4rm + 2517655762U, // VFMADDSS4rm_Int + 2517655762U, // VFMADDSS4rr + 2517655762U, // VFMADDSS4rr_Int + 2517655762U, // VFMADDSS4rr_Int_REV + 2517655762U, // VFMADDSS4rr_REV + 2182105411U, // VFMADDSUB132PDYm + 2182105411U, // VFMADDSUB132PDYr + 2182105411U, // VFMADDSUB132PDZ128m + 2182105411U, // VFMADDSUB132PDZ128mb + 49301827U, // VFMADDSUB132PDZ128mbk + 2196785475U, // VFMADDSUB132PDZ128mbkz + 49301827U, // VFMADDSUB132PDZ128mk + 2196785475U, // VFMADDSUB132PDZ128mkz + 2182105411U, // VFMADDSUB132PDZ128r + 49301827U, // VFMADDSUB132PDZ128rk + 2196785475U, // VFMADDSUB132PDZ128rkz + 2182105411U, // VFMADDSUB132PDZ256m + 2182105411U, // VFMADDSUB132PDZ256mb + 49301827U, // VFMADDSUB132PDZ256mbk + 2196785475U, // VFMADDSUB132PDZ256mbkz + 49301827U, // VFMADDSUB132PDZ256mk + 2196785475U, // VFMADDSUB132PDZ256mkz + 2182105411U, // VFMADDSUB132PDZ256r + 49301827U, // VFMADDSUB132PDZ256rk + 2196785475U, // VFMADDSUB132PDZ256rkz + 2182105411U, // VFMADDSUB132PDZm + 2182105411U, // VFMADDSUB132PDZmb + 49301827U, // VFMADDSUB132PDZmbk + 2196785475U, // VFMADDSUB132PDZmbkz + 49301827U, // VFMADDSUB132PDZmk + 2196785475U, // VFMADDSUB132PDZmkz + 2182105411U, // VFMADDSUB132PDZr + 2182105411U, // VFMADDSUB132PDZrb + 49301827U, // VFMADDSUB132PDZrbk + 2196785475U, // VFMADDSUB132PDZrbkz + 49301827U, // VFMADDSUB132PDZrk + 2196785475U, // VFMADDSUB132PDZrkz + 2182105411U, // VFMADDSUB132PDm + 2182105411U, // VFMADDSUB132PDr + 2182110184U, // VFMADDSUB132PSYm + 2182110184U, // VFMADDSUB132PSYr + 2182110184U, // VFMADDSUB132PSZ128m + 2182110184U, // VFMADDSUB132PSZ128mb + 49306600U, // VFMADDSUB132PSZ128mbk + 2196790248U, // VFMADDSUB132PSZ128mbkz + 49306600U, // VFMADDSUB132PSZ128mk + 2196790248U, // VFMADDSUB132PSZ128mkz + 2182110184U, // VFMADDSUB132PSZ128r + 49306600U, // VFMADDSUB132PSZ128rk + 2196790248U, // VFMADDSUB132PSZ128rkz + 2182110184U, // VFMADDSUB132PSZ256m + 2182110184U, // VFMADDSUB132PSZ256mb + 49306600U, // VFMADDSUB132PSZ256mbk + 2196790248U, // VFMADDSUB132PSZ256mbkz + 49306600U, // VFMADDSUB132PSZ256mk + 2196790248U, // VFMADDSUB132PSZ256mkz + 2182110184U, // VFMADDSUB132PSZ256r + 49306600U, // VFMADDSUB132PSZ256rk + 2196790248U, // VFMADDSUB132PSZ256rkz + 2182110184U, // VFMADDSUB132PSZm + 2182110184U, // VFMADDSUB132PSZmb + 49306600U, // VFMADDSUB132PSZmbk + 2196790248U, // VFMADDSUB132PSZmbkz + 49306600U, // VFMADDSUB132PSZmk + 2196790248U, // VFMADDSUB132PSZmkz + 2182110184U, // VFMADDSUB132PSZr + 2182110184U, // VFMADDSUB132PSZrb + 49306600U, // VFMADDSUB132PSZrbk + 2196790248U, // VFMADDSUB132PSZrbkz + 49306600U, // VFMADDSUB132PSZrk + 2196790248U, // VFMADDSUB132PSZrkz + 2182110184U, // VFMADDSUB132PSm + 2182110184U, // VFMADDSUB132PSr + 2182105607U, // VFMADDSUB213PDYm + 2182105607U, // VFMADDSUB213PDYr + 2182105607U, // VFMADDSUB213PDZ128m + 2182105607U, // VFMADDSUB213PDZ128mb + 49302023U, // VFMADDSUB213PDZ128mbk + 2196785671U, // VFMADDSUB213PDZ128mbkz + 49302023U, // VFMADDSUB213PDZ128mk + 2196785671U, // VFMADDSUB213PDZ128mkz + 2182105607U, // VFMADDSUB213PDZ128r + 49302023U, // VFMADDSUB213PDZ128rk + 2196785671U, // VFMADDSUB213PDZ128rkz + 2182105607U, // VFMADDSUB213PDZ256m + 2182105607U, // VFMADDSUB213PDZ256mb + 49302023U, // VFMADDSUB213PDZ256mbk + 2196785671U, // VFMADDSUB213PDZ256mbkz + 49302023U, // VFMADDSUB213PDZ256mk + 2196785671U, // VFMADDSUB213PDZ256mkz + 2182105607U, // VFMADDSUB213PDZ256r + 49302023U, // VFMADDSUB213PDZ256rk + 2196785671U, // VFMADDSUB213PDZ256rkz + 2182105607U, // VFMADDSUB213PDZm + 2182105607U, // VFMADDSUB213PDZmb + 49302023U, // VFMADDSUB213PDZmbk + 2196785671U, // VFMADDSUB213PDZmbkz + 49302023U, // VFMADDSUB213PDZmk + 2196785671U, // VFMADDSUB213PDZmkz + 2182105607U, // VFMADDSUB213PDZr + 2182105607U, // VFMADDSUB213PDZrb + 49302023U, // VFMADDSUB213PDZrbk + 2196785671U, // VFMADDSUB213PDZrbkz + 49302023U, // VFMADDSUB213PDZrk + 2196785671U, // VFMADDSUB213PDZrkz + 2182105607U, // VFMADDSUB213PDm + 2182105607U, // VFMADDSUB213PDr + 2182110391U, // VFMADDSUB213PSYm + 2182110391U, // VFMADDSUB213PSYr + 2182110391U, // VFMADDSUB213PSZ128m + 2182110391U, // VFMADDSUB213PSZ128mb + 49306807U, // VFMADDSUB213PSZ128mbk + 2196790455U, // VFMADDSUB213PSZ128mbkz + 49306807U, // VFMADDSUB213PSZ128mk + 2196790455U, // VFMADDSUB213PSZ128mkz + 2182110391U, // VFMADDSUB213PSZ128r + 49306807U, // VFMADDSUB213PSZ128rk + 2196790455U, // VFMADDSUB213PSZ128rkz + 2182110391U, // VFMADDSUB213PSZ256m + 2182110391U, // VFMADDSUB213PSZ256mb + 49306807U, // VFMADDSUB213PSZ256mbk + 2196790455U, // VFMADDSUB213PSZ256mbkz + 49306807U, // VFMADDSUB213PSZ256mk + 2196790455U, // VFMADDSUB213PSZ256mkz + 2182110391U, // VFMADDSUB213PSZ256r + 49306807U, // VFMADDSUB213PSZ256rk + 2196790455U, // VFMADDSUB213PSZ256rkz + 2182110391U, // VFMADDSUB213PSZm + 2182110391U, // VFMADDSUB213PSZmb + 49306807U, // VFMADDSUB213PSZmbk + 2196790455U, // VFMADDSUB213PSZmbkz + 49306807U, // VFMADDSUB213PSZmk + 2196790455U, // VFMADDSUB213PSZmkz + 2182110391U, // VFMADDSUB213PSZr + 2182110391U, // VFMADDSUB213PSZrb + 49306807U, // VFMADDSUB213PSZrbk + 2196790455U, // VFMADDSUB213PSZrbkz + 49306807U, // VFMADDSUB213PSZrk + 2196790455U, // VFMADDSUB213PSZrkz + 2182110391U, // VFMADDSUB213PSm + 2182110391U, // VFMADDSUB213PSr + 2182105325U, // VFMADDSUB231PDYm + 2182105325U, // VFMADDSUB231PDYr + 2182105325U, // VFMADDSUB231PDZ128m + 2182105325U, // VFMADDSUB231PDZ128mb + 49301741U, // VFMADDSUB231PDZ128mbk + 2196785389U, // VFMADDSUB231PDZ128mbkz + 49301741U, // VFMADDSUB231PDZ128mk + 2196785389U, // VFMADDSUB231PDZ128mkz + 2182105325U, // VFMADDSUB231PDZ128r + 49301741U, // VFMADDSUB231PDZ128rk + 2196785389U, // VFMADDSUB231PDZ128rkz + 2182105325U, // VFMADDSUB231PDZ256m + 2182105325U, // VFMADDSUB231PDZ256mb + 49301741U, // VFMADDSUB231PDZ256mbk + 2196785389U, // VFMADDSUB231PDZ256mbkz + 49301741U, // VFMADDSUB231PDZ256mk + 2196785389U, // VFMADDSUB231PDZ256mkz + 2182105325U, // VFMADDSUB231PDZ256r + 49301741U, // VFMADDSUB231PDZ256rk + 2196785389U, // VFMADDSUB231PDZ256rkz + 2182105325U, // VFMADDSUB231PDZm + 2182105325U, // VFMADDSUB231PDZmb + 49301741U, // VFMADDSUB231PDZmbk + 2196785389U, // VFMADDSUB231PDZmbkz + 49301741U, // VFMADDSUB231PDZmk + 2196785389U, // VFMADDSUB231PDZmkz + 2182105325U, // VFMADDSUB231PDZr + 2182105325U, // VFMADDSUB231PDZrb + 49301741U, // VFMADDSUB231PDZrbk + 2196785389U, // VFMADDSUB231PDZrbkz + 49301741U, // VFMADDSUB231PDZrk + 2196785389U, // VFMADDSUB231PDZrkz + 2182105325U, // VFMADDSUB231PDm + 2182105325U, // VFMADDSUB231PDr + 2182110098U, // VFMADDSUB231PSYm + 2182110098U, // VFMADDSUB231PSYr + 2182110098U, // VFMADDSUB231PSZ128m + 2182110098U, // VFMADDSUB231PSZ128mb + 49306514U, // VFMADDSUB231PSZ128mbk + 2196790162U, // VFMADDSUB231PSZ128mbkz + 49306514U, // VFMADDSUB231PSZ128mk + 2196790162U, // VFMADDSUB231PSZ128mkz + 2182110098U, // VFMADDSUB231PSZ128r + 49306514U, // VFMADDSUB231PSZ128rk + 2196790162U, // VFMADDSUB231PSZ128rkz + 2182110098U, // VFMADDSUB231PSZ256m + 2182110098U, // VFMADDSUB231PSZ256mb + 49306514U, // VFMADDSUB231PSZ256mbk + 2196790162U, // VFMADDSUB231PSZ256mbkz + 49306514U, // VFMADDSUB231PSZ256mk + 2196790162U, // VFMADDSUB231PSZ256mkz + 2182110098U, // VFMADDSUB231PSZ256r + 49306514U, // VFMADDSUB231PSZ256rk + 2196790162U, // VFMADDSUB231PSZ256rkz + 2182110098U, // VFMADDSUB231PSZm + 2182110098U, // VFMADDSUB231PSZmb + 49306514U, // VFMADDSUB231PSZmbk + 2196790162U, // VFMADDSUB231PSZmbkz + 49306514U, // VFMADDSUB231PSZmk + 2196790162U, // VFMADDSUB231PSZmkz + 2182110098U, // VFMADDSUB231PSZr + 2182110098U, // VFMADDSUB231PSZrb + 49306514U, // VFMADDSUB231PSZrbk + 2196790162U, // VFMADDSUB231PSZrbkz + 49306514U, // VFMADDSUB231PSZrk + 2196790162U, // VFMADDSUB231PSZrkz + 2182110098U, // VFMADDSUB231PSm + 2182110098U, // VFMADDSUB231PSr + 2517650074U, // VFMADDSUBPD4Ymr + 2517650074U, // VFMADDSUBPD4Yrm + 2517650074U, // VFMADDSUBPD4Yrr + 2517650074U, // VFMADDSUBPD4Yrr_REV + 2517650074U, // VFMADDSUBPD4mr + 2517650074U, // VFMADDSUBPD4rm + 2517650074U, // VFMADDSUBPD4rr + 2517650074U, // VFMADDSUBPD4rr_REV + 2517654850U, // VFMADDSUBPS4Ymr + 2517654850U, // VFMADDSUBPS4Yrm + 2517654850U, // VFMADDSUBPS4Yrr + 2517654850U, // VFMADDSUBPS4Yrr_REV + 2517654850U, // VFMADDSUBPS4mr + 2517654850U, // VFMADDSUBPS4rm + 2517654850U, // VFMADDSUBPS4rr + 2517654850U, // VFMADDSUBPS4rr_REV + 2182105427U, // VFMSUB132PDYm + 2182105427U, // VFMSUB132PDYr + 2182105427U, // VFMSUB132PDZ128m + 2182105427U, // VFMSUB132PDZ128mb + 49301843U, // VFMSUB132PDZ128mbk + 2196785491U, // VFMSUB132PDZ128mbkz + 49301843U, // VFMSUB132PDZ128mk + 2196785491U, // VFMSUB132PDZ128mkz + 2182105427U, // VFMSUB132PDZ128r + 49301843U, // VFMSUB132PDZ128rk + 2196785491U, // VFMSUB132PDZ128rkz + 2182105427U, // VFMSUB132PDZ256m + 2182105427U, // VFMSUB132PDZ256mb + 49301843U, // VFMSUB132PDZ256mbk + 2196785491U, // VFMSUB132PDZ256mbkz + 49301843U, // VFMSUB132PDZ256mk + 2196785491U, // VFMSUB132PDZ256mkz + 2182105427U, // VFMSUB132PDZ256r + 49301843U, // VFMSUB132PDZ256rk + 2196785491U, // VFMSUB132PDZ256rkz + 2182105427U, // VFMSUB132PDZm + 2182105427U, // VFMSUB132PDZmb + 49301843U, // VFMSUB132PDZmbk + 2196785491U, // VFMSUB132PDZmbkz + 49301843U, // VFMSUB132PDZmk + 2196785491U, // VFMSUB132PDZmkz + 2182105427U, // VFMSUB132PDZr + 2182105427U, // VFMSUB132PDZrb + 49301843U, // VFMSUB132PDZrbk + 2196785491U, // VFMSUB132PDZrbkz + 49301843U, // VFMSUB132PDZrk + 2196785491U, // VFMSUB132PDZrkz + 2182105427U, // VFMSUB132PDm + 2182105427U, // VFMSUB132PDr + 2182110200U, // VFMSUB132PSYm + 2182110200U, // VFMSUB132PSYr + 2182110200U, // VFMSUB132PSZ128m + 2182110200U, // VFMSUB132PSZ128mb + 49306616U, // VFMSUB132PSZ128mbk + 2196790264U, // VFMSUB132PSZ128mbkz + 49306616U, // VFMSUB132PSZ128mk + 2196790264U, // VFMSUB132PSZ128mkz + 2182110200U, // VFMSUB132PSZ128r + 49306616U, // VFMSUB132PSZ128rk + 2196790264U, // VFMSUB132PSZ128rkz + 2182110200U, // VFMSUB132PSZ256m + 2182110200U, // VFMSUB132PSZ256mb + 49306616U, // VFMSUB132PSZ256mbk + 2196790264U, // VFMSUB132PSZ256mbkz + 49306616U, // VFMSUB132PSZ256mk + 2196790264U, // VFMSUB132PSZ256mkz + 2182110200U, // VFMSUB132PSZ256r + 49306616U, // VFMSUB132PSZ256rk + 2196790264U, // VFMSUB132PSZ256rkz + 2182110200U, // VFMSUB132PSZm + 2182110200U, // VFMSUB132PSZmb + 49306616U, // VFMSUB132PSZmbk + 2196790264U, // VFMSUB132PSZmbkz + 49306616U, // VFMSUB132PSZmk + 2196790264U, // VFMSUB132PSZmkz + 2182110200U, // VFMSUB132PSZr + 2182110200U, // VFMSUB132PSZrb + 49306616U, // VFMSUB132PSZrbk + 2196790264U, // VFMSUB132PSZrbkz + 49306616U, // VFMSUB132PSZrk + 2196790264U, // VFMSUB132PSZrkz + 2182110200U, // VFMSUB132PSm + 2182110200U, // VFMSUB132PSr + 2182106515U, // VFMSUB132SDZm + 2182106515U, // VFMSUB132SDZm_Int + 49302931U, // VFMSUB132SDZm_Intk + 2196786579U, // VFMSUB132SDZm_Intkz + 2182106515U, // VFMSUB132SDZr + 2182106515U, // VFMSUB132SDZr_Int + 49302931U, // VFMSUB132SDZr_Intk + 2196786579U, // VFMSUB132SDZr_Intkz + 2182106515U, // VFMSUB132SDZrb + 2182106515U, // VFMSUB132SDZrb_Int + 49302931U, // VFMSUB132SDZrb_Intk + 2196786579U, // VFMSUB132SDZrb_Intkz + 2182106515U, // VFMSUB132SDm + 2182106515U, // VFMSUB132SDm_Int + 2182106515U, // VFMSUB132SDr + 2182106515U, // VFMSUB132SDr_Int + 2182111216U, // VFMSUB132SSZm + 2182111216U, // VFMSUB132SSZm_Int + 49307632U, // VFMSUB132SSZm_Intk + 2196791280U, // VFMSUB132SSZm_Intkz + 2182111216U, // VFMSUB132SSZr + 2182111216U, // VFMSUB132SSZr_Int + 49307632U, // VFMSUB132SSZr_Intk + 2196791280U, // VFMSUB132SSZr_Intkz + 2182111216U, // VFMSUB132SSZrb + 2182111216U, // VFMSUB132SSZrb_Int + 49307632U, // VFMSUB132SSZrb_Intk + 2196791280U, // VFMSUB132SSZrb_Intkz + 2182111216U, // VFMSUB132SSm + 2182111216U, // VFMSUB132SSm_Int + 2182111216U, // VFMSUB132SSr + 2182111216U, // VFMSUB132SSr_Int + 2182105623U, // VFMSUB213PDYm + 2182105623U, // VFMSUB213PDYr + 2182105623U, // VFMSUB213PDZ128m + 2182105623U, // VFMSUB213PDZ128mb + 49302039U, // VFMSUB213PDZ128mbk + 2196785687U, // VFMSUB213PDZ128mbkz + 49302039U, // VFMSUB213PDZ128mk + 2196785687U, // VFMSUB213PDZ128mkz + 2182105623U, // VFMSUB213PDZ128r + 49302039U, // VFMSUB213PDZ128rk + 2196785687U, // VFMSUB213PDZ128rkz + 2182105623U, // VFMSUB213PDZ256m + 2182105623U, // VFMSUB213PDZ256mb + 49302039U, // VFMSUB213PDZ256mbk + 2196785687U, // VFMSUB213PDZ256mbkz + 49302039U, // VFMSUB213PDZ256mk + 2196785687U, // VFMSUB213PDZ256mkz + 2182105623U, // VFMSUB213PDZ256r + 49302039U, // VFMSUB213PDZ256rk + 2196785687U, // VFMSUB213PDZ256rkz + 2182105623U, // VFMSUB213PDZm + 2182105623U, // VFMSUB213PDZmb + 49302039U, // VFMSUB213PDZmbk + 2196785687U, // VFMSUB213PDZmbkz + 49302039U, // VFMSUB213PDZmk + 2196785687U, // VFMSUB213PDZmkz + 2182105623U, // VFMSUB213PDZr + 2182105623U, // VFMSUB213PDZrb + 49302039U, // VFMSUB213PDZrbk + 2196785687U, // VFMSUB213PDZrbkz + 49302039U, // VFMSUB213PDZrk + 2196785687U, // VFMSUB213PDZrkz + 2182105623U, // VFMSUB213PDm + 2182105623U, // VFMSUB213PDr + 2182110407U, // VFMSUB213PSYm + 2182110407U, // VFMSUB213PSYr + 2182110407U, // VFMSUB213PSZ128m + 2182110407U, // VFMSUB213PSZ128mb + 49306823U, // VFMSUB213PSZ128mbk + 2196790471U, // VFMSUB213PSZ128mbkz + 49306823U, // VFMSUB213PSZ128mk + 2196790471U, // VFMSUB213PSZ128mkz + 2182110407U, // VFMSUB213PSZ128r + 49306823U, // VFMSUB213PSZ128rk + 2196790471U, // VFMSUB213PSZ128rkz + 2182110407U, // VFMSUB213PSZ256m + 2182110407U, // VFMSUB213PSZ256mb + 49306823U, // VFMSUB213PSZ256mbk + 2196790471U, // VFMSUB213PSZ256mbkz + 49306823U, // VFMSUB213PSZ256mk + 2196790471U, // VFMSUB213PSZ256mkz + 2182110407U, // VFMSUB213PSZ256r + 49306823U, // VFMSUB213PSZ256rk + 2196790471U, // VFMSUB213PSZ256rkz + 2182110407U, // VFMSUB213PSZm + 2182110407U, // VFMSUB213PSZmb + 49306823U, // VFMSUB213PSZmbk + 2196790471U, // VFMSUB213PSZmbkz + 49306823U, // VFMSUB213PSZmk + 2196790471U, // VFMSUB213PSZmkz + 2182110407U, // VFMSUB213PSZr + 2182110407U, // VFMSUB213PSZrb + 49306823U, // VFMSUB213PSZrbk + 2196790471U, // VFMSUB213PSZrbkz + 49306823U, // VFMSUB213PSZrk + 2196790471U, // VFMSUB213PSZrkz + 2182110407U, // VFMSUB213PSm + 2182110407U, // VFMSUB213PSr + 2182106603U, // VFMSUB213SDZm + 2182106603U, // VFMSUB213SDZm_Int + 49303019U, // VFMSUB213SDZm_Intk + 2196786667U, // VFMSUB213SDZm_Intkz + 2182106603U, // VFMSUB213SDZr + 2182106603U, // VFMSUB213SDZr_Int + 49303019U, // VFMSUB213SDZr_Intk + 2196786667U, // VFMSUB213SDZr_Intkz + 2182106603U, // VFMSUB213SDZrb + 2182106603U, // VFMSUB213SDZrb_Int + 49303019U, // VFMSUB213SDZrb_Intk + 2196786667U, // VFMSUB213SDZrb_Intkz + 2182106603U, // VFMSUB213SDm + 2182106603U, // VFMSUB213SDm_Int + 2182106603U, // VFMSUB213SDr + 2182106603U, // VFMSUB213SDr_Int + 2182111304U, // VFMSUB213SSZm + 2182111304U, // VFMSUB213SSZm_Int + 49307720U, // VFMSUB213SSZm_Intk + 2196791368U, // VFMSUB213SSZm_Intkz + 2182111304U, // VFMSUB213SSZr + 2182111304U, // VFMSUB213SSZr_Int + 49307720U, // VFMSUB213SSZr_Intk + 2196791368U, // VFMSUB213SSZr_Intkz + 2182111304U, // VFMSUB213SSZrb + 2182111304U, // VFMSUB213SSZrb_Int + 49307720U, // VFMSUB213SSZrb_Intk + 2196791368U, // VFMSUB213SSZrb_Intkz + 2182111304U, // VFMSUB213SSm + 2182111304U, // VFMSUB213SSm_Int + 2182111304U, // VFMSUB213SSr + 2182111304U, // VFMSUB213SSr_Int + 2182105341U, // VFMSUB231PDYm + 2182105341U, // VFMSUB231PDYr + 2182105341U, // VFMSUB231PDZ128m + 2182105341U, // VFMSUB231PDZ128mb + 49301757U, // VFMSUB231PDZ128mbk + 2196785405U, // VFMSUB231PDZ128mbkz + 49301757U, // VFMSUB231PDZ128mk + 2196785405U, // VFMSUB231PDZ128mkz + 2182105341U, // VFMSUB231PDZ128r + 49301757U, // VFMSUB231PDZ128rk + 2196785405U, // VFMSUB231PDZ128rkz + 2182105341U, // VFMSUB231PDZ256m + 2182105341U, // VFMSUB231PDZ256mb + 49301757U, // VFMSUB231PDZ256mbk + 2196785405U, // VFMSUB231PDZ256mbkz + 49301757U, // VFMSUB231PDZ256mk + 2196785405U, // VFMSUB231PDZ256mkz + 2182105341U, // VFMSUB231PDZ256r + 49301757U, // VFMSUB231PDZ256rk + 2196785405U, // VFMSUB231PDZ256rkz + 2182105341U, // VFMSUB231PDZm + 2182105341U, // VFMSUB231PDZmb + 49301757U, // VFMSUB231PDZmbk + 2196785405U, // VFMSUB231PDZmbkz + 49301757U, // VFMSUB231PDZmk + 2196785405U, // VFMSUB231PDZmkz + 2182105341U, // VFMSUB231PDZr + 2182105341U, // VFMSUB231PDZrb + 49301757U, // VFMSUB231PDZrbk + 2196785405U, // VFMSUB231PDZrbkz + 49301757U, // VFMSUB231PDZrk + 2196785405U, // VFMSUB231PDZrkz + 2182105341U, // VFMSUB231PDm + 2182105341U, // VFMSUB231PDr + 2182110114U, // VFMSUB231PSYm + 2182110114U, // VFMSUB231PSYr + 2182110114U, // VFMSUB231PSZ128m + 2182110114U, // VFMSUB231PSZ128mb + 49306530U, // VFMSUB231PSZ128mbk + 2196790178U, // VFMSUB231PSZ128mbkz + 49306530U, // VFMSUB231PSZ128mk + 2196790178U, // VFMSUB231PSZ128mkz + 2182110114U, // VFMSUB231PSZ128r + 49306530U, // VFMSUB231PSZ128rk + 2196790178U, // VFMSUB231PSZ128rkz + 2182110114U, // VFMSUB231PSZ256m + 2182110114U, // VFMSUB231PSZ256mb + 49306530U, // VFMSUB231PSZ256mbk + 2196790178U, // VFMSUB231PSZ256mbkz + 49306530U, // VFMSUB231PSZ256mk + 2196790178U, // VFMSUB231PSZ256mkz + 2182110114U, // VFMSUB231PSZ256r + 49306530U, // VFMSUB231PSZ256rk + 2196790178U, // VFMSUB231PSZ256rkz + 2182110114U, // VFMSUB231PSZm + 2182110114U, // VFMSUB231PSZmb + 49306530U, // VFMSUB231PSZmbk + 2196790178U, // VFMSUB231PSZmbkz + 49306530U, // VFMSUB231PSZmk + 2196790178U, // VFMSUB231PSZmkz + 2182110114U, // VFMSUB231PSZr + 2182110114U, // VFMSUB231PSZrb + 49306530U, // VFMSUB231PSZrbk + 2196790178U, // VFMSUB231PSZrbkz + 49306530U, // VFMSUB231PSZrk + 2196790178U, // VFMSUB231PSZrkz + 2182110114U, // VFMSUB231PSm + 2182110114U, // VFMSUB231PSr + 2182106461U, // VFMSUB231SDZm + 2182106461U, // VFMSUB231SDZm_Int + 49302877U, // VFMSUB231SDZm_Intk + 2196786525U, // VFMSUB231SDZm_Intkz + 2182106461U, // VFMSUB231SDZr + 2182106461U, // VFMSUB231SDZr_Int + 49302877U, // VFMSUB231SDZr_Intk + 2196786525U, // VFMSUB231SDZr_Intkz + 2182106461U, // VFMSUB231SDZrb + 2182106461U, // VFMSUB231SDZrb_Int + 49302877U, // VFMSUB231SDZrb_Intk + 2196786525U, // VFMSUB231SDZrb_Intkz + 2182106461U, // VFMSUB231SDm + 2182106461U, // VFMSUB231SDm_Int + 2182106461U, // VFMSUB231SDr + 2182106461U, // VFMSUB231SDr_Int + 2182111162U, // VFMSUB231SSZm + 2182111162U, // VFMSUB231SSZm_Int + 49307578U, // VFMSUB231SSZm_Intk + 2196791226U, // VFMSUB231SSZm_Intkz + 2182111162U, // VFMSUB231SSZr + 2182111162U, // VFMSUB231SSZr_Int + 49307578U, // VFMSUB231SSZr_Intk + 2196791226U, // VFMSUB231SSZr_Intkz + 2182111162U, // VFMSUB231SSZrb + 2182111162U, // VFMSUB231SSZrb_Int + 49307578U, // VFMSUB231SSZrb_Intk + 2196791226U, // VFMSUB231SSZrb_Intkz + 2182111162U, // VFMSUB231SSm + 2182111162U, // VFMSUB231SSm_Int + 2182111162U, // VFMSUB231SSr + 2182111162U, // VFMSUB231SSr_Int + 2182105454U, // VFMSUBADD132PDYm + 2182105454U, // VFMSUBADD132PDYr + 2182105454U, // VFMSUBADD132PDZ128m + 2182105454U, // VFMSUBADD132PDZ128mb + 49301870U, // VFMSUBADD132PDZ128mbk + 2196785518U, // VFMSUBADD132PDZ128mbkz + 49301870U, // VFMSUBADD132PDZ128mk + 2196785518U, // VFMSUBADD132PDZ128mkz + 2182105454U, // VFMSUBADD132PDZ128r + 49301870U, // VFMSUBADD132PDZ128rk + 2196785518U, // VFMSUBADD132PDZ128rkz + 2182105454U, // VFMSUBADD132PDZ256m + 2182105454U, // VFMSUBADD132PDZ256mb + 49301870U, // VFMSUBADD132PDZ256mbk + 2196785518U, // VFMSUBADD132PDZ256mbkz + 49301870U, // VFMSUBADD132PDZ256mk + 2196785518U, // VFMSUBADD132PDZ256mkz + 2182105454U, // VFMSUBADD132PDZ256r + 49301870U, // VFMSUBADD132PDZ256rk + 2196785518U, // VFMSUBADD132PDZ256rkz + 2182105454U, // VFMSUBADD132PDZm + 2182105454U, // VFMSUBADD132PDZmb + 49301870U, // VFMSUBADD132PDZmbk + 2196785518U, // VFMSUBADD132PDZmbkz + 49301870U, // VFMSUBADD132PDZmk + 2196785518U, // VFMSUBADD132PDZmkz + 2182105454U, // VFMSUBADD132PDZr + 2182105454U, // VFMSUBADD132PDZrb + 49301870U, // VFMSUBADD132PDZrbk + 2196785518U, // VFMSUBADD132PDZrbkz + 49301870U, // VFMSUBADD132PDZrk + 2196785518U, // VFMSUBADD132PDZrkz + 2182105454U, // VFMSUBADD132PDm + 2182105454U, // VFMSUBADD132PDr + 2182110227U, // VFMSUBADD132PSYm + 2182110227U, // VFMSUBADD132PSYr + 2182110227U, // VFMSUBADD132PSZ128m + 2182110227U, // VFMSUBADD132PSZ128mb + 49306643U, // VFMSUBADD132PSZ128mbk + 2196790291U, // VFMSUBADD132PSZ128mbkz + 49306643U, // VFMSUBADD132PSZ128mk + 2196790291U, // VFMSUBADD132PSZ128mkz + 2182110227U, // VFMSUBADD132PSZ128r + 49306643U, // VFMSUBADD132PSZ128rk + 2196790291U, // VFMSUBADD132PSZ128rkz + 2182110227U, // VFMSUBADD132PSZ256m + 2182110227U, // VFMSUBADD132PSZ256mb + 49306643U, // VFMSUBADD132PSZ256mbk + 2196790291U, // VFMSUBADD132PSZ256mbkz + 49306643U, // VFMSUBADD132PSZ256mk + 2196790291U, // VFMSUBADD132PSZ256mkz + 2182110227U, // VFMSUBADD132PSZ256r + 49306643U, // VFMSUBADD132PSZ256rk + 2196790291U, // VFMSUBADD132PSZ256rkz + 2182110227U, // VFMSUBADD132PSZm + 2182110227U, // VFMSUBADD132PSZmb + 49306643U, // VFMSUBADD132PSZmbk + 2196790291U, // VFMSUBADD132PSZmbkz + 49306643U, // VFMSUBADD132PSZmk + 2196790291U, // VFMSUBADD132PSZmkz + 2182110227U, // VFMSUBADD132PSZr + 2182110227U, // VFMSUBADD132PSZrb + 49306643U, // VFMSUBADD132PSZrbk + 2196790291U, // VFMSUBADD132PSZrbkz + 49306643U, // VFMSUBADD132PSZrk + 2196790291U, // VFMSUBADD132PSZrkz + 2182110227U, // VFMSUBADD132PSm + 2182110227U, // VFMSUBADD132PSr + 2182105650U, // VFMSUBADD213PDYm + 2182105650U, // VFMSUBADD213PDYr + 2182105650U, // VFMSUBADD213PDZ128m + 2182105650U, // VFMSUBADD213PDZ128mb + 49302066U, // VFMSUBADD213PDZ128mbk + 2196785714U, // VFMSUBADD213PDZ128mbkz + 49302066U, // VFMSUBADD213PDZ128mk + 2196785714U, // VFMSUBADD213PDZ128mkz + 2182105650U, // VFMSUBADD213PDZ128r + 49302066U, // VFMSUBADD213PDZ128rk + 2196785714U, // VFMSUBADD213PDZ128rkz + 2182105650U, // VFMSUBADD213PDZ256m + 2182105650U, // VFMSUBADD213PDZ256mb + 49302066U, // VFMSUBADD213PDZ256mbk + 2196785714U, // VFMSUBADD213PDZ256mbkz + 49302066U, // VFMSUBADD213PDZ256mk + 2196785714U, // VFMSUBADD213PDZ256mkz + 2182105650U, // VFMSUBADD213PDZ256r + 49302066U, // VFMSUBADD213PDZ256rk + 2196785714U, // VFMSUBADD213PDZ256rkz + 2182105650U, // VFMSUBADD213PDZm + 2182105650U, // VFMSUBADD213PDZmb + 49302066U, // VFMSUBADD213PDZmbk + 2196785714U, // VFMSUBADD213PDZmbkz + 49302066U, // VFMSUBADD213PDZmk + 2196785714U, // VFMSUBADD213PDZmkz + 2182105650U, // VFMSUBADD213PDZr + 2182105650U, // VFMSUBADD213PDZrb + 49302066U, // VFMSUBADD213PDZrbk + 2196785714U, // VFMSUBADD213PDZrbkz + 49302066U, // VFMSUBADD213PDZrk + 2196785714U, // VFMSUBADD213PDZrkz + 2182105650U, // VFMSUBADD213PDm + 2182105650U, // VFMSUBADD213PDr + 2182110434U, // VFMSUBADD213PSYm + 2182110434U, // VFMSUBADD213PSYr + 2182110434U, // VFMSUBADD213PSZ128m + 2182110434U, // VFMSUBADD213PSZ128mb + 49306850U, // VFMSUBADD213PSZ128mbk + 2196790498U, // VFMSUBADD213PSZ128mbkz + 49306850U, // VFMSUBADD213PSZ128mk + 2196790498U, // VFMSUBADD213PSZ128mkz + 2182110434U, // VFMSUBADD213PSZ128r + 49306850U, // VFMSUBADD213PSZ128rk + 2196790498U, // VFMSUBADD213PSZ128rkz + 2182110434U, // VFMSUBADD213PSZ256m + 2182110434U, // VFMSUBADD213PSZ256mb + 49306850U, // VFMSUBADD213PSZ256mbk + 2196790498U, // VFMSUBADD213PSZ256mbkz + 49306850U, // VFMSUBADD213PSZ256mk + 2196790498U, // VFMSUBADD213PSZ256mkz + 2182110434U, // VFMSUBADD213PSZ256r + 49306850U, // VFMSUBADD213PSZ256rk + 2196790498U, // VFMSUBADD213PSZ256rkz + 2182110434U, // VFMSUBADD213PSZm + 2182110434U, // VFMSUBADD213PSZmb + 49306850U, // VFMSUBADD213PSZmbk + 2196790498U, // VFMSUBADD213PSZmbkz + 49306850U, // VFMSUBADD213PSZmk + 2196790498U, // VFMSUBADD213PSZmkz + 2182110434U, // VFMSUBADD213PSZr + 2182110434U, // VFMSUBADD213PSZrb + 49306850U, // VFMSUBADD213PSZrbk + 2196790498U, // VFMSUBADD213PSZrbkz + 49306850U, // VFMSUBADD213PSZrk + 2196790498U, // VFMSUBADD213PSZrkz + 2182110434U, // VFMSUBADD213PSm + 2182110434U, // VFMSUBADD213PSr + 2182105368U, // VFMSUBADD231PDYm + 2182105368U, // VFMSUBADD231PDYr + 2182105368U, // VFMSUBADD231PDZ128m + 2182105368U, // VFMSUBADD231PDZ128mb + 49301784U, // VFMSUBADD231PDZ128mbk + 2196785432U, // VFMSUBADD231PDZ128mbkz + 49301784U, // VFMSUBADD231PDZ128mk + 2196785432U, // VFMSUBADD231PDZ128mkz + 2182105368U, // VFMSUBADD231PDZ128r + 49301784U, // VFMSUBADD231PDZ128rk + 2196785432U, // VFMSUBADD231PDZ128rkz + 2182105368U, // VFMSUBADD231PDZ256m + 2182105368U, // VFMSUBADD231PDZ256mb + 49301784U, // VFMSUBADD231PDZ256mbk + 2196785432U, // VFMSUBADD231PDZ256mbkz + 49301784U, // VFMSUBADD231PDZ256mk + 2196785432U, // VFMSUBADD231PDZ256mkz + 2182105368U, // VFMSUBADD231PDZ256r + 49301784U, // VFMSUBADD231PDZ256rk + 2196785432U, // VFMSUBADD231PDZ256rkz + 2182105368U, // VFMSUBADD231PDZm + 2182105368U, // VFMSUBADD231PDZmb + 49301784U, // VFMSUBADD231PDZmbk + 2196785432U, // VFMSUBADD231PDZmbkz + 49301784U, // VFMSUBADD231PDZmk + 2196785432U, // VFMSUBADD231PDZmkz + 2182105368U, // VFMSUBADD231PDZr + 2182105368U, // VFMSUBADD231PDZrb + 49301784U, // VFMSUBADD231PDZrbk + 2196785432U, // VFMSUBADD231PDZrbkz + 49301784U, // VFMSUBADD231PDZrk + 2196785432U, // VFMSUBADD231PDZrkz + 2182105368U, // VFMSUBADD231PDm + 2182105368U, // VFMSUBADD231PDr + 2182110141U, // VFMSUBADD231PSYm + 2182110141U, // VFMSUBADD231PSYr + 2182110141U, // VFMSUBADD231PSZ128m + 2182110141U, // VFMSUBADD231PSZ128mb + 49306557U, // VFMSUBADD231PSZ128mbk + 2196790205U, // VFMSUBADD231PSZ128mbkz + 49306557U, // VFMSUBADD231PSZ128mk + 2196790205U, // VFMSUBADD231PSZ128mkz + 2182110141U, // VFMSUBADD231PSZ128r + 49306557U, // VFMSUBADD231PSZ128rk + 2196790205U, // VFMSUBADD231PSZ128rkz + 2182110141U, // VFMSUBADD231PSZ256m + 2182110141U, // VFMSUBADD231PSZ256mb + 49306557U, // VFMSUBADD231PSZ256mbk + 2196790205U, // VFMSUBADD231PSZ256mbkz + 49306557U, // VFMSUBADD231PSZ256mk + 2196790205U, // VFMSUBADD231PSZ256mkz + 2182110141U, // VFMSUBADD231PSZ256r + 49306557U, // VFMSUBADD231PSZ256rk + 2196790205U, // VFMSUBADD231PSZ256rkz + 2182110141U, // VFMSUBADD231PSZm + 2182110141U, // VFMSUBADD231PSZmb + 49306557U, // VFMSUBADD231PSZmbk + 2196790205U, // VFMSUBADD231PSZmbkz + 49306557U, // VFMSUBADD231PSZmk + 2196790205U, // VFMSUBADD231PSZmkz + 2182110141U, // VFMSUBADD231PSZr + 2182110141U, // VFMSUBADD231PSZrb + 49306557U, // VFMSUBADD231PSZrbk + 2196790205U, // VFMSUBADD231PSZrbkz + 49306557U, // VFMSUBADD231PSZrk + 2196790205U, // VFMSUBADD231PSZrkz + 2182110141U, // VFMSUBADD231PSm + 2182110141U, // VFMSUBADD231PSr + 2517650136U, // VFMSUBADDPD4Ymr + 2517650136U, // VFMSUBADDPD4Yrm + 2517650136U, // VFMSUBADDPD4Yrr + 2517650136U, // VFMSUBADDPD4Yrr_REV + 2517650136U, // VFMSUBADDPD4mr + 2517650136U, // VFMSUBADDPD4rm + 2517650136U, // VFMSUBADDPD4rr + 2517650136U, // VFMSUBADDPD4rr_REV + 2517654912U, // VFMSUBADDPS4Ymr + 2517654912U, // VFMSUBADDPS4Yrm + 2517654912U, // VFMSUBADDPS4Yrr + 2517654912U, // VFMSUBADDPS4Yrr_REV + 2517654912U, // VFMSUBADDPS4mr + 2517654912U, // VFMSUBADDPS4rm + 2517654912U, // VFMSUBADDPS4rr + 2517654912U, // VFMSUBADDPS4rr_REV + 2517650107U, // VFMSUBPD4Ymr + 2517650107U, // VFMSUBPD4Yrm + 2517650107U, // VFMSUBPD4Yrr + 2517650107U, // VFMSUBPD4Yrr_REV + 2517650107U, // VFMSUBPD4mr + 2517650107U, // VFMSUBPD4rm + 2517650107U, // VFMSUBPD4rr + 2517650107U, // VFMSUBPD4rr_REV + 2517654883U, // VFMSUBPS4Ymr + 2517654883U, // VFMSUBPS4Yrm + 2517654883U, // VFMSUBPS4Yrr + 2517654883U, // VFMSUBPS4Yrr_REV + 2517654883U, // VFMSUBPS4mr + 2517654883U, // VFMSUBPS4rm + 2517654883U, // VFMSUBPS4rr + 2517654883U, // VFMSUBPS4rr_REV + 2517651029U, // VFMSUBSD4mr + 2517651029U, // VFMSUBSD4mr_Int + 2517651029U, // VFMSUBSD4rm + 2517651029U, // VFMSUBSD4rm_Int + 2517651029U, // VFMSUBSD4rr + 2517651029U, // VFMSUBSD4rr_Int + 2517651029U, // VFMSUBSD4rr_Int_REV + 2517651029U, // VFMSUBSD4rr_REV + 2517655722U, // VFMSUBSS4mr + 2517655722U, // VFMSUBSS4mr_Int + 2517655722U, // VFMSUBSS4rm + 2517655722U, // VFMSUBSS4rm_Int + 2517655722U, // VFMSUBSS4rr + 2517655722U, // VFMSUBSS4rr_Int + 2517655722U, // VFMSUBSS4rr_Int_REV + 2517655722U, // VFMSUBSS4rr_REV + 2182105483U, // VFNMADD132PDYm + 2182105483U, // VFNMADD132PDYr + 2182105483U, // VFNMADD132PDZ128m + 2182105483U, // VFNMADD132PDZ128mb + 49301899U, // VFNMADD132PDZ128mbk + 2196785547U, // VFNMADD132PDZ128mbkz + 49301899U, // VFNMADD132PDZ128mk + 2196785547U, // VFNMADD132PDZ128mkz + 2182105483U, // VFNMADD132PDZ128r + 49301899U, // VFNMADD132PDZ128rk + 2196785547U, // VFNMADD132PDZ128rkz + 2182105483U, // VFNMADD132PDZ256m + 2182105483U, // VFNMADD132PDZ256mb + 49301899U, // VFNMADD132PDZ256mbk + 2196785547U, // VFNMADD132PDZ256mbkz + 49301899U, // VFNMADD132PDZ256mk + 2196785547U, // VFNMADD132PDZ256mkz + 2182105483U, // VFNMADD132PDZ256r + 49301899U, // VFNMADD132PDZ256rk + 2196785547U, // VFNMADD132PDZ256rkz + 2182105483U, // VFNMADD132PDZm + 2182105483U, // VFNMADD132PDZmb + 49301899U, // VFNMADD132PDZmbk + 2196785547U, // VFNMADD132PDZmbkz + 49301899U, // VFNMADD132PDZmk + 2196785547U, // VFNMADD132PDZmkz + 2182105483U, // VFNMADD132PDZr + 2182105483U, // VFNMADD132PDZrb + 49301899U, // VFNMADD132PDZrbk + 2196785547U, // VFNMADD132PDZrbkz + 49301899U, // VFNMADD132PDZrk + 2196785547U, // VFNMADD132PDZrkz + 2182105483U, // VFNMADD132PDm + 2182105483U, // VFNMADD132PDr + 2182110256U, // VFNMADD132PSYm + 2182110256U, // VFNMADD132PSYr + 2182110256U, // VFNMADD132PSZ128m + 2182110256U, // VFNMADD132PSZ128mb + 49306672U, // VFNMADD132PSZ128mbk + 2196790320U, // VFNMADD132PSZ128mbkz + 49306672U, // VFNMADD132PSZ128mk + 2196790320U, // VFNMADD132PSZ128mkz + 2182110256U, // VFNMADD132PSZ128r + 49306672U, // VFNMADD132PSZ128rk + 2196790320U, // VFNMADD132PSZ128rkz + 2182110256U, // VFNMADD132PSZ256m + 2182110256U, // VFNMADD132PSZ256mb + 49306672U, // VFNMADD132PSZ256mbk + 2196790320U, // VFNMADD132PSZ256mbkz + 49306672U, // VFNMADD132PSZ256mk + 2196790320U, // VFNMADD132PSZ256mkz + 2182110256U, // VFNMADD132PSZ256r + 49306672U, // VFNMADD132PSZ256rk + 2196790320U, // VFNMADD132PSZ256rkz + 2182110256U, // VFNMADD132PSZm + 2182110256U, // VFNMADD132PSZmb + 49306672U, // VFNMADD132PSZmbk + 2196790320U, // VFNMADD132PSZmbkz + 49306672U, // VFNMADD132PSZmk + 2196790320U, // VFNMADD132PSZmkz + 2182110256U, // VFNMADD132PSZr + 2182110256U, // VFNMADD132PSZrb + 49306672U, // VFNMADD132PSZrbk + 2196790320U, // VFNMADD132PSZrbkz + 49306672U, // VFNMADD132PSZrk + 2196790320U, // VFNMADD132PSZrkz + 2182110256U, // VFNMADD132PSm + 2182110256U, // VFNMADD132PSr + 2182106555U, // VFNMADD132SDZm + 2182106555U, // VFNMADD132SDZm_Int + 49302971U, // VFNMADD132SDZm_Intk + 2196786619U, // VFNMADD132SDZm_Intkz + 2182106555U, // VFNMADD132SDZr + 2182106555U, // VFNMADD132SDZr_Int + 49302971U, // VFNMADD132SDZr_Intk + 2196786619U, // VFNMADD132SDZr_Intkz + 2182106555U, // VFNMADD132SDZrb + 2182106555U, // VFNMADD132SDZrb_Int + 49302971U, // VFNMADD132SDZrb_Intk + 2196786619U, // VFNMADD132SDZrb_Intkz + 2182106555U, // VFNMADD132SDm + 2182106555U, // VFNMADD132SDm_Int + 2182106555U, // VFNMADD132SDr + 2182106555U, // VFNMADD132SDr_Int + 2182111256U, // VFNMADD132SSZm + 2182111256U, // VFNMADD132SSZm_Int + 49307672U, // VFNMADD132SSZm_Intk + 2196791320U, // VFNMADD132SSZm_Intkz + 2182111256U, // VFNMADD132SSZr + 2182111256U, // VFNMADD132SSZr_Int + 49307672U, // VFNMADD132SSZr_Intk + 2196791320U, // VFNMADD132SSZr_Intkz + 2182111256U, // VFNMADD132SSZrb + 2182111256U, // VFNMADD132SSZrb_Int + 49307672U, // VFNMADD132SSZrb_Intk + 2196791320U, // VFNMADD132SSZrb_Intkz + 2182111256U, // VFNMADD132SSm + 2182111256U, // VFNMADD132SSm_Int + 2182111256U, // VFNMADD132SSr + 2182111256U, // VFNMADD132SSr_Int + 2182105679U, // VFNMADD213PDYm + 2182105679U, // VFNMADD213PDYr + 2182105679U, // VFNMADD213PDZ128m + 2182105679U, // VFNMADD213PDZ128mb + 49302095U, // VFNMADD213PDZ128mbk + 2196785743U, // VFNMADD213PDZ128mbkz + 49302095U, // VFNMADD213PDZ128mk + 2196785743U, // VFNMADD213PDZ128mkz + 2182105679U, // VFNMADD213PDZ128r + 49302095U, // VFNMADD213PDZ128rk + 2196785743U, // VFNMADD213PDZ128rkz + 2182105679U, // VFNMADD213PDZ256m + 2182105679U, // VFNMADD213PDZ256mb + 49302095U, // VFNMADD213PDZ256mbk + 2196785743U, // VFNMADD213PDZ256mbkz + 49302095U, // VFNMADD213PDZ256mk + 2196785743U, // VFNMADD213PDZ256mkz + 2182105679U, // VFNMADD213PDZ256r + 49302095U, // VFNMADD213PDZ256rk + 2196785743U, // VFNMADD213PDZ256rkz + 2182105679U, // VFNMADD213PDZm + 2182105679U, // VFNMADD213PDZmb + 49302095U, // VFNMADD213PDZmbk + 2196785743U, // VFNMADD213PDZmbkz + 49302095U, // VFNMADD213PDZmk + 2196785743U, // VFNMADD213PDZmkz + 2182105679U, // VFNMADD213PDZr + 2182105679U, // VFNMADD213PDZrb + 49302095U, // VFNMADD213PDZrbk + 2196785743U, // VFNMADD213PDZrbkz + 49302095U, // VFNMADD213PDZrk + 2196785743U, // VFNMADD213PDZrkz + 2182105679U, // VFNMADD213PDm + 2182105679U, // VFNMADD213PDr + 2182110463U, // VFNMADD213PSYm + 2182110463U, // VFNMADD213PSYr + 2182110463U, // VFNMADD213PSZ128m + 2182110463U, // VFNMADD213PSZ128mb + 49306879U, // VFNMADD213PSZ128mbk + 2196790527U, // VFNMADD213PSZ128mbkz + 49306879U, // VFNMADD213PSZ128mk + 2196790527U, // VFNMADD213PSZ128mkz + 2182110463U, // VFNMADD213PSZ128r + 49306879U, // VFNMADD213PSZ128rk + 2196790527U, // VFNMADD213PSZ128rkz + 2182110463U, // VFNMADD213PSZ256m + 2182110463U, // VFNMADD213PSZ256mb + 49306879U, // VFNMADD213PSZ256mbk + 2196790527U, // VFNMADD213PSZ256mbkz + 49306879U, // VFNMADD213PSZ256mk + 2196790527U, // VFNMADD213PSZ256mkz + 2182110463U, // VFNMADD213PSZ256r + 49306879U, // VFNMADD213PSZ256rk + 2196790527U, // VFNMADD213PSZ256rkz + 2182110463U, // VFNMADD213PSZm + 2182110463U, // VFNMADD213PSZmb + 49306879U, // VFNMADD213PSZmbk + 2196790527U, // VFNMADD213PSZmbkz + 49306879U, // VFNMADD213PSZmk + 2196790527U, // VFNMADD213PSZmkz + 2182110463U, // VFNMADD213PSZr + 2182110463U, // VFNMADD213PSZrb + 49306879U, // VFNMADD213PSZrbk + 2196790527U, // VFNMADD213PSZrbkz + 49306879U, // VFNMADD213PSZrk + 2196790527U, // VFNMADD213PSZrkz + 2182110463U, // VFNMADD213PSm + 2182110463U, // VFNMADD213PSr + 2182106643U, // VFNMADD213SDZm + 2182106643U, // VFNMADD213SDZm_Int + 49303059U, // VFNMADD213SDZm_Intk + 2196786707U, // VFNMADD213SDZm_Intkz + 2182106643U, // VFNMADD213SDZr + 2182106643U, // VFNMADD213SDZr_Int + 49303059U, // VFNMADD213SDZr_Intk + 2196786707U, // VFNMADD213SDZr_Intkz + 2182106643U, // VFNMADD213SDZrb + 2182106643U, // VFNMADD213SDZrb_Int + 49303059U, // VFNMADD213SDZrb_Intk + 2196786707U, // VFNMADD213SDZrb_Intkz + 2182106643U, // VFNMADD213SDm + 2182106643U, // VFNMADD213SDm_Int + 2182106643U, // VFNMADD213SDr + 2182106643U, // VFNMADD213SDr_Int + 2182111344U, // VFNMADD213SSZm + 2182111344U, // VFNMADD213SSZm_Int + 49307760U, // VFNMADD213SSZm_Intk + 2196791408U, // VFNMADD213SSZm_Intkz + 2182111344U, // VFNMADD213SSZr + 2182111344U, // VFNMADD213SSZr_Int + 49307760U, // VFNMADD213SSZr_Intk + 2196791408U, // VFNMADD213SSZr_Intkz + 2182111344U, // VFNMADD213SSZrb + 2182111344U, // VFNMADD213SSZrb_Int + 49307760U, // VFNMADD213SSZrb_Intk + 2196791408U, // VFNMADD213SSZrb_Intkz + 2182111344U, // VFNMADD213SSm + 2182111344U, // VFNMADD213SSm_Int + 2182111344U, // VFNMADD213SSr + 2182111344U, // VFNMADD213SSr_Int + 2182105397U, // VFNMADD231PDYm + 2182105397U, // VFNMADD231PDYr + 2182105397U, // VFNMADD231PDZ128m + 2182105397U, // VFNMADD231PDZ128mb + 49301813U, // VFNMADD231PDZ128mbk + 2196785461U, // VFNMADD231PDZ128mbkz + 49301813U, // VFNMADD231PDZ128mk + 2196785461U, // VFNMADD231PDZ128mkz + 2182105397U, // VFNMADD231PDZ128r + 49301813U, // VFNMADD231PDZ128rk + 2196785461U, // VFNMADD231PDZ128rkz + 2182105397U, // VFNMADD231PDZ256m + 2182105397U, // VFNMADD231PDZ256mb + 49301813U, // VFNMADD231PDZ256mbk + 2196785461U, // VFNMADD231PDZ256mbkz + 49301813U, // VFNMADD231PDZ256mk + 2196785461U, // VFNMADD231PDZ256mkz + 2182105397U, // VFNMADD231PDZ256r + 49301813U, // VFNMADD231PDZ256rk + 2196785461U, // VFNMADD231PDZ256rkz + 2182105397U, // VFNMADD231PDZm + 2182105397U, // VFNMADD231PDZmb + 49301813U, // VFNMADD231PDZmbk + 2196785461U, // VFNMADD231PDZmbkz + 49301813U, // VFNMADD231PDZmk + 2196785461U, // VFNMADD231PDZmkz + 2182105397U, // VFNMADD231PDZr + 2182105397U, // VFNMADD231PDZrb + 49301813U, // VFNMADD231PDZrbk + 2196785461U, // VFNMADD231PDZrbkz + 49301813U, // VFNMADD231PDZrk + 2196785461U, // VFNMADD231PDZrkz + 2182105397U, // VFNMADD231PDm + 2182105397U, // VFNMADD231PDr + 2182110170U, // VFNMADD231PSYm + 2182110170U, // VFNMADD231PSYr + 2182110170U, // VFNMADD231PSZ128m + 2182110170U, // VFNMADD231PSZ128mb + 49306586U, // VFNMADD231PSZ128mbk + 2196790234U, // VFNMADD231PSZ128mbkz + 49306586U, // VFNMADD231PSZ128mk + 2196790234U, // VFNMADD231PSZ128mkz + 2182110170U, // VFNMADD231PSZ128r + 49306586U, // VFNMADD231PSZ128rk + 2196790234U, // VFNMADD231PSZ128rkz + 2182110170U, // VFNMADD231PSZ256m + 2182110170U, // VFNMADD231PSZ256mb + 49306586U, // VFNMADD231PSZ256mbk + 2196790234U, // VFNMADD231PSZ256mbkz + 49306586U, // VFNMADD231PSZ256mk + 2196790234U, // VFNMADD231PSZ256mkz + 2182110170U, // VFNMADD231PSZ256r + 49306586U, // VFNMADD231PSZ256rk + 2196790234U, // VFNMADD231PSZ256rkz + 2182110170U, // VFNMADD231PSZm + 2182110170U, // VFNMADD231PSZmb + 49306586U, // VFNMADD231PSZmbk + 2196790234U, // VFNMADD231PSZmbkz + 49306586U, // VFNMADD231PSZmk + 2196790234U, // VFNMADD231PSZmkz + 2182110170U, // VFNMADD231PSZr + 2182110170U, // VFNMADD231PSZrb + 49306586U, // VFNMADD231PSZrbk + 2196790234U, // VFNMADD231PSZrbkz + 49306586U, // VFNMADD231PSZrk + 2196790234U, // VFNMADD231PSZrkz + 2182110170U, // VFNMADD231PSm + 2182110170U, // VFNMADD231PSr + 2182106501U, // VFNMADD231SDZm + 2182106501U, // VFNMADD231SDZm_Int + 49302917U, // VFNMADD231SDZm_Intk + 2196786565U, // VFNMADD231SDZm_Intkz + 2182106501U, // VFNMADD231SDZr + 2182106501U, // VFNMADD231SDZr_Int + 49302917U, // VFNMADD231SDZr_Intk + 2196786565U, // VFNMADD231SDZr_Intkz + 2182106501U, // VFNMADD231SDZrb + 2182106501U, // VFNMADD231SDZrb_Int + 49302917U, // VFNMADD231SDZrb_Intk + 2196786565U, // VFNMADD231SDZrb_Intkz + 2182106501U, // VFNMADD231SDm + 2182106501U, // VFNMADD231SDm_Int + 2182106501U, // VFNMADD231SDr + 2182106501U, // VFNMADD231SDr_Int + 2182111202U, // VFNMADD231SSZm + 2182111202U, // VFNMADD231SSZm_Int + 49307618U, // VFNMADD231SSZm_Intk + 2196791266U, // VFNMADD231SSZm_Intkz + 2182111202U, // VFNMADD231SSZr + 2182111202U, // VFNMADD231SSZr_Int + 49307618U, // VFNMADD231SSZr_Intk + 2196791266U, // VFNMADD231SSZr_Intkz + 2182111202U, // VFNMADD231SSZrb + 2182111202U, // VFNMADD231SSZrb_Int + 49307618U, // VFNMADD231SSZrb_Intk + 2196791266U, // VFNMADD231SSZrb_Intkz + 2182111202U, // VFNMADD231SSm + 2182111202U, // VFNMADD231SSm_Int + 2182111202U, // VFNMADD231SSr + 2182111202U, // VFNMADD231SSr_Int + 2517650168U, // VFNMADDPD4Ymr + 2517650168U, // VFNMADDPD4Yrm + 2517650168U, // VFNMADDPD4Yrr + 2517650168U, // VFNMADDPD4Yrr_REV + 2517650168U, // VFNMADDPD4mr + 2517650168U, // VFNMADDPD4rm + 2517650168U, // VFNMADDPD4rr + 2517650168U, // VFNMADDPD4rr_REV + 2517654967U, // VFNMADDPS4Ymr + 2517654967U, // VFNMADDPS4Yrm + 2517654967U, // VFNMADDPS4Yrr + 2517654967U, // VFNMADDPS4Yrr_REV + 2517654967U, // VFNMADDPS4mr + 2517654967U, // VFNMADDPS4rm + 2517654967U, // VFNMADDPS4rr + 2517654967U, // VFNMADDPS4rr_REV + 2517651068U, // VFNMADDSD4mr + 2517651068U, // VFNMADDSD4mr_Int + 2517651068U, // VFNMADDSD4rm + 2517651068U, // VFNMADDSD4rm_Int + 2517651068U, // VFNMADDSD4rr + 2517651068U, // VFNMADDSD4rr_Int + 2517651068U, // VFNMADDSD4rr_Int_REV + 2517651068U, // VFNMADDSD4rr_REV + 2517655784U, // VFNMADDSS4mr + 2517655784U, // VFNMADDSS4mr_Int + 2517655784U, // VFNMADDSS4rm + 2517655784U, // VFNMADDSS4rm_Int + 2517655784U, // VFNMADDSS4rr + 2517655784U, // VFNMADDSS4rr_Int + 2517655784U, // VFNMADDSS4rr_Int_REV + 2517655784U, // VFNMADDSS4rr_REV + 2182105440U, // VFNMSUB132PDYm + 2182105440U, // VFNMSUB132PDYr + 2182105440U, // VFNMSUB132PDZ128m + 2182105440U, // VFNMSUB132PDZ128mb + 49301856U, // VFNMSUB132PDZ128mbk + 2196785504U, // VFNMSUB132PDZ128mbkz + 49301856U, // VFNMSUB132PDZ128mk + 2196785504U, // VFNMSUB132PDZ128mkz + 2182105440U, // VFNMSUB132PDZ128r + 49301856U, // VFNMSUB132PDZ128rk + 2196785504U, // VFNMSUB132PDZ128rkz + 2182105440U, // VFNMSUB132PDZ256m + 2182105440U, // VFNMSUB132PDZ256mb + 49301856U, // VFNMSUB132PDZ256mbk + 2196785504U, // VFNMSUB132PDZ256mbkz + 49301856U, // VFNMSUB132PDZ256mk + 2196785504U, // VFNMSUB132PDZ256mkz + 2182105440U, // VFNMSUB132PDZ256r + 49301856U, // VFNMSUB132PDZ256rk + 2196785504U, // VFNMSUB132PDZ256rkz + 2182105440U, // VFNMSUB132PDZm + 2182105440U, // VFNMSUB132PDZmb + 49301856U, // VFNMSUB132PDZmbk + 2196785504U, // VFNMSUB132PDZmbkz + 49301856U, // VFNMSUB132PDZmk + 2196785504U, // VFNMSUB132PDZmkz + 2182105440U, // VFNMSUB132PDZr + 2182105440U, // VFNMSUB132PDZrb + 49301856U, // VFNMSUB132PDZrbk + 2196785504U, // VFNMSUB132PDZrbkz + 49301856U, // VFNMSUB132PDZrk + 2196785504U, // VFNMSUB132PDZrkz + 2182105440U, // VFNMSUB132PDm + 2182105440U, // VFNMSUB132PDr + 2182110213U, // VFNMSUB132PSYm + 2182110213U, // VFNMSUB132PSYr + 2182110213U, // VFNMSUB132PSZ128m + 2182110213U, // VFNMSUB132PSZ128mb + 49306629U, // VFNMSUB132PSZ128mbk + 2196790277U, // VFNMSUB132PSZ128mbkz + 49306629U, // VFNMSUB132PSZ128mk + 2196790277U, // VFNMSUB132PSZ128mkz + 2182110213U, // VFNMSUB132PSZ128r + 49306629U, // VFNMSUB132PSZ128rk + 2196790277U, // VFNMSUB132PSZ128rkz + 2182110213U, // VFNMSUB132PSZ256m + 2182110213U, // VFNMSUB132PSZ256mb + 49306629U, // VFNMSUB132PSZ256mbk + 2196790277U, // VFNMSUB132PSZ256mbkz + 49306629U, // VFNMSUB132PSZ256mk + 2196790277U, // VFNMSUB132PSZ256mkz + 2182110213U, // VFNMSUB132PSZ256r + 49306629U, // VFNMSUB132PSZ256rk + 2196790277U, // VFNMSUB132PSZ256rkz + 2182110213U, // VFNMSUB132PSZm + 2182110213U, // VFNMSUB132PSZmb + 49306629U, // VFNMSUB132PSZmbk + 2196790277U, // VFNMSUB132PSZmbkz + 49306629U, // VFNMSUB132PSZmk + 2196790277U, // VFNMSUB132PSZmkz + 2182110213U, // VFNMSUB132PSZr + 2182110213U, // VFNMSUB132PSZrb + 49306629U, // VFNMSUB132PSZrbk + 2196790277U, // VFNMSUB132PSZrbkz + 49306629U, // VFNMSUB132PSZrk + 2196790277U, // VFNMSUB132PSZrkz + 2182110213U, // VFNMSUB132PSm + 2182110213U, // VFNMSUB132PSr + 2182106528U, // VFNMSUB132SDZm + 2182106528U, // VFNMSUB132SDZm_Int + 49302944U, // VFNMSUB132SDZm_Intk + 2196786592U, // VFNMSUB132SDZm_Intkz + 2182106528U, // VFNMSUB132SDZr + 2182106528U, // VFNMSUB132SDZr_Int + 49302944U, // VFNMSUB132SDZr_Intk + 2196786592U, // VFNMSUB132SDZr_Intkz + 2182106528U, // VFNMSUB132SDZrb + 2182106528U, // VFNMSUB132SDZrb_Int + 49302944U, // VFNMSUB132SDZrb_Intk + 2196786592U, // VFNMSUB132SDZrb_Intkz + 2182106528U, // VFNMSUB132SDm + 2182106528U, // VFNMSUB132SDm_Int + 2182106528U, // VFNMSUB132SDr + 2182106528U, // VFNMSUB132SDr_Int + 2182111229U, // VFNMSUB132SSZm + 2182111229U, // VFNMSUB132SSZm_Int + 49307645U, // VFNMSUB132SSZm_Intk + 2196791293U, // VFNMSUB132SSZm_Intkz + 2182111229U, // VFNMSUB132SSZr + 2182111229U, // VFNMSUB132SSZr_Int + 49307645U, // VFNMSUB132SSZr_Intk + 2196791293U, // VFNMSUB132SSZr_Intkz + 2182111229U, // VFNMSUB132SSZrb + 2182111229U, // VFNMSUB132SSZrb_Int + 49307645U, // VFNMSUB132SSZrb_Intk + 2196791293U, // VFNMSUB132SSZrb_Intkz + 2182111229U, // VFNMSUB132SSm + 2182111229U, // VFNMSUB132SSm_Int + 2182111229U, // VFNMSUB132SSr + 2182111229U, // VFNMSUB132SSr_Int + 2182105636U, // VFNMSUB213PDYm + 2182105636U, // VFNMSUB213PDYr + 2182105636U, // VFNMSUB213PDZ128m + 2182105636U, // VFNMSUB213PDZ128mb + 49302052U, // VFNMSUB213PDZ128mbk + 2196785700U, // VFNMSUB213PDZ128mbkz + 49302052U, // VFNMSUB213PDZ128mk + 2196785700U, // VFNMSUB213PDZ128mkz + 2182105636U, // VFNMSUB213PDZ128r + 49302052U, // VFNMSUB213PDZ128rk + 2196785700U, // VFNMSUB213PDZ128rkz + 2182105636U, // VFNMSUB213PDZ256m + 2182105636U, // VFNMSUB213PDZ256mb + 49302052U, // VFNMSUB213PDZ256mbk + 2196785700U, // VFNMSUB213PDZ256mbkz + 49302052U, // VFNMSUB213PDZ256mk + 2196785700U, // VFNMSUB213PDZ256mkz + 2182105636U, // VFNMSUB213PDZ256r + 49302052U, // VFNMSUB213PDZ256rk + 2196785700U, // VFNMSUB213PDZ256rkz + 2182105636U, // VFNMSUB213PDZm + 2182105636U, // VFNMSUB213PDZmb + 49302052U, // VFNMSUB213PDZmbk + 2196785700U, // VFNMSUB213PDZmbkz + 49302052U, // VFNMSUB213PDZmk + 2196785700U, // VFNMSUB213PDZmkz + 2182105636U, // VFNMSUB213PDZr + 2182105636U, // VFNMSUB213PDZrb + 49302052U, // VFNMSUB213PDZrbk + 2196785700U, // VFNMSUB213PDZrbkz + 49302052U, // VFNMSUB213PDZrk + 2196785700U, // VFNMSUB213PDZrkz + 2182105636U, // VFNMSUB213PDm + 2182105636U, // VFNMSUB213PDr + 2182110420U, // VFNMSUB213PSYm + 2182110420U, // VFNMSUB213PSYr + 2182110420U, // VFNMSUB213PSZ128m + 2182110420U, // VFNMSUB213PSZ128mb + 49306836U, // VFNMSUB213PSZ128mbk + 2196790484U, // VFNMSUB213PSZ128mbkz + 49306836U, // VFNMSUB213PSZ128mk + 2196790484U, // VFNMSUB213PSZ128mkz + 2182110420U, // VFNMSUB213PSZ128r + 49306836U, // VFNMSUB213PSZ128rk + 2196790484U, // VFNMSUB213PSZ128rkz + 2182110420U, // VFNMSUB213PSZ256m + 2182110420U, // VFNMSUB213PSZ256mb + 49306836U, // VFNMSUB213PSZ256mbk + 2196790484U, // VFNMSUB213PSZ256mbkz + 49306836U, // VFNMSUB213PSZ256mk + 2196790484U, // VFNMSUB213PSZ256mkz + 2182110420U, // VFNMSUB213PSZ256r + 49306836U, // VFNMSUB213PSZ256rk + 2196790484U, // VFNMSUB213PSZ256rkz + 2182110420U, // VFNMSUB213PSZm + 2182110420U, // VFNMSUB213PSZmb + 49306836U, // VFNMSUB213PSZmbk + 2196790484U, // VFNMSUB213PSZmbkz + 49306836U, // VFNMSUB213PSZmk + 2196790484U, // VFNMSUB213PSZmkz + 2182110420U, // VFNMSUB213PSZr + 2182110420U, // VFNMSUB213PSZrb + 49306836U, // VFNMSUB213PSZrbk + 2196790484U, // VFNMSUB213PSZrbkz + 49306836U, // VFNMSUB213PSZrk + 2196790484U, // VFNMSUB213PSZrkz + 2182110420U, // VFNMSUB213PSm + 2182110420U, // VFNMSUB213PSr + 2182106616U, // VFNMSUB213SDZm + 2182106616U, // VFNMSUB213SDZm_Int + 49303032U, // VFNMSUB213SDZm_Intk + 2196786680U, // VFNMSUB213SDZm_Intkz + 2182106616U, // VFNMSUB213SDZr + 2182106616U, // VFNMSUB213SDZr_Int + 49303032U, // VFNMSUB213SDZr_Intk + 2196786680U, // VFNMSUB213SDZr_Intkz + 2182106616U, // VFNMSUB213SDZrb + 2182106616U, // VFNMSUB213SDZrb_Int + 49303032U, // VFNMSUB213SDZrb_Intk + 2196786680U, // VFNMSUB213SDZrb_Intkz + 2182106616U, // VFNMSUB213SDm + 2182106616U, // VFNMSUB213SDm_Int + 2182106616U, // VFNMSUB213SDr + 2182106616U, // VFNMSUB213SDr_Int + 2182111317U, // VFNMSUB213SSZm + 2182111317U, // VFNMSUB213SSZm_Int + 49307733U, // VFNMSUB213SSZm_Intk + 2196791381U, // VFNMSUB213SSZm_Intkz + 2182111317U, // VFNMSUB213SSZr + 2182111317U, // VFNMSUB213SSZr_Int + 49307733U, // VFNMSUB213SSZr_Intk + 2196791381U, // VFNMSUB213SSZr_Intkz + 2182111317U, // VFNMSUB213SSZrb + 2182111317U, // VFNMSUB213SSZrb_Int + 49307733U, // VFNMSUB213SSZrb_Intk + 2196791381U, // VFNMSUB213SSZrb_Intkz + 2182111317U, // VFNMSUB213SSm + 2182111317U, // VFNMSUB213SSm_Int + 2182111317U, // VFNMSUB213SSr + 2182111317U, // VFNMSUB213SSr_Int + 2182105354U, // VFNMSUB231PDYm + 2182105354U, // VFNMSUB231PDYr + 2182105354U, // VFNMSUB231PDZ128m + 2182105354U, // VFNMSUB231PDZ128mb + 49301770U, // VFNMSUB231PDZ128mbk + 2196785418U, // VFNMSUB231PDZ128mbkz + 49301770U, // VFNMSUB231PDZ128mk + 2196785418U, // VFNMSUB231PDZ128mkz + 2182105354U, // VFNMSUB231PDZ128r + 49301770U, // VFNMSUB231PDZ128rk + 2196785418U, // VFNMSUB231PDZ128rkz + 2182105354U, // VFNMSUB231PDZ256m + 2182105354U, // VFNMSUB231PDZ256mb + 49301770U, // VFNMSUB231PDZ256mbk + 2196785418U, // VFNMSUB231PDZ256mbkz + 49301770U, // VFNMSUB231PDZ256mk + 2196785418U, // VFNMSUB231PDZ256mkz + 2182105354U, // VFNMSUB231PDZ256r + 49301770U, // VFNMSUB231PDZ256rk + 2196785418U, // VFNMSUB231PDZ256rkz + 2182105354U, // VFNMSUB231PDZm + 2182105354U, // VFNMSUB231PDZmb + 49301770U, // VFNMSUB231PDZmbk + 2196785418U, // VFNMSUB231PDZmbkz + 49301770U, // VFNMSUB231PDZmk + 2196785418U, // VFNMSUB231PDZmkz + 2182105354U, // VFNMSUB231PDZr + 2182105354U, // VFNMSUB231PDZrb + 49301770U, // VFNMSUB231PDZrbk + 2196785418U, // VFNMSUB231PDZrbkz + 49301770U, // VFNMSUB231PDZrk + 2196785418U, // VFNMSUB231PDZrkz + 2182105354U, // VFNMSUB231PDm + 2182105354U, // VFNMSUB231PDr + 2182110127U, // VFNMSUB231PSYm + 2182110127U, // VFNMSUB231PSYr + 2182110127U, // VFNMSUB231PSZ128m + 2182110127U, // VFNMSUB231PSZ128mb + 49306543U, // VFNMSUB231PSZ128mbk + 2196790191U, // VFNMSUB231PSZ128mbkz + 49306543U, // VFNMSUB231PSZ128mk + 2196790191U, // VFNMSUB231PSZ128mkz + 2182110127U, // VFNMSUB231PSZ128r + 49306543U, // VFNMSUB231PSZ128rk + 2196790191U, // VFNMSUB231PSZ128rkz + 2182110127U, // VFNMSUB231PSZ256m + 2182110127U, // VFNMSUB231PSZ256mb + 49306543U, // VFNMSUB231PSZ256mbk + 2196790191U, // VFNMSUB231PSZ256mbkz + 49306543U, // VFNMSUB231PSZ256mk + 2196790191U, // VFNMSUB231PSZ256mkz + 2182110127U, // VFNMSUB231PSZ256r + 49306543U, // VFNMSUB231PSZ256rk + 2196790191U, // VFNMSUB231PSZ256rkz + 2182110127U, // VFNMSUB231PSZm + 2182110127U, // VFNMSUB231PSZmb + 49306543U, // VFNMSUB231PSZmbk + 2196790191U, // VFNMSUB231PSZmbkz + 49306543U, // VFNMSUB231PSZmk + 2196790191U, // VFNMSUB231PSZmkz + 2182110127U, // VFNMSUB231PSZr + 2182110127U, // VFNMSUB231PSZrb + 49306543U, // VFNMSUB231PSZrbk + 2196790191U, // VFNMSUB231PSZrbkz + 49306543U, // VFNMSUB231PSZrk + 2196790191U, // VFNMSUB231PSZrkz + 2182110127U, // VFNMSUB231PSm + 2182110127U, // VFNMSUB231PSr + 2182106474U, // VFNMSUB231SDZm + 2182106474U, // VFNMSUB231SDZm_Int + 49302890U, // VFNMSUB231SDZm_Intk + 2196786538U, // VFNMSUB231SDZm_Intkz + 2182106474U, // VFNMSUB231SDZr + 2182106474U, // VFNMSUB231SDZr_Int + 49302890U, // VFNMSUB231SDZr_Intk + 2196786538U, // VFNMSUB231SDZr_Intkz + 2182106474U, // VFNMSUB231SDZrb + 2182106474U, // VFNMSUB231SDZrb_Int + 49302890U, // VFNMSUB231SDZrb_Intk + 2196786538U, // VFNMSUB231SDZrb_Intkz + 2182106474U, // VFNMSUB231SDm + 2182106474U, // VFNMSUB231SDm_Int + 2182106474U, // VFNMSUB231SDr + 2182106474U, // VFNMSUB231SDr_Int + 2182111175U, // VFNMSUB231SSZm + 2182111175U, // VFNMSUB231SSZm_Int + 49307591U, // VFNMSUB231SSZm_Intk + 2196791239U, // VFNMSUB231SSZm_Intkz + 2182111175U, // VFNMSUB231SSZr + 2182111175U, // VFNMSUB231SSZr_Int + 49307591U, // VFNMSUB231SSZr_Intk + 2196791239U, // VFNMSUB231SSZr_Intkz + 2182111175U, // VFNMSUB231SSZrb + 2182111175U, // VFNMSUB231SSZrb_Int + 49307591U, // VFNMSUB231SSZrb_Intk + 2196791239U, // VFNMSUB231SSZrb_Intkz + 2182111175U, // VFNMSUB231SSm + 2182111175U, // VFNMSUB231SSm_Int + 2182111175U, // VFNMSUB231SSr + 2182111175U, // VFNMSUB231SSr_Int + 2517650117U, // VFNMSUBPD4Ymr + 2517650117U, // VFNMSUBPD4Yrm + 2517650117U, // VFNMSUBPD4Yrr + 2517650117U, // VFNMSUBPD4Yrr_REV + 2517650117U, // VFNMSUBPD4mr + 2517650117U, // VFNMSUBPD4rm + 2517650117U, // VFNMSUBPD4rr + 2517650117U, // VFNMSUBPD4rr_REV + 2517654893U, // VFNMSUBPS4Ymr + 2517654893U, // VFNMSUBPS4Yrm + 2517654893U, // VFNMSUBPS4Yrr + 2517654893U, // VFNMSUBPS4Yrr_REV + 2517654893U, // VFNMSUBPS4mr + 2517654893U, // VFNMSUBPS4rm + 2517654893U, // VFNMSUBPS4rr + 2517654893U, // VFNMSUBPS4rr_REV + 2517651039U, // VFNMSUBSD4mr + 2517651039U, // VFNMSUBSD4mr_Int + 2517651039U, // VFNMSUBSD4rm + 2517651039U, // VFNMSUBSD4rm_Int + 2517651039U, // VFNMSUBSD4rr + 2517651039U, // VFNMSUBSD4rr_Int + 2517651039U, // VFNMSUBSD4rr_Int_REV + 2517651039U, // VFNMSUBSD4rr_REV + 2517655732U, // VFNMSUBSS4mr + 2517655732U, // VFNMSUBSS4mr_Int + 2517655732U, // VFNMSUBSS4rm + 2517655732U, // VFNMSUBSS4rm_Int + 2517655732U, // VFNMSUBSS4rr + 2517655732U, // VFNMSUBSS4rr_Int + 2517655732U, // VFNMSUBSS4rr_Int_REV + 2517655732U, // VFNMSUBSS4rr_REV + 2819640387U, // VFPCLASSPDZ128rm + 2752531523U, // VFPCLASSPDZ128rmb + 384846915U, // VFPCLASSPDZ128rmbk + 384846915U, // VFPCLASSPDZ128rmk + 2517650499U, // VFPCLASSPDZ128rr + 384846915U, // VFPCLASSPDZ128rrk + 3155184707U, // VFPCLASSPDZ256rm + 605047875U, // VFPCLASSPDZ256rmb + 384846915U, // VFPCLASSPDZ256rmbk + 384846915U, // VFPCLASSPDZ256rmk + 2517650499U, // VFPCLASSPDZ256rr + 384846915U, // VFPCLASSPDZ256rrk + 3255848003U, // VFPCLASSPDZrm + 2752531523U, // VFPCLASSPDZrmb + 384846915U, // VFPCLASSPDZrmbk + 384846915U, // VFPCLASSPDZrmk + 2517650499U, // VFPCLASSPDZrr + 384846915U, // VFPCLASSPDZrrk + 2819645206U, // VFPCLASSPSZ128rm + 638607126U, // VFPCLASSPSZ128rmb + 384851734U, // VFPCLASSPSZ128rmbk + 384851734U, // VFPCLASSPSZ128rmk + 2517655318U, // VFPCLASSPSZ128rr + 384851734U, // VFPCLASSPSZ128rrk + 3155189526U, // VFPCLASSPSZ256rm + 2786090774U, // VFPCLASSPSZ256rmb + 384851734U, // VFPCLASSPSZ256rmbk + 384851734U, // VFPCLASSPSZ256rmk + 2517655318U, // VFPCLASSPSZ256rr + 384851734U, // VFPCLASSPSZ256rrk + 3255852822U, // VFPCLASSPSZrm + 638607126U, // VFPCLASSPSZrmb + 384851734U, // VFPCLASSPSZrmbk + 384851734U, // VFPCLASSPSZrmk + 2517655318U, // VFPCLASSPSZrr + 384851734U, // VFPCLASSPSZrrk + 2752532269U, // VFPCLASSSDZrm + 384847661U, // VFPCLASSSDZrmk + 2517651245U, // VFPCLASSSDZrr + 384847661U, // VFPCLASSSDZrrk + 2786091389U, // VFPCLASSSSZrm + 384852349U, // VFPCLASSSSZrmk + 2517655933U, // VFPCLASSSSZrr + 384852349U, // VFPCLASSSSZrrk + 1007701189U, // VFRCZPDYrm + 370166981U, // VFRCZPDYrr + 672156869U, // VFRCZPDrm + 370166981U, // VFRCZPDrr + 1007706024U, // VFRCZPSYrm + 370171816U, // VFRCZPSYrr + 672161704U, // VFRCZPSrm + 370171816U, // VFRCZPSrr + 605048749U, // VFRCZSDrm + 370167725U, // VFRCZSDrr + 638607831U, // VFRCZSSrm + 370172375U, // VFRCZSSrr + 1141918514U, // VGATHERDPDYrm + 3337636658U, // VGATHERDPDZ128rm + 1190153010U, // VGATHERDPDZ256rm + 3337636658U, // VGATHERDPDZrm + 1209027378U, // VGATHERDPDrm + 1141923313U, // VGATHERDPSYrm + 3337641457U, // VGATHERDPSZ128rm + 1190157809U, // VGATHERDPSZ256rm + 3337641457U, // VGATHERDPSZrm + 1209032177U, // VGATHERDPSrm + 822112218U, // VGATHERPF0DPDm + 822112350U, // VGATHERPF0DPSm + 822112284U, // VGATHERPF0QPDm + 1056993440U, // VGATHERPF0QPSm + 822112251U, // VGATHERPF1DPDm + 822112383U, // VGATHERPF1DPSm + 822112317U, // VGATHERPF1QPDm + 1056993473U, // VGATHERPF1QPSm + 1141918747U, // VGATHERQPDYrm + 3337636891U, // VGATHERQPDZ128rm + 1190153243U, // VGATHERQPDZ256rm + 3337636891U, // VGATHERQPDZrm + 1209027611U, // VGATHERQPDrm + 1209032430U, // VGATHERQPSYrm + 1190158062U, // VGATHERQPSZ128rm + 3337641710U, // VGATHERQPSZ256rm + 1190158062U, // VGATHERQPSZrm + 1242586862U, // VGATHERQPSrm + 672156688U, // VGETEXPPDZ128m + 605047824U, // VGETEXPPDZ128mb + 49302544U, // VGETEXPPDZ128mbk + 2532330512U, // VGETEXPPDZ128mbkz + 49302544U, // VGETEXPPDZ128mk + 2532330512U, // VGETEXPPDZ128mkz + 370166800U, // VGETEXPPDZ128r + 49302544U, // VGETEXPPDZ128rk + 2532330512U, // VGETEXPPDZ128rkz + 1007701008U, // VGETEXPPDZ256m + 2752531472U, // VGETEXPPDZ256mb + 49302544U, // VGETEXPPDZ256mbk + 2532330512U, // VGETEXPPDZ256mbkz + 49302544U, // VGETEXPPDZ256mk + 2532330512U, // VGETEXPPDZ256mkz + 370166800U, // VGETEXPPDZ256r + 49302544U, // VGETEXPPDZ256rk + 2532330512U, // VGETEXPPDZ256rkz + 1108364304U, // VGETEXPPDZm + 605047824U, // VGETEXPPDZmb + 49302544U, // VGETEXPPDZmbk + 2532330512U, // VGETEXPPDZmbkz + 49302544U, // VGETEXPPDZmk + 2532330512U, // VGETEXPPDZmkz + 370166800U, // VGETEXPPDZr + 2517650448U, // VGETEXPPDZrb + 49302544U, // VGETEXPPDZrbk + 2532330512U, // VGETEXPPDZrbkz + 49302544U, // VGETEXPPDZrk + 2532330512U, // VGETEXPPDZrkz + 672161507U, // VGETEXPPSZ128m + 2786090723U, // VGETEXPPSZ128mb + 49307363U, // VGETEXPPSZ128mbk + 2532335331U, // VGETEXPPSZ128mbkz + 49307363U, // VGETEXPPSZ128mk + 2532335331U, // VGETEXPPSZ128mkz + 370171619U, // VGETEXPPSZ128r + 49307363U, // VGETEXPPSZ128rk + 2532335331U, // VGETEXPPSZ128rkz + 1007705827U, // VGETEXPPSZ256m + 638607075U, // VGETEXPPSZ256mb + 49307363U, // VGETEXPPSZ256mbk + 2532335331U, // VGETEXPPSZ256mbkz + 49307363U, // VGETEXPPSZ256mk + 2532335331U, // VGETEXPPSZ256mkz + 370171619U, // VGETEXPPSZ256r + 49307363U, // VGETEXPPSZ256rk + 2532335331U, // VGETEXPPSZ256rkz + 1108369123U, // VGETEXPPSZm + 2786090723U, // VGETEXPPSZmb + 49307363U, // VGETEXPPSZmbk + 2532335331U, // VGETEXPPSZmbkz + 49307363U, // VGETEXPPSZmk + 2532335331U, // VGETEXPPSZmkz + 370171619U, // VGETEXPPSZr + 2517655267U, // VGETEXPPSZrb + 49307363U, // VGETEXPPSZrbk + 2532335331U, // VGETEXPPSZrbkz + 49307363U, // VGETEXPPSZrk + 2532335331U, // VGETEXPPSZrkz + 2517651214U, // VGETEXPSDZm + 49303310U, // VGETEXPSDZmk + 2532331278U, // VGETEXPSDZmkz + 2517651214U, // VGETEXPSDZr + 2517651214U, // VGETEXPSDZrb + 49303310U, // VGETEXPSDZrbk + 2532331278U, // VGETEXPSDZrbkz + 49303310U, // VGETEXPSDZrk + 2532331278U, // VGETEXPSDZrkz + 2517655922U, // VGETEXPSSZm + 49308018U, // VGETEXPSSZmk + 2532335986U, // VGETEXPSSZmkz + 2517655922U, // VGETEXPSSZr + 2517655922U, // VGETEXPSSZrb + 49308018U, // VGETEXPSSZrbk + 2532335986U, // VGETEXPSSZrbkz + 49308018U, // VGETEXPSSZrk + 2532335986U, // VGETEXPSSZrkz + 2752531565U, // VGETMANTPDZ128rmbi + 49302637U, // VGETMANTPDZ128rmbik + 2532330605U, // VGETMANTPDZ128rmbikz + 2819640429U, // VGETMANTPDZ128rmi + 49302637U, // VGETMANTPDZ128rmik + 2532330605U, // VGETMANTPDZ128rmikz + 2517650541U, // VGETMANTPDZ128rri + 49302637U, // VGETMANTPDZ128rrik + 2532330605U, // VGETMANTPDZ128rrikz + 605047917U, // VGETMANTPDZ256rmbi + 49302637U, // VGETMANTPDZ256rmbik + 2532330605U, // VGETMANTPDZ256rmbikz + 3155184749U, // VGETMANTPDZ256rmi + 49302637U, // VGETMANTPDZ256rmik + 2532330605U, // VGETMANTPDZ256rmikz + 2517650541U, // VGETMANTPDZ256rri + 49302637U, // VGETMANTPDZ256rrik + 2532330605U, // VGETMANTPDZ256rrikz + 2752531565U, // VGETMANTPDZrmbi + 49302637U, // VGETMANTPDZrmbik + 2532330605U, // VGETMANTPDZrmbikz + 3255848045U, // VGETMANTPDZrmi + 49302637U, // VGETMANTPDZrmik + 2532330605U, // VGETMANTPDZrmikz + 2517650541U, // VGETMANTPDZrri + 370166893U, // VGETMANTPDZrrib + 49302637U, // VGETMANTPDZrribk + 2532330605U, // VGETMANTPDZrribkz + 49302637U, // VGETMANTPDZrrik + 2532330605U, // VGETMANTPDZrrikz + 638607163U, // VGETMANTPSZ128rmbi + 49307451U, // VGETMANTPSZ128rmbik + 2532335419U, // VGETMANTPSZ128rmbikz + 2819645243U, // VGETMANTPSZ128rmi + 49307451U, // VGETMANTPSZ128rmik + 2532335419U, // VGETMANTPSZ128rmikz + 2517655355U, // VGETMANTPSZ128rri + 49307451U, // VGETMANTPSZ128rrik + 2532335419U, // VGETMANTPSZ128rrikz + 2786090811U, // VGETMANTPSZ256rmbi + 49307451U, // VGETMANTPSZ256rmbik + 2532335419U, // VGETMANTPSZ256rmbikz + 3155189563U, // VGETMANTPSZ256rmi + 49307451U, // VGETMANTPSZ256rmik + 2532335419U, // VGETMANTPSZ256rmikz + 2517655355U, // VGETMANTPSZ256rri + 49307451U, // VGETMANTPSZ256rrik + 2532335419U, // VGETMANTPSZ256rrikz + 638607163U, // VGETMANTPSZrmbi + 49307451U, // VGETMANTPSZrmbik + 2532335419U, // VGETMANTPSZrmbikz + 3255852859U, // VGETMANTPSZrmi + 49307451U, // VGETMANTPSZrmik + 2532335419U, // VGETMANTPSZrmikz + 2517655355U, // VGETMANTPSZrri + 370171707U, // VGETMANTPSZrrib + 49307451U, // VGETMANTPSZrribk + 2532335419U, // VGETMANTPSZrribkz + 49307451U, // VGETMANTPSZrrik + 2532335419U, // VGETMANTPSZrrikz + 2517651286U, // VGETMANTSDZrmi + 49303382U, // VGETMANTSDZrmik + 2532331350U, // VGETMANTSDZrmikz + 2517651286U, // VGETMANTSDZrri + 2517651286U, // VGETMANTSDZrrib + 49303382U, // VGETMANTSDZrribk + 2532331350U, // VGETMANTSDZrribkz + 49303382U, // VGETMANTSDZrrik + 2532331350U, // VGETMANTSDZrrikz + 2517655945U, // VGETMANTSSZrmi + 49308041U, // VGETMANTSSZrmik + 2532336009U, // VGETMANTSSZrmikz + 2517655945U, // VGETMANTSSZrri + 2517655945U, // VGETMANTSSZrrib + 49308041U, // VGETMANTSSZrribk + 2532336009U, // VGETMANTSSZrribkz + 49308041U, // VGETMANTSSZrrik + 2532336009U, // VGETMANTSSZrrikz + 2517648635U, // VGF2P8AFFINEINVQBYrmi + 2517648635U, // VGF2P8AFFINEINVQBYrri + 2517648635U, // VGF2P8AFFINEINVQBZ128rmbi + 49300731U, // VGF2P8AFFINEINVQBZ128rmbik + 2532328699U, // VGF2P8AFFINEINVQBZ128rmbikz + 2517648635U, // VGF2P8AFFINEINVQBZ128rmi + 49300731U, // VGF2P8AFFINEINVQBZ128rmik + 2532328699U, // VGF2P8AFFINEINVQBZ128rmikz + 2517648635U, // VGF2P8AFFINEINVQBZ128rri + 49300731U, // VGF2P8AFFINEINVQBZ128rrik + 2532328699U, // VGF2P8AFFINEINVQBZ128rrikz + 2517648635U, // VGF2P8AFFINEINVQBZ256rmbi + 49300731U, // VGF2P8AFFINEINVQBZ256rmbik + 2532328699U, // VGF2P8AFFINEINVQBZ256rmbikz + 2517648635U, // VGF2P8AFFINEINVQBZ256rmi + 49300731U, // VGF2P8AFFINEINVQBZ256rmik + 2532328699U, // VGF2P8AFFINEINVQBZ256rmikz + 2517648635U, // VGF2P8AFFINEINVQBZ256rri + 49300731U, // VGF2P8AFFINEINVQBZ256rrik + 2532328699U, // VGF2P8AFFINEINVQBZ256rrikz + 2517648635U, // VGF2P8AFFINEINVQBZrmbi + 49300731U, // VGF2P8AFFINEINVQBZrmbik + 2532328699U, // VGF2P8AFFINEINVQBZrmbikz + 2517648635U, // VGF2P8AFFINEINVQBZrmi + 49300731U, // VGF2P8AFFINEINVQBZrmik + 2532328699U, // VGF2P8AFFINEINVQBZrmikz + 2517648635U, // VGF2P8AFFINEINVQBZrri + 49300731U, // VGF2P8AFFINEINVQBZrrik + 2532328699U, // VGF2P8AFFINEINVQBZrrikz + 2517648635U, // VGF2P8AFFINEINVQBrmi + 2517648635U, // VGF2P8AFFINEINVQBrri + 2517648572U, // VGF2P8AFFINEQBYrmi + 2517648572U, // VGF2P8AFFINEQBYrri + 2517648572U, // VGF2P8AFFINEQBZ128rmbi + 49300668U, // VGF2P8AFFINEQBZ128rmbik + 2532328636U, // VGF2P8AFFINEQBZ128rmbikz + 2517648572U, // VGF2P8AFFINEQBZ128rmi + 49300668U, // VGF2P8AFFINEQBZ128rmik + 2532328636U, // VGF2P8AFFINEQBZ128rmikz + 2517648572U, // VGF2P8AFFINEQBZ128rri + 49300668U, // VGF2P8AFFINEQBZ128rrik + 2532328636U, // VGF2P8AFFINEQBZ128rrikz + 2517648572U, // VGF2P8AFFINEQBZ256rmbi + 49300668U, // VGF2P8AFFINEQBZ256rmbik + 2532328636U, // VGF2P8AFFINEQBZ256rmbikz + 2517648572U, // VGF2P8AFFINEQBZ256rmi + 49300668U, // VGF2P8AFFINEQBZ256rmik + 2532328636U, // VGF2P8AFFINEQBZ256rmikz + 2517648572U, // VGF2P8AFFINEQBZ256rri + 49300668U, // VGF2P8AFFINEQBZ256rrik + 2532328636U, // VGF2P8AFFINEQBZ256rrikz + 2517648572U, // VGF2P8AFFINEQBZrmbi + 49300668U, // VGF2P8AFFINEQBZrmbik + 2532328636U, // VGF2P8AFFINEQBZrmbikz + 2517648572U, // VGF2P8AFFINEQBZrmi + 49300668U, // VGF2P8AFFINEQBZrmik + 2532328636U, // VGF2P8AFFINEQBZrmikz + 2517648572U, // VGF2P8AFFINEQBZrri + 49300668U, // VGF2P8AFFINEQBZrrik + 2532328636U, // VGF2P8AFFINEQBZrrikz + 2517648572U, // VGF2P8AFFINEQBrmi + 2517648572U, // VGF2P8AFFINEQBrri + 2517648473U, // VGF2P8MULBYrm + 2517648473U, // VGF2P8MULBYrr + 2517648473U, // VGF2P8MULBZ128rm + 49300569U, // VGF2P8MULBZ128rmk + 2532328537U, // VGF2P8MULBZ128rmkz + 2517648473U, // VGF2P8MULBZ128rr + 49300569U, // VGF2P8MULBZ128rrk + 2532328537U, // VGF2P8MULBZ128rrkz + 2517648473U, // VGF2P8MULBZ256rm + 49300569U, // VGF2P8MULBZ256rmk + 2532328537U, // VGF2P8MULBZ256rmkz + 2517648473U, // VGF2P8MULBZ256rr + 49300569U, // VGF2P8MULBZ256rrk + 2532328537U, // VGF2P8MULBZ256rrkz + 2517648473U, // VGF2P8MULBZrm + 49300569U, // VGF2P8MULBZrmk + 2532328537U, // VGF2P8MULBZrmkz + 2517648473U, // VGF2P8MULBZrr + 49300569U, // VGF2P8MULBZrrk + 2532328537U, // VGF2P8MULBZrrkz + 2517648473U, // VGF2P8MULBrm + 2517648473U, // VGF2P8MULBrr + 2517650149U, // VHADDPDYrm + 2517650149U, // VHADDPDYrr + 2517650149U, // VHADDPDrm + 2517650149U, // VHADDPDrr + 2517654925U, // VHADDPSYrm + 2517654925U, // VHADDPSYrr + 2517654925U, // VHADDPSrm + 2517654925U, // VHADDPSrr + 2517650098U, // VHSUBPDYrm + 2517650098U, // VHSUBPDYrr + 2517650098U, // VHSUBPDrm + 2517650098U, // VHSUBPDrr + 2517654874U, // VHSUBPSYrm + 2517654874U, // VHSUBPSYrr + 2517654874U, // VHSUBPSrm + 2517654874U, // VHSUBPSrr + 2517648018U, // VINSERTF128rm + 2517648018U, // VINSERTF128rr + 2517647800U, // VINSERTF32x4Z256rm + 49299896U, // VINSERTF32x4Z256rmk + 2532327864U, // VINSERTF32x4Z256rmkz + 2517647800U, // VINSERTF32x4Z256rr + 49299896U, // VINSERTF32x4Z256rrk + 2532327864U, // VINSERTF32x4Z256rrkz + 2517647800U, // VINSERTF32x4Zrm + 49299896U, // VINSERTF32x4Zrmk + 2532327864U, // VINSERTF32x4Zrmkz + 2517647800U, // VINSERTF32x4Zrr + 49299896U, // VINSERTF32x4Zrrk + 2532327864U, // VINSERTF32x4Zrrkz + 2517648127U, // VINSERTF32x8Zrm + 49300223U, // VINSERTF32x8Zrmk + 2532328191U, // VINSERTF32x8Zrmkz + 2517648127U, // VINSERTF32x8Zrr + 49300223U, // VINSERTF32x8Zrrk + 2532328191U, // VINSERTF32x8Zrrkz + 2517647587U, // VINSERTF64x2Z256rm + 49299683U, // VINSERTF64x2Z256rmk + 2532327651U, // VINSERTF64x2Z256rmkz + 2517647587U, // VINSERTF64x2Z256rr + 49299683U, // VINSERTF64x2Z256rrk + 2532327651U, // VINSERTF64x2Z256rrkz + 2517647587U, // VINSERTF64x2Zrm + 49299683U, // VINSERTF64x2Zrmk + 2532327651U, // VINSERTF64x2Zrmkz + 2517647587U, // VINSERTF64x2Zrr + 49299683U, // VINSERTF64x2Zrrk + 2532327651U, // VINSERTF64x2Zrrkz + 2517647904U, // VINSERTF64x4Zrm + 49300000U, // VINSERTF64x4Zrmk + 2532327968U, // VINSERTF64x4Zrmkz + 2517647904U, // VINSERTF64x4Zrr + 49300000U, // VINSERTF64x4Zrrk + 2532327968U, // VINSERTF64x4Zrrkz + 2517648073U, // VINSERTI128rm + 2517648073U, // VINSERTI128rr + 2517647858U, // VINSERTI32x4Z256rm + 49299954U, // VINSERTI32x4Z256rmk + 2532327922U, // VINSERTI32x4Z256rmkz + 2517647858U, // VINSERTI32x4Z256rr + 49299954U, // VINSERTI32x4Z256rrk + 2532327922U, // VINSERTI32x4Z256rrkz + 2517647858U, // VINSERTI32x4Zrm + 49299954U, // VINSERTI32x4Zrmk + 2532327922U, // VINSERTI32x4Zrmkz + 2517647858U, // VINSERTI32x4Zrr + 49299954U, // VINSERTI32x4Zrrk + 2532327922U, // VINSERTI32x4Zrrkz + 2517648173U, // VINSERTI32x8Zrm + 49300269U, // VINSERTI32x8Zrmk + 2532328237U, // VINSERTI32x8Zrmkz + 2517648173U, // VINSERTI32x8Zrr + 49300269U, // VINSERTI32x8Zrrk + 2532328237U, // VINSERTI32x8Zrrkz + 2517647645U, // VINSERTI64x2Z256rm + 49299741U, // VINSERTI64x2Z256rmk + 2532327709U, // VINSERTI64x2Z256rmkz + 2517647645U, // VINSERTI64x2Z256rr + 49299741U, // VINSERTI64x2Z256rrk + 2532327709U, // VINSERTI64x2Z256rrkz + 2517647645U, // VINSERTI64x2Zrm + 49299741U, // VINSERTI64x2Zrmk + 2532327709U, // VINSERTI64x2Zrmkz + 2517647645U, // VINSERTI64x2Zrr + 49299741U, // VINSERTI64x2Zrrk + 2532327709U, // VINSERTI64x2Zrrkz + 2517647950U, // VINSERTI64x4Zrm + 49300046U, // VINSERTI64x4Zrmk + 2532328014U, // VINSERTI64x4Zrmkz + 2517647950U, // VINSERTI64x4Zrr + 49300046U, // VINSERTI64x4Zrrk + 2532328014U, // VINSERTI64x4Zrrkz + 2517655377U, // VINSERTPSZrm + 2517655377U, // VINSERTPSZrr + 2517655377U, // VINSERTPSrm + 2517655377U, // VINSERTPSrr + 1041261273U, // VLDDQUYrm + 336618201U, // VLDDQUrm + 72423U, // VLDMXCSR + 370172641U, // VMASKMOVDQU + 370172641U, // VMASKMOVDQU64 + 2149125297U, // VMASKMOVPDYmr + 2517650609U, // VMASKMOVPDYrm + 2149059761U, // VMASKMOVPDmr + 2517650609U, // VMASKMOVPDrm + 2149130132U, // VMASKMOVPSYmr + 2517655444U, // VMASKMOVPSYrm + 2149064596U, // VMASKMOVPSmr + 2517655444U, // VMASKMOVPSrm + 2517650621U, // VMAXCPDYrm + 2517650621U, // VMAXCPDYrr + 2517650621U, // VMAXCPDZ128rm + 2517650621U, // VMAXCPDZ128rmb + 49302717U, // VMAXCPDZ128rmbk + 2532330685U, // VMAXCPDZ128rmbkz + 49302717U, // VMAXCPDZ128rmk + 2532330685U, // VMAXCPDZ128rmkz + 2517650621U, // VMAXCPDZ128rr + 49302717U, // VMAXCPDZ128rrk + 2532330685U, // VMAXCPDZ128rrkz + 2517650621U, // VMAXCPDZ256rm + 2517650621U, // VMAXCPDZ256rmb + 49302717U, // VMAXCPDZ256rmbk + 2532330685U, // VMAXCPDZ256rmbkz + 49302717U, // VMAXCPDZ256rmk + 2532330685U, // VMAXCPDZ256rmkz + 2517650621U, // VMAXCPDZ256rr + 49302717U, // VMAXCPDZ256rrk + 2532330685U, // VMAXCPDZ256rrkz + 2517650621U, // VMAXCPDZrm + 2517650621U, // VMAXCPDZrmb + 49302717U, // VMAXCPDZrmbk + 2532330685U, // VMAXCPDZrmbkz + 49302717U, // VMAXCPDZrmk + 2532330685U, // VMAXCPDZrmkz + 2517650621U, // VMAXCPDZrr + 49302717U, // VMAXCPDZrrk + 2532330685U, // VMAXCPDZrrkz + 2517650621U, // VMAXCPDrm + 2517650621U, // VMAXCPDrr + 2517655456U, // VMAXCPSYrm + 2517655456U, // VMAXCPSYrr + 2517655456U, // VMAXCPSZ128rm + 2517655456U, // VMAXCPSZ128rmb + 49307552U, // VMAXCPSZ128rmbk + 2532335520U, // VMAXCPSZ128rmbkz + 49307552U, // VMAXCPSZ128rmk + 2532335520U, // VMAXCPSZ128rmkz + 2517655456U, // VMAXCPSZ128rr + 49307552U, // VMAXCPSZ128rrk + 2532335520U, // VMAXCPSZ128rrkz + 2517655456U, // VMAXCPSZ256rm + 2517655456U, // VMAXCPSZ256rmb + 49307552U, // VMAXCPSZ256rmbk + 2532335520U, // VMAXCPSZ256rmbkz + 49307552U, // VMAXCPSZ256rmk + 2532335520U, // VMAXCPSZ256rmkz + 2517655456U, // VMAXCPSZ256rr + 49307552U, // VMAXCPSZ256rrk + 2532335520U, // VMAXCPSZ256rrkz + 2517655456U, // VMAXCPSZrm + 2517655456U, // VMAXCPSZrmb + 49307552U, // VMAXCPSZrmbk + 2532335520U, // VMAXCPSZrmbkz + 49307552U, // VMAXCPSZrmk + 2532335520U, // VMAXCPSZrmkz + 2517655456U, // VMAXCPSZrr + 49307552U, // VMAXCPSZrrk + 2532335520U, // VMAXCPSZrrkz + 2517655456U, // VMAXCPSrm + 2517655456U, // VMAXCPSrr + 2517651365U, // VMAXCSDZrm + 2517651365U, // VMAXCSDZrr + 2517651365U, // VMAXCSDrm + 2517651365U, // VMAXCSDrr + 2517656015U, // VMAXCSSZrm + 2517656015U, // VMAXCSSZrr + 2517656015U, // VMAXCSSrm + 2517656015U, // VMAXCSSrr + 2517650621U, // VMAXPDYrm + 2517650621U, // VMAXPDYrr + 2517650621U, // VMAXPDZ128rm + 2517650621U, // VMAXPDZ128rmb + 49302717U, // VMAXPDZ128rmbk + 2532330685U, // VMAXPDZ128rmbkz + 49302717U, // VMAXPDZ128rmk + 2532330685U, // VMAXPDZ128rmkz + 2517650621U, // VMAXPDZ128rr + 49302717U, // VMAXPDZ128rrk + 2532330685U, // VMAXPDZ128rrkz + 2517650621U, // VMAXPDZ256rm + 2517650621U, // VMAXPDZ256rmb + 49302717U, // VMAXPDZ256rmbk + 2532330685U, // VMAXPDZ256rmbkz + 49302717U, // VMAXPDZ256rmk + 2532330685U, // VMAXPDZ256rmkz + 2517650621U, // VMAXPDZ256rr + 49302717U, // VMAXPDZ256rrk + 2532330685U, // VMAXPDZ256rrkz + 2517650621U, // VMAXPDZrm + 2517650621U, // VMAXPDZrmb + 49302717U, // VMAXPDZrmbk + 2532330685U, // VMAXPDZrmbkz + 49302717U, // VMAXPDZrmk + 2532330685U, // VMAXPDZrmkz + 2517650621U, // VMAXPDZrr + 2517650621U, // VMAXPDZrrb + 49302717U, // VMAXPDZrrbk + 2532330685U, // VMAXPDZrrbkz + 49302717U, // VMAXPDZrrk + 2532330685U, // VMAXPDZrrkz + 2517650621U, // VMAXPDrm + 2517650621U, // VMAXPDrr + 2517655456U, // VMAXPSYrm + 2517655456U, // VMAXPSYrr + 2517655456U, // VMAXPSZ128rm + 2517655456U, // VMAXPSZ128rmb + 49307552U, // VMAXPSZ128rmbk + 2532335520U, // VMAXPSZ128rmbkz + 49307552U, // VMAXPSZ128rmk + 2532335520U, // VMAXPSZ128rmkz + 2517655456U, // VMAXPSZ128rr + 49307552U, // VMAXPSZ128rrk + 2532335520U, // VMAXPSZ128rrkz + 2517655456U, // VMAXPSZ256rm + 2517655456U, // VMAXPSZ256rmb + 49307552U, // VMAXPSZ256rmbk + 2532335520U, // VMAXPSZ256rmbkz + 49307552U, // VMAXPSZ256rmk + 2532335520U, // VMAXPSZ256rmkz + 2517655456U, // VMAXPSZ256rr + 49307552U, // VMAXPSZ256rrk + 2532335520U, // VMAXPSZ256rrkz + 2517655456U, // VMAXPSZrm + 2517655456U, // VMAXPSZrmb + 49307552U, // VMAXPSZrmbk + 2532335520U, // VMAXPSZrmbkz + 49307552U, // VMAXPSZrmk + 2532335520U, // VMAXPSZrmkz + 2517655456U, // VMAXPSZrr + 2517655456U, // VMAXPSZrrb + 49307552U, // VMAXPSZrrbk + 2532335520U, // VMAXPSZrrbkz + 49307552U, // VMAXPSZrrk + 2532335520U, // VMAXPSZrrkz + 2517655456U, // VMAXPSrm + 2517655456U, // VMAXPSrr + 2517651365U, // VMAXSDZrm + 2517651365U, // VMAXSDZrm_Int + 49303461U, // VMAXSDZrm_Intk + 2532331429U, // VMAXSDZrm_Intkz + 2517651365U, // VMAXSDZrr + 2517651365U, // VMAXSDZrr_Int + 49303461U, // VMAXSDZrr_Intk + 2532331429U, // VMAXSDZrr_Intkz + 2517651365U, // VMAXSDZrrb_Int + 49303461U, // VMAXSDZrrb_Intk + 2532331429U, // VMAXSDZrrb_Intkz + 2517651365U, // VMAXSDrm + 2517651365U, // VMAXSDrm_Int + 2517651365U, // VMAXSDrr + 2517651365U, // VMAXSDrr_Int + 2517656015U, // VMAXSSZrm + 2517656015U, // VMAXSSZrm_Int + 49308111U, // VMAXSSZrm_Intk + 2532336079U, // VMAXSSZrm_Intkz + 2517656015U, // VMAXSSZrr + 2517656015U, // VMAXSSZrr_Int + 49308111U, // VMAXSSZrr_Intk + 2532336079U, // VMAXSSZrr_Intkz + 2517656015U, // VMAXSSZrrb_Int + 49308111U, // VMAXSSZrrb_Intk + 2532336079U, // VMAXSSZrrb_Intkz + 2517656015U, // VMAXSSrm + 2517656015U, // VMAXSSrm_Int + 2517656015U, // VMAXSSrr + 2517656015U, // VMAXSSrr_Int + 11475U, // VMCALL + 88689U, // VMCLEARm + 11178U, // VMFUNC + 2517650425U, // VMINCPDYrm + 2517650425U, // VMINCPDYrr + 2517650425U, // VMINCPDZ128rm + 2517650425U, // VMINCPDZ128rmb + 49302521U, // VMINCPDZ128rmbk + 2532330489U, // VMINCPDZ128rmbkz + 49302521U, // VMINCPDZ128rmk + 2532330489U, // VMINCPDZ128rmkz + 2517650425U, // VMINCPDZ128rr + 49302521U, // VMINCPDZ128rrk + 2532330489U, // VMINCPDZ128rrkz + 2517650425U, // VMINCPDZ256rm + 2517650425U, // VMINCPDZ256rmb + 49302521U, // VMINCPDZ256rmbk + 2532330489U, // VMINCPDZ256rmbkz + 49302521U, // VMINCPDZ256rmk + 2532330489U, // VMINCPDZ256rmkz + 2517650425U, // VMINCPDZ256rr + 49302521U, // VMINCPDZ256rrk + 2532330489U, // VMINCPDZ256rrkz + 2517650425U, // VMINCPDZrm + 2517650425U, // VMINCPDZrmb + 49302521U, // VMINCPDZrmbk + 2532330489U, // VMINCPDZrmbkz + 49302521U, // VMINCPDZrmk + 2532330489U, // VMINCPDZrmkz + 2517650425U, // VMINCPDZrr + 49302521U, // VMINCPDZrrk + 2532330489U, // VMINCPDZrrkz + 2517650425U, // VMINCPDrm + 2517650425U, // VMINCPDrr + 2517655236U, // VMINCPSYrm + 2517655236U, // VMINCPSYrr + 2517655236U, // VMINCPSZ128rm + 2517655236U, // VMINCPSZ128rmb + 49307332U, // VMINCPSZ128rmbk + 2532335300U, // VMINCPSZ128rmbkz + 49307332U, // VMINCPSZ128rmk + 2532335300U, // VMINCPSZ128rmkz + 2517655236U, // VMINCPSZ128rr + 49307332U, // VMINCPSZ128rrk + 2532335300U, // VMINCPSZ128rrkz + 2517655236U, // VMINCPSZ256rm + 2517655236U, // VMINCPSZ256rmb + 49307332U, // VMINCPSZ256rmbk + 2532335300U, // VMINCPSZ256rmbkz + 49307332U, // VMINCPSZ256rmk + 2532335300U, // VMINCPSZ256rmkz + 2517655236U, // VMINCPSZ256rr + 49307332U, // VMINCPSZ256rrk + 2532335300U, // VMINCPSZ256rrkz + 2517655236U, // VMINCPSZrm + 2517655236U, // VMINCPSZrmb + 49307332U, // VMINCPSZrmbk + 2532335300U, // VMINCPSZrmbkz + 49307332U, // VMINCPSZrmk + 2532335300U, // VMINCPSZrmkz + 2517655236U, // VMINCPSZrr + 49307332U, // VMINCPSZrrk + 2532335300U, // VMINCPSZrrkz + 2517655236U, // VMINCPSrm + 2517655236U, // VMINCPSrr + 2517651191U, // VMINCSDZrm + 2517651191U, // VMINCSDZrr + 2517651191U, // VMINCSDrm + 2517651191U, // VMINCSDrr + 2517655898U, // VMINCSSZrm + 2517655898U, // VMINCSSZrr + 2517655898U, // VMINCSSrm + 2517655898U, // VMINCSSrr + 2517650425U, // VMINPDYrm + 2517650425U, // VMINPDYrr + 2517650425U, // VMINPDZ128rm + 2517650425U, // VMINPDZ128rmb + 49302521U, // VMINPDZ128rmbk + 2532330489U, // VMINPDZ128rmbkz + 49302521U, // VMINPDZ128rmk + 2532330489U, // VMINPDZ128rmkz + 2517650425U, // VMINPDZ128rr + 49302521U, // VMINPDZ128rrk + 2532330489U, // VMINPDZ128rrkz + 2517650425U, // VMINPDZ256rm + 2517650425U, // VMINPDZ256rmb + 49302521U, // VMINPDZ256rmbk + 2532330489U, // VMINPDZ256rmbkz + 49302521U, // VMINPDZ256rmk + 2532330489U, // VMINPDZ256rmkz + 2517650425U, // VMINPDZ256rr + 49302521U, // VMINPDZ256rrk + 2532330489U, // VMINPDZ256rrkz + 2517650425U, // VMINPDZrm + 2517650425U, // VMINPDZrmb + 49302521U, // VMINPDZrmbk + 2532330489U, // VMINPDZrmbkz + 49302521U, // VMINPDZrmk + 2532330489U, // VMINPDZrmkz + 2517650425U, // VMINPDZrr + 2517650425U, // VMINPDZrrb + 49302521U, // VMINPDZrrbk + 2532330489U, // VMINPDZrrbkz + 49302521U, // VMINPDZrrk + 2532330489U, // VMINPDZrrkz + 2517650425U, // VMINPDrm + 2517650425U, // VMINPDrr + 2517655236U, // VMINPSYrm + 2517655236U, // VMINPSYrr + 2517655236U, // VMINPSZ128rm + 2517655236U, // VMINPSZ128rmb + 49307332U, // VMINPSZ128rmbk + 2532335300U, // VMINPSZ128rmbkz + 49307332U, // VMINPSZ128rmk + 2532335300U, // VMINPSZ128rmkz + 2517655236U, // VMINPSZ128rr + 49307332U, // VMINPSZ128rrk + 2532335300U, // VMINPSZ128rrkz + 2517655236U, // VMINPSZ256rm + 2517655236U, // VMINPSZ256rmb + 49307332U, // VMINPSZ256rmbk + 2532335300U, // VMINPSZ256rmbkz + 49307332U, // VMINPSZ256rmk + 2532335300U, // VMINPSZ256rmkz + 2517655236U, // VMINPSZ256rr + 49307332U, // VMINPSZ256rrk + 2532335300U, // VMINPSZ256rrkz + 2517655236U, // VMINPSZrm + 2517655236U, // VMINPSZrmb + 49307332U, // VMINPSZrmbk + 2532335300U, // VMINPSZrmbkz + 49307332U, // VMINPSZrmk + 2532335300U, // VMINPSZrmkz + 2517655236U, // VMINPSZrr + 2517655236U, // VMINPSZrrb + 49307332U, // VMINPSZrrbk + 2532335300U, // VMINPSZrrbkz + 49307332U, // VMINPSZrrk + 2532335300U, // VMINPSZrrkz + 2517655236U, // VMINPSrm + 2517655236U, // VMINPSrr + 2517651191U, // VMINSDZrm + 2517651191U, // VMINSDZrm_Int + 49303287U, // VMINSDZrm_Intk + 2532331255U, // VMINSDZrm_Intkz + 2517651191U, // VMINSDZrr + 2517651191U, // VMINSDZrr_Int + 49303287U, // VMINSDZrr_Intk + 2532331255U, // VMINSDZrr_Intkz + 2517651191U, // VMINSDZrrb_Int + 49303287U, // VMINSDZrrb_Intk + 2532331255U, // VMINSDZrrb_Intkz + 2517651191U, // VMINSDrm + 2517651191U, // VMINSDrm_Int + 2517651191U, // VMINSDrr + 2517651191U, // VMINSDrr_Int + 2517655898U, // VMINSSZrm + 2517655898U, // VMINSSZrm_Int + 49307994U, // VMINSSZrm_Intk + 2532335962U, // VMINSSZrm_Intkz + 2517655898U, // VMINSSZrr + 2517655898U, // VMINSSZrr_Int + 49307994U, // VMINSSZrr_Intk + 2532335962U, // VMINSSZrr_Intkz + 2517655898U, // VMINSSZrrb_Int + 49307994U, // VMINSSZrrb_Intk + 2532335962U, // VMINSSZrrb_Intkz + 2517655898U, // VMINSSrm + 2517655898U, // VMINSSrm_Int + 2517655898U, // VMINSSrr + 2517655898U, // VMINSSrr_Int + 11391U, // VMLAUNCH + 12061U, // VMLOAD32 + 12116U, // VMLOAD64 + 11467U, // VMMCALL + 437279286U, // VMOV64toPQIZrm + 370170422U, // VMOV64toPQIZrr + 437279286U, // VMOV64toPQIrm + 370170422U, // VMOV64toPQIrr + 437279286U, // VMOV64toSDZrm + 370170422U, // VMOV64toSDZrr + 437279286U, // VMOV64toSDrm + 370170422U, // VMOV64toSDrr + 1641097U, // VMOVAPDYmr + 1007700617U, // VMOVAPDYrm + 370166409U, // VMOVAPDYrr + 370166409U, // VMOVAPDYrr_REV + 1575561U, // VMOVAPDZ128mr + 16255625U, // VMOVAPDZ128mrk + 672156297U, // VMOVAPDZ128rm + 49302153U, // VMOVAPDZ128rmk + 2532330121U, // VMOVAPDZ128rmkz + 370166409U, // VMOVAPDZ128rr + 370166409U, // VMOVAPDZ128rr_REV + 49302153U, // VMOVAPDZ128rrk + 384846473U, // VMOVAPDZ128rrk_REV + 2532330121U, // VMOVAPDZ128rrkz + 2532330121U, // VMOVAPDZ128rrkz_REV + 1641097U, // VMOVAPDZ256mr + 16321161U, // VMOVAPDZ256mrk + 1007700617U, // VMOVAPDZ256rm + 49302153U, // VMOVAPDZ256rmk + 2532330121U, // VMOVAPDZ256rmkz + 370166409U, // VMOVAPDZ256rr + 370166409U, // VMOVAPDZ256rr_REV + 49302153U, // VMOVAPDZ256rrk + 384846473U, // VMOVAPDZ256rrk_REV + 2532330121U, // VMOVAPDZ256rrkz + 2532330121U, // VMOVAPDZ256rrkz_REV + 1657481U, // VMOVAPDZmr + 16337545U, // VMOVAPDZmrk + 1108363913U, // VMOVAPDZrm + 49302153U, // VMOVAPDZrmk + 2532330121U, // VMOVAPDZrmkz + 370166409U, // VMOVAPDZrr + 370166409U, // VMOVAPDZrr_REV + 49302153U, // VMOVAPDZrrk + 384846473U, // VMOVAPDZrrk_REV + 2532330121U, // VMOVAPDZrrkz + 2532330121U, // VMOVAPDZrrkz_REV + 1575561U, // VMOVAPDmr + 672156297U, // VMOVAPDrm + 370166409U, // VMOVAPDrr + 370166409U, // VMOVAPDrr_REV + 1645881U, // VMOVAPSYmr + 1007705401U, // VMOVAPSYrm + 370171193U, // VMOVAPSYrr + 370171193U, // VMOVAPSYrr_REV + 1580345U, // VMOVAPSZ128mr + 16260409U, // VMOVAPSZ128mrk + 672161081U, // VMOVAPSZ128rm + 49306937U, // VMOVAPSZ128rmk + 2532334905U, // VMOVAPSZ128rmkz + 370171193U, // VMOVAPSZ128rr + 370171193U, // VMOVAPSZ128rr_REV + 49306937U, // VMOVAPSZ128rrk + 384851257U, // VMOVAPSZ128rrk_REV + 2532334905U, // VMOVAPSZ128rrkz + 2532334905U, // VMOVAPSZ128rrkz_REV + 1645881U, // VMOVAPSZ256mr + 16325945U, // VMOVAPSZ256mrk + 1007705401U, // VMOVAPSZ256rm + 49306937U, // VMOVAPSZ256rmk + 2532334905U, // VMOVAPSZ256rmkz + 370171193U, // VMOVAPSZ256rr + 370171193U, // VMOVAPSZ256rr_REV + 49306937U, // VMOVAPSZ256rrk + 384851257U, // VMOVAPSZ256rrk_REV + 2532334905U, // VMOVAPSZ256rrkz + 2532334905U, // VMOVAPSZ256rrkz_REV + 1662265U, // VMOVAPSZmr + 16342329U, // VMOVAPSZmrk + 1108368697U, // VMOVAPSZrm + 49306937U, // VMOVAPSZrmk + 2532334905U, // VMOVAPSZrmkz + 370171193U, // VMOVAPSZrr + 370171193U, // VMOVAPSZrr_REV + 49306937U, // VMOVAPSZrrk + 384851257U, // VMOVAPSZrrk_REV + 2532334905U, // VMOVAPSZrrkz + 2532334905U, // VMOVAPSZrrkz_REV + 1580345U, // VMOVAPSmr + 672161081U, // VMOVAPSrm + 370171193U, // VMOVAPSrr + 370171193U, // VMOVAPSrr_REV + 1007703407U, // VMOVDDUPYrm + 370169199U, // VMOVDDUPYrr + 605050223U, // VMOVDDUPZ128rm + 49304943U, // VMOVDDUPZ128rmk + 2532332911U, // VMOVDDUPZ128rmkz + 370169199U, // VMOVDDUPZ128rr + 49304943U, // VMOVDDUPZ128rrk + 2532332911U, // VMOVDDUPZ128rrkz + 1007703407U, // VMOVDDUPZ256rm + 49304943U, // VMOVDDUPZ256rmk + 2532332911U, // VMOVDDUPZ256rmkz + 370169199U, // VMOVDDUPZ256rr + 49304943U, // VMOVDDUPZ256rrk + 2532332911U, // VMOVDDUPZ256rrkz + 1108366703U, // VMOVDDUPZrm + 49304943U, // VMOVDDUPZrmk + 2532332911U, // VMOVDDUPZrmkz + 370169199U, // VMOVDDUPZrr + 49304943U, // VMOVDDUPZrrk + 2532332911U, // VMOVDDUPZrrkz + 605050223U, // VMOVDDUPrm + 370169199U, // VMOVDDUPrr + 403722360U, // VMOVDI2PDIZrm + 370167928U, // VMOVDI2PDIZrr + 403722360U, // VMOVDI2PDIrm + 370167928U, // VMOVDI2PDIrr + 403722360U, // VMOVDI2SSZrm + 370167928U, // VMOVDI2SSZrr + 403722360U, // VMOVDI2SSrm + 370167928U, // VMOVDI2SSrr + 1196112U, // VMOVDQA32Z128mr + 15876176U, // VMOVDQA32Z128mrk + 336609360U, // VMOVDQA32Z128rm + 49299536U, // VMOVDQA32Z128rmk + 2532327504U, // VMOVDQA32Z128rmkz + 370163792U, // VMOVDQA32Z128rr + 370163792U, // VMOVDQA32Z128rr_REV + 49299536U, // VMOVDQA32Z128rrk + 384843856U, // VMOVDQA32Z128rrk_REV + 2532327504U, // VMOVDQA32Z128rrkz + 2532327504U, // VMOVDQA32Z128rrkz_REV + 1671248U, // VMOVDQA32Z256mr + 16351312U, // VMOVDQA32Z256mrk + 1041252432U, // VMOVDQA32Z256rm + 49299536U, // VMOVDQA32Z256rmk + 2532327504U, // VMOVDQA32Z256rmkz + 370163792U, // VMOVDQA32Z256rr + 370163792U, // VMOVDQA32Z256rr_REV + 49299536U, // VMOVDQA32Z256rrk + 384843856U, // VMOVDQA32Z256rrk_REV + 2532327504U, // VMOVDQA32Z256rrkz + 2532327504U, // VMOVDQA32Z256rrkz_REV + 1687632U, // VMOVDQA32Zmr + 16367696U, // VMOVDQA32Zmrk + 806371408U, // VMOVDQA32Zrm + 49299536U, // VMOVDQA32Zrmk + 2532327504U, // VMOVDQA32Zrmkz + 370163792U, // VMOVDQA32Zrr + 370163792U, // VMOVDQA32Zrr_REV + 49299536U, // VMOVDQA32Zrrk + 384843856U, // VMOVDQA32Zrrk_REV + 2532327504U, // VMOVDQA32Zrrkz + 2532327504U, // VMOVDQA32Zrrkz_REV + 1196348U, // VMOVDQA64Z128mr + 15876412U, // VMOVDQA64Z128mrk + 336609596U, // VMOVDQA64Z128rm + 49299772U, // VMOVDQA64Z128rmk + 2532327740U, // VMOVDQA64Z128rmkz + 370164028U, // VMOVDQA64Z128rr + 370164028U, // VMOVDQA64Z128rr_REV + 49299772U, // VMOVDQA64Z128rrk + 384844092U, // VMOVDQA64Z128rrk_REV + 2532327740U, // VMOVDQA64Z128rrkz + 2532327740U, // VMOVDQA64Z128rrkz_REV + 1671484U, // VMOVDQA64Z256mr + 16351548U, // VMOVDQA64Z256mrk + 1041252668U, // VMOVDQA64Z256rm + 49299772U, // VMOVDQA64Z256rmk + 2532327740U, // VMOVDQA64Z256rmkz + 370164028U, // VMOVDQA64Z256rr + 370164028U, // VMOVDQA64Z256rr_REV + 49299772U, // VMOVDQA64Z256rrk + 384844092U, // VMOVDQA64Z256rrk_REV + 2532327740U, // VMOVDQA64Z256rrkz + 2532327740U, // VMOVDQA64Z256rrkz_REV + 1687868U, // VMOVDQA64Zmr + 16367932U, // VMOVDQA64Zmrk + 806371644U, // VMOVDQA64Zrm + 49299772U, // VMOVDQA64Zrmk + 2532327740U, // VMOVDQA64Zrmkz + 370164028U, // VMOVDQA64Zrr + 370164028U, // VMOVDQA64Zrr_REV + 49299772U, // VMOVDQA64Zrrk + 384844092U, // VMOVDQA64Zrrk_REV + 2532327740U, // VMOVDQA64Zrrkz + 2532327740U, // VMOVDQA64Zrrkz_REV + 1672032U, // VMOVDQAYmr + 1041253216U, // VMOVDQAYrm + 370164576U, // VMOVDQAYrr + 370164576U, // VMOVDQAYrr_REV + 1196896U, // VMOVDQAmr + 336610144U, // VMOVDQArm + 370164576U, // VMOVDQArr + 370164576U, // VMOVDQArr_REV + 1196653U, // VMOVDQU16Z128mr + 15876717U, // VMOVDQU16Z128mrk + 336609901U, // VMOVDQU16Z128rm + 49300077U, // VMOVDQU16Z128rmk + 2532328045U, // VMOVDQU16Z128rmkz + 370164333U, // VMOVDQU16Z128rr + 370164333U, // VMOVDQU16Z128rr_REV + 49300077U, // VMOVDQU16Z128rrk + 384844397U, // VMOVDQU16Z128rrk_REV + 2532328045U, // VMOVDQU16Z128rrkz + 2532328045U, // VMOVDQU16Z128rrkz_REV + 1671789U, // VMOVDQU16Z256mr + 16351853U, // VMOVDQU16Z256mrk + 1041252973U, // VMOVDQU16Z256rm + 49300077U, // VMOVDQU16Z256rmk + 2532328045U, // VMOVDQU16Z256rmkz + 370164333U, // VMOVDQU16Z256rr + 370164333U, // VMOVDQU16Z256rr_REV + 49300077U, // VMOVDQU16Z256rrk + 384844397U, // VMOVDQU16Z256rrk_REV + 2532328045U, // VMOVDQU16Z256rrkz + 2532328045U, // VMOVDQU16Z256rrkz_REV + 1688173U, // VMOVDQU16Zmr + 16368237U, // VMOVDQU16Zmrk + 806371949U, // VMOVDQU16Zrm + 49300077U, // VMOVDQU16Zrmk + 2532328045U, // VMOVDQU16Zrmkz + 370164333U, // VMOVDQU16Zrr + 370164333U, // VMOVDQU16Zrr_REV + 49300077U, // VMOVDQU16Zrrk + 384844397U, // VMOVDQU16Zrrk_REV + 2532328045U, // VMOVDQU16Zrrkz + 2532328045U, // VMOVDQU16Zrrkz_REV + 1196130U, // VMOVDQU32Z128mr + 15876194U, // VMOVDQU32Z128mrk + 336609378U, // VMOVDQU32Z128rm + 49299554U, // VMOVDQU32Z128rmk + 2532327522U, // VMOVDQU32Z128rmkz + 370163810U, // VMOVDQU32Z128rr + 370163810U, // VMOVDQU32Z128rr_REV + 49299554U, // VMOVDQU32Z128rrk + 384843874U, // VMOVDQU32Z128rrk_REV + 2532327522U, // VMOVDQU32Z128rrkz + 2532327522U, // VMOVDQU32Z128rrkz_REV + 1671266U, // VMOVDQU32Z256mr + 16351330U, // VMOVDQU32Z256mrk + 1041252450U, // VMOVDQU32Z256rm + 49299554U, // VMOVDQU32Z256rmk + 2532327522U, // VMOVDQU32Z256rmkz + 370163810U, // VMOVDQU32Z256rr + 370163810U, // VMOVDQU32Z256rr_REV + 49299554U, // VMOVDQU32Z256rrk + 384843874U, // VMOVDQU32Z256rrk_REV + 2532327522U, // VMOVDQU32Z256rrkz + 2532327522U, // VMOVDQU32Z256rrkz_REV + 1687650U, // VMOVDQU32Zmr + 16367714U, // VMOVDQU32Zmrk + 806371426U, // VMOVDQU32Zrm + 49299554U, // VMOVDQU32Zrmk + 2532327522U, // VMOVDQU32Zrmkz + 370163810U, // VMOVDQU32Zrr + 370163810U, // VMOVDQU32Zrr_REV + 49299554U, // VMOVDQU32Zrrk + 384843874U, // VMOVDQU32Zrrk_REV + 2532327522U, // VMOVDQU32Zrrkz + 2532327522U, // VMOVDQU32Zrrkz_REV + 1196423U, // VMOVDQU64Z128mr + 15876487U, // VMOVDQU64Z128mrk + 336609671U, // VMOVDQU64Z128rm + 49299847U, // VMOVDQU64Z128rmk + 2532327815U, // VMOVDQU64Z128rmkz + 370164103U, // VMOVDQU64Z128rr + 370164103U, // VMOVDQU64Z128rr_REV + 49299847U, // VMOVDQU64Z128rrk + 384844167U, // VMOVDQU64Z128rrk_REV + 2532327815U, // VMOVDQU64Z128rrkz + 2532327815U, // VMOVDQU64Z128rrkz_REV + 1671559U, // VMOVDQU64Z256mr + 16351623U, // VMOVDQU64Z256mrk + 1041252743U, // VMOVDQU64Z256rm + 49299847U, // VMOVDQU64Z256rmk + 2532327815U, // VMOVDQU64Z256rmkz + 370164103U, // VMOVDQU64Z256rr + 370164103U, // VMOVDQU64Z256rr_REV + 49299847U, // VMOVDQU64Z256rrk + 384844167U, // VMOVDQU64Z256rrk_REV + 2532327815U, // VMOVDQU64Z256rrkz + 2532327815U, // VMOVDQU64Z256rrkz_REV + 1687943U, // VMOVDQU64Zmr + 16368007U, // VMOVDQU64Zmrk + 806371719U, // VMOVDQU64Zrm + 49299847U, // VMOVDQU64Zrmk + 2532327815U, // VMOVDQU64Zrmkz + 370164103U, // VMOVDQU64Zrr + 370164103U, // VMOVDQU64Zrr_REV + 49299847U, // VMOVDQU64Zrrk + 384844167U, // VMOVDQU64Zrrk_REV + 2532327815U, // VMOVDQU64Zrrkz + 2532327815U, // VMOVDQU64Zrrkz_REV + 1196774U, // VMOVDQU8Z128mr + 15876838U, // VMOVDQU8Z128mrk + 336610022U, // VMOVDQU8Z128rm + 49300198U, // VMOVDQU8Z128rmk + 2532328166U, // VMOVDQU8Z128rmkz + 370164454U, // VMOVDQU8Z128rr + 370164454U, // VMOVDQU8Z128rr_REV + 49300198U, // VMOVDQU8Z128rrk + 384844518U, // VMOVDQU8Z128rrk_REV + 2532328166U, // VMOVDQU8Z128rrkz + 2532328166U, // VMOVDQU8Z128rrkz_REV + 1671910U, // VMOVDQU8Z256mr + 16351974U, // VMOVDQU8Z256mrk + 1041253094U, // VMOVDQU8Z256rm + 49300198U, // VMOVDQU8Z256rmk + 2532328166U, // VMOVDQU8Z256rmkz + 370164454U, // VMOVDQU8Z256rr + 370164454U, // VMOVDQU8Z256rr_REV + 49300198U, // VMOVDQU8Z256rrk + 384844518U, // VMOVDQU8Z256rrk_REV + 2532328166U, // VMOVDQU8Z256rrkz + 2532328166U, // VMOVDQU8Z256rrkz_REV + 1688294U, // VMOVDQU8Zmr + 16368358U, // VMOVDQU8Zmrk + 806372070U, // VMOVDQU8Zrm + 49300198U, // VMOVDQU8Zrmk + 2532328166U, // VMOVDQU8Zrmkz + 370164454U, // VMOVDQU8Zrr + 370164454U, // VMOVDQU8Zrr_REV + 49300198U, // VMOVDQU8Zrrk + 384844518U, // VMOVDQU8Zrrk_REV + 2532328166U, // VMOVDQU8Zrrkz + 2532328166U, // VMOVDQU8Zrrkz_REV + 1680110U, // VMOVDQUYmr + 1041261294U, // VMOVDQUYrm + 370172654U, // VMOVDQUYrr + 370172654U, // VMOVDQUYrr_REV + 1204974U, // VMOVDQUmr + 336618222U, // VMOVDQUrm + 370172654U, // VMOVDQUrr + 370172654U, // VMOVDQUrr_REV + 2517655145U, // VMOVHLPSZrr + 2517655145U, // VMOVHLPSrr + 1182604U, // VMOVHPDZ128mr + 2517650316U, // VMOVHPDZ128rm + 1182604U, // VMOVHPDmr + 2517650316U, // VMOVHPDrm + 1187413U, // VMOVHPSZ128mr + 2517655125U, // VMOVHPSZ128rm + 1187413U, // VMOVHPSmr + 2517655125U, // VMOVHPSrm + 2517655115U, // VMOVLHPSZrr + 2517655115U, // VMOVLHPSrr + 1182654U, // VMOVLPDZ128mr + 2517650366U, // VMOVLPDZ128rm + 1182654U, // VMOVLPDmr + 2517650366U, // VMOVLPDrm + 1187473U, // VMOVLPSZ128mr + 2517655185U, // VMOVLPSZ128rm + 1187473U, // VMOVLPSmr + 2517655185U, // VMOVLPSrm + 370166677U, // VMOVMSKPDYrr + 370166677U, // VMOVMSKPDrr + 370171486U, // VMOVMSKPSYrr + 370171486U, // VMOVMSKPSrr + 1041253205U, // VMOVNTDQAYrm + 336610133U, // VMOVNTDQAZ128rm + 1041253205U, // VMOVNTDQAZ256rm + 806372181U, // VMOVNTDQAZrm + 336610133U, // VMOVNTDQArm + 1677082U, // VMOVNTDQYmr + 1201946U, // VMOVNTDQZ128mr + 1677082U, // VMOVNTDQZ256mr + 1693466U, // VMOVNTDQZmr + 1201946U, // VMOVNTDQmr + 1641593U, // VMOVNTPDYmr + 1576057U, // VMOVNTPDZ128mr + 1641593U, // VMOVNTPDZ256mr + 1657977U, // VMOVNTPDZmr + 1576057U, // VMOVNTPDmr + 1646407U, // VMOVNTPSYmr + 1580871U, // VMOVNTPSZ128mr + 1646407U, // VMOVNTPSZ256mr + 1662791U, // VMOVNTPSZmr + 1580871U, // VMOVNTPSmr + 1118328U, // VMOVPDI2DIZmr + 370167928U, // VMOVPDI2DIZrr + 1118328U, // VMOVPDI2DImr + 370167928U, // VMOVPDI2DIrr + 1137206U, // VMOVPQI2QIZmr + 370170422U, // VMOVPQI2QIZrr + 1137206U, // VMOVPQI2QImr + 370170422U, // VMOVPQI2QIrr + 1137206U, // VMOVPQIto64Zmr + 370170422U, // VMOVPQIto64Zrr + 1137206U, // VMOVPQIto64mr + 370170422U, // VMOVPQIto64rr + 437279286U, // VMOVQI2PQIZrm + 437279286U, // VMOVQI2PQIrm + 1183636U, // VMOVSDZmr + 15863700U, // VMOVSDZmrk + 605048724U, // VMOVSDZrm + 49303444U, // VMOVSDZrmk + 2532331412U, // VMOVSDZrmkz + 2517651348U, // VMOVSDZrr + 2517651348U, // VMOVSDZrr_REV + 49303444U, // VMOVSDZrrk + 49303444U, // VMOVSDZrrk_REV + 2532331412U, // VMOVSDZrrkz + 2532331412U, // VMOVSDZrrkz_REV + 1183636U, // VMOVSDmr + 605048724U, // VMOVSDrm + 2517651348U, // VMOVSDrr + 2517651348U, // VMOVSDrr_REV + 1137206U, // VMOVSDto64Zmr + 370170422U, // VMOVSDto64Zrr + 1137206U, // VMOVSDto64mr + 370170422U, // VMOVSDto64rr + 1007703417U, // VMOVSHDUPYrm + 370169209U, // VMOVSHDUPYrr + 672159097U, // VMOVSHDUPZ128rm + 49304953U, // VMOVSHDUPZ128rmk + 2532332921U, // VMOVSHDUPZ128rmkz + 370169209U, // VMOVSHDUPZ128rr + 49304953U, // VMOVSHDUPZ128rrk + 2532332921U, // VMOVSHDUPZ128rrkz + 1007703417U, // VMOVSHDUPZ256rm + 49304953U, // VMOVSHDUPZ256rmk + 2532332921U, // VMOVSHDUPZ256rmkz + 370169209U, // VMOVSHDUPZ256rr + 49304953U, // VMOVSHDUPZ256rrk + 2532332921U, // VMOVSHDUPZ256rrkz + 1108366713U, // VMOVSHDUPZrm + 49304953U, // VMOVSHDUPZrmk + 2532332921U, // VMOVSHDUPZrmkz + 370169209U, // VMOVSHDUPZrr + 49304953U, // VMOVSHDUPZrrk + 2532332921U, // VMOVSHDUPZrrkz + 672159097U, // VMOVSHDUPrm + 370169209U, // VMOVSHDUPrr + 1007703428U, // VMOVSLDUPYrm + 370169220U, // VMOVSLDUPYrr + 672159108U, // VMOVSLDUPZ128rm + 49304964U, // VMOVSLDUPZ128rmk + 2532332932U, // VMOVSLDUPZ128rmkz + 370169220U, // VMOVSLDUPZ128rr + 49304964U, // VMOVSLDUPZ128rrk + 2532332932U, // VMOVSLDUPZ128rrkz + 1007703428U, // VMOVSLDUPZ256rm + 49304964U, // VMOVSLDUPZ256rmk + 2532332932U, // VMOVSLDUPZ256rmkz + 370169220U, // VMOVSLDUPZ256rr + 49304964U, // VMOVSLDUPZ256rrk + 2532332932U, // VMOVSLDUPZ256rrkz + 1108366724U, // VMOVSLDUPZrm + 49304964U, // VMOVSLDUPZrmk + 2532332932U, // VMOVSLDUPZrmkz + 370169220U, // VMOVSLDUPZrr + 49304964U, // VMOVSLDUPZrrk + 2532332932U, // VMOVSLDUPZrrkz + 672159108U, // VMOVSLDUPrm + 370169220U, // VMOVSLDUPrr + 1118328U, // VMOVSS2DIZmr + 370167928U, // VMOVSS2DIZrr + 1118328U, // VMOVSS2DImr + 370167928U, // VMOVSS2DIrr + 1171911U, // VMOVSSZmr + 15851975U, // VMOVSSZmrk + 638607815U, // VMOVSSZrm + 49308103U, // VMOVSSZrmk + 2532336071U, // VMOVSSZrmkz + 2517656007U, // VMOVSSZrr + 2517656007U, // VMOVSSZrr_REV + 49308103U, // VMOVSSZrrk + 49308103U, // VMOVSSZrrk_REV + 2532336071U, // VMOVSSZrrkz + 2532336071U, // VMOVSSZrrkz_REV + 1171911U, // VMOVSSmr + 638607815U, // VMOVSSrm + 2517656007U, // VMOVSSrr + 2517656007U, // VMOVSSrr_REV + 1641621U, // VMOVUPDYmr + 1007701141U, // VMOVUPDYrm + 370166933U, // VMOVUPDYrr + 370166933U, // VMOVUPDYrr_REV + 1576085U, // VMOVUPDZ128mr + 16256149U, // VMOVUPDZ128mrk + 672156821U, // VMOVUPDZ128rm + 49302677U, // VMOVUPDZ128rmk + 2532330645U, // VMOVUPDZ128rmkz + 370166933U, // VMOVUPDZ128rr + 370166933U, // VMOVUPDZ128rr_REV + 49302677U, // VMOVUPDZ128rrk + 384846997U, // VMOVUPDZ128rrk_REV + 2532330645U, // VMOVUPDZ128rrkz + 2532330645U, // VMOVUPDZ128rrkz_REV + 1641621U, // VMOVUPDZ256mr + 16321685U, // VMOVUPDZ256mrk + 1007701141U, // VMOVUPDZ256rm + 49302677U, // VMOVUPDZ256rmk + 2532330645U, // VMOVUPDZ256rmkz + 370166933U, // VMOVUPDZ256rr + 370166933U, // VMOVUPDZ256rr_REV + 49302677U, // VMOVUPDZ256rrk + 384846997U, // VMOVUPDZ256rrk_REV + 2532330645U, // VMOVUPDZ256rrkz + 2532330645U, // VMOVUPDZ256rrkz_REV + 1658005U, // VMOVUPDZmr + 16338069U, // VMOVUPDZmrk + 1108364437U, // VMOVUPDZrm + 49302677U, // VMOVUPDZrmk + 2532330645U, // VMOVUPDZrmkz + 370166933U, // VMOVUPDZrr + 370166933U, // VMOVUPDZrr_REV + 49302677U, // VMOVUPDZrrk + 384846997U, // VMOVUPDZrrk_REV + 2532330645U, // VMOVUPDZrrkz + 2532330645U, // VMOVUPDZrrkz_REV + 1576085U, // VMOVUPDmr + 672156821U, // VMOVUPDrm + 370166933U, // VMOVUPDrr + 370166933U, // VMOVUPDrr_REV + 1646456U, // VMOVUPSYmr + 1007705976U, // VMOVUPSYrm + 370171768U, // VMOVUPSYrr + 370171768U, // VMOVUPSYrr_REV + 1580920U, // VMOVUPSZ128mr + 16260984U, // VMOVUPSZ128mrk + 672161656U, // VMOVUPSZ128rm + 49307512U, // VMOVUPSZ128rmk + 2532335480U, // VMOVUPSZ128rmkz + 370171768U, // VMOVUPSZ128rr + 370171768U, // VMOVUPSZ128rr_REV + 49307512U, // VMOVUPSZ128rrk + 384851832U, // VMOVUPSZ128rrk_REV + 2532335480U, // VMOVUPSZ128rrkz + 2532335480U, // VMOVUPSZ128rrkz_REV + 1646456U, // VMOVUPSZ256mr + 16326520U, // VMOVUPSZ256mrk + 1007705976U, // VMOVUPSZ256rm + 49307512U, // VMOVUPSZ256rmk + 2532335480U, // VMOVUPSZ256rmkz + 370171768U, // VMOVUPSZ256rr + 370171768U, // VMOVUPSZ256rr_REV + 49307512U, // VMOVUPSZ256rrk + 384851832U, // VMOVUPSZ256rrk_REV + 2532335480U, // VMOVUPSZ256rrkz + 2532335480U, // VMOVUPSZ256rrkz_REV + 1662840U, // VMOVUPSZmr + 16342904U, // VMOVUPSZmrk + 1108369272U, // VMOVUPSZrm + 49307512U, // VMOVUPSZrmk + 2532335480U, // VMOVUPSZrmkz + 370171768U, // VMOVUPSZrr + 370171768U, // VMOVUPSZrr_REV + 49307512U, // VMOVUPSZrrk + 384851832U, // VMOVUPSZrrk_REV + 2532335480U, // VMOVUPSZrrkz + 2532335480U, // VMOVUPSZrrkz_REV + 1580920U, // VMOVUPSmr + 672161656U, // VMOVUPSrm + 370171768U, // VMOVUPSrr + 370171768U, // VMOVUPSrr_REV + 370170422U, // VMOVZPQILo2PQIZrr + 370170422U, // VMOVZPQILo2PQIrr + 2517656424U, // VMPSADBWYrmi + 2517656424U, // VMPSADBWYrri + 2517656424U, // VMPSADBWrmi + 2517656424U, // VMPSADBWrri + 84081U, // VMPTRLDm + 90814U, // VMPTRSTm + 1115925U, // VMREAD32mr + 370165525U, // VMREAD32rr + 1132309U, // VMREAD64mr + 370165525U, // VMREAD64rr + 11293U, // VMRESUME + 12083U, // VMRUN32 + 12138U, // VMRUN64 + 12072U, // VMSAVE32 + 12127U, // VMSAVE64 + 2517650358U, // VMULPDYrm + 2517650358U, // VMULPDYrr + 2517650358U, // VMULPDZ128rm + 2517650358U, // VMULPDZ128rmb + 49302454U, // VMULPDZ128rmbk + 2532330422U, // VMULPDZ128rmbkz + 49302454U, // VMULPDZ128rmk + 2532330422U, // VMULPDZ128rmkz + 2517650358U, // VMULPDZ128rr + 49302454U, // VMULPDZ128rrk + 2532330422U, // VMULPDZ128rrkz + 2517650358U, // VMULPDZ256rm + 2517650358U, // VMULPDZ256rmb + 49302454U, // VMULPDZ256rmbk + 2532330422U, // VMULPDZ256rmbkz + 49302454U, // VMULPDZ256rmk + 2532330422U, // VMULPDZ256rmkz + 2517650358U, // VMULPDZ256rr + 49302454U, // VMULPDZ256rrk + 2532330422U, // VMULPDZ256rrkz + 2517650358U, // VMULPDZrm + 2517650358U, // VMULPDZrmb + 49302454U, // VMULPDZrmbk + 2532330422U, // VMULPDZrmbkz + 49302454U, // VMULPDZrmk + 2532330422U, // VMULPDZrmkz + 2517650358U, // VMULPDZrr + 2517650358U, // VMULPDZrrb + 49302454U, // VMULPDZrrbk + 2532330422U, // VMULPDZrrbkz + 49302454U, // VMULPDZrrk + 2532330422U, // VMULPDZrrkz + 2517650358U, // VMULPDrm + 2517650358U, // VMULPDrr + 2517655177U, // VMULPSYrm + 2517655177U, // VMULPSYrr + 2517655177U, // VMULPSZ128rm + 2517655177U, // VMULPSZ128rmb + 49307273U, // VMULPSZ128rmbk + 2532335241U, // VMULPSZ128rmbkz + 49307273U, // VMULPSZ128rmk + 2532335241U, // VMULPSZ128rmkz + 2517655177U, // VMULPSZ128rr + 49307273U, // VMULPSZ128rrk + 2532335241U, // VMULPSZ128rrkz + 2517655177U, // VMULPSZ256rm + 2517655177U, // VMULPSZ256rmb + 49307273U, // VMULPSZ256rmbk + 2532335241U, // VMULPSZ256rmbkz + 49307273U, // VMULPSZ256rmk + 2532335241U, // VMULPSZ256rmkz + 2517655177U, // VMULPSZ256rr + 49307273U, // VMULPSZ256rrk + 2532335241U, // VMULPSZ256rrkz + 2517655177U, // VMULPSZrm + 2517655177U, // VMULPSZrmb + 49307273U, // VMULPSZrmbk + 2532335241U, // VMULPSZrmbkz + 49307273U, // VMULPSZrmk + 2532335241U, // VMULPSZrmkz + 2517655177U, // VMULPSZrr + 2517655177U, // VMULPSZrrb + 49307273U, // VMULPSZrrbk + 2532335241U, // VMULPSZrrbkz + 49307273U, // VMULPSZrrk + 2532335241U, // VMULPSZrrkz + 2517655177U, // VMULPSrm + 2517655177U, // VMULPSrr + 2517651161U, // VMULSDZrm + 2517651161U, // VMULSDZrm_Int + 49303257U, // VMULSDZrm_Intk + 2532331225U, // VMULSDZrm_Intkz + 2517651161U, // VMULSDZrr + 2517651161U, // VMULSDZrr_Int + 49303257U, // VMULSDZrr_Intk + 2532331225U, // VMULSDZrr_Intkz + 2517651161U, // VMULSDZrrb_Int + 49303257U, // VMULSDZrrb_Intk + 2532331225U, // VMULSDZrrb_Intkz + 2517651161U, // VMULSDrm + 2517651161U, // VMULSDrm_Int + 2517651161U, // VMULSDrr + 2517651161U, // VMULSDrr_Int + 2517655877U, // VMULSSZrm + 2517655877U, // VMULSSZrm_Int + 49307973U, // VMULSSZrm_Intk + 2532335941U, // VMULSSZrm_Intkz + 2517655877U, // VMULSSZrr + 2517655877U, // VMULSSZrr_Int + 49307973U, // VMULSSZrr_Intk + 2532335941U, // VMULSSZrr_Intkz + 2517655877U, // VMULSSZrrb_Int + 49307973U, // VMULSSZrrb_Intk + 2532335941U, // VMULSSZrrb_Intkz + 2517655877U, // VMULSSrm + 2517655877U, // VMULSSrm_Int + 2517655877U, // VMULSSrr + 2517655877U, // VMULSSrr_Int + 403722723U, // VMWRITE32rm + 370168291U, // VMWRITE32rr + 437277155U, // VMWRITE64rm + 370168291U, // VMWRITE64rr + 11350U, // VMXOFF + 87187U, // VMXON + 2517650484U, // VORPDYrm + 2517650484U, // VORPDYrr + 2517650484U, // VORPDZ128rm + 2517650484U, // VORPDZ128rmb + 49302580U, // VORPDZ128rmbk + 2532330548U, // VORPDZ128rmbkz + 49302580U, // VORPDZ128rmk + 2532330548U, // VORPDZ128rmkz + 2517650484U, // VORPDZ128rr + 49302580U, // VORPDZ128rrk + 2532330548U, // VORPDZ128rrkz + 2517650484U, // VORPDZ256rm + 2517650484U, // VORPDZ256rmb + 49302580U, // VORPDZ256rmbk + 2532330548U, // VORPDZ256rmbkz + 49302580U, // VORPDZ256rmk + 2532330548U, // VORPDZ256rmkz + 2517650484U, // VORPDZ256rr + 49302580U, // VORPDZ256rrk + 2532330548U, // VORPDZ256rrkz + 2517650484U, // VORPDZrm + 2517650484U, // VORPDZrmb + 49302580U, // VORPDZrmbk + 2532330548U, // VORPDZrmbkz + 49302580U, // VORPDZrmk + 2532330548U, // VORPDZrmkz + 2517650484U, // VORPDZrr + 49302580U, // VORPDZrrk + 2532330548U, // VORPDZrrkz + 2517650484U, // VORPDrm + 2517650484U, // VORPDrr + 2517655303U, // VORPSYrm + 2517655303U, // VORPSYrr + 2517655303U, // VORPSZ128rm + 2517655303U, // VORPSZ128rmb + 49307399U, // VORPSZ128rmbk + 2532335367U, // VORPSZ128rmbkz + 49307399U, // VORPSZ128rmk + 2532335367U, // VORPSZ128rmkz + 2517655303U, // VORPSZ128rr + 49307399U, // VORPSZ128rrk + 2532335367U, // VORPSZ128rrkz + 2517655303U, // VORPSZ256rm + 2517655303U, // VORPSZ256rmb + 49307399U, // VORPSZ256rmbk + 2532335367U, // VORPSZ256rmbkz + 49307399U, // VORPSZ256rmk + 2532335367U, // VORPSZ256rmkz + 2517655303U, // VORPSZ256rr + 49307399U, // VORPSZ256rrk + 2532335367U, // VORPSZ256rrkz + 2517655303U, // VORPSZrm + 2517655303U, // VORPSZrmb + 49307399U, // VORPSZrmbk + 2532335367U, // VORPSZrmbkz + 49307399U, // VORPSZrmk + 2532335367U, // VORPSZrmkz + 2517655303U, // VORPSZrr + 49307399U, // VORPSZrrk + 2532335367U, // VORPSZrrkz + 2517655303U, // VORPSrm + 2517655303U, // VORPSrr + 2182110009U, // VP4DPWSSDSrm + 49306425U, // VP4DPWSSDSrmk + 2196790073U, // VP4DPWSSDSrmkz + 2182106945U, // VP4DPWSSDrm + 49303361U, // VP4DPWSSDrmk + 2196787009U, // VP4DPWSSDrmkz + 1041253704U, // VPABSBYrm + 370165064U, // VPABSBYrr + 336610632U, // VPABSBZ128rm + 49300808U, // VPABSBZ128rmk + 2532328776U, // VPABSBZ128rmkz + 370165064U, // VPABSBZ128rr + 49300808U, // VPABSBZ128rrk + 2532328776U, // VPABSBZ128rrkz + 1041253704U, // VPABSBZ256rm + 49300808U, // VPABSBZ256rmk + 2532328776U, // VPABSBZ256rmkz + 370165064U, // VPABSBZ256rr + 49300808U, // VPABSBZ256rrk + 2532328776U, // VPABSBZ256rrkz + 806372680U, // VPABSBZrm + 49300808U, // VPABSBZrmk + 2532328776U, // VPABSBZrmkz + 370165064U, // VPABSBZrr + 49300808U, // VPABSBZrrk + 2532328776U, // VPABSBZrrkz + 336610632U, // VPABSBrm + 370165064U, // VPABSBrr + 1041256013U, // VPABSDYrm + 370167373U, // VPABSDYrr + 336612941U, // VPABSDZ128rm + 2551205453U, // VPABSDZ128rmb + 49303117U, // VPABSDZ128rmbk + 2532331085U, // VPABSDZ128rmbkz + 49303117U, // VPABSDZ128rmk + 2532331085U, // VPABSDZ128rmkz + 370167373U, // VPABSDZ128rr + 49303117U, // VPABSDZ128rrk + 2532331085U, // VPABSDZ128rrkz + 1041256013U, // VPABSDZ256rm + 403721805U, // VPABSDZ256rmb + 49303117U, // VPABSDZ256rmbk + 2532331085U, // VPABSDZ256rmbkz + 49303117U, // VPABSDZ256rmk + 2532331085U, // VPABSDZ256rmkz + 370167373U, // VPABSDZ256rr + 49303117U, // VPABSDZ256rrk + 2532331085U, // VPABSDZ256rrkz + 806374989U, // VPABSDZrm + 2551205453U, // VPABSDZrmb + 49303117U, // VPABSDZrmbk + 2532331085U, // VPABSDZrmbkz + 49303117U, // VPABSDZrmk + 2532331085U, // VPABSDZrmkz + 370167373U, // VPABSDZrr + 49303117U, // VPABSDZrrk + 2532331085U, // VPABSDZrrkz + 336612941U, // VPABSDrm + 370167373U, // VPABSDrr + 336615678U, // VPABSQZ128rm + 437278974U, // VPABSQZ128rmb + 49305854U, // VPABSQZ128rmbk + 2532333822U, // VPABSQZ128rmbkz + 49305854U, // VPABSQZ128rmk + 2532333822U, // VPABSQZ128rmkz + 370170110U, // VPABSQZ128rr + 49305854U, // VPABSQZ128rrk + 2532333822U, // VPABSQZ128rrkz + 1041258750U, // VPABSQZ256rm + 2584762622U, // VPABSQZ256rmb + 49305854U, // VPABSQZ256rmbk + 2532333822U, // VPABSQZ256rmbkz + 49305854U, // VPABSQZ256rmk + 2532333822U, // VPABSQZ256rmkz + 370170110U, // VPABSQZ256rr + 49305854U, // VPABSQZ256rrk + 2532333822U, // VPABSQZ256rrkz + 806377726U, // VPABSQZrm + 437278974U, // VPABSQZrmb + 49305854U, // VPABSQZrmbk + 2532333822U, // VPABSQZrmbkz + 49305854U, // VPABSQZrmk + 2532333822U, // VPABSQZrmkz + 370170110U, // VPABSQZrr + 49305854U, // VPABSQZrrk + 2532333822U, // VPABSQZrrkz + 1041261956U, // VPABSWYrm + 370173316U, // VPABSWYrr + 336618884U, // VPABSWZ128rm + 49309060U, // VPABSWZ128rmk + 2532337028U, // VPABSWZ128rmkz + 370173316U, // VPABSWZ128rr + 49309060U, // VPABSWZ128rrk + 2532337028U, // VPABSWZ128rrkz + 1041261956U, // VPABSWZ256rm + 49309060U, // VPABSWZ256rmk + 2532337028U, // VPABSWZ256rmkz + 370173316U, // VPABSWZ256rr + 49309060U, // VPABSWZ256rrk + 2532337028U, // VPABSWZ256rrkz + 806380932U, // VPABSWZrm + 49309060U, // VPABSWZrmk + 2532337028U, // VPABSWZrmkz + 370173316U, // VPABSWZrr + 49309060U, // VPABSWZrrk + 2532337028U, // VPABSWZrrkz + 336618884U, // VPABSWrm + 370173316U, // VPABSWrr + 2517656622U, // VPACKSSDWYrm + 2517656622U, // VPACKSSDWYrr + 2517656622U, // VPACKSSDWZ128rm + 2517656622U, // VPACKSSDWZ128rmb + 49308718U, // VPACKSSDWZ128rmbk + 2532336686U, // VPACKSSDWZ128rmbkz + 49308718U, // VPACKSSDWZ128rmk + 2532336686U, // VPACKSSDWZ128rmkz + 2517656622U, // VPACKSSDWZ128rr + 49308718U, // VPACKSSDWZ128rrk + 2532336686U, // VPACKSSDWZ128rrkz + 2517656622U, // VPACKSSDWZ256rm + 2517656622U, // VPACKSSDWZ256rmb + 49308718U, // VPACKSSDWZ256rmbk + 2532336686U, // VPACKSSDWZ256rmbkz + 49308718U, // VPACKSSDWZ256rmk + 2532336686U, // VPACKSSDWZ256rmkz + 2517656622U, // VPACKSSDWZ256rr + 49308718U, // VPACKSSDWZ256rrk + 2532336686U, // VPACKSSDWZ256rrkz + 2517656622U, // VPACKSSDWZrm + 2517656622U, // VPACKSSDWZrmb + 49308718U, // VPACKSSDWZrmbk + 2532336686U, // VPACKSSDWZrmbkz + 49308718U, // VPACKSSDWZrmk + 2532336686U, // VPACKSSDWZrmkz + 2517656622U, // VPACKSSDWZrr + 49308718U, // VPACKSSDWZrrk + 2532336686U, // VPACKSSDWZrrkz + 2517656622U, // VPACKSSDWrm + 2517656622U, // VPACKSSDWrr + 2517648973U, // VPACKSSWBYrm + 2517648973U, // VPACKSSWBYrr + 2517648973U, // VPACKSSWBZ128rm + 49301069U, // VPACKSSWBZ128rmk + 2532329037U, // VPACKSSWBZ128rmkz + 2517648973U, // VPACKSSWBZ128rr + 49301069U, // VPACKSSWBZ128rrk + 2532329037U, // VPACKSSWBZ128rrkz + 2517648973U, // VPACKSSWBZ256rm + 49301069U, // VPACKSSWBZ256rmk + 2532329037U, // VPACKSSWBZ256rmkz + 2517648973U, // VPACKSSWBZ256rr + 49301069U, // VPACKSSWBZ256rrk + 2532329037U, // VPACKSSWBZ256rrkz + 2517648973U, // VPACKSSWBZrm + 49301069U, // VPACKSSWBZrmk + 2532329037U, // VPACKSSWBZrmkz + 2517648973U, // VPACKSSWBZrr + 49301069U, // VPACKSSWBZrrk + 2532329037U, // VPACKSSWBZrrkz + 2517648973U, // VPACKSSWBrm + 2517648973U, // VPACKSSWBrr + 2517656633U, // VPACKUSDWYrm + 2517656633U, // VPACKUSDWYrr + 2517656633U, // VPACKUSDWZ128rm + 2517656633U, // VPACKUSDWZ128rmb + 49308729U, // VPACKUSDWZ128rmbk + 2532336697U, // VPACKUSDWZ128rmbkz + 49308729U, // VPACKUSDWZ128rmk + 2532336697U, // VPACKUSDWZ128rmkz + 2517656633U, // VPACKUSDWZ128rr + 49308729U, // VPACKUSDWZ128rrk + 2532336697U, // VPACKUSDWZ128rrkz + 2517656633U, // VPACKUSDWZ256rm + 2517656633U, // VPACKUSDWZ256rmb + 49308729U, // VPACKUSDWZ256rmbk + 2532336697U, // VPACKUSDWZ256rmbkz + 49308729U, // VPACKUSDWZ256rmk + 2532336697U, // VPACKUSDWZ256rmkz + 2517656633U, // VPACKUSDWZ256rr + 49308729U, // VPACKUSDWZ256rrk + 2532336697U, // VPACKUSDWZ256rrkz + 2517656633U, // VPACKUSDWZrm + 2517656633U, // VPACKUSDWZrmb + 49308729U, // VPACKUSDWZrmbk + 2532336697U, // VPACKUSDWZrmbkz + 49308729U, // VPACKUSDWZrmk + 2532336697U, // VPACKUSDWZrmkz + 2517656633U, // VPACKUSDWZrr + 49308729U, // VPACKUSDWZrrk + 2532336697U, // VPACKUSDWZrrkz + 2517656633U, // VPACKUSDWrm + 2517656633U, // VPACKUSDWrr + 2517648984U, // VPACKUSWBYrm + 2517648984U, // VPACKUSWBYrr + 2517648984U, // VPACKUSWBZ128rm + 49301080U, // VPACKUSWBZ128rmk + 2532329048U, // VPACKUSWBZ128rmkz + 2517648984U, // VPACKUSWBZ128rr + 49301080U, // VPACKUSWBZ128rrk + 2532329048U, // VPACKUSWBZ128rrkz + 2517648984U, // VPACKUSWBZ256rm + 49301080U, // VPACKUSWBZ256rmk + 2532329048U, // VPACKUSWBZ256rmkz + 2517648984U, // VPACKUSWBZ256rr + 49301080U, // VPACKUSWBZ256rrk + 2532329048U, // VPACKUSWBZ256rrkz + 2517648984U, // VPACKUSWBZrm + 49301080U, // VPACKUSWBZrmk + 2532329048U, // VPACKUSWBZrmkz + 2517648984U, // VPACKUSWBZrr + 49301080U, // VPACKUSWBZrrk + 2532329048U, // VPACKUSWBZrrkz + 2517648984U, // VPACKUSWBrm + 2517648984U, // VPACKUSWBrr + 2517648367U, // VPADDBYrm + 2517648367U, // VPADDBYrr + 2517648367U, // VPADDBZ128rm + 49300463U, // VPADDBZ128rmk + 2532328431U, // VPADDBZ128rmkz + 2517648367U, // VPADDBZ128rr + 49300463U, // VPADDBZ128rrk + 2532328431U, // VPADDBZ128rrkz + 2517648367U, // VPADDBZ256rm + 49300463U, // VPADDBZ256rmk + 2532328431U, // VPADDBZ256rmkz + 2517648367U, // VPADDBZ256rr + 49300463U, // VPADDBZ256rrk + 2532328431U, // VPADDBZ256rrkz + 2517648367U, // VPADDBZrm + 49300463U, // VPADDBZrmk + 2532328431U, // VPADDBZrmkz + 2517648367U, // VPADDBZrr + 49300463U, // VPADDBZrrk + 2532328431U, // VPADDBZrrkz + 2517648367U, // VPADDBrm + 2517648367U, // VPADDBrr + 2517649293U, // VPADDDYrm + 2517649293U, // VPADDDYrr + 2517649293U, // VPADDDZ128rm + 2517649293U, // VPADDDZ128rmb + 49301389U, // VPADDDZ128rmbk + 2532329357U, // VPADDDZ128rmbkz + 49301389U, // VPADDDZ128rmk + 2532329357U, // VPADDDZ128rmkz + 2517649293U, // VPADDDZ128rr + 49301389U, // VPADDDZ128rrk + 2532329357U, // VPADDDZ128rrkz + 2517649293U, // VPADDDZ256rm + 2517649293U, // VPADDDZ256rmb + 49301389U, // VPADDDZ256rmbk + 2532329357U, // VPADDDZ256rmbkz + 49301389U, // VPADDDZ256rmk + 2532329357U, // VPADDDZ256rmkz + 2517649293U, // VPADDDZ256rr + 49301389U, // VPADDDZ256rrk + 2532329357U, // VPADDDZ256rrkz + 2517649293U, // VPADDDZrm + 2517649293U, // VPADDDZrmb + 49301389U, // VPADDDZrmbk + 2532329357U, // VPADDDZrmbkz + 49301389U, // VPADDDZrmk + 2532329357U, // VPADDDZrmkz + 2517649293U, // VPADDDZrr + 49301389U, // VPADDDZrrk + 2532329357U, // VPADDDZrrkz + 2517649293U, // VPADDDrm + 2517649293U, // VPADDDrr + 2517653088U, // VPADDQYrm + 2517653088U, // VPADDQYrr + 2517653088U, // VPADDQZ128rm + 2517653088U, // VPADDQZ128rmb + 49305184U, // VPADDQZ128rmbk + 2532333152U, // VPADDQZ128rmbkz + 49305184U, // VPADDQZ128rmk + 2532333152U, // VPADDQZ128rmkz + 2517653088U, // VPADDQZ128rr + 49305184U, // VPADDQZ128rrk + 2532333152U, // VPADDQZ128rrkz + 2517653088U, // VPADDQZ256rm + 2517653088U, // VPADDQZ256rmb + 49305184U, // VPADDQZ256rmbk + 2532333152U, // VPADDQZ256rmbkz + 49305184U, // VPADDQZ256rmk + 2532333152U, // VPADDQZ256rmkz + 2517653088U, // VPADDQZ256rr + 49305184U, // VPADDQZ256rrk + 2532333152U, // VPADDQZ256rrkz + 2517653088U, // VPADDQZrm + 2517653088U, // VPADDQZrmb + 49305184U, // VPADDQZrmbk + 2532333152U, // VPADDQZrmbkz + 49305184U, // VPADDQZrmk + 2532333152U, // VPADDQZrmkz + 2517653088U, // VPADDQZrr + 49305184U, // VPADDQZrrk + 2532333152U, // VPADDQZrrkz + 2517653088U, // VPADDQrm + 2517653088U, // VPADDQrr + 2517648729U, // VPADDSBYrm + 2517648729U, // VPADDSBYrr + 2517648729U, // VPADDSBZ128rm + 49300825U, // VPADDSBZ128rmk + 2532328793U, // VPADDSBZ128rmkz + 2517648729U, // VPADDSBZ128rr + 49300825U, // VPADDSBZ128rrk + 2532328793U, // VPADDSBZ128rrkz + 2517648729U, // VPADDSBZ256rm + 49300825U, // VPADDSBZ256rmk + 2532328793U, // VPADDSBZ256rmkz + 2517648729U, // VPADDSBZ256rr + 49300825U, // VPADDSBZ256rrk + 2532328793U, // VPADDSBZ256rrkz + 2517648729U, // VPADDSBZrm + 49300825U, // VPADDSBZrmk + 2532328793U, // VPADDSBZrmkz + 2517648729U, // VPADDSBZrr + 49300825U, // VPADDSBZrrk + 2532328793U, // VPADDSBZrrkz + 2517648729U, // VPADDSBrm + 2517648729U, // VPADDSBrr + 2517657013U, // VPADDSWYrm + 2517657013U, // VPADDSWYrr + 2517657013U, // VPADDSWZ128rm + 49309109U, // VPADDSWZ128rmk + 2532337077U, // VPADDSWZ128rmkz + 2517657013U, // VPADDSWZ128rr + 49309109U, // VPADDSWZ128rrk + 2532337077U, // VPADDSWZ128rrkz + 2517657013U, // VPADDSWZ256rm + 49309109U, // VPADDSWZ256rmk + 2532337077U, // VPADDSWZ256rmkz + 2517657013U, // VPADDSWZ256rr + 49309109U, // VPADDSWZ256rrk + 2532337077U, // VPADDSWZ256rrkz + 2517657013U, // VPADDSWZrm + 49309109U, // VPADDSWZrmk + 2532337077U, // VPADDSWZrmkz + 2517657013U, // VPADDSWZrr + 49309109U, // VPADDSWZrrk + 2532337077U, // VPADDSWZrrkz + 2517657013U, // VPADDSWrm + 2517657013U, // VPADDSWrr + 2517648784U, // VPADDUSBYrm + 2517648784U, // VPADDUSBYrr + 2517648784U, // VPADDUSBZ128rm + 49300880U, // VPADDUSBZ128rmk + 2532328848U, // VPADDUSBZ128rmkz + 2517648784U, // VPADDUSBZ128rr + 49300880U, // VPADDUSBZ128rrk + 2532328848U, // VPADDUSBZ128rrkz + 2517648784U, // VPADDUSBZ256rm + 49300880U, // VPADDUSBZ256rmk + 2532328848U, // VPADDUSBZ256rmkz + 2517648784U, // VPADDUSBZ256rr + 49300880U, // VPADDUSBZ256rrk + 2532328848U, // VPADDUSBZ256rrkz + 2517648784U, // VPADDUSBZrm + 49300880U, // VPADDUSBZrmk + 2532328848U, // VPADDUSBZrmkz + 2517648784U, // VPADDUSBZrr + 49300880U, // VPADDUSBZrrk + 2532328848U, // VPADDUSBZrrkz + 2517648784U, // VPADDUSBrm + 2517648784U, // VPADDUSBrr + 2517657099U, // VPADDUSWYrm + 2517657099U, // VPADDUSWYrr + 2517657099U, // VPADDUSWZ128rm + 49309195U, // VPADDUSWZ128rmk + 2532337163U, // VPADDUSWZ128rmkz + 2517657099U, // VPADDUSWZ128rr + 49309195U, // VPADDUSWZ128rrk + 2532337163U, // VPADDUSWZ128rrkz + 2517657099U, // VPADDUSWZ256rm + 49309195U, // VPADDUSWZ256rmk + 2532337163U, // VPADDUSWZ256rmkz + 2517657099U, // VPADDUSWZ256rr + 49309195U, // VPADDUSWZ256rrk + 2532337163U, // VPADDUSWZ256rrkz + 2517657099U, // VPADDUSWZrm + 49309195U, // VPADDUSWZrmk + 2532337163U, // VPADDUSWZrmkz + 2517657099U, // VPADDUSWZrr + 49309195U, // VPADDUSWZrrk + 2532337163U, // VPADDUSWZrrkz + 2517657099U, // VPADDUSWrm + 2517657099U, // VPADDUSWrr + 2517656568U, // VPADDWYrm + 2517656568U, // VPADDWYrr + 2517656568U, // VPADDWZ128rm + 49308664U, // VPADDWZ128rmk + 2532336632U, // VPADDWZ128rmkz + 2517656568U, // VPADDWZ128rr + 49308664U, // VPADDWZ128rrk + 2532336632U, // VPADDWZ128rrkz + 2517656568U, // VPADDWZ256rm + 49308664U, // VPADDWZ256rmk + 2532336632U, // VPADDWZ256rmkz + 2517656568U, // VPADDWZ256rr + 49308664U, // VPADDWZ256rrk + 2532336632U, // VPADDWZ256rrkz + 2517656568U, // VPADDWZrm + 49308664U, // VPADDWZrmk + 2532336632U, // VPADDWZrmkz + 2517656568U, // VPADDWZrr + 49308664U, // VPADDWZrrk + 2532336632U, // VPADDWZrrkz + 2517656568U, // VPADDWrm + 2517656568U, // VPADDWrr + 2517654181U, // VPALIGNRYrmi + 2517654181U, // VPALIGNRYrri + 2517654181U, // VPALIGNRZ128rmi + 49306277U, // VPALIGNRZ128rmik + 2532334245U, // VPALIGNRZ128rmikz + 2517654181U, // VPALIGNRZ128rri + 49306277U, // VPALIGNRZ128rrik + 2532334245U, // VPALIGNRZ128rrikz + 2517654181U, // VPALIGNRZ256rmi + 49306277U, // VPALIGNRZ256rmik + 2532334245U, // VPALIGNRZ256rmikz + 2517654181U, // VPALIGNRZ256rri + 49306277U, // VPALIGNRZ256rrik + 2532334245U, // VPALIGNRZ256rrikz + 2517654181U, // VPALIGNRZrmi + 49306277U, // VPALIGNRZrmik + 2532334245U, // VPALIGNRZrmikz + 2517654181U, // VPALIGNRZrri + 49306277U, // VPALIGNRZrrik + 2532334245U, // VPALIGNRZrrikz + 2517654181U, // VPALIGNRrmi + 2517654181U, // VPALIGNRrri + 2517649317U, // VPANDDZ128rm + 2517649317U, // VPANDDZ128rmb + 49301413U, // VPANDDZ128rmbk + 2532329381U, // VPANDDZ128rmbkz + 49301413U, // VPANDDZ128rmk + 2532329381U, // VPANDDZ128rmkz + 2517649317U, // VPANDDZ128rr + 49301413U, // VPANDDZ128rrk + 2532329381U, // VPANDDZ128rrkz + 2517649317U, // VPANDDZ256rm + 2517649317U, // VPANDDZ256rmb + 49301413U, // VPANDDZ256rmbk + 2532329381U, // VPANDDZ256rmbkz + 49301413U, // VPANDDZ256rmk + 2532329381U, // VPANDDZ256rmkz + 2517649317U, // VPANDDZ256rr + 49301413U, // VPANDDZ256rrk + 2532329381U, // VPANDDZ256rrkz + 2517649317U, // VPANDDZrm + 2517649317U, // VPANDDZrmb + 49301413U, // VPANDDZrmbk + 2532329381U, // VPANDDZrmbkz + 49301413U, // VPANDDZrmk + 2532329381U, // VPANDDZrmkz + 2517649317U, // VPANDDZrr + 49301413U, // VPANDDZrrk + 2532329381U, // VPANDDZrrkz + 2517649611U, // VPANDNDZ128rm + 2517649611U, // VPANDNDZ128rmb + 49301707U, // VPANDNDZ128rmbk + 2532329675U, // VPANDNDZ128rmbkz + 49301707U, // VPANDNDZ128rmk + 2532329675U, // VPANDNDZ128rmkz + 2517649611U, // VPANDNDZ128rr + 49301707U, // VPANDNDZ128rrk + 2532329675U, // VPANDNDZ128rrkz + 2517649611U, // VPANDNDZ256rm + 2517649611U, // VPANDNDZ256rmb + 49301707U, // VPANDNDZ256rmbk + 2532329675U, // VPANDNDZ256rmbkz + 49301707U, // VPANDNDZ256rmk + 2532329675U, // VPANDNDZ256rmkz + 2517649611U, // VPANDNDZ256rr + 49301707U, // VPANDNDZ256rrk + 2532329675U, // VPANDNDZ256rrkz + 2517649611U, // VPANDNDZrm + 2517649611U, // VPANDNDZrmb + 49301707U, // VPANDNDZrmbk + 2532329675U, // VPANDNDZrmbkz + 49301707U, // VPANDNDZrmk + 2532329675U, // VPANDNDZrmkz + 2517649611U, // VPANDNDZrr + 49301707U, // VPANDNDZrrk + 2532329675U, // VPANDNDZrrkz + 2517653512U, // VPANDNQZ128rm + 2517653512U, // VPANDNQZ128rmb + 49305608U, // VPANDNQZ128rmbk + 2532333576U, // VPANDNQZ128rmbkz + 49305608U, // VPANDNQZ128rmk + 2532333576U, // VPANDNQZ128rmkz + 2517653512U, // VPANDNQZ128rr + 49305608U, // VPANDNQZ128rrk + 2532333576U, // VPANDNQZ128rrkz + 2517653512U, // VPANDNQZ256rm + 2517653512U, // VPANDNQZ256rmb + 49305608U, // VPANDNQZ256rmbk + 2532333576U, // VPANDNQZ256rmbkz + 49305608U, // VPANDNQZ256rmk + 2532333576U, // VPANDNQZ256rmkz + 2517653512U, // VPANDNQZ256rr + 49305608U, // VPANDNQZ256rrk + 2532333576U, // VPANDNQZ256rrkz + 2517653512U, // VPANDNQZrm + 2517653512U, // VPANDNQZrmb + 49305608U, // VPANDNQZrmbk + 2532333576U, // VPANDNQZrmbkz + 49305608U, // VPANDNQZrmk + 2532333576U, // VPANDNQZrmkz + 2517653512U, // VPANDNQZrr + 49305608U, // VPANDNQZrrk + 2532333576U, // VPANDNQZrrkz + 2517652604U, // VPANDNYrm + 2517652604U, // VPANDNYrr + 2517652604U, // VPANDNrm + 2517652604U, // VPANDNrr + 2517653183U, // VPANDQZ128rm + 2517653183U, // VPANDQZ128rmb + 49305279U, // VPANDQZ128rmbk + 2532333247U, // VPANDQZ128rmbkz + 49305279U, // VPANDQZ128rmk + 2532333247U, // VPANDQZ128rmkz + 2517653183U, // VPANDQZ128rr + 49305279U, // VPANDQZ128rrk + 2532333247U, // VPANDQZ128rrkz + 2517653183U, // VPANDQZ256rm + 2517653183U, // VPANDQZ256rmb + 49305279U, // VPANDQZ256rmbk + 2532333247U, // VPANDQZ256rmbkz + 49305279U, // VPANDQZ256rmk + 2532333247U, // VPANDQZ256rmkz + 2517653183U, // VPANDQZ256rr + 49305279U, // VPANDQZ256rrk + 2532333247U, // VPANDQZ256rrkz + 2517653183U, // VPANDQZrm + 2517653183U, // VPANDQZrmb + 49305279U, // VPANDQZrmbk + 2532333247U, // VPANDQZrmbkz + 49305279U, // VPANDQZrmk + 2532333247U, // VPANDQZrmkz + 2517653183U, // VPANDQZrr + 49305279U, // VPANDQZrrk + 2532333247U, // VPANDQZrrkz + 2517649588U, // VPANDYrm + 2517649588U, // VPANDYrr + 2517649588U, // VPANDrm + 2517649588U, // VPANDrr + 2517648432U, // VPAVGBYrm + 2517648432U, // VPAVGBYrr + 2517648432U, // VPAVGBZ128rm + 49300528U, // VPAVGBZ128rmk + 2532328496U, // VPAVGBZ128rmkz + 2517648432U, // VPAVGBZ128rr + 49300528U, // VPAVGBZ128rrk + 2532328496U, // VPAVGBZ128rrkz + 2517648432U, // VPAVGBZ256rm + 49300528U, // VPAVGBZ256rmk + 2532328496U, // VPAVGBZ256rmkz + 2517648432U, // VPAVGBZ256rr + 49300528U, // VPAVGBZ256rrk + 2532328496U, // VPAVGBZ256rrkz + 2517648432U, // VPAVGBZrm + 49300528U, // VPAVGBZrmk + 2532328496U, // VPAVGBZrmkz + 2517648432U, // VPAVGBZrr + 49300528U, // VPAVGBZrrk + 2532328496U, // VPAVGBZrrkz + 2517648432U, // VPAVGBrm + 2517648432U, // VPAVGBrr + 2517656689U, // VPAVGWYrm + 2517656689U, // VPAVGWYrr + 2517656689U, // VPAVGWZ128rm + 49308785U, // VPAVGWZ128rmk + 2532336753U, // VPAVGWZ128rmkz + 2517656689U, // VPAVGWZ128rr + 49308785U, // VPAVGWZ128rrk + 2532336753U, // VPAVGWZ128rrkz + 2517656689U, // VPAVGWZ256rm + 49308785U, // VPAVGWZ256rmk + 2532336753U, // VPAVGWZ256rmkz + 2517656689U, // VPAVGWZ256rr + 49308785U, // VPAVGWZ256rrk + 2532336753U, // VPAVGWZ256rrkz + 2517656689U, // VPAVGWZrm + 49308785U, // VPAVGWZrmk + 2532336753U, // VPAVGWZrmkz + 2517656689U, // VPAVGWZrr + 49308785U, // VPAVGWZrrk + 2532336753U, // VPAVGWZrrkz + 2517656689U, // VPAVGWrm + 2517656689U, // VPAVGWrr + 2517649336U, // VPBLENDDYrmi + 2517649336U, // VPBLENDDYrri + 2517649336U, // VPBLENDDrmi + 2517649336U, // VPBLENDDrri + 2517648485U, // VPBLENDMBZ128rm + 384844901U, // VPBLENDMBZ128rmk + 2532328549U, // VPBLENDMBZ128rmkz + 2517648485U, // VPBLENDMBZ128rr + 384844901U, // VPBLENDMBZ128rrk + 2532328549U, // VPBLENDMBZ128rrkz + 2517648485U, // VPBLENDMBZ256rm + 384844901U, // VPBLENDMBZ256rmk + 2532328549U, // VPBLENDMBZ256rmkz + 2517648485U, // VPBLENDMBZ256rr + 384844901U, // VPBLENDMBZ256rrk + 2532328549U, // VPBLENDMBZ256rrkz + 2517648485U, // VPBLENDMBZrm + 384844901U, // VPBLENDMBZrmk + 2532328549U, // VPBLENDMBZrmkz + 2517648485U, // VPBLENDMBZrr + 384844901U, // VPBLENDMBZrrk + 2532328549U, // VPBLENDMBZrrkz + 2517649540U, // VPBLENDMDZ128rm + 2517649540U, // VPBLENDMDZ128rmb + 384845956U, // VPBLENDMDZ128rmbk + 2532329604U, // VPBLENDMDZ128rmbkz + 384845956U, // VPBLENDMDZ128rmk + 2532329604U, // VPBLENDMDZ128rmkz + 2517649540U, // VPBLENDMDZ128rr + 384845956U, // VPBLENDMDZ128rrk + 2532329604U, // VPBLENDMDZ128rrkz + 2517649540U, // VPBLENDMDZ256rm + 2517649540U, // VPBLENDMDZ256rmb + 384845956U, // VPBLENDMDZ256rmbk + 2532329604U, // VPBLENDMDZ256rmbkz + 384845956U, // VPBLENDMDZ256rmk + 2532329604U, // VPBLENDMDZ256rmkz + 2517649540U, // VPBLENDMDZ256rr + 384845956U, // VPBLENDMDZ256rrk + 2532329604U, // VPBLENDMDZ256rrkz + 2517649540U, // VPBLENDMDZrm + 2517649540U, // VPBLENDMDZrmb + 384845956U, // VPBLENDMDZrmbk + 2532329604U, // VPBLENDMDZrmbkz + 384845956U, // VPBLENDMDZrmk + 2532329604U, // VPBLENDMDZrmkz + 2517649540U, // VPBLENDMDZrr + 384845956U, // VPBLENDMDZrrk + 2532329604U, // VPBLENDMDZrrkz + 2517653456U, // VPBLENDMQZ128rm + 2517653456U, // VPBLENDMQZ128rmb + 384849872U, // VPBLENDMQZ128rmbk + 2532333520U, // VPBLENDMQZ128rmbkz + 384849872U, // VPBLENDMQZ128rmk + 2532333520U, // VPBLENDMQZ128rmkz + 2517653456U, // VPBLENDMQZ128rr + 384849872U, // VPBLENDMQZ128rrk + 2532333520U, // VPBLENDMQZ128rrkz + 2517653456U, // VPBLENDMQZ256rm + 2517653456U, // VPBLENDMQZ256rmb + 384849872U, // VPBLENDMQZ256rmbk + 2532333520U, // VPBLENDMQZ256rmbkz + 384849872U, // VPBLENDMQZ256rmk + 2532333520U, // VPBLENDMQZ256rmkz + 2517653456U, // VPBLENDMQZ256rr + 384849872U, // VPBLENDMQZ256rrk + 2532333520U, // VPBLENDMQZ256rrkz + 2517653456U, // VPBLENDMQZrm + 2517653456U, // VPBLENDMQZrmb + 384849872U, // VPBLENDMQZrmbk + 2532333520U, // VPBLENDMQZrmbkz + 384849872U, // VPBLENDMQZrmk + 2532333520U, // VPBLENDMQZrmkz + 2517653456U, // VPBLENDMQZrr + 384849872U, // VPBLENDMQZrrk + 2532333520U, // VPBLENDMQZrrkz + 2517656787U, // VPBLENDMWZ128rm + 384853203U, // VPBLENDMWZ128rmk + 2532336851U, // VPBLENDMWZ128rmkz + 2517656787U, // VPBLENDMWZ128rr + 384853203U, // VPBLENDMWZ128rrk + 2532336851U, // VPBLENDMWZ128rrkz + 2517656787U, // VPBLENDMWZ256rm + 384853203U, // VPBLENDMWZ256rmk + 2532336851U, // VPBLENDMWZ256rmkz + 2517656787U, // VPBLENDMWZ256rr + 384853203U, // VPBLENDMWZ256rrk + 2532336851U, // VPBLENDMWZ256rrkz + 2517656787U, // VPBLENDMWZrm + 384853203U, // VPBLENDMWZrmk + 2532336851U, // VPBLENDMWZrmkz + 2517656787U, // VPBLENDMWZrr + 384853203U, // VPBLENDMWZrrk + 2532336851U, // VPBLENDMWZrrkz + 2517648942U, // VPBLENDVBYrm + 2517648942U, // VPBLENDVBYrr + 2517648942U, // VPBLENDVBrm + 2517648942U, // VPBLENDVBrr + 2517656603U, // VPBLENDWYrmi + 2517656603U, // VPBLENDWYrri + 2517656603U, // VPBLENDWrmi + 2517656603U, // VPBLENDWrri + 537937372U, // VPBROADCASTBYrm + 370165212U, // VPBROADCASTBYrr + 537937372U, // VPBROADCASTBZ128m + 49300956U, // VPBROADCASTBZ128mk + 2532328924U, // VPBROADCASTBZ128mkz + 370165212U, // VPBROADCASTBZ128r + 49300956U, // VPBROADCASTBZ128rk + 2532328924U, // VPBROADCASTBZ128rkz + 537937372U, // VPBROADCASTBZ256m + 49300956U, // VPBROADCASTBZ256mk + 2532328924U, // VPBROADCASTBZ256mkz + 370165212U, // VPBROADCASTBZ256r + 49300956U, // VPBROADCASTBZ256rk + 2532328924U, // VPBROADCASTBZ256rkz + 537937372U, // VPBROADCASTBZm + 49300956U, // VPBROADCASTBZmk + 2532328924U, // VPBROADCASTBZmkz + 370165212U, // VPBROADCASTBZr + 49300956U, // VPBROADCASTBZrk + 2532328924U, // VPBROADCASTBZrkz + 370165212U, // VPBROADCASTBrZ128r + 49300956U, // VPBROADCASTBrZ128rk + 2532328924U, // VPBROADCASTBrZ128rkz + 370165212U, // VPBROADCASTBrZ256r + 49300956U, // VPBROADCASTBrZ256rk + 2532328924U, // VPBROADCASTBrZ256rkz + 370165212U, // VPBROADCASTBrZr + 49300956U, // VPBROADCASTBrZrk + 2532328924U, // VPBROADCASTBrZrkz + 537937372U, // VPBROADCASTBrm + 370165212U, // VPBROADCASTBrr + 403722224U, // VPBROADCASTDYrm + 370167792U, // VPBROADCASTDYrr + 403722224U, // VPBROADCASTDZ128m + 49303536U, // VPBROADCASTDZ128mk + 2532331504U, // VPBROADCASTDZ128mkz + 370167792U, // VPBROADCASTDZ128r + 49303536U, // VPBROADCASTDZ128rk + 2532331504U, // VPBROADCASTDZ128rkz + 403722224U, // VPBROADCASTDZ256m + 49303536U, // VPBROADCASTDZ256mk + 2532331504U, // VPBROADCASTDZ256mkz + 370167792U, // VPBROADCASTDZ256r + 49303536U, // VPBROADCASTDZ256rk + 2532331504U, // VPBROADCASTDZ256rkz + 403722224U, // VPBROADCASTDZm + 49303536U, // VPBROADCASTDZmk + 2532331504U, // VPBROADCASTDZmkz + 370167792U, // VPBROADCASTDZr + 49303536U, // VPBROADCASTDZrk + 2532331504U, // VPBROADCASTDZrkz + 370167792U, // VPBROADCASTDrZ128r + 49303536U, // VPBROADCASTDrZ128rk + 2532331504U, // VPBROADCASTDrZ128rkz + 370167792U, // VPBROADCASTDrZ256r + 49303536U, // VPBROADCASTDrZ256rk + 2532331504U, // VPBROADCASTDrZ256rkz + 370167792U, // VPBROADCASTDrZr + 49303536U, // VPBROADCASTDrZrk + 2532331504U, // VPBROADCASTDrZrkz + 403722224U, // VPBROADCASTDrm + 370167792U, // VPBROADCASTDrr + 370169245U, // VPBROADCASTMB2QZ128rr + 370169245U, // VPBROADCASTMB2QZ256rr + 370169245U, // VPBROADCASTMB2QZrr + 370165503U, // VPBROADCASTMW2DZ128rr + 370165503U, // VPBROADCASTMW2DZ256rr + 370165503U, // VPBROADCASTMW2DZrr + 437279124U, // VPBROADCASTQYrm + 370170260U, // VPBROADCASTQYrr + 437279124U, // VPBROADCASTQZ128m + 49306004U, // VPBROADCASTQZ128mk + 2532333972U, // VPBROADCASTQZ128mkz + 370170260U, // VPBROADCASTQZ128r + 49306004U, // VPBROADCASTQZ128rk + 2532333972U, // VPBROADCASTQZ128rkz + 437279124U, // VPBROADCASTQZ256m + 49306004U, // VPBROADCASTQZ256mk + 2532333972U, // VPBROADCASTQZ256mkz + 370170260U, // VPBROADCASTQZ256r + 49306004U, // VPBROADCASTQZ256rk + 2532333972U, // VPBROADCASTQZ256rkz + 437279124U, // VPBROADCASTQZm + 49306004U, // VPBROADCASTQZmk + 2532333972U, // VPBROADCASTQZmkz + 370170260U, // VPBROADCASTQZr + 49306004U, // VPBROADCASTQZrk + 2532333972U, // VPBROADCASTQZrkz + 370170260U, // VPBROADCASTQrZ128r + 49306004U, // VPBROADCASTQrZ128rk + 2532333972U, // VPBROADCASTQrZ128rkz + 370170260U, // VPBROADCASTQrZ256r + 49306004U, // VPBROADCASTQrZ256rk + 2532333972U, // VPBROADCASTQrZ256rkz + 370170260U, // VPBROADCASTQrZr + 49306004U, // VPBROADCASTQrZrk + 2532333972U, // VPBROADCASTQrZrkz + 437279124U, // VPBROADCASTQrm + 370170260U, // VPBROADCASTQrr + 504391240U, // VPBROADCASTWYrm + 370173512U, // VPBROADCASTWYrr + 504391240U, // VPBROADCASTWZ128m + 49309256U, // VPBROADCASTWZ128mk + 2532337224U, // VPBROADCASTWZ128mkz + 370173512U, // VPBROADCASTWZ128r + 49309256U, // VPBROADCASTWZ128rk + 2532337224U, // VPBROADCASTWZ128rkz + 504391240U, // VPBROADCASTWZ256m + 49309256U, // VPBROADCASTWZ256mk + 2532337224U, // VPBROADCASTWZ256mkz + 370173512U, // VPBROADCASTWZ256r + 49309256U, // VPBROADCASTWZ256rk + 2532337224U, // VPBROADCASTWZ256rkz + 504391240U, // VPBROADCASTWZm + 49309256U, // VPBROADCASTWZmk + 2532337224U, // VPBROADCASTWZmkz + 370173512U, // VPBROADCASTWZr + 49309256U, // VPBROADCASTWZrk + 2532337224U, // VPBROADCASTWZrkz + 370173512U, // VPBROADCASTWrZ128r + 49309256U, // VPBROADCASTWrZ128rk + 2532337224U, // VPBROADCASTWrZ128rkz + 370173512U, // VPBROADCASTWrZ256r + 49309256U, // VPBROADCASTWrZ256rk + 2532337224U, // VPBROADCASTWrZ256rkz + 370173512U, // VPBROADCASTWrZr + 49309256U, // VPBROADCASTWrZrk + 2532337224U, // VPBROADCASTWrZrkz + 504391240U, // VPBROADCASTWrm + 370173512U, // VPBROADCASTWrr + 2517653228U, // VPCLMULQDQYrm + 2517653228U, // VPCLMULQDQYrr + 2517653228U, // VPCLMULQDQZ128rm + 2517653228U, // VPCLMULQDQZ128rr + 2517653228U, // VPCLMULQDQZ256rm + 2517653228U, // VPCLMULQDQZ256rr + 2517653228U, // VPCLMULQDQZrm + 2517653228U, // VPCLMULQDQZrr + 2517653228U, // VPCLMULQDQrm + 2517653228U, // VPCLMULQDQrr + 2517656341U, // VPCMOVYrmr + 2517656341U, // VPCMOVYrrm + 2517656341U, // VPCMOVYrrr + 2517656341U, // VPCMOVYrrr_REV + 2517656341U, // VPCMOVrmr + 2517656341U, // VPCMOVrrm + 2517656341U, // VPCMOVrrr + 2517656341U, // VPCMOVrrr_REV + 588459324U, // VPCMPBZ128rmi + 2517648564U, // VPCMPBZ128rmi_alt + 3239619900U, // VPCMPBZ128rmik + 384844980U, // VPCMPBZ128rmik_alt + 588475708U, // VPCMPBZ128rri + 2517648564U, // VPCMPBZ128rri_alt + 3239636284U, // VPCMPBZ128rrik + 384844980U, // VPCMPBZ128rrik_alt + 588459324U, // VPCMPBZ256rmi + 2517648564U, // VPCMPBZ256rmi_alt + 1092136252U, // VPCMPBZ256rmik + 384844980U, // VPCMPBZ256rmik_alt + 588475708U, // VPCMPBZ256rri + 2517648564U, // VPCMPBZ256rri_alt + 3239636284U, // VPCMPBZ256rrik + 384844980U, // VPCMPBZ256rrik_alt + 588459324U, // VPCMPBZrmi + 2517648564U, // VPCMPBZrmi_alt + 3239619900U, // VPCMPBZrmik + 384844980U, // VPCMPBZrmik_alt + 588475708U, // VPCMPBZrri + 2517648564U, // VPCMPBZrri_alt + 3239636284U, // VPCMPBZrrik + 384844980U, // VPCMPBZrrik_alt + 589507900U, // VPCMPDZ128rmi + 2517650375U, // VPCMPDZ128rmi_alt + 589507900U, // VPCMPDZ128rmib + 2517650375U, // VPCMPDZ128rmib_alt + 1093184828U, // VPCMPDZ128rmibk + 384846791U, // VPCMPDZ128rmibk_alt + 3240668476U, // VPCMPDZ128rmik + 384846791U, // VPCMPDZ128rmik_alt + 589524284U, // VPCMPDZ128rri + 2517650375U, // VPCMPDZ128rri_alt + 3240684860U, // VPCMPDZ128rrik + 384846791U, // VPCMPDZ128rrik_alt + 589507900U, // VPCMPDZ256rmi + 2517650375U, // VPCMPDZ256rmi_alt + 589507900U, // VPCMPDZ256rmib + 2517650375U, // VPCMPDZ256rmib_alt + 1093184828U, // VPCMPDZ256rmibk + 384846791U, // VPCMPDZ256rmibk_alt + 1093184828U, // VPCMPDZ256rmik + 384846791U, // VPCMPDZ256rmik_alt + 589524284U, // VPCMPDZ256rri + 2517650375U, // VPCMPDZ256rri_alt + 3240684860U, // VPCMPDZ256rrik + 384846791U, // VPCMPDZ256rrik_alt + 589507900U, // VPCMPDZrmi + 2517650375U, // VPCMPDZrmi_alt + 589507900U, // VPCMPDZrmib + 2517650375U, // VPCMPDZrmib_alt + 1093184828U, // VPCMPDZrmibk + 384846791U, // VPCMPDZrmibk_alt + 3240668476U, // VPCMPDZrmik + 384846791U, // VPCMPDZrmik_alt + 589524284U, // VPCMPDZrri + 2517650375U, // VPCMPDZrri_alt + 3240684860U, // VPCMPDZrrik + 384846791U, // VPCMPDZrrik_alt + 2517648588U, // VPCMPEQBYrm + 2517648588U, // VPCMPEQBYrr + 2517648588U, // VPCMPEQBZ128rm + 384845004U, // VPCMPEQBZ128rmk + 2517648588U, // VPCMPEQBZ128rr + 384845004U, // VPCMPEQBZ128rrk + 2517648588U, // VPCMPEQBZ256rm + 384845004U, // VPCMPEQBZ256rmk + 2517648588U, // VPCMPEQBZ256rr + 384845004U, // VPCMPEQBZ256rrk + 2517648588U, // VPCMPEQBZrm + 384845004U, // VPCMPEQBZrmk + 2517648588U, // VPCMPEQBZrr + 384845004U, // VPCMPEQBZrrk + 2517648588U, // VPCMPEQBrm + 2517648588U, // VPCMPEQBrr + 2517650638U, // VPCMPEQDYrm + 2517650638U, // VPCMPEQDYrr + 2517650638U, // VPCMPEQDZ128rm + 2517650638U, // VPCMPEQDZ128rmb + 384847054U, // VPCMPEQDZ128rmbk + 384847054U, // VPCMPEQDZ128rmk + 2517650638U, // VPCMPEQDZ128rr + 384847054U, // VPCMPEQDZ128rrk + 2517650638U, // VPCMPEQDZ256rm + 2517650638U, // VPCMPEQDZ256rmb + 384847054U, // VPCMPEQDZ256rmbk + 384847054U, // VPCMPEQDZ256rmk + 2517650638U, // VPCMPEQDZ256rr + 384847054U, // VPCMPEQDZ256rrk + 2517650638U, // VPCMPEQDZrm + 2517650638U, // VPCMPEQDZrmb + 384847054U, // VPCMPEQDZrmbk + 384847054U, // VPCMPEQDZrmk + 2517650638U, // VPCMPEQDZrr + 384847054U, // VPCMPEQDZrrk + 2517650638U, // VPCMPEQDrm + 2517650638U, // VPCMPEQDrr + 2517653601U, // VPCMPEQQYrm + 2517653601U, // VPCMPEQQYrr + 2517653601U, // VPCMPEQQZ128rm + 2517653601U, // VPCMPEQQZ128rmb + 384850017U, // VPCMPEQQZ128rmbk + 384850017U, // VPCMPEQQZ128rmk + 2517653601U, // VPCMPEQQZ128rr + 384850017U, // VPCMPEQQZ128rrk + 2517653601U, // VPCMPEQQZ256rm + 2517653601U, // VPCMPEQQZ256rmb + 384850017U, // VPCMPEQQZ256rmbk + 384850017U, // VPCMPEQQZ256rmk + 2517653601U, // VPCMPEQQZ256rr + 384850017U, // VPCMPEQQZ256rrk + 2517653601U, // VPCMPEQQZrm + 2517653601U, // VPCMPEQQZrmb + 384850017U, // VPCMPEQQZrmbk + 384850017U, // VPCMPEQQZrmk + 2517653601U, // VPCMPEQQZrr + 384850017U, // VPCMPEQQZrrk + 2517653601U, // VPCMPEQQrm + 2517653601U, // VPCMPEQQrr + 2517656860U, // VPCMPEQWYrm + 2517656860U, // VPCMPEQWYrr + 2517656860U, // VPCMPEQWZ128rm + 384853276U, // VPCMPEQWZ128rmk + 2517656860U, // VPCMPEQWZ128rr + 384853276U, // VPCMPEQWZ128rrk + 2517656860U, // VPCMPEQWZ256rm + 384853276U, // VPCMPEQWZ256rmk + 2517656860U, // VPCMPEQWZ256rr + 384853276U, // VPCMPEQWZ256rrk + 2517656860U, // VPCMPEQWZrm + 384853276U, // VPCMPEQWZrmk + 2517656860U, // VPCMPEQWZrr + 384853276U, // VPCMPEQWZrrk + 2517656860U, // VPCMPEQWrm + 2517656860U, // VPCMPEQWrr + 2484097779U, // VPCMPESTRIrm + 2517652211U, // VPCMPESTRIrr + 2484098141U, // VPCMPESTRMrm + 2517652573U, // VPCMPESTRMrr + 2517648825U, // VPCMPGTBYrm + 2517648825U, // VPCMPGTBYrr + 2517648825U, // VPCMPGTBZ128rm + 384845241U, // VPCMPGTBZ128rmk + 2517648825U, // VPCMPGTBZ128rr + 384845241U, // VPCMPGTBZ128rrk + 2517648825U, // VPCMPGTBZ256rm + 384845241U, // VPCMPGTBZ256rmk + 2517648825U, // VPCMPGTBZ256rr + 384845241U, // VPCMPGTBZ256rrk + 2517648825U, // VPCMPGTBZrm + 384845241U, // VPCMPGTBZrmk + 2517648825U, // VPCMPGTBZrr + 384845241U, // VPCMPGTBZrrk + 2517648825U, // VPCMPGTBrm + 2517648825U, // VPCMPGTBrr + 2517651395U, // VPCMPGTDYrm + 2517651395U, // VPCMPGTDYrr + 2517651395U, // VPCMPGTDZ128rm + 2517651395U, // VPCMPGTDZ128rmb + 384847811U, // VPCMPGTDZ128rmbk + 384847811U, // VPCMPGTDZ128rmk + 2517651395U, // VPCMPGTDZ128rr + 384847811U, // VPCMPGTDZ128rrk + 2517651395U, // VPCMPGTDZ256rm + 2517651395U, // VPCMPGTDZ256rmb + 384847811U, // VPCMPGTDZ256rmbk + 384847811U, // VPCMPGTDZ256rmk + 2517651395U, // VPCMPGTDZ256rr + 384847811U, // VPCMPGTDZ256rrk + 2517651395U, // VPCMPGTDZrm + 2517651395U, // VPCMPGTDZrmb + 384847811U, // VPCMPGTDZrmbk + 384847811U, // VPCMPGTDZrmk + 2517651395U, // VPCMPGTDZrr + 384847811U, // VPCMPGTDZrrk + 2517651395U, // VPCMPGTDrm + 2517651395U, // VPCMPGTDrr + 2517653846U, // VPCMPGTQYrm + 2517653846U, // VPCMPGTQYrr + 2517653846U, // VPCMPGTQZ128rm + 2517653846U, // VPCMPGTQZ128rmb + 384850262U, // VPCMPGTQZ128rmbk + 384850262U, // VPCMPGTQZ128rmk + 2517653846U, // VPCMPGTQZ128rr + 384850262U, // VPCMPGTQZ128rrk + 2517653846U, // VPCMPGTQZ256rm + 2517653846U, // VPCMPGTQZ256rmb + 384850262U, // VPCMPGTQZ256rmbk + 384850262U, // VPCMPGTQZ256rmk + 2517653846U, // VPCMPGTQZ256rr + 384850262U, // VPCMPGTQZ256rrk + 2517653846U, // VPCMPGTQZrm + 2517653846U, // VPCMPGTQZrmb + 384850262U, // VPCMPGTQZrmbk + 384850262U, // VPCMPGTQZrmk + 2517653846U, // VPCMPGTQZrr + 384850262U, // VPCMPGTQZrrk + 2517653846U, // VPCMPGTQrm + 2517653846U, // VPCMPGTQrr + 2517657125U, // VPCMPGTWYrm + 2517657125U, // VPCMPGTWYrr + 2517657125U, // VPCMPGTWZ128rm + 384853541U, // VPCMPGTWZ128rmk + 2517657125U, // VPCMPGTWZ128rr + 384853541U, // VPCMPGTWZ128rrk + 2517657125U, // VPCMPGTWZ256rm + 384853541U, // VPCMPGTWZ256rmk + 2517657125U, // VPCMPGTWZ256rr + 384853541U, // VPCMPGTWZ256rrk + 2517657125U, // VPCMPGTWZrm + 384853541U, // VPCMPGTWZrmk + 2517657125U, // VPCMPGTWZrr + 384853541U, // VPCMPGTWZrrk + 2517657125U, // VPCMPGTWrm + 2517657125U, // VPCMPGTWrr + 2484097791U, // VPCMPISTRIrm + 2517652223U, // VPCMPISTRIrr + 2484098153U, // VPCMPISTRMrm + 2517652585U, // VPCMPISTRMrr + 590556476U, // VPCMPQZ128rmi + 2517653530U, // VPCMPQZ128rmi_alt + 590556476U, // VPCMPQZ128rmib + 2517653530U, // VPCMPQZ128rmib_alt + 3241717052U, // VPCMPQZ128rmibk + 384849946U, // VPCMPQZ128rmibk_alt + 3241717052U, // VPCMPQZ128rmik + 384849946U, // VPCMPQZ128rmik_alt + 590572860U, // VPCMPQZ128rri + 2517653530U, // VPCMPQZ128rri_alt + 3241733436U, // VPCMPQZ128rrik + 384849946U, // VPCMPQZ128rrik_alt + 590556476U, // VPCMPQZ256rmi + 2517653530U, // VPCMPQZ256rmi_alt + 590556476U, // VPCMPQZ256rmib + 2517653530U, // VPCMPQZ256rmib_alt + 3241717052U, // VPCMPQZ256rmibk + 384849946U, // VPCMPQZ256rmibk_alt + 1094233404U, // VPCMPQZ256rmik + 384849946U, // VPCMPQZ256rmik_alt + 590572860U, // VPCMPQZ256rri + 2517653530U, // VPCMPQZ256rri_alt + 3241733436U, // VPCMPQZ256rrik + 384849946U, // VPCMPQZ256rrik_alt + 590556476U, // VPCMPQZrmi + 2517653530U, // VPCMPQZrmi_alt + 590556476U, // VPCMPQZrmib + 2517653530U, // VPCMPQZrmib_alt + 3241717052U, // VPCMPQZrmibk + 384849946U, // VPCMPQZrmibk_alt + 3241717052U, // VPCMPQZrmik + 384849946U, // VPCMPQZrmik_alt + 590572860U, // VPCMPQZrri + 2517653530U, // VPCMPQZrri_alt + 3241733436U, // VPCMPQZrrik + 384849946U, // VPCMPQZrrik_alt + 591605052U, // VPCMPUBZ128rmi + 2517648910U, // VPCMPUBZ128rmi_alt + 3242765628U, // VPCMPUBZ128rmik + 384845326U, // VPCMPUBZ128rmik_alt + 591621436U, // VPCMPUBZ128rri + 2517648910U, // VPCMPUBZ128rri_alt + 3242782012U, // VPCMPUBZ128rrik + 384845326U, // VPCMPUBZ128rrik_alt + 591605052U, // VPCMPUBZ256rmi + 2517648910U, // VPCMPUBZ256rmi_alt + 1095281980U, // VPCMPUBZ256rmik + 384845326U, // VPCMPUBZ256rmik_alt + 591621436U, // VPCMPUBZ256rri + 2517648910U, // VPCMPUBZ256rri_alt + 3242782012U, // VPCMPUBZ256rrik + 384845326U, // VPCMPUBZ256rrik_alt + 591605052U, // VPCMPUBZrmi + 2517648910U, // VPCMPUBZrmi_alt + 3242765628U, // VPCMPUBZrmik + 384845326U, // VPCMPUBZrmik_alt + 591621436U, // VPCMPUBZrri + 2517648910U, // VPCMPUBZrri_alt + 3242782012U, // VPCMPUBZrrik + 384845326U, // VPCMPUBZrrik_alt + 592653628U, // VPCMPUDZ128rmi + 2517651490U, // VPCMPUDZ128rmi_alt + 592653628U, // VPCMPUDZ128rmib + 2517651490U, // VPCMPUDZ128rmib_alt + 1096330556U, // VPCMPUDZ128rmibk + 384847906U, // VPCMPUDZ128rmibk_alt + 3243814204U, // VPCMPUDZ128rmik + 384847906U, // VPCMPUDZ128rmik_alt + 592670012U, // VPCMPUDZ128rri + 2517651490U, // VPCMPUDZ128rri_alt + 3243830588U, // VPCMPUDZ128rrik + 384847906U, // VPCMPUDZ128rrik_alt + 592653628U, // VPCMPUDZ256rmi + 2517651490U, // VPCMPUDZ256rmi_alt + 592653628U, // VPCMPUDZ256rmib + 2517651490U, // VPCMPUDZ256rmib_alt + 1096330556U, // VPCMPUDZ256rmibk + 384847906U, // VPCMPUDZ256rmibk_alt + 1096330556U, // VPCMPUDZ256rmik + 384847906U, // VPCMPUDZ256rmik_alt + 592670012U, // VPCMPUDZ256rri + 2517651490U, // VPCMPUDZ256rri_alt + 3243830588U, // VPCMPUDZ256rrik + 384847906U, // VPCMPUDZ256rrik_alt + 592653628U, // VPCMPUDZrmi + 2517651490U, // VPCMPUDZrmi_alt + 592653628U, // VPCMPUDZrmib + 2517651490U, // VPCMPUDZrmib_alt + 1096330556U, // VPCMPUDZrmibk + 384847906U, // VPCMPUDZrmibk_alt + 3243814204U, // VPCMPUDZrmik + 384847906U, // VPCMPUDZrmik_alt + 592670012U, // VPCMPUDZrri + 2517651490U, // VPCMPUDZrri_alt + 3243830588U, // VPCMPUDZrrik + 384847906U, // VPCMPUDZrrik_alt + 593702204U, // VPCMPUQZ128rmi + 2517653984U, // VPCMPUQZ128rmi_alt + 593702204U, // VPCMPUQZ128rmib + 2517653984U, // VPCMPUQZ128rmib_alt + 3244862780U, // VPCMPUQZ128rmibk + 384850400U, // VPCMPUQZ128rmibk_alt + 3244862780U, // VPCMPUQZ128rmik + 384850400U, // VPCMPUQZ128rmik_alt + 593718588U, // VPCMPUQZ128rri + 2517653984U, // VPCMPUQZ128rri_alt + 3244879164U, // VPCMPUQZ128rrik + 384850400U, // VPCMPUQZ128rrik_alt + 593702204U, // VPCMPUQZ256rmi + 2517653984U, // VPCMPUQZ256rmi_alt + 593702204U, // VPCMPUQZ256rmib + 2517653984U, // VPCMPUQZ256rmib_alt + 3244862780U, // VPCMPUQZ256rmibk + 384850400U, // VPCMPUQZ256rmibk_alt + 1097379132U, // VPCMPUQZ256rmik + 384850400U, // VPCMPUQZ256rmik_alt + 593718588U, // VPCMPUQZ256rri + 2517653984U, // VPCMPUQZ256rri_alt + 3244879164U, // VPCMPUQZ256rrik + 384850400U, // VPCMPUQZ256rrik_alt + 593702204U, // VPCMPUQZrmi + 2517653984U, // VPCMPUQZrmi_alt + 593702204U, // VPCMPUQZrmib + 2517653984U, // VPCMPUQZrmib_alt + 3244862780U, // VPCMPUQZrmibk + 384850400U, // VPCMPUQZrmibk_alt + 3244862780U, // VPCMPUQZrmik + 384850400U, // VPCMPUQZrmik_alt + 593718588U, // VPCMPUQZrri + 2517653984U, // VPCMPUQZrri_alt + 3244879164U, // VPCMPUQZrrik + 384850400U, // VPCMPUQZrrik_alt + 594750780U, // VPCMPUWZ128rmi + 2517657220U, // VPCMPUWZ128rmi_alt + 3245911356U, // VPCMPUWZ128rmik + 384853636U, // VPCMPUWZ128rmik_alt + 594767164U, // VPCMPUWZ128rri + 2517657220U, // VPCMPUWZ128rri_alt + 3245927740U, // VPCMPUWZ128rrik + 384853636U, // VPCMPUWZ128rrik_alt + 594750780U, // VPCMPUWZ256rmi + 2517657220U, // VPCMPUWZ256rmi_alt + 1098427708U, // VPCMPUWZ256rmik + 384853636U, // VPCMPUWZ256rmik_alt + 594767164U, // VPCMPUWZ256rri + 2517657220U, // VPCMPUWZ256rri_alt + 3245927740U, // VPCMPUWZ256rrik + 384853636U, // VPCMPUWZ256rrik_alt + 594750780U, // VPCMPUWZrmi + 2517657220U, // VPCMPUWZrmi_alt + 3245911356U, // VPCMPUWZrmik + 384853636U, // VPCMPUWZrmik_alt + 594767164U, // VPCMPUWZrri + 2517657220U, // VPCMPUWZrri_alt + 3245927740U, // VPCMPUWZrrik + 384853636U, // VPCMPUWZrrik_alt + 595799356U, // VPCMPWZ128rmi + 2517656852U, // VPCMPWZ128rmi_alt + 3246959932U, // VPCMPWZ128rmik + 384853268U, // VPCMPWZ128rmik_alt + 595815740U, // VPCMPWZ128rri + 2517656852U, // VPCMPWZ128rri_alt + 3246976316U, // VPCMPWZ128rrik + 384853268U, // VPCMPWZ128rrik_alt + 595799356U, // VPCMPWZ256rmi + 2517656852U, // VPCMPWZ256rmi_alt + 1099476284U, // VPCMPWZ256rmik + 384853268U, // VPCMPWZ256rmik_alt + 595815740U, // VPCMPWZ256rri + 2517656852U, // VPCMPWZ256rri_alt + 3246976316U, // VPCMPWZ256rrik + 384853268U, // VPCMPWZ256rrik_alt + 595799356U, // VPCMPWZrmi + 2517656852U, // VPCMPWZrmi_alt + 3246959932U, // VPCMPWZrmik + 384853268U, // VPCMPWZrmik_alt + 595815740U, // VPCMPWZrri + 2517656852U, // VPCMPWZrri_alt + 3246976316U, // VPCMPWZrrik + 384853268U, // VPCMPWZrrik_alt + 588918014U, // VPCOMBmi + 2517648507U, // VPCOMBmi_alt + 588934398U, // VPCOMBri + 2517648507U, // VPCOMBri_alt + 589966590U, // VPCOMDmi + 2517649562U, // VPCOMDmi_alt + 589982974U, // VPCOMDri + 2517649562U, // VPCOMDri_alt + 1197433U, // VPCOMPRESSBZ128mr + 15877497U, // VPCOMPRESSBZ128mrk + 370165113U, // VPCOMPRESSBZ128rr + 49300857U, // VPCOMPRESSBZ128rrk + 2532328825U, // VPCOMPRESSBZ128rrkz + 1672569U, // VPCOMPRESSBZ256mr + 16352633U, // VPCOMPRESSBZ256mrk + 370165113U, // VPCOMPRESSBZ256rr + 49300857U, // VPCOMPRESSBZ256rrk + 2532328825U, // VPCOMPRESSBZ256rrkz + 1688953U, // VPCOMPRESSBZmr + 16369017U, // VPCOMPRESSBZmrk + 370165113U, // VPCOMPRESSBZrr + 49300857U, // VPCOMPRESSBZrrk + 2532328825U, // VPCOMPRESSBZrrkz + 1199897U, // VPCOMPRESSDZ128mr + 15879961U, // VPCOMPRESSDZ128mrk + 370167577U, // VPCOMPRESSDZ128rr + 49303321U, // VPCOMPRESSDZ128rrk + 2532331289U, // VPCOMPRESSDZ128rrkz + 1675033U, // VPCOMPRESSDZ256mr + 16355097U, // VPCOMPRESSDZ256mrk + 370167577U, // VPCOMPRESSDZ256rr + 49303321U, // VPCOMPRESSDZ256rrk + 2532331289U, // VPCOMPRESSDZ256rrkz + 1691417U, // VPCOMPRESSDZmr + 16371481U, // VPCOMPRESSDZmrk + 370167577U, // VPCOMPRESSDZrr + 49303321U, // VPCOMPRESSDZrrk + 2532331289U, // VPCOMPRESSDZrrkz + 1202461U, // VPCOMPRESSQZ128mr + 15882525U, // VPCOMPRESSQZ128mrk + 370170141U, // VPCOMPRESSQZ128rr + 49305885U, // VPCOMPRESSQZ128rrk + 2532333853U, // VPCOMPRESSQZ128rrkz + 1677597U, // VPCOMPRESSQZ256mr + 16357661U, // VPCOMPRESSQZ256mrk + 370170141U, // VPCOMPRESSQZ256rr + 49305885U, // VPCOMPRESSQZ256rrk + 2532333853U, // VPCOMPRESSQZ256rrkz + 1693981U, // VPCOMPRESSQZmr + 16374045U, // VPCOMPRESSQZmrk + 370170141U, // VPCOMPRESSQZrr + 49305885U, // VPCOMPRESSQZrrk + 2532333853U, // VPCOMPRESSQZrrkz + 1205740U, // VPCOMPRESSWZ128mr + 15885804U, // VPCOMPRESSWZ128mrk + 370173420U, // VPCOMPRESSWZ128rr + 49309164U, // VPCOMPRESSWZ128rrk + 2532337132U, // VPCOMPRESSWZ128rrkz + 1680876U, // VPCOMPRESSWZ256mr + 16360940U, // VPCOMPRESSWZ256mrk + 370173420U, // VPCOMPRESSWZ256rr + 49309164U, // VPCOMPRESSWZ256rrk + 2532337132U, // VPCOMPRESSWZ256rrkz + 1697260U, // VPCOMPRESSWZmr + 16377324U, // VPCOMPRESSWZmrk + 370173420U, // VPCOMPRESSWZrr + 49309164U, // VPCOMPRESSWZrrk + 2532337132U, // VPCOMPRESSWZrrkz + 591015166U, // VPCOMQmi + 2517653478U, // VPCOMQmi_alt + 591031550U, // VPCOMQri + 2517653478U, // VPCOMQri_alt + 592063742U, // VPCOMUBmi + 2517648892U, // VPCOMUBmi_alt + 592080126U, // VPCOMUBri + 2517648892U, // VPCOMUBri_alt + 593112318U, // VPCOMUDmi + 2517651472U, // VPCOMUDmi_alt + 593128702U, // VPCOMUDri + 2517651472U, // VPCOMUDri_alt + 594160894U, // VPCOMUQmi + 2517653966U, // VPCOMUQmi_alt + 594177278U, // VPCOMUQri + 2517653966U, // VPCOMUQri_alt + 595209470U, // VPCOMUWmi + 2517657202U, // VPCOMUWmi_alt + 595225854U, // VPCOMUWri + 2517657202U, // VPCOMUWri_alt + 596258046U, // VPCOMWmi + 2517656809U, // VPCOMWmi_alt + 596274430U, // VPCOMWri + 2517656809U, // VPCOMWri_alt + 336613302U, // VPCONFLICTDZ128rm + 2551205814U, // VPCONFLICTDZ128rmb + 49303478U, // VPCONFLICTDZ128rmbk + 2532331446U, // VPCONFLICTDZ128rmbkz + 49303478U, // VPCONFLICTDZ128rmk + 2532331446U, // VPCONFLICTDZ128rmkz + 370167734U, // VPCONFLICTDZ128rr + 49303478U, // VPCONFLICTDZ128rrk + 2532331446U, // VPCONFLICTDZ128rrkz + 1041256374U, // VPCONFLICTDZ256rm + 403722166U, // VPCONFLICTDZ256rmb + 49303478U, // VPCONFLICTDZ256rmbk + 2532331446U, // VPCONFLICTDZ256rmbkz + 49303478U, // VPCONFLICTDZ256rmk + 2532331446U, // VPCONFLICTDZ256rmkz + 370167734U, // VPCONFLICTDZ256rr + 49303478U, // VPCONFLICTDZ256rrk + 2532331446U, // VPCONFLICTDZ256rrkz + 806375350U, // VPCONFLICTDZrm + 2551205814U, // VPCONFLICTDZrmb + 49303478U, // VPCONFLICTDZrmbk + 2532331446U, // VPCONFLICTDZrmbkz + 49303478U, // VPCONFLICTDZrmk + 2532331446U, // VPCONFLICTDZrmkz + 370167734U, // VPCONFLICTDZrr + 49303478U, // VPCONFLICTDZrrk + 2532331446U, // VPCONFLICTDZrrkz + 336615753U, // VPCONFLICTQZ128rm + 437279049U, // VPCONFLICTQZ128rmb + 49305929U, // VPCONFLICTQZ128rmbk + 2532333897U, // VPCONFLICTQZ128rmbkz + 49305929U, // VPCONFLICTQZ128rmk + 2532333897U, // VPCONFLICTQZ128rmkz + 370170185U, // VPCONFLICTQZ128rr + 49305929U, // VPCONFLICTQZ128rrk + 2532333897U, // VPCONFLICTQZ128rrkz + 1041258825U, // VPCONFLICTQZ256rm + 2584762697U, // VPCONFLICTQZ256rmb + 49305929U, // VPCONFLICTQZ256rmbk + 2532333897U, // VPCONFLICTQZ256rmbkz + 49305929U, // VPCONFLICTQZ256rmk + 2532333897U, // VPCONFLICTQZ256rmkz + 370170185U, // VPCONFLICTQZ256rr + 49305929U, // VPCONFLICTQZ256rrk + 2532333897U, // VPCONFLICTQZ256rrkz + 806377801U, // VPCONFLICTQZrm + 437279049U, // VPCONFLICTQZrmb + 49305929U, // VPCONFLICTQZrmbk + 2532333897U, // VPCONFLICTQZrmbkz + 49305929U, // VPCONFLICTQZrmk + 2532333897U, // VPCONFLICTQZrmkz + 370170185U, // VPCONFLICTQZrr + 49305929U, // VPCONFLICTQZrrk + 2532333897U, // VPCONFLICTQZrrkz + 2182110032U, // VPDPBUSDSZ128m + 2182110032U, // VPDPBUSDSZ128mb + 49306448U, // VPDPBUSDSZ128mbk + 2196790096U, // VPDPBUSDSZ128mbkz + 49306448U, // VPDPBUSDSZ128mk + 2196790096U, // VPDPBUSDSZ128mkz + 2182110032U, // VPDPBUSDSZ128r + 49306448U, // VPDPBUSDSZ128rk + 2196790096U, // VPDPBUSDSZ128rkz + 2182110032U, // VPDPBUSDSZ256m + 2182110032U, // VPDPBUSDSZ256mb + 49306448U, // VPDPBUSDSZ256mbk + 2196790096U, // VPDPBUSDSZ256mbkz + 49306448U, // VPDPBUSDSZ256mk + 2196790096U, // VPDPBUSDSZ256mkz + 2182110032U, // VPDPBUSDSZ256r + 49306448U, // VPDPBUSDSZ256rk + 2196790096U, // VPDPBUSDSZ256rkz + 2182110032U, // VPDPBUSDSZm + 2182110032U, // VPDPBUSDSZmb + 49306448U, // VPDPBUSDSZmbk + 2196790096U, // VPDPBUSDSZmbkz + 49306448U, // VPDPBUSDSZmk + 2196790096U, // VPDPBUSDSZmkz + 2182110032U, // VPDPBUSDSZr + 49306448U, // VPDPBUSDSZrk + 2196790096U, // VPDPBUSDSZrkz + 2182107010U, // VPDPBUSDZ128m + 2182107010U, // VPDPBUSDZ128mb + 49303426U, // VPDPBUSDZ128mbk + 2196787074U, // VPDPBUSDZ128mbkz + 49303426U, // VPDPBUSDZ128mk + 2196787074U, // VPDPBUSDZ128mkz + 2182107010U, // VPDPBUSDZ128r + 49303426U, // VPDPBUSDZ128rk + 2196787074U, // VPDPBUSDZ128rkz + 2182107010U, // VPDPBUSDZ256m + 2182107010U, // VPDPBUSDZ256mb + 49303426U, // VPDPBUSDZ256mbk + 2196787074U, // VPDPBUSDZ256mbkz + 49303426U, // VPDPBUSDZ256mk + 2196787074U, // VPDPBUSDZ256mkz + 2182107010U, // VPDPBUSDZ256r + 49303426U, // VPDPBUSDZ256rk + 2196787074U, // VPDPBUSDZ256rkz + 2182107010U, // VPDPBUSDZm + 2182107010U, // VPDPBUSDZmb + 49303426U, // VPDPBUSDZmbk + 2196787074U, // VPDPBUSDZmbkz + 49303426U, // VPDPBUSDZmk + 2196787074U, // VPDPBUSDZmkz + 2182107010U, // VPDPBUSDZr + 49303426U, // VPDPBUSDZrk + 2196787074U, // VPDPBUSDZrkz + 2182110021U, // VPDPWSSDSZ128m + 2182110021U, // VPDPWSSDSZ128mb + 49306437U, // VPDPWSSDSZ128mbk + 2196790085U, // VPDPWSSDSZ128mbkz + 49306437U, // VPDPWSSDSZ128mk + 2196790085U, // VPDPWSSDSZ128mkz + 2182110021U, // VPDPWSSDSZ128r + 49306437U, // VPDPWSSDSZ128rk + 2196790085U, // VPDPWSSDSZ128rkz + 2182110021U, // VPDPWSSDSZ256m + 2182110021U, // VPDPWSSDSZ256mb + 49306437U, // VPDPWSSDSZ256mbk + 2196790085U, // VPDPWSSDSZ256mbkz + 49306437U, // VPDPWSSDSZ256mk + 2196790085U, // VPDPWSSDSZ256mkz + 2182110021U, // VPDPWSSDSZ256r + 49306437U, // VPDPWSSDSZ256rk + 2196790085U, // VPDPWSSDSZ256rkz + 2182110021U, // VPDPWSSDSZm + 2182110021U, // VPDPWSSDSZmb + 49306437U, // VPDPWSSDSZmbk + 2196790085U, // VPDPWSSDSZmbkz + 49306437U, // VPDPWSSDSZmk + 2196790085U, // VPDPWSSDSZmkz + 2182110021U, // VPDPWSSDSZr + 49306437U, // VPDPWSSDSZrk + 2196790085U, // VPDPWSSDSZrkz + 2182106956U, // VPDPWSSDZ128m + 2182106956U, // VPDPWSSDZ128mb + 49303372U, // VPDPWSSDZ128mbk + 2196787020U, // VPDPWSSDZ128mbkz + 49303372U, // VPDPWSSDZ128mk + 2196787020U, // VPDPWSSDZ128mkz + 2182106956U, // VPDPWSSDZ128r + 49303372U, // VPDPWSSDZ128rk + 2196787020U, // VPDPWSSDZ128rkz + 2182106956U, // VPDPWSSDZ256m + 2182106956U, // VPDPWSSDZ256mb + 49303372U, // VPDPWSSDZ256mbk + 2196787020U, // VPDPWSSDZ256mbkz + 49303372U, // VPDPWSSDZ256mk + 2196787020U, // VPDPWSSDZ256mkz + 2182106956U, // VPDPWSSDZ256r + 49303372U, // VPDPWSSDZ256rk + 2196787020U, // VPDPWSSDZ256rkz + 2182106956U, // VPDPWSSDZm + 2182106956U, // VPDPWSSDZmb + 49303372U, // VPDPWSSDZmbk + 2196787020U, // VPDPWSSDZmbkz + 49303372U, // VPDPWSSDZmk + 2196787020U, // VPDPWSSDZmkz + 2182106956U, // VPDPWSSDZr + 49303372U, // VPDPWSSDZrk + 2196787020U, // VPDPWSSDZrkz + 2517647992U, // VPERM2F128rm + 2517647992U, // VPERM2F128rr + 2517648047U, // VPERM2I128rm + 2517648047U, // VPERM2I128rr + 2517648529U, // VPERMBZ128rm + 49300625U, // VPERMBZ128rmk + 2532328593U, // VPERMBZ128rmkz + 2517648529U, // VPERMBZ128rr + 49300625U, // VPERMBZ128rrk + 2532328593U, // VPERMBZ128rrkz + 2517648529U, // VPERMBZ256rm + 49300625U, // VPERMBZ256rmk + 2532328593U, // VPERMBZ256rmkz + 2517648529U, // VPERMBZ256rr + 49300625U, // VPERMBZ256rrk + 2532328593U, // VPERMBZ256rrkz + 2517648529U, // VPERMBZrm + 49300625U, // VPERMBZrmk + 2532328593U, // VPERMBZrmkz + 2517648529U, // VPERMBZrr + 49300625U, // VPERMBZrrk + 2532328593U, // VPERMBZrrkz + 2517649570U, // VPERMDYrm + 2517649570U, // VPERMDYrr + 2517649570U, // VPERMDZ256rm + 2517649570U, // VPERMDZ256rmb + 49301666U, // VPERMDZ256rmbk + 2532329634U, // VPERMDZ256rmbkz + 49301666U, // VPERMDZ256rmk + 2532329634U, // VPERMDZ256rmkz + 2517649570U, // VPERMDZ256rr + 49301666U, // VPERMDZ256rrk + 2532329634U, // VPERMDZ256rrkz + 2517649570U, // VPERMDZrm + 2517649570U, // VPERMDZrmb + 49301666U, // VPERMDZrmbk + 2532329634U, // VPERMDZrmbkz + 49301666U, // VPERMDZrmk + 2532329634U, // VPERMDZrmkz + 2517649570U, // VPERMDZrr + 49301666U, // VPERMDZrrk + 2532329634U, // VPERMDZrrkz + 2182103939U, // VPERMI2B128rm + 49300355U, // VPERMI2B128rmk + 2196784003U, // VPERMI2B128rmkz + 2182103939U, // VPERMI2B128rr + 49300355U, // VPERMI2B128rrk + 2196784003U, // VPERMI2B128rrkz + 2182103939U, // VPERMI2B256rm + 49300355U, // VPERMI2B256rmk + 2196784003U, // VPERMI2B256rmkz + 2182103939U, // VPERMI2B256rr + 49300355U, // VPERMI2B256rrk + 2196784003U, // VPERMI2B256rrkz + 2182103939U, // VPERMI2Brm + 49300355U, // VPERMI2Brmk + 2196784003U, // VPERMI2Brmkz + 2182103939U, // VPERMI2Brr + 49300355U, // VPERMI2Brrk + 2196784003U, // VPERMI2Brrkz + 2182104801U, // VPERMI2D128rm + 2182104801U, // VPERMI2D128rmb + 49301217U, // VPERMI2D128rmbk + 2196784865U, // VPERMI2D128rmbkz + 49301217U, // VPERMI2D128rmk + 2196784865U, // VPERMI2D128rmkz + 2182104801U, // VPERMI2D128rr + 49301217U, // VPERMI2D128rrk + 2196784865U, // VPERMI2D128rrkz + 2182104801U, // VPERMI2D256rm + 2182104801U, // VPERMI2D256rmb + 49301217U, // VPERMI2D256rmbk + 2196784865U, // VPERMI2D256rmbkz + 49301217U, // VPERMI2D256rmk + 2196784865U, // VPERMI2D256rmkz + 2182104801U, // VPERMI2D256rr + 49301217U, // VPERMI2D256rrk + 2196784865U, // VPERMI2D256rrkz + 2182104801U, // VPERMI2Drm + 2182104801U, // VPERMI2Drmb + 49301217U, // VPERMI2Drmbk + 2196784865U, // VPERMI2Drmbkz + 49301217U, // VPERMI2Drmk + 2196784865U, // VPERMI2Drmkz + 2182104801U, // VPERMI2Drr + 49301217U, // VPERMI2Drrk + 2196784865U, // VPERMI2Drrkz + 2182105497U, // VPERMI2PD128rm + 2182105497U, // VPERMI2PD128rmb + 49301913U, // VPERMI2PD128rmbk + 2196785561U, // VPERMI2PD128rmbkz + 49301913U, // VPERMI2PD128rmk + 2196785561U, // VPERMI2PD128rmkz + 2182105497U, // VPERMI2PD128rr + 49301913U, // VPERMI2PD128rrk + 2196785561U, // VPERMI2PD128rrkz + 2182105497U, // VPERMI2PD256rm + 2182105497U, // VPERMI2PD256rmb + 49301913U, // VPERMI2PD256rmbk + 2196785561U, // VPERMI2PD256rmbkz + 49301913U, // VPERMI2PD256rmk + 2196785561U, // VPERMI2PD256rmkz + 2182105497U, // VPERMI2PD256rr + 49301913U, // VPERMI2PD256rrk + 2196785561U, // VPERMI2PD256rrkz + 2182105497U, // VPERMI2PDrm + 2182105497U, // VPERMI2PDrmb + 49301913U, // VPERMI2PDrmbk + 2196785561U, // VPERMI2PDrmbkz + 49301913U, // VPERMI2PDrmk + 2196785561U, // VPERMI2PDrmkz + 2182105497U, // VPERMI2PDrr + 49301913U, // VPERMI2PDrrk + 2196785561U, // VPERMI2PDrrkz + 2182110292U, // VPERMI2PS128rm + 2182110292U, // VPERMI2PS128rmb + 49306708U, // VPERMI2PS128rmbk + 2196790356U, // VPERMI2PS128rmbkz + 49306708U, // VPERMI2PS128rmk + 2196790356U, // VPERMI2PS128rmkz + 2182110292U, // VPERMI2PS128rr + 49306708U, // VPERMI2PS128rrk + 2196790356U, // VPERMI2PS128rrkz + 2182110292U, // VPERMI2PS256rm + 2182110292U, // VPERMI2PS256rmb + 49306708U, // VPERMI2PS256rmbk + 2196790356U, // VPERMI2PS256rmbkz + 49306708U, // VPERMI2PS256rmk + 2196790356U, // VPERMI2PS256rmkz + 2182110292U, // VPERMI2PS256rr + 49306708U, // VPERMI2PS256rrk + 2196790356U, // VPERMI2PS256rrkz + 2182110292U, // VPERMI2PSrm + 2182110292U, // VPERMI2PSrmb + 49306708U, // VPERMI2PSrmbk + 2196790356U, // VPERMI2PSrmbkz + 49306708U, // VPERMI2PSrmk + 2196790356U, // VPERMI2PSrmkz + 2182110292U, // VPERMI2PSrr + 49306708U, // VPERMI2PSrrk + 2196790356U, // VPERMI2PSrrkz + 2182108590U, // VPERMI2Q128rm + 2182108590U, // VPERMI2Q128rmb + 49305006U, // VPERMI2Q128rmbk + 2196788654U, // VPERMI2Q128rmbkz + 49305006U, // VPERMI2Q128rmk + 2196788654U, // VPERMI2Q128rmkz + 2182108590U, // VPERMI2Q128rr + 49305006U, // VPERMI2Q128rrk + 2196788654U, // VPERMI2Q128rrkz + 2182108590U, // VPERMI2Q256rm + 2182108590U, // VPERMI2Q256rmb + 49305006U, // VPERMI2Q256rmbk + 2196788654U, // VPERMI2Q256rmbkz + 49305006U, // VPERMI2Q256rmk + 2196788654U, // VPERMI2Q256rmkz + 2182108590U, // VPERMI2Q256rr + 49305006U, // VPERMI2Q256rrk + 2196788654U, // VPERMI2Q256rrkz + 2182108590U, // VPERMI2Qrm + 2182108590U, // VPERMI2Qrmb + 49305006U, // VPERMI2Qrmbk + 2196788654U, // VPERMI2Qrmbkz + 49305006U, // VPERMI2Qrmk + 2196788654U, // VPERMI2Qrmkz + 2182108590U, // VPERMI2Qrr + 49305006U, // VPERMI2Qrrk + 2196788654U, // VPERMI2Qrrkz + 2182112037U, // VPERMI2W128rm + 49308453U, // VPERMI2W128rmk + 2196792101U, // VPERMI2W128rmkz + 2182112037U, // VPERMI2W128rr + 49308453U, // VPERMI2W128rrk + 2196792101U, // VPERMI2W128rrkz + 2182112037U, // VPERMI2W256rm + 49308453U, // VPERMI2W256rmk + 2196792101U, // VPERMI2W256rmkz + 2182112037U, // VPERMI2W256rr + 49308453U, // VPERMI2W256rrk + 2196792101U, // VPERMI2W256rrkz + 2182112037U, // VPERMI2Wrm + 49308453U, // VPERMI2Wrmk + 2196792101U, // VPERMI2Wrmkz + 2182112037U, // VPERMI2Wrr + 49308453U, // VPERMI2Wrrk + 2196792101U, // VPERMI2Wrrkz + 2517649838U, // VPERMIL2PDYmr + 2517649838U, // VPERMIL2PDYrm + 2517649838U, // VPERMIL2PDYrr + 2517649838U, // VPERMIL2PDYrr_REV + 2517649838U, // VPERMIL2PDmr + 2517649838U, // VPERMIL2PDrm + 2517649838U, // VPERMIL2PDrr + 2517649838U, // VPERMIL2PDrr_REV + 2517654633U, // VPERMIL2PSYmr + 2517654633U, // VPERMIL2PSYrm + 2517654633U, // VPERMIL2PSYrr + 2517654633U, // VPERMIL2PSYrr_REV + 2517654633U, // VPERMIL2PSmr + 2517654633U, // VPERMIL2PSrm + 2517654633U, // VPERMIL2PSrr + 2517654633U, // VPERMIL2PSrr_REV + 3155184544U, // VPERMILPDYmi + 2517650336U, // VPERMILPDYri + 2517650336U, // VPERMILPDYrm + 2517650336U, // VPERMILPDYrr + 2752531360U, // VPERMILPDZ128mbi + 49302432U, // VPERMILPDZ128mbik + 2532330400U, // VPERMILPDZ128mbikz + 2819640224U, // VPERMILPDZ128mi + 49302432U, // VPERMILPDZ128mik + 2532330400U, // VPERMILPDZ128mikz + 2517650336U, // VPERMILPDZ128ri + 49302432U, // VPERMILPDZ128rik + 2532330400U, // VPERMILPDZ128rikz + 2517650336U, // VPERMILPDZ128rm + 2517650336U, // VPERMILPDZ128rmb + 49302432U, // VPERMILPDZ128rmbk + 2532330400U, // VPERMILPDZ128rmbkz + 49302432U, // VPERMILPDZ128rmk + 2532330400U, // VPERMILPDZ128rmkz + 2517650336U, // VPERMILPDZ128rr + 49302432U, // VPERMILPDZ128rrk + 2532330400U, // VPERMILPDZ128rrkz + 605047712U, // VPERMILPDZ256mbi + 49302432U, // VPERMILPDZ256mbik + 2532330400U, // VPERMILPDZ256mbikz + 3155184544U, // VPERMILPDZ256mi + 49302432U, // VPERMILPDZ256mik + 2532330400U, // VPERMILPDZ256mikz + 2517650336U, // VPERMILPDZ256ri + 49302432U, // VPERMILPDZ256rik + 2532330400U, // VPERMILPDZ256rikz + 2517650336U, // VPERMILPDZ256rm + 2517650336U, // VPERMILPDZ256rmb + 49302432U, // VPERMILPDZ256rmbk + 2532330400U, // VPERMILPDZ256rmbkz + 49302432U, // VPERMILPDZ256rmk + 2532330400U, // VPERMILPDZ256rmkz + 2517650336U, // VPERMILPDZ256rr + 49302432U, // VPERMILPDZ256rrk + 2532330400U, // VPERMILPDZ256rrkz + 2752531360U, // VPERMILPDZmbi + 49302432U, // VPERMILPDZmbik + 2532330400U, // VPERMILPDZmbikz + 3255847840U, // VPERMILPDZmi + 49302432U, // VPERMILPDZmik + 2532330400U, // VPERMILPDZmikz + 2517650336U, // VPERMILPDZri + 49302432U, // VPERMILPDZrik + 2532330400U, // VPERMILPDZrikz + 2517650336U, // VPERMILPDZrm + 2517650336U, // VPERMILPDZrmb + 49302432U, // VPERMILPDZrmbk + 2532330400U, // VPERMILPDZrmbkz + 49302432U, // VPERMILPDZrmk + 2532330400U, // VPERMILPDZrmkz + 2517650336U, // VPERMILPDZrr + 49302432U, // VPERMILPDZrrk + 2532330400U, // VPERMILPDZrrkz + 2819640224U, // VPERMILPDmi + 2517650336U, // VPERMILPDri + 2517650336U, // VPERMILPDrm + 2517650336U, // VPERMILPDrr + 3155189363U, // VPERMILPSYmi + 2517655155U, // VPERMILPSYri + 2517655155U, // VPERMILPSYrm + 2517655155U, // VPERMILPSYrr + 638606963U, // VPERMILPSZ128mbi + 49307251U, // VPERMILPSZ128mbik + 2532335219U, // VPERMILPSZ128mbikz + 2819645043U, // VPERMILPSZ128mi + 49307251U, // VPERMILPSZ128mik + 2532335219U, // VPERMILPSZ128mikz + 2517655155U, // VPERMILPSZ128ri + 49307251U, // VPERMILPSZ128rik + 2532335219U, // VPERMILPSZ128rikz + 2517655155U, // VPERMILPSZ128rm + 2517655155U, // VPERMILPSZ128rmb + 49307251U, // VPERMILPSZ128rmbk + 2532335219U, // VPERMILPSZ128rmbkz + 49307251U, // VPERMILPSZ128rmk + 2532335219U, // VPERMILPSZ128rmkz + 2517655155U, // VPERMILPSZ128rr + 49307251U, // VPERMILPSZ128rrk + 2532335219U, // VPERMILPSZ128rrkz + 2786090611U, // VPERMILPSZ256mbi + 49307251U, // VPERMILPSZ256mbik + 2532335219U, // VPERMILPSZ256mbikz + 3155189363U, // VPERMILPSZ256mi + 49307251U, // VPERMILPSZ256mik + 2532335219U, // VPERMILPSZ256mikz + 2517655155U, // VPERMILPSZ256ri + 49307251U, // VPERMILPSZ256rik + 2532335219U, // VPERMILPSZ256rikz + 2517655155U, // VPERMILPSZ256rm + 2517655155U, // VPERMILPSZ256rmb + 49307251U, // VPERMILPSZ256rmbk + 2532335219U, // VPERMILPSZ256rmbkz + 49307251U, // VPERMILPSZ256rmk + 2532335219U, // VPERMILPSZ256rmkz + 2517655155U, // VPERMILPSZ256rr + 49307251U, // VPERMILPSZ256rrk + 2532335219U, // VPERMILPSZ256rrkz + 638606963U, // VPERMILPSZmbi + 49307251U, // VPERMILPSZmbik + 2532335219U, // VPERMILPSZmbikz + 3255852659U, // VPERMILPSZmi + 49307251U, // VPERMILPSZmik + 2532335219U, // VPERMILPSZmikz + 2517655155U, // VPERMILPSZri + 49307251U, // VPERMILPSZrik + 2532335219U, // VPERMILPSZrikz + 2517655155U, // VPERMILPSZrm + 2517655155U, // VPERMILPSZrmb + 49307251U, // VPERMILPSZrmbk + 2532335219U, // VPERMILPSZrmbkz + 49307251U, // VPERMILPSZrmk + 2532335219U, // VPERMILPSZrmkz + 2517655155U, // VPERMILPSZrr + 49307251U, // VPERMILPSZrrk + 2532335219U, // VPERMILPSZrrkz + 2819645043U, // VPERMILPSmi + 2517655155U, // VPERMILPSri + 2517655155U, // VPERMILPSrm + 2517655155U, // VPERMILPSrr + 3155184615U, // VPERMPDYmi + 2517650407U, // VPERMPDYri + 605047783U, // VPERMPDZ256mbi + 49302503U, // VPERMPDZ256mbik + 2532330471U, // VPERMPDZ256mbikz + 3155184615U, // VPERMPDZ256mi + 49302503U, // VPERMPDZ256mik + 2532330471U, // VPERMPDZ256mikz + 2517650407U, // VPERMPDZ256ri + 49302503U, // VPERMPDZ256rik + 2532330471U, // VPERMPDZ256rikz + 2517650407U, // VPERMPDZ256rm + 2517650407U, // VPERMPDZ256rmb + 49302503U, // VPERMPDZ256rmbk + 2532330471U, // VPERMPDZ256rmbkz + 49302503U, // VPERMPDZ256rmk + 2532330471U, // VPERMPDZ256rmkz + 2517650407U, // VPERMPDZ256rr + 49302503U, // VPERMPDZ256rrk + 2532330471U, // VPERMPDZ256rrkz + 2752531431U, // VPERMPDZmbi + 49302503U, // VPERMPDZmbik + 2532330471U, // VPERMPDZmbikz + 3255847911U, // VPERMPDZmi + 49302503U, // VPERMPDZmik + 2532330471U, // VPERMPDZmikz + 2517650407U, // VPERMPDZri + 49302503U, // VPERMPDZrik + 2532330471U, // VPERMPDZrikz + 2517650407U, // VPERMPDZrm + 2517650407U, // VPERMPDZrmb + 49302503U, // VPERMPDZrmbk + 2532330471U, // VPERMPDZrmbkz + 49302503U, // VPERMPDZrmk + 2532330471U, // VPERMPDZrmkz + 2517650407U, // VPERMPDZrr + 49302503U, // VPERMPDZrrk + 2532330471U, // VPERMPDZrrkz + 2517655218U, // VPERMPSYrm + 2517655218U, // VPERMPSYrr + 2517655218U, // VPERMPSZ256rm + 2517655218U, // VPERMPSZ256rmb + 49307314U, // VPERMPSZ256rmbk + 2532335282U, // VPERMPSZ256rmbkz + 49307314U, // VPERMPSZ256rmk + 2532335282U, // VPERMPSZ256rmkz + 2517655218U, // VPERMPSZ256rr + 49307314U, // VPERMPSZ256rrk + 2532335282U, // VPERMPSZ256rrkz + 2517655218U, // VPERMPSZrm + 2517655218U, // VPERMPSZrmb + 49307314U, // VPERMPSZrmbk + 2532335282U, // VPERMPSZrmbkz + 49307314U, // VPERMPSZrmk + 2532335282U, // VPERMPSZrmkz + 2517655218U, // VPERMPSZrr + 49307314U, // VPERMPSZrrk + 2532335282U, // VPERMPSZrrkz + 3188742126U, // VPERMQYmi + 2517653486U, // VPERMQYri + 437278702U, // VPERMQZ256mbi + 49305582U, // VPERMQZ256mbik + 2532333550U, // VPERMQZ256mbikz + 3188742126U, // VPERMQZ256mi + 49305582U, // VPERMQZ256mik + 2532333550U, // VPERMQZ256mikz + 2517653486U, // VPERMQZ256ri + 49305582U, // VPERMQZ256rik + 2532333550U, // VPERMQZ256rikz + 2517653486U, // VPERMQZ256rm + 2517653486U, // VPERMQZ256rmb + 49305582U, // VPERMQZ256rmbk + 2532333550U, // VPERMQZ256rmbkz + 49305582U, // VPERMQZ256rmk + 2532333550U, // VPERMQZ256rmkz + 2517653486U, // VPERMQZ256rr + 49305582U, // VPERMQZ256rrk + 2532333550U, // VPERMQZ256rrkz + 2584762350U, // VPERMQZmbi + 49305582U, // VPERMQZmbik + 2532333550U, // VPERMQZmbikz + 2953861102U, // VPERMQZmi + 49305582U, // VPERMQZmik + 2532333550U, // VPERMQZmikz + 2517653486U, // VPERMQZri + 49305582U, // VPERMQZrik + 2532333550U, // VPERMQZrikz + 2517653486U, // VPERMQZrm + 2517653486U, // VPERMQZrmb + 49305582U, // VPERMQZrmbk + 2532333550U, // VPERMQZrmbkz + 49305582U, // VPERMQZrmk + 2532333550U, // VPERMQZrmkz + 2517653486U, // VPERMQZrr + 49305582U, // VPERMQZrrk + 2532333550U, // VPERMQZrrkz + 2182103959U, // VPERMT2B128rm + 49300375U, // VPERMT2B128rmk + 2196784023U, // VPERMT2B128rmkz + 2182103959U, // VPERMT2B128rr + 49300375U, // VPERMT2B128rrk + 2196784023U, // VPERMT2B128rrkz + 2182103959U, // VPERMT2B256rm + 49300375U, // VPERMT2B256rmk + 2196784023U, // VPERMT2B256rmkz + 2182103959U, // VPERMT2B256rr + 49300375U, // VPERMT2B256rrk + 2196784023U, // VPERMT2B256rrkz + 2182103959U, // VPERMT2Brm + 49300375U, // VPERMT2Brmk + 2196784023U, // VPERMT2Brmkz + 2182103959U, // VPERMT2Brr + 49300375U, // VPERMT2Brrk + 2196784023U, // VPERMT2Brrkz + 2182104821U, // VPERMT2D128rm + 2182104821U, // VPERMT2D128rmb + 49301237U, // VPERMT2D128rmbk + 2196784885U, // VPERMT2D128rmbkz + 49301237U, // VPERMT2D128rmk + 2196784885U, // VPERMT2D128rmkz + 2182104821U, // VPERMT2D128rr + 49301237U, // VPERMT2D128rrk + 2196784885U, // VPERMT2D128rrkz + 2182104821U, // VPERMT2D256rm + 2182104821U, // VPERMT2D256rmb + 49301237U, // VPERMT2D256rmbk + 2196784885U, // VPERMT2D256rmbkz + 49301237U, // VPERMT2D256rmk + 2196784885U, // VPERMT2D256rmkz + 2182104821U, // VPERMT2D256rr + 49301237U, // VPERMT2D256rrk + 2196784885U, // VPERMT2D256rrkz + 2182104821U, // VPERMT2Drm + 2182104821U, // VPERMT2Drmb + 49301237U, // VPERMT2Drmbk + 2196784885U, // VPERMT2Drmbkz + 49301237U, // VPERMT2Drmk + 2196784885U, // VPERMT2Drmkz + 2182104821U, // VPERMT2Drr + 49301237U, // VPERMT2Drrk + 2196784885U, // VPERMT2Drrkz + 2182105596U, // VPERMT2PD128rm + 2182105596U, // VPERMT2PD128rmb + 49302012U, // VPERMT2PD128rmbk + 2196785660U, // VPERMT2PD128rmbkz + 49302012U, // VPERMT2PD128rmk + 2196785660U, // VPERMT2PD128rmkz + 2182105596U, // VPERMT2PD128rr + 49302012U, // VPERMT2PD128rrk + 2196785660U, // VPERMT2PD128rrkz + 2182105596U, // VPERMT2PD256rm + 2182105596U, // VPERMT2PD256rmb + 49302012U, // VPERMT2PD256rmbk + 2196785660U, // VPERMT2PD256rmbkz + 49302012U, // VPERMT2PD256rmk + 2196785660U, // VPERMT2PD256rmkz + 2182105596U, // VPERMT2PD256rr + 49302012U, // VPERMT2PD256rrk + 2196785660U, // VPERMT2PD256rrkz + 2182105596U, // VPERMT2PDrm + 2182105596U, // VPERMT2PDrmb + 49302012U, // VPERMT2PDrmbk + 2196785660U, // VPERMT2PDrmbkz + 49302012U, // VPERMT2PDrmk + 2196785660U, // VPERMT2PDrmkz + 2182105596U, // VPERMT2PDrr + 49302012U, // VPERMT2PDrrk + 2196785660U, // VPERMT2PDrrkz + 2182110380U, // VPERMT2PS128rm + 2182110380U, // VPERMT2PS128rmb + 49306796U, // VPERMT2PS128rmbk + 2196790444U, // VPERMT2PS128rmbkz + 49306796U, // VPERMT2PS128rmk + 2196790444U, // VPERMT2PS128rmkz + 2182110380U, // VPERMT2PS128rr + 49306796U, // VPERMT2PS128rrk + 2196790444U, // VPERMT2PS128rrkz + 2182110380U, // VPERMT2PS256rm + 2182110380U, // VPERMT2PS256rmb + 49306796U, // VPERMT2PS256rmbk + 2196790444U, // VPERMT2PS256rmbkz + 49306796U, // VPERMT2PS256rmk + 2196790444U, // VPERMT2PS256rmkz + 2182110380U, // VPERMT2PS256rr + 49306796U, // VPERMT2PS256rrk + 2196790444U, // VPERMT2PS256rrkz + 2182110380U, // VPERMT2PSrm + 2182110380U, // VPERMT2PSrmb + 49306796U, // VPERMT2PSrmbk + 2196790444U, // VPERMT2PSrmbkz + 49306796U, // VPERMT2PSrmk + 2196790444U, // VPERMT2PSrmkz + 2182110380U, // VPERMT2PSrr + 49306796U, // VPERMT2PSrrk + 2196790444U, // VPERMT2PSrrkz + 2182108619U, // VPERMT2Q128rm + 2182108619U, // VPERMT2Q128rmb + 49305035U, // VPERMT2Q128rmbk + 2196788683U, // VPERMT2Q128rmbkz + 49305035U, // VPERMT2Q128rmk + 2196788683U, // VPERMT2Q128rmkz + 2182108619U, // VPERMT2Q128rr + 49305035U, // VPERMT2Q128rrk + 2196788683U, // VPERMT2Q128rrkz + 2182108619U, // VPERMT2Q256rm + 2182108619U, // VPERMT2Q256rmb + 49305035U, // VPERMT2Q256rmbk + 2196788683U, // VPERMT2Q256rmbkz + 49305035U, // VPERMT2Q256rmk + 2196788683U, // VPERMT2Q256rmkz + 2182108619U, // VPERMT2Q256rr + 49305035U, // VPERMT2Q256rrk + 2196788683U, // VPERMT2Q256rrkz + 2182108619U, // VPERMT2Qrm + 2182108619U, // VPERMT2Qrmb + 49305035U, // VPERMT2Qrmbk + 2196788683U, // VPERMT2Qrmbkz + 49305035U, // VPERMT2Qrmk + 2196788683U, // VPERMT2Qrmkz + 2182108619U, // VPERMT2Qrr + 49305035U, // VPERMT2Qrrk + 2196788683U, // VPERMT2Qrrkz + 2182112057U, // VPERMT2W128rm + 49308473U, // VPERMT2W128rmk + 2196792121U, // VPERMT2W128rmkz + 2182112057U, // VPERMT2W128rr + 49308473U, // VPERMT2W128rrk + 2196792121U, // VPERMT2W128rrkz + 2182112057U, // VPERMT2W256rm + 49308473U, // VPERMT2W256rmk + 2196792121U, // VPERMT2W256rmkz + 2182112057U, // VPERMT2W256rr + 49308473U, // VPERMT2W256rrk + 2196792121U, // VPERMT2W256rrkz + 2182112057U, // VPERMT2Wrm + 49308473U, // VPERMT2Wrmk + 2196792121U, // VPERMT2Wrmkz + 2182112057U, // VPERMT2Wrr + 49308473U, // VPERMT2Wrrk + 2196792121U, // VPERMT2Wrrkz + 2517656817U, // VPERMWZ128rm + 49308913U, // VPERMWZ128rmk + 2532336881U, // VPERMWZ128rmkz + 2517656817U, // VPERMWZ128rr + 49308913U, // VPERMWZ128rrk + 2532336881U, // VPERMWZ128rrkz + 2517656817U, // VPERMWZ256rm + 49308913U, // VPERMWZ256rmk + 2532336881U, // VPERMWZ256rmkz + 2517656817U, // VPERMWZ256rr + 49308913U, // VPERMWZ256rrk + 2532336881U, // VPERMWZ256rrkz + 2517656817U, // VPERMWZrm + 49308913U, // VPERMWZrmk + 2532336881U, // VPERMWZrmkz + 2517656817U, // VPERMWZrr + 49308913U, // VPERMWZrrk + 2532336881U, // VPERMWZrrkz + 336610302U, // VPEXPANDBZ128rm + 49300478U, // VPEXPANDBZ128rmk + 2532328446U, // VPEXPANDBZ128rmkz + 370164734U, // VPEXPANDBZ128rr + 49300478U, // VPEXPANDBZ128rrk + 2532328446U, // VPEXPANDBZ128rrkz + 1041253374U, // VPEXPANDBZ256rm + 49300478U, // VPEXPANDBZ256rmk + 2532328446U, // VPEXPANDBZ256rmkz + 370164734U, // VPEXPANDBZ256rr + 49300478U, // VPEXPANDBZ256rrk + 2532328446U, // VPEXPANDBZ256rrkz + 806372350U, // VPEXPANDBZrm + 49300478U, // VPEXPANDBZrmk + 2532328446U, // VPEXPANDBZrmkz + 370164734U, // VPEXPANDBZrr + 49300478U, // VPEXPANDBZrrk + 2532328446U, // VPEXPANDBZrrkz + 336611245U, // VPEXPANDDZ128rm + 49301421U, // VPEXPANDDZ128rmk + 2532329389U, // VPEXPANDDZ128rmkz + 370165677U, // VPEXPANDDZ128rr + 49301421U, // VPEXPANDDZ128rrk + 2532329389U, // VPEXPANDDZ128rrkz + 1041254317U, // VPEXPANDDZ256rm + 49301421U, // VPEXPANDDZ256rmk + 2532329389U, // VPEXPANDDZ256rmkz + 370165677U, // VPEXPANDDZ256rr + 49301421U, // VPEXPANDDZ256rrk + 2532329389U, // VPEXPANDDZ256rrkz + 806373293U, // VPEXPANDDZrm + 49301421U, // VPEXPANDDZrmk + 2532329389U, // VPEXPANDDZrmkz + 370165677U, // VPEXPANDDZrr + 49301421U, // VPEXPANDDZrrk + 2532329389U, // VPEXPANDDZrrkz + 336615111U, // VPEXPANDQZ128rm + 49305287U, // VPEXPANDQZ128rmk + 2532333255U, // VPEXPANDQZ128rmkz + 370169543U, // VPEXPANDQZ128rr + 49305287U, // VPEXPANDQZ128rrk + 2532333255U, // VPEXPANDQZ128rrkz + 1041258183U, // VPEXPANDQZ256rm + 49305287U, // VPEXPANDQZ256rmk + 2532333255U, // VPEXPANDQZ256rmkz + 370169543U, // VPEXPANDQZ256rr + 49305287U, // VPEXPANDQZ256rrk + 2532333255U, // VPEXPANDQZ256rrkz + 806377159U, // VPEXPANDQZrm + 49305287U, // VPEXPANDQZrmk + 2532333255U, // VPEXPANDQZrmkz + 370169543U, // VPEXPANDQZrr + 49305287U, // VPEXPANDQZrrk + 2532333255U, // VPEXPANDQZrrkz + 336618512U, // VPEXPANDWZ128rm + 49308688U, // VPEXPANDWZ128rmk + 2532336656U, // VPEXPANDWZ128rmkz + 370172944U, // VPEXPANDWZ128rr + 49308688U, // VPEXPANDWZ128rrk + 2532336656U, // VPEXPANDWZ128rrkz + 1041261584U, // VPEXPANDWZ256rm + 49308688U, // VPEXPANDWZ256rmk + 2532336656U, // VPEXPANDWZ256rmkz + 370172944U, // VPEXPANDWZ256rr + 49308688U, // VPEXPANDWZ256rrk + 2532336656U, // VPEXPANDWZ256rrkz + 806380560U, // VPEXPANDWZrm + 49308688U, // VPEXPANDWZrmk + 2532336656U, // VPEXPANDWZrmkz + 370172944U, // VPEXPANDWZrr + 49308688U, // VPEXPANDWZrrk + 2532336656U, // VPEXPANDWZrrkz + 2148631871U, // VPEXTRBZmr + 2517648703U, // VPEXTRBZrr + 2148631871U, // VPEXTRBmr + 2517648703U, // VPEXTRBrr + 2148601172U, // VPEXTRDZmr + 2517650772U, // VPEXTRDZrr + 2148601172U, // VPEXTRDmr + 2517650772U, // VPEXTRDrr + 2148620533U, // VPEXTRQZmr + 2517653749U, // VPEXTRQZrr + 2148620533U, // VPEXTRQmr + 2517653749U, // VPEXTRQrr + 2148574587U, // VPEXTRWZmr + 2517656955U, // VPEXTRWZrr + 2517656955U, // VPEXTRWZrr_REV + 2148574587U, // VPEXTRWmr + 2517656955U, // VPEXTRWrr + 2517656955U, // VPEXTRWrr_REV + 1141917634U, // VPGATHERDDYrm + 3337635778U, // VPGATHERDDZ128rm + 1190152130U, // VPGATHERDDZ256rm + 3337635778U, // VPGATHERDDZrm + 1209026498U, // VPGATHERDDrm + 1141921528U, // VPGATHERDQYrm + 3337639672U, // VPGATHERDQZ128rm + 1190156024U, // VPGATHERDQZ256rm + 3337639672U, // VPGATHERDQZrm + 1209030392U, // VPGATHERDQrm + 1209027800U, // VPGATHERQDYrm + 1190153432U, // VPGATHERQDZ128rm + 3337637080U, // VPGATHERQDZ256rm + 1190153432U, // VPGATHERQDZrm + 1242582232U, // VPGATHERQDrm + 1141921899U, // VPGATHERQQYrm + 3337640043U, // VPGATHERQQZ128rm + 1190156395U, // VPGATHERQQZ256rm + 3337640043U, // VPGATHERQQZrm + 1209030763U, // VPGATHERQQrm + 336611117U, // VPHADDBDrm + 370165549U, // VPHADDBDrr + 336614885U, // VPHADDBQrm + 370169317U, // VPHADDBQrr + 336618363U, // VPHADDBWrm + 370172795U, // VPHADDBWrr + 336615016U, // VPHADDDQrm + 370169448U, // VPHADDDQrr + 2517649277U, // VPHADDDYrm + 2517649277U, // VPHADDDYrr + 2517649277U, // VPHADDDrm + 2517649277U, // VPHADDDrr + 2517657003U, // VPHADDSWYrm + 2517657003U, // VPHADDSWYrr + 2517657003U, // VPHADDSWrm + 2517657003U, // VPHADDSWrr + 336611127U, // VPHADDUBDrm + 370165559U, // VPHADDUBDrr + 336614895U, // VPHADDUBQrm + 370169327U, // VPHADDUBQrr + 336618407U, // VPHADDUBWrm + 370172839U, // VPHADDUBWrr + 336615254U, // VPHADDUDQrm + 370169686U, // VPHADDUDQrr + 336613620U, // VPHADDUWDrm + 370168052U, // VPHADDUWDrr + 336616016U, // VPHADDUWQrm + 370170448U, // VPHADDUWQrr + 336613522U, // VPHADDWDrm + 370167954U, // VPHADDWDrr + 336616006U, // VPHADDWQrm + 370170438U, // VPHADDWQrr + 2517656552U, // VPHADDWYrm + 2517656552U, // VPHADDWYrr + 2517656552U, // VPHADDWrm + 2517656552U, // VPHADDWrr + 336619149U, // VPHMINPOSUWrm + 370173581U, // VPHMINPOSUWrr + 336618323U, // VPHSUBBWrm + 370172755U, // VPHSUBBWrr + 336614991U, // VPHSUBDQrm + 370169423U, // VPHSUBDQrr + 2517649218U, // VPHSUBDYrm + 2517649218U, // VPHSUBDYrr + 2517649218U, // VPHSUBDrm + 2517649218U, // VPHSUBDrr + 2517656984U, // VPHSUBSWYrm + 2517656984U, // VPHSUBSWYrr + 2517656984U, // VPHSUBSWrm + 2517656984U, // VPHSUBSWrr + 336613512U, // VPHSUBWDrm + 370167944U, // VPHSUBWDrr + 2517656498U, // VPHSUBWYrm + 2517656498U, // VPHSUBWYrr + 2517656498U, // VPHSUBWrm + 2517656498U, // VPHSUBWrr + 2517648684U, // VPINSRBZrm + 2517648684U, // VPINSRBZrr + 2517648684U, // VPINSRBrm + 2517648684U, // VPINSRBrr + 2517650753U, // VPINSRDZrm + 2517650753U, // VPINSRDZrr + 2517650753U, // VPINSRDrm + 2517650753U, // VPINSRDrr + 2517653730U, // VPINSRQZrm + 2517653730U, // VPINSRQZrr + 2517653730U, // VPINSRQrm + 2517653730U, // VPINSRQrr + 2517656936U, // VPINSRWZrm + 2517656936U, // VPINSRWZrr + 2517656936U, // VPINSRWrm + 2517656936U, // VPINSRWrr + 336613335U, // VPLZCNTDZ128rm + 2551205847U, // VPLZCNTDZ128rmb + 49303511U, // VPLZCNTDZ128rmbk + 2532331479U, // VPLZCNTDZ128rmbkz + 49303511U, // VPLZCNTDZ128rmk + 2532331479U, // VPLZCNTDZ128rmkz + 370167767U, // VPLZCNTDZ128rr + 49303511U, // VPLZCNTDZ128rrk + 2532331479U, // VPLZCNTDZ128rrkz + 1041256407U, // VPLZCNTDZ256rm + 403722199U, // VPLZCNTDZ256rmb + 49303511U, // VPLZCNTDZ256rmbk + 2532331479U, // VPLZCNTDZ256rmbkz + 49303511U, // VPLZCNTDZ256rmk + 2532331479U, // VPLZCNTDZ256rmkz + 370167767U, // VPLZCNTDZ256rr + 49303511U, // VPLZCNTDZ256rrk + 2532331479U, // VPLZCNTDZ256rrkz + 806375383U, // VPLZCNTDZrm + 2551205847U, // VPLZCNTDZrmb + 49303511U, // VPLZCNTDZrmbk + 2532331479U, // VPLZCNTDZrmbkz + 49303511U, // VPLZCNTDZrmk + 2532331479U, // VPLZCNTDZrmkz + 370167767U, // VPLZCNTDZrr + 49303511U, // VPLZCNTDZrrk + 2532331479U, // VPLZCNTDZrrkz + 336615786U, // VPLZCNTQZ128rm + 437279082U, // VPLZCNTQZ128rmb + 49305962U, // VPLZCNTQZ128rmbk + 2532333930U, // VPLZCNTQZ128rmbkz + 49305962U, // VPLZCNTQZ128rmk + 2532333930U, // VPLZCNTQZ128rmkz + 370170218U, // VPLZCNTQZ128rr + 49305962U, // VPLZCNTQZ128rrk + 2532333930U, // VPLZCNTQZ128rrkz + 1041258858U, // VPLZCNTQZ256rm + 2584762730U, // VPLZCNTQZ256rmb + 49305962U, // VPLZCNTQZ256rmbk + 2532333930U, // VPLZCNTQZ256rmbkz + 49305962U, // VPLZCNTQZ256rmk + 2532333930U, // VPLZCNTQZ256rmkz + 370170218U, // VPLZCNTQZ256rr + 49305962U, // VPLZCNTQZ256rrk + 2532333930U, // VPLZCNTQZ256rrkz + 806377834U, // VPLZCNTQZrm + 437279082U, // VPLZCNTQZrmb + 49305962U, // VPLZCNTQZrmbk + 2532333930U, // VPLZCNTQZrmbkz + 49305962U, // VPLZCNTQZrmk + 2532333930U, // VPLZCNTQZrmkz + 370170218U, // VPLZCNTQZrr + 49305962U, // VPLZCNTQZrrk + 2532333930U, // VPLZCNTQZrrkz + 2517649380U, // VPMACSDDrm + 2517649380U, // VPMACSDDrr + 2517652078U, // VPMACSDQHrm + 2517652078U, // VPMACSDQHrr + 2517652445U, // VPMACSDQLrm + 2517652445U, // VPMACSDQLrr + 2517649390U, // VPMACSSDDrm + 2517649390U, // VPMACSSDDrr + 2517652089U, // VPMACSSDQHrm + 2517652089U, // VPMACSSDQHrr + 2517652456U, // VPMACSSDQLrm + 2517652456U, // VPMACSSDQLrr + 2517651677U, // VPMACSSWDrm + 2517651677U, // VPMACSSWDrr + 2517657315U, // VPMACSSWWrm + 2517657315U, // VPMACSSWWrr + 2517651656U, // VPMACSWDrm + 2517651656U, // VPMACSWDrr + 2517657305U, // VPMACSWWrm + 2517657305U, // VPMACSWWrr + 2517651688U, // VPMADCSSWDrm + 2517651688U, // VPMADCSSWDrr + 2517651666U, // VPMADCSWDrm + 2517651666U, // VPMADCSWDrr + 2182109620U, // VPMADD52HUQZ128m + 2182109620U, // VPMADD52HUQZ128mb + 49306036U, // VPMADD52HUQZ128mbk + 2196789684U, // VPMADD52HUQZ128mbkz + 49306036U, // VPMADD52HUQZ128mk + 2196789684U, // VPMADD52HUQZ128mkz + 2182109620U, // VPMADD52HUQZ128r + 49306036U, // VPMADD52HUQZ128rk + 2196789684U, // VPMADD52HUQZ128rkz + 2182109620U, // VPMADD52HUQZ256m + 2182109620U, // VPMADD52HUQZ256mb + 49306036U, // VPMADD52HUQZ256mbk + 2196789684U, // VPMADD52HUQZ256mbkz + 49306036U, // VPMADD52HUQZ256mk + 2196789684U, // VPMADD52HUQZ256mkz + 2182109620U, // VPMADD52HUQZ256r + 49306036U, // VPMADD52HUQZ256rk + 2196789684U, // VPMADD52HUQZ256rkz + 2182109620U, // VPMADD52HUQZm + 2182109620U, // VPMADD52HUQZmb + 49306036U, // VPMADD52HUQZmbk + 2196789684U, // VPMADD52HUQZmbkz + 49306036U, // VPMADD52HUQZmk + 2196789684U, // VPMADD52HUQZmkz + 2182109620U, // VPMADD52HUQZr + 49306036U, // VPMADD52HUQZrk + 2196789684U, // VPMADD52HUQZrkz + 2182109633U, // VPMADD52LUQZ128m + 2182109633U, // VPMADD52LUQZ128mb + 49306049U, // VPMADD52LUQZ128mbk + 2196789697U, // VPMADD52LUQZ128mbkz + 49306049U, // VPMADD52LUQZ128mk + 2196789697U, // VPMADD52LUQZ128mkz + 2182109633U, // VPMADD52LUQZ128r + 49306049U, // VPMADD52LUQZ128rk + 2196789697U, // VPMADD52LUQZ128rkz + 2182109633U, // VPMADD52LUQZ256m + 2182109633U, // VPMADD52LUQZ256mb + 49306049U, // VPMADD52LUQZ256mbk + 2196789697U, // VPMADD52LUQZ256mbkz + 49306049U, // VPMADD52LUQZ256mk + 2196789697U, // VPMADD52LUQZ256mkz + 2182109633U, // VPMADD52LUQZ256r + 49306049U, // VPMADD52LUQZ256rk + 2196789697U, // VPMADD52LUQZ256rkz + 2182109633U, // VPMADD52LUQZm + 2182109633U, // VPMADD52LUQZmb + 49306049U, // VPMADD52LUQZmbk + 2196789697U, // VPMADD52LUQZmbkz + 49306049U, // VPMADD52LUQZmk + 2196789697U, // VPMADD52LUQZmkz + 2182109633U, // VPMADD52LUQZr + 49306049U, // VPMADD52LUQZrk + 2196789697U, // VPMADD52LUQZrkz + 2517656972U, // VPMADDUBSWYrm + 2517656972U, // VPMADDUBSWYrr + 2517656972U, // VPMADDUBSWZ128rm + 49309068U, // VPMADDUBSWZ128rmk + 2532337036U, // VPMADDUBSWZ128rmkz + 2517656972U, // VPMADDUBSWZ128rr + 49309068U, // VPMADDUBSWZ128rrk + 2532337036U, // VPMADDUBSWZ128rrkz + 2517656972U, // VPMADDUBSWZ256rm + 49309068U, // VPMADDUBSWZ256rmk + 2532337036U, // VPMADDUBSWZ256rmkz + 2517656972U, // VPMADDUBSWZ256rr + 49309068U, // VPMADDUBSWZ256rrk + 2532337036U, // VPMADDUBSWZ256rrkz + 2517656972U, // VPMADDUBSWZrm + 49309068U, // VPMADDUBSWZrmk + 2532337036U, // VPMADDUBSWZrmkz + 2517656972U, // VPMADDUBSWZrr + 49309068U, // VPMADDUBSWZrrk + 2532337036U, // VPMADDUBSWZrrkz + 2517656972U, // VPMADDUBSWrm + 2517656972U, // VPMADDUBSWrr + 2517651612U, // VPMADDWDYrm + 2517651612U, // VPMADDWDYrr + 2517651612U, // VPMADDWDZ128rm + 49303708U, // VPMADDWDZ128rmk + 2532331676U, // VPMADDWDZ128rmkz + 2517651612U, // VPMADDWDZ128rr + 49303708U, // VPMADDWDZ128rrk + 2532331676U, // VPMADDWDZ128rrkz + 2517651612U, // VPMADDWDZ256rm + 49303708U, // VPMADDWDZ256rmk + 2532331676U, // VPMADDWDZ256rmkz + 2517651612U, // VPMADDWDZ256rr + 49303708U, // VPMADDWDZ256rrk + 2532331676U, // VPMADDWDZ256rrkz + 2517651612U, // VPMADDWDZrm + 49303708U, // VPMADDWDZrmk + 2532331676U, // VPMADDWDZrmkz + 2517651612U, // VPMADDWDZrr + 49303708U, // VPMADDWDZrrk + 2532331676U, // VPMADDWDZrrkz + 2517651612U, // VPMADDWDrm + 2517651612U, // VPMADDWDrr + 2149159020U, // VPMASKMOVDYmr + 2517651564U, // VPMASKMOVDYrm + 2148683884U, // VPMASKMOVDmr + 2517651564U, // VPMASKMOVDrm + 2149161514U, // VPMASKMOVQYmr + 2517654058U, // VPMASKMOVQYrm + 2148686378U, // VPMASKMOVQmr + 2517654058U, // VPMASKMOVQrm + 2517648810U, // VPMAXSBYrm + 2517648810U, // VPMAXSBYrr + 2517648810U, // VPMAXSBZ128rm + 49300906U, // VPMAXSBZ128rmk + 2532328874U, // VPMAXSBZ128rmkz + 2517648810U, // VPMAXSBZ128rr + 49300906U, // VPMAXSBZ128rrk + 2532328874U, // VPMAXSBZ128rrkz + 2517648810U, // VPMAXSBZ256rm + 49300906U, // VPMAXSBZ256rmk + 2532328874U, // VPMAXSBZ256rmkz + 2517648810U, // VPMAXSBZ256rr + 49300906U, // VPMAXSBZ256rrk + 2532328874U, // VPMAXSBZ256rrkz + 2517648810U, // VPMAXSBZrm + 49300906U, // VPMAXSBZrmk + 2532328874U, // VPMAXSBZrmkz + 2517648810U, // VPMAXSBZrr + 49300906U, // VPMAXSBZrrk + 2532328874U, // VPMAXSBZrrkz + 2517648810U, // VPMAXSBrm + 2517648810U, // VPMAXSBrr + 2517651356U, // VPMAXSDYrm + 2517651356U, // VPMAXSDYrr + 2517651356U, // VPMAXSDZ128rm + 2517651356U, // VPMAXSDZ128rmb + 49303452U, // VPMAXSDZ128rmbk + 2532331420U, // VPMAXSDZ128rmbkz + 49303452U, // VPMAXSDZ128rmk + 2532331420U, // VPMAXSDZ128rmkz + 2517651356U, // VPMAXSDZ128rr + 49303452U, // VPMAXSDZ128rrk + 2532331420U, // VPMAXSDZ128rrkz + 2517651356U, // VPMAXSDZ256rm + 2517651356U, // VPMAXSDZ256rmb + 49303452U, // VPMAXSDZ256rmbk + 2532331420U, // VPMAXSDZ256rmbkz + 49303452U, // VPMAXSDZ256rmk + 2532331420U, // VPMAXSDZ256rmkz + 2517651356U, // VPMAXSDZ256rr + 49303452U, // VPMAXSDZ256rrk + 2532331420U, // VPMAXSDZ256rrkz + 2517651356U, // VPMAXSDZrm + 2517651356U, // VPMAXSDZrmb + 49303452U, // VPMAXSDZrmbk + 2532331420U, // VPMAXSDZrmbkz + 49303452U, // VPMAXSDZrmk + 2532331420U, // VPMAXSDZrmkz + 2517651356U, // VPMAXSDZrr + 49303452U, // VPMAXSDZrrk + 2532331420U, // VPMAXSDZrrkz + 2517651356U, // VPMAXSDrm + 2517651356U, // VPMAXSDrr + 2517653824U, // VPMAXSQZ128rm + 2517653824U, // VPMAXSQZ128rmb + 49305920U, // VPMAXSQZ128rmbk + 2532333888U, // VPMAXSQZ128rmbkz + 49305920U, // VPMAXSQZ128rmk + 2532333888U, // VPMAXSQZ128rmkz + 2517653824U, // VPMAXSQZ128rr + 49305920U, // VPMAXSQZ128rrk + 2532333888U, // VPMAXSQZ128rrkz + 2517653824U, // VPMAXSQZ256rm + 2517653824U, // VPMAXSQZ256rmb + 49305920U, // VPMAXSQZ256rmbk + 2532333888U, // VPMAXSQZ256rmbkz + 49305920U, // VPMAXSQZ256rmk + 2532333888U, // VPMAXSQZ256rmkz + 2517653824U, // VPMAXSQZ256rr + 49305920U, // VPMAXSQZ256rrk + 2532333888U, // VPMAXSQZ256rrkz + 2517653824U, // VPMAXSQZrm + 2517653824U, // VPMAXSQZrmb + 49305920U, // VPMAXSQZrmbk + 2532333888U, // VPMAXSQZrmbkz + 49305920U, // VPMAXSQZrmk + 2532333888U, // VPMAXSQZrmkz + 2517653824U, // VPMAXSQZrr + 49305920U, // VPMAXSQZrrk + 2532333888U, // VPMAXSQZrrkz + 2517657116U, // VPMAXSWYrm + 2517657116U, // VPMAXSWYrr + 2517657116U, // VPMAXSWZ128rm + 49309212U, // VPMAXSWZ128rmk + 2532337180U, // VPMAXSWZ128rmkz + 2517657116U, // VPMAXSWZ128rr + 49309212U, // VPMAXSWZ128rrk + 2532337180U, // VPMAXSWZ128rrkz + 2517657116U, // VPMAXSWZ256rm + 49309212U, // VPMAXSWZ256rmk + 2532337180U, // VPMAXSWZ256rmkz + 2517657116U, // VPMAXSWZ256rr + 49309212U, // VPMAXSWZ256rrk + 2532337180U, // VPMAXSWZ256rrkz + 2517657116U, // VPMAXSWZrm + 49309212U, // VPMAXSWZrmk + 2532337180U, // VPMAXSWZrmkz + 2517657116U, // VPMAXSWZrr + 49309212U, // VPMAXSWZrrk + 2532337180U, // VPMAXSWZrrkz + 2517657116U, // VPMAXSWrm + 2517657116U, // VPMAXSWrr + 2517648933U, // VPMAXUBYrm + 2517648933U, // VPMAXUBYrr + 2517648933U, // VPMAXUBZ128rm + 49301029U, // VPMAXUBZ128rmk + 2532328997U, // VPMAXUBZ128rmkz + 2517648933U, // VPMAXUBZ128rr + 49301029U, // VPMAXUBZ128rrk + 2532328997U, // VPMAXUBZ128rrkz + 2517648933U, // VPMAXUBZ256rm + 49301029U, // VPMAXUBZ256rmk + 2532328997U, // VPMAXUBZ256rmkz + 2517648933U, // VPMAXUBZ256rr + 49301029U, // VPMAXUBZ256rrk + 2532328997U, // VPMAXUBZ256rrkz + 2517648933U, // VPMAXUBZrm + 49301029U, // VPMAXUBZrmk + 2532328997U, // VPMAXUBZrmkz + 2517648933U, // VPMAXUBZrr + 49301029U, // VPMAXUBZrrk + 2532328997U, // VPMAXUBZrrkz + 2517648933U, // VPMAXUBrm + 2517648933U, // VPMAXUBrr + 2517651499U, // VPMAXUDYrm + 2517651499U, // VPMAXUDYrr + 2517651499U, // VPMAXUDZ128rm + 2517651499U, // VPMAXUDZ128rmb + 49303595U, // VPMAXUDZ128rmbk + 2532331563U, // VPMAXUDZ128rmbkz + 49303595U, // VPMAXUDZ128rmk + 2532331563U, // VPMAXUDZ128rmkz + 2517651499U, // VPMAXUDZ128rr + 49303595U, // VPMAXUDZ128rrk + 2532331563U, // VPMAXUDZ128rrkz + 2517651499U, // VPMAXUDZ256rm + 2517651499U, // VPMAXUDZ256rmb + 49303595U, // VPMAXUDZ256rmbk + 2532331563U, // VPMAXUDZ256rmbkz + 49303595U, // VPMAXUDZ256rmk + 2532331563U, // VPMAXUDZ256rmkz + 2517651499U, // VPMAXUDZ256rr + 49303595U, // VPMAXUDZ256rrk + 2532331563U, // VPMAXUDZ256rrkz + 2517651499U, // VPMAXUDZrm + 2517651499U, // VPMAXUDZrmb + 49303595U, // VPMAXUDZrmbk + 2532331563U, // VPMAXUDZrmbkz + 49303595U, // VPMAXUDZrmk + 2532331563U, // VPMAXUDZrmkz + 2517651499U, // VPMAXUDZrr + 49303595U, // VPMAXUDZrrk + 2532331563U, // VPMAXUDZrrkz + 2517651499U, // VPMAXUDrm + 2517651499U, // VPMAXUDrr + 2517653993U, // VPMAXUQZ128rm + 2517653993U, // VPMAXUQZ128rmb + 49306089U, // VPMAXUQZ128rmbk + 2532334057U, // VPMAXUQZ128rmbkz + 49306089U, // VPMAXUQZ128rmk + 2532334057U, // VPMAXUQZ128rmkz + 2517653993U, // VPMAXUQZ128rr + 49306089U, // VPMAXUQZ128rrk + 2532334057U, // VPMAXUQZ128rrkz + 2517653993U, // VPMAXUQZ256rm + 2517653993U, // VPMAXUQZ256rmb + 49306089U, // VPMAXUQZ256rmbk + 2532334057U, // VPMAXUQZ256rmbkz + 49306089U, // VPMAXUQZ256rmk + 2532334057U, // VPMAXUQZ256rmkz + 2517653993U, // VPMAXUQZ256rr + 49306089U, // VPMAXUQZ256rrk + 2532334057U, // VPMAXUQZ256rrkz + 2517653993U, // VPMAXUQZrm + 2517653993U, // VPMAXUQZrmb + 49306089U, // VPMAXUQZrmbk + 2532334057U, // VPMAXUQZrmbkz + 49306089U, // VPMAXUQZrmk + 2532334057U, // VPMAXUQZrmkz + 2517653993U, // VPMAXUQZrr + 49306089U, // VPMAXUQZrrk + 2532334057U, // VPMAXUQZrrkz + 2517657242U, // VPMAXUWYrm + 2517657242U, // VPMAXUWYrr + 2517657242U, // VPMAXUWZ128rm + 49309338U, // VPMAXUWZ128rmk + 2532337306U, // VPMAXUWZ128rmkz + 2517657242U, // VPMAXUWZ128rr + 49309338U, // VPMAXUWZ128rrk + 2532337306U, // VPMAXUWZ128rrkz + 2517657242U, // VPMAXUWZ256rm + 49309338U, // VPMAXUWZ256rmk + 2532337306U, // VPMAXUWZ256rmkz + 2517657242U, // VPMAXUWZ256rr + 49309338U, // VPMAXUWZ256rrk + 2532337306U, // VPMAXUWZ256rrkz + 2517657242U, // VPMAXUWZrm + 49309338U, // VPMAXUWZrmk + 2532337306U, // VPMAXUWZrmkz + 2517657242U, // VPMAXUWZrr + 49309338U, // VPMAXUWZrrk + 2532337306U, // VPMAXUWZrrkz + 2517657242U, // VPMAXUWrm + 2517657242U, // VPMAXUWrr + 2517648738U, // VPMINSBYrm + 2517648738U, // VPMINSBYrr + 2517648738U, // VPMINSBZ128rm + 49300834U, // VPMINSBZ128rmk + 2532328802U, // VPMINSBZ128rmkz + 2517648738U, // VPMINSBZ128rr + 49300834U, // VPMINSBZ128rrk + 2532328802U, // VPMINSBZ128rrkz + 2517648738U, // VPMINSBZ256rm + 49300834U, // VPMINSBZ256rmk + 2532328802U, // VPMINSBZ256rmkz + 2517648738U, // VPMINSBZ256rr + 49300834U, // VPMINSBZ256rrk + 2532328802U, // VPMINSBZ256rrkz + 2517648738U, // VPMINSBZrm + 49300834U, // VPMINSBZrmk + 2532328802U, // VPMINSBZrmkz + 2517648738U, // VPMINSBZrr + 49300834U, // VPMINSBZrrk + 2532328802U, // VPMINSBZrrkz + 2517648738U, // VPMINSBrm + 2517648738U, // VPMINSBrr + 2517651182U, // VPMINSDYrm + 2517651182U, // VPMINSDYrr + 2517651182U, // VPMINSDZ128rm + 2517651182U, // VPMINSDZ128rmb + 49303278U, // VPMINSDZ128rmbk + 2532331246U, // VPMINSDZ128rmbkz + 49303278U, // VPMINSDZ128rmk + 2532331246U, // VPMINSDZ128rmkz + 2517651182U, // VPMINSDZ128rr + 49303278U, // VPMINSDZ128rrk + 2532331246U, // VPMINSDZ128rrkz + 2517651182U, // VPMINSDZ256rm + 2517651182U, // VPMINSDZ256rmb + 49303278U, // VPMINSDZ256rmbk + 2532331246U, // VPMINSDZ256rmbkz + 49303278U, // VPMINSDZ256rmk + 2532331246U, // VPMINSDZ256rmkz + 2517651182U, // VPMINSDZ256rr + 49303278U, // VPMINSDZ256rrk + 2532331246U, // VPMINSDZ256rrkz + 2517651182U, // VPMINSDZrm + 2517651182U, // VPMINSDZrmb + 49303278U, // VPMINSDZrmbk + 2532331246U, // VPMINSDZrmbkz + 49303278U, // VPMINSDZrmk + 2532331246U, // VPMINSDZrmkz + 2517651182U, // VPMINSDZrr + 49303278U, // VPMINSDZrrk + 2532331246U, // VPMINSDZrrkz + 2517651182U, // VPMINSDrm + 2517651182U, // VPMINSDrr + 2517653766U, // VPMINSQZ128rm + 2517653766U, // VPMINSQZ128rmb + 49305862U, // VPMINSQZ128rmbk + 2532333830U, // VPMINSQZ128rmbkz + 49305862U, // VPMINSQZ128rmk + 2532333830U, // VPMINSQZ128rmkz + 2517653766U, // VPMINSQZ128rr + 49305862U, // VPMINSQZ128rrk + 2532333830U, // VPMINSQZ128rrkz + 2517653766U, // VPMINSQZ256rm + 2517653766U, // VPMINSQZ256rmb + 49305862U, // VPMINSQZ256rmbk + 2532333830U, // VPMINSQZ256rmbkz + 49305862U, // VPMINSQZ256rmk + 2532333830U, // VPMINSQZ256rmkz + 2517653766U, // VPMINSQZ256rr + 49305862U, // VPMINSQZ256rrk + 2532333830U, // VPMINSQZ256rrkz + 2517653766U, // VPMINSQZrm + 2517653766U, // VPMINSQZrmb + 49305862U, // VPMINSQZrmbk + 2532333830U, // VPMINSQZrmbkz + 49305862U, // VPMINSQZrmk + 2532333830U, // VPMINSQZrmkz + 2517653766U, // VPMINSQZrr + 49305862U, // VPMINSQZrrk + 2532333830U, // VPMINSQZrrkz + 2517657034U, // VPMINSWYrm + 2517657034U, // VPMINSWYrr + 2517657034U, // VPMINSWZ128rm + 49309130U, // VPMINSWZ128rmk + 2532337098U, // VPMINSWZ128rmkz + 2517657034U, // VPMINSWZ128rr + 49309130U, // VPMINSWZ128rrk + 2532337098U, // VPMINSWZ128rrkz + 2517657034U, // VPMINSWZ256rm + 49309130U, // VPMINSWZ256rmk + 2532337098U, // VPMINSWZ256rmkz + 2517657034U, // VPMINSWZ256rr + 49309130U, // VPMINSWZ256rrk + 2532337098U, // VPMINSWZ256rrkz + 2517657034U, // VPMINSWZrm + 49309130U, // VPMINSWZrmk + 2532337098U, // VPMINSWZrmkz + 2517657034U, // VPMINSWZrr + 49309130U, // VPMINSWZrrk + 2532337098U, // VPMINSWZrrkz + 2517657034U, // VPMINSWrm + 2517657034U, // VPMINSWrr + 2517648901U, // VPMINUBYrm + 2517648901U, // VPMINUBYrr + 2517648901U, // VPMINUBZ128rm + 49300997U, // VPMINUBZ128rmk + 2532328965U, // VPMINUBZ128rmkz + 2517648901U, // VPMINUBZ128rr + 49300997U, // VPMINUBZ128rrk + 2532328965U, // VPMINUBZ128rrkz + 2517648901U, // VPMINUBZ256rm + 49300997U, // VPMINUBZ256rmk + 2532328965U, // VPMINUBZ256rmkz + 2517648901U, // VPMINUBZ256rr + 49300997U, // VPMINUBZ256rrk + 2532328965U, // VPMINUBZ256rrkz + 2517648901U, // VPMINUBZrm + 49300997U, // VPMINUBZrmk + 2532328965U, // VPMINUBZrmkz + 2517648901U, // VPMINUBZrr + 49300997U, // VPMINUBZrrk + 2532328965U, // VPMINUBZrrkz + 2517648901U, // VPMINUBrm + 2517648901U, // VPMINUBrr + 2517651481U, // VPMINUDYrm + 2517651481U, // VPMINUDYrr + 2517651481U, // VPMINUDZ128rm + 2517651481U, // VPMINUDZ128rmb + 49303577U, // VPMINUDZ128rmbk + 2532331545U, // VPMINUDZ128rmbkz + 49303577U, // VPMINUDZ128rmk + 2532331545U, // VPMINUDZ128rmkz + 2517651481U, // VPMINUDZ128rr + 49303577U, // VPMINUDZ128rrk + 2532331545U, // VPMINUDZ128rrkz + 2517651481U, // VPMINUDZ256rm + 2517651481U, // VPMINUDZ256rmb + 49303577U, // VPMINUDZ256rmbk + 2532331545U, // VPMINUDZ256rmbkz + 49303577U, // VPMINUDZ256rmk + 2532331545U, // VPMINUDZ256rmkz + 2517651481U, // VPMINUDZ256rr + 49303577U, // VPMINUDZ256rrk + 2532331545U, // VPMINUDZ256rrkz + 2517651481U, // VPMINUDZrm + 2517651481U, // VPMINUDZrmb + 49303577U, // VPMINUDZrmbk + 2532331545U, // VPMINUDZrmbkz + 49303577U, // VPMINUDZrmk + 2532331545U, // VPMINUDZrmkz + 2517651481U, // VPMINUDZrr + 49303577U, // VPMINUDZrrk + 2532331545U, // VPMINUDZrrkz + 2517651481U, // VPMINUDrm + 2517651481U, // VPMINUDrr + 2517653975U, // VPMINUQZ128rm + 2517653975U, // VPMINUQZ128rmb + 49306071U, // VPMINUQZ128rmbk + 2532334039U, // VPMINUQZ128rmbkz + 49306071U, // VPMINUQZ128rmk + 2532334039U, // VPMINUQZ128rmkz + 2517653975U, // VPMINUQZ128rr + 49306071U, // VPMINUQZ128rrk + 2532334039U, // VPMINUQZ128rrkz + 2517653975U, // VPMINUQZ256rm + 2517653975U, // VPMINUQZ256rmb + 49306071U, // VPMINUQZ256rmbk + 2532334039U, // VPMINUQZ256rmbkz + 49306071U, // VPMINUQZ256rmk + 2532334039U, // VPMINUQZ256rmkz + 2517653975U, // VPMINUQZ256rr + 49306071U, // VPMINUQZ256rrk + 2532334039U, // VPMINUQZ256rrkz + 2517653975U, // VPMINUQZrm + 2517653975U, // VPMINUQZrmb + 49306071U, // VPMINUQZrmbk + 2532334039U, // VPMINUQZrmbkz + 49306071U, // VPMINUQZrmk + 2532334039U, // VPMINUQZrmkz + 2517653975U, // VPMINUQZrr + 49306071U, // VPMINUQZrrk + 2532334039U, // VPMINUQZrrkz + 2517657211U, // VPMINUWYrm + 2517657211U, // VPMINUWYrr + 2517657211U, // VPMINUWZ128rm + 49309307U, // VPMINUWZ128rmk + 2532337275U, // VPMINUWZ128rmkz + 2517657211U, // VPMINUWZ128rr + 49309307U, // VPMINUWZ128rrk + 2532337275U, // VPMINUWZ128rrkz + 2517657211U, // VPMINUWZ256rm + 49309307U, // VPMINUWZ256rmk + 2532337275U, // VPMINUWZ256rmkz + 2517657211U, // VPMINUWZ256rr + 49309307U, // VPMINUWZ256rrk + 2532337275U, // VPMINUWZ256rrkz + 2517657211U, // VPMINUWZrm + 49309307U, // VPMINUWZrmk + 2532337275U, // VPMINUWZrmkz + 2517657211U, // VPMINUWZrr + 49309307U, // VPMINUWZrrk + 2532337275U, // VPMINUWZrrkz + 2517657211U, // VPMINUWrm + 2517657211U, // VPMINUWrr + 370168852U, // VPMOVB2MZ128rr + 370168852U, // VPMOVB2MZ256rr + 370168852U, // VPMOVB2MZrr + 370168862U, // VPMOVD2MZ128rr + 370168862U, // VPMOVD2MZ256rr + 370168862U, // VPMOVD2MZrr + 1115166U, // VPMOVDBZ128mr + 15795230U, // VPMOVDBZ128mrk + 370164766U, // VPMOVDBZ128rr + 49300510U, // VPMOVDBZ128rrk + 2532328478U, // VPMOVDBZ128rrkz + 1131550U, // VPMOVDBZ256mr + 15811614U, // VPMOVDBZ256mrk + 370164766U, // VPMOVDBZ256rr + 49300510U, // VPMOVDBZ256rrk + 2532328478U, // VPMOVDBZ256rrkz + 1197086U, // VPMOVDBZmr + 15877150U, // VPMOVDBZmrk + 370164766U, // VPMOVDBZrr + 49300510U, // VPMOVDBZrrk + 2532328478U, // VPMOVDBZrrkz + 1139801U, // VPMOVDWZ128mr + 15819865U, // VPMOVDWZ128mrk + 370173017U, // VPMOVDWZ128rr + 49308761U, // VPMOVDWZ128rrk + 2532336729U, // VPMOVDWZ128rrkz + 1205337U, // VPMOVDWZ256mr + 15885401U, // VPMOVDWZ256mrk + 370173017U, // VPMOVDWZ256rr + 49308761U, // VPMOVDWZ256rrk + 2532336729U, // VPMOVDWZ256rrkz + 1680473U, // VPMOVDWZmr + 16360537U, // VPMOVDWZmrk + 370173017U, // VPMOVDWZrr + 49308761U, // VPMOVDWZrrk + 2532336729U, // VPMOVDWZrrkz + 370164621U, // VPMOVM2BZ128rr + 370164621U, // VPMOVM2BZ256rr + 370164621U, // VPMOVM2BZrr + 370165483U, // VPMOVM2DZ128rr + 370165483U, // VPMOVM2DZ256rr + 370165483U, // VPMOVM2DZrr + 370169272U, // VPMOVM2QZ128rr + 370169272U, // VPMOVM2QZ256rr + 370169272U, // VPMOVM2QZrr + 370172719U, // VPMOVM2WZ128rr + 370172719U, // VPMOVM2WZ256rr + 370172719U, // VPMOVM2WZrr + 370164796U, // VPMOVMSKBYrr + 370164796U, // VPMOVMSKBrr + 370168872U, // VPMOVQ2MZ128rr + 370168872U, // VPMOVQ2MZ256rr + 370168872U, // VPMOVQ2MZrr + 1082638U, // VPMOVQBZ128mr + 15762702U, // VPMOVQBZ128mrk + 370165006U, // VPMOVQBZ128rr + 49300750U, // VPMOVQBZ128rrk + 2532328718U, // VPMOVQBZ128rrkz + 1115406U, // VPMOVQBZ256mr + 15795470U, // VPMOVQBZ256mrk + 370165006U, // VPMOVQBZ256rr + 49300750U, // VPMOVQBZ256rrk + 2532328718U, // VPMOVQBZ256rrkz + 1131790U, // VPMOVQBZmr + 15811854U, // VPMOVQBZmrk + 370165006U, // VPMOVQBZrr + 49300750U, // VPMOVQBZrrk + 2532328718U, // VPMOVQBZrrkz + 1133830U, // VPMOVQDZ128mr + 15813894U, // VPMOVQDZ128mrk + 370167046U, // VPMOVQDZ128rr + 49302790U, // VPMOVQDZ128rrk + 2532330758U, // VPMOVQDZ128rrkz + 1199366U, // VPMOVQDZ256mr + 15879430U, // VPMOVQDZ256mrk + 370167046U, // VPMOVQDZ256rr + 49302790U, // VPMOVQDZ256rrk + 2532330758U, // VPMOVQDZ256rrkz + 1674502U, // VPMOVQDZmr + 16354566U, // VPMOVQDZmrk + 370167046U, // VPMOVQDZrr + 49302790U, // VPMOVQDZrrk + 2532330758U, // VPMOVQDZrrkz + 1123643U, // VPMOVQWZ128mr + 15803707U, // VPMOVQWZ128mrk + 370173243U, // VPMOVQWZ128rr + 49308987U, // VPMOVQWZ128rrk + 2532336955U, // VPMOVQWZ128rrkz + 1140027U, // VPMOVQWZ256mr + 15820091U, // VPMOVQWZ256mrk + 370173243U, // VPMOVQWZ256rr + 49308987U, // VPMOVQWZ256rrk + 2532336955U, // VPMOVQWZ256rrkz + 1205563U, // VPMOVQWZmr + 15885627U, // VPMOVQWZmrk + 370173243U, // VPMOVQWZrr + 49308987U, // VPMOVQWZrrk + 2532336955U, // VPMOVQWZrrkz + 1115156U, // VPMOVSDBZ128mr + 15795220U, // VPMOVSDBZ128mrk + 370164756U, // VPMOVSDBZ128rr + 49300500U, // VPMOVSDBZ128rrk + 2532328468U, // VPMOVSDBZ128rrkz + 1131540U, // VPMOVSDBZ256mr + 15811604U, // VPMOVSDBZ256mrk + 370164756U, // VPMOVSDBZ256rr + 49300500U, // VPMOVSDBZ256rrk + 2532328468U, // VPMOVSDBZ256rrkz + 1197076U, // VPMOVSDBZmr + 15877140U, // VPMOVSDBZmrk + 370164756U, // VPMOVSDBZrr + 49300500U, // VPMOVSDBZrrk + 2532328468U, // VPMOVSDBZrrkz + 1139791U, // VPMOVSDWZ128mr + 15819855U, // VPMOVSDWZ128mrk + 370173007U, // VPMOVSDWZ128rr + 49308751U, // VPMOVSDWZ128rrk + 2532336719U, // VPMOVSDWZ128rrkz + 1205327U, // VPMOVSDWZ256mr + 15885391U, // VPMOVSDWZ256mrk + 370173007U, // VPMOVSDWZ256rr + 49308751U, // VPMOVSDWZ256rrk + 2532336719U, // VPMOVSDWZ256rrkz + 1680463U, // VPMOVSDWZmr + 16360527U, // VPMOVSDWZmrk + 370173007U, // VPMOVSDWZrr + 49308751U, // VPMOVSDWZrrk + 2532336719U, // VPMOVSDWZrrkz + 1082593U, // VPMOVSQBZ128mr + 15762657U, // VPMOVSQBZ128mrk + 370164961U, // VPMOVSQBZ128rr + 49300705U, // VPMOVSQBZ128rrk + 2532328673U, // VPMOVSQBZ128rrkz + 1115361U, // VPMOVSQBZ256mr + 15795425U, // VPMOVSQBZ256mrk + 370164961U, // VPMOVSQBZ256rr + 49300705U, // VPMOVSQBZ256rrk + 2532328673U, // VPMOVSQBZ256rrkz + 1131745U, // VPMOVSQBZmr + 15811809U, // VPMOVSQBZmrk + 370164961U, // VPMOVSQBZrr + 49300705U, // VPMOVSQBZrrk + 2532328673U, // VPMOVSQBZrrkz + 1133820U, // VPMOVSQDZ128mr + 15813884U, // VPMOVSQDZ128mrk + 370167036U, // VPMOVSQDZ128rr + 49302780U, // VPMOVSQDZ128rrk + 2532330748U, // VPMOVSQDZ128rrkz + 1199356U, // VPMOVSQDZ256mr + 15879420U, // VPMOVSQDZ256mrk + 370167036U, // VPMOVSQDZ256rr + 49302780U, // VPMOVSQDZ256rrk + 2532330748U, // VPMOVSQDZ256rrkz + 1674492U, // VPMOVSQDZmr + 16354556U, // VPMOVSQDZmrk + 370167036U, // VPMOVSQDZrr + 49302780U, // VPMOVSQDZrrk + 2532330748U, // VPMOVSQDZrrkz + 1123633U, // VPMOVSQWZ128mr + 15803697U, // VPMOVSQWZ128mrk + 370173233U, // VPMOVSQWZ128rr + 49308977U, // VPMOVSQWZ128rrk + 2532336945U, // VPMOVSQWZ128rrkz + 1140017U, // VPMOVSQWZ256mr + 15820081U, // VPMOVSQWZ256mrk + 370173233U, // VPMOVSQWZ256rr + 49308977U, // VPMOVSQWZ256rrk + 2532336945U, // VPMOVSQWZ256rrkz + 1205553U, // VPMOVSQWZmr + 15885617U, // VPMOVSQWZmrk + 370173233U, // VPMOVSQWZrr + 49308977U, // VPMOVSQWZrrk + 2532336945U, // VPMOVSQWZrrkz + 1132142U, // VPMOVSWBZ128mr + 15812206U, // VPMOVSWBZ128mrk + 370165358U, // VPMOVSWBZ128rr + 49301102U, // VPMOVSWBZ128rrk + 2532329070U, // VPMOVSWBZ128rrkz + 1197678U, // VPMOVSWBZ256mr + 15877742U, // VPMOVSWBZ256mrk + 370165358U, // VPMOVSWBZ256rr + 49301102U, // VPMOVSWBZ256rrk + 2532329070U, // VPMOVSWBZ256rrkz + 1672814U, // VPMOVSWBZmr + 16352878U, // VPMOVSWBZmrk + 370165358U, // VPMOVSWBZrr + 49301102U, // VPMOVSWBZrrk + 2532329070U, // VPMOVSWBZrrkz + 437274451U, // VPMOVSXBDYrm + 370165587U, // VPMOVSXBDYrr + 403720019U, // VPMOVSXBDZ128rm + 49301331U, // VPMOVSXBDZ128rmk + 2532329299U, // VPMOVSXBDZ128rmkz + 370165587U, // VPMOVSXBDZ128rr + 49301331U, // VPMOVSXBDZ128rrk + 2532329299U, // VPMOVSXBDZ128rrkz + 437274451U, // VPMOVSXBDZ256rm + 49301331U, // VPMOVSXBDZ256rmk + 2532329299U, // VPMOVSXBDZ256rmkz + 370165587U, // VPMOVSXBDZ256rr + 49301331U, // VPMOVSXBDZ256rrk + 2532329299U, // VPMOVSXBDZ256rrkz + 336611155U, // VPMOVSXBDZrm + 49301331U, // VPMOVSXBDZrmk + 2532329299U, // VPMOVSXBDZrmkz + 370165587U, // VPMOVSXBDZrr + 49301331U, // VPMOVSXBDZrrk + 2532329299U, // VPMOVSXBDZrrkz + 403720019U, // VPMOVSXBDrm + 370165587U, // VPMOVSXBDrr + 403723778U, // VPMOVSXBQYrm + 370169346U, // VPMOVSXBQYrr + 504387074U, // VPMOVSXBQZ128rm + 49305090U, // VPMOVSXBQZ128rmk + 2532333058U, // VPMOVSXBQZ128rmkz + 370169346U, // VPMOVSXBQZ128rr + 49305090U, // VPMOVSXBQZ128rrk + 2532333058U, // VPMOVSXBQZ128rrkz + 403723778U, // VPMOVSXBQZ256rm + 49305090U, // VPMOVSXBQZ256rmk + 2532333058U, // VPMOVSXBQZ256rmkz + 370169346U, // VPMOVSXBQZ256rr + 49305090U, // VPMOVSXBQZ256rrk + 2532333058U, // VPMOVSXBQZ256rrkz + 437278210U, // VPMOVSXBQZrm + 49305090U, // VPMOVSXBQZrmk + 2532333058U, // VPMOVSXBQZrmkz + 370169346U, // VPMOVSXBQZrr + 49305090U, // VPMOVSXBQZrrk + 2532333058U, // VPMOVSXBQZrrkz + 504387074U, // VPMOVSXBQrm + 370169346U, // VPMOVSXBQrr + 336618435U, // VPMOVSXBWYrm + 370172867U, // VPMOVSXBWYrr + 437281731U, // VPMOVSXBWZ128rm + 49308611U, // VPMOVSXBWZ128rmk + 2532336579U, // VPMOVSXBWZ128rmkz + 370172867U, // VPMOVSXBWZ128rr + 49308611U, // VPMOVSXBWZ128rrk + 2532336579U, // VPMOVSXBWZ128rrkz + 336618435U, // VPMOVSXBWZ256rm + 49308611U, // VPMOVSXBWZ256rmk + 2532336579U, // VPMOVSXBWZ256rmkz + 370172867U, // VPMOVSXBWZ256rr + 49308611U, // VPMOVSXBWZ256rrk + 2532336579U, // VPMOVSXBWZ256rrkz + 1041261507U, // VPMOVSXBWZrm + 49308611U, // VPMOVSXBWZrmk + 2532336579U, // VPMOVSXBWZrmkz + 370172867U, // VPMOVSXBWZrr + 49308611U, // VPMOVSXBWZrrk + 2532336579U, // VPMOVSXBWZrrkz + 437281731U, // VPMOVSXBWrm + 370172867U, // VPMOVSXBWrr + 336615275U, // VPMOVSXDQYrm + 370169707U, // VPMOVSXDQYrr + 437278571U, // VPMOVSXDQZ128rm + 49305451U, // VPMOVSXDQZ128rmk + 2532333419U, // VPMOVSXDQZ128rmkz + 370169707U, // VPMOVSXDQZ128rr + 49305451U, // VPMOVSXDQZ128rrk + 2532333419U, // VPMOVSXDQZ128rrkz + 336615275U, // VPMOVSXDQZ256rm + 49305451U, // VPMOVSXDQZ256rmk + 2532333419U, // VPMOVSXDQZ256rmkz + 370169707U, // VPMOVSXDQZ256rr + 49305451U, // VPMOVSXDQZ256rrk + 2532333419U, // VPMOVSXDQZ256rrkz + 1041258347U, // VPMOVSXDQZrm + 49305451U, // VPMOVSXDQZrmk + 2532333419U, // VPMOVSXDQZrmkz + 370169707U, // VPMOVSXDQZrr + 49305451U, // VPMOVSXDQZrrk + 2532333419U, // VPMOVSXDQZrrkz + 437278571U, // VPMOVSXDQrm + 370169707U, // VPMOVSXDQrr + 336613631U, // VPMOVSXWDYrm + 370168063U, // VPMOVSXWDYrr + 437276927U, // VPMOVSXWDZ128rm + 49303807U, // VPMOVSXWDZ128rmk + 2532331775U, // VPMOVSXWDZ128rmkz + 370168063U, // VPMOVSXWDZ128rr + 49303807U, // VPMOVSXWDZ128rrk + 2532331775U, // VPMOVSXWDZ128rrkz + 336613631U, // VPMOVSXWDZ256rm + 49303807U, // VPMOVSXWDZ256rmk + 2532331775U, // VPMOVSXWDZ256rmkz + 370168063U, // VPMOVSXWDZ256rr + 49303807U, // VPMOVSXWDZ256rrk + 2532331775U, // VPMOVSXWDZ256rrkz + 1041256703U, // VPMOVSXWDZrm + 49303807U, // VPMOVSXWDZrmk + 2532331775U, // VPMOVSXWDZrmkz + 370168063U, // VPMOVSXWDZrr + 49303807U, // VPMOVSXWDZrrk + 2532331775U, // VPMOVSXWDZrrkz + 437276927U, // VPMOVSXWDrm + 370168063U, // VPMOVSXWDrr + 437279323U, // VPMOVSXWQYrm + 370170459U, // VPMOVSXWQYrr + 403724891U, // VPMOVSXWQZ128rm + 49306203U, // VPMOVSXWQZ128rmk + 2532334171U, // VPMOVSXWQZ128rmkz + 370170459U, // VPMOVSXWQZ128rr + 49306203U, // VPMOVSXWQZ128rrk + 2532334171U, // VPMOVSXWQZ128rrkz + 437279323U, // VPMOVSXWQZ256rm + 49306203U, // VPMOVSXWQZ256rmk + 2532334171U, // VPMOVSXWQZ256rmkz + 370170459U, // VPMOVSXWQZ256rr + 49306203U, // VPMOVSXWQZ256rrk + 2532334171U, // VPMOVSXWQZ256rrkz + 336616027U, // VPMOVSXWQZrm + 49306203U, // VPMOVSXWQZrmk + 2532334171U, // VPMOVSXWQZrmkz + 370170459U, // VPMOVSXWQZrr + 49306203U, // VPMOVSXWQZrrk + 2532334171U, // VPMOVSXWQZrrkz + 403724891U, // VPMOVSXWQrm + 370170459U, // VPMOVSXWQrr + 1115145U, // VPMOVUSDBZ128mr + 15795209U, // VPMOVUSDBZ128mrk + 370164745U, // VPMOVUSDBZ128rr + 49300489U, // VPMOVUSDBZ128rrk + 2532328457U, // VPMOVUSDBZ128rrkz + 1131529U, // VPMOVUSDBZ256mr + 15811593U, // VPMOVUSDBZ256mrk + 370164745U, // VPMOVUSDBZ256rr + 49300489U, // VPMOVUSDBZ256rrk + 2532328457U, // VPMOVUSDBZ256rrkz + 1197065U, // VPMOVUSDBZmr + 15877129U, // VPMOVUSDBZmrk + 370164745U, // VPMOVUSDBZrr + 49300489U, // VPMOVUSDBZrrk + 2532328457U, // VPMOVUSDBZrrkz + 1139780U, // VPMOVUSDWZ128mr + 15819844U, // VPMOVUSDWZ128mrk + 370172996U, // VPMOVUSDWZ128rr + 49308740U, // VPMOVUSDWZ128rrk + 2532336708U, // VPMOVUSDWZ128rrkz + 1205316U, // VPMOVUSDWZ256mr + 15885380U, // VPMOVUSDWZ256mrk + 370172996U, // VPMOVUSDWZ256rr + 49308740U, // VPMOVUSDWZ256rrk + 2532336708U, // VPMOVUSDWZ256rrkz + 1680452U, // VPMOVUSDWZmr + 16360516U, // VPMOVUSDWZmrk + 370172996U, // VPMOVUSDWZrr + 49308740U, // VPMOVUSDWZrrk + 2532336708U, // VPMOVUSDWZrrkz + 1082582U, // VPMOVUSQBZ128mr + 15762646U, // VPMOVUSQBZ128mrk + 370164950U, // VPMOVUSQBZ128rr + 49300694U, // VPMOVUSQBZ128rrk + 2532328662U, // VPMOVUSQBZ128rrkz + 1115350U, // VPMOVUSQBZ256mr + 15795414U, // VPMOVUSQBZ256mrk + 370164950U, // VPMOVUSQBZ256rr + 49300694U, // VPMOVUSQBZ256rrk + 2532328662U, // VPMOVUSQBZ256rrkz + 1131734U, // VPMOVUSQBZmr + 15811798U, // VPMOVUSQBZmrk + 370164950U, // VPMOVUSQBZrr + 49300694U, // VPMOVUSQBZrrk + 2532328662U, // VPMOVUSQBZrrkz + 1133809U, // VPMOVUSQDZ128mr + 15813873U, // VPMOVUSQDZ128mrk + 370167025U, // VPMOVUSQDZ128rr + 49302769U, // VPMOVUSQDZ128rrk + 2532330737U, // VPMOVUSQDZ128rrkz + 1199345U, // VPMOVUSQDZ256mr + 15879409U, // VPMOVUSQDZ256mrk + 370167025U, // VPMOVUSQDZ256rr + 49302769U, // VPMOVUSQDZ256rrk + 2532330737U, // VPMOVUSQDZ256rrkz + 1674481U, // VPMOVUSQDZmr + 16354545U, // VPMOVUSQDZmrk + 370167025U, // VPMOVUSQDZrr + 49302769U, // VPMOVUSQDZrrk + 2532330737U, // VPMOVUSQDZrrkz + 1123622U, // VPMOVUSQWZ128mr + 15803686U, // VPMOVUSQWZ128mrk + 370173222U, // VPMOVUSQWZ128rr + 49308966U, // VPMOVUSQWZ128rrk + 2532336934U, // VPMOVUSQWZ128rrkz + 1140006U, // VPMOVUSQWZ256mr + 15820070U, // VPMOVUSQWZ256mrk + 370173222U, // VPMOVUSQWZ256rr + 49308966U, // VPMOVUSQWZ256rrk + 2532336934U, // VPMOVUSQWZ256rrkz + 1205542U, // VPMOVUSQWZmr + 15885606U, // VPMOVUSQWZmrk + 370173222U, // VPMOVUSQWZrr + 49308966U, // VPMOVUSQWZrrk + 2532336934U, // VPMOVUSQWZrrkz + 1132131U, // VPMOVUSWBZ128mr + 15812195U, // VPMOVUSWBZ128mrk + 370165347U, // VPMOVUSWBZ128rr + 49301091U, // VPMOVUSWBZ128rrk + 2532329059U, // VPMOVUSWBZ128rrkz + 1197667U, // VPMOVUSWBZ256mr + 15877731U, // VPMOVUSWBZ256mrk + 370165347U, // VPMOVUSWBZ256rr + 49301091U, // VPMOVUSWBZ256rrk + 2532329059U, // VPMOVUSWBZ256rrkz + 1672803U, // VPMOVUSWBZmr + 16352867U, // VPMOVUSWBZmrk + 370165347U, // VPMOVUSWBZrr + 49301091U, // VPMOVUSWBZrrk + 2532329059U, // VPMOVUSWBZrrkz + 370168882U, // VPMOVW2MZ128rr + 370168882U, // VPMOVW2MZ256rr + 370168882U, // VPMOVW2MZrr + 1132152U, // VPMOVWBZ128mr + 15812216U, // VPMOVWBZ128mrk + 370165368U, // VPMOVWBZ128rr + 49301112U, // VPMOVWBZ128rrk + 2532329080U, // VPMOVWBZ128rrkz + 1197688U, // VPMOVWBZ256mr + 15877752U, // VPMOVWBZ256mrk + 370165368U, // VPMOVWBZ256rr + 49301112U, // VPMOVWBZ256rrk + 2532329080U, // VPMOVWBZ256rrkz + 1672824U, // VPMOVWBZmr + 16352888U, // VPMOVWBZmrk + 370165368U, // VPMOVWBZrr + 49301112U, // VPMOVWBZrrk + 2532329080U, // VPMOVWBZrrkz + 437274462U, // VPMOVZXBDYrm + 370165598U, // VPMOVZXBDYrr + 403720030U, // VPMOVZXBDZ128rm + 49301342U, // VPMOVZXBDZ128rmk + 2532329310U, // VPMOVZXBDZ128rmkz + 370165598U, // VPMOVZXBDZ128rr + 49301342U, // VPMOVZXBDZ128rrk + 2532329310U, // VPMOVZXBDZ128rrkz + 437274462U, // VPMOVZXBDZ256rm + 49301342U, // VPMOVZXBDZ256rmk + 2532329310U, // VPMOVZXBDZ256rmkz + 370165598U, // VPMOVZXBDZ256rr + 49301342U, // VPMOVZXBDZ256rrk + 2532329310U, // VPMOVZXBDZ256rrkz + 336611166U, // VPMOVZXBDZrm + 49301342U, // VPMOVZXBDZrmk + 2532329310U, // VPMOVZXBDZrmkz + 370165598U, // VPMOVZXBDZrr + 49301342U, // VPMOVZXBDZrrk + 2532329310U, // VPMOVZXBDZrrkz + 403720030U, // VPMOVZXBDrm + 370165598U, // VPMOVZXBDrr + 403723789U, // VPMOVZXBQYrm + 370169357U, // VPMOVZXBQYrr + 504387085U, // VPMOVZXBQZ128rm + 49305101U, // VPMOVZXBQZ128rmk + 2532333069U, // VPMOVZXBQZ128rmkz + 370169357U, // VPMOVZXBQZ128rr + 49305101U, // VPMOVZXBQZ128rrk + 2532333069U, // VPMOVZXBQZ128rrkz + 403723789U, // VPMOVZXBQZ256rm + 49305101U, // VPMOVZXBQZ256rmk + 2532333069U, // VPMOVZXBQZ256rmkz + 370169357U, // VPMOVZXBQZ256rr + 49305101U, // VPMOVZXBQZ256rrk + 2532333069U, // VPMOVZXBQZ256rrkz + 437278221U, // VPMOVZXBQZrm + 49305101U, // VPMOVZXBQZrmk + 2532333069U, // VPMOVZXBQZrmkz + 370169357U, // VPMOVZXBQZrr + 49305101U, // VPMOVZXBQZrrk + 2532333069U, // VPMOVZXBQZrrkz + 504387085U, // VPMOVZXBQrm + 370169357U, // VPMOVZXBQrr + 336618446U, // VPMOVZXBWYrm + 370172878U, // VPMOVZXBWYrr + 437281742U, // VPMOVZXBWZ128rm + 49308622U, // VPMOVZXBWZ128rmk + 2532336590U, // VPMOVZXBWZ128rmkz + 370172878U, // VPMOVZXBWZ128rr + 49308622U, // VPMOVZXBWZ128rrk + 2532336590U, // VPMOVZXBWZ128rrkz + 336618446U, // VPMOVZXBWZ256rm + 49308622U, // VPMOVZXBWZ256rmk + 2532336590U, // VPMOVZXBWZ256rmkz + 370172878U, // VPMOVZXBWZ256rr + 49308622U, // VPMOVZXBWZ256rrk + 2532336590U, // VPMOVZXBWZ256rrkz + 1041261518U, // VPMOVZXBWZrm + 49308622U, // VPMOVZXBWZrmk + 2532336590U, // VPMOVZXBWZrmkz + 370172878U, // VPMOVZXBWZrr + 49308622U, // VPMOVZXBWZrrk + 2532336590U, // VPMOVZXBWZrrkz + 437281742U, // VPMOVZXBWrm + 370172878U, // VPMOVZXBWrr + 336615286U, // VPMOVZXDQYrm + 370169718U, // VPMOVZXDQYrr + 437278582U, // VPMOVZXDQZ128rm + 49305462U, // VPMOVZXDQZ128rmk + 2532333430U, // VPMOVZXDQZ128rmkz + 370169718U, // VPMOVZXDQZ128rr + 49305462U, // VPMOVZXDQZ128rrk + 2532333430U, // VPMOVZXDQZ128rrkz + 336615286U, // VPMOVZXDQZ256rm + 49305462U, // VPMOVZXDQZ256rmk + 2532333430U, // VPMOVZXDQZ256rmkz + 370169718U, // VPMOVZXDQZ256rr + 49305462U, // VPMOVZXDQZ256rrk + 2532333430U, // VPMOVZXDQZ256rrkz + 1041258358U, // VPMOVZXDQZrm + 49305462U, // VPMOVZXDQZrmk + 2532333430U, // VPMOVZXDQZrmkz + 370169718U, // VPMOVZXDQZrr + 49305462U, // VPMOVZXDQZrrk + 2532333430U, // VPMOVZXDQZrrkz + 437278582U, // VPMOVZXDQrm + 370169718U, // VPMOVZXDQrr + 336613642U, // VPMOVZXWDYrm + 370168074U, // VPMOVZXWDYrr + 437276938U, // VPMOVZXWDZ128rm + 49303818U, // VPMOVZXWDZ128rmk + 2532331786U, // VPMOVZXWDZ128rmkz + 370168074U, // VPMOVZXWDZ128rr + 49303818U, // VPMOVZXWDZ128rrk + 2532331786U, // VPMOVZXWDZ128rrkz + 336613642U, // VPMOVZXWDZ256rm + 49303818U, // VPMOVZXWDZ256rmk + 2532331786U, // VPMOVZXWDZ256rmkz + 370168074U, // VPMOVZXWDZ256rr + 49303818U, // VPMOVZXWDZ256rrk + 2532331786U, // VPMOVZXWDZ256rrkz + 1041256714U, // VPMOVZXWDZrm + 49303818U, // VPMOVZXWDZrmk + 2532331786U, // VPMOVZXWDZrmkz + 370168074U, // VPMOVZXWDZrr + 49303818U, // VPMOVZXWDZrrk + 2532331786U, // VPMOVZXWDZrrkz + 437276938U, // VPMOVZXWDrm + 370168074U, // VPMOVZXWDrr + 437279334U, // VPMOVZXWQYrm + 370170470U, // VPMOVZXWQYrr + 403724902U, // VPMOVZXWQZ128rm + 49306214U, // VPMOVZXWQZ128rmk + 2532334182U, // VPMOVZXWQZ128rmkz + 370170470U, // VPMOVZXWQZ128rr + 49306214U, // VPMOVZXWQZ128rrk + 2532334182U, // VPMOVZXWQZ128rrkz + 437279334U, // VPMOVZXWQZ256rm + 49306214U, // VPMOVZXWQZ256rmk + 2532334182U, // VPMOVZXWQZ256rmkz + 370170470U, // VPMOVZXWQZ256rr + 49306214U, // VPMOVZXWQZ256rrk + 2532334182U, // VPMOVZXWQZ256rrkz + 336616038U, // VPMOVZXWQZrm + 49306214U, // VPMOVZXWQZrmk + 2532334182U, // VPMOVZXWQZrmkz + 370170470U, // VPMOVZXWQZrr + 49306214U, // VPMOVZXWQZrrk + 2532334182U, // VPMOVZXWQZrrkz + 403724902U, // VPMOVZXWQrm + 370170470U, // VPMOVZXWQrr + 2517653167U, // VPMULDQYrm + 2517653167U, // VPMULDQYrr + 2517653167U, // VPMULDQZ128rm + 2517653167U, // VPMULDQZ128rmb + 49305263U, // VPMULDQZ128rmbk + 2532333231U, // VPMULDQZ128rmbkz + 49305263U, // VPMULDQZ128rmk + 2532333231U, // VPMULDQZ128rmkz + 2517653167U, // VPMULDQZ128rr + 49305263U, // VPMULDQZ128rrk + 2532333231U, // VPMULDQZ128rrkz + 2517653167U, // VPMULDQZ256rm + 2517653167U, // VPMULDQZ256rmb + 49305263U, // VPMULDQZ256rmbk + 2532333231U, // VPMULDQZ256rmbkz + 49305263U, // VPMULDQZ256rmk + 2532333231U, // VPMULDQZ256rmkz + 2517653167U, // VPMULDQZ256rr + 49305263U, // VPMULDQZ256rrk + 2532333231U, // VPMULDQZ256rrkz + 2517653167U, // VPMULDQZrm + 2517653167U, // VPMULDQZrmb + 49305263U, // VPMULDQZrmbk + 2532333231U, // VPMULDQZrmbkz + 49305263U, // VPMULDQZrmk + 2532333231U, // VPMULDQZrmkz + 2517653167U, // VPMULDQZrr + 49305263U, // VPMULDQZrrk + 2532333231U, // VPMULDQZrrkz + 2517653167U, // VPMULDQrm + 2517653167U, // VPMULDQrr + 2517657057U, // VPMULHRSWYrm + 2517657057U, // VPMULHRSWYrr + 2517657057U, // VPMULHRSWZ128rm + 49309153U, // VPMULHRSWZ128rmk + 2532337121U, // VPMULHRSWZ128rmkz + 2517657057U, // VPMULHRSWZ128rr + 49309153U, // VPMULHRSWZ128rrk + 2532337121U, // VPMULHRSWZ128rrkz + 2517657057U, // VPMULHRSWZ256rm + 49309153U, // VPMULHRSWZ256rmk + 2532337121U, // VPMULHRSWZ256rmkz + 2517657057U, // VPMULHRSWZ256rr + 49309153U, // VPMULHRSWZ256rrk + 2532337121U, // VPMULHRSWZ256rrkz + 2517657057U, // VPMULHRSWZrm + 49309153U, // VPMULHRSWZrmk + 2532337121U, // VPMULHRSWZrmkz + 2517657057U, // VPMULHRSWZrr + 49309153U, // VPMULHRSWZrrk + 2532337121U, // VPMULHRSWZrrkz + 2517657057U, // VPMULHRSWrm + 2517657057U, // VPMULHRSWrr + 2517657192U, // VPMULHUWYrm + 2517657192U, // VPMULHUWYrr + 2517657192U, // VPMULHUWZ128rm + 49309288U, // VPMULHUWZ128rmk + 2532337256U, // VPMULHUWZ128rmkz + 2517657192U, // VPMULHUWZ128rr + 49309288U, // VPMULHUWZ128rrk + 2532337256U, // VPMULHUWZ128rrkz + 2517657192U, // VPMULHUWZ256rm + 49309288U, // VPMULHUWZ256rmk + 2532337256U, // VPMULHUWZ256rmkz + 2517657192U, // VPMULHUWZ256rr + 49309288U, // VPMULHUWZ256rrk + 2532337256U, // VPMULHUWZ256rrkz + 2517657192U, // VPMULHUWZrm + 49309288U, // VPMULHUWZrmk + 2532337256U, // VPMULHUWZrmkz + 2517657192U, // VPMULHUWZrr + 49309288U, // VPMULHUWZrrk + 2532337256U, // VPMULHUWZrrkz + 2517657192U, // VPMULHUWrm + 2517657192U, // VPMULHUWrr + 2517656718U, // VPMULHWYrm + 2517656718U, // VPMULHWYrr + 2517656718U, // VPMULHWZ128rm + 49308814U, // VPMULHWZ128rmk + 2532336782U, // VPMULHWZ128rmkz + 2517656718U, // VPMULHWZ128rr + 49308814U, // VPMULHWZ128rrk + 2532336782U, // VPMULHWZ128rrkz + 2517656718U, // VPMULHWZ256rm + 49308814U, // VPMULHWZ256rmk + 2532336782U, // VPMULHWZ256rmkz + 2517656718U, // VPMULHWZ256rr + 49308814U, // VPMULHWZ256rrk + 2532336782U, // VPMULHWZ256rrkz + 2517656718U, // VPMULHWZrm + 49308814U, // VPMULHWZrmk + 2532336782U, // VPMULHWZrmkz + 2517656718U, // VPMULHWZrr + 49308814U, // VPMULHWZrrk + 2532336782U, // VPMULHWZrrkz + 2517656718U, // VPMULHWrm + 2517656718U, // VPMULHWrr + 2517649496U, // VPMULLDYrm + 2517649496U, // VPMULLDYrr + 2517649496U, // VPMULLDZ128rm + 2517649496U, // VPMULLDZ128rmb + 49301592U, // VPMULLDZ128rmbk + 2532329560U, // VPMULLDZ128rmbkz + 49301592U, // VPMULLDZ128rmk + 2532329560U, // VPMULLDZ128rmkz + 2517649496U, // VPMULLDZ128rr + 49301592U, // VPMULLDZ128rrk + 2532329560U, // VPMULLDZ128rrkz + 2517649496U, // VPMULLDZ256rm + 2517649496U, // VPMULLDZ256rmb + 49301592U, // VPMULLDZ256rmbk + 2532329560U, // VPMULLDZ256rmbkz + 49301592U, // VPMULLDZ256rmk + 2532329560U, // VPMULLDZ256rmkz + 2517649496U, // VPMULLDZ256rr + 49301592U, // VPMULLDZ256rrk + 2532329560U, // VPMULLDZ256rrkz + 2517649496U, // VPMULLDZrm + 2517649496U, // VPMULLDZrmb + 49301592U, // VPMULLDZrmbk + 2532329560U, // VPMULLDZrmbkz + 49301592U, // VPMULLDZrmk + 2532329560U, // VPMULLDZrmkz + 2517649496U, // VPMULLDZrr + 49301592U, // VPMULLDZrrk + 2532329560U, // VPMULLDZrrkz + 2517649496U, // VPMULLDrm + 2517649496U, // VPMULLDrr + 2517653421U, // VPMULLQZ128rm + 2517653421U, // VPMULLQZ128rmb + 49305517U, // VPMULLQZ128rmbk + 2532333485U, // VPMULLQZ128rmbkz + 49305517U, // VPMULLQZ128rmk + 2532333485U, // VPMULLQZ128rmkz + 2517653421U, // VPMULLQZ128rr + 49305517U, // VPMULLQZ128rrk + 2532333485U, // VPMULLQZ128rrkz + 2517653421U, // VPMULLQZ256rm + 2517653421U, // VPMULLQZ256rmb + 49305517U, // VPMULLQZ256rmbk + 2532333485U, // VPMULLQZ256rmbkz + 49305517U, // VPMULLQZ256rmk + 2532333485U, // VPMULLQZ256rmkz + 2517653421U, // VPMULLQZ256rr + 49305517U, // VPMULLQZ256rrk + 2532333485U, // VPMULLQZ256rrkz + 2517653421U, // VPMULLQZrm + 2517653421U, // VPMULLQZrmb + 49305517U, // VPMULLQZrmbk + 2532333485U, // VPMULLQZrmbkz + 49305517U, // VPMULLQZrmk + 2532333485U, // VPMULLQZrmkz + 2517653421U, // VPMULLQZrr + 49305517U, // VPMULLQZrrk + 2532333485U, // VPMULLQZrrkz + 2517656760U, // VPMULLWYrm + 2517656760U, // VPMULLWYrr + 2517656760U, // VPMULLWZ128rm + 49308856U, // VPMULLWZ128rmk + 2532336824U, // VPMULLWZ128rmkz + 2517656760U, // VPMULLWZ128rr + 49308856U, // VPMULLWZ128rrk + 2532336824U, // VPMULLWZ128rrkz + 2517656760U, // VPMULLWZ256rm + 49308856U, // VPMULLWZ256rmk + 2532336824U, // VPMULLWZ256rmkz + 2517656760U, // VPMULLWZ256rr + 49308856U, // VPMULLWZ256rrk + 2532336824U, // VPMULLWZ256rrkz + 2517656760U, // VPMULLWZrm + 49308856U, // VPMULLWZrmk + 2532336824U, // VPMULLWZrmkz + 2517656760U, // VPMULLWZrr + 49308856U, // VPMULLWZrrk + 2532336824U, // VPMULLWZrrkz + 2517656760U, // VPMULLWrm + 2517656760U, // VPMULLWrr + 2517648619U, // VPMULTISHIFTQBZ128rm + 2517648619U, // VPMULTISHIFTQBZ128rmb + 49300715U, // VPMULTISHIFTQBZ128rmbk + 2532328683U, // VPMULTISHIFTQBZ128rmbkz + 49300715U, // VPMULTISHIFTQBZ128rmk + 2532328683U, // VPMULTISHIFTQBZ128rmkz + 2517648619U, // VPMULTISHIFTQBZ128rr + 49300715U, // VPMULTISHIFTQBZ128rrk + 2532328683U, // VPMULTISHIFTQBZ128rrkz + 2517648619U, // VPMULTISHIFTQBZ256rm + 2517648619U, // VPMULTISHIFTQBZ256rmb + 49300715U, // VPMULTISHIFTQBZ256rmbk + 2532328683U, // VPMULTISHIFTQBZ256rmbkz + 49300715U, // VPMULTISHIFTQBZ256rmk + 2532328683U, // VPMULTISHIFTQBZ256rmkz + 2517648619U, // VPMULTISHIFTQBZ256rr + 49300715U, // VPMULTISHIFTQBZ256rrk + 2532328683U, // VPMULTISHIFTQBZ256rrkz + 2517648619U, // VPMULTISHIFTQBZrm + 2517648619U, // VPMULTISHIFTQBZrmb + 49300715U, // VPMULTISHIFTQBZrmbk + 2532328683U, // VPMULTISHIFTQBZrmbkz + 49300715U, // VPMULTISHIFTQBZrmk + 2532328683U, // VPMULTISHIFTQBZrmkz + 2517648619U, // VPMULTISHIFTQBZrr + 49300715U, // VPMULTISHIFTQBZrrk + 2532328683U, // VPMULTISHIFTQBZrrkz + 2517653345U, // VPMULUDQYrm + 2517653345U, // VPMULUDQYrr + 2517653345U, // VPMULUDQZ128rm + 2517653345U, // VPMULUDQZ128rmb + 49305441U, // VPMULUDQZ128rmbk + 2532333409U, // VPMULUDQZ128rmbkz + 49305441U, // VPMULUDQZ128rmk + 2532333409U, // VPMULUDQZ128rmkz + 2517653345U, // VPMULUDQZ128rr + 49305441U, // VPMULUDQZ128rrk + 2532333409U, // VPMULUDQZ128rrkz + 2517653345U, // VPMULUDQZ256rm + 2517653345U, // VPMULUDQZ256rmb + 49305441U, // VPMULUDQZ256rmbk + 2532333409U, // VPMULUDQZ256rmbkz + 49305441U, // VPMULUDQZ256rmk + 2532333409U, // VPMULUDQZ256rmkz + 2517653345U, // VPMULUDQZ256rr + 49305441U, // VPMULUDQZ256rrk + 2532333409U, // VPMULUDQZ256rrkz + 2517653345U, // VPMULUDQZrm + 2517653345U, // VPMULUDQZrmb + 49305441U, // VPMULUDQZrmbk + 2532333409U, // VPMULUDQZrmbkz + 49305441U, // VPMULUDQZrmk + 2532333409U, // VPMULUDQZrmkz + 2517653345U, // VPMULUDQZrr + 49305441U, // VPMULUDQZrrk + 2532333409U, // VPMULUDQZrrkz + 2517653345U, // VPMULUDQrm + 2517653345U, // VPMULUDQrr + 336610755U, // VPOPCNTBZ128rm + 49300931U, // VPOPCNTBZ128rmk + 2532328899U, // VPOPCNTBZ128rmkz + 370165187U, // VPOPCNTBZ128rr + 49300931U, // VPOPCNTBZ128rrk + 2532328899U, // VPOPCNTBZ128rrkz + 1041253827U, // VPOPCNTBZ256rm + 49300931U, // VPOPCNTBZ256rmk + 2532328899U, // VPOPCNTBZ256rmkz + 370165187U, // VPOPCNTBZ256rr + 49300931U, // VPOPCNTBZ256rrk + 2532328899U, // VPOPCNTBZ256rrkz + 806372803U, // VPOPCNTBZrm + 49300931U, // VPOPCNTBZrmk + 2532328899U, // VPOPCNTBZrmkz + 370165187U, // VPOPCNTBZrr + 49300931U, // VPOPCNTBZrrk + 2532328899U, // VPOPCNTBZrrkz + 336613325U, // VPOPCNTDZ128rm + 2551205837U, // VPOPCNTDZ128rmb + 49303501U, // VPOPCNTDZ128rmbk + 2532331469U, // VPOPCNTDZ128rmbkz + 49303501U, // VPOPCNTDZ128rmk + 2532331469U, // VPOPCNTDZ128rmkz + 370167757U, // VPOPCNTDZ128rr + 49303501U, // VPOPCNTDZ128rrk + 2532331469U, // VPOPCNTDZ128rrkz + 1041256397U, // VPOPCNTDZ256rm + 403722189U, // VPOPCNTDZ256rmb + 49303501U, // VPOPCNTDZ256rmbk + 2532331469U, // VPOPCNTDZ256rmbkz + 49303501U, // VPOPCNTDZ256rmk + 2532331469U, // VPOPCNTDZ256rmkz + 370167757U, // VPOPCNTDZ256rr + 49303501U, // VPOPCNTDZ256rrk + 2532331469U, // VPOPCNTDZ256rrkz + 806375373U, // VPOPCNTDZrm + 2551205837U, // VPOPCNTDZrmb + 49303501U, // VPOPCNTDZrmbk + 2532331469U, // VPOPCNTDZrmbkz + 49303501U, // VPOPCNTDZrmk + 2532331469U, // VPOPCNTDZrmkz + 370167757U, // VPOPCNTDZrr + 49303501U, // VPOPCNTDZrrk + 2532331469U, // VPOPCNTDZrrkz + 336615776U, // VPOPCNTQZ128rm + 437279072U, // VPOPCNTQZ128rmb + 49305952U, // VPOPCNTQZ128rmbk + 2532333920U, // VPOPCNTQZ128rmbkz + 49305952U, // VPOPCNTQZ128rmk + 2532333920U, // VPOPCNTQZ128rmkz + 370170208U, // VPOPCNTQZ128rr + 49305952U, // VPOPCNTQZ128rrk + 2532333920U, // VPOPCNTQZ128rrkz + 1041258848U, // VPOPCNTQZ256rm + 2584762720U, // VPOPCNTQZ256rmb + 49305952U, // VPOPCNTQZ256rmbk + 2532333920U, // VPOPCNTQZ256rmbkz + 49305952U, // VPOPCNTQZ256rmk + 2532333920U, // VPOPCNTQZ256rmkz + 370170208U, // VPOPCNTQZ256rr + 49305952U, // VPOPCNTQZ256rrk + 2532333920U, // VPOPCNTQZ256rrkz + 806377824U, // VPOPCNTQZrm + 437279072U, // VPOPCNTQZrmb + 49305952U, // VPOPCNTQZrmbk + 2532333920U, // VPOPCNTQZrmbkz + 49305952U, // VPOPCNTQZrmk + 2532333920U, // VPOPCNTQZrmkz + 370170208U, // VPOPCNTQZrr + 49305952U, // VPOPCNTQZrrk + 2532333920U, // VPOPCNTQZrrkz + 336619055U, // VPOPCNTWZ128rm + 49309231U, // VPOPCNTWZ128rmk + 2532337199U, // VPOPCNTWZ128rmkz + 370173487U, // VPOPCNTWZ128rr + 49309231U, // VPOPCNTWZ128rrk + 2532337199U, // VPOPCNTWZ128rrkz + 1041262127U, // VPOPCNTWZ256rm + 49309231U, // VPOPCNTWZ256rmk + 2532337199U, // VPOPCNTWZ256rmkz + 370173487U, // VPOPCNTWZ256rr + 49309231U, // VPOPCNTWZ256rrk + 2532337199U, // VPOPCNTWZ256rrkz + 806381103U, // VPOPCNTWZrm + 49309231U, // VPOPCNTWZrmk + 2532337199U, // VPOPCNTWZrmkz + 370173487U, // VPOPCNTWZrr + 49309231U, // VPOPCNTWZrrk + 2532337199U, // VPOPCNTWZrrkz + 2517650723U, // VPORDZ128rm + 2517650723U, // VPORDZ128rmb + 49302819U, // VPORDZ128rmbk + 2532330787U, // VPORDZ128rmbkz + 49302819U, // VPORDZ128rmk + 2532330787U, // VPORDZ128rmkz + 2517650723U, // VPORDZ128rr + 49302819U, // VPORDZ128rrk + 2532330787U, // VPORDZ128rrkz + 2517650723U, // VPORDZ256rm + 2517650723U, // VPORDZ256rmb + 49302819U, // VPORDZ256rmbk + 2532330787U, // VPORDZ256rmbkz + 49302819U, // VPORDZ256rmk + 2532330787U, // VPORDZ256rmkz + 2517650723U, // VPORDZ256rr + 49302819U, // VPORDZ256rrk + 2532330787U, // VPORDZ256rrkz + 2517650723U, // VPORDZrm + 2517650723U, // VPORDZrmb + 49302819U, // VPORDZrmbk + 2532330787U, // VPORDZrmbkz + 49302819U, // VPORDZrmk + 2532330787U, // VPORDZrmkz + 2517650723U, // VPORDZrr + 49302819U, // VPORDZrrk + 2532330787U, // VPORDZrrkz + 2517653700U, // VPORQZ128rm + 2517653700U, // VPORQZ128rmb + 49305796U, // VPORQZ128rmbk + 2532333764U, // VPORQZ128rmbkz + 49305796U, // VPORQZ128rmk + 2532333764U, // VPORQZ128rmkz + 2517653700U, // VPORQZ128rr + 49305796U, // VPORQZ128rrk + 2532333764U, // VPORQZ128rrkz + 2517653700U, // VPORQZ256rm + 2517653700U, // VPORQZ256rmb + 49305796U, // VPORQZ256rmbk + 2532333764U, // VPORQZ256rmbkz + 49305796U, // VPORQZ256rmk + 2532333764U, // VPORQZ256rmkz + 2517653700U, // VPORQZ256rr + 49305796U, // VPORQZ256rrk + 2532333764U, // VPORQZ256rrkz + 2517653700U, // VPORQZrm + 2517653700U, // VPORQZrmb + 49305796U, // VPORQZrmbk + 2532333764U, // VPORQZrmbkz + 49305796U, // VPORQZrmk + 2532333764U, // VPORQZrmkz + 2517653700U, // VPORQZrr + 49305796U, // VPORQZrrk + 2532333764U, // VPORQZrrkz + 2517654191U, // VPORYrm + 2517654191U, // VPORYrr + 2517654191U, // VPORrm + 2517654191U, // VPORrr + 2517652565U, // VPPERMrmr + 2517652565U, // VPPERMrrm + 2517652565U, // VPPERMrrr + 2517652565U, // VPPERMrrr_REV + 403720289U, // VPROLDZ128mbi + 49301601U, // VPROLDZ128mbik + 2532329569U, // VPROLDZ128mbikz + 2484095073U, // VPROLDZ128mi + 49301601U, // VPROLDZ128mik + 2532329569U, // VPROLDZ128mikz + 2517649505U, // VPROLDZ128ri + 49301601U, // VPROLDZ128rik + 2532329569U, // VPROLDZ128rikz + 2551203937U, // VPROLDZ256mbi + 49301601U, // VPROLDZ256mbik + 2532329569U, // VPROLDZ256mbikz + 3188738145U, // VPROLDZ256mi + 49301601U, // VPROLDZ256mik + 2532329569U, // VPROLDZ256mikz + 2517649505U, // VPROLDZ256ri + 49301601U, // VPROLDZ256rik + 2532329569U, // VPROLDZ256rikz + 403720289U, // VPROLDZmbi + 49301601U, // VPROLDZmbik + 2532329569U, // VPROLDZmbikz + 2953857121U, // VPROLDZmi + 49301601U, // VPROLDZmik + 2532329569U, // VPROLDZmikz + 2517649505U, // VPROLDZri + 49301601U, // VPROLDZrik + 2532329569U, // VPROLDZrikz + 2584762294U, // VPROLQZ128mbi + 49305526U, // VPROLQZ128mbik + 2532333494U, // VPROLQZ128mbikz + 2484098998U, // VPROLQZ128mi + 49305526U, // VPROLQZ128mik + 2532333494U, // VPROLQZ128mikz + 2517653430U, // VPROLQZ128ri + 49305526U, // VPROLQZ128rik + 2532333494U, // VPROLQZ128rikz + 437278646U, // VPROLQZ256mbi + 49305526U, // VPROLQZ256mbik + 2532333494U, // VPROLQZ256mbikz + 3188742070U, // VPROLQZ256mi + 49305526U, // VPROLQZ256mik + 2532333494U, // VPROLQZ256mikz + 2517653430U, // VPROLQZ256ri + 49305526U, // VPROLQZ256rik + 2532333494U, // VPROLQZ256rikz + 2584762294U, // VPROLQZmbi + 49305526U, // VPROLQZmbik + 2532333494U, // VPROLQZmbikz + 2953861046U, // VPROLQZmi + 49305526U, // VPROLQZmik + 2532333494U, // VPROLQZmikz + 2517653430U, // VPROLQZri + 49305526U, // VPROLQZrik + 2532333494U, // VPROLQZrikz + 2517651546U, // VPROLVDZ128rm + 2517651546U, // VPROLVDZ128rmb + 49303642U, // VPROLVDZ128rmbk + 2532331610U, // VPROLVDZ128rmbkz + 49303642U, // VPROLVDZ128rmk + 2532331610U, // VPROLVDZ128rmkz + 2517651546U, // VPROLVDZ128rr + 49303642U, // VPROLVDZ128rrk + 2532331610U, // VPROLVDZ128rrkz + 2517651546U, // VPROLVDZ256rm + 2517651546U, // VPROLVDZ256rmb + 49303642U, // VPROLVDZ256rmbk + 2532331610U, // VPROLVDZ256rmbkz + 49303642U, // VPROLVDZ256rmk + 2532331610U, // VPROLVDZ256rmkz + 2517651546U, // VPROLVDZ256rr + 49303642U, // VPROLVDZ256rrk + 2532331610U, // VPROLVDZ256rrkz + 2517651546U, // VPROLVDZrm + 2517651546U, // VPROLVDZrmb + 49303642U, // VPROLVDZrmbk + 2532331610U, // VPROLVDZrmbkz + 49303642U, // VPROLVDZrmk + 2532331610U, // VPROLVDZrmkz + 2517651546U, // VPROLVDZrr + 49303642U, // VPROLVDZrrk + 2532331610U, // VPROLVDZrrkz + 2517654040U, // VPROLVQZ128rm + 2517654040U, // VPROLVQZ128rmb + 49306136U, // VPROLVQZ128rmbk + 2532334104U, // VPROLVQZ128rmbkz + 49306136U, // VPROLVQZ128rmk + 2532334104U, // VPROLVQZ128rmkz + 2517654040U, // VPROLVQZ128rr + 49306136U, // VPROLVQZ128rrk + 2532334104U, // VPROLVQZ128rrkz + 2517654040U, // VPROLVQZ256rm + 2517654040U, // VPROLVQZ256rmb + 49306136U, // VPROLVQZ256rmbk + 2532334104U, // VPROLVQZ256rmbkz + 49306136U, // VPROLVQZ256rmk + 2532334104U, // VPROLVQZ256rmkz + 2517654040U, // VPROLVQZ256rr + 49306136U, // VPROLVQZ256rrk + 2532334104U, // VPROLVQZ256rrkz + 2517654040U, // VPROLVQZrm + 2517654040U, // VPROLVQZrmb + 49306136U, // VPROLVQZrmbk + 2532334104U, // VPROLVQZrmbkz + 49306136U, // VPROLVQZrmk + 2532334104U, // VPROLVQZrmkz + 2517654040U, // VPROLVQZrr + 49306136U, // VPROLVQZrrk + 2532334104U, // VPROLVQZrrkz + 403721514U, // VPRORDZ128mbi + 49302826U, // VPRORDZ128mbik + 2532330794U, // VPRORDZ128mbikz + 2484096298U, // VPRORDZ128mi + 49302826U, // VPRORDZ128mik + 2532330794U, // VPRORDZ128mikz + 2517650730U, // VPRORDZ128ri + 49302826U, // VPRORDZ128rik + 2532330794U, // VPRORDZ128rikz + 2551205162U, // VPRORDZ256mbi + 49302826U, // VPRORDZ256mbik + 2532330794U, // VPRORDZ256mbikz + 3188739370U, // VPRORDZ256mi + 49302826U, // VPRORDZ256mik + 2532330794U, // VPRORDZ256mikz + 2517650730U, // VPRORDZ256ri + 49302826U, // VPRORDZ256rik + 2532330794U, // VPRORDZ256rikz + 403721514U, // VPRORDZmbi + 49302826U, // VPRORDZmbik + 2532330794U, // VPRORDZmbikz + 2953858346U, // VPRORDZmi + 49302826U, // VPRORDZmik + 2532330794U, // VPRORDZmikz + 2517650730U, // VPRORDZri + 49302826U, // VPRORDZrik + 2532330794U, // VPRORDZrikz + 2584762571U, // VPRORQZ128mbi + 49305803U, // VPRORQZ128mbik + 2532333771U, // VPRORQZ128mbikz + 2484099275U, // VPRORQZ128mi + 49305803U, // VPRORQZ128mik + 2532333771U, // VPRORQZ128mikz + 2517653707U, // VPRORQZ128ri + 49305803U, // VPRORQZ128rik + 2532333771U, // VPRORQZ128rikz + 437278923U, // VPRORQZ256mbi + 49305803U, // VPRORQZ256mbik + 2532333771U, // VPRORQZ256mbikz + 3188742347U, // VPRORQZ256mi + 49305803U, // VPRORQZ256mik + 2532333771U, // VPRORQZ256mikz + 2517653707U, // VPRORQZ256ri + 49305803U, // VPRORQZ256rik + 2532333771U, // VPRORQZ256rikz + 2584762571U, // VPRORQZmbi + 49305803U, // VPRORQZmbik + 2532333771U, // VPRORQZmbikz + 2953861323U, // VPRORQZmi + 49305803U, // VPRORQZmik + 2532333771U, // VPRORQZmikz + 2517653707U, // VPRORQZri + 49305803U, // VPRORQZrik + 2532333771U, // VPRORQZrikz + 2517651583U, // VPRORVDZ128rm + 2517651583U, // VPRORVDZ128rmb + 49303679U, // VPRORVDZ128rmbk + 2532331647U, // VPRORVDZ128rmbkz + 49303679U, // VPRORVDZ128rmk + 2532331647U, // VPRORVDZ128rmkz + 2517651583U, // VPRORVDZ128rr + 49303679U, // VPRORVDZ128rrk + 2532331647U, // VPRORVDZ128rrkz + 2517651583U, // VPRORVDZ256rm + 2517651583U, // VPRORVDZ256rmb + 49303679U, // VPRORVDZ256rmbk + 2532331647U, // VPRORVDZ256rmbkz + 49303679U, // VPRORVDZ256rmk + 2532331647U, // VPRORVDZ256rmkz + 2517651583U, // VPRORVDZ256rr + 49303679U, // VPRORVDZ256rrk + 2532331647U, // VPRORVDZ256rrkz + 2517651583U, // VPRORVDZrm + 2517651583U, // VPRORVDZrmb + 49303679U, // VPRORVDZrmbk + 2532331647U, // VPRORVDZrmbkz + 49303679U, // VPRORVDZrmk + 2532331647U, // VPRORVDZrmkz + 2517651583U, // VPRORVDZrr + 49303679U, // VPRORVDZrrk + 2532331647U, // VPRORVDZrrkz + 2517654077U, // VPRORVQZ128rm + 2517654077U, // VPRORVQZ128rmb + 49306173U, // VPRORVQZ128rmbk + 2532334141U, // VPRORVQZ128rmbkz + 49306173U, // VPRORVQZ128rmk + 2532334141U, // VPRORVQZ128rmkz + 2517654077U, // VPRORVQZ128rr + 49306173U, // VPRORVQZ128rrk + 2532334141U, // VPRORVQZ128rrkz + 2517654077U, // VPRORVQZ256rm + 2517654077U, // VPRORVQZ256rmb + 49306173U, // VPRORVQZ256rmbk + 2532334141U, // VPRORVQZ256rmbkz + 49306173U, // VPRORVQZ256rmk + 2532334141U, // VPRORVQZ256rmkz + 2517654077U, // VPRORVQZ256rr + 49306173U, // VPRORVQZ256rrk + 2532334141U, // VPRORVQZ256rrkz + 2517654077U, // VPRORVQZrm + 2517654077U, // VPRORVQZrmb + 49306173U, // VPRORVQZrmbk + 2532334141U, // VPRORVQZrmbkz + 49306173U, // VPRORVQZrmk + 2532334141U, // VPRORVQZrmkz + 2517654077U, // VPRORVQZrr + 49306173U, // VPRORVQZrrk + 2532334141U, // VPRORVQZrrkz + 2484094420U, // VPROTBmi + 2484094420U, // VPROTBmr + 2517648852U, // VPROTBri + 2517648852U, // VPROTBrm + 2517648852U, // VPROTBrr + 2517648852U, // VPROTBrr_REV + 2484097000U, // VPROTDmi + 2484097000U, // VPROTDmr + 2517651432U, // VPROTDri + 2517651432U, // VPROTDrm + 2517651432U, // VPROTDrr + 2517651432U, // VPROTDrr_REV + 2484099459U, // VPROTQmi + 2484099459U, // VPROTQmr + 2517653891U, // VPROTQri + 2517653891U, // VPROTQrm + 2517653891U, // VPROTQrr + 2517653891U, // VPROTQrr_REV + 2484102720U, // VPROTWmi + 2484102720U, // VPROTWmr + 2517657152U, // VPROTWri + 2517657152U, // VPROTWrm + 2517657152U, // VPROTWrr + 2517657152U, // VPROTWrr_REV + 2517656434U, // VPSADBWYrm + 2517656434U, // VPSADBWYrr + 2517656434U, // VPSADBWZ128rm + 2517656434U, // VPSADBWZ128rr + 2517656434U, // VPSADBWZ256rm + 2517656434U, // VPSADBWZ256rr + 2517656434U, // VPSADBWZrm + 2517656434U, // VPSADBWZrr + 2517656434U, // VPSADBWrm + 2517656434U, // VPSADBWrr + 690126U, // VPSCATTERDDZ128mr + 706510U, // VPSCATTERDDZ256mr + 722894U, // VPSCATTERDDZmr + 694020U, // VPSCATTERDQZ128mr + 710404U, // VPSCATTERDQZ256mr + 726788U, // VPSCATTERDQZmr + 740580U, // VPSCATTERQDZ128mr + 691428U, // VPSCATTERQDZ256mr + 707812U, // VPSCATTERQDZmr + 694391U, // VPSCATTERQQZ128mr + 710775U, // VPSCATTERQQZ256mr + 727159U, // VPSCATTERQQZmr + 2484093891U, // VPSHABmr + 2517648323U, // VPSHABrm + 2517648323U, // VPSHABrr + 2517648323U, // VPSHABrr_REV + 2484094749U, // VPSHADmr + 2517649181U, // VPSHADrm + 2517649181U, // VPSHADrr + 2517649181U, // VPSHADrr_REV + 2484098517U, // VPSHAQmr + 2517652949U, // VPSHAQrm + 2517652949U, // VPSHAQrr + 2517652949U, // VPSHAQrr_REV + 2484101955U, // VPSHAWmr + 2517656387U, // VPSHAWrm + 2517656387U, // VPSHAWrr + 2517656387U, // VPSHAWrr_REV + 2484094023U, // VPSHLBmr + 2517648455U, // VPSHLBrm + 2517648455U, // VPSHLBrr + 2517648455U, // VPSHLBrr_REV + 2517649301U, // VPSHLDDZ128rmbi + 49301397U, // VPSHLDDZ128rmbik + 2532329365U, // VPSHLDDZ128rmbikz + 2517649301U, // VPSHLDDZ128rmi + 49301397U, // VPSHLDDZ128rmik + 2532329365U, // VPSHLDDZ128rmikz + 2517649301U, // VPSHLDDZ128rri + 49301397U, // VPSHLDDZ128rrik + 2532329365U, // VPSHLDDZ128rrikz + 2517649301U, // VPSHLDDZ256rmbi + 49301397U, // VPSHLDDZ256rmbik + 2532329365U, // VPSHLDDZ256rmbikz + 2517649301U, // VPSHLDDZ256rmi + 49301397U, // VPSHLDDZ256rmik + 2532329365U, // VPSHLDDZ256rmikz + 2517649301U, // VPSHLDDZ256rri + 49301397U, // VPSHLDDZ256rrik + 2532329365U, // VPSHLDDZ256rrikz + 2517649301U, // VPSHLDDZrmbi + 49301397U, // VPSHLDDZrmbik + 2532329365U, // VPSHLDDZrmbikz + 2517649301U, // VPSHLDDZrmi + 49301397U, // VPSHLDDZrmik + 2532329365U, // VPSHLDDZrmikz + 2517649301U, // VPSHLDDZrri + 49301397U, // VPSHLDDZrrik + 2532329365U, // VPSHLDDZrrikz + 2517653128U, // VPSHLDQZ128rmbi + 49305224U, // VPSHLDQZ128rmbik + 2532333192U, // VPSHLDQZ128rmbikz + 2517653128U, // VPSHLDQZ128rmi + 49305224U, // VPSHLDQZ128rmik + 2532333192U, // VPSHLDQZ128rmikz + 2517653128U, // VPSHLDQZ128rri + 49305224U, // VPSHLDQZ128rrik + 2532333192U, // VPSHLDQZ128rrikz + 2517653128U, // VPSHLDQZ256rmbi + 49305224U, // VPSHLDQZ256rmbik + 2532333192U, // VPSHLDQZ256rmbikz + 2517653128U, // VPSHLDQZ256rmi + 49305224U, // VPSHLDQZ256rmik + 2532333192U, // VPSHLDQZ256rmikz + 2517653128U, // VPSHLDQZ256rri + 49305224U, // VPSHLDQZ256rrik + 2532333192U, // VPSHLDQZ256rrikz + 2517653128U, // VPSHLDQZrmbi + 49305224U, // VPSHLDQZrmbik + 2532333192U, // VPSHLDQZrmbikz + 2517653128U, // VPSHLDQZrmi + 49305224U, // VPSHLDQZrmik + 2532333192U, // VPSHLDQZrmikz + 2517653128U, // VPSHLDQZrri + 49305224U, // VPSHLDQZrrik + 2532333192U, // VPSHLDQZrrikz + 2182107197U, // VPSHLDVDZ128m + 2182107197U, // VPSHLDVDZ128mb + 49303613U, // VPSHLDVDZ128mbk + 2196787261U, // VPSHLDVDZ128mbkz + 49303613U, // VPSHLDVDZ128mk + 2196787261U, // VPSHLDVDZ128mkz + 2182107197U, // VPSHLDVDZ128r + 49303613U, // VPSHLDVDZ128rk + 2196787261U, // VPSHLDVDZ128rkz + 2182107197U, // VPSHLDVDZ256m + 2182107197U, // VPSHLDVDZ256mb + 49303613U, // VPSHLDVDZ256mbk + 2196787261U, // VPSHLDVDZ256mbkz + 49303613U, // VPSHLDVDZ256mk + 2196787261U, // VPSHLDVDZ256mkz + 2182107197U, // VPSHLDVDZ256r + 49303613U, // VPSHLDVDZ256rk + 2196787261U, // VPSHLDVDZ256rkz + 2182107197U, // VPSHLDVDZm + 2182107197U, // VPSHLDVDZmb + 49303613U, // VPSHLDVDZmbk + 2196787261U, // VPSHLDVDZmbkz + 49303613U, // VPSHLDVDZmk + 2196787261U, // VPSHLDVDZmkz + 2182107197U, // VPSHLDVDZr + 49303613U, // VPSHLDVDZrk + 2196787261U, // VPSHLDVDZrkz + 2182109691U, // VPSHLDVQZ128m + 2182109691U, // VPSHLDVQZ128mb + 49306107U, // VPSHLDVQZ128mbk + 2196789755U, // VPSHLDVQZ128mbkz + 49306107U, // VPSHLDVQZ128mk + 2196789755U, // VPSHLDVQZ128mkz + 2182109691U, // VPSHLDVQZ128r + 49306107U, // VPSHLDVQZ128rk + 2196789755U, // VPSHLDVQZ128rkz + 2182109691U, // VPSHLDVQZ256m + 2182109691U, // VPSHLDVQZ256mb + 49306107U, // VPSHLDVQZ256mbk + 2196789755U, // VPSHLDVQZ256mbkz + 49306107U, // VPSHLDVQZ256mk + 2196789755U, // VPSHLDVQZ256mkz + 2182109691U, // VPSHLDVQZ256r + 49306107U, // VPSHLDVQZ256rk + 2196789755U, // VPSHLDVQZ256rkz + 2182109691U, // VPSHLDVQZm + 2182109691U, // VPSHLDVQZmb + 49306107U, // VPSHLDVQZmbk + 2196789755U, // VPSHLDVQZmbkz + 49306107U, // VPSHLDVQZmk + 2196789755U, // VPSHLDVQZmkz + 2182109691U, // VPSHLDVQZr + 49306107U, // VPSHLDVQZrk + 2196789755U, // VPSHLDVQZrkz + 2182112940U, // VPSHLDVWZ128m + 49309356U, // VPSHLDVWZ128mk + 2196793004U, // VPSHLDVWZ128mkz + 2182112940U, // VPSHLDVWZ128r + 49309356U, // VPSHLDVWZ128rk + 2196793004U, // VPSHLDVWZ128rkz + 2182112940U, // VPSHLDVWZ256m + 49309356U, // VPSHLDVWZ256mk + 2196793004U, // VPSHLDVWZ256mkz + 2182112940U, // VPSHLDVWZ256r + 49309356U, // VPSHLDVWZ256rk + 2196793004U, // VPSHLDVWZ256rkz + 2182112940U, // VPSHLDVWZm + 49309356U, // VPSHLDVWZmk + 2196793004U, // VPSHLDVWZmkz + 2182112940U, // VPSHLDVWZr + 49309356U, // VPSHLDVWZrk + 2196793004U, // VPSHLDVWZrkz + 2517656576U, // VPSHLDWZ128rmi + 49308672U, // VPSHLDWZ128rmik + 2532336640U, // VPSHLDWZ128rmikz + 2517656576U, // VPSHLDWZ128rri + 49308672U, // VPSHLDWZ128rrik + 2532336640U, // VPSHLDWZ128rrikz + 2517656576U, // VPSHLDWZ256rmi + 49308672U, // VPSHLDWZ256rmik + 2532336640U, // VPSHLDWZ256rmikz + 2517656576U, // VPSHLDWZ256rri + 49308672U, // VPSHLDWZ256rrik + 2532336640U, // VPSHLDWZ256rrikz + 2517656576U, // VPSHLDWZrmi + 49308672U, // VPSHLDWZrmik + 2532336640U, // VPSHLDWZrmikz + 2517656576U, // VPSHLDWZrri + 49308672U, // VPSHLDWZrrik + 2532336640U, // VPSHLDWZrrikz + 2484095042U, // VPSHLDmr + 2517649474U, // VPSHLDrm + 2517649474U, // VPSHLDrr + 2517649474U, // VPSHLDrr_REV + 2484098973U, // VPSHLQmr + 2517653405U, // VPSHLQrm + 2517653405U, // VPSHLQrr + 2517653405U, // VPSHLQrr_REV + 2484102312U, // VPSHLWmr + 2517656744U, // VPSHLWrm + 2517656744U, // VPSHLWrr + 2517656744U, // VPSHLWrr_REV + 2517649371U, // VPSHRDDZ128rmbi + 49301467U, // VPSHRDDZ128rmbik + 2532329435U, // VPSHRDDZ128rmbikz + 2517649371U, // VPSHRDDZ128rmi + 49301467U, // VPSHRDDZ128rmik + 2532329435U, // VPSHRDDZ128rmikz + 2517649371U, // VPSHRDDZ128rri + 49301467U, // VPSHRDDZ128rrik + 2532329435U, // VPSHRDDZ128rrikz + 2517649371U, // VPSHRDDZ256rmbi + 49301467U, // VPSHRDDZ256rmbik + 2532329435U, // VPSHRDDZ256rmbikz + 2517649371U, // VPSHRDDZ256rmi + 49301467U, // VPSHRDDZ256rmik + 2532329435U, // VPSHRDDZ256rmikz + 2517649371U, // VPSHRDDZ256rri + 49301467U, // VPSHRDDZ256rrik + 2532329435U, // VPSHRDDZ256rrikz + 2517649371U, // VPSHRDDZrmbi + 49301467U, // VPSHRDDZrmbik + 2532329435U, // VPSHRDDZrmbikz + 2517649371U, // VPSHRDDZrmi + 49301467U, // VPSHRDDZrmik + 2532329435U, // VPSHRDDZrmikz + 2517649371U, // VPSHRDDZrri + 49301467U, // VPSHRDDZrrik + 2532329435U, // VPSHRDDZrrikz + 2517653265U, // VPSHRDQZ128rmbi + 49305361U, // VPSHRDQZ128rmbik + 2532333329U, // VPSHRDQZ128rmbikz + 2517653265U, // VPSHRDQZ128rmi + 49305361U, // VPSHRDQZ128rmik + 2532333329U, // VPSHRDQZ128rmikz + 2517653265U, // VPSHRDQZ128rri + 49305361U, // VPSHRDQZ128rrik + 2532333329U, // VPSHRDQZ128rrikz + 2517653265U, // VPSHRDQZ256rmbi + 49305361U, // VPSHRDQZ256rmbik + 2532333329U, // VPSHRDQZ256rmbikz + 2517653265U, // VPSHRDQZ256rmi + 49305361U, // VPSHRDQZ256rmik + 2532333329U, // VPSHRDQZ256rmikz + 2517653265U, // VPSHRDQZ256rri + 49305361U, // VPSHRDQZ256rrik + 2532333329U, // VPSHRDQZ256rrikz + 2517653265U, // VPSHRDQZrmbi + 49305361U, // VPSHRDQZrmbik + 2532333329U, // VPSHRDQZrmbikz + 2517653265U, // VPSHRDQZrmi + 49305361U, // VPSHRDQZrmik + 2532333329U, // VPSHRDQZrmikz + 2517653265U, // VPSHRDQZrri + 49305361U, // VPSHRDQZrrik + 2532333329U, // VPSHRDQZrrikz + 2182107207U, // VPSHRDVDZ128m + 2182107207U, // VPSHRDVDZ128mb + 49303623U, // VPSHRDVDZ128mbk + 2196787271U, // VPSHRDVDZ128mbkz + 49303623U, // VPSHRDVDZ128mk + 2196787271U, // VPSHRDVDZ128mkz + 2182107207U, // VPSHRDVDZ128r + 49303623U, // VPSHRDVDZ128rk + 2196787271U, // VPSHRDVDZ128rkz + 2182107207U, // VPSHRDVDZ256m + 2182107207U, // VPSHRDVDZ256mb + 49303623U, // VPSHRDVDZ256mbk + 2196787271U, // VPSHRDVDZ256mbkz + 49303623U, // VPSHRDVDZ256mk + 2196787271U, // VPSHRDVDZ256mkz + 2182107207U, // VPSHRDVDZ256r + 49303623U, // VPSHRDVDZ256rk + 2196787271U, // VPSHRDVDZ256rkz + 2182107207U, // VPSHRDVDZm + 2182107207U, // VPSHRDVDZmb + 49303623U, // VPSHRDVDZmbk + 2196787271U, // VPSHRDVDZmbkz + 49303623U, // VPSHRDVDZmk + 2196787271U, // VPSHRDVDZmkz + 2182107207U, // VPSHRDVDZr + 49303623U, // VPSHRDVDZrk + 2196787271U, // VPSHRDVDZrkz + 2182109701U, // VPSHRDVQZ128m + 2182109701U, // VPSHRDVQZ128mb + 49306117U, // VPSHRDVQZ128mbk + 2196789765U, // VPSHRDVQZ128mbkz + 49306117U, // VPSHRDVQZ128mk + 2196789765U, // VPSHRDVQZ128mkz + 2182109701U, // VPSHRDVQZ128r + 49306117U, // VPSHRDVQZ128rk + 2196789765U, // VPSHRDVQZ128rkz + 2182109701U, // VPSHRDVQZ256m + 2182109701U, // VPSHRDVQZ256mb + 49306117U, // VPSHRDVQZ256mbk + 2196789765U, // VPSHRDVQZ256mbkz + 49306117U, // VPSHRDVQZ256mk + 2196789765U, // VPSHRDVQZ256mkz + 2182109701U, // VPSHRDVQZ256r + 49306117U, // VPSHRDVQZ256rk + 2196789765U, // VPSHRDVQZ256rkz + 2182109701U, // VPSHRDVQZm + 2182109701U, // VPSHRDVQZmb + 49306117U, // VPSHRDVQZmbk + 2196789765U, // VPSHRDVQZmbkz + 49306117U, // VPSHRDVQZmk + 2196789765U, // VPSHRDVQZmkz + 2182109701U, // VPSHRDVQZr + 49306117U, // VPSHRDVQZrk + 2196789765U, // VPSHRDVQZrkz + 2182112950U, // VPSHRDVWZ128m + 49309366U, // VPSHRDVWZ128mk + 2196793014U, // VPSHRDVWZ128mkz + 2182112950U, // VPSHRDVWZ128r + 49309366U, // VPSHRDVWZ128rk + 2196793014U, // VPSHRDVWZ128rkz + 2182112950U, // VPSHRDVWZ256m + 49309366U, // VPSHRDVWZ256mk + 2196793014U, // VPSHRDVWZ256mkz + 2182112950U, // VPSHRDVWZ256r + 49309366U, // VPSHRDVWZ256rk + 2196793014U, // VPSHRDVWZ256rkz + 2182112950U, // VPSHRDVWZm + 49309366U, // VPSHRDVWZmk + 2196793014U, // VPSHRDVWZmkz + 2182112950U, // VPSHRDVWZr + 49309366U, // VPSHRDVWZrk + 2196793014U, // VPSHRDVWZrkz + 2517656613U, // VPSHRDWZ128rmi + 49308709U, // VPSHRDWZ128rmik + 2532336677U, // VPSHRDWZ128rmikz + 2517656613U, // VPSHRDWZ128rri + 49308709U, // VPSHRDWZ128rrik + 2532336677U, // VPSHRDWZ128rrikz + 2517656613U, // VPSHRDWZ256rmi + 49308709U, // VPSHRDWZ256rmik + 2532336677U, // VPSHRDWZ256rmikz + 2517656613U, // VPSHRDWZ256rri + 49308709U, // VPSHRDWZ256rrik + 2532336677U, // VPSHRDWZ256rrikz + 2517656613U, // VPSHRDWZrmi + 49308709U, // VPSHRDWZrmik + 2532336677U, // VPSHRDWZrmikz + 2517656613U, // VPSHRDWZrri + 49308709U, // VPSHRDWZrrik + 2532336677U, // VPSHRDWZrrikz + 2517648515U, // VPSHUFBITQMBZ128rm + 384844931U, // VPSHUFBITQMBZ128rmk + 2517648515U, // VPSHUFBITQMBZ128rr + 384844931U, // VPSHUFBITQMBZ128rrk + 2517648515U, // VPSHUFBITQMBZ256rm + 384844931U, // VPSHUFBITQMBZ256rmk + 2517648515U, // VPSHUFBITQMBZ256rr + 384844931U, // VPSHUFBITQMBZ256rrk + 2517648515U, // VPSHUFBITQMBZrm + 384844931U, // VPSHUFBITQMBZrmk + 2517648515U, // VPSHUFBITQMBZrr + 384844931U, // VPSHUFBITQMBZrrk + 2517648423U, // VPSHUFBYrm + 2517648423U, // VPSHUFBYrr + 2517648423U, // VPSHUFBZ128rm + 49300519U, // VPSHUFBZ128rmk + 2532328487U, // VPSHUFBZ128rmkz + 2517648423U, // VPSHUFBZ128rr + 49300519U, // VPSHUFBZ128rrk + 2532328487U, // VPSHUFBZ128rrkz + 2517648423U, // VPSHUFBZ256rm + 49300519U, // VPSHUFBZ256rmk + 2532328487U, // VPSHUFBZ256rmkz + 2517648423U, // VPSHUFBZ256rr + 49300519U, // VPSHUFBZ256rrk + 2532328487U, // VPSHUFBZ256rrkz + 2517648423U, // VPSHUFBZrm + 49300519U, // VPSHUFBZrmk + 2532328487U, // VPSHUFBZrmkz + 2517648423U, // VPSHUFBZrr + 49300519U, // VPSHUFBZrrk + 2532328487U, // VPSHUFBZrrkz + 2517648423U, // VPSHUFBrm + 2517648423U, // VPSHUFBrr + 3188738056U, // VPSHUFDYmi + 2517649416U, // VPSHUFDYri + 403720200U, // VPSHUFDZ128mbi + 49301512U, // VPSHUFDZ128mbik + 2532329480U, // VPSHUFDZ128mbikz + 2484094984U, // VPSHUFDZ128mi + 49301512U, // VPSHUFDZ128mik + 2532329480U, // VPSHUFDZ128mikz + 2517649416U, // VPSHUFDZ128ri + 49301512U, // VPSHUFDZ128rik + 2532329480U, // VPSHUFDZ128rikz + 2551203848U, // VPSHUFDZ256mbi + 49301512U, // VPSHUFDZ256mbik + 2532329480U, // VPSHUFDZ256mbikz + 3188738056U, // VPSHUFDZ256mi + 49301512U, // VPSHUFDZ256mik + 2532329480U, // VPSHUFDZ256mikz + 2517649416U, // VPSHUFDZ256ri + 49301512U, // VPSHUFDZ256rik + 2532329480U, // VPSHUFDZ256rikz + 403720200U, // VPSHUFDZmbi + 49301512U, // VPSHUFDZmbik + 2532329480U, // VPSHUFDZmbikz + 2953857032U, // VPSHUFDZmi + 49301512U, // VPSHUFDZmik + 2532329480U, // VPSHUFDZmikz + 2517649416U, // VPSHUFDZri + 49301512U, // VPSHUFDZrik + 2532329480U, // VPSHUFDZrikz + 2484094984U, // VPSHUFDmi + 2517649416U, // VPSHUFDri + 3188745348U, // VPSHUFHWYmi + 2517656708U, // VPSHUFHWYri + 2484102276U, // VPSHUFHWZ128mi + 49308804U, // VPSHUFHWZ128mik + 2532336772U, // VPSHUFHWZ128mikz + 2517656708U, // VPSHUFHWZ128ri + 49308804U, // VPSHUFHWZ128rik + 2532336772U, // VPSHUFHWZ128rikz + 3188745348U, // VPSHUFHWZ256mi + 49308804U, // VPSHUFHWZ256mik + 2532336772U, // VPSHUFHWZ256mikz + 2517656708U, // VPSHUFHWZ256ri + 49308804U, // VPSHUFHWZ256rik + 2532336772U, // VPSHUFHWZ256rikz + 2953864324U, // VPSHUFHWZmi + 49308804U, // VPSHUFHWZmik + 2532336772U, // VPSHUFHWZmikz + 2517656708U, // VPSHUFHWZri + 49308804U, // VPSHUFHWZrik + 2532336772U, // VPSHUFHWZrikz + 2484102276U, // VPSHUFHWmi + 2517656708U, // VPSHUFHWri + 3188745374U, // VPSHUFLWYmi + 2517656734U, // VPSHUFLWYri + 2484102302U, // VPSHUFLWZ128mi + 49308830U, // VPSHUFLWZ128mik + 2532336798U, // VPSHUFLWZ128mikz + 2517656734U, // VPSHUFLWZ128ri + 49308830U, // VPSHUFLWZ128rik + 2532336798U, // VPSHUFLWZ128rikz + 3188745374U, // VPSHUFLWZ256mi + 49308830U, // VPSHUFLWZ256mik + 2532336798U, // VPSHUFLWZ256mikz + 2517656734U, // VPSHUFLWZ256ri + 49308830U, // VPSHUFLWZ256rik + 2532336798U, // VPSHUFLWZ256rikz + 2953864350U, // VPSHUFLWZmi + 49308830U, // VPSHUFLWZmik + 2532336798U, // VPSHUFLWZmikz + 2517656734U, // VPSHUFLWZri + 49308830U, // VPSHUFLWZrik + 2532336798U, // VPSHUFLWZrikz + 2484102302U, // VPSHUFLWmi + 2517656734U, // VPSHUFLWri + 2517648555U, // VPSIGNBYrm + 2517648555U, // VPSIGNBYrr + 2517648555U, // VPSIGNBrm + 2517648555U, // VPSIGNBrr + 2517649629U, // VPSIGNDYrm + 2517649629U, // VPSIGNDYrr + 2517649629U, // VPSIGNDrm + 2517649629U, // VPSIGNDrr + 2517656843U, // VPSIGNWYrm + 2517656843U, // VPSIGNWYrr + 2517656843U, // VPSIGNWrm + 2517656843U, // VPSIGNWrr + 2517653149U, // VPSLLDQYri + 2484098717U, // VPSLLDQZ128rm + 2517653149U, // VPSLLDQZ128rr + 3188741789U, // VPSLLDQZ256rm + 2517653149U, // VPSLLDQZ256rr + 2953860765U, // VPSLLDQZrm + 2517653149U, // VPSLLDQZrr + 2517653149U, // VPSLLDQri + 2517649488U, // VPSLLDYri + 2517649488U, // VPSLLDYrm + 2517649488U, // VPSLLDYrr + 403720272U, // VPSLLDZ128mbi + 49301584U, // VPSLLDZ128mbik + 2532329552U, // VPSLLDZ128mbikz + 2484095056U, // VPSLLDZ128mi + 49301584U, // VPSLLDZ128mik + 2532329552U, // VPSLLDZ128mikz + 2517649488U, // VPSLLDZ128ri + 49301584U, // VPSLLDZ128rik + 2532329552U, // VPSLLDZ128rikz + 2517649488U, // VPSLLDZ128rm + 49301584U, // VPSLLDZ128rmk + 2532329552U, // VPSLLDZ128rmkz + 2517649488U, // VPSLLDZ128rr + 49301584U, // VPSLLDZ128rrk + 2532329552U, // VPSLLDZ128rrkz + 2551203920U, // VPSLLDZ256mbi + 49301584U, // VPSLLDZ256mbik + 2532329552U, // VPSLLDZ256mbikz + 3188738128U, // VPSLLDZ256mi + 49301584U, // VPSLLDZ256mik + 2532329552U, // VPSLLDZ256mikz + 2517649488U, // VPSLLDZ256ri + 49301584U, // VPSLLDZ256rik + 2532329552U, // VPSLLDZ256rikz + 2517649488U, // VPSLLDZ256rm + 49301584U, // VPSLLDZ256rmk + 2532329552U, // VPSLLDZ256rmkz + 2517649488U, // VPSLLDZ256rr + 49301584U, // VPSLLDZ256rrk + 2532329552U, // VPSLLDZ256rrkz + 403720272U, // VPSLLDZmbi + 49301584U, // VPSLLDZmbik + 2532329552U, // VPSLLDZmbikz + 2953857104U, // VPSLLDZmi + 49301584U, // VPSLLDZmik + 2532329552U, // VPSLLDZmikz + 2517649488U, // VPSLLDZri + 49301584U, // VPSLLDZrik + 2532329552U, // VPSLLDZrikz + 2517649488U, // VPSLLDZrm + 49301584U, // VPSLLDZrmk + 2532329552U, // VPSLLDZrmkz + 2517649488U, // VPSLLDZrr + 49301584U, // VPSLLDZrrk + 2532329552U, // VPSLLDZrrkz + 2517649488U, // VPSLLDri + 2517649488U, // VPSLLDrm + 2517649488U, // VPSLLDrr + 2517653413U, // VPSLLQYri + 2517653413U, // VPSLLQYrm + 2517653413U, // VPSLLQYrr + 2584762277U, // VPSLLQZ128mbi + 49305509U, // VPSLLQZ128mbik + 2532333477U, // VPSLLQZ128mbikz + 2484098981U, // VPSLLQZ128mi + 49305509U, // VPSLLQZ128mik + 2532333477U, // VPSLLQZ128mikz + 2517653413U, // VPSLLQZ128ri + 49305509U, // VPSLLQZ128rik + 2532333477U, // VPSLLQZ128rikz + 2517653413U, // VPSLLQZ128rm + 49305509U, // VPSLLQZ128rmk + 2532333477U, // VPSLLQZ128rmkz + 2517653413U, // VPSLLQZ128rr + 49305509U, // VPSLLQZ128rrk + 2532333477U, // VPSLLQZ128rrkz + 437278629U, // VPSLLQZ256mbi + 49305509U, // VPSLLQZ256mbik + 2532333477U, // VPSLLQZ256mbikz + 3188742053U, // VPSLLQZ256mi + 49305509U, // VPSLLQZ256mik + 2532333477U, // VPSLLQZ256mikz + 2517653413U, // VPSLLQZ256ri + 49305509U, // VPSLLQZ256rik + 2532333477U, // VPSLLQZ256rikz + 2517653413U, // VPSLLQZ256rm + 49305509U, // VPSLLQZ256rmk + 2532333477U, // VPSLLQZ256rmkz + 2517653413U, // VPSLLQZ256rr + 49305509U, // VPSLLQZ256rrk + 2532333477U, // VPSLLQZ256rrkz + 2584762277U, // VPSLLQZmbi + 49305509U, // VPSLLQZmbik + 2532333477U, // VPSLLQZmbikz + 2953861029U, // VPSLLQZmi + 49305509U, // VPSLLQZmik + 2532333477U, // VPSLLQZmikz + 2517653413U, // VPSLLQZri + 49305509U, // VPSLLQZrik + 2532333477U, // VPSLLQZrikz + 2517653413U, // VPSLLQZrm + 49305509U, // VPSLLQZrmk + 2532333477U, // VPSLLQZrmkz + 2517653413U, // VPSLLQZrr + 49305509U, // VPSLLQZrrk + 2532333477U, // VPSLLQZrrkz + 2517653413U, // VPSLLQri + 2517653413U, // VPSLLQrm + 2517653413U, // VPSLLQrr + 2517651537U, // VPSLLVDYrm + 2517651537U, // VPSLLVDYrr + 2517651537U, // VPSLLVDZ128rm + 2517651537U, // VPSLLVDZ128rmb + 49303633U, // VPSLLVDZ128rmbk + 2532331601U, // VPSLLVDZ128rmbkz + 49303633U, // VPSLLVDZ128rmk + 2532331601U, // VPSLLVDZ128rmkz + 2517651537U, // VPSLLVDZ128rr + 49303633U, // VPSLLVDZ128rrk + 2532331601U, // VPSLLVDZ128rrkz + 2517651537U, // VPSLLVDZ256rm + 2517651537U, // VPSLLVDZ256rmb + 49303633U, // VPSLLVDZ256rmbk + 2532331601U, // VPSLLVDZ256rmbkz + 49303633U, // VPSLLVDZ256rmk + 2532331601U, // VPSLLVDZ256rmkz + 2517651537U, // VPSLLVDZ256rr + 49303633U, // VPSLLVDZ256rrk + 2532331601U, // VPSLLVDZ256rrkz + 2517651537U, // VPSLLVDZrm + 2517651537U, // VPSLLVDZrmb + 49303633U, // VPSLLVDZrmbk + 2532331601U, // VPSLLVDZrmbkz + 49303633U, // VPSLLVDZrmk + 2532331601U, // VPSLLVDZrmkz + 2517651537U, // VPSLLVDZrr + 49303633U, // VPSLLVDZrrk + 2532331601U, // VPSLLVDZrrkz + 2517651537U, // VPSLLVDrm + 2517651537U, // VPSLLVDrr + 2517654031U, // VPSLLVQYrm + 2517654031U, // VPSLLVQYrr + 2517654031U, // VPSLLVQZ128rm + 2517654031U, // VPSLLVQZ128rmb + 49306127U, // VPSLLVQZ128rmbk + 2532334095U, // VPSLLVQZ128rmbkz + 49306127U, // VPSLLVQZ128rmk + 2532334095U, // VPSLLVQZ128rmkz + 2517654031U, // VPSLLVQZ128rr + 49306127U, // VPSLLVQZ128rrk + 2532334095U, // VPSLLVQZ128rrkz + 2517654031U, // VPSLLVQZ256rm + 2517654031U, // VPSLLVQZ256rmb + 49306127U, // VPSLLVQZ256rmbk + 2532334095U, // VPSLLVQZ256rmbkz + 49306127U, // VPSLLVQZ256rmk + 2532334095U, // VPSLLVQZ256rmkz + 2517654031U, // VPSLLVQZ256rr + 49306127U, // VPSLLVQZ256rrk + 2532334095U, // VPSLLVQZ256rrkz + 2517654031U, // VPSLLVQZrm + 2517654031U, // VPSLLVQZrmb + 49306127U, // VPSLLVQZrmbk + 2532334095U, // VPSLLVQZrmbkz + 49306127U, // VPSLLVQZrmk + 2532334095U, // VPSLLVQZrmkz + 2517654031U, // VPSLLVQZrr + 49306127U, // VPSLLVQZrrk + 2532334095U, // VPSLLVQZrrkz + 2517654031U, // VPSLLVQrm + 2517654031U, // VPSLLVQrr + 2517657280U, // VPSLLVWZ128rm + 49309376U, // VPSLLVWZ128rmk + 2532337344U, // VPSLLVWZ128rmkz + 2517657280U, // VPSLLVWZ128rr + 49309376U, // VPSLLVWZ128rrk + 2532337344U, // VPSLLVWZ128rrkz + 2517657280U, // VPSLLVWZ256rm + 49309376U, // VPSLLVWZ256rmk + 2532337344U, // VPSLLVWZ256rmkz + 2517657280U, // VPSLLVWZ256rr + 49309376U, // VPSLLVWZ256rrk + 2532337344U, // VPSLLVWZ256rrkz + 2517657280U, // VPSLLVWZrm + 49309376U, // VPSLLVWZrmk + 2532337344U, // VPSLLVWZrmkz + 2517657280U, // VPSLLVWZrr + 49309376U, // VPSLLVWZrrk + 2532337344U, // VPSLLVWZrrkz + 2517656752U, // VPSLLWYri + 2517656752U, // VPSLLWYrm + 2517656752U, // VPSLLWYrr + 2484102320U, // VPSLLWZ128mi + 49308848U, // VPSLLWZ128mik + 2532336816U, // VPSLLWZ128mikz + 2517656752U, // VPSLLWZ128ri + 49308848U, // VPSLLWZ128rik + 2532336816U, // VPSLLWZ128rikz + 2517656752U, // VPSLLWZ128rm + 49308848U, // VPSLLWZ128rmk + 2532336816U, // VPSLLWZ128rmkz + 2517656752U, // VPSLLWZ128rr + 49308848U, // VPSLLWZ128rrk + 2532336816U, // VPSLLWZ128rrkz + 3188745392U, // VPSLLWZ256mi + 49308848U, // VPSLLWZ256mik + 2532336816U, // VPSLLWZ256mikz + 2517656752U, // VPSLLWZ256ri + 49308848U, // VPSLLWZ256rik + 2532336816U, // VPSLLWZ256rikz + 2517656752U, // VPSLLWZ256rm + 49308848U, // VPSLLWZ256rmk + 2532336816U, // VPSLLWZ256rmkz + 2517656752U, // VPSLLWZ256rr + 49308848U, // VPSLLWZ256rrk + 2532336816U, // VPSLLWZ256rrkz + 2953864368U, // VPSLLWZmi + 49308848U, // VPSLLWZmik + 2532336816U, // VPSLLWZmikz + 2517656752U, // VPSLLWZri + 49308848U, // VPSLLWZrik + 2532336816U, // VPSLLWZrikz + 2517656752U, // VPSLLWZrm + 49308848U, // VPSLLWZrmk + 2532336816U, // VPSLLWZrmkz + 2517656752U, // VPSLLWZrr + 49308848U, // VPSLLWZrrk + 2532336816U, // VPSLLWZrrkz + 2517656752U, // VPSLLWri + 2517656752U, // VPSLLWrm + 2517656752U, // VPSLLWrr + 2517649189U, // VPSRADYri + 2517649189U, // VPSRADYrm + 2517649189U, // VPSRADYrr + 403719973U, // VPSRADZ128mbi + 49301285U, // VPSRADZ128mbik + 2532329253U, // VPSRADZ128mbikz + 2484094757U, // VPSRADZ128mi + 49301285U, // VPSRADZ128mik + 2532329253U, // VPSRADZ128mikz + 2517649189U, // VPSRADZ128ri + 49301285U, // VPSRADZ128rik + 2532329253U, // VPSRADZ128rikz + 2517649189U, // VPSRADZ128rm + 49301285U, // VPSRADZ128rmk + 2532329253U, // VPSRADZ128rmkz + 2517649189U, // VPSRADZ128rr + 49301285U, // VPSRADZ128rrk + 2532329253U, // VPSRADZ128rrkz + 2551203621U, // VPSRADZ256mbi + 49301285U, // VPSRADZ256mbik + 2532329253U, // VPSRADZ256mbikz + 3188737829U, // VPSRADZ256mi + 49301285U, // VPSRADZ256mik + 2532329253U, // VPSRADZ256mikz + 2517649189U, // VPSRADZ256ri + 49301285U, // VPSRADZ256rik + 2532329253U, // VPSRADZ256rikz + 2517649189U, // VPSRADZ256rm + 49301285U, // VPSRADZ256rmk + 2532329253U, // VPSRADZ256rmkz + 2517649189U, // VPSRADZ256rr + 49301285U, // VPSRADZ256rrk + 2532329253U, // VPSRADZ256rrkz + 403719973U, // VPSRADZmbi + 49301285U, // VPSRADZmbik + 2532329253U, // VPSRADZmbikz + 2953856805U, // VPSRADZmi + 49301285U, // VPSRADZmik + 2532329253U, // VPSRADZmikz + 2517649189U, // VPSRADZri + 49301285U, // VPSRADZrik + 2532329253U, // VPSRADZrikz + 2517649189U, // VPSRADZrm + 49301285U, // VPSRADZrmk + 2532329253U, // VPSRADZrmkz + 2517649189U, // VPSRADZrr + 49301285U, // VPSRADZrrk + 2532329253U, // VPSRADZrrkz + 2517649189U, // VPSRADri + 2517649189U, // VPSRADrm + 2517649189U, // VPSRADrr + 2584761821U, // VPSRAQZ128mbi + 49305053U, // VPSRAQZ128mbik + 2532333021U, // VPSRAQZ128mbikz + 2484098525U, // VPSRAQZ128mi + 49305053U, // VPSRAQZ128mik + 2532333021U, // VPSRAQZ128mikz + 2517652957U, // VPSRAQZ128ri + 49305053U, // VPSRAQZ128rik + 2532333021U, // VPSRAQZ128rikz + 2517652957U, // VPSRAQZ128rm + 49305053U, // VPSRAQZ128rmk + 2532333021U, // VPSRAQZ128rmkz + 2517652957U, // VPSRAQZ128rr + 49305053U, // VPSRAQZ128rrk + 2532333021U, // VPSRAQZ128rrkz + 437278173U, // VPSRAQZ256mbi + 49305053U, // VPSRAQZ256mbik + 2532333021U, // VPSRAQZ256mbikz + 3188741597U, // VPSRAQZ256mi + 49305053U, // VPSRAQZ256mik + 2532333021U, // VPSRAQZ256mikz + 2517652957U, // VPSRAQZ256ri + 49305053U, // VPSRAQZ256rik + 2532333021U, // VPSRAQZ256rikz + 2517652957U, // VPSRAQZ256rm + 49305053U, // VPSRAQZ256rmk + 2532333021U, // VPSRAQZ256rmkz + 2517652957U, // VPSRAQZ256rr + 49305053U, // VPSRAQZ256rrk + 2532333021U, // VPSRAQZ256rrkz + 2584761821U, // VPSRAQZmbi + 49305053U, // VPSRAQZmbik + 2532333021U, // VPSRAQZmbikz + 2953860573U, // VPSRAQZmi + 49305053U, // VPSRAQZmik + 2532333021U, // VPSRAQZmikz + 2517652957U, // VPSRAQZri + 49305053U, // VPSRAQZrik + 2532333021U, // VPSRAQZrikz + 2517652957U, // VPSRAQZrm + 49305053U, // VPSRAQZrmk + 2532333021U, // VPSRAQZrmkz + 2517652957U, // VPSRAQZrr + 49305053U, // VPSRAQZrrk + 2532333021U, // VPSRAQZrrkz + 2517651508U, // VPSRAVDYrm + 2517651508U, // VPSRAVDYrr + 2517651508U, // VPSRAVDZ128rm + 2517651508U, // VPSRAVDZ128rmb + 49303604U, // VPSRAVDZ128rmbk + 2532331572U, // VPSRAVDZ128rmbkz + 49303604U, // VPSRAVDZ128rmk + 2532331572U, // VPSRAVDZ128rmkz + 2517651508U, // VPSRAVDZ128rr + 49303604U, // VPSRAVDZ128rrk + 2532331572U, // VPSRAVDZ128rrkz + 2517651508U, // VPSRAVDZ256rm + 2517651508U, // VPSRAVDZ256rmb + 49303604U, // VPSRAVDZ256rmbk + 2532331572U, // VPSRAVDZ256rmbkz + 49303604U, // VPSRAVDZ256rmk + 2532331572U, // VPSRAVDZ256rmkz + 2517651508U, // VPSRAVDZ256rr + 49303604U, // VPSRAVDZ256rrk + 2532331572U, // VPSRAVDZ256rrkz + 2517651508U, // VPSRAVDZrm + 2517651508U, // VPSRAVDZrmb + 49303604U, // VPSRAVDZrmbk + 2532331572U, // VPSRAVDZrmbkz + 49303604U, // VPSRAVDZrmk + 2532331572U, // VPSRAVDZrmkz + 2517651508U, // VPSRAVDZrr + 49303604U, // VPSRAVDZrrk + 2532331572U, // VPSRAVDZrrkz + 2517651508U, // VPSRAVDrm + 2517651508U, // VPSRAVDrr + 2517654002U, // VPSRAVQZ128rm + 2517654002U, // VPSRAVQZ128rmb + 49306098U, // VPSRAVQZ128rmbk + 2532334066U, // VPSRAVQZ128rmbkz + 49306098U, // VPSRAVQZ128rmk + 2532334066U, // VPSRAVQZ128rmkz + 2517654002U, // VPSRAVQZ128rr + 49306098U, // VPSRAVQZ128rrk + 2532334066U, // VPSRAVQZ128rrkz + 2517654002U, // VPSRAVQZ256rm + 2517654002U, // VPSRAVQZ256rmb + 49306098U, // VPSRAVQZ256rmbk + 2532334066U, // VPSRAVQZ256rmbkz + 49306098U, // VPSRAVQZ256rmk + 2532334066U, // VPSRAVQZ256rmkz + 2517654002U, // VPSRAVQZ256rr + 49306098U, // VPSRAVQZ256rrk + 2532334066U, // VPSRAVQZ256rrkz + 2517654002U, // VPSRAVQZrm + 2517654002U, // VPSRAVQZrmb + 49306098U, // VPSRAVQZrmbk + 2532334066U, // VPSRAVQZrmbkz + 49306098U, // VPSRAVQZrmk + 2532334066U, // VPSRAVQZrmkz + 2517654002U, // VPSRAVQZrr + 49306098U, // VPSRAVQZrrk + 2532334066U, // VPSRAVQZrrkz + 2517657251U, // VPSRAVWZ128rm + 49309347U, // VPSRAVWZ128rmk + 2532337315U, // VPSRAVWZ128rmkz + 2517657251U, // VPSRAVWZ128rr + 49309347U, // VPSRAVWZ128rrk + 2532337315U, // VPSRAVWZ128rrkz + 2517657251U, // VPSRAVWZ256rm + 49309347U, // VPSRAVWZ256rmk + 2532337315U, // VPSRAVWZ256rmkz + 2517657251U, // VPSRAVWZ256rr + 49309347U, // VPSRAVWZ256rrk + 2532337315U, // VPSRAVWZ256rrkz + 2517657251U, // VPSRAVWZrm + 49309347U, // VPSRAVWZrmk + 2532337315U, // VPSRAVWZrmkz + 2517657251U, // VPSRAVWZrr + 49309347U, // VPSRAVWZrrk + 2532337315U, // VPSRAVWZrrkz + 2517656395U, // VPSRAWYri + 2517656395U, // VPSRAWYrm + 2517656395U, // VPSRAWYrr + 2484101963U, // VPSRAWZ128mi + 49308491U, // VPSRAWZ128mik + 2532336459U, // VPSRAWZ128mikz + 2517656395U, // VPSRAWZ128ri + 49308491U, // VPSRAWZ128rik + 2532336459U, // VPSRAWZ128rikz + 2517656395U, // VPSRAWZ128rm + 49308491U, // VPSRAWZ128rmk + 2532336459U, // VPSRAWZ128rmkz + 2517656395U, // VPSRAWZ128rr + 49308491U, // VPSRAWZ128rrk + 2532336459U, // VPSRAWZ128rrkz + 3188745035U, // VPSRAWZ256mi + 49308491U, // VPSRAWZ256mik + 2532336459U, // VPSRAWZ256mikz + 2517656395U, // VPSRAWZ256ri + 49308491U, // VPSRAWZ256rik + 2532336459U, // VPSRAWZ256rikz + 2517656395U, // VPSRAWZ256rm + 49308491U, // VPSRAWZ256rmk + 2532336459U, // VPSRAWZ256rmkz + 2517656395U, // VPSRAWZ256rr + 49308491U, // VPSRAWZ256rrk + 2532336459U, // VPSRAWZ256rrkz + 2953864011U, // VPSRAWZmi + 49308491U, // VPSRAWZmik + 2532336459U, // VPSRAWZmikz + 2517656395U, // VPSRAWZri + 49308491U, // VPSRAWZrik + 2532336459U, // VPSRAWZrikz + 2517656395U, // VPSRAWZrm + 49308491U, // VPSRAWZrmk + 2532336459U, // VPSRAWZrmkz + 2517656395U, // VPSRAWZrr + 49308491U, // VPSRAWZrrk + 2532336459U, // VPSRAWZrrkz + 2517656395U, // VPSRAWri + 2517656395U, // VPSRAWrm + 2517656395U, // VPSRAWrr + 2517653158U, // VPSRLDQYri + 2484098726U, // VPSRLDQZ128rm + 2517653158U, // VPSRLDQZ128rr + 3188741798U, // VPSRLDQZ256rm + 2517653158U, // VPSRLDQZ256rr + 2953860774U, // VPSRLDQZrm + 2517653158U, // VPSRLDQZrr + 2517653158U, // VPSRLDQri + 2517649513U, // VPSRLDYri + 2517649513U, // VPSRLDYrm + 2517649513U, // VPSRLDYrr + 403720297U, // VPSRLDZ128mbi + 49301609U, // VPSRLDZ128mbik + 2532329577U, // VPSRLDZ128mbikz + 2484095081U, // VPSRLDZ128mi + 49301609U, // VPSRLDZ128mik + 2532329577U, // VPSRLDZ128mikz + 2517649513U, // VPSRLDZ128ri + 49301609U, // VPSRLDZ128rik + 2532329577U, // VPSRLDZ128rikz + 2517649513U, // VPSRLDZ128rm + 49301609U, // VPSRLDZ128rmk + 2532329577U, // VPSRLDZ128rmkz + 2517649513U, // VPSRLDZ128rr + 49301609U, // VPSRLDZ128rrk + 2532329577U, // VPSRLDZ128rrkz + 2551203945U, // VPSRLDZ256mbi + 49301609U, // VPSRLDZ256mbik + 2532329577U, // VPSRLDZ256mbikz + 3188738153U, // VPSRLDZ256mi + 49301609U, // VPSRLDZ256mik + 2532329577U, // VPSRLDZ256mikz + 2517649513U, // VPSRLDZ256ri + 49301609U, // VPSRLDZ256rik + 2532329577U, // VPSRLDZ256rikz + 2517649513U, // VPSRLDZ256rm + 49301609U, // VPSRLDZ256rmk + 2532329577U, // VPSRLDZ256rmkz + 2517649513U, // VPSRLDZ256rr + 49301609U, // VPSRLDZ256rrk + 2532329577U, // VPSRLDZ256rrkz + 403720297U, // VPSRLDZmbi + 49301609U, // VPSRLDZmbik + 2532329577U, // VPSRLDZmbikz + 2953857129U, // VPSRLDZmi + 49301609U, // VPSRLDZmik + 2532329577U, // VPSRLDZmikz + 2517649513U, // VPSRLDZri + 49301609U, // VPSRLDZrik + 2532329577U, // VPSRLDZrikz + 2517649513U, // VPSRLDZrm + 49301609U, // VPSRLDZrmk + 2532329577U, // VPSRLDZrmkz + 2517649513U, // VPSRLDZrr + 49301609U, // VPSRLDZrrk + 2532329577U, // VPSRLDZrrkz + 2517649513U, // VPSRLDri + 2517649513U, // VPSRLDrm + 2517649513U, // VPSRLDrr + 2517653438U, // VPSRLQYri + 2517653438U, // VPSRLQYrm + 2517653438U, // VPSRLQYrr + 2584762302U, // VPSRLQZ128mbi + 49305534U, // VPSRLQZ128mbik + 2532333502U, // VPSRLQZ128mbikz + 2484099006U, // VPSRLQZ128mi + 49305534U, // VPSRLQZ128mik + 2532333502U, // VPSRLQZ128mikz + 2517653438U, // VPSRLQZ128ri + 49305534U, // VPSRLQZ128rik + 2532333502U, // VPSRLQZ128rikz + 2517653438U, // VPSRLQZ128rm + 49305534U, // VPSRLQZ128rmk + 2532333502U, // VPSRLQZ128rmkz + 2517653438U, // VPSRLQZ128rr + 49305534U, // VPSRLQZ128rrk + 2532333502U, // VPSRLQZ128rrkz + 437278654U, // VPSRLQZ256mbi + 49305534U, // VPSRLQZ256mbik + 2532333502U, // VPSRLQZ256mbikz + 3188742078U, // VPSRLQZ256mi + 49305534U, // VPSRLQZ256mik + 2532333502U, // VPSRLQZ256mikz + 2517653438U, // VPSRLQZ256ri + 49305534U, // VPSRLQZ256rik + 2532333502U, // VPSRLQZ256rikz + 2517653438U, // VPSRLQZ256rm + 49305534U, // VPSRLQZ256rmk + 2532333502U, // VPSRLQZ256rmkz + 2517653438U, // VPSRLQZ256rr + 49305534U, // VPSRLQZ256rrk + 2532333502U, // VPSRLQZ256rrkz + 2584762302U, // VPSRLQZmbi + 49305534U, // VPSRLQZmbik + 2532333502U, // VPSRLQZmbikz + 2953861054U, // VPSRLQZmi + 49305534U, // VPSRLQZmik + 2532333502U, // VPSRLQZmikz + 2517653438U, // VPSRLQZri + 49305534U, // VPSRLQZrik + 2532333502U, // VPSRLQZrikz + 2517653438U, // VPSRLQZrm + 49305534U, // VPSRLQZrmk + 2532333502U, // VPSRLQZrmkz + 2517653438U, // VPSRLQZrr + 49305534U, // VPSRLQZrrk + 2532333502U, // VPSRLQZrrkz + 2517653438U, // VPSRLQri + 2517653438U, // VPSRLQrm + 2517653438U, // VPSRLQrr + 2517651555U, // VPSRLVDYrm + 2517651555U, // VPSRLVDYrr + 2517651555U, // VPSRLVDZ128rm + 2517651555U, // VPSRLVDZ128rmb + 49303651U, // VPSRLVDZ128rmbk + 2532331619U, // VPSRLVDZ128rmbkz + 49303651U, // VPSRLVDZ128rmk + 2532331619U, // VPSRLVDZ128rmkz + 2517651555U, // VPSRLVDZ128rr + 49303651U, // VPSRLVDZ128rrk + 2532331619U, // VPSRLVDZ128rrkz + 2517651555U, // VPSRLVDZ256rm + 2517651555U, // VPSRLVDZ256rmb + 49303651U, // VPSRLVDZ256rmbk + 2532331619U, // VPSRLVDZ256rmbkz + 49303651U, // VPSRLVDZ256rmk + 2532331619U, // VPSRLVDZ256rmkz + 2517651555U, // VPSRLVDZ256rr + 49303651U, // VPSRLVDZ256rrk + 2532331619U, // VPSRLVDZ256rrkz + 2517651555U, // VPSRLVDZrm + 2517651555U, // VPSRLVDZrmb + 49303651U, // VPSRLVDZrmbk + 2532331619U, // VPSRLVDZrmbkz + 49303651U, // VPSRLVDZrmk + 2532331619U, // VPSRLVDZrmkz + 2517651555U, // VPSRLVDZrr + 49303651U, // VPSRLVDZrrk + 2532331619U, // VPSRLVDZrrkz + 2517651555U, // VPSRLVDrm + 2517651555U, // VPSRLVDrr + 2517654049U, // VPSRLVQYrm + 2517654049U, // VPSRLVQYrr + 2517654049U, // VPSRLVQZ128rm + 2517654049U, // VPSRLVQZ128rmb + 49306145U, // VPSRLVQZ128rmbk + 2532334113U, // VPSRLVQZ128rmbkz + 49306145U, // VPSRLVQZ128rmk + 2532334113U, // VPSRLVQZ128rmkz + 2517654049U, // VPSRLVQZ128rr + 49306145U, // VPSRLVQZ128rrk + 2532334113U, // VPSRLVQZ128rrkz + 2517654049U, // VPSRLVQZ256rm + 2517654049U, // VPSRLVQZ256rmb + 49306145U, // VPSRLVQZ256rmbk + 2532334113U, // VPSRLVQZ256rmbkz + 49306145U, // VPSRLVQZ256rmk + 2532334113U, // VPSRLVQZ256rmkz + 2517654049U, // VPSRLVQZ256rr + 49306145U, // VPSRLVQZ256rrk + 2532334113U, // VPSRLVQZ256rrkz + 2517654049U, // VPSRLVQZrm + 2517654049U, // VPSRLVQZrmb + 49306145U, // VPSRLVQZrmbk + 2532334113U, // VPSRLVQZrmbkz + 49306145U, // VPSRLVQZrmk + 2532334113U, // VPSRLVQZrmkz + 2517654049U, // VPSRLVQZrr + 49306145U, // VPSRLVQZrrk + 2532334113U, // VPSRLVQZrrkz + 2517654049U, // VPSRLVQrm + 2517654049U, // VPSRLVQrr + 2517657289U, // VPSRLVWZ128rm + 49309385U, // VPSRLVWZ128rmk + 2532337353U, // VPSRLVWZ128rmkz + 2517657289U, // VPSRLVWZ128rr + 49309385U, // VPSRLVWZ128rrk + 2532337353U, // VPSRLVWZ128rrkz + 2517657289U, // VPSRLVWZ256rm + 49309385U, // VPSRLVWZ256rmk + 2532337353U, // VPSRLVWZ256rmkz + 2517657289U, // VPSRLVWZ256rr + 49309385U, // VPSRLVWZ256rrk + 2532337353U, // VPSRLVWZ256rrkz + 2517657289U, // VPSRLVWZrm + 49309385U, // VPSRLVWZrmk + 2532337353U, // VPSRLVWZrmkz + 2517657289U, // VPSRLVWZrr + 49309385U, // VPSRLVWZrrk + 2532337353U, // VPSRLVWZrrkz + 2517656769U, // VPSRLWYri + 2517656769U, // VPSRLWYrm + 2517656769U, // VPSRLWYrr + 2484102337U, // VPSRLWZ128mi + 49308865U, // VPSRLWZ128mik + 2532336833U, // VPSRLWZ128mikz + 2517656769U, // VPSRLWZ128ri + 49308865U, // VPSRLWZ128rik + 2532336833U, // VPSRLWZ128rikz + 2517656769U, // VPSRLWZ128rm + 49308865U, // VPSRLWZ128rmk + 2532336833U, // VPSRLWZ128rmkz + 2517656769U, // VPSRLWZ128rr + 49308865U, // VPSRLWZ128rrk + 2532336833U, // VPSRLWZ128rrkz + 3188745409U, // VPSRLWZ256mi + 49308865U, // VPSRLWZ256mik + 2532336833U, // VPSRLWZ256mikz + 2517656769U, // VPSRLWZ256ri + 49308865U, // VPSRLWZ256rik + 2532336833U, // VPSRLWZ256rikz + 2517656769U, // VPSRLWZ256rm + 49308865U, // VPSRLWZ256rmk + 2532336833U, // VPSRLWZ256rmkz + 2517656769U, // VPSRLWZ256rr + 49308865U, // VPSRLWZ256rrk + 2532336833U, // VPSRLWZ256rrkz + 2953864385U, // VPSRLWZmi + 49308865U, // VPSRLWZmik + 2532336833U, // VPSRLWZmikz + 2517656769U, // VPSRLWZri + 49308865U, // VPSRLWZrik + 2532336833U, // VPSRLWZrikz + 2517656769U, // VPSRLWZrm + 49308865U, // VPSRLWZrmk + 2532336833U, // VPSRLWZrmkz + 2517656769U, // VPSRLWZrr + 49308865U, // VPSRLWZrrk + 2532336833U, // VPSRLWZrrkz + 2517656769U, // VPSRLWri + 2517656769U, // VPSRLWrm + 2517656769U, // VPSRLWrr + 2517648336U, // VPSUBBYrm + 2517648336U, // VPSUBBYrr + 2517648336U, // VPSUBBZ128rm + 49300432U, // VPSUBBZ128rmk + 2532328400U, // VPSUBBZ128rmkz + 2517648336U, // VPSUBBZ128rr + 49300432U, // VPSUBBZ128rrk + 2532328400U, // VPSUBBZ128rrkz + 2517648336U, // VPSUBBZ256rm + 49300432U, // VPSUBBZ256rmk + 2532328400U, // VPSUBBZ256rmkz + 2517648336U, // VPSUBBZ256rr + 49300432U, // VPSUBBZ256rrk + 2532328400U, // VPSUBBZ256rrkz + 2517648336U, // VPSUBBZrm + 49300432U, // VPSUBBZrmk + 2532328400U, // VPSUBBZrmkz + 2517648336U, // VPSUBBZrr + 49300432U, // VPSUBBZrrk + 2532328400U, // VPSUBBZrrkz + 2517648336U, // VPSUBBrm + 2517648336U, // VPSUBBrr + 2517649227U, // VPSUBDYrm + 2517649227U, // VPSUBDYrr + 2517649227U, // VPSUBDZ128rm + 2517649227U, // VPSUBDZ128rmb + 49301323U, // VPSUBDZ128rmbk + 2532329291U, // VPSUBDZ128rmbkz + 49301323U, // VPSUBDZ128rmk + 2532329291U, // VPSUBDZ128rmkz + 2517649227U, // VPSUBDZ128rr + 49301323U, // VPSUBDZ128rrk + 2532329291U, // VPSUBDZ128rrkz + 2517649227U, // VPSUBDZ256rm + 2517649227U, // VPSUBDZ256rmb + 49301323U, // VPSUBDZ256rmbk + 2532329291U, // VPSUBDZ256rmbkz + 49301323U, // VPSUBDZ256rmk + 2532329291U, // VPSUBDZ256rmkz + 2517649227U, // VPSUBDZ256rr + 49301323U, // VPSUBDZ256rrk + 2532329291U, // VPSUBDZ256rrkz + 2517649227U, // VPSUBDZrm + 2517649227U, // VPSUBDZrmb + 49301323U, // VPSUBDZrmbk + 2532329291U, // VPSUBDZrmbkz + 49301323U, // VPSUBDZrmk + 2532329291U, // VPSUBDZrmkz + 2517649227U, // VPSUBDZrr + 49301323U, // VPSUBDZrrk + 2532329291U, // VPSUBDZrrkz + 2517649227U, // VPSUBDrm + 2517649227U, // VPSUBDrr + 2517652986U, // VPSUBQYrm + 2517652986U, // VPSUBQYrr + 2517652986U, // VPSUBQZ128rm + 2517652986U, // VPSUBQZ128rmb + 49305082U, // VPSUBQZ128rmbk + 2532333050U, // VPSUBQZ128rmbkz + 49305082U, // VPSUBQZ128rmk + 2532333050U, // VPSUBQZ128rmkz + 2517652986U, // VPSUBQZ128rr + 49305082U, // VPSUBQZ128rrk + 2532333050U, // VPSUBQZ128rrkz + 2517652986U, // VPSUBQZ256rm + 2517652986U, // VPSUBQZ256rmb + 49305082U, // VPSUBQZ256rmbk + 2532333050U, // VPSUBQZ256rmbkz + 49305082U, // VPSUBQZ256rmk + 2532333050U, // VPSUBQZ256rmkz + 2517652986U, // VPSUBQZ256rr + 49305082U, // VPSUBQZ256rrk + 2532333050U, // VPSUBQZ256rrkz + 2517652986U, // VPSUBQZrm + 2517652986U, // VPSUBQZrmb + 49305082U, // VPSUBQZrmbk + 2532333050U, // VPSUBQZrmbkz + 49305082U, // VPSUBQZrmk + 2532333050U, // VPSUBQZrmkz + 2517652986U, // VPSUBQZrr + 49305082U, // VPSUBQZrrk + 2532333050U, // VPSUBQZrrkz + 2517652986U, // VPSUBQrm + 2517652986U, // VPSUBQrr + 2517648720U, // VPSUBSBYrm + 2517648720U, // VPSUBSBYrr + 2517648720U, // VPSUBSBZ128rm + 49300816U, // VPSUBSBZ128rmk + 2532328784U, // VPSUBSBZ128rmkz + 2517648720U, // VPSUBSBZ128rr + 49300816U, // VPSUBSBZ128rrk + 2532328784U, // VPSUBSBZ128rrkz + 2517648720U, // VPSUBSBZ256rm + 49300816U, // VPSUBSBZ256rmk + 2532328784U, // VPSUBSBZ256rmkz + 2517648720U, // VPSUBSBZ256rr + 49300816U, // VPSUBSBZ256rrk + 2532328784U, // VPSUBSBZ256rrkz + 2517648720U, // VPSUBSBZrm + 49300816U, // VPSUBSBZrmk + 2532328784U, // VPSUBSBZrmkz + 2517648720U, // VPSUBSBZrr + 49300816U, // VPSUBSBZrrk + 2532328784U, // VPSUBSBZrrkz + 2517648720U, // VPSUBSBrm + 2517648720U, // VPSUBSBrr + 2517656994U, // VPSUBSWYrm + 2517656994U, // VPSUBSWYrr + 2517656994U, // VPSUBSWZ128rm + 49309090U, // VPSUBSWZ128rmk + 2532337058U, // VPSUBSWZ128rmkz + 2517656994U, // VPSUBSWZ128rr + 49309090U, // VPSUBSWZ128rrk + 2532337058U, // VPSUBSWZ128rrkz + 2517656994U, // VPSUBSWZ256rm + 49309090U, // VPSUBSWZ256rmk + 2532337058U, // VPSUBSWZ256rmkz + 2517656994U, // VPSUBSWZ256rr + 49309090U, // VPSUBSWZ256rrk + 2532337058U, // VPSUBSWZ256rrkz + 2517656994U, // VPSUBSWZrm + 49309090U, // VPSUBSWZrmk + 2532337058U, // VPSUBSWZrmkz + 2517656994U, // VPSUBSWZrr + 49309090U, // VPSUBSWZrrk + 2532337058U, // VPSUBSWZrrkz + 2517656994U, // VPSUBSWrm + 2517656994U, // VPSUBSWrr + 2517648774U, // VPSUBUSBYrm + 2517648774U, // VPSUBUSBYrr + 2517648774U, // VPSUBUSBZ128rm + 49300870U, // VPSUBUSBZ128rmk + 2532328838U, // VPSUBUSBZ128rmkz + 2517648774U, // VPSUBUSBZ128rr + 49300870U, // VPSUBUSBZ128rrk + 2532328838U, // VPSUBUSBZ128rrkz + 2517648774U, // VPSUBUSBZ256rm + 49300870U, // VPSUBUSBZ256rmk + 2532328838U, // VPSUBUSBZ256rmkz + 2517648774U, // VPSUBUSBZ256rr + 49300870U, // VPSUBUSBZ256rrk + 2532328838U, // VPSUBUSBZ256rrkz + 2517648774U, // VPSUBUSBZrm + 49300870U, // VPSUBUSBZrmk + 2532328838U, // VPSUBUSBZrmkz + 2517648774U, // VPSUBUSBZrr + 49300870U, // VPSUBUSBZrrk + 2532328838U, // VPSUBUSBZrrkz + 2517648774U, // VPSUBUSBrm + 2517648774U, // VPSUBUSBrr + 2517657089U, // VPSUBUSWYrm + 2517657089U, // VPSUBUSWYrr + 2517657089U, // VPSUBUSWZ128rm + 49309185U, // VPSUBUSWZ128rmk + 2532337153U, // VPSUBUSWZ128rmkz + 2517657089U, // VPSUBUSWZ128rr + 49309185U, // VPSUBUSWZ128rrk + 2532337153U, // VPSUBUSWZ128rrkz + 2517657089U, // VPSUBUSWZ256rm + 49309185U, // VPSUBUSWZ256rmk + 2532337153U, // VPSUBUSWZ256rmkz + 2517657089U, // VPSUBUSWZ256rr + 49309185U, // VPSUBUSWZ256rrk + 2532337153U, // VPSUBUSWZ256rrkz + 2517657089U, // VPSUBUSWZrm + 49309185U, // VPSUBUSWZrmk + 2532337153U, // VPSUBUSWZrmkz + 2517657089U, // VPSUBUSWZrr + 49309185U, // VPSUBUSWZrrk + 2532337153U, // VPSUBUSWZrrkz + 2517657089U, // VPSUBUSWrm + 2517657089U, // VPSUBUSWrr + 2517656507U, // VPSUBWYrm + 2517656507U, // VPSUBWYrr + 2517656507U, // VPSUBWZ128rm + 49308603U, // VPSUBWZ128rmk + 2532336571U, // VPSUBWZ128rmkz + 2517656507U, // VPSUBWZ128rr + 49308603U, // VPSUBWZ128rrk + 2532336571U, // VPSUBWZ128rrkz + 2517656507U, // VPSUBWZ256rm + 49308603U, // VPSUBWZ256rmk + 2532336571U, // VPSUBWZ256rmkz + 2517656507U, // VPSUBWZ256rr + 49308603U, // VPSUBWZ256rrk + 2532336571U, // VPSUBWZ256rrkz + 2517656507U, // VPSUBWZrm + 49308603U, // VPSUBWZrmk + 2532336571U, // VPSUBWZrmkz + 2517656507U, // VPSUBWZrr + 49308603U, // VPSUBWZrrk + 2532336571U, // VPSUBWZrrkz + 2517656507U, // VPSUBWrm + 2517656507U, // VPSUBWrr + 2182105105U, // VPTERNLOGDZ128rmbi + 49301521U, // VPTERNLOGDZ128rmbik + 2196785169U, // VPTERNLOGDZ128rmbikz + 2182105105U, // VPTERNLOGDZ128rmi + 49301521U, // VPTERNLOGDZ128rmik + 2196785169U, // VPTERNLOGDZ128rmikz + 2182105105U, // VPTERNLOGDZ128rri + 49301521U, // VPTERNLOGDZ128rrik + 2196785169U, // VPTERNLOGDZ128rrikz + 2182105105U, // VPTERNLOGDZ256rmbi + 49301521U, // VPTERNLOGDZ256rmbik + 2196785169U, // VPTERNLOGDZ256rmbikz + 2182105105U, // VPTERNLOGDZ256rmi + 49301521U, // VPTERNLOGDZ256rmik + 2196785169U, // VPTERNLOGDZ256rmikz + 2182105105U, // VPTERNLOGDZ256rri + 49301521U, // VPTERNLOGDZ256rrik + 2196785169U, // VPTERNLOGDZ256rrikz + 2182105105U, // VPTERNLOGDZrmbi + 49301521U, // VPTERNLOGDZrmbik + 2196785169U, // VPTERNLOGDZrmbikz + 2182105105U, // VPTERNLOGDZrmi + 49301521U, // VPTERNLOGDZrmik + 2196785169U, // VPTERNLOGDZrmikz + 2182105105U, // VPTERNLOGDZrri + 49301521U, // VPTERNLOGDZrrik + 2196785169U, // VPTERNLOGDZrrikz + 2182109073U, // VPTERNLOGQZ128rmbi + 49305489U, // VPTERNLOGQZ128rmbik + 2196789137U, // VPTERNLOGQZ128rmbikz + 2182109073U, // VPTERNLOGQZ128rmi + 49305489U, // VPTERNLOGQZ128rmik + 2196789137U, // VPTERNLOGQZ128rmikz + 2182109073U, // VPTERNLOGQZ128rri + 49305489U, // VPTERNLOGQZ128rrik + 2196789137U, // VPTERNLOGQZ128rrikz + 2182109073U, // VPTERNLOGQZ256rmbi + 49305489U, // VPTERNLOGQZ256rmbik + 2196789137U, // VPTERNLOGQZ256rmbikz + 2182109073U, // VPTERNLOGQZ256rmi + 49305489U, // VPTERNLOGQZ256rmik + 2196789137U, // VPTERNLOGQZ256rmikz + 2182109073U, // VPTERNLOGQZ256rri + 49305489U, // VPTERNLOGQZ256rrik + 2196789137U, // VPTERNLOGQZ256rrikz + 2182109073U, // VPTERNLOGQZrmbi + 49305489U, // VPTERNLOGQZrmbik + 2196789137U, // VPTERNLOGQZrmbikz + 2182109073U, // VPTERNLOGQZrmi + 49305489U, // VPTERNLOGQZrmik + 2196789137U, // VPTERNLOGQZrmikz + 2182109073U, // VPTERNLOGQZrri + 49305489U, // VPTERNLOGQZrrik + 2196789137U, // VPTERNLOGQZrrikz + 2517648537U, // VPTESTMBZ128rm + 384844953U, // VPTESTMBZ128rmk + 2517648537U, // VPTESTMBZ128rr + 384844953U, // VPTESTMBZ128rrk + 2517648537U, // VPTESTMBZ256rm + 384844953U, // VPTESTMBZ256rmk + 2517648537U, // VPTESTMBZ256rr + 384844953U, // VPTESTMBZ256rrk + 2517648537U, // VPTESTMBZrm + 384844953U, // VPTESTMBZrmk + 2517648537U, // VPTESTMBZrr + 384844953U, // VPTESTMBZrrk + 2517649578U, // VPTESTMDZ128rm + 2517649578U, // VPTESTMDZ128rmb + 384845994U, // VPTESTMDZ128rmbk + 384845994U, // VPTESTMDZ128rmk + 2517649578U, // VPTESTMDZ128rr + 384845994U, // VPTESTMDZ128rrk + 2517649578U, // VPTESTMDZ256rm + 2517649578U, // VPTESTMDZ256rmb + 384845994U, // VPTESTMDZ256rmbk + 384845994U, // VPTESTMDZ256rmk + 2517649578U, // VPTESTMDZ256rr + 384845994U, // VPTESTMDZ256rrk + 2517649578U, // VPTESTMDZrm + 2517649578U, // VPTESTMDZrmb + 384845994U, // VPTESTMDZrmbk + 384845994U, // VPTESTMDZrmk + 2517649578U, // VPTESTMDZrr + 384845994U, // VPTESTMDZrrk + 2517653494U, // VPTESTMQZ128rm + 2517653494U, // VPTESTMQZ128rmb + 384849910U, // VPTESTMQZ128rmbk + 384849910U, // VPTESTMQZ128rmk + 2517653494U, // VPTESTMQZ128rr + 384849910U, // VPTESTMQZ128rrk + 2517653494U, // VPTESTMQZ256rm + 2517653494U, // VPTESTMQZ256rmb + 384849910U, // VPTESTMQZ256rmbk + 384849910U, // VPTESTMQZ256rmk + 2517653494U, // VPTESTMQZ256rr + 384849910U, // VPTESTMQZ256rrk + 2517653494U, // VPTESTMQZrm + 2517653494U, // VPTESTMQZrmb + 384849910U, // VPTESTMQZrmbk + 384849910U, // VPTESTMQZrmk + 2517653494U, // VPTESTMQZrr + 384849910U, // VPTESTMQZrrk + 2517656825U, // VPTESTMWZ128rm + 384853241U, // VPTESTMWZ128rmk + 2517656825U, // VPTESTMWZ128rr + 384853241U, // VPTESTMWZ128rrk + 2517656825U, // VPTESTMWZ256rm + 384853241U, // VPTESTMWZ256rmk + 2517656825U, // VPTESTMWZ256rr + 384853241U, // VPTESTMWZ256rrk + 2517656825U, // VPTESTMWZrm + 384853241U, // VPTESTMWZrmk + 2517656825U, // VPTESTMWZrr + 384853241U, // VPTESTMWZrrk + 2517648496U, // VPTESTNMBZ128rm + 384844912U, // VPTESTNMBZ128rmk + 2517648496U, // VPTESTNMBZ128rr + 384844912U, // VPTESTNMBZ128rrk + 2517648496U, // VPTESTNMBZ256rm + 384844912U, // VPTESTNMBZ256rmk + 2517648496U, // VPTESTNMBZ256rr + 384844912U, // VPTESTNMBZ256rrk + 2517648496U, // VPTESTNMBZrm + 384844912U, // VPTESTNMBZrmk + 2517648496U, // VPTESTNMBZrr + 384844912U, // VPTESTNMBZrrk + 2517649551U, // VPTESTNMDZ128rm + 2517649551U, // VPTESTNMDZ128rmb + 384845967U, // VPTESTNMDZ128rmbk + 384845967U, // VPTESTNMDZ128rmk + 2517649551U, // VPTESTNMDZ128rr + 384845967U, // VPTESTNMDZ128rrk + 2517649551U, // VPTESTNMDZ256rm + 2517649551U, // VPTESTNMDZ256rmb + 384845967U, // VPTESTNMDZ256rmbk + 384845967U, // VPTESTNMDZ256rmk + 2517649551U, // VPTESTNMDZ256rr + 384845967U, // VPTESTNMDZ256rrk + 2517649551U, // VPTESTNMDZrm + 2517649551U, // VPTESTNMDZrmb + 384845967U, // VPTESTNMDZrmbk + 384845967U, // VPTESTNMDZrmk + 2517649551U, // VPTESTNMDZrr + 384845967U, // VPTESTNMDZrrk + 2517653467U, // VPTESTNMQZ128rm + 2517653467U, // VPTESTNMQZ128rmb + 384849883U, // VPTESTNMQZ128rmbk + 384849883U, // VPTESTNMQZ128rmk + 2517653467U, // VPTESTNMQZ128rr + 384849883U, // VPTESTNMQZ128rrk + 2517653467U, // VPTESTNMQZ256rm + 2517653467U, // VPTESTNMQZ256rmb + 384849883U, // VPTESTNMQZ256rmbk + 384849883U, // VPTESTNMQZ256rmk + 2517653467U, // VPTESTNMQZ256rr + 384849883U, // VPTESTNMQZ256rrk + 2517653467U, // VPTESTNMQZrm + 2517653467U, // VPTESTNMQZrmb + 384849883U, // VPTESTNMQZrmbk + 384849883U, // VPTESTNMQZrmk + 2517653467U, // VPTESTNMQZrr + 384849883U, // VPTESTNMQZrrk + 2517656798U, // VPTESTNMWZ128rm + 384853214U, // VPTESTNMWZ128rmk + 2517656798U, // VPTESTNMWZ128rr + 384853214U, // VPTESTNMWZ128rrk + 2517656798U, // VPTESTNMWZ256rm + 384853214U, // VPTESTNMWZ256rmk + 2517656798U, // VPTESTNMWZ256rr + 384853214U, // VPTESTNMWZ256rrk + 2517656798U, // VPTESTNMWZrm + 384853214U, // VPTESTNMWZrmk + 2517656798U, // VPTESTNMWZrr + 384853214U, // VPTESTNMWZrrk + 1041261209U, // VPTESTYrm + 370172569U, // VPTESTYrr + 672162457U, // VPTESTrm + 370172569U, // VPTESTrr + 2517656453U, // VPUNPCKHBWYrm + 2517656453U, // VPUNPCKHBWYrr + 2517656453U, // VPUNPCKHBWZ128rm + 49308549U, // VPUNPCKHBWZ128rmk + 2532336517U, // VPUNPCKHBWZ128rmkz + 2517656453U, // VPUNPCKHBWZ128rr + 49308549U, // VPUNPCKHBWZ128rrk + 2532336517U, // VPUNPCKHBWZ128rrkz + 2517656453U, // VPUNPCKHBWZ256rm + 49308549U, // VPUNPCKHBWZ256rmk + 2532336517U, // VPUNPCKHBWZ256rmkz + 2517656453U, // VPUNPCKHBWZ256rr + 49308549U, // VPUNPCKHBWZ256rrk + 2532336517U, // VPUNPCKHBWZ256rrkz + 2517656453U, // VPUNPCKHBWZrm + 49308549U, // VPUNPCKHBWZrmk + 2532336517U, // VPUNPCKHBWZrmkz + 2517656453U, // VPUNPCKHBWZrr + 49308549U, // VPUNPCKHBWZrrk + 2532336517U, // VPUNPCKHBWZrrkz + 2517656453U, // VPUNPCKHBWrm + 2517656453U, // VPUNPCKHBWrr + 2517653106U, // VPUNPCKHDQYrm + 2517653106U, // VPUNPCKHDQYrr + 2517653106U, // VPUNPCKHDQZ128rm + 2517653106U, // VPUNPCKHDQZ128rmb + 49305202U, // VPUNPCKHDQZ128rmbk + 2532333170U, // VPUNPCKHDQZ128rmbkz + 49305202U, // VPUNPCKHDQZ128rmk + 2532333170U, // VPUNPCKHDQZ128rmkz + 2517653106U, // VPUNPCKHDQZ128rr + 49305202U, // VPUNPCKHDQZ128rrk + 2532333170U, // VPUNPCKHDQZ128rrkz + 2517653106U, // VPUNPCKHDQZ256rm + 2517653106U, // VPUNPCKHDQZ256rmb + 49305202U, // VPUNPCKHDQZ256rmbk + 2532333170U, // VPUNPCKHDQZ256rmbkz + 49305202U, // VPUNPCKHDQZ256rmk + 2532333170U, // VPUNPCKHDQZ256rmkz + 2517653106U, // VPUNPCKHDQZ256rr + 49305202U, // VPUNPCKHDQZ256rrk + 2532333170U, // VPUNPCKHDQZ256rrkz + 2517653106U, // VPUNPCKHDQZrm + 2517653106U, // VPUNPCKHDQZrmb + 49305202U, // VPUNPCKHDQZrmbk + 2532333170U, // VPUNPCKHDQZrmbkz + 49305202U, // VPUNPCKHDQZrmk + 2532333170U, // VPUNPCKHDQZrmkz + 2517653106U, // VPUNPCKHDQZrr + 49305202U, // VPUNPCKHDQZrrk + 2532333170U, // VPUNPCKHDQZrrkz + 2517653106U, // VPUNPCKHDQrm + 2517653106U, // VPUNPCKHDQrr + 2517653202U, // VPUNPCKHQDQYrm + 2517653202U, // VPUNPCKHQDQYrr + 2517653202U, // VPUNPCKHQDQZ128rm + 2517653202U, // VPUNPCKHQDQZ128rmb + 49305298U, // VPUNPCKHQDQZ128rmbk + 2532333266U, // VPUNPCKHQDQZ128rmbkz + 49305298U, // VPUNPCKHQDQZ128rmk + 2532333266U, // VPUNPCKHQDQZ128rmkz + 2517653202U, // VPUNPCKHQDQZ128rr + 49305298U, // VPUNPCKHQDQZ128rrk + 2532333266U, // VPUNPCKHQDQZ128rrkz + 2517653202U, // VPUNPCKHQDQZ256rm + 2517653202U, // VPUNPCKHQDQZ256rmb + 49305298U, // VPUNPCKHQDQZ256rmbk + 2532333266U, // VPUNPCKHQDQZ256rmbkz + 49305298U, // VPUNPCKHQDQZ256rmk + 2532333266U, // VPUNPCKHQDQZ256rmkz + 2517653202U, // VPUNPCKHQDQZ256rr + 49305298U, // VPUNPCKHQDQZ256rrk + 2532333266U, // VPUNPCKHQDQZ256rrkz + 2517653202U, // VPUNPCKHQDQZrm + 2517653202U, // VPUNPCKHQDQZrmb + 49305298U, // VPUNPCKHQDQZrmbk + 2532333266U, // VPUNPCKHQDQZrmbkz + 49305298U, // VPUNPCKHQDQZrmk + 2532333266U, // VPUNPCKHQDQZrmkz + 2517653202U, // VPUNPCKHQDQZrr + 49305298U, // VPUNPCKHQDQZrrk + 2532333266U, // VPUNPCKHQDQZrrkz + 2517653202U, // VPUNPCKHQDQrm + 2517653202U, // VPUNPCKHQDQrr + 2517651622U, // VPUNPCKHWDYrm + 2517651622U, // VPUNPCKHWDYrr + 2517651622U, // VPUNPCKHWDZ128rm + 49303718U, // VPUNPCKHWDZ128rmk + 2532331686U, // VPUNPCKHWDZ128rmkz + 2517651622U, // VPUNPCKHWDZ128rr + 49303718U, // VPUNPCKHWDZ128rrk + 2532331686U, // VPUNPCKHWDZ128rrkz + 2517651622U, // VPUNPCKHWDZ256rm + 49303718U, // VPUNPCKHWDZ256rmk + 2532331686U, // VPUNPCKHWDZ256rmkz + 2517651622U, // VPUNPCKHWDZ256rr + 49303718U, // VPUNPCKHWDZ256rrk + 2532331686U, // VPUNPCKHWDZ256rrkz + 2517651622U, // VPUNPCKHWDZrm + 49303718U, // VPUNPCKHWDZrmk + 2532331686U, // VPUNPCKHWDZrmkz + 2517651622U, // VPUNPCKHWDZrr + 49303718U, // VPUNPCKHWDZrrk + 2532331686U, // VPUNPCKHWDZrrkz + 2517651622U, // VPUNPCKHWDrm + 2517651622U, // VPUNPCKHWDrr + 2517656475U, // VPUNPCKLBWYrm + 2517656475U, // VPUNPCKLBWYrr + 2517656475U, // VPUNPCKLBWZ128rm + 49308571U, // VPUNPCKLBWZ128rmk + 2532336539U, // VPUNPCKLBWZ128rmkz + 2517656475U, // VPUNPCKLBWZ128rr + 49308571U, // VPUNPCKLBWZ128rrk + 2532336539U, // VPUNPCKLBWZ128rrkz + 2517656475U, // VPUNPCKLBWZ256rm + 49308571U, // VPUNPCKLBWZ256rmk + 2532336539U, // VPUNPCKLBWZ256rmkz + 2517656475U, // VPUNPCKLBWZ256rr + 49308571U, // VPUNPCKLBWZ256rrk + 2532336539U, // VPUNPCKLBWZ256rrkz + 2517656475U, // VPUNPCKLBWZrm + 49308571U, // VPUNPCKLBWZrmk + 2532336539U, // VPUNPCKLBWZrmkz + 2517656475U, // VPUNPCKLBWZrr + 49308571U, // VPUNPCKLBWZrrk + 2532336539U, // VPUNPCKLBWZrrkz + 2517656475U, // VPUNPCKLBWrm + 2517656475U, // VPUNPCKLBWrr + 2517653137U, // VPUNPCKLDQYrm + 2517653137U, // VPUNPCKLDQYrr + 2517653137U, // VPUNPCKLDQZ128rm + 2517653137U, // VPUNPCKLDQZ128rmb + 49305233U, // VPUNPCKLDQZ128rmbk + 2532333201U, // VPUNPCKLDQZ128rmbkz + 49305233U, // VPUNPCKLDQZ128rmk + 2532333201U, // VPUNPCKLDQZ128rmkz + 2517653137U, // VPUNPCKLDQZ128rr + 49305233U, // VPUNPCKLDQZ128rrk + 2532333201U, // VPUNPCKLDQZ128rrkz + 2517653137U, // VPUNPCKLDQZ256rm + 2517653137U, // VPUNPCKLDQZ256rmb + 49305233U, // VPUNPCKLDQZ256rmbk + 2532333201U, // VPUNPCKLDQZ256rmbkz + 49305233U, // VPUNPCKLDQZ256rmk + 2532333201U, // VPUNPCKLDQZ256rmkz + 2517653137U, // VPUNPCKLDQZ256rr + 49305233U, // VPUNPCKLDQZ256rrk + 2532333201U, // VPUNPCKLDQZ256rrkz + 2517653137U, // VPUNPCKLDQZrm + 2517653137U, // VPUNPCKLDQZrmb + 49305233U, // VPUNPCKLDQZrmbk + 2532333201U, // VPUNPCKLDQZrmbkz + 49305233U, // VPUNPCKLDQZrmk + 2532333201U, // VPUNPCKLDQZrmkz + 2517653137U, // VPUNPCKLDQZrr + 49305233U, // VPUNPCKLDQZrrk + 2532333201U, // VPUNPCKLDQZrrkz + 2517653137U, // VPUNPCKLDQrm + 2517653137U, // VPUNPCKLDQrr + 2517653215U, // VPUNPCKLQDQYrm + 2517653215U, // VPUNPCKLQDQYrr + 2517653215U, // VPUNPCKLQDQZ128rm + 2517653215U, // VPUNPCKLQDQZ128rmb + 49305311U, // VPUNPCKLQDQZ128rmbk + 2532333279U, // VPUNPCKLQDQZ128rmbkz + 49305311U, // VPUNPCKLQDQZ128rmk + 2532333279U, // VPUNPCKLQDQZ128rmkz + 2517653215U, // VPUNPCKLQDQZ128rr + 49305311U, // VPUNPCKLQDQZ128rrk + 2532333279U, // VPUNPCKLQDQZ128rrkz + 2517653215U, // VPUNPCKLQDQZ256rm + 2517653215U, // VPUNPCKLQDQZ256rmb + 49305311U, // VPUNPCKLQDQZ256rmbk + 2532333279U, // VPUNPCKLQDQZ256rmbkz + 49305311U, // VPUNPCKLQDQZ256rmk + 2532333279U, // VPUNPCKLQDQZ256rmkz + 2517653215U, // VPUNPCKLQDQZ256rr + 49305311U, // VPUNPCKLQDQZ256rrk + 2532333279U, // VPUNPCKLQDQZ256rrkz + 2517653215U, // VPUNPCKLQDQZrm + 2517653215U, // VPUNPCKLQDQZrmb + 49305311U, // VPUNPCKLQDQZrmbk + 2532333279U, // VPUNPCKLQDQZrmbkz + 49305311U, // VPUNPCKLQDQZrmk + 2532333279U, // VPUNPCKLQDQZrmkz + 2517653215U, // VPUNPCKLQDQZrr + 49305311U, // VPUNPCKLQDQZrrk + 2532333279U, // VPUNPCKLQDQZrrkz + 2517653215U, // VPUNPCKLQDQrm + 2517653215U, // VPUNPCKLQDQrr + 2517651644U, // VPUNPCKLWDYrm + 2517651644U, // VPUNPCKLWDYrr + 2517651644U, // VPUNPCKLWDZ128rm + 49303740U, // VPUNPCKLWDZ128rmk + 2532331708U, // VPUNPCKLWDZ128rmkz + 2517651644U, // VPUNPCKLWDZ128rr + 49303740U, // VPUNPCKLWDZ128rrk + 2532331708U, // VPUNPCKLWDZ128rrkz + 2517651644U, // VPUNPCKLWDZ256rm + 49303740U, // VPUNPCKLWDZ256rmk + 2532331708U, // VPUNPCKLWDZ256rmkz + 2517651644U, // VPUNPCKLWDZ256rr + 49303740U, // VPUNPCKLWDZ256rrk + 2532331708U, // VPUNPCKLWDZ256rrkz + 2517651644U, // VPUNPCKLWDZrm + 49303740U, // VPUNPCKLWDZrmk + 2532331708U, // VPUNPCKLWDZrmkz + 2517651644U, // VPUNPCKLWDZrr + 49303740U, // VPUNPCKLWDZrrk + 2532331708U, // VPUNPCKLWDZrrkz + 2517651644U, // VPUNPCKLWDrm + 2517651644U, // VPUNPCKLWDrr + 2517650745U, // VPXORDZ128rm + 2517650745U, // VPXORDZ128rmb + 49302841U, // VPXORDZ128rmbk + 2532330809U, // VPXORDZ128rmbkz + 49302841U, // VPXORDZ128rmk + 2532330809U, // VPXORDZ128rmkz + 2517650745U, // VPXORDZ128rr + 49302841U, // VPXORDZ128rrk + 2532330809U, // VPXORDZ128rrkz + 2517650745U, // VPXORDZ256rm + 2517650745U, // VPXORDZ256rmb + 49302841U, // VPXORDZ256rmbk + 2532330809U, // VPXORDZ256rmbkz + 49302841U, // VPXORDZ256rmk + 2532330809U, // VPXORDZ256rmkz + 2517650745U, // VPXORDZ256rr + 49302841U, // VPXORDZ256rrk + 2532330809U, // VPXORDZ256rrkz + 2517650745U, // VPXORDZrm + 2517650745U, // VPXORDZrmb + 49302841U, // VPXORDZrmbk + 2532330809U, // VPXORDZrmbkz + 49302841U, // VPXORDZrmk + 2532330809U, // VPXORDZrmkz + 2517650745U, // VPXORDZrr + 49302841U, // VPXORDZrrk + 2532330809U, // VPXORDZrrkz + 2517653722U, // VPXORQZ128rm + 2517653722U, // VPXORQZ128rmb + 49305818U, // VPXORQZ128rmbk + 2532333786U, // VPXORQZ128rmbkz + 49305818U, // VPXORQZ128rmk + 2532333786U, // VPXORQZ128rmkz + 2517653722U, // VPXORQZ128rr + 49305818U, // VPXORQZ128rrk + 2532333786U, // VPXORQZ128rrkz + 2517653722U, // VPXORQZ256rm + 2517653722U, // VPXORQZ256rmb + 49305818U, // VPXORQZ256rmbk + 2532333786U, // VPXORQZ256rmbkz + 49305818U, // VPXORQZ256rmk + 2532333786U, // VPXORQZ256rmkz + 2517653722U, // VPXORQZ256rr + 49305818U, // VPXORQZ256rrk + 2532333786U, // VPXORQZ256rrkz + 2517653722U, // VPXORQZrm + 2517653722U, // VPXORQZrmb + 49305818U, // VPXORQZrmbk + 2532333786U, // VPXORQZrmbkz + 49305818U, // VPXORQZrmk + 2532333786U, // VPXORQZrmkz + 2517653722U, // VPXORQZrr + 49305818U, // VPXORQZrrk + 2532333786U, // VPXORQZrrkz + 2517654229U, // VPXORYrm + 2517654229U, // VPXORYrr + 2517654229U, // VPXORrm + 2517654229U, // VPXORrr + 2517650262U, // VRANGEPDZ128rmbi + 49302358U, // VRANGEPDZ128rmbik + 2532330326U, // VRANGEPDZ128rmbikz + 2517650262U, // VRANGEPDZ128rmi + 49302358U, // VRANGEPDZ128rmik + 2532330326U, // VRANGEPDZ128rmikz + 2517650262U, // VRANGEPDZ128rri + 49302358U, // VRANGEPDZ128rrik + 2532330326U, // VRANGEPDZ128rrikz + 2517650262U, // VRANGEPDZ256rmbi + 49302358U, // VRANGEPDZ256rmbik + 2532330326U, // VRANGEPDZ256rmbikz + 2517650262U, // VRANGEPDZ256rmi + 49302358U, // VRANGEPDZ256rmik + 2532330326U, // VRANGEPDZ256rmikz + 2517650262U, // VRANGEPDZ256rri + 49302358U, // VRANGEPDZ256rrik + 2532330326U, // VRANGEPDZ256rrikz + 2517650262U, // VRANGEPDZrmbi + 49302358U, // VRANGEPDZrmbik + 2532330326U, // VRANGEPDZrmbikz + 2517650262U, // VRANGEPDZrmi + 49302358U, // VRANGEPDZrmik + 2532330326U, // VRANGEPDZrmikz + 2517650262U, // VRANGEPDZrri + 2517650262U, // VRANGEPDZrrib + 49302358U, // VRANGEPDZrribk + 2532330326U, // VRANGEPDZrribkz + 49302358U, // VRANGEPDZrrik + 2532330326U, // VRANGEPDZrrikz + 2517655061U, // VRANGEPSZ128rmbi + 49307157U, // VRANGEPSZ128rmbik + 2532335125U, // VRANGEPSZ128rmbikz + 2517655061U, // VRANGEPSZ128rmi + 49307157U, // VRANGEPSZ128rmik + 2532335125U, // VRANGEPSZ128rmikz + 2517655061U, // VRANGEPSZ128rri + 49307157U, // VRANGEPSZ128rrik + 2532335125U, // VRANGEPSZ128rrikz + 2517655061U, // VRANGEPSZ256rmbi + 49307157U, // VRANGEPSZ256rmbik + 2532335125U, // VRANGEPSZ256rmbikz + 2517655061U, // VRANGEPSZ256rmi + 49307157U, // VRANGEPSZ256rmik + 2532335125U, // VRANGEPSZ256rmikz + 2517655061U, // VRANGEPSZ256rri + 49307157U, // VRANGEPSZ256rrik + 2532335125U, // VRANGEPSZ256rrikz + 2517655061U, // VRANGEPSZrmbi + 49307157U, // VRANGEPSZrmbik + 2532335125U, // VRANGEPSZrmbikz + 2517655061U, // VRANGEPSZrmi + 49307157U, // VRANGEPSZrmik + 2532335125U, // VRANGEPSZrmikz + 2517655061U, // VRANGEPSZrri + 2517655061U, // VRANGEPSZrrib + 49307157U, // VRANGEPSZrribk + 2532335125U, // VRANGEPSZrribkz + 49307157U, // VRANGEPSZrrik + 2532335125U, // VRANGEPSZrrikz + 2517651108U, // VRANGESDZrmi + 49303204U, // VRANGESDZrmik + 2532331172U, // VRANGESDZrmikz + 2517651108U, // VRANGESDZrri + 2517651108U, // VRANGESDZrrib + 49303204U, // VRANGESDZrribk + 2532331172U, // VRANGESDZrribkz + 49303204U, // VRANGESDZrrik + 2532331172U, // VRANGESDZrrikz + 2517655824U, // VRANGESSZrmi + 49307920U, // VRANGESSZrmik + 2532335888U, // VRANGESSZrmikz + 2517655824U, // VRANGESSZrri + 2517655824U, // VRANGESSZrrib + 49307920U, // VRANGESSZrribk + 2532335888U, // VRANGESSZrribkz + 49307920U, // VRANGESSZrrik + 2532335888U, // VRANGESSZrrikz + 672156253U, // VRCP14PDZ128m + 605047389U, // VRCP14PDZ128mb + 49302109U, // VRCP14PDZ128mbk + 2532330077U, // VRCP14PDZ128mbkz + 49302109U, // VRCP14PDZ128mk + 2532330077U, // VRCP14PDZ128mkz + 370166365U, // VRCP14PDZ128r + 49302109U, // VRCP14PDZ128rk + 2532330077U, // VRCP14PDZ128rkz + 1007700573U, // VRCP14PDZ256m + 2752531037U, // VRCP14PDZ256mb + 49302109U, // VRCP14PDZ256mbk + 2532330077U, // VRCP14PDZ256mbkz + 49302109U, // VRCP14PDZ256mk + 2532330077U, // VRCP14PDZ256mkz + 370166365U, // VRCP14PDZ256r + 49302109U, // VRCP14PDZ256rk + 2532330077U, // VRCP14PDZ256rkz + 1108363869U, // VRCP14PDZm + 605047389U, // VRCP14PDZmb + 49302109U, // VRCP14PDZmbk + 2532330077U, // VRCP14PDZmbkz + 49302109U, // VRCP14PDZmk + 2532330077U, // VRCP14PDZmkz + 370166365U, // VRCP14PDZr + 49302109U, // VRCP14PDZrk + 2532330077U, // VRCP14PDZrkz + 672161037U, // VRCP14PSZ128m + 2786090253U, // VRCP14PSZ128mb + 49306893U, // VRCP14PSZ128mbk + 2532334861U, // VRCP14PSZ128mbkz + 49306893U, // VRCP14PSZ128mk + 2532334861U, // VRCP14PSZ128mkz + 370171149U, // VRCP14PSZ128r + 49306893U, // VRCP14PSZ128rk + 2532334861U, // VRCP14PSZ128rkz + 1007705357U, // VRCP14PSZ256m + 638606605U, // VRCP14PSZ256mb + 49306893U, // VRCP14PSZ256mbk + 2532334861U, // VRCP14PSZ256mbkz + 49306893U, // VRCP14PSZ256mk + 2532334861U, // VRCP14PSZ256mkz + 370171149U, // VRCP14PSZ256r + 49306893U, // VRCP14PSZ256rk + 2532334861U, // VRCP14PSZ256rkz + 1108368653U, // VRCP14PSZm + 2786090253U, // VRCP14PSZmb + 49306893U, // VRCP14PSZmbk + 2532334861U, // VRCP14PSZmbkz + 49306893U, // VRCP14PSZmk + 2532334861U, // VRCP14PSZmkz + 370171149U, // VRCP14PSZr + 49306893U, // VRCP14PSZrk + 2532334861U, // VRCP14PSZrkz + 2517650977U, // VRCP14SDZrm + 49303073U, // VRCP14SDZrmk + 2532331041U, // VRCP14SDZrmkz + 2517650977U, // VRCP14SDZrr + 49303073U, // VRCP14SDZrrk + 2532331041U, // VRCP14SDZrrkz + 2517655678U, // VRCP14SSZrm + 49307774U, // VRCP14SSZrmk + 2532335742U, // VRCP14SSZrmkz + 2517655678U, // VRCP14SSZrr + 49307774U, // VRCP14SSZrrk + 2532335742U, // VRCP14SSZrrkz + 1108363891U, // VRCP28PDZm + 605047411U, // VRCP28PDZmb + 49302131U, // VRCP28PDZmbk + 2532330099U, // VRCP28PDZmbkz + 49302131U, // VRCP28PDZmk + 2532330099U, // VRCP28PDZmkz + 370166387U, // VRCP28PDZr + 2517650035U, // VRCP28PDZrb + 49302131U, // VRCP28PDZrbk + 2532330099U, // VRCP28PDZrbkz + 49302131U, // VRCP28PDZrk + 2532330099U, // VRCP28PDZrkz + 1108368675U, // VRCP28PSZm + 2786090275U, // VRCP28PSZmb + 49306915U, // VRCP28PSZmbk + 2532334883U, // VRCP28PSZmbkz + 49306915U, // VRCP28PSZmk + 2532334883U, // VRCP28PSZmkz + 370171171U, // VRCP28PSZr + 2517654819U, // VRCP28PSZrb + 49306915U, // VRCP28PSZrbk + 2532334883U, // VRCP28PSZrbkz + 49306915U, // VRCP28PSZrk + 2532334883U, // VRCP28PSZrkz + 2517650999U, // VRCP28SDZm + 49303095U, // VRCP28SDZmk + 2532331063U, // VRCP28SDZmkz + 2517650999U, // VRCP28SDZr + 2517650999U, // VRCP28SDZrb + 49303095U, // VRCP28SDZrbk + 2532331063U, // VRCP28SDZrbkz + 49303095U, // VRCP28SDZrk + 2532331063U, // VRCP28SDZrkz + 2517655700U, // VRCP28SSZm + 49307796U, // VRCP28SSZmk + 2532335764U, // VRCP28SSZmkz + 2517655700U, // VRCP28SSZr + 2517655700U, // VRCP28SSZrb + 49307796U, // VRCP28SSZrbk + 2532335764U, // VRCP28SSZrbkz + 49307796U, // VRCP28SSZrk + 2532335764U, // VRCP28SSZrkz + 1007705804U, // VRCPPSYm + 370171596U, // VRCPPSYr + 672161484U, // VRCPPSm + 370171596U, // VRCPPSr + 2517655906U, // VRCPSSm + 2517655906U, // VRCPSSm_Int + 2517655906U, // VRCPSSr + 2517655906U, // VRCPSSr_Int + 2752531275U, // VREDUCEPDZ128rmbi + 49302347U, // VREDUCEPDZ128rmbik + 2532330315U, // VREDUCEPDZ128rmbikz + 2819640139U, // VREDUCEPDZ128rmi + 49302347U, // VREDUCEPDZ128rmik + 2532330315U, // VREDUCEPDZ128rmikz + 2517650251U, // VREDUCEPDZ128rri + 49302347U, // VREDUCEPDZ128rrik + 2532330315U, // VREDUCEPDZ128rrikz + 605047627U, // VREDUCEPDZ256rmbi + 49302347U, // VREDUCEPDZ256rmbik + 2532330315U, // VREDUCEPDZ256rmbikz + 3155184459U, // VREDUCEPDZ256rmi + 49302347U, // VREDUCEPDZ256rmik + 2532330315U, // VREDUCEPDZ256rmikz + 2517650251U, // VREDUCEPDZ256rri + 49302347U, // VREDUCEPDZ256rrik + 2532330315U, // VREDUCEPDZ256rrikz + 2752531275U, // VREDUCEPDZrmbi + 49302347U, // VREDUCEPDZrmbik + 2532330315U, // VREDUCEPDZrmbikz + 3255847755U, // VREDUCEPDZrmi + 49302347U, // VREDUCEPDZrmik + 2532330315U, // VREDUCEPDZrmikz + 2517650251U, // VREDUCEPDZrri + 370166603U, // VREDUCEPDZrrib + 49302347U, // VREDUCEPDZrribk + 2532330315U, // VREDUCEPDZrribkz + 49302347U, // VREDUCEPDZrrik + 2532330315U, // VREDUCEPDZrrikz + 638606858U, // VREDUCEPSZ128rmbi + 49307146U, // VREDUCEPSZ128rmbik + 2532335114U, // VREDUCEPSZ128rmbikz + 2819644938U, // VREDUCEPSZ128rmi + 49307146U, // VREDUCEPSZ128rmik + 2532335114U, // VREDUCEPSZ128rmikz + 2517655050U, // VREDUCEPSZ128rri + 49307146U, // VREDUCEPSZ128rrik + 2532335114U, // VREDUCEPSZ128rrikz + 2786090506U, // VREDUCEPSZ256rmbi + 49307146U, // VREDUCEPSZ256rmbik + 2532335114U, // VREDUCEPSZ256rmbikz + 3155189258U, // VREDUCEPSZ256rmi + 49307146U, // VREDUCEPSZ256rmik + 2532335114U, // VREDUCEPSZ256rmikz + 2517655050U, // VREDUCEPSZ256rri + 49307146U, // VREDUCEPSZ256rrik + 2532335114U, // VREDUCEPSZ256rrikz + 638606858U, // VREDUCEPSZrmbi + 49307146U, // VREDUCEPSZrmbik + 2532335114U, // VREDUCEPSZrmbikz + 3255852554U, // VREDUCEPSZrmi + 49307146U, // VREDUCEPSZrmik + 2532335114U, // VREDUCEPSZrmikz + 2517655050U, // VREDUCEPSZrri + 370171402U, // VREDUCEPSZrrib + 49307146U, // VREDUCEPSZrribk + 2532335114U, // VREDUCEPSZrribkz + 49307146U, // VREDUCEPSZrrik + 2532335114U, // VREDUCEPSZrrikz + 2517651097U, // VREDUCESDZrmi + 49303193U, // VREDUCESDZrmik + 2532331161U, // VREDUCESDZrmikz + 2517651097U, // VREDUCESDZrri + 2517651097U, // VREDUCESDZrrib + 49303193U, // VREDUCESDZrribk + 2532331161U, // VREDUCESDZrribkz + 49303193U, // VREDUCESDZrrik + 2532331161U, // VREDUCESDZrrikz + 2517655813U, // VREDUCESSZrmi + 49307909U, // VREDUCESSZrmik + 2532335877U, // VREDUCESSZrmikz + 2517655813U, // VREDUCESSZrri + 2517655813U, // VREDUCESSZrrib + 49307909U, // VREDUCESSZrribk + 2532335877U, // VREDUCESSZrribkz + 49307909U, // VREDUCESSZrrik + 2532335877U, // VREDUCESSZrrikz + 2752531296U, // VRNDSCALEPDZ128rmbi + 49302368U, // VRNDSCALEPDZ128rmbik + 2532330336U, // VRNDSCALEPDZ128rmbikz + 2819640160U, // VRNDSCALEPDZ128rmi + 49302368U, // VRNDSCALEPDZ128rmik + 2532330336U, // VRNDSCALEPDZ128rmikz + 2517650272U, // VRNDSCALEPDZ128rri + 49302368U, // VRNDSCALEPDZ128rrik + 2532330336U, // VRNDSCALEPDZ128rrikz + 605047648U, // VRNDSCALEPDZ256rmbi + 49302368U, // VRNDSCALEPDZ256rmbik + 2532330336U, // VRNDSCALEPDZ256rmbikz + 3155184480U, // VRNDSCALEPDZ256rmi + 49302368U, // VRNDSCALEPDZ256rmik + 2532330336U, // VRNDSCALEPDZ256rmikz + 2517650272U, // VRNDSCALEPDZ256rri + 49302368U, // VRNDSCALEPDZ256rrik + 2532330336U, // VRNDSCALEPDZ256rrikz + 2752531296U, // VRNDSCALEPDZrmbi + 49302368U, // VRNDSCALEPDZrmbik + 2532330336U, // VRNDSCALEPDZrmbikz + 3255847776U, // VRNDSCALEPDZrmi + 49302368U, // VRNDSCALEPDZrmik + 2532330336U, // VRNDSCALEPDZrmikz + 2517650272U, // VRNDSCALEPDZrri + 370166624U, // VRNDSCALEPDZrrib + 49302368U, // VRNDSCALEPDZrribk + 2532330336U, // VRNDSCALEPDZrribkz + 49302368U, // VRNDSCALEPDZrrik + 2532330336U, // VRNDSCALEPDZrrikz + 638606879U, // VRNDSCALEPSZ128rmbi + 49307167U, // VRNDSCALEPSZ128rmbik + 2532335135U, // VRNDSCALEPSZ128rmbikz + 2819644959U, // VRNDSCALEPSZ128rmi + 49307167U, // VRNDSCALEPSZ128rmik + 2532335135U, // VRNDSCALEPSZ128rmikz + 2517655071U, // VRNDSCALEPSZ128rri + 49307167U, // VRNDSCALEPSZ128rrik + 2532335135U, // VRNDSCALEPSZ128rrikz + 2786090527U, // VRNDSCALEPSZ256rmbi + 49307167U, // VRNDSCALEPSZ256rmbik + 2532335135U, // VRNDSCALEPSZ256rmbikz + 3155189279U, // VRNDSCALEPSZ256rmi + 49307167U, // VRNDSCALEPSZ256rmik + 2532335135U, // VRNDSCALEPSZ256rmikz + 2517655071U, // VRNDSCALEPSZ256rri + 49307167U, // VRNDSCALEPSZ256rrik + 2532335135U, // VRNDSCALEPSZ256rrikz + 638606879U, // VRNDSCALEPSZrmbi + 49307167U, // VRNDSCALEPSZrmbik + 2532335135U, // VRNDSCALEPSZrmbikz + 3255852575U, // VRNDSCALEPSZrmi + 49307167U, // VRNDSCALEPSZrmik + 2532335135U, // VRNDSCALEPSZrmikz + 2517655071U, // VRNDSCALEPSZrri + 370171423U, // VRNDSCALEPSZrrib + 49307167U, // VRNDSCALEPSZrribk + 2532335135U, // VRNDSCALEPSZrribkz + 49307167U, // VRNDSCALEPSZrrik + 2532335135U, // VRNDSCALEPSZrrikz + 2517651118U, // VRNDSCALESDZm + 2517651118U, // VRNDSCALESDZm_Int + 49303214U, // VRNDSCALESDZm_Intk + 2532331182U, // VRNDSCALESDZm_Intkz + 2517651118U, // VRNDSCALESDZr + 2517651118U, // VRNDSCALESDZr_Int + 49303214U, // VRNDSCALESDZr_Intk + 2532331182U, // VRNDSCALESDZr_Intkz + 2517651118U, // VRNDSCALESDZrb_Int + 49303214U, // VRNDSCALESDZrb_Intk + 2532331182U, // VRNDSCALESDZrb_Intkz + 2517655834U, // VRNDSCALESSZm + 2517655834U, // VRNDSCALESSZm_Int + 49307930U, // VRNDSCALESSZm_Intk + 2532335898U, // VRNDSCALESSZm_Intkz + 2517655834U, // VRNDSCALESSZr + 2517655834U, // VRNDSCALESSZr_Int + 49307930U, // VRNDSCALESSZr_Intk + 2532335898U, // VRNDSCALESSZr_Intkz + 2517655834U, // VRNDSCALESSZrb_Int + 49307930U, // VRNDSCALESSZrb_Intk + 2532335898U, // VRNDSCALESSZrb_Intkz + 3155184424U, // VROUNDPDYm + 2517650216U, // VROUNDPDYr + 2819640104U, // VROUNDPDm + 2517650216U, // VROUNDPDr + 3155189223U, // VROUNDPSYm + 2517655015U, // VROUNDPSYr + 2819644903U, // VROUNDPSm + 2517655015U, // VROUNDPSr + 2517651087U, // VROUNDSDm + 2517651087U, // VROUNDSDm_Int + 2517651087U, // VROUNDSDr + 2517651087U, // VROUNDSDr_Int + 2517655803U, // VROUNDSSm + 2517655803U, // VROUNDSSm_Int + 2517655803U, // VROUNDSSr + 2517655803U, // VROUNDSSr_Int + 672156263U, // VRSQRT14PDZ128m + 605047399U, // VRSQRT14PDZ128mb + 49302119U, // VRSQRT14PDZ128mbk + 2532330087U, // VRSQRT14PDZ128mbkz + 49302119U, // VRSQRT14PDZ128mk + 2532330087U, // VRSQRT14PDZ128mkz + 370166375U, // VRSQRT14PDZ128r + 49302119U, // VRSQRT14PDZ128rk + 2532330087U, // VRSQRT14PDZ128rkz + 1007700583U, // VRSQRT14PDZ256m + 2752531047U, // VRSQRT14PDZ256mb + 49302119U, // VRSQRT14PDZ256mbk + 2532330087U, // VRSQRT14PDZ256mbkz + 49302119U, // VRSQRT14PDZ256mk + 2532330087U, // VRSQRT14PDZ256mkz + 370166375U, // VRSQRT14PDZ256r + 49302119U, // VRSQRT14PDZ256rk + 2532330087U, // VRSQRT14PDZ256rkz + 1108363879U, // VRSQRT14PDZm + 605047399U, // VRSQRT14PDZmb + 49302119U, // VRSQRT14PDZmbk + 2532330087U, // VRSQRT14PDZmbkz + 49302119U, // VRSQRT14PDZmk + 2532330087U, // VRSQRT14PDZmkz + 370166375U, // VRSQRT14PDZr + 49302119U, // VRSQRT14PDZrk + 2532330087U, // VRSQRT14PDZrkz + 672161047U, // VRSQRT14PSZ128m + 2786090263U, // VRSQRT14PSZ128mb + 49306903U, // VRSQRT14PSZ128mbk + 2532334871U, // VRSQRT14PSZ128mbkz + 49306903U, // VRSQRT14PSZ128mk + 2532334871U, // VRSQRT14PSZ128mkz + 370171159U, // VRSQRT14PSZ128r + 49306903U, // VRSQRT14PSZ128rk + 2532334871U, // VRSQRT14PSZ128rkz + 1007705367U, // VRSQRT14PSZ256m + 638606615U, // VRSQRT14PSZ256mb + 49306903U, // VRSQRT14PSZ256mbk + 2532334871U, // VRSQRT14PSZ256mbkz + 49306903U, // VRSQRT14PSZ256mk + 2532334871U, // VRSQRT14PSZ256mkz + 370171159U, // VRSQRT14PSZ256r + 49306903U, // VRSQRT14PSZ256rk + 2532334871U, // VRSQRT14PSZ256rkz + 1108368663U, // VRSQRT14PSZm + 2786090263U, // VRSQRT14PSZmb + 49306903U, // VRSQRT14PSZmbk + 2532334871U, // VRSQRT14PSZmbkz + 49306903U, // VRSQRT14PSZmk + 2532334871U, // VRSQRT14PSZmkz + 370171159U, // VRSQRT14PSZr + 49306903U, // VRSQRT14PSZrk + 2532334871U, // VRSQRT14PSZrkz + 2517650987U, // VRSQRT14SDZrm + 49303083U, // VRSQRT14SDZrmk + 2532331051U, // VRSQRT14SDZrmkz + 2517650987U, // VRSQRT14SDZrr + 49303083U, // VRSQRT14SDZrrk + 2532331051U, // VRSQRT14SDZrrkz + 2517655688U, // VRSQRT14SSZrm + 49307784U, // VRSQRT14SSZrmk + 2532335752U, // VRSQRT14SSZrmkz + 2517655688U, // VRSQRT14SSZrr + 49307784U, // VRSQRT14SSZrrk + 2532335752U, // VRSQRT14SSZrrkz + 1108363901U, // VRSQRT28PDZm + 605047421U, // VRSQRT28PDZmb + 49302141U, // VRSQRT28PDZmbk + 2532330109U, // VRSQRT28PDZmbkz + 49302141U, // VRSQRT28PDZmk + 2532330109U, // VRSQRT28PDZmkz + 370166397U, // VRSQRT28PDZr + 2517650045U, // VRSQRT28PDZrb + 49302141U, // VRSQRT28PDZrbk + 2532330109U, // VRSQRT28PDZrbkz + 49302141U, // VRSQRT28PDZrk + 2532330109U, // VRSQRT28PDZrkz + 1108368685U, // VRSQRT28PSZm + 2786090285U, // VRSQRT28PSZmb + 49306925U, // VRSQRT28PSZmbk + 2532334893U, // VRSQRT28PSZmbkz + 49306925U, // VRSQRT28PSZmk + 2532334893U, // VRSQRT28PSZmkz + 370171181U, // VRSQRT28PSZr + 2517654829U, // VRSQRT28PSZrb + 49306925U, // VRSQRT28PSZrbk + 2532334893U, // VRSQRT28PSZrbkz + 49306925U, // VRSQRT28PSZrk + 2532334893U, // VRSQRT28PSZrkz + 2517651009U, // VRSQRT28SDZm + 49303105U, // VRSQRT28SDZmk + 2532331073U, // VRSQRT28SDZmkz + 2517651009U, // VRSQRT28SDZr + 2517651009U, // VRSQRT28SDZrb + 49303105U, // VRSQRT28SDZrbk + 2532331073U, // VRSQRT28SDZrbkz + 49303105U, // VRSQRT28SDZrk + 2532331073U, // VRSQRT28SDZrkz + 2517655710U, // VRSQRT28SSZm + 49307806U, // VRSQRT28SSZmk + 2532335774U, // VRSQRT28SSZmkz + 2517655710U, // VRSQRT28SSZr + 2517655710U, // VRSQRT28SSZrb + 49307806U, // VRSQRT28SSZrbk + 2532335774U, // VRSQRT28SSZrbkz + 49307806U, // VRSQRT28SSZrk + 2532335774U, // VRSQRT28SSZrkz + 1007705948U, // VRSQRTPSYm + 370171740U, // VRSQRTPSYr + 672161628U, // VRSQRTPSm + 370171740U, // VRSQRTPSr + 2517655966U, // VRSQRTSSm + 2517655966U, // VRSQRTSSm_Int + 2517655966U, // VRSQRTSSr + 2517655966U, // VRSQRTSSr_Int + 2517650285U, // VSCALEFPDZ128rm + 2517650285U, // VSCALEFPDZ128rmb + 49302381U, // VSCALEFPDZ128rmbk + 2532330349U, // VSCALEFPDZ128rmbkz + 49302381U, // VSCALEFPDZ128rmk + 2532330349U, // VSCALEFPDZ128rmkz + 2517650285U, // VSCALEFPDZ128rr + 49302381U, // VSCALEFPDZ128rrk + 2532330349U, // VSCALEFPDZ128rrkz + 2517650285U, // VSCALEFPDZ256rm + 2517650285U, // VSCALEFPDZ256rmb + 49302381U, // VSCALEFPDZ256rmbk + 2532330349U, // VSCALEFPDZ256rmbkz + 49302381U, // VSCALEFPDZ256rmk + 2532330349U, // VSCALEFPDZ256rmkz + 2517650285U, // VSCALEFPDZ256rr + 49302381U, // VSCALEFPDZ256rrk + 2532330349U, // VSCALEFPDZ256rrkz + 2517650285U, // VSCALEFPDZrm + 2517650285U, // VSCALEFPDZrmb + 49302381U, // VSCALEFPDZrmbk + 2532330349U, // VSCALEFPDZrmbkz + 49302381U, // VSCALEFPDZrmk + 2532330349U, // VSCALEFPDZrmkz + 2517650285U, // VSCALEFPDZrr + 2517650285U, // VSCALEFPDZrrb + 49302381U, // VSCALEFPDZrrbk + 2532330349U, // VSCALEFPDZrrbkz + 49302381U, // VSCALEFPDZrrk + 2532330349U, // VSCALEFPDZrrkz + 2517655084U, // VSCALEFPSZ128rm + 2517655084U, // VSCALEFPSZ128rmb + 49307180U, // VSCALEFPSZ128rmbk + 2532335148U, // VSCALEFPSZ128rmbkz + 49307180U, // VSCALEFPSZ128rmk + 2532335148U, // VSCALEFPSZ128rmkz + 2517655084U, // VSCALEFPSZ128rr + 49307180U, // VSCALEFPSZ128rrk + 2532335148U, // VSCALEFPSZ128rrkz + 2517655084U, // VSCALEFPSZ256rm + 2517655084U, // VSCALEFPSZ256rmb + 49307180U, // VSCALEFPSZ256rmbk + 2532335148U, // VSCALEFPSZ256rmbkz + 49307180U, // VSCALEFPSZ256rmk + 2532335148U, // VSCALEFPSZ256rmkz + 2517655084U, // VSCALEFPSZ256rr + 49307180U, // VSCALEFPSZ256rrk + 2532335148U, // VSCALEFPSZ256rrkz + 2517655084U, // VSCALEFPSZrm + 2517655084U, // VSCALEFPSZrmb + 49307180U, // VSCALEFPSZrmbk + 2532335148U, // VSCALEFPSZrmbkz + 49307180U, // VSCALEFPSZrmk + 2532335148U, // VSCALEFPSZrmkz + 2517655084U, // VSCALEFPSZrr + 2517655084U, // VSCALEFPSZrrb + 49307180U, // VSCALEFPSZrrbk + 2532335148U, // VSCALEFPSZrrbkz + 49307180U, // VSCALEFPSZrrk + 2532335148U, // VSCALEFPSZrrkz + 2517651131U, // VSCALEFSDZrm + 49303227U, // VSCALEFSDZrmk + 2532331195U, // VSCALEFSDZrmkz + 2517651131U, // VSCALEFSDZrr + 2517651131U, // VSCALEFSDZrrb_Int + 49303227U, // VSCALEFSDZrrb_Intk + 2532331195U, // VSCALEFSDZrrb_Intkz + 49303227U, // VSCALEFSDZrrk + 2532331195U, // VSCALEFSDZrrkz + 2517655847U, // VSCALEFSSZrm + 49307943U, // VSCALEFSSZrmk + 2532335911U, // VSCALEFSSZrmkz + 2517655847U, // VSCALEFSSZrr + 2517655847U, // VSCALEFSSZrrb_Int + 49307943U, // VSCALEFSSZrrb_Intk + 2532335911U, // VSCALEFSSZrrb_Intkz + 49307943U, // VSCALEFSSZrrk + 2532335911U, // VSCALEFSSZrrkz + 691006U, // VSCATTERDPDZ128mr + 707390U, // VSCATTERDPDZ256mr + 723774U, // VSCATTERDPDZmr + 695805U, // VSCATTERDPSZ128mr + 712189U, // VSCATTERDPSZ256mr + 728573U, // VSCATTERDPSZmr + 822112234U, // VSCATTERPF0DPDm + 822112366U, // VSCATTERPF0DPSm + 822112300U, // VSCATTERPF0QPDm + 1056993456U, // VSCATTERPF0QPSm + 822112267U, // VSCATTERPF1DPDm + 822112399U, // VSCATTERPF1DPSm + 822112333U, // VSCATTERPF1QPDm + 1056993489U, // VSCATTERPF1QPSm + 691239U, // VSCATTERQPDZ128mr + 707623U, // VSCATTERQPDZ256mr + 724007U, // VSCATTERQPDZmr + 745210U, // VSCATTERQPSZ128mr + 696058U, // VSCATTERQPSZ256mr + 712442U, // VSCATTERQPSZmr + 2517647773U, // VSHUFF32X4Z256rmbi + 49299869U, // VSHUFF32X4Z256rmbik + 2532327837U, // VSHUFF32X4Z256rmbikz + 2517647773U, // VSHUFF32X4Z256rmi + 49299869U, // VSHUFF32X4Z256rmik + 2532327837U, // VSHUFF32X4Z256rmikz + 2517647773U, // VSHUFF32X4Z256rri + 49299869U, // VSHUFF32X4Z256rrik + 2532327837U, // VSHUFF32X4Z256rrikz + 2517647773U, // VSHUFF32X4Zrmbi + 49299869U, // VSHUFF32X4Zrmbik + 2532327837U, // VSHUFF32X4Zrmbikz + 2517647773U, // VSHUFF32X4Zrmi + 49299869U, // VSHUFF32X4Zrmik + 2532327837U, // VSHUFF32X4Zrmikz + 2517647773U, // VSHUFF32X4Zrri + 49299869U, // VSHUFF32X4Zrrik + 2532327837U, // VSHUFF32X4Zrrikz + 2517647560U, // VSHUFF64X2Z256rmbi + 49299656U, // VSHUFF64X2Z256rmbik + 2532327624U, // VSHUFF64X2Z256rmbikz + 2517647560U, // VSHUFF64X2Z256rmi + 49299656U, // VSHUFF64X2Z256rmik + 2532327624U, // VSHUFF64X2Z256rmikz + 2517647560U, // VSHUFF64X2Z256rri + 49299656U, // VSHUFF64X2Z256rrik + 2532327624U, // VSHUFF64X2Z256rrikz + 2517647560U, // VSHUFF64X2Zrmbi + 49299656U, // VSHUFF64X2Zrmbik + 2532327624U, // VSHUFF64X2Zrmbikz + 2517647560U, // VSHUFF64X2Zrmi + 49299656U, // VSHUFF64X2Zrmik + 2532327624U, // VSHUFF64X2Zrmikz + 2517647560U, // VSHUFF64X2Zrri + 49299656U, // VSHUFF64X2Zrrik + 2532327624U, // VSHUFF64X2Zrrikz + 2517647831U, // VSHUFI32X4Z256rmbi + 49299927U, // VSHUFI32X4Z256rmbik + 2532327895U, // VSHUFI32X4Z256rmbikz + 2517647831U, // VSHUFI32X4Z256rmi + 49299927U, // VSHUFI32X4Z256rmik + 2532327895U, // VSHUFI32X4Z256rmikz + 2517647831U, // VSHUFI32X4Z256rri + 49299927U, // VSHUFI32X4Z256rrik + 2532327895U, // VSHUFI32X4Z256rrikz + 2517647831U, // VSHUFI32X4Zrmbi + 49299927U, // VSHUFI32X4Zrmbik + 2532327895U, // VSHUFI32X4Zrmbikz + 2517647831U, // VSHUFI32X4Zrmi + 49299927U, // VSHUFI32X4Zrmik + 2532327895U, // VSHUFI32X4Zrmikz + 2517647831U, // VSHUFI32X4Zrri + 49299927U, // VSHUFI32X4Zrrik + 2532327895U, // VSHUFI32X4Zrrikz + 2517647618U, // VSHUFI64X2Z256rmbi + 49299714U, // VSHUFI64X2Z256rmbik + 2532327682U, // VSHUFI64X2Z256rmbikz + 2517647618U, // VSHUFI64X2Z256rmi + 49299714U, // VSHUFI64X2Z256rmik + 2532327682U, // VSHUFI64X2Z256rmikz + 2517647618U, // VSHUFI64X2Z256rri + 49299714U, // VSHUFI64X2Z256rrik + 2532327682U, // VSHUFI64X2Z256rrikz + 2517647618U, // VSHUFI64X2Zrmbi + 49299714U, // VSHUFI64X2Zrmbik + 2532327682U, // VSHUFI64X2Zrmbikz + 2517647618U, // VSHUFI64X2Zrmi + 49299714U, // VSHUFI64X2Zrmik + 2532327682U, // VSHUFI64X2Zrmikz + 2517647618U, // VSHUFI64X2Zrri + 49299714U, // VSHUFI64X2Zrrik + 2532327682U, // VSHUFI64X2Zrrikz + 2517650296U, // VSHUFPDYrmi + 2517650296U, // VSHUFPDYrri + 2517650296U, // VSHUFPDZ128rmbi + 49302392U, // VSHUFPDZ128rmbik + 2532330360U, // VSHUFPDZ128rmbikz + 2517650296U, // VSHUFPDZ128rmi + 49302392U, // VSHUFPDZ128rmik + 2532330360U, // VSHUFPDZ128rmikz + 2517650296U, // VSHUFPDZ128rri + 49302392U, // VSHUFPDZ128rrik + 2532330360U, // VSHUFPDZ128rrikz + 2517650296U, // VSHUFPDZ256rmbi + 49302392U, // VSHUFPDZ256rmbik + 2532330360U, // VSHUFPDZ256rmbikz + 2517650296U, // VSHUFPDZ256rmi + 49302392U, // VSHUFPDZ256rmik + 2532330360U, // VSHUFPDZ256rmikz + 2517650296U, // VSHUFPDZ256rri + 49302392U, // VSHUFPDZ256rrik + 2532330360U, // VSHUFPDZ256rrikz + 2517650296U, // VSHUFPDZrmbi + 49302392U, // VSHUFPDZrmbik + 2532330360U, // VSHUFPDZrmbikz + 2517650296U, // VSHUFPDZrmi + 49302392U, // VSHUFPDZrmik + 2532330360U, // VSHUFPDZrmikz + 2517650296U, // VSHUFPDZrri + 49302392U, // VSHUFPDZrrik + 2532330360U, // VSHUFPDZrrikz + 2517650296U, // VSHUFPDrmi + 2517650296U, // VSHUFPDrri + 2517655095U, // VSHUFPSYrmi + 2517655095U, // VSHUFPSYrri + 2517655095U, // VSHUFPSZ128rmbi + 49307191U, // VSHUFPSZ128rmbik + 2532335159U, // VSHUFPSZ128rmbikz + 2517655095U, // VSHUFPSZ128rmi + 49307191U, // VSHUFPSZ128rmik + 2532335159U, // VSHUFPSZ128rmikz + 2517655095U, // VSHUFPSZ128rri + 49307191U, // VSHUFPSZ128rrik + 2532335159U, // VSHUFPSZ128rrikz + 2517655095U, // VSHUFPSZ256rmbi + 49307191U, // VSHUFPSZ256rmbik + 2532335159U, // VSHUFPSZ256rmbikz + 2517655095U, // VSHUFPSZ256rmi + 49307191U, // VSHUFPSZ256rmik + 2532335159U, // VSHUFPSZ256rmikz + 2517655095U, // VSHUFPSZ256rri + 49307191U, // VSHUFPSZ256rrik + 2532335159U, // VSHUFPSZ256rrikz + 2517655095U, // VSHUFPSZrmbi + 49307191U, // VSHUFPSZrmbik + 2532335159U, // VSHUFPSZrmbikz + 2517655095U, // VSHUFPSZrmi + 49307191U, // VSHUFPSZrmik + 2532335159U, // VSHUFPSZrmikz + 2517655095U, // VSHUFPSZrri + 49307191U, // VSHUFPSZrrik + 2532335159U, // VSHUFPSZrrikz + 2517655095U, // VSHUFPSrmi + 2517655095U, // VSHUFPSrri + 1007701123U, // VSQRTPDYm + 370166915U, // VSQRTPDYr + 672156803U, // VSQRTPDZ128m + 605047939U, // VSQRTPDZ128mb + 49302659U, // VSQRTPDZ128mbk + 2532330627U, // VSQRTPDZ128mbkz + 49302659U, // VSQRTPDZ128mk + 2532330627U, // VSQRTPDZ128mkz + 370166915U, // VSQRTPDZ128r + 49302659U, // VSQRTPDZ128rk + 2532330627U, // VSQRTPDZ128rkz + 1007701123U, // VSQRTPDZ256m + 2752531587U, // VSQRTPDZ256mb + 49302659U, // VSQRTPDZ256mbk + 2532330627U, // VSQRTPDZ256mbkz + 49302659U, // VSQRTPDZ256mk + 2532330627U, // VSQRTPDZ256mkz + 370166915U, // VSQRTPDZ256r + 49302659U, // VSQRTPDZ256rk + 2532330627U, // VSQRTPDZ256rkz + 1108364419U, // VSQRTPDZm + 605047939U, // VSQRTPDZmb + 49302659U, // VSQRTPDZmbk + 2532330627U, // VSQRTPDZmbkz + 49302659U, // VSQRTPDZmk + 2532330627U, // VSQRTPDZmkz + 370166915U, // VSQRTPDZr + 2517650563U, // VSQRTPDZrb + 49302659U, // VSQRTPDZrbk + 2532330627U, // VSQRTPDZrbkz + 49302659U, // VSQRTPDZrk + 2532330627U, // VSQRTPDZrkz + 672156803U, // VSQRTPDm + 370166915U, // VSQRTPDr + 1007705958U, // VSQRTPSYm + 370171750U, // VSQRTPSYr + 672161638U, // VSQRTPSZ128m + 2786090854U, // VSQRTPSZ128mb + 49307494U, // VSQRTPSZ128mbk + 2532335462U, // VSQRTPSZ128mbkz + 49307494U, // VSQRTPSZ128mk + 2532335462U, // VSQRTPSZ128mkz + 370171750U, // VSQRTPSZ128r + 49307494U, // VSQRTPSZ128rk + 2532335462U, // VSQRTPSZ128rkz + 1007705958U, // VSQRTPSZ256m + 638607206U, // VSQRTPSZ256mb + 49307494U, // VSQRTPSZ256mbk + 2532335462U, // VSQRTPSZ256mbkz + 49307494U, // VSQRTPSZ256mk + 2532335462U, // VSQRTPSZ256mkz + 370171750U, // VSQRTPSZ256r + 49307494U, // VSQRTPSZ256rk + 2532335462U, // VSQRTPSZ256rkz + 1108369254U, // VSQRTPSZm + 2786090854U, // VSQRTPSZmb + 49307494U, // VSQRTPSZmbk + 2532335462U, // VSQRTPSZmbkz + 49307494U, // VSQRTPSZmk + 2532335462U, // VSQRTPSZmkz + 370171750U, // VSQRTPSZr + 2517655398U, // VSQRTPSZrb + 49307494U, // VSQRTPSZrbk + 2532335462U, // VSQRTPSZrbkz + 49307494U, // VSQRTPSZrk + 2532335462U, // VSQRTPSZrkz + 672161638U, // VSQRTPSm + 370171750U, // VSQRTPSr + 2517651307U, // VSQRTSDZm + 2517651307U, // VSQRTSDZm_Int + 49303403U, // VSQRTSDZm_Intk + 2532331371U, // VSQRTSDZm_Intkz + 2517651307U, // VSQRTSDZr + 2517651307U, // VSQRTSDZr_Int + 49303403U, // VSQRTSDZr_Intk + 2532331371U, // VSQRTSDZr_Intkz + 2517651307U, // VSQRTSDZrb_Int + 49303403U, // VSQRTSDZrb_Intk + 2532331371U, // VSQRTSDZrb_Intkz + 2517651307U, // VSQRTSDm + 2517651307U, // VSQRTSDm_Int + 2517651307U, // VSQRTSDr + 2517651307U, // VSQRTSDr_Int + 2517655976U, // VSQRTSSZm + 2517655976U, // VSQRTSSZm_Int + 49308072U, // VSQRTSSZm_Intk + 2532336040U, // VSQRTSSZm_Intkz + 2517655976U, // VSQRTSSZr + 2517655976U, // VSQRTSSZr_Int + 49308072U, // VSQRTSSZr_Intk + 2532336040U, // VSQRTSSZr_Intkz + 2517655976U, // VSQRTSSZrb_Int + 49308072U, // VSQRTSSZrb_Intk + 2532336040U, // VSQRTSSZrb_Intkz + 2517655976U, // VSQRTSSm + 2517655976U, // VSQRTSSm_Int + 2517655976U, // VSQRTSSr + 2517655976U, // VSQRTSSr_Int + 72433U, // VSTMXCSR + 2517650128U, // VSUBPDYrm + 2517650128U, // VSUBPDYrr + 2517650128U, // VSUBPDZ128rm + 2517650128U, // VSUBPDZ128rmb + 49302224U, // VSUBPDZ128rmbk + 2532330192U, // VSUBPDZ128rmbkz + 49302224U, // VSUBPDZ128rmk + 2532330192U, // VSUBPDZ128rmkz + 2517650128U, // VSUBPDZ128rr + 49302224U, // VSUBPDZ128rrk + 2532330192U, // VSUBPDZ128rrkz + 2517650128U, // VSUBPDZ256rm + 2517650128U, // VSUBPDZ256rmb + 49302224U, // VSUBPDZ256rmbk + 2532330192U, // VSUBPDZ256rmbkz + 49302224U, // VSUBPDZ256rmk + 2532330192U, // VSUBPDZ256rmkz + 2517650128U, // VSUBPDZ256rr + 49302224U, // VSUBPDZ256rrk + 2532330192U, // VSUBPDZ256rrkz + 2517650128U, // VSUBPDZrm + 2517650128U, // VSUBPDZrmb + 49302224U, // VSUBPDZrmbk + 2532330192U, // VSUBPDZrmbkz + 49302224U, // VSUBPDZrmk + 2532330192U, // VSUBPDZrmkz + 2517650128U, // VSUBPDZrr + 2517650128U, // VSUBPDZrrb + 49302224U, // VSUBPDZrrbk + 2532330192U, // VSUBPDZrrbkz + 49302224U, // VSUBPDZrrk + 2532330192U, // VSUBPDZrrkz + 2517650128U, // VSUBPDrm + 2517650128U, // VSUBPDrr + 2517654904U, // VSUBPSYrm + 2517654904U, // VSUBPSYrr + 2517654904U, // VSUBPSZ128rm + 2517654904U, // VSUBPSZ128rmb + 49307000U, // VSUBPSZ128rmbk + 2532334968U, // VSUBPSZ128rmbkz + 49307000U, // VSUBPSZ128rmk + 2532334968U, // VSUBPSZ128rmkz + 2517654904U, // VSUBPSZ128rr + 49307000U, // VSUBPSZ128rrk + 2532334968U, // VSUBPSZ128rrkz + 2517654904U, // VSUBPSZ256rm + 2517654904U, // VSUBPSZ256rmb + 49307000U, // VSUBPSZ256rmbk + 2532334968U, // VSUBPSZ256rmbkz + 49307000U, // VSUBPSZ256rmk + 2532334968U, // VSUBPSZ256rmkz + 2517654904U, // VSUBPSZ256rr + 49307000U, // VSUBPSZ256rrk + 2532334968U, // VSUBPSZ256rrkz + 2517654904U, // VSUBPSZrm + 2517654904U, // VSUBPSZrmb + 49307000U, // VSUBPSZrmbk + 2532334968U, // VSUBPSZrmbkz + 49307000U, // VSUBPSZrmk + 2532334968U, // VSUBPSZrmkz + 2517654904U, // VSUBPSZrr + 2517654904U, // VSUBPSZrrb + 49307000U, // VSUBPSZrrbk + 2532334968U, // VSUBPSZrrbkz + 49307000U, // VSUBPSZrrk + 2532334968U, // VSUBPSZrrkz + 2517654904U, // VSUBPSrm + 2517654904U, // VSUBPSrr + 2517651050U, // VSUBSDZrm + 2517651050U, // VSUBSDZrm_Int + 49303146U, // VSUBSDZrm_Intk + 2532331114U, // VSUBSDZrm_Intkz + 2517651050U, // VSUBSDZrr + 2517651050U, // VSUBSDZrr_Int + 49303146U, // VSUBSDZrr_Intk + 2532331114U, // VSUBSDZrr_Intkz + 2517651050U, // VSUBSDZrrb_Int + 49303146U, // VSUBSDZrrb_Intk + 2532331114U, // VSUBSDZrrb_Intkz + 2517651050U, // VSUBSDrm + 2517651050U, // VSUBSDrm_Int + 2517651050U, // VSUBSDrr + 2517651050U, // VSUBSDrr_Int + 2517655743U, // VSUBSSZrm + 2517655743U, // VSUBSSZrm_Int + 49307839U, // VSUBSSZrm_Intk + 2532335807U, // VSUBSSZrm_Intkz + 2517655743U, // VSUBSSZrr + 2517655743U, // VSUBSSZrr_Int + 49307839U, // VSUBSSZrr_Intk + 2532335807U, // VSUBSSZrr_Intkz + 2517655743U, // VSUBSSZrrb_Int + 49307839U, // VSUBSSZrrb_Intk + 2532335807U, // VSUBSSZrrb_Intkz + 2517655743U, // VSUBSSrm + 2517655743U, // VSUBSSrm_Int + 2517655743U, // VSUBSSrr + 2517655743U, // VSUBSSrr_Int + 1007701132U, // VTESTPDYrm + 370166924U, // VTESTPDYrr + 672156812U, // VTESTPDrm + 370166924U, // VTESTPDrr + 1007705967U, // VTESTPSYrm + 370171759U, // VTESTPSYrr + 672161647U, // VTESTPSrm + 370171759U, // VTESTPSrr + 605048518U, // VUCOMISDZrm + 605048518U, // VUCOMISDZrm_Int + 370167494U, // VUCOMISDZrr + 370167494U, // VUCOMISDZrr_Int + 2517651142U, // VUCOMISDZrrb + 605048518U, // VUCOMISDrm + 605048518U, // VUCOMISDrm_Int + 370167494U, // VUCOMISDrr + 370167494U, // VUCOMISDrr_Int + 638607666U, // VUCOMISSZrm + 638607666U, // VUCOMISSZrm_Int + 370172210U, // VUCOMISSZrr + 370172210U, // VUCOMISSZrr_Int + 2517655858U, // VUCOMISSZrrb + 638607666U, // VUCOMISSrm + 638607666U, // VUCOMISSrm_Int + 370172210U, // VUCOMISSrr + 370172210U, // VUCOMISSrr_Int + 2517650305U, // VUNPCKHPDYrm + 2517650305U, // VUNPCKHPDYrr + 2517650305U, // VUNPCKHPDZ128rm + 2517650305U, // VUNPCKHPDZ128rmb + 49302401U, // VUNPCKHPDZ128rmbk + 2532330369U, // VUNPCKHPDZ128rmbkz + 49302401U, // VUNPCKHPDZ128rmk + 2532330369U, // VUNPCKHPDZ128rmkz + 2517650305U, // VUNPCKHPDZ128rr + 49302401U, // VUNPCKHPDZ128rrk + 2532330369U, // VUNPCKHPDZ128rrkz + 2517650305U, // VUNPCKHPDZ256rm + 2517650305U, // VUNPCKHPDZ256rmb + 49302401U, // VUNPCKHPDZ256rmbk + 2532330369U, // VUNPCKHPDZ256rmbkz + 49302401U, // VUNPCKHPDZ256rmk + 2532330369U, // VUNPCKHPDZ256rmkz + 2517650305U, // VUNPCKHPDZ256rr + 49302401U, // VUNPCKHPDZ256rrk + 2532330369U, // VUNPCKHPDZ256rrkz + 2517650305U, // VUNPCKHPDZrm + 2517650305U, // VUNPCKHPDZrmb + 49302401U, // VUNPCKHPDZrmbk + 2532330369U, // VUNPCKHPDZrmbkz + 49302401U, // VUNPCKHPDZrmk + 2532330369U, // VUNPCKHPDZrmkz + 2517650305U, // VUNPCKHPDZrr + 49302401U, // VUNPCKHPDZrrk + 2532330369U, // VUNPCKHPDZrrkz + 2517650305U, // VUNPCKHPDrm + 2517650305U, // VUNPCKHPDrr + 2517655104U, // VUNPCKHPSYrm + 2517655104U, // VUNPCKHPSYrr + 2517655104U, // VUNPCKHPSZ128rm + 2517655104U, // VUNPCKHPSZ128rmb + 49307200U, // VUNPCKHPSZ128rmbk + 2532335168U, // VUNPCKHPSZ128rmbkz + 49307200U, // VUNPCKHPSZ128rmk + 2532335168U, // VUNPCKHPSZ128rmkz + 2517655104U, // VUNPCKHPSZ128rr + 49307200U, // VUNPCKHPSZ128rrk + 2532335168U, // VUNPCKHPSZ128rrkz + 2517655104U, // VUNPCKHPSZ256rm + 2517655104U, // VUNPCKHPSZ256rmb + 49307200U, // VUNPCKHPSZ256rmbk + 2532335168U, // VUNPCKHPSZ256rmbkz + 49307200U, // VUNPCKHPSZ256rmk + 2532335168U, // VUNPCKHPSZ256rmkz + 2517655104U, // VUNPCKHPSZ256rr + 49307200U, // VUNPCKHPSZ256rrk + 2532335168U, // VUNPCKHPSZ256rrkz + 2517655104U, // VUNPCKHPSZrm + 2517655104U, // VUNPCKHPSZrmb + 49307200U, // VUNPCKHPSZrmbk + 2532335168U, // VUNPCKHPSZrmbkz + 49307200U, // VUNPCKHPSZrmk + 2532335168U, // VUNPCKHPSZrmkz + 2517655104U, // VUNPCKHPSZrr + 49307200U, // VUNPCKHPSZrrk + 2532335168U, // VUNPCKHPSZrrkz + 2517655104U, // VUNPCKHPSrm + 2517655104U, // VUNPCKHPSrr + 2517650347U, // VUNPCKLPDYrm + 2517650347U, // VUNPCKLPDYrr + 2517650347U, // VUNPCKLPDZ128rm + 2517650347U, // VUNPCKLPDZ128rmb + 49302443U, // VUNPCKLPDZ128rmbk + 2532330411U, // VUNPCKLPDZ128rmbkz + 49302443U, // VUNPCKLPDZ128rmk + 2532330411U, // VUNPCKLPDZ128rmkz + 2517650347U, // VUNPCKLPDZ128rr + 49302443U, // VUNPCKLPDZ128rrk + 2532330411U, // VUNPCKLPDZ128rrkz + 2517650347U, // VUNPCKLPDZ256rm + 2517650347U, // VUNPCKLPDZ256rmb + 49302443U, // VUNPCKLPDZ256rmbk + 2532330411U, // VUNPCKLPDZ256rmbkz + 49302443U, // VUNPCKLPDZ256rmk + 2532330411U, // VUNPCKLPDZ256rmkz + 2517650347U, // VUNPCKLPDZ256rr + 49302443U, // VUNPCKLPDZ256rrk + 2532330411U, // VUNPCKLPDZ256rrkz + 2517650347U, // VUNPCKLPDZrm + 2517650347U, // VUNPCKLPDZrmb + 49302443U, // VUNPCKLPDZrmbk + 2532330411U, // VUNPCKLPDZrmbkz + 49302443U, // VUNPCKLPDZrmk + 2532330411U, // VUNPCKLPDZrmkz + 2517650347U, // VUNPCKLPDZrr + 49302443U, // VUNPCKLPDZrrk + 2532330411U, // VUNPCKLPDZrrkz + 2517650347U, // VUNPCKLPDrm + 2517650347U, // VUNPCKLPDrr + 2517655166U, // VUNPCKLPSYrm + 2517655166U, // VUNPCKLPSYrr + 2517655166U, // VUNPCKLPSZ128rm + 2517655166U, // VUNPCKLPSZ128rmb + 49307262U, // VUNPCKLPSZ128rmbk + 2532335230U, // VUNPCKLPSZ128rmbkz + 49307262U, // VUNPCKLPSZ128rmk + 2532335230U, // VUNPCKLPSZ128rmkz + 2517655166U, // VUNPCKLPSZ128rr + 49307262U, // VUNPCKLPSZ128rrk + 2532335230U, // VUNPCKLPSZ128rrkz + 2517655166U, // VUNPCKLPSZ256rm + 2517655166U, // VUNPCKLPSZ256rmb + 49307262U, // VUNPCKLPSZ256rmbk + 2532335230U, // VUNPCKLPSZ256rmbkz + 49307262U, // VUNPCKLPSZ256rmk + 2532335230U, // VUNPCKLPSZ256rmkz + 2517655166U, // VUNPCKLPSZ256rr + 49307262U, // VUNPCKLPSZ256rrk + 2532335230U, // VUNPCKLPSZ256rrkz + 2517655166U, // VUNPCKLPSZrm + 2517655166U, // VUNPCKLPSZrmb + 49307262U, // VUNPCKLPSZrmbk + 2532335230U, // VUNPCKLPSZrmbkz + 49307262U, // VUNPCKLPSZrmk + 2532335230U, // VUNPCKLPSZrmkz + 2517655166U, // VUNPCKLPSZrr + 49307262U, // VUNPCKLPSZrrk + 2532335230U, // VUNPCKLPSZrrkz + 2517655166U, // VUNPCKLPSrm + 2517655166U, // VUNPCKLPSrr + 2517650491U, // VXORPDYrm + 2517650491U, // VXORPDYrr + 2517650491U, // VXORPDZ128rm + 2517650491U, // VXORPDZ128rmb + 49302587U, // VXORPDZ128rmbk + 2532330555U, // VXORPDZ128rmbkz + 49302587U, // VXORPDZ128rmk + 2532330555U, // VXORPDZ128rmkz + 2517650491U, // VXORPDZ128rr + 49302587U, // VXORPDZ128rrk + 2532330555U, // VXORPDZ128rrkz + 2517650491U, // VXORPDZ256rm + 2517650491U, // VXORPDZ256rmb + 49302587U, // VXORPDZ256rmbk + 2532330555U, // VXORPDZ256rmbkz + 49302587U, // VXORPDZ256rmk + 2532330555U, // VXORPDZ256rmkz + 2517650491U, // VXORPDZ256rr + 49302587U, // VXORPDZ256rrk + 2532330555U, // VXORPDZ256rrkz + 2517650491U, // VXORPDZrm + 2517650491U, // VXORPDZrmb + 49302587U, // VXORPDZrmbk + 2532330555U, // VXORPDZrmbkz + 49302587U, // VXORPDZrmk + 2532330555U, // VXORPDZrmkz + 2517650491U, // VXORPDZrr + 49302587U, // VXORPDZrrk + 2532330555U, // VXORPDZrrkz + 2517650491U, // VXORPDrm + 2517650491U, // VXORPDrr + 2517655310U, // VXORPSYrm + 2517655310U, // VXORPSYrr + 2517655310U, // VXORPSZ128rm + 2517655310U, // VXORPSZ128rmb + 49307406U, // VXORPSZ128rmbk + 2532335374U, // VXORPSZ128rmbkz + 49307406U, // VXORPSZ128rmk + 2532335374U, // VXORPSZ128rmkz + 2517655310U, // VXORPSZ128rr + 49307406U, // VXORPSZ128rrk + 2532335374U, // VXORPSZ128rrkz + 2517655310U, // VXORPSZ256rm + 2517655310U, // VXORPSZ256rmb + 49307406U, // VXORPSZ256rmbk + 2532335374U, // VXORPSZ256rmbkz + 49307406U, // VXORPSZ256rmk + 2532335374U, // VXORPSZ256rmkz + 2517655310U, // VXORPSZ256rr + 49307406U, // VXORPSZ256rrk + 2532335374U, // VXORPSZ256rrkz + 2517655310U, // VXORPSZrm + 2517655310U, // VXORPSZrmb + 49307406U, // VXORPSZrmbk + 2532335374U, // VXORPSZrmbkz + 49307406U, // VXORPSZrmk + 2532335374U, // VXORPSZrmkz + 2517655310U, // VXORPSZrr + 49307406U, // VXORPSZrrk + 2532335374U, // VXORPSZrrkz + 2517655310U, // VXORPSrm + 2517655310U, // VXORPSrr + 11490U, // VZEROALL + 11712U, // VZEROUPPER + 11928U, // WAIT + 11233U, // WBINVD + 11240U, // WBNOINVD + 20919U, // WRFSBASE + 20919U, // WRFSBASE64 + 20939U, // WRGSBASE + 20939U, // WRGSBASE64 + 11746U, // WRMSR + 11990U, // WRPKRUr + 1117990U, // WRSSD + 1136938U, // WRSSQ + 1118009U, // WRUSSD + 1136945U, // WRUSSQ + 25198U, // XABORT + 11313U, // XACQUIRE_PREFIX + 755575U, // XADD16rm + 771959U, // XADD16rr + 788343U, // XADD32rm + 771959U, // XADD32rr + 804727U, // XADD64rm + 771959U, // XADD64rr + 821111U, // XADD8rm + 771959U, // XADD8rr + 185476U, // XBEGIN_2 + 185476U, // XBEGIN_4 + 9490996U, // XCHG16ar + 758324U, // XCHG16rm + 840244U, // XCHG16rr + 10539572U, // XCHG32ar + 791092U, // XCHG32rm + 840244U, // XCHG32rr + 11588148U, // XCHG64ar + 807476U, // XCHG64rm + 840244U, // XCHG64rr + 823860U, // XCHG8rm + 840244U, // XCHG8rr + 21085U, // XCH_F + 11142U, // XCRYPTCBC + 11106U, // XCRYPTCFB + 11752U, // XCRYPTCTR + 11096U, // XCRYPTECB + 11116U, // XCRYPTOFB + 11218U, // XEND + 11997U, // XGETBV + 11126U, // XLAT + 26771U, // XOR16i16 + 1088215U, // XOR16mi + 1088215U, // XOR16mi8 + 1088215U, // XOR16mr + 34659031U, // XOR16ri + 34659031U, // XOR16ri8 + 68213463U, // XOR16rm + 34659031U, // XOR16rr + 34626263U, // XOR16rr_REV + 26926U, // XOR32i32 + 1120983U, // XOR32mi + 1120983U, // XOR32mi8 + 1120983U, // XOR32mr + 34659031U, // XOR32ri + 34659031U, // XOR32ri8 + 101767895U, // XOR32rm + 34659031U, // XOR32rr + 34626263U, // XOR32rr_REV + 27054U, // XOR64i32 + 1137367U, // XOR64mi32 + 1137367U, // XOR64mi8 + 1137367U, // XOR64mr + 34659031U, // XOR64ri32 + 34659031U, // XOR64ri8 + 135322327U, // XOR64rm + 34659031U, // XOR64rr + 34626263U, // XOR64rr_REV + 26669U, // XOR8i8 + 1153751U, // XOR8mi + 1153751U, // XOR8mi8 + 1153751U, // XOR8mr + 34659031U, // XOR8ri + 34659031U, // XOR8ri8 + 168876759U, // XOR8rm + 34659031U, // XOR8rr + 34626263U, // XOR8rr_REV + 202394684U, // XORPDrm + 34622524U, // XORPDrr + 202399503U, // XORPSrm + 34627343U, // XORPSrr + 11329U, // XRELEASE_PREFIX + 301773U, // XRSTOR + 295260U, // XRSTOR64 + 303025U, // XRSTORS + 295280U, // XRSTORS64 + 299539U, // XSAVE + 295250U, // XSAVE64 + 296615U, // XSAVEC + 295239U, // XSAVEC64 + 303704U, // XSAVEOPT + 295291U, // XSAVEOPT64 + 301920U, // XSAVES + 295270U, // XSAVES64 + 12004U, // XSETBV + 10932U, // XSHA1 + 11025U, // XSHA256 + 11322U, // XSTORE + 11966U, // XTEST + }; + + static const uint32_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // AVX1_SETALLONES + 0U, // AVX2_SETALLONES + 0U, // AVX512_128_SET0 + 0U, // AVX512_256_SET0 + 0U, // AVX512_512_SET0 + 0U, // AVX512_512_SETALLONES + 0U, // AVX512_512_SEXT_MASK_32 + 0U, // AVX512_512_SEXT_MASK_64 + 0U, // AVX512_FsFLD0SD + 0U, // AVX512_FsFLD0SS + 0U, // AVX_SET0 + 0U, // KSET0D + 0U, // KSET0Q + 0U, // KSET0W + 0U, // KSET1D + 0U, // KSET1Q + 0U, // KSET1W + 0U, // MMX_SET0 + 0U, // V_SET0 + 0U, // V_SETALLONES + 0U, // AAA + 0U, // AAD8i8 + 0U, // AAM8i8 + 0U, // AAS + 0U, // ABS_F + 0U, // ABS_Fp32 + 0U, // ABS_Fp64 + 0U, // ABS_Fp80 + 0U, // ADC16i16 + 0U, // ADC16mi + 0U, // ADC16mi8 + 0U, // ADC16mr + 0U, // ADC16ri + 0U, // ADC16ri8 + 0U, // ADC16rm + 0U, // ADC16rr + 0U, // ADC16rr_REV + 0U, // ADC32i32 + 0U, // ADC32mi + 0U, // ADC32mi8 + 0U, // ADC32mr + 0U, // ADC32ri + 0U, // ADC32ri8 + 0U, // ADC32rm + 0U, // ADC32rr + 0U, // ADC32rr_REV + 0U, // ADC64i32 + 0U, // ADC64mi32 + 0U, // ADC64mi8 + 0U, // ADC64mr + 0U, // ADC64ri32 + 0U, // ADC64ri8 + 0U, // ADC64rm + 0U, // ADC64rr + 0U, // ADC64rr_REV + 0U, // ADC8i8 + 0U, // ADC8mi + 0U, // ADC8mi8 + 0U, // ADC8mr + 0U, // ADC8ri + 0U, // ADC8ri8 + 0U, // ADC8rm + 0U, // ADC8rr + 0U, // ADC8rr_REV + 0U, // ADCX32rm + 0U, // ADCX32rr + 0U, // ADCX64rm + 0U, // ADCX64rr + 0U, // ADD16i16 + 0U, // ADD16mi + 0U, // ADD16mi8 + 0U, // ADD16mr + 0U, // ADD16ri + 0U, // ADD16ri8 + 0U, // ADD16rm + 0U, // ADD16rr + 0U, // ADD16rr_REV + 0U, // ADD32i32 + 0U, // ADD32mi + 0U, // ADD32mi8 + 0U, // ADD32mr + 0U, // ADD32ri + 0U, // ADD32ri8 + 0U, // ADD32rm + 0U, // ADD32rr + 0U, // ADD32rr_REV + 0U, // ADD64i32 + 0U, // ADD64mi32 + 0U, // ADD64mi8 + 0U, // ADD64mr + 0U, // ADD64ri32 + 0U, // ADD64ri8 + 0U, // ADD64rm + 0U, // ADD64rr + 0U, // ADD64rr_REV + 0U, // ADD8i8 + 0U, // ADD8mi + 0U, // ADD8mi8 + 0U, // ADD8mr + 0U, // ADD8ri + 0U, // ADD8ri8 + 0U, // ADD8rm + 0U, // ADD8rr + 0U, // ADD8rr_REV + 0U, // ADDPDrm + 0U, // ADDPDrr + 0U, // ADDPSrm + 0U, // ADDPSrr + 0U, // ADDSDrm + 0U, // ADDSDrm_Int + 0U, // ADDSDrr + 0U, // ADDSDrr_Int + 0U, // ADDSSrm + 0U, // ADDSSrm_Int + 0U, // ADDSSrr + 0U, // ADDSSrr_Int + 0U, // ADDSUBPDrm + 0U, // ADDSUBPDrr + 0U, // ADDSUBPSrm + 0U, // ADDSUBPSrr + 0U, // ADD_F32m + 0U, // ADD_F64m + 0U, // ADD_FI16m + 0U, // ADD_FI32m + 0U, // ADD_FPrST0 + 0U, // ADD_FST0r + 0U, // ADD_Fp32 + 0U, // ADD_Fp32m + 0U, // ADD_Fp64 + 0U, // ADD_Fp64m + 0U, // ADD_Fp64m32 + 0U, // ADD_Fp80 + 0U, // ADD_Fp80m32 + 0U, // ADD_Fp80m64 + 0U, // ADD_FpI16m32 + 0U, // ADD_FpI16m64 + 0U, // ADD_FpI16m80 + 0U, // ADD_FpI32m32 + 0U, // ADD_FpI32m64 + 0U, // ADD_FpI32m80 + 0U, // ADD_FrST0 + 0U, // ADOX32rm + 0U, // ADOX32rr + 0U, // ADOX64rm + 0U, // ADOX64rr + 0U, // AESDECLASTrm + 0U, // AESDECLASTrr + 0U, // AESDECrm + 0U, // AESDECrr + 0U, // AESENCLASTrm + 0U, // AESENCLASTrr + 0U, // AESENCrm + 0U, // AESENCrr + 0U, // AESIMCrm + 0U, // AESIMCrr + 0U, // AESKEYGENASSIST128rm + 32U, // AESKEYGENASSIST128rr + 0U, // AND16i16 + 0U, // AND16mi + 0U, // AND16mi8 + 0U, // AND16mr + 0U, // AND16ri + 0U, // AND16ri8 + 0U, // AND16rm + 0U, // AND16rr + 0U, // AND16rr_REV + 0U, // AND32i32 + 0U, // AND32mi + 0U, // AND32mi8 + 0U, // AND32mr + 0U, // AND32ri + 0U, // AND32ri8 + 0U, // AND32rm + 0U, // AND32rr + 0U, // AND32rr_REV + 0U, // AND64i32 + 0U, // AND64mi32 + 0U, // AND64mi8 + 0U, // AND64mr + 0U, // AND64ri32 + 0U, // AND64ri8 + 0U, // AND64rm + 0U, // AND64rr + 0U, // AND64rr_REV + 0U, // AND8i8 + 0U, // AND8mi + 0U, // AND8mi8 + 0U, // AND8mr + 0U, // AND8ri + 0U, // AND8ri8 + 0U, // AND8rm + 0U, // AND8rr + 0U, // AND8rr_REV + 64U, // ANDN32rm + 96U, // ANDN32rr + 128U, // ANDN64rm + 96U, // ANDN64rr + 0U, // ANDNPDrm + 0U, // ANDNPDrr + 0U, // ANDNPSrm + 0U, // ANDNPSrr + 0U, // ANDPDrm + 0U, // ANDPDrr + 0U, // ANDPSrm + 0U, // ANDPSrr + 0U, // ARPL16mr + 0U, // ARPL16rr + 160U, // BEXTR32rm + 96U, // BEXTR32rr + 160U, // BEXTR64rm + 96U, // BEXTR64rr + 160U, // BEXTRI32mi + 96U, // BEXTRI32ri + 160U, // BEXTRI64mi + 96U, // BEXTRI64ri + 0U, // BLCFILL32rm + 0U, // BLCFILL32rr + 0U, // BLCFILL64rm + 0U, // BLCFILL64rr + 0U, // BLCI32rm + 0U, // BLCI32rr + 0U, // BLCI64rm + 0U, // BLCI64rr + 0U, // BLCIC32rm + 0U, // BLCIC32rr + 0U, // BLCIC64rm + 0U, // BLCIC64rr + 0U, // BLCMSK32rm + 0U, // BLCMSK32rr + 0U, // BLCMSK64rm + 0U, // BLCMSK64rr + 0U, // BLCS32rm + 0U, // BLCS32rr + 0U, // BLCS64rm + 0U, // BLCS64rr + 192U, // BLENDPDrmi + 224U, // BLENDPDrri + 192U, // BLENDPSrmi + 224U, // BLENDPSrri + 1U, // BLENDVPDrm0 + 1U, // BLENDVPDrr0 + 1U, // BLENDVPSrm0 + 1U, // BLENDVPSrr0 + 0U, // BLSFILL32rm + 0U, // BLSFILL32rr + 0U, // BLSFILL64rm + 0U, // BLSFILL64rr + 0U, // BLSI32rm + 0U, // BLSI32rr + 0U, // BLSI64rm + 0U, // BLSI64rr + 0U, // BLSIC32rm + 0U, // BLSIC32rr + 0U, // BLSIC64rm + 0U, // BLSIC64rr + 0U, // BLSMSK32rm + 0U, // BLSMSK32rr + 0U, // BLSMSK64rm + 0U, // BLSMSK64rr + 0U, // BLSR32rm + 0U, // BLSR32rr + 0U, // BLSR64rm + 0U, // BLSR64rr + 0U, // BNDCL32rm + 0U, // BNDCL32rr + 0U, // BNDCL64rm + 0U, // BNDCL64rr + 0U, // BNDCN32rm + 0U, // BNDCN32rr + 0U, // BNDCN64rm + 0U, // BNDCN64rr + 0U, // BNDCU32rm + 0U, // BNDCU32rr + 0U, // BNDCU64rm + 0U, // BNDCU64rr + 0U, // BNDLDXrm + 0U, // BNDMK32rm + 0U, // BNDMK64rm + 0U, // BNDMOV32mr + 0U, // BNDMOV32rm + 0U, // BNDMOV64mr + 0U, // BNDMOV64rm + 0U, // BNDMOVrr + 0U, // BNDMOVrr_REV + 0U, // BNDSTXmr + 0U, // BOUNDS16rm + 0U, // BOUNDS32rm + 0U, // BSF16rm + 0U, // BSF16rr + 0U, // BSF32rm + 0U, // BSF32rr + 0U, // BSF64rm + 0U, // BSF64rr + 0U, // BSR16rm + 0U, // BSR16rr + 0U, // BSR32rm + 0U, // BSR32rr + 0U, // BSR64rm + 0U, // BSR64rr + 0U, // BSWAP16r_BAD + 0U, // BSWAP32r + 0U, // BSWAP64r + 0U, // BT16mi8 + 0U, // BT16mr + 0U, // BT16ri8 + 0U, // BT16rr + 0U, // BT32mi8 + 0U, // BT32mr + 0U, // BT32ri8 + 0U, // BT32rr + 0U, // BT64mi8 + 0U, // BT64mr + 0U, // BT64ri8 + 0U, // BT64rr + 0U, // BTC16mi8 + 0U, // BTC16mr + 0U, // BTC16ri8 + 0U, // BTC16rr + 0U, // BTC32mi8 + 0U, // BTC32mr + 0U, // BTC32ri8 + 0U, // BTC32rr + 0U, // BTC64mi8 + 0U, // BTC64mr + 0U, // BTC64ri8 + 0U, // BTC64rr + 0U, // BTR16mi8 + 0U, // BTR16mr + 0U, // BTR16ri8 + 0U, // BTR16rr + 0U, // BTR32mi8 + 0U, // BTR32mr + 0U, // BTR32ri8 + 0U, // BTR32rr + 0U, // BTR64mi8 + 0U, // BTR64mr + 0U, // BTR64ri8 + 0U, // BTR64rr + 0U, // BTS16mi8 + 0U, // BTS16mr + 0U, // BTS16ri8 + 0U, // BTS16rr + 0U, // BTS32mi8 + 0U, // BTS32mr + 0U, // BTS32ri8 + 0U, // BTS32rr + 0U, // BTS64mi8 + 0U, // BTS64mr + 0U, // BTS64ri8 + 0U, // BTS64rr + 160U, // BZHI32rm + 96U, // BZHI32rr + 160U, // BZHI64rm + 96U, // BZHI64rr + 0U, // CALL16m + 0U, // CALL16m_NT + 0U, // CALL16r + 0U, // CALL16r_NT + 0U, // CALL32m + 0U, // CALL32m_NT + 0U, // CALL32r + 0U, // CALL32r_NT + 0U, // CALL64m + 0U, // CALL64m_NT + 0U, // CALL64pcrel32 + 0U, // CALL64r + 0U, // CALL64r_NT + 0U, // CALLpcrel16 + 0U, // CALLpcrel32 + 0U, // CBW + 0U, // CDQ + 0U, // CDQE + 0U, // CHS_F + 0U, // CHS_Fp32 + 0U, // CHS_Fp64 + 0U, // CHS_Fp80 + 0U, // CLAC + 0U, // CLC + 0U, // CLD + 0U, // CLDEMOTE + 0U, // CLFLUSH + 0U, // CLFLUSHOPT + 0U, // CLGI + 0U, // CLI + 0U, // CLRSSBSY + 0U, // CLTS + 0U, // CLWB + 0U, // CLZEROr + 0U, // CMC + 0U, // CMOVA16rm + 0U, // CMOVA16rr + 0U, // CMOVA32rm + 0U, // CMOVA32rr + 0U, // CMOVA64rm + 0U, // CMOVA64rr + 0U, // CMOVAE16rm + 0U, // CMOVAE16rr + 0U, // CMOVAE32rm + 0U, // CMOVAE32rr + 0U, // CMOVAE64rm + 0U, // CMOVAE64rr + 0U, // CMOVB16rm + 0U, // CMOVB16rr + 0U, // CMOVB32rm + 0U, // CMOVB32rr + 0U, // CMOVB64rm + 0U, // CMOVB64rr + 0U, // CMOVBE16rm + 0U, // CMOVBE16rr + 0U, // CMOVBE32rm + 0U, // CMOVBE32rr + 0U, // CMOVBE64rm + 0U, // CMOVBE64rr + 0U, // CMOVBE_F + 0U, // CMOVBE_Fp32 + 0U, // CMOVBE_Fp64 + 0U, // CMOVBE_Fp80 + 0U, // CMOVB_F + 0U, // CMOVB_Fp32 + 0U, // CMOVB_Fp64 + 0U, // CMOVB_Fp80 + 0U, // CMOVE16rm + 0U, // CMOVE16rr + 0U, // CMOVE32rm + 0U, // CMOVE32rr + 0U, // CMOVE64rm + 0U, // CMOVE64rr + 0U, // CMOVE_F + 0U, // CMOVE_Fp32 + 0U, // CMOVE_Fp64 + 0U, // CMOVE_Fp80 + 0U, // CMOVG16rm + 0U, // CMOVG16rr + 0U, // CMOVG32rm + 0U, // CMOVG32rr + 0U, // CMOVG64rm + 0U, // CMOVG64rr + 0U, // CMOVGE16rm + 0U, // CMOVGE16rr + 0U, // CMOVGE32rm + 0U, // CMOVGE32rr + 0U, // CMOVGE64rm + 0U, // CMOVGE64rr + 0U, // CMOVL16rm + 0U, // CMOVL16rr + 0U, // CMOVL32rm + 0U, // CMOVL32rr + 0U, // CMOVL64rm + 0U, // CMOVL64rr + 0U, // CMOVLE16rm + 0U, // CMOVLE16rr + 0U, // CMOVLE32rm + 0U, // CMOVLE32rr + 0U, // CMOVLE64rm + 0U, // CMOVLE64rr + 0U, // CMOVNBE_F + 0U, // CMOVNBE_Fp32 + 0U, // CMOVNBE_Fp64 + 0U, // CMOVNBE_Fp80 + 0U, // CMOVNB_F + 0U, // CMOVNB_Fp32 + 0U, // CMOVNB_Fp64 + 0U, // CMOVNB_Fp80 + 0U, // CMOVNE16rm + 0U, // CMOVNE16rr + 0U, // CMOVNE32rm + 0U, // CMOVNE32rr + 0U, // CMOVNE64rm + 0U, // CMOVNE64rr + 0U, // CMOVNE_F + 0U, // CMOVNE_Fp32 + 0U, // CMOVNE_Fp64 + 0U, // CMOVNE_Fp80 + 0U, // CMOVNO16rm + 0U, // CMOVNO16rr + 0U, // CMOVNO32rm + 0U, // CMOVNO32rr + 0U, // CMOVNO64rm + 0U, // CMOVNO64rr + 0U, // CMOVNP16rm + 0U, // CMOVNP16rr + 0U, // CMOVNP32rm + 0U, // CMOVNP32rr + 0U, // CMOVNP64rm + 0U, // CMOVNP64rr + 0U, // CMOVNP_F + 0U, // CMOVNP_Fp32 + 0U, // CMOVNP_Fp64 + 0U, // CMOVNP_Fp80 + 0U, // CMOVNS16rm + 0U, // CMOVNS16rr + 0U, // CMOVNS32rm + 0U, // CMOVNS32rr + 0U, // CMOVNS64rm + 0U, // CMOVNS64rr + 0U, // CMOVO16rm + 0U, // CMOVO16rr + 0U, // CMOVO32rm + 0U, // CMOVO32rr + 0U, // CMOVO64rm + 0U, // CMOVO64rr + 0U, // CMOVP16rm + 0U, // CMOVP16rr + 0U, // CMOVP32rm + 0U, // CMOVP32rr + 0U, // CMOVP64rm + 0U, // CMOVP64rr + 0U, // CMOVP_F + 0U, // CMOVP_Fp32 + 0U, // CMOVP_Fp64 + 0U, // CMOVP_Fp80 + 0U, // CMOVS16rm + 0U, // CMOVS16rr + 0U, // CMOVS32rm + 0U, // CMOVS32rr + 0U, // CMOVS64rm + 0U, // CMOVS64rr + 0U, // CMP16i16 + 0U, // CMP16mi + 0U, // CMP16mi8 + 0U, // CMP16mr + 0U, // CMP16ri + 0U, // CMP16ri8 + 0U, // CMP16rm + 0U, // CMP16rr + 0U, // CMP16rr_REV + 0U, // CMP32i32 + 0U, // CMP32mi + 0U, // CMP32mi8 + 0U, // CMP32mr + 0U, // CMP32ri + 0U, // CMP32ri8 + 0U, // CMP32rm + 0U, // CMP32rr + 0U, // CMP32rr_REV + 0U, // CMP64i32 + 0U, // CMP64mi32 + 0U, // CMP64mi8 + 0U, // CMP64mr + 0U, // CMP64ri32 + 0U, // CMP64ri8 + 0U, // CMP64rm + 0U, // CMP64rr + 0U, // CMP64rr_REV + 0U, // CMP8i8 + 0U, // CMP8mi + 0U, // CMP8mi8 + 0U, // CMP8mr + 0U, // CMP8ri + 0U, // CMP8ri8 + 0U, // CMP8rm + 0U, // CMP8rr + 0U, // CMP8rr_REV + 1U, // CMPPDrmi + 192U, // CMPPDrmi_alt + 2U, // CMPPDrri + 224U, // CMPPDrri_alt + 1U, // CMPPSrmi + 192U, // CMPPSrmi_alt + 2U, // CMPPSrri + 224U, // CMPPSrri_alt + 0U, // CMPSB + 2U, // CMPSDrm + 2U, // CMPSDrm_Int + 192U, // CMPSDrm_alt + 2U, // CMPSDrr + 2U, // CMPSDrr_Int + 224U, // CMPSDrr_alt + 0U, // CMPSL + 0U, // CMPSQ + 3U, // CMPSSrm + 3U, // CMPSSrm_Int + 192U, // CMPSSrm_alt + 2U, // CMPSSrr + 2U, // CMPSSrr_Int + 224U, // CMPSSrr_alt + 0U, // CMPSW + 0U, // CMPXCHG16B + 0U, // CMPXCHG16rm + 0U, // CMPXCHG16rr + 0U, // CMPXCHG32rm + 0U, // CMPXCHG32rr + 0U, // CMPXCHG64rm + 0U, // CMPXCHG64rr + 0U, // CMPXCHG8B + 0U, // CMPXCHG8rm + 0U, // CMPXCHG8rr + 0U, // COMISDrm + 0U, // COMISDrm_Int + 0U, // COMISDrr + 0U, // COMISDrr_Int + 0U, // COMISSrm + 0U, // COMISSrm_Int + 0U, // COMISSrr + 0U, // COMISSrr_Int + 0U, // COMP_FST0r + 0U, // COM_FIPr + 0U, // COM_FIr + 0U, // COM_FST0r + 0U, // COS_F + 0U, // COS_Fp32 + 0U, // COS_Fp64 + 0U, // COS_Fp80 + 0U, // CPUID + 0U, // CQO + 0U, // CRC32r32m16 + 0U, // CRC32r32m32 + 0U, // CRC32r32m8 + 0U, // CRC32r32r16 + 0U, // CRC32r32r32 + 0U, // CRC32r32r8 + 0U, // CRC32r64m64 + 0U, // CRC32r64m8 + 0U, // CRC32r64r64 + 0U, // CRC32r64r8 + 0U, // CVTDQ2PDrm + 0U, // CVTDQ2PDrr + 0U, // CVTDQ2PSrm + 0U, // CVTDQ2PSrr + 0U, // CVTPD2DQrm + 0U, // CVTPD2DQrr + 0U, // CVTPD2PSrm + 0U, // CVTPD2PSrr + 0U, // CVTPS2DQrm + 0U, // CVTPS2DQrr + 0U, // CVTPS2PDrm + 0U, // CVTPS2PDrr + 0U, // CVTSD2SI64rm_Int + 0U, // CVTSD2SI64rr_Int + 0U, // CVTSD2SIrm_Int + 0U, // CVTSD2SIrr_Int + 0U, // CVTSD2SSrm + 0U, // CVTSD2SSrm_Int + 0U, // CVTSD2SSrr + 0U, // CVTSD2SSrr_Int + 0U, // CVTSI2SDrm + 0U, // CVTSI2SDrm_Int + 0U, // CVTSI2SDrr + 0U, // CVTSI2SDrr_Int + 0U, // CVTSI2SSrm + 0U, // CVTSI2SSrm_Int + 0U, // CVTSI2SSrr + 0U, // CVTSI2SSrr_Int + 0U, // CVTSI642SDrm + 0U, // CVTSI642SDrm_Int + 0U, // CVTSI642SDrr + 0U, // CVTSI642SDrr_Int + 0U, // CVTSI642SSrm + 0U, // CVTSI642SSrm_Int + 0U, // CVTSI642SSrr + 0U, // CVTSI642SSrr_Int + 0U, // CVTSS2SDrm + 0U, // CVTSS2SDrm_Int + 0U, // CVTSS2SDrr + 0U, // CVTSS2SDrr_Int + 0U, // CVTSS2SI64rm_Int + 0U, // CVTSS2SI64rr_Int + 0U, // CVTSS2SIrm_Int + 0U, // CVTSS2SIrr_Int + 0U, // CVTTPD2DQrm + 0U, // CVTTPD2DQrr + 0U, // CVTTPS2DQrm + 0U, // CVTTPS2DQrr + 0U, // CVTTSD2SI64rm + 0U, // CVTTSD2SI64rm_Int + 0U, // CVTTSD2SI64rr + 0U, // CVTTSD2SI64rr_Int + 0U, // CVTTSD2SIrm + 0U, // CVTTSD2SIrm_Int + 0U, // CVTTSD2SIrr + 0U, // CVTTSD2SIrr_Int + 0U, // CVTTSS2SI64rm + 0U, // CVTTSS2SI64rm_Int + 0U, // CVTTSS2SI64rr + 0U, // CVTTSS2SI64rr_Int + 0U, // CVTTSS2SIrm + 0U, // CVTTSS2SIrm_Int + 0U, // CVTTSS2SIrr + 0U, // CVTTSS2SIrr_Int + 0U, // CWD + 0U, // CWDE + 0U, // DAA + 0U, // DAS + 0U, // DATA16_PREFIX + 0U, // DEC16m + 0U, // DEC16r + 0U, // DEC16r_alt + 0U, // DEC32m + 0U, // DEC32r + 0U, // DEC32r_alt + 0U, // DEC64m + 0U, // DEC64r + 0U, // DEC8m + 0U, // DEC8r + 0U, // DIV16m + 0U, // DIV16r + 0U, // DIV32m + 0U, // DIV32r + 0U, // DIV64m + 0U, // DIV64r + 0U, // DIV8m + 0U, // DIV8r + 0U, // DIVPDrm + 0U, // DIVPDrr + 0U, // DIVPSrm + 0U, // DIVPSrr + 0U, // DIVR_F32m + 0U, // DIVR_F64m + 0U, // DIVR_FI16m + 0U, // DIVR_FI32m + 0U, // DIVR_FPrST0 + 0U, // DIVR_FST0r + 0U, // DIVR_Fp32m + 0U, // DIVR_Fp64m + 0U, // DIVR_Fp64m32 + 0U, // DIVR_Fp80m32 + 0U, // DIVR_Fp80m64 + 0U, // DIVR_FpI16m32 + 0U, // DIVR_FpI16m64 + 0U, // DIVR_FpI16m80 + 0U, // DIVR_FpI32m32 + 0U, // DIVR_FpI32m64 + 0U, // DIVR_FpI32m80 + 0U, // DIVR_FrST0 + 0U, // DIVSDrm + 0U, // DIVSDrm_Int + 0U, // DIVSDrr + 0U, // DIVSDrr_Int + 0U, // DIVSSrm + 0U, // DIVSSrm_Int + 0U, // DIVSSrr + 0U, // DIVSSrr_Int + 0U, // DIV_F32m + 0U, // DIV_F64m + 0U, // DIV_FI16m + 0U, // DIV_FI32m + 0U, // DIV_FPrST0 + 0U, // DIV_FST0r + 0U, // DIV_Fp32 + 0U, // DIV_Fp32m + 0U, // DIV_Fp64 + 0U, // DIV_Fp64m + 0U, // DIV_Fp64m32 + 0U, // DIV_Fp80 + 0U, // DIV_Fp80m32 + 0U, // DIV_Fp80m64 + 0U, // DIV_FpI16m32 + 0U, // DIV_FpI16m64 + 0U, // DIV_FpI16m80 + 0U, // DIV_FpI32m32 + 0U, // DIV_FpI32m64 + 0U, // DIV_FpI32m80 + 0U, // DIV_FrST0 + 192U, // DPPDrmi + 224U, // DPPDrri + 192U, // DPPSrmi + 224U, // DPPSrri + 0U, // ENCLS + 0U, // ENCLU + 0U, // ENCLV + 0U, // ENDBR32 + 0U, // ENDBR64 + 0U, // ENTER + 0U, // EXTRACTPSmr + 32U, // EXTRACTPSrr + 0U, // EXTRQ + 224U, // EXTRQI + 0U, // F2XM1 + 0U, // FARCALL16i + 0U, // FARCALL16m + 0U, // FARCALL32i + 0U, // FARCALL32m + 0U, // FARCALL64 + 0U, // FARJMP16i + 0U, // FARJMP16m + 0U, // FARJMP32i + 0U, // FARJMP32m + 0U, // FARJMP64 + 0U, // FBLDm + 0U, // FBSTPm + 0U, // FCOM32m + 0U, // FCOM64m + 0U, // FCOMP32m + 0U, // FCOMP64m + 0U, // FCOMPP + 0U, // FDECSTP + 0U, // FDISI8087_NOP + 0U, // FEMMS + 0U, // FENI8087_NOP + 0U, // FFREE + 0U, // FFREEP + 0U, // FICOM16m + 0U, // FICOM32m + 0U, // FICOMP16m + 0U, // FICOMP32m + 0U, // FINCSTP + 0U, // FLDCW16m + 0U, // FLDENVm + 0U, // FLDL2E + 0U, // FLDL2T + 0U, // FLDLG2 + 0U, // FLDLN2 + 0U, // FLDPI + 0U, // FNCLEX + 0U, // FNINIT + 0U, // FNOP + 0U, // FNSTCW16m + 0U, // FNSTSW16r + 0U, // FNSTSWm + 0U, // FPATAN + 0U, // FPNCEST0r + 0U, // FPREM + 0U, // FPREM1 + 0U, // FPTAN + 0U, // FRNDINT + 0U, // FRSTORm + 0U, // FSAVEm + 0U, // FSCALE + 0U, // FSETPM + 0U, // FSINCOS + 0U, // FSTENVm + 0U, // FXAM + 0U, // FXRSTOR + 0U, // FXRSTOR64 + 0U, // FXSAVE + 0U, // FXSAVE64 + 0U, // FXTRACT + 0U, // FYL2X + 0U, // FYL2XP1 + 0U, // GETSEC + 192U, // GF2P8AFFINEINVQBrmi + 224U, // GF2P8AFFINEINVQBrri + 192U, // GF2P8AFFINEQBrmi + 224U, // GF2P8AFFINEQBrri + 0U, // GF2P8MULBrm + 0U, // GF2P8MULBrr + 0U, // HADDPDrm + 0U, // HADDPDrr + 0U, // HADDPSrm + 0U, // HADDPSrr + 0U, // HLT + 0U, // HSUBPDrm + 0U, // HSUBPDrr + 0U, // HSUBPSrm + 0U, // HSUBPSrr + 0U, // IDIV16m + 0U, // IDIV16r + 0U, // IDIV32m + 0U, // IDIV32r + 0U, // IDIV64m + 0U, // IDIV64r + 0U, // IDIV8m + 0U, // IDIV8r + 0U, // ILD_F16m + 0U, // ILD_F32m + 0U, // ILD_F64m + 0U, // ILD_Fp16m32 + 0U, // ILD_Fp16m64 + 0U, // ILD_Fp16m80 + 0U, // ILD_Fp32m32 + 0U, // ILD_Fp32m64 + 0U, // ILD_Fp32m80 + 0U, // ILD_Fp64m32 + 0U, // ILD_Fp64m64 + 0U, // ILD_Fp64m80 + 0U, // IMUL16m + 0U, // IMUL16r + 0U, // IMUL16rm + 160U, // IMUL16rmi + 160U, // IMUL16rmi8 + 0U, // IMUL16rr + 96U, // IMUL16rri + 96U, // IMUL16rri8 + 0U, // IMUL32m + 0U, // IMUL32r + 0U, // IMUL32rm + 160U, // IMUL32rmi + 160U, // IMUL32rmi8 + 0U, // IMUL32rr + 96U, // IMUL32rri + 96U, // IMUL32rri8 + 0U, // IMUL64m + 0U, // IMUL64r + 0U, // IMUL64rm + 160U, // IMUL64rmi32 + 160U, // IMUL64rmi8 + 0U, // IMUL64rr + 96U, // IMUL64rri32 + 96U, // IMUL64rri8 + 0U, // IMUL8m + 0U, // IMUL8r + 0U, // IN16ri + 0U, // IN16rr + 0U, // IN32ri + 0U, // IN32rr + 0U, // IN8ri + 0U, // IN8rr + 0U, // INC16m + 0U, // INC16r + 0U, // INC16r_alt + 0U, // INC32m + 0U, // INC32r + 0U, // INC32r_alt + 0U, // INC64m + 0U, // INC64r + 0U, // INC8m + 0U, // INC8r + 0U, // INCSSPD + 0U, // INCSSPQ + 0U, // INSB + 192U, // INSERTPSrm + 224U, // INSERTPSrr + 0U, // INSERTQ + 2272U, // INSERTQI + 0U, // INSL + 0U, // INSW + 0U, // INT + 0U, // INT1 + 0U, // INT3 + 0U, // INTO + 0U, // INVD + 0U, // INVEPT32 + 0U, // INVEPT64 + 0U, // INVLPG + 0U, // INVLPGA32 + 0U, // INVLPGA64 + 0U, // INVPCID32 + 0U, // INVPCID64 + 0U, // INVVPID32 + 0U, // INVVPID64 + 0U, // IRET16 + 0U, // IRET32 + 0U, // IRET64 + 0U, // ISTT_FP16m + 0U, // ISTT_FP32m + 0U, // ISTT_FP64m + 0U, // ISTT_Fp16m32 + 0U, // ISTT_Fp16m64 + 0U, // ISTT_Fp16m80 + 0U, // ISTT_Fp32m32 + 0U, // ISTT_Fp32m64 + 0U, // ISTT_Fp32m80 + 0U, // ISTT_Fp64m32 + 0U, // ISTT_Fp64m64 + 0U, // ISTT_Fp64m80 + 0U, // IST_F16m + 0U, // IST_F32m + 0U, // IST_FP16m + 0U, // IST_FP32m + 0U, // IST_FP64m + 0U, // IST_Fp16m32 + 0U, // IST_Fp16m64 + 0U, // IST_Fp16m80 + 0U, // IST_Fp32m32 + 0U, // IST_Fp32m64 + 0U, // IST_Fp32m80 + 0U, // IST_Fp64m32 + 0U, // IST_Fp64m64 + 0U, // IST_Fp64m80 + 0U, // JAE_1 + 0U, // JAE_2 + 0U, // JAE_4 + 0U, // JA_1 + 0U, // JA_2 + 0U, // JA_4 + 0U, // JBE_1 + 0U, // JBE_2 + 0U, // JBE_4 + 0U, // JB_1 + 0U, // JB_2 + 0U, // JB_4 + 0U, // JCXZ + 0U, // JECXZ + 0U, // JE_1 + 0U, // JE_2 + 0U, // JE_4 + 0U, // JGE_1 + 0U, // JGE_2 + 0U, // JGE_4 + 0U, // JG_1 + 0U, // JG_2 + 0U, // JG_4 + 0U, // JLE_1 + 0U, // JLE_2 + 0U, // JLE_4 + 0U, // JL_1 + 0U, // JL_2 + 0U, // JL_4 + 0U, // JMP16m + 0U, // JMP16m_NT + 0U, // JMP16r + 0U, // JMP16r_NT + 0U, // JMP32m + 0U, // JMP32m_NT + 0U, // JMP32r + 0U, // JMP32r_NT + 0U, // JMP64m + 0U, // JMP64m_NT + 0U, // JMP64r + 0U, // JMP64r_NT + 0U, // JMP_1 + 0U, // JMP_2 + 0U, // JMP_4 + 0U, // JNE_1 + 0U, // JNE_2 + 0U, // JNE_4 + 0U, // JNO_1 + 0U, // JNO_2 + 0U, // JNO_4 + 0U, // JNP_1 + 0U, // JNP_2 + 0U, // JNP_4 + 0U, // JNS_1 + 0U, // JNS_2 + 0U, // JNS_4 + 0U, // JO_1 + 0U, // JO_2 + 0U, // JO_4 + 0U, // JP_1 + 0U, // JP_2 + 0U, // JP_4 + 0U, // JRCXZ + 0U, // JS_1 + 0U, // JS_2 + 0U, // JS_4 + 96U, // KADDBrr + 96U, // KADDDrr + 96U, // KADDQrr + 96U, // KADDWrr + 96U, // KANDBrr + 96U, // KANDDrr + 96U, // KANDNBrr + 96U, // KANDNDrr + 96U, // KANDNQrr + 96U, // KANDNWrr + 96U, // KANDQrr + 96U, // KANDWrr + 0U, // KMOVBkk + 0U, // KMOVBkm + 0U, // KMOVBkr + 0U, // KMOVBmk + 0U, // KMOVBrk + 0U, // KMOVDkk + 0U, // KMOVDkm + 0U, // KMOVDkr + 0U, // KMOVDmk + 0U, // KMOVDrk + 0U, // KMOVQkk + 0U, // KMOVQkm + 0U, // KMOVQkr + 0U, // KMOVQmk + 0U, // KMOVQrk + 0U, // KMOVWkk + 0U, // KMOVWkm + 0U, // KMOVWkr + 0U, // KMOVWmk + 0U, // KMOVWrk + 0U, // KNOTBrr + 0U, // KNOTDrr + 0U, // KNOTQrr + 0U, // KNOTWrr + 96U, // KORBrr + 96U, // KORDrr + 96U, // KORQrr + 0U, // KORTESTBrr + 0U, // KORTESTDrr + 0U, // KORTESTQrr + 0U, // KORTESTWrr + 96U, // KORWrr + 32U, // KSHIFTLBri + 32U, // KSHIFTLDri + 32U, // KSHIFTLQri + 32U, // KSHIFTLWri + 32U, // KSHIFTRBri + 32U, // KSHIFTRDri + 32U, // KSHIFTRQri + 32U, // KSHIFTRWri + 0U, // KTESTBrr + 0U, // KTESTDrr + 0U, // KTESTQrr + 0U, // KTESTWrr + 96U, // KUNPCKBWrr + 96U, // KUNPCKDQrr + 96U, // KUNPCKWDrr + 96U, // KXNORBrr + 96U, // KXNORDrr + 96U, // KXNORQrr + 96U, // KXNORWrr + 96U, // KXORBrr + 96U, // KXORDrr + 96U, // KXORQrr + 96U, // KXORWrr + 0U, // LAHF + 0U, // LAR16rm + 0U, // LAR16rr + 0U, // LAR32rm + 0U, // LAR32rr + 0U, // LAR64rm + 0U, // LAR64rr + 0U, // LDDQUrm + 0U, // LDMXCSR + 0U, // LDS16rm + 0U, // LDS32rm + 0U, // LD_F0 + 0U, // LD_F1 + 0U, // LD_F32m + 0U, // LD_F64m + 0U, // LD_F80m + 0U, // LD_Fp032 + 0U, // LD_Fp064 + 0U, // LD_Fp080 + 0U, // LD_Fp132 + 0U, // LD_Fp164 + 0U, // LD_Fp180 + 0U, // LD_Fp32m + 0U, // LD_Fp32m64 + 0U, // LD_Fp32m80 + 0U, // LD_Fp64m + 0U, // LD_Fp64m80 + 0U, // LD_Fp80m + 0U, // LD_Frr + 0U, // LEA16r + 0U, // LEA32r + 0U, // LEA64_32r + 0U, // LEA64r + 0U, // LEAVE + 0U, // LEAVE64 + 0U, // LES16rm + 0U, // LES32rm + 0U, // LFENCE + 0U, // LFS16rm + 0U, // LFS32rm + 0U, // LFS64rm + 0U, // LGDT16m + 0U, // LGDT32m + 0U, // LGDT64m + 0U, // LGS16rm + 0U, // LGS32rm + 0U, // LGS64rm + 0U, // LIDT16m + 0U, // LIDT32m + 0U, // LIDT64m + 0U, // LLDT16m + 0U, // LLDT16r + 0U, // LLWPCB + 0U, // LLWPCB64 + 0U, // LMSW16m + 0U, // LMSW16r + 0U, // LOCK_PREFIX + 0U, // LODSB + 0U, // LODSL + 0U, // LODSQ + 0U, // LODSW + 0U, // LOOP + 0U, // LOOPE + 0U, // LOOPNE + 0U, // LRETIL + 0U, // LRETIQ + 0U, // LRETIW + 0U, // LRETL + 0U, // LRETQ + 0U, // LRETW + 0U, // LSL16rm + 0U, // LSL16rr + 0U, // LSL32rm + 0U, // LSL32rr + 0U, // LSL64rm + 0U, // LSL64rr + 0U, // LSS16rm + 0U, // LSS32rm + 0U, // LSS64rm + 0U, // LTRm + 0U, // LTRr + 160U, // LWPINS32rmi + 96U, // LWPINS32rri + 160U, // LWPINS64rmi + 96U, // LWPINS64rri + 160U, // LWPVAL32rmi + 96U, // LWPVAL32rri + 160U, // LWPVAL64rmi + 96U, // LWPVAL64rri + 0U, // LZCNT16rm + 0U, // LZCNT16rr + 0U, // LZCNT32rm + 0U, // LZCNT32rr + 0U, // LZCNT64rm + 0U, // LZCNT64rr + 0U, // MASKMOVDQU + 0U, // MASKMOVDQU64 + 0U, // MAXCPDrm + 0U, // MAXCPDrr + 0U, // MAXCPSrm + 0U, // MAXCPSrr + 0U, // MAXCSDrm + 0U, // MAXCSDrr + 0U, // MAXCSSrm + 0U, // MAXCSSrr + 0U, // MAXPDrm + 0U, // MAXPDrr + 0U, // MAXPSrm + 0U, // MAXPSrr + 0U, // MAXSDrm + 0U, // MAXSDrm_Int + 0U, // MAXSDrr + 0U, // MAXSDrr_Int + 0U, // MAXSSrm + 0U, // MAXSSrm_Int + 0U, // MAXSSrr + 0U, // MAXSSrr_Int + 0U, // MFENCE + 0U, // MINCPDrm + 0U, // MINCPDrr + 0U, // MINCPSrm + 0U, // MINCPSrr + 0U, // MINCSDrm + 0U, // MINCSDrr + 0U, // MINCSSrm + 0U, // MINCSSrr + 0U, // MINPDrm + 0U, // MINPDrr + 0U, // MINPSrm + 0U, // MINPSrr + 0U, // MINSDrm + 0U, // MINSDrm_Int + 0U, // MINSDrr + 0U, // MINSDrr_Int + 0U, // MINSSrm + 0U, // MINSSrm_Int + 0U, // MINSSrr + 0U, // MINSSrr_Int + 0U, // MMX_CVTPD2PIirm + 0U, // MMX_CVTPD2PIirr + 0U, // MMX_CVTPI2PDirm + 0U, // MMX_CVTPI2PDirr + 0U, // MMX_CVTPI2PSirm + 0U, // MMX_CVTPI2PSirr + 0U, // MMX_CVTPS2PIirm + 0U, // MMX_CVTPS2PIirr + 0U, // MMX_CVTTPD2PIirm + 0U, // MMX_CVTTPD2PIirr + 0U, // MMX_CVTTPS2PIirm + 0U, // MMX_CVTTPS2PIirr + 0U, // MMX_EMMS + 0U, // MMX_MASKMOVQ + 0U, // MMX_MASKMOVQ64 + 0U, // MMX_MOVD64from64rm + 0U, // MMX_MOVD64from64rr + 0U, // MMX_MOVD64grr + 0U, // MMX_MOVD64mr + 0U, // MMX_MOVD64rm + 0U, // MMX_MOVD64rr + 0U, // MMX_MOVD64to64rm + 0U, // MMX_MOVD64to64rr + 0U, // MMX_MOVDQ2Qrr + 0U, // MMX_MOVFR642Qrr + 0U, // MMX_MOVNTQmr + 0U, // MMX_MOVQ2DQrr + 0U, // MMX_MOVQ2FR64rr + 0U, // MMX_MOVQ64mr + 0U, // MMX_MOVQ64rm + 0U, // MMX_MOVQ64rr + 0U, // MMX_MOVQ64rr_REV + 0U, // MMX_PABSBrm + 0U, // MMX_PABSBrr + 0U, // MMX_PABSDrm + 0U, // MMX_PABSDrr + 0U, // MMX_PABSWrm + 0U, // MMX_PABSWrr + 0U, // MMX_PACKSSDWirm + 0U, // MMX_PACKSSDWirr + 0U, // MMX_PACKSSWBirm + 0U, // MMX_PACKSSWBirr + 0U, // MMX_PACKUSWBirm + 0U, // MMX_PACKUSWBirr + 0U, // MMX_PADDBirm + 0U, // MMX_PADDBirr + 0U, // MMX_PADDDirm + 0U, // MMX_PADDDirr + 0U, // MMX_PADDQirm + 0U, // MMX_PADDQirr + 0U, // MMX_PADDSBirm + 0U, // MMX_PADDSBirr + 0U, // MMX_PADDSWirm + 0U, // MMX_PADDSWirr + 0U, // MMX_PADDUSBirm + 0U, // MMX_PADDUSBirr + 0U, // MMX_PADDUSWirm + 0U, // MMX_PADDUSWirr + 0U, // MMX_PADDWirm + 0U, // MMX_PADDWirr + 192U, // MMX_PALIGNRrmi + 224U, // MMX_PALIGNRrri + 0U, // MMX_PANDNirm + 0U, // MMX_PANDNirr + 0U, // MMX_PANDirm + 0U, // MMX_PANDirr + 0U, // MMX_PAVGBirm + 0U, // MMX_PAVGBirr + 0U, // MMX_PAVGWirm + 0U, // MMX_PAVGWirr + 0U, // MMX_PCMPEQBirm + 0U, // MMX_PCMPEQBirr + 0U, // MMX_PCMPEQDirm + 0U, // MMX_PCMPEQDirr + 0U, // MMX_PCMPEQWirm + 0U, // MMX_PCMPEQWirr + 0U, // MMX_PCMPGTBirm + 0U, // MMX_PCMPGTBirr + 0U, // MMX_PCMPGTDirm + 0U, // MMX_PCMPGTDirr + 0U, // MMX_PCMPGTWirm + 0U, // MMX_PCMPGTWirr + 32U, // MMX_PEXTRWrr + 0U, // MMX_PHADDDrm + 0U, // MMX_PHADDDrr + 0U, // MMX_PHADDSWrm + 0U, // MMX_PHADDSWrr + 0U, // MMX_PHADDWrm + 0U, // MMX_PHADDWrr + 0U, // MMX_PHSUBDrm + 0U, // MMX_PHSUBDrr + 0U, // MMX_PHSUBSWrm + 0U, // MMX_PHSUBSWrr + 0U, // MMX_PHSUBWrm + 0U, // MMX_PHSUBWrr + 192U, // MMX_PINSRWrm + 224U, // MMX_PINSRWrr + 0U, // MMX_PMADDUBSWrm + 0U, // MMX_PMADDUBSWrr + 0U, // MMX_PMADDWDirm + 0U, // MMX_PMADDWDirr + 0U, // MMX_PMAXSWirm + 0U, // MMX_PMAXSWirr + 0U, // MMX_PMAXUBirm + 0U, // MMX_PMAXUBirr + 0U, // MMX_PMINSWirm + 0U, // MMX_PMINSWirr + 0U, // MMX_PMINUBirm + 0U, // MMX_PMINUBirr + 0U, // MMX_PMOVMSKBrr + 0U, // MMX_PMULHRSWrm + 0U, // MMX_PMULHRSWrr + 0U, // MMX_PMULHUWirm + 0U, // MMX_PMULHUWirr + 0U, // MMX_PMULHWirm + 0U, // MMX_PMULHWirr + 0U, // MMX_PMULLWirm + 0U, // MMX_PMULLWirr + 0U, // MMX_PMULUDQirm + 0U, // MMX_PMULUDQirr + 0U, // MMX_PORirm + 0U, // MMX_PORirr + 0U, // MMX_PSADBWirm + 0U, // MMX_PSADBWirr + 0U, // MMX_PSHUFBrm + 0U, // MMX_PSHUFBrr + 0U, // MMX_PSHUFWmi + 32U, // MMX_PSHUFWri + 0U, // MMX_PSIGNBrm + 0U, // MMX_PSIGNBrr + 0U, // MMX_PSIGNDrm + 0U, // MMX_PSIGNDrr + 0U, // MMX_PSIGNWrm + 0U, // MMX_PSIGNWrr + 0U, // MMX_PSLLDri + 0U, // MMX_PSLLDrm + 0U, // MMX_PSLLDrr + 0U, // MMX_PSLLQri + 0U, // MMX_PSLLQrm + 0U, // MMX_PSLLQrr + 0U, // MMX_PSLLWri + 0U, // MMX_PSLLWrm + 0U, // MMX_PSLLWrr + 0U, // MMX_PSRADri + 0U, // MMX_PSRADrm + 0U, // MMX_PSRADrr + 0U, // MMX_PSRAWri + 0U, // MMX_PSRAWrm + 0U, // MMX_PSRAWrr + 0U, // MMX_PSRLDri + 0U, // MMX_PSRLDrm + 0U, // MMX_PSRLDrr + 0U, // MMX_PSRLQri + 0U, // MMX_PSRLQrm + 0U, // MMX_PSRLQrr + 0U, // MMX_PSRLWri + 0U, // MMX_PSRLWrm + 0U, // MMX_PSRLWrr + 0U, // MMX_PSUBBirm + 0U, // MMX_PSUBBirr + 0U, // MMX_PSUBDirm + 0U, // MMX_PSUBDirr + 0U, // MMX_PSUBQirm + 0U, // MMX_PSUBQirr + 0U, // MMX_PSUBSBirm + 0U, // MMX_PSUBSBirr + 0U, // MMX_PSUBSWirm + 0U, // MMX_PSUBSWirr + 0U, // MMX_PSUBUSBirm + 0U, // MMX_PSUBUSBirr + 0U, // MMX_PSUBUSWirm + 0U, // MMX_PSUBUSWirr + 0U, // MMX_PSUBWirm + 0U, // MMX_PSUBWirr + 0U, // MMX_PUNPCKHBWirm + 0U, // MMX_PUNPCKHBWirr + 0U, // MMX_PUNPCKHDQirm + 0U, // MMX_PUNPCKHDQirr + 0U, // MMX_PUNPCKHWDirm + 0U, // MMX_PUNPCKHWDirr + 0U, // MMX_PUNPCKLBWirm + 0U, // MMX_PUNPCKLBWirr + 0U, // MMX_PUNPCKLDQirm + 0U, // MMX_PUNPCKLDQirr + 0U, // MMX_PUNPCKLWDirm + 0U, // MMX_PUNPCKLWDirr + 0U, // MMX_PXORirm + 0U, // MMX_PXORirr + 0U, // MONITORXrrr + 0U, // MONITORrrr + 0U, // MONTMUL + 0U, // MOV16ao16 + 0U, // MOV16ao32 + 0U, // MOV16ao64 + 0U, // MOV16mi + 0U, // MOV16mr + 0U, // MOV16ms + 0U, // MOV16o16a + 0U, // MOV16o32a + 0U, // MOV16o64a + 0U, // MOV16ri + 0U, // MOV16ri_alt + 0U, // MOV16rm + 0U, // MOV16rr + 0U, // MOV16rr_REV + 0U, // MOV16rs + 0U, // MOV16sm + 0U, // MOV16sr + 0U, // MOV32ao16 + 0U, // MOV32ao32 + 0U, // MOV32ao64 + 0U, // MOV32cr + 0U, // MOV32dr + 0U, // MOV32mi + 0U, // MOV32mr + 0U, // MOV32o16a + 0U, // MOV32o32a + 0U, // MOV32o64a + 0U, // MOV32rc + 0U, // MOV32rd + 0U, // MOV32ri + 0U, // MOV32ri_alt + 0U, // MOV32rm + 0U, // MOV32rr + 0U, // MOV32rr_REV + 0U, // MOV32rs + 0U, // MOV32sr + 0U, // MOV64ao32 + 0U, // MOV64ao64 + 0U, // MOV64cr + 0U, // MOV64dr + 0U, // MOV64mi32 + 0U, // MOV64mr + 0U, // MOV64o32a + 0U, // MOV64o64a + 0U, // MOV64rc + 0U, // MOV64rd + 0U, // MOV64ri + 0U, // MOV64ri32 + 0U, // MOV64rm + 0U, // MOV64rr + 0U, // MOV64rr_REV + 0U, // MOV64rs + 0U, // MOV64sr + 0U, // MOV64toPQIrm + 0U, // MOV64toPQIrr + 0U, // MOV64toSDrm + 0U, // MOV64toSDrr + 0U, // MOV8ao16 + 0U, // MOV8ao32 + 0U, // MOV8ao64 + 0U, // MOV8mi + 0U, // MOV8mr + 0U, // MOV8mr_NOREX + 0U, // MOV8o16a + 0U, // MOV8o32a + 0U, // MOV8o64a + 0U, // MOV8ri + 0U, // MOV8ri_alt + 0U, // MOV8rm + 0U, // MOV8rm_NOREX + 0U, // MOV8rr + 0U, // MOV8rr_NOREX + 0U, // MOV8rr_REV + 0U, // MOVAPDmr + 0U, // MOVAPDrm + 0U, // MOVAPDrr + 0U, // MOVAPDrr_REV + 0U, // MOVAPSmr + 0U, // MOVAPSrm + 0U, // MOVAPSrr + 0U, // MOVAPSrr_REV + 0U, // MOVBE16mr + 0U, // MOVBE16rm + 0U, // MOVBE32mr + 0U, // MOVBE32rm + 0U, // MOVBE64mr + 0U, // MOVBE64rm + 0U, // MOVDDUPrm + 0U, // MOVDDUPrr + 0U, // MOVDI2PDIrm + 0U, // MOVDI2PDIrr + 0U, // MOVDI2SSrm + 0U, // MOVDI2SSrr + 0U, // MOVDIR64B16 + 0U, // MOVDIR64B32 + 0U, // MOVDIR64B64 + 0U, // MOVDIRI32 + 0U, // MOVDIRI64 + 0U, // MOVDQAmr + 0U, // MOVDQArm + 0U, // MOVDQArr + 0U, // MOVDQArr_REV + 0U, // MOVDQUmr + 0U, // MOVDQUrm + 0U, // MOVDQUrr + 0U, // MOVDQUrr_REV + 0U, // MOVHLPSrr + 0U, // MOVHPDmr + 0U, // MOVHPDrm + 0U, // MOVHPSmr + 0U, // MOVHPSrm + 0U, // MOVLHPSrr + 0U, // MOVLPDmr + 0U, // MOVLPDrm + 0U, // MOVLPSmr + 0U, // MOVLPSrm + 0U, // MOVMSKPDrr + 0U, // MOVMSKPSrr + 0U, // MOVNTDQArm + 0U, // MOVNTDQmr + 0U, // MOVNTI_64mr + 0U, // MOVNTImr + 0U, // MOVNTPDmr + 0U, // MOVNTPSmr + 0U, // MOVNTSD + 0U, // MOVNTSS + 0U, // MOVPDI2DImr + 0U, // MOVPDI2DIrr + 0U, // MOVPQI2QImr + 0U, // MOVPQI2QIrr + 0U, // MOVPQIto64mr + 0U, // MOVPQIto64rr + 0U, // MOVQI2PQIrm + 0U, // MOVSB + 0U, // MOVSDmr + 0U, // MOVSDrm + 0U, // MOVSDrr + 0U, // MOVSDrr_REV + 0U, // MOVSDto64mr + 0U, // MOVSDto64rr + 0U, // MOVSHDUPrm + 0U, // MOVSHDUPrr + 0U, // MOVSL + 0U, // MOVSLDUPrm + 0U, // MOVSLDUPrr + 0U, // MOVSQ + 0U, // MOVSS2DImr + 0U, // MOVSS2DIrr + 0U, // MOVSSmr + 0U, // MOVSSrm + 0U, // MOVSSrr + 0U, // MOVSSrr_REV + 0U, // MOVSW + 0U, // MOVSX16rm16 + 0U, // MOVSX16rm8 + 0U, // MOVSX16rr16 + 0U, // MOVSX16rr8 + 0U, // MOVSX32rm16 + 0U, // MOVSX32rm8 + 0U, // MOVSX32rm8_NOREX + 0U, // MOVSX32rr16 + 0U, // MOVSX32rr8 + 0U, // MOVSX32rr8_NOREX + 0U, // MOVSX64rm16 + 0U, // MOVSX64rm32 + 0U, // MOVSX64rm8 + 0U, // MOVSX64rr16 + 0U, // MOVSX64rr32 + 0U, // MOVSX64rr8 + 0U, // MOVUPDmr + 0U, // MOVUPDrm + 0U, // MOVUPDrr + 0U, // MOVUPDrr_REV + 0U, // MOVUPSmr + 0U, // MOVUPSrm + 0U, // MOVUPSrr + 0U, // MOVUPSrr_REV + 0U, // MOVZPQILo2PQIrr + 0U, // MOVZX16rm16 + 0U, // MOVZX16rm8 + 0U, // MOVZX16rr16 + 0U, // MOVZX16rr8 + 0U, // MOVZX32rm16 + 0U, // MOVZX32rm8 + 0U, // MOVZX32rm8_NOREX + 0U, // MOVZX32rr16 + 0U, // MOVZX32rr8 + 0U, // MOVZX32rr8_NOREX + 0U, // MOVZX64rm16 + 0U, // MOVZX64rm8 + 0U, // MOVZX64rr16 + 0U, // MOVZX64rr8 + 192U, // MPSADBWrmi + 224U, // MPSADBWrri + 0U, // MUL16m + 0U, // MUL16r + 0U, // MUL32m + 0U, // MUL32r + 0U, // MUL64m + 0U, // MUL64r + 0U, // MUL8m + 0U, // MUL8r + 0U, // MULPDrm + 0U, // MULPDrr + 0U, // MULPSrm + 0U, // MULPSrr + 0U, // MULSDrm + 0U, // MULSDrm_Int + 0U, // MULSDrr + 0U, // MULSDrr_Int + 0U, // MULSSrm + 0U, // MULSSrm_Int + 0U, // MULSSrr + 0U, // MULSSrr_Int + 64U, // MULX32rm + 96U, // MULX32rr + 128U, // MULX64rm + 96U, // MULX64rr + 0U, // MUL_F32m + 0U, // MUL_F64m + 0U, // MUL_FI16m + 0U, // MUL_FI32m + 0U, // MUL_FPrST0 + 0U, // MUL_FST0r + 0U, // MUL_Fp32 + 0U, // MUL_Fp32m + 0U, // MUL_Fp64 + 0U, // MUL_Fp64m + 0U, // MUL_Fp64m32 + 0U, // MUL_Fp80 + 0U, // MUL_Fp80m32 + 0U, // MUL_Fp80m64 + 0U, // MUL_FpI16m32 + 0U, // MUL_FpI16m64 + 0U, // MUL_FpI16m80 + 0U, // MUL_FpI32m32 + 0U, // MUL_FpI32m64 + 0U, // MUL_FpI32m80 + 0U, // MUL_FrST0 + 0U, // MWAITXrrr + 0U, // MWAITrr + 0U, // NEG16m + 0U, // NEG16r + 0U, // NEG32m + 0U, // NEG32r + 0U, // NEG64m + 0U, // NEG64r + 0U, // NEG8m + 0U, // NEG8r + 0U, // NOOP + 0U, // NOOP18_16m4 + 0U, // NOOP18_16m5 + 0U, // NOOP18_16m6 + 0U, // NOOP18_16m7 + 0U, // NOOP18_16r4 + 0U, // NOOP18_16r5 + 0U, // NOOP18_16r6 + 0U, // NOOP18_16r7 + 0U, // NOOP18_m4 + 0U, // NOOP18_m5 + 0U, // NOOP18_m6 + 0U, // NOOP18_m7 + 0U, // NOOP18_r4 + 0U, // NOOP18_r5 + 0U, // NOOP18_r6 + 0U, // NOOP18_r7 + 0U, // NOOP19rr + 0U, // NOOPL + 0U, // NOOPL_19 + 0U, // NOOPL_1d + 0U, // NOOPL_1e + 0U, // NOOPLr + 0U, // NOOPQ + 0U, // NOOPQr + 0U, // NOOPW + 0U, // NOOPW_19 + 0U, // NOOPW_1c + 0U, // NOOPW_1d + 0U, // NOOPW_1e + 0U, // NOOPWr + 0U, // NOT16m + 0U, // NOT16r + 0U, // NOT32m + 0U, // NOT32r + 0U, // NOT64m + 0U, // NOT64r + 0U, // NOT8m + 0U, // NOT8r + 0U, // OR16i16 + 0U, // OR16mi + 0U, // OR16mi8 + 0U, // OR16mr + 0U, // OR16ri + 0U, // OR16ri8 + 0U, // OR16rm + 0U, // OR16rr + 0U, // OR16rr_REV + 0U, // OR32i32 + 0U, // OR32mi + 0U, // OR32mi8 + 0U, // OR32mr + 0U, // OR32ri + 0U, // OR32ri8 + 0U, // OR32rm + 0U, // OR32rr + 0U, // OR32rr_REV + 0U, // OR64i32 + 0U, // OR64mi32 + 0U, // OR64mi8 + 0U, // OR64mr + 0U, // OR64ri32 + 0U, // OR64ri8 + 0U, // OR64rm + 0U, // OR64rr + 0U, // OR64rr_REV + 0U, // OR8i8 + 0U, // OR8mi + 0U, // OR8mi8 + 0U, // OR8mr + 0U, // OR8ri + 0U, // OR8ri8 + 0U, // OR8rm + 0U, // OR8rr + 0U, // OR8rr_REV + 0U, // ORPDrm + 0U, // ORPDrr + 0U, // ORPSrm + 0U, // ORPSrr + 0U, // OUT16ir + 0U, // OUT16rr + 0U, // OUT32ir + 0U, // OUT32rr + 0U, // OUT8ir + 0U, // OUT8rr + 0U, // OUTSB + 0U, // OUTSL + 0U, // OUTSW + 0U, // PABSBrm + 0U, // PABSBrr + 0U, // PABSDrm + 0U, // PABSDrr + 0U, // PABSWrm + 0U, // PABSWrr + 0U, // PACKSSDWrm + 0U, // PACKSSDWrr + 0U, // PACKSSWBrm + 0U, // PACKSSWBrr + 0U, // PACKUSDWrm + 0U, // PACKUSDWrr + 0U, // PACKUSWBrm + 0U, // PACKUSWBrr + 0U, // PADDBrm + 0U, // PADDBrr + 0U, // PADDDrm + 0U, // PADDDrr + 0U, // PADDQrm + 0U, // PADDQrr + 0U, // PADDSBrm + 0U, // PADDSBrr + 0U, // PADDSWrm + 0U, // PADDSWrr + 0U, // PADDUSBrm + 0U, // PADDUSBrr + 0U, // PADDUSWrm + 0U, // PADDUSWrr + 0U, // PADDWrm + 0U, // PADDWrr + 192U, // PALIGNRrmi + 224U, // PALIGNRrri + 0U, // PANDNrm + 0U, // PANDNrr + 0U, // PANDrm + 0U, // PANDrr + 0U, // PAUSE + 0U, // PAVGBrm + 0U, // PAVGBrr + 0U, // PAVGUSBrm + 0U, // PAVGUSBrr + 0U, // PAVGWrm + 0U, // PAVGWrr + 1U, // PBLENDVBrm0 + 1U, // PBLENDVBrr0 + 192U, // PBLENDWrmi + 224U, // PBLENDWrri + 192U, // PCLMULQDQrm + 224U, // PCLMULQDQrr + 0U, // PCMPEQBrm + 0U, // PCMPEQBrr + 0U, // PCMPEQDrm + 0U, // PCMPEQDrr + 0U, // PCMPEQQrm + 0U, // PCMPEQQrr + 0U, // PCMPEQWrm + 0U, // PCMPEQWrr + 0U, // PCMPESTRIrm + 32U, // PCMPESTRIrr + 0U, // PCMPESTRMrm + 32U, // PCMPESTRMrr + 0U, // PCMPGTBrm + 0U, // PCMPGTBrr + 0U, // PCMPGTDrm + 0U, // PCMPGTDrr + 0U, // PCMPGTQrm + 0U, // PCMPGTQrr + 0U, // PCMPGTWrm + 0U, // PCMPGTWrr + 0U, // PCMPISTRIrm + 32U, // PCMPISTRIrr + 0U, // PCMPISTRMrm + 32U, // PCMPISTRMrr + 0U, // PCONFIG + 64U, // PDEP32rm + 96U, // PDEP32rr + 128U, // PDEP64rm + 96U, // PDEP64rr + 64U, // PEXT32rm + 96U, // PEXT32rr + 128U, // PEXT64rm + 96U, // PEXT64rr + 0U, // PEXTRBmr + 32U, // PEXTRBrr + 0U, // PEXTRDmr + 32U, // PEXTRDrr + 0U, // PEXTRQmr + 32U, // PEXTRQrr + 0U, // PEXTRWmr + 32U, // PEXTRWrr + 32U, // PEXTRWrr_REV + 0U, // PF2IDrm + 0U, // PF2IDrr + 0U, // PF2IWrm + 0U, // PF2IWrr + 0U, // PFACCrm + 0U, // PFACCrr + 0U, // PFADDrm + 0U, // PFADDrr + 0U, // PFCMPEQrm + 0U, // PFCMPEQrr + 0U, // PFCMPGErm + 0U, // PFCMPGErr + 0U, // PFCMPGTrm + 0U, // PFCMPGTrr + 0U, // PFMAXrm + 0U, // PFMAXrr + 0U, // PFMINrm + 0U, // PFMINrr + 0U, // PFMULrm + 0U, // PFMULrr + 0U, // PFNACCrm + 0U, // PFNACCrr + 0U, // PFPNACCrm + 0U, // PFPNACCrr + 0U, // PFRCPIT1rm + 0U, // PFRCPIT1rr + 0U, // PFRCPIT2rm + 0U, // PFRCPIT2rr + 0U, // PFRCPrm + 0U, // PFRCPrr + 0U, // PFRSQIT1rm + 0U, // PFRSQIT1rr + 0U, // PFRSQRTrm + 0U, // PFRSQRTrr + 0U, // PFSUBRrm + 0U, // PFSUBRrr + 0U, // PFSUBrm + 0U, // PFSUBrr + 0U, // PHADDDrm + 0U, // PHADDDrr + 0U, // PHADDSWrm + 0U, // PHADDSWrr + 0U, // PHADDWrm + 0U, // PHADDWrr + 0U, // PHMINPOSUWrm + 0U, // PHMINPOSUWrr + 0U, // PHSUBDrm + 0U, // PHSUBDrr + 0U, // PHSUBSWrm + 0U, // PHSUBSWrr + 0U, // PHSUBWrm + 0U, // PHSUBWrr + 0U, // PI2FDrm + 0U, // PI2FDrr + 0U, // PI2FWrm + 0U, // PI2FWrr + 192U, // PINSRBrm + 224U, // PINSRBrr + 192U, // PINSRDrm + 224U, // PINSRDrr + 192U, // PINSRQrm + 224U, // PINSRQrr + 192U, // PINSRWrm + 224U, // PINSRWrr + 0U, // PMADDUBSWrm + 0U, // PMADDUBSWrr + 0U, // PMADDWDrm + 0U, // PMADDWDrr + 0U, // PMAXSBrm + 0U, // PMAXSBrr + 0U, // PMAXSDrm + 0U, // PMAXSDrr + 0U, // PMAXSWrm + 0U, // PMAXSWrr + 0U, // PMAXUBrm + 0U, // PMAXUBrr + 0U, // PMAXUDrm + 0U, // PMAXUDrr + 0U, // PMAXUWrm + 0U, // PMAXUWrr + 0U, // PMINSBrm + 0U, // PMINSBrr + 0U, // PMINSDrm + 0U, // PMINSDrr + 0U, // PMINSWrm + 0U, // PMINSWrr + 0U, // PMINUBrm + 0U, // PMINUBrr + 0U, // PMINUDrm + 0U, // PMINUDrr + 0U, // PMINUWrm + 0U, // PMINUWrr + 0U, // PMOVMSKBrr + 0U, // PMOVSXBDrm + 0U, // PMOVSXBDrr + 0U, // PMOVSXBQrm + 0U, // PMOVSXBQrr + 0U, // PMOVSXBWrm + 0U, // PMOVSXBWrr + 0U, // PMOVSXDQrm + 0U, // PMOVSXDQrr + 0U, // PMOVSXWDrm + 0U, // PMOVSXWDrr + 0U, // PMOVSXWQrm + 0U, // PMOVSXWQrr + 0U, // PMOVZXBDrm + 0U, // PMOVZXBDrr + 0U, // PMOVZXBQrm + 0U, // PMOVZXBQrr + 0U, // PMOVZXBWrm + 0U, // PMOVZXBWrr + 0U, // PMOVZXDQrm + 0U, // PMOVZXDQrr + 0U, // PMOVZXWDrm + 0U, // PMOVZXWDrr + 0U, // PMOVZXWQrm + 0U, // PMOVZXWQrr + 0U, // PMULDQrm + 0U, // PMULDQrr + 0U, // PMULHRSWrm + 0U, // PMULHRSWrr + 0U, // PMULHRWrm + 0U, // PMULHRWrr + 0U, // PMULHUWrm + 0U, // PMULHUWrr + 0U, // PMULHWrm + 0U, // PMULHWrr + 0U, // PMULLDrm + 0U, // PMULLDrr + 0U, // PMULLWrm + 0U, // PMULLWrr + 0U, // PMULUDQrm + 0U, // PMULUDQrr + 0U, // POP16r + 0U, // POP16rmm + 0U, // POP16rmr + 0U, // POP32r + 0U, // POP32rmm + 0U, // POP32rmr + 0U, // POP64r + 0U, // POP64rmm + 0U, // POP64rmr + 0U, // POPA16 + 0U, // POPA32 + 0U, // POPCNT16rm + 0U, // POPCNT16rr + 0U, // POPCNT32rm + 0U, // POPCNT32rr + 0U, // POPCNT64rm + 0U, // POPCNT64rr + 0U, // POPDS16 + 0U, // POPDS32 + 0U, // POPES16 + 0U, // POPES32 + 0U, // POPF16 + 0U, // POPF32 + 0U, // POPF64 + 0U, // POPFS16 + 0U, // POPFS32 + 0U, // POPFS64 + 0U, // POPGS16 + 0U, // POPGS32 + 0U, // POPGS64 + 0U, // POPSS16 + 0U, // POPSS32 + 0U, // PORrm + 0U, // PORrr + 0U, // PREFETCH + 0U, // PREFETCHNTA + 0U, // PREFETCHT0 + 0U, // PREFETCHT1 + 0U, // PREFETCHT2 + 0U, // PREFETCHW + 0U, // PREFETCHWT1 + 0U, // PSADBWrm + 0U, // PSADBWrr + 0U, // PSHUFBrm + 0U, // PSHUFBrr + 0U, // PSHUFDmi + 32U, // PSHUFDri + 0U, // PSHUFHWmi + 32U, // PSHUFHWri + 0U, // PSHUFLWmi + 32U, // PSHUFLWri + 0U, // PSIGNBrm + 0U, // PSIGNBrr + 0U, // PSIGNDrm + 0U, // PSIGNDrr + 0U, // PSIGNWrm + 0U, // PSIGNWrr + 0U, // PSLLDQri + 0U, // PSLLDri + 0U, // PSLLDrm + 0U, // PSLLDrr + 0U, // PSLLQri + 0U, // PSLLQrm + 0U, // PSLLQrr + 0U, // PSLLWri + 0U, // PSLLWrm + 0U, // PSLLWrr + 0U, // PSRADri + 0U, // PSRADrm + 0U, // PSRADrr + 0U, // PSRAWri + 0U, // PSRAWrm + 0U, // PSRAWrr + 0U, // PSRLDQri + 0U, // PSRLDri + 0U, // PSRLDrm + 0U, // PSRLDrr + 0U, // PSRLQri + 0U, // PSRLQrm + 0U, // PSRLQrr + 0U, // PSRLWri + 0U, // PSRLWrm + 0U, // PSRLWrr + 0U, // PSUBBrm + 0U, // PSUBBrr + 0U, // PSUBDrm + 0U, // PSUBDrr + 0U, // PSUBQrm + 0U, // PSUBQrr + 0U, // PSUBSBrm + 0U, // PSUBSBrr + 0U, // PSUBSWrm + 0U, // PSUBSWrr + 0U, // PSUBUSBrm + 0U, // PSUBUSBrr + 0U, // PSUBUSWrm + 0U, // PSUBUSWrr + 0U, // PSUBWrm + 0U, // PSUBWrr + 0U, // PSWAPDrm + 0U, // PSWAPDrr + 0U, // PTESTrm + 0U, // PTESTrr + 0U, // PTWRITE64m + 0U, // PTWRITE64r + 0U, // PTWRITEm + 0U, // PTWRITEr + 0U, // PUNPCKHBWrm + 0U, // PUNPCKHBWrr + 0U, // PUNPCKHDQrm + 0U, // PUNPCKHDQrr + 0U, // PUNPCKHQDQrm + 0U, // PUNPCKHQDQrr + 0U, // PUNPCKHWDrm + 0U, // PUNPCKHWDrr + 0U, // PUNPCKLBWrm + 0U, // PUNPCKLBWrr + 0U, // PUNPCKLDQrm + 0U, // PUNPCKLDQrr + 0U, // PUNPCKLQDQrm + 0U, // PUNPCKLQDQrr + 0U, // PUNPCKLWDrm + 0U, // PUNPCKLWDrr + 0U, // PUSH16i8 + 0U, // PUSH16r + 0U, // PUSH16rmm + 0U, // PUSH16rmr + 0U, // PUSH32i8 + 0U, // PUSH32r + 0U, // PUSH32rmm + 0U, // PUSH32rmr + 0U, // PUSH64i32 + 0U, // PUSH64i8 + 0U, // PUSH64r + 0U, // PUSH64rmm + 0U, // PUSH64rmr + 0U, // PUSHA16 + 0U, // PUSHA32 + 0U, // PUSHCS16 + 0U, // PUSHCS32 + 0U, // PUSHDS16 + 0U, // PUSHDS32 + 0U, // PUSHES16 + 0U, // PUSHES32 + 0U, // PUSHF16 + 0U, // PUSHF32 + 0U, // PUSHF64 + 0U, // PUSHFS16 + 0U, // PUSHFS32 + 0U, // PUSHFS64 + 0U, // PUSHGS16 + 0U, // PUSHGS32 + 0U, // PUSHGS64 + 0U, // PUSHSS16 + 0U, // PUSHSS32 + 0U, // PUSHi16 + 0U, // PUSHi32 + 0U, // PXORrm + 0U, // PXORrr + 0U, // RCL16m1 + 0U, // RCL16mCL + 0U, // RCL16mi + 0U, // RCL16r1 + 0U, // RCL16rCL + 0U, // RCL16ri + 0U, // RCL32m1 + 0U, // RCL32mCL + 0U, // RCL32mi + 0U, // RCL32r1 + 0U, // RCL32rCL + 0U, // RCL32ri + 0U, // RCL64m1 + 0U, // RCL64mCL + 0U, // RCL64mi + 0U, // RCL64r1 + 0U, // RCL64rCL + 0U, // RCL64ri + 0U, // RCL8m1 + 0U, // RCL8mCL + 0U, // RCL8mi + 0U, // RCL8r1 + 0U, // RCL8rCL + 0U, // RCL8ri + 0U, // RCPPSm + 0U, // RCPPSr + 0U, // RCPSSm + 0U, // RCPSSm_Int + 0U, // RCPSSr + 0U, // RCPSSr_Int + 0U, // RCR16m1 + 0U, // RCR16mCL + 0U, // RCR16mi + 0U, // RCR16r1 + 0U, // RCR16rCL + 0U, // RCR16ri + 0U, // RCR32m1 + 0U, // RCR32mCL + 0U, // RCR32mi + 0U, // RCR32r1 + 0U, // RCR32rCL + 0U, // RCR32ri + 0U, // RCR64m1 + 0U, // RCR64mCL + 0U, // RCR64mi + 0U, // RCR64r1 + 0U, // RCR64rCL + 0U, // RCR64ri + 0U, // RCR8m1 + 0U, // RCR8mCL + 0U, // RCR8mi + 0U, // RCR8r1 + 0U, // RCR8rCL + 0U, // RCR8ri + 0U, // RDFSBASE + 0U, // RDFSBASE64 + 0U, // RDGSBASE + 0U, // RDGSBASE64 + 0U, // RDMSR + 0U, // RDPID32 + 0U, // RDPID64 + 0U, // RDPKRUr + 0U, // RDPMC + 0U, // RDRAND16r + 0U, // RDRAND32r + 0U, // RDRAND64r + 0U, // RDSEED16r + 0U, // RDSEED32r + 0U, // RDSEED64r + 0U, // RDSSPD + 0U, // RDSSPQ + 0U, // RDTSC + 0U, // RDTSCP + 0U, // REPNE_PREFIX + 0U, // REP_PREFIX + 0U, // RETIL + 0U, // RETIQ + 0U, // RETIW + 0U, // RETL + 0U, // RETQ + 0U, // RETW + 0U, // REX64_PREFIX + 0U, // ROL16m1 + 0U, // ROL16mCL + 0U, // ROL16mi + 0U, // ROL16r1 + 0U, // ROL16rCL + 0U, // ROL16ri + 0U, // ROL32m1 + 0U, // ROL32mCL + 0U, // ROL32mi + 0U, // ROL32r1 + 0U, // ROL32rCL + 0U, // ROL32ri + 0U, // ROL64m1 + 0U, // ROL64mCL + 0U, // ROL64mi + 0U, // ROL64r1 + 0U, // ROL64rCL + 0U, // ROL64ri + 0U, // ROL8m1 + 0U, // ROL8mCL + 0U, // ROL8mi + 0U, // ROL8r1 + 0U, // ROL8rCL + 0U, // ROL8ri + 0U, // ROR16m1 + 0U, // ROR16mCL + 0U, // ROR16mi + 0U, // ROR16r1 + 0U, // ROR16rCL + 0U, // ROR16ri + 0U, // ROR32m1 + 0U, // ROR32mCL + 0U, // ROR32mi + 0U, // ROR32r1 + 0U, // ROR32rCL + 0U, // ROR32ri + 0U, // ROR64m1 + 0U, // ROR64mCL + 0U, // ROR64mi + 0U, // ROR64r1 + 0U, // ROR64rCL + 0U, // ROR64ri + 0U, // ROR8m1 + 0U, // ROR8mCL + 0U, // ROR8mi + 0U, // ROR8r1 + 0U, // ROR8rCL + 0U, // ROR8ri + 0U, // RORX32mi + 32U, // RORX32ri + 0U, // RORX64mi + 32U, // RORX64ri + 0U, // ROUNDPDm + 32U, // ROUNDPDr + 0U, // ROUNDPSm + 32U, // ROUNDPSr + 0U, // ROUNDSDm + 192U, // ROUNDSDm_Int + 32U, // ROUNDSDr + 224U, // ROUNDSDr_Int + 0U, // ROUNDSSm + 192U, // ROUNDSSm_Int + 32U, // ROUNDSSr + 224U, // ROUNDSSr_Int + 0U, // RSM + 0U, // RSQRTPSm + 0U, // RSQRTPSr + 0U, // RSQRTSSm + 0U, // RSQRTSSm_Int + 0U, // RSQRTSSr + 0U, // RSQRTSSr_Int + 0U, // RSTORSSP + 0U, // SAHF + 0U, // SAL16m1 + 0U, // SAL16mCL + 0U, // SAL16mi + 0U, // SAL16r1 + 0U, // SAL16rCL + 0U, // SAL16ri + 0U, // SAL32m1 + 0U, // SAL32mCL + 0U, // SAL32mi + 0U, // SAL32r1 + 0U, // SAL32rCL + 0U, // SAL32ri + 0U, // SAL64m1 + 0U, // SAL64mCL + 0U, // SAL64mi + 0U, // SAL64r1 + 0U, // SAL64rCL + 0U, // SAL64ri + 0U, // SAL8m1 + 0U, // SAL8mCL + 0U, // SAL8mi + 0U, // SAL8r1 + 0U, // SAL8rCL + 0U, // SAL8ri + 0U, // SALC + 0U, // SAR16m1 + 0U, // SAR16mCL + 0U, // SAR16mi + 0U, // SAR16r1 + 0U, // SAR16rCL + 0U, // SAR16ri + 0U, // SAR32m1 + 0U, // SAR32mCL + 0U, // SAR32mi + 0U, // SAR32r1 + 0U, // SAR32rCL + 0U, // SAR32ri + 0U, // SAR64m1 + 0U, // SAR64mCL + 0U, // SAR64mi + 0U, // SAR64r1 + 0U, // SAR64rCL + 0U, // SAR64ri + 0U, // SAR8m1 + 0U, // SAR8mCL + 0U, // SAR8mi + 0U, // SAR8r1 + 0U, // SAR8rCL + 0U, // SAR8ri + 160U, // SARX32rm + 96U, // SARX32rr + 160U, // SARX64rm + 96U, // SARX64rr + 0U, // SAVEPREVSSP + 0U, // SBB16i16 + 0U, // SBB16mi + 0U, // SBB16mi8 + 0U, // SBB16mr + 0U, // SBB16ri + 0U, // SBB16ri8 + 0U, // SBB16rm + 0U, // SBB16rr + 0U, // SBB16rr_REV + 0U, // SBB32i32 + 0U, // SBB32mi + 0U, // SBB32mi8 + 0U, // SBB32mr + 0U, // SBB32ri + 0U, // SBB32ri8 + 0U, // SBB32rm + 0U, // SBB32rr + 0U, // SBB32rr_REV + 0U, // SBB64i32 + 0U, // SBB64mi32 + 0U, // SBB64mi8 + 0U, // SBB64mr + 0U, // SBB64ri32 + 0U, // SBB64ri8 + 0U, // SBB64rm + 0U, // SBB64rr + 0U, // SBB64rr_REV + 0U, // SBB8i8 + 0U, // SBB8mi + 0U, // SBB8mi8 + 0U, // SBB8mr + 0U, // SBB8ri + 0U, // SBB8ri8 + 0U, // SBB8rm + 0U, // SBB8rr + 0U, // SBB8rr_REV + 0U, // SCASB + 0U, // SCASL + 0U, // SCASQ + 0U, // SCASW + 0U, // SETAEm + 0U, // SETAEr + 0U, // SETAm + 0U, // SETAr + 0U, // SETBEm + 0U, // SETBEr + 0U, // SETBm + 0U, // SETBr + 0U, // SETEm + 0U, // SETEr + 0U, // SETGEm + 0U, // SETGEr + 0U, // SETGm + 0U, // SETGr + 0U, // SETLEm + 0U, // SETLEr + 0U, // SETLm + 0U, // SETLr + 0U, // SETNEm + 0U, // SETNEr + 0U, // SETNOm + 0U, // SETNOr + 0U, // SETNPm + 0U, // SETNPr + 0U, // SETNSm + 0U, // SETNSr + 0U, // SETOm + 0U, // SETOr + 0U, // SETPm + 0U, // SETPr + 0U, // SETSSBSY + 0U, // SETSm + 0U, // SETSr + 0U, // SFENCE + 0U, // SGDT16m + 0U, // SGDT32m + 0U, // SGDT64m + 0U, // SHA1MSG1rm + 0U, // SHA1MSG1rr + 0U, // SHA1MSG2rm + 0U, // SHA1MSG2rr + 0U, // SHA1NEXTErm + 0U, // SHA1NEXTErr + 192U, // SHA1RNDS4rmi + 224U, // SHA1RNDS4rri + 0U, // SHA256MSG1rm + 0U, // SHA256MSG1rr + 0U, // SHA256MSG2rm + 0U, // SHA256MSG2rr + 1U, // SHA256RNDS2rm + 1U, // SHA256RNDS2rr + 0U, // SHL16m1 + 0U, // SHL16mCL + 0U, // SHL16mi + 0U, // SHL16r1 + 0U, // SHL16rCL + 0U, // SHL16ri + 0U, // SHL32m1 + 0U, // SHL32mCL + 0U, // SHL32mi + 0U, // SHL32r1 + 0U, // SHL32rCL + 0U, // SHL32ri + 0U, // SHL64m1 + 0U, // SHL64mCL + 0U, // SHL64mi + 0U, // SHL64r1 + 0U, // SHL64rCL + 0U, // SHL64ri + 0U, // SHL8m1 + 0U, // SHL8mCL + 0U, // SHL8mi + 0U, // SHL8r1 + 0U, // SHL8rCL + 0U, // SHL8ri + 3U, // SHLD16mrCL + 0U, // SHLD16mri8 + 3U, // SHLD16rrCL + 224U, // SHLD16rri8 + 3U, // SHLD32mrCL + 0U, // SHLD32mri8 + 3U, // SHLD32rrCL + 224U, // SHLD32rri8 + 3U, // SHLD64mrCL + 0U, // SHLD64mri8 + 3U, // SHLD64rrCL + 224U, // SHLD64rri8 + 160U, // SHLX32rm + 96U, // SHLX32rr + 160U, // SHLX64rm + 96U, // SHLX64rr + 0U, // SHR16m1 + 0U, // SHR16mCL + 0U, // SHR16mi + 0U, // SHR16r1 + 0U, // SHR16rCL + 0U, // SHR16ri + 0U, // SHR32m1 + 0U, // SHR32mCL + 0U, // SHR32mi + 0U, // SHR32r1 + 0U, // SHR32rCL + 0U, // SHR32ri + 0U, // SHR64m1 + 0U, // SHR64mCL + 0U, // SHR64mi + 0U, // SHR64r1 + 0U, // SHR64rCL + 0U, // SHR64ri + 0U, // SHR8m1 + 0U, // SHR8mCL + 0U, // SHR8mi + 0U, // SHR8r1 + 0U, // SHR8rCL + 0U, // SHR8ri + 3U, // SHRD16mrCL + 0U, // SHRD16mri8 + 3U, // SHRD16rrCL + 224U, // SHRD16rri8 + 3U, // SHRD32mrCL + 0U, // SHRD32mri8 + 3U, // SHRD32rrCL + 224U, // SHRD32rri8 + 3U, // SHRD64mrCL + 0U, // SHRD64mri8 + 3U, // SHRD64rrCL + 224U, // SHRD64rri8 + 160U, // SHRX32rm + 96U, // SHRX32rr + 160U, // SHRX64rm + 96U, // SHRX64rr + 192U, // SHUFPDrmi + 224U, // SHUFPDrri + 192U, // SHUFPSrmi + 224U, // SHUFPSrri + 0U, // SIDT16m + 0U, // SIDT32m + 0U, // SIDT64m + 0U, // SIN_F + 0U, // SIN_Fp32 + 0U, // SIN_Fp64 + 0U, // SIN_Fp80 + 0U, // SKINIT + 0U, // SLDT16m + 0U, // SLDT16r + 0U, // SLDT32r + 0U, // SLDT64r + 0U, // SLWPCB + 0U, // SLWPCB64 + 0U, // SMSW16m + 0U, // SMSW16r + 0U, // SMSW32r + 0U, // SMSW64r + 0U, // SQRTPDm + 0U, // SQRTPDr + 0U, // SQRTPSm + 0U, // SQRTPSr + 0U, // SQRTSDm + 0U, // SQRTSDm_Int + 0U, // SQRTSDr + 0U, // SQRTSDr_Int + 0U, // SQRTSSm + 0U, // SQRTSSm_Int + 0U, // SQRTSSr + 0U, // SQRTSSr_Int + 0U, // SQRT_F + 0U, // SQRT_Fp32 + 0U, // SQRT_Fp64 + 0U, // SQRT_Fp80 + 0U, // STAC + 0U, // STC + 0U, // STD + 0U, // STGI + 0U, // STI + 0U, // STMXCSR + 0U, // STOSB + 0U, // STOSL + 0U, // STOSQ + 0U, // STOSW + 0U, // STR16r + 0U, // STR32r + 0U, // STR64r + 0U, // STRm + 0U, // ST_F32m + 0U, // ST_F64m + 0U, // ST_FP32m + 0U, // ST_FP64m + 0U, // ST_FP80m + 0U, // ST_FPrr + 0U, // ST_Fp32m + 0U, // ST_Fp64m + 0U, // ST_Fp64m32 + 0U, // ST_Fp80m32 + 0U, // ST_Fp80m64 + 0U, // ST_FpP32m + 0U, // ST_FpP64m + 0U, // ST_FpP64m32 + 0U, // ST_FpP80m + 0U, // ST_FpP80m32 + 0U, // ST_FpP80m64 + 0U, // ST_Frr + 0U, // SUB16i16 + 0U, // SUB16mi + 0U, // SUB16mi8 + 0U, // SUB16mr + 0U, // SUB16ri + 0U, // SUB16ri8 + 0U, // SUB16rm + 0U, // SUB16rr + 0U, // SUB16rr_REV + 0U, // SUB32i32 + 0U, // SUB32mi + 0U, // SUB32mi8 + 0U, // SUB32mr + 0U, // SUB32ri + 0U, // SUB32ri8 + 0U, // SUB32rm + 0U, // SUB32rr + 0U, // SUB32rr_REV + 0U, // SUB64i32 + 0U, // SUB64mi32 + 0U, // SUB64mi8 + 0U, // SUB64mr + 0U, // SUB64ri32 + 0U, // SUB64ri8 + 0U, // SUB64rm + 0U, // SUB64rr + 0U, // SUB64rr_REV + 0U, // SUB8i8 + 0U, // SUB8mi + 0U, // SUB8mi8 + 0U, // SUB8mr + 0U, // SUB8ri + 0U, // SUB8ri8 + 0U, // SUB8rm + 0U, // SUB8rr + 0U, // SUB8rr_REV + 0U, // SUBPDrm + 0U, // SUBPDrr + 0U, // SUBPSrm + 0U, // SUBPSrr + 0U, // SUBR_F32m + 0U, // SUBR_F64m + 0U, // SUBR_FI16m + 0U, // SUBR_FI32m + 0U, // SUBR_FPrST0 + 0U, // SUBR_FST0r + 0U, // SUBR_Fp32m + 0U, // SUBR_Fp64m + 0U, // SUBR_Fp64m32 + 0U, // SUBR_Fp80m32 + 0U, // SUBR_Fp80m64 + 0U, // SUBR_FpI16m32 + 0U, // SUBR_FpI16m64 + 0U, // SUBR_FpI16m80 + 0U, // SUBR_FpI32m32 + 0U, // SUBR_FpI32m64 + 0U, // SUBR_FpI32m80 + 0U, // SUBR_FrST0 + 0U, // SUBSDrm + 0U, // SUBSDrm_Int + 0U, // SUBSDrr + 0U, // SUBSDrr_Int + 0U, // SUBSSrm + 0U, // SUBSSrm_Int + 0U, // SUBSSrr + 0U, // SUBSSrr_Int + 0U, // SUB_F32m + 0U, // SUB_F64m + 0U, // SUB_FI16m + 0U, // SUB_FI32m + 0U, // SUB_FPrST0 + 0U, // SUB_FST0r + 0U, // SUB_Fp32 + 0U, // SUB_Fp32m + 0U, // SUB_Fp64 + 0U, // SUB_Fp64m + 0U, // SUB_Fp64m32 + 0U, // SUB_Fp80 + 0U, // SUB_Fp80m32 + 0U, // SUB_Fp80m64 + 0U, // SUB_FpI16m32 + 0U, // SUB_FpI16m64 + 0U, // SUB_FpI16m80 + 0U, // SUB_FpI32m32 + 0U, // SUB_FpI32m64 + 0U, // SUB_FpI32m80 + 0U, // SUB_FrST0 + 0U, // SWAPGS + 0U, // SYSCALL + 0U, // SYSENTER + 0U, // SYSEXIT + 0U, // SYSEXIT64 + 0U, // SYSRET + 0U, // SYSRET64 + 0U, // T1MSKC32rm + 0U, // T1MSKC32rr + 0U, // T1MSKC64rm + 0U, // T1MSKC64rr + 0U, // TEST16i16 + 0U, // TEST16mi + 0U, // TEST16mi_alt + 0U, // TEST16mr + 0U, // TEST16ri + 0U, // TEST16ri_alt + 0U, // TEST16rr + 0U, // TEST32i32 + 0U, // TEST32mi + 0U, // TEST32mi_alt + 0U, // TEST32mr + 0U, // TEST32ri + 0U, // TEST32ri_alt + 0U, // TEST32rr + 0U, // TEST64i32 + 0U, // TEST64mi32 + 0U, // TEST64mi32_alt + 0U, // TEST64mr + 0U, // TEST64ri32 + 0U, // TEST64ri32_alt + 0U, // TEST64rr + 0U, // TEST8i8 + 0U, // TEST8mi + 0U, // TEST8mi_alt + 0U, // TEST8mr + 0U, // TEST8ri + 0U, // TEST8ri_alt + 0U, // TEST8rr + 0U, // TPAUSE + 0U, // TST_F + 0U, // TST_Fp32 + 0U, // TST_Fp64 + 0U, // TST_Fp80 + 0U, // TZCNT16rm + 0U, // TZCNT16rr + 0U, // TZCNT32rm + 0U, // TZCNT32rr + 0U, // TZCNT64rm + 0U, // TZCNT64rr + 0U, // TZMSK32rm + 0U, // TZMSK32rr + 0U, // TZMSK64rm + 0U, // TZMSK64rr + 0U, // UCOMISDrm + 0U, // UCOMISDrm_Int + 0U, // UCOMISDrr + 0U, // UCOMISDrr_Int + 0U, // UCOMISSrm + 0U, // UCOMISSrm_Int + 0U, // UCOMISSrr + 0U, // UCOMISSrr_Int + 0U, // UCOM_FIPr + 0U, // UCOM_FIr + 0U, // UCOM_FPPr + 0U, // UCOM_FPr + 0U, // UCOM_FpIr32 + 0U, // UCOM_FpIr64 + 0U, // UCOM_FpIr80 + 0U, // UCOM_Fpr32 + 0U, // UCOM_Fpr64 + 0U, // UCOM_Fpr80 + 0U, // UCOM_Fr + 0U, // UD0 + 0U, // UD1 + 0U, // UD2 + 0U, // UMONITOR16 + 0U, // UMONITOR32 + 0U, // UMONITOR64 + 0U, // UMWAIT + 0U, // UNPCKHPDrm + 0U, // UNPCKHPDrr + 0U, // UNPCKHPSrm + 0U, // UNPCKHPSrr + 0U, // UNPCKLPDrm + 0U, // UNPCKLPDrr + 0U, // UNPCKLPSrm + 0U, // UNPCKLPSrr + 256U, // V4FMADDPSrm + 35108U, // V4FMADDPSrmk + 35108U, // V4FMADDPSrmkz + 256U, // V4FMADDSSrm + 35108U, // V4FMADDSSrmk + 35108U, // V4FMADDSSrmkz + 256U, // V4FNMADDPSrm + 35108U, // V4FNMADDPSrmk + 35108U, // V4FNMADDPSrmkz + 256U, // V4FNMADDSSrm + 35108U, // V4FNMADDSSrmk + 35108U, // V4FNMADDSSrmkz + 320U, // VADDPDYrm + 96U, // VADDPDYrr + 352U, // VADDPDZ128rm + 4480U, // VADDPDZ128rmb + 1116452U, // VADDPDZ128rmbk + 1149028U, // VADDPDZ128rmbkz + 35108U, // VADDPDZ128rmk + 133220U, // VADDPDZ128rmkz + 96U, // VADDPDZ128rr + 166180U, // VADDPDZ128rrk + 198756U, // VADDPDZ128rrkz + 320U, // VADDPDZ256rm + 6528U, // VADDPDZ256rmb + 2165028U, // VADDPDZ256rmbk + 2197604U, // VADDPDZ256rmbkz + 231716U, // VADDPDZ256rmk + 264292U, // VADDPDZ256rmkz + 96U, // VADDPDZ256rr + 166180U, // VADDPDZ256rrk + 198756U, // VADDPDZ256rrkz + 416U, // VADDPDZrm + 8576U, // VADDPDZrmb + 3213604U, // VADDPDZrmbk + 3246180U, // VADDPDZrmbkz + 297252U, // VADDPDZrmk + 329828U, // VADDPDZrmkz + 96U, // VADDPDZrr + 362592U, // VADDPDZrrb + 4360484U, // VADDPDZrrbk + 21170276U, // VADDPDZrrbkz + 166180U, // VADDPDZrrk + 198756U, // VADDPDZrrkz + 352U, // VADDPDrm + 96U, // VADDPDrr + 320U, // VADDPSYrm + 96U, // VADDPSYrr + 352U, // VADDPSZ128rm + 6592U, // VADDPSZ128rmb + 2492708U, // VADDPSZ128rmbk + 2525284U, // VADDPSZ128rmbkz + 35108U, // VADDPSZ128rmk + 133220U, // VADDPSZ128rmkz + 96U, // VADDPSZ128rr + 166180U, // VADDPSZ128rrk + 198756U, // VADDPSZ128rrkz + 320U, // VADDPSZ256rm + 8640U, // VADDPSZ256rmb + 3541284U, // VADDPSZ256rmbk + 3573860U, // VADDPSZ256rmbkz + 231716U, // VADDPSZ256rmk + 264292U, // VADDPSZ256rmkz + 96U, // VADDPSZ256rr + 166180U, // VADDPSZ256rrk + 198756U, // VADDPSZ256rrkz + 416U, // VADDPSZrm + 10688U, // VADDPSZrmb + 5638436U, // VADDPSZrmbk + 5671012U, // VADDPSZrmbkz + 297252U, // VADDPSZrmk + 329828U, // VADDPSZrmkz + 96U, // VADDPSZrr + 362592U, // VADDPSZrrb + 4360484U, // VADDPSZrrbk + 21170276U, // VADDPSZrrbkz + 166180U, // VADDPSZrrk + 198756U, // VADDPSZrrkz + 352U, // VADDPSrm + 96U, // VADDPSrr + 384U, // VADDSDZrm + 384U, // VADDSDZrm_Int + 67876U, // VADDSDZrm_Intk + 100452U, // VADDSDZrm_Intkz + 96U, // VADDSDZrr + 96U, // VADDSDZrr_Int + 166180U, // VADDSDZrr_Intk + 198756U, // VADDSDZrr_Intkz + 362592U, // VADDSDZrrb_Int + 4360484U, // VADDSDZrrb_Intk + 21170276U, // VADDSDZrrb_Intkz + 384U, // VADDSDrm + 384U, // VADDSDrm_Int + 96U, // VADDSDrr + 96U, // VADDSDrr_Int + 448U, // VADDSSZrm + 448U, // VADDSSZrm_Int + 395556U, // VADDSSZrm_Intk + 428132U, // VADDSSZrm_Intkz + 96U, // VADDSSZrr + 96U, // VADDSSZrr_Int + 166180U, // VADDSSZrr_Intk + 198756U, // VADDSSZrr_Intkz + 362592U, // VADDSSZrrb_Int + 4360484U, // VADDSSZrrb_Intk + 21170276U, // VADDSSZrrb_Intkz + 448U, // VADDSSrm + 448U, // VADDSSrm_Int + 96U, // VADDSSrr + 96U, // VADDSSrr_Int + 320U, // VADDSUBPDYrm + 96U, // VADDSUBPDYrr + 352U, // VADDSUBPDrm + 96U, // VADDSUBPDrr + 320U, // VADDSUBPSYrm + 96U, // VADDSUBPSYrr + 352U, // VADDSUBPSrm + 96U, // VADDSUBPSrr + 480U, // VAESDECLASTYrm + 96U, // VAESDECLASTYrr + 512U, // VAESDECLASTZ128rm + 96U, // VAESDECLASTZ128rr + 480U, // VAESDECLASTZ256rm + 96U, // VAESDECLASTZ256rr + 544U, // VAESDECLASTZrm + 96U, // VAESDECLASTZrr + 512U, // VAESDECLASTrm + 96U, // VAESDECLASTrr + 480U, // VAESDECYrm + 96U, // VAESDECYrr + 512U, // VAESDECZ128rm + 96U, // VAESDECZ128rr + 480U, // VAESDECZ256rm + 96U, // VAESDECZ256rr + 544U, // VAESDECZrm + 96U, // VAESDECZrr + 512U, // VAESDECrm + 96U, // VAESDECrr + 480U, // VAESENCLASTYrm + 96U, // VAESENCLASTYrr + 512U, // VAESENCLASTZ128rm + 96U, // VAESENCLASTZ128rr + 480U, // VAESENCLASTZ256rm + 96U, // VAESENCLASTZ256rr + 544U, // VAESENCLASTZrm + 96U, // VAESENCLASTZrr + 512U, // VAESENCLASTrm + 96U, // VAESENCLASTrr + 480U, // VAESENCYrm + 96U, // VAESENCYrr + 512U, // VAESENCZ128rm + 96U, // VAESENCZ128rr + 480U, // VAESENCZ256rm + 96U, // VAESENCZ256rr + 544U, // VAESENCZrm + 96U, // VAESENCZrr + 512U, // VAESENCrm + 96U, // VAESENCrr + 0U, // VAESIMCrm + 0U, // VAESIMCrr + 0U, // VAESKEYGENASSIST128rm + 32U, // VAESKEYGENASSIST128rr + 471104U, // VALIGNDZ128rmbi + 40339748U, // VALIGNDZ128rmbik + 57149540U, // VALIGNDZ128rmbikz + 461312U, // VALIGNDZ128rmi + 38308132U, // VALIGNDZ128rmik + 55117924U, // VALIGNDZ128rmikz + 624736U, // VALIGNDZ128rri + 71469348U, // VALIGNDZ128rrik + 88279140U, // VALIGNDZ128rrikz + 473152U, // VALIGNDZ256rmbi + 41388324U, // VALIGNDZ256rmbik + 58198116U, // VALIGNDZ256rmbikz + 461280U, // VALIGNDZ256rmi + 38406436U, // VALIGNDZ256rmik + 55216228U, // VALIGNDZ256rmikz + 624736U, // VALIGNDZ256rri + 71469348U, // VALIGNDZ256rrik + 88279140U, // VALIGNDZ256rrikz + 475200U, // VALIGNDZrmbi + 42436900U, // VALIGNDZrmbik + 59246692U, // VALIGNDZrmbikz + 461344U, // VALIGNDZrmi + 38471972U, // VALIGNDZrmik + 55281764U, // VALIGNDZrmikz + 624736U, // VALIGNDZrri + 71469348U, // VALIGNDZrrik + 88279140U, // VALIGNDZrrikz + 477312U, // VALIGNQZ128rmbi + 43780388U, // VALIGNQZ128rmbik + 60590180U, // VALIGNQZ128rmbikz + 461312U, // VALIGNQZ128rmi + 38308132U, // VALIGNQZ128rmik + 55117924U, // VALIGNQZ128rmikz + 624736U, // VALIGNQZ128rri + 71469348U, // VALIGNQZ128rrik + 88279140U, // VALIGNQZ128rrikz + 471168U, // VALIGNQZ256rmbi + 40634660U, // VALIGNQZ256rmbik + 57444452U, // VALIGNQZ256rmbikz + 461280U, // VALIGNQZ256rmi + 38406436U, // VALIGNQZ256rmik + 55216228U, // VALIGNQZ256rmikz + 624736U, // VALIGNQZ256rri + 71469348U, // VALIGNQZ256rrik + 88279140U, // VALIGNQZ256rrikz + 473216U, // VALIGNQZrmbi + 41683236U, // VALIGNQZrmbik + 58493028U, // VALIGNQZrmbikz + 461344U, // VALIGNQZrmi + 38471972U, // VALIGNQZrmik + 55281764U, // VALIGNQZrmikz + 624736U, // VALIGNQZrri + 71469348U, // VALIGNQZrrik + 88279140U, // VALIGNQZrrikz + 320U, // VANDNPDYrm + 96U, // VANDNPDYrr + 352U, // VANDNPDZ128rm + 4480U, // VANDNPDZ128rmb + 1116452U, // VANDNPDZ128rmbk + 1149028U, // VANDNPDZ128rmbkz + 35108U, // VANDNPDZ128rmk + 133220U, // VANDNPDZ128rmkz + 96U, // VANDNPDZ128rr + 166180U, // VANDNPDZ128rrk + 198756U, // VANDNPDZ128rrkz + 320U, // VANDNPDZ256rm + 6528U, // VANDNPDZ256rmb + 2165028U, // VANDNPDZ256rmbk + 2197604U, // VANDNPDZ256rmbkz + 231716U, // VANDNPDZ256rmk + 264292U, // VANDNPDZ256rmkz + 96U, // VANDNPDZ256rr + 166180U, // VANDNPDZ256rrk + 198756U, // VANDNPDZ256rrkz + 416U, // VANDNPDZrm + 8576U, // VANDNPDZrmb + 3213604U, // VANDNPDZrmbk + 3246180U, // VANDNPDZrmbkz + 297252U, // VANDNPDZrmk + 329828U, // VANDNPDZrmkz + 96U, // VANDNPDZrr + 166180U, // VANDNPDZrrk + 198756U, // VANDNPDZrrkz + 352U, // VANDNPDrm + 96U, // VANDNPDrr + 320U, // VANDNPSYrm + 96U, // VANDNPSYrr + 352U, // VANDNPSZ128rm + 6592U, // VANDNPSZ128rmb + 2492708U, // VANDNPSZ128rmbk + 2525284U, // VANDNPSZ128rmbkz + 35108U, // VANDNPSZ128rmk + 133220U, // VANDNPSZ128rmkz + 96U, // VANDNPSZ128rr + 166180U, // VANDNPSZ128rrk + 198756U, // VANDNPSZ128rrkz + 320U, // VANDNPSZ256rm + 8640U, // VANDNPSZ256rmb + 3541284U, // VANDNPSZ256rmbk + 3573860U, // VANDNPSZ256rmbkz + 231716U, // VANDNPSZ256rmk + 264292U, // VANDNPSZ256rmkz + 96U, // VANDNPSZ256rr + 166180U, // VANDNPSZ256rrk + 198756U, // VANDNPSZ256rrkz + 416U, // VANDNPSZrm + 10688U, // VANDNPSZrmb + 5638436U, // VANDNPSZrmbk + 5671012U, // VANDNPSZrmbkz + 297252U, // VANDNPSZrmk + 329828U, // VANDNPSZrmkz + 96U, // VANDNPSZrr + 166180U, // VANDNPSZrrk + 198756U, // VANDNPSZrrkz + 352U, // VANDNPSrm + 96U, // VANDNPSrr + 320U, // VANDPDYrm + 96U, // VANDPDYrr + 352U, // VANDPDZ128rm + 4480U, // VANDPDZ128rmb + 1116452U, // VANDPDZ128rmbk + 1149028U, // VANDPDZ128rmbkz + 35108U, // VANDPDZ128rmk + 133220U, // VANDPDZ128rmkz + 96U, // VANDPDZ128rr + 166180U, // VANDPDZ128rrk + 198756U, // VANDPDZ128rrkz + 320U, // VANDPDZ256rm + 6528U, // VANDPDZ256rmb + 2165028U, // VANDPDZ256rmbk + 2197604U, // VANDPDZ256rmbkz + 231716U, // VANDPDZ256rmk + 264292U, // VANDPDZ256rmkz + 96U, // VANDPDZ256rr + 166180U, // VANDPDZ256rrk + 198756U, // VANDPDZ256rrkz + 416U, // VANDPDZrm + 8576U, // VANDPDZrmb + 3213604U, // VANDPDZrmbk + 3246180U, // VANDPDZrmbkz + 297252U, // VANDPDZrmk + 329828U, // VANDPDZrmkz + 96U, // VANDPDZrr + 166180U, // VANDPDZrrk + 198756U, // VANDPDZrrkz + 352U, // VANDPDrm + 96U, // VANDPDrr + 320U, // VANDPSYrm + 96U, // VANDPSYrr + 352U, // VANDPSZ128rm + 6592U, // VANDPSZ128rmb + 2492708U, // VANDPSZ128rmbk + 2525284U, // VANDPSZ128rmbkz + 35108U, // VANDPSZ128rmk + 133220U, // VANDPSZ128rmkz + 96U, // VANDPSZ128rr + 166180U, // VANDPSZ128rrk + 198756U, // VANDPSZ128rrkz + 320U, // VANDPSZ256rm + 8640U, // VANDPSZ256rmb + 3541284U, // VANDPSZ256rmbk + 3573860U, // VANDPSZ256rmbkz + 231716U, // VANDPSZ256rmk + 264292U, // VANDPSZ256rmkz + 96U, // VANDPSZ256rr + 166180U, // VANDPSZ256rrk + 198756U, // VANDPSZ256rrkz + 416U, // VANDPSZrm + 10688U, // VANDPSZrmb + 5638436U, // VANDPSZrmbk + 5671012U, // VANDPSZrmbkz + 297252U, // VANDPSZrmk + 329828U, // VANDPSZrmkz + 96U, // VANDPSZrr + 166180U, // VANDPSZrrk + 198756U, // VANDPSZrrkz + 352U, // VANDPSrm + 96U, // VANDPSrr + 352U, // VBLENDMPDZ128rm + 4480U, // VBLENDMPDZ128rmb + 1149028U, // VBLENDMPDZ128rmbk + 1149028U, // VBLENDMPDZ128rmbkz + 133220U, // VBLENDMPDZ128rmk + 133220U, // VBLENDMPDZ128rmkz + 96U, // VBLENDMPDZ128rr + 198756U, // VBLENDMPDZ128rrk + 198756U, // VBLENDMPDZ128rrkz + 320U, // VBLENDMPDZ256rm + 6528U, // VBLENDMPDZ256rmb + 2197604U, // VBLENDMPDZ256rmbk + 2197604U, // VBLENDMPDZ256rmbkz + 264292U, // VBLENDMPDZ256rmk + 264292U, // VBLENDMPDZ256rmkz + 96U, // VBLENDMPDZ256rr + 198756U, // VBLENDMPDZ256rrk + 198756U, // VBLENDMPDZ256rrkz + 416U, // VBLENDMPDZrm + 8576U, // VBLENDMPDZrmb + 3246180U, // VBLENDMPDZrmbk + 3246180U, // VBLENDMPDZrmbkz + 329828U, // VBLENDMPDZrmk + 329828U, // VBLENDMPDZrmkz + 96U, // VBLENDMPDZrr + 198756U, // VBLENDMPDZrrk + 198756U, // VBLENDMPDZrrkz + 352U, // VBLENDMPSZ128rm + 6592U, // VBLENDMPSZ128rmb + 2525284U, // VBLENDMPSZ128rmbk + 2525284U, // VBLENDMPSZ128rmbkz + 133220U, // VBLENDMPSZ128rmk + 133220U, // VBLENDMPSZ128rmkz + 96U, // VBLENDMPSZ128rr + 198756U, // VBLENDMPSZ128rrk + 198756U, // VBLENDMPSZ128rrkz + 320U, // VBLENDMPSZ256rm + 8640U, // VBLENDMPSZ256rmb + 3573860U, // VBLENDMPSZ256rmbk + 3573860U, // VBLENDMPSZ256rmbkz + 264292U, // VBLENDMPSZ256rmk + 264292U, // VBLENDMPSZ256rmkz + 96U, // VBLENDMPSZ256rr + 198756U, // VBLENDMPSZ256rrk + 198756U, // VBLENDMPSZ256rrkz + 416U, // VBLENDMPSZrm + 10688U, // VBLENDMPSZrmb + 5671012U, // VBLENDMPSZrmbk + 5671012U, // VBLENDMPSZrmbkz + 329828U, // VBLENDMPSZrmk + 329828U, // VBLENDMPSZrmkz + 96U, // VBLENDMPSZrr + 198756U, // VBLENDMPSZrrk + 198756U, // VBLENDMPSZrrkz + 461120U, // VBLENDPDYrmi + 624736U, // VBLENDPDYrri + 461152U, // VBLENDPDrmi + 624736U, // VBLENDPDrri + 461120U, // VBLENDPSYrmi + 624736U, // VBLENDPSYrri + 461152U, // VBLENDPSrmi + 624736U, // VBLENDPSrri + 854336U, // VBLENDVPDYrm + 198752U, // VBLENDVPDYrr + 854368U, // VBLENDVPDrm + 198752U, // VBLENDVPDrr + 854336U, // VBLENDVPSYrm + 198752U, // VBLENDVPSYrr + 854368U, // VBLENDVPSrm + 198752U, // VBLENDVPSrr + 0U, // VBROADCASTF128 + 0U, // VBROADCASTF32X2Z256m + 580U, // VBROADCASTF32X2Z256mk + 388U, // VBROADCASTF32X2Z256mkz + 0U, // VBROADCASTF32X2Z256r + 292U, // VBROADCASTF32X2Z256rk + 100U, // VBROADCASTF32X2Z256rkz + 0U, // VBROADCASTF32X2Zm + 580U, // VBROADCASTF32X2Zmk + 388U, // VBROADCASTF32X2Zmkz + 0U, // VBROADCASTF32X2Zr + 292U, // VBROADCASTF32X2Zrk + 100U, // VBROADCASTF32X2Zrkz + 0U, // VBROADCASTF32X4Z256rm + 260U, // VBROADCASTF32X4Z256rmk + 356U, // VBROADCASTF32X4Z256rmkz + 0U, // VBROADCASTF32X4rm + 260U, // VBROADCASTF32X4rmk + 356U, // VBROADCASTF32X4rmkz + 0U, // VBROADCASTF32X8rm + 612U, // VBROADCASTF32X8rmk + 324U, // VBROADCASTF32X8rmkz + 0U, // VBROADCASTF64X2Z128rm + 260U, // VBROADCASTF64X2Z128rmk + 356U, // VBROADCASTF64X2Z128rmkz + 0U, // VBROADCASTF64X2rm + 260U, // VBROADCASTF64X2rmk + 356U, // VBROADCASTF64X2rmkz + 0U, // VBROADCASTF64X4rm + 612U, // VBROADCASTF64X4rmk + 324U, // VBROADCASTF64X4rmkz + 0U, // VBROADCASTI128 + 0U, // VBROADCASTI32X2Z128m + 644U, // VBROADCASTI32X2Z128mk + 132U, // VBROADCASTI32X2Z128mkz + 0U, // VBROADCASTI32X2Z128r + 292U, // VBROADCASTI32X2Z128rk + 100U, // VBROADCASTI32X2Z128rkz + 0U, // VBROADCASTI32X2Z256m + 644U, // VBROADCASTI32X2Z256mk + 132U, // VBROADCASTI32X2Z256mkz + 0U, // VBROADCASTI32X2Z256r + 292U, // VBROADCASTI32X2Z256rk + 100U, // VBROADCASTI32X2Z256rkz + 0U, // VBROADCASTI32X2Zm + 644U, // VBROADCASTI32X2Zmk + 132U, // VBROADCASTI32X2Zmkz + 0U, // VBROADCASTI32X2Zr + 292U, // VBROADCASTI32X2Zrk + 100U, // VBROADCASTI32X2Zrkz + 0U, // VBROADCASTI32X4Z256rm + 676U, // VBROADCASTI32X4Z256rmk + 516U, // VBROADCASTI32X4Z256rmkz + 0U, // VBROADCASTI32X4rm + 676U, // VBROADCASTI32X4rmk + 516U, // VBROADCASTI32X4rmkz + 0U, // VBROADCASTI32X8rm + 708U, // VBROADCASTI32X8rmk + 484U, // VBROADCASTI32X8rmkz + 0U, // VBROADCASTI64X2Z128rm + 676U, // VBROADCASTI64X2Z128rmk + 516U, // VBROADCASTI64X2Z128rmkz + 0U, // VBROADCASTI64X2rm + 676U, // VBROADCASTI64X2rmk + 516U, // VBROADCASTI64X2rmkz + 0U, // VBROADCASTI64X4rm + 708U, // VBROADCASTI64X4rmk + 484U, // VBROADCASTI64X4rmkz + 0U, // VBROADCASTSDYrm + 0U, // VBROADCASTSDYrr + 0U, // VBROADCASTSDZ256m + 580U, // VBROADCASTSDZ256mk + 388U, // VBROADCASTSDZ256mkz + 0U, // VBROADCASTSDZ256r + 292U, // VBROADCASTSDZ256rk + 100U, // VBROADCASTSDZ256rkz + 0U, // VBROADCASTSDZm + 580U, // VBROADCASTSDZmk + 388U, // VBROADCASTSDZmkz + 0U, // VBROADCASTSDZr + 292U, // VBROADCASTSDZrk + 100U, // VBROADCASTSDZrkz + 0U, // VBROADCASTSSYrm + 0U, // VBROADCASTSSYrr + 0U, // VBROADCASTSSZ128m + 740U, // VBROADCASTSSZ128mk + 452U, // VBROADCASTSSZ128mkz + 0U, // VBROADCASTSSZ128r + 292U, // VBROADCASTSSZ128rk + 100U, // VBROADCASTSSZ128rkz + 0U, // VBROADCASTSSZ256m + 740U, // VBROADCASTSSZ256mk + 452U, // VBROADCASTSSZ256mkz + 0U, // VBROADCASTSSZ256r + 292U, // VBROADCASTSSZ256rk + 100U, // VBROADCASTSSZ256rkz + 0U, // VBROADCASTSSZm + 740U, // VBROADCASTSSZmk + 452U, // VBROADCASTSSZmkz + 0U, // VBROADCASTSSZr + 292U, // VBROADCASTSSZrk + 100U, // VBROADCASTSSZrkz + 0U, // VBROADCASTSSrm + 0U, // VBROADCASTSSrr + 325U, // VCMPPDYrmi + 461120U, // VCMPPDYrmi_alt + 101U, // VCMPPDYrri + 624736U, // VCMPPDYrri_alt + 4485U, // VCMPPDZ128rmbi + 477568U, // VCMPPDZ128rmbi_alt + 59869284U, // VCMPPDZ128rmbi_altk + 773U, // VCMPPDZ128rmbik + 357U, // VCMPPDZ128rmi + 461152U, // VCMPPDZ128rmi_alt + 54659172U, // VCMPPDZ128rmi_altk + 6U, // VCMPPDZ128rmik + 101U, // VCMPPDZ128rri + 624736U, // VCMPPDZ128rri_alt + 88279140U, // VCMPPDZ128rri_altk + 806U, // VCMPPDZ128rrik + 6533U, // VCMPPDZ256rmbi + 471424U, // VCMPPDZ256rmbi_alt + 56723556U, // VCMPPDZ256rmbi_altk + 837U, // VCMPPDZ256rmbik + 325U, // VCMPPDZ256rmi + 461120U, // VCMPPDZ256rmi_alt + 54790244U, // VCMPPDZ256rmi_altk + 7U, // VCMPPDZ256rmik + 101U, // VCMPPDZ256rri + 624736U, // VCMPPDZ256rri_alt + 88279140U, // VCMPPDZ256rri_altk + 806U, // VCMPPDZ256rrik + 8581U, // VCMPPDZrmbi + 473472U, // VCMPPDZrmbi_alt + 57772132U, // VCMPPDZrmbi_altk + 869U, // VCMPPDZrmbik + 421U, // VCMPPDZrmi + 461216U, // VCMPPDZrmi_alt + 54855780U, // VCMPPDZrmi_altk + 7U, // VCMPPDZrmik + 101U, // VCMPPDZrri + 624736U, // VCMPPDZrri_alt + 88279140U, // VCMPPDZrri_altk + 20581U, // VCMPPDZrrib + 645216U, // VCMPPDZrrib_alt + 94570596U, // VCMPPDZrrib_altk + 902U, // VCMPPDZrribk + 806U, // VCMPPDZrrik + 357U, // VCMPPDrmi + 461152U, // VCMPPDrmi_alt + 101U, // VCMPPDrri + 624736U, // VCMPPDrri_alt + 325U, // VCMPPSYrmi + 461120U, // VCMPPSYrmi_alt + 101U, // VCMPPSYrri + 624736U, // VCMPPSYrri_alt + 6597U, // VCMPPSZ128rmbi + 471488U, // VCMPPSZ128rmbi_alt + 57051236U, // VCMPPSZ128rmbi_altk + 840U, // VCMPPSZ128rmbik + 357U, // VCMPPSZ128rmi + 461152U, // VCMPPSZ128rmi_alt + 54659172U, // VCMPPSZ128rmi_altk + 6U, // VCMPPSZ128rmik + 101U, // VCMPPSZ128rri + 624736U, // VCMPPSZ128rri_alt + 88279140U, // VCMPPSZ128rri_altk + 806U, // VCMPPSZ128rrik + 8645U, // VCMPPSZ256rmbi + 473536U, // VCMPPSZ256rmbi_alt + 58099812U, // VCMPPSZ256rmbi_altk + 872U, // VCMPPSZ256rmbik + 325U, // VCMPPSZ256rmi + 461120U, // VCMPPSZ256rmi_alt + 54790244U, // VCMPPSZ256rmi_altk + 7U, // VCMPPSZ256rmik + 101U, // VCMPPSZ256rri + 624736U, // VCMPPSZ256rri_alt + 88279140U, // VCMPPSZ256rri_altk + 806U, // VCMPPSZ256rrik + 10693U, // VCMPPSZrmbi + 475584U, // VCMPPSZrmbi_alt + 59148388U, // VCMPPSZrmbi_altk + 936U, // VCMPPSZrmbik + 421U, // VCMPPSZrmi + 461216U, // VCMPPSZrmi_alt + 54855780U, // VCMPPSZrmi_altk + 7U, // VCMPPSZrmik + 101U, // VCMPPSZrri + 624736U, // VCMPPSZrri_alt + 88279140U, // VCMPPSZrri_altk + 20581U, // VCMPPSZrrib + 645216U, // VCMPPSZrrib_alt + 94570596U, // VCMPPSZrrib_altk + 902U, // VCMPPSZrribk + 806U, // VCMPPSZrrik + 357U, // VCMPPSrmi + 461152U, // VCMPPSrmi_alt + 101U, // VCMPPSrri + 624736U, // VCMPPSrri_alt + 389U, // VCMPSDZrm + 389U, // VCMPSDZrm_Int + 805U, // VCMPSDZrm_Intk + 461184U, // VCMPSDZrmi_alt + 54626404U, // VCMPSDZrmi_altk + 101U, // VCMPSDZrr + 101U, // VCMPSDZrr_Int + 806U, // VCMPSDZrr_Intk + 20581U, // VCMPSDZrrb_Int + 902U, // VCMPSDZrrb_Intk + 645216U, // VCMPSDZrrb_alt + 94570596U, // VCMPSDZrrb_altk + 624736U, // VCMPSDZrri_alt + 88279140U, // VCMPSDZrri_altk + 389U, // VCMPSDrm + 389U, // VCMPSDrm_Int + 461184U, // VCMPSDrm_alt + 101U, // VCMPSDrr + 101U, // VCMPSDrr_Int + 624736U, // VCMPSDrr_alt + 453U, // VCMPSSZrm + 453U, // VCMPSSZrm_Int + 808U, // VCMPSSZrm_Intk + 461248U, // VCMPSSZrmi_alt + 54954084U, // VCMPSSZrmi_altk + 101U, // VCMPSSZrr + 101U, // VCMPSSZrr_Int + 806U, // VCMPSSZrr_Intk + 20581U, // VCMPSSZrrb_Int + 902U, // VCMPSSZrrb_Intk + 645216U, // VCMPSSZrrb_alt + 94570596U, // VCMPSSZrrb_altk + 624736U, // VCMPSSZrri_alt + 88279140U, // VCMPSSZrri_altk + 453U, // VCMPSSrm + 453U, // VCMPSSrm_Int + 461248U, // VCMPSSrm_alt + 101U, // VCMPSSrr + 101U, // VCMPSSrr_Int + 624736U, // VCMPSSrr_alt + 0U, // VCOMISDZrm + 0U, // VCOMISDZrm_Int + 0U, // VCOMISDZrr + 0U, // VCOMISDZrr_Int + 8U, // VCOMISDZrrb + 0U, // VCOMISDrm + 0U, // VCOMISDrm_Int + 0U, // VCOMISDrr + 0U, // VCOMISDrr_Int + 0U, // VCOMISSZrm + 0U, // VCOMISSZrm_Int + 0U, // VCOMISSZrr + 0U, // VCOMISSZrr_Int + 8U, // VCOMISSZrrb + 0U, // VCOMISSrm + 0U, // VCOMISSrm_Int + 0U, // VCOMISSrr + 0U, // VCOMISSrr_Int + 0U, // VCOMPRESSPDZ128mr + 164U, // VCOMPRESSPDZ128mrk + 0U, // VCOMPRESSPDZ128rr + 292U, // VCOMPRESSPDZ128rrk + 100U, // VCOMPRESSPDZ128rrkz + 0U, // VCOMPRESSPDZ256mr + 164U, // VCOMPRESSPDZ256mrk + 0U, // VCOMPRESSPDZ256rr + 292U, // VCOMPRESSPDZ256rrk + 100U, // VCOMPRESSPDZ256rrkz + 0U, // VCOMPRESSPDZmr + 164U, // VCOMPRESSPDZmrk + 0U, // VCOMPRESSPDZrr + 292U, // VCOMPRESSPDZrrk + 100U, // VCOMPRESSPDZrrkz + 0U, // VCOMPRESSPSZ128mr + 164U, // VCOMPRESSPSZ128mrk + 0U, // VCOMPRESSPSZ128rr + 292U, // VCOMPRESSPSZ128rrk + 100U, // VCOMPRESSPSZ128rrkz + 0U, // VCOMPRESSPSZ256mr + 164U, // VCOMPRESSPSZ256mrk + 0U, // VCOMPRESSPSZ256rr + 292U, // VCOMPRESSPSZ256rrk + 100U, // VCOMPRESSPSZ256rrkz + 0U, // VCOMPRESSPSZmr + 164U, // VCOMPRESSPSZmrk + 0U, // VCOMPRESSPSZrr + 292U, // VCOMPRESSPSZrrk + 100U, // VCOMPRESSPSZrrkz + 0U, // VCVTDQ2PDYrm + 0U, // VCVTDQ2PDYrr + 0U, // VCVTDQ2PDZ128rm + 9U, // VCVTDQ2PDZ128rmb + 5060U, // VCVTDQ2PDZ128rmbk + 4164U, // VCVTDQ2PDZ128rmbkz + 644U, // VCVTDQ2PDZ128rmk + 132U, // VCVTDQ2PDZ128rmkz + 0U, // VCVTDQ2PDZ128rr + 292U, // VCVTDQ2PDZ128rrk + 100U, // VCVTDQ2PDZ128rrkz + 0U, // VCVTDQ2PDZ256rm + 9U, // VCVTDQ2PDZ256rmb + 7108U, // VCVTDQ2PDZ256rmbk + 6212U, // VCVTDQ2PDZ256rmbkz + 676U, // VCVTDQ2PDZ256rmk + 516U, // VCVTDQ2PDZ256rmkz + 0U, // VCVTDQ2PDZ256rr + 292U, // VCVTDQ2PDZ256rrk + 100U, // VCVTDQ2PDZ256rrkz + 0U, // VCVTDQ2PDZrm + 10U, // VCVTDQ2PDZrmb + 9156U, // VCVTDQ2PDZrmbk + 8260U, // VCVTDQ2PDZrmbkz + 708U, // VCVTDQ2PDZrmk + 484U, // VCVTDQ2PDZrmkz + 0U, // VCVTDQ2PDZrr + 292U, // VCVTDQ2PDZrrk + 100U, // VCVTDQ2PDZrrkz + 0U, // VCVTDQ2PDrm + 0U, // VCVTDQ2PDrr + 0U, // VCVTDQ2PSYrm + 0U, // VCVTDQ2PSYrr + 0U, // VCVTDQ2PSZ128rm + 9U, // VCVTDQ2PSZ128rmb + 7108U, // VCVTDQ2PSZ128rmbk + 6212U, // VCVTDQ2PSZ128rmbkz + 676U, // VCVTDQ2PSZ128rmk + 516U, // VCVTDQ2PSZ128rmkz + 0U, // VCVTDQ2PSZ128rr + 292U, // VCVTDQ2PSZ128rrk + 100U, // VCVTDQ2PSZ128rrkz + 0U, // VCVTDQ2PSZ256rm + 10U, // VCVTDQ2PSZ256rmb + 9156U, // VCVTDQ2PSZ256rmbk + 8260U, // VCVTDQ2PSZ256rmbkz + 708U, // VCVTDQ2PSZ256rmk + 484U, // VCVTDQ2PSZ256rmkz + 0U, // VCVTDQ2PSZ256rr + 292U, // VCVTDQ2PSZ256rrk + 100U, // VCVTDQ2PSZ256rrkz + 0U, // VCVTDQ2PSZrm + 10U, // VCVTDQ2PSZrmb + 11204U, // VCVTDQ2PSZrmbk + 10308U, // VCVTDQ2PSZrmbkz + 996U, // VCVTDQ2PSZrmk + 548U, // VCVTDQ2PSZrmkz + 0U, // VCVTDQ2PSZrr + 1024U, // VCVTDQ2PSZrrb + 887076U, // VCVTDQ2PSZrrbk + 362596U, // VCVTDQ2PSZrrbkz + 292U, // VCVTDQ2PSZrrk + 100U, // VCVTDQ2PSZrrkz + 0U, // VCVTDQ2PSrm + 0U, // VCVTDQ2PSrr + 0U, // VCVTPD2DQYrm + 0U, // VCVTPD2DQYrr + 0U, // VCVTPD2DQZ128rm + 9U, // VCVTPD2DQZ128rmb + 4676U, // VCVTPD2DQZ128rmbk + 4484U, // VCVTPD2DQZ128rmbkz + 260U, // VCVTPD2DQZ128rmk + 356U, // VCVTPD2DQZ128rmkz + 0U, // VCVTPD2DQZ128rr + 292U, // VCVTPD2DQZ128rrk + 100U, // VCVTPD2DQZ128rrkz + 0U, // VCVTPD2DQZ256rm + 9U, // VCVTPD2DQZ256rmb + 6724U, // VCVTPD2DQZ256rmbk + 6532U, // VCVTPD2DQZ256rmbkz + 612U, // VCVTPD2DQZ256rmk + 324U, // VCVTPD2DQZ256rmkz + 0U, // VCVTPD2DQZ256rr + 292U, // VCVTPD2DQZ256rrk + 100U, // VCVTPD2DQZ256rrkz + 0U, // VCVTPD2DQZrm + 10U, // VCVTPD2DQZrmb + 8772U, // VCVTPD2DQZrmbk + 8580U, // VCVTPD2DQZrmbkz + 1060U, // VCVTPD2DQZrmk + 420U, // VCVTPD2DQZrmkz + 0U, // VCVTPD2DQZrr + 1024U, // VCVTPD2DQZrrb + 887076U, // VCVTPD2DQZrrbk + 362596U, // VCVTPD2DQZrrbkz + 292U, // VCVTPD2DQZrrk + 100U, // VCVTPD2DQZrrkz + 0U, // VCVTPD2DQrm + 0U, // VCVTPD2DQrr + 0U, // VCVTPD2PSYrm + 0U, // VCVTPD2PSYrr + 0U, // VCVTPD2PSZ128rm + 9U, // VCVTPD2PSZ128rmb + 4676U, // VCVTPD2PSZ128rmbk + 4484U, // VCVTPD2PSZ128rmbkz + 260U, // VCVTPD2PSZ128rmk + 356U, // VCVTPD2PSZ128rmkz + 0U, // VCVTPD2PSZ128rr + 292U, // VCVTPD2PSZ128rrk + 100U, // VCVTPD2PSZ128rrkz + 0U, // VCVTPD2PSZ256rm + 9U, // VCVTPD2PSZ256rmb + 6724U, // VCVTPD2PSZ256rmbk + 6532U, // VCVTPD2PSZ256rmbkz + 612U, // VCVTPD2PSZ256rmk + 324U, // VCVTPD2PSZ256rmkz + 0U, // VCVTPD2PSZ256rr + 292U, // VCVTPD2PSZ256rrk + 100U, // VCVTPD2PSZ256rrkz + 0U, // VCVTPD2PSZrm + 10U, // VCVTPD2PSZrmb + 8772U, // VCVTPD2PSZrmbk + 8580U, // VCVTPD2PSZrmbkz + 1060U, // VCVTPD2PSZrmk + 420U, // VCVTPD2PSZrmkz + 0U, // VCVTPD2PSZrr + 1024U, // VCVTPD2PSZrrb + 887076U, // VCVTPD2PSZrrbk + 362596U, // VCVTPD2PSZrrbkz + 292U, // VCVTPD2PSZrrk + 100U, // VCVTPD2PSZrrkz + 0U, // VCVTPD2PSrm + 0U, // VCVTPD2PSrr + 0U, // VCVTPD2QQZ128rm + 9U, // VCVTPD2QQZ128rmb + 4676U, // VCVTPD2QQZ128rmbk + 4484U, // VCVTPD2QQZ128rmbkz + 260U, // VCVTPD2QQZ128rmk + 356U, // VCVTPD2QQZ128rmkz + 0U, // VCVTPD2QQZ128rr + 292U, // VCVTPD2QQZ128rrk + 100U, // VCVTPD2QQZ128rrkz + 0U, // VCVTPD2QQZ256rm + 9U, // VCVTPD2QQZ256rmb + 6724U, // VCVTPD2QQZ256rmbk + 6532U, // VCVTPD2QQZ256rmbkz + 612U, // VCVTPD2QQZ256rmk + 324U, // VCVTPD2QQZ256rmkz + 0U, // VCVTPD2QQZ256rr + 292U, // VCVTPD2QQZ256rrk + 100U, // VCVTPD2QQZ256rrkz + 0U, // VCVTPD2QQZrm + 10U, // VCVTPD2QQZrmb + 8772U, // VCVTPD2QQZrmbk + 8580U, // VCVTPD2QQZrmbkz + 1060U, // VCVTPD2QQZrmk + 420U, // VCVTPD2QQZrmkz + 0U, // VCVTPD2QQZrr + 1024U, // VCVTPD2QQZrrb + 887076U, // VCVTPD2QQZrrbk + 362596U, // VCVTPD2QQZrrbkz + 292U, // VCVTPD2QQZrrk + 100U, // VCVTPD2QQZrrkz + 0U, // VCVTPD2UDQZ128rm + 9U, // VCVTPD2UDQZ128rmb + 4676U, // VCVTPD2UDQZ128rmbk + 4484U, // VCVTPD2UDQZ128rmbkz + 260U, // VCVTPD2UDQZ128rmk + 356U, // VCVTPD2UDQZ128rmkz + 0U, // VCVTPD2UDQZ128rr + 292U, // VCVTPD2UDQZ128rrk + 100U, // VCVTPD2UDQZ128rrkz + 0U, // VCVTPD2UDQZ256rm + 9U, // VCVTPD2UDQZ256rmb + 6724U, // VCVTPD2UDQZ256rmbk + 6532U, // VCVTPD2UDQZ256rmbkz + 612U, // VCVTPD2UDQZ256rmk + 324U, // VCVTPD2UDQZ256rmkz + 0U, // VCVTPD2UDQZ256rr + 292U, // VCVTPD2UDQZ256rrk + 100U, // VCVTPD2UDQZ256rrkz + 0U, // VCVTPD2UDQZrm + 10U, // VCVTPD2UDQZrmb + 8772U, // VCVTPD2UDQZrmbk + 8580U, // VCVTPD2UDQZrmbkz + 1060U, // VCVTPD2UDQZrmk + 420U, // VCVTPD2UDQZrmkz + 0U, // VCVTPD2UDQZrr + 1024U, // VCVTPD2UDQZrrb + 887076U, // VCVTPD2UDQZrrbk + 362596U, // VCVTPD2UDQZrrbkz + 292U, // VCVTPD2UDQZrrk + 100U, // VCVTPD2UDQZrrkz + 0U, // VCVTPD2UQQZ128rm + 9U, // VCVTPD2UQQZ128rmb + 4676U, // VCVTPD2UQQZ128rmbk + 4484U, // VCVTPD2UQQZ128rmbkz + 260U, // VCVTPD2UQQZ128rmk + 356U, // VCVTPD2UQQZ128rmkz + 0U, // VCVTPD2UQQZ128rr + 292U, // VCVTPD2UQQZ128rrk + 100U, // VCVTPD2UQQZ128rrkz + 0U, // VCVTPD2UQQZ256rm + 9U, // VCVTPD2UQQZ256rmb + 6724U, // VCVTPD2UQQZ256rmbk + 6532U, // VCVTPD2UQQZ256rmbkz + 612U, // VCVTPD2UQQZ256rmk + 324U, // VCVTPD2UQQZ256rmkz + 0U, // VCVTPD2UQQZ256rr + 292U, // VCVTPD2UQQZ256rrk + 100U, // VCVTPD2UQQZ256rrkz + 0U, // VCVTPD2UQQZrm + 10U, // VCVTPD2UQQZrmb + 8772U, // VCVTPD2UQQZrmbk + 8580U, // VCVTPD2UQQZrmbkz + 1060U, // VCVTPD2UQQZrmk + 420U, // VCVTPD2UQQZrmkz + 0U, // VCVTPD2UQQZrr + 1024U, // VCVTPD2UQQZrrb + 887076U, // VCVTPD2UQQZrrbk + 362596U, // VCVTPD2UQQZrrbkz + 292U, // VCVTPD2UQQZrrk + 100U, // VCVTPD2UQQZrrkz + 0U, // VCVTPH2PSYrm + 0U, // VCVTPH2PSYrr + 0U, // VCVTPH2PSZ128rm + 580U, // VCVTPH2PSZ128rmk + 388U, // VCVTPH2PSZ128rmkz + 0U, // VCVTPH2PSZ128rr + 292U, // VCVTPH2PSZ128rrk + 100U, // VCVTPH2PSZ128rrkz + 0U, // VCVTPH2PSZ256rm + 260U, // VCVTPH2PSZ256rmk + 356U, // VCVTPH2PSZ256rmkz + 0U, // VCVTPH2PSZ256rr + 292U, // VCVTPH2PSZ256rrk + 100U, // VCVTPH2PSZ256rrkz + 0U, // VCVTPH2PSZrm + 612U, // VCVTPH2PSZrmk + 324U, // VCVTPH2PSZrmkz + 0U, // VCVTPH2PSZrr + 8U, // VCVTPH2PSZrrb + 20772U, // VCVTPH2PSZrrbk + 20580U, // VCVTPH2PSZrrbkz + 292U, // VCVTPH2PSZrrk + 100U, // VCVTPH2PSZrrkz + 0U, // VCVTPH2PSrm + 0U, // VCVTPH2PSrr + 0U, // VCVTPS2DQYrm + 0U, // VCVTPS2DQYrr + 0U, // VCVTPS2DQZ128rm + 9U, // VCVTPS2DQZ128rmb + 6884U, // VCVTPS2DQZ128rmbk + 6596U, // VCVTPS2DQZ128rmbkz + 260U, // VCVTPS2DQZ128rmk + 356U, // VCVTPS2DQZ128rmkz + 0U, // VCVTPS2DQZ128rr + 292U, // VCVTPS2DQZ128rrk + 100U, // VCVTPS2DQZ128rrkz + 0U, // VCVTPS2DQZ256rm + 10U, // VCVTPS2DQZ256rmb + 8932U, // VCVTPS2DQZ256rmbk + 8644U, // VCVTPS2DQZ256rmbkz + 612U, // VCVTPS2DQZ256rmk + 324U, // VCVTPS2DQZ256rmkz + 0U, // VCVTPS2DQZ256rr + 292U, // VCVTPS2DQZ256rrk + 100U, // VCVTPS2DQZ256rrkz + 0U, // VCVTPS2DQZrm + 10U, // VCVTPS2DQZrmb + 10980U, // VCVTPS2DQZrmbk + 10692U, // VCVTPS2DQZrmbkz + 1060U, // VCVTPS2DQZrmk + 420U, // VCVTPS2DQZrmkz + 0U, // VCVTPS2DQZrr + 1024U, // VCVTPS2DQZrrb + 887076U, // VCVTPS2DQZrrbk + 362596U, // VCVTPS2DQZrrbkz + 292U, // VCVTPS2DQZrrk + 100U, // VCVTPS2DQZrrkz + 0U, // VCVTPS2DQrm + 0U, // VCVTPS2DQrr + 0U, // VCVTPS2PDYrm + 0U, // VCVTPS2PDYrr + 0U, // VCVTPS2PDZ128rm + 9U, // VCVTPS2PDZ128rmb + 4836U, // VCVTPS2PDZ128rmbk + 4548U, // VCVTPS2PDZ128rmbkz + 580U, // VCVTPS2PDZ128rmk + 388U, // VCVTPS2PDZ128rmkz + 0U, // VCVTPS2PDZ128rr + 292U, // VCVTPS2PDZ128rrk + 100U, // VCVTPS2PDZ128rrkz + 0U, // VCVTPS2PDZ256rm + 9U, // VCVTPS2PDZ256rmb + 6884U, // VCVTPS2PDZ256rmbk + 6596U, // VCVTPS2PDZ256rmbkz + 260U, // VCVTPS2PDZ256rmk + 356U, // VCVTPS2PDZ256rmkz + 0U, // VCVTPS2PDZ256rr + 292U, // VCVTPS2PDZ256rrk + 100U, // VCVTPS2PDZ256rrkz + 0U, // VCVTPS2PDZrm + 10U, // VCVTPS2PDZrmb + 8932U, // VCVTPS2PDZrmbk + 8644U, // VCVTPS2PDZrmbkz + 612U, // VCVTPS2PDZrmk + 324U, // VCVTPS2PDZrmkz + 0U, // VCVTPS2PDZrr + 8U, // VCVTPS2PDZrrb + 20772U, // VCVTPS2PDZrrbk + 20580U, // VCVTPS2PDZrrbkz + 292U, // VCVTPS2PDZrrk + 100U, // VCVTPS2PDZrrkz + 0U, // VCVTPS2PDrm + 0U, // VCVTPS2PDrr + 0U, // VCVTPS2PHYmr + 32U, // VCVTPS2PHYrr + 0U, // VCVTPS2PHZ128mr + 460964U, // VCVTPS2PHZ128mrk + 32U, // VCVTPS2PHZ128rr + 2340U, // VCVTPS2PHZ128rrk + 624740U, // VCVTPS2PHZ128rrkz + 0U, // VCVTPS2PHZ256mr + 460964U, // VCVTPS2PHZ256mrk + 32U, // VCVTPS2PHZ256rr + 2340U, // VCVTPS2PHZ256rrk + 624740U, // VCVTPS2PHZ256rrkz + 0U, // VCVTPS2PHZmr + 460964U, // VCVTPS2PHZmrk + 32U, // VCVTPS2PHZrr + 11U, // VCVTPS2PHZrrb + 22820U, // VCVTPS2PHZrrbk + 645220U, // VCVTPS2PHZrrbkz + 2340U, // VCVTPS2PHZrrk + 624740U, // VCVTPS2PHZrrkz + 0U, // VCVTPS2PHmr + 32U, // VCVTPS2PHrr + 0U, // VCVTPS2QQZ128rm + 9U, // VCVTPS2QQZ128rmb + 4836U, // VCVTPS2QQZ128rmbk + 4548U, // VCVTPS2QQZ128rmbkz + 580U, // VCVTPS2QQZ128rmk + 388U, // VCVTPS2QQZ128rmkz + 0U, // VCVTPS2QQZ128rr + 292U, // VCVTPS2QQZ128rrk + 100U, // VCVTPS2QQZ128rrkz + 0U, // VCVTPS2QQZ256rm + 9U, // VCVTPS2QQZ256rmb + 6884U, // VCVTPS2QQZ256rmbk + 6596U, // VCVTPS2QQZ256rmbkz + 260U, // VCVTPS2QQZ256rmk + 356U, // VCVTPS2QQZ256rmkz + 0U, // VCVTPS2QQZ256rr + 292U, // VCVTPS2QQZ256rrk + 100U, // VCVTPS2QQZ256rrkz + 0U, // VCVTPS2QQZrm + 10U, // VCVTPS2QQZrmb + 8932U, // VCVTPS2QQZrmbk + 8644U, // VCVTPS2QQZrmbkz + 612U, // VCVTPS2QQZrmk + 324U, // VCVTPS2QQZrmkz + 0U, // VCVTPS2QQZrr + 1024U, // VCVTPS2QQZrrb + 887076U, // VCVTPS2QQZrrbk + 362596U, // VCVTPS2QQZrrbkz + 292U, // VCVTPS2QQZrrk + 100U, // VCVTPS2QQZrrkz + 0U, // VCVTPS2UDQZ128rm + 9U, // VCVTPS2UDQZ128rmb + 6884U, // VCVTPS2UDQZ128rmbk + 6596U, // VCVTPS2UDQZ128rmbkz + 260U, // VCVTPS2UDQZ128rmk + 356U, // VCVTPS2UDQZ128rmkz + 0U, // VCVTPS2UDQZ128rr + 292U, // VCVTPS2UDQZ128rrk + 100U, // VCVTPS2UDQZ128rrkz + 0U, // VCVTPS2UDQZ256rm + 10U, // VCVTPS2UDQZ256rmb + 8932U, // VCVTPS2UDQZ256rmbk + 8644U, // VCVTPS2UDQZ256rmbkz + 612U, // VCVTPS2UDQZ256rmk + 324U, // VCVTPS2UDQZ256rmkz + 0U, // VCVTPS2UDQZ256rr + 292U, // VCVTPS2UDQZ256rrk + 100U, // VCVTPS2UDQZ256rrkz + 0U, // VCVTPS2UDQZrm + 10U, // VCVTPS2UDQZrmb + 10980U, // VCVTPS2UDQZrmbk + 10692U, // VCVTPS2UDQZrmbkz + 1060U, // VCVTPS2UDQZrmk + 420U, // VCVTPS2UDQZrmkz + 0U, // VCVTPS2UDQZrr + 1024U, // VCVTPS2UDQZrrb + 887076U, // VCVTPS2UDQZrrbk + 362596U, // VCVTPS2UDQZrrbkz + 292U, // VCVTPS2UDQZrrk + 100U, // VCVTPS2UDQZrrkz + 0U, // VCVTPS2UQQZ128rm + 9U, // VCVTPS2UQQZ128rmb + 4836U, // VCVTPS2UQQZ128rmbk + 4548U, // VCVTPS2UQQZ128rmbkz + 580U, // VCVTPS2UQQZ128rmk + 388U, // VCVTPS2UQQZ128rmkz + 0U, // VCVTPS2UQQZ128rr + 292U, // VCVTPS2UQQZ128rrk + 100U, // VCVTPS2UQQZ128rrkz + 0U, // VCVTPS2UQQZ256rm + 9U, // VCVTPS2UQQZ256rmb + 6884U, // VCVTPS2UQQZ256rmbk + 6596U, // VCVTPS2UQQZ256rmbkz + 260U, // VCVTPS2UQQZ256rmk + 356U, // VCVTPS2UQQZ256rmkz + 0U, // VCVTPS2UQQZ256rr + 292U, // VCVTPS2UQQZ256rrk + 100U, // VCVTPS2UQQZ256rrkz + 0U, // VCVTPS2UQQZrm + 10U, // VCVTPS2UQQZrmb + 8932U, // VCVTPS2UQQZrmbk + 8644U, // VCVTPS2UQQZrmbkz + 612U, // VCVTPS2UQQZrmk + 324U, // VCVTPS2UQQZrmkz + 0U, // VCVTPS2UQQZrr + 1024U, // VCVTPS2UQQZrrb + 887076U, // VCVTPS2UQQZrrbk + 362596U, // VCVTPS2UQQZrrbkz + 292U, // VCVTPS2UQQZrrk + 100U, // VCVTPS2UQQZrrkz + 0U, // VCVTQQ2PDZ128rm + 9U, // VCVTQQ2PDZ128rmb + 4740U, // VCVTQQ2PDZ128rmbk + 4228U, // VCVTQQ2PDZ128rmbkz + 676U, // VCVTQQ2PDZ128rmk + 516U, // VCVTQQ2PDZ128rmkz + 0U, // VCVTQQ2PDZ128rr + 292U, // VCVTQQ2PDZ128rrk + 100U, // VCVTQQ2PDZ128rrkz + 0U, // VCVTQQ2PDZ256rm + 9U, // VCVTQQ2PDZ256rmb + 6788U, // VCVTQQ2PDZ256rmbk + 6276U, // VCVTQQ2PDZ256rmbkz + 708U, // VCVTQQ2PDZ256rmk + 484U, // VCVTQQ2PDZ256rmkz + 0U, // VCVTQQ2PDZ256rr + 292U, // VCVTQQ2PDZ256rrk + 100U, // VCVTQQ2PDZ256rrkz + 0U, // VCVTQQ2PDZrm + 10U, // VCVTQQ2PDZrmb + 8836U, // VCVTQQ2PDZrmbk + 8324U, // VCVTQQ2PDZrmbkz + 996U, // VCVTQQ2PDZrmk + 548U, // VCVTQQ2PDZrmkz + 0U, // VCVTQQ2PDZrr + 1024U, // VCVTQQ2PDZrrb + 887076U, // VCVTQQ2PDZrrbk + 362596U, // VCVTQQ2PDZrrbkz + 292U, // VCVTQQ2PDZrrk + 100U, // VCVTQQ2PDZrrkz + 0U, // VCVTQQ2PSZ128rm + 9U, // VCVTQQ2PSZ128rmb + 4740U, // VCVTQQ2PSZ128rmbk + 4228U, // VCVTQQ2PSZ128rmbkz + 676U, // VCVTQQ2PSZ128rmk + 516U, // VCVTQQ2PSZ128rmkz + 0U, // VCVTQQ2PSZ128rr + 292U, // VCVTQQ2PSZ128rrk + 100U, // VCVTQQ2PSZ128rrkz + 0U, // VCVTQQ2PSZ256rm + 9U, // VCVTQQ2PSZ256rmb + 6788U, // VCVTQQ2PSZ256rmbk + 6276U, // VCVTQQ2PSZ256rmbkz + 708U, // VCVTQQ2PSZ256rmk + 484U, // VCVTQQ2PSZ256rmkz + 0U, // VCVTQQ2PSZ256rr + 292U, // VCVTQQ2PSZ256rrk + 100U, // VCVTQQ2PSZ256rrkz + 0U, // VCVTQQ2PSZrm + 10U, // VCVTQQ2PSZrmb + 8836U, // VCVTQQ2PSZrmbk + 8324U, // VCVTQQ2PSZrmbkz + 996U, // VCVTQQ2PSZrmk + 548U, // VCVTQQ2PSZrmkz + 0U, // VCVTQQ2PSZrr + 1024U, // VCVTQQ2PSZrrb + 887076U, // VCVTQQ2PSZrrbk + 362596U, // VCVTQQ2PSZrrbkz + 292U, // VCVTQQ2PSZrrk + 100U, // VCVTQQ2PSZrrkz + 0U, // VCVTSD2SI64Zrm_Int + 0U, // VCVTSD2SI64Zrr_Int + 1024U, // VCVTSD2SI64Zrrb_Int + 0U, // VCVTSD2SI64rm_Int + 0U, // VCVTSD2SI64rr_Int + 0U, // VCVTSD2SIZrm_Int + 0U, // VCVTSD2SIZrr_Int + 1024U, // VCVTSD2SIZrrb_Int + 0U, // VCVTSD2SIrm_Int + 0U, // VCVTSD2SIrr_Int + 384U, // VCVTSD2SSZrm + 384U, // VCVTSD2SSZrm_Int + 67876U, // VCVTSD2SSZrm_Intk + 100452U, // VCVTSD2SSZrm_Intkz + 96U, // VCVTSD2SSZrr + 96U, // VCVTSD2SSZrr_Int + 166180U, // VCVTSD2SSZrr_Intk + 198756U, // VCVTSD2SSZrr_Intkz + 362592U, // VCVTSD2SSZrrb_Int + 4360484U, // VCVTSD2SSZrrb_Intk + 21170276U, // VCVTSD2SSZrrb_Intkz + 384U, // VCVTSD2SSrm + 384U, // VCVTSD2SSrm_Int + 96U, // VCVTSD2SSrr + 96U, // VCVTSD2SSrr_Int + 0U, // VCVTSD2USI64Zrm_Int + 0U, // VCVTSD2USI64Zrr_Int + 1024U, // VCVTSD2USI64Zrrb_Int + 0U, // VCVTSD2USIZrm_Int + 0U, // VCVTSD2USIZrr_Int + 1024U, // VCVTSD2USIZrrb_Int + 64U, // VCVTSI2SDZrm + 64U, // VCVTSI2SDZrm_Int + 96U, // VCVTSI2SDZrr + 96U, // VCVTSI2SDZrr_Int + 1088U, // VCVTSI2SDZrrb_Int + 64U, // VCVTSI2SDrm + 64U, // VCVTSI2SDrm_Int + 96U, // VCVTSI2SDrr + 96U, // VCVTSI2SDrr_Int + 64U, // VCVTSI2SSZrm + 64U, // VCVTSI2SSZrm_Int + 96U, // VCVTSI2SSZrr + 96U, // VCVTSI2SSZrr_Int + 1088U, // VCVTSI2SSZrrb_Int + 64U, // VCVTSI2SSrm + 64U, // VCVTSI2SSrm_Int + 96U, // VCVTSI2SSrr + 96U, // VCVTSI2SSrr_Int + 128U, // VCVTSI642SDZrm + 128U, // VCVTSI642SDZrm_Int + 96U, // VCVTSI642SDZrr + 96U, // VCVTSI642SDZrr_Int + 1088U, // VCVTSI642SDZrrb_Int + 128U, // VCVTSI642SDrm + 128U, // VCVTSI642SDrm_Int + 96U, // VCVTSI642SDrr + 96U, // VCVTSI642SDrr_Int + 128U, // VCVTSI642SSZrm + 128U, // VCVTSI642SSZrm_Int + 96U, // VCVTSI642SSZrr + 96U, // VCVTSI642SSZrr_Int + 1088U, // VCVTSI642SSZrrb_Int + 128U, // VCVTSI642SSrm + 128U, // VCVTSI642SSrm_Int + 96U, // VCVTSI642SSrr + 96U, // VCVTSI642SSrr_Int + 448U, // VCVTSS2SDZrm + 448U, // VCVTSS2SDZrm_Int + 395556U, // VCVTSS2SDZrm_Intk + 428132U, // VCVTSS2SDZrm_Intkz + 96U, // VCVTSS2SDZrr + 96U, // VCVTSS2SDZrr_Int + 166180U, // VCVTSS2SDZrr_Intk + 198756U, // VCVTSS2SDZrr_Intkz + 20576U, // VCVTSS2SDZrrb_Int + 11700516U, // VCVTSS2SDZrrb_Intk + 11733092U, // VCVTSS2SDZrrb_Intkz + 448U, // VCVTSS2SDrm + 448U, // VCVTSS2SDrm_Int + 96U, // VCVTSS2SDrr + 96U, // VCVTSS2SDrr_Int + 0U, // VCVTSS2SI64Zrm_Int + 0U, // VCVTSS2SI64Zrr_Int + 1024U, // VCVTSS2SI64Zrrb_Int + 0U, // VCVTSS2SI64rm_Int + 0U, // VCVTSS2SI64rr_Int + 0U, // VCVTSS2SIZrm_Int + 0U, // VCVTSS2SIZrr_Int + 1024U, // VCVTSS2SIZrrb_Int + 0U, // VCVTSS2SIrm_Int + 0U, // VCVTSS2SIrr_Int + 0U, // VCVTSS2USI64Zrm_Int + 0U, // VCVTSS2USI64Zrr_Int + 1024U, // VCVTSS2USI64Zrrb_Int + 0U, // VCVTSS2USIZrm_Int + 0U, // VCVTSS2USIZrr_Int + 1024U, // VCVTSS2USIZrrb_Int + 0U, // VCVTTPD2DQYrm + 0U, // VCVTTPD2DQYrr + 0U, // VCVTTPD2DQZ128rm + 9U, // VCVTTPD2DQZ128rmb + 4676U, // VCVTTPD2DQZ128rmbk + 4484U, // VCVTTPD2DQZ128rmbkz + 260U, // VCVTTPD2DQZ128rmk + 356U, // VCVTTPD2DQZ128rmkz + 0U, // VCVTTPD2DQZ128rr + 292U, // VCVTTPD2DQZ128rrk + 100U, // VCVTTPD2DQZ128rrkz + 0U, // VCVTTPD2DQZ256rm + 9U, // VCVTTPD2DQZ256rmb + 6724U, // VCVTTPD2DQZ256rmbk + 6532U, // VCVTTPD2DQZ256rmbkz + 612U, // VCVTTPD2DQZ256rmk + 324U, // VCVTTPD2DQZ256rmkz + 0U, // VCVTTPD2DQZ256rr + 292U, // VCVTTPD2DQZ256rrk + 100U, // VCVTTPD2DQZ256rrkz + 0U, // VCVTTPD2DQZrm + 10U, // VCVTTPD2DQZrmb + 8772U, // VCVTTPD2DQZrmbk + 8580U, // VCVTTPD2DQZrmbkz + 1060U, // VCVTTPD2DQZrmk + 420U, // VCVTTPD2DQZrmkz + 0U, // VCVTTPD2DQZrr + 8U, // VCVTTPD2DQZrrb + 20772U, // VCVTTPD2DQZrrbk + 20580U, // VCVTTPD2DQZrrbkz + 292U, // VCVTTPD2DQZrrk + 100U, // VCVTTPD2DQZrrkz + 0U, // VCVTTPD2DQrm + 0U, // VCVTTPD2DQrr + 0U, // VCVTTPD2QQZ128rm + 9U, // VCVTTPD2QQZ128rmb + 4676U, // VCVTTPD2QQZ128rmbk + 4484U, // VCVTTPD2QQZ128rmbkz + 260U, // VCVTTPD2QQZ128rmk + 356U, // VCVTTPD2QQZ128rmkz + 0U, // VCVTTPD2QQZ128rr + 292U, // VCVTTPD2QQZ128rrk + 100U, // VCVTTPD2QQZ128rrkz + 0U, // VCVTTPD2QQZ256rm + 9U, // VCVTTPD2QQZ256rmb + 6724U, // VCVTTPD2QQZ256rmbk + 6532U, // VCVTTPD2QQZ256rmbkz + 612U, // VCVTTPD2QQZ256rmk + 324U, // VCVTTPD2QQZ256rmkz + 0U, // VCVTTPD2QQZ256rr + 292U, // VCVTTPD2QQZ256rrk + 100U, // VCVTTPD2QQZ256rrkz + 0U, // VCVTTPD2QQZrm + 10U, // VCVTTPD2QQZrmb + 8772U, // VCVTTPD2QQZrmbk + 8580U, // VCVTTPD2QQZrmbkz + 1060U, // VCVTTPD2QQZrmk + 420U, // VCVTTPD2QQZrmkz + 0U, // VCVTTPD2QQZrr + 8U, // VCVTTPD2QQZrrb + 20772U, // VCVTTPD2QQZrrbk + 20580U, // VCVTTPD2QQZrrbkz + 292U, // VCVTTPD2QQZrrk + 100U, // VCVTTPD2QQZrrkz + 0U, // VCVTTPD2UDQZ128rm + 9U, // VCVTTPD2UDQZ128rmb + 4676U, // VCVTTPD2UDQZ128rmbk + 4484U, // VCVTTPD2UDQZ128rmbkz + 260U, // VCVTTPD2UDQZ128rmk + 356U, // VCVTTPD2UDQZ128rmkz + 0U, // VCVTTPD2UDQZ128rr + 292U, // VCVTTPD2UDQZ128rrk + 100U, // VCVTTPD2UDQZ128rrkz + 0U, // VCVTTPD2UDQZ256rm + 9U, // VCVTTPD2UDQZ256rmb + 6724U, // VCVTTPD2UDQZ256rmbk + 6532U, // VCVTTPD2UDQZ256rmbkz + 612U, // VCVTTPD2UDQZ256rmk + 324U, // VCVTTPD2UDQZ256rmkz + 0U, // VCVTTPD2UDQZ256rr + 292U, // VCVTTPD2UDQZ256rrk + 100U, // VCVTTPD2UDQZ256rrkz + 0U, // VCVTTPD2UDQZrm + 10U, // VCVTTPD2UDQZrmb + 8772U, // VCVTTPD2UDQZrmbk + 8580U, // VCVTTPD2UDQZrmbkz + 1060U, // VCVTTPD2UDQZrmk + 420U, // VCVTTPD2UDQZrmkz + 0U, // VCVTTPD2UDQZrr + 8U, // VCVTTPD2UDQZrrb + 20772U, // VCVTTPD2UDQZrrbk + 20580U, // VCVTTPD2UDQZrrbkz + 292U, // VCVTTPD2UDQZrrk + 100U, // VCVTTPD2UDQZrrkz + 0U, // VCVTTPD2UQQZ128rm + 9U, // VCVTTPD2UQQZ128rmb + 4676U, // VCVTTPD2UQQZ128rmbk + 4484U, // VCVTTPD2UQQZ128rmbkz + 260U, // VCVTTPD2UQQZ128rmk + 356U, // VCVTTPD2UQQZ128rmkz + 0U, // VCVTTPD2UQQZ128rr + 292U, // VCVTTPD2UQQZ128rrk + 100U, // VCVTTPD2UQQZ128rrkz + 0U, // VCVTTPD2UQQZ256rm + 9U, // VCVTTPD2UQQZ256rmb + 6724U, // VCVTTPD2UQQZ256rmbk + 6532U, // VCVTTPD2UQQZ256rmbkz + 612U, // VCVTTPD2UQQZ256rmk + 324U, // VCVTTPD2UQQZ256rmkz + 0U, // VCVTTPD2UQQZ256rr + 292U, // VCVTTPD2UQQZ256rrk + 100U, // VCVTTPD2UQQZ256rrkz + 0U, // VCVTTPD2UQQZrm + 10U, // VCVTTPD2UQQZrmb + 8772U, // VCVTTPD2UQQZrmbk + 8580U, // VCVTTPD2UQQZrmbkz + 1060U, // VCVTTPD2UQQZrmk + 420U, // VCVTTPD2UQQZrmkz + 0U, // VCVTTPD2UQQZrr + 8U, // VCVTTPD2UQQZrrb + 20772U, // VCVTTPD2UQQZrrbk + 20580U, // VCVTTPD2UQQZrrbkz + 292U, // VCVTTPD2UQQZrrk + 100U, // VCVTTPD2UQQZrrkz + 0U, // VCVTTPS2DQYrm + 0U, // VCVTTPS2DQYrr + 0U, // VCVTTPS2DQZ128rm + 9U, // VCVTTPS2DQZ128rmb + 6884U, // VCVTTPS2DQZ128rmbk + 6596U, // VCVTTPS2DQZ128rmbkz + 260U, // VCVTTPS2DQZ128rmk + 356U, // VCVTTPS2DQZ128rmkz + 0U, // VCVTTPS2DQZ128rr + 292U, // VCVTTPS2DQZ128rrk + 100U, // VCVTTPS2DQZ128rrkz + 0U, // VCVTTPS2DQZ256rm + 10U, // VCVTTPS2DQZ256rmb + 8932U, // VCVTTPS2DQZ256rmbk + 8644U, // VCVTTPS2DQZ256rmbkz + 612U, // VCVTTPS2DQZ256rmk + 324U, // VCVTTPS2DQZ256rmkz + 0U, // VCVTTPS2DQZ256rr + 292U, // VCVTTPS2DQZ256rrk + 100U, // VCVTTPS2DQZ256rrkz + 0U, // VCVTTPS2DQZrm + 10U, // VCVTTPS2DQZrmb + 10980U, // VCVTTPS2DQZrmbk + 10692U, // VCVTTPS2DQZrmbkz + 1060U, // VCVTTPS2DQZrmk + 420U, // VCVTTPS2DQZrmkz + 0U, // VCVTTPS2DQZrr + 8U, // VCVTTPS2DQZrrb + 20772U, // VCVTTPS2DQZrrbk + 20580U, // VCVTTPS2DQZrrbkz + 292U, // VCVTTPS2DQZrrk + 100U, // VCVTTPS2DQZrrkz + 0U, // VCVTTPS2DQrm + 0U, // VCVTTPS2DQrr + 0U, // VCVTTPS2QQZ128rm + 9U, // VCVTTPS2QQZ128rmb + 4836U, // VCVTTPS2QQZ128rmbk + 4548U, // VCVTTPS2QQZ128rmbkz + 580U, // VCVTTPS2QQZ128rmk + 388U, // VCVTTPS2QQZ128rmkz + 0U, // VCVTTPS2QQZ128rr + 292U, // VCVTTPS2QQZ128rrk + 100U, // VCVTTPS2QQZ128rrkz + 0U, // VCVTTPS2QQZ256rm + 9U, // VCVTTPS2QQZ256rmb + 6884U, // VCVTTPS2QQZ256rmbk + 6596U, // VCVTTPS2QQZ256rmbkz + 260U, // VCVTTPS2QQZ256rmk + 356U, // VCVTTPS2QQZ256rmkz + 0U, // VCVTTPS2QQZ256rr + 292U, // VCVTTPS2QQZ256rrk + 100U, // VCVTTPS2QQZ256rrkz + 0U, // VCVTTPS2QQZrm + 10U, // VCVTTPS2QQZrmb + 8932U, // VCVTTPS2QQZrmbk + 8644U, // VCVTTPS2QQZrmbkz + 612U, // VCVTTPS2QQZrmk + 324U, // VCVTTPS2QQZrmkz + 0U, // VCVTTPS2QQZrr + 8U, // VCVTTPS2QQZrrb + 20772U, // VCVTTPS2QQZrrbk + 20580U, // VCVTTPS2QQZrrbkz + 292U, // VCVTTPS2QQZrrk + 100U, // VCVTTPS2QQZrrkz + 0U, // VCVTTPS2UDQZ128rm + 9U, // VCVTTPS2UDQZ128rmb + 6884U, // VCVTTPS2UDQZ128rmbk + 6596U, // VCVTTPS2UDQZ128rmbkz + 260U, // VCVTTPS2UDQZ128rmk + 356U, // VCVTTPS2UDQZ128rmkz + 0U, // VCVTTPS2UDQZ128rr + 292U, // VCVTTPS2UDQZ128rrk + 100U, // VCVTTPS2UDQZ128rrkz + 0U, // VCVTTPS2UDQZ256rm + 10U, // VCVTTPS2UDQZ256rmb + 8932U, // VCVTTPS2UDQZ256rmbk + 8644U, // VCVTTPS2UDQZ256rmbkz + 612U, // VCVTTPS2UDQZ256rmk + 324U, // VCVTTPS2UDQZ256rmkz + 0U, // VCVTTPS2UDQZ256rr + 292U, // VCVTTPS2UDQZ256rrk + 100U, // VCVTTPS2UDQZ256rrkz + 0U, // VCVTTPS2UDQZrm + 10U, // VCVTTPS2UDQZrmb + 10980U, // VCVTTPS2UDQZrmbk + 10692U, // VCVTTPS2UDQZrmbkz + 1060U, // VCVTTPS2UDQZrmk + 420U, // VCVTTPS2UDQZrmkz + 0U, // VCVTTPS2UDQZrr + 8U, // VCVTTPS2UDQZrrb + 20772U, // VCVTTPS2UDQZrrbk + 20580U, // VCVTTPS2UDQZrrbkz + 292U, // VCVTTPS2UDQZrrk + 100U, // VCVTTPS2UDQZrrkz + 0U, // VCVTTPS2UQQZ128rm + 9U, // VCVTTPS2UQQZ128rmb + 4836U, // VCVTTPS2UQQZ128rmbk + 4548U, // VCVTTPS2UQQZ128rmbkz + 580U, // VCVTTPS2UQQZ128rmk + 388U, // VCVTTPS2UQQZ128rmkz + 0U, // VCVTTPS2UQQZ128rr + 292U, // VCVTTPS2UQQZ128rrk + 100U, // VCVTTPS2UQQZ128rrkz + 0U, // VCVTTPS2UQQZ256rm + 9U, // VCVTTPS2UQQZ256rmb + 6884U, // VCVTTPS2UQQZ256rmbk + 6596U, // VCVTTPS2UQQZ256rmbkz + 260U, // VCVTTPS2UQQZ256rmk + 356U, // VCVTTPS2UQQZ256rmkz + 0U, // VCVTTPS2UQQZ256rr + 292U, // VCVTTPS2UQQZ256rrk + 100U, // VCVTTPS2UQQZ256rrkz + 0U, // VCVTTPS2UQQZrm + 10U, // VCVTTPS2UQQZrmb + 8932U, // VCVTTPS2UQQZrmbk + 8644U, // VCVTTPS2UQQZrmbkz + 612U, // VCVTTPS2UQQZrmk + 324U, // VCVTTPS2UQQZrmkz + 0U, // VCVTTPS2UQQZrr + 8U, // VCVTTPS2UQQZrrb + 20772U, // VCVTTPS2UQQZrrbk + 20580U, // VCVTTPS2UQQZrrbkz + 292U, // VCVTTPS2UQQZrrk + 100U, // VCVTTPS2UQQZrrkz + 0U, // VCVTTSD2SI64Zrm + 0U, // VCVTTSD2SI64Zrm_Int + 0U, // VCVTTSD2SI64Zrr + 0U, // VCVTTSD2SI64Zrr_Int + 8U, // VCVTTSD2SI64Zrrb_Int + 0U, // VCVTTSD2SI64rm + 0U, // VCVTTSD2SI64rm_Int + 0U, // VCVTTSD2SI64rr + 0U, // VCVTTSD2SI64rr_Int + 0U, // VCVTTSD2SIZrm + 0U, // VCVTTSD2SIZrm_Int + 0U, // VCVTTSD2SIZrr + 0U, // VCVTTSD2SIZrr_Int + 8U, // VCVTTSD2SIZrrb_Int + 0U, // VCVTTSD2SIrm + 0U, // VCVTTSD2SIrm_Int + 0U, // VCVTTSD2SIrr + 0U, // VCVTTSD2SIrr_Int + 0U, // VCVTTSD2USI64Zrm + 0U, // VCVTTSD2USI64Zrm_Int + 0U, // VCVTTSD2USI64Zrr + 0U, // VCVTTSD2USI64Zrr_Int + 8U, // VCVTTSD2USI64Zrrb_Int + 0U, // VCVTTSD2USIZrm + 0U, // VCVTTSD2USIZrm_Int + 0U, // VCVTTSD2USIZrr + 0U, // VCVTTSD2USIZrr_Int + 8U, // VCVTTSD2USIZrrb_Int + 0U, // VCVTTSS2SI64Zrm + 0U, // VCVTTSS2SI64Zrm_Int + 0U, // VCVTTSS2SI64Zrr + 0U, // VCVTTSS2SI64Zrr_Int + 8U, // VCVTTSS2SI64Zrrb_Int + 0U, // VCVTTSS2SI64rm + 0U, // VCVTTSS2SI64rm_Int + 0U, // VCVTTSS2SI64rr + 0U, // VCVTTSS2SI64rr_Int + 0U, // VCVTTSS2SIZrm + 0U, // VCVTTSS2SIZrm_Int + 0U, // VCVTTSS2SIZrr + 0U, // VCVTTSS2SIZrr_Int + 8U, // VCVTTSS2SIZrrb_Int + 0U, // VCVTTSS2SIrm + 0U, // VCVTTSS2SIrm_Int + 0U, // VCVTTSS2SIrr + 0U, // VCVTTSS2SIrr_Int + 0U, // VCVTTSS2USI64Zrm + 0U, // VCVTTSS2USI64Zrm_Int + 0U, // VCVTTSS2USI64Zrr + 0U, // VCVTTSS2USI64Zrr_Int + 8U, // VCVTTSS2USI64Zrrb_Int + 0U, // VCVTTSS2USIZrm + 0U, // VCVTTSS2USIZrm_Int + 0U, // VCVTTSS2USIZrr + 0U, // VCVTTSS2USIZrr_Int + 8U, // VCVTTSS2USIZrrb_Int + 0U, // VCVTUDQ2PDZ128rm + 9U, // VCVTUDQ2PDZ128rmb + 5060U, // VCVTUDQ2PDZ128rmbk + 4164U, // VCVTUDQ2PDZ128rmbkz + 644U, // VCVTUDQ2PDZ128rmk + 132U, // VCVTUDQ2PDZ128rmkz + 0U, // VCVTUDQ2PDZ128rr + 292U, // VCVTUDQ2PDZ128rrk + 100U, // VCVTUDQ2PDZ128rrkz + 0U, // VCVTUDQ2PDZ256rm + 9U, // VCVTUDQ2PDZ256rmb + 7108U, // VCVTUDQ2PDZ256rmbk + 6212U, // VCVTUDQ2PDZ256rmbkz + 676U, // VCVTUDQ2PDZ256rmk + 516U, // VCVTUDQ2PDZ256rmkz + 0U, // VCVTUDQ2PDZ256rr + 292U, // VCVTUDQ2PDZ256rrk + 100U, // VCVTUDQ2PDZ256rrkz + 0U, // VCVTUDQ2PDZrm + 10U, // VCVTUDQ2PDZrmb + 9156U, // VCVTUDQ2PDZrmbk + 8260U, // VCVTUDQ2PDZrmbkz + 708U, // VCVTUDQ2PDZrmk + 484U, // VCVTUDQ2PDZrmkz + 0U, // VCVTUDQ2PDZrr + 292U, // VCVTUDQ2PDZrrk + 100U, // VCVTUDQ2PDZrrkz + 0U, // VCVTUDQ2PSZ128rm + 9U, // VCVTUDQ2PSZ128rmb + 7108U, // VCVTUDQ2PSZ128rmbk + 6212U, // VCVTUDQ2PSZ128rmbkz + 676U, // VCVTUDQ2PSZ128rmk + 516U, // VCVTUDQ2PSZ128rmkz + 0U, // VCVTUDQ2PSZ128rr + 292U, // VCVTUDQ2PSZ128rrk + 100U, // VCVTUDQ2PSZ128rrkz + 0U, // VCVTUDQ2PSZ256rm + 10U, // VCVTUDQ2PSZ256rmb + 9156U, // VCVTUDQ2PSZ256rmbk + 8260U, // VCVTUDQ2PSZ256rmbkz + 708U, // VCVTUDQ2PSZ256rmk + 484U, // VCVTUDQ2PSZ256rmkz + 0U, // VCVTUDQ2PSZ256rr + 292U, // VCVTUDQ2PSZ256rrk + 100U, // VCVTUDQ2PSZ256rrkz + 0U, // VCVTUDQ2PSZrm + 10U, // VCVTUDQ2PSZrmb + 11204U, // VCVTUDQ2PSZrmbk + 10308U, // VCVTUDQ2PSZrmbkz + 996U, // VCVTUDQ2PSZrmk + 548U, // VCVTUDQ2PSZrmkz + 0U, // VCVTUDQ2PSZrr + 1024U, // VCVTUDQ2PSZrrb + 887076U, // VCVTUDQ2PSZrrbk + 362596U, // VCVTUDQ2PSZrrbkz + 292U, // VCVTUDQ2PSZrrk + 100U, // VCVTUDQ2PSZrrkz + 0U, // VCVTUQQ2PDZ128rm + 9U, // VCVTUQQ2PDZ128rmb + 4740U, // VCVTUQQ2PDZ128rmbk + 4228U, // VCVTUQQ2PDZ128rmbkz + 676U, // VCVTUQQ2PDZ128rmk + 516U, // VCVTUQQ2PDZ128rmkz + 0U, // VCVTUQQ2PDZ128rr + 292U, // VCVTUQQ2PDZ128rrk + 100U, // VCVTUQQ2PDZ128rrkz + 0U, // VCVTUQQ2PDZ256rm + 9U, // VCVTUQQ2PDZ256rmb + 6788U, // VCVTUQQ2PDZ256rmbk + 6276U, // VCVTUQQ2PDZ256rmbkz + 708U, // VCVTUQQ2PDZ256rmk + 484U, // VCVTUQQ2PDZ256rmkz + 0U, // VCVTUQQ2PDZ256rr + 292U, // VCVTUQQ2PDZ256rrk + 100U, // VCVTUQQ2PDZ256rrkz + 0U, // VCVTUQQ2PDZrm + 10U, // VCVTUQQ2PDZrmb + 8836U, // VCVTUQQ2PDZrmbk + 8324U, // VCVTUQQ2PDZrmbkz + 996U, // VCVTUQQ2PDZrmk + 548U, // VCVTUQQ2PDZrmkz + 0U, // VCVTUQQ2PDZrr + 1024U, // VCVTUQQ2PDZrrb + 887076U, // VCVTUQQ2PDZrrbk + 362596U, // VCVTUQQ2PDZrrbkz + 292U, // VCVTUQQ2PDZrrk + 100U, // VCVTUQQ2PDZrrkz + 0U, // VCVTUQQ2PSZ128rm + 9U, // VCVTUQQ2PSZ128rmb + 4740U, // VCVTUQQ2PSZ128rmbk + 4228U, // VCVTUQQ2PSZ128rmbkz + 676U, // VCVTUQQ2PSZ128rmk + 516U, // VCVTUQQ2PSZ128rmkz + 0U, // VCVTUQQ2PSZ128rr + 292U, // VCVTUQQ2PSZ128rrk + 100U, // VCVTUQQ2PSZ128rrkz + 0U, // VCVTUQQ2PSZ256rm + 9U, // VCVTUQQ2PSZ256rmb + 6788U, // VCVTUQQ2PSZ256rmbk + 6276U, // VCVTUQQ2PSZ256rmbkz + 708U, // VCVTUQQ2PSZ256rmk + 484U, // VCVTUQQ2PSZ256rmkz + 0U, // VCVTUQQ2PSZ256rr + 292U, // VCVTUQQ2PSZ256rrk + 100U, // VCVTUQQ2PSZ256rrkz + 0U, // VCVTUQQ2PSZrm + 10U, // VCVTUQQ2PSZrmb + 8836U, // VCVTUQQ2PSZrmbk + 8324U, // VCVTUQQ2PSZrmbkz + 996U, // VCVTUQQ2PSZrmk + 548U, // VCVTUQQ2PSZrmkz + 0U, // VCVTUQQ2PSZrr + 1024U, // VCVTUQQ2PSZrrb + 887076U, // VCVTUQQ2PSZrrbk + 362596U, // VCVTUQQ2PSZrrbkz + 292U, // VCVTUQQ2PSZrrk + 100U, // VCVTUQQ2PSZrrkz + 64U, // VCVTUSI2SDZrm + 64U, // VCVTUSI2SDZrm_Int + 96U, // VCVTUSI2SDZrr + 96U, // VCVTUSI2SDZrr_Int + 64U, // VCVTUSI2SSZrm + 64U, // VCVTUSI2SSZrm_Int + 96U, // VCVTUSI2SSZrr + 96U, // VCVTUSI2SSZrr_Int + 1088U, // VCVTUSI2SSZrrb_Int + 128U, // VCVTUSI642SDZrm + 128U, // VCVTUSI642SDZrm_Int + 96U, // VCVTUSI642SDZrr + 96U, // VCVTUSI642SDZrr_Int + 1088U, // VCVTUSI642SDZrrb_Int + 128U, // VCVTUSI642SSZrm + 128U, // VCVTUSI642SSZrm_Int + 96U, // VCVTUSI642SSZrr + 96U, // VCVTUSI642SSZrr_Int + 1088U, // VCVTUSI642SSZrrb_Int + 461312U, // VDBPSADBWZ128rmi + 38308132U, // VDBPSADBWZ128rmik + 55117924U, // VDBPSADBWZ128rmikz + 624736U, // VDBPSADBWZ128rri + 71469348U, // VDBPSADBWZ128rrik + 88279140U, // VDBPSADBWZ128rrikz + 461280U, // VDBPSADBWZ256rmi + 38406436U, // VDBPSADBWZ256rmik + 55216228U, // VDBPSADBWZ256rmikz + 624736U, // VDBPSADBWZ256rri + 71469348U, // VDBPSADBWZ256rrik + 88279140U, // VDBPSADBWZ256rrikz + 461344U, // VDBPSADBWZrmi + 38471972U, // VDBPSADBWZrmik + 55281764U, // VDBPSADBWZrmikz + 624736U, // VDBPSADBWZrri + 71469348U, // VDBPSADBWZrrik + 88279140U, // VDBPSADBWZrrikz + 320U, // VDIVPDYrm + 96U, // VDIVPDYrr + 352U, // VDIVPDZ128rm + 4480U, // VDIVPDZ128rmb + 1116452U, // VDIVPDZ128rmbk + 1149028U, // VDIVPDZ128rmbkz + 35108U, // VDIVPDZ128rmk + 133220U, // VDIVPDZ128rmkz + 96U, // VDIVPDZ128rr + 166180U, // VDIVPDZ128rrk + 198756U, // VDIVPDZ128rrkz + 320U, // VDIVPDZ256rm + 6528U, // VDIVPDZ256rmb + 2165028U, // VDIVPDZ256rmbk + 2197604U, // VDIVPDZ256rmbkz + 231716U, // VDIVPDZ256rmk + 264292U, // VDIVPDZ256rmkz + 96U, // VDIVPDZ256rr + 166180U, // VDIVPDZ256rrk + 198756U, // VDIVPDZ256rrkz + 416U, // VDIVPDZrm + 8576U, // VDIVPDZrmb + 3213604U, // VDIVPDZrmbk + 3246180U, // VDIVPDZrmbkz + 297252U, // VDIVPDZrmk + 329828U, // VDIVPDZrmkz + 96U, // VDIVPDZrr + 362592U, // VDIVPDZrrb + 4360484U, // VDIVPDZrrbk + 21170276U, // VDIVPDZrrbkz + 166180U, // VDIVPDZrrk + 198756U, // VDIVPDZrrkz + 352U, // VDIVPDrm + 96U, // VDIVPDrr + 320U, // VDIVPSYrm + 96U, // VDIVPSYrr + 352U, // VDIVPSZ128rm + 6592U, // VDIVPSZ128rmb + 2492708U, // VDIVPSZ128rmbk + 2525284U, // VDIVPSZ128rmbkz + 35108U, // VDIVPSZ128rmk + 133220U, // VDIVPSZ128rmkz + 96U, // VDIVPSZ128rr + 166180U, // VDIVPSZ128rrk + 198756U, // VDIVPSZ128rrkz + 320U, // VDIVPSZ256rm + 8640U, // VDIVPSZ256rmb + 3541284U, // VDIVPSZ256rmbk + 3573860U, // VDIVPSZ256rmbkz + 231716U, // VDIVPSZ256rmk + 264292U, // VDIVPSZ256rmkz + 96U, // VDIVPSZ256rr + 166180U, // VDIVPSZ256rrk + 198756U, // VDIVPSZ256rrkz + 416U, // VDIVPSZrm + 10688U, // VDIVPSZrmb + 5638436U, // VDIVPSZrmbk + 5671012U, // VDIVPSZrmbkz + 297252U, // VDIVPSZrmk + 329828U, // VDIVPSZrmkz + 96U, // VDIVPSZrr + 362592U, // VDIVPSZrrb + 4360484U, // VDIVPSZrrbk + 21170276U, // VDIVPSZrrbkz + 166180U, // VDIVPSZrrk + 198756U, // VDIVPSZrrkz + 352U, // VDIVPSrm + 96U, // VDIVPSrr + 384U, // VDIVSDZrm + 384U, // VDIVSDZrm_Int + 67876U, // VDIVSDZrm_Intk + 100452U, // VDIVSDZrm_Intkz + 96U, // VDIVSDZrr + 96U, // VDIVSDZrr_Int + 166180U, // VDIVSDZrr_Intk + 198756U, // VDIVSDZrr_Intkz + 362592U, // VDIVSDZrrb_Int + 4360484U, // VDIVSDZrrb_Intk + 21170276U, // VDIVSDZrrb_Intkz + 384U, // VDIVSDrm + 384U, // VDIVSDrm_Int + 96U, // VDIVSDrr + 96U, // VDIVSDrr_Int + 448U, // VDIVSSZrm + 448U, // VDIVSSZrm_Int + 395556U, // VDIVSSZrm_Intk + 428132U, // VDIVSSZrm_Intkz + 96U, // VDIVSSZrr + 96U, // VDIVSSZrr_Int + 166180U, // VDIVSSZrr_Intk + 198756U, // VDIVSSZrr_Intkz + 362592U, // VDIVSSZrrb_Int + 4360484U, // VDIVSSZrrb_Intk + 21170276U, // VDIVSSZrrb_Intkz + 448U, // VDIVSSrm + 448U, // VDIVSSrm_Int + 96U, // VDIVSSrr + 96U, // VDIVSSrr_Int + 461152U, // VDPPDrmi + 624736U, // VDPPDrri + 461280U, // VDPPSYrmi + 624736U, // VDPPSYrri + 461152U, // VDPPSrmi + 624736U, // VDPPSrri + 0U, // VERRm + 0U, // VERRr + 0U, // VERWm + 0U, // VERWr + 0U, // VEXP2PDZm + 10U, // VEXP2PDZmb + 8772U, // VEXP2PDZmbk + 8580U, // VEXP2PDZmbkz + 1060U, // VEXP2PDZmk + 420U, // VEXP2PDZmkz + 0U, // VEXP2PDZr + 8U, // VEXP2PDZrb + 20772U, // VEXP2PDZrbk + 20580U, // VEXP2PDZrbkz + 292U, // VEXP2PDZrk + 100U, // VEXP2PDZrkz + 0U, // VEXP2PSZm + 10U, // VEXP2PSZmb + 10980U, // VEXP2PSZmbk + 10692U, // VEXP2PSZmbkz + 1060U, // VEXP2PSZmk + 420U, // VEXP2PSZmkz + 0U, // VEXP2PSZr + 8U, // VEXP2PSZrb + 20772U, // VEXP2PSZrbk + 20580U, // VEXP2PSZrbkz + 292U, // VEXP2PSZrk + 100U, // VEXP2PSZrkz + 0U, // VEXPANDPDZ128rm + 260U, // VEXPANDPDZ128rmk + 356U, // VEXPANDPDZ128rmkz + 0U, // VEXPANDPDZ128rr + 292U, // VEXPANDPDZ128rrk + 100U, // VEXPANDPDZ128rrkz + 0U, // VEXPANDPDZ256rm + 612U, // VEXPANDPDZ256rmk + 324U, // VEXPANDPDZ256rmkz + 0U, // VEXPANDPDZ256rr + 292U, // VEXPANDPDZ256rrk + 100U, // VEXPANDPDZ256rrkz + 0U, // VEXPANDPDZrm + 1060U, // VEXPANDPDZrmk + 420U, // VEXPANDPDZrmkz + 0U, // VEXPANDPDZrr + 292U, // VEXPANDPDZrrk + 100U, // VEXPANDPDZrrkz + 0U, // VEXPANDPSZ128rm + 260U, // VEXPANDPSZ128rmk + 356U, // VEXPANDPSZ128rmkz + 0U, // VEXPANDPSZ128rr + 292U, // VEXPANDPSZ128rrk + 100U, // VEXPANDPSZ128rrkz + 0U, // VEXPANDPSZ256rm + 612U, // VEXPANDPSZ256rmk + 324U, // VEXPANDPSZ256rmkz + 0U, // VEXPANDPSZ256rr + 292U, // VEXPANDPSZ256rrk + 100U, // VEXPANDPSZ256rrkz + 0U, // VEXPANDPSZrm + 1060U, // VEXPANDPSZrmk + 420U, // VEXPANDPSZrmkz + 0U, // VEXPANDPSZrr + 292U, // VEXPANDPSZrrk + 100U, // VEXPANDPSZrrkz + 0U, // VEXTRACTF128mr + 32U, // VEXTRACTF128rr + 0U, // VEXTRACTF32x4Z256mr + 460964U, // VEXTRACTF32x4Z256mrk + 32U, // VEXTRACTF32x4Z256rr + 2340U, // VEXTRACTF32x4Z256rrk + 624740U, // VEXTRACTF32x4Z256rrkz + 0U, // VEXTRACTF32x4Zmr + 460964U, // VEXTRACTF32x4Zmrk + 32U, // VEXTRACTF32x4Zrr + 2340U, // VEXTRACTF32x4Zrrk + 624740U, // VEXTRACTF32x4Zrrkz + 0U, // VEXTRACTF32x8Zmr + 460964U, // VEXTRACTF32x8Zmrk + 32U, // VEXTRACTF32x8Zrr + 2340U, // VEXTRACTF32x8Zrrk + 624740U, // VEXTRACTF32x8Zrrkz + 0U, // VEXTRACTF64x2Z256mr + 460964U, // VEXTRACTF64x2Z256mrk + 32U, // VEXTRACTF64x2Z256rr + 2340U, // VEXTRACTF64x2Z256rrk + 624740U, // VEXTRACTF64x2Z256rrkz + 0U, // VEXTRACTF64x2Zmr + 460964U, // VEXTRACTF64x2Zmrk + 32U, // VEXTRACTF64x2Zrr + 2340U, // VEXTRACTF64x2Zrrk + 624740U, // VEXTRACTF64x2Zrrkz + 0U, // VEXTRACTF64x4Zmr + 460964U, // VEXTRACTF64x4Zmrk + 32U, // VEXTRACTF64x4Zrr + 2340U, // VEXTRACTF64x4Zrrk + 624740U, // VEXTRACTF64x4Zrrkz + 0U, // VEXTRACTI128mr + 32U, // VEXTRACTI128rr + 0U, // VEXTRACTI32x4Z256mr + 460964U, // VEXTRACTI32x4Z256mrk + 32U, // VEXTRACTI32x4Z256rr + 2340U, // VEXTRACTI32x4Z256rrk + 624740U, // VEXTRACTI32x4Z256rrkz + 0U, // VEXTRACTI32x4Zmr + 460964U, // VEXTRACTI32x4Zmrk + 32U, // VEXTRACTI32x4Zrr + 2340U, // VEXTRACTI32x4Zrrk + 624740U, // VEXTRACTI32x4Zrrkz + 0U, // VEXTRACTI32x8Zmr + 460964U, // VEXTRACTI32x8Zmrk + 32U, // VEXTRACTI32x8Zrr + 2340U, // VEXTRACTI32x8Zrrk + 624740U, // VEXTRACTI32x8Zrrkz + 0U, // VEXTRACTI64x2Z256mr + 460964U, // VEXTRACTI64x2Z256mrk + 32U, // VEXTRACTI64x2Z256rr + 2340U, // VEXTRACTI64x2Z256rrk + 624740U, // VEXTRACTI64x2Z256rrkz + 0U, // VEXTRACTI64x2Zmr + 460964U, // VEXTRACTI64x2Zmrk + 32U, // VEXTRACTI64x2Zrr + 2340U, // VEXTRACTI64x2Zrrk + 624740U, // VEXTRACTI64x2Zrrkz + 0U, // VEXTRACTI64x4Zmr + 460964U, // VEXTRACTI64x4Zmrk + 32U, // VEXTRACTI64x4Zrr + 2340U, // VEXTRACTI64x4Zrrk + 624740U, // VEXTRACTI64x4Zrrkz + 0U, // VEXTRACTPSZmr + 32U, // VEXTRACTPSZrr + 0U, // VEXTRACTPSmr + 32U, // VEXTRACTPSrr + 936512U, // VFIXUPIMMPDZ128rmbi + 43059492U, // VFIXUPIMMPDZ128rmbik + 43059492U, // VFIXUPIMMPDZ128rmbikz + 919808U, // VFIXUPIMMPDZ128rmi + 37783844U, // VFIXUPIMMPDZ128rmik + 37783844U, // VFIXUPIMMPDZ128rmikz + 2336U, // VFIXUPIMMPDZ128rri + 71469348U, // VFIXUPIMMPDZ128rrik + 71469348U, // VFIXUPIMMPDZ128rrikz + 930368U, // VFIXUPIMMPDZ256rmbi + 39913764U, // VFIXUPIMMPDZ256rmbik + 39913764U, // VFIXUPIMMPDZ256rmbikz + 920160U, // VFIXUPIMMPDZ256rmi + 37980452U, // VFIXUPIMMPDZ256rmik + 37980452U, // VFIXUPIMMPDZ256rmikz + 2336U, // VFIXUPIMMPDZ256rri + 71469348U, // VFIXUPIMMPDZ256rrik + 71469348U, // VFIXUPIMMPDZ256rrikz + 932416U, // VFIXUPIMMPDZrmbi + 40962340U, // VFIXUPIMMPDZrmbik + 40962340U, // VFIXUPIMMPDZrmbikz + 920608U, // VFIXUPIMMPDZrmi + 38045988U, // VFIXUPIMMPDZrmik + 38045988U, // VFIXUPIMMPDZrmikz + 2336U, // VFIXUPIMMPDZrri + 22816U, // VFIXUPIMMPDZrrib + 77760804U, // VFIXUPIMMPDZrribk + 77760804U, // VFIXUPIMMPDZrribkz + 71469348U, // VFIXUPIMMPDZrrik + 71469348U, // VFIXUPIMMPDZrrikz + 930528U, // VFIXUPIMMPSZ128rmbi + 40241444U, // VFIXUPIMMPSZ128rmbik + 40241444U, // VFIXUPIMMPSZ128rmbikz + 919808U, // VFIXUPIMMPSZ128rmi + 37783844U, // VFIXUPIMMPSZ128rmik + 37783844U, // VFIXUPIMMPSZ128rmikz + 2336U, // VFIXUPIMMPSZ128rri + 71469348U, // VFIXUPIMMPSZ128rrik + 71469348U, // VFIXUPIMMPSZ128rrikz + 932576U, // VFIXUPIMMPSZ256rmbi + 41290020U, // VFIXUPIMMPSZ256rmbik + 41290020U, // VFIXUPIMMPSZ256rmbikz + 920160U, // VFIXUPIMMPSZ256rmi + 37980452U, // VFIXUPIMMPSZ256rmik + 37980452U, // VFIXUPIMMPSZ256rmikz + 2336U, // VFIXUPIMMPSZ256rri + 71469348U, // VFIXUPIMMPSZ256rrik + 71469348U, // VFIXUPIMMPSZ256rrikz + 934624U, // VFIXUPIMMPSZrmbi + 42338596U, // VFIXUPIMMPSZrmbik + 42338596U, // VFIXUPIMMPSZrmbikz + 920608U, // VFIXUPIMMPSZrmi + 38045988U, // VFIXUPIMMPSZrmik + 38045988U, // VFIXUPIMMPSZrmikz + 2336U, // VFIXUPIMMPSZrri + 22816U, // VFIXUPIMMPSZrrib + 77760804U, // VFIXUPIMMPSZrribk + 77760804U, // VFIXUPIMMPSZrribkz + 71469348U, // VFIXUPIMMPSZrrik + 71469348U, // VFIXUPIMMPSZrrikz + 920128U, // VFIXUPIMMSDZrmi + 37816612U, // VFIXUPIMMSDZrmik + 37816612U, // VFIXUPIMMSDZrmikz + 2336U, // VFIXUPIMMSDZrri + 22816U, // VFIXUPIMMSDZrrib + 77760804U, // VFIXUPIMMSDZrribk + 77760804U, // VFIXUPIMMSDZrribkz + 71469348U, // VFIXUPIMMSDZrrik + 71469348U, // VFIXUPIMMSDZrrikz + 920288U, // VFIXUPIMMSSZrmi + 38144292U, // VFIXUPIMMSSZrmik + 38144292U, // VFIXUPIMMSSZrmikz + 2336U, // VFIXUPIMMSSZrri + 22816U, // VFIXUPIMMSSZrrib + 77760804U, // VFIXUPIMMSSZrribk + 77760804U, // VFIXUPIMMSSZrribkz + 71469348U, // VFIXUPIMMSSZrrik + 71469348U, // VFIXUPIMMSSZrrikz + 608U, // VFMADD132PDYm + 288U, // VFMADD132PDYr + 256U, // VFMADD132PDZ128m + 4672U, // VFMADD132PDZ128mb + 1116452U, // VFMADD132PDZ128mbk + 1116452U, // VFMADD132PDZ128mbkz + 35108U, // VFMADD132PDZ128mk + 35108U, // VFMADD132PDZ128mkz + 288U, // VFMADD132PDZ128r + 166180U, // VFMADD132PDZ128rk + 166180U, // VFMADD132PDZ128rkz + 608U, // VFMADD132PDZ256m + 6720U, // VFMADD132PDZ256mb + 2165028U, // VFMADD132PDZ256mbk + 2165028U, // VFMADD132PDZ256mbkz + 231716U, // VFMADD132PDZ256mk + 231716U, // VFMADD132PDZ256mkz + 288U, // VFMADD132PDZ256r + 166180U, // VFMADD132PDZ256rk + 166180U, // VFMADD132PDZ256rkz + 1056U, // VFMADD132PDZm + 8768U, // VFMADD132PDZmb + 3213604U, // VFMADD132PDZmbk + 3213604U, // VFMADD132PDZmbkz + 297252U, // VFMADD132PDZmk + 297252U, // VFMADD132PDZmkz + 288U, // VFMADD132PDZr + 887072U, // VFMADD132PDZrb + 4360484U, // VFMADD132PDZrbk + 4360484U, // VFMADD132PDZrbkz + 166180U, // VFMADD132PDZrk + 166180U, // VFMADD132PDZrkz + 256U, // VFMADD132PDm + 288U, // VFMADD132PDr + 608U, // VFMADD132PSYm + 288U, // VFMADD132PSYr + 256U, // VFMADD132PSZ128m + 6880U, // VFMADD132PSZ128mb + 2492708U, // VFMADD132PSZ128mbk + 2492708U, // VFMADD132PSZ128mbkz + 35108U, // VFMADD132PSZ128mk + 35108U, // VFMADD132PSZ128mkz + 288U, // VFMADD132PSZ128r + 166180U, // VFMADD132PSZ128rk + 166180U, // VFMADD132PSZ128rkz + 608U, // VFMADD132PSZ256m + 8928U, // VFMADD132PSZ256mb + 3541284U, // VFMADD132PSZ256mbk + 3541284U, // VFMADD132PSZ256mbkz + 231716U, // VFMADD132PSZ256mk + 231716U, // VFMADD132PSZ256mkz + 288U, // VFMADD132PSZ256r + 166180U, // VFMADD132PSZ256rk + 166180U, // VFMADD132PSZ256rkz + 1056U, // VFMADD132PSZm + 10976U, // VFMADD132PSZmb + 5638436U, // VFMADD132PSZmbk + 5638436U, // VFMADD132PSZmbkz + 297252U, // VFMADD132PSZmk + 297252U, // VFMADD132PSZmkz + 288U, // VFMADD132PSZr + 887072U, // VFMADD132PSZrb + 4360484U, // VFMADD132PSZrbk + 4360484U, // VFMADD132PSZrbkz + 166180U, // VFMADD132PSZrk + 166180U, // VFMADD132PSZrkz + 256U, // VFMADD132PSm + 288U, // VFMADD132PSr + 576U, // VFMADD132SDZm + 576U, // VFMADD132SDZm_Int + 67876U, // VFMADD132SDZm_Intk + 67876U, // VFMADD132SDZm_Intkz + 288U, // VFMADD132SDZr + 288U, // VFMADD132SDZr_Int + 166180U, // VFMADD132SDZr_Intk + 166180U, // VFMADD132SDZr_Intkz + 288U, // VFMADD132SDZrb + 887072U, // VFMADD132SDZrb_Int + 4360484U, // VFMADD132SDZrb_Intk + 4360484U, // VFMADD132SDZrb_Intkz + 576U, // VFMADD132SDm + 576U, // VFMADD132SDm_Int + 288U, // VFMADD132SDr + 288U, // VFMADD132SDr_Int + 736U, // VFMADD132SSZm + 736U, // VFMADD132SSZm_Int + 395556U, // VFMADD132SSZm_Intk + 395556U, // VFMADD132SSZm_Intkz + 288U, // VFMADD132SSZr + 288U, // VFMADD132SSZr_Int + 166180U, // VFMADD132SSZr_Intk + 166180U, // VFMADD132SSZr_Intkz + 288U, // VFMADD132SSZrb + 887072U, // VFMADD132SSZrb_Int + 4360484U, // VFMADD132SSZrb_Intk + 4360484U, // VFMADD132SSZrb_Intkz + 736U, // VFMADD132SSm + 736U, // VFMADD132SSm_Int + 288U, // VFMADD132SSr + 288U, // VFMADD132SSr_Int + 608U, // VFMADD213PDYm + 288U, // VFMADD213PDYr + 256U, // VFMADD213PDZ128m + 4672U, // VFMADD213PDZ128mb + 1116452U, // VFMADD213PDZ128mbk + 1116452U, // VFMADD213PDZ128mbkz + 35108U, // VFMADD213PDZ128mk + 35108U, // VFMADD213PDZ128mkz + 288U, // VFMADD213PDZ128r + 166180U, // VFMADD213PDZ128rk + 166180U, // VFMADD213PDZ128rkz + 608U, // VFMADD213PDZ256m + 6720U, // VFMADD213PDZ256mb + 2165028U, // VFMADD213PDZ256mbk + 2165028U, // VFMADD213PDZ256mbkz + 231716U, // VFMADD213PDZ256mk + 231716U, // VFMADD213PDZ256mkz + 288U, // VFMADD213PDZ256r + 166180U, // VFMADD213PDZ256rk + 166180U, // VFMADD213PDZ256rkz + 1056U, // VFMADD213PDZm + 8768U, // VFMADD213PDZmb + 3213604U, // VFMADD213PDZmbk + 3213604U, // VFMADD213PDZmbkz + 297252U, // VFMADD213PDZmk + 297252U, // VFMADD213PDZmkz + 288U, // VFMADD213PDZr + 887072U, // VFMADD213PDZrb + 4360484U, // VFMADD213PDZrbk + 4360484U, // VFMADD213PDZrbkz + 166180U, // VFMADD213PDZrk + 166180U, // VFMADD213PDZrkz + 256U, // VFMADD213PDm + 288U, // VFMADD213PDr + 608U, // VFMADD213PSYm + 288U, // VFMADD213PSYr + 256U, // VFMADD213PSZ128m + 6880U, // VFMADD213PSZ128mb + 2492708U, // VFMADD213PSZ128mbk + 2492708U, // VFMADD213PSZ128mbkz + 35108U, // VFMADD213PSZ128mk + 35108U, // VFMADD213PSZ128mkz + 288U, // VFMADD213PSZ128r + 166180U, // VFMADD213PSZ128rk + 166180U, // VFMADD213PSZ128rkz + 608U, // VFMADD213PSZ256m + 8928U, // VFMADD213PSZ256mb + 3541284U, // VFMADD213PSZ256mbk + 3541284U, // VFMADD213PSZ256mbkz + 231716U, // VFMADD213PSZ256mk + 231716U, // VFMADD213PSZ256mkz + 288U, // VFMADD213PSZ256r + 166180U, // VFMADD213PSZ256rk + 166180U, // VFMADD213PSZ256rkz + 1056U, // VFMADD213PSZm + 10976U, // VFMADD213PSZmb + 5638436U, // VFMADD213PSZmbk + 5638436U, // VFMADD213PSZmbkz + 297252U, // VFMADD213PSZmk + 297252U, // VFMADD213PSZmkz + 288U, // VFMADD213PSZr + 887072U, // VFMADD213PSZrb + 4360484U, // VFMADD213PSZrbk + 4360484U, // VFMADD213PSZrbkz + 166180U, // VFMADD213PSZrk + 166180U, // VFMADD213PSZrkz + 256U, // VFMADD213PSm + 288U, // VFMADD213PSr + 576U, // VFMADD213SDZm + 576U, // VFMADD213SDZm_Int + 67876U, // VFMADD213SDZm_Intk + 67876U, // VFMADD213SDZm_Intkz + 288U, // VFMADD213SDZr + 288U, // VFMADD213SDZr_Int + 166180U, // VFMADD213SDZr_Intk + 166180U, // VFMADD213SDZr_Intkz + 288U, // VFMADD213SDZrb + 887072U, // VFMADD213SDZrb_Int + 4360484U, // VFMADD213SDZrb_Intk + 4360484U, // VFMADD213SDZrb_Intkz + 576U, // VFMADD213SDm + 576U, // VFMADD213SDm_Int + 288U, // VFMADD213SDr + 288U, // VFMADD213SDr_Int + 736U, // VFMADD213SSZm + 736U, // VFMADD213SSZm_Int + 395556U, // VFMADD213SSZm_Intk + 395556U, // VFMADD213SSZm_Intkz + 288U, // VFMADD213SSZr + 288U, // VFMADD213SSZr_Int + 166180U, // VFMADD213SSZr_Intk + 166180U, // VFMADD213SSZr_Intkz + 288U, // VFMADD213SSZrb + 887072U, // VFMADD213SSZrb_Int + 4360484U, // VFMADD213SSZrb_Intk + 4360484U, // VFMADD213SSZrb_Intkz + 736U, // VFMADD213SSm + 736U, // VFMADD213SSm_Int + 288U, // VFMADD213SSr + 288U, // VFMADD213SSr_Int + 608U, // VFMADD231PDYm + 288U, // VFMADD231PDYr + 256U, // VFMADD231PDZ128m + 4672U, // VFMADD231PDZ128mb + 1116452U, // VFMADD231PDZ128mbk + 1116452U, // VFMADD231PDZ128mbkz + 35108U, // VFMADD231PDZ128mk + 35108U, // VFMADD231PDZ128mkz + 288U, // VFMADD231PDZ128r + 166180U, // VFMADD231PDZ128rk + 166180U, // VFMADD231PDZ128rkz + 608U, // VFMADD231PDZ256m + 6720U, // VFMADD231PDZ256mb + 2165028U, // VFMADD231PDZ256mbk + 2165028U, // VFMADD231PDZ256mbkz + 231716U, // VFMADD231PDZ256mk + 231716U, // VFMADD231PDZ256mkz + 288U, // VFMADD231PDZ256r + 166180U, // VFMADD231PDZ256rk + 166180U, // VFMADD231PDZ256rkz + 1056U, // VFMADD231PDZm + 8768U, // VFMADD231PDZmb + 3213604U, // VFMADD231PDZmbk + 3213604U, // VFMADD231PDZmbkz + 297252U, // VFMADD231PDZmk + 297252U, // VFMADD231PDZmkz + 288U, // VFMADD231PDZr + 887072U, // VFMADD231PDZrb + 4360484U, // VFMADD231PDZrbk + 4360484U, // VFMADD231PDZrbkz + 166180U, // VFMADD231PDZrk + 166180U, // VFMADD231PDZrkz + 256U, // VFMADD231PDm + 288U, // VFMADD231PDr + 608U, // VFMADD231PSYm + 288U, // VFMADD231PSYr + 256U, // VFMADD231PSZ128m + 6880U, // VFMADD231PSZ128mb + 2492708U, // VFMADD231PSZ128mbk + 2492708U, // VFMADD231PSZ128mbkz + 35108U, // VFMADD231PSZ128mk + 35108U, // VFMADD231PSZ128mkz + 288U, // VFMADD231PSZ128r + 166180U, // VFMADD231PSZ128rk + 166180U, // VFMADD231PSZ128rkz + 608U, // VFMADD231PSZ256m + 8928U, // VFMADD231PSZ256mb + 3541284U, // VFMADD231PSZ256mbk + 3541284U, // VFMADD231PSZ256mbkz + 231716U, // VFMADD231PSZ256mk + 231716U, // VFMADD231PSZ256mkz + 288U, // VFMADD231PSZ256r + 166180U, // VFMADD231PSZ256rk + 166180U, // VFMADD231PSZ256rkz + 1056U, // VFMADD231PSZm + 10976U, // VFMADD231PSZmb + 5638436U, // VFMADD231PSZmbk + 5638436U, // VFMADD231PSZmbkz + 297252U, // VFMADD231PSZmk + 297252U, // VFMADD231PSZmkz + 288U, // VFMADD231PSZr + 887072U, // VFMADD231PSZrb + 4360484U, // VFMADD231PSZrbk + 4360484U, // VFMADD231PSZrbkz + 166180U, // VFMADD231PSZrk + 166180U, // VFMADD231PSZrkz + 256U, // VFMADD231PSm + 288U, // VFMADD231PSr + 576U, // VFMADD231SDZm + 576U, // VFMADD231SDZm_Int + 67876U, // VFMADD231SDZm_Intk + 67876U, // VFMADD231SDZm_Intkz + 288U, // VFMADD231SDZr + 288U, // VFMADD231SDZr_Int + 166180U, // VFMADD231SDZr_Intk + 166180U, // VFMADD231SDZr_Intkz + 288U, // VFMADD231SDZrb + 887072U, // VFMADD231SDZrb_Int + 4360484U, // VFMADD231SDZrb_Intk + 4360484U, // VFMADD231SDZrb_Intkz + 576U, // VFMADD231SDm + 576U, // VFMADD231SDm_Int + 288U, // VFMADD231SDr + 288U, // VFMADD231SDr_Int + 736U, // VFMADD231SSZm + 736U, // VFMADD231SSZm_Int + 395556U, // VFMADD231SSZm_Intk + 395556U, // VFMADD231SSZm_Intkz + 288U, // VFMADD231SSZr + 288U, // VFMADD231SSZr_Int + 166180U, // VFMADD231SSZr_Intk + 166180U, // VFMADD231SSZr_Intkz + 288U, // VFMADD231SSZrb + 887072U, // VFMADD231SSZrb_Int + 4360484U, // VFMADD231SSZrb_Intk + 4360484U, // VFMADD231SSZrb_Intkz + 736U, // VFMADD231SSm + 736U, // VFMADD231SSm_Int + 288U, // VFMADD231SSr + 288U, // VFMADD231SSr_Int + 854336U, // VFMADDPD4Ymr + 264288U, // VFMADDPD4Yrm + 198752U, // VFMADDPD4Yrr + 198752U, // VFMADDPD4Yrr_REV + 854368U, // VFMADDPD4mr + 133216U, // VFMADDPD4rm + 198752U, // VFMADDPD4rr + 198752U, // VFMADDPD4rr_REV + 854336U, // VFMADDPS4Ymr + 264288U, // VFMADDPS4Yrm + 198752U, // VFMADDPS4Yrr + 198752U, // VFMADDPS4Yrr_REV + 854368U, // VFMADDPS4mr + 133216U, // VFMADDPS4rm + 198752U, // VFMADDPS4rr + 198752U, // VFMADDPS4rr_REV + 854400U, // VFMADDSD4mr + 854400U, // VFMADDSD4mr_Int + 100448U, // VFMADDSD4rm + 100448U, // VFMADDSD4rm_Int + 198752U, // VFMADDSD4rr + 198752U, // VFMADDSD4rr_Int + 198752U, // VFMADDSD4rr_Int_REV + 198752U, // VFMADDSD4rr_REV + 854464U, // VFMADDSS4mr + 854464U, // VFMADDSS4mr_Int + 428128U, // VFMADDSS4rm + 428128U, // VFMADDSS4rm_Int + 198752U, // VFMADDSS4rr + 198752U, // VFMADDSS4rr_Int + 198752U, // VFMADDSS4rr_Int_REV + 198752U, // VFMADDSS4rr_REV + 608U, // VFMADDSUB132PDYm + 288U, // VFMADDSUB132PDYr + 256U, // VFMADDSUB132PDZ128m + 4672U, // VFMADDSUB132PDZ128mb + 1116452U, // VFMADDSUB132PDZ128mbk + 1116452U, // VFMADDSUB132PDZ128mbkz + 35108U, // VFMADDSUB132PDZ128mk + 35108U, // VFMADDSUB132PDZ128mkz + 288U, // VFMADDSUB132PDZ128r + 166180U, // VFMADDSUB132PDZ128rk + 166180U, // VFMADDSUB132PDZ128rkz + 608U, // VFMADDSUB132PDZ256m + 6720U, // VFMADDSUB132PDZ256mb + 2165028U, // VFMADDSUB132PDZ256mbk + 2165028U, // VFMADDSUB132PDZ256mbkz + 231716U, // VFMADDSUB132PDZ256mk + 231716U, // VFMADDSUB132PDZ256mkz + 288U, // VFMADDSUB132PDZ256r + 166180U, // VFMADDSUB132PDZ256rk + 166180U, // VFMADDSUB132PDZ256rkz + 1056U, // VFMADDSUB132PDZm + 8768U, // VFMADDSUB132PDZmb + 3213604U, // VFMADDSUB132PDZmbk + 3213604U, // VFMADDSUB132PDZmbkz + 297252U, // VFMADDSUB132PDZmk + 297252U, // VFMADDSUB132PDZmkz + 288U, // VFMADDSUB132PDZr + 887072U, // VFMADDSUB132PDZrb + 4360484U, // VFMADDSUB132PDZrbk + 4360484U, // VFMADDSUB132PDZrbkz + 166180U, // VFMADDSUB132PDZrk + 166180U, // VFMADDSUB132PDZrkz + 256U, // VFMADDSUB132PDm + 288U, // VFMADDSUB132PDr + 608U, // VFMADDSUB132PSYm + 288U, // VFMADDSUB132PSYr + 256U, // VFMADDSUB132PSZ128m + 6880U, // VFMADDSUB132PSZ128mb + 2492708U, // VFMADDSUB132PSZ128mbk + 2492708U, // VFMADDSUB132PSZ128mbkz + 35108U, // VFMADDSUB132PSZ128mk + 35108U, // VFMADDSUB132PSZ128mkz + 288U, // VFMADDSUB132PSZ128r + 166180U, // VFMADDSUB132PSZ128rk + 166180U, // VFMADDSUB132PSZ128rkz + 608U, // VFMADDSUB132PSZ256m + 8928U, // VFMADDSUB132PSZ256mb + 3541284U, // VFMADDSUB132PSZ256mbk + 3541284U, // VFMADDSUB132PSZ256mbkz + 231716U, // VFMADDSUB132PSZ256mk + 231716U, // VFMADDSUB132PSZ256mkz + 288U, // VFMADDSUB132PSZ256r + 166180U, // VFMADDSUB132PSZ256rk + 166180U, // VFMADDSUB132PSZ256rkz + 1056U, // VFMADDSUB132PSZm + 10976U, // VFMADDSUB132PSZmb + 5638436U, // VFMADDSUB132PSZmbk + 5638436U, // VFMADDSUB132PSZmbkz + 297252U, // VFMADDSUB132PSZmk + 297252U, // VFMADDSUB132PSZmkz + 288U, // VFMADDSUB132PSZr + 887072U, // VFMADDSUB132PSZrb + 4360484U, // VFMADDSUB132PSZrbk + 4360484U, // VFMADDSUB132PSZrbkz + 166180U, // VFMADDSUB132PSZrk + 166180U, // VFMADDSUB132PSZrkz + 256U, // VFMADDSUB132PSm + 288U, // VFMADDSUB132PSr + 608U, // VFMADDSUB213PDYm + 288U, // VFMADDSUB213PDYr + 256U, // VFMADDSUB213PDZ128m + 4672U, // VFMADDSUB213PDZ128mb + 1116452U, // VFMADDSUB213PDZ128mbk + 1116452U, // VFMADDSUB213PDZ128mbkz + 35108U, // VFMADDSUB213PDZ128mk + 35108U, // VFMADDSUB213PDZ128mkz + 288U, // VFMADDSUB213PDZ128r + 166180U, // VFMADDSUB213PDZ128rk + 166180U, // VFMADDSUB213PDZ128rkz + 608U, // VFMADDSUB213PDZ256m + 6720U, // VFMADDSUB213PDZ256mb + 2165028U, // VFMADDSUB213PDZ256mbk + 2165028U, // VFMADDSUB213PDZ256mbkz + 231716U, // VFMADDSUB213PDZ256mk + 231716U, // VFMADDSUB213PDZ256mkz + 288U, // VFMADDSUB213PDZ256r + 166180U, // VFMADDSUB213PDZ256rk + 166180U, // VFMADDSUB213PDZ256rkz + 1056U, // VFMADDSUB213PDZm + 8768U, // VFMADDSUB213PDZmb + 3213604U, // VFMADDSUB213PDZmbk + 3213604U, // VFMADDSUB213PDZmbkz + 297252U, // VFMADDSUB213PDZmk + 297252U, // VFMADDSUB213PDZmkz + 288U, // VFMADDSUB213PDZr + 887072U, // VFMADDSUB213PDZrb + 4360484U, // VFMADDSUB213PDZrbk + 4360484U, // VFMADDSUB213PDZrbkz + 166180U, // VFMADDSUB213PDZrk + 166180U, // VFMADDSUB213PDZrkz + 256U, // VFMADDSUB213PDm + 288U, // VFMADDSUB213PDr + 608U, // VFMADDSUB213PSYm + 288U, // VFMADDSUB213PSYr + 256U, // VFMADDSUB213PSZ128m + 6880U, // VFMADDSUB213PSZ128mb + 2492708U, // VFMADDSUB213PSZ128mbk + 2492708U, // VFMADDSUB213PSZ128mbkz + 35108U, // VFMADDSUB213PSZ128mk + 35108U, // VFMADDSUB213PSZ128mkz + 288U, // VFMADDSUB213PSZ128r + 166180U, // VFMADDSUB213PSZ128rk + 166180U, // VFMADDSUB213PSZ128rkz + 608U, // VFMADDSUB213PSZ256m + 8928U, // VFMADDSUB213PSZ256mb + 3541284U, // VFMADDSUB213PSZ256mbk + 3541284U, // VFMADDSUB213PSZ256mbkz + 231716U, // VFMADDSUB213PSZ256mk + 231716U, // VFMADDSUB213PSZ256mkz + 288U, // VFMADDSUB213PSZ256r + 166180U, // VFMADDSUB213PSZ256rk + 166180U, // VFMADDSUB213PSZ256rkz + 1056U, // VFMADDSUB213PSZm + 10976U, // VFMADDSUB213PSZmb + 5638436U, // VFMADDSUB213PSZmbk + 5638436U, // VFMADDSUB213PSZmbkz + 297252U, // VFMADDSUB213PSZmk + 297252U, // VFMADDSUB213PSZmkz + 288U, // VFMADDSUB213PSZr + 887072U, // VFMADDSUB213PSZrb + 4360484U, // VFMADDSUB213PSZrbk + 4360484U, // VFMADDSUB213PSZrbkz + 166180U, // VFMADDSUB213PSZrk + 166180U, // VFMADDSUB213PSZrkz + 256U, // VFMADDSUB213PSm + 288U, // VFMADDSUB213PSr + 608U, // VFMADDSUB231PDYm + 288U, // VFMADDSUB231PDYr + 256U, // VFMADDSUB231PDZ128m + 4672U, // VFMADDSUB231PDZ128mb + 1116452U, // VFMADDSUB231PDZ128mbk + 1116452U, // VFMADDSUB231PDZ128mbkz + 35108U, // VFMADDSUB231PDZ128mk + 35108U, // VFMADDSUB231PDZ128mkz + 288U, // VFMADDSUB231PDZ128r + 166180U, // VFMADDSUB231PDZ128rk + 166180U, // VFMADDSUB231PDZ128rkz + 608U, // VFMADDSUB231PDZ256m + 6720U, // VFMADDSUB231PDZ256mb + 2165028U, // VFMADDSUB231PDZ256mbk + 2165028U, // VFMADDSUB231PDZ256mbkz + 231716U, // VFMADDSUB231PDZ256mk + 231716U, // VFMADDSUB231PDZ256mkz + 288U, // VFMADDSUB231PDZ256r + 166180U, // VFMADDSUB231PDZ256rk + 166180U, // VFMADDSUB231PDZ256rkz + 1056U, // VFMADDSUB231PDZm + 8768U, // VFMADDSUB231PDZmb + 3213604U, // VFMADDSUB231PDZmbk + 3213604U, // VFMADDSUB231PDZmbkz + 297252U, // VFMADDSUB231PDZmk + 297252U, // VFMADDSUB231PDZmkz + 288U, // VFMADDSUB231PDZr + 887072U, // VFMADDSUB231PDZrb + 4360484U, // VFMADDSUB231PDZrbk + 4360484U, // VFMADDSUB231PDZrbkz + 166180U, // VFMADDSUB231PDZrk + 166180U, // VFMADDSUB231PDZrkz + 256U, // VFMADDSUB231PDm + 288U, // VFMADDSUB231PDr + 608U, // VFMADDSUB231PSYm + 288U, // VFMADDSUB231PSYr + 256U, // VFMADDSUB231PSZ128m + 6880U, // VFMADDSUB231PSZ128mb + 2492708U, // VFMADDSUB231PSZ128mbk + 2492708U, // VFMADDSUB231PSZ128mbkz + 35108U, // VFMADDSUB231PSZ128mk + 35108U, // VFMADDSUB231PSZ128mkz + 288U, // VFMADDSUB231PSZ128r + 166180U, // VFMADDSUB231PSZ128rk + 166180U, // VFMADDSUB231PSZ128rkz + 608U, // VFMADDSUB231PSZ256m + 8928U, // VFMADDSUB231PSZ256mb + 3541284U, // VFMADDSUB231PSZ256mbk + 3541284U, // VFMADDSUB231PSZ256mbkz + 231716U, // VFMADDSUB231PSZ256mk + 231716U, // VFMADDSUB231PSZ256mkz + 288U, // VFMADDSUB231PSZ256r + 166180U, // VFMADDSUB231PSZ256rk + 166180U, // VFMADDSUB231PSZ256rkz + 1056U, // VFMADDSUB231PSZm + 10976U, // VFMADDSUB231PSZmb + 5638436U, // VFMADDSUB231PSZmbk + 5638436U, // VFMADDSUB231PSZmbkz + 297252U, // VFMADDSUB231PSZmk + 297252U, // VFMADDSUB231PSZmkz + 288U, // VFMADDSUB231PSZr + 887072U, // VFMADDSUB231PSZrb + 4360484U, // VFMADDSUB231PSZrbk + 4360484U, // VFMADDSUB231PSZrbkz + 166180U, // VFMADDSUB231PSZrk + 166180U, // VFMADDSUB231PSZrkz + 256U, // VFMADDSUB231PSm + 288U, // VFMADDSUB231PSr + 854336U, // VFMADDSUBPD4Ymr + 264288U, // VFMADDSUBPD4Yrm + 198752U, // VFMADDSUBPD4Yrr + 198752U, // VFMADDSUBPD4Yrr_REV + 854368U, // VFMADDSUBPD4mr + 133216U, // VFMADDSUBPD4rm + 198752U, // VFMADDSUBPD4rr + 198752U, // VFMADDSUBPD4rr_REV + 854336U, // VFMADDSUBPS4Ymr + 264288U, // VFMADDSUBPS4Yrm + 198752U, // VFMADDSUBPS4Yrr + 198752U, // VFMADDSUBPS4Yrr_REV + 854368U, // VFMADDSUBPS4mr + 133216U, // VFMADDSUBPS4rm + 198752U, // VFMADDSUBPS4rr + 198752U, // VFMADDSUBPS4rr_REV + 608U, // VFMSUB132PDYm + 288U, // VFMSUB132PDYr + 256U, // VFMSUB132PDZ128m + 4672U, // VFMSUB132PDZ128mb + 1116452U, // VFMSUB132PDZ128mbk + 1116452U, // VFMSUB132PDZ128mbkz + 35108U, // VFMSUB132PDZ128mk + 35108U, // VFMSUB132PDZ128mkz + 288U, // VFMSUB132PDZ128r + 166180U, // VFMSUB132PDZ128rk + 166180U, // VFMSUB132PDZ128rkz + 608U, // VFMSUB132PDZ256m + 6720U, // VFMSUB132PDZ256mb + 2165028U, // VFMSUB132PDZ256mbk + 2165028U, // VFMSUB132PDZ256mbkz + 231716U, // VFMSUB132PDZ256mk + 231716U, // VFMSUB132PDZ256mkz + 288U, // VFMSUB132PDZ256r + 166180U, // VFMSUB132PDZ256rk + 166180U, // VFMSUB132PDZ256rkz + 1056U, // VFMSUB132PDZm + 8768U, // VFMSUB132PDZmb + 3213604U, // VFMSUB132PDZmbk + 3213604U, // VFMSUB132PDZmbkz + 297252U, // VFMSUB132PDZmk + 297252U, // VFMSUB132PDZmkz + 288U, // VFMSUB132PDZr + 887072U, // VFMSUB132PDZrb + 4360484U, // VFMSUB132PDZrbk + 4360484U, // VFMSUB132PDZrbkz + 166180U, // VFMSUB132PDZrk + 166180U, // VFMSUB132PDZrkz + 256U, // VFMSUB132PDm + 288U, // VFMSUB132PDr + 608U, // VFMSUB132PSYm + 288U, // VFMSUB132PSYr + 256U, // VFMSUB132PSZ128m + 6880U, // VFMSUB132PSZ128mb + 2492708U, // VFMSUB132PSZ128mbk + 2492708U, // VFMSUB132PSZ128mbkz + 35108U, // VFMSUB132PSZ128mk + 35108U, // VFMSUB132PSZ128mkz + 288U, // VFMSUB132PSZ128r + 166180U, // VFMSUB132PSZ128rk + 166180U, // VFMSUB132PSZ128rkz + 608U, // VFMSUB132PSZ256m + 8928U, // VFMSUB132PSZ256mb + 3541284U, // VFMSUB132PSZ256mbk + 3541284U, // VFMSUB132PSZ256mbkz + 231716U, // VFMSUB132PSZ256mk + 231716U, // VFMSUB132PSZ256mkz + 288U, // VFMSUB132PSZ256r + 166180U, // VFMSUB132PSZ256rk + 166180U, // VFMSUB132PSZ256rkz + 1056U, // VFMSUB132PSZm + 10976U, // VFMSUB132PSZmb + 5638436U, // VFMSUB132PSZmbk + 5638436U, // VFMSUB132PSZmbkz + 297252U, // VFMSUB132PSZmk + 297252U, // VFMSUB132PSZmkz + 288U, // VFMSUB132PSZr + 887072U, // VFMSUB132PSZrb + 4360484U, // VFMSUB132PSZrbk + 4360484U, // VFMSUB132PSZrbkz + 166180U, // VFMSUB132PSZrk + 166180U, // VFMSUB132PSZrkz + 256U, // VFMSUB132PSm + 288U, // VFMSUB132PSr + 576U, // VFMSUB132SDZm + 576U, // VFMSUB132SDZm_Int + 67876U, // VFMSUB132SDZm_Intk + 67876U, // VFMSUB132SDZm_Intkz + 288U, // VFMSUB132SDZr + 288U, // VFMSUB132SDZr_Int + 166180U, // VFMSUB132SDZr_Intk + 166180U, // VFMSUB132SDZr_Intkz + 288U, // VFMSUB132SDZrb + 887072U, // VFMSUB132SDZrb_Int + 4360484U, // VFMSUB132SDZrb_Intk + 4360484U, // VFMSUB132SDZrb_Intkz + 576U, // VFMSUB132SDm + 576U, // VFMSUB132SDm_Int + 288U, // VFMSUB132SDr + 288U, // VFMSUB132SDr_Int + 736U, // VFMSUB132SSZm + 736U, // VFMSUB132SSZm_Int + 395556U, // VFMSUB132SSZm_Intk + 395556U, // VFMSUB132SSZm_Intkz + 288U, // VFMSUB132SSZr + 288U, // VFMSUB132SSZr_Int + 166180U, // VFMSUB132SSZr_Intk + 166180U, // VFMSUB132SSZr_Intkz + 288U, // VFMSUB132SSZrb + 887072U, // VFMSUB132SSZrb_Int + 4360484U, // VFMSUB132SSZrb_Intk + 4360484U, // VFMSUB132SSZrb_Intkz + 736U, // VFMSUB132SSm + 736U, // VFMSUB132SSm_Int + 288U, // VFMSUB132SSr + 288U, // VFMSUB132SSr_Int + 608U, // VFMSUB213PDYm + 288U, // VFMSUB213PDYr + 256U, // VFMSUB213PDZ128m + 4672U, // VFMSUB213PDZ128mb + 1116452U, // VFMSUB213PDZ128mbk + 1116452U, // VFMSUB213PDZ128mbkz + 35108U, // VFMSUB213PDZ128mk + 35108U, // VFMSUB213PDZ128mkz + 288U, // VFMSUB213PDZ128r + 166180U, // VFMSUB213PDZ128rk + 166180U, // VFMSUB213PDZ128rkz + 608U, // VFMSUB213PDZ256m + 6720U, // VFMSUB213PDZ256mb + 2165028U, // VFMSUB213PDZ256mbk + 2165028U, // VFMSUB213PDZ256mbkz + 231716U, // VFMSUB213PDZ256mk + 231716U, // VFMSUB213PDZ256mkz + 288U, // VFMSUB213PDZ256r + 166180U, // VFMSUB213PDZ256rk + 166180U, // VFMSUB213PDZ256rkz + 1056U, // VFMSUB213PDZm + 8768U, // VFMSUB213PDZmb + 3213604U, // VFMSUB213PDZmbk + 3213604U, // VFMSUB213PDZmbkz + 297252U, // VFMSUB213PDZmk + 297252U, // VFMSUB213PDZmkz + 288U, // VFMSUB213PDZr + 887072U, // VFMSUB213PDZrb + 4360484U, // VFMSUB213PDZrbk + 4360484U, // VFMSUB213PDZrbkz + 166180U, // VFMSUB213PDZrk + 166180U, // VFMSUB213PDZrkz + 256U, // VFMSUB213PDm + 288U, // VFMSUB213PDr + 608U, // VFMSUB213PSYm + 288U, // VFMSUB213PSYr + 256U, // VFMSUB213PSZ128m + 6880U, // VFMSUB213PSZ128mb + 2492708U, // VFMSUB213PSZ128mbk + 2492708U, // VFMSUB213PSZ128mbkz + 35108U, // VFMSUB213PSZ128mk + 35108U, // VFMSUB213PSZ128mkz + 288U, // VFMSUB213PSZ128r + 166180U, // VFMSUB213PSZ128rk + 166180U, // VFMSUB213PSZ128rkz + 608U, // VFMSUB213PSZ256m + 8928U, // VFMSUB213PSZ256mb + 3541284U, // VFMSUB213PSZ256mbk + 3541284U, // VFMSUB213PSZ256mbkz + 231716U, // VFMSUB213PSZ256mk + 231716U, // VFMSUB213PSZ256mkz + 288U, // VFMSUB213PSZ256r + 166180U, // VFMSUB213PSZ256rk + 166180U, // VFMSUB213PSZ256rkz + 1056U, // VFMSUB213PSZm + 10976U, // VFMSUB213PSZmb + 5638436U, // VFMSUB213PSZmbk + 5638436U, // VFMSUB213PSZmbkz + 297252U, // VFMSUB213PSZmk + 297252U, // VFMSUB213PSZmkz + 288U, // VFMSUB213PSZr + 887072U, // VFMSUB213PSZrb + 4360484U, // VFMSUB213PSZrbk + 4360484U, // VFMSUB213PSZrbkz + 166180U, // VFMSUB213PSZrk + 166180U, // VFMSUB213PSZrkz + 256U, // VFMSUB213PSm + 288U, // VFMSUB213PSr + 576U, // VFMSUB213SDZm + 576U, // VFMSUB213SDZm_Int + 67876U, // VFMSUB213SDZm_Intk + 67876U, // VFMSUB213SDZm_Intkz + 288U, // VFMSUB213SDZr + 288U, // VFMSUB213SDZr_Int + 166180U, // VFMSUB213SDZr_Intk + 166180U, // VFMSUB213SDZr_Intkz + 288U, // VFMSUB213SDZrb + 887072U, // VFMSUB213SDZrb_Int + 4360484U, // VFMSUB213SDZrb_Intk + 4360484U, // VFMSUB213SDZrb_Intkz + 576U, // VFMSUB213SDm + 576U, // VFMSUB213SDm_Int + 288U, // VFMSUB213SDr + 288U, // VFMSUB213SDr_Int + 736U, // VFMSUB213SSZm + 736U, // VFMSUB213SSZm_Int + 395556U, // VFMSUB213SSZm_Intk + 395556U, // VFMSUB213SSZm_Intkz + 288U, // VFMSUB213SSZr + 288U, // VFMSUB213SSZr_Int + 166180U, // VFMSUB213SSZr_Intk + 166180U, // VFMSUB213SSZr_Intkz + 288U, // VFMSUB213SSZrb + 887072U, // VFMSUB213SSZrb_Int + 4360484U, // VFMSUB213SSZrb_Intk + 4360484U, // VFMSUB213SSZrb_Intkz + 736U, // VFMSUB213SSm + 736U, // VFMSUB213SSm_Int + 288U, // VFMSUB213SSr + 288U, // VFMSUB213SSr_Int + 608U, // VFMSUB231PDYm + 288U, // VFMSUB231PDYr + 256U, // VFMSUB231PDZ128m + 4672U, // VFMSUB231PDZ128mb + 1116452U, // VFMSUB231PDZ128mbk + 1116452U, // VFMSUB231PDZ128mbkz + 35108U, // VFMSUB231PDZ128mk + 35108U, // VFMSUB231PDZ128mkz + 288U, // VFMSUB231PDZ128r + 166180U, // VFMSUB231PDZ128rk + 166180U, // VFMSUB231PDZ128rkz + 608U, // VFMSUB231PDZ256m + 6720U, // VFMSUB231PDZ256mb + 2165028U, // VFMSUB231PDZ256mbk + 2165028U, // VFMSUB231PDZ256mbkz + 231716U, // VFMSUB231PDZ256mk + 231716U, // VFMSUB231PDZ256mkz + 288U, // VFMSUB231PDZ256r + 166180U, // VFMSUB231PDZ256rk + 166180U, // VFMSUB231PDZ256rkz + 1056U, // VFMSUB231PDZm + 8768U, // VFMSUB231PDZmb + 3213604U, // VFMSUB231PDZmbk + 3213604U, // VFMSUB231PDZmbkz + 297252U, // VFMSUB231PDZmk + 297252U, // VFMSUB231PDZmkz + 288U, // VFMSUB231PDZr + 887072U, // VFMSUB231PDZrb + 4360484U, // VFMSUB231PDZrbk + 4360484U, // VFMSUB231PDZrbkz + 166180U, // VFMSUB231PDZrk + 166180U, // VFMSUB231PDZrkz + 256U, // VFMSUB231PDm + 288U, // VFMSUB231PDr + 608U, // VFMSUB231PSYm + 288U, // VFMSUB231PSYr + 256U, // VFMSUB231PSZ128m + 6880U, // VFMSUB231PSZ128mb + 2492708U, // VFMSUB231PSZ128mbk + 2492708U, // VFMSUB231PSZ128mbkz + 35108U, // VFMSUB231PSZ128mk + 35108U, // VFMSUB231PSZ128mkz + 288U, // VFMSUB231PSZ128r + 166180U, // VFMSUB231PSZ128rk + 166180U, // VFMSUB231PSZ128rkz + 608U, // VFMSUB231PSZ256m + 8928U, // VFMSUB231PSZ256mb + 3541284U, // VFMSUB231PSZ256mbk + 3541284U, // VFMSUB231PSZ256mbkz + 231716U, // VFMSUB231PSZ256mk + 231716U, // VFMSUB231PSZ256mkz + 288U, // VFMSUB231PSZ256r + 166180U, // VFMSUB231PSZ256rk + 166180U, // VFMSUB231PSZ256rkz + 1056U, // VFMSUB231PSZm + 10976U, // VFMSUB231PSZmb + 5638436U, // VFMSUB231PSZmbk + 5638436U, // VFMSUB231PSZmbkz + 297252U, // VFMSUB231PSZmk + 297252U, // VFMSUB231PSZmkz + 288U, // VFMSUB231PSZr + 887072U, // VFMSUB231PSZrb + 4360484U, // VFMSUB231PSZrbk + 4360484U, // VFMSUB231PSZrbkz + 166180U, // VFMSUB231PSZrk + 166180U, // VFMSUB231PSZrkz + 256U, // VFMSUB231PSm + 288U, // VFMSUB231PSr + 576U, // VFMSUB231SDZm + 576U, // VFMSUB231SDZm_Int + 67876U, // VFMSUB231SDZm_Intk + 67876U, // VFMSUB231SDZm_Intkz + 288U, // VFMSUB231SDZr + 288U, // VFMSUB231SDZr_Int + 166180U, // VFMSUB231SDZr_Intk + 166180U, // VFMSUB231SDZr_Intkz + 288U, // VFMSUB231SDZrb + 887072U, // VFMSUB231SDZrb_Int + 4360484U, // VFMSUB231SDZrb_Intk + 4360484U, // VFMSUB231SDZrb_Intkz + 576U, // VFMSUB231SDm + 576U, // VFMSUB231SDm_Int + 288U, // VFMSUB231SDr + 288U, // VFMSUB231SDr_Int + 736U, // VFMSUB231SSZm + 736U, // VFMSUB231SSZm_Int + 395556U, // VFMSUB231SSZm_Intk + 395556U, // VFMSUB231SSZm_Intkz + 288U, // VFMSUB231SSZr + 288U, // VFMSUB231SSZr_Int + 166180U, // VFMSUB231SSZr_Intk + 166180U, // VFMSUB231SSZr_Intkz + 288U, // VFMSUB231SSZrb + 887072U, // VFMSUB231SSZrb_Int + 4360484U, // VFMSUB231SSZrb_Intk + 4360484U, // VFMSUB231SSZrb_Intkz + 736U, // VFMSUB231SSm + 736U, // VFMSUB231SSm_Int + 288U, // VFMSUB231SSr + 288U, // VFMSUB231SSr_Int + 608U, // VFMSUBADD132PDYm + 288U, // VFMSUBADD132PDYr + 256U, // VFMSUBADD132PDZ128m + 4672U, // VFMSUBADD132PDZ128mb + 1116452U, // VFMSUBADD132PDZ128mbk + 1116452U, // VFMSUBADD132PDZ128mbkz + 35108U, // VFMSUBADD132PDZ128mk + 35108U, // VFMSUBADD132PDZ128mkz + 288U, // VFMSUBADD132PDZ128r + 166180U, // VFMSUBADD132PDZ128rk + 166180U, // VFMSUBADD132PDZ128rkz + 608U, // VFMSUBADD132PDZ256m + 6720U, // VFMSUBADD132PDZ256mb + 2165028U, // VFMSUBADD132PDZ256mbk + 2165028U, // VFMSUBADD132PDZ256mbkz + 231716U, // VFMSUBADD132PDZ256mk + 231716U, // VFMSUBADD132PDZ256mkz + 288U, // VFMSUBADD132PDZ256r + 166180U, // VFMSUBADD132PDZ256rk + 166180U, // VFMSUBADD132PDZ256rkz + 1056U, // VFMSUBADD132PDZm + 8768U, // VFMSUBADD132PDZmb + 3213604U, // VFMSUBADD132PDZmbk + 3213604U, // VFMSUBADD132PDZmbkz + 297252U, // VFMSUBADD132PDZmk + 297252U, // VFMSUBADD132PDZmkz + 288U, // VFMSUBADD132PDZr + 887072U, // VFMSUBADD132PDZrb + 4360484U, // VFMSUBADD132PDZrbk + 4360484U, // VFMSUBADD132PDZrbkz + 166180U, // VFMSUBADD132PDZrk + 166180U, // VFMSUBADD132PDZrkz + 256U, // VFMSUBADD132PDm + 288U, // VFMSUBADD132PDr + 608U, // VFMSUBADD132PSYm + 288U, // VFMSUBADD132PSYr + 256U, // VFMSUBADD132PSZ128m + 6880U, // VFMSUBADD132PSZ128mb + 2492708U, // VFMSUBADD132PSZ128mbk + 2492708U, // VFMSUBADD132PSZ128mbkz + 35108U, // VFMSUBADD132PSZ128mk + 35108U, // VFMSUBADD132PSZ128mkz + 288U, // VFMSUBADD132PSZ128r + 166180U, // VFMSUBADD132PSZ128rk + 166180U, // VFMSUBADD132PSZ128rkz + 608U, // VFMSUBADD132PSZ256m + 8928U, // VFMSUBADD132PSZ256mb + 3541284U, // VFMSUBADD132PSZ256mbk + 3541284U, // VFMSUBADD132PSZ256mbkz + 231716U, // VFMSUBADD132PSZ256mk + 231716U, // VFMSUBADD132PSZ256mkz + 288U, // VFMSUBADD132PSZ256r + 166180U, // VFMSUBADD132PSZ256rk + 166180U, // VFMSUBADD132PSZ256rkz + 1056U, // VFMSUBADD132PSZm + 10976U, // VFMSUBADD132PSZmb + 5638436U, // VFMSUBADD132PSZmbk + 5638436U, // VFMSUBADD132PSZmbkz + 297252U, // VFMSUBADD132PSZmk + 297252U, // VFMSUBADD132PSZmkz + 288U, // VFMSUBADD132PSZr + 887072U, // VFMSUBADD132PSZrb + 4360484U, // VFMSUBADD132PSZrbk + 4360484U, // VFMSUBADD132PSZrbkz + 166180U, // VFMSUBADD132PSZrk + 166180U, // VFMSUBADD132PSZrkz + 256U, // VFMSUBADD132PSm + 288U, // VFMSUBADD132PSr + 608U, // VFMSUBADD213PDYm + 288U, // VFMSUBADD213PDYr + 256U, // VFMSUBADD213PDZ128m + 4672U, // VFMSUBADD213PDZ128mb + 1116452U, // VFMSUBADD213PDZ128mbk + 1116452U, // VFMSUBADD213PDZ128mbkz + 35108U, // VFMSUBADD213PDZ128mk + 35108U, // VFMSUBADD213PDZ128mkz + 288U, // VFMSUBADD213PDZ128r + 166180U, // VFMSUBADD213PDZ128rk + 166180U, // VFMSUBADD213PDZ128rkz + 608U, // VFMSUBADD213PDZ256m + 6720U, // VFMSUBADD213PDZ256mb + 2165028U, // VFMSUBADD213PDZ256mbk + 2165028U, // VFMSUBADD213PDZ256mbkz + 231716U, // VFMSUBADD213PDZ256mk + 231716U, // VFMSUBADD213PDZ256mkz + 288U, // VFMSUBADD213PDZ256r + 166180U, // VFMSUBADD213PDZ256rk + 166180U, // VFMSUBADD213PDZ256rkz + 1056U, // VFMSUBADD213PDZm + 8768U, // VFMSUBADD213PDZmb + 3213604U, // VFMSUBADD213PDZmbk + 3213604U, // VFMSUBADD213PDZmbkz + 297252U, // VFMSUBADD213PDZmk + 297252U, // VFMSUBADD213PDZmkz + 288U, // VFMSUBADD213PDZr + 887072U, // VFMSUBADD213PDZrb + 4360484U, // VFMSUBADD213PDZrbk + 4360484U, // VFMSUBADD213PDZrbkz + 166180U, // VFMSUBADD213PDZrk + 166180U, // VFMSUBADD213PDZrkz + 256U, // VFMSUBADD213PDm + 288U, // VFMSUBADD213PDr + 608U, // VFMSUBADD213PSYm + 288U, // VFMSUBADD213PSYr + 256U, // VFMSUBADD213PSZ128m + 6880U, // VFMSUBADD213PSZ128mb + 2492708U, // VFMSUBADD213PSZ128mbk + 2492708U, // VFMSUBADD213PSZ128mbkz + 35108U, // VFMSUBADD213PSZ128mk + 35108U, // VFMSUBADD213PSZ128mkz + 288U, // VFMSUBADD213PSZ128r + 166180U, // VFMSUBADD213PSZ128rk + 166180U, // VFMSUBADD213PSZ128rkz + 608U, // VFMSUBADD213PSZ256m + 8928U, // VFMSUBADD213PSZ256mb + 3541284U, // VFMSUBADD213PSZ256mbk + 3541284U, // VFMSUBADD213PSZ256mbkz + 231716U, // VFMSUBADD213PSZ256mk + 231716U, // VFMSUBADD213PSZ256mkz + 288U, // VFMSUBADD213PSZ256r + 166180U, // VFMSUBADD213PSZ256rk + 166180U, // VFMSUBADD213PSZ256rkz + 1056U, // VFMSUBADD213PSZm + 10976U, // VFMSUBADD213PSZmb + 5638436U, // VFMSUBADD213PSZmbk + 5638436U, // VFMSUBADD213PSZmbkz + 297252U, // VFMSUBADD213PSZmk + 297252U, // VFMSUBADD213PSZmkz + 288U, // VFMSUBADD213PSZr + 887072U, // VFMSUBADD213PSZrb + 4360484U, // VFMSUBADD213PSZrbk + 4360484U, // VFMSUBADD213PSZrbkz + 166180U, // VFMSUBADD213PSZrk + 166180U, // VFMSUBADD213PSZrkz + 256U, // VFMSUBADD213PSm + 288U, // VFMSUBADD213PSr + 608U, // VFMSUBADD231PDYm + 288U, // VFMSUBADD231PDYr + 256U, // VFMSUBADD231PDZ128m + 4672U, // VFMSUBADD231PDZ128mb + 1116452U, // VFMSUBADD231PDZ128mbk + 1116452U, // VFMSUBADD231PDZ128mbkz + 35108U, // VFMSUBADD231PDZ128mk + 35108U, // VFMSUBADD231PDZ128mkz + 288U, // VFMSUBADD231PDZ128r + 166180U, // VFMSUBADD231PDZ128rk + 166180U, // VFMSUBADD231PDZ128rkz + 608U, // VFMSUBADD231PDZ256m + 6720U, // VFMSUBADD231PDZ256mb + 2165028U, // VFMSUBADD231PDZ256mbk + 2165028U, // VFMSUBADD231PDZ256mbkz + 231716U, // VFMSUBADD231PDZ256mk + 231716U, // VFMSUBADD231PDZ256mkz + 288U, // VFMSUBADD231PDZ256r + 166180U, // VFMSUBADD231PDZ256rk + 166180U, // VFMSUBADD231PDZ256rkz + 1056U, // VFMSUBADD231PDZm + 8768U, // VFMSUBADD231PDZmb + 3213604U, // VFMSUBADD231PDZmbk + 3213604U, // VFMSUBADD231PDZmbkz + 297252U, // VFMSUBADD231PDZmk + 297252U, // VFMSUBADD231PDZmkz + 288U, // VFMSUBADD231PDZr + 887072U, // VFMSUBADD231PDZrb + 4360484U, // VFMSUBADD231PDZrbk + 4360484U, // VFMSUBADD231PDZrbkz + 166180U, // VFMSUBADD231PDZrk + 166180U, // VFMSUBADD231PDZrkz + 256U, // VFMSUBADD231PDm + 288U, // VFMSUBADD231PDr + 608U, // VFMSUBADD231PSYm + 288U, // VFMSUBADD231PSYr + 256U, // VFMSUBADD231PSZ128m + 6880U, // VFMSUBADD231PSZ128mb + 2492708U, // VFMSUBADD231PSZ128mbk + 2492708U, // VFMSUBADD231PSZ128mbkz + 35108U, // VFMSUBADD231PSZ128mk + 35108U, // VFMSUBADD231PSZ128mkz + 288U, // VFMSUBADD231PSZ128r + 166180U, // VFMSUBADD231PSZ128rk + 166180U, // VFMSUBADD231PSZ128rkz + 608U, // VFMSUBADD231PSZ256m + 8928U, // VFMSUBADD231PSZ256mb + 3541284U, // VFMSUBADD231PSZ256mbk + 3541284U, // VFMSUBADD231PSZ256mbkz + 231716U, // VFMSUBADD231PSZ256mk + 231716U, // VFMSUBADD231PSZ256mkz + 288U, // VFMSUBADD231PSZ256r + 166180U, // VFMSUBADD231PSZ256rk + 166180U, // VFMSUBADD231PSZ256rkz + 1056U, // VFMSUBADD231PSZm + 10976U, // VFMSUBADD231PSZmb + 5638436U, // VFMSUBADD231PSZmbk + 5638436U, // VFMSUBADD231PSZmbkz + 297252U, // VFMSUBADD231PSZmk + 297252U, // VFMSUBADD231PSZmkz + 288U, // VFMSUBADD231PSZr + 887072U, // VFMSUBADD231PSZrb + 4360484U, // VFMSUBADD231PSZrbk + 4360484U, // VFMSUBADD231PSZrbkz + 166180U, // VFMSUBADD231PSZrk + 166180U, // VFMSUBADD231PSZrkz + 256U, // VFMSUBADD231PSm + 288U, // VFMSUBADD231PSr + 854336U, // VFMSUBADDPD4Ymr + 264288U, // VFMSUBADDPD4Yrm + 198752U, // VFMSUBADDPD4Yrr + 198752U, // VFMSUBADDPD4Yrr_REV + 854368U, // VFMSUBADDPD4mr + 133216U, // VFMSUBADDPD4rm + 198752U, // VFMSUBADDPD4rr + 198752U, // VFMSUBADDPD4rr_REV + 854336U, // VFMSUBADDPS4Ymr + 264288U, // VFMSUBADDPS4Yrm + 198752U, // VFMSUBADDPS4Yrr + 198752U, // VFMSUBADDPS4Yrr_REV + 854368U, // VFMSUBADDPS4mr + 133216U, // VFMSUBADDPS4rm + 198752U, // VFMSUBADDPS4rr + 198752U, // VFMSUBADDPS4rr_REV + 854336U, // VFMSUBPD4Ymr + 264288U, // VFMSUBPD4Yrm + 198752U, // VFMSUBPD4Yrr + 198752U, // VFMSUBPD4Yrr_REV + 854368U, // VFMSUBPD4mr + 133216U, // VFMSUBPD4rm + 198752U, // VFMSUBPD4rr + 198752U, // VFMSUBPD4rr_REV + 854336U, // VFMSUBPS4Ymr + 264288U, // VFMSUBPS4Yrm + 198752U, // VFMSUBPS4Yrr + 198752U, // VFMSUBPS4Yrr_REV + 854368U, // VFMSUBPS4mr + 133216U, // VFMSUBPS4rm + 198752U, // VFMSUBPS4rr + 198752U, // VFMSUBPS4rr_REV + 854400U, // VFMSUBSD4mr + 854400U, // VFMSUBSD4mr_Int + 100448U, // VFMSUBSD4rm + 100448U, // VFMSUBSD4rm_Int + 198752U, // VFMSUBSD4rr + 198752U, // VFMSUBSD4rr_Int + 198752U, // VFMSUBSD4rr_Int_REV + 198752U, // VFMSUBSD4rr_REV + 854464U, // VFMSUBSS4mr + 854464U, // VFMSUBSS4mr_Int + 428128U, // VFMSUBSS4rm + 428128U, // VFMSUBSS4rm_Int + 198752U, // VFMSUBSS4rr + 198752U, // VFMSUBSS4rr_Int + 198752U, // VFMSUBSS4rr_Int_REV + 198752U, // VFMSUBSS4rr_REV + 608U, // VFNMADD132PDYm + 288U, // VFNMADD132PDYr + 256U, // VFNMADD132PDZ128m + 4672U, // VFNMADD132PDZ128mb + 1116452U, // VFNMADD132PDZ128mbk + 1116452U, // VFNMADD132PDZ128mbkz + 35108U, // VFNMADD132PDZ128mk + 35108U, // VFNMADD132PDZ128mkz + 288U, // VFNMADD132PDZ128r + 166180U, // VFNMADD132PDZ128rk + 166180U, // VFNMADD132PDZ128rkz + 608U, // VFNMADD132PDZ256m + 6720U, // VFNMADD132PDZ256mb + 2165028U, // VFNMADD132PDZ256mbk + 2165028U, // VFNMADD132PDZ256mbkz + 231716U, // VFNMADD132PDZ256mk + 231716U, // VFNMADD132PDZ256mkz + 288U, // VFNMADD132PDZ256r + 166180U, // VFNMADD132PDZ256rk + 166180U, // VFNMADD132PDZ256rkz + 1056U, // VFNMADD132PDZm + 8768U, // VFNMADD132PDZmb + 3213604U, // VFNMADD132PDZmbk + 3213604U, // VFNMADD132PDZmbkz + 297252U, // VFNMADD132PDZmk + 297252U, // VFNMADD132PDZmkz + 288U, // VFNMADD132PDZr + 887072U, // VFNMADD132PDZrb + 4360484U, // VFNMADD132PDZrbk + 4360484U, // VFNMADD132PDZrbkz + 166180U, // VFNMADD132PDZrk + 166180U, // VFNMADD132PDZrkz + 256U, // VFNMADD132PDm + 288U, // VFNMADD132PDr + 608U, // VFNMADD132PSYm + 288U, // VFNMADD132PSYr + 256U, // VFNMADD132PSZ128m + 6880U, // VFNMADD132PSZ128mb + 2492708U, // VFNMADD132PSZ128mbk + 2492708U, // VFNMADD132PSZ128mbkz + 35108U, // VFNMADD132PSZ128mk + 35108U, // VFNMADD132PSZ128mkz + 288U, // VFNMADD132PSZ128r + 166180U, // VFNMADD132PSZ128rk + 166180U, // VFNMADD132PSZ128rkz + 608U, // VFNMADD132PSZ256m + 8928U, // VFNMADD132PSZ256mb + 3541284U, // VFNMADD132PSZ256mbk + 3541284U, // VFNMADD132PSZ256mbkz + 231716U, // VFNMADD132PSZ256mk + 231716U, // VFNMADD132PSZ256mkz + 288U, // VFNMADD132PSZ256r + 166180U, // VFNMADD132PSZ256rk + 166180U, // VFNMADD132PSZ256rkz + 1056U, // VFNMADD132PSZm + 10976U, // VFNMADD132PSZmb + 5638436U, // VFNMADD132PSZmbk + 5638436U, // VFNMADD132PSZmbkz + 297252U, // VFNMADD132PSZmk + 297252U, // VFNMADD132PSZmkz + 288U, // VFNMADD132PSZr + 887072U, // VFNMADD132PSZrb + 4360484U, // VFNMADD132PSZrbk + 4360484U, // VFNMADD132PSZrbkz + 166180U, // VFNMADD132PSZrk + 166180U, // VFNMADD132PSZrkz + 256U, // VFNMADD132PSm + 288U, // VFNMADD132PSr + 576U, // VFNMADD132SDZm + 576U, // VFNMADD132SDZm_Int + 67876U, // VFNMADD132SDZm_Intk + 67876U, // VFNMADD132SDZm_Intkz + 288U, // VFNMADD132SDZr + 288U, // VFNMADD132SDZr_Int + 166180U, // VFNMADD132SDZr_Intk + 166180U, // VFNMADD132SDZr_Intkz + 288U, // VFNMADD132SDZrb + 887072U, // VFNMADD132SDZrb_Int + 4360484U, // VFNMADD132SDZrb_Intk + 4360484U, // VFNMADD132SDZrb_Intkz + 576U, // VFNMADD132SDm + 576U, // VFNMADD132SDm_Int + 288U, // VFNMADD132SDr + 288U, // VFNMADD132SDr_Int + 736U, // VFNMADD132SSZm + 736U, // VFNMADD132SSZm_Int + 395556U, // VFNMADD132SSZm_Intk + 395556U, // VFNMADD132SSZm_Intkz + 288U, // VFNMADD132SSZr + 288U, // VFNMADD132SSZr_Int + 166180U, // VFNMADD132SSZr_Intk + 166180U, // VFNMADD132SSZr_Intkz + 288U, // VFNMADD132SSZrb + 887072U, // VFNMADD132SSZrb_Int + 4360484U, // VFNMADD132SSZrb_Intk + 4360484U, // VFNMADD132SSZrb_Intkz + 736U, // VFNMADD132SSm + 736U, // VFNMADD132SSm_Int + 288U, // VFNMADD132SSr + 288U, // VFNMADD132SSr_Int + 608U, // VFNMADD213PDYm + 288U, // VFNMADD213PDYr + 256U, // VFNMADD213PDZ128m + 4672U, // VFNMADD213PDZ128mb + 1116452U, // VFNMADD213PDZ128mbk + 1116452U, // VFNMADD213PDZ128mbkz + 35108U, // VFNMADD213PDZ128mk + 35108U, // VFNMADD213PDZ128mkz + 288U, // VFNMADD213PDZ128r + 166180U, // VFNMADD213PDZ128rk + 166180U, // VFNMADD213PDZ128rkz + 608U, // VFNMADD213PDZ256m + 6720U, // VFNMADD213PDZ256mb + 2165028U, // VFNMADD213PDZ256mbk + 2165028U, // VFNMADD213PDZ256mbkz + 231716U, // VFNMADD213PDZ256mk + 231716U, // VFNMADD213PDZ256mkz + 288U, // VFNMADD213PDZ256r + 166180U, // VFNMADD213PDZ256rk + 166180U, // VFNMADD213PDZ256rkz + 1056U, // VFNMADD213PDZm + 8768U, // VFNMADD213PDZmb + 3213604U, // VFNMADD213PDZmbk + 3213604U, // VFNMADD213PDZmbkz + 297252U, // VFNMADD213PDZmk + 297252U, // VFNMADD213PDZmkz + 288U, // VFNMADD213PDZr + 887072U, // VFNMADD213PDZrb + 4360484U, // VFNMADD213PDZrbk + 4360484U, // VFNMADD213PDZrbkz + 166180U, // VFNMADD213PDZrk + 166180U, // VFNMADD213PDZrkz + 256U, // VFNMADD213PDm + 288U, // VFNMADD213PDr + 608U, // VFNMADD213PSYm + 288U, // VFNMADD213PSYr + 256U, // VFNMADD213PSZ128m + 6880U, // VFNMADD213PSZ128mb + 2492708U, // VFNMADD213PSZ128mbk + 2492708U, // VFNMADD213PSZ128mbkz + 35108U, // VFNMADD213PSZ128mk + 35108U, // VFNMADD213PSZ128mkz + 288U, // VFNMADD213PSZ128r + 166180U, // VFNMADD213PSZ128rk + 166180U, // VFNMADD213PSZ128rkz + 608U, // VFNMADD213PSZ256m + 8928U, // VFNMADD213PSZ256mb + 3541284U, // VFNMADD213PSZ256mbk + 3541284U, // VFNMADD213PSZ256mbkz + 231716U, // VFNMADD213PSZ256mk + 231716U, // VFNMADD213PSZ256mkz + 288U, // VFNMADD213PSZ256r + 166180U, // VFNMADD213PSZ256rk + 166180U, // VFNMADD213PSZ256rkz + 1056U, // VFNMADD213PSZm + 10976U, // VFNMADD213PSZmb + 5638436U, // VFNMADD213PSZmbk + 5638436U, // VFNMADD213PSZmbkz + 297252U, // VFNMADD213PSZmk + 297252U, // VFNMADD213PSZmkz + 288U, // VFNMADD213PSZr + 887072U, // VFNMADD213PSZrb + 4360484U, // VFNMADD213PSZrbk + 4360484U, // VFNMADD213PSZrbkz + 166180U, // VFNMADD213PSZrk + 166180U, // VFNMADD213PSZrkz + 256U, // VFNMADD213PSm + 288U, // VFNMADD213PSr + 576U, // VFNMADD213SDZm + 576U, // VFNMADD213SDZm_Int + 67876U, // VFNMADD213SDZm_Intk + 67876U, // VFNMADD213SDZm_Intkz + 288U, // VFNMADD213SDZr + 288U, // VFNMADD213SDZr_Int + 166180U, // VFNMADD213SDZr_Intk + 166180U, // VFNMADD213SDZr_Intkz + 288U, // VFNMADD213SDZrb + 887072U, // VFNMADD213SDZrb_Int + 4360484U, // VFNMADD213SDZrb_Intk + 4360484U, // VFNMADD213SDZrb_Intkz + 576U, // VFNMADD213SDm + 576U, // VFNMADD213SDm_Int + 288U, // VFNMADD213SDr + 288U, // VFNMADD213SDr_Int + 736U, // VFNMADD213SSZm + 736U, // VFNMADD213SSZm_Int + 395556U, // VFNMADD213SSZm_Intk + 395556U, // VFNMADD213SSZm_Intkz + 288U, // VFNMADD213SSZr + 288U, // VFNMADD213SSZr_Int + 166180U, // VFNMADD213SSZr_Intk + 166180U, // VFNMADD213SSZr_Intkz + 288U, // VFNMADD213SSZrb + 887072U, // VFNMADD213SSZrb_Int + 4360484U, // VFNMADD213SSZrb_Intk + 4360484U, // VFNMADD213SSZrb_Intkz + 736U, // VFNMADD213SSm + 736U, // VFNMADD213SSm_Int + 288U, // VFNMADD213SSr + 288U, // VFNMADD213SSr_Int + 608U, // VFNMADD231PDYm + 288U, // VFNMADD231PDYr + 256U, // VFNMADD231PDZ128m + 4672U, // VFNMADD231PDZ128mb + 1116452U, // VFNMADD231PDZ128mbk + 1116452U, // VFNMADD231PDZ128mbkz + 35108U, // VFNMADD231PDZ128mk + 35108U, // VFNMADD231PDZ128mkz + 288U, // VFNMADD231PDZ128r + 166180U, // VFNMADD231PDZ128rk + 166180U, // VFNMADD231PDZ128rkz + 608U, // VFNMADD231PDZ256m + 6720U, // VFNMADD231PDZ256mb + 2165028U, // VFNMADD231PDZ256mbk + 2165028U, // VFNMADD231PDZ256mbkz + 231716U, // VFNMADD231PDZ256mk + 231716U, // VFNMADD231PDZ256mkz + 288U, // VFNMADD231PDZ256r + 166180U, // VFNMADD231PDZ256rk + 166180U, // VFNMADD231PDZ256rkz + 1056U, // VFNMADD231PDZm + 8768U, // VFNMADD231PDZmb + 3213604U, // VFNMADD231PDZmbk + 3213604U, // VFNMADD231PDZmbkz + 297252U, // VFNMADD231PDZmk + 297252U, // VFNMADD231PDZmkz + 288U, // VFNMADD231PDZr + 887072U, // VFNMADD231PDZrb + 4360484U, // VFNMADD231PDZrbk + 4360484U, // VFNMADD231PDZrbkz + 166180U, // VFNMADD231PDZrk + 166180U, // VFNMADD231PDZrkz + 256U, // VFNMADD231PDm + 288U, // VFNMADD231PDr + 608U, // VFNMADD231PSYm + 288U, // VFNMADD231PSYr + 256U, // VFNMADD231PSZ128m + 6880U, // VFNMADD231PSZ128mb + 2492708U, // VFNMADD231PSZ128mbk + 2492708U, // VFNMADD231PSZ128mbkz + 35108U, // VFNMADD231PSZ128mk + 35108U, // VFNMADD231PSZ128mkz + 288U, // VFNMADD231PSZ128r + 166180U, // VFNMADD231PSZ128rk + 166180U, // VFNMADD231PSZ128rkz + 608U, // VFNMADD231PSZ256m + 8928U, // VFNMADD231PSZ256mb + 3541284U, // VFNMADD231PSZ256mbk + 3541284U, // VFNMADD231PSZ256mbkz + 231716U, // VFNMADD231PSZ256mk + 231716U, // VFNMADD231PSZ256mkz + 288U, // VFNMADD231PSZ256r + 166180U, // VFNMADD231PSZ256rk + 166180U, // VFNMADD231PSZ256rkz + 1056U, // VFNMADD231PSZm + 10976U, // VFNMADD231PSZmb + 5638436U, // VFNMADD231PSZmbk + 5638436U, // VFNMADD231PSZmbkz + 297252U, // VFNMADD231PSZmk + 297252U, // VFNMADD231PSZmkz + 288U, // VFNMADD231PSZr + 887072U, // VFNMADD231PSZrb + 4360484U, // VFNMADD231PSZrbk + 4360484U, // VFNMADD231PSZrbkz + 166180U, // VFNMADD231PSZrk + 166180U, // VFNMADD231PSZrkz + 256U, // VFNMADD231PSm + 288U, // VFNMADD231PSr + 576U, // VFNMADD231SDZm + 576U, // VFNMADD231SDZm_Int + 67876U, // VFNMADD231SDZm_Intk + 67876U, // VFNMADD231SDZm_Intkz + 288U, // VFNMADD231SDZr + 288U, // VFNMADD231SDZr_Int + 166180U, // VFNMADD231SDZr_Intk + 166180U, // VFNMADD231SDZr_Intkz + 288U, // VFNMADD231SDZrb + 887072U, // VFNMADD231SDZrb_Int + 4360484U, // VFNMADD231SDZrb_Intk + 4360484U, // VFNMADD231SDZrb_Intkz + 576U, // VFNMADD231SDm + 576U, // VFNMADD231SDm_Int + 288U, // VFNMADD231SDr + 288U, // VFNMADD231SDr_Int + 736U, // VFNMADD231SSZm + 736U, // VFNMADD231SSZm_Int + 395556U, // VFNMADD231SSZm_Intk + 395556U, // VFNMADD231SSZm_Intkz + 288U, // VFNMADD231SSZr + 288U, // VFNMADD231SSZr_Int + 166180U, // VFNMADD231SSZr_Intk + 166180U, // VFNMADD231SSZr_Intkz + 288U, // VFNMADD231SSZrb + 887072U, // VFNMADD231SSZrb_Int + 4360484U, // VFNMADD231SSZrb_Intk + 4360484U, // VFNMADD231SSZrb_Intkz + 736U, // VFNMADD231SSm + 736U, // VFNMADD231SSm_Int + 288U, // VFNMADD231SSr + 288U, // VFNMADD231SSr_Int + 854336U, // VFNMADDPD4Ymr + 264288U, // VFNMADDPD4Yrm + 198752U, // VFNMADDPD4Yrr + 198752U, // VFNMADDPD4Yrr_REV + 854368U, // VFNMADDPD4mr + 133216U, // VFNMADDPD4rm + 198752U, // VFNMADDPD4rr + 198752U, // VFNMADDPD4rr_REV + 854336U, // VFNMADDPS4Ymr + 264288U, // VFNMADDPS4Yrm + 198752U, // VFNMADDPS4Yrr + 198752U, // VFNMADDPS4Yrr_REV + 854368U, // VFNMADDPS4mr + 133216U, // VFNMADDPS4rm + 198752U, // VFNMADDPS4rr + 198752U, // VFNMADDPS4rr_REV + 854400U, // VFNMADDSD4mr + 854400U, // VFNMADDSD4mr_Int + 100448U, // VFNMADDSD4rm + 100448U, // VFNMADDSD4rm_Int + 198752U, // VFNMADDSD4rr + 198752U, // VFNMADDSD4rr_Int + 198752U, // VFNMADDSD4rr_Int_REV + 198752U, // VFNMADDSD4rr_REV + 854464U, // VFNMADDSS4mr + 854464U, // VFNMADDSS4mr_Int + 428128U, // VFNMADDSS4rm + 428128U, // VFNMADDSS4rm_Int + 198752U, // VFNMADDSS4rr + 198752U, // VFNMADDSS4rr_Int + 198752U, // VFNMADDSS4rr_Int_REV + 198752U, // VFNMADDSS4rr_REV + 608U, // VFNMSUB132PDYm + 288U, // VFNMSUB132PDYr + 256U, // VFNMSUB132PDZ128m + 4672U, // VFNMSUB132PDZ128mb + 1116452U, // VFNMSUB132PDZ128mbk + 1116452U, // VFNMSUB132PDZ128mbkz + 35108U, // VFNMSUB132PDZ128mk + 35108U, // VFNMSUB132PDZ128mkz + 288U, // VFNMSUB132PDZ128r + 166180U, // VFNMSUB132PDZ128rk + 166180U, // VFNMSUB132PDZ128rkz + 608U, // VFNMSUB132PDZ256m + 6720U, // VFNMSUB132PDZ256mb + 2165028U, // VFNMSUB132PDZ256mbk + 2165028U, // VFNMSUB132PDZ256mbkz + 231716U, // VFNMSUB132PDZ256mk + 231716U, // VFNMSUB132PDZ256mkz + 288U, // VFNMSUB132PDZ256r + 166180U, // VFNMSUB132PDZ256rk + 166180U, // VFNMSUB132PDZ256rkz + 1056U, // VFNMSUB132PDZm + 8768U, // VFNMSUB132PDZmb + 3213604U, // VFNMSUB132PDZmbk + 3213604U, // VFNMSUB132PDZmbkz + 297252U, // VFNMSUB132PDZmk + 297252U, // VFNMSUB132PDZmkz + 288U, // VFNMSUB132PDZr + 887072U, // VFNMSUB132PDZrb + 4360484U, // VFNMSUB132PDZrbk + 4360484U, // VFNMSUB132PDZrbkz + 166180U, // VFNMSUB132PDZrk + 166180U, // VFNMSUB132PDZrkz + 256U, // VFNMSUB132PDm + 288U, // VFNMSUB132PDr + 608U, // VFNMSUB132PSYm + 288U, // VFNMSUB132PSYr + 256U, // VFNMSUB132PSZ128m + 6880U, // VFNMSUB132PSZ128mb + 2492708U, // VFNMSUB132PSZ128mbk + 2492708U, // VFNMSUB132PSZ128mbkz + 35108U, // VFNMSUB132PSZ128mk + 35108U, // VFNMSUB132PSZ128mkz + 288U, // VFNMSUB132PSZ128r + 166180U, // VFNMSUB132PSZ128rk + 166180U, // VFNMSUB132PSZ128rkz + 608U, // VFNMSUB132PSZ256m + 8928U, // VFNMSUB132PSZ256mb + 3541284U, // VFNMSUB132PSZ256mbk + 3541284U, // VFNMSUB132PSZ256mbkz + 231716U, // VFNMSUB132PSZ256mk + 231716U, // VFNMSUB132PSZ256mkz + 288U, // VFNMSUB132PSZ256r + 166180U, // VFNMSUB132PSZ256rk + 166180U, // VFNMSUB132PSZ256rkz + 1056U, // VFNMSUB132PSZm + 10976U, // VFNMSUB132PSZmb + 5638436U, // VFNMSUB132PSZmbk + 5638436U, // VFNMSUB132PSZmbkz + 297252U, // VFNMSUB132PSZmk + 297252U, // VFNMSUB132PSZmkz + 288U, // VFNMSUB132PSZr + 887072U, // VFNMSUB132PSZrb + 4360484U, // VFNMSUB132PSZrbk + 4360484U, // VFNMSUB132PSZrbkz + 166180U, // VFNMSUB132PSZrk + 166180U, // VFNMSUB132PSZrkz + 256U, // VFNMSUB132PSm + 288U, // VFNMSUB132PSr + 576U, // VFNMSUB132SDZm + 576U, // VFNMSUB132SDZm_Int + 67876U, // VFNMSUB132SDZm_Intk + 67876U, // VFNMSUB132SDZm_Intkz + 288U, // VFNMSUB132SDZr + 288U, // VFNMSUB132SDZr_Int + 166180U, // VFNMSUB132SDZr_Intk + 166180U, // VFNMSUB132SDZr_Intkz + 288U, // VFNMSUB132SDZrb + 887072U, // VFNMSUB132SDZrb_Int + 4360484U, // VFNMSUB132SDZrb_Intk + 4360484U, // VFNMSUB132SDZrb_Intkz + 576U, // VFNMSUB132SDm + 576U, // VFNMSUB132SDm_Int + 288U, // VFNMSUB132SDr + 288U, // VFNMSUB132SDr_Int + 736U, // VFNMSUB132SSZm + 736U, // VFNMSUB132SSZm_Int + 395556U, // VFNMSUB132SSZm_Intk + 395556U, // VFNMSUB132SSZm_Intkz + 288U, // VFNMSUB132SSZr + 288U, // VFNMSUB132SSZr_Int + 166180U, // VFNMSUB132SSZr_Intk + 166180U, // VFNMSUB132SSZr_Intkz + 288U, // VFNMSUB132SSZrb + 887072U, // VFNMSUB132SSZrb_Int + 4360484U, // VFNMSUB132SSZrb_Intk + 4360484U, // VFNMSUB132SSZrb_Intkz + 736U, // VFNMSUB132SSm + 736U, // VFNMSUB132SSm_Int + 288U, // VFNMSUB132SSr + 288U, // VFNMSUB132SSr_Int + 608U, // VFNMSUB213PDYm + 288U, // VFNMSUB213PDYr + 256U, // VFNMSUB213PDZ128m + 4672U, // VFNMSUB213PDZ128mb + 1116452U, // VFNMSUB213PDZ128mbk + 1116452U, // VFNMSUB213PDZ128mbkz + 35108U, // VFNMSUB213PDZ128mk + 35108U, // VFNMSUB213PDZ128mkz + 288U, // VFNMSUB213PDZ128r + 166180U, // VFNMSUB213PDZ128rk + 166180U, // VFNMSUB213PDZ128rkz + 608U, // VFNMSUB213PDZ256m + 6720U, // VFNMSUB213PDZ256mb + 2165028U, // VFNMSUB213PDZ256mbk + 2165028U, // VFNMSUB213PDZ256mbkz + 231716U, // VFNMSUB213PDZ256mk + 231716U, // VFNMSUB213PDZ256mkz + 288U, // VFNMSUB213PDZ256r + 166180U, // VFNMSUB213PDZ256rk + 166180U, // VFNMSUB213PDZ256rkz + 1056U, // VFNMSUB213PDZm + 8768U, // VFNMSUB213PDZmb + 3213604U, // VFNMSUB213PDZmbk + 3213604U, // VFNMSUB213PDZmbkz + 297252U, // VFNMSUB213PDZmk + 297252U, // VFNMSUB213PDZmkz + 288U, // VFNMSUB213PDZr + 887072U, // VFNMSUB213PDZrb + 4360484U, // VFNMSUB213PDZrbk + 4360484U, // VFNMSUB213PDZrbkz + 166180U, // VFNMSUB213PDZrk + 166180U, // VFNMSUB213PDZrkz + 256U, // VFNMSUB213PDm + 288U, // VFNMSUB213PDr + 608U, // VFNMSUB213PSYm + 288U, // VFNMSUB213PSYr + 256U, // VFNMSUB213PSZ128m + 6880U, // VFNMSUB213PSZ128mb + 2492708U, // VFNMSUB213PSZ128mbk + 2492708U, // VFNMSUB213PSZ128mbkz + 35108U, // VFNMSUB213PSZ128mk + 35108U, // VFNMSUB213PSZ128mkz + 288U, // VFNMSUB213PSZ128r + 166180U, // VFNMSUB213PSZ128rk + 166180U, // VFNMSUB213PSZ128rkz + 608U, // VFNMSUB213PSZ256m + 8928U, // VFNMSUB213PSZ256mb + 3541284U, // VFNMSUB213PSZ256mbk + 3541284U, // VFNMSUB213PSZ256mbkz + 231716U, // VFNMSUB213PSZ256mk + 231716U, // VFNMSUB213PSZ256mkz + 288U, // VFNMSUB213PSZ256r + 166180U, // VFNMSUB213PSZ256rk + 166180U, // VFNMSUB213PSZ256rkz + 1056U, // VFNMSUB213PSZm + 10976U, // VFNMSUB213PSZmb + 5638436U, // VFNMSUB213PSZmbk + 5638436U, // VFNMSUB213PSZmbkz + 297252U, // VFNMSUB213PSZmk + 297252U, // VFNMSUB213PSZmkz + 288U, // VFNMSUB213PSZr + 887072U, // VFNMSUB213PSZrb + 4360484U, // VFNMSUB213PSZrbk + 4360484U, // VFNMSUB213PSZrbkz + 166180U, // VFNMSUB213PSZrk + 166180U, // VFNMSUB213PSZrkz + 256U, // VFNMSUB213PSm + 288U, // VFNMSUB213PSr + 576U, // VFNMSUB213SDZm + 576U, // VFNMSUB213SDZm_Int + 67876U, // VFNMSUB213SDZm_Intk + 67876U, // VFNMSUB213SDZm_Intkz + 288U, // VFNMSUB213SDZr + 288U, // VFNMSUB213SDZr_Int + 166180U, // VFNMSUB213SDZr_Intk + 166180U, // VFNMSUB213SDZr_Intkz + 288U, // VFNMSUB213SDZrb + 887072U, // VFNMSUB213SDZrb_Int + 4360484U, // VFNMSUB213SDZrb_Intk + 4360484U, // VFNMSUB213SDZrb_Intkz + 576U, // VFNMSUB213SDm + 576U, // VFNMSUB213SDm_Int + 288U, // VFNMSUB213SDr + 288U, // VFNMSUB213SDr_Int + 736U, // VFNMSUB213SSZm + 736U, // VFNMSUB213SSZm_Int + 395556U, // VFNMSUB213SSZm_Intk + 395556U, // VFNMSUB213SSZm_Intkz + 288U, // VFNMSUB213SSZr + 288U, // VFNMSUB213SSZr_Int + 166180U, // VFNMSUB213SSZr_Intk + 166180U, // VFNMSUB213SSZr_Intkz + 288U, // VFNMSUB213SSZrb + 887072U, // VFNMSUB213SSZrb_Int + 4360484U, // VFNMSUB213SSZrb_Intk + 4360484U, // VFNMSUB213SSZrb_Intkz + 736U, // VFNMSUB213SSm + 736U, // VFNMSUB213SSm_Int + 288U, // VFNMSUB213SSr + 288U, // VFNMSUB213SSr_Int + 608U, // VFNMSUB231PDYm + 288U, // VFNMSUB231PDYr + 256U, // VFNMSUB231PDZ128m + 4672U, // VFNMSUB231PDZ128mb + 1116452U, // VFNMSUB231PDZ128mbk + 1116452U, // VFNMSUB231PDZ128mbkz + 35108U, // VFNMSUB231PDZ128mk + 35108U, // VFNMSUB231PDZ128mkz + 288U, // VFNMSUB231PDZ128r + 166180U, // VFNMSUB231PDZ128rk + 166180U, // VFNMSUB231PDZ128rkz + 608U, // VFNMSUB231PDZ256m + 6720U, // VFNMSUB231PDZ256mb + 2165028U, // VFNMSUB231PDZ256mbk + 2165028U, // VFNMSUB231PDZ256mbkz + 231716U, // VFNMSUB231PDZ256mk + 231716U, // VFNMSUB231PDZ256mkz + 288U, // VFNMSUB231PDZ256r + 166180U, // VFNMSUB231PDZ256rk + 166180U, // VFNMSUB231PDZ256rkz + 1056U, // VFNMSUB231PDZm + 8768U, // VFNMSUB231PDZmb + 3213604U, // VFNMSUB231PDZmbk + 3213604U, // VFNMSUB231PDZmbkz + 297252U, // VFNMSUB231PDZmk + 297252U, // VFNMSUB231PDZmkz + 288U, // VFNMSUB231PDZr + 887072U, // VFNMSUB231PDZrb + 4360484U, // VFNMSUB231PDZrbk + 4360484U, // VFNMSUB231PDZrbkz + 166180U, // VFNMSUB231PDZrk + 166180U, // VFNMSUB231PDZrkz + 256U, // VFNMSUB231PDm + 288U, // VFNMSUB231PDr + 608U, // VFNMSUB231PSYm + 288U, // VFNMSUB231PSYr + 256U, // VFNMSUB231PSZ128m + 6880U, // VFNMSUB231PSZ128mb + 2492708U, // VFNMSUB231PSZ128mbk + 2492708U, // VFNMSUB231PSZ128mbkz + 35108U, // VFNMSUB231PSZ128mk + 35108U, // VFNMSUB231PSZ128mkz + 288U, // VFNMSUB231PSZ128r + 166180U, // VFNMSUB231PSZ128rk + 166180U, // VFNMSUB231PSZ128rkz + 608U, // VFNMSUB231PSZ256m + 8928U, // VFNMSUB231PSZ256mb + 3541284U, // VFNMSUB231PSZ256mbk + 3541284U, // VFNMSUB231PSZ256mbkz + 231716U, // VFNMSUB231PSZ256mk + 231716U, // VFNMSUB231PSZ256mkz + 288U, // VFNMSUB231PSZ256r + 166180U, // VFNMSUB231PSZ256rk + 166180U, // VFNMSUB231PSZ256rkz + 1056U, // VFNMSUB231PSZm + 10976U, // VFNMSUB231PSZmb + 5638436U, // VFNMSUB231PSZmbk + 5638436U, // VFNMSUB231PSZmbkz + 297252U, // VFNMSUB231PSZmk + 297252U, // VFNMSUB231PSZmkz + 288U, // VFNMSUB231PSZr + 887072U, // VFNMSUB231PSZrb + 4360484U, // VFNMSUB231PSZrbk + 4360484U, // VFNMSUB231PSZrbkz + 166180U, // VFNMSUB231PSZrk + 166180U, // VFNMSUB231PSZrkz + 256U, // VFNMSUB231PSm + 288U, // VFNMSUB231PSr + 576U, // VFNMSUB231SDZm + 576U, // VFNMSUB231SDZm_Int + 67876U, // VFNMSUB231SDZm_Intk + 67876U, // VFNMSUB231SDZm_Intkz + 288U, // VFNMSUB231SDZr + 288U, // VFNMSUB231SDZr_Int + 166180U, // VFNMSUB231SDZr_Intk + 166180U, // VFNMSUB231SDZr_Intkz + 288U, // VFNMSUB231SDZrb + 887072U, // VFNMSUB231SDZrb_Int + 4360484U, // VFNMSUB231SDZrb_Intk + 4360484U, // VFNMSUB231SDZrb_Intkz + 576U, // VFNMSUB231SDm + 576U, // VFNMSUB231SDm_Int + 288U, // VFNMSUB231SDr + 288U, // VFNMSUB231SDr_Int + 736U, // VFNMSUB231SSZm + 736U, // VFNMSUB231SSZm_Int + 395556U, // VFNMSUB231SSZm_Intk + 395556U, // VFNMSUB231SSZm_Intkz + 288U, // VFNMSUB231SSZr + 288U, // VFNMSUB231SSZr_Int + 166180U, // VFNMSUB231SSZr_Intk + 166180U, // VFNMSUB231SSZr_Intkz + 288U, // VFNMSUB231SSZrb + 887072U, // VFNMSUB231SSZrb_Int + 4360484U, // VFNMSUB231SSZrb_Intk + 4360484U, // VFNMSUB231SSZrb_Intkz + 736U, // VFNMSUB231SSm + 736U, // VFNMSUB231SSm_Int + 288U, // VFNMSUB231SSr + 288U, // VFNMSUB231SSr_Int + 854336U, // VFNMSUBPD4Ymr + 264288U, // VFNMSUBPD4Yrm + 198752U, // VFNMSUBPD4Yrr + 198752U, // VFNMSUBPD4Yrr_REV + 854368U, // VFNMSUBPD4mr + 133216U, // VFNMSUBPD4rm + 198752U, // VFNMSUBPD4rr + 198752U, // VFNMSUBPD4rr_REV + 854336U, // VFNMSUBPS4Ymr + 264288U, // VFNMSUBPS4Yrm + 198752U, // VFNMSUBPS4Yrr + 198752U, // VFNMSUBPS4Yrr_REV + 854368U, // VFNMSUBPS4mr + 133216U, // VFNMSUBPS4rm + 198752U, // VFNMSUBPS4rr + 198752U, // VFNMSUBPS4rr_REV + 854400U, // VFNMSUBSD4mr + 854400U, // VFNMSUBSD4mr_Int + 100448U, // VFNMSUBSD4rm + 100448U, // VFNMSUBSD4rm_Int + 198752U, // VFNMSUBSD4rr + 198752U, // VFNMSUBSD4rr_Int + 198752U, // VFNMSUBSD4rr_Int_REV + 198752U, // VFNMSUBSD4rr_REV + 854464U, // VFNMSUBSS4mr + 854464U, // VFNMSUBSS4mr_Int + 428128U, // VFNMSUBSS4rm + 428128U, // VFNMSUBSS4rm_Int + 198752U, // VFNMSUBSS4rr + 198752U, // VFNMSUBSS4rr_Int + 198752U, // VFNMSUBSS4rr_Int_REV + 198752U, // VFNMSUBSS4rr_REV + 0U, // VFPCLASSPDZ128rm + 11U, // VFPCLASSPDZ128rmb + 477572U, // VFPCLASSPDZ128rmbk + 461156U, // VFPCLASSPDZ128rmk + 32U, // VFPCLASSPDZ128rr + 624740U, // VFPCLASSPDZ128rrk + 0U, // VFPCLASSPDZ256rm + 12U, // VFPCLASSPDZ256rmb + 471428U, // VFPCLASSPDZ256rmbk + 461124U, // VFPCLASSPDZ256rmk + 32U, // VFPCLASSPDZ256rr + 624740U, // VFPCLASSPDZ256rrk + 0U, // VFPCLASSPDZrm + 12U, // VFPCLASSPDZrmb + 473476U, // VFPCLASSPDZrmbk + 461220U, // VFPCLASSPDZrmk + 32U, // VFPCLASSPDZrr + 624740U, // VFPCLASSPDZrrk + 0U, // VFPCLASSPSZ128rm + 12U, // VFPCLASSPSZ128rmb + 471492U, // VFPCLASSPSZ128rmbk + 461156U, // VFPCLASSPSZ128rmk + 32U, // VFPCLASSPSZ128rr + 624740U, // VFPCLASSPSZ128rrk + 0U, // VFPCLASSPSZ256rm + 12U, // VFPCLASSPSZ256rmb + 473540U, // VFPCLASSPSZ256rmbk + 461124U, // VFPCLASSPSZ256rmk + 32U, // VFPCLASSPSZ256rr + 624740U, // VFPCLASSPSZ256rrk + 0U, // VFPCLASSPSZrm + 13U, // VFPCLASSPSZrmb + 475588U, // VFPCLASSPSZrmbk + 461220U, // VFPCLASSPSZrmk + 32U, // VFPCLASSPSZrr + 624740U, // VFPCLASSPSZrrk + 0U, // VFPCLASSSDZrm + 461188U, // VFPCLASSSDZrmk + 32U, // VFPCLASSSDZrr + 624740U, // VFPCLASSSDZrrk + 0U, // VFPCLASSSSZrm + 461252U, // VFPCLASSSSZrmk + 32U, // VFPCLASSSSZrr + 624740U, // VFPCLASSSSZrrk + 0U, // VFRCZPDYrm + 0U, // VFRCZPDYrr + 0U, // VFRCZPDrm + 0U, // VFRCZPDrr + 0U, // VFRCZPSYrm + 0U, // VFRCZPSYrr + 0U, // VFRCZPSrm + 0U, // VFRCZPSrr + 0U, // VFRCZSDrm + 0U, // VFRCZSDrr + 0U, // VFRCZSSrm + 0U, // VFRCZSSrr + 0U, // VGATHERDPDYrm + 13U, // VGATHERDPDZ128rm + 14U, // VGATHERDPDZ256rm + 14U, // VGATHERDPDZrm + 0U, // VGATHERDPDrm + 0U, // VGATHERDPSYrm + 13U, // VGATHERDPSZ128rm + 14U, // VGATHERDPSZ256rm + 14U, // VGATHERDPSZrm + 0U, // VGATHERDPSrm + 0U, // VGATHERPF0DPDm + 0U, // VGATHERPF0DPSm + 0U, // VGATHERPF0QPDm + 0U, // VGATHERPF0QPSm + 0U, // VGATHERPF1DPDm + 0U, // VGATHERPF1DPSm + 0U, // VGATHERPF1QPDm + 0U, // VGATHERPF1QPSm + 0U, // VGATHERQPDYrm + 13U, // VGATHERQPDZ128rm + 14U, // VGATHERQPDZ256rm + 14U, // VGATHERQPDZrm + 0U, // VGATHERQPDrm + 0U, // VGATHERQPSYrm + 15U, // VGATHERQPSZ128rm + 13U, // VGATHERQPSZ256rm + 14U, // VGATHERQPSZrm + 0U, // VGATHERQPSrm + 0U, // VGETEXPPDZ128m + 9U, // VGETEXPPDZ128mb + 4676U, // VGETEXPPDZ128mbk + 4484U, // VGETEXPPDZ128mbkz + 260U, // VGETEXPPDZ128mk + 356U, // VGETEXPPDZ128mkz + 0U, // VGETEXPPDZ128r + 292U, // VGETEXPPDZ128rk + 100U, // VGETEXPPDZ128rkz + 0U, // VGETEXPPDZ256m + 9U, // VGETEXPPDZ256mb + 6724U, // VGETEXPPDZ256mbk + 6532U, // VGETEXPPDZ256mbkz + 612U, // VGETEXPPDZ256mk + 324U, // VGETEXPPDZ256mkz + 0U, // VGETEXPPDZ256r + 292U, // VGETEXPPDZ256rk + 100U, // VGETEXPPDZ256rkz + 0U, // VGETEXPPDZm + 10U, // VGETEXPPDZmb + 8772U, // VGETEXPPDZmbk + 8580U, // VGETEXPPDZmbkz + 1060U, // VGETEXPPDZmk + 420U, // VGETEXPPDZmkz + 0U, // VGETEXPPDZr + 8U, // VGETEXPPDZrb + 20772U, // VGETEXPPDZrbk + 20580U, // VGETEXPPDZrbkz + 292U, // VGETEXPPDZrk + 100U, // VGETEXPPDZrkz + 0U, // VGETEXPPSZ128m + 9U, // VGETEXPPSZ128mb + 6884U, // VGETEXPPSZ128mbk + 6596U, // VGETEXPPSZ128mbkz + 260U, // VGETEXPPSZ128mk + 356U, // VGETEXPPSZ128mkz + 0U, // VGETEXPPSZ128r + 292U, // VGETEXPPSZ128rk + 100U, // VGETEXPPSZ128rkz + 0U, // VGETEXPPSZ256m + 10U, // VGETEXPPSZ256mb + 8932U, // VGETEXPPSZ256mbk + 8644U, // VGETEXPPSZ256mbkz + 612U, // VGETEXPPSZ256mk + 324U, // VGETEXPPSZ256mkz + 0U, // VGETEXPPSZ256r + 292U, // VGETEXPPSZ256rk + 100U, // VGETEXPPSZ256rkz + 0U, // VGETEXPPSZm + 10U, // VGETEXPPSZmb + 10980U, // VGETEXPPSZmbk + 10692U, // VGETEXPPSZmbkz + 1060U, // VGETEXPPSZmk + 420U, // VGETEXPPSZmkz + 0U, // VGETEXPPSZr + 8U, // VGETEXPPSZrb + 20772U, // VGETEXPPSZrbk + 20580U, // VGETEXPPSZrbkz + 292U, // VGETEXPPSZrk + 100U, // VGETEXPPSZrkz + 384U, // VGETEXPSDZm + 67876U, // VGETEXPSDZmk + 100452U, // VGETEXPSDZmkz + 96U, // VGETEXPSDZr + 20576U, // VGETEXPSDZrb + 11700516U, // VGETEXPSDZrbk + 11733092U, // VGETEXPSDZrbkz + 166180U, // VGETEXPSDZrk + 198756U, // VGETEXPSDZrkz + 448U, // VGETEXPSSZm + 395556U, // VGETEXPSSZmk + 428132U, // VGETEXPSSZmkz + 96U, // VGETEXPSSZr + 20576U, // VGETEXPSSZrb + 11700516U, // VGETEXPSSZrbk + 11733092U, // VGETEXPSSZrbkz + 166180U, // VGETEXPSSZrk + 198756U, // VGETEXPSSZrkz + 11U, // VGETMANTPDZ128rmbi + 936516U, // VGETMANTPDZ128rmbik + 477572U, // VGETMANTPDZ128rmbikz + 0U, // VGETMANTPDZ128rmi + 919812U, // VGETMANTPDZ128rmik + 461156U, // VGETMANTPDZ128rmikz + 32U, // VGETMANTPDZ128rri + 2340U, // VGETMANTPDZ128rrik + 624740U, // VGETMANTPDZ128rrikz + 12U, // VGETMANTPDZ256rmbi + 930372U, // VGETMANTPDZ256rmbik + 471428U, // VGETMANTPDZ256rmbikz + 0U, // VGETMANTPDZ256rmi + 920164U, // VGETMANTPDZ256rmik + 461124U, // VGETMANTPDZ256rmikz + 32U, // VGETMANTPDZ256rri + 2340U, // VGETMANTPDZ256rrik + 624740U, // VGETMANTPDZ256rrikz + 12U, // VGETMANTPDZrmbi + 932420U, // VGETMANTPDZrmbik + 473476U, // VGETMANTPDZrmbikz + 0U, // VGETMANTPDZrmi + 920612U, // VGETMANTPDZrmik + 461220U, // VGETMANTPDZrmikz + 32U, // VGETMANTPDZrri + 11U, // VGETMANTPDZrrib + 22820U, // VGETMANTPDZrribk + 645220U, // VGETMANTPDZrribkz + 2340U, // VGETMANTPDZrrik + 624740U, // VGETMANTPDZrrikz + 12U, // VGETMANTPSZ128rmbi + 930532U, // VGETMANTPSZ128rmbik + 471492U, // VGETMANTPSZ128rmbikz + 0U, // VGETMANTPSZ128rmi + 919812U, // VGETMANTPSZ128rmik + 461156U, // VGETMANTPSZ128rmikz + 32U, // VGETMANTPSZ128rri + 2340U, // VGETMANTPSZ128rrik + 624740U, // VGETMANTPSZ128rrikz + 12U, // VGETMANTPSZ256rmbi + 932580U, // VGETMANTPSZ256rmbik + 473540U, // VGETMANTPSZ256rmbikz + 0U, // VGETMANTPSZ256rmi + 920164U, // VGETMANTPSZ256rmik + 461124U, // VGETMANTPSZ256rmikz + 32U, // VGETMANTPSZ256rri + 2340U, // VGETMANTPSZ256rrik + 624740U, // VGETMANTPSZ256rrikz + 13U, // VGETMANTPSZrmbi + 934628U, // VGETMANTPSZrmbik + 475588U, // VGETMANTPSZrmbikz + 0U, // VGETMANTPSZrmi + 920612U, // VGETMANTPSZrmik + 461220U, // VGETMANTPSZrmikz + 32U, // VGETMANTPSZrri + 11U, // VGETMANTPSZrrib + 22820U, // VGETMANTPSZrribk + 645220U, // VGETMANTPSZrribkz + 2340U, // VGETMANTPSZrrik + 624740U, // VGETMANTPSZrrikz + 461184U, // VGETMANTSDZrmi + 37816612U, // VGETMANTSDZrmik + 54626404U, // VGETMANTSDZrmikz + 624736U, // VGETMANTSDZrri + 645216U, // VGETMANTSDZrrib + 77760804U, // VGETMANTSDZrribk + 94570596U, // VGETMANTSDZrribkz + 71469348U, // VGETMANTSDZrrik + 88279140U, // VGETMANTSDZrrikz + 461248U, // VGETMANTSSZrmi + 38144292U, // VGETMANTSSZrmik + 54954084U, // VGETMANTSSZrmikz + 624736U, // VGETMANTSSZrri + 645216U, // VGETMANTSSZrrib + 77760804U, // VGETMANTSSZrribk + 94570596U, // VGETMANTSSZrribkz + 71469348U, // VGETMANTSSZrrik + 88279140U, // VGETMANTSSZrrikz + 461280U, // VGF2P8AFFINEINVQBYrmi + 624736U, // VGF2P8AFFINEINVQBYrri + 478304U, // VGF2P8AFFINEINVQBZ128rmbi + 43944228U, // VGF2P8AFFINEINVQBZ128rmbik + 60754020U, // VGF2P8AFFINEINVQBZ128rmbikz + 461312U, // VGF2P8AFFINEINVQBZ128rmi + 38308132U, // VGF2P8AFFINEINVQBZ128rmik + 55117924U, // VGF2P8AFFINEINVQBZ128rmikz + 624736U, // VGF2P8AFFINEINVQBZ128rri + 71469348U, // VGF2P8AFFINEINVQBZ128rrik + 88279140U, // VGF2P8AFFINEINVQBZ128rrikz + 472160U, // VGF2P8AFFINEINVQBZ256rmbi + 40798500U, // VGF2P8AFFINEINVQBZ256rmbik + 57608292U, // VGF2P8AFFINEINVQBZ256rmbikz + 461280U, // VGF2P8AFFINEINVQBZ256rmi + 38406436U, // VGF2P8AFFINEINVQBZ256rmik + 55216228U, // VGF2P8AFFINEINVQBZ256rmikz + 624736U, // VGF2P8AFFINEINVQBZ256rri + 71469348U, // VGF2P8AFFINEINVQBZ256rrik + 88279140U, // VGF2P8AFFINEINVQBZ256rrikz + 474208U, // VGF2P8AFFINEINVQBZrmbi + 41847076U, // VGF2P8AFFINEINVQBZrmbik + 58656868U, // VGF2P8AFFINEINVQBZrmbikz + 461344U, // VGF2P8AFFINEINVQBZrmi + 38471972U, // VGF2P8AFFINEINVQBZrmik + 55281764U, // VGF2P8AFFINEINVQBZrmikz + 624736U, // VGF2P8AFFINEINVQBZrri + 71469348U, // VGF2P8AFFINEINVQBZrrik + 88279140U, // VGF2P8AFFINEINVQBZrrikz + 461312U, // VGF2P8AFFINEINVQBrmi + 624736U, // VGF2P8AFFINEINVQBrri + 461280U, // VGF2P8AFFINEQBYrmi + 624736U, // VGF2P8AFFINEQBYrri + 478304U, // VGF2P8AFFINEQBZ128rmbi + 43944228U, // VGF2P8AFFINEQBZ128rmbik + 60754020U, // VGF2P8AFFINEQBZ128rmbikz + 461312U, // VGF2P8AFFINEQBZ128rmi + 38308132U, // VGF2P8AFFINEQBZ128rmik + 55117924U, // VGF2P8AFFINEQBZ128rmikz + 624736U, // VGF2P8AFFINEQBZ128rri + 71469348U, // VGF2P8AFFINEQBZ128rrik + 88279140U, // VGF2P8AFFINEQBZ128rrikz + 472160U, // VGF2P8AFFINEQBZ256rmbi + 40798500U, // VGF2P8AFFINEQBZ256rmbik + 57608292U, // VGF2P8AFFINEQBZ256rmbikz + 461280U, // VGF2P8AFFINEQBZ256rmi + 38406436U, // VGF2P8AFFINEQBZ256rmik + 55216228U, // VGF2P8AFFINEQBZ256rmikz + 624736U, // VGF2P8AFFINEQBZ256rri + 71469348U, // VGF2P8AFFINEQBZ256rrik + 88279140U, // VGF2P8AFFINEQBZ256rrikz + 474208U, // VGF2P8AFFINEQBZrmbi + 41847076U, // VGF2P8AFFINEQBZrmbik + 58656868U, // VGF2P8AFFINEQBZrmbikz + 461344U, // VGF2P8AFFINEQBZrmi + 38471972U, // VGF2P8AFFINEQBZrmik + 55281764U, // VGF2P8AFFINEQBZrmikz + 624736U, // VGF2P8AFFINEQBZrri + 71469348U, // VGF2P8AFFINEQBZrrik + 88279140U, // VGF2P8AFFINEQBZrrikz + 461312U, // VGF2P8AFFINEQBrmi + 624736U, // VGF2P8AFFINEQBrri + 480U, // VGF2P8MULBYrm + 96U, // VGF2P8MULBYrr + 512U, // VGF2P8MULBZ128rm + 559396U, // VGF2P8MULBZ128rmk + 591972U, // VGF2P8MULBZ128rmkz + 96U, // VGF2P8MULBZ128rr + 166180U, // VGF2P8MULBZ128rrk + 198756U, // VGF2P8MULBZ128rrkz + 480U, // VGF2P8MULBZ256rm + 657700U, // VGF2P8MULBZ256rmk + 690276U, // VGF2P8MULBZ256rmkz + 96U, // VGF2P8MULBZ256rr + 166180U, // VGF2P8MULBZ256rrk + 198756U, // VGF2P8MULBZ256rrkz + 544U, // VGF2P8MULBZrm + 723236U, // VGF2P8MULBZrmk + 755812U, // VGF2P8MULBZrmkz + 96U, // VGF2P8MULBZrr + 166180U, // VGF2P8MULBZrrk + 198756U, // VGF2P8MULBZrrkz + 512U, // VGF2P8MULBrm + 96U, // VGF2P8MULBrr + 320U, // VHADDPDYrm + 96U, // VHADDPDYrr + 352U, // VHADDPDrm + 96U, // VHADDPDrr + 320U, // VHADDPSYrm + 96U, // VHADDPSYrr + 352U, // VHADDPSrm + 96U, // VHADDPSrr + 320U, // VHSUBPDYrm + 96U, // VHSUBPDYrr + 352U, // VHSUBPDrm + 96U, // VHSUBPDrr + 320U, // VHSUBPSYrm + 96U, // VHSUBPSYrr + 352U, // VHSUBPSrm + 96U, // VHSUBPSrr + 461152U, // VINSERTF128rm + 624736U, // VINSERTF128rr + 461152U, // VINSERTF32x4Z256rm + 37783844U, // VINSERTF32x4Z256rmk + 54659172U, // VINSERTF32x4Z256rmkz + 624736U, // VINSERTF32x4Z256rr + 71469348U, // VINSERTF32x4Z256rrk + 88279140U, // VINSERTF32x4Z256rrkz + 461152U, // VINSERTF32x4Zrm + 37783844U, // VINSERTF32x4Zrmk + 54659172U, // VINSERTF32x4Zrmkz + 624736U, // VINSERTF32x4Zrr + 71469348U, // VINSERTF32x4Zrrk + 88279140U, // VINSERTF32x4Zrrkz + 461120U, // VINSERTF32x8Zrm + 37980452U, // VINSERTF32x8Zrmk + 54790244U, // VINSERTF32x8Zrmkz + 624736U, // VINSERTF32x8Zrr + 71469348U, // VINSERTF32x8Zrrk + 88279140U, // VINSERTF32x8Zrrkz + 461152U, // VINSERTF64x2Z256rm + 37783844U, // VINSERTF64x2Z256rmk + 54659172U, // VINSERTF64x2Z256rmkz + 624736U, // VINSERTF64x2Z256rr + 71469348U, // VINSERTF64x2Z256rrk + 88279140U, // VINSERTF64x2Z256rrkz + 461152U, // VINSERTF64x2Zrm + 37783844U, // VINSERTF64x2Zrmk + 54659172U, // VINSERTF64x2Zrmkz + 624736U, // VINSERTF64x2Zrr + 71469348U, // VINSERTF64x2Zrrk + 88279140U, // VINSERTF64x2Zrrkz + 461120U, // VINSERTF64x4Zrm + 37980452U, // VINSERTF64x4Zrmk + 54790244U, // VINSERTF64x4Zrmkz + 624736U, // VINSERTF64x4Zrr + 71469348U, // VINSERTF64x4Zrrk + 88279140U, // VINSERTF64x4Zrrkz + 461312U, // VINSERTI128rm + 624736U, // VINSERTI128rr + 461312U, // VINSERTI32x4Z256rm + 38308132U, // VINSERTI32x4Z256rmk + 55117924U, // VINSERTI32x4Z256rmkz + 624736U, // VINSERTI32x4Z256rr + 71469348U, // VINSERTI32x4Z256rrk + 88279140U, // VINSERTI32x4Z256rrkz + 461312U, // VINSERTI32x4Zrm + 38308132U, // VINSERTI32x4Zrmk + 55117924U, // VINSERTI32x4Zrmkz + 624736U, // VINSERTI32x4Zrr + 71469348U, // VINSERTI32x4Zrrk + 88279140U, // VINSERTI32x4Zrrkz + 461280U, // VINSERTI32x8Zrm + 38406436U, // VINSERTI32x8Zrmk + 55216228U, // VINSERTI32x8Zrmkz + 624736U, // VINSERTI32x8Zrr + 71469348U, // VINSERTI32x8Zrrk + 88279140U, // VINSERTI32x8Zrrkz + 461312U, // VINSERTI64x2Z256rm + 38308132U, // VINSERTI64x2Z256rmk + 55117924U, // VINSERTI64x2Z256rmkz + 624736U, // VINSERTI64x2Z256rr + 71469348U, // VINSERTI64x2Z256rrk + 88279140U, // VINSERTI64x2Z256rrkz + 461312U, // VINSERTI64x2Zrm + 38308132U, // VINSERTI64x2Zrmk + 55117924U, // VINSERTI64x2Zrmkz + 624736U, // VINSERTI64x2Zrr + 71469348U, // VINSERTI64x2Zrrk + 88279140U, // VINSERTI64x2Zrrkz + 461280U, // VINSERTI64x4Zrm + 38406436U, // VINSERTI64x4Zrmk + 55216228U, // VINSERTI64x4Zrmkz + 624736U, // VINSERTI64x4Zrr + 71469348U, // VINSERTI64x4Zrrk + 88279140U, // VINSERTI64x4Zrrkz + 461248U, // VINSERTPSZrm + 624736U, // VINSERTPSZrr + 461248U, // VINSERTPSrm + 624736U, // VINSERTPSrr + 0U, // VLDDQUYrm + 0U, // VLDDQUrm + 0U, // VLDMXCSR + 0U, // VMASKMOVDQU + 0U, // VMASKMOVDQU64 + 160U, // VMASKMOVPDYmr + 320U, // VMASKMOVPDYrm + 160U, // VMASKMOVPDmr + 352U, // VMASKMOVPDrm + 160U, // VMASKMOVPSYmr + 320U, // VMASKMOVPSYrm + 160U, // VMASKMOVPSmr + 352U, // VMASKMOVPSrm + 320U, // VMAXCPDYrm + 96U, // VMAXCPDYrr + 352U, // VMAXCPDZ128rm + 4480U, // VMAXCPDZ128rmb + 1116452U, // VMAXCPDZ128rmbk + 1149028U, // VMAXCPDZ128rmbkz + 35108U, // VMAXCPDZ128rmk + 133220U, // VMAXCPDZ128rmkz + 96U, // VMAXCPDZ128rr + 166180U, // VMAXCPDZ128rrk + 198756U, // VMAXCPDZ128rrkz + 320U, // VMAXCPDZ256rm + 6528U, // VMAXCPDZ256rmb + 2165028U, // VMAXCPDZ256rmbk + 2197604U, // VMAXCPDZ256rmbkz + 231716U, // VMAXCPDZ256rmk + 264292U, // VMAXCPDZ256rmkz + 96U, // VMAXCPDZ256rr + 166180U, // VMAXCPDZ256rrk + 198756U, // VMAXCPDZ256rrkz + 416U, // VMAXCPDZrm + 8576U, // VMAXCPDZrmb + 3213604U, // VMAXCPDZrmbk + 3246180U, // VMAXCPDZrmbkz + 297252U, // VMAXCPDZrmk + 329828U, // VMAXCPDZrmkz + 96U, // VMAXCPDZrr + 166180U, // VMAXCPDZrrk + 198756U, // VMAXCPDZrrkz + 352U, // VMAXCPDrm + 96U, // VMAXCPDrr + 320U, // VMAXCPSYrm + 96U, // VMAXCPSYrr + 352U, // VMAXCPSZ128rm + 6592U, // VMAXCPSZ128rmb + 2492708U, // VMAXCPSZ128rmbk + 2525284U, // VMAXCPSZ128rmbkz + 35108U, // VMAXCPSZ128rmk + 133220U, // VMAXCPSZ128rmkz + 96U, // VMAXCPSZ128rr + 166180U, // VMAXCPSZ128rrk + 198756U, // VMAXCPSZ128rrkz + 320U, // VMAXCPSZ256rm + 8640U, // VMAXCPSZ256rmb + 3541284U, // VMAXCPSZ256rmbk + 3573860U, // VMAXCPSZ256rmbkz + 231716U, // VMAXCPSZ256rmk + 264292U, // VMAXCPSZ256rmkz + 96U, // VMAXCPSZ256rr + 166180U, // VMAXCPSZ256rrk + 198756U, // VMAXCPSZ256rrkz + 416U, // VMAXCPSZrm + 10688U, // VMAXCPSZrmb + 5638436U, // VMAXCPSZrmbk + 5671012U, // VMAXCPSZrmbkz + 297252U, // VMAXCPSZrmk + 329828U, // VMAXCPSZrmkz + 96U, // VMAXCPSZrr + 166180U, // VMAXCPSZrrk + 198756U, // VMAXCPSZrrkz + 352U, // VMAXCPSrm + 96U, // VMAXCPSrr + 384U, // VMAXCSDZrm + 96U, // VMAXCSDZrr + 384U, // VMAXCSDrm + 96U, // VMAXCSDrr + 448U, // VMAXCSSZrm + 96U, // VMAXCSSZrr + 448U, // VMAXCSSrm + 96U, // VMAXCSSrr + 320U, // VMAXPDYrm + 96U, // VMAXPDYrr + 352U, // VMAXPDZ128rm + 4480U, // VMAXPDZ128rmb + 1116452U, // VMAXPDZ128rmbk + 1149028U, // VMAXPDZ128rmbkz + 35108U, // VMAXPDZ128rmk + 133220U, // VMAXPDZ128rmkz + 96U, // VMAXPDZ128rr + 166180U, // VMAXPDZ128rrk + 198756U, // VMAXPDZ128rrkz + 320U, // VMAXPDZ256rm + 6528U, // VMAXPDZ256rmb + 2165028U, // VMAXPDZ256rmbk + 2197604U, // VMAXPDZ256rmbkz + 231716U, // VMAXPDZ256rmk + 264292U, // VMAXPDZ256rmkz + 96U, // VMAXPDZ256rr + 166180U, // VMAXPDZ256rrk + 198756U, // VMAXPDZ256rrkz + 416U, // VMAXPDZrm + 8576U, // VMAXPDZrmb + 3213604U, // VMAXPDZrmbk + 3246180U, // VMAXPDZrmbkz + 297252U, // VMAXPDZrmk + 329828U, // VMAXPDZrmkz + 96U, // VMAXPDZrr + 20576U, // VMAXPDZrrb + 11700516U, // VMAXPDZrrbk + 11733092U, // VMAXPDZrrbkz + 166180U, // VMAXPDZrrk + 198756U, // VMAXPDZrrkz + 352U, // VMAXPDrm + 96U, // VMAXPDrr + 320U, // VMAXPSYrm + 96U, // VMAXPSYrr + 352U, // VMAXPSZ128rm + 6592U, // VMAXPSZ128rmb + 2492708U, // VMAXPSZ128rmbk + 2525284U, // VMAXPSZ128rmbkz + 35108U, // VMAXPSZ128rmk + 133220U, // VMAXPSZ128rmkz + 96U, // VMAXPSZ128rr + 166180U, // VMAXPSZ128rrk + 198756U, // VMAXPSZ128rrkz + 320U, // VMAXPSZ256rm + 8640U, // VMAXPSZ256rmb + 3541284U, // VMAXPSZ256rmbk + 3573860U, // VMAXPSZ256rmbkz + 231716U, // VMAXPSZ256rmk + 264292U, // VMAXPSZ256rmkz + 96U, // VMAXPSZ256rr + 166180U, // VMAXPSZ256rrk + 198756U, // VMAXPSZ256rrkz + 416U, // VMAXPSZrm + 10688U, // VMAXPSZrmb + 5638436U, // VMAXPSZrmbk + 5671012U, // VMAXPSZrmbkz + 297252U, // VMAXPSZrmk + 329828U, // VMAXPSZrmkz + 96U, // VMAXPSZrr + 20576U, // VMAXPSZrrb + 11700516U, // VMAXPSZrrbk + 11733092U, // VMAXPSZrrbkz + 166180U, // VMAXPSZrrk + 198756U, // VMAXPSZrrkz + 352U, // VMAXPSrm + 96U, // VMAXPSrr + 384U, // VMAXSDZrm + 384U, // VMAXSDZrm_Int + 67876U, // VMAXSDZrm_Intk + 100452U, // VMAXSDZrm_Intkz + 96U, // VMAXSDZrr + 96U, // VMAXSDZrr_Int + 166180U, // VMAXSDZrr_Intk + 198756U, // VMAXSDZrr_Intkz + 20576U, // VMAXSDZrrb_Int + 11700516U, // VMAXSDZrrb_Intk + 11733092U, // VMAXSDZrrb_Intkz + 384U, // VMAXSDrm + 384U, // VMAXSDrm_Int + 96U, // VMAXSDrr + 96U, // VMAXSDrr_Int + 448U, // VMAXSSZrm + 448U, // VMAXSSZrm_Int + 395556U, // VMAXSSZrm_Intk + 428132U, // VMAXSSZrm_Intkz + 96U, // VMAXSSZrr + 96U, // VMAXSSZrr_Int + 166180U, // VMAXSSZrr_Intk + 198756U, // VMAXSSZrr_Intkz + 20576U, // VMAXSSZrrb_Int + 11700516U, // VMAXSSZrrb_Intk + 11733092U, // VMAXSSZrrb_Intkz + 448U, // VMAXSSrm + 448U, // VMAXSSrm_Int + 96U, // VMAXSSrr + 96U, // VMAXSSrr_Int + 0U, // VMCALL + 0U, // VMCLEARm + 0U, // VMFUNC + 320U, // VMINCPDYrm + 96U, // VMINCPDYrr + 352U, // VMINCPDZ128rm + 4480U, // VMINCPDZ128rmb + 1116452U, // VMINCPDZ128rmbk + 1149028U, // VMINCPDZ128rmbkz + 35108U, // VMINCPDZ128rmk + 133220U, // VMINCPDZ128rmkz + 96U, // VMINCPDZ128rr + 166180U, // VMINCPDZ128rrk + 198756U, // VMINCPDZ128rrkz + 320U, // VMINCPDZ256rm + 6528U, // VMINCPDZ256rmb + 2165028U, // VMINCPDZ256rmbk + 2197604U, // VMINCPDZ256rmbkz + 231716U, // VMINCPDZ256rmk + 264292U, // VMINCPDZ256rmkz + 96U, // VMINCPDZ256rr + 166180U, // VMINCPDZ256rrk + 198756U, // VMINCPDZ256rrkz + 416U, // VMINCPDZrm + 8576U, // VMINCPDZrmb + 3213604U, // VMINCPDZrmbk + 3246180U, // VMINCPDZrmbkz + 297252U, // VMINCPDZrmk + 329828U, // VMINCPDZrmkz + 96U, // VMINCPDZrr + 166180U, // VMINCPDZrrk + 198756U, // VMINCPDZrrkz + 352U, // VMINCPDrm + 96U, // VMINCPDrr + 320U, // VMINCPSYrm + 96U, // VMINCPSYrr + 352U, // VMINCPSZ128rm + 6592U, // VMINCPSZ128rmb + 2492708U, // VMINCPSZ128rmbk + 2525284U, // VMINCPSZ128rmbkz + 35108U, // VMINCPSZ128rmk + 133220U, // VMINCPSZ128rmkz + 96U, // VMINCPSZ128rr + 166180U, // VMINCPSZ128rrk + 198756U, // VMINCPSZ128rrkz + 320U, // VMINCPSZ256rm + 8640U, // VMINCPSZ256rmb + 3541284U, // VMINCPSZ256rmbk + 3573860U, // VMINCPSZ256rmbkz + 231716U, // VMINCPSZ256rmk + 264292U, // VMINCPSZ256rmkz + 96U, // VMINCPSZ256rr + 166180U, // VMINCPSZ256rrk + 198756U, // VMINCPSZ256rrkz + 416U, // VMINCPSZrm + 10688U, // VMINCPSZrmb + 5638436U, // VMINCPSZrmbk + 5671012U, // VMINCPSZrmbkz + 297252U, // VMINCPSZrmk + 329828U, // VMINCPSZrmkz + 96U, // VMINCPSZrr + 166180U, // VMINCPSZrrk + 198756U, // VMINCPSZrrkz + 352U, // VMINCPSrm + 96U, // VMINCPSrr + 384U, // VMINCSDZrm + 96U, // VMINCSDZrr + 384U, // VMINCSDrm + 96U, // VMINCSDrr + 448U, // VMINCSSZrm + 96U, // VMINCSSZrr + 448U, // VMINCSSrm + 96U, // VMINCSSrr + 320U, // VMINPDYrm + 96U, // VMINPDYrr + 352U, // VMINPDZ128rm + 4480U, // VMINPDZ128rmb + 1116452U, // VMINPDZ128rmbk + 1149028U, // VMINPDZ128rmbkz + 35108U, // VMINPDZ128rmk + 133220U, // VMINPDZ128rmkz + 96U, // VMINPDZ128rr + 166180U, // VMINPDZ128rrk + 198756U, // VMINPDZ128rrkz + 320U, // VMINPDZ256rm + 6528U, // VMINPDZ256rmb + 2165028U, // VMINPDZ256rmbk + 2197604U, // VMINPDZ256rmbkz + 231716U, // VMINPDZ256rmk + 264292U, // VMINPDZ256rmkz + 96U, // VMINPDZ256rr + 166180U, // VMINPDZ256rrk + 198756U, // VMINPDZ256rrkz + 416U, // VMINPDZrm + 8576U, // VMINPDZrmb + 3213604U, // VMINPDZrmbk + 3246180U, // VMINPDZrmbkz + 297252U, // VMINPDZrmk + 329828U, // VMINPDZrmkz + 96U, // VMINPDZrr + 20576U, // VMINPDZrrb + 11700516U, // VMINPDZrrbk + 11733092U, // VMINPDZrrbkz + 166180U, // VMINPDZrrk + 198756U, // VMINPDZrrkz + 352U, // VMINPDrm + 96U, // VMINPDrr + 320U, // VMINPSYrm + 96U, // VMINPSYrr + 352U, // VMINPSZ128rm + 6592U, // VMINPSZ128rmb + 2492708U, // VMINPSZ128rmbk + 2525284U, // VMINPSZ128rmbkz + 35108U, // VMINPSZ128rmk + 133220U, // VMINPSZ128rmkz + 96U, // VMINPSZ128rr + 166180U, // VMINPSZ128rrk + 198756U, // VMINPSZ128rrkz + 320U, // VMINPSZ256rm + 8640U, // VMINPSZ256rmb + 3541284U, // VMINPSZ256rmbk + 3573860U, // VMINPSZ256rmbkz + 231716U, // VMINPSZ256rmk + 264292U, // VMINPSZ256rmkz + 96U, // VMINPSZ256rr + 166180U, // VMINPSZ256rrk + 198756U, // VMINPSZ256rrkz + 416U, // VMINPSZrm + 10688U, // VMINPSZrmb + 5638436U, // VMINPSZrmbk + 5671012U, // VMINPSZrmbkz + 297252U, // VMINPSZrmk + 329828U, // VMINPSZrmkz + 96U, // VMINPSZrr + 20576U, // VMINPSZrrb + 11700516U, // VMINPSZrrbk + 11733092U, // VMINPSZrrbkz + 166180U, // VMINPSZrrk + 198756U, // VMINPSZrrkz + 352U, // VMINPSrm + 96U, // VMINPSrr + 384U, // VMINSDZrm + 384U, // VMINSDZrm_Int + 67876U, // VMINSDZrm_Intk + 100452U, // VMINSDZrm_Intkz + 96U, // VMINSDZrr + 96U, // VMINSDZrr_Int + 166180U, // VMINSDZrr_Intk + 198756U, // VMINSDZrr_Intkz + 20576U, // VMINSDZrrb_Int + 11700516U, // VMINSDZrrb_Intk + 11733092U, // VMINSDZrrb_Intkz + 384U, // VMINSDrm + 384U, // VMINSDrm_Int + 96U, // VMINSDrr + 96U, // VMINSDrr_Int + 448U, // VMINSSZrm + 448U, // VMINSSZrm_Int + 395556U, // VMINSSZrm_Intk + 428132U, // VMINSSZrm_Intkz + 96U, // VMINSSZrr + 96U, // VMINSSZrr_Int + 166180U, // VMINSSZrr_Intk + 198756U, // VMINSSZrr_Intkz + 20576U, // VMINSSZrrb_Int + 11700516U, // VMINSSZrrb_Intk + 11733092U, // VMINSSZrrb_Intkz + 448U, // VMINSSrm + 448U, // VMINSSrm_Int + 96U, // VMINSSrr + 96U, // VMINSSrr_Int + 0U, // VMLAUNCH + 0U, // VMLOAD32 + 0U, // VMLOAD64 + 0U, // VMMCALL + 0U, // VMOV64toPQIZrm + 0U, // VMOV64toPQIZrr + 0U, // VMOV64toPQIrm + 0U, // VMOV64toPQIrr + 0U, // VMOV64toSDZrm + 0U, // VMOV64toSDZrr + 0U, // VMOV64toSDrm + 0U, // VMOV64toSDrr + 0U, // VMOVAPDYmr + 0U, // VMOVAPDYrm + 0U, // VMOVAPDYrr + 0U, // VMOVAPDYrr_REV + 0U, // VMOVAPDZ128mr + 164U, // VMOVAPDZ128mrk + 0U, // VMOVAPDZ128rm + 260U, // VMOVAPDZ128rmk + 356U, // VMOVAPDZ128rmkz + 0U, // VMOVAPDZ128rr + 0U, // VMOVAPDZ128rr_REV + 292U, // VMOVAPDZ128rrk + 100U, // VMOVAPDZ128rrk_REV + 100U, // VMOVAPDZ128rrkz + 100U, // VMOVAPDZ128rrkz_REV + 0U, // VMOVAPDZ256mr + 164U, // VMOVAPDZ256mrk + 0U, // VMOVAPDZ256rm + 612U, // VMOVAPDZ256rmk + 324U, // VMOVAPDZ256rmkz + 0U, // VMOVAPDZ256rr + 0U, // VMOVAPDZ256rr_REV + 292U, // VMOVAPDZ256rrk + 100U, // VMOVAPDZ256rrk_REV + 100U, // VMOVAPDZ256rrkz + 100U, // VMOVAPDZ256rrkz_REV + 0U, // VMOVAPDZmr + 164U, // VMOVAPDZmrk + 0U, // VMOVAPDZrm + 1060U, // VMOVAPDZrmk + 420U, // VMOVAPDZrmkz + 0U, // VMOVAPDZrr + 0U, // VMOVAPDZrr_REV + 292U, // VMOVAPDZrrk + 100U, // VMOVAPDZrrk_REV + 100U, // VMOVAPDZrrkz + 100U, // VMOVAPDZrrkz_REV + 0U, // VMOVAPDmr + 0U, // VMOVAPDrm + 0U, // VMOVAPDrr + 0U, // VMOVAPDrr_REV + 0U, // VMOVAPSYmr + 0U, // VMOVAPSYrm + 0U, // VMOVAPSYrr + 0U, // VMOVAPSYrr_REV + 0U, // VMOVAPSZ128mr + 164U, // VMOVAPSZ128mrk + 0U, // VMOVAPSZ128rm + 260U, // VMOVAPSZ128rmk + 356U, // VMOVAPSZ128rmkz + 0U, // VMOVAPSZ128rr + 0U, // VMOVAPSZ128rr_REV + 292U, // VMOVAPSZ128rrk + 100U, // VMOVAPSZ128rrk_REV + 100U, // VMOVAPSZ128rrkz + 100U, // VMOVAPSZ128rrkz_REV + 0U, // VMOVAPSZ256mr + 164U, // VMOVAPSZ256mrk + 0U, // VMOVAPSZ256rm + 612U, // VMOVAPSZ256rmk + 324U, // VMOVAPSZ256rmkz + 0U, // VMOVAPSZ256rr + 0U, // VMOVAPSZ256rr_REV + 292U, // VMOVAPSZ256rrk + 100U, // VMOVAPSZ256rrk_REV + 100U, // VMOVAPSZ256rrkz + 100U, // VMOVAPSZ256rrkz_REV + 0U, // VMOVAPSZmr + 164U, // VMOVAPSZmrk + 0U, // VMOVAPSZrm + 1060U, // VMOVAPSZrmk + 420U, // VMOVAPSZrmkz + 0U, // VMOVAPSZrr + 0U, // VMOVAPSZrr_REV + 292U, // VMOVAPSZrrk + 100U, // VMOVAPSZrrk_REV + 100U, // VMOVAPSZrrkz + 100U, // VMOVAPSZrrkz_REV + 0U, // VMOVAPSmr + 0U, // VMOVAPSrm + 0U, // VMOVAPSrr + 0U, // VMOVAPSrr_REV + 0U, // VMOVDDUPYrm + 0U, // VMOVDDUPYrr + 0U, // VMOVDDUPZ128rm + 580U, // VMOVDDUPZ128rmk + 388U, // VMOVDDUPZ128rmkz + 0U, // VMOVDDUPZ128rr + 292U, // VMOVDDUPZ128rrk + 100U, // VMOVDDUPZ128rrkz + 0U, // VMOVDDUPZ256rm + 612U, // VMOVDDUPZ256rmk + 324U, // VMOVDDUPZ256rmkz + 0U, // VMOVDDUPZ256rr + 292U, // VMOVDDUPZ256rrk + 100U, // VMOVDDUPZ256rrkz + 0U, // VMOVDDUPZrm + 1060U, // VMOVDDUPZrmk + 420U, // VMOVDDUPZrmkz + 0U, // VMOVDDUPZrr + 292U, // VMOVDDUPZrrk + 100U, // VMOVDDUPZrrkz + 0U, // VMOVDDUPrm + 0U, // VMOVDDUPrr + 0U, // VMOVDI2PDIZrm + 0U, // VMOVDI2PDIZrr + 0U, // VMOVDI2PDIrm + 0U, // VMOVDI2PDIrr + 0U, // VMOVDI2SSZrm + 0U, // VMOVDI2SSZrr + 0U, // VMOVDI2SSrm + 0U, // VMOVDI2SSrr + 0U, // VMOVDQA32Z128mr + 164U, // VMOVDQA32Z128mrk + 0U, // VMOVDQA32Z128rm + 676U, // VMOVDQA32Z128rmk + 516U, // VMOVDQA32Z128rmkz + 0U, // VMOVDQA32Z128rr + 0U, // VMOVDQA32Z128rr_REV + 292U, // VMOVDQA32Z128rrk + 100U, // VMOVDQA32Z128rrk_REV + 100U, // VMOVDQA32Z128rrkz + 100U, // VMOVDQA32Z128rrkz_REV + 0U, // VMOVDQA32Z256mr + 164U, // VMOVDQA32Z256mrk + 0U, // VMOVDQA32Z256rm + 708U, // VMOVDQA32Z256rmk + 484U, // VMOVDQA32Z256rmkz + 0U, // VMOVDQA32Z256rr + 0U, // VMOVDQA32Z256rr_REV + 292U, // VMOVDQA32Z256rrk + 100U, // VMOVDQA32Z256rrk_REV + 100U, // VMOVDQA32Z256rrkz + 100U, // VMOVDQA32Z256rrkz_REV + 0U, // VMOVDQA32Zmr + 164U, // VMOVDQA32Zmrk + 0U, // VMOVDQA32Zrm + 996U, // VMOVDQA32Zrmk + 548U, // VMOVDQA32Zrmkz + 0U, // VMOVDQA32Zrr + 0U, // VMOVDQA32Zrr_REV + 292U, // VMOVDQA32Zrrk + 100U, // VMOVDQA32Zrrk_REV + 100U, // VMOVDQA32Zrrkz + 100U, // VMOVDQA32Zrrkz_REV + 0U, // VMOVDQA64Z128mr + 164U, // VMOVDQA64Z128mrk + 0U, // VMOVDQA64Z128rm + 676U, // VMOVDQA64Z128rmk + 516U, // VMOVDQA64Z128rmkz + 0U, // VMOVDQA64Z128rr + 0U, // VMOVDQA64Z128rr_REV + 292U, // VMOVDQA64Z128rrk + 100U, // VMOVDQA64Z128rrk_REV + 100U, // VMOVDQA64Z128rrkz + 100U, // VMOVDQA64Z128rrkz_REV + 0U, // VMOVDQA64Z256mr + 164U, // VMOVDQA64Z256mrk + 0U, // VMOVDQA64Z256rm + 708U, // VMOVDQA64Z256rmk + 484U, // VMOVDQA64Z256rmkz + 0U, // VMOVDQA64Z256rr + 0U, // VMOVDQA64Z256rr_REV + 292U, // VMOVDQA64Z256rrk + 100U, // VMOVDQA64Z256rrk_REV + 100U, // VMOVDQA64Z256rrkz + 100U, // VMOVDQA64Z256rrkz_REV + 0U, // VMOVDQA64Zmr + 164U, // VMOVDQA64Zmrk + 0U, // VMOVDQA64Zrm + 996U, // VMOVDQA64Zrmk + 548U, // VMOVDQA64Zrmkz + 0U, // VMOVDQA64Zrr + 0U, // VMOVDQA64Zrr_REV + 292U, // VMOVDQA64Zrrk + 100U, // VMOVDQA64Zrrk_REV + 100U, // VMOVDQA64Zrrkz + 100U, // VMOVDQA64Zrrkz_REV + 0U, // VMOVDQAYmr + 0U, // VMOVDQAYrm + 0U, // VMOVDQAYrr + 0U, // VMOVDQAYrr_REV + 0U, // VMOVDQAmr + 0U, // VMOVDQArm + 0U, // VMOVDQArr + 0U, // VMOVDQArr_REV + 0U, // VMOVDQU16Z128mr + 164U, // VMOVDQU16Z128mrk + 0U, // VMOVDQU16Z128rm + 676U, // VMOVDQU16Z128rmk + 516U, // VMOVDQU16Z128rmkz + 0U, // VMOVDQU16Z128rr + 0U, // VMOVDQU16Z128rr_REV + 292U, // VMOVDQU16Z128rrk + 100U, // VMOVDQU16Z128rrk_REV + 100U, // VMOVDQU16Z128rrkz + 100U, // VMOVDQU16Z128rrkz_REV + 0U, // VMOVDQU16Z256mr + 164U, // VMOVDQU16Z256mrk + 0U, // VMOVDQU16Z256rm + 708U, // VMOVDQU16Z256rmk + 484U, // VMOVDQU16Z256rmkz + 0U, // VMOVDQU16Z256rr + 0U, // VMOVDQU16Z256rr_REV + 292U, // VMOVDQU16Z256rrk + 100U, // VMOVDQU16Z256rrk_REV + 100U, // VMOVDQU16Z256rrkz + 100U, // VMOVDQU16Z256rrkz_REV + 0U, // VMOVDQU16Zmr + 164U, // VMOVDQU16Zmrk + 0U, // VMOVDQU16Zrm + 996U, // VMOVDQU16Zrmk + 548U, // VMOVDQU16Zrmkz + 0U, // VMOVDQU16Zrr + 0U, // VMOVDQU16Zrr_REV + 292U, // VMOVDQU16Zrrk + 100U, // VMOVDQU16Zrrk_REV + 100U, // VMOVDQU16Zrrkz + 100U, // VMOVDQU16Zrrkz_REV + 0U, // VMOVDQU32Z128mr + 164U, // VMOVDQU32Z128mrk + 0U, // VMOVDQU32Z128rm + 676U, // VMOVDQU32Z128rmk + 516U, // VMOVDQU32Z128rmkz + 0U, // VMOVDQU32Z128rr + 0U, // VMOVDQU32Z128rr_REV + 292U, // VMOVDQU32Z128rrk + 100U, // VMOVDQU32Z128rrk_REV + 100U, // VMOVDQU32Z128rrkz + 100U, // VMOVDQU32Z128rrkz_REV + 0U, // VMOVDQU32Z256mr + 164U, // VMOVDQU32Z256mrk + 0U, // VMOVDQU32Z256rm + 708U, // VMOVDQU32Z256rmk + 484U, // VMOVDQU32Z256rmkz + 0U, // VMOVDQU32Z256rr + 0U, // VMOVDQU32Z256rr_REV + 292U, // VMOVDQU32Z256rrk + 100U, // VMOVDQU32Z256rrk_REV + 100U, // VMOVDQU32Z256rrkz + 100U, // VMOVDQU32Z256rrkz_REV + 0U, // VMOVDQU32Zmr + 164U, // VMOVDQU32Zmrk + 0U, // VMOVDQU32Zrm + 996U, // VMOVDQU32Zrmk + 548U, // VMOVDQU32Zrmkz + 0U, // VMOVDQU32Zrr + 0U, // VMOVDQU32Zrr_REV + 292U, // VMOVDQU32Zrrk + 100U, // VMOVDQU32Zrrk_REV + 100U, // VMOVDQU32Zrrkz + 100U, // VMOVDQU32Zrrkz_REV + 0U, // VMOVDQU64Z128mr + 164U, // VMOVDQU64Z128mrk + 0U, // VMOVDQU64Z128rm + 676U, // VMOVDQU64Z128rmk + 516U, // VMOVDQU64Z128rmkz + 0U, // VMOVDQU64Z128rr + 0U, // VMOVDQU64Z128rr_REV + 292U, // VMOVDQU64Z128rrk + 100U, // VMOVDQU64Z128rrk_REV + 100U, // VMOVDQU64Z128rrkz + 100U, // VMOVDQU64Z128rrkz_REV + 0U, // VMOVDQU64Z256mr + 164U, // VMOVDQU64Z256mrk + 0U, // VMOVDQU64Z256rm + 708U, // VMOVDQU64Z256rmk + 484U, // VMOVDQU64Z256rmkz + 0U, // VMOVDQU64Z256rr + 0U, // VMOVDQU64Z256rr_REV + 292U, // VMOVDQU64Z256rrk + 100U, // VMOVDQU64Z256rrk_REV + 100U, // VMOVDQU64Z256rrkz + 100U, // VMOVDQU64Z256rrkz_REV + 0U, // VMOVDQU64Zmr + 164U, // VMOVDQU64Zmrk + 0U, // VMOVDQU64Zrm + 996U, // VMOVDQU64Zrmk + 548U, // VMOVDQU64Zrmkz + 0U, // VMOVDQU64Zrr + 0U, // VMOVDQU64Zrr_REV + 292U, // VMOVDQU64Zrrk + 100U, // VMOVDQU64Zrrk_REV + 100U, // VMOVDQU64Zrrkz + 100U, // VMOVDQU64Zrrkz_REV + 0U, // VMOVDQU8Z128mr + 164U, // VMOVDQU8Z128mrk + 0U, // VMOVDQU8Z128rm + 676U, // VMOVDQU8Z128rmk + 516U, // VMOVDQU8Z128rmkz + 0U, // VMOVDQU8Z128rr + 0U, // VMOVDQU8Z128rr_REV + 292U, // VMOVDQU8Z128rrk + 100U, // VMOVDQU8Z128rrk_REV + 100U, // VMOVDQU8Z128rrkz + 100U, // VMOVDQU8Z128rrkz_REV + 0U, // VMOVDQU8Z256mr + 164U, // VMOVDQU8Z256mrk + 0U, // VMOVDQU8Z256rm + 708U, // VMOVDQU8Z256rmk + 484U, // VMOVDQU8Z256rmkz + 0U, // VMOVDQU8Z256rr + 0U, // VMOVDQU8Z256rr_REV + 292U, // VMOVDQU8Z256rrk + 100U, // VMOVDQU8Z256rrk_REV + 100U, // VMOVDQU8Z256rrkz + 100U, // VMOVDQU8Z256rrkz_REV + 0U, // VMOVDQU8Zmr + 164U, // VMOVDQU8Zmrk + 0U, // VMOVDQU8Zrm + 996U, // VMOVDQU8Zrmk + 548U, // VMOVDQU8Zrmkz + 0U, // VMOVDQU8Zrr + 0U, // VMOVDQU8Zrr_REV + 292U, // VMOVDQU8Zrrk + 100U, // VMOVDQU8Zrrk_REV + 100U, // VMOVDQU8Zrrkz + 100U, // VMOVDQU8Zrrkz_REV + 0U, // VMOVDQUYmr + 0U, // VMOVDQUYrm + 0U, // VMOVDQUYrr + 0U, // VMOVDQUYrr_REV + 0U, // VMOVDQUmr + 0U, // VMOVDQUrm + 0U, // VMOVDQUrr + 0U, // VMOVDQUrr_REV + 96U, // VMOVHLPSZrr + 96U, // VMOVHLPSrr + 0U, // VMOVHPDZ128mr + 384U, // VMOVHPDZ128rm + 0U, // VMOVHPDmr + 384U, // VMOVHPDrm + 0U, // VMOVHPSZ128mr + 384U, // VMOVHPSZ128rm + 0U, // VMOVHPSmr + 384U, // VMOVHPSrm + 96U, // VMOVLHPSZrr + 96U, // VMOVLHPSrr + 0U, // VMOVLPDZ128mr + 384U, // VMOVLPDZ128rm + 0U, // VMOVLPDmr + 384U, // VMOVLPDrm + 0U, // VMOVLPSZ128mr + 384U, // VMOVLPSZ128rm + 0U, // VMOVLPSmr + 384U, // VMOVLPSrm + 0U, // VMOVMSKPDYrr + 0U, // VMOVMSKPDrr + 0U, // VMOVMSKPSYrr + 0U, // VMOVMSKPSrr + 0U, // VMOVNTDQAYrm + 0U, // VMOVNTDQAZ128rm + 0U, // VMOVNTDQAZ256rm + 0U, // VMOVNTDQAZrm + 0U, // VMOVNTDQArm + 0U, // VMOVNTDQYmr + 0U, // VMOVNTDQZ128mr + 0U, // VMOVNTDQZ256mr + 0U, // VMOVNTDQZmr + 0U, // VMOVNTDQmr + 0U, // VMOVNTPDYmr + 0U, // VMOVNTPDZ128mr + 0U, // VMOVNTPDZ256mr + 0U, // VMOVNTPDZmr + 0U, // VMOVNTPDmr + 0U, // VMOVNTPSYmr + 0U, // VMOVNTPSZ128mr + 0U, // VMOVNTPSZ256mr + 0U, // VMOVNTPSZmr + 0U, // VMOVNTPSmr + 0U, // VMOVPDI2DIZmr + 0U, // VMOVPDI2DIZrr + 0U, // VMOVPDI2DImr + 0U, // VMOVPDI2DIrr + 0U, // VMOVPQI2QIZmr + 0U, // VMOVPQI2QIZrr + 0U, // VMOVPQI2QImr + 0U, // VMOVPQI2QIrr + 0U, // VMOVPQIto64Zmr + 0U, // VMOVPQIto64Zrr + 0U, // VMOVPQIto64mr + 0U, // VMOVPQIto64rr + 0U, // VMOVQI2PQIZrm + 0U, // VMOVQI2PQIrm + 0U, // VMOVSDZmr + 164U, // VMOVSDZmrk + 0U, // VMOVSDZrm + 580U, // VMOVSDZrmk + 388U, // VMOVSDZrmkz + 96U, // VMOVSDZrr + 96U, // VMOVSDZrr_REV + 166180U, // VMOVSDZrrk + 166180U, // VMOVSDZrrk_REV + 198756U, // VMOVSDZrrkz + 198756U, // VMOVSDZrrkz_REV + 0U, // VMOVSDmr + 0U, // VMOVSDrm + 96U, // VMOVSDrr + 96U, // VMOVSDrr_REV + 0U, // VMOVSDto64Zmr + 0U, // VMOVSDto64Zrr + 0U, // VMOVSDto64mr + 0U, // VMOVSDto64rr + 0U, // VMOVSHDUPYrm + 0U, // VMOVSHDUPYrr + 0U, // VMOVSHDUPZ128rm + 260U, // VMOVSHDUPZ128rmk + 356U, // VMOVSHDUPZ128rmkz + 0U, // VMOVSHDUPZ128rr + 292U, // VMOVSHDUPZ128rrk + 100U, // VMOVSHDUPZ128rrkz + 0U, // VMOVSHDUPZ256rm + 612U, // VMOVSHDUPZ256rmk + 324U, // VMOVSHDUPZ256rmkz + 0U, // VMOVSHDUPZ256rr + 292U, // VMOVSHDUPZ256rrk + 100U, // VMOVSHDUPZ256rrkz + 0U, // VMOVSHDUPZrm + 1060U, // VMOVSHDUPZrmk + 420U, // VMOVSHDUPZrmkz + 0U, // VMOVSHDUPZrr + 292U, // VMOVSHDUPZrrk + 100U, // VMOVSHDUPZrrkz + 0U, // VMOVSHDUPrm + 0U, // VMOVSHDUPrr + 0U, // VMOVSLDUPYrm + 0U, // VMOVSLDUPYrr + 0U, // VMOVSLDUPZ128rm + 260U, // VMOVSLDUPZ128rmk + 356U, // VMOVSLDUPZ128rmkz + 0U, // VMOVSLDUPZ128rr + 292U, // VMOVSLDUPZ128rrk + 100U, // VMOVSLDUPZ128rrkz + 0U, // VMOVSLDUPZ256rm + 612U, // VMOVSLDUPZ256rmk + 324U, // VMOVSLDUPZ256rmkz + 0U, // VMOVSLDUPZ256rr + 292U, // VMOVSLDUPZ256rrk + 100U, // VMOVSLDUPZ256rrkz + 0U, // VMOVSLDUPZrm + 1060U, // VMOVSLDUPZrmk + 420U, // VMOVSLDUPZrmkz + 0U, // VMOVSLDUPZrr + 292U, // VMOVSLDUPZrrk + 100U, // VMOVSLDUPZrrkz + 0U, // VMOVSLDUPrm + 0U, // VMOVSLDUPrr + 0U, // VMOVSS2DIZmr + 0U, // VMOVSS2DIZrr + 0U, // VMOVSS2DImr + 0U, // VMOVSS2DIrr + 0U, // VMOVSSZmr + 164U, // VMOVSSZmrk + 0U, // VMOVSSZrm + 740U, // VMOVSSZrmk + 452U, // VMOVSSZrmkz + 96U, // VMOVSSZrr + 96U, // VMOVSSZrr_REV + 166180U, // VMOVSSZrrk + 166180U, // VMOVSSZrrk_REV + 198756U, // VMOVSSZrrkz + 198756U, // VMOVSSZrrkz_REV + 0U, // VMOVSSmr + 0U, // VMOVSSrm + 96U, // VMOVSSrr + 96U, // VMOVSSrr_REV + 0U, // VMOVUPDYmr + 0U, // VMOVUPDYrm + 0U, // VMOVUPDYrr + 0U, // VMOVUPDYrr_REV + 0U, // VMOVUPDZ128mr + 164U, // VMOVUPDZ128mrk + 0U, // VMOVUPDZ128rm + 260U, // VMOVUPDZ128rmk + 356U, // VMOVUPDZ128rmkz + 0U, // VMOVUPDZ128rr + 0U, // VMOVUPDZ128rr_REV + 292U, // VMOVUPDZ128rrk + 100U, // VMOVUPDZ128rrk_REV + 100U, // VMOVUPDZ128rrkz + 100U, // VMOVUPDZ128rrkz_REV + 0U, // VMOVUPDZ256mr + 164U, // VMOVUPDZ256mrk + 0U, // VMOVUPDZ256rm + 612U, // VMOVUPDZ256rmk + 324U, // VMOVUPDZ256rmkz + 0U, // VMOVUPDZ256rr + 0U, // VMOVUPDZ256rr_REV + 292U, // VMOVUPDZ256rrk + 100U, // VMOVUPDZ256rrk_REV + 100U, // VMOVUPDZ256rrkz + 100U, // VMOVUPDZ256rrkz_REV + 0U, // VMOVUPDZmr + 164U, // VMOVUPDZmrk + 0U, // VMOVUPDZrm + 1060U, // VMOVUPDZrmk + 420U, // VMOVUPDZrmkz + 0U, // VMOVUPDZrr + 0U, // VMOVUPDZrr_REV + 292U, // VMOVUPDZrrk + 100U, // VMOVUPDZrrk_REV + 100U, // VMOVUPDZrrkz + 100U, // VMOVUPDZrrkz_REV + 0U, // VMOVUPDmr + 0U, // VMOVUPDrm + 0U, // VMOVUPDrr + 0U, // VMOVUPDrr_REV + 0U, // VMOVUPSYmr + 0U, // VMOVUPSYrm + 0U, // VMOVUPSYrr + 0U, // VMOVUPSYrr_REV + 0U, // VMOVUPSZ128mr + 164U, // VMOVUPSZ128mrk + 0U, // VMOVUPSZ128rm + 260U, // VMOVUPSZ128rmk + 356U, // VMOVUPSZ128rmkz + 0U, // VMOVUPSZ128rr + 0U, // VMOVUPSZ128rr_REV + 292U, // VMOVUPSZ128rrk + 100U, // VMOVUPSZ128rrk_REV + 100U, // VMOVUPSZ128rrkz + 100U, // VMOVUPSZ128rrkz_REV + 0U, // VMOVUPSZ256mr + 164U, // VMOVUPSZ256mrk + 0U, // VMOVUPSZ256rm + 612U, // VMOVUPSZ256rmk + 324U, // VMOVUPSZ256rmkz + 0U, // VMOVUPSZ256rr + 0U, // VMOVUPSZ256rr_REV + 292U, // VMOVUPSZ256rrk + 100U, // VMOVUPSZ256rrk_REV + 100U, // VMOVUPSZ256rrkz + 100U, // VMOVUPSZ256rrkz_REV + 0U, // VMOVUPSZmr + 164U, // VMOVUPSZmrk + 0U, // VMOVUPSZrm + 1060U, // VMOVUPSZrmk + 420U, // VMOVUPSZrmkz + 0U, // VMOVUPSZrr + 0U, // VMOVUPSZrr_REV + 292U, // VMOVUPSZrrk + 100U, // VMOVUPSZrrk_REV + 100U, // VMOVUPSZrrkz + 100U, // VMOVUPSZrrkz_REV + 0U, // VMOVUPSmr + 0U, // VMOVUPSrm + 0U, // VMOVUPSrr + 0U, // VMOVUPSrr_REV + 0U, // VMOVZPQILo2PQIZrr + 0U, // VMOVZPQILo2PQIrr + 461280U, // VMPSADBWYrmi + 624736U, // VMPSADBWYrri + 461312U, // VMPSADBWrmi + 624736U, // VMPSADBWrri + 0U, // VMPTRLDm + 0U, // VMPTRSTm + 0U, // VMREAD32mr + 0U, // VMREAD32rr + 0U, // VMREAD64mr + 0U, // VMREAD64rr + 0U, // VMRESUME + 0U, // VMRUN32 + 0U, // VMRUN64 + 0U, // VMSAVE32 + 0U, // VMSAVE64 + 320U, // VMULPDYrm + 96U, // VMULPDYrr + 352U, // VMULPDZ128rm + 4480U, // VMULPDZ128rmb + 1116452U, // VMULPDZ128rmbk + 1149028U, // VMULPDZ128rmbkz + 35108U, // VMULPDZ128rmk + 133220U, // VMULPDZ128rmkz + 96U, // VMULPDZ128rr + 166180U, // VMULPDZ128rrk + 198756U, // VMULPDZ128rrkz + 320U, // VMULPDZ256rm + 6528U, // VMULPDZ256rmb + 2165028U, // VMULPDZ256rmbk + 2197604U, // VMULPDZ256rmbkz + 231716U, // VMULPDZ256rmk + 264292U, // VMULPDZ256rmkz + 96U, // VMULPDZ256rr + 166180U, // VMULPDZ256rrk + 198756U, // VMULPDZ256rrkz + 416U, // VMULPDZrm + 8576U, // VMULPDZrmb + 3213604U, // VMULPDZrmbk + 3246180U, // VMULPDZrmbkz + 297252U, // VMULPDZrmk + 329828U, // VMULPDZrmkz + 96U, // VMULPDZrr + 362592U, // VMULPDZrrb + 4360484U, // VMULPDZrrbk + 21170276U, // VMULPDZrrbkz + 166180U, // VMULPDZrrk + 198756U, // VMULPDZrrkz + 352U, // VMULPDrm + 96U, // VMULPDrr + 320U, // VMULPSYrm + 96U, // VMULPSYrr + 352U, // VMULPSZ128rm + 6592U, // VMULPSZ128rmb + 2492708U, // VMULPSZ128rmbk + 2525284U, // VMULPSZ128rmbkz + 35108U, // VMULPSZ128rmk + 133220U, // VMULPSZ128rmkz + 96U, // VMULPSZ128rr + 166180U, // VMULPSZ128rrk + 198756U, // VMULPSZ128rrkz + 320U, // VMULPSZ256rm + 8640U, // VMULPSZ256rmb + 3541284U, // VMULPSZ256rmbk + 3573860U, // VMULPSZ256rmbkz + 231716U, // VMULPSZ256rmk + 264292U, // VMULPSZ256rmkz + 96U, // VMULPSZ256rr + 166180U, // VMULPSZ256rrk + 198756U, // VMULPSZ256rrkz + 416U, // VMULPSZrm + 10688U, // VMULPSZrmb + 5638436U, // VMULPSZrmbk + 5671012U, // VMULPSZrmbkz + 297252U, // VMULPSZrmk + 329828U, // VMULPSZrmkz + 96U, // VMULPSZrr + 362592U, // VMULPSZrrb + 4360484U, // VMULPSZrrbk + 21170276U, // VMULPSZrrbkz + 166180U, // VMULPSZrrk + 198756U, // VMULPSZrrkz + 352U, // VMULPSrm + 96U, // VMULPSrr + 384U, // VMULSDZrm + 384U, // VMULSDZrm_Int + 67876U, // VMULSDZrm_Intk + 100452U, // VMULSDZrm_Intkz + 96U, // VMULSDZrr + 96U, // VMULSDZrr_Int + 166180U, // VMULSDZrr_Intk + 198756U, // VMULSDZrr_Intkz + 362592U, // VMULSDZrrb_Int + 4360484U, // VMULSDZrrb_Intk + 21170276U, // VMULSDZrrb_Intkz + 384U, // VMULSDrm + 384U, // VMULSDrm_Int + 96U, // VMULSDrr + 96U, // VMULSDrr_Int + 448U, // VMULSSZrm + 448U, // VMULSSZrm_Int + 395556U, // VMULSSZrm_Intk + 428132U, // VMULSSZrm_Intkz + 96U, // VMULSSZrr + 96U, // VMULSSZrr_Int + 166180U, // VMULSSZrr_Intk + 198756U, // VMULSSZrr_Intkz + 362592U, // VMULSSZrrb_Int + 4360484U, // VMULSSZrrb_Intk + 21170276U, // VMULSSZrrb_Intkz + 448U, // VMULSSrm + 448U, // VMULSSrm_Int + 96U, // VMULSSrr + 96U, // VMULSSrr_Int + 0U, // VMWRITE32rm + 0U, // VMWRITE32rr + 0U, // VMWRITE64rm + 0U, // VMWRITE64rr + 0U, // VMXOFF + 0U, // VMXON + 320U, // VORPDYrm + 96U, // VORPDYrr + 352U, // VORPDZ128rm + 4480U, // VORPDZ128rmb + 1116452U, // VORPDZ128rmbk + 1149028U, // VORPDZ128rmbkz + 35108U, // VORPDZ128rmk + 133220U, // VORPDZ128rmkz + 96U, // VORPDZ128rr + 166180U, // VORPDZ128rrk + 198756U, // VORPDZ128rrkz + 320U, // VORPDZ256rm + 6528U, // VORPDZ256rmb + 2165028U, // VORPDZ256rmbk + 2197604U, // VORPDZ256rmbkz + 231716U, // VORPDZ256rmk + 264292U, // VORPDZ256rmkz + 96U, // VORPDZ256rr + 166180U, // VORPDZ256rrk + 198756U, // VORPDZ256rrkz + 416U, // VORPDZrm + 8576U, // VORPDZrmb + 3213604U, // VORPDZrmbk + 3246180U, // VORPDZrmbkz + 297252U, // VORPDZrmk + 329828U, // VORPDZrmkz + 96U, // VORPDZrr + 166180U, // VORPDZrrk + 198756U, // VORPDZrrkz + 352U, // VORPDrm + 96U, // VORPDrr + 320U, // VORPSYrm + 96U, // VORPSYrr + 352U, // VORPSZ128rm + 6592U, // VORPSZ128rmb + 2492708U, // VORPSZ128rmbk + 2525284U, // VORPSZ128rmbkz + 35108U, // VORPSZ128rmk + 133220U, // VORPSZ128rmkz + 96U, // VORPSZ128rr + 166180U, // VORPSZ128rrk + 198756U, // VORPSZ128rrkz + 320U, // VORPSZ256rm + 8640U, // VORPSZ256rmb + 3541284U, // VORPSZ256rmbk + 3573860U, // VORPSZ256rmbkz + 231716U, // VORPSZ256rmk + 264292U, // VORPSZ256rmkz + 96U, // VORPSZ256rr + 166180U, // VORPSZ256rrk + 198756U, // VORPSZ256rrkz + 416U, // VORPSZrm + 10688U, // VORPSZrmb + 5638436U, // VORPSZrmbk + 5671012U, // VORPSZrmbkz + 297252U, // VORPSZrmk + 329828U, // VORPSZrmkz + 96U, // VORPSZrr + 166180U, // VORPSZrrk + 198756U, // VORPSZrrkz + 352U, // VORPSrm + 96U, // VORPSrr + 256U, // VP4DPWSSDSrm + 35108U, // VP4DPWSSDSrmk + 35108U, // VP4DPWSSDSrmkz + 256U, // VP4DPWSSDrm + 35108U, // VP4DPWSSDrmk + 35108U, // VP4DPWSSDrmkz + 0U, // VPABSBYrm + 0U, // VPABSBYrr + 0U, // VPABSBZ128rm + 676U, // VPABSBZ128rmk + 516U, // VPABSBZ128rmkz + 0U, // VPABSBZ128rr + 292U, // VPABSBZ128rrk + 100U, // VPABSBZ128rrkz + 0U, // VPABSBZ256rm + 708U, // VPABSBZ256rmk + 484U, // VPABSBZ256rmkz + 0U, // VPABSBZ256rr + 292U, // VPABSBZ256rrk + 100U, // VPABSBZ256rrkz + 0U, // VPABSBZrm + 996U, // VPABSBZrmk + 548U, // VPABSBZrmkz + 0U, // VPABSBZrr + 292U, // VPABSBZrrk + 100U, // VPABSBZrrkz + 0U, // VPABSBrm + 0U, // VPABSBrr + 0U, // VPABSDYrm + 0U, // VPABSDYrr + 0U, // VPABSDZ128rm + 9U, // VPABSDZ128rmb + 7108U, // VPABSDZ128rmbk + 6212U, // VPABSDZ128rmbkz + 676U, // VPABSDZ128rmk + 516U, // VPABSDZ128rmkz + 0U, // VPABSDZ128rr + 292U, // VPABSDZ128rrk + 100U, // VPABSDZ128rrkz + 0U, // VPABSDZ256rm + 10U, // VPABSDZ256rmb + 9156U, // VPABSDZ256rmbk + 8260U, // VPABSDZ256rmbkz + 708U, // VPABSDZ256rmk + 484U, // VPABSDZ256rmkz + 0U, // VPABSDZ256rr + 292U, // VPABSDZ256rrk + 100U, // VPABSDZ256rrkz + 0U, // VPABSDZrm + 10U, // VPABSDZrmb + 11204U, // VPABSDZrmbk + 10308U, // VPABSDZrmbkz + 996U, // VPABSDZrmk + 548U, // VPABSDZrmkz + 0U, // VPABSDZrr + 292U, // VPABSDZrrk + 100U, // VPABSDZrrkz + 0U, // VPABSDrm + 0U, // VPABSDrr + 0U, // VPABSQZ128rm + 9U, // VPABSQZ128rmb + 4740U, // VPABSQZ128rmbk + 4228U, // VPABSQZ128rmbkz + 676U, // VPABSQZ128rmk + 516U, // VPABSQZ128rmkz + 0U, // VPABSQZ128rr + 292U, // VPABSQZ128rrk + 100U, // VPABSQZ128rrkz + 0U, // VPABSQZ256rm + 9U, // VPABSQZ256rmb + 6788U, // VPABSQZ256rmbk + 6276U, // VPABSQZ256rmbkz + 708U, // VPABSQZ256rmk + 484U, // VPABSQZ256rmkz + 0U, // VPABSQZ256rr + 292U, // VPABSQZ256rrk + 100U, // VPABSQZ256rrkz + 0U, // VPABSQZrm + 10U, // VPABSQZrmb + 8836U, // VPABSQZrmbk + 8324U, // VPABSQZrmbkz + 996U, // VPABSQZrmk + 548U, // VPABSQZrmkz + 0U, // VPABSQZrr + 292U, // VPABSQZrrk + 100U, // VPABSQZrrkz + 0U, // VPABSWYrm + 0U, // VPABSWYrr + 0U, // VPABSWZ128rm + 676U, // VPABSWZ128rmk + 516U, // VPABSWZ128rmkz + 0U, // VPABSWZ128rr + 292U, // VPABSWZ128rrk + 100U, // VPABSWZ128rrkz + 0U, // VPABSWZ256rm + 708U, // VPABSWZ256rmk + 484U, // VPABSWZ256rmkz + 0U, // VPABSWZ256rr + 292U, // VPABSWZ256rrk + 100U, // VPABSWZ256rrkz + 0U, // VPABSWZrm + 996U, // VPABSWZrmk + 548U, // VPABSWZrmkz + 0U, // VPABSWZrr + 292U, // VPABSWZrrk + 100U, // VPABSWZrrkz + 0U, // VPABSWrm + 0U, // VPABSWrr + 480U, // VPACKSSDWYrm + 96U, // VPACKSSDWYrr + 512U, // VPACKSSDWZ128rm + 6208U, // VPACKSSDWZ128rmb + 2591012U, // VPACKSSDWZ128rmbk + 2623588U, // VPACKSSDWZ128rmbkz + 559396U, // VPACKSSDWZ128rmk + 591972U, // VPACKSSDWZ128rmkz + 96U, // VPACKSSDWZ128rr + 166180U, // VPACKSSDWZ128rrk + 198756U, // VPACKSSDWZ128rrkz + 480U, // VPACKSSDWZ256rm + 8256U, // VPACKSSDWZ256rmb + 3639588U, // VPACKSSDWZ256rmbk + 3672164U, // VPACKSSDWZ256rmbkz + 657700U, // VPACKSSDWZ256rmk + 690276U, // VPACKSSDWZ256rmkz + 96U, // VPACKSSDWZ256rr + 166180U, // VPACKSSDWZ256rrk + 198756U, // VPACKSSDWZ256rrkz + 544U, // VPACKSSDWZrm + 10304U, // VPACKSSDWZrmb + 5736740U, // VPACKSSDWZrmbk + 5769316U, // VPACKSSDWZrmbkz + 723236U, // VPACKSSDWZrmk + 755812U, // VPACKSSDWZrmkz + 96U, // VPACKSSDWZrr + 166180U, // VPACKSSDWZrrk + 198756U, // VPACKSSDWZrrkz + 512U, // VPACKSSDWrm + 96U, // VPACKSSDWrr + 480U, // VPACKSSWBYrm + 96U, // VPACKSSWBYrr + 512U, // VPACKSSWBZ128rm + 559396U, // VPACKSSWBZ128rmk + 591972U, // VPACKSSWBZ128rmkz + 96U, // VPACKSSWBZ128rr + 166180U, // VPACKSSWBZ128rrk + 198756U, // VPACKSSWBZ128rrkz + 480U, // VPACKSSWBZ256rm + 657700U, // VPACKSSWBZ256rmk + 690276U, // VPACKSSWBZ256rmkz + 96U, // VPACKSSWBZ256rr + 166180U, // VPACKSSWBZ256rrk + 198756U, // VPACKSSWBZ256rrkz + 544U, // VPACKSSWBZrm + 723236U, // VPACKSSWBZrmk + 755812U, // VPACKSSWBZrmkz + 96U, // VPACKSSWBZrr + 166180U, // VPACKSSWBZrrk + 198756U, // VPACKSSWBZrrkz + 512U, // VPACKSSWBrm + 96U, // VPACKSSWBrr + 480U, // VPACKUSDWYrm + 96U, // VPACKUSDWYrr + 512U, // VPACKUSDWZ128rm + 6208U, // VPACKUSDWZ128rmb + 2591012U, // VPACKUSDWZ128rmbk + 2623588U, // VPACKUSDWZ128rmbkz + 559396U, // VPACKUSDWZ128rmk + 591972U, // VPACKUSDWZ128rmkz + 96U, // VPACKUSDWZ128rr + 166180U, // VPACKUSDWZ128rrk + 198756U, // VPACKUSDWZ128rrkz + 480U, // VPACKUSDWZ256rm + 8256U, // VPACKUSDWZ256rmb + 3639588U, // VPACKUSDWZ256rmbk + 3672164U, // VPACKUSDWZ256rmbkz + 657700U, // VPACKUSDWZ256rmk + 690276U, // VPACKUSDWZ256rmkz + 96U, // VPACKUSDWZ256rr + 166180U, // VPACKUSDWZ256rrk + 198756U, // VPACKUSDWZ256rrkz + 544U, // VPACKUSDWZrm + 10304U, // VPACKUSDWZrmb + 5736740U, // VPACKUSDWZrmbk + 5769316U, // VPACKUSDWZrmbkz + 723236U, // VPACKUSDWZrmk + 755812U, // VPACKUSDWZrmkz + 96U, // VPACKUSDWZrr + 166180U, // VPACKUSDWZrrk + 198756U, // VPACKUSDWZrrkz + 512U, // VPACKUSDWrm + 96U, // VPACKUSDWrr + 480U, // VPACKUSWBYrm + 96U, // VPACKUSWBYrr + 512U, // VPACKUSWBZ128rm + 559396U, // VPACKUSWBZ128rmk + 591972U, // VPACKUSWBZ128rmkz + 96U, // VPACKUSWBZ128rr + 166180U, // VPACKUSWBZ128rrk + 198756U, // VPACKUSWBZ128rrkz + 480U, // VPACKUSWBZ256rm + 657700U, // VPACKUSWBZ256rmk + 690276U, // VPACKUSWBZ256rmkz + 96U, // VPACKUSWBZ256rr + 166180U, // VPACKUSWBZ256rrk + 198756U, // VPACKUSWBZ256rrkz + 544U, // VPACKUSWBZrm + 723236U, // VPACKUSWBZrmk + 755812U, // VPACKUSWBZrmkz + 96U, // VPACKUSWBZrr + 166180U, // VPACKUSWBZrrk + 198756U, // VPACKUSWBZrrkz + 512U, // VPACKUSWBrm + 96U, // VPACKUSWBrr + 480U, // VPADDBYrm + 96U, // VPADDBYrr + 512U, // VPADDBZ128rm + 559396U, // VPADDBZ128rmk + 591972U, // VPADDBZ128rmkz + 96U, // VPADDBZ128rr + 166180U, // VPADDBZ128rrk + 198756U, // VPADDBZ128rrkz + 480U, // VPADDBZ256rm + 657700U, // VPADDBZ256rmk + 690276U, // VPADDBZ256rmkz + 96U, // VPADDBZ256rr + 166180U, // VPADDBZ256rrk + 198756U, // VPADDBZ256rrkz + 544U, // VPADDBZrm + 723236U, // VPADDBZrmk + 755812U, // VPADDBZrmkz + 96U, // VPADDBZrr + 166180U, // VPADDBZrrk + 198756U, // VPADDBZrrkz + 512U, // VPADDBrm + 96U, // VPADDBrr + 480U, // VPADDDYrm + 96U, // VPADDDYrr + 512U, // VPADDDZ128rm + 6208U, // VPADDDZ128rmb + 2591012U, // VPADDDZ128rmbk + 2623588U, // VPADDDZ128rmbkz + 559396U, // VPADDDZ128rmk + 591972U, // VPADDDZ128rmkz + 96U, // VPADDDZ128rr + 166180U, // VPADDDZ128rrk + 198756U, // VPADDDZ128rrkz + 480U, // VPADDDZ256rm + 8256U, // VPADDDZ256rmb + 3639588U, // VPADDDZ256rmbk + 3672164U, // VPADDDZ256rmbkz + 657700U, // VPADDDZ256rmk + 690276U, // VPADDDZ256rmkz + 96U, // VPADDDZ256rr + 166180U, // VPADDDZ256rrk + 198756U, // VPADDDZ256rrkz + 544U, // VPADDDZrm + 10304U, // VPADDDZrmb + 5736740U, // VPADDDZrmbk + 5769316U, // VPADDDZrmbkz + 723236U, // VPADDDZrmk + 755812U, // VPADDDZrmkz + 96U, // VPADDDZrr + 166180U, // VPADDDZrrk + 198756U, // VPADDDZrrkz + 512U, // VPADDDrm + 96U, // VPADDDrr + 480U, // VPADDQYrm + 96U, // VPADDQYrr + 512U, // VPADDQZ128rm + 4224U, // VPADDQZ128rmb + 1837348U, // VPADDQZ128rmbk + 1869924U, // VPADDQZ128rmbkz + 559396U, // VPADDQZ128rmk + 591972U, // VPADDQZ128rmkz + 96U, // VPADDQZ128rr + 166180U, // VPADDQZ128rrk + 198756U, // VPADDQZ128rrkz + 480U, // VPADDQZ256rm + 6272U, // VPADDQZ256rmb + 2885924U, // VPADDQZ256rmbk + 2918500U, // VPADDQZ256rmbkz + 657700U, // VPADDQZ256rmk + 690276U, // VPADDQZ256rmkz + 96U, // VPADDQZ256rr + 166180U, // VPADDQZ256rrk + 198756U, // VPADDQZ256rrkz + 544U, // VPADDQZrm + 8320U, // VPADDQZrmb + 3934500U, // VPADDQZrmbk + 3967076U, // VPADDQZrmbkz + 723236U, // VPADDQZrmk + 755812U, // VPADDQZrmkz + 96U, // VPADDQZrr + 166180U, // VPADDQZrrk + 198756U, // VPADDQZrrkz + 512U, // VPADDQrm + 96U, // VPADDQrr + 480U, // VPADDSBYrm + 96U, // VPADDSBYrr + 512U, // VPADDSBZ128rm + 559396U, // VPADDSBZ128rmk + 591972U, // VPADDSBZ128rmkz + 96U, // VPADDSBZ128rr + 166180U, // VPADDSBZ128rrk + 198756U, // VPADDSBZ128rrkz + 480U, // VPADDSBZ256rm + 657700U, // VPADDSBZ256rmk + 690276U, // VPADDSBZ256rmkz + 96U, // VPADDSBZ256rr + 166180U, // VPADDSBZ256rrk + 198756U, // VPADDSBZ256rrkz + 544U, // VPADDSBZrm + 723236U, // VPADDSBZrmk + 755812U, // VPADDSBZrmkz + 96U, // VPADDSBZrr + 166180U, // VPADDSBZrrk + 198756U, // VPADDSBZrrkz + 512U, // VPADDSBrm + 96U, // VPADDSBrr + 480U, // VPADDSWYrm + 96U, // VPADDSWYrr + 512U, // VPADDSWZ128rm + 559396U, // VPADDSWZ128rmk + 591972U, // VPADDSWZ128rmkz + 96U, // VPADDSWZ128rr + 166180U, // VPADDSWZ128rrk + 198756U, // VPADDSWZ128rrkz + 480U, // VPADDSWZ256rm + 657700U, // VPADDSWZ256rmk + 690276U, // VPADDSWZ256rmkz + 96U, // VPADDSWZ256rr + 166180U, // VPADDSWZ256rrk + 198756U, // VPADDSWZ256rrkz + 544U, // VPADDSWZrm + 723236U, // VPADDSWZrmk + 755812U, // VPADDSWZrmkz + 96U, // VPADDSWZrr + 166180U, // VPADDSWZrrk + 198756U, // VPADDSWZrrkz + 512U, // VPADDSWrm + 96U, // VPADDSWrr + 480U, // VPADDUSBYrm + 96U, // VPADDUSBYrr + 512U, // VPADDUSBZ128rm + 559396U, // VPADDUSBZ128rmk + 591972U, // VPADDUSBZ128rmkz + 96U, // VPADDUSBZ128rr + 166180U, // VPADDUSBZ128rrk + 198756U, // VPADDUSBZ128rrkz + 480U, // VPADDUSBZ256rm + 657700U, // VPADDUSBZ256rmk + 690276U, // VPADDUSBZ256rmkz + 96U, // VPADDUSBZ256rr + 166180U, // VPADDUSBZ256rrk + 198756U, // VPADDUSBZ256rrkz + 544U, // VPADDUSBZrm + 723236U, // VPADDUSBZrmk + 755812U, // VPADDUSBZrmkz + 96U, // VPADDUSBZrr + 166180U, // VPADDUSBZrrk + 198756U, // VPADDUSBZrrkz + 512U, // VPADDUSBrm + 96U, // VPADDUSBrr + 480U, // VPADDUSWYrm + 96U, // VPADDUSWYrr + 512U, // VPADDUSWZ128rm + 559396U, // VPADDUSWZ128rmk + 591972U, // VPADDUSWZ128rmkz + 96U, // VPADDUSWZ128rr + 166180U, // VPADDUSWZ128rrk + 198756U, // VPADDUSWZ128rrkz + 480U, // VPADDUSWZ256rm + 657700U, // VPADDUSWZ256rmk + 690276U, // VPADDUSWZ256rmkz + 96U, // VPADDUSWZ256rr + 166180U, // VPADDUSWZ256rrk + 198756U, // VPADDUSWZ256rrkz + 544U, // VPADDUSWZrm + 723236U, // VPADDUSWZrmk + 755812U, // VPADDUSWZrmkz + 96U, // VPADDUSWZrr + 166180U, // VPADDUSWZrrk + 198756U, // VPADDUSWZrrkz + 512U, // VPADDUSWrm + 96U, // VPADDUSWrr + 480U, // VPADDWYrm + 96U, // VPADDWYrr + 512U, // VPADDWZ128rm + 559396U, // VPADDWZ128rmk + 591972U, // VPADDWZ128rmkz + 96U, // VPADDWZ128rr + 166180U, // VPADDWZ128rrk + 198756U, // VPADDWZ128rrkz + 480U, // VPADDWZ256rm + 657700U, // VPADDWZ256rmk + 690276U, // VPADDWZ256rmkz + 96U, // VPADDWZ256rr + 166180U, // VPADDWZ256rrk + 198756U, // VPADDWZ256rrkz + 544U, // VPADDWZrm + 723236U, // VPADDWZrmk + 755812U, // VPADDWZrmkz + 96U, // VPADDWZrr + 166180U, // VPADDWZrrk + 198756U, // VPADDWZrrkz + 512U, // VPADDWrm + 96U, // VPADDWrr + 461280U, // VPALIGNRYrmi + 624736U, // VPALIGNRYrri + 461312U, // VPALIGNRZ128rmi + 38308132U, // VPALIGNRZ128rmik + 55117924U, // VPALIGNRZ128rmikz + 624736U, // VPALIGNRZ128rri + 71469348U, // VPALIGNRZ128rrik + 88279140U, // VPALIGNRZ128rrikz + 461280U, // VPALIGNRZ256rmi + 38406436U, // VPALIGNRZ256rmik + 55216228U, // VPALIGNRZ256rmikz + 624736U, // VPALIGNRZ256rri + 71469348U, // VPALIGNRZ256rrik + 88279140U, // VPALIGNRZ256rrikz + 461344U, // VPALIGNRZrmi + 38471972U, // VPALIGNRZrmik + 55281764U, // VPALIGNRZrmikz + 624736U, // VPALIGNRZrri + 71469348U, // VPALIGNRZrrik + 88279140U, // VPALIGNRZrrikz + 461312U, // VPALIGNRrmi + 624736U, // VPALIGNRrri + 512U, // VPANDDZ128rm + 6208U, // VPANDDZ128rmb + 2591012U, // VPANDDZ128rmbk + 2623588U, // VPANDDZ128rmbkz + 559396U, // VPANDDZ128rmk + 591972U, // VPANDDZ128rmkz + 96U, // VPANDDZ128rr + 166180U, // VPANDDZ128rrk + 198756U, // VPANDDZ128rrkz + 480U, // VPANDDZ256rm + 8256U, // VPANDDZ256rmb + 3639588U, // VPANDDZ256rmbk + 3672164U, // VPANDDZ256rmbkz + 657700U, // VPANDDZ256rmk + 690276U, // VPANDDZ256rmkz + 96U, // VPANDDZ256rr + 166180U, // VPANDDZ256rrk + 198756U, // VPANDDZ256rrkz + 544U, // VPANDDZrm + 10304U, // VPANDDZrmb + 5736740U, // VPANDDZrmbk + 5769316U, // VPANDDZrmbkz + 723236U, // VPANDDZrmk + 755812U, // VPANDDZrmkz + 96U, // VPANDDZrr + 166180U, // VPANDDZrrk + 198756U, // VPANDDZrrkz + 512U, // VPANDNDZ128rm + 6208U, // VPANDNDZ128rmb + 2591012U, // VPANDNDZ128rmbk + 2623588U, // VPANDNDZ128rmbkz + 559396U, // VPANDNDZ128rmk + 591972U, // VPANDNDZ128rmkz + 96U, // VPANDNDZ128rr + 166180U, // VPANDNDZ128rrk + 198756U, // VPANDNDZ128rrkz + 480U, // VPANDNDZ256rm + 8256U, // VPANDNDZ256rmb + 3639588U, // VPANDNDZ256rmbk + 3672164U, // VPANDNDZ256rmbkz + 657700U, // VPANDNDZ256rmk + 690276U, // VPANDNDZ256rmkz + 96U, // VPANDNDZ256rr + 166180U, // VPANDNDZ256rrk + 198756U, // VPANDNDZ256rrkz + 544U, // VPANDNDZrm + 10304U, // VPANDNDZrmb + 5736740U, // VPANDNDZrmbk + 5769316U, // VPANDNDZrmbkz + 723236U, // VPANDNDZrmk + 755812U, // VPANDNDZrmkz + 96U, // VPANDNDZrr + 166180U, // VPANDNDZrrk + 198756U, // VPANDNDZrrkz + 512U, // VPANDNQZ128rm + 4224U, // VPANDNQZ128rmb + 1837348U, // VPANDNQZ128rmbk + 1869924U, // VPANDNQZ128rmbkz + 559396U, // VPANDNQZ128rmk + 591972U, // VPANDNQZ128rmkz + 96U, // VPANDNQZ128rr + 166180U, // VPANDNQZ128rrk + 198756U, // VPANDNQZ128rrkz + 480U, // VPANDNQZ256rm + 6272U, // VPANDNQZ256rmb + 2885924U, // VPANDNQZ256rmbk + 2918500U, // VPANDNQZ256rmbkz + 657700U, // VPANDNQZ256rmk + 690276U, // VPANDNQZ256rmkz + 96U, // VPANDNQZ256rr + 166180U, // VPANDNQZ256rrk + 198756U, // VPANDNQZ256rrkz + 544U, // VPANDNQZrm + 8320U, // VPANDNQZrmb + 3934500U, // VPANDNQZrmbk + 3967076U, // VPANDNQZrmbkz + 723236U, // VPANDNQZrmk + 755812U, // VPANDNQZrmkz + 96U, // VPANDNQZrr + 166180U, // VPANDNQZrrk + 198756U, // VPANDNQZrrkz + 480U, // VPANDNYrm + 96U, // VPANDNYrr + 512U, // VPANDNrm + 96U, // VPANDNrr + 512U, // VPANDQZ128rm + 4224U, // VPANDQZ128rmb + 1837348U, // VPANDQZ128rmbk + 1869924U, // VPANDQZ128rmbkz + 559396U, // VPANDQZ128rmk + 591972U, // VPANDQZ128rmkz + 96U, // VPANDQZ128rr + 166180U, // VPANDQZ128rrk + 198756U, // VPANDQZ128rrkz + 480U, // VPANDQZ256rm + 6272U, // VPANDQZ256rmb + 2885924U, // VPANDQZ256rmbk + 2918500U, // VPANDQZ256rmbkz + 657700U, // VPANDQZ256rmk + 690276U, // VPANDQZ256rmkz + 96U, // VPANDQZ256rr + 166180U, // VPANDQZ256rrk + 198756U, // VPANDQZ256rrkz + 544U, // VPANDQZrm + 8320U, // VPANDQZrmb + 3934500U, // VPANDQZrmbk + 3967076U, // VPANDQZrmbkz + 723236U, // VPANDQZrmk + 755812U, // VPANDQZrmkz + 96U, // VPANDQZrr + 166180U, // VPANDQZrrk + 198756U, // VPANDQZrrkz + 480U, // VPANDYrm + 96U, // VPANDYrr + 512U, // VPANDrm + 96U, // VPANDrr + 480U, // VPAVGBYrm + 96U, // VPAVGBYrr + 512U, // VPAVGBZ128rm + 559396U, // VPAVGBZ128rmk + 591972U, // VPAVGBZ128rmkz + 96U, // VPAVGBZ128rr + 166180U, // VPAVGBZ128rrk + 198756U, // VPAVGBZ128rrkz + 480U, // VPAVGBZ256rm + 657700U, // VPAVGBZ256rmk + 690276U, // VPAVGBZ256rmkz + 96U, // VPAVGBZ256rr + 166180U, // VPAVGBZ256rrk + 198756U, // VPAVGBZ256rrkz + 544U, // VPAVGBZrm + 723236U, // VPAVGBZrmk + 755812U, // VPAVGBZrmkz + 96U, // VPAVGBZrr + 166180U, // VPAVGBZrrk + 198756U, // VPAVGBZrrkz + 512U, // VPAVGBrm + 96U, // VPAVGBrr + 480U, // VPAVGWYrm + 96U, // VPAVGWYrr + 512U, // VPAVGWZ128rm + 559396U, // VPAVGWZ128rmk + 591972U, // VPAVGWZ128rmkz + 96U, // VPAVGWZ128rr + 166180U, // VPAVGWZ128rrk + 198756U, // VPAVGWZ128rrkz + 480U, // VPAVGWZ256rm + 657700U, // VPAVGWZ256rmk + 690276U, // VPAVGWZ256rmkz + 96U, // VPAVGWZ256rr + 166180U, // VPAVGWZ256rrk + 198756U, // VPAVGWZ256rrkz + 544U, // VPAVGWZrm + 723236U, // VPAVGWZrmk + 755812U, // VPAVGWZrmkz + 96U, // VPAVGWZrr + 166180U, // VPAVGWZrrk + 198756U, // VPAVGWZrrkz + 512U, // VPAVGWrm + 96U, // VPAVGWrr + 461280U, // VPBLENDDYrmi + 624736U, // VPBLENDDYrri + 461312U, // VPBLENDDrmi + 624736U, // VPBLENDDrri + 512U, // VPBLENDMBZ128rm + 591972U, // VPBLENDMBZ128rmk + 591972U, // VPBLENDMBZ128rmkz + 96U, // VPBLENDMBZ128rr + 198756U, // VPBLENDMBZ128rrk + 198756U, // VPBLENDMBZ128rrkz + 480U, // VPBLENDMBZ256rm + 690276U, // VPBLENDMBZ256rmk + 690276U, // VPBLENDMBZ256rmkz + 96U, // VPBLENDMBZ256rr + 198756U, // VPBLENDMBZ256rrk + 198756U, // VPBLENDMBZ256rrkz + 544U, // VPBLENDMBZrm + 755812U, // VPBLENDMBZrmk + 755812U, // VPBLENDMBZrmkz + 96U, // VPBLENDMBZrr + 198756U, // VPBLENDMBZrrk + 198756U, // VPBLENDMBZrrkz + 512U, // VPBLENDMDZ128rm + 6208U, // VPBLENDMDZ128rmb + 2623588U, // VPBLENDMDZ128rmbk + 2623588U, // VPBLENDMDZ128rmbkz + 591972U, // VPBLENDMDZ128rmk + 591972U, // VPBLENDMDZ128rmkz + 96U, // VPBLENDMDZ128rr + 198756U, // VPBLENDMDZ128rrk + 198756U, // VPBLENDMDZ128rrkz + 480U, // VPBLENDMDZ256rm + 8256U, // VPBLENDMDZ256rmb + 3672164U, // VPBLENDMDZ256rmbk + 3672164U, // VPBLENDMDZ256rmbkz + 690276U, // VPBLENDMDZ256rmk + 690276U, // VPBLENDMDZ256rmkz + 96U, // VPBLENDMDZ256rr + 198756U, // VPBLENDMDZ256rrk + 198756U, // VPBLENDMDZ256rrkz + 544U, // VPBLENDMDZrm + 10304U, // VPBLENDMDZrmb + 5769316U, // VPBLENDMDZrmbk + 5769316U, // VPBLENDMDZrmbkz + 755812U, // VPBLENDMDZrmk + 755812U, // VPBLENDMDZrmkz + 96U, // VPBLENDMDZrr + 198756U, // VPBLENDMDZrrk + 198756U, // VPBLENDMDZrrkz + 512U, // VPBLENDMQZ128rm + 4224U, // VPBLENDMQZ128rmb + 1869924U, // VPBLENDMQZ128rmbk + 1869924U, // VPBLENDMQZ128rmbkz + 591972U, // VPBLENDMQZ128rmk + 591972U, // VPBLENDMQZ128rmkz + 96U, // VPBLENDMQZ128rr + 198756U, // VPBLENDMQZ128rrk + 198756U, // VPBLENDMQZ128rrkz + 480U, // VPBLENDMQZ256rm + 6272U, // VPBLENDMQZ256rmb + 2918500U, // VPBLENDMQZ256rmbk + 2918500U, // VPBLENDMQZ256rmbkz + 690276U, // VPBLENDMQZ256rmk + 690276U, // VPBLENDMQZ256rmkz + 96U, // VPBLENDMQZ256rr + 198756U, // VPBLENDMQZ256rrk + 198756U, // VPBLENDMQZ256rrkz + 544U, // VPBLENDMQZrm + 8320U, // VPBLENDMQZrmb + 3967076U, // VPBLENDMQZrmbk + 3967076U, // VPBLENDMQZrmbkz + 755812U, // VPBLENDMQZrmk + 755812U, // VPBLENDMQZrmkz + 96U, // VPBLENDMQZrr + 198756U, // VPBLENDMQZrrk + 198756U, // VPBLENDMQZrrkz + 512U, // VPBLENDMWZ128rm + 591972U, // VPBLENDMWZ128rmk + 591972U, // VPBLENDMWZ128rmkz + 96U, // VPBLENDMWZ128rr + 198756U, // VPBLENDMWZ128rrk + 198756U, // VPBLENDMWZ128rrkz + 480U, // VPBLENDMWZ256rm + 690276U, // VPBLENDMWZ256rmk + 690276U, // VPBLENDMWZ256rmkz + 96U, // VPBLENDMWZ256rr + 198756U, // VPBLENDMWZ256rrk + 198756U, // VPBLENDMWZ256rrkz + 544U, // VPBLENDMWZrm + 755812U, // VPBLENDMWZrmk + 755812U, // VPBLENDMWZrmkz + 96U, // VPBLENDMWZrr + 198756U, // VPBLENDMWZrrk + 198756U, // VPBLENDMWZrrkz + 854496U, // VPBLENDVBYrm + 198752U, // VPBLENDVBYrr + 854528U, // VPBLENDVBrm + 198752U, // VPBLENDVBrr + 461280U, // VPBLENDWYrmi + 624736U, // VPBLENDWYrri + 461312U, // VPBLENDWrmi + 624736U, // VPBLENDWrri + 0U, // VPBROADCASTBYrm + 0U, // VPBROADCASTBYrr + 0U, // VPBROADCASTBZ128m + 1156U, // VPBROADCASTBZ128mk + 1124U, // VPBROADCASTBZ128mkz + 0U, // VPBROADCASTBZ128r + 292U, // VPBROADCASTBZ128rk + 100U, // VPBROADCASTBZ128rkz + 0U, // VPBROADCASTBZ256m + 1156U, // VPBROADCASTBZ256mk + 1124U, // VPBROADCASTBZ256mkz + 0U, // VPBROADCASTBZ256r + 292U, // VPBROADCASTBZ256rk + 100U, // VPBROADCASTBZ256rkz + 0U, // VPBROADCASTBZm + 1156U, // VPBROADCASTBZmk + 1124U, // VPBROADCASTBZmkz + 0U, // VPBROADCASTBZr + 292U, // VPBROADCASTBZrk + 100U, // VPBROADCASTBZrkz + 0U, // VPBROADCASTBrZ128r + 292U, // VPBROADCASTBrZ128rk + 100U, // VPBROADCASTBrZ128rkz + 0U, // VPBROADCASTBrZ256r + 292U, // VPBROADCASTBrZ256rk + 100U, // VPBROADCASTBrZ256rkz + 0U, // VPBROADCASTBrZr + 292U, // VPBROADCASTBrZrk + 100U, // VPBROADCASTBrZrkz + 0U, // VPBROADCASTBrm + 0U, // VPBROADCASTBrr + 0U, // VPBROADCASTDYrm + 0U, // VPBROADCASTDYrr + 0U, // VPBROADCASTDZ128m + 964U, // VPBROADCASTDZ128mk + 68U, // VPBROADCASTDZ128mkz + 0U, // VPBROADCASTDZ128r + 292U, // VPBROADCASTDZ128rk + 100U, // VPBROADCASTDZ128rkz + 0U, // VPBROADCASTDZ256m + 964U, // VPBROADCASTDZ256mk + 68U, // VPBROADCASTDZ256mkz + 0U, // VPBROADCASTDZ256r + 292U, // VPBROADCASTDZ256rk + 100U, // VPBROADCASTDZ256rkz + 0U, // VPBROADCASTDZm + 964U, // VPBROADCASTDZmk + 68U, // VPBROADCASTDZmkz + 0U, // VPBROADCASTDZr + 292U, // VPBROADCASTDZrk + 100U, // VPBROADCASTDZrkz + 0U, // VPBROADCASTDrZ128r + 292U, // VPBROADCASTDrZ128rk + 100U, // VPBROADCASTDrZ128rkz + 0U, // VPBROADCASTDrZ256r + 292U, // VPBROADCASTDrZ256rk + 100U, // VPBROADCASTDrZ256rkz + 0U, // VPBROADCASTDrZr + 292U, // VPBROADCASTDrZrk + 100U, // VPBROADCASTDrZrkz + 0U, // VPBROADCASTDrm + 0U, // VPBROADCASTDrr + 0U, // VPBROADCASTMB2QZ128rr + 0U, // VPBROADCASTMB2QZ256rr + 0U, // VPBROADCASTMB2QZrr + 0U, // VPBROADCASTMW2DZ128rr + 0U, // VPBROADCASTMW2DZ256rr + 0U, // VPBROADCASTMW2DZrr + 0U, // VPBROADCASTQYrm + 0U, // VPBROADCASTQYrr + 0U, // VPBROADCASTQZ128m + 644U, // VPBROADCASTQZ128mk + 132U, // VPBROADCASTQZ128mkz + 0U, // VPBROADCASTQZ128r + 292U, // VPBROADCASTQZ128rk + 100U, // VPBROADCASTQZ128rkz + 0U, // VPBROADCASTQZ256m + 644U, // VPBROADCASTQZ256mk + 132U, // VPBROADCASTQZ256mkz + 0U, // VPBROADCASTQZ256r + 292U, // VPBROADCASTQZ256rk + 100U, // VPBROADCASTQZ256rkz + 0U, // VPBROADCASTQZm + 644U, // VPBROADCASTQZmk + 132U, // VPBROADCASTQZmkz + 0U, // VPBROADCASTQZr + 292U, // VPBROADCASTQZrk + 100U, // VPBROADCASTQZrkz + 0U, // VPBROADCASTQrZ128r + 292U, // VPBROADCASTQrZ128rk + 100U, // VPBROADCASTQrZ128rkz + 0U, // VPBROADCASTQrZ256r + 292U, // VPBROADCASTQrZ256rk + 100U, // VPBROADCASTQrZ256rkz + 0U, // VPBROADCASTQrZr + 292U, // VPBROADCASTQrZrk + 100U, // VPBROADCASTQrZrkz + 0U, // VPBROADCASTQrm + 0U, // VPBROADCASTQrr + 0U, // VPBROADCASTWYrm + 0U, // VPBROADCASTWYrr + 0U, // VPBROADCASTWZ128m + 1188U, // VPBROADCASTWZ128mk + 1220U, // VPBROADCASTWZ128mkz + 0U, // VPBROADCASTWZ128r + 292U, // VPBROADCASTWZ128rk + 100U, // VPBROADCASTWZ128rkz + 0U, // VPBROADCASTWZ256m + 1188U, // VPBROADCASTWZ256mk + 1220U, // VPBROADCASTWZ256mkz + 0U, // VPBROADCASTWZ256r + 292U, // VPBROADCASTWZ256rk + 100U, // VPBROADCASTWZ256rkz + 0U, // VPBROADCASTWZm + 1188U, // VPBROADCASTWZmk + 1220U, // VPBROADCASTWZmkz + 0U, // VPBROADCASTWZr + 292U, // VPBROADCASTWZrk + 100U, // VPBROADCASTWZrkz + 0U, // VPBROADCASTWrZ128r + 292U, // VPBROADCASTWrZ128rk + 100U, // VPBROADCASTWrZ128rkz + 0U, // VPBROADCASTWrZ256r + 292U, // VPBROADCASTWrZ256rk + 100U, // VPBROADCASTWrZ256rkz + 0U, // VPBROADCASTWrZr + 292U, // VPBROADCASTWrZrk + 100U, // VPBROADCASTWrZrkz + 0U, // VPBROADCASTWrm + 0U, // VPBROADCASTWrr + 461280U, // VPCLMULQDQYrm + 624736U, // VPCLMULQDQYrr + 461312U, // VPCLMULQDQZ128rm + 624736U, // VPCLMULQDQZ128rr + 461280U, // VPCLMULQDQZ256rm + 624736U, // VPCLMULQDQZ256rr + 461344U, // VPCLMULQDQZrm + 624736U, // VPCLMULQDQZrr + 461312U, // VPCLMULQDQrm + 624736U, // VPCLMULQDQrr + 854496U, // VPCMOVYrmr + 690272U, // VPCMOVYrrm + 198752U, // VPCMOVYrrr + 198752U, // VPCMOVYrrr_REV + 854528U, // VPCMOVrmr + 591968U, // VPCMOVrrm + 198752U, // VPCMOVrrr + 198752U, // VPCMOVrrr_REV + 517U, // VPCMPBZ128rmi + 461312U, // VPCMPBZ128rmi_alt + 15U, // VPCMPBZ128rmik + 55117924U, // VPCMPBZ128rmik_alt + 101U, // VPCMPBZ128rri + 624736U, // VPCMPBZ128rri_alt + 806U, // VPCMPBZ128rrik + 88279140U, // VPCMPBZ128rrik_alt + 485U, // VPCMPBZ256rmi + 461280U, // VPCMPBZ256rmi_alt + 16U, // VPCMPBZ256rmik + 55216228U, // VPCMPBZ256rmik_alt + 101U, // VPCMPBZ256rri + 624736U, // VPCMPBZ256rri_alt + 806U, // VPCMPBZ256rrik + 88279140U, // VPCMPBZ256rrik_alt + 549U, // VPCMPBZrmi + 461344U, // VPCMPBZrmi_alt + 16U, // VPCMPBZrmik + 55281764U, // VPCMPBZrmik_alt + 101U, // VPCMPBZrri + 624736U, // VPCMPBZrri_alt + 806U, // VPCMPBZrrik + 88279140U, // VPCMPBZrrik_alt + 517U, // VPCMPDZ128rmi + 461312U, // VPCMPDZ128rmi_alt + 6213U, // VPCMPDZ128rmib + 471104U, // VPCMPDZ128rmib_alt + 849U, // VPCMPDZ128rmibk + 57149540U, // VPCMPDZ128rmibk_alt + 15U, // VPCMPDZ128rmik + 55117924U, // VPCMPDZ128rmik_alt + 101U, // VPCMPDZ128rri + 624736U, // VPCMPDZ128rri_alt + 806U, // VPCMPDZ128rrik + 88279140U, // VPCMPDZ128rrik_alt + 485U, // VPCMPDZ256rmi + 461280U, // VPCMPDZ256rmi_alt + 8261U, // VPCMPDZ256rmib + 473152U, // VPCMPDZ256rmib_alt + 881U, // VPCMPDZ256rmibk + 58198116U, // VPCMPDZ256rmibk_alt + 16U, // VPCMPDZ256rmik + 55216228U, // VPCMPDZ256rmik_alt + 101U, // VPCMPDZ256rri + 624736U, // VPCMPDZ256rri_alt + 806U, // VPCMPDZ256rrik + 88279140U, // VPCMPDZ256rrik_alt + 549U, // VPCMPDZrmi + 461344U, // VPCMPDZrmi_alt + 10309U, // VPCMPDZrmib + 475200U, // VPCMPDZrmib_alt + 945U, // VPCMPDZrmibk + 59246692U, // VPCMPDZrmibk_alt + 16U, // VPCMPDZrmik + 55281764U, // VPCMPDZrmik_alt + 101U, // VPCMPDZrri + 624736U, // VPCMPDZrri_alt + 806U, // VPCMPDZrrik + 88279140U, // VPCMPDZrrik_alt + 480U, // VPCMPEQBYrm + 96U, // VPCMPEQBYrr + 512U, // VPCMPEQBZ128rm + 591972U, // VPCMPEQBZ128rmk + 96U, // VPCMPEQBZ128rr + 198756U, // VPCMPEQBZ128rrk + 480U, // VPCMPEQBZ256rm + 690276U, // VPCMPEQBZ256rmk + 96U, // VPCMPEQBZ256rr + 198756U, // VPCMPEQBZ256rrk + 544U, // VPCMPEQBZrm + 755812U, // VPCMPEQBZrmk + 96U, // VPCMPEQBZrr + 198756U, // VPCMPEQBZrrk + 512U, // VPCMPEQBrm + 96U, // VPCMPEQBrr + 480U, // VPCMPEQDYrm + 96U, // VPCMPEQDYrr + 512U, // VPCMPEQDZ128rm + 6208U, // VPCMPEQDZ128rmb + 2623588U, // VPCMPEQDZ128rmbk + 591972U, // VPCMPEQDZ128rmk + 96U, // VPCMPEQDZ128rr + 198756U, // VPCMPEQDZ128rrk + 480U, // VPCMPEQDZ256rm + 8256U, // VPCMPEQDZ256rmb + 3672164U, // VPCMPEQDZ256rmbk + 690276U, // VPCMPEQDZ256rmk + 96U, // VPCMPEQDZ256rr + 198756U, // VPCMPEQDZ256rrk + 544U, // VPCMPEQDZrm + 10304U, // VPCMPEQDZrmb + 5769316U, // VPCMPEQDZrmbk + 755812U, // VPCMPEQDZrmk + 96U, // VPCMPEQDZrr + 198756U, // VPCMPEQDZrrk + 512U, // VPCMPEQDrm + 96U, // VPCMPEQDrr + 480U, // VPCMPEQQYrm + 96U, // VPCMPEQQYrr + 512U, // VPCMPEQQZ128rm + 4224U, // VPCMPEQQZ128rmb + 1869924U, // VPCMPEQQZ128rmbk + 591972U, // VPCMPEQQZ128rmk + 96U, // VPCMPEQQZ128rr + 198756U, // VPCMPEQQZ128rrk + 480U, // VPCMPEQQZ256rm + 6272U, // VPCMPEQQZ256rmb + 2918500U, // VPCMPEQQZ256rmbk + 690276U, // VPCMPEQQZ256rmk + 96U, // VPCMPEQQZ256rr + 198756U, // VPCMPEQQZ256rrk + 544U, // VPCMPEQQZrm + 8320U, // VPCMPEQQZrmb + 3967076U, // VPCMPEQQZrmbk + 755812U, // VPCMPEQQZrmk + 96U, // VPCMPEQQZrr + 198756U, // VPCMPEQQZrrk + 512U, // VPCMPEQQrm + 96U, // VPCMPEQQrr + 480U, // VPCMPEQWYrm + 96U, // VPCMPEQWYrr + 512U, // VPCMPEQWZ128rm + 591972U, // VPCMPEQWZ128rmk + 96U, // VPCMPEQWZ128rr + 198756U, // VPCMPEQWZ128rrk + 480U, // VPCMPEQWZ256rm + 690276U, // VPCMPEQWZ256rmk + 96U, // VPCMPEQWZ256rr + 198756U, // VPCMPEQWZ256rrk + 544U, // VPCMPEQWZrm + 755812U, // VPCMPEQWZrmk + 96U, // VPCMPEQWZrr + 198756U, // VPCMPEQWZrrk + 512U, // VPCMPEQWrm + 96U, // VPCMPEQWrr + 0U, // VPCMPESTRIrm + 32U, // VPCMPESTRIrr + 0U, // VPCMPESTRMrm + 32U, // VPCMPESTRMrr + 480U, // VPCMPGTBYrm + 96U, // VPCMPGTBYrr + 512U, // VPCMPGTBZ128rm + 591972U, // VPCMPGTBZ128rmk + 96U, // VPCMPGTBZ128rr + 198756U, // VPCMPGTBZ128rrk + 480U, // VPCMPGTBZ256rm + 690276U, // VPCMPGTBZ256rmk + 96U, // VPCMPGTBZ256rr + 198756U, // VPCMPGTBZ256rrk + 544U, // VPCMPGTBZrm + 755812U, // VPCMPGTBZrmk + 96U, // VPCMPGTBZrr + 198756U, // VPCMPGTBZrrk + 512U, // VPCMPGTBrm + 96U, // VPCMPGTBrr + 480U, // VPCMPGTDYrm + 96U, // VPCMPGTDYrr + 512U, // VPCMPGTDZ128rm + 6208U, // VPCMPGTDZ128rmb + 2623588U, // VPCMPGTDZ128rmbk + 591972U, // VPCMPGTDZ128rmk + 96U, // VPCMPGTDZ128rr + 198756U, // VPCMPGTDZ128rrk + 480U, // VPCMPGTDZ256rm + 8256U, // VPCMPGTDZ256rmb + 3672164U, // VPCMPGTDZ256rmbk + 690276U, // VPCMPGTDZ256rmk + 96U, // VPCMPGTDZ256rr + 198756U, // VPCMPGTDZ256rrk + 544U, // VPCMPGTDZrm + 10304U, // VPCMPGTDZrmb + 5769316U, // VPCMPGTDZrmbk + 755812U, // VPCMPGTDZrmk + 96U, // VPCMPGTDZrr + 198756U, // VPCMPGTDZrrk + 512U, // VPCMPGTDrm + 96U, // VPCMPGTDrr + 480U, // VPCMPGTQYrm + 96U, // VPCMPGTQYrr + 512U, // VPCMPGTQZ128rm + 4224U, // VPCMPGTQZ128rmb + 1869924U, // VPCMPGTQZ128rmbk + 591972U, // VPCMPGTQZ128rmk + 96U, // VPCMPGTQZ128rr + 198756U, // VPCMPGTQZ128rrk + 480U, // VPCMPGTQZ256rm + 6272U, // VPCMPGTQZ256rmb + 2918500U, // VPCMPGTQZ256rmbk + 690276U, // VPCMPGTQZ256rmk + 96U, // VPCMPGTQZ256rr + 198756U, // VPCMPGTQZ256rrk + 544U, // VPCMPGTQZrm + 8320U, // VPCMPGTQZrmb + 3967076U, // VPCMPGTQZrmbk + 755812U, // VPCMPGTQZrmk + 96U, // VPCMPGTQZrr + 198756U, // VPCMPGTQZrrk + 512U, // VPCMPGTQrm + 96U, // VPCMPGTQrr + 480U, // VPCMPGTWYrm + 96U, // VPCMPGTWYrr + 512U, // VPCMPGTWZ128rm + 591972U, // VPCMPGTWZ128rmk + 96U, // VPCMPGTWZ128rr + 198756U, // VPCMPGTWZ128rrk + 480U, // VPCMPGTWZ256rm + 690276U, // VPCMPGTWZ256rmk + 96U, // VPCMPGTWZ256rr + 198756U, // VPCMPGTWZ256rrk + 544U, // VPCMPGTWZrm + 755812U, // VPCMPGTWZrmk + 96U, // VPCMPGTWZrr + 198756U, // VPCMPGTWZrrk + 512U, // VPCMPGTWrm + 96U, // VPCMPGTWrr + 0U, // VPCMPISTRIrm + 32U, // VPCMPISTRIrr + 0U, // VPCMPISTRMrm + 32U, // VPCMPISTRMrr + 517U, // VPCMPQZ128rmi + 461312U, // VPCMPQZ128rmi_alt + 4229U, // VPCMPQZ128rmib + 477312U, // VPCMPQZ128rmib_alt + 785U, // VPCMPQZ128rmibk + 60590180U, // VPCMPQZ128rmibk_alt + 15U, // VPCMPQZ128rmik + 55117924U, // VPCMPQZ128rmik_alt + 101U, // VPCMPQZ128rri + 624736U, // VPCMPQZ128rri_alt + 806U, // VPCMPQZ128rrik + 88279140U, // VPCMPQZ128rrik_alt + 485U, // VPCMPQZ256rmi + 461280U, // VPCMPQZ256rmi_alt + 6277U, // VPCMPQZ256rmib + 471168U, // VPCMPQZ256rmib_alt + 849U, // VPCMPQZ256rmibk + 57444452U, // VPCMPQZ256rmibk_alt + 16U, // VPCMPQZ256rmik + 55216228U, // VPCMPQZ256rmik_alt + 101U, // VPCMPQZ256rri + 624736U, // VPCMPQZ256rri_alt + 806U, // VPCMPQZ256rrik + 88279140U, // VPCMPQZ256rrik_alt + 549U, // VPCMPQZrmi + 461344U, // VPCMPQZrmi_alt + 8325U, // VPCMPQZrmib + 473216U, // VPCMPQZrmib_alt + 881U, // VPCMPQZrmibk + 58493028U, // VPCMPQZrmibk_alt + 16U, // VPCMPQZrmik + 55281764U, // VPCMPQZrmik_alt + 101U, // VPCMPQZrri + 624736U, // VPCMPQZrri_alt + 806U, // VPCMPQZrrik + 88279140U, // VPCMPQZrrik_alt + 517U, // VPCMPUBZ128rmi + 461312U, // VPCMPUBZ128rmi_alt + 15U, // VPCMPUBZ128rmik + 55117924U, // VPCMPUBZ128rmik_alt + 101U, // VPCMPUBZ128rri + 624736U, // VPCMPUBZ128rri_alt + 806U, // VPCMPUBZ128rrik + 88279140U, // VPCMPUBZ128rrik_alt + 485U, // VPCMPUBZ256rmi + 461280U, // VPCMPUBZ256rmi_alt + 16U, // VPCMPUBZ256rmik + 55216228U, // VPCMPUBZ256rmik_alt + 101U, // VPCMPUBZ256rri + 624736U, // VPCMPUBZ256rri_alt + 806U, // VPCMPUBZ256rrik + 88279140U, // VPCMPUBZ256rrik_alt + 549U, // VPCMPUBZrmi + 461344U, // VPCMPUBZrmi_alt + 16U, // VPCMPUBZrmik + 55281764U, // VPCMPUBZrmik_alt + 101U, // VPCMPUBZrri + 624736U, // VPCMPUBZrri_alt + 806U, // VPCMPUBZrrik + 88279140U, // VPCMPUBZrrik_alt + 517U, // VPCMPUDZ128rmi + 461312U, // VPCMPUDZ128rmi_alt + 6213U, // VPCMPUDZ128rmib + 471104U, // VPCMPUDZ128rmib_alt + 849U, // VPCMPUDZ128rmibk + 57149540U, // VPCMPUDZ128rmibk_alt + 15U, // VPCMPUDZ128rmik + 55117924U, // VPCMPUDZ128rmik_alt + 101U, // VPCMPUDZ128rri + 624736U, // VPCMPUDZ128rri_alt + 806U, // VPCMPUDZ128rrik + 88279140U, // VPCMPUDZ128rrik_alt + 485U, // VPCMPUDZ256rmi + 461280U, // VPCMPUDZ256rmi_alt + 8261U, // VPCMPUDZ256rmib + 473152U, // VPCMPUDZ256rmib_alt + 881U, // VPCMPUDZ256rmibk + 58198116U, // VPCMPUDZ256rmibk_alt + 16U, // VPCMPUDZ256rmik + 55216228U, // VPCMPUDZ256rmik_alt + 101U, // VPCMPUDZ256rri + 624736U, // VPCMPUDZ256rri_alt + 806U, // VPCMPUDZ256rrik + 88279140U, // VPCMPUDZ256rrik_alt + 549U, // VPCMPUDZrmi + 461344U, // VPCMPUDZrmi_alt + 10309U, // VPCMPUDZrmib + 475200U, // VPCMPUDZrmib_alt + 945U, // VPCMPUDZrmibk + 59246692U, // VPCMPUDZrmibk_alt + 16U, // VPCMPUDZrmik + 55281764U, // VPCMPUDZrmik_alt + 101U, // VPCMPUDZrri + 624736U, // VPCMPUDZrri_alt + 806U, // VPCMPUDZrrik + 88279140U, // VPCMPUDZrrik_alt + 517U, // VPCMPUQZ128rmi + 461312U, // VPCMPUQZ128rmi_alt + 4229U, // VPCMPUQZ128rmib + 477312U, // VPCMPUQZ128rmib_alt + 785U, // VPCMPUQZ128rmibk + 60590180U, // VPCMPUQZ128rmibk_alt + 15U, // VPCMPUQZ128rmik + 55117924U, // VPCMPUQZ128rmik_alt + 101U, // VPCMPUQZ128rri + 624736U, // VPCMPUQZ128rri_alt + 806U, // VPCMPUQZ128rrik + 88279140U, // VPCMPUQZ128rrik_alt + 485U, // VPCMPUQZ256rmi + 461280U, // VPCMPUQZ256rmi_alt + 6277U, // VPCMPUQZ256rmib + 471168U, // VPCMPUQZ256rmib_alt + 849U, // VPCMPUQZ256rmibk + 57444452U, // VPCMPUQZ256rmibk_alt + 16U, // VPCMPUQZ256rmik + 55216228U, // VPCMPUQZ256rmik_alt + 101U, // VPCMPUQZ256rri + 624736U, // VPCMPUQZ256rri_alt + 806U, // VPCMPUQZ256rrik + 88279140U, // VPCMPUQZ256rrik_alt + 549U, // VPCMPUQZrmi + 461344U, // VPCMPUQZrmi_alt + 8325U, // VPCMPUQZrmib + 473216U, // VPCMPUQZrmib_alt + 881U, // VPCMPUQZrmibk + 58493028U, // VPCMPUQZrmibk_alt + 16U, // VPCMPUQZrmik + 55281764U, // VPCMPUQZrmik_alt + 101U, // VPCMPUQZrri + 624736U, // VPCMPUQZrri_alt + 806U, // VPCMPUQZrrik + 88279140U, // VPCMPUQZrrik_alt + 517U, // VPCMPUWZ128rmi + 461312U, // VPCMPUWZ128rmi_alt + 15U, // VPCMPUWZ128rmik + 55117924U, // VPCMPUWZ128rmik_alt + 101U, // VPCMPUWZ128rri + 624736U, // VPCMPUWZ128rri_alt + 806U, // VPCMPUWZ128rrik + 88279140U, // VPCMPUWZ128rrik_alt + 485U, // VPCMPUWZ256rmi + 461280U, // VPCMPUWZ256rmi_alt + 16U, // VPCMPUWZ256rmik + 55216228U, // VPCMPUWZ256rmik_alt + 101U, // VPCMPUWZ256rri + 624736U, // VPCMPUWZ256rri_alt + 806U, // VPCMPUWZ256rrik + 88279140U, // VPCMPUWZ256rrik_alt + 549U, // VPCMPUWZrmi + 461344U, // VPCMPUWZrmi_alt + 16U, // VPCMPUWZrmik + 55281764U, // VPCMPUWZrmik_alt + 101U, // VPCMPUWZrri + 624736U, // VPCMPUWZrri_alt + 806U, // VPCMPUWZrrik + 88279140U, // VPCMPUWZrrik_alt + 517U, // VPCMPWZ128rmi + 461312U, // VPCMPWZ128rmi_alt + 15U, // VPCMPWZ128rmik + 55117924U, // VPCMPWZ128rmik_alt + 101U, // VPCMPWZ128rri + 624736U, // VPCMPWZ128rri_alt + 806U, // VPCMPWZ128rrik + 88279140U, // VPCMPWZ128rrik_alt + 485U, // VPCMPWZ256rmi + 461280U, // VPCMPWZ256rmi_alt + 16U, // VPCMPWZ256rmik + 55216228U, // VPCMPWZ256rmik_alt + 101U, // VPCMPWZ256rri + 624736U, // VPCMPWZ256rri_alt + 806U, // VPCMPWZ256rrik + 88279140U, // VPCMPWZ256rrik_alt + 549U, // VPCMPWZrmi + 461344U, // VPCMPWZrmi_alt + 16U, // VPCMPWZrmik + 55281764U, // VPCMPWZrmik_alt + 101U, // VPCMPWZrri + 624736U, // VPCMPWZrri_alt + 806U, // VPCMPWZrrik + 88279140U, // VPCMPWZrrik_alt + 517U, // VPCOMBmi + 461312U, // VPCOMBmi_alt + 101U, // VPCOMBri + 624736U, // VPCOMBri_alt + 517U, // VPCOMDmi + 461312U, // VPCOMDmi_alt + 101U, // VPCOMDri + 624736U, // VPCOMDri_alt + 0U, // VPCOMPRESSBZ128mr + 164U, // VPCOMPRESSBZ128mrk + 0U, // VPCOMPRESSBZ128rr + 292U, // VPCOMPRESSBZ128rrk + 100U, // VPCOMPRESSBZ128rrkz + 0U, // VPCOMPRESSBZ256mr + 164U, // VPCOMPRESSBZ256mrk + 0U, // VPCOMPRESSBZ256rr + 292U, // VPCOMPRESSBZ256rrk + 100U, // VPCOMPRESSBZ256rrkz + 0U, // VPCOMPRESSBZmr + 164U, // VPCOMPRESSBZmrk + 0U, // VPCOMPRESSBZrr + 292U, // VPCOMPRESSBZrrk + 100U, // VPCOMPRESSBZrrkz + 0U, // VPCOMPRESSDZ128mr + 164U, // VPCOMPRESSDZ128mrk + 0U, // VPCOMPRESSDZ128rr + 292U, // VPCOMPRESSDZ128rrk + 100U, // VPCOMPRESSDZ128rrkz + 0U, // VPCOMPRESSDZ256mr + 164U, // VPCOMPRESSDZ256mrk + 0U, // VPCOMPRESSDZ256rr + 292U, // VPCOMPRESSDZ256rrk + 100U, // VPCOMPRESSDZ256rrkz + 0U, // VPCOMPRESSDZmr + 164U, // VPCOMPRESSDZmrk + 0U, // VPCOMPRESSDZrr + 292U, // VPCOMPRESSDZrrk + 100U, // VPCOMPRESSDZrrkz + 0U, // VPCOMPRESSQZ128mr + 164U, // VPCOMPRESSQZ128mrk + 0U, // VPCOMPRESSQZ128rr + 292U, // VPCOMPRESSQZ128rrk + 100U, // VPCOMPRESSQZ128rrkz + 0U, // VPCOMPRESSQZ256mr + 164U, // VPCOMPRESSQZ256mrk + 0U, // VPCOMPRESSQZ256rr + 292U, // VPCOMPRESSQZ256rrk + 100U, // VPCOMPRESSQZ256rrkz + 0U, // VPCOMPRESSQZmr + 164U, // VPCOMPRESSQZmrk + 0U, // VPCOMPRESSQZrr + 292U, // VPCOMPRESSQZrrk + 100U, // VPCOMPRESSQZrrkz + 0U, // VPCOMPRESSWZ128mr + 164U, // VPCOMPRESSWZ128mrk + 0U, // VPCOMPRESSWZ128rr + 292U, // VPCOMPRESSWZ128rrk + 100U, // VPCOMPRESSWZ128rrkz + 0U, // VPCOMPRESSWZ256mr + 164U, // VPCOMPRESSWZ256mrk + 0U, // VPCOMPRESSWZ256rr + 292U, // VPCOMPRESSWZ256rrk + 100U, // VPCOMPRESSWZ256rrkz + 0U, // VPCOMPRESSWZmr + 164U, // VPCOMPRESSWZmrk + 0U, // VPCOMPRESSWZrr + 292U, // VPCOMPRESSWZrrk + 100U, // VPCOMPRESSWZrrkz + 517U, // VPCOMQmi + 461312U, // VPCOMQmi_alt + 101U, // VPCOMQri + 624736U, // VPCOMQri_alt + 517U, // VPCOMUBmi + 461312U, // VPCOMUBmi_alt + 101U, // VPCOMUBri + 624736U, // VPCOMUBri_alt + 517U, // VPCOMUDmi + 461312U, // VPCOMUDmi_alt + 101U, // VPCOMUDri + 624736U, // VPCOMUDri_alt + 517U, // VPCOMUQmi + 461312U, // VPCOMUQmi_alt + 101U, // VPCOMUQri + 624736U, // VPCOMUQri_alt + 517U, // VPCOMUWmi + 461312U, // VPCOMUWmi_alt + 101U, // VPCOMUWri + 624736U, // VPCOMUWri_alt + 517U, // VPCOMWmi + 461312U, // VPCOMWmi_alt + 101U, // VPCOMWri + 624736U, // VPCOMWri_alt + 0U, // VPCONFLICTDZ128rm + 9U, // VPCONFLICTDZ128rmb + 7108U, // VPCONFLICTDZ128rmbk + 6212U, // VPCONFLICTDZ128rmbkz + 676U, // VPCONFLICTDZ128rmk + 516U, // VPCONFLICTDZ128rmkz + 0U, // VPCONFLICTDZ128rr + 292U, // VPCONFLICTDZ128rrk + 100U, // VPCONFLICTDZ128rrkz + 0U, // VPCONFLICTDZ256rm + 10U, // VPCONFLICTDZ256rmb + 9156U, // VPCONFLICTDZ256rmbk + 8260U, // VPCONFLICTDZ256rmbkz + 708U, // VPCONFLICTDZ256rmk + 484U, // VPCONFLICTDZ256rmkz + 0U, // VPCONFLICTDZ256rr + 292U, // VPCONFLICTDZ256rrk + 100U, // VPCONFLICTDZ256rrkz + 0U, // VPCONFLICTDZrm + 10U, // VPCONFLICTDZrmb + 11204U, // VPCONFLICTDZrmbk + 10308U, // VPCONFLICTDZrmbkz + 996U, // VPCONFLICTDZrmk + 548U, // VPCONFLICTDZrmkz + 0U, // VPCONFLICTDZrr + 292U, // VPCONFLICTDZrrk + 100U, // VPCONFLICTDZrrkz + 0U, // VPCONFLICTQZ128rm + 9U, // VPCONFLICTQZ128rmb + 4740U, // VPCONFLICTQZ128rmbk + 4228U, // VPCONFLICTQZ128rmbkz + 676U, // VPCONFLICTQZ128rmk + 516U, // VPCONFLICTQZ128rmkz + 0U, // VPCONFLICTQZ128rr + 292U, // VPCONFLICTQZ128rrk + 100U, // VPCONFLICTQZ128rrkz + 0U, // VPCONFLICTQZ256rm + 9U, // VPCONFLICTQZ256rmb + 6788U, // VPCONFLICTQZ256rmbk + 6276U, // VPCONFLICTQZ256rmbkz + 708U, // VPCONFLICTQZ256rmk + 484U, // VPCONFLICTQZ256rmkz + 0U, // VPCONFLICTQZ256rr + 292U, // VPCONFLICTQZ256rrk + 100U, // VPCONFLICTQZ256rrkz + 0U, // VPCONFLICTQZrm + 10U, // VPCONFLICTQZrmb + 8836U, // VPCONFLICTQZrmbk + 8324U, // VPCONFLICTQZrmbkz + 996U, // VPCONFLICTQZrmk + 548U, // VPCONFLICTQZrmkz + 0U, // VPCONFLICTQZrr + 292U, // VPCONFLICTQZrrk + 100U, // VPCONFLICTQZrrkz + 672U, // VPDPBUSDSZ128m + 7104U, // VPDPBUSDSZ128mb + 2591012U, // VPDPBUSDSZ128mbk + 2591012U, // VPDPBUSDSZ128mbkz + 559396U, // VPDPBUSDSZ128mk + 559396U, // VPDPBUSDSZ128mkz + 288U, // VPDPBUSDSZ128r + 166180U, // VPDPBUSDSZ128rk + 166180U, // VPDPBUSDSZ128rkz + 704U, // VPDPBUSDSZ256m + 9152U, // VPDPBUSDSZ256mb + 3639588U, // VPDPBUSDSZ256mbk + 3639588U, // VPDPBUSDSZ256mbkz + 657700U, // VPDPBUSDSZ256mk + 657700U, // VPDPBUSDSZ256mkz + 288U, // VPDPBUSDSZ256r + 166180U, // VPDPBUSDSZ256rk + 166180U, // VPDPBUSDSZ256rkz + 992U, // VPDPBUSDSZm + 11200U, // VPDPBUSDSZmb + 5736740U, // VPDPBUSDSZmbk + 5736740U, // VPDPBUSDSZmbkz + 723236U, // VPDPBUSDSZmk + 723236U, // VPDPBUSDSZmkz + 288U, // VPDPBUSDSZr + 166180U, // VPDPBUSDSZrk + 166180U, // VPDPBUSDSZrkz + 672U, // VPDPBUSDZ128m + 7104U, // VPDPBUSDZ128mb + 2591012U, // VPDPBUSDZ128mbk + 2591012U, // VPDPBUSDZ128mbkz + 559396U, // VPDPBUSDZ128mk + 559396U, // VPDPBUSDZ128mkz + 288U, // VPDPBUSDZ128r + 166180U, // VPDPBUSDZ128rk + 166180U, // VPDPBUSDZ128rkz + 704U, // VPDPBUSDZ256m + 9152U, // VPDPBUSDZ256mb + 3639588U, // VPDPBUSDZ256mbk + 3639588U, // VPDPBUSDZ256mbkz + 657700U, // VPDPBUSDZ256mk + 657700U, // VPDPBUSDZ256mkz + 288U, // VPDPBUSDZ256r + 166180U, // VPDPBUSDZ256rk + 166180U, // VPDPBUSDZ256rkz + 992U, // VPDPBUSDZm + 11200U, // VPDPBUSDZmb + 5736740U, // VPDPBUSDZmbk + 5736740U, // VPDPBUSDZmbkz + 723236U, // VPDPBUSDZmk + 723236U, // VPDPBUSDZmkz + 288U, // VPDPBUSDZr + 166180U, // VPDPBUSDZrk + 166180U, // VPDPBUSDZrkz + 672U, // VPDPWSSDSZ128m + 7104U, // VPDPWSSDSZ128mb + 2591012U, // VPDPWSSDSZ128mbk + 2591012U, // VPDPWSSDSZ128mbkz + 559396U, // VPDPWSSDSZ128mk + 559396U, // VPDPWSSDSZ128mkz + 288U, // VPDPWSSDSZ128r + 166180U, // VPDPWSSDSZ128rk + 166180U, // VPDPWSSDSZ128rkz + 704U, // VPDPWSSDSZ256m + 9152U, // VPDPWSSDSZ256mb + 3639588U, // VPDPWSSDSZ256mbk + 3639588U, // VPDPWSSDSZ256mbkz + 657700U, // VPDPWSSDSZ256mk + 657700U, // VPDPWSSDSZ256mkz + 288U, // VPDPWSSDSZ256r + 166180U, // VPDPWSSDSZ256rk + 166180U, // VPDPWSSDSZ256rkz + 992U, // VPDPWSSDSZm + 11200U, // VPDPWSSDSZmb + 5736740U, // VPDPWSSDSZmbk + 5736740U, // VPDPWSSDSZmbkz + 723236U, // VPDPWSSDSZmk + 723236U, // VPDPWSSDSZmkz + 288U, // VPDPWSSDSZr + 166180U, // VPDPWSSDSZrk + 166180U, // VPDPWSSDSZrkz + 672U, // VPDPWSSDZ128m + 7104U, // VPDPWSSDZ128mb + 2591012U, // VPDPWSSDZ128mbk + 2591012U, // VPDPWSSDZ128mbkz + 559396U, // VPDPWSSDZ128mk + 559396U, // VPDPWSSDZ128mkz + 288U, // VPDPWSSDZ128r + 166180U, // VPDPWSSDZ128rk + 166180U, // VPDPWSSDZ128rkz + 704U, // VPDPWSSDZ256m + 9152U, // VPDPWSSDZ256mb + 3639588U, // VPDPWSSDZ256mbk + 3639588U, // VPDPWSSDZ256mbkz + 657700U, // VPDPWSSDZ256mk + 657700U, // VPDPWSSDZ256mkz + 288U, // VPDPWSSDZ256r + 166180U, // VPDPWSSDZ256rk + 166180U, // VPDPWSSDZ256rkz + 992U, // VPDPWSSDZm + 11200U, // VPDPWSSDZmb + 5736740U, // VPDPWSSDZmbk + 5736740U, // VPDPWSSDZmbkz + 723236U, // VPDPWSSDZmk + 723236U, // VPDPWSSDZmkz + 288U, // VPDPWSSDZr + 166180U, // VPDPWSSDZrk + 166180U, // VPDPWSSDZrkz + 461120U, // VPERM2F128rm + 624736U, // VPERM2F128rr + 461120U, // VPERM2I128rm + 624736U, // VPERM2I128rr + 512U, // VPERMBZ128rm + 559396U, // VPERMBZ128rmk + 591972U, // VPERMBZ128rmkz + 96U, // VPERMBZ128rr + 166180U, // VPERMBZ128rrk + 198756U, // VPERMBZ128rrkz + 480U, // VPERMBZ256rm + 657700U, // VPERMBZ256rmk + 690276U, // VPERMBZ256rmkz + 96U, // VPERMBZ256rr + 166180U, // VPERMBZ256rrk + 198756U, // VPERMBZ256rrkz + 544U, // VPERMBZrm + 723236U, // VPERMBZrmk + 755812U, // VPERMBZrmkz + 96U, // VPERMBZrr + 166180U, // VPERMBZrrk + 198756U, // VPERMBZrrkz + 480U, // VPERMDYrm + 96U, // VPERMDYrr + 480U, // VPERMDZ256rm + 8256U, // VPERMDZ256rmb + 3639588U, // VPERMDZ256rmbk + 3672164U, // VPERMDZ256rmbkz + 657700U, // VPERMDZ256rmk + 690276U, // VPERMDZ256rmkz + 96U, // VPERMDZ256rr + 166180U, // VPERMDZ256rrk + 198756U, // VPERMDZ256rrkz + 544U, // VPERMDZrm + 10304U, // VPERMDZrmb + 5736740U, // VPERMDZrmbk + 5769316U, // VPERMDZrmbkz + 723236U, // VPERMDZrmk + 755812U, // VPERMDZrmkz + 96U, // VPERMDZrr + 166180U, // VPERMDZrrk + 198756U, // VPERMDZrrkz + 672U, // VPERMI2B128rm + 559396U, // VPERMI2B128rmk + 559396U, // VPERMI2B128rmkz + 288U, // VPERMI2B128rr + 166180U, // VPERMI2B128rrk + 166180U, // VPERMI2B128rrkz + 704U, // VPERMI2B256rm + 657700U, // VPERMI2B256rmk + 657700U, // VPERMI2B256rmkz + 288U, // VPERMI2B256rr + 166180U, // VPERMI2B256rrk + 166180U, // VPERMI2B256rrkz + 992U, // VPERMI2Brm + 723236U, // VPERMI2Brmk + 723236U, // VPERMI2Brmkz + 288U, // VPERMI2Brr + 166180U, // VPERMI2Brrk + 166180U, // VPERMI2Brrkz + 672U, // VPERMI2D128rm + 7104U, // VPERMI2D128rmb + 2591012U, // VPERMI2D128rmbk + 2591012U, // VPERMI2D128rmbkz + 559396U, // VPERMI2D128rmk + 559396U, // VPERMI2D128rmkz + 288U, // VPERMI2D128rr + 166180U, // VPERMI2D128rrk + 166180U, // VPERMI2D128rrkz + 704U, // VPERMI2D256rm + 9152U, // VPERMI2D256rmb + 3639588U, // VPERMI2D256rmbk + 3639588U, // VPERMI2D256rmbkz + 657700U, // VPERMI2D256rmk + 657700U, // VPERMI2D256rmkz + 288U, // VPERMI2D256rr + 166180U, // VPERMI2D256rrk + 166180U, // VPERMI2D256rrkz + 992U, // VPERMI2Drm + 11200U, // VPERMI2Drmb + 5736740U, // VPERMI2Drmbk + 5736740U, // VPERMI2Drmbkz + 723236U, // VPERMI2Drmk + 723236U, // VPERMI2Drmkz + 288U, // VPERMI2Drr + 166180U, // VPERMI2Drrk + 166180U, // VPERMI2Drrkz + 256U, // VPERMI2PD128rm + 4672U, // VPERMI2PD128rmb + 1116452U, // VPERMI2PD128rmbk + 1116452U, // VPERMI2PD128rmbkz + 35108U, // VPERMI2PD128rmk + 35108U, // VPERMI2PD128rmkz + 288U, // VPERMI2PD128rr + 166180U, // VPERMI2PD128rrk + 166180U, // VPERMI2PD128rrkz + 608U, // VPERMI2PD256rm + 6720U, // VPERMI2PD256rmb + 2165028U, // VPERMI2PD256rmbk + 2165028U, // VPERMI2PD256rmbkz + 231716U, // VPERMI2PD256rmk + 231716U, // VPERMI2PD256rmkz + 288U, // VPERMI2PD256rr + 166180U, // VPERMI2PD256rrk + 166180U, // VPERMI2PD256rrkz + 1056U, // VPERMI2PDrm + 8768U, // VPERMI2PDrmb + 3213604U, // VPERMI2PDrmbk + 3213604U, // VPERMI2PDrmbkz + 297252U, // VPERMI2PDrmk + 297252U, // VPERMI2PDrmkz + 288U, // VPERMI2PDrr + 166180U, // VPERMI2PDrrk + 166180U, // VPERMI2PDrrkz + 256U, // VPERMI2PS128rm + 6880U, // VPERMI2PS128rmb + 2492708U, // VPERMI2PS128rmbk + 2492708U, // VPERMI2PS128rmbkz + 35108U, // VPERMI2PS128rmk + 35108U, // VPERMI2PS128rmkz + 288U, // VPERMI2PS128rr + 166180U, // VPERMI2PS128rrk + 166180U, // VPERMI2PS128rrkz + 608U, // VPERMI2PS256rm + 8928U, // VPERMI2PS256rmb + 3541284U, // VPERMI2PS256rmbk + 3541284U, // VPERMI2PS256rmbkz + 231716U, // VPERMI2PS256rmk + 231716U, // VPERMI2PS256rmkz + 288U, // VPERMI2PS256rr + 166180U, // VPERMI2PS256rrk + 166180U, // VPERMI2PS256rrkz + 1056U, // VPERMI2PSrm + 10976U, // VPERMI2PSrmb + 5638436U, // VPERMI2PSrmbk + 5638436U, // VPERMI2PSrmbkz + 297252U, // VPERMI2PSrmk + 297252U, // VPERMI2PSrmkz + 288U, // VPERMI2PSrr + 166180U, // VPERMI2PSrrk + 166180U, // VPERMI2PSrrkz + 672U, // VPERMI2Q128rm + 4736U, // VPERMI2Q128rmb + 1837348U, // VPERMI2Q128rmbk + 1837348U, // VPERMI2Q128rmbkz + 559396U, // VPERMI2Q128rmk + 559396U, // VPERMI2Q128rmkz + 288U, // VPERMI2Q128rr + 166180U, // VPERMI2Q128rrk + 166180U, // VPERMI2Q128rrkz + 704U, // VPERMI2Q256rm + 6784U, // VPERMI2Q256rmb + 2885924U, // VPERMI2Q256rmbk + 2885924U, // VPERMI2Q256rmbkz + 657700U, // VPERMI2Q256rmk + 657700U, // VPERMI2Q256rmkz + 288U, // VPERMI2Q256rr + 166180U, // VPERMI2Q256rrk + 166180U, // VPERMI2Q256rrkz + 992U, // VPERMI2Qrm + 8832U, // VPERMI2Qrmb + 3934500U, // VPERMI2Qrmbk + 3934500U, // VPERMI2Qrmbkz + 723236U, // VPERMI2Qrmk + 723236U, // VPERMI2Qrmkz + 288U, // VPERMI2Qrr + 166180U, // VPERMI2Qrrk + 166180U, // VPERMI2Qrrkz + 672U, // VPERMI2W128rm + 559396U, // VPERMI2W128rmk + 559396U, // VPERMI2W128rmkz + 288U, // VPERMI2W128rr + 166180U, // VPERMI2W128rrk + 166180U, // VPERMI2W128rrkz + 704U, // VPERMI2W256rm + 657700U, // VPERMI2W256rmk + 657700U, // VPERMI2W256rmkz + 288U, // VPERMI2W256rr + 166180U, // VPERMI2W256rrk + 166180U, // VPERMI2W256rrkz + 992U, // VPERMI2Wrm + 723236U, // VPERMI2Wrmk + 723236U, // VPERMI2Wrmkz + 288U, // VPERMI2Wrr + 166180U, // VPERMI2Wrrk + 166180U, // VPERMI2Wrrkz + 55380288U, // VPERMIL2PDYmr + 55216224U, // VPERMIL2PDYrm + 88279136U, // VPERMIL2PDYrr + 88279136U, // VPERMIL2PDYrr_REV + 55380320U, // VPERMIL2PDmr + 55117920U, // VPERMIL2PDrm + 88279136U, // VPERMIL2PDrr + 88279136U, // VPERMIL2PDrr_REV + 55380288U, // VPERMIL2PSYmr + 55216224U, // VPERMIL2PSYrm + 88279136U, // VPERMIL2PSYrr + 88279136U, // VPERMIL2PSYrr_REV + 55380320U, // VPERMIL2PSmr + 55117920U, // VPERMIL2PSrm + 88279136U, // VPERMIL2PSrr + 88279136U, // VPERMIL2PSrr_REV + 0U, // VPERMILPDYmi + 32U, // VPERMILPDYri + 480U, // VPERMILPDYrm + 96U, // VPERMILPDYrr + 11U, // VPERMILPDZ128mbi + 936516U, // VPERMILPDZ128mbik + 477572U, // VPERMILPDZ128mbikz + 0U, // VPERMILPDZ128mi + 919812U, // VPERMILPDZ128mik + 461156U, // VPERMILPDZ128mikz + 32U, // VPERMILPDZ128ri + 2340U, // VPERMILPDZ128rik + 624740U, // VPERMILPDZ128rikz + 512U, // VPERMILPDZ128rm + 4480U, // VPERMILPDZ128rmb + 1116452U, // VPERMILPDZ128rmbk + 1149028U, // VPERMILPDZ128rmbkz + 559396U, // VPERMILPDZ128rmk + 591972U, // VPERMILPDZ128rmkz + 96U, // VPERMILPDZ128rr + 166180U, // VPERMILPDZ128rrk + 198756U, // VPERMILPDZ128rrkz + 12U, // VPERMILPDZ256mbi + 930372U, // VPERMILPDZ256mbik + 471428U, // VPERMILPDZ256mbikz + 0U, // VPERMILPDZ256mi + 920164U, // VPERMILPDZ256mik + 461124U, // VPERMILPDZ256mikz + 32U, // VPERMILPDZ256ri + 2340U, // VPERMILPDZ256rik + 624740U, // VPERMILPDZ256rikz + 480U, // VPERMILPDZ256rm + 6528U, // VPERMILPDZ256rmb + 2165028U, // VPERMILPDZ256rmbk + 2197604U, // VPERMILPDZ256rmbkz + 657700U, // VPERMILPDZ256rmk + 690276U, // VPERMILPDZ256rmkz + 96U, // VPERMILPDZ256rr + 166180U, // VPERMILPDZ256rrk + 198756U, // VPERMILPDZ256rrkz + 12U, // VPERMILPDZmbi + 932420U, // VPERMILPDZmbik + 473476U, // VPERMILPDZmbikz + 0U, // VPERMILPDZmi + 920612U, // VPERMILPDZmik + 461220U, // VPERMILPDZmikz + 32U, // VPERMILPDZri + 2340U, // VPERMILPDZrik + 624740U, // VPERMILPDZrikz + 544U, // VPERMILPDZrm + 8576U, // VPERMILPDZrmb + 3213604U, // VPERMILPDZrmbk + 3246180U, // VPERMILPDZrmbkz + 723236U, // VPERMILPDZrmk + 755812U, // VPERMILPDZrmkz + 96U, // VPERMILPDZrr + 166180U, // VPERMILPDZrrk + 198756U, // VPERMILPDZrrkz + 0U, // VPERMILPDmi + 32U, // VPERMILPDri + 512U, // VPERMILPDrm + 96U, // VPERMILPDrr + 0U, // VPERMILPSYmi + 32U, // VPERMILPSYri + 480U, // VPERMILPSYrm + 96U, // VPERMILPSYrr + 12U, // VPERMILPSZ128mbi + 930532U, // VPERMILPSZ128mbik + 471492U, // VPERMILPSZ128mbikz + 0U, // VPERMILPSZ128mi + 919812U, // VPERMILPSZ128mik + 461156U, // VPERMILPSZ128mikz + 32U, // VPERMILPSZ128ri + 2340U, // VPERMILPSZ128rik + 624740U, // VPERMILPSZ128rikz + 512U, // VPERMILPSZ128rm + 6592U, // VPERMILPSZ128rmb + 2492708U, // VPERMILPSZ128rmbk + 2525284U, // VPERMILPSZ128rmbkz + 559396U, // VPERMILPSZ128rmk + 591972U, // VPERMILPSZ128rmkz + 96U, // VPERMILPSZ128rr + 166180U, // VPERMILPSZ128rrk + 198756U, // VPERMILPSZ128rrkz + 12U, // VPERMILPSZ256mbi + 932580U, // VPERMILPSZ256mbik + 473540U, // VPERMILPSZ256mbikz + 0U, // VPERMILPSZ256mi + 920164U, // VPERMILPSZ256mik + 461124U, // VPERMILPSZ256mikz + 32U, // VPERMILPSZ256ri + 2340U, // VPERMILPSZ256rik + 624740U, // VPERMILPSZ256rikz + 480U, // VPERMILPSZ256rm + 8640U, // VPERMILPSZ256rmb + 3541284U, // VPERMILPSZ256rmbk + 3573860U, // VPERMILPSZ256rmbkz + 657700U, // VPERMILPSZ256rmk + 690276U, // VPERMILPSZ256rmkz + 96U, // VPERMILPSZ256rr + 166180U, // VPERMILPSZ256rrk + 198756U, // VPERMILPSZ256rrkz + 13U, // VPERMILPSZmbi + 934628U, // VPERMILPSZmbik + 475588U, // VPERMILPSZmbikz + 0U, // VPERMILPSZmi + 920612U, // VPERMILPSZmik + 461220U, // VPERMILPSZmikz + 32U, // VPERMILPSZri + 2340U, // VPERMILPSZrik + 624740U, // VPERMILPSZrikz + 544U, // VPERMILPSZrm + 10688U, // VPERMILPSZrmb + 5638436U, // VPERMILPSZrmbk + 5671012U, // VPERMILPSZrmbkz + 723236U, // VPERMILPSZrmk + 755812U, // VPERMILPSZrmkz + 96U, // VPERMILPSZrr + 166180U, // VPERMILPSZrrk + 198756U, // VPERMILPSZrrkz + 0U, // VPERMILPSmi + 32U, // VPERMILPSri + 512U, // VPERMILPSrm + 96U, // VPERMILPSrr + 0U, // VPERMPDYmi + 32U, // VPERMPDYri + 12U, // VPERMPDZ256mbi + 930372U, // VPERMPDZ256mbik + 471428U, // VPERMPDZ256mbikz + 0U, // VPERMPDZ256mi + 920164U, // VPERMPDZ256mik + 461124U, // VPERMPDZ256mikz + 32U, // VPERMPDZ256ri + 2340U, // VPERMPDZ256rik + 624740U, // VPERMPDZ256rikz + 320U, // VPERMPDZ256rm + 6528U, // VPERMPDZ256rmb + 2165028U, // VPERMPDZ256rmbk + 2197604U, // VPERMPDZ256rmbkz + 231716U, // VPERMPDZ256rmk + 264292U, // VPERMPDZ256rmkz + 96U, // VPERMPDZ256rr + 166180U, // VPERMPDZ256rrk + 198756U, // VPERMPDZ256rrkz + 12U, // VPERMPDZmbi + 932420U, // VPERMPDZmbik + 473476U, // VPERMPDZmbikz + 0U, // VPERMPDZmi + 920612U, // VPERMPDZmik + 461220U, // VPERMPDZmikz + 32U, // VPERMPDZri + 2340U, // VPERMPDZrik + 624740U, // VPERMPDZrikz + 416U, // VPERMPDZrm + 8576U, // VPERMPDZrmb + 3213604U, // VPERMPDZrmbk + 3246180U, // VPERMPDZrmbkz + 297252U, // VPERMPDZrmk + 329828U, // VPERMPDZrmkz + 96U, // VPERMPDZrr + 166180U, // VPERMPDZrrk + 198756U, // VPERMPDZrrkz + 320U, // VPERMPSYrm + 96U, // VPERMPSYrr + 320U, // VPERMPSZ256rm + 8640U, // VPERMPSZ256rmb + 3541284U, // VPERMPSZ256rmbk + 3573860U, // VPERMPSZ256rmbkz + 231716U, // VPERMPSZ256rmk + 264292U, // VPERMPSZ256rmkz + 96U, // VPERMPSZ256rr + 166180U, // VPERMPSZ256rrk + 198756U, // VPERMPSZ256rrkz + 416U, // VPERMPSZrm + 10688U, // VPERMPSZrmb + 5638436U, // VPERMPSZrmbk + 5671012U, // VPERMPSZrmbkz + 297252U, // VPERMPSZrmk + 329828U, // VPERMPSZrmkz + 96U, // VPERMPSZrr + 166180U, // VPERMPSZrrk + 198756U, // VPERMPSZrrkz + 0U, // VPERMQYmi + 32U, // VPERMQYri + 12U, // VPERMQZ256mbi + 930436U, // VPERMQZ256mbik + 471172U, // VPERMQZ256mbikz + 0U, // VPERMQZ256mi + 920260U, // VPERMQZ256mik + 461284U, // VPERMQZ256mikz + 32U, // VPERMQZ256ri + 2340U, // VPERMQZ256rik + 624740U, // VPERMQZ256rikz + 480U, // VPERMQZ256rm + 6272U, // VPERMQZ256rmb + 2885924U, // VPERMQZ256rmbk + 2918500U, // VPERMQZ256rmbkz + 657700U, // VPERMQZ256rmk + 690276U, // VPERMQZ256rmkz + 96U, // VPERMQZ256rr + 166180U, // VPERMQZ256rrk + 198756U, // VPERMQZ256rrkz + 12U, // VPERMQZmbi + 932484U, // VPERMQZmbik + 473220U, // VPERMQZmbikz + 0U, // VPERMQZmi + 920548U, // VPERMQZmik + 461348U, // VPERMQZmikz + 32U, // VPERMQZri + 2340U, // VPERMQZrik + 624740U, // VPERMQZrikz + 544U, // VPERMQZrm + 8320U, // VPERMQZrmb + 3934500U, // VPERMQZrmbk + 3967076U, // VPERMQZrmbkz + 723236U, // VPERMQZrmk + 755812U, // VPERMQZrmkz + 96U, // VPERMQZrr + 166180U, // VPERMQZrrk + 198756U, // VPERMQZrrkz + 672U, // VPERMT2B128rm + 559396U, // VPERMT2B128rmk + 559396U, // VPERMT2B128rmkz + 288U, // VPERMT2B128rr + 166180U, // VPERMT2B128rrk + 166180U, // VPERMT2B128rrkz + 704U, // VPERMT2B256rm + 657700U, // VPERMT2B256rmk + 657700U, // VPERMT2B256rmkz + 288U, // VPERMT2B256rr + 166180U, // VPERMT2B256rrk + 166180U, // VPERMT2B256rrkz + 992U, // VPERMT2Brm + 723236U, // VPERMT2Brmk + 723236U, // VPERMT2Brmkz + 288U, // VPERMT2Brr + 166180U, // VPERMT2Brrk + 166180U, // VPERMT2Brrkz + 672U, // VPERMT2D128rm + 7104U, // VPERMT2D128rmb + 2591012U, // VPERMT2D128rmbk + 2591012U, // VPERMT2D128rmbkz + 559396U, // VPERMT2D128rmk + 559396U, // VPERMT2D128rmkz + 288U, // VPERMT2D128rr + 166180U, // VPERMT2D128rrk + 166180U, // VPERMT2D128rrkz + 704U, // VPERMT2D256rm + 9152U, // VPERMT2D256rmb + 3639588U, // VPERMT2D256rmbk + 3639588U, // VPERMT2D256rmbkz + 657700U, // VPERMT2D256rmk + 657700U, // VPERMT2D256rmkz + 288U, // VPERMT2D256rr + 166180U, // VPERMT2D256rrk + 166180U, // VPERMT2D256rrkz + 992U, // VPERMT2Drm + 11200U, // VPERMT2Drmb + 5736740U, // VPERMT2Drmbk + 5736740U, // VPERMT2Drmbkz + 723236U, // VPERMT2Drmk + 723236U, // VPERMT2Drmkz + 288U, // VPERMT2Drr + 166180U, // VPERMT2Drrk + 166180U, // VPERMT2Drrkz + 256U, // VPERMT2PD128rm + 4672U, // VPERMT2PD128rmb + 1116452U, // VPERMT2PD128rmbk + 1116452U, // VPERMT2PD128rmbkz + 35108U, // VPERMT2PD128rmk + 35108U, // VPERMT2PD128rmkz + 288U, // VPERMT2PD128rr + 166180U, // VPERMT2PD128rrk + 166180U, // VPERMT2PD128rrkz + 608U, // VPERMT2PD256rm + 6720U, // VPERMT2PD256rmb + 2165028U, // VPERMT2PD256rmbk + 2165028U, // VPERMT2PD256rmbkz + 231716U, // VPERMT2PD256rmk + 231716U, // VPERMT2PD256rmkz + 288U, // VPERMT2PD256rr + 166180U, // VPERMT2PD256rrk + 166180U, // VPERMT2PD256rrkz + 1056U, // VPERMT2PDrm + 8768U, // VPERMT2PDrmb + 3213604U, // VPERMT2PDrmbk + 3213604U, // VPERMT2PDrmbkz + 297252U, // VPERMT2PDrmk + 297252U, // VPERMT2PDrmkz + 288U, // VPERMT2PDrr + 166180U, // VPERMT2PDrrk + 166180U, // VPERMT2PDrrkz + 256U, // VPERMT2PS128rm + 6880U, // VPERMT2PS128rmb + 2492708U, // VPERMT2PS128rmbk + 2492708U, // VPERMT2PS128rmbkz + 35108U, // VPERMT2PS128rmk + 35108U, // VPERMT2PS128rmkz + 288U, // VPERMT2PS128rr + 166180U, // VPERMT2PS128rrk + 166180U, // VPERMT2PS128rrkz + 608U, // VPERMT2PS256rm + 8928U, // VPERMT2PS256rmb + 3541284U, // VPERMT2PS256rmbk + 3541284U, // VPERMT2PS256rmbkz + 231716U, // VPERMT2PS256rmk + 231716U, // VPERMT2PS256rmkz + 288U, // VPERMT2PS256rr + 166180U, // VPERMT2PS256rrk + 166180U, // VPERMT2PS256rrkz + 1056U, // VPERMT2PSrm + 10976U, // VPERMT2PSrmb + 5638436U, // VPERMT2PSrmbk + 5638436U, // VPERMT2PSrmbkz + 297252U, // VPERMT2PSrmk + 297252U, // VPERMT2PSrmkz + 288U, // VPERMT2PSrr + 166180U, // VPERMT2PSrrk + 166180U, // VPERMT2PSrrkz + 672U, // VPERMT2Q128rm + 4736U, // VPERMT2Q128rmb + 1837348U, // VPERMT2Q128rmbk + 1837348U, // VPERMT2Q128rmbkz + 559396U, // VPERMT2Q128rmk + 559396U, // VPERMT2Q128rmkz + 288U, // VPERMT2Q128rr + 166180U, // VPERMT2Q128rrk + 166180U, // VPERMT2Q128rrkz + 704U, // VPERMT2Q256rm + 6784U, // VPERMT2Q256rmb + 2885924U, // VPERMT2Q256rmbk + 2885924U, // VPERMT2Q256rmbkz + 657700U, // VPERMT2Q256rmk + 657700U, // VPERMT2Q256rmkz + 288U, // VPERMT2Q256rr + 166180U, // VPERMT2Q256rrk + 166180U, // VPERMT2Q256rrkz + 992U, // VPERMT2Qrm + 8832U, // VPERMT2Qrmb + 3934500U, // VPERMT2Qrmbk + 3934500U, // VPERMT2Qrmbkz + 723236U, // VPERMT2Qrmk + 723236U, // VPERMT2Qrmkz + 288U, // VPERMT2Qrr + 166180U, // VPERMT2Qrrk + 166180U, // VPERMT2Qrrkz + 672U, // VPERMT2W128rm + 559396U, // VPERMT2W128rmk + 559396U, // VPERMT2W128rmkz + 288U, // VPERMT2W128rr + 166180U, // VPERMT2W128rrk + 166180U, // VPERMT2W128rrkz + 704U, // VPERMT2W256rm + 657700U, // VPERMT2W256rmk + 657700U, // VPERMT2W256rmkz + 288U, // VPERMT2W256rr + 166180U, // VPERMT2W256rrk + 166180U, // VPERMT2W256rrkz + 992U, // VPERMT2Wrm + 723236U, // VPERMT2Wrmk + 723236U, // VPERMT2Wrmkz + 288U, // VPERMT2Wrr + 166180U, // VPERMT2Wrrk + 166180U, // VPERMT2Wrrkz + 512U, // VPERMWZ128rm + 559396U, // VPERMWZ128rmk + 591972U, // VPERMWZ128rmkz + 96U, // VPERMWZ128rr + 166180U, // VPERMWZ128rrk + 198756U, // VPERMWZ128rrkz + 480U, // VPERMWZ256rm + 657700U, // VPERMWZ256rmk + 690276U, // VPERMWZ256rmkz + 96U, // VPERMWZ256rr + 166180U, // VPERMWZ256rrk + 198756U, // VPERMWZ256rrkz + 544U, // VPERMWZrm + 723236U, // VPERMWZrmk + 755812U, // VPERMWZrmkz + 96U, // VPERMWZrr + 166180U, // VPERMWZrrk + 198756U, // VPERMWZrrkz + 0U, // VPEXPANDBZ128rm + 676U, // VPEXPANDBZ128rmk + 516U, // VPEXPANDBZ128rmkz + 0U, // VPEXPANDBZ128rr + 292U, // VPEXPANDBZ128rrk + 100U, // VPEXPANDBZ128rrkz + 0U, // VPEXPANDBZ256rm + 708U, // VPEXPANDBZ256rmk + 484U, // VPEXPANDBZ256rmkz + 0U, // VPEXPANDBZ256rr + 292U, // VPEXPANDBZ256rrk + 100U, // VPEXPANDBZ256rrkz + 0U, // VPEXPANDBZrm + 996U, // VPEXPANDBZrmk + 548U, // VPEXPANDBZrmkz + 0U, // VPEXPANDBZrr + 292U, // VPEXPANDBZrrk + 100U, // VPEXPANDBZrrkz + 0U, // VPEXPANDDZ128rm + 676U, // VPEXPANDDZ128rmk + 516U, // VPEXPANDDZ128rmkz + 0U, // VPEXPANDDZ128rr + 292U, // VPEXPANDDZ128rrk + 100U, // VPEXPANDDZ128rrkz + 0U, // VPEXPANDDZ256rm + 708U, // VPEXPANDDZ256rmk + 484U, // VPEXPANDDZ256rmkz + 0U, // VPEXPANDDZ256rr + 292U, // VPEXPANDDZ256rrk + 100U, // VPEXPANDDZ256rrkz + 0U, // VPEXPANDDZrm + 996U, // VPEXPANDDZrmk + 548U, // VPEXPANDDZrmkz + 0U, // VPEXPANDDZrr + 292U, // VPEXPANDDZrrk + 100U, // VPEXPANDDZrrkz + 0U, // VPEXPANDQZ128rm + 676U, // VPEXPANDQZ128rmk + 516U, // VPEXPANDQZ128rmkz + 0U, // VPEXPANDQZ128rr + 292U, // VPEXPANDQZ128rrk + 100U, // VPEXPANDQZ128rrkz + 0U, // VPEXPANDQZ256rm + 708U, // VPEXPANDQZ256rmk + 484U, // VPEXPANDQZ256rmkz + 0U, // VPEXPANDQZ256rr + 292U, // VPEXPANDQZ256rrk + 100U, // VPEXPANDQZ256rrkz + 0U, // VPEXPANDQZrm + 996U, // VPEXPANDQZrmk + 548U, // VPEXPANDQZrmkz + 0U, // VPEXPANDQZrr + 292U, // VPEXPANDQZrrk + 100U, // VPEXPANDQZrrkz + 0U, // VPEXPANDWZ128rm + 676U, // VPEXPANDWZ128rmk + 516U, // VPEXPANDWZ128rmkz + 0U, // VPEXPANDWZ128rr + 292U, // VPEXPANDWZ128rrk + 100U, // VPEXPANDWZ128rrkz + 0U, // VPEXPANDWZ256rm + 708U, // VPEXPANDWZ256rmk + 484U, // VPEXPANDWZ256rmkz + 0U, // VPEXPANDWZ256rr + 292U, // VPEXPANDWZ256rrk + 100U, // VPEXPANDWZ256rrkz + 0U, // VPEXPANDWZrm + 996U, // VPEXPANDWZrmk + 548U, // VPEXPANDWZrmkz + 0U, // VPEXPANDWZrr + 292U, // VPEXPANDWZrrk + 100U, // VPEXPANDWZrrkz + 0U, // VPEXTRBZmr + 32U, // VPEXTRBZrr + 0U, // VPEXTRBmr + 32U, // VPEXTRBrr + 0U, // VPEXTRDZmr + 32U, // VPEXTRDZrr + 0U, // VPEXTRDmr + 32U, // VPEXTRDrr + 0U, // VPEXTRQZmr + 32U, // VPEXTRQZrr + 0U, // VPEXTRQmr + 32U, // VPEXTRQrr + 0U, // VPEXTRWZmr + 32U, // VPEXTRWZrr + 32U, // VPEXTRWZrr_REV + 0U, // VPEXTRWmr + 32U, // VPEXTRWrr + 32U, // VPEXTRWrr_REV + 0U, // VPGATHERDDYrm + 13U, // VPGATHERDDZ128rm + 14U, // VPGATHERDDZ256rm + 14U, // VPGATHERDDZrm + 0U, // VPGATHERDDrm + 0U, // VPGATHERDQYrm + 13U, // VPGATHERDQZ128rm + 14U, // VPGATHERDQZ256rm + 14U, // VPGATHERDQZrm + 0U, // VPGATHERDQrm + 0U, // VPGATHERQDYrm + 15U, // VPGATHERQDZ128rm + 13U, // VPGATHERQDZ256rm + 14U, // VPGATHERQDZrm + 0U, // VPGATHERQDrm + 0U, // VPGATHERQQYrm + 13U, // VPGATHERQQZ128rm + 14U, // VPGATHERQQZ256rm + 14U, // VPGATHERQQZrm + 0U, // VPGATHERQQrm + 0U, // VPHADDBDrm + 0U, // VPHADDBDrr + 0U, // VPHADDBQrm + 0U, // VPHADDBQrr + 0U, // VPHADDBWrm + 0U, // VPHADDBWrr + 0U, // VPHADDDQrm + 0U, // VPHADDDQrr + 480U, // VPHADDDYrm + 96U, // VPHADDDYrr + 512U, // VPHADDDrm + 96U, // VPHADDDrr + 480U, // VPHADDSWYrm + 96U, // VPHADDSWYrr + 512U, // VPHADDSWrm + 96U, // VPHADDSWrr + 0U, // VPHADDUBDrm + 0U, // VPHADDUBDrr + 0U, // VPHADDUBQrm + 0U, // VPHADDUBQrr + 0U, // VPHADDUBWrm + 0U, // VPHADDUBWrr + 0U, // VPHADDUDQrm + 0U, // VPHADDUDQrr + 0U, // VPHADDUWDrm + 0U, // VPHADDUWDrr + 0U, // VPHADDUWQrm + 0U, // VPHADDUWQrr + 0U, // VPHADDWDrm + 0U, // VPHADDWDrr + 0U, // VPHADDWQrm + 0U, // VPHADDWQrr + 480U, // VPHADDWYrm + 96U, // VPHADDWYrr + 512U, // VPHADDWrm + 96U, // VPHADDWrr + 0U, // VPHMINPOSUWrm + 0U, // VPHMINPOSUWrr + 0U, // VPHSUBBWrm + 0U, // VPHSUBBWrr + 0U, // VPHSUBDQrm + 0U, // VPHSUBDQrr + 480U, // VPHSUBDYrm + 96U, // VPHSUBDYrr + 512U, // VPHSUBDrm + 96U, // VPHSUBDrr + 480U, // VPHSUBSWYrm + 96U, // VPHSUBSWYrr + 512U, // VPHSUBSWrm + 96U, // VPHSUBSWrr + 0U, // VPHSUBWDrm + 0U, // VPHSUBWDrr + 480U, // VPHSUBWYrm + 96U, // VPHSUBWYrr + 512U, // VPHSUBWrm + 96U, // VPHSUBWrr + 461920U, // VPINSRBZrm + 624736U, // VPINSRBZrr + 461920U, // VPINSRBrm + 624736U, // VPINSRBrr + 460864U, // VPINSRDZrm + 624736U, // VPINSRDZrr + 460864U, // VPINSRDrm + 624736U, // VPINSRDrr + 460928U, // VPINSRQZrm + 624736U, // VPINSRQZrr + 460928U, // VPINSRQrm + 624736U, // VPINSRQrr + 462016U, // VPINSRWZrm + 624736U, // VPINSRWZrr + 462016U, // VPINSRWrm + 624736U, // VPINSRWrr + 0U, // VPLZCNTDZ128rm + 9U, // VPLZCNTDZ128rmb + 7108U, // VPLZCNTDZ128rmbk + 6212U, // VPLZCNTDZ128rmbkz + 676U, // VPLZCNTDZ128rmk + 516U, // VPLZCNTDZ128rmkz + 0U, // VPLZCNTDZ128rr + 292U, // VPLZCNTDZ128rrk + 100U, // VPLZCNTDZ128rrkz + 0U, // VPLZCNTDZ256rm + 10U, // VPLZCNTDZ256rmb + 9156U, // VPLZCNTDZ256rmbk + 8260U, // VPLZCNTDZ256rmbkz + 708U, // VPLZCNTDZ256rmk + 484U, // VPLZCNTDZ256rmkz + 0U, // VPLZCNTDZ256rr + 292U, // VPLZCNTDZ256rrk + 100U, // VPLZCNTDZ256rrkz + 0U, // VPLZCNTDZrm + 10U, // VPLZCNTDZrmb + 11204U, // VPLZCNTDZrmbk + 10308U, // VPLZCNTDZrmbkz + 996U, // VPLZCNTDZrmk + 548U, // VPLZCNTDZrmkz + 0U, // VPLZCNTDZrr + 292U, // VPLZCNTDZrrk + 100U, // VPLZCNTDZrrkz + 0U, // VPLZCNTQZ128rm + 9U, // VPLZCNTQZ128rmb + 4740U, // VPLZCNTQZ128rmbk + 4228U, // VPLZCNTQZ128rmbkz + 676U, // VPLZCNTQZ128rmk + 516U, // VPLZCNTQZ128rmkz + 0U, // VPLZCNTQZ128rr + 292U, // VPLZCNTQZ128rrk + 100U, // VPLZCNTQZ128rrkz + 0U, // VPLZCNTQZ256rm + 9U, // VPLZCNTQZ256rmb + 6788U, // VPLZCNTQZ256rmbk + 6276U, // VPLZCNTQZ256rmbkz + 708U, // VPLZCNTQZ256rmk + 484U, // VPLZCNTQZ256rmkz + 0U, // VPLZCNTQZ256rr + 292U, // VPLZCNTQZ256rrk + 100U, // VPLZCNTQZ256rrkz + 0U, // VPLZCNTQZrm + 10U, // VPLZCNTQZrmb + 8836U, // VPLZCNTQZrmbk + 8324U, // VPLZCNTQZrmbkz + 996U, // VPLZCNTQZrmk + 548U, // VPLZCNTQZrmkz + 0U, // VPLZCNTQZrr + 292U, // VPLZCNTQZrrk + 100U, // VPLZCNTQZrrkz + 854528U, // VPMACSDDrm + 198752U, // VPMACSDDrr + 854528U, // VPMACSDQHrm + 198752U, // VPMACSDQHrr + 854528U, // VPMACSDQLrm + 198752U, // VPMACSDQLrr + 854528U, // VPMACSSDDrm + 198752U, // VPMACSSDDrr + 854528U, // VPMACSSDQHrm + 198752U, // VPMACSSDQHrr + 854528U, // VPMACSSDQLrm + 198752U, // VPMACSSDQLrr + 854528U, // VPMACSSWDrm + 198752U, // VPMACSSWDrr + 854528U, // VPMACSSWWrm + 198752U, // VPMACSSWWrr + 854528U, // VPMACSWDrm + 198752U, // VPMACSWDrr + 854528U, // VPMACSWWrm + 198752U, // VPMACSWWrr + 854528U, // VPMADCSSWDrm + 198752U, // VPMADCSSWDrr + 854528U, // VPMADCSWDrm + 198752U, // VPMADCSWDrr + 672U, // VPMADD52HUQZ128m + 4736U, // VPMADD52HUQZ128mb + 1837348U, // VPMADD52HUQZ128mbk + 1837348U, // VPMADD52HUQZ128mbkz + 559396U, // VPMADD52HUQZ128mk + 559396U, // VPMADD52HUQZ128mkz + 288U, // VPMADD52HUQZ128r + 166180U, // VPMADD52HUQZ128rk + 166180U, // VPMADD52HUQZ128rkz + 704U, // VPMADD52HUQZ256m + 6784U, // VPMADD52HUQZ256mb + 2885924U, // VPMADD52HUQZ256mbk + 2885924U, // VPMADD52HUQZ256mbkz + 657700U, // VPMADD52HUQZ256mk + 657700U, // VPMADD52HUQZ256mkz + 288U, // VPMADD52HUQZ256r + 166180U, // VPMADD52HUQZ256rk + 166180U, // VPMADD52HUQZ256rkz + 992U, // VPMADD52HUQZm + 8832U, // VPMADD52HUQZmb + 3934500U, // VPMADD52HUQZmbk + 3934500U, // VPMADD52HUQZmbkz + 723236U, // VPMADD52HUQZmk + 723236U, // VPMADD52HUQZmkz + 288U, // VPMADD52HUQZr + 166180U, // VPMADD52HUQZrk + 166180U, // VPMADD52HUQZrkz + 672U, // VPMADD52LUQZ128m + 4736U, // VPMADD52LUQZ128mb + 1837348U, // VPMADD52LUQZ128mbk + 1837348U, // VPMADD52LUQZ128mbkz + 559396U, // VPMADD52LUQZ128mk + 559396U, // VPMADD52LUQZ128mkz + 288U, // VPMADD52LUQZ128r + 166180U, // VPMADD52LUQZ128rk + 166180U, // VPMADD52LUQZ128rkz + 704U, // VPMADD52LUQZ256m + 6784U, // VPMADD52LUQZ256mb + 2885924U, // VPMADD52LUQZ256mbk + 2885924U, // VPMADD52LUQZ256mbkz + 657700U, // VPMADD52LUQZ256mk + 657700U, // VPMADD52LUQZ256mkz + 288U, // VPMADD52LUQZ256r + 166180U, // VPMADD52LUQZ256rk + 166180U, // VPMADD52LUQZ256rkz + 992U, // VPMADD52LUQZm + 8832U, // VPMADD52LUQZmb + 3934500U, // VPMADD52LUQZmbk + 3934500U, // VPMADD52LUQZmbkz + 723236U, // VPMADD52LUQZmk + 723236U, // VPMADD52LUQZmkz + 288U, // VPMADD52LUQZr + 166180U, // VPMADD52LUQZrk + 166180U, // VPMADD52LUQZrkz + 480U, // VPMADDUBSWYrm + 96U, // VPMADDUBSWYrr + 512U, // VPMADDUBSWZ128rm + 559396U, // VPMADDUBSWZ128rmk + 591972U, // VPMADDUBSWZ128rmkz + 96U, // VPMADDUBSWZ128rr + 166180U, // VPMADDUBSWZ128rrk + 198756U, // VPMADDUBSWZ128rrkz + 480U, // VPMADDUBSWZ256rm + 657700U, // VPMADDUBSWZ256rmk + 690276U, // VPMADDUBSWZ256rmkz + 96U, // VPMADDUBSWZ256rr + 166180U, // VPMADDUBSWZ256rrk + 198756U, // VPMADDUBSWZ256rrkz + 544U, // VPMADDUBSWZrm + 723236U, // VPMADDUBSWZrmk + 755812U, // VPMADDUBSWZrmkz + 96U, // VPMADDUBSWZrr + 166180U, // VPMADDUBSWZrrk + 198756U, // VPMADDUBSWZrrkz + 512U, // VPMADDUBSWrm + 96U, // VPMADDUBSWrr + 480U, // VPMADDWDYrm + 96U, // VPMADDWDYrr + 512U, // VPMADDWDZ128rm + 559396U, // VPMADDWDZ128rmk + 591972U, // VPMADDWDZ128rmkz + 96U, // VPMADDWDZ128rr + 166180U, // VPMADDWDZ128rrk + 198756U, // VPMADDWDZ128rrkz + 480U, // VPMADDWDZ256rm + 657700U, // VPMADDWDZ256rmk + 690276U, // VPMADDWDZ256rmkz + 96U, // VPMADDWDZ256rr + 166180U, // VPMADDWDZ256rrk + 198756U, // VPMADDWDZ256rrkz + 544U, // VPMADDWDZrm + 723236U, // VPMADDWDZrmk + 755812U, // VPMADDWDZrmkz + 96U, // VPMADDWDZrr + 166180U, // VPMADDWDZrrk + 198756U, // VPMADDWDZrrkz + 512U, // VPMADDWDrm + 96U, // VPMADDWDrr + 160U, // VPMASKMOVDYmr + 480U, // VPMASKMOVDYrm + 160U, // VPMASKMOVDmr + 512U, // VPMASKMOVDrm + 160U, // VPMASKMOVQYmr + 480U, // VPMASKMOVQYrm + 160U, // VPMASKMOVQmr + 512U, // VPMASKMOVQrm + 480U, // VPMAXSBYrm + 96U, // VPMAXSBYrr + 512U, // VPMAXSBZ128rm + 559396U, // VPMAXSBZ128rmk + 591972U, // VPMAXSBZ128rmkz + 96U, // VPMAXSBZ128rr + 166180U, // VPMAXSBZ128rrk + 198756U, // VPMAXSBZ128rrkz + 480U, // VPMAXSBZ256rm + 657700U, // VPMAXSBZ256rmk + 690276U, // VPMAXSBZ256rmkz + 96U, // VPMAXSBZ256rr + 166180U, // VPMAXSBZ256rrk + 198756U, // VPMAXSBZ256rrkz + 544U, // VPMAXSBZrm + 723236U, // VPMAXSBZrmk + 755812U, // VPMAXSBZrmkz + 96U, // VPMAXSBZrr + 166180U, // VPMAXSBZrrk + 198756U, // VPMAXSBZrrkz + 512U, // VPMAXSBrm + 96U, // VPMAXSBrr + 480U, // VPMAXSDYrm + 96U, // VPMAXSDYrr + 512U, // VPMAXSDZ128rm + 6208U, // VPMAXSDZ128rmb + 2591012U, // VPMAXSDZ128rmbk + 2623588U, // VPMAXSDZ128rmbkz + 559396U, // VPMAXSDZ128rmk + 591972U, // VPMAXSDZ128rmkz + 96U, // VPMAXSDZ128rr + 166180U, // VPMAXSDZ128rrk + 198756U, // VPMAXSDZ128rrkz + 480U, // VPMAXSDZ256rm + 8256U, // VPMAXSDZ256rmb + 3639588U, // VPMAXSDZ256rmbk + 3672164U, // VPMAXSDZ256rmbkz + 657700U, // VPMAXSDZ256rmk + 690276U, // VPMAXSDZ256rmkz + 96U, // VPMAXSDZ256rr + 166180U, // VPMAXSDZ256rrk + 198756U, // VPMAXSDZ256rrkz + 544U, // VPMAXSDZrm + 10304U, // VPMAXSDZrmb + 5736740U, // VPMAXSDZrmbk + 5769316U, // VPMAXSDZrmbkz + 723236U, // VPMAXSDZrmk + 755812U, // VPMAXSDZrmkz + 96U, // VPMAXSDZrr + 166180U, // VPMAXSDZrrk + 198756U, // VPMAXSDZrrkz + 512U, // VPMAXSDrm + 96U, // VPMAXSDrr + 512U, // VPMAXSQZ128rm + 4224U, // VPMAXSQZ128rmb + 1837348U, // VPMAXSQZ128rmbk + 1869924U, // VPMAXSQZ128rmbkz + 559396U, // VPMAXSQZ128rmk + 591972U, // VPMAXSQZ128rmkz + 96U, // VPMAXSQZ128rr + 166180U, // VPMAXSQZ128rrk + 198756U, // VPMAXSQZ128rrkz + 480U, // VPMAXSQZ256rm + 6272U, // VPMAXSQZ256rmb + 2885924U, // VPMAXSQZ256rmbk + 2918500U, // VPMAXSQZ256rmbkz + 657700U, // VPMAXSQZ256rmk + 690276U, // VPMAXSQZ256rmkz + 96U, // VPMAXSQZ256rr + 166180U, // VPMAXSQZ256rrk + 198756U, // VPMAXSQZ256rrkz + 544U, // VPMAXSQZrm + 8320U, // VPMAXSQZrmb + 3934500U, // VPMAXSQZrmbk + 3967076U, // VPMAXSQZrmbkz + 723236U, // VPMAXSQZrmk + 755812U, // VPMAXSQZrmkz + 96U, // VPMAXSQZrr + 166180U, // VPMAXSQZrrk + 198756U, // VPMAXSQZrrkz + 480U, // VPMAXSWYrm + 96U, // VPMAXSWYrr + 512U, // VPMAXSWZ128rm + 559396U, // VPMAXSWZ128rmk + 591972U, // VPMAXSWZ128rmkz + 96U, // VPMAXSWZ128rr + 166180U, // VPMAXSWZ128rrk + 198756U, // VPMAXSWZ128rrkz + 480U, // VPMAXSWZ256rm + 657700U, // VPMAXSWZ256rmk + 690276U, // VPMAXSWZ256rmkz + 96U, // VPMAXSWZ256rr + 166180U, // VPMAXSWZ256rrk + 198756U, // VPMAXSWZ256rrkz + 544U, // VPMAXSWZrm + 723236U, // VPMAXSWZrmk + 755812U, // VPMAXSWZrmkz + 96U, // VPMAXSWZrr + 166180U, // VPMAXSWZrrk + 198756U, // VPMAXSWZrrkz + 512U, // VPMAXSWrm + 96U, // VPMAXSWrr + 480U, // VPMAXUBYrm + 96U, // VPMAXUBYrr + 512U, // VPMAXUBZ128rm + 559396U, // VPMAXUBZ128rmk + 591972U, // VPMAXUBZ128rmkz + 96U, // VPMAXUBZ128rr + 166180U, // VPMAXUBZ128rrk + 198756U, // VPMAXUBZ128rrkz + 480U, // VPMAXUBZ256rm + 657700U, // VPMAXUBZ256rmk + 690276U, // VPMAXUBZ256rmkz + 96U, // VPMAXUBZ256rr + 166180U, // VPMAXUBZ256rrk + 198756U, // VPMAXUBZ256rrkz + 544U, // VPMAXUBZrm + 723236U, // VPMAXUBZrmk + 755812U, // VPMAXUBZrmkz + 96U, // VPMAXUBZrr + 166180U, // VPMAXUBZrrk + 198756U, // VPMAXUBZrrkz + 512U, // VPMAXUBrm + 96U, // VPMAXUBrr + 480U, // VPMAXUDYrm + 96U, // VPMAXUDYrr + 512U, // VPMAXUDZ128rm + 6208U, // VPMAXUDZ128rmb + 2591012U, // VPMAXUDZ128rmbk + 2623588U, // VPMAXUDZ128rmbkz + 559396U, // VPMAXUDZ128rmk + 591972U, // VPMAXUDZ128rmkz + 96U, // VPMAXUDZ128rr + 166180U, // VPMAXUDZ128rrk + 198756U, // VPMAXUDZ128rrkz + 480U, // VPMAXUDZ256rm + 8256U, // VPMAXUDZ256rmb + 3639588U, // VPMAXUDZ256rmbk + 3672164U, // VPMAXUDZ256rmbkz + 657700U, // VPMAXUDZ256rmk + 690276U, // VPMAXUDZ256rmkz + 96U, // VPMAXUDZ256rr + 166180U, // VPMAXUDZ256rrk + 198756U, // VPMAXUDZ256rrkz + 544U, // VPMAXUDZrm + 10304U, // VPMAXUDZrmb + 5736740U, // VPMAXUDZrmbk + 5769316U, // VPMAXUDZrmbkz + 723236U, // VPMAXUDZrmk + 755812U, // VPMAXUDZrmkz + 96U, // VPMAXUDZrr + 166180U, // VPMAXUDZrrk + 198756U, // VPMAXUDZrrkz + 512U, // VPMAXUDrm + 96U, // VPMAXUDrr + 512U, // VPMAXUQZ128rm + 4224U, // VPMAXUQZ128rmb + 1837348U, // VPMAXUQZ128rmbk + 1869924U, // VPMAXUQZ128rmbkz + 559396U, // VPMAXUQZ128rmk + 591972U, // VPMAXUQZ128rmkz + 96U, // VPMAXUQZ128rr + 166180U, // VPMAXUQZ128rrk + 198756U, // VPMAXUQZ128rrkz + 480U, // VPMAXUQZ256rm + 6272U, // VPMAXUQZ256rmb + 2885924U, // VPMAXUQZ256rmbk + 2918500U, // VPMAXUQZ256rmbkz + 657700U, // VPMAXUQZ256rmk + 690276U, // VPMAXUQZ256rmkz + 96U, // VPMAXUQZ256rr + 166180U, // VPMAXUQZ256rrk + 198756U, // VPMAXUQZ256rrkz + 544U, // VPMAXUQZrm + 8320U, // VPMAXUQZrmb + 3934500U, // VPMAXUQZrmbk + 3967076U, // VPMAXUQZrmbkz + 723236U, // VPMAXUQZrmk + 755812U, // VPMAXUQZrmkz + 96U, // VPMAXUQZrr + 166180U, // VPMAXUQZrrk + 198756U, // VPMAXUQZrrkz + 480U, // VPMAXUWYrm + 96U, // VPMAXUWYrr + 512U, // VPMAXUWZ128rm + 559396U, // VPMAXUWZ128rmk + 591972U, // VPMAXUWZ128rmkz + 96U, // VPMAXUWZ128rr + 166180U, // VPMAXUWZ128rrk + 198756U, // VPMAXUWZ128rrkz + 480U, // VPMAXUWZ256rm + 657700U, // VPMAXUWZ256rmk + 690276U, // VPMAXUWZ256rmkz + 96U, // VPMAXUWZ256rr + 166180U, // VPMAXUWZ256rrk + 198756U, // VPMAXUWZ256rrkz + 544U, // VPMAXUWZrm + 723236U, // VPMAXUWZrmk + 755812U, // VPMAXUWZrmkz + 96U, // VPMAXUWZrr + 166180U, // VPMAXUWZrrk + 198756U, // VPMAXUWZrrkz + 512U, // VPMAXUWrm + 96U, // VPMAXUWrr + 480U, // VPMINSBYrm + 96U, // VPMINSBYrr + 512U, // VPMINSBZ128rm + 559396U, // VPMINSBZ128rmk + 591972U, // VPMINSBZ128rmkz + 96U, // VPMINSBZ128rr + 166180U, // VPMINSBZ128rrk + 198756U, // VPMINSBZ128rrkz + 480U, // VPMINSBZ256rm + 657700U, // VPMINSBZ256rmk + 690276U, // VPMINSBZ256rmkz + 96U, // VPMINSBZ256rr + 166180U, // VPMINSBZ256rrk + 198756U, // VPMINSBZ256rrkz + 544U, // VPMINSBZrm + 723236U, // VPMINSBZrmk + 755812U, // VPMINSBZrmkz + 96U, // VPMINSBZrr + 166180U, // VPMINSBZrrk + 198756U, // VPMINSBZrrkz + 512U, // VPMINSBrm + 96U, // VPMINSBrr + 480U, // VPMINSDYrm + 96U, // VPMINSDYrr + 512U, // VPMINSDZ128rm + 6208U, // VPMINSDZ128rmb + 2591012U, // VPMINSDZ128rmbk + 2623588U, // VPMINSDZ128rmbkz + 559396U, // VPMINSDZ128rmk + 591972U, // VPMINSDZ128rmkz + 96U, // VPMINSDZ128rr + 166180U, // VPMINSDZ128rrk + 198756U, // VPMINSDZ128rrkz + 480U, // VPMINSDZ256rm + 8256U, // VPMINSDZ256rmb + 3639588U, // VPMINSDZ256rmbk + 3672164U, // VPMINSDZ256rmbkz + 657700U, // VPMINSDZ256rmk + 690276U, // VPMINSDZ256rmkz + 96U, // VPMINSDZ256rr + 166180U, // VPMINSDZ256rrk + 198756U, // VPMINSDZ256rrkz + 544U, // VPMINSDZrm + 10304U, // VPMINSDZrmb + 5736740U, // VPMINSDZrmbk + 5769316U, // VPMINSDZrmbkz + 723236U, // VPMINSDZrmk + 755812U, // VPMINSDZrmkz + 96U, // VPMINSDZrr + 166180U, // VPMINSDZrrk + 198756U, // VPMINSDZrrkz + 512U, // VPMINSDrm + 96U, // VPMINSDrr + 512U, // VPMINSQZ128rm + 4224U, // VPMINSQZ128rmb + 1837348U, // VPMINSQZ128rmbk + 1869924U, // VPMINSQZ128rmbkz + 559396U, // VPMINSQZ128rmk + 591972U, // VPMINSQZ128rmkz + 96U, // VPMINSQZ128rr + 166180U, // VPMINSQZ128rrk + 198756U, // VPMINSQZ128rrkz + 480U, // VPMINSQZ256rm + 6272U, // VPMINSQZ256rmb + 2885924U, // VPMINSQZ256rmbk + 2918500U, // VPMINSQZ256rmbkz + 657700U, // VPMINSQZ256rmk + 690276U, // VPMINSQZ256rmkz + 96U, // VPMINSQZ256rr + 166180U, // VPMINSQZ256rrk + 198756U, // VPMINSQZ256rrkz + 544U, // VPMINSQZrm + 8320U, // VPMINSQZrmb + 3934500U, // VPMINSQZrmbk + 3967076U, // VPMINSQZrmbkz + 723236U, // VPMINSQZrmk + 755812U, // VPMINSQZrmkz + 96U, // VPMINSQZrr + 166180U, // VPMINSQZrrk + 198756U, // VPMINSQZrrkz + 480U, // VPMINSWYrm + 96U, // VPMINSWYrr + 512U, // VPMINSWZ128rm + 559396U, // VPMINSWZ128rmk + 591972U, // VPMINSWZ128rmkz + 96U, // VPMINSWZ128rr + 166180U, // VPMINSWZ128rrk + 198756U, // VPMINSWZ128rrkz + 480U, // VPMINSWZ256rm + 657700U, // VPMINSWZ256rmk + 690276U, // VPMINSWZ256rmkz + 96U, // VPMINSWZ256rr + 166180U, // VPMINSWZ256rrk + 198756U, // VPMINSWZ256rrkz + 544U, // VPMINSWZrm + 723236U, // VPMINSWZrmk + 755812U, // VPMINSWZrmkz + 96U, // VPMINSWZrr + 166180U, // VPMINSWZrrk + 198756U, // VPMINSWZrrkz + 512U, // VPMINSWrm + 96U, // VPMINSWrr + 480U, // VPMINUBYrm + 96U, // VPMINUBYrr + 512U, // VPMINUBZ128rm + 559396U, // VPMINUBZ128rmk + 591972U, // VPMINUBZ128rmkz + 96U, // VPMINUBZ128rr + 166180U, // VPMINUBZ128rrk + 198756U, // VPMINUBZ128rrkz + 480U, // VPMINUBZ256rm + 657700U, // VPMINUBZ256rmk + 690276U, // VPMINUBZ256rmkz + 96U, // VPMINUBZ256rr + 166180U, // VPMINUBZ256rrk + 198756U, // VPMINUBZ256rrkz + 544U, // VPMINUBZrm + 723236U, // VPMINUBZrmk + 755812U, // VPMINUBZrmkz + 96U, // VPMINUBZrr + 166180U, // VPMINUBZrrk + 198756U, // VPMINUBZrrkz + 512U, // VPMINUBrm + 96U, // VPMINUBrr + 480U, // VPMINUDYrm + 96U, // VPMINUDYrr + 512U, // VPMINUDZ128rm + 6208U, // VPMINUDZ128rmb + 2591012U, // VPMINUDZ128rmbk + 2623588U, // VPMINUDZ128rmbkz + 559396U, // VPMINUDZ128rmk + 591972U, // VPMINUDZ128rmkz + 96U, // VPMINUDZ128rr + 166180U, // VPMINUDZ128rrk + 198756U, // VPMINUDZ128rrkz + 480U, // VPMINUDZ256rm + 8256U, // VPMINUDZ256rmb + 3639588U, // VPMINUDZ256rmbk + 3672164U, // VPMINUDZ256rmbkz + 657700U, // VPMINUDZ256rmk + 690276U, // VPMINUDZ256rmkz + 96U, // VPMINUDZ256rr + 166180U, // VPMINUDZ256rrk + 198756U, // VPMINUDZ256rrkz + 544U, // VPMINUDZrm + 10304U, // VPMINUDZrmb + 5736740U, // VPMINUDZrmbk + 5769316U, // VPMINUDZrmbkz + 723236U, // VPMINUDZrmk + 755812U, // VPMINUDZrmkz + 96U, // VPMINUDZrr + 166180U, // VPMINUDZrrk + 198756U, // VPMINUDZrrkz + 512U, // VPMINUDrm + 96U, // VPMINUDrr + 512U, // VPMINUQZ128rm + 4224U, // VPMINUQZ128rmb + 1837348U, // VPMINUQZ128rmbk + 1869924U, // VPMINUQZ128rmbkz + 559396U, // VPMINUQZ128rmk + 591972U, // VPMINUQZ128rmkz + 96U, // VPMINUQZ128rr + 166180U, // VPMINUQZ128rrk + 198756U, // VPMINUQZ128rrkz + 480U, // VPMINUQZ256rm + 6272U, // VPMINUQZ256rmb + 2885924U, // VPMINUQZ256rmbk + 2918500U, // VPMINUQZ256rmbkz + 657700U, // VPMINUQZ256rmk + 690276U, // VPMINUQZ256rmkz + 96U, // VPMINUQZ256rr + 166180U, // VPMINUQZ256rrk + 198756U, // VPMINUQZ256rrkz + 544U, // VPMINUQZrm + 8320U, // VPMINUQZrmb + 3934500U, // VPMINUQZrmbk + 3967076U, // VPMINUQZrmbkz + 723236U, // VPMINUQZrmk + 755812U, // VPMINUQZrmkz + 96U, // VPMINUQZrr + 166180U, // VPMINUQZrrk + 198756U, // VPMINUQZrrkz + 480U, // VPMINUWYrm + 96U, // VPMINUWYrr + 512U, // VPMINUWZ128rm + 559396U, // VPMINUWZ128rmk + 591972U, // VPMINUWZ128rmkz + 96U, // VPMINUWZ128rr + 166180U, // VPMINUWZ128rrk + 198756U, // VPMINUWZ128rrkz + 480U, // VPMINUWZ256rm + 657700U, // VPMINUWZ256rmk + 690276U, // VPMINUWZ256rmkz + 96U, // VPMINUWZ256rr + 166180U, // VPMINUWZ256rrk + 198756U, // VPMINUWZ256rrkz + 544U, // VPMINUWZrm + 723236U, // VPMINUWZrmk + 755812U, // VPMINUWZrmkz + 96U, // VPMINUWZrr + 166180U, // VPMINUWZrrk + 198756U, // VPMINUWZrrkz + 512U, // VPMINUWrm + 96U, // VPMINUWrr + 0U, // VPMOVB2MZ128rr + 0U, // VPMOVB2MZ256rr + 0U, // VPMOVB2MZrr + 0U, // VPMOVD2MZ128rr + 0U, // VPMOVD2MZ256rr + 0U, // VPMOVD2MZrr + 0U, // VPMOVDBZ128mr + 164U, // VPMOVDBZ128mrk + 0U, // VPMOVDBZ128rr + 292U, // VPMOVDBZ128rrk + 100U, // VPMOVDBZ128rrkz + 0U, // VPMOVDBZ256mr + 164U, // VPMOVDBZ256mrk + 0U, // VPMOVDBZ256rr + 292U, // VPMOVDBZ256rrk + 100U, // VPMOVDBZ256rrkz + 0U, // VPMOVDBZmr + 164U, // VPMOVDBZmrk + 0U, // VPMOVDBZrr + 292U, // VPMOVDBZrrk + 100U, // VPMOVDBZrrkz + 0U, // VPMOVDWZ128mr + 164U, // VPMOVDWZ128mrk + 0U, // VPMOVDWZ128rr + 292U, // VPMOVDWZ128rrk + 100U, // VPMOVDWZ128rrkz + 0U, // VPMOVDWZ256mr + 164U, // VPMOVDWZ256mrk + 0U, // VPMOVDWZ256rr + 292U, // VPMOVDWZ256rrk + 100U, // VPMOVDWZ256rrkz + 0U, // VPMOVDWZmr + 164U, // VPMOVDWZmrk + 0U, // VPMOVDWZrr + 292U, // VPMOVDWZrrk + 100U, // VPMOVDWZrrkz + 0U, // VPMOVM2BZ128rr + 0U, // VPMOVM2BZ256rr + 0U, // VPMOVM2BZrr + 0U, // VPMOVM2DZ128rr + 0U, // VPMOVM2DZ256rr + 0U, // VPMOVM2DZrr + 0U, // VPMOVM2QZ128rr + 0U, // VPMOVM2QZ256rr + 0U, // VPMOVM2QZrr + 0U, // VPMOVM2WZ128rr + 0U, // VPMOVM2WZ256rr + 0U, // VPMOVM2WZrr + 0U, // VPMOVMSKBYrr + 0U, // VPMOVMSKBrr + 0U, // VPMOVQ2MZ128rr + 0U, // VPMOVQ2MZ256rr + 0U, // VPMOVQ2MZrr + 0U, // VPMOVQBZ128mr + 164U, // VPMOVQBZ128mrk + 0U, // VPMOVQBZ128rr + 292U, // VPMOVQBZ128rrk + 100U, // VPMOVQBZ128rrkz + 0U, // VPMOVQBZ256mr + 164U, // VPMOVQBZ256mrk + 0U, // VPMOVQBZ256rr + 292U, // VPMOVQBZ256rrk + 100U, // VPMOVQBZ256rrkz + 0U, // VPMOVQBZmr + 164U, // VPMOVQBZmrk + 0U, // VPMOVQBZrr + 292U, // VPMOVQBZrrk + 100U, // VPMOVQBZrrkz + 0U, // VPMOVQDZ128mr + 164U, // VPMOVQDZ128mrk + 0U, // VPMOVQDZ128rr + 292U, // VPMOVQDZ128rrk + 100U, // VPMOVQDZ128rrkz + 0U, // VPMOVQDZ256mr + 164U, // VPMOVQDZ256mrk + 0U, // VPMOVQDZ256rr + 292U, // VPMOVQDZ256rrk + 100U, // VPMOVQDZ256rrkz + 0U, // VPMOVQDZmr + 164U, // VPMOVQDZmrk + 0U, // VPMOVQDZrr + 292U, // VPMOVQDZrrk + 100U, // VPMOVQDZrrkz + 0U, // VPMOVQWZ128mr + 164U, // VPMOVQWZ128mrk + 0U, // VPMOVQWZ128rr + 292U, // VPMOVQWZ128rrk + 100U, // VPMOVQWZ128rrkz + 0U, // VPMOVQWZ256mr + 164U, // VPMOVQWZ256mrk + 0U, // VPMOVQWZ256rr + 292U, // VPMOVQWZ256rrk + 100U, // VPMOVQWZ256rrkz + 0U, // VPMOVQWZmr + 164U, // VPMOVQWZmrk + 0U, // VPMOVQWZrr + 292U, // VPMOVQWZrrk + 100U, // VPMOVQWZrrkz + 0U, // VPMOVSDBZ128mr + 164U, // VPMOVSDBZ128mrk + 0U, // VPMOVSDBZ128rr + 292U, // VPMOVSDBZ128rrk + 100U, // VPMOVSDBZ128rrkz + 0U, // VPMOVSDBZ256mr + 164U, // VPMOVSDBZ256mrk + 0U, // VPMOVSDBZ256rr + 292U, // VPMOVSDBZ256rrk + 100U, // VPMOVSDBZ256rrkz + 0U, // VPMOVSDBZmr + 164U, // VPMOVSDBZmrk + 0U, // VPMOVSDBZrr + 292U, // VPMOVSDBZrrk + 100U, // VPMOVSDBZrrkz + 0U, // VPMOVSDWZ128mr + 164U, // VPMOVSDWZ128mrk + 0U, // VPMOVSDWZ128rr + 292U, // VPMOVSDWZ128rrk + 100U, // VPMOVSDWZ128rrkz + 0U, // VPMOVSDWZ256mr + 164U, // VPMOVSDWZ256mrk + 0U, // VPMOVSDWZ256rr + 292U, // VPMOVSDWZ256rrk + 100U, // VPMOVSDWZ256rrkz + 0U, // VPMOVSDWZmr + 164U, // VPMOVSDWZmrk + 0U, // VPMOVSDWZrr + 292U, // VPMOVSDWZrrk + 100U, // VPMOVSDWZrrkz + 0U, // VPMOVSQBZ128mr + 164U, // VPMOVSQBZ128mrk + 0U, // VPMOVSQBZ128rr + 292U, // VPMOVSQBZ128rrk + 100U, // VPMOVSQBZ128rrkz + 0U, // VPMOVSQBZ256mr + 164U, // VPMOVSQBZ256mrk + 0U, // VPMOVSQBZ256rr + 292U, // VPMOVSQBZ256rrk + 100U, // VPMOVSQBZ256rrkz + 0U, // VPMOVSQBZmr + 164U, // VPMOVSQBZmrk + 0U, // VPMOVSQBZrr + 292U, // VPMOVSQBZrrk + 100U, // VPMOVSQBZrrkz + 0U, // VPMOVSQDZ128mr + 164U, // VPMOVSQDZ128mrk + 0U, // VPMOVSQDZ128rr + 292U, // VPMOVSQDZ128rrk + 100U, // VPMOVSQDZ128rrkz + 0U, // VPMOVSQDZ256mr + 164U, // VPMOVSQDZ256mrk + 0U, // VPMOVSQDZ256rr + 292U, // VPMOVSQDZ256rrk + 100U, // VPMOVSQDZ256rrkz + 0U, // VPMOVSQDZmr + 164U, // VPMOVSQDZmrk + 0U, // VPMOVSQDZrr + 292U, // VPMOVSQDZrrk + 100U, // VPMOVSQDZrrkz + 0U, // VPMOVSQWZ128mr + 164U, // VPMOVSQWZ128mrk + 0U, // VPMOVSQWZ128rr + 292U, // VPMOVSQWZ128rrk + 100U, // VPMOVSQWZ128rrkz + 0U, // VPMOVSQWZ256mr + 164U, // VPMOVSQWZ256mrk + 0U, // VPMOVSQWZ256rr + 292U, // VPMOVSQWZ256rrk + 100U, // VPMOVSQWZ256rrkz + 0U, // VPMOVSQWZmr + 164U, // VPMOVSQWZmrk + 0U, // VPMOVSQWZrr + 292U, // VPMOVSQWZrrk + 100U, // VPMOVSQWZrrkz + 0U, // VPMOVSWBZ128mr + 164U, // VPMOVSWBZ128mrk + 0U, // VPMOVSWBZ128rr + 292U, // VPMOVSWBZ128rrk + 100U, // VPMOVSWBZ128rrkz + 0U, // VPMOVSWBZ256mr + 164U, // VPMOVSWBZ256mrk + 0U, // VPMOVSWBZ256rr + 292U, // VPMOVSWBZ256rrk + 100U, // VPMOVSWBZ256rrkz + 0U, // VPMOVSWBZmr + 164U, // VPMOVSWBZmrk + 0U, // VPMOVSWBZrr + 292U, // VPMOVSWBZrrk + 100U, // VPMOVSWBZrrkz + 0U, // VPMOVSXBDYrm + 0U, // VPMOVSXBDYrr + 0U, // VPMOVSXBDZ128rm + 964U, // VPMOVSXBDZ128rmk + 68U, // VPMOVSXBDZ128rmkz + 0U, // VPMOVSXBDZ128rr + 292U, // VPMOVSXBDZ128rrk + 100U, // VPMOVSXBDZ128rrkz + 0U, // VPMOVSXBDZ256rm + 644U, // VPMOVSXBDZ256rmk + 132U, // VPMOVSXBDZ256rmkz + 0U, // VPMOVSXBDZ256rr + 292U, // VPMOVSXBDZ256rrk + 100U, // VPMOVSXBDZ256rrkz + 0U, // VPMOVSXBDZrm + 676U, // VPMOVSXBDZrmk + 516U, // VPMOVSXBDZrmkz + 0U, // VPMOVSXBDZrr + 292U, // VPMOVSXBDZrrk + 100U, // VPMOVSXBDZrrkz + 0U, // VPMOVSXBDrm + 0U, // VPMOVSXBDrr + 0U, // VPMOVSXBQYrm + 0U, // VPMOVSXBQYrr + 0U, // VPMOVSXBQZ128rm + 1188U, // VPMOVSXBQZ128rmk + 1220U, // VPMOVSXBQZ128rmkz + 0U, // VPMOVSXBQZ128rr + 292U, // VPMOVSXBQZ128rrk + 100U, // VPMOVSXBQZ128rrkz + 0U, // VPMOVSXBQZ256rm + 964U, // VPMOVSXBQZ256rmk + 68U, // VPMOVSXBQZ256rmkz + 0U, // VPMOVSXBQZ256rr + 292U, // VPMOVSXBQZ256rrk + 100U, // VPMOVSXBQZ256rrkz + 0U, // VPMOVSXBQZrm + 644U, // VPMOVSXBQZrmk + 132U, // VPMOVSXBQZrmkz + 0U, // VPMOVSXBQZrr + 292U, // VPMOVSXBQZrrk + 100U, // VPMOVSXBQZrrkz + 0U, // VPMOVSXBQrm + 0U, // VPMOVSXBQrr + 0U, // VPMOVSXBWYrm + 0U, // VPMOVSXBWYrr + 0U, // VPMOVSXBWZ128rm + 644U, // VPMOVSXBWZ128rmk + 132U, // VPMOVSXBWZ128rmkz + 0U, // VPMOVSXBWZ128rr + 292U, // VPMOVSXBWZ128rrk + 100U, // VPMOVSXBWZ128rrkz + 0U, // VPMOVSXBWZ256rm + 676U, // VPMOVSXBWZ256rmk + 516U, // VPMOVSXBWZ256rmkz + 0U, // VPMOVSXBWZ256rr + 292U, // VPMOVSXBWZ256rrk + 100U, // VPMOVSXBWZ256rrkz + 0U, // VPMOVSXBWZrm + 708U, // VPMOVSXBWZrmk + 484U, // VPMOVSXBWZrmkz + 0U, // VPMOVSXBWZrr + 292U, // VPMOVSXBWZrrk + 100U, // VPMOVSXBWZrrkz + 0U, // VPMOVSXBWrm + 0U, // VPMOVSXBWrr + 0U, // VPMOVSXDQYrm + 0U, // VPMOVSXDQYrr + 0U, // VPMOVSXDQZ128rm + 644U, // VPMOVSXDQZ128rmk + 132U, // VPMOVSXDQZ128rmkz + 0U, // VPMOVSXDQZ128rr + 292U, // VPMOVSXDQZ128rrk + 100U, // VPMOVSXDQZ128rrkz + 0U, // VPMOVSXDQZ256rm + 676U, // VPMOVSXDQZ256rmk + 516U, // VPMOVSXDQZ256rmkz + 0U, // VPMOVSXDQZ256rr + 292U, // VPMOVSXDQZ256rrk + 100U, // VPMOVSXDQZ256rrkz + 0U, // VPMOVSXDQZrm + 708U, // VPMOVSXDQZrmk + 484U, // VPMOVSXDQZrmkz + 0U, // VPMOVSXDQZrr + 292U, // VPMOVSXDQZrrk + 100U, // VPMOVSXDQZrrkz + 0U, // VPMOVSXDQrm + 0U, // VPMOVSXDQrr + 0U, // VPMOVSXWDYrm + 0U, // VPMOVSXWDYrr + 0U, // VPMOVSXWDZ128rm + 644U, // VPMOVSXWDZ128rmk + 132U, // VPMOVSXWDZ128rmkz + 0U, // VPMOVSXWDZ128rr + 292U, // VPMOVSXWDZ128rrk + 100U, // VPMOVSXWDZ128rrkz + 0U, // VPMOVSXWDZ256rm + 676U, // VPMOVSXWDZ256rmk + 516U, // VPMOVSXWDZ256rmkz + 0U, // VPMOVSXWDZ256rr + 292U, // VPMOVSXWDZ256rrk + 100U, // VPMOVSXWDZ256rrkz + 0U, // VPMOVSXWDZrm + 708U, // VPMOVSXWDZrmk + 484U, // VPMOVSXWDZrmkz + 0U, // VPMOVSXWDZrr + 292U, // VPMOVSXWDZrrk + 100U, // VPMOVSXWDZrrkz + 0U, // VPMOVSXWDrm + 0U, // VPMOVSXWDrr + 0U, // VPMOVSXWQYrm + 0U, // VPMOVSXWQYrr + 0U, // VPMOVSXWQZ128rm + 964U, // VPMOVSXWQZ128rmk + 68U, // VPMOVSXWQZ128rmkz + 0U, // VPMOVSXWQZ128rr + 292U, // VPMOVSXWQZ128rrk + 100U, // VPMOVSXWQZ128rrkz + 0U, // VPMOVSXWQZ256rm + 644U, // VPMOVSXWQZ256rmk + 132U, // VPMOVSXWQZ256rmkz + 0U, // VPMOVSXWQZ256rr + 292U, // VPMOVSXWQZ256rrk + 100U, // VPMOVSXWQZ256rrkz + 0U, // VPMOVSXWQZrm + 676U, // VPMOVSXWQZrmk + 516U, // VPMOVSXWQZrmkz + 0U, // VPMOVSXWQZrr + 292U, // VPMOVSXWQZrrk + 100U, // VPMOVSXWQZrrkz + 0U, // VPMOVSXWQrm + 0U, // VPMOVSXWQrr + 0U, // VPMOVUSDBZ128mr + 164U, // VPMOVUSDBZ128mrk + 0U, // VPMOVUSDBZ128rr + 292U, // VPMOVUSDBZ128rrk + 100U, // VPMOVUSDBZ128rrkz + 0U, // VPMOVUSDBZ256mr + 164U, // VPMOVUSDBZ256mrk + 0U, // VPMOVUSDBZ256rr + 292U, // VPMOVUSDBZ256rrk + 100U, // VPMOVUSDBZ256rrkz + 0U, // VPMOVUSDBZmr + 164U, // VPMOVUSDBZmrk + 0U, // VPMOVUSDBZrr + 292U, // VPMOVUSDBZrrk + 100U, // VPMOVUSDBZrrkz + 0U, // VPMOVUSDWZ128mr + 164U, // VPMOVUSDWZ128mrk + 0U, // VPMOVUSDWZ128rr + 292U, // VPMOVUSDWZ128rrk + 100U, // VPMOVUSDWZ128rrkz + 0U, // VPMOVUSDWZ256mr + 164U, // VPMOVUSDWZ256mrk + 0U, // VPMOVUSDWZ256rr + 292U, // VPMOVUSDWZ256rrk + 100U, // VPMOVUSDWZ256rrkz + 0U, // VPMOVUSDWZmr + 164U, // VPMOVUSDWZmrk + 0U, // VPMOVUSDWZrr + 292U, // VPMOVUSDWZrrk + 100U, // VPMOVUSDWZrrkz + 0U, // VPMOVUSQBZ128mr + 164U, // VPMOVUSQBZ128mrk + 0U, // VPMOVUSQBZ128rr + 292U, // VPMOVUSQBZ128rrk + 100U, // VPMOVUSQBZ128rrkz + 0U, // VPMOVUSQBZ256mr + 164U, // VPMOVUSQBZ256mrk + 0U, // VPMOVUSQBZ256rr + 292U, // VPMOVUSQBZ256rrk + 100U, // VPMOVUSQBZ256rrkz + 0U, // VPMOVUSQBZmr + 164U, // VPMOVUSQBZmrk + 0U, // VPMOVUSQBZrr + 292U, // VPMOVUSQBZrrk + 100U, // VPMOVUSQBZrrkz + 0U, // VPMOVUSQDZ128mr + 164U, // VPMOVUSQDZ128mrk + 0U, // VPMOVUSQDZ128rr + 292U, // VPMOVUSQDZ128rrk + 100U, // VPMOVUSQDZ128rrkz + 0U, // VPMOVUSQDZ256mr + 164U, // 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0U, // VPMOVW2MZ128rr + 0U, // VPMOVW2MZ256rr + 0U, // VPMOVW2MZrr + 0U, // VPMOVWBZ128mr + 164U, // VPMOVWBZ128mrk + 0U, // VPMOVWBZ128rr + 292U, // VPMOVWBZ128rrk + 100U, // VPMOVWBZ128rrkz + 0U, // VPMOVWBZ256mr + 164U, // VPMOVWBZ256mrk + 0U, // VPMOVWBZ256rr + 292U, // VPMOVWBZ256rrk + 100U, // VPMOVWBZ256rrkz + 0U, // VPMOVWBZmr + 164U, // VPMOVWBZmrk + 0U, // VPMOVWBZrr + 292U, // VPMOVWBZrrk + 100U, // VPMOVWBZrrkz + 0U, // VPMOVZXBDYrm + 0U, // VPMOVZXBDYrr + 0U, // VPMOVZXBDZ128rm + 964U, // VPMOVZXBDZ128rmk + 68U, // VPMOVZXBDZ128rmkz + 0U, // VPMOVZXBDZ128rr + 292U, // VPMOVZXBDZ128rrk + 100U, // VPMOVZXBDZ128rrkz + 0U, // VPMOVZXBDZ256rm + 644U, // VPMOVZXBDZ256rmk + 132U, // VPMOVZXBDZ256rmkz + 0U, // VPMOVZXBDZ256rr + 292U, // VPMOVZXBDZ256rrk + 100U, // VPMOVZXBDZ256rrkz + 0U, // VPMOVZXBDZrm + 676U, // VPMOVZXBDZrmk + 516U, // VPMOVZXBDZrmkz + 0U, // VPMOVZXBDZrr + 292U, // VPMOVZXBDZrrk + 100U, // VPMOVZXBDZrrkz + 0U, // VPMOVZXBDrm + 0U, // VPMOVZXBDrr + 0U, // VPMOVZXBQYrm + 0U, // VPMOVZXBQYrr + 0U, // VPMOVZXBQZ128rm + 1188U, // VPMOVZXBQZ128rmk + 1220U, // VPMOVZXBQZ128rmkz + 0U, // VPMOVZXBQZ128rr + 292U, // VPMOVZXBQZ128rrk + 100U, // VPMOVZXBQZ128rrkz + 0U, // VPMOVZXBQZ256rm + 964U, // VPMOVZXBQZ256rmk + 68U, // VPMOVZXBQZ256rmkz + 0U, // VPMOVZXBQZ256rr + 292U, // VPMOVZXBQZ256rrk + 100U, // VPMOVZXBQZ256rrkz + 0U, // VPMOVZXBQZrm + 644U, // VPMOVZXBQZrmk + 132U, // VPMOVZXBQZrmkz + 0U, // VPMOVZXBQZrr + 292U, // VPMOVZXBQZrrk + 100U, // VPMOVZXBQZrrkz + 0U, // VPMOVZXBQrm + 0U, // VPMOVZXBQrr + 0U, // VPMOVZXBWYrm + 0U, // VPMOVZXBWYrr + 0U, // VPMOVZXBWZ128rm + 644U, // VPMOVZXBWZ128rmk + 132U, // VPMOVZXBWZ128rmkz + 0U, // VPMOVZXBWZ128rr + 292U, // VPMOVZXBWZ128rrk + 100U, // VPMOVZXBWZ128rrkz + 0U, // VPMOVZXBWZ256rm + 676U, // VPMOVZXBWZ256rmk + 516U, // VPMOVZXBWZ256rmkz + 0U, // VPMOVZXBWZ256rr + 292U, // VPMOVZXBWZ256rrk + 100U, // VPMOVZXBWZ256rrkz + 0U, // VPMOVZXBWZrm + 708U, // VPMOVZXBWZrmk + 484U, // VPMOVZXBWZrmkz + 0U, // VPMOVZXBWZrr + 292U, // VPMOVZXBWZrrk + 100U, // VPMOVZXBWZrrkz + 0U, // VPMOVZXBWrm + 0U, // VPMOVZXBWrr + 0U, // VPMOVZXDQYrm + 0U, // VPMOVZXDQYrr + 0U, // VPMOVZXDQZ128rm + 644U, // VPMOVZXDQZ128rmk + 132U, // VPMOVZXDQZ128rmkz + 0U, // VPMOVZXDQZ128rr + 292U, // VPMOVZXDQZ128rrk + 100U, // VPMOVZXDQZ128rrkz + 0U, // VPMOVZXDQZ256rm + 676U, // VPMOVZXDQZ256rmk + 516U, // VPMOVZXDQZ256rmkz + 0U, // VPMOVZXDQZ256rr + 292U, // VPMOVZXDQZ256rrk + 100U, // VPMOVZXDQZ256rrkz + 0U, // VPMOVZXDQZrm + 708U, // VPMOVZXDQZrmk + 484U, // VPMOVZXDQZrmkz + 0U, // VPMOVZXDQZrr + 292U, // VPMOVZXDQZrrk + 100U, // VPMOVZXDQZrrkz + 0U, // VPMOVZXDQrm + 0U, // VPMOVZXDQrr + 0U, // VPMOVZXWDYrm + 0U, // VPMOVZXWDYrr + 0U, // VPMOVZXWDZ128rm + 644U, // VPMOVZXWDZ128rmk + 132U, // VPMOVZXWDZ128rmkz + 0U, // VPMOVZXWDZ128rr + 292U, // VPMOVZXWDZ128rrk + 100U, // VPMOVZXWDZ128rrkz + 0U, // VPMOVZXWDZ256rm + 676U, // VPMOVZXWDZ256rmk + 516U, // VPMOVZXWDZ256rmkz + 0U, // VPMOVZXWDZ256rr + 292U, // VPMOVZXWDZ256rrk + 100U, // VPMOVZXWDZ256rrkz + 0U, // VPMOVZXWDZrm + 708U, // VPMOVZXWDZrmk + 484U, // VPMOVZXWDZrmkz + 0U, // VPMOVZXWDZrr + 292U, // VPMOVZXWDZrrk + 100U, // VPMOVZXWDZrrkz + 0U, // VPMOVZXWDrm + 0U, // VPMOVZXWDrr + 0U, // VPMOVZXWQYrm + 0U, // VPMOVZXWQYrr + 0U, // VPMOVZXWQZ128rm + 964U, // VPMOVZXWQZ128rmk + 68U, // VPMOVZXWQZ128rmkz + 0U, // VPMOVZXWQZ128rr + 292U, // VPMOVZXWQZ128rrk + 100U, // VPMOVZXWQZ128rrkz + 0U, // VPMOVZXWQZ256rm + 644U, // VPMOVZXWQZ256rmk + 132U, // VPMOVZXWQZ256rmkz + 0U, // VPMOVZXWQZ256rr + 292U, // VPMOVZXWQZ256rrk + 100U, // VPMOVZXWQZ256rrkz + 0U, // VPMOVZXWQZrm + 676U, // VPMOVZXWQZrmk + 516U, // VPMOVZXWQZrmkz + 0U, // VPMOVZXWQZrr + 292U, // VPMOVZXWQZrrk + 100U, // VPMOVZXWQZrrkz + 0U, // VPMOVZXWQrm + 0U, // VPMOVZXWQrr + 480U, // VPMULDQYrm + 96U, // VPMULDQYrr + 512U, // VPMULDQZ128rm + 4224U, // VPMULDQZ128rmb + 1837348U, // VPMULDQZ128rmbk + 1869924U, // VPMULDQZ128rmbkz + 559396U, // VPMULDQZ128rmk + 591972U, // VPMULDQZ128rmkz + 96U, // VPMULDQZ128rr + 166180U, // VPMULDQZ128rrk + 198756U, // VPMULDQZ128rrkz + 480U, // VPMULDQZ256rm + 6272U, // VPMULDQZ256rmb + 2885924U, // VPMULDQZ256rmbk + 2918500U, // VPMULDQZ256rmbkz + 657700U, // VPMULDQZ256rmk + 690276U, // VPMULDQZ256rmkz + 96U, // VPMULDQZ256rr + 166180U, // VPMULDQZ256rrk + 198756U, // VPMULDQZ256rrkz + 544U, // VPMULDQZrm + 8320U, // VPMULDQZrmb + 3934500U, // VPMULDQZrmbk + 3967076U, // VPMULDQZrmbkz + 723236U, // VPMULDQZrmk + 755812U, // VPMULDQZrmkz + 96U, // VPMULDQZrr + 166180U, // VPMULDQZrrk + 198756U, // VPMULDQZrrkz + 512U, // VPMULDQrm + 96U, // VPMULDQrr + 480U, // VPMULHRSWYrm + 96U, // VPMULHRSWYrr + 512U, // VPMULHRSWZ128rm + 559396U, // VPMULHRSWZ128rmk + 591972U, // VPMULHRSWZ128rmkz + 96U, // VPMULHRSWZ128rr + 166180U, // VPMULHRSWZ128rrk + 198756U, // VPMULHRSWZ128rrkz + 480U, // VPMULHRSWZ256rm + 657700U, // VPMULHRSWZ256rmk + 690276U, // VPMULHRSWZ256rmkz + 96U, // VPMULHRSWZ256rr + 166180U, // VPMULHRSWZ256rrk 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VPMULHWZ128rrk + 198756U, // VPMULHWZ128rrkz + 480U, // VPMULHWZ256rm + 657700U, // VPMULHWZ256rmk + 690276U, // VPMULHWZ256rmkz + 96U, // VPMULHWZ256rr + 166180U, // VPMULHWZ256rrk + 198756U, // VPMULHWZ256rrkz + 544U, // VPMULHWZrm + 723236U, // VPMULHWZrmk + 755812U, // VPMULHWZrmkz + 96U, // VPMULHWZrr + 166180U, // VPMULHWZrrk + 198756U, // VPMULHWZrrkz + 512U, // VPMULHWrm + 96U, // VPMULHWrr + 480U, // VPMULLDYrm + 96U, // VPMULLDYrr + 512U, // VPMULLDZ128rm + 6208U, // VPMULLDZ128rmb + 2591012U, // VPMULLDZ128rmbk + 2623588U, // VPMULLDZ128rmbkz + 559396U, // VPMULLDZ128rmk + 591972U, // VPMULLDZ128rmkz + 96U, // VPMULLDZ128rr + 166180U, // VPMULLDZ128rrk + 198756U, // VPMULLDZ128rrkz + 480U, // VPMULLDZ256rm + 8256U, // VPMULLDZ256rmb + 3639588U, // VPMULLDZ256rmbk + 3672164U, // VPMULLDZ256rmbkz + 657700U, // VPMULLDZ256rmk + 690276U, // VPMULLDZ256rmkz + 96U, // VPMULLDZ256rr + 166180U, // VPMULLDZ256rrk + 198756U, // VPMULLDZ256rrkz + 544U, // VPMULLDZrm + 10304U, // VPMULLDZrmb + 5736740U, // VPMULLDZrmbk + 5769316U, // VPMULLDZrmbkz + 723236U, // VPMULLDZrmk + 755812U, // VPMULLDZrmkz + 96U, // VPMULLDZrr + 166180U, // VPMULLDZrrk + 198756U, // VPMULLDZrrkz + 512U, // VPMULLDrm + 96U, // VPMULLDrr + 512U, // VPMULLQZ128rm + 4224U, // VPMULLQZ128rmb + 1837348U, // VPMULLQZ128rmbk + 1869924U, // VPMULLQZ128rmbkz + 559396U, // VPMULLQZ128rmk + 591972U, // VPMULLQZ128rmkz + 96U, // VPMULLQZ128rr + 166180U, // VPMULLQZ128rrk + 198756U, // VPMULLQZ128rrkz + 480U, // VPMULLQZ256rm + 6272U, // VPMULLQZ256rmb + 2885924U, // VPMULLQZ256rmbk + 2918500U, // VPMULLQZ256rmbkz + 657700U, // VPMULLQZ256rmk + 690276U, // VPMULLQZ256rmkz + 96U, // VPMULLQZ256rr + 166180U, // VPMULLQZ256rrk + 198756U, // VPMULLQZ256rrkz + 544U, // VPMULLQZrm + 8320U, // VPMULLQZrmb + 3934500U, // VPMULLQZrmbk + 3967076U, // VPMULLQZrmbkz + 723236U, // VPMULLQZrmk + 755812U, // VPMULLQZrmkz + 96U, // VPMULLQZrr + 166180U, // VPMULLQZrrk + 198756U, // VPMULLQZrrkz + 480U, // VPMULLWYrm + 96U, // VPMULLWYrr + 512U, // VPMULLWZ128rm + 559396U, // VPMULLWZ128rmk + 591972U, // VPMULLWZ128rmkz + 96U, // VPMULLWZ128rr + 166180U, // VPMULLWZ128rrk + 198756U, // VPMULLWZ128rrkz + 480U, // VPMULLWZ256rm + 657700U, // VPMULLWZ256rmk + 690276U, // VPMULLWZ256rmkz + 96U, // VPMULLWZ256rr + 166180U, // VPMULLWZ256rrk + 198756U, // VPMULLWZ256rrkz + 544U, // VPMULLWZrm + 723236U, // VPMULLWZrmk + 755812U, // VPMULLWZrmkz + 96U, // VPMULLWZrr + 166180U, // VPMULLWZrrk + 198756U, // VPMULLWZrrkz + 512U, // VPMULLWrm + 96U, // VPMULLWrr + 512U, // VPMULTISHIFTQBZ128rm + 4224U, // VPMULTISHIFTQBZ128rmb + 1837348U, // VPMULTISHIFTQBZ128rmbk + 1869924U, // VPMULTISHIFTQBZ128rmbkz + 559396U, // VPMULTISHIFTQBZ128rmk + 591972U, // VPMULTISHIFTQBZ128rmkz + 96U, // VPMULTISHIFTQBZ128rr + 166180U, // VPMULTISHIFTQBZ128rrk + 198756U, // VPMULTISHIFTQBZ128rrkz + 480U, // VPMULTISHIFTQBZ256rm + 6272U, // VPMULTISHIFTQBZ256rmb + 2885924U, // VPMULTISHIFTQBZ256rmbk + 2918500U, // VPMULTISHIFTQBZ256rmbkz + 657700U, // VPMULTISHIFTQBZ256rmk + 690276U, // VPMULTISHIFTQBZ256rmkz + 96U, // VPMULTISHIFTQBZ256rr + 166180U, // VPMULTISHIFTQBZ256rrk + 198756U, // VPMULTISHIFTQBZ256rrkz + 544U, // VPMULTISHIFTQBZrm + 8320U, // VPMULTISHIFTQBZrmb + 3934500U, // VPMULTISHIFTQBZrmbk + 3967076U, // VPMULTISHIFTQBZrmbkz + 723236U, // VPMULTISHIFTQBZrmk + 755812U, // VPMULTISHIFTQBZrmkz + 96U, // VPMULTISHIFTQBZrr + 166180U, // VPMULTISHIFTQBZrrk + 198756U, // VPMULTISHIFTQBZrrkz + 480U, // VPMULUDQYrm + 96U, // VPMULUDQYrr + 512U, // VPMULUDQZ128rm + 4224U, // VPMULUDQZ128rmb + 1837348U, // VPMULUDQZ128rmbk + 1869924U, // VPMULUDQZ128rmbkz + 559396U, // VPMULUDQZ128rmk + 591972U, // VPMULUDQZ128rmkz + 96U, // VPMULUDQZ128rr + 166180U, // VPMULUDQZ128rrk + 198756U, // VPMULUDQZ128rrkz + 480U, // VPMULUDQZ256rm + 6272U, // VPMULUDQZ256rmb + 2885924U, // VPMULUDQZ256rmbk + 2918500U, // VPMULUDQZ256rmbkz + 657700U, // VPMULUDQZ256rmk + 690276U, // VPMULUDQZ256rmkz + 96U, // VPMULUDQZ256rr + 166180U, // VPMULUDQZ256rrk + 198756U, // VPMULUDQZ256rrkz + 544U, // VPMULUDQZrm + 8320U, // VPMULUDQZrmb + 3934500U, // VPMULUDQZrmbk + 3967076U, // VPMULUDQZrmbkz + 723236U, // VPMULUDQZrmk + 755812U, // VPMULUDQZrmkz + 96U, // VPMULUDQZrr + 166180U, // VPMULUDQZrrk + 198756U, // VPMULUDQZrrkz + 512U, // VPMULUDQrm + 96U, // VPMULUDQrr + 0U, // VPOPCNTBZ128rm + 676U, // VPOPCNTBZ128rmk + 516U, // VPOPCNTBZ128rmkz + 0U, // VPOPCNTBZ128rr + 292U, // VPOPCNTBZ128rrk + 100U, // VPOPCNTBZ128rrkz + 0U, // VPOPCNTBZ256rm + 708U, // VPOPCNTBZ256rmk + 484U, // VPOPCNTBZ256rmkz + 0U, // VPOPCNTBZ256rr + 292U, // VPOPCNTBZ256rrk + 100U, // VPOPCNTBZ256rrkz + 0U, // VPOPCNTBZrm + 996U, // VPOPCNTBZrmk + 548U, // VPOPCNTBZrmkz + 0U, // VPOPCNTBZrr + 292U, // VPOPCNTBZrrk + 100U, // VPOPCNTBZrrkz + 0U, // VPOPCNTDZ128rm + 9U, // VPOPCNTDZ128rmb + 7108U, // VPOPCNTDZ128rmbk + 6212U, // VPOPCNTDZ128rmbkz + 676U, // VPOPCNTDZ128rmk + 516U, // VPOPCNTDZ128rmkz + 0U, // VPOPCNTDZ128rr + 292U, // VPOPCNTDZ128rrk + 100U, // VPOPCNTDZ128rrkz + 0U, // VPOPCNTDZ256rm + 10U, // VPOPCNTDZ256rmb + 9156U, // VPOPCNTDZ256rmbk + 8260U, // VPOPCNTDZ256rmbkz + 708U, // VPOPCNTDZ256rmk + 484U, // VPOPCNTDZ256rmkz + 0U, // VPOPCNTDZ256rr + 292U, // VPOPCNTDZ256rrk + 100U, // VPOPCNTDZ256rrkz + 0U, // VPOPCNTDZrm + 10U, // VPOPCNTDZrmb + 11204U, // VPOPCNTDZrmbk + 10308U, // VPOPCNTDZrmbkz + 996U, // VPOPCNTDZrmk + 548U, // VPOPCNTDZrmkz + 0U, // VPOPCNTDZrr + 292U, // VPOPCNTDZrrk + 100U, // VPOPCNTDZrrkz + 0U, // VPOPCNTQZ128rm + 9U, // VPOPCNTQZ128rmb + 4740U, // VPOPCNTQZ128rmbk + 4228U, // VPOPCNTQZ128rmbkz + 676U, // VPOPCNTQZ128rmk + 516U, // VPOPCNTQZ128rmkz + 0U, // VPOPCNTQZ128rr + 292U, // VPOPCNTQZ128rrk + 100U, // VPOPCNTQZ128rrkz + 0U, // VPOPCNTQZ256rm + 9U, // VPOPCNTQZ256rmb + 6788U, // VPOPCNTQZ256rmbk + 6276U, // VPOPCNTQZ256rmbkz + 708U, // VPOPCNTQZ256rmk + 484U, // VPOPCNTQZ256rmkz + 0U, // VPOPCNTQZ256rr + 292U, // VPOPCNTQZ256rrk + 100U, // VPOPCNTQZ256rrkz + 0U, // VPOPCNTQZrm + 10U, // VPOPCNTQZrmb + 8836U, // VPOPCNTQZrmbk + 8324U, // VPOPCNTQZrmbkz + 996U, // VPOPCNTQZrmk + 548U, // VPOPCNTQZrmkz + 0U, // VPOPCNTQZrr + 292U, // VPOPCNTQZrrk + 100U, // VPOPCNTQZrrkz + 0U, // VPOPCNTWZ128rm + 676U, // VPOPCNTWZ128rmk + 516U, // VPOPCNTWZ128rmkz + 0U, // VPOPCNTWZ128rr + 292U, // VPOPCNTWZ128rrk + 100U, // VPOPCNTWZ128rrkz + 0U, // VPOPCNTWZ256rm + 708U, // VPOPCNTWZ256rmk + 484U, // VPOPCNTWZ256rmkz + 0U, // VPOPCNTWZ256rr + 292U, // VPOPCNTWZ256rrk + 100U, // VPOPCNTWZ256rrkz + 0U, // VPOPCNTWZrm + 996U, // VPOPCNTWZrmk + 548U, // VPOPCNTWZrmkz + 0U, // VPOPCNTWZrr + 292U, // VPOPCNTWZrrk + 100U, // VPOPCNTWZrrkz + 512U, // VPORDZ128rm + 6208U, // VPORDZ128rmb + 2591012U, // VPORDZ128rmbk + 2623588U, // VPORDZ128rmbkz + 559396U, // VPORDZ128rmk + 591972U, // VPORDZ128rmkz + 96U, // VPORDZ128rr + 166180U, // VPORDZ128rrk + 198756U, // VPORDZ128rrkz + 480U, // VPORDZ256rm + 8256U, // VPORDZ256rmb + 3639588U, // VPORDZ256rmbk + 3672164U, // VPORDZ256rmbkz + 657700U, // VPORDZ256rmk + 690276U, // VPORDZ256rmkz + 96U, // VPORDZ256rr + 166180U, // VPORDZ256rrk + 198756U, // VPORDZ256rrkz + 544U, // VPORDZrm + 10304U, // VPORDZrmb + 5736740U, // VPORDZrmbk + 5769316U, // VPORDZrmbkz + 723236U, // VPORDZrmk + 755812U, // VPORDZrmkz + 96U, // VPORDZrr + 166180U, // VPORDZrrk + 198756U, // VPORDZrrkz + 512U, // VPORQZ128rm + 4224U, // VPORQZ128rmb + 1837348U, // VPORQZ128rmbk + 1869924U, // VPORQZ128rmbkz + 559396U, // VPORQZ128rmk + 591972U, // VPORQZ128rmkz + 96U, // VPORQZ128rr + 166180U, // VPORQZ128rrk + 198756U, // VPORQZ128rrkz + 480U, // VPORQZ256rm + 6272U, // VPORQZ256rmb + 2885924U, // VPORQZ256rmbk + 2918500U, // VPORQZ256rmbkz + 657700U, // VPORQZ256rmk + 690276U, // VPORQZ256rmkz + 96U, // VPORQZ256rr + 166180U, // VPORQZ256rrk + 198756U, // VPORQZ256rrkz + 544U, // VPORQZrm + 8320U, // VPORQZrmb + 3934500U, // VPORQZrmbk + 3967076U, // VPORQZrmbkz + 723236U, // VPORQZrmk + 755812U, // VPORQZrmkz + 96U, // VPORQZrr + 166180U, // VPORQZrrk + 198756U, // VPORQZrrkz + 480U, // VPORYrm + 96U, // VPORYrr + 512U, // VPORrm + 96U, // VPORrr + 854528U, // VPPERMrmr + 591968U, // VPPERMrrm + 198752U, // VPPERMrrr + 198752U, // VPPERMrrr_REV + 12U, // VPROLDZ128mbi + 930756U, // VPROLDZ128mbik + 471108U, // VPROLDZ128mbikz + 0U, // VPROLDZ128mi + 920228U, // VPROLDZ128mik + 461316U, // VPROLDZ128mikz + 32U, // VPROLDZ128ri + 2340U, // VPROLDZ128rik + 624740U, // VPROLDZ128rikz + 12U, // VPROLDZ256mbi + 932804U, // VPROLDZ256mbik + 473156U, // VPROLDZ256mbikz + 0U, // VPROLDZ256mi + 920260U, // VPROLDZ256mik + 461284U, // VPROLDZ256mikz + 32U, // VPROLDZ256ri + 2340U, // VPROLDZ256rik + 624740U, // VPROLDZ256rikz + 13U, // VPROLDZmbi + 934852U, // VPROLDZmbik + 475204U, // VPROLDZmbikz + 0U, // VPROLDZmi + 920548U, // VPROLDZmik + 461348U, // VPROLDZmikz + 32U, // VPROLDZri + 2340U, // VPROLDZrik + 624740U, // VPROLDZrikz + 11U, // VPROLQZ128mbi + 936580U, // VPROLQZ128mbik + 477316U, // VPROLQZ128mbikz + 0U, // VPROLQZ128mi + 920228U, // VPROLQZ128mik + 461316U, // VPROLQZ128mikz + 32U, // VPROLQZ128ri + 2340U, // VPROLQZ128rik + 624740U, // VPROLQZ128rikz + 12U, // VPROLQZ256mbi + 930436U, // VPROLQZ256mbik + 471172U, // VPROLQZ256mbikz + 0U, // VPROLQZ256mi + 920260U, // VPROLQZ256mik + 461284U, // VPROLQZ256mikz + 32U, // VPROLQZ256ri + 2340U, // VPROLQZ256rik + 624740U, // VPROLQZ256rikz + 12U, // VPROLQZmbi + 932484U, // VPROLQZmbik + 473220U, // VPROLQZmbikz + 0U, // VPROLQZmi + 920548U, // VPROLQZmik + 461348U, // VPROLQZmikz + 32U, // VPROLQZri + 2340U, // VPROLQZrik + 624740U, // VPROLQZrikz + 512U, // VPROLVDZ128rm + 6208U, // VPROLVDZ128rmb + 2591012U, // VPROLVDZ128rmbk + 2623588U, // VPROLVDZ128rmbkz + 559396U, // VPROLVDZ128rmk + 591972U, // VPROLVDZ128rmkz + 96U, // VPROLVDZ128rr + 166180U, // VPROLVDZ128rrk + 198756U, // VPROLVDZ128rrkz + 480U, // VPROLVDZ256rm + 8256U, // VPROLVDZ256rmb + 3639588U, // VPROLVDZ256rmbk + 3672164U, // VPROLVDZ256rmbkz + 657700U, // VPROLVDZ256rmk + 690276U, // VPROLVDZ256rmkz + 96U, // VPROLVDZ256rr + 166180U, // VPROLVDZ256rrk + 198756U, // VPROLVDZ256rrkz + 544U, // VPROLVDZrm + 10304U, // VPROLVDZrmb + 5736740U, // VPROLVDZrmbk + 5769316U, // VPROLVDZrmbkz + 723236U, // VPROLVDZrmk + 755812U, // VPROLVDZrmkz + 96U, // VPROLVDZrr + 166180U, // VPROLVDZrrk + 198756U, // VPROLVDZrrkz + 512U, // VPROLVQZ128rm + 4224U, // VPROLVQZ128rmb + 1837348U, // VPROLVQZ128rmbk + 1869924U, // VPROLVQZ128rmbkz + 559396U, // VPROLVQZ128rmk + 591972U, // VPROLVQZ128rmkz + 96U, // VPROLVQZ128rr + 166180U, // VPROLVQZ128rrk + 198756U, // VPROLVQZ128rrkz + 480U, // VPROLVQZ256rm + 6272U, // VPROLVQZ256rmb + 2885924U, // VPROLVQZ256rmbk + 2918500U, // VPROLVQZ256rmbkz + 657700U, // VPROLVQZ256rmk + 690276U, // VPROLVQZ256rmkz + 96U, // VPROLVQZ256rr + 166180U, // VPROLVQZ256rrk + 198756U, // VPROLVQZ256rrkz + 544U, // VPROLVQZrm + 8320U, // VPROLVQZrmb + 3934500U, // VPROLVQZrmbk + 3967076U, // VPROLVQZrmbkz + 723236U, // VPROLVQZrmk + 755812U, // VPROLVQZrmkz + 96U, // VPROLVQZrr + 166180U, // VPROLVQZrrk + 198756U, // VPROLVQZrrkz + 12U, // VPRORDZ128mbi + 930756U, // VPRORDZ128mbik + 471108U, // VPRORDZ128mbikz + 0U, // VPRORDZ128mi + 920228U, // VPRORDZ128mik + 461316U, // VPRORDZ128mikz + 32U, // VPRORDZ128ri + 2340U, // VPRORDZ128rik + 624740U, // VPRORDZ128rikz + 12U, // VPRORDZ256mbi + 932804U, // VPRORDZ256mbik + 473156U, // VPRORDZ256mbikz + 0U, // VPRORDZ256mi + 920260U, // VPRORDZ256mik + 461284U, // VPRORDZ256mikz + 32U, // VPRORDZ256ri + 2340U, // VPRORDZ256rik + 624740U, // VPRORDZ256rikz + 13U, // VPRORDZmbi + 934852U, // VPRORDZmbik + 475204U, // VPRORDZmbikz + 0U, // VPRORDZmi + 920548U, // VPRORDZmik + 461348U, // VPRORDZmikz + 32U, // VPRORDZri + 2340U, // VPRORDZrik + 624740U, // VPRORDZrikz + 11U, // VPRORQZ128mbi + 936580U, // VPRORQZ128mbik + 477316U, // VPRORQZ128mbikz + 0U, // VPRORQZ128mi + 920228U, // VPRORQZ128mik + 461316U, // VPRORQZ128mikz + 32U, // VPRORQZ128ri + 2340U, // VPRORQZ128rik + 624740U, // VPRORQZ128rikz + 12U, // VPRORQZ256mbi + 930436U, // VPRORQZ256mbik + 471172U, // VPRORQZ256mbikz + 0U, // VPRORQZ256mi + 920260U, // VPRORQZ256mik + 461284U, // VPRORQZ256mikz + 32U, // VPRORQZ256ri + 2340U, // VPRORQZ256rik + 624740U, // VPRORQZ256rikz + 12U, // VPRORQZmbi + 932484U, // VPRORQZmbik + 473220U, // VPRORQZmbikz + 0U, // VPRORQZmi + 920548U, // VPRORQZmik + 461348U, // VPRORQZmikz + 32U, // VPRORQZri + 2340U, // VPRORQZrik + 624740U, // VPRORQZrikz + 512U, // VPRORVDZ128rm + 6208U, // VPRORVDZ128rmb + 2591012U, // VPRORVDZ128rmbk + 2623588U, // VPRORVDZ128rmbkz + 559396U, // VPRORVDZ128rmk + 591972U, // VPRORVDZ128rmkz + 96U, // VPRORVDZ128rr + 166180U, // VPRORVDZ128rrk + 198756U, // VPRORVDZ128rrkz + 480U, // VPRORVDZ256rm + 8256U, // VPRORVDZ256rmb + 3639588U, // VPRORVDZ256rmbk + 3672164U, // VPRORVDZ256rmbkz + 657700U, // VPRORVDZ256rmk + 690276U, // VPRORVDZ256rmkz + 96U, // VPRORVDZ256rr + 166180U, // VPRORVDZ256rrk + 198756U, // VPRORVDZ256rrkz + 544U, // VPRORVDZrm + 10304U, // VPRORVDZrmb + 5736740U, // VPRORVDZrmbk + 5769316U, // VPRORVDZrmbkz + 723236U, // VPRORVDZrmk + 755812U, // VPRORVDZrmkz + 96U, // VPRORVDZrr + 166180U, // VPRORVDZrrk + 198756U, // VPRORVDZrrkz + 512U, // VPRORVQZ128rm + 4224U, // VPRORVQZ128rmb + 1837348U, // VPRORVQZ128rmbk + 1869924U, // VPRORVQZ128rmbkz + 559396U, // VPRORVQZ128rmk + 591972U, // VPRORVQZ128rmkz + 96U, // VPRORVQZ128rr + 166180U, // VPRORVQZ128rrk + 198756U, // VPRORVQZ128rrkz + 480U, // VPRORVQZ256rm + 6272U, // VPRORVQZ256rmb + 2885924U, // VPRORVQZ256rmbk + 2918500U, // VPRORVQZ256rmbkz + 657700U, // VPRORVQZ256rmk + 690276U, // VPRORVQZ256rmkz + 96U, // VPRORVQZ256rr + 166180U, // VPRORVQZ256rrk + 198756U, // VPRORVQZ256rrkz + 544U, // VPRORVQZrm + 8320U, // VPRORVQZrmb + 3934500U, // VPRORVQZrmbk + 3967076U, // VPRORVQZrmbkz + 723236U, // VPRORVQZrmk + 755812U, // VPRORVQZrmkz + 96U, // VPRORVQZrr + 166180U, // VPRORVQZrrk + 198756U, // VPRORVQZrrkz + 0U, // VPROTBmi + 160U, // VPROTBmr + 32U, // VPROTBri + 512U, // VPROTBrm + 96U, // VPROTBrr + 96U, // VPROTBrr_REV + 0U, // VPROTDmi + 160U, // VPROTDmr + 32U, // VPROTDri + 512U, // VPROTDrm + 96U, // VPROTDrr + 96U, // VPROTDrr_REV + 0U, // VPROTQmi + 160U, // VPROTQmr + 32U, // VPROTQri + 512U, // VPROTQrm + 96U, // VPROTQrr + 96U, // VPROTQrr_REV + 0U, // VPROTWmi + 160U, // VPROTWmr + 32U, // VPROTWri + 512U, // VPROTWrm + 96U, // VPROTWrr + 96U, // VPROTWrr_REV + 480U, // VPSADBWYrm + 96U, // VPSADBWYrr + 512U, // VPSADBWZ128rm + 96U, // VPSADBWZ128rr + 480U, // VPSADBWZ256rm + 96U, // VPSADBWZ256rr + 544U, // VPSADBWZrm + 96U, // VPSADBWZrr + 512U, // VPSADBWrm + 96U, // VPSADBWrr + 0U, // VPSCATTERDDZ128mr + 0U, // VPSCATTERDDZ256mr + 0U, // VPSCATTERDDZmr + 0U, // VPSCATTERDQZ128mr + 0U, // VPSCATTERDQZ256mr + 0U, // VPSCATTERDQZmr + 0U, // VPSCATTERQDZ128mr + 0U, // VPSCATTERQDZ256mr + 0U, // VPSCATTERQDZmr + 0U, // VPSCATTERQQZ128mr + 0U, // VPSCATTERQQZ256mr + 0U, // VPSCATTERQQZmr + 160U, // VPSHABmr + 512U, // VPSHABrm + 96U, // VPSHABrr + 96U, // VPSHABrr_REV + 160U, // VPSHADmr + 512U, // VPSHADrm + 96U, // VPSHADrr + 96U, // VPSHADrr_REV + 160U, // VPSHAQmr + 512U, // VPSHAQrm + 96U, // VPSHAQrr + 96U, // VPSHAQrr_REV + 160U, // VPSHAWmr + 512U, // VPSHAWrm + 96U, // VPSHAWrr + 96U, // VPSHAWrr_REV + 160U, // VPSHLBmr + 512U, // VPSHLBrm + 96U, // VPSHLBrr + 96U, // VPSHLBrr_REV + 471104U, // VPSHLDDZ128rmbi + 40339748U, // VPSHLDDZ128rmbik + 57149540U, // VPSHLDDZ128rmbikz + 461312U, // VPSHLDDZ128rmi + 38308132U, // VPSHLDDZ128rmik + 55117924U, // VPSHLDDZ128rmikz + 624736U, // VPSHLDDZ128rri + 71469348U, // VPSHLDDZ128rrik + 88279140U, // VPSHLDDZ128rrikz + 473152U, // VPSHLDDZ256rmbi + 41388324U, // VPSHLDDZ256rmbik + 58198116U, // VPSHLDDZ256rmbikz + 461280U, // VPSHLDDZ256rmi + 38406436U, // VPSHLDDZ256rmik + 55216228U, // VPSHLDDZ256rmikz + 624736U, // VPSHLDDZ256rri + 71469348U, // VPSHLDDZ256rrik + 88279140U, // VPSHLDDZ256rrikz + 475200U, // VPSHLDDZrmbi + 42436900U, // VPSHLDDZrmbik + 59246692U, // VPSHLDDZrmbikz + 461344U, // VPSHLDDZrmi + 38471972U, // VPSHLDDZrmik + 55281764U, // VPSHLDDZrmikz + 624736U, // VPSHLDDZrri + 71469348U, // VPSHLDDZrrik + 88279140U, // VPSHLDDZrrikz + 477312U, // VPSHLDQZ128rmbi + 43780388U, // VPSHLDQZ128rmbik + 60590180U, // VPSHLDQZ128rmbikz + 461312U, // VPSHLDQZ128rmi + 38308132U, // VPSHLDQZ128rmik + 55117924U, // VPSHLDQZ128rmikz + 624736U, // VPSHLDQZ128rri + 71469348U, // VPSHLDQZ128rrik + 88279140U, // VPSHLDQZ128rrikz + 471168U, // VPSHLDQZ256rmbi + 40634660U, // VPSHLDQZ256rmbik + 57444452U, // VPSHLDQZ256rmbikz + 461280U, // VPSHLDQZ256rmi + 38406436U, // VPSHLDQZ256rmik + 55216228U, // VPSHLDQZ256rmikz + 624736U, // VPSHLDQZ256rri + 71469348U, // VPSHLDQZ256rrik + 88279140U, // VPSHLDQZ256rrikz + 473216U, // VPSHLDQZrmbi + 41683236U, // VPSHLDQZrmbik + 58493028U, // VPSHLDQZrmbikz + 461344U, // VPSHLDQZrmi + 38471972U, // VPSHLDQZrmik + 55281764U, // VPSHLDQZrmikz + 624736U, // VPSHLDQZrri + 71469348U, // VPSHLDQZrrik + 88279140U, // VPSHLDQZrrikz + 672U, // VPSHLDVDZ128m + 7104U, // VPSHLDVDZ128mb + 2591012U, // VPSHLDVDZ128mbk + 2591012U, // VPSHLDVDZ128mbkz + 559396U, // VPSHLDVDZ128mk + 559396U, // VPSHLDVDZ128mkz + 288U, // VPSHLDVDZ128r + 166180U, // VPSHLDVDZ128rk + 166180U, // VPSHLDVDZ128rkz + 704U, // VPSHLDVDZ256m + 9152U, // VPSHLDVDZ256mb + 3639588U, // VPSHLDVDZ256mbk + 3639588U, // VPSHLDVDZ256mbkz + 657700U, // VPSHLDVDZ256mk + 657700U, // VPSHLDVDZ256mkz + 288U, // VPSHLDVDZ256r + 166180U, // VPSHLDVDZ256rk + 166180U, // VPSHLDVDZ256rkz + 992U, // VPSHLDVDZm + 11200U, // VPSHLDVDZmb + 5736740U, // VPSHLDVDZmbk + 5736740U, // VPSHLDVDZmbkz + 723236U, // VPSHLDVDZmk + 723236U, // VPSHLDVDZmkz + 288U, // VPSHLDVDZr + 166180U, // VPSHLDVDZrk + 166180U, // VPSHLDVDZrkz + 672U, // VPSHLDVQZ128m + 4736U, // VPSHLDVQZ128mb + 1837348U, // VPSHLDVQZ128mbk + 1837348U, // VPSHLDVQZ128mbkz + 559396U, // VPSHLDVQZ128mk + 559396U, // VPSHLDVQZ128mkz + 288U, // VPSHLDVQZ128r + 166180U, // VPSHLDVQZ128rk + 166180U, // VPSHLDVQZ128rkz + 704U, // VPSHLDVQZ256m + 6784U, // VPSHLDVQZ256mb + 2885924U, // VPSHLDVQZ256mbk + 2885924U, // VPSHLDVQZ256mbkz + 657700U, // VPSHLDVQZ256mk + 657700U, // VPSHLDVQZ256mkz + 288U, // VPSHLDVQZ256r + 166180U, // VPSHLDVQZ256rk + 166180U, // VPSHLDVQZ256rkz + 992U, // VPSHLDVQZm + 8832U, // VPSHLDVQZmb + 3934500U, // VPSHLDVQZmbk + 3934500U, // VPSHLDVQZmbkz + 723236U, // VPSHLDVQZmk + 723236U, // VPSHLDVQZmkz + 288U, // VPSHLDVQZr + 166180U, // VPSHLDVQZrk + 166180U, // VPSHLDVQZrkz + 672U, // VPSHLDVWZ128m + 559396U, // VPSHLDVWZ128mk + 559396U, // VPSHLDVWZ128mkz + 288U, // VPSHLDVWZ128r + 166180U, // VPSHLDVWZ128rk + 166180U, // VPSHLDVWZ128rkz + 704U, // VPSHLDVWZ256m + 657700U, // VPSHLDVWZ256mk + 657700U, // VPSHLDVWZ256mkz + 288U, // VPSHLDVWZ256r + 166180U, // VPSHLDVWZ256rk + 166180U, // VPSHLDVWZ256rkz + 992U, // VPSHLDVWZm + 723236U, // VPSHLDVWZmk + 723236U, // VPSHLDVWZmkz + 288U, // VPSHLDVWZr + 166180U, // VPSHLDVWZrk + 166180U, // VPSHLDVWZrkz + 461312U, // VPSHLDWZ128rmi + 38308132U, // VPSHLDWZ128rmik + 55117924U, // VPSHLDWZ128rmikz + 624736U, // VPSHLDWZ128rri + 71469348U, // VPSHLDWZ128rrik + 88279140U, // VPSHLDWZ128rrikz + 461280U, // VPSHLDWZ256rmi + 38406436U, // VPSHLDWZ256rmik + 55216228U, // VPSHLDWZ256rmikz + 624736U, // VPSHLDWZ256rri + 71469348U, // VPSHLDWZ256rrik + 88279140U, // VPSHLDWZ256rrikz + 461344U, // VPSHLDWZrmi + 38471972U, // VPSHLDWZrmik + 55281764U, // VPSHLDWZrmikz + 624736U, // VPSHLDWZrri + 71469348U, // VPSHLDWZrrik + 88279140U, // VPSHLDWZrrikz + 160U, // VPSHLDmr + 512U, // VPSHLDrm + 96U, // VPSHLDrr + 96U, // VPSHLDrr_REV + 160U, // VPSHLQmr + 512U, // VPSHLQrm + 96U, // VPSHLQrr + 96U, // VPSHLQrr_REV + 160U, // VPSHLWmr + 512U, // VPSHLWrm + 96U, // VPSHLWrr + 96U, // VPSHLWrr_REV + 471104U, // VPSHRDDZ128rmbi + 40339748U, // VPSHRDDZ128rmbik + 57149540U, // VPSHRDDZ128rmbikz + 461312U, // VPSHRDDZ128rmi + 38308132U, // VPSHRDDZ128rmik + 55117924U, // VPSHRDDZ128rmikz + 624736U, // VPSHRDDZ128rri + 71469348U, // VPSHRDDZ128rrik + 88279140U, // VPSHRDDZ128rrikz + 473152U, // VPSHRDDZ256rmbi + 41388324U, // VPSHRDDZ256rmbik + 58198116U, // VPSHRDDZ256rmbikz + 461280U, // VPSHRDDZ256rmi + 38406436U, // VPSHRDDZ256rmik + 55216228U, // VPSHRDDZ256rmikz + 624736U, // VPSHRDDZ256rri + 71469348U, // VPSHRDDZ256rrik + 88279140U, // VPSHRDDZ256rrikz + 475200U, // VPSHRDDZrmbi + 42436900U, // VPSHRDDZrmbik + 59246692U, // VPSHRDDZrmbikz + 461344U, // VPSHRDDZrmi + 38471972U, // VPSHRDDZrmik + 55281764U, // VPSHRDDZrmikz + 624736U, // VPSHRDDZrri + 71469348U, // VPSHRDDZrrik + 88279140U, // VPSHRDDZrrikz + 477312U, // VPSHRDQZ128rmbi + 43780388U, // VPSHRDQZ128rmbik + 60590180U, // VPSHRDQZ128rmbikz + 461312U, // VPSHRDQZ128rmi + 38308132U, // VPSHRDQZ128rmik + 55117924U, // VPSHRDQZ128rmikz + 624736U, // VPSHRDQZ128rri + 71469348U, // VPSHRDQZ128rrik + 88279140U, // VPSHRDQZ128rrikz + 471168U, // VPSHRDQZ256rmbi + 40634660U, // VPSHRDQZ256rmbik + 57444452U, // VPSHRDQZ256rmbikz + 461280U, // VPSHRDQZ256rmi + 38406436U, // VPSHRDQZ256rmik + 55216228U, // VPSHRDQZ256rmikz + 624736U, // VPSHRDQZ256rri + 71469348U, // VPSHRDQZ256rrik + 88279140U, // VPSHRDQZ256rrikz + 473216U, // VPSHRDQZrmbi + 41683236U, // VPSHRDQZrmbik + 58493028U, // VPSHRDQZrmbikz + 461344U, // VPSHRDQZrmi + 38471972U, // VPSHRDQZrmik + 55281764U, // VPSHRDQZrmikz + 624736U, // VPSHRDQZrri + 71469348U, // VPSHRDQZrrik + 88279140U, // VPSHRDQZrrikz + 672U, // VPSHRDVDZ128m + 7104U, // VPSHRDVDZ128mb + 2591012U, // VPSHRDVDZ128mbk + 2591012U, // VPSHRDVDZ128mbkz + 559396U, // VPSHRDVDZ128mk + 559396U, // VPSHRDVDZ128mkz + 288U, // VPSHRDVDZ128r + 166180U, // VPSHRDVDZ128rk + 166180U, // VPSHRDVDZ128rkz + 704U, // VPSHRDVDZ256m + 9152U, // VPSHRDVDZ256mb + 3639588U, // VPSHRDVDZ256mbk + 3639588U, // VPSHRDVDZ256mbkz + 657700U, // VPSHRDVDZ256mk + 657700U, // VPSHRDVDZ256mkz + 288U, // VPSHRDVDZ256r + 166180U, // VPSHRDVDZ256rk + 166180U, // VPSHRDVDZ256rkz + 992U, // VPSHRDVDZm + 11200U, // VPSHRDVDZmb + 5736740U, // VPSHRDVDZmbk + 5736740U, // VPSHRDVDZmbkz + 723236U, // VPSHRDVDZmk + 723236U, // VPSHRDVDZmkz + 288U, // VPSHRDVDZr + 166180U, // VPSHRDVDZrk + 166180U, // VPSHRDVDZrkz + 672U, // VPSHRDVQZ128m + 4736U, // VPSHRDVQZ128mb + 1837348U, // VPSHRDVQZ128mbk + 1837348U, // VPSHRDVQZ128mbkz + 559396U, // VPSHRDVQZ128mk + 559396U, // VPSHRDVQZ128mkz + 288U, // VPSHRDVQZ128r + 166180U, // VPSHRDVQZ128rk + 166180U, // VPSHRDVQZ128rkz + 704U, // VPSHRDVQZ256m + 6784U, // VPSHRDVQZ256mb + 2885924U, // VPSHRDVQZ256mbk + 2885924U, // VPSHRDVQZ256mbkz + 657700U, // VPSHRDVQZ256mk + 657700U, // VPSHRDVQZ256mkz + 288U, // VPSHRDVQZ256r + 166180U, // VPSHRDVQZ256rk + 166180U, // VPSHRDVQZ256rkz + 992U, // VPSHRDVQZm + 8832U, // VPSHRDVQZmb + 3934500U, // VPSHRDVQZmbk + 3934500U, // VPSHRDVQZmbkz + 723236U, // VPSHRDVQZmk + 723236U, // VPSHRDVQZmkz + 288U, // VPSHRDVQZr + 166180U, // VPSHRDVQZrk + 166180U, // VPSHRDVQZrkz + 672U, // VPSHRDVWZ128m + 559396U, // VPSHRDVWZ128mk + 559396U, // VPSHRDVWZ128mkz + 288U, // VPSHRDVWZ128r + 166180U, // VPSHRDVWZ128rk + 166180U, // VPSHRDVWZ128rkz + 704U, // VPSHRDVWZ256m + 657700U, // VPSHRDVWZ256mk + 657700U, // VPSHRDVWZ256mkz + 288U, // VPSHRDVWZ256r + 166180U, // VPSHRDVWZ256rk + 166180U, // VPSHRDVWZ256rkz + 992U, // VPSHRDVWZm + 723236U, // VPSHRDVWZmk + 723236U, // VPSHRDVWZmkz + 288U, // VPSHRDVWZr + 166180U, // VPSHRDVWZrk + 166180U, // VPSHRDVWZrkz + 461312U, // VPSHRDWZ128rmi + 38308132U, // VPSHRDWZ128rmik + 55117924U, // VPSHRDWZ128rmikz + 624736U, // VPSHRDWZ128rri + 71469348U, // VPSHRDWZ128rrik + 88279140U, // VPSHRDWZ128rrikz + 461280U, // VPSHRDWZ256rmi + 38406436U, // VPSHRDWZ256rmik + 55216228U, // VPSHRDWZ256rmikz + 624736U, // VPSHRDWZ256rri + 71469348U, // VPSHRDWZ256rrik + 88279140U, // VPSHRDWZ256rrikz + 461344U, // VPSHRDWZrmi + 38471972U, // VPSHRDWZrmik + 55281764U, // VPSHRDWZrmikz + 624736U, // VPSHRDWZrri + 71469348U, // VPSHRDWZrrik + 88279140U, // VPSHRDWZrrikz + 512U, // VPSHUFBITQMBZ128rm + 591972U, // VPSHUFBITQMBZ128rmk + 96U, // VPSHUFBITQMBZ128rr + 198756U, // VPSHUFBITQMBZ128rrk + 480U, // VPSHUFBITQMBZ256rm + 690276U, // VPSHUFBITQMBZ256rmk + 96U, // VPSHUFBITQMBZ256rr + 198756U, // VPSHUFBITQMBZ256rrk + 544U, // VPSHUFBITQMBZrm + 755812U, // VPSHUFBITQMBZrmk + 96U, // VPSHUFBITQMBZrr + 198756U, // VPSHUFBITQMBZrrk + 480U, // VPSHUFBYrm + 96U, // VPSHUFBYrr + 512U, // VPSHUFBZ128rm + 559396U, // VPSHUFBZ128rmk + 591972U, // VPSHUFBZ128rmkz + 96U, // VPSHUFBZ128rr + 166180U, // VPSHUFBZ128rrk + 198756U, // VPSHUFBZ128rrkz + 480U, // VPSHUFBZ256rm + 657700U, // VPSHUFBZ256rmk + 690276U, // VPSHUFBZ256rmkz + 96U, // VPSHUFBZ256rr + 166180U, // VPSHUFBZ256rrk + 198756U, // VPSHUFBZ256rrkz + 544U, // VPSHUFBZrm + 723236U, // VPSHUFBZrmk + 755812U, // VPSHUFBZrmkz + 96U, // VPSHUFBZrr + 166180U, // VPSHUFBZrrk + 198756U, // VPSHUFBZrrkz + 512U, // VPSHUFBrm + 96U, // VPSHUFBrr + 0U, // VPSHUFDYmi + 32U, // VPSHUFDYri + 12U, // VPSHUFDZ128mbi + 930756U, // VPSHUFDZ128mbik + 471108U, // VPSHUFDZ128mbikz + 0U, // VPSHUFDZ128mi + 920228U, // VPSHUFDZ128mik + 461316U, // VPSHUFDZ128mikz + 32U, // VPSHUFDZ128ri + 2340U, // VPSHUFDZ128rik + 624740U, // VPSHUFDZ128rikz + 12U, // VPSHUFDZ256mbi + 932804U, // VPSHUFDZ256mbik + 473156U, // VPSHUFDZ256mbikz + 0U, // VPSHUFDZ256mi + 920260U, // VPSHUFDZ256mik + 461284U, // VPSHUFDZ256mikz + 32U, // VPSHUFDZ256ri + 2340U, // VPSHUFDZ256rik + 624740U, // VPSHUFDZ256rikz + 13U, // VPSHUFDZmbi + 934852U, // VPSHUFDZmbik + 475204U, // VPSHUFDZmbikz + 0U, // VPSHUFDZmi + 920548U, // VPSHUFDZmik + 461348U, // VPSHUFDZmikz + 32U, // VPSHUFDZri + 2340U, // VPSHUFDZrik + 624740U, // VPSHUFDZrikz + 0U, // VPSHUFDmi + 32U, // VPSHUFDri + 0U, // VPSHUFHWYmi + 32U, // VPSHUFHWYri + 0U, // VPSHUFHWZ128mi + 920228U, // VPSHUFHWZ128mik + 461316U, // VPSHUFHWZ128mikz + 32U, // VPSHUFHWZ128ri + 2340U, // VPSHUFHWZ128rik + 624740U, // VPSHUFHWZ128rikz + 0U, // VPSHUFHWZ256mi + 920260U, // VPSHUFHWZ256mik + 461284U, // VPSHUFHWZ256mikz + 32U, // VPSHUFHWZ256ri + 2340U, // VPSHUFHWZ256rik + 624740U, // VPSHUFHWZ256rikz + 0U, // VPSHUFHWZmi + 920548U, // VPSHUFHWZmik + 461348U, // VPSHUFHWZmikz + 32U, // VPSHUFHWZri + 2340U, // VPSHUFHWZrik + 624740U, // VPSHUFHWZrikz + 0U, // VPSHUFHWmi + 32U, // VPSHUFHWri + 0U, // VPSHUFLWYmi + 32U, // VPSHUFLWYri + 0U, // VPSHUFLWZ128mi + 920228U, // VPSHUFLWZ128mik + 461316U, // VPSHUFLWZ128mikz + 32U, // VPSHUFLWZ128ri + 2340U, // VPSHUFLWZ128rik + 624740U, // VPSHUFLWZ128rikz + 0U, // VPSHUFLWZ256mi + 920260U, // VPSHUFLWZ256mik + 461284U, // VPSHUFLWZ256mikz + 32U, // VPSHUFLWZ256ri + 2340U, // VPSHUFLWZ256rik + 624740U, // VPSHUFLWZ256rikz + 0U, // VPSHUFLWZmi + 920548U, // VPSHUFLWZmik + 461348U, // VPSHUFLWZmikz + 32U, // VPSHUFLWZri + 2340U, // VPSHUFLWZrik + 624740U, // VPSHUFLWZrikz + 0U, // VPSHUFLWmi + 32U, // VPSHUFLWri + 480U, // VPSIGNBYrm + 96U, // VPSIGNBYrr + 512U, // VPSIGNBrm + 96U, // VPSIGNBrr + 480U, // VPSIGNDYrm + 96U, // VPSIGNDYrr + 512U, // VPSIGNDrm + 96U, // VPSIGNDrr + 480U, // VPSIGNWYrm + 96U, // VPSIGNWYrr + 512U, // VPSIGNWrm + 96U, // VPSIGNWrr + 32U, // VPSLLDQYri + 0U, // VPSLLDQZ128rm + 32U, // VPSLLDQZ128rr + 0U, // VPSLLDQZ256rm + 32U, // VPSLLDQZ256rr + 0U, // VPSLLDQZrm + 32U, // VPSLLDQZrr + 32U, // VPSLLDQri + 32U, // VPSLLDYri + 512U, // VPSLLDYrm + 96U, // VPSLLDYrr + 12U, // VPSLLDZ128mbi + 930756U, // VPSLLDZ128mbik + 471108U, // VPSLLDZ128mbikz + 0U, // VPSLLDZ128mi + 920228U, // VPSLLDZ128mik + 461316U, // VPSLLDZ128mikz + 32U, // VPSLLDZ128ri + 2340U, // VPSLLDZ128rik + 624740U, // VPSLLDZ128rikz + 512U, // VPSLLDZ128rm + 559396U, // VPSLLDZ128rmk + 591972U, // VPSLLDZ128rmkz + 96U, // VPSLLDZ128rr + 166180U, // VPSLLDZ128rrk + 198756U, // VPSLLDZ128rrkz + 12U, // VPSLLDZ256mbi + 932804U, // VPSLLDZ256mbik + 473156U, // VPSLLDZ256mbikz + 0U, // VPSLLDZ256mi + 920260U, // VPSLLDZ256mik + 461284U, // VPSLLDZ256mikz + 32U, // VPSLLDZ256ri + 2340U, // VPSLLDZ256rik + 624740U, // VPSLLDZ256rikz + 512U, // VPSLLDZ256rm + 559396U, // VPSLLDZ256rmk + 591972U, // VPSLLDZ256rmkz + 96U, // VPSLLDZ256rr + 166180U, // VPSLLDZ256rrk + 198756U, // VPSLLDZ256rrkz + 13U, // VPSLLDZmbi + 934852U, // VPSLLDZmbik + 475204U, // VPSLLDZmbikz + 0U, // VPSLLDZmi + 920548U, // VPSLLDZmik + 461348U, // VPSLLDZmikz + 32U, // VPSLLDZri + 2340U, // VPSLLDZrik + 624740U, // VPSLLDZrikz + 512U, // VPSLLDZrm + 559396U, // VPSLLDZrmk + 591972U, // VPSLLDZrmkz + 96U, // VPSLLDZrr + 166180U, // VPSLLDZrrk + 198756U, // VPSLLDZrrkz + 32U, // VPSLLDri + 512U, // VPSLLDrm + 96U, // VPSLLDrr + 32U, // VPSLLQYri + 512U, // VPSLLQYrm + 96U, // VPSLLQYrr + 11U, // VPSLLQZ128mbi + 936580U, // VPSLLQZ128mbik + 477316U, // VPSLLQZ128mbikz + 0U, // VPSLLQZ128mi + 920228U, // VPSLLQZ128mik + 461316U, // VPSLLQZ128mikz + 32U, // VPSLLQZ128ri + 2340U, // VPSLLQZ128rik + 624740U, // VPSLLQZ128rikz + 512U, // VPSLLQZ128rm + 559396U, // VPSLLQZ128rmk + 591972U, // VPSLLQZ128rmkz + 96U, // VPSLLQZ128rr + 166180U, // VPSLLQZ128rrk + 198756U, // VPSLLQZ128rrkz + 12U, // VPSLLQZ256mbi + 930436U, // VPSLLQZ256mbik + 471172U, // VPSLLQZ256mbikz + 0U, // VPSLLQZ256mi + 920260U, // VPSLLQZ256mik + 461284U, // VPSLLQZ256mikz + 32U, // VPSLLQZ256ri + 2340U, // VPSLLQZ256rik + 624740U, // VPSLLQZ256rikz + 512U, // VPSLLQZ256rm + 559396U, // VPSLLQZ256rmk + 591972U, // VPSLLQZ256rmkz + 96U, // VPSLLQZ256rr + 166180U, // VPSLLQZ256rrk + 198756U, // VPSLLQZ256rrkz + 12U, // VPSLLQZmbi + 932484U, // VPSLLQZmbik + 473220U, // VPSLLQZmbikz + 0U, // VPSLLQZmi + 920548U, // VPSLLQZmik + 461348U, // VPSLLQZmikz + 32U, // VPSLLQZri + 2340U, // VPSLLQZrik + 624740U, // VPSLLQZrikz + 512U, // VPSLLQZrm + 559396U, // VPSLLQZrmk + 591972U, // VPSLLQZrmkz + 96U, // VPSLLQZrr + 166180U, // VPSLLQZrrk + 198756U, // VPSLLQZrrkz + 32U, // VPSLLQri + 512U, // VPSLLQrm + 96U, // VPSLLQrr + 480U, // VPSLLVDYrm + 96U, // VPSLLVDYrr + 512U, // VPSLLVDZ128rm + 6208U, // VPSLLVDZ128rmb + 2591012U, // VPSLLVDZ128rmbk + 2623588U, // VPSLLVDZ128rmbkz + 559396U, // VPSLLVDZ128rmk + 591972U, // VPSLLVDZ128rmkz + 96U, // VPSLLVDZ128rr + 166180U, // VPSLLVDZ128rrk + 198756U, // VPSLLVDZ128rrkz + 480U, // VPSLLVDZ256rm + 8256U, // VPSLLVDZ256rmb + 3639588U, // VPSLLVDZ256rmbk + 3672164U, // VPSLLVDZ256rmbkz + 657700U, // VPSLLVDZ256rmk + 690276U, // VPSLLVDZ256rmkz + 96U, // VPSLLVDZ256rr + 166180U, // VPSLLVDZ256rrk + 198756U, // VPSLLVDZ256rrkz + 544U, // VPSLLVDZrm + 10304U, // VPSLLVDZrmb + 5736740U, // VPSLLVDZrmbk + 5769316U, // VPSLLVDZrmbkz + 723236U, // VPSLLVDZrmk + 755812U, // VPSLLVDZrmkz + 96U, // VPSLLVDZrr + 166180U, // VPSLLVDZrrk + 198756U, // VPSLLVDZrrkz + 512U, // VPSLLVDrm + 96U, // VPSLLVDrr + 480U, // VPSLLVQYrm + 96U, // VPSLLVQYrr + 512U, // VPSLLVQZ128rm + 4224U, // VPSLLVQZ128rmb + 1837348U, // VPSLLVQZ128rmbk + 1869924U, // VPSLLVQZ128rmbkz + 559396U, // VPSLLVQZ128rmk + 591972U, // VPSLLVQZ128rmkz + 96U, // VPSLLVQZ128rr + 166180U, // VPSLLVQZ128rrk + 198756U, // VPSLLVQZ128rrkz + 480U, // VPSLLVQZ256rm + 6272U, // VPSLLVQZ256rmb + 2885924U, // VPSLLVQZ256rmbk + 2918500U, // VPSLLVQZ256rmbkz + 657700U, // VPSLLVQZ256rmk + 690276U, // VPSLLVQZ256rmkz + 96U, // VPSLLVQZ256rr + 166180U, // VPSLLVQZ256rrk + 198756U, // VPSLLVQZ256rrkz + 544U, // VPSLLVQZrm + 8320U, // VPSLLVQZrmb + 3934500U, // VPSLLVQZrmbk + 3967076U, // VPSLLVQZrmbkz + 723236U, // VPSLLVQZrmk + 755812U, // VPSLLVQZrmkz + 96U, // VPSLLVQZrr + 166180U, // VPSLLVQZrrk + 198756U, // VPSLLVQZrrkz + 512U, // VPSLLVQrm + 96U, // VPSLLVQrr + 512U, // VPSLLVWZ128rm + 559396U, // VPSLLVWZ128rmk + 591972U, // VPSLLVWZ128rmkz + 96U, // VPSLLVWZ128rr + 166180U, // VPSLLVWZ128rrk + 198756U, // VPSLLVWZ128rrkz + 480U, // VPSLLVWZ256rm + 657700U, // VPSLLVWZ256rmk + 690276U, // VPSLLVWZ256rmkz + 96U, // VPSLLVWZ256rr + 166180U, // VPSLLVWZ256rrk + 198756U, // VPSLLVWZ256rrkz + 544U, // VPSLLVWZrm + 723236U, // VPSLLVWZrmk + 755812U, // VPSLLVWZrmkz + 96U, // VPSLLVWZrr + 166180U, // VPSLLVWZrrk + 198756U, // VPSLLVWZrrkz + 32U, // VPSLLWYri + 512U, // VPSLLWYrm + 96U, // VPSLLWYrr + 0U, // VPSLLWZ128mi + 920228U, // VPSLLWZ128mik + 461316U, // VPSLLWZ128mikz + 32U, // VPSLLWZ128ri + 2340U, // VPSLLWZ128rik + 624740U, // VPSLLWZ128rikz + 512U, // VPSLLWZ128rm + 559396U, // VPSLLWZ128rmk + 591972U, // VPSLLWZ128rmkz + 96U, // VPSLLWZ128rr + 166180U, // VPSLLWZ128rrk + 198756U, // VPSLLWZ128rrkz + 0U, // VPSLLWZ256mi + 920260U, // VPSLLWZ256mik + 461284U, // VPSLLWZ256mikz + 32U, // VPSLLWZ256ri + 2340U, // VPSLLWZ256rik + 624740U, // VPSLLWZ256rikz + 512U, // VPSLLWZ256rm + 559396U, // VPSLLWZ256rmk + 591972U, // VPSLLWZ256rmkz + 96U, // VPSLLWZ256rr + 166180U, // VPSLLWZ256rrk + 198756U, // VPSLLWZ256rrkz + 0U, // VPSLLWZmi + 920548U, // VPSLLWZmik + 461348U, // VPSLLWZmikz + 32U, // VPSLLWZri + 2340U, // VPSLLWZrik + 624740U, // VPSLLWZrikz + 512U, // VPSLLWZrm + 559396U, // VPSLLWZrmk + 591972U, // VPSLLWZrmkz + 96U, // VPSLLWZrr + 166180U, // VPSLLWZrrk + 198756U, // VPSLLWZrrkz + 32U, // VPSLLWri + 512U, // VPSLLWrm + 96U, // VPSLLWrr + 32U, // VPSRADYri + 512U, // VPSRADYrm + 96U, // VPSRADYrr + 12U, // VPSRADZ128mbi + 930756U, // VPSRADZ128mbik + 471108U, // VPSRADZ128mbikz + 0U, // VPSRADZ128mi + 920228U, // VPSRADZ128mik + 461316U, // VPSRADZ128mikz + 32U, // VPSRADZ128ri + 2340U, // VPSRADZ128rik + 624740U, // VPSRADZ128rikz + 512U, // VPSRADZ128rm + 559396U, // VPSRADZ128rmk + 591972U, // VPSRADZ128rmkz + 96U, // VPSRADZ128rr + 166180U, // VPSRADZ128rrk + 198756U, // VPSRADZ128rrkz + 12U, // VPSRADZ256mbi + 932804U, // VPSRADZ256mbik + 473156U, // VPSRADZ256mbikz + 0U, // VPSRADZ256mi + 920260U, // VPSRADZ256mik + 461284U, // VPSRADZ256mikz + 32U, // VPSRADZ256ri + 2340U, // VPSRADZ256rik + 624740U, // VPSRADZ256rikz + 512U, // VPSRADZ256rm + 559396U, // VPSRADZ256rmk + 591972U, // VPSRADZ256rmkz + 96U, // VPSRADZ256rr + 166180U, // VPSRADZ256rrk + 198756U, // VPSRADZ256rrkz + 13U, // VPSRADZmbi + 934852U, // VPSRADZmbik + 475204U, // VPSRADZmbikz + 0U, // VPSRADZmi + 920548U, // VPSRADZmik + 461348U, // VPSRADZmikz + 32U, // VPSRADZri + 2340U, // VPSRADZrik + 624740U, // VPSRADZrikz + 512U, // VPSRADZrm + 559396U, // VPSRADZrmk + 591972U, // VPSRADZrmkz + 96U, // VPSRADZrr + 166180U, // VPSRADZrrk + 198756U, // VPSRADZrrkz + 32U, // VPSRADri + 512U, // VPSRADrm + 96U, // VPSRADrr + 11U, // VPSRAQZ128mbi + 936580U, // VPSRAQZ128mbik + 477316U, // VPSRAQZ128mbikz + 0U, // VPSRAQZ128mi + 920228U, // VPSRAQZ128mik + 461316U, // VPSRAQZ128mikz + 32U, // VPSRAQZ128ri + 2340U, // VPSRAQZ128rik + 624740U, // VPSRAQZ128rikz + 512U, // VPSRAQZ128rm + 559396U, // VPSRAQZ128rmk + 591972U, // VPSRAQZ128rmkz + 96U, // VPSRAQZ128rr + 166180U, // VPSRAQZ128rrk + 198756U, // VPSRAQZ128rrkz + 12U, // VPSRAQZ256mbi + 930436U, // VPSRAQZ256mbik + 471172U, // VPSRAQZ256mbikz + 0U, // VPSRAQZ256mi + 920260U, // VPSRAQZ256mik + 461284U, // VPSRAQZ256mikz + 32U, // VPSRAQZ256ri + 2340U, // VPSRAQZ256rik + 624740U, // VPSRAQZ256rikz + 512U, // VPSRAQZ256rm + 559396U, // VPSRAQZ256rmk + 591972U, // VPSRAQZ256rmkz + 96U, // VPSRAQZ256rr + 166180U, // VPSRAQZ256rrk + 198756U, // VPSRAQZ256rrkz + 12U, // VPSRAQZmbi + 932484U, // VPSRAQZmbik + 473220U, // VPSRAQZmbikz + 0U, // VPSRAQZmi + 920548U, // VPSRAQZmik + 461348U, // VPSRAQZmikz + 32U, // VPSRAQZri + 2340U, // VPSRAQZrik + 624740U, // VPSRAQZrikz + 512U, // VPSRAQZrm + 559396U, // VPSRAQZrmk + 591972U, // VPSRAQZrmkz + 96U, // VPSRAQZrr + 166180U, // VPSRAQZrrk + 198756U, // VPSRAQZrrkz + 480U, // VPSRAVDYrm + 96U, // VPSRAVDYrr + 512U, // VPSRAVDZ128rm + 6208U, // VPSRAVDZ128rmb + 2591012U, // VPSRAVDZ128rmbk + 2623588U, // VPSRAVDZ128rmbkz + 559396U, // VPSRAVDZ128rmk + 591972U, // VPSRAVDZ128rmkz + 96U, // VPSRAVDZ128rr + 166180U, // VPSRAVDZ128rrk + 198756U, // VPSRAVDZ128rrkz + 480U, // VPSRAVDZ256rm + 8256U, // VPSRAVDZ256rmb + 3639588U, // VPSRAVDZ256rmbk + 3672164U, // VPSRAVDZ256rmbkz + 657700U, // VPSRAVDZ256rmk + 690276U, // VPSRAVDZ256rmkz + 96U, // VPSRAVDZ256rr + 166180U, // VPSRAVDZ256rrk + 198756U, // VPSRAVDZ256rrkz + 544U, // VPSRAVDZrm + 10304U, // VPSRAVDZrmb + 5736740U, // VPSRAVDZrmbk + 5769316U, // VPSRAVDZrmbkz + 723236U, // VPSRAVDZrmk + 755812U, // VPSRAVDZrmkz + 96U, // VPSRAVDZrr + 166180U, // VPSRAVDZrrk + 198756U, // VPSRAVDZrrkz + 512U, // VPSRAVDrm + 96U, // VPSRAVDrr + 512U, // VPSRAVQZ128rm + 4224U, // VPSRAVQZ128rmb + 1837348U, // VPSRAVQZ128rmbk + 1869924U, // VPSRAVQZ128rmbkz + 559396U, // VPSRAVQZ128rmk + 591972U, // VPSRAVQZ128rmkz + 96U, // VPSRAVQZ128rr + 166180U, // VPSRAVQZ128rrk + 198756U, // VPSRAVQZ128rrkz + 480U, // VPSRAVQZ256rm + 6272U, // VPSRAVQZ256rmb + 2885924U, // VPSRAVQZ256rmbk + 2918500U, // VPSRAVQZ256rmbkz + 657700U, // VPSRAVQZ256rmk + 690276U, // VPSRAVQZ256rmkz + 96U, // VPSRAVQZ256rr + 166180U, // VPSRAVQZ256rrk + 198756U, // VPSRAVQZ256rrkz + 544U, // VPSRAVQZrm + 8320U, // VPSRAVQZrmb + 3934500U, // VPSRAVQZrmbk + 3967076U, // VPSRAVQZrmbkz + 723236U, // VPSRAVQZrmk + 755812U, // VPSRAVQZrmkz + 96U, // VPSRAVQZrr + 166180U, // VPSRAVQZrrk + 198756U, // VPSRAVQZrrkz + 512U, // VPSRAVWZ128rm + 559396U, // VPSRAVWZ128rmk + 591972U, // VPSRAVWZ128rmkz + 96U, // VPSRAVWZ128rr + 166180U, // VPSRAVWZ128rrk + 198756U, // VPSRAVWZ128rrkz + 480U, // VPSRAVWZ256rm + 657700U, // VPSRAVWZ256rmk + 690276U, // VPSRAVWZ256rmkz + 96U, // VPSRAVWZ256rr + 166180U, // VPSRAVWZ256rrk + 198756U, // VPSRAVWZ256rrkz + 544U, // VPSRAVWZrm + 723236U, // VPSRAVWZrmk + 755812U, // VPSRAVWZrmkz + 96U, // VPSRAVWZrr + 166180U, // VPSRAVWZrrk + 198756U, // VPSRAVWZrrkz + 32U, // VPSRAWYri + 512U, // VPSRAWYrm + 96U, // VPSRAWYrr + 0U, // VPSRAWZ128mi + 920228U, // VPSRAWZ128mik + 461316U, // VPSRAWZ128mikz + 32U, // VPSRAWZ128ri + 2340U, // VPSRAWZ128rik + 624740U, // VPSRAWZ128rikz + 512U, // VPSRAWZ128rm + 559396U, // VPSRAWZ128rmk + 591972U, // VPSRAWZ128rmkz + 96U, // VPSRAWZ128rr + 166180U, // VPSRAWZ128rrk + 198756U, // VPSRAWZ128rrkz + 0U, // VPSRAWZ256mi + 920260U, // VPSRAWZ256mik + 461284U, // VPSRAWZ256mikz + 32U, // VPSRAWZ256ri + 2340U, // VPSRAWZ256rik + 624740U, // VPSRAWZ256rikz + 512U, // VPSRAWZ256rm + 559396U, // VPSRAWZ256rmk + 591972U, // VPSRAWZ256rmkz + 96U, // VPSRAWZ256rr + 166180U, // VPSRAWZ256rrk + 198756U, // VPSRAWZ256rrkz + 0U, // VPSRAWZmi + 920548U, // VPSRAWZmik + 461348U, // VPSRAWZmikz + 32U, // VPSRAWZri + 2340U, // VPSRAWZrik + 624740U, // VPSRAWZrikz + 512U, // VPSRAWZrm + 559396U, // VPSRAWZrmk + 591972U, // VPSRAWZrmkz + 96U, // VPSRAWZrr + 166180U, // VPSRAWZrrk + 198756U, // VPSRAWZrrkz + 32U, // VPSRAWri + 512U, // VPSRAWrm + 96U, // VPSRAWrr + 32U, // VPSRLDQYri + 0U, // VPSRLDQZ128rm + 32U, // VPSRLDQZ128rr + 0U, // VPSRLDQZ256rm + 32U, // VPSRLDQZ256rr + 0U, // VPSRLDQZrm + 32U, // VPSRLDQZrr + 32U, // VPSRLDQri + 32U, // VPSRLDYri + 512U, // VPSRLDYrm + 96U, // VPSRLDYrr + 12U, // VPSRLDZ128mbi + 930756U, // VPSRLDZ128mbik + 471108U, // VPSRLDZ128mbikz + 0U, // VPSRLDZ128mi + 920228U, // VPSRLDZ128mik + 461316U, // VPSRLDZ128mikz + 32U, // VPSRLDZ128ri + 2340U, // VPSRLDZ128rik + 624740U, // VPSRLDZ128rikz + 512U, // VPSRLDZ128rm + 559396U, // VPSRLDZ128rmk + 591972U, // VPSRLDZ128rmkz + 96U, // VPSRLDZ128rr + 166180U, // VPSRLDZ128rrk + 198756U, // VPSRLDZ128rrkz + 12U, // VPSRLDZ256mbi + 932804U, // VPSRLDZ256mbik + 473156U, // VPSRLDZ256mbikz + 0U, // VPSRLDZ256mi + 920260U, // VPSRLDZ256mik + 461284U, // VPSRLDZ256mikz + 32U, // VPSRLDZ256ri + 2340U, // VPSRLDZ256rik + 624740U, // VPSRLDZ256rikz + 512U, // VPSRLDZ256rm + 559396U, // VPSRLDZ256rmk + 591972U, // VPSRLDZ256rmkz + 96U, // VPSRLDZ256rr + 166180U, // VPSRLDZ256rrk + 198756U, // VPSRLDZ256rrkz + 13U, // VPSRLDZmbi + 934852U, // VPSRLDZmbik + 475204U, // VPSRLDZmbikz + 0U, // VPSRLDZmi + 920548U, // VPSRLDZmik + 461348U, // VPSRLDZmikz + 32U, // VPSRLDZri + 2340U, // VPSRLDZrik + 624740U, // VPSRLDZrikz + 512U, // VPSRLDZrm + 559396U, // VPSRLDZrmk + 591972U, // VPSRLDZrmkz + 96U, // VPSRLDZrr + 166180U, // VPSRLDZrrk + 198756U, // VPSRLDZrrkz + 32U, // VPSRLDri + 512U, // VPSRLDrm + 96U, // VPSRLDrr + 32U, // VPSRLQYri + 512U, // VPSRLQYrm + 96U, // VPSRLQYrr + 11U, // VPSRLQZ128mbi + 936580U, // VPSRLQZ128mbik + 477316U, // VPSRLQZ128mbikz + 0U, // VPSRLQZ128mi + 920228U, // VPSRLQZ128mik + 461316U, // VPSRLQZ128mikz + 32U, // VPSRLQZ128ri + 2340U, // VPSRLQZ128rik + 624740U, // VPSRLQZ128rikz + 512U, // VPSRLQZ128rm + 559396U, // VPSRLQZ128rmk + 591972U, // VPSRLQZ128rmkz + 96U, // VPSRLQZ128rr + 166180U, // VPSRLQZ128rrk + 198756U, // VPSRLQZ128rrkz + 12U, // VPSRLQZ256mbi + 930436U, // VPSRLQZ256mbik + 471172U, // VPSRLQZ256mbikz + 0U, // VPSRLQZ256mi + 920260U, // VPSRLQZ256mik + 461284U, // VPSRLQZ256mikz + 32U, // VPSRLQZ256ri + 2340U, // VPSRLQZ256rik + 624740U, // VPSRLQZ256rikz + 512U, // VPSRLQZ256rm + 559396U, // VPSRLQZ256rmk + 591972U, // VPSRLQZ256rmkz + 96U, // VPSRLQZ256rr + 166180U, // VPSRLQZ256rrk + 198756U, // VPSRLQZ256rrkz + 12U, // VPSRLQZmbi + 932484U, // VPSRLQZmbik + 473220U, // VPSRLQZmbikz + 0U, // VPSRLQZmi + 920548U, // VPSRLQZmik + 461348U, // VPSRLQZmikz + 32U, // VPSRLQZri + 2340U, // VPSRLQZrik + 624740U, // VPSRLQZrikz + 512U, // VPSRLQZrm + 559396U, // VPSRLQZrmk + 591972U, // VPSRLQZrmkz + 96U, // VPSRLQZrr + 166180U, // VPSRLQZrrk + 198756U, // VPSRLQZrrkz + 32U, // VPSRLQri + 512U, // VPSRLQrm + 96U, // VPSRLQrr + 480U, // VPSRLVDYrm + 96U, // VPSRLVDYrr + 512U, // VPSRLVDZ128rm + 6208U, // VPSRLVDZ128rmb + 2591012U, // VPSRLVDZ128rmbk + 2623588U, // VPSRLVDZ128rmbkz + 559396U, // VPSRLVDZ128rmk + 591972U, // VPSRLVDZ128rmkz + 96U, // VPSRLVDZ128rr + 166180U, // VPSRLVDZ128rrk + 198756U, // VPSRLVDZ128rrkz + 480U, // VPSRLVDZ256rm + 8256U, // VPSRLVDZ256rmb + 3639588U, // VPSRLVDZ256rmbk + 3672164U, // VPSRLVDZ256rmbkz + 657700U, // VPSRLVDZ256rmk + 690276U, // VPSRLVDZ256rmkz + 96U, // VPSRLVDZ256rr + 166180U, // VPSRLVDZ256rrk + 198756U, // VPSRLVDZ256rrkz + 544U, // VPSRLVDZrm + 10304U, // VPSRLVDZrmb + 5736740U, // VPSRLVDZrmbk + 5769316U, // VPSRLVDZrmbkz + 723236U, // VPSRLVDZrmk + 755812U, // VPSRLVDZrmkz + 96U, // VPSRLVDZrr + 166180U, // VPSRLVDZrrk + 198756U, // VPSRLVDZrrkz + 512U, // VPSRLVDrm + 96U, // VPSRLVDrr + 480U, // VPSRLVQYrm + 96U, // VPSRLVQYrr + 512U, // VPSRLVQZ128rm + 4224U, // VPSRLVQZ128rmb + 1837348U, // VPSRLVQZ128rmbk + 1869924U, // VPSRLVQZ128rmbkz + 559396U, // VPSRLVQZ128rmk + 591972U, // VPSRLVQZ128rmkz + 96U, // VPSRLVQZ128rr + 166180U, // VPSRLVQZ128rrk + 198756U, // VPSRLVQZ128rrkz + 480U, // VPSRLVQZ256rm + 6272U, // VPSRLVQZ256rmb + 2885924U, // VPSRLVQZ256rmbk + 2918500U, // VPSRLVQZ256rmbkz + 657700U, // VPSRLVQZ256rmk + 690276U, // VPSRLVQZ256rmkz + 96U, // VPSRLVQZ256rr + 166180U, // VPSRLVQZ256rrk + 198756U, // VPSRLVQZ256rrkz + 544U, // VPSRLVQZrm + 8320U, // VPSRLVQZrmb + 3934500U, // VPSRLVQZrmbk + 3967076U, // VPSRLVQZrmbkz + 723236U, // VPSRLVQZrmk + 755812U, // VPSRLVQZrmkz + 96U, // VPSRLVQZrr + 166180U, // VPSRLVQZrrk + 198756U, // VPSRLVQZrrkz + 512U, // VPSRLVQrm + 96U, // VPSRLVQrr + 512U, // VPSRLVWZ128rm + 559396U, // VPSRLVWZ128rmk + 591972U, // VPSRLVWZ128rmkz + 96U, // VPSRLVWZ128rr + 166180U, // VPSRLVWZ128rrk + 198756U, // VPSRLVWZ128rrkz + 480U, // VPSRLVWZ256rm + 657700U, // VPSRLVWZ256rmk + 690276U, // VPSRLVWZ256rmkz + 96U, // VPSRLVWZ256rr + 166180U, // VPSRLVWZ256rrk + 198756U, // VPSRLVWZ256rrkz + 544U, // VPSRLVWZrm + 723236U, // VPSRLVWZrmk + 755812U, // VPSRLVWZrmkz + 96U, // VPSRLVWZrr + 166180U, // VPSRLVWZrrk + 198756U, // VPSRLVWZrrkz + 32U, // VPSRLWYri + 512U, // VPSRLWYrm + 96U, // VPSRLWYrr + 0U, // VPSRLWZ128mi + 920228U, // VPSRLWZ128mik + 461316U, // VPSRLWZ128mikz + 32U, // VPSRLWZ128ri + 2340U, // VPSRLWZ128rik + 624740U, // VPSRLWZ128rikz + 512U, // VPSRLWZ128rm + 559396U, // VPSRLWZ128rmk + 591972U, // VPSRLWZ128rmkz + 96U, // VPSRLWZ128rr + 166180U, // VPSRLWZ128rrk + 198756U, // VPSRLWZ128rrkz + 0U, // VPSRLWZ256mi + 920260U, // VPSRLWZ256mik + 461284U, // VPSRLWZ256mikz + 32U, // VPSRLWZ256ri + 2340U, // VPSRLWZ256rik + 624740U, // VPSRLWZ256rikz + 512U, // VPSRLWZ256rm + 559396U, // VPSRLWZ256rmk + 591972U, // VPSRLWZ256rmkz + 96U, // VPSRLWZ256rr + 166180U, // VPSRLWZ256rrk + 198756U, // VPSRLWZ256rrkz + 0U, // VPSRLWZmi + 920548U, // VPSRLWZmik + 461348U, // VPSRLWZmikz + 32U, // VPSRLWZri + 2340U, // VPSRLWZrik + 624740U, // VPSRLWZrikz + 512U, // VPSRLWZrm + 559396U, // VPSRLWZrmk + 591972U, // VPSRLWZrmkz + 96U, // VPSRLWZrr + 166180U, // VPSRLWZrrk + 198756U, // VPSRLWZrrkz + 32U, // VPSRLWri + 512U, // VPSRLWrm + 96U, // VPSRLWrr + 480U, // VPSUBBYrm + 96U, // VPSUBBYrr + 512U, // VPSUBBZ128rm + 559396U, // VPSUBBZ128rmk + 591972U, // VPSUBBZ128rmkz + 96U, // VPSUBBZ128rr + 166180U, // VPSUBBZ128rrk + 198756U, // VPSUBBZ128rrkz + 480U, // VPSUBBZ256rm + 657700U, // VPSUBBZ256rmk + 690276U, // VPSUBBZ256rmkz + 96U, // VPSUBBZ256rr + 166180U, // VPSUBBZ256rrk + 198756U, // VPSUBBZ256rrkz + 544U, // VPSUBBZrm + 723236U, // VPSUBBZrmk + 755812U, // VPSUBBZrmkz + 96U, // VPSUBBZrr + 166180U, // VPSUBBZrrk + 198756U, // VPSUBBZrrkz + 512U, // VPSUBBrm + 96U, // VPSUBBrr + 480U, // VPSUBDYrm + 96U, // VPSUBDYrr + 512U, // VPSUBDZ128rm + 6208U, // VPSUBDZ128rmb + 2591012U, // VPSUBDZ128rmbk + 2623588U, // VPSUBDZ128rmbkz + 559396U, // VPSUBDZ128rmk + 591972U, // VPSUBDZ128rmkz + 96U, // VPSUBDZ128rr + 166180U, // VPSUBDZ128rrk + 198756U, // VPSUBDZ128rrkz + 480U, // VPSUBDZ256rm + 8256U, // VPSUBDZ256rmb + 3639588U, // VPSUBDZ256rmbk + 3672164U, // VPSUBDZ256rmbkz + 657700U, // VPSUBDZ256rmk + 690276U, // VPSUBDZ256rmkz + 96U, // VPSUBDZ256rr + 166180U, // VPSUBDZ256rrk + 198756U, // VPSUBDZ256rrkz + 544U, // VPSUBDZrm + 10304U, // VPSUBDZrmb + 5736740U, // VPSUBDZrmbk + 5769316U, // VPSUBDZrmbkz + 723236U, // VPSUBDZrmk + 755812U, // VPSUBDZrmkz + 96U, // VPSUBDZrr + 166180U, // VPSUBDZrrk + 198756U, // VPSUBDZrrkz + 512U, // VPSUBDrm + 96U, // VPSUBDrr + 480U, // VPSUBQYrm + 96U, // VPSUBQYrr + 512U, // VPSUBQZ128rm + 4224U, // VPSUBQZ128rmb + 1837348U, // VPSUBQZ128rmbk + 1869924U, // VPSUBQZ128rmbkz + 559396U, // VPSUBQZ128rmk + 591972U, // VPSUBQZ128rmkz + 96U, // VPSUBQZ128rr + 166180U, // VPSUBQZ128rrk + 198756U, // VPSUBQZ128rrkz + 480U, // VPSUBQZ256rm + 6272U, // VPSUBQZ256rmb + 2885924U, // VPSUBQZ256rmbk + 2918500U, // VPSUBQZ256rmbkz + 657700U, // VPSUBQZ256rmk + 690276U, // VPSUBQZ256rmkz + 96U, // VPSUBQZ256rr + 166180U, // VPSUBQZ256rrk + 198756U, // VPSUBQZ256rrkz + 544U, // VPSUBQZrm + 8320U, // VPSUBQZrmb + 3934500U, // VPSUBQZrmbk + 3967076U, // VPSUBQZrmbkz + 723236U, // VPSUBQZrmk + 755812U, // VPSUBQZrmkz + 96U, // VPSUBQZrr + 166180U, // VPSUBQZrrk + 198756U, // VPSUBQZrrkz + 512U, // VPSUBQrm + 96U, // VPSUBQrr + 480U, // VPSUBSBYrm + 96U, // VPSUBSBYrr + 512U, // VPSUBSBZ128rm + 559396U, // VPSUBSBZ128rmk + 591972U, // VPSUBSBZ128rmkz + 96U, // VPSUBSBZ128rr + 166180U, // VPSUBSBZ128rrk + 198756U, // VPSUBSBZ128rrkz + 480U, // VPSUBSBZ256rm + 657700U, // VPSUBSBZ256rmk + 690276U, // VPSUBSBZ256rmkz + 96U, // VPSUBSBZ256rr + 166180U, // VPSUBSBZ256rrk + 198756U, // VPSUBSBZ256rrkz + 544U, // VPSUBSBZrm + 723236U, // VPSUBSBZrmk + 755812U, // VPSUBSBZrmkz + 96U, // VPSUBSBZrr + 166180U, // VPSUBSBZrrk + 198756U, // VPSUBSBZrrkz + 512U, // VPSUBSBrm + 96U, // VPSUBSBrr + 480U, // VPSUBSWYrm + 96U, // VPSUBSWYrr + 512U, // VPSUBSWZ128rm + 559396U, // VPSUBSWZ128rmk + 591972U, // VPSUBSWZ128rmkz + 96U, // VPSUBSWZ128rr + 166180U, // VPSUBSWZ128rrk + 198756U, // VPSUBSWZ128rrkz + 480U, // VPSUBSWZ256rm + 657700U, // VPSUBSWZ256rmk + 690276U, // VPSUBSWZ256rmkz + 96U, // VPSUBSWZ256rr + 166180U, // VPSUBSWZ256rrk + 198756U, // VPSUBSWZ256rrkz + 544U, // VPSUBSWZrm + 723236U, // VPSUBSWZrmk + 755812U, // VPSUBSWZrmkz + 96U, // VPSUBSWZrr + 166180U, // VPSUBSWZrrk + 198756U, // VPSUBSWZrrkz + 512U, // VPSUBSWrm + 96U, // VPSUBSWrr + 480U, // VPSUBUSBYrm + 96U, // VPSUBUSBYrr + 512U, // VPSUBUSBZ128rm + 559396U, // VPSUBUSBZ128rmk + 591972U, // VPSUBUSBZ128rmkz + 96U, // VPSUBUSBZ128rr + 166180U, // VPSUBUSBZ128rrk + 198756U, // VPSUBUSBZ128rrkz + 480U, // VPSUBUSBZ256rm + 657700U, // VPSUBUSBZ256rmk + 690276U, // VPSUBUSBZ256rmkz + 96U, // VPSUBUSBZ256rr + 166180U, // VPSUBUSBZ256rrk + 198756U, // VPSUBUSBZ256rrkz + 544U, // VPSUBUSBZrm + 723236U, // VPSUBUSBZrmk + 755812U, // VPSUBUSBZrmkz + 96U, // VPSUBUSBZrr + 166180U, // VPSUBUSBZrrk + 198756U, // VPSUBUSBZrrkz + 512U, // VPSUBUSBrm + 96U, // VPSUBUSBrr + 480U, // VPSUBUSWYrm + 96U, // VPSUBUSWYrr + 512U, // VPSUBUSWZ128rm + 559396U, // VPSUBUSWZ128rmk + 591972U, // VPSUBUSWZ128rmkz + 96U, // VPSUBUSWZ128rr + 166180U, // VPSUBUSWZ128rrk + 198756U, // VPSUBUSWZ128rrkz + 480U, // VPSUBUSWZ256rm + 657700U, // VPSUBUSWZ256rmk + 690276U, // VPSUBUSWZ256rmkz + 96U, // VPSUBUSWZ256rr + 166180U, // VPSUBUSWZ256rrk + 198756U, // VPSUBUSWZ256rrkz + 544U, // VPSUBUSWZrm + 723236U, // VPSUBUSWZrmk + 755812U, // VPSUBUSWZrmkz + 96U, // VPSUBUSWZrr + 166180U, // VPSUBUSWZrrk + 198756U, // VPSUBUSWZrrkz + 512U, // VPSUBUSWrm + 96U, // VPSUBUSWrr + 480U, // VPSUBWYrm + 96U, // VPSUBWYrr + 512U, // VPSUBWZ128rm + 559396U, // VPSUBWZ128rmk + 591972U, // VPSUBWZ128rmkz + 96U, // VPSUBWZ128rr + 166180U, // VPSUBWZ128rrk + 198756U, // VPSUBWZ128rrkz + 480U, // VPSUBWZ256rm + 657700U, // VPSUBWZ256rmk + 690276U, // VPSUBWZ256rmkz + 96U, // VPSUBWZ256rr + 166180U, // VPSUBWZ256rrk + 198756U, // VPSUBWZ256rrkz + 544U, // VPSUBWZrm + 723236U, // VPSUBWZrmk + 755812U, // VPSUBWZrmkz + 96U, // VPSUBWZrr + 166180U, // VPSUBWZrrk + 198756U, // VPSUBWZrrkz + 512U, // VPSUBWrm + 96U, // VPSUBWrr + 930752U, // VPTERNLOGDZ128rmbi + 40339748U, // VPTERNLOGDZ128rmbik + 40339748U, // VPTERNLOGDZ128rmbikz + 920224U, // VPTERNLOGDZ128rmi + 38308132U, // VPTERNLOGDZ128rmik + 38308132U, // VPTERNLOGDZ128rmikz + 2336U, // VPTERNLOGDZ128rri + 71469348U, // VPTERNLOGDZ128rrik + 71469348U, // VPTERNLOGDZ128rrikz + 932800U, // VPTERNLOGDZ256rmbi + 41388324U, // VPTERNLOGDZ256rmbik + 41388324U, // VPTERNLOGDZ256rmbikz + 920256U, // VPTERNLOGDZ256rmi + 38406436U, // VPTERNLOGDZ256rmik + 38406436U, // VPTERNLOGDZ256rmikz + 2336U, // VPTERNLOGDZ256rri + 71469348U, // VPTERNLOGDZ256rrik + 71469348U, // VPTERNLOGDZ256rrikz + 934848U, // VPTERNLOGDZrmbi + 42436900U, // VPTERNLOGDZrmbik + 42436900U, // VPTERNLOGDZrmbikz + 920544U, // VPTERNLOGDZrmi + 38471972U, // VPTERNLOGDZrmik + 38471972U, // VPTERNLOGDZrmikz + 2336U, // VPTERNLOGDZrri + 71469348U, // VPTERNLOGDZrrik + 71469348U, // VPTERNLOGDZrrikz + 936576U, // VPTERNLOGQZ128rmbi + 43780388U, // VPTERNLOGQZ128rmbik + 43780388U, // VPTERNLOGQZ128rmbikz + 920224U, // VPTERNLOGQZ128rmi + 38308132U, // VPTERNLOGQZ128rmik + 38308132U, // VPTERNLOGQZ128rmikz + 2336U, // VPTERNLOGQZ128rri + 71469348U, // VPTERNLOGQZ128rrik + 71469348U, // VPTERNLOGQZ128rrikz + 930432U, // VPTERNLOGQZ256rmbi + 40634660U, // VPTERNLOGQZ256rmbik + 40634660U, // VPTERNLOGQZ256rmbikz + 920256U, // VPTERNLOGQZ256rmi + 38406436U, // VPTERNLOGQZ256rmik + 38406436U, // VPTERNLOGQZ256rmikz + 2336U, // VPTERNLOGQZ256rri + 71469348U, // VPTERNLOGQZ256rrik + 71469348U, // VPTERNLOGQZ256rrikz + 932480U, // VPTERNLOGQZrmbi + 41683236U, // VPTERNLOGQZrmbik + 41683236U, // VPTERNLOGQZrmbikz + 920544U, // VPTERNLOGQZrmi + 38471972U, // VPTERNLOGQZrmik + 38471972U, // VPTERNLOGQZrmikz + 2336U, // VPTERNLOGQZrri + 71469348U, // VPTERNLOGQZrrik + 71469348U, // VPTERNLOGQZrrikz + 512U, // VPTESTMBZ128rm + 591972U, // VPTESTMBZ128rmk + 96U, // VPTESTMBZ128rr + 198756U, // VPTESTMBZ128rrk + 480U, // VPTESTMBZ256rm + 690276U, // VPTESTMBZ256rmk + 96U, // VPTESTMBZ256rr + 198756U, // VPTESTMBZ256rrk + 544U, // VPTESTMBZrm + 755812U, // VPTESTMBZrmk + 96U, // VPTESTMBZrr + 198756U, // VPTESTMBZrrk + 512U, // VPTESTMDZ128rm + 6208U, // VPTESTMDZ128rmb + 2623588U, // VPTESTMDZ128rmbk + 591972U, // VPTESTMDZ128rmk + 96U, // VPTESTMDZ128rr + 198756U, // VPTESTMDZ128rrk + 480U, // VPTESTMDZ256rm + 8256U, // VPTESTMDZ256rmb + 3672164U, // VPTESTMDZ256rmbk + 690276U, // VPTESTMDZ256rmk + 96U, // VPTESTMDZ256rr + 198756U, // VPTESTMDZ256rrk + 544U, // VPTESTMDZrm + 10304U, // VPTESTMDZrmb + 5769316U, // VPTESTMDZrmbk + 755812U, // VPTESTMDZrmk + 96U, // VPTESTMDZrr + 198756U, // VPTESTMDZrrk + 512U, // VPTESTMQZ128rm + 4224U, // VPTESTMQZ128rmb + 1869924U, // VPTESTMQZ128rmbk + 591972U, // VPTESTMQZ128rmk + 96U, // VPTESTMQZ128rr + 198756U, // VPTESTMQZ128rrk + 480U, // VPTESTMQZ256rm + 6272U, // VPTESTMQZ256rmb + 2918500U, // VPTESTMQZ256rmbk + 690276U, // VPTESTMQZ256rmk + 96U, // VPTESTMQZ256rr + 198756U, // VPTESTMQZ256rrk + 544U, // VPTESTMQZrm + 8320U, // VPTESTMQZrmb + 3967076U, // VPTESTMQZrmbk + 755812U, // VPTESTMQZrmk + 96U, // VPTESTMQZrr + 198756U, // VPTESTMQZrrk + 512U, // VPTESTMWZ128rm + 591972U, // VPTESTMWZ128rmk + 96U, // VPTESTMWZ128rr + 198756U, // VPTESTMWZ128rrk + 480U, // VPTESTMWZ256rm + 690276U, // VPTESTMWZ256rmk + 96U, // VPTESTMWZ256rr + 198756U, // VPTESTMWZ256rrk + 544U, // VPTESTMWZrm + 755812U, // VPTESTMWZrmk + 96U, // VPTESTMWZrr + 198756U, // VPTESTMWZrrk + 512U, // VPTESTNMBZ128rm + 591972U, // VPTESTNMBZ128rmk + 96U, // VPTESTNMBZ128rr + 198756U, // VPTESTNMBZ128rrk + 480U, // VPTESTNMBZ256rm + 690276U, // VPTESTNMBZ256rmk + 96U, // VPTESTNMBZ256rr + 198756U, // VPTESTNMBZ256rrk + 544U, // VPTESTNMBZrm + 755812U, // VPTESTNMBZrmk + 96U, // VPTESTNMBZrr + 198756U, // VPTESTNMBZrrk + 512U, // VPTESTNMDZ128rm + 6208U, // VPTESTNMDZ128rmb + 2623588U, // VPTESTNMDZ128rmbk + 591972U, // VPTESTNMDZ128rmk + 96U, // VPTESTNMDZ128rr + 198756U, // VPTESTNMDZ128rrk + 480U, // VPTESTNMDZ256rm + 8256U, // VPTESTNMDZ256rmb + 3672164U, // VPTESTNMDZ256rmbk + 690276U, // VPTESTNMDZ256rmk + 96U, // VPTESTNMDZ256rr + 198756U, // VPTESTNMDZ256rrk + 544U, // VPTESTNMDZrm + 10304U, // VPTESTNMDZrmb + 5769316U, // VPTESTNMDZrmbk + 755812U, // VPTESTNMDZrmk + 96U, // VPTESTNMDZrr + 198756U, // VPTESTNMDZrrk + 512U, // VPTESTNMQZ128rm + 4224U, // VPTESTNMQZ128rmb + 1869924U, // VPTESTNMQZ128rmbk + 591972U, // VPTESTNMQZ128rmk + 96U, // VPTESTNMQZ128rr + 198756U, // VPTESTNMQZ128rrk + 480U, // VPTESTNMQZ256rm + 6272U, // VPTESTNMQZ256rmb + 2918500U, // VPTESTNMQZ256rmbk + 690276U, // VPTESTNMQZ256rmk + 96U, // VPTESTNMQZ256rr + 198756U, // VPTESTNMQZ256rrk + 544U, // VPTESTNMQZrm + 8320U, // VPTESTNMQZrmb + 3967076U, // VPTESTNMQZrmbk + 755812U, // VPTESTNMQZrmk + 96U, // VPTESTNMQZrr + 198756U, // VPTESTNMQZrrk + 512U, // VPTESTNMWZ128rm + 591972U, // VPTESTNMWZ128rmk + 96U, // VPTESTNMWZ128rr + 198756U, // VPTESTNMWZ128rrk + 480U, // VPTESTNMWZ256rm + 690276U, // VPTESTNMWZ256rmk + 96U, // VPTESTNMWZ256rr + 198756U, // VPTESTNMWZ256rrk + 544U, // VPTESTNMWZrm + 755812U, // VPTESTNMWZrmk + 96U, // VPTESTNMWZrr + 198756U, // VPTESTNMWZrrk + 0U, // VPTESTYrm + 0U, // VPTESTYrr + 0U, // VPTESTrm + 0U, // VPTESTrr + 480U, // VPUNPCKHBWYrm + 96U, // VPUNPCKHBWYrr + 512U, // VPUNPCKHBWZ128rm + 559396U, // VPUNPCKHBWZ128rmk + 591972U, // VPUNPCKHBWZ128rmkz + 96U, // VPUNPCKHBWZ128rr + 166180U, // VPUNPCKHBWZ128rrk + 198756U, // VPUNPCKHBWZ128rrkz + 480U, // VPUNPCKHBWZ256rm + 657700U, // VPUNPCKHBWZ256rmk + 690276U, // VPUNPCKHBWZ256rmkz + 96U, // VPUNPCKHBWZ256rr + 166180U, // VPUNPCKHBWZ256rrk + 198756U, // VPUNPCKHBWZ256rrkz + 544U, // VPUNPCKHBWZrm + 723236U, // VPUNPCKHBWZrmk + 755812U, // VPUNPCKHBWZrmkz + 96U, // VPUNPCKHBWZrr + 166180U, // VPUNPCKHBWZrrk + 198756U, // VPUNPCKHBWZrrkz + 512U, // VPUNPCKHBWrm + 96U, // VPUNPCKHBWrr + 480U, // VPUNPCKHDQYrm + 96U, // VPUNPCKHDQYrr + 512U, // VPUNPCKHDQZ128rm + 6208U, // VPUNPCKHDQZ128rmb + 2591012U, // VPUNPCKHDQZ128rmbk + 2623588U, // VPUNPCKHDQZ128rmbkz + 559396U, // VPUNPCKHDQZ128rmk + 591972U, // VPUNPCKHDQZ128rmkz + 96U, // VPUNPCKHDQZ128rr + 166180U, // VPUNPCKHDQZ128rrk + 198756U, // VPUNPCKHDQZ128rrkz + 480U, // VPUNPCKHDQZ256rm + 8256U, // VPUNPCKHDQZ256rmb + 3639588U, // VPUNPCKHDQZ256rmbk + 3672164U, // VPUNPCKHDQZ256rmbkz + 657700U, // VPUNPCKHDQZ256rmk + 690276U, // VPUNPCKHDQZ256rmkz + 96U, // VPUNPCKHDQZ256rr + 166180U, // VPUNPCKHDQZ256rrk + 198756U, // VPUNPCKHDQZ256rrkz + 544U, // VPUNPCKHDQZrm + 10304U, // VPUNPCKHDQZrmb + 5736740U, // VPUNPCKHDQZrmbk + 5769316U, // VPUNPCKHDQZrmbkz + 723236U, // VPUNPCKHDQZrmk + 755812U, // VPUNPCKHDQZrmkz + 96U, // VPUNPCKHDQZrr + 166180U, // VPUNPCKHDQZrrk + 198756U, // VPUNPCKHDQZrrkz + 512U, // VPUNPCKHDQrm + 96U, // VPUNPCKHDQrr + 480U, // VPUNPCKHQDQYrm + 96U, // VPUNPCKHQDQYrr + 512U, // VPUNPCKHQDQZ128rm + 4224U, // VPUNPCKHQDQZ128rmb + 1837348U, // VPUNPCKHQDQZ128rmbk + 1869924U, // VPUNPCKHQDQZ128rmbkz + 559396U, // VPUNPCKHQDQZ128rmk + 591972U, // VPUNPCKHQDQZ128rmkz + 96U, // VPUNPCKHQDQZ128rr + 166180U, // VPUNPCKHQDQZ128rrk + 198756U, // VPUNPCKHQDQZ128rrkz + 480U, // VPUNPCKHQDQZ256rm + 6272U, // VPUNPCKHQDQZ256rmb + 2885924U, // VPUNPCKHQDQZ256rmbk + 2918500U, // VPUNPCKHQDQZ256rmbkz + 657700U, // VPUNPCKHQDQZ256rmk + 690276U, // VPUNPCKHQDQZ256rmkz + 96U, // VPUNPCKHQDQZ256rr + 166180U, // VPUNPCKHQDQZ256rrk + 198756U, // VPUNPCKHQDQZ256rrkz + 544U, // VPUNPCKHQDQZrm + 8320U, // VPUNPCKHQDQZrmb + 3934500U, // VPUNPCKHQDQZrmbk + 3967076U, // VPUNPCKHQDQZrmbkz + 723236U, // VPUNPCKHQDQZrmk + 755812U, // VPUNPCKHQDQZrmkz + 96U, // VPUNPCKHQDQZrr + 166180U, // VPUNPCKHQDQZrrk + 198756U, // VPUNPCKHQDQZrrkz + 512U, // VPUNPCKHQDQrm + 96U, // VPUNPCKHQDQrr + 480U, // VPUNPCKHWDYrm + 96U, // VPUNPCKHWDYrr + 512U, // VPUNPCKHWDZ128rm + 559396U, // VPUNPCKHWDZ128rmk + 591972U, // VPUNPCKHWDZ128rmkz + 96U, // VPUNPCKHWDZ128rr + 166180U, // VPUNPCKHWDZ128rrk + 198756U, // VPUNPCKHWDZ128rrkz + 480U, // VPUNPCKHWDZ256rm + 657700U, // VPUNPCKHWDZ256rmk + 690276U, // VPUNPCKHWDZ256rmkz + 96U, // VPUNPCKHWDZ256rr + 166180U, // VPUNPCKHWDZ256rrk + 198756U, // VPUNPCKHWDZ256rrkz + 544U, // VPUNPCKHWDZrm + 723236U, // VPUNPCKHWDZrmk + 755812U, // VPUNPCKHWDZrmkz + 96U, // VPUNPCKHWDZrr + 166180U, // VPUNPCKHWDZrrk + 198756U, // VPUNPCKHWDZrrkz + 512U, // VPUNPCKHWDrm + 96U, // VPUNPCKHWDrr + 480U, // VPUNPCKLBWYrm + 96U, // VPUNPCKLBWYrr + 512U, // VPUNPCKLBWZ128rm + 559396U, // VPUNPCKLBWZ128rmk + 591972U, // VPUNPCKLBWZ128rmkz + 96U, // VPUNPCKLBWZ128rr + 166180U, // VPUNPCKLBWZ128rrk + 198756U, // VPUNPCKLBWZ128rrkz + 480U, // VPUNPCKLBWZ256rm + 657700U, // VPUNPCKLBWZ256rmk + 690276U, // VPUNPCKLBWZ256rmkz + 96U, // VPUNPCKLBWZ256rr + 166180U, // VPUNPCKLBWZ256rrk + 198756U, // VPUNPCKLBWZ256rrkz + 544U, // VPUNPCKLBWZrm + 723236U, // VPUNPCKLBWZrmk + 755812U, // VPUNPCKLBWZrmkz + 96U, // VPUNPCKLBWZrr + 166180U, // VPUNPCKLBWZrrk + 198756U, // VPUNPCKLBWZrrkz + 512U, // VPUNPCKLBWrm + 96U, // VPUNPCKLBWrr + 480U, // VPUNPCKLDQYrm + 96U, // VPUNPCKLDQYrr + 512U, // VPUNPCKLDQZ128rm + 6208U, // VPUNPCKLDQZ128rmb + 2591012U, // VPUNPCKLDQZ128rmbk + 2623588U, // VPUNPCKLDQZ128rmbkz + 559396U, // VPUNPCKLDQZ128rmk + 591972U, // VPUNPCKLDQZ128rmkz + 96U, // VPUNPCKLDQZ128rr + 166180U, // VPUNPCKLDQZ128rrk + 198756U, // VPUNPCKLDQZ128rrkz + 480U, // VPUNPCKLDQZ256rm + 8256U, // VPUNPCKLDQZ256rmb + 3639588U, // VPUNPCKLDQZ256rmbk + 3672164U, // VPUNPCKLDQZ256rmbkz + 657700U, // VPUNPCKLDQZ256rmk + 690276U, // VPUNPCKLDQZ256rmkz + 96U, // VPUNPCKLDQZ256rr + 166180U, // VPUNPCKLDQZ256rrk + 198756U, // VPUNPCKLDQZ256rrkz + 544U, // VPUNPCKLDQZrm + 10304U, // VPUNPCKLDQZrmb + 5736740U, // VPUNPCKLDQZrmbk + 5769316U, // VPUNPCKLDQZrmbkz + 723236U, // VPUNPCKLDQZrmk + 755812U, // VPUNPCKLDQZrmkz + 96U, // VPUNPCKLDQZrr + 166180U, // VPUNPCKLDQZrrk + 198756U, // VPUNPCKLDQZrrkz + 512U, // VPUNPCKLDQrm + 96U, // VPUNPCKLDQrr + 480U, // VPUNPCKLQDQYrm + 96U, // VPUNPCKLQDQYrr + 512U, // VPUNPCKLQDQZ128rm + 4224U, // VPUNPCKLQDQZ128rmb + 1837348U, // VPUNPCKLQDQZ128rmbk + 1869924U, // VPUNPCKLQDQZ128rmbkz + 559396U, // VPUNPCKLQDQZ128rmk + 591972U, // VPUNPCKLQDQZ128rmkz + 96U, // VPUNPCKLQDQZ128rr + 166180U, // VPUNPCKLQDQZ128rrk + 198756U, // VPUNPCKLQDQZ128rrkz + 480U, // VPUNPCKLQDQZ256rm + 6272U, // VPUNPCKLQDQZ256rmb + 2885924U, // VPUNPCKLQDQZ256rmbk + 2918500U, // VPUNPCKLQDQZ256rmbkz + 657700U, // VPUNPCKLQDQZ256rmk + 690276U, // VPUNPCKLQDQZ256rmkz + 96U, // VPUNPCKLQDQZ256rr + 166180U, // VPUNPCKLQDQZ256rrk + 198756U, // VPUNPCKLQDQZ256rrkz + 544U, // VPUNPCKLQDQZrm + 8320U, // VPUNPCKLQDQZrmb + 3934500U, // VPUNPCKLQDQZrmbk + 3967076U, // VPUNPCKLQDQZrmbkz + 723236U, // VPUNPCKLQDQZrmk + 755812U, // VPUNPCKLQDQZrmkz + 96U, // VPUNPCKLQDQZrr + 166180U, // VPUNPCKLQDQZrrk + 198756U, // VPUNPCKLQDQZrrkz + 512U, // VPUNPCKLQDQrm + 96U, // VPUNPCKLQDQrr + 480U, // VPUNPCKLWDYrm + 96U, // VPUNPCKLWDYrr + 512U, // VPUNPCKLWDZ128rm + 559396U, // VPUNPCKLWDZ128rmk + 591972U, // VPUNPCKLWDZ128rmkz + 96U, // VPUNPCKLWDZ128rr + 166180U, // VPUNPCKLWDZ128rrk + 198756U, // VPUNPCKLWDZ128rrkz + 480U, // VPUNPCKLWDZ256rm + 657700U, // VPUNPCKLWDZ256rmk + 690276U, // VPUNPCKLWDZ256rmkz + 96U, // VPUNPCKLWDZ256rr + 166180U, // VPUNPCKLWDZ256rrk + 198756U, // VPUNPCKLWDZ256rrkz + 544U, // VPUNPCKLWDZrm + 723236U, // VPUNPCKLWDZrmk + 755812U, // VPUNPCKLWDZrmkz + 96U, // VPUNPCKLWDZrr + 166180U, // VPUNPCKLWDZrrk + 198756U, // VPUNPCKLWDZrrkz + 512U, // VPUNPCKLWDrm + 96U, // VPUNPCKLWDrr + 512U, // VPXORDZ128rm + 6208U, // VPXORDZ128rmb + 2591012U, // VPXORDZ128rmbk + 2623588U, // VPXORDZ128rmbkz + 559396U, // VPXORDZ128rmk + 591972U, // VPXORDZ128rmkz + 96U, // VPXORDZ128rr + 166180U, // VPXORDZ128rrk + 198756U, // VPXORDZ128rrkz + 480U, // VPXORDZ256rm + 8256U, // VPXORDZ256rmb + 3639588U, // VPXORDZ256rmbk + 3672164U, // VPXORDZ256rmbkz + 657700U, // VPXORDZ256rmk + 690276U, // VPXORDZ256rmkz + 96U, // VPXORDZ256rr + 166180U, // VPXORDZ256rrk + 198756U, // VPXORDZ256rrkz + 544U, // VPXORDZrm + 10304U, // VPXORDZrmb + 5736740U, // VPXORDZrmbk + 5769316U, // VPXORDZrmbkz + 723236U, // VPXORDZrmk + 755812U, // VPXORDZrmkz + 96U, // VPXORDZrr + 166180U, // VPXORDZrrk + 198756U, // VPXORDZrrkz + 512U, // VPXORQZ128rm + 4224U, // VPXORQZ128rmb + 1837348U, // VPXORQZ128rmbk + 1869924U, // VPXORQZ128rmbkz + 559396U, // VPXORQZ128rmk + 591972U, // VPXORQZ128rmkz + 96U, // VPXORQZ128rr + 166180U, // VPXORQZ128rrk + 198756U, // VPXORQZ128rrkz + 480U, // VPXORQZ256rm + 6272U, // VPXORQZ256rmb + 2885924U, // VPXORQZ256rmbk + 2918500U, // VPXORQZ256rmbkz + 657700U, // VPXORQZ256rmk + 690276U, // VPXORQZ256rmkz + 96U, // VPXORQZ256rr + 166180U, // VPXORQZ256rrk + 198756U, // VPXORQZ256rrkz + 544U, // VPXORQZrm + 8320U, // VPXORQZrmb + 3934500U, // VPXORQZrmbk + 3967076U, // VPXORQZrmbkz + 723236U, // VPXORQZrmk + 755812U, // VPXORQZrmkz + 96U, // VPXORQZrr + 166180U, // VPXORQZrrk + 198756U, // VPXORQZrrkz + 480U, // VPXORYrm + 96U, // VPXORYrr + 512U, // VPXORrm + 96U, // VPXORrr + 477568U, // VRANGEPDZ128rmbi + 43059492U, // VRANGEPDZ128rmbik + 59869284U, // VRANGEPDZ128rmbikz + 461152U, // VRANGEPDZ128rmi + 37783844U, // VRANGEPDZ128rmik + 54659172U, // VRANGEPDZ128rmikz + 624736U, // VRANGEPDZ128rri + 71469348U, // VRANGEPDZ128rrik + 88279140U, // VRANGEPDZ128rrikz + 471424U, // VRANGEPDZ256rmbi + 39913764U, // VRANGEPDZ256rmbik + 56723556U, // VRANGEPDZ256rmbikz + 461120U, // VRANGEPDZ256rmi + 37980452U, // VRANGEPDZ256rmik + 54790244U, // VRANGEPDZ256rmikz + 624736U, // VRANGEPDZ256rri + 71469348U, // VRANGEPDZ256rrik + 88279140U, // VRANGEPDZ256rrikz + 473472U, // VRANGEPDZrmbi + 40962340U, // VRANGEPDZrmbik + 57772132U, // VRANGEPDZrmbikz + 461216U, // VRANGEPDZrmi + 38045988U, // VRANGEPDZrmik + 54855780U, // VRANGEPDZrmikz + 624736U, // VRANGEPDZrri + 645216U, // VRANGEPDZrrib + 77760804U, // VRANGEPDZrribk + 94570596U, // VRANGEPDZrribkz + 71469348U, // VRANGEPDZrrik + 88279140U, // VRANGEPDZrrikz + 471488U, // VRANGEPSZ128rmbi + 40241444U, // VRANGEPSZ128rmbik + 57051236U, // VRANGEPSZ128rmbikz + 461152U, // VRANGEPSZ128rmi + 37783844U, // VRANGEPSZ128rmik + 54659172U, // VRANGEPSZ128rmikz + 624736U, // VRANGEPSZ128rri + 71469348U, // VRANGEPSZ128rrik + 88279140U, // VRANGEPSZ128rrikz + 473536U, // VRANGEPSZ256rmbi + 41290020U, // VRANGEPSZ256rmbik + 58099812U, // VRANGEPSZ256rmbikz + 461120U, // VRANGEPSZ256rmi + 37980452U, // VRANGEPSZ256rmik + 54790244U, // VRANGEPSZ256rmikz + 624736U, // VRANGEPSZ256rri + 71469348U, // VRANGEPSZ256rrik + 88279140U, // VRANGEPSZ256rrikz + 475584U, // VRANGEPSZrmbi + 42338596U, // VRANGEPSZrmbik + 59148388U, // VRANGEPSZrmbikz + 461216U, // VRANGEPSZrmi + 38045988U, // VRANGEPSZrmik + 54855780U, // VRANGEPSZrmikz + 624736U, // VRANGEPSZrri + 645216U, // VRANGEPSZrrib + 77760804U, // VRANGEPSZrribk + 94570596U, // VRANGEPSZrribkz + 71469348U, // VRANGEPSZrrik + 88279140U, // VRANGEPSZrrikz + 461184U, // VRANGESDZrmi + 37816612U, // VRANGESDZrmik + 54626404U, // VRANGESDZrmikz + 624736U, // VRANGESDZrri + 645216U, // VRANGESDZrrib + 77760804U, // VRANGESDZrribk + 94570596U, // VRANGESDZrribkz + 71469348U, // VRANGESDZrrik + 88279140U, // VRANGESDZrrikz + 461248U, // VRANGESSZrmi + 38144292U, // VRANGESSZrmik + 54954084U, // VRANGESSZrmikz + 624736U, // VRANGESSZrri + 645216U, // VRANGESSZrrib + 77760804U, // VRANGESSZrribk + 94570596U, // VRANGESSZrribkz + 71469348U, // VRANGESSZrrik + 88279140U, // VRANGESSZrrikz + 0U, // VRCP14PDZ128m + 9U, // VRCP14PDZ128mb + 4676U, // VRCP14PDZ128mbk + 4484U, // VRCP14PDZ128mbkz + 260U, // VRCP14PDZ128mk + 356U, // VRCP14PDZ128mkz + 0U, // VRCP14PDZ128r + 292U, // VRCP14PDZ128rk + 100U, // VRCP14PDZ128rkz + 0U, // VRCP14PDZ256m + 9U, // VRCP14PDZ256mb + 6724U, // VRCP14PDZ256mbk + 6532U, // VRCP14PDZ256mbkz + 612U, // VRCP14PDZ256mk + 324U, // VRCP14PDZ256mkz + 0U, // VRCP14PDZ256r + 292U, // VRCP14PDZ256rk + 100U, // VRCP14PDZ256rkz + 0U, // VRCP14PDZm + 10U, // VRCP14PDZmb + 8772U, // VRCP14PDZmbk + 8580U, // VRCP14PDZmbkz + 1060U, // VRCP14PDZmk + 420U, // VRCP14PDZmkz + 0U, // VRCP14PDZr + 292U, // VRCP14PDZrk + 100U, // VRCP14PDZrkz + 0U, // VRCP14PSZ128m + 9U, // VRCP14PSZ128mb + 6884U, // VRCP14PSZ128mbk + 6596U, // VRCP14PSZ128mbkz + 260U, // VRCP14PSZ128mk + 356U, // VRCP14PSZ128mkz + 0U, // VRCP14PSZ128r + 292U, // VRCP14PSZ128rk + 100U, // VRCP14PSZ128rkz + 0U, // VRCP14PSZ256m + 10U, // VRCP14PSZ256mb + 8932U, // VRCP14PSZ256mbk + 8644U, // VRCP14PSZ256mbkz + 612U, // VRCP14PSZ256mk + 324U, // VRCP14PSZ256mkz + 0U, // VRCP14PSZ256r + 292U, // VRCP14PSZ256rk + 100U, // VRCP14PSZ256rkz + 0U, // VRCP14PSZm + 10U, // VRCP14PSZmb + 10980U, // VRCP14PSZmbk + 10692U, // VRCP14PSZmbkz + 1060U, // VRCP14PSZmk + 420U, // VRCP14PSZmkz + 0U, // VRCP14PSZr + 292U, // VRCP14PSZrk + 100U, // VRCP14PSZrkz + 384U, // VRCP14SDZrm + 67876U, // VRCP14SDZrmk + 100452U, // VRCP14SDZrmkz + 96U, // VRCP14SDZrr + 166180U, // VRCP14SDZrrk + 198756U, // VRCP14SDZrrkz + 448U, // VRCP14SSZrm + 395556U, // VRCP14SSZrmk + 428132U, // VRCP14SSZrmkz + 96U, // VRCP14SSZrr + 166180U, // VRCP14SSZrrk + 198756U, // VRCP14SSZrrkz + 0U, // VRCP28PDZm + 10U, // VRCP28PDZmb + 8772U, // VRCP28PDZmbk + 8580U, // VRCP28PDZmbkz + 1060U, // VRCP28PDZmk + 420U, // VRCP28PDZmkz + 0U, // VRCP28PDZr + 8U, // VRCP28PDZrb + 20772U, // VRCP28PDZrbk + 20580U, // VRCP28PDZrbkz + 292U, // VRCP28PDZrk + 100U, // VRCP28PDZrkz + 0U, // VRCP28PSZm + 10U, // VRCP28PSZmb + 10980U, // VRCP28PSZmbk + 10692U, // VRCP28PSZmbkz + 1060U, // VRCP28PSZmk + 420U, // VRCP28PSZmkz + 0U, // VRCP28PSZr + 8U, // VRCP28PSZrb + 20772U, // VRCP28PSZrbk + 20580U, // VRCP28PSZrbkz + 292U, // VRCP28PSZrk + 100U, // VRCP28PSZrkz + 384U, // VRCP28SDZm + 67876U, // VRCP28SDZmk + 100452U, // VRCP28SDZmkz + 96U, // VRCP28SDZr + 20576U, // VRCP28SDZrb + 11700516U, // VRCP28SDZrbk + 11733092U, // VRCP28SDZrbkz + 166180U, // VRCP28SDZrk + 198756U, // VRCP28SDZrkz + 448U, // VRCP28SSZm + 395556U, // VRCP28SSZmk + 428132U, // VRCP28SSZmkz + 96U, // VRCP28SSZr + 20576U, // VRCP28SSZrb + 11700516U, // VRCP28SSZrbk + 11733092U, // VRCP28SSZrbkz + 166180U, // VRCP28SSZrk + 198756U, // VRCP28SSZrkz + 0U, // VRCPPSYm + 0U, // VRCPPSYr + 0U, // VRCPPSm + 0U, // VRCPPSr + 448U, // VRCPSSm + 448U, // VRCPSSm_Int + 96U, // VRCPSSr + 96U, // VRCPSSr_Int + 11U, // VREDUCEPDZ128rmbi + 936516U, // VREDUCEPDZ128rmbik + 477572U, // VREDUCEPDZ128rmbikz + 0U, // VREDUCEPDZ128rmi + 919812U, // VREDUCEPDZ128rmik + 461156U, // VREDUCEPDZ128rmikz + 32U, // VREDUCEPDZ128rri + 2340U, // VREDUCEPDZ128rrik + 624740U, // VREDUCEPDZ128rrikz + 12U, // VREDUCEPDZ256rmbi + 930372U, // VREDUCEPDZ256rmbik + 471428U, // VREDUCEPDZ256rmbikz + 0U, // VREDUCEPDZ256rmi + 920164U, // VREDUCEPDZ256rmik + 461124U, // VREDUCEPDZ256rmikz + 32U, // VREDUCEPDZ256rri + 2340U, // VREDUCEPDZ256rrik + 624740U, // VREDUCEPDZ256rrikz + 12U, // VREDUCEPDZrmbi + 932420U, // VREDUCEPDZrmbik + 473476U, // VREDUCEPDZrmbikz + 0U, // VREDUCEPDZrmi + 920612U, // VREDUCEPDZrmik + 461220U, // VREDUCEPDZrmikz + 32U, // VREDUCEPDZrri + 11U, // VREDUCEPDZrrib + 22820U, // VREDUCEPDZrribk + 645220U, // VREDUCEPDZrribkz + 2340U, // VREDUCEPDZrrik + 624740U, // VREDUCEPDZrrikz + 12U, // VREDUCEPSZ128rmbi + 930532U, // VREDUCEPSZ128rmbik + 471492U, // VREDUCEPSZ128rmbikz + 0U, // VREDUCEPSZ128rmi + 919812U, // VREDUCEPSZ128rmik + 461156U, // VREDUCEPSZ128rmikz + 32U, // VREDUCEPSZ128rri + 2340U, // VREDUCEPSZ128rrik + 624740U, // VREDUCEPSZ128rrikz + 12U, // VREDUCEPSZ256rmbi + 932580U, // VREDUCEPSZ256rmbik + 473540U, // VREDUCEPSZ256rmbikz + 0U, // VREDUCEPSZ256rmi + 920164U, // VREDUCEPSZ256rmik + 461124U, // VREDUCEPSZ256rmikz + 32U, // VREDUCEPSZ256rri + 2340U, // VREDUCEPSZ256rrik + 624740U, // VREDUCEPSZ256rrikz + 13U, // VREDUCEPSZrmbi + 934628U, // VREDUCEPSZrmbik + 475588U, // VREDUCEPSZrmbikz + 0U, // VREDUCEPSZrmi + 920612U, // VREDUCEPSZrmik + 461220U, // VREDUCEPSZrmikz + 32U, // VREDUCEPSZrri + 11U, // VREDUCEPSZrrib + 22820U, // VREDUCEPSZrribk + 645220U, // VREDUCEPSZrribkz + 2340U, // VREDUCEPSZrrik + 624740U, // VREDUCEPSZrrikz + 461184U, // VREDUCESDZrmi + 37816612U, // VREDUCESDZrmik + 54626404U, // VREDUCESDZrmikz + 624736U, // VREDUCESDZrri + 645216U, // VREDUCESDZrrib + 77760804U, // VREDUCESDZrribk + 94570596U, // VREDUCESDZrribkz + 71469348U, // VREDUCESDZrrik + 88279140U, // VREDUCESDZrrikz + 461248U, // VREDUCESSZrmi + 38144292U, // VREDUCESSZrmik + 54954084U, // VREDUCESSZrmikz + 624736U, // VREDUCESSZrri + 645216U, // VREDUCESSZrrib + 77760804U, // VREDUCESSZrribk + 94570596U, // VREDUCESSZrribkz + 71469348U, // VREDUCESSZrrik + 88279140U, // VREDUCESSZrrikz + 11U, // VRNDSCALEPDZ128rmbi + 936516U, // VRNDSCALEPDZ128rmbik + 477572U, // VRNDSCALEPDZ128rmbikz + 0U, // VRNDSCALEPDZ128rmi + 919812U, // VRNDSCALEPDZ128rmik + 461156U, // VRNDSCALEPDZ128rmikz + 32U, // VRNDSCALEPDZ128rri + 2340U, // VRNDSCALEPDZ128rrik + 624740U, // VRNDSCALEPDZ128rrikz + 12U, // VRNDSCALEPDZ256rmbi + 930372U, // VRNDSCALEPDZ256rmbik + 471428U, // VRNDSCALEPDZ256rmbikz + 0U, // VRNDSCALEPDZ256rmi + 920164U, // VRNDSCALEPDZ256rmik + 461124U, // VRNDSCALEPDZ256rmikz + 32U, // VRNDSCALEPDZ256rri + 2340U, // VRNDSCALEPDZ256rrik + 624740U, // VRNDSCALEPDZ256rrikz + 12U, // VRNDSCALEPDZrmbi + 932420U, // VRNDSCALEPDZrmbik + 473476U, // VRNDSCALEPDZrmbikz + 0U, // VRNDSCALEPDZrmi + 920612U, // VRNDSCALEPDZrmik + 461220U, // VRNDSCALEPDZrmikz + 32U, // VRNDSCALEPDZrri + 11U, // VRNDSCALEPDZrrib + 22820U, // VRNDSCALEPDZrribk + 645220U, // VRNDSCALEPDZrribkz + 2340U, // VRNDSCALEPDZrrik + 624740U, // VRNDSCALEPDZrrikz + 12U, // VRNDSCALEPSZ128rmbi + 930532U, // VRNDSCALEPSZ128rmbik + 471492U, // VRNDSCALEPSZ128rmbikz + 0U, // VRNDSCALEPSZ128rmi + 919812U, // VRNDSCALEPSZ128rmik + 461156U, // VRNDSCALEPSZ128rmikz + 32U, // VRNDSCALEPSZ128rri + 2340U, // VRNDSCALEPSZ128rrik + 624740U, // VRNDSCALEPSZ128rrikz + 12U, // VRNDSCALEPSZ256rmbi + 932580U, // VRNDSCALEPSZ256rmbik + 473540U, // VRNDSCALEPSZ256rmbikz + 0U, // VRNDSCALEPSZ256rmi + 920164U, // VRNDSCALEPSZ256rmik + 461124U, // VRNDSCALEPSZ256rmikz + 32U, // VRNDSCALEPSZ256rri + 2340U, // VRNDSCALEPSZ256rrik + 624740U, // VRNDSCALEPSZ256rrikz + 13U, // VRNDSCALEPSZrmbi + 934628U, // VRNDSCALEPSZrmbik + 475588U, // VRNDSCALEPSZrmbikz + 0U, // VRNDSCALEPSZrmi + 920612U, // VRNDSCALEPSZrmik + 461220U, // VRNDSCALEPSZrmikz + 32U, // VRNDSCALEPSZrri + 11U, // VRNDSCALEPSZrrib + 22820U, // VRNDSCALEPSZrribk + 645220U, // VRNDSCALEPSZrribkz + 2340U, // VRNDSCALEPSZrrik + 624740U, // VRNDSCALEPSZrrikz + 461184U, // VRNDSCALESDZm + 461184U, // VRNDSCALESDZm_Int + 37816612U, // VRNDSCALESDZm_Intk + 54626404U, // VRNDSCALESDZm_Intkz + 624736U, // VRNDSCALESDZr + 624736U, // VRNDSCALESDZr_Int + 71469348U, // VRNDSCALESDZr_Intk + 88279140U, // VRNDSCALESDZr_Intkz + 645216U, // VRNDSCALESDZrb_Int + 77760804U, // VRNDSCALESDZrb_Intk + 94570596U, // VRNDSCALESDZrb_Intkz + 461248U, // VRNDSCALESSZm + 461248U, // VRNDSCALESSZm_Int + 38144292U, // VRNDSCALESSZm_Intk + 54954084U, // VRNDSCALESSZm_Intkz + 624736U, // VRNDSCALESSZr + 624736U, // VRNDSCALESSZr_Int + 71469348U, // VRNDSCALESSZr_Intk + 88279140U, // VRNDSCALESSZr_Intkz + 645216U, // VRNDSCALESSZrb_Int + 77760804U, // VRNDSCALESSZrb_Intk + 94570596U, // VRNDSCALESSZrb_Intkz + 0U, // VROUNDPDYm + 32U, // VROUNDPDYr + 0U, // VROUNDPDm + 32U, // VROUNDPDr + 0U, // VROUNDPSYm + 32U, // VROUNDPSYr + 0U, // VROUNDPSm + 32U, // VROUNDPSr + 461184U, // VROUNDSDm + 461184U, // VROUNDSDm_Int + 624736U, // VROUNDSDr + 624736U, // VROUNDSDr_Int + 461248U, // VROUNDSSm + 461248U, // VROUNDSSm_Int + 624736U, // VROUNDSSr + 624736U, // VROUNDSSr_Int + 0U, // VRSQRT14PDZ128m + 9U, // VRSQRT14PDZ128mb + 4676U, // VRSQRT14PDZ128mbk + 4484U, // VRSQRT14PDZ128mbkz + 260U, // VRSQRT14PDZ128mk + 356U, // VRSQRT14PDZ128mkz + 0U, // VRSQRT14PDZ128r + 292U, // VRSQRT14PDZ128rk + 100U, // VRSQRT14PDZ128rkz + 0U, // VRSQRT14PDZ256m + 9U, // VRSQRT14PDZ256mb + 6724U, // VRSQRT14PDZ256mbk + 6532U, // VRSQRT14PDZ256mbkz + 612U, // VRSQRT14PDZ256mk + 324U, // VRSQRT14PDZ256mkz + 0U, // VRSQRT14PDZ256r + 292U, // VRSQRT14PDZ256rk + 100U, // VRSQRT14PDZ256rkz + 0U, // VRSQRT14PDZm + 10U, // VRSQRT14PDZmb + 8772U, // VRSQRT14PDZmbk + 8580U, // VRSQRT14PDZmbkz + 1060U, // VRSQRT14PDZmk + 420U, // VRSQRT14PDZmkz + 0U, // VRSQRT14PDZr + 292U, // VRSQRT14PDZrk + 100U, // VRSQRT14PDZrkz + 0U, // VRSQRT14PSZ128m + 9U, // VRSQRT14PSZ128mb + 6884U, // VRSQRT14PSZ128mbk + 6596U, // VRSQRT14PSZ128mbkz + 260U, // VRSQRT14PSZ128mk + 356U, // VRSQRT14PSZ128mkz + 0U, // VRSQRT14PSZ128r + 292U, // VRSQRT14PSZ128rk + 100U, // VRSQRT14PSZ128rkz + 0U, // VRSQRT14PSZ256m + 10U, // VRSQRT14PSZ256mb + 8932U, // VRSQRT14PSZ256mbk + 8644U, // VRSQRT14PSZ256mbkz + 612U, // VRSQRT14PSZ256mk + 324U, // VRSQRT14PSZ256mkz + 0U, // VRSQRT14PSZ256r + 292U, // VRSQRT14PSZ256rk + 100U, // VRSQRT14PSZ256rkz + 0U, // VRSQRT14PSZm + 10U, // VRSQRT14PSZmb + 10980U, // VRSQRT14PSZmbk + 10692U, // VRSQRT14PSZmbkz + 1060U, // VRSQRT14PSZmk + 420U, // VRSQRT14PSZmkz + 0U, // VRSQRT14PSZr + 292U, // VRSQRT14PSZrk + 100U, // VRSQRT14PSZrkz + 384U, // VRSQRT14SDZrm + 67876U, // VRSQRT14SDZrmk + 100452U, // VRSQRT14SDZrmkz + 96U, // VRSQRT14SDZrr + 166180U, // VRSQRT14SDZrrk + 198756U, // VRSQRT14SDZrrkz + 448U, // VRSQRT14SSZrm + 395556U, // VRSQRT14SSZrmk + 428132U, // VRSQRT14SSZrmkz + 96U, // VRSQRT14SSZrr + 166180U, // VRSQRT14SSZrrk + 198756U, // VRSQRT14SSZrrkz + 0U, // VRSQRT28PDZm + 10U, // VRSQRT28PDZmb + 8772U, // VRSQRT28PDZmbk + 8580U, // VRSQRT28PDZmbkz + 1060U, // VRSQRT28PDZmk + 420U, // VRSQRT28PDZmkz + 0U, // VRSQRT28PDZr + 8U, // VRSQRT28PDZrb + 20772U, // VRSQRT28PDZrbk + 20580U, // VRSQRT28PDZrbkz + 292U, // VRSQRT28PDZrk + 100U, // VRSQRT28PDZrkz + 0U, // VRSQRT28PSZm + 10U, // VRSQRT28PSZmb + 10980U, // VRSQRT28PSZmbk + 10692U, // VRSQRT28PSZmbkz + 1060U, // VRSQRT28PSZmk + 420U, // VRSQRT28PSZmkz + 0U, // VRSQRT28PSZr + 8U, // VRSQRT28PSZrb + 20772U, // VRSQRT28PSZrbk + 20580U, // VRSQRT28PSZrbkz + 292U, // VRSQRT28PSZrk + 100U, // VRSQRT28PSZrkz + 384U, // VRSQRT28SDZm + 67876U, // VRSQRT28SDZmk + 100452U, // VRSQRT28SDZmkz + 96U, // VRSQRT28SDZr + 20576U, // VRSQRT28SDZrb + 11700516U, // VRSQRT28SDZrbk + 11733092U, // VRSQRT28SDZrbkz + 166180U, // VRSQRT28SDZrk + 198756U, // VRSQRT28SDZrkz + 448U, // VRSQRT28SSZm + 395556U, // VRSQRT28SSZmk + 428132U, // VRSQRT28SSZmkz + 96U, // VRSQRT28SSZr + 20576U, // VRSQRT28SSZrb + 11700516U, // VRSQRT28SSZrbk + 11733092U, // VRSQRT28SSZrbkz + 166180U, // VRSQRT28SSZrk + 198756U, // VRSQRT28SSZrkz + 0U, // VRSQRTPSYm + 0U, // VRSQRTPSYr + 0U, // VRSQRTPSm + 0U, // VRSQRTPSr + 448U, // VRSQRTSSm + 448U, // VRSQRTSSm_Int + 96U, // VRSQRTSSr + 96U, // VRSQRTSSr_Int + 352U, // VSCALEFPDZ128rm + 4480U, // VSCALEFPDZ128rmb + 1116452U, // VSCALEFPDZ128rmbk + 1149028U, // VSCALEFPDZ128rmbkz + 35108U, // VSCALEFPDZ128rmk + 133220U, // VSCALEFPDZ128rmkz + 96U, // VSCALEFPDZ128rr + 166180U, // VSCALEFPDZ128rrk + 198756U, // VSCALEFPDZ128rrkz + 320U, // VSCALEFPDZ256rm + 6528U, // VSCALEFPDZ256rmb + 2165028U, // VSCALEFPDZ256rmbk + 2197604U, // VSCALEFPDZ256rmbkz + 231716U, // VSCALEFPDZ256rmk + 264292U, // VSCALEFPDZ256rmkz + 96U, // VSCALEFPDZ256rr + 166180U, // VSCALEFPDZ256rrk + 198756U, // VSCALEFPDZ256rrkz + 416U, // VSCALEFPDZrm + 8576U, // VSCALEFPDZrmb + 3213604U, // VSCALEFPDZrmbk + 3246180U, // VSCALEFPDZrmbkz + 297252U, // VSCALEFPDZrmk + 329828U, // VSCALEFPDZrmkz + 96U, // VSCALEFPDZrr + 362592U, // VSCALEFPDZrrb + 4360484U, // VSCALEFPDZrrbk + 21170276U, // VSCALEFPDZrrbkz + 166180U, // VSCALEFPDZrrk + 198756U, // VSCALEFPDZrrkz + 352U, // VSCALEFPSZ128rm + 6592U, // VSCALEFPSZ128rmb + 2492708U, // VSCALEFPSZ128rmbk + 2525284U, // VSCALEFPSZ128rmbkz + 35108U, // VSCALEFPSZ128rmk + 133220U, // VSCALEFPSZ128rmkz + 96U, // VSCALEFPSZ128rr + 166180U, // VSCALEFPSZ128rrk + 198756U, // VSCALEFPSZ128rrkz + 320U, // VSCALEFPSZ256rm + 8640U, // VSCALEFPSZ256rmb + 3541284U, // VSCALEFPSZ256rmbk + 3573860U, // VSCALEFPSZ256rmbkz + 231716U, // VSCALEFPSZ256rmk + 264292U, // VSCALEFPSZ256rmkz + 96U, // VSCALEFPSZ256rr + 166180U, // VSCALEFPSZ256rrk + 198756U, // VSCALEFPSZ256rrkz + 416U, // VSCALEFPSZrm + 10688U, // VSCALEFPSZrmb + 5638436U, // VSCALEFPSZrmbk + 5671012U, // VSCALEFPSZrmbkz + 297252U, // VSCALEFPSZrmk + 329828U, // VSCALEFPSZrmkz + 96U, // VSCALEFPSZrr + 362592U, // VSCALEFPSZrrb + 4360484U, // VSCALEFPSZrrbk + 21170276U, // VSCALEFPSZrrbkz + 166180U, // VSCALEFPSZrrk + 198756U, // VSCALEFPSZrrkz + 384U, // VSCALEFSDZrm + 67876U, // VSCALEFSDZrmk + 100452U, // VSCALEFSDZrmkz + 96U, // VSCALEFSDZrr + 362592U, // VSCALEFSDZrrb_Int + 4360484U, // VSCALEFSDZrrb_Intk + 21170276U, // VSCALEFSDZrrb_Intkz + 166180U, // VSCALEFSDZrrk + 198756U, // VSCALEFSDZrrkz + 448U, // VSCALEFSSZrm + 395556U, // VSCALEFSSZrmk + 428132U, // VSCALEFSSZrmkz + 96U, // VSCALEFSSZrr + 362592U, // VSCALEFSSZrrb_Int + 4360484U, // VSCALEFSSZrrb_Intk + 21170276U, // VSCALEFSSZrrb_Intkz + 166180U, // VSCALEFSSZrrk + 198756U, // VSCALEFSSZrrkz + 0U, // VSCATTERDPDZ128mr + 0U, // VSCATTERDPDZ256mr + 0U, // VSCATTERDPDZmr + 0U, // VSCATTERDPSZ128mr + 0U, // VSCATTERDPSZ256mr + 0U, // VSCATTERDPSZmr + 0U, // VSCATTERPF0DPDm + 0U, // VSCATTERPF0DPSm + 0U, // VSCATTERPF0QPDm + 0U, // VSCATTERPF0QPSm + 0U, // VSCATTERPF1DPDm + 0U, // VSCATTERPF1DPSm + 0U, // VSCATTERPF1QPDm + 0U, // VSCATTERPF1QPSm + 0U, // VSCATTERQPDZ128mr + 0U, // VSCATTERQPDZ256mr + 0U, // VSCATTERQPDZmr + 0U, // VSCATTERQPSZ128mr + 0U, // VSCATTERQPSZ256mr + 0U, // VSCATTERQPSZmr + 473536U, // VSHUFF32X4Z256rmbi + 41290020U, // VSHUFF32X4Z256rmbik + 58099812U, // VSHUFF32X4Z256rmbikz + 461120U, // VSHUFF32X4Z256rmi + 37980452U, // VSHUFF32X4Z256rmik + 54790244U, // VSHUFF32X4Z256rmikz + 624736U, // VSHUFF32X4Z256rri + 71469348U, // VSHUFF32X4Z256rrik + 88279140U, // VSHUFF32X4Z256rrikz + 475584U, // VSHUFF32X4Zrmbi + 42338596U, // VSHUFF32X4Zrmbik + 59148388U, // VSHUFF32X4Zrmbikz + 461216U, // VSHUFF32X4Zrmi + 38045988U, // VSHUFF32X4Zrmik + 54855780U, // VSHUFF32X4Zrmikz + 624736U, // VSHUFF32X4Zrri + 71469348U, // VSHUFF32X4Zrrik + 88279140U, // VSHUFF32X4Zrrikz + 471424U, // VSHUFF64X2Z256rmbi + 39913764U, // VSHUFF64X2Z256rmbik + 56723556U, // VSHUFF64X2Z256rmbikz + 461120U, // VSHUFF64X2Z256rmi + 37980452U, // VSHUFF64X2Z256rmik + 54790244U, // VSHUFF64X2Z256rmikz + 624736U, // VSHUFF64X2Z256rri + 71469348U, // VSHUFF64X2Z256rrik + 88279140U, // VSHUFF64X2Z256rrikz + 473472U, // VSHUFF64X2Zrmbi + 40962340U, // VSHUFF64X2Zrmbik + 57772132U, // VSHUFF64X2Zrmbikz + 461216U, // VSHUFF64X2Zrmi + 38045988U, // VSHUFF64X2Zrmik + 54855780U, // VSHUFF64X2Zrmikz + 624736U, // VSHUFF64X2Zrri + 71469348U, // VSHUFF64X2Zrrik + 88279140U, // VSHUFF64X2Zrrikz + 473152U, // VSHUFI32X4Z256rmbi + 41388324U, // VSHUFI32X4Z256rmbik + 58198116U, // VSHUFI32X4Z256rmbikz + 461280U, // VSHUFI32X4Z256rmi + 38406436U, // VSHUFI32X4Z256rmik + 55216228U, // VSHUFI32X4Z256rmikz + 624736U, // VSHUFI32X4Z256rri + 71469348U, // VSHUFI32X4Z256rrik + 88279140U, // VSHUFI32X4Z256rrikz + 475200U, // VSHUFI32X4Zrmbi + 42436900U, // VSHUFI32X4Zrmbik + 59246692U, // VSHUFI32X4Zrmbikz + 461344U, // VSHUFI32X4Zrmi + 38471972U, // VSHUFI32X4Zrmik + 55281764U, // VSHUFI32X4Zrmikz + 624736U, // VSHUFI32X4Zrri + 71469348U, // VSHUFI32X4Zrrik + 88279140U, // VSHUFI32X4Zrrikz + 471168U, // VSHUFI64X2Z256rmbi + 40634660U, // VSHUFI64X2Z256rmbik + 57444452U, // VSHUFI64X2Z256rmbikz + 461280U, // VSHUFI64X2Z256rmi + 38406436U, // VSHUFI64X2Z256rmik + 55216228U, // VSHUFI64X2Z256rmikz + 624736U, // VSHUFI64X2Z256rri + 71469348U, // VSHUFI64X2Z256rrik + 88279140U, // VSHUFI64X2Z256rrikz + 473216U, // VSHUFI64X2Zrmbi + 41683236U, // VSHUFI64X2Zrmbik + 58493028U, // VSHUFI64X2Zrmbikz + 461344U, // VSHUFI64X2Zrmi + 38471972U, // VSHUFI64X2Zrmik + 55281764U, // VSHUFI64X2Zrmikz + 624736U, // VSHUFI64X2Zrri + 71469348U, // VSHUFI64X2Zrrik + 88279140U, // VSHUFI64X2Zrrikz + 461120U, // VSHUFPDYrmi + 624736U, // VSHUFPDYrri + 477568U, // VSHUFPDZ128rmbi + 43059492U, // VSHUFPDZ128rmbik + 59869284U, // VSHUFPDZ128rmbikz + 461152U, // VSHUFPDZ128rmi + 37783844U, // VSHUFPDZ128rmik + 54659172U, // VSHUFPDZ128rmikz + 624736U, // VSHUFPDZ128rri + 71469348U, // VSHUFPDZ128rrik + 88279140U, // VSHUFPDZ128rrikz + 471424U, // VSHUFPDZ256rmbi + 39913764U, // VSHUFPDZ256rmbik + 56723556U, // VSHUFPDZ256rmbikz + 461120U, // VSHUFPDZ256rmi + 37980452U, // VSHUFPDZ256rmik + 54790244U, // VSHUFPDZ256rmikz + 624736U, // VSHUFPDZ256rri + 71469348U, // VSHUFPDZ256rrik + 88279140U, // VSHUFPDZ256rrikz + 473472U, // VSHUFPDZrmbi + 40962340U, // VSHUFPDZrmbik + 57772132U, // VSHUFPDZrmbikz + 461216U, // VSHUFPDZrmi + 38045988U, // VSHUFPDZrmik + 54855780U, // VSHUFPDZrmikz + 624736U, // VSHUFPDZrri + 71469348U, // VSHUFPDZrrik + 88279140U, // VSHUFPDZrrikz + 461152U, // VSHUFPDrmi + 624736U, // VSHUFPDrri + 461120U, // VSHUFPSYrmi + 624736U, // VSHUFPSYrri + 471488U, // VSHUFPSZ128rmbi + 40241444U, // VSHUFPSZ128rmbik + 57051236U, // VSHUFPSZ128rmbikz + 461152U, // VSHUFPSZ128rmi + 37783844U, // VSHUFPSZ128rmik + 54659172U, // VSHUFPSZ128rmikz + 624736U, // VSHUFPSZ128rri + 71469348U, // VSHUFPSZ128rrik + 88279140U, // VSHUFPSZ128rrikz + 473536U, // VSHUFPSZ256rmbi + 41290020U, // VSHUFPSZ256rmbik + 58099812U, // VSHUFPSZ256rmbikz + 461120U, // VSHUFPSZ256rmi + 37980452U, // VSHUFPSZ256rmik + 54790244U, // VSHUFPSZ256rmikz + 624736U, // VSHUFPSZ256rri + 71469348U, // VSHUFPSZ256rrik + 88279140U, // VSHUFPSZ256rrikz + 475584U, // VSHUFPSZrmbi + 42338596U, // VSHUFPSZrmbik + 59148388U, // VSHUFPSZrmbikz + 461216U, // VSHUFPSZrmi + 38045988U, // VSHUFPSZrmik + 54855780U, // VSHUFPSZrmikz + 624736U, // VSHUFPSZrri + 71469348U, // VSHUFPSZrrik + 88279140U, // VSHUFPSZrrikz + 461152U, // VSHUFPSrmi + 624736U, // VSHUFPSrri + 0U, // VSQRTPDYm + 0U, // VSQRTPDYr + 0U, // VSQRTPDZ128m + 9U, // VSQRTPDZ128mb + 4676U, // VSQRTPDZ128mbk + 4484U, // VSQRTPDZ128mbkz + 260U, // VSQRTPDZ128mk + 356U, // VSQRTPDZ128mkz + 0U, // VSQRTPDZ128r + 292U, // VSQRTPDZ128rk + 100U, // VSQRTPDZ128rkz + 0U, // VSQRTPDZ256m + 9U, // VSQRTPDZ256mb + 6724U, // VSQRTPDZ256mbk + 6532U, // VSQRTPDZ256mbkz + 612U, // VSQRTPDZ256mk + 324U, // VSQRTPDZ256mkz + 0U, // VSQRTPDZ256r + 292U, // VSQRTPDZ256rk + 100U, // VSQRTPDZ256rkz + 0U, // VSQRTPDZm + 10U, // VSQRTPDZmb + 8772U, // VSQRTPDZmbk + 8580U, // VSQRTPDZmbkz + 1060U, // VSQRTPDZmk + 420U, // VSQRTPDZmkz + 0U, // VSQRTPDZr + 1024U, // VSQRTPDZrb + 887076U, // VSQRTPDZrbk + 362596U, // VSQRTPDZrbkz + 292U, // VSQRTPDZrk + 100U, // VSQRTPDZrkz + 0U, // VSQRTPDm + 0U, // VSQRTPDr + 0U, // VSQRTPSYm + 0U, // VSQRTPSYr + 0U, // VSQRTPSZ128m + 9U, // VSQRTPSZ128mb + 6884U, // VSQRTPSZ128mbk + 6596U, // VSQRTPSZ128mbkz + 260U, // VSQRTPSZ128mk + 356U, // VSQRTPSZ128mkz + 0U, // VSQRTPSZ128r + 292U, // VSQRTPSZ128rk + 100U, // VSQRTPSZ128rkz + 0U, // VSQRTPSZ256m + 10U, // VSQRTPSZ256mb + 8932U, // VSQRTPSZ256mbk + 8644U, // VSQRTPSZ256mbkz + 612U, // VSQRTPSZ256mk + 324U, // VSQRTPSZ256mkz + 0U, // VSQRTPSZ256r + 292U, // VSQRTPSZ256rk + 100U, // VSQRTPSZ256rkz + 0U, // VSQRTPSZm + 10U, // VSQRTPSZmb + 10980U, // VSQRTPSZmbk + 10692U, // VSQRTPSZmbkz + 1060U, // VSQRTPSZmk + 420U, // VSQRTPSZmkz + 0U, // VSQRTPSZr + 1024U, // VSQRTPSZrb + 887076U, // VSQRTPSZrbk + 362596U, // VSQRTPSZrbkz + 292U, // VSQRTPSZrk + 100U, // VSQRTPSZrkz + 0U, // VSQRTPSm + 0U, // VSQRTPSr + 384U, // VSQRTSDZm + 384U, // VSQRTSDZm_Int + 67876U, // VSQRTSDZm_Intk + 100452U, // VSQRTSDZm_Intkz + 96U, // VSQRTSDZr + 96U, // VSQRTSDZr_Int + 166180U, // VSQRTSDZr_Intk + 198756U, // VSQRTSDZr_Intkz + 362592U, // VSQRTSDZrb_Int + 4360484U, // VSQRTSDZrb_Intk + 21170276U, // VSQRTSDZrb_Intkz + 384U, // VSQRTSDm + 384U, // VSQRTSDm_Int + 96U, // VSQRTSDr + 96U, // VSQRTSDr_Int + 448U, // VSQRTSSZm + 448U, // VSQRTSSZm_Int + 395556U, // VSQRTSSZm_Intk + 428132U, // VSQRTSSZm_Intkz + 96U, // VSQRTSSZr + 96U, // VSQRTSSZr_Int + 166180U, // VSQRTSSZr_Intk + 198756U, // VSQRTSSZr_Intkz + 362592U, // VSQRTSSZrb_Int + 4360484U, // VSQRTSSZrb_Intk + 21170276U, // VSQRTSSZrb_Intkz + 448U, // VSQRTSSm + 448U, // VSQRTSSm_Int + 96U, // VSQRTSSr + 96U, // VSQRTSSr_Int + 0U, // VSTMXCSR + 320U, // VSUBPDYrm + 96U, // VSUBPDYrr + 352U, // VSUBPDZ128rm + 4480U, // VSUBPDZ128rmb + 1116452U, // VSUBPDZ128rmbk + 1149028U, // VSUBPDZ128rmbkz + 35108U, // VSUBPDZ128rmk + 133220U, // VSUBPDZ128rmkz + 96U, // VSUBPDZ128rr + 166180U, // VSUBPDZ128rrk + 198756U, // VSUBPDZ128rrkz + 320U, // VSUBPDZ256rm + 6528U, // VSUBPDZ256rmb + 2165028U, // VSUBPDZ256rmbk + 2197604U, // VSUBPDZ256rmbkz + 231716U, // VSUBPDZ256rmk + 264292U, // VSUBPDZ256rmkz + 96U, // VSUBPDZ256rr + 166180U, // VSUBPDZ256rrk + 198756U, // VSUBPDZ256rrkz + 416U, // VSUBPDZrm + 8576U, // VSUBPDZrmb + 3213604U, // VSUBPDZrmbk + 3246180U, // VSUBPDZrmbkz + 297252U, // VSUBPDZrmk + 329828U, // VSUBPDZrmkz + 96U, // VSUBPDZrr + 362592U, // VSUBPDZrrb + 4360484U, // VSUBPDZrrbk + 21170276U, // VSUBPDZrrbkz + 166180U, // VSUBPDZrrk + 198756U, // VSUBPDZrrkz + 352U, // VSUBPDrm + 96U, // VSUBPDrr + 320U, // VSUBPSYrm + 96U, // VSUBPSYrr + 352U, // VSUBPSZ128rm + 6592U, // VSUBPSZ128rmb + 2492708U, // VSUBPSZ128rmbk + 2525284U, // VSUBPSZ128rmbkz + 35108U, // VSUBPSZ128rmk + 133220U, // VSUBPSZ128rmkz + 96U, // VSUBPSZ128rr + 166180U, // VSUBPSZ128rrk + 198756U, // VSUBPSZ128rrkz + 320U, // VSUBPSZ256rm + 8640U, // VSUBPSZ256rmb + 3541284U, // VSUBPSZ256rmbk + 3573860U, // VSUBPSZ256rmbkz + 231716U, // VSUBPSZ256rmk + 264292U, // VSUBPSZ256rmkz + 96U, // VSUBPSZ256rr + 166180U, // VSUBPSZ256rrk + 198756U, // VSUBPSZ256rrkz + 416U, // VSUBPSZrm + 10688U, // VSUBPSZrmb + 5638436U, // VSUBPSZrmbk + 5671012U, // VSUBPSZrmbkz + 297252U, // VSUBPSZrmk + 329828U, // VSUBPSZrmkz + 96U, // VSUBPSZrr + 362592U, // VSUBPSZrrb + 4360484U, // VSUBPSZrrbk + 21170276U, // VSUBPSZrrbkz + 166180U, // VSUBPSZrrk + 198756U, // VSUBPSZrrkz + 352U, // VSUBPSrm + 96U, // VSUBPSrr + 384U, // VSUBSDZrm + 384U, // VSUBSDZrm_Int + 67876U, // VSUBSDZrm_Intk + 100452U, // VSUBSDZrm_Intkz + 96U, // VSUBSDZrr + 96U, // VSUBSDZrr_Int + 166180U, // VSUBSDZrr_Intk + 198756U, // VSUBSDZrr_Intkz + 362592U, // VSUBSDZrrb_Int + 4360484U, // VSUBSDZrrb_Intk + 21170276U, // VSUBSDZrrb_Intkz + 384U, // VSUBSDrm + 384U, // VSUBSDrm_Int + 96U, // VSUBSDrr + 96U, // VSUBSDrr_Int + 448U, // VSUBSSZrm + 448U, // VSUBSSZrm_Int + 395556U, // VSUBSSZrm_Intk + 428132U, // VSUBSSZrm_Intkz + 96U, // VSUBSSZrr + 96U, // VSUBSSZrr_Int + 166180U, // VSUBSSZrr_Intk + 198756U, // VSUBSSZrr_Intkz + 362592U, // VSUBSSZrrb_Int + 4360484U, // VSUBSSZrrb_Intk + 21170276U, // VSUBSSZrrb_Intkz + 448U, // VSUBSSrm + 448U, // VSUBSSrm_Int + 96U, // VSUBSSrr + 96U, // VSUBSSrr_Int + 0U, // VTESTPDYrm + 0U, // VTESTPDYrr + 0U, // VTESTPDrm + 0U, // VTESTPDrr + 0U, // VTESTPSYrm + 0U, // VTESTPSYrr + 0U, // VTESTPSrm + 0U, // VTESTPSrr + 0U, // VUCOMISDZrm + 0U, // VUCOMISDZrm_Int + 0U, // VUCOMISDZrr + 0U, // VUCOMISDZrr_Int + 8U, // VUCOMISDZrrb + 0U, // VUCOMISDrm + 0U, // VUCOMISDrm_Int + 0U, // VUCOMISDrr + 0U, // VUCOMISDrr_Int + 0U, // VUCOMISSZrm + 0U, // VUCOMISSZrm_Int + 0U, // VUCOMISSZrr + 0U, // VUCOMISSZrr_Int + 8U, // VUCOMISSZrrb + 0U, // VUCOMISSrm + 0U, // VUCOMISSrm_Int + 0U, // VUCOMISSrr + 0U, // VUCOMISSrr_Int + 320U, // VUNPCKHPDYrm + 96U, // VUNPCKHPDYrr + 352U, // VUNPCKHPDZ128rm + 4480U, // VUNPCKHPDZ128rmb + 1116452U, // VUNPCKHPDZ128rmbk + 1149028U, // VUNPCKHPDZ128rmbkz + 35108U, // VUNPCKHPDZ128rmk + 133220U, // VUNPCKHPDZ128rmkz + 96U, // VUNPCKHPDZ128rr + 166180U, // VUNPCKHPDZ128rrk + 198756U, // VUNPCKHPDZ128rrkz + 320U, // VUNPCKHPDZ256rm + 6528U, // VUNPCKHPDZ256rmb + 2165028U, // VUNPCKHPDZ256rmbk + 2197604U, // VUNPCKHPDZ256rmbkz + 231716U, // VUNPCKHPDZ256rmk + 264292U, // VUNPCKHPDZ256rmkz + 96U, // VUNPCKHPDZ256rr + 166180U, // VUNPCKHPDZ256rrk + 198756U, // VUNPCKHPDZ256rrkz + 416U, // VUNPCKHPDZrm + 8576U, // VUNPCKHPDZrmb + 3213604U, // VUNPCKHPDZrmbk + 3246180U, // VUNPCKHPDZrmbkz + 297252U, // VUNPCKHPDZrmk + 329828U, // VUNPCKHPDZrmkz + 96U, // VUNPCKHPDZrr + 166180U, // VUNPCKHPDZrrk + 198756U, // VUNPCKHPDZrrkz + 352U, // VUNPCKHPDrm + 96U, // VUNPCKHPDrr + 320U, // VUNPCKHPSYrm + 96U, // VUNPCKHPSYrr + 352U, // VUNPCKHPSZ128rm + 6592U, // VUNPCKHPSZ128rmb + 2492708U, // VUNPCKHPSZ128rmbk + 2525284U, // VUNPCKHPSZ128rmbkz + 35108U, // VUNPCKHPSZ128rmk + 133220U, // VUNPCKHPSZ128rmkz + 96U, // VUNPCKHPSZ128rr + 166180U, // VUNPCKHPSZ128rrk + 198756U, // VUNPCKHPSZ128rrkz + 320U, // VUNPCKHPSZ256rm + 8640U, // VUNPCKHPSZ256rmb + 3541284U, // VUNPCKHPSZ256rmbk + 3573860U, // VUNPCKHPSZ256rmbkz + 231716U, // VUNPCKHPSZ256rmk + 264292U, // VUNPCKHPSZ256rmkz + 96U, // VUNPCKHPSZ256rr + 166180U, // VUNPCKHPSZ256rrk + 198756U, // VUNPCKHPSZ256rrkz + 416U, // VUNPCKHPSZrm + 10688U, // VUNPCKHPSZrmb + 5638436U, // VUNPCKHPSZrmbk + 5671012U, // VUNPCKHPSZrmbkz + 297252U, // VUNPCKHPSZrmk + 329828U, // VUNPCKHPSZrmkz + 96U, // VUNPCKHPSZrr + 166180U, // VUNPCKHPSZrrk + 198756U, // VUNPCKHPSZrrkz + 352U, // VUNPCKHPSrm + 96U, // VUNPCKHPSrr + 320U, // VUNPCKLPDYrm + 96U, // VUNPCKLPDYrr + 352U, // VUNPCKLPDZ128rm + 4480U, // VUNPCKLPDZ128rmb + 1116452U, // VUNPCKLPDZ128rmbk + 1149028U, // VUNPCKLPDZ128rmbkz + 35108U, // VUNPCKLPDZ128rmk + 133220U, // VUNPCKLPDZ128rmkz + 96U, // VUNPCKLPDZ128rr + 166180U, // VUNPCKLPDZ128rrk + 198756U, // VUNPCKLPDZ128rrkz + 320U, // VUNPCKLPDZ256rm + 6528U, // VUNPCKLPDZ256rmb + 2165028U, // VUNPCKLPDZ256rmbk + 2197604U, // VUNPCKLPDZ256rmbkz + 231716U, // VUNPCKLPDZ256rmk + 264292U, // VUNPCKLPDZ256rmkz + 96U, // VUNPCKLPDZ256rr + 166180U, // VUNPCKLPDZ256rrk + 198756U, // VUNPCKLPDZ256rrkz + 416U, // VUNPCKLPDZrm + 8576U, // VUNPCKLPDZrmb + 3213604U, // VUNPCKLPDZrmbk + 3246180U, // VUNPCKLPDZrmbkz + 297252U, // VUNPCKLPDZrmk + 329828U, // VUNPCKLPDZrmkz + 96U, // VUNPCKLPDZrr + 166180U, // VUNPCKLPDZrrk + 198756U, // VUNPCKLPDZrrkz + 352U, // VUNPCKLPDrm + 96U, // VUNPCKLPDrr + 320U, // VUNPCKLPSYrm + 96U, // VUNPCKLPSYrr + 352U, // VUNPCKLPSZ128rm + 6592U, // VUNPCKLPSZ128rmb + 2492708U, // VUNPCKLPSZ128rmbk + 2525284U, // VUNPCKLPSZ128rmbkz + 35108U, // VUNPCKLPSZ128rmk + 133220U, // VUNPCKLPSZ128rmkz + 96U, // VUNPCKLPSZ128rr + 166180U, // VUNPCKLPSZ128rrk + 198756U, // VUNPCKLPSZ128rrkz + 320U, // VUNPCKLPSZ256rm + 8640U, // VUNPCKLPSZ256rmb + 3541284U, // VUNPCKLPSZ256rmbk + 3573860U, // VUNPCKLPSZ256rmbkz + 231716U, // VUNPCKLPSZ256rmk + 264292U, // VUNPCKLPSZ256rmkz + 96U, // VUNPCKLPSZ256rr + 166180U, // VUNPCKLPSZ256rrk + 198756U, // VUNPCKLPSZ256rrkz + 416U, // VUNPCKLPSZrm + 10688U, // VUNPCKLPSZrmb + 5638436U, // VUNPCKLPSZrmbk + 5671012U, // VUNPCKLPSZrmbkz + 297252U, // VUNPCKLPSZrmk + 329828U, // VUNPCKLPSZrmkz + 96U, // VUNPCKLPSZrr + 166180U, // VUNPCKLPSZrrk + 198756U, // VUNPCKLPSZrrkz + 352U, // VUNPCKLPSrm + 96U, // VUNPCKLPSrr + 320U, // VXORPDYrm + 96U, // VXORPDYrr + 352U, // VXORPDZ128rm + 4480U, // VXORPDZ128rmb + 1116452U, // VXORPDZ128rmbk + 1149028U, // VXORPDZ128rmbkz + 35108U, // VXORPDZ128rmk + 133220U, // VXORPDZ128rmkz + 96U, // VXORPDZ128rr + 166180U, // VXORPDZ128rrk + 198756U, // VXORPDZ128rrkz + 320U, // VXORPDZ256rm + 6528U, // VXORPDZ256rmb + 2165028U, // VXORPDZ256rmbk + 2197604U, // VXORPDZ256rmbkz + 231716U, // VXORPDZ256rmk + 264292U, // VXORPDZ256rmkz + 96U, // VXORPDZ256rr + 166180U, // VXORPDZ256rrk + 198756U, // VXORPDZ256rrkz + 416U, // VXORPDZrm + 8576U, // VXORPDZrmb + 3213604U, // VXORPDZrmbk + 3246180U, // VXORPDZrmbkz + 297252U, // VXORPDZrmk + 329828U, // VXORPDZrmkz + 96U, // VXORPDZrr + 166180U, // VXORPDZrrk + 198756U, // VXORPDZrrkz + 352U, // VXORPDrm + 96U, // VXORPDrr + 320U, // VXORPSYrm + 96U, // VXORPSYrr + 352U, // VXORPSZ128rm + 6592U, // VXORPSZ128rmb + 2492708U, // VXORPSZ128rmbk + 2525284U, // VXORPSZ128rmbkz + 35108U, // VXORPSZ128rmk + 133220U, // VXORPSZ128rmkz + 96U, // VXORPSZ128rr + 166180U, // VXORPSZ128rrk + 198756U, // VXORPSZ128rrkz + 320U, // VXORPSZ256rm + 8640U, // VXORPSZ256rmb + 3541284U, // VXORPSZ256rmbk + 3573860U, // VXORPSZ256rmbkz + 231716U, // VXORPSZ256rmk + 264292U, // VXORPSZ256rmkz + 96U, // VXORPSZ256rr + 166180U, // VXORPSZ256rrk + 198756U, // VXORPSZ256rrkz + 416U, // VXORPSZrm + 10688U, // VXORPSZrmb + 5638436U, // VXORPSZrmbk + 5671012U, // VXORPSZrmbkz + 297252U, // VXORPSZrmk + 329828U, // VXORPSZrmkz + 96U, // VXORPSZrr + 166180U, // VXORPSZrrk + 198756U, // VXORPSZrrkz + 352U, // VXORPSrm + 96U, // VXORPSrr + 0U, // VZEROALL + 0U, // VZEROUPPER + 0U, // WAIT + 0U, // WBINVD + 0U, // WBNOINVD + 0U, // WRFSBASE + 0U, // WRFSBASE64 + 0U, // WRGSBASE + 0U, // WRGSBASE64 + 0U, // WRMSR + 0U, // WRPKRUr + 0U, // WRSSD + 0U, // WRSSQ + 0U, // WRUSSD + 0U, // WRUSSQ + 0U, // XABORT + 0U, // XACQUIRE_PREFIX + 0U, // XADD16rm + 0U, // XADD16rr + 0U, // XADD32rm + 0U, // XADD32rr + 0U, // XADD64rm + 0U, // XADD64rr + 0U, // XADD8rm + 0U, // XADD8rr + 0U, // XBEGIN_2 + 0U, // XBEGIN_4 + 0U, // XCHG16ar + 0U, // XCHG16rm + 0U, // XCHG16rr + 0U, // XCHG32ar + 0U, // XCHG32rm + 0U, // XCHG32rr + 0U, // XCHG64ar + 0U, // XCHG64rm + 0U, // XCHG64rr + 0U, // XCHG8rm + 0U, // XCHG8rr + 0U, // XCH_F + 0U, // XCRYPTCBC + 0U, // XCRYPTCFB + 0U, // XCRYPTCTR + 0U, // XCRYPTECB + 0U, // XCRYPTOFB + 0U, // XEND + 0U, // XGETBV + 0U, // XLAT + 0U, // XOR16i16 + 0U, // XOR16mi + 0U, // XOR16mi8 + 0U, // XOR16mr + 0U, // XOR16ri + 0U, // XOR16ri8 + 0U, // XOR16rm + 0U, // XOR16rr + 0U, // XOR16rr_REV + 0U, // XOR32i32 + 0U, // XOR32mi + 0U, // XOR32mi8 + 0U, // XOR32mr + 0U, // XOR32ri + 0U, // XOR32ri8 + 0U, // XOR32rm + 0U, // XOR32rr + 0U, // XOR32rr_REV + 0U, // XOR64i32 + 0U, // XOR64mi32 + 0U, // XOR64mi8 + 0U, // XOR64mr + 0U, // XOR64ri32 + 0U, // XOR64ri8 + 0U, // XOR64rm + 0U, // XOR64rr + 0U, // XOR64rr_REV + 0U, // XOR8i8 + 0U, // XOR8mi + 0U, // XOR8mi8 + 0U, // XOR8mr + 0U, // XOR8ri + 0U, // XOR8ri8 + 0U, // XOR8rm + 0U, // XOR8rr + 0U, // XOR8rr_REV + 0U, // XORPDrm + 0U, // XORPDrr + 0U, // XORPSrm + 0U, // XORPSrr + 0U, // XRELEASE_PREFIX + 0U, // XRSTOR + 0U, // XRSTOR64 + 0U, // XRSTORS + 0U, // XRSTORS64 + 0U, // XSAVE + 0U, // XSAVE64 + 0U, // XSAVEC + 0U, // XSAVEC64 + 0U, // XSAVEOPT + 0U, // XSAVEOPT64 + 0U, // XSAVES + 0U, // XSAVES64 + 0U, // XSETBV + 0U, // XSHA1 + 0U, // XSHA256 + 0U, // XSTORE + 0U, // XTEST + }; + + unsigned int opcode = MCInst_getOpcode(MI); + // printf("opcode = %u\n", opcode); + + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[opcode] << 0; + Bits |= (uint64_t)OpInfo1[opcode] << 32; +#ifndef CAPSTONE_DIET + SStream_concat0(O, AsmStrs+(Bits & 16383)-1); +#endif + + + // Fragment 0 encoded into 6 bits for 52 unique commands. + // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 14) & 63)); + switch ((uint32_t)((Bits >> 14) & 63)) { + default: // unreachable + case 0: + // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... + return; + break; + case 1: + // AAD8i8, AAM8i8, ADC16i16, ADC16rr_REV, ADC32i32, ADC32rr_REV, ADC64i32... + printOperand(MI, 0, O); + break; + case 2: + // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, ADD_FI16m, AND... + printi16mem(MI, 0, O); + break; + case 3: + // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32... + printOperand(MI, 1, O); + break; + case 4: + // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, ADD_FI32m, AND... + printi32mem(MI, 0, O); + break; + case 5: + // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,... + printi64mem(MI, 0, O); + break; + case 6: + // ADC8mi, ADC8mi8, ADC8mr, ADD8mi, ADD8mi8, ADD8mr, AND8mi, AND8mi8, AND... + printi8mem(MI, 0, O); + break; + case 7: + // ADD_F32m, DIVR_F32m, DIV_F32m, EXTRACTPSmr, FCOM32m, FCOMP32m, FLDENVm... + printf32mem(MI, 0, O); + break; + case 8: + // ADD_F64m, DIVR_F64m, DIV_F64m, FCOM64m, FCOMP64m, LD_F64m, MOVHPDmr, M... + printf64mem(MI, 0, O); + break; + case 9: + // BNDMOV64mr, CMPXCHG16B, MOVDQAmr, MOVDQUmr, VEXTRACTI128mr, VEXTRACTI3... + printi128mem(MI, 0, O); + break; + case 10: + // BNDSTXmr + printanymem(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 11: + // CALL64pcrel32, CALLpcrel16, CALLpcrel32, JAE_1, JAE_2, JAE_4, JA_1, JA... + printPCRelImm(MI, 0, O); + return; + break; + case 12: + // CMPPDrmi, CMPPSrmi, CMPSDrm, CMPSDrm_Int, CMPSSrm, CMPSSrm_Int, VCMPPD... + printSSEAVXCC(MI, 7, O); + break; + case 13: + // CMPPDrri, CMPPSrri, CMPSDrr, CMPSDrr_Int, CMPSSrr, CMPSSrr_Int, VCMPPD... + printSSEAVXCC(MI, 3, O); + break; + case 14: + // CMPSB + printSrcIdx8(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx8(MI, 0, O); + return; + break; + case 15: + // CMPSL + printSrcIdx32(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx32(MI, 0, O); + return; + break; + case 16: + // CMPSQ + printSrcIdx64(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx64(MI, 0, O); + return; + break; + case 17: + // CMPSW + printSrcIdx16(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx16(MI, 0, O); + return; + break; + case 18: + // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, FXR... + printopaquemem(MI, 0, O); + return; + break; + case 19: + // FBLDm, FBSTPm, LD_F80m, ST_FP80m + printf80mem(MI, 0, O); + return; + break; + case 20: + // IN16ri, IN32ri, IN8ri, INT, OUT16ir, OUT32ir, OUT8ir + printU8Imm(MI, 0, O); + break; + case 21: + // INSB, MOVSB, SCASB, STOSB + printDstIdx8(MI, 0, O); + break; + case 22: + // INSL, MOVSL, SCASL, STOSL + printDstIdx32(MI, 0, O); + break; + case 23: + // INSW, MOVSW, SCASW, STOSW + printDstIdx16(MI, 0, O); + break; + case 24: + // LODSB, OUTSB + printSrcIdx8(MI, 0, O); + return; + break; + case 25: + // LODSL, OUTSL + printSrcIdx32(MI, 0, O); + return; + break; + case 26: + // LODSQ + printSrcIdx64(MI, 0, O); + return; + break; + case 27: + // LODSW, OUTSW + printSrcIdx16(MI, 0, O); + return; + break; + case 28: + // MOV16ao16, MOV16ao32, MOV16ao64, MOV16o16a, MOV16o32a, MOV16o64a + printMemOffs16(MI, 0, O); + break; + case 29: + // MOV32ao16, MOV32ao32, MOV32ao64, MOV32o16a, MOV32o32a, MOV32o64a + printMemOffs32(MI, 0, O); + break; + case 30: + // MOV64ao32, MOV64ao64, MOV64o32a, MOV64o64a + printMemOffs64(MI, 0, O); + break; + case 31: + // MOV8ao16, MOV8ao32, MOV8ao64, MOV8o16a, MOV8o32a, MOV8o64a + printMemOffs8(MI, 0, O); + break; + case 32: + // MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVNTPDmr, MOVNTPSmr, MOVUPDmr, MOVUPSm... + printf128mem(MI, 0, O); + break; + case 33: + // MOVSQ, SCASQ, STOSQ + printDstIdx64(MI, 0, O); + break; + case 34: + // VCMPPDZ128rmbik, VCMPPDZ128rmik, VCMPPDZ256rmbik, VCMPPDZ256rmik, VCMP... + printSSEAVXCC(MI, 8, O); + break; + case 35: + // VCMPPDZ128rrik, VCMPPDZ256rrik, VCMPPDZrribk, VCMPPDZrrik, VCMPPSZ128r... + printSSEAVXCC(MI, 4, O); + break; + case 36: + // VCOMPRESSPDZ256mr, VCOMPRESSPDZ256mrk, VCOMPRESSPSZ256mr, VCOMPRESSPSZ... + printf256mem(MI, 0, O); + break; + case 37: + // VCOMPRESSPDZmr, VCOMPRESSPDZmrk, VCOMPRESSPSZmr, VCOMPRESSPSZmrk, VMOV... + printf512mem(MI, 0, O); + break; + case 38: + // VEXTRACTI32x8Zmr, VEXTRACTI32x8Zmrk, VEXTRACTI64x4Zmr, VEXTRACTI64x4Zm... + printi256mem(MI, 0, O); + break; + case 39: + // VMOVDQA32Zmr, VMOVDQA32Zmrk, VMOVDQA64Zmr, VMOVDQA64Zmrk, VMOVDQU16Zmr... + printi512mem(MI, 0, O); + break; + case 40: + // VPCOMBmi, VPCOMDmi, VPCOMQmi, VPCOMUBmi, VPCOMUDmi, VPCOMUQmi, VPCOMUW... + printXOPCC(MI, 7, O); + break; + case 41: + // VPCOMBri, VPCOMDri, VPCOMQri, VPCOMUBri, VPCOMUDri, VPCOMUQri, VPCOMUW... + printXOPCC(MI, 3, O); + break; + case 42: + // VPSCATTERDDZ128mr, VPSCATTERDQZ128mr, VPSCATTERQDZ256mr, VPSCATTERQQZ1... + printi128mem(MI, 1, O); + SStream_concat0(O, " {"); + printOperand(MI, 6, O); + SStream_concat0(O, "}, "); + printOperand(MI, 7, O); + return; + break; + case 43: + // VPSCATTERDDZ256mr, VPSCATTERDQZ256mr, VPSCATTERQDZmr, VPSCATTERQQZ256m... + printi256mem(MI, 1, O); + SStream_concat0(O, " {"); + printOperand(MI, 6, O); + SStream_concat0(O, "}, "); + printOperand(MI, 7, O); + return; + break; + case 44: + // VPSCATTERDDZmr, VPSCATTERDQZmr, VPSCATTERQQZmr, VSCATTERDPDZmr, VSCATT... + printi512mem(MI, 1, O); + SStream_concat0(O, " {"); + printOperand(MI, 6, O); + SStream_concat0(O, "}, "); + printOperand(MI, 7, O); + return; + break; + case 45: + // VPSCATTERQDZ128mr, VSCATTERQPSZ128mr + printi64mem(MI, 1, O); + SStream_concat0(O, " {"); + printOperand(MI, 6, O); + SStream_concat0(O, "}, "); + printOperand(MI, 7, O); + return; + break; + case 46: + // XADD16rm, XCHG16rm + printi16mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 47: + // XADD16rr, XADD32rr, XADD64rr, XADD8rr + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 48: + // XADD32rm, XCHG32rm + printi32mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 49: + // XADD64rm, XCHG64rm + printi64mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 50: + // XADD8rm, XCHG8rm + printi8mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 51: + // XCHG16rr, XCHG32rr, XCHG64rr, XCHG8rr + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + } + + + // Fragment 1 encoded into 5 bits for 25 unique commands. + // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 20) & 31)); + switch ((uint32_t)((Bits >> 20) & 31)) { + default: // unreachable + case 0: + // AAD8i8, AAM8i8, ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i... + return; + break; + case 1: + // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16... + SStream_concat0(O, ", "); + break; + case 2: + // ADD_FrST0, DIVR_FrST0, DIV_FrST0, FPNCEST0r, MUL_FrST0, SUBR_FrST0, SU... + SStream_concat0(O, ", st(0)"); + op_addReg(MI, X86_REG_ST0); + return; + break; + case 3: + // CMPPDrmi, CMPPDrri, VCMPPDYrmi, VCMPPDYrri, VCMPPDZ128rmbi, VCMPPDZ128... + SStream_concat0(O, "pd\t"); + printOperand(MI, 0, O); + break; + case 4: + // CMPPSrmi, CMPPSrri, VCMPPSYrmi, VCMPPSYrri, VCMPPSZ128rmbi, VCMPPSZ128... + SStream_concat0(O, "ps\t"); + printOperand(MI, 0, O); + break; + case 5: + // CMPSDrm, CMPSDrm_Int, CMPSDrr, CMPSDrr_Int, VCMPSDZrm, VCMPSDZrm_Int, ... + SStream_concat0(O, "sd\t"); + printOperand(MI, 0, O); + break; + case 6: + // CMPSSrm, CMPSSrm_Int, CMPSSrr, CMPSSrr_Int, VCMPSSZrm, VCMPSSZrm_Int, ... + SStream_concat0(O, "ss\t"); + printOperand(MI, 0, O); + break; + case 7: + // FARJMP16i, FARJMP32i + SStream_concat0(O, ":"); + printOperand(MI, 0, O); + return; + break; + case 8: + // INSB, INSL, INSW + SStream_concat0(O, ", dx"); + op_addReg(MI, X86_REG_DX); + return; + break; + case 9: + // MOV16o16a, MOV16o32a, MOV16o64a, OUT16ir, STOSW, XCHG16ar + SStream_concat0(O, ", ax"); + op_addReg(MI, X86_REG_AX); + return; + break; + case 10: + // MOV32o16a, MOV32o32a, MOV32o64a, OUT32ir, STOSL, XCHG32ar + SStream_concat0(O, ", eax"); + op_addReg(MI, X86_REG_EAX); + return; + break; + case 11: + // MOV64o32a, MOV64o64a, STOSQ, XCHG64ar + SStream_concat0(O, ", rax"); + op_addReg(MI, X86_REG_RAX); + return; + break; + case 12: + // MOV8o16a, MOV8o32a, MOV8o64a, OUT8ir, STOSB + SStream_concat0(O, ", al"); + op_addReg(MI, X86_REG_AL); + return; + break; + case 13: + // RCL16mCL, RCL16rCL, RCL32mCL, RCL32rCL, RCL64mCL, RCL64rCL, RCL8mCL, R... + SStream_concat0(O, ", cl"); + op_addReg(MI, X86_REG_CL); + return; + break; + case 14: + // RCL16r1, RCL32r1, RCL64r1, RCL8r1, RCR16m1, RCR16r1, RCR32m1, RCR32r1,... + SStream_concat0(O, ", 1"); + op_addImm(MI, 1); + return; + break; + case 15: + // V4FMADDPSrmk, V4FMADDPSrmkz, V4FMADDSSrmk, V4FMADDSSrmkz, V4FNMADDPSrm... + SStream_concat0(O, " {"); + break; + case 16: + // VGATHERPF0DPDm, VGATHERPF0DPSm, VGATHERPF0QPDm, VGATHERPF0QPSm, VGATHE... + SStream_concat0(O, "}, "); + break; + case 17: + // VPCMPBZ128rmi, VPCMPBZ128rmik, VPCMPBZ128rri, VPCMPBZ128rrik, VPCMPBZ2... + SStream_concat0(O, "b\t"); + printOperand(MI, 0, O); + break; + case 18: + // VPCMPDZ128rmi, VPCMPDZ128rmib, VPCMPDZ128rmibk, VPCMPDZ128rmik, VPCMPD... + SStream_concat0(O, "d\t"); + printOperand(MI, 0, O); + break; + case 19: + // VPCMPQZ128rmi, VPCMPQZ128rmib, VPCMPQZ128rmibk, VPCMPQZ128rmik, VPCMPQ... + SStream_concat0(O, "q\t"); + printOperand(MI, 0, O); + break; + case 20: + // VPCMPUBZ128rmi, VPCMPUBZ128rmik, VPCMPUBZ128rri, VPCMPUBZ128rrik, VPCM... + SStream_concat0(O, "ub\t"); + printOperand(MI, 0, O); + break; + case 21: + // VPCMPUDZ128rmi, VPCMPUDZ128rmib, VPCMPUDZ128rmibk, VPCMPUDZ128rmik, VP... + SStream_concat0(O, "ud\t"); + printOperand(MI, 0, O); + break; + case 22: + // VPCMPUQZ128rmi, VPCMPUQZ128rmib, VPCMPUQZ128rmibk, VPCMPUQZ128rmik, VP... + SStream_concat0(O, "uq\t"); + printOperand(MI, 0, O); + break; + case 23: + // VPCMPUWZ128rmi, VPCMPUWZ128rmik, VPCMPUWZ128rri, VPCMPUWZ128rrik, VPCM... + SStream_concat0(O, "uw\t"); + printOperand(MI, 0, O); + break; + case 24: + // VPCMPWZ128rmi, VPCMPWZ128rmik, VPCMPWZ128rri, VPCMPWZ128rrik, VPCMPWZ2... + SStream_concat0(O, "w\t"); + printOperand(MI, 0, O); + break; + } + + + // Fragment 2 encoded into 6 bits for 38 unique commands. + // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 25) & 63)); + switch ((uint32_t)((Bits >> 25) & 63)) { + default: // unreachable + case 0: + // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC... + printOperand(MI, 5, O); + break; + case 1: + // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A... + printOperand(MI, 2, O); + break; + case 2: + // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r... + printi16mem(MI, 2, O); + break; + case 3: + // ADC32rm, ADCX32rm, ADD32rm, ADOX32rm, AND32rm, CMOVA32rm, CMOVAE32rm, ... + printi32mem(MI, 2, O); + break; + case 4: + // ADC64rm, ADCX64rm, ADD64rm, ADOX64rm, AND64rm, CMOVA64rm, CMOVAE64rm, ... + printi64mem(MI, 2, O); + break; + case 5: + // ADC8rm, ADD8rm, AND8rm, CRC32r32m8, CRC32r64m8, OR8rm, PINSRBrm, SBB8r... + printi8mem(MI, 2, O); + break; + case 6: + // ADDPDrm, ADDPSrm, ADDSUBPDrm, ADDSUBPSrm, ANDNPDrm, ANDNPSrm, ANDPDrm,... + printf128mem(MI, 2, O); + break; + case 7: + // ADDSDrm, ADDSDrm_Int, CMPSDrm_alt, CVTSD2SSrm_Int, DIVSDrm, DIVSDrm_In... + printf64mem(MI, 2, O); + break; + case 8: + // ADDSSrm, ADDSSrm_Int, CMPSSrm_alt, CVTSS2SDrm_Int, DIVSSrm, DIVSSrm_In... + printf32mem(MI, 2, O); + break; + case 9: + // AESDECLASTrm, AESDECrm, AESENCLASTrm, AESENCrm, GF2P8AFFINEINVQBrmi, G... + printi128mem(MI, 2, O); + break; + case 10: + // AESIMCrm, AESKEYGENASSIST128rm, BNDMOV64rm, CVTDQ2PSrm, INVEPT32, INVE... + printi128mem(MI, 1, O); + break; + case 11: + // AESIMCrr, AESKEYGENASSIST128rr, ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr... + printOperand(MI, 1, O); + break; + case 12: + // BEXTR32rm, BEXTRI32mi, BLCFILL32rm, BLCI32rm, BLCIC32rm, BLCMSK32rm, B... + printi32mem(MI, 1, O); + break; + case 13: + // BEXTR64rm, BEXTRI64mi, BLCFILL64rm, BLCI64rm, BLCIC64rm, BLCMSK64rm, B... + printi64mem(MI, 1, O); + break; + case 14: + // BNDCL32rm, BNDCL64rm, BNDCN32rm, BNDCN64rm, BNDCU32rm, BNDCU64rm, BNDL... + printanymem(MI, 1, O); + return; + break; + case 15: + // BSF16rm, BSR16rm, CMP16rm, IMUL16rmi, IMUL16rmi8, KMOVWkm, LAR16rm, LA... + printi16mem(MI, 1, O); + break; + case 16: + // CMP8rm, KMOVBkm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX32... + printi8mem(MI, 1, O); + return; + break; + case 17: + // CMPPDrmi, CMPPDrri, CMPPSrmi, CMPPSrri, CMPSDrm, CMPSDrm_Int, CMPSDrr,... + SStream_concat0(O, ", "); + break; + case 18: + // COMISDrm, COMISDrm_Int, CVTPS2PDrm, CVTSD2SI64rm_Int, CVTSD2SIrm_Int, ... + printf64mem(MI, 1, O); + break; + case 19: + // COMISSrm, COMISSrm_Int, CVTSS2SDrm, CVTSS2SI64rm_Int, CVTSS2SIrm_Int, ... + printf32mem(MI, 1, O); + break; + case 20: + // CVTPD2DQrm, CVTPD2PSrm, CVTPS2DQrm, CVTTPD2DQrm, CVTTPS2DQrm, MMX_CVTP... + printf128mem(MI, 1, O); + break; + case 21: + // EXTRQI, MMX_PSLLDri, MMX_PSLLQri, MMX_PSLLWri, MMX_PSRADri, MMX_PSRAWr... + printU8Imm(MI, 2, O); + break; + case 22: + // FARCALL16i, FARCALL32i, NOOP19rr + printOperand(MI, 0, O); + return; + break; + case 23: + // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm... + printopaquemem(MI, 1, O); + return; + break; + case 24: + // MOVDIR64B16, MOVDIR64B32, MOVDIR64B64, VCVTDQ2PSZrm, VCVTQQ2PDZrm, VCV... + printi512mem(MI, 1, O); + break; + case 25: + // MOVSB + printSrcIdx8(MI, 1, O); + return; + break; + case 26: + // MOVSL + printSrcIdx32(MI, 1, O); + return; + break; + case 27: + // MOVSQ + printSrcIdx64(MI, 1, O); + return; + break; + case 28: + // MOVSW + printSrcIdx16(MI, 1, O); + return; + break; + case 29: + // RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi, ... + printU8Imm(MI, 5, O); + return; + break; + case 30: + // VBROADCASTF32X8rm, VBROADCASTF64X4rm, VCVTPD2DQYrm, VCVTPD2DQZ256rm, V... + printf256mem(MI, 1, O); + break; + case 31: + // VBROADCASTI32X8rm, VBROADCASTI64X4rm, VCVTDQ2PDZrm, VCVTDQ2PSYrm, VCVT... + printi256mem(MI, 1, O); + break; + case 32: + // VCMPPDZ128rmbik, VCMPPDZ128rmik, VCMPPDZ128rrik, VCMPPDZ256rmbik, VCMP... + SStream_concat0(O, " {"); + printOperand(MI, 1, O); + SStream_concat0(O, "}, "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 33: + // VCVTPD2DQZrm, VCVTPD2PSZrm, VCVTPD2QQZrm, VCVTPD2UDQZrm, VCVTPD2UQQZrm... + printf512mem(MI, 1, O); + break; + case 34: + // VGATHERDPDYrm, VGATHERDPSYrm, VGATHERQPDYrm, VPGATHERDDYrm, VPGATHERDQ... + printi256mem(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 8, O); + return; + break; + case 35: + // VGATHERDPDZ128rm, VGATHERDPDZ256rm, VGATHERDPDZrm, VGATHERDPSZ128rm, V... + printOperand(MI, 3, O); + SStream_concat0(O, "}, "); + break; + case 36: + // VGATHERDPDrm, VGATHERDPSrm, VGATHERQPDrm, VGATHERQPSYrm, VPGATHERDDrm,... + printi128mem(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 8, O); + return; + break; + case 37: + // VGATHERQPSrm, VPGATHERQDrm + printi64mem(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 8, O); + return; + break; + } + + + // Fragment 3 encoded into 6 bits for 36 unique commands. + // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 31) & 63)); + switch ((uint32_t)((Bits >> 31) & 63)) { + default: // unreachable + case 0: + // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16... + return; + break; + case 1: + // AESKEYGENASSIST128rm, AESKEYGENASSIST128rr, ANDN32rm, ANDN32rr, ANDN64... + SStream_concat0(O, ", "); + break; + case 2: + // BLENDVPDrm0, BLENDVPDrr0, BLENDVPSrm0, BLENDVPSrr0, PBLENDVBrm0, PBLEN... + SStream_concat0(O, ", xmm0"); + return; + break; + case 3: + // CMPPDrmi, CMPPSrmi + printf128mem(MI, 2, O); + return; + break; + case 4: + // CMPPDrri, CMPPSrri, CMPSDrr, CMPSDrr_Int, CMPSSrr, CMPSSrr_Int + printOperand(MI, 2, O); + return; + break; + case 5: + // CMPSDrm, CMPSDrm_Int + printf64mem(MI, 2, O); + return; + break; + case 6: + // CMPSSrm, CMPSSrm_Int + printf32mem(MI, 2, O); + return; + break; + case 7: + // SHLD16mrCL, SHLD16rrCL, SHLD32mrCL, SHLD32rrCL, SHLD64mrCL, SHLD64rrCL... + SStream_concat0(O, ", cl"); + op_addReg(MI, X86_REG_CL); + return; + break; + case 8: + // V4FMADDPSrmk, V4FMADDSSrmk, V4FNMADDPSrmk, V4FNMADDSSrmk, VADDPDZ128rm... + SStream_concat0(O, "}, "); + break; + case 9: + // V4FMADDPSrmkz, V4FMADDSSrmkz, V4FNMADDPSrmkz, V4FNMADDSSrmkz, VADDPDZ1... + SStream_concat0(O, "} {z}, "); + op_addAvxZeroOpmask(MI); + break; + case 10: + // VCMPPDYrmi, VCMPPDYrri, VCMPPDZ128rmbi, VCMPPDZ128rmi, VCMPPDZ128rri, ... + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 11: + // VCMPPDZ128rmbik, VCMPPDZ256rmbik, VCMPPDZrmbik, VCMPSDZrm_Intk + printf64mem(MI, 3, O); + break; + case 12: + // VCMPPDZ128rmik, VCMPPSZ128rmik + printf128mem(MI, 3, O); + return; + break; + case 13: + // VCMPPDZ128rrik, VCMPPDZ256rrik, VCMPPDZrribk, VCMPPDZrrik, VCMPPSZ128r... + printOperand(MI, 3, O); + break; + case 14: + // VCMPPDZ256rmik, VCMPPSZ256rmik + printf256mem(MI, 3, O); + return; + break; + case 15: + // VCMPPDZrmik, VCMPPSZrmik + printf512mem(MI, 3, O); + return; + break; + case 16: + // VCMPPSZ128rmbik, VCMPPSZ256rmbik, VCMPPSZrmbik, VCMPSSZrm_Intk + printf32mem(MI, 3, O); + break; + case 17: + // VCOMISDZrrb, VCOMISSZrrb, VCVTPH2PSZrrb, VCVTPS2PDZrrb, VCVTTPD2DQZrrb... + SStream_concat0(O, ", {sae}"); + op_addAvxSae(MI); + return; + break; + case 18: + // VCVTDQ2PDZ128rmb, VCVTPD2DQZ128rmb, VCVTPD2PSZ128rmb, VCVTPD2QQZ128rmb... + SStream_concat0(O, "{1to2}"); + return; + break; + case 19: + // VCVTDQ2PDZ256rmb, VCVTDQ2PSZ128rmb, VCVTPD2DQZ256rmb, VCVTPD2PSZ256rmb... + SStream_concat0(O, "{1to4}"); + return; + break; + case 20: + // VCVTDQ2PDZrmb, VCVTDQ2PSZ256rmb, VCVTPD2DQZrmb, VCVTPD2PSZrmb, VCVTPD2... + SStream_concat0(O, "{1to8}"); + return; + break; + case 21: + // VCVTDQ2PSZrmb, VCVTPS2DQZrmb, VCVTPS2UDQZrmb, VCVTTPS2DQZrmb, VCVTTPS2... + SStream_concat0(O, "{1to16}"); + return; + break; + case 22: + // VCVTPS2PHZrrb, VGETMANTPDZrrib, VGETMANTPSZrrib, VREDUCEPDZrrib, VREDU... + SStream_concat0(O, ", {sae}, "); + op_addAvxSae(MI); + printU8Imm(MI, 2, O); + return; + break; + case 23: + // VFPCLASSPDZ128rmb, VGETMANTPDZ128rmbi, VPERMILPDZ128mbi, VPROLQZ128mbi... + SStream_concat0(O, "{1to2}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_2); + printU8Imm(MI, 6, O); + return; + break; + case 24: + // VFPCLASSPDZ256rmb, VFPCLASSPSZ128rmb, VGETMANTPDZ256rmbi, VGETMANTPSZ1... + SStream_concat0(O, "{1to4}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_4); + printU8Imm(MI, 6, O); + return; + break; + case 25: + // VFPCLASSPDZrmb, VFPCLASSPSZ256rmb, VGETMANTPDZrmbi, VGETMANTPSZ256rmbi... + SStream_concat0(O, "{1to8}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_8); + printU8Imm(MI, 6, O); + return; + break; + case 26: + // VFPCLASSPSZrmb, VGETMANTPSZrmbi, VPERMILPSZmbi, VPROLDZmbi, VPRORDZmbi... + SStream_concat0(O, "{1to16}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_16); + printU8Imm(MI, 6, O); + return; + break; + case 27: + // VGATHERDPDZ128rm, VGATHERDPSZ128rm, VGATHERQPDZ128rm, VGATHERQPSZ256rm... + printi128mem(MI, 4, O); + return; + break; + case 28: + // VGATHERDPDZ256rm, VGATHERDPSZ256rm, VGATHERQPDZ256rm, VGATHERQPSZrm, V... + printi256mem(MI, 4, O); + return; + break; + case 29: + // VGATHERDPDZrm, VGATHERDPSZrm, VGATHERQPDZrm, VPGATHERDDZrm, VPGATHERDQ... + printi512mem(MI, 4, O); + return; + break; + case 30: + // VGATHERQPSZ128rm, VPGATHERQDZ128rm + printi64mem(MI, 4, O); + return; + break; + case 31: + // VPCMPBZ128rmik, VPCMPDZ128rmik, VPCMPQZ128rmik, VPCMPUBZ128rmik, VPCMP... + printi128mem(MI, 3, O); + return; + break; + case 32: + // VPCMPBZ256rmik, VPCMPDZ256rmik, VPCMPQZ256rmik, VPCMPUBZ256rmik, VPCMP... + printi256mem(MI, 3, O); + return; + break; + case 33: + // VPCMPBZrmik, VPCMPDZrmik, VPCMPQZrmik, VPCMPUBZrmik, VPCMPUDZrmik, VPC... + printi512mem(MI, 3, O); + return; + break; + case 34: + // VPCMPDZ128rmibk, VPCMPDZ256rmibk, VPCMPDZrmibk, VPCMPUDZ128rmibk, VPCM... + printi32mem(MI, 3, O); + break; + case 35: + // VPCMPQZ128rmibk, VPCMPQZ256rmibk, VPCMPQZrmibk, VPCMPUQZ128rmibk, VPCM... + printi64mem(MI, 3, O); + break; + } + + + // Fragment 4 encoded into 6 bits for 39 unique commands. + // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 37) & 63)); + switch ((uint32_t)((Bits >> 37) & 63)) { + default: // unreachable + case 0: + // AESKEYGENASSIST128rm, EXTRACTPSmr, MMX_PSHUFWmi, PCMPESTRIrm, PCMPESTR... + printU8Imm(MI, 6, O); + return; + break; + case 1: + // AESKEYGENASSIST128rr, EXTRACTPSrr, KSHIFTLBri, KSHIFTLDri, KSHIFTLQri,... + printU8Imm(MI, 2, O); + return; + break; + case 2: + // ANDN32rm, MULX32rm, PDEP32rm, PEXT32rm, VALIGNDZ128rmbi, VALIGNDZ256rm... + printi32mem(MI, 2, O); + break; + case 3: + // ANDN32rr, ANDN64rr, BEXTR32rr, BEXTR64rr, BEXTRI32ri, BEXTRI64ri, BZHI... + printOperand(MI, 2, O); + break; + case 4: + // ANDN64rm, MULX64rm, PDEP64rm, PEXT64rm, VALIGNQZ128rmbi, VALIGNQZ256rm... + printi64mem(MI, 2, O); + break; + case 5: + // BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZHI32rm, BZHI64rm, IMUL... + printOperand(MI, 6, O); + break; + case 6: + // BLENDPDrmi, BLENDPSrmi, CMPPDrmi_alt, CMPPSrmi_alt, CMPSDrm_alt, CMPSS... + printU8Imm(MI, 7, O); + return; + break; + case 7: + // BLENDPDrri, BLENDPSrri, CMPPDrri_alt, CMPPSrri_alt, CMPSDrr_alt, CMPSS... + printU8Imm(MI, 3, O); + break; + case 8: + // V4FMADDPSrm, V4FMADDSSrm, V4FNMADDPSrm, V4FNMADDSSrm, VBROADCASTF32X4Z... + printf128mem(MI, 3, O); + break; + case 9: + // V4FMADDPSrmk, V4FMADDPSrmkz, V4FMADDSSrmk, V4FMADDSSrmkz, V4FNMADDPSrm... + printOperand(MI, 3, O); + break; + case 10: + // VADDPDYrm, VADDPDZ256rm, VADDPSYrm, VADDPSZ256rm, VADDSUBPDYrm, VADDSU... + printf256mem(MI, 2, O); + break; + case 11: + // VADDPDZ128rm, VADDPDrm, VADDPSZ128rm, VADDPSrm, VADDSUBPDrm, VADDSUBPS... + printf128mem(MI, 2, O); + break; + case 12: + // VADDPDZ128rmb, VADDPDZ256rmb, VADDPDZrmb, VADDSDZrm, VADDSDZrm_Int, VA... + printf64mem(MI, 2, O); + break; + case 13: + // VADDPDZrm, VADDPSZrm, VANDNPDZrm, VANDNPSZrm, VANDPDZrm, VANDPSZrm, VB... + printf512mem(MI, 2, O); + break; + case 14: + // VADDPSZ128rmb, VADDPSZ256rmb, VADDPSZrmb, VADDSSZrm, VADDSSZrm_Int, VA... + printf32mem(MI, 2, O); + break; + case 15: + // VAESDECLASTYrm, VAESDECLASTZ256rm, VAESDECYrm, VAESDECZ256rm, VAESENCL... + printi256mem(MI, 2, O); + break; + case 16: + // VAESDECLASTZ128rm, VAESDECLASTrm, VAESDECZ128rm, VAESDECrm, VAESENCLAS... + printi128mem(MI, 2, O); + break; + case 17: + // VAESDECLASTZrm, VAESDECZrm, VAESENCLASTZrm, VAESENCZrm, VALIGNDZrmi, V... + printi512mem(MI, 2, O); + break; + case 18: + // VBROADCASTF32X2Z256mk, VBROADCASTF32X2Zmk, VBROADCASTSDZ256mk, VBROADC... + printf64mem(MI, 3, O); + break; + case 19: + // VBROADCASTF32X8rmk, VBROADCASTF64X4rmk, VCVTPD2DQZ256rmk, VCVTPD2PSZ25... + printf256mem(MI, 3, O); + break; + case 20: + // VBROADCASTI32X2Z128mk, VBROADCASTI32X2Z256mk, VBROADCASTI32X2Zmk, VCVT... + printi64mem(MI, 3, O); + break; + case 21: + // VBROADCASTI32X4Z256rmk, VBROADCASTI32X4rmk, VBROADCASTI64X2Z128rmk, VB... + printi128mem(MI, 3, O); + break; + case 22: + // VBROADCASTI32X8rmk, VBROADCASTI64X4rmk, VCVTDQ2PDZrmk, VCVTDQ2PSZ256rm... + printi256mem(MI, 3, O); + break; + case 23: + // VBROADCASTSSZ128mk, VBROADCASTSSZ256mk, VBROADCASTSSZmk, VCVTPS2DQZ128... + printf32mem(MI, 3, O); + break; + case 24: + // VCMPPDZ128rmbik, VPCMPQZ128rmibk, VPCMPUQZ128rmibk + SStream_concat0(O, "{1to2}"); + return; + break; + case 25: + // VCMPPDZ128rrik, VCMPPDZ256rrik, VCMPPDZrrik, VCMPPSZ128rrik, VCMPPSZ25... + return; + break; + case 26: + // VCMPPDZ256rmbik, VCMPPSZ128rmbik, VPCMPDZ128rmibk, VPCMPQZ256rmibk, VP... + SStream_concat0(O, "{1to4}"); + return; + break; + case 27: + // VCMPPDZrmbik, VCMPPSZ256rmbik, VPCMPDZ256rmibk, VPCMPQZrmibk, VPCMPUDZ... + SStream_concat0(O, "{1to8}"); + return; + break; + case 28: + // VCMPPDZrribk, VCMPPSZrribk, VCMPSDZrrb_Intk, VCMPSSZrrb_Intk + SStream_concat0(O, ", {sae}"); + op_addAvxSae(MI); + return; + break; + case 29: + // VCMPPSZrmbik, VPCMPDZrmibk, VPCMPUDZrmibk + SStream_concat0(O, "{1to16}"); + return; + break; + case 30: + // VCVTDQ2PDZ128rmbk, VCVTDQ2PDZ256rmbk, VCVTDQ2PDZrmbk, VCVTDQ2PSZ128rmb... + printi32mem(MI, 3, O); + break; + case 31: + // VCVTDQ2PSZrmk, VCVTQQ2PDZrmk, VCVTQQ2PSZrmk, VCVTUDQ2PSZrmk, VCVTUQQ2P... + printi512mem(MI, 3, O); + break; + case 32: + // VCVTDQ2PSZrrb, VCVTPD2DQZrrb, VCVTPD2PSZrrb, VCVTPD2QQZrrb, VCVTPD2UDQ... + printRoundingControl(MI, 2, O); + return; + break; + case 33: + // VCVTPD2DQZrmk, VCVTPD2PSZrmk, VCVTPD2QQZrmk, VCVTPD2UDQZrmk, VCVTPD2UQ... + printf512mem(MI, 3, O); + break; + case 34: + // VCVTSI2SDZrrb_Int, VCVTSI2SSZrrb_Int, VCVTSI642SDZrrb_Int, VCVTSI642SS... + printRoundingControl(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 35: + // VGF2P8AFFINEINVQBZ128rmbi, VGF2P8AFFINEINVQBZ256rmbi, VGF2P8AFFINEINVQ... + printi8mem(MI, 2, O); + break; + case 36: + // VPBROADCASTBZ128mk, VPBROADCASTBZ256mk, VPBROADCASTBZmk + printi8mem(MI, 3, O); + return; + break; + case 37: + // VPBROADCASTWZ128mk, VPBROADCASTWZ256mk, VPBROADCASTWZmk, VPMOVSXBQZ128... + printi16mem(MI, 3, O); + return; + break; + case 38: + // VPBROADCASTWZ128mkz, VPBROADCASTWZ256mkz, VPBROADCASTWZmkz, VPINSRWZrm... + printi16mem(MI, 2, O); + break; + } + + + // Fragment 5 encoded into 4 bits for 12 unique commands. + // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 43) & 15)); + switch ((uint32_t)((Bits >> 43) & 15)) { + default: // unreachable + case 0: + // ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr, BEXTR32rm, BEXTR32rr, BEXTR64r... + return; + break; + case 1: + // INSERTQI, V4FMADDPSrmk, V4FMADDPSrmkz, V4FMADDSSrmk, V4FMADDSSrmkz, V4... + SStream_concat0(O, ", "); + break; + case 2: + // VADDPDZ128rmb, VANDNPDZ128rmb, VANDPDZ128rmb, VBLENDMPDZ128rmb, VCMPPD... + SStream_concat0(O, "{1to2}"); + return; + break; + case 3: + // VADDPDZ256rmb, VADDPSZ128rmb, VANDNPDZ256rmb, VANDNPSZ128rmb, VANDPDZ2... + SStream_concat0(O, "{1to4}"); + return; + break; + case 4: + // VADDPDZrmb, VADDPSZ256rmb, VANDNPDZrmb, VANDNPSZ256rmb, VANDPDZrmb, VA... + SStream_concat0(O, "{1to8}"); + return; + break; + case 5: + // VADDPSZrmb, VANDNPSZrmb, VANDPSZrmb, VBLENDMPSZrmb, VCMPPSZrmbi, VCVTD... + SStream_concat0(O, "{1to16}"); + return; + break; + case 6: + // VALIGNDZ128rmbi, VALIGNQZ256rmbi, VCMPPDZ256rmbi_alt, VCMPPSZ128rmbi_a... + SStream_concat0(O, "{1to4}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_4); + break; + case 7: + // VALIGNDZ256rmbi, VALIGNQZrmbi, VCMPPDZrmbi_alt, VCMPPSZ256rmbi_alt, VF... + SStream_concat0(O, "{1to8}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_8); + break; + case 8: + // VALIGNDZrmbi, VCMPPSZrmbi_alt, VFIXUPIMMPSZrmbi, VFPCLASSPSZrmbk, VGET... + SStream_concat0(O, "{1to16}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_16); + break; + case 9: + // VALIGNQZ128rmbi, VCMPPDZ128rmbi_alt, VFIXUPIMMPDZ128rmbi, VFPCLASSPDZ1... + SStream_concat0(O, "{1to2}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_2); + break; + case 10: + // VCMPPDZrrib, VCMPPSZrrib, VCMPSDZrrb_Int, VCMPSSZrrb_Int, VCVTPH2PSZrr... + SStream_concat0(O, ", {sae}"); + op_addAvxSae(MI); + return; + break; + case 11: + // VCMPPDZrrib_alt, VCMPPSZrrib_alt, VCMPSDZrrb_alt, VCMPSSZrrb_alt, VCVT... + SStream_concat0(O, ", {sae}, "); + op_addAvxSae(MI); + break; + } + + + // Fragment 6 encoded into 5 bits for 31 unique commands. + // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 47) & 31)); + switch ((uint32_t)((Bits >> 47) & 31)) { + default: // unreachable + case 0: + // INSERTQI, VCVTPS2PHZ128rrk, VCVTPS2PHZ256rrk, VCVTPS2PHZrrbk, VCVTPS2P... + printU8Imm(MI, 4, O); + return; + break; + case 1: + // V4FMADDPSrmk, V4FMADDPSrmkz, V4FMADDSSrmk, V4FMADDSSrmkz, V4FNMADDPSrm... + printf128mem(MI, 4, O); + break; + case 2: + // VADDPDZ128rmbk, VADDPDZ256rmbk, VADDPDZrmbk, VADDSDZrm_Intk, VANDNPDZ1... + printf64mem(MI, 4, O); + break; + case 3: + // VADDPDZ128rmbkz, VADDPDZ256rmbkz, VADDPDZrmbkz, VADDSDZrm_Intkz, VANDN... + printf64mem(MI, 3, O); + break; + case 4: + // VADDPDZ128rmkz, VADDPSZ128rmkz, VANDNPDZ128rmkz, VANDNPSZ128rmkz, VAND... + printf128mem(MI, 3, O); + break; + case 5: + // VADDPDZ128rrk, VADDPDZ256rrk, VADDPDZrrbk, VADDPDZrrk, VADDPSZ128rrk, ... + printOperand(MI, 4, O); + break; + case 6: + // VADDPDZ128rrkz, VADDPDZ256rrkz, VADDPDZrrbkz, VADDPDZrrkz, VADDPSZ128r... + printOperand(MI, 3, O); + break; + case 7: + // VADDPDZ256rmk, VADDPSZ256rmk, VANDNPDZ256rmk, VANDNPSZ256rmk, VANDPDZ2... + printf256mem(MI, 4, O); + break; + case 8: + // VADDPDZ256rmkz, VADDPSZ256rmkz, VANDNPDZ256rmkz, VANDNPSZ256rmkz, VAND... + printf256mem(MI, 3, O); + break; + case 9: + // VADDPDZrmk, VADDPSZrmk, VANDNPDZrmk, VANDNPSZrmk, VANDPDZrmk, VANDPSZr... + printf512mem(MI, 4, O); + break; + case 10: + // VADDPDZrmkz, VADDPSZrmkz, VANDNPDZrmkz, VANDNPSZrmkz, VANDPDZrmkz, VAN... + printf512mem(MI, 3, O); + break; + case 11: + // VADDPDZrrb, VADDPSZrrb, VADDSDZrrb_Int, VADDSSZrrb_Int, VCVTDQ2PSZrrbk... + printRoundingControl(MI, 3, O); + return; + break; + case 12: + // VADDPSZ128rmbk, VADDPSZ256rmbk, VADDPSZrmbk, VADDSSZrm_Intk, VANDNPSZ1... + printf32mem(MI, 4, O); + break; + case 13: + // VADDPSZ128rmbkz, VADDPSZ256rmbkz, VADDPSZrmbkz, VADDSSZrm_Intkz, VANDN... + printf32mem(MI, 3, O); + break; + case 14: + // VALIGNDZ128rmbi, VALIGNDZ128rmi, VALIGNDZ256rmbi, VALIGNDZ256rmi, VALI... + printU8Imm(MI, 7, O); + return; + break; + case 15: + // VALIGNDZ128rmbik, VALIGNDZ256rmbik, VALIGNDZrmbik, VPACKSSDWZ128rmbk, ... + printi32mem(MI, 4, O); + break; + case 16: + // VALIGNDZ128rmbikz, VALIGNDZ256rmbikz, VALIGNDZrmbikz, VPACKSSDWZ128rmb... + printi32mem(MI, 3, O); + break; + case 17: + // VALIGNDZ128rmik, VALIGNQZ128rmik, VDBPSADBWZ128rmik, VGF2P8AFFINEINVQB... + printi128mem(MI, 4, O); + break; + case 18: + // VALIGNDZ128rmikz, VALIGNQZ128rmikz, VDBPSADBWZ128rmikz, VGF2P8AFFINEIN... + printi128mem(MI, 3, O); + break; + case 19: + // VALIGNDZ128rri, VALIGNDZ256rri, VALIGNDZrri, VALIGNQZ128rri, VALIGNQZ2... + printU8Imm(MI, 3, O); + return; + break; + case 20: + // VALIGNDZ256rmik, VALIGNQZ256rmik, VDBPSADBWZ256rmik, VGF2P8AFFINEINVQB... + printi256mem(MI, 4, O); + break; + case 21: + // VALIGNDZ256rmikz, VALIGNQZ256rmikz, VDBPSADBWZ256rmikz, VGF2P8AFFINEIN... + printi256mem(MI, 3, O); + break; + case 22: + // VALIGNDZrmik, VALIGNQZrmik, VDBPSADBWZrmik, VGF2P8AFFINEINVQBZrmik, VG... + printi512mem(MI, 4, O); + break; + case 23: + // VALIGNDZrmikz, VALIGNQZrmikz, VDBPSADBWZrmikz, VGF2P8AFFINEINVQBZrmikz... + printi512mem(MI, 3, O); + break; + case 24: + // VALIGNQZ128rmbik, VALIGNQZ256rmbik, VALIGNQZrmbik, VPADDQZ128rmbk, VPA... + printi64mem(MI, 4, O); + break; + case 25: + // VALIGNQZ128rmbikz, VALIGNQZ256rmbikz, VALIGNQZrmbikz, VPADDQZ128rmbkz,... + printi64mem(MI, 3, O); + break; + case 26: + // VBLENDVPDYrm, VBLENDVPDrm, VBLENDVPSYrm, VBLENDVPSrm, VFMADDPD4Ymr, VF... + printOperand(MI, 7, O); + break; + case 27: + // VCVTDQ2PSZrrbk, VCVTPD2DQZrrbk, VCVTPD2PSZrrbk, VCVTPD2QQZrrbk, VCVTPD... + printRoundingControl(MI, 4, O); + return; + break; + case 28: + // VFIXUPIMMPDZ128rmbi, VFIXUPIMMPDZ128rmi, VFIXUPIMMPDZ256rmbi, VFIXUPIM... + printU8Imm(MI, 8, O); + return; + break; + case 29: + // VGF2P8AFFINEINVQBZ128rmbik, VGF2P8AFFINEINVQBZ256rmbik, VGF2P8AFFINEIN... + printi8mem(MI, 4, O); + break; + case 30: + // VGF2P8AFFINEINVQBZ128rmbikz, VGF2P8AFFINEINVQBZ256rmbikz, VGF2P8AFFINE... + printi8mem(MI, 3, O); + break; + } + + + // Fragment 7 encoded into 4 bits for 12 unique commands. + // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 52) & 15)); + switch ((uint32_t)((Bits >> 52) & 15)) { + default: // unreachable + case 0: + // V4FMADDPSrmk, V4FMADDPSrmkz, V4FMADDSSrmk, V4FMADDSSrmkz, V4FNMADDPSrm... + return; + break; + case 1: + // VADDPDZ128rmbk, VADDPDZ128rmbkz, VANDNPDZ128rmbk, VANDNPDZ128rmbkz, VA... + SStream_concat0(O, "{1to2}"); + return; + break; + case 2: + // VADDPDZ256rmbk, VADDPDZ256rmbkz, VADDPSZ128rmbk, VADDPSZ128rmbkz, VAND... + SStream_concat0(O, "{1to4}"); + return; + break; + case 3: + // VADDPDZrmbk, VADDPDZrmbkz, VADDPSZ256rmbk, VADDPSZ256rmbkz, VANDNPDZrm... + SStream_concat0(O, "{1to8}"); + return; + break; + case 4: + // VADDPDZrrbk, VADDPDZrrbkz, VADDPSZrrbk, VADDPSZrrbkz, VADDSDZrrb_Intk,... + SStream_concat0(O, ", "); + break; + case 5: + // VADDPSZrmbk, VADDPSZrmbkz, VANDNPSZrmbk, VANDNPSZrmbkz, VANDPSZrmbk, V... + SStream_concat0(O, "{1to16}"); + return; + break; + case 6: + // VALIGNDZ128rmbik, VALIGNDZ128rmbikz, VALIGNQZ256rmbik, VALIGNQZ256rmbi... + SStream_concat0(O, "{1to4}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_4); + break; + case 7: + // VALIGNDZ256rmbik, VALIGNDZ256rmbikz, VALIGNQZrmbik, VALIGNQZrmbikz, VC... + SStream_concat0(O, "{1to8}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_8); + break; + case 8: + // VALIGNDZrmbik, VALIGNDZrmbikz, VCMPPSZrmbi_altk, VFIXUPIMMPSZrmbik, VF... + SStream_concat0(O, "{1to16}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_16); + break; + case 9: + // VALIGNQZ128rmbik, VALIGNQZ128rmbikz, VCMPPDZ128rmbi_altk, VFIXUPIMMPDZ... + SStream_concat0(O, "{1to2}, "); + op_addAvxBroadcast(MI, X86_AVX_BCAST_2); + break; + case 10: + // VCMPPDZrrib_altk, VCMPPSZrrib_altk, VCMPSDZrrb_altk, VCMPSSZrrb_altk, ... + SStream_concat0(O, ", {sae}, "); + op_addAvxSae(MI); + break; + case 11: + // VCVTSS2SDZrrb_Intk, VCVTSS2SDZrrb_Intkz, VGETEXPSDZrbk, VGETEXPSDZrbkz... + SStream_concat0(O, ", {sae}"); + op_addAvxSae(MI); + return; + break; + } + + + // Fragment 8 encoded into 3 bits for 6 unique commands. + // printf("Fragment 8: %"PRIu64"\n", ((Bits >> 56) & 7)); + switch ((uint32_t)((Bits >> 56) & 7)) { + default: // unreachable + case 0: + // VADDPDZrrbk, VADDPSZrrbk, VADDSDZrrb_Intk, VADDSSZrrb_Intk, VCVTSD2SSZ... + printRoundingControl(MI, 5, O); + return; + break; + case 1: + // VADDPDZrrbkz, VADDPSZrrbkz, VADDSDZrrb_Intkz, VADDSSZrrb_Intkz, VCVTSD... + printRoundingControl(MI, 4, O); + return; + break; + case 2: + // VALIGNDZ128rmbik, VALIGNDZ128rmik, VALIGNDZ256rmbik, VALIGNDZ256rmik, ... + printU8Imm(MI, 9, O); + return; + break; + case 3: + // VALIGNDZ128rmbikz, VALIGNDZ128rmikz, VALIGNDZ256rmbikz, VALIGNDZ256rmi... + printU8Imm(MI, 8, O); + return; + break; + case 4: + // VALIGNDZ128rrik, VALIGNDZ256rrik, VALIGNDZrrik, VALIGNQZ128rrik, VALIG... + printU8Imm(MI, 5, O); + return; + break; + case 5: + // VALIGNDZ128rrikz, VALIGNDZ256rrikz, VALIGNDZrrikz, VALIGNQZ128rrikz, V... + printU8Imm(MI, 4, O); + return; + break; + } + +} + + + diff --git a/thirdparty/capstone/arch/X86/X86GenAsmWriter1_reduce.inc b/thirdparty/capstone/arch/X86/X86GenAsmWriter1_reduce.inc new file mode 100644 index 0000000..9f027ed --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenAsmWriter1_reduce.inc @@ -0,0 +1,2533 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) +{ +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'x', 's', 'a', 'v', 'e', 'c', '6', '4', 9, 0, + /* 10 */ 'x', 's', 'a', 'v', 'e', '6', '4', 9, 0, + /* 19 */ 'x', 'r', 's', 't', 'o', 'r', '6', '4', 9, 0, + /* 29 */ 'x', 's', 'a', 'v', 'e', 's', '6', '4', 9, 0, + /* 39 */ 'x', 'r', 's', 't', 'o', 'r', 's', '6', '4', 9, 0, + /* 50 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', '6', '4', 9, 0, + /* 62 */ 'l', 'e', 'a', 9, 0, + /* 67 */ 'j', 'a', 9, 0, + /* 71 */ 's', 'e', 't', 'a', 9, 0, + /* 77 */ 'c', 'm', 'o', 'v', 'a', 9, 0, + /* 84 */ 'm', 'o', 'v', 'd', 'i', 'r', '6', '4', 'b', 9, 0, + /* 95 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0, + /* 107 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '8', 'b', 9, 0, + /* 118 */ 's', 'b', 'b', 9, 0, + /* 123 */ 'l', 'l', 'w', 'p', 'c', 'b', 9, 0, + /* 131 */ 's', 'l', 'w', 'p', 'c', 'b', 9, 0, + /* 139 */ 'j', 'b', 9, 0, + /* 143 */ 'i', 'n', 's', 'b', 9, 0, + /* 149 */ 's', 't', 'o', 's', 'b', 9, 0, + /* 156 */ 'c', 'm', 'p', 's', 'b', 9, 0, + /* 163 */ 'm', 'o', 'v', 's', 'b', 9, 0, + /* 170 */ 's', 'e', 't', 'b', 9, 0, + /* 176 */ 's', 'u', 'b', 9, 0, + /* 181 */ 'c', 'm', 'o', 'v', 'b', 9, 0, + /* 188 */ 'c', 'l', 'w', 'b', 9, 0, + /* 194 */ 'a', 'd', 'c', 9, 0, + /* 199 */ 'd', 'e', 'c', 9, 0, + /* 204 */ 'x', 's', 'a', 'v', 'e', 'c', 9, 0, + /* 212 */ 'b', 'l', 'c', 'i', 'c', 9, 0, + /* 219 */ 'b', 'l', 's', 'i', 'c', 9, 0, + /* 226 */ 't', '1', 'm', 's', 'k', 'c', 9, 0, + /* 234 */ 'i', 'n', 'c', 9, 0, + /* 239 */ 'b', 't', 'c', 9, 0, + /* 244 */ 'a', 'a', 'd', 9, 0, + /* 249 */ 'v', 'm', 'r', 'e', 'a', 'd', 9, 0, + /* 257 */ 'x', 'a', 'd', 'd', 9, 0, + /* 263 */ 'r', 'd', 's', 'e', 'e', 'd', 9, 0, + /* 271 */ 'i', 'n', 'v', 'p', 'c', 'i', 'd', 9, 0, + /* 280 */ 'r', 'd', 'p', 'i', 'd', 9, 0, + /* 287 */ 'i', 'n', 'v', 'v', 'p', 'i', 'd', 9, 0, + /* 296 */ 's', 'h', 'l', 'd', 9, 0, + /* 302 */ 'v', 'm', 'p', 't', 'r', 'l', 'd', 9, 0, + /* 311 */ 'r', 'd', 'r', 'a', 'n', 'd', 9, 0, + /* 319 */ 'b', 'o', 'u', 'n', 'd', 9, 0, + /* 326 */ 'i', 'n', 'c', 's', 's', 'p', 'd', 9, 0, + /* 335 */ 'r', 'd', 's', 's', 'p', 'd', 9, 0, + /* 343 */ 's', 'h', 'r', 'd', 9, 0, + /* 349 */ 'i', 'n', 's', 'd', 9, 0, + /* 355 */ 's', 't', 'o', 's', 'd', 9, 0, + /* 362 */ 'c', 'm', 'p', 's', 'd', 9, 0, + /* 369 */ 'w', 'r', 's', 's', 'd', 9, 0, + /* 376 */ 'w', 'r', 'u', 's', 's', 'd', 9, 0, + /* 384 */ 'm', 'o', 'v', 's', 'd', 9, 0, + /* 391 */ 'm', 'o', 'v', 's', 'x', 'd', 9, 0, + /* 399 */ 'j', 'a', 'e', 9, 0, + /* 404 */ 's', 'e', 't', 'a', 'e', 9, 0, + /* 411 */ 'c', 'm', 'o', 'v', 'a', 'e', 9, 0, + /* 419 */ 'j', 'b', 'e', 9, 0, + /* 424 */ 's', 'e', 't', 'b', 'e', 9, 0, + /* 431 */ 'c', 'm', 'o', 'v', 'b', 'e', 9, 0, + /* 439 */ 'j', 'g', 'e', 9, 0, + /* 444 */ 's', 'e', 't', 'g', 'e', 9, 0, + /* 451 */ 'c', 'm', 'o', 'v', 'g', 'e', 9, 0, + /* 459 */ 'j', 'e', 9, 0, + /* 463 */ 'j', 'l', 'e', 9, 0, + /* 468 */ 's', 'e', 't', 'l', 'e', 9, 0, + /* 475 */ 'c', 'm', 'o', 'v', 'l', 'e', 9, 0, + /* 483 */ 'j', 'n', 'e', 9, 0, + /* 488 */ 'l', 'o', 'o', 'p', 'n', 'e', 9, 0, + /* 496 */ 's', 'e', 't', 'n', 'e', 9, 0, + /* 503 */ 'c', 'm', 'o', 'v', 'n', 'e', 9, 0, + /* 511 */ 'l', 'o', 'o', 'p', 'e', 9, 0, + /* 518 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 9, 0, + /* 528 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 9, 0, + /* 538 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 9, 0, + /* 548 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 9, 0, + /* 558 */ 't', 'p', 'a', 'u', 's', 'e', 9, 0, + /* 566 */ 's', 'e', 't', 'e', 9, 0, + /* 572 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 9, 0, + /* 581 */ 'p', 't', 'w', 'r', 'i', 't', 'e', 9, 0, + /* 590 */ 'c', 'l', 'd', 'e', 'm', 'o', 't', 'e', 9, 0, + /* 600 */ 'x', 's', 'a', 'v', 'e', 9, 0, + /* 607 */ 'c', 'm', 'o', 'v', 'e', 9, 0, + /* 614 */ 'b', 's', 'f', 9, 0, + /* 619 */ 'r', 'e', 't', 'f', 9, 0, + /* 625 */ 'n', 'e', 'g', 9, 0, + /* 630 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 9, 0, + /* 639 */ 'j', 'g', 9, 0, + /* 643 */ 'i', 'n', 'v', 'l', 'p', 'g', 9, 0, + /* 651 */ 's', 'e', 't', 'g', 9, 0, + /* 657 */ 'c', 'm', 'o', 'v', 'g', 9, 0, + /* 664 */ 'p', 'u', 's', 'h', 9, 0, + /* 670 */ 'b', 'l', 'c', 'i', 9, 0, + /* 676 */ 'b', 'z', 'h', 'i', 9, 0, + /* 682 */ 'm', 'o', 'v', 'd', 'i', 'r', 'i', 9, 0, + /* 691 */ 'b', 'l', 's', 'i', 9, 0, + /* 697 */ 'b', 'l', 'c', 'm', 's', 'k', 9, 0, + /* 705 */ 'b', 'l', 's', 'm', 's', 'k', 9, 0, + /* 713 */ 't', 'z', 'm', 's', 'k', 9, 0, + /* 720 */ 's', 'a', 'l', 9, 0, + /* 725 */ 'l', 'w', 'p', 'v', 'a', 'l', 9, 0, + /* 733 */ 'r', 'c', 'l', 9, 0, + /* 738 */ 's', 'h', 'l', 9, 0, + /* 743 */ 'j', 'l', 9, 0, + /* 747 */ 'l', 'c', 'a', 'l', 'l', 9, 0, + /* 754 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 9, 0, + /* 763 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 9, 0, + /* 772 */ 'r', 'o', 'l', 9, 0, + /* 777 */ 'a', 'r', 'p', 'l', 9, 0, + /* 783 */ 'l', 's', 'l', 9, 0, + /* 788 */ 's', 'e', 't', 'l', 9, 0, + /* 794 */ 'i', 'm', 'u', 'l', 9, 0, + /* 800 */ 'c', 'm', 'o', 'v', 'l', 9, 0, + /* 807 */ 'a', 'a', 'm', 9, 0, + /* 812 */ 'a', 'n', 'd', 'n', 9, 0, + /* 818 */ 'v', 'm', 'x', 'o', 'n', 9, 0, + /* 825 */ 'j', 'o', 9, 0, + /* 829 */ 'j', 'n', 'o', 9, 0, + /* 834 */ 's', 'e', 't', 'n', 'o', 9, 0, + /* 841 */ 'c', 'm', 'o', 'v', 'n', 'o', 9, 0, + /* 849 */ 's', 'e', 't', 'o', 9, 0, + /* 855 */ 'c', 'm', 'o', 'v', 'o', 9, 0, + /* 862 */ 'b', 's', 'w', 'a', 'p', 9, 0, + /* 869 */ 'p', 'd', 'e', 'p', 9, 0, + /* 875 */ 'j', 'p', 9, 0, + /* 879 */ 'c', 'm', 'p', 9, 0, + /* 884 */ 'l', 'j', 'm', 'p', 9, 0, + /* 890 */ 'j', 'n', 'p', 9, 0, + /* 895 */ 's', 'e', 't', 'n', 'p', 9, 0, + /* 902 */ 'c', 'm', 'o', 'v', 'n', 'p', 9, 0, + /* 910 */ 'n', 'o', 'p', 9, 0, + /* 915 */ 'l', 'o', 'o', 'p', 9, 0, + /* 921 */ 'p', 'o', 'p', 9, 0, + /* 926 */ 'r', 's', 't', 'o', 'r', 's', 's', 'p', 9, 0, + /* 936 */ 's', 'e', 't', 'p', 9, 0, + /* 942 */ 'c', 'm', 'o', 'v', 'p', 9, 0, + /* 949 */ 'r', 'e', 't', 'f', 'q', 9, 0, + /* 956 */ 'i', 'n', 'c', 's', 's', 'p', 'q', 9, 0, + /* 965 */ 'r', 'd', 's', 's', 'p', 'q', 9, 0, + /* 973 */ 's', 't', 'o', 's', 'q', 9, 0, + /* 980 */ 'c', 'm', 'p', 's', 'q', 9, 0, + /* 987 */ 'w', 'r', 's', 's', 'q', 9, 0, + /* 994 */ 'w', 'r', 'u', 's', 's', 'q', 9, 0, + /* 1002 */ 'm', 'o', 'v', 's', 'q', 9, 0, + /* 1009 */ 'v', 'm', 'c', 'l', 'e', 'a', 'r', 9, 0, + /* 1018 */ 'l', 'a', 'r', 9, 0, + /* 1023 */ 's', 'a', 'r', 9, 0, + /* 1028 */ 'r', 'c', 'r', 9, 0, + /* 1033 */ 'e', 'n', 't', 'e', 'r', 9, 0, + /* 1040 */ 's', 'h', 'r', 9, 0, + /* 1045 */ 'r', 'o', 'r', 9, 0, + /* 1050 */ 'u', 'm', 'o', 'n', 'i', 't', 'o', 'r', 9, 0, + /* 1060 */ 'x', 'r', 's', 't', 'o', 'r', 9, 0, + /* 1068 */ 'x', 'o', 'r', 9, 0, + /* 1073 */ 'v', 'e', 'r', 'r', 9, 0, + /* 1079 */ 'b', 's', 'r', 9, 0, + /* 1084 */ 'b', 'l', 's', 'r', 9, 0, + /* 1090 */ 'b', 't', 'r', 9, 0, + /* 1095 */ 'l', 't', 'r', 9, 0, + /* 1100 */ 's', 't', 'r', 9, 0, + /* 1105 */ 'b', 'e', 'x', 't', 'r', 9, 0, + /* 1112 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 0, + /* 1120 */ 'b', 'l', 'c', 's', 9, 0, + /* 1126 */ 'l', 'd', 's', 9, 0, + /* 1131 */ 'l', 'e', 's', 9, 0, + /* 1136 */ 'x', 's', 'a', 'v', 'e', 's', 9, 0, + /* 1144 */ 'l', 'f', 's', 9, 0, + /* 1149 */ 'l', 'g', 's', 9, 0, + /* 1154 */ 'j', 's', 9, 0, + /* 1158 */ 'l', 'w', 'p', 'i', 'n', 's', 9, 0, + /* 1166 */ 'j', 'n', 's', 9, 0, + /* 1171 */ 's', 'e', 't', 'n', 's', 9, 0, + /* 1178 */ 'c', 'm', 'o', 'v', 'n', 's', 9, 0, + /* 1186 */ 'x', 'r', 's', 't', 'o', 'r', 's', 9, 0, + /* 1195 */ 'l', 's', 's', 9, 0, + /* 1200 */ 'b', 't', 's', 9, 0, + /* 1205 */ 's', 'e', 't', 's', 9, 0, + /* 1211 */ 'c', 'm', 'o', 'v', 's', 9, 0, + /* 1218 */ 'b', 't', 9, 0, + /* 1222 */ 'l', 'g', 'd', 't', 9, 0, + /* 1228 */ 's', 'g', 'd', 't', 9, 0, + /* 1234 */ 'l', 'i', 'd', 't', 9, 0, + /* 1240 */ 's', 'i', 'd', 't', 9, 0, + /* 1246 */ 'l', 'l', 'd', 't', 9, 0, + /* 1252 */ 's', 'l', 'd', 't', 9, 0, + /* 1258 */ 'r', 'e', 't', 9, 0, + /* 1263 */ 'u', 'm', 'w', 'a', 'i', 't', 9, 0, + /* 1271 */ 'l', 'z', 'c', 'n', 't', 9, 0, + /* 1278 */ 't', 'z', 'c', 'n', 't', 9, 0, + /* 1285 */ 'i', 'n', 't', 9, 0, + /* 1290 */ 'n', 'o', 't', 9, 0, + /* 1295 */ 'i', 'n', 'v', 'e', 'p', 't', 9, 0, + /* 1303 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 9, 0, + /* 1313 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 'o', 'p', 't', 9, 0, + /* 1325 */ 't', 'e', 's', 't', 9, 0, + /* 1331 */ 'v', 'm', 'p', 't', 'r', 's', 't', 9, 0, + /* 1340 */ 'o', 'u', 't', 9, 0, + /* 1345 */ 'p', 'e', 'x', 't', 9, 0, + /* 1351 */ 'i', 'd', 'i', 'v', 9, 0, + /* 1357 */ 'm', 'o', 'v', 9, 0, + /* 1362 */ 'v', 'e', 'r', 'w', 9, 0, + /* 1368 */ 'l', 'm', 's', 'w', 9, 0, + /* 1374 */ 's', 'm', 's', 'w', 9, 0, + /* 1380 */ 'i', 'n', 's', 'w', 9, 0, + /* 1386 */ 's', 't', 'o', 's', 'w', 9, 0, + /* 1393 */ 'c', 'm', 'p', 's', 'w', 9, 0, + /* 1400 */ 'm', 'o', 'v', 's', 'w', 9, 0, + /* 1407 */ 'a', 'd', 'c', 'x', 9, 0, + /* 1413 */ 's', 'h', 'l', 'x', 9, 0, + /* 1419 */ 'm', 'u', 'l', 'x', 9, 0, + /* 1425 */ 'a', 'd', 'o', 'x', 9, 0, + /* 1431 */ 's', 'a', 'r', 'x', 9, 0, + /* 1437 */ 's', 'h', 'r', 'x', 9, 0, + /* 1443 */ 'r', 'o', 'r', 'x', 9, 0, + /* 1449 */ 'm', 'o', 'v', 's', 'x', 9, 0, + /* 1456 */ 'm', 'o', 'v', 'z', 'x', 9, 0, + /* 1463 */ 'c', 'l', 'r', 's', 's', 'b', 's', 'y', 9, 0, + /* 1473 */ 'j', 'e', 'c', 'x', 'z', 9, 0, + /* 1480 */ 'j', 'c', 'x', 'z', 9, 0, + /* 1486 */ 'j', 'r', 'c', 'x', 'z', 9, 0, + /* 1493 */ 's', 'b', 'b', 9, 'a', 'l', ',', 32, 0, + /* 1502 */ 's', 'c', 'a', 's', 'b', 9, 'a', 'l', ',', 32, 0, + /* 1513 */ 'l', 'o', 'd', 's', 'b', 9, 'a', 'l', ',', 32, 0, + /* 1524 */ 's', 'u', 'b', 9, 'a', 'l', ',', 32, 0, + /* 1533 */ 'a', 'd', 'c', 9, 'a', 'l', ',', 32, 0, + /* 1542 */ 'a', 'd', 'd', 9, 'a', 'l', ',', 32, 0, + /* 1551 */ 'a', 'n', 'd', 9, 'a', 'l', ',', 32, 0, + /* 1560 */ 'i', 'n', 9, 'a', 'l', ',', 32, 0, + /* 1568 */ 'c', 'm', 'p', 9, 'a', 'l', ',', 32, 0, + /* 1577 */ 'x', 'o', 'r', 9, 'a', 'l', ',', 32, 0, + /* 1586 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 'a', 'l', ',', 32, 0, + /* 1598 */ 't', 'e', 's', 't', 9, 'a', 'l', ',', 32, 0, + /* 1608 */ 'm', 'o', 'v', 9, 'a', 'l', ',', 32, 0, + /* 1617 */ 's', 'b', 'b', 9, 'a', 'x', ',', 32, 0, + /* 1626 */ 's', 'u', 'b', 9, 'a', 'x', ',', 32, 0, + /* 1635 */ 'a', 'd', 'c', 9, 'a', 'x', ',', 32, 0, + /* 1644 */ 'a', 'd', 'd', 9, 'a', 'x', ',', 32, 0, + /* 1653 */ 'a', 'n', 'd', 9, 'a', 'x', ',', 32, 0, + /* 1662 */ 'i', 'n', 9, 'a', 'x', ',', 32, 0, + /* 1670 */ 'c', 'm', 'p', 9, 'a', 'x', ',', 32, 0, + /* 1679 */ 'x', 'o', 'r', 9, 'a', 'x', ',', 32, 0, + /* 1688 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 'a', 'x', ',', 32, 0, + /* 1700 */ 't', 'e', 's', 't', 9, 'a', 'x', ',', 32, 0, + /* 1710 */ 'm', 'o', 'v', 9, 'a', 'x', ',', 32, 0, + /* 1719 */ 's', 'c', 'a', 's', 'w', 9, 'a', 'x', ',', 32, 0, + /* 1730 */ 'l', 'o', 'd', 's', 'w', 9, 'a', 'x', ',', 32, 0, + /* 1741 */ 's', 'b', 'b', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1751 */ 's', 'u', 'b', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1761 */ 'a', 'd', 'c', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1771 */ 'a', 'd', 'd', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1781 */ 'a', 'n', 'd', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1791 */ 's', 'c', 'a', 's', 'd', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1803 */ 'l', 'o', 'd', 's', 'd', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1815 */ 'i', 'n', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1824 */ 'c', 'm', 'p', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1834 */ 'x', 'o', 'r', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1844 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1857 */ 't', 'e', 's', 't', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1868 */ 'm', 'o', 'v', 9, 'e', 'a', 'x', ',', 32, 0, + /* 1878 */ 's', 'b', 'b', 9, 'r', 'a', 'x', ',', 32, 0, + /* 1888 */ 's', 'u', 'b', 9, 'r', 'a', 'x', ',', 32, 0, + /* 1898 */ 'a', 'd', 'c', 9, 'r', 'a', 'x', ',', 32, 0, + /* 1908 */ 'a', 'd', 'd', 9, 'r', 'a', 'x', ',', 32, 0, + /* 1918 */ 'a', 'n', 'd', 9, 'r', 'a', 'x', ',', 32, 0, + /* 1928 */ 'c', 'm', 'p', 9, 'r', 'a', 'x', ',', 32, 0, + /* 1938 */ 's', 'c', 'a', 's', 'q', 9, 'r', 'a', 'x', ',', 32, 0, + /* 1950 */ 'l', 'o', 'd', 's', 'q', 9, 'r', 'a', 'x', ',', 32, 0, + /* 1962 */ 'x', 'o', 'r', 9, 'r', 'a', 'x', ',', 32, 0, + /* 1972 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 'r', 'a', 'x', ',', 32, 0, + /* 1985 */ 't', 'e', 's', 't', 9, 'r', 'a', 'x', ',', 32, 0, + /* 1996 */ 'm', 'o', 'v', 9, 'r', 'a', 'x', ',', 32, 0, + /* 2006 */ 'o', 'u', 't', 's', 'b', 9, 'd', 'x', ',', 32, 0, + /* 2017 */ 'o', 'u', 't', 's', 'd', 9, 'd', 'x', ',', 32, 0, + /* 2028 */ 'o', 'u', 't', 's', 'w', 9, 'd', 'x', ',', 32, 0, + /* 2039 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, + /* 2070 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 2094 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 2119 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, + /* 2142 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, + /* 2165 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, + /* 2187 */ 'u', 'd', '0', 0, + /* 2191 */ 'x', 's', 'h', 'a', '1', 0, + /* 2197 */ 'u', 'd', '1', 0, + /* 2201 */ 'i', 'n', 't', '1', 0, + /* 2206 */ 'e', 'n', 'd', 'b', 'r', '3', '2', 0, + /* 2214 */ 'u', 'd', '2', 0, + /* 2218 */ 'i', 'n', 't', '3', 0, + /* 2223 */ 'e', 'n', 'd', 'b', 'r', '6', '4', 0, + /* 2231 */ 'r', 'e', 'x', '6', '4', 0, + /* 2237 */ 'd', 'a', 't', 'a', '1', '6', 0, + /* 2244 */ 'x', 's', 'h', 'a', '2', '5', '6', 0, + /* 2252 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 2265 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 2272 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 2282 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, + /* 2292 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 2307 */ 'a', 'a', 'a', 0, + /* 2311 */ 'd', 'a', 'a', 0, + /* 2315 */ 'x', 'c', 'r', 'y', 'p', 't', 'e', 'c', 'b', 0, + /* 2325 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'f', 'b', 0, + /* 2335 */ 'x', 'c', 'r', 'y', 'p', 't', 'o', 'f', 'b', 0, + /* 2345 */ 'x', 'l', 'a', 't', 'b', 0, + /* 2351 */ 'c', 'l', 'a', 'c', 0, + /* 2356 */ 's', 't', 'a', 'c', 0, + /* 2361 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'b', 'c', 0, + /* 2371 */ 'g', 'e', 't', 's', 'e', 'c', 0, + /* 2378 */ 's', 'a', 'l', 'c', 0, + /* 2383 */ 'c', 'l', 'c', 0, + /* 2387 */ 'c', 'm', 'c', 0, + /* 2391 */ 'r', 'd', 'p', 'm', 'c', 0, + /* 2397 */ 'v', 'm', 'f', 'u', 'n', 'c', 0, + /* 2404 */ 'r', 'd', 't', 's', 'c', 0, + /* 2410 */ 's', 't', 'c', 0, + /* 2414 */ 'p', 'u', 's', 'h', 'f', 'd', 0, + /* 2421 */ 'p', 'o', 'p', 'f', 'd', 0, + /* 2427 */ 'c', 'p', 'u', 'i', 'd', 0, + /* 2433 */ 'c', 'l', 'd', 0, + /* 2437 */ 'i', 'r', 'e', 't', 'd', 0, + /* 2443 */ 's', 't', 'd', 0, + /* 2447 */ 'w', 'b', 'i', 'n', 'v', 'd', 0, + /* 2454 */ 'w', 'b', 'n', 'o', 'i', 'n', 'v', 'd', 0, + /* 2463 */ 'c', 'w', 'd', 0, + /* 2467 */ 'c', 'w', 'd', 'e', 0, + /* 2472 */ 'v', 'm', 'r', 'e', 's', 'u', 'm', 'e', 0, + /* 2481 */ 'r', 'e', 'p', 'n', 'e', 0, + /* 2487 */ 'c', 'd', 'q', 'e', 0, + /* 2492 */ 'x', 's', 't', 'o', 'r', 'e', 0, + /* 2499 */ 'l', 'e', 'a', 'v', 'e', 0, + /* 2505 */ 'v', 'm', 'x', 'o', 'f', 'f', 0, + /* 2512 */ 'l', 'a', 'h', 'f', 0, + /* 2517 */ 's', 'a', 'h', 'f', 0, + /* 2522 */ 'p', 'u', 's', 'h', 'f', 0, + /* 2528 */ 'p', 'o', 'p', 'f', 0, + /* 2533 */ 'r', 'e', 't', 'f', 0, + /* 2538 */ 'p', 'c', 'o', 'n', 'f', 'i', 'g', 0, + /* 2546 */ 'v', 'm', 'l', 'a', 'u', 'n', 'c', 'h', 0, + /* 2555 */ 'c', 'l', 'g', 'i', 0, + /* 2560 */ 's', 't', 'g', 'i', 0, + /* 2565 */ 'c', 'l', 'i', 0, + /* 2569 */ 's', 't', 'i', 0, + /* 2573 */ 'l', 'o', 'c', 'k', 0, + /* 2578 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'a', 'l', 0, + /* 2589 */ 'p', 'u', 's', 'h', 'a', 'l', 0, + /* 2596 */ 'p', 'o', 'p', 'a', 'l', 0, + /* 2602 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, + /* 2616 */ 'v', 'm', 'm', 'c', 'a', 'l', 'l', 0, + /* 2624 */ 'v', 'm', 'c', 'a', 'l', 'l', 0, + /* 2631 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 0, + /* 2639 */ 'm', 'o', 'n', 't', 'm', 'u', 'l', 0, + /* 2647 */ 'f', 's', 'e', 't', 'p', 'm', 0, + /* 2654 */ 'r', 's', 'm', 0, + /* 2658 */ 'c', 'q', 'o', 0, + /* 2662 */ 'c', 'l', 'z', 'e', 'r', 'o', 0, + /* 2669 */ 'i', 'n', 't', 'o', 0, + /* 2674 */ 'r', 'd', 't', 's', 'c', 'p', 0, + /* 2681 */ 'r', 'e', 'p', 0, + /* 2685 */ 'n', 'o', 'p', 0, + /* 2689 */ 's', 'a', 'v', 'e', 'p', 'r', 'e', 'v', 's', 's', 'p', 0, + /* 2701 */ 'c', 'd', 'q', 0, + /* 2705 */ 'p', 'u', 's', 'h', 'f', 'q', 0, + /* 2712 */ 'p', 'o', 'p', 'f', 'q', 0, + /* 2718 */ 'r', 'e', 't', 'f', 'q', 0, + /* 2724 */ 'i', 'r', 'e', 't', 'q', 0, + /* 2730 */ 's', 'y', 's', 'r', 'e', 't', 'q', 0, + /* 2738 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'q', 0, + /* 2747 */ 's', 'y', 's', 'e', 'n', 't', 'e', 'r', 0, + /* 2756 */ 'r', 'd', 'm', 's', 'r', 0, + /* 2762 */ 'w', 'r', 'm', 's', 'r', 0, + /* 2768 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 't', 'r', 0, + /* 2778 */ 'a', 'a', 's', 0, + /* 2782 */ 'd', 'a', 's', 0, + /* 2786 */ 'p', 'u', 's', 'h', 9, 'c', 's', 0, + /* 2794 */ 'p', 'u', 's', 'h', 9, 'd', 's', 0, + /* 2802 */ 'p', 'o', 'p', 9, 'd', 's', 0, + /* 2809 */ 'p', 'u', 's', 'h', 9, 'e', 's', 0, + /* 2817 */ 'p', 'o', 'p', 9, 'e', 's', 0, + /* 2824 */ 'p', 'u', 's', 'h', 9, 'f', 's', 0, + /* 2832 */ 'p', 'o', 'p', 9, 'f', 's', 0, + /* 2839 */ 'p', 'u', 's', 'h', 9, 'g', 's', 0, + /* 2847 */ 'p', 'o', 'p', 9, 'g', 's', 0, + /* 2854 */ 's', 'w', 'a', 'p', 'g', 's', 0, + /* 2861 */ 'p', 'u', 's', 'h', 9, 's', 's', 0, + /* 2869 */ 'p', 'o', 'p', 9, 's', 's', 0, + /* 2876 */ 'c', 'l', 't', 's', 0, + /* 2881 */ 'i', 'r', 'e', 't', 0, + /* 2886 */ 's', 'y', 's', 'r', 'e', 't', 0, + /* 2893 */ 's', 'y', 's', 'e', 'x', 'i', 't', 0, + /* 2901 */ 'h', 'l', 't', 0, + /* 2905 */ 'r', 'd', 'p', 'k', 'r', 'u', 0, + /* 2912 */ 'w', 'r', 'p', 'k', 'r', 'u', 0, + /* 2919 */ 'x', 'g', 'e', 't', 'b', 'v', 0, + /* 2926 */ 'x', 's', 'e', 't', 'b', 'v', 0, + /* 2933 */ 'p', 'u', 's', 'h', 'a', 'w', 0, + /* 2940 */ 'p', 'o', 'p', 'a', 'w', 0, + /* 2946 */ 'c', 'b', 'w', 0, + /* 2950 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'a', 'x', 0, + /* 2961 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, 'e', 'a', 'x', 0, + /* 2972 */ 'v', 'm', 's', 'a', 'v', 'e', 9, 'e', 'a', 'x', 0, + /* 2983 */ 'v', 'm', 'r', 'u', 'n', 9, 'e', 'a', 'x', 0, + /* 2993 */ 's', 'k', 'i', 'n', 'i', 't', 9, 'e', 'a', 'x', 0, + /* 3004 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'e', 'a', 'x', 0, + /* 3016 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, 'r', 'a', 'x', 0, + /* 3027 */ 'v', 'm', 's', 'a', 'v', 'e', 9, 'r', 'a', 'x', 0, + /* 3038 */ 'v', 'm', 'r', 'u', 'n', 9, 'r', 'a', 'x', 0, + /* 3048 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, 'e', 'a', 'x', ',', 32, 'e', 'c', 'x', 0, + /* 3065 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, 'r', 'a', 'x', ',', 32, 'e', 'c', 'x', 0, + /* 3082 */ 'i', 'n', 9, 'a', 'l', ',', 32, 'd', 'x', 0, + /* 3092 */ 'i', 'n', 9, 'a', 'x', ',', 32, 'd', 'x', 0, + /* 3102 */ 'i', 'n', 9, 'e', 'a', 'x', ',', 32, 'd', 'x', 0, + /* 3113 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 'x', 0, + /* 3122 */ 'm', 'w', 'a', 'i', 't', 'x', 0, + /* 3129 */ 's', 'e', 't', 's', 's', 'b', 's', 'y', 0, + }; +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 2273U, // DBG_VALUE + 2283U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 2266U, // BUNDLE + 2293U, // LIFETIME_START + 2253U, // LIFETIME_END + 0U, // STACKMAP + 2603U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 2120U, // PATCHABLE_FUNCTION_ENTER + 2040U, // PATCHABLE_RET + 2166U, // PATCHABLE_FUNCTION_EXIT + 2143U, // PATCHABLE_TAIL_CALL + 2095U, // PATCHABLE_EVENT_CALL + 2071U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 2308U, // AAA + 4341U, // AAD8i8 + 4904U, // AAM8i8 + 2779U, // AAS + 5732U, // ADC16i16 + 270531U, // ADC16mi + 270531U, // ADC16mi8 + 270531U, // ADC16mr + 4468931U, // ADC16ri + 4468931U, // ADC16ri8 + 8663235U, // ADC16rm + 4468931U, // ADC16rr + 4460739U, // ADC16rr_REV + 5858U, // ADC32i32 + 278723U, // ADC32mi + 278723U, // ADC32mi8 + 278723U, // ADC32mr + 4468931U, // ADC32ri + 4468931U, // ADC32ri8 + 12857539U, // ADC32rm + 4468931U, // ADC32rr + 4460739U, // ADC32rr_REV + 5995U, // ADC64i32 + 282819U, // ADC64mi32 + 282819U, // ADC64mi8 + 282819U, // ADC64mr + 4468931U, // ADC64ri32 + 4468931U, // ADC64ri8 + 17051843U, // ADC64rm + 4468931U, // ADC64rr + 4460739U, // ADC64rr_REV + 5630U, // ADC8i8 + 286915U, // ADC8mi + 286915U, // ADC8mi8 + 286915U, // ADC8mr + 4468931U, // ADC8ri + 4468931U, // ADC8ri8 + 21246147U, // ADC8rm + 4468931U, // ADC8rr + 4460739U, // ADC8rr_REV + 12850560U, // ADCX32rm + 4461952U, // ADCX32rr + 17044864U, // ADCX64rm + 4461952U, // ADCX64rr + 5741U, // ADD16i16 + 270595U, // ADD16mi + 270595U, // ADD16mi8 + 270595U, // ADD16mr + 4468995U, // ADD16ri + 4468995U, // ADD16ri8 + 8663299U, // ADD16rm + 4468995U, // ADD16rr + 4460803U, // ADD16rr_REV + 5868U, // ADD32i32 + 278787U, // ADD32mi + 278787U, // ADD32mi8 + 278787U, // ADD32mr + 4468995U, // ADD32ri + 4468995U, // ADD32ri8 + 12857603U, // ADD32rm + 4468995U, // ADD32rr + 4460803U, // ADD32rr_REV + 6005U, // ADD64i32 + 282883U, // ADD64mi32 + 282883U, // ADD64mi8 + 282883U, // ADD64mr + 4468995U, // ADD64ri32 + 4468995U, // ADD64ri8 + 17051907U, // ADD64rm + 4468995U, // ADD64rr + 4460803U, // ADD64rr_REV + 5639U, // ADD8i8 + 286979U, // ADD8mi + 286979U, // ADD8mi8 + 286979U, // ADD8mr + 4468995U, // ADD8ri + 4468995U, // ADD8ri8 + 21246211U, // ADD8rm + 4468995U, // ADD8rr + 4460803U, // ADD8rr_REV + 12850578U, // ADOX32rm + 4461970U, // ADOX32rr + 17044882U, // ADOX64rm + 4461970U, // ADOX64rr + 5750U, // AND16i16 + 270651U, // AND16mi + 270651U, // AND16mi8 + 270651U, // AND16mr + 4469051U, // AND16ri + 4469051U, // AND16ri8 + 8663355U, // AND16rm + 4469051U, // AND16rr + 4460859U, // AND16rr_REV + 5878U, // AND32i32 + 278843U, // AND32mi + 278843U, // AND32mi8 + 278843U, // AND32mr + 4469051U, // AND32ri + 4469051U, // AND32ri8 + 12857659U, // AND32rm + 4469051U, // AND32rr + 4460859U, // AND32rr_REV + 6015U, // AND64i32 + 282939U, // AND64mi32 + 282939U, // AND64mi8 + 282939U, // AND64mr + 4469051U, // AND64ri32 + 4469051U, // AND64ri8 + 17051963U, // AND64rm + 4469051U, // AND64rr + 4460859U, // AND64rr_REV + 5648U, // AND8i8 + 287035U, // AND8mi + 287035U, // AND8mi8 + 287035U, // AND8mr + 4469051U, // AND8ri + 4469051U, // AND8ri8 + 21246267U, // AND8rm + 4469051U, // AND8rr + 4460859U, // AND8rr_REV + 159650605U, // ANDN32rm + 696521517U, // ANDN32rr + 1233392429U, // ANDN64rm + 696521517U, // ANDN64rr + 271114U, // ARPL16mr + 25432842U, // ARPL16rr + 1774457938U, // BEXTR32rm + 696521810U, // BEXTR32rr + 1778652242U, // BEXTR64rm + 696521810U, // BEXTR64rr + 1774457938U, // BEXTRI32mi + 696521810U, // BEXTRI32ri + 1778652242U, // BEXTRI64mi + 696521810U, // BEXTRI64ri + 29627123U, // BLCFILL32rm + 25432819U, // BLCFILL32rr + 33821427U, // BLCFILL64rm + 25432819U, // BLCFILL64rr + 29627039U, // BLCI32rm + 25432735U, // BLCI32rr + 33821343U, // BLCI64rm + 25432735U, // BLCI64rr + 29626581U, // BLCIC32rm + 25432277U, // BLCIC32rr + 33820885U, // BLCIC64rm + 25432277U, // BLCIC64rr + 29627066U, // BLCMSK32rm + 25432762U, // BLCMSK32rr + 33821370U, // BLCMSK64rm + 25432762U, // BLCMSK64rr + 29627489U, // BLCS32rm + 25433185U, // BLCS32rr + 33821793U, // BLCS64rm + 25433185U, // BLCS64rr + 29627132U, // BLSFILL32rm + 25432828U, // BLSFILL32rr + 33821436U, // BLSFILL64rm + 25432828U, // BLSFILL64rr + 29627060U, // BLSI32rm + 25432756U, // BLSI32rr + 33821364U, // BLSI64rm + 25432756U, // BLSI64rr + 29626588U, // BLSIC32rm + 25432284U, // BLSIC32rr + 33820892U, // BLSIC64rm + 25432284U, // BLSIC64rr + 29627074U, // BLSMSK32rm + 25432770U, // BLSMSK32rr + 33821378U, // BLSMSK64rm + 25432770U, // BLSMSK64rr + 29627453U, // BLSR32rm + 25433149U, // BLSR32rr + 33821757U, // BLSR64rm + 25433149U, // BLSR64rr + 29626688U, // BOUNDS16rm + 33820992U, // BOUNDS32rm + 38015591U, // BSF16rm + 25432679U, // BSF16rr + 29626983U, // BSF32rm + 25432679U, // BSF32rr + 33821287U, // BSF64rm + 25432679U, // BSF64rr + 38016056U, // BSR16rm + 25433144U, // BSR16rr + 29627448U, // BSR32rm + 25433144U, // BSR32rr + 33821752U, // BSR64rm + 25433144U, // BSR64rr + 4959U, // BSWAP16r_BAD + 4959U, // BSWAP32r + 4959U, // BSWAP64r + 271555U, // BT16mi8 + 271555U, // BT16mr + 25433283U, // BT16ri8 + 25433283U, // BT16rr + 279747U, // BT32mi8 + 279747U, // BT32mr + 25433283U, // BT32ri8 + 25433283U, // BT32rr + 283843U, // BT64mi8 + 283843U, // BT64mr + 25433283U, // BT64ri8 + 25433283U, // BT64rr + 270576U, // BTC16mi8 + 270576U, // BTC16mr + 4468976U, // BTC16ri8 + 4468976U, // BTC16rr + 278768U, // BTC32mi8 + 278768U, // BTC32mr + 4468976U, // BTC32ri8 + 4468976U, // BTC32rr + 282864U, // BTC64mi8 + 282864U, // BTC64mr + 4468976U, // BTC64ri8 + 4468976U, // BTC64rr + 271427U, // BTR16mi8 + 271427U, // BTR16mr + 4469827U, // BTR16ri8 + 4469827U, // BTR16rr + 279619U, // BTR32mi8 + 279619U, // BTR32mr + 4469827U, // BTR32ri8 + 4469827U, // BTR32rr + 283715U, // BTR64mi8 + 283715U, // BTR64mr + 4469827U, // BTR64ri8 + 4469827U, // BTR64rr + 271537U, // BTS16mi8 + 271537U, // BTS16mr + 4469937U, // BTS16ri8 + 4469937U, // BTS16rr + 279729U, // BTS32mi8 + 279729U, // BTS32mr + 4469937U, // BTS32ri8 + 4469937U, // BTS32rr + 283825U, // BTS64mi8 + 283825U, // BTS64mr + 4469937U, // BTS64ri8 + 4469937U, // BTS64rr + 1774457509U, // BZHI32rm + 696521381U, // BZHI32rr + 1778651813U, // BZHI64rm + 696521381U, // BZHI64rr + 8941U, // CALL16m + 8941U, // CALL16m_NT + 4845U, // CALL16r + 4845U, // CALL16r_NT + 17133U, // CALL32m + 17133U, // CALL32m_NT + 4845U, // CALL32r + 4845U, // CALL32r_NT + 21229U, // CALL64m + 21229U, // CALL64m_NT + 29421U, // CALL64pcrel32 + 4845U, // CALL64r + 4845U, // CALL64r_NT + 29421U, // CALLpcrel16 + 29421U, // CALLpcrel32 + 2947U, // CBW + 2702U, // CDQ + 2488U, // CDQE + 2352U, // CLAC + 2384U, // CLC + 2434U, // CLD + 25167U, // CLDEMOTE + 25890U, // CLFLUSHOPT + 2556U, // CLGI + 2566U, // CLI + 17848U, // CLRSSBSY + 2877U, // CLTS + 24765U, // CLWB + 2663U, // CLZEROr + 2388U, // CMC + 8654926U, // CMOVA16rm + 4460622U, // CMOVA16rr + 12849230U, // CMOVA32rm + 4460622U, // CMOVA32rr + 17043534U, // CMOVA64rm + 4460622U, // CMOVA64rr + 8655260U, // CMOVAE16rm + 4460956U, // CMOVAE16rr + 12849564U, // CMOVAE32rm + 4460956U, // CMOVAE32rr + 17043868U, // CMOVAE64rm + 4460956U, // CMOVAE64rr + 8655030U, // CMOVB16rm + 4460726U, // CMOVB16rr + 12849334U, // CMOVB32rm + 4460726U, // CMOVB32rr + 17043638U, // CMOVB64rm + 4460726U, // CMOVB64rr + 8655280U, // CMOVBE16rm + 4460976U, // CMOVBE16rr + 12849584U, // CMOVBE32rm + 4460976U, // CMOVBE32rr + 17043888U, // CMOVBE64rm + 4460976U, // CMOVBE64rr + 8655456U, // CMOVE16rm + 4461152U, // CMOVE16rr + 12849760U, // CMOVE32rm + 4461152U, // CMOVE32rr + 17044064U, // CMOVE64rm + 4461152U, // CMOVE64rr + 8655506U, // CMOVG16rm + 4461202U, // CMOVG16rr + 12849810U, // CMOVG32rm + 4461202U, // CMOVG32rr + 17044114U, // CMOVG64rm + 4461202U, // CMOVG64rr + 8655300U, // CMOVGE16rm + 4460996U, // CMOVGE16rr + 12849604U, // CMOVGE32rm + 4460996U, // CMOVGE32rr + 17043908U, // CMOVGE64rm + 4460996U, // CMOVGE64rr + 8655649U, // CMOVL16rm + 4461345U, // CMOVL16rr + 12849953U, // CMOVL32rm + 4461345U, // CMOVL32rr + 17044257U, // CMOVL64rm + 4461345U, // CMOVL64rr + 8655324U, // CMOVLE16rm + 4461020U, // CMOVLE16rr + 12849628U, // CMOVLE32rm + 4461020U, // CMOVLE32rr + 17043932U, // CMOVLE64rm + 4461020U, // CMOVLE64rr + 8655352U, // CMOVNE16rm + 4461048U, // CMOVNE16rr + 12849656U, // CMOVNE32rm + 4461048U, // CMOVNE32rr + 17043960U, // CMOVNE64rm + 4461048U, // CMOVNE64rr + 8655690U, // CMOVNO16rm + 4461386U, // CMOVNO16rr + 12849994U, // CMOVNO32rm + 4461386U, // CMOVNO32rr + 17044298U, // CMOVNO64rm + 4461386U, // CMOVNO64rr + 8655751U, // CMOVNP16rm + 4461447U, // CMOVNP16rr + 12850055U, // CMOVNP32rm + 4461447U, // CMOVNP32rr + 17044359U, // CMOVNP64rm + 4461447U, // CMOVNP64rr + 8656027U, // CMOVNS16rm + 4461723U, // CMOVNS16rr + 12850331U, // CMOVNS32rm + 4461723U, // CMOVNS32rr + 17044635U, // CMOVNS64rm + 4461723U, // CMOVNS64rr + 8655704U, // CMOVO16rm + 4461400U, // CMOVO16rr + 12850008U, // CMOVO32rm + 4461400U, // CMOVO32rr + 17044312U, // CMOVO64rm + 4461400U, // CMOVO64rr + 8655791U, // CMOVP16rm + 4461487U, // CMOVP16rr + 12850095U, // CMOVP32rm + 4461487U, // CMOVP32rr + 17044399U, // CMOVP64rm + 4461487U, // CMOVP64rr + 8656060U, // CMOVS16rm + 4461756U, // CMOVS16rr + 12850364U, // CMOVS32rm + 4461756U, // CMOVS32rr + 17044668U, // CMOVS64rm + 4461756U, // CMOVS64rr + 5767U, // CMP16i16 + 271216U, // CMP16mi + 271216U, // CMP16mi8 + 271216U, // CMP16mr + 25432944U, // CMP16ri + 25432944U, // CMP16ri8 + 38015856U, // CMP16rm + 25432944U, // CMP16rr + 25432944U, // CMP16rr_REV + 5921U, // CMP32i32 + 279408U, // CMP32mi + 279408U, // CMP32mi8 + 279408U, // CMP32mr + 25432944U, // CMP32ri + 25432944U, // CMP32ri8 + 29627248U, // CMP32rm + 25432944U, // CMP32rr + 25432944U, // CMP32rr_REV + 6025U, // CMP64i32 + 283504U, // CMP64mi32 + 283504U, // CMP64mi8 + 283504U, // CMP64mr + 25432944U, // CMP64ri32 + 25432944U, // CMP64ri8 + 33821552U, // CMP64rm + 25432944U, // CMP64rr + 25432944U, // CMP64rr_REV + 5665U, // CMP8i8 + 287600U, // CMP8mi + 287600U, // CMP8mi8 + 287600U, // CMP8mr + 25432944U, // CMP8ri + 25432944U, // CMP8ri8 + 42210160U, // CMP8rm + 25432944U, // CMP8rr + 25432944U, // CMP8rr_REV + 32925U, // CMPSB + 37227U, // CMPSL + 41941U, // CMPSQ + 46450U, // CMPSW + 49248U, // CMPXCHG16B + 270967U, // CMPXCHG16rm + 25432695U, // CMPXCHG16rr + 279159U, // CMPXCHG32rm + 25432695U, // CMPXCHG32rr + 283255U, // CMPXCHG64rm + 25432695U, // CMPXCHG64rr + 20588U, // CMPXCHG8B + 287351U, // CMPXCHG8rm + 25432695U, // CMPXCHG8rr + 2428U, // CPUID + 2659U, // CQO + 2464U, // CWD + 2468U, // CWDE + 2312U, // DAA + 2783U, // DAS + 2238U, // DATA16_PREFIX + 8392U, // DEC16m + 4296U, // DEC16r + 4296U, // DEC16r_alt + 16584U, // DEC32m + 4296U, // DEC32r + 4296U, // DEC32r_alt + 20680U, // DEC64m + 4296U, // DEC64r + 24776U, // DEC8m + 4296U, // DEC8r + 9545U, // DIV16m + 5449U, // DIV16r + 17737U, // DIV32m + 5449U, // DIV32r + 21833U, // DIV64m + 5449U, // DIV64r + 25929U, // DIV8m + 5449U, // DIV8r + 2207U, // ENDBR32 + 2224U, // ENDBR64 + 25433098U, // ENTER + 46412524U, // FARCALL16i + 53996U, // FARCALL16m + 46412524U, // FARCALL32i + 53997U, // FARCALL32m + 53996U, // FARCALL64 + 537461U, // FARJMP16i + 54133U, // FARJMP16m + 537461U, // FARJMP32i + 54134U, // FARJMP32m + 54133U, // FARJMP64 + 2648U, // FSETPM + 2372U, // GETSEC + 2902U, // HLT + 9544U, // IDIV16m + 5448U, // IDIV16r + 17736U, // IDIV32m + 5448U, // IDIV32r + 21832U, // IDIV64m + 5448U, // IDIV64r + 25928U, // IDIV8m + 5448U, // IDIV8r + 8987U, // IMUL16m + 4891U, // IMUL16r + 8655643U, // IMUL16rm + 1782846235U, // IMUL16rmi + 1782846235U, // IMUL16rmi8 + 4461339U, // IMUL16rr + 696521499U, // IMUL16rri + 696521499U, // IMUL16rri8 + 17179U, // IMUL32m + 4891U, // IMUL32r + 12849947U, // IMUL32rm + 1774457627U, // IMUL32rmi + 1774457627U, // IMUL32rmi8 + 4461339U, // IMUL32rr + 696521499U, // IMUL32rri + 696521499U, // IMUL32rri8 + 21275U, // IMUL64m + 4891U, // IMUL64r + 17044251U, // IMUL64rm + 1778651931U, // IMUL64rmi32 + 1778651931U, // IMUL64rmi8 + 4461339U, // IMUL64rr + 696521499U, // IMUL64rri32 + 696521499U, // IMUL64rri8 + 25371U, // IMUL8m + 4891U, // IMUL8r + 59007U, // IN16ri + 3093U, // IN16rr + 59160U, // IN32ri + 3103U, // IN32rr + 58905U, // IN8ri + 3083U, // IN8rr + 8427U, // INC16m + 4331U, // INC16r + 4331U, // INC16r_alt + 16619U, // INC32m + 4331U, // INC32r + 4331U, // INC32r_alt + 20715U, // INC64m + 4331U, // INC64r + 24811U, // INC8m + 4331U, // INC8r + 4423U, // INCSSPD + 5053U, // INCSSPQ + 848016U, // INSB + 852318U, // INSL + 857445U, // INSW + 58630U, // INT + 2202U, // INT1 + 2219U, // INT3 + 2670U, // INTO + 2450U, // INVD + 50599184U, // INVEPT32 + 50599184U, // INVEPT64 + 25220U, // INVLPG + 3049U, // INVLPGA32 + 3066U, // INVLPGA64 + 50598160U, // INVPCID32 + 50598160U, // INVPCID64 + 50598176U, // INVVPID32 + 50598176U, // INVVPID64 + 2882U, // IRET16 + 2438U, // IRET32 + 2725U, // IRET64 + 29072U, // JAE_1 + 29072U, // JAE_2 + 29072U, // JAE_4 + 28740U, // JA_1 + 28740U, // JA_2 + 28740U, // JA_4 + 29092U, // JBE_1 + 29092U, // JBE_2 + 29092U, // JBE_4 + 28812U, // JB_1 + 28812U, // JB_2 + 28812U, // JB_4 + 30153U, // JCXZ + 30146U, // JECXZ + 29132U, // JE_1 + 29132U, // JE_2 + 29132U, // JE_4 + 29112U, // JGE_1 + 29112U, // JGE_2 + 29112U, // JGE_4 + 29312U, // JG_1 + 29312U, // JG_2 + 29312U, // JG_4 + 29136U, // JLE_1 + 29136U, // JLE_2 + 29136U, // JLE_4 + 29416U, // JL_1 + 29416U, // JL_2 + 29416U, // JL_4 + 9078U, // JMP16m + 9078U, // JMP16m_NT + 4982U, // JMP16r + 4982U, // JMP16r_NT + 17270U, // JMP32m + 17270U, // JMP32m_NT + 4982U, // JMP32r + 4982U, // JMP32r_NT + 21366U, // JMP64m + 21366U, // JMP64m_NT + 4982U, // JMP64r + 4982U, // JMP64r_NT + 29558U, // JMP_1 + 29558U, // JMP_2 + 29558U, // JMP_4 + 29156U, // JNE_1 + 29156U, // JNE_2 + 29156U, // JNE_4 + 29502U, // JNO_1 + 29502U, // JNO_2 + 29502U, // JNO_4 + 29563U, // JNP_1 + 29563U, // JNP_2 + 29563U, // JNP_4 + 29839U, // JNS_1 + 29839U, // JNS_2 + 29839U, // JNS_4 + 29498U, // JO_1 + 29498U, // JO_2 + 29498U, // JO_4 + 29548U, // JP_1 + 29548U, // JP_2 + 29548U, // JP_4 + 30159U, // JRCXZ + 29827U, // JS_1 + 29827U, // JS_2 + 29827U, // JS_4 + 2513U, // LAHF + 38015995U, // LAR16rm + 25433083U, // LAR16rr + 38015995U, // LAR32rm + 25433083U, // LAR32rr + 38015995U, // LAR64rm + 25433083U, // LAR64rr + 54793319U, // LDS16rm + 54793319U, // LDS32rm + 58986559U, // LEA16r + 58986559U, // LEA32r + 58986559U, // LEA64_32r + 58986559U, // LEA64r + 2500U, // LEAVE + 2500U, // LEAVE64 + 54793324U, // LES16rm + 54793324U, // LES32rm + 54793337U, // LFS16rm + 54793337U, // LFS32rm + 54793337U, // LFS64rm + 54471U, // LGDT16m + 54471U, // LGDT32m + 54471U, // LGDT64m + 54793342U, // LGS16rm + 54793342U, // LGS32rm + 54793342U, // LGS64rm + 54483U, // LIDT16m + 54483U, // LIDT32m + 54483U, // LIDT64m + 9439U, // LLDT16m + 5343U, // LLDT16r + 4220U, // LLWPCB + 4220U, // LLWPCB64 + 9561U, // LMSW16m + 5465U, // LMSW16r + 2574U, // LOCK_PREFIX + 75242U, // LODSB + 79628U, // LODSL + 83871U, // LODSQ + 87747U, // LODSW + 29588U, // LOOP + 29184U, // LOOPE + 29161U, // LOOPNE + 4716U, // LRETIL + 5046U, // LRETIQ + 4716U, // LRETIW + 2534U, // LRETL + 2719U, // LRETQ + 2534U, // LRETW + 38015760U, // LSL16rm + 25432848U, // LSL16rr + 38015760U, // LSL32rm + 25432848U, // LSL32rr + 38015760U, // LSL64rm + 25432848U, // LSL64rr + 54793388U, // LSS16rm + 54793388U, // LSS32rm + 54793388U, // LSS64rm + 9288U, // LTRm + 5192U, // LTRr + 1774457991U, // LWPINS32rmi + 696521863U, // LWPINS32rri + 1774457991U, // LWPINS64rmi + 696521863U, // LWPINS64rri + 1774457558U, // LWPVAL32rmi + 696521430U, // LWPVAL32rri + 1774457558U, // LWPVAL64rmi + 696521430U, // LWPVAL64rri + 38016248U, // LZCNT16rm + 25433336U, // LZCNT16rr + 29627640U, // LZCNT32rm + 25433336U, // LZCNT32rr + 33821944U, // LZCNT64rm + 25433336U, // LZCNT64rr + 3114U, // MONITORXrrr + 2640U, // MONTMUL + 91823U, // MOV16ao16 + 91823U, // MOV16ao32 + 91801U, // MOV16ao64 + 271694U, // MOV16mi + 271694U, // MOV16mr + 271694U, // MOV16ms + 1140046U, // MOV16o16a + 1140046U, // MOV16o32a + 1139801U, // MOV16o64a + 25433422U, // MOV16ri + 25433422U, // MOV16ri_alt + 38016334U, // MOV16rm + 25433422U, // MOV16rr + 25433422U, // MOV16rr_REV + 25433422U, // MOV16rs + 38016334U, // MOV16sm + 25433422U, // MOV16sr + 96077U, // MOV32ao16 + 96077U, // MOV32ao32 + 96053U, // MOV32ao64 + 25433422U, // MOV32cr + 25433422U, // MOV32dr + 279886U, // MOV32mi + 279886U, // MOV32mr + 1406286U, // MOV32o16a + 1406286U, // MOV32o32a + 1406041U, // MOV32o64a + 25433422U, // MOV32rc + 25433422U, // MOV32rd + 25433422U, // MOV32ri + 25433422U, // MOV32ri_alt + 29627726U, // MOV32rm + 25433422U, // MOV32rr + 25433422U, // MOV32rr_REV + 25433422U, // MOV32rs + 25433422U, // MOV32sr + 100301U, // MOV64ao32 + 100277U, // MOV64ao64 + 25433422U, // MOV64cr + 25433422U, // MOV64dr + 283982U, // MOV64mi32 + 283982U, // MOV64mr + 1672526U, // MOV64o32a + 1672281U, // MOV64o64a + 25433422U, // MOV64rc + 25433422U, // MOV64rd + 25433177U, // MOV64ri + 25433422U, // MOV64ri32 + 33822030U, // MOV64rm + 25433422U, // MOV64rr + 25433422U, // MOV64rr_REV + 25433422U, // MOV64rs + 25433422U, // MOV64sr + 104009U, // MOV8ao16 + 104009U, // MOV8ao32 + 103987U, // MOV8ao64 + 288078U, // MOV8mi + 288078U, // MOV8mr + 288078U, // MOV8mr_NOREX + 1938766U, // MOV8o16a + 1938766U, // MOV8o32a + 1938521U, // MOV8o64a + 25433422U, // MOV8ri + 25433422U, // MOV8ri_alt + 42210638U, // MOV8rm + 42210638U, // MOV8rm_NOREX + 25433422U, // MOV8rr + 25433422U, // MOV8rr_NOREX + 25433422U, // MOV8rr_REV + 270769U, // MOVBE16mr + 38015409U, // MOVBE16rm + 278961U, // MOVBE32mr + 29626801U, // MOVBE32rm + 283057U, // MOVBE64mr + 33821105U, // MOVBE64rm + 63180885U, // MOVDIR64B16 + 63180885U, // MOVDIR64B32 + 63180885U, // MOVDIR64B64 + 279211U, // MOVDIRI32 + 283307U, // MOVDIRI64 + 67432612U, // MOVSB + 71631233U, // MOVSL + 75867115U, // MOVSQ + 80024953U, // MOVSW + 38016426U, // MOVSX16rm16 + 42210730U, // MOVSX16rm8 + 25433514U, // MOVSX16rr16 + 25433514U, // MOVSX16rr8 + 38016426U, // MOVSX32rm16 + 42210730U, // MOVSX32rm8 + 42210730U, // MOVSX32rm8_NOREX + 25433514U, // MOVSX32rr16 + 25433514U, // MOVSX32rr8 + 25433514U, // MOVSX32rr8_NOREX + 38016426U, // MOVSX64rm16 + 29626760U, // MOVSX64rm32 + 42210730U, // MOVSX64rm8 + 25433514U, // MOVSX64rr16 + 25432456U, // MOVSX64rr32 + 25433514U, // MOVSX64rr8 + 38016433U, // MOVZX16rm16 + 42210737U, // MOVZX16rm8 + 25433521U, // MOVZX16rr16 + 25433521U, // MOVZX16rr8 + 38016433U, // MOVZX32rm16 + 42210737U, // MOVZX32rm8 + 42210737U, // MOVZX32rm8_NOREX + 25433521U, // MOVZX32rr16 + 25433521U, // MOVZX32rr8 + 25433521U, // MOVZX32rr8_NOREX + 38016433U, // MOVZX64rm16 + 42210737U, // MOVZX64rm8 + 25433521U, // MOVZX64rr16 + 25433521U, // MOVZX64rr8 + 8988U, // MUL16m + 4892U, // MUL16r + 17180U, // MUL32m + 4892U, // MUL32r + 21276U, // MUL64m + 4892U, // MUL64r + 25372U, // MUL8m + 4892U, // MUL8r + 159651212U, // MULX32rm + 696522124U, // MULX32rr + 1233393036U, // MULX64rm + 696522124U, // MULX64rr + 3123U, // MWAITXrrr + 8818U, // NEG16m + 4722U, // NEG16r + 17010U, // NEG32m + 4722U, // NEG32r + 21106U, // NEG64m + 4722U, // NEG64r + 25202U, // NEG8m + 4722U, // NEG8r + 2686U, // NOOP + 9103U, // NOOP18_16m4 + 9103U, // NOOP18_16m5 + 9103U, // NOOP18_16m6 + 9103U, // NOOP18_16m7 + 5007U, // NOOP18_16r4 + 5007U, // NOOP18_16r5 + 5007U, // NOOP18_16r6 + 5007U, // NOOP18_16r7 + 17295U, // NOOP18_m4 + 17295U, // NOOP18_m5 + 17295U, // NOOP18_m6 + 17295U, // NOOP18_m7 + 5007U, // NOOP18_r4 + 5007U, // NOOP18_r5 + 5007U, // NOOP18_r6 + 5007U, // NOOP18_r7 + 46412687U, // NOOP19rr + 17295U, // NOOPL + 17295U, // NOOPL_19 + 17295U, // NOOPL_1d + 17295U, // NOOPL_1e + 5007U, // NOOPLr + 21391U, // NOOPQ + 5007U, // NOOPQr + 9103U, // NOOPW + 9103U, // NOOPW_19 + 9103U, // NOOPW_1c + 9103U, // NOOPW_1d + 9103U, // NOOPW_1e + 5007U, // NOOPWr + 9483U, // NOT16m + 5387U, // NOT16r + 17675U, // NOT32m + 5387U, // NOT32r + 21771U, // NOT64m + 5387U, // NOT64r + 25867U, // NOT8m + 5387U, // NOT8r + 5777U, // OR16i16 + 271383U, // OR16mi + 271383U, // OR16mi8 + 271383U, // OR16mr + 4469783U, // OR16ri + 4469783U, // OR16ri8 + 8664087U, // OR16rm + 4469783U, // OR16rr + 4461591U, // OR16rr_REV + 5932U, // OR32i32 + 279575U, // OR32mi + 279575U, // OR32mi8 + 279575U, // OR32mr + 4469783U, // OR32ri + 4469783U, // OR32ri8 + 12858391U, // OR32rm + 4469783U, // OR32rr + 4461591U, // OR32rr_REV + 6060U, // OR64i32 + 283671U, // OR64mi32 + 283671U, // OR64mi8 + 283671U, // OR64mr + 4469783U, // OR64ri32 + 4469783U, // OR64ri8 + 17052695U, // OR64rm + 4469783U, // OR64rr + 4461591U, // OR64rr_REV + 5675U, // OR8i8 + 287767U, // OR8mi + 287767U, // OR8mi8 + 287767U, // OR8mr + 4469783U, // OR8ri + 4469783U, // OR8ri8 + 21246999U, // OR8rm + 4469783U, // OR8rr + 4461591U, // OR8rr_REV + 1107261U, // OUT16ir + 2951U, // OUT16rr + 1369405U, // OUT32ir + 3005U, // OUT32rr + 1893693U, // OUT8ir + 2579U, // OUT8rr + 75735U, // OUTSB + 79842U, // OUTSL + 88045U, // OUTSW + 2539U, // PCONFIG + 159650662U, // PDEP32rm + 696521574U, // PDEP32rr + 1233392486U, // PDEP64rm + 696521574U, // PDEP64rr + 159651138U, // PEXT32rm + 696522050U, // PEXT32rr + 1233392962U, // PEXT64rm + 696522050U, // PEXT64rr + 5018U, // POP16r + 9114U, // POP16rmm + 5018U, // POP16rmr + 5018U, // POP32r + 17306U, // POP32rmm + 5018U, // POP32rmr + 5018U, // POP64r + 21402U, // POP64rmm + 5018U, // POP64rmr + 2941U, // POPA16 + 2597U, // POPA32 + 2803U, // POPDS16 + 2803U, // POPDS32 + 2818U, // POPES16 + 2818U, // POPES32 + 2529U, // POPF16 + 2422U, // POPF32 + 2713U, // POPF64 + 2833U, // POPFS16 + 2833U, // POPFS32 + 2833U, // POPFS64 + 2848U, // POPGS16 + 2848U, // POPGS32 + 2848U, // POPGS64 + 2870U, // POPSS16 + 2870U, // POPSS32 + 21062U, // PTWRITE64m + 4678U, // PTWRITE64r + 16966U, // PTWRITEm + 4678U, // PTWRITEr + 4761U, // PUSH16i8 + 4761U, // PUSH16r + 8857U, // PUSH16rmm + 4761U, // PUSH16rmr + 4761U, // PUSH32i8 + 4761U, // PUSH32r + 17049U, // PUSH32rmm + 4761U, // PUSH32rmr + 4761U, // PUSH64i32 + 4761U, // PUSH64i8 + 4761U, // PUSH64r + 21145U, // PUSH64rmm + 4761U, // PUSH64rmr + 2934U, // PUSHA16 + 2590U, // PUSHA32 + 2787U, // PUSHCS16 + 2787U, // PUSHCS32 + 2795U, // PUSHDS16 + 2795U, // PUSHDS32 + 2810U, // PUSHES16 + 2810U, // PUSHES32 + 2523U, // PUSHF16 + 2415U, // PUSHF32 + 2706U, // PUSHF64 + 2825U, // PUSHFS16 + 2825U, // PUSHFS32 + 2825U, // PUSHFS64 + 2840U, // PUSHGS16 + 2840U, // PUSHGS32 + 2840U, // PUSHGS64 + 2862U, // PUSHSS16 + 2862U, // PUSHSS32 + 4761U, // PUSHi16 + 4761U, // PUSHi32 + 8926U, // RCL16m1 + 2106078U, // RCL16mCL + 84157150U, // RCL16mi + 2364126U, // RCL16r1 + 2101982U, // RCL16rCL + 88347358U, // RCL16ri + 17118U, // RCL32m1 + 2114270U, // RCL32mCL + 84165342U, // RCL32mi + 2364126U, // RCL32r1 + 2101982U, // RCL32rCL + 88347358U, // RCL32ri + 21214U, // RCL64m1 + 2118366U, // RCL64mCL + 84169438U, // RCL64mi + 2364126U, // RCL64r1 + 2101982U, // RCL64rCL + 88347358U, // RCL64ri + 25310U, // RCL8m1 + 2122462U, // RCL8mCL + 84173534U, // RCL8mi + 2364126U, // RCL8r1 + 2101982U, // RCL8rCL + 88347358U, // RCL8ri + 2368517U, // RCR16m1 + 2106373U, // RCR16mCL + 84157445U, // RCR16mi + 2364421U, // RCR16r1 + 2102277U, // RCR16rCL + 88347653U, // RCR16ri + 2376709U, // RCR32m1 + 2114565U, // RCR32mCL + 84165637U, // RCR32mi + 2364421U, // RCR32r1 + 2102277U, // RCR32rCL + 88347653U, // RCR32ri + 2380805U, // RCR64m1 + 2118661U, // RCR64mCL + 84169733U, // RCR64mi + 2364421U, // RCR64r1 + 2102277U, // RCR64rCL + 88347653U, // RCR64ri + 2384901U, // RCR8m1 + 2122757U, // RCR8mCL + 84173829U, // RCR8mi + 2364421U, // RCR8r1 + 2102277U, // RCR8rCL + 88347653U, // RCR8ri + 4615U, // RDFSBASE + 4615U, // RDFSBASE64 + 4635U, // RDGSBASE + 4635U, // RDGSBASE64 + 2757U, // RDMSR + 4377U, // RDPID32 + 4377U, // RDPID64 + 2906U, // RDPKRUr + 2392U, // RDPMC + 4408U, // RDRAND16r + 4408U, // RDRAND32r + 4408U, // RDRAND64r + 4360U, // RDSEED16r + 4360U, // RDSEED32r + 4360U, // RDSEED64r + 4432U, // RDSSPD + 5062U, // RDSSPQ + 2405U, // RDTSC + 2675U, // RDTSCP + 2482U, // REPNE_PREFIX + 2682U, // REP_PREFIX + 5355U, // RETIL + 5355U, // RETIQ + 5355U, // RETIW + 2883U, // RETL + 2883U, // RETQ + 2883U, // RETW + 2232U, // REX64_PREFIX + 2368261U, // ROL16m1 + 2106117U, // ROL16mCL + 84157189U, // ROL16mi + 2364165U, // ROL16r1 + 2102021U, // ROL16rCL + 88347397U, // ROL16ri + 2376453U, // ROL32m1 + 2114309U, // ROL32mCL + 84165381U, // ROL32mi + 2364165U, // ROL32r1 + 2102021U, // ROL32rCL + 88347397U, // ROL32ri + 2380549U, // ROL64m1 + 2118405U, // ROL64mCL + 84169477U, // ROL64mi + 2364165U, // ROL64r1 + 2102021U, // ROL64rCL + 88347397U, // ROL64ri + 2384645U, // ROL8m1 + 2122501U, // ROL8mCL + 84173573U, // ROL8mi + 2364165U, // ROL8r1 + 2102021U, // ROL8rCL + 88347397U, // ROL8ri + 2368534U, // ROR16m1 + 2106390U, // ROR16mCL + 84157462U, // ROR16mi + 2364438U, // ROR16r1 + 2102294U, // ROR16rCL + 88347670U, // ROR16ri + 2376726U, // ROR32m1 + 2114582U, // ROR32mCL + 84165654U, // ROR32mi + 2364438U, // ROR32r1 + 2102294U, // ROR32rCL + 88347670U, // ROR32ri + 2380822U, // ROR64m1 + 2118678U, // ROR64mCL + 84169750U, // ROR64mi + 2364438U, // ROR64r1 + 2102294U, // ROR64rCL + 88347670U, // ROR64ri + 2384918U, // ROR8m1 + 2122774U, // ROR8mCL + 84173846U, // ROR8mi + 2364438U, // ROR8r1 + 2102294U, // ROR8rCL + 88347670U, // ROR8ri + 2311329188U, // RORX32mi + 2844005796U, // RORX32ri + 2315523492U, // RORX64mi + 2844005796U, // RORX64ri + 2655U, // RSM + 17311U, // RSTORSSP + 2518U, // SAHF + 2368209U, // SAL16m1 + 2106065U, // SAL16mCL + 271057U, // SAL16mi + 2364113U, // SAL16r1 + 2101969U, // SAL16rCL + 4461265U, // SAL16ri + 2376401U, // SAL32m1 + 2114257U, // SAL32mCL + 279249U, // SAL32mi + 2364113U, // SAL32r1 + 2101969U, // SAL32rCL + 4461265U, // SAL32ri + 2380497U, // SAL64m1 + 2118353U, // SAL64mCL + 283345U, // SAL64mi + 2364113U, // SAL64r1 + 2101969U, // SAL64rCL + 4461265U, // SAL64ri + 2384593U, // SAL8m1 + 2122449U, // SAL8mCL + 287441U, // SAL8mi + 2364113U, // SAL8r1 + 2101969U, // SAL8rCL + 4461265U, // SAL8ri + 2379U, // SALC + 2368512U, // SAR16m1 + 2106368U, // SAR16mCL + 84157440U, // SAR16mi + 2364416U, // SAR16r1 + 2102272U, // SAR16rCL + 88347648U, // SAR16ri + 2376704U, // SAR32m1 + 2114560U, // SAR32mCL + 84165632U, // SAR32mi + 2364416U, // SAR32r1 + 2102272U, // SAR32rCL + 88347648U, // SAR32ri + 2380800U, // SAR64m1 + 2118656U, // SAR64mCL + 84169728U, // SAR64mi + 2364416U, // SAR64r1 + 2102272U, // SAR64rCL + 88347648U, // SAR64ri + 2384896U, // SAR8m1 + 2122752U, // SAR8mCL + 84173824U, // SAR8mi + 2364416U, // SAR8r1 + 2102272U, // SAR8rCL + 88347648U, // SAR8ri + 1774458264U, // SARX32rm + 696522136U, // SARX32rr + 1778652568U, // SARX64rm + 696522136U, // SARX64rr + 2690U, // SAVEPREVSSP + 5714U, // SBB16i16 + 270455U, // SBB16mi + 270455U, // SBB16mi8 + 270455U, // SBB16mr + 4468855U, // SBB16ri + 4468855U, // SBB16ri8 + 8663159U, // SBB16rm + 4468855U, // SBB16rr + 4460663U, // SBB16rr_REV + 5838U, // SBB32i32 + 278647U, // SBB32mi + 278647U, // SBB32mi8 + 278647U, // SBB32mr + 4468855U, // SBB32ri + 4468855U, // SBB32ri8 + 12857463U, // SBB32rm + 4468855U, // SBB32rr + 4460663U, // SBB32rr_REV + 5975U, // SBB64i32 + 282743U, // SBB64mi32 + 282743U, // SBB64mi8 + 282743U, // SBB64mr + 4468855U, // SBB64ri32 + 4468855U, // SBB64ri8 + 17051767U, // SBB64rm + 4468855U, // SBB64rr + 4460663U, // SBB64rr_REV + 5590U, // SBB8i8 + 286839U, // SBB8mi + 286839U, // SBB8mi8 + 286839U, // SBB8mr + 4468855U, // SBB8ri + 4468855U, // SBB8ri8 + 21246071U, // SBB8rm + 4468855U, // SBB8rr + 4460663U, // SBB8rr_REV + 62943U, // SCASB + 67328U, // SCASL + 108435U, // SCASQ + 71352U, // SCASW + 24981U, // SETAEm + 4501U, // SETAEr + 24648U, // SETAm + 4168U, // SETAr + 25001U, // SETBEm + 4521U, // SETBEr + 24747U, // SETBm + 4267U, // SETBr + 25143U, // SETEm + 4663U, // SETEr + 25021U, // SETGEm + 4541U, // SETGEr + 25228U, // SETGm + 4748U, // SETGr + 25045U, // SETLEm + 4565U, // SETLEr + 25365U, // SETLm + 4885U, // SETLr + 25073U, // SETNEm + 4593U, // SETNEr + 25411U, // SETNOm + 4931U, // SETNOr + 25472U, // SETNPm + 4992U, // SETNPr + 25748U, // SETNSm + 5268U, // SETNSr + 25426U, // SETOm + 4946U, // SETOr + 25513U, // SETPm + 5033U, // SETPr + 3130U, // SETSSBSY + 25782U, // SETSm + 5302U, // SETSr + 54477U, // SGDT16m + 54477U, // SGDT32m + 54477U, // SGDT64m + 2368227U, // SHL16m1 + 2106083U, // SHL16mCL + 84157155U, // SHL16mi + 2364131U, // SHL16r1 + 2101987U, // SHL16rCL + 88347363U, // SHL16ri + 2376419U, // SHL32m1 + 2114275U, // SHL32mCL + 84165347U, // SHL32mi + 2364131U, // SHL32r1 + 2101987U, // SHL32rCL + 88347363U, // SHL32ri + 2380515U, // SHL64m1 + 2118371U, // SHL64mCL + 84169443U, // SHL64mi + 2364131U, // SHL64r1 + 2101987U, // SHL64rCL + 88347363U, // SHL64ri + 2384611U, // SHL8m1 + 2122467U, // SHL8mCL + 84173539U, // SHL8mi + 2364131U, // SHL8r1 + 2101987U, // SHL8rCL + 88347363U, // SHL8ri + 268706089U, // SHLD16mrCL + 2281972009U, // SHLD16mri8 + 272896297U, // SHLD16rrCL + 3359904041U, // SHLD16rri8 + 268714281U, // SHLD32mrCL + 2281980201U, // SHLD32mri8 + 272896297U, // SHLD32rrCL + 3359904041U, // SHLD32rri8 + 268718377U, // SHLD64mrCL + 2281984297U, // SHLD64mri8 + 272896297U, // SHLD64rrCL + 3359904041U, // SHLD64rri8 + 1774458246U, // SHLX32rm + 696522118U, // SHLX32rr + 1778652550U, // SHLX64rm + 696522118U, // SHLX64rr + 2368529U, // SHR16m1 + 2106385U, // SHR16mCL + 84157457U, // SHR16mi + 2364433U, // SHR16r1 + 2102289U, // SHR16rCL + 88347665U, // SHR16ri + 2376721U, // SHR32m1 + 2114577U, // SHR32mCL + 84165649U, // SHR32mi + 2364433U, // SHR32r1 + 2102289U, // SHR32rCL + 88347665U, // SHR32ri + 2380817U, // SHR64m1 + 2118673U, // SHR64mCL + 84169745U, // SHR64mi + 2364433U, // SHR64r1 + 2102289U, // SHR64rCL + 88347665U, // SHR64ri + 2384913U, // SHR8m1 + 2122769U, // SHR8mCL + 84173841U, // SHR8mi + 2364433U, // SHR8r1 + 2102289U, // SHR8rCL + 88347665U, // SHR8ri + 268706136U, // SHRD16mrCL + 2281972056U, // SHRD16mri8 + 272896344U, // SHRD16rrCL + 3359904088U, // SHRD16rri8 + 268714328U, // SHRD32mrCL + 2281980248U, // SHRD32mri8 + 272896344U, // SHRD32rrCL + 3359904088U, // SHRD32rri8 + 268718424U, // SHRD64mrCL + 2281984344U, // SHRD64mri8 + 272896344U, // SHRD64rrCL + 3359904088U, // SHRD64rri8 + 1774458270U, // SHRX32rm + 696522142U, // SHRX32rr + 1778652574U, // SHRX64rm + 696522142U, // SHRX64rr + 54489U, // SIDT16m + 54489U, // SIDT32m + 54489U, // SIDT64m + 2994U, // SKINIT + 9445U, // SLDT16m + 5349U, // SLDT16r + 5349U, // SLDT32r + 5349U, // SLDT64r + 4228U, // SLWPCB + 4228U, // SLWPCB64 + 9567U, // SMSW16m + 5471U, // SMSW16r + 5471U, // SMSW32r + 5471U, // SMSW64r + 2357U, // STAC + 2411U, // STC + 2444U, // STD + 2561U, // STGI + 2570U, // STI + 1896598U, // STOSB + 1376612U, // STOSL + 1680334U, // STOSQ + 1119595U, // STOSW + 5197U, // STR16r + 5197U, // STR32r + 5197U, // STR64r + 9293U, // STRm + 5723U, // SUB16i16 + 270513U, // SUB16mi + 270513U, // SUB16mi8 + 270513U, // SUB16mr + 4468913U, // SUB16ri + 4468913U, // SUB16ri8 + 8663217U, // SUB16rm + 4468913U, // SUB16rr + 4460721U, // SUB16rr_REV + 5848U, // SUB32i32 + 278705U, // SUB32mi + 278705U, // SUB32mi8 + 278705U, // SUB32mr + 4468913U, // SUB32ri + 4468913U, // SUB32ri8 + 12857521U, // SUB32rm + 4468913U, // SUB32rr + 4460721U, // SUB32rr_REV + 5985U, // SUB64i32 + 282801U, // SUB64mi32 + 282801U, // SUB64mi8 + 282801U, // SUB64mr + 4468913U, // SUB64ri32 + 4468913U, // SUB64ri8 + 17051825U, // SUB64rm + 4468913U, // SUB64rr + 4460721U, // SUB64rr_REV + 5621U, // SUB8i8 + 286897U, // SUB8mi + 286897U, // SUB8mi8 + 286897U, // SUB8mr + 4468913U, // SUB8ri + 4468913U, // SUB8ri8 + 21246129U, // SUB8rm + 4468913U, // SUB8rr + 4460721U, // SUB8rr_REV + 2855U, // SWAPGS + 2632U, // SYSCALL + 2748U, // SYSENTER + 2894U, // SYSEXIT + 2739U, // SYSEXIT64 + 2887U, // SYSRET + 2731U, // SYSRET64 + 29626595U, // T1MSKC32rm + 25432291U, // T1MSKC32rr + 33820899U, // T1MSKC64rm + 25432291U, // T1MSKC64rr + 5797U, // TEST16i16 + 271662U, // TEST16mi + 271662U, // TEST16mi_alt + 271662U, // TEST16mr + 25433390U, // TEST16ri + 25433390U, // TEST16ri_alt + 25433390U, // TEST16rr + 5954U, // TEST32i32 + 279854U, // TEST32mi + 279854U, // TEST32mi_alt + 279854U, // TEST32mr + 25433390U, // TEST32ri + 25433390U, // TEST32ri_alt + 25433390U, // TEST32rr + 6082U, // TEST64i32 + 283950U, // TEST64mi32 + 283950U, // TEST64mi32_alt + 283950U, // TEST64mr + 25433390U, // TEST64ri32 + 25433390U, // TEST64ri32_alt + 25433390U, // TEST64rr + 5695U, // TEST8i8 + 288046U, // TEST8mi + 288046U, // TEST8mi_alt + 288046U, // TEST8mr + 25433390U, // TEST8ri + 25433390U, // TEST8ri_alt + 25433390U, // TEST8rr + 4655U, // TPAUSE + 38016255U, // TZCNT16rm + 25433343U, // TZCNT16rr + 29627647U, // TZCNT32rm + 25433343U, // TZCNT32rr + 33821951U, // TZCNT64rm + 25433343U, // TZCNT64rr + 29627082U, // TZMSK32rm + 25432778U, // TZMSK32rr + 33821386U, // TZMSK64rm + 25432778U, // TZMSK64rr + 2188U, // UD0 + 2198U, // UD1 + 2215U, // UD2 + 5147U, // UMONITOR16 + 5147U, // UMONITOR32 + 5147U, // UMONITOR64 + 5360U, // UMWAIT + 9266U, // VERRm + 5170U, // VERRr + 9555U, // VERWm + 5459U, // VERWr + 2625U, // VMCALL + 21490U, // VMCLEARm + 2398U, // VMFUNC + 2547U, // VMLAUNCH + 2962U, // VMLOAD32 + 3017U, // VMLOAD64 + 2617U, // VMMCALL + 20783U, // VMPTRLDm + 21812U, // VMPTRSTm + 278778U, // VMREAD32mr + 25432314U, // VMREAD32rr + 282874U, // VMREAD64mr + 25432314U, // VMREAD64rr + 2473U, // VMRESUME + 2984U, // VMRUN32 + 3039U, // VMRUN64 + 2973U, // VMSAVE32 + 3028U, // VMSAVE64 + 29626941U, // VMWRITE32rm + 25432637U, // VMWRITE32rr + 33821245U, // VMWRITE64rm + 25432637U, // VMWRITE64rr + 2506U, // VMXOFF + 21299U, // VMXON + 2448U, // WBINVD + 2455U, // WBNOINVD + 4625U, // WRFSBASE + 4625U, // WRFSBASE64 + 4645U, // WRGSBASE + 4645U, // WRGSBASE64 + 2763U, // WRMSR + 2913U, // WRPKRUr + 278898U, // WRSSD + 283612U, // WRSSQ + 278905U, // WRUSSD + 283619U, // WRUSSQ + 110850U, // XADD16rm + 114946U, // XADD16rr + 119042U, // XADD32rm + 114946U, // XADD32rr + 123138U, // XADD64rm + 114946U, // XADD64rr + 127234U, // XADD8rm + 114946U, // XADD8rr + 1061498U, // XCHG16ar + 111226U, // XCHG16rm + 131706U, // XCHG16rr + 1323642U, // XCHG32ar + 119418U, // XCHG32rm + 131706U, // XCHG32rr + 1585786U, // XCHG64ar + 123514U, // XCHG64rm + 131706U, // XCHG64rr + 127610U, // XCHG8rm + 131706U, // XCHG8rr + 2362U, // XCRYPTCBC + 2326U, // XCRYPTCFB + 2769U, // XCRYPTCTR + 2316U, // XCRYPTECB + 2336U, // XCRYPTOFB + 2920U, // XGETBV + 2346U, // XLAT + 5776U, // XOR16i16 + 271405U, // XOR16mi + 271405U, // XOR16mi8 + 271405U, // XOR16mr + 4469805U, // XOR16ri + 4469805U, // XOR16ri8 + 8664109U, // XOR16rm + 4469805U, // XOR16rr + 4461613U, // XOR16rr_REV + 5931U, // XOR32i32 + 279597U, // XOR32mi + 279597U, // XOR32mi8 + 279597U, // XOR32mr + 4469805U, // XOR32ri + 4469805U, // XOR32ri8 + 12858413U, // XOR32rm + 4469805U, // XOR32rr + 4461613U, // XOR32rr_REV + 6059U, // XOR64i32 + 283693U, // XOR64mi32 + 283693U, // XOR64mi8 + 283693U, // XOR64mr + 4469805U, // XOR64ri32 + 4469805U, // XOR64ri8 + 17052717U, // XOR64rm + 4469805U, // XOR64rr + 4461613U, // XOR64rr_REV + 5674U, // XOR8i8 + 287789U, // XOR8mi + 287789U, // XOR8mi8 + 287789U, // XOR8mr + 4469805U, // XOR8ri + 4469805U, // XOR8ri8 + 21247021U, // XOR8rm + 4469805U, // XOR8rr + 4461613U, // XOR8rr_REV + 54309U, // XRSTOR + 53268U, // XRSTOR64 + 54435U, // XRSTORS + 53288U, // XRSTORS64 + 53849U, // XSAVE + 53259U, // XSAVE64 + 53453U, // XSAVEC + 53249U, // XSAVEC64 + 54552U, // XSAVEOPT + 53299U, // XSAVEOPT64 + 54385U, // XSAVES + 53278U, // XSAVES64 + 2927U, // XSETBV + 2192U, // XSHA1 + 2245U, // XSHA256 + 2493U, // XSTORE + }; + + unsigned int opcode = MCInst_getOpcode(MI); + // printf("opcode = %u\n", opcode); + + // Emit the opcode for the instruction. + uint32_t Bits = 0; + Bits |= OpInfo0[opcode] << 0; +#ifndef CAPSTONE_DIET + SStream_concat0(O, AsmStrs+(Bits & 4095)-1); +#endif + + + // Fragment 0 encoded into 6 bits for 33 unique commands. + // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 12) & 63)); + switch ((uint32_t)((Bits >> 12) & 63)) { + default: // unreachable + case 0: + // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... + return; + break; + case 1: + // AAD8i8, AAM8i8, ADC16i16, ADC16rr_REV, ADC32i32, ADC32rr_REV, ADC64i32... + printOperand(MI, 0, O); + break; + case 2: + // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, AND16mi, AND16... + printi16mem(MI, 0, O); + break; + case 3: + // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32... + printOperand(MI, 1, O); + break; + case 4: + // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, AND32mi, AND32... + printi32mem(MI, 0, O); + break; + case 5: + // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,... + printi64mem(MI, 0, O); + break; + case 6: + // ADC8mi, ADC8mi8, ADC8mr, ADD8mi, ADD8mi8, ADD8mr, AND8mi, AND8mi8, AND... + printi8mem(MI, 0, O); + break; + case 7: + // CALL64pcrel32, CALLpcrel16, CALLpcrel32, JAE_1, JAE_2, JAE_4, JA_1, JA... + printPCRelImm(MI, 0, O); + return; + break; + case 8: + // CMPSB + printSrcIdx8(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx8(MI, 0, O); + return; + break; + case 9: + // CMPSL + printSrcIdx32(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx32(MI, 0, O); + return; + break; + case 10: + // CMPSQ + printSrcIdx64(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx64(MI, 0, O); + return; + break; + case 11: + // CMPSW + printSrcIdx16(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx16(MI, 0, O); + return; + break; + case 12: + // CMPXCHG16B + printi128mem(MI, 0, O); + return; + break; + case 13: + // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, LGD... + printopaquemem(MI, 0, O); + return; + break; + case 14: + // IN16ri, IN32ri, IN8ri, INT, OUT16ir, OUT32ir, OUT8ir + printU8Imm(MI, 0, O); + break; + case 15: + // INSB, MOVSB, SCASB, STOSB + printDstIdx8(MI, 0, O); + break; + case 16: + // INSL, MOVSL, SCASL, STOSL + printDstIdx32(MI, 0, O); + break; + case 17: + // INSW, MOVSW, SCASW, STOSW + printDstIdx16(MI, 0, O); + break; + case 18: + // LODSB, OUTSB + printSrcIdx8(MI, 0, O); + return; + break; + case 19: + // LODSL, OUTSL + printSrcIdx32(MI, 0, O); + return; + break; + case 20: + // LODSQ + printSrcIdx64(MI, 0, O); + return; + break; + case 21: + // LODSW, OUTSW + printSrcIdx16(MI, 0, O); + return; + break; + case 22: + // MOV16ao16, MOV16ao32, MOV16ao64, MOV16o16a, MOV16o32a, MOV16o64a + printMemOffs16(MI, 0, O); + break; + case 23: + // MOV32ao16, MOV32ao32, MOV32ao64, MOV32o16a, MOV32o32a, MOV32o64a + printMemOffs32(MI, 0, O); + break; + case 24: + // MOV64ao32, MOV64ao64, MOV64o32a, MOV64o64a + printMemOffs64(MI, 0, O); + break; + case 25: + // MOV8ao16, MOV8ao32, MOV8ao64, MOV8o16a, MOV8o32a, MOV8o64a + printMemOffs8(MI, 0, O); + break; + case 26: + // MOVSQ, SCASQ, STOSQ + printDstIdx64(MI, 0, O); + break; + case 27: + // XADD16rm, XCHG16rm + printi16mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 28: + // XADD16rr, XADD32rr, XADD64rr, XADD8rr + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 29: + // XADD32rm, XCHG32rm + printi32mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 30: + // XADD64rm, XCHG64rm + printi64mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 31: + // XADD8rm, XCHG8rm + printi8mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 32: + // XCHG16rr, XCHG32rr, XCHG64rr, XCHG8rr + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + } + + + // Fragment 1 encoded into 4 bits for 10 unique commands. + // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 18) & 15)); + switch ((uint32_t)((Bits >> 18) & 15)) { + default: // unreachable + case 0: + // AAD8i8, AAM8i8, ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i... + return; + break; + case 1: + // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16... + SStream_concat0(O, ", "); + break; + case 2: + // FARJMP16i, FARJMP32i + SStream_concat0(O, ":"); + printOperand(MI, 0, O); + return; + break; + case 3: + // INSB, INSL, INSW + SStream_concat0(O, ", dx"); + op_addReg(MI, X86_REG_DX); + return; + break; + case 4: + // MOV16o16a, MOV16o32a, MOV16o64a, OUT16ir, STOSW, XCHG16ar + SStream_concat0(O, ", ax"); + op_addReg(MI, X86_REG_AX); + return; + break; + case 5: + // MOV32o16a, MOV32o32a, MOV32o64a, OUT32ir, STOSL, XCHG32ar + SStream_concat0(O, ", eax"); + op_addReg(MI, X86_REG_EAX); + return; + break; + case 6: + // MOV64o32a, MOV64o64a, STOSQ, XCHG64ar + SStream_concat0(O, ", rax"); + op_addReg(MI, X86_REG_RAX); + return; + break; + case 7: + // MOV8o16a, MOV8o32a, MOV8o64a, OUT8ir, STOSB + SStream_concat0(O, ", al"); + op_addReg(MI, X86_REG_AL); + return; + break; + case 8: + // RCL16mCL, RCL16rCL, RCL32mCL, RCL32rCL, RCL64mCL, RCL64rCL, RCL8mCL, R... + SStream_concat0(O, ", cl"); + op_addReg(MI, X86_REG_CL); + return; + break; + case 9: + // RCL16r1, RCL32r1, RCL64r1, RCL8r1, RCR16m1, RCR16r1, RCR32m1, RCR32r1,... + SStream_concat0(O, ", 1"); + op_addImm(MI, 1); + return; + break; + } + + + // Fragment 2 encoded into 5 bits for 22 unique commands. + // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 22) & 31)); + switch ((uint32_t)((Bits >> 22) & 31)) { + default: // unreachable + case 0: + // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC... + printOperand(MI, 5, O); + break; + case 1: + // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A... + printOperand(MI, 2, O); + break; + case 2: + // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r... + printi16mem(MI, 2, O); + return; + break; + case 3: + // ADC32rm, ADCX32rm, ADD32rm, ADOX32rm, AND32rm, CMOVA32rm, CMOVAE32rm, ... + printi32mem(MI, 2, O); + return; + break; + case 4: + // ADC64rm, ADCX64rm, ADD64rm, ADOX64rm, AND64rm, CMOVA64rm, CMOVAE64rm, ... + printi64mem(MI, 2, O); + return; + break; + case 5: + // ADC8rm, ADD8rm, AND8rm, OR8rm, SBB8rm, SUB8rm, XOR8rm + printi8mem(MI, 2, O); + return; + break; + case 6: + // ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr, ARPL16rr, BEXTR32rr, BEXTR64rr... + printOperand(MI, 1, O); + break; + case 7: + // BEXTR32rm, BEXTRI32mi, BLCFILL32rm, BLCI32rm, BLCIC32rm, BLCMSK32rm, B... + printi32mem(MI, 1, O); + break; + case 8: + // BEXTR64rm, BEXTRI64mi, BLCFILL64rm, BLCI64rm, BLCIC64rm, BLCMSK64rm, B... + printi64mem(MI, 1, O); + break; + case 9: + // BSF16rm, BSR16rm, CMP16rm, IMUL16rmi, IMUL16rmi8, LAR16rm, LAR32rm, LA... + printi16mem(MI, 1, O); + break; + case 10: + // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX32rm8_NOREX... + printi8mem(MI, 1, O); + return; + break; + case 11: + // FARCALL16i, FARCALL32i, NOOP19rr + printOperand(MI, 0, O); + return; + break; + case 12: + // INVEPT32, INVEPT64, INVPCID32, INVPCID64, INVVPID32, INVVPID64 + printi128mem(MI, 1, O); + return; + break; + case 13: + // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm... + printopaquemem(MI, 1, O); + return; + break; + case 14: + // LEA16r, LEA32r, LEA64_32r, LEA64r + printanymem(MI, 1, O); + return; + break; + case 15: + // MOVDIR64B16, MOVDIR64B32, MOVDIR64B64 + printi512mem(MI, 1, O); + return; + break; + case 16: + // MOVSB + printSrcIdx8(MI, 1, O); + return; + break; + case 17: + // MOVSL + printSrcIdx32(MI, 1, O); + return; + break; + case 18: + // MOVSQ + printSrcIdx64(MI, 1, O); + return; + break; + case 19: + // MOVSW + printSrcIdx16(MI, 1, O); + return; + break; + case 20: + // RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi, ... + printU8Imm(MI, 5, O); + return; + break; + case 21: + // RCL16ri, RCL32ri, RCL64ri, RCL8ri, RCR16ri, RCR32ri, RCR64ri, RCR8ri, ... + printU8Imm(MI, 2, O); + return; + break; + } + + + // Fragment 3 encoded into 2 bits for 3 unique commands. + // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 27) & 3)); + switch ((uint32_t)((Bits >> 27) & 3)) { + default: // unreachable + case 0: + // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, A... + return; + break; + case 1: + // ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr, BEXTR32rm, BEXTR32rr, BEXTR64r... + SStream_concat0(O, ", "); + break; + case 2: + // SHLD16mrCL, SHLD16rrCL, SHLD32mrCL, SHLD32rrCL, SHLD64mrCL, SHLD64rrCL... + SStream_concat0(O, ", cl"); + op_addReg(MI, X86_REG_CL); + return; + break; + } + + + // Fragment 4 encoded into 3 bits for 7 unique commands. + // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 29) & 7)); + switch ((uint32_t)((Bits >> 29) & 7)) { + default: // unreachable + case 0: + // ANDN32rm, MULX32rm, PDEP32rm, PEXT32rm + printi32mem(MI, 2, O); + return; + break; + case 1: + // ANDN32rr, ANDN64rr, BEXTR32rr, BEXTR64rr, BEXTRI32ri, BEXTRI64ri, BZHI... + printOperand(MI, 2, O); + return; + break; + case 2: + // ANDN64rm, MULX64rm, PDEP64rm, PEXT64rm + printi64mem(MI, 2, O); + return; + break; + case 3: + // BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZHI32rm, BZHI64rm, IMUL... + printOperand(MI, 6, O); + return; + break; + case 4: + // RORX32mi, RORX64mi, SHLD16mri8, SHLD32mri8, SHLD64mri8, SHRD16mri8, SH... + printU8Imm(MI, 6, O); + return; + break; + case 5: + // RORX32ri, RORX64ri + printU8Imm(MI, 2, O); + return; + break; + case 6: + // SHLD16rri8, SHLD32rri8, SHLD64rri8, SHRD16rri8, SHRD32rri8, SHRD64rri8 + printU8Imm(MI, 3, O); + return; + break; + } + +} + + + diff --git a/thirdparty/capstone/arch/X86/X86GenAsmWriter_reduce.inc b/thirdparty/capstone/arch/X86/X86GenAsmWriter_reduce.inc new file mode 100644 index 0000000..dc5c042 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenAsmWriter_reduce.inc @@ -0,0 +1,2855 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) +{ +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'x', 's', 'a', 'v', 'e', 'c', '6', '4', 9, 0, + /* 10 */ 'x', 's', 'a', 'v', 'e', '6', '4', 9, 0, + /* 19 */ 'x', 'r', 's', 't', 'o', 'r', '6', '4', 9, 0, + /* 29 */ 'x', 's', 'a', 'v', 'e', 's', '6', '4', 9, 0, + /* 39 */ 'x', 'r', 's', 't', 'o', 'r', 's', '6', '4', 9, 0, + /* 50 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', '6', '4', 9, 0, + /* 62 */ 'j', 'a', 9, 0, + /* 66 */ 's', 'e', 't', 'a', 9, 0, + /* 72 */ 'm', 'o', 'v', 'd', 'i', 'r', '6', '4', 'b', 9, 0, + /* 83 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0, + /* 95 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '8', 'b', 9, 0, + /* 106 */ 's', 'b', 'b', 'b', 9, 0, + /* 112 */ 's', 'u', 'b', 'b', 9, 0, + /* 118 */ 'a', 'd', 'c', 'b', 9, 0, + /* 124 */ 'd', 'e', 'c', 'b', 9, 0, + /* 130 */ 'i', 'n', 'c', 'b', 9, 0, + /* 136 */ 'l', 'l', 'w', 'p', 'c', 'b', 9, 0, + /* 144 */ 's', 'l', 'w', 'p', 'c', 'b', 9, 0, + /* 152 */ 'x', 'a', 'd', 'd', 'b', 9, 0, + /* 159 */ 'a', 'n', 'd', 'b', 9, 0, + /* 165 */ 'n', 'e', 'g', 'b', 9, 0, + /* 171 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'b', 9, 0, + /* 181 */ 'j', 'b', 9, 0, + /* 185 */ 's', 'a', 'l', 'b', 9, 0, + /* 191 */ 'r', 'c', 'l', 'b', 9, 0, + /* 197 */ 's', 'h', 'l', 'b', 9, 0, + /* 203 */ 'r', 'o', 'l', 'b', 9, 0, + /* 209 */ 'i', 'm', 'u', 'l', 'b', 9, 0, + /* 216 */ 'i', 'n', 'b', 9, 0, + /* 221 */ 'c', 'm', 'p', 'b', 9, 0, + /* 227 */ 's', 'a', 'r', 'b', 9, 0, + /* 233 */ 'r', 'c', 'r', 'b', 9, 0, + /* 239 */ 's', 'h', 'r', 'b', 9, 0, + /* 245 */ 'r', 'o', 'r', 'b', 9, 0, + /* 251 */ 'x', 'o', 'r', 'b', 9, 0, + /* 257 */ 's', 'c', 'a', 's', 'b', 9, 0, + /* 264 */ 'm', 'o', 'v', 'a', 'b', 's', 'b', 9, 0, + /* 273 */ 'l', 'o', 'd', 's', 'b', 9, 0, + /* 280 */ 'c', 'm', 'p', 's', 'b', 9, 0, + /* 287 */ 'o', 'u', 't', 's', 'b', 9, 0, + /* 294 */ 'm', 'o', 'v', 's', 'b', 9, 0, + /* 301 */ 's', 'e', 't', 'b', 9, 0, + /* 307 */ 'n', 'o', 't', 'b', 9, 0, + /* 313 */ 't', 'e', 's', 't', 'b', 9, 0, + /* 320 */ 'i', 'd', 'i', 'v', 'b', 9, 0, + /* 327 */ 'm', 'o', 'v', 'b', 9, 0, + /* 333 */ 'c', 'l', 'w', 'b', 9, 0, + /* 339 */ 'x', 's', 'a', 'v', 'e', 'c', 9, 0, + /* 347 */ 'a', 'a', 'd', 9, 0, + /* 352 */ 'i', 'n', 'v', 'p', 'c', 'i', 'd', 9, 0, + /* 361 */ 'r', 'd', 'p', 'i', 'd', 9, 0, + /* 368 */ 'i', 'n', 'v', 'v', 'p', 'i', 'd', 9, 0, + /* 377 */ 'v', 'm', 'p', 't', 'r', 'l', 'd', 9, 0, + /* 386 */ 'b', 'o', 'u', 'n', 'd', 9, 0, + /* 393 */ 'i', 'n', 'c', 's', 's', 'p', 'd', 9, 0, + /* 402 */ 'r', 'd', 's', 's', 'p', 'd', 9, 0, + /* 410 */ 'w', 'r', 's', 's', 'd', 9, 0, + /* 417 */ 'w', 'r', 'u', 's', 's', 'd', 9, 0, + /* 425 */ 'j', 'a', 'e', 9, 0, + /* 430 */ 's', 'e', 't', 'a', 'e', 9, 0, + /* 437 */ 'j', 'b', 'e', 9, 0, + /* 442 */ 's', 'e', 't', 'b', 'e', 9, 0, + /* 449 */ 'j', 'g', 'e', 9, 0, + /* 454 */ 's', 'e', 't', 'g', 'e', 9, 0, + /* 461 */ 'j', 'e', 9, 0, + /* 465 */ 'j', 'l', 'e', 9, 0, + /* 470 */ 's', 'e', 't', 'l', 'e', 9, 0, + /* 477 */ 'j', 'n', 'e', 9, 0, + /* 482 */ 'l', 'o', 'o', 'p', 'n', 'e', 9, 0, + /* 490 */ 's', 'e', 't', 'n', 'e', 9, 0, + /* 497 */ 'l', 'o', 'o', 'p', 'e', 9, 0, + /* 504 */ 't', 'p', 'a', 'u', 's', 'e', 9, 0, + /* 512 */ 's', 'e', 't', 'e', 9, 0, + /* 518 */ 'c', 'l', 'd', 'e', 'm', 'o', 't', 'e', 9, 0, + /* 528 */ 'x', 's', 'a', 'v', 'e', 9, 0, + /* 535 */ 'j', 'g', 9, 0, + /* 539 */ 'i', 'n', 'v', 'l', 'p', 'g', 9, 0, + /* 547 */ 's', 'e', 't', 'g', 9, 0, + /* 553 */ 'm', 'o', 'v', 'd', 'i', 'r', 'i', 9, 0, + /* 562 */ 'l', 'e', 'a', 'l', 9, 0, + /* 568 */ 'c', 'm', 'o', 'v', 'a', 'l', 9, 0, + /* 576 */ 'l', 'w', 'p', 'v', 'a', 'l', 9, 0, + /* 584 */ 's', 'b', 'b', 'l', 9, 0, + /* 590 */ 'm', 'o', 'v', 's', 'b', 'l', 9, 0, + /* 598 */ 's', 'u', 'b', 'l', 9, 0, + /* 604 */ 'c', 'm', 'o', 'v', 'b', 'l', 9, 0, + /* 612 */ 'm', 'o', 'v', 'z', 'b', 'l', 9, 0, + /* 620 */ 'a', 'd', 'c', 'l', 9, 0, + /* 626 */ 'd', 'e', 'c', 'l', 9, 0, + /* 632 */ 'b', 'l', 'c', 'i', 'c', 'l', 9, 0, + /* 640 */ 'b', 'l', 's', 'i', 'c', 'l', 9, 0, + /* 648 */ 't', '1', 'm', 's', 'k', 'c', 'l', 9, 0, + /* 657 */ 'i', 'n', 'c', 'l', 9, 0, + /* 663 */ 'b', 't', 'c', 'l', 9, 0, + /* 669 */ 'v', 'm', 'r', 'e', 'a', 'd', 'l', 9, 0, + /* 678 */ 'x', 'a', 'd', 'd', 'l', 9, 0, + /* 685 */ 'r', 'd', 's', 'e', 'e', 'd', 'l', 9, 0, + /* 694 */ 's', 'h', 'l', 'd', 'l', 9, 0, + /* 701 */ 'r', 'd', 'r', 'a', 'n', 'd', 'l', 9, 0, + /* 710 */ 's', 'h', 'r', 'd', 'l', 9, 0, + /* 717 */ 'c', 'm', 'o', 'v', 'a', 'e', 'l', 9, 0, + /* 726 */ 'c', 'm', 'o', 'v', 'b', 'e', 'l', 9, 0, + /* 735 */ 'c', 'm', 'o', 'v', 'g', 'e', 'l', 9, 0, + /* 744 */ 'c', 'm', 'o', 'v', 'l', 'e', 'l', 9, 0, + /* 753 */ 'c', 'm', 'o', 'v', 'n', 'e', 'l', 9, 0, + /* 762 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 'l', 9, 0, + /* 773 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 'l', 9, 0, + /* 784 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 'l', 9, 0, + /* 795 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 'l', 9, 0, + /* 806 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 'l', 9, 0, + /* 816 */ 'p', 't', 'w', 'r', 'i', 't', 'e', 'l', 9, 0, + /* 826 */ 'c', 'm', 'o', 'v', 'e', 'l', 9, 0, + /* 834 */ 'b', 's', 'f', 'l', 9, 0, + /* 840 */ 'n', 'e', 'g', 'l', 9, 0, + /* 846 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'l', 9, 0, + /* 856 */ 'c', 'm', 'o', 'v', 'g', 'l', 9, 0, + /* 864 */ 'p', 'u', 's', 'h', 'l', 9, 0, + /* 871 */ 'b', 'l', 'c', 'i', 'l', 9, 0, + /* 878 */ 'b', 'z', 'h', 'i', 'l', 9, 0, + /* 885 */ 'b', 'l', 's', 'i', 'l', 9, 0, + /* 892 */ 'j', 'l', 9, 0, + /* 896 */ 'b', 'l', 'c', 'm', 's', 'k', 'l', 9, 0, + /* 905 */ 'b', 'l', 's', 'm', 's', 'k', 'l', 9, 0, + /* 914 */ 't', 'z', 'm', 's', 'k', 'l', 9, 0, + /* 922 */ 's', 'a', 'l', 'l', 9, 0, + /* 928 */ 'r', 'c', 'l', 'l', 9, 0, + /* 934 */ 's', 'h', 'l', 'l', 9, 0, + /* 940 */ 'l', 'c', 'a', 'l', 'l', 'l', 9, 0, + /* 948 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 'l', 9, 0, + /* 958 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 'l', 9, 0, + /* 968 */ 'r', 'o', 'l', 'l', 9, 0, + /* 974 */ 'l', 's', 'l', 'l', 9, 0, + /* 980 */ 'i', 'm', 'u', 'l', 'l', 9, 0, + /* 987 */ 'c', 'm', 'o', 'v', 'l', 'l', 9, 0, + /* 995 */ 'a', 'n', 'd', 'n', 'l', 9, 0, + /* 1002 */ 'i', 'n', 'l', 9, 0, + /* 1007 */ 'c', 'm', 'o', 'v', 'n', 'o', 'l', 9, 0, + /* 1016 */ 'c', 'm', 'o', 'v', 'o', 'l', 9, 0, + /* 1024 */ 'b', 's', 'w', 'a', 'p', 'l', 9, 0, + /* 1032 */ 'p', 'd', 'e', 'p', 'l', 9, 0, + /* 1039 */ 'c', 'm', 'p', 'l', 9, 0, + /* 1045 */ 'l', 'j', 'm', 'p', 'l', 9, 0, + /* 1052 */ 'c', 'm', 'o', 'v', 'n', 'p', 'l', 9, 0, + /* 1061 */ 'n', 'o', 'p', 'l', 9, 0, + /* 1067 */ 'p', 'o', 'p', 'l', 9, 0, + /* 1073 */ 'a', 'r', 'p', 'l', 9, 0, + /* 1079 */ 'c', 'm', 'o', 'v', 'p', 'l', 9, 0, + /* 1087 */ 'l', 'a', 'r', 'l', 9, 0, + /* 1093 */ 's', 'a', 'r', 'l', 9, 0, + /* 1099 */ 'r', 'c', 'r', 'l', 9, 0, + /* 1105 */ 's', 'h', 'r', 'l', 9, 0, + /* 1111 */ 'r', 'o', 'r', 'l', 9, 0, + /* 1117 */ 'x', 'o', 'r', 'l', 9, 0, + /* 1123 */ 'b', 's', 'r', 'l', 9, 0, + /* 1129 */ 'b', 'l', 's', 'r', 'l', 9, 0, + /* 1136 */ 'b', 't', 'r', 'l', 9, 0, + /* 1142 */ 's', 't', 'r', 'l', 9, 0, + /* 1148 */ 'b', 'e', 'x', 't', 'r', 'l', 9, 0, + /* 1156 */ 's', 'c', 'a', 's', 'l', 9, 0, + /* 1163 */ 'm', 'o', 'v', 'a', 'b', 's', 'l', 9, 0, + /* 1172 */ 'b', 'l', 'c', 's', 'l', 9, 0, + /* 1179 */ 'l', 'd', 's', 'l', 9, 0, + /* 1185 */ 'l', 'o', 'd', 's', 'l', 9, 0, + /* 1192 */ 'l', 'e', 's', 'l', 9, 0, + /* 1198 */ 'l', 'f', 's', 'l', 9, 0, + /* 1204 */ 'l', 'g', 's', 'l', 9, 0, + /* 1210 */ 'c', 'm', 'o', 'v', 'n', 's', 'l', 9, 0, + /* 1219 */ 'c', 'm', 'p', 's', 'l', 9, 0, + /* 1226 */ 'l', 's', 's', 'l', 9, 0, + /* 1232 */ 'b', 't', 's', 'l', 9, 0, + /* 1238 */ 'o', 'u', 't', 's', 'l', 9, 0, + /* 1245 */ 'c', 'm', 'o', 'v', 's', 'l', 9, 0, + /* 1253 */ 'b', 't', 'l', 9, 0, + /* 1258 */ 'l', 'g', 'd', 't', 'l', 9, 0, + /* 1265 */ 's', 'g', 'd', 't', 'l', 9, 0, + /* 1272 */ 'l', 'i', 'd', 't', 'l', 9, 0, + /* 1279 */ 's', 'i', 'd', 't', 'l', 9, 0, + /* 1286 */ 's', 'l', 'd', 't', 'l', 9, 0, + /* 1293 */ 'l', 'r', 'e', 't', 'l', 9, 0, + /* 1300 */ 's', 'e', 't', 'l', 9, 0, + /* 1306 */ 'l', 'z', 'c', 'n', 't', 'l', 9, 0, + /* 1314 */ 't', 'z', 'c', 'n', 't', 'l', 9, 0, + /* 1322 */ 'n', 'o', 't', 'l', 9, 0, + /* 1328 */ 't', 'e', 's', 't', 'l', 9, 0, + /* 1335 */ 'p', 'e', 'x', 't', 'l', 9, 0, + /* 1342 */ 'i', 'd', 'i', 'v', 'l', 9, 0, + /* 1349 */ 'm', 'o', 'v', 'l', 9, 0, + /* 1355 */ 's', 'm', 's', 'w', 'l', 9, 0, + /* 1362 */ 'm', 'o', 'v', 's', 'w', 'l', 9, 0, + /* 1370 */ 'm', 'o', 'v', 'z', 'w', 'l', 9, 0, + /* 1378 */ 'a', 'd', 'c', 'x', 'l', 9, 0, + /* 1385 */ 's', 'h', 'l', 'x', 'l', 9, 0, + /* 1392 */ 'm', 'u', 'l', 'x', 'l', 9, 0, + /* 1399 */ 'a', 'd', 'o', 'x', 'l', 9, 0, + /* 1406 */ 's', 'a', 'r', 'x', 'l', 9, 0, + /* 1413 */ 's', 'h', 'r', 'x', 'l', 9, 0, + /* 1420 */ 'r', 'o', 'r', 'x', 'l', 9, 0, + /* 1427 */ 'a', 'a', 'm', 9, 0, + /* 1432 */ 'v', 'm', 'x', 'o', 'n', 9, 0, + /* 1439 */ 'j', 'o', 9, 0, + /* 1443 */ 'j', 'n', 'o', 9, 0, + /* 1448 */ 's', 'e', 't', 'n', 'o', 9, 0, + /* 1455 */ 's', 'e', 't', 'o', 9, 0, + /* 1461 */ 'j', 'p', 9, 0, + /* 1465 */ 'j', 'm', 'p', 9, 0, + /* 1470 */ 'j', 'n', 'p', 9, 0, + /* 1475 */ 's', 'e', 't', 'n', 'p', 9, 0, + /* 1482 */ 'n', 'o', 'p', 9, 0, + /* 1487 */ 'l', 'o', 'o', 'p', 9, 0, + /* 1493 */ 'r', 's', 't', 'o', 'r', 's', 's', 'p', 9, 0, + /* 1503 */ 's', 'e', 't', 'p', 9, 0, + /* 1509 */ 'l', 'e', 'a', 'q', 9, 0, + /* 1515 */ 'c', 'm', 'o', 'v', 'a', 'q', 9, 0, + /* 1523 */ 's', 'b', 'b', 'q', 9, 0, + /* 1529 */ 'm', 'o', 'v', 's', 'b', 'q', 9, 0, + /* 1537 */ 's', 'u', 'b', 'q', 9, 0, + /* 1543 */ 'c', 'm', 'o', 'v', 'b', 'q', 9, 0, + /* 1551 */ 'm', 'o', 'v', 'z', 'b', 'q', 9, 0, + /* 1559 */ 'a', 'd', 'c', 'q', 9, 0, + /* 1565 */ 'd', 'e', 'c', 'q', 9, 0, + /* 1571 */ 'b', 'l', 'c', 'i', 'c', 'q', 9, 0, + /* 1579 */ 'b', 'l', 's', 'i', 'c', 'q', 9, 0, + /* 1587 */ 't', '1', 'm', 's', 'k', 'c', 'q', 9, 0, + /* 1596 */ 'i', 'n', 'c', 'q', 9, 0, + /* 1602 */ 'b', 't', 'c', 'q', 9, 0, + /* 1608 */ 'v', 'm', 'r', 'e', 'a', 'd', 'q', 9, 0, + /* 1617 */ 'x', 'a', 'd', 'd', 'q', 9, 0, + /* 1624 */ 'r', 'd', 's', 'e', 'e', 'd', 'q', 9, 0, + /* 1633 */ 's', 'h', 'l', 'd', 'q', 9, 0, + /* 1640 */ 'r', 'd', 'r', 'a', 'n', 'd', 'q', 9, 0, + /* 1649 */ 's', 'h', 'r', 'd', 'q', 9, 0, + /* 1656 */ 'c', 'm', 'o', 'v', 'a', 'e', 'q', 9, 0, + /* 1665 */ 'c', 'm', 'o', 'v', 'b', 'e', 'q', 9, 0, + /* 1674 */ 'c', 'm', 'o', 'v', 'g', 'e', 'q', 9, 0, + /* 1683 */ 'c', 'm', 'o', 'v', 'l', 'e', 'q', 9, 0, + /* 1692 */ 'c', 'm', 'o', 'v', 'n', 'e', 'q', 9, 0, + /* 1701 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 'q', 9, 0, + /* 1712 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 'q', 9, 0, + /* 1723 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 'q', 9, 0, + /* 1734 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 'q', 9, 0, + /* 1745 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 'q', 9, 0, + /* 1755 */ 'p', 't', 'w', 'r', 'i', 't', 'e', 'q', 9, 0, + /* 1765 */ 'c', 'm', 'o', 'v', 'e', 'q', 9, 0, + /* 1773 */ 'b', 's', 'f', 'q', 9, 0, + /* 1779 */ 'n', 'e', 'g', 'q', 9, 0, + /* 1785 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'q', 9, 0, + /* 1795 */ 'c', 'm', 'o', 'v', 'g', 'q', 9, 0, + /* 1803 */ 'p', 'u', 's', 'h', 'q', 9, 0, + /* 1810 */ 'b', 'l', 'c', 'i', 'q', 9, 0, + /* 1817 */ 'b', 'z', 'h', 'i', 'q', 9, 0, + /* 1824 */ 'b', 'l', 's', 'i', 'q', 9, 0, + /* 1831 */ 'b', 'l', 'c', 'm', 's', 'k', 'q', 9, 0, + /* 1840 */ 'b', 'l', 's', 'm', 's', 'k', 'q', 9, 0, + /* 1849 */ 't', 'z', 'm', 's', 'k', 'q', 9, 0, + /* 1857 */ 's', 'a', 'l', 'q', 9, 0, + /* 1863 */ 'r', 'c', 'l', 'q', 9, 0, + /* 1869 */ 's', 'h', 'l', 'q', 9, 0, + /* 1875 */ 'c', 'a', 'l', 'l', 'q', 9, 0, + /* 1882 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 'q', 9, 0, + /* 1892 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 'q', 9, 0, + /* 1902 */ 'r', 'o', 'l', 'q', 9, 0, + /* 1908 */ 'l', 's', 'l', 'q', 9, 0, + /* 1914 */ 'm', 'o', 'v', 's', 'l', 'q', 9, 0, + /* 1922 */ 'i', 'm', 'u', 'l', 'q', 9, 0, + /* 1929 */ 'c', 'm', 'o', 'v', 'l', 'q', 9, 0, + /* 1937 */ 'a', 'n', 'd', 'n', 'q', 9, 0, + /* 1944 */ 'c', 'm', 'o', 'v', 'n', 'o', 'q', 9, 0, + /* 1953 */ 'c', 'm', 'o', 'v', 'o', 'q', 9, 0, + /* 1961 */ 'b', 's', 'w', 'a', 'p', 'q', 9, 0, + /* 1969 */ 'p', 'd', 'e', 'p', 'q', 9, 0, + /* 1976 */ 'c', 'm', 'p', 'q', 9, 0, + /* 1982 */ 'c', 'm', 'o', 'v', 'n', 'p', 'q', 9, 0, + /* 1991 */ 'n', 'o', 'p', 'q', 9, 0, + /* 1997 */ 'p', 'o', 'p', 'q', 9, 0, + /* 2003 */ 'i', 'n', 'c', 's', 's', 'p', 'q', 9, 0, + /* 2012 */ 'r', 'd', 's', 's', 'p', 'q', 9, 0, + /* 2020 */ 'c', 'm', 'o', 'v', 'p', 'q', 9, 0, + /* 2028 */ 'l', 'a', 'r', 'q', 9, 0, + /* 2034 */ 's', 'a', 'r', 'q', 9, 0, + /* 2040 */ 'r', 'c', 'r', 'q', 9, 0, + /* 2046 */ 's', 'h', 'r', 'q', 9, 0, + /* 2052 */ 'r', 'o', 'r', 'q', 9, 0, + /* 2058 */ 'x', 'o', 'r', 'q', 9, 0, + /* 2064 */ 'b', 's', 'r', 'q', 9, 0, + /* 2070 */ 'b', 'l', 's', 'r', 'q', 9, 0, + /* 2077 */ 'b', 't', 'r', 'q', 9, 0, + /* 2083 */ 's', 't', 'r', 'q', 9, 0, + /* 2089 */ 'b', 'e', 'x', 't', 'r', 'q', 9, 0, + /* 2097 */ 's', 'c', 'a', 's', 'q', 9, 0, + /* 2104 */ 'm', 'o', 'v', 'a', 'b', 's', 'q', 9, 0, + /* 2113 */ 'b', 'l', 'c', 's', 'q', 9, 0, + /* 2120 */ 'l', 'o', 'd', 's', 'q', 9, 0, + /* 2127 */ 'l', 'f', 's', 'q', 9, 0, + /* 2133 */ 'c', 'm', 'o', 'v', 'n', 's', 'q', 9, 0, + /* 2142 */ 'c', 'm', 'p', 's', 'q', 9, 0, + /* 2149 */ 'l', 's', 's', 'q', 9, 0, + /* 2155 */ 'w', 'r', 's', 's', 'q', 9, 0, + /* 2162 */ 'w', 'r', 'u', 's', 's', 'q', 9, 0, + /* 2170 */ 'b', 't', 's', 'q', 9, 0, + /* 2176 */ 'c', 'm', 'o', 'v', 's', 'q', 9, 0, + /* 2184 */ 'b', 't', 'q', 9, 0, + /* 2189 */ 'l', 'g', 'd', 't', 'q', 9, 0, + /* 2196 */ 's', 'g', 'd', 't', 'q', 9, 0, + /* 2203 */ 'l', 'i', 'd', 't', 'q', 9, 0, + /* 2210 */ 's', 'i', 'd', 't', 'q', 9, 0, + /* 2217 */ 's', 'l', 'd', 't', 'q', 9, 0, + /* 2224 */ 'l', 'r', 'e', 't', 'q', 9, 0, + /* 2231 */ 'l', 'z', 'c', 'n', 't', 'q', 9, 0, + /* 2239 */ 't', 'z', 'c', 'n', 't', 'q', 9, 0, + /* 2247 */ 'n', 'o', 't', 'q', 9, 0, + /* 2253 */ 't', 'e', 's', 't', 'q', 9, 0, + /* 2260 */ 'p', 'e', 'x', 't', 'q', 9, 0, + /* 2267 */ 'i', 'd', 'i', 'v', 'q', 9, 0, + /* 2274 */ 'm', 'o', 'v', 'q', 9, 0, + /* 2280 */ 's', 'm', 's', 'w', 'q', 9, 0, + /* 2287 */ 'm', 'o', 'v', 's', 'w', 'q', 9, 0, + /* 2295 */ 'm', 'o', 'v', 'z', 'w', 'q', 9, 0, + /* 2303 */ 'a', 'd', 'c', 'x', 'q', 9, 0, + /* 2310 */ 's', 'h', 'l', 'x', 'q', 9, 0, + /* 2317 */ 'm', 'u', 'l', 'x', 'q', 9, 0, + /* 2324 */ 'a', 'd', 'o', 'x', 'q', 9, 0, + /* 2331 */ 's', 'a', 'r', 'x', 'q', 9, 0, + /* 2338 */ 's', 'h', 'r', 'x', 'q', 9, 0, + /* 2345 */ 'r', 'o', 'r', 'x', 'q', 9, 0, + /* 2352 */ 'v', 'm', 'c', 'l', 'e', 'a', 'r', 9, 0, + /* 2361 */ 'e', 'n', 't', 'e', 'r', 9, 0, + /* 2368 */ 'u', 'm', 'o', 'n', 'i', 't', 'o', 'r', 9, 0, + /* 2378 */ 'x', 'r', 's', 't', 'o', 'r', 9, 0, + /* 2386 */ 'v', 'e', 'r', 'r', 9, 0, + /* 2392 */ 'x', 's', 'a', 'v', 'e', 's', 9, 0, + /* 2400 */ 'l', 'g', 's', 9, 0, + /* 2405 */ 'j', 's', 9, 0, + /* 2409 */ 'l', 'w', 'p', 'i', 'n', 's', 9, 0, + /* 2417 */ 'j', 'n', 's', 9, 0, + /* 2422 */ 's', 'e', 't', 'n', 's', 9, 0, + /* 2429 */ 'x', 'r', 's', 't', 'o', 'r', 's', 9, 0, + /* 2438 */ 's', 'e', 't', 's', 9, 0, + /* 2444 */ 'u', 'm', 'w', 'a', 'i', 't', 9, 0, + /* 2452 */ 'i', 'n', 't', 9, 0, + /* 2457 */ 'i', 'n', 'v', 'e', 'p', 't', 9, 0, + /* 2465 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 9, 0, + /* 2475 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 'o', 'p', 't', 9, 0, + /* 2487 */ 'v', 'm', 'p', 't', 'r', 's', 't', 9, 0, + /* 2496 */ 'l', 'e', 'a', 'w', 9, 0, + /* 2502 */ 'c', 'm', 'o', 'v', 'a', 'w', 9, 0, + /* 2510 */ 's', 'b', 'b', 'w', 9, 0, + /* 2516 */ 'm', 'o', 'v', 's', 'b', 'w', 9, 0, + /* 2524 */ 's', 'u', 'b', 'w', 9, 0, + /* 2530 */ 'c', 'm', 'o', 'v', 'b', 'w', 9, 0, + /* 2538 */ 'm', 'o', 'v', 'z', 'b', 'w', 9, 0, + /* 2546 */ 'a', 'd', 'c', 'w', 9, 0, + /* 2552 */ 'd', 'e', 'c', 'w', 9, 0, + /* 2558 */ 'i', 'n', 'c', 'w', 9, 0, + /* 2564 */ 'b', 't', 'c', 'w', 9, 0, + /* 2570 */ 'x', 'a', 'd', 'd', 'w', 9, 0, + /* 2577 */ 'r', 'd', 's', 'e', 'e', 'd', 'w', 9, 0, + /* 2586 */ 's', 'h', 'l', 'd', 'w', 9, 0, + /* 2593 */ 'r', 'd', 'r', 'a', 'n', 'd', 'w', 9, 0, + /* 2602 */ 's', 'h', 'r', 'd', 'w', 9, 0, + /* 2609 */ 'c', 'm', 'o', 'v', 'a', 'e', 'w', 9, 0, + /* 2618 */ 'c', 'm', 'o', 'v', 'b', 'e', 'w', 9, 0, + /* 2627 */ 'c', 'm', 'o', 'v', 'g', 'e', 'w', 9, 0, + /* 2636 */ 'c', 'm', 'o', 'v', 'l', 'e', 'w', 9, 0, + /* 2645 */ 'c', 'm', 'o', 'v', 'n', 'e', 'w', 9, 0, + /* 2654 */ 'c', 'm', 'o', 'v', 'e', 'w', 9, 0, + /* 2662 */ 'b', 's', 'f', 'w', 9, 0, + /* 2668 */ 'n', 'e', 'g', 'w', 9, 0, + /* 2674 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'w', 9, 0, + /* 2684 */ 'c', 'm', 'o', 'v', 'g', 'w', 9, 0, + /* 2692 */ 'p', 'u', 's', 'h', 'w', 9, 0, + /* 2699 */ 's', 'a', 'l', 'w', 9, 0, + /* 2705 */ 'r', 'c', 'l', 'w', 9, 0, + /* 2711 */ 's', 'h', 'l', 'w', 9, 0, + /* 2717 */ 'l', 'c', 'a', 'l', 'l', 'w', 9, 0, + /* 2725 */ 'r', 'o', 'l', 'w', 9, 0, + /* 2731 */ 'l', 's', 'l', 'w', 9, 0, + /* 2737 */ 'i', 'm', 'u', 'l', 'w', 9, 0, + /* 2744 */ 'c', 'm', 'o', 'v', 'l', 'w', 9, 0, + /* 2752 */ 'i', 'n', 'w', 9, 0, + /* 2757 */ 'c', 'm', 'o', 'v', 'n', 'o', 'w', 9, 0, + /* 2766 */ 'c', 'm', 'o', 'v', 'o', 'w', 9, 0, + /* 2774 */ 'b', 's', 'w', 'a', 'p', 'w', 9, 0, + /* 2782 */ 'c', 'm', 'p', 'w', 9, 0, + /* 2788 */ 'l', 'j', 'm', 'p', 'w', 9, 0, + /* 2795 */ 'c', 'm', 'o', 'v', 'n', 'p', 'w', 9, 0, + /* 2804 */ 'n', 'o', 'p', 'w', 9, 0, + /* 2810 */ 'p', 'o', 'p', 'w', 9, 0, + /* 2816 */ 'c', 'm', 'o', 'v', 'p', 'w', 9, 0, + /* 2824 */ 'l', 'a', 'r', 'w', 9, 0, + /* 2830 */ 's', 'a', 'r', 'w', 9, 0, + /* 2836 */ 'r', 'c', 'r', 'w', 9, 0, + /* 2842 */ 'v', 'e', 'r', 'w', 9, 0, + /* 2848 */ 's', 'h', 'r', 'w', 9, 0, + /* 2854 */ 'r', 'o', 'r', 'w', 9, 0, + /* 2860 */ 'x', 'o', 'r', 'w', 9, 0, + /* 2866 */ 'b', 's', 'r', 'w', 9, 0, + /* 2872 */ 'b', 't', 'r', 'w', 9, 0, + /* 2878 */ 'l', 't', 'r', 'w', 9, 0, + /* 2884 */ 's', 't', 'r', 'w', 9, 0, + /* 2890 */ 's', 'c', 'a', 's', 'w', 9, 0, + /* 2897 */ 'm', 'o', 'v', 'a', 'b', 's', 'w', 9, 0, + /* 2906 */ 'l', 'd', 's', 'w', 9, 0, + /* 2912 */ 'l', 'o', 'd', 's', 'w', 9, 0, + /* 2919 */ 'l', 'e', 's', 'w', 9, 0, + /* 2925 */ 'l', 'f', 's', 'w', 9, 0, + /* 2931 */ 'l', 'g', 's', 'w', 9, 0, + /* 2937 */ 'c', 'm', 'o', 'v', 'n', 's', 'w', 9, 0, + /* 2946 */ 'c', 'm', 'p', 's', 'w', 9, 0, + /* 2953 */ 'l', 's', 's', 'w', 9, 0, + /* 2959 */ 'b', 't', 's', 'w', 9, 0, + /* 2965 */ 'o', 'u', 't', 's', 'w', 9, 0, + /* 2972 */ 'c', 'm', 'o', 'v', 's', 'w', 9, 0, + /* 2980 */ 'b', 't', 'w', 9, 0, + /* 2985 */ 'l', 'g', 'd', 't', 'w', 9, 0, + /* 2992 */ 's', 'g', 'd', 't', 'w', 9, 0, + /* 2999 */ 'l', 'i', 'd', 't', 'w', 9, 0, + /* 3006 */ 's', 'i', 'd', 't', 'w', 9, 0, + /* 3013 */ 'l', 'l', 'd', 't', 'w', 9, 0, + /* 3020 */ 's', 'l', 'd', 't', 'w', 9, 0, + /* 3027 */ 'l', 'r', 'e', 't', 'w', 9, 0, + /* 3034 */ 'l', 'z', 'c', 'n', 't', 'w', 9, 0, + /* 3042 */ 't', 'z', 'c', 'n', 't', 'w', 9, 0, + /* 3050 */ 'n', 'o', 't', 'w', 9, 0, + /* 3056 */ 't', 'e', 's', 't', 'w', 9, 0, + /* 3063 */ 'i', 'd', 'i', 'v', 'w', 9, 0, + /* 3070 */ 'm', 'o', 'v', 'w', 9, 0, + /* 3076 */ 'l', 'm', 's', 'w', 'w', 9, 0, + /* 3083 */ 's', 'm', 's', 'w', 'w', 9, 0, + /* 3090 */ 'm', 'o', 'v', 's', 'w', 'w', 9, 0, + /* 3098 */ 'm', 'o', 'v', 'z', 'w', 'w', 9, 0, + /* 3106 */ 'c', 'l', 'r', 's', 's', 'b', 's', 'y', 9, 0, + /* 3116 */ 'j', 'e', 'c', 'x', 'z', 9, 0, + /* 3123 */ 'j', 'c', 'x', 'z', 9, 0, + /* 3129 */ 'j', 'r', 'c', 'x', 'z', 9, 0, + /* 3136 */ 's', 'a', 'l', 'b', 9, '$', '1', ',', 32, 0, + /* 3146 */ 'r', 'c', 'l', 'b', 9, '$', '1', ',', 32, 0, + /* 3156 */ 's', 'h', 'l', 'b', 9, '$', '1', ',', 32, 0, + /* 3166 */ 'r', 'o', 'l', 'b', 9, '$', '1', ',', 32, 0, + /* 3176 */ 's', 'a', 'r', 'b', 9, '$', '1', ',', 32, 0, + /* 3186 */ 'r', 'c', 'r', 'b', 9, '$', '1', ',', 32, 0, + /* 3196 */ 's', 'h', 'r', 'b', 9, '$', '1', ',', 32, 0, + /* 3206 */ 'r', 'o', 'r', 'b', 9, '$', '1', ',', 32, 0, + /* 3216 */ 's', 'a', 'l', 'l', 9, '$', '1', ',', 32, 0, + /* 3226 */ 'r', 'c', 'l', 'l', 9, '$', '1', ',', 32, 0, + /* 3236 */ 's', 'h', 'l', 'l', 9, '$', '1', ',', 32, 0, + /* 3246 */ 'r', 'o', 'l', 'l', 9, '$', '1', ',', 32, 0, + /* 3256 */ 's', 'a', 'r', 'l', 9, '$', '1', ',', 32, 0, + /* 3266 */ 'r', 'c', 'r', 'l', 9, '$', '1', ',', 32, 0, + /* 3276 */ 's', 'h', 'r', 'l', 9, '$', '1', ',', 32, 0, + /* 3286 */ 'r', 'o', 'r', 'l', 9, '$', '1', ',', 32, 0, + /* 3296 */ 's', 'a', 'l', 'q', 9, '$', '1', ',', 32, 0, + /* 3306 */ 'r', 'c', 'l', 'q', 9, '$', '1', ',', 32, 0, + /* 3316 */ 's', 'h', 'l', 'q', 9, '$', '1', ',', 32, 0, + /* 3326 */ 'r', 'o', 'l', 'q', 9, '$', '1', ',', 32, 0, + /* 3336 */ 's', 'a', 'r', 'q', 9, '$', '1', ',', 32, 0, + /* 3346 */ 'r', 'c', 'r', 'q', 9, '$', '1', ',', 32, 0, + /* 3356 */ 's', 'h', 'r', 'q', 9, '$', '1', ',', 32, 0, + /* 3366 */ 'r', 'o', 'r', 'q', 9, '$', '1', ',', 32, 0, + /* 3376 */ 's', 'a', 'l', 'w', 9, '$', '1', ',', 32, 0, + /* 3386 */ 'r', 'c', 'l', 'w', 9, '$', '1', ',', 32, 0, + /* 3396 */ 's', 'h', 'l', 'w', 9, '$', '1', ',', 32, 0, + /* 3406 */ 'r', 'o', 'l', 'w', 9, '$', '1', ',', 32, 0, + /* 3416 */ 's', 'a', 'r', 'w', 9, '$', '1', ',', 32, 0, + /* 3426 */ 'r', 'c', 'r', 'w', 9, '$', '1', ',', 32, 0, + /* 3436 */ 's', 'h', 'r', 'w', 9, '$', '1', ',', 32, 0, + /* 3446 */ 'r', 'o', 'r', 'w', 9, '$', '1', ',', 32, 0, + /* 3456 */ 'm', 'o', 'v', 'a', 'b', 's', 'b', 9, '%', 'a', 'l', ',', 32, 0, + /* 3470 */ 's', 't', 'o', 's', 'b', 9, '%', 'a', 'l', ',', 32, 0, + /* 3482 */ 'o', 'u', 't', 'b', 9, '%', 'a', 'l', ',', 32, 0, + /* 3493 */ 'm', 'o', 'v', 'b', 9, '%', 'a', 'l', ',', 32, 0, + /* 3504 */ 's', 'a', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 3515 */ 'r', 'c', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 3526 */ 's', 'h', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 3537 */ 'r', 'o', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 3548 */ 's', 'a', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 3559 */ 'r', 'c', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 3570 */ 's', 'h', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 3581 */ 'r', 'o', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, + /* 3592 */ 's', 'h', 'l', 'd', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 3604 */ 's', 'h', 'r', 'd', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 3616 */ 's', 'a', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 3627 */ 'r', 'c', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 3638 */ 's', 'h', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 3649 */ 'r', 'o', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 3660 */ 's', 'a', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 3671 */ 'r', 'c', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 3682 */ 's', 'h', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 3693 */ 'r', 'o', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, + /* 3704 */ 's', 'h', 'l', 'd', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 3716 */ 's', 'h', 'r', 'd', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 3728 */ 's', 'a', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 3739 */ 'r', 'c', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 3750 */ 's', 'h', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 3761 */ 'r', 'o', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 3772 */ 's', 'a', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 3783 */ 'r', 'c', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 3794 */ 's', 'h', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 3805 */ 'r', 'o', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, + /* 3816 */ 's', 'h', 'l', 'd', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 3828 */ 's', 'h', 'r', 'd', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 3840 */ 's', 'a', 'l', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 3851 */ 'r', 'c', 'l', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 3862 */ 's', 'h', 'l', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 3873 */ 'r', 'o', 'l', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 3884 */ 's', 'a', 'r', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 3895 */ 'r', 'c', 'r', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 3906 */ 's', 'h', 'r', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 3917 */ 'r', 'o', 'r', 'w', 9, '%', 'c', 'l', ',', 32, 0, + /* 3928 */ 'x', 'c', 'h', 'g', 'w', 9, '%', 'a', 'x', ',', 32, 0, + /* 3940 */ 'm', 'o', 'v', 'a', 'b', 's', 'w', 9, '%', 'a', 'x', ',', 32, 0, + /* 3954 */ 's', 't', 'o', 's', 'w', 9, '%', 'a', 'x', ',', 32, 0, + /* 3966 */ 'o', 'u', 't', 'w', 9, '%', 'a', 'x', ',', 32, 0, + /* 3977 */ 'm', 'o', 'v', 'w', 9, '%', 'a', 'x', ',', 32, 0, + /* 3988 */ 'x', 'c', 'h', 'g', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, + /* 4001 */ 'm', 'o', 'v', 'a', 'b', 's', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, + /* 4016 */ 's', 't', 'o', 's', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, + /* 4029 */ 'o', 'u', 't', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, + /* 4041 */ 'm', 'o', 'v', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, + /* 4053 */ 'x', 'c', 'h', 'g', 'q', 9, '%', 'r', 'a', 'x', ',', 32, 0, + /* 4066 */ 'm', 'o', 'v', 'a', 'b', 's', 'q', 9, '%', 'r', 'a', 'x', ',', 32, 0, + /* 4081 */ 's', 't', 'o', 's', 'q', 9, '%', 'r', 'a', 'x', ',', 32, 0, + /* 4094 */ 'm', 'o', 'v', 'q', 9, '%', 'r', 'a', 'x', ',', 32, 0, + /* 4106 */ 'i', 'n', 's', 'b', 9, '%', 'd', 'x', ',', 32, 0, + /* 4117 */ 'i', 'n', 's', 'l', 9, '%', 'd', 'x', ',', 32, 0, + /* 4128 */ 'i', 'n', 's', 'w', 9, '%', 'd', 'x', ',', 32, 0, + /* 4139 */ 'l', 'c', 'a', 'l', 'l', 'l', 9, '*', 0, + /* 4148 */ 'l', 'j', 'm', 'p', 'l', 9, '*', 0, + /* 4156 */ 'l', 'c', 'a', 'l', 'l', 'q', 9, '*', 0, + /* 4165 */ 'l', 'j', 'm', 'p', 'q', 9, '*', 0, + /* 4173 */ 'l', 'c', 'a', 'l', 'l', 'w', 9, '*', 0, + /* 4182 */ 'l', 'j', 'm', 'p', 'w', 9, '*', 0, + /* 4190 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, + /* 4221 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 4245 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 4270 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, + /* 4293 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, + /* 4316 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, + /* 4338 */ 'u', 'd', '0', 0, + /* 4342 */ 'x', 's', 'h', 'a', '1', 0, + /* 4348 */ 'u', 'd', '1', 0, + /* 4352 */ 'i', 'n', 't', '1', 0, + /* 4357 */ 'e', 'n', 'd', 'b', 'r', '3', '2', 0, + /* 4365 */ 'u', 'd', '2', 0, + /* 4369 */ 'i', 'n', 't', '3', 0, + /* 4374 */ 'e', 'n', 'd', 'b', 'r', '6', '4', 0, + /* 4382 */ 'r', 'e', 'x', '6', '4', 0, + /* 4388 */ 'd', 'a', 't', 'a', '1', '6', 0, + /* 4395 */ 'x', 's', 'h', 'a', '2', '5', '6', 0, + /* 4403 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 4416 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 4423 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 4433 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, + /* 4443 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 4458 */ 'a', 'a', 'a', 0, + /* 4462 */ 'd', 'a', 'a', 0, + /* 4466 */ 'x', 'c', 'r', 'y', 'p', 't', 'e', 'c', 'b', 0, + /* 4476 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'f', 'b', 0, + /* 4486 */ 'x', 'c', 'r', 'y', 'p', 't', 'o', 'f', 'b', 0, + /* 4496 */ 'x', 'l', 'a', 't', 'b', 0, + /* 4502 */ 'c', 'l', 'a', 'c', 0, + /* 4507 */ 's', 't', 'a', 'c', 0, + /* 4512 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'b', 'c', 0, + /* 4522 */ 'g', 'e', 't', 's', 'e', 'c', 0, + /* 4529 */ 's', 'a', 'l', 'c', 0, + /* 4534 */ 'c', 'l', 'c', 0, + /* 4538 */ 'c', 'm', 'c', 0, + /* 4542 */ 'r', 'd', 'p', 'm', 'c', 0, + /* 4548 */ 'v', 'm', 'f', 'u', 'n', 'c', 0, + /* 4555 */ 'r', 'd', 't', 's', 'c', 0, + /* 4561 */ 's', 't', 'c', 0, + /* 4565 */ 'c', 'p', 'u', 'i', 'd', 0, + /* 4571 */ 'c', 'l', 'd', 0, + /* 4575 */ 'c', 'l', 't', 'd', 0, + /* 4580 */ 's', 't', 'd', 0, + /* 4584 */ 'c', 'w', 't', 'd', 0, + /* 4589 */ 'w', 'b', 'i', 'n', 'v', 'd', 0, + /* 4596 */ 'w', 'b', 'n', 'o', 'i', 'n', 'v', 'd', 0, + /* 4605 */ 'v', 'm', 'r', 'e', 's', 'u', 'm', 'e', 0, + /* 4614 */ 'r', 'e', 'p', 'n', 'e', 0, + /* 4620 */ 'x', 's', 't', 'o', 'r', 'e', 0, + /* 4627 */ 'l', 'e', 'a', 'v', 'e', 0, + /* 4633 */ 'v', 'm', 'x', 'o', 'f', 'f', 0, + /* 4640 */ 'l', 'a', 'h', 'f', 0, + /* 4645 */ 's', 'a', 'h', 'f', 0, + /* 4650 */ 'p', 'c', 'o', 'n', 'f', 'i', 'g', 0, + /* 4658 */ 'v', 'm', 'l', 'a', 'u', 'n', 'c', 'h', 0, + /* 4667 */ 'c', 'l', 'g', 'i', 0, + /* 4672 */ 's', 't', 'g', 'i', 0, + /* 4677 */ 'c', 'l', 'i', 0, + /* 4681 */ 's', 't', 'i', 0, + /* 4685 */ 'l', 'o', 'c', 'k', 0, + /* 4690 */ 'i', 'n', 'b', 9, '%', 'd', 'x', ',', 32, '%', 'a', 'l', 0, + /* 4703 */ 'p', 'u', 's', 'h', 'a', 'l', 0, + /* 4710 */ 'p', 'o', 'p', 'a', 'l', 0, + /* 4716 */ 'p', 'u', 's', 'h', 'f', 'l', 0, + /* 4723 */ 'p', 'o', 'p', 'f', 'l', 0, + /* 4729 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, + /* 4743 */ 'v', 'm', 'm', 'c', 'a', 'l', 'l', 0, + /* 4751 */ 'v', 'm', 'c', 'a', 'l', 'l', 0, + /* 4758 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 0, + /* 4766 */ 'i', 'r', 'e', 't', 'l', 0, + /* 4772 */ 'l', 'r', 'e', 't', 'l', 0, + /* 4778 */ 's', 'y', 's', 'r', 'e', 't', 'l', 0, + /* 4786 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'l', 0, + /* 4795 */ 'c', 'w', 't', 'l', 0, + /* 4800 */ 'm', 'o', 'n', 't', 'm', 'u', 'l', 0, + /* 4808 */ 'f', 's', 'e', 't', 'p', 'm', 0, + /* 4815 */ 'r', 's', 'm', 0, + /* 4819 */ 'c', 'l', 'z', 'e', 'r', 'o', 0, + /* 4826 */ 'i', 'n', 't', 'o', 0, + /* 4831 */ 'c', 'q', 't', 'o', 0, + /* 4836 */ 'r', 'd', 't', 's', 'c', 'p', 0, + /* 4843 */ 'r', 'e', 'p', 0, + /* 4847 */ 'n', 'o', 'p', 0, + /* 4851 */ 's', 'a', 'v', 'e', 'p', 'r', 'e', 'v', 's', 's', 'p', 0, + /* 4863 */ 'p', 'u', 's', 'h', 'f', 'q', 0, + /* 4870 */ 'p', 'o', 'p', 'f', 'q', 0, + /* 4876 */ 'i', 'r', 'e', 't', 'q', 0, + /* 4882 */ 'l', 'r', 'e', 't', 'q', 0, + /* 4888 */ 's', 'y', 's', 'r', 'e', 't', 'q', 0, + /* 4896 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'q', 0, + /* 4905 */ 'c', 'l', 't', 'q', 0, + /* 4910 */ 's', 'y', 's', 'e', 'n', 't', 'e', 'r', 0, + /* 4919 */ 'r', 'd', 'm', 's', 'r', 0, + /* 4925 */ 'w', 'r', 'm', 's', 'r', 0, + /* 4931 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 't', 'r', 0, + /* 4941 */ 'a', 'a', 's', 0, + /* 4945 */ 'd', 'a', 's', 0, + /* 4949 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'c', 's', 0, + /* 4959 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'c', 's', 0, + /* 4969 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'd', 's', 0, + /* 4979 */ 'p', 'o', 'p', 'l', 9, '%', 'd', 's', 0, + /* 4988 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'd', 's', 0, + /* 4998 */ 'p', 'o', 'p', 'w', 9, '%', 'd', 's', 0, + /* 5007 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'e', 's', 0, + /* 5017 */ 'p', 'o', 'p', 'l', 9, '%', 'e', 's', 0, + /* 5026 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'e', 's', 0, + /* 5036 */ 'p', 'o', 'p', 'w', 9, '%', 'e', 's', 0, + /* 5045 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'f', 's', 0, + /* 5055 */ 'p', 'o', 'p', 'l', 9, '%', 'f', 's', 0, + /* 5064 */ 'p', 'u', 's', 'h', 'q', 9, '%', 'f', 's', 0, + /* 5074 */ 'p', 'o', 'p', 'q', 9, '%', 'f', 's', 0, + /* 5083 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'f', 's', 0, + /* 5093 */ 'p', 'o', 'p', 'w', 9, '%', 'f', 's', 0, + /* 5102 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'g', 's', 0, + /* 5112 */ 'p', 'o', 'p', 'l', 9, '%', 'g', 's', 0, + /* 5121 */ 'p', 'u', 's', 'h', 'q', 9, '%', 'g', 's', 0, + /* 5131 */ 'p', 'o', 'p', 'q', 9, '%', 'g', 's', 0, + /* 5140 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'g', 's', 0, + /* 5150 */ 'p', 'o', 'p', 'w', 9, '%', 'g', 's', 0, + /* 5159 */ 's', 'w', 'a', 'p', 'g', 's', 0, + /* 5166 */ 'p', 'u', 's', 'h', 'l', 9, '%', 's', 's', 0, + /* 5176 */ 'p', 'o', 'p', 'l', 9, '%', 's', 's', 0, + /* 5185 */ 'p', 'u', 's', 'h', 'w', 9, '%', 's', 's', 0, + /* 5195 */ 'p', 'o', 'p', 'w', 9, '%', 's', 's', 0, + /* 5204 */ 'c', 'l', 't', 's', 0, + /* 5209 */ 'h', 'l', 't', 0, + /* 5213 */ 'r', 'd', 'p', 'k', 'r', 'u', 0, + /* 5220 */ 'w', 'r', 'p', 'k', 'r', 'u', 0, + /* 5227 */ 'x', 'g', 'e', 't', 'b', 'v', 0, + /* 5234 */ 'x', 's', 'e', 't', 'b', 'v', 0, + /* 5241 */ 'p', 'u', 's', 'h', 'a', 'w', 0, + /* 5248 */ 'p', 'o', 'p', 'a', 'w', 0, + /* 5254 */ 'p', 'u', 's', 'h', 'f', 'w', 0, + /* 5261 */ 'p', 'o', 'p', 'f', 'w', 0, + /* 5267 */ 'c', 'b', 't', 'w', 0, + /* 5272 */ 'i', 'r', 'e', 't', 'w', 0, + /* 5278 */ 'l', 'r', 'e', 't', 'w', 0, + /* 5284 */ 'i', 'n', 'w', 9, '%', 'd', 'x', ',', 32, '%', 'a', 'x', 0, + /* 5297 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, '%', 'e', 'a', 'x', 0, + /* 5309 */ 'v', 'm', 's', 'a', 'v', 'e', 9, '%', 'e', 'a', 'x', 0, + /* 5321 */ 'v', 'm', 'r', 'u', 'n', 9, '%', 'e', 'a', 'x', 0, + /* 5332 */ 's', 'k', 'i', 'n', 'i', 't', 9, '%', 'e', 'a', 'x', 0, + /* 5344 */ 'i', 'n', 'l', 9, '%', 'd', 'x', ',', 32, '%', 'e', 'a', 'x', 0, + /* 5358 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, '%', 'r', 'a', 'x', 0, + /* 5370 */ 'v', 'm', 's', 'a', 'v', 'e', 9, '%', 'r', 'a', 'x', 0, + /* 5382 */ 'v', 'm', 'r', 'u', 'n', 9, '%', 'r', 'a', 'x', 0, + /* 5393 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, '%', 'e', 'a', 'x', ',', 32, '%', 'e', 'c', 'x', 0, + /* 5412 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, '%', 'r', 'a', 'x', ',', 32, '%', 'e', 'c', 'x', 0, + /* 5431 */ 'o', 'u', 't', 'b', 9, '%', 'a', 'l', ',', 32, '%', 'd', 'x', 0, + /* 5445 */ 'o', 'u', 't', 'w', 9, '%', 'a', 'x', ',', 32, '%', 'd', 'x', 0, + /* 5459 */ 'o', 'u', 't', 'l', 9, '%', 'e', 'a', 'x', ',', 32, '%', 'd', 'x', 0, + /* 5474 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 'x', 0, + /* 5483 */ 'm', 'w', 'a', 'i', 't', 'x', 0, + /* 5490 */ 's', 'e', 't', 's', 's', 'b', 's', 'y', 0, + }; +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 4424U, // DBG_VALUE + 4434U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 4417U, // BUNDLE + 4444U, // LIFETIME_START + 4404U, // LIFETIME_END + 0U, // STACKMAP + 4730U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 4271U, // PATCHABLE_FUNCTION_ENTER + 4191U, // PATCHABLE_RET + 4317U, // PATCHABLE_FUNCTION_EXIT + 4294U, // PATCHABLE_TAIL_CALL + 4246U, // PATCHABLE_EVENT_CALL + 4222U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 4459U, // AAA + 8540U, // AAD8i8 + 9620U, // AAM8i8 + 4942U, // AAS + 535027U, // ADC16i16 + 1067507U, // ADC16mi + 1067507U, // ADC16mi8 + 1067507U, // ADC16mr + 1599987U, // ADC16ri + 1599987U, // ADC16ri8 + 1608179U, // ADC16rm + 1599987U, // ADC16rr + 2124275U, // ADC16rr_REV + 2630253U, // ADC32i32 + 3162733U, // ADC32mi + 3162733U, // ADC32mi8 + 3162733U, // ADC32mr + 1598061U, // ADC32ri + 1598061U, // ADC32ri8 + 1614445U, // ADC32rm + 1598061U, // ADC32rr + 2122349U, // ADC32rr_REV + 3679768U, // ADC64i32 + 4212248U, // ADC64mi32 + 4212248U, // ADC64mi8 + 4212248U, // ADC64mr + 1599000U, // ADC64ri32 + 1599000U, // ADC64ri8 + 1623576U, // ADC64rm + 1599000U, // ADC64rr + 2123288U, // ADC64rr_REV + 4726903U, // ADC8i8 + 5259383U, // ADC8mi + 5259383U, // ADC8mi8 + 5259383U, // ADC8mr + 1597559U, // ADC8ri + 1597559U, // ADC8ri8 + 57463U, // ADC8rm + 1597559U, // ADC8rr + 2121847U, // ADC8rr_REV + 2139491U, // ADCX32rm + 2123107U, // ADCX32rr + 2148608U, // ADCX64rm + 2124032U, // ADCX64rr + 535052U, // ADD16i16 + 1067532U, // ADD16mi + 1067532U, // ADD16mi8 + 1067532U, // ADD16mr + 1600012U, // ADD16ri + 1600012U, // ADD16ri8 + 1608204U, // ADD16rm + 1600012U, // ADD16rr + 2124300U, // ADD16rr_REV + 2630312U, // ADD32i32 + 3162792U, // ADD32mi + 3162792U, // ADD32mi8 + 3162792U, // ADD32mr + 1598120U, // ADD32ri + 1598120U, // ADD32ri8 + 1614504U, // ADD32rm + 1598120U, // ADD32rr + 2122408U, // ADD32rr_REV + 3679827U, // ADD64i32 + 4212307U, // ADD64mi32 + 4212307U, // ADD64mi8 + 4212307U, // ADD64mr + 1599059U, // ADD64ri32 + 1599059U, // ADD64ri8 + 1623635U, // ADD64rm + 1599059U, // ADD64rr + 2123347U, // ADD64rr_REV + 4726938U, // ADD8i8 + 5259418U, // ADD8mi + 5259418U, // ADD8mi8 + 5259418U, // ADD8mr + 1597594U, // ADD8ri + 1597594U, // ADD8ri8 + 57498U, // ADD8rm + 1597594U, // ADD8rr + 2121882U, // ADD8rr_REV + 2139512U, // ADOX32rm + 2123128U, // ADOX32rr + 2148629U, // ADOX64rm + 2124053U, // ADOX64rr + 535077U, // AND16i16 + 1067557U, // AND16mi + 1067557U, // AND16mi8 + 1067557U, // AND16mr + 1600037U, // AND16ri + 1600037U, // AND16ri8 + 1608229U, // AND16rm + 1600037U, // AND16rr + 2124325U, // AND16rr_REV + 2630337U, // AND32i32 + 3162817U, // AND32mi + 3162817U, // AND32mi8 + 3162817U, // AND32mr + 1598145U, // AND32ri + 1598145U, // AND32ri8 + 1614529U, // AND32rm + 1598145U, // AND32rr + 2122433U, // AND32rr_REV + 3679852U, // AND64i32 + 4212332U, // AND64mi32 + 4212332U, // AND64mi8 + 4212332U, // AND64mr + 1599084U, // AND64ri32 + 1599084U, // AND64ri8 + 1623660U, // AND64rm + 1599084U, // AND64rr + 2123372U, // AND64rr_REV + 4726944U, // AND8i8 + 5259424U, // AND8mi + 5259424U, // AND8mi8 + 5259424U, // AND8mr + 1597600U, // AND8ri + 1597600U, // AND8ri8 + 57504U, // AND8rm + 1597600U, // AND8rr + 2121888U, // AND8rr_REV + 18392036U, // ANDN32rm + 18375652U, // ANDN32rr + 18401170U, // ANDN64rm + 18376594U, // ANDN64rr + 1066034U, // ARPL16mr + 39388210U, // ARPL16rr + 6366333U, // BEXTR32rm + 18375805U, // BEXTR32rr + 6891562U, // BEXTR64rm + 18376746U, // BEXTR64rr + 6366333U, // BEXTRI32mi + 18375805U, // BEXTRI32ri + 6891562U, // BEXTRI64mi + 18376746U, // BEXTRI64ri + 82869U, // BLCFILL32rm + 39388085U, // BLCFILL32rr + 91995U, // BLCFILL64rm + 39389019U, // BLCFILL64rr + 82792U, // BLCI32rm + 39388008U, // BLCI32rr + 91923U, // BLCI64rm + 39388947U, // BLCI64rr + 82553U, // BLCIC32rm + 39387769U, // BLCIC32rr + 91684U, // BLCIC64rm + 39388708U, // BLCIC64rr + 82817U, // BLCMSK32rm + 39388033U, // BLCMSK32rr + 91944U, // BLCMSK64rm + 39388968U, // BLCMSK64rr + 83093U, // BLCS32rm + 39388309U, // BLCS32rr + 92226U, // BLCS64rm + 39389250U, // BLCS64rr + 82879U, // BLSFILL32rm + 39388095U, // BLSFILL32rr + 92005U, // BLSFILL64rm + 39389029U, // BLSFILL64rr + 82806U, // BLSI32rm + 39388022U, // BLSI32rr + 91937U, // BLSI64rm + 39388961U, // BLSI64rr + 82561U, // BLSIC32rm + 39387777U, // BLSIC32rr + 91692U, // BLSIC64rm + 39388716U, // BLSIC64rr + 82826U, // BLSMSK32rm + 39388042U, // BLSMSK32rr + 91953U, // BLSMSK64rm + 39388977U, // BLSMSK64rr + 83050U, // BLSR32rm + 39388266U, // BLSR32rr + 92183U, // BLSR64rm + 39389207U, // BLSR64rr + 56107395U, // BOUNDS16rm + 72884611U, // BOUNDS32rm + 100967U, // BSF16rm + 39389799U, // BSF16rr + 82755U, // BSF32rm + 39387971U, // BSF32rr + 91886U, // BSF64rm + 39388910U, // BSF64rr + 101171U, // BSR16rm + 39390003U, // BSR16rr + 83044U, // BSR32rm + 39388260U, // BSR32rr + 92177U, // BSR64rm + 39389201U, // BSR64rr + 10967U, // BSWAP16r_BAD + 9217U, // BSWAP32r + 10154U, // BSWAP64r + 1067941U, // BT16mi8 + 1067941U, // BT16mr + 39390117U, // BT16ri8 + 39390117U, // BT16rr + 3163366U, // BT32mi8 + 3163366U, // BT32mr + 39388390U, // BT32ri8 + 39388390U, // BT32rr + 4212873U, // BT64mi8 + 4212873U, // BT64mr + 39389321U, // BT64ri8 + 39389321U, // BT64rr + 1067525U, // BTC16mi8 + 1067525U, // BTC16mr + 1600005U, // BTC16ri8 + 1600005U, // BTC16rr + 3162776U, // BTC32mi8 + 3162776U, // BTC32mr + 1598104U, // BTC32ri8 + 1598104U, // BTC32rr + 4212291U, // BTC64mi8 + 4212291U, // BTC64mr + 1599043U, // BTC64ri8 + 1599043U, // BTC64rr + 1067833U, // BTR16mi8 + 1067833U, // BTR16mr + 1600313U, // BTR16ri8 + 1600313U, // BTR16rr + 3163249U, // BTR32mi8 + 3163249U, // BTR32mr + 1598577U, // BTR32ri8 + 1598577U, // BTR32rr + 4212766U, // BTR64mi8 + 4212766U, // BTR64mr + 1599518U, // BTR64ri8 + 1599518U, // BTR64rr + 1067920U, // BTS16mi8 + 1067920U, // BTS16mr + 1600400U, // BTS16ri8 + 1600400U, // BTS16rr + 3163345U, // BTS32mi8 + 3163345U, // BTS32mr + 1598673U, // BTS32ri8 + 1598673U, // BTS32rr + 4212859U, // BTS64mi8 + 4212859U, // BTS64mr + 1599611U, // BTS64ri8 + 1599611U, // BTS64rr + 6366063U, // BZHI32rm + 18375535U, // BZHI32rr + 6891290U, // BZHI64rm + 18376474U, // BZHI64rr + 110671U, // CALL16m + 110671U, // CALL16m_NT + 12367U, // CALL16r + 12367U, // CALL16r_NT + 118829U, // CALL32m + 118829U, // CALL32m_NT + 12333U, // CALL32r + 12333U, // CALL32r_NT + 127038U, // CALL64m + 127038U, // CALL64m_NT + 132948U, // CALL64pcrel32 + 12350U, // CALL64r + 12350U, // CALL64r_NT + 133791U, // CALLpcrel16 + 132014U, // CALLpcrel32 + 5268U, // CBW + 4576U, // CDQ + 4906U, // CDQE + 4503U, // CLAC + 4535U, // CLC + 4572U, // CLD + 139783U, // CLDEMOTE + 141740U, // CLFLUSHOPT + 4668U, // CLGI + 4678U, // CLI + 117795U, // CLRSSBSY + 5205U, // CLTS + 139598U, // CLWB + 4820U, // CLZEROr + 4539U, // CMC + 2132423U, // CMOVA16rm + 2124231U, // CMOVA16rr + 2138681U, // CMOVA32rm + 2122297U, // CMOVA32rr + 2147820U, // CMOVA64rm + 2123244U, // CMOVA64rr + 2132530U, // CMOVAE16rm + 2124338U, // CMOVAE16rr + 2138830U, // CMOVAE32rm + 2122446U, // CMOVAE32rr + 2147961U, // CMOVAE64rm + 2123385U, // CMOVAE64rr + 2132451U, // CMOVB16rm + 2124259U, // CMOVB16rr + 2138717U, // CMOVB32rm + 2122333U, // CMOVB32rr + 2147848U, // CMOVB64rm + 2123272U, // CMOVB64rr + 2132539U, // CMOVBE16rm + 2124347U, // CMOVBE16rr + 2138839U, // CMOVBE32rm + 2122455U, // CMOVBE32rr + 2147970U, // CMOVBE64rm + 2123394U, // CMOVBE64rr + 2132575U, // CMOVE16rm + 2124383U, // CMOVE16rr + 2138939U, // CMOVE32rm + 2122555U, // CMOVE32rr + 2148070U, // CMOVE64rm + 2123494U, // CMOVE64rr + 2132605U, // CMOVG16rm + 2124413U, // CMOVG16rr + 2138969U, // CMOVG32rm + 2122585U, // CMOVG32rr + 2148100U, // CMOVG64rm + 2123524U, // CMOVG64rr + 2132548U, // CMOVGE16rm + 2124356U, // CMOVGE16rr + 2138848U, // CMOVGE32rm + 2122464U, // CMOVGE32rr + 2147979U, // CMOVGE64rm + 2123403U, // CMOVGE64rr + 2132665U, // CMOVL16rm + 2124473U, // CMOVL16rr + 2139100U, // CMOVL32rm + 2122716U, // CMOVL32rr + 2148234U, // CMOVL64rm + 2123658U, // CMOVL64rr + 2132557U, // CMOVLE16rm + 2124365U, // CMOVLE16rr + 2138857U, // CMOVLE32rm + 2122473U, // CMOVLE32rr + 2147988U, // CMOVLE64rm + 2123412U, // CMOVLE64rr + 2132566U, // CMOVNE16rm + 2124374U, // CMOVNE16rr + 2138866U, // CMOVNE32rm + 2122482U, // CMOVNE32rr + 2147997U, // CMOVNE64rm + 2123421U, // CMOVNE64rr + 2132678U, // CMOVNO16rm + 2124486U, // CMOVNO16rr + 2139120U, // CMOVNO32rm + 2122736U, // CMOVNO32rr + 2148249U, // CMOVNO64rm + 2123673U, // CMOVNO64rr + 2132716U, // CMOVNP16rm + 2124524U, // CMOVNP16rr + 2139165U, // CMOVNP32rm + 2122781U, // CMOVNP32rr + 2148287U, // CMOVNP64rm + 2123711U, // CMOVNP64rr + 2132858U, // CMOVNS16rm + 2124666U, // CMOVNS16rr + 2139323U, // CMOVNS32rm + 2122939U, // CMOVNS32rr + 2148438U, // CMOVNS64rm + 2123862U, // CMOVNS64rr + 2132687U, // CMOVO16rm + 2124495U, // CMOVO16rr + 2139129U, // CMOVO32rm + 2122745U, // CMOVO32rr + 2148258U, // CMOVO64rm + 2123682U, // CMOVO64rr + 2132737U, // CMOVP16rm + 2124545U, // CMOVP16rr + 2139192U, // CMOVP32rm + 2122808U, // CMOVP32rr + 2148325U, // CMOVP64rm + 2123749U, // CMOVP64rr + 2132893U, // CMOVS16rm + 2124701U, // CMOVS16rr + 2139358U, // CMOVS32rm + 2122974U, // CMOVS32rr + 2148481U, // CMOVS64rm + 2123905U, // CMOVS64rr + 535263U, // CMP16i16 + 1067743U, // CMP16mi + 1067743U, // CMP16mi8 + 1067743U, // CMP16mr + 39389919U, // CMP16ri + 39389919U, // CMP16ri8 + 101087U, // CMP16rm + 39389919U, // CMP16rr + 39389919U, // CMP16rr_REV + 2630672U, // CMP32i32 + 3163152U, // CMP32mi + 3163152U, // CMP32mi8 + 3163152U, // CMP32mr + 39388176U, // CMP32ri + 39388176U, // CMP32ri8 + 82960U, // CMP32rm + 39388176U, // CMP32rr + 39388176U, // CMP32rr_REV + 3680185U, // CMP64i32 + 4212665U, // CMP64mi32 + 4212665U, // CMP64mi8 + 4212665U, // CMP64mr + 39389113U, // CMP64ri32 + 39389113U, // CMP64ri8 + 92089U, // CMP64rm + 39389113U, // CMP64rr + 39389113U, // CMP64rr_REV + 4727006U, // CMP8i8 + 5259486U, // CMP8mi + 5259486U, // CMP8mi8 + 5259486U, // CMP8mr + 39387358U, // CMP8ri + 39387358U, // CMP8ri8 + 147678U, // CMP8rm + 39387358U, // CMP8rr + 39387358U, // CMP8rr_REV + 89809177U, // CMPSB + 106595524U, // CMPSL + 123381855U, // CMPSQ + 140168067U, // CMPSW + 188500U, // CMPXCHG16B + 1067635U, // CMPXCHG16rm + 39389811U, // CMPXCHG16rr + 3162959U, // CMPXCHG32rm + 39387983U, // CMPXCHG32rr + 4212474U, // CMPXCHG64rm + 39388922U, // CMPXCHG64rr + 122976U, // CMPXCHG8B + 5259436U, // CMPXCHG8rm + 39387308U, // CMPXCHG8rr + 4566U, // CPUID + 4832U, // CQO + 4585U, // CWD + 4796U, // CWDE + 4463U, // DAA + 4946U, // DAS + 4389U, // DATA16_PREFIX + 109049U, // DEC16m + 10745U, // DEC16r + 10745U, // DEC16r_alt + 115315U, // DEC32m + 8819U, // DEC32r + 8819U, // DEC32r_alt + 124446U, // DEC64m + 9758U, // DEC64r + 139389U, // DEC8m + 8317U, // DEC8r + 109561U, // DIV16m + 11257U, // DIV16r + 116032U, // DIV32m + 9536U, // DIV32r + 125149U, // DIV64m + 10461U, // DIV64r + 139586U, // DIV8m + 8514U, // DIV8r + 4358U, // ENDBR32 + 4375U, // ENDBR64 + 156772666U, // ENTER + 39389854U, // FARCALL16i + 200782U, // FARCALL16m + 39388077U, // FARCALL32i + 200748U, // FARCALL32m + 200765U, // FARCALL64 + 7408357U, // FARJMP16i + 200791U, // FARJMP16m + 7406614U, // FARJMP32i + 200757U, // FARJMP32m + 200774U, // FARJMP64 + 4809U, // FSETPM + 4523U, // GETSEC + 5210U, // HLT + 109560U, // IDIV16m + 11256U, // IDIV16r + 116031U, // IDIV32m + 9535U, // IDIV32r + 125148U, // IDIV64m + 10460U, // IDIV64r + 139585U, // IDIV8m + 8513U, // IDIV8r + 109234U, // IMUL16m + 10930U, // IMUL16r + 2132658U, // IMUL16rm + 7940786U, // IMUL16rmi + 7940786U, // IMUL16rmi8 + 2124466U, // IMUL16rr + 18377394U, // IMUL16rri + 18377394U, // IMUL16rri8 + 115669U, // IMUL32m + 9173U, // IMUL32r + 2139093U, // IMUL32rm + 6366165U, // IMUL32rmi + 6366165U, // IMUL32rmi8 + 2122709U, // IMUL32rr + 18375637U, // IMUL32rri + 18375637U, // IMUL32rri8 + 124803U, // IMUL64m + 10115U, // IMUL64r + 2148227U, // IMUL64rm + 6891395U, // IMUL64rmi32 + 6891395U, // IMUL64rmi8 + 2123651U, // IMUL64rr + 18376579U, // IMUL64rri32 + 18376579U, // IMUL64rri8 + 139474U, // IMUL8m + 8402U, // IMUL8r + 731841U, // IN16ri + 5285U, // IN16rr + 2827243U, // IN32ri + 5345U, // IN32rr + 4923609U, // IN8ri + 4691U, // IN8rr + 109055U, // INC16m + 10751U, // INC16r + 10751U, // INC16r_alt + 115346U, // INC32m + 8850U, // INC32r + 8850U, // INC32r_alt + 124477U, // INC64m + 9789U, // INC64r + 139395U, // INC8m + 8323U, // INC8r + 8586U, // INCSSPD + 10196U, // INCSSPQ + 159755U, // INSB + 167958U, // INSL + 184353U, // INSW + 207253U, // INT + 4353U, // INT1 + 4370U, // INT3 + 4827U, // INTO + 4592U, // INVD + 215450U, // INVEPT32 + 215450U, // INVEPT64 + 139804U, // INVLPG + 5394U, // INVLPGA32 + 5413U, // INVLPGA64 + 213345U, // INVPCID32 + 213345U, // INVPCID64 + 213361U, // INVVPID32 + 213361U, // INVVPID64 + 5273U, // IRET16 + 4767U, // IRET32 + 4877U, // IRET64 + 131498U, // JAE_1 + 131498U, // JAE_2 + 131498U, // JAE_4 + 131135U, // JA_1 + 131135U, // JA_2 + 131135U, // JA_4 + 131510U, // JBE_1 + 131510U, // JBE_2 + 131510U, // JBE_4 + 131254U, // JB_1 + 131254U, // JB_2 + 131254U, // JB_4 + 134196U, // JCXZ + 134189U, // JECXZ + 131534U, // JE_1 + 131534U, // JE_2 + 131534U, // JE_4 + 131522U, // JGE_1 + 131522U, // JGE_2 + 131522U, // JGE_4 + 131608U, // JG_1 + 131608U, // JG_2 + 131608U, // JG_4 + 131538U, // JLE_1 + 131538U, // JLE_2 + 131538U, // JLE_4 + 131965U, // JL_1 + 131965U, // JL_2 + 131965U, // JL_4 + 110680U, // JMP16m + 110680U, // JMP16m_NT + 12376U, // JMP16r + 12376U, // JMP16r_NT + 118838U, // JMP32m + 118838U, // JMP32m_NT + 12342U, // JMP32r + 12342U, // JMP32r_NT + 127047U, // JMP64m + 127047U, // JMP64m_NT + 12359U, // JMP64r + 12359U, // JMP64r_NT + 132538U, // JMP_1 + 132538U, // JMP_2 + 132538U, // JMP_4 + 131550U, // JNE_1 + 131550U, // JNE_2 + 131550U, // JNE_4 + 132516U, // JNO_1 + 132516U, // JNO_2 + 132516U, // JNO_4 + 132543U, // JNP_1 + 132543U, // JNP_2 + 132543U, // JNP_4 + 133490U, // JNS_1 + 133490U, // JNS_2 + 133490U, // JNS_4 + 132512U, // JO_1 + 132512U, // JO_2 + 132512U, // JO_4 + 132534U, // JP_1 + 132534U, // JP_2 + 132534U, // JP_4 + 134202U, // JRCXZ + 133478U, // JS_1 + 133478U, // JS_2 + 133478U, // JS_4 + 4641U, // LAHF + 101129U, // LAR16rm + 39389961U, // LAR16rr + 99392U, // LAR32rm + 39388224U, // LAR32rr + 100333U, // LAR64rm + 39389165U, // LAR64rr + 224091U, // LDS16rm + 222364U, // LDS32rm + 231873U, // LEA16r + 229939U, // LEA32r + 229939U, // LEA64_32r + 230886U, // LEA64r + 4628U, // LEAVE + 4628U, // LEAVE64 + 224104U, // LES16rm + 222377U, // LES32rm + 224110U, // LFS16rm + 222383U, // LFS32rm + 223312U, // LFS64rm + 199594U, // LGDT16m + 197867U, // LGDT32m + 198798U, // LGDT64m + 224116U, // LGS16rm + 222389U, // LGS32rm + 223585U, // LGS64rm + 199608U, // LIDT16m + 197881U, // LIDT32m + 198812U, // LIDT64m + 109510U, // LLDT16m + 11206U, // LLDT16r + 8329U, // LLWPCB + 8329U, // LLWPCB64 + 109573U, // LMSW16m + 11269U, // LMSW16r + 4686U, // LOCK_PREFIX + 4956434U, // LODSB + 2868386U, // LODSL + 256073U, // LODSQ + 789345U, // LODSW + 132560U, // LOOP + 131570U, // LOOPE + 131555U, // LOOPNE + 9486U, // LRETIL + 10417U, // LRETIQ + 11220U, // LRETIW + 4773U, // LRETL + 4883U, // LRETQ + 5279U, // LRETW + 101036U, // LSL16rm + 39389868U, // LSL16rr + 99279U, // LSL32rm + 39388111U, // LSL32rr + 100213U, // LSL64rm + 39389045U, // LSL64rr + 224138U, // LSS16rm + 222411U, // LSS32rm + 223334U, // LSS64rm + 109375U, // LTRm + 11071U, // LTRr + 6367594U, // LWPINS32rmi + 18377066U, // LWPINS32rri + 6367594U, // LWPINS64rmi + 18377066U, // LWPINS64rri + 6365761U, // LWPVAL32rmi + 18375233U, // LWPVAL32rri + 6365761U, // LWPVAL64rmi + 18375233U, // LWPVAL64rri + 101339U, // LZCNT16rm + 39390171U, // LZCNT16rr + 83227U, // LZCNT32rm + 39388443U, // LZCNT32rr + 92344U, // LZCNT64rm + 39389368U, // LZCNT64rr + 5475U, // MONITORXrrr + 4801U, // MONTMUL + 797695U, // MOV16ao16 + 797695U, // MOV16ao32 + 797522U, // MOV16ao64 + 1068031U, // MOV16mi + 1068031U, // MOV16mr + 1068031U, // MOV16ms + 274314U, // MOV16o16a + 274314U, // MOV16o32a + 274277U, // MOV16o64a + 39390207U, // MOV16ri + 39390207U, // MOV16ri_alt + 101375U, // MOV16rm + 39390207U, // MOV16rr + 39390207U, // MOV16rr_REV + 39390207U, // MOV16rs + 101375U, // MOV16sm + 39390207U, // MOV16sr + 2901318U, // MOV32ao16 + 2901318U, // MOV32ao32 + 2901132U, // MOV32ao64 + 39388486U, // MOV32cr + 39388486U, // MOV32dr + 3163462U, // MOV32mi + 3163462U, // MOV32mr + 282570U, // MOV32o16a + 282570U, // MOV32o32a + 282530U, // MOV32o64a + 39388486U, // MOV32rc + 39388486U, // MOV32rd + 39388486U, // MOV32ri + 39388486U, // MOV32ri_alt + 83270U, // MOV32rm + 39388486U, // MOV32rr + 39388486U, // MOV32rr_REV + 39388486U, // MOV32rs + 39388486U, // MOV32sr + 3959011U, // MOV64ao32 + 3958841U, // MOV64ao64 + 39389411U, // MOV64cr + 39389411U, // MOV64dr + 4212963U, // MOV64mi32 + 4212963U, // MOV64mr + 290815U, // MOV64o32a + 290787U, // MOV64o64a + 39389411U, // MOV64rc + 39389411U, // MOV64rd + 39389241U, // MOV64ri + 39389411U, // MOV64ri32 + 92387U, // MOV64rm + 39389411U, // MOV64rr + 39389411U, // MOV64rr_REV + 39389411U, // MOV64rs + 39389411U, // MOV64sr + 5013832U, // MOV8ao16 + 5013832U, // MOV8ao32 + 5013769U, // MOV8ao64 + 5259592U, // MOV8mi + 5259592U, // MOV8mr + 5259592U, // MOV8mr_NOREX + 298406U, // MOV8o16a + 298406U, // MOV8o32a + 298369U, // MOV8o64a + 39387464U, // MOV8ri + 39387464U, // MOV8ri_alt + 147784U, // MOV8rm + 147784U, // MOV8rm_NOREX + 39387464U, // MOV8rr + 39387464U, // MOV8rr_NOREX + 39387464U, // MOV8rr_REV + 1067580U, // MOVBE16mr + 100924U, // MOVBE16rm + 3162840U, // MOVBE32mr + 82648U, // MOVBE32rm + 4212355U, // MOVBE64mr + 91779U, // MOVBE64rm + 303177U, // MOVDIR64B16 + 303177U, // MOVDIR64B32 + 303177U, // MOVDIR64B64 + 3162666U, // MOVDIRI32 + 4211242U, // MOVDIRI64 + 311591U, // MOVSB + 320735U, // MOVSL + 329858U, // MOVSQ + 338846U, // MOVSW + 101395U, // MOVSX16rm16 + 149973U, // MOVSX16rm8 + 39390227U, // MOVSX16rr16 + 39389653U, // MOVSX16rr8 + 99667U, // MOVSX32rm16 + 148047U, // MOVSX32rm8 + 148047U, // MOVSX32rm8_NOREX + 39388499U, // MOVSX32rr16 + 39387727U, // MOVSX32rr8 + 39387727U, // MOVSX32rr8_NOREX + 100592U, // MOVSX64rm16 + 83835U, // MOVSX64rm32 + 148986U, // MOVSX64rm8 + 39389424U, // MOVSX64rr16 + 39389051U, // MOVSX64rr32 + 39388666U, // MOVSX64rr8 + 101403U, // MOVZX16rm16 + 149995U, // MOVZX16rm8 + 39390235U, // MOVZX16rr16 + 39389675U, // MOVZX16rr8 + 99675U, // MOVZX32rm16 + 148069U, // MOVZX32rm8 + 148069U, // MOVZX32rm8_NOREX + 39388507U, // MOVZX32rr16 + 39387749U, // MOVZX32rr8 + 39387749U, // MOVZX32rr8_NOREX + 100600U, // MOVZX64rm16 + 149008U, // MOVZX64rm8 + 39389432U, // MOVZX64rr16 + 39388688U, // MOVZX64rr8 + 109235U, // MUL16m + 10931U, // MUL16r + 115670U, // MUL32m + 9174U, // MUL32r + 124804U, // MUL64m + 10116U, // MUL64r + 139475U, // MUL8m + 8403U, // MUL8r + 18392433U, // MULX32rm + 18376049U, // MULX32rr + 18401550U, // MULX64rm + 18376974U, // MULX64rr + 5484U, // MWAITXrrr + 109165U, // NEG16m + 10861U, // NEG16r + 115529U, // NEG32m + 9033U, // NEG32r + 124660U, // NEG64m + 9972U, // NEG64r + 139430U, // NEG8m + 8358U, // NEG8r + 4848U, // NOOP + 109301U, // NOOP18_16m4 + 109301U, // NOOP18_16m5 + 109301U, // NOOP18_16m6 + 109301U, // NOOP18_16m7 + 10997U, // NOOP18_16r4 + 10997U, // NOOP18_16r5 + 10997U, // NOOP18_16r6 + 10997U, // NOOP18_16r7 + 115750U, // NOOP18_m4 + 115750U, // NOOP18_m5 + 115750U, // NOOP18_m6 + 115750U, // NOOP18_m7 + 9254U, // NOOP18_r4 + 9254U, // NOOP18_r5 + 9254U, // NOOP18_r6 + 9254U, // NOOP18_r7 + 156771787U, // NOOP19rr + 115750U, // NOOPL + 115750U, // NOOPL_19 + 115750U, // NOOPL_1d + 115750U, // NOOPL_1e + 9254U, // NOOPLr + 124872U, // NOOPQ + 10184U, // NOOPQr + 109301U, // NOOPW + 109301U, // NOOPW_19 + 109301U, // NOOPW_1c + 109301U, // NOOPW_1d + 109301U, // NOOPW_1e + 10997U, // NOOPWr + 109547U, // NOT16m + 11243U, // NOT16r + 116011U, // NOT32m + 9515U, // NOT32r + 125128U, // NOT64m + 10440U, // NOT64r + 139572U, // NOT8m + 8500U, // NOT8r + 535336U, // OR16i16 + 1067816U, // OR16mi + 1067816U, // OR16mi8 + 1067816U, // OR16mr + 1600296U, // OR16ri + 1600296U, // OR16ri8 + 1608488U, // OR16rm + 1600296U, // OR16rr + 2124584U, // OR16rr_REV + 2630745U, // OR32i32 + 3163225U, // OR32mi + 3163225U, // OR32mi8 + 3163225U, // OR32mr + 1598553U, // OR32ri + 1598553U, // OR32ri8 + 1614937U, // OR32rm + 1598553U, // OR32rr + 2122841U, // OR32rr_REV + 3680262U, // OR64i32 + 4212742U, // OR64mi32 + 4212742U, // OR64mi8 + 4212742U, // OR64mr + 1599494U, // OR64ri32 + 1599494U, // OR64ri8 + 1624070U, // OR64rm + 1599494U, // OR64rr + 2123782U, // OR64rr_REV + 4727031U, // OR8i8 + 5259511U, // OR8mi + 5259511U, // OR8mi8 + 5259511U, // OR8mr + 1597687U, // OR8ri + 1597687U, // OR8ri8 + 57591U, // OR8rm + 1597687U, // OR8rr + 2121975U, // OR8rr_REV + 208767U, // OUT16ir + 5446U, // OUT16rr + 208830U, // OUT32ir + 5460U, // OUT32rr + 208283U, // OUT8ir + 5432U, // OUT8rr + 8626464U, // OUTSB + 8635607U, // OUTSL + 8653718U, // OUTSW + 4651U, // PCONFIG + 18392073U, // PDEP32rm + 18375689U, // PDEP32rr + 18401202U, // PDEP64rm + 18376626U, // PDEP64rr + 18392376U, // PEXT32rm + 18375992U, // PEXT32rr + 18401493U, // PEXT64rm + 18376917U, // PEXT64rr + 11003U, // POP16r + 109307U, // POP16rmm + 11003U, // POP16rmr + 9260U, // POP32r + 115756U, // POP32rmm + 9260U, // POP32rmr + 10190U, // POP64r + 124878U, // POP64rmm + 10190U, // POP64rmr + 5249U, // POPA16 + 4711U, // POPA32 + 4999U, // POPDS16 + 4980U, // POPDS32 + 5037U, // POPES16 + 5018U, // POPES32 + 5262U, // POPF16 + 4724U, // POPF32 + 4871U, // POPF64 + 5094U, // POPFS16 + 5056U, // POPFS32 + 5075U, // POPFS64 + 5151U, // POPGS16 + 5113U, // POPGS32 + 5132U, // POPGS64 + 5196U, // POPSS16 + 5177U, // POPSS32 + 124636U, // PTWRITE64m + 9948U, // PTWRITE64r + 115505U, // PTWRITEm + 9009U, // PTWRITEr + 10885U, // PUSH16i8 + 10885U, // PUSH16r + 109189U, // PUSH16rmm + 10885U, // PUSH16rmr + 9057U, // PUSH32i8 + 9057U, // PUSH32r + 115553U, // PUSH32rmm + 9057U, // PUSH32rmr + 9996U, // PUSH64i32 + 9996U, // PUSH64i8 + 9996U, // PUSH64r + 124684U, // PUSH64rmm + 9996U, // PUSH64rmr + 5242U, // PUSHA16 + 4704U, // PUSHA32 + 4960U, // PUSHCS16 + 4950U, // PUSHCS32 + 4989U, // PUSHDS16 + 4970U, // PUSHDS32 + 5027U, // PUSHES16 + 5008U, // PUSHES32 + 5255U, // PUSHF16 + 4717U, // PUSHF32 + 4864U, // PUSHF64 + 5084U, // PUSHFS16 + 5046U, // PUSHFS32 + 5065U, // PUSHFS64 + 5141U, // PUSHGS16 + 5103U, // PUSHGS32 + 5122U, // PUSHGS64 + 5186U, // PUSHSS16 + 5167U, // PUSHSS32 + 10885U, // PUSHi16 + 9057U, // PUSHi32 + 109202U, // RCL16m1 + 110348U, // RCL16mCL + 1395346U, // RCL16mi + 11579U, // RCL16r1 + 12044U, // RCL16rCL + 2452114U, // RCL16ri + 115617U, // RCL32m1 + 118316U, // RCL32mCL + 3490721U, // RCL32mi + 11419U, // RCL32r1 + 11820U, // RCL32rCL + 2450337U, // RCL32ri + 124744U, // RCL64m1 + 126620U, // RCL64mCL + 4540232U, // RCL64mi + 11499U, // RCL64r1 + 11932U, // RCL64rCL + 2451272U, // RCL64ri + 139456U, // RCL8m1 + 142780U, // RCL8mCL + 5587136U, // RCL8mi + 11339U, // RCL8r1 + 11708U, // RCL8rCL + 2449600U, // RCL8ri + 109923U, // RCR16m1 + 110392U, // RCR16mCL + 1395477U, // RCR16mi + 11619U, // RCR16r1 + 12088U, // RCR16rCL + 2452245U, // RCR16ri + 117955U, // RCR32m1 + 118360U, // RCR32mCL + 3490892U, // RCR32mi + 11459U, // RCR32r1 + 11864U, // RCR32rCL + 2450508U, // RCR32ri + 126227U, // RCR64m1 + 126664U, // RCR64mCL + 4540409U, // RCR64mi + 11539U, // RCR64r1 + 11976U, // RCR64rCL + 2451449U, // RCR64ri + 142451U, // RCR8m1 + 142824U, // RCR8mCL + 5587178U, // RCR8mi + 11379U, // RCR8r1 + 11752U, // RCR8rCL + 2449642U, // RCR8ri + 8955U, // RDFSBASE + 9894U, // RDFSBASE64 + 8977U, // RDGSBASE + 9916U, // RDGSBASE64 + 4920U, // RDMSR + 8554U, // RDPID32 + 8554U, // RDPID64 + 5214U, // RDPKRUr + 4543U, // RDPMC + 10786U, // RDRAND16r + 8894U, // RDRAND32r + 9833U, // RDRAND64r + 10770U, // RDSEED16r + 8878U, // RDSEED32r + 9817U, // RDSEED64r + 8595U, // RDSSPD + 10205U, // RDSSPQ + 4556U, // RDTSC + 4837U, // RDTSCP + 4615U, // REPNE_PREFIX + 4844U, // REP_PREFIX + 9487U, // RETIL + 10418U, // RETIQ + 11221U, // RETIW + 4768U, // RETL + 4878U, // RETQ + 5274U, // RETW + 4383U, // REX64_PREFIX + 109222U, // ROL16m1 + 110370U, // ROL16mCL + 1395366U, // ROL16mi + 11599U, // ROL16r1 + 12066U, // ROL16rCL + 2452134U, // ROL16ri + 115657U, // ROL32m1 + 118338U, // ROL32mCL + 3490761U, // ROL32mi + 11439U, // ROL32r1 + 11842U, // ROL32rCL + 2450377U, // ROL32ri + 124783U, // ROL64m1 + 126642U, // ROL64mCL + 4540271U, // ROL64mi + 11519U, // ROL64r1 + 11954U, // ROL64rCL + 2451311U, // ROL64ri + 139468U, // ROL8m1 + 142802U, // ROL8mCL + 5587148U, // ROL8mi + 11359U, // ROL8r1 + 11730U, // ROL8rCL + 2449612U, // ROL8ri + 109351U, // ROR16m1 + 110414U, // ROR16mCL + 1395495U, // ROR16mi + 11639U, // ROR16r1 + 12110U, // ROR16rCL + 2452263U, // ROR16ri + 115800U, // ROR32m1 + 118382U, // ROR32mCL + 3490904U, // ROR32mi + 11479U, // ROR32r1 + 11886U, // ROR32rCL + 2450520U, // ROR32ri + 124933U, // ROR64m1 + 126686U, // ROR64mCL + 4540421U, // ROR64mi + 11559U, // ROR64r1 + 11998U, // ROR64rCL + 2451461U, // ROR64ri + 139510U, // ROR8m1 + 142846U, // ROR8mCL + 5587190U, // ROR8mi + 11399U, // ROR8r1 + 11774U, // ROR8rCL + 2449654U, // ROR8ri + 6653325U, // RORX32mi + 18703757U, // RORX32ri + 7178538U, // RORX64mi + 18704682U, // RORX64ri + 4816U, // RSM + 116182U, // RSTORSSP + 4646U, // SAHF + 109196U, // SAL16m1 + 110337U, // SAL16mCL + 1067660U, // SAL16mi + 11569U, // SAL16r1 + 12033U, // SAL16rCL + 2124428U, // SAL16ri + 115611U, // SAL32m1 + 118305U, // SAL32mCL + 3163035U, // SAL32mi + 11409U, // SAL32r1 + 11809U, // SAL32rCL + 2122651U, // SAL32ri + 124738U, // SAL64m1 + 126609U, // SAL64mCL + 4212546U, // SAL64mi + 11489U, // SAL64r1 + 11921U, // SAL64rCL + 2123586U, // SAL64ri + 139450U, // SAL8m1 + 142769U, // SAL8mCL + 5259450U, // SAL8mi + 11329U, // SAL8r1 + 11697U, // SAL8rCL + 2121914U, // SAL8ri + 4530U, // SALC + 109327U, // SAR16m1 + 110381U, // SAR16mCL + 1395471U, // SAR16mi + 11609U, // SAR16r1 + 12077U, // SAR16rCL + 2452239U, // SAR16ri + 115782U, // SAR32m1 + 118349U, // SAR32mCL + 3490886U, // SAR32mi + 11449U, // SAR32r1 + 11853U, // SAR32rCL + 2450502U, // SAR32ri + 124915U, // SAR64m1 + 126653U, // SAR64mCL + 4540403U, // SAR64mi + 11529U, // SAR64r1 + 11965U, // SAR64rCL + 2451443U, // SAR64ri + 139492U, // SAR8m1 + 142813U, // SAR8mCL + 5587172U, // SAR8mi + 11369U, // SAR8r1 + 11741U, // SAR8rCL + 2449636U, // SAR8ri + 6366591U, // SARX32rm + 18376063U, // SARX32rr + 6891804U, // SARX64rm + 18376988U, // SARX64rr + 4852U, // SAVEPREVSSP + 534991U, // SBB16i16 + 1067471U, // SBB16mi + 1067471U, // SBB16mi8 + 1067471U, // SBB16mr + 1599951U, // SBB16ri + 1599951U, // SBB16ri8 + 1608143U, // SBB16rm + 1599951U, // SBB16rr + 2124239U, // SBB16rr_REV + 2630217U, // SBB32i32 + 3162697U, // SBB32mi + 3162697U, // SBB32mi8 + 3162697U, // SBB32mr + 1598025U, // SBB32ri + 1598025U, // SBB32ri8 + 1614409U, // SBB32rm + 1598025U, // SBB32rr + 2122313U, // SBB32rr_REV + 3679732U, // SBB64i32 + 4212212U, // SBB64mi32 + 4212212U, // SBB64mi8 + 4212212U, // SBB64mr + 1598964U, // SBB64ri32 + 1598964U, // SBB64ri8 + 1623540U, // SBB64rm + 1598964U, // SBB64rr + 2123252U, // SBB64rr_REV + 4726891U, // SBB8i8 + 5259371U, // SBB8mi + 5259371U, // SBB8mi8 + 5259371U, // SBB8mr + 1597547U, // SBB8ri + 1597547U, // SBB8ri8 + 57451U, // SBB8rm + 1597547U, // SBB8rr + 2121835U, // SBB8rr_REV + 4874498U, // SCASB + 2786437U, // SCASL + 3844146U, // SCASQ + 707403U, // SCASW + 139695U, // SETAEm + 8623U, // SETAEr + 139331U, // SETAm + 8259U, // SETAr + 139707U, // SETBEm + 8635U, // SETBEr + 139566U, // SETBm + 8494U, // SETBr + 139777U, // SETEm + 8705U, // SETEr + 139719U, // SETGEm + 8647U, // SETGEr + 139812U, // SETGm + 8740U, // SETGr + 139735U, // SETLEm + 8663U, // SETLEr + 140565U, // SETLm + 9493U, // SETLr + 139755U, // SETNEm + 8683U, // SETNEr + 140713U, // SETNOm + 9641U, // SETNOr + 140740U, // SETNPm + 9668U, // SETNPr + 141687U, // SETNSm + 10615U, // SETNSr + 140720U, // SETOm + 9648U, // SETOr + 140768U, // SETPm + 9696U, // SETPr + 5491U, // SETSSBSY + 141703U, // SETSm + 10631U, // SETSr + 199601U, // SGDT16m + 197874U, // SGDT32m + 198805U, // SGDT64m + 109208U, // SHL16m1 + 110359U, // SHL16mCL + 1395352U, // SHL16mi + 11589U, // SHL16r1 + 12055U, // SHL16rCL + 2452120U, // SHL16ri + 115623U, // SHL32m1 + 118327U, // SHL32mCL + 3490727U, // SHL32mi + 11429U, // SHL32r1 + 11831U, // SHL32rCL + 2450343U, // SHL32ri + 124750U, // SHL64m1 + 126631U, // SHL64mCL + 4540238U, // SHL64mi + 11509U, // SHL64r1 + 11943U, // SHL64rCL + 2451278U, // SHL64ri + 139462U, // SHL8m1 + 142791U, // SHL8mCL + 5587142U, // SHL8mi + 11349U, // SHL8r1 + 11719U, // SHL8rCL + 2449606U, // SHL8ri + 1068777U, // SHLD16mrCL + 177048091U, // SHLD16mri8 + 2125545U, // SHLD16rrCL + 371227U, // SHLD16rri8 + 3165705U, // SHLD32mrCL + 193823415U, // SHLD32mri8 + 2125321U, // SHLD32rrCL + 369335U, // SHLD32rri8 + 4214393U, // SHLD64mrCL + 210601570U, // SHLD64mri8 + 2125433U, // SHLD64rrCL + 370274U, // SHLD64rri8 + 6366570U, // SHLX32rm + 18376042U, // SHLX32rr + 6891783U, // SHLX64rm + 18376967U, // SHLX64rr + 109345U, // SHR16m1 + 110403U, // SHR16mCL + 1395489U, // SHR16mi + 11629U, // SHR16r1 + 12099U, // SHR16rCL + 2452257U, // SHR16ri + 115794U, // SHR32m1 + 118371U, // SHR32mCL + 3490898U, // SHR32mi + 11469U, // SHR32r1 + 11875U, // SHR32rCL + 2450514U, // SHR32ri + 124927U, // SHR64m1 + 126675U, // SHR64mCL + 4540415U, // SHR64mi + 11549U, // SHR64r1 + 11987U, // SHR64rCL + 2451455U, // SHR64ri + 139504U, // SHR8m1 + 142835U, // SHR8mCL + 5587184U, // SHR8mi + 11389U, // SHR8r1 + 11763U, // SHR8rCL + 2449648U, // SHR8ri + 1068789U, // SHRD16mrCL + 177048107U, // SHRD16mri8 + 2125557U, // SHRD16rrCL + 371243U, // SHRD16rri8 + 3165717U, // SHRD32mrCL + 193823431U, // SHRD32mri8 + 2125333U, // SHRD32rrCL + 369351U, // SHRD32rri8 + 4214405U, // SHRD64mrCL + 210601586U, // SHRD64mri8 + 2125445U, // SHRD64rrCL + 370290U, // SHRD64rri8 + 6366598U, // SHRX32rm + 18376070U, // SHRX32rr + 6891811U, // SHRX64rm + 18376995U, // SHRX64rr + 199615U, // SIDT16m + 197888U, // SIDT32m + 198819U, // SIDT64m + 5333U, // SKINIT + 109517U, // SLDT16m + 11213U, // SLDT16r + 9479U, // SLDT32r + 10410U, // SLDT64r + 8337U, // SLWPCB + 8337U, // SLWPCB64 + 109580U, // SMSW16m + 11276U, // SMSW16r + 9548U, // SMSW32r + 10473U, // SMSW64r + 4508U, // STAC + 4562U, // STC + 4581U, // STD + 4673U, // STGI + 4682U, // STI + 159119U, // STOSB + 167857U, // STOSL + 176114U, // STOSQ + 184179U, // STOSW + 11077U, // STR16r + 9335U, // STR32r + 10276U, // STR64r + 109381U, // STRm + 535005U, // SUB16i16 + 1067485U, // SUB16mi + 1067485U, // SUB16mi8 + 1067485U, // SUB16mr + 1599965U, // SUB16ri + 1599965U, // SUB16ri8 + 1608157U, // SUB16rm + 1599965U, // SUB16rr + 2124253U, // SUB16rr_REV + 2630231U, // SUB32i32 + 3162711U, // SUB32mi + 3162711U, // SUB32mi8 + 3162711U, // SUB32mr + 1598039U, // SUB32ri + 1598039U, // SUB32ri8 + 1614423U, // SUB32rm + 1598039U, // SUB32rr + 2122327U, // SUB32rr_REV + 3679746U, // SUB64i32 + 4212226U, // SUB64mi32 + 4212226U, // SUB64mi8 + 4212226U, // SUB64mr + 1598978U, // SUB64ri32 + 1598978U, // SUB64ri8 + 1623554U, // SUB64rm + 1598978U, // SUB64rr + 2123266U, // SUB64rr_REV + 4726897U, // SUB8i8 + 5259377U, // SUB8mi + 5259377U, // SUB8mi8 + 5259377U, // SUB8mr + 1597553U, // SUB8ri + 1597553U, // SUB8ri8 + 57457U, // SUB8rm + 1597553U, // SUB8rr + 2121841U, // SUB8rr_REV + 5160U, // SWAPGS + 4759U, // SYSCALL + 4911U, // SYSENTER + 4787U, // SYSEXIT + 4897U, // SYSEXIT64 + 4779U, // SYSRET + 4889U, // SYSRET64 + 82569U, // T1MSKC32rm + 39387785U, // T1MSKC32rr + 91700U, // T1MSKC64rm + 39388724U, // T1MSKC64rr + 535537U, // TEST16i16 + 1068017U, // TEST16mi + 1068017U, // TEST16mi_alt + 1068017U, // TEST16mr + 39390193U, // TEST16ri + 39390193U, // TEST16ri_alt + 39390193U, // TEST16rr + 2630961U, // TEST32i32 + 3163441U, // TEST32mi + 3163441U, // TEST32mi_alt + 3163441U, // TEST32mr + 39388465U, // TEST32ri + 39388465U, // TEST32ri_alt + 39388465U, // TEST32rr + 3680462U, // TEST64i32 + 4212942U, // TEST64mi32 + 4212942U, // TEST64mi32_alt + 4212942U, // TEST64mr + 39389390U, // TEST64ri32 + 39389390U, // TEST64ri32_alt + 39389390U, // TEST64rr + 4727098U, // TEST8i8 + 5259578U, // TEST8mi + 5259578U, // TEST8mi_alt + 5259578U, // TEST8mr + 39387450U, // TEST8ri + 39387450U, // TEST8ri_alt + 39387450U, // TEST8rr + 8697U, // TPAUSE + 101347U, // TZCNT16rm + 39390179U, // TZCNT16rr + 83235U, // TZCNT32rm + 39388451U, // TZCNT32rr + 92352U, // TZCNT64rm + 39389376U, // TZCNT64rr + 82835U, // TZMSK32rm + 39388051U, // TZMSK32rr + 91962U, // TZMSK64rm + 39388986U, // TZMSK64rr + 4339U, // UD0 + 4349U, // UD1 + 4366U, // UD2 + 10561U, // UMONITOR16 + 10561U, // UMONITOR32 + 10561U, // UMONITOR64 + 10637U, // UMWAIT + 108883U, // VERRm + 10579U, // VERRr + 109339U, // VERWm + 11035U, // VERWr + 4752U, // VMCALL + 125233U, // VMCLEARm + 4549U, // VMFUNC + 4659U, // VMLAUNCH + 5298U, // VMLOAD32 + 5359U, // VMLOAD64 + 4744U, // VMMCALL + 123258U, // VMPTRLDm + 125368U, // VMPTRSTm + 3162782U, // VMREAD32mr + 39387806U, // VMREAD32rr + 4212297U, // VMREAD64mr + 39388745U, // VMREAD64rr + 4606U, // VMRESUME + 5322U, // VMRUN32 + 5383U, // VMRUN64 + 5310U, // VMSAVE32 + 5371U, // VMSAVE64 + 82727U, // VMWRITE32rm + 39387943U, // VMWRITE32rr + 91858U, // VMWRITE64rm + 39388882U, // VMWRITE64rr + 4634U, // VMXOFF + 124313U, // VMXON + 4590U, // WBINVD + 4597U, // WBNOINVD + 8966U, // WRFSBASE + 9905U, // WRFSBASE64 + 8988U, // WRGSBASE + 9927U, // WRGSBASE64 + 4926U, // WRMSR + 5221U, // WRPKRUr + 3162523U, // WRSSD + 4212844U, // WRSSQ + 3162530U, // WRUSSD + 4212851U, // WRUSSQ + 223939083U, // XADD16rm + 379403U, // XADD16rr + 240714407U, // XADD32rm + 377511U, // XADD32rr + 257492562U, // XADD64rm + 378450U, // XADD64rr + 274268313U, // XADD8rm + 376985U, // XADD8rr + 69465U, // XCHG16ar + 223939190U, // XCHG16rm + 9464438U, // XCHG16rr + 69525U, // XCHG32ar + 240714578U, // XCHG32rm + 9462610U, // XCHG32rr + 69590U, // XCHG64ar + 257492733U, // XCHG64rm + 9463549U, // XCHG64rr + 274268335U, // XCHG8rm + 9461935U, // XCHG8rr + 4513U, // XCRYPTCBC + 4477U, // XCRYPTCFB + 4932U, // XCRYPTCTR + 4467U, // XCRYPTECB + 4487U, // XCRYPTOFB + 5228U, // XGETBV + 4497U, // XLAT + 535341U, // XOR16i16 + 1067821U, // XOR16mi + 1067821U, // XOR16mi8 + 1067821U, // XOR16mr + 1600301U, // XOR16ri + 1600301U, // XOR16ri8 + 1608493U, // XOR16rm + 1600301U, // XOR16rr + 2124589U, // XOR16rr_REV + 2630750U, // XOR32i32 + 3163230U, // XOR32mi + 3163230U, // XOR32mi8 + 3163230U, // XOR32mr + 1598558U, // XOR32ri + 1598558U, // XOR32ri8 + 1614942U, // XOR32rm + 1598558U, // XOR32rr + 2122846U, // XOR32rr_REV + 3680267U, // XOR64i32 + 4212747U, // XOR64mi32 + 4212747U, // XOR64mi8 + 4212747U, // XOR64mr + 1599499U, // XOR64ri32 + 1599499U, // XOR64ri8 + 1624075U, // XOR64rm + 1599499U, // XOR64rr + 2123787U, // XOR64rr_REV + 4727036U, // XOR8i8 + 5259516U, // XOR8mi + 5259516U, // XOR8mi8 + 5259516U, // XOR8mr + 1597692U, // XOR8ri + 1597692U, // XOR8ri8 + 57596U, // XOR8rm + 1597692U, // XOR8rr + 2121980U, // XOR8rr_REV + 198987U, // XRSTOR + 196628U, // XRSTOR64 + 199038U, // XRSTORS + 196648U, // XRSTORS64 + 197137U, // XSAVE + 196619U, // XSAVE64 + 196948U, // XSAVEC + 196609U, // XSAVEC64 + 199074U, // XSAVEOPT + 196659U, // XSAVEOPT64 + 199001U, // XSAVES + 196638U, // XSAVES64 + 5235U, // XSETBV + 4343U, // XSHA1 + 4396U, // XSHA256 + 4621U, // XSTORE + }; + + unsigned int opcode = MCInst_getOpcode(MI); + // printf("opcode = %u\n", opcode); + + // Emit the opcode for the instruction. + uint32_t Bits = 0; + Bits |= OpInfo0[opcode] << 0; + SStream_concat0(O, AsmStrs+(Bits & 8191)-1); + + + // Fragment 0 encoded into 6 bits for 47 unique commands. + // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 13) & 63)); + switch ((uint32_t)((Bits >> 13) & 63)) { + default: // unreachable + case 0: + // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... + return; + break; + case 1: + // AAD8i8, AAM8i8, ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i... + printOperand(MI, 0, O); + break; + case 2: + // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC... + printOperand(MI, 5, O); + SStream_concat0(O, ", "); + break; + case 3: + // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A... + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 4: + // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r... + printi16mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 5: + // ADC32rm, ADCX32rm, ADD32rm, ADOX32rm, AND32rm, ANDN32rm, CMOVA32rm, CM... + printi32mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 6: + // ADC64rm, ADCX64rm, ADD64rm, ADOX64rm, AND64rm, ANDN64rm, CMOVA64rm, CM... + printi64mem(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 7: + // ADC8rm, ADD8rm, AND8rm, OR8rm, SBB8rm, SUB8rm, XOR8rm + printi8mem(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 8: + // ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI64rr, BLCIC32rr, BLC... + printOperand(MI, 1, O); + break; + case 9: + // BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZHI32rm, BZHI64rm, IMUL... + printOperand(MI, 6, O); + SStream_concat0(O, ", "); + break; + case 10: + // BLCFILL32rm, BLCI32rm, BLCIC32rm, BLCMSK32rm, BLCS32rm, BLSFILL32rm, B... + printi32mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 11: + // BLCFILL64rm, BLCI64rm, BLCIC64rm, BLCMSK64rm, BLCS64rm, BLSFILL64rm, B... + printi64mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 12: + // BSF16rm, BSR16rm, CMP16rm, LAR16rm, LAR32rm, LAR64rm, LSL16rm, LSL32rm... + printi16mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 13: + // CALL16m, CALL16m_NT, DEC16m, DIV16m, IDIV16m, IMUL16m, INC16m, JMP16m,... + printi16mem(MI, 0, O); + return; + break; + case 14: + // CALL32m, CALL32m_NT, CLRSSBSY, DEC32m, DIV32m, IDIV32m, IMUL32m, INC32... + printi32mem(MI, 0, O); + return; + break; + case 15: + // CALL64m, CALL64m_NT, CMPXCHG8B, DEC64m, DIV64m, IDIV64m, IMUL64m, INC6... + printi64mem(MI, 0, O); + return; + break; + case 16: + // CALL64pcrel32, CALLpcrel16, CALLpcrel32, JAE_1, JAE_2, JAE_4, JA_1, JA... + printPCRelImm(MI, 0, O); + return; + break; + case 17: + // CLDEMOTE, CLFLUSHOPT, CLWB, DEC8m, DIV8m, IDIV8m, IMUL8m, INC8m, INVLP... + printi8mem(MI, 0, O); + return; + break; + case 18: + // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX32rm8_NOREX... + printi8mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 19: + // CMPSB, INSB, SCASB, STOSB + printDstIdx8(MI, 0, O); + break; + case 20: + // CMPSL, INSL, SCASL, STOSL + printDstIdx32(MI, 0, O); + break; + case 21: + // CMPSQ, SCASQ, STOSQ + printDstIdx64(MI, 0, O); + break; + case 22: + // CMPSW, INSW, SCASW, STOSW + printDstIdx16(MI, 0, O); + break; + case 23: + // CMPXCHG16B + printi128mem(MI, 0, O); + return; + break; + case 24: + // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, LGD... + printopaquemem(MI, 0, O); + return; + break; + case 25: + // IN16ri, IN32ri, IN8ri, INT, OUT16ir, OUT32ir, OUT8ir + printU8Imm(MI, 0, O); + break; + case 26: + // INVEPT32, INVEPT64, INVPCID32, INVPCID64, INVVPID32, INVVPID64 + printi128mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 27: + // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm... + printopaquemem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 28: + // LEA16r, LEA32r, LEA64_32r, LEA64r + printanymem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 29: + // LODSB, OUTSB + printSrcIdx8(MI, 0, O); + break; + case 30: + // LODSL, OUTSL + printSrcIdx32(MI, 0, O); + break; + case 31: + // LODSQ + printSrcIdx64(MI, 0, O); + SStream_concat0(O, ", %rax"); + op_addReg(MI, X86_REG_RAX); + return; + break; + case 32: + // LODSW, OUTSW + printSrcIdx16(MI, 0, O); + break; + case 33: + // MOV16ao16, MOV16ao32, MOV16ao64, MOV16o16a, MOV16o32a, MOV16o64a + printMemOffs16(MI, 0, O); + break; + case 34: + // MOV32ao16, MOV32ao32, MOV32ao64, MOV32o16a, MOV32o32a, MOV32o64a + printMemOffs32(MI, 0, O); + break; + case 35: + // MOV64ao32, MOV64ao64, MOV64o32a, MOV64o64a + printMemOffs64(MI, 0, O); + break; + case 36: + // MOV8ao16, MOV8ao32, MOV8ao64, MOV8o16a, MOV8o32a, MOV8o64a + printMemOffs8(MI, 0, O); + break; + case 37: + // MOVDIR64B16, MOVDIR64B32, MOVDIR64B64 + printi512mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 38: + // MOVSB + printSrcIdx8(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx8(MI, 0, O); + return; + break; + case 39: + // MOVSL + printSrcIdx32(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx32(MI, 0, O); + return; + break; + case 40: + // MOVSQ + printSrcIdx64(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx64(MI, 0, O); + return; + break; + case 41: + // MOVSW + printSrcIdx16(MI, 1, O); + SStream_concat0(O, ", "); + printDstIdx16(MI, 0, O); + return; + break; + case 42: + // RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi, ... + printU8Imm(MI, 5, O); + SStream_concat0(O, ", "); + break; + case 43: + // RCL16ri, RCL32ri, RCL64ri, RCL8ri, RCR16ri, RCR32ri, RCR64ri, RCR8ri, ... + printU8Imm(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 44: + // RORX32mi, RORX64mi, SHLD16mri8, SHLD32mri8, SHLD64mri8, SHRD16mri8, SH... + printU8Imm(MI, 6, O); + SStream_concat0(O, ", "); + break; + case 45: + // SHLD16rri8, SHLD32rri8, SHLD64rri8, SHRD16rri8, SHRD32rri8, SHRD64rri8 + printU8Imm(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 46: + // XADD16rr, XADD32rr, XADD64rr, XADD8rr + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + } + + + // Fragment 1 encoded into 5 bits for 19 unique commands. + // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 19) & 31)); + switch ((uint32_t)((Bits >> 19) & 31)) { + default: // unreachable + case 0: + // AAD8i8, AAM8i8, BSWAP16r_BAD, BSWAP32r, BSWAP64r, CALL16r, CALL16r_NT,... + return; + break; + case 1: + // ADC16i16, ADD16i16, AND16i16, CMP16i16, IN16ri, LODSW, MOV16ao16, MOV1... + SStream_concat0(O, ", %ax"); + op_addReg(MI, X86_REG_AX); + return; + break; + case 2: + // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, AND16mi, AND16... + printi16mem(MI, 0, O); + return; + break; + case 3: + // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32... + printOperand(MI, 1, O); + break; + case 4: + // ADC16rr_REV, ADC32rr_REV, ADC64rr_REV, ADC8rr_REV, ADCX32rm, ADCX32rr,... + printOperand(MI, 0, O); + return; + break; + case 5: + // ADC32i32, ADD32i32, AND32i32, CMP32i32, IN32ri, LODSL, MOV32ao16, MOV3... + SStream_concat0(O, ", %eax"); + op_addReg(MI, X86_REG_EAX); + return; + break; + case 6: + // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, AND32mi, AND32... + printi32mem(MI, 0, O); + return; + break; + case 7: + // ADC64i32, ADD64i32, AND64i32, CMP64i32, MOV64ao32, MOV64ao64, OR64i32,... + SStream_concat0(O, ", %rax"); + op_addReg(MI, X86_REG_RAX); + return; + break; + case 8: + // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,... + printi64mem(MI, 0, O); + return; + break; + case 9: + // ADC8i8, ADD8i8, AND8i8, CMP8i8, IN8ri, LODSB, MOV8ao16, MOV8ao32, MOV8... + SStream_concat0(O, ", %al"); + op_addReg(MI, X86_REG_AL); + return; + break; + case 10: + // ADC8mi, ADC8mi8, ADC8mr, ADD8mi, ADD8mi8, ADD8mr, AND8mi, AND8mi8, AND... + printi8mem(MI, 0, O); + return; + break; + case 11: + // ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI64rr, BLCIC32rr, BLC... + SStream_concat0(O, ", "); + break; + case 12: + // BEXTR32rm, BEXTRI32mi, BZHI32rm, IMUL32rmi, IMUL32rmi8, LWPINS32rmi, L... + printi32mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 13: + // BEXTR64rm, BEXTRI64mi, BZHI64rm, IMUL64rmi32, IMUL64rmi8, RORX64mi, SA... + printi64mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 14: + // FARJMP16i, FARJMP32i + SStream_concat0(O, ":"); + printOperand(MI, 0, O); + return; + break; + case 15: + // IMUL16rmi, IMUL16rmi8 + printi16mem(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 16: + // OUTSB, OUTSL, OUTSW + SStream_concat0(O, ", %dx"); + op_addReg(MI, X86_REG_DX); + return; + break; + case 17: + // SHLD16mri8, SHLD32mri8, SHLD64mri8, SHRD16mri8, SHRD32mri8, SHRD64mri8 + printOperand(MI, 5, O); + SStream_concat0(O, ", "); + break; + case 18: + // XCHG16rr, XCHG32rr, XCHG64rr, XCHG8rr + printOperand(MI, 3, O); + return; + break; + } + + + // Fragment 2 encoded into 5 bits for 17 unique commands. + // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 24) & 31)); + switch ((uint32_t)((Bits >> 24) & 31)) { + default: // unreachable + case 0: + // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32... + return; + break; + case 1: + // ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr, BEXTR32rr, BEXTR64rr, BEXTRI32... + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 2: + // ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI64rr, BLCIC32rr, BLC... + printOperand(MI, 0, O); + return; + break; + case 3: + // BOUNDS16rm + printi32mem(MI, 1, O); + return; + break; + case 4: + // BOUNDS32rm + printi64mem(MI, 1, O); + return; + break; + case 5: + // CMPSB + printSrcIdx8(MI, 1, O); + return; + break; + case 6: + // CMPSL + printSrcIdx32(MI, 1, O); + return; + break; + case 7: + // CMPSQ + printSrcIdx64(MI, 1, O); + return; + break; + case 8: + // CMPSW + printSrcIdx16(MI, 1, O); + return; + break; + case 9: + // ENTER, NOOP19rr + printOperand(MI, 1, O); + return; + break; + case 10: + // SHLD16mri8, SHRD16mri8 + printi16mem(MI, 0, O); + return; + break; + case 11: + // SHLD32mri8, SHRD32mri8 + printi32mem(MI, 0, O); + return; + break; + case 12: + // SHLD64mri8, SHRD64mri8 + printi64mem(MI, 0, O); + return; + break; + case 13: + // XADD16rm, XCHG16rm + printi16mem(MI, 2, O); + return; + break; + case 14: + // XADD32rm, XCHG32rm + printi32mem(MI, 2, O); + return; + break; + case 15: + // XADD64rm, XCHG64rm + printi64mem(MI, 2, O); + return; + break; + case 16: + // XADD8rm, XCHG8rm + printi8mem(MI, 2, O); + return; + break; + } + +} + + + diff --git a/thirdparty/capstone/arch/X86/X86GenDisassemblerTables.inc b/thirdparty/capstone/arch/X86/X86GenDisassemblerTables.inc new file mode 100644 index 0000000..163cf0e --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenDisassemblerTables.inc @@ -0,0 +1,112961 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* * X86 Disassembler *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +static const struct OperandSpecifier x86OperandSets[][6] = { + { /* 0 */ + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 1 */ + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 2 */ + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 3 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 4 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 5 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 6 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 7 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 8 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 9 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 10 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 11 */ + { ENCODING_ID, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 12 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_ID, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 13 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 14 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_ID, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 15 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 16 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 17 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 18 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 19 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 20 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 21 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 22 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 23 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 24 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 25 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 26 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 27 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 28 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 29 */ + { ENCODING_FP, TYPE_ST }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 30 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 31 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 32 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 33 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 34 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 35 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 36 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 37 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 38 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_R16 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 39 */ + { ENCODING_RM, TYPE_R16 }, + { ENCODING_REG, TYPE_R16 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 40 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 41 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 42 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 43 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 44 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 45 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 46 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_ID, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 47 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_ID, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 48 */ + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 49 */ + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 50 */ + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 51 */ + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 52 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 53 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 54 */ + { ENCODING_REG, TYPE_BNDR }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 55 */ + { ENCODING_REG, TYPE_BNDR }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 56 */ + { ENCODING_REG, TYPE_BNDR }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 57 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_BNDR }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 58 */ + { ENCODING_REG, TYPE_BNDR }, + { ENCODING_RM, TYPE_BNDR }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 59 */ + { ENCODING_RM, TYPE_BNDR }, + { ENCODING_REG, TYPE_BNDR }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 60 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 61 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 62 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 63 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 64 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_Rv, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 65 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RO, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 66 */ + { ENCODING_RM, TYPE_Rv }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 67 */ + { ENCODING_RM, TYPE_Rv }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 68 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 69 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 70 */ + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 71 */ + { ENCODING_ID, TYPE_REL }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 72 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 73 */ + { ENCODING_IW, TYPE_REL }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 74 */ + { ENCODING_RM, TYPE_Rv }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 75 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_ID, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 76 */ + { ENCODING_RM, TYPE_R8 }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 77 */ + { ENCODING_REG, TYPE_R8 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 78 */ + { ENCODING_RM, TYPE_R8 }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 79 */ + { ENCODING_REG, TYPE_R8 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 80 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_IMM3 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 81 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_IMM3 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 82 */ + { ENCODING_DI, TYPE_DSTIDX }, + { ENCODING_SI, TYPE_SRCIDX }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 83 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 84 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 85 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 86 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 87 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 88 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 89 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 90 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 91 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 92 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 93 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 94 */ + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 95 */ + { ENCODING_IW, TYPE_IMM }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 96 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 97 */ + { ENCODING_RM, TYPE_R32 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 98 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 99 */ + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 100 */ + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_IW, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 101 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_M }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 102 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 103 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 104 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 105 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 106 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 107 */ + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 108 */ + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 109 */ + { ENCODING_DI, TYPE_DSTIDX }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 110 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 111 */ + { ENCODING_IB, TYPE_REL }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 112 */ + { ENCODING_Iv, TYPE_REL }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 113 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_VK }, + { ENCODING_RM, TYPE_VK }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 114 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM, TYPE_VK }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 115 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 116 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 117 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_VK }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 118 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_VK }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 119 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 120 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_VK }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 121 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM, TYPE_VK }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 122 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 123 */ + { ENCODING_RM, TYPE_R16 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 124 */ + { ENCODING_SI, TYPE_SRCIDX }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 125 */ + { ENCODING_IW, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 126 */ + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 127 */ + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 128 */ + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 129 */ + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 130 */ + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 131 */ + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 132 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_MM64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 133 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_MM64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 134 */ + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_RM, TYPE_MM64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 135 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 136 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 137 */ + { ENCODING_RM, TYPE_R32 }, + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 138 */ + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 139 */ + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 140 */ + { ENCODING_RM, TYPE_MM64 }, + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 141 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 142 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_RM, TYPE_MM64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 143 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 144 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_RM, TYPE_MM64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 145 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_MM64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 146 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 147 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_MM64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 148 */ + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 149 */ + { ENCODING_REG, TYPE_MM64 }, + { ENCODING_RM, TYPE_MM64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 150 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_MM64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 151 */ + { ENCODING_Ia, TYPE_MOFFS }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 152 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_SEGMENTREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 153 */ + { ENCODING_Rv, TYPE_Rv }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 154 */ + { ENCODING_RM, TYPE_Rv }, + { ENCODING_REG, TYPE_SEGMENTREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 155 */ + { ENCODING_REG, TYPE_SEGMENTREG }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 156 */ + { ENCODING_REG, TYPE_SEGMENTREG }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 157 */ + { ENCODING_REG, TYPE_CONTROLREG }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 158 */ + { ENCODING_REG, TYPE_DEBUGREG }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 159 */ + { ENCODING_RM, TYPE_R32 }, + { ENCODING_REG, TYPE_CONTROLREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 160 */ + { ENCODING_RM, TYPE_R32 }, + { ENCODING_REG, TYPE_DEBUGREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 161 */ + { ENCODING_REG, TYPE_CONTROLREG }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 162 */ + { ENCODING_REG, TYPE_DEBUGREG }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 163 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_CONTROLREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 164 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_DEBUGREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 165 */ + { ENCODING_RO, TYPE_R64 }, + { ENCODING_IO, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 166 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_SEGMENTREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 167 */ + { ENCODING_REG, TYPE_SEGMENTREG }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 168 */ + { ENCODING_RB, TYPE_R8 }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 169 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 170 */ + { ENCODING_RM, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 171 */ + { ENCODING_REG, TYPE_R16 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 172 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 173 */ + { ENCODING_RM, TYPE_R32 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 174 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 175 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 176 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 177 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_R16 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 178 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R16 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 179 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 180 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 181 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 182 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 183 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 184 */ + { ENCODING_Rv, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 185 */ + { ENCODING_RO, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 186 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 187 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 188 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 189 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 190 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 191 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 192 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 193 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 194 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 195 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 196 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 197 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 198 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 199 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 200 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 201 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 202 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 203 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 204 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 205 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 206 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 207 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 208 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 209 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 210 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 211 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 212 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 213 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 214 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 215 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 216 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 217 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 218 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 219 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 220 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 221 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 222 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 223 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 224 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 225 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 226 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 227 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 228 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 229 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 230 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 231 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + }, + { /* 232 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 233 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 234 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 235 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 236 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 237 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 238 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 239 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 240 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 241 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 242 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 243 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 244 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 245 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 246 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 247 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + }, + { /* 248 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 249 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 250 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 251 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 252 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 253 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_IRC, TYPE_IMM }, + }, + { /* 254 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 255 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 256 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 257 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 258 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 259 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_IRC, TYPE_IMM }, + }, + { /* 260 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 261 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 262 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 263 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 264 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 265 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 266 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 267 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 268 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 269 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 270 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 271 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 272 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 273 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 274 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 275 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 276 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 277 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 278 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 279 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 280 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 281 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 282 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 283 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 284 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 285 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 286 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 287 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 288 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 289 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 290 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 291 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 292 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 293 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 294 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 295 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 296 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 297 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 298 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 299 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 300 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 301 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 302 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_IB, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 303 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 304 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 305 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 306 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 307 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 308 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 309 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 310 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 311 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 312 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 313 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 314 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 315 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 316 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 317 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 318 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 319 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 320 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 321 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 322 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 323 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 324 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 325 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 326 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 327 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 328 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 329 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 330 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 331 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 332 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 333 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 334 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 335 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 336 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 337 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 338 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 339 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 340 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 341 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 342 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 343 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 344 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 345 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 346 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 347 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 348 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 349 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 350 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 351 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 352 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 353 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 354 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 355 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 356 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 357 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 358 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 359 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 360 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 361 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 362 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 363 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 364 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 365 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 366 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 367 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 368 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 369 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 370 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 371 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 372 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 373 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 374 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 375 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 376 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_IMM5 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 377 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 378 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 379 */ + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 380 */ + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 381 */ + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 382 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 383 */ + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 384 */ + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 385 */ + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 386 */ + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 387 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 388 */ + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 389 */ + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 390 */ + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 391 */ + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 392 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 393 */ + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 394 */ + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 395 */ + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 396 */ + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 397 */ + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 398 */ + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 399 */ + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 400 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 401 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 402 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 403 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 404 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 405 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 406 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 407 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 408 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 409 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 410 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 411 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 412 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 413 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 414 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 415 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 416 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 417 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 418 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 419 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 420 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 421 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 422 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 423 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 424 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 425 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 426 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 427 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 428 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 429 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 430 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 431 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 432 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 433 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 434 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 435 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 436 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 437 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 438 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 439 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 440 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 441 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 442 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 443 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 444 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 445 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 446 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 447 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 448 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 449 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 450 */ + { ENCODING_RM, TYPE_XMM }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 451 */ + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 452 */ + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 453 */ + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 454 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 455 */ + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 456 */ + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 457 */ + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 458 */ + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 459 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 460 */ + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 461 */ + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 462 */ + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 463 */ + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 464 */ + { ENCODING_RM_CD4, TYPE_YMM }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 465 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD4, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 466 */ + { ENCODING_RM_CD4, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 467 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 468 */ + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 469 */ + { ENCODING_RM, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 470 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_YMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 471 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_YMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 472 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_YMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 473 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 474 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 475 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 476 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 477 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 478 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 479 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 480 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_R32 }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 481 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 482 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 483 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_R64 }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 484 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 485 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 486 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 487 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 488 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 489 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 490 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 491 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 492 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 493 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 494 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 495 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 496 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 497 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 498 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 499 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 500 */ + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 501 */ + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 502 */ + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 503 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 504 */ + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 505 */ + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 506 */ + { ENCODING_RM_CD16, TYPE_R32 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 507 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 508 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 509 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 510 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 511 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 512 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 513 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 514 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 515 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 516 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 517 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 518 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 519 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 520 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 521 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 522 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 523 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 524 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 525 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 526 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 527 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 528 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 529 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 530 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 531 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 532 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 533 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 534 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 535 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 536 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 537 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 538 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 539 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 540 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 541 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 542 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 543 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 544 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 545 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 546 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 547 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_IRC, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 548 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_IB, TYPE_YMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 549 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_IB, TYPE_YMM }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 550 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_IB, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 551 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_IB, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 552 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 553 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 554 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 555 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 556 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 557 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 558 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 559 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 560 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 561 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 562 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 563 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 564 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 565 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 566 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 567 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 568 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 569 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 570 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 571 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 572 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP4 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VSIB, TYPE_MVSIBX }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 573 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD8, TYPE_MVSIBX }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 574 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD8, TYPE_MVSIBX }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 575 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD8, TYPE_MVSIBY }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 576 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP4 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VSIB, TYPE_MVSIBX }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 577 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP4 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VSIB, TYPE_MVSIBY }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 578 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD4, TYPE_MVSIBX }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 579 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD4, TYPE_MVSIBY }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 580 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD4, TYPE_MVSIBZ }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 581 */ + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD4, TYPE_MVSIBY }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 582 */ + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD4, TYPE_MVSIBZ }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 583 */ + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD8, TYPE_MVSIBZ }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 584 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD8, TYPE_MVSIBY }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 585 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD8, TYPE_MVSIBZ }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 586 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP4 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VSIB, TYPE_MVSIBY }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 587 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD4, TYPE_MVSIBY }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 588 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VSIB_CD4, TYPE_MVSIBZ }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 589 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 590 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 591 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 592 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 593 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 594 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 595 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 596 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 597 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 598 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 599 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 600 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 601 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 602 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 603 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 604 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 605 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 606 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 607 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 608 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 609 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 610 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 611 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 612 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 613 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 614 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 615 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 616 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 617 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 618 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 619 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 620 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 621 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 622 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 623 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 624 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 625 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 626 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 627 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 628 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 629 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 630 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 631 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 632 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 633 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 634 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 635 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 636 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 637 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 638 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 639 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 640 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 641 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 642 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 643 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 644 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 645 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 646 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 647 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 648 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 649 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 650 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 651 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 652 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 653 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 654 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 655 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 656 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 657 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 658 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 659 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + }, + { /* 660 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 661 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 662 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 663 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 664 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 665 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 666 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 667 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 668 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 669 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 670 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 671 */ + { ENCODING_RM, TYPE_YMM }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 672 */ + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 673 */ + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 674 */ + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 675 */ + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 676 */ + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 677 */ + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 678 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 679 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 680 */ + { ENCODING_RM_CD16, TYPE_R32 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 681 */ + { ENCODING_RM_CD16, TYPE_R64 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 682 */ + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 683 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 684 */ + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 685 */ + { ENCODING_RM, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 686 */ + { ENCODING_RM, TYPE_R32 }, + { ENCODING_REG, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 687 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 688 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 689 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 690 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 691 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 692 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 693 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 694 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 695 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 696 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 697 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 698 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 699 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 700 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 701 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 702 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 703 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_VK }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 704 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_VK }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 705 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_VK }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 706 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 707 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 708 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 709 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 710 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 711 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 712 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 713 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 714 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 715 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 716 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 717 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 718 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 719 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 720 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 721 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 722 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 723 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 724 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 725 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 726 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 727 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 728 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 729 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 730 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 731 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 732 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 733 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 734 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 735 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 736 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 737 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 738 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 739 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 740 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 741 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 742 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 743 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 744 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 745 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 746 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 747 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 748 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 749 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 750 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 751 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 752 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 753 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 754 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 755 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 756 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 757 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 758 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 759 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 760 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 761 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 762 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 763 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 764 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 765 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 766 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 767 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 768 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 769 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 770 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_AVX512ICC }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 771 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_IMM3 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 772 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_IMM3 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 773 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 774 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 775 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 776 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 777 */ + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 778 */ + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 779 */ + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 780 */ + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 781 */ + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 782 */ + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 783 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 784 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_IB, TYPE_YMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 785 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_IB, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 786 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_IB, TYPE_YMM }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 787 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 788 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_IB, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 789 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 790 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_IB, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 791 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 792 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 793 */ + { ENCODING_RM_CD16, TYPE_R64 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 794 */ + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 795 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 796 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_R32 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 797 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 798 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_R64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 799 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 800 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD2, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 801 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 802 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 803 */ + { ENCODING_REG, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 804 */ + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 805 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 806 */ + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 807 */ + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 808 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 809 */ + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 810 */ + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 811 */ + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 812 */ + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 813 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 814 */ + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 815 */ + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 816 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 817 */ + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 818 */ + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 819 */ + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 820 */ + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 821 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 822 */ + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 823 */ + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 824 */ + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 825 */ + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 826 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 827 */ + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 828 */ + { ENCODING_RM_CD2, TYPE_XMM }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 829 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD2, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 830 */ + { ENCODING_RM_CD2, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 831 */ + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 832 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 833 */ + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 834 */ + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 835 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 836 */ + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 837 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 838 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 839 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 840 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 841 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 842 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 843 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 844 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 845 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM_CD2, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 846 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD2, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 847 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD2, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 848 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 849 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 850 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 851 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 852 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 853 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 854 */ + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 855 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 856 */ + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 857 */ + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 858 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 859 */ + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 860 */ + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 861 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 862 */ + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 863 */ + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 864 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 865 */ + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 866 */ + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 867 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 868 */ + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 869 */ + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 870 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 871 */ + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD32, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 872 */ + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 873 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 874 */ + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD4, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 875 */ + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 876 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 877 */ + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 878 */ + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 879 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 880 */ + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD64, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 881 */ + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 882 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 883 */ + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 884 */ + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 885 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 886 */ + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 887 */ + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 888 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 889 */ + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_RM_CD8, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 890 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_M }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 891 */ + { ENCODING_REG, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 892 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_VSIB_CD4, TYPE_MVSIBX }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 893 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_VSIB_CD4, TYPE_MVSIBY }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 894 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_VSIB_CD4, TYPE_MVSIBZ }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 895 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_VSIB_CD8, TYPE_MVSIBX }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 896 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_VSIB_CD8, TYPE_MVSIBX }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 897 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_VSIB_CD8, TYPE_MVSIBY }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 898 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_VSIB_CD4, TYPE_MVSIBY }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 899 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_VSIB_CD4, TYPE_MVSIBZ }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 900 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_VSIB_CD8, TYPE_MVSIBY }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 901 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_VSIB_CD8, TYPE_MVSIBZ }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 902 */ + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_YMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 903 */ + { ENCODING_VVVV, TYPE_XMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 904 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 905 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 906 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 907 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 908 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 909 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 910 */ + { ENCODING_REG, TYPE_YMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_YMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 911 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 912 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD16, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 913 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 914 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 915 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD16, TYPE_XMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 916 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 917 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD8, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 918 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 919 */ + { ENCODING_REG, TYPE_ZMM }, + { ENCODING_WRITEMASK, TYPE_VK }, + { ENCODING_VVVV, TYPE_ZMM }, + { ENCODING_RM_CD4, TYPE_ZMM }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 920 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 921 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 922 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 923 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 924 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 925 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, +}; + +static const struct InstructionSpecifier x86DisassemblerInstrSpecifiers[15285] = { + { /* 0 */ + 0, + /* */ + }, + { /* 1 */ + 0, + /* */ + }, + { /* 2 */ + 0, + /* */ + }, + { /* 3 */ + 0, + /* */ + }, + { /* 4 */ + 0, + /* */ + }, + { /* 5 */ + 0, + /* */ + }, + { /* 6 */ + 0, + /* */ + }, + { /* 7 */ + 0, + /* */ + }, + { /* 8 */ + 0, + /* */ + }, + { /* 9 */ + 0, + /* */ + }, + { /* 10 */ + 0, + /* */ + }, + { /* 11 */ + 0, + /* */ + }, + { /* 12 */ + 0, + /* */ + }, + { /* 13 */ + 0, + /* */ + }, + { /* 14 */ + 0, + /* */ + }, + { /* 15 */ + 0, + /* */ + }, + { /* 16 */ + 0, + /* */ + }, + { /* 17 */ + 0, + /* */ + }, + { /* 18 */ + 0, + /* */ + }, + { /* 19 */ + 0, + /* */ + }, + { /* 20 */ + 0, + /* */ + }, + { /* 21 */ + 0, + /* */ + }, + { /* 22 */ + 0, + /* */ + }, + { /* 23 */ + 0, + /* */ + }, + { /* 24 */ + 0, + /* */ + }, + { /* 25 */ + 0, + /* */ + }, + { /* 26 */ + 0, + /* */ + }, + { /* 27 */ + 0, + /* */ + }, + { /* 28 */ + 0, + /* */ + }, + { /* 29 */ + 0, + /* */ + }, + { /* 30 */ + 0, + /* */ + }, + { /* 31 */ + 0, + /* */ + }, + { /* 32 */ + 0, + /* */ + }, + { /* 33 */ + 0, + /* */ + }, + { /* 34 */ + 0, + /* */ + }, + { /* 35 */ + 0, + /* */ + }, + { /* 36 */ + 0, + /* */ + }, + { /* 37 */ + 0, + /* */ + }, + { /* 38 */ + 0, + /* */ + }, + { /* 39 */ + 0, + /* */ + }, + { /* 40 */ + 0, + /* */ + }, + { /* 41 */ + 0, + /* */ + }, + { /* 42 */ + 0, + /* */ + }, + { /* 43 */ + 0, + /* */ + }, + { /* 44 */ + 0, + /* */ + }, + { /* 45 */ + 0, + /* */ + }, + { /* 46 */ + 0, + /* */ + }, + { /* 47 */ + 0, + /* */ + }, + { /* 48 */ + 0, + /* */ + }, + { /* 49 */ + 0, + /* */ + }, + { /* 50 */ + 0, + /* */ + }, + { /* 51 */ + 0, + /* */ + }, + { /* 52 */ + 0, + /* */ + }, + { /* 53 */ + 0, + /* */ + }, + { /* 54 */ + 0, + /* */ + }, + { /* 55 */ + 0, + /* */ + }, + { /* 56 */ + 0, + /* */ + }, + { /* 57 */ + 0, + /* */ + }, + { /* 58 */ + 0, + /* */ + }, + { /* 59 */ + 0, + /* */ + }, + { /* 60 */ + 0, + /* */ + }, + { /* 61 */ + 0, + /* */ + }, + { /* 62 */ + 0, + /* */ + }, + { /* 63 */ + 0, + /* */ + }, + { /* 64 */ + 0, + /* */ + }, + { /* 65 */ + 0, + /* */ + }, + { /* 66 */ + 0, + /* */ + }, + { /* 67 */ + 0, + /* */ + }, + { /* 68 */ + 0, + /* */ + }, + { /* 69 */ + 0, + /* */ + }, + { /* 70 */ + 0, + /* */ + }, + { /* 71 */ + 0, + /* */ + }, + { /* 72 */ + 0, + /* */ + }, + { /* 73 */ + 0, + /* */ + }, + { /* 74 */ + 0, + /* */ + }, + { /* 75 */ + 0, + /* */ + }, + { /* 76 */ + 0, + /* */ + }, + { /* 77 */ + 0, + /* */ + }, + { /* 78 */ + 0, + /* */ + }, + { /* 79 */ + 0, + /* */ + }, + { /* 80 */ + 0, + /* */ + }, + { /* 81 */ + 0, + /* */ + }, + { /* 82 */ + 0, + /* */ + }, + { /* 83 */ + 0, + /* */ + }, + { /* 84 */ + 0, + /* */ + }, + { /* 85 */ + 0, + /* */ + }, + { /* 86 */ + 0, + /* */ + }, + { /* 87 */ + 0, + /* */ + }, + { /* 88 */ + 0, + /* */ + }, + { /* 89 */ + 0, + /* */ + }, + { /* 90 */ + 0, + /* */ + }, + { /* 91 */ + 0, + /* */ + }, + { /* 92 */ + 0, + /* */ + }, + { /* 93 */ + 0, + /* */ + }, + { /* 94 */ + 0, + /* */ + }, + { /* 95 */ + 0, + /* */ + }, + { /* 96 */ + 0, + /* */ + }, + { /* 97 */ + 0, + /* */ + }, + { /* 98 */ + 0, + /* */ + }, + { /* 99 */ + 0, + /* */ + }, + { /* 100 */ + 0, + /* */ + }, + { /* 101 */ + 0, + /* */ + }, + { /* 102 */ + 0, + /* */ + }, + { /* 103 */ + 0, + /* */ + }, + { /* 104 */ + 0, + /* */ + }, + { /* 105 */ + 0, + /* */ + }, + { /* 106 */ + 0, + /* */ + }, + { /* 107 */ + 0, + /* */ + }, + { /* 108 */ + 0, + /* */ + }, + { /* 109 */ + 0, + /* */ + }, + { /* 110 */ + 0, + /* */ + }, + { /* 111 */ + 0, + /* */ + }, + { /* 112 */ + 0, + /* */ + }, + { /* 113 */ + 0, + /* */ + }, + { /* 114 */ + 0, + /* */ + }, + { /* 115 */ + 0, + /* */ + }, + { /* 116 */ + 0, + /* */ + }, + { /* 117 */ + 0, + /* */ + }, + { /* 118 */ + 0, + /* */ + }, + { /* 119 */ + 0, + /* */ + }, + { /* 120 */ + 0, + /* */ + }, + { /* 121 */ + 0, + /* */ + }, + { /* 122 */ + 0, + /* */ + }, + { /* 123 */ + 0, + /* */ + }, + { /* 124 */ + 0, + /* */ + }, + { /* 125 */ + 0, + /* */ + }, + { /* 126 */ + 0, + /* */ + }, + { /* 127 */ + 0, + /* */ + }, + { /* 128 */ + 0, + /* */ + }, + { /* 129 */ + 0, + /* */ + }, + { /* 130 */ + 0, + /* */ + }, + { /* 131 */ + 0, + /* */ + }, + { /* 132 */ + 0, + /* */ + }, + { /* 133 */ + 0, + /* */ + }, + { /* 134 */ + 0, + /* */ + }, + { /* 135 */ + 0, + /* */ + }, + { /* 136 */ + 0, + /* */ + }, + { /* 137 */ + 0, + /* */ + }, + { /* 138 */ + 0, + /* */ + }, + { /* 139 */ + 0, + /* */ + }, + { /* 140 */ + 0, + /* */ + }, + { /* 141 */ + 0, + /* */ + }, + { /* 142 */ + 0, + /* */ + }, + { /* 143 */ + 0, + /* */ + }, + { /* 144 */ + 0, + /* */ + }, + { /* 145 */ + 0, + /* */ + }, + { /* 146 */ + 0, + /* AAA */ + }, + { /* 147 */ + 1, + /* AAD8i8 */ + }, + { /* 148 */ + 1, + /* AAM8i8 */ + }, + { /* 149 */ + 0, + /* AAS */ + }, + { /* 150 */ + 0, + /* ABS_F */ + }, + { /* 151 */ + 0, + /* */ + }, + { /* 152 */ + 0, + /* */ + }, + { /* 153 */ + 0, + /* */ + }, + { /* 154 */ + 2, + /* ADC16i16 */ + }, + { /* 155 */ + 3, + /* ADC16mi */ + }, + { /* 156 */ + 4, + /* ADC16mi8 */ + }, + { /* 157 */ + 5, + /* ADC16mr */ + }, + { /* 158 */ + 6, + /* ADC16ri */ + }, + { /* 159 */ + 7, + /* ADC16ri8 */ + }, + { /* 160 */ + 8, + /* ADC16rm */ + }, + { /* 161 */ + 9, + /* ADC16rr */ + }, + { /* 162 */ + 10, + /* ADC16rr_REV */ + }, + { /* 163 */ + 2, + /* ADC32i32 */ + }, + { /* 164 */ + 3, + /* ADC32mi */ + }, + { /* 165 */ + 4, + /* ADC32mi8 */ + }, + { /* 166 */ + 5, + /* ADC32mr */ + }, + { /* 167 */ + 6, + /* ADC32ri */ + }, + { /* 168 */ + 7, + /* ADC32ri8 */ + }, + { /* 169 */ + 8, + /* ADC32rm */ + }, + { /* 170 */ + 9, + /* ADC32rr */ + }, + { /* 171 */ + 10, + /* ADC32rr_REV */ + }, + { /* 172 */ + 11, + /* ADC64i32 */ + }, + { /* 173 */ + 12, + /* ADC64mi32 */ + }, + { /* 174 */ + 4, + /* ADC64mi8 */ + }, + { /* 175 */ + 13, + /* ADC64mr */ + }, + { /* 176 */ + 14, + /* ADC64ri32 */ + }, + { /* 177 */ + 15, + /* ADC64ri8 */ + }, + { /* 178 */ + 16, + /* ADC64rm */ + }, + { /* 179 */ + 17, + /* ADC64rr */ + }, + { /* 180 */ + 18, + /* ADC64rr_REV */ + }, + { /* 181 */ + 1, + /* ADC8i8 */ + }, + { /* 182 */ + 4, + /* ADC8mi */ + }, + { /* 183 */ + 4, + /* ADC8mi8 */ + }, + { /* 184 */ + 19, + /* ADC8mr */ + }, + { /* 185 */ + 20, + /* ADC8ri */ + }, + { /* 186 */ + 20, + /* ADC8ri8 */ + }, + { /* 187 */ + 21, + /* ADC8rm */ + }, + { /* 188 */ + 22, + /* ADC8rr */ + }, + { /* 189 */ + 23, + /* ADC8rr_REV */ + }, + { /* 190 */ + 24, + /* ADCX32rm */ + }, + { /* 191 */ + 25, + /* ADCX32rr */ + }, + { /* 192 */ + 16, + /* ADCX64rm */ + }, + { /* 193 */ + 18, + /* ADCX64rr */ + }, + { /* 194 */ + 2, + /* ADD16i16 */ + }, + { /* 195 */ + 3, + /* ADD16mi */ + }, + { /* 196 */ + 4, + /* ADD16mi8 */ + }, + { /* 197 */ + 5, + /* ADD16mr */ + }, + { /* 198 */ + 6, + /* ADD16ri */ + }, + { /* 199 */ + 7, + /* ADD16ri8 */ + }, + { /* 200 */ + 8, + /* ADD16rm */ + }, + { /* 201 */ + 9, + /* ADD16rr */ + }, + { /* 202 */ + 10, + /* ADD16rr_REV */ + }, + { /* 203 */ + 2, + /* ADD32i32 */ + }, + { /* 204 */ + 3, + /* ADD32mi */ + }, + { /* 205 */ + 4, + /* ADD32mi8 */ + }, + { /* 206 */ + 5, + /* ADD32mr */ + }, + { /* 207 */ + 6, + /* ADD32ri */ + }, + { /* 208 */ + 7, + /* ADD32ri8 */ + }, + { /* 209 */ + 8, + /* ADD32rm */ + }, + { /* 210 */ + 9, + /* ADD32rr */ + }, + { /* 211 */ + 10, + /* ADD32rr_REV */ + }, + { /* 212 */ + 11, + /* ADD64i32 */ + }, + { /* 213 */ + 12, + /* ADD64mi32 */ + }, + { /* 214 */ + 4, + /* ADD64mi8 */ + }, + { /* 215 */ + 13, + /* ADD64mr */ + }, + { /* 216 */ + 14, + /* ADD64ri32 */ + }, + { /* 217 */ + 15, + /* ADD64ri8 */ + }, + { /* 218 */ + 16, + /* ADD64rm */ + }, + { /* 219 */ + 17, + /* ADD64rr */ + }, + { /* 220 */ + 18, + /* ADD64rr_REV */ + }, + { /* 221 */ + 1, + /* ADD8i8 */ + }, + { /* 222 */ + 4, + /* ADD8mi */ + }, + { /* 223 */ + 4, + /* ADD8mi8 */ + }, + { /* 224 */ + 19, + /* ADD8mr */ + }, + { /* 225 */ + 20, + /* ADD8ri */ + }, + { /* 226 */ + 20, + /* ADD8ri8 */ + }, + { /* 227 */ + 21, + /* ADD8rm */ + }, + { /* 228 */ + 22, + /* ADD8rr */ + }, + { /* 229 */ + 23, + /* ADD8rr_REV */ + }, + { /* 230 */ + 26, + /* ADDPDrm */ + }, + { /* 231 */ + 27, + /* ADDPDrr */ + }, + { /* 232 */ + 26, + /* ADDPSrm */ + }, + { /* 233 */ + 27, + /* ADDPSrr */ + }, + { /* 234 */ + 26, + /* ADDSDrm */ + }, + { /* 235 */ + 0, + /* */ + }, + { /* 236 */ + 27, + /* ADDSDrr */ + }, + { /* 237 */ + 0, + /* */ + }, + { /* 238 */ + 26, + /* ADDSSrm */ + }, + { /* 239 */ + 0, + /* */ + }, + { /* 240 */ + 27, + /* ADDSSrr */ + }, + { /* 241 */ + 0, + /* */ + }, + { /* 242 */ + 26, + /* ADDSUBPDrm */ + }, + { /* 243 */ + 27, + /* ADDSUBPDrr */ + }, + { /* 244 */ + 26, + /* ADDSUBPSrm */ + }, + { /* 245 */ + 27, + /* ADDSUBPSrr */ + }, + { /* 246 */ + 28, + /* ADD_F32m */ + }, + { /* 247 */ + 28, + /* ADD_F64m */ + }, + { /* 248 */ + 28, + /* ADD_FI16m */ + }, + { /* 249 */ + 28, + /* ADD_FI32m */ + }, + { /* 250 */ + 29, + /* ADD_FPrST0 */ + }, + { /* 251 */ + 29, + /* ADD_FST0r */ + }, + { /* 252 */ + 0, + /* */ + }, + { /* 253 */ + 0, + /* */ + }, + { /* 254 */ + 0, + /* */ + }, + { /* 255 */ + 0, + /* */ + }, + { /* 256 */ + 0, + /* */ + }, + { /* 257 */ + 0, + /* */ + }, + { /* 258 */ + 0, + /* */ + }, + { /* 259 */ + 0, + /* */ + }, + { /* 260 */ + 0, + /* */ + }, + { /* 261 */ + 0, + /* */ + }, + { /* 262 */ + 0, + /* */ + }, + { /* 263 */ + 0, + /* */ + }, + { /* 264 */ + 0, + /* */ + }, + { /* 265 */ + 0, + /* */ + }, + { /* 266 */ + 29, + /* ADD_FrST0 */ + }, + { /* 267 */ + 24, + /* ADOX32rm */ + }, + { /* 268 */ + 25, + /* ADOX32rr */ + }, + { /* 269 */ + 16, + /* ADOX64rm */ + }, + { /* 270 */ + 18, + /* ADOX64rr */ + }, + { /* 271 */ + 26, + /* AESDECLASTrm */ + }, + { /* 272 */ + 27, + /* AESDECLASTrr */ + }, + { /* 273 */ + 26, + /* AESDECrm */ + }, + { /* 274 */ + 27, + /* AESDECrr */ + }, + { /* 275 */ + 26, + /* AESENCLASTrm */ + }, + { /* 276 */ + 27, + /* AESENCLASTrr */ + }, + { /* 277 */ + 26, + /* AESENCrm */ + }, + { /* 278 */ + 27, + /* AESENCrr */ + }, + { /* 279 */ + 30, + /* AESIMCrm */ + }, + { /* 280 */ + 31, + /* AESIMCrr */ + }, + { /* 281 */ + 32, + /* AESKEYGENASSIST128rm */ + }, + { /* 282 */ + 33, + /* AESKEYGENASSIST128rr */ + }, + { /* 283 */ + 2, + /* AND16i16 */ + }, + { /* 284 */ + 3, + /* AND16mi */ + }, + { /* 285 */ + 4, + /* AND16mi8 */ + }, + { /* 286 */ + 5, + /* AND16mr */ + }, + { /* 287 */ + 6, + /* AND16ri */ + }, + { /* 288 */ + 7, + /* AND16ri8 */ + }, + { /* 289 */ + 8, + /* AND16rm */ + }, + { /* 290 */ + 9, + /* AND16rr */ + }, + { /* 291 */ + 10, + /* AND16rr_REV */ + }, + { /* 292 */ + 2, + /* AND32i32 */ + }, + { /* 293 */ + 3, + /* AND32mi */ + }, + { /* 294 */ + 4, + /* AND32mi8 */ + }, + { /* 295 */ + 5, + /* AND32mr */ + }, + { /* 296 */ + 6, + /* AND32ri */ + }, + { /* 297 */ + 7, + /* AND32ri8 */ + }, + { /* 298 */ + 8, + /* AND32rm */ + }, + { /* 299 */ + 9, + /* AND32rr */ + }, + { /* 300 */ + 10, + /* AND32rr_REV */ + }, + { /* 301 */ + 11, + /* AND64i32 */ + }, + { /* 302 */ + 12, + /* AND64mi32 */ + }, + { /* 303 */ + 4, + /* AND64mi8 */ + }, + { /* 304 */ + 13, + /* AND64mr */ + }, + { /* 305 */ + 14, + /* AND64ri32 */ + }, + { /* 306 */ + 15, + /* AND64ri8 */ + }, + { /* 307 */ + 16, + /* AND64rm */ + }, + { /* 308 */ + 17, + /* AND64rr */ + }, + { /* 309 */ + 18, + /* AND64rr_REV */ + }, + { /* 310 */ + 1, + /* AND8i8 */ + }, + { /* 311 */ + 4, + /* AND8mi */ + }, + { /* 312 */ + 4, + /* AND8mi8 */ + }, + { /* 313 */ + 19, + /* AND8mr */ + }, + { /* 314 */ + 20, + /* AND8ri */ + }, + { /* 315 */ + 20, + /* AND8ri8 */ + }, + { /* 316 */ + 21, + /* AND8rm */ + }, + { /* 317 */ + 22, + /* AND8rr */ + }, + { /* 318 */ + 23, + /* AND8rr_REV */ + }, + { /* 319 */ + 34, + /* ANDN32rm */ + }, + { /* 320 */ + 35, + /* ANDN32rr */ + }, + { /* 321 */ + 36, + /* ANDN64rm */ + }, + { /* 322 */ + 37, + /* ANDN64rr */ + }, + { /* 323 */ + 26, + /* ANDNPDrm */ + }, + { /* 324 */ + 27, + /* ANDNPDrr */ + }, + { /* 325 */ + 26, + /* ANDNPSrm */ + }, + { /* 326 */ + 27, + /* ANDNPSrr */ + }, + { /* 327 */ + 26, + /* ANDPDrm */ + }, + { /* 328 */ + 27, + /* ANDPDrr */ + }, + { /* 329 */ + 26, + /* ANDPSrm */ + }, + { /* 330 */ + 27, + /* ANDPSrr */ + }, + { /* 331 */ + 38, + /* ARPL16mr */ + }, + { /* 332 */ + 39, + /* ARPL16rr */ + }, + { /* 333 */ + 40, + /* BEXTR32rm */ + }, + { /* 334 */ + 41, + /* BEXTR32rr */ + }, + { /* 335 */ + 42, + /* BEXTR64rm */ + }, + { /* 336 */ + 43, + /* BEXTR64rr */ + }, + { /* 337 */ + 44, + /* BEXTRI32mi */ + }, + { /* 338 */ + 45, + /* BEXTRI32ri */ + }, + { /* 339 */ + 46, + /* BEXTRI64mi */ + }, + { /* 340 */ + 47, + /* BEXTRI64ri */ + }, + { /* 341 */ + 48, + /* BLCFILL32rm */ + }, + { /* 342 */ + 49, + /* BLCFILL32rr */ + }, + { /* 343 */ + 50, + /* BLCFILL64rm */ + }, + { /* 344 */ + 51, + /* BLCFILL64rr */ + }, + { /* 345 */ + 48, + /* BLCI32rm */ + }, + { /* 346 */ + 49, + /* BLCI32rr */ + }, + { /* 347 */ + 50, + /* BLCI64rm */ + }, + { /* 348 */ + 51, + /* BLCI64rr */ + }, + { /* 349 */ + 48, + /* BLCIC32rm */ + }, + { /* 350 */ + 49, + /* BLCIC32rr */ + }, + { /* 351 */ + 50, + /* BLCIC64rm */ + }, + { /* 352 */ + 51, + /* BLCIC64rr */ + }, + { /* 353 */ + 48, + /* BLCMSK32rm */ + }, + { /* 354 */ + 49, + /* BLCMSK32rr */ + }, + { /* 355 */ + 50, + /* BLCMSK64rm */ + }, + { /* 356 */ + 51, + /* BLCMSK64rr */ + }, + { /* 357 */ + 48, + /* BLCS32rm */ + }, + { /* 358 */ + 49, + /* BLCS32rr */ + }, + { /* 359 */ + 50, + /* BLCS64rm */ + }, + { /* 360 */ + 51, + /* BLCS64rr */ + }, + { /* 361 */ + 52, + /* BLENDPDrmi */ + }, + { /* 362 */ + 53, + /* BLENDPDrri */ + }, + { /* 363 */ + 52, + /* BLENDPSrmi */ + }, + { /* 364 */ + 53, + /* BLENDPSrri */ + }, + { /* 365 */ + 26, + /* BLENDVPDrm0 */ + }, + { /* 366 */ + 27, + /* BLENDVPDrr0 */ + }, + { /* 367 */ + 26, + /* BLENDVPSrm0 */ + }, + { /* 368 */ + 27, + /* BLENDVPSrr0 */ + }, + { /* 369 */ + 48, + /* BLSFILL32rm */ + }, + { /* 370 */ + 49, + /* BLSFILL32rr */ + }, + { /* 371 */ + 50, + /* BLSFILL64rm */ + }, + { /* 372 */ + 51, + /* BLSFILL64rr */ + }, + { /* 373 */ + 48, + /* BLSI32rm */ + }, + { /* 374 */ + 49, + /* BLSI32rr */ + }, + { /* 375 */ + 50, + /* BLSI64rm */ + }, + { /* 376 */ + 51, + /* BLSI64rr */ + }, + { /* 377 */ + 48, + /* BLSIC32rm */ + }, + { /* 378 */ + 49, + /* BLSIC32rr */ + }, + { /* 379 */ + 50, + /* BLSIC64rm */ + }, + { /* 380 */ + 51, + /* BLSIC64rr */ + }, + { /* 381 */ + 48, + /* BLSMSK32rm */ + }, + { /* 382 */ + 49, + /* BLSMSK32rr */ + }, + { /* 383 */ + 50, + /* BLSMSK64rm */ + }, + { /* 384 */ + 51, + /* BLSMSK64rr */ + }, + { /* 385 */ + 48, + /* BLSR32rm */ + }, + { /* 386 */ + 49, + /* BLSR32rr */ + }, + { /* 387 */ + 50, + /* BLSR64rm */ + }, + { /* 388 */ + 51, + /* BLSR64rr */ + }, + { /* 389 */ + 54, + /* BNDCL32rm */ + }, + { /* 390 */ + 55, + /* BNDCL32rr */ + }, + { /* 391 */ + 54, + /* BNDCL64rm */ + }, + { /* 392 */ + 56, + /* BNDCL64rr */ + }, + { /* 393 */ + 54, + /* BNDCN32rm */ + }, + { /* 394 */ + 55, + /* BNDCN32rr */ + }, + { /* 395 */ + 54, + /* BNDCN64rm */ + }, + { /* 396 */ + 56, + /* BNDCN64rr */ + }, + { /* 397 */ + 54, + /* BNDCU32rm */ + }, + { /* 398 */ + 55, + /* BNDCU32rr */ + }, + { /* 399 */ + 54, + /* BNDCU64rm */ + }, + { /* 400 */ + 56, + /* BNDCU64rr */ + }, + { /* 401 */ + 54, + /* BNDLDXrm */ + }, + { /* 402 */ + 54, + /* BNDMK32rm */ + }, + { /* 403 */ + 54, + /* BNDMK64rm */ + }, + { /* 404 */ + 57, + /* BNDMOV32mr */ + }, + { /* 405 */ + 54, + /* BNDMOV32rm */ + }, + { /* 406 */ + 57, + /* BNDMOV64mr */ + }, + { /* 407 */ + 54, + /* BNDMOV64rm */ + }, + { /* 408 */ + 58, + /* BNDMOVrr */ + }, + { /* 409 */ + 59, + /* BNDMOVrr_REV */ + }, + { /* 410 */ + 57, + /* BNDSTXmr */ + }, + { /* 411 */ + 60, + /* BOUNDS16rm */ + }, + { /* 412 */ + 60, + /* BOUNDS32rm */ + }, + { /* 413 */ + 60, + /* BSF16rm */ + }, + { /* 414 */ + 61, + /* BSF16rr */ + }, + { /* 415 */ + 60, + /* BSF32rm */ + }, + { /* 416 */ + 61, + /* BSF32rr */ + }, + { /* 417 */ + 62, + /* BSF64rm */ + }, + { /* 418 */ + 63, + /* BSF64rr */ + }, + { /* 419 */ + 60, + /* BSR16rm */ + }, + { /* 420 */ + 61, + /* BSR16rr */ + }, + { /* 421 */ + 60, + /* BSR32rm */ + }, + { /* 422 */ + 61, + /* BSR32rr */ + }, + { /* 423 */ + 62, + /* BSR64rm */ + }, + { /* 424 */ + 63, + /* BSR64rr */ + }, + { /* 425 */ + 64, + /* BSWAP16r_BAD */ + }, + { /* 426 */ + 64, + /* BSWAP32r */ + }, + { /* 427 */ + 65, + /* BSWAP64r */ + }, + { /* 428 */ + 4, + /* BT16mi8 */ + }, + { /* 429 */ + 5, + /* BT16mr */ + }, + { /* 430 */ + 66, + /* BT16ri8 */ + }, + { /* 431 */ + 67, + /* BT16rr */ + }, + { /* 432 */ + 4, + /* BT32mi8 */ + }, + { /* 433 */ + 5, + /* BT32mr */ + }, + { /* 434 */ + 66, + /* BT32ri8 */ + }, + { /* 435 */ + 67, + /* BT32rr */ + }, + { /* 436 */ + 4, + /* BT64mi8 */ + }, + { /* 437 */ + 13, + /* BT64mr */ + }, + { /* 438 */ + 68, + /* BT64ri8 */ + }, + { /* 439 */ + 69, + /* BT64rr */ + }, + { /* 440 */ + 4, + /* BTC16mi8 */ + }, + { /* 441 */ + 5, + /* BTC16mr */ + }, + { /* 442 */ + 7, + /* BTC16ri8 */ + }, + { /* 443 */ + 9, + /* BTC16rr */ + }, + { /* 444 */ + 4, + /* BTC32mi8 */ + }, + { /* 445 */ + 5, + /* BTC32mr */ + }, + { /* 446 */ + 7, + /* BTC32ri8 */ + }, + { /* 447 */ + 9, + /* BTC32rr */ + }, + { /* 448 */ + 4, + /* BTC64mi8 */ + }, + { /* 449 */ + 13, + /* BTC64mr */ + }, + { /* 450 */ + 15, + /* BTC64ri8 */ + }, + { /* 451 */ + 17, + /* BTC64rr */ + }, + { /* 452 */ + 4, + /* BTR16mi8 */ + }, + { /* 453 */ + 5, + /* BTR16mr */ + }, + { /* 454 */ + 7, + /* BTR16ri8 */ + }, + { /* 455 */ + 9, + /* BTR16rr */ + }, + { /* 456 */ + 4, + /* BTR32mi8 */ + }, + { /* 457 */ + 5, + /* BTR32mr */ + }, + { /* 458 */ + 7, + /* BTR32ri8 */ + }, + { /* 459 */ + 9, + /* BTR32rr */ + }, + { /* 460 */ + 4, + /* BTR64mi8 */ + }, + { /* 461 */ + 13, + /* BTR64mr */ + }, + { /* 462 */ + 15, + /* BTR64ri8 */ + }, + { /* 463 */ + 17, + /* BTR64rr */ + }, + { /* 464 */ + 4, + /* BTS16mi8 */ + }, + { /* 465 */ + 5, + /* BTS16mr */ + }, + { /* 466 */ + 7, + /* BTS16ri8 */ + }, + { /* 467 */ + 9, + /* BTS16rr */ + }, + { /* 468 */ + 4, + /* BTS32mi8 */ + }, + { /* 469 */ + 5, + /* BTS32mr */ + }, + { /* 470 */ + 7, + /* BTS32ri8 */ + }, + { /* 471 */ + 9, + /* BTS32rr */ + }, + { /* 472 */ + 4, + /* BTS64mi8 */ + }, + { /* 473 */ + 13, + /* BTS64mr */ + }, + { /* 474 */ + 15, + /* BTS64ri8 */ + }, + { /* 475 */ + 17, + /* BTS64rr */ + }, + { /* 476 */ + 40, + /* BZHI32rm */ + }, + { /* 477 */ + 41, + /* BZHI32rr */ + }, + { /* 478 */ + 42, + /* BZHI64rm */ + }, + { /* 479 */ + 43, + /* BZHI64rr */ + }, + { /* 480 */ + 28, + /* CALL16m */ + }, + { /* 481 */ + 0, + /* */ + }, + { /* 482 */ + 70, + /* CALL16r */ + }, + { /* 483 */ + 0, + /* */ + }, + { /* 484 */ + 28, + /* CALL32m */ + }, + { /* 485 */ + 0, + /* */ + }, + { /* 486 */ + 70, + /* CALL32r */ + }, + { /* 487 */ + 0, + /* */ + }, + { /* 488 */ + 28, + /* CALL64m */ + }, + { /* 489 */ + 0, + /* */ + }, + { /* 490 */ + 71, + /* CALL64pcrel32 */ + }, + { /* 491 */ + 72, + /* CALL64r */ + }, + { /* 492 */ + 0, + /* */ + }, + { /* 493 */ + 73, + /* CALLpcrel16 */ + }, + { /* 494 */ + 71, + /* CALLpcrel32 */ + }, + { /* 495 */ + 0, + /* CBW */ + }, + { /* 496 */ + 0, + /* CDQ */ + }, + { /* 497 */ + 0, + /* CDQE */ + }, + { /* 498 */ + 0, + /* CHS_F */ + }, + { /* 499 */ + 0, + /* */ + }, + { /* 500 */ + 0, + /* */ + }, + { /* 501 */ + 0, + /* */ + }, + { /* 502 */ + 0, + /* CLAC */ + }, + { /* 503 */ + 0, + /* CLC */ + }, + { /* 504 */ + 0, + /* CLD */ + }, + { /* 505 */ + 28, + /* CLDEMOTE */ + }, + { /* 506 */ + 28, + /* CLFLUSH */ + }, + { /* 507 */ + 28, + /* CLFLUSHOPT */ + }, + { /* 508 */ + 0, + /* CLGI */ + }, + { /* 509 */ + 0, + /* CLI */ + }, + { /* 510 */ + 28, + /* CLRSSBSY */ + }, + { /* 511 */ + 0, + /* CLTS */ + }, + { /* 512 */ + 28, + /* CLWB */ + }, + { /* 513 */ + 0, + /* CLZEROr */ + }, + { /* 514 */ + 0, + /* CMC */ + }, + { /* 515 */ + 8, + /* CMOVA16rm */ + }, + { /* 516 */ + 10, + /* CMOVA16rr */ + }, + { /* 517 */ + 8, + /* CMOVA32rm */ + }, + { /* 518 */ + 10, + /* CMOVA32rr */ + }, + { /* 519 */ + 16, + /* CMOVA64rm */ + }, + { /* 520 */ + 18, + /* CMOVA64rr */ + }, + { /* 521 */ + 8, + /* CMOVAE16rm */ + }, + { /* 522 */ + 10, + /* CMOVAE16rr */ + }, + { /* 523 */ + 8, + /* CMOVAE32rm */ + }, + { /* 524 */ + 10, + /* CMOVAE32rr */ + }, + { /* 525 */ + 16, + /* CMOVAE64rm */ + }, + { /* 526 */ + 18, + /* CMOVAE64rr */ + }, + { /* 527 */ + 8, + /* CMOVB16rm */ + }, + { /* 528 */ + 10, + /* CMOVB16rr */ + }, + { /* 529 */ + 8, + /* CMOVB32rm */ + }, + { /* 530 */ + 10, + /* CMOVB32rr */ + }, + { /* 531 */ + 16, + /* CMOVB64rm */ + }, + { /* 532 */ + 18, + /* CMOVB64rr */ + }, + { /* 533 */ + 8, + /* CMOVBE16rm */ + }, + { /* 534 */ + 10, + /* CMOVBE16rr */ + }, + { /* 535 */ + 8, + /* CMOVBE32rm */ + }, + { /* 536 */ + 10, + /* CMOVBE32rr */ + }, + { /* 537 */ + 16, + /* CMOVBE64rm */ + }, + { /* 538 */ + 18, + /* CMOVBE64rr */ + }, + { /* 539 */ + 29, + /* CMOVBE_F */ + }, + { /* 540 */ + 0, + /* */ + }, + { /* 541 */ + 0, + /* */ + }, + { /* 542 */ + 0, + /* */ + }, + { /* 543 */ + 29, + /* CMOVB_F */ + }, + { /* 544 */ + 0, + /* */ + }, + { /* 545 */ + 0, + /* */ + }, + { /* 546 */ + 0, + /* */ + }, + { /* 547 */ + 8, + /* CMOVE16rm */ + }, + { /* 548 */ + 10, + /* CMOVE16rr */ + }, + { /* 549 */ + 8, + /* CMOVE32rm */ + }, + { /* 550 */ + 10, + /* CMOVE32rr */ + }, + { /* 551 */ + 16, + /* CMOVE64rm */ + }, + { /* 552 */ + 18, + /* CMOVE64rr */ + }, + { /* 553 */ + 29, + /* CMOVE_F */ + }, + { /* 554 */ + 0, + /* */ + }, + { /* 555 */ + 0, + /* */ + }, + { /* 556 */ + 0, + /* */ + }, + { /* 557 */ + 8, + /* CMOVG16rm */ + }, + { /* 558 */ + 10, + /* CMOVG16rr */ + }, + { /* 559 */ + 8, + /* CMOVG32rm */ + }, + { /* 560 */ + 10, + /* CMOVG32rr */ + }, + { /* 561 */ + 16, + /* CMOVG64rm */ + }, + { /* 562 */ + 18, + /* CMOVG64rr */ + }, + { /* 563 */ + 8, + /* CMOVGE16rm */ + }, + { /* 564 */ + 10, + /* CMOVGE16rr */ + }, + { /* 565 */ + 8, + /* CMOVGE32rm */ + }, + { /* 566 */ + 10, + /* CMOVGE32rr */ + }, + { /* 567 */ + 16, + /* CMOVGE64rm */ + }, + { /* 568 */ + 18, + /* CMOVGE64rr */ + }, + { /* 569 */ + 8, + /* CMOVL16rm */ + }, + { /* 570 */ + 10, + /* CMOVL16rr */ + }, + { /* 571 */ + 8, + /* CMOVL32rm */ + }, + { /* 572 */ + 10, + /* CMOVL32rr */ + }, + { /* 573 */ + 16, + /* CMOVL64rm */ + }, + { /* 574 */ + 18, + /* CMOVL64rr */ + }, + { /* 575 */ + 8, + /* CMOVLE16rm */ + }, + { /* 576 */ + 10, + /* CMOVLE16rr */ + }, + { /* 577 */ + 8, + /* CMOVLE32rm */ + }, + { /* 578 */ + 10, + /* CMOVLE32rr */ + }, + { /* 579 */ + 16, + /* CMOVLE64rm */ + }, + { /* 580 */ + 18, + /* CMOVLE64rr */ + }, + { /* 581 */ + 29, + /* CMOVNBE_F */ + }, + { /* 582 */ + 0, + /* */ + }, + { /* 583 */ + 0, + /* */ + }, + { /* 584 */ + 0, + /* */ + }, + { /* 585 */ + 29, + /* CMOVNB_F */ + }, + { /* 586 */ + 0, + /* */ + }, + { /* 587 */ + 0, + /* */ + }, + { /* 588 */ + 0, + /* */ + }, + { /* 589 */ + 8, + /* CMOVNE16rm */ + }, + { /* 590 */ + 10, + /* CMOVNE16rr */ + }, + { /* 591 */ + 8, + /* CMOVNE32rm */ + }, + { /* 592 */ + 10, + /* CMOVNE32rr */ + }, + { /* 593 */ + 16, + /* CMOVNE64rm */ + }, + { /* 594 */ + 18, + /* CMOVNE64rr */ + }, + { /* 595 */ + 29, + /* CMOVNE_F */ + }, + { /* 596 */ + 0, + /* */ + }, + { /* 597 */ + 0, + /* */ + }, + { /* 598 */ + 0, + /* */ + }, + { /* 599 */ + 8, + /* CMOVNO16rm */ + }, + { /* 600 */ + 10, + /* CMOVNO16rr */ + }, + { /* 601 */ + 8, + /* CMOVNO32rm */ + }, + { /* 602 */ + 10, + /* CMOVNO32rr */ + }, + { /* 603 */ + 16, + /* CMOVNO64rm */ + }, + { /* 604 */ + 18, + /* CMOVNO64rr */ + }, + { /* 605 */ + 8, + /* CMOVNP16rm */ + }, + { /* 606 */ + 10, + /* CMOVNP16rr */ + }, + { /* 607 */ + 8, + /* CMOVNP32rm */ + }, + { /* 608 */ + 10, + /* CMOVNP32rr */ + }, + { /* 609 */ + 16, + /* CMOVNP64rm */ + }, + { /* 610 */ + 18, + /* CMOVNP64rr */ + }, + { /* 611 */ + 29, + /* CMOVNP_F */ + }, + { /* 612 */ + 0, + /* */ + }, + { /* 613 */ + 0, + /* */ + }, + { /* 614 */ + 0, + /* */ + }, + { /* 615 */ + 8, + /* CMOVNS16rm */ + }, + { /* 616 */ + 10, + /* CMOVNS16rr */ + }, + { /* 617 */ + 8, + /* CMOVNS32rm */ + }, + { /* 618 */ + 10, + /* CMOVNS32rr */ + }, + { /* 619 */ + 16, + /* CMOVNS64rm */ + }, + { /* 620 */ + 18, + /* CMOVNS64rr */ + }, + { /* 621 */ + 8, + /* CMOVO16rm */ + }, + { /* 622 */ + 10, + /* CMOVO16rr */ + }, + { /* 623 */ + 8, + /* CMOVO32rm */ + }, + { /* 624 */ + 10, + /* CMOVO32rr */ + }, + { /* 625 */ + 16, + /* CMOVO64rm */ + }, + { /* 626 */ + 18, + /* CMOVO64rr */ + }, + { /* 627 */ + 8, + /* CMOVP16rm */ + }, + { /* 628 */ + 10, + /* CMOVP16rr */ + }, + { /* 629 */ + 8, + /* CMOVP32rm */ + }, + { /* 630 */ + 10, + /* CMOVP32rr */ + }, + { /* 631 */ + 16, + /* CMOVP64rm */ + }, + { /* 632 */ + 18, + /* CMOVP64rr */ + }, + { /* 633 */ + 29, + /* CMOVP_F */ + }, + { /* 634 */ + 0, + /* */ + }, + { /* 635 */ + 0, + /* */ + }, + { /* 636 */ + 0, + /* */ + }, + { /* 637 */ + 8, + /* CMOVS16rm */ + }, + { /* 638 */ + 10, + /* CMOVS16rr */ + }, + { /* 639 */ + 8, + /* CMOVS32rm */ + }, + { /* 640 */ + 10, + /* CMOVS32rr */ + }, + { /* 641 */ + 16, + /* CMOVS64rm */ + }, + { /* 642 */ + 18, + /* CMOVS64rr */ + }, + { /* 643 */ + 2, + /* CMP16i16 */ + }, + { /* 644 */ + 3, + /* CMP16mi */ + }, + { /* 645 */ + 4, + /* CMP16mi8 */ + }, + { /* 646 */ + 5, + /* CMP16mr */ + }, + { /* 647 */ + 74, + /* CMP16ri */ + }, + { /* 648 */ + 66, + /* CMP16ri8 */ + }, + { /* 649 */ + 60, + /* CMP16rm */ + }, + { /* 650 */ + 67, + /* CMP16rr */ + }, + { /* 651 */ + 61, + /* CMP16rr_REV */ + }, + { /* 652 */ + 2, + /* CMP32i32 */ + }, + { /* 653 */ + 3, + /* CMP32mi */ + }, + { /* 654 */ + 4, + /* CMP32mi8 */ + }, + { /* 655 */ + 5, + /* CMP32mr */ + }, + { /* 656 */ + 74, + /* CMP32ri */ + }, + { /* 657 */ + 66, + /* CMP32ri8 */ + }, + { /* 658 */ + 60, + /* CMP32rm */ + }, + { /* 659 */ + 67, + /* CMP32rr */ + }, + { /* 660 */ + 61, + /* CMP32rr_REV */ + }, + { /* 661 */ + 11, + /* CMP64i32 */ + }, + { /* 662 */ + 12, + /* CMP64mi32 */ + }, + { /* 663 */ + 4, + /* CMP64mi8 */ + }, + { /* 664 */ + 13, + /* CMP64mr */ + }, + { /* 665 */ + 75, + /* CMP64ri32 */ + }, + { /* 666 */ + 68, + /* CMP64ri8 */ + }, + { /* 667 */ + 62, + /* CMP64rm */ + }, + { /* 668 */ + 69, + /* CMP64rr */ + }, + { /* 669 */ + 63, + /* CMP64rr_REV */ + }, + { /* 670 */ + 1, + /* CMP8i8 */ + }, + { /* 671 */ + 4, + /* CMP8mi */ + }, + { /* 672 */ + 4, + /* CMP8mi8 */ + }, + { /* 673 */ + 19, + /* CMP8mr */ + }, + { /* 674 */ + 76, + /* CMP8ri */ + }, + { /* 675 */ + 76, + /* CMP8ri8 */ + }, + { /* 676 */ + 77, + /* CMP8rm */ + }, + { /* 677 */ + 78, + /* CMP8rr */ + }, + { /* 678 */ + 79, + /* CMP8rr_REV */ + }, + { /* 679 */ + 80, + /* CMPPDrmi */ + }, + { /* 680 */ + 0, + /* */ + }, + { /* 681 */ + 81, + /* CMPPDrri */ + }, + { /* 682 */ + 0, + /* */ + }, + { /* 683 */ + 80, + /* CMPPSrmi */ + }, + { /* 684 */ + 0, + /* */ + }, + { /* 685 */ + 81, + /* CMPPSrri */ + }, + { /* 686 */ + 0, + /* */ + }, + { /* 687 */ + 82, + /* CMPSB */ + }, + { /* 688 */ + 80, + /* CMPSDrm */ + }, + { /* 689 */ + 0, + /* */ + }, + { /* 690 */ + 0, + /* */ + }, + { /* 691 */ + 81, + /* CMPSDrr */ + }, + { /* 692 */ + 0, + /* */ + }, + { /* 693 */ + 0, + /* */ + }, + { /* 694 */ + 82, + /* CMPSL */ + }, + { /* 695 */ + 82, + /* CMPSQ */ + }, + { /* 696 */ + 80, + /* CMPSSrm */ + }, + { /* 697 */ + 0, + /* */ + }, + { /* 698 */ + 0, + /* */ + }, + { /* 699 */ + 81, + /* CMPSSrr */ + }, + { /* 700 */ + 0, + /* */ + }, + { /* 701 */ + 0, + /* */ + }, + { /* 702 */ + 82, + /* CMPSW */ + }, + { /* 703 */ + 28, + /* CMPXCHG16B */ + }, + { /* 704 */ + 5, + /* CMPXCHG16rm */ + }, + { /* 705 */ + 67, + /* CMPXCHG16rr */ + }, + { /* 706 */ + 5, + /* CMPXCHG32rm */ + }, + { /* 707 */ + 67, + /* CMPXCHG32rr */ + }, + { /* 708 */ + 13, + /* CMPXCHG64rm */ + }, + { /* 709 */ + 69, + /* CMPXCHG64rr */ + }, + { /* 710 */ + 28, + /* CMPXCHG8B */ + }, + { /* 711 */ + 19, + /* CMPXCHG8rm */ + }, + { /* 712 */ + 78, + /* CMPXCHG8rr */ + }, + { /* 713 */ + 30, + /* COMISDrm */ + }, + { /* 714 */ + 0, + /* */ + }, + { /* 715 */ + 31, + /* COMISDrr */ + }, + { /* 716 */ + 0, + /* */ + }, + { /* 717 */ + 30, + /* COMISSrm */ + }, + { /* 718 */ + 0, + /* */ + }, + { /* 719 */ + 31, + /* COMISSrr */ + }, + { /* 720 */ + 0, + /* */ + }, + { /* 721 */ + 29, + /* COMP_FST0r */ + }, + { /* 722 */ + 29, + /* COM_FIPr */ + }, + { /* 723 */ + 29, + /* COM_FIr */ + }, + { /* 724 */ + 29, + /* COM_FST0r */ + }, + { /* 725 */ + 0, + /* COS_F */ + }, + { /* 726 */ + 0, + /* */ + }, + { /* 727 */ + 0, + /* */ + }, + { /* 728 */ + 0, + /* */ + }, + { /* 729 */ + 0, + /* CPUID */ + }, + { /* 730 */ + 0, + /* CQO */ + }, + { /* 731 */ + 24, + /* CRC32r32m16 */ + }, + { /* 732 */ + 8, + /* CRC32r32m32 */ + }, + { /* 733 */ + 24, + /* CRC32r32m8 */ + }, + { /* 734 */ + 83, + /* CRC32r32r16 */ + }, + { /* 735 */ + 10, + /* CRC32r32r32 */ + }, + { /* 736 */ + 84, + /* CRC32r32r8 */ + }, + { /* 737 */ + 16, + /* CRC32r64m64 */ + }, + { /* 738 */ + 16, + /* CRC32r64m8 */ + }, + { /* 739 */ + 18, + /* CRC32r64r64 */ + }, + { /* 740 */ + 85, + /* CRC32r64r8 */ + }, + { /* 741 */ + 30, + /* CVTDQ2PDrm */ + }, + { /* 742 */ + 31, + /* CVTDQ2PDrr */ + }, + { /* 743 */ + 30, + /* CVTDQ2PSrm */ + }, + { /* 744 */ + 31, + /* CVTDQ2PSrr */ + }, + { /* 745 */ + 30, + /* CVTPD2DQrm */ + }, + { /* 746 */ + 31, + /* CVTPD2DQrr */ + }, + { /* 747 */ + 30, + /* CVTPD2PSrm */ + }, + { /* 748 */ + 31, + /* CVTPD2PSrr */ + }, + { /* 749 */ + 30, + /* CVTPS2DQrm */ + }, + { /* 750 */ + 31, + /* CVTPS2DQrr */ + }, + { /* 751 */ + 30, + /* CVTPS2PDrm */ + }, + { /* 752 */ + 31, + /* CVTPS2PDrr */ + }, + { /* 753 */ + 62, + /* CVTSD2SI64rm_Int */ + }, + { /* 754 */ + 86, + /* CVTSD2SI64rr_Int */ + }, + { /* 755 */ + 87, + /* CVTSD2SIrm_Int */ + }, + { /* 756 */ + 88, + /* CVTSD2SIrr_Int */ + }, + { /* 757 */ + 30, + /* CVTSD2SSrm */ + }, + { /* 758 */ + 0, + /* */ + }, + { /* 759 */ + 31, + /* CVTSD2SSrr */ + }, + { /* 760 */ + 0, + /* */ + }, + { /* 761 */ + 30, + /* CVTSI2SDrm */ + }, + { /* 762 */ + 0, + /* */ + }, + { /* 763 */ + 89, + /* CVTSI2SDrr */ + }, + { /* 764 */ + 0, + /* */ + }, + { /* 765 */ + 30, + /* CVTSI2SSrm */ + }, + { /* 766 */ + 0, + /* */ + }, + { /* 767 */ + 89, + /* CVTSI2SSrr */ + }, + { /* 768 */ + 0, + /* */ + }, + { /* 769 */ + 30, + /* CVTSI642SDrm */ + }, + { /* 770 */ + 0, + /* */ + }, + { /* 771 */ + 90, + /* CVTSI642SDrr */ + }, + { /* 772 */ + 0, + /* */ + }, + { /* 773 */ + 30, + /* CVTSI642SSrm */ + }, + { /* 774 */ + 0, + /* */ + }, + { /* 775 */ + 90, + /* CVTSI642SSrr */ + }, + { /* 776 */ + 0, + /* */ + }, + { /* 777 */ + 30, + /* CVTSS2SDrm */ + }, + { /* 778 */ + 0, + /* */ + }, + { /* 779 */ + 31, + /* CVTSS2SDrr */ + }, + { /* 780 */ + 0, + /* */ + }, + { /* 781 */ + 62, + /* CVTSS2SI64rm_Int */ + }, + { /* 782 */ + 86, + /* CVTSS2SI64rr_Int */ + }, + { /* 783 */ + 87, + /* CVTSS2SIrm_Int */ + }, + { /* 784 */ + 88, + /* CVTSS2SIrr_Int */ + }, + { /* 785 */ + 30, + /* CVTTPD2DQrm */ + }, + { /* 786 */ + 31, + /* CVTTPD2DQrr */ + }, + { /* 787 */ + 30, + /* CVTTPS2DQrm */ + }, + { /* 788 */ + 31, + /* CVTTPS2DQrr */ + }, + { /* 789 */ + 62, + /* CVTTSD2SI64rm */ + }, + { /* 790 */ + 0, + /* */ + }, + { /* 791 */ + 86, + /* CVTTSD2SI64rr */ + }, + { /* 792 */ + 0, + /* */ + }, + { /* 793 */ + 87, + /* CVTTSD2SIrm */ + }, + { /* 794 */ + 0, + /* */ + }, + { /* 795 */ + 88, + /* CVTTSD2SIrr */ + }, + { /* 796 */ + 0, + /* */ + }, + { /* 797 */ + 62, + /* CVTTSS2SI64rm */ + }, + { /* 798 */ + 0, + /* */ + }, + { /* 799 */ + 86, + /* CVTTSS2SI64rr */ + }, + { /* 800 */ + 0, + /* */ + }, + { /* 801 */ + 87, + /* CVTTSS2SIrm */ + }, + { /* 802 */ + 0, + /* */ + }, + { /* 803 */ + 88, + /* CVTTSS2SIrr */ + }, + { /* 804 */ + 0, + /* */ + }, + { /* 805 */ + 0, + /* CWD */ + }, + { /* 806 */ + 0, + /* CWDE */ + }, + { /* 807 */ + 0, + /* DAA */ + }, + { /* 808 */ + 0, + /* DAS */ + }, + { /* 809 */ + 0, + /* DATA16_PREFIX */ + }, + { /* 810 */ + 28, + /* DEC16m */ + }, + { /* 811 */ + 91, + /* DEC16r */ + }, + { /* 812 */ + 64, + /* DEC16r_alt */ + }, + { /* 813 */ + 28, + /* DEC32m */ + }, + { /* 814 */ + 91, + /* DEC32r */ + }, + { /* 815 */ + 64, + /* DEC32r_alt */ + }, + { /* 816 */ + 28, + /* DEC64m */ + }, + { /* 817 */ + 92, + /* DEC64r */ + }, + { /* 818 */ + 28, + /* DEC8m */ + }, + { /* 819 */ + 93, + /* DEC8r */ + }, + { /* 820 */ + 28, + /* DIV16m */ + }, + { /* 821 */ + 70, + /* DIV16r */ + }, + { /* 822 */ + 28, + /* DIV32m */ + }, + { /* 823 */ + 70, + /* DIV32r */ + }, + { /* 824 */ + 28, + /* DIV64m */ + }, + { /* 825 */ + 72, + /* DIV64r */ + }, + { /* 826 */ + 28, + /* DIV8m */ + }, + { /* 827 */ + 94, + /* DIV8r */ + }, + { /* 828 */ + 26, + /* DIVPDrm */ + }, + { /* 829 */ + 27, + /* DIVPDrr */ + }, + { /* 830 */ + 26, + /* DIVPSrm */ + }, + { /* 831 */ + 27, + /* DIVPSrr */ + }, + { /* 832 */ + 28, + /* DIVR_F32m */ + }, + { /* 833 */ + 28, + /* DIVR_F64m */ + }, + { /* 834 */ + 28, + /* DIVR_FI16m */ + }, + { /* 835 */ + 28, + /* DIVR_FI32m */ + }, + { /* 836 */ + 29, + /* DIVR_FPrST0 */ + }, + { /* 837 */ + 29, + /* DIVR_FST0r */ + }, + { /* 838 */ + 0, + /* */ + }, + { /* 839 */ + 0, + /* */ + }, + { /* 840 */ + 0, + /* */ + }, + { /* 841 */ + 0, + /* */ + }, + { /* 842 */ + 0, + /* */ + }, + { /* 843 */ + 0, + /* */ + }, + { /* 844 */ + 0, + /* */ + }, + { /* 845 */ + 0, + /* */ + }, + { /* 846 */ + 0, + /* */ + }, + { /* 847 */ + 0, + /* */ + }, + { /* 848 */ + 0, + /* */ + }, + { /* 849 */ + 29, + /* DIVR_FrST0 */ + }, + { /* 850 */ + 26, + /* DIVSDrm */ + }, + { /* 851 */ + 0, + /* */ + }, + { /* 852 */ + 27, + /* DIVSDrr */ + }, + { /* 853 */ + 0, + /* */ + }, + { /* 854 */ + 26, + /* DIVSSrm */ + }, + { /* 855 */ + 0, + /* */ + }, + { /* 856 */ + 27, + /* DIVSSrr */ + }, + { /* 857 */ + 0, + /* */ + }, + { /* 858 */ + 28, + /* DIV_F32m */ + }, + { /* 859 */ + 28, + /* DIV_F64m */ + }, + { /* 860 */ + 28, + /* DIV_FI16m */ + }, + { /* 861 */ + 28, + /* DIV_FI32m */ + }, + { /* 862 */ + 29, + /* DIV_FPrST0 */ + }, + { /* 863 */ + 29, + /* DIV_FST0r */ + }, + { /* 864 */ + 0, + /* */ + }, + { /* 865 */ + 0, + /* */ + }, + { /* 866 */ + 0, + /* */ + }, + { /* 867 */ + 0, + /* */ + }, + { /* 868 */ + 0, + /* */ + }, + { /* 869 */ + 0, + /* */ + }, + { /* 870 */ + 0, + /* */ + }, + { /* 871 */ + 0, + /* */ + }, + { /* 872 */ + 0, + /* */ + }, + { /* 873 */ + 0, + /* */ + }, + { /* 874 */ + 0, + /* */ + }, + { /* 875 */ + 0, + /* */ + }, + { /* 876 */ + 0, + /* */ + }, + { /* 877 */ + 0, + /* */ + }, + { /* 878 */ + 29, + /* DIV_FrST0 */ + }, + { /* 879 */ + 52, + /* DPPDrmi */ + }, + { /* 880 */ + 53, + /* DPPDrri */ + }, + { /* 881 */ + 52, + /* DPPSrmi */ + }, + { /* 882 */ + 53, + /* DPPSrri */ + }, + { /* 883 */ + 0, + /* ENCLS */ + }, + { /* 884 */ + 0, + /* ENCLU */ + }, + { /* 885 */ + 0, + /* ENCLV */ + }, + { /* 886 */ + 0, + /* ENDBR32 */ + }, + { /* 887 */ + 0, + /* ENDBR64 */ + }, + { /* 888 */ + 95, + /* ENTER */ + }, + { /* 889 */ + 96, + /* EXTRACTPSmr */ + }, + { /* 890 */ + 97, + /* EXTRACTPSrr */ + }, + { /* 891 */ + 27, + /* EXTRQ */ + }, + { /* 892 */ + 98, + /* EXTRQI */ + }, + { /* 893 */ + 0, + /* F2XM1 */ + }, + { /* 894 */ + 99, + /* FARCALL16i */ + }, + { /* 895 */ + 28, + /* FARCALL16m */ + }, + { /* 896 */ + 100, + /* FARCALL32i */ + }, + { /* 897 */ + 28, + /* FARCALL32m */ + }, + { /* 898 */ + 28, + /* FARCALL64 */ + }, + { /* 899 */ + 99, + /* FARJMP16i */ + }, + { /* 900 */ + 28, + /* FARJMP16m */ + }, + { /* 901 */ + 100, + /* FARJMP32i */ + }, + { /* 902 */ + 28, + /* FARJMP32m */ + }, + { /* 903 */ + 28, + /* FARJMP64 */ + }, + { /* 904 */ + 28, + /* FBLDm */ + }, + { /* 905 */ + 28, + /* FBSTPm */ + }, + { /* 906 */ + 28, + /* FCOM32m */ + }, + { /* 907 */ + 28, + /* FCOM64m */ + }, + { /* 908 */ + 28, + /* FCOMP32m */ + }, + { /* 909 */ + 28, + /* FCOMP64m */ + }, + { /* 910 */ + 0, + /* FCOMPP */ + }, + { /* 911 */ + 0, + /* FDECSTP */ + }, + { /* 912 */ + 0, + /* FDISI8087_NOP */ + }, + { /* 913 */ + 0, + /* FEMMS */ + }, + { /* 914 */ + 0, + /* FENI8087_NOP */ + }, + { /* 915 */ + 29, + /* FFREE */ + }, + { /* 916 */ + 29, + /* FFREEP */ + }, + { /* 917 */ + 28, + /* FICOM16m */ + }, + { /* 918 */ + 28, + /* FICOM32m */ + }, + { /* 919 */ + 28, + /* FICOMP16m */ + }, + { /* 920 */ + 28, + /* FICOMP32m */ + }, + { /* 921 */ + 0, + /* FINCSTP */ + }, + { /* 922 */ + 28, + /* FLDCW16m */ + }, + { /* 923 */ + 28, + /* FLDENVm */ + }, + { /* 924 */ + 0, + /* FLDL2E */ + }, + { /* 925 */ + 0, + /* FLDL2T */ + }, + { /* 926 */ + 0, + /* FLDLG2 */ + }, + { /* 927 */ + 0, + /* FLDLN2 */ + }, + { /* 928 */ + 0, + /* FLDPI */ + }, + { /* 929 */ + 0, + /* FNCLEX */ + }, + { /* 930 */ + 0, + /* FNINIT */ + }, + { /* 931 */ + 0, + /* FNOP */ + }, + { /* 932 */ + 28, + /* FNSTCW16m */ + }, + { /* 933 */ + 0, + /* FNSTSW16r */ + }, + { /* 934 */ + 28, + /* FNSTSWm */ + }, + { /* 935 */ + 0, + /* FPATAN */ + }, + { /* 936 */ + 29, + /* FPNCEST0r */ + }, + { /* 937 */ + 0, + /* FPREM */ + }, + { /* 938 */ + 0, + /* FPREM1 */ + }, + { /* 939 */ + 0, + /* FPTAN */ + }, + { /* 940 */ + 0, + /* FRNDINT */ + }, + { /* 941 */ + 28, + /* FRSTORm */ + }, + { /* 942 */ + 28, + /* FSAVEm */ + }, + { /* 943 */ + 0, + /* FSCALE */ + }, + { /* 944 */ + 0, + /* FSETPM */ + }, + { /* 945 */ + 0, + /* FSINCOS */ + }, + { /* 946 */ + 28, + /* FSTENVm */ + }, + { /* 947 */ + 0, + /* FXAM */ + }, + { /* 948 */ + 28, + /* FXRSTOR */ + }, + { /* 949 */ + 28, + /* FXRSTOR64 */ + }, + { /* 950 */ + 28, + /* FXSAVE */ + }, + { /* 951 */ + 28, + /* FXSAVE64 */ + }, + { /* 952 */ + 0, + /* FXTRACT */ + }, + { /* 953 */ + 0, + /* FYL2X */ + }, + { /* 954 */ + 0, + /* FYL2XP1 */ + }, + { /* 955 */ + 0, + /* GETSEC */ + }, + { /* 956 */ + 52, + /* GF2P8AFFINEINVQBrmi */ + }, + { /* 957 */ + 53, + /* GF2P8AFFINEINVQBrri */ + }, + { /* 958 */ + 52, + /* GF2P8AFFINEQBrmi */ + }, + { /* 959 */ + 53, + /* GF2P8AFFINEQBrri */ + }, + { /* 960 */ + 26, + /* GF2P8MULBrm */ + }, + { /* 961 */ + 27, + /* GF2P8MULBrr */ + }, + { /* 962 */ + 26, + /* HADDPDrm */ + }, + { /* 963 */ + 27, + /* HADDPDrr */ + }, + { /* 964 */ + 26, + /* HADDPSrm */ + }, + { /* 965 */ + 27, + /* HADDPSrr */ + }, + { /* 966 */ + 0, + /* HLT */ + }, + { /* 967 */ + 26, + /* HSUBPDrm */ + }, + { /* 968 */ + 27, + /* HSUBPDrr */ + }, + { /* 969 */ + 26, + /* HSUBPSrm */ + }, + { /* 970 */ + 27, + /* HSUBPSrr */ + }, + { /* 971 */ + 28, + /* IDIV16m */ + }, + { /* 972 */ + 70, + /* IDIV16r */ + }, + { /* 973 */ + 28, + /* IDIV32m */ + }, + { /* 974 */ + 70, + /* IDIV32r */ + }, + { /* 975 */ + 28, + /* IDIV64m */ + }, + { /* 976 */ + 72, + /* IDIV64r */ + }, + { /* 977 */ + 28, + /* IDIV8m */ + }, + { /* 978 */ + 94, + /* IDIV8r */ + }, + { /* 979 */ + 28, + /* ILD_F16m */ + }, + { /* 980 */ + 28, + /* ILD_F32m */ + }, + { /* 981 */ + 28, + /* ILD_F64m */ + }, + { /* 982 */ + 0, + /* */ + }, + { /* 983 */ + 0, + /* */ + }, + { /* 984 */ + 0, + /* */ + }, + { /* 985 */ + 0, + /* */ + }, + { /* 986 */ + 0, + /* */ + }, + { /* 987 */ + 0, + /* */ + }, + { /* 988 */ + 0, + /* */ + }, + { /* 989 */ + 0, + /* */ + }, + { /* 990 */ + 0, + /* */ + }, + { /* 991 */ + 28, + /* IMUL16m */ + }, + { /* 992 */ + 70, + /* IMUL16r */ + }, + { /* 993 */ + 8, + /* IMUL16rm */ + }, + { /* 994 */ + 101, + /* IMUL16rmi */ + }, + { /* 995 */ + 102, + /* IMUL16rmi8 */ + }, + { /* 996 */ + 10, + /* IMUL16rr */ + }, + { /* 997 */ + 103, + /* IMUL16rri */ + }, + { /* 998 */ + 104, + /* IMUL16rri8 */ + }, + { /* 999 */ + 28, + /* IMUL32m */ + }, + { /* 1000 */ + 70, + /* IMUL32r */ + }, + { /* 1001 */ + 8, + /* IMUL32rm */ + }, + { /* 1002 */ + 101, + /* IMUL32rmi */ + }, + { /* 1003 */ + 102, + /* IMUL32rmi8 */ + }, + { /* 1004 */ + 10, + /* IMUL32rr */ + }, + { /* 1005 */ + 103, + /* IMUL32rri */ + }, + { /* 1006 */ + 104, + /* IMUL32rri8 */ + }, + { /* 1007 */ + 28, + /* IMUL64m */ + }, + { /* 1008 */ + 72, + /* IMUL64r */ + }, + { /* 1009 */ + 16, + /* IMUL64rm */ + }, + { /* 1010 */ + 46, + /* IMUL64rmi32 */ + }, + { /* 1011 */ + 105, + /* IMUL64rmi8 */ + }, + { /* 1012 */ + 18, + /* IMUL64rr */ + }, + { /* 1013 */ + 47, + /* IMUL64rri32 */ + }, + { /* 1014 */ + 106, + /* IMUL64rri8 */ + }, + { /* 1015 */ + 28, + /* IMUL8m */ + }, + { /* 1016 */ + 94, + /* IMUL8r */ + }, + { /* 1017 */ + 107, + /* IN16ri */ + }, + { /* 1018 */ + 0, + /* IN16rr */ + }, + { /* 1019 */ + 107, + /* IN32ri */ + }, + { /* 1020 */ + 0, + /* IN32rr */ + }, + { /* 1021 */ + 107, + /* IN8ri */ + }, + { /* 1022 */ + 0, + /* IN8rr */ + }, + { /* 1023 */ + 28, + /* INC16m */ + }, + { /* 1024 */ + 91, + /* INC16r */ + }, + { /* 1025 */ + 64, + /* INC16r_alt */ + }, + { /* 1026 */ + 28, + /* INC32m */ + }, + { /* 1027 */ + 91, + /* INC32r */ + }, + { /* 1028 */ + 64, + /* INC32r_alt */ + }, + { /* 1029 */ + 28, + /* INC64m */ + }, + { /* 1030 */ + 92, + /* INC64r */ + }, + { /* 1031 */ + 28, + /* INC8m */ + }, + { /* 1032 */ + 93, + /* INC8r */ + }, + { /* 1033 */ + 108, + /* INCSSPD */ + }, + { /* 1034 */ + 72, + /* INCSSPQ */ + }, + { /* 1035 */ + 109, + /* INSB */ + }, + { /* 1036 */ + 52, + /* INSERTPSrm */ + }, + { /* 1037 */ + 53, + /* INSERTPSrr */ + }, + { /* 1038 */ + 27, + /* INSERTQ */ + }, + { /* 1039 */ + 110, + /* INSERTQI */ + }, + { /* 1040 */ + 109, + /* INSL */ + }, + { /* 1041 */ + 109, + /* INSW */ + }, + { /* 1042 */ + 107, + /* INT */ + }, + { /* 1043 */ + 0, + /* INT1 */ + }, + { /* 1044 */ + 0, + /* INT3 */ + }, + { /* 1045 */ + 0, + /* INTO */ + }, + { /* 1046 */ + 0, + /* INVD */ + }, + { /* 1047 */ + 87, + /* INVEPT32 */ + }, + { /* 1048 */ + 62, + /* INVEPT64 */ + }, + { /* 1049 */ + 28, + /* INVLPG */ + }, + { /* 1050 */ + 0, + /* INVLPGA32 */ + }, + { /* 1051 */ + 0, + /* INVLPGA64 */ + }, + { /* 1052 */ + 87, + /* INVPCID32 */ + }, + { /* 1053 */ + 62, + /* INVPCID64 */ + }, + { /* 1054 */ + 87, + /* INVVPID32 */ + }, + { /* 1055 */ + 62, + /* INVVPID64 */ + }, + { /* 1056 */ + 0, + /* IRET16 */ + }, + { /* 1057 */ + 0, + /* IRET32 */ + }, + { /* 1058 */ + 0, + /* IRET64 */ + }, + { /* 1059 */ + 28, + /* ISTT_FP16m */ + }, + { /* 1060 */ + 28, + /* ISTT_FP32m */ + }, + { /* 1061 */ + 28, + /* ISTT_FP64m */ + }, + { /* 1062 */ + 0, + /* */ + }, + { /* 1063 */ + 0, + /* */ + }, + { /* 1064 */ + 0, + /* */ + }, + { /* 1065 */ + 0, + /* */ + }, + { /* 1066 */ + 0, + /* */ + }, + { /* 1067 */ + 0, + /* */ + }, + { /* 1068 */ + 0, + /* */ + }, + { /* 1069 */ + 0, + /* */ + }, + { /* 1070 */ + 0, + /* */ + }, + { /* 1071 */ + 28, + /* IST_F16m */ + }, + { /* 1072 */ + 28, + /* IST_F32m */ + }, + { /* 1073 */ + 28, + /* IST_FP16m */ + }, + { /* 1074 */ + 28, + /* IST_FP32m */ + }, + { /* 1075 */ + 28, + /* IST_FP64m */ + }, + { /* 1076 */ + 0, + /* */ + }, + { /* 1077 */ + 0, + /* */ + }, + { /* 1078 */ + 0, + /* */ + }, + { /* 1079 */ + 0, + /* */ + }, + { /* 1080 */ + 0, + /* */ + }, + { /* 1081 */ + 0, + /* */ + }, + { /* 1082 */ + 0, + /* */ + }, + { /* 1083 */ + 0, + /* */ + }, + { /* 1084 */ + 0, + /* */ + }, + { /* 1085 */ + 111, + /* JAE_1 */ + }, + { /* 1086 */ + 112, + /* JAE_2 */ + }, + { /* 1087 */ + 112, + /* JAE_4 */ + }, + { /* 1088 */ + 111, + /* JA_1 */ + }, + { /* 1089 */ + 112, + /* JA_2 */ + }, + { /* 1090 */ + 112, + /* JA_4 */ + }, + { /* 1091 */ + 111, + /* JBE_1 */ + }, + { /* 1092 */ + 112, + /* JBE_2 */ + }, + { /* 1093 */ + 112, + /* JBE_4 */ + }, + { /* 1094 */ + 111, + /* JB_1 */ + }, + { /* 1095 */ + 112, + /* JB_2 */ + }, + { /* 1096 */ + 112, + /* JB_4 */ + }, + { /* 1097 */ + 111, + /* JCXZ */ + }, + { /* 1098 */ + 111, + /* JECXZ */ + }, + { /* 1099 */ + 111, + /* JE_1 */ + }, + { /* 1100 */ + 112, + /* JE_2 */ + }, + { /* 1101 */ + 112, + /* JE_4 */ + }, + { /* 1102 */ + 111, + /* JGE_1 */ + }, + { /* 1103 */ + 112, + /* JGE_2 */ + }, + { /* 1104 */ + 112, + /* JGE_4 */ + }, + { /* 1105 */ + 111, + /* JG_1 */ + }, + { /* 1106 */ + 112, + /* JG_2 */ + }, + { /* 1107 */ + 112, + /* JG_4 */ + }, + { /* 1108 */ + 111, + /* JLE_1 */ + }, + { /* 1109 */ + 112, + /* JLE_2 */ + }, + { /* 1110 */ + 112, + /* JLE_4 */ + }, + { /* 1111 */ + 111, + /* JL_1 */ + }, + { /* 1112 */ + 112, + /* JL_2 */ + }, + { /* 1113 */ + 112, + /* JL_4 */ + }, + { /* 1114 */ + 28, + /* JMP16m */ + }, + { /* 1115 */ + 0, + /* */ + }, + { /* 1116 */ + 70, + /* JMP16r */ + }, + { /* 1117 */ + 0, + /* */ + }, + { /* 1118 */ + 28, + /* JMP32m */ + }, + { /* 1119 */ + 0, + /* */ + }, + { /* 1120 */ + 70, + /* JMP32r */ + }, + { /* 1121 */ + 0, + /* */ + }, + { /* 1122 */ + 28, + /* JMP64m */ + }, + { /* 1123 */ + 0, + /* */ + }, + { /* 1124 */ + 72, + /* JMP64r */ + }, + { /* 1125 */ + 0, + /* */ + }, + { /* 1126 */ + 111, + /* JMP_1 */ + }, + { /* 1127 */ + 112, + /* JMP_2 */ + }, + { /* 1128 */ + 112, + /* JMP_4 */ + }, + { /* 1129 */ + 111, + /* JNE_1 */ + }, + { /* 1130 */ + 112, + /* JNE_2 */ + }, + { /* 1131 */ + 112, + /* JNE_4 */ + }, + { /* 1132 */ + 111, + /* JNO_1 */ + }, + { /* 1133 */ + 112, + /* JNO_2 */ + }, + { /* 1134 */ + 112, + /* JNO_4 */ + }, + { /* 1135 */ + 111, + /* JNP_1 */ + }, + { /* 1136 */ + 112, + /* JNP_2 */ + }, + { /* 1137 */ + 112, + /* JNP_4 */ + }, + { /* 1138 */ + 111, + /* JNS_1 */ + }, + { /* 1139 */ + 112, + /* JNS_2 */ + }, + { /* 1140 */ + 112, + /* JNS_4 */ + }, + { /* 1141 */ + 111, + /* JO_1 */ + }, + { /* 1142 */ + 112, + /* JO_2 */ + }, + { /* 1143 */ + 112, + /* JO_4 */ + }, + { /* 1144 */ + 111, + /* JP_1 */ + }, + { /* 1145 */ + 112, + /* JP_2 */ + }, + { /* 1146 */ + 112, + /* JP_4 */ + }, + { /* 1147 */ + 111, + /* JRCXZ */ + }, + { /* 1148 */ + 111, + /* JS_1 */ + }, + { /* 1149 */ + 112, + /* JS_2 */ + }, + { /* 1150 */ + 112, + /* JS_4 */ + }, + { /* 1151 */ + 113, + /* KADDBrr */ + }, + { /* 1152 */ + 113, + /* KADDDrr */ + }, + { /* 1153 */ + 113, + /* KADDQrr */ + }, + { /* 1154 */ + 113, + /* KADDWrr */ + }, + { /* 1155 */ + 113, + /* KANDBrr */ + }, + { /* 1156 */ + 113, + /* KANDDrr */ + }, + { /* 1157 */ + 113, + /* KANDNBrr */ + }, + { /* 1158 */ + 113, + /* KANDNDrr */ + }, + { /* 1159 */ + 113, + /* KANDNQrr */ + }, + { /* 1160 */ + 113, + /* KANDNWrr */ + }, + { /* 1161 */ + 113, + /* KANDQrr */ + }, + { /* 1162 */ + 113, + /* KANDWrr */ + }, + { /* 1163 */ + 114, + /* KMOVBkk */ + }, + { /* 1164 */ + 115, + /* KMOVBkm */ + }, + { /* 1165 */ + 116, + /* KMOVBkr */ + }, + { /* 1166 */ + 117, + /* KMOVBmk */ + }, + { /* 1167 */ + 118, + /* KMOVBrk */ + }, + { /* 1168 */ + 114, + /* KMOVDkk */ + }, + { /* 1169 */ + 115, + /* KMOVDkm */ + }, + { /* 1170 */ + 116, + /* KMOVDkr */ + }, + { /* 1171 */ + 117, + /* KMOVDmk */ + }, + { /* 1172 */ + 118, + /* KMOVDrk */ + }, + { /* 1173 */ + 114, + /* KMOVQkk */ + }, + { /* 1174 */ + 115, + /* KMOVQkm */ + }, + { /* 1175 */ + 119, + /* KMOVQkr */ + }, + { /* 1176 */ + 117, + /* KMOVQmk */ + }, + { /* 1177 */ + 120, + /* KMOVQrk */ + }, + { /* 1178 */ + 114, + /* KMOVWkk */ + }, + { /* 1179 */ + 115, + /* KMOVWkm */ + }, + { /* 1180 */ + 116, + /* KMOVWkr */ + }, + { /* 1181 */ + 117, + /* KMOVWmk */ + }, + { /* 1182 */ + 118, + /* KMOVWrk */ + }, + { /* 1183 */ + 114, + /* KNOTBrr */ + }, + { /* 1184 */ + 114, + /* KNOTDrr */ + }, + { /* 1185 */ + 114, + /* KNOTQrr */ + }, + { /* 1186 */ + 114, + /* KNOTWrr */ + }, + { /* 1187 */ + 113, + /* KORBrr */ + }, + { /* 1188 */ + 113, + /* KORDrr */ + }, + { /* 1189 */ + 113, + /* KORQrr */ + }, + { /* 1190 */ + 114, + /* KORTESTBrr */ + }, + { /* 1191 */ + 114, + /* KORTESTDrr */ + }, + { /* 1192 */ + 114, + /* KORTESTQrr */ + }, + { /* 1193 */ + 114, + /* KORTESTWrr */ + }, + { /* 1194 */ + 113, + /* KORWrr */ + }, + { /* 1195 */ + 121, + /* KSHIFTLBri */ + }, + { /* 1196 */ + 121, + /* KSHIFTLDri */ + }, + { /* 1197 */ + 121, + /* KSHIFTLQri */ + }, + { /* 1198 */ + 121, + /* KSHIFTLWri */ + }, + { /* 1199 */ + 121, + /* KSHIFTRBri */ + }, + { /* 1200 */ + 121, + /* KSHIFTRDri */ + }, + { /* 1201 */ + 121, + /* KSHIFTRQri */ + }, + { /* 1202 */ + 121, + /* KSHIFTRWri */ + }, + { /* 1203 */ + 114, + /* KTESTBrr */ + }, + { /* 1204 */ + 114, + /* KTESTDrr */ + }, + { /* 1205 */ + 114, + /* KTESTQrr */ + }, + { /* 1206 */ + 114, + /* KTESTWrr */ + }, + { /* 1207 */ + 113, + /* KUNPCKBWrr */ + }, + { /* 1208 */ + 113, + /* KUNPCKDQrr */ + }, + { /* 1209 */ + 113, + /* KUNPCKWDrr */ + }, + { /* 1210 */ + 113, + /* KXNORBrr */ + }, + { /* 1211 */ + 113, + /* KXNORDrr */ + }, + { /* 1212 */ + 113, + /* KXNORQrr */ + }, + { /* 1213 */ + 113, + /* KXNORWrr */ + }, + { /* 1214 */ + 113, + /* KXORBrr */ + }, + { /* 1215 */ + 113, + /* KXORDrr */ + }, + { /* 1216 */ + 113, + /* KXORQrr */ + }, + { /* 1217 */ + 113, + /* KXORWrr */ + }, + { /* 1218 */ + 0, + /* LAHF */ + }, + { /* 1219 */ + 60, + /* LAR16rm */ + }, + { /* 1220 */ + 61, + /* LAR16rr */ + }, + { /* 1221 */ + 60, + /* LAR32rm */ + }, + { /* 1222 */ + 61, + /* LAR32rr */ + }, + { /* 1223 */ + 62, + /* LAR64rm */ + }, + { /* 1224 */ + 122, + /* LAR64rr */ + }, + { /* 1225 */ + 30, + /* LDDQUrm */ + }, + { /* 1226 */ + 28, + /* LDMXCSR */ + }, + { /* 1227 */ + 60, + /* LDS16rm */ + }, + { /* 1228 */ + 60, + /* LDS32rm */ + }, + { /* 1229 */ + 0, + /* LD_F0 */ + }, + { /* 1230 */ + 0, + /* LD_F1 */ + }, + { /* 1231 */ + 28, + /* LD_F32m */ + }, + { /* 1232 */ + 28, + /* LD_F64m */ + }, + { /* 1233 */ + 28, + /* LD_F80m */ + }, + { /* 1234 */ + 0, + /* */ + }, + { /* 1235 */ + 0, + /* */ + }, + { /* 1236 */ + 0, + /* */ + }, + { /* 1237 */ + 0, + /* */ + }, + { /* 1238 */ + 0, + /* */ + }, + { /* 1239 */ + 0, + /* */ + }, + { /* 1240 */ + 0, + /* */ + }, + { /* 1241 */ + 0, + /* */ + }, + { /* 1242 */ + 0, + /* */ + }, + { /* 1243 */ + 0, + /* */ + }, + { /* 1244 */ + 0, + /* */ + }, + { /* 1245 */ + 0, + /* */ + }, + { /* 1246 */ + 29, + /* LD_Frr */ + }, + { /* 1247 */ + 60, + /* LEA16r */ + }, + { /* 1248 */ + 60, + /* LEA32r */ + }, + { /* 1249 */ + 60, + /* LEA64_32r */ + }, + { /* 1250 */ + 62, + /* LEA64r */ + }, + { /* 1251 */ + 0, + /* LEAVE */ + }, + { /* 1252 */ + 0, + /* LEAVE64 */ + }, + { /* 1253 */ + 60, + /* LES16rm */ + }, + { /* 1254 */ + 60, + /* LES32rm */ + }, + { /* 1255 */ + 0, + /* LFENCE */ + }, + { /* 1256 */ + 60, + /* LFS16rm */ + }, + { /* 1257 */ + 60, + /* LFS32rm */ + }, + { /* 1258 */ + 62, + /* LFS64rm */ + }, + { /* 1259 */ + 28, + /* LGDT16m */ + }, + { /* 1260 */ + 28, + /* LGDT32m */ + }, + { /* 1261 */ + 28, + /* LGDT64m */ + }, + { /* 1262 */ + 60, + /* LGS16rm */ + }, + { /* 1263 */ + 60, + /* LGS32rm */ + }, + { /* 1264 */ + 62, + /* LGS64rm */ + }, + { /* 1265 */ + 28, + /* LIDT16m */ + }, + { /* 1266 */ + 28, + /* LIDT32m */ + }, + { /* 1267 */ + 28, + /* LIDT64m */ + }, + { /* 1268 */ + 28, + /* LLDT16m */ + }, + { /* 1269 */ + 123, + /* LLDT16r */ + }, + { /* 1270 */ + 108, + /* LLWPCB */ + }, + { /* 1271 */ + 72, + /* LLWPCB64 */ + }, + { /* 1272 */ + 28, + /* LMSW16m */ + }, + { /* 1273 */ + 123, + /* LMSW16r */ + }, + { /* 1274 */ + 0, + /* LOCK_PREFIX */ + }, + { /* 1275 */ + 124, + /* LODSB */ + }, + { /* 1276 */ + 124, + /* LODSL */ + }, + { /* 1277 */ + 124, + /* LODSQ */ + }, + { /* 1278 */ + 124, + /* LODSW */ + }, + { /* 1279 */ + 111, + /* LOOP */ + }, + { /* 1280 */ + 111, + /* LOOPE */ + }, + { /* 1281 */ + 111, + /* LOOPNE */ + }, + { /* 1282 */ + 125, + /* LRETIL */ + }, + { /* 1283 */ + 125, + /* LRETIQ */ + }, + { /* 1284 */ + 2, + /* LRETIW */ + }, + { /* 1285 */ + 0, + /* LRETL */ + }, + { /* 1286 */ + 0, + /* LRETQ */ + }, + { /* 1287 */ + 0, + /* LRETW */ + }, + { /* 1288 */ + 60, + /* LSL16rm */ + }, + { /* 1289 */ + 61, + /* LSL16rr */ + }, + { /* 1290 */ + 60, + /* LSL32rm */ + }, + { /* 1291 */ + 61, + /* LSL32rr */ + }, + { /* 1292 */ + 62, + /* LSL64rm */ + }, + { /* 1293 */ + 122, + /* LSL64rr */ + }, + { /* 1294 */ + 60, + /* LSS16rm */ + }, + { /* 1295 */ + 60, + /* LSS32rm */ + }, + { /* 1296 */ + 62, + /* LSS64rm */ + }, + { /* 1297 */ + 28, + /* LTRm */ + }, + { /* 1298 */ + 123, + /* LTRr */ + }, + { /* 1299 */ + 126, + /* LWPINS32rmi */ + }, + { /* 1300 */ + 127, + /* LWPINS32rri */ + }, + { /* 1301 */ + 128, + /* LWPINS64rmi */ + }, + { /* 1302 */ + 129, + /* LWPINS64rri */ + }, + { /* 1303 */ + 126, + /* LWPVAL32rmi */ + }, + { /* 1304 */ + 127, + /* LWPVAL32rri */ + }, + { /* 1305 */ + 128, + /* LWPVAL64rmi */ + }, + { /* 1306 */ + 129, + /* LWPVAL64rri */ + }, + { /* 1307 */ + 60, + /* LZCNT16rm */ + }, + { /* 1308 */ + 61, + /* LZCNT16rr */ + }, + { /* 1309 */ + 60, + /* LZCNT32rm */ + }, + { /* 1310 */ + 61, + /* LZCNT32rr */ + }, + { /* 1311 */ + 62, + /* LZCNT64rm */ + }, + { /* 1312 */ + 63, + /* LZCNT64rr */ + }, + { /* 1313 */ + 31, + /* MASKMOVDQU */ + }, + { /* 1314 */ + 31, + /* MASKMOVDQU64 */ + }, + { /* 1315 */ + 0, + /* */ + }, + { /* 1316 */ + 0, + /* */ + }, + { /* 1317 */ + 0, + /* */ + }, + { /* 1318 */ + 0, + /* */ + }, + { /* 1319 */ + 0, + /* */ + }, + { /* 1320 */ + 0, + /* */ + }, + { /* 1321 */ + 0, + /* */ + }, + { /* 1322 */ + 0, + /* */ + }, + { /* 1323 */ + 26, + /* MAXPDrm */ + }, + { /* 1324 */ + 27, + /* MAXPDrr */ + }, + { /* 1325 */ + 26, + /* MAXPSrm */ + }, + { /* 1326 */ + 27, + /* MAXPSrr */ + }, + { /* 1327 */ + 26, + /* MAXSDrm */ + }, + { /* 1328 */ + 0, + /* */ + }, + { /* 1329 */ + 27, + /* MAXSDrr */ + }, + { /* 1330 */ + 0, + /* */ + }, + { /* 1331 */ + 26, + /* MAXSSrm */ + }, + { /* 1332 */ + 0, + /* */ + }, + { /* 1333 */ + 27, + /* MAXSSrr */ + }, + { /* 1334 */ + 0, + /* */ + }, + { /* 1335 */ + 0, + /* MFENCE */ + }, + { /* 1336 */ + 0, + /* */ + }, + { /* 1337 */ + 0, + /* */ + }, + { /* 1338 */ + 0, + /* */ + }, + { /* 1339 */ + 0, + /* */ + }, + { /* 1340 */ + 0, + /* */ + }, + { /* 1341 */ + 0, + /* */ + }, + { /* 1342 */ + 0, + /* */ + }, + { /* 1343 */ + 0, + /* */ + }, + { /* 1344 */ + 26, + /* MINPDrm */ + }, + { /* 1345 */ + 27, + /* MINPDrr */ + }, + { /* 1346 */ + 26, + /* MINPSrm */ + }, + { /* 1347 */ + 27, + /* MINPSrr */ + }, + { /* 1348 */ + 26, + /* MINSDrm */ + }, + { /* 1349 */ + 0, + /* */ + }, + { /* 1350 */ + 27, + /* MINSDrr */ + }, + { /* 1351 */ + 0, + /* */ + }, + { /* 1352 */ + 26, + /* MINSSrm */ + }, + { /* 1353 */ + 0, + /* */ + }, + { /* 1354 */ + 27, + /* MINSSrr */ + }, + { /* 1355 */ + 0, + /* */ + }, + { /* 1356 */ + 130, + /* MMX_CVTPD2PIirm */ + }, + { /* 1357 */ + 131, + /* MMX_CVTPD2PIirr */ + }, + { /* 1358 */ + 30, + /* MMX_CVTPI2PDirm */ + }, + { /* 1359 */ + 132, + /* MMX_CVTPI2PDirr */ + }, + { /* 1360 */ + 26, + /* MMX_CVTPI2PSirm */ + }, + { /* 1361 */ + 133, + /* MMX_CVTPI2PSirr */ + }, + { /* 1362 */ + 130, + /* MMX_CVTPS2PIirm */ + }, + { /* 1363 */ + 131, + /* MMX_CVTPS2PIirr */ + }, + { /* 1364 */ + 130, + /* MMX_CVTTPD2PIirm */ + }, + { /* 1365 */ + 131, + /* MMX_CVTTPD2PIirr */ + }, + { /* 1366 */ + 130, + /* MMX_CVTTPS2PIirm */ + }, + { /* 1367 */ + 131, + /* MMX_CVTTPS2PIirr */ + }, + { /* 1368 */ + 0, + /* MMX_EMMS */ + }, + { /* 1369 */ + 134, + /* MMX_MASKMOVQ */ + }, + { /* 1370 */ + 134, + /* MMX_MASKMOVQ64 */ + }, + { /* 1371 */ + 135, + /* MMX_MOVD64from64rm */ + }, + { /* 1372 */ + 136, + /* MMX_MOVD64from64rr */ + }, + { /* 1373 */ + 137, + /* MMX_MOVD64grr */ + }, + { /* 1374 */ + 135, + /* MMX_MOVD64mr */ + }, + { /* 1375 */ + 130, + /* MMX_MOVD64rm */ + }, + { /* 1376 */ + 138, + /* MMX_MOVD64rr */ + }, + { /* 1377 */ + 130, + /* MMX_MOVD64to64rm */ + }, + { /* 1378 */ + 139, + /* MMX_MOVD64to64rr */ + }, + { /* 1379 */ + 131, + /* MMX_MOVDQ2Qrr */ + }, + { /* 1380 */ + 0, + /* */ + }, + { /* 1381 */ + 135, + /* MMX_MOVNTQmr */ + }, + { /* 1382 */ + 132, + /* MMX_MOVQ2DQrr */ + }, + { /* 1383 */ + 0, + /* */ + }, + { /* 1384 */ + 135, + /* MMX_MOVQ64mr */ + }, + { /* 1385 */ + 130, + /* MMX_MOVQ64rm */ + }, + { /* 1386 */ + 134, + /* MMX_MOVQ64rr */ + }, + { /* 1387 */ + 140, + /* MMX_MOVQ64rr_REV */ + }, + { /* 1388 */ + 130, + /* MMX_PABSBrm */ + }, + { /* 1389 */ + 134, + /* MMX_PABSBrr */ + }, + { /* 1390 */ + 130, + /* MMX_PABSDrm */ + }, + { /* 1391 */ + 134, + /* MMX_PABSDrr */ + }, + { /* 1392 */ + 130, + /* MMX_PABSWrm */ + }, + { /* 1393 */ + 134, + /* MMX_PABSWrr */ + }, + { /* 1394 */ + 141, + /* MMX_PACKSSDWirm */ + }, + { /* 1395 */ + 142, + /* MMX_PACKSSDWirr */ + }, + { /* 1396 */ + 141, + /* MMX_PACKSSWBirm */ + }, + { /* 1397 */ + 142, + /* MMX_PACKSSWBirr */ + }, + { /* 1398 */ + 141, + /* MMX_PACKUSWBirm */ + }, + { /* 1399 */ + 142, + /* MMX_PACKUSWBirr */ + }, + { /* 1400 */ + 141, + /* MMX_PADDBirm */ + }, + { /* 1401 */ + 142, + /* MMX_PADDBirr */ + }, + { /* 1402 */ + 141, + /* MMX_PADDDirm */ + }, + { /* 1403 */ + 142, + /* MMX_PADDDirr */ + }, + { /* 1404 */ + 141, + /* MMX_PADDQirm */ + }, + { /* 1405 */ + 142, + /* MMX_PADDQirr */ + }, + { /* 1406 */ + 141, + /* MMX_PADDSBirm */ + }, + { /* 1407 */ + 142, + /* MMX_PADDSBirr */ + }, + { /* 1408 */ + 141, + /* MMX_PADDSWirm */ + }, + { /* 1409 */ + 142, + /* MMX_PADDSWirr */ + }, + { /* 1410 */ + 141, + /* MMX_PADDUSBirm */ + }, + { /* 1411 */ + 142, + /* MMX_PADDUSBirr */ + }, + { /* 1412 */ + 141, + /* MMX_PADDUSWirm */ + }, + { /* 1413 */ + 142, + /* MMX_PADDUSWirr */ + }, + { /* 1414 */ + 141, + /* MMX_PADDWirm */ + }, + { /* 1415 */ + 142, + /* MMX_PADDWirr */ + }, + { /* 1416 */ + 143, + /* MMX_PALIGNRrmi */ + }, + { /* 1417 */ + 144, + /* MMX_PALIGNRrri */ + }, + { /* 1418 */ + 141, + /* MMX_PANDNirm */ + }, + { /* 1419 */ + 142, + /* MMX_PANDNirr */ + }, + { /* 1420 */ + 141, + /* MMX_PANDirm */ + }, + { /* 1421 */ + 142, + /* MMX_PANDirr */ + }, + { /* 1422 */ + 141, + /* MMX_PAVGBirm */ + }, + { /* 1423 */ + 142, + /* MMX_PAVGBirr */ + }, + { /* 1424 */ + 141, + /* MMX_PAVGWirm */ + }, + { /* 1425 */ + 142, + /* MMX_PAVGWirr */ + }, + { /* 1426 */ + 141, + /* MMX_PCMPEQBirm */ + }, + { /* 1427 */ + 142, + /* MMX_PCMPEQBirr */ + }, + { /* 1428 */ + 141, + /* MMX_PCMPEQDirm */ + }, + { /* 1429 */ + 142, + /* MMX_PCMPEQDirr */ + }, + { /* 1430 */ + 141, + /* MMX_PCMPEQWirm */ + }, + { /* 1431 */ + 142, + /* MMX_PCMPEQWirr */ + }, + { /* 1432 */ + 141, + /* MMX_PCMPGTBirm */ + }, + { /* 1433 */ + 142, + /* MMX_PCMPGTBirr */ + }, + { /* 1434 */ + 141, + /* MMX_PCMPGTDirm */ + }, + { /* 1435 */ + 142, + /* MMX_PCMPGTDirr */ + }, + { /* 1436 */ + 141, + /* MMX_PCMPGTWirm */ + }, + { /* 1437 */ + 142, + /* MMX_PCMPGTWirr */ + }, + { /* 1438 */ + 145, + /* MMX_PEXTRWrr */ + }, + { /* 1439 */ + 141, + /* MMX_PHADDDrm */ + }, + { /* 1440 */ + 142, + /* MMX_PHADDDrr */ + }, + { /* 1441 */ + 141, + /* MMX_PHADDSWrm */ + }, + { /* 1442 */ + 142, + /* MMX_PHADDSWrr */ + }, + { /* 1443 */ + 141, + /* MMX_PHADDWrm */ + }, + { /* 1444 */ + 142, + /* MMX_PHADDWrr */ + }, + { /* 1445 */ + 141, + /* MMX_PHSUBDrm */ + }, + { /* 1446 */ + 142, + /* MMX_PHSUBDrr */ + }, + { /* 1447 */ + 141, + /* MMX_PHSUBSWrm */ + }, + { /* 1448 */ + 142, + /* MMX_PHSUBSWrr */ + }, + { /* 1449 */ + 141, + /* MMX_PHSUBWrm */ + }, + { /* 1450 */ + 142, + /* MMX_PHSUBWrr */ + }, + { /* 1451 */ + 143, + /* MMX_PINSRWrm */ + }, + { /* 1452 */ + 146, + /* MMX_PINSRWrr */ + }, + { /* 1453 */ + 141, + /* MMX_PMADDUBSWrm */ + }, + { /* 1454 */ + 142, + /* MMX_PMADDUBSWrr */ + }, + { /* 1455 */ + 141, + /* MMX_PMADDWDirm */ + }, + { /* 1456 */ + 142, + /* MMX_PMADDWDirr */ + }, + { /* 1457 */ + 141, + /* MMX_PMAXSWirm */ + }, + { /* 1458 */ + 142, + /* MMX_PMAXSWirr */ + }, + { /* 1459 */ + 141, + /* MMX_PMAXUBirm */ + }, + { /* 1460 */ + 142, + /* MMX_PMAXUBirr */ + }, + { /* 1461 */ + 141, + /* MMX_PMINSWirm */ + }, + { /* 1462 */ + 142, + /* MMX_PMINSWirr */ + }, + { /* 1463 */ + 141, + /* MMX_PMINUBirm */ + }, + { /* 1464 */ + 142, + /* MMX_PMINUBirr */ + }, + { /* 1465 */ + 147, + /* MMX_PMOVMSKBrr */ + }, + { /* 1466 */ + 141, + /* MMX_PMULHRSWrm */ + }, + { /* 1467 */ + 142, + /* MMX_PMULHRSWrr */ + }, + { /* 1468 */ + 141, + /* MMX_PMULHUWirm */ + }, + { /* 1469 */ + 142, + /* MMX_PMULHUWirr */ + }, + { /* 1470 */ + 141, + /* MMX_PMULHWirm */ + }, + { /* 1471 */ + 142, + /* MMX_PMULHWirr */ + }, + { /* 1472 */ + 141, + /* MMX_PMULLWirm */ + }, + { /* 1473 */ + 142, + /* MMX_PMULLWirr */ + }, + { /* 1474 */ + 141, + /* MMX_PMULUDQirm */ + }, + { /* 1475 */ + 142, + /* MMX_PMULUDQirr */ + }, + { /* 1476 */ + 141, + /* MMX_PORirm */ + }, + { /* 1477 */ + 142, + /* MMX_PORirr */ + }, + { /* 1478 */ + 141, + /* MMX_PSADBWirm */ + }, + { /* 1479 */ + 142, + /* MMX_PSADBWirr */ + }, + { /* 1480 */ + 141, + /* MMX_PSHUFBrm */ + }, + { /* 1481 */ + 142, + /* MMX_PSHUFBrr */ + }, + { /* 1482 */ + 148, + /* MMX_PSHUFWmi */ + }, + { /* 1483 */ + 149, + /* MMX_PSHUFWri */ + }, + { /* 1484 */ + 141, + /* MMX_PSIGNBrm */ + }, + { /* 1485 */ + 142, + /* MMX_PSIGNBrr */ + }, + { /* 1486 */ + 141, + /* MMX_PSIGNDrm */ + }, + { /* 1487 */ + 142, + /* MMX_PSIGNDrr */ + }, + { /* 1488 */ + 141, + /* MMX_PSIGNWrm */ + }, + { /* 1489 */ + 142, + /* MMX_PSIGNWrr */ + }, + { /* 1490 */ + 150, + /* MMX_PSLLDri */ + }, + { /* 1491 */ + 141, + /* MMX_PSLLDrm */ + }, + { /* 1492 */ + 142, + /* MMX_PSLLDrr */ + }, + { /* 1493 */ + 150, + /* MMX_PSLLQri */ + }, + { /* 1494 */ + 141, + /* MMX_PSLLQrm */ + }, + { /* 1495 */ + 142, + /* MMX_PSLLQrr */ + }, + { /* 1496 */ + 150, + /* MMX_PSLLWri */ + }, + { /* 1497 */ + 141, + /* MMX_PSLLWrm */ + }, + { /* 1498 */ + 142, + /* MMX_PSLLWrr */ + }, + { /* 1499 */ + 150, + /* MMX_PSRADri */ + }, + { /* 1500 */ + 141, + /* MMX_PSRADrm */ + }, + { /* 1501 */ + 142, + /* MMX_PSRADrr */ + }, + { /* 1502 */ + 150, + /* MMX_PSRAWri */ + }, + { /* 1503 */ + 141, + /* MMX_PSRAWrm */ + }, + { /* 1504 */ + 142, + /* MMX_PSRAWrr */ + }, + { /* 1505 */ + 150, + /* MMX_PSRLDri */ + }, + { /* 1506 */ + 141, + /* MMX_PSRLDrm */ + }, + { /* 1507 */ + 142, + /* MMX_PSRLDrr */ + }, + { /* 1508 */ + 150, + /* MMX_PSRLQri */ + }, + { /* 1509 */ + 141, + /* MMX_PSRLQrm */ + }, + { /* 1510 */ + 142, + /* MMX_PSRLQrr */ + }, + { /* 1511 */ + 150, + /* MMX_PSRLWri */ + }, + { /* 1512 */ + 141, + /* MMX_PSRLWrm */ + }, + { /* 1513 */ + 142, + /* MMX_PSRLWrr */ + }, + { /* 1514 */ + 141, + /* MMX_PSUBBirm */ + }, + { /* 1515 */ + 142, + /* MMX_PSUBBirr */ + }, + { /* 1516 */ + 141, + /* MMX_PSUBDirm */ + }, + { /* 1517 */ + 142, + /* MMX_PSUBDirr */ + }, + { /* 1518 */ + 141, + /* MMX_PSUBQirm */ + }, + { /* 1519 */ + 142, + /* MMX_PSUBQirr */ + }, + { /* 1520 */ + 141, + /* MMX_PSUBSBirm */ + }, + { /* 1521 */ + 142, + /* MMX_PSUBSBirr */ + }, + { /* 1522 */ + 141, + /* MMX_PSUBSWirm */ + }, + { /* 1523 */ + 142, + /* MMX_PSUBSWirr */ + }, + { /* 1524 */ + 141, + /* MMX_PSUBUSBirm */ + }, + { /* 1525 */ + 142, + /* MMX_PSUBUSBirr */ + }, + { /* 1526 */ + 141, + /* MMX_PSUBUSWirm */ + }, + { /* 1527 */ + 142, + /* MMX_PSUBUSWirr */ + }, + { /* 1528 */ + 141, + /* MMX_PSUBWirm */ + }, + { /* 1529 */ + 142, + /* MMX_PSUBWirr */ + }, + { /* 1530 */ + 141, + /* MMX_PUNPCKHBWirm */ + }, + { /* 1531 */ + 142, + /* MMX_PUNPCKHBWirr */ + }, + { /* 1532 */ + 141, + /* MMX_PUNPCKHDQirm */ + }, + { /* 1533 */ + 142, + /* MMX_PUNPCKHDQirr */ + }, + { /* 1534 */ + 141, + /* MMX_PUNPCKHWDirm */ + }, + { /* 1535 */ + 142, + /* MMX_PUNPCKHWDirr */ + }, + { /* 1536 */ + 141, + /* MMX_PUNPCKLBWirm */ + }, + { /* 1537 */ + 142, + /* MMX_PUNPCKLBWirr */ + }, + { /* 1538 */ + 141, + /* MMX_PUNPCKLDQirm */ + }, + { /* 1539 */ + 142, + /* MMX_PUNPCKLDQirr */ + }, + { /* 1540 */ + 141, + /* MMX_PUNPCKLWDirm */ + }, + { /* 1541 */ + 142, + /* MMX_PUNPCKLWDirr */ + }, + { /* 1542 */ + 141, + /* MMX_PXORirm */ + }, + { /* 1543 */ + 142, + /* MMX_PXORirr */ + }, + { /* 1544 */ + 0, + /* MONITORXrrr */ + }, + { /* 1545 */ + 0, + /* MONITORrrr */ + }, + { /* 1546 */ + 0, + /* MONTMUL */ + }, + { /* 1547 */ + 151, + /* MOV16ao16 */ + }, + { /* 1548 */ + 151, + /* MOV16ao32 */ + }, + { /* 1549 */ + 151, + /* MOV16ao64 */ + }, + { /* 1550 */ + 3, + /* MOV16mi */ + }, + { /* 1551 */ + 5, + /* MOV16mr */ + }, + { /* 1552 */ + 152, + /* MOV16ms */ + }, + { /* 1553 */ + 151, + /* MOV16o16a */ + }, + { /* 1554 */ + 151, + /* MOV16o32a */ + }, + { /* 1555 */ + 151, + /* MOV16o64a */ + }, + { /* 1556 */ + 153, + /* MOV16ri */ + }, + { /* 1557 */ + 74, + /* MOV16ri_alt */ + }, + { /* 1558 */ + 60, + /* MOV16rm */ + }, + { /* 1559 */ + 67, + /* MOV16rr */ + }, + { /* 1560 */ + 61, + /* MOV16rr_REV */ + }, + { /* 1561 */ + 154, + /* MOV16rs */ + }, + { /* 1562 */ + 155, + /* MOV16sm */ + }, + { /* 1563 */ + 156, + /* MOV16sr */ + }, + { /* 1564 */ + 151, + /* MOV32ao16 */ + }, + { /* 1565 */ + 151, + /* MOV32ao32 */ + }, + { /* 1566 */ + 151, + /* MOV32ao64 */ + }, + { /* 1567 */ + 157, + /* MOV32cr */ + }, + { /* 1568 */ + 158, + /* MOV32dr */ + }, + { /* 1569 */ + 3, + /* MOV32mi */ + }, + { /* 1570 */ + 5, + /* MOV32mr */ + }, + { /* 1571 */ + 151, + /* MOV32o16a */ + }, + { /* 1572 */ + 151, + /* MOV32o32a */ + }, + { /* 1573 */ + 151, + /* MOV32o64a */ + }, + { /* 1574 */ + 159, + /* MOV32rc */ + }, + { /* 1575 */ + 160, + /* MOV32rd */ + }, + { /* 1576 */ + 153, + /* MOV32ri */ + }, + { /* 1577 */ + 74, + /* MOV32ri_alt */ + }, + { /* 1578 */ + 60, + /* MOV32rm */ + }, + { /* 1579 */ + 67, + /* MOV32rr */ + }, + { /* 1580 */ + 61, + /* MOV32rr_REV */ + }, + { /* 1581 */ + 154, + /* MOV32rs */ + }, + { /* 1582 */ + 156, + /* MOV32sr */ + }, + { /* 1583 */ + 151, + /* MOV64ao32 */ + }, + { /* 1584 */ + 151, + /* MOV64ao64 */ + }, + { /* 1585 */ + 161, + /* MOV64cr */ + }, + { /* 1586 */ + 162, + /* MOV64dr */ + }, + { /* 1587 */ + 12, + /* MOV64mi32 */ + }, + { /* 1588 */ + 13, + /* MOV64mr */ + }, + { /* 1589 */ + 151, + /* MOV64o32a */ + }, + { /* 1590 */ + 151, + /* MOV64o64a */ + }, + { /* 1591 */ + 163, + /* MOV64rc */ + }, + { /* 1592 */ + 164, + /* MOV64rd */ + }, + { /* 1593 */ + 165, + /* MOV64ri */ + }, + { /* 1594 */ + 75, + /* MOV64ri32 */ + }, + { /* 1595 */ + 62, + /* MOV64rm */ + }, + { /* 1596 */ + 69, + /* MOV64rr */ + }, + { /* 1597 */ + 63, + /* MOV64rr_REV */ + }, + { /* 1598 */ + 166, + /* MOV64rs */ + }, + { /* 1599 */ + 167, + /* MOV64sr */ + }, + { /* 1600 */ + 30, + /* MOV64toPQIrm */ + }, + { /* 1601 */ + 90, + /* MOV64toPQIrr */ + }, + { /* 1602 */ + 0, + /* */ + }, + { /* 1603 */ + 0, + /* */ + }, + { /* 1604 */ + 151, + /* MOV8ao16 */ + }, + { /* 1605 */ + 151, + /* MOV8ao32 */ + }, + { /* 1606 */ + 151, + /* MOV8ao64 */ + }, + { /* 1607 */ + 4, + /* MOV8mi */ + }, + { /* 1608 */ + 19, + /* MOV8mr */ + }, + { /* 1609 */ + 0, + /* */ + }, + { /* 1610 */ + 151, + /* MOV8o16a */ + }, + { /* 1611 */ + 151, + /* MOV8o32a */ + }, + { /* 1612 */ + 151, + /* MOV8o64a */ + }, + { /* 1613 */ + 168, + /* MOV8ri */ + }, + { /* 1614 */ + 76, + /* MOV8ri_alt */ + }, + { /* 1615 */ + 77, + /* MOV8rm */ + }, + { /* 1616 */ + 0, + /* */ + }, + { /* 1617 */ + 78, + /* MOV8rr */ + }, + { /* 1618 */ + 0, + /* */ + }, + { /* 1619 */ + 79, + /* MOV8rr_REV */ + }, + { /* 1620 */ + 169, + /* MOVAPDmr */ + }, + { /* 1621 */ + 30, + /* MOVAPDrm */ + }, + { /* 1622 */ + 31, + /* MOVAPDrr */ + }, + { /* 1623 */ + 170, + /* MOVAPDrr_REV */ + }, + { /* 1624 */ + 169, + /* MOVAPSmr */ + }, + { /* 1625 */ + 30, + /* MOVAPSrm */ + }, + { /* 1626 */ + 31, + /* MOVAPSrr */ + }, + { /* 1627 */ + 170, + /* MOVAPSrr_REV */ + }, + { /* 1628 */ + 5, + /* MOVBE16mr */ + }, + { /* 1629 */ + 60, + /* MOVBE16rm */ + }, + { /* 1630 */ + 5, + /* MOVBE32mr */ + }, + { /* 1631 */ + 60, + /* MOVBE32rm */ + }, + { /* 1632 */ + 13, + /* MOVBE64mr */ + }, + { /* 1633 */ + 62, + /* MOVBE64rm */ + }, + { /* 1634 */ + 30, + /* MOVDDUPrm */ + }, + { /* 1635 */ + 31, + /* MOVDDUPrr */ + }, + { /* 1636 */ + 30, + /* MOVDI2PDIrm */ + }, + { /* 1637 */ + 89, + /* MOVDI2PDIrr */ + }, + { /* 1638 */ + 0, + /* */ + }, + { /* 1639 */ + 0, + /* */ + }, + { /* 1640 */ + 171, + /* MOVDIR64B16 */ + }, + { /* 1641 */ + 87, + /* MOVDIR64B32 */ + }, + { /* 1642 */ + 62, + /* MOVDIR64B64 */ + }, + { /* 1643 */ + 172, + /* MOVDIRI32 */ + }, + { /* 1644 */ + 13, + /* MOVDIRI64 */ + }, + { /* 1645 */ + 169, + /* MOVDQAmr */ + }, + { /* 1646 */ + 30, + /* MOVDQArm */ + }, + { /* 1647 */ + 31, + /* MOVDQArr */ + }, + { /* 1648 */ + 170, + /* MOVDQArr_REV */ + }, + { /* 1649 */ + 169, + /* MOVDQUmr */ + }, + { /* 1650 */ + 30, + /* MOVDQUrm */ + }, + { /* 1651 */ + 31, + /* MOVDQUrr */ + }, + { /* 1652 */ + 170, + /* MOVDQUrr_REV */ + }, + { /* 1653 */ + 27, + /* MOVHLPSrr */ + }, + { /* 1654 */ + 169, + /* MOVHPDmr */ + }, + { /* 1655 */ + 26, + /* MOVHPDrm */ + }, + { /* 1656 */ + 169, + /* MOVHPSmr */ + }, + { /* 1657 */ + 26, + /* MOVHPSrm */ + }, + { /* 1658 */ + 27, + /* MOVLHPSrr */ + }, + { /* 1659 */ + 169, + /* MOVLPDmr */ + }, + { /* 1660 */ + 26, + /* MOVLPDrm */ + }, + { /* 1661 */ + 169, + /* MOVLPSmr */ + }, + { /* 1662 */ + 26, + /* MOVLPSrm */ + }, + { /* 1663 */ + 88, + /* MOVMSKPDrr */ + }, + { /* 1664 */ + 88, + /* MOVMSKPSrr */ + }, + { /* 1665 */ + 30, + /* MOVNTDQArm */ + }, + { /* 1666 */ + 169, + /* MOVNTDQmr */ + }, + { /* 1667 */ + 13, + /* MOVNTI_64mr */ + }, + { /* 1668 */ + 172, + /* MOVNTImr */ + }, + { /* 1669 */ + 169, + /* MOVNTPDmr */ + }, + { /* 1670 */ + 169, + /* MOVNTPSmr */ + }, + { /* 1671 */ + 169, + /* MOVNTSD */ + }, + { /* 1672 */ + 169, + /* MOVNTSS */ + }, + { /* 1673 */ + 169, + /* MOVPDI2DImr */ + }, + { /* 1674 */ + 173, + /* MOVPDI2DIrr */ + }, + { /* 1675 */ + 169, + /* MOVPQI2QImr */ + }, + { /* 1676 */ + 170, + /* MOVPQI2QIrr */ + }, + { /* 1677 */ + 169, + /* MOVPQIto64mr */ + }, + { /* 1678 */ + 174, + /* MOVPQIto64rr */ + }, + { /* 1679 */ + 30, + /* MOVQI2PQIrm */ + }, + { /* 1680 */ + 82, + /* MOVSB */ + }, + { /* 1681 */ + 169, + /* MOVSDmr */ + }, + { /* 1682 */ + 30, + /* MOVSDrm */ + }, + { /* 1683 */ + 27, + /* MOVSDrr */ + }, + { /* 1684 */ + 175, + /* MOVSDrr_REV */ + }, + { /* 1685 */ + 0, + /* */ + }, + { /* 1686 */ + 0, + /* */ + }, + { /* 1687 */ + 30, + /* MOVSHDUPrm */ + }, + { /* 1688 */ + 31, + /* MOVSHDUPrr */ + }, + { /* 1689 */ + 82, + /* MOVSL */ + }, + { /* 1690 */ + 30, + /* MOVSLDUPrm */ + }, + { /* 1691 */ + 31, + /* MOVSLDUPrr */ + }, + { /* 1692 */ + 82, + /* MOVSQ */ + }, + { /* 1693 */ + 0, + /* */ + }, + { /* 1694 */ + 0, + /* */ + }, + { /* 1695 */ + 169, + /* MOVSSmr */ + }, + { /* 1696 */ + 30, + /* MOVSSrm */ + }, + { /* 1697 */ + 27, + /* MOVSSrr */ + }, + { /* 1698 */ + 175, + /* MOVSSrr_REV */ + }, + { /* 1699 */ + 82, + /* MOVSW */ + }, + { /* 1700 */ + 60, + /* MOVSX16rm16 */ + }, + { /* 1701 */ + 60, + /* MOVSX16rm8 */ + }, + { /* 1702 */ + 61, + /* MOVSX16rr16 */ + }, + { /* 1703 */ + 176, + /* MOVSX16rr8 */ + }, + { /* 1704 */ + 60, + /* MOVSX32rm16 */ + }, + { /* 1705 */ + 60, + /* MOVSX32rm8 */ + }, + { /* 1706 */ + 0, + /* */ + }, + { /* 1707 */ + 177, + /* MOVSX32rr16 */ + }, + { /* 1708 */ + 176, + /* MOVSX32rr8 */ + }, + { /* 1709 */ + 0, + /* */ + }, + { /* 1710 */ + 62, + /* MOVSX64rm16 */ + }, + { /* 1711 */ + 62, + /* MOVSX64rm32 */ + }, + { /* 1712 */ + 62, + /* MOVSX64rm8 */ + }, + { /* 1713 */ + 178, + /* MOVSX64rr16 */ + }, + { /* 1714 */ + 122, + /* MOVSX64rr32 */ + }, + { /* 1715 */ + 179, + /* MOVSX64rr8 */ + }, + { /* 1716 */ + 169, + /* MOVUPDmr */ + }, + { /* 1717 */ + 30, + /* MOVUPDrm */ + }, + { /* 1718 */ + 31, + /* MOVUPDrr */ + }, + { /* 1719 */ + 170, + /* MOVUPDrr_REV */ + }, + { /* 1720 */ + 169, + /* MOVUPSmr */ + }, + { /* 1721 */ + 30, + /* MOVUPSrm */ + }, + { /* 1722 */ + 31, + /* MOVUPSrr */ + }, + { /* 1723 */ + 170, + /* MOVUPSrr_REV */ + }, + { /* 1724 */ + 31, + /* MOVZPQILo2PQIrr */ + }, + { /* 1725 */ + 60, + /* MOVZX16rm16 */ + }, + { /* 1726 */ + 60, + /* MOVZX16rm8 */ + }, + { /* 1727 */ + 61, + /* MOVZX16rr16 */ + }, + { /* 1728 */ + 176, + /* MOVZX16rr8 */ + }, + { /* 1729 */ + 60, + /* MOVZX32rm16 */ + }, + { /* 1730 */ + 60, + /* MOVZX32rm8 */ + }, + { /* 1731 */ + 0, + /* */ + }, + { /* 1732 */ + 177, + /* MOVZX32rr16 */ + }, + { /* 1733 */ + 176, + /* MOVZX32rr8 */ + }, + { /* 1734 */ + 0, + /* */ + }, + { /* 1735 */ + 62, + /* MOVZX64rm16 */ + }, + { /* 1736 */ + 62, + /* MOVZX64rm8 */ + }, + { /* 1737 */ + 178, + /* MOVZX64rr16 */ + }, + { /* 1738 */ + 179, + /* MOVZX64rr8 */ + }, + { /* 1739 */ + 52, + /* MPSADBWrmi */ + }, + { /* 1740 */ + 53, + /* MPSADBWrri */ + }, + { /* 1741 */ + 28, + /* MUL16m */ + }, + { /* 1742 */ + 70, + /* MUL16r */ + }, + { /* 1743 */ + 28, + /* MUL32m */ + }, + { /* 1744 */ + 70, + /* MUL32r */ + }, + { /* 1745 */ + 28, + /* MUL64m */ + }, + { /* 1746 */ + 72, + /* MUL64r */ + }, + { /* 1747 */ + 28, + /* MUL8m */ + }, + { /* 1748 */ + 94, + /* MUL8r */ + }, + { /* 1749 */ + 26, + /* MULPDrm */ + }, + { /* 1750 */ + 27, + /* MULPDrr */ + }, + { /* 1751 */ + 26, + /* MULPSrm */ + }, + { /* 1752 */ + 27, + /* MULPSrr */ + }, + { /* 1753 */ + 26, + /* MULSDrm */ + }, + { /* 1754 */ + 0, + /* */ + }, + { /* 1755 */ + 27, + /* MULSDrr */ + }, + { /* 1756 */ + 0, + /* */ + }, + { /* 1757 */ + 26, + /* MULSSrm */ + }, + { /* 1758 */ + 0, + /* */ + }, + { /* 1759 */ + 27, + /* MULSSrr */ + }, + { /* 1760 */ + 0, + /* */ + }, + { /* 1761 */ + 34, + /* MULX32rm */ + }, + { /* 1762 */ + 35, + /* MULX32rr */ + }, + { /* 1763 */ + 36, + /* MULX64rm */ + }, + { /* 1764 */ + 37, + /* MULX64rr */ + }, + { /* 1765 */ + 28, + /* MUL_F32m */ + }, + { /* 1766 */ + 28, + /* MUL_F64m */ + }, + { /* 1767 */ + 28, + /* MUL_FI16m */ + }, + { /* 1768 */ + 28, + /* MUL_FI32m */ + }, + { /* 1769 */ + 29, + /* MUL_FPrST0 */ + }, + { /* 1770 */ + 29, + /* MUL_FST0r */ + }, + { /* 1771 */ + 0, + /* */ + }, + { /* 1772 */ + 0, + /* */ + }, + { /* 1773 */ + 0, + /* */ + }, + { /* 1774 */ + 0, + /* */ + }, + { /* 1775 */ + 0, + /* */ + }, + { /* 1776 */ + 0, + /* */ + }, + { /* 1777 */ + 0, + /* */ + }, + { /* 1778 */ + 0, + /* */ + }, + { /* 1779 */ + 0, + /* */ + }, + { /* 1780 */ + 0, + /* */ + }, + { /* 1781 */ + 0, + /* */ + }, + { /* 1782 */ + 0, + /* */ + }, + { /* 1783 */ + 0, + /* */ + }, + { /* 1784 */ + 0, + /* */ + }, + { /* 1785 */ + 29, + /* MUL_FrST0 */ + }, + { /* 1786 */ + 0, + /* MWAITXrrr */ + }, + { /* 1787 */ + 0, + /* MWAITrr */ + }, + { /* 1788 */ + 28, + /* NEG16m */ + }, + { /* 1789 */ + 91, + /* NEG16r */ + }, + { /* 1790 */ + 28, + /* NEG32m */ + }, + { /* 1791 */ + 91, + /* NEG32r */ + }, + { /* 1792 */ + 28, + /* NEG64m */ + }, + { /* 1793 */ + 92, + /* NEG64r */ + }, + { /* 1794 */ + 28, + /* NEG8m */ + }, + { /* 1795 */ + 93, + /* NEG8r */ + }, + { /* 1796 */ + 0, + /* NOOP */ + }, + { /* 1797 */ + 28, + /* NOOP18_16m4 */ + }, + { /* 1798 */ + 28, + /* NOOP18_16m5 */ + }, + { /* 1799 */ + 28, + /* NOOP18_16m6 */ + }, + { /* 1800 */ + 28, + /* NOOP18_16m7 */ + }, + { /* 1801 */ + 70, + /* NOOP18_16r4 */ + }, + { /* 1802 */ + 70, + /* NOOP18_16r5 */ + }, + { /* 1803 */ + 70, + /* NOOP18_16r6 */ + }, + { /* 1804 */ + 70, + /* NOOP18_16r7 */ + }, + { /* 1805 */ + 28, + /* NOOP18_m4 */ + }, + { /* 1806 */ + 28, + /* NOOP18_m5 */ + }, + { /* 1807 */ + 28, + /* NOOP18_m6 */ + }, + { /* 1808 */ + 28, + /* NOOP18_m7 */ + }, + { /* 1809 */ + 70, + /* NOOP18_r4 */ + }, + { /* 1810 */ + 70, + /* NOOP18_r5 */ + }, + { /* 1811 */ + 70, + /* NOOP18_r6 */ + }, + { /* 1812 */ + 70, + /* NOOP18_r7 */ + }, + { /* 1813 */ + 61, + /* NOOP19rr */ + }, + { /* 1814 */ + 28, + /* NOOPL */ + }, + { /* 1815 */ + 28, + /* NOOPL_19 */ + }, + { /* 1816 */ + 28, + /* NOOPL_1d */ + }, + { /* 1817 */ + 28, + /* NOOPL_1e */ + }, + { /* 1818 */ + 70, + /* NOOPLr */ + }, + { /* 1819 */ + 28, + /* NOOPQ */ + }, + { /* 1820 */ + 72, + /* NOOPQr */ + }, + { /* 1821 */ + 28, + /* NOOPW */ + }, + { /* 1822 */ + 28, + /* NOOPW_19 */ + }, + { /* 1823 */ + 28, + /* NOOPW_1c */ + }, + { /* 1824 */ + 28, + /* NOOPW_1d */ + }, + { /* 1825 */ + 28, + /* NOOPW_1e */ + }, + { /* 1826 */ + 70, + /* NOOPWr */ + }, + { /* 1827 */ + 28, + /* NOT16m */ + }, + { /* 1828 */ + 91, + /* NOT16r */ + }, + { /* 1829 */ + 28, + /* NOT32m */ + }, + { /* 1830 */ + 91, + /* NOT32r */ + }, + { /* 1831 */ + 28, + /* NOT64m */ + }, + { /* 1832 */ + 92, + /* NOT64r */ + }, + { /* 1833 */ + 28, + /* NOT8m */ + }, + { /* 1834 */ + 93, + /* NOT8r */ + }, + { /* 1835 */ + 2, + /* OR16i16 */ + }, + { /* 1836 */ + 3, + /* OR16mi */ + }, + { /* 1837 */ + 4, + /* OR16mi8 */ + }, + { /* 1838 */ + 5, + /* OR16mr */ + }, + { /* 1839 */ + 6, + /* OR16ri */ + }, + { /* 1840 */ + 7, + /* OR16ri8 */ + }, + { /* 1841 */ + 8, + /* OR16rm */ + }, + { /* 1842 */ + 9, + /* OR16rr */ + }, + { /* 1843 */ + 10, + /* OR16rr_REV */ + }, + { /* 1844 */ + 2, + /* OR32i32 */ + }, + { /* 1845 */ + 3, + /* OR32mi */ + }, + { /* 1846 */ + 4, + /* OR32mi8 */ + }, + { /* 1847 */ + 5, + /* OR32mr */ + }, + { /* 1848 */ + 6, + /* OR32ri */ + }, + { /* 1849 */ + 7, + /* OR32ri8 */ + }, + { /* 1850 */ + 8, + /* OR32rm */ + }, + { /* 1851 */ + 9, + /* OR32rr */ + }, + { /* 1852 */ + 10, + /* OR32rr_REV */ + }, + { /* 1853 */ + 11, + /* OR64i32 */ + }, + { /* 1854 */ + 12, + /* OR64mi32 */ + }, + { /* 1855 */ + 4, + /* OR64mi8 */ + }, + { /* 1856 */ + 13, + /* OR64mr */ + }, + { /* 1857 */ + 14, + /* OR64ri32 */ + }, + { /* 1858 */ + 15, + /* OR64ri8 */ + }, + { /* 1859 */ + 16, + /* OR64rm */ + }, + { /* 1860 */ + 17, + /* OR64rr */ + }, + { /* 1861 */ + 18, + /* OR64rr_REV */ + }, + { /* 1862 */ + 1, + /* OR8i8 */ + }, + { /* 1863 */ + 4, + /* OR8mi */ + }, + { /* 1864 */ + 4, + /* OR8mi8 */ + }, + { /* 1865 */ + 19, + /* OR8mr */ + }, + { /* 1866 */ + 20, + /* OR8ri */ + }, + { /* 1867 */ + 20, + /* OR8ri8 */ + }, + { /* 1868 */ + 21, + /* OR8rm */ + }, + { /* 1869 */ + 22, + /* OR8rr */ + }, + { /* 1870 */ + 23, + /* OR8rr_REV */ + }, + { /* 1871 */ + 26, + /* ORPDrm */ + }, + { /* 1872 */ + 27, + /* ORPDrr */ + }, + { /* 1873 */ + 26, + /* ORPSrm */ + }, + { /* 1874 */ + 27, + /* ORPSrr */ + }, + { /* 1875 */ + 107, + /* OUT16ir */ + }, + { /* 1876 */ + 0, + /* OUT16rr */ + }, + { /* 1877 */ + 107, + /* OUT32ir */ + }, + { /* 1878 */ + 0, + /* OUT32rr */ + }, + { /* 1879 */ + 107, + /* OUT8ir */ + }, + { /* 1880 */ + 0, + /* OUT8rr */ + }, + { /* 1881 */ + 124, + /* OUTSB */ + }, + { /* 1882 */ + 124, + /* OUTSL */ + }, + { /* 1883 */ + 124, + /* OUTSW */ + }, + { /* 1884 */ + 30, + /* PABSBrm */ + }, + { /* 1885 */ + 31, + /* PABSBrr */ + }, + { /* 1886 */ + 30, + /* PABSDrm */ + }, + { /* 1887 */ + 31, + /* PABSDrr */ + }, + { /* 1888 */ + 30, + /* PABSWrm */ + }, + { /* 1889 */ + 31, + /* PABSWrr */ + }, + { /* 1890 */ + 26, + /* PACKSSDWrm */ + }, + { /* 1891 */ + 27, + /* PACKSSDWrr */ + }, + { /* 1892 */ + 26, + /* PACKSSWBrm */ + }, + { /* 1893 */ + 27, + /* PACKSSWBrr */ + }, + { /* 1894 */ + 26, + /* PACKUSDWrm */ + }, + { /* 1895 */ + 27, + /* PACKUSDWrr */ + }, + { /* 1896 */ + 26, + /* PACKUSWBrm */ + }, + { /* 1897 */ + 27, + /* PACKUSWBrr */ + }, + { /* 1898 */ + 26, + /* PADDBrm */ + }, + { /* 1899 */ + 27, + /* PADDBrr */ + }, + { /* 1900 */ + 26, + /* PADDDrm */ + }, + { /* 1901 */ + 27, + /* PADDDrr */ + }, + { /* 1902 */ + 26, + /* PADDQrm */ + }, + { /* 1903 */ + 27, + /* PADDQrr */ + }, + { /* 1904 */ + 26, + /* PADDSBrm */ + }, + { /* 1905 */ + 27, + /* PADDSBrr */ + }, + { /* 1906 */ + 26, + /* PADDSWrm */ + }, + { /* 1907 */ + 27, + /* PADDSWrr */ + }, + { /* 1908 */ + 26, + /* PADDUSBrm */ + }, + { /* 1909 */ + 27, + /* PADDUSBrr */ + }, + { /* 1910 */ + 26, + /* PADDUSWrm */ + }, + { /* 1911 */ + 27, + /* PADDUSWrr */ + }, + { /* 1912 */ + 26, + /* PADDWrm */ + }, + { /* 1913 */ + 27, + /* PADDWrr */ + }, + { /* 1914 */ + 52, + /* PALIGNRrmi */ + }, + { /* 1915 */ + 53, + /* PALIGNRrri */ + }, + { /* 1916 */ + 26, + /* PANDNrm */ + }, + { /* 1917 */ + 27, + /* PANDNrr */ + }, + { /* 1918 */ + 26, + /* PANDrm */ + }, + { /* 1919 */ + 27, + /* PANDrr */ + }, + { /* 1920 */ + 0, + /* PAUSE */ + }, + { /* 1921 */ + 26, + /* PAVGBrm */ + }, + { /* 1922 */ + 27, + /* PAVGBrr */ + }, + { /* 1923 */ + 141, + /* PAVGUSBrm */ + }, + { /* 1924 */ + 142, + /* PAVGUSBrr */ + }, + { /* 1925 */ + 26, + /* PAVGWrm */ + }, + { /* 1926 */ + 27, + /* PAVGWrr */ + }, + { /* 1927 */ + 26, + /* PBLENDVBrm0 */ + }, + { /* 1928 */ + 27, + /* PBLENDVBrr0 */ + }, + { /* 1929 */ + 52, + /* PBLENDWrmi */ + }, + { /* 1930 */ + 53, + /* PBLENDWrri */ + }, + { /* 1931 */ + 52, + /* PCLMULQDQrm */ + }, + { /* 1932 */ + 53, + /* PCLMULQDQrr */ + }, + { /* 1933 */ + 26, + /* PCMPEQBrm */ + }, + { /* 1934 */ + 27, + /* PCMPEQBrr */ + }, + { /* 1935 */ + 26, + /* PCMPEQDrm */ + }, + { /* 1936 */ + 27, + /* PCMPEQDrr */ + }, + { /* 1937 */ + 26, + /* PCMPEQQrm */ + }, + { /* 1938 */ + 27, + /* PCMPEQQrr */ + }, + { /* 1939 */ + 26, + /* PCMPEQWrm */ + }, + { /* 1940 */ + 27, + /* PCMPEQWrr */ + }, + { /* 1941 */ + 32, + /* PCMPESTRIrm */ + }, + { /* 1942 */ + 33, + /* PCMPESTRIrr */ + }, + { /* 1943 */ + 32, + /* PCMPESTRMrm */ + }, + { /* 1944 */ + 33, + /* PCMPESTRMrr */ + }, + { /* 1945 */ + 26, + /* PCMPGTBrm */ + }, + { /* 1946 */ + 27, + /* PCMPGTBrr */ + }, + { /* 1947 */ + 26, + /* PCMPGTDrm */ + }, + { /* 1948 */ + 27, + /* PCMPGTDrr */ + }, + { /* 1949 */ + 26, + /* PCMPGTQrm */ + }, + { /* 1950 */ + 27, + /* PCMPGTQrr */ + }, + { /* 1951 */ + 26, + /* PCMPGTWrm */ + }, + { /* 1952 */ + 27, + /* PCMPGTWrr */ + }, + { /* 1953 */ + 32, + /* PCMPISTRIrm */ + }, + { /* 1954 */ + 33, + /* PCMPISTRIrr */ + }, + { /* 1955 */ + 32, + /* PCMPISTRMrm */ + }, + { /* 1956 */ + 33, + /* PCMPISTRMrr */ + }, + { /* 1957 */ + 0, + /* PCONFIG */ + }, + { /* 1958 */ + 34, + /* PDEP32rm */ + }, + { /* 1959 */ + 35, + /* PDEP32rr */ + }, + { /* 1960 */ + 36, + /* PDEP64rm */ + }, + { /* 1961 */ + 37, + /* PDEP64rr */ + }, + { /* 1962 */ + 34, + /* PEXT32rm */ + }, + { /* 1963 */ + 35, + /* PEXT32rr */ + }, + { /* 1964 */ + 36, + /* PEXT64rm */ + }, + { /* 1965 */ + 37, + /* PEXT64rr */ + }, + { /* 1966 */ + 96, + /* PEXTRBmr */ + }, + { /* 1967 */ + 97, + /* PEXTRBrr */ + }, + { /* 1968 */ + 96, + /* PEXTRDmr */ + }, + { /* 1969 */ + 97, + /* PEXTRDrr */ + }, + { /* 1970 */ + 96, + /* PEXTRQmr */ + }, + { /* 1971 */ + 180, + /* PEXTRQrr */ + }, + { /* 1972 */ + 96, + /* PEXTRWmr */ + }, + { /* 1973 */ + 181, + /* PEXTRWrr */ + }, + { /* 1974 */ + 97, + /* PEXTRWrr_REV */ + }, + { /* 1975 */ + 130, + /* PF2IDrm */ + }, + { /* 1976 */ + 134, + /* PF2IDrr */ + }, + { /* 1977 */ + 130, + /* PF2IWrm */ + }, + { /* 1978 */ + 134, + /* PF2IWrr */ + }, + { /* 1979 */ + 141, + /* PFACCrm */ + }, + { /* 1980 */ + 142, + /* PFACCrr */ + }, + { /* 1981 */ + 141, + /* PFADDrm */ + }, + { /* 1982 */ + 142, + /* PFADDrr */ + }, + { /* 1983 */ + 141, + /* PFCMPEQrm */ + }, + { /* 1984 */ + 142, + /* PFCMPEQrr */ + }, + { /* 1985 */ + 141, + /* PFCMPGErm */ + }, + { /* 1986 */ + 142, + /* PFCMPGErr */ + }, + { /* 1987 */ + 141, + /* PFCMPGTrm */ + }, + { /* 1988 */ + 142, + /* PFCMPGTrr */ + }, + { /* 1989 */ + 141, + /* PFMAXrm */ + }, + { /* 1990 */ + 142, + /* PFMAXrr */ + }, + { /* 1991 */ + 141, + /* PFMINrm */ + }, + { /* 1992 */ + 142, + /* PFMINrr */ + }, + { /* 1993 */ + 141, + /* PFMULrm */ + }, + { /* 1994 */ + 142, + /* PFMULrr */ + }, + { /* 1995 */ + 141, + /* PFNACCrm */ + }, + { /* 1996 */ + 142, + /* PFNACCrr */ + }, + { /* 1997 */ + 141, + /* PFPNACCrm */ + }, + { /* 1998 */ + 142, + /* PFPNACCrr */ + }, + { /* 1999 */ + 141, + /* PFRCPIT1rm */ + }, + { /* 2000 */ + 142, + /* PFRCPIT1rr */ + }, + { /* 2001 */ + 141, + /* PFRCPIT2rm */ + }, + { /* 2002 */ + 142, + /* PFRCPIT2rr */ + }, + { /* 2003 */ + 130, + /* PFRCPrm */ + }, + { /* 2004 */ + 134, + /* PFRCPrr */ + }, + { /* 2005 */ + 141, + /* PFRSQIT1rm */ + }, + { /* 2006 */ + 142, + /* PFRSQIT1rr */ + }, + { /* 2007 */ + 130, + /* PFRSQRTrm */ + }, + { /* 2008 */ + 134, + /* PFRSQRTrr */ + }, + { /* 2009 */ + 141, + /* PFSUBRrm */ + }, + { /* 2010 */ + 142, + /* PFSUBRrr */ + }, + { /* 2011 */ + 141, + /* PFSUBrm */ + }, + { /* 2012 */ + 142, + /* PFSUBrr */ + }, + { /* 2013 */ + 26, + /* PHADDDrm */ + }, + { /* 2014 */ + 27, + /* PHADDDrr */ + }, + { /* 2015 */ + 26, + /* PHADDSWrm */ + }, + { /* 2016 */ + 27, + /* PHADDSWrr */ + }, + { /* 2017 */ + 26, + /* PHADDWrm */ + }, + { /* 2018 */ + 27, + /* PHADDWrr */ + }, + { /* 2019 */ + 30, + /* PHMINPOSUWrm */ + }, + { /* 2020 */ + 31, + /* PHMINPOSUWrr */ + }, + { /* 2021 */ + 26, + /* PHSUBDrm */ + }, + { /* 2022 */ + 27, + /* PHSUBDrr */ + }, + { /* 2023 */ + 26, + /* PHSUBSWrm */ + }, + { /* 2024 */ + 27, + /* PHSUBSWrr */ + }, + { /* 2025 */ + 26, + /* PHSUBWrm */ + }, + { /* 2026 */ + 27, + /* PHSUBWrr */ + }, + { /* 2027 */ + 130, + /* PI2FDrm */ + }, + { /* 2028 */ + 134, + /* PI2FDrr */ + }, + { /* 2029 */ + 130, + /* PI2FWrm */ + }, + { /* 2030 */ + 134, + /* PI2FWrr */ + }, + { /* 2031 */ + 52, + /* PINSRBrm */ + }, + { /* 2032 */ + 182, + /* PINSRBrr */ + }, + { /* 2033 */ + 52, + /* PINSRDrm */ + }, + { /* 2034 */ + 182, + /* PINSRDrr */ + }, + { /* 2035 */ + 52, + /* PINSRQrm */ + }, + { /* 2036 */ + 183, + /* PINSRQrr */ + }, + { /* 2037 */ + 52, + /* PINSRWrm */ + }, + { /* 2038 */ + 182, + /* PINSRWrr */ + }, + { /* 2039 */ + 26, + /* PMADDUBSWrm */ + }, + { /* 2040 */ + 27, + /* PMADDUBSWrr */ + }, + { /* 2041 */ + 26, + /* PMADDWDrm */ + }, + { /* 2042 */ + 27, + /* PMADDWDrr */ + }, + { /* 2043 */ + 26, + /* PMAXSBrm */ + }, + { /* 2044 */ + 27, + /* PMAXSBrr */ + }, + { /* 2045 */ + 26, + /* PMAXSDrm */ + }, + { /* 2046 */ + 27, + /* PMAXSDrr */ + }, + { /* 2047 */ + 26, + /* PMAXSWrm */ + }, + { /* 2048 */ + 27, + /* PMAXSWrr */ + }, + { /* 2049 */ + 26, + /* PMAXUBrm */ + }, + { /* 2050 */ + 27, + /* PMAXUBrr */ + }, + { /* 2051 */ + 26, + /* PMAXUDrm */ + }, + { /* 2052 */ + 27, + /* PMAXUDrr */ + }, + { /* 2053 */ + 26, + /* PMAXUWrm */ + }, + { /* 2054 */ + 27, + /* PMAXUWrr */ + }, + { /* 2055 */ + 26, + /* PMINSBrm */ + }, + { /* 2056 */ + 27, + /* PMINSBrr */ + }, + { /* 2057 */ + 26, + /* PMINSDrm */ + }, + { /* 2058 */ + 27, + /* PMINSDrr */ + }, + { /* 2059 */ + 26, + /* PMINSWrm */ + }, + { /* 2060 */ + 27, + /* PMINSWrr */ + }, + { /* 2061 */ + 26, + /* PMINUBrm */ + }, + { /* 2062 */ + 27, + /* PMINUBrr */ + }, + { /* 2063 */ + 26, + /* PMINUDrm */ + }, + { /* 2064 */ + 27, + /* PMINUDrr */ + }, + { /* 2065 */ + 26, + /* PMINUWrm */ + }, + { /* 2066 */ + 27, + /* PMINUWrr */ + }, + { /* 2067 */ + 88, + /* PMOVMSKBrr */ + }, + { /* 2068 */ + 30, + /* PMOVSXBDrm */ + }, + { /* 2069 */ + 31, + /* PMOVSXBDrr */ + }, + { /* 2070 */ + 30, + /* PMOVSXBQrm */ + }, + { /* 2071 */ + 31, + /* PMOVSXBQrr */ + }, + { /* 2072 */ + 30, + /* PMOVSXBWrm */ + }, + { /* 2073 */ + 31, + /* PMOVSXBWrr */ + }, + { /* 2074 */ + 30, + /* PMOVSXDQrm */ + }, + { /* 2075 */ + 31, + /* PMOVSXDQrr */ + }, + { /* 2076 */ + 30, + /* PMOVSXWDrm */ + }, + { /* 2077 */ + 31, + /* PMOVSXWDrr */ + }, + { /* 2078 */ + 30, + /* PMOVSXWQrm */ + }, + { /* 2079 */ + 31, + /* PMOVSXWQrr */ + }, + { /* 2080 */ + 30, + /* PMOVZXBDrm */ + }, + { /* 2081 */ + 31, + /* PMOVZXBDrr */ + }, + { /* 2082 */ + 30, + /* PMOVZXBQrm */ + }, + { /* 2083 */ + 31, + /* PMOVZXBQrr */ + }, + { /* 2084 */ + 30, + /* PMOVZXBWrm */ + }, + { /* 2085 */ + 31, + /* PMOVZXBWrr */ + }, + { /* 2086 */ + 30, + /* PMOVZXDQrm */ + }, + { /* 2087 */ + 31, + /* PMOVZXDQrr */ + }, + { /* 2088 */ + 30, + /* PMOVZXWDrm */ + }, + { /* 2089 */ + 31, + /* PMOVZXWDrr */ + }, + { /* 2090 */ + 30, + /* PMOVZXWQrm */ + }, + { /* 2091 */ + 31, + /* PMOVZXWQrr */ + }, + { /* 2092 */ + 26, + /* PMULDQrm */ + }, + { /* 2093 */ + 27, + /* PMULDQrr */ + }, + { /* 2094 */ + 26, + /* PMULHRSWrm */ + }, + { /* 2095 */ + 27, + /* PMULHRSWrr */ + }, + { /* 2096 */ + 141, + /* PMULHRWrm */ + }, + { /* 2097 */ + 142, + /* PMULHRWrr */ + }, + { /* 2098 */ + 26, + /* PMULHUWrm */ + }, + { /* 2099 */ + 27, + /* PMULHUWrr */ + }, + { /* 2100 */ + 26, + /* PMULHWrm */ + }, + { /* 2101 */ + 27, + /* PMULHWrr */ + }, + { /* 2102 */ + 26, + /* PMULLDrm */ + }, + { /* 2103 */ + 27, + /* PMULLDrr */ + }, + { /* 2104 */ + 26, + /* PMULLWrm */ + }, + { /* 2105 */ + 27, + /* PMULLWrr */ + }, + { /* 2106 */ + 26, + /* PMULUDQrm */ + }, + { /* 2107 */ + 27, + /* PMULUDQrr */ + }, + { /* 2108 */ + 184, + /* POP16r */ + }, + { /* 2109 */ + 28, + /* POP16rmm */ + }, + { /* 2110 */ + 70, + /* POP16rmr */ + }, + { /* 2111 */ + 184, + /* POP32r */ + }, + { /* 2112 */ + 28, + /* POP32rmm */ + }, + { /* 2113 */ + 70, + /* POP32rmr */ + }, + { /* 2114 */ + 185, + /* POP64r */ + }, + { /* 2115 */ + 28, + /* POP64rmm */ + }, + { /* 2116 */ + 72, + /* POP64rmr */ + }, + { /* 2117 */ + 0, + /* POPA16 */ + }, + { /* 2118 */ + 0, + /* POPA32 */ + }, + { /* 2119 */ + 60, + /* POPCNT16rm */ + }, + { /* 2120 */ + 61, + /* POPCNT16rr */ + }, + { /* 2121 */ + 60, + /* POPCNT32rm */ + }, + { /* 2122 */ + 61, + /* POPCNT32rr */ + }, + { /* 2123 */ + 62, + /* POPCNT64rm */ + }, + { /* 2124 */ + 63, + /* POPCNT64rr */ + }, + { /* 2125 */ + 0, + /* POPDS16 */ + }, + { /* 2126 */ + 0, + /* POPDS32 */ + }, + { /* 2127 */ + 0, + /* POPES16 */ + }, + { /* 2128 */ + 0, + /* POPES32 */ + }, + { /* 2129 */ + 0, + /* POPF16 */ + }, + { /* 2130 */ + 0, + /* POPF32 */ + }, + { /* 2131 */ + 0, + /* POPF64 */ + }, + { /* 2132 */ + 0, + /* POPFS16 */ + }, + { /* 2133 */ + 0, + /* POPFS32 */ + }, + { /* 2134 */ + 0, + /* POPFS64 */ + }, + { /* 2135 */ + 0, + /* POPGS16 */ + }, + { /* 2136 */ + 0, + /* POPGS32 */ + }, + { /* 2137 */ + 0, + /* POPGS64 */ + }, + { /* 2138 */ + 0, + /* POPSS16 */ + }, + { /* 2139 */ + 0, + /* POPSS32 */ + }, + { /* 2140 */ + 26, + /* PORrm */ + }, + { /* 2141 */ + 27, + /* PORrr */ + }, + { /* 2142 */ + 28, + /* PREFETCH */ + }, + { /* 2143 */ + 28, + /* PREFETCHNTA */ + }, + { /* 2144 */ + 28, + /* PREFETCHT0 */ + }, + { /* 2145 */ + 28, + /* PREFETCHT1 */ + }, + { /* 2146 */ + 28, + /* PREFETCHT2 */ + }, + { /* 2147 */ + 28, + /* PREFETCHW */ + }, + { /* 2148 */ + 28, + /* PREFETCHWT1 */ + }, + { /* 2149 */ + 26, + /* PSADBWrm */ + }, + { /* 2150 */ + 27, + /* PSADBWrr */ + }, + { /* 2151 */ + 26, + /* PSHUFBrm */ + }, + { /* 2152 */ + 27, + /* PSHUFBrr */ + }, + { /* 2153 */ + 32, + /* PSHUFDmi */ + }, + { /* 2154 */ + 33, + /* PSHUFDri */ + }, + { /* 2155 */ + 32, + /* PSHUFHWmi */ + }, + { /* 2156 */ + 33, + /* PSHUFHWri */ + }, + { /* 2157 */ + 32, + /* PSHUFLWmi */ + }, + { /* 2158 */ + 33, + /* PSHUFLWri */ + }, + { /* 2159 */ + 26, + /* PSIGNBrm */ + }, + { /* 2160 */ + 27, + /* PSIGNBrr */ + }, + { /* 2161 */ + 26, + /* PSIGNDrm */ + }, + { /* 2162 */ + 27, + /* PSIGNDrr */ + }, + { /* 2163 */ + 26, + /* PSIGNWrm */ + }, + { /* 2164 */ + 27, + /* PSIGNWrr */ + }, + { /* 2165 */ + 186, + /* PSLLDQri */ + }, + { /* 2166 */ + 186, + /* PSLLDri */ + }, + { /* 2167 */ + 26, + /* PSLLDrm */ + }, + { /* 2168 */ + 27, + /* PSLLDrr */ + }, + { /* 2169 */ + 186, + /* PSLLQri */ + }, + { /* 2170 */ + 26, + /* PSLLQrm */ + }, + { /* 2171 */ + 27, + /* PSLLQrr */ + }, + { /* 2172 */ + 186, + /* PSLLWri */ + }, + { /* 2173 */ + 26, + /* PSLLWrm */ + }, + { /* 2174 */ + 27, + /* PSLLWrr */ + }, + { /* 2175 */ + 186, + /* PSRADri */ + }, + { /* 2176 */ + 26, + /* PSRADrm */ + }, + { /* 2177 */ + 27, + /* PSRADrr */ + }, + { /* 2178 */ + 186, + /* PSRAWri */ + }, + { /* 2179 */ + 26, + /* PSRAWrm */ + }, + { /* 2180 */ + 27, + /* PSRAWrr */ + }, + { /* 2181 */ + 186, + /* PSRLDQri */ + }, + { /* 2182 */ + 186, + /* PSRLDri */ + }, + { /* 2183 */ + 26, + /* PSRLDrm */ + }, + { /* 2184 */ + 27, + /* PSRLDrr */ + }, + { /* 2185 */ + 186, + /* PSRLQri */ + }, + { /* 2186 */ + 26, + /* PSRLQrm */ + }, + { /* 2187 */ + 27, + /* PSRLQrr */ + }, + { /* 2188 */ + 186, + /* PSRLWri */ + }, + { /* 2189 */ + 26, + /* PSRLWrm */ + }, + { /* 2190 */ + 27, + /* PSRLWrr */ + }, + { /* 2191 */ + 26, + /* PSUBBrm */ + }, + { /* 2192 */ + 27, + /* PSUBBrr */ + }, + { /* 2193 */ + 26, + /* PSUBDrm */ + }, + { /* 2194 */ + 27, + /* PSUBDrr */ + }, + { /* 2195 */ + 26, + /* PSUBQrm */ + }, + { /* 2196 */ + 27, + /* PSUBQrr */ + }, + { /* 2197 */ + 26, + /* PSUBSBrm */ + }, + { /* 2198 */ + 27, + /* PSUBSBrr */ + }, + { /* 2199 */ + 26, + /* PSUBSWrm */ + }, + { /* 2200 */ + 27, + /* PSUBSWrr */ + }, + { /* 2201 */ + 26, + /* PSUBUSBrm */ + }, + { /* 2202 */ + 27, + /* PSUBUSBrr */ + }, + { /* 2203 */ + 26, + /* PSUBUSWrm */ + }, + { /* 2204 */ + 27, + /* PSUBUSWrr */ + }, + { /* 2205 */ + 26, + /* PSUBWrm */ + }, + { /* 2206 */ + 27, + /* PSUBWrr */ + }, + { /* 2207 */ + 130, + /* PSWAPDrm */ + }, + { /* 2208 */ + 134, + /* PSWAPDrr */ + }, + { /* 2209 */ + 30, + /* PTESTrm */ + }, + { /* 2210 */ + 31, + /* PTESTrr */ + }, + { /* 2211 */ + 28, + /* PTWRITE64m */ + }, + { /* 2212 */ + 72, + /* PTWRITE64r */ + }, + { /* 2213 */ + 28, + /* PTWRITEm */ + }, + { /* 2214 */ + 108, + /* PTWRITEr */ + }, + { /* 2215 */ + 26, + /* PUNPCKHBWrm */ + }, + { /* 2216 */ + 27, + /* PUNPCKHBWrr */ + }, + { /* 2217 */ + 26, + /* PUNPCKHDQrm */ + }, + { /* 2218 */ + 27, + /* PUNPCKHDQrr */ + }, + { /* 2219 */ + 26, + /* PUNPCKHQDQrm */ + }, + { /* 2220 */ + 27, + /* PUNPCKHQDQrr */ + }, + { /* 2221 */ + 26, + /* PUNPCKHWDrm */ + }, + { /* 2222 */ + 27, + /* PUNPCKHWDrr */ + }, + { /* 2223 */ + 26, + /* PUNPCKLBWrm */ + }, + { /* 2224 */ + 27, + /* PUNPCKLBWrr */ + }, + { /* 2225 */ + 26, + /* PUNPCKLDQrm */ + }, + { /* 2226 */ + 27, + /* PUNPCKLDQrr */ + }, + { /* 2227 */ + 26, + /* PUNPCKLQDQrm */ + }, + { /* 2228 */ + 27, + /* PUNPCKLQDQrr */ + }, + { /* 2229 */ + 26, + /* PUNPCKLWDrm */ + }, + { /* 2230 */ + 27, + /* PUNPCKLWDrr */ + }, + { /* 2231 */ + 1, + /* PUSH16i8 */ + }, + { /* 2232 */ + 184, + /* PUSH16r */ + }, + { /* 2233 */ + 28, + /* PUSH16rmm */ + }, + { /* 2234 */ + 70, + /* PUSH16rmr */ + }, + { /* 2235 */ + 1, + /* PUSH32i8 */ + }, + { /* 2236 */ + 184, + /* PUSH32r */ + }, + { /* 2237 */ + 28, + /* PUSH32rmm */ + }, + { /* 2238 */ + 70, + /* PUSH32rmr */ + }, + { /* 2239 */ + 11, + /* PUSH64i32 */ + }, + { /* 2240 */ + 1, + /* PUSH64i8 */ + }, + { /* 2241 */ + 185, + /* PUSH64r */ + }, + { /* 2242 */ + 28, + /* PUSH64rmm */ + }, + { /* 2243 */ + 72, + /* PUSH64rmr */ + }, + { /* 2244 */ + 0, + /* PUSHA16 */ + }, + { /* 2245 */ + 0, + /* PUSHA32 */ + }, + { /* 2246 */ + 0, + /* PUSHCS16 */ + }, + { /* 2247 */ + 0, + /* PUSHCS32 */ + }, + { /* 2248 */ + 0, + /* PUSHDS16 */ + }, + { /* 2249 */ + 0, + /* PUSHDS32 */ + }, + { /* 2250 */ + 0, + /* PUSHES16 */ + }, + { /* 2251 */ + 0, + /* PUSHES32 */ + }, + { /* 2252 */ + 0, + /* PUSHF16 */ + }, + { /* 2253 */ + 0, + /* PUSHF32 */ + }, + { /* 2254 */ + 0, + /* PUSHF64 */ + }, + { /* 2255 */ + 0, + /* PUSHFS16 */ + }, + { /* 2256 */ + 0, + /* PUSHFS32 */ + }, + { /* 2257 */ + 0, + /* PUSHFS64 */ + }, + { /* 2258 */ + 0, + /* PUSHGS16 */ + }, + { /* 2259 */ + 0, + /* PUSHGS32 */ + }, + { /* 2260 */ + 0, + /* PUSHGS64 */ + }, + { /* 2261 */ + 0, + /* PUSHSS16 */ + }, + { /* 2262 */ + 0, + /* PUSHSS32 */ + }, + { /* 2263 */ + 2, + /* PUSHi16 */ + }, + { /* 2264 */ + 2, + /* PUSHi32 */ + }, + { /* 2265 */ + 26, + /* PXORrm */ + }, + { /* 2266 */ + 27, + /* PXORrr */ + }, + { /* 2267 */ + 28, + /* RCL16m1 */ + }, + { /* 2268 */ + 28, + /* RCL16mCL */ + }, + { /* 2269 */ + 187, + /* RCL16mi */ + }, + { /* 2270 */ + 91, + /* RCL16r1 */ + }, + { /* 2271 */ + 91, + /* RCL16rCL */ + }, + { /* 2272 */ + 188, + /* RCL16ri */ + }, + { /* 2273 */ + 28, + /* RCL32m1 */ + }, + { /* 2274 */ + 28, + /* RCL32mCL */ + }, + { /* 2275 */ + 187, + /* RCL32mi */ + }, + { /* 2276 */ + 91, + /* RCL32r1 */ + }, + { /* 2277 */ + 91, + /* RCL32rCL */ + }, + { /* 2278 */ + 188, + /* RCL32ri */ + }, + { /* 2279 */ + 28, + /* RCL64m1 */ + }, + { /* 2280 */ + 28, + /* RCL64mCL */ + }, + { /* 2281 */ + 187, + /* RCL64mi */ + }, + { /* 2282 */ + 92, + /* RCL64r1 */ + }, + { /* 2283 */ + 92, + /* RCL64rCL */ + }, + { /* 2284 */ + 189, + /* RCL64ri */ + }, + { /* 2285 */ + 28, + /* RCL8m1 */ + }, + { /* 2286 */ + 28, + /* RCL8mCL */ + }, + { /* 2287 */ + 187, + /* RCL8mi */ + }, + { /* 2288 */ + 93, + /* RCL8r1 */ + }, + { /* 2289 */ + 93, + /* RCL8rCL */ + }, + { /* 2290 */ + 190, + /* RCL8ri */ + }, + { /* 2291 */ + 30, + /* RCPPSm */ + }, + { /* 2292 */ + 31, + /* RCPPSr */ + }, + { /* 2293 */ + 30, + /* RCPSSm */ + }, + { /* 2294 */ + 0, + /* */ + }, + { /* 2295 */ + 31, + /* RCPSSr */ + }, + { /* 2296 */ + 0, + /* */ + }, + { /* 2297 */ + 28, + /* RCR16m1 */ + }, + { /* 2298 */ + 28, + /* RCR16mCL */ + }, + { /* 2299 */ + 187, + /* RCR16mi */ + }, + { /* 2300 */ + 91, + /* RCR16r1 */ + }, + { /* 2301 */ + 91, + /* RCR16rCL */ + }, + { /* 2302 */ + 188, + /* RCR16ri */ + }, + { /* 2303 */ + 28, + /* RCR32m1 */ + }, + { /* 2304 */ + 28, + /* RCR32mCL */ + }, + { /* 2305 */ + 187, + /* RCR32mi */ + }, + { /* 2306 */ + 91, + /* RCR32r1 */ + }, + { /* 2307 */ + 91, + /* RCR32rCL */ + }, + { /* 2308 */ + 188, + /* RCR32ri */ + }, + { /* 2309 */ + 28, + /* RCR64m1 */ + }, + { /* 2310 */ + 28, + /* RCR64mCL */ + }, + { /* 2311 */ + 187, + /* RCR64mi */ + }, + { /* 2312 */ + 92, + /* RCR64r1 */ + }, + { /* 2313 */ + 92, + /* RCR64rCL */ + }, + { /* 2314 */ + 189, + /* RCR64ri */ + }, + { /* 2315 */ + 28, + /* RCR8m1 */ + }, + { /* 2316 */ + 28, + /* RCR8mCL */ + }, + { /* 2317 */ + 187, + /* RCR8mi */ + }, + { /* 2318 */ + 93, + /* RCR8r1 */ + }, + { /* 2319 */ + 93, + /* RCR8rCL */ + }, + { /* 2320 */ + 190, + /* RCR8ri */ + }, + { /* 2321 */ + 108, + /* RDFSBASE */ + }, + { /* 2322 */ + 72, + /* RDFSBASE64 */ + }, + { /* 2323 */ + 108, + /* RDGSBASE */ + }, + { /* 2324 */ + 72, + /* RDGSBASE64 */ + }, + { /* 2325 */ + 0, + /* RDMSR */ + }, + { /* 2326 */ + 108, + /* RDPID32 */ + }, + { /* 2327 */ + 72, + /* RDPID64 */ + }, + { /* 2328 */ + 0, + /* RDPKRUr */ + }, + { /* 2329 */ + 0, + /* RDPMC */ + }, + { /* 2330 */ + 70, + /* RDRAND16r */ + }, + { /* 2331 */ + 70, + /* RDRAND32r */ + }, + { /* 2332 */ + 72, + /* RDRAND64r */ + }, + { /* 2333 */ + 70, + /* RDSEED16r */ + }, + { /* 2334 */ + 70, + /* RDSEED32r */ + }, + { /* 2335 */ + 72, + /* RDSEED64r */ + }, + { /* 2336 */ + 191, + /* RDSSPD */ + }, + { /* 2337 */ + 92, + /* RDSSPQ */ + }, + { /* 2338 */ + 0, + /* RDTSC */ + }, + { /* 2339 */ + 0, + /* RDTSCP */ + }, + { /* 2340 */ + 0, + /* REPNE_PREFIX */ + }, + { /* 2341 */ + 0, + /* REP_PREFIX */ + }, + { /* 2342 */ + 125, + /* RETIL */ + }, + { /* 2343 */ + 125, + /* RETIQ */ + }, + { /* 2344 */ + 2, + /* RETIW */ + }, + { /* 2345 */ + 0, + /* RETL */ + }, + { /* 2346 */ + 0, + /* RETQ */ + }, + { /* 2347 */ + 0, + /* RETW */ + }, + { /* 2348 */ + 0, + /* REX64_PREFIX */ + }, + { /* 2349 */ + 28, + /* ROL16m1 */ + }, + { /* 2350 */ + 28, + /* ROL16mCL */ + }, + { /* 2351 */ + 187, + /* ROL16mi */ + }, + { /* 2352 */ + 91, + /* ROL16r1 */ + }, + { /* 2353 */ + 91, + /* ROL16rCL */ + }, + { /* 2354 */ + 188, + /* ROL16ri */ + }, + { /* 2355 */ + 28, + /* ROL32m1 */ + }, + { /* 2356 */ + 28, + /* ROL32mCL */ + }, + { /* 2357 */ + 187, + /* ROL32mi */ + }, + { /* 2358 */ + 91, + /* ROL32r1 */ + }, + { /* 2359 */ + 91, + /* ROL32rCL */ + }, + { /* 2360 */ + 188, + /* ROL32ri */ + }, + { /* 2361 */ + 28, + /* ROL64m1 */ + }, + { /* 2362 */ + 28, + /* ROL64mCL */ + }, + { /* 2363 */ + 187, + /* ROL64mi */ + }, + { /* 2364 */ + 92, + /* ROL64r1 */ + }, + { /* 2365 */ + 92, + /* ROL64rCL */ + }, + { /* 2366 */ + 189, + /* ROL64ri */ + }, + { /* 2367 */ + 28, + /* ROL8m1 */ + }, + { /* 2368 */ + 28, + /* ROL8mCL */ + }, + { /* 2369 */ + 187, + /* ROL8mi */ + }, + { /* 2370 */ + 93, + /* ROL8r1 */ + }, + { /* 2371 */ + 93, + /* ROL8rCL */ + }, + { /* 2372 */ + 190, + /* ROL8ri */ + }, + { /* 2373 */ + 28, + /* ROR16m1 */ + }, + { /* 2374 */ + 28, + /* ROR16mCL */ + }, + { /* 2375 */ + 187, + /* ROR16mi */ + }, + { /* 2376 */ + 91, + /* ROR16r1 */ + }, + { /* 2377 */ + 91, + /* ROR16rCL */ + }, + { /* 2378 */ + 188, + /* ROR16ri */ + }, + { /* 2379 */ + 28, + /* ROR32m1 */ + }, + { /* 2380 */ + 28, + /* ROR32mCL */ + }, + { /* 2381 */ + 187, + /* ROR32mi */ + }, + { /* 2382 */ + 91, + /* ROR32r1 */ + }, + { /* 2383 */ + 91, + /* ROR32rCL */ + }, + { /* 2384 */ + 188, + /* ROR32ri */ + }, + { /* 2385 */ + 28, + /* ROR64m1 */ + }, + { /* 2386 */ + 28, + /* ROR64mCL */ + }, + { /* 2387 */ + 187, + /* ROR64mi */ + }, + { /* 2388 */ + 92, + /* ROR64r1 */ + }, + { /* 2389 */ + 92, + /* ROR64rCL */ + }, + { /* 2390 */ + 189, + /* ROR64ri */ + }, + { /* 2391 */ + 28, + /* ROR8m1 */ + }, + { /* 2392 */ + 28, + /* ROR8mCL */ + }, + { /* 2393 */ + 187, + /* ROR8mi */ + }, + { /* 2394 */ + 93, + /* ROR8r1 */ + }, + { /* 2395 */ + 93, + /* ROR8rCL */ + }, + { /* 2396 */ + 190, + /* ROR8ri */ + }, + { /* 2397 */ + 192, + /* RORX32mi */ + }, + { /* 2398 */ + 193, + /* RORX32ri */ + }, + { /* 2399 */ + 194, + /* RORX64mi */ + }, + { /* 2400 */ + 195, + /* RORX64ri */ + }, + { /* 2401 */ + 32, + /* ROUNDPDm */ + }, + { /* 2402 */ + 33, + /* ROUNDPDr */ + }, + { /* 2403 */ + 32, + /* ROUNDPSm */ + }, + { /* 2404 */ + 33, + /* ROUNDPSr */ + }, + { /* 2405 */ + 32, + /* ROUNDSDm */ + }, + { /* 2406 */ + 0, + /* */ + }, + { /* 2407 */ + 33, + /* ROUNDSDr */ + }, + { /* 2408 */ + 0, + /* */ + }, + { /* 2409 */ + 32, + /* ROUNDSSm */ + }, + { /* 2410 */ + 0, + /* */ + }, + { /* 2411 */ + 33, + /* ROUNDSSr */ + }, + { /* 2412 */ + 0, + /* */ + }, + { /* 2413 */ + 0, + /* RSM */ + }, + { /* 2414 */ + 30, + /* RSQRTPSm */ + }, + { /* 2415 */ + 31, + /* RSQRTPSr */ + }, + { /* 2416 */ + 30, + /* RSQRTSSm */ + }, + { /* 2417 */ + 0, + /* */ + }, + { /* 2418 */ + 31, + /* RSQRTSSr */ + }, + { /* 2419 */ + 0, + /* */ + }, + { /* 2420 */ + 28, + /* RSTORSSP */ + }, + { /* 2421 */ + 0, + /* SAHF */ + }, + { /* 2422 */ + 28, + /* SAL16m1 */ + }, + { /* 2423 */ + 28, + /* SAL16mCL */ + }, + { /* 2424 */ + 4, + /* SAL16mi */ + }, + { /* 2425 */ + 91, + /* SAL16r1 */ + }, + { /* 2426 */ + 91, + /* SAL16rCL */ + }, + { /* 2427 */ + 7, + /* SAL16ri */ + }, + { /* 2428 */ + 28, + /* SAL32m1 */ + }, + { /* 2429 */ + 28, + /* SAL32mCL */ + }, + { /* 2430 */ + 4, + /* SAL32mi */ + }, + { /* 2431 */ + 91, + /* SAL32r1 */ + }, + { /* 2432 */ + 91, + /* SAL32rCL */ + }, + { /* 2433 */ + 7, + /* SAL32ri */ + }, + { /* 2434 */ + 28, + /* SAL64m1 */ + }, + { /* 2435 */ + 28, + /* SAL64mCL */ + }, + { /* 2436 */ + 4, + /* SAL64mi */ + }, + { /* 2437 */ + 92, + /* SAL64r1 */ + }, + { /* 2438 */ + 92, + /* SAL64rCL */ + }, + { /* 2439 */ + 15, + /* SAL64ri */ + }, + { /* 2440 */ + 28, + /* SAL8m1 */ + }, + { /* 2441 */ + 28, + /* SAL8mCL */ + }, + { /* 2442 */ + 4, + /* SAL8mi */ + }, + { /* 2443 */ + 93, + /* SAL8r1 */ + }, + { /* 2444 */ + 93, + /* SAL8rCL */ + }, + { /* 2445 */ + 20, + /* SAL8ri */ + }, + { /* 2446 */ + 0, + /* SALC */ + }, + { /* 2447 */ + 28, + /* SAR16m1 */ + }, + { /* 2448 */ + 28, + /* SAR16mCL */ + }, + { /* 2449 */ + 187, + /* SAR16mi */ + }, + { /* 2450 */ + 91, + /* SAR16r1 */ + }, + { /* 2451 */ + 91, + /* SAR16rCL */ + }, + { /* 2452 */ + 188, + /* SAR16ri */ + }, + { /* 2453 */ + 28, + /* SAR32m1 */ + }, + { /* 2454 */ + 28, + /* SAR32mCL */ + }, + { /* 2455 */ + 187, + /* SAR32mi */ + }, + { /* 2456 */ + 91, + /* SAR32r1 */ + }, + { /* 2457 */ + 91, + /* SAR32rCL */ + }, + { /* 2458 */ + 188, + /* SAR32ri */ + }, + { /* 2459 */ + 28, + /* SAR64m1 */ + }, + { /* 2460 */ + 28, + /* SAR64mCL */ + }, + { /* 2461 */ + 187, + /* SAR64mi */ + }, + { /* 2462 */ + 92, + /* SAR64r1 */ + }, + { /* 2463 */ + 92, + /* SAR64rCL */ + }, + { /* 2464 */ + 189, + /* SAR64ri */ + }, + { /* 2465 */ + 28, + /* SAR8m1 */ + }, + { /* 2466 */ + 28, + /* SAR8mCL */ + }, + { /* 2467 */ + 187, + /* SAR8mi */ + }, + { /* 2468 */ + 93, + /* SAR8r1 */ + }, + { /* 2469 */ + 93, + /* SAR8rCL */ + }, + { /* 2470 */ + 190, + /* SAR8ri */ + }, + { /* 2471 */ + 40, + /* SARX32rm */ + }, + { /* 2472 */ + 41, + /* SARX32rr */ + }, + { /* 2473 */ + 42, + /* SARX64rm */ + }, + { /* 2474 */ + 43, + /* SARX64rr */ + }, + { /* 2475 */ + 0, + /* SAVEPREVSSP */ + }, + { /* 2476 */ + 2, + /* SBB16i16 */ + }, + { /* 2477 */ + 3, + /* SBB16mi */ + }, + { /* 2478 */ + 4, + /* SBB16mi8 */ + }, + { /* 2479 */ + 5, + /* SBB16mr */ + }, + { /* 2480 */ + 6, + /* SBB16ri */ + }, + { /* 2481 */ + 7, + /* SBB16ri8 */ + }, + { /* 2482 */ + 8, + /* SBB16rm */ + }, + { /* 2483 */ + 9, + /* SBB16rr */ + }, + { /* 2484 */ + 10, + /* SBB16rr_REV */ + }, + { /* 2485 */ + 2, + /* SBB32i32 */ + }, + { /* 2486 */ + 3, + /* SBB32mi */ + }, + { /* 2487 */ + 4, + /* SBB32mi8 */ + }, + { /* 2488 */ + 5, + /* SBB32mr */ + }, + { /* 2489 */ + 6, + /* SBB32ri */ + }, + { /* 2490 */ + 7, + /* SBB32ri8 */ + }, + { /* 2491 */ + 8, + /* SBB32rm */ + }, + { /* 2492 */ + 9, + /* SBB32rr */ + }, + { /* 2493 */ + 10, + /* SBB32rr_REV */ + }, + { /* 2494 */ + 11, + /* SBB64i32 */ + }, + { /* 2495 */ + 12, + /* SBB64mi32 */ + }, + { /* 2496 */ + 4, + /* SBB64mi8 */ + }, + { /* 2497 */ + 13, + /* SBB64mr */ + }, + { /* 2498 */ + 14, + /* SBB64ri32 */ + }, + { /* 2499 */ + 15, + /* SBB64ri8 */ + }, + { /* 2500 */ + 16, + /* SBB64rm */ + }, + { /* 2501 */ + 17, + /* SBB64rr */ + }, + { /* 2502 */ + 18, + /* SBB64rr_REV */ + }, + { /* 2503 */ + 1, + /* SBB8i8 */ + }, + { /* 2504 */ + 4, + /* SBB8mi */ + }, + { /* 2505 */ + 4, + /* SBB8mi8 */ + }, + { /* 2506 */ + 19, + /* SBB8mr */ + }, + { /* 2507 */ + 20, + /* SBB8ri */ + }, + { /* 2508 */ + 20, + /* SBB8ri8 */ + }, + { /* 2509 */ + 21, + /* SBB8rm */ + }, + { /* 2510 */ + 22, + /* SBB8rr */ + }, + { /* 2511 */ + 23, + /* SBB8rr_REV */ + }, + { /* 2512 */ + 109, + /* SCASB */ + }, + { /* 2513 */ + 109, + /* SCASL */ + }, + { /* 2514 */ + 109, + /* SCASQ */ + }, + { /* 2515 */ + 109, + /* SCASW */ + }, + { /* 2516 */ + 28, + /* SETAEm */ + }, + { /* 2517 */ + 94, + /* SETAEr */ + }, + { /* 2518 */ + 28, + /* SETAm */ + }, + { /* 2519 */ + 94, + /* SETAr */ + }, + { /* 2520 */ + 28, + /* SETBEm */ + }, + { /* 2521 */ + 94, + /* SETBEr */ + }, + { /* 2522 */ + 28, + /* SETBm */ + }, + { /* 2523 */ + 94, + /* SETBr */ + }, + { /* 2524 */ + 28, + /* SETEm */ + }, + { /* 2525 */ + 94, + /* SETEr */ + }, + { /* 2526 */ + 28, + /* SETGEm */ + }, + { /* 2527 */ + 94, + /* SETGEr */ + }, + { /* 2528 */ + 28, + /* SETGm */ + }, + { /* 2529 */ + 94, + /* SETGr */ + }, + { /* 2530 */ + 28, + /* SETLEm */ + }, + { /* 2531 */ + 94, + /* SETLEr */ + }, + { /* 2532 */ + 28, + /* SETLm */ + }, + { /* 2533 */ + 94, + /* SETLr */ + }, + { /* 2534 */ + 28, + /* SETNEm */ + }, + { /* 2535 */ + 94, + /* SETNEr */ + }, + { /* 2536 */ + 28, + /* SETNOm */ + }, + { /* 2537 */ + 94, + /* SETNOr */ + }, + { /* 2538 */ + 28, + /* SETNPm */ + }, + { /* 2539 */ + 94, + /* SETNPr */ + }, + { /* 2540 */ + 28, + /* SETNSm */ + }, + { /* 2541 */ + 94, + /* SETNSr */ + }, + { /* 2542 */ + 28, + /* SETOm */ + }, + { /* 2543 */ + 94, + /* SETOr */ + }, + { /* 2544 */ + 28, + /* SETPm */ + }, + { /* 2545 */ + 94, + /* SETPr */ + }, + { /* 2546 */ + 0, + /* SETSSBSY */ + }, + { /* 2547 */ + 28, + /* SETSm */ + }, + { /* 2548 */ + 94, + /* SETSr */ + }, + { /* 2549 */ + 0, + /* SFENCE */ + }, + { /* 2550 */ + 28, + /* SGDT16m */ + }, + { /* 2551 */ + 28, + /* SGDT32m */ + }, + { /* 2552 */ + 28, + /* SGDT64m */ + }, + { /* 2553 */ + 26, + /* SHA1MSG1rm */ + }, + { /* 2554 */ + 27, + /* SHA1MSG1rr */ + }, + { /* 2555 */ + 26, + /* SHA1MSG2rm */ + }, + { /* 2556 */ + 27, + /* SHA1MSG2rr */ + }, + { /* 2557 */ + 26, + /* SHA1NEXTErm */ + }, + { /* 2558 */ + 27, + /* SHA1NEXTErr */ + }, + { /* 2559 */ + 52, + /* SHA1RNDS4rmi */ + }, + { /* 2560 */ + 53, + /* SHA1RNDS4rri */ + }, + { /* 2561 */ + 26, + /* SHA256MSG1rm */ + }, + { /* 2562 */ + 27, + /* SHA256MSG1rr */ + }, + { /* 2563 */ + 26, + /* SHA256MSG2rm */ + }, + { /* 2564 */ + 27, + /* SHA256MSG2rr */ + }, + { /* 2565 */ + 26, + /* SHA256RNDS2rm */ + }, + { /* 2566 */ + 27, + /* SHA256RNDS2rr */ + }, + { /* 2567 */ + 28, + /* SHL16m1 */ + }, + { /* 2568 */ + 28, + /* SHL16mCL */ + }, + { /* 2569 */ + 187, + /* SHL16mi */ + }, + { /* 2570 */ + 91, + /* SHL16r1 */ + }, + { /* 2571 */ + 91, + /* SHL16rCL */ + }, + { /* 2572 */ + 188, + /* SHL16ri */ + }, + { /* 2573 */ + 28, + /* SHL32m1 */ + }, + { /* 2574 */ + 28, + /* SHL32mCL */ + }, + { /* 2575 */ + 187, + /* SHL32mi */ + }, + { /* 2576 */ + 91, + /* SHL32r1 */ + }, + { /* 2577 */ + 91, + /* SHL32rCL */ + }, + { /* 2578 */ + 188, + /* SHL32ri */ + }, + { /* 2579 */ + 28, + /* SHL64m1 */ + }, + { /* 2580 */ + 28, + /* SHL64mCL */ + }, + { /* 2581 */ + 187, + /* SHL64mi */ + }, + { /* 2582 */ + 92, + /* SHL64r1 */ + }, + { /* 2583 */ + 92, + /* SHL64rCL */ + }, + { /* 2584 */ + 189, + /* SHL64ri */ + }, + { /* 2585 */ + 28, + /* SHL8m1 */ + }, + { /* 2586 */ + 28, + /* SHL8mCL */ + }, + { /* 2587 */ + 187, + /* SHL8mi */ + }, + { /* 2588 */ + 93, + /* SHL8r1 */ + }, + { /* 2589 */ + 93, + /* SHL8rCL */ + }, + { /* 2590 */ + 190, + /* SHL8ri */ + }, + { /* 2591 */ + 5, + /* SHLD16mrCL */ + }, + { /* 2592 */ + 196, + /* SHLD16mri8 */ + }, + { /* 2593 */ + 9, + /* SHLD16rrCL */ + }, + { /* 2594 */ + 197, + /* SHLD16rri8 */ + }, + { /* 2595 */ + 5, + /* SHLD32mrCL */ + }, + { /* 2596 */ + 196, + /* SHLD32mri8 */ + }, + { /* 2597 */ + 9, + /* SHLD32rrCL */ + }, + { /* 2598 */ + 197, + /* SHLD32rri8 */ + }, + { /* 2599 */ + 13, + /* SHLD64mrCL */ + }, + { /* 2600 */ + 198, + /* SHLD64mri8 */ + }, + { /* 2601 */ + 17, + /* SHLD64rrCL */ + }, + { /* 2602 */ + 199, + /* SHLD64rri8 */ + }, + { /* 2603 */ + 40, + /* SHLX32rm */ + }, + { /* 2604 */ + 41, + /* SHLX32rr */ + }, + { /* 2605 */ + 42, + /* SHLX64rm */ + }, + { /* 2606 */ + 43, + /* SHLX64rr */ + }, + { /* 2607 */ + 28, + /* SHR16m1 */ + }, + { /* 2608 */ + 28, + /* SHR16mCL */ + }, + { /* 2609 */ + 187, + /* SHR16mi */ + }, + { /* 2610 */ + 91, + /* SHR16r1 */ + }, + { /* 2611 */ + 91, + /* SHR16rCL */ + }, + { /* 2612 */ + 188, + /* SHR16ri */ + }, + { /* 2613 */ + 28, + /* SHR32m1 */ + }, + { /* 2614 */ + 28, + /* SHR32mCL */ + }, + { /* 2615 */ + 187, + /* SHR32mi */ + }, + { /* 2616 */ + 91, + /* SHR32r1 */ + }, + { /* 2617 */ + 91, + /* SHR32rCL */ + }, + { /* 2618 */ + 188, + /* SHR32ri */ + }, + { /* 2619 */ + 28, + /* SHR64m1 */ + }, + { /* 2620 */ + 28, + /* SHR64mCL */ + }, + { /* 2621 */ + 187, + /* SHR64mi */ + }, + { /* 2622 */ + 92, + /* SHR64r1 */ + }, + { /* 2623 */ + 92, + /* SHR64rCL */ + }, + { /* 2624 */ + 189, + /* SHR64ri */ + }, + { /* 2625 */ + 28, + /* SHR8m1 */ + }, + { /* 2626 */ + 28, + /* SHR8mCL */ + }, + { /* 2627 */ + 187, + /* SHR8mi */ + }, + { /* 2628 */ + 93, + /* SHR8r1 */ + }, + { /* 2629 */ + 93, + /* SHR8rCL */ + }, + { /* 2630 */ + 190, + /* SHR8ri */ + }, + { /* 2631 */ + 5, + /* SHRD16mrCL */ + }, + { /* 2632 */ + 196, + /* SHRD16mri8 */ + }, + { /* 2633 */ + 9, + /* SHRD16rrCL */ + }, + { /* 2634 */ + 197, + /* SHRD16rri8 */ + }, + { /* 2635 */ + 5, + /* SHRD32mrCL */ + }, + { /* 2636 */ + 196, + /* SHRD32mri8 */ + }, + { /* 2637 */ + 9, + /* SHRD32rrCL */ + }, + { /* 2638 */ + 197, + /* SHRD32rri8 */ + }, + { /* 2639 */ + 13, + /* SHRD64mrCL */ + }, + { /* 2640 */ + 198, + /* SHRD64mri8 */ + }, + { /* 2641 */ + 17, + /* SHRD64rrCL */ + }, + { /* 2642 */ + 199, + /* SHRD64rri8 */ + }, + { /* 2643 */ + 40, + /* SHRX32rm */ + }, + { /* 2644 */ + 41, + /* SHRX32rr */ + }, + { /* 2645 */ + 42, + /* SHRX64rm */ + }, + { /* 2646 */ + 43, + /* SHRX64rr */ + }, + { /* 2647 */ + 52, + /* SHUFPDrmi */ + }, + { /* 2648 */ + 53, + /* SHUFPDrri */ + }, + { /* 2649 */ + 52, + /* SHUFPSrmi */ + }, + { /* 2650 */ + 53, + /* SHUFPSrri */ + }, + { /* 2651 */ + 28, + /* SIDT16m */ + }, + { /* 2652 */ + 28, + /* SIDT32m */ + }, + { /* 2653 */ + 28, + /* SIDT64m */ + }, + { /* 2654 */ + 0, + /* SIN_F */ + }, + { /* 2655 */ + 0, + /* */ + }, + { /* 2656 */ + 0, + /* */ + }, + { /* 2657 */ + 0, + /* */ + }, + { /* 2658 */ + 0, + /* SKINIT */ + }, + { /* 2659 */ + 28, + /* SLDT16m */ + }, + { /* 2660 */ + 70, + /* SLDT16r */ + }, + { /* 2661 */ + 70, + /* SLDT32r */ + }, + { /* 2662 */ + 72, + /* SLDT64r */ + }, + { /* 2663 */ + 108, + /* SLWPCB */ + }, + { /* 2664 */ + 72, + /* SLWPCB64 */ + }, + { /* 2665 */ + 28, + /* SMSW16m */ + }, + { /* 2666 */ + 70, + /* SMSW16r */ + }, + { /* 2667 */ + 70, + /* SMSW32r */ + }, + { /* 2668 */ + 72, + /* SMSW64r */ + }, + { /* 2669 */ + 30, + /* SQRTPDm */ + }, + { /* 2670 */ + 31, + /* SQRTPDr */ + }, + { /* 2671 */ + 30, + /* SQRTPSm */ + }, + { /* 2672 */ + 31, + /* SQRTPSr */ + }, + { /* 2673 */ + 30, + /* SQRTSDm */ + }, + { /* 2674 */ + 0, + /* */ + }, + { /* 2675 */ + 31, + /* SQRTSDr */ + }, + { /* 2676 */ + 0, + /* */ + }, + { /* 2677 */ + 30, + /* SQRTSSm */ + }, + { /* 2678 */ + 0, + /* */ + }, + { /* 2679 */ + 31, + /* SQRTSSr */ + }, + { /* 2680 */ + 0, + /* */ + }, + { /* 2681 */ + 0, + /* SQRT_F */ + }, + { /* 2682 */ + 0, + /* */ + }, + { /* 2683 */ + 0, + /* */ + }, + { /* 2684 */ + 0, + /* */ + }, + { /* 2685 */ + 0, + /* STAC */ + }, + { /* 2686 */ + 0, + /* STC */ + }, + { /* 2687 */ + 0, + /* STD */ + }, + { /* 2688 */ + 0, + /* STGI */ + }, + { /* 2689 */ + 0, + /* STI */ + }, + { /* 2690 */ + 28, + /* STMXCSR */ + }, + { /* 2691 */ + 109, + /* STOSB */ + }, + { /* 2692 */ + 109, + /* STOSL */ + }, + { /* 2693 */ + 109, + /* STOSQ */ + }, + { /* 2694 */ + 109, + /* STOSW */ + }, + { /* 2695 */ + 70, + /* STR16r */ + }, + { /* 2696 */ + 70, + /* STR32r */ + }, + { /* 2697 */ + 72, + /* STR64r */ + }, + { /* 2698 */ + 28, + /* STRm */ + }, + { /* 2699 */ + 28, + /* ST_F32m */ + }, + { /* 2700 */ + 28, + /* ST_F64m */ + }, + { /* 2701 */ + 28, + /* ST_FP32m */ + }, + { /* 2702 */ + 28, + /* ST_FP64m */ + }, + { /* 2703 */ + 28, + /* ST_FP80m */ + }, + { /* 2704 */ + 29, + /* ST_FPrr */ + }, + { /* 2705 */ + 0, + /* */ + }, + { /* 2706 */ + 0, + /* */ + }, + { /* 2707 */ + 0, + /* */ + }, + { /* 2708 */ + 0, + /* */ + }, + { /* 2709 */ + 0, + /* */ + }, + { /* 2710 */ + 0, + /* */ + }, + { /* 2711 */ + 0, + /* */ + }, + { /* 2712 */ + 0, + /* */ + }, + { /* 2713 */ + 0, + /* */ + }, + { /* 2714 */ + 0, + /* */ + }, + { /* 2715 */ + 0, + /* */ + }, + { /* 2716 */ + 29, + /* ST_Frr */ + }, + { /* 2717 */ + 2, + /* SUB16i16 */ + }, + { /* 2718 */ + 3, + /* SUB16mi */ + }, + { /* 2719 */ + 4, + /* SUB16mi8 */ + }, + { /* 2720 */ + 5, + /* SUB16mr */ + }, + { /* 2721 */ + 6, + /* SUB16ri */ + }, + { /* 2722 */ + 7, + /* SUB16ri8 */ + }, + { /* 2723 */ + 8, + /* SUB16rm */ + }, + { /* 2724 */ + 9, + /* SUB16rr */ + }, + { /* 2725 */ + 10, + /* SUB16rr_REV */ + }, + { /* 2726 */ + 2, + /* SUB32i32 */ + }, + { /* 2727 */ + 3, + /* SUB32mi */ + }, + { /* 2728 */ + 4, + /* SUB32mi8 */ + }, + { /* 2729 */ + 5, + /* SUB32mr */ + }, + { /* 2730 */ + 6, + /* SUB32ri */ + }, + { /* 2731 */ + 7, + /* SUB32ri8 */ + }, + { /* 2732 */ + 8, + /* SUB32rm */ + }, + { /* 2733 */ + 9, + /* SUB32rr */ + }, + { /* 2734 */ + 10, + /* SUB32rr_REV */ + }, + { /* 2735 */ + 11, + /* SUB64i32 */ + }, + { /* 2736 */ + 12, + /* SUB64mi32 */ + }, + { /* 2737 */ + 4, + /* SUB64mi8 */ + }, + { /* 2738 */ + 13, + /* SUB64mr */ + }, + { /* 2739 */ + 14, + /* SUB64ri32 */ + }, + { /* 2740 */ + 15, + /* SUB64ri8 */ + }, + { /* 2741 */ + 16, + /* SUB64rm */ + }, + { /* 2742 */ + 17, + /* SUB64rr */ + }, + { /* 2743 */ + 18, + /* SUB64rr_REV */ + }, + { /* 2744 */ + 1, + /* SUB8i8 */ + }, + { /* 2745 */ + 4, + /* SUB8mi */ + }, + { /* 2746 */ + 4, + /* SUB8mi8 */ + }, + { /* 2747 */ + 19, + /* SUB8mr */ + }, + { /* 2748 */ + 20, + /* SUB8ri */ + }, + { /* 2749 */ + 20, + /* SUB8ri8 */ + }, + { /* 2750 */ + 21, + /* SUB8rm */ + }, + { /* 2751 */ + 22, + /* SUB8rr */ + }, + { /* 2752 */ + 23, + /* SUB8rr_REV */ + }, + { /* 2753 */ + 26, + /* SUBPDrm */ + }, + { /* 2754 */ + 27, + /* SUBPDrr */ + }, + { /* 2755 */ + 26, + /* SUBPSrm */ + }, + { /* 2756 */ + 27, + /* SUBPSrr */ + }, + { /* 2757 */ + 28, + /* SUBR_F32m */ + }, + { /* 2758 */ + 28, + /* SUBR_F64m */ + }, + { /* 2759 */ + 28, + /* SUBR_FI16m */ + }, + { /* 2760 */ + 28, + /* SUBR_FI32m */ + }, + { /* 2761 */ + 29, + /* SUBR_FPrST0 */ + }, + { /* 2762 */ + 29, + /* SUBR_FST0r */ + }, + { /* 2763 */ + 0, + /* */ + }, + { /* 2764 */ + 0, + /* */ + }, + { /* 2765 */ + 0, + /* */ + }, + { /* 2766 */ + 0, + /* */ + }, + { /* 2767 */ + 0, + /* */ + }, + { /* 2768 */ + 0, + /* */ + }, + { /* 2769 */ + 0, + /* */ + }, + { /* 2770 */ + 0, + /* */ + }, + { /* 2771 */ + 0, + /* */ + }, + { /* 2772 */ + 0, + /* */ + }, + { /* 2773 */ + 0, + /* */ + }, + { /* 2774 */ + 29, + /* SUBR_FrST0 */ + }, + { /* 2775 */ + 26, + /* SUBSDrm */ + }, + { /* 2776 */ + 0, + /* */ + }, + { /* 2777 */ + 27, + /* SUBSDrr */ + }, + { /* 2778 */ + 0, + /* */ + }, + { /* 2779 */ + 26, + /* SUBSSrm */ + }, + { /* 2780 */ + 0, + /* */ + }, + { /* 2781 */ + 27, + /* SUBSSrr */ + }, + { /* 2782 */ + 0, + /* */ + }, + { /* 2783 */ + 28, + /* SUB_F32m */ + }, + { /* 2784 */ + 28, + /* SUB_F64m */ + }, + { /* 2785 */ + 28, + /* SUB_FI16m */ + }, + { /* 2786 */ + 28, + /* SUB_FI32m */ + }, + { /* 2787 */ + 29, + /* SUB_FPrST0 */ + }, + { /* 2788 */ + 29, + /* SUB_FST0r */ + }, + { /* 2789 */ + 0, + /* */ + }, + { /* 2790 */ + 0, + /* */ + }, + { /* 2791 */ + 0, + /* */ + }, + { /* 2792 */ + 0, + /* */ + }, + { /* 2793 */ + 0, + /* */ + }, + { /* 2794 */ + 0, + /* */ + }, + { /* 2795 */ + 0, + /* */ + }, + { /* 2796 */ + 0, + /* */ + }, + { /* 2797 */ + 0, + /* */ + }, + { /* 2798 */ + 0, + /* */ + }, + { /* 2799 */ + 0, + /* */ + }, + { /* 2800 */ + 0, + /* */ + }, + { /* 2801 */ + 0, + /* */ + }, + { /* 2802 */ + 0, + /* */ + }, + { /* 2803 */ + 29, + /* SUB_FrST0 */ + }, + { /* 2804 */ + 0, + /* SWAPGS */ + }, + { /* 2805 */ + 0, + /* SYSCALL */ + }, + { /* 2806 */ + 0, + /* SYSENTER */ + }, + { /* 2807 */ + 0, + /* SYSEXIT */ + }, + { /* 2808 */ + 0, + /* SYSEXIT64 */ + }, + { /* 2809 */ + 0, + /* SYSRET */ + }, + { /* 2810 */ + 0, + /* SYSRET64 */ + }, + { /* 2811 */ + 48, + /* T1MSKC32rm */ + }, + { /* 2812 */ + 49, + /* T1MSKC32rr */ + }, + { /* 2813 */ + 50, + /* T1MSKC64rm */ + }, + { /* 2814 */ + 51, + /* T1MSKC64rr */ + }, + { /* 2815 */ + 2, + /* TEST16i16 */ + }, + { /* 2816 */ + 3, + /* TEST16mi */ + }, + { /* 2817 */ + 3, + /* TEST16mi_alt */ + }, + { /* 2818 */ + 5, + /* TEST16mr */ + }, + { /* 2819 */ + 74, + /* TEST16ri */ + }, + { /* 2820 */ + 74, + /* TEST16ri_alt */ + }, + { /* 2821 */ + 67, + /* TEST16rr */ + }, + { /* 2822 */ + 2, + /* TEST32i32 */ + }, + { /* 2823 */ + 3, + /* TEST32mi */ + }, + { /* 2824 */ + 3, + /* TEST32mi_alt */ + }, + { /* 2825 */ + 5, + /* TEST32mr */ + }, + { /* 2826 */ + 74, + /* TEST32ri */ + }, + { /* 2827 */ + 74, + /* TEST32ri_alt */ + }, + { /* 2828 */ + 67, + /* TEST32rr */ + }, + { /* 2829 */ + 11, + /* TEST64i32 */ + }, + { /* 2830 */ + 12, + /* TEST64mi32 */ + }, + { /* 2831 */ + 12, + /* TEST64mi32_alt */ + }, + { /* 2832 */ + 13, + /* TEST64mr */ + }, + { /* 2833 */ + 75, + /* TEST64ri32 */ + }, + { /* 2834 */ + 75, + /* TEST64ri32_alt */ + }, + { /* 2835 */ + 69, + /* TEST64rr */ + }, + { /* 2836 */ + 1, + /* TEST8i8 */ + }, + { /* 2837 */ + 4, + /* TEST8mi */ + }, + { /* 2838 */ + 4, + /* TEST8mi_alt */ + }, + { /* 2839 */ + 19, + /* TEST8mr */ + }, + { /* 2840 */ + 76, + /* TEST8ri */ + }, + { /* 2841 */ + 76, + /* TEST8ri_alt */ + }, + { /* 2842 */ + 78, + /* TEST8rr */ + }, + { /* 2843 */ + 108, + /* TPAUSE */ + }, + { /* 2844 */ + 0, + /* TST_F */ + }, + { /* 2845 */ + 0, + /* */ + }, + { /* 2846 */ + 0, + /* */ + }, + { /* 2847 */ + 0, + /* */ + }, + { /* 2848 */ + 60, + /* TZCNT16rm */ + }, + { /* 2849 */ + 61, + /* TZCNT16rr */ + }, + { /* 2850 */ + 60, + /* TZCNT32rm */ + }, + { /* 2851 */ + 61, + /* TZCNT32rr */ + }, + { /* 2852 */ + 62, + /* TZCNT64rm */ + }, + { /* 2853 */ + 63, + /* TZCNT64rr */ + }, + { /* 2854 */ + 48, + /* TZMSK32rm */ + }, + { /* 2855 */ + 49, + /* TZMSK32rr */ + }, + { /* 2856 */ + 50, + /* TZMSK64rm */ + }, + { /* 2857 */ + 51, + /* TZMSK64rr */ + }, + { /* 2858 */ + 30, + /* UCOMISDrm */ + }, + { /* 2859 */ + 0, + /* */ + }, + { /* 2860 */ + 31, + /* UCOMISDrr */ + }, + { /* 2861 */ + 0, + /* */ + }, + { /* 2862 */ + 30, + /* UCOMISSrm */ + }, + { /* 2863 */ + 0, + /* */ + }, + { /* 2864 */ + 31, + /* UCOMISSrr */ + }, + { /* 2865 */ + 0, + /* */ + }, + { /* 2866 */ + 29, + /* UCOM_FIPr */ + }, + { /* 2867 */ + 29, + /* UCOM_FIr */ + }, + { /* 2868 */ + 0, + /* UCOM_FPPr */ + }, + { /* 2869 */ + 29, + /* UCOM_FPr */ + }, + { /* 2870 */ + 0, + /* */ + }, + { /* 2871 */ + 0, + /* */ + }, + { /* 2872 */ + 0, + /* */ + }, + { /* 2873 */ + 0, + /* */ + }, + { /* 2874 */ + 0, + /* */ + }, + { /* 2875 */ + 0, + /* */ + }, + { /* 2876 */ + 29, + /* UCOM_Fr */ + }, + { /* 2877 */ + 0, + /* UD0 */ + }, + { /* 2878 */ + 0, + /* UD1 */ + }, + { /* 2879 */ + 0, + /* UD2 */ + }, + { /* 2880 */ + 123, + /* UMONITOR16 */ + }, + { /* 2881 */ + 108, + /* UMONITOR32 */ + }, + { /* 2882 */ + 72, + /* UMONITOR64 */ + }, + { /* 2883 */ + 108, + /* UMWAIT */ + }, + { /* 2884 */ + 26, + /* UNPCKHPDrm */ + }, + { /* 2885 */ + 27, + /* UNPCKHPDrr */ + }, + { /* 2886 */ + 26, + /* UNPCKHPSrm */ + }, + { /* 2887 */ + 27, + /* UNPCKHPSrr */ + }, + { /* 2888 */ + 26, + /* UNPCKLPDrm */ + }, + { /* 2889 */ + 27, + /* UNPCKLPDrr */ + }, + { /* 2890 */ + 26, + /* UNPCKLPSrm */ + }, + { /* 2891 */ + 27, + /* UNPCKLPSrr */ + }, + { /* 2892 */ + 200, + /* V4FMADDPSrm */ + }, + { /* 2893 */ + 201, + /* V4FMADDPSrmk */ + }, + { /* 2894 */ + 201, + /* V4FMADDPSrmkz */ + }, + { /* 2895 */ + 202, + /* V4FMADDSSrm */ + }, + { /* 2896 */ + 203, + /* V4FMADDSSrmk */ + }, + { /* 2897 */ + 203, + /* V4FMADDSSrmkz */ + }, + { /* 2898 */ + 200, + /* V4FNMADDPSrm */ + }, + { /* 2899 */ + 201, + /* V4FNMADDPSrmk */ + }, + { /* 2900 */ + 201, + /* V4FNMADDPSrmkz */ + }, + { /* 2901 */ + 202, + /* V4FNMADDSSrm */ + }, + { /* 2902 */ + 203, + /* V4FNMADDSSrmk */ + }, + { /* 2903 */ + 203, + /* V4FNMADDSSrmkz */ + }, + { /* 2904 */ + 204, + /* VADDPDYrm */ + }, + { /* 2905 */ + 205, + /* VADDPDYrr */ + }, + { /* 2906 */ + 206, + /* VADDPDZ128rm */ + }, + { /* 2907 */ + 207, + /* VADDPDZ128rmb */ + }, + { /* 2908 */ + 208, + /* VADDPDZ128rmbk */ + }, + { /* 2909 */ + 209, + /* VADDPDZ128rmbkz */ + }, + { /* 2910 */ + 203, + /* VADDPDZ128rmk */ + }, + { /* 2911 */ + 210, + /* VADDPDZ128rmkz */ + }, + { /* 2912 */ + 211, + /* VADDPDZ128rr */ + }, + { /* 2913 */ + 212, + /* VADDPDZ128rrk */ + }, + { /* 2914 */ + 213, + /* VADDPDZ128rrkz */ + }, + { /* 2915 */ + 214, + /* VADDPDZ256rm */ + }, + { /* 2916 */ + 215, + /* VADDPDZ256rmb */ + }, + { /* 2917 */ + 216, + /* VADDPDZ256rmbk */ + }, + { /* 2918 */ + 217, + /* VADDPDZ256rmbkz */ + }, + { /* 2919 */ + 218, + /* VADDPDZ256rmk */ + }, + { /* 2920 */ + 219, + /* VADDPDZ256rmkz */ + }, + { /* 2921 */ + 220, + /* VADDPDZ256rr */ + }, + { /* 2922 */ + 221, + /* VADDPDZ256rrk */ + }, + { /* 2923 */ + 222, + /* VADDPDZ256rrkz */ + }, + { /* 2924 */ + 223, + /* VADDPDZrm */ + }, + { /* 2925 */ + 224, + /* VADDPDZrmb */ + }, + { /* 2926 */ + 225, + /* VADDPDZrmbk */ + }, + { /* 2927 */ + 226, + /* VADDPDZrmbkz */ + }, + { /* 2928 */ + 227, + /* VADDPDZrmk */ + }, + { /* 2929 */ + 228, + /* VADDPDZrmkz */ + }, + { /* 2930 */ + 229, + /* VADDPDZrr */ + }, + { /* 2931 */ + 230, + /* VADDPDZrrb */ + }, + { /* 2932 */ + 231, + /* VADDPDZrrbk */ + }, + { /* 2933 */ + 232, + /* VADDPDZrrbkz */ + }, + { /* 2934 */ + 233, + /* VADDPDZrrk */ + }, + { /* 2935 */ + 234, + /* VADDPDZrrkz */ + }, + { /* 2936 */ + 235, + /* VADDPDrm */ + }, + { /* 2937 */ + 236, + /* VADDPDrr */ + }, + { /* 2938 */ + 204, + /* VADDPSYrm */ + }, + { /* 2939 */ + 205, + /* VADDPSYrr */ + }, + { /* 2940 */ + 206, + /* VADDPSZ128rm */ + }, + { /* 2941 */ + 237, + /* VADDPSZ128rmb */ + }, + { /* 2942 */ + 238, + /* VADDPSZ128rmbk */ + }, + { /* 2943 */ + 239, + /* VADDPSZ128rmbkz */ + }, + { /* 2944 */ + 203, + /* VADDPSZ128rmk */ + }, + { /* 2945 */ + 210, + /* VADDPSZ128rmkz */ + }, + { /* 2946 */ + 211, + /* VADDPSZ128rr */ + }, + { /* 2947 */ + 212, + /* VADDPSZ128rrk */ + }, + { /* 2948 */ + 213, + /* VADDPSZ128rrkz */ + }, + { /* 2949 */ + 214, + /* VADDPSZ256rm */ + }, + { /* 2950 */ + 240, + /* VADDPSZ256rmb */ + }, + { /* 2951 */ + 241, + /* VADDPSZ256rmbk */ + }, + { /* 2952 */ + 242, + /* VADDPSZ256rmbkz */ + }, + { /* 2953 */ + 218, + /* VADDPSZ256rmk */ + }, + { /* 2954 */ + 219, + /* VADDPSZ256rmkz */ + }, + { /* 2955 */ + 220, + /* VADDPSZ256rr */ + }, + { /* 2956 */ + 221, + /* VADDPSZ256rrk */ + }, + { /* 2957 */ + 222, + /* VADDPSZ256rrkz */ + }, + { /* 2958 */ + 223, + /* VADDPSZrm */ + }, + { /* 2959 */ + 243, + /* VADDPSZrmb */ + }, + { /* 2960 */ + 244, + /* VADDPSZrmbk */ + }, + { /* 2961 */ + 245, + /* VADDPSZrmbkz */ + }, + { /* 2962 */ + 227, + /* VADDPSZrmk */ + }, + { /* 2963 */ + 228, + /* VADDPSZrmkz */ + }, + { /* 2964 */ + 229, + /* VADDPSZrr */ + }, + { /* 2965 */ + 246, + /* VADDPSZrrb */ + }, + { /* 2966 */ + 247, + /* VADDPSZrrbk */ + }, + { /* 2967 */ + 248, + /* VADDPSZrrbkz */ + }, + { /* 2968 */ + 233, + /* VADDPSZrrk */ + }, + { /* 2969 */ + 234, + /* VADDPSZrrkz */ + }, + { /* 2970 */ + 235, + /* VADDPSrm */ + }, + { /* 2971 */ + 236, + /* VADDPSrr */ + }, + { /* 2972 */ + 0, + /* */ + }, + { /* 2973 */ + 207, + /* VADDSDZrm_Int */ + }, + { /* 2974 */ + 208, + /* VADDSDZrm_Intk */ + }, + { /* 2975 */ + 209, + /* VADDSDZrm_Intkz */ + }, + { /* 2976 */ + 0, + /* */ + }, + { /* 2977 */ + 249, + /* VADDSDZrr_Int */ + }, + { /* 2978 */ + 250, + /* VADDSDZrr_Intk */ + }, + { /* 2979 */ + 251, + /* VADDSDZrr_Intkz */ + }, + { /* 2980 */ + 252, + /* VADDSDZrrb_Int */ + }, + { /* 2981 */ + 253, + /* VADDSDZrrb_Intk */ + }, + { /* 2982 */ + 254, + /* VADDSDZrrb_Intkz */ + }, + { /* 2983 */ + 235, + /* VADDSDrm */ + }, + { /* 2984 */ + 0, + /* */ + }, + { /* 2985 */ + 236, + /* VADDSDrr */ + }, + { /* 2986 */ + 0, + /* */ + }, + { /* 2987 */ + 0, + /* */ + }, + { /* 2988 */ + 237, + /* VADDSSZrm_Int */ + }, + { /* 2989 */ + 238, + /* VADDSSZrm_Intk */ + }, + { /* 2990 */ + 239, + /* VADDSSZrm_Intkz */ + }, + { /* 2991 */ + 0, + /* */ + }, + { /* 2992 */ + 255, + /* VADDSSZrr_Int */ + }, + { /* 2993 */ + 256, + /* VADDSSZrr_Intk */ + }, + { /* 2994 */ + 257, + /* VADDSSZrr_Intkz */ + }, + { /* 2995 */ + 258, + /* VADDSSZrrb_Int */ + }, + { /* 2996 */ + 259, + /* VADDSSZrrb_Intk */ + }, + { /* 2997 */ + 260, + /* VADDSSZrrb_Intkz */ + }, + { /* 2998 */ + 235, + /* VADDSSrm */ + }, + { /* 2999 */ + 0, + /* */ + }, + { /* 3000 */ + 236, + /* VADDSSrr */ + }, + { /* 3001 */ + 0, + /* */ + }, + { /* 3002 */ + 204, + /* VADDSUBPDYrm */ + }, + { /* 3003 */ + 205, + /* VADDSUBPDYrr */ + }, + { /* 3004 */ + 235, + /* VADDSUBPDrm */ + }, + { /* 3005 */ + 236, + /* VADDSUBPDrr */ + }, + { /* 3006 */ + 204, + /* VADDSUBPSYrm */ + }, + { /* 3007 */ + 205, + /* VADDSUBPSYrr */ + }, + { /* 3008 */ + 235, + /* VADDSUBPSrm */ + }, + { /* 3009 */ + 236, + /* VADDSUBPSrr */ + }, + { /* 3010 */ + 204, + /* VAESDECLASTYrm */ + }, + { /* 3011 */ + 205, + /* VAESDECLASTYrr */ + }, + { /* 3012 */ + 206, + /* VAESDECLASTZ128rm */ + }, + { /* 3013 */ + 211, + /* VAESDECLASTZ128rr */ + }, + { /* 3014 */ + 214, + /* VAESDECLASTZ256rm */ + }, + { /* 3015 */ + 220, + /* VAESDECLASTZ256rr */ + }, + { /* 3016 */ + 223, + /* VAESDECLASTZrm */ + }, + { /* 3017 */ + 229, + /* VAESDECLASTZrr */ + }, + { /* 3018 */ + 235, + /* VAESDECLASTrm */ + }, + { /* 3019 */ + 236, + /* VAESDECLASTrr */ + }, + { /* 3020 */ + 204, + /* VAESDECYrm */ + }, + { /* 3021 */ + 205, + /* VAESDECYrr */ + }, + { /* 3022 */ + 206, + /* VAESDECZ128rm */ + }, + { /* 3023 */ + 211, + /* VAESDECZ128rr */ + }, + { /* 3024 */ + 214, + /* VAESDECZ256rm */ + }, + { /* 3025 */ + 220, + /* VAESDECZ256rr */ + }, + { /* 3026 */ + 223, + /* VAESDECZrm */ + }, + { /* 3027 */ + 229, + /* VAESDECZrr */ + }, + { /* 3028 */ + 235, + /* VAESDECrm */ + }, + { /* 3029 */ + 236, + /* VAESDECrr */ + }, + { /* 3030 */ + 204, + /* VAESENCLASTYrm */ + }, + { /* 3031 */ + 205, + /* VAESENCLASTYrr */ + }, + { /* 3032 */ + 206, + /* VAESENCLASTZ128rm */ + }, + { /* 3033 */ + 211, + /* VAESENCLASTZ128rr */ + }, + { /* 3034 */ + 214, + /* VAESENCLASTZ256rm */ + }, + { /* 3035 */ + 220, + /* VAESENCLASTZ256rr */ + }, + { /* 3036 */ + 223, + /* VAESENCLASTZrm */ + }, + { /* 3037 */ + 229, + /* VAESENCLASTZrr */ + }, + { /* 3038 */ + 235, + /* VAESENCLASTrm */ + }, + { /* 3039 */ + 236, + /* VAESENCLASTrr */ + }, + { /* 3040 */ + 204, + /* VAESENCYrm */ + }, + { /* 3041 */ + 205, + /* VAESENCYrr */ + }, + { /* 3042 */ + 206, + /* VAESENCZ128rm */ + }, + { /* 3043 */ + 211, + /* VAESENCZ128rr */ + }, + { /* 3044 */ + 214, + /* VAESENCZ256rm */ + }, + { /* 3045 */ + 220, + /* VAESENCZ256rr */ + }, + { /* 3046 */ + 223, + /* VAESENCZrm */ + }, + { /* 3047 */ + 229, + /* VAESENCZrr */ + }, + { /* 3048 */ + 235, + /* VAESENCrm */ + }, + { /* 3049 */ + 236, + /* VAESENCrr */ + }, + { /* 3050 */ + 30, + /* VAESIMCrm */ + }, + { /* 3051 */ + 31, + /* VAESIMCrr */ + }, + { /* 3052 */ + 32, + /* VAESKEYGENASSIST128rm */ + }, + { /* 3053 */ + 33, + /* VAESKEYGENASSIST128rr */ + }, + { /* 3054 */ + 261, + /* VALIGNDZ128rmbi */ + }, + { /* 3055 */ + 262, + /* VALIGNDZ128rmbik */ + }, + { /* 3056 */ + 263, + /* VALIGNDZ128rmbikz */ + }, + { /* 3057 */ + 264, + /* VALIGNDZ128rmi */ + }, + { /* 3058 */ + 265, + /* VALIGNDZ128rmik */ + }, + { /* 3059 */ + 266, + /* VALIGNDZ128rmikz */ + }, + { /* 3060 */ + 267, + /* VALIGNDZ128rri */ + }, + { /* 3061 */ + 268, + /* VALIGNDZ128rrik */ + }, + { /* 3062 */ + 269, + /* VALIGNDZ128rrikz */ + }, + { /* 3063 */ + 270, + /* VALIGNDZ256rmbi */ + }, + { /* 3064 */ + 271, + /* VALIGNDZ256rmbik */ + }, + { /* 3065 */ + 272, + /* VALIGNDZ256rmbikz */ + }, + { /* 3066 */ + 273, + /* VALIGNDZ256rmi */ + }, + { /* 3067 */ + 274, + /* VALIGNDZ256rmik */ + }, + { /* 3068 */ + 275, + /* VALIGNDZ256rmikz */ + }, + { /* 3069 */ + 276, + /* VALIGNDZ256rri */ + }, + { /* 3070 */ + 277, + /* VALIGNDZ256rrik */ + }, + { /* 3071 */ + 278, + /* VALIGNDZ256rrikz */ + }, + { /* 3072 */ + 279, + /* VALIGNDZrmbi */ + }, + { /* 3073 */ + 280, + /* VALIGNDZrmbik */ + }, + { /* 3074 */ + 281, + /* VALIGNDZrmbikz */ + }, + { /* 3075 */ + 282, + /* VALIGNDZrmi */ + }, + { /* 3076 */ + 283, + /* VALIGNDZrmik */ + }, + { /* 3077 */ + 284, + /* VALIGNDZrmikz */ + }, + { /* 3078 */ + 285, + /* VALIGNDZrri */ + }, + { /* 3079 */ + 286, + /* VALIGNDZrrik */ + }, + { /* 3080 */ + 287, + /* VALIGNDZrrikz */ + }, + { /* 3081 */ + 288, + /* VALIGNQZ128rmbi */ + }, + { /* 3082 */ + 289, + /* VALIGNQZ128rmbik */ + }, + { /* 3083 */ + 290, + /* VALIGNQZ128rmbikz */ + }, + { /* 3084 */ + 264, + /* VALIGNQZ128rmi */ + }, + { /* 3085 */ + 265, + /* VALIGNQZ128rmik */ + }, + { /* 3086 */ + 266, + /* VALIGNQZ128rmikz */ + }, + { /* 3087 */ + 267, + /* VALIGNQZ128rri */ + }, + { /* 3088 */ + 268, + /* VALIGNQZ128rrik */ + }, + { /* 3089 */ + 269, + /* VALIGNQZ128rrikz */ + }, + { /* 3090 */ + 291, + /* VALIGNQZ256rmbi */ + }, + { /* 3091 */ + 292, + /* VALIGNQZ256rmbik */ + }, + { /* 3092 */ + 293, + /* VALIGNQZ256rmbikz */ + }, + { /* 3093 */ + 273, + /* VALIGNQZ256rmi */ + }, + { /* 3094 */ + 274, + /* VALIGNQZ256rmik */ + }, + { /* 3095 */ + 275, + /* VALIGNQZ256rmikz */ + }, + { /* 3096 */ + 276, + /* VALIGNQZ256rri */ + }, + { /* 3097 */ + 277, + /* VALIGNQZ256rrik */ + }, + { /* 3098 */ + 278, + /* VALIGNQZ256rrikz */ + }, + { /* 3099 */ + 294, + /* VALIGNQZrmbi */ + }, + { /* 3100 */ + 295, + /* VALIGNQZrmbik */ + }, + { /* 3101 */ + 296, + /* VALIGNQZrmbikz */ + }, + { /* 3102 */ + 282, + /* VALIGNQZrmi */ + }, + { /* 3103 */ + 283, + /* VALIGNQZrmik */ + }, + { /* 3104 */ + 284, + /* VALIGNQZrmikz */ + }, + { /* 3105 */ + 285, + /* VALIGNQZrri */ + }, + { /* 3106 */ + 286, + /* VALIGNQZrrik */ + }, + { /* 3107 */ + 287, + /* VALIGNQZrrikz */ + }, + { /* 3108 */ + 204, + /* VANDNPDYrm */ + }, + { /* 3109 */ + 205, + /* VANDNPDYrr */ + }, + { /* 3110 */ + 206, + /* VANDNPDZ128rm */ + }, + { /* 3111 */ + 207, + /* VANDNPDZ128rmb */ + }, + { /* 3112 */ + 208, + /* VANDNPDZ128rmbk */ + }, + { /* 3113 */ + 209, + /* VANDNPDZ128rmbkz */ + }, + { /* 3114 */ + 203, + /* VANDNPDZ128rmk */ + }, + { /* 3115 */ + 210, + /* VANDNPDZ128rmkz */ + }, + { /* 3116 */ + 211, + /* VANDNPDZ128rr */ + }, + { /* 3117 */ + 212, + /* VANDNPDZ128rrk */ + }, + { /* 3118 */ + 213, + /* VANDNPDZ128rrkz */ + }, + { /* 3119 */ + 214, + /* VANDNPDZ256rm */ + }, + { /* 3120 */ + 215, + /* VANDNPDZ256rmb */ + }, + { /* 3121 */ + 216, + /* VANDNPDZ256rmbk */ + }, + { /* 3122 */ + 217, + /* VANDNPDZ256rmbkz */ + }, + { /* 3123 */ + 218, + /* VANDNPDZ256rmk */ + }, + { /* 3124 */ + 219, + /* VANDNPDZ256rmkz */ + }, + { /* 3125 */ + 220, + /* VANDNPDZ256rr */ + }, + { /* 3126 */ + 221, + /* VANDNPDZ256rrk */ + }, + { /* 3127 */ + 222, + /* VANDNPDZ256rrkz */ + }, + { /* 3128 */ + 223, + /* VANDNPDZrm */ + }, + { /* 3129 */ + 224, + /* VANDNPDZrmb */ + }, + { /* 3130 */ + 225, + /* VANDNPDZrmbk */ + }, + { /* 3131 */ + 226, + /* VANDNPDZrmbkz */ + }, + { /* 3132 */ + 227, + /* VANDNPDZrmk */ + }, + { /* 3133 */ + 228, + /* VANDNPDZrmkz */ + }, + { /* 3134 */ + 229, + /* VANDNPDZrr */ + }, + { /* 3135 */ + 233, + /* VANDNPDZrrk */ + }, + { /* 3136 */ + 234, + /* VANDNPDZrrkz */ + }, + { /* 3137 */ + 235, + /* VANDNPDrm */ + }, + { /* 3138 */ + 236, + /* VANDNPDrr */ + }, + { /* 3139 */ + 204, + /* VANDNPSYrm */ + }, + { /* 3140 */ + 205, + /* VANDNPSYrr */ + }, + { /* 3141 */ + 206, + /* VANDNPSZ128rm */ + }, + { /* 3142 */ + 237, + /* VANDNPSZ128rmb */ + }, + { /* 3143 */ + 238, + /* VANDNPSZ128rmbk */ + }, + { /* 3144 */ + 239, + /* VANDNPSZ128rmbkz */ + }, + { /* 3145 */ + 203, + /* VANDNPSZ128rmk */ + }, + { /* 3146 */ + 210, + /* VANDNPSZ128rmkz */ + }, + { /* 3147 */ + 211, + /* VANDNPSZ128rr */ + }, + { /* 3148 */ + 212, + /* VANDNPSZ128rrk */ + }, + { /* 3149 */ + 213, + /* VANDNPSZ128rrkz */ + }, + { /* 3150 */ + 214, + /* VANDNPSZ256rm */ + }, + { /* 3151 */ + 240, + /* VANDNPSZ256rmb */ + }, + { /* 3152 */ + 241, + /* VANDNPSZ256rmbk */ + }, + { /* 3153 */ + 242, + /* VANDNPSZ256rmbkz */ + }, + { /* 3154 */ + 218, + /* VANDNPSZ256rmk */ + }, + { /* 3155 */ + 219, + /* VANDNPSZ256rmkz */ + }, + { /* 3156 */ + 220, + /* VANDNPSZ256rr */ + }, + { /* 3157 */ + 221, + /* VANDNPSZ256rrk */ + }, + { /* 3158 */ + 222, + /* VANDNPSZ256rrkz */ + }, + { /* 3159 */ + 223, + /* VANDNPSZrm */ + }, + { /* 3160 */ + 243, + /* VANDNPSZrmb */ + }, + { /* 3161 */ + 244, + /* VANDNPSZrmbk */ + }, + { /* 3162 */ + 245, + /* VANDNPSZrmbkz */ + }, + { /* 3163 */ + 227, + /* VANDNPSZrmk */ + }, + { /* 3164 */ + 228, + /* VANDNPSZrmkz */ + }, + { /* 3165 */ + 229, + /* VANDNPSZrr */ + }, + { /* 3166 */ + 233, + /* VANDNPSZrrk */ + }, + { /* 3167 */ + 234, + /* VANDNPSZrrkz */ + }, + { /* 3168 */ + 235, + /* VANDNPSrm */ + }, + { /* 3169 */ + 236, + /* VANDNPSrr */ + }, + { /* 3170 */ + 204, + /* VANDPDYrm */ + }, + { /* 3171 */ + 205, + /* VANDPDYrr */ + }, + { /* 3172 */ + 206, + /* VANDPDZ128rm */ + }, + { /* 3173 */ + 207, + /* VANDPDZ128rmb */ + }, + { /* 3174 */ + 208, + /* VANDPDZ128rmbk */ + }, + { /* 3175 */ + 209, + /* VANDPDZ128rmbkz */ + }, + { /* 3176 */ + 203, + /* VANDPDZ128rmk */ + }, + { /* 3177 */ + 210, + /* VANDPDZ128rmkz */ + }, + { /* 3178 */ + 211, + /* VANDPDZ128rr */ + }, + { /* 3179 */ + 212, + /* VANDPDZ128rrk */ + }, + { /* 3180 */ + 213, + /* VANDPDZ128rrkz */ + }, + { /* 3181 */ + 214, + /* VANDPDZ256rm */ + }, + { /* 3182 */ + 215, + /* VANDPDZ256rmb */ + }, + { /* 3183 */ + 216, + /* VANDPDZ256rmbk */ + }, + { /* 3184 */ + 217, + /* VANDPDZ256rmbkz */ + }, + { /* 3185 */ + 218, + /* VANDPDZ256rmk */ + }, + { /* 3186 */ + 219, + /* VANDPDZ256rmkz */ + }, + { /* 3187 */ + 220, + /* VANDPDZ256rr */ + }, + { /* 3188 */ + 221, + /* VANDPDZ256rrk */ + }, + { /* 3189 */ + 222, + /* VANDPDZ256rrkz */ + }, + { /* 3190 */ + 223, + /* VANDPDZrm */ + }, + { /* 3191 */ + 224, + /* VANDPDZrmb */ + }, + { /* 3192 */ + 225, + /* VANDPDZrmbk */ + }, + { /* 3193 */ + 226, + /* VANDPDZrmbkz */ + }, + { /* 3194 */ + 227, + /* VANDPDZrmk */ + }, + { /* 3195 */ + 228, + /* VANDPDZrmkz */ + }, + { /* 3196 */ + 229, + /* VANDPDZrr */ + }, + { /* 3197 */ + 233, + /* VANDPDZrrk */ + }, + { /* 3198 */ + 234, + /* VANDPDZrrkz */ + }, + { /* 3199 */ + 235, + /* VANDPDrm */ + }, + { /* 3200 */ + 236, + /* VANDPDrr */ + }, + { /* 3201 */ + 204, + /* VANDPSYrm */ + }, + { /* 3202 */ + 205, + /* VANDPSYrr */ + }, + { /* 3203 */ + 206, + /* VANDPSZ128rm */ + }, + { /* 3204 */ + 237, + /* VANDPSZ128rmb */ + }, + { /* 3205 */ + 238, + /* VANDPSZ128rmbk */ + }, + { /* 3206 */ + 239, + /* VANDPSZ128rmbkz */ + }, + { /* 3207 */ + 203, + /* VANDPSZ128rmk */ + }, + { /* 3208 */ + 210, + /* VANDPSZ128rmkz */ + }, + { /* 3209 */ + 211, + /* VANDPSZ128rr */ + }, + { /* 3210 */ + 212, + /* VANDPSZ128rrk */ + }, + { /* 3211 */ + 213, + /* VANDPSZ128rrkz */ + }, + { /* 3212 */ + 214, + /* VANDPSZ256rm */ + }, + { /* 3213 */ + 240, + /* VANDPSZ256rmb */ + }, + { /* 3214 */ + 241, + /* VANDPSZ256rmbk */ + }, + { /* 3215 */ + 242, + /* VANDPSZ256rmbkz */ + }, + { /* 3216 */ + 218, + /* VANDPSZ256rmk */ + }, + { /* 3217 */ + 219, + /* VANDPSZ256rmkz */ + }, + { /* 3218 */ + 220, + /* VANDPSZ256rr */ + }, + { /* 3219 */ + 221, + /* VANDPSZ256rrk */ + }, + { /* 3220 */ + 222, + /* VANDPSZ256rrkz */ + }, + { /* 3221 */ + 223, + /* VANDPSZrm */ + }, + { /* 3222 */ + 243, + /* VANDPSZrmb */ + }, + { /* 3223 */ + 244, + /* VANDPSZrmbk */ + }, + { /* 3224 */ + 245, + /* VANDPSZrmbkz */ + }, + { /* 3225 */ + 227, + /* VANDPSZrmk */ + }, + { /* 3226 */ + 228, + /* VANDPSZrmkz */ + }, + { /* 3227 */ + 229, + /* VANDPSZrr */ + }, + { /* 3228 */ + 233, + /* VANDPSZrrk */ + }, + { /* 3229 */ + 234, + /* VANDPSZrrkz */ + }, + { /* 3230 */ + 235, + /* VANDPSrm */ + }, + { /* 3231 */ + 236, + /* VANDPSrr */ + }, + { /* 3232 */ + 206, + /* VBLENDMPDZ128rm */ + }, + { /* 3233 */ + 207, + /* VBLENDMPDZ128rmb */ + }, + { /* 3234 */ + 209, + /* VBLENDMPDZ128rmbk */ + }, + { /* 3235 */ + 209, + /* VBLENDMPDZ128rmbkz */ + }, + { /* 3236 */ + 210, + /* VBLENDMPDZ128rmk */ + }, + { /* 3237 */ + 210, + /* VBLENDMPDZ128rmkz */ + }, + { /* 3238 */ + 211, + /* VBLENDMPDZ128rr */ + }, + { /* 3239 */ + 213, + /* VBLENDMPDZ128rrk */ + }, + { /* 3240 */ + 213, + /* VBLENDMPDZ128rrkz */ + }, + { /* 3241 */ + 214, + /* VBLENDMPDZ256rm */ + }, + { /* 3242 */ + 215, + /* VBLENDMPDZ256rmb */ + }, + { /* 3243 */ + 217, + /* VBLENDMPDZ256rmbk */ + }, + { /* 3244 */ + 217, + /* VBLENDMPDZ256rmbkz */ + }, + { /* 3245 */ + 219, + /* VBLENDMPDZ256rmk */ + }, + { /* 3246 */ + 219, + /* VBLENDMPDZ256rmkz */ + }, + { /* 3247 */ + 220, + /* VBLENDMPDZ256rr */ + }, + { /* 3248 */ + 222, + /* VBLENDMPDZ256rrk */ + }, + { /* 3249 */ + 222, + /* VBLENDMPDZ256rrkz */ + }, + { /* 3250 */ + 223, + /* VBLENDMPDZrm */ + }, + { /* 3251 */ + 224, + /* VBLENDMPDZrmb */ + }, + { /* 3252 */ + 226, + /* VBLENDMPDZrmbk */ + }, + { /* 3253 */ + 226, + /* VBLENDMPDZrmbkz */ + }, + { /* 3254 */ + 228, + /* VBLENDMPDZrmk */ + }, + { /* 3255 */ + 228, + /* VBLENDMPDZrmkz */ + }, + { /* 3256 */ + 229, + /* VBLENDMPDZrr */ + }, + { /* 3257 */ + 234, + /* VBLENDMPDZrrk */ + }, + { /* 3258 */ + 234, + /* VBLENDMPDZrrkz */ + }, + { /* 3259 */ + 206, + /* VBLENDMPSZ128rm */ + }, + { /* 3260 */ + 237, + /* VBLENDMPSZ128rmb */ + }, + { /* 3261 */ + 239, + /* VBLENDMPSZ128rmbk */ + }, + { /* 3262 */ + 239, + /* VBLENDMPSZ128rmbkz */ + }, + { /* 3263 */ + 210, + /* VBLENDMPSZ128rmk */ + }, + { /* 3264 */ + 210, + /* VBLENDMPSZ128rmkz */ + }, + { /* 3265 */ + 211, + /* VBLENDMPSZ128rr */ + }, + { /* 3266 */ + 213, + /* VBLENDMPSZ128rrk */ + }, + { /* 3267 */ + 213, + /* VBLENDMPSZ128rrkz */ + }, + { /* 3268 */ + 214, + /* VBLENDMPSZ256rm */ + }, + { /* 3269 */ + 240, + /* VBLENDMPSZ256rmb */ + }, + { /* 3270 */ + 242, + /* VBLENDMPSZ256rmbk */ + }, + { /* 3271 */ + 242, + /* VBLENDMPSZ256rmbkz */ + }, + { /* 3272 */ + 219, + /* VBLENDMPSZ256rmk */ + }, + { /* 3273 */ + 219, + /* VBLENDMPSZ256rmkz */ + }, + { /* 3274 */ + 220, + /* VBLENDMPSZ256rr */ + }, + { /* 3275 */ + 222, + /* VBLENDMPSZ256rrk */ + }, + { /* 3276 */ + 222, + /* VBLENDMPSZ256rrkz */ + }, + { /* 3277 */ + 223, + /* VBLENDMPSZrm */ + }, + { /* 3278 */ + 243, + /* VBLENDMPSZrmb */ + }, + { /* 3279 */ + 245, + /* VBLENDMPSZrmbk */ + }, + { /* 3280 */ + 245, + /* VBLENDMPSZrmbkz */ + }, + { /* 3281 */ + 228, + /* VBLENDMPSZrmk */ + }, + { /* 3282 */ + 228, + /* VBLENDMPSZrmkz */ + }, + { /* 3283 */ + 229, + /* VBLENDMPSZrr */ + }, + { /* 3284 */ + 234, + /* VBLENDMPSZrrk */ + }, + { /* 3285 */ + 234, + /* VBLENDMPSZrrkz */ + }, + { /* 3286 */ + 297, + /* VBLENDPDYrmi */ + }, + { /* 3287 */ + 298, + /* VBLENDPDYrri */ + }, + { /* 3288 */ + 299, + /* VBLENDPDrmi */ + }, + { /* 3289 */ + 300, + /* VBLENDPDrri */ + }, + { /* 3290 */ + 297, + /* VBLENDPSYrmi */ + }, + { /* 3291 */ + 298, + /* VBLENDPSYrri */ + }, + { /* 3292 */ + 299, + /* VBLENDPSrmi */ + }, + { /* 3293 */ + 300, + /* VBLENDPSrri */ + }, + { /* 3294 */ + 301, + /* VBLENDVPDYrm */ + }, + { /* 3295 */ + 302, + /* VBLENDVPDYrr */ + }, + { /* 3296 */ + 303, + /* VBLENDVPDrm */ + }, + { /* 3297 */ + 304, + /* VBLENDVPDrr */ + }, + { /* 3298 */ + 301, + /* VBLENDVPSYrm */ + }, + { /* 3299 */ + 302, + /* VBLENDVPSYrr */ + }, + { /* 3300 */ + 303, + /* VBLENDVPSrm */ + }, + { /* 3301 */ + 304, + /* VBLENDVPSrr */ + }, + { /* 3302 */ + 305, + /* VBROADCASTF128 */ + }, + { /* 3303 */ + 306, + /* VBROADCASTF32X2Z256m */ + }, + { /* 3304 */ + 307, + /* VBROADCASTF32X2Z256mk */ + }, + { /* 3305 */ + 308, + /* VBROADCASTF32X2Z256mkz */ + }, + { /* 3306 */ + 309, + /* VBROADCASTF32X2Z256r */ + }, + { /* 3307 */ + 310, + /* VBROADCASTF32X2Z256rk */ + }, + { /* 3308 */ + 311, + /* VBROADCASTF32X2Z256rkz */ + }, + { /* 3309 */ + 312, + /* VBROADCASTF32X2Zm */ + }, + { /* 3310 */ + 313, + /* VBROADCASTF32X2Zmk */ + }, + { /* 3311 */ + 314, + /* VBROADCASTF32X2Zmkz */ + }, + { /* 3312 */ + 315, + /* VBROADCASTF32X2Zr */ + }, + { /* 3313 */ + 316, + /* VBROADCASTF32X2Zrk */ + }, + { /* 3314 */ + 317, + /* VBROADCASTF32X2Zrkz */ + }, + { /* 3315 */ + 318, + /* VBROADCASTF32X4Z256rm */ + }, + { /* 3316 */ + 319, + /* VBROADCASTF32X4Z256rmk */ + }, + { /* 3317 */ + 320, + /* VBROADCASTF32X4Z256rmkz */ + }, + { /* 3318 */ + 321, + /* VBROADCASTF32X4rm */ + }, + { /* 3319 */ + 322, + /* VBROADCASTF32X4rmk */ + }, + { /* 3320 */ + 323, + /* VBROADCASTF32X4rmkz */ + }, + { /* 3321 */ + 324, + /* VBROADCASTF32X8rm */ + }, + { /* 3322 */ + 325, + /* VBROADCASTF32X8rmk */ + }, + { /* 3323 */ + 326, + /* VBROADCASTF32X8rmkz */ + }, + { /* 3324 */ + 318, + /* VBROADCASTF64X2Z128rm */ + }, + { /* 3325 */ + 319, + /* VBROADCASTF64X2Z128rmk */ + }, + { /* 3326 */ + 320, + /* VBROADCASTF64X2Z128rmkz */ + }, + { /* 3327 */ + 321, + /* VBROADCASTF64X2rm */ + }, + { /* 3328 */ + 322, + /* VBROADCASTF64X2rmk */ + }, + { /* 3329 */ + 323, + /* VBROADCASTF64X2rmkz */ + }, + { /* 3330 */ + 324, + /* VBROADCASTF64X4rm */ + }, + { /* 3331 */ + 325, + /* VBROADCASTF64X4rmk */ + }, + { /* 3332 */ + 326, + /* VBROADCASTF64X4rmkz */ + }, + { /* 3333 */ + 305, + /* VBROADCASTI128 */ + }, + { /* 3334 */ + 327, + /* VBROADCASTI32X2Z128m */ + }, + { /* 3335 */ + 328, + /* VBROADCASTI32X2Z128mk */ + }, + { /* 3336 */ + 329, + /* VBROADCASTI32X2Z128mkz */ + }, + { /* 3337 */ + 330, + /* VBROADCASTI32X2Z128r */ + }, + { /* 3338 */ + 331, + /* VBROADCASTI32X2Z128rk */ + }, + { /* 3339 */ + 332, + /* VBROADCASTI32X2Z128rkz */ + }, + { /* 3340 */ + 306, + /* VBROADCASTI32X2Z256m */ + }, + { /* 3341 */ + 307, + /* VBROADCASTI32X2Z256mk */ + }, + { /* 3342 */ + 308, + /* VBROADCASTI32X2Z256mkz */ + }, + { /* 3343 */ + 309, + /* VBROADCASTI32X2Z256r */ + }, + { /* 3344 */ + 310, + /* VBROADCASTI32X2Z256rk */ + }, + { /* 3345 */ + 311, + /* VBROADCASTI32X2Z256rkz */ + }, + { /* 3346 */ + 312, + /* VBROADCASTI32X2Zm */ + }, + { /* 3347 */ + 313, + /* VBROADCASTI32X2Zmk */ + }, + { /* 3348 */ + 314, + /* VBROADCASTI32X2Zmkz */ + }, + { /* 3349 */ + 315, + /* VBROADCASTI32X2Zr */ + }, + { /* 3350 */ + 316, + /* VBROADCASTI32X2Zrk */ + }, + { /* 3351 */ + 317, + /* VBROADCASTI32X2Zrkz */ + }, + { /* 3352 */ + 318, + /* VBROADCASTI32X4Z256rm */ + }, + { /* 3353 */ + 319, + /* VBROADCASTI32X4Z256rmk */ + }, + { /* 3354 */ + 320, + /* VBROADCASTI32X4Z256rmkz */ + }, + { /* 3355 */ + 321, + /* VBROADCASTI32X4rm */ + }, + { /* 3356 */ + 322, + /* VBROADCASTI32X4rmk */ + }, + { /* 3357 */ + 323, + /* VBROADCASTI32X4rmkz */ + }, + { /* 3358 */ + 324, + /* VBROADCASTI32X8rm */ + }, + { /* 3359 */ + 325, + /* VBROADCASTI32X8rmk */ + }, + { /* 3360 */ + 326, + /* VBROADCASTI32X8rmkz */ + }, + { /* 3361 */ + 318, + /* VBROADCASTI64X2Z128rm */ + }, + { /* 3362 */ + 319, + /* VBROADCASTI64X2Z128rmk */ + }, + { /* 3363 */ + 320, + /* VBROADCASTI64X2Z128rmkz */ + }, + { /* 3364 */ + 321, + /* VBROADCASTI64X2rm */ + }, + { /* 3365 */ + 322, + /* VBROADCASTI64X2rmk */ + }, + { /* 3366 */ + 323, + /* VBROADCASTI64X2rmkz */ + }, + { /* 3367 */ + 324, + /* VBROADCASTI64X4rm */ + }, + { /* 3368 */ + 325, + /* VBROADCASTI64X4rmk */ + }, + { /* 3369 */ + 326, + /* VBROADCASTI64X4rmkz */ + }, + { /* 3370 */ + 305, + /* VBROADCASTSDYrm */ + }, + { /* 3371 */ + 333, + /* VBROADCASTSDYrr */ + }, + { /* 3372 */ + 306, + /* VBROADCASTSDZ256m */ + }, + { /* 3373 */ + 307, + /* VBROADCASTSDZ256mk */ + }, + { /* 3374 */ + 308, + /* VBROADCASTSDZ256mkz */ + }, + { /* 3375 */ + 309, + /* VBROADCASTSDZ256r */ + }, + { /* 3376 */ + 310, + /* VBROADCASTSDZ256rk */ + }, + { /* 3377 */ + 311, + /* VBROADCASTSDZ256rkz */ + }, + { /* 3378 */ + 312, + /* VBROADCASTSDZm */ + }, + { /* 3379 */ + 313, + /* VBROADCASTSDZmk */ + }, + { /* 3380 */ + 314, + /* VBROADCASTSDZmkz */ + }, + { /* 3381 */ + 315, + /* VBROADCASTSDZr */ + }, + { /* 3382 */ + 316, + /* VBROADCASTSDZrk */ + }, + { /* 3383 */ + 317, + /* VBROADCASTSDZrkz */ + }, + { /* 3384 */ + 305, + /* VBROADCASTSSYrm */ + }, + { /* 3385 */ + 333, + /* VBROADCASTSSYrr */ + }, + { /* 3386 */ + 334, + /* VBROADCASTSSZ128m */ + }, + { /* 3387 */ + 335, + /* VBROADCASTSSZ128mk */ + }, + { /* 3388 */ + 336, + /* VBROADCASTSSZ128mkz */ + }, + { /* 3389 */ + 330, + /* VBROADCASTSSZ128r */ + }, + { /* 3390 */ + 331, + /* VBROADCASTSSZ128rk */ + }, + { /* 3391 */ + 332, + /* VBROADCASTSSZ128rkz */ + }, + { /* 3392 */ + 337, + /* VBROADCASTSSZ256m */ + }, + { /* 3393 */ + 338, + /* VBROADCASTSSZ256mk */ + }, + { /* 3394 */ + 339, + /* VBROADCASTSSZ256mkz */ + }, + { /* 3395 */ + 309, + /* VBROADCASTSSZ256r */ + }, + { /* 3396 */ + 310, + /* VBROADCASTSSZ256rk */ + }, + { /* 3397 */ + 311, + /* VBROADCASTSSZ256rkz */ + }, + { /* 3398 */ + 340, + /* VBROADCASTSSZm */ + }, + { /* 3399 */ + 341, + /* VBROADCASTSSZmk */ + }, + { /* 3400 */ + 342, + /* VBROADCASTSSZmkz */ + }, + { /* 3401 */ + 315, + /* VBROADCASTSSZr */ + }, + { /* 3402 */ + 316, + /* VBROADCASTSSZrk */ + }, + { /* 3403 */ + 317, + /* VBROADCASTSSZrkz */ + }, + { /* 3404 */ + 30, + /* VBROADCASTSSrm */ + }, + { /* 3405 */ + 31, + /* VBROADCASTSSrr */ + }, + { /* 3406 */ + 343, + /* VCMPPDYrmi */ + }, + { /* 3407 */ + 0, + /* */ + }, + { /* 3408 */ + 344, + /* VCMPPDYrri */ + }, + { /* 3409 */ + 0, + /* */ + }, + { /* 3410 */ + 345, + /* VCMPPDZ128rmbi */ + }, + { /* 3411 */ + 0, + /* */ + }, + { /* 3412 */ + 0, + /* */ + }, + { /* 3413 */ + 346, + /* VCMPPDZ128rmbik */ + }, + { /* 3414 */ + 347, + /* VCMPPDZ128rmi */ + }, + { /* 3415 */ + 0, + /* */ + }, + { /* 3416 */ + 0, + /* */ + }, + { /* 3417 */ + 348, + /* VCMPPDZ128rmik */ + }, + { /* 3418 */ + 349, + /* VCMPPDZ128rri */ + }, + { /* 3419 */ + 0, + /* */ + }, + { /* 3420 */ + 0, + /* */ + }, + { /* 3421 */ + 350, + /* VCMPPDZ128rrik */ + }, + { /* 3422 */ + 351, + /* VCMPPDZ256rmbi */ + }, + { /* 3423 */ + 0, + /* */ + }, + { /* 3424 */ + 0, + /* */ + }, + { /* 3425 */ + 352, + /* VCMPPDZ256rmbik */ + }, + { /* 3426 */ + 353, + /* VCMPPDZ256rmi */ + }, + { /* 3427 */ + 0, + /* */ + }, + { /* 3428 */ + 0, + /* */ + }, + { /* 3429 */ + 354, + /* VCMPPDZ256rmik */ + }, + { /* 3430 */ + 355, + /* VCMPPDZ256rri */ + }, + { /* 3431 */ + 0, + /* */ + }, + { /* 3432 */ + 0, + /* */ + }, + { /* 3433 */ + 356, + /* VCMPPDZ256rrik */ + }, + { /* 3434 */ + 357, + /* VCMPPDZrmbi */ + }, + { /* 3435 */ + 0, + /* */ + }, + { /* 3436 */ + 0, + /* */ + }, + { /* 3437 */ + 358, + /* VCMPPDZrmbik */ + }, + { /* 3438 */ + 359, + /* VCMPPDZrmi */ + }, + { /* 3439 */ + 0, + /* */ + }, + { /* 3440 */ + 0, + /* */ + }, + { /* 3441 */ + 360, + /* VCMPPDZrmik */ + }, + { /* 3442 */ + 361, + /* VCMPPDZrri */ + }, + { /* 3443 */ + 0, + /* */ + }, + { /* 3444 */ + 0, + /* */ + }, + { /* 3445 */ + 362, + /* VCMPPDZrrib */ + }, + { /* 3446 */ + 0, + /* */ + }, + { /* 3447 */ + 0, + /* */ + }, + { /* 3448 */ + 363, + /* VCMPPDZrribk */ + }, + { /* 3449 */ + 364, + /* VCMPPDZrrik */ + }, + { /* 3450 */ + 365, + /* VCMPPDrmi */ + }, + { /* 3451 */ + 0, + /* */ + }, + { /* 3452 */ + 366, + /* VCMPPDrri */ + }, + { /* 3453 */ + 0, + /* */ + }, + { /* 3454 */ + 343, + /* VCMPPSYrmi */ + }, + { /* 3455 */ + 0, + /* */ + }, + { /* 3456 */ + 344, + /* VCMPPSYrri */ + }, + { /* 3457 */ + 0, + /* */ + }, + { /* 3458 */ + 367, + /* VCMPPSZ128rmbi */ + }, + { /* 3459 */ + 0, + /* */ + }, + { /* 3460 */ + 0, + /* */ + }, + { /* 3461 */ + 368, + /* VCMPPSZ128rmbik */ + }, + { /* 3462 */ + 347, + /* VCMPPSZ128rmi */ + }, + { /* 3463 */ + 0, + /* */ + }, + { /* 3464 */ + 0, + /* */ + }, + { /* 3465 */ + 348, + /* VCMPPSZ128rmik */ + }, + { /* 3466 */ + 349, + /* VCMPPSZ128rri */ + }, + { /* 3467 */ + 0, + /* */ + }, + { /* 3468 */ + 0, + /* */ + }, + { /* 3469 */ + 350, + /* VCMPPSZ128rrik */ + }, + { /* 3470 */ + 369, + /* VCMPPSZ256rmbi */ + }, + { /* 3471 */ + 0, + /* */ + }, + { /* 3472 */ + 0, + /* */ + }, + { /* 3473 */ + 370, + /* VCMPPSZ256rmbik */ + }, + { /* 3474 */ + 353, + /* VCMPPSZ256rmi */ + }, + { /* 3475 */ + 0, + /* */ + }, + { /* 3476 */ + 0, + /* */ + }, + { /* 3477 */ + 354, + /* VCMPPSZ256rmik */ + }, + { /* 3478 */ + 355, + /* VCMPPSZ256rri */ + }, + { /* 3479 */ + 0, + /* */ + }, + { /* 3480 */ + 0, + /* */ + }, + { /* 3481 */ + 356, + /* VCMPPSZ256rrik */ + }, + { /* 3482 */ + 371, + /* VCMPPSZrmbi */ + }, + { /* 3483 */ + 0, + /* */ + }, + { /* 3484 */ + 0, + /* */ + }, + { /* 3485 */ + 372, + /* VCMPPSZrmbik */ + }, + { /* 3486 */ + 359, + /* VCMPPSZrmi */ + }, + { /* 3487 */ + 0, + /* */ + }, + { /* 3488 */ + 0, + /* */ + }, + { /* 3489 */ + 360, + /* VCMPPSZrmik */ + }, + { /* 3490 */ + 361, + /* VCMPPSZrri */ + }, + { /* 3491 */ + 0, + /* */ + }, + { /* 3492 */ + 0, + /* */ + }, + { /* 3493 */ + 373, + /* VCMPPSZrrib */ + }, + { /* 3494 */ + 0, + /* */ + }, + { /* 3495 */ + 0, + /* */ + }, + { /* 3496 */ + 374, + /* VCMPPSZrribk */ + }, + { /* 3497 */ + 364, + /* VCMPPSZrrik */ + }, + { /* 3498 */ + 365, + /* VCMPPSrmi */ + }, + { /* 3499 */ + 0, + /* */ + }, + { /* 3500 */ + 366, + /* VCMPPSrri */ + }, + { /* 3501 */ + 0, + /* */ + }, + { /* 3502 */ + 0, + /* */ + }, + { /* 3503 */ + 345, + /* VCMPSDZrm_Int */ + }, + { /* 3504 */ + 346, + /* VCMPSDZrm_Intk */ + }, + { /* 3505 */ + 0, + /* */ + }, + { /* 3506 */ + 0, + /* */ + }, + { /* 3507 */ + 0, + /* */ + }, + { /* 3508 */ + 349, + /* VCMPSDZrr_Int */ + }, + { /* 3509 */ + 350, + /* VCMPSDZrr_Intk */ + }, + { /* 3510 */ + 375, + /* VCMPSDZrrb_Int */ + }, + { /* 3511 */ + 376, + /* VCMPSDZrrb_Intk */ + }, + { /* 3512 */ + 0, + /* */ + }, + { /* 3513 */ + 0, + /* */ + }, + { /* 3514 */ + 0, + /* */ + }, + { /* 3515 */ + 0, + /* */ + }, + { /* 3516 */ + 365, + /* VCMPSDrm */ + }, + { /* 3517 */ + 0, + /* */ + }, + { /* 3518 */ + 0, + /* */ + }, + { /* 3519 */ + 366, + /* VCMPSDrr */ + }, + { /* 3520 */ + 0, + /* */ + }, + { /* 3521 */ + 0, + /* */ + }, + { /* 3522 */ + 0, + /* */ + }, + { /* 3523 */ + 367, + /* VCMPSSZrm_Int */ + }, + { /* 3524 */ + 368, + /* VCMPSSZrm_Intk */ + }, + { /* 3525 */ + 0, + /* */ + }, + { /* 3526 */ + 0, + /* */ + }, + { /* 3527 */ + 0, + /* */ + }, + { /* 3528 */ + 349, + /* VCMPSSZrr_Int */ + }, + { /* 3529 */ + 350, + /* VCMPSSZrr_Intk */ + }, + { /* 3530 */ + 375, + /* VCMPSSZrrb_Int */ + }, + { /* 3531 */ + 376, + /* VCMPSSZrrb_Intk */ + }, + { /* 3532 */ + 0, + /* */ + }, + { /* 3533 */ + 0, + /* */ + }, + { /* 3534 */ + 0, + /* */ + }, + { /* 3535 */ + 0, + /* */ + }, + { /* 3536 */ + 365, + /* VCMPSSrm */ + }, + { /* 3537 */ + 0, + /* */ + }, + { /* 3538 */ + 0, + /* */ + }, + { /* 3539 */ + 366, + /* VCMPSSrr */ + }, + { /* 3540 */ + 0, + /* */ + }, + { /* 3541 */ + 0, + /* */ + }, + { /* 3542 */ + 327, + /* VCOMISDZrm */ + }, + { /* 3543 */ + 0, + /* */ + }, + { /* 3544 */ + 377, + /* VCOMISDZrr */ + }, + { /* 3545 */ + 0, + /* */ + }, + { /* 3546 */ + 377, + /* VCOMISDZrrb */ + }, + { /* 3547 */ + 30, + /* VCOMISDrm */ + }, + { /* 3548 */ + 0, + /* */ + }, + { /* 3549 */ + 31, + /* VCOMISDrr */ + }, + { /* 3550 */ + 0, + /* */ + }, + { /* 3551 */ + 334, + /* VCOMISSZrm */ + }, + { /* 3552 */ + 0, + /* */ + }, + { /* 3553 */ + 378, + /* VCOMISSZrr */ + }, + { /* 3554 */ + 0, + /* */ + }, + { /* 3555 */ + 378, + /* VCOMISSZrrb */ + }, + { /* 3556 */ + 30, + /* VCOMISSrm */ + }, + { /* 3557 */ + 0, + /* */ + }, + { /* 3558 */ + 31, + /* VCOMISSrr */ + }, + { /* 3559 */ + 0, + /* */ + }, + { /* 3560 */ + 379, + /* VCOMPRESSPDZ128mr */ + }, + { /* 3561 */ + 380, + /* VCOMPRESSPDZ128mrk */ + }, + { /* 3562 */ + 381, + /* VCOMPRESSPDZ128rr */ + }, + { /* 3563 */ + 382, + /* VCOMPRESSPDZ128rrk */ + }, + { /* 3564 */ + 383, + /* VCOMPRESSPDZ128rrkz */ + }, + { /* 3565 */ + 384, + /* VCOMPRESSPDZ256mr */ + }, + { /* 3566 */ + 385, + /* VCOMPRESSPDZ256mrk */ + }, + { /* 3567 */ + 386, + /* VCOMPRESSPDZ256rr */ + }, + { /* 3568 */ + 387, + /* VCOMPRESSPDZ256rrk */ + }, + { /* 3569 */ + 388, + /* VCOMPRESSPDZ256rrkz */ + }, + { /* 3570 */ + 389, + /* VCOMPRESSPDZmr */ + }, + { /* 3571 */ + 390, + /* VCOMPRESSPDZmrk */ + }, + { /* 3572 */ + 391, + /* VCOMPRESSPDZrr */ + }, + { /* 3573 */ + 392, + /* VCOMPRESSPDZrrk */ + }, + { /* 3574 */ + 393, + /* VCOMPRESSPDZrrkz */ + }, + { /* 3575 */ + 394, + /* VCOMPRESSPSZ128mr */ + }, + { /* 3576 */ + 395, + /* VCOMPRESSPSZ128mrk */ + }, + { /* 3577 */ + 381, + /* VCOMPRESSPSZ128rr */ + }, + { /* 3578 */ + 382, + /* VCOMPRESSPSZ128rrk */ + }, + { /* 3579 */ + 383, + /* VCOMPRESSPSZ128rrkz */ + }, + { /* 3580 */ + 396, + /* VCOMPRESSPSZ256mr */ + }, + { /* 3581 */ + 397, + /* VCOMPRESSPSZ256mrk */ + }, + { /* 3582 */ + 386, + /* VCOMPRESSPSZ256rr */ + }, + { /* 3583 */ + 387, + /* VCOMPRESSPSZ256rrk */ + }, + { /* 3584 */ + 388, + /* VCOMPRESSPSZ256rrkz */ + }, + { /* 3585 */ + 398, + /* VCOMPRESSPSZmr */ + }, + { /* 3586 */ + 399, + /* VCOMPRESSPSZmrk */ + }, + { /* 3587 */ + 391, + /* VCOMPRESSPSZrr */ + }, + { /* 3588 */ + 392, + /* VCOMPRESSPSZrrk */ + }, + { /* 3589 */ + 393, + /* VCOMPRESSPSZrrkz */ + }, + { /* 3590 */ + 305, + /* VCVTDQ2PDYrm */ + }, + { /* 3591 */ + 333, + /* VCVTDQ2PDYrr */ + }, + { /* 3592 */ + 327, + /* VCVTDQ2PDZ128rm */ + }, + { /* 3593 */ + 334, + /* VCVTDQ2PDZ128rmb */ + }, + { /* 3594 */ + 335, + /* VCVTDQ2PDZ128rmbk */ + }, + { /* 3595 */ + 336, + /* VCVTDQ2PDZ128rmbkz */ + }, + { /* 3596 */ + 328, + /* VCVTDQ2PDZ128rmk */ + }, + { /* 3597 */ + 329, + /* VCVTDQ2PDZ128rmkz */ + }, + { /* 3598 */ + 377, + /* VCVTDQ2PDZ128rr */ + }, + { /* 3599 */ + 400, + /* VCVTDQ2PDZ128rrk */ + }, + { /* 3600 */ + 401, + /* VCVTDQ2PDZ128rrkz */ + }, + { /* 3601 */ + 318, + /* VCVTDQ2PDZ256rm */ + }, + { /* 3602 */ + 337, + /* VCVTDQ2PDZ256rmb */ + }, + { /* 3603 */ + 338, + /* VCVTDQ2PDZ256rmbk */ + }, + { /* 3604 */ + 339, + /* VCVTDQ2PDZ256rmbkz */ + }, + { /* 3605 */ + 319, + /* VCVTDQ2PDZ256rmk */ + }, + { /* 3606 */ + 320, + /* VCVTDQ2PDZ256rmkz */ + }, + { /* 3607 */ + 402, + /* VCVTDQ2PDZ256rr */ + }, + { /* 3608 */ + 403, + /* VCVTDQ2PDZ256rrk */ + }, + { /* 3609 */ + 404, + /* VCVTDQ2PDZ256rrkz */ + }, + { /* 3610 */ + 324, + /* VCVTDQ2PDZrm */ + }, + { /* 3611 */ + 340, + /* VCVTDQ2PDZrmb */ + }, + { /* 3612 */ + 341, + /* VCVTDQ2PDZrmbk */ + }, + { /* 3613 */ + 342, + /* VCVTDQ2PDZrmbkz */ + }, + { /* 3614 */ + 325, + /* VCVTDQ2PDZrmk */ + }, + { /* 3615 */ + 326, + /* VCVTDQ2PDZrmkz */ + }, + { /* 3616 */ + 405, + /* VCVTDQ2PDZrr */ + }, + { /* 3617 */ + 406, + /* VCVTDQ2PDZrrk */ + }, + { /* 3618 */ + 407, + /* VCVTDQ2PDZrrkz */ + }, + { /* 3619 */ + 30, + /* VCVTDQ2PDrm */ + }, + { /* 3620 */ + 31, + /* VCVTDQ2PDrr */ + }, + { /* 3621 */ + 305, + /* VCVTDQ2PSYrm */ + }, + { /* 3622 */ + 408, + /* VCVTDQ2PSYrr */ + }, + { /* 3623 */ + 409, + /* VCVTDQ2PSZ128rm */ + }, + { /* 3624 */ + 334, + /* VCVTDQ2PSZ128rmb */ + }, + { /* 3625 */ + 335, + /* VCVTDQ2PSZ128rmbk */ + }, + { /* 3626 */ + 336, + /* VCVTDQ2PSZ128rmbkz */ + }, + { /* 3627 */ + 410, + /* VCVTDQ2PSZ128rmk */ + }, + { /* 3628 */ + 411, + /* VCVTDQ2PSZ128rmkz */ + }, + { /* 3629 */ + 330, + /* VCVTDQ2PSZ128rr */ + }, + { /* 3630 */ + 331, + /* VCVTDQ2PSZ128rrk */ + }, + { /* 3631 */ + 332, + /* VCVTDQ2PSZ128rrkz */ + }, + { /* 3632 */ + 412, + /* VCVTDQ2PSZ256rm */ + }, + { /* 3633 */ + 337, + /* VCVTDQ2PSZ256rmb */ + }, + { /* 3634 */ + 338, + /* VCVTDQ2PSZ256rmbk */ + }, + { /* 3635 */ + 339, + /* VCVTDQ2PSZ256rmbkz */ + }, + { /* 3636 */ + 413, + /* VCVTDQ2PSZ256rmk */ + }, + { /* 3637 */ + 414, + /* VCVTDQ2PSZ256rmkz */ + }, + { /* 3638 */ + 415, + /* VCVTDQ2PSZ256rr */ + }, + { /* 3639 */ + 416, + /* VCVTDQ2PSZ256rrk */ + }, + { /* 3640 */ + 417, + /* VCVTDQ2PSZ256rrkz */ + }, + { /* 3641 */ + 418, + /* VCVTDQ2PSZrm */ + }, + { /* 3642 */ + 340, + /* VCVTDQ2PSZrmb */ + }, + { /* 3643 */ + 341, + /* VCVTDQ2PSZrmbk */ + }, + { /* 3644 */ + 342, + /* VCVTDQ2PSZrmbkz */ + }, + { /* 3645 */ + 419, + /* VCVTDQ2PSZrmk */ + }, + { /* 3646 */ + 420, + /* VCVTDQ2PSZrmkz */ + }, + { /* 3647 */ + 421, + /* VCVTDQ2PSZrr */ + }, + { /* 3648 */ + 422, + /* VCVTDQ2PSZrrb */ + }, + { /* 3649 */ + 423, + /* VCVTDQ2PSZrrbk */ + }, + { /* 3650 */ + 424, + /* VCVTDQ2PSZrrbkz */ + }, + { /* 3651 */ + 425, + /* VCVTDQ2PSZrrk */ + }, + { /* 3652 */ + 426, + /* VCVTDQ2PSZrrkz */ + }, + { /* 3653 */ + 30, + /* VCVTDQ2PSrm */ + }, + { /* 3654 */ + 31, + /* VCVTDQ2PSrr */ + }, + { /* 3655 */ + 30, + /* VCVTPD2DQYrm */ + }, + { /* 3656 */ + 427, + /* VCVTPD2DQYrr */ + }, + { /* 3657 */ + 409, + /* VCVTPD2DQZ128rm */ + }, + { /* 3658 */ + 327, + /* VCVTPD2DQZ128rmb */ + }, + { /* 3659 */ + 328, + /* VCVTPD2DQZ128rmbk */ + }, + { /* 3660 */ + 329, + /* VCVTPD2DQZ128rmbkz */ + }, + { /* 3661 */ + 410, + /* VCVTPD2DQZ128rmk */ + }, + { /* 3662 */ + 411, + /* VCVTPD2DQZ128rmkz */ + }, + { /* 3663 */ + 330, + /* VCVTPD2DQZ128rr */ + }, + { /* 3664 */ + 331, + /* VCVTPD2DQZ128rrk */ + }, + { /* 3665 */ + 332, + /* VCVTPD2DQZ128rrkz */ + }, + { /* 3666 */ + 428, + /* VCVTPD2DQZ256rm */ + }, + { /* 3667 */ + 327, + /* VCVTPD2DQZ256rmb */ + }, + { /* 3668 */ + 328, + /* VCVTPD2DQZ256rmbk */ + }, + { /* 3669 */ + 329, + /* VCVTPD2DQZ256rmbkz */ + }, + { /* 3670 */ + 429, + /* VCVTPD2DQZ256rmk */ + }, + { /* 3671 */ + 430, + /* VCVTPD2DQZ256rmkz */ + }, + { /* 3672 */ + 431, + /* VCVTPD2DQZ256rr */ + }, + { /* 3673 */ + 432, + /* VCVTPD2DQZ256rrk */ + }, + { /* 3674 */ + 433, + /* VCVTPD2DQZ256rrkz */ + }, + { /* 3675 */ + 434, + /* VCVTPD2DQZrm */ + }, + { /* 3676 */ + 306, + /* VCVTPD2DQZrmb */ + }, + { /* 3677 */ + 307, + /* VCVTPD2DQZrmbk */ + }, + { /* 3678 */ + 308, + /* VCVTPD2DQZrmbkz */ + }, + { /* 3679 */ + 435, + /* VCVTPD2DQZrmk */ + }, + { /* 3680 */ + 436, + /* VCVTPD2DQZrmkz */ + }, + { /* 3681 */ + 437, + /* VCVTPD2DQZrr */ + }, + { /* 3682 */ + 438, + /* VCVTPD2DQZrrb */ + }, + { /* 3683 */ + 439, + /* VCVTPD2DQZrrbk */ + }, + { /* 3684 */ + 440, + /* VCVTPD2DQZrrbkz */ + }, + { /* 3685 */ + 441, + /* VCVTPD2DQZrrk */ + }, + { /* 3686 */ + 442, + /* VCVTPD2DQZrrkz */ + }, + { /* 3687 */ + 30, + /* VCVTPD2DQrm */ + }, + { /* 3688 */ + 31, + /* VCVTPD2DQrr */ + }, + { /* 3689 */ + 30, + /* VCVTPD2PSYrm */ + }, + { /* 3690 */ + 427, + /* VCVTPD2PSYrr */ + }, + { /* 3691 */ + 409, + /* VCVTPD2PSZ128rm */ + }, + { /* 3692 */ + 327, + /* VCVTPD2PSZ128rmb */ + }, + { /* 3693 */ + 328, + /* VCVTPD2PSZ128rmbk */ + }, + { /* 3694 */ + 329, + /* VCVTPD2PSZ128rmbkz */ + }, + { /* 3695 */ + 410, + /* VCVTPD2PSZ128rmk */ + }, + { /* 3696 */ + 411, + /* VCVTPD2PSZ128rmkz */ + }, + { /* 3697 */ + 330, + /* VCVTPD2PSZ128rr */ + }, + { /* 3698 */ + 331, + /* VCVTPD2PSZ128rrk */ + }, + { /* 3699 */ + 332, + /* VCVTPD2PSZ128rrkz */ + }, + { /* 3700 */ + 428, + /* VCVTPD2PSZ256rm */ + }, + { /* 3701 */ + 327, + /* VCVTPD2PSZ256rmb */ + }, + { /* 3702 */ + 328, + /* VCVTPD2PSZ256rmbk */ + }, + { /* 3703 */ + 329, + /* VCVTPD2PSZ256rmbkz */ + }, + { /* 3704 */ + 429, + /* VCVTPD2PSZ256rmk */ + }, + { /* 3705 */ + 430, + /* VCVTPD2PSZ256rmkz */ + }, + { /* 3706 */ + 431, + /* VCVTPD2PSZ256rr */ + }, + { /* 3707 */ + 432, + /* VCVTPD2PSZ256rrk */ + }, + { /* 3708 */ + 433, + /* VCVTPD2PSZ256rrkz */ + }, + { /* 3709 */ + 434, + /* VCVTPD2PSZrm */ + }, + { /* 3710 */ + 306, + /* VCVTPD2PSZrmb */ + }, + { /* 3711 */ + 307, + /* VCVTPD2PSZrmbk */ + }, + { /* 3712 */ + 308, + /* VCVTPD2PSZrmbkz */ + }, + { /* 3713 */ + 435, + /* VCVTPD2PSZrmk */ + }, + { /* 3714 */ + 436, + /* VCVTPD2PSZrmkz */ + }, + { /* 3715 */ + 437, + /* VCVTPD2PSZrr */ + }, + { /* 3716 */ + 438, + /* VCVTPD2PSZrrb */ + }, + { /* 3717 */ + 439, + /* VCVTPD2PSZrrbk */ + }, + { /* 3718 */ + 440, + /* VCVTPD2PSZrrbkz */ + }, + { /* 3719 */ + 441, + /* VCVTPD2PSZrrk */ + }, + { /* 3720 */ + 442, + /* VCVTPD2PSZrrkz */ + }, + { /* 3721 */ + 30, + /* VCVTPD2PSrm */ + }, + { /* 3722 */ + 31, + /* VCVTPD2PSrr */ + }, + { /* 3723 */ + 409, + /* VCVTPD2QQZ128rm */ + }, + { /* 3724 */ + 327, + /* VCVTPD2QQZ128rmb */ + }, + { /* 3725 */ + 328, + /* VCVTPD2QQZ128rmbk */ + }, + { /* 3726 */ + 329, + /* VCVTPD2QQZ128rmbkz */ + }, + { /* 3727 */ + 410, + /* VCVTPD2QQZ128rmk */ + }, + { /* 3728 */ + 411, + /* VCVTPD2QQZ128rmkz */ + }, + { /* 3729 */ + 330, + /* VCVTPD2QQZ128rr */ + }, + { /* 3730 */ + 331, + /* VCVTPD2QQZ128rrk */ + }, + { /* 3731 */ + 332, + /* VCVTPD2QQZ128rrkz */ + }, + { /* 3732 */ + 412, + /* VCVTPD2QQZ256rm */ + }, + { /* 3733 */ + 306, + /* VCVTPD2QQZ256rmb */ + }, + { /* 3734 */ + 307, + /* VCVTPD2QQZ256rmbk */ + }, + { /* 3735 */ + 308, + /* VCVTPD2QQZ256rmbkz */ + }, + { /* 3736 */ + 413, + /* VCVTPD2QQZ256rmk */ + }, + { /* 3737 */ + 414, + /* VCVTPD2QQZ256rmkz */ + }, + { /* 3738 */ + 415, + /* VCVTPD2QQZ256rr */ + }, + { /* 3739 */ + 416, + /* VCVTPD2QQZ256rrk */ + }, + { /* 3740 */ + 417, + /* VCVTPD2QQZ256rrkz */ + }, + { /* 3741 */ + 418, + /* VCVTPD2QQZrm */ + }, + { /* 3742 */ + 312, + /* VCVTPD2QQZrmb */ + }, + { /* 3743 */ + 313, + /* VCVTPD2QQZrmbk */ + }, + { /* 3744 */ + 314, + /* VCVTPD2QQZrmbkz */ + }, + { /* 3745 */ + 419, + /* VCVTPD2QQZrmk */ + }, + { /* 3746 */ + 420, + /* VCVTPD2QQZrmkz */ + }, + { /* 3747 */ + 421, + /* VCVTPD2QQZrr */ + }, + { /* 3748 */ + 443, + /* VCVTPD2QQZrrb */ + }, + { /* 3749 */ + 444, + /* VCVTPD2QQZrrbk */ + }, + { /* 3750 */ + 445, + /* VCVTPD2QQZrrbkz */ + }, + { /* 3751 */ + 425, + /* VCVTPD2QQZrrk */ + }, + { /* 3752 */ + 426, + /* VCVTPD2QQZrrkz */ + }, + { /* 3753 */ + 409, + /* VCVTPD2UDQZ128rm */ + }, + { /* 3754 */ + 327, + /* VCVTPD2UDQZ128rmb */ + }, + { /* 3755 */ + 328, + /* VCVTPD2UDQZ128rmbk */ + }, + { /* 3756 */ + 329, + /* VCVTPD2UDQZ128rmbkz */ + }, + { /* 3757 */ + 410, + /* VCVTPD2UDQZ128rmk */ + }, + { /* 3758 */ + 411, + /* VCVTPD2UDQZ128rmkz */ + }, + { /* 3759 */ + 330, + /* VCVTPD2UDQZ128rr */ + }, + { /* 3760 */ + 331, + /* VCVTPD2UDQZ128rrk */ + }, + { /* 3761 */ + 332, + /* VCVTPD2UDQZ128rrkz */ + }, + { /* 3762 */ + 428, + /* VCVTPD2UDQZ256rm */ + }, + { /* 3763 */ + 327, + /* VCVTPD2UDQZ256rmb */ + }, + { /* 3764 */ + 328, + /* VCVTPD2UDQZ256rmbk */ + }, + { /* 3765 */ + 329, + /* VCVTPD2UDQZ256rmbkz */ + }, + { /* 3766 */ + 429, + /* VCVTPD2UDQZ256rmk */ + }, + { /* 3767 */ + 430, + /* VCVTPD2UDQZ256rmkz */ + }, + { /* 3768 */ + 431, + /* VCVTPD2UDQZ256rr */ + }, + { /* 3769 */ + 432, + /* VCVTPD2UDQZ256rrk */ + }, + { /* 3770 */ + 433, + /* VCVTPD2UDQZ256rrkz */ + }, + { /* 3771 */ + 434, + /* VCVTPD2UDQZrm */ + }, + { /* 3772 */ + 306, + /* VCVTPD2UDQZrmb */ + }, + { /* 3773 */ + 307, + /* VCVTPD2UDQZrmbk */ + }, + { /* 3774 */ + 308, + /* VCVTPD2UDQZrmbkz */ + }, + { /* 3775 */ + 435, + /* VCVTPD2UDQZrmk */ + }, + { /* 3776 */ + 436, + /* VCVTPD2UDQZrmkz */ + }, + { /* 3777 */ + 437, + /* VCVTPD2UDQZrr */ + }, + { /* 3778 */ + 438, + /* VCVTPD2UDQZrrb */ + }, + { /* 3779 */ + 439, + /* VCVTPD2UDQZrrbk */ + }, + { /* 3780 */ + 440, + /* VCVTPD2UDQZrrbkz */ + }, + { /* 3781 */ + 441, + /* VCVTPD2UDQZrrk */ + }, + { /* 3782 */ + 442, + /* VCVTPD2UDQZrrkz */ + }, + { /* 3783 */ + 409, + /* VCVTPD2UQQZ128rm */ + }, + { /* 3784 */ + 327, + /* VCVTPD2UQQZ128rmb */ + }, + { /* 3785 */ + 328, + /* VCVTPD2UQQZ128rmbk */ + }, + { /* 3786 */ + 329, + /* VCVTPD2UQQZ128rmbkz */ + }, + { /* 3787 */ + 410, + /* VCVTPD2UQQZ128rmk */ + }, + { /* 3788 */ + 411, + /* VCVTPD2UQQZ128rmkz */ + }, + { /* 3789 */ + 330, + /* VCVTPD2UQQZ128rr */ + }, + { /* 3790 */ + 331, + /* VCVTPD2UQQZ128rrk */ + }, + { /* 3791 */ + 332, + /* VCVTPD2UQQZ128rrkz */ + }, + { /* 3792 */ + 412, + /* VCVTPD2UQQZ256rm */ + }, + { /* 3793 */ + 306, + /* VCVTPD2UQQZ256rmb */ + }, + { /* 3794 */ + 307, + /* VCVTPD2UQQZ256rmbk */ + }, + { /* 3795 */ + 308, + /* VCVTPD2UQQZ256rmbkz */ + }, + { /* 3796 */ + 413, + /* VCVTPD2UQQZ256rmk */ + }, + { /* 3797 */ + 414, + /* VCVTPD2UQQZ256rmkz */ + }, + { /* 3798 */ + 415, + /* VCVTPD2UQQZ256rr */ + }, + { /* 3799 */ + 416, + /* VCVTPD2UQQZ256rrk */ + }, + { /* 3800 */ + 417, + /* VCVTPD2UQQZ256rrkz */ + }, + { /* 3801 */ + 418, + /* VCVTPD2UQQZrm */ + }, + { /* 3802 */ + 312, + /* VCVTPD2UQQZrmb */ + }, + { /* 3803 */ + 313, + /* VCVTPD2UQQZrmbk */ + }, + { /* 3804 */ + 314, + /* VCVTPD2UQQZrmbkz */ + }, + { /* 3805 */ + 419, + /* VCVTPD2UQQZrmk */ + }, + { /* 3806 */ + 420, + /* VCVTPD2UQQZrmkz */ + }, + { /* 3807 */ + 421, + /* VCVTPD2UQQZrr */ + }, + { /* 3808 */ + 443, + /* VCVTPD2UQQZrrb */ + }, + { /* 3809 */ + 444, + /* VCVTPD2UQQZrrbk */ + }, + { /* 3810 */ + 445, + /* VCVTPD2UQQZrrbkz */ + }, + { /* 3811 */ + 425, + /* VCVTPD2UQQZrrk */ + }, + { /* 3812 */ + 426, + /* VCVTPD2UQQZrrkz */ + }, + { /* 3813 */ + 305, + /* VCVTPH2PSYrm */ + }, + { /* 3814 */ + 333, + /* VCVTPH2PSYrr */ + }, + { /* 3815 */ + 327, + /* VCVTPH2PSZ128rm */ + }, + { /* 3816 */ + 328, + /* VCVTPH2PSZ128rmk */ + }, + { /* 3817 */ + 329, + /* VCVTPH2PSZ128rmkz */ + }, + { /* 3818 */ + 377, + /* VCVTPH2PSZ128rr */ + }, + { /* 3819 */ + 400, + /* VCVTPH2PSZ128rrk */ + }, + { /* 3820 */ + 401, + /* VCVTPH2PSZ128rrkz */ + }, + { /* 3821 */ + 318, + /* VCVTPH2PSZ256rm */ + }, + { /* 3822 */ + 319, + /* VCVTPH2PSZ256rmk */ + }, + { /* 3823 */ + 320, + /* VCVTPH2PSZ256rmkz */ + }, + { /* 3824 */ + 402, + /* VCVTPH2PSZ256rr */ + }, + { /* 3825 */ + 403, + /* VCVTPH2PSZ256rrk */ + }, + { /* 3826 */ + 404, + /* VCVTPH2PSZ256rrkz */ + }, + { /* 3827 */ + 324, + /* VCVTPH2PSZrm */ + }, + { /* 3828 */ + 325, + /* VCVTPH2PSZrmk */ + }, + { /* 3829 */ + 326, + /* VCVTPH2PSZrmkz */ + }, + { /* 3830 */ + 405, + /* VCVTPH2PSZrr */ + }, + { /* 3831 */ + 446, + /* VCVTPH2PSZrrb */ + }, + { /* 3832 */ + 447, + /* VCVTPH2PSZrrbk */ + }, + { /* 3833 */ + 448, + /* VCVTPH2PSZrrbkz */ + }, + { /* 3834 */ + 406, + /* VCVTPH2PSZrrk */ + }, + { /* 3835 */ + 407, + /* VCVTPH2PSZrrkz */ + }, + { /* 3836 */ + 30, + /* VCVTPH2PSrm */ + }, + { /* 3837 */ + 31, + /* VCVTPH2PSrr */ + }, + { /* 3838 */ + 305, + /* VCVTPS2DQYrm */ + }, + { /* 3839 */ + 408, + /* VCVTPS2DQYrr */ + }, + { /* 3840 */ + 409, + /* VCVTPS2DQZ128rm */ + }, + { /* 3841 */ + 334, + /* VCVTPS2DQZ128rmb */ + }, + { /* 3842 */ + 335, + /* VCVTPS2DQZ128rmbk */ + }, + { /* 3843 */ + 336, + /* VCVTPS2DQZ128rmbkz */ + }, + { /* 3844 */ + 410, + /* VCVTPS2DQZ128rmk */ + }, + { /* 3845 */ + 411, + /* VCVTPS2DQZ128rmkz */ + }, + { /* 3846 */ + 330, + /* VCVTPS2DQZ128rr */ + }, + { /* 3847 */ + 331, + /* VCVTPS2DQZ128rrk */ + }, + { /* 3848 */ + 332, + /* VCVTPS2DQZ128rrkz */ + }, + { /* 3849 */ + 412, + /* VCVTPS2DQZ256rm */ + }, + { /* 3850 */ + 337, + /* VCVTPS2DQZ256rmb */ + }, + { /* 3851 */ + 338, + /* VCVTPS2DQZ256rmbk */ + }, + { /* 3852 */ + 339, + /* VCVTPS2DQZ256rmbkz */ + }, + { /* 3853 */ + 413, + /* VCVTPS2DQZ256rmk */ + }, + { /* 3854 */ + 414, + /* VCVTPS2DQZ256rmkz */ + }, + { /* 3855 */ + 415, + /* VCVTPS2DQZ256rr */ + }, + { /* 3856 */ + 416, + /* VCVTPS2DQZ256rrk */ + }, + { /* 3857 */ + 417, + /* VCVTPS2DQZ256rrkz */ + }, + { /* 3858 */ + 418, + /* VCVTPS2DQZrm */ + }, + { /* 3859 */ + 340, + /* VCVTPS2DQZrmb */ + }, + { /* 3860 */ + 341, + /* VCVTPS2DQZrmbk */ + }, + { /* 3861 */ + 342, + /* VCVTPS2DQZrmbkz */ + }, + { /* 3862 */ + 419, + /* VCVTPS2DQZrmk */ + }, + { /* 3863 */ + 420, + /* VCVTPS2DQZrmkz */ + }, + { /* 3864 */ + 421, + /* VCVTPS2DQZrr */ + }, + { /* 3865 */ + 422, + /* VCVTPS2DQZrrb */ + }, + { /* 3866 */ + 423, + /* VCVTPS2DQZrrbk */ + }, + { /* 3867 */ + 424, + /* VCVTPS2DQZrrbkz */ + }, + { /* 3868 */ + 425, + /* VCVTPS2DQZrrk */ + }, + { /* 3869 */ + 426, + /* VCVTPS2DQZrrkz */ + }, + { /* 3870 */ + 30, + /* VCVTPS2DQrm */ + }, + { /* 3871 */ + 31, + /* VCVTPS2DQrr */ + }, + { /* 3872 */ + 305, + /* VCVTPS2PDYrm */ + }, + { /* 3873 */ + 333, + /* VCVTPS2PDYrr */ + }, + { /* 3874 */ + 327, + /* VCVTPS2PDZ128rm */ + }, + { /* 3875 */ + 334, + /* VCVTPS2PDZ128rmb */ + }, + { /* 3876 */ + 335, + /* VCVTPS2PDZ128rmbk */ + }, + { /* 3877 */ + 336, + /* VCVTPS2PDZ128rmbkz */ + }, + { /* 3878 */ + 328, + /* VCVTPS2PDZ128rmk */ + }, + { /* 3879 */ + 329, + /* VCVTPS2PDZ128rmkz */ + }, + { /* 3880 */ + 377, + /* VCVTPS2PDZ128rr */ + }, + { /* 3881 */ + 400, + /* VCVTPS2PDZ128rrk */ + }, + { /* 3882 */ + 401, + /* VCVTPS2PDZ128rrkz */ + }, + { /* 3883 */ + 318, + /* VCVTPS2PDZ256rm */ + }, + { /* 3884 */ + 337, + /* VCVTPS2PDZ256rmb */ + }, + { /* 3885 */ + 338, + /* VCVTPS2PDZ256rmbk */ + }, + { /* 3886 */ + 339, + /* VCVTPS2PDZ256rmbkz */ + }, + { /* 3887 */ + 319, + /* VCVTPS2PDZ256rmk */ + }, + { /* 3888 */ + 320, + /* VCVTPS2PDZ256rmkz */ + }, + { /* 3889 */ + 402, + /* VCVTPS2PDZ256rr */ + }, + { /* 3890 */ + 403, + /* VCVTPS2PDZ256rrk */ + }, + { /* 3891 */ + 404, + /* VCVTPS2PDZ256rrkz */ + }, + { /* 3892 */ + 324, + /* VCVTPS2PDZrm */ + }, + { /* 3893 */ + 340, + /* VCVTPS2PDZrmb */ + }, + { /* 3894 */ + 341, + /* VCVTPS2PDZrmbk */ + }, + { /* 3895 */ + 342, + /* VCVTPS2PDZrmbkz */ + }, + { /* 3896 */ + 325, + /* VCVTPS2PDZrmk */ + }, + { /* 3897 */ + 326, + /* VCVTPS2PDZrmkz */ + }, + { /* 3898 */ + 405, + /* VCVTPS2PDZrr */ + }, + { /* 3899 */ + 446, + /* VCVTPS2PDZrrb */ + }, + { /* 3900 */ + 447, + /* VCVTPS2PDZrrbk */ + }, + { /* 3901 */ + 448, + /* VCVTPS2PDZrrbkz */ + }, + { /* 3902 */ + 406, + /* VCVTPS2PDZrrk */ + }, + { /* 3903 */ + 407, + /* VCVTPS2PDZrrkz */ + }, + { /* 3904 */ + 30, + /* VCVTPS2PDrm */ + }, + { /* 3905 */ + 31, + /* VCVTPS2PDrr */ + }, + { /* 3906 */ + 449, + /* VCVTPS2PHYmr */ + }, + { /* 3907 */ + 450, + /* VCVTPS2PHYrr */ + }, + { /* 3908 */ + 451, + /* VCVTPS2PHZ128mr */ + }, + { /* 3909 */ + 452, + /* VCVTPS2PHZ128mrk */ + }, + { /* 3910 */ + 453, + /* VCVTPS2PHZ128rr */ + }, + { /* 3911 */ + 454, + /* VCVTPS2PHZ128rrk */ + }, + { /* 3912 */ + 455, + /* VCVTPS2PHZ128rrkz */ + }, + { /* 3913 */ + 456, + /* VCVTPS2PHZ256mr */ + }, + { /* 3914 */ + 457, + /* VCVTPS2PHZ256mrk */ + }, + { /* 3915 */ + 458, + /* VCVTPS2PHZ256rr */ + }, + { /* 3916 */ + 459, + /* VCVTPS2PHZ256rrk */ + }, + { /* 3917 */ + 460, + /* VCVTPS2PHZ256rrkz */ + }, + { /* 3918 */ + 461, + /* VCVTPS2PHZmr */ + }, + { /* 3919 */ + 462, + /* VCVTPS2PHZmrk */ + }, + { /* 3920 */ + 463, + /* VCVTPS2PHZrr */ + }, + { /* 3921 */ + 464, + /* VCVTPS2PHZrrb */ + }, + { /* 3922 */ + 465, + /* VCVTPS2PHZrrbk */ + }, + { /* 3923 */ + 466, + /* VCVTPS2PHZrrbkz */ + }, + { /* 3924 */ + 467, + /* VCVTPS2PHZrrk */ + }, + { /* 3925 */ + 468, + /* VCVTPS2PHZrrkz */ + }, + { /* 3926 */ + 96, + /* VCVTPS2PHmr */ + }, + { /* 3927 */ + 469, + /* VCVTPS2PHrr */ + }, + { /* 3928 */ + 327, + /* VCVTPS2QQZ128rm */ + }, + { /* 3929 */ + 334, + /* VCVTPS2QQZ128rmb */ + }, + { /* 3930 */ + 335, + /* VCVTPS2QQZ128rmbk */ + }, + { /* 3931 */ + 336, + /* VCVTPS2QQZ128rmbkz */ + }, + { /* 3932 */ + 328, + /* VCVTPS2QQZ128rmk */ + }, + { /* 3933 */ + 329, + /* VCVTPS2QQZ128rmkz */ + }, + { /* 3934 */ + 377, + /* VCVTPS2QQZ128rr */ + }, + { /* 3935 */ + 400, + /* VCVTPS2QQZ128rrk */ + }, + { /* 3936 */ + 401, + /* VCVTPS2QQZ128rrkz */ + }, + { /* 3937 */ + 318, + /* VCVTPS2QQZ256rm */ + }, + { /* 3938 */ + 337, + /* VCVTPS2QQZ256rmb */ + }, + { /* 3939 */ + 338, + /* VCVTPS2QQZ256rmbk */ + }, + { /* 3940 */ + 339, + /* VCVTPS2QQZ256rmbkz */ + }, + { /* 3941 */ + 319, + /* VCVTPS2QQZ256rmk */ + }, + { /* 3942 */ + 320, + /* VCVTPS2QQZ256rmkz */ + }, + { /* 3943 */ + 402, + /* VCVTPS2QQZ256rr */ + }, + { /* 3944 */ + 403, + /* VCVTPS2QQZ256rrk */ + }, + { /* 3945 */ + 404, + /* VCVTPS2QQZ256rrkz */ + }, + { /* 3946 */ + 324, + /* VCVTPS2QQZrm */ + }, + { /* 3947 */ + 340, + /* VCVTPS2QQZrmb */ + }, + { /* 3948 */ + 341, + /* VCVTPS2QQZrmbk */ + }, + { /* 3949 */ + 342, + /* VCVTPS2QQZrmbkz */ + }, + { /* 3950 */ + 325, + /* VCVTPS2QQZrmk */ + }, + { /* 3951 */ + 326, + /* VCVTPS2QQZrmkz */ + }, + { /* 3952 */ + 405, + /* VCVTPS2QQZrr */ + }, + { /* 3953 */ + 470, + /* VCVTPS2QQZrrb */ + }, + { /* 3954 */ + 471, + /* VCVTPS2QQZrrbk */ + }, + { /* 3955 */ + 472, + /* VCVTPS2QQZrrbkz */ + }, + { /* 3956 */ + 406, + /* VCVTPS2QQZrrk */ + }, + { /* 3957 */ + 407, + /* VCVTPS2QQZrrkz */ + }, + { /* 3958 */ + 409, + /* VCVTPS2UDQZ128rm */ + }, + { /* 3959 */ + 334, + /* VCVTPS2UDQZ128rmb */ + }, + { /* 3960 */ + 335, + /* VCVTPS2UDQZ128rmbk */ + }, + { /* 3961 */ + 336, + /* VCVTPS2UDQZ128rmbkz */ + }, + { /* 3962 */ + 410, + /* VCVTPS2UDQZ128rmk */ + }, + { /* 3963 */ + 411, + /* VCVTPS2UDQZ128rmkz */ + }, + { /* 3964 */ + 330, + /* VCVTPS2UDQZ128rr */ + }, + { /* 3965 */ + 331, + /* VCVTPS2UDQZ128rrk */ + }, + { /* 3966 */ + 332, + /* VCVTPS2UDQZ128rrkz */ + }, + { /* 3967 */ + 412, + /* VCVTPS2UDQZ256rm */ + }, + { /* 3968 */ + 337, + /* VCVTPS2UDQZ256rmb */ + }, + { /* 3969 */ + 338, + /* VCVTPS2UDQZ256rmbk */ + }, + { /* 3970 */ + 339, + /* VCVTPS2UDQZ256rmbkz */ + }, + { /* 3971 */ + 413, + /* VCVTPS2UDQZ256rmk */ + }, + { /* 3972 */ + 414, + /* VCVTPS2UDQZ256rmkz */ + }, + { /* 3973 */ + 415, + /* VCVTPS2UDQZ256rr */ + }, + { /* 3974 */ + 416, + /* VCVTPS2UDQZ256rrk */ + }, + { /* 3975 */ + 417, + /* VCVTPS2UDQZ256rrkz */ + }, + { /* 3976 */ + 418, + /* VCVTPS2UDQZrm */ + }, + { /* 3977 */ + 340, + /* VCVTPS2UDQZrmb */ + }, + { /* 3978 */ + 341, + /* VCVTPS2UDQZrmbk */ + }, + { /* 3979 */ + 342, + /* VCVTPS2UDQZrmbkz */ + }, + { /* 3980 */ + 419, + /* VCVTPS2UDQZrmk */ + }, + { /* 3981 */ + 420, + /* VCVTPS2UDQZrmkz */ + }, + { /* 3982 */ + 421, + /* VCVTPS2UDQZrr */ + }, + { /* 3983 */ + 422, + /* VCVTPS2UDQZrrb */ + }, + { /* 3984 */ + 423, + /* VCVTPS2UDQZrrbk */ + }, + { /* 3985 */ + 424, + /* VCVTPS2UDQZrrbkz */ + }, + { /* 3986 */ + 425, + /* VCVTPS2UDQZrrk */ + }, + { /* 3987 */ + 426, + /* VCVTPS2UDQZrrkz */ + }, + { /* 3988 */ + 327, + /* VCVTPS2UQQZ128rm */ + }, + { /* 3989 */ + 334, + /* VCVTPS2UQQZ128rmb */ + }, + { /* 3990 */ + 335, + /* VCVTPS2UQQZ128rmbk */ + }, + { /* 3991 */ + 336, + /* VCVTPS2UQQZ128rmbkz */ + }, + { /* 3992 */ + 328, + /* VCVTPS2UQQZ128rmk */ + }, + { /* 3993 */ + 329, + /* VCVTPS2UQQZ128rmkz */ + }, + { /* 3994 */ + 377, + /* VCVTPS2UQQZ128rr */ + }, + { /* 3995 */ + 400, + /* VCVTPS2UQQZ128rrk */ + }, + { /* 3996 */ + 401, + /* VCVTPS2UQQZ128rrkz */ + }, + { /* 3997 */ + 318, + /* VCVTPS2UQQZ256rm */ + }, + { /* 3998 */ + 337, + /* VCVTPS2UQQZ256rmb */ + }, + { /* 3999 */ + 338, + /* VCVTPS2UQQZ256rmbk */ + }, + { /* 4000 */ + 339, + /* VCVTPS2UQQZ256rmbkz */ + }, + { /* 4001 */ + 319, + /* VCVTPS2UQQZ256rmk */ + }, + { /* 4002 */ + 320, + /* VCVTPS2UQQZ256rmkz */ + }, + { /* 4003 */ + 402, + /* VCVTPS2UQQZ256rr */ + }, + { /* 4004 */ + 403, + /* VCVTPS2UQQZ256rrk */ + }, + { /* 4005 */ + 404, + /* VCVTPS2UQQZ256rrkz */ + }, + { /* 4006 */ + 324, + /* VCVTPS2UQQZrm */ + }, + { /* 4007 */ + 340, + /* VCVTPS2UQQZrmb */ + }, + { /* 4008 */ + 341, + /* VCVTPS2UQQZrmbk */ + }, + { /* 4009 */ + 342, + /* VCVTPS2UQQZrmbkz */ + }, + { /* 4010 */ + 325, + /* VCVTPS2UQQZrmk */ + }, + { /* 4011 */ + 326, + /* VCVTPS2UQQZrmkz */ + }, + { /* 4012 */ + 405, + /* VCVTPS2UQQZrr */ + }, + { /* 4013 */ + 470, + /* VCVTPS2UQQZrrb */ + }, + { /* 4014 */ + 471, + /* VCVTPS2UQQZrrbk */ + }, + { /* 4015 */ + 472, + /* VCVTPS2UQQZrrbkz */ + }, + { /* 4016 */ + 406, + /* VCVTPS2UQQZrrk */ + }, + { /* 4017 */ + 407, + /* VCVTPS2UQQZrrkz */ + }, + { /* 4018 */ + 409, + /* VCVTQQ2PDZ128rm */ + }, + { /* 4019 */ + 327, + /* VCVTQQ2PDZ128rmb */ + }, + { /* 4020 */ + 328, + /* VCVTQQ2PDZ128rmbk */ + }, + { /* 4021 */ + 329, + /* VCVTQQ2PDZ128rmbkz */ + }, + { /* 4022 */ + 410, + /* VCVTQQ2PDZ128rmk */ + }, + { /* 4023 */ + 411, + /* VCVTQQ2PDZ128rmkz */ + }, + { /* 4024 */ + 330, + /* VCVTQQ2PDZ128rr */ + }, + { /* 4025 */ + 331, + /* VCVTQQ2PDZ128rrk */ + }, + { /* 4026 */ + 332, + /* VCVTQQ2PDZ128rrkz */ + }, + { /* 4027 */ + 412, + /* VCVTQQ2PDZ256rm */ + }, + { /* 4028 */ + 306, + /* VCVTQQ2PDZ256rmb */ + }, + { /* 4029 */ + 307, + /* VCVTQQ2PDZ256rmbk */ + }, + { /* 4030 */ + 308, + /* VCVTQQ2PDZ256rmbkz */ + }, + { /* 4031 */ + 413, + /* VCVTQQ2PDZ256rmk */ + }, + { /* 4032 */ + 414, + /* VCVTQQ2PDZ256rmkz */ + }, + { /* 4033 */ + 415, + /* VCVTQQ2PDZ256rr */ + }, + { /* 4034 */ + 416, + /* VCVTQQ2PDZ256rrk */ + }, + { /* 4035 */ + 417, + /* VCVTQQ2PDZ256rrkz */ + }, + { /* 4036 */ + 418, + /* VCVTQQ2PDZrm */ + }, + { /* 4037 */ + 312, + /* VCVTQQ2PDZrmb */ + }, + { /* 4038 */ + 313, + /* VCVTQQ2PDZrmbk */ + }, + { /* 4039 */ + 314, + /* VCVTQQ2PDZrmbkz */ + }, + { /* 4040 */ + 419, + /* VCVTQQ2PDZrmk */ + }, + { /* 4041 */ + 420, + /* VCVTQQ2PDZrmkz */ + }, + { /* 4042 */ + 421, + /* VCVTQQ2PDZrr */ + }, + { /* 4043 */ + 443, + /* VCVTQQ2PDZrrb */ + }, + { /* 4044 */ + 444, + /* VCVTQQ2PDZrrbk */ + }, + { /* 4045 */ + 445, + /* VCVTQQ2PDZrrbkz */ + }, + { /* 4046 */ + 425, + /* VCVTQQ2PDZrrk */ + }, + { /* 4047 */ + 426, + /* VCVTQQ2PDZrrkz */ + }, + { /* 4048 */ + 409, + /* VCVTQQ2PSZ128rm */ + }, + { /* 4049 */ + 327, + /* VCVTQQ2PSZ128rmb */ + }, + { /* 4050 */ + 328, + /* VCVTQQ2PSZ128rmbk */ + }, + { /* 4051 */ + 329, + /* VCVTQQ2PSZ128rmbkz */ + }, + { /* 4052 */ + 410, + /* VCVTQQ2PSZ128rmk */ + }, + { /* 4053 */ + 411, + /* VCVTQQ2PSZ128rmkz */ + }, + { /* 4054 */ + 330, + /* VCVTQQ2PSZ128rr */ + }, + { /* 4055 */ + 331, + /* VCVTQQ2PSZ128rrk */ + }, + { /* 4056 */ + 332, + /* VCVTQQ2PSZ128rrkz */ + }, + { /* 4057 */ + 428, + /* VCVTQQ2PSZ256rm */ + }, + { /* 4058 */ + 327, + /* VCVTQQ2PSZ256rmb */ + }, + { /* 4059 */ + 328, + /* VCVTQQ2PSZ256rmbk */ + }, + { /* 4060 */ + 329, + /* VCVTQQ2PSZ256rmbkz */ + }, + { /* 4061 */ + 429, + /* VCVTQQ2PSZ256rmk */ + }, + { /* 4062 */ + 430, + /* VCVTQQ2PSZ256rmkz */ + }, + { /* 4063 */ + 431, + /* VCVTQQ2PSZ256rr */ + }, + { /* 4064 */ + 432, + /* VCVTQQ2PSZ256rrk */ + }, + { /* 4065 */ + 433, + /* VCVTQQ2PSZ256rrkz */ + }, + { /* 4066 */ + 434, + /* VCVTQQ2PSZrm */ + }, + { /* 4067 */ + 306, + /* VCVTQQ2PSZrmb */ + }, + { /* 4068 */ + 307, + /* VCVTQQ2PSZrmbk */ + }, + { /* 4069 */ + 308, + /* VCVTQQ2PSZrmbkz */ + }, + { /* 4070 */ + 435, + /* VCVTQQ2PSZrmk */ + }, + { /* 4071 */ + 436, + /* VCVTQQ2PSZrmkz */ + }, + { /* 4072 */ + 437, + /* VCVTQQ2PSZrr */ + }, + { /* 4073 */ + 438, + /* VCVTQQ2PSZrrb */ + }, + { /* 4074 */ + 439, + /* VCVTQQ2PSZrrbk */ + }, + { /* 4075 */ + 440, + /* VCVTQQ2PSZrrbkz */ + }, + { /* 4076 */ + 441, + /* VCVTQQ2PSZrrk */ + }, + { /* 4077 */ + 442, + /* VCVTQQ2PSZrrkz */ + }, + { /* 4078 */ + 473, + /* VCVTSD2SI64Zrm_Int */ + }, + { /* 4079 */ + 474, + /* VCVTSD2SI64Zrr_Int */ + }, + { /* 4080 */ + 475, + /* VCVTSD2SI64Zrrb_Int */ + }, + { /* 4081 */ + 62, + /* VCVTSD2SI64rm_Int */ + }, + { /* 4082 */ + 86, + /* VCVTSD2SI64rr_Int */ + }, + { /* 4083 */ + 476, + /* VCVTSD2SIZrm_Int */ + }, + { /* 4084 */ + 477, + /* VCVTSD2SIZrr_Int */ + }, + { /* 4085 */ + 478, + /* VCVTSD2SIZrrb_Int */ + }, + { /* 4086 */ + 87, + /* VCVTSD2SIrm_Int */ + }, + { /* 4087 */ + 88, + /* VCVTSD2SIrr_Int */ + }, + { /* 4088 */ + 0, + /* */ + }, + { /* 4089 */ + 207, + /* VCVTSD2SSZrm_Int */ + }, + { /* 4090 */ + 208, + /* VCVTSD2SSZrm_Intk */ + }, + { /* 4091 */ + 209, + /* VCVTSD2SSZrm_Intkz */ + }, + { /* 4092 */ + 0, + /* */ + }, + { /* 4093 */ + 249, + /* VCVTSD2SSZrr_Int */ + }, + { /* 4094 */ + 250, + /* VCVTSD2SSZrr_Intk */ + }, + { /* 4095 */ + 251, + /* VCVTSD2SSZrr_Intkz */ + }, + { /* 4096 */ + 252, + /* VCVTSD2SSZrrb_Int */ + }, + { /* 4097 */ + 253, + /* VCVTSD2SSZrrb_Intk */ + }, + { /* 4098 */ + 254, + /* VCVTSD2SSZrrb_Intkz */ + }, + { /* 4099 */ + 235, + /* VCVTSD2SSrm */ + }, + { /* 4100 */ + 0, + /* */ + }, + { /* 4101 */ + 236, + /* VCVTSD2SSrr */ + }, + { /* 4102 */ + 0, + /* */ + }, + { /* 4103 */ + 473, + /* VCVTSD2USI64Zrm_Int */ + }, + { /* 4104 */ + 474, + /* VCVTSD2USI64Zrr_Int */ + }, + { /* 4105 */ + 475, + /* VCVTSD2USI64Zrrb_Int */ + }, + { /* 4106 */ + 476, + /* VCVTSD2USIZrm_Int */ + }, + { /* 4107 */ + 477, + /* VCVTSD2USIZrr_Int */ + }, + { /* 4108 */ + 478, + /* VCVTSD2USIZrrb_Int */ + }, + { /* 4109 */ + 237, + /* VCVTSI2SDZrm */ + }, + { /* 4110 */ + 0, + /* */ + }, + { /* 4111 */ + 479, + /* VCVTSI2SDZrr */ + }, + { /* 4112 */ + 0, + /* */ + }, + { /* 4113 */ + 480, + /* VCVTSI2SDZrrb_Int */ + }, + { /* 4114 */ + 235, + /* VCVTSI2SDrm */ + }, + { /* 4115 */ + 0, + /* */ + }, + { /* 4116 */ + 481, + /* VCVTSI2SDrr */ + }, + { /* 4117 */ + 0, + /* */ + }, + { /* 4118 */ + 237, + /* VCVTSI2SSZrm */ + }, + { /* 4119 */ + 0, + /* */ + }, + { /* 4120 */ + 479, + /* VCVTSI2SSZrr */ + }, + { /* 4121 */ + 0, + /* */ + }, + { /* 4122 */ + 480, + /* VCVTSI2SSZrrb_Int */ + }, + { /* 4123 */ + 235, + /* VCVTSI2SSrm */ + }, + { /* 4124 */ + 0, + /* */ + }, + { /* 4125 */ + 481, + /* VCVTSI2SSrr */ + }, + { /* 4126 */ + 0, + /* */ + }, + { /* 4127 */ + 207, + /* VCVTSI642SDZrm */ + }, + { /* 4128 */ + 0, + /* */ + }, + { /* 4129 */ + 482, + /* VCVTSI642SDZrr */ + }, + { /* 4130 */ + 0, + /* */ + }, + { /* 4131 */ + 483, + /* VCVTSI642SDZrrb_Int */ + }, + { /* 4132 */ + 235, + /* VCVTSI642SDrm */ + }, + { /* 4133 */ + 0, + /* */ + }, + { /* 4134 */ + 484, + /* VCVTSI642SDrr */ + }, + { /* 4135 */ + 0, + /* */ + }, + { /* 4136 */ + 207, + /* VCVTSI642SSZrm */ + }, + { /* 4137 */ + 0, + /* */ + }, + { /* 4138 */ + 482, + /* VCVTSI642SSZrr */ + }, + { /* 4139 */ + 0, + /* */ + }, + { /* 4140 */ + 483, + /* VCVTSI642SSZrrb_Int */ + }, + { /* 4141 */ + 235, + /* VCVTSI642SSrm */ + }, + { /* 4142 */ + 0, + /* */ + }, + { /* 4143 */ + 484, + /* VCVTSI642SSrr */ + }, + { /* 4144 */ + 0, + /* */ + }, + { /* 4145 */ + 0, + /* */ + }, + { /* 4146 */ + 237, + /* VCVTSS2SDZrm_Int */ + }, + { /* 4147 */ + 238, + /* VCVTSS2SDZrm_Intk */ + }, + { /* 4148 */ + 239, + /* VCVTSS2SDZrm_Intkz */ + }, + { /* 4149 */ + 0, + /* */ + }, + { /* 4150 */ + 255, + /* VCVTSS2SDZrr_Int */ + }, + { /* 4151 */ + 256, + /* VCVTSS2SDZrr_Intk */ + }, + { /* 4152 */ + 257, + /* VCVTSS2SDZrr_Intkz */ + }, + { /* 4153 */ + 255, + /* VCVTSS2SDZrrb_Int */ + }, + { /* 4154 */ + 256, + /* VCVTSS2SDZrrb_Intk */ + }, + { /* 4155 */ + 257, + /* VCVTSS2SDZrrb_Intkz */ + }, + { /* 4156 */ + 235, + /* VCVTSS2SDrm */ + }, + { /* 4157 */ + 0, + /* */ + }, + { /* 4158 */ + 236, + /* VCVTSS2SDrr */ + }, + { /* 4159 */ + 0, + /* */ + }, + { /* 4160 */ + 485, + /* VCVTSS2SI64Zrm_Int */ + }, + { /* 4161 */ + 486, + /* VCVTSS2SI64Zrr_Int */ + }, + { /* 4162 */ + 487, + /* VCVTSS2SI64Zrrb_Int */ + }, + { /* 4163 */ + 62, + /* VCVTSS2SI64rm_Int */ + }, + { /* 4164 */ + 86, + /* VCVTSS2SI64rr_Int */ + }, + { /* 4165 */ + 488, + /* VCVTSS2SIZrm_Int */ + }, + { /* 4166 */ + 489, + /* VCVTSS2SIZrr_Int */ + }, + { /* 4167 */ + 490, + /* VCVTSS2SIZrrb_Int */ + }, + { /* 4168 */ + 87, + /* VCVTSS2SIrm_Int */ + }, + { /* 4169 */ + 88, + /* VCVTSS2SIrr_Int */ + }, + { /* 4170 */ + 485, + /* VCVTSS2USI64Zrm_Int */ + }, + { /* 4171 */ + 486, + /* VCVTSS2USI64Zrr_Int */ + }, + { /* 4172 */ + 487, + /* VCVTSS2USI64Zrrb_Int */ + }, + { /* 4173 */ + 488, + /* VCVTSS2USIZrm_Int */ + }, + { /* 4174 */ + 489, + /* VCVTSS2USIZrr_Int */ + }, + { /* 4175 */ + 490, + /* VCVTSS2USIZrrb_Int */ + }, + { /* 4176 */ + 30, + /* VCVTTPD2DQYrm */ + }, + { /* 4177 */ + 427, + /* VCVTTPD2DQYrr */ + }, + { /* 4178 */ + 409, + /* VCVTTPD2DQZ128rm */ + }, + { /* 4179 */ + 327, + /* VCVTTPD2DQZ128rmb */ + }, + { /* 4180 */ + 328, + /* VCVTTPD2DQZ128rmbk */ + }, + { /* 4181 */ + 329, + /* VCVTTPD2DQZ128rmbkz */ + }, + { /* 4182 */ + 410, + /* VCVTTPD2DQZ128rmk */ + }, + { /* 4183 */ + 411, + /* VCVTTPD2DQZ128rmkz */ + }, + { /* 4184 */ + 330, + /* VCVTTPD2DQZ128rr */ + }, + { /* 4185 */ + 331, + /* VCVTTPD2DQZ128rrk */ + }, + { /* 4186 */ + 332, + /* VCVTTPD2DQZ128rrkz */ + }, + { /* 4187 */ + 428, + /* VCVTTPD2DQZ256rm */ + }, + { /* 4188 */ + 327, + /* VCVTTPD2DQZ256rmb */ + }, + { /* 4189 */ + 328, + /* VCVTTPD2DQZ256rmbk */ + }, + { /* 4190 */ + 329, + /* VCVTTPD2DQZ256rmbkz */ + }, + { /* 4191 */ + 429, + /* VCVTTPD2DQZ256rmk */ + }, + { /* 4192 */ + 430, + /* VCVTTPD2DQZ256rmkz */ + }, + { /* 4193 */ + 431, + /* VCVTTPD2DQZ256rr */ + }, + { /* 4194 */ + 432, + /* VCVTTPD2DQZ256rrk */ + }, + { /* 4195 */ + 433, + /* VCVTTPD2DQZ256rrkz */ + }, + { /* 4196 */ + 434, + /* VCVTTPD2DQZrm */ + }, + { /* 4197 */ + 306, + /* VCVTTPD2DQZrmb */ + }, + { /* 4198 */ + 307, + /* VCVTTPD2DQZrmbk */ + }, + { /* 4199 */ + 308, + /* VCVTTPD2DQZrmbkz */ + }, + { /* 4200 */ + 435, + /* VCVTTPD2DQZrmk */ + }, + { /* 4201 */ + 436, + /* VCVTTPD2DQZrmkz */ + }, + { /* 4202 */ + 437, + /* VCVTTPD2DQZrr */ + }, + { /* 4203 */ + 491, + /* VCVTTPD2DQZrrb */ + }, + { /* 4204 */ + 492, + /* VCVTTPD2DQZrrbk */ + }, + { /* 4205 */ + 493, + /* VCVTTPD2DQZrrbkz */ + }, + { /* 4206 */ + 441, + /* VCVTTPD2DQZrrk */ + }, + { /* 4207 */ + 442, + /* VCVTTPD2DQZrrkz */ + }, + { /* 4208 */ + 30, + /* VCVTTPD2DQrm */ + }, + { /* 4209 */ + 31, + /* VCVTTPD2DQrr */ + }, + { /* 4210 */ + 409, + /* VCVTTPD2QQZ128rm */ + }, + { /* 4211 */ + 327, + /* VCVTTPD2QQZ128rmb */ + }, + { /* 4212 */ + 328, + /* VCVTTPD2QQZ128rmbk */ + }, + { /* 4213 */ + 329, + /* VCVTTPD2QQZ128rmbkz */ + }, + { /* 4214 */ + 410, + /* VCVTTPD2QQZ128rmk */ + }, + { /* 4215 */ + 411, + /* VCVTTPD2QQZ128rmkz */ + }, + { /* 4216 */ + 330, + /* VCVTTPD2QQZ128rr */ + }, + { /* 4217 */ + 331, + /* VCVTTPD2QQZ128rrk */ + }, + { /* 4218 */ + 332, + /* VCVTTPD2QQZ128rrkz */ + }, + { /* 4219 */ + 412, + /* VCVTTPD2QQZ256rm */ + }, + { /* 4220 */ + 306, + /* VCVTTPD2QQZ256rmb */ + }, + { /* 4221 */ + 307, + /* VCVTTPD2QQZ256rmbk */ + }, + { /* 4222 */ + 308, + /* VCVTTPD2QQZ256rmbkz */ + }, + { /* 4223 */ + 413, + /* VCVTTPD2QQZ256rmk */ + }, + { /* 4224 */ + 414, + /* VCVTTPD2QQZ256rmkz */ + }, + { /* 4225 */ + 415, + /* VCVTTPD2QQZ256rr */ + }, + { /* 4226 */ + 416, + /* VCVTTPD2QQZ256rrk */ + }, + { /* 4227 */ + 417, + /* VCVTTPD2QQZ256rrkz */ + }, + { /* 4228 */ + 418, + /* VCVTTPD2QQZrm */ + }, + { /* 4229 */ + 312, + /* VCVTTPD2QQZrmb */ + }, + { /* 4230 */ + 313, + /* VCVTTPD2QQZrmbk */ + }, + { /* 4231 */ + 314, + /* VCVTTPD2QQZrmbkz */ + }, + { /* 4232 */ + 419, + /* VCVTTPD2QQZrmk */ + }, + { /* 4233 */ + 420, + /* VCVTTPD2QQZrmkz */ + }, + { /* 4234 */ + 421, + /* VCVTTPD2QQZrr */ + }, + { /* 4235 */ + 494, + /* VCVTTPD2QQZrrb */ + }, + { /* 4236 */ + 495, + /* VCVTTPD2QQZrrbk */ + }, + { /* 4237 */ + 496, + /* VCVTTPD2QQZrrbkz */ + }, + { /* 4238 */ + 425, + /* VCVTTPD2QQZrrk */ + }, + { /* 4239 */ + 426, + /* VCVTTPD2QQZrrkz */ + }, + { /* 4240 */ + 409, + /* VCVTTPD2UDQZ128rm */ + }, + { /* 4241 */ + 327, + /* VCVTTPD2UDQZ128rmb */ + }, + { /* 4242 */ + 328, + /* VCVTTPD2UDQZ128rmbk */ + }, + { /* 4243 */ + 329, + /* VCVTTPD2UDQZ128rmbkz */ + }, + { /* 4244 */ + 410, + /* VCVTTPD2UDQZ128rmk */ + }, + { /* 4245 */ + 411, + /* VCVTTPD2UDQZ128rmkz */ + }, + { /* 4246 */ + 330, + /* VCVTTPD2UDQZ128rr */ + }, + { /* 4247 */ + 331, + /* VCVTTPD2UDQZ128rrk */ + }, + { /* 4248 */ + 332, + /* VCVTTPD2UDQZ128rrkz */ + }, + { /* 4249 */ + 428, + /* VCVTTPD2UDQZ256rm */ + }, + { /* 4250 */ + 327, + /* VCVTTPD2UDQZ256rmb */ + }, + { /* 4251 */ + 328, + /* VCVTTPD2UDQZ256rmbk */ + }, + { /* 4252 */ + 329, + /* VCVTTPD2UDQZ256rmbkz */ + }, + { /* 4253 */ + 429, + /* VCVTTPD2UDQZ256rmk */ + }, + { /* 4254 */ + 430, + /* VCVTTPD2UDQZ256rmkz */ + }, + { /* 4255 */ + 431, + /* VCVTTPD2UDQZ256rr */ + }, + { /* 4256 */ + 432, + /* VCVTTPD2UDQZ256rrk */ + }, + { /* 4257 */ + 433, + /* VCVTTPD2UDQZ256rrkz */ + }, + { /* 4258 */ + 434, + /* VCVTTPD2UDQZrm */ + }, + { /* 4259 */ + 306, + /* VCVTTPD2UDQZrmb */ + }, + { /* 4260 */ + 307, + /* VCVTTPD2UDQZrmbk */ + }, + { /* 4261 */ + 308, + /* VCVTTPD2UDQZrmbkz */ + }, + { /* 4262 */ + 435, + /* VCVTTPD2UDQZrmk */ + }, + { /* 4263 */ + 436, + /* VCVTTPD2UDQZrmkz */ + }, + { /* 4264 */ + 437, + /* VCVTTPD2UDQZrr */ + }, + { /* 4265 */ + 491, + /* VCVTTPD2UDQZrrb */ + }, + { /* 4266 */ + 492, + /* VCVTTPD2UDQZrrbk */ + }, + { /* 4267 */ + 493, + /* VCVTTPD2UDQZrrbkz */ + }, + { /* 4268 */ + 441, + /* VCVTTPD2UDQZrrk */ + }, + { /* 4269 */ + 442, + /* VCVTTPD2UDQZrrkz */ + }, + { /* 4270 */ + 409, + /* VCVTTPD2UQQZ128rm */ + }, + { /* 4271 */ + 327, + /* VCVTTPD2UQQZ128rmb */ + }, + { /* 4272 */ + 328, + /* VCVTTPD2UQQZ128rmbk */ + }, + { /* 4273 */ + 329, + /* VCVTTPD2UQQZ128rmbkz */ + }, + { /* 4274 */ + 410, + /* VCVTTPD2UQQZ128rmk */ + }, + { /* 4275 */ + 411, + /* VCVTTPD2UQQZ128rmkz */ + }, + { /* 4276 */ + 330, + /* VCVTTPD2UQQZ128rr */ + }, + { /* 4277 */ + 331, + /* VCVTTPD2UQQZ128rrk */ + }, + { /* 4278 */ + 332, + /* VCVTTPD2UQQZ128rrkz */ + }, + { /* 4279 */ + 412, + /* VCVTTPD2UQQZ256rm */ + }, + { /* 4280 */ + 306, + /* VCVTTPD2UQQZ256rmb */ + }, + { /* 4281 */ + 307, + /* VCVTTPD2UQQZ256rmbk */ + }, + { /* 4282 */ + 308, + /* VCVTTPD2UQQZ256rmbkz */ + }, + { /* 4283 */ + 413, + /* VCVTTPD2UQQZ256rmk */ + }, + { /* 4284 */ + 414, + /* VCVTTPD2UQQZ256rmkz */ + }, + { /* 4285 */ + 415, + /* VCVTTPD2UQQZ256rr */ + }, + { /* 4286 */ + 416, + /* VCVTTPD2UQQZ256rrk */ + }, + { /* 4287 */ + 417, + /* VCVTTPD2UQQZ256rrkz */ + }, + { /* 4288 */ + 418, + /* VCVTTPD2UQQZrm */ + }, + { /* 4289 */ + 312, + /* VCVTTPD2UQQZrmb */ + }, + { /* 4290 */ + 313, + /* VCVTTPD2UQQZrmbk */ + }, + { /* 4291 */ + 314, + /* VCVTTPD2UQQZrmbkz */ + }, + { /* 4292 */ + 419, + /* VCVTTPD2UQQZrmk */ + }, + { /* 4293 */ + 420, + /* VCVTTPD2UQQZrmkz */ + }, + { /* 4294 */ + 421, + /* VCVTTPD2UQQZrr */ + }, + { /* 4295 */ + 494, + /* VCVTTPD2UQQZrrb */ + }, + { /* 4296 */ + 495, + /* VCVTTPD2UQQZrrbk */ + }, + { /* 4297 */ + 496, + /* VCVTTPD2UQQZrrbkz */ + }, + { /* 4298 */ + 425, + /* VCVTTPD2UQQZrrk */ + }, + { /* 4299 */ + 426, + /* VCVTTPD2UQQZrrkz */ + }, + { /* 4300 */ + 305, + /* VCVTTPS2DQYrm */ + }, + { /* 4301 */ + 408, + /* VCVTTPS2DQYrr */ + }, + { /* 4302 */ + 409, + /* VCVTTPS2DQZ128rm */ + }, + { /* 4303 */ + 334, + /* VCVTTPS2DQZ128rmb */ + }, + { /* 4304 */ + 335, + /* VCVTTPS2DQZ128rmbk */ + }, + { /* 4305 */ + 336, + /* VCVTTPS2DQZ128rmbkz */ + }, + { /* 4306 */ + 410, + /* VCVTTPS2DQZ128rmk */ + }, + { /* 4307 */ + 411, + /* VCVTTPS2DQZ128rmkz */ + }, + { /* 4308 */ + 330, + /* VCVTTPS2DQZ128rr */ + }, + { /* 4309 */ + 331, + /* VCVTTPS2DQZ128rrk */ + }, + { /* 4310 */ + 332, + /* VCVTTPS2DQZ128rrkz */ + }, + { /* 4311 */ + 412, + /* VCVTTPS2DQZ256rm */ + }, + { /* 4312 */ + 337, + /* VCVTTPS2DQZ256rmb */ + }, + { /* 4313 */ + 338, + /* VCVTTPS2DQZ256rmbk */ + }, + { /* 4314 */ + 339, + /* VCVTTPS2DQZ256rmbkz */ + }, + { /* 4315 */ + 413, + /* VCVTTPS2DQZ256rmk */ + }, + { /* 4316 */ + 414, + /* VCVTTPS2DQZ256rmkz */ + }, + { /* 4317 */ + 415, + /* VCVTTPS2DQZ256rr */ + }, + { /* 4318 */ + 416, + /* VCVTTPS2DQZ256rrk */ + }, + { /* 4319 */ + 417, + /* VCVTTPS2DQZ256rrkz */ + }, + { /* 4320 */ + 418, + /* VCVTTPS2DQZrm */ + }, + { /* 4321 */ + 340, + /* VCVTTPS2DQZrmb */ + }, + { /* 4322 */ + 341, + /* VCVTTPS2DQZrmbk */ + }, + { /* 4323 */ + 342, + /* VCVTTPS2DQZrmbkz */ + }, + { /* 4324 */ + 419, + /* VCVTTPS2DQZrmk */ + }, + { /* 4325 */ + 420, + /* VCVTTPS2DQZrmkz */ + }, + { /* 4326 */ + 421, + /* VCVTTPS2DQZrr */ + }, + { /* 4327 */ + 497, + /* VCVTTPS2DQZrrb */ + }, + { /* 4328 */ + 498, + /* VCVTTPS2DQZrrbk */ + }, + { /* 4329 */ + 499, + /* VCVTTPS2DQZrrbkz */ + }, + { /* 4330 */ + 425, + /* VCVTTPS2DQZrrk */ + }, + { /* 4331 */ + 426, + /* VCVTTPS2DQZrrkz */ + }, + { /* 4332 */ + 30, + /* VCVTTPS2DQrm */ + }, + { /* 4333 */ + 31, + /* VCVTTPS2DQrr */ + }, + { /* 4334 */ + 327, + /* VCVTTPS2QQZ128rm */ + }, + { /* 4335 */ + 334, + /* VCVTTPS2QQZ128rmb */ + }, + { /* 4336 */ + 335, + /* VCVTTPS2QQZ128rmbk */ + }, + { /* 4337 */ + 336, + /* VCVTTPS2QQZ128rmbkz */ + }, + { /* 4338 */ + 328, + /* VCVTTPS2QQZ128rmk */ + }, + { /* 4339 */ + 329, + /* VCVTTPS2QQZ128rmkz */ + }, + { /* 4340 */ + 377, + /* VCVTTPS2QQZ128rr */ + }, + { /* 4341 */ + 400, + /* VCVTTPS2QQZ128rrk */ + }, + { /* 4342 */ + 401, + /* VCVTTPS2QQZ128rrkz */ + }, + { /* 4343 */ + 318, + /* VCVTTPS2QQZ256rm */ + }, + { /* 4344 */ + 337, + /* VCVTTPS2QQZ256rmb */ + }, + { /* 4345 */ + 338, + /* VCVTTPS2QQZ256rmbk */ + }, + { /* 4346 */ + 339, + /* VCVTTPS2QQZ256rmbkz */ + }, + { /* 4347 */ + 319, + /* VCVTTPS2QQZ256rmk */ + }, + { /* 4348 */ + 320, + /* VCVTTPS2QQZ256rmkz */ + }, + { /* 4349 */ + 402, + /* VCVTTPS2QQZ256rr */ + }, + { /* 4350 */ + 403, + /* VCVTTPS2QQZ256rrk */ + }, + { /* 4351 */ + 404, + /* VCVTTPS2QQZ256rrkz */ + }, + { /* 4352 */ + 324, + /* VCVTTPS2QQZrm */ + }, + { /* 4353 */ + 340, + /* VCVTTPS2QQZrmb */ + }, + { /* 4354 */ + 341, + /* VCVTTPS2QQZrmbk */ + }, + { /* 4355 */ + 342, + /* VCVTTPS2QQZrmbkz */ + }, + { /* 4356 */ + 325, + /* VCVTTPS2QQZrmk */ + }, + { /* 4357 */ + 326, + /* VCVTTPS2QQZrmkz */ + }, + { /* 4358 */ + 405, + /* VCVTTPS2QQZrr */ + }, + { /* 4359 */ + 446, + /* VCVTTPS2QQZrrb */ + }, + { /* 4360 */ + 447, + /* VCVTTPS2QQZrrbk */ + }, + { /* 4361 */ + 448, + /* VCVTTPS2QQZrrbkz */ + }, + { /* 4362 */ + 406, + /* VCVTTPS2QQZrrk */ + }, + { /* 4363 */ + 407, + /* VCVTTPS2QQZrrkz */ + }, + { /* 4364 */ + 409, + /* VCVTTPS2UDQZ128rm */ + }, + { /* 4365 */ + 334, + /* VCVTTPS2UDQZ128rmb */ + }, + { /* 4366 */ + 335, + /* VCVTTPS2UDQZ128rmbk */ + }, + { /* 4367 */ + 336, + /* VCVTTPS2UDQZ128rmbkz */ + }, + { /* 4368 */ + 410, + /* VCVTTPS2UDQZ128rmk */ + }, + { /* 4369 */ + 411, + /* VCVTTPS2UDQZ128rmkz */ + }, + { /* 4370 */ + 330, + /* VCVTTPS2UDQZ128rr */ + }, + { /* 4371 */ + 331, + /* VCVTTPS2UDQZ128rrk */ + }, + { /* 4372 */ + 332, + /* VCVTTPS2UDQZ128rrkz */ + }, + { /* 4373 */ + 412, + /* VCVTTPS2UDQZ256rm */ + }, + { /* 4374 */ + 337, + /* VCVTTPS2UDQZ256rmb */ + }, + { /* 4375 */ + 338, + /* VCVTTPS2UDQZ256rmbk */ + }, + { /* 4376 */ + 339, + /* VCVTTPS2UDQZ256rmbkz */ + }, + { /* 4377 */ + 413, + /* VCVTTPS2UDQZ256rmk */ + }, + { /* 4378 */ + 414, + /* VCVTTPS2UDQZ256rmkz */ + }, + { /* 4379 */ + 415, + /* VCVTTPS2UDQZ256rr */ + }, + { /* 4380 */ + 416, + /* VCVTTPS2UDQZ256rrk */ + }, + { /* 4381 */ + 417, + /* VCVTTPS2UDQZ256rrkz */ + }, + { /* 4382 */ + 418, + /* VCVTTPS2UDQZrm */ + }, + { /* 4383 */ + 340, + /* VCVTTPS2UDQZrmb */ + }, + { /* 4384 */ + 341, + /* VCVTTPS2UDQZrmbk */ + }, + { /* 4385 */ + 342, + /* VCVTTPS2UDQZrmbkz */ + }, + { /* 4386 */ + 419, + /* VCVTTPS2UDQZrmk */ + }, + { /* 4387 */ + 420, + /* VCVTTPS2UDQZrmkz */ + }, + { /* 4388 */ + 421, + /* VCVTTPS2UDQZrr */ + }, + { /* 4389 */ + 497, + /* VCVTTPS2UDQZrrb */ + }, + { /* 4390 */ + 498, + /* VCVTTPS2UDQZrrbk */ + }, + { /* 4391 */ + 499, + /* VCVTTPS2UDQZrrbkz */ + }, + { /* 4392 */ + 425, + /* VCVTTPS2UDQZrrk */ + }, + { /* 4393 */ + 426, + /* VCVTTPS2UDQZrrkz */ + }, + { /* 4394 */ + 327, + /* VCVTTPS2UQQZ128rm */ + }, + { /* 4395 */ + 334, + /* VCVTTPS2UQQZ128rmb */ + }, + { /* 4396 */ + 335, + /* VCVTTPS2UQQZ128rmbk */ + }, + { /* 4397 */ + 336, + /* VCVTTPS2UQQZ128rmbkz */ + }, + { /* 4398 */ + 328, + /* VCVTTPS2UQQZ128rmk */ + }, + { /* 4399 */ + 329, + /* VCVTTPS2UQQZ128rmkz */ + }, + { /* 4400 */ + 377, + /* VCVTTPS2UQQZ128rr */ + }, + { /* 4401 */ + 400, + /* VCVTTPS2UQQZ128rrk */ + }, + { /* 4402 */ + 401, + /* VCVTTPS2UQQZ128rrkz */ + }, + { /* 4403 */ + 318, + /* VCVTTPS2UQQZ256rm */ + }, + { /* 4404 */ + 337, + /* VCVTTPS2UQQZ256rmb */ + }, + { /* 4405 */ + 338, + /* VCVTTPS2UQQZ256rmbk */ + }, + { /* 4406 */ + 339, + /* VCVTTPS2UQQZ256rmbkz */ + }, + { /* 4407 */ + 319, + /* VCVTTPS2UQQZ256rmk */ + }, + { /* 4408 */ + 320, + /* VCVTTPS2UQQZ256rmkz */ + }, + { /* 4409 */ + 402, + /* VCVTTPS2UQQZ256rr */ + }, + { /* 4410 */ + 403, + /* VCVTTPS2UQQZ256rrk */ + }, + { /* 4411 */ + 404, + /* VCVTTPS2UQQZ256rrkz */ + }, + { /* 4412 */ + 324, + /* VCVTTPS2UQQZrm */ + }, + { /* 4413 */ + 340, + /* VCVTTPS2UQQZrmb */ + }, + { /* 4414 */ + 341, + /* VCVTTPS2UQQZrmbk */ + }, + { /* 4415 */ + 342, + /* VCVTTPS2UQQZrmbkz */ + }, + { /* 4416 */ + 325, + /* VCVTTPS2UQQZrmk */ + }, + { /* 4417 */ + 326, + /* VCVTTPS2UQQZrmkz */ + }, + { /* 4418 */ + 405, + /* VCVTTPS2UQQZrr */ + }, + { /* 4419 */ + 446, + /* VCVTTPS2UQQZrrb */ + }, + { /* 4420 */ + 447, + /* VCVTTPS2UQQZrrbk */ + }, + { /* 4421 */ + 448, + /* VCVTTPS2UQQZrrbkz */ + }, + { /* 4422 */ + 406, + /* VCVTTPS2UQQZrrk */ + }, + { /* 4423 */ + 407, + /* VCVTTPS2UQQZrrkz */ + }, + { /* 4424 */ + 0, + /* */ + }, + { /* 4425 */ + 473, + /* VCVTTSD2SI64Zrm_Int */ + }, + { /* 4426 */ + 0, + /* */ + }, + { /* 4427 */ + 474, + /* VCVTTSD2SI64Zrr_Int */ + }, + { /* 4428 */ + 474, + /* VCVTTSD2SI64Zrrb_Int */ + }, + { /* 4429 */ + 62, + /* VCVTTSD2SI64rm */ + }, + { /* 4430 */ + 0, + /* */ + }, + { /* 4431 */ + 86, + /* VCVTTSD2SI64rr */ + }, + { /* 4432 */ + 0, + /* */ + }, + { /* 4433 */ + 0, + /* */ + }, + { /* 4434 */ + 476, + /* VCVTTSD2SIZrm_Int */ + }, + { /* 4435 */ + 0, + /* */ + }, + { /* 4436 */ + 477, + /* VCVTTSD2SIZrr_Int */ + }, + { /* 4437 */ + 477, + /* VCVTTSD2SIZrrb_Int */ + }, + { /* 4438 */ + 87, + /* VCVTTSD2SIrm */ + }, + { /* 4439 */ + 0, + /* */ + }, + { /* 4440 */ + 88, + /* VCVTTSD2SIrr */ + }, + { /* 4441 */ + 0, + /* */ + }, + { /* 4442 */ + 0, + /* */ + }, + { /* 4443 */ + 473, + /* VCVTTSD2USI64Zrm_Int */ + }, + { /* 4444 */ + 0, + /* */ + }, + { /* 4445 */ + 474, + /* VCVTTSD2USI64Zrr_Int */ + }, + { /* 4446 */ + 474, + /* VCVTTSD2USI64Zrrb_Int */ + }, + { /* 4447 */ + 0, + /* */ + }, + { /* 4448 */ + 476, + /* VCVTTSD2USIZrm_Int */ + }, + { /* 4449 */ + 0, + /* */ + }, + { /* 4450 */ + 477, + /* VCVTTSD2USIZrr_Int */ + }, + { /* 4451 */ + 477, + /* VCVTTSD2USIZrrb_Int */ + }, + { /* 4452 */ + 0, + /* */ + }, + { /* 4453 */ + 485, + /* VCVTTSS2SI64Zrm_Int */ + }, + { /* 4454 */ + 0, + /* */ + }, + { /* 4455 */ + 486, + /* VCVTTSS2SI64Zrr_Int */ + }, + { /* 4456 */ + 486, + /* VCVTTSS2SI64Zrrb_Int */ + }, + { /* 4457 */ + 62, + /* VCVTTSS2SI64rm */ + }, + { /* 4458 */ + 0, + /* */ + }, + { /* 4459 */ + 86, + /* VCVTTSS2SI64rr */ + }, + { /* 4460 */ + 0, + /* */ + }, + { /* 4461 */ + 0, + /* */ + }, + { /* 4462 */ + 488, + /* VCVTTSS2SIZrm_Int */ + }, + { /* 4463 */ + 0, + /* */ + }, + { /* 4464 */ + 489, + /* VCVTTSS2SIZrr_Int */ + }, + { /* 4465 */ + 489, + /* VCVTTSS2SIZrrb_Int */ + }, + { /* 4466 */ + 87, + /* VCVTTSS2SIrm */ + }, + { /* 4467 */ + 0, + /* */ + }, + { /* 4468 */ + 88, + /* VCVTTSS2SIrr */ + }, + { /* 4469 */ + 0, + /* */ + }, + { /* 4470 */ + 0, + /* */ + }, + { /* 4471 */ + 485, + /* VCVTTSS2USI64Zrm_Int */ + }, + { /* 4472 */ + 0, + /* */ + }, + { /* 4473 */ + 486, + /* VCVTTSS2USI64Zrr_Int */ + }, + { /* 4474 */ + 486, + /* VCVTTSS2USI64Zrrb_Int */ + }, + { /* 4475 */ + 0, + /* */ + }, + { /* 4476 */ + 488, + /* VCVTTSS2USIZrm_Int */ + }, + { /* 4477 */ + 0, + /* */ + }, + { /* 4478 */ + 489, + /* VCVTTSS2USIZrr_Int */ + }, + { /* 4479 */ + 489, + /* VCVTTSS2USIZrrb_Int */ + }, + { /* 4480 */ + 327, + /* VCVTUDQ2PDZ128rm */ + }, + { /* 4481 */ + 334, + /* VCVTUDQ2PDZ128rmb */ + }, + { /* 4482 */ + 335, + /* VCVTUDQ2PDZ128rmbk */ + }, + { /* 4483 */ + 336, + /* VCVTUDQ2PDZ128rmbkz */ + }, + { /* 4484 */ + 328, + /* VCVTUDQ2PDZ128rmk */ + }, + { /* 4485 */ + 329, + /* VCVTUDQ2PDZ128rmkz */ + }, + { /* 4486 */ + 377, + /* VCVTUDQ2PDZ128rr */ + }, + { /* 4487 */ + 400, + /* VCVTUDQ2PDZ128rrk */ + }, + { /* 4488 */ + 401, + /* VCVTUDQ2PDZ128rrkz */ + }, + { /* 4489 */ + 318, + /* VCVTUDQ2PDZ256rm */ + }, + { /* 4490 */ + 337, + /* VCVTUDQ2PDZ256rmb */ + }, + { /* 4491 */ + 338, + /* VCVTUDQ2PDZ256rmbk */ + }, + { /* 4492 */ + 339, + /* VCVTUDQ2PDZ256rmbkz */ + }, + { /* 4493 */ + 319, + /* VCVTUDQ2PDZ256rmk */ + }, + { /* 4494 */ + 320, + /* VCVTUDQ2PDZ256rmkz */ + }, + { /* 4495 */ + 402, + /* VCVTUDQ2PDZ256rr */ + }, + { /* 4496 */ + 403, + /* VCVTUDQ2PDZ256rrk */ + }, + { /* 4497 */ + 404, + /* VCVTUDQ2PDZ256rrkz */ + }, + { /* 4498 */ + 324, + /* VCVTUDQ2PDZrm */ + }, + { /* 4499 */ + 340, + /* VCVTUDQ2PDZrmb */ + }, + { /* 4500 */ + 341, + /* VCVTUDQ2PDZrmbk */ + }, + { /* 4501 */ + 342, + /* VCVTUDQ2PDZrmbkz */ + }, + { /* 4502 */ + 325, + /* VCVTUDQ2PDZrmk */ + }, + { /* 4503 */ + 326, + /* VCVTUDQ2PDZrmkz */ + }, + { /* 4504 */ + 405, + /* VCVTUDQ2PDZrr */ + }, + { /* 4505 */ + 406, + /* VCVTUDQ2PDZrrk */ + }, + { /* 4506 */ + 407, + /* VCVTUDQ2PDZrrkz */ + }, + { /* 4507 */ + 409, + /* VCVTUDQ2PSZ128rm */ + }, + { /* 4508 */ + 334, + /* VCVTUDQ2PSZ128rmb */ + }, + { /* 4509 */ + 335, + /* VCVTUDQ2PSZ128rmbk */ + }, + { /* 4510 */ + 336, + /* VCVTUDQ2PSZ128rmbkz */ + }, + { /* 4511 */ + 410, + /* VCVTUDQ2PSZ128rmk */ + }, + { /* 4512 */ + 411, + /* VCVTUDQ2PSZ128rmkz */ + }, + { /* 4513 */ + 330, + /* VCVTUDQ2PSZ128rr */ + }, + { /* 4514 */ + 331, + /* VCVTUDQ2PSZ128rrk */ + }, + { /* 4515 */ + 332, + /* VCVTUDQ2PSZ128rrkz */ + }, + { /* 4516 */ + 412, + /* VCVTUDQ2PSZ256rm */ + }, + { /* 4517 */ + 337, + /* VCVTUDQ2PSZ256rmb */ + }, + { /* 4518 */ + 338, + /* VCVTUDQ2PSZ256rmbk */ + }, + { /* 4519 */ + 339, + /* VCVTUDQ2PSZ256rmbkz */ + }, + { /* 4520 */ + 413, + /* VCVTUDQ2PSZ256rmk */ + }, + { /* 4521 */ + 414, + /* VCVTUDQ2PSZ256rmkz */ + }, + { /* 4522 */ + 415, + /* VCVTUDQ2PSZ256rr */ + }, + { /* 4523 */ + 416, + /* VCVTUDQ2PSZ256rrk */ + }, + { /* 4524 */ + 417, + /* VCVTUDQ2PSZ256rrkz */ + }, + { /* 4525 */ + 418, + /* VCVTUDQ2PSZrm */ + }, + { /* 4526 */ + 340, + /* VCVTUDQ2PSZrmb */ + }, + { /* 4527 */ + 341, + /* VCVTUDQ2PSZrmbk */ + }, + { /* 4528 */ + 342, + /* VCVTUDQ2PSZrmbkz */ + }, + { /* 4529 */ + 419, + /* VCVTUDQ2PSZrmk */ + }, + { /* 4530 */ + 420, + /* VCVTUDQ2PSZrmkz */ + }, + { /* 4531 */ + 421, + /* VCVTUDQ2PSZrr */ + }, + { /* 4532 */ + 422, + /* VCVTUDQ2PSZrrb */ + }, + { /* 4533 */ + 423, + /* VCVTUDQ2PSZrrbk */ + }, + { /* 4534 */ + 424, + /* VCVTUDQ2PSZrrbkz */ + }, + { /* 4535 */ + 425, + /* VCVTUDQ2PSZrrk */ + }, + { /* 4536 */ + 426, + /* VCVTUDQ2PSZrrkz */ + }, + { /* 4537 */ + 409, + /* VCVTUQQ2PDZ128rm */ + }, + { /* 4538 */ + 327, + /* VCVTUQQ2PDZ128rmb */ + }, + { /* 4539 */ + 328, + /* VCVTUQQ2PDZ128rmbk */ + }, + { /* 4540 */ + 329, + /* VCVTUQQ2PDZ128rmbkz */ + }, + { /* 4541 */ + 410, + /* VCVTUQQ2PDZ128rmk */ + }, + { /* 4542 */ + 411, + /* VCVTUQQ2PDZ128rmkz */ + }, + { /* 4543 */ + 330, + /* VCVTUQQ2PDZ128rr */ + }, + { /* 4544 */ + 331, + /* VCVTUQQ2PDZ128rrk */ + }, + { /* 4545 */ + 332, + /* VCVTUQQ2PDZ128rrkz */ + }, + { /* 4546 */ + 412, + /* VCVTUQQ2PDZ256rm */ + }, + { /* 4547 */ + 306, + /* VCVTUQQ2PDZ256rmb */ + }, + { /* 4548 */ + 307, + /* VCVTUQQ2PDZ256rmbk */ + }, + { /* 4549 */ + 308, + /* VCVTUQQ2PDZ256rmbkz */ + }, + { /* 4550 */ + 413, + /* VCVTUQQ2PDZ256rmk */ + }, + { /* 4551 */ + 414, + /* VCVTUQQ2PDZ256rmkz */ + }, + { /* 4552 */ + 415, + /* VCVTUQQ2PDZ256rr */ + }, + { /* 4553 */ + 416, + /* VCVTUQQ2PDZ256rrk */ + }, + { /* 4554 */ + 417, + /* VCVTUQQ2PDZ256rrkz */ + }, + { /* 4555 */ + 418, + /* VCVTUQQ2PDZrm */ + }, + { /* 4556 */ + 312, + /* VCVTUQQ2PDZrmb */ + }, + { /* 4557 */ + 313, + /* VCVTUQQ2PDZrmbk */ + }, + { /* 4558 */ + 314, + /* VCVTUQQ2PDZrmbkz */ + }, + { /* 4559 */ + 419, + /* VCVTUQQ2PDZrmk */ + }, + { /* 4560 */ + 420, + /* VCVTUQQ2PDZrmkz */ + }, + { /* 4561 */ + 421, + /* VCVTUQQ2PDZrr */ + }, + { /* 4562 */ + 443, + /* VCVTUQQ2PDZrrb */ + }, + { /* 4563 */ + 444, + /* VCVTUQQ2PDZrrbk */ + }, + { /* 4564 */ + 445, + /* VCVTUQQ2PDZrrbkz */ + }, + { /* 4565 */ + 425, + /* VCVTUQQ2PDZrrk */ + }, + { /* 4566 */ + 426, + /* VCVTUQQ2PDZrrkz */ + }, + { /* 4567 */ + 409, + /* VCVTUQQ2PSZ128rm */ + }, + { /* 4568 */ + 327, + /* VCVTUQQ2PSZ128rmb */ + }, + { /* 4569 */ + 328, + /* VCVTUQQ2PSZ128rmbk */ + }, + { /* 4570 */ + 329, + /* VCVTUQQ2PSZ128rmbkz */ + }, + { /* 4571 */ + 410, + /* VCVTUQQ2PSZ128rmk */ + }, + { /* 4572 */ + 411, + /* VCVTUQQ2PSZ128rmkz */ + }, + { /* 4573 */ + 330, + /* VCVTUQQ2PSZ128rr */ + }, + { /* 4574 */ + 331, + /* VCVTUQQ2PSZ128rrk */ + }, + { /* 4575 */ + 332, + /* VCVTUQQ2PSZ128rrkz */ + }, + { /* 4576 */ + 428, + /* VCVTUQQ2PSZ256rm */ + }, + { /* 4577 */ + 327, + /* VCVTUQQ2PSZ256rmb */ + }, + { /* 4578 */ + 328, + /* VCVTUQQ2PSZ256rmbk */ + }, + { /* 4579 */ + 329, + /* VCVTUQQ2PSZ256rmbkz */ + }, + { /* 4580 */ + 429, + /* VCVTUQQ2PSZ256rmk */ + }, + { /* 4581 */ + 430, + /* VCVTUQQ2PSZ256rmkz */ + }, + { /* 4582 */ + 431, + /* VCVTUQQ2PSZ256rr */ + }, + { /* 4583 */ + 432, + /* VCVTUQQ2PSZ256rrk */ + }, + { /* 4584 */ + 433, + /* VCVTUQQ2PSZ256rrkz */ + }, + { /* 4585 */ + 434, + /* VCVTUQQ2PSZrm */ + }, + { /* 4586 */ + 306, + /* VCVTUQQ2PSZrmb */ + }, + { /* 4587 */ + 307, + /* VCVTUQQ2PSZrmbk */ + }, + { /* 4588 */ + 308, + /* VCVTUQQ2PSZrmbkz */ + }, + { /* 4589 */ + 435, + /* VCVTUQQ2PSZrmk */ + }, + { /* 4590 */ + 436, + /* VCVTUQQ2PSZrmkz */ + }, + { /* 4591 */ + 437, + /* VCVTUQQ2PSZrr */ + }, + { /* 4592 */ + 438, + /* VCVTUQQ2PSZrrb */ + }, + { /* 4593 */ + 439, + /* VCVTUQQ2PSZrrbk */ + }, + { /* 4594 */ + 440, + /* VCVTUQQ2PSZrrbkz */ + }, + { /* 4595 */ + 441, + /* VCVTUQQ2PSZrrk */ + }, + { /* 4596 */ + 442, + /* VCVTUQQ2PSZrrkz */ + }, + { /* 4597 */ + 237, + /* VCVTUSI2SDZrm */ + }, + { /* 4598 */ + 0, + /* */ + }, + { /* 4599 */ + 479, + /* VCVTUSI2SDZrr */ + }, + { /* 4600 */ + 0, + /* */ + }, + { /* 4601 */ + 237, + /* VCVTUSI2SSZrm */ + }, + { /* 4602 */ + 0, + /* */ + }, + { /* 4603 */ + 479, + /* VCVTUSI2SSZrr */ + }, + { /* 4604 */ + 0, + /* */ + }, + { /* 4605 */ + 480, + /* VCVTUSI2SSZrrb_Int */ + }, + { /* 4606 */ + 207, + /* VCVTUSI642SDZrm */ + }, + { /* 4607 */ + 0, + /* */ + }, + { /* 4608 */ + 482, + /* VCVTUSI642SDZrr */ + }, + { /* 4609 */ + 0, + /* */ + }, + { /* 4610 */ + 483, + /* VCVTUSI642SDZrrb_Int */ + }, + { /* 4611 */ + 207, + /* VCVTUSI642SSZrm */ + }, + { /* 4612 */ + 0, + /* */ + }, + { /* 4613 */ + 482, + /* VCVTUSI642SSZrr */ + }, + { /* 4614 */ + 0, + /* */ + }, + { /* 4615 */ + 483, + /* VCVTUSI642SSZrrb_Int */ + }, + { /* 4616 */ + 264, + /* VDBPSADBWZ128rmi */ + }, + { /* 4617 */ + 265, + /* VDBPSADBWZ128rmik */ + }, + { /* 4618 */ + 266, + /* VDBPSADBWZ128rmikz */ + }, + { /* 4619 */ + 267, + /* VDBPSADBWZ128rri */ + }, + { /* 4620 */ + 268, + /* VDBPSADBWZ128rrik */ + }, + { /* 4621 */ + 269, + /* VDBPSADBWZ128rrikz */ + }, + { /* 4622 */ + 273, + /* VDBPSADBWZ256rmi */ + }, + { /* 4623 */ + 274, + /* VDBPSADBWZ256rmik */ + }, + { /* 4624 */ + 275, + /* VDBPSADBWZ256rmikz */ + }, + { /* 4625 */ + 276, + /* VDBPSADBWZ256rri */ + }, + { /* 4626 */ + 277, + /* VDBPSADBWZ256rrik */ + }, + { /* 4627 */ + 278, + /* VDBPSADBWZ256rrikz */ + }, + { /* 4628 */ + 282, + /* VDBPSADBWZrmi */ + }, + { /* 4629 */ + 283, + /* VDBPSADBWZrmik */ + }, + { /* 4630 */ + 284, + /* VDBPSADBWZrmikz */ + }, + { /* 4631 */ + 285, + /* VDBPSADBWZrri */ + }, + { /* 4632 */ + 286, + /* VDBPSADBWZrrik */ + }, + { /* 4633 */ + 287, + /* VDBPSADBWZrrikz */ + }, + { /* 4634 */ + 204, + /* VDIVPDYrm */ + }, + { /* 4635 */ + 205, + /* VDIVPDYrr */ + }, + { /* 4636 */ + 206, + /* VDIVPDZ128rm */ + }, + { /* 4637 */ + 207, + /* VDIVPDZ128rmb */ + }, + { /* 4638 */ + 208, + /* VDIVPDZ128rmbk */ + }, + { /* 4639 */ + 209, + /* VDIVPDZ128rmbkz */ + }, + { /* 4640 */ + 203, + /* VDIVPDZ128rmk */ + }, + { /* 4641 */ + 210, + /* VDIVPDZ128rmkz */ + }, + { /* 4642 */ + 211, + /* VDIVPDZ128rr */ + }, + { /* 4643 */ + 212, + /* VDIVPDZ128rrk */ + }, + { /* 4644 */ + 213, + /* VDIVPDZ128rrkz */ + }, + { /* 4645 */ + 214, + /* VDIVPDZ256rm */ + }, + { /* 4646 */ + 215, + /* VDIVPDZ256rmb */ + }, + { /* 4647 */ + 216, + /* VDIVPDZ256rmbk */ + }, + { /* 4648 */ + 217, + /* VDIVPDZ256rmbkz */ + }, + { /* 4649 */ + 218, + /* VDIVPDZ256rmk */ + }, + { /* 4650 */ + 219, + /* VDIVPDZ256rmkz */ + }, + { /* 4651 */ + 220, + /* VDIVPDZ256rr */ + }, + { /* 4652 */ + 221, + /* VDIVPDZ256rrk */ + }, + { /* 4653 */ + 222, + /* VDIVPDZ256rrkz */ + }, + { /* 4654 */ + 223, + /* VDIVPDZrm */ + }, + { /* 4655 */ + 224, + /* VDIVPDZrmb */ + }, + { /* 4656 */ + 225, + /* VDIVPDZrmbk */ + }, + { /* 4657 */ + 226, + /* VDIVPDZrmbkz */ + }, + { /* 4658 */ + 227, + /* VDIVPDZrmk */ + }, + { /* 4659 */ + 228, + /* VDIVPDZrmkz */ + }, + { /* 4660 */ + 229, + /* VDIVPDZrr */ + }, + { /* 4661 */ + 230, + /* VDIVPDZrrb */ + }, + { /* 4662 */ + 231, + /* VDIVPDZrrbk */ + }, + { /* 4663 */ + 232, + /* VDIVPDZrrbkz */ + }, + { /* 4664 */ + 233, + /* VDIVPDZrrk */ + }, + { /* 4665 */ + 234, + /* VDIVPDZrrkz */ + }, + { /* 4666 */ + 235, + /* VDIVPDrm */ + }, + { /* 4667 */ + 236, + /* VDIVPDrr */ + }, + { /* 4668 */ + 204, + /* VDIVPSYrm */ + }, + { /* 4669 */ + 205, + /* VDIVPSYrr */ + }, + { /* 4670 */ + 206, + /* VDIVPSZ128rm */ + }, + { /* 4671 */ + 237, + /* VDIVPSZ128rmb */ + }, + { /* 4672 */ + 238, + /* VDIVPSZ128rmbk */ + }, + { /* 4673 */ + 239, + /* VDIVPSZ128rmbkz */ + }, + { /* 4674 */ + 203, + /* VDIVPSZ128rmk */ + }, + { /* 4675 */ + 210, + /* VDIVPSZ128rmkz */ + }, + { /* 4676 */ + 211, + /* VDIVPSZ128rr */ + }, + { /* 4677 */ + 212, + /* VDIVPSZ128rrk */ + }, + { /* 4678 */ + 213, + /* VDIVPSZ128rrkz */ + }, + { /* 4679 */ + 214, + /* VDIVPSZ256rm */ + }, + { /* 4680 */ + 240, + /* VDIVPSZ256rmb */ + }, + { /* 4681 */ + 241, + /* VDIVPSZ256rmbk */ + }, + { /* 4682 */ + 242, + /* VDIVPSZ256rmbkz */ + }, + { /* 4683 */ + 218, + /* VDIVPSZ256rmk */ + }, + { /* 4684 */ + 219, + /* VDIVPSZ256rmkz */ + }, + { /* 4685 */ + 220, + /* VDIVPSZ256rr */ + }, + { /* 4686 */ + 221, + /* VDIVPSZ256rrk */ + }, + { /* 4687 */ + 222, + /* VDIVPSZ256rrkz */ + }, + { /* 4688 */ + 223, + /* VDIVPSZrm */ + }, + { /* 4689 */ + 243, + /* VDIVPSZrmb */ + }, + { /* 4690 */ + 244, + /* VDIVPSZrmbk */ + }, + { /* 4691 */ + 245, + /* VDIVPSZrmbkz */ + }, + { /* 4692 */ + 227, + /* VDIVPSZrmk */ + }, + { /* 4693 */ + 228, + /* VDIVPSZrmkz */ + }, + { /* 4694 */ + 229, + /* VDIVPSZrr */ + }, + { /* 4695 */ + 246, + /* VDIVPSZrrb */ + }, + { /* 4696 */ + 247, + /* VDIVPSZrrbk */ + }, + { /* 4697 */ + 248, + /* VDIVPSZrrbkz */ + }, + { /* 4698 */ + 233, + /* VDIVPSZrrk */ + }, + { /* 4699 */ + 234, + /* VDIVPSZrrkz */ + }, + { /* 4700 */ + 235, + /* VDIVPSrm */ + }, + { /* 4701 */ + 236, + /* VDIVPSrr */ + }, + { /* 4702 */ + 0, + /* */ + }, + { /* 4703 */ + 207, + /* VDIVSDZrm_Int */ + }, + { /* 4704 */ + 208, + /* VDIVSDZrm_Intk */ + }, + { /* 4705 */ + 209, + /* VDIVSDZrm_Intkz */ + }, + { /* 4706 */ + 0, + /* */ + }, + { /* 4707 */ + 249, + /* VDIVSDZrr_Int */ + }, + { /* 4708 */ + 250, + /* VDIVSDZrr_Intk */ + }, + { /* 4709 */ + 251, + /* VDIVSDZrr_Intkz */ + }, + { /* 4710 */ + 252, + /* VDIVSDZrrb_Int */ + }, + { /* 4711 */ + 253, + /* VDIVSDZrrb_Intk */ + }, + { /* 4712 */ + 254, + /* VDIVSDZrrb_Intkz */ + }, + { /* 4713 */ + 235, + /* VDIVSDrm */ + }, + { /* 4714 */ + 0, + /* */ + }, + { /* 4715 */ + 236, + /* VDIVSDrr */ + }, + { /* 4716 */ + 0, + /* */ + }, + { /* 4717 */ + 0, + /* */ + }, + { /* 4718 */ + 237, + /* VDIVSSZrm_Int */ + }, + { /* 4719 */ + 238, + /* VDIVSSZrm_Intk */ + }, + { /* 4720 */ + 239, + /* VDIVSSZrm_Intkz */ + }, + { /* 4721 */ + 0, + /* */ + }, + { /* 4722 */ + 255, + /* VDIVSSZrr_Int */ + }, + { /* 4723 */ + 256, + /* VDIVSSZrr_Intk */ + }, + { /* 4724 */ + 257, + /* VDIVSSZrr_Intkz */ + }, + { /* 4725 */ + 258, + /* VDIVSSZrrb_Int */ + }, + { /* 4726 */ + 259, + /* VDIVSSZrrb_Intk */ + }, + { /* 4727 */ + 260, + /* VDIVSSZrrb_Intkz */ + }, + { /* 4728 */ + 235, + /* VDIVSSrm */ + }, + { /* 4729 */ + 0, + /* */ + }, + { /* 4730 */ + 236, + /* VDIVSSrr */ + }, + { /* 4731 */ + 0, + /* */ + }, + { /* 4732 */ + 299, + /* VDPPDrmi */ + }, + { /* 4733 */ + 300, + /* VDPPDrri */ + }, + { /* 4734 */ + 297, + /* VDPPSYrmi */ + }, + { /* 4735 */ + 298, + /* VDPPSYrri */ + }, + { /* 4736 */ + 299, + /* VDPPSrmi */ + }, + { /* 4737 */ + 300, + /* VDPPSrri */ + }, + { /* 4738 */ + 28, + /* VERRm */ + }, + { /* 4739 */ + 123, + /* VERRr */ + }, + { /* 4740 */ + 28, + /* VERWm */ + }, + { /* 4741 */ + 123, + /* VERWr */ + }, + { /* 4742 */ + 418, + /* VEXP2PDZm */ + }, + { /* 4743 */ + 312, + /* VEXP2PDZmb */ + }, + { /* 4744 */ + 313, + /* VEXP2PDZmbk */ + }, + { /* 4745 */ + 314, + /* VEXP2PDZmbkz */ + }, + { /* 4746 */ + 419, + /* VEXP2PDZmk */ + }, + { /* 4747 */ + 420, + /* VEXP2PDZmkz */ + }, + { /* 4748 */ + 421, + /* VEXP2PDZr */ + }, + { /* 4749 */ + 494, + /* VEXP2PDZrb */ + }, + { /* 4750 */ + 495, + /* VEXP2PDZrbk */ + }, + { /* 4751 */ + 496, + /* VEXP2PDZrbkz */ + }, + { /* 4752 */ + 425, + /* VEXP2PDZrk */ + }, + { /* 4753 */ + 426, + /* VEXP2PDZrkz */ + }, + { /* 4754 */ + 418, + /* VEXP2PSZm */ + }, + { /* 4755 */ + 340, + /* VEXP2PSZmb */ + }, + { /* 4756 */ + 341, + /* VEXP2PSZmbk */ + }, + { /* 4757 */ + 342, + /* VEXP2PSZmbkz */ + }, + { /* 4758 */ + 419, + /* VEXP2PSZmk */ + }, + { /* 4759 */ + 420, + /* VEXP2PSZmkz */ + }, + { /* 4760 */ + 421, + /* VEXP2PSZr */ + }, + { /* 4761 */ + 497, + /* VEXP2PSZrb */ + }, + { /* 4762 */ + 498, + /* VEXP2PSZrbk */ + }, + { /* 4763 */ + 499, + /* VEXP2PSZrbkz */ + }, + { /* 4764 */ + 425, + /* VEXP2PSZrk */ + }, + { /* 4765 */ + 426, + /* VEXP2PSZrkz */ + }, + { /* 4766 */ + 327, + /* VEXPANDPDZ128rm */ + }, + { /* 4767 */ + 328, + /* VEXPANDPDZ128rmk */ + }, + { /* 4768 */ + 329, + /* VEXPANDPDZ128rmkz */ + }, + { /* 4769 */ + 330, + /* VEXPANDPDZ128rr */ + }, + { /* 4770 */ + 331, + /* VEXPANDPDZ128rrk */ + }, + { /* 4771 */ + 332, + /* VEXPANDPDZ128rrkz */ + }, + { /* 4772 */ + 306, + /* VEXPANDPDZ256rm */ + }, + { /* 4773 */ + 307, + /* VEXPANDPDZ256rmk */ + }, + { /* 4774 */ + 308, + /* VEXPANDPDZ256rmkz */ + }, + { /* 4775 */ + 415, + /* VEXPANDPDZ256rr */ + }, + { /* 4776 */ + 416, + /* VEXPANDPDZ256rrk */ + }, + { /* 4777 */ + 417, + /* VEXPANDPDZ256rrkz */ + }, + { /* 4778 */ + 312, + /* VEXPANDPDZrm */ + }, + { /* 4779 */ + 313, + /* VEXPANDPDZrmk */ + }, + { /* 4780 */ + 314, + /* VEXPANDPDZrmkz */ + }, + { /* 4781 */ + 421, + /* VEXPANDPDZrr */ + }, + { /* 4782 */ + 425, + /* VEXPANDPDZrrk */ + }, + { /* 4783 */ + 426, + /* VEXPANDPDZrrkz */ + }, + { /* 4784 */ + 334, + /* VEXPANDPSZ128rm */ + }, + { /* 4785 */ + 335, + /* VEXPANDPSZ128rmk */ + }, + { /* 4786 */ + 336, + /* VEXPANDPSZ128rmkz */ + }, + { /* 4787 */ + 330, + /* VEXPANDPSZ128rr */ + }, + { /* 4788 */ + 331, + /* VEXPANDPSZ128rrk */ + }, + { /* 4789 */ + 332, + /* VEXPANDPSZ128rrkz */ + }, + { /* 4790 */ + 337, + /* VEXPANDPSZ256rm */ + }, + { /* 4791 */ + 338, + /* VEXPANDPSZ256rmk */ + }, + { /* 4792 */ + 339, + /* VEXPANDPSZ256rmkz */ + }, + { /* 4793 */ + 415, + /* VEXPANDPSZ256rr */ + }, + { /* 4794 */ + 416, + /* VEXPANDPSZ256rrk */ + }, + { /* 4795 */ + 417, + /* VEXPANDPSZ256rrkz */ + }, + { /* 4796 */ + 340, + /* VEXPANDPSZrm */ + }, + { /* 4797 */ + 341, + /* VEXPANDPSZrmk */ + }, + { /* 4798 */ + 342, + /* VEXPANDPSZrmkz */ + }, + { /* 4799 */ + 421, + /* VEXPANDPSZrr */ + }, + { /* 4800 */ + 425, + /* VEXPANDPSZrrk */ + }, + { /* 4801 */ + 426, + /* VEXPANDPSZrrkz */ + }, + { /* 4802 */ + 449, + /* VEXTRACTF128mr */ + }, + { /* 4803 */ + 450, + /* VEXTRACTF128rr */ + }, + { /* 4804 */ + 456, + /* VEXTRACTF32x4Z256mr */ + }, + { /* 4805 */ + 457, + /* VEXTRACTF32x4Z256mrk */ + }, + { /* 4806 */ + 458, + /* VEXTRACTF32x4Z256rr */ + }, + { /* 4807 */ + 459, + /* VEXTRACTF32x4Z256rrk */ + }, + { /* 4808 */ + 460, + /* VEXTRACTF32x4Z256rrkz */ + }, + { /* 4809 */ + 500, + /* VEXTRACTF32x4Zmr */ + }, + { /* 4810 */ + 501, + /* VEXTRACTF32x4Zmrk */ + }, + { /* 4811 */ + 502, + /* VEXTRACTF32x4Zrr */ + }, + { /* 4812 */ + 503, + /* VEXTRACTF32x4Zrrk */ + }, + { /* 4813 */ + 504, + /* VEXTRACTF32x4Zrrkz */ + }, + { /* 4814 */ + 461, + /* VEXTRACTF32x8Zmr */ + }, + { /* 4815 */ + 462, + /* VEXTRACTF32x8Zmrk */ + }, + { /* 4816 */ + 463, + /* VEXTRACTF32x8Zrr */ + }, + { /* 4817 */ + 467, + /* VEXTRACTF32x8Zrrk */ + }, + { /* 4818 */ + 468, + /* VEXTRACTF32x8Zrrkz */ + }, + { /* 4819 */ + 456, + /* VEXTRACTF64x2Z256mr */ + }, + { /* 4820 */ + 457, + /* VEXTRACTF64x2Z256mrk */ + }, + { /* 4821 */ + 458, + /* VEXTRACTF64x2Z256rr */ + }, + { /* 4822 */ + 459, + /* VEXTRACTF64x2Z256rrk */ + }, + { /* 4823 */ + 460, + /* VEXTRACTF64x2Z256rrkz */ + }, + { /* 4824 */ + 500, + /* VEXTRACTF64x2Zmr */ + }, + { /* 4825 */ + 501, + /* VEXTRACTF64x2Zmrk */ + }, + { /* 4826 */ + 502, + /* VEXTRACTF64x2Zrr */ + }, + { /* 4827 */ + 503, + /* VEXTRACTF64x2Zrrk */ + }, + { /* 4828 */ + 504, + /* VEXTRACTF64x2Zrrkz */ + }, + { /* 4829 */ + 461, + /* VEXTRACTF64x4Zmr */ + }, + { /* 4830 */ + 462, + /* VEXTRACTF64x4Zmrk */ + }, + { /* 4831 */ + 463, + /* VEXTRACTF64x4Zrr */ + }, + { /* 4832 */ + 467, + /* VEXTRACTF64x4Zrrk */ + }, + { /* 4833 */ + 468, + /* VEXTRACTF64x4Zrrkz */ + }, + { /* 4834 */ + 449, + /* VEXTRACTI128mr */ + }, + { /* 4835 */ + 450, + /* VEXTRACTI128rr */ + }, + { /* 4836 */ + 456, + /* VEXTRACTI32x4Z256mr */ + }, + { /* 4837 */ + 457, + /* VEXTRACTI32x4Z256mrk */ + }, + { /* 4838 */ + 458, + /* VEXTRACTI32x4Z256rr */ + }, + { /* 4839 */ + 459, + /* VEXTRACTI32x4Z256rrk */ + }, + { /* 4840 */ + 460, + /* VEXTRACTI32x4Z256rrkz */ + }, + { /* 4841 */ + 500, + /* VEXTRACTI32x4Zmr */ + }, + { /* 4842 */ + 501, + /* VEXTRACTI32x4Zmrk */ + }, + { /* 4843 */ + 502, + /* VEXTRACTI32x4Zrr */ + }, + { /* 4844 */ + 503, + /* VEXTRACTI32x4Zrrk */ + }, + { /* 4845 */ + 504, + /* VEXTRACTI32x4Zrrkz */ + }, + { /* 4846 */ + 461, + /* VEXTRACTI32x8Zmr */ + }, + { /* 4847 */ + 462, + /* VEXTRACTI32x8Zmrk */ + }, + { /* 4848 */ + 463, + /* VEXTRACTI32x8Zrr */ + }, + { /* 4849 */ + 467, + /* VEXTRACTI32x8Zrrk */ + }, + { /* 4850 */ + 468, + /* VEXTRACTI32x8Zrrkz */ + }, + { /* 4851 */ + 456, + /* VEXTRACTI64x2Z256mr */ + }, + { /* 4852 */ + 457, + /* VEXTRACTI64x2Z256mrk */ + }, + { /* 4853 */ + 458, + /* VEXTRACTI64x2Z256rr */ + }, + { /* 4854 */ + 459, + /* VEXTRACTI64x2Z256rrk */ + }, + { /* 4855 */ + 460, + /* VEXTRACTI64x2Z256rrkz */ + }, + { /* 4856 */ + 500, + /* VEXTRACTI64x2Zmr */ + }, + { /* 4857 */ + 501, + /* VEXTRACTI64x2Zmrk */ + }, + { /* 4858 */ + 502, + /* VEXTRACTI64x2Zrr */ + }, + { /* 4859 */ + 503, + /* VEXTRACTI64x2Zrrk */ + }, + { /* 4860 */ + 504, + /* VEXTRACTI64x2Zrrkz */ + }, + { /* 4861 */ + 461, + /* VEXTRACTI64x4Zmr */ + }, + { /* 4862 */ + 462, + /* VEXTRACTI64x4Zmrk */ + }, + { /* 4863 */ + 463, + /* VEXTRACTI64x4Zrr */ + }, + { /* 4864 */ + 467, + /* VEXTRACTI64x4Zrrk */ + }, + { /* 4865 */ + 468, + /* VEXTRACTI64x4Zrrkz */ + }, + { /* 4866 */ + 505, + /* VEXTRACTPSZmr */ + }, + { /* 4867 */ + 506, + /* VEXTRACTPSZrr */ + }, + { /* 4868 */ + 96, + /* VEXTRACTPSmr */ + }, + { /* 4869 */ + 97, + /* VEXTRACTPSrr */ + }, + { /* 4870 */ + 507, + /* VFIXUPIMMPDZ128rmbi */ + }, + { /* 4871 */ + 289, + /* VFIXUPIMMPDZ128rmbik */ + }, + { /* 4872 */ + 289, + /* VFIXUPIMMPDZ128rmbikz */ + }, + { /* 4873 */ + 508, + /* VFIXUPIMMPDZ128rmi */ + }, + { /* 4874 */ + 265, + /* VFIXUPIMMPDZ128rmik */ + }, + { /* 4875 */ + 265, + /* VFIXUPIMMPDZ128rmikz */ + }, + { /* 4876 */ + 509, + /* VFIXUPIMMPDZ128rri */ + }, + { /* 4877 */ + 268, + /* VFIXUPIMMPDZ128rrik */ + }, + { /* 4878 */ + 268, + /* VFIXUPIMMPDZ128rrikz */ + }, + { /* 4879 */ + 510, + /* VFIXUPIMMPDZ256rmbi */ + }, + { /* 4880 */ + 292, + /* VFIXUPIMMPDZ256rmbik */ + }, + { /* 4881 */ + 292, + /* VFIXUPIMMPDZ256rmbikz */ + }, + { /* 4882 */ + 511, + /* VFIXUPIMMPDZ256rmi */ + }, + { /* 4883 */ + 274, + /* VFIXUPIMMPDZ256rmik */ + }, + { /* 4884 */ + 274, + /* VFIXUPIMMPDZ256rmikz */ + }, + { /* 4885 */ + 512, + /* VFIXUPIMMPDZ256rri */ + }, + { /* 4886 */ + 277, + /* VFIXUPIMMPDZ256rrik */ + }, + { /* 4887 */ + 277, + /* VFIXUPIMMPDZ256rrikz */ + }, + { /* 4888 */ + 513, + /* VFIXUPIMMPDZrmbi */ + }, + { /* 4889 */ + 295, + /* VFIXUPIMMPDZrmbik */ + }, + { /* 4890 */ + 295, + /* VFIXUPIMMPDZrmbikz */ + }, + { /* 4891 */ + 514, + /* VFIXUPIMMPDZrmi */ + }, + { /* 4892 */ + 283, + /* VFIXUPIMMPDZrmik */ + }, + { /* 4893 */ + 283, + /* VFIXUPIMMPDZrmikz */ + }, + { /* 4894 */ + 515, + /* VFIXUPIMMPDZrri */ + }, + { /* 4895 */ + 516, + /* VFIXUPIMMPDZrrib */ + }, + { /* 4896 */ + 517, + /* VFIXUPIMMPDZrribk */ + }, + { /* 4897 */ + 517, + /* VFIXUPIMMPDZrribkz */ + }, + { /* 4898 */ + 286, + /* VFIXUPIMMPDZrrik */ + }, + { /* 4899 */ + 286, + /* VFIXUPIMMPDZrrikz */ + }, + { /* 4900 */ + 518, + /* VFIXUPIMMPSZ128rmbi */ + }, + { /* 4901 */ + 262, + /* VFIXUPIMMPSZ128rmbik */ + }, + { /* 4902 */ + 262, + /* VFIXUPIMMPSZ128rmbikz */ + }, + { /* 4903 */ + 508, + /* VFIXUPIMMPSZ128rmi */ + }, + { /* 4904 */ + 265, + /* VFIXUPIMMPSZ128rmik */ + }, + { /* 4905 */ + 265, + /* VFIXUPIMMPSZ128rmikz */ + }, + { /* 4906 */ + 509, + /* VFIXUPIMMPSZ128rri */ + }, + { /* 4907 */ + 268, + /* VFIXUPIMMPSZ128rrik */ + }, + { /* 4908 */ + 268, + /* VFIXUPIMMPSZ128rrikz */ + }, + { /* 4909 */ + 519, + /* VFIXUPIMMPSZ256rmbi */ + }, + { /* 4910 */ + 271, + /* VFIXUPIMMPSZ256rmbik */ + }, + { /* 4911 */ + 271, + /* VFIXUPIMMPSZ256rmbikz */ + }, + { /* 4912 */ + 511, + /* VFIXUPIMMPSZ256rmi */ + }, + { /* 4913 */ + 274, + /* VFIXUPIMMPSZ256rmik */ + }, + { /* 4914 */ + 274, + /* VFIXUPIMMPSZ256rmikz */ + }, + { /* 4915 */ + 512, + /* VFIXUPIMMPSZ256rri */ + }, + { /* 4916 */ + 277, + /* VFIXUPIMMPSZ256rrik */ + }, + { /* 4917 */ + 277, + /* VFIXUPIMMPSZ256rrikz */ + }, + { /* 4918 */ + 520, + /* VFIXUPIMMPSZrmbi */ + }, + { /* 4919 */ + 280, + /* VFIXUPIMMPSZrmbik */ + }, + { /* 4920 */ + 280, + /* VFIXUPIMMPSZrmbikz */ + }, + { /* 4921 */ + 514, + /* VFIXUPIMMPSZrmi */ + }, + { /* 4922 */ + 283, + /* VFIXUPIMMPSZrmik */ + }, + { /* 4923 */ + 283, + /* VFIXUPIMMPSZrmikz */ + }, + { /* 4924 */ + 515, + /* VFIXUPIMMPSZrri */ + }, + { /* 4925 */ + 521, + /* VFIXUPIMMPSZrrib */ + }, + { /* 4926 */ + 522, + /* VFIXUPIMMPSZrribk */ + }, + { /* 4927 */ + 522, + /* VFIXUPIMMPSZrribkz */ + }, + { /* 4928 */ + 286, + /* VFIXUPIMMPSZrrik */ + }, + { /* 4929 */ + 286, + /* VFIXUPIMMPSZrrikz */ + }, + { /* 4930 */ + 507, + /* VFIXUPIMMSDZrmi */ + }, + { /* 4931 */ + 289, + /* VFIXUPIMMSDZrmik */ + }, + { /* 4932 */ + 289, + /* VFIXUPIMMSDZrmikz */ + }, + { /* 4933 */ + 523, + /* VFIXUPIMMSDZrri */ + }, + { /* 4934 */ + 523, + /* VFIXUPIMMSDZrrib */ + }, + { /* 4935 */ + 524, + /* VFIXUPIMMSDZrribk */ + }, + { /* 4936 */ + 524, + /* VFIXUPIMMSDZrribkz */ + }, + { /* 4937 */ + 524, + /* VFIXUPIMMSDZrrik */ + }, + { /* 4938 */ + 524, + /* VFIXUPIMMSDZrrikz */ + }, + { /* 4939 */ + 518, + /* VFIXUPIMMSSZrmi */ + }, + { /* 4940 */ + 262, + /* VFIXUPIMMSSZrmik */ + }, + { /* 4941 */ + 262, + /* VFIXUPIMMSSZrmikz */ + }, + { /* 4942 */ + 525, + /* VFIXUPIMMSSZrri */ + }, + { /* 4943 */ + 525, + /* VFIXUPIMMSSZrrib */ + }, + { /* 4944 */ + 526, + /* VFIXUPIMMSSZrribk */ + }, + { /* 4945 */ + 526, + /* VFIXUPIMMSSZrribkz */ + }, + { /* 4946 */ + 526, + /* VFIXUPIMMSSZrrik */ + }, + { /* 4947 */ + 526, + /* VFIXUPIMMSSZrrikz */ + }, + { /* 4948 */ + 527, + /* VFMADD132PDYm */ + }, + { /* 4949 */ + 528, + /* VFMADD132PDYr */ + }, + { /* 4950 */ + 202, + /* VFMADD132PDZ128m */ + }, + { /* 4951 */ + 529, + /* VFMADD132PDZ128mb */ + }, + { /* 4952 */ + 208, + /* VFMADD132PDZ128mbk */ + }, + { /* 4953 */ + 208, + /* VFMADD132PDZ128mbkz */ + }, + { /* 4954 */ + 203, + /* VFMADD132PDZ128mk */ + }, + { /* 4955 */ + 203, + /* VFMADD132PDZ128mkz */ + }, + { /* 4956 */ + 530, + /* VFMADD132PDZ128r */ + }, + { /* 4957 */ + 212, + /* VFMADD132PDZ128rk */ + }, + { /* 4958 */ + 212, + /* VFMADD132PDZ128rkz */ + }, + { /* 4959 */ + 531, + /* VFMADD132PDZ256m */ + }, + { /* 4960 */ + 532, + /* VFMADD132PDZ256mb */ + }, + { /* 4961 */ + 216, + /* VFMADD132PDZ256mbk */ + }, + { /* 4962 */ + 216, + /* VFMADD132PDZ256mbkz */ + }, + { /* 4963 */ + 218, + /* VFMADD132PDZ256mk */ + }, + { /* 4964 */ + 218, + /* VFMADD132PDZ256mkz */ + }, + { /* 4965 */ + 533, + /* VFMADD132PDZ256r */ + }, + { /* 4966 */ + 221, + /* VFMADD132PDZ256rk */ + }, + { /* 4967 */ + 221, + /* VFMADD132PDZ256rkz */ + }, + { /* 4968 */ + 534, + /* VFMADD132PDZm */ + }, + { /* 4969 */ + 535, + /* VFMADD132PDZmb */ + }, + { /* 4970 */ + 225, + /* VFMADD132PDZmbk */ + }, + { /* 4971 */ + 225, + /* VFMADD132PDZmbkz */ + }, + { /* 4972 */ + 227, + /* VFMADD132PDZmk */ + }, + { /* 4973 */ + 227, + /* VFMADD132PDZmkz */ + }, + { /* 4974 */ + 536, + /* VFMADD132PDZr */ + }, + { /* 4975 */ + 537, + /* VFMADD132PDZrb */ + }, + { /* 4976 */ + 231, + /* VFMADD132PDZrbk */ + }, + { /* 4977 */ + 231, + /* VFMADD132PDZrbkz */ + }, + { /* 4978 */ + 233, + /* VFMADD132PDZrk */ + }, + { /* 4979 */ + 233, + /* VFMADD132PDZrkz */ + }, + { /* 4980 */ + 538, + /* VFMADD132PDm */ + }, + { /* 4981 */ + 539, + /* VFMADD132PDr */ + }, + { /* 4982 */ + 527, + /* VFMADD132PSYm */ + }, + { /* 4983 */ + 528, + /* VFMADD132PSYr */ + }, + { /* 4984 */ + 202, + /* VFMADD132PSZ128m */ + }, + { /* 4985 */ + 540, + /* VFMADD132PSZ128mb */ + }, + { /* 4986 */ + 238, + /* VFMADD132PSZ128mbk */ + }, + { /* 4987 */ + 238, + /* VFMADD132PSZ128mbkz */ + }, + { /* 4988 */ + 203, + /* VFMADD132PSZ128mk */ + }, + { /* 4989 */ + 203, + /* VFMADD132PSZ128mkz */ + }, + { /* 4990 */ + 530, + /* VFMADD132PSZ128r */ + }, + { /* 4991 */ + 212, + /* VFMADD132PSZ128rk */ + }, + { /* 4992 */ + 212, + /* VFMADD132PSZ128rkz */ + }, + { /* 4993 */ + 531, + /* VFMADD132PSZ256m */ + }, + { /* 4994 */ + 541, + /* VFMADD132PSZ256mb */ + }, + { /* 4995 */ + 241, + /* VFMADD132PSZ256mbk */ + }, + { /* 4996 */ + 241, + /* VFMADD132PSZ256mbkz */ + }, + { /* 4997 */ + 218, + /* VFMADD132PSZ256mk */ + }, + { /* 4998 */ + 218, + /* VFMADD132PSZ256mkz */ + }, + { /* 4999 */ + 533, + /* VFMADD132PSZ256r */ + }, + { /* 5000 */ + 221, + /* VFMADD132PSZ256rk */ + }, + { /* 5001 */ + 221, + /* VFMADD132PSZ256rkz */ + }, + { /* 5002 */ + 534, + /* VFMADD132PSZm */ + }, + { /* 5003 */ + 542, + /* VFMADD132PSZmb */ + }, + { /* 5004 */ + 244, + /* VFMADD132PSZmbk */ + }, + { /* 5005 */ + 244, + /* VFMADD132PSZmbkz */ + }, + { /* 5006 */ + 227, + /* VFMADD132PSZmk */ + }, + { /* 5007 */ + 227, + /* VFMADD132PSZmkz */ + }, + { /* 5008 */ + 536, + /* VFMADD132PSZr */ + }, + { /* 5009 */ + 543, + /* VFMADD132PSZrb */ + }, + { /* 5010 */ + 247, + /* VFMADD132PSZrbk */ + }, + { /* 5011 */ + 247, + /* VFMADD132PSZrbkz */ + }, + { /* 5012 */ + 233, + /* VFMADD132PSZrk */ + }, + { /* 5013 */ + 233, + /* VFMADD132PSZrkz */ + }, + { /* 5014 */ + 538, + /* VFMADD132PSm */ + }, + { /* 5015 */ + 539, + /* VFMADD132PSr */ + }, + { /* 5016 */ + 0, + /* */ + }, + { /* 5017 */ + 529, + /* VFMADD132SDZm_Int */ + }, + { /* 5018 */ + 208, + /* VFMADD132SDZm_Intk */ + }, + { /* 5019 */ + 208, + /* VFMADD132SDZm_Intkz */ + }, + { /* 5020 */ + 0, + /* */ + }, + { /* 5021 */ + 544, + /* VFMADD132SDZr_Int */ + }, + { /* 5022 */ + 250, + /* VFMADD132SDZr_Intk */ + }, + { /* 5023 */ + 250, + /* VFMADD132SDZr_Intkz */ + }, + { /* 5024 */ + 0, + /* */ + }, + { /* 5025 */ + 545, + /* VFMADD132SDZrb_Int */ + }, + { /* 5026 */ + 253, + /* VFMADD132SDZrb_Intk */ + }, + { /* 5027 */ + 253, + /* VFMADD132SDZrb_Intkz */ + }, + { /* 5028 */ + 538, + /* VFMADD132SDm */ + }, + { /* 5029 */ + 0, + /* */ + }, + { /* 5030 */ + 539, + /* VFMADD132SDr */ + }, + { /* 5031 */ + 0, + /* */ + }, + { /* 5032 */ + 0, + /* */ + }, + { /* 5033 */ + 540, + /* VFMADD132SSZm_Int */ + }, + { /* 5034 */ + 238, + /* VFMADD132SSZm_Intk */ + }, + { /* 5035 */ + 238, + /* VFMADD132SSZm_Intkz */ + }, + { /* 5036 */ + 0, + /* */ + }, + { /* 5037 */ + 546, + /* VFMADD132SSZr_Int */ + }, + { /* 5038 */ + 256, + /* VFMADD132SSZr_Intk */ + }, + { /* 5039 */ + 256, + /* VFMADD132SSZr_Intkz */ + }, + { /* 5040 */ + 0, + /* */ + }, + { /* 5041 */ + 547, + /* VFMADD132SSZrb_Int */ + }, + { /* 5042 */ + 259, + /* VFMADD132SSZrb_Intk */ + }, + { /* 5043 */ + 259, + /* VFMADD132SSZrb_Intkz */ + }, + { /* 5044 */ + 538, + /* VFMADD132SSm */ + }, + { /* 5045 */ + 0, + /* */ + }, + { /* 5046 */ + 539, + /* VFMADD132SSr */ + }, + { /* 5047 */ + 0, + /* */ + }, + { /* 5048 */ + 527, + /* VFMADD213PDYm */ + }, + { /* 5049 */ + 528, + /* VFMADD213PDYr */ + }, + { /* 5050 */ + 202, + /* VFMADD213PDZ128m */ + }, + { /* 5051 */ + 529, + /* VFMADD213PDZ128mb */ + }, + { /* 5052 */ + 208, + /* VFMADD213PDZ128mbk */ + }, + { /* 5053 */ + 208, + /* VFMADD213PDZ128mbkz */ + }, + { /* 5054 */ + 203, + /* VFMADD213PDZ128mk */ + }, + { /* 5055 */ + 203, + /* VFMADD213PDZ128mkz */ + }, + { /* 5056 */ + 530, + /* VFMADD213PDZ128r */ + }, + { /* 5057 */ + 212, + /* VFMADD213PDZ128rk */ + }, + { /* 5058 */ + 212, + /* VFMADD213PDZ128rkz */ + }, + { /* 5059 */ + 531, + /* VFMADD213PDZ256m */ + }, + { /* 5060 */ + 532, + /* VFMADD213PDZ256mb */ + }, + { /* 5061 */ + 216, + /* VFMADD213PDZ256mbk */ + }, + { /* 5062 */ + 216, + /* VFMADD213PDZ256mbkz */ + }, + { /* 5063 */ + 218, + /* VFMADD213PDZ256mk */ + }, + { /* 5064 */ + 218, + /* VFMADD213PDZ256mkz */ + }, + { /* 5065 */ + 533, + /* VFMADD213PDZ256r */ + }, + { /* 5066 */ + 221, + /* VFMADD213PDZ256rk */ + }, + { /* 5067 */ + 221, + /* VFMADD213PDZ256rkz */ + }, + { /* 5068 */ + 534, + /* VFMADD213PDZm */ + }, + { /* 5069 */ + 535, + /* VFMADD213PDZmb */ + }, + { /* 5070 */ + 225, + /* VFMADD213PDZmbk */ + }, + { /* 5071 */ + 225, + /* VFMADD213PDZmbkz */ + }, + { /* 5072 */ + 227, + /* VFMADD213PDZmk */ + }, + { /* 5073 */ + 227, + /* VFMADD213PDZmkz */ + }, + { /* 5074 */ + 536, + /* VFMADD213PDZr */ + }, + { /* 5075 */ + 537, + /* VFMADD213PDZrb */ + }, + { /* 5076 */ + 231, + /* VFMADD213PDZrbk */ + }, + { /* 5077 */ + 231, + /* VFMADD213PDZrbkz */ + }, + { /* 5078 */ + 233, + /* VFMADD213PDZrk */ + }, + { /* 5079 */ + 233, + /* VFMADD213PDZrkz */ + }, + { /* 5080 */ + 538, + /* VFMADD213PDm */ + }, + { /* 5081 */ + 539, + /* VFMADD213PDr */ + }, + { /* 5082 */ + 527, + /* VFMADD213PSYm */ + }, + { /* 5083 */ + 528, + /* VFMADD213PSYr */ + }, + { /* 5084 */ + 202, + /* VFMADD213PSZ128m */ + }, + { /* 5085 */ + 540, + /* VFMADD213PSZ128mb */ + }, + { /* 5086 */ + 238, + /* VFMADD213PSZ128mbk */ + }, + { /* 5087 */ + 238, + /* VFMADD213PSZ128mbkz */ + }, + { /* 5088 */ + 203, + /* VFMADD213PSZ128mk */ + }, + { /* 5089 */ + 203, + /* VFMADD213PSZ128mkz */ + }, + { /* 5090 */ + 530, + /* VFMADD213PSZ128r */ + }, + { /* 5091 */ + 212, + /* VFMADD213PSZ128rk */ + }, + { /* 5092 */ + 212, + /* VFMADD213PSZ128rkz */ + }, + { /* 5093 */ + 531, + /* VFMADD213PSZ256m */ + }, + { /* 5094 */ + 541, + /* VFMADD213PSZ256mb */ + }, + { /* 5095 */ + 241, + /* VFMADD213PSZ256mbk */ + }, + { /* 5096 */ + 241, + /* VFMADD213PSZ256mbkz */ + }, + { /* 5097 */ + 218, + /* VFMADD213PSZ256mk */ + }, + { /* 5098 */ + 218, + /* VFMADD213PSZ256mkz */ + }, + { /* 5099 */ + 533, + /* VFMADD213PSZ256r */ + }, + { /* 5100 */ + 221, + /* VFMADD213PSZ256rk */ + }, + { /* 5101 */ + 221, + /* VFMADD213PSZ256rkz */ + }, + { /* 5102 */ + 534, + /* VFMADD213PSZm */ + }, + { /* 5103 */ + 542, + /* VFMADD213PSZmb */ + }, + { /* 5104 */ + 244, + /* VFMADD213PSZmbk */ + }, + { /* 5105 */ + 244, + /* VFMADD213PSZmbkz */ + }, + { /* 5106 */ + 227, + /* VFMADD213PSZmk */ + }, + { /* 5107 */ + 227, + /* VFMADD213PSZmkz */ + }, + { /* 5108 */ + 536, + /* VFMADD213PSZr */ + }, + { /* 5109 */ + 543, + /* VFMADD213PSZrb */ + }, + { /* 5110 */ + 247, + /* VFMADD213PSZrbk */ + }, + { /* 5111 */ + 247, + /* VFMADD213PSZrbkz */ + }, + { /* 5112 */ + 233, + /* VFMADD213PSZrk */ + }, + { /* 5113 */ + 233, + /* VFMADD213PSZrkz */ + }, + { /* 5114 */ + 538, + /* VFMADD213PSm */ + }, + { /* 5115 */ + 539, + /* VFMADD213PSr */ + }, + { /* 5116 */ + 0, + /* */ + }, + { /* 5117 */ + 529, + /* VFMADD213SDZm_Int */ + }, + { /* 5118 */ + 208, + /* VFMADD213SDZm_Intk */ + }, + { /* 5119 */ + 208, + /* VFMADD213SDZm_Intkz */ + }, + { /* 5120 */ + 0, + /* */ + }, + { /* 5121 */ + 544, + /* VFMADD213SDZr_Int */ + }, + { /* 5122 */ + 250, + /* VFMADD213SDZr_Intk */ + }, + { /* 5123 */ + 250, + /* VFMADD213SDZr_Intkz */ + }, + { /* 5124 */ + 0, + /* */ + }, + { /* 5125 */ + 545, + /* VFMADD213SDZrb_Int */ + }, + { /* 5126 */ + 253, + /* VFMADD213SDZrb_Intk */ + }, + { /* 5127 */ + 253, + /* VFMADD213SDZrb_Intkz */ + }, + { /* 5128 */ + 538, + /* VFMADD213SDm */ + }, + { /* 5129 */ + 0, + /* */ + }, + { /* 5130 */ + 539, + /* VFMADD213SDr */ + }, + { /* 5131 */ + 0, + /* */ + }, + { /* 5132 */ + 0, + /* */ + }, + { /* 5133 */ + 540, + /* VFMADD213SSZm_Int */ + }, + { /* 5134 */ + 238, + /* VFMADD213SSZm_Intk */ + }, + { /* 5135 */ + 238, + /* VFMADD213SSZm_Intkz */ + }, + { /* 5136 */ + 0, + /* */ + }, + { /* 5137 */ + 546, + /* VFMADD213SSZr_Int */ + }, + { /* 5138 */ + 256, + /* VFMADD213SSZr_Intk */ + }, + { /* 5139 */ + 256, + /* VFMADD213SSZr_Intkz */ + }, + { /* 5140 */ + 0, + /* */ + }, + { /* 5141 */ + 547, + /* VFMADD213SSZrb_Int */ + }, + { /* 5142 */ + 259, + /* VFMADD213SSZrb_Intk */ + }, + { /* 5143 */ + 259, + /* VFMADD213SSZrb_Intkz */ + }, + { /* 5144 */ + 538, + /* VFMADD213SSm */ + }, + { /* 5145 */ + 0, + /* */ + }, + { /* 5146 */ + 539, + /* VFMADD213SSr */ + }, + { /* 5147 */ + 0, + /* */ + }, + { /* 5148 */ + 527, + /* VFMADD231PDYm */ + }, + { /* 5149 */ + 528, + /* VFMADD231PDYr */ + }, + { /* 5150 */ + 202, + /* VFMADD231PDZ128m */ + }, + { /* 5151 */ + 529, + /* VFMADD231PDZ128mb */ + }, + { /* 5152 */ + 208, + /* VFMADD231PDZ128mbk */ + }, + { /* 5153 */ + 208, + /* VFMADD231PDZ128mbkz */ + }, + { /* 5154 */ + 203, + /* VFMADD231PDZ128mk */ + }, + { /* 5155 */ + 203, + /* VFMADD231PDZ128mkz */ + }, + { /* 5156 */ + 530, + /* VFMADD231PDZ128r */ + }, + { /* 5157 */ + 212, + /* VFMADD231PDZ128rk */ + }, + { /* 5158 */ + 212, + /* VFMADD231PDZ128rkz */ + }, + { /* 5159 */ + 531, + /* VFMADD231PDZ256m */ + }, + { /* 5160 */ + 532, + /* VFMADD231PDZ256mb */ + }, + { /* 5161 */ + 216, + /* VFMADD231PDZ256mbk */ + }, + { /* 5162 */ + 216, + /* VFMADD231PDZ256mbkz */ + }, + { /* 5163 */ + 218, + /* VFMADD231PDZ256mk */ + }, + { /* 5164 */ + 218, + /* VFMADD231PDZ256mkz */ + }, + { /* 5165 */ + 533, + /* VFMADD231PDZ256r */ + }, + { /* 5166 */ + 221, + /* VFMADD231PDZ256rk */ + }, + { /* 5167 */ + 221, + /* VFMADD231PDZ256rkz */ + }, + { /* 5168 */ + 534, + /* VFMADD231PDZm */ + }, + { /* 5169 */ + 535, + /* VFMADD231PDZmb */ + }, + { /* 5170 */ + 225, + /* VFMADD231PDZmbk */ + }, + { /* 5171 */ + 225, + /* VFMADD231PDZmbkz */ + }, + { /* 5172 */ + 227, + /* VFMADD231PDZmk */ + }, + { /* 5173 */ + 227, + /* VFMADD231PDZmkz */ + }, + { /* 5174 */ + 536, + /* VFMADD231PDZr */ + }, + { /* 5175 */ + 537, + /* VFMADD231PDZrb */ + }, + { /* 5176 */ + 231, + /* VFMADD231PDZrbk */ + }, + { /* 5177 */ + 231, + /* VFMADD231PDZrbkz */ + }, + { /* 5178 */ + 233, + /* VFMADD231PDZrk */ + }, + { /* 5179 */ + 233, + /* VFMADD231PDZrkz */ + }, + { /* 5180 */ + 538, + /* VFMADD231PDm */ + }, + { /* 5181 */ + 539, + /* VFMADD231PDr */ + }, + { /* 5182 */ + 527, + /* VFMADD231PSYm */ + }, + { /* 5183 */ + 528, + /* VFMADD231PSYr */ + }, + { /* 5184 */ + 202, + /* VFMADD231PSZ128m */ + }, + { /* 5185 */ + 540, + /* VFMADD231PSZ128mb */ + }, + { /* 5186 */ + 238, + /* VFMADD231PSZ128mbk */ + }, + { /* 5187 */ + 238, + /* VFMADD231PSZ128mbkz */ + }, + { /* 5188 */ + 203, + /* VFMADD231PSZ128mk */ + }, + { /* 5189 */ + 203, + /* VFMADD231PSZ128mkz */ + }, + { /* 5190 */ + 530, + /* VFMADD231PSZ128r */ + }, + { /* 5191 */ + 212, + /* VFMADD231PSZ128rk */ + }, + { /* 5192 */ + 212, + /* VFMADD231PSZ128rkz */ + }, + { /* 5193 */ + 531, + /* VFMADD231PSZ256m */ + }, + { /* 5194 */ + 541, + /* VFMADD231PSZ256mb */ + }, + { /* 5195 */ + 241, + /* VFMADD231PSZ256mbk */ + }, + { /* 5196 */ + 241, + /* VFMADD231PSZ256mbkz */ + }, + { /* 5197 */ + 218, + /* VFMADD231PSZ256mk */ + }, + { /* 5198 */ + 218, + /* VFMADD231PSZ256mkz */ + }, + { /* 5199 */ + 533, + /* VFMADD231PSZ256r */ + }, + { /* 5200 */ + 221, + /* VFMADD231PSZ256rk */ + }, + { /* 5201 */ + 221, + /* VFMADD231PSZ256rkz */ + }, + { /* 5202 */ + 534, + /* VFMADD231PSZm */ + }, + { /* 5203 */ + 542, + /* VFMADD231PSZmb */ + }, + { /* 5204 */ + 244, + /* VFMADD231PSZmbk */ + }, + { /* 5205 */ + 244, + /* VFMADD231PSZmbkz */ + }, + { /* 5206 */ + 227, + /* VFMADD231PSZmk */ + }, + { /* 5207 */ + 227, + /* VFMADD231PSZmkz */ + }, + { /* 5208 */ + 536, + /* VFMADD231PSZr */ + }, + { /* 5209 */ + 543, + /* VFMADD231PSZrb */ + }, + { /* 5210 */ + 247, + /* VFMADD231PSZrbk */ + }, + { /* 5211 */ + 247, + /* VFMADD231PSZrbkz */ + }, + { /* 5212 */ + 233, + /* VFMADD231PSZrk */ + }, + { /* 5213 */ + 233, + /* VFMADD231PSZrkz */ + }, + { /* 5214 */ + 538, + /* VFMADD231PSm */ + }, + { /* 5215 */ + 539, + /* VFMADD231PSr */ + }, + { /* 5216 */ + 0, + /* */ + }, + { /* 5217 */ + 529, + /* VFMADD231SDZm_Int */ + }, + { /* 5218 */ + 208, + /* VFMADD231SDZm_Intk */ + }, + { /* 5219 */ + 208, + /* VFMADD231SDZm_Intkz */ + }, + { /* 5220 */ + 0, + /* */ + }, + { /* 5221 */ + 544, + /* VFMADD231SDZr_Int */ + }, + { /* 5222 */ + 250, + /* VFMADD231SDZr_Intk */ + }, + { /* 5223 */ + 250, + /* VFMADD231SDZr_Intkz */ + }, + { /* 5224 */ + 0, + /* */ + }, + { /* 5225 */ + 545, + /* VFMADD231SDZrb_Int */ + }, + { /* 5226 */ + 253, + /* VFMADD231SDZrb_Intk */ + }, + { /* 5227 */ + 253, + /* VFMADD231SDZrb_Intkz */ + }, + { /* 5228 */ + 538, + /* VFMADD231SDm */ + }, + { /* 5229 */ + 0, + /* */ + }, + { /* 5230 */ + 539, + /* VFMADD231SDr */ + }, + { /* 5231 */ + 0, + /* */ + }, + { /* 5232 */ + 0, + /* */ + }, + { /* 5233 */ + 540, + /* VFMADD231SSZm_Int */ + }, + { /* 5234 */ + 238, + /* VFMADD231SSZm_Intk */ + }, + { /* 5235 */ + 238, + /* VFMADD231SSZm_Intkz */ + }, + { /* 5236 */ + 0, + /* */ + }, + { /* 5237 */ + 546, + /* VFMADD231SSZr_Int */ + }, + { /* 5238 */ + 256, + /* VFMADD231SSZr_Intk */ + }, + { /* 5239 */ + 256, + /* VFMADD231SSZr_Intkz */ + }, + { /* 5240 */ + 0, + /* */ + }, + { /* 5241 */ + 547, + /* VFMADD231SSZrb_Int */ + }, + { /* 5242 */ + 259, + /* VFMADD231SSZrb_Intk */ + }, + { /* 5243 */ + 259, + /* VFMADD231SSZrb_Intkz */ + }, + { /* 5244 */ + 538, + /* VFMADD231SSm */ + }, + { /* 5245 */ + 0, + /* */ + }, + { /* 5246 */ + 539, + /* VFMADD231SSr */ + }, + { /* 5247 */ + 0, + /* */ + }, + { /* 5248 */ + 301, + /* VFMADDPD4Ymr */ + }, + { /* 5249 */ + 548, + /* VFMADDPD4Yrm */ + }, + { /* 5250 */ + 549, + /* VFMADDPD4Yrr */ + }, + { /* 5251 */ + 302, + /* VFMADDPD4Yrr_REV */ + }, + { /* 5252 */ + 303, + /* VFMADDPD4mr */ + }, + { /* 5253 */ + 550, + /* VFMADDPD4rm */ + }, + { /* 5254 */ + 551, + /* VFMADDPD4rr */ + }, + { /* 5255 */ + 304, + /* VFMADDPD4rr_REV */ + }, + { /* 5256 */ + 301, + /* VFMADDPS4Ymr */ + }, + { /* 5257 */ + 548, + /* VFMADDPS4Yrm */ + }, + { /* 5258 */ + 549, + /* VFMADDPS4Yrr */ + }, + { /* 5259 */ + 302, + /* VFMADDPS4Yrr_REV */ + }, + { /* 5260 */ + 303, + /* VFMADDPS4mr */ + }, + { /* 5261 */ + 550, + /* VFMADDPS4rm */ + }, + { /* 5262 */ + 551, + /* VFMADDPS4rr */ + }, + { /* 5263 */ + 304, + /* VFMADDPS4rr_REV */ + }, + { /* 5264 */ + 303, + /* VFMADDSD4mr */ + }, + { /* 5265 */ + 0, + /* */ + }, + { /* 5266 */ + 550, + /* VFMADDSD4rm */ + }, + { /* 5267 */ + 0, + /* */ + }, + { /* 5268 */ + 551, + /* VFMADDSD4rr */ + }, + { /* 5269 */ + 0, + /* */ + }, + { /* 5270 */ + 0, + /* */ + }, + { /* 5271 */ + 304, + /* VFMADDSD4rr_REV */ + }, + { /* 5272 */ + 303, + /* VFMADDSS4mr */ + }, + { /* 5273 */ + 0, + /* */ + }, + { /* 5274 */ + 550, + /* VFMADDSS4rm */ + }, + { /* 5275 */ + 0, + /* */ + }, + { /* 5276 */ + 551, + /* VFMADDSS4rr */ + }, + { /* 5277 */ + 0, + /* */ + }, + { /* 5278 */ + 0, + /* */ + }, + { /* 5279 */ + 304, + /* VFMADDSS4rr_REV */ + }, + { /* 5280 */ + 527, + /* VFMADDSUB132PDYm */ + }, + { /* 5281 */ + 528, + /* VFMADDSUB132PDYr */ + }, + { /* 5282 */ + 202, + /* VFMADDSUB132PDZ128m */ + }, + { /* 5283 */ + 529, + /* VFMADDSUB132PDZ128mb */ + }, + { /* 5284 */ + 208, + /* VFMADDSUB132PDZ128mbk */ + }, + { /* 5285 */ + 208, + /* VFMADDSUB132PDZ128mbkz */ + }, + { /* 5286 */ + 203, + /* VFMADDSUB132PDZ128mk */ + }, + { /* 5287 */ + 203, + /* VFMADDSUB132PDZ128mkz */ + }, + { /* 5288 */ + 530, + /* VFMADDSUB132PDZ128r */ + }, + { /* 5289 */ + 212, + /* VFMADDSUB132PDZ128rk */ + }, + { /* 5290 */ + 212, + /* VFMADDSUB132PDZ128rkz */ + }, + { /* 5291 */ + 531, + /* VFMADDSUB132PDZ256m */ + }, + { /* 5292 */ + 532, + /* VFMADDSUB132PDZ256mb */ + }, + { /* 5293 */ + 216, + /* VFMADDSUB132PDZ256mbk */ + }, + { /* 5294 */ + 216, + /* VFMADDSUB132PDZ256mbkz */ + }, + { /* 5295 */ + 218, + /* VFMADDSUB132PDZ256mk */ + }, + { /* 5296 */ + 218, + /* VFMADDSUB132PDZ256mkz */ + }, + { /* 5297 */ + 533, + /* VFMADDSUB132PDZ256r */ + }, + { /* 5298 */ + 221, + /* VFMADDSUB132PDZ256rk */ + }, + { /* 5299 */ + 221, + /* VFMADDSUB132PDZ256rkz */ + }, + { /* 5300 */ + 534, + /* VFMADDSUB132PDZm */ + }, + { /* 5301 */ + 535, + /* VFMADDSUB132PDZmb */ + }, + { /* 5302 */ + 225, + /* VFMADDSUB132PDZmbk */ + }, + { /* 5303 */ + 225, + /* VFMADDSUB132PDZmbkz */ + }, + { /* 5304 */ + 227, + /* VFMADDSUB132PDZmk */ + }, + { /* 5305 */ + 227, + /* VFMADDSUB132PDZmkz */ + }, + { /* 5306 */ + 536, + /* VFMADDSUB132PDZr */ + }, + { /* 5307 */ + 537, + /* VFMADDSUB132PDZrb */ + }, + { /* 5308 */ + 231, + /* VFMADDSUB132PDZrbk */ + }, + { /* 5309 */ + 231, + /* VFMADDSUB132PDZrbkz */ + }, + { /* 5310 */ + 233, + /* VFMADDSUB132PDZrk */ + }, + { /* 5311 */ + 233, + /* VFMADDSUB132PDZrkz */ + }, + { /* 5312 */ + 538, + /* VFMADDSUB132PDm */ + }, + { /* 5313 */ + 539, + /* VFMADDSUB132PDr */ + }, + { /* 5314 */ + 527, + /* VFMADDSUB132PSYm */ + }, + { /* 5315 */ + 528, + /* VFMADDSUB132PSYr */ + }, + { /* 5316 */ + 202, + /* VFMADDSUB132PSZ128m */ + }, + { /* 5317 */ + 540, + /* VFMADDSUB132PSZ128mb */ + }, + { /* 5318 */ + 238, + /* VFMADDSUB132PSZ128mbk */ + }, + { /* 5319 */ + 238, + /* VFMADDSUB132PSZ128mbkz */ + }, + { /* 5320 */ + 203, + /* VFMADDSUB132PSZ128mk */ + }, + { /* 5321 */ + 203, + /* VFMADDSUB132PSZ128mkz */ + }, + { /* 5322 */ + 530, + /* VFMADDSUB132PSZ128r */ + }, + { /* 5323 */ + 212, + /* VFMADDSUB132PSZ128rk */ + }, + { /* 5324 */ + 212, + /* VFMADDSUB132PSZ128rkz */ + }, + { /* 5325 */ + 531, + /* VFMADDSUB132PSZ256m */ + }, + { /* 5326 */ + 541, + /* VFMADDSUB132PSZ256mb */ + }, + { /* 5327 */ + 241, + /* VFMADDSUB132PSZ256mbk */ + }, + { /* 5328 */ + 241, + /* VFMADDSUB132PSZ256mbkz */ + }, + { /* 5329 */ + 218, + /* VFMADDSUB132PSZ256mk */ + }, + { /* 5330 */ + 218, + /* VFMADDSUB132PSZ256mkz */ + }, + { /* 5331 */ + 533, + /* VFMADDSUB132PSZ256r */ + }, + { /* 5332 */ + 221, + /* VFMADDSUB132PSZ256rk */ + }, + { /* 5333 */ + 221, + /* VFMADDSUB132PSZ256rkz */ + }, + { /* 5334 */ + 534, + /* VFMADDSUB132PSZm */ + }, + { /* 5335 */ + 542, + /* VFMADDSUB132PSZmb */ + }, + { /* 5336 */ + 244, + /* VFMADDSUB132PSZmbk */ + }, + { /* 5337 */ + 244, + /* VFMADDSUB132PSZmbkz */ + }, + { /* 5338 */ + 227, + /* VFMADDSUB132PSZmk */ + }, + { /* 5339 */ + 227, + /* VFMADDSUB132PSZmkz */ + }, + { /* 5340 */ + 536, + /* VFMADDSUB132PSZr */ + }, + { /* 5341 */ + 543, + /* VFMADDSUB132PSZrb */ + }, + { /* 5342 */ + 247, + /* VFMADDSUB132PSZrbk */ + }, + { /* 5343 */ + 247, + /* VFMADDSUB132PSZrbkz */ + }, + { /* 5344 */ + 233, + /* VFMADDSUB132PSZrk */ + }, + { /* 5345 */ + 233, + /* VFMADDSUB132PSZrkz */ + }, + { /* 5346 */ + 538, + /* VFMADDSUB132PSm */ + }, + { /* 5347 */ + 539, + /* VFMADDSUB132PSr */ + }, + { /* 5348 */ + 527, + /* VFMADDSUB213PDYm */ + }, + { /* 5349 */ + 528, + /* VFMADDSUB213PDYr */ + }, + { /* 5350 */ + 202, + /* VFMADDSUB213PDZ128m */ + }, + { /* 5351 */ + 529, + /* VFMADDSUB213PDZ128mb */ + }, + { /* 5352 */ + 208, + /* VFMADDSUB213PDZ128mbk */ + }, + { /* 5353 */ + 208, + /* VFMADDSUB213PDZ128mbkz */ + }, + { /* 5354 */ + 203, + /* VFMADDSUB213PDZ128mk */ + }, + { /* 5355 */ + 203, + /* VFMADDSUB213PDZ128mkz */ + }, + { /* 5356 */ + 530, + /* VFMADDSUB213PDZ128r */ + }, + { /* 5357 */ + 212, + /* VFMADDSUB213PDZ128rk */ + }, + { /* 5358 */ + 212, + /* VFMADDSUB213PDZ128rkz */ + }, + { /* 5359 */ + 531, + /* VFMADDSUB213PDZ256m */ + }, + { /* 5360 */ + 532, + /* VFMADDSUB213PDZ256mb */ + }, + { /* 5361 */ + 216, + /* VFMADDSUB213PDZ256mbk */ + }, + { /* 5362 */ + 216, + /* VFMADDSUB213PDZ256mbkz */ + }, + { /* 5363 */ + 218, + /* VFMADDSUB213PDZ256mk */ + }, + { /* 5364 */ + 218, + /* VFMADDSUB213PDZ256mkz */ + }, + { /* 5365 */ + 533, + /* VFMADDSUB213PDZ256r */ + }, + { /* 5366 */ + 221, + /* VFMADDSUB213PDZ256rk */ + }, + { /* 5367 */ + 221, + /* VFMADDSUB213PDZ256rkz */ + }, + { /* 5368 */ + 534, + /* VFMADDSUB213PDZm */ + }, + { /* 5369 */ + 535, + /* VFMADDSUB213PDZmb */ + }, + { /* 5370 */ + 225, + /* VFMADDSUB213PDZmbk */ + }, + { /* 5371 */ + 225, + /* VFMADDSUB213PDZmbkz */ + }, + { /* 5372 */ + 227, + /* VFMADDSUB213PDZmk */ + }, + { /* 5373 */ + 227, + /* VFMADDSUB213PDZmkz */ + }, + { /* 5374 */ + 536, + /* VFMADDSUB213PDZr */ + }, + { /* 5375 */ + 537, + /* VFMADDSUB213PDZrb */ + }, + { /* 5376 */ + 231, + /* VFMADDSUB213PDZrbk */ + }, + { /* 5377 */ + 231, + /* VFMADDSUB213PDZrbkz */ + }, + { /* 5378 */ + 233, + /* VFMADDSUB213PDZrk */ + }, + { /* 5379 */ + 233, + /* VFMADDSUB213PDZrkz */ + }, + { /* 5380 */ + 538, + /* VFMADDSUB213PDm */ + }, + { /* 5381 */ + 539, + /* VFMADDSUB213PDr */ + }, + { /* 5382 */ + 527, + /* VFMADDSUB213PSYm */ + }, + { /* 5383 */ + 528, + /* VFMADDSUB213PSYr */ + }, + { /* 5384 */ + 202, + /* VFMADDSUB213PSZ128m */ + }, + { /* 5385 */ + 540, + /* VFMADDSUB213PSZ128mb */ + }, + { /* 5386 */ + 238, + /* VFMADDSUB213PSZ128mbk */ + }, + { /* 5387 */ + 238, + /* VFMADDSUB213PSZ128mbkz */ + }, + { /* 5388 */ + 203, + /* VFMADDSUB213PSZ128mk */ + }, + { /* 5389 */ + 203, + /* VFMADDSUB213PSZ128mkz */ + }, + { /* 5390 */ + 530, + /* VFMADDSUB213PSZ128r */ + }, + { /* 5391 */ + 212, + /* VFMADDSUB213PSZ128rk */ + }, + { /* 5392 */ + 212, + /* VFMADDSUB213PSZ128rkz */ + }, + { /* 5393 */ + 531, + /* VFMADDSUB213PSZ256m */ + }, + { /* 5394 */ + 541, + /* VFMADDSUB213PSZ256mb */ + }, + { /* 5395 */ + 241, + /* VFMADDSUB213PSZ256mbk */ + }, + { /* 5396 */ + 241, + /* VFMADDSUB213PSZ256mbkz */ + }, + { /* 5397 */ + 218, + /* VFMADDSUB213PSZ256mk */ + }, + { /* 5398 */ + 218, + /* VFMADDSUB213PSZ256mkz */ + }, + { /* 5399 */ + 533, + /* VFMADDSUB213PSZ256r */ + }, + { /* 5400 */ + 221, + /* VFMADDSUB213PSZ256rk */ + }, + { /* 5401 */ + 221, + /* VFMADDSUB213PSZ256rkz */ + }, + { /* 5402 */ + 534, + /* VFMADDSUB213PSZm */ + }, + { /* 5403 */ + 542, + /* VFMADDSUB213PSZmb */ + }, + { /* 5404 */ + 244, + /* VFMADDSUB213PSZmbk */ + }, + { /* 5405 */ + 244, + /* VFMADDSUB213PSZmbkz */ + }, + { /* 5406 */ + 227, + /* VFMADDSUB213PSZmk */ + }, + { /* 5407 */ + 227, + /* VFMADDSUB213PSZmkz */ + }, + { /* 5408 */ + 536, + /* VFMADDSUB213PSZr */ + }, + { /* 5409 */ + 543, + /* VFMADDSUB213PSZrb */ + }, + { /* 5410 */ + 247, + /* VFMADDSUB213PSZrbk */ + }, + { /* 5411 */ + 247, + /* VFMADDSUB213PSZrbkz */ + }, + { /* 5412 */ + 233, + /* VFMADDSUB213PSZrk */ + }, + { /* 5413 */ + 233, + /* VFMADDSUB213PSZrkz */ + }, + { /* 5414 */ + 538, + /* VFMADDSUB213PSm */ + }, + { /* 5415 */ + 539, + /* VFMADDSUB213PSr */ + }, + { /* 5416 */ + 527, + /* VFMADDSUB231PDYm */ + }, + { /* 5417 */ + 528, + /* VFMADDSUB231PDYr */ + }, + { /* 5418 */ + 202, + /* VFMADDSUB231PDZ128m */ + }, + { /* 5419 */ + 529, + /* VFMADDSUB231PDZ128mb */ + }, + { /* 5420 */ + 208, + /* VFMADDSUB231PDZ128mbk */ + }, + { /* 5421 */ + 208, + /* VFMADDSUB231PDZ128mbkz */ + }, + { /* 5422 */ + 203, + /* VFMADDSUB231PDZ128mk */ + }, + { /* 5423 */ + 203, + /* VFMADDSUB231PDZ128mkz */ + }, + { /* 5424 */ + 530, + /* VFMADDSUB231PDZ128r */ + }, + { /* 5425 */ + 212, + /* VFMADDSUB231PDZ128rk */ + }, + { /* 5426 */ + 212, + /* VFMADDSUB231PDZ128rkz */ + }, + { /* 5427 */ + 531, + /* VFMADDSUB231PDZ256m */ + }, + { /* 5428 */ + 532, + /* VFMADDSUB231PDZ256mb */ + }, + { /* 5429 */ + 216, + /* VFMADDSUB231PDZ256mbk */ + }, + { /* 5430 */ + 216, + /* VFMADDSUB231PDZ256mbkz */ + }, + { /* 5431 */ + 218, + /* VFMADDSUB231PDZ256mk */ + }, + { /* 5432 */ + 218, + /* VFMADDSUB231PDZ256mkz */ + }, + { /* 5433 */ + 533, + /* VFMADDSUB231PDZ256r */ + }, + { /* 5434 */ + 221, + /* VFMADDSUB231PDZ256rk */ + }, + { /* 5435 */ + 221, + /* VFMADDSUB231PDZ256rkz */ + }, + { /* 5436 */ + 534, + /* VFMADDSUB231PDZm */ + }, + { /* 5437 */ + 535, + /* VFMADDSUB231PDZmb */ + }, + { /* 5438 */ + 225, + /* VFMADDSUB231PDZmbk */ + }, + { /* 5439 */ + 225, + /* VFMADDSUB231PDZmbkz */ + }, + { /* 5440 */ + 227, + /* VFMADDSUB231PDZmk */ + }, + { /* 5441 */ + 227, + /* VFMADDSUB231PDZmkz */ + }, + { /* 5442 */ + 536, + /* VFMADDSUB231PDZr */ + }, + { /* 5443 */ + 537, + /* VFMADDSUB231PDZrb */ + }, + { /* 5444 */ + 231, + /* VFMADDSUB231PDZrbk */ + }, + { /* 5445 */ + 231, + /* VFMADDSUB231PDZrbkz */ + }, + { /* 5446 */ + 233, + /* VFMADDSUB231PDZrk */ + }, + { /* 5447 */ + 233, + /* VFMADDSUB231PDZrkz */ + }, + { /* 5448 */ + 538, + /* VFMADDSUB231PDm */ + }, + { /* 5449 */ + 539, + /* VFMADDSUB231PDr */ + }, + { /* 5450 */ + 527, + /* VFMADDSUB231PSYm */ + }, + { /* 5451 */ + 528, + /* VFMADDSUB231PSYr */ + }, + { /* 5452 */ + 202, + /* VFMADDSUB231PSZ128m */ + }, + { /* 5453 */ + 540, + /* VFMADDSUB231PSZ128mb */ + }, + { /* 5454 */ + 238, + /* VFMADDSUB231PSZ128mbk */ + }, + { /* 5455 */ + 238, + /* VFMADDSUB231PSZ128mbkz */ + }, + { /* 5456 */ + 203, + /* VFMADDSUB231PSZ128mk */ + }, + { /* 5457 */ + 203, + /* VFMADDSUB231PSZ128mkz */ + }, + { /* 5458 */ + 530, + /* VFMADDSUB231PSZ128r */ + }, + { /* 5459 */ + 212, + /* VFMADDSUB231PSZ128rk */ + }, + { /* 5460 */ + 212, + /* VFMADDSUB231PSZ128rkz */ + }, + { /* 5461 */ + 531, + /* VFMADDSUB231PSZ256m */ + }, + { /* 5462 */ + 541, + /* VFMADDSUB231PSZ256mb */ + }, + { /* 5463 */ + 241, + /* VFMADDSUB231PSZ256mbk */ + }, + { /* 5464 */ + 241, + /* VFMADDSUB231PSZ256mbkz */ + }, + { /* 5465 */ + 218, + /* VFMADDSUB231PSZ256mk */ + }, + { /* 5466 */ + 218, + /* VFMADDSUB231PSZ256mkz */ + }, + { /* 5467 */ + 533, + /* VFMADDSUB231PSZ256r */ + }, + { /* 5468 */ + 221, + /* VFMADDSUB231PSZ256rk */ + }, + { /* 5469 */ + 221, + /* VFMADDSUB231PSZ256rkz */ + }, + { /* 5470 */ + 534, + /* VFMADDSUB231PSZm */ + }, + { /* 5471 */ + 542, + /* VFMADDSUB231PSZmb */ + }, + { /* 5472 */ + 244, + /* VFMADDSUB231PSZmbk */ + }, + { /* 5473 */ + 244, + /* VFMADDSUB231PSZmbkz */ + }, + { /* 5474 */ + 227, + /* VFMADDSUB231PSZmk */ + }, + { /* 5475 */ + 227, + /* VFMADDSUB231PSZmkz */ + }, + { /* 5476 */ + 536, + /* VFMADDSUB231PSZr */ + }, + { /* 5477 */ + 543, + /* VFMADDSUB231PSZrb */ + }, + { /* 5478 */ + 247, + /* VFMADDSUB231PSZrbk */ + }, + { /* 5479 */ + 247, + /* VFMADDSUB231PSZrbkz */ + }, + { /* 5480 */ + 233, + /* VFMADDSUB231PSZrk */ + }, + { /* 5481 */ + 233, + /* VFMADDSUB231PSZrkz */ + }, + { /* 5482 */ + 538, + /* VFMADDSUB231PSm */ + }, + { /* 5483 */ + 539, + /* VFMADDSUB231PSr */ + }, + { /* 5484 */ + 301, + /* VFMADDSUBPD4Ymr */ + }, + { /* 5485 */ + 548, + /* VFMADDSUBPD4Yrm */ + }, + { /* 5486 */ + 549, + /* VFMADDSUBPD4Yrr */ + }, + { /* 5487 */ + 302, + /* VFMADDSUBPD4Yrr_REV */ + }, + { /* 5488 */ + 303, + /* VFMADDSUBPD4mr */ + }, + { /* 5489 */ + 550, + /* VFMADDSUBPD4rm */ + }, + { /* 5490 */ + 551, + /* VFMADDSUBPD4rr */ + }, + { /* 5491 */ + 304, + /* VFMADDSUBPD4rr_REV */ + }, + { /* 5492 */ + 301, + /* VFMADDSUBPS4Ymr */ + }, + { /* 5493 */ + 548, + /* VFMADDSUBPS4Yrm */ + }, + { /* 5494 */ + 549, + /* VFMADDSUBPS4Yrr */ + }, + { /* 5495 */ + 302, + /* VFMADDSUBPS4Yrr_REV */ + }, + { /* 5496 */ + 303, + /* VFMADDSUBPS4mr */ + }, + { /* 5497 */ + 550, + /* VFMADDSUBPS4rm */ + }, + { /* 5498 */ + 551, + /* VFMADDSUBPS4rr */ + }, + { /* 5499 */ + 304, + /* VFMADDSUBPS4rr_REV */ + }, + { /* 5500 */ + 527, + /* VFMSUB132PDYm */ + }, + { /* 5501 */ + 528, + /* VFMSUB132PDYr */ + }, + { /* 5502 */ + 202, + /* VFMSUB132PDZ128m */ + }, + { /* 5503 */ + 529, + /* VFMSUB132PDZ128mb */ + }, + { /* 5504 */ + 208, + /* VFMSUB132PDZ128mbk */ + }, + { /* 5505 */ + 208, + /* VFMSUB132PDZ128mbkz */ + }, + { /* 5506 */ + 203, + /* VFMSUB132PDZ128mk */ + }, + { /* 5507 */ + 203, + /* VFMSUB132PDZ128mkz */ + }, + { /* 5508 */ + 530, + /* VFMSUB132PDZ128r */ + }, + { /* 5509 */ + 212, + /* VFMSUB132PDZ128rk */ + }, + { /* 5510 */ + 212, + /* VFMSUB132PDZ128rkz */ + }, + { /* 5511 */ + 531, + /* VFMSUB132PDZ256m */ + }, + { /* 5512 */ + 532, + /* VFMSUB132PDZ256mb */ + }, + { /* 5513 */ + 216, + /* VFMSUB132PDZ256mbk */ + }, + { /* 5514 */ + 216, + /* VFMSUB132PDZ256mbkz */ + }, + { /* 5515 */ + 218, + /* VFMSUB132PDZ256mk */ + }, + { /* 5516 */ + 218, + /* VFMSUB132PDZ256mkz */ + }, + { /* 5517 */ + 533, + /* VFMSUB132PDZ256r */ + }, + { /* 5518 */ + 221, + /* VFMSUB132PDZ256rk */ + }, + { /* 5519 */ + 221, + /* VFMSUB132PDZ256rkz */ + }, + { /* 5520 */ + 534, + /* VFMSUB132PDZm */ + }, + { /* 5521 */ + 535, + /* VFMSUB132PDZmb */ + }, + { /* 5522 */ + 225, + /* VFMSUB132PDZmbk */ + }, + { /* 5523 */ + 225, + /* VFMSUB132PDZmbkz */ + }, + { /* 5524 */ + 227, + /* VFMSUB132PDZmk */ + }, + { /* 5525 */ + 227, + /* VFMSUB132PDZmkz */ + }, + { /* 5526 */ + 536, + /* VFMSUB132PDZr */ + }, + { /* 5527 */ + 537, + /* VFMSUB132PDZrb */ + }, + { /* 5528 */ + 231, + /* VFMSUB132PDZrbk */ + }, + { /* 5529 */ + 231, + /* VFMSUB132PDZrbkz */ + }, + { /* 5530 */ + 233, + /* VFMSUB132PDZrk */ + }, + { /* 5531 */ + 233, + /* VFMSUB132PDZrkz */ + }, + { /* 5532 */ + 538, + /* VFMSUB132PDm */ + }, + { /* 5533 */ + 539, + /* VFMSUB132PDr */ + }, + { /* 5534 */ + 527, + /* VFMSUB132PSYm */ + }, + { /* 5535 */ + 528, + /* VFMSUB132PSYr */ + }, + { /* 5536 */ + 202, + /* VFMSUB132PSZ128m */ + }, + { /* 5537 */ + 540, + /* VFMSUB132PSZ128mb */ + }, + { /* 5538 */ + 238, + /* VFMSUB132PSZ128mbk */ + }, + { /* 5539 */ + 238, + /* VFMSUB132PSZ128mbkz */ + }, + { /* 5540 */ + 203, + /* VFMSUB132PSZ128mk */ + }, + { /* 5541 */ + 203, + /* VFMSUB132PSZ128mkz */ + }, + { /* 5542 */ + 530, + /* VFMSUB132PSZ128r */ + }, + { /* 5543 */ + 212, + /* VFMSUB132PSZ128rk */ + }, + { /* 5544 */ + 212, + /* VFMSUB132PSZ128rkz */ + }, + { /* 5545 */ + 531, + /* VFMSUB132PSZ256m */ + }, + { /* 5546 */ + 541, + /* VFMSUB132PSZ256mb */ + }, + { /* 5547 */ + 241, + /* VFMSUB132PSZ256mbk */ + }, + { /* 5548 */ + 241, + /* VFMSUB132PSZ256mbkz */ + }, + { /* 5549 */ + 218, + /* VFMSUB132PSZ256mk */ + }, + { /* 5550 */ + 218, + /* VFMSUB132PSZ256mkz */ + }, + { /* 5551 */ + 533, + /* VFMSUB132PSZ256r */ + }, + { /* 5552 */ + 221, + /* VFMSUB132PSZ256rk */ + }, + { /* 5553 */ + 221, + /* VFMSUB132PSZ256rkz */ + }, + { /* 5554 */ + 534, + /* VFMSUB132PSZm */ + }, + { /* 5555 */ + 542, + /* VFMSUB132PSZmb */ + }, + { /* 5556 */ + 244, + /* VFMSUB132PSZmbk */ + }, + { /* 5557 */ + 244, + /* VFMSUB132PSZmbkz */ + }, + { /* 5558 */ + 227, + /* VFMSUB132PSZmk */ + }, + { /* 5559 */ + 227, + /* VFMSUB132PSZmkz */ + }, + { /* 5560 */ + 536, + /* VFMSUB132PSZr */ + }, + { /* 5561 */ + 543, + /* VFMSUB132PSZrb */ + }, + { /* 5562 */ + 247, + /* VFMSUB132PSZrbk */ + }, + { /* 5563 */ + 247, + /* VFMSUB132PSZrbkz */ + }, + { /* 5564 */ + 233, + /* VFMSUB132PSZrk */ + }, + { /* 5565 */ + 233, + /* VFMSUB132PSZrkz */ + }, + { /* 5566 */ + 538, + /* VFMSUB132PSm */ + }, + { /* 5567 */ + 539, + /* VFMSUB132PSr */ + }, + { /* 5568 */ + 0, + /* */ + }, + { /* 5569 */ + 529, + /* VFMSUB132SDZm_Int */ + }, + { /* 5570 */ + 208, + /* VFMSUB132SDZm_Intk */ + }, + { /* 5571 */ + 208, + /* VFMSUB132SDZm_Intkz */ + }, + { /* 5572 */ + 0, + /* */ + }, + { /* 5573 */ + 544, + /* VFMSUB132SDZr_Int */ + }, + { /* 5574 */ + 250, + /* VFMSUB132SDZr_Intk */ + }, + { /* 5575 */ + 250, + /* VFMSUB132SDZr_Intkz */ + }, + { /* 5576 */ + 0, + /* */ + }, + { /* 5577 */ + 545, + /* VFMSUB132SDZrb_Int */ + }, + { /* 5578 */ + 253, + /* VFMSUB132SDZrb_Intk */ + }, + { /* 5579 */ + 253, + /* VFMSUB132SDZrb_Intkz */ + }, + { /* 5580 */ + 538, + /* VFMSUB132SDm */ + }, + { /* 5581 */ + 0, + /* */ + }, + { /* 5582 */ + 539, + /* VFMSUB132SDr */ + }, + { /* 5583 */ + 0, + /* */ + }, + { /* 5584 */ + 0, + /* */ + }, + { /* 5585 */ + 540, + /* VFMSUB132SSZm_Int */ + }, + { /* 5586 */ + 238, + /* VFMSUB132SSZm_Intk */ + }, + { /* 5587 */ + 238, + /* VFMSUB132SSZm_Intkz */ + }, + { /* 5588 */ + 0, + /* */ + }, + { /* 5589 */ + 546, + /* VFMSUB132SSZr_Int */ + }, + { /* 5590 */ + 256, + /* VFMSUB132SSZr_Intk */ + }, + { /* 5591 */ + 256, + /* VFMSUB132SSZr_Intkz */ + }, + { /* 5592 */ + 0, + /* */ + }, + { /* 5593 */ + 547, + /* VFMSUB132SSZrb_Int */ + }, + { /* 5594 */ + 259, + /* VFMSUB132SSZrb_Intk */ + }, + { /* 5595 */ + 259, + /* VFMSUB132SSZrb_Intkz */ + }, + { /* 5596 */ + 538, + /* VFMSUB132SSm */ + }, + { /* 5597 */ + 0, + /* */ + }, + { /* 5598 */ + 539, + /* VFMSUB132SSr */ + }, + { /* 5599 */ + 0, + /* */ + }, + { /* 5600 */ + 527, + /* VFMSUB213PDYm */ + }, + { /* 5601 */ + 528, + /* VFMSUB213PDYr */ + }, + { /* 5602 */ + 202, + /* VFMSUB213PDZ128m */ + }, + { /* 5603 */ + 529, + /* VFMSUB213PDZ128mb */ + }, + { /* 5604 */ + 208, + /* VFMSUB213PDZ128mbk */ + }, + { /* 5605 */ + 208, + /* VFMSUB213PDZ128mbkz */ + }, + { /* 5606 */ + 203, + /* VFMSUB213PDZ128mk */ + }, + { /* 5607 */ + 203, + /* VFMSUB213PDZ128mkz */ + }, + { /* 5608 */ + 530, + /* VFMSUB213PDZ128r */ + }, + { /* 5609 */ + 212, + /* VFMSUB213PDZ128rk */ + }, + { /* 5610 */ + 212, + /* VFMSUB213PDZ128rkz */ + }, + { /* 5611 */ + 531, + /* VFMSUB213PDZ256m */ + }, + { /* 5612 */ + 532, + /* VFMSUB213PDZ256mb */ + }, + { /* 5613 */ + 216, + /* VFMSUB213PDZ256mbk */ + }, + { /* 5614 */ + 216, + /* VFMSUB213PDZ256mbkz */ + }, + { /* 5615 */ + 218, + /* VFMSUB213PDZ256mk */ + }, + { /* 5616 */ + 218, + /* VFMSUB213PDZ256mkz */ + }, + { /* 5617 */ + 533, + /* VFMSUB213PDZ256r */ + }, + { /* 5618 */ + 221, + /* VFMSUB213PDZ256rk */ + }, + { /* 5619 */ + 221, + /* VFMSUB213PDZ256rkz */ + }, + { /* 5620 */ + 534, + /* VFMSUB213PDZm */ + }, + { /* 5621 */ + 535, + /* VFMSUB213PDZmb */ + }, + { /* 5622 */ + 225, + /* VFMSUB213PDZmbk */ + }, + { /* 5623 */ + 225, + /* VFMSUB213PDZmbkz */ + }, + { /* 5624 */ + 227, + /* VFMSUB213PDZmk */ + }, + { /* 5625 */ + 227, + /* VFMSUB213PDZmkz */ + }, + { /* 5626 */ + 536, + /* VFMSUB213PDZr */ + }, + { /* 5627 */ + 537, + /* VFMSUB213PDZrb */ + }, + { /* 5628 */ + 231, + /* VFMSUB213PDZrbk */ + }, + { /* 5629 */ + 231, + /* VFMSUB213PDZrbkz */ + }, + { /* 5630 */ + 233, + /* VFMSUB213PDZrk */ + }, + { /* 5631 */ + 233, + /* VFMSUB213PDZrkz */ + }, + { /* 5632 */ + 538, + /* VFMSUB213PDm */ + }, + { /* 5633 */ + 539, + /* VFMSUB213PDr */ + }, + { /* 5634 */ + 527, + /* VFMSUB213PSYm */ + }, + { /* 5635 */ + 528, + /* VFMSUB213PSYr */ + }, + { /* 5636 */ + 202, + /* VFMSUB213PSZ128m */ + }, + { /* 5637 */ + 540, + /* VFMSUB213PSZ128mb */ + }, + { /* 5638 */ + 238, + /* VFMSUB213PSZ128mbk */ + }, + { /* 5639 */ + 238, + /* VFMSUB213PSZ128mbkz */ + }, + { /* 5640 */ + 203, + /* VFMSUB213PSZ128mk */ + }, + { /* 5641 */ + 203, + /* VFMSUB213PSZ128mkz */ + }, + { /* 5642 */ + 530, + /* VFMSUB213PSZ128r */ + }, + { /* 5643 */ + 212, + /* VFMSUB213PSZ128rk */ + }, + { /* 5644 */ + 212, + /* VFMSUB213PSZ128rkz */ + }, + { /* 5645 */ + 531, + /* VFMSUB213PSZ256m */ + }, + { /* 5646 */ + 541, + /* VFMSUB213PSZ256mb */ + }, + { /* 5647 */ + 241, + /* VFMSUB213PSZ256mbk */ + }, + { /* 5648 */ + 241, + /* VFMSUB213PSZ256mbkz */ + }, + { /* 5649 */ + 218, + /* VFMSUB213PSZ256mk */ + }, + { /* 5650 */ + 218, + /* VFMSUB213PSZ256mkz */ + }, + { /* 5651 */ + 533, + /* VFMSUB213PSZ256r */ + }, + { /* 5652 */ + 221, + /* VFMSUB213PSZ256rk */ + }, + { /* 5653 */ + 221, + /* VFMSUB213PSZ256rkz */ + }, + { /* 5654 */ + 534, + /* VFMSUB213PSZm */ + }, + { /* 5655 */ + 542, + /* VFMSUB213PSZmb */ + }, + { /* 5656 */ + 244, + /* VFMSUB213PSZmbk */ + }, + { /* 5657 */ + 244, + /* VFMSUB213PSZmbkz */ + }, + { /* 5658 */ + 227, + /* VFMSUB213PSZmk */ + }, + { /* 5659 */ + 227, + /* VFMSUB213PSZmkz */ + }, + { /* 5660 */ + 536, + /* VFMSUB213PSZr */ + }, + { /* 5661 */ + 543, + /* VFMSUB213PSZrb */ + }, + { /* 5662 */ + 247, + /* VFMSUB213PSZrbk */ + }, + { /* 5663 */ + 247, + /* VFMSUB213PSZrbkz */ + }, + { /* 5664 */ + 233, + /* VFMSUB213PSZrk */ + }, + { /* 5665 */ + 233, + /* VFMSUB213PSZrkz */ + }, + { /* 5666 */ + 538, + /* VFMSUB213PSm */ + }, + { /* 5667 */ + 539, + /* VFMSUB213PSr */ + }, + { /* 5668 */ + 0, + /* */ + }, + { /* 5669 */ + 529, + /* VFMSUB213SDZm_Int */ + }, + { /* 5670 */ + 208, + /* VFMSUB213SDZm_Intk */ + }, + { /* 5671 */ + 208, + /* VFMSUB213SDZm_Intkz */ + }, + { /* 5672 */ + 0, + /* */ + }, + { /* 5673 */ + 544, + /* VFMSUB213SDZr_Int */ + }, + { /* 5674 */ + 250, + /* VFMSUB213SDZr_Intk */ + }, + { /* 5675 */ + 250, + /* VFMSUB213SDZr_Intkz */ + }, + { /* 5676 */ + 0, + /* */ + }, + { /* 5677 */ + 545, + /* VFMSUB213SDZrb_Int */ + }, + { /* 5678 */ + 253, + /* VFMSUB213SDZrb_Intk */ + }, + { /* 5679 */ + 253, + /* VFMSUB213SDZrb_Intkz */ + }, + { /* 5680 */ + 538, + /* VFMSUB213SDm */ + }, + { /* 5681 */ + 0, + /* */ + }, + { /* 5682 */ + 539, + /* VFMSUB213SDr */ + }, + { /* 5683 */ + 0, + /* */ + }, + { /* 5684 */ + 0, + /* */ + }, + { /* 5685 */ + 540, + /* VFMSUB213SSZm_Int */ + }, + { /* 5686 */ + 238, + /* VFMSUB213SSZm_Intk */ + }, + { /* 5687 */ + 238, + /* VFMSUB213SSZm_Intkz */ + }, + { /* 5688 */ + 0, + /* */ + }, + { /* 5689 */ + 546, + /* VFMSUB213SSZr_Int */ + }, + { /* 5690 */ + 256, + /* VFMSUB213SSZr_Intk */ + }, + { /* 5691 */ + 256, + /* VFMSUB213SSZr_Intkz */ + }, + { /* 5692 */ + 0, + /* */ + }, + { /* 5693 */ + 547, + /* VFMSUB213SSZrb_Int */ + }, + { /* 5694 */ + 259, + /* VFMSUB213SSZrb_Intk */ + }, + { /* 5695 */ + 259, + /* VFMSUB213SSZrb_Intkz */ + }, + { /* 5696 */ + 538, + /* VFMSUB213SSm */ + }, + { /* 5697 */ + 0, + /* */ + }, + { /* 5698 */ + 539, + /* VFMSUB213SSr */ + }, + { /* 5699 */ + 0, + /* */ + }, + { /* 5700 */ + 527, + /* VFMSUB231PDYm */ + }, + { /* 5701 */ + 528, + /* VFMSUB231PDYr */ + }, + { /* 5702 */ + 202, + /* VFMSUB231PDZ128m */ + }, + { /* 5703 */ + 529, + /* VFMSUB231PDZ128mb */ + }, + { /* 5704 */ + 208, + /* VFMSUB231PDZ128mbk */ + }, + { /* 5705 */ + 208, + /* VFMSUB231PDZ128mbkz */ + }, + { /* 5706 */ + 203, + /* VFMSUB231PDZ128mk */ + }, + { /* 5707 */ + 203, + /* VFMSUB231PDZ128mkz */ + }, + { /* 5708 */ + 530, + /* VFMSUB231PDZ128r */ + }, + { /* 5709 */ + 212, + /* VFMSUB231PDZ128rk */ + }, + { /* 5710 */ + 212, + /* VFMSUB231PDZ128rkz */ + }, + { /* 5711 */ + 531, + /* VFMSUB231PDZ256m */ + }, + { /* 5712 */ + 532, + /* VFMSUB231PDZ256mb */ + }, + { /* 5713 */ + 216, + /* VFMSUB231PDZ256mbk */ + }, + { /* 5714 */ + 216, + /* VFMSUB231PDZ256mbkz */ + }, + { /* 5715 */ + 218, + /* VFMSUB231PDZ256mk */ + }, + { /* 5716 */ + 218, + /* VFMSUB231PDZ256mkz */ + }, + { /* 5717 */ + 533, + /* VFMSUB231PDZ256r */ + }, + { /* 5718 */ + 221, + /* VFMSUB231PDZ256rk */ + }, + { /* 5719 */ + 221, + /* VFMSUB231PDZ256rkz */ + }, + { /* 5720 */ + 534, + /* VFMSUB231PDZm */ + }, + { /* 5721 */ + 535, + /* VFMSUB231PDZmb */ + }, + { /* 5722 */ + 225, + /* VFMSUB231PDZmbk */ + }, + { /* 5723 */ + 225, + /* VFMSUB231PDZmbkz */ + }, + { /* 5724 */ + 227, + /* VFMSUB231PDZmk */ + }, + { /* 5725 */ + 227, + /* VFMSUB231PDZmkz */ + }, + { /* 5726 */ + 536, + /* VFMSUB231PDZr */ + }, + { /* 5727 */ + 537, + /* VFMSUB231PDZrb */ + }, + { /* 5728 */ + 231, + /* VFMSUB231PDZrbk */ + }, + { /* 5729 */ + 231, + /* VFMSUB231PDZrbkz */ + }, + { /* 5730 */ + 233, + /* VFMSUB231PDZrk */ + }, + { /* 5731 */ + 233, + /* VFMSUB231PDZrkz */ + }, + { /* 5732 */ + 538, + /* VFMSUB231PDm */ + }, + { /* 5733 */ + 539, + /* VFMSUB231PDr */ + }, + { /* 5734 */ + 527, + /* VFMSUB231PSYm */ + }, + { /* 5735 */ + 528, + /* VFMSUB231PSYr */ + }, + { /* 5736 */ + 202, + /* VFMSUB231PSZ128m */ + }, + { /* 5737 */ + 540, + /* VFMSUB231PSZ128mb */ + }, + { /* 5738 */ + 238, + /* VFMSUB231PSZ128mbk */ + }, + { /* 5739 */ + 238, + /* VFMSUB231PSZ128mbkz */ + }, + { /* 5740 */ + 203, + /* VFMSUB231PSZ128mk */ + }, + { /* 5741 */ + 203, + /* VFMSUB231PSZ128mkz */ + }, + { /* 5742 */ + 530, + /* VFMSUB231PSZ128r */ + }, + { /* 5743 */ + 212, + /* VFMSUB231PSZ128rk */ + }, + { /* 5744 */ + 212, + /* VFMSUB231PSZ128rkz */ + }, + { /* 5745 */ + 531, + /* VFMSUB231PSZ256m */ + }, + { /* 5746 */ + 541, + /* VFMSUB231PSZ256mb */ + }, + { /* 5747 */ + 241, + /* VFMSUB231PSZ256mbk */ + }, + { /* 5748 */ + 241, + /* VFMSUB231PSZ256mbkz */ + }, + { /* 5749 */ + 218, + /* VFMSUB231PSZ256mk */ + }, + { /* 5750 */ + 218, + /* VFMSUB231PSZ256mkz */ + }, + { /* 5751 */ + 533, + /* VFMSUB231PSZ256r */ + }, + { /* 5752 */ + 221, + /* VFMSUB231PSZ256rk */ + }, + { /* 5753 */ + 221, + /* VFMSUB231PSZ256rkz */ + }, + { /* 5754 */ + 534, + /* VFMSUB231PSZm */ + }, + { /* 5755 */ + 542, + /* VFMSUB231PSZmb */ + }, + { /* 5756 */ + 244, + /* VFMSUB231PSZmbk */ + }, + { /* 5757 */ + 244, + /* VFMSUB231PSZmbkz */ + }, + { /* 5758 */ + 227, + /* VFMSUB231PSZmk */ + }, + { /* 5759 */ + 227, + /* VFMSUB231PSZmkz */ + }, + { /* 5760 */ + 536, + /* VFMSUB231PSZr */ + }, + { /* 5761 */ + 543, + /* VFMSUB231PSZrb */ + }, + { /* 5762 */ + 247, + /* VFMSUB231PSZrbk */ + }, + { /* 5763 */ + 247, + /* VFMSUB231PSZrbkz */ + }, + { /* 5764 */ + 233, + /* VFMSUB231PSZrk */ + }, + { /* 5765 */ + 233, + /* VFMSUB231PSZrkz */ + }, + { /* 5766 */ + 538, + /* VFMSUB231PSm */ + }, + { /* 5767 */ + 539, + /* VFMSUB231PSr */ + }, + { /* 5768 */ + 0, + /* */ + }, + { /* 5769 */ + 529, + /* VFMSUB231SDZm_Int */ + }, + { /* 5770 */ + 208, + /* VFMSUB231SDZm_Intk */ + }, + { /* 5771 */ + 208, + /* VFMSUB231SDZm_Intkz */ + }, + { /* 5772 */ + 0, + /* */ + }, + { /* 5773 */ + 544, + /* VFMSUB231SDZr_Int */ + }, + { /* 5774 */ + 250, + /* VFMSUB231SDZr_Intk */ + }, + { /* 5775 */ + 250, + /* VFMSUB231SDZr_Intkz */ + }, + { /* 5776 */ + 0, + /* */ + }, + { /* 5777 */ + 545, + /* VFMSUB231SDZrb_Int */ + }, + { /* 5778 */ + 253, + /* VFMSUB231SDZrb_Intk */ + }, + { /* 5779 */ + 253, + /* VFMSUB231SDZrb_Intkz */ + }, + { /* 5780 */ + 538, + /* VFMSUB231SDm */ + }, + { /* 5781 */ + 0, + /* */ + }, + { /* 5782 */ + 539, + /* VFMSUB231SDr */ + }, + { /* 5783 */ + 0, + /* */ + }, + { /* 5784 */ + 0, + /* */ + }, + { /* 5785 */ + 540, + /* VFMSUB231SSZm_Int */ + }, + { /* 5786 */ + 238, + /* VFMSUB231SSZm_Intk */ + }, + { /* 5787 */ + 238, + /* VFMSUB231SSZm_Intkz */ + }, + { /* 5788 */ + 0, + /* */ + }, + { /* 5789 */ + 546, + /* VFMSUB231SSZr_Int */ + }, + { /* 5790 */ + 256, + /* VFMSUB231SSZr_Intk */ + }, + { /* 5791 */ + 256, + /* VFMSUB231SSZr_Intkz */ + }, + { /* 5792 */ + 0, + /* */ + }, + { /* 5793 */ + 547, + /* VFMSUB231SSZrb_Int */ + }, + { /* 5794 */ + 259, + /* VFMSUB231SSZrb_Intk */ + }, + { /* 5795 */ + 259, + /* VFMSUB231SSZrb_Intkz */ + }, + { /* 5796 */ + 538, + /* VFMSUB231SSm */ + }, + { /* 5797 */ + 0, + /* */ + }, + { /* 5798 */ + 539, + /* VFMSUB231SSr */ + }, + { /* 5799 */ + 0, + /* */ + }, + { /* 5800 */ + 527, + /* VFMSUBADD132PDYm */ + }, + { /* 5801 */ + 528, + /* VFMSUBADD132PDYr */ + }, + { /* 5802 */ + 202, + /* VFMSUBADD132PDZ128m */ + }, + { /* 5803 */ + 529, + /* VFMSUBADD132PDZ128mb */ + }, + { /* 5804 */ + 208, + /* VFMSUBADD132PDZ128mbk */ + }, + { /* 5805 */ + 208, + /* VFMSUBADD132PDZ128mbkz */ + }, + { /* 5806 */ + 203, + /* VFMSUBADD132PDZ128mk */ + }, + { /* 5807 */ + 203, + /* VFMSUBADD132PDZ128mkz */ + }, + { /* 5808 */ + 530, + /* VFMSUBADD132PDZ128r */ + }, + { /* 5809 */ + 212, + /* VFMSUBADD132PDZ128rk */ + }, + { /* 5810 */ + 212, + /* VFMSUBADD132PDZ128rkz */ + }, + { /* 5811 */ + 531, + /* VFMSUBADD132PDZ256m */ + }, + { /* 5812 */ + 532, + /* VFMSUBADD132PDZ256mb */ + }, + { /* 5813 */ + 216, + /* VFMSUBADD132PDZ256mbk */ + }, + { /* 5814 */ + 216, + /* VFMSUBADD132PDZ256mbkz */ + }, + { /* 5815 */ + 218, + /* VFMSUBADD132PDZ256mk */ + }, + { /* 5816 */ + 218, + /* VFMSUBADD132PDZ256mkz */ + }, + { /* 5817 */ + 533, + /* VFMSUBADD132PDZ256r */ + }, + { /* 5818 */ + 221, + /* VFMSUBADD132PDZ256rk */ + }, + { /* 5819 */ + 221, + /* VFMSUBADD132PDZ256rkz */ + }, + { /* 5820 */ + 534, + /* VFMSUBADD132PDZm */ + }, + { /* 5821 */ + 535, + /* VFMSUBADD132PDZmb */ + }, + { /* 5822 */ + 225, + /* VFMSUBADD132PDZmbk */ + }, + { /* 5823 */ + 225, + /* VFMSUBADD132PDZmbkz */ + }, + { /* 5824 */ + 227, + /* VFMSUBADD132PDZmk */ + }, + { /* 5825 */ + 227, + /* VFMSUBADD132PDZmkz */ + }, + { /* 5826 */ + 536, + /* VFMSUBADD132PDZr */ + }, + { /* 5827 */ + 537, + /* VFMSUBADD132PDZrb */ + }, + { /* 5828 */ + 231, + /* VFMSUBADD132PDZrbk */ + }, + { /* 5829 */ + 231, + /* VFMSUBADD132PDZrbkz */ + }, + { /* 5830 */ + 233, + /* VFMSUBADD132PDZrk */ + }, + { /* 5831 */ + 233, + /* VFMSUBADD132PDZrkz */ + }, + { /* 5832 */ + 538, + /* VFMSUBADD132PDm */ + }, + { /* 5833 */ + 539, + /* VFMSUBADD132PDr */ + }, + { /* 5834 */ + 527, + /* VFMSUBADD132PSYm */ + }, + { /* 5835 */ + 528, + /* VFMSUBADD132PSYr */ + }, + { /* 5836 */ + 202, + /* VFMSUBADD132PSZ128m */ + }, + { /* 5837 */ + 540, + /* VFMSUBADD132PSZ128mb */ + }, + { /* 5838 */ + 238, + /* VFMSUBADD132PSZ128mbk */ + }, + { /* 5839 */ + 238, + /* VFMSUBADD132PSZ128mbkz */ + }, + { /* 5840 */ + 203, + /* VFMSUBADD132PSZ128mk */ + }, + { /* 5841 */ + 203, + /* VFMSUBADD132PSZ128mkz */ + }, + { /* 5842 */ + 530, + /* VFMSUBADD132PSZ128r */ + }, + { /* 5843 */ + 212, + /* VFMSUBADD132PSZ128rk */ + }, + { /* 5844 */ + 212, + /* VFMSUBADD132PSZ128rkz */ + }, + { /* 5845 */ + 531, + /* VFMSUBADD132PSZ256m */ + }, + { /* 5846 */ + 541, + /* VFMSUBADD132PSZ256mb */ + }, + { /* 5847 */ + 241, + /* VFMSUBADD132PSZ256mbk */ + }, + { /* 5848 */ + 241, + /* VFMSUBADD132PSZ256mbkz */ + }, + { /* 5849 */ + 218, + /* VFMSUBADD132PSZ256mk */ + }, + { /* 5850 */ + 218, + /* VFMSUBADD132PSZ256mkz */ + }, + { /* 5851 */ + 533, + /* VFMSUBADD132PSZ256r */ + }, + { /* 5852 */ + 221, + /* VFMSUBADD132PSZ256rk */ + }, + { /* 5853 */ + 221, + /* VFMSUBADD132PSZ256rkz */ + }, + { /* 5854 */ + 534, + /* VFMSUBADD132PSZm */ + }, + { /* 5855 */ + 542, + /* VFMSUBADD132PSZmb */ + }, + { /* 5856 */ + 244, + /* VFMSUBADD132PSZmbk */ + }, + { /* 5857 */ + 244, + /* VFMSUBADD132PSZmbkz */ + }, + { /* 5858 */ + 227, + /* VFMSUBADD132PSZmk */ + }, + { /* 5859 */ + 227, + /* VFMSUBADD132PSZmkz */ + }, + { /* 5860 */ + 536, + /* VFMSUBADD132PSZr */ + }, + { /* 5861 */ + 543, + /* VFMSUBADD132PSZrb */ + }, + { /* 5862 */ + 247, + /* VFMSUBADD132PSZrbk */ + }, + { /* 5863 */ + 247, + /* VFMSUBADD132PSZrbkz */ + }, + { /* 5864 */ + 233, + /* VFMSUBADD132PSZrk */ + }, + { /* 5865 */ + 233, + /* VFMSUBADD132PSZrkz */ + }, + { /* 5866 */ + 538, + /* VFMSUBADD132PSm */ + }, + { /* 5867 */ + 539, + /* VFMSUBADD132PSr */ + }, + { /* 5868 */ + 527, + /* VFMSUBADD213PDYm */ + }, + { /* 5869 */ + 528, + /* VFMSUBADD213PDYr */ + }, + { /* 5870 */ + 202, + /* VFMSUBADD213PDZ128m */ + }, + { /* 5871 */ + 529, + /* VFMSUBADD213PDZ128mb */ + }, + { /* 5872 */ + 208, + /* VFMSUBADD213PDZ128mbk */ + }, + { /* 5873 */ + 208, + /* VFMSUBADD213PDZ128mbkz */ + }, + { /* 5874 */ + 203, + /* VFMSUBADD213PDZ128mk */ + }, + { /* 5875 */ + 203, + /* VFMSUBADD213PDZ128mkz */ + }, + { /* 5876 */ + 530, + /* VFMSUBADD213PDZ128r */ + }, + { /* 5877 */ + 212, + /* VFMSUBADD213PDZ128rk */ + }, + { /* 5878 */ + 212, + /* VFMSUBADD213PDZ128rkz */ + }, + { /* 5879 */ + 531, + /* VFMSUBADD213PDZ256m */ + }, + { /* 5880 */ + 532, + /* VFMSUBADD213PDZ256mb */ + }, + { /* 5881 */ + 216, + /* VFMSUBADD213PDZ256mbk */ + }, + { /* 5882 */ + 216, + /* VFMSUBADD213PDZ256mbkz */ + }, + { /* 5883 */ + 218, + /* VFMSUBADD213PDZ256mk */ + }, + { /* 5884 */ + 218, + /* VFMSUBADD213PDZ256mkz */ + }, + { /* 5885 */ + 533, + /* VFMSUBADD213PDZ256r */ + }, + { /* 5886 */ + 221, + /* VFMSUBADD213PDZ256rk */ + }, + { /* 5887 */ + 221, + /* VFMSUBADD213PDZ256rkz */ + }, + { /* 5888 */ + 534, + /* VFMSUBADD213PDZm */ + }, + { /* 5889 */ + 535, + /* VFMSUBADD213PDZmb */ + }, + { /* 5890 */ + 225, + /* VFMSUBADD213PDZmbk */ + }, + { /* 5891 */ + 225, + /* VFMSUBADD213PDZmbkz */ + }, + { /* 5892 */ + 227, + /* VFMSUBADD213PDZmk */ + }, + { /* 5893 */ + 227, + /* VFMSUBADD213PDZmkz */ + }, + { /* 5894 */ + 536, + /* VFMSUBADD213PDZr */ + }, + { /* 5895 */ + 537, + /* VFMSUBADD213PDZrb */ + }, + { /* 5896 */ + 231, + /* VFMSUBADD213PDZrbk */ + }, + { /* 5897 */ + 231, + /* VFMSUBADD213PDZrbkz */ + }, + { /* 5898 */ + 233, + /* VFMSUBADD213PDZrk */ + }, + { /* 5899 */ + 233, + /* VFMSUBADD213PDZrkz */ + }, + { /* 5900 */ + 538, + /* VFMSUBADD213PDm */ + }, + { /* 5901 */ + 539, + /* VFMSUBADD213PDr */ + }, + { /* 5902 */ + 527, + /* VFMSUBADD213PSYm */ + }, + { /* 5903 */ + 528, + /* VFMSUBADD213PSYr */ + }, + { /* 5904 */ + 202, + /* VFMSUBADD213PSZ128m */ + }, + { /* 5905 */ + 540, + /* VFMSUBADD213PSZ128mb */ + }, + { /* 5906 */ + 238, + /* VFMSUBADD213PSZ128mbk */ + }, + { /* 5907 */ + 238, + /* VFMSUBADD213PSZ128mbkz */ + }, + { /* 5908 */ + 203, + /* VFMSUBADD213PSZ128mk */ + }, + { /* 5909 */ + 203, + /* VFMSUBADD213PSZ128mkz */ + }, + { /* 5910 */ + 530, + /* VFMSUBADD213PSZ128r */ + }, + { /* 5911 */ + 212, + /* VFMSUBADD213PSZ128rk */ + }, + { /* 5912 */ + 212, + /* VFMSUBADD213PSZ128rkz */ + }, + { /* 5913 */ + 531, + /* VFMSUBADD213PSZ256m */ + }, + { /* 5914 */ + 541, + /* VFMSUBADD213PSZ256mb */ + }, + { /* 5915 */ + 241, + /* VFMSUBADD213PSZ256mbk */ + }, + { /* 5916 */ + 241, + /* VFMSUBADD213PSZ256mbkz */ + }, + { /* 5917 */ + 218, + /* VFMSUBADD213PSZ256mk */ + }, + { /* 5918 */ + 218, + /* VFMSUBADD213PSZ256mkz */ + }, + { /* 5919 */ + 533, + /* VFMSUBADD213PSZ256r */ + }, + { /* 5920 */ + 221, + /* VFMSUBADD213PSZ256rk */ + }, + { /* 5921 */ + 221, + /* VFMSUBADD213PSZ256rkz */ + }, + { /* 5922 */ + 534, + /* VFMSUBADD213PSZm */ + }, + { /* 5923 */ + 542, + /* VFMSUBADD213PSZmb */ + }, + { /* 5924 */ + 244, + /* VFMSUBADD213PSZmbk */ + }, + { /* 5925 */ + 244, + /* VFMSUBADD213PSZmbkz */ + }, + { /* 5926 */ + 227, + /* VFMSUBADD213PSZmk */ + }, + { /* 5927 */ + 227, + /* VFMSUBADD213PSZmkz */ + }, + { /* 5928 */ + 536, + /* VFMSUBADD213PSZr */ + }, + { /* 5929 */ + 543, + /* VFMSUBADD213PSZrb */ + }, + { /* 5930 */ + 247, + /* VFMSUBADD213PSZrbk */ + }, + { /* 5931 */ + 247, + /* VFMSUBADD213PSZrbkz */ + }, + { /* 5932 */ + 233, + /* VFMSUBADD213PSZrk */ + }, + { /* 5933 */ + 233, + /* VFMSUBADD213PSZrkz */ + }, + { /* 5934 */ + 538, + /* VFMSUBADD213PSm */ + }, + { /* 5935 */ + 539, + /* VFMSUBADD213PSr */ + }, + { /* 5936 */ + 527, + /* VFMSUBADD231PDYm */ + }, + { /* 5937 */ + 528, + /* VFMSUBADD231PDYr */ + }, + { /* 5938 */ + 202, + /* VFMSUBADD231PDZ128m */ + }, + { /* 5939 */ + 529, + /* VFMSUBADD231PDZ128mb */ + }, + { /* 5940 */ + 208, + /* VFMSUBADD231PDZ128mbk */ + }, + { /* 5941 */ + 208, + /* VFMSUBADD231PDZ128mbkz */ + }, + { /* 5942 */ + 203, + /* VFMSUBADD231PDZ128mk */ + }, + { /* 5943 */ + 203, + /* VFMSUBADD231PDZ128mkz */ + }, + { /* 5944 */ + 530, + /* VFMSUBADD231PDZ128r */ + }, + { /* 5945 */ + 212, + /* VFMSUBADD231PDZ128rk */ + }, + { /* 5946 */ + 212, + /* VFMSUBADD231PDZ128rkz */ + }, + { /* 5947 */ + 531, + /* VFMSUBADD231PDZ256m */ + }, + { /* 5948 */ + 532, + /* VFMSUBADD231PDZ256mb */ + }, + { /* 5949 */ + 216, + /* VFMSUBADD231PDZ256mbk */ + }, + { /* 5950 */ + 216, + /* VFMSUBADD231PDZ256mbkz */ + }, + { /* 5951 */ + 218, + /* VFMSUBADD231PDZ256mk */ + }, + { /* 5952 */ + 218, + /* VFMSUBADD231PDZ256mkz */ + }, + { /* 5953 */ + 533, + /* VFMSUBADD231PDZ256r */ + }, + { /* 5954 */ + 221, + /* VFMSUBADD231PDZ256rk */ + }, + { /* 5955 */ + 221, + /* VFMSUBADD231PDZ256rkz */ + }, + { /* 5956 */ + 534, + /* VFMSUBADD231PDZm */ + }, + { /* 5957 */ + 535, + /* VFMSUBADD231PDZmb */ + }, + { /* 5958 */ + 225, + /* VFMSUBADD231PDZmbk */ + }, + { /* 5959 */ + 225, + /* VFMSUBADD231PDZmbkz */ + }, + { /* 5960 */ + 227, + /* VFMSUBADD231PDZmk */ + }, + { /* 5961 */ + 227, + /* VFMSUBADD231PDZmkz */ + }, + { /* 5962 */ + 536, + /* VFMSUBADD231PDZr */ + }, + { /* 5963 */ + 537, + /* VFMSUBADD231PDZrb */ + }, + { /* 5964 */ + 231, + /* VFMSUBADD231PDZrbk */ + }, + { /* 5965 */ + 231, + /* VFMSUBADD231PDZrbkz */ + }, + { /* 5966 */ + 233, + /* VFMSUBADD231PDZrk */ + }, + { /* 5967 */ + 233, + /* VFMSUBADD231PDZrkz */ + }, + { /* 5968 */ + 538, + /* VFMSUBADD231PDm */ + }, + { /* 5969 */ + 539, + /* VFMSUBADD231PDr */ + }, + { /* 5970 */ + 527, + /* VFMSUBADD231PSYm */ + }, + { /* 5971 */ + 528, + /* VFMSUBADD231PSYr */ + }, + { /* 5972 */ + 202, + /* VFMSUBADD231PSZ128m */ + }, + { /* 5973 */ + 540, + /* VFMSUBADD231PSZ128mb */ + }, + { /* 5974 */ + 238, + /* VFMSUBADD231PSZ128mbk */ + }, + { /* 5975 */ + 238, + /* VFMSUBADD231PSZ128mbkz */ + }, + { /* 5976 */ + 203, + /* VFMSUBADD231PSZ128mk */ + }, + { /* 5977 */ + 203, + /* VFMSUBADD231PSZ128mkz */ + }, + { /* 5978 */ + 530, + /* VFMSUBADD231PSZ128r */ + }, + { /* 5979 */ + 212, + /* VFMSUBADD231PSZ128rk */ + }, + { /* 5980 */ + 212, + /* VFMSUBADD231PSZ128rkz */ + }, + { /* 5981 */ + 531, + /* VFMSUBADD231PSZ256m */ + }, + { /* 5982 */ + 541, + /* VFMSUBADD231PSZ256mb */ + }, + { /* 5983 */ + 241, + /* VFMSUBADD231PSZ256mbk */ + }, + { /* 5984 */ + 241, + /* VFMSUBADD231PSZ256mbkz */ + }, + { /* 5985 */ + 218, + /* VFMSUBADD231PSZ256mk */ + }, + { /* 5986 */ + 218, + /* VFMSUBADD231PSZ256mkz */ + }, + { /* 5987 */ + 533, + /* VFMSUBADD231PSZ256r */ + }, + { /* 5988 */ + 221, + /* VFMSUBADD231PSZ256rk */ + }, + { /* 5989 */ + 221, + /* VFMSUBADD231PSZ256rkz */ + }, + { /* 5990 */ + 534, + /* VFMSUBADD231PSZm */ + }, + { /* 5991 */ + 542, + /* VFMSUBADD231PSZmb */ + }, + { /* 5992 */ + 244, + /* VFMSUBADD231PSZmbk */ + }, + { /* 5993 */ + 244, + /* VFMSUBADD231PSZmbkz */ + }, + { /* 5994 */ + 227, + /* VFMSUBADD231PSZmk */ + }, + { /* 5995 */ + 227, + /* VFMSUBADD231PSZmkz */ + }, + { /* 5996 */ + 536, + /* VFMSUBADD231PSZr */ + }, + { /* 5997 */ + 543, + /* VFMSUBADD231PSZrb */ + }, + { /* 5998 */ + 247, + /* VFMSUBADD231PSZrbk */ + }, + { /* 5999 */ + 247, + /* VFMSUBADD231PSZrbkz */ + }, + { /* 6000 */ + 233, + /* VFMSUBADD231PSZrk */ + }, + { /* 6001 */ + 233, + /* VFMSUBADD231PSZrkz */ + }, + { /* 6002 */ + 538, + /* VFMSUBADD231PSm */ + }, + { /* 6003 */ + 539, + /* VFMSUBADD231PSr */ + }, + { /* 6004 */ + 301, + /* VFMSUBADDPD4Ymr */ + }, + { /* 6005 */ + 548, + /* VFMSUBADDPD4Yrm */ + }, + { /* 6006 */ + 549, + /* VFMSUBADDPD4Yrr */ + }, + { /* 6007 */ + 302, + /* VFMSUBADDPD4Yrr_REV */ + }, + { /* 6008 */ + 303, + /* VFMSUBADDPD4mr */ + }, + { /* 6009 */ + 550, + /* VFMSUBADDPD4rm */ + }, + { /* 6010 */ + 551, + /* VFMSUBADDPD4rr */ + }, + { /* 6011 */ + 304, + /* VFMSUBADDPD4rr_REV */ + }, + { /* 6012 */ + 301, + /* VFMSUBADDPS4Ymr */ + }, + { /* 6013 */ + 548, + /* VFMSUBADDPS4Yrm */ + }, + { /* 6014 */ + 549, + /* VFMSUBADDPS4Yrr */ + }, + { /* 6015 */ + 302, + /* VFMSUBADDPS4Yrr_REV */ + }, + { /* 6016 */ + 303, + /* VFMSUBADDPS4mr */ + }, + { /* 6017 */ + 550, + /* VFMSUBADDPS4rm */ + }, + { /* 6018 */ + 551, + /* VFMSUBADDPS4rr */ + }, + { /* 6019 */ + 304, + /* VFMSUBADDPS4rr_REV */ + }, + { /* 6020 */ + 301, + /* VFMSUBPD4Ymr */ + }, + { /* 6021 */ + 548, + /* VFMSUBPD4Yrm */ + }, + { /* 6022 */ + 549, + /* VFMSUBPD4Yrr */ + }, + { /* 6023 */ + 302, + /* VFMSUBPD4Yrr_REV */ + }, + { /* 6024 */ + 303, + /* VFMSUBPD4mr */ + }, + { /* 6025 */ + 550, + /* VFMSUBPD4rm */ + }, + { /* 6026 */ + 551, + /* VFMSUBPD4rr */ + }, + { /* 6027 */ + 304, + /* VFMSUBPD4rr_REV */ + }, + { /* 6028 */ + 301, + /* VFMSUBPS4Ymr */ + }, + { /* 6029 */ + 548, + /* VFMSUBPS4Yrm */ + }, + { /* 6030 */ + 549, + /* VFMSUBPS4Yrr */ + }, + { /* 6031 */ + 302, + /* VFMSUBPS4Yrr_REV */ + }, + { /* 6032 */ + 303, + /* VFMSUBPS4mr */ + }, + { /* 6033 */ + 550, + /* VFMSUBPS4rm */ + }, + { /* 6034 */ + 551, + /* VFMSUBPS4rr */ + }, + { /* 6035 */ + 304, + /* VFMSUBPS4rr_REV */ + }, + { /* 6036 */ + 303, + /* VFMSUBSD4mr */ + }, + { /* 6037 */ + 0, + /* */ + }, + { /* 6038 */ + 550, + /* VFMSUBSD4rm */ + }, + { /* 6039 */ + 0, + /* */ + }, + { /* 6040 */ + 551, + /* VFMSUBSD4rr */ + }, + { /* 6041 */ + 0, + /* */ + }, + { /* 6042 */ + 0, + /* */ + }, + { /* 6043 */ + 304, + /* VFMSUBSD4rr_REV */ + }, + { /* 6044 */ + 303, + /* VFMSUBSS4mr */ + }, + { /* 6045 */ + 0, + /* */ + }, + { /* 6046 */ + 550, + /* VFMSUBSS4rm */ + }, + { /* 6047 */ + 0, + /* */ + }, + { /* 6048 */ + 551, + /* VFMSUBSS4rr */ + }, + { /* 6049 */ + 0, + /* */ + }, + { /* 6050 */ + 0, + /* */ + }, + { /* 6051 */ + 304, + /* VFMSUBSS4rr_REV */ + }, + { /* 6052 */ + 527, + /* VFNMADD132PDYm */ + }, + { /* 6053 */ + 528, + /* VFNMADD132PDYr */ + }, + { /* 6054 */ + 202, + /* VFNMADD132PDZ128m */ + }, + { /* 6055 */ + 529, + /* VFNMADD132PDZ128mb */ + }, + { /* 6056 */ + 208, + /* VFNMADD132PDZ128mbk */ + }, + { /* 6057 */ + 208, + /* VFNMADD132PDZ128mbkz */ + }, + { /* 6058 */ + 203, + /* VFNMADD132PDZ128mk */ + }, + { /* 6059 */ + 203, + /* VFNMADD132PDZ128mkz */ + }, + { /* 6060 */ + 530, + /* VFNMADD132PDZ128r */ + }, + { /* 6061 */ + 212, + /* VFNMADD132PDZ128rk */ + }, + { /* 6062 */ + 212, + /* VFNMADD132PDZ128rkz */ + }, + { /* 6063 */ + 531, + /* VFNMADD132PDZ256m */ + }, + { /* 6064 */ + 532, + /* VFNMADD132PDZ256mb */ + }, + { /* 6065 */ + 216, + /* VFNMADD132PDZ256mbk */ + }, + { /* 6066 */ + 216, + /* VFNMADD132PDZ256mbkz */ + }, + { /* 6067 */ + 218, + /* VFNMADD132PDZ256mk */ + }, + { /* 6068 */ + 218, + /* VFNMADD132PDZ256mkz */ + }, + { /* 6069 */ + 533, + /* VFNMADD132PDZ256r */ + }, + { /* 6070 */ + 221, + /* VFNMADD132PDZ256rk */ + }, + { /* 6071 */ + 221, + /* VFNMADD132PDZ256rkz */ + }, + { /* 6072 */ + 534, + /* VFNMADD132PDZm */ + }, + { /* 6073 */ + 535, + /* VFNMADD132PDZmb */ + }, + { /* 6074 */ + 225, + /* VFNMADD132PDZmbk */ + }, + { /* 6075 */ + 225, + /* VFNMADD132PDZmbkz */ + }, + { /* 6076 */ + 227, + /* VFNMADD132PDZmk */ + }, + { /* 6077 */ + 227, + /* VFNMADD132PDZmkz */ + }, + { /* 6078 */ + 536, + /* VFNMADD132PDZr */ + }, + { /* 6079 */ + 537, + /* VFNMADD132PDZrb */ + }, + { /* 6080 */ + 231, + /* VFNMADD132PDZrbk */ + }, + { /* 6081 */ + 231, + /* VFNMADD132PDZrbkz */ + }, + { /* 6082 */ + 233, + /* VFNMADD132PDZrk */ + }, + { /* 6083 */ + 233, + /* VFNMADD132PDZrkz */ + }, + { /* 6084 */ + 538, + /* VFNMADD132PDm */ + }, + { /* 6085 */ + 539, + /* VFNMADD132PDr */ + }, + { /* 6086 */ + 527, + /* VFNMADD132PSYm */ + }, + { /* 6087 */ + 528, + /* VFNMADD132PSYr */ + }, + { /* 6088 */ + 202, + /* VFNMADD132PSZ128m */ + }, + { /* 6089 */ + 540, + /* VFNMADD132PSZ128mb */ + }, + { /* 6090 */ + 238, + /* VFNMADD132PSZ128mbk */ + }, + { /* 6091 */ + 238, + /* VFNMADD132PSZ128mbkz */ + }, + { /* 6092 */ + 203, + /* VFNMADD132PSZ128mk */ + }, + { /* 6093 */ + 203, + /* VFNMADD132PSZ128mkz */ + }, + { /* 6094 */ + 530, + /* VFNMADD132PSZ128r */ + }, + { /* 6095 */ + 212, + /* VFNMADD132PSZ128rk */ + }, + { /* 6096 */ + 212, + /* VFNMADD132PSZ128rkz */ + }, + { /* 6097 */ + 531, + /* VFNMADD132PSZ256m */ + }, + { /* 6098 */ + 541, + /* VFNMADD132PSZ256mb */ + }, + { /* 6099 */ + 241, + /* VFNMADD132PSZ256mbk */ + }, + { /* 6100 */ + 241, + /* VFNMADD132PSZ256mbkz */ + }, + { /* 6101 */ + 218, + /* VFNMADD132PSZ256mk */ + }, + { /* 6102 */ + 218, + /* VFNMADD132PSZ256mkz */ + }, + { /* 6103 */ + 533, + /* VFNMADD132PSZ256r */ + }, + { /* 6104 */ + 221, + /* VFNMADD132PSZ256rk */ + }, + { /* 6105 */ + 221, + /* VFNMADD132PSZ256rkz */ + }, + { /* 6106 */ + 534, + /* VFNMADD132PSZm */ + }, + { /* 6107 */ + 542, + /* VFNMADD132PSZmb */ + }, + { /* 6108 */ + 244, + /* VFNMADD132PSZmbk */ + }, + { /* 6109 */ + 244, + /* VFNMADD132PSZmbkz */ + }, + { /* 6110 */ + 227, + /* VFNMADD132PSZmk */ + }, + { /* 6111 */ + 227, + /* VFNMADD132PSZmkz */ + }, + { /* 6112 */ + 536, + /* VFNMADD132PSZr */ + }, + { /* 6113 */ + 543, + /* VFNMADD132PSZrb */ + }, + { /* 6114 */ + 247, + /* VFNMADD132PSZrbk */ + }, + { /* 6115 */ + 247, + /* VFNMADD132PSZrbkz */ + }, + { /* 6116 */ + 233, + /* VFNMADD132PSZrk */ + }, + { /* 6117 */ + 233, + /* VFNMADD132PSZrkz */ + }, + { /* 6118 */ + 538, + /* VFNMADD132PSm */ + }, + { /* 6119 */ + 539, + /* VFNMADD132PSr */ + }, + { /* 6120 */ + 0, + /* */ + }, + { /* 6121 */ + 529, + /* VFNMADD132SDZm_Int */ + }, + { /* 6122 */ + 208, + /* VFNMADD132SDZm_Intk */ + }, + { /* 6123 */ + 208, + /* VFNMADD132SDZm_Intkz */ + }, + { /* 6124 */ + 0, + /* */ + }, + { /* 6125 */ + 544, + /* VFNMADD132SDZr_Int */ + }, + { /* 6126 */ + 250, + /* VFNMADD132SDZr_Intk */ + }, + { /* 6127 */ + 250, + /* VFNMADD132SDZr_Intkz */ + }, + { /* 6128 */ + 0, + /* */ + }, + { /* 6129 */ + 545, + /* VFNMADD132SDZrb_Int */ + }, + { /* 6130 */ + 253, + /* VFNMADD132SDZrb_Intk */ + }, + { /* 6131 */ + 253, + /* VFNMADD132SDZrb_Intkz */ + }, + { /* 6132 */ + 538, + /* VFNMADD132SDm */ + }, + { /* 6133 */ + 0, + /* */ + }, + { /* 6134 */ + 539, + /* VFNMADD132SDr */ + }, + { /* 6135 */ + 0, + /* */ + }, + { /* 6136 */ + 0, + /* */ + }, + { /* 6137 */ + 540, + /* VFNMADD132SSZm_Int */ + }, + { /* 6138 */ + 238, + /* VFNMADD132SSZm_Intk */ + }, + { /* 6139 */ + 238, + /* VFNMADD132SSZm_Intkz */ + }, + { /* 6140 */ + 0, + /* */ + }, + { /* 6141 */ + 546, + /* VFNMADD132SSZr_Int */ + }, + { /* 6142 */ + 256, + /* VFNMADD132SSZr_Intk */ + }, + { /* 6143 */ + 256, + /* VFNMADD132SSZr_Intkz */ + }, + { /* 6144 */ + 0, + /* */ + }, + { /* 6145 */ + 547, + /* VFNMADD132SSZrb_Int */ + }, + { /* 6146 */ + 259, + /* VFNMADD132SSZrb_Intk */ + }, + { /* 6147 */ + 259, + /* VFNMADD132SSZrb_Intkz */ + }, + { /* 6148 */ + 538, + /* VFNMADD132SSm */ + }, + { /* 6149 */ + 0, + /* */ + }, + { /* 6150 */ + 539, + /* VFNMADD132SSr */ + }, + { /* 6151 */ + 0, + /* */ + }, + { /* 6152 */ + 527, + /* VFNMADD213PDYm */ + }, + { /* 6153 */ + 528, + /* VFNMADD213PDYr */ + }, + { /* 6154 */ + 202, + /* VFNMADD213PDZ128m */ + }, + { /* 6155 */ + 529, + /* VFNMADD213PDZ128mb */ + }, + { /* 6156 */ + 208, + /* VFNMADD213PDZ128mbk */ + }, + { /* 6157 */ + 208, + /* VFNMADD213PDZ128mbkz */ + }, + { /* 6158 */ + 203, + /* VFNMADD213PDZ128mk */ + }, + { /* 6159 */ + 203, + /* VFNMADD213PDZ128mkz */ + }, + { /* 6160 */ + 530, + /* VFNMADD213PDZ128r */ + }, + { /* 6161 */ + 212, + /* VFNMADD213PDZ128rk */ + }, + { /* 6162 */ + 212, + /* VFNMADD213PDZ128rkz */ + }, + { /* 6163 */ + 531, + /* VFNMADD213PDZ256m */ + }, + { /* 6164 */ + 532, + /* VFNMADD213PDZ256mb */ + }, + { /* 6165 */ + 216, + /* VFNMADD213PDZ256mbk */ + }, + { /* 6166 */ + 216, + /* VFNMADD213PDZ256mbkz */ + }, + { /* 6167 */ + 218, + /* VFNMADD213PDZ256mk */ + }, + { /* 6168 */ + 218, + /* VFNMADD213PDZ256mkz */ + }, + { /* 6169 */ + 533, + /* VFNMADD213PDZ256r */ + }, + { /* 6170 */ + 221, + /* VFNMADD213PDZ256rk */ + }, + { /* 6171 */ + 221, + /* VFNMADD213PDZ256rkz */ + }, + { /* 6172 */ + 534, + /* VFNMADD213PDZm */ + }, + { /* 6173 */ + 535, + /* VFNMADD213PDZmb */ + }, + { /* 6174 */ + 225, + /* VFNMADD213PDZmbk */ + }, + { /* 6175 */ + 225, + /* VFNMADD213PDZmbkz */ + }, + { /* 6176 */ + 227, + /* VFNMADD213PDZmk */ + }, + { /* 6177 */ + 227, + /* VFNMADD213PDZmkz */ + }, + { /* 6178 */ + 536, + /* VFNMADD213PDZr */ + }, + { /* 6179 */ + 537, + /* VFNMADD213PDZrb */ + }, + { /* 6180 */ + 231, + /* VFNMADD213PDZrbk */ + }, + { /* 6181 */ + 231, + /* VFNMADD213PDZrbkz */ + }, + { /* 6182 */ + 233, + /* VFNMADD213PDZrk */ + }, + { /* 6183 */ + 233, + /* VFNMADD213PDZrkz */ + }, + { /* 6184 */ + 538, + /* VFNMADD213PDm */ + }, + { /* 6185 */ + 539, + /* VFNMADD213PDr */ + }, + { /* 6186 */ + 527, + /* VFNMADD213PSYm */ + }, + { /* 6187 */ + 528, + /* VFNMADD213PSYr */ + }, + { /* 6188 */ + 202, + /* VFNMADD213PSZ128m */ + }, + { /* 6189 */ + 540, + /* VFNMADD213PSZ128mb */ + }, + { /* 6190 */ + 238, + /* VFNMADD213PSZ128mbk */ + }, + { /* 6191 */ + 238, + /* VFNMADD213PSZ128mbkz */ + }, + { /* 6192 */ + 203, + /* VFNMADD213PSZ128mk */ + }, + { /* 6193 */ + 203, + /* VFNMADD213PSZ128mkz */ + }, + { /* 6194 */ + 530, + /* VFNMADD213PSZ128r */ + }, + { /* 6195 */ + 212, + /* VFNMADD213PSZ128rk */ + }, + { /* 6196 */ + 212, + /* VFNMADD213PSZ128rkz */ + }, + { /* 6197 */ + 531, + /* VFNMADD213PSZ256m */ + }, + { /* 6198 */ + 541, + /* VFNMADD213PSZ256mb */ + }, + { /* 6199 */ + 241, + /* VFNMADD213PSZ256mbk */ + }, + { /* 6200 */ + 241, + /* VFNMADD213PSZ256mbkz */ + }, + { /* 6201 */ + 218, + /* VFNMADD213PSZ256mk */ + }, + { /* 6202 */ + 218, + /* VFNMADD213PSZ256mkz */ + }, + { /* 6203 */ + 533, + /* VFNMADD213PSZ256r */ + }, + { /* 6204 */ + 221, + /* VFNMADD213PSZ256rk */ + }, + { /* 6205 */ + 221, + /* VFNMADD213PSZ256rkz */ + }, + { /* 6206 */ + 534, + /* VFNMADD213PSZm */ + }, + { /* 6207 */ + 542, + /* VFNMADD213PSZmb */ + }, + { /* 6208 */ + 244, + /* VFNMADD213PSZmbk */ + }, + { /* 6209 */ + 244, + /* VFNMADD213PSZmbkz */ + }, + { /* 6210 */ + 227, + /* VFNMADD213PSZmk */ + }, + { /* 6211 */ + 227, + /* VFNMADD213PSZmkz */ + }, + { /* 6212 */ + 536, + /* VFNMADD213PSZr */ + }, + { /* 6213 */ + 543, + /* VFNMADD213PSZrb */ + }, + { /* 6214 */ + 247, + /* VFNMADD213PSZrbk */ + }, + { /* 6215 */ + 247, + /* VFNMADD213PSZrbkz */ + }, + { /* 6216 */ + 233, + /* VFNMADD213PSZrk */ + }, + { /* 6217 */ + 233, + /* VFNMADD213PSZrkz */ + }, + { /* 6218 */ + 538, + /* VFNMADD213PSm */ + }, + { /* 6219 */ + 539, + /* VFNMADD213PSr */ + }, + { /* 6220 */ + 0, + /* */ + }, + { /* 6221 */ + 529, + /* VFNMADD213SDZm_Int */ + }, + { /* 6222 */ + 208, + /* VFNMADD213SDZm_Intk */ + }, + { /* 6223 */ + 208, + /* VFNMADD213SDZm_Intkz */ + }, + { /* 6224 */ + 0, + /* */ + }, + { /* 6225 */ + 544, + /* VFNMADD213SDZr_Int */ + }, + { /* 6226 */ + 250, + /* VFNMADD213SDZr_Intk */ + }, + { /* 6227 */ + 250, + /* VFNMADD213SDZr_Intkz */ + }, + { /* 6228 */ + 0, + /* */ + }, + { /* 6229 */ + 545, + /* VFNMADD213SDZrb_Int */ + }, + { /* 6230 */ + 253, + /* VFNMADD213SDZrb_Intk */ + }, + { /* 6231 */ + 253, + /* VFNMADD213SDZrb_Intkz */ + }, + { /* 6232 */ + 538, + /* VFNMADD213SDm */ + }, + { /* 6233 */ + 0, + /* */ + }, + { /* 6234 */ + 539, + /* VFNMADD213SDr */ + }, + { /* 6235 */ + 0, + /* */ + }, + { /* 6236 */ + 0, + /* */ + }, + { /* 6237 */ + 540, + /* VFNMADD213SSZm_Int */ + }, + { /* 6238 */ + 238, + /* VFNMADD213SSZm_Intk */ + }, + { /* 6239 */ + 238, + /* VFNMADD213SSZm_Intkz */ + }, + { /* 6240 */ + 0, + /* */ + }, + { /* 6241 */ + 546, + /* VFNMADD213SSZr_Int */ + }, + { /* 6242 */ + 256, + /* VFNMADD213SSZr_Intk */ + }, + { /* 6243 */ + 256, + /* VFNMADD213SSZr_Intkz */ + }, + { /* 6244 */ + 0, + /* */ + }, + { /* 6245 */ + 547, + /* VFNMADD213SSZrb_Int */ + }, + { /* 6246 */ + 259, + /* VFNMADD213SSZrb_Intk */ + }, + { /* 6247 */ + 259, + /* VFNMADD213SSZrb_Intkz */ + }, + { /* 6248 */ + 538, + /* VFNMADD213SSm */ + }, + { /* 6249 */ + 0, + /* */ + }, + { /* 6250 */ + 539, + /* VFNMADD213SSr */ + }, + { /* 6251 */ + 0, + /* */ + }, + { /* 6252 */ + 527, + /* VFNMADD231PDYm */ + }, + { /* 6253 */ + 528, + /* VFNMADD231PDYr */ + }, + { /* 6254 */ + 202, + /* VFNMADD231PDZ128m */ + }, + { /* 6255 */ + 529, + /* VFNMADD231PDZ128mb */ + }, + { /* 6256 */ + 208, + /* VFNMADD231PDZ128mbk */ + }, + { /* 6257 */ + 208, + /* VFNMADD231PDZ128mbkz */ + }, + { /* 6258 */ + 203, + /* VFNMADD231PDZ128mk */ + }, + { /* 6259 */ + 203, + /* VFNMADD231PDZ128mkz */ + }, + { /* 6260 */ + 530, + /* VFNMADD231PDZ128r */ + }, + { /* 6261 */ + 212, + /* VFNMADD231PDZ128rk */ + }, + { /* 6262 */ + 212, + /* VFNMADD231PDZ128rkz */ + }, + { /* 6263 */ + 531, + /* VFNMADD231PDZ256m */ + }, + { /* 6264 */ + 532, + /* VFNMADD231PDZ256mb */ + }, + { /* 6265 */ + 216, + /* VFNMADD231PDZ256mbk */ + }, + { /* 6266 */ + 216, + /* VFNMADD231PDZ256mbkz */ + }, + { /* 6267 */ + 218, + /* VFNMADD231PDZ256mk */ + }, + { /* 6268 */ + 218, + /* VFNMADD231PDZ256mkz */ + }, + { /* 6269 */ + 533, + /* VFNMADD231PDZ256r */ + }, + { /* 6270 */ + 221, + /* VFNMADD231PDZ256rk */ + }, + { /* 6271 */ + 221, + /* VFNMADD231PDZ256rkz */ + }, + { /* 6272 */ + 534, + /* VFNMADD231PDZm */ + }, + { /* 6273 */ + 535, + /* VFNMADD231PDZmb */ + }, + { /* 6274 */ + 225, + /* VFNMADD231PDZmbk */ + }, + { /* 6275 */ + 225, + /* VFNMADD231PDZmbkz */ + }, + { /* 6276 */ + 227, + /* VFNMADD231PDZmk */ + }, + { /* 6277 */ + 227, + /* VFNMADD231PDZmkz */ + }, + { /* 6278 */ + 536, + /* VFNMADD231PDZr */ + }, + { /* 6279 */ + 537, + /* VFNMADD231PDZrb */ + }, + { /* 6280 */ + 231, + /* VFNMADD231PDZrbk */ + }, + { /* 6281 */ + 231, + /* VFNMADD231PDZrbkz */ + }, + { /* 6282 */ + 233, + /* VFNMADD231PDZrk */ + }, + { /* 6283 */ + 233, + /* VFNMADD231PDZrkz */ + }, + { /* 6284 */ + 538, + /* VFNMADD231PDm */ + }, + { /* 6285 */ + 539, + /* VFNMADD231PDr */ + }, + { /* 6286 */ + 527, + /* VFNMADD231PSYm */ + }, + { /* 6287 */ + 528, + /* VFNMADD231PSYr */ + }, + { /* 6288 */ + 202, + /* VFNMADD231PSZ128m */ + }, + { /* 6289 */ + 540, + /* VFNMADD231PSZ128mb */ + }, + { /* 6290 */ + 238, + /* VFNMADD231PSZ128mbk */ + }, + { /* 6291 */ + 238, + /* VFNMADD231PSZ128mbkz */ + }, + { /* 6292 */ + 203, + /* VFNMADD231PSZ128mk */ + }, + { /* 6293 */ + 203, + /* VFNMADD231PSZ128mkz */ + }, + { /* 6294 */ + 530, + /* VFNMADD231PSZ128r */ + }, + { /* 6295 */ + 212, + /* VFNMADD231PSZ128rk */ + }, + { /* 6296 */ + 212, + /* VFNMADD231PSZ128rkz */ + }, + { /* 6297 */ + 531, + /* VFNMADD231PSZ256m */ + }, + { /* 6298 */ + 541, + /* VFNMADD231PSZ256mb */ + }, + { /* 6299 */ + 241, + /* VFNMADD231PSZ256mbk */ + }, + { /* 6300 */ + 241, + /* VFNMADD231PSZ256mbkz */ + }, + { /* 6301 */ + 218, + /* VFNMADD231PSZ256mk */ + }, + { /* 6302 */ + 218, + /* VFNMADD231PSZ256mkz */ + }, + { /* 6303 */ + 533, + /* VFNMADD231PSZ256r */ + }, + { /* 6304 */ + 221, + /* VFNMADD231PSZ256rk */ + }, + { /* 6305 */ + 221, + /* VFNMADD231PSZ256rkz */ + }, + { /* 6306 */ + 534, + /* VFNMADD231PSZm */ + }, + { /* 6307 */ + 542, + /* VFNMADD231PSZmb */ + }, + { /* 6308 */ + 244, + /* VFNMADD231PSZmbk */ + }, + { /* 6309 */ + 244, + /* VFNMADD231PSZmbkz */ + }, + { /* 6310 */ + 227, + /* VFNMADD231PSZmk */ + }, + { /* 6311 */ + 227, + /* VFNMADD231PSZmkz */ + }, + { /* 6312 */ + 536, + /* VFNMADD231PSZr */ + }, + { /* 6313 */ + 543, + /* VFNMADD231PSZrb */ + }, + { /* 6314 */ + 247, + /* VFNMADD231PSZrbk */ + }, + { /* 6315 */ + 247, + /* VFNMADD231PSZrbkz */ + }, + { /* 6316 */ + 233, + /* VFNMADD231PSZrk */ + }, + { /* 6317 */ + 233, + /* VFNMADD231PSZrkz */ + }, + { /* 6318 */ + 538, + /* VFNMADD231PSm */ + }, + { /* 6319 */ + 539, + /* VFNMADD231PSr */ + }, + { /* 6320 */ + 0, + /* */ + }, + { /* 6321 */ + 529, + /* VFNMADD231SDZm_Int */ + }, + { /* 6322 */ + 208, + /* VFNMADD231SDZm_Intk */ + }, + { /* 6323 */ + 208, + /* VFNMADD231SDZm_Intkz */ + }, + { /* 6324 */ + 0, + /* */ + }, + { /* 6325 */ + 544, + /* VFNMADD231SDZr_Int */ + }, + { /* 6326 */ + 250, + /* VFNMADD231SDZr_Intk */ + }, + { /* 6327 */ + 250, + /* VFNMADD231SDZr_Intkz */ + }, + { /* 6328 */ + 0, + /* */ + }, + { /* 6329 */ + 545, + /* VFNMADD231SDZrb_Int */ + }, + { /* 6330 */ + 253, + /* VFNMADD231SDZrb_Intk */ + }, + { /* 6331 */ + 253, + /* VFNMADD231SDZrb_Intkz */ + }, + { /* 6332 */ + 538, + /* VFNMADD231SDm */ + }, + { /* 6333 */ + 0, + /* */ + }, + { /* 6334 */ + 539, + /* VFNMADD231SDr */ + }, + { /* 6335 */ + 0, + /* */ + }, + { /* 6336 */ + 0, + /* */ + }, + { /* 6337 */ + 540, + /* VFNMADD231SSZm_Int */ + }, + { /* 6338 */ + 238, + /* VFNMADD231SSZm_Intk */ + }, + { /* 6339 */ + 238, + /* VFNMADD231SSZm_Intkz */ + }, + { /* 6340 */ + 0, + /* */ + }, + { /* 6341 */ + 546, + /* VFNMADD231SSZr_Int */ + }, + { /* 6342 */ + 256, + /* VFNMADD231SSZr_Intk */ + }, + { /* 6343 */ + 256, + /* VFNMADD231SSZr_Intkz */ + }, + { /* 6344 */ + 0, + /* */ + }, + { /* 6345 */ + 547, + /* VFNMADD231SSZrb_Int */ + }, + { /* 6346 */ + 259, + /* VFNMADD231SSZrb_Intk */ + }, + { /* 6347 */ + 259, + /* VFNMADD231SSZrb_Intkz */ + }, + { /* 6348 */ + 538, + /* VFNMADD231SSm */ + }, + { /* 6349 */ + 0, + /* */ + }, + { /* 6350 */ + 539, + /* VFNMADD231SSr */ + }, + { /* 6351 */ + 0, + /* */ + }, + { /* 6352 */ + 301, + /* VFNMADDPD4Ymr */ + }, + { /* 6353 */ + 548, + /* VFNMADDPD4Yrm */ + }, + { /* 6354 */ + 549, + /* VFNMADDPD4Yrr */ + }, + { /* 6355 */ + 302, + /* VFNMADDPD4Yrr_REV */ + }, + { /* 6356 */ + 303, + /* VFNMADDPD4mr */ + }, + { /* 6357 */ + 550, + /* VFNMADDPD4rm */ + }, + { /* 6358 */ + 551, + /* VFNMADDPD4rr */ + }, + { /* 6359 */ + 304, + /* VFNMADDPD4rr_REV */ + }, + { /* 6360 */ + 301, + /* VFNMADDPS4Ymr */ + }, + { /* 6361 */ + 548, + /* VFNMADDPS4Yrm */ + }, + { /* 6362 */ + 549, + /* VFNMADDPS4Yrr */ + }, + { /* 6363 */ + 302, + /* VFNMADDPS4Yrr_REV */ + }, + { /* 6364 */ + 303, + /* VFNMADDPS4mr */ + }, + { /* 6365 */ + 550, + /* VFNMADDPS4rm */ + }, + { /* 6366 */ + 551, + /* VFNMADDPS4rr */ + }, + { /* 6367 */ + 304, + /* VFNMADDPS4rr_REV */ + }, + { /* 6368 */ + 303, + /* VFNMADDSD4mr */ + }, + { /* 6369 */ + 0, + /* */ + }, + { /* 6370 */ + 550, + /* VFNMADDSD4rm */ + }, + { /* 6371 */ + 0, + /* */ + }, + { /* 6372 */ + 551, + /* VFNMADDSD4rr */ + }, + { /* 6373 */ + 0, + /* */ + }, + { /* 6374 */ + 0, + /* */ + }, + { /* 6375 */ + 304, + /* VFNMADDSD4rr_REV */ + }, + { /* 6376 */ + 303, + /* VFNMADDSS4mr */ + }, + { /* 6377 */ + 0, + /* */ + }, + { /* 6378 */ + 550, + /* VFNMADDSS4rm */ + }, + { /* 6379 */ + 0, + /* */ + }, + { /* 6380 */ + 551, + /* VFNMADDSS4rr */ + }, + { /* 6381 */ + 0, + /* */ + }, + { /* 6382 */ + 0, + /* */ + }, + { /* 6383 */ + 304, + /* VFNMADDSS4rr_REV */ + }, + { /* 6384 */ + 527, + /* VFNMSUB132PDYm */ + }, + { /* 6385 */ + 528, + /* VFNMSUB132PDYr */ + }, + { /* 6386 */ + 202, + /* VFNMSUB132PDZ128m */ + }, + { /* 6387 */ + 529, + /* VFNMSUB132PDZ128mb */ + }, + { /* 6388 */ + 208, + /* VFNMSUB132PDZ128mbk */ + }, + { /* 6389 */ + 208, + /* VFNMSUB132PDZ128mbkz */ + }, + { /* 6390 */ + 203, + /* VFNMSUB132PDZ128mk */ + }, + { /* 6391 */ + 203, + /* VFNMSUB132PDZ128mkz */ + }, + { /* 6392 */ + 530, + /* VFNMSUB132PDZ128r */ + }, + { /* 6393 */ + 212, + /* VFNMSUB132PDZ128rk */ + }, + { /* 6394 */ + 212, + /* VFNMSUB132PDZ128rkz */ + }, + { /* 6395 */ + 531, + /* VFNMSUB132PDZ256m */ + }, + { /* 6396 */ + 532, + /* VFNMSUB132PDZ256mb */ + }, + { /* 6397 */ + 216, + /* VFNMSUB132PDZ256mbk */ + }, + { /* 6398 */ + 216, + /* VFNMSUB132PDZ256mbkz */ + }, + { /* 6399 */ + 218, + /* VFNMSUB132PDZ256mk */ + }, + { /* 6400 */ + 218, + /* VFNMSUB132PDZ256mkz */ + }, + { /* 6401 */ + 533, + /* VFNMSUB132PDZ256r */ + }, + { /* 6402 */ + 221, + /* VFNMSUB132PDZ256rk */ + }, + { /* 6403 */ + 221, + /* VFNMSUB132PDZ256rkz */ + }, + { /* 6404 */ + 534, + /* VFNMSUB132PDZm */ + }, + { /* 6405 */ + 535, + /* VFNMSUB132PDZmb */ + }, + { /* 6406 */ + 225, + /* VFNMSUB132PDZmbk */ + }, + { /* 6407 */ + 225, + /* VFNMSUB132PDZmbkz */ + }, + { /* 6408 */ + 227, + /* VFNMSUB132PDZmk */ + }, + { /* 6409 */ + 227, + /* VFNMSUB132PDZmkz */ + }, + { /* 6410 */ + 536, + /* VFNMSUB132PDZr */ + }, + { /* 6411 */ + 537, + /* VFNMSUB132PDZrb */ + }, + { /* 6412 */ + 231, + /* VFNMSUB132PDZrbk */ + }, + { /* 6413 */ + 231, + /* VFNMSUB132PDZrbkz */ + }, + { /* 6414 */ + 233, + /* VFNMSUB132PDZrk */ + }, + { /* 6415 */ + 233, + /* VFNMSUB132PDZrkz */ + }, + { /* 6416 */ + 538, + /* VFNMSUB132PDm */ + }, + { /* 6417 */ + 539, + /* VFNMSUB132PDr */ + }, + { /* 6418 */ + 527, + /* VFNMSUB132PSYm */ + }, + { /* 6419 */ + 528, + /* VFNMSUB132PSYr */ + }, + { /* 6420 */ + 202, + /* VFNMSUB132PSZ128m */ + }, + { /* 6421 */ + 540, + /* VFNMSUB132PSZ128mb */ + }, + { /* 6422 */ + 238, + /* VFNMSUB132PSZ128mbk */ + }, + { /* 6423 */ + 238, + /* VFNMSUB132PSZ128mbkz */ + }, + { /* 6424 */ + 203, + /* VFNMSUB132PSZ128mk */ + }, + { /* 6425 */ + 203, + /* VFNMSUB132PSZ128mkz */ + }, + { /* 6426 */ + 530, + /* VFNMSUB132PSZ128r */ + }, + { /* 6427 */ + 212, + /* VFNMSUB132PSZ128rk */ + }, + { /* 6428 */ + 212, + /* VFNMSUB132PSZ128rkz */ + }, + { /* 6429 */ + 531, + /* VFNMSUB132PSZ256m */ + }, + { /* 6430 */ + 541, + /* VFNMSUB132PSZ256mb */ + }, + { /* 6431 */ + 241, + /* VFNMSUB132PSZ256mbk */ + }, + { /* 6432 */ + 241, + /* VFNMSUB132PSZ256mbkz */ + }, + { /* 6433 */ + 218, + /* VFNMSUB132PSZ256mk */ + }, + { /* 6434 */ + 218, + /* VFNMSUB132PSZ256mkz */ + }, + { /* 6435 */ + 533, + /* VFNMSUB132PSZ256r */ + }, + { /* 6436 */ + 221, + /* VFNMSUB132PSZ256rk */ + }, + { /* 6437 */ + 221, + /* VFNMSUB132PSZ256rkz */ + }, + { /* 6438 */ + 534, + /* VFNMSUB132PSZm */ + }, + { /* 6439 */ + 542, + /* VFNMSUB132PSZmb */ + }, + { /* 6440 */ + 244, + /* VFNMSUB132PSZmbk */ + }, + { /* 6441 */ + 244, + /* VFNMSUB132PSZmbkz */ + }, + { /* 6442 */ + 227, + /* VFNMSUB132PSZmk */ + }, + { /* 6443 */ + 227, + /* VFNMSUB132PSZmkz */ + }, + { /* 6444 */ + 536, + /* VFNMSUB132PSZr */ + }, + { /* 6445 */ + 543, + /* VFNMSUB132PSZrb */ + }, + { /* 6446 */ + 247, + /* VFNMSUB132PSZrbk */ + }, + { /* 6447 */ + 247, + /* VFNMSUB132PSZrbkz */ + }, + { /* 6448 */ + 233, + /* VFNMSUB132PSZrk */ + }, + { /* 6449 */ + 233, + /* VFNMSUB132PSZrkz */ + }, + { /* 6450 */ + 538, + /* VFNMSUB132PSm */ + }, + { /* 6451 */ + 539, + /* VFNMSUB132PSr */ + }, + { /* 6452 */ + 0, + /* */ + }, + { /* 6453 */ + 529, + /* VFNMSUB132SDZm_Int */ + }, + { /* 6454 */ + 208, + /* VFNMSUB132SDZm_Intk */ + }, + { /* 6455 */ + 208, + /* VFNMSUB132SDZm_Intkz */ + }, + { /* 6456 */ + 0, + /* */ + }, + { /* 6457 */ + 544, + /* VFNMSUB132SDZr_Int */ + }, + { /* 6458 */ + 250, + /* VFNMSUB132SDZr_Intk */ + }, + { /* 6459 */ + 250, + /* VFNMSUB132SDZr_Intkz */ + }, + { /* 6460 */ + 0, + /* */ + }, + { /* 6461 */ + 545, + /* VFNMSUB132SDZrb_Int */ + }, + { /* 6462 */ + 253, + /* VFNMSUB132SDZrb_Intk */ + }, + { /* 6463 */ + 253, + /* VFNMSUB132SDZrb_Intkz */ + }, + { /* 6464 */ + 538, + /* VFNMSUB132SDm */ + }, + { /* 6465 */ + 0, + /* */ + }, + { /* 6466 */ + 539, + /* VFNMSUB132SDr */ + }, + { /* 6467 */ + 0, + /* */ + }, + { /* 6468 */ + 0, + /* */ + }, + { /* 6469 */ + 540, + /* VFNMSUB132SSZm_Int */ + }, + { /* 6470 */ + 238, + /* VFNMSUB132SSZm_Intk */ + }, + { /* 6471 */ + 238, + /* VFNMSUB132SSZm_Intkz */ + }, + { /* 6472 */ + 0, + /* */ + }, + { /* 6473 */ + 546, + /* VFNMSUB132SSZr_Int */ + }, + { /* 6474 */ + 256, + /* VFNMSUB132SSZr_Intk */ + }, + { /* 6475 */ + 256, + /* VFNMSUB132SSZr_Intkz */ + }, + { /* 6476 */ + 0, + /* */ + }, + { /* 6477 */ + 547, + /* VFNMSUB132SSZrb_Int */ + }, + { /* 6478 */ + 259, + /* VFNMSUB132SSZrb_Intk */ + }, + { /* 6479 */ + 259, + /* VFNMSUB132SSZrb_Intkz */ + }, + { /* 6480 */ + 538, + /* VFNMSUB132SSm */ + }, + { /* 6481 */ + 0, + /* */ + }, + { /* 6482 */ + 539, + /* VFNMSUB132SSr */ + }, + { /* 6483 */ + 0, + /* */ + }, + { /* 6484 */ + 527, + /* VFNMSUB213PDYm */ + }, + { /* 6485 */ + 528, + /* VFNMSUB213PDYr */ + }, + { /* 6486 */ + 202, + /* VFNMSUB213PDZ128m */ + }, + { /* 6487 */ + 529, + /* VFNMSUB213PDZ128mb */ + }, + { /* 6488 */ + 208, + /* VFNMSUB213PDZ128mbk */ + }, + { /* 6489 */ + 208, + /* VFNMSUB213PDZ128mbkz */ + }, + { /* 6490 */ + 203, + /* VFNMSUB213PDZ128mk */ + }, + { /* 6491 */ + 203, + /* VFNMSUB213PDZ128mkz */ + }, + { /* 6492 */ + 530, + /* VFNMSUB213PDZ128r */ + }, + { /* 6493 */ + 212, + /* VFNMSUB213PDZ128rk */ + }, + { /* 6494 */ + 212, + /* VFNMSUB213PDZ128rkz */ + }, + { /* 6495 */ + 531, + /* VFNMSUB213PDZ256m */ + }, + { /* 6496 */ + 532, + /* VFNMSUB213PDZ256mb */ + }, + { /* 6497 */ + 216, + /* VFNMSUB213PDZ256mbk */ + }, + { /* 6498 */ + 216, + /* VFNMSUB213PDZ256mbkz */ + }, + { /* 6499 */ + 218, + /* VFNMSUB213PDZ256mk */ + }, + { /* 6500 */ + 218, + /* VFNMSUB213PDZ256mkz */ + }, + { /* 6501 */ + 533, + /* VFNMSUB213PDZ256r */ + }, + { /* 6502 */ + 221, + /* VFNMSUB213PDZ256rk */ + }, + { /* 6503 */ + 221, + /* VFNMSUB213PDZ256rkz */ + }, + { /* 6504 */ + 534, + /* VFNMSUB213PDZm */ + }, + { /* 6505 */ + 535, + /* VFNMSUB213PDZmb */ + }, + { /* 6506 */ + 225, + /* VFNMSUB213PDZmbk */ + }, + { /* 6507 */ + 225, + /* VFNMSUB213PDZmbkz */ + }, + { /* 6508 */ + 227, + /* VFNMSUB213PDZmk */ + }, + { /* 6509 */ + 227, + /* VFNMSUB213PDZmkz */ + }, + { /* 6510 */ + 536, + /* VFNMSUB213PDZr */ + }, + { /* 6511 */ + 537, + /* VFNMSUB213PDZrb */ + }, + { /* 6512 */ + 231, + /* VFNMSUB213PDZrbk */ + }, + { /* 6513 */ + 231, + /* VFNMSUB213PDZrbkz */ + }, + { /* 6514 */ + 233, + /* VFNMSUB213PDZrk */ + }, + { /* 6515 */ + 233, + /* VFNMSUB213PDZrkz */ + }, + { /* 6516 */ + 538, + /* VFNMSUB213PDm */ + }, + { /* 6517 */ + 539, + /* VFNMSUB213PDr */ + }, + { /* 6518 */ + 527, + /* VFNMSUB213PSYm */ + }, + { /* 6519 */ + 528, + /* VFNMSUB213PSYr */ + }, + { /* 6520 */ + 202, + /* VFNMSUB213PSZ128m */ + }, + { /* 6521 */ + 540, + /* VFNMSUB213PSZ128mb */ + }, + { /* 6522 */ + 238, + /* VFNMSUB213PSZ128mbk */ + }, + { /* 6523 */ + 238, + /* VFNMSUB213PSZ128mbkz */ + }, + { /* 6524 */ + 203, + /* VFNMSUB213PSZ128mk */ + }, + { /* 6525 */ + 203, + /* VFNMSUB213PSZ128mkz */ + }, + { /* 6526 */ + 530, + /* VFNMSUB213PSZ128r */ + }, + { /* 6527 */ + 212, + /* VFNMSUB213PSZ128rk */ + }, + { /* 6528 */ + 212, + /* VFNMSUB213PSZ128rkz */ + }, + { /* 6529 */ + 531, + /* VFNMSUB213PSZ256m */ + }, + { /* 6530 */ + 541, + /* VFNMSUB213PSZ256mb */ + }, + { /* 6531 */ + 241, + /* VFNMSUB213PSZ256mbk */ + }, + { /* 6532 */ + 241, + /* VFNMSUB213PSZ256mbkz */ + }, + { /* 6533 */ + 218, + /* VFNMSUB213PSZ256mk */ + }, + { /* 6534 */ + 218, + /* VFNMSUB213PSZ256mkz */ + }, + { /* 6535 */ + 533, + /* VFNMSUB213PSZ256r */ + }, + { /* 6536 */ + 221, + /* VFNMSUB213PSZ256rk */ + }, + { /* 6537 */ + 221, + /* VFNMSUB213PSZ256rkz */ + }, + { /* 6538 */ + 534, + /* VFNMSUB213PSZm */ + }, + { /* 6539 */ + 542, + /* VFNMSUB213PSZmb */ + }, + { /* 6540 */ + 244, + /* VFNMSUB213PSZmbk */ + }, + { /* 6541 */ + 244, + /* VFNMSUB213PSZmbkz */ + }, + { /* 6542 */ + 227, + /* VFNMSUB213PSZmk */ + }, + { /* 6543 */ + 227, + /* VFNMSUB213PSZmkz */ + }, + { /* 6544 */ + 536, + /* VFNMSUB213PSZr */ + }, + { /* 6545 */ + 543, + /* VFNMSUB213PSZrb */ + }, + { /* 6546 */ + 247, + /* VFNMSUB213PSZrbk */ + }, + { /* 6547 */ + 247, + /* VFNMSUB213PSZrbkz */ + }, + { /* 6548 */ + 233, + /* VFNMSUB213PSZrk */ + }, + { /* 6549 */ + 233, + /* VFNMSUB213PSZrkz */ + }, + { /* 6550 */ + 538, + /* VFNMSUB213PSm */ + }, + { /* 6551 */ + 539, + /* VFNMSUB213PSr */ + }, + { /* 6552 */ + 0, + /* */ + }, + { /* 6553 */ + 529, + /* VFNMSUB213SDZm_Int */ + }, + { /* 6554 */ + 208, + /* VFNMSUB213SDZm_Intk */ + }, + { /* 6555 */ + 208, + /* VFNMSUB213SDZm_Intkz */ + }, + { /* 6556 */ + 0, + /* */ + }, + { /* 6557 */ + 544, + /* VFNMSUB213SDZr_Int */ + }, + { /* 6558 */ + 250, + /* VFNMSUB213SDZr_Intk */ + }, + { /* 6559 */ + 250, + /* VFNMSUB213SDZr_Intkz */ + }, + { /* 6560 */ + 0, + /* */ + }, + { /* 6561 */ + 545, + /* VFNMSUB213SDZrb_Int */ + }, + { /* 6562 */ + 253, + /* VFNMSUB213SDZrb_Intk */ + }, + { /* 6563 */ + 253, + /* VFNMSUB213SDZrb_Intkz */ + }, + { /* 6564 */ + 538, + /* VFNMSUB213SDm */ + }, + { /* 6565 */ + 0, + /* */ + }, + { /* 6566 */ + 539, + /* VFNMSUB213SDr */ + }, + { /* 6567 */ + 0, + /* */ + }, + { /* 6568 */ + 0, + /* */ + }, + { /* 6569 */ + 540, + /* VFNMSUB213SSZm_Int */ + }, + { /* 6570 */ + 238, + /* VFNMSUB213SSZm_Intk */ + }, + { /* 6571 */ + 238, + /* VFNMSUB213SSZm_Intkz */ + }, + { /* 6572 */ + 0, + /* */ + }, + { /* 6573 */ + 546, + /* VFNMSUB213SSZr_Int */ + }, + { /* 6574 */ + 256, + /* VFNMSUB213SSZr_Intk */ + }, + { /* 6575 */ + 256, + /* VFNMSUB213SSZr_Intkz */ + }, + { /* 6576 */ + 0, + /* */ + }, + { /* 6577 */ + 547, + /* VFNMSUB213SSZrb_Int */ + }, + { /* 6578 */ + 259, + /* VFNMSUB213SSZrb_Intk */ + }, + { /* 6579 */ + 259, + /* VFNMSUB213SSZrb_Intkz */ + }, + { /* 6580 */ + 538, + /* VFNMSUB213SSm */ + }, + { /* 6581 */ + 0, + /* */ + }, + { /* 6582 */ + 539, + /* VFNMSUB213SSr */ + }, + { /* 6583 */ + 0, + /* */ + }, + { /* 6584 */ + 527, + /* VFNMSUB231PDYm */ + }, + { /* 6585 */ + 528, + /* VFNMSUB231PDYr */ + }, + { /* 6586 */ + 202, + /* VFNMSUB231PDZ128m */ + }, + { /* 6587 */ + 529, + /* VFNMSUB231PDZ128mb */ + }, + { /* 6588 */ + 208, + /* VFNMSUB231PDZ128mbk */ + }, + { /* 6589 */ + 208, + /* VFNMSUB231PDZ128mbkz */ + }, + { /* 6590 */ + 203, + /* VFNMSUB231PDZ128mk */ + }, + { /* 6591 */ + 203, + /* VFNMSUB231PDZ128mkz */ + }, + { /* 6592 */ + 530, + /* VFNMSUB231PDZ128r */ + }, + { /* 6593 */ + 212, + /* VFNMSUB231PDZ128rk */ + }, + { /* 6594 */ + 212, + /* VFNMSUB231PDZ128rkz */ + }, + { /* 6595 */ + 531, + /* VFNMSUB231PDZ256m */ + }, + { /* 6596 */ + 532, + /* VFNMSUB231PDZ256mb */ + }, + { /* 6597 */ + 216, + /* VFNMSUB231PDZ256mbk */ + }, + { /* 6598 */ + 216, + /* VFNMSUB231PDZ256mbkz */ + }, + { /* 6599 */ + 218, + /* VFNMSUB231PDZ256mk */ + }, + { /* 6600 */ + 218, + /* VFNMSUB231PDZ256mkz */ + }, + { /* 6601 */ + 533, + /* VFNMSUB231PDZ256r */ + }, + { /* 6602 */ + 221, + /* VFNMSUB231PDZ256rk */ + }, + { /* 6603 */ + 221, + /* VFNMSUB231PDZ256rkz */ + }, + { /* 6604 */ + 534, + /* VFNMSUB231PDZm */ + }, + { /* 6605 */ + 535, + /* VFNMSUB231PDZmb */ + }, + { /* 6606 */ + 225, + /* VFNMSUB231PDZmbk */ + }, + { /* 6607 */ + 225, + /* VFNMSUB231PDZmbkz */ + }, + { /* 6608 */ + 227, + /* VFNMSUB231PDZmk */ + }, + { /* 6609 */ + 227, + /* VFNMSUB231PDZmkz */ + }, + { /* 6610 */ + 536, + /* VFNMSUB231PDZr */ + }, + { /* 6611 */ + 537, + /* VFNMSUB231PDZrb */ + }, + { /* 6612 */ + 231, + /* VFNMSUB231PDZrbk */ + }, + { /* 6613 */ + 231, + /* VFNMSUB231PDZrbkz */ + }, + { /* 6614 */ + 233, + /* VFNMSUB231PDZrk */ + }, + { /* 6615 */ + 233, + /* VFNMSUB231PDZrkz */ + }, + { /* 6616 */ + 538, + /* VFNMSUB231PDm */ + }, + { /* 6617 */ + 539, + /* VFNMSUB231PDr */ + }, + { /* 6618 */ + 527, + /* VFNMSUB231PSYm */ + }, + { /* 6619 */ + 528, + /* VFNMSUB231PSYr */ + }, + { /* 6620 */ + 202, + /* VFNMSUB231PSZ128m */ + }, + { /* 6621 */ + 540, + /* VFNMSUB231PSZ128mb */ + }, + { /* 6622 */ + 238, + /* VFNMSUB231PSZ128mbk */ + }, + { /* 6623 */ + 238, + /* VFNMSUB231PSZ128mbkz */ + }, + { /* 6624 */ + 203, + /* VFNMSUB231PSZ128mk */ + }, + { /* 6625 */ + 203, + /* VFNMSUB231PSZ128mkz */ + }, + { /* 6626 */ + 530, + /* VFNMSUB231PSZ128r */ + }, + { /* 6627 */ + 212, + /* VFNMSUB231PSZ128rk */ + }, + { /* 6628 */ + 212, + /* VFNMSUB231PSZ128rkz */ + }, + { /* 6629 */ + 531, + /* VFNMSUB231PSZ256m */ + }, + { /* 6630 */ + 541, + /* VFNMSUB231PSZ256mb */ + }, + { /* 6631 */ + 241, + /* VFNMSUB231PSZ256mbk */ + }, + { /* 6632 */ + 241, + /* VFNMSUB231PSZ256mbkz */ + }, + { /* 6633 */ + 218, + /* VFNMSUB231PSZ256mk */ + }, + { /* 6634 */ + 218, + /* VFNMSUB231PSZ256mkz */ + }, + { /* 6635 */ + 533, + /* VFNMSUB231PSZ256r */ + }, + { /* 6636 */ + 221, + /* VFNMSUB231PSZ256rk */ + }, + { /* 6637 */ + 221, + /* VFNMSUB231PSZ256rkz */ + }, + { /* 6638 */ + 534, + /* VFNMSUB231PSZm */ + }, + { /* 6639 */ + 542, + /* VFNMSUB231PSZmb */ + }, + { /* 6640 */ + 244, + /* VFNMSUB231PSZmbk */ + }, + { /* 6641 */ + 244, + /* VFNMSUB231PSZmbkz */ + }, + { /* 6642 */ + 227, + /* VFNMSUB231PSZmk */ + }, + { /* 6643 */ + 227, + /* VFNMSUB231PSZmkz */ + }, + { /* 6644 */ + 536, + /* VFNMSUB231PSZr */ + }, + { /* 6645 */ + 543, + /* VFNMSUB231PSZrb */ + }, + { /* 6646 */ + 247, + /* VFNMSUB231PSZrbk */ + }, + { /* 6647 */ + 247, + /* VFNMSUB231PSZrbkz */ + }, + { /* 6648 */ + 233, + /* VFNMSUB231PSZrk */ + }, + { /* 6649 */ + 233, + /* VFNMSUB231PSZrkz */ + }, + { /* 6650 */ + 538, + /* VFNMSUB231PSm */ + }, + { /* 6651 */ + 539, + /* VFNMSUB231PSr */ + }, + { /* 6652 */ + 0, + /* */ + }, + { /* 6653 */ + 529, + /* VFNMSUB231SDZm_Int */ + }, + { /* 6654 */ + 208, + /* VFNMSUB231SDZm_Intk */ + }, + { /* 6655 */ + 208, + /* VFNMSUB231SDZm_Intkz */ + }, + { /* 6656 */ + 0, + /* */ + }, + { /* 6657 */ + 544, + /* VFNMSUB231SDZr_Int */ + }, + { /* 6658 */ + 250, + /* VFNMSUB231SDZr_Intk */ + }, + { /* 6659 */ + 250, + /* VFNMSUB231SDZr_Intkz */ + }, + { /* 6660 */ + 0, + /* */ + }, + { /* 6661 */ + 545, + /* VFNMSUB231SDZrb_Int */ + }, + { /* 6662 */ + 253, + /* VFNMSUB231SDZrb_Intk */ + }, + { /* 6663 */ + 253, + /* VFNMSUB231SDZrb_Intkz */ + }, + { /* 6664 */ + 538, + /* VFNMSUB231SDm */ + }, + { /* 6665 */ + 0, + /* */ + }, + { /* 6666 */ + 539, + /* VFNMSUB231SDr */ + }, + { /* 6667 */ + 0, + /* */ + }, + { /* 6668 */ + 0, + /* */ + }, + { /* 6669 */ + 540, + /* VFNMSUB231SSZm_Int */ + }, + { /* 6670 */ + 238, + /* VFNMSUB231SSZm_Intk */ + }, + { /* 6671 */ + 238, + /* VFNMSUB231SSZm_Intkz */ + }, + { /* 6672 */ + 0, + /* */ + }, + { /* 6673 */ + 546, + /* VFNMSUB231SSZr_Int */ + }, + { /* 6674 */ + 256, + /* VFNMSUB231SSZr_Intk */ + }, + { /* 6675 */ + 256, + /* VFNMSUB231SSZr_Intkz */ + }, + { /* 6676 */ + 0, + /* */ + }, + { /* 6677 */ + 547, + /* VFNMSUB231SSZrb_Int */ + }, + { /* 6678 */ + 259, + /* VFNMSUB231SSZrb_Intk */ + }, + { /* 6679 */ + 259, + /* VFNMSUB231SSZrb_Intkz */ + }, + { /* 6680 */ + 538, + /* VFNMSUB231SSm */ + }, + { /* 6681 */ + 0, + /* */ + }, + { /* 6682 */ + 539, + /* VFNMSUB231SSr */ + }, + { /* 6683 */ + 0, + /* */ + }, + { /* 6684 */ + 301, + /* VFNMSUBPD4Ymr */ + }, + { /* 6685 */ + 548, + /* VFNMSUBPD4Yrm */ + }, + { /* 6686 */ + 549, + /* VFNMSUBPD4Yrr */ + }, + { /* 6687 */ + 302, + /* VFNMSUBPD4Yrr_REV */ + }, + { /* 6688 */ + 303, + /* VFNMSUBPD4mr */ + }, + { /* 6689 */ + 550, + /* VFNMSUBPD4rm */ + }, + { /* 6690 */ + 551, + /* VFNMSUBPD4rr */ + }, + { /* 6691 */ + 304, + /* VFNMSUBPD4rr_REV */ + }, + { /* 6692 */ + 301, + /* VFNMSUBPS4Ymr */ + }, + { /* 6693 */ + 548, + /* VFNMSUBPS4Yrm */ + }, + { /* 6694 */ + 549, + /* VFNMSUBPS4Yrr */ + }, + { /* 6695 */ + 302, + /* VFNMSUBPS4Yrr_REV */ + }, + { /* 6696 */ + 303, + /* VFNMSUBPS4mr */ + }, + { /* 6697 */ + 550, + /* VFNMSUBPS4rm */ + }, + { /* 6698 */ + 551, + /* VFNMSUBPS4rr */ + }, + { /* 6699 */ + 304, + /* VFNMSUBPS4rr_REV */ + }, + { /* 6700 */ + 303, + /* VFNMSUBSD4mr */ + }, + { /* 6701 */ + 0, + /* */ + }, + { /* 6702 */ + 550, + /* VFNMSUBSD4rm */ + }, + { /* 6703 */ + 0, + /* */ + }, + { /* 6704 */ + 551, + /* VFNMSUBSD4rr */ + }, + { /* 6705 */ + 0, + /* */ + }, + { /* 6706 */ + 0, + /* */ + }, + { /* 6707 */ + 304, + /* VFNMSUBSD4rr_REV */ + }, + { /* 6708 */ + 303, + /* VFNMSUBSS4mr */ + }, + { /* 6709 */ + 0, + /* */ + }, + { /* 6710 */ + 550, + /* VFNMSUBSS4rm */ + }, + { /* 6711 */ + 0, + /* */ + }, + { /* 6712 */ + 551, + /* VFNMSUBSS4rr */ + }, + { /* 6713 */ + 0, + /* */ + }, + { /* 6714 */ + 0, + /* */ + }, + { /* 6715 */ + 304, + /* VFNMSUBSS4rr_REV */ + }, + { /* 6716 */ + 552, + /* VFPCLASSPDZ128rm */ + }, + { /* 6717 */ + 553, + /* VFPCLASSPDZ128rmb */ + }, + { /* 6718 */ + 554, + /* VFPCLASSPDZ128rmbk */ + }, + { /* 6719 */ + 555, + /* VFPCLASSPDZ128rmk */ + }, + { /* 6720 */ + 556, + /* VFPCLASSPDZ128rr */ + }, + { /* 6721 */ + 557, + /* VFPCLASSPDZ128rrk */ + }, + { /* 6722 */ + 558, + /* VFPCLASSPDZ256rm */ + }, + { /* 6723 */ + 553, + /* VFPCLASSPDZ256rmb */ + }, + { /* 6724 */ + 554, + /* VFPCLASSPDZ256rmbk */ + }, + { /* 6725 */ + 559, + /* VFPCLASSPDZ256rmk */ + }, + { /* 6726 */ + 560, + /* VFPCLASSPDZ256rr */ + }, + { /* 6727 */ + 561, + /* VFPCLASSPDZ256rrk */ + }, + { /* 6728 */ + 562, + /* VFPCLASSPDZrm */ + }, + { /* 6729 */ + 553, + /* VFPCLASSPDZrmb */ + }, + { /* 6730 */ + 554, + /* VFPCLASSPDZrmbk */ + }, + { /* 6731 */ + 563, + /* VFPCLASSPDZrmk */ + }, + { /* 6732 */ + 564, + /* VFPCLASSPDZrr */ + }, + { /* 6733 */ + 565, + /* VFPCLASSPDZrrk */ + }, + { /* 6734 */ + 552, + /* VFPCLASSPSZ128rm */ + }, + { /* 6735 */ + 566, + /* VFPCLASSPSZ128rmb */ + }, + { /* 6736 */ + 567, + /* VFPCLASSPSZ128rmbk */ + }, + { /* 6737 */ + 555, + /* VFPCLASSPSZ128rmk */ + }, + { /* 6738 */ + 556, + /* VFPCLASSPSZ128rr */ + }, + { /* 6739 */ + 557, + /* VFPCLASSPSZ128rrk */ + }, + { /* 6740 */ + 558, + /* VFPCLASSPSZ256rm */ + }, + { /* 6741 */ + 566, + /* VFPCLASSPSZ256rmb */ + }, + { /* 6742 */ + 567, + /* VFPCLASSPSZ256rmbk */ + }, + { /* 6743 */ + 559, + /* VFPCLASSPSZ256rmk */ + }, + { /* 6744 */ + 560, + /* VFPCLASSPSZ256rr */ + }, + { /* 6745 */ + 561, + /* VFPCLASSPSZ256rrk */ + }, + { /* 6746 */ + 562, + /* VFPCLASSPSZrm */ + }, + { /* 6747 */ + 566, + /* VFPCLASSPSZrmb */ + }, + { /* 6748 */ + 567, + /* VFPCLASSPSZrmbk */ + }, + { /* 6749 */ + 563, + /* VFPCLASSPSZrmk */ + }, + { /* 6750 */ + 564, + /* VFPCLASSPSZrr */ + }, + { /* 6751 */ + 565, + /* VFPCLASSPSZrrk */ + }, + { /* 6752 */ + 553, + /* VFPCLASSSDZrm */ + }, + { /* 6753 */ + 554, + /* VFPCLASSSDZrmk */ + }, + { /* 6754 */ + 568, + /* VFPCLASSSDZrr */ + }, + { /* 6755 */ + 569, + /* VFPCLASSSDZrrk */ + }, + { /* 6756 */ + 566, + /* VFPCLASSSSZrm */ + }, + { /* 6757 */ + 567, + /* VFPCLASSSSZrmk */ + }, + { /* 6758 */ + 570, + /* VFPCLASSSSZrr */ + }, + { /* 6759 */ + 571, + /* VFPCLASSSSZrrk */ + }, + { /* 6760 */ + 305, + /* VFRCZPDYrm */ + }, + { /* 6761 */ + 408, + /* VFRCZPDYrr */ + }, + { /* 6762 */ + 30, + /* VFRCZPDrm */ + }, + { /* 6763 */ + 31, + /* VFRCZPDrr */ + }, + { /* 6764 */ + 305, + /* VFRCZPSYrm */ + }, + { /* 6765 */ + 408, + /* VFRCZPSYrr */ + }, + { /* 6766 */ + 30, + /* VFRCZPSrm */ + }, + { /* 6767 */ + 31, + /* VFRCZPSrr */ + }, + { /* 6768 */ + 30, + /* VFRCZSDrm */ + }, + { /* 6769 */ + 31, + /* VFRCZSDrr */ + }, + { /* 6770 */ + 30, + /* VFRCZSSrm */ + }, + { /* 6771 */ + 31, + /* VFRCZSSrr */ + }, + { /* 6772 */ + 572, + /* VGATHERDPDYrm */ + }, + { /* 6773 */ + 573, + /* VGATHERDPDZ128rm */ + }, + { /* 6774 */ + 574, + /* VGATHERDPDZ256rm */ + }, + { /* 6775 */ + 575, + /* VGATHERDPDZrm */ + }, + { /* 6776 */ + 576, + /* VGATHERDPDrm */ + }, + { /* 6777 */ + 577, + /* VGATHERDPSYrm */ + }, + { /* 6778 */ + 578, + /* VGATHERDPSZ128rm */ + }, + { /* 6779 */ + 579, + /* VGATHERDPSZ256rm */ + }, + { /* 6780 */ + 580, + /* VGATHERDPSZrm */ + }, + { /* 6781 */ + 576, + /* VGATHERDPSrm */ + }, + { /* 6782 */ + 581, + /* VGATHERPF0DPDm */ + }, + { /* 6783 */ + 582, + /* VGATHERPF0DPSm */ + }, + { /* 6784 */ + 583, + /* VGATHERPF0QPDm */ + }, + { /* 6785 */ + 583, + /* VGATHERPF0QPSm */ + }, + { /* 6786 */ + 581, + /* VGATHERPF1DPDm */ + }, + { /* 6787 */ + 582, + /* VGATHERPF1DPSm */ + }, + { /* 6788 */ + 583, + /* VGATHERPF1QPDm */ + }, + { /* 6789 */ + 583, + /* VGATHERPF1QPSm */ + }, + { /* 6790 */ + 577, + /* VGATHERQPDYrm */ + }, + { /* 6791 */ + 573, + /* VGATHERQPDZ128rm */ + }, + { /* 6792 */ + 584, + /* VGATHERQPDZ256rm */ + }, + { /* 6793 */ + 585, + /* VGATHERQPDZrm */ + }, + { /* 6794 */ + 576, + /* VGATHERQPDrm */ + }, + { /* 6795 */ + 586, + /* VGATHERQPSYrm */ + }, + { /* 6796 */ + 578, + /* VGATHERQPSZ128rm */ + }, + { /* 6797 */ + 587, + /* VGATHERQPSZ256rm */ + }, + { /* 6798 */ + 588, + /* VGATHERQPSZrm */ + }, + { /* 6799 */ + 576, + /* VGATHERQPSrm */ + }, + { /* 6800 */ + 409, + /* VGETEXPPDZ128m */ + }, + { /* 6801 */ + 327, + /* VGETEXPPDZ128mb */ + }, + { /* 6802 */ + 328, + /* VGETEXPPDZ128mbk */ + }, + { /* 6803 */ + 329, + /* VGETEXPPDZ128mbkz */ + }, + { /* 6804 */ + 410, + /* VGETEXPPDZ128mk */ + }, + { /* 6805 */ + 411, + /* VGETEXPPDZ128mkz */ + }, + { /* 6806 */ + 330, + /* VGETEXPPDZ128r */ + }, + { /* 6807 */ + 331, + /* VGETEXPPDZ128rk */ + }, + { /* 6808 */ + 332, + /* VGETEXPPDZ128rkz */ + }, + { /* 6809 */ + 412, + /* VGETEXPPDZ256m */ + }, + { /* 6810 */ + 306, + /* VGETEXPPDZ256mb */ + }, + { /* 6811 */ + 307, + /* VGETEXPPDZ256mbk */ + }, + { /* 6812 */ + 308, + /* VGETEXPPDZ256mbkz */ + }, + { /* 6813 */ + 413, + /* VGETEXPPDZ256mk */ + }, + { /* 6814 */ + 414, + /* VGETEXPPDZ256mkz */ + }, + { /* 6815 */ + 415, + /* VGETEXPPDZ256r */ + }, + { /* 6816 */ + 416, + /* VGETEXPPDZ256rk */ + }, + { /* 6817 */ + 417, + /* VGETEXPPDZ256rkz */ + }, + { /* 6818 */ + 418, + /* VGETEXPPDZm */ + }, + { /* 6819 */ + 312, + /* VGETEXPPDZmb */ + }, + { /* 6820 */ + 313, + /* VGETEXPPDZmbk */ + }, + { /* 6821 */ + 314, + /* VGETEXPPDZmbkz */ + }, + { /* 6822 */ + 419, + /* VGETEXPPDZmk */ + }, + { /* 6823 */ + 420, + /* VGETEXPPDZmkz */ + }, + { /* 6824 */ + 421, + /* VGETEXPPDZr */ + }, + { /* 6825 */ + 494, + /* VGETEXPPDZrb */ + }, + { /* 6826 */ + 495, + /* VGETEXPPDZrbk */ + }, + { /* 6827 */ + 496, + /* VGETEXPPDZrbkz */ + }, + { /* 6828 */ + 425, + /* VGETEXPPDZrk */ + }, + { /* 6829 */ + 426, + /* VGETEXPPDZrkz */ + }, + { /* 6830 */ + 409, + /* VGETEXPPSZ128m */ + }, + { /* 6831 */ + 334, + /* VGETEXPPSZ128mb */ + }, + { /* 6832 */ + 335, + /* VGETEXPPSZ128mbk */ + }, + { /* 6833 */ + 336, + /* VGETEXPPSZ128mbkz */ + }, + { /* 6834 */ + 410, + /* VGETEXPPSZ128mk */ + }, + { /* 6835 */ + 411, + /* VGETEXPPSZ128mkz */ + }, + { /* 6836 */ + 330, + /* VGETEXPPSZ128r */ + }, + { /* 6837 */ + 331, + /* VGETEXPPSZ128rk */ + }, + { /* 6838 */ + 332, + /* VGETEXPPSZ128rkz */ + }, + { /* 6839 */ + 412, + /* VGETEXPPSZ256m */ + }, + { /* 6840 */ + 337, + /* VGETEXPPSZ256mb */ + }, + { /* 6841 */ + 338, + /* VGETEXPPSZ256mbk */ + }, + { /* 6842 */ + 339, + /* VGETEXPPSZ256mbkz */ + }, + { /* 6843 */ + 413, + /* VGETEXPPSZ256mk */ + }, + { /* 6844 */ + 414, + /* VGETEXPPSZ256mkz */ + }, + { /* 6845 */ + 415, + /* VGETEXPPSZ256r */ + }, + { /* 6846 */ + 416, + /* VGETEXPPSZ256rk */ + }, + { /* 6847 */ + 417, + /* VGETEXPPSZ256rkz */ + }, + { /* 6848 */ + 418, + /* VGETEXPPSZm */ + }, + { /* 6849 */ + 340, + /* VGETEXPPSZmb */ + }, + { /* 6850 */ + 341, + /* VGETEXPPSZmbk */ + }, + { /* 6851 */ + 342, + /* VGETEXPPSZmbkz */ + }, + { /* 6852 */ + 419, + /* VGETEXPPSZmk */ + }, + { /* 6853 */ + 420, + /* VGETEXPPSZmkz */ + }, + { /* 6854 */ + 421, + /* VGETEXPPSZr */ + }, + { /* 6855 */ + 497, + /* VGETEXPPSZrb */ + }, + { /* 6856 */ + 498, + /* VGETEXPPSZrbk */ + }, + { /* 6857 */ + 499, + /* VGETEXPPSZrbkz */ + }, + { /* 6858 */ + 425, + /* VGETEXPPSZrk */ + }, + { /* 6859 */ + 426, + /* VGETEXPPSZrkz */ + }, + { /* 6860 */ + 207, + /* VGETEXPSDZm */ + }, + { /* 6861 */ + 208, + /* VGETEXPSDZmk */ + }, + { /* 6862 */ + 209, + /* VGETEXPSDZmkz */ + }, + { /* 6863 */ + 249, + /* VGETEXPSDZr */ + }, + { /* 6864 */ + 249, + /* VGETEXPSDZrb */ + }, + { /* 6865 */ + 250, + /* VGETEXPSDZrbk */ + }, + { /* 6866 */ + 251, + /* VGETEXPSDZrbkz */ + }, + { /* 6867 */ + 250, + /* VGETEXPSDZrk */ + }, + { /* 6868 */ + 251, + /* VGETEXPSDZrkz */ + }, + { /* 6869 */ + 237, + /* VGETEXPSSZm */ + }, + { /* 6870 */ + 238, + /* VGETEXPSSZmk */ + }, + { /* 6871 */ + 239, + /* VGETEXPSSZmkz */ + }, + { /* 6872 */ + 255, + /* VGETEXPSSZr */ + }, + { /* 6873 */ + 255, + /* VGETEXPSSZrb */ + }, + { /* 6874 */ + 256, + /* VGETEXPSSZrbk */ + }, + { /* 6875 */ + 257, + /* VGETEXPSSZrbkz */ + }, + { /* 6876 */ + 256, + /* VGETEXPSSZrk */ + }, + { /* 6877 */ + 257, + /* VGETEXPSSZrkz */ + }, + { /* 6878 */ + 589, + /* VGETMANTPDZ128rmbi */ + }, + { /* 6879 */ + 590, + /* VGETMANTPDZ128rmbik */ + }, + { /* 6880 */ + 591, + /* VGETMANTPDZ128rmbikz */ + }, + { /* 6881 */ + 592, + /* VGETMANTPDZ128rmi */ + }, + { /* 6882 */ + 593, + /* VGETMANTPDZ128rmik */ + }, + { /* 6883 */ + 594, + /* VGETMANTPDZ128rmikz */ + }, + { /* 6884 */ + 595, + /* VGETMANTPDZ128rri */ + }, + { /* 6885 */ + 596, + /* VGETMANTPDZ128rrik */ + }, + { /* 6886 */ + 597, + /* VGETMANTPDZ128rrikz */ + }, + { /* 6887 */ + 598, + /* VGETMANTPDZ256rmbi */ + }, + { /* 6888 */ + 599, + /* VGETMANTPDZ256rmbik */ + }, + { /* 6889 */ + 600, + /* VGETMANTPDZ256rmbikz */ + }, + { /* 6890 */ + 601, + /* VGETMANTPDZ256rmi */ + }, + { /* 6891 */ + 602, + /* VGETMANTPDZ256rmik */ + }, + { /* 6892 */ + 603, + /* VGETMANTPDZ256rmikz */ + }, + { /* 6893 */ + 604, + /* VGETMANTPDZ256rri */ + }, + { /* 6894 */ + 605, + /* VGETMANTPDZ256rrik */ + }, + { /* 6895 */ + 606, + /* VGETMANTPDZ256rrikz */ + }, + { /* 6896 */ + 607, + /* VGETMANTPDZrmbi */ + }, + { /* 6897 */ + 608, + /* VGETMANTPDZrmbik */ + }, + { /* 6898 */ + 609, + /* VGETMANTPDZrmbikz */ + }, + { /* 6899 */ + 610, + /* VGETMANTPDZrmi */ + }, + { /* 6900 */ + 611, + /* VGETMANTPDZrmik */ + }, + { /* 6901 */ + 612, + /* VGETMANTPDZrmikz */ + }, + { /* 6902 */ + 613, + /* VGETMANTPDZrri */ + }, + { /* 6903 */ + 614, + /* VGETMANTPDZrrib */ + }, + { /* 6904 */ + 615, + /* VGETMANTPDZrribk */ + }, + { /* 6905 */ + 616, + /* VGETMANTPDZrribkz */ + }, + { /* 6906 */ + 617, + /* VGETMANTPDZrrik */ + }, + { /* 6907 */ + 618, + /* VGETMANTPDZrrikz */ + }, + { /* 6908 */ + 619, + /* VGETMANTPSZ128rmbi */ + }, + { /* 6909 */ + 620, + /* VGETMANTPSZ128rmbik */ + }, + { /* 6910 */ + 621, + /* VGETMANTPSZ128rmbikz */ + }, + { /* 6911 */ + 592, + /* VGETMANTPSZ128rmi */ + }, + { /* 6912 */ + 593, + /* VGETMANTPSZ128rmik */ + }, + { /* 6913 */ + 594, + /* VGETMANTPSZ128rmikz */ + }, + { /* 6914 */ + 595, + /* VGETMANTPSZ128rri */ + }, + { /* 6915 */ + 596, + /* VGETMANTPSZ128rrik */ + }, + { /* 6916 */ + 597, + /* VGETMANTPSZ128rrikz */ + }, + { /* 6917 */ + 622, + /* VGETMANTPSZ256rmbi */ + }, + { /* 6918 */ + 623, + /* VGETMANTPSZ256rmbik */ + }, + { /* 6919 */ + 624, + /* VGETMANTPSZ256rmbikz */ + }, + { /* 6920 */ + 601, + /* VGETMANTPSZ256rmi */ + }, + { /* 6921 */ + 602, + /* VGETMANTPSZ256rmik */ + }, + { /* 6922 */ + 603, + /* VGETMANTPSZ256rmikz */ + }, + { /* 6923 */ + 604, + /* VGETMANTPSZ256rri */ + }, + { /* 6924 */ + 605, + /* VGETMANTPSZ256rrik */ + }, + { /* 6925 */ + 606, + /* VGETMANTPSZ256rrikz */ + }, + { /* 6926 */ + 625, + /* VGETMANTPSZrmbi */ + }, + { /* 6927 */ + 626, + /* VGETMANTPSZrmbik */ + }, + { /* 6928 */ + 627, + /* VGETMANTPSZrmbikz */ + }, + { /* 6929 */ + 610, + /* VGETMANTPSZrmi */ + }, + { /* 6930 */ + 611, + /* VGETMANTPSZrmik */ + }, + { /* 6931 */ + 612, + /* VGETMANTPSZrmikz */ + }, + { /* 6932 */ + 613, + /* VGETMANTPSZrri */ + }, + { /* 6933 */ + 628, + /* VGETMANTPSZrrib */ + }, + { /* 6934 */ + 629, + /* VGETMANTPSZrribk */ + }, + { /* 6935 */ + 630, + /* VGETMANTPSZrribkz */ + }, + { /* 6936 */ + 617, + /* VGETMANTPSZrrik */ + }, + { /* 6937 */ + 618, + /* VGETMANTPSZrrikz */ + }, + { /* 6938 */ + 288, + /* VGETMANTSDZrmi */ + }, + { /* 6939 */ + 289, + /* VGETMANTSDZrmik */ + }, + { /* 6940 */ + 290, + /* VGETMANTSDZrmikz */ + }, + { /* 6941 */ + 631, + /* VGETMANTSDZrri */ + }, + { /* 6942 */ + 631, + /* VGETMANTSDZrrib */ + }, + { /* 6943 */ + 524, + /* VGETMANTSDZrribk */ + }, + { /* 6944 */ + 632, + /* VGETMANTSDZrribkz */ + }, + { /* 6945 */ + 524, + /* VGETMANTSDZrrik */ + }, + { /* 6946 */ + 632, + /* VGETMANTSDZrrikz */ + }, + { /* 6947 */ + 261, + /* VGETMANTSSZrmi */ + }, + { /* 6948 */ + 262, + /* VGETMANTSSZrmik */ + }, + { /* 6949 */ + 263, + /* VGETMANTSSZrmikz */ + }, + { /* 6950 */ + 633, + /* VGETMANTSSZrri */ + }, + { /* 6951 */ + 633, + /* VGETMANTSSZrrib */ + }, + { /* 6952 */ + 526, + /* VGETMANTSSZrribk */ + }, + { /* 6953 */ + 634, + /* VGETMANTSSZrribkz */ + }, + { /* 6954 */ + 526, + /* VGETMANTSSZrrik */ + }, + { /* 6955 */ + 634, + /* VGETMANTSSZrrikz */ + }, + { /* 6956 */ + 297, + /* VGF2P8AFFINEINVQBYrmi */ + }, + { /* 6957 */ + 298, + /* VGF2P8AFFINEINVQBYrri */ + }, + { /* 6958 */ + 299, + /* VGF2P8AFFINEINVQBZ128rmbi */ + }, + { /* 6959 */ + 635, + /* VGF2P8AFFINEINVQBZ128rmbik */ + }, + { /* 6960 */ + 636, + /* VGF2P8AFFINEINVQBZ128rmbikz */ + }, + { /* 6961 */ + 264, + /* VGF2P8AFFINEINVQBZ128rmi */ + }, + { /* 6962 */ + 265, + /* VGF2P8AFFINEINVQBZ128rmik */ + }, + { /* 6963 */ + 266, + /* VGF2P8AFFINEINVQBZ128rmikz */ + }, + { /* 6964 */ + 267, + /* VGF2P8AFFINEINVQBZ128rri */ + }, + { /* 6965 */ + 268, + /* VGF2P8AFFINEINVQBZ128rrik */ + }, + { /* 6966 */ + 269, + /* VGF2P8AFFINEINVQBZ128rrikz */ + }, + { /* 6967 */ + 297, + /* VGF2P8AFFINEINVQBZ256rmbi */ + }, + { /* 6968 */ + 637, + /* VGF2P8AFFINEINVQBZ256rmbik */ + }, + { /* 6969 */ + 638, + /* VGF2P8AFFINEINVQBZ256rmbikz */ + }, + { /* 6970 */ + 273, + /* VGF2P8AFFINEINVQBZ256rmi */ + }, + { /* 6971 */ + 274, + /* VGF2P8AFFINEINVQBZ256rmik */ + }, + { /* 6972 */ + 275, + /* VGF2P8AFFINEINVQBZ256rmikz */ + }, + { /* 6973 */ + 276, + /* VGF2P8AFFINEINVQBZ256rri */ + }, + { /* 6974 */ + 277, + /* VGF2P8AFFINEINVQBZ256rrik */ + }, + { /* 6975 */ + 278, + /* VGF2P8AFFINEINVQBZ256rrikz */ + }, + { /* 6976 */ + 639, + /* VGF2P8AFFINEINVQBZrmbi */ + }, + { /* 6977 */ + 640, + /* VGF2P8AFFINEINVQBZrmbik */ + }, + { /* 6978 */ + 641, + /* VGF2P8AFFINEINVQBZrmbikz */ + }, + { /* 6979 */ + 282, + /* VGF2P8AFFINEINVQBZrmi */ + }, + { /* 6980 */ + 283, + /* VGF2P8AFFINEINVQBZrmik */ + }, + { /* 6981 */ + 284, + /* VGF2P8AFFINEINVQBZrmikz */ + }, + { /* 6982 */ + 285, + /* VGF2P8AFFINEINVQBZrri */ + }, + { /* 6983 */ + 286, + /* VGF2P8AFFINEINVQBZrrik */ + }, + { /* 6984 */ + 287, + /* VGF2P8AFFINEINVQBZrrikz */ + }, + { /* 6985 */ + 299, + /* VGF2P8AFFINEINVQBrmi */ + }, + { /* 6986 */ + 300, + /* VGF2P8AFFINEINVQBrri */ + }, + { /* 6987 */ + 297, + /* VGF2P8AFFINEQBYrmi */ + }, + { /* 6988 */ + 298, + /* VGF2P8AFFINEQBYrri */ + }, + { /* 6989 */ + 299, + /* VGF2P8AFFINEQBZ128rmbi */ + }, + { /* 6990 */ + 635, + /* VGF2P8AFFINEQBZ128rmbik */ + }, + { /* 6991 */ + 636, + /* VGF2P8AFFINEQBZ128rmbikz */ + }, + { /* 6992 */ + 264, + /* VGF2P8AFFINEQBZ128rmi */ + }, + { /* 6993 */ + 265, + /* VGF2P8AFFINEQBZ128rmik */ + }, + { /* 6994 */ + 266, + /* VGF2P8AFFINEQBZ128rmikz */ + }, + { /* 6995 */ + 267, + /* VGF2P8AFFINEQBZ128rri */ + }, + { /* 6996 */ + 268, + /* VGF2P8AFFINEQBZ128rrik */ + }, + { /* 6997 */ + 269, + /* VGF2P8AFFINEQBZ128rrikz */ + }, + { /* 6998 */ + 297, + /* VGF2P8AFFINEQBZ256rmbi */ + }, + { /* 6999 */ + 637, + /* VGF2P8AFFINEQBZ256rmbik */ + }, + { /* 7000 */ + 638, + /* VGF2P8AFFINEQBZ256rmbikz */ + }, + { /* 7001 */ + 273, + /* VGF2P8AFFINEQBZ256rmi */ + }, + { /* 7002 */ + 274, + /* VGF2P8AFFINEQBZ256rmik */ + }, + { /* 7003 */ + 275, + /* VGF2P8AFFINEQBZ256rmikz */ + }, + { /* 7004 */ + 276, + /* VGF2P8AFFINEQBZ256rri */ + }, + { /* 7005 */ + 277, + /* VGF2P8AFFINEQBZ256rrik */ + }, + { /* 7006 */ + 278, + /* VGF2P8AFFINEQBZ256rrikz */ + }, + { /* 7007 */ + 639, + /* VGF2P8AFFINEQBZrmbi */ + }, + { /* 7008 */ + 640, + /* VGF2P8AFFINEQBZrmbik */ + }, + { /* 7009 */ + 641, + /* VGF2P8AFFINEQBZrmbikz */ + }, + { /* 7010 */ + 282, + /* VGF2P8AFFINEQBZrmi */ + }, + { /* 7011 */ + 283, + /* VGF2P8AFFINEQBZrmik */ + }, + { /* 7012 */ + 284, + /* VGF2P8AFFINEQBZrmikz */ + }, + { /* 7013 */ + 285, + /* VGF2P8AFFINEQBZrri */ + }, + { /* 7014 */ + 286, + /* VGF2P8AFFINEQBZrrik */ + }, + { /* 7015 */ + 287, + /* VGF2P8AFFINEQBZrrikz */ + }, + { /* 7016 */ + 299, + /* VGF2P8AFFINEQBrmi */ + }, + { /* 7017 */ + 300, + /* VGF2P8AFFINEQBrri */ + }, + { /* 7018 */ + 204, + /* VGF2P8MULBYrm */ + }, + { /* 7019 */ + 205, + /* VGF2P8MULBYrr */ + }, + { /* 7020 */ + 206, + /* VGF2P8MULBZ128rm */ + }, + { /* 7021 */ + 203, + /* VGF2P8MULBZ128rmk */ + }, + { /* 7022 */ + 210, + /* VGF2P8MULBZ128rmkz */ + }, + { /* 7023 */ + 211, + /* VGF2P8MULBZ128rr */ + }, + { /* 7024 */ + 212, + /* VGF2P8MULBZ128rrk */ + }, + { /* 7025 */ + 213, + /* VGF2P8MULBZ128rrkz */ + }, + { /* 7026 */ + 214, + /* VGF2P8MULBZ256rm */ + }, + { /* 7027 */ + 218, + /* VGF2P8MULBZ256rmk */ + }, + { /* 7028 */ + 219, + /* VGF2P8MULBZ256rmkz */ + }, + { /* 7029 */ + 220, + /* VGF2P8MULBZ256rr */ + }, + { /* 7030 */ + 221, + /* VGF2P8MULBZ256rrk */ + }, + { /* 7031 */ + 222, + /* VGF2P8MULBZ256rrkz */ + }, + { /* 7032 */ + 223, + /* VGF2P8MULBZrm */ + }, + { /* 7033 */ + 227, + /* VGF2P8MULBZrmk */ + }, + { /* 7034 */ + 228, + /* VGF2P8MULBZrmkz */ + }, + { /* 7035 */ + 229, + /* VGF2P8MULBZrr */ + }, + { /* 7036 */ + 233, + /* VGF2P8MULBZrrk */ + }, + { /* 7037 */ + 234, + /* VGF2P8MULBZrrkz */ + }, + { /* 7038 */ + 235, + /* VGF2P8MULBrm */ + }, + { /* 7039 */ + 236, + /* VGF2P8MULBrr */ + }, + { /* 7040 */ + 204, + /* VHADDPDYrm */ + }, + { /* 7041 */ + 205, + /* VHADDPDYrr */ + }, + { /* 7042 */ + 235, + /* VHADDPDrm */ + }, + { /* 7043 */ + 236, + /* VHADDPDrr */ + }, + { /* 7044 */ + 204, + /* VHADDPSYrm */ + }, + { /* 7045 */ + 205, + /* VHADDPSYrr */ + }, + { /* 7046 */ + 235, + /* VHADDPSrm */ + }, + { /* 7047 */ + 236, + /* VHADDPSrr */ + }, + { /* 7048 */ + 204, + /* VHSUBPDYrm */ + }, + { /* 7049 */ + 205, + /* VHSUBPDYrr */ + }, + { /* 7050 */ + 235, + /* VHSUBPDrm */ + }, + { /* 7051 */ + 236, + /* VHSUBPDrr */ + }, + { /* 7052 */ + 204, + /* VHSUBPSYrm */ + }, + { /* 7053 */ + 205, + /* VHSUBPSYrr */ + }, + { /* 7054 */ + 235, + /* VHSUBPSrm */ + }, + { /* 7055 */ + 236, + /* VHSUBPSrr */ + }, + { /* 7056 */ + 297, + /* VINSERTF128rm */ + }, + { /* 7057 */ + 642, + /* VINSERTF128rr */ + }, + { /* 7058 */ + 643, + /* VINSERTF32x4Z256rm */ + }, + { /* 7059 */ + 644, + /* VINSERTF32x4Z256rmk */ + }, + { /* 7060 */ + 645, + /* VINSERTF32x4Z256rmkz */ + }, + { /* 7061 */ + 646, + /* VINSERTF32x4Z256rr */ + }, + { /* 7062 */ + 647, + /* VINSERTF32x4Z256rrk */ + }, + { /* 7063 */ + 648, + /* VINSERTF32x4Z256rrkz */ + }, + { /* 7064 */ + 649, + /* VINSERTF32x4Zrm */ + }, + { /* 7065 */ + 650, + /* VINSERTF32x4Zrmk */ + }, + { /* 7066 */ + 651, + /* VINSERTF32x4Zrmkz */ + }, + { /* 7067 */ + 652, + /* VINSERTF32x4Zrr */ + }, + { /* 7068 */ + 653, + /* VINSERTF32x4Zrrk */ + }, + { /* 7069 */ + 654, + /* VINSERTF32x4Zrrkz */ + }, + { /* 7070 */ + 655, + /* VINSERTF32x8Zrm */ + }, + { /* 7071 */ + 656, + /* VINSERTF32x8Zrmk */ + }, + { /* 7072 */ + 657, + /* VINSERTF32x8Zrmkz */ + }, + { /* 7073 */ + 658, + /* VINSERTF32x8Zrr */ + }, + { /* 7074 */ + 659, + /* VINSERTF32x8Zrrk */ + }, + { /* 7075 */ + 660, + /* VINSERTF32x8Zrrkz */ + }, + { /* 7076 */ + 643, + /* VINSERTF64x2Z256rm */ + }, + { /* 7077 */ + 644, + /* VINSERTF64x2Z256rmk */ + }, + { /* 7078 */ + 645, + /* VINSERTF64x2Z256rmkz */ + }, + { /* 7079 */ + 646, + /* VINSERTF64x2Z256rr */ + }, + { /* 7080 */ + 647, + /* VINSERTF64x2Z256rrk */ + }, + { /* 7081 */ + 648, + /* VINSERTF64x2Z256rrkz */ + }, + { /* 7082 */ + 649, + /* VINSERTF64x2Zrm */ + }, + { /* 7083 */ + 650, + /* VINSERTF64x2Zrmk */ + }, + { /* 7084 */ + 651, + /* VINSERTF64x2Zrmkz */ + }, + { /* 7085 */ + 652, + /* VINSERTF64x2Zrr */ + }, + { /* 7086 */ + 653, + /* VINSERTF64x2Zrrk */ + }, + { /* 7087 */ + 654, + /* VINSERTF64x2Zrrkz */ + }, + { /* 7088 */ + 655, + /* VINSERTF64x4Zrm */ + }, + { /* 7089 */ + 656, + /* VINSERTF64x4Zrmk */ + }, + { /* 7090 */ + 657, + /* VINSERTF64x4Zrmkz */ + }, + { /* 7091 */ + 658, + /* VINSERTF64x4Zrr */ + }, + { /* 7092 */ + 659, + /* VINSERTF64x4Zrrk */ + }, + { /* 7093 */ + 660, + /* VINSERTF64x4Zrrkz */ + }, + { /* 7094 */ + 297, + /* VINSERTI128rm */ + }, + { /* 7095 */ + 642, + /* VINSERTI128rr */ + }, + { /* 7096 */ + 643, + /* VINSERTI32x4Z256rm */ + }, + { /* 7097 */ + 644, + /* VINSERTI32x4Z256rmk */ + }, + { /* 7098 */ + 645, + /* VINSERTI32x4Z256rmkz */ + }, + { /* 7099 */ + 646, + /* VINSERTI32x4Z256rr */ + }, + { /* 7100 */ + 647, + /* VINSERTI32x4Z256rrk */ + }, + { /* 7101 */ + 648, + /* VINSERTI32x4Z256rrkz */ + }, + { /* 7102 */ + 649, + /* VINSERTI32x4Zrm */ + }, + { /* 7103 */ + 650, + /* VINSERTI32x4Zrmk */ + }, + { /* 7104 */ + 651, + /* VINSERTI32x4Zrmkz */ + }, + { /* 7105 */ + 652, + /* VINSERTI32x4Zrr */ + }, + { /* 7106 */ + 653, + /* VINSERTI32x4Zrrk */ + }, + { /* 7107 */ + 654, + /* VINSERTI32x4Zrrkz */ + }, + { /* 7108 */ + 655, + /* VINSERTI32x8Zrm */ + }, + { /* 7109 */ + 656, + /* VINSERTI32x8Zrmk */ + }, + { /* 7110 */ + 657, + /* VINSERTI32x8Zrmkz */ + }, + { /* 7111 */ + 658, + /* VINSERTI32x8Zrr */ + }, + { /* 7112 */ + 659, + /* VINSERTI32x8Zrrk */ + }, + { /* 7113 */ + 660, + /* VINSERTI32x8Zrrkz */ + }, + { /* 7114 */ + 643, + /* VINSERTI64x2Z256rm */ + }, + { /* 7115 */ + 644, + /* VINSERTI64x2Z256rmk */ + }, + { /* 7116 */ + 645, + /* VINSERTI64x2Z256rmkz */ + }, + { /* 7117 */ + 646, + /* VINSERTI64x2Z256rr */ + }, + { /* 7118 */ + 647, + /* VINSERTI64x2Z256rrk */ + }, + { /* 7119 */ + 648, + /* VINSERTI64x2Z256rrkz */ + }, + { /* 7120 */ + 649, + /* VINSERTI64x2Zrm */ + }, + { /* 7121 */ + 650, + /* VINSERTI64x2Zrmk */ + }, + { /* 7122 */ + 651, + /* VINSERTI64x2Zrmkz */ + }, + { /* 7123 */ + 652, + /* VINSERTI64x2Zrr */ + }, + { /* 7124 */ + 653, + /* VINSERTI64x2Zrrk */ + }, + { /* 7125 */ + 654, + /* VINSERTI64x2Zrrkz */ + }, + { /* 7126 */ + 655, + /* VINSERTI64x4Zrm */ + }, + { /* 7127 */ + 656, + /* VINSERTI64x4Zrmk */ + }, + { /* 7128 */ + 657, + /* VINSERTI64x4Zrmkz */ + }, + { /* 7129 */ + 658, + /* VINSERTI64x4Zrr */ + }, + { /* 7130 */ + 659, + /* VINSERTI64x4Zrrk */ + }, + { /* 7131 */ + 660, + /* VINSERTI64x4Zrrkz */ + }, + { /* 7132 */ + 261, + /* VINSERTPSZrm */ + }, + { /* 7133 */ + 267, + /* VINSERTPSZrr */ + }, + { /* 7134 */ + 299, + /* VINSERTPSrm */ + }, + { /* 7135 */ + 300, + /* VINSERTPSrr */ + }, + { /* 7136 */ + 305, + /* VLDDQUYrm */ + }, + { /* 7137 */ + 30, + /* VLDDQUrm */ + }, + { /* 7138 */ + 28, + /* VLDMXCSR */ + }, + { /* 7139 */ + 31, + /* VMASKMOVDQU */ + }, + { /* 7140 */ + 0, + /* */ + }, + { /* 7141 */ + 661, + /* VMASKMOVPDYmr */ + }, + { /* 7142 */ + 204, + /* VMASKMOVPDYrm */ + }, + { /* 7143 */ + 662, + /* VMASKMOVPDmr */ + }, + { /* 7144 */ + 235, + /* VMASKMOVPDrm */ + }, + { /* 7145 */ + 661, + /* VMASKMOVPSYmr */ + }, + { /* 7146 */ + 204, + /* VMASKMOVPSYrm */ + }, + { /* 7147 */ + 662, + /* VMASKMOVPSmr */ + }, + { /* 7148 */ + 235, + /* VMASKMOVPSrm */ + }, + { /* 7149 */ + 0, + /* */ + }, + { /* 7150 */ + 0, + /* */ + }, + { /* 7151 */ + 0, + /* */ + }, + { /* 7152 */ + 0, + /* */ + }, + { /* 7153 */ + 0, + /* */ + }, + { /* 7154 */ + 0, + /* */ + }, + { /* 7155 */ + 0, + /* */ + }, + { /* 7156 */ + 0, + /* */ + }, + { /* 7157 */ + 0, + /* */ + }, + { /* 7158 */ + 0, + /* */ + }, + { /* 7159 */ + 0, + /* */ + }, + { /* 7160 */ + 0, + /* */ + }, + { /* 7161 */ + 0, + /* */ + }, + { /* 7162 */ + 0, + /* */ + }, + { /* 7163 */ + 0, + /* */ + }, + { /* 7164 */ + 0, + /* */ + }, + { /* 7165 */ + 0, + /* */ + }, + { /* 7166 */ + 0, + /* */ + }, + { /* 7167 */ + 0, + /* */ + }, + { /* 7168 */ + 0, + /* */ + }, + { /* 7169 */ + 0, + /* */ + }, + { /* 7170 */ + 0, + /* */ + }, + { /* 7171 */ + 0, + /* */ + }, + { /* 7172 */ + 0, + /* */ + }, + { /* 7173 */ + 0, + /* */ + }, + { /* 7174 */ + 0, + /* */ + }, + { /* 7175 */ + 0, + /* */ + }, + { /* 7176 */ + 0, + /* */ + }, + { /* 7177 */ + 0, + /* */ + }, + { /* 7178 */ + 0, + /* */ + }, + { /* 7179 */ + 0, + /* */ + }, + { /* 7180 */ + 0, + /* */ + }, + { /* 7181 */ + 0, + /* */ + }, + { /* 7182 */ + 0, + /* */ + }, + { /* 7183 */ + 0, + /* */ + }, + { /* 7184 */ + 0, + /* */ + }, + { /* 7185 */ + 0, + /* */ + }, + { /* 7186 */ + 0, + /* */ + }, + { /* 7187 */ + 0, + /* */ + }, + { /* 7188 */ + 0, + /* */ + }, + { /* 7189 */ + 0, + /* */ + }, + { /* 7190 */ + 0, + /* */ + }, + { /* 7191 */ + 0, + /* */ + }, + { /* 7192 */ + 0, + /* */ + }, + { /* 7193 */ + 0, + /* */ + }, + { /* 7194 */ + 0, + /* */ + }, + { /* 7195 */ + 0, + /* */ + }, + { /* 7196 */ + 0, + /* */ + }, + { /* 7197 */ + 0, + /* */ + }, + { /* 7198 */ + 0, + /* */ + }, + { /* 7199 */ + 0, + /* */ + }, + { /* 7200 */ + 0, + /* */ + }, + { /* 7201 */ + 0, + /* */ + }, + { /* 7202 */ + 0, + /* */ + }, + { /* 7203 */ + 0, + /* */ + }, + { /* 7204 */ + 0, + /* */ + }, + { /* 7205 */ + 0, + /* */ + }, + { /* 7206 */ + 0, + /* */ + }, + { /* 7207 */ + 0, + /* */ + }, + { /* 7208 */ + 0, + /* */ + }, + { /* 7209 */ + 0, + /* */ + }, + { /* 7210 */ + 0, + /* */ + }, + { /* 7211 */ + 0, + /* */ + }, + { /* 7212 */ + 0, + /* */ + }, + { /* 7213 */ + 0, + /* */ + }, + { /* 7214 */ + 0, + /* */ + }, + { /* 7215 */ + 0, + /* */ + }, + { /* 7216 */ + 0, + /* */ + }, + { /* 7217 */ + 0, + /* */ + }, + { /* 7218 */ + 0, + /* */ + }, + { /* 7219 */ + 204, + /* VMAXPDYrm */ + }, + { /* 7220 */ + 205, + /* VMAXPDYrr */ + }, + { /* 7221 */ + 206, + /* VMAXPDZ128rm */ + }, + { /* 7222 */ + 207, + /* VMAXPDZ128rmb */ + }, + { /* 7223 */ + 208, + /* VMAXPDZ128rmbk */ + }, + { /* 7224 */ + 209, + /* VMAXPDZ128rmbkz */ + }, + { /* 7225 */ + 203, + /* VMAXPDZ128rmk */ + }, + { /* 7226 */ + 210, + /* VMAXPDZ128rmkz */ + }, + { /* 7227 */ + 211, + /* VMAXPDZ128rr */ + }, + { /* 7228 */ + 212, + /* VMAXPDZ128rrk */ + }, + { /* 7229 */ + 213, + /* VMAXPDZ128rrkz */ + }, + { /* 7230 */ + 214, + /* VMAXPDZ256rm */ + }, + { /* 7231 */ + 215, + /* VMAXPDZ256rmb */ + }, + { /* 7232 */ + 216, + /* VMAXPDZ256rmbk */ + }, + { /* 7233 */ + 217, + /* VMAXPDZ256rmbkz */ + }, + { /* 7234 */ + 218, + /* VMAXPDZ256rmk */ + }, + { /* 7235 */ + 219, + /* VMAXPDZ256rmkz */ + }, + { /* 7236 */ + 220, + /* VMAXPDZ256rr */ + }, + { /* 7237 */ + 221, + /* VMAXPDZ256rrk */ + }, + { /* 7238 */ + 222, + /* VMAXPDZ256rrkz */ + }, + { /* 7239 */ + 223, + /* VMAXPDZrm */ + }, + { /* 7240 */ + 224, + /* VMAXPDZrmb */ + }, + { /* 7241 */ + 225, + /* VMAXPDZrmbk */ + }, + { /* 7242 */ + 226, + /* VMAXPDZrmbkz */ + }, + { /* 7243 */ + 227, + /* VMAXPDZrmk */ + }, + { /* 7244 */ + 228, + /* VMAXPDZrmkz */ + }, + { /* 7245 */ + 229, + /* VMAXPDZrr */ + }, + { /* 7246 */ + 663, + /* VMAXPDZrrb */ + }, + { /* 7247 */ + 664, + /* VMAXPDZrrbk */ + }, + { /* 7248 */ + 665, + /* VMAXPDZrrbkz */ + }, + { /* 7249 */ + 233, + /* VMAXPDZrrk */ + }, + { /* 7250 */ + 234, + /* VMAXPDZrrkz */ + }, + { /* 7251 */ + 235, + /* VMAXPDrm */ + }, + { /* 7252 */ + 236, + /* VMAXPDrr */ + }, + { /* 7253 */ + 204, + /* VMAXPSYrm */ + }, + { /* 7254 */ + 205, + /* VMAXPSYrr */ + }, + { /* 7255 */ + 206, + /* VMAXPSZ128rm */ + }, + { /* 7256 */ + 237, + /* VMAXPSZ128rmb */ + }, + { /* 7257 */ + 238, + /* VMAXPSZ128rmbk */ + }, + { /* 7258 */ + 239, + /* VMAXPSZ128rmbkz */ + }, + { /* 7259 */ + 203, + /* VMAXPSZ128rmk */ + }, + { /* 7260 */ + 210, + /* VMAXPSZ128rmkz */ + }, + { /* 7261 */ + 211, + /* VMAXPSZ128rr */ + }, + { /* 7262 */ + 212, + /* VMAXPSZ128rrk */ + }, + { /* 7263 */ + 213, + /* VMAXPSZ128rrkz */ + }, + { /* 7264 */ + 214, + /* VMAXPSZ256rm */ + }, + { /* 7265 */ + 240, + /* VMAXPSZ256rmb */ + }, + { /* 7266 */ + 241, + /* VMAXPSZ256rmbk */ + }, + { /* 7267 */ + 242, + /* VMAXPSZ256rmbkz */ + }, + { /* 7268 */ + 218, + /* VMAXPSZ256rmk */ + }, + { /* 7269 */ + 219, + /* VMAXPSZ256rmkz */ + }, + { /* 7270 */ + 220, + /* VMAXPSZ256rr */ + }, + { /* 7271 */ + 221, + /* VMAXPSZ256rrk */ + }, + { /* 7272 */ + 222, + /* VMAXPSZ256rrkz */ + }, + { /* 7273 */ + 223, + /* VMAXPSZrm */ + }, + { /* 7274 */ + 243, + /* VMAXPSZrmb */ + }, + { /* 7275 */ + 244, + /* VMAXPSZrmbk */ + }, + { /* 7276 */ + 245, + /* VMAXPSZrmbkz */ + }, + { /* 7277 */ + 227, + /* VMAXPSZrmk */ + }, + { /* 7278 */ + 228, + /* VMAXPSZrmkz */ + }, + { /* 7279 */ + 229, + /* VMAXPSZrr */ + }, + { /* 7280 */ + 666, + /* VMAXPSZrrb */ + }, + { /* 7281 */ + 667, + /* VMAXPSZrrbk */ + }, + { /* 7282 */ + 668, + /* VMAXPSZrrbkz */ + }, + { /* 7283 */ + 233, + /* VMAXPSZrrk */ + }, + { /* 7284 */ + 234, + /* VMAXPSZrrkz */ + }, + { /* 7285 */ + 235, + /* VMAXPSrm */ + }, + { /* 7286 */ + 236, + /* VMAXPSrr */ + }, + { /* 7287 */ + 0, + /* */ + }, + { /* 7288 */ + 207, + /* VMAXSDZrm_Int */ + }, + { /* 7289 */ + 208, + /* VMAXSDZrm_Intk */ + }, + { /* 7290 */ + 209, + /* VMAXSDZrm_Intkz */ + }, + { /* 7291 */ + 0, + /* */ + }, + { /* 7292 */ + 249, + /* VMAXSDZrr_Int */ + }, + { /* 7293 */ + 250, + /* VMAXSDZrr_Intk */ + }, + { /* 7294 */ + 251, + /* VMAXSDZrr_Intkz */ + }, + { /* 7295 */ + 249, + /* VMAXSDZrrb_Int */ + }, + { /* 7296 */ + 250, + /* VMAXSDZrrb_Intk */ + }, + { /* 7297 */ + 251, + /* VMAXSDZrrb_Intkz */ + }, + { /* 7298 */ + 235, + /* VMAXSDrm */ + }, + { /* 7299 */ + 0, + /* */ + }, + { /* 7300 */ + 236, + /* VMAXSDrr */ + }, + { /* 7301 */ + 0, + /* */ + }, + { /* 7302 */ + 0, + /* */ + }, + { /* 7303 */ + 237, + /* VMAXSSZrm_Int */ + }, + { /* 7304 */ + 238, + /* VMAXSSZrm_Intk */ + }, + { /* 7305 */ + 239, + /* VMAXSSZrm_Intkz */ + }, + { /* 7306 */ + 0, + /* */ + }, + { /* 7307 */ + 255, + /* VMAXSSZrr_Int */ + }, + { /* 7308 */ + 256, + /* VMAXSSZrr_Intk */ + }, + { /* 7309 */ + 257, + /* VMAXSSZrr_Intkz */ + }, + { /* 7310 */ + 255, + /* VMAXSSZrrb_Int */ + }, + { /* 7311 */ + 256, + /* VMAXSSZrrb_Intk */ + }, + { /* 7312 */ + 257, + /* VMAXSSZrrb_Intkz */ + }, + { /* 7313 */ + 235, + /* VMAXSSrm */ + }, + { /* 7314 */ + 0, + /* */ + }, + { /* 7315 */ + 236, + /* VMAXSSrr */ + }, + { /* 7316 */ + 0, + /* */ + }, + { /* 7317 */ + 0, + /* VMCALL */ + }, + { /* 7318 */ + 28, + /* VMCLEARm */ + }, + { /* 7319 */ + 0, + /* VMFUNC */ + }, + { /* 7320 */ + 0, + /* */ + }, + { /* 7321 */ + 0, + /* */ + }, + { /* 7322 */ + 0, + /* */ + }, + { /* 7323 */ + 0, + /* */ + }, + { /* 7324 */ + 0, + /* */ + }, + { /* 7325 */ + 0, + /* */ + }, + { /* 7326 */ + 0, + /* */ + }, + { /* 7327 */ + 0, + /* */ + }, + { /* 7328 */ + 0, + /* */ + }, + { /* 7329 */ + 0, + /* */ + }, + { /* 7330 */ + 0, + /* */ + }, + { /* 7331 */ + 0, + /* */ + }, + { /* 7332 */ + 0, + /* */ + }, + { /* 7333 */ + 0, + /* */ + }, + { /* 7334 */ + 0, + /* */ + }, + { /* 7335 */ + 0, + /* */ + }, + { /* 7336 */ + 0, + /* */ + }, + { /* 7337 */ + 0, + /* */ + }, + { /* 7338 */ + 0, + /* */ + }, + { /* 7339 */ + 0, + /* */ + }, + { /* 7340 */ + 0, + /* */ + }, + { /* 7341 */ + 0, + /* */ + }, + { /* 7342 */ + 0, + /* */ + }, + { /* 7343 */ + 0, + /* */ + }, + { /* 7344 */ + 0, + /* */ + }, + { /* 7345 */ + 0, + /* */ + }, + { /* 7346 */ + 0, + /* */ + }, + { /* 7347 */ + 0, + /* */ + }, + { /* 7348 */ + 0, + /* */ + }, + { /* 7349 */ + 0, + /* */ + }, + { /* 7350 */ + 0, + /* */ + }, + { /* 7351 */ + 0, + /* */ + }, + { /* 7352 */ + 0, + /* */ + }, + { /* 7353 */ + 0, + /* */ + }, + { /* 7354 */ + 0, + /* */ + }, + { /* 7355 */ + 0, + /* */ + }, + { /* 7356 */ + 0, + /* */ + }, + { /* 7357 */ + 0, + /* */ + }, + { /* 7358 */ + 0, + /* */ + }, + { /* 7359 */ + 0, + /* */ + }, + { /* 7360 */ + 0, + /* */ + }, + { /* 7361 */ + 0, + /* */ + }, + { /* 7362 */ + 0, + /* */ + }, + { /* 7363 */ + 0, + /* */ + }, + { /* 7364 */ + 0, + /* */ + }, + { /* 7365 */ + 0, + /* */ + }, + { /* 7366 */ + 0, + /* */ + }, + { /* 7367 */ + 0, + /* */ + }, + { /* 7368 */ + 0, + /* */ + }, + { /* 7369 */ + 0, + /* */ + }, + { /* 7370 */ + 0, + /* */ + }, + { /* 7371 */ + 0, + /* */ + }, + { /* 7372 */ + 0, + /* */ + }, + { /* 7373 */ + 0, + /* */ + }, + { /* 7374 */ + 0, + /* */ + }, + { /* 7375 */ + 0, + /* */ + }, + { /* 7376 */ + 0, + /* */ + }, + { /* 7377 */ + 0, + /* */ + }, + { /* 7378 */ + 0, + /* */ + }, + { /* 7379 */ + 0, + /* */ + }, + { /* 7380 */ + 0, + /* */ + }, + { /* 7381 */ + 0, + /* */ + }, + { /* 7382 */ + 0, + /* */ + }, + { /* 7383 */ + 0, + /* */ + }, + { /* 7384 */ + 0, + /* */ + }, + { /* 7385 */ + 0, + /* */ + }, + { /* 7386 */ + 0, + /* */ + }, + { /* 7387 */ + 0, + /* */ + }, + { /* 7388 */ + 0, + /* */ + }, + { /* 7389 */ + 0, + /* */ + }, + { /* 7390 */ + 204, + /* VMINPDYrm */ + }, + { /* 7391 */ + 205, + /* VMINPDYrr */ + }, + { /* 7392 */ + 206, + /* VMINPDZ128rm */ + }, + { /* 7393 */ + 207, + /* VMINPDZ128rmb */ + }, + { /* 7394 */ + 208, + /* VMINPDZ128rmbk */ + }, + { /* 7395 */ + 209, + /* VMINPDZ128rmbkz */ + }, + { /* 7396 */ + 203, + /* VMINPDZ128rmk */ + }, + { /* 7397 */ + 210, + /* VMINPDZ128rmkz */ + }, + { /* 7398 */ + 211, + /* VMINPDZ128rr */ + }, + { /* 7399 */ + 212, + /* VMINPDZ128rrk */ + }, + { /* 7400 */ + 213, + /* VMINPDZ128rrkz */ + }, + { /* 7401 */ + 214, + /* VMINPDZ256rm */ + }, + { /* 7402 */ + 215, + /* VMINPDZ256rmb */ + }, + { /* 7403 */ + 216, + /* VMINPDZ256rmbk */ + }, + { /* 7404 */ + 217, + /* VMINPDZ256rmbkz */ + }, + { /* 7405 */ + 218, + /* VMINPDZ256rmk */ + }, + { /* 7406 */ + 219, + /* VMINPDZ256rmkz */ + }, + { /* 7407 */ + 220, + /* VMINPDZ256rr */ + }, + { /* 7408 */ + 221, + /* VMINPDZ256rrk */ + }, + { /* 7409 */ + 222, + /* VMINPDZ256rrkz */ + }, + { /* 7410 */ + 223, + /* VMINPDZrm */ + }, + { /* 7411 */ + 224, + /* VMINPDZrmb */ + }, + { /* 7412 */ + 225, + /* VMINPDZrmbk */ + }, + { /* 7413 */ + 226, + /* VMINPDZrmbkz */ + }, + { /* 7414 */ + 227, + /* VMINPDZrmk */ + }, + { /* 7415 */ + 228, + /* VMINPDZrmkz */ + }, + { /* 7416 */ + 229, + /* VMINPDZrr */ + }, + { /* 7417 */ + 663, + /* VMINPDZrrb */ + }, + { /* 7418 */ + 664, + /* VMINPDZrrbk */ + }, + { /* 7419 */ + 665, + /* VMINPDZrrbkz */ + }, + { /* 7420 */ + 233, + /* VMINPDZrrk */ + }, + { /* 7421 */ + 234, + /* VMINPDZrrkz */ + }, + { /* 7422 */ + 235, + /* VMINPDrm */ + }, + { /* 7423 */ + 236, + /* VMINPDrr */ + }, + { /* 7424 */ + 204, + /* VMINPSYrm */ + }, + { /* 7425 */ + 205, + /* VMINPSYrr */ + }, + { /* 7426 */ + 206, + /* VMINPSZ128rm */ + }, + { /* 7427 */ + 237, + /* VMINPSZ128rmb */ + }, + { /* 7428 */ + 238, + /* VMINPSZ128rmbk */ + }, + { /* 7429 */ + 239, + /* VMINPSZ128rmbkz */ + }, + { /* 7430 */ + 203, + /* VMINPSZ128rmk */ + }, + { /* 7431 */ + 210, + /* VMINPSZ128rmkz */ + }, + { /* 7432 */ + 211, + /* VMINPSZ128rr */ + }, + { /* 7433 */ + 212, + /* VMINPSZ128rrk */ + }, + { /* 7434 */ + 213, + /* VMINPSZ128rrkz */ + }, + { /* 7435 */ + 214, + /* VMINPSZ256rm */ + }, + { /* 7436 */ + 240, + /* VMINPSZ256rmb */ + }, + { /* 7437 */ + 241, + /* VMINPSZ256rmbk */ + }, + { /* 7438 */ + 242, + /* VMINPSZ256rmbkz */ + }, + { /* 7439 */ + 218, + /* VMINPSZ256rmk */ + }, + { /* 7440 */ + 219, + /* VMINPSZ256rmkz */ + }, + { /* 7441 */ + 220, + /* VMINPSZ256rr */ + }, + { /* 7442 */ + 221, + /* VMINPSZ256rrk */ + }, + { /* 7443 */ + 222, + /* VMINPSZ256rrkz */ + }, + { /* 7444 */ + 223, + /* VMINPSZrm */ + }, + { /* 7445 */ + 243, + /* VMINPSZrmb */ + }, + { /* 7446 */ + 244, + /* VMINPSZrmbk */ + }, + { /* 7447 */ + 245, + /* VMINPSZrmbkz */ + }, + { /* 7448 */ + 227, + /* VMINPSZrmk */ + }, + { /* 7449 */ + 228, + /* VMINPSZrmkz */ + }, + { /* 7450 */ + 229, + /* VMINPSZrr */ + }, + { /* 7451 */ + 666, + /* VMINPSZrrb */ + }, + { /* 7452 */ + 667, + /* VMINPSZrrbk */ + }, + { /* 7453 */ + 668, + /* VMINPSZrrbkz */ + }, + { /* 7454 */ + 233, + /* VMINPSZrrk */ + }, + { /* 7455 */ + 234, + /* VMINPSZrrkz */ + }, + { /* 7456 */ + 235, + /* VMINPSrm */ + }, + { /* 7457 */ + 236, + /* VMINPSrr */ + }, + { /* 7458 */ + 0, + /* */ + }, + { /* 7459 */ + 207, + /* VMINSDZrm_Int */ + }, + { /* 7460 */ + 208, + /* VMINSDZrm_Intk */ + }, + { /* 7461 */ + 209, + /* VMINSDZrm_Intkz */ + }, + { /* 7462 */ + 0, + /* */ + }, + { /* 7463 */ + 249, + /* VMINSDZrr_Int */ + }, + { /* 7464 */ + 250, + /* VMINSDZrr_Intk */ + }, + { /* 7465 */ + 251, + /* VMINSDZrr_Intkz */ + }, + { /* 7466 */ + 249, + /* VMINSDZrrb_Int */ + }, + { /* 7467 */ + 250, + /* VMINSDZrrb_Intk */ + }, + { /* 7468 */ + 251, + /* VMINSDZrrb_Intkz */ + }, + { /* 7469 */ + 235, + /* VMINSDrm */ + }, + { /* 7470 */ + 0, + /* */ + }, + { /* 7471 */ + 236, + /* VMINSDrr */ + }, + { /* 7472 */ + 0, + /* */ + }, + { /* 7473 */ + 0, + /* */ + }, + { /* 7474 */ + 237, + /* VMINSSZrm_Int */ + }, + { /* 7475 */ + 238, + /* VMINSSZrm_Intk */ + }, + { /* 7476 */ + 239, + /* VMINSSZrm_Intkz */ + }, + { /* 7477 */ + 0, + /* */ + }, + { /* 7478 */ + 255, + /* VMINSSZrr_Int */ + }, + { /* 7479 */ + 256, + /* VMINSSZrr_Intk */ + }, + { /* 7480 */ + 257, + /* VMINSSZrr_Intkz */ + }, + { /* 7481 */ + 255, + /* VMINSSZrrb_Int */ + }, + { /* 7482 */ + 256, + /* VMINSSZrrb_Intk */ + }, + { /* 7483 */ + 257, + /* VMINSSZrrb_Intkz */ + }, + { /* 7484 */ + 235, + /* VMINSSrm */ + }, + { /* 7485 */ + 0, + /* */ + }, + { /* 7486 */ + 236, + /* VMINSSrr */ + }, + { /* 7487 */ + 0, + /* */ + }, + { /* 7488 */ + 0, + /* VMLAUNCH */ + }, + { /* 7489 */ + 0, + /* VMLOAD32 */ + }, + { /* 7490 */ + 0, + /* VMLOAD64 */ + }, + { /* 7491 */ + 0, + /* VMMCALL */ + }, + { /* 7492 */ + 327, + /* VMOV64toPQIZrm */ + }, + { /* 7493 */ + 669, + /* VMOV64toPQIZrr */ + }, + { /* 7494 */ + 30, + /* VMOV64toPQIrm */ + }, + { /* 7495 */ + 90, + /* VMOV64toPQIrr */ + }, + { /* 7496 */ + 0, + /* */ + }, + { /* 7497 */ + 0, + /* */ + }, + { /* 7498 */ + 0, + /* */ + }, + { /* 7499 */ + 0, + /* */ + }, + { /* 7500 */ + 670, + /* VMOVAPDYmr */ + }, + { /* 7501 */ + 305, + /* VMOVAPDYrm */ + }, + { /* 7502 */ + 408, + /* VMOVAPDYrr */ + }, + { /* 7503 */ + 671, + /* VMOVAPDYrr_REV */ + }, + { /* 7504 */ + 672, + /* VMOVAPDZ128mr */ + }, + { /* 7505 */ + 673, + /* VMOVAPDZ128mrk */ + }, + { /* 7506 */ + 409, + /* VMOVAPDZ128rm */ + }, + { /* 7507 */ + 410, + /* VMOVAPDZ128rmk */ + }, + { /* 7508 */ + 411, + /* VMOVAPDZ128rmkz */ + }, + { /* 7509 */ + 330, + /* VMOVAPDZ128rr */ + }, + { /* 7510 */ + 381, + /* VMOVAPDZ128rr_REV */ + }, + { /* 7511 */ + 331, + /* VMOVAPDZ128rrk */ + }, + { /* 7512 */ + 383, + /* VMOVAPDZ128rrk_REV */ + }, + { /* 7513 */ + 332, + /* VMOVAPDZ128rrkz */ + }, + { /* 7514 */ + 383, + /* VMOVAPDZ128rrkz_REV */ + }, + { /* 7515 */ + 674, + /* VMOVAPDZ256mr */ + }, + { /* 7516 */ + 675, + /* VMOVAPDZ256mrk */ + }, + { /* 7517 */ + 412, + /* VMOVAPDZ256rm */ + }, + { /* 7518 */ + 413, + /* VMOVAPDZ256rmk */ + }, + { /* 7519 */ + 414, + /* VMOVAPDZ256rmkz */ + }, + { /* 7520 */ + 415, + /* VMOVAPDZ256rr */ + }, + { /* 7521 */ + 386, + /* VMOVAPDZ256rr_REV */ + }, + { /* 7522 */ + 416, + /* VMOVAPDZ256rrk */ + }, + { /* 7523 */ + 388, + /* VMOVAPDZ256rrk_REV */ + }, + { /* 7524 */ + 417, + /* VMOVAPDZ256rrkz */ + }, + { /* 7525 */ + 388, + /* VMOVAPDZ256rrkz_REV */ + }, + { /* 7526 */ + 676, + /* VMOVAPDZmr */ + }, + { /* 7527 */ + 677, + /* VMOVAPDZmrk */ + }, + { /* 7528 */ + 418, + /* VMOVAPDZrm */ + }, + { /* 7529 */ + 419, + /* VMOVAPDZrmk */ + }, + { /* 7530 */ + 420, + /* VMOVAPDZrmkz */ + }, + { /* 7531 */ + 421, + /* VMOVAPDZrr */ + }, + { /* 7532 */ + 391, + /* VMOVAPDZrr_REV */ + }, + { /* 7533 */ + 425, + /* VMOVAPDZrrk */ + }, + { /* 7534 */ + 393, + /* VMOVAPDZrrk_REV */ + }, + { /* 7535 */ + 426, + /* VMOVAPDZrrkz */ + }, + { /* 7536 */ + 393, + /* VMOVAPDZrrkz_REV */ + }, + { /* 7537 */ + 169, + /* VMOVAPDmr */ + }, + { /* 7538 */ + 30, + /* VMOVAPDrm */ + }, + { /* 7539 */ + 31, + /* VMOVAPDrr */ + }, + { /* 7540 */ + 170, + /* VMOVAPDrr_REV */ + }, + { /* 7541 */ + 670, + /* VMOVAPSYmr */ + }, + { /* 7542 */ + 305, + /* VMOVAPSYrm */ + }, + { /* 7543 */ + 408, + /* VMOVAPSYrr */ + }, + { /* 7544 */ + 671, + /* VMOVAPSYrr_REV */ + }, + { /* 7545 */ + 672, + /* VMOVAPSZ128mr */ + }, + { /* 7546 */ + 673, + /* VMOVAPSZ128mrk */ + }, + { /* 7547 */ + 409, + /* VMOVAPSZ128rm */ + }, + { /* 7548 */ + 410, + /* VMOVAPSZ128rmk */ + }, + { /* 7549 */ + 411, + /* VMOVAPSZ128rmkz */ + }, + { /* 7550 */ + 330, + /* VMOVAPSZ128rr */ + }, + { /* 7551 */ + 381, + /* VMOVAPSZ128rr_REV */ + }, + { /* 7552 */ + 331, + /* VMOVAPSZ128rrk */ + }, + { /* 7553 */ + 383, + /* VMOVAPSZ128rrk_REV */ + }, + { /* 7554 */ + 332, + /* VMOVAPSZ128rrkz */ + }, + { /* 7555 */ + 383, + /* VMOVAPSZ128rrkz_REV */ + }, + { /* 7556 */ + 674, + /* VMOVAPSZ256mr */ + }, + { /* 7557 */ + 675, + /* VMOVAPSZ256mrk */ + }, + { /* 7558 */ + 412, + /* VMOVAPSZ256rm */ + }, + { /* 7559 */ + 413, + /* VMOVAPSZ256rmk */ + }, + { /* 7560 */ + 414, + /* VMOVAPSZ256rmkz */ + }, + { /* 7561 */ + 415, + /* VMOVAPSZ256rr */ + }, + { /* 7562 */ + 386, + /* VMOVAPSZ256rr_REV */ + }, + { /* 7563 */ + 416, + /* VMOVAPSZ256rrk */ + }, + { /* 7564 */ + 388, + /* VMOVAPSZ256rrk_REV */ + }, + { /* 7565 */ + 417, + /* VMOVAPSZ256rrkz */ + }, + { /* 7566 */ + 388, + /* VMOVAPSZ256rrkz_REV */ + }, + { /* 7567 */ + 676, + /* VMOVAPSZmr */ + }, + { /* 7568 */ + 677, + /* VMOVAPSZmrk */ + }, + { /* 7569 */ + 418, + /* VMOVAPSZrm */ + }, + { /* 7570 */ + 419, + /* VMOVAPSZrmk */ + }, + { /* 7571 */ + 420, + /* VMOVAPSZrmkz */ + }, + { /* 7572 */ + 421, + /* VMOVAPSZrr */ + }, + { /* 7573 */ + 391, + /* VMOVAPSZrr_REV */ + }, + { /* 7574 */ + 425, + /* VMOVAPSZrrk */ + }, + { /* 7575 */ + 393, + /* VMOVAPSZrrk_REV */ + }, + { /* 7576 */ + 426, + /* VMOVAPSZrrkz */ + }, + { /* 7577 */ + 393, + /* VMOVAPSZrrkz_REV */ + }, + { /* 7578 */ + 169, + /* VMOVAPSmr */ + }, + { /* 7579 */ + 30, + /* VMOVAPSrm */ + }, + { /* 7580 */ + 31, + /* VMOVAPSrr */ + }, + { /* 7581 */ + 170, + /* VMOVAPSrr_REV */ + }, + { /* 7582 */ + 305, + /* VMOVDDUPYrm */ + }, + { /* 7583 */ + 408, + /* VMOVDDUPYrr */ + }, + { /* 7584 */ + 327, + /* VMOVDDUPZ128rm */ + }, + { /* 7585 */ + 328, + /* VMOVDDUPZ128rmk */ + }, + { /* 7586 */ + 329, + /* VMOVDDUPZ128rmkz */ + }, + { /* 7587 */ + 330, + /* VMOVDDUPZ128rr */ + }, + { /* 7588 */ + 331, + /* VMOVDDUPZ128rrk */ + }, + { /* 7589 */ + 332, + /* VMOVDDUPZ128rrkz */ + }, + { /* 7590 */ + 412, + /* VMOVDDUPZ256rm */ + }, + { /* 7591 */ + 413, + /* VMOVDDUPZ256rmk */ + }, + { /* 7592 */ + 414, + /* VMOVDDUPZ256rmkz */ + }, + { /* 7593 */ + 415, + /* VMOVDDUPZ256rr */ + }, + { /* 7594 */ + 416, + /* VMOVDDUPZ256rrk */ + }, + { /* 7595 */ + 417, + /* VMOVDDUPZ256rrkz */ + }, + { /* 7596 */ + 418, + /* VMOVDDUPZrm */ + }, + { /* 7597 */ + 419, + /* VMOVDDUPZrmk */ + }, + { /* 7598 */ + 420, + /* VMOVDDUPZrmkz */ + }, + { /* 7599 */ + 421, + /* VMOVDDUPZrr */ + }, + { /* 7600 */ + 425, + /* VMOVDDUPZrrk */ + }, + { /* 7601 */ + 426, + /* VMOVDDUPZrrkz */ + }, + { /* 7602 */ + 30, + /* VMOVDDUPrm */ + }, + { /* 7603 */ + 31, + /* VMOVDDUPrr */ + }, + { /* 7604 */ + 334, + /* VMOVDI2PDIZrm */ + }, + { /* 7605 */ + 678, + /* VMOVDI2PDIZrr */ + }, + { /* 7606 */ + 30, + /* VMOVDI2PDIrm */ + }, + { /* 7607 */ + 89, + /* VMOVDI2PDIrr */ + }, + { /* 7608 */ + 0, + /* */ + }, + { /* 7609 */ + 0, + /* */ + }, + { /* 7610 */ + 0, + /* */ + }, + { /* 7611 */ + 0, + /* */ + }, + { /* 7612 */ + 672, + /* VMOVDQA32Z128mr */ + }, + { /* 7613 */ + 673, + /* VMOVDQA32Z128mrk */ + }, + { /* 7614 */ + 409, + /* VMOVDQA32Z128rm */ + }, + { /* 7615 */ + 410, + /* VMOVDQA32Z128rmk */ + }, + { /* 7616 */ + 411, + /* VMOVDQA32Z128rmkz */ + }, + { /* 7617 */ + 330, + /* VMOVDQA32Z128rr */ + }, + { /* 7618 */ + 381, + /* VMOVDQA32Z128rr_REV */ + }, + { /* 7619 */ + 331, + /* VMOVDQA32Z128rrk */ + }, + { /* 7620 */ + 383, + /* VMOVDQA32Z128rrk_REV */ + }, + { /* 7621 */ + 332, + /* VMOVDQA32Z128rrkz */ + }, + { /* 7622 */ + 383, + /* VMOVDQA32Z128rrkz_REV */ + }, + { /* 7623 */ + 674, + /* VMOVDQA32Z256mr */ + }, + { /* 7624 */ + 675, + /* VMOVDQA32Z256mrk */ + }, + { /* 7625 */ + 412, + /* VMOVDQA32Z256rm */ + }, + { /* 7626 */ + 413, + /* VMOVDQA32Z256rmk */ + }, + { /* 7627 */ + 414, + /* VMOVDQA32Z256rmkz */ + }, + { /* 7628 */ + 415, + /* VMOVDQA32Z256rr */ + }, + { /* 7629 */ + 386, + /* VMOVDQA32Z256rr_REV */ + }, + { /* 7630 */ + 416, + /* VMOVDQA32Z256rrk */ + }, + { /* 7631 */ + 388, + /* VMOVDQA32Z256rrk_REV */ + }, + { /* 7632 */ + 417, + /* VMOVDQA32Z256rrkz */ + }, + { /* 7633 */ + 388, + /* VMOVDQA32Z256rrkz_REV */ + }, + { /* 7634 */ + 676, + /* VMOVDQA32Zmr */ + }, + { /* 7635 */ + 677, + /* VMOVDQA32Zmrk */ + }, + { /* 7636 */ + 418, + /* VMOVDQA32Zrm */ + }, + { /* 7637 */ + 419, + /* VMOVDQA32Zrmk */ + }, + { /* 7638 */ + 420, + /* VMOVDQA32Zrmkz */ + }, + { /* 7639 */ + 421, + /* VMOVDQA32Zrr */ + }, + { /* 7640 */ + 391, + /* VMOVDQA32Zrr_REV */ + }, + { /* 7641 */ + 425, + /* VMOVDQA32Zrrk */ + }, + { /* 7642 */ + 393, + /* VMOVDQA32Zrrk_REV */ + }, + { /* 7643 */ + 426, + /* VMOVDQA32Zrrkz */ + }, + { /* 7644 */ + 393, + /* VMOVDQA32Zrrkz_REV */ + }, + { /* 7645 */ + 672, + /* VMOVDQA64Z128mr */ + }, + { /* 7646 */ + 673, + /* VMOVDQA64Z128mrk */ + }, + { /* 7647 */ + 409, + /* VMOVDQA64Z128rm */ + }, + { /* 7648 */ + 410, + /* VMOVDQA64Z128rmk */ + }, + { /* 7649 */ + 411, + /* VMOVDQA64Z128rmkz */ + }, + { /* 7650 */ + 330, + /* VMOVDQA64Z128rr */ + }, + { /* 7651 */ + 381, + /* VMOVDQA64Z128rr_REV */ + }, + { /* 7652 */ + 331, + /* VMOVDQA64Z128rrk */ + }, + { /* 7653 */ + 383, + /* VMOVDQA64Z128rrk_REV */ + }, + { /* 7654 */ + 332, + /* VMOVDQA64Z128rrkz */ + }, + { /* 7655 */ + 383, + /* VMOVDQA64Z128rrkz_REV */ + }, + { /* 7656 */ + 674, + /* VMOVDQA64Z256mr */ + }, + { /* 7657 */ + 675, + /* VMOVDQA64Z256mrk */ + }, + { /* 7658 */ + 412, + /* VMOVDQA64Z256rm */ + }, + { /* 7659 */ + 413, + /* VMOVDQA64Z256rmk */ + }, + { /* 7660 */ + 414, + /* VMOVDQA64Z256rmkz */ + }, + { /* 7661 */ + 415, + /* VMOVDQA64Z256rr */ + }, + { /* 7662 */ + 386, + /* VMOVDQA64Z256rr_REV */ + }, + { /* 7663 */ + 416, + /* VMOVDQA64Z256rrk */ + }, + { /* 7664 */ + 388, + /* VMOVDQA64Z256rrk_REV */ + }, + { /* 7665 */ + 417, + /* VMOVDQA64Z256rrkz */ + }, + { /* 7666 */ + 388, + /* VMOVDQA64Z256rrkz_REV */ + }, + { /* 7667 */ + 676, + /* VMOVDQA64Zmr */ + }, + { /* 7668 */ + 677, + /* VMOVDQA64Zmrk */ + }, + { /* 7669 */ + 418, + /* VMOVDQA64Zrm */ + }, + { /* 7670 */ + 419, + /* VMOVDQA64Zrmk */ + }, + { /* 7671 */ + 420, + /* VMOVDQA64Zrmkz */ + }, + { /* 7672 */ + 421, + /* VMOVDQA64Zrr */ + }, + { /* 7673 */ + 391, + /* VMOVDQA64Zrr_REV */ + }, + { /* 7674 */ + 425, + /* VMOVDQA64Zrrk */ + }, + { /* 7675 */ + 393, + /* VMOVDQA64Zrrk_REV */ + }, + { /* 7676 */ + 426, + /* VMOVDQA64Zrrkz */ + }, + { /* 7677 */ + 393, + /* VMOVDQA64Zrrkz_REV */ + }, + { /* 7678 */ + 670, + /* VMOVDQAYmr */ + }, + { /* 7679 */ + 305, + /* VMOVDQAYrm */ + }, + { /* 7680 */ + 408, + /* VMOVDQAYrr */ + }, + { /* 7681 */ + 671, + /* VMOVDQAYrr_REV */ + }, + { /* 7682 */ + 169, + /* VMOVDQAmr */ + }, + { /* 7683 */ + 30, + /* VMOVDQArm */ + }, + { /* 7684 */ + 31, + /* VMOVDQArr */ + }, + { /* 7685 */ + 170, + /* VMOVDQArr_REV */ + }, + { /* 7686 */ + 672, + /* VMOVDQU16Z128mr */ + }, + { /* 7687 */ + 673, + /* VMOVDQU16Z128mrk */ + }, + { /* 7688 */ + 409, + /* VMOVDQU16Z128rm */ + }, + { /* 7689 */ + 410, + /* VMOVDQU16Z128rmk */ + }, + { /* 7690 */ + 411, + /* VMOVDQU16Z128rmkz */ + }, + { /* 7691 */ + 330, + /* VMOVDQU16Z128rr */ + }, + { /* 7692 */ + 381, + /* VMOVDQU16Z128rr_REV */ + }, + { /* 7693 */ + 331, + /* VMOVDQU16Z128rrk */ + }, + { /* 7694 */ + 383, + /* VMOVDQU16Z128rrk_REV */ + }, + { /* 7695 */ + 332, + /* VMOVDQU16Z128rrkz */ + }, + { /* 7696 */ + 383, + /* VMOVDQU16Z128rrkz_REV */ + }, + { /* 7697 */ + 674, + /* VMOVDQU16Z256mr */ + }, + { /* 7698 */ + 675, + /* VMOVDQU16Z256mrk */ + }, + { /* 7699 */ + 412, + /* VMOVDQU16Z256rm */ + }, + { /* 7700 */ + 413, + /* VMOVDQU16Z256rmk */ + }, + { /* 7701 */ + 414, + /* VMOVDQU16Z256rmkz */ + }, + { /* 7702 */ + 415, + /* VMOVDQU16Z256rr */ + }, + { /* 7703 */ + 386, + /* VMOVDQU16Z256rr_REV */ + }, + { /* 7704 */ + 416, + /* VMOVDQU16Z256rrk */ + }, + { /* 7705 */ + 388, + /* VMOVDQU16Z256rrk_REV */ + }, + { /* 7706 */ + 417, + /* VMOVDQU16Z256rrkz */ + }, + { /* 7707 */ + 388, + /* VMOVDQU16Z256rrkz_REV */ + }, + { /* 7708 */ + 676, + /* VMOVDQU16Zmr */ + }, + { /* 7709 */ + 677, + /* VMOVDQU16Zmrk */ + }, + { /* 7710 */ + 418, + /* VMOVDQU16Zrm */ + }, + { /* 7711 */ + 419, + /* VMOVDQU16Zrmk */ + }, + { /* 7712 */ + 420, + /* VMOVDQU16Zrmkz */ + }, + { /* 7713 */ + 421, + /* VMOVDQU16Zrr */ + }, + { /* 7714 */ + 391, + /* VMOVDQU16Zrr_REV */ + }, + { /* 7715 */ + 425, + /* VMOVDQU16Zrrk */ + }, + { /* 7716 */ + 393, + /* VMOVDQU16Zrrk_REV */ + }, + { /* 7717 */ + 426, + /* VMOVDQU16Zrrkz */ + }, + { /* 7718 */ + 393, + /* VMOVDQU16Zrrkz_REV */ + }, + { /* 7719 */ + 672, + /* VMOVDQU32Z128mr */ + }, + { /* 7720 */ + 673, + /* VMOVDQU32Z128mrk */ + }, + { /* 7721 */ + 409, + /* VMOVDQU32Z128rm */ + }, + { /* 7722 */ + 410, + /* VMOVDQU32Z128rmk */ + }, + { /* 7723 */ + 411, + /* VMOVDQU32Z128rmkz */ + }, + { /* 7724 */ + 330, + /* VMOVDQU32Z128rr */ + }, + { /* 7725 */ + 381, + /* VMOVDQU32Z128rr_REV */ + }, + { /* 7726 */ + 331, + /* VMOVDQU32Z128rrk */ + }, + { /* 7727 */ + 383, + /* VMOVDQU32Z128rrk_REV */ + }, + { /* 7728 */ + 332, + /* VMOVDQU32Z128rrkz */ + }, + { /* 7729 */ + 383, + /* VMOVDQU32Z128rrkz_REV */ + }, + { /* 7730 */ + 674, + /* VMOVDQU32Z256mr */ + }, + { /* 7731 */ + 675, + /* VMOVDQU32Z256mrk */ + }, + { /* 7732 */ + 412, + /* VMOVDQU32Z256rm */ + }, + { /* 7733 */ + 413, + /* VMOVDQU32Z256rmk */ + }, + { /* 7734 */ + 414, + /* VMOVDQU32Z256rmkz */ + }, + { /* 7735 */ + 415, + /* VMOVDQU32Z256rr */ + }, + { /* 7736 */ + 386, + /* VMOVDQU32Z256rr_REV */ + }, + { /* 7737 */ + 416, + /* VMOVDQU32Z256rrk */ + }, + { /* 7738 */ + 388, + /* VMOVDQU32Z256rrk_REV */ + }, + { /* 7739 */ + 417, + /* VMOVDQU32Z256rrkz */ + }, + { /* 7740 */ + 388, + /* VMOVDQU32Z256rrkz_REV */ + }, + { /* 7741 */ + 676, + /* VMOVDQU32Zmr */ + }, + { /* 7742 */ + 677, + /* VMOVDQU32Zmrk */ + }, + { /* 7743 */ + 418, + /* VMOVDQU32Zrm */ + }, + { /* 7744 */ + 419, + /* VMOVDQU32Zrmk */ + }, + { /* 7745 */ + 420, + /* VMOVDQU32Zrmkz */ + }, + { /* 7746 */ + 421, + /* VMOVDQU32Zrr */ + }, + { /* 7747 */ + 391, + /* VMOVDQU32Zrr_REV */ + }, + { /* 7748 */ + 425, + /* VMOVDQU32Zrrk */ + }, + { /* 7749 */ + 393, + /* VMOVDQU32Zrrk_REV */ + }, + { /* 7750 */ + 426, + /* VMOVDQU32Zrrkz */ + }, + { /* 7751 */ + 393, + /* VMOVDQU32Zrrkz_REV */ + }, + { /* 7752 */ + 672, + /* VMOVDQU64Z128mr */ + }, + { /* 7753 */ + 673, + /* VMOVDQU64Z128mrk */ + }, + { /* 7754 */ + 409, + /* VMOVDQU64Z128rm */ + }, + { /* 7755 */ + 410, + /* VMOVDQU64Z128rmk */ + }, + { /* 7756 */ + 411, + /* VMOVDQU64Z128rmkz */ + }, + { /* 7757 */ + 330, + /* VMOVDQU64Z128rr */ + }, + { /* 7758 */ + 381, + /* VMOVDQU64Z128rr_REV */ + }, + { /* 7759 */ + 331, + /* VMOVDQU64Z128rrk */ + }, + { /* 7760 */ + 383, + /* VMOVDQU64Z128rrk_REV */ + }, + { /* 7761 */ + 332, + /* VMOVDQU64Z128rrkz */ + }, + { /* 7762 */ + 383, + /* VMOVDQU64Z128rrkz_REV */ + }, + { /* 7763 */ + 674, + /* VMOVDQU64Z256mr */ + }, + { /* 7764 */ + 675, + /* VMOVDQU64Z256mrk */ + }, + { /* 7765 */ + 412, + /* VMOVDQU64Z256rm */ + }, + { /* 7766 */ + 413, + /* VMOVDQU64Z256rmk */ + }, + { /* 7767 */ + 414, + /* VMOVDQU64Z256rmkz */ + }, + { /* 7768 */ + 415, + /* VMOVDQU64Z256rr */ + }, + { /* 7769 */ + 386, + /* VMOVDQU64Z256rr_REV */ + }, + { /* 7770 */ + 416, + /* VMOVDQU64Z256rrk */ + }, + { /* 7771 */ + 388, + /* VMOVDQU64Z256rrk_REV */ + }, + { /* 7772 */ + 417, + /* VMOVDQU64Z256rrkz */ + }, + { /* 7773 */ + 388, + /* VMOVDQU64Z256rrkz_REV */ + }, + { /* 7774 */ + 676, + /* VMOVDQU64Zmr */ + }, + { /* 7775 */ + 677, + /* VMOVDQU64Zmrk */ + }, + { /* 7776 */ + 418, + /* VMOVDQU64Zrm */ + }, + { /* 7777 */ + 419, + /* VMOVDQU64Zrmk */ + }, + { /* 7778 */ + 420, + /* VMOVDQU64Zrmkz */ + }, + { /* 7779 */ + 421, + /* VMOVDQU64Zrr */ + }, + { /* 7780 */ + 391, + /* VMOVDQU64Zrr_REV */ + }, + { /* 7781 */ + 425, + /* VMOVDQU64Zrrk */ + }, + { /* 7782 */ + 393, + /* VMOVDQU64Zrrk_REV */ + }, + { /* 7783 */ + 426, + /* VMOVDQU64Zrrkz */ + }, + { /* 7784 */ + 393, + /* VMOVDQU64Zrrkz_REV */ + }, + { /* 7785 */ + 672, + /* VMOVDQU8Z128mr */ + }, + { /* 7786 */ + 673, + /* VMOVDQU8Z128mrk */ + }, + { /* 7787 */ + 409, + /* VMOVDQU8Z128rm */ + }, + { /* 7788 */ + 410, + /* VMOVDQU8Z128rmk */ + }, + { /* 7789 */ + 411, + /* VMOVDQU8Z128rmkz */ + }, + { /* 7790 */ + 330, + /* VMOVDQU8Z128rr */ + }, + { /* 7791 */ + 381, + /* VMOVDQU8Z128rr_REV */ + }, + { /* 7792 */ + 331, + /* VMOVDQU8Z128rrk */ + }, + { /* 7793 */ + 383, + /* VMOVDQU8Z128rrk_REV */ + }, + { /* 7794 */ + 332, + /* VMOVDQU8Z128rrkz */ + }, + { /* 7795 */ + 383, + /* VMOVDQU8Z128rrkz_REV */ + }, + { /* 7796 */ + 674, + /* VMOVDQU8Z256mr */ + }, + { /* 7797 */ + 675, + /* VMOVDQU8Z256mrk */ + }, + { /* 7798 */ + 412, + /* VMOVDQU8Z256rm */ + }, + { /* 7799 */ + 413, + /* VMOVDQU8Z256rmk */ + }, + { /* 7800 */ + 414, + /* VMOVDQU8Z256rmkz */ + }, + { /* 7801 */ + 415, + /* VMOVDQU8Z256rr */ + }, + { /* 7802 */ + 386, + /* VMOVDQU8Z256rr_REV */ + }, + { /* 7803 */ + 416, + /* VMOVDQU8Z256rrk */ + }, + { /* 7804 */ + 388, + /* VMOVDQU8Z256rrk_REV */ + }, + { /* 7805 */ + 417, + /* VMOVDQU8Z256rrkz */ + }, + { /* 7806 */ + 388, + /* VMOVDQU8Z256rrkz_REV */ + }, + { /* 7807 */ + 676, + /* VMOVDQU8Zmr */ + }, + { /* 7808 */ + 677, + /* VMOVDQU8Zmrk */ + }, + { /* 7809 */ + 418, + /* VMOVDQU8Zrm */ + }, + { /* 7810 */ + 419, + /* VMOVDQU8Zrmk */ + }, + { /* 7811 */ + 420, + /* VMOVDQU8Zrmkz */ + }, + { /* 7812 */ + 421, + /* VMOVDQU8Zrr */ + }, + { /* 7813 */ + 391, + /* VMOVDQU8Zrr_REV */ + }, + { /* 7814 */ + 425, + /* VMOVDQU8Zrrk */ + }, + { /* 7815 */ + 393, + /* VMOVDQU8Zrrk_REV */ + }, + { /* 7816 */ + 426, + /* VMOVDQU8Zrrkz */ + }, + { /* 7817 */ + 393, + /* VMOVDQU8Zrrkz_REV */ + }, + { /* 7818 */ + 670, + /* VMOVDQUYmr */ + }, + { /* 7819 */ + 305, + /* VMOVDQUYrm */ + }, + { /* 7820 */ + 408, + /* VMOVDQUYrr */ + }, + { /* 7821 */ + 671, + /* VMOVDQUYrr_REV */ + }, + { /* 7822 */ + 169, + /* VMOVDQUmr */ + }, + { /* 7823 */ + 30, + /* VMOVDQUrm */ + }, + { /* 7824 */ + 31, + /* VMOVDQUrr */ + }, + { /* 7825 */ + 170, + /* VMOVDQUrr_REV */ + }, + { /* 7826 */ + 211, + /* VMOVHLPSZrr */ + }, + { /* 7827 */ + 236, + /* VMOVHLPSrr */ + }, + { /* 7828 */ + 379, + /* VMOVHPDZ128mr */ + }, + { /* 7829 */ + 207, + /* VMOVHPDZ128rm */ + }, + { /* 7830 */ + 169, + /* VMOVHPDmr */ + }, + { /* 7831 */ + 235, + /* VMOVHPDrm */ + }, + { /* 7832 */ + 379, + /* VMOVHPSZ128mr */ + }, + { /* 7833 */ + 207, + /* VMOVHPSZ128rm */ + }, + { /* 7834 */ + 169, + /* VMOVHPSmr */ + }, + { /* 7835 */ + 235, + /* VMOVHPSrm */ + }, + { /* 7836 */ + 211, + /* VMOVLHPSZrr */ + }, + { /* 7837 */ + 236, + /* VMOVLHPSrr */ + }, + { /* 7838 */ + 379, + /* VMOVLPDZ128mr */ + }, + { /* 7839 */ + 207, + /* VMOVLPDZ128rm */ + }, + { /* 7840 */ + 169, + /* VMOVLPDmr */ + }, + { /* 7841 */ + 235, + /* VMOVLPDrm */ + }, + { /* 7842 */ + 379, + /* VMOVLPSZ128mr */ + }, + { /* 7843 */ + 207, + /* VMOVLPSZ128rm */ + }, + { /* 7844 */ + 169, + /* VMOVLPSmr */ + }, + { /* 7845 */ + 235, + /* VMOVLPSrm */ + }, + { /* 7846 */ + 679, + /* VMOVMSKPDYrr */ + }, + { /* 7847 */ + 88, + /* VMOVMSKPDrr */ + }, + { /* 7848 */ + 679, + /* VMOVMSKPSYrr */ + }, + { /* 7849 */ + 88, + /* VMOVMSKPSrr */ + }, + { /* 7850 */ + 305, + /* VMOVNTDQAYrm */ + }, + { /* 7851 */ + 409, + /* VMOVNTDQAZ128rm */ + }, + { /* 7852 */ + 412, + /* VMOVNTDQAZ256rm */ + }, + { /* 7853 */ + 418, + /* VMOVNTDQAZrm */ + }, + { /* 7854 */ + 30, + /* VMOVNTDQArm */ + }, + { /* 7855 */ + 670, + /* VMOVNTDQYmr */ + }, + { /* 7856 */ + 672, + /* VMOVNTDQZ128mr */ + }, + { /* 7857 */ + 674, + /* VMOVNTDQZ256mr */ + }, + { /* 7858 */ + 676, + /* VMOVNTDQZmr */ + }, + { /* 7859 */ + 169, + /* VMOVNTDQmr */ + }, + { /* 7860 */ + 670, + /* VMOVNTPDYmr */ + }, + { /* 7861 */ + 672, + /* VMOVNTPDZ128mr */ + }, + { /* 7862 */ + 674, + /* VMOVNTPDZ256mr */ + }, + { /* 7863 */ + 676, + /* VMOVNTPDZmr */ + }, + { /* 7864 */ + 169, + /* VMOVNTPDmr */ + }, + { /* 7865 */ + 670, + /* VMOVNTPSYmr */ + }, + { /* 7866 */ + 672, + /* VMOVNTPSZ128mr */ + }, + { /* 7867 */ + 674, + /* VMOVNTPSZ256mr */ + }, + { /* 7868 */ + 676, + /* VMOVNTPSZmr */ + }, + { /* 7869 */ + 169, + /* VMOVNTPSmr */ + }, + { /* 7870 */ + 394, + /* VMOVPDI2DIZmr */ + }, + { /* 7871 */ + 680, + /* VMOVPDI2DIZrr */ + }, + { /* 7872 */ + 169, + /* VMOVPDI2DImr */ + }, + { /* 7873 */ + 173, + /* VMOVPDI2DIrr */ + }, + { /* 7874 */ + 379, + /* VMOVPQI2QIZmr */ + }, + { /* 7875 */ + 381, + /* VMOVPQI2QIZrr */ + }, + { /* 7876 */ + 169, + /* VMOVPQI2QImr */ + }, + { /* 7877 */ + 170, + /* VMOVPQI2QIrr */ + }, + { /* 7878 */ + 672, + /* VMOVPQIto64Zmr */ + }, + { /* 7879 */ + 681, + /* VMOVPQIto64Zrr */ + }, + { /* 7880 */ + 169, + /* VMOVPQIto64mr */ + }, + { /* 7881 */ + 174, + /* VMOVPQIto64rr */ + }, + { /* 7882 */ + 327, + /* VMOVQI2PQIZrm */ + }, + { /* 7883 */ + 30, + /* VMOVQI2PQIrm */ + }, + { /* 7884 */ + 379, + /* VMOVSDZmr */ + }, + { /* 7885 */ + 380, + /* VMOVSDZmrk */ + }, + { /* 7886 */ + 327, + /* VMOVSDZrm */ + }, + { /* 7887 */ + 328, + /* VMOVSDZrmk */ + }, + { /* 7888 */ + 329, + /* VMOVSDZrmkz */ + }, + { /* 7889 */ + 249, + /* VMOVSDZrr */ + }, + { /* 7890 */ + 682, + /* VMOVSDZrr_REV */ + }, + { /* 7891 */ + 250, + /* VMOVSDZrrk */ + }, + { /* 7892 */ + 683, + /* VMOVSDZrrk_REV */ + }, + { /* 7893 */ + 251, + /* VMOVSDZrrkz */ + }, + { /* 7894 */ + 684, + /* VMOVSDZrrkz_REV */ + }, + { /* 7895 */ + 169, + /* VMOVSDmr */ + }, + { /* 7896 */ + 30, + /* VMOVSDrm */ + }, + { /* 7897 */ + 236, + /* VMOVSDrr */ + }, + { /* 7898 */ + 685, + /* VMOVSDrr_REV */ + }, + { /* 7899 */ + 0, + /* */ + }, + { /* 7900 */ + 0, + /* */ + }, + { /* 7901 */ + 0, + /* */ + }, + { /* 7902 */ + 0, + /* */ + }, + { /* 7903 */ + 305, + /* VMOVSHDUPYrm */ + }, + { /* 7904 */ + 408, + /* VMOVSHDUPYrr */ + }, + { /* 7905 */ + 409, + /* VMOVSHDUPZ128rm */ + }, + { /* 7906 */ + 410, + /* VMOVSHDUPZ128rmk */ + }, + { /* 7907 */ + 411, + /* VMOVSHDUPZ128rmkz */ + }, + { /* 7908 */ + 330, + /* VMOVSHDUPZ128rr */ + }, + { /* 7909 */ + 331, + /* VMOVSHDUPZ128rrk */ + }, + { /* 7910 */ + 332, + /* VMOVSHDUPZ128rrkz */ + }, + { /* 7911 */ + 412, + /* VMOVSHDUPZ256rm */ + }, + { /* 7912 */ + 413, + /* VMOVSHDUPZ256rmk */ + }, + { /* 7913 */ + 414, + /* VMOVSHDUPZ256rmkz */ + }, + { /* 7914 */ + 415, + /* VMOVSHDUPZ256rr */ + }, + { /* 7915 */ + 416, + /* VMOVSHDUPZ256rrk */ + }, + { /* 7916 */ + 417, + /* VMOVSHDUPZ256rrkz */ + }, + { /* 7917 */ + 418, + /* VMOVSHDUPZrm */ + }, + { /* 7918 */ + 419, + /* VMOVSHDUPZrmk */ + }, + { /* 7919 */ + 420, + /* VMOVSHDUPZrmkz */ + }, + { /* 7920 */ + 421, + /* VMOVSHDUPZrr */ + }, + { /* 7921 */ + 425, + /* VMOVSHDUPZrrk */ + }, + { /* 7922 */ + 426, + /* VMOVSHDUPZrrkz */ + }, + { /* 7923 */ + 30, + /* VMOVSHDUPrm */ + }, + { /* 7924 */ + 31, + /* VMOVSHDUPrr */ + }, + { /* 7925 */ + 305, + /* VMOVSLDUPYrm */ + }, + { /* 7926 */ + 408, + /* VMOVSLDUPYrr */ + }, + { /* 7927 */ + 409, + /* VMOVSLDUPZ128rm */ + }, + { /* 7928 */ + 410, + /* VMOVSLDUPZ128rmk */ + }, + { /* 7929 */ + 411, + /* VMOVSLDUPZ128rmkz */ + }, + { /* 7930 */ + 330, + /* VMOVSLDUPZ128rr */ + }, + { /* 7931 */ + 331, + /* VMOVSLDUPZ128rrk */ + }, + { /* 7932 */ + 332, + /* VMOVSLDUPZ128rrkz */ + }, + { /* 7933 */ + 412, + /* VMOVSLDUPZ256rm */ + }, + { /* 7934 */ + 413, + /* VMOVSLDUPZ256rmk */ + }, + { /* 7935 */ + 414, + /* VMOVSLDUPZ256rmkz */ + }, + { /* 7936 */ + 415, + /* VMOVSLDUPZ256rr */ + }, + { /* 7937 */ + 416, + /* VMOVSLDUPZ256rrk */ + }, + { /* 7938 */ + 417, + /* VMOVSLDUPZ256rrkz */ + }, + { /* 7939 */ + 418, + /* VMOVSLDUPZrm */ + }, + { /* 7940 */ + 419, + /* VMOVSLDUPZrmk */ + }, + { /* 7941 */ + 420, + /* VMOVSLDUPZrmkz */ + }, + { /* 7942 */ + 421, + /* VMOVSLDUPZrr */ + }, + { /* 7943 */ + 425, + /* VMOVSLDUPZrrk */ + }, + { /* 7944 */ + 426, + /* VMOVSLDUPZrrkz */ + }, + { /* 7945 */ + 30, + /* VMOVSLDUPrm */ + }, + { /* 7946 */ + 31, + /* VMOVSLDUPrr */ + }, + { /* 7947 */ + 0, + /* */ + }, + { /* 7948 */ + 0, + /* */ + }, + { /* 7949 */ + 0, + /* */ + }, + { /* 7950 */ + 0, + /* */ + }, + { /* 7951 */ + 394, + /* VMOVSSZmr */ + }, + { /* 7952 */ + 395, + /* VMOVSSZmrk */ + }, + { /* 7953 */ + 334, + /* VMOVSSZrm */ + }, + { /* 7954 */ + 335, + /* VMOVSSZrmk */ + }, + { /* 7955 */ + 336, + /* VMOVSSZrmkz */ + }, + { /* 7956 */ + 255, + /* VMOVSSZrr */ + }, + { /* 7957 */ + 682, + /* VMOVSSZrr_REV */ + }, + { /* 7958 */ + 256, + /* VMOVSSZrrk */ + }, + { /* 7959 */ + 683, + /* VMOVSSZrrk_REV */ + }, + { /* 7960 */ + 257, + /* VMOVSSZrrkz */ + }, + { /* 7961 */ + 684, + /* VMOVSSZrrkz_REV */ + }, + { /* 7962 */ + 169, + /* VMOVSSmr */ + }, + { /* 7963 */ + 30, + /* VMOVSSrm */ + }, + { /* 7964 */ + 236, + /* VMOVSSrr */ + }, + { /* 7965 */ + 685, + /* VMOVSSrr_REV */ + }, + { /* 7966 */ + 670, + /* VMOVUPDYmr */ + }, + { /* 7967 */ + 305, + /* VMOVUPDYrm */ + }, + { /* 7968 */ + 408, + /* VMOVUPDYrr */ + }, + { /* 7969 */ + 671, + /* VMOVUPDYrr_REV */ + }, + { /* 7970 */ + 672, + /* VMOVUPDZ128mr */ + }, + { /* 7971 */ + 673, + /* VMOVUPDZ128mrk */ + }, + { /* 7972 */ + 409, + /* VMOVUPDZ128rm */ + }, + { /* 7973 */ + 410, + /* VMOVUPDZ128rmk */ + }, + { /* 7974 */ + 411, + /* VMOVUPDZ128rmkz */ + }, + { /* 7975 */ + 330, + /* VMOVUPDZ128rr */ + }, + { /* 7976 */ + 381, + /* VMOVUPDZ128rr_REV */ + }, + { /* 7977 */ + 331, + /* VMOVUPDZ128rrk */ + }, + { /* 7978 */ + 383, + /* VMOVUPDZ128rrk_REV */ + }, + { /* 7979 */ + 332, + /* VMOVUPDZ128rrkz */ + }, + { /* 7980 */ + 383, + /* VMOVUPDZ128rrkz_REV */ + }, + { /* 7981 */ + 674, + /* VMOVUPDZ256mr */ + }, + { /* 7982 */ + 675, + /* VMOVUPDZ256mrk */ + }, + { /* 7983 */ + 412, + /* VMOVUPDZ256rm */ + }, + { /* 7984 */ + 413, + /* VMOVUPDZ256rmk */ + }, + { /* 7985 */ + 414, + /* VMOVUPDZ256rmkz */ + }, + { /* 7986 */ + 415, + /* VMOVUPDZ256rr */ + }, + { /* 7987 */ + 386, + /* VMOVUPDZ256rr_REV */ + }, + { /* 7988 */ + 416, + /* VMOVUPDZ256rrk */ + }, + { /* 7989 */ + 388, + /* VMOVUPDZ256rrk_REV */ + }, + { /* 7990 */ + 417, + /* VMOVUPDZ256rrkz */ + }, + { /* 7991 */ + 388, + /* VMOVUPDZ256rrkz_REV */ + }, + { /* 7992 */ + 676, + /* VMOVUPDZmr */ + }, + { /* 7993 */ + 677, + /* VMOVUPDZmrk */ + }, + { /* 7994 */ + 418, + /* VMOVUPDZrm */ + }, + { /* 7995 */ + 419, + /* VMOVUPDZrmk */ + }, + { /* 7996 */ + 420, + /* VMOVUPDZrmkz */ + }, + { /* 7997 */ + 421, + /* VMOVUPDZrr */ + }, + { /* 7998 */ + 391, + /* VMOVUPDZrr_REV */ + }, + { /* 7999 */ + 425, + /* VMOVUPDZrrk */ + }, + { /* 8000 */ + 393, + /* VMOVUPDZrrk_REV */ + }, + { /* 8001 */ + 426, + /* VMOVUPDZrrkz */ + }, + { /* 8002 */ + 393, + /* VMOVUPDZrrkz_REV */ + }, + { /* 8003 */ + 169, + /* VMOVUPDmr */ + }, + { /* 8004 */ + 30, + /* VMOVUPDrm */ + }, + { /* 8005 */ + 31, + /* VMOVUPDrr */ + }, + { /* 8006 */ + 170, + /* VMOVUPDrr_REV */ + }, + { /* 8007 */ + 670, + /* VMOVUPSYmr */ + }, + { /* 8008 */ + 305, + /* VMOVUPSYrm */ + }, + { /* 8009 */ + 408, + /* VMOVUPSYrr */ + }, + { /* 8010 */ + 671, + /* VMOVUPSYrr_REV */ + }, + { /* 8011 */ + 672, + /* VMOVUPSZ128mr */ + }, + { /* 8012 */ + 673, + /* VMOVUPSZ128mrk */ + }, + { /* 8013 */ + 409, + /* VMOVUPSZ128rm */ + }, + { /* 8014 */ + 410, + /* VMOVUPSZ128rmk */ + }, + { /* 8015 */ + 411, + /* VMOVUPSZ128rmkz */ + }, + { /* 8016 */ + 330, + /* VMOVUPSZ128rr */ + }, + { /* 8017 */ + 381, + /* VMOVUPSZ128rr_REV */ + }, + { /* 8018 */ + 331, + /* VMOVUPSZ128rrk */ + }, + { /* 8019 */ + 383, + /* VMOVUPSZ128rrk_REV */ + }, + { /* 8020 */ + 332, + /* VMOVUPSZ128rrkz */ + }, + { /* 8021 */ + 383, + /* VMOVUPSZ128rrkz_REV */ + }, + { /* 8022 */ + 674, + /* VMOVUPSZ256mr */ + }, + { /* 8023 */ + 675, + /* VMOVUPSZ256mrk */ + }, + { /* 8024 */ + 412, + /* VMOVUPSZ256rm */ + }, + { /* 8025 */ + 413, + /* VMOVUPSZ256rmk */ + }, + { /* 8026 */ + 414, + /* VMOVUPSZ256rmkz */ + }, + { /* 8027 */ + 415, + /* VMOVUPSZ256rr */ + }, + { /* 8028 */ + 386, + /* VMOVUPSZ256rr_REV */ + }, + { /* 8029 */ + 416, + /* VMOVUPSZ256rrk */ + }, + { /* 8030 */ + 388, + /* VMOVUPSZ256rrk_REV */ + }, + { /* 8031 */ + 417, + /* VMOVUPSZ256rrkz */ + }, + { /* 8032 */ + 388, + /* VMOVUPSZ256rrkz_REV */ + }, + { /* 8033 */ + 676, + /* VMOVUPSZmr */ + }, + { /* 8034 */ + 677, + /* VMOVUPSZmrk */ + }, + { /* 8035 */ + 418, + /* VMOVUPSZrm */ + }, + { /* 8036 */ + 419, + /* VMOVUPSZrmk */ + }, + { /* 8037 */ + 420, + /* VMOVUPSZrmkz */ + }, + { /* 8038 */ + 421, + /* VMOVUPSZrr */ + }, + { /* 8039 */ + 391, + /* VMOVUPSZrr_REV */ + }, + { /* 8040 */ + 425, + /* VMOVUPSZrrk */ + }, + { /* 8041 */ + 393, + /* VMOVUPSZrrk_REV */ + }, + { /* 8042 */ + 426, + /* VMOVUPSZrrkz */ + }, + { /* 8043 */ + 393, + /* VMOVUPSZrrkz_REV */ + }, + { /* 8044 */ + 169, + /* VMOVUPSmr */ + }, + { /* 8045 */ + 30, + /* VMOVUPSrm */ + }, + { /* 8046 */ + 31, + /* VMOVUPSrr */ + }, + { /* 8047 */ + 170, + /* VMOVUPSrr_REV */ + }, + { /* 8048 */ + 330, + /* VMOVZPQILo2PQIZrr */ + }, + { /* 8049 */ + 31, + /* VMOVZPQILo2PQIrr */ + }, + { /* 8050 */ + 297, + /* VMPSADBWYrmi */ + }, + { /* 8051 */ + 298, + /* VMPSADBWYrri */ + }, + { /* 8052 */ + 299, + /* VMPSADBWrmi */ + }, + { /* 8053 */ + 300, + /* VMPSADBWrri */ + }, + { /* 8054 */ + 28, + /* VMPTRLDm */ + }, + { /* 8055 */ + 28, + /* VMPTRSTm */ + }, + { /* 8056 */ + 172, + /* VMREAD32mr */ + }, + { /* 8057 */ + 686, + /* VMREAD32rr */ + }, + { /* 8058 */ + 13, + /* VMREAD64mr */ + }, + { /* 8059 */ + 69, + /* VMREAD64rr */ + }, + { /* 8060 */ + 0, + /* VMRESUME */ + }, + { /* 8061 */ + 0, + /* VMRUN32 */ + }, + { /* 8062 */ + 0, + /* VMRUN64 */ + }, + { /* 8063 */ + 0, + /* VMSAVE32 */ + }, + { /* 8064 */ + 0, + /* VMSAVE64 */ + }, + { /* 8065 */ + 204, + /* VMULPDYrm */ + }, + { /* 8066 */ + 205, + /* VMULPDYrr */ + }, + { /* 8067 */ + 206, + /* VMULPDZ128rm */ + }, + { /* 8068 */ + 207, + /* VMULPDZ128rmb */ + }, + { /* 8069 */ + 208, + /* VMULPDZ128rmbk */ + }, + { /* 8070 */ + 209, + /* VMULPDZ128rmbkz */ + }, + { /* 8071 */ + 203, + /* VMULPDZ128rmk */ + }, + { /* 8072 */ + 210, + /* VMULPDZ128rmkz */ + }, + { /* 8073 */ + 211, + /* VMULPDZ128rr */ + }, + { /* 8074 */ + 212, + /* VMULPDZ128rrk */ + }, + { /* 8075 */ + 213, + /* VMULPDZ128rrkz */ + }, + { /* 8076 */ + 214, + /* VMULPDZ256rm */ + }, + { /* 8077 */ + 215, + /* VMULPDZ256rmb */ + }, + { /* 8078 */ + 216, + /* VMULPDZ256rmbk */ + }, + { /* 8079 */ + 217, + /* VMULPDZ256rmbkz */ + }, + { /* 8080 */ + 218, + /* VMULPDZ256rmk */ + }, + { /* 8081 */ + 219, + /* VMULPDZ256rmkz */ + }, + { /* 8082 */ + 220, + /* VMULPDZ256rr */ + }, + { /* 8083 */ + 221, + /* VMULPDZ256rrk */ + }, + { /* 8084 */ + 222, + /* VMULPDZ256rrkz */ + }, + { /* 8085 */ + 223, + /* VMULPDZrm */ + }, + { /* 8086 */ + 224, + /* VMULPDZrmb */ + }, + { /* 8087 */ + 225, + /* VMULPDZrmbk */ + }, + { /* 8088 */ + 226, + /* VMULPDZrmbkz */ + }, + { /* 8089 */ + 227, + /* VMULPDZrmk */ + }, + { /* 8090 */ + 228, + /* VMULPDZrmkz */ + }, + { /* 8091 */ + 229, + /* VMULPDZrr */ + }, + { /* 8092 */ + 230, + /* VMULPDZrrb */ + }, + { /* 8093 */ + 231, + /* VMULPDZrrbk */ + }, + { /* 8094 */ + 232, + /* VMULPDZrrbkz */ + }, + { /* 8095 */ + 233, + /* VMULPDZrrk */ + }, + { /* 8096 */ + 234, + /* VMULPDZrrkz */ + }, + { /* 8097 */ + 235, + /* VMULPDrm */ + }, + { /* 8098 */ + 236, + /* VMULPDrr */ + }, + { /* 8099 */ + 204, + /* VMULPSYrm */ + }, + { /* 8100 */ + 205, + /* VMULPSYrr */ + }, + { /* 8101 */ + 206, + /* VMULPSZ128rm */ + }, + { /* 8102 */ + 237, + /* VMULPSZ128rmb */ + }, + { /* 8103 */ + 238, + /* VMULPSZ128rmbk */ + }, + { /* 8104 */ + 239, + /* VMULPSZ128rmbkz */ + }, + { /* 8105 */ + 203, + /* VMULPSZ128rmk */ + }, + { /* 8106 */ + 210, + /* VMULPSZ128rmkz */ + }, + { /* 8107 */ + 211, + /* VMULPSZ128rr */ + }, + { /* 8108 */ + 212, + /* VMULPSZ128rrk */ + }, + { /* 8109 */ + 213, + /* VMULPSZ128rrkz */ + }, + { /* 8110 */ + 214, + /* VMULPSZ256rm */ + }, + { /* 8111 */ + 240, + /* VMULPSZ256rmb */ + }, + { /* 8112 */ + 241, + /* VMULPSZ256rmbk */ + }, + { /* 8113 */ + 242, + /* VMULPSZ256rmbkz */ + }, + { /* 8114 */ + 218, + /* VMULPSZ256rmk */ + }, + { /* 8115 */ + 219, + /* VMULPSZ256rmkz */ + }, + { /* 8116 */ + 220, + /* VMULPSZ256rr */ + }, + { /* 8117 */ + 221, + /* VMULPSZ256rrk */ + }, + { /* 8118 */ + 222, + /* VMULPSZ256rrkz */ + }, + { /* 8119 */ + 223, + /* VMULPSZrm */ + }, + { /* 8120 */ + 243, + /* VMULPSZrmb */ + }, + { /* 8121 */ + 244, + /* VMULPSZrmbk */ + }, + { /* 8122 */ + 245, + /* VMULPSZrmbkz */ + }, + { /* 8123 */ + 227, + /* VMULPSZrmk */ + }, + { /* 8124 */ + 228, + /* VMULPSZrmkz */ + }, + { /* 8125 */ + 229, + /* VMULPSZrr */ + }, + { /* 8126 */ + 246, + /* VMULPSZrrb */ + }, + { /* 8127 */ + 247, + /* VMULPSZrrbk */ + }, + { /* 8128 */ + 248, + /* VMULPSZrrbkz */ + }, + { /* 8129 */ + 233, + /* VMULPSZrrk */ + }, + { /* 8130 */ + 234, + /* VMULPSZrrkz */ + }, + { /* 8131 */ + 235, + /* VMULPSrm */ + }, + { /* 8132 */ + 236, + /* VMULPSrr */ + }, + { /* 8133 */ + 0, + /* */ + }, + { /* 8134 */ + 207, + /* VMULSDZrm_Int */ + }, + { /* 8135 */ + 208, + /* VMULSDZrm_Intk */ + }, + { /* 8136 */ + 209, + /* VMULSDZrm_Intkz */ + }, + { /* 8137 */ + 0, + /* */ + }, + { /* 8138 */ + 249, + /* VMULSDZrr_Int */ + }, + { /* 8139 */ + 250, + /* VMULSDZrr_Intk */ + }, + { /* 8140 */ + 251, + /* VMULSDZrr_Intkz */ + }, + { /* 8141 */ + 252, + /* VMULSDZrrb_Int */ + }, + { /* 8142 */ + 253, + /* VMULSDZrrb_Intk */ + }, + { /* 8143 */ + 254, + /* VMULSDZrrb_Intkz */ + }, + { /* 8144 */ + 235, + /* VMULSDrm */ + }, + { /* 8145 */ + 0, + /* */ + }, + { /* 8146 */ + 236, + /* VMULSDrr */ + }, + { /* 8147 */ + 0, + /* */ + }, + { /* 8148 */ + 0, + /* */ + }, + { /* 8149 */ + 237, + /* VMULSSZrm_Int */ + }, + { /* 8150 */ + 238, + /* VMULSSZrm_Intk */ + }, + { /* 8151 */ + 239, + /* VMULSSZrm_Intkz */ + }, + { /* 8152 */ + 0, + /* */ + }, + { /* 8153 */ + 255, + /* VMULSSZrr_Int */ + }, + { /* 8154 */ + 256, + /* VMULSSZrr_Intk */ + }, + { /* 8155 */ + 257, + /* VMULSSZrr_Intkz */ + }, + { /* 8156 */ + 258, + /* VMULSSZrrb_Int */ + }, + { /* 8157 */ + 259, + /* VMULSSZrrb_Intk */ + }, + { /* 8158 */ + 260, + /* VMULSSZrrb_Intkz */ + }, + { /* 8159 */ + 235, + /* VMULSSrm */ + }, + { /* 8160 */ + 0, + /* */ + }, + { /* 8161 */ + 236, + /* VMULSSrr */ + }, + { /* 8162 */ + 0, + /* */ + }, + { /* 8163 */ + 87, + /* VMWRITE32rm */ + }, + { /* 8164 */ + 687, + /* VMWRITE32rr */ + }, + { /* 8165 */ + 62, + /* VMWRITE64rm */ + }, + { /* 8166 */ + 63, + /* VMWRITE64rr */ + }, + { /* 8167 */ + 0, + /* VMXOFF */ + }, + { /* 8168 */ + 28, + /* VMXON */ + }, + { /* 8169 */ + 204, + /* VORPDYrm */ + }, + { /* 8170 */ + 205, + /* VORPDYrr */ + }, + { /* 8171 */ + 206, + /* VORPDZ128rm */ + }, + { /* 8172 */ + 207, + /* VORPDZ128rmb */ + }, + { /* 8173 */ + 208, + /* VORPDZ128rmbk */ + }, + { /* 8174 */ + 209, + /* VORPDZ128rmbkz */ + }, + { /* 8175 */ + 203, + /* VORPDZ128rmk */ + }, + { /* 8176 */ + 210, + /* VORPDZ128rmkz */ + }, + { /* 8177 */ + 211, + /* VORPDZ128rr */ + }, + { /* 8178 */ + 212, + /* VORPDZ128rrk */ + }, + { /* 8179 */ + 213, + /* VORPDZ128rrkz */ + }, + { /* 8180 */ + 214, + /* VORPDZ256rm */ + }, + { /* 8181 */ + 215, + /* VORPDZ256rmb */ + }, + { /* 8182 */ + 216, + /* VORPDZ256rmbk */ + }, + { /* 8183 */ + 217, + /* VORPDZ256rmbkz */ + }, + { /* 8184 */ + 218, + /* VORPDZ256rmk */ + }, + { /* 8185 */ + 219, + /* VORPDZ256rmkz */ + }, + { /* 8186 */ + 220, + /* VORPDZ256rr */ + }, + { /* 8187 */ + 221, + /* VORPDZ256rrk */ + }, + { /* 8188 */ + 222, + /* VORPDZ256rrkz */ + }, + { /* 8189 */ + 223, + /* VORPDZrm */ + }, + { /* 8190 */ + 224, + /* VORPDZrmb */ + }, + { /* 8191 */ + 225, + /* VORPDZrmbk */ + }, + { /* 8192 */ + 226, + /* VORPDZrmbkz */ + }, + { /* 8193 */ + 227, + /* VORPDZrmk */ + }, + { /* 8194 */ + 228, + /* VORPDZrmkz */ + }, + { /* 8195 */ + 229, + /* VORPDZrr */ + }, + { /* 8196 */ + 233, + /* VORPDZrrk */ + }, + { /* 8197 */ + 234, + /* VORPDZrrkz */ + }, + { /* 8198 */ + 235, + /* VORPDrm */ + }, + { /* 8199 */ + 236, + /* VORPDrr */ + }, + { /* 8200 */ + 204, + /* VORPSYrm */ + }, + { /* 8201 */ + 205, + /* VORPSYrr */ + }, + { /* 8202 */ + 206, + /* VORPSZ128rm */ + }, + { /* 8203 */ + 237, + /* VORPSZ128rmb */ + }, + { /* 8204 */ + 238, + /* VORPSZ128rmbk */ + }, + { /* 8205 */ + 239, + /* VORPSZ128rmbkz */ + }, + { /* 8206 */ + 203, + /* VORPSZ128rmk */ + }, + { /* 8207 */ + 210, + /* VORPSZ128rmkz */ + }, + { /* 8208 */ + 211, + /* VORPSZ128rr */ + }, + { /* 8209 */ + 212, + /* VORPSZ128rrk */ + }, + { /* 8210 */ + 213, + /* VORPSZ128rrkz */ + }, + { /* 8211 */ + 214, + /* VORPSZ256rm */ + }, + { /* 8212 */ + 240, + /* VORPSZ256rmb */ + }, + { /* 8213 */ + 241, + /* VORPSZ256rmbk */ + }, + { /* 8214 */ + 242, + /* VORPSZ256rmbkz */ + }, + { /* 8215 */ + 218, + /* VORPSZ256rmk */ + }, + { /* 8216 */ + 219, + /* VORPSZ256rmkz */ + }, + { /* 8217 */ + 220, + /* VORPSZ256rr */ + }, + { /* 8218 */ + 221, + /* VORPSZ256rrk */ + }, + { /* 8219 */ + 222, + /* VORPSZ256rrkz */ + }, + { /* 8220 */ + 223, + /* VORPSZrm */ + }, + { /* 8221 */ + 243, + /* VORPSZrmb */ + }, + { /* 8222 */ + 244, + /* VORPSZrmbk */ + }, + { /* 8223 */ + 245, + /* VORPSZrmbkz */ + }, + { /* 8224 */ + 227, + /* VORPSZrmk */ + }, + { /* 8225 */ + 228, + /* VORPSZrmkz */ + }, + { /* 8226 */ + 229, + /* VORPSZrr */ + }, + { /* 8227 */ + 233, + /* VORPSZrrk */ + }, + { /* 8228 */ + 234, + /* VORPSZrrkz */ + }, + { /* 8229 */ + 235, + /* VORPSrm */ + }, + { /* 8230 */ + 236, + /* VORPSrr */ + }, + { /* 8231 */ + 200, + /* VP4DPWSSDSrm */ + }, + { /* 8232 */ + 201, + /* VP4DPWSSDSrmk */ + }, + { /* 8233 */ + 201, + /* VP4DPWSSDSrmkz */ + }, + { /* 8234 */ + 200, + /* VP4DPWSSDrm */ + }, + { /* 8235 */ + 201, + /* VP4DPWSSDrmk */ + }, + { /* 8236 */ + 201, + /* VP4DPWSSDrmkz */ + }, + { /* 8237 */ + 305, + /* VPABSBYrm */ + }, + { /* 8238 */ + 408, + /* VPABSBYrr */ + }, + { /* 8239 */ + 409, + /* VPABSBZ128rm */ + }, + { /* 8240 */ + 410, + /* VPABSBZ128rmk */ + }, + { /* 8241 */ + 411, + /* VPABSBZ128rmkz */ + }, + { /* 8242 */ + 330, + /* VPABSBZ128rr */ + }, + { /* 8243 */ + 331, + /* VPABSBZ128rrk */ + }, + { /* 8244 */ + 332, + /* VPABSBZ128rrkz */ + }, + { /* 8245 */ + 412, + /* VPABSBZ256rm */ + }, + { /* 8246 */ + 413, + /* VPABSBZ256rmk */ + }, + { /* 8247 */ + 414, + /* VPABSBZ256rmkz */ + }, + { /* 8248 */ + 415, + /* VPABSBZ256rr */ + }, + { /* 8249 */ + 416, + /* VPABSBZ256rrk */ + }, + { /* 8250 */ + 417, + /* VPABSBZ256rrkz */ + }, + { /* 8251 */ + 418, + /* VPABSBZrm */ + }, + { /* 8252 */ + 419, + /* VPABSBZrmk */ + }, + { /* 8253 */ + 420, + /* VPABSBZrmkz */ + }, + { /* 8254 */ + 421, + /* VPABSBZrr */ + }, + { /* 8255 */ + 425, + /* VPABSBZrrk */ + }, + { /* 8256 */ + 426, + /* VPABSBZrrkz */ + }, + { /* 8257 */ + 30, + /* VPABSBrm */ + }, + { /* 8258 */ + 31, + /* VPABSBrr */ + }, + { /* 8259 */ + 305, + /* VPABSDYrm */ + }, + { /* 8260 */ + 408, + /* VPABSDYrr */ + }, + { /* 8261 */ + 409, + /* VPABSDZ128rm */ + }, + { /* 8262 */ + 334, + /* VPABSDZ128rmb */ + }, + { /* 8263 */ + 335, + /* VPABSDZ128rmbk */ + }, + { /* 8264 */ + 336, + /* VPABSDZ128rmbkz */ + }, + { /* 8265 */ + 410, + /* VPABSDZ128rmk */ + }, + { /* 8266 */ + 411, + /* VPABSDZ128rmkz */ + }, + { /* 8267 */ + 330, + /* VPABSDZ128rr */ + }, + { /* 8268 */ + 331, + /* VPABSDZ128rrk */ + }, + { /* 8269 */ + 332, + /* VPABSDZ128rrkz */ + }, + { /* 8270 */ + 412, + /* VPABSDZ256rm */ + }, + { /* 8271 */ + 337, + /* VPABSDZ256rmb */ + }, + { /* 8272 */ + 338, + /* VPABSDZ256rmbk */ + }, + { /* 8273 */ + 339, + /* VPABSDZ256rmbkz */ + }, + { /* 8274 */ + 413, + /* VPABSDZ256rmk */ + }, + { /* 8275 */ + 414, + /* VPABSDZ256rmkz */ + }, + { /* 8276 */ + 415, + /* VPABSDZ256rr */ + }, + { /* 8277 */ + 416, + /* VPABSDZ256rrk */ + }, + { /* 8278 */ + 417, + /* VPABSDZ256rrkz */ + }, + { /* 8279 */ + 418, + /* VPABSDZrm */ + }, + { /* 8280 */ + 340, + /* VPABSDZrmb */ + }, + { /* 8281 */ + 341, + /* VPABSDZrmbk */ + }, + { /* 8282 */ + 342, + /* VPABSDZrmbkz */ + }, + { /* 8283 */ + 419, + /* VPABSDZrmk */ + }, + { /* 8284 */ + 420, + /* VPABSDZrmkz */ + }, + { /* 8285 */ + 421, + /* VPABSDZrr */ + }, + { /* 8286 */ + 425, + /* VPABSDZrrk */ + }, + { /* 8287 */ + 426, + /* VPABSDZrrkz */ + }, + { /* 8288 */ + 30, + /* VPABSDrm */ + }, + { /* 8289 */ + 31, + /* VPABSDrr */ + }, + { /* 8290 */ + 409, + /* VPABSQZ128rm */ + }, + { /* 8291 */ + 327, + /* VPABSQZ128rmb */ + }, + { /* 8292 */ + 328, + /* VPABSQZ128rmbk */ + }, + { /* 8293 */ + 329, + /* VPABSQZ128rmbkz */ + }, + { /* 8294 */ + 410, + /* VPABSQZ128rmk */ + }, + { /* 8295 */ + 411, + /* VPABSQZ128rmkz */ + }, + { /* 8296 */ + 330, + /* VPABSQZ128rr */ + }, + { /* 8297 */ + 331, + /* VPABSQZ128rrk */ + }, + { /* 8298 */ + 332, + /* VPABSQZ128rrkz */ + }, + { /* 8299 */ + 412, + /* VPABSQZ256rm */ + }, + { /* 8300 */ + 306, + /* VPABSQZ256rmb */ + }, + { /* 8301 */ + 307, + /* VPABSQZ256rmbk */ + }, + { /* 8302 */ + 308, + /* VPABSQZ256rmbkz */ + }, + { /* 8303 */ + 413, + /* VPABSQZ256rmk */ + }, + { /* 8304 */ + 414, + /* VPABSQZ256rmkz */ + }, + { /* 8305 */ + 415, + /* VPABSQZ256rr */ + }, + { /* 8306 */ + 416, + /* VPABSQZ256rrk */ + }, + { /* 8307 */ + 417, + /* VPABSQZ256rrkz */ + }, + { /* 8308 */ + 418, + /* VPABSQZrm */ + }, + { /* 8309 */ + 312, + /* VPABSQZrmb */ + }, + { /* 8310 */ + 313, + /* VPABSQZrmbk */ + }, + { /* 8311 */ + 314, + /* VPABSQZrmbkz */ + }, + { /* 8312 */ + 419, + /* VPABSQZrmk */ + }, + { /* 8313 */ + 420, + /* VPABSQZrmkz */ + }, + { /* 8314 */ + 421, + /* VPABSQZrr */ + }, + { /* 8315 */ + 425, + /* VPABSQZrrk */ + }, + { /* 8316 */ + 426, + /* VPABSQZrrkz */ + }, + { /* 8317 */ + 305, + /* VPABSWYrm */ + }, + { /* 8318 */ + 408, + /* VPABSWYrr */ + }, + { /* 8319 */ + 409, + /* VPABSWZ128rm */ + }, + { /* 8320 */ + 410, + /* VPABSWZ128rmk */ + }, + { /* 8321 */ + 411, + /* VPABSWZ128rmkz */ + }, + { /* 8322 */ + 330, + /* VPABSWZ128rr */ + }, + { /* 8323 */ + 331, + /* VPABSWZ128rrk */ + }, + { /* 8324 */ + 332, + /* VPABSWZ128rrkz */ + }, + { /* 8325 */ + 412, + /* VPABSWZ256rm */ + }, + { /* 8326 */ + 413, + /* VPABSWZ256rmk */ + }, + { /* 8327 */ + 414, + /* VPABSWZ256rmkz */ + }, + { /* 8328 */ + 415, + /* VPABSWZ256rr */ + }, + { /* 8329 */ + 416, + /* VPABSWZ256rrk */ + }, + { /* 8330 */ + 417, + /* VPABSWZ256rrkz */ + }, + { /* 8331 */ + 418, + /* VPABSWZrm */ + }, + { /* 8332 */ + 419, + /* VPABSWZrmk */ + }, + { /* 8333 */ + 420, + /* VPABSWZrmkz */ + }, + { /* 8334 */ + 421, + /* VPABSWZrr */ + }, + { /* 8335 */ + 425, + /* VPABSWZrrk */ + }, + { /* 8336 */ + 426, + /* VPABSWZrrkz */ + }, + { /* 8337 */ + 30, + /* VPABSWrm */ + }, + { /* 8338 */ + 31, + /* VPABSWrr */ + }, + { /* 8339 */ + 204, + /* VPACKSSDWYrm */ + }, + { /* 8340 */ + 205, + /* VPACKSSDWYrr */ + }, + { /* 8341 */ + 206, + /* VPACKSSDWZ128rm */ + }, + { /* 8342 */ + 237, + /* VPACKSSDWZ128rmb */ + }, + { /* 8343 */ + 238, + /* VPACKSSDWZ128rmbk */ + }, + { /* 8344 */ + 239, + /* VPACKSSDWZ128rmbkz */ + }, + { /* 8345 */ + 203, + /* VPACKSSDWZ128rmk */ + }, + { /* 8346 */ + 210, + /* VPACKSSDWZ128rmkz */ + }, + { /* 8347 */ + 211, + /* VPACKSSDWZ128rr */ + }, + { /* 8348 */ + 212, + /* VPACKSSDWZ128rrk */ + }, + { /* 8349 */ + 213, + /* VPACKSSDWZ128rrkz */ + }, + { /* 8350 */ + 214, + /* VPACKSSDWZ256rm */ + }, + { /* 8351 */ + 240, + /* VPACKSSDWZ256rmb */ + }, + { /* 8352 */ + 241, + /* VPACKSSDWZ256rmbk */ + }, + { /* 8353 */ + 242, + /* VPACKSSDWZ256rmbkz */ + }, + { /* 8354 */ + 218, + /* VPACKSSDWZ256rmk */ + }, + { /* 8355 */ + 219, + /* VPACKSSDWZ256rmkz */ + }, + { /* 8356 */ + 220, + /* VPACKSSDWZ256rr */ + }, + { /* 8357 */ + 221, + /* VPACKSSDWZ256rrk */ + }, + { /* 8358 */ + 222, + /* VPACKSSDWZ256rrkz */ + }, + { /* 8359 */ + 223, + /* VPACKSSDWZrm */ + }, + { /* 8360 */ + 243, + /* VPACKSSDWZrmb */ + }, + { /* 8361 */ + 244, + /* VPACKSSDWZrmbk */ + }, + { /* 8362 */ + 245, + /* VPACKSSDWZrmbkz */ + }, + { /* 8363 */ + 227, + /* VPACKSSDWZrmk */ + }, + { /* 8364 */ + 228, + /* VPACKSSDWZrmkz */ + }, + { /* 8365 */ + 229, + /* VPACKSSDWZrr */ + }, + { /* 8366 */ + 233, + /* VPACKSSDWZrrk */ + }, + { /* 8367 */ + 234, + /* VPACKSSDWZrrkz */ + }, + { /* 8368 */ + 235, + /* VPACKSSDWrm */ + }, + { /* 8369 */ + 236, + /* VPACKSSDWrr */ + }, + { /* 8370 */ + 204, + /* VPACKSSWBYrm */ + }, + { /* 8371 */ + 205, + /* VPACKSSWBYrr */ + }, + { /* 8372 */ + 206, + /* VPACKSSWBZ128rm */ + }, + { /* 8373 */ + 203, + /* VPACKSSWBZ128rmk */ + }, + { /* 8374 */ + 210, + /* VPACKSSWBZ128rmkz */ + }, + { /* 8375 */ + 211, + /* VPACKSSWBZ128rr */ + }, + { /* 8376 */ + 212, + /* VPACKSSWBZ128rrk */ + }, + { /* 8377 */ + 213, + /* VPACKSSWBZ128rrkz */ + }, + { /* 8378 */ + 214, + /* VPACKSSWBZ256rm */ + }, + { /* 8379 */ + 218, + /* VPACKSSWBZ256rmk */ + }, + { /* 8380 */ + 219, + /* VPACKSSWBZ256rmkz */ + }, + { /* 8381 */ + 220, + /* VPACKSSWBZ256rr */ + }, + { /* 8382 */ + 221, + /* VPACKSSWBZ256rrk */ + }, + { /* 8383 */ + 222, + /* VPACKSSWBZ256rrkz */ + }, + { /* 8384 */ + 223, + /* VPACKSSWBZrm */ + }, + { /* 8385 */ + 227, + /* VPACKSSWBZrmk */ + }, + { /* 8386 */ + 228, + /* VPACKSSWBZrmkz */ + }, + { /* 8387 */ + 229, + /* VPACKSSWBZrr */ + }, + { /* 8388 */ + 233, + /* VPACKSSWBZrrk */ + }, + { /* 8389 */ + 234, + /* VPACKSSWBZrrkz */ + }, + { /* 8390 */ + 235, + /* VPACKSSWBrm */ + }, + { /* 8391 */ + 236, + /* VPACKSSWBrr */ + }, + { /* 8392 */ + 204, + /* VPACKUSDWYrm */ + }, + { /* 8393 */ + 205, + /* VPACKUSDWYrr */ + }, + { /* 8394 */ + 206, + /* VPACKUSDWZ128rm */ + }, + { /* 8395 */ + 237, + /* VPACKUSDWZ128rmb */ + }, + { /* 8396 */ + 238, + /* VPACKUSDWZ128rmbk */ + }, + { /* 8397 */ + 239, + /* VPACKUSDWZ128rmbkz */ + }, + { /* 8398 */ + 203, + /* VPACKUSDWZ128rmk */ + }, + { /* 8399 */ + 210, + /* VPACKUSDWZ128rmkz */ + }, + { /* 8400 */ + 211, + /* VPACKUSDWZ128rr */ + }, + { /* 8401 */ + 212, + /* VPACKUSDWZ128rrk */ + }, + { /* 8402 */ + 213, + /* VPACKUSDWZ128rrkz */ + }, + { /* 8403 */ + 214, + /* VPACKUSDWZ256rm */ + }, + { /* 8404 */ + 240, + /* VPACKUSDWZ256rmb */ + }, + { /* 8405 */ + 241, + /* VPACKUSDWZ256rmbk */ + }, + { /* 8406 */ + 242, + /* VPACKUSDWZ256rmbkz */ + }, + { /* 8407 */ + 218, + /* VPACKUSDWZ256rmk */ + }, + { /* 8408 */ + 219, + /* VPACKUSDWZ256rmkz */ + }, + { /* 8409 */ + 220, + /* VPACKUSDWZ256rr */ + }, + { /* 8410 */ + 221, + /* VPACKUSDWZ256rrk */ + }, + { /* 8411 */ + 222, + /* VPACKUSDWZ256rrkz */ + }, + { /* 8412 */ + 223, + /* VPACKUSDWZrm */ + }, + { /* 8413 */ + 243, + /* VPACKUSDWZrmb */ + }, + { /* 8414 */ + 244, + /* VPACKUSDWZrmbk */ + }, + { /* 8415 */ + 245, + /* VPACKUSDWZrmbkz */ + }, + { /* 8416 */ + 227, + /* VPACKUSDWZrmk */ + }, + { /* 8417 */ + 228, + /* VPACKUSDWZrmkz */ + }, + { /* 8418 */ + 229, + /* VPACKUSDWZrr */ + }, + { /* 8419 */ + 233, + /* VPACKUSDWZrrk */ + }, + { /* 8420 */ + 234, + /* VPACKUSDWZrrkz */ + }, + { /* 8421 */ + 235, + /* VPACKUSDWrm */ + }, + { /* 8422 */ + 236, + /* VPACKUSDWrr */ + }, + { /* 8423 */ + 204, + /* VPACKUSWBYrm */ + }, + { /* 8424 */ + 205, + /* VPACKUSWBYrr */ + }, + { /* 8425 */ + 206, + /* VPACKUSWBZ128rm */ + }, + { /* 8426 */ + 203, + /* VPACKUSWBZ128rmk */ + }, + { /* 8427 */ + 210, + /* VPACKUSWBZ128rmkz */ + }, + { /* 8428 */ + 211, + /* VPACKUSWBZ128rr */ + }, + { /* 8429 */ + 212, + /* VPACKUSWBZ128rrk */ + }, + { /* 8430 */ + 213, + /* VPACKUSWBZ128rrkz */ + }, + { /* 8431 */ + 214, + /* VPACKUSWBZ256rm */ + }, + { /* 8432 */ + 218, + /* VPACKUSWBZ256rmk */ + }, + { /* 8433 */ + 219, + /* VPACKUSWBZ256rmkz */ + }, + { /* 8434 */ + 220, + /* VPACKUSWBZ256rr */ + }, + { /* 8435 */ + 221, + /* VPACKUSWBZ256rrk */ + }, + { /* 8436 */ + 222, + /* VPACKUSWBZ256rrkz */ + }, + { /* 8437 */ + 223, + /* VPACKUSWBZrm */ + }, + { /* 8438 */ + 227, + /* VPACKUSWBZrmk */ + }, + { /* 8439 */ + 228, + /* VPACKUSWBZrmkz */ + }, + { /* 8440 */ + 229, + /* VPACKUSWBZrr */ + }, + { /* 8441 */ + 233, + /* VPACKUSWBZrrk */ + }, + { /* 8442 */ + 234, + /* VPACKUSWBZrrkz */ + }, + { /* 8443 */ + 235, + /* VPACKUSWBrm */ + }, + { /* 8444 */ + 236, + /* VPACKUSWBrr */ + }, + { /* 8445 */ + 204, + /* VPADDBYrm */ + }, + { /* 8446 */ + 205, + /* VPADDBYrr */ + }, + { /* 8447 */ + 206, + /* VPADDBZ128rm */ + }, + { /* 8448 */ + 203, + /* VPADDBZ128rmk */ + }, + { /* 8449 */ + 210, + /* VPADDBZ128rmkz */ + }, + { /* 8450 */ + 211, + /* VPADDBZ128rr */ + }, + { /* 8451 */ + 212, + /* VPADDBZ128rrk */ + }, + { /* 8452 */ + 213, + /* VPADDBZ128rrkz */ + }, + { /* 8453 */ + 214, + /* VPADDBZ256rm */ + }, + { /* 8454 */ + 218, + /* VPADDBZ256rmk */ + }, + { /* 8455 */ + 219, + /* VPADDBZ256rmkz */ + }, + { /* 8456 */ + 220, + /* VPADDBZ256rr */ + }, + { /* 8457 */ + 221, + /* VPADDBZ256rrk */ + }, + { /* 8458 */ + 222, + /* VPADDBZ256rrkz */ + }, + { /* 8459 */ + 223, + /* VPADDBZrm */ + }, + { /* 8460 */ + 227, + /* VPADDBZrmk */ + }, + { /* 8461 */ + 228, + /* VPADDBZrmkz */ + }, + { /* 8462 */ + 229, + /* VPADDBZrr */ + }, + { /* 8463 */ + 233, + /* VPADDBZrrk */ + }, + { /* 8464 */ + 234, + /* VPADDBZrrkz */ + }, + { /* 8465 */ + 235, + /* VPADDBrm */ + }, + { /* 8466 */ + 236, + /* VPADDBrr */ + }, + { /* 8467 */ + 204, + /* VPADDDYrm */ + }, + { /* 8468 */ + 205, + /* VPADDDYrr */ + }, + { /* 8469 */ + 206, + /* VPADDDZ128rm */ + }, + { /* 8470 */ + 237, + /* VPADDDZ128rmb */ + }, + { /* 8471 */ + 238, + /* VPADDDZ128rmbk */ + }, + { /* 8472 */ + 239, + /* VPADDDZ128rmbkz */ + }, + { /* 8473 */ + 203, + /* VPADDDZ128rmk */ + }, + { /* 8474 */ + 210, + /* VPADDDZ128rmkz */ + }, + { /* 8475 */ + 211, + /* VPADDDZ128rr */ + }, + { /* 8476 */ + 212, + /* VPADDDZ128rrk */ + }, + { /* 8477 */ + 213, + /* VPADDDZ128rrkz */ + }, + { /* 8478 */ + 214, + /* VPADDDZ256rm */ + }, + { /* 8479 */ + 240, + /* VPADDDZ256rmb */ + }, + { /* 8480 */ + 241, + /* VPADDDZ256rmbk */ + }, + { /* 8481 */ + 242, + /* VPADDDZ256rmbkz */ + }, + { /* 8482 */ + 218, + /* VPADDDZ256rmk */ + }, + { /* 8483 */ + 219, + /* VPADDDZ256rmkz */ + }, + { /* 8484 */ + 220, + /* VPADDDZ256rr */ + }, + { /* 8485 */ + 221, + /* VPADDDZ256rrk */ + }, + { /* 8486 */ + 222, + /* VPADDDZ256rrkz */ + }, + { /* 8487 */ + 223, + /* VPADDDZrm */ + }, + { /* 8488 */ + 243, + /* VPADDDZrmb */ + }, + { /* 8489 */ + 244, + /* VPADDDZrmbk */ + }, + { /* 8490 */ + 245, + /* VPADDDZrmbkz */ + }, + { /* 8491 */ + 227, + /* VPADDDZrmk */ + }, + { /* 8492 */ + 228, + /* VPADDDZrmkz */ + }, + { /* 8493 */ + 229, + /* VPADDDZrr */ + }, + { /* 8494 */ + 233, + /* VPADDDZrrk */ + }, + { /* 8495 */ + 234, + /* VPADDDZrrkz */ + }, + { /* 8496 */ + 235, + /* VPADDDrm */ + }, + { /* 8497 */ + 236, + /* VPADDDrr */ + }, + { /* 8498 */ + 204, + /* VPADDQYrm */ + }, + { /* 8499 */ + 205, + /* VPADDQYrr */ + }, + { /* 8500 */ + 206, + /* VPADDQZ128rm */ + }, + { /* 8501 */ + 207, + /* VPADDQZ128rmb */ + }, + { /* 8502 */ + 208, + /* VPADDQZ128rmbk */ + }, + { /* 8503 */ + 209, + /* VPADDQZ128rmbkz */ + }, + { /* 8504 */ + 203, + /* VPADDQZ128rmk */ + }, + { /* 8505 */ + 210, + /* VPADDQZ128rmkz */ + }, + { /* 8506 */ + 211, + /* VPADDQZ128rr */ + }, + { /* 8507 */ + 212, + /* VPADDQZ128rrk */ + }, + { /* 8508 */ + 213, + /* VPADDQZ128rrkz */ + }, + { /* 8509 */ + 214, + /* VPADDQZ256rm */ + }, + { /* 8510 */ + 215, + /* VPADDQZ256rmb */ + }, + { /* 8511 */ + 216, + /* VPADDQZ256rmbk */ + }, + { /* 8512 */ + 217, + /* VPADDQZ256rmbkz */ + }, + { /* 8513 */ + 218, + /* VPADDQZ256rmk */ + }, + { /* 8514 */ + 219, + /* VPADDQZ256rmkz */ + }, + { /* 8515 */ + 220, + /* VPADDQZ256rr */ + }, + { /* 8516 */ + 221, + /* VPADDQZ256rrk */ + }, + { /* 8517 */ + 222, + /* VPADDQZ256rrkz */ + }, + { /* 8518 */ + 223, + /* VPADDQZrm */ + }, + { /* 8519 */ + 224, + /* VPADDQZrmb */ + }, + { /* 8520 */ + 225, + /* VPADDQZrmbk */ + }, + { /* 8521 */ + 226, + /* VPADDQZrmbkz */ + }, + { /* 8522 */ + 227, + /* VPADDQZrmk */ + }, + { /* 8523 */ + 228, + /* VPADDQZrmkz */ + }, + { /* 8524 */ + 229, + /* VPADDQZrr */ + }, + { /* 8525 */ + 233, + /* VPADDQZrrk */ + }, + { /* 8526 */ + 234, + /* VPADDQZrrkz */ + }, + { /* 8527 */ + 235, + /* VPADDQrm */ + }, + { /* 8528 */ + 236, + /* VPADDQrr */ + }, + { /* 8529 */ + 204, + /* VPADDSBYrm */ + }, + { /* 8530 */ + 205, + /* VPADDSBYrr */ + }, + { /* 8531 */ + 206, + /* VPADDSBZ128rm */ + }, + { /* 8532 */ + 203, + /* VPADDSBZ128rmk */ + }, + { /* 8533 */ + 210, + /* VPADDSBZ128rmkz */ + }, + { /* 8534 */ + 211, + /* VPADDSBZ128rr */ + }, + { /* 8535 */ + 212, + /* VPADDSBZ128rrk */ + }, + { /* 8536 */ + 213, + /* VPADDSBZ128rrkz */ + }, + { /* 8537 */ + 214, + /* VPADDSBZ256rm */ + }, + { /* 8538 */ + 218, + /* VPADDSBZ256rmk */ + }, + { /* 8539 */ + 219, + /* VPADDSBZ256rmkz */ + }, + { /* 8540 */ + 220, + /* VPADDSBZ256rr */ + }, + { /* 8541 */ + 221, + /* VPADDSBZ256rrk */ + }, + { /* 8542 */ + 222, + /* VPADDSBZ256rrkz */ + }, + { /* 8543 */ + 223, + /* VPADDSBZrm */ + }, + { /* 8544 */ + 227, + /* VPADDSBZrmk */ + }, + { /* 8545 */ + 228, + /* VPADDSBZrmkz */ + }, + { /* 8546 */ + 229, + /* VPADDSBZrr */ + }, + { /* 8547 */ + 233, + /* VPADDSBZrrk */ + }, + { /* 8548 */ + 234, + /* VPADDSBZrrkz */ + }, + { /* 8549 */ + 235, + /* VPADDSBrm */ + }, + { /* 8550 */ + 236, + /* VPADDSBrr */ + }, + { /* 8551 */ + 204, + /* VPADDSWYrm */ + }, + { /* 8552 */ + 205, + /* VPADDSWYrr */ + }, + { /* 8553 */ + 206, + /* VPADDSWZ128rm */ + }, + { /* 8554 */ + 203, + /* VPADDSWZ128rmk */ + }, + { /* 8555 */ + 210, + /* VPADDSWZ128rmkz */ + }, + { /* 8556 */ + 211, + /* VPADDSWZ128rr */ + }, + { /* 8557 */ + 212, + /* VPADDSWZ128rrk */ + }, + { /* 8558 */ + 213, + /* VPADDSWZ128rrkz */ + }, + { /* 8559 */ + 214, + /* VPADDSWZ256rm */ + }, + { /* 8560 */ + 218, + /* VPADDSWZ256rmk */ + }, + { /* 8561 */ + 219, + /* VPADDSWZ256rmkz */ + }, + { /* 8562 */ + 220, + /* VPADDSWZ256rr */ + }, + { /* 8563 */ + 221, + /* VPADDSWZ256rrk */ + }, + { /* 8564 */ + 222, + /* VPADDSWZ256rrkz */ + }, + { /* 8565 */ + 223, + /* VPADDSWZrm */ + }, + { /* 8566 */ + 227, + /* VPADDSWZrmk */ + }, + { /* 8567 */ + 228, + /* VPADDSWZrmkz */ + }, + { /* 8568 */ + 229, + /* VPADDSWZrr */ + }, + { /* 8569 */ + 233, + /* VPADDSWZrrk */ + }, + { /* 8570 */ + 234, + /* VPADDSWZrrkz */ + }, + { /* 8571 */ + 235, + /* VPADDSWrm */ + }, + { /* 8572 */ + 236, + /* VPADDSWrr */ + }, + { /* 8573 */ + 204, + /* VPADDUSBYrm */ + }, + { /* 8574 */ + 205, + /* VPADDUSBYrr */ + }, + { /* 8575 */ + 206, + /* VPADDUSBZ128rm */ + }, + { /* 8576 */ + 203, + /* VPADDUSBZ128rmk */ + }, + { /* 8577 */ + 210, + /* VPADDUSBZ128rmkz */ + }, + { /* 8578 */ + 211, + /* VPADDUSBZ128rr */ + }, + { /* 8579 */ + 212, + /* VPADDUSBZ128rrk */ + }, + { /* 8580 */ + 213, + /* VPADDUSBZ128rrkz */ + }, + { /* 8581 */ + 214, + /* VPADDUSBZ256rm */ + }, + { /* 8582 */ + 218, + /* VPADDUSBZ256rmk */ + }, + { /* 8583 */ + 219, + /* VPADDUSBZ256rmkz */ + }, + { /* 8584 */ + 220, + /* VPADDUSBZ256rr */ + }, + { /* 8585 */ + 221, + /* VPADDUSBZ256rrk */ + }, + { /* 8586 */ + 222, + /* VPADDUSBZ256rrkz */ + }, + { /* 8587 */ + 223, + /* VPADDUSBZrm */ + }, + { /* 8588 */ + 227, + /* VPADDUSBZrmk */ + }, + { /* 8589 */ + 228, + /* VPADDUSBZrmkz */ + }, + { /* 8590 */ + 229, + /* VPADDUSBZrr */ + }, + { /* 8591 */ + 233, + /* VPADDUSBZrrk */ + }, + { /* 8592 */ + 234, + /* VPADDUSBZrrkz */ + }, + { /* 8593 */ + 235, + /* VPADDUSBrm */ + }, + { /* 8594 */ + 236, + /* VPADDUSBrr */ + }, + { /* 8595 */ + 204, + /* VPADDUSWYrm */ + }, + { /* 8596 */ + 205, + /* VPADDUSWYrr */ + }, + { /* 8597 */ + 206, + /* VPADDUSWZ128rm */ + }, + { /* 8598 */ + 203, + /* VPADDUSWZ128rmk */ + }, + { /* 8599 */ + 210, + /* VPADDUSWZ128rmkz */ + }, + { /* 8600 */ + 211, + /* VPADDUSWZ128rr */ + }, + { /* 8601 */ + 212, + /* VPADDUSWZ128rrk */ + }, + { /* 8602 */ + 213, + /* VPADDUSWZ128rrkz */ + }, + { /* 8603 */ + 214, + /* VPADDUSWZ256rm */ + }, + { /* 8604 */ + 218, + /* VPADDUSWZ256rmk */ + }, + { /* 8605 */ + 219, + /* VPADDUSWZ256rmkz */ + }, + { /* 8606 */ + 220, + /* VPADDUSWZ256rr */ + }, + { /* 8607 */ + 221, + /* VPADDUSWZ256rrk */ + }, + { /* 8608 */ + 222, + /* VPADDUSWZ256rrkz */ + }, + { /* 8609 */ + 223, + /* VPADDUSWZrm */ + }, + { /* 8610 */ + 227, + /* VPADDUSWZrmk */ + }, + { /* 8611 */ + 228, + /* VPADDUSWZrmkz */ + }, + { /* 8612 */ + 229, + /* VPADDUSWZrr */ + }, + { /* 8613 */ + 233, + /* VPADDUSWZrrk */ + }, + { /* 8614 */ + 234, + /* VPADDUSWZrrkz */ + }, + { /* 8615 */ + 235, + /* VPADDUSWrm */ + }, + { /* 8616 */ + 236, + /* VPADDUSWrr */ + }, + { /* 8617 */ + 204, + /* VPADDWYrm */ + }, + { /* 8618 */ + 205, + /* VPADDWYrr */ + }, + { /* 8619 */ + 206, + /* VPADDWZ128rm */ + }, + { /* 8620 */ + 203, + /* VPADDWZ128rmk */ + }, + { /* 8621 */ + 210, + /* VPADDWZ128rmkz */ + }, + { /* 8622 */ + 211, + /* VPADDWZ128rr */ + }, + { /* 8623 */ + 212, + /* VPADDWZ128rrk */ + }, + { /* 8624 */ + 213, + /* VPADDWZ128rrkz */ + }, + { /* 8625 */ + 214, + /* VPADDWZ256rm */ + }, + { /* 8626 */ + 218, + /* VPADDWZ256rmk */ + }, + { /* 8627 */ + 219, + /* VPADDWZ256rmkz */ + }, + { /* 8628 */ + 220, + /* VPADDWZ256rr */ + }, + { /* 8629 */ + 221, + /* VPADDWZ256rrk */ + }, + { /* 8630 */ + 222, + /* VPADDWZ256rrkz */ + }, + { /* 8631 */ + 223, + /* VPADDWZrm */ + }, + { /* 8632 */ + 227, + /* VPADDWZrmk */ + }, + { /* 8633 */ + 228, + /* VPADDWZrmkz */ + }, + { /* 8634 */ + 229, + /* VPADDWZrr */ + }, + { /* 8635 */ + 233, + /* VPADDWZrrk */ + }, + { /* 8636 */ + 234, + /* VPADDWZrrkz */ + }, + { /* 8637 */ + 235, + /* VPADDWrm */ + }, + { /* 8638 */ + 236, + /* VPADDWrr */ + }, + { /* 8639 */ + 297, + /* VPALIGNRYrmi */ + }, + { /* 8640 */ + 298, + /* VPALIGNRYrri */ + }, + { /* 8641 */ + 264, + /* VPALIGNRZ128rmi */ + }, + { /* 8642 */ + 265, + /* VPALIGNRZ128rmik */ + }, + { /* 8643 */ + 266, + /* VPALIGNRZ128rmikz */ + }, + { /* 8644 */ + 267, + /* VPALIGNRZ128rri */ + }, + { /* 8645 */ + 268, + /* VPALIGNRZ128rrik */ + }, + { /* 8646 */ + 269, + /* VPALIGNRZ128rrikz */ + }, + { /* 8647 */ + 273, + /* VPALIGNRZ256rmi */ + }, + { /* 8648 */ + 274, + /* VPALIGNRZ256rmik */ + }, + { /* 8649 */ + 275, + /* VPALIGNRZ256rmikz */ + }, + { /* 8650 */ + 276, + /* VPALIGNRZ256rri */ + }, + { /* 8651 */ + 277, + /* VPALIGNRZ256rrik */ + }, + { /* 8652 */ + 278, + /* VPALIGNRZ256rrikz */ + }, + { /* 8653 */ + 282, + /* VPALIGNRZrmi */ + }, + { /* 8654 */ + 283, + /* VPALIGNRZrmik */ + }, + { /* 8655 */ + 284, + /* VPALIGNRZrmikz */ + }, + { /* 8656 */ + 285, + /* VPALIGNRZrri */ + }, + { /* 8657 */ + 286, + /* VPALIGNRZrrik */ + }, + { /* 8658 */ + 287, + /* VPALIGNRZrrikz */ + }, + { /* 8659 */ + 299, + /* VPALIGNRrmi */ + }, + { /* 8660 */ + 300, + /* VPALIGNRrri */ + }, + { /* 8661 */ + 206, + /* VPANDDZ128rm */ + }, + { /* 8662 */ + 237, + /* VPANDDZ128rmb */ + }, + { /* 8663 */ + 238, + /* VPANDDZ128rmbk */ + }, + { /* 8664 */ + 239, + /* VPANDDZ128rmbkz */ + }, + { /* 8665 */ + 203, + /* VPANDDZ128rmk */ + }, + { /* 8666 */ + 210, + /* VPANDDZ128rmkz */ + }, + { /* 8667 */ + 211, + /* VPANDDZ128rr */ + }, + { /* 8668 */ + 212, + /* VPANDDZ128rrk */ + }, + { /* 8669 */ + 213, + /* VPANDDZ128rrkz */ + }, + { /* 8670 */ + 214, + /* VPANDDZ256rm */ + }, + { /* 8671 */ + 240, + /* VPANDDZ256rmb */ + }, + { /* 8672 */ + 241, + /* VPANDDZ256rmbk */ + }, + { /* 8673 */ + 242, + /* VPANDDZ256rmbkz */ + }, + { /* 8674 */ + 218, + /* VPANDDZ256rmk */ + }, + { /* 8675 */ + 219, + /* VPANDDZ256rmkz */ + }, + { /* 8676 */ + 220, + /* VPANDDZ256rr */ + }, + { /* 8677 */ + 221, + /* VPANDDZ256rrk */ + }, + { /* 8678 */ + 222, + /* VPANDDZ256rrkz */ + }, + { /* 8679 */ + 223, + /* VPANDDZrm */ + }, + { /* 8680 */ + 243, + /* VPANDDZrmb */ + }, + { /* 8681 */ + 244, + /* VPANDDZrmbk */ + }, + { /* 8682 */ + 245, + /* VPANDDZrmbkz */ + }, + { /* 8683 */ + 227, + /* VPANDDZrmk */ + }, + { /* 8684 */ + 228, + /* VPANDDZrmkz */ + }, + { /* 8685 */ + 229, + /* VPANDDZrr */ + }, + { /* 8686 */ + 233, + /* VPANDDZrrk */ + }, + { /* 8687 */ + 234, + /* VPANDDZrrkz */ + }, + { /* 8688 */ + 206, + /* VPANDNDZ128rm */ + }, + { /* 8689 */ + 237, + /* VPANDNDZ128rmb */ + }, + { /* 8690 */ + 238, + /* VPANDNDZ128rmbk */ + }, + { /* 8691 */ + 239, + /* VPANDNDZ128rmbkz */ + }, + { /* 8692 */ + 203, + /* VPANDNDZ128rmk */ + }, + { /* 8693 */ + 210, + /* VPANDNDZ128rmkz */ + }, + { /* 8694 */ + 211, + /* VPANDNDZ128rr */ + }, + { /* 8695 */ + 212, + /* VPANDNDZ128rrk */ + }, + { /* 8696 */ + 213, + /* VPANDNDZ128rrkz */ + }, + { /* 8697 */ + 214, + /* VPANDNDZ256rm */ + }, + { /* 8698 */ + 240, + /* VPANDNDZ256rmb */ + }, + { /* 8699 */ + 241, + /* VPANDNDZ256rmbk */ + }, + { /* 8700 */ + 242, + /* VPANDNDZ256rmbkz */ + }, + { /* 8701 */ + 218, + /* VPANDNDZ256rmk */ + }, + { /* 8702 */ + 219, + /* VPANDNDZ256rmkz */ + }, + { /* 8703 */ + 220, + /* VPANDNDZ256rr */ + }, + { /* 8704 */ + 221, + /* VPANDNDZ256rrk */ + }, + { /* 8705 */ + 222, + /* VPANDNDZ256rrkz */ + }, + { /* 8706 */ + 223, + /* VPANDNDZrm */ + }, + { /* 8707 */ + 243, + /* VPANDNDZrmb */ + }, + { /* 8708 */ + 244, + /* VPANDNDZrmbk */ + }, + { /* 8709 */ + 245, + /* VPANDNDZrmbkz */ + }, + { /* 8710 */ + 227, + /* VPANDNDZrmk */ + }, + { /* 8711 */ + 228, + /* VPANDNDZrmkz */ + }, + { /* 8712 */ + 229, + /* VPANDNDZrr */ + }, + { /* 8713 */ + 233, + /* VPANDNDZrrk */ + }, + { /* 8714 */ + 234, + /* VPANDNDZrrkz */ + }, + { /* 8715 */ + 206, + /* VPANDNQZ128rm */ + }, + { /* 8716 */ + 207, + /* VPANDNQZ128rmb */ + }, + { /* 8717 */ + 208, + /* VPANDNQZ128rmbk */ + }, + { /* 8718 */ + 209, + /* VPANDNQZ128rmbkz */ + }, + { /* 8719 */ + 203, + /* VPANDNQZ128rmk */ + }, + { /* 8720 */ + 210, + /* VPANDNQZ128rmkz */ + }, + { /* 8721 */ + 211, + /* VPANDNQZ128rr */ + }, + { /* 8722 */ + 212, + /* VPANDNQZ128rrk */ + }, + { /* 8723 */ + 213, + /* VPANDNQZ128rrkz */ + }, + { /* 8724 */ + 214, + /* VPANDNQZ256rm */ + }, + { /* 8725 */ + 215, + /* VPANDNQZ256rmb */ + }, + { /* 8726 */ + 216, + /* VPANDNQZ256rmbk */ + }, + { /* 8727 */ + 217, + /* VPANDNQZ256rmbkz */ + }, + { /* 8728 */ + 218, + /* VPANDNQZ256rmk */ + }, + { /* 8729 */ + 219, + /* VPANDNQZ256rmkz */ + }, + { /* 8730 */ + 220, + /* VPANDNQZ256rr */ + }, + { /* 8731 */ + 221, + /* VPANDNQZ256rrk */ + }, + { /* 8732 */ + 222, + /* VPANDNQZ256rrkz */ + }, + { /* 8733 */ + 223, + /* VPANDNQZrm */ + }, + { /* 8734 */ + 224, + /* VPANDNQZrmb */ + }, + { /* 8735 */ + 225, + /* VPANDNQZrmbk */ + }, + { /* 8736 */ + 226, + /* VPANDNQZrmbkz */ + }, + { /* 8737 */ + 227, + /* VPANDNQZrmk */ + }, + { /* 8738 */ + 228, + /* VPANDNQZrmkz */ + }, + { /* 8739 */ + 229, + /* VPANDNQZrr */ + }, + { /* 8740 */ + 233, + /* VPANDNQZrrk */ + }, + { /* 8741 */ + 234, + /* VPANDNQZrrkz */ + }, + { /* 8742 */ + 204, + /* VPANDNYrm */ + }, + { /* 8743 */ + 205, + /* VPANDNYrr */ + }, + { /* 8744 */ + 235, + /* VPANDNrm */ + }, + { /* 8745 */ + 236, + /* VPANDNrr */ + }, + { /* 8746 */ + 206, + /* VPANDQZ128rm */ + }, + { /* 8747 */ + 207, + /* VPANDQZ128rmb */ + }, + { /* 8748 */ + 208, + /* VPANDQZ128rmbk */ + }, + { /* 8749 */ + 209, + /* VPANDQZ128rmbkz */ + }, + { /* 8750 */ + 203, + /* VPANDQZ128rmk */ + }, + { /* 8751 */ + 210, + /* VPANDQZ128rmkz */ + }, + { /* 8752 */ + 211, + /* VPANDQZ128rr */ + }, + { /* 8753 */ + 212, + /* VPANDQZ128rrk */ + }, + { /* 8754 */ + 213, + /* VPANDQZ128rrkz */ + }, + { /* 8755 */ + 214, + /* VPANDQZ256rm */ + }, + { /* 8756 */ + 215, + /* VPANDQZ256rmb */ + }, + { /* 8757 */ + 216, + /* VPANDQZ256rmbk */ + }, + { /* 8758 */ + 217, + /* VPANDQZ256rmbkz */ + }, + { /* 8759 */ + 218, + /* VPANDQZ256rmk */ + }, + { /* 8760 */ + 219, + /* VPANDQZ256rmkz */ + }, + { /* 8761 */ + 220, + /* VPANDQZ256rr */ + }, + { /* 8762 */ + 221, + /* VPANDQZ256rrk */ + }, + { /* 8763 */ + 222, + /* VPANDQZ256rrkz */ + }, + { /* 8764 */ + 223, + /* VPANDQZrm */ + }, + { /* 8765 */ + 224, + /* VPANDQZrmb */ + }, + { /* 8766 */ + 225, + /* VPANDQZrmbk */ + }, + { /* 8767 */ + 226, + /* VPANDQZrmbkz */ + }, + { /* 8768 */ + 227, + /* VPANDQZrmk */ + }, + { /* 8769 */ + 228, + /* VPANDQZrmkz */ + }, + { /* 8770 */ + 229, + /* VPANDQZrr */ + }, + { /* 8771 */ + 233, + /* VPANDQZrrk */ + }, + { /* 8772 */ + 234, + /* VPANDQZrrkz */ + }, + { /* 8773 */ + 204, + /* VPANDYrm */ + }, + { /* 8774 */ + 205, + /* VPANDYrr */ + }, + { /* 8775 */ + 235, + /* VPANDrm */ + }, + { /* 8776 */ + 236, + /* VPANDrr */ + }, + { /* 8777 */ + 204, + /* VPAVGBYrm */ + }, + { /* 8778 */ + 205, + /* VPAVGBYrr */ + }, + { /* 8779 */ + 206, + /* VPAVGBZ128rm */ + }, + { /* 8780 */ + 203, + /* VPAVGBZ128rmk */ + }, + { /* 8781 */ + 210, + /* VPAVGBZ128rmkz */ + }, + { /* 8782 */ + 211, + /* VPAVGBZ128rr */ + }, + { /* 8783 */ + 212, + /* VPAVGBZ128rrk */ + }, + { /* 8784 */ + 213, + /* VPAVGBZ128rrkz */ + }, + { /* 8785 */ + 214, + /* VPAVGBZ256rm */ + }, + { /* 8786 */ + 218, + /* VPAVGBZ256rmk */ + }, + { /* 8787 */ + 219, + /* VPAVGBZ256rmkz */ + }, + { /* 8788 */ + 220, + /* VPAVGBZ256rr */ + }, + { /* 8789 */ + 221, + /* VPAVGBZ256rrk */ + }, + { /* 8790 */ + 222, + /* VPAVGBZ256rrkz */ + }, + { /* 8791 */ + 223, + /* VPAVGBZrm */ + }, + { /* 8792 */ + 227, + /* VPAVGBZrmk */ + }, + { /* 8793 */ + 228, + /* VPAVGBZrmkz */ + }, + { /* 8794 */ + 229, + /* VPAVGBZrr */ + }, + { /* 8795 */ + 233, + /* VPAVGBZrrk */ + }, + { /* 8796 */ + 234, + /* VPAVGBZrrkz */ + }, + { /* 8797 */ + 235, + /* VPAVGBrm */ + }, + { /* 8798 */ + 236, + /* VPAVGBrr */ + }, + { /* 8799 */ + 204, + /* VPAVGWYrm */ + }, + { /* 8800 */ + 205, + /* VPAVGWYrr */ + }, + { /* 8801 */ + 206, + /* VPAVGWZ128rm */ + }, + { /* 8802 */ + 203, + /* VPAVGWZ128rmk */ + }, + { /* 8803 */ + 210, + /* VPAVGWZ128rmkz */ + }, + { /* 8804 */ + 211, + /* VPAVGWZ128rr */ + }, + { /* 8805 */ + 212, + /* VPAVGWZ128rrk */ + }, + { /* 8806 */ + 213, + /* VPAVGWZ128rrkz */ + }, + { /* 8807 */ + 214, + /* VPAVGWZ256rm */ + }, + { /* 8808 */ + 218, + /* VPAVGWZ256rmk */ + }, + { /* 8809 */ + 219, + /* VPAVGWZ256rmkz */ + }, + { /* 8810 */ + 220, + /* VPAVGWZ256rr */ + }, + { /* 8811 */ + 221, + /* VPAVGWZ256rrk */ + }, + { /* 8812 */ + 222, + /* VPAVGWZ256rrkz */ + }, + { /* 8813 */ + 223, + /* VPAVGWZrm */ + }, + { /* 8814 */ + 227, + /* VPAVGWZrmk */ + }, + { /* 8815 */ + 228, + /* VPAVGWZrmkz */ + }, + { /* 8816 */ + 229, + /* VPAVGWZrr */ + }, + { /* 8817 */ + 233, + /* VPAVGWZrrk */ + }, + { /* 8818 */ + 234, + /* VPAVGWZrrkz */ + }, + { /* 8819 */ + 235, + /* VPAVGWrm */ + }, + { /* 8820 */ + 236, + /* VPAVGWrr */ + }, + { /* 8821 */ + 297, + /* VPBLENDDYrmi */ + }, + { /* 8822 */ + 298, + /* VPBLENDDYrri */ + }, + { /* 8823 */ + 299, + /* VPBLENDDrmi */ + }, + { /* 8824 */ + 300, + /* VPBLENDDrri */ + }, + { /* 8825 */ + 206, + /* VPBLENDMBZ128rm */ + }, + { /* 8826 */ + 210, + /* VPBLENDMBZ128rmk */ + }, + { /* 8827 */ + 210, + /* VPBLENDMBZ128rmkz */ + }, + { /* 8828 */ + 211, + /* VPBLENDMBZ128rr */ + }, + { /* 8829 */ + 213, + /* VPBLENDMBZ128rrk */ + }, + { /* 8830 */ + 213, + /* VPBLENDMBZ128rrkz */ + }, + { /* 8831 */ + 214, + /* VPBLENDMBZ256rm */ + }, + { /* 8832 */ + 219, + /* VPBLENDMBZ256rmk */ + }, + { /* 8833 */ + 219, + /* VPBLENDMBZ256rmkz */ + }, + { /* 8834 */ + 220, + /* VPBLENDMBZ256rr */ + }, + { /* 8835 */ + 222, + /* VPBLENDMBZ256rrk */ + }, + { /* 8836 */ + 222, + /* VPBLENDMBZ256rrkz */ + }, + { /* 8837 */ + 223, + /* VPBLENDMBZrm */ + }, + { /* 8838 */ + 228, + /* VPBLENDMBZrmk */ + }, + { /* 8839 */ + 228, + /* VPBLENDMBZrmkz */ + }, + { /* 8840 */ + 229, + /* VPBLENDMBZrr */ + }, + { /* 8841 */ + 234, + /* VPBLENDMBZrrk */ + }, + { /* 8842 */ + 234, + /* VPBLENDMBZrrkz */ + }, + { /* 8843 */ + 206, + /* VPBLENDMDZ128rm */ + }, + { /* 8844 */ + 237, + /* VPBLENDMDZ128rmb */ + }, + { /* 8845 */ + 239, + /* VPBLENDMDZ128rmbk */ + }, + { /* 8846 */ + 239, + /* VPBLENDMDZ128rmbkz */ + }, + { /* 8847 */ + 210, + /* VPBLENDMDZ128rmk */ + }, + { /* 8848 */ + 210, + /* VPBLENDMDZ128rmkz */ + }, + { /* 8849 */ + 211, + /* VPBLENDMDZ128rr */ + }, + { /* 8850 */ + 213, + /* VPBLENDMDZ128rrk */ + }, + { /* 8851 */ + 213, + /* VPBLENDMDZ128rrkz */ + }, + { /* 8852 */ + 214, + /* VPBLENDMDZ256rm */ + }, + { /* 8853 */ + 240, + /* VPBLENDMDZ256rmb */ + }, + { /* 8854 */ + 242, + /* VPBLENDMDZ256rmbk */ + }, + { /* 8855 */ + 242, + /* VPBLENDMDZ256rmbkz */ + }, + { /* 8856 */ + 219, + /* VPBLENDMDZ256rmk */ + }, + { /* 8857 */ + 219, + /* VPBLENDMDZ256rmkz */ + }, + { /* 8858 */ + 220, + /* VPBLENDMDZ256rr */ + }, + { /* 8859 */ + 222, + /* VPBLENDMDZ256rrk */ + }, + { /* 8860 */ + 222, + /* VPBLENDMDZ256rrkz */ + }, + { /* 8861 */ + 223, + /* VPBLENDMDZrm */ + }, + { /* 8862 */ + 243, + /* VPBLENDMDZrmb */ + }, + { /* 8863 */ + 245, + /* VPBLENDMDZrmbk */ + }, + { /* 8864 */ + 245, + /* VPBLENDMDZrmbkz */ + }, + { /* 8865 */ + 228, + /* VPBLENDMDZrmk */ + }, + { /* 8866 */ + 228, + /* VPBLENDMDZrmkz */ + }, + { /* 8867 */ + 229, + /* VPBLENDMDZrr */ + }, + { /* 8868 */ + 234, + /* VPBLENDMDZrrk */ + }, + { /* 8869 */ + 234, + /* VPBLENDMDZrrkz */ + }, + { /* 8870 */ + 206, + /* VPBLENDMQZ128rm */ + }, + { /* 8871 */ + 207, + /* VPBLENDMQZ128rmb */ + }, + { /* 8872 */ + 209, + /* VPBLENDMQZ128rmbk */ + }, + { /* 8873 */ + 209, + /* VPBLENDMQZ128rmbkz */ + }, + { /* 8874 */ + 210, + /* VPBLENDMQZ128rmk */ + }, + { /* 8875 */ + 210, + /* VPBLENDMQZ128rmkz */ + }, + { /* 8876 */ + 211, + /* VPBLENDMQZ128rr */ + }, + { /* 8877 */ + 213, + /* VPBLENDMQZ128rrk */ + }, + { /* 8878 */ + 213, + /* VPBLENDMQZ128rrkz */ + }, + { /* 8879 */ + 214, + /* VPBLENDMQZ256rm */ + }, + { /* 8880 */ + 215, + /* VPBLENDMQZ256rmb */ + }, + { /* 8881 */ + 217, + /* VPBLENDMQZ256rmbk */ + }, + { /* 8882 */ + 217, + /* VPBLENDMQZ256rmbkz */ + }, + { /* 8883 */ + 219, + /* VPBLENDMQZ256rmk */ + }, + { /* 8884 */ + 219, + /* VPBLENDMQZ256rmkz */ + }, + { /* 8885 */ + 220, + /* VPBLENDMQZ256rr */ + }, + { /* 8886 */ + 222, + /* VPBLENDMQZ256rrk */ + }, + { /* 8887 */ + 222, + /* VPBLENDMQZ256rrkz */ + }, + { /* 8888 */ + 223, + /* VPBLENDMQZrm */ + }, + { /* 8889 */ + 224, + /* VPBLENDMQZrmb */ + }, + { /* 8890 */ + 226, + /* VPBLENDMQZrmbk */ + }, + { /* 8891 */ + 226, + /* VPBLENDMQZrmbkz */ + }, + { /* 8892 */ + 228, + /* VPBLENDMQZrmk */ + }, + { /* 8893 */ + 228, + /* VPBLENDMQZrmkz */ + }, + { /* 8894 */ + 229, + /* VPBLENDMQZrr */ + }, + { /* 8895 */ + 234, + /* VPBLENDMQZrrk */ + }, + { /* 8896 */ + 234, + /* VPBLENDMQZrrkz */ + }, + { /* 8897 */ + 206, + /* VPBLENDMWZ128rm */ + }, + { /* 8898 */ + 210, + /* VPBLENDMWZ128rmk */ + }, + { /* 8899 */ + 210, + /* VPBLENDMWZ128rmkz */ + }, + { /* 8900 */ + 211, + /* VPBLENDMWZ128rr */ + }, + { /* 8901 */ + 213, + /* VPBLENDMWZ128rrk */ + }, + { /* 8902 */ + 213, + /* VPBLENDMWZ128rrkz */ + }, + { /* 8903 */ + 214, + /* VPBLENDMWZ256rm */ + }, + { /* 8904 */ + 219, + /* VPBLENDMWZ256rmk */ + }, + { /* 8905 */ + 219, + /* VPBLENDMWZ256rmkz */ + }, + { /* 8906 */ + 220, + /* VPBLENDMWZ256rr */ + }, + { /* 8907 */ + 222, + /* VPBLENDMWZ256rrk */ + }, + { /* 8908 */ + 222, + /* VPBLENDMWZ256rrkz */ + }, + { /* 8909 */ + 223, + /* VPBLENDMWZrm */ + }, + { /* 8910 */ + 228, + /* VPBLENDMWZrmk */ + }, + { /* 8911 */ + 228, + /* VPBLENDMWZrmkz */ + }, + { /* 8912 */ + 229, + /* VPBLENDMWZrr */ + }, + { /* 8913 */ + 234, + /* VPBLENDMWZrrk */ + }, + { /* 8914 */ + 234, + /* VPBLENDMWZrrkz */ + }, + { /* 8915 */ + 301, + /* VPBLENDVBYrm */ + }, + { /* 8916 */ + 302, + /* VPBLENDVBYrr */ + }, + { /* 8917 */ + 303, + /* VPBLENDVBrm */ + }, + { /* 8918 */ + 304, + /* VPBLENDVBrr */ + }, + { /* 8919 */ + 297, + /* VPBLENDWYrmi */ + }, + { /* 8920 */ + 298, + /* VPBLENDWYrri */ + }, + { /* 8921 */ + 299, + /* VPBLENDWrmi */ + }, + { /* 8922 */ + 300, + /* VPBLENDWrri */ + }, + { /* 8923 */ + 305, + /* VPBROADCASTBYrm */ + }, + { /* 8924 */ + 333, + /* VPBROADCASTBYrr */ + }, + { /* 8925 */ + 30, + /* VPBROADCASTBZ128m */ + }, + { /* 8926 */ + 688, + /* VPBROADCASTBZ128mk */ + }, + { /* 8927 */ + 689, + /* VPBROADCASTBZ128mkz */ + }, + { /* 8928 */ + 330, + /* VPBROADCASTBZ128r */ + }, + { /* 8929 */ + 331, + /* VPBROADCASTBZ128rk */ + }, + { /* 8930 */ + 332, + /* VPBROADCASTBZ128rkz */ + }, + { /* 8931 */ + 305, + /* VPBROADCASTBZ256m */ + }, + { /* 8932 */ + 690, + /* VPBROADCASTBZ256mk */ + }, + { /* 8933 */ + 691, + /* VPBROADCASTBZ256mkz */ + }, + { /* 8934 */ + 309, + /* VPBROADCASTBZ256r */ + }, + { /* 8935 */ + 310, + /* VPBROADCASTBZ256rk */ + }, + { /* 8936 */ + 311, + /* VPBROADCASTBZ256rkz */ + }, + { /* 8937 */ + 692, + /* VPBROADCASTBZm */ + }, + { /* 8938 */ + 693, + /* VPBROADCASTBZmk */ + }, + { /* 8939 */ + 694, + /* VPBROADCASTBZmkz */ + }, + { /* 8940 */ + 315, + /* VPBROADCASTBZr */ + }, + { /* 8941 */ + 316, + /* VPBROADCASTBZrk */ + }, + { /* 8942 */ + 317, + /* VPBROADCASTBZrkz */ + }, + { /* 8943 */ + 678, + /* VPBROADCASTBrZ128r */ + }, + { /* 8944 */ + 695, + /* VPBROADCASTBrZ128rk */ + }, + { /* 8945 */ + 696, + /* VPBROADCASTBrZ128rkz */ + }, + { /* 8946 */ + 697, + /* VPBROADCASTBrZ256r */ + }, + { /* 8947 */ + 698, + /* VPBROADCASTBrZ256rk */ + }, + { /* 8948 */ + 699, + /* VPBROADCASTBrZ256rkz */ + }, + { /* 8949 */ + 700, + /* VPBROADCASTBrZr */ + }, + { /* 8950 */ + 701, + /* VPBROADCASTBrZrk */ + }, + { /* 8951 */ + 702, + /* VPBROADCASTBrZrkz */ + }, + { /* 8952 */ + 30, + /* VPBROADCASTBrm */ + }, + { /* 8953 */ + 31, + /* VPBROADCASTBrr */ + }, + { /* 8954 */ + 305, + /* VPBROADCASTDYrm */ + }, + { /* 8955 */ + 333, + /* VPBROADCASTDYrr */ + }, + { /* 8956 */ + 334, + /* VPBROADCASTDZ128m */ + }, + { /* 8957 */ + 335, + /* VPBROADCASTDZ128mk */ + }, + { /* 8958 */ + 336, + /* VPBROADCASTDZ128mkz */ + }, + { /* 8959 */ + 330, + /* VPBROADCASTDZ128r */ + }, + { /* 8960 */ + 331, + /* VPBROADCASTDZ128rk */ + }, + { /* 8961 */ + 332, + /* VPBROADCASTDZ128rkz */ + }, + { /* 8962 */ + 337, + /* VPBROADCASTDZ256m */ + }, + { /* 8963 */ + 338, + /* VPBROADCASTDZ256mk */ + }, + { /* 8964 */ + 339, + /* VPBROADCASTDZ256mkz */ + }, + { /* 8965 */ + 309, + /* VPBROADCASTDZ256r */ + }, + { /* 8966 */ + 310, + /* VPBROADCASTDZ256rk */ + }, + { /* 8967 */ + 311, + /* VPBROADCASTDZ256rkz */ + }, + { /* 8968 */ + 340, + /* VPBROADCASTDZm */ + }, + { /* 8969 */ + 341, + /* VPBROADCASTDZmk */ + }, + { /* 8970 */ + 342, + /* VPBROADCASTDZmkz */ + }, + { /* 8971 */ + 315, + /* VPBROADCASTDZr */ + }, + { /* 8972 */ + 316, + /* VPBROADCASTDZrk */ + }, + { /* 8973 */ + 317, + /* VPBROADCASTDZrkz */ + }, + { /* 8974 */ + 678, + /* VPBROADCASTDrZ128r */ + }, + { /* 8975 */ + 695, + /* VPBROADCASTDrZ128rk */ + }, + { /* 8976 */ + 696, + /* VPBROADCASTDrZ128rkz */ + }, + { /* 8977 */ + 697, + /* VPBROADCASTDrZ256r */ + }, + { /* 8978 */ + 698, + /* VPBROADCASTDrZ256rk */ + }, + { /* 8979 */ + 699, + /* VPBROADCASTDrZ256rkz */ + }, + { /* 8980 */ + 700, + /* VPBROADCASTDrZr */ + }, + { /* 8981 */ + 701, + /* VPBROADCASTDrZrk */ + }, + { /* 8982 */ + 702, + /* VPBROADCASTDrZrkz */ + }, + { /* 8983 */ + 30, + /* VPBROADCASTDrm */ + }, + { /* 8984 */ + 31, + /* VPBROADCASTDrr */ + }, + { /* 8985 */ + 703, + /* VPBROADCASTMB2QZ128rr */ + }, + { /* 8986 */ + 704, + /* VPBROADCASTMB2QZ256rr */ + }, + { /* 8987 */ + 705, + /* VPBROADCASTMB2QZrr */ + }, + { /* 8988 */ + 703, + /* VPBROADCASTMW2DZ128rr */ + }, + { /* 8989 */ + 704, + /* VPBROADCASTMW2DZ256rr */ + }, + { /* 8990 */ + 705, + /* VPBROADCASTMW2DZrr */ + }, + { /* 8991 */ + 305, + /* VPBROADCASTQYrm */ + }, + { /* 8992 */ + 333, + /* VPBROADCASTQYrr */ + }, + { /* 8993 */ + 327, + /* VPBROADCASTQZ128m */ + }, + { /* 8994 */ + 328, + /* VPBROADCASTQZ128mk */ + }, + { /* 8995 */ + 329, + /* VPBROADCASTQZ128mkz */ + }, + { /* 8996 */ + 330, + /* VPBROADCASTQZ128r */ + }, + { /* 8997 */ + 331, + /* VPBROADCASTQZ128rk */ + }, + { /* 8998 */ + 332, + /* VPBROADCASTQZ128rkz */ + }, + { /* 8999 */ + 306, + /* VPBROADCASTQZ256m */ + }, + { /* 9000 */ + 307, + /* VPBROADCASTQZ256mk */ + }, + { /* 9001 */ + 308, + /* VPBROADCASTQZ256mkz */ + }, + { /* 9002 */ + 309, + /* VPBROADCASTQZ256r */ + }, + { /* 9003 */ + 310, + /* VPBROADCASTQZ256rk */ + }, + { /* 9004 */ + 311, + /* VPBROADCASTQZ256rkz */ + }, + { /* 9005 */ + 312, + /* VPBROADCASTQZm */ + }, + { /* 9006 */ + 313, + /* VPBROADCASTQZmk */ + }, + { /* 9007 */ + 314, + /* VPBROADCASTQZmkz */ + }, + { /* 9008 */ + 315, + /* VPBROADCASTQZr */ + }, + { /* 9009 */ + 316, + /* VPBROADCASTQZrk */ + }, + { /* 9010 */ + 317, + /* VPBROADCASTQZrkz */ + }, + { /* 9011 */ + 669, + /* VPBROADCASTQrZ128r */ + }, + { /* 9012 */ + 706, + /* VPBROADCASTQrZ128rk */ + }, + { /* 9013 */ + 707, + /* VPBROADCASTQrZ128rkz */ + }, + { /* 9014 */ + 708, + /* VPBROADCASTQrZ256r */ + }, + { /* 9015 */ + 709, + /* VPBROADCASTQrZ256rk */ + }, + { /* 9016 */ + 710, + /* VPBROADCASTQrZ256rkz */ + }, + { /* 9017 */ + 711, + /* VPBROADCASTQrZr */ + }, + { /* 9018 */ + 712, + /* VPBROADCASTQrZrk */ + }, + { /* 9019 */ + 713, + /* VPBROADCASTQrZrkz */ + }, + { /* 9020 */ + 30, + /* VPBROADCASTQrm */ + }, + { /* 9021 */ + 31, + /* VPBROADCASTQrr */ + }, + { /* 9022 */ + 305, + /* VPBROADCASTWYrm */ + }, + { /* 9023 */ + 333, + /* VPBROADCASTWYrr */ + }, + { /* 9024 */ + 714, + /* VPBROADCASTWZ128m */ + }, + { /* 9025 */ + 715, + /* VPBROADCASTWZ128mk */ + }, + { /* 9026 */ + 716, + /* VPBROADCASTWZ128mkz */ + }, + { /* 9027 */ + 330, + /* VPBROADCASTWZ128r */ + }, + { /* 9028 */ + 331, + /* VPBROADCASTWZ128rk */ + }, + { /* 9029 */ + 332, + /* VPBROADCASTWZ128rkz */ + }, + { /* 9030 */ + 717, + /* VPBROADCASTWZ256m */ + }, + { /* 9031 */ + 718, + /* VPBROADCASTWZ256mk */ + }, + { /* 9032 */ + 719, + /* VPBROADCASTWZ256mkz */ + }, + { /* 9033 */ + 309, + /* VPBROADCASTWZ256r */ + }, + { /* 9034 */ + 310, + /* VPBROADCASTWZ256rk */ + }, + { /* 9035 */ + 311, + /* VPBROADCASTWZ256rkz */ + }, + { /* 9036 */ + 720, + /* VPBROADCASTWZm */ + }, + { /* 9037 */ + 721, + /* VPBROADCASTWZmk */ + }, + { /* 9038 */ + 722, + /* VPBROADCASTWZmkz */ + }, + { /* 9039 */ + 315, + /* VPBROADCASTWZr */ + }, + { /* 9040 */ + 316, + /* VPBROADCASTWZrk */ + }, + { /* 9041 */ + 317, + /* VPBROADCASTWZrkz */ + }, + { /* 9042 */ + 678, + /* VPBROADCASTWrZ128r */ + }, + { /* 9043 */ + 695, + /* VPBROADCASTWrZ128rk */ + }, + { /* 9044 */ + 696, + /* VPBROADCASTWrZ128rkz */ + }, + { /* 9045 */ + 697, + /* VPBROADCASTWrZ256r */ + }, + { /* 9046 */ + 698, + /* VPBROADCASTWrZ256rk */ + }, + { /* 9047 */ + 699, + /* VPBROADCASTWrZ256rkz */ + }, + { /* 9048 */ + 700, + /* VPBROADCASTWrZr */ + }, + { /* 9049 */ + 701, + /* VPBROADCASTWrZrk */ + }, + { /* 9050 */ + 702, + /* VPBROADCASTWrZrkz */ + }, + { /* 9051 */ + 30, + /* VPBROADCASTWrm */ + }, + { /* 9052 */ + 31, + /* VPBROADCASTWrr */ + }, + { /* 9053 */ + 297, + /* VPCLMULQDQYrm */ + }, + { /* 9054 */ + 298, + /* VPCLMULQDQYrr */ + }, + { /* 9055 */ + 264, + /* VPCLMULQDQZ128rm */ + }, + { /* 9056 */ + 267, + /* VPCLMULQDQZ128rr */ + }, + { /* 9057 */ + 273, + /* VPCLMULQDQZ256rm */ + }, + { /* 9058 */ + 276, + /* VPCLMULQDQZ256rr */ + }, + { /* 9059 */ + 282, + /* VPCLMULQDQZrm */ + }, + { /* 9060 */ + 285, + /* VPCLMULQDQZrr */ + }, + { /* 9061 */ + 299, + /* VPCLMULQDQrm */ + }, + { /* 9062 */ + 300, + /* VPCLMULQDQrr */ + }, + { /* 9063 */ + 301, + /* VPCMOVYrmr */ + }, + { /* 9064 */ + 548, + /* VPCMOVYrrm */ + }, + { /* 9065 */ + 302, + /* VPCMOVYrrr */ + }, + { /* 9066 */ + 549, + /* VPCMOVYrrr_REV */ + }, + { /* 9067 */ + 303, + /* VPCMOVrmr */ + }, + { /* 9068 */ + 550, + /* VPCMOVrrm */ + }, + { /* 9069 */ + 304, + /* VPCMOVrrr */ + }, + { /* 9070 */ + 551, + /* VPCMOVrrr_REV */ + }, + { /* 9071 */ + 723, + /* VPCMPBZ128rmi */ + }, + { /* 9072 */ + 0, + /* */ + }, + { /* 9073 */ + 724, + /* VPCMPBZ128rmik */ + }, + { /* 9074 */ + 0, + /* */ + }, + { /* 9075 */ + 725, + /* VPCMPBZ128rri */ + }, + { /* 9076 */ + 0, + /* */ + }, + { /* 9077 */ + 726, + /* VPCMPBZ128rrik */ + }, + { /* 9078 */ + 0, + /* */ + }, + { /* 9079 */ + 727, + /* VPCMPBZ256rmi */ + }, + { /* 9080 */ + 0, + /* */ + }, + { /* 9081 */ + 728, + /* VPCMPBZ256rmik */ + }, + { /* 9082 */ + 0, + /* */ + }, + { /* 9083 */ + 729, + /* VPCMPBZ256rri */ + }, + { /* 9084 */ + 0, + /* */ + }, + { /* 9085 */ + 730, + /* VPCMPBZ256rrik */ + }, + { /* 9086 */ + 0, + /* */ + }, + { /* 9087 */ + 731, + /* VPCMPBZrmi */ + }, + { /* 9088 */ + 0, + /* */ + }, + { /* 9089 */ + 732, + /* VPCMPBZrmik */ + }, + { /* 9090 */ + 0, + /* */ + }, + { /* 9091 */ + 733, + /* VPCMPBZrri */ + }, + { /* 9092 */ + 0, + /* */ + }, + { /* 9093 */ + 734, + /* VPCMPBZrrik */ + }, + { /* 9094 */ + 0, + /* */ + }, + { /* 9095 */ + 723, + /* VPCMPDZ128rmi */ + }, + { /* 9096 */ + 0, + /* */ + }, + { /* 9097 */ + 735, + /* VPCMPDZ128rmib */ + }, + { /* 9098 */ + 0, + /* */ + }, + { /* 9099 */ + 736, + /* VPCMPDZ128rmibk */ + }, + { /* 9100 */ + 0, + /* */ + }, + { /* 9101 */ + 724, + /* VPCMPDZ128rmik */ + }, + { /* 9102 */ + 0, + /* */ + }, + { /* 9103 */ + 725, + /* VPCMPDZ128rri */ + }, + { /* 9104 */ + 0, + /* */ + }, + { /* 9105 */ + 726, + /* VPCMPDZ128rrik */ + }, + { /* 9106 */ + 0, + /* */ + }, + { /* 9107 */ + 727, + /* VPCMPDZ256rmi */ + }, + { /* 9108 */ + 0, + /* */ + }, + { /* 9109 */ + 737, + /* VPCMPDZ256rmib */ + }, + { /* 9110 */ + 0, + /* */ + }, + { /* 9111 */ + 738, + /* VPCMPDZ256rmibk */ + }, + { /* 9112 */ + 0, + /* */ + }, + { /* 9113 */ + 728, + /* VPCMPDZ256rmik */ + }, + { /* 9114 */ + 0, + /* */ + }, + { /* 9115 */ + 729, + /* VPCMPDZ256rri */ + }, + { /* 9116 */ + 0, + /* */ + }, + { /* 9117 */ + 730, + /* VPCMPDZ256rrik */ + }, + { /* 9118 */ + 0, + /* */ + }, + { /* 9119 */ + 731, + /* VPCMPDZrmi */ + }, + { /* 9120 */ + 0, + /* */ + }, + { /* 9121 */ + 739, + /* VPCMPDZrmib */ + }, + { /* 9122 */ + 0, + /* */ + }, + { /* 9123 */ + 740, + /* VPCMPDZrmibk */ + }, + { /* 9124 */ + 0, + /* */ + }, + { /* 9125 */ + 732, + /* VPCMPDZrmik */ + }, + { /* 9126 */ + 0, + /* */ + }, + { /* 9127 */ + 733, + /* VPCMPDZrri */ + }, + { /* 9128 */ + 0, + /* */ + }, + { /* 9129 */ + 734, + /* VPCMPDZrrik */ + }, + { /* 9130 */ + 0, + /* */ + }, + { /* 9131 */ + 204, + /* VPCMPEQBYrm */ + }, + { /* 9132 */ + 205, + /* VPCMPEQBYrr */ + }, + { /* 9133 */ + 741, + /* VPCMPEQBZ128rm */ + }, + { /* 9134 */ + 742, + /* VPCMPEQBZ128rmk */ + }, + { /* 9135 */ + 743, + /* VPCMPEQBZ128rr */ + }, + { /* 9136 */ + 744, + /* VPCMPEQBZ128rrk */ + }, + { /* 9137 */ + 745, + /* VPCMPEQBZ256rm */ + }, + { /* 9138 */ + 746, + /* VPCMPEQBZ256rmk */ + }, + { /* 9139 */ + 747, + /* VPCMPEQBZ256rr */ + }, + { /* 9140 */ + 748, + /* VPCMPEQBZ256rrk */ + }, + { /* 9141 */ + 749, + /* VPCMPEQBZrm */ + }, + { /* 9142 */ + 750, + /* VPCMPEQBZrmk */ + }, + { /* 9143 */ + 751, + /* VPCMPEQBZrr */ + }, + { /* 9144 */ + 752, + /* VPCMPEQBZrrk */ + }, + { /* 9145 */ + 235, + /* VPCMPEQBrm */ + }, + { /* 9146 */ + 236, + /* VPCMPEQBrr */ + }, + { /* 9147 */ + 204, + /* VPCMPEQDYrm */ + }, + { /* 9148 */ + 205, + /* VPCMPEQDYrr */ + }, + { /* 9149 */ + 741, + /* VPCMPEQDZ128rm */ + }, + { /* 9150 */ + 753, + /* VPCMPEQDZ128rmb */ + }, + { /* 9151 */ + 754, + /* VPCMPEQDZ128rmbk */ + }, + { /* 9152 */ + 742, + /* VPCMPEQDZ128rmk */ + }, + { /* 9153 */ + 743, + /* VPCMPEQDZ128rr */ + }, + { /* 9154 */ + 744, + /* VPCMPEQDZ128rrk */ + }, + { /* 9155 */ + 745, + /* VPCMPEQDZ256rm */ + }, + { /* 9156 */ + 755, + /* VPCMPEQDZ256rmb */ + }, + { /* 9157 */ + 756, + /* VPCMPEQDZ256rmbk */ + }, + { /* 9158 */ + 746, + /* VPCMPEQDZ256rmk */ + }, + { /* 9159 */ + 747, + /* VPCMPEQDZ256rr */ + }, + { /* 9160 */ + 748, + /* VPCMPEQDZ256rrk */ + }, + { /* 9161 */ + 749, + /* VPCMPEQDZrm */ + }, + { /* 9162 */ + 757, + /* VPCMPEQDZrmb */ + }, + { /* 9163 */ + 758, + /* VPCMPEQDZrmbk */ + }, + { /* 9164 */ + 750, + /* VPCMPEQDZrmk */ + }, + { /* 9165 */ + 751, + /* VPCMPEQDZrr */ + }, + { /* 9166 */ + 752, + /* VPCMPEQDZrrk */ + }, + { /* 9167 */ + 235, + /* VPCMPEQDrm */ + }, + { /* 9168 */ + 236, + /* VPCMPEQDrr */ + }, + { /* 9169 */ + 204, + /* VPCMPEQQYrm */ + }, + { /* 9170 */ + 205, + /* VPCMPEQQYrr */ + }, + { /* 9171 */ + 741, + /* VPCMPEQQZ128rm */ + }, + { /* 9172 */ + 759, + /* VPCMPEQQZ128rmb */ + }, + { /* 9173 */ + 760, + /* VPCMPEQQZ128rmbk */ + }, + { /* 9174 */ + 742, + /* VPCMPEQQZ128rmk */ + }, + { /* 9175 */ + 743, + /* VPCMPEQQZ128rr */ + }, + { /* 9176 */ + 744, + /* VPCMPEQQZ128rrk */ + }, + { /* 9177 */ + 745, + /* VPCMPEQQZ256rm */ + }, + { /* 9178 */ + 761, + /* VPCMPEQQZ256rmb */ + }, + { /* 9179 */ + 762, + /* VPCMPEQQZ256rmbk */ + }, + { /* 9180 */ + 746, + /* VPCMPEQQZ256rmk */ + }, + { /* 9181 */ + 747, + /* VPCMPEQQZ256rr */ + }, + { /* 9182 */ + 748, + /* VPCMPEQQZ256rrk */ + }, + { /* 9183 */ + 749, + /* VPCMPEQQZrm */ + }, + { /* 9184 */ + 763, + /* VPCMPEQQZrmb */ + }, + { /* 9185 */ + 764, + /* VPCMPEQQZrmbk */ + }, + { /* 9186 */ + 750, + /* VPCMPEQQZrmk */ + }, + { /* 9187 */ + 751, + /* VPCMPEQQZrr */ + }, + { /* 9188 */ + 752, + /* VPCMPEQQZrrk */ + }, + { /* 9189 */ + 235, + /* VPCMPEQQrm */ + }, + { /* 9190 */ + 236, + /* VPCMPEQQrr */ + }, + { /* 9191 */ + 204, + /* VPCMPEQWYrm */ + }, + { /* 9192 */ + 205, + /* VPCMPEQWYrr */ + }, + { /* 9193 */ + 741, + /* VPCMPEQWZ128rm */ + }, + { /* 9194 */ + 742, + /* VPCMPEQWZ128rmk */ + }, + { /* 9195 */ + 743, + /* VPCMPEQWZ128rr */ + }, + { /* 9196 */ + 744, + /* VPCMPEQWZ128rrk */ + }, + { /* 9197 */ + 745, + /* VPCMPEQWZ256rm */ + }, + { /* 9198 */ + 746, + /* VPCMPEQWZ256rmk */ + }, + { /* 9199 */ + 747, + /* VPCMPEQWZ256rr */ + }, + { /* 9200 */ + 748, + /* VPCMPEQWZ256rrk */ + }, + { /* 9201 */ + 749, + /* VPCMPEQWZrm */ + }, + { /* 9202 */ + 750, + /* VPCMPEQWZrmk */ + }, + { /* 9203 */ + 751, + /* VPCMPEQWZrr */ + }, + { /* 9204 */ + 752, + /* VPCMPEQWZrrk */ + }, + { /* 9205 */ + 235, + /* VPCMPEQWrm */ + }, + { /* 9206 */ + 236, + /* VPCMPEQWrr */ + }, + { /* 9207 */ + 32, + /* VPCMPESTRIrm */ + }, + { /* 9208 */ + 33, + /* VPCMPESTRIrr */ + }, + { /* 9209 */ + 32, + /* VPCMPESTRMrm */ + }, + { /* 9210 */ + 33, + /* VPCMPESTRMrr */ + }, + { /* 9211 */ + 204, + /* VPCMPGTBYrm */ + }, + { /* 9212 */ + 205, + /* VPCMPGTBYrr */ + }, + { /* 9213 */ + 741, + /* VPCMPGTBZ128rm */ + }, + { /* 9214 */ + 742, + /* VPCMPGTBZ128rmk */ + }, + { /* 9215 */ + 743, + /* VPCMPGTBZ128rr */ + }, + { /* 9216 */ + 744, + /* VPCMPGTBZ128rrk */ + }, + { /* 9217 */ + 745, + /* VPCMPGTBZ256rm */ + }, + { /* 9218 */ + 746, + /* VPCMPGTBZ256rmk */ + }, + { /* 9219 */ + 747, + /* VPCMPGTBZ256rr */ + }, + { /* 9220 */ + 748, + /* VPCMPGTBZ256rrk */ + }, + { /* 9221 */ + 749, + /* VPCMPGTBZrm */ + }, + { /* 9222 */ + 750, + /* VPCMPGTBZrmk */ + }, + { /* 9223 */ + 751, + /* VPCMPGTBZrr */ + }, + { /* 9224 */ + 752, + /* VPCMPGTBZrrk */ + }, + { /* 9225 */ + 235, + /* VPCMPGTBrm */ + }, + { /* 9226 */ + 236, + /* VPCMPGTBrr */ + }, + { /* 9227 */ + 204, + /* VPCMPGTDYrm */ + }, + { /* 9228 */ + 205, + /* VPCMPGTDYrr */ + }, + { /* 9229 */ + 741, + /* VPCMPGTDZ128rm */ + }, + { /* 9230 */ + 753, + /* VPCMPGTDZ128rmb */ + }, + { /* 9231 */ + 754, + /* VPCMPGTDZ128rmbk */ + }, + { /* 9232 */ + 742, + /* VPCMPGTDZ128rmk */ + }, + { /* 9233 */ + 743, + /* VPCMPGTDZ128rr */ + }, + { /* 9234 */ + 744, + /* VPCMPGTDZ128rrk */ + }, + { /* 9235 */ + 745, + /* VPCMPGTDZ256rm */ + }, + { /* 9236 */ + 755, + /* VPCMPGTDZ256rmb */ + }, + { /* 9237 */ + 756, + /* VPCMPGTDZ256rmbk */ + }, + { /* 9238 */ + 746, + /* VPCMPGTDZ256rmk */ + }, + { /* 9239 */ + 747, + /* VPCMPGTDZ256rr */ + }, + { /* 9240 */ + 748, + /* VPCMPGTDZ256rrk */ + }, + { /* 9241 */ + 749, + /* VPCMPGTDZrm */ + }, + { /* 9242 */ + 757, + /* VPCMPGTDZrmb */ + }, + { /* 9243 */ + 758, + /* VPCMPGTDZrmbk */ + }, + { /* 9244 */ + 750, + /* VPCMPGTDZrmk */ + }, + { /* 9245 */ + 751, + /* VPCMPGTDZrr */ + }, + { /* 9246 */ + 752, + /* VPCMPGTDZrrk */ + }, + { /* 9247 */ + 235, + /* VPCMPGTDrm */ + }, + { /* 9248 */ + 236, + /* VPCMPGTDrr */ + }, + { /* 9249 */ + 204, + /* VPCMPGTQYrm */ + }, + { /* 9250 */ + 205, + /* VPCMPGTQYrr */ + }, + { /* 9251 */ + 741, + /* VPCMPGTQZ128rm */ + }, + { /* 9252 */ + 759, + /* VPCMPGTQZ128rmb */ + }, + { /* 9253 */ + 760, + /* VPCMPGTQZ128rmbk */ + }, + { /* 9254 */ + 742, + /* VPCMPGTQZ128rmk */ + }, + { /* 9255 */ + 743, + /* VPCMPGTQZ128rr */ + }, + { /* 9256 */ + 744, + /* VPCMPGTQZ128rrk */ + }, + { /* 9257 */ + 745, + /* VPCMPGTQZ256rm */ + }, + { /* 9258 */ + 761, + /* VPCMPGTQZ256rmb */ + }, + { /* 9259 */ + 762, + /* VPCMPGTQZ256rmbk */ + }, + { /* 9260 */ + 746, + /* VPCMPGTQZ256rmk */ + }, + { /* 9261 */ + 747, + /* VPCMPGTQZ256rr */ + }, + { /* 9262 */ + 748, + /* VPCMPGTQZ256rrk */ + }, + { /* 9263 */ + 749, + /* VPCMPGTQZrm */ + }, + { /* 9264 */ + 763, + /* VPCMPGTQZrmb */ + }, + { /* 9265 */ + 764, + /* VPCMPGTQZrmbk */ + }, + { /* 9266 */ + 750, + /* VPCMPGTQZrmk */ + }, + { /* 9267 */ + 751, + /* VPCMPGTQZrr */ + }, + { /* 9268 */ + 752, + /* VPCMPGTQZrrk */ + }, + { /* 9269 */ + 235, + /* VPCMPGTQrm */ + }, + { /* 9270 */ + 236, + /* VPCMPGTQrr */ + }, + { /* 9271 */ + 204, + /* VPCMPGTWYrm */ + }, + { /* 9272 */ + 205, + /* VPCMPGTWYrr */ + }, + { /* 9273 */ + 741, + /* VPCMPGTWZ128rm */ + }, + { /* 9274 */ + 742, + /* VPCMPGTWZ128rmk */ + }, + { /* 9275 */ + 743, + /* VPCMPGTWZ128rr */ + }, + { /* 9276 */ + 744, + /* VPCMPGTWZ128rrk */ + }, + { /* 9277 */ + 745, + /* VPCMPGTWZ256rm */ + }, + { /* 9278 */ + 746, + /* VPCMPGTWZ256rmk */ + }, + { /* 9279 */ + 747, + /* VPCMPGTWZ256rr */ + }, + { /* 9280 */ + 748, + /* VPCMPGTWZ256rrk */ + }, + { /* 9281 */ + 749, + /* VPCMPGTWZrm */ + }, + { /* 9282 */ + 750, + /* VPCMPGTWZrmk */ + }, + { /* 9283 */ + 751, + /* VPCMPGTWZrr */ + }, + { /* 9284 */ + 752, + /* VPCMPGTWZrrk */ + }, + { /* 9285 */ + 235, + /* VPCMPGTWrm */ + }, + { /* 9286 */ + 236, + /* VPCMPGTWrr */ + }, + { /* 9287 */ + 32, + /* VPCMPISTRIrm */ + }, + { /* 9288 */ + 33, + /* VPCMPISTRIrr */ + }, + { /* 9289 */ + 32, + /* VPCMPISTRMrm */ + }, + { /* 9290 */ + 33, + /* VPCMPISTRMrr */ + }, + { /* 9291 */ + 723, + /* VPCMPQZ128rmi */ + }, + { /* 9292 */ + 0, + /* */ + }, + { /* 9293 */ + 765, + /* VPCMPQZ128rmib */ + }, + { /* 9294 */ + 0, + /* */ + }, + { /* 9295 */ + 766, + /* VPCMPQZ128rmibk */ + }, + { /* 9296 */ + 0, + /* */ + }, + { /* 9297 */ + 724, + /* VPCMPQZ128rmik */ + }, + { /* 9298 */ + 0, + /* */ + }, + { /* 9299 */ + 725, + /* VPCMPQZ128rri */ + }, + { /* 9300 */ + 0, + /* */ + }, + { /* 9301 */ + 726, + /* VPCMPQZ128rrik */ + }, + { /* 9302 */ + 0, + /* */ + }, + { /* 9303 */ + 727, + /* VPCMPQZ256rmi */ + }, + { /* 9304 */ + 0, + /* */ + }, + { /* 9305 */ + 767, + /* VPCMPQZ256rmib */ + }, + { /* 9306 */ + 0, + /* */ + }, + { /* 9307 */ + 768, + /* VPCMPQZ256rmibk */ + }, + { /* 9308 */ + 0, + /* */ + }, + { /* 9309 */ + 728, + /* VPCMPQZ256rmik */ + }, + { /* 9310 */ + 0, + /* */ + }, + { /* 9311 */ + 729, + /* VPCMPQZ256rri */ + }, + { /* 9312 */ + 0, + /* */ + }, + { /* 9313 */ + 730, + /* VPCMPQZ256rrik */ + }, + { /* 9314 */ + 0, + /* */ + }, + { /* 9315 */ + 731, + /* VPCMPQZrmi */ + }, + { /* 9316 */ + 0, + /* */ + }, + { /* 9317 */ + 769, + /* VPCMPQZrmib */ + }, + { /* 9318 */ + 0, + /* */ + }, + { /* 9319 */ + 770, + /* VPCMPQZrmibk */ + }, + { /* 9320 */ + 0, + /* */ + }, + { /* 9321 */ + 732, + /* VPCMPQZrmik */ + }, + { /* 9322 */ + 0, + /* */ + }, + { /* 9323 */ + 733, + /* VPCMPQZrri */ + }, + { /* 9324 */ + 0, + /* */ + }, + { /* 9325 */ + 734, + /* VPCMPQZrrik */ + }, + { /* 9326 */ + 0, + /* */ + }, + { /* 9327 */ + 723, + /* VPCMPUBZ128rmi */ + }, + { /* 9328 */ + 0, + /* */ + }, + { /* 9329 */ + 724, + /* VPCMPUBZ128rmik */ + }, + { /* 9330 */ + 0, + /* */ + }, + { /* 9331 */ + 725, + /* VPCMPUBZ128rri */ + }, + { /* 9332 */ + 0, + /* */ + }, + { /* 9333 */ + 726, + /* VPCMPUBZ128rrik */ + }, + { /* 9334 */ + 0, + /* */ + }, + { /* 9335 */ + 727, + /* VPCMPUBZ256rmi */ + }, + { /* 9336 */ + 0, + /* */ + }, + { /* 9337 */ + 728, + /* VPCMPUBZ256rmik */ + }, + { /* 9338 */ + 0, + /* */ + }, + { /* 9339 */ + 729, + /* VPCMPUBZ256rri */ + }, + { /* 9340 */ + 0, + /* */ + }, + { /* 9341 */ + 730, + /* VPCMPUBZ256rrik */ + }, + { /* 9342 */ + 0, + /* */ + }, + { /* 9343 */ + 731, + /* VPCMPUBZrmi */ + }, + { /* 9344 */ + 0, + /* */ + }, + { /* 9345 */ + 732, + /* VPCMPUBZrmik */ + }, + { /* 9346 */ + 0, + /* */ + }, + { /* 9347 */ + 733, + /* VPCMPUBZrri */ + }, + { /* 9348 */ + 0, + /* */ + }, + { /* 9349 */ + 734, + /* VPCMPUBZrrik */ + }, + { /* 9350 */ + 0, + /* */ + }, + { /* 9351 */ + 723, + /* VPCMPUDZ128rmi */ + }, + { /* 9352 */ + 0, + /* */ + }, + { /* 9353 */ + 735, + /* VPCMPUDZ128rmib */ + }, + { /* 9354 */ + 0, + /* */ + }, + { /* 9355 */ + 736, + /* VPCMPUDZ128rmibk */ + }, + { /* 9356 */ + 0, + /* */ + }, + { /* 9357 */ + 724, + /* VPCMPUDZ128rmik */ + }, + { /* 9358 */ + 0, + /* */ + }, + { /* 9359 */ + 725, + /* VPCMPUDZ128rri */ + }, + { /* 9360 */ + 0, + /* */ + }, + { /* 9361 */ + 726, + /* VPCMPUDZ128rrik */ + }, + { /* 9362 */ + 0, + /* */ + }, + { /* 9363 */ + 727, + /* VPCMPUDZ256rmi */ + }, + { /* 9364 */ + 0, + /* */ + }, + { /* 9365 */ + 737, + /* VPCMPUDZ256rmib */ + }, + { /* 9366 */ + 0, + /* */ + }, + { /* 9367 */ + 738, + /* VPCMPUDZ256rmibk */ + }, + { /* 9368 */ + 0, + /* */ + }, + { /* 9369 */ + 728, + /* VPCMPUDZ256rmik */ + }, + { /* 9370 */ + 0, + /* */ + }, + { /* 9371 */ + 729, + /* VPCMPUDZ256rri */ + }, + { /* 9372 */ + 0, + /* */ + }, + { /* 9373 */ + 730, + /* VPCMPUDZ256rrik */ + }, + { /* 9374 */ + 0, + /* */ + }, + { /* 9375 */ + 731, + /* VPCMPUDZrmi */ + }, + { /* 9376 */ + 0, + /* */ + }, + { /* 9377 */ + 739, + /* VPCMPUDZrmib */ + }, + { /* 9378 */ + 0, + /* */ + }, + { /* 9379 */ + 740, + /* VPCMPUDZrmibk */ + }, + { /* 9380 */ + 0, + /* */ + }, + { /* 9381 */ + 732, + /* VPCMPUDZrmik */ + }, + { /* 9382 */ + 0, + /* */ + }, + { /* 9383 */ + 733, + /* VPCMPUDZrri */ + }, + { /* 9384 */ + 0, + /* */ + }, + { /* 9385 */ + 734, + /* VPCMPUDZrrik */ + }, + { /* 9386 */ + 0, + /* */ + }, + { /* 9387 */ + 723, + /* VPCMPUQZ128rmi */ + }, + { /* 9388 */ + 0, + /* */ + }, + { /* 9389 */ + 765, + /* VPCMPUQZ128rmib */ + }, + { /* 9390 */ + 0, + /* */ + }, + { /* 9391 */ + 766, + /* VPCMPUQZ128rmibk */ + }, + { /* 9392 */ + 0, + /* */ + }, + { /* 9393 */ + 724, + /* VPCMPUQZ128rmik */ + }, + { /* 9394 */ + 0, + /* */ + }, + { /* 9395 */ + 725, + /* VPCMPUQZ128rri */ + }, + { /* 9396 */ + 0, + /* */ + }, + { /* 9397 */ + 726, + /* VPCMPUQZ128rrik */ + }, + { /* 9398 */ + 0, + /* */ + }, + { /* 9399 */ + 727, + /* VPCMPUQZ256rmi */ + }, + { /* 9400 */ + 0, + /* */ + }, + { /* 9401 */ + 767, + /* VPCMPUQZ256rmib */ + }, + { /* 9402 */ + 0, + /* */ + }, + { /* 9403 */ + 768, + /* VPCMPUQZ256rmibk */ + }, + { /* 9404 */ + 0, + /* */ + }, + { /* 9405 */ + 728, + /* VPCMPUQZ256rmik */ + }, + { /* 9406 */ + 0, + /* */ + }, + { /* 9407 */ + 729, + /* VPCMPUQZ256rri */ + }, + { /* 9408 */ + 0, + /* */ + }, + { /* 9409 */ + 730, + /* VPCMPUQZ256rrik */ + }, + { /* 9410 */ + 0, + /* */ + }, + { /* 9411 */ + 731, + /* VPCMPUQZrmi */ + }, + { /* 9412 */ + 0, + /* */ + }, + { /* 9413 */ + 769, + /* VPCMPUQZrmib */ + }, + { /* 9414 */ + 0, + /* */ + }, + { /* 9415 */ + 770, + /* VPCMPUQZrmibk */ + }, + { /* 9416 */ + 0, + /* */ + }, + { /* 9417 */ + 732, + /* VPCMPUQZrmik */ + }, + { /* 9418 */ + 0, + /* */ + }, + { /* 9419 */ + 733, + /* VPCMPUQZrri */ + }, + { /* 9420 */ + 0, + /* */ + }, + { /* 9421 */ + 734, + /* VPCMPUQZrrik */ + }, + { /* 9422 */ + 0, + /* */ + }, + { /* 9423 */ + 723, + /* VPCMPUWZ128rmi */ + }, + { /* 9424 */ + 0, + /* */ + }, + { /* 9425 */ + 724, + /* VPCMPUWZ128rmik */ + }, + { /* 9426 */ + 0, + /* */ + }, + { /* 9427 */ + 725, + /* VPCMPUWZ128rri */ + }, + { /* 9428 */ + 0, + /* */ + }, + { /* 9429 */ + 726, + /* VPCMPUWZ128rrik */ + }, + { /* 9430 */ + 0, + /* */ + }, + { /* 9431 */ + 727, + /* VPCMPUWZ256rmi */ + }, + { /* 9432 */ + 0, + /* */ + }, + { /* 9433 */ + 728, + /* VPCMPUWZ256rmik */ + }, + { /* 9434 */ + 0, + /* */ + }, + { /* 9435 */ + 729, + /* VPCMPUWZ256rri */ + }, + { /* 9436 */ + 0, + /* */ + }, + { /* 9437 */ + 730, + /* VPCMPUWZ256rrik */ + }, + { /* 9438 */ + 0, + /* */ + }, + { /* 9439 */ + 731, + /* VPCMPUWZrmi */ + }, + { /* 9440 */ + 0, + /* */ + }, + { /* 9441 */ + 732, + /* VPCMPUWZrmik */ + }, + { /* 9442 */ + 0, + /* */ + }, + { /* 9443 */ + 733, + /* VPCMPUWZrri */ + }, + { /* 9444 */ + 0, + /* */ + }, + { /* 9445 */ + 734, + /* VPCMPUWZrrik */ + }, + { /* 9446 */ + 0, + /* */ + }, + { /* 9447 */ + 723, + /* VPCMPWZ128rmi */ + }, + { /* 9448 */ + 0, + /* */ + }, + { /* 9449 */ + 724, + /* VPCMPWZ128rmik */ + }, + { /* 9450 */ + 0, + /* */ + }, + { /* 9451 */ + 725, + /* VPCMPWZ128rri */ + }, + { /* 9452 */ + 0, + /* */ + }, + { /* 9453 */ + 726, + /* VPCMPWZ128rrik */ + }, + { /* 9454 */ + 0, + /* */ + }, + { /* 9455 */ + 727, + /* VPCMPWZ256rmi */ + }, + { /* 9456 */ + 0, + /* */ + }, + { /* 9457 */ + 728, + /* VPCMPWZ256rmik */ + }, + { /* 9458 */ + 0, + /* */ + }, + { /* 9459 */ + 729, + /* VPCMPWZ256rri */ + }, + { /* 9460 */ + 0, + /* */ + }, + { /* 9461 */ + 730, + /* VPCMPWZ256rrik */ + }, + { /* 9462 */ + 0, + /* */ + }, + { /* 9463 */ + 731, + /* VPCMPWZrmi */ + }, + { /* 9464 */ + 0, + /* */ + }, + { /* 9465 */ + 732, + /* VPCMPWZrmik */ + }, + { /* 9466 */ + 0, + /* */ + }, + { /* 9467 */ + 733, + /* VPCMPWZrri */ + }, + { /* 9468 */ + 0, + /* */ + }, + { /* 9469 */ + 734, + /* VPCMPWZrrik */ + }, + { /* 9470 */ + 0, + /* */ + }, + { /* 9471 */ + 771, + /* VPCOMBmi */ + }, + { /* 9472 */ + 0, + /* */ + }, + { /* 9473 */ + 772, + /* VPCOMBri */ + }, + { /* 9474 */ + 0, + /* */ + }, + { /* 9475 */ + 771, + /* VPCOMDmi */ + }, + { /* 9476 */ + 0, + /* */ + }, + { /* 9477 */ + 772, + /* VPCOMDri */ + }, + { /* 9478 */ + 0, + /* */ + }, + { /* 9479 */ + 169, + /* VPCOMPRESSBZ128mr */ + }, + { /* 9480 */ + 773, + /* VPCOMPRESSBZ128mrk */ + }, + { /* 9481 */ + 381, + /* VPCOMPRESSBZ128rr */ + }, + { /* 9482 */ + 382, + /* VPCOMPRESSBZ128rrk */ + }, + { /* 9483 */ + 383, + /* VPCOMPRESSBZ128rrkz */ + }, + { /* 9484 */ + 670, + /* VPCOMPRESSBZ256mr */ + }, + { /* 9485 */ + 774, + /* VPCOMPRESSBZ256mrk */ + }, + { /* 9486 */ + 386, + /* VPCOMPRESSBZ256rr */ + }, + { /* 9487 */ + 387, + /* VPCOMPRESSBZ256rrk */ + }, + { /* 9488 */ + 388, + /* VPCOMPRESSBZ256rrkz */ + }, + { /* 9489 */ + 775, + /* VPCOMPRESSBZmr */ + }, + { /* 9490 */ + 776, + /* VPCOMPRESSBZmrk */ + }, + { /* 9491 */ + 391, + /* VPCOMPRESSBZrr */ + }, + { /* 9492 */ + 392, + /* VPCOMPRESSBZrrk */ + }, + { /* 9493 */ + 393, + /* VPCOMPRESSBZrrkz */ + }, + { /* 9494 */ + 394, + /* VPCOMPRESSDZ128mr */ + }, + { /* 9495 */ + 395, + /* VPCOMPRESSDZ128mrk */ + }, + { /* 9496 */ + 381, + /* VPCOMPRESSDZ128rr */ + }, + { /* 9497 */ + 382, + /* VPCOMPRESSDZ128rrk */ + }, + { /* 9498 */ + 383, + /* VPCOMPRESSDZ128rrkz */ + }, + { /* 9499 */ + 396, + /* VPCOMPRESSDZ256mr */ + }, + { /* 9500 */ + 397, + /* VPCOMPRESSDZ256mrk */ + }, + { /* 9501 */ + 386, + /* VPCOMPRESSDZ256rr */ + }, + { /* 9502 */ + 387, + /* VPCOMPRESSDZ256rrk */ + }, + { /* 9503 */ + 388, + /* VPCOMPRESSDZ256rrkz */ + }, + { /* 9504 */ + 398, + /* VPCOMPRESSDZmr */ + }, + { /* 9505 */ + 399, + /* VPCOMPRESSDZmrk */ + }, + { /* 9506 */ + 391, + /* VPCOMPRESSDZrr */ + }, + { /* 9507 */ + 392, + /* VPCOMPRESSDZrrk */ + }, + { /* 9508 */ + 393, + /* VPCOMPRESSDZrrkz */ + }, + { /* 9509 */ + 379, + /* VPCOMPRESSQZ128mr */ + }, + { /* 9510 */ + 380, + /* VPCOMPRESSQZ128mrk */ + }, + { /* 9511 */ + 381, + /* VPCOMPRESSQZ128rr */ + }, + { /* 9512 */ + 382, + /* VPCOMPRESSQZ128rrk */ + }, + { /* 9513 */ + 383, + /* VPCOMPRESSQZ128rrkz */ + }, + { /* 9514 */ + 384, + /* VPCOMPRESSQZ256mr */ + }, + { /* 9515 */ + 385, + /* VPCOMPRESSQZ256mrk */ + }, + { /* 9516 */ + 386, + /* VPCOMPRESSQZ256rr */ + }, + { /* 9517 */ + 387, + /* VPCOMPRESSQZ256rrk */ + }, + { /* 9518 */ + 388, + /* VPCOMPRESSQZ256rrkz */ + }, + { /* 9519 */ + 389, + /* VPCOMPRESSQZmr */ + }, + { /* 9520 */ + 390, + /* VPCOMPRESSQZmrk */ + }, + { /* 9521 */ + 391, + /* VPCOMPRESSQZrr */ + }, + { /* 9522 */ + 392, + /* VPCOMPRESSQZrrk */ + }, + { /* 9523 */ + 393, + /* VPCOMPRESSQZrrkz */ + }, + { /* 9524 */ + 777, + /* VPCOMPRESSWZ128mr */ + }, + { /* 9525 */ + 778, + /* VPCOMPRESSWZ128mrk */ + }, + { /* 9526 */ + 381, + /* VPCOMPRESSWZ128rr */ + }, + { /* 9527 */ + 382, + /* VPCOMPRESSWZ128rrk */ + }, + { /* 9528 */ + 383, + /* VPCOMPRESSWZ128rrkz */ + }, + { /* 9529 */ + 779, + /* VPCOMPRESSWZ256mr */ + }, + { /* 9530 */ + 780, + /* VPCOMPRESSWZ256mrk */ + }, + { /* 9531 */ + 386, + /* VPCOMPRESSWZ256rr */ + }, + { /* 9532 */ + 387, + /* VPCOMPRESSWZ256rrk */ + }, + { /* 9533 */ + 388, + /* VPCOMPRESSWZ256rrkz */ + }, + { /* 9534 */ + 781, + /* VPCOMPRESSWZmr */ + }, + { /* 9535 */ + 782, + /* VPCOMPRESSWZmrk */ + }, + { /* 9536 */ + 391, + /* VPCOMPRESSWZrr */ + }, + { /* 9537 */ + 392, + /* VPCOMPRESSWZrrk */ + }, + { /* 9538 */ + 393, + /* VPCOMPRESSWZrrkz */ + }, + { /* 9539 */ + 771, + /* VPCOMQmi */ + }, + { /* 9540 */ + 0, + /* */ + }, + { /* 9541 */ + 772, + /* VPCOMQri */ + }, + { /* 9542 */ + 0, + /* */ + }, + { /* 9543 */ + 771, + /* VPCOMUBmi */ + }, + { /* 9544 */ + 0, + /* */ + }, + { /* 9545 */ + 772, + /* VPCOMUBri */ + }, + { /* 9546 */ + 0, + /* */ + }, + { /* 9547 */ + 771, + /* VPCOMUDmi */ + }, + { /* 9548 */ + 0, + /* */ + }, + { /* 9549 */ + 772, + /* VPCOMUDri */ + }, + { /* 9550 */ + 0, + /* */ + }, + { /* 9551 */ + 771, + /* VPCOMUQmi */ + }, + { /* 9552 */ + 0, + /* */ + }, + { /* 9553 */ + 772, + /* VPCOMUQri */ + }, + { /* 9554 */ + 0, + /* */ + }, + { /* 9555 */ + 771, + /* VPCOMUWmi */ + }, + { /* 9556 */ + 0, + /* */ + }, + { /* 9557 */ + 772, + /* VPCOMUWri */ + }, + { /* 9558 */ + 0, + /* */ + }, + { /* 9559 */ + 771, + /* VPCOMWmi */ + }, + { /* 9560 */ + 0, + /* */ + }, + { /* 9561 */ + 772, + /* VPCOMWri */ + }, + { /* 9562 */ + 0, + /* */ + }, + { /* 9563 */ + 409, + /* VPCONFLICTDZ128rm */ + }, + { /* 9564 */ + 334, + /* VPCONFLICTDZ128rmb */ + }, + { /* 9565 */ + 335, + /* VPCONFLICTDZ128rmbk */ + }, + { /* 9566 */ + 336, + /* VPCONFLICTDZ128rmbkz */ + }, + { /* 9567 */ + 410, + /* VPCONFLICTDZ128rmk */ + }, + { /* 9568 */ + 411, + /* VPCONFLICTDZ128rmkz */ + }, + { /* 9569 */ + 330, + /* VPCONFLICTDZ128rr */ + }, + { /* 9570 */ + 331, + /* VPCONFLICTDZ128rrk */ + }, + { /* 9571 */ + 332, + /* VPCONFLICTDZ128rrkz */ + }, + { /* 9572 */ + 412, + /* VPCONFLICTDZ256rm */ + }, + { /* 9573 */ + 337, + /* VPCONFLICTDZ256rmb */ + }, + { /* 9574 */ + 338, + /* VPCONFLICTDZ256rmbk */ + }, + { /* 9575 */ + 339, + /* VPCONFLICTDZ256rmbkz */ + }, + { /* 9576 */ + 413, + /* VPCONFLICTDZ256rmk */ + }, + { /* 9577 */ + 414, + /* VPCONFLICTDZ256rmkz */ + }, + { /* 9578 */ + 415, + /* VPCONFLICTDZ256rr */ + }, + { /* 9579 */ + 416, + /* VPCONFLICTDZ256rrk */ + }, + { /* 9580 */ + 417, + /* VPCONFLICTDZ256rrkz */ + }, + { /* 9581 */ + 418, + /* VPCONFLICTDZrm */ + }, + { /* 9582 */ + 340, + /* VPCONFLICTDZrmb */ + }, + { /* 9583 */ + 341, + /* VPCONFLICTDZrmbk */ + }, + { /* 9584 */ + 342, + /* VPCONFLICTDZrmbkz */ + }, + { /* 9585 */ + 419, + /* VPCONFLICTDZrmk */ + }, + { /* 9586 */ + 420, + /* VPCONFLICTDZrmkz */ + }, + { /* 9587 */ + 421, + /* VPCONFLICTDZrr */ + }, + { /* 9588 */ + 425, + /* VPCONFLICTDZrrk */ + }, + { /* 9589 */ + 426, + /* VPCONFLICTDZrrkz */ + }, + { /* 9590 */ + 409, + /* VPCONFLICTQZ128rm */ + }, + { /* 9591 */ + 327, + /* VPCONFLICTQZ128rmb */ + }, + { /* 9592 */ + 328, + /* VPCONFLICTQZ128rmbk */ + }, + { /* 9593 */ + 329, + /* VPCONFLICTQZ128rmbkz */ + }, + { /* 9594 */ + 410, + /* VPCONFLICTQZ128rmk */ + }, + { /* 9595 */ + 411, + /* VPCONFLICTQZ128rmkz */ + }, + { /* 9596 */ + 330, + /* VPCONFLICTQZ128rr */ + }, + { /* 9597 */ + 331, + /* VPCONFLICTQZ128rrk */ + }, + { /* 9598 */ + 332, + /* VPCONFLICTQZ128rrkz */ + }, + { /* 9599 */ + 412, + /* VPCONFLICTQZ256rm */ + }, + { /* 9600 */ + 306, + /* VPCONFLICTQZ256rmb */ + }, + { /* 9601 */ + 307, + /* VPCONFLICTQZ256rmbk */ + }, + { /* 9602 */ + 308, + /* VPCONFLICTQZ256rmbkz */ + }, + { /* 9603 */ + 413, + /* VPCONFLICTQZ256rmk */ + }, + { /* 9604 */ + 414, + /* VPCONFLICTQZ256rmkz */ + }, + { /* 9605 */ + 415, + /* VPCONFLICTQZ256rr */ + }, + { /* 9606 */ + 416, + /* VPCONFLICTQZ256rrk */ + }, + { /* 9607 */ + 417, + /* VPCONFLICTQZ256rrkz */ + }, + { /* 9608 */ + 418, + /* VPCONFLICTQZrm */ + }, + { /* 9609 */ + 312, + /* VPCONFLICTQZrmb */ + }, + { /* 9610 */ + 313, + /* VPCONFLICTQZrmbk */ + }, + { /* 9611 */ + 314, + /* VPCONFLICTQZrmbkz */ + }, + { /* 9612 */ + 419, + /* VPCONFLICTQZrmk */ + }, + { /* 9613 */ + 420, + /* VPCONFLICTQZrmkz */ + }, + { /* 9614 */ + 421, + /* VPCONFLICTQZrr */ + }, + { /* 9615 */ + 425, + /* VPCONFLICTQZrrk */ + }, + { /* 9616 */ + 426, + /* VPCONFLICTQZrrkz */ + }, + { /* 9617 */ + 202, + /* VPDPBUSDSZ128m */ + }, + { /* 9618 */ + 540, + /* VPDPBUSDSZ128mb */ + }, + { /* 9619 */ + 238, + /* VPDPBUSDSZ128mbk */ + }, + { /* 9620 */ + 238, + /* VPDPBUSDSZ128mbkz */ + }, + { /* 9621 */ + 203, + /* VPDPBUSDSZ128mk */ + }, + { /* 9622 */ + 203, + /* VPDPBUSDSZ128mkz */ + }, + { /* 9623 */ + 530, + /* VPDPBUSDSZ128r */ + }, + { /* 9624 */ + 212, + /* VPDPBUSDSZ128rk */ + }, + { /* 9625 */ + 212, + /* VPDPBUSDSZ128rkz */ + }, + { /* 9626 */ + 531, + /* VPDPBUSDSZ256m */ + }, + { /* 9627 */ + 541, + /* VPDPBUSDSZ256mb */ + }, + { /* 9628 */ + 241, + /* VPDPBUSDSZ256mbk */ + }, + { /* 9629 */ + 241, + /* VPDPBUSDSZ256mbkz */ + }, + { /* 9630 */ + 218, + /* VPDPBUSDSZ256mk */ + }, + { /* 9631 */ + 218, + /* VPDPBUSDSZ256mkz */ + }, + { /* 9632 */ + 533, + /* VPDPBUSDSZ256r */ + }, + { /* 9633 */ + 221, + /* VPDPBUSDSZ256rk */ + }, + { /* 9634 */ + 221, + /* VPDPBUSDSZ256rkz */ + }, + { /* 9635 */ + 534, + /* VPDPBUSDSZm */ + }, + { /* 9636 */ + 542, + /* VPDPBUSDSZmb */ + }, + { /* 9637 */ + 244, + /* VPDPBUSDSZmbk */ + }, + { /* 9638 */ + 244, + /* VPDPBUSDSZmbkz */ + }, + { /* 9639 */ + 227, + /* VPDPBUSDSZmk */ + }, + { /* 9640 */ + 227, + /* VPDPBUSDSZmkz */ + }, + { /* 9641 */ + 536, + /* VPDPBUSDSZr */ + }, + { /* 9642 */ + 233, + /* VPDPBUSDSZrk */ + }, + { /* 9643 */ + 233, + /* VPDPBUSDSZrkz */ + }, + { /* 9644 */ + 202, + /* VPDPBUSDZ128m */ + }, + { /* 9645 */ + 540, + /* VPDPBUSDZ128mb */ + }, + { /* 9646 */ + 238, + /* VPDPBUSDZ128mbk */ + }, + { /* 9647 */ + 238, + /* VPDPBUSDZ128mbkz */ + }, + { /* 9648 */ + 203, + /* VPDPBUSDZ128mk */ + }, + { /* 9649 */ + 203, + /* VPDPBUSDZ128mkz */ + }, + { /* 9650 */ + 530, + /* VPDPBUSDZ128r */ + }, + { /* 9651 */ + 212, + /* VPDPBUSDZ128rk */ + }, + { /* 9652 */ + 212, + /* VPDPBUSDZ128rkz */ + }, + { /* 9653 */ + 531, + /* VPDPBUSDZ256m */ + }, + { /* 9654 */ + 541, + /* VPDPBUSDZ256mb */ + }, + { /* 9655 */ + 241, + /* VPDPBUSDZ256mbk */ + }, + { /* 9656 */ + 241, + /* VPDPBUSDZ256mbkz */ + }, + { /* 9657 */ + 218, + /* VPDPBUSDZ256mk */ + }, + { /* 9658 */ + 218, + /* VPDPBUSDZ256mkz */ + }, + { /* 9659 */ + 533, + /* VPDPBUSDZ256r */ + }, + { /* 9660 */ + 221, + /* VPDPBUSDZ256rk */ + }, + { /* 9661 */ + 221, + /* VPDPBUSDZ256rkz */ + }, + { /* 9662 */ + 534, + /* VPDPBUSDZm */ + }, + { /* 9663 */ + 542, + /* VPDPBUSDZmb */ + }, + { /* 9664 */ + 244, + /* VPDPBUSDZmbk */ + }, + { /* 9665 */ + 244, + /* VPDPBUSDZmbkz */ + }, + { /* 9666 */ + 227, + /* VPDPBUSDZmk */ + }, + { /* 9667 */ + 227, + /* VPDPBUSDZmkz */ + }, + { /* 9668 */ + 536, + /* VPDPBUSDZr */ + }, + { /* 9669 */ + 233, + /* VPDPBUSDZrk */ + }, + { /* 9670 */ + 233, + /* VPDPBUSDZrkz */ + }, + { /* 9671 */ + 202, + /* VPDPWSSDSZ128m */ + }, + { /* 9672 */ + 540, + /* VPDPWSSDSZ128mb */ + }, + { /* 9673 */ + 238, + /* VPDPWSSDSZ128mbk */ + }, + { /* 9674 */ + 238, + /* VPDPWSSDSZ128mbkz */ + }, + { /* 9675 */ + 203, + /* VPDPWSSDSZ128mk */ + }, + { /* 9676 */ + 203, + /* VPDPWSSDSZ128mkz */ + }, + { /* 9677 */ + 530, + /* VPDPWSSDSZ128r */ + }, + { /* 9678 */ + 212, + /* VPDPWSSDSZ128rk */ + }, + { /* 9679 */ + 212, + /* VPDPWSSDSZ128rkz */ + }, + { /* 9680 */ + 531, + /* VPDPWSSDSZ256m */ + }, + { /* 9681 */ + 541, + /* VPDPWSSDSZ256mb */ + }, + { /* 9682 */ + 241, + /* VPDPWSSDSZ256mbk */ + }, + { /* 9683 */ + 241, + /* VPDPWSSDSZ256mbkz */ + }, + { /* 9684 */ + 218, + /* VPDPWSSDSZ256mk */ + }, + { /* 9685 */ + 218, + /* VPDPWSSDSZ256mkz */ + }, + { /* 9686 */ + 533, + /* VPDPWSSDSZ256r */ + }, + { /* 9687 */ + 221, + /* VPDPWSSDSZ256rk */ + }, + { /* 9688 */ + 221, + /* VPDPWSSDSZ256rkz */ + }, + { /* 9689 */ + 534, + /* VPDPWSSDSZm */ + }, + { /* 9690 */ + 542, + /* VPDPWSSDSZmb */ + }, + { /* 9691 */ + 244, + /* VPDPWSSDSZmbk */ + }, + { /* 9692 */ + 244, + /* VPDPWSSDSZmbkz */ + }, + { /* 9693 */ + 227, + /* VPDPWSSDSZmk */ + }, + { /* 9694 */ + 227, + /* VPDPWSSDSZmkz */ + }, + { /* 9695 */ + 536, + /* VPDPWSSDSZr */ + }, + { /* 9696 */ + 233, + /* VPDPWSSDSZrk */ + }, + { /* 9697 */ + 233, + /* VPDPWSSDSZrkz */ + }, + { /* 9698 */ + 202, + /* VPDPWSSDZ128m */ + }, + { /* 9699 */ + 540, + /* VPDPWSSDZ128mb */ + }, + { /* 9700 */ + 238, + /* VPDPWSSDZ128mbk */ + }, + { /* 9701 */ + 238, + /* VPDPWSSDZ128mbkz */ + }, + { /* 9702 */ + 203, + /* VPDPWSSDZ128mk */ + }, + { /* 9703 */ + 203, + /* VPDPWSSDZ128mkz */ + }, + { /* 9704 */ + 530, + /* VPDPWSSDZ128r */ + }, + { /* 9705 */ + 212, + /* VPDPWSSDZ128rk */ + }, + { /* 9706 */ + 212, + /* VPDPWSSDZ128rkz */ + }, + { /* 9707 */ + 531, + /* VPDPWSSDZ256m */ + }, + { /* 9708 */ + 541, + /* VPDPWSSDZ256mb */ + }, + { /* 9709 */ + 241, + /* VPDPWSSDZ256mbk */ + }, + { /* 9710 */ + 241, + /* VPDPWSSDZ256mbkz */ + }, + { /* 9711 */ + 218, + /* VPDPWSSDZ256mk */ + }, + { /* 9712 */ + 218, + /* VPDPWSSDZ256mkz */ + }, + { /* 9713 */ + 533, + /* VPDPWSSDZ256r */ + }, + { /* 9714 */ + 221, + /* VPDPWSSDZ256rk */ + }, + { /* 9715 */ + 221, + /* VPDPWSSDZ256rkz */ + }, + { /* 9716 */ + 534, + /* VPDPWSSDZm */ + }, + { /* 9717 */ + 542, + /* VPDPWSSDZmb */ + }, + { /* 9718 */ + 244, + /* VPDPWSSDZmbk */ + }, + { /* 9719 */ + 244, + /* VPDPWSSDZmbkz */ + }, + { /* 9720 */ + 227, + /* VPDPWSSDZmk */ + }, + { /* 9721 */ + 227, + /* VPDPWSSDZmkz */ + }, + { /* 9722 */ + 536, + /* VPDPWSSDZr */ + }, + { /* 9723 */ + 233, + /* VPDPWSSDZrk */ + }, + { /* 9724 */ + 233, + /* VPDPWSSDZrkz */ + }, + { /* 9725 */ + 297, + /* VPERM2F128rm */ + }, + { /* 9726 */ + 298, + /* VPERM2F128rr */ + }, + { /* 9727 */ + 297, + /* VPERM2I128rm */ + }, + { /* 9728 */ + 298, + /* VPERM2I128rr */ + }, + { /* 9729 */ + 206, + /* VPERMBZ128rm */ + }, + { /* 9730 */ + 203, + /* VPERMBZ128rmk */ + }, + { /* 9731 */ + 210, + /* VPERMBZ128rmkz */ + }, + { /* 9732 */ + 211, + /* VPERMBZ128rr */ + }, + { /* 9733 */ + 212, + /* VPERMBZ128rrk */ + }, + { /* 9734 */ + 213, + /* VPERMBZ128rrkz */ + }, + { /* 9735 */ + 214, + /* VPERMBZ256rm */ + }, + { /* 9736 */ + 218, + /* VPERMBZ256rmk */ + }, + { /* 9737 */ + 219, + /* VPERMBZ256rmkz */ + }, + { /* 9738 */ + 220, + /* VPERMBZ256rr */ + }, + { /* 9739 */ + 221, + /* VPERMBZ256rrk */ + }, + { /* 9740 */ + 222, + /* VPERMBZ256rrkz */ + }, + { /* 9741 */ + 223, + /* VPERMBZrm */ + }, + { /* 9742 */ + 227, + /* VPERMBZrmk */ + }, + { /* 9743 */ + 228, + /* VPERMBZrmkz */ + }, + { /* 9744 */ + 229, + /* VPERMBZrr */ + }, + { /* 9745 */ + 233, + /* VPERMBZrrk */ + }, + { /* 9746 */ + 234, + /* VPERMBZrrkz */ + }, + { /* 9747 */ + 204, + /* VPERMDYrm */ + }, + { /* 9748 */ + 205, + /* VPERMDYrr */ + }, + { /* 9749 */ + 214, + /* VPERMDZ256rm */ + }, + { /* 9750 */ + 240, + /* VPERMDZ256rmb */ + }, + { /* 9751 */ + 241, + /* VPERMDZ256rmbk */ + }, + { /* 9752 */ + 242, + /* VPERMDZ256rmbkz */ + }, + { /* 9753 */ + 218, + /* VPERMDZ256rmk */ + }, + { /* 9754 */ + 219, + /* VPERMDZ256rmkz */ + }, + { /* 9755 */ + 220, + /* VPERMDZ256rr */ + }, + { /* 9756 */ + 221, + /* VPERMDZ256rrk */ + }, + { /* 9757 */ + 222, + /* VPERMDZ256rrkz */ + }, + { /* 9758 */ + 223, + /* VPERMDZrm */ + }, + { /* 9759 */ + 243, + /* VPERMDZrmb */ + }, + { /* 9760 */ + 244, + /* VPERMDZrmbk */ + }, + { /* 9761 */ + 245, + /* VPERMDZrmbkz */ + }, + { /* 9762 */ + 227, + /* VPERMDZrmk */ + }, + { /* 9763 */ + 228, + /* VPERMDZrmkz */ + }, + { /* 9764 */ + 229, + /* VPERMDZrr */ + }, + { /* 9765 */ + 233, + /* VPERMDZrrk */ + }, + { /* 9766 */ + 234, + /* VPERMDZrrkz */ + }, + { /* 9767 */ + 202, + /* VPERMI2B128rm */ + }, + { /* 9768 */ + 203, + /* VPERMI2B128rmk */ + }, + { /* 9769 */ + 203, + /* VPERMI2B128rmkz */ + }, + { /* 9770 */ + 530, + /* VPERMI2B128rr */ + }, + { /* 9771 */ + 212, + /* VPERMI2B128rrk */ + }, + { /* 9772 */ + 212, + /* VPERMI2B128rrkz */ + }, + { /* 9773 */ + 531, + /* VPERMI2B256rm */ + }, + { /* 9774 */ + 218, + /* VPERMI2B256rmk */ + }, + { /* 9775 */ + 218, + /* VPERMI2B256rmkz */ + }, + { /* 9776 */ + 533, + /* VPERMI2B256rr */ + }, + { /* 9777 */ + 221, + /* VPERMI2B256rrk */ + }, + { /* 9778 */ + 221, + /* VPERMI2B256rrkz */ + }, + { /* 9779 */ + 534, + /* VPERMI2Brm */ + }, + { /* 9780 */ + 227, + /* VPERMI2Brmk */ + }, + { /* 9781 */ + 227, + /* VPERMI2Brmkz */ + }, + { /* 9782 */ + 536, + /* VPERMI2Brr */ + }, + { /* 9783 */ + 233, + /* VPERMI2Brrk */ + }, + { /* 9784 */ + 233, + /* VPERMI2Brrkz */ + }, + { /* 9785 */ + 202, + /* VPERMI2D128rm */ + }, + { /* 9786 */ + 540, + /* VPERMI2D128rmb */ + }, + { /* 9787 */ + 238, + /* VPERMI2D128rmbk */ + }, + { /* 9788 */ + 238, + /* VPERMI2D128rmbkz */ + }, + { /* 9789 */ + 203, + /* VPERMI2D128rmk */ + }, + { /* 9790 */ + 203, + /* VPERMI2D128rmkz */ + }, + { /* 9791 */ + 530, + /* VPERMI2D128rr */ + }, + { /* 9792 */ + 212, + /* VPERMI2D128rrk */ + }, + { /* 9793 */ + 212, + /* VPERMI2D128rrkz */ + }, + { /* 9794 */ + 531, + /* VPERMI2D256rm */ + }, + { /* 9795 */ + 541, + /* VPERMI2D256rmb */ + }, + { /* 9796 */ + 241, + /* VPERMI2D256rmbk */ + }, + { /* 9797 */ + 241, + /* VPERMI2D256rmbkz */ + }, + { /* 9798 */ + 218, + /* VPERMI2D256rmk */ + }, + { /* 9799 */ + 218, + /* VPERMI2D256rmkz */ + }, + { /* 9800 */ + 533, + /* VPERMI2D256rr */ + }, + { /* 9801 */ + 221, + /* VPERMI2D256rrk */ + }, + { /* 9802 */ + 221, + /* VPERMI2D256rrkz */ + }, + { /* 9803 */ + 534, + /* VPERMI2Drm */ + }, + { /* 9804 */ + 542, + /* VPERMI2Drmb */ + }, + { /* 9805 */ + 244, + /* VPERMI2Drmbk */ + }, + { /* 9806 */ + 244, + /* VPERMI2Drmbkz */ + }, + { /* 9807 */ + 227, + /* VPERMI2Drmk */ + }, + { /* 9808 */ + 227, + /* VPERMI2Drmkz */ + }, + { /* 9809 */ + 536, + /* VPERMI2Drr */ + }, + { /* 9810 */ + 233, + /* VPERMI2Drrk */ + }, + { /* 9811 */ + 233, + /* VPERMI2Drrkz */ + }, + { /* 9812 */ + 202, + /* VPERMI2PD128rm */ + }, + { /* 9813 */ + 529, + /* VPERMI2PD128rmb */ + }, + { /* 9814 */ + 208, + /* VPERMI2PD128rmbk */ + }, + { /* 9815 */ + 208, + /* VPERMI2PD128rmbkz */ + }, + { /* 9816 */ + 203, + /* VPERMI2PD128rmk */ + }, + { /* 9817 */ + 203, + /* VPERMI2PD128rmkz */ + }, + { /* 9818 */ + 530, + /* VPERMI2PD128rr */ + }, + { /* 9819 */ + 212, + /* VPERMI2PD128rrk */ + }, + { /* 9820 */ + 212, + /* VPERMI2PD128rrkz */ + }, + { /* 9821 */ + 531, + /* VPERMI2PD256rm */ + }, + { /* 9822 */ + 532, + /* VPERMI2PD256rmb */ + }, + { /* 9823 */ + 216, + /* VPERMI2PD256rmbk */ + }, + { /* 9824 */ + 216, + /* VPERMI2PD256rmbkz */ + }, + { /* 9825 */ + 218, + /* VPERMI2PD256rmk */ + }, + { /* 9826 */ + 218, + /* VPERMI2PD256rmkz */ + }, + { /* 9827 */ + 533, + /* VPERMI2PD256rr */ + }, + { /* 9828 */ + 221, + /* VPERMI2PD256rrk */ + }, + { /* 9829 */ + 221, + /* VPERMI2PD256rrkz */ + }, + { /* 9830 */ + 534, + /* VPERMI2PDrm */ + }, + { /* 9831 */ + 535, + /* VPERMI2PDrmb */ + }, + { /* 9832 */ + 225, + /* VPERMI2PDrmbk */ + }, + { /* 9833 */ + 225, + /* VPERMI2PDrmbkz */ + }, + { /* 9834 */ + 227, + /* VPERMI2PDrmk */ + }, + { /* 9835 */ + 227, + /* VPERMI2PDrmkz */ + }, + { /* 9836 */ + 536, + /* VPERMI2PDrr */ + }, + { /* 9837 */ + 233, + /* VPERMI2PDrrk */ + }, + { /* 9838 */ + 233, + /* VPERMI2PDrrkz */ + }, + { /* 9839 */ + 202, + /* VPERMI2PS128rm */ + }, + { /* 9840 */ + 540, + /* VPERMI2PS128rmb */ + }, + { /* 9841 */ + 238, + /* VPERMI2PS128rmbk */ + }, + { /* 9842 */ + 238, + /* VPERMI2PS128rmbkz */ + }, + { /* 9843 */ + 203, + /* VPERMI2PS128rmk */ + }, + { /* 9844 */ + 203, + /* VPERMI2PS128rmkz */ + }, + { /* 9845 */ + 530, + /* VPERMI2PS128rr */ + }, + { /* 9846 */ + 212, + /* VPERMI2PS128rrk */ + }, + { /* 9847 */ + 212, + /* VPERMI2PS128rrkz */ + }, + { /* 9848 */ + 531, + /* VPERMI2PS256rm */ + }, + { /* 9849 */ + 541, + /* VPERMI2PS256rmb */ + }, + { /* 9850 */ + 241, + /* VPERMI2PS256rmbk */ + }, + { /* 9851 */ + 241, + /* VPERMI2PS256rmbkz */ + }, + { /* 9852 */ + 218, + /* VPERMI2PS256rmk */ + }, + { /* 9853 */ + 218, + /* VPERMI2PS256rmkz */ + }, + { /* 9854 */ + 533, + /* VPERMI2PS256rr */ + }, + { /* 9855 */ + 221, + /* VPERMI2PS256rrk */ + }, + { /* 9856 */ + 221, + /* VPERMI2PS256rrkz */ + }, + { /* 9857 */ + 534, + /* VPERMI2PSrm */ + }, + { /* 9858 */ + 542, + /* VPERMI2PSrmb */ + }, + { /* 9859 */ + 244, + /* VPERMI2PSrmbk */ + }, + { /* 9860 */ + 244, + /* VPERMI2PSrmbkz */ + }, + { /* 9861 */ + 227, + /* VPERMI2PSrmk */ + }, + { /* 9862 */ + 227, + /* VPERMI2PSrmkz */ + }, + { /* 9863 */ + 536, + /* VPERMI2PSrr */ + }, + { /* 9864 */ + 233, + /* VPERMI2PSrrk */ + }, + { /* 9865 */ + 233, + /* VPERMI2PSrrkz */ + }, + { /* 9866 */ + 202, + /* VPERMI2Q128rm */ + }, + { /* 9867 */ + 529, + /* VPERMI2Q128rmb */ + }, + { /* 9868 */ + 208, + /* VPERMI2Q128rmbk */ + }, + { /* 9869 */ + 208, + /* VPERMI2Q128rmbkz */ + }, + { /* 9870 */ + 203, + /* VPERMI2Q128rmk */ + }, + { /* 9871 */ + 203, + /* VPERMI2Q128rmkz */ + }, + { /* 9872 */ + 530, + /* VPERMI2Q128rr */ + }, + { /* 9873 */ + 212, + /* VPERMI2Q128rrk */ + }, + { /* 9874 */ + 212, + /* VPERMI2Q128rrkz */ + }, + { /* 9875 */ + 531, + /* VPERMI2Q256rm */ + }, + { /* 9876 */ + 532, + /* VPERMI2Q256rmb */ + }, + { /* 9877 */ + 216, + /* VPERMI2Q256rmbk */ + }, + { /* 9878 */ + 216, + /* VPERMI2Q256rmbkz */ + }, + { /* 9879 */ + 218, + /* VPERMI2Q256rmk */ + }, + { /* 9880 */ + 218, + /* VPERMI2Q256rmkz */ + }, + { /* 9881 */ + 533, + /* VPERMI2Q256rr */ + }, + { /* 9882 */ + 221, + /* VPERMI2Q256rrk */ + }, + { /* 9883 */ + 221, + /* VPERMI2Q256rrkz */ + }, + { /* 9884 */ + 534, + /* VPERMI2Qrm */ + }, + { /* 9885 */ + 535, + /* VPERMI2Qrmb */ + }, + { /* 9886 */ + 225, + /* VPERMI2Qrmbk */ + }, + { /* 9887 */ + 225, + /* VPERMI2Qrmbkz */ + }, + { /* 9888 */ + 227, + /* VPERMI2Qrmk */ + }, + { /* 9889 */ + 227, + /* VPERMI2Qrmkz */ + }, + { /* 9890 */ + 536, + /* VPERMI2Qrr */ + }, + { /* 9891 */ + 233, + /* VPERMI2Qrrk */ + }, + { /* 9892 */ + 233, + /* VPERMI2Qrrkz */ + }, + { /* 9893 */ + 202, + /* VPERMI2W128rm */ + }, + { /* 9894 */ + 203, + /* VPERMI2W128rmk */ + }, + { /* 9895 */ + 203, + /* VPERMI2W128rmkz */ + }, + { /* 9896 */ + 530, + /* VPERMI2W128rr */ + }, + { /* 9897 */ + 212, + /* VPERMI2W128rrk */ + }, + { /* 9898 */ + 212, + /* VPERMI2W128rrkz */ + }, + { /* 9899 */ + 531, + /* VPERMI2W256rm */ + }, + { /* 9900 */ + 218, + /* VPERMI2W256rmk */ + }, + { /* 9901 */ + 218, + /* VPERMI2W256rmkz */ + }, + { /* 9902 */ + 533, + /* VPERMI2W256rr */ + }, + { /* 9903 */ + 221, + /* VPERMI2W256rrk */ + }, + { /* 9904 */ + 221, + /* VPERMI2W256rrkz */ + }, + { /* 9905 */ + 534, + /* VPERMI2Wrm */ + }, + { /* 9906 */ + 227, + /* VPERMI2Wrmk */ + }, + { /* 9907 */ + 227, + /* VPERMI2Wrmkz */ + }, + { /* 9908 */ + 536, + /* VPERMI2Wrr */ + }, + { /* 9909 */ + 233, + /* VPERMI2Wrrk */ + }, + { /* 9910 */ + 233, + /* VPERMI2Wrrkz */ + }, + { /* 9911 */ + 783, + /* VPERMIL2PDYmr */ + }, + { /* 9912 */ + 784, + /* VPERMIL2PDYrm */ + }, + { /* 9913 */ + 785, + /* VPERMIL2PDYrr */ + }, + { /* 9914 */ + 786, + /* VPERMIL2PDYrr_REV */ + }, + { /* 9915 */ + 787, + /* VPERMIL2PDmr */ + }, + { /* 9916 */ + 788, + /* VPERMIL2PDrm */ + }, + { /* 9917 */ + 789, + /* VPERMIL2PDrr */ + }, + { /* 9918 */ + 790, + /* VPERMIL2PDrr_REV */ + }, + { /* 9919 */ + 783, + /* VPERMIL2PSYmr */ + }, + { /* 9920 */ + 784, + /* VPERMIL2PSYrm */ + }, + { /* 9921 */ + 785, + /* VPERMIL2PSYrr */ + }, + { /* 9922 */ + 786, + /* VPERMIL2PSYrr_REV */ + }, + { /* 9923 */ + 787, + /* VPERMIL2PSmr */ + }, + { /* 9924 */ + 788, + /* VPERMIL2PSrm */ + }, + { /* 9925 */ + 789, + /* VPERMIL2PSrr */ + }, + { /* 9926 */ + 790, + /* VPERMIL2PSrr_REV */ + }, + { /* 9927 */ + 791, + /* VPERMILPDYmi */ + }, + { /* 9928 */ + 792, + /* VPERMILPDYri */ + }, + { /* 9929 */ + 204, + /* VPERMILPDYrm */ + }, + { /* 9930 */ + 205, + /* VPERMILPDYrr */ + }, + { /* 9931 */ + 589, + /* VPERMILPDZ128mbi */ + }, + { /* 9932 */ + 590, + /* VPERMILPDZ128mbik */ + }, + { /* 9933 */ + 591, + /* VPERMILPDZ128mbikz */ + }, + { /* 9934 */ + 592, + /* VPERMILPDZ128mi */ + }, + { /* 9935 */ + 593, + /* VPERMILPDZ128mik */ + }, + { /* 9936 */ + 594, + /* VPERMILPDZ128mikz */ + }, + { /* 9937 */ + 595, + /* VPERMILPDZ128ri */ + }, + { /* 9938 */ + 596, + /* VPERMILPDZ128rik */ + }, + { /* 9939 */ + 597, + /* VPERMILPDZ128rikz */ + }, + { /* 9940 */ + 206, + /* VPERMILPDZ128rm */ + }, + { /* 9941 */ + 207, + /* VPERMILPDZ128rmb */ + }, + { /* 9942 */ + 208, + /* VPERMILPDZ128rmbk */ + }, + { /* 9943 */ + 209, + /* VPERMILPDZ128rmbkz */ + }, + { /* 9944 */ + 203, + /* VPERMILPDZ128rmk */ + }, + { /* 9945 */ + 210, + /* VPERMILPDZ128rmkz */ + }, + { /* 9946 */ + 211, + /* VPERMILPDZ128rr */ + }, + { /* 9947 */ + 212, + /* VPERMILPDZ128rrk */ + }, + { /* 9948 */ + 213, + /* VPERMILPDZ128rrkz */ + }, + { /* 9949 */ + 598, + /* VPERMILPDZ256mbi */ + }, + { /* 9950 */ + 599, + /* VPERMILPDZ256mbik */ + }, + { /* 9951 */ + 600, + /* VPERMILPDZ256mbikz */ + }, + { /* 9952 */ + 601, + /* VPERMILPDZ256mi */ + }, + { /* 9953 */ + 602, + /* VPERMILPDZ256mik */ + }, + { /* 9954 */ + 603, + /* VPERMILPDZ256mikz */ + }, + { /* 9955 */ + 604, + /* VPERMILPDZ256ri */ + }, + { /* 9956 */ + 605, + /* VPERMILPDZ256rik */ + }, + { /* 9957 */ + 606, + /* VPERMILPDZ256rikz */ + }, + { /* 9958 */ + 214, + /* VPERMILPDZ256rm */ + }, + { /* 9959 */ + 215, + /* VPERMILPDZ256rmb */ + }, + { /* 9960 */ + 216, + /* VPERMILPDZ256rmbk */ + }, + { /* 9961 */ + 217, + /* VPERMILPDZ256rmbkz */ + }, + { /* 9962 */ + 218, + /* VPERMILPDZ256rmk */ + }, + { /* 9963 */ + 219, + /* VPERMILPDZ256rmkz */ + }, + { /* 9964 */ + 220, + /* VPERMILPDZ256rr */ + }, + { /* 9965 */ + 221, + /* VPERMILPDZ256rrk */ + }, + { /* 9966 */ + 222, + /* VPERMILPDZ256rrkz */ + }, + { /* 9967 */ + 607, + /* VPERMILPDZmbi */ + }, + { /* 9968 */ + 608, + /* VPERMILPDZmbik */ + }, + { /* 9969 */ + 609, + /* VPERMILPDZmbikz */ + }, + { /* 9970 */ + 610, + /* VPERMILPDZmi */ + }, + { /* 9971 */ + 611, + /* VPERMILPDZmik */ + }, + { /* 9972 */ + 612, + /* VPERMILPDZmikz */ + }, + { /* 9973 */ + 613, + /* VPERMILPDZri */ + }, + { /* 9974 */ + 617, + /* VPERMILPDZrik */ + }, + { /* 9975 */ + 618, + /* VPERMILPDZrikz */ + }, + { /* 9976 */ + 223, + /* VPERMILPDZrm */ + }, + { /* 9977 */ + 224, + /* VPERMILPDZrmb */ + }, + { /* 9978 */ + 225, + /* VPERMILPDZrmbk */ + }, + { /* 9979 */ + 226, + /* VPERMILPDZrmbkz */ + }, + { /* 9980 */ + 227, + /* VPERMILPDZrmk */ + }, + { /* 9981 */ + 228, + /* VPERMILPDZrmkz */ + }, + { /* 9982 */ + 229, + /* VPERMILPDZrr */ + }, + { /* 9983 */ + 233, + /* VPERMILPDZrrk */ + }, + { /* 9984 */ + 234, + /* VPERMILPDZrrkz */ + }, + { /* 9985 */ + 32, + /* VPERMILPDmi */ + }, + { /* 9986 */ + 33, + /* VPERMILPDri */ + }, + { /* 9987 */ + 235, + /* VPERMILPDrm */ + }, + { /* 9988 */ + 236, + /* VPERMILPDrr */ + }, + { /* 9989 */ + 791, + /* VPERMILPSYmi */ + }, + { /* 9990 */ + 792, + /* VPERMILPSYri */ + }, + { /* 9991 */ + 204, + /* VPERMILPSYrm */ + }, + { /* 9992 */ + 205, + /* VPERMILPSYrr */ + }, + { /* 9993 */ + 619, + /* VPERMILPSZ128mbi */ + }, + { /* 9994 */ + 620, + /* VPERMILPSZ128mbik */ + }, + { /* 9995 */ + 621, + /* VPERMILPSZ128mbikz */ + }, + { /* 9996 */ + 592, + /* VPERMILPSZ128mi */ + }, + { /* 9997 */ + 593, + /* VPERMILPSZ128mik */ + }, + { /* 9998 */ + 594, + /* VPERMILPSZ128mikz */ + }, + { /* 9999 */ + 595, + /* VPERMILPSZ128ri */ + }, + { /* 10000 */ + 596, + /* VPERMILPSZ128rik */ + }, + { /* 10001 */ + 597, + /* VPERMILPSZ128rikz */ + }, + { /* 10002 */ + 206, + /* VPERMILPSZ128rm */ + }, + { /* 10003 */ + 237, + /* VPERMILPSZ128rmb */ + }, + { /* 10004 */ + 238, + /* VPERMILPSZ128rmbk */ + }, + { /* 10005 */ + 239, + /* VPERMILPSZ128rmbkz */ + }, + { /* 10006 */ + 203, + /* VPERMILPSZ128rmk */ + }, + { /* 10007 */ + 210, + /* VPERMILPSZ128rmkz */ + }, + { /* 10008 */ + 211, + /* VPERMILPSZ128rr */ + }, + { /* 10009 */ + 212, + /* VPERMILPSZ128rrk */ + }, + { /* 10010 */ + 213, + /* VPERMILPSZ128rrkz */ + }, + { /* 10011 */ + 622, + /* VPERMILPSZ256mbi */ + }, + { /* 10012 */ + 623, + /* VPERMILPSZ256mbik */ + }, + { /* 10013 */ + 624, + /* VPERMILPSZ256mbikz */ + }, + { /* 10014 */ + 601, + /* VPERMILPSZ256mi */ + }, + { /* 10015 */ + 602, + /* VPERMILPSZ256mik */ + }, + { /* 10016 */ + 603, + /* VPERMILPSZ256mikz */ + }, + { /* 10017 */ + 604, + /* VPERMILPSZ256ri */ + }, + { /* 10018 */ + 605, + /* VPERMILPSZ256rik */ + }, + { /* 10019 */ + 606, + /* VPERMILPSZ256rikz */ + }, + { /* 10020 */ + 214, + /* VPERMILPSZ256rm */ + }, + { /* 10021 */ + 240, + /* VPERMILPSZ256rmb */ + }, + { /* 10022 */ + 241, + /* VPERMILPSZ256rmbk */ + }, + { /* 10023 */ + 242, + /* VPERMILPSZ256rmbkz */ + }, + { /* 10024 */ + 218, + /* VPERMILPSZ256rmk */ + }, + { /* 10025 */ + 219, + /* VPERMILPSZ256rmkz */ + }, + { /* 10026 */ + 220, + /* VPERMILPSZ256rr */ + }, + { /* 10027 */ + 221, + /* VPERMILPSZ256rrk */ + }, + { /* 10028 */ + 222, + /* VPERMILPSZ256rrkz */ + }, + { /* 10029 */ + 625, + /* VPERMILPSZmbi */ + }, + { /* 10030 */ + 626, + /* VPERMILPSZmbik */ + }, + { /* 10031 */ + 627, + /* VPERMILPSZmbikz */ + }, + { /* 10032 */ + 610, + /* VPERMILPSZmi */ + }, + { /* 10033 */ + 611, + /* VPERMILPSZmik */ + }, + { /* 10034 */ + 612, + /* VPERMILPSZmikz */ + }, + { /* 10035 */ + 613, + /* VPERMILPSZri */ + }, + { /* 10036 */ + 617, + /* VPERMILPSZrik */ + }, + { /* 10037 */ + 618, + /* VPERMILPSZrikz */ + }, + { /* 10038 */ + 223, + /* VPERMILPSZrm */ + }, + { /* 10039 */ + 243, + /* VPERMILPSZrmb */ + }, + { /* 10040 */ + 244, + /* VPERMILPSZrmbk */ + }, + { /* 10041 */ + 245, + /* VPERMILPSZrmbkz */ + }, + { /* 10042 */ + 227, + /* VPERMILPSZrmk */ + }, + { /* 10043 */ + 228, + /* VPERMILPSZrmkz */ + }, + { /* 10044 */ + 229, + /* VPERMILPSZrr */ + }, + { /* 10045 */ + 233, + /* VPERMILPSZrrk */ + }, + { /* 10046 */ + 234, + /* VPERMILPSZrrkz */ + }, + { /* 10047 */ + 32, + /* VPERMILPSmi */ + }, + { /* 10048 */ + 33, + /* VPERMILPSri */ + }, + { /* 10049 */ + 235, + /* VPERMILPSrm */ + }, + { /* 10050 */ + 236, + /* VPERMILPSrr */ + }, + { /* 10051 */ + 791, + /* VPERMPDYmi */ + }, + { /* 10052 */ + 792, + /* VPERMPDYri */ + }, + { /* 10053 */ + 598, + /* VPERMPDZ256mbi */ + }, + { /* 10054 */ + 599, + /* VPERMPDZ256mbik */ + }, + { /* 10055 */ + 600, + /* VPERMPDZ256mbikz */ + }, + { /* 10056 */ + 601, + /* VPERMPDZ256mi */ + }, + { /* 10057 */ + 602, + /* VPERMPDZ256mik */ + }, + { /* 10058 */ + 603, + /* VPERMPDZ256mikz */ + }, + { /* 10059 */ + 604, + /* VPERMPDZ256ri */ + }, + { /* 10060 */ + 605, + /* VPERMPDZ256rik */ + }, + { /* 10061 */ + 606, + /* VPERMPDZ256rikz */ + }, + { /* 10062 */ + 214, + /* VPERMPDZ256rm */ + }, + { /* 10063 */ + 215, + /* VPERMPDZ256rmb */ + }, + { /* 10064 */ + 216, + /* VPERMPDZ256rmbk */ + }, + { /* 10065 */ + 217, + /* VPERMPDZ256rmbkz */ + }, + { /* 10066 */ + 218, + /* VPERMPDZ256rmk */ + }, + { /* 10067 */ + 219, + /* VPERMPDZ256rmkz */ + }, + { /* 10068 */ + 220, + /* VPERMPDZ256rr */ + }, + { /* 10069 */ + 221, + /* VPERMPDZ256rrk */ + }, + { /* 10070 */ + 222, + /* VPERMPDZ256rrkz */ + }, + { /* 10071 */ + 607, + /* VPERMPDZmbi */ + }, + { /* 10072 */ + 608, + /* VPERMPDZmbik */ + }, + { /* 10073 */ + 609, + /* VPERMPDZmbikz */ + }, + { /* 10074 */ + 610, + /* VPERMPDZmi */ + }, + { /* 10075 */ + 611, + /* VPERMPDZmik */ + }, + { /* 10076 */ + 612, + /* VPERMPDZmikz */ + }, + { /* 10077 */ + 613, + /* VPERMPDZri */ + }, + { /* 10078 */ + 617, + /* VPERMPDZrik */ + }, + { /* 10079 */ + 618, + /* VPERMPDZrikz */ + }, + { /* 10080 */ + 223, + /* VPERMPDZrm */ + }, + { /* 10081 */ + 224, + /* VPERMPDZrmb */ + }, + { /* 10082 */ + 225, + /* VPERMPDZrmbk */ + }, + { /* 10083 */ + 226, + /* VPERMPDZrmbkz */ + }, + { /* 10084 */ + 227, + /* VPERMPDZrmk */ + }, + { /* 10085 */ + 228, + /* VPERMPDZrmkz */ + }, + { /* 10086 */ + 229, + /* VPERMPDZrr */ + }, + { /* 10087 */ + 233, + /* VPERMPDZrrk */ + }, + { /* 10088 */ + 234, + /* VPERMPDZrrkz */ + }, + { /* 10089 */ + 204, + /* VPERMPSYrm */ + }, + { /* 10090 */ + 205, + /* VPERMPSYrr */ + }, + { /* 10091 */ + 214, + /* VPERMPSZ256rm */ + }, + { /* 10092 */ + 240, + /* VPERMPSZ256rmb */ + }, + { /* 10093 */ + 241, + /* VPERMPSZ256rmbk */ + }, + { /* 10094 */ + 242, + /* VPERMPSZ256rmbkz */ + }, + { /* 10095 */ + 218, + /* VPERMPSZ256rmk */ + }, + { /* 10096 */ + 219, + /* VPERMPSZ256rmkz */ + }, + { /* 10097 */ + 220, + /* VPERMPSZ256rr */ + }, + { /* 10098 */ + 221, + /* VPERMPSZ256rrk */ + }, + { /* 10099 */ + 222, + /* VPERMPSZ256rrkz */ + }, + { /* 10100 */ + 223, + /* VPERMPSZrm */ + }, + { /* 10101 */ + 243, + /* VPERMPSZrmb */ + }, + { /* 10102 */ + 244, + /* VPERMPSZrmbk */ + }, + { /* 10103 */ + 245, + /* VPERMPSZrmbkz */ + }, + { /* 10104 */ + 227, + /* VPERMPSZrmk */ + }, + { /* 10105 */ + 228, + /* VPERMPSZrmkz */ + }, + { /* 10106 */ + 229, + /* VPERMPSZrr */ + }, + { /* 10107 */ + 233, + /* VPERMPSZrrk */ + }, + { /* 10108 */ + 234, + /* VPERMPSZrrkz */ + }, + { /* 10109 */ + 791, + /* VPERMQYmi */ + }, + { /* 10110 */ + 792, + /* VPERMQYri */ + }, + { /* 10111 */ + 598, + /* VPERMQZ256mbi */ + }, + { /* 10112 */ + 599, + /* VPERMQZ256mbik */ + }, + { /* 10113 */ + 600, + /* VPERMQZ256mbikz */ + }, + { /* 10114 */ + 601, + /* VPERMQZ256mi */ + }, + { /* 10115 */ + 602, + /* VPERMQZ256mik */ + }, + { /* 10116 */ + 603, + /* VPERMQZ256mikz */ + }, + { /* 10117 */ + 604, + /* VPERMQZ256ri */ + }, + { /* 10118 */ + 605, + /* VPERMQZ256rik */ + }, + { /* 10119 */ + 606, + /* VPERMQZ256rikz */ + }, + { /* 10120 */ + 214, + /* VPERMQZ256rm */ + }, + { /* 10121 */ + 215, + /* VPERMQZ256rmb */ + }, + { /* 10122 */ + 216, + /* VPERMQZ256rmbk */ + }, + { /* 10123 */ + 217, + /* VPERMQZ256rmbkz */ + }, + { /* 10124 */ + 218, + /* VPERMQZ256rmk */ + }, + { /* 10125 */ + 219, + /* VPERMQZ256rmkz */ + }, + { /* 10126 */ + 220, + /* VPERMQZ256rr */ + }, + { /* 10127 */ + 221, + /* VPERMQZ256rrk */ + }, + { /* 10128 */ + 222, + /* VPERMQZ256rrkz */ + }, + { /* 10129 */ + 607, + /* VPERMQZmbi */ + }, + { /* 10130 */ + 608, + /* VPERMQZmbik */ + }, + { /* 10131 */ + 609, + /* VPERMQZmbikz */ + }, + { /* 10132 */ + 610, + /* VPERMQZmi */ + }, + { /* 10133 */ + 611, + /* VPERMQZmik */ + }, + { /* 10134 */ + 612, + /* VPERMQZmikz */ + }, + { /* 10135 */ + 613, + /* VPERMQZri */ + }, + { /* 10136 */ + 617, + /* VPERMQZrik */ + }, + { /* 10137 */ + 618, + /* VPERMQZrikz */ + }, + { /* 10138 */ + 223, + /* VPERMQZrm */ + }, + { /* 10139 */ + 224, + /* VPERMQZrmb */ + }, + { /* 10140 */ + 225, + /* VPERMQZrmbk */ + }, + { /* 10141 */ + 226, + /* VPERMQZrmbkz */ + }, + { /* 10142 */ + 227, + /* VPERMQZrmk */ + }, + { /* 10143 */ + 228, + /* VPERMQZrmkz */ + }, + { /* 10144 */ + 229, + /* VPERMQZrr */ + }, + { /* 10145 */ + 233, + /* VPERMQZrrk */ + }, + { /* 10146 */ + 234, + /* VPERMQZrrkz */ + }, + { /* 10147 */ + 202, + /* VPERMT2B128rm */ + }, + { /* 10148 */ + 203, + /* VPERMT2B128rmk */ + }, + { /* 10149 */ + 203, + /* VPERMT2B128rmkz */ + }, + { /* 10150 */ + 530, + /* VPERMT2B128rr */ + }, + { /* 10151 */ + 212, + /* VPERMT2B128rrk */ + }, + { /* 10152 */ + 212, + /* VPERMT2B128rrkz */ + }, + { /* 10153 */ + 531, + /* VPERMT2B256rm */ + }, + { /* 10154 */ + 218, + /* VPERMT2B256rmk */ + }, + { /* 10155 */ + 218, + /* VPERMT2B256rmkz */ + }, + { /* 10156 */ + 533, + /* VPERMT2B256rr */ + }, + { /* 10157 */ + 221, + /* VPERMT2B256rrk */ + }, + { /* 10158 */ + 221, + /* VPERMT2B256rrkz */ + }, + { /* 10159 */ + 534, + /* VPERMT2Brm */ + }, + { /* 10160 */ + 227, + /* VPERMT2Brmk */ + }, + { /* 10161 */ + 227, + /* VPERMT2Brmkz */ + }, + { /* 10162 */ + 536, + /* VPERMT2Brr */ + }, + { /* 10163 */ + 233, + /* VPERMT2Brrk */ + }, + { /* 10164 */ + 233, + /* VPERMT2Brrkz */ + }, + { /* 10165 */ + 202, + /* VPERMT2D128rm */ + }, + { /* 10166 */ + 540, + /* VPERMT2D128rmb */ + }, + { /* 10167 */ + 238, + /* VPERMT2D128rmbk */ + }, + { /* 10168 */ + 238, + /* VPERMT2D128rmbkz */ + }, + { /* 10169 */ + 203, + /* VPERMT2D128rmk */ + }, + { /* 10170 */ + 203, + /* VPERMT2D128rmkz */ + }, + { /* 10171 */ + 530, + /* VPERMT2D128rr */ + }, + { /* 10172 */ + 212, + /* VPERMT2D128rrk */ + }, + { /* 10173 */ + 212, + /* VPERMT2D128rrkz */ + }, + { /* 10174 */ + 531, + /* VPERMT2D256rm */ + }, + { /* 10175 */ + 541, + /* VPERMT2D256rmb */ + }, + { /* 10176 */ + 241, + /* VPERMT2D256rmbk */ + }, + { /* 10177 */ + 241, + /* VPERMT2D256rmbkz */ + }, + { /* 10178 */ + 218, + /* VPERMT2D256rmk */ + }, + { /* 10179 */ + 218, + /* VPERMT2D256rmkz */ + }, + { /* 10180 */ + 533, + /* VPERMT2D256rr */ + }, + { /* 10181 */ + 221, + /* VPERMT2D256rrk */ + }, + { /* 10182 */ + 221, + /* VPERMT2D256rrkz */ + }, + { /* 10183 */ + 534, + /* VPERMT2Drm */ + }, + { /* 10184 */ + 542, + /* VPERMT2Drmb */ + }, + { /* 10185 */ + 244, + /* VPERMT2Drmbk */ + }, + { /* 10186 */ + 244, + /* VPERMT2Drmbkz */ + }, + { /* 10187 */ + 227, + /* VPERMT2Drmk */ + }, + { /* 10188 */ + 227, + /* VPERMT2Drmkz */ + }, + { /* 10189 */ + 536, + /* VPERMT2Drr */ + }, + { /* 10190 */ + 233, + /* VPERMT2Drrk */ + }, + { /* 10191 */ + 233, + /* VPERMT2Drrkz */ + }, + { /* 10192 */ + 202, + /* VPERMT2PD128rm */ + }, + { /* 10193 */ + 529, + /* VPERMT2PD128rmb */ + }, + { /* 10194 */ + 208, + /* VPERMT2PD128rmbk */ + }, + { /* 10195 */ + 208, + /* VPERMT2PD128rmbkz */ + }, + { /* 10196 */ + 203, + /* VPERMT2PD128rmk */ + }, + { /* 10197 */ + 203, + /* VPERMT2PD128rmkz */ + }, + { /* 10198 */ + 530, + /* VPERMT2PD128rr */ + }, + { /* 10199 */ + 212, + /* VPERMT2PD128rrk */ + }, + { /* 10200 */ + 212, + /* VPERMT2PD128rrkz */ + }, + { /* 10201 */ + 531, + /* VPERMT2PD256rm */ + }, + { /* 10202 */ + 532, + /* VPERMT2PD256rmb */ + }, + { /* 10203 */ + 216, + /* VPERMT2PD256rmbk */ + }, + { /* 10204 */ + 216, + /* VPERMT2PD256rmbkz */ + }, + { /* 10205 */ + 218, + /* VPERMT2PD256rmk */ + }, + { /* 10206 */ + 218, + /* VPERMT2PD256rmkz */ + }, + { /* 10207 */ + 533, + /* VPERMT2PD256rr */ + }, + { /* 10208 */ + 221, + /* VPERMT2PD256rrk */ + }, + { /* 10209 */ + 221, + /* VPERMT2PD256rrkz */ + }, + { /* 10210 */ + 534, + /* VPERMT2PDrm */ + }, + { /* 10211 */ + 535, + /* VPERMT2PDrmb */ + }, + { /* 10212 */ + 225, + /* VPERMT2PDrmbk */ + }, + { /* 10213 */ + 225, + /* VPERMT2PDrmbkz */ + }, + { /* 10214 */ + 227, + /* VPERMT2PDrmk */ + }, + { /* 10215 */ + 227, + /* VPERMT2PDrmkz */ + }, + { /* 10216 */ + 536, + /* VPERMT2PDrr */ + }, + { /* 10217 */ + 233, + /* VPERMT2PDrrk */ + }, + { /* 10218 */ + 233, + /* VPERMT2PDrrkz */ + }, + { /* 10219 */ + 202, + /* VPERMT2PS128rm */ + }, + { /* 10220 */ + 540, + /* VPERMT2PS128rmb */ + }, + { /* 10221 */ + 238, + /* VPERMT2PS128rmbk */ + }, + { /* 10222 */ + 238, + /* VPERMT2PS128rmbkz */ + }, + { /* 10223 */ + 203, + /* VPERMT2PS128rmk */ + }, + { /* 10224 */ + 203, + /* VPERMT2PS128rmkz */ + }, + { /* 10225 */ + 530, + /* VPERMT2PS128rr */ + }, + { /* 10226 */ + 212, + /* VPERMT2PS128rrk */ + }, + { /* 10227 */ + 212, + /* VPERMT2PS128rrkz */ + }, + { /* 10228 */ + 531, + /* VPERMT2PS256rm */ + }, + { /* 10229 */ + 541, + /* VPERMT2PS256rmb */ + }, + { /* 10230 */ + 241, + /* VPERMT2PS256rmbk */ + }, + { /* 10231 */ + 241, + /* VPERMT2PS256rmbkz */ + }, + { /* 10232 */ + 218, + /* VPERMT2PS256rmk */ + }, + { /* 10233 */ + 218, + /* VPERMT2PS256rmkz */ + }, + { /* 10234 */ + 533, + /* VPERMT2PS256rr */ + }, + { /* 10235 */ + 221, + /* VPERMT2PS256rrk */ + }, + { /* 10236 */ + 221, + /* VPERMT2PS256rrkz */ + }, + { /* 10237 */ + 534, + /* VPERMT2PSrm */ + }, + { /* 10238 */ + 542, + /* VPERMT2PSrmb */ + }, + { /* 10239 */ + 244, + /* VPERMT2PSrmbk */ + }, + { /* 10240 */ + 244, + /* VPERMT2PSrmbkz */ + }, + { /* 10241 */ + 227, + /* VPERMT2PSrmk */ + }, + { /* 10242 */ + 227, + /* VPERMT2PSrmkz */ + }, + { /* 10243 */ + 536, + /* VPERMT2PSrr */ + }, + { /* 10244 */ + 233, + /* VPERMT2PSrrk */ + }, + { /* 10245 */ + 233, + /* VPERMT2PSrrkz */ + }, + { /* 10246 */ + 202, + /* VPERMT2Q128rm */ + }, + { /* 10247 */ + 529, + /* VPERMT2Q128rmb */ + }, + { /* 10248 */ + 208, + /* VPERMT2Q128rmbk */ + }, + { /* 10249 */ + 208, + /* VPERMT2Q128rmbkz */ + }, + { /* 10250 */ + 203, + /* VPERMT2Q128rmk */ + }, + { /* 10251 */ + 203, + /* VPERMT2Q128rmkz */ + }, + { /* 10252 */ + 530, + /* VPERMT2Q128rr */ + }, + { /* 10253 */ + 212, + /* VPERMT2Q128rrk */ + }, + { /* 10254 */ + 212, + /* VPERMT2Q128rrkz */ + }, + { /* 10255 */ + 531, + /* VPERMT2Q256rm */ + }, + { /* 10256 */ + 532, + /* VPERMT2Q256rmb */ + }, + { /* 10257 */ + 216, + /* VPERMT2Q256rmbk */ + }, + { /* 10258 */ + 216, + /* VPERMT2Q256rmbkz */ + }, + { /* 10259 */ + 218, + /* VPERMT2Q256rmk */ + }, + { /* 10260 */ + 218, + /* VPERMT2Q256rmkz */ + }, + { /* 10261 */ + 533, + /* VPERMT2Q256rr */ + }, + { /* 10262 */ + 221, + /* VPERMT2Q256rrk */ + }, + { /* 10263 */ + 221, + /* VPERMT2Q256rrkz */ + }, + { /* 10264 */ + 534, + /* VPERMT2Qrm */ + }, + { /* 10265 */ + 535, + /* VPERMT2Qrmb */ + }, + { /* 10266 */ + 225, + /* VPERMT2Qrmbk */ + }, + { /* 10267 */ + 225, + /* VPERMT2Qrmbkz */ + }, + { /* 10268 */ + 227, + /* VPERMT2Qrmk */ + }, + { /* 10269 */ + 227, + /* VPERMT2Qrmkz */ + }, + { /* 10270 */ + 536, + /* VPERMT2Qrr */ + }, + { /* 10271 */ + 233, + /* VPERMT2Qrrk */ + }, + { /* 10272 */ + 233, + /* VPERMT2Qrrkz */ + }, + { /* 10273 */ + 202, + /* VPERMT2W128rm */ + }, + { /* 10274 */ + 203, + /* VPERMT2W128rmk */ + }, + { /* 10275 */ + 203, + /* VPERMT2W128rmkz */ + }, + { /* 10276 */ + 530, + /* VPERMT2W128rr */ + }, + { /* 10277 */ + 212, + /* VPERMT2W128rrk */ + }, + { /* 10278 */ + 212, + /* VPERMT2W128rrkz */ + }, + { /* 10279 */ + 531, + /* VPERMT2W256rm */ + }, + { /* 10280 */ + 218, + /* VPERMT2W256rmk */ + }, + { /* 10281 */ + 218, + /* VPERMT2W256rmkz */ + }, + { /* 10282 */ + 533, + /* VPERMT2W256rr */ + }, + { /* 10283 */ + 221, + /* VPERMT2W256rrk */ + }, + { /* 10284 */ + 221, + /* VPERMT2W256rrkz */ + }, + { /* 10285 */ + 534, + /* VPERMT2Wrm */ + }, + { /* 10286 */ + 227, + /* VPERMT2Wrmk */ + }, + { /* 10287 */ + 227, + /* VPERMT2Wrmkz */ + }, + { /* 10288 */ + 536, + /* VPERMT2Wrr */ + }, + { /* 10289 */ + 233, + /* VPERMT2Wrrk */ + }, + { /* 10290 */ + 233, + /* VPERMT2Wrrkz */ + }, + { /* 10291 */ + 206, + /* VPERMWZ128rm */ + }, + { /* 10292 */ + 203, + /* VPERMWZ128rmk */ + }, + { /* 10293 */ + 210, + /* VPERMWZ128rmkz */ + }, + { /* 10294 */ + 211, + /* VPERMWZ128rr */ + }, + { /* 10295 */ + 212, + /* VPERMWZ128rrk */ + }, + { /* 10296 */ + 213, + /* VPERMWZ128rrkz */ + }, + { /* 10297 */ + 214, + /* VPERMWZ256rm */ + }, + { /* 10298 */ + 218, + /* VPERMWZ256rmk */ + }, + { /* 10299 */ + 219, + /* VPERMWZ256rmkz */ + }, + { /* 10300 */ + 220, + /* VPERMWZ256rr */ + }, + { /* 10301 */ + 221, + /* VPERMWZ256rrk */ + }, + { /* 10302 */ + 222, + /* VPERMWZ256rrkz */ + }, + { /* 10303 */ + 223, + /* VPERMWZrm */ + }, + { /* 10304 */ + 227, + /* VPERMWZrmk */ + }, + { /* 10305 */ + 228, + /* VPERMWZrmkz */ + }, + { /* 10306 */ + 229, + /* VPERMWZrr */ + }, + { /* 10307 */ + 233, + /* VPERMWZrrk */ + }, + { /* 10308 */ + 234, + /* VPERMWZrrkz */ + }, + { /* 10309 */ + 30, + /* VPEXPANDBZ128rm */ + }, + { /* 10310 */ + 688, + /* VPEXPANDBZ128rmk */ + }, + { /* 10311 */ + 689, + /* VPEXPANDBZ128rmkz */ + }, + { /* 10312 */ + 330, + /* VPEXPANDBZ128rr */ + }, + { /* 10313 */ + 331, + /* VPEXPANDBZ128rrk */ + }, + { /* 10314 */ + 332, + /* VPEXPANDBZ128rrkz */ + }, + { /* 10315 */ + 305, + /* VPEXPANDBZ256rm */ + }, + { /* 10316 */ + 690, + /* VPEXPANDBZ256rmk */ + }, + { /* 10317 */ + 691, + /* VPEXPANDBZ256rmkz */ + }, + { /* 10318 */ + 415, + /* VPEXPANDBZ256rr */ + }, + { /* 10319 */ + 416, + /* VPEXPANDBZ256rrk */ + }, + { /* 10320 */ + 417, + /* VPEXPANDBZ256rrkz */ + }, + { /* 10321 */ + 692, + /* VPEXPANDBZrm */ + }, + { /* 10322 */ + 693, + /* VPEXPANDBZrmk */ + }, + { /* 10323 */ + 694, + /* VPEXPANDBZrmkz */ + }, + { /* 10324 */ + 421, + /* VPEXPANDBZrr */ + }, + { /* 10325 */ + 425, + /* VPEXPANDBZrrk */ + }, + { /* 10326 */ + 426, + /* VPEXPANDBZrrkz */ + }, + { /* 10327 */ + 334, + /* VPEXPANDDZ128rm */ + }, + { /* 10328 */ + 335, + /* VPEXPANDDZ128rmk */ + }, + { /* 10329 */ + 336, + /* VPEXPANDDZ128rmkz */ + }, + { /* 10330 */ + 330, + /* VPEXPANDDZ128rr */ + }, + { /* 10331 */ + 331, + /* VPEXPANDDZ128rrk */ + }, + { /* 10332 */ + 332, + /* VPEXPANDDZ128rrkz */ + }, + { /* 10333 */ + 337, + /* VPEXPANDDZ256rm */ + }, + { /* 10334 */ + 338, + /* VPEXPANDDZ256rmk */ + }, + { /* 10335 */ + 339, + /* VPEXPANDDZ256rmkz */ + }, + { /* 10336 */ + 415, + /* VPEXPANDDZ256rr */ + }, + { /* 10337 */ + 416, + /* VPEXPANDDZ256rrk */ + }, + { /* 10338 */ + 417, + /* VPEXPANDDZ256rrkz */ + }, + { /* 10339 */ + 340, + /* VPEXPANDDZrm */ + }, + { /* 10340 */ + 341, + /* VPEXPANDDZrmk */ + }, + { /* 10341 */ + 342, + /* VPEXPANDDZrmkz */ + }, + { /* 10342 */ + 421, + /* VPEXPANDDZrr */ + }, + { /* 10343 */ + 425, + /* VPEXPANDDZrrk */ + }, + { /* 10344 */ + 426, + /* VPEXPANDDZrrkz */ + }, + { /* 10345 */ + 327, + /* VPEXPANDQZ128rm */ + }, + { /* 10346 */ + 328, + /* VPEXPANDQZ128rmk */ + }, + { /* 10347 */ + 329, + /* VPEXPANDQZ128rmkz */ + }, + { /* 10348 */ + 330, + /* VPEXPANDQZ128rr */ + }, + { /* 10349 */ + 331, + /* VPEXPANDQZ128rrk */ + }, + { /* 10350 */ + 332, + /* VPEXPANDQZ128rrkz */ + }, + { /* 10351 */ + 306, + /* VPEXPANDQZ256rm */ + }, + { /* 10352 */ + 307, + /* VPEXPANDQZ256rmk */ + }, + { /* 10353 */ + 308, + /* VPEXPANDQZ256rmkz */ + }, + { /* 10354 */ + 415, + /* VPEXPANDQZ256rr */ + }, + { /* 10355 */ + 416, + /* VPEXPANDQZ256rrk */ + }, + { /* 10356 */ + 417, + /* VPEXPANDQZ256rrkz */ + }, + { /* 10357 */ + 312, + /* VPEXPANDQZrm */ + }, + { /* 10358 */ + 313, + /* VPEXPANDQZrmk */ + }, + { /* 10359 */ + 314, + /* VPEXPANDQZrmkz */ + }, + { /* 10360 */ + 421, + /* VPEXPANDQZrr */ + }, + { /* 10361 */ + 425, + /* VPEXPANDQZrrk */ + }, + { /* 10362 */ + 426, + /* VPEXPANDQZrrkz */ + }, + { /* 10363 */ + 714, + /* VPEXPANDWZ128rm */ + }, + { /* 10364 */ + 715, + /* VPEXPANDWZ128rmk */ + }, + { /* 10365 */ + 716, + /* VPEXPANDWZ128rmkz */ + }, + { /* 10366 */ + 330, + /* VPEXPANDWZ128rr */ + }, + { /* 10367 */ + 331, + /* VPEXPANDWZ128rrk */ + }, + { /* 10368 */ + 332, + /* VPEXPANDWZ128rrkz */ + }, + { /* 10369 */ + 717, + /* VPEXPANDWZ256rm */ + }, + { /* 10370 */ + 718, + /* VPEXPANDWZ256rmk */ + }, + { /* 10371 */ + 719, + /* VPEXPANDWZ256rmkz */ + }, + { /* 10372 */ + 415, + /* VPEXPANDWZ256rr */ + }, + { /* 10373 */ + 416, + /* VPEXPANDWZ256rrk */ + }, + { /* 10374 */ + 417, + /* VPEXPANDWZ256rrkz */ + }, + { /* 10375 */ + 720, + /* VPEXPANDWZrm */ + }, + { /* 10376 */ + 721, + /* VPEXPANDWZrmk */ + }, + { /* 10377 */ + 722, + /* VPEXPANDWZrmkz */ + }, + { /* 10378 */ + 421, + /* VPEXPANDWZrr */ + }, + { /* 10379 */ + 425, + /* VPEXPANDWZrrk */ + }, + { /* 10380 */ + 426, + /* VPEXPANDWZrrkz */ + }, + { /* 10381 */ + 96, + /* VPEXTRBZmr */ + }, + { /* 10382 */ + 506, + /* VPEXTRBZrr */ + }, + { /* 10383 */ + 96, + /* VPEXTRBmr */ + }, + { /* 10384 */ + 97, + /* VPEXTRBrr */ + }, + { /* 10385 */ + 505, + /* VPEXTRDZmr */ + }, + { /* 10386 */ + 506, + /* VPEXTRDZrr */ + }, + { /* 10387 */ + 96, + /* VPEXTRDmr */ + }, + { /* 10388 */ + 97, + /* VPEXTRDrr */ + }, + { /* 10389 */ + 451, + /* VPEXTRQZmr */ + }, + { /* 10390 */ + 793, + /* VPEXTRQZrr */ + }, + { /* 10391 */ + 96, + /* VPEXTRQmr */ + }, + { /* 10392 */ + 180, + /* VPEXTRQrr */ + }, + { /* 10393 */ + 794, + /* VPEXTRWZmr */ + }, + { /* 10394 */ + 795, + /* VPEXTRWZrr */ + }, + { /* 10395 */ + 506, + /* VPEXTRWZrr_REV */ + }, + { /* 10396 */ + 96, + /* VPEXTRWmr */ + }, + { /* 10397 */ + 181, + /* VPEXTRWrr */ + }, + { /* 10398 */ + 97, + /* VPEXTRWrr_REV */ + }, + { /* 10399 */ + 577, + /* VPGATHERDDYrm */ + }, + { /* 10400 */ + 578, + /* VPGATHERDDZ128rm */ + }, + { /* 10401 */ + 579, + /* VPGATHERDDZ256rm */ + }, + { /* 10402 */ + 580, + /* VPGATHERDDZrm */ + }, + { /* 10403 */ + 576, + /* VPGATHERDDrm */ + }, + { /* 10404 */ + 572, + /* VPGATHERDQYrm */ + }, + { /* 10405 */ + 573, + /* VPGATHERDQZ128rm */ + }, + { /* 10406 */ + 574, + /* VPGATHERDQZ256rm */ + }, + { /* 10407 */ + 575, + /* VPGATHERDQZrm */ + }, + { /* 10408 */ + 576, + /* VPGATHERDQrm */ + }, + { /* 10409 */ + 586, + /* VPGATHERQDYrm */ + }, + { /* 10410 */ + 578, + /* VPGATHERQDZ128rm */ + }, + { /* 10411 */ + 587, + /* VPGATHERQDZ256rm */ + }, + { /* 10412 */ + 588, + /* VPGATHERQDZrm */ + }, + { /* 10413 */ + 576, + /* VPGATHERQDrm */ + }, + { /* 10414 */ + 577, + /* VPGATHERQQYrm */ + }, + { /* 10415 */ + 573, + /* VPGATHERQQZ128rm */ + }, + { /* 10416 */ + 584, + /* VPGATHERQQZ256rm */ + }, + { /* 10417 */ + 585, + /* VPGATHERQQZrm */ + }, + { /* 10418 */ + 576, + /* VPGATHERQQrm */ + }, + { /* 10419 */ + 30, + /* VPHADDBDrm */ + }, + { /* 10420 */ + 31, + /* VPHADDBDrr */ + }, + { /* 10421 */ + 30, + /* VPHADDBQrm */ + }, + { /* 10422 */ + 31, + /* VPHADDBQrr */ + }, + { /* 10423 */ + 30, + /* VPHADDBWrm */ + }, + { /* 10424 */ + 31, + /* VPHADDBWrr */ + }, + { /* 10425 */ + 30, + /* VPHADDDQrm */ + }, + { /* 10426 */ + 31, + /* VPHADDDQrr */ + }, + { /* 10427 */ + 204, + /* VPHADDDYrm */ + }, + { /* 10428 */ + 205, + /* VPHADDDYrr */ + }, + { /* 10429 */ + 235, + /* VPHADDDrm */ + }, + { /* 10430 */ + 236, + /* VPHADDDrr */ + }, + { /* 10431 */ + 204, + /* VPHADDSWYrm */ + }, + { /* 10432 */ + 205, + /* VPHADDSWYrr */ + }, + { /* 10433 */ + 235, + /* VPHADDSWrm */ + }, + { /* 10434 */ + 236, + /* VPHADDSWrr */ + }, + { /* 10435 */ + 30, + /* VPHADDUBDrm */ + }, + { /* 10436 */ + 31, + /* VPHADDUBDrr */ + }, + { /* 10437 */ + 30, + /* VPHADDUBQrm */ + }, + { /* 10438 */ + 31, + /* VPHADDUBQrr */ + }, + { /* 10439 */ + 30, + /* VPHADDUBWrm */ + }, + { /* 10440 */ + 31, + /* VPHADDUBWrr */ + }, + { /* 10441 */ + 30, + /* VPHADDUDQrm */ + }, + { /* 10442 */ + 31, + /* VPHADDUDQrr */ + }, + { /* 10443 */ + 30, + /* VPHADDUWDrm */ + }, + { /* 10444 */ + 31, + /* VPHADDUWDrr */ + }, + { /* 10445 */ + 30, + /* VPHADDUWQrm */ + }, + { /* 10446 */ + 31, + /* VPHADDUWQrr */ + }, + { /* 10447 */ + 30, + /* VPHADDWDrm */ + }, + { /* 10448 */ + 31, + /* VPHADDWDrr */ + }, + { /* 10449 */ + 30, + /* VPHADDWQrm */ + }, + { /* 10450 */ + 31, + /* VPHADDWQrr */ + }, + { /* 10451 */ + 204, + /* VPHADDWYrm */ + }, + { /* 10452 */ + 205, + /* VPHADDWYrr */ + }, + { /* 10453 */ + 235, + /* VPHADDWrm */ + }, + { /* 10454 */ + 236, + /* VPHADDWrr */ + }, + { /* 10455 */ + 30, + /* VPHMINPOSUWrm */ + }, + { /* 10456 */ + 31, + /* VPHMINPOSUWrr */ + }, + { /* 10457 */ + 30, + /* VPHSUBBWrm */ + }, + { /* 10458 */ + 31, + /* VPHSUBBWrr */ + }, + { /* 10459 */ + 30, + /* VPHSUBDQrm */ + }, + { /* 10460 */ + 31, + /* VPHSUBDQrr */ + }, + { /* 10461 */ + 204, + /* VPHSUBDYrm */ + }, + { /* 10462 */ + 205, + /* VPHSUBDYrr */ + }, + { /* 10463 */ + 235, + /* VPHSUBDrm */ + }, + { /* 10464 */ + 236, + /* VPHSUBDrr */ + }, + { /* 10465 */ + 204, + /* VPHSUBSWYrm */ + }, + { /* 10466 */ + 205, + /* VPHSUBSWYrr */ + }, + { /* 10467 */ + 235, + /* VPHSUBSWrm */ + }, + { /* 10468 */ + 236, + /* VPHSUBSWrr */ + }, + { /* 10469 */ + 30, + /* VPHSUBWDrm */ + }, + { /* 10470 */ + 31, + /* VPHSUBWDrr */ + }, + { /* 10471 */ + 204, + /* VPHSUBWYrm */ + }, + { /* 10472 */ + 205, + /* VPHSUBWYrr */ + }, + { /* 10473 */ + 235, + /* VPHSUBWrm */ + }, + { /* 10474 */ + 236, + /* VPHSUBWrr */ + }, + { /* 10475 */ + 299, + /* VPINSRBZrm */ + }, + { /* 10476 */ + 796, + /* VPINSRBZrr */ + }, + { /* 10477 */ + 299, + /* VPINSRBrm */ + }, + { /* 10478 */ + 797, + /* VPINSRBrr */ + }, + { /* 10479 */ + 261, + /* VPINSRDZrm */ + }, + { /* 10480 */ + 796, + /* VPINSRDZrr */ + }, + { /* 10481 */ + 299, + /* VPINSRDrm */ + }, + { /* 10482 */ + 797, + /* VPINSRDrr */ + }, + { /* 10483 */ + 288, + /* VPINSRQZrm */ + }, + { /* 10484 */ + 798, + /* VPINSRQZrr */ + }, + { /* 10485 */ + 299, + /* VPINSRQrm */ + }, + { /* 10486 */ + 799, + /* VPINSRQrr */ + }, + { /* 10487 */ + 800, + /* VPINSRWZrm */ + }, + { /* 10488 */ + 796, + /* VPINSRWZrr */ + }, + { /* 10489 */ + 299, + /* VPINSRWrm */ + }, + { /* 10490 */ + 797, + /* VPINSRWrr */ + }, + { /* 10491 */ + 409, + /* VPLZCNTDZ128rm */ + }, + { /* 10492 */ + 334, + /* VPLZCNTDZ128rmb */ + }, + { /* 10493 */ + 335, + /* VPLZCNTDZ128rmbk */ + }, + { /* 10494 */ + 336, + /* VPLZCNTDZ128rmbkz */ + }, + { /* 10495 */ + 410, + /* VPLZCNTDZ128rmk */ + }, + { /* 10496 */ + 411, + /* VPLZCNTDZ128rmkz */ + }, + { /* 10497 */ + 330, + /* VPLZCNTDZ128rr */ + }, + { /* 10498 */ + 331, + /* VPLZCNTDZ128rrk */ + }, + { /* 10499 */ + 332, + /* VPLZCNTDZ128rrkz */ + }, + { /* 10500 */ + 412, + /* VPLZCNTDZ256rm */ + }, + { /* 10501 */ + 337, + /* VPLZCNTDZ256rmb */ + }, + { /* 10502 */ + 338, + /* VPLZCNTDZ256rmbk */ + }, + { /* 10503 */ + 339, + /* VPLZCNTDZ256rmbkz */ + }, + { /* 10504 */ + 413, + /* VPLZCNTDZ256rmk */ + }, + { /* 10505 */ + 414, + /* VPLZCNTDZ256rmkz */ + }, + { /* 10506 */ + 415, + /* VPLZCNTDZ256rr */ + }, + { /* 10507 */ + 416, + /* VPLZCNTDZ256rrk */ + }, + { /* 10508 */ + 417, + /* VPLZCNTDZ256rrkz */ + }, + { /* 10509 */ + 418, + /* VPLZCNTDZrm */ + }, + { /* 10510 */ + 340, + /* VPLZCNTDZrmb */ + }, + { /* 10511 */ + 341, + /* VPLZCNTDZrmbk */ + }, + { /* 10512 */ + 342, + /* VPLZCNTDZrmbkz */ + }, + { /* 10513 */ + 419, + /* VPLZCNTDZrmk */ + }, + { /* 10514 */ + 420, + /* VPLZCNTDZrmkz */ + }, + { /* 10515 */ + 421, + /* VPLZCNTDZrr */ + }, + { /* 10516 */ + 425, + /* VPLZCNTDZrrk */ + }, + { /* 10517 */ + 426, + /* VPLZCNTDZrrkz */ + }, + { /* 10518 */ + 409, + /* VPLZCNTQZ128rm */ + }, + { /* 10519 */ + 327, + /* VPLZCNTQZ128rmb */ + }, + { /* 10520 */ + 328, + /* VPLZCNTQZ128rmbk */ + }, + { /* 10521 */ + 329, + /* VPLZCNTQZ128rmbkz */ + }, + { /* 10522 */ + 410, + /* VPLZCNTQZ128rmk */ + }, + { /* 10523 */ + 411, + /* VPLZCNTQZ128rmkz */ + }, + { /* 10524 */ + 330, + /* VPLZCNTQZ128rr */ + }, + { /* 10525 */ + 331, + /* VPLZCNTQZ128rrk */ + }, + { /* 10526 */ + 332, + /* VPLZCNTQZ128rrkz */ + }, + { /* 10527 */ + 412, + /* VPLZCNTQZ256rm */ + }, + { /* 10528 */ + 306, + /* VPLZCNTQZ256rmb */ + }, + { /* 10529 */ + 307, + /* VPLZCNTQZ256rmbk */ + }, + { /* 10530 */ + 308, + /* VPLZCNTQZ256rmbkz */ + }, + { /* 10531 */ + 413, + /* VPLZCNTQZ256rmk */ + }, + { /* 10532 */ + 414, + /* VPLZCNTQZ256rmkz */ + }, + { /* 10533 */ + 415, + /* VPLZCNTQZ256rr */ + }, + { /* 10534 */ + 416, + /* VPLZCNTQZ256rrk */ + }, + { /* 10535 */ + 417, + /* VPLZCNTQZ256rrkz */ + }, + { /* 10536 */ + 418, + /* VPLZCNTQZrm */ + }, + { /* 10537 */ + 312, + /* VPLZCNTQZrmb */ + }, + { /* 10538 */ + 313, + /* VPLZCNTQZrmbk */ + }, + { /* 10539 */ + 314, + /* VPLZCNTQZrmbkz */ + }, + { /* 10540 */ + 419, + /* VPLZCNTQZrmk */ + }, + { /* 10541 */ + 420, + /* VPLZCNTQZrmkz */ + }, + { /* 10542 */ + 421, + /* VPLZCNTQZrr */ + }, + { /* 10543 */ + 425, + /* VPLZCNTQZrrk */ + }, + { /* 10544 */ + 426, + /* VPLZCNTQZrrkz */ + }, + { /* 10545 */ + 303, + /* VPMACSDDrm */ + }, + { /* 10546 */ + 304, + /* VPMACSDDrr */ + }, + { /* 10547 */ + 303, + /* VPMACSDQHrm */ + }, + { /* 10548 */ + 304, + /* VPMACSDQHrr */ + }, + { /* 10549 */ + 303, + /* VPMACSDQLrm */ + }, + { /* 10550 */ + 304, + /* VPMACSDQLrr */ + }, + { /* 10551 */ + 303, + /* VPMACSSDDrm */ + }, + { /* 10552 */ + 304, + /* VPMACSSDDrr */ + }, + { /* 10553 */ + 303, + /* VPMACSSDQHrm */ + }, + { /* 10554 */ + 304, + /* VPMACSSDQHrr */ + }, + { /* 10555 */ + 303, + /* VPMACSSDQLrm */ + }, + { /* 10556 */ + 304, + /* VPMACSSDQLrr */ + }, + { /* 10557 */ + 303, + /* VPMACSSWDrm */ + }, + { /* 10558 */ + 304, + /* VPMACSSWDrr */ + }, + { /* 10559 */ + 303, + /* VPMACSSWWrm */ + }, + { /* 10560 */ + 304, + /* VPMACSSWWrr */ + }, + { /* 10561 */ + 303, + /* VPMACSWDrm */ + }, + { /* 10562 */ + 304, + /* VPMACSWDrr */ + }, + { /* 10563 */ + 303, + /* VPMACSWWrm */ + }, + { /* 10564 */ + 304, + /* VPMACSWWrr */ + }, + { /* 10565 */ + 303, + /* VPMADCSSWDrm */ + }, + { /* 10566 */ + 304, + /* VPMADCSSWDrr */ + }, + { /* 10567 */ + 303, + /* VPMADCSWDrm */ + }, + { /* 10568 */ + 304, + /* VPMADCSWDrr */ + }, + { /* 10569 */ + 202, + /* VPMADD52HUQZ128m */ + }, + { /* 10570 */ + 529, + /* VPMADD52HUQZ128mb */ + }, + { /* 10571 */ + 208, + /* VPMADD52HUQZ128mbk */ + }, + { /* 10572 */ + 208, + /* VPMADD52HUQZ128mbkz */ + }, + { /* 10573 */ + 203, + /* VPMADD52HUQZ128mk */ + }, + { /* 10574 */ + 203, + /* VPMADD52HUQZ128mkz */ + }, + { /* 10575 */ + 530, + /* VPMADD52HUQZ128r */ + }, + { /* 10576 */ + 212, + /* VPMADD52HUQZ128rk */ + }, + { /* 10577 */ + 212, + /* VPMADD52HUQZ128rkz */ + }, + { /* 10578 */ + 531, + /* VPMADD52HUQZ256m */ + }, + { /* 10579 */ + 532, + /* VPMADD52HUQZ256mb */ + }, + { /* 10580 */ + 216, + /* VPMADD52HUQZ256mbk */ + }, + { /* 10581 */ + 216, + /* VPMADD52HUQZ256mbkz */ + }, + { /* 10582 */ + 218, + /* VPMADD52HUQZ256mk */ + }, + { /* 10583 */ + 218, + /* VPMADD52HUQZ256mkz */ + }, + { /* 10584 */ + 533, + /* VPMADD52HUQZ256r */ + }, + { /* 10585 */ + 221, + /* VPMADD52HUQZ256rk */ + }, + { /* 10586 */ + 221, + /* VPMADD52HUQZ256rkz */ + }, + { /* 10587 */ + 534, + /* VPMADD52HUQZm */ + }, + { /* 10588 */ + 535, + /* VPMADD52HUQZmb */ + }, + { /* 10589 */ + 225, + /* VPMADD52HUQZmbk */ + }, + { /* 10590 */ + 225, + /* VPMADD52HUQZmbkz */ + }, + { /* 10591 */ + 227, + /* VPMADD52HUQZmk */ + }, + { /* 10592 */ + 227, + /* VPMADD52HUQZmkz */ + }, + { /* 10593 */ + 536, + /* VPMADD52HUQZr */ + }, + { /* 10594 */ + 233, + /* VPMADD52HUQZrk */ + }, + { /* 10595 */ + 233, + /* VPMADD52HUQZrkz */ + }, + { /* 10596 */ + 202, + /* VPMADD52LUQZ128m */ + }, + { /* 10597 */ + 529, + /* VPMADD52LUQZ128mb */ + }, + { /* 10598 */ + 208, + /* VPMADD52LUQZ128mbk */ + }, + { /* 10599 */ + 208, + /* VPMADD52LUQZ128mbkz */ + }, + { /* 10600 */ + 203, + /* VPMADD52LUQZ128mk */ + }, + { /* 10601 */ + 203, + /* VPMADD52LUQZ128mkz */ + }, + { /* 10602 */ + 530, + /* VPMADD52LUQZ128r */ + }, + { /* 10603 */ + 212, + /* VPMADD52LUQZ128rk */ + }, + { /* 10604 */ + 212, + /* VPMADD52LUQZ128rkz */ + }, + { /* 10605 */ + 531, + /* VPMADD52LUQZ256m */ + }, + { /* 10606 */ + 532, + /* VPMADD52LUQZ256mb */ + }, + { /* 10607 */ + 216, + /* VPMADD52LUQZ256mbk */ + }, + { /* 10608 */ + 216, + /* VPMADD52LUQZ256mbkz */ + }, + { /* 10609 */ + 218, + /* VPMADD52LUQZ256mk */ + }, + { /* 10610 */ + 218, + /* VPMADD52LUQZ256mkz */ + }, + { /* 10611 */ + 533, + /* VPMADD52LUQZ256r */ + }, + { /* 10612 */ + 221, + /* VPMADD52LUQZ256rk */ + }, + { /* 10613 */ + 221, + /* VPMADD52LUQZ256rkz */ + }, + { /* 10614 */ + 534, + /* VPMADD52LUQZm */ + }, + { /* 10615 */ + 535, + /* VPMADD52LUQZmb */ + }, + { /* 10616 */ + 225, + /* VPMADD52LUQZmbk */ + }, + { /* 10617 */ + 225, + /* VPMADD52LUQZmbkz */ + }, + { /* 10618 */ + 227, + /* VPMADD52LUQZmk */ + }, + { /* 10619 */ + 227, + /* VPMADD52LUQZmkz */ + }, + { /* 10620 */ + 536, + /* VPMADD52LUQZr */ + }, + { /* 10621 */ + 233, + /* VPMADD52LUQZrk */ + }, + { /* 10622 */ + 233, + /* VPMADD52LUQZrkz */ + }, + { /* 10623 */ + 204, + /* VPMADDUBSWYrm */ + }, + { /* 10624 */ + 205, + /* VPMADDUBSWYrr */ + }, + { /* 10625 */ + 206, + /* VPMADDUBSWZ128rm */ + }, + { /* 10626 */ + 203, + /* VPMADDUBSWZ128rmk */ + }, + { /* 10627 */ + 210, + /* VPMADDUBSWZ128rmkz */ + }, + { /* 10628 */ + 211, + /* VPMADDUBSWZ128rr */ + }, + { /* 10629 */ + 212, + /* VPMADDUBSWZ128rrk */ + }, + { /* 10630 */ + 213, + /* VPMADDUBSWZ128rrkz */ + }, + { /* 10631 */ + 214, + /* VPMADDUBSWZ256rm */ + }, + { /* 10632 */ + 218, + /* VPMADDUBSWZ256rmk */ + }, + { /* 10633 */ + 219, + /* VPMADDUBSWZ256rmkz */ + }, + { /* 10634 */ + 220, + /* VPMADDUBSWZ256rr */ + }, + { /* 10635 */ + 221, + /* VPMADDUBSWZ256rrk */ + }, + { /* 10636 */ + 222, + /* VPMADDUBSWZ256rrkz */ + }, + { /* 10637 */ + 223, + /* VPMADDUBSWZrm */ + }, + { /* 10638 */ + 227, + /* VPMADDUBSWZrmk */ + }, + { /* 10639 */ + 228, + /* VPMADDUBSWZrmkz */ + }, + { /* 10640 */ + 229, + /* VPMADDUBSWZrr */ + }, + { /* 10641 */ + 233, + /* VPMADDUBSWZrrk */ + }, + { /* 10642 */ + 234, + /* VPMADDUBSWZrrkz */ + }, + { /* 10643 */ + 235, + /* VPMADDUBSWrm */ + }, + { /* 10644 */ + 236, + /* VPMADDUBSWrr */ + }, + { /* 10645 */ + 204, + /* VPMADDWDYrm */ + }, + { /* 10646 */ + 205, + /* VPMADDWDYrr */ + }, + { /* 10647 */ + 206, + /* VPMADDWDZ128rm */ + }, + { /* 10648 */ + 203, + /* VPMADDWDZ128rmk */ + }, + { /* 10649 */ + 210, + /* VPMADDWDZ128rmkz */ + }, + { /* 10650 */ + 211, + /* VPMADDWDZ128rr */ + }, + { /* 10651 */ + 212, + /* VPMADDWDZ128rrk */ + }, + { /* 10652 */ + 213, + /* VPMADDWDZ128rrkz */ + }, + { /* 10653 */ + 214, + /* VPMADDWDZ256rm */ + }, + { /* 10654 */ + 218, + /* VPMADDWDZ256rmk */ + }, + { /* 10655 */ + 219, + /* VPMADDWDZ256rmkz */ + }, + { /* 10656 */ + 220, + /* VPMADDWDZ256rr */ + }, + { /* 10657 */ + 221, + /* VPMADDWDZ256rrk */ + }, + { /* 10658 */ + 222, + /* VPMADDWDZ256rrkz */ + }, + { /* 10659 */ + 223, + /* VPMADDWDZrm */ + }, + { /* 10660 */ + 227, + /* VPMADDWDZrmk */ + }, + { /* 10661 */ + 228, + /* VPMADDWDZrmkz */ + }, + { /* 10662 */ + 229, + /* VPMADDWDZrr */ + }, + { /* 10663 */ + 233, + /* VPMADDWDZrrk */ + }, + { /* 10664 */ + 234, + /* VPMADDWDZrrkz */ + }, + { /* 10665 */ + 235, + /* VPMADDWDrm */ + }, + { /* 10666 */ + 236, + /* VPMADDWDrr */ + }, + { /* 10667 */ + 661, + /* VPMASKMOVDYmr */ + }, + { /* 10668 */ + 204, + /* VPMASKMOVDYrm */ + }, + { /* 10669 */ + 662, + /* VPMASKMOVDmr */ + }, + { /* 10670 */ + 235, + /* VPMASKMOVDrm */ + }, + { /* 10671 */ + 661, + /* VPMASKMOVQYmr */ + }, + { /* 10672 */ + 204, + /* VPMASKMOVQYrm */ + }, + { /* 10673 */ + 662, + /* VPMASKMOVQmr */ + }, + { /* 10674 */ + 235, + /* VPMASKMOVQrm */ + }, + { /* 10675 */ + 204, + /* VPMAXSBYrm */ + }, + { /* 10676 */ + 205, + /* VPMAXSBYrr */ + }, + { /* 10677 */ + 206, + /* VPMAXSBZ128rm */ + }, + { /* 10678 */ + 203, + /* VPMAXSBZ128rmk */ + }, + { /* 10679 */ + 210, + /* VPMAXSBZ128rmkz */ + }, + { /* 10680 */ + 211, + /* VPMAXSBZ128rr */ + }, + { /* 10681 */ + 212, + /* VPMAXSBZ128rrk */ + }, + { /* 10682 */ + 213, + /* VPMAXSBZ128rrkz */ + }, + { /* 10683 */ + 214, + /* VPMAXSBZ256rm */ + }, + { /* 10684 */ + 218, + /* VPMAXSBZ256rmk */ + }, + { /* 10685 */ + 219, + /* VPMAXSBZ256rmkz */ + }, + { /* 10686 */ + 220, + /* VPMAXSBZ256rr */ + }, + { /* 10687 */ + 221, + /* VPMAXSBZ256rrk */ + }, + { /* 10688 */ + 222, + /* VPMAXSBZ256rrkz */ + }, + { /* 10689 */ + 223, + /* VPMAXSBZrm */ + }, + { /* 10690 */ + 227, + /* VPMAXSBZrmk */ + }, + { /* 10691 */ + 228, + /* VPMAXSBZrmkz */ + }, + { /* 10692 */ + 229, + /* VPMAXSBZrr */ + }, + { /* 10693 */ + 233, + /* VPMAXSBZrrk */ + }, + { /* 10694 */ + 234, + /* VPMAXSBZrrkz */ + }, + { /* 10695 */ + 235, + /* VPMAXSBrm */ + }, + { /* 10696 */ + 236, + /* VPMAXSBrr */ + }, + { /* 10697 */ + 204, + /* VPMAXSDYrm */ + }, + { /* 10698 */ + 205, + /* VPMAXSDYrr */ + }, + { /* 10699 */ + 206, + /* VPMAXSDZ128rm */ + }, + { /* 10700 */ + 237, + /* VPMAXSDZ128rmb */ + }, + { /* 10701 */ + 238, + /* VPMAXSDZ128rmbk */ + }, + { /* 10702 */ + 239, + /* VPMAXSDZ128rmbkz */ + }, + { /* 10703 */ + 203, + /* VPMAXSDZ128rmk */ + }, + { /* 10704 */ + 210, + /* VPMAXSDZ128rmkz */ + }, + { /* 10705 */ + 211, + /* VPMAXSDZ128rr */ + }, + { /* 10706 */ + 212, + /* VPMAXSDZ128rrk */ + }, + { /* 10707 */ + 213, + /* VPMAXSDZ128rrkz */ + }, + { /* 10708 */ + 214, + /* VPMAXSDZ256rm */ + }, + { /* 10709 */ + 240, + /* VPMAXSDZ256rmb */ + }, + { /* 10710 */ + 241, + /* VPMAXSDZ256rmbk */ + }, + { /* 10711 */ + 242, + /* VPMAXSDZ256rmbkz */ + }, + { /* 10712 */ + 218, + /* VPMAXSDZ256rmk */ + }, + { /* 10713 */ + 219, + /* VPMAXSDZ256rmkz */ + }, + { /* 10714 */ + 220, + /* VPMAXSDZ256rr */ + }, + { /* 10715 */ + 221, + /* VPMAXSDZ256rrk */ + }, + { /* 10716 */ + 222, + /* VPMAXSDZ256rrkz */ + }, + { /* 10717 */ + 223, + /* VPMAXSDZrm */ + }, + { /* 10718 */ + 243, + /* VPMAXSDZrmb */ + }, + { /* 10719 */ + 244, + /* VPMAXSDZrmbk */ + }, + { /* 10720 */ + 245, + /* VPMAXSDZrmbkz */ + }, + { /* 10721 */ + 227, + /* VPMAXSDZrmk */ + }, + { /* 10722 */ + 228, + /* VPMAXSDZrmkz */ + }, + { /* 10723 */ + 229, + /* VPMAXSDZrr */ + }, + { /* 10724 */ + 233, + /* VPMAXSDZrrk */ + }, + { /* 10725 */ + 234, + /* VPMAXSDZrrkz */ + }, + { /* 10726 */ + 235, + /* VPMAXSDrm */ + }, + { /* 10727 */ + 236, + /* VPMAXSDrr */ + }, + { /* 10728 */ + 206, + /* VPMAXSQZ128rm */ + }, + { /* 10729 */ + 207, + /* VPMAXSQZ128rmb */ + }, + { /* 10730 */ + 208, + /* VPMAXSQZ128rmbk */ + }, + { /* 10731 */ + 209, + /* VPMAXSQZ128rmbkz */ + }, + { /* 10732 */ + 203, + /* VPMAXSQZ128rmk */ + }, + { /* 10733 */ + 210, + /* VPMAXSQZ128rmkz */ + }, + { /* 10734 */ + 211, + /* VPMAXSQZ128rr */ + }, + { /* 10735 */ + 212, + /* VPMAXSQZ128rrk */ + }, + { /* 10736 */ + 213, + /* VPMAXSQZ128rrkz */ + }, + { /* 10737 */ + 214, + /* VPMAXSQZ256rm */ + }, + { /* 10738 */ + 215, + /* VPMAXSQZ256rmb */ + }, + { /* 10739 */ + 216, + /* VPMAXSQZ256rmbk */ + }, + { /* 10740 */ + 217, + /* VPMAXSQZ256rmbkz */ + }, + { /* 10741 */ + 218, + /* VPMAXSQZ256rmk */ + }, + { /* 10742 */ + 219, + /* VPMAXSQZ256rmkz */ + }, + { /* 10743 */ + 220, + /* VPMAXSQZ256rr */ + }, + { /* 10744 */ + 221, + /* VPMAXSQZ256rrk */ + }, + { /* 10745 */ + 222, + /* VPMAXSQZ256rrkz */ + }, + { /* 10746 */ + 223, + /* VPMAXSQZrm */ + }, + { /* 10747 */ + 224, + /* VPMAXSQZrmb */ + }, + { /* 10748 */ + 225, + /* VPMAXSQZrmbk */ + }, + { /* 10749 */ + 226, + /* VPMAXSQZrmbkz */ + }, + { /* 10750 */ + 227, + /* VPMAXSQZrmk */ + }, + { /* 10751 */ + 228, + /* VPMAXSQZrmkz */ + }, + { /* 10752 */ + 229, + /* VPMAXSQZrr */ + }, + { /* 10753 */ + 233, + /* VPMAXSQZrrk */ + }, + { /* 10754 */ + 234, + /* VPMAXSQZrrkz */ + }, + { /* 10755 */ + 204, + /* VPMAXSWYrm */ + }, + { /* 10756 */ + 205, + /* VPMAXSWYrr */ + }, + { /* 10757 */ + 206, + /* VPMAXSWZ128rm */ + }, + { /* 10758 */ + 203, + /* VPMAXSWZ128rmk */ + }, + { /* 10759 */ + 210, + /* VPMAXSWZ128rmkz */ + }, + { /* 10760 */ + 211, + /* VPMAXSWZ128rr */ + }, + { /* 10761 */ + 212, + /* VPMAXSWZ128rrk */ + }, + { /* 10762 */ + 213, + /* VPMAXSWZ128rrkz */ + }, + { /* 10763 */ + 214, + /* VPMAXSWZ256rm */ + }, + { /* 10764 */ + 218, + /* VPMAXSWZ256rmk */ + }, + { /* 10765 */ + 219, + /* VPMAXSWZ256rmkz */ + }, + { /* 10766 */ + 220, + /* VPMAXSWZ256rr */ + }, + { /* 10767 */ + 221, + /* VPMAXSWZ256rrk */ + }, + { /* 10768 */ + 222, + /* VPMAXSWZ256rrkz */ + }, + { /* 10769 */ + 223, + /* VPMAXSWZrm */ + }, + { /* 10770 */ + 227, + /* VPMAXSWZrmk */ + }, + { /* 10771 */ + 228, + /* VPMAXSWZrmkz */ + }, + { /* 10772 */ + 229, + /* VPMAXSWZrr */ + }, + { /* 10773 */ + 233, + /* VPMAXSWZrrk */ + }, + { /* 10774 */ + 234, + /* VPMAXSWZrrkz */ + }, + { /* 10775 */ + 235, + /* VPMAXSWrm */ + }, + { /* 10776 */ + 236, + /* VPMAXSWrr */ + }, + { /* 10777 */ + 204, + /* VPMAXUBYrm */ + }, + { /* 10778 */ + 205, + /* VPMAXUBYrr */ + }, + { /* 10779 */ + 206, + /* VPMAXUBZ128rm */ + }, + { /* 10780 */ + 203, + /* VPMAXUBZ128rmk */ + }, + { /* 10781 */ + 210, + /* VPMAXUBZ128rmkz */ + }, + { /* 10782 */ + 211, + /* VPMAXUBZ128rr */ + }, + { /* 10783 */ + 212, + /* VPMAXUBZ128rrk */ + }, + { /* 10784 */ + 213, + /* VPMAXUBZ128rrkz */ + }, + { /* 10785 */ + 214, + /* VPMAXUBZ256rm */ + }, + { /* 10786 */ + 218, + /* VPMAXUBZ256rmk */ + }, + { /* 10787 */ + 219, + /* VPMAXUBZ256rmkz */ + }, + { /* 10788 */ + 220, + /* VPMAXUBZ256rr */ + }, + { /* 10789 */ + 221, + /* VPMAXUBZ256rrk */ + }, + { /* 10790 */ + 222, + /* VPMAXUBZ256rrkz */ + }, + { /* 10791 */ + 223, + /* VPMAXUBZrm */ + }, + { /* 10792 */ + 227, + /* VPMAXUBZrmk */ + }, + { /* 10793 */ + 228, + /* VPMAXUBZrmkz */ + }, + { /* 10794 */ + 229, + /* VPMAXUBZrr */ + }, + { /* 10795 */ + 233, + /* VPMAXUBZrrk */ + }, + { /* 10796 */ + 234, + /* VPMAXUBZrrkz */ + }, + { /* 10797 */ + 235, + /* VPMAXUBrm */ + }, + { /* 10798 */ + 236, + /* VPMAXUBrr */ + }, + { /* 10799 */ + 204, + /* VPMAXUDYrm */ + }, + { /* 10800 */ + 205, + /* VPMAXUDYrr */ + }, + { /* 10801 */ + 206, + /* VPMAXUDZ128rm */ + }, + { /* 10802 */ + 237, + /* VPMAXUDZ128rmb */ + }, + { /* 10803 */ + 238, + /* VPMAXUDZ128rmbk */ + }, + { /* 10804 */ + 239, + /* VPMAXUDZ128rmbkz */ + }, + { /* 10805 */ + 203, + /* VPMAXUDZ128rmk */ + }, + { /* 10806 */ + 210, + /* VPMAXUDZ128rmkz */ + }, + { /* 10807 */ + 211, + /* VPMAXUDZ128rr */ + }, + { /* 10808 */ + 212, + /* VPMAXUDZ128rrk */ + }, + { /* 10809 */ + 213, + /* VPMAXUDZ128rrkz */ + }, + { /* 10810 */ + 214, + /* VPMAXUDZ256rm */ + }, + { /* 10811 */ + 240, + /* VPMAXUDZ256rmb */ + }, + { /* 10812 */ + 241, + /* VPMAXUDZ256rmbk */ + }, + { /* 10813 */ + 242, + /* VPMAXUDZ256rmbkz */ + }, + { /* 10814 */ + 218, + /* VPMAXUDZ256rmk */ + }, + { /* 10815 */ + 219, + /* VPMAXUDZ256rmkz */ + }, + { /* 10816 */ + 220, + /* VPMAXUDZ256rr */ + }, + { /* 10817 */ + 221, + /* VPMAXUDZ256rrk */ + }, + { /* 10818 */ + 222, + /* VPMAXUDZ256rrkz */ + }, + { /* 10819 */ + 223, + /* VPMAXUDZrm */ + }, + { /* 10820 */ + 243, + /* VPMAXUDZrmb */ + }, + { /* 10821 */ + 244, + /* VPMAXUDZrmbk */ + }, + { /* 10822 */ + 245, + /* VPMAXUDZrmbkz */ + }, + { /* 10823 */ + 227, + /* VPMAXUDZrmk */ + }, + { /* 10824 */ + 228, + /* VPMAXUDZrmkz */ + }, + { /* 10825 */ + 229, + /* VPMAXUDZrr */ + }, + { /* 10826 */ + 233, + /* VPMAXUDZrrk */ + }, + { /* 10827 */ + 234, + /* VPMAXUDZrrkz */ + }, + { /* 10828 */ + 235, + /* VPMAXUDrm */ + }, + { /* 10829 */ + 236, + /* VPMAXUDrr */ + }, + { /* 10830 */ + 206, + /* VPMAXUQZ128rm */ + }, + { /* 10831 */ + 207, + /* VPMAXUQZ128rmb */ + }, + { /* 10832 */ + 208, + /* VPMAXUQZ128rmbk */ + }, + { /* 10833 */ + 209, + /* VPMAXUQZ128rmbkz */ + }, + { /* 10834 */ + 203, + /* VPMAXUQZ128rmk */ + }, + { /* 10835 */ + 210, + /* VPMAXUQZ128rmkz */ + }, + { /* 10836 */ + 211, + /* VPMAXUQZ128rr */ + }, + { /* 10837 */ + 212, + /* VPMAXUQZ128rrk */ + }, + { /* 10838 */ + 213, + /* VPMAXUQZ128rrkz */ + }, + { /* 10839 */ + 214, + /* VPMAXUQZ256rm */ + }, + { /* 10840 */ + 215, + /* VPMAXUQZ256rmb */ + }, + { /* 10841 */ + 216, + /* VPMAXUQZ256rmbk */ + }, + { /* 10842 */ + 217, + /* VPMAXUQZ256rmbkz */ + }, + { /* 10843 */ + 218, + /* VPMAXUQZ256rmk */ + }, + { /* 10844 */ + 219, + /* VPMAXUQZ256rmkz */ + }, + { /* 10845 */ + 220, + /* VPMAXUQZ256rr */ + }, + { /* 10846 */ + 221, + /* VPMAXUQZ256rrk */ + }, + { /* 10847 */ + 222, + /* VPMAXUQZ256rrkz */ + }, + { /* 10848 */ + 223, + /* VPMAXUQZrm */ + }, + { /* 10849 */ + 224, + /* VPMAXUQZrmb */ + }, + { /* 10850 */ + 225, + /* VPMAXUQZrmbk */ + }, + { /* 10851 */ + 226, + /* VPMAXUQZrmbkz */ + }, + { /* 10852 */ + 227, + /* VPMAXUQZrmk */ + }, + { /* 10853 */ + 228, + /* VPMAXUQZrmkz */ + }, + { /* 10854 */ + 229, + /* VPMAXUQZrr */ + }, + { /* 10855 */ + 233, + /* VPMAXUQZrrk */ + }, + { /* 10856 */ + 234, + /* VPMAXUQZrrkz */ + }, + { /* 10857 */ + 204, + /* VPMAXUWYrm */ + }, + { /* 10858 */ + 205, + /* VPMAXUWYrr */ + }, + { /* 10859 */ + 206, + /* VPMAXUWZ128rm */ + }, + { /* 10860 */ + 203, + /* VPMAXUWZ128rmk */ + }, + { /* 10861 */ + 210, + /* VPMAXUWZ128rmkz */ + }, + { /* 10862 */ + 211, + /* VPMAXUWZ128rr */ + }, + { /* 10863 */ + 212, + /* VPMAXUWZ128rrk */ + }, + { /* 10864 */ + 213, + /* VPMAXUWZ128rrkz */ + }, + { /* 10865 */ + 214, + /* VPMAXUWZ256rm */ + }, + { /* 10866 */ + 218, + /* VPMAXUWZ256rmk */ + }, + { /* 10867 */ + 219, + /* VPMAXUWZ256rmkz */ + }, + { /* 10868 */ + 220, + /* VPMAXUWZ256rr */ + }, + { /* 10869 */ + 221, + /* VPMAXUWZ256rrk */ + }, + { /* 10870 */ + 222, + /* VPMAXUWZ256rrkz */ + }, + { /* 10871 */ + 223, + /* VPMAXUWZrm */ + }, + { /* 10872 */ + 227, + /* VPMAXUWZrmk */ + }, + { /* 10873 */ + 228, + /* VPMAXUWZrmkz */ + }, + { /* 10874 */ + 229, + /* VPMAXUWZrr */ + }, + { /* 10875 */ + 233, + /* VPMAXUWZrrk */ + }, + { /* 10876 */ + 234, + /* VPMAXUWZrrkz */ + }, + { /* 10877 */ + 235, + /* VPMAXUWrm */ + }, + { /* 10878 */ + 236, + /* VPMAXUWrr */ + }, + { /* 10879 */ + 204, + /* VPMINSBYrm */ + }, + { /* 10880 */ + 205, + /* VPMINSBYrr */ + }, + { /* 10881 */ + 206, + /* VPMINSBZ128rm */ + }, + { /* 10882 */ + 203, + /* VPMINSBZ128rmk */ + }, + { /* 10883 */ + 210, + /* VPMINSBZ128rmkz */ + }, + { /* 10884 */ + 211, + /* VPMINSBZ128rr */ + }, + { /* 10885 */ + 212, + /* VPMINSBZ128rrk */ + }, + { /* 10886 */ + 213, + /* VPMINSBZ128rrkz */ + }, + { /* 10887 */ + 214, + /* VPMINSBZ256rm */ + }, + { /* 10888 */ + 218, + /* VPMINSBZ256rmk */ + }, + { /* 10889 */ + 219, + /* VPMINSBZ256rmkz */ + }, + { /* 10890 */ + 220, + /* VPMINSBZ256rr */ + }, + { /* 10891 */ + 221, + /* VPMINSBZ256rrk */ + }, + { /* 10892 */ + 222, + /* VPMINSBZ256rrkz */ + }, + { /* 10893 */ + 223, + /* VPMINSBZrm */ + }, + { /* 10894 */ + 227, + /* VPMINSBZrmk */ + }, + { /* 10895 */ + 228, + /* VPMINSBZrmkz */ + }, + { /* 10896 */ + 229, + /* VPMINSBZrr */ + }, + { /* 10897 */ + 233, + /* VPMINSBZrrk */ + }, + { /* 10898 */ + 234, + /* VPMINSBZrrkz */ + }, + { /* 10899 */ + 235, + /* VPMINSBrm */ + }, + { /* 10900 */ + 236, + /* VPMINSBrr */ + }, + { /* 10901 */ + 204, + /* VPMINSDYrm */ + }, + { /* 10902 */ + 205, + /* VPMINSDYrr */ + }, + { /* 10903 */ + 206, + /* VPMINSDZ128rm */ + }, + { /* 10904 */ + 237, + /* VPMINSDZ128rmb */ + }, + { /* 10905 */ + 238, + /* VPMINSDZ128rmbk */ + }, + { /* 10906 */ + 239, + /* VPMINSDZ128rmbkz */ + }, + { /* 10907 */ + 203, + /* VPMINSDZ128rmk */ + }, + { /* 10908 */ + 210, + /* VPMINSDZ128rmkz */ + }, + { /* 10909 */ + 211, + /* VPMINSDZ128rr */ + }, + { /* 10910 */ + 212, + /* VPMINSDZ128rrk */ + }, + { /* 10911 */ + 213, + /* VPMINSDZ128rrkz */ + }, + { /* 10912 */ + 214, + /* VPMINSDZ256rm */ + }, + { /* 10913 */ + 240, + /* VPMINSDZ256rmb */ + }, + { /* 10914 */ + 241, + /* VPMINSDZ256rmbk */ + }, + { /* 10915 */ + 242, + /* VPMINSDZ256rmbkz */ + }, + { /* 10916 */ + 218, + /* VPMINSDZ256rmk */ + }, + { /* 10917 */ + 219, + /* VPMINSDZ256rmkz */ + }, + { /* 10918 */ + 220, + /* VPMINSDZ256rr */ + }, + { /* 10919 */ + 221, + /* VPMINSDZ256rrk */ + }, + { /* 10920 */ + 222, + /* VPMINSDZ256rrkz */ + }, + { /* 10921 */ + 223, + /* VPMINSDZrm */ + }, + { /* 10922 */ + 243, + /* VPMINSDZrmb */ + }, + { /* 10923 */ + 244, + /* VPMINSDZrmbk */ + }, + { /* 10924 */ + 245, + /* VPMINSDZrmbkz */ + }, + { /* 10925 */ + 227, + /* VPMINSDZrmk */ + }, + { /* 10926 */ + 228, + /* VPMINSDZrmkz */ + }, + { /* 10927 */ + 229, + /* VPMINSDZrr */ + }, + { /* 10928 */ + 233, + /* VPMINSDZrrk */ + }, + { /* 10929 */ + 234, + /* VPMINSDZrrkz */ + }, + { /* 10930 */ + 235, + /* VPMINSDrm */ + }, + { /* 10931 */ + 236, + /* VPMINSDrr */ + }, + { /* 10932 */ + 206, + /* VPMINSQZ128rm */ + }, + { /* 10933 */ + 207, + /* VPMINSQZ128rmb */ + }, + { /* 10934 */ + 208, + /* VPMINSQZ128rmbk */ + }, + { /* 10935 */ + 209, + /* VPMINSQZ128rmbkz */ + }, + { /* 10936 */ + 203, + /* VPMINSQZ128rmk */ + }, + { /* 10937 */ + 210, + /* VPMINSQZ128rmkz */ + }, + { /* 10938 */ + 211, + /* VPMINSQZ128rr */ + }, + { /* 10939 */ + 212, + /* VPMINSQZ128rrk */ + }, + { /* 10940 */ + 213, + /* VPMINSQZ128rrkz */ + }, + { /* 10941 */ + 214, + /* VPMINSQZ256rm */ + }, + { /* 10942 */ + 215, + /* VPMINSQZ256rmb */ + }, + { /* 10943 */ + 216, + /* VPMINSQZ256rmbk */ + }, + { /* 10944 */ + 217, + /* VPMINSQZ256rmbkz */ + }, + { /* 10945 */ + 218, + /* VPMINSQZ256rmk */ + }, + { /* 10946 */ + 219, + /* VPMINSQZ256rmkz */ + }, + { /* 10947 */ + 220, + /* VPMINSQZ256rr */ + }, + { /* 10948 */ + 221, + /* VPMINSQZ256rrk */ + }, + { /* 10949 */ + 222, + /* VPMINSQZ256rrkz */ + }, + { /* 10950 */ + 223, + /* VPMINSQZrm */ + }, + { /* 10951 */ + 224, + /* VPMINSQZrmb */ + }, + { /* 10952 */ + 225, + /* VPMINSQZrmbk */ + }, + { /* 10953 */ + 226, + /* VPMINSQZrmbkz */ + }, + { /* 10954 */ + 227, + /* VPMINSQZrmk */ + }, + { /* 10955 */ + 228, + /* VPMINSQZrmkz */ + }, + { /* 10956 */ + 229, + /* VPMINSQZrr */ + }, + { /* 10957 */ + 233, + /* VPMINSQZrrk */ + }, + { /* 10958 */ + 234, + /* VPMINSQZrrkz */ + }, + { /* 10959 */ + 204, + /* VPMINSWYrm */ + }, + { /* 10960 */ + 205, + /* VPMINSWYrr */ + }, + { /* 10961 */ + 206, + /* VPMINSWZ128rm */ + }, + { /* 10962 */ + 203, + /* VPMINSWZ128rmk */ + }, + { /* 10963 */ + 210, + /* VPMINSWZ128rmkz */ + }, + { /* 10964 */ + 211, + /* VPMINSWZ128rr */ + }, + { /* 10965 */ + 212, + /* VPMINSWZ128rrk */ + }, + { /* 10966 */ + 213, + /* VPMINSWZ128rrkz */ + }, + { /* 10967 */ + 214, + /* VPMINSWZ256rm */ + }, + { /* 10968 */ + 218, + /* VPMINSWZ256rmk */ + }, + { /* 10969 */ + 219, + /* VPMINSWZ256rmkz */ + }, + { /* 10970 */ + 220, + /* VPMINSWZ256rr */ + }, + { /* 10971 */ + 221, + /* VPMINSWZ256rrk */ + }, + { /* 10972 */ + 222, + /* VPMINSWZ256rrkz */ + }, + { /* 10973 */ + 223, + /* VPMINSWZrm */ + }, + { /* 10974 */ + 227, + /* VPMINSWZrmk */ + }, + { /* 10975 */ + 228, + /* VPMINSWZrmkz */ + }, + { /* 10976 */ + 229, + /* VPMINSWZrr */ + }, + { /* 10977 */ + 233, + /* VPMINSWZrrk */ + }, + { /* 10978 */ + 234, + /* VPMINSWZrrkz */ + }, + { /* 10979 */ + 235, + /* VPMINSWrm */ + }, + { /* 10980 */ + 236, + /* VPMINSWrr */ + }, + { /* 10981 */ + 204, + /* VPMINUBYrm */ + }, + { /* 10982 */ + 205, + /* VPMINUBYrr */ + }, + { /* 10983 */ + 206, + /* VPMINUBZ128rm */ + }, + { /* 10984 */ + 203, + /* VPMINUBZ128rmk */ + }, + { /* 10985 */ + 210, + /* VPMINUBZ128rmkz */ + }, + { /* 10986 */ + 211, + /* VPMINUBZ128rr */ + }, + { /* 10987 */ + 212, + /* VPMINUBZ128rrk */ + }, + { /* 10988 */ + 213, + /* VPMINUBZ128rrkz */ + }, + { /* 10989 */ + 214, + /* VPMINUBZ256rm */ + }, + { /* 10990 */ + 218, + /* VPMINUBZ256rmk */ + }, + { /* 10991 */ + 219, + /* VPMINUBZ256rmkz */ + }, + { /* 10992 */ + 220, + /* VPMINUBZ256rr */ + }, + { /* 10993 */ + 221, + /* VPMINUBZ256rrk */ + }, + { /* 10994 */ + 222, + /* VPMINUBZ256rrkz */ + }, + { /* 10995 */ + 223, + /* VPMINUBZrm */ + }, + { /* 10996 */ + 227, + /* VPMINUBZrmk */ + }, + { /* 10997 */ + 228, + /* VPMINUBZrmkz */ + }, + { /* 10998 */ + 229, + /* VPMINUBZrr */ + }, + { /* 10999 */ + 233, + /* VPMINUBZrrk */ + }, + { /* 11000 */ + 234, + /* VPMINUBZrrkz */ + }, + { /* 11001 */ + 235, + /* VPMINUBrm */ + }, + { /* 11002 */ + 236, + /* VPMINUBrr */ + }, + { /* 11003 */ + 204, + /* VPMINUDYrm */ + }, + { /* 11004 */ + 205, + /* VPMINUDYrr */ + }, + { /* 11005 */ + 206, + /* VPMINUDZ128rm */ + }, + { /* 11006 */ + 237, + /* VPMINUDZ128rmb */ + }, + { /* 11007 */ + 238, + /* VPMINUDZ128rmbk */ + }, + { /* 11008 */ + 239, + /* VPMINUDZ128rmbkz */ + }, + { /* 11009 */ + 203, + /* VPMINUDZ128rmk */ + }, + { /* 11010 */ + 210, + /* VPMINUDZ128rmkz */ + }, + { /* 11011 */ + 211, + /* VPMINUDZ128rr */ + }, + { /* 11012 */ + 212, + /* VPMINUDZ128rrk */ + }, + { /* 11013 */ + 213, + /* VPMINUDZ128rrkz */ + }, + { /* 11014 */ + 214, + /* VPMINUDZ256rm */ + }, + { /* 11015 */ + 240, + /* VPMINUDZ256rmb */ + }, + { /* 11016 */ + 241, + /* VPMINUDZ256rmbk */ + }, + { /* 11017 */ + 242, + /* VPMINUDZ256rmbkz */ + }, + { /* 11018 */ + 218, + /* VPMINUDZ256rmk */ + }, + { /* 11019 */ + 219, + /* VPMINUDZ256rmkz */ + }, + { /* 11020 */ + 220, + /* VPMINUDZ256rr */ + }, + { /* 11021 */ + 221, + /* VPMINUDZ256rrk */ + }, + { /* 11022 */ + 222, + /* VPMINUDZ256rrkz */ + }, + { /* 11023 */ + 223, + /* VPMINUDZrm */ + }, + { /* 11024 */ + 243, + /* VPMINUDZrmb */ + }, + { /* 11025 */ + 244, + /* VPMINUDZrmbk */ + }, + { /* 11026 */ + 245, + /* VPMINUDZrmbkz */ + }, + { /* 11027 */ + 227, + /* VPMINUDZrmk */ + }, + { /* 11028 */ + 228, + /* VPMINUDZrmkz */ + }, + { /* 11029 */ + 229, + /* VPMINUDZrr */ + }, + { /* 11030 */ + 233, + /* VPMINUDZrrk */ + }, + { /* 11031 */ + 234, + /* VPMINUDZrrkz */ + }, + { /* 11032 */ + 235, + /* VPMINUDrm */ + }, + { /* 11033 */ + 236, + /* VPMINUDrr */ + }, + { /* 11034 */ + 206, + /* VPMINUQZ128rm */ + }, + { /* 11035 */ + 207, + /* VPMINUQZ128rmb */ + }, + { /* 11036 */ + 208, + /* VPMINUQZ128rmbk */ + }, + { /* 11037 */ + 209, + /* VPMINUQZ128rmbkz */ + }, + { /* 11038 */ + 203, + /* VPMINUQZ128rmk */ + }, + { /* 11039 */ + 210, + /* VPMINUQZ128rmkz */ + }, + { /* 11040 */ + 211, + /* VPMINUQZ128rr */ + }, + { /* 11041 */ + 212, + /* VPMINUQZ128rrk */ + }, + { /* 11042 */ + 213, + /* VPMINUQZ128rrkz */ + }, + { /* 11043 */ + 214, + /* VPMINUQZ256rm */ + }, + { /* 11044 */ + 215, + /* VPMINUQZ256rmb */ + }, + { /* 11045 */ + 216, + /* VPMINUQZ256rmbk */ + }, + { /* 11046 */ + 217, + /* VPMINUQZ256rmbkz */ + }, + { /* 11047 */ + 218, + /* VPMINUQZ256rmk */ + }, + { /* 11048 */ + 219, + /* VPMINUQZ256rmkz */ + }, + { /* 11049 */ + 220, + /* VPMINUQZ256rr */ + }, + { /* 11050 */ + 221, + /* VPMINUQZ256rrk */ + }, + { /* 11051 */ + 222, + /* VPMINUQZ256rrkz */ + }, + { /* 11052 */ + 223, + /* VPMINUQZrm */ + }, + { /* 11053 */ + 224, + /* VPMINUQZrmb */ + }, + { /* 11054 */ + 225, + /* VPMINUQZrmbk */ + }, + { /* 11055 */ + 226, + /* VPMINUQZrmbkz */ + }, + { /* 11056 */ + 227, + /* VPMINUQZrmk */ + }, + { /* 11057 */ + 228, + /* VPMINUQZrmkz */ + }, + { /* 11058 */ + 229, + /* VPMINUQZrr */ + }, + { /* 11059 */ + 233, + /* VPMINUQZrrk */ + }, + { /* 11060 */ + 234, + /* VPMINUQZrrkz */ + }, + { /* 11061 */ + 204, + /* VPMINUWYrm */ + }, + { /* 11062 */ + 205, + /* VPMINUWYrr */ + }, + { /* 11063 */ + 206, + /* VPMINUWZ128rm */ + }, + { /* 11064 */ + 203, + /* VPMINUWZ128rmk */ + }, + { /* 11065 */ + 210, + /* VPMINUWZ128rmkz */ + }, + { /* 11066 */ + 211, + /* VPMINUWZ128rr */ + }, + { /* 11067 */ + 212, + /* VPMINUWZ128rrk */ + }, + { /* 11068 */ + 213, + /* VPMINUWZ128rrkz */ + }, + { /* 11069 */ + 214, + /* VPMINUWZ256rm */ + }, + { /* 11070 */ + 218, + /* VPMINUWZ256rmk */ + }, + { /* 11071 */ + 219, + /* VPMINUWZ256rmkz */ + }, + { /* 11072 */ + 220, + /* VPMINUWZ256rr */ + }, + { /* 11073 */ + 221, + /* VPMINUWZ256rrk */ + }, + { /* 11074 */ + 222, + /* VPMINUWZ256rrkz */ + }, + { /* 11075 */ + 223, + /* VPMINUWZrm */ + }, + { /* 11076 */ + 227, + /* VPMINUWZrmk */ + }, + { /* 11077 */ + 228, + /* VPMINUWZrmkz */ + }, + { /* 11078 */ + 229, + /* VPMINUWZrr */ + }, + { /* 11079 */ + 233, + /* VPMINUWZrrk */ + }, + { /* 11080 */ + 234, + /* VPMINUWZrrkz */ + }, + { /* 11081 */ + 235, + /* VPMINUWrm */ + }, + { /* 11082 */ + 236, + /* VPMINUWrr */ + }, + { /* 11083 */ + 801, + /* VPMOVB2MZ128rr */ + }, + { /* 11084 */ + 802, + /* VPMOVB2MZ256rr */ + }, + { /* 11085 */ + 803, + /* VPMOVB2MZrr */ + }, + { /* 11086 */ + 801, + /* VPMOVD2MZ128rr */ + }, + { /* 11087 */ + 802, + /* VPMOVD2MZ256rr */ + }, + { /* 11088 */ + 803, + /* VPMOVD2MZrr */ + }, + { /* 11089 */ + 394, + /* VPMOVDBZ128mr */ + }, + { /* 11090 */ + 395, + /* VPMOVDBZ128mrk */ + }, + { /* 11091 */ + 804, + /* VPMOVDBZ128rr */ + }, + { /* 11092 */ + 805, + /* VPMOVDBZ128rrk */ + }, + { /* 11093 */ + 806, + /* VPMOVDBZ128rrkz */ + }, + { /* 11094 */ + 384, + /* VPMOVDBZ256mr */ + }, + { /* 11095 */ + 385, + /* VPMOVDBZ256mrk */ + }, + { /* 11096 */ + 807, + /* VPMOVDBZ256rr */ + }, + { /* 11097 */ + 808, + /* VPMOVDBZ256rrk */ + }, + { /* 11098 */ + 809, + /* VPMOVDBZ256rrkz */ + }, + { /* 11099 */ + 810, + /* VPMOVDBZmr */ + }, + { /* 11100 */ + 811, + /* VPMOVDBZmrk */ + }, + { /* 11101 */ + 812, + /* VPMOVDBZrr */ + }, + { /* 11102 */ + 813, + /* VPMOVDBZrrk */ + }, + { /* 11103 */ + 814, + /* VPMOVDBZrrkz */ + }, + { /* 11104 */ + 379, + /* VPMOVDWZ128mr */ + }, + { /* 11105 */ + 380, + /* VPMOVDWZ128mrk */ + }, + { /* 11106 */ + 815, + /* VPMOVDWZ128rr */ + }, + { /* 11107 */ + 816, + /* VPMOVDWZ128rrk */ + }, + { /* 11108 */ + 817, + /* VPMOVDWZ128rrkz */ + }, + { /* 11109 */ + 818, + /* VPMOVDWZ256mr */ + }, + { /* 11110 */ + 819, + /* VPMOVDWZ256mrk */ + }, + { /* 11111 */ + 820, + /* VPMOVDWZ256rr */ + }, + { /* 11112 */ + 821, + /* VPMOVDWZ256rrk */ + }, + { /* 11113 */ + 822, + /* VPMOVDWZ256rrkz */ + }, + { /* 11114 */ + 823, + /* VPMOVDWZmr */ + }, + { /* 11115 */ + 824, + /* VPMOVDWZmrk */ + }, + { /* 11116 */ + 825, + /* VPMOVDWZrr */ + }, + { /* 11117 */ + 826, + /* VPMOVDWZrrk */ + }, + { /* 11118 */ + 827, + /* VPMOVDWZrrkz */ + }, + { /* 11119 */ + 703, + /* VPMOVM2BZ128rr */ + }, + { /* 11120 */ + 704, + /* VPMOVM2BZ256rr */ + }, + { /* 11121 */ + 705, + /* VPMOVM2BZrr */ + }, + { /* 11122 */ + 703, + /* VPMOVM2DZ128rr */ + }, + { /* 11123 */ + 704, + /* VPMOVM2DZ256rr */ + }, + { /* 11124 */ + 705, + /* VPMOVM2DZrr */ + }, + { /* 11125 */ + 703, + /* VPMOVM2QZ128rr */ + }, + { /* 11126 */ + 704, + /* VPMOVM2QZ256rr */ + }, + { /* 11127 */ + 705, + /* VPMOVM2QZrr */ + }, + { /* 11128 */ + 703, + /* VPMOVM2WZ128rr */ + }, + { /* 11129 */ + 704, + /* VPMOVM2WZ256rr */ + }, + { /* 11130 */ + 705, + /* VPMOVM2WZrr */ + }, + { /* 11131 */ + 679, + /* VPMOVMSKBYrr */ + }, + { /* 11132 */ + 88, + /* VPMOVMSKBrr */ + }, + { /* 11133 */ + 801, + /* VPMOVQ2MZ128rr */ + }, + { /* 11134 */ + 802, + /* VPMOVQ2MZ256rr */ + }, + { /* 11135 */ + 803, + /* VPMOVQ2MZrr */ + }, + { /* 11136 */ + 777, + /* VPMOVQBZ128mr */ + }, + { /* 11137 */ + 778, + /* VPMOVQBZ128mrk */ + }, + { /* 11138 */ + 828, + /* VPMOVQBZ128rr */ + }, + { /* 11139 */ + 829, + /* VPMOVQBZ128rrk */ + }, + { /* 11140 */ + 830, + /* VPMOVQBZ128rrkz */ + }, + { /* 11141 */ + 396, + /* VPMOVQBZ256mr */ + }, + { /* 11142 */ + 397, + /* VPMOVQBZ256mrk */ + }, + { /* 11143 */ + 831, + /* VPMOVQBZ256rr */ + }, + { /* 11144 */ + 832, + /* VPMOVQBZ256rrk */ + }, + { /* 11145 */ + 833, + /* VPMOVQBZ256rrkz */ + }, + { /* 11146 */ + 389, + /* VPMOVQBZmr */ + }, + { /* 11147 */ + 390, + /* VPMOVQBZmrk */ + }, + { /* 11148 */ + 834, + /* VPMOVQBZrr */ + }, + { /* 11149 */ + 835, + /* VPMOVQBZrrk */ + }, + { /* 11150 */ + 836, + /* VPMOVQBZrrkz */ + }, + { /* 11151 */ + 379, + /* VPMOVQDZ128mr */ + }, + { /* 11152 */ + 380, + /* VPMOVQDZ128mrk */ + }, + { /* 11153 */ + 815, + /* VPMOVQDZ128rr */ + }, + { /* 11154 */ + 816, + /* VPMOVQDZ128rrk */ + }, + { /* 11155 */ + 817, + /* VPMOVQDZ128rrkz */ + }, + { /* 11156 */ + 818, + /* VPMOVQDZ256mr */ + }, + { /* 11157 */ + 819, + /* VPMOVQDZ256mrk */ + }, + { /* 11158 */ + 820, + /* VPMOVQDZ256rr */ + }, + { /* 11159 */ + 821, + /* VPMOVQDZ256rrk */ + }, + { /* 11160 */ + 822, + /* VPMOVQDZ256rrkz */ + }, + { /* 11161 */ + 823, + /* VPMOVQDZmr */ + }, + { /* 11162 */ + 824, + /* VPMOVQDZmrk */ + }, + { /* 11163 */ + 825, + /* VPMOVQDZrr */ + }, + { /* 11164 */ + 826, + /* VPMOVQDZrrk */ + }, + { /* 11165 */ + 827, + /* VPMOVQDZrrkz */ + }, + { /* 11166 */ + 394, + /* VPMOVQWZ128mr */ + }, + { /* 11167 */ + 395, + /* VPMOVQWZ128mrk */ + }, + { /* 11168 */ + 804, + /* VPMOVQWZ128rr */ + }, + { /* 11169 */ + 805, + /* VPMOVQWZ128rrk */ + }, + { /* 11170 */ + 806, + /* VPMOVQWZ128rrkz */ + }, + { /* 11171 */ + 384, + /* VPMOVQWZ256mr */ + }, + { /* 11172 */ + 385, + /* VPMOVQWZ256mrk */ + }, + { /* 11173 */ + 807, + /* VPMOVQWZ256rr */ + }, + { /* 11174 */ + 808, + /* VPMOVQWZ256rrk */ + }, + { /* 11175 */ + 809, + /* VPMOVQWZ256rrkz */ + }, + { /* 11176 */ + 810, + /* VPMOVQWZmr */ + }, + { /* 11177 */ + 811, + /* VPMOVQWZmrk */ + }, + { /* 11178 */ + 812, + /* VPMOVQWZrr */ + }, + { /* 11179 */ + 813, + /* VPMOVQWZrrk */ + }, + { /* 11180 */ + 814, + /* VPMOVQWZrrkz */ + }, + { /* 11181 */ + 394, + /* VPMOVSDBZ128mr */ + }, + { /* 11182 */ + 395, + /* VPMOVSDBZ128mrk */ + }, + { /* 11183 */ + 804, + /* VPMOVSDBZ128rr */ + }, + { /* 11184 */ + 805, + /* VPMOVSDBZ128rrk */ + }, + { /* 11185 */ + 806, + /* VPMOVSDBZ128rrkz */ + }, + { /* 11186 */ + 384, + /* VPMOVSDBZ256mr */ + }, + { /* 11187 */ + 385, + /* VPMOVSDBZ256mrk */ + }, + { /* 11188 */ + 807, + /* VPMOVSDBZ256rr */ + }, + { /* 11189 */ + 808, + /* VPMOVSDBZ256rrk */ + }, + { /* 11190 */ + 809, + /* VPMOVSDBZ256rrkz */ + }, + { /* 11191 */ + 810, + /* VPMOVSDBZmr */ + }, + { /* 11192 */ + 811, + /* VPMOVSDBZmrk */ + }, + { /* 11193 */ + 812, + /* VPMOVSDBZrr */ + }, + { /* 11194 */ + 813, + /* VPMOVSDBZrrk */ + }, + { /* 11195 */ + 814, + /* VPMOVSDBZrrkz */ + }, + { /* 11196 */ + 379, + /* VPMOVSDWZ128mr */ + }, + { /* 11197 */ + 380, + /* VPMOVSDWZ128mrk */ + }, + { /* 11198 */ + 815, + /* VPMOVSDWZ128rr */ + }, + { /* 11199 */ + 816, + /* VPMOVSDWZ128rrk */ + }, + { /* 11200 */ + 817, + /* VPMOVSDWZ128rrkz */ + }, + { /* 11201 */ + 818, + /* VPMOVSDWZ256mr */ + }, + { /* 11202 */ + 819, + /* VPMOVSDWZ256mrk */ + }, + { /* 11203 */ + 820, + /* VPMOVSDWZ256rr */ + }, + { /* 11204 */ + 821, + /* VPMOVSDWZ256rrk */ + }, + { /* 11205 */ + 822, + /* VPMOVSDWZ256rrkz */ + }, + { /* 11206 */ + 823, + /* VPMOVSDWZmr */ + }, + { /* 11207 */ + 824, + /* VPMOVSDWZmrk */ + }, + { /* 11208 */ + 825, + /* VPMOVSDWZrr */ + }, + { /* 11209 */ + 826, + /* VPMOVSDWZrrk */ + }, + { /* 11210 */ + 827, + /* VPMOVSDWZrrkz */ + }, + { /* 11211 */ + 777, + /* VPMOVSQBZ128mr */ + }, + { /* 11212 */ + 778, + /* VPMOVSQBZ128mrk */ + }, + { /* 11213 */ + 828, + /* VPMOVSQBZ128rr */ + }, + { /* 11214 */ + 829, + /* VPMOVSQBZ128rrk */ + }, + { /* 11215 */ + 830, + /* VPMOVSQBZ128rrkz */ + }, + { /* 11216 */ + 396, + /* VPMOVSQBZ256mr */ + }, + { /* 11217 */ + 397, + /* VPMOVSQBZ256mrk */ + }, + { /* 11218 */ + 831, + /* VPMOVSQBZ256rr */ + }, + { /* 11219 */ + 832, + /* VPMOVSQBZ256rrk */ + }, + { /* 11220 */ + 833, + /* VPMOVSQBZ256rrkz */ + }, + { /* 11221 */ + 389, + /* VPMOVSQBZmr */ + }, + { /* 11222 */ + 390, + /* VPMOVSQBZmrk */ + }, + { /* 11223 */ + 834, + /* VPMOVSQBZrr */ + }, + { /* 11224 */ + 835, + /* VPMOVSQBZrrk */ + }, + { /* 11225 */ + 836, + /* VPMOVSQBZrrkz */ + }, + { /* 11226 */ + 379, + /* VPMOVSQDZ128mr */ + }, + { /* 11227 */ + 380, + /* VPMOVSQDZ128mrk */ + }, + { /* 11228 */ + 815, + /* VPMOVSQDZ128rr */ + }, + { /* 11229 */ + 816, + /* VPMOVSQDZ128rrk */ + }, + { /* 11230 */ + 817, + /* VPMOVSQDZ128rrkz */ + }, + { /* 11231 */ + 818, + /* VPMOVSQDZ256mr */ + }, + { /* 11232 */ + 819, + /* VPMOVSQDZ256mrk */ + }, + { /* 11233 */ + 820, + /* VPMOVSQDZ256rr */ + }, + { /* 11234 */ + 821, + /* VPMOVSQDZ256rrk */ + }, + { /* 11235 */ + 822, + /* VPMOVSQDZ256rrkz */ + }, + { /* 11236 */ + 823, + /* VPMOVSQDZmr */ + }, + { /* 11237 */ + 824, + /* VPMOVSQDZmrk */ + }, + { /* 11238 */ + 825, + /* VPMOVSQDZrr */ + }, + { /* 11239 */ + 826, + /* VPMOVSQDZrrk */ + }, + { /* 11240 */ + 827, + /* VPMOVSQDZrrkz */ + }, + { /* 11241 */ + 394, + /* VPMOVSQWZ128mr */ + }, + { /* 11242 */ + 395, + /* VPMOVSQWZ128mrk */ + }, + { /* 11243 */ + 804, + /* VPMOVSQWZ128rr */ + }, + { /* 11244 */ + 805, + /* VPMOVSQWZ128rrk */ + }, + { /* 11245 */ + 806, + /* VPMOVSQWZ128rrkz */ + }, + { /* 11246 */ + 384, + /* VPMOVSQWZ256mr */ + }, + { /* 11247 */ + 385, + /* VPMOVSQWZ256mrk */ + }, + { /* 11248 */ + 807, + /* VPMOVSQWZ256rr */ + }, + { /* 11249 */ + 808, + /* VPMOVSQWZ256rrk */ + }, + { /* 11250 */ + 809, + /* VPMOVSQWZ256rrkz */ + }, + { /* 11251 */ + 810, + /* VPMOVSQWZmr */ + }, + { /* 11252 */ + 811, + /* VPMOVSQWZmrk */ + }, + { /* 11253 */ + 812, + /* VPMOVSQWZrr */ + }, + { /* 11254 */ + 813, + /* VPMOVSQWZrrk */ + }, + { /* 11255 */ + 814, + /* VPMOVSQWZrrkz */ + }, + { /* 11256 */ + 379, + /* VPMOVSWBZ128mr */ + }, + { /* 11257 */ + 380, + /* VPMOVSWBZ128mrk */ + }, + { /* 11258 */ + 815, + /* VPMOVSWBZ128rr */ + }, + { /* 11259 */ + 816, + /* VPMOVSWBZ128rrk */ + }, + { /* 11260 */ + 817, + /* VPMOVSWBZ128rrkz */ + }, + { /* 11261 */ + 818, + /* VPMOVSWBZ256mr */ + }, + { /* 11262 */ + 819, + /* VPMOVSWBZ256mrk */ + }, + { /* 11263 */ + 820, + /* VPMOVSWBZ256rr */ + }, + { /* 11264 */ + 821, + /* VPMOVSWBZ256rrk */ + }, + { /* 11265 */ + 822, + /* VPMOVSWBZ256rrkz */ + }, + { /* 11266 */ + 823, + /* VPMOVSWBZmr */ + }, + { /* 11267 */ + 824, + /* VPMOVSWBZmrk */ + }, + { /* 11268 */ + 825, + /* VPMOVSWBZrr */ + }, + { /* 11269 */ + 826, + /* VPMOVSWBZrrk */ + }, + { /* 11270 */ + 827, + /* VPMOVSWBZrrkz */ + }, + { /* 11271 */ + 305, + /* VPMOVSXBDYrm */ + }, + { /* 11272 */ + 333, + /* VPMOVSXBDYrr */ + }, + { /* 11273 */ + 334, + /* VPMOVSXBDZ128rm */ + }, + { /* 11274 */ + 335, + /* VPMOVSXBDZ128rmk */ + }, + { /* 11275 */ + 336, + /* VPMOVSXBDZ128rmkz */ + }, + { /* 11276 */ + 378, + /* VPMOVSXBDZ128rr */ + }, + { /* 11277 */ + 837, + /* VPMOVSXBDZ128rrk */ + }, + { /* 11278 */ + 838, + /* VPMOVSXBDZ128rrkz */ + }, + { /* 11279 */ + 306, + /* VPMOVSXBDZ256rm */ + }, + { /* 11280 */ + 307, + /* VPMOVSXBDZ256rmk */ + }, + { /* 11281 */ + 308, + /* VPMOVSXBDZ256rmkz */ + }, + { /* 11282 */ + 839, + /* VPMOVSXBDZ256rr */ + }, + { /* 11283 */ + 840, + /* VPMOVSXBDZ256rrk */ + }, + { /* 11284 */ + 841, + /* VPMOVSXBDZ256rrkz */ + }, + { /* 11285 */ + 321, + /* VPMOVSXBDZrm */ + }, + { /* 11286 */ + 322, + /* VPMOVSXBDZrmk */ + }, + { /* 11287 */ + 323, + /* VPMOVSXBDZrmkz */ + }, + { /* 11288 */ + 842, + /* VPMOVSXBDZrr */ + }, + { /* 11289 */ + 843, + /* VPMOVSXBDZrrk */ + }, + { /* 11290 */ + 844, + /* VPMOVSXBDZrrkz */ + }, + { /* 11291 */ + 30, + /* VPMOVSXBDrm */ + }, + { /* 11292 */ + 31, + /* VPMOVSXBDrr */ + }, + { /* 11293 */ + 305, + /* VPMOVSXBQYrm */ + }, + { /* 11294 */ + 333, + /* VPMOVSXBQYrr */ + }, + { /* 11295 */ + 714, + /* VPMOVSXBQZ128rm */ + }, + { /* 11296 */ + 715, + /* VPMOVSXBQZ128rmk */ + }, + { /* 11297 */ + 716, + /* VPMOVSXBQZ128rmkz */ + }, + { /* 11298 */ + 845, + /* VPMOVSXBQZ128rr */ + }, + { /* 11299 */ + 846, + /* VPMOVSXBQZ128rrk */ + }, + { /* 11300 */ + 847, + /* VPMOVSXBQZ128rrkz */ + }, + { /* 11301 */ + 337, + /* VPMOVSXBQZ256rm */ + }, + { /* 11302 */ + 338, + /* VPMOVSXBQZ256rmk */ + }, + { /* 11303 */ + 339, + /* VPMOVSXBQZ256rmkz */ + }, + { /* 11304 */ + 848, + /* VPMOVSXBQZ256rr */ + }, + { /* 11305 */ + 849, + /* VPMOVSXBQZ256rrk */ + }, + { /* 11306 */ + 850, + /* VPMOVSXBQZ256rrkz */ + }, + { /* 11307 */ + 312, + /* VPMOVSXBQZrm */ + }, + { /* 11308 */ + 313, + /* VPMOVSXBQZrmk */ + }, + { /* 11309 */ + 314, + /* VPMOVSXBQZrmkz */ + }, + { /* 11310 */ + 851, + /* VPMOVSXBQZrr */ + }, + { /* 11311 */ + 852, + /* VPMOVSXBQZrrk */ + }, + { /* 11312 */ + 853, + /* VPMOVSXBQZrrkz */ + }, + { /* 11313 */ + 30, + /* VPMOVSXBQrm */ + }, + { /* 11314 */ + 31, + /* VPMOVSXBQrr */ + }, + { /* 11315 */ + 305, + /* VPMOVSXBWYrm */ + }, + { /* 11316 */ + 333, + /* VPMOVSXBWYrr */ + }, + { /* 11317 */ + 327, + /* VPMOVSXBWZ128rm */ + }, + { /* 11318 */ + 328, + /* VPMOVSXBWZ128rmk */ + }, + { /* 11319 */ + 329, + /* VPMOVSXBWZ128rmkz */ + }, + { /* 11320 */ + 377, + /* VPMOVSXBWZ128rr */ + }, + { /* 11321 */ + 400, + /* VPMOVSXBWZ128rrk */ + }, + { /* 11322 */ + 401, + /* VPMOVSXBWZ128rrkz */ + }, + { /* 11323 */ + 318, + /* VPMOVSXBWZ256rm */ + }, + { /* 11324 */ + 319, + /* VPMOVSXBWZ256rmk */ + }, + { /* 11325 */ + 320, + /* VPMOVSXBWZ256rmkz */ + }, + { /* 11326 */ + 402, + /* VPMOVSXBWZ256rr */ + }, + { /* 11327 */ + 403, + /* VPMOVSXBWZ256rrk */ + }, + { /* 11328 */ + 404, + /* VPMOVSXBWZ256rrkz */ + }, + { /* 11329 */ + 324, + /* VPMOVSXBWZrm */ + }, + { /* 11330 */ + 325, + /* VPMOVSXBWZrmk */ + }, + { /* 11331 */ + 326, + /* VPMOVSXBWZrmkz */ + }, + { /* 11332 */ + 405, + /* VPMOVSXBWZrr */ + }, + { /* 11333 */ + 406, + /* VPMOVSXBWZrrk */ + }, + { /* 11334 */ + 407, + /* VPMOVSXBWZrrkz */ + }, + { /* 11335 */ + 30, + /* VPMOVSXBWrm */ + }, + { /* 11336 */ + 31, + /* VPMOVSXBWrr */ + }, + { /* 11337 */ + 305, + /* VPMOVSXDQYrm */ + }, + { /* 11338 */ + 333, + /* VPMOVSXDQYrr */ + }, + { /* 11339 */ + 327, + /* VPMOVSXDQZ128rm */ + }, + { /* 11340 */ + 328, + /* VPMOVSXDQZ128rmk */ + }, + { /* 11341 */ + 329, + /* VPMOVSXDQZ128rmkz */ + }, + { /* 11342 */ + 377, + /* VPMOVSXDQZ128rr */ + }, + { /* 11343 */ + 400, + /* VPMOVSXDQZ128rrk */ + }, + { /* 11344 */ + 401, + /* VPMOVSXDQZ128rrkz */ + }, + { /* 11345 */ + 318, + /* VPMOVSXDQZ256rm */ + }, + { /* 11346 */ + 319, + /* VPMOVSXDQZ256rmk */ + }, + { /* 11347 */ + 320, + /* VPMOVSXDQZ256rmkz */ + }, + { /* 11348 */ + 402, + /* VPMOVSXDQZ256rr */ + }, + { /* 11349 */ + 403, + /* VPMOVSXDQZ256rrk */ + }, + { /* 11350 */ + 404, + /* VPMOVSXDQZ256rrkz */ + }, + { /* 11351 */ + 324, + /* VPMOVSXDQZrm */ + }, + { /* 11352 */ + 325, + /* VPMOVSXDQZrmk */ + }, + { /* 11353 */ + 326, + /* VPMOVSXDQZrmkz */ + }, + { /* 11354 */ + 405, + /* VPMOVSXDQZrr */ + }, + { /* 11355 */ + 406, + /* VPMOVSXDQZrrk */ + }, + { /* 11356 */ + 407, + /* VPMOVSXDQZrrkz */ + }, + { /* 11357 */ + 30, + /* VPMOVSXDQrm */ + }, + { /* 11358 */ + 31, + /* VPMOVSXDQrr */ + }, + { /* 11359 */ + 305, + /* VPMOVSXWDYrm */ + }, + { /* 11360 */ + 333, + /* VPMOVSXWDYrr */ + }, + { /* 11361 */ + 327, + /* VPMOVSXWDZ128rm */ + }, + { /* 11362 */ + 328, + /* VPMOVSXWDZ128rmk */ + }, + { /* 11363 */ + 329, + /* VPMOVSXWDZ128rmkz */ + }, + { /* 11364 */ + 377, + /* VPMOVSXWDZ128rr */ + }, + { /* 11365 */ + 400, + /* VPMOVSXWDZ128rrk */ + }, + { /* 11366 */ + 401, + /* VPMOVSXWDZ128rrkz */ + }, + { /* 11367 */ + 318, + /* VPMOVSXWDZ256rm */ + }, + { /* 11368 */ + 319, + /* VPMOVSXWDZ256rmk */ + }, + { /* 11369 */ + 320, + /* VPMOVSXWDZ256rmkz */ + }, + { /* 11370 */ + 402, + /* VPMOVSXWDZ256rr */ + }, + { /* 11371 */ + 403, + /* VPMOVSXWDZ256rrk */ + }, + { /* 11372 */ + 404, + /* VPMOVSXWDZ256rrkz */ + }, + { /* 11373 */ + 324, + /* VPMOVSXWDZrm */ + }, + { /* 11374 */ + 325, + /* VPMOVSXWDZrmk */ + }, + { /* 11375 */ + 326, + /* VPMOVSXWDZrmkz */ + }, + { /* 11376 */ + 405, + /* VPMOVSXWDZrr */ + }, + { /* 11377 */ + 406, + /* VPMOVSXWDZrrk */ + }, + { /* 11378 */ + 407, + /* VPMOVSXWDZrrkz */ + }, + { /* 11379 */ + 30, + /* VPMOVSXWDrm */ + }, + { /* 11380 */ + 31, + /* VPMOVSXWDrr */ + }, + { /* 11381 */ + 305, + /* VPMOVSXWQYrm */ + }, + { /* 11382 */ + 333, + /* VPMOVSXWQYrr */ + }, + { /* 11383 */ + 334, + /* VPMOVSXWQZ128rm */ + }, + { /* 11384 */ + 335, + /* VPMOVSXWQZ128rmk */ + }, + { /* 11385 */ + 336, + /* VPMOVSXWQZ128rmkz */ + }, + { /* 11386 */ + 378, + /* VPMOVSXWQZ128rr */ + }, + { /* 11387 */ + 837, + /* VPMOVSXWQZ128rrk */ + }, + { /* 11388 */ + 838, + /* VPMOVSXWQZ128rrkz */ + }, + { /* 11389 */ + 306, + /* VPMOVSXWQZ256rm */ + }, + { /* 11390 */ + 307, + /* VPMOVSXWQZ256rmk */ + }, + { /* 11391 */ + 308, + /* VPMOVSXWQZ256rmkz */ + }, + { /* 11392 */ + 839, + /* VPMOVSXWQZ256rr */ + }, + { /* 11393 */ + 840, + /* VPMOVSXWQZ256rrk */ + }, + { /* 11394 */ + 841, + /* VPMOVSXWQZ256rrkz */ + }, + { /* 11395 */ + 321, + /* VPMOVSXWQZrm */ + }, + { /* 11396 */ + 322, + /* VPMOVSXWQZrmk */ + }, + { /* 11397 */ + 323, + /* VPMOVSXWQZrmkz */ + }, + { /* 11398 */ + 842, + /* VPMOVSXWQZrr */ + }, + { /* 11399 */ + 843, + /* VPMOVSXWQZrrk */ + }, + { /* 11400 */ + 844, + /* VPMOVSXWQZrrkz */ + }, + { /* 11401 */ + 30, + /* VPMOVSXWQrm */ + }, + { /* 11402 */ + 31, + /* VPMOVSXWQrr */ + }, + { /* 11403 */ + 394, + /* VPMOVUSDBZ128mr */ + }, + { /* 11404 */ + 395, + /* VPMOVUSDBZ128mrk */ + }, + { /* 11405 */ + 804, + /* VPMOVUSDBZ128rr */ + }, + { /* 11406 */ + 805, + /* VPMOVUSDBZ128rrk */ + }, + { /* 11407 */ + 806, + /* VPMOVUSDBZ128rrkz */ + }, + { /* 11408 */ + 384, + /* VPMOVUSDBZ256mr */ + }, + { /* 11409 */ + 385, + /* VPMOVUSDBZ256mrk */ + }, + { /* 11410 */ + 807, + /* VPMOVUSDBZ256rr */ + }, + { /* 11411 */ + 808, + /* VPMOVUSDBZ256rrk */ + }, + { /* 11412 */ + 809, + /* VPMOVUSDBZ256rrkz */ + }, + { /* 11413 */ + 810, + /* VPMOVUSDBZmr */ + }, + { /* 11414 */ + 811, + /* VPMOVUSDBZmrk */ + }, + { /* 11415 */ + 812, + /* VPMOVUSDBZrr */ + }, + { /* 11416 */ + 813, + /* VPMOVUSDBZrrk */ + }, + { /* 11417 */ + 814, + /* VPMOVUSDBZrrkz */ + }, + { /* 11418 */ + 379, + /* VPMOVUSDWZ128mr */ + }, + { /* 11419 */ + 380, + /* VPMOVUSDWZ128mrk */ + }, + { /* 11420 */ + 815, + /* VPMOVUSDWZ128rr */ + }, + { /* 11421 */ + 816, + /* VPMOVUSDWZ128rrk */ + }, + { /* 11422 */ + 817, + /* VPMOVUSDWZ128rrkz */ + }, + { /* 11423 */ + 818, + /* VPMOVUSDWZ256mr */ + }, + { /* 11424 */ + 819, + /* VPMOVUSDWZ256mrk */ + }, + { /* 11425 */ + 820, + /* VPMOVUSDWZ256rr */ + }, + { /* 11426 */ + 821, + /* VPMOVUSDWZ256rrk */ + }, + { /* 11427 */ + 822, + /* VPMOVUSDWZ256rrkz */ + }, + { /* 11428 */ + 823, + /* VPMOVUSDWZmr */ + }, + { /* 11429 */ + 824, + /* VPMOVUSDWZmrk */ + }, + { /* 11430 */ + 825, + /* VPMOVUSDWZrr */ + }, + { /* 11431 */ + 826, + /* VPMOVUSDWZrrk */ + }, + { /* 11432 */ + 827, + /* VPMOVUSDWZrrkz */ + }, + { /* 11433 */ + 777, + /* VPMOVUSQBZ128mr */ + }, + { /* 11434 */ + 778, + /* VPMOVUSQBZ128mrk */ + }, + { /* 11435 */ + 828, + /* VPMOVUSQBZ128rr */ + }, + { /* 11436 */ + 829, + /* VPMOVUSQBZ128rrk */ + }, + { /* 11437 */ + 830, + /* VPMOVUSQBZ128rrkz */ + }, + { /* 11438 */ + 396, + /* VPMOVUSQBZ256mr */ + }, + { /* 11439 */ + 397, + /* VPMOVUSQBZ256mrk */ + }, + { /* 11440 */ + 831, + /* VPMOVUSQBZ256rr */ + }, + { /* 11441 */ + 832, + /* VPMOVUSQBZ256rrk */ + }, + { /* 11442 */ + 833, + /* VPMOVUSQBZ256rrkz */ + }, + { /* 11443 */ + 389, + /* VPMOVUSQBZmr */ + }, + { /* 11444 */ + 390, + /* VPMOVUSQBZmrk */ + }, + { /* 11445 */ + 834, + /* VPMOVUSQBZrr */ + }, + { /* 11446 */ + 835, + /* VPMOVUSQBZrrk */ + }, + { /* 11447 */ + 836, + /* VPMOVUSQBZrrkz */ + }, + { /* 11448 */ + 379, + /* VPMOVUSQDZ128mr */ + }, + { /* 11449 */ + 380, + /* VPMOVUSQDZ128mrk */ + }, + { /* 11450 */ + 815, + /* VPMOVUSQDZ128rr */ + }, + { /* 11451 */ + 816, + /* VPMOVUSQDZ128rrk */ + }, + { /* 11452 */ + 817, + /* VPMOVUSQDZ128rrkz */ + }, + { /* 11453 */ + 818, + /* VPMOVUSQDZ256mr */ + }, + { /* 11454 */ + 819, + /* VPMOVUSQDZ256mrk */ + }, + { /* 11455 */ + 820, + /* VPMOVUSQDZ256rr */ + }, + { /* 11456 */ + 821, + /* VPMOVUSQDZ256rrk */ + }, + { /* 11457 */ + 822, + /* VPMOVUSQDZ256rrkz */ + }, + { /* 11458 */ + 823, + /* VPMOVUSQDZmr */ + }, + { /* 11459 */ + 824, + /* VPMOVUSQDZmrk */ + }, + { /* 11460 */ + 825, + /* VPMOVUSQDZrr */ + }, + { /* 11461 */ + 826, + /* VPMOVUSQDZrrk */ + }, + { /* 11462 */ + 827, + /* VPMOVUSQDZrrkz */ + }, + { /* 11463 */ + 394, + /* VPMOVUSQWZ128mr */ + }, + { /* 11464 */ + 395, + /* VPMOVUSQWZ128mrk */ + }, + { /* 11465 */ + 804, + /* VPMOVUSQWZ128rr */ + }, + { /* 11466 */ + 805, + /* VPMOVUSQWZ128rrk */ + }, + { /* 11467 */ + 806, + /* VPMOVUSQWZ128rrkz */ + }, + { /* 11468 */ + 384, + /* VPMOVUSQWZ256mr */ + }, + { /* 11469 */ + 385, + /* VPMOVUSQWZ256mrk */ + }, + { /* 11470 */ + 807, + /* VPMOVUSQWZ256rr */ + }, + { /* 11471 */ + 808, + /* VPMOVUSQWZ256rrk */ + }, + { /* 11472 */ + 809, + /* VPMOVUSQWZ256rrkz */ + }, + { /* 11473 */ + 810, + /* VPMOVUSQWZmr */ + }, + { /* 11474 */ + 811, + /* VPMOVUSQWZmrk */ + }, + { /* 11475 */ + 812, + /* VPMOVUSQWZrr */ + }, + { /* 11476 */ + 813, + /* VPMOVUSQWZrrk */ + }, + { /* 11477 */ + 814, + /* VPMOVUSQWZrrkz */ + }, + { /* 11478 */ + 379, + /* VPMOVUSWBZ128mr */ + }, + { /* 11479 */ + 380, + /* VPMOVUSWBZ128mrk */ + }, + { /* 11480 */ + 815, + /* VPMOVUSWBZ128rr */ + }, + { /* 11481 */ + 816, + /* VPMOVUSWBZ128rrk */ + }, + { /* 11482 */ + 817, + /* VPMOVUSWBZ128rrkz */ + }, + { /* 11483 */ + 818, + /* VPMOVUSWBZ256mr */ + }, + { /* 11484 */ + 819, + /* VPMOVUSWBZ256mrk */ + }, + { /* 11485 */ + 820, + /* VPMOVUSWBZ256rr */ + }, + { /* 11486 */ + 821, + /* VPMOVUSWBZ256rrk */ + }, + { /* 11487 */ + 822, + /* VPMOVUSWBZ256rrkz */ + }, + { /* 11488 */ + 823, + /* VPMOVUSWBZmr */ + }, + { /* 11489 */ + 824, + /* VPMOVUSWBZmrk */ + }, + { /* 11490 */ + 825, + /* VPMOVUSWBZrr */ + }, + { /* 11491 */ + 826, + /* VPMOVUSWBZrrk */ + }, + { /* 11492 */ + 827, + /* VPMOVUSWBZrrkz */ + }, + { /* 11493 */ + 801, + /* VPMOVW2MZ128rr */ + }, + { /* 11494 */ + 802, + /* VPMOVW2MZ256rr */ + }, + { /* 11495 */ + 803, + /* VPMOVW2MZrr */ + }, + { /* 11496 */ + 379, + /* VPMOVWBZ128mr */ + }, + { /* 11497 */ + 380, + /* VPMOVWBZ128mrk */ + }, + { /* 11498 */ + 815, + /* VPMOVWBZ128rr */ + }, + { /* 11499 */ + 816, + /* VPMOVWBZ128rrk */ + }, + { /* 11500 */ + 817, + /* VPMOVWBZ128rrkz */ + }, + { /* 11501 */ + 818, + /* VPMOVWBZ256mr */ + }, + { /* 11502 */ + 819, + /* VPMOVWBZ256mrk */ + }, + { /* 11503 */ + 820, + /* VPMOVWBZ256rr */ + }, + { /* 11504 */ + 821, + /* VPMOVWBZ256rrk */ + }, + { /* 11505 */ + 822, + /* VPMOVWBZ256rrkz */ + }, + { /* 11506 */ + 823, + /* VPMOVWBZmr */ + }, + { /* 11507 */ + 824, + /* VPMOVWBZmrk */ + }, + { /* 11508 */ + 825, + /* VPMOVWBZrr */ + }, + { /* 11509 */ + 826, + /* VPMOVWBZrrk */ + }, + { /* 11510 */ + 827, + /* VPMOVWBZrrkz */ + }, + { /* 11511 */ + 305, + /* VPMOVZXBDYrm */ + }, + { /* 11512 */ + 333, + /* VPMOVZXBDYrr */ + }, + { /* 11513 */ + 334, + /* VPMOVZXBDZ128rm */ + }, + { /* 11514 */ + 335, + /* VPMOVZXBDZ128rmk */ + }, + { /* 11515 */ + 336, + /* VPMOVZXBDZ128rmkz */ + }, + { /* 11516 */ + 378, + /* VPMOVZXBDZ128rr */ + }, + { /* 11517 */ + 837, + /* VPMOVZXBDZ128rrk */ + }, + { /* 11518 */ + 838, + /* VPMOVZXBDZ128rrkz */ + }, + { /* 11519 */ + 306, + /* VPMOVZXBDZ256rm */ + }, + { /* 11520 */ + 307, + /* VPMOVZXBDZ256rmk */ + }, + { /* 11521 */ + 308, + /* VPMOVZXBDZ256rmkz */ + }, + { /* 11522 */ + 839, + /* VPMOVZXBDZ256rr */ + }, + { /* 11523 */ + 840, + /* VPMOVZXBDZ256rrk */ + }, + { /* 11524 */ + 841, + /* VPMOVZXBDZ256rrkz */ + }, + { /* 11525 */ + 321, + /* VPMOVZXBDZrm */ + }, + { /* 11526 */ + 322, + /* VPMOVZXBDZrmk */ + }, + { /* 11527 */ + 323, + /* VPMOVZXBDZrmkz */ + }, + { /* 11528 */ + 842, + /* VPMOVZXBDZrr */ + }, + { /* 11529 */ + 843, + /* VPMOVZXBDZrrk */ + }, + { /* 11530 */ + 844, + /* VPMOVZXBDZrrkz */ + }, + { /* 11531 */ + 30, + /* VPMOVZXBDrm */ + }, + { /* 11532 */ + 31, + /* VPMOVZXBDrr */ + }, + { /* 11533 */ + 305, + /* VPMOVZXBQYrm */ + }, + { /* 11534 */ + 333, + /* VPMOVZXBQYrr */ + }, + { /* 11535 */ + 714, + /* VPMOVZXBQZ128rm */ + }, + { /* 11536 */ + 715, + /* VPMOVZXBQZ128rmk */ + }, + { /* 11537 */ + 716, + /* VPMOVZXBQZ128rmkz */ + }, + { /* 11538 */ + 845, + /* VPMOVZXBQZ128rr */ + }, + { /* 11539 */ + 846, + /* VPMOVZXBQZ128rrk */ + }, + { /* 11540 */ + 847, + /* VPMOVZXBQZ128rrkz */ + }, + { /* 11541 */ + 337, + /* VPMOVZXBQZ256rm */ + }, + { /* 11542 */ + 338, + /* VPMOVZXBQZ256rmk */ + }, + { /* 11543 */ + 339, + /* VPMOVZXBQZ256rmkz */ + }, + { /* 11544 */ + 848, + /* VPMOVZXBQZ256rr */ + }, + { /* 11545 */ + 849, + /* VPMOVZXBQZ256rrk */ + }, + { /* 11546 */ + 850, + /* VPMOVZXBQZ256rrkz */ + }, + { /* 11547 */ + 312, + /* VPMOVZXBQZrm */ + }, + { /* 11548 */ + 313, + /* VPMOVZXBQZrmk */ + }, + { /* 11549 */ + 314, + /* VPMOVZXBQZrmkz */ + }, + { /* 11550 */ + 851, + /* VPMOVZXBQZrr */ + }, + { /* 11551 */ + 852, + /* VPMOVZXBQZrrk */ + }, + { /* 11552 */ + 853, + /* VPMOVZXBQZrrkz */ + }, + { /* 11553 */ + 30, + /* VPMOVZXBQrm */ + }, + { /* 11554 */ + 31, + /* VPMOVZXBQrr */ + }, + { /* 11555 */ + 305, + /* VPMOVZXBWYrm */ + }, + { /* 11556 */ + 333, + /* VPMOVZXBWYrr */ + }, + { /* 11557 */ + 327, + /* VPMOVZXBWZ128rm */ + }, + { /* 11558 */ + 328, + /* VPMOVZXBWZ128rmk */ + }, + { /* 11559 */ + 329, + /* VPMOVZXBWZ128rmkz */ + }, + { /* 11560 */ + 377, + /* VPMOVZXBWZ128rr */ + }, + { /* 11561 */ + 400, + /* VPMOVZXBWZ128rrk */ + }, + { /* 11562 */ + 401, + /* VPMOVZXBWZ128rrkz */ + }, + { /* 11563 */ + 318, + /* VPMOVZXBWZ256rm */ + }, + { /* 11564 */ + 319, + /* VPMOVZXBWZ256rmk */ + }, + { /* 11565 */ + 320, + /* VPMOVZXBWZ256rmkz */ + }, + { /* 11566 */ + 402, + /* VPMOVZXBWZ256rr */ + }, + { /* 11567 */ + 403, + /* VPMOVZXBWZ256rrk */ + }, + { /* 11568 */ + 404, + /* VPMOVZXBWZ256rrkz */ + }, + { /* 11569 */ + 324, + /* VPMOVZXBWZrm */ + }, + { /* 11570 */ + 325, + /* VPMOVZXBWZrmk */ + }, + { /* 11571 */ + 326, + /* VPMOVZXBWZrmkz */ + }, + { /* 11572 */ + 405, + /* VPMOVZXBWZrr */ + }, + { /* 11573 */ + 406, + /* VPMOVZXBWZrrk */ + }, + { /* 11574 */ + 407, + /* VPMOVZXBWZrrkz */ + }, + { /* 11575 */ + 30, + /* VPMOVZXBWrm */ + }, + { /* 11576 */ + 31, + /* VPMOVZXBWrr */ + }, + { /* 11577 */ + 305, + /* VPMOVZXDQYrm */ + }, + { /* 11578 */ + 333, + /* VPMOVZXDQYrr */ + }, + { /* 11579 */ + 327, + /* VPMOVZXDQZ128rm */ + }, + { /* 11580 */ + 328, + /* VPMOVZXDQZ128rmk */ + }, + { /* 11581 */ + 329, + /* VPMOVZXDQZ128rmkz */ + }, + { /* 11582 */ + 377, + /* VPMOVZXDQZ128rr */ + }, + { /* 11583 */ + 400, + /* VPMOVZXDQZ128rrk */ + }, + { /* 11584 */ + 401, + /* VPMOVZXDQZ128rrkz */ + }, + { /* 11585 */ + 318, + /* VPMOVZXDQZ256rm */ + }, + { /* 11586 */ + 319, + /* VPMOVZXDQZ256rmk */ + }, + { /* 11587 */ + 320, + /* VPMOVZXDQZ256rmkz */ + }, + { /* 11588 */ + 402, + /* VPMOVZXDQZ256rr */ + }, + { /* 11589 */ + 403, + /* VPMOVZXDQZ256rrk */ + }, + { /* 11590 */ + 404, + /* VPMOVZXDQZ256rrkz */ + }, + { /* 11591 */ + 324, + /* VPMOVZXDQZrm */ + }, + { /* 11592 */ + 325, + /* VPMOVZXDQZrmk */ + }, + { /* 11593 */ + 326, + /* VPMOVZXDQZrmkz */ + }, + { /* 11594 */ + 405, + /* VPMOVZXDQZrr */ + }, + { /* 11595 */ + 406, + /* VPMOVZXDQZrrk */ + }, + { /* 11596 */ + 407, + /* VPMOVZXDQZrrkz */ + }, + { /* 11597 */ + 30, + /* VPMOVZXDQrm */ + }, + { /* 11598 */ + 31, + /* VPMOVZXDQrr */ + }, + { /* 11599 */ + 305, + /* VPMOVZXWDYrm */ + }, + { /* 11600 */ + 333, + /* VPMOVZXWDYrr */ + }, + { /* 11601 */ + 327, + /* VPMOVZXWDZ128rm */ + }, + { /* 11602 */ + 328, + /* VPMOVZXWDZ128rmk */ + }, + { /* 11603 */ + 329, + /* VPMOVZXWDZ128rmkz */ + }, + { /* 11604 */ + 377, + /* VPMOVZXWDZ128rr */ + }, + { /* 11605 */ + 400, + /* VPMOVZXWDZ128rrk */ + }, + { /* 11606 */ + 401, + /* VPMOVZXWDZ128rrkz */ + }, + { /* 11607 */ + 318, + /* VPMOVZXWDZ256rm */ + }, + { /* 11608 */ + 319, + /* VPMOVZXWDZ256rmk */ + }, + { /* 11609 */ + 320, + /* VPMOVZXWDZ256rmkz */ + }, + { /* 11610 */ + 402, + /* VPMOVZXWDZ256rr */ + }, + { /* 11611 */ + 403, + /* VPMOVZXWDZ256rrk */ + }, + { /* 11612 */ + 404, + /* VPMOVZXWDZ256rrkz */ + }, + { /* 11613 */ + 324, + /* VPMOVZXWDZrm */ + }, + { /* 11614 */ + 325, + /* VPMOVZXWDZrmk */ + }, + { /* 11615 */ + 326, + /* VPMOVZXWDZrmkz */ + }, + { /* 11616 */ + 405, + /* VPMOVZXWDZrr */ + }, + { /* 11617 */ + 406, + /* VPMOVZXWDZrrk */ + }, + { /* 11618 */ + 407, + /* VPMOVZXWDZrrkz */ + }, + { /* 11619 */ + 30, + /* VPMOVZXWDrm */ + }, + { /* 11620 */ + 31, + /* VPMOVZXWDrr */ + }, + { /* 11621 */ + 305, + /* VPMOVZXWQYrm */ + }, + { /* 11622 */ + 333, + /* VPMOVZXWQYrr */ + }, + { /* 11623 */ + 334, + /* VPMOVZXWQZ128rm */ + }, + { /* 11624 */ + 335, + /* VPMOVZXWQZ128rmk */ + }, + { /* 11625 */ + 336, + /* VPMOVZXWQZ128rmkz */ + }, + { /* 11626 */ + 378, + /* VPMOVZXWQZ128rr */ + }, + { /* 11627 */ + 837, + /* VPMOVZXWQZ128rrk */ + }, + { /* 11628 */ + 838, + /* VPMOVZXWQZ128rrkz */ + }, + { /* 11629 */ + 306, + /* VPMOVZXWQZ256rm */ + }, + { /* 11630 */ + 307, + /* VPMOVZXWQZ256rmk */ + }, + { /* 11631 */ + 308, + /* VPMOVZXWQZ256rmkz */ + }, + { /* 11632 */ + 839, + /* VPMOVZXWQZ256rr */ + }, + { /* 11633 */ + 840, + /* VPMOVZXWQZ256rrk */ + }, + { /* 11634 */ + 841, + /* VPMOVZXWQZ256rrkz */ + }, + { /* 11635 */ + 321, + /* VPMOVZXWQZrm */ + }, + { /* 11636 */ + 322, + /* VPMOVZXWQZrmk */ + }, + { /* 11637 */ + 323, + /* VPMOVZXWQZrmkz */ + }, + { /* 11638 */ + 842, + /* VPMOVZXWQZrr */ + }, + { /* 11639 */ + 843, + /* VPMOVZXWQZrrk */ + }, + { /* 11640 */ + 844, + /* VPMOVZXWQZrrkz */ + }, + { /* 11641 */ + 30, + /* VPMOVZXWQrm */ + }, + { /* 11642 */ + 31, + /* VPMOVZXWQrr */ + }, + { /* 11643 */ + 204, + /* VPMULDQYrm */ + }, + { /* 11644 */ + 205, + /* VPMULDQYrr */ + }, + { /* 11645 */ + 206, + /* VPMULDQZ128rm */ + }, + { /* 11646 */ + 207, + /* VPMULDQZ128rmb */ + }, + { /* 11647 */ + 208, + /* VPMULDQZ128rmbk */ + }, + { /* 11648 */ + 209, + /* VPMULDQZ128rmbkz */ + }, + { /* 11649 */ + 203, + /* VPMULDQZ128rmk */ + }, + { /* 11650 */ + 210, + /* VPMULDQZ128rmkz */ + }, + { /* 11651 */ + 211, + /* VPMULDQZ128rr */ + }, + { /* 11652 */ + 212, + /* VPMULDQZ128rrk */ + }, + { /* 11653 */ + 213, + /* VPMULDQZ128rrkz */ + }, + { /* 11654 */ + 214, + /* VPMULDQZ256rm */ + }, + { /* 11655 */ + 215, + /* VPMULDQZ256rmb */ + }, + { /* 11656 */ + 216, + /* VPMULDQZ256rmbk */ + }, + { /* 11657 */ + 217, + /* VPMULDQZ256rmbkz */ + }, + { /* 11658 */ + 218, + /* VPMULDQZ256rmk */ + }, + { /* 11659 */ + 219, + /* VPMULDQZ256rmkz */ + }, + { /* 11660 */ + 220, + /* VPMULDQZ256rr */ + }, + { /* 11661 */ + 221, + /* VPMULDQZ256rrk */ + }, + { /* 11662 */ + 222, + /* VPMULDQZ256rrkz */ + }, + { /* 11663 */ + 223, + /* VPMULDQZrm */ + }, + { /* 11664 */ + 224, + /* VPMULDQZrmb */ + }, + { /* 11665 */ + 225, + /* VPMULDQZrmbk */ + }, + { /* 11666 */ + 226, + /* VPMULDQZrmbkz */ + }, + { /* 11667 */ + 227, + /* VPMULDQZrmk */ + }, + { /* 11668 */ + 228, + /* VPMULDQZrmkz */ + }, + { /* 11669 */ + 229, + /* VPMULDQZrr */ + }, + { /* 11670 */ + 233, + /* VPMULDQZrrk */ + }, + { /* 11671 */ + 234, + /* VPMULDQZrrkz */ + }, + { /* 11672 */ + 235, + /* VPMULDQrm */ + }, + { /* 11673 */ + 236, + /* VPMULDQrr */ + }, + { /* 11674 */ + 204, + /* VPMULHRSWYrm */ + }, + { /* 11675 */ + 205, + /* VPMULHRSWYrr */ + }, + { /* 11676 */ + 206, + /* VPMULHRSWZ128rm */ + }, + { /* 11677 */ + 203, + /* VPMULHRSWZ128rmk */ + }, + { /* 11678 */ + 210, + /* VPMULHRSWZ128rmkz */ + }, + { /* 11679 */ + 211, + /* VPMULHRSWZ128rr */ + }, + { /* 11680 */ + 212, + /* VPMULHRSWZ128rrk */ + }, + { /* 11681 */ + 213, + /* VPMULHRSWZ128rrkz */ + }, + { /* 11682 */ + 214, + /* VPMULHRSWZ256rm */ + }, + { /* 11683 */ + 218, + /* VPMULHRSWZ256rmk */ + }, + { /* 11684 */ + 219, + /* VPMULHRSWZ256rmkz */ + }, + { /* 11685 */ + 220, + /* VPMULHRSWZ256rr */ + }, + { /* 11686 */ + 221, + /* VPMULHRSWZ256rrk */ + }, + { /* 11687 */ + 222, + /* VPMULHRSWZ256rrkz */ + }, + { /* 11688 */ + 223, + /* VPMULHRSWZrm */ + }, + { /* 11689 */ + 227, + /* VPMULHRSWZrmk */ + }, + { /* 11690 */ + 228, + /* VPMULHRSWZrmkz */ + }, + { /* 11691 */ + 229, + /* VPMULHRSWZrr */ + }, + { /* 11692 */ + 233, + /* VPMULHRSWZrrk */ + }, + { /* 11693 */ + 234, + /* VPMULHRSWZrrkz */ + }, + { /* 11694 */ + 235, + /* VPMULHRSWrm */ + }, + { /* 11695 */ + 236, + /* VPMULHRSWrr */ + }, + { /* 11696 */ + 204, + /* VPMULHUWYrm */ + }, + { /* 11697 */ + 205, + /* VPMULHUWYrr */ + }, + { /* 11698 */ + 206, + /* VPMULHUWZ128rm */ + }, + { /* 11699 */ + 203, + /* VPMULHUWZ128rmk */ + }, + { /* 11700 */ + 210, + /* VPMULHUWZ128rmkz */ + }, + { /* 11701 */ + 211, + /* VPMULHUWZ128rr */ + }, + { /* 11702 */ + 212, + /* VPMULHUWZ128rrk */ + }, + { /* 11703 */ + 213, + /* VPMULHUWZ128rrkz */ + }, + { /* 11704 */ + 214, + /* VPMULHUWZ256rm */ + }, + { /* 11705 */ + 218, + /* VPMULHUWZ256rmk */ + }, + { /* 11706 */ + 219, + /* VPMULHUWZ256rmkz */ + }, + { /* 11707 */ + 220, + /* VPMULHUWZ256rr */ + }, + { /* 11708 */ + 221, + /* VPMULHUWZ256rrk */ + }, + { /* 11709 */ + 222, + /* VPMULHUWZ256rrkz */ + }, + { /* 11710 */ + 223, + /* VPMULHUWZrm */ + }, + { /* 11711 */ + 227, + /* VPMULHUWZrmk */ + }, + { /* 11712 */ + 228, + /* VPMULHUWZrmkz */ + }, + { /* 11713 */ + 229, + /* VPMULHUWZrr */ + }, + { /* 11714 */ + 233, + /* VPMULHUWZrrk */ + }, + { /* 11715 */ + 234, + /* VPMULHUWZrrkz */ + }, + { /* 11716 */ + 235, + /* VPMULHUWrm */ + }, + { /* 11717 */ + 236, + /* VPMULHUWrr */ + }, + { /* 11718 */ + 204, + /* VPMULHWYrm */ + }, + { /* 11719 */ + 205, + /* VPMULHWYrr */ + }, + { /* 11720 */ + 206, + /* VPMULHWZ128rm */ + }, + { /* 11721 */ + 203, + /* VPMULHWZ128rmk */ + }, + { /* 11722 */ + 210, + /* VPMULHWZ128rmkz */ + }, + { /* 11723 */ + 211, + /* VPMULHWZ128rr */ + }, + { /* 11724 */ + 212, + /* VPMULHWZ128rrk */ + }, + { /* 11725 */ + 213, + /* VPMULHWZ128rrkz */ + }, + { /* 11726 */ + 214, + /* VPMULHWZ256rm */ + }, + { /* 11727 */ + 218, + /* VPMULHWZ256rmk */ + }, + { /* 11728 */ + 219, + /* VPMULHWZ256rmkz */ + }, + { /* 11729 */ + 220, + /* VPMULHWZ256rr */ + }, + { /* 11730 */ + 221, + /* VPMULHWZ256rrk */ + }, + { /* 11731 */ + 222, + /* VPMULHWZ256rrkz */ + }, + { /* 11732 */ + 223, + /* VPMULHWZrm */ + }, + { /* 11733 */ + 227, + /* VPMULHWZrmk */ + }, + { /* 11734 */ + 228, + /* VPMULHWZrmkz */ + }, + { /* 11735 */ + 229, + /* VPMULHWZrr */ + }, + { /* 11736 */ + 233, + /* VPMULHWZrrk */ + }, + { /* 11737 */ + 234, + /* VPMULHWZrrkz */ + }, + { /* 11738 */ + 235, + /* VPMULHWrm */ + }, + { /* 11739 */ + 236, + /* VPMULHWrr */ + }, + { /* 11740 */ + 204, + /* VPMULLDYrm */ + }, + { /* 11741 */ + 205, + /* VPMULLDYrr */ + }, + { /* 11742 */ + 206, + /* VPMULLDZ128rm */ + }, + { /* 11743 */ + 237, + /* VPMULLDZ128rmb */ + }, + { /* 11744 */ + 238, + /* VPMULLDZ128rmbk */ + }, + { /* 11745 */ + 239, + /* VPMULLDZ128rmbkz */ + }, + { /* 11746 */ + 203, + /* VPMULLDZ128rmk */ + }, + { /* 11747 */ + 210, + /* VPMULLDZ128rmkz */ + }, + { /* 11748 */ + 211, + /* VPMULLDZ128rr */ + }, + { /* 11749 */ + 212, + /* VPMULLDZ128rrk */ + }, + { /* 11750 */ + 213, + /* VPMULLDZ128rrkz */ + }, + { /* 11751 */ + 214, + /* VPMULLDZ256rm */ + }, + { /* 11752 */ + 240, + /* VPMULLDZ256rmb */ + }, + { /* 11753 */ + 241, + /* VPMULLDZ256rmbk */ + }, + { /* 11754 */ + 242, + /* VPMULLDZ256rmbkz */ + }, + { /* 11755 */ + 218, + /* VPMULLDZ256rmk */ + }, + { /* 11756 */ + 219, + /* VPMULLDZ256rmkz */ + }, + { /* 11757 */ + 220, + /* VPMULLDZ256rr */ + }, + { /* 11758 */ + 221, + /* VPMULLDZ256rrk */ + }, + { /* 11759 */ + 222, + /* VPMULLDZ256rrkz */ + }, + { /* 11760 */ + 223, + /* VPMULLDZrm */ + }, + { /* 11761 */ + 243, + /* VPMULLDZrmb */ + }, + { /* 11762 */ + 244, + /* VPMULLDZrmbk */ + }, + { /* 11763 */ + 245, + /* VPMULLDZrmbkz */ + }, + { /* 11764 */ + 227, + /* VPMULLDZrmk */ + }, + { /* 11765 */ + 228, + /* VPMULLDZrmkz */ + }, + { /* 11766 */ + 229, + /* VPMULLDZrr */ + }, + { /* 11767 */ + 233, + /* VPMULLDZrrk */ + }, + { /* 11768 */ + 234, + /* VPMULLDZrrkz */ + }, + { /* 11769 */ + 235, + /* VPMULLDrm */ + }, + { /* 11770 */ + 236, + /* VPMULLDrr */ + }, + { /* 11771 */ + 206, + /* VPMULLQZ128rm */ + }, + { /* 11772 */ + 207, + /* VPMULLQZ128rmb */ + }, + { /* 11773 */ + 208, + /* VPMULLQZ128rmbk */ + }, + { /* 11774 */ + 209, + /* VPMULLQZ128rmbkz */ + }, + { /* 11775 */ + 203, + /* VPMULLQZ128rmk */ + }, + { /* 11776 */ + 210, + /* VPMULLQZ128rmkz */ + }, + { /* 11777 */ + 211, + /* VPMULLQZ128rr */ + }, + { /* 11778 */ + 212, + /* VPMULLQZ128rrk */ + }, + { /* 11779 */ + 213, + /* VPMULLQZ128rrkz */ + }, + { /* 11780 */ + 214, + /* VPMULLQZ256rm */ + }, + { /* 11781 */ + 215, + /* VPMULLQZ256rmb */ + }, + { /* 11782 */ + 216, + /* VPMULLQZ256rmbk */ + }, + { /* 11783 */ + 217, + /* VPMULLQZ256rmbkz */ + }, + { /* 11784 */ + 218, + /* VPMULLQZ256rmk */ + }, + { /* 11785 */ + 219, + /* VPMULLQZ256rmkz */ + }, + { /* 11786 */ + 220, + /* VPMULLQZ256rr */ + }, + { /* 11787 */ + 221, + /* VPMULLQZ256rrk */ + }, + { /* 11788 */ + 222, + /* VPMULLQZ256rrkz */ + }, + { /* 11789 */ + 223, + /* VPMULLQZrm */ + }, + { /* 11790 */ + 224, + /* VPMULLQZrmb */ + }, + { /* 11791 */ + 225, + /* VPMULLQZrmbk */ + }, + { /* 11792 */ + 226, + /* VPMULLQZrmbkz */ + }, + { /* 11793 */ + 227, + /* VPMULLQZrmk */ + }, + { /* 11794 */ + 228, + /* VPMULLQZrmkz */ + }, + { /* 11795 */ + 229, + /* VPMULLQZrr */ + }, + { /* 11796 */ + 233, + /* VPMULLQZrrk */ + }, + { /* 11797 */ + 234, + /* VPMULLQZrrkz */ + }, + { /* 11798 */ + 204, + /* VPMULLWYrm */ + }, + { /* 11799 */ + 205, + /* VPMULLWYrr */ + }, + { /* 11800 */ + 206, + /* VPMULLWZ128rm */ + }, + { /* 11801 */ + 203, + /* VPMULLWZ128rmk */ + }, + { /* 11802 */ + 210, + /* VPMULLWZ128rmkz */ + }, + { /* 11803 */ + 211, + /* VPMULLWZ128rr */ + }, + { /* 11804 */ + 212, + /* VPMULLWZ128rrk */ + }, + { /* 11805 */ + 213, + /* VPMULLWZ128rrkz */ + }, + { /* 11806 */ + 214, + /* VPMULLWZ256rm */ + }, + { /* 11807 */ + 218, + /* VPMULLWZ256rmk */ + }, + { /* 11808 */ + 219, + /* VPMULLWZ256rmkz */ + }, + { /* 11809 */ + 220, + /* VPMULLWZ256rr */ + }, + { /* 11810 */ + 221, + /* VPMULLWZ256rrk */ + }, + { /* 11811 */ + 222, + /* VPMULLWZ256rrkz */ + }, + { /* 11812 */ + 223, + /* VPMULLWZrm */ + }, + { /* 11813 */ + 227, + /* VPMULLWZrmk */ + }, + { /* 11814 */ + 228, + /* VPMULLWZrmkz */ + }, + { /* 11815 */ + 229, + /* VPMULLWZrr */ + }, + { /* 11816 */ + 233, + /* VPMULLWZrrk */ + }, + { /* 11817 */ + 234, + /* VPMULLWZrrkz */ + }, + { /* 11818 */ + 235, + /* VPMULLWrm */ + }, + { /* 11819 */ + 236, + /* VPMULLWrr */ + }, + { /* 11820 */ + 206, + /* VPMULTISHIFTQBZ128rm */ + }, + { /* 11821 */ + 207, + /* VPMULTISHIFTQBZ128rmb */ + }, + { /* 11822 */ + 208, + /* VPMULTISHIFTQBZ128rmbk */ + }, + { /* 11823 */ + 209, + /* VPMULTISHIFTQBZ128rmbkz */ + }, + { /* 11824 */ + 203, + /* VPMULTISHIFTQBZ128rmk */ + }, + { /* 11825 */ + 210, + /* VPMULTISHIFTQBZ128rmkz */ + }, + { /* 11826 */ + 211, + /* VPMULTISHIFTQBZ128rr */ + }, + { /* 11827 */ + 212, + /* VPMULTISHIFTQBZ128rrk */ + }, + { /* 11828 */ + 213, + /* VPMULTISHIFTQBZ128rrkz */ + }, + { /* 11829 */ + 214, + /* VPMULTISHIFTQBZ256rm */ + }, + { /* 11830 */ + 215, + /* VPMULTISHIFTQBZ256rmb */ + }, + { /* 11831 */ + 216, + /* VPMULTISHIFTQBZ256rmbk */ + }, + { /* 11832 */ + 217, + /* VPMULTISHIFTQBZ256rmbkz */ + }, + { /* 11833 */ + 218, + /* VPMULTISHIFTQBZ256rmk */ + }, + { /* 11834 */ + 219, + /* VPMULTISHIFTQBZ256rmkz */ + }, + { /* 11835 */ + 220, + /* VPMULTISHIFTQBZ256rr */ + }, + { /* 11836 */ + 221, + /* VPMULTISHIFTQBZ256rrk */ + }, + { /* 11837 */ + 222, + /* VPMULTISHIFTQBZ256rrkz */ + }, + { /* 11838 */ + 223, + /* VPMULTISHIFTQBZrm */ + }, + { /* 11839 */ + 224, + /* VPMULTISHIFTQBZrmb */ + }, + { /* 11840 */ + 225, + /* VPMULTISHIFTQBZrmbk */ + }, + { /* 11841 */ + 226, + /* VPMULTISHIFTQBZrmbkz */ + }, + { /* 11842 */ + 227, + /* VPMULTISHIFTQBZrmk */ + }, + { /* 11843 */ + 228, + /* VPMULTISHIFTQBZrmkz */ + }, + { /* 11844 */ + 229, + /* VPMULTISHIFTQBZrr */ + }, + { /* 11845 */ + 233, + /* VPMULTISHIFTQBZrrk */ + }, + { /* 11846 */ + 234, + /* VPMULTISHIFTQBZrrkz */ + }, + { /* 11847 */ + 204, + /* VPMULUDQYrm */ + }, + { /* 11848 */ + 205, + /* VPMULUDQYrr */ + }, + { /* 11849 */ + 206, + /* VPMULUDQZ128rm */ + }, + { /* 11850 */ + 207, + /* VPMULUDQZ128rmb */ + }, + { /* 11851 */ + 208, + /* VPMULUDQZ128rmbk */ + }, + { /* 11852 */ + 209, + /* VPMULUDQZ128rmbkz */ + }, + { /* 11853 */ + 203, + /* VPMULUDQZ128rmk */ + }, + { /* 11854 */ + 210, + /* VPMULUDQZ128rmkz */ + }, + { /* 11855 */ + 211, + /* VPMULUDQZ128rr */ + }, + { /* 11856 */ + 212, + /* VPMULUDQZ128rrk */ + }, + { /* 11857 */ + 213, + /* VPMULUDQZ128rrkz */ + }, + { /* 11858 */ + 214, + /* VPMULUDQZ256rm */ + }, + { /* 11859 */ + 215, + /* VPMULUDQZ256rmb */ + }, + { /* 11860 */ + 216, + /* VPMULUDQZ256rmbk */ + }, + { /* 11861 */ + 217, + /* VPMULUDQZ256rmbkz */ + }, + { /* 11862 */ + 218, + /* VPMULUDQZ256rmk */ + }, + { /* 11863 */ + 219, + /* VPMULUDQZ256rmkz */ + }, + { /* 11864 */ + 220, + /* VPMULUDQZ256rr */ + }, + { /* 11865 */ + 221, + /* VPMULUDQZ256rrk */ + }, + { /* 11866 */ + 222, + /* VPMULUDQZ256rrkz */ + }, + { /* 11867 */ + 223, + /* VPMULUDQZrm */ + }, + { /* 11868 */ + 224, + /* VPMULUDQZrmb */ + }, + { /* 11869 */ + 225, + /* VPMULUDQZrmbk */ + }, + { /* 11870 */ + 226, + /* VPMULUDQZrmbkz */ + }, + { /* 11871 */ + 227, + /* VPMULUDQZrmk */ + }, + { /* 11872 */ + 228, + /* VPMULUDQZrmkz */ + }, + { /* 11873 */ + 229, + /* VPMULUDQZrr */ + }, + { /* 11874 */ + 233, + /* VPMULUDQZrrk */ + }, + { /* 11875 */ + 234, + /* VPMULUDQZrrkz */ + }, + { /* 11876 */ + 235, + /* VPMULUDQrm */ + }, + { /* 11877 */ + 236, + /* VPMULUDQrr */ + }, + { /* 11878 */ + 409, + /* VPOPCNTBZ128rm */ + }, + { /* 11879 */ + 410, + /* VPOPCNTBZ128rmk */ + }, + { /* 11880 */ + 411, + /* VPOPCNTBZ128rmkz */ + }, + { /* 11881 */ + 330, + /* VPOPCNTBZ128rr */ + }, + { /* 11882 */ + 331, + /* VPOPCNTBZ128rrk */ + }, + { /* 11883 */ + 332, + /* VPOPCNTBZ128rrkz */ + }, + { /* 11884 */ + 412, + /* VPOPCNTBZ256rm */ + }, + { /* 11885 */ + 413, + /* VPOPCNTBZ256rmk */ + }, + { /* 11886 */ + 414, + /* VPOPCNTBZ256rmkz */ + }, + { /* 11887 */ + 415, + /* VPOPCNTBZ256rr */ + }, + { /* 11888 */ + 416, + /* VPOPCNTBZ256rrk */ + }, + { /* 11889 */ + 417, + /* VPOPCNTBZ256rrkz */ + }, + { /* 11890 */ + 418, + /* VPOPCNTBZrm */ + }, + { /* 11891 */ + 419, + /* VPOPCNTBZrmk */ + }, + { /* 11892 */ + 420, + /* VPOPCNTBZrmkz */ + }, + { /* 11893 */ + 421, + /* VPOPCNTBZrr */ + }, + { /* 11894 */ + 425, + /* VPOPCNTBZrrk */ + }, + { /* 11895 */ + 426, + /* VPOPCNTBZrrkz */ + }, + { /* 11896 */ + 409, + /* VPOPCNTDZ128rm */ + }, + { /* 11897 */ + 334, + /* VPOPCNTDZ128rmb */ + }, + { /* 11898 */ + 335, + /* VPOPCNTDZ128rmbk */ + }, + { /* 11899 */ + 336, + /* VPOPCNTDZ128rmbkz */ + }, + { /* 11900 */ + 410, + /* VPOPCNTDZ128rmk */ + }, + { /* 11901 */ + 411, + /* VPOPCNTDZ128rmkz */ + }, + { /* 11902 */ + 330, + /* VPOPCNTDZ128rr */ + }, + { /* 11903 */ + 331, + /* VPOPCNTDZ128rrk */ + }, + { /* 11904 */ + 332, + /* VPOPCNTDZ128rrkz */ + }, + { /* 11905 */ + 412, + /* VPOPCNTDZ256rm */ + }, + { /* 11906 */ + 337, + /* VPOPCNTDZ256rmb */ + }, + { /* 11907 */ + 338, + /* VPOPCNTDZ256rmbk */ + }, + { /* 11908 */ + 339, + /* VPOPCNTDZ256rmbkz */ + }, + { /* 11909 */ + 413, + /* VPOPCNTDZ256rmk */ + }, + { /* 11910 */ + 414, + /* VPOPCNTDZ256rmkz */ + }, + { /* 11911 */ + 415, + /* VPOPCNTDZ256rr */ + }, + { /* 11912 */ + 416, + /* VPOPCNTDZ256rrk */ + }, + { /* 11913 */ + 417, + /* VPOPCNTDZ256rrkz */ + }, + { /* 11914 */ + 418, + /* VPOPCNTDZrm */ + }, + { /* 11915 */ + 340, + /* VPOPCNTDZrmb */ + }, + { /* 11916 */ + 341, + /* VPOPCNTDZrmbk */ + }, + { /* 11917 */ + 342, + /* VPOPCNTDZrmbkz */ + }, + { /* 11918 */ + 419, + /* VPOPCNTDZrmk */ + }, + { /* 11919 */ + 420, + /* VPOPCNTDZrmkz */ + }, + { /* 11920 */ + 421, + /* VPOPCNTDZrr */ + }, + { /* 11921 */ + 425, + /* VPOPCNTDZrrk */ + }, + { /* 11922 */ + 426, + /* VPOPCNTDZrrkz */ + }, + { /* 11923 */ + 409, + /* VPOPCNTQZ128rm */ + }, + { /* 11924 */ + 327, + /* VPOPCNTQZ128rmb */ + }, + { /* 11925 */ + 328, + /* VPOPCNTQZ128rmbk */ + }, + { /* 11926 */ + 329, + /* VPOPCNTQZ128rmbkz */ + }, + { /* 11927 */ + 410, + /* VPOPCNTQZ128rmk */ + }, + { /* 11928 */ + 411, + /* VPOPCNTQZ128rmkz */ + }, + { /* 11929 */ + 330, + /* VPOPCNTQZ128rr */ + }, + { /* 11930 */ + 331, + /* VPOPCNTQZ128rrk */ + }, + { /* 11931 */ + 332, + /* VPOPCNTQZ128rrkz */ + }, + { /* 11932 */ + 412, + /* VPOPCNTQZ256rm */ + }, + { /* 11933 */ + 306, + /* VPOPCNTQZ256rmb */ + }, + { /* 11934 */ + 307, + /* VPOPCNTQZ256rmbk */ + }, + { /* 11935 */ + 308, + /* VPOPCNTQZ256rmbkz */ + }, + { /* 11936 */ + 413, + /* VPOPCNTQZ256rmk */ + }, + { /* 11937 */ + 414, + /* VPOPCNTQZ256rmkz */ + }, + { /* 11938 */ + 415, + /* VPOPCNTQZ256rr */ + }, + { /* 11939 */ + 416, + /* VPOPCNTQZ256rrk */ + }, + { /* 11940 */ + 417, + /* VPOPCNTQZ256rrkz */ + }, + { /* 11941 */ + 418, + /* VPOPCNTQZrm */ + }, + { /* 11942 */ + 312, + /* VPOPCNTQZrmb */ + }, + { /* 11943 */ + 313, + /* VPOPCNTQZrmbk */ + }, + { /* 11944 */ + 314, + /* VPOPCNTQZrmbkz */ + }, + { /* 11945 */ + 419, + /* VPOPCNTQZrmk */ + }, + { /* 11946 */ + 420, + /* VPOPCNTQZrmkz */ + }, + { /* 11947 */ + 421, + /* VPOPCNTQZrr */ + }, + { /* 11948 */ + 425, + /* VPOPCNTQZrrk */ + }, + { /* 11949 */ + 426, + /* VPOPCNTQZrrkz */ + }, + { /* 11950 */ + 409, + /* VPOPCNTWZ128rm */ + }, + { /* 11951 */ + 410, + /* VPOPCNTWZ128rmk */ + }, + { /* 11952 */ + 411, + /* VPOPCNTWZ128rmkz */ + }, + { /* 11953 */ + 330, + /* VPOPCNTWZ128rr */ + }, + { /* 11954 */ + 331, + /* VPOPCNTWZ128rrk */ + }, + { /* 11955 */ + 332, + /* VPOPCNTWZ128rrkz */ + }, + { /* 11956 */ + 412, + /* VPOPCNTWZ256rm */ + }, + { /* 11957 */ + 413, + /* VPOPCNTWZ256rmk */ + }, + { /* 11958 */ + 414, + /* VPOPCNTWZ256rmkz */ + }, + { /* 11959 */ + 415, + /* VPOPCNTWZ256rr */ + }, + { /* 11960 */ + 416, + /* VPOPCNTWZ256rrk */ + }, + { /* 11961 */ + 417, + /* VPOPCNTWZ256rrkz */ + }, + { /* 11962 */ + 418, + /* VPOPCNTWZrm */ + }, + { /* 11963 */ + 419, + /* VPOPCNTWZrmk */ + }, + { /* 11964 */ + 420, + /* VPOPCNTWZrmkz */ + }, + { /* 11965 */ + 421, + /* VPOPCNTWZrr */ + }, + { /* 11966 */ + 425, + /* VPOPCNTWZrrk */ + }, + { /* 11967 */ + 426, + /* VPOPCNTWZrrkz */ + }, + { /* 11968 */ + 206, + /* VPORDZ128rm */ + }, + { /* 11969 */ + 237, + /* VPORDZ128rmb */ + }, + { /* 11970 */ + 238, + /* VPORDZ128rmbk */ + }, + { /* 11971 */ + 239, + /* VPORDZ128rmbkz */ + }, + { /* 11972 */ + 203, + /* VPORDZ128rmk */ + }, + { /* 11973 */ + 210, + /* VPORDZ128rmkz */ + }, + { /* 11974 */ + 211, + /* VPORDZ128rr */ + }, + { /* 11975 */ + 212, + /* VPORDZ128rrk */ + }, + { /* 11976 */ + 213, + /* VPORDZ128rrkz */ + }, + { /* 11977 */ + 214, + /* VPORDZ256rm */ + }, + { /* 11978 */ + 240, + /* VPORDZ256rmb */ + }, + { /* 11979 */ + 241, + /* VPORDZ256rmbk */ + }, + { /* 11980 */ + 242, + /* VPORDZ256rmbkz */ + }, + { /* 11981 */ + 218, + /* VPORDZ256rmk */ + }, + { /* 11982 */ + 219, + /* VPORDZ256rmkz */ + }, + { /* 11983 */ + 220, + /* VPORDZ256rr */ + }, + { /* 11984 */ + 221, + /* VPORDZ256rrk */ + }, + { /* 11985 */ + 222, + /* VPORDZ256rrkz */ + }, + { /* 11986 */ + 223, + /* VPORDZrm */ + }, + { /* 11987 */ + 243, + /* VPORDZrmb */ + }, + { /* 11988 */ + 244, + /* VPORDZrmbk */ + }, + { /* 11989 */ + 245, + /* VPORDZrmbkz */ + }, + { /* 11990 */ + 227, + /* VPORDZrmk */ + }, + { /* 11991 */ + 228, + /* VPORDZrmkz */ + }, + { /* 11992 */ + 229, + /* VPORDZrr */ + }, + { /* 11993 */ + 233, + /* VPORDZrrk */ + }, + { /* 11994 */ + 234, + /* VPORDZrrkz */ + }, + { /* 11995 */ + 206, + /* VPORQZ128rm */ + }, + { /* 11996 */ + 207, + /* VPORQZ128rmb */ + }, + { /* 11997 */ + 208, + /* VPORQZ128rmbk */ + }, + { /* 11998 */ + 209, + /* VPORQZ128rmbkz */ + }, + { /* 11999 */ + 203, + /* VPORQZ128rmk */ + }, + { /* 12000 */ + 210, + /* VPORQZ128rmkz */ + }, + { /* 12001 */ + 211, + /* VPORQZ128rr */ + }, + { /* 12002 */ + 212, + /* VPORQZ128rrk */ + }, + { /* 12003 */ + 213, + /* VPORQZ128rrkz */ + }, + { /* 12004 */ + 214, + /* VPORQZ256rm */ + }, + { /* 12005 */ + 215, + /* VPORQZ256rmb */ + }, + { /* 12006 */ + 216, + /* VPORQZ256rmbk */ + }, + { /* 12007 */ + 217, + /* VPORQZ256rmbkz */ + }, + { /* 12008 */ + 218, + /* VPORQZ256rmk */ + }, + { /* 12009 */ + 219, + /* VPORQZ256rmkz */ + }, + { /* 12010 */ + 220, + /* VPORQZ256rr */ + }, + { /* 12011 */ + 221, + /* VPORQZ256rrk */ + }, + { /* 12012 */ + 222, + /* VPORQZ256rrkz */ + }, + { /* 12013 */ + 223, + /* VPORQZrm */ + }, + { /* 12014 */ + 224, + /* VPORQZrmb */ + }, + { /* 12015 */ + 225, + /* VPORQZrmbk */ + }, + { /* 12016 */ + 226, + /* VPORQZrmbkz */ + }, + { /* 12017 */ + 227, + /* VPORQZrmk */ + }, + { /* 12018 */ + 228, + /* VPORQZrmkz */ + }, + { /* 12019 */ + 229, + /* VPORQZrr */ + }, + { /* 12020 */ + 233, + /* VPORQZrrk */ + }, + { /* 12021 */ + 234, + /* VPORQZrrkz */ + }, + { /* 12022 */ + 204, + /* VPORYrm */ + }, + { /* 12023 */ + 205, + /* VPORYrr */ + }, + { /* 12024 */ + 235, + /* VPORrm */ + }, + { /* 12025 */ + 236, + /* VPORrr */ + }, + { /* 12026 */ + 303, + /* VPPERMrmr */ + }, + { /* 12027 */ + 550, + /* VPPERMrrm */ + }, + { /* 12028 */ + 304, + /* VPPERMrrr */ + }, + { /* 12029 */ + 551, + /* VPPERMrrr_REV */ + }, + { /* 12030 */ + 854, + /* VPROLDZ128mbi */ + }, + { /* 12031 */ + 855, + /* VPROLDZ128mbik */ + }, + { /* 12032 */ + 856, + /* VPROLDZ128mbikz */ + }, + { /* 12033 */ + 857, + /* VPROLDZ128mi */ + }, + { /* 12034 */ + 858, + /* VPROLDZ128mik */ + }, + { /* 12035 */ + 859, + /* VPROLDZ128mikz */ + }, + { /* 12036 */ + 860, + /* VPROLDZ128ri */ + }, + { /* 12037 */ + 861, + /* VPROLDZ128rik */ + }, + { /* 12038 */ + 862, + /* VPROLDZ128rikz */ + }, + { /* 12039 */ + 863, + /* VPROLDZ256mbi */ + }, + { /* 12040 */ + 864, + /* VPROLDZ256mbik */ + }, + { /* 12041 */ + 865, + /* VPROLDZ256mbikz */ + }, + { /* 12042 */ + 866, + /* VPROLDZ256mi */ + }, + { /* 12043 */ + 867, + /* VPROLDZ256mik */ + }, + { /* 12044 */ + 868, + /* VPROLDZ256mikz */ + }, + { /* 12045 */ + 869, + /* VPROLDZ256ri */ + }, + { /* 12046 */ + 870, + /* VPROLDZ256rik */ + }, + { /* 12047 */ + 871, + /* VPROLDZ256rikz */ + }, + { /* 12048 */ + 872, + /* VPROLDZmbi */ + }, + { /* 12049 */ + 873, + /* VPROLDZmbik */ + }, + { /* 12050 */ + 874, + /* VPROLDZmbikz */ + }, + { /* 12051 */ + 875, + /* VPROLDZmi */ + }, + { /* 12052 */ + 876, + /* VPROLDZmik */ + }, + { /* 12053 */ + 877, + /* VPROLDZmikz */ + }, + { /* 12054 */ + 878, + /* VPROLDZri */ + }, + { /* 12055 */ + 879, + /* VPROLDZrik */ + }, + { /* 12056 */ + 880, + /* VPROLDZrikz */ + }, + { /* 12057 */ + 881, + /* VPROLQZ128mbi */ + }, + { /* 12058 */ + 882, + /* VPROLQZ128mbik */ + }, + { /* 12059 */ + 883, + /* VPROLQZ128mbikz */ + }, + { /* 12060 */ + 857, + /* VPROLQZ128mi */ + }, + { /* 12061 */ + 858, + /* VPROLQZ128mik */ + }, + { /* 12062 */ + 859, + /* VPROLQZ128mikz */ + }, + { /* 12063 */ + 860, + /* VPROLQZ128ri */ + }, + { /* 12064 */ + 861, + /* VPROLQZ128rik */ + }, + { /* 12065 */ + 862, + /* VPROLQZ128rikz */ + }, + { /* 12066 */ + 884, + /* VPROLQZ256mbi */ + }, + { /* 12067 */ + 885, + /* VPROLQZ256mbik */ + }, + { /* 12068 */ + 886, + /* VPROLQZ256mbikz */ + }, + { /* 12069 */ + 866, + /* VPROLQZ256mi */ + }, + { /* 12070 */ + 867, + /* VPROLQZ256mik */ + }, + { /* 12071 */ + 868, + /* VPROLQZ256mikz */ + }, + { /* 12072 */ + 869, + /* VPROLQZ256ri */ + }, + { /* 12073 */ + 870, + /* VPROLQZ256rik */ + }, + { /* 12074 */ + 871, + /* VPROLQZ256rikz */ + }, + { /* 12075 */ + 887, + /* VPROLQZmbi */ + }, + { /* 12076 */ + 888, + /* VPROLQZmbik */ + }, + { /* 12077 */ + 889, + /* VPROLQZmbikz */ + }, + { /* 12078 */ + 875, + /* VPROLQZmi */ + }, + { /* 12079 */ + 876, + /* VPROLQZmik */ + }, + { /* 12080 */ + 877, + /* VPROLQZmikz */ + }, + { /* 12081 */ + 878, + /* VPROLQZri */ + }, + { /* 12082 */ + 879, + /* VPROLQZrik */ + }, + { /* 12083 */ + 880, + /* VPROLQZrikz */ + }, + { /* 12084 */ + 206, + /* VPROLVDZ128rm */ + }, + { /* 12085 */ + 237, + /* VPROLVDZ128rmb */ + }, + { /* 12086 */ + 238, + /* VPROLVDZ128rmbk */ + }, + { /* 12087 */ + 239, + /* VPROLVDZ128rmbkz */ + }, + { /* 12088 */ + 203, + /* VPROLVDZ128rmk */ + }, + { /* 12089 */ + 210, + /* VPROLVDZ128rmkz */ + }, + { /* 12090 */ + 211, + /* VPROLVDZ128rr */ + }, + { /* 12091 */ + 212, + /* VPROLVDZ128rrk */ + }, + { /* 12092 */ + 213, + /* VPROLVDZ128rrkz */ + }, + { /* 12093 */ + 214, + /* VPROLVDZ256rm */ + }, + { /* 12094 */ + 240, + /* VPROLVDZ256rmb */ + }, + { /* 12095 */ + 241, + /* VPROLVDZ256rmbk */ + }, + { /* 12096 */ + 242, + /* VPROLVDZ256rmbkz */ + }, + { /* 12097 */ + 218, + /* VPROLVDZ256rmk */ + }, + { /* 12098 */ + 219, + /* VPROLVDZ256rmkz */ + }, + { /* 12099 */ + 220, + /* VPROLVDZ256rr */ + }, + { /* 12100 */ + 221, + /* VPROLVDZ256rrk */ + }, + { /* 12101 */ + 222, + /* VPROLVDZ256rrkz */ + }, + { /* 12102 */ + 223, + /* VPROLVDZrm */ + }, + { /* 12103 */ + 243, + /* VPROLVDZrmb */ + }, + { /* 12104 */ + 244, + /* VPROLVDZrmbk */ + }, + { /* 12105 */ + 245, + /* VPROLVDZrmbkz */ + }, + { /* 12106 */ + 227, + /* VPROLVDZrmk */ + }, + { /* 12107 */ + 228, + /* VPROLVDZrmkz */ + }, + { /* 12108 */ + 229, + /* VPROLVDZrr */ + }, + { /* 12109 */ + 233, + /* VPROLVDZrrk */ + }, + { /* 12110 */ + 234, + /* VPROLVDZrrkz */ + }, + { /* 12111 */ + 206, + /* VPROLVQZ128rm */ + }, + { /* 12112 */ + 207, + /* VPROLVQZ128rmb */ + }, + { /* 12113 */ + 208, + /* VPROLVQZ128rmbk */ + }, + { /* 12114 */ + 209, + /* VPROLVQZ128rmbkz */ + }, + { /* 12115 */ + 203, + /* VPROLVQZ128rmk */ + }, + { /* 12116 */ + 210, + /* VPROLVQZ128rmkz */ + }, + { /* 12117 */ + 211, + /* VPROLVQZ128rr */ + }, + { /* 12118 */ + 212, + /* VPROLVQZ128rrk */ + }, + { /* 12119 */ + 213, + /* VPROLVQZ128rrkz */ + }, + { /* 12120 */ + 214, + /* VPROLVQZ256rm */ + }, + { /* 12121 */ + 215, + /* VPROLVQZ256rmb */ + }, + { /* 12122 */ + 216, + /* VPROLVQZ256rmbk */ + }, + { /* 12123 */ + 217, + /* VPROLVQZ256rmbkz */ + }, + { /* 12124 */ + 218, + /* VPROLVQZ256rmk */ + }, + { /* 12125 */ + 219, + /* VPROLVQZ256rmkz */ + }, + { /* 12126 */ + 220, + /* VPROLVQZ256rr */ + }, + { /* 12127 */ + 221, + /* VPROLVQZ256rrk */ + }, + { /* 12128 */ + 222, + /* VPROLVQZ256rrkz */ + }, + { /* 12129 */ + 223, + /* VPROLVQZrm */ + }, + { /* 12130 */ + 224, + /* VPROLVQZrmb */ + }, + { /* 12131 */ + 225, + /* VPROLVQZrmbk */ + }, + { /* 12132 */ + 226, + /* VPROLVQZrmbkz */ + }, + { /* 12133 */ + 227, + /* VPROLVQZrmk */ + }, + { /* 12134 */ + 228, + /* VPROLVQZrmkz */ + }, + { /* 12135 */ + 229, + /* VPROLVQZrr */ + }, + { /* 12136 */ + 233, + /* VPROLVQZrrk */ + }, + { /* 12137 */ + 234, + /* VPROLVQZrrkz */ + }, + { /* 12138 */ + 854, + /* VPRORDZ128mbi */ + }, + { /* 12139 */ + 855, + /* VPRORDZ128mbik */ + }, + { /* 12140 */ + 856, + /* VPRORDZ128mbikz */ + }, + { /* 12141 */ + 857, + /* VPRORDZ128mi */ + }, + { /* 12142 */ + 858, + /* VPRORDZ128mik */ + }, + { /* 12143 */ + 859, + /* VPRORDZ128mikz */ + }, + { /* 12144 */ + 860, + /* VPRORDZ128ri */ + }, + { /* 12145 */ + 861, + /* VPRORDZ128rik */ + }, + { /* 12146 */ + 862, + /* VPRORDZ128rikz */ + }, + { /* 12147 */ + 863, + /* VPRORDZ256mbi */ + }, + { /* 12148 */ + 864, + /* VPRORDZ256mbik */ + }, + { /* 12149 */ + 865, + /* VPRORDZ256mbikz */ + }, + { /* 12150 */ + 866, + /* VPRORDZ256mi */ + }, + { /* 12151 */ + 867, + /* VPRORDZ256mik */ + }, + { /* 12152 */ + 868, + /* VPRORDZ256mikz */ + }, + { /* 12153 */ + 869, + /* VPRORDZ256ri */ + }, + { /* 12154 */ + 870, + /* VPRORDZ256rik */ + }, + { /* 12155 */ + 871, + /* VPRORDZ256rikz */ + }, + { /* 12156 */ + 872, + /* VPRORDZmbi */ + }, + { /* 12157 */ + 873, + /* VPRORDZmbik */ + }, + { /* 12158 */ + 874, + /* VPRORDZmbikz */ + }, + { /* 12159 */ + 875, + /* VPRORDZmi */ + }, + { /* 12160 */ + 876, + /* VPRORDZmik */ + }, + { /* 12161 */ + 877, + /* VPRORDZmikz */ + }, + { /* 12162 */ + 878, + /* VPRORDZri */ + }, + { /* 12163 */ + 879, + /* VPRORDZrik */ + }, + { /* 12164 */ + 880, + /* VPRORDZrikz */ + }, + { /* 12165 */ + 881, + /* VPRORQZ128mbi */ + }, + { /* 12166 */ + 882, + /* VPRORQZ128mbik */ + }, + { /* 12167 */ + 883, + /* VPRORQZ128mbikz */ + }, + { /* 12168 */ + 857, + /* VPRORQZ128mi */ + }, + { /* 12169 */ + 858, + /* VPRORQZ128mik */ + }, + { /* 12170 */ + 859, + /* VPRORQZ128mikz */ + }, + { /* 12171 */ + 860, + /* VPRORQZ128ri */ + }, + { /* 12172 */ + 861, + /* VPRORQZ128rik */ + }, + { /* 12173 */ + 862, + /* VPRORQZ128rikz */ + }, + { /* 12174 */ + 884, + /* VPRORQZ256mbi */ + }, + { /* 12175 */ + 885, + /* VPRORQZ256mbik */ + }, + { /* 12176 */ + 886, + /* VPRORQZ256mbikz */ + }, + { /* 12177 */ + 866, + /* VPRORQZ256mi */ + }, + { /* 12178 */ + 867, + /* VPRORQZ256mik */ + }, + { /* 12179 */ + 868, + /* VPRORQZ256mikz */ + }, + { /* 12180 */ + 869, + /* VPRORQZ256ri */ + }, + { /* 12181 */ + 870, + /* VPRORQZ256rik */ + }, + { /* 12182 */ + 871, + /* VPRORQZ256rikz */ + }, + { /* 12183 */ + 887, + /* VPRORQZmbi */ + }, + { /* 12184 */ + 888, + /* VPRORQZmbik */ + }, + { /* 12185 */ + 889, + /* VPRORQZmbikz */ + }, + { /* 12186 */ + 875, + /* VPRORQZmi */ + }, + { /* 12187 */ + 876, + /* VPRORQZmik */ + }, + { /* 12188 */ + 877, + /* VPRORQZmikz */ + }, + { /* 12189 */ + 878, + /* VPRORQZri */ + }, + { /* 12190 */ + 879, + /* VPRORQZrik */ + }, + { /* 12191 */ + 880, + /* VPRORQZrikz */ + }, + { /* 12192 */ + 206, + /* VPRORVDZ128rm */ + }, + { /* 12193 */ + 237, + /* VPRORVDZ128rmb */ + }, + { /* 12194 */ + 238, + /* VPRORVDZ128rmbk */ + }, + { /* 12195 */ + 239, + /* VPRORVDZ128rmbkz */ + }, + { /* 12196 */ + 203, + /* VPRORVDZ128rmk */ + }, + { /* 12197 */ + 210, + /* VPRORVDZ128rmkz */ + }, + { /* 12198 */ + 211, + /* VPRORVDZ128rr */ + }, + { /* 12199 */ + 212, + /* VPRORVDZ128rrk */ + }, + { /* 12200 */ + 213, + /* VPRORVDZ128rrkz */ + }, + { /* 12201 */ + 214, + /* VPRORVDZ256rm */ + }, + { /* 12202 */ + 240, + /* VPRORVDZ256rmb */ + }, + { /* 12203 */ + 241, + /* VPRORVDZ256rmbk */ + }, + { /* 12204 */ + 242, + /* VPRORVDZ256rmbkz */ + }, + { /* 12205 */ + 218, + /* VPRORVDZ256rmk */ + }, + { /* 12206 */ + 219, + /* VPRORVDZ256rmkz */ + }, + { /* 12207 */ + 220, + /* VPRORVDZ256rr */ + }, + { /* 12208 */ + 221, + /* VPRORVDZ256rrk */ + }, + { /* 12209 */ + 222, + /* VPRORVDZ256rrkz */ + }, + { /* 12210 */ + 223, + /* VPRORVDZrm */ + }, + { /* 12211 */ + 243, + /* VPRORVDZrmb */ + }, + { /* 12212 */ + 244, + /* VPRORVDZrmbk */ + }, + { /* 12213 */ + 245, + /* VPRORVDZrmbkz */ + }, + { /* 12214 */ + 227, + /* VPRORVDZrmk */ + }, + { /* 12215 */ + 228, + /* VPRORVDZrmkz */ + }, + { /* 12216 */ + 229, + /* VPRORVDZrr */ + }, + { /* 12217 */ + 233, + /* VPRORVDZrrk */ + }, + { /* 12218 */ + 234, + /* VPRORVDZrrkz */ + }, + { /* 12219 */ + 206, + /* VPRORVQZ128rm */ + }, + { /* 12220 */ + 207, + /* VPRORVQZ128rmb */ + }, + { /* 12221 */ + 208, + /* VPRORVQZ128rmbk */ + }, + { /* 12222 */ + 209, + /* VPRORVQZ128rmbkz */ + }, + { /* 12223 */ + 203, + /* VPRORVQZ128rmk */ + }, + { /* 12224 */ + 210, + /* VPRORVQZ128rmkz */ + }, + { /* 12225 */ + 211, + /* VPRORVQZ128rr */ + }, + { /* 12226 */ + 212, + /* VPRORVQZ128rrk */ + }, + { /* 12227 */ + 213, + /* VPRORVQZ128rrkz */ + }, + { /* 12228 */ + 214, + /* VPRORVQZ256rm */ + }, + { /* 12229 */ + 215, + /* VPRORVQZ256rmb */ + }, + { /* 12230 */ + 216, + /* VPRORVQZ256rmbk */ + }, + { /* 12231 */ + 217, + /* VPRORVQZ256rmbkz */ + }, + { /* 12232 */ + 218, + /* VPRORVQZ256rmk */ + }, + { /* 12233 */ + 219, + /* VPRORVQZ256rmkz */ + }, + { /* 12234 */ + 220, + /* VPRORVQZ256rr */ + }, + { /* 12235 */ + 221, + /* VPRORVQZ256rrk */ + }, + { /* 12236 */ + 222, + /* VPRORVQZ256rrkz */ + }, + { /* 12237 */ + 223, + /* VPRORVQZrm */ + }, + { /* 12238 */ + 224, + /* VPRORVQZrmb */ + }, + { /* 12239 */ + 225, + /* VPRORVQZrmbk */ + }, + { /* 12240 */ + 226, + /* VPRORVQZrmbkz */ + }, + { /* 12241 */ + 227, + /* VPRORVQZrmk */ + }, + { /* 12242 */ + 228, + /* VPRORVQZrmkz */ + }, + { /* 12243 */ + 229, + /* VPRORVQZrr */ + }, + { /* 12244 */ + 233, + /* VPRORVQZrrk */ + }, + { /* 12245 */ + 234, + /* VPRORVQZrrkz */ + }, + { /* 12246 */ + 32, + /* VPROTBmi */ + }, + { /* 12247 */ + 890, + /* VPROTBmr */ + }, + { /* 12248 */ + 33, + /* VPROTBri */ + }, + { /* 12249 */ + 235, + /* VPROTBrm */ + }, + { /* 12250 */ + 891, + /* VPROTBrr */ + }, + { /* 12251 */ + 236, + /* VPROTBrr_REV */ + }, + { /* 12252 */ + 32, + /* VPROTDmi */ + }, + { /* 12253 */ + 890, + /* VPROTDmr */ + }, + { /* 12254 */ + 33, + /* VPROTDri */ + }, + { /* 12255 */ + 235, + /* VPROTDrm */ + }, + { /* 12256 */ + 891, + /* VPROTDrr */ + }, + { /* 12257 */ + 236, + /* VPROTDrr_REV */ + }, + { /* 12258 */ + 32, + /* VPROTQmi */ + }, + { /* 12259 */ + 890, + /* VPROTQmr */ + }, + { /* 12260 */ + 33, + /* VPROTQri */ + }, + { /* 12261 */ + 235, + /* VPROTQrm */ + }, + { /* 12262 */ + 891, + /* VPROTQrr */ + }, + { /* 12263 */ + 236, + /* VPROTQrr_REV */ + }, + { /* 12264 */ + 32, + /* VPROTWmi */ + }, + { /* 12265 */ + 890, + /* VPROTWmr */ + }, + { /* 12266 */ + 33, + /* VPROTWri */ + }, + { /* 12267 */ + 235, + /* VPROTWrm */ + }, + { /* 12268 */ + 891, + /* VPROTWrr */ + }, + { /* 12269 */ + 236, + /* VPROTWrr_REV */ + }, + { /* 12270 */ + 204, + /* VPSADBWYrm */ + }, + { /* 12271 */ + 205, + /* VPSADBWYrr */ + }, + { /* 12272 */ + 206, + /* VPSADBWZ128rm */ + }, + { /* 12273 */ + 211, + /* VPSADBWZ128rr */ + }, + { /* 12274 */ + 214, + /* VPSADBWZ256rm */ + }, + { /* 12275 */ + 220, + /* VPSADBWZ256rr */ + }, + { /* 12276 */ + 223, + /* VPSADBWZrm */ + }, + { /* 12277 */ + 229, + /* VPSADBWZrr */ + }, + { /* 12278 */ + 235, + /* VPSADBWrm */ + }, + { /* 12279 */ + 236, + /* VPSADBWrr */ + }, + { /* 12280 */ + 892, + /* VPSCATTERDDZ128mr */ + }, + { /* 12281 */ + 893, + /* VPSCATTERDDZ256mr */ + }, + { /* 12282 */ + 894, + /* VPSCATTERDDZmr */ + }, + { /* 12283 */ + 895, + /* VPSCATTERDQZ128mr */ + }, + { /* 12284 */ + 896, + /* VPSCATTERDQZ256mr */ + }, + { /* 12285 */ + 897, + /* VPSCATTERDQZmr */ + }, + { /* 12286 */ + 892, + /* VPSCATTERQDZ128mr */ + }, + { /* 12287 */ + 898, + /* VPSCATTERQDZ256mr */ + }, + { /* 12288 */ + 899, + /* VPSCATTERQDZmr */ + }, + { /* 12289 */ + 895, + /* VPSCATTERQQZ128mr */ + }, + { /* 12290 */ + 900, + /* VPSCATTERQQZ256mr */ + }, + { /* 12291 */ + 901, + /* VPSCATTERQQZmr */ + }, + { /* 12292 */ + 890, + /* VPSHABmr */ + }, + { /* 12293 */ + 235, + /* VPSHABrm */ + }, + { /* 12294 */ + 891, + /* VPSHABrr */ + }, + { /* 12295 */ + 236, + /* VPSHABrr_REV */ + }, + { /* 12296 */ + 890, + /* VPSHADmr */ + }, + { /* 12297 */ + 235, + /* VPSHADrm */ + }, + { /* 12298 */ + 891, + /* VPSHADrr */ + }, + { /* 12299 */ + 236, + /* VPSHADrr_REV */ + }, + { /* 12300 */ + 890, + /* VPSHAQmr */ + }, + { /* 12301 */ + 235, + /* VPSHAQrm */ + }, + { /* 12302 */ + 891, + /* VPSHAQrr */ + }, + { /* 12303 */ + 236, + /* VPSHAQrr_REV */ + }, + { /* 12304 */ + 890, + /* VPSHAWmr */ + }, + { /* 12305 */ + 235, + /* VPSHAWrm */ + }, + { /* 12306 */ + 891, + /* VPSHAWrr */ + }, + { /* 12307 */ + 236, + /* VPSHAWrr_REV */ + }, + { /* 12308 */ + 890, + /* VPSHLBmr */ + }, + { /* 12309 */ + 235, + /* VPSHLBrm */ + }, + { /* 12310 */ + 891, + /* VPSHLBrr */ + }, + { /* 12311 */ + 236, + /* VPSHLBrr_REV */ + }, + { /* 12312 */ + 261, + /* VPSHLDDZ128rmbi */ + }, + { /* 12313 */ + 262, + /* VPSHLDDZ128rmbik */ + }, + { /* 12314 */ + 263, + /* VPSHLDDZ128rmbikz */ + }, + { /* 12315 */ + 264, + /* VPSHLDDZ128rmi */ + }, + { /* 12316 */ + 265, + /* VPSHLDDZ128rmik */ + }, + { /* 12317 */ + 266, + /* VPSHLDDZ128rmikz */ + }, + { /* 12318 */ + 267, + /* VPSHLDDZ128rri */ + }, + { /* 12319 */ + 268, + /* VPSHLDDZ128rrik */ + }, + { /* 12320 */ + 269, + /* VPSHLDDZ128rrikz */ + }, + { /* 12321 */ + 270, + /* VPSHLDDZ256rmbi */ + }, + { /* 12322 */ + 271, + /* VPSHLDDZ256rmbik */ + }, + { /* 12323 */ + 272, + /* VPSHLDDZ256rmbikz */ + }, + { /* 12324 */ + 273, + /* VPSHLDDZ256rmi */ + }, + { /* 12325 */ + 274, + /* VPSHLDDZ256rmik */ + }, + { /* 12326 */ + 275, + /* VPSHLDDZ256rmikz */ + }, + { /* 12327 */ + 276, + /* VPSHLDDZ256rri */ + }, + { /* 12328 */ + 277, + /* VPSHLDDZ256rrik */ + }, + { /* 12329 */ + 278, + /* VPSHLDDZ256rrikz */ + }, + { /* 12330 */ + 279, + /* VPSHLDDZrmbi */ + }, + { /* 12331 */ + 280, + /* VPSHLDDZrmbik */ + }, + { /* 12332 */ + 281, + /* VPSHLDDZrmbikz */ + }, + { /* 12333 */ + 282, + /* VPSHLDDZrmi */ + }, + { /* 12334 */ + 283, + /* VPSHLDDZrmik */ + }, + { /* 12335 */ + 284, + /* VPSHLDDZrmikz */ + }, + { /* 12336 */ + 285, + /* VPSHLDDZrri */ + }, + { /* 12337 */ + 286, + /* VPSHLDDZrrik */ + }, + { /* 12338 */ + 287, + /* VPSHLDDZrrikz */ + }, + { /* 12339 */ + 288, + /* VPSHLDQZ128rmbi */ + }, + { /* 12340 */ + 289, + /* VPSHLDQZ128rmbik */ + }, + { /* 12341 */ + 290, + /* VPSHLDQZ128rmbikz */ + }, + { /* 12342 */ + 264, + /* VPSHLDQZ128rmi */ + }, + { /* 12343 */ + 265, + /* VPSHLDQZ128rmik */ + }, + { /* 12344 */ + 266, + /* VPSHLDQZ128rmikz */ + }, + { /* 12345 */ + 267, + /* VPSHLDQZ128rri */ + }, + { /* 12346 */ + 268, + /* VPSHLDQZ128rrik */ + }, + { /* 12347 */ + 269, + /* VPSHLDQZ128rrikz */ + }, + { /* 12348 */ + 291, + /* VPSHLDQZ256rmbi */ + }, + { /* 12349 */ + 292, + /* VPSHLDQZ256rmbik */ + }, + { /* 12350 */ + 293, + /* VPSHLDQZ256rmbikz */ + }, + { /* 12351 */ + 273, + /* VPSHLDQZ256rmi */ + }, + { /* 12352 */ + 274, + /* VPSHLDQZ256rmik */ + }, + { /* 12353 */ + 275, + /* VPSHLDQZ256rmikz */ + }, + { /* 12354 */ + 276, + /* VPSHLDQZ256rri */ + }, + { /* 12355 */ + 277, + /* VPSHLDQZ256rrik */ + }, + { /* 12356 */ + 278, + /* VPSHLDQZ256rrikz */ + }, + { /* 12357 */ + 294, + /* VPSHLDQZrmbi */ + }, + { /* 12358 */ + 295, + /* VPSHLDQZrmbik */ + }, + { /* 12359 */ + 296, + /* VPSHLDQZrmbikz */ + }, + { /* 12360 */ + 282, + /* VPSHLDQZrmi */ + }, + { /* 12361 */ + 283, + /* VPSHLDQZrmik */ + }, + { /* 12362 */ + 284, + /* VPSHLDQZrmikz */ + }, + { /* 12363 */ + 285, + /* VPSHLDQZrri */ + }, + { /* 12364 */ + 286, + /* VPSHLDQZrrik */ + }, + { /* 12365 */ + 287, + /* VPSHLDQZrrikz */ + }, + { /* 12366 */ + 202, + /* VPSHLDVDZ128m */ + }, + { /* 12367 */ + 540, + /* VPSHLDVDZ128mb */ + }, + { /* 12368 */ + 238, + /* VPSHLDVDZ128mbk */ + }, + { /* 12369 */ + 238, + /* VPSHLDVDZ128mbkz */ + }, + { /* 12370 */ + 203, + /* VPSHLDVDZ128mk */ + }, + { /* 12371 */ + 203, + /* VPSHLDVDZ128mkz */ + }, + { /* 12372 */ + 530, + /* VPSHLDVDZ128r */ + }, + { /* 12373 */ + 212, + /* VPSHLDVDZ128rk */ + }, + { /* 12374 */ + 212, + /* VPSHLDVDZ128rkz */ + }, + { /* 12375 */ + 531, + /* VPSHLDVDZ256m */ + }, + { /* 12376 */ + 541, + /* VPSHLDVDZ256mb */ + }, + { /* 12377 */ + 241, + /* VPSHLDVDZ256mbk */ + }, + { /* 12378 */ + 241, + /* VPSHLDVDZ256mbkz */ + }, + { /* 12379 */ + 218, + /* VPSHLDVDZ256mk */ + }, + { /* 12380 */ + 218, + /* VPSHLDVDZ256mkz */ + }, + { /* 12381 */ + 533, + /* VPSHLDVDZ256r */ + }, + { /* 12382 */ + 221, + /* VPSHLDVDZ256rk */ + }, + { /* 12383 */ + 221, + /* VPSHLDVDZ256rkz */ + }, + { /* 12384 */ + 534, + /* VPSHLDVDZm */ + }, + { /* 12385 */ + 542, + /* VPSHLDVDZmb */ + }, + { /* 12386 */ + 244, + /* VPSHLDVDZmbk */ + }, + { /* 12387 */ + 244, + /* VPSHLDVDZmbkz */ + }, + { /* 12388 */ + 227, + /* VPSHLDVDZmk */ + }, + { /* 12389 */ + 227, + /* VPSHLDVDZmkz */ + }, + { /* 12390 */ + 536, + /* VPSHLDVDZr */ + }, + { /* 12391 */ + 233, + /* VPSHLDVDZrk */ + }, + { /* 12392 */ + 233, + /* VPSHLDVDZrkz */ + }, + { /* 12393 */ + 202, + /* VPSHLDVQZ128m */ + }, + { /* 12394 */ + 529, + /* VPSHLDVQZ128mb */ + }, + { /* 12395 */ + 208, + /* VPSHLDVQZ128mbk */ + }, + { /* 12396 */ + 208, + /* VPSHLDVQZ128mbkz */ + }, + { /* 12397 */ + 203, + /* VPSHLDVQZ128mk */ + }, + { /* 12398 */ + 203, + /* VPSHLDVQZ128mkz */ + }, + { /* 12399 */ + 530, + /* VPSHLDVQZ128r */ + }, + { /* 12400 */ + 212, + /* VPSHLDVQZ128rk */ + }, + { /* 12401 */ + 212, + /* VPSHLDVQZ128rkz */ + }, + { /* 12402 */ + 531, + /* VPSHLDVQZ256m */ + }, + { /* 12403 */ + 532, + /* VPSHLDVQZ256mb */ + }, + { /* 12404 */ + 216, + /* VPSHLDVQZ256mbk */ + }, + { /* 12405 */ + 216, + /* VPSHLDVQZ256mbkz */ + }, + { /* 12406 */ + 218, + /* VPSHLDVQZ256mk */ + }, + { /* 12407 */ + 218, + /* VPSHLDVQZ256mkz */ + }, + { /* 12408 */ + 533, + /* VPSHLDVQZ256r */ + }, + { /* 12409 */ + 221, + /* VPSHLDVQZ256rk */ + }, + { /* 12410 */ + 221, + /* VPSHLDVQZ256rkz */ + }, + { /* 12411 */ + 534, + /* VPSHLDVQZm */ + }, + { /* 12412 */ + 535, + /* VPSHLDVQZmb */ + }, + { /* 12413 */ + 225, + /* VPSHLDVQZmbk */ + }, + { /* 12414 */ + 225, + /* VPSHLDVQZmbkz */ + }, + { /* 12415 */ + 227, + /* VPSHLDVQZmk */ + }, + { /* 12416 */ + 227, + /* VPSHLDVQZmkz */ + }, + { /* 12417 */ + 536, + /* VPSHLDVQZr */ + }, + { /* 12418 */ + 233, + /* VPSHLDVQZrk */ + }, + { /* 12419 */ + 233, + /* VPSHLDVQZrkz */ + }, + { /* 12420 */ + 202, + /* VPSHLDVWZ128m */ + }, + { /* 12421 */ + 203, + /* VPSHLDVWZ128mk */ + }, + { /* 12422 */ + 203, + /* VPSHLDVWZ128mkz */ + }, + { /* 12423 */ + 530, + /* VPSHLDVWZ128r */ + }, + { /* 12424 */ + 212, + /* VPSHLDVWZ128rk */ + }, + { /* 12425 */ + 212, + /* VPSHLDVWZ128rkz */ + }, + { /* 12426 */ + 531, + /* VPSHLDVWZ256m */ + }, + { /* 12427 */ + 218, + /* VPSHLDVWZ256mk */ + }, + { /* 12428 */ + 218, + /* VPSHLDVWZ256mkz */ + }, + { /* 12429 */ + 533, + /* VPSHLDVWZ256r */ + }, + { /* 12430 */ + 221, + /* VPSHLDVWZ256rk */ + }, + { /* 12431 */ + 221, + /* VPSHLDVWZ256rkz */ + }, + { /* 12432 */ + 534, + /* VPSHLDVWZm */ + }, + { /* 12433 */ + 227, + /* VPSHLDVWZmk */ + }, + { /* 12434 */ + 227, + /* VPSHLDVWZmkz */ + }, + { /* 12435 */ + 536, + /* VPSHLDVWZr */ + }, + { /* 12436 */ + 233, + /* VPSHLDVWZrk */ + }, + { /* 12437 */ + 233, + /* VPSHLDVWZrkz */ + }, + { /* 12438 */ + 264, + /* VPSHLDWZ128rmi */ + }, + { /* 12439 */ + 265, + /* VPSHLDWZ128rmik */ + }, + { /* 12440 */ + 266, + /* VPSHLDWZ128rmikz */ + }, + { /* 12441 */ + 267, + /* VPSHLDWZ128rri */ + }, + { /* 12442 */ + 268, + /* VPSHLDWZ128rrik */ + }, + { /* 12443 */ + 269, + /* VPSHLDWZ128rrikz */ + }, + { /* 12444 */ + 273, + /* VPSHLDWZ256rmi */ + }, + { /* 12445 */ + 274, + /* VPSHLDWZ256rmik */ + }, + { /* 12446 */ + 275, + /* VPSHLDWZ256rmikz */ + }, + { /* 12447 */ + 276, + /* VPSHLDWZ256rri */ + }, + { /* 12448 */ + 277, + /* VPSHLDWZ256rrik */ + }, + { /* 12449 */ + 278, + /* VPSHLDWZ256rrikz */ + }, + { /* 12450 */ + 282, + /* VPSHLDWZrmi */ + }, + { /* 12451 */ + 283, + /* VPSHLDWZrmik */ + }, + { /* 12452 */ + 284, + /* VPSHLDWZrmikz */ + }, + { /* 12453 */ + 285, + /* VPSHLDWZrri */ + }, + { /* 12454 */ + 286, + /* VPSHLDWZrrik */ + }, + { /* 12455 */ + 287, + /* VPSHLDWZrrikz */ + }, + { /* 12456 */ + 890, + /* VPSHLDmr */ + }, + { /* 12457 */ + 235, + /* VPSHLDrm */ + }, + { /* 12458 */ + 891, + /* VPSHLDrr */ + }, + { /* 12459 */ + 236, + /* VPSHLDrr_REV */ + }, + { /* 12460 */ + 890, + /* VPSHLQmr */ + }, + { /* 12461 */ + 235, + /* VPSHLQrm */ + }, + { /* 12462 */ + 891, + /* VPSHLQrr */ + }, + { /* 12463 */ + 236, + /* VPSHLQrr_REV */ + }, + { /* 12464 */ + 890, + /* VPSHLWmr */ + }, + { /* 12465 */ + 235, + /* VPSHLWrm */ + }, + { /* 12466 */ + 891, + /* VPSHLWrr */ + }, + { /* 12467 */ + 236, + /* VPSHLWrr_REV */ + }, + { /* 12468 */ + 261, + /* VPSHRDDZ128rmbi */ + }, + { /* 12469 */ + 262, + /* VPSHRDDZ128rmbik */ + }, + { /* 12470 */ + 263, + /* VPSHRDDZ128rmbikz */ + }, + { /* 12471 */ + 264, + /* VPSHRDDZ128rmi */ + }, + { /* 12472 */ + 265, + /* VPSHRDDZ128rmik */ + }, + { /* 12473 */ + 266, + /* VPSHRDDZ128rmikz */ + }, + { /* 12474 */ + 267, + /* VPSHRDDZ128rri */ + }, + { /* 12475 */ + 268, + /* VPSHRDDZ128rrik */ + }, + { /* 12476 */ + 269, + /* VPSHRDDZ128rrikz */ + }, + { /* 12477 */ + 270, + /* VPSHRDDZ256rmbi */ + }, + { /* 12478 */ + 271, + /* VPSHRDDZ256rmbik */ + }, + { /* 12479 */ + 272, + /* VPSHRDDZ256rmbikz */ + }, + { /* 12480 */ + 273, + /* VPSHRDDZ256rmi */ + }, + { /* 12481 */ + 274, + /* VPSHRDDZ256rmik */ + }, + { /* 12482 */ + 275, + /* VPSHRDDZ256rmikz */ + }, + { /* 12483 */ + 276, + /* VPSHRDDZ256rri */ + }, + { /* 12484 */ + 277, + /* VPSHRDDZ256rrik */ + }, + { /* 12485 */ + 278, + /* VPSHRDDZ256rrikz */ + }, + { /* 12486 */ + 279, + /* VPSHRDDZrmbi */ + }, + { /* 12487 */ + 280, + /* VPSHRDDZrmbik */ + }, + { /* 12488 */ + 281, + /* VPSHRDDZrmbikz */ + }, + { /* 12489 */ + 282, + /* VPSHRDDZrmi */ + }, + { /* 12490 */ + 283, + /* VPSHRDDZrmik */ + }, + { /* 12491 */ + 284, + /* VPSHRDDZrmikz */ + }, + { /* 12492 */ + 285, + /* VPSHRDDZrri */ + }, + { /* 12493 */ + 286, + /* VPSHRDDZrrik */ + }, + { /* 12494 */ + 287, + /* VPSHRDDZrrikz */ + }, + { /* 12495 */ + 288, + /* VPSHRDQZ128rmbi */ + }, + { /* 12496 */ + 289, + /* VPSHRDQZ128rmbik */ + }, + { /* 12497 */ + 290, + /* VPSHRDQZ128rmbikz */ + }, + { /* 12498 */ + 264, + /* VPSHRDQZ128rmi */ + }, + { /* 12499 */ + 265, + /* VPSHRDQZ128rmik */ + }, + { /* 12500 */ + 266, + /* VPSHRDQZ128rmikz */ + }, + { /* 12501 */ + 267, + /* VPSHRDQZ128rri */ + }, + { /* 12502 */ + 268, + /* VPSHRDQZ128rrik */ + }, + { /* 12503 */ + 269, + /* VPSHRDQZ128rrikz */ + }, + { /* 12504 */ + 291, + /* VPSHRDQZ256rmbi */ + }, + { /* 12505 */ + 292, + /* VPSHRDQZ256rmbik */ + }, + { /* 12506 */ + 293, + /* VPSHRDQZ256rmbikz */ + }, + { /* 12507 */ + 273, + /* VPSHRDQZ256rmi */ + }, + { /* 12508 */ + 274, + /* VPSHRDQZ256rmik */ + }, + { /* 12509 */ + 275, + /* VPSHRDQZ256rmikz */ + }, + { /* 12510 */ + 276, + /* VPSHRDQZ256rri */ + }, + { /* 12511 */ + 277, + /* VPSHRDQZ256rrik */ + }, + { /* 12512 */ + 278, + /* VPSHRDQZ256rrikz */ + }, + { /* 12513 */ + 294, + /* VPSHRDQZrmbi */ + }, + { /* 12514 */ + 295, + /* VPSHRDQZrmbik */ + }, + { /* 12515 */ + 296, + /* VPSHRDQZrmbikz */ + }, + { /* 12516 */ + 282, + /* VPSHRDQZrmi */ + }, + { /* 12517 */ + 283, + /* VPSHRDQZrmik */ + }, + { /* 12518 */ + 284, + /* VPSHRDQZrmikz */ + }, + { /* 12519 */ + 285, + /* VPSHRDQZrri */ + }, + { /* 12520 */ + 286, + /* VPSHRDQZrrik */ + }, + { /* 12521 */ + 287, + /* VPSHRDQZrrikz */ + }, + { /* 12522 */ + 202, + /* VPSHRDVDZ128m */ + }, + { /* 12523 */ + 540, + /* VPSHRDVDZ128mb */ + }, + { /* 12524 */ + 238, + /* VPSHRDVDZ128mbk */ + }, + { /* 12525 */ + 238, + /* VPSHRDVDZ128mbkz */ + }, + { /* 12526 */ + 203, + /* VPSHRDVDZ128mk */ + }, + { /* 12527 */ + 203, + /* VPSHRDVDZ128mkz */ + }, + { /* 12528 */ + 530, + /* VPSHRDVDZ128r */ + }, + { /* 12529 */ + 212, + /* VPSHRDVDZ128rk */ + }, + { /* 12530 */ + 212, + /* VPSHRDVDZ128rkz */ + }, + { /* 12531 */ + 531, + /* VPSHRDVDZ256m */ + }, + { /* 12532 */ + 541, + /* VPSHRDVDZ256mb */ + }, + { /* 12533 */ + 241, + /* VPSHRDVDZ256mbk */ + }, + { /* 12534 */ + 241, + /* VPSHRDVDZ256mbkz */ + }, + { /* 12535 */ + 218, + /* VPSHRDVDZ256mk */ + }, + { /* 12536 */ + 218, + /* VPSHRDVDZ256mkz */ + }, + { /* 12537 */ + 533, + /* VPSHRDVDZ256r */ + }, + { /* 12538 */ + 221, + /* VPSHRDVDZ256rk */ + }, + { /* 12539 */ + 221, + /* VPSHRDVDZ256rkz */ + }, + { /* 12540 */ + 534, + /* VPSHRDVDZm */ + }, + { /* 12541 */ + 542, + /* VPSHRDVDZmb */ + }, + { /* 12542 */ + 244, + /* VPSHRDVDZmbk */ + }, + { /* 12543 */ + 244, + /* VPSHRDVDZmbkz */ + }, + { /* 12544 */ + 227, + /* VPSHRDVDZmk */ + }, + { /* 12545 */ + 227, + /* VPSHRDVDZmkz */ + }, + { /* 12546 */ + 536, + /* VPSHRDVDZr */ + }, + { /* 12547 */ + 233, + /* VPSHRDVDZrk */ + }, + { /* 12548 */ + 233, + /* VPSHRDVDZrkz */ + }, + { /* 12549 */ + 202, + /* VPSHRDVQZ128m */ + }, + { /* 12550 */ + 529, + /* VPSHRDVQZ128mb */ + }, + { /* 12551 */ + 208, + /* VPSHRDVQZ128mbk */ + }, + { /* 12552 */ + 208, + /* VPSHRDVQZ128mbkz */ + }, + { /* 12553 */ + 203, + /* VPSHRDVQZ128mk */ + }, + { /* 12554 */ + 203, + /* VPSHRDVQZ128mkz */ + }, + { /* 12555 */ + 530, + /* VPSHRDVQZ128r */ + }, + { /* 12556 */ + 212, + /* VPSHRDVQZ128rk */ + }, + { /* 12557 */ + 212, + /* VPSHRDVQZ128rkz */ + }, + { /* 12558 */ + 531, + /* VPSHRDVQZ256m */ + }, + { /* 12559 */ + 532, + /* VPSHRDVQZ256mb */ + }, + { /* 12560 */ + 216, + /* VPSHRDVQZ256mbk */ + }, + { /* 12561 */ + 216, + /* VPSHRDVQZ256mbkz */ + }, + { /* 12562 */ + 218, + /* VPSHRDVQZ256mk */ + }, + { /* 12563 */ + 218, + /* VPSHRDVQZ256mkz */ + }, + { /* 12564 */ + 533, + /* VPSHRDVQZ256r */ + }, + { /* 12565 */ + 221, + /* VPSHRDVQZ256rk */ + }, + { /* 12566 */ + 221, + /* VPSHRDVQZ256rkz */ + }, + { /* 12567 */ + 534, + /* VPSHRDVQZm */ + }, + { /* 12568 */ + 535, + /* VPSHRDVQZmb */ + }, + { /* 12569 */ + 225, + /* VPSHRDVQZmbk */ + }, + { /* 12570 */ + 225, + /* VPSHRDVQZmbkz */ + }, + { /* 12571 */ + 227, + /* VPSHRDVQZmk */ + }, + { /* 12572 */ + 227, + /* VPSHRDVQZmkz */ + }, + { /* 12573 */ + 536, + /* VPSHRDVQZr */ + }, + { /* 12574 */ + 233, + /* VPSHRDVQZrk */ + }, + { /* 12575 */ + 233, + /* VPSHRDVQZrkz */ + }, + { /* 12576 */ + 202, + /* VPSHRDVWZ128m */ + }, + { /* 12577 */ + 203, + /* VPSHRDVWZ128mk */ + }, + { /* 12578 */ + 203, + /* VPSHRDVWZ128mkz */ + }, + { /* 12579 */ + 530, + /* VPSHRDVWZ128r */ + }, + { /* 12580 */ + 212, + /* VPSHRDVWZ128rk */ + }, + { /* 12581 */ + 212, + /* VPSHRDVWZ128rkz */ + }, + { /* 12582 */ + 531, + /* VPSHRDVWZ256m */ + }, + { /* 12583 */ + 218, + /* VPSHRDVWZ256mk */ + }, + { /* 12584 */ + 218, + /* VPSHRDVWZ256mkz */ + }, + { /* 12585 */ + 533, + /* VPSHRDVWZ256r */ + }, + { /* 12586 */ + 221, + /* VPSHRDVWZ256rk */ + }, + { /* 12587 */ + 221, + /* VPSHRDVWZ256rkz */ + }, + { /* 12588 */ + 534, + /* VPSHRDVWZm */ + }, + { /* 12589 */ + 227, + /* VPSHRDVWZmk */ + }, + { /* 12590 */ + 227, + /* VPSHRDVWZmkz */ + }, + { /* 12591 */ + 536, + /* VPSHRDVWZr */ + }, + { /* 12592 */ + 233, + /* VPSHRDVWZrk */ + }, + { /* 12593 */ + 233, + /* VPSHRDVWZrkz */ + }, + { /* 12594 */ + 264, + /* VPSHRDWZ128rmi */ + }, + { /* 12595 */ + 265, + /* VPSHRDWZ128rmik */ + }, + { /* 12596 */ + 266, + /* VPSHRDWZ128rmikz */ + }, + { /* 12597 */ + 267, + /* VPSHRDWZ128rri */ + }, + { /* 12598 */ + 268, + /* VPSHRDWZ128rrik */ + }, + { /* 12599 */ + 269, + /* VPSHRDWZ128rrikz */ + }, + { /* 12600 */ + 273, + /* VPSHRDWZ256rmi */ + }, + { /* 12601 */ + 274, + /* VPSHRDWZ256rmik */ + }, + { /* 12602 */ + 275, + /* VPSHRDWZ256rmikz */ + }, + { /* 12603 */ + 276, + /* VPSHRDWZ256rri */ + }, + { /* 12604 */ + 277, + /* VPSHRDWZ256rrik */ + }, + { /* 12605 */ + 278, + /* VPSHRDWZ256rrikz */ + }, + { /* 12606 */ + 282, + /* VPSHRDWZrmi */ + }, + { /* 12607 */ + 283, + /* VPSHRDWZrmik */ + }, + { /* 12608 */ + 284, + /* VPSHRDWZrmikz */ + }, + { /* 12609 */ + 285, + /* VPSHRDWZrri */ + }, + { /* 12610 */ + 286, + /* VPSHRDWZrrik */ + }, + { /* 12611 */ + 287, + /* VPSHRDWZrrikz */ + }, + { /* 12612 */ + 741, + /* VPSHUFBITQMBZ128rm */ + }, + { /* 12613 */ + 742, + /* VPSHUFBITQMBZ128rmk */ + }, + { /* 12614 */ + 743, + /* VPSHUFBITQMBZ128rr */ + }, + { /* 12615 */ + 744, + /* VPSHUFBITQMBZ128rrk */ + }, + { /* 12616 */ + 745, + /* VPSHUFBITQMBZ256rm */ + }, + { /* 12617 */ + 746, + /* VPSHUFBITQMBZ256rmk */ + }, + { /* 12618 */ + 747, + /* VPSHUFBITQMBZ256rr */ + }, + { /* 12619 */ + 748, + /* VPSHUFBITQMBZ256rrk */ + }, + { /* 12620 */ + 749, + /* VPSHUFBITQMBZrm */ + }, + { /* 12621 */ + 750, + /* VPSHUFBITQMBZrmk */ + }, + { /* 12622 */ + 751, + /* VPSHUFBITQMBZrr */ + }, + { /* 12623 */ + 752, + /* VPSHUFBITQMBZrrk */ + }, + { /* 12624 */ + 204, + /* VPSHUFBYrm */ + }, + { /* 12625 */ + 205, + /* VPSHUFBYrr */ + }, + { /* 12626 */ + 206, + /* VPSHUFBZ128rm */ + }, + { /* 12627 */ + 203, + /* VPSHUFBZ128rmk */ + }, + { /* 12628 */ + 210, + /* VPSHUFBZ128rmkz */ + }, + { /* 12629 */ + 211, + /* VPSHUFBZ128rr */ + }, + { /* 12630 */ + 212, + /* VPSHUFBZ128rrk */ + }, + { /* 12631 */ + 213, + /* VPSHUFBZ128rrkz */ + }, + { /* 12632 */ + 214, + /* VPSHUFBZ256rm */ + }, + { /* 12633 */ + 218, + /* VPSHUFBZ256rmk */ + }, + { /* 12634 */ + 219, + /* VPSHUFBZ256rmkz */ + }, + { /* 12635 */ + 220, + /* VPSHUFBZ256rr */ + }, + { /* 12636 */ + 221, + /* VPSHUFBZ256rrk */ + }, + { /* 12637 */ + 222, + /* VPSHUFBZ256rrkz */ + }, + { /* 12638 */ + 223, + /* VPSHUFBZrm */ + }, + { /* 12639 */ + 227, + /* VPSHUFBZrmk */ + }, + { /* 12640 */ + 228, + /* VPSHUFBZrmkz */ + }, + { /* 12641 */ + 229, + /* VPSHUFBZrr */ + }, + { /* 12642 */ + 233, + /* VPSHUFBZrrk */ + }, + { /* 12643 */ + 234, + /* VPSHUFBZrrkz */ + }, + { /* 12644 */ + 235, + /* VPSHUFBrm */ + }, + { /* 12645 */ + 236, + /* VPSHUFBrr */ + }, + { /* 12646 */ + 791, + /* VPSHUFDYmi */ + }, + { /* 12647 */ + 792, + /* VPSHUFDYri */ + }, + { /* 12648 */ + 619, + /* VPSHUFDZ128mbi */ + }, + { /* 12649 */ + 620, + /* VPSHUFDZ128mbik */ + }, + { /* 12650 */ + 621, + /* VPSHUFDZ128mbikz */ + }, + { /* 12651 */ + 592, + /* VPSHUFDZ128mi */ + }, + { /* 12652 */ + 593, + /* VPSHUFDZ128mik */ + }, + { /* 12653 */ + 594, + /* VPSHUFDZ128mikz */ + }, + { /* 12654 */ + 595, + /* VPSHUFDZ128ri */ + }, + { /* 12655 */ + 596, + /* VPSHUFDZ128rik */ + }, + { /* 12656 */ + 597, + /* VPSHUFDZ128rikz */ + }, + { /* 12657 */ + 622, + /* VPSHUFDZ256mbi */ + }, + { /* 12658 */ + 623, + /* VPSHUFDZ256mbik */ + }, + { /* 12659 */ + 624, + /* VPSHUFDZ256mbikz */ + }, + { /* 12660 */ + 601, + /* VPSHUFDZ256mi */ + }, + { /* 12661 */ + 602, + /* VPSHUFDZ256mik */ + }, + { /* 12662 */ + 603, + /* VPSHUFDZ256mikz */ + }, + { /* 12663 */ + 604, + /* VPSHUFDZ256ri */ + }, + { /* 12664 */ + 605, + /* VPSHUFDZ256rik */ + }, + { /* 12665 */ + 606, + /* VPSHUFDZ256rikz */ + }, + { /* 12666 */ + 625, + /* VPSHUFDZmbi */ + }, + { /* 12667 */ + 626, + /* VPSHUFDZmbik */ + }, + { /* 12668 */ + 627, + /* VPSHUFDZmbikz */ + }, + { /* 12669 */ + 610, + /* VPSHUFDZmi */ + }, + { /* 12670 */ + 611, + /* VPSHUFDZmik */ + }, + { /* 12671 */ + 612, + /* VPSHUFDZmikz */ + }, + { /* 12672 */ + 613, + /* VPSHUFDZri */ + }, + { /* 12673 */ + 617, + /* VPSHUFDZrik */ + }, + { /* 12674 */ + 618, + /* VPSHUFDZrikz */ + }, + { /* 12675 */ + 32, + /* VPSHUFDmi */ + }, + { /* 12676 */ + 33, + /* VPSHUFDri */ + }, + { /* 12677 */ + 791, + /* VPSHUFHWYmi */ + }, + { /* 12678 */ + 792, + /* VPSHUFHWYri */ + }, + { /* 12679 */ + 592, + /* VPSHUFHWZ128mi */ + }, + { /* 12680 */ + 593, + /* VPSHUFHWZ128mik */ + }, + { /* 12681 */ + 594, + /* VPSHUFHWZ128mikz */ + }, + { /* 12682 */ + 595, + /* VPSHUFHWZ128ri */ + }, + { /* 12683 */ + 596, + /* VPSHUFHWZ128rik */ + }, + { /* 12684 */ + 597, + /* VPSHUFHWZ128rikz */ + }, + { /* 12685 */ + 601, + /* VPSHUFHWZ256mi */ + }, + { /* 12686 */ + 602, + /* VPSHUFHWZ256mik */ + }, + { /* 12687 */ + 603, + /* VPSHUFHWZ256mikz */ + }, + { /* 12688 */ + 604, + /* VPSHUFHWZ256ri */ + }, + { /* 12689 */ + 605, + /* VPSHUFHWZ256rik */ + }, + { /* 12690 */ + 606, + /* VPSHUFHWZ256rikz */ + }, + { /* 12691 */ + 610, + /* VPSHUFHWZmi */ + }, + { /* 12692 */ + 611, + /* VPSHUFHWZmik */ + }, + { /* 12693 */ + 612, + /* VPSHUFHWZmikz */ + }, + { /* 12694 */ + 613, + /* VPSHUFHWZri */ + }, + { /* 12695 */ + 617, + /* VPSHUFHWZrik */ + }, + { /* 12696 */ + 618, + /* VPSHUFHWZrikz */ + }, + { /* 12697 */ + 32, + /* VPSHUFHWmi */ + }, + { /* 12698 */ + 33, + /* VPSHUFHWri */ + }, + { /* 12699 */ + 791, + /* VPSHUFLWYmi */ + }, + { /* 12700 */ + 792, + /* VPSHUFLWYri */ + }, + { /* 12701 */ + 592, + /* VPSHUFLWZ128mi */ + }, + { /* 12702 */ + 593, + /* VPSHUFLWZ128mik */ + }, + { /* 12703 */ + 594, + /* VPSHUFLWZ128mikz */ + }, + { /* 12704 */ + 595, + /* VPSHUFLWZ128ri */ + }, + { /* 12705 */ + 596, + /* VPSHUFLWZ128rik */ + }, + { /* 12706 */ + 597, + /* VPSHUFLWZ128rikz */ + }, + { /* 12707 */ + 601, + /* VPSHUFLWZ256mi */ + }, + { /* 12708 */ + 602, + /* VPSHUFLWZ256mik */ + }, + { /* 12709 */ + 603, + /* VPSHUFLWZ256mikz */ + }, + { /* 12710 */ + 604, + /* VPSHUFLWZ256ri */ + }, + { /* 12711 */ + 605, + /* VPSHUFLWZ256rik */ + }, + { /* 12712 */ + 606, + /* VPSHUFLWZ256rikz */ + }, + { /* 12713 */ + 610, + /* VPSHUFLWZmi */ + }, + { /* 12714 */ + 611, + /* VPSHUFLWZmik */ + }, + { /* 12715 */ + 612, + /* VPSHUFLWZmikz */ + }, + { /* 12716 */ + 613, + /* VPSHUFLWZri */ + }, + { /* 12717 */ + 617, + /* VPSHUFLWZrik */ + }, + { /* 12718 */ + 618, + /* VPSHUFLWZrikz */ + }, + { /* 12719 */ + 32, + /* VPSHUFLWmi */ + }, + { /* 12720 */ + 33, + /* VPSHUFLWri */ + }, + { /* 12721 */ + 204, + /* VPSIGNBYrm */ + }, + { /* 12722 */ + 205, + /* VPSIGNBYrr */ + }, + { /* 12723 */ + 235, + /* VPSIGNBrm */ + }, + { /* 12724 */ + 236, + /* VPSIGNBrr */ + }, + { /* 12725 */ + 204, + /* VPSIGNDYrm */ + }, + { /* 12726 */ + 205, + /* VPSIGNDYrr */ + }, + { /* 12727 */ + 235, + /* VPSIGNDrm */ + }, + { /* 12728 */ + 236, + /* VPSIGNDrr */ + }, + { /* 12729 */ + 204, + /* VPSIGNWYrm */ + }, + { /* 12730 */ + 205, + /* VPSIGNWYrr */ + }, + { /* 12731 */ + 235, + /* VPSIGNWrm */ + }, + { /* 12732 */ + 236, + /* VPSIGNWrr */ + }, + { /* 12733 */ + 902, + /* VPSLLDQYri */ + }, + { /* 12734 */ + 857, + /* VPSLLDQZ128rm */ + }, + { /* 12735 */ + 860, + /* VPSLLDQZ128rr */ + }, + { /* 12736 */ + 866, + /* VPSLLDQZ256rm */ + }, + { /* 12737 */ + 869, + /* VPSLLDQZ256rr */ + }, + { /* 12738 */ + 875, + /* VPSLLDQZrm */ + }, + { /* 12739 */ + 878, + /* VPSLLDQZrr */ + }, + { /* 12740 */ + 903, + /* VPSLLDQri */ + }, + { /* 12741 */ + 902, + /* VPSLLDYri */ + }, + { /* 12742 */ + 204, + /* VPSLLDYrm */ + }, + { /* 12743 */ + 904, + /* VPSLLDYrr */ + }, + { /* 12744 */ + 854, + /* VPSLLDZ128mbi */ + }, + { /* 12745 */ + 855, + /* VPSLLDZ128mbik */ + }, + { /* 12746 */ + 856, + /* VPSLLDZ128mbikz */ + }, + { /* 12747 */ + 857, + /* VPSLLDZ128mi */ + }, + { /* 12748 */ + 858, + /* VPSLLDZ128mik */ + }, + { /* 12749 */ + 859, + /* VPSLLDZ128mikz */ + }, + { /* 12750 */ + 860, + /* VPSLLDZ128ri */ + }, + { /* 12751 */ + 861, + /* VPSLLDZ128rik */ + }, + { /* 12752 */ + 862, + /* VPSLLDZ128rikz */ + }, + { /* 12753 */ + 206, + /* VPSLLDZ128rm */ + }, + { /* 12754 */ + 203, + /* VPSLLDZ128rmk */ + }, + { /* 12755 */ + 210, + /* VPSLLDZ128rmkz */ + }, + { /* 12756 */ + 211, + /* VPSLLDZ128rr */ + }, + { /* 12757 */ + 212, + /* VPSLLDZ128rrk */ + }, + { /* 12758 */ + 213, + /* VPSLLDZ128rrkz */ + }, + { /* 12759 */ + 863, + /* VPSLLDZ256mbi */ + }, + { /* 12760 */ + 864, + /* VPSLLDZ256mbik */ + }, + { /* 12761 */ + 865, + /* VPSLLDZ256mbikz */ + }, + { /* 12762 */ + 866, + /* VPSLLDZ256mi */ + }, + { /* 12763 */ + 867, + /* VPSLLDZ256mik */ + }, + { /* 12764 */ + 868, + /* VPSLLDZ256mikz */ + }, + { /* 12765 */ + 869, + /* VPSLLDZ256ri */ + }, + { /* 12766 */ + 870, + /* VPSLLDZ256rik */ + }, + { /* 12767 */ + 871, + /* VPSLLDZ256rikz */ + }, + { /* 12768 */ + 905, + /* VPSLLDZ256rm */ + }, + { /* 12769 */ + 906, + /* VPSLLDZ256rmk */ + }, + { /* 12770 */ + 907, + /* VPSLLDZ256rmkz */ + }, + { /* 12771 */ + 908, + /* VPSLLDZ256rr */ + }, + { /* 12772 */ + 909, + /* VPSLLDZ256rrk */ + }, + { /* 12773 */ + 910, + /* VPSLLDZ256rrkz */ + }, + { /* 12774 */ + 872, + /* VPSLLDZmbi */ + }, + { /* 12775 */ + 873, + /* VPSLLDZmbik */ + }, + { /* 12776 */ + 874, + /* VPSLLDZmbikz */ + }, + { /* 12777 */ + 875, + /* VPSLLDZmi */ + }, + { /* 12778 */ + 876, + /* VPSLLDZmik */ + }, + { /* 12779 */ + 877, + /* VPSLLDZmikz */ + }, + { /* 12780 */ + 878, + /* VPSLLDZri */ + }, + { /* 12781 */ + 879, + /* VPSLLDZrik */ + }, + { /* 12782 */ + 880, + /* VPSLLDZrikz */ + }, + { /* 12783 */ + 911, + /* VPSLLDZrm */ + }, + { /* 12784 */ + 201, + /* VPSLLDZrmk */ + }, + { /* 12785 */ + 912, + /* VPSLLDZrmkz */ + }, + { /* 12786 */ + 913, + /* VPSLLDZrr */ + }, + { /* 12787 */ + 914, + /* VPSLLDZrrk */ + }, + { /* 12788 */ + 915, + /* VPSLLDZrrkz */ + }, + { /* 12789 */ + 903, + /* VPSLLDri */ + }, + { /* 12790 */ + 235, + /* VPSLLDrm */ + }, + { /* 12791 */ + 236, + /* VPSLLDrr */ + }, + { /* 12792 */ + 902, + /* VPSLLQYri */ + }, + { /* 12793 */ + 204, + /* VPSLLQYrm */ + }, + { /* 12794 */ + 904, + /* VPSLLQYrr */ + }, + { /* 12795 */ + 881, + /* VPSLLQZ128mbi */ + }, + { /* 12796 */ + 882, + /* VPSLLQZ128mbik */ + }, + { /* 12797 */ + 883, + /* VPSLLQZ128mbikz */ + }, + { /* 12798 */ + 857, + /* VPSLLQZ128mi */ + }, + { /* 12799 */ + 858, + /* VPSLLQZ128mik */ + }, + { /* 12800 */ + 859, + /* VPSLLQZ128mikz */ + }, + { /* 12801 */ + 860, + /* VPSLLQZ128ri */ + }, + { /* 12802 */ + 861, + /* VPSLLQZ128rik */ + }, + { /* 12803 */ + 862, + /* VPSLLQZ128rikz */ + }, + { /* 12804 */ + 206, + /* VPSLLQZ128rm */ + }, + { /* 12805 */ + 203, + /* VPSLLQZ128rmk */ + }, + { /* 12806 */ + 210, + /* VPSLLQZ128rmkz */ + }, + { /* 12807 */ + 211, + /* VPSLLQZ128rr */ + }, + { /* 12808 */ + 212, + /* VPSLLQZ128rrk */ + }, + { /* 12809 */ + 213, + /* VPSLLQZ128rrkz */ + }, + { /* 12810 */ + 884, + /* VPSLLQZ256mbi */ + }, + { /* 12811 */ + 885, + /* VPSLLQZ256mbik */ + }, + { /* 12812 */ + 886, + /* VPSLLQZ256mbikz */ + }, + { /* 12813 */ + 866, + /* VPSLLQZ256mi */ + }, + { /* 12814 */ + 867, + /* VPSLLQZ256mik */ + }, + { /* 12815 */ + 868, + /* VPSLLQZ256mikz */ + }, + { /* 12816 */ + 869, + /* VPSLLQZ256ri */ + }, + { /* 12817 */ + 870, + /* VPSLLQZ256rik */ + }, + { /* 12818 */ + 871, + /* VPSLLQZ256rikz */ + }, + { /* 12819 */ + 905, + /* VPSLLQZ256rm */ + }, + { /* 12820 */ + 906, + /* VPSLLQZ256rmk */ + }, + { /* 12821 */ + 907, + /* VPSLLQZ256rmkz */ + }, + { /* 12822 */ + 908, + /* VPSLLQZ256rr */ + }, + { /* 12823 */ + 909, + /* VPSLLQZ256rrk */ + }, + { /* 12824 */ + 910, + /* VPSLLQZ256rrkz */ + }, + { /* 12825 */ + 887, + /* VPSLLQZmbi */ + }, + { /* 12826 */ + 888, + /* VPSLLQZmbik */ + }, + { /* 12827 */ + 889, + /* VPSLLQZmbikz */ + }, + { /* 12828 */ + 875, + /* VPSLLQZmi */ + }, + { /* 12829 */ + 876, + /* VPSLLQZmik */ + }, + { /* 12830 */ + 877, + /* VPSLLQZmikz */ + }, + { /* 12831 */ + 878, + /* VPSLLQZri */ + }, + { /* 12832 */ + 879, + /* VPSLLQZrik */ + }, + { /* 12833 */ + 880, + /* VPSLLQZrikz */ + }, + { /* 12834 */ + 911, + /* VPSLLQZrm */ + }, + { /* 12835 */ + 201, + /* VPSLLQZrmk */ + }, + { /* 12836 */ + 912, + /* VPSLLQZrmkz */ + }, + { /* 12837 */ + 913, + /* VPSLLQZrr */ + }, + { /* 12838 */ + 914, + /* VPSLLQZrrk */ + }, + { /* 12839 */ + 915, + /* VPSLLQZrrkz */ + }, + { /* 12840 */ + 903, + /* VPSLLQri */ + }, + { /* 12841 */ + 235, + /* VPSLLQrm */ + }, + { /* 12842 */ + 236, + /* VPSLLQrr */ + }, + { /* 12843 */ + 204, + /* VPSLLVDYrm */ + }, + { /* 12844 */ + 205, + /* VPSLLVDYrr */ + }, + { /* 12845 */ + 206, + /* VPSLLVDZ128rm */ + }, + { /* 12846 */ + 237, + /* VPSLLVDZ128rmb */ + }, + { /* 12847 */ + 238, + /* VPSLLVDZ128rmbk */ + }, + { /* 12848 */ + 239, + /* VPSLLVDZ128rmbkz */ + }, + { /* 12849 */ + 203, + /* VPSLLVDZ128rmk */ + }, + { /* 12850 */ + 210, + /* VPSLLVDZ128rmkz */ + }, + { /* 12851 */ + 211, + /* VPSLLVDZ128rr */ + }, + { /* 12852 */ + 212, + /* VPSLLVDZ128rrk */ + }, + { /* 12853 */ + 213, + /* VPSLLVDZ128rrkz */ + }, + { /* 12854 */ + 214, + /* VPSLLVDZ256rm */ + }, + { /* 12855 */ + 240, + /* VPSLLVDZ256rmb */ + }, + { /* 12856 */ + 241, + /* VPSLLVDZ256rmbk */ + }, + { /* 12857 */ + 242, + /* VPSLLVDZ256rmbkz */ + }, + { /* 12858 */ + 218, + /* VPSLLVDZ256rmk */ + }, + { /* 12859 */ + 219, + /* VPSLLVDZ256rmkz */ + }, + { /* 12860 */ + 220, + /* VPSLLVDZ256rr */ + }, + { /* 12861 */ + 221, + /* VPSLLVDZ256rrk */ + }, + { /* 12862 */ + 222, + /* VPSLLVDZ256rrkz */ + }, + { /* 12863 */ + 223, + /* VPSLLVDZrm */ + }, + { /* 12864 */ + 243, + /* VPSLLVDZrmb */ + }, + { /* 12865 */ + 244, + /* VPSLLVDZrmbk */ + }, + { /* 12866 */ + 245, + /* VPSLLVDZrmbkz */ + }, + { /* 12867 */ + 227, + /* VPSLLVDZrmk */ + }, + { /* 12868 */ + 228, + /* VPSLLVDZrmkz */ + }, + { /* 12869 */ + 229, + /* VPSLLVDZrr */ + }, + { /* 12870 */ + 233, + /* VPSLLVDZrrk */ + }, + { /* 12871 */ + 234, + /* VPSLLVDZrrkz */ + }, + { /* 12872 */ + 235, + /* VPSLLVDrm */ + }, + { /* 12873 */ + 236, + /* VPSLLVDrr */ + }, + { /* 12874 */ + 204, + /* VPSLLVQYrm */ + }, + { /* 12875 */ + 205, + /* VPSLLVQYrr */ + }, + { /* 12876 */ + 206, + /* VPSLLVQZ128rm */ + }, + { /* 12877 */ + 207, + /* VPSLLVQZ128rmb */ + }, + { /* 12878 */ + 208, + /* VPSLLVQZ128rmbk */ + }, + { /* 12879 */ + 209, + /* VPSLLVQZ128rmbkz */ + }, + { /* 12880 */ + 203, + /* VPSLLVQZ128rmk */ + }, + { /* 12881 */ + 210, + /* VPSLLVQZ128rmkz */ + }, + { /* 12882 */ + 211, + /* VPSLLVQZ128rr */ + }, + { /* 12883 */ + 212, + /* VPSLLVQZ128rrk */ + }, + { /* 12884 */ + 213, + /* VPSLLVQZ128rrkz */ + }, + { /* 12885 */ + 214, + /* VPSLLVQZ256rm */ + }, + { /* 12886 */ + 215, + /* VPSLLVQZ256rmb */ + }, + { /* 12887 */ + 216, + /* VPSLLVQZ256rmbk */ + }, + { /* 12888 */ + 217, + /* VPSLLVQZ256rmbkz */ + }, + { /* 12889 */ + 218, + /* VPSLLVQZ256rmk */ + }, + { /* 12890 */ + 219, + /* VPSLLVQZ256rmkz */ + }, + { /* 12891 */ + 220, + /* VPSLLVQZ256rr */ + }, + { /* 12892 */ + 221, + /* VPSLLVQZ256rrk */ + }, + { /* 12893 */ + 222, + /* VPSLLVQZ256rrkz */ + }, + { /* 12894 */ + 223, + /* VPSLLVQZrm */ + }, + { /* 12895 */ + 224, + /* VPSLLVQZrmb */ + }, + { /* 12896 */ + 225, + /* VPSLLVQZrmbk */ + }, + { /* 12897 */ + 226, + /* VPSLLVQZrmbkz */ + }, + { /* 12898 */ + 227, + /* VPSLLVQZrmk */ + }, + { /* 12899 */ + 228, + /* VPSLLVQZrmkz */ + }, + { /* 12900 */ + 229, + /* VPSLLVQZrr */ + }, + { /* 12901 */ + 233, + /* VPSLLVQZrrk */ + }, + { /* 12902 */ + 234, + /* VPSLLVQZrrkz */ + }, + { /* 12903 */ + 235, + /* VPSLLVQrm */ + }, + { /* 12904 */ + 236, + /* VPSLLVQrr */ + }, + { /* 12905 */ + 206, + /* VPSLLVWZ128rm */ + }, + { /* 12906 */ + 203, + /* VPSLLVWZ128rmk */ + }, + { /* 12907 */ + 210, + /* VPSLLVWZ128rmkz */ + }, + { /* 12908 */ + 211, + /* VPSLLVWZ128rr */ + }, + { /* 12909 */ + 212, + /* VPSLLVWZ128rrk */ + }, + { /* 12910 */ + 213, + /* VPSLLVWZ128rrkz */ + }, + { /* 12911 */ + 214, + /* VPSLLVWZ256rm */ + }, + { /* 12912 */ + 218, + /* VPSLLVWZ256rmk */ + }, + { /* 12913 */ + 219, + /* VPSLLVWZ256rmkz */ + }, + { /* 12914 */ + 220, + /* VPSLLVWZ256rr */ + }, + { /* 12915 */ + 221, + /* VPSLLVWZ256rrk */ + }, + { /* 12916 */ + 222, + /* VPSLLVWZ256rrkz */ + }, + { /* 12917 */ + 223, + /* VPSLLVWZrm */ + }, + { /* 12918 */ + 227, + /* VPSLLVWZrmk */ + }, + { /* 12919 */ + 228, + /* VPSLLVWZrmkz */ + }, + { /* 12920 */ + 229, + /* VPSLLVWZrr */ + }, + { /* 12921 */ + 233, + /* VPSLLVWZrrk */ + }, + { /* 12922 */ + 234, + /* VPSLLVWZrrkz */ + }, + { /* 12923 */ + 902, + /* VPSLLWYri */ + }, + { /* 12924 */ + 204, + /* VPSLLWYrm */ + }, + { /* 12925 */ + 904, + /* VPSLLWYrr */ + }, + { /* 12926 */ + 857, + /* VPSLLWZ128mi */ + }, + { /* 12927 */ + 858, + /* VPSLLWZ128mik */ + }, + { /* 12928 */ + 859, + /* VPSLLWZ128mikz */ + }, + { /* 12929 */ + 860, + /* VPSLLWZ128ri */ + }, + { /* 12930 */ + 861, + /* VPSLLWZ128rik */ + }, + { /* 12931 */ + 862, + /* VPSLLWZ128rikz */ + }, + { /* 12932 */ + 206, + /* VPSLLWZ128rm */ + }, + { /* 12933 */ + 203, + /* VPSLLWZ128rmk */ + }, + { /* 12934 */ + 210, + /* VPSLLWZ128rmkz */ + }, + { /* 12935 */ + 211, + /* VPSLLWZ128rr */ + }, + { /* 12936 */ + 212, + /* VPSLLWZ128rrk */ + }, + { /* 12937 */ + 213, + /* VPSLLWZ128rrkz */ + }, + { /* 12938 */ + 866, + /* VPSLLWZ256mi */ + }, + { /* 12939 */ + 867, + /* VPSLLWZ256mik */ + }, + { /* 12940 */ + 868, + /* VPSLLWZ256mikz */ + }, + { /* 12941 */ + 869, + /* VPSLLWZ256ri */ + }, + { /* 12942 */ + 870, + /* VPSLLWZ256rik */ + }, + { /* 12943 */ + 871, + /* VPSLLWZ256rikz */ + }, + { /* 12944 */ + 905, + /* VPSLLWZ256rm */ + }, + { /* 12945 */ + 906, + /* VPSLLWZ256rmk */ + }, + { /* 12946 */ + 907, + /* VPSLLWZ256rmkz */ + }, + { /* 12947 */ + 908, + /* VPSLLWZ256rr */ + }, + { /* 12948 */ + 909, + /* VPSLLWZ256rrk */ + }, + { /* 12949 */ + 910, + /* VPSLLWZ256rrkz */ + }, + { /* 12950 */ + 875, + /* VPSLLWZmi */ + }, + { /* 12951 */ + 876, + /* VPSLLWZmik */ + }, + { /* 12952 */ + 877, + /* VPSLLWZmikz */ + }, + { /* 12953 */ + 878, + /* VPSLLWZri */ + }, + { /* 12954 */ + 879, + /* VPSLLWZrik */ + }, + { /* 12955 */ + 880, + /* VPSLLWZrikz */ + }, + { /* 12956 */ + 911, + /* VPSLLWZrm */ + }, + { /* 12957 */ + 201, + /* VPSLLWZrmk */ + }, + { /* 12958 */ + 912, + /* VPSLLWZrmkz */ + }, + { /* 12959 */ + 913, + /* VPSLLWZrr */ + }, + { /* 12960 */ + 914, + /* VPSLLWZrrk */ + }, + { /* 12961 */ + 915, + /* VPSLLWZrrkz */ + }, + { /* 12962 */ + 903, + /* VPSLLWri */ + }, + { /* 12963 */ + 235, + /* VPSLLWrm */ + }, + { /* 12964 */ + 236, + /* VPSLLWrr */ + }, + { /* 12965 */ + 902, + /* VPSRADYri */ + }, + { /* 12966 */ + 204, + /* VPSRADYrm */ + }, + { /* 12967 */ + 904, + /* VPSRADYrr */ + }, + { /* 12968 */ + 854, + /* VPSRADZ128mbi */ + }, + { /* 12969 */ + 855, + /* VPSRADZ128mbik */ + }, + { /* 12970 */ + 856, + /* VPSRADZ128mbikz */ + }, + { /* 12971 */ + 857, + /* VPSRADZ128mi */ + }, + { /* 12972 */ + 858, + /* VPSRADZ128mik */ + }, + { /* 12973 */ + 859, + /* VPSRADZ128mikz */ + }, + { /* 12974 */ + 860, + /* VPSRADZ128ri */ + }, + { /* 12975 */ + 861, + /* VPSRADZ128rik */ + }, + { /* 12976 */ + 862, + /* VPSRADZ128rikz */ + }, + { /* 12977 */ + 206, + /* VPSRADZ128rm */ + }, + { /* 12978 */ + 203, + /* VPSRADZ128rmk */ + }, + { /* 12979 */ + 210, + /* VPSRADZ128rmkz */ + }, + { /* 12980 */ + 211, + /* VPSRADZ128rr */ + }, + { /* 12981 */ + 212, + /* VPSRADZ128rrk */ + }, + { /* 12982 */ + 213, + /* VPSRADZ128rrkz */ + }, + { /* 12983 */ + 863, + /* VPSRADZ256mbi */ + }, + { /* 12984 */ + 864, + /* VPSRADZ256mbik */ + }, + { /* 12985 */ + 865, + /* VPSRADZ256mbikz */ + }, + { /* 12986 */ + 866, + /* VPSRADZ256mi */ + }, + { /* 12987 */ + 867, + /* VPSRADZ256mik */ + }, + { /* 12988 */ + 868, + /* VPSRADZ256mikz */ + }, + { /* 12989 */ + 869, + /* VPSRADZ256ri */ + }, + { /* 12990 */ + 870, + /* VPSRADZ256rik */ + }, + { /* 12991 */ + 871, + /* VPSRADZ256rikz */ + }, + { /* 12992 */ + 905, + /* VPSRADZ256rm */ + }, + { /* 12993 */ + 906, + /* VPSRADZ256rmk */ + }, + { /* 12994 */ + 907, + /* VPSRADZ256rmkz */ + }, + { /* 12995 */ + 908, + /* VPSRADZ256rr */ + }, + { /* 12996 */ + 909, + /* VPSRADZ256rrk */ + }, + { /* 12997 */ + 910, + /* VPSRADZ256rrkz */ + }, + { /* 12998 */ + 872, + /* VPSRADZmbi */ + }, + { /* 12999 */ + 873, + /* VPSRADZmbik */ + }, + { /* 13000 */ + 874, + /* VPSRADZmbikz */ + }, + { /* 13001 */ + 875, + /* VPSRADZmi */ + }, + { /* 13002 */ + 876, + /* VPSRADZmik */ + }, + { /* 13003 */ + 877, + /* VPSRADZmikz */ + }, + { /* 13004 */ + 878, + /* VPSRADZri */ + }, + { /* 13005 */ + 879, + /* VPSRADZrik */ + }, + { /* 13006 */ + 880, + /* VPSRADZrikz */ + }, + { /* 13007 */ + 911, + /* VPSRADZrm */ + }, + { /* 13008 */ + 201, + /* VPSRADZrmk */ + }, + { /* 13009 */ + 912, + /* VPSRADZrmkz */ + }, + { /* 13010 */ + 913, + /* VPSRADZrr */ + }, + { /* 13011 */ + 914, + /* VPSRADZrrk */ + }, + { /* 13012 */ + 915, + /* VPSRADZrrkz */ + }, + { /* 13013 */ + 903, + /* VPSRADri */ + }, + { /* 13014 */ + 235, + /* VPSRADrm */ + }, + { /* 13015 */ + 236, + /* VPSRADrr */ + }, + { /* 13016 */ + 881, + /* VPSRAQZ128mbi */ + }, + { /* 13017 */ + 882, + /* VPSRAQZ128mbik */ + }, + { /* 13018 */ + 883, + /* VPSRAQZ128mbikz */ + }, + { /* 13019 */ + 857, + /* VPSRAQZ128mi */ + }, + { /* 13020 */ + 858, + /* VPSRAQZ128mik */ + }, + { /* 13021 */ + 859, + /* VPSRAQZ128mikz */ + }, + { /* 13022 */ + 860, + /* VPSRAQZ128ri */ + }, + { /* 13023 */ + 861, + /* VPSRAQZ128rik */ + }, + { /* 13024 */ + 862, + /* VPSRAQZ128rikz */ + }, + { /* 13025 */ + 206, + /* VPSRAQZ128rm */ + }, + { /* 13026 */ + 203, + /* VPSRAQZ128rmk */ + }, + { /* 13027 */ + 210, + /* VPSRAQZ128rmkz */ + }, + { /* 13028 */ + 211, + /* VPSRAQZ128rr */ + }, + { /* 13029 */ + 212, + /* VPSRAQZ128rrk */ + }, + { /* 13030 */ + 213, + /* VPSRAQZ128rrkz */ + }, + { /* 13031 */ + 884, + /* VPSRAQZ256mbi */ + }, + { /* 13032 */ + 885, + /* VPSRAQZ256mbik */ + }, + { /* 13033 */ + 886, + /* VPSRAQZ256mbikz */ + }, + { /* 13034 */ + 866, + /* VPSRAQZ256mi */ + }, + { /* 13035 */ + 867, + /* VPSRAQZ256mik */ + }, + { /* 13036 */ + 868, + /* VPSRAQZ256mikz */ + }, + { /* 13037 */ + 869, + /* VPSRAQZ256ri */ + }, + { /* 13038 */ + 870, + /* VPSRAQZ256rik */ + }, + { /* 13039 */ + 871, + /* VPSRAQZ256rikz */ + }, + { /* 13040 */ + 905, + /* VPSRAQZ256rm */ + }, + { /* 13041 */ + 906, + /* VPSRAQZ256rmk */ + }, + { /* 13042 */ + 907, + /* VPSRAQZ256rmkz */ + }, + { /* 13043 */ + 908, + /* VPSRAQZ256rr */ + }, + { /* 13044 */ + 909, + /* VPSRAQZ256rrk */ + }, + { /* 13045 */ + 910, + /* VPSRAQZ256rrkz */ + }, + { /* 13046 */ + 887, + /* VPSRAQZmbi */ + }, + { /* 13047 */ + 888, + /* VPSRAQZmbik */ + }, + { /* 13048 */ + 889, + /* VPSRAQZmbikz */ + }, + { /* 13049 */ + 875, + /* VPSRAQZmi */ + }, + { /* 13050 */ + 876, + /* VPSRAQZmik */ + }, + { /* 13051 */ + 877, + /* VPSRAQZmikz */ + }, + { /* 13052 */ + 878, + /* VPSRAQZri */ + }, + { /* 13053 */ + 879, + /* VPSRAQZrik */ + }, + { /* 13054 */ + 880, + /* VPSRAQZrikz */ + }, + { /* 13055 */ + 911, + /* VPSRAQZrm */ + }, + { /* 13056 */ + 201, + /* VPSRAQZrmk */ + }, + { /* 13057 */ + 912, + /* VPSRAQZrmkz */ + }, + { /* 13058 */ + 913, + /* VPSRAQZrr */ + }, + { /* 13059 */ + 914, + /* VPSRAQZrrk */ + }, + { /* 13060 */ + 915, + /* VPSRAQZrrkz */ + }, + { /* 13061 */ + 204, + /* VPSRAVDYrm */ + }, + { /* 13062 */ + 205, + /* VPSRAVDYrr */ + }, + { /* 13063 */ + 206, + /* VPSRAVDZ128rm */ + }, + { /* 13064 */ + 237, + /* VPSRAVDZ128rmb */ + }, + { /* 13065 */ + 238, + /* VPSRAVDZ128rmbk */ + }, + { /* 13066 */ + 239, + /* VPSRAVDZ128rmbkz */ + }, + { /* 13067 */ + 203, + /* VPSRAVDZ128rmk */ + }, + { /* 13068 */ + 210, + /* VPSRAVDZ128rmkz */ + }, + { /* 13069 */ + 211, + /* VPSRAVDZ128rr */ + }, + { /* 13070 */ + 212, + /* VPSRAVDZ128rrk */ + }, + { /* 13071 */ + 213, + /* VPSRAVDZ128rrkz */ + }, + { /* 13072 */ + 214, + /* VPSRAVDZ256rm */ + }, + { /* 13073 */ + 240, + /* VPSRAVDZ256rmb */ + }, + { /* 13074 */ + 241, + /* VPSRAVDZ256rmbk */ + }, + { /* 13075 */ + 242, + /* VPSRAVDZ256rmbkz */ + }, + { /* 13076 */ + 218, + /* VPSRAVDZ256rmk */ + }, + { /* 13077 */ + 219, + /* VPSRAVDZ256rmkz */ + }, + { /* 13078 */ + 220, + /* VPSRAVDZ256rr */ + }, + { /* 13079 */ + 221, + /* VPSRAVDZ256rrk */ + }, + { /* 13080 */ + 222, + /* VPSRAVDZ256rrkz */ + }, + { /* 13081 */ + 223, + /* VPSRAVDZrm */ + }, + { /* 13082 */ + 243, + /* VPSRAVDZrmb */ + }, + { /* 13083 */ + 244, + /* VPSRAVDZrmbk */ + }, + { /* 13084 */ + 245, + /* VPSRAVDZrmbkz */ + }, + { /* 13085 */ + 227, + /* VPSRAVDZrmk */ + }, + { /* 13086 */ + 228, + /* VPSRAVDZrmkz */ + }, + { /* 13087 */ + 229, + /* VPSRAVDZrr */ + }, + { /* 13088 */ + 233, + /* VPSRAVDZrrk */ + }, + { /* 13089 */ + 234, + /* VPSRAVDZrrkz */ + }, + { /* 13090 */ + 235, + /* VPSRAVDrm */ + }, + { /* 13091 */ + 236, + /* VPSRAVDrr */ + }, + { /* 13092 */ + 206, + /* VPSRAVQZ128rm */ + }, + { /* 13093 */ + 207, + /* VPSRAVQZ128rmb */ + }, + { /* 13094 */ + 208, + /* VPSRAVQZ128rmbk */ + }, + { /* 13095 */ + 209, + /* VPSRAVQZ128rmbkz */ + }, + { /* 13096 */ + 203, + /* VPSRAVQZ128rmk */ + }, + { /* 13097 */ + 210, + /* VPSRAVQZ128rmkz */ + }, + { /* 13098 */ + 211, + /* VPSRAVQZ128rr */ + }, + { /* 13099 */ + 212, + /* VPSRAVQZ128rrk */ + }, + { /* 13100 */ + 213, + /* VPSRAVQZ128rrkz */ + }, + { /* 13101 */ + 214, + /* VPSRAVQZ256rm */ + }, + { /* 13102 */ + 215, + /* VPSRAVQZ256rmb */ + }, + { /* 13103 */ + 216, + /* VPSRAVQZ256rmbk */ + }, + { /* 13104 */ + 217, + /* VPSRAVQZ256rmbkz */ + }, + { /* 13105 */ + 218, + /* VPSRAVQZ256rmk */ + }, + { /* 13106 */ + 219, + /* VPSRAVQZ256rmkz */ + }, + { /* 13107 */ + 220, + /* VPSRAVQZ256rr */ + }, + { /* 13108 */ + 221, + /* VPSRAVQZ256rrk */ + }, + { /* 13109 */ + 222, + /* VPSRAVQZ256rrkz */ + }, + { /* 13110 */ + 223, + /* VPSRAVQZrm */ + }, + { /* 13111 */ + 224, + /* VPSRAVQZrmb */ + }, + { /* 13112 */ + 225, + /* VPSRAVQZrmbk */ + }, + { /* 13113 */ + 226, + /* VPSRAVQZrmbkz */ + }, + { /* 13114 */ + 227, + /* VPSRAVQZrmk */ + }, + { /* 13115 */ + 228, + /* VPSRAVQZrmkz */ + }, + { /* 13116 */ + 229, + /* VPSRAVQZrr */ + }, + { /* 13117 */ + 233, + /* VPSRAVQZrrk */ + }, + { /* 13118 */ + 234, + /* VPSRAVQZrrkz */ + }, + { /* 13119 */ + 206, + /* VPSRAVWZ128rm */ + }, + { /* 13120 */ + 203, + /* VPSRAVWZ128rmk */ + }, + { /* 13121 */ + 210, + /* VPSRAVWZ128rmkz */ + }, + { /* 13122 */ + 211, + /* VPSRAVWZ128rr */ + }, + { /* 13123 */ + 212, + /* VPSRAVWZ128rrk */ + }, + { /* 13124 */ + 213, + /* VPSRAVWZ128rrkz */ + }, + { /* 13125 */ + 214, + /* VPSRAVWZ256rm */ + }, + { /* 13126 */ + 218, + /* VPSRAVWZ256rmk */ + }, + { /* 13127 */ + 219, + /* VPSRAVWZ256rmkz */ + }, + { /* 13128 */ + 220, + /* VPSRAVWZ256rr */ + }, + { /* 13129 */ + 221, + /* VPSRAVWZ256rrk */ + }, + { /* 13130 */ + 222, + /* VPSRAVWZ256rrkz */ + }, + { /* 13131 */ + 223, + /* VPSRAVWZrm */ + }, + { /* 13132 */ + 227, + /* VPSRAVWZrmk */ + }, + { /* 13133 */ + 228, + /* VPSRAVWZrmkz */ + }, + { /* 13134 */ + 229, + /* VPSRAVWZrr */ + }, + { /* 13135 */ + 233, + /* VPSRAVWZrrk */ + }, + { /* 13136 */ + 234, + /* VPSRAVWZrrkz */ + }, + { /* 13137 */ + 902, + /* VPSRAWYri */ + }, + { /* 13138 */ + 204, + /* VPSRAWYrm */ + }, + { /* 13139 */ + 904, + /* VPSRAWYrr */ + }, + { /* 13140 */ + 857, + /* VPSRAWZ128mi */ + }, + { /* 13141 */ + 858, + /* VPSRAWZ128mik */ + }, + { /* 13142 */ + 859, + /* VPSRAWZ128mikz */ + }, + { /* 13143 */ + 860, + /* VPSRAWZ128ri */ + }, + { /* 13144 */ + 861, + /* VPSRAWZ128rik */ + }, + { /* 13145 */ + 862, + /* VPSRAWZ128rikz */ + }, + { /* 13146 */ + 206, + /* VPSRAWZ128rm */ + }, + { /* 13147 */ + 203, + /* VPSRAWZ128rmk */ + }, + { /* 13148 */ + 210, + /* VPSRAWZ128rmkz */ + }, + { /* 13149 */ + 211, + /* VPSRAWZ128rr */ + }, + { /* 13150 */ + 212, + /* VPSRAWZ128rrk */ + }, + { /* 13151 */ + 213, + /* VPSRAWZ128rrkz */ + }, + { /* 13152 */ + 866, + /* VPSRAWZ256mi */ + }, + { /* 13153 */ + 867, + /* VPSRAWZ256mik */ + }, + { /* 13154 */ + 868, + /* VPSRAWZ256mikz */ + }, + { /* 13155 */ + 869, + /* VPSRAWZ256ri */ + }, + { /* 13156 */ + 870, + /* VPSRAWZ256rik */ + }, + { /* 13157 */ + 871, + /* VPSRAWZ256rikz */ + }, + { /* 13158 */ + 905, + /* VPSRAWZ256rm */ + }, + { /* 13159 */ + 906, + /* VPSRAWZ256rmk */ + }, + { /* 13160 */ + 907, + /* VPSRAWZ256rmkz */ + }, + { /* 13161 */ + 908, + /* VPSRAWZ256rr */ + }, + { /* 13162 */ + 909, + /* VPSRAWZ256rrk */ + }, + { /* 13163 */ + 910, + /* VPSRAWZ256rrkz */ + }, + { /* 13164 */ + 875, + /* VPSRAWZmi */ + }, + { /* 13165 */ + 876, + /* VPSRAWZmik */ + }, + { /* 13166 */ + 877, + /* VPSRAWZmikz */ + }, + { /* 13167 */ + 878, + /* VPSRAWZri */ + }, + { /* 13168 */ + 879, + /* VPSRAWZrik */ + }, + { /* 13169 */ + 880, + /* VPSRAWZrikz */ + }, + { /* 13170 */ + 911, + /* VPSRAWZrm */ + }, + { /* 13171 */ + 201, + /* VPSRAWZrmk */ + }, + { /* 13172 */ + 912, + /* VPSRAWZrmkz */ + }, + { /* 13173 */ + 913, + /* VPSRAWZrr */ + }, + { /* 13174 */ + 914, + /* VPSRAWZrrk */ + }, + { /* 13175 */ + 915, + /* VPSRAWZrrkz */ + }, + { /* 13176 */ + 903, + /* VPSRAWri */ + }, + { /* 13177 */ + 235, + /* VPSRAWrm */ + }, + { /* 13178 */ + 236, + /* VPSRAWrr */ + }, + { /* 13179 */ + 902, + /* VPSRLDQYri */ + }, + { /* 13180 */ + 857, + /* VPSRLDQZ128rm */ + }, + { /* 13181 */ + 860, + /* VPSRLDQZ128rr */ + }, + { /* 13182 */ + 866, + /* VPSRLDQZ256rm */ + }, + { /* 13183 */ + 869, + /* VPSRLDQZ256rr */ + }, + { /* 13184 */ + 875, + /* VPSRLDQZrm */ + }, + { /* 13185 */ + 878, + /* VPSRLDQZrr */ + }, + { /* 13186 */ + 903, + /* VPSRLDQri */ + }, + { /* 13187 */ + 902, + /* VPSRLDYri */ + }, + { /* 13188 */ + 204, + /* VPSRLDYrm */ + }, + { /* 13189 */ + 904, + /* VPSRLDYrr */ + }, + { /* 13190 */ + 854, + /* VPSRLDZ128mbi */ + }, + { /* 13191 */ + 855, + /* VPSRLDZ128mbik */ + }, + { /* 13192 */ + 856, + /* VPSRLDZ128mbikz */ + }, + { /* 13193 */ + 857, + /* VPSRLDZ128mi */ + }, + { /* 13194 */ + 858, + /* VPSRLDZ128mik */ + }, + { /* 13195 */ + 859, + /* VPSRLDZ128mikz */ + }, + { /* 13196 */ + 860, + /* VPSRLDZ128ri */ + }, + { /* 13197 */ + 861, + /* VPSRLDZ128rik */ + }, + { /* 13198 */ + 862, + /* VPSRLDZ128rikz */ + }, + { /* 13199 */ + 206, + /* VPSRLDZ128rm */ + }, + { /* 13200 */ + 203, + /* VPSRLDZ128rmk */ + }, + { /* 13201 */ + 210, + /* VPSRLDZ128rmkz */ + }, + { /* 13202 */ + 211, + /* VPSRLDZ128rr */ + }, + { /* 13203 */ + 212, + /* VPSRLDZ128rrk */ + }, + { /* 13204 */ + 213, + /* VPSRLDZ128rrkz */ + }, + { /* 13205 */ + 863, + /* VPSRLDZ256mbi */ + }, + { /* 13206 */ + 864, + /* VPSRLDZ256mbik */ + }, + { /* 13207 */ + 865, + /* VPSRLDZ256mbikz */ + }, + { /* 13208 */ + 866, + /* VPSRLDZ256mi */ + }, + { /* 13209 */ + 867, + /* VPSRLDZ256mik */ + }, + { /* 13210 */ + 868, + /* VPSRLDZ256mikz */ + }, + { /* 13211 */ + 869, + /* VPSRLDZ256ri */ + }, + { /* 13212 */ + 870, + /* VPSRLDZ256rik */ + }, + { /* 13213 */ + 871, + /* VPSRLDZ256rikz */ + }, + { /* 13214 */ + 905, + /* VPSRLDZ256rm */ + }, + { /* 13215 */ + 906, + /* VPSRLDZ256rmk */ + }, + { /* 13216 */ + 907, + /* VPSRLDZ256rmkz */ + }, + { /* 13217 */ + 908, + /* VPSRLDZ256rr */ + }, + { /* 13218 */ + 909, + /* VPSRLDZ256rrk */ + }, + { /* 13219 */ + 910, + /* VPSRLDZ256rrkz */ + }, + { /* 13220 */ + 872, + /* VPSRLDZmbi */ + }, + { /* 13221 */ + 873, + /* VPSRLDZmbik */ + }, + { /* 13222 */ + 874, + /* VPSRLDZmbikz */ + }, + { /* 13223 */ + 875, + /* VPSRLDZmi */ + }, + { /* 13224 */ + 876, + /* VPSRLDZmik */ + }, + { /* 13225 */ + 877, + /* VPSRLDZmikz */ + }, + { /* 13226 */ + 878, + /* VPSRLDZri */ + }, + { /* 13227 */ + 879, + /* VPSRLDZrik */ + }, + { /* 13228 */ + 880, + /* VPSRLDZrikz */ + }, + { /* 13229 */ + 911, + /* VPSRLDZrm */ + }, + { /* 13230 */ + 201, + /* VPSRLDZrmk */ + }, + { /* 13231 */ + 912, + /* VPSRLDZrmkz */ + }, + { /* 13232 */ + 913, + /* VPSRLDZrr */ + }, + { /* 13233 */ + 914, + /* VPSRLDZrrk */ + }, + { /* 13234 */ + 915, + /* VPSRLDZrrkz */ + }, + { /* 13235 */ + 903, + /* VPSRLDri */ + }, + { /* 13236 */ + 235, + /* VPSRLDrm */ + }, + { /* 13237 */ + 236, + /* VPSRLDrr */ + }, + { /* 13238 */ + 902, + /* VPSRLQYri */ + }, + { /* 13239 */ + 204, + /* VPSRLQYrm */ + }, + { /* 13240 */ + 904, + /* VPSRLQYrr */ + }, + { /* 13241 */ + 881, + /* VPSRLQZ128mbi */ + }, + { /* 13242 */ + 882, + /* VPSRLQZ128mbik */ + }, + { /* 13243 */ + 883, + /* VPSRLQZ128mbikz */ + }, + { /* 13244 */ + 857, + /* VPSRLQZ128mi */ + }, + { /* 13245 */ + 858, + /* VPSRLQZ128mik */ + }, + { /* 13246 */ + 859, + /* VPSRLQZ128mikz */ + }, + { /* 13247 */ + 860, + /* VPSRLQZ128ri */ + }, + { /* 13248 */ + 861, + /* VPSRLQZ128rik */ + }, + { /* 13249 */ + 862, + /* VPSRLQZ128rikz */ + }, + { /* 13250 */ + 206, + /* VPSRLQZ128rm */ + }, + { /* 13251 */ + 203, + /* VPSRLQZ128rmk */ + }, + { /* 13252 */ + 210, + /* VPSRLQZ128rmkz */ + }, + { /* 13253 */ + 211, + /* VPSRLQZ128rr */ + }, + { /* 13254 */ + 212, + /* VPSRLQZ128rrk */ + }, + { /* 13255 */ + 213, + /* VPSRLQZ128rrkz */ + }, + { /* 13256 */ + 884, + /* VPSRLQZ256mbi */ + }, + { /* 13257 */ + 885, + /* VPSRLQZ256mbik */ + }, + { /* 13258 */ + 886, + /* VPSRLQZ256mbikz */ + }, + { /* 13259 */ + 866, + /* VPSRLQZ256mi */ + }, + { /* 13260 */ + 867, + /* VPSRLQZ256mik */ + }, + { /* 13261 */ + 868, + /* VPSRLQZ256mikz */ + }, + { /* 13262 */ + 869, + /* VPSRLQZ256ri */ + }, + { /* 13263 */ + 870, + /* VPSRLQZ256rik */ + }, + { /* 13264 */ + 871, + /* VPSRLQZ256rikz */ + }, + { /* 13265 */ + 905, + /* VPSRLQZ256rm */ + }, + { /* 13266 */ + 906, + /* VPSRLQZ256rmk */ + }, + { /* 13267 */ + 907, + /* VPSRLQZ256rmkz */ + }, + { /* 13268 */ + 908, + /* VPSRLQZ256rr */ + }, + { /* 13269 */ + 909, + /* VPSRLQZ256rrk */ + }, + { /* 13270 */ + 910, + /* VPSRLQZ256rrkz */ + }, + { /* 13271 */ + 887, + /* VPSRLQZmbi */ + }, + { /* 13272 */ + 888, + /* VPSRLQZmbik */ + }, + { /* 13273 */ + 889, + /* VPSRLQZmbikz */ + }, + { /* 13274 */ + 875, + /* VPSRLQZmi */ + }, + { /* 13275 */ + 876, + /* VPSRLQZmik */ + }, + { /* 13276 */ + 877, + /* VPSRLQZmikz */ + }, + { /* 13277 */ + 878, + /* VPSRLQZri */ + }, + { /* 13278 */ + 879, + /* VPSRLQZrik */ + }, + { /* 13279 */ + 880, + /* VPSRLQZrikz */ + }, + { /* 13280 */ + 911, + /* VPSRLQZrm */ + }, + { /* 13281 */ + 201, + /* VPSRLQZrmk */ + }, + { /* 13282 */ + 912, + /* VPSRLQZrmkz */ + }, + { /* 13283 */ + 913, + /* VPSRLQZrr */ + }, + { /* 13284 */ + 914, + /* VPSRLQZrrk */ + }, + { /* 13285 */ + 915, + /* VPSRLQZrrkz */ + }, + { /* 13286 */ + 903, + /* VPSRLQri */ + }, + { /* 13287 */ + 235, + /* VPSRLQrm */ + }, + { /* 13288 */ + 236, + /* VPSRLQrr */ + }, + { /* 13289 */ + 204, + /* VPSRLVDYrm */ + }, + { /* 13290 */ + 205, + /* VPSRLVDYrr */ + }, + { /* 13291 */ + 206, + /* VPSRLVDZ128rm */ + }, + { /* 13292 */ + 237, + /* VPSRLVDZ128rmb */ + }, + { /* 13293 */ + 238, + /* VPSRLVDZ128rmbk */ + }, + { /* 13294 */ + 239, + /* VPSRLVDZ128rmbkz */ + }, + { /* 13295 */ + 203, + /* VPSRLVDZ128rmk */ + }, + { /* 13296 */ + 210, + /* VPSRLVDZ128rmkz */ + }, + { /* 13297 */ + 211, + /* VPSRLVDZ128rr */ + }, + { /* 13298 */ + 212, + /* VPSRLVDZ128rrk */ + }, + { /* 13299 */ + 213, + /* VPSRLVDZ128rrkz */ + }, + { /* 13300 */ + 214, + /* VPSRLVDZ256rm */ + }, + { /* 13301 */ + 240, + /* VPSRLVDZ256rmb */ + }, + { /* 13302 */ + 241, + /* VPSRLVDZ256rmbk */ + }, + { /* 13303 */ + 242, + /* VPSRLVDZ256rmbkz */ + }, + { /* 13304 */ + 218, + /* VPSRLVDZ256rmk */ + }, + { /* 13305 */ + 219, + /* VPSRLVDZ256rmkz */ + }, + { /* 13306 */ + 220, + /* VPSRLVDZ256rr */ + }, + { /* 13307 */ + 221, + /* VPSRLVDZ256rrk */ + }, + { /* 13308 */ + 222, + /* VPSRLVDZ256rrkz */ + }, + { /* 13309 */ + 223, + /* VPSRLVDZrm */ + }, + { /* 13310 */ + 243, + /* VPSRLVDZrmb */ + }, + { /* 13311 */ + 244, + /* VPSRLVDZrmbk */ + }, + { /* 13312 */ + 245, + /* VPSRLVDZrmbkz */ + }, + { /* 13313 */ + 227, + /* VPSRLVDZrmk */ + }, + { /* 13314 */ + 228, + /* VPSRLVDZrmkz */ + }, + { /* 13315 */ + 229, + /* VPSRLVDZrr */ + }, + { /* 13316 */ + 233, + /* VPSRLVDZrrk */ + }, + { /* 13317 */ + 234, + /* VPSRLVDZrrkz */ + }, + { /* 13318 */ + 235, + /* VPSRLVDrm */ + }, + { /* 13319 */ + 236, + /* VPSRLVDrr */ + }, + { /* 13320 */ + 204, + /* VPSRLVQYrm */ + }, + { /* 13321 */ + 205, + /* VPSRLVQYrr */ + }, + { /* 13322 */ + 206, + /* VPSRLVQZ128rm */ + }, + { /* 13323 */ + 207, + /* VPSRLVQZ128rmb */ + }, + { /* 13324 */ + 208, + /* VPSRLVQZ128rmbk */ + }, + { /* 13325 */ + 209, + /* VPSRLVQZ128rmbkz */ + }, + { /* 13326 */ + 203, + /* VPSRLVQZ128rmk */ + }, + { /* 13327 */ + 210, + /* VPSRLVQZ128rmkz */ + }, + { /* 13328 */ + 211, + /* VPSRLVQZ128rr */ + }, + { /* 13329 */ + 212, + /* VPSRLVQZ128rrk */ + }, + { /* 13330 */ + 213, + /* VPSRLVQZ128rrkz */ + }, + { /* 13331 */ + 214, + /* VPSRLVQZ256rm */ + }, + { /* 13332 */ + 215, + /* VPSRLVQZ256rmb */ + }, + { /* 13333 */ + 216, + /* VPSRLVQZ256rmbk */ + }, + { /* 13334 */ + 217, + /* VPSRLVQZ256rmbkz */ + }, + { /* 13335 */ + 218, + /* VPSRLVQZ256rmk */ + }, + { /* 13336 */ + 219, + /* VPSRLVQZ256rmkz */ + }, + { /* 13337 */ + 220, + /* VPSRLVQZ256rr */ + }, + { /* 13338 */ + 221, + /* VPSRLVQZ256rrk */ + }, + { /* 13339 */ + 222, + /* VPSRLVQZ256rrkz */ + }, + { /* 13340 */ + 223, + /* VPSRLVQZrm */ + }, + { /* 13341 */ + 224, + /* VPSRLVQZrmb */ + }, + { /* 13342 */ + 225, + /* VPSRLVQZrmbk */ + }, + { /* 13343 */ + 226, + /* VPSRLVQZrmbkz */ + }, + { /* 13344 */ + 227, + /* VPSRLVQZrmk */ + }, + { /* 13345 */ + 228, + /* VPSRLVQZrmkz */ + }, + { /* 13346 */ + 229, + /* VPSRLVQZrr */ + }, + { /* 13347 */ + 233, + /* VPSRLVQZrrk */ + }, + { /* 13348 */ + 234, + /* VPSRLVQZrrkz */ + }, + { /* 13349 */ + 235, + /* VPSRLVQrm */ + }, + { /* 13350 */ + 236, + /* VPSRLVQrr */ + }, + { /* 13351 */ + 206, + /* VPSRLVWZ128rm */ + }, + { /* 13352 */ + 203, + /* VPSRLVWZ128rmk */ + }, + { /* 13353 */ + 210, + /* VPSRLVWZ128rmkz */ + }, + { /* 13354 */ + 211, + /* VPSRLVWZ128rr */ + }, + { /* 13355 */ + 212, + /* VPSRLVWZ128rrk */ + }, + { /* 13356 */ + 213, + /* VPSRLVWZ128rrkz */ + }, + { /* 13357 */ + 214, + /* VPSRLVWZ256rm */ + }, + { /* 13358 */ + 218, + /* VPSRLVWZ256rmk */ + }, + { /* 13359 */ + 219, + /* VPSRLVWZ256rmkz */ + }, + { /* 13360 */ + 220, + /* VPSRLVWZ256rr */ + }, + { /* 13361 */ + 221, + /* VPSRLVWZ256rrk */ + }, + { /* 13362 */ + 222, + /* VPSRLVWZ256rrkz */ + }, + { /* 13363 */ + 223, + /* VPSRLVWZrm */ + }, + { /* 13364 */ + 227, + /* VPSRLVWZrmk */ + }, + { /* 13365 */ + 228, + /* VPSRLVWZrmkz */ + }, + { /* 13366 */ + 229, + /* VPSRLVWZrr */ + }, + { /* 13367 */ + 233, + /* VPSRLVWZrrk */ + }, + { /* 13368 */ + 234, + /* VPSRLVWZrrkz */ + }, + { /* 13369 */ + 902, + /* VPSRLWYri */ + }, + { /* 13370 */ + 204, + /* VPSRLWYrm */ + }, + { /* 13371 */ + 904, + /* VPSRLWYrr */ + }, + { /* 13372 */ + 857, + /* VPSRLWZ128mi */ + }, + { /* 13373 */ + 858, + /* VPSRLWZ128mik */ + }, + { /* 13374 */ + 859, + /* VPSRLWZ128mikz */ + }, + { /* 13375 */ + 860, + /* VPSRLWZ128ri */ + }, + { /* 13376 */ + 861, + /* VPSRLWZ128rik */ + }, + { /* 13377 */ + 862, + /* VPSRLWZ128rikz */ + }, + { /* 13378 */ + 206, + /* VPSRLWZ128rm */ + }, + { /* 13379 */ + 203, + /* VPSRLWZ128rmk */ + }, + { /* 13380 */ + 210, + /* VPSRLWZ128rmkz */ + }, + { /* 13381 */ + 211, + /* VPSRLWZ128rr */ + }, + { /* 13382 */ + 212, + /* VPSRLWZ128rrk */ + }, + { /* 13383 */ + 213, + /* VPSRLWZ128rrkz */ + }, + { /* 13384 */ + 866, + /* VPSRLWZ256mi */ + }, + { /* 13385 */ + 867, + /* VPSRLWZ256mik */ + }, + { /* 13386 */ + 868, + /* VPSRLWZ256mikz */ + }, + { /* 13387 */ + 869, + /* VPSRLWZ256ri */ + }, + { /* 13388 */ + 870, + /* VPSRLWZ256rik */ + }, + { /* 13389 */ + 871, + /* VPSRLWZ256rikz */ + }, + { /* 13390 */ + 905, + /* VPSRLWZ256rm */ + }, + { /* 13391 */ + 906, + /* VPSRLWZ256rmk */ + }, + { /* 13392 */ + 907, + /* VPSRLWZ256rmkz */ + }, + { /* 13393 */ + 908, + /* VPSRLWZ256rr */ + }, + { /* 13394 */ + 909, + /* VPSRLWZ256rrk */ + }, + { /* 13395 */ + 910, + /* VPSRLWZ256rrkz */ + }, + { /* 13396 */ + 875, + /* VPSRLWZmi */ + }, + { /* 13397 */ + 876, + /* VPSRLWZmik */ + }, + { /* 13398 */ + 877, + /* VPSRLWZmikz */ + }, + { /* 13399 */ + 878, + /* VPSRLWZri */ + }, + { /* 13400 */ + 879, + /* VPSRLWZrik */ + }, + { /* 13401 */ + 880, + /* VPSRLWZrikz */ + }, + { /* 13402 */ + 911, + /* VPSRLWZrm */ + }, + { /* 13403 */ + 201, + /* VPSRLWZrmk */ + }, + { /* 13404 */ + 912, + /* VPSRLWZrmkz */ + }, + { /* 13405 */ + 913, + /* VPSRLWZrr */ + }, + { /* 13406 */ + 914, + /* VPSRLWZrrk */ + }, + { /* 13407 */ + 915, + /* VPSRLWZrrkz */ + }, + { /* 13408 */ + 903, + /* VPSRLWri */ + }, + { /* 13409 */ + 235, + /* VPSRLWrm */ + }, + { /* 13410 */ + 236, + /* VPSRLWrr */ + }, + { /* 13411 */ + 204, + /* VPSUBBYrm */ + }, + { /* 13412 */ + 205, + /* VPSUBBYrr */ + }, + { /* 13413 */ + 206, + /* VPSUBBZ128rm */ + }, + { /* 13414 */ + 203, + /* VPSUBBZ128rmk */ + }, + { /* 13415 */ + 210, + /* VPSUBBZ128rmkz */ + }, + { /* 13416 */ + 211, + /* VPSUBBZ128rr */ + }, + { /* 13417 */ + 212, + /* VPSUBBZ128rrk */ + }, + { /* 13418 */ + 213, + /* VPSUBBZ128rrkz */ + }, + { /* 13419 */ + 214, + /* VPSUBBZ256rm */ + }, + { /* 13420 */ + 218, + /* VPSUBBZ256rmk */ + }, + { /* 13421 */ + 219, + /* VPSUBBZ256rmkz */ + }, + { /* 13422 */ + 220, + /* VPSUBBZ256rr */ + }, + { /* 13423 */ + 221, + /* VPSUBBZ256rrk */ + }, + { /* 13424 */ + 222, + /* VPSUBBZ256rrkz */ + }, + { /* 13425 */ + 223, + /* VPSUBBZrm */ + }, + { /* 13426 */ + 227, + /* VPSUBBZrmk */ + }, + { /* 13427 */ + 228, + /* VPSUBBZrmkz */ + }, + { /* 13428 */ + 229, + /* VPSUBBZrr */ + }, + { /* 13429 */ + 233, + /* VPSUBBZrrk */ + }, + { /* 13430 */ + 234, + /* VPSUBBZrrkz */ + }, + { /* 13431 */ + 235, + /* VPSUBBrm */ + }, + { /* 13432 */ + 236, + /* VPSUBBrr */ + }, + { /* 13433 */ + 204, + /* VPSUBDYrm */ + }, + { /* 13434 */ + 205, + /* VPSUBDYrr */ + }, + { /* 13435 */ + 206, + /* VPSUBDZ128rm */ + }, + { /* 13436 */ + 237, + /* VPSUBDZ128rmb */ + }, + { /* 13437 */ + 238, + /* VPSUBDZ128rmbk */ + }, + { /* 13438 */ + 239, + /* VPSUBDZ128rmbkz */ + }, + { /* 13439 */ + 203, + /* VPSUBDZ128rmk */ + }, + { /* 13440 */ + 210, + /* VPSUBDZ128rmkz */ + }, + { /* 13441 */ + 211, + /* VPSUBDZ128rr */ + }, + { /* 13442 */ + 212, + /* VPSUBDZ128rrk */ + }, + { /* 13443 */ + 213, + /* VPSUBDZ128rrkz */ + }, + { /* 13444 */ + 214, + /* VPSUBDZ256rm */ + }, + { /* 13445 */ + 240, + /* VPSUBDZ256rmb */ + }, + { /* 13446 */ + 241, + /* VPSUBDZ256rmbk */ + }, + { /* 13447 */ + 242, + /* VPSUBDZ256rmbkz */ + }, + { /* 13448 */ + 218, + /* VPSUBDZ256rmk */ + }, + { /* 13449 */ + 219, + /* VPSUBDZ256rmkz */ + }, + { /* 13450 */ + 220, + /* VPSUBDZ256rr */ + }, + { /* 13451 */ + 221, + /* VPSUBDZ256rrk */ + }, + { /* 13452 */ + 222, + /* VPSUBDZ256rrkz */ + }, + { /* 13453 */ + 223, + /* VPSUBDZrm */ + }, + { /* 13454 */ + 243, + /* VPSUBDZrmb */ + }, + { /* 13455 */ + 244, + /* VPSUBDZrmbk */ + }, + { /* 13456 */ + 245, + /* VPSUBDZrmbkz */ + }, + { /* 13457 */ + 227, + /* VPSUBDZrmk */ + }, + { /* 13458 */ + 228, + /* VPSUBDZrmkz */ + }, + { /* 13459 */ + 229, + /* VPSUBDZrr */ + }, + { /* 13460 */ + 233, + /* VPSUBDZrrk */ + }, + { /* 13461 */ + 234, + /* VPSUBDZrrkz */ + }, + { /* 13462 */ + 235, + /* VPSUBDrm */ + }, + { /* 13463 */ + 236, + /* VPSUBDrr */ + }, + { /* 13464 */ + 204, + /* VPSUBQYrm */ + }, + { /* 13465 */ + 205, + /* VPSUBQYrr */ + }, + { /* 13466 */ + 206, + /* VPSUBQZ128rm */ + }, + { /* 13467 */ + 207, + /* VPSUBQZ128rmb */ + }, + { /* 13468 */ + 208, + /* VPSUBQZ128rmbk */ + }, + { /* 13469 */ + 209, + /* VPSUBQZ128rmbkz */ + }, + { /* 13470 */ + 203, + /* VPSUBQZ128rmk */ + }, + { /* 13471 */ + 210, + /* VPSUBQZ128rmkz */ + }, + { /* 13472 */ + 211, + /* VPSUBQZ128rr */ + }, + { /* 13473 */ + 212, + /* VPSUBQZ128rrk */ + }, + { /* 13474 */ + 213, + /* VPSUBQZ128rrkz */ + }, + { /* 13475 */ + 214, + /* VPSUBQZ256rm */ + }, + { /* 13476 */ + 215, + /* VPSUBQZ256rmb */ + }, + { /* 13477 */ + 216, + /* VPSUBQZ256rmbk */ + }, + { /* 13478 */ + 217, + /* VPSUBQZ256rmbkz */ + }, + { /* 13479 */ + 218, + /* VPSUBQZ256rmk */ + }, + { /* 13480 */ + 219, + /* VPSUBQZ256rmkz */ + }, + { /* 13481 */ + 220, + /* VPSUBQZ256rr */ + }, + { /* 13482 */ + 221, + /* VPSUBQZ256rrk */ + }, + { /* 13483 */ + 222, + /* VPSUBQZ256rrkz */ + }, + { /* 13484 */ + 223, + /* VPSUBQZrm */ + }, + { /* 13485 */ + 224, + /* VPSUBQZrmb */ + }, + { /* 13486 */ + 225, + /* VPSUBQZrmbk */ + }, + { /* 13487 */ + 226, + /* VPSUBQZrmbkz */ + }, + { /* 13488 */ + 227, + /* VPSUBQZrmk */ + }, + { /* 13489 */ + 228, + /* VPSUBQZrmkz */ + }, + { /* 13490 */ + 229, + /* VPSUBQZrr */ + }, + { /* 13491 */ + 233, + /* VPSUBQZrrk */ + }, + { /* 13492 */ + 234, + /* VPSUBQZrrkz */ + }, + { /* 13493 */ + 235, + /* VPSUBQrm */ + }, + { /* 13494 */ + 236, + /* VPSUBQrr */ + }, + { /* 13495 */ + 204, + /* VPSUBSBYrm */ + }, + { /* 13496 */ + 205, + /* VPSUBSBYrr */ + }, + { /* 13497 */ + 206, + /* VPSUBSBZ128rm */ + }, + { /* 13498 */ + 203, + /* VPSUBSBZ128rmk */ + }, + { /* 13499 */ + 210, + /* VPSUBSBZ128rmkz */ + }, + { /* 13500 */ + 211, + /* VPSUBSBZ128rr */ + }, + { /* 13501 */ + 212, + /* VPSUBSBZ128rrk */ + }, + { /* 13502 */ + 213, + /* VPSUBSBZ128rrkz */ + }, + { /* 13503 */ + 214, + /* VPSUBSBZ256rm */ + }, + { /* 13504 */ + 218, + /* VPSUBSBZ256rmk */ + }, + { /* 13505 */ + 219, + /* VPSUBSBZ256rmkz */ + }, + { /* 13506 */ + 220, + /* VPSUBSBZ256rr */ + }, + { /* 13507 */ + 221, + /* VPSUBSBZ256rrk */ + }, + { /* 13508 */ + 222, + /* VPSUBSBZ256rrkz */ + }, + { /* 13509 */ + 223, + /* VPSUBSBZrm */ + }, + { /* 13510 */ + 227, + /* VPSUBSBZrmk */ + }, + { /* 13511 */ + 228, + /* VPSUBSBZrmkz */ + }, + { /* 13512 */ + 229, + /* VPSUBSBZrr */ + }, + { /* 13513 */ + 233, + /* VPSUBSBZrrk */ + }, + { /* 13514 */ + 234, + /* VPSUBSBZrrkz */ + }, + { /* 13515 */ + 235, + /* VPSUBSBrm */ + }, + { /* 13516 */ + 236, + /* VPSUBSBrr */ + }, + { /* 13517 */ + 204, + /* VPSUBSWYrm */ + }, + { /* 13518 */ + 205, + /* VPSUBSWYrr */ + }, + { /* 13519 */ + 206, + /* VPSUBSWZ128rm */ + }, + { /* 13520 */ + 203, + /* VPSUBSWZ128rmk */ + }, + { /* 13521 */ + 210, + /* VPSUBSWZ128rmkz */ + }, + { /* 13522 */ + 211, + /* VPSUBSWZ128rr */ + }, + { /* 13523 */ + 212, + /* VPSUBSWZ128rrk */ + }, + { /* 13524 */ + 213, + /* VPSUBSWZ128rrkz */ + }, + { /* 13525 */ + 214, + /* VPSUBSWZ256rm */ + }, + { /* 13526 */ + 218, + /* VPSUBSWZ256rmk */ + }, + { /* 13527 */ + 219, + /* VPSUBSWZ256rmkz */ + }, + { /* 13528 */ + 220, + /* VPSUBSWZ256rr */ + }, + { /* 13529 */ + 221, + /* VPSUBSWZ256rrk */ + }, + { /* 13530 */ + 222, + /* VPSUBSWZ256rrkz */ + }, + { /* 13531 */ + 223, + /* VPSUBSWZrm */ + }, + { /* 13532 */ + 227, + /* VPSUBSWZrmk */ + }, + { /* 13533 */ + 228, + /* VPSUBSWZrmkz */ + }, + { /* 13534 */ + 229, + /* VPSUBSWZrr */ + }, + { /* 13535 */ + 233, + /* VPSUBSWZrrk */ + }, + { /* 13536 */ + 234, + /* VPSUBSWZrrkz */ + }, + { /* 13537 */ + 235, + /* VPSUBSWrm */ + }, + { /* 13538 */ + 236, + /* VPSUBSWrr */ + }, + { /* 13539 */ + 204, + /* VPSUBUSBYrm */ + }, + { /* 13540 */ + 205, + /* VPSUBUSBYrr */ + }, + { /* 13541 */ + 206, + /* VPSUBUSBZ128rm */ + }, + { /* 13542 */ + 203, + /* VPSUBUSBZ128rmk */ + }, + { /* 13543 */ + 210, + /* VPSUBUSBZ128rmkz */ + }, + { /* 13544 */ + 211, + /* VPSUBUSBZ128rr */ + }, + { /* 13545 */ + 212, + /* VPSUBUSBZ128rrk */ + }, + { /* 13546 */ + 213, + /* VPSUBUSBZ128rrkz */ + }, + { /* 13547 */ + 214, + /* VPSUBUSBZ256rm */ + }, + { /* 13548 */ + 218, + /* VPSUBUSBZ256rmk */ + }, + { /* 13549 */ + 219, + /* VPSUBUSBZ256rmkz */ + }, + { /* 13550 */ + 220, + /* VPSUBUSBZ256rr */ + }, + { /* 13551 */ + 221, + /* VPSUBUSBZ256rrk */ + }, + { /* 13552 */ + 222, + /* VPSUBUSBZ256rrkz */ + }, + { /* 13553 */ + 223, + /* VPSUBUSBZrm */ + }, + { /* 13554 */ + 227, + /* VPSUBUSBZrmk */ + }, + { /* 13555 */ + 228, + /* VPSUBUSBZrmkz */ + }, + { /* 13556 */ + 229, + /* VPSUBUSBZrr */ + }, + { /* 13557 */ + 233, + /* VPSUBUSBZrrk */ + }, + { /* 13558 */ + 234, + /* VPSUBUSBZrrkz */ + }, + { /* 13559 */ + 235, + /* VPSUBUSBrm */ + }, + { /* 13560 */ + 236, + /* VPSUBUSBrr */ + }, + { /* 13561 */ + 204, + /* VPSUBUSWYrm */ + }, + { /* 13562 */ + 205, + /* VPSUBUSWYrr */ + }, + { /* 13563 */ + 206, + /* VPSUBUSWZ128rm */ + }, + { /* 13564 */ + 203, + /* VPSUBUSWZ128rmk */ + }, + { /* 13565 */ + 210, + /* VPSUBUSWZ128rmkz */ + }, + { /* 13566 */ + 211, + /* VPSUBUSWZ128rr */ + }, + { /* 13567 */ + 212, + /* VPSUBUSWZ128rrk */ + }, + { /* 13568 */ + 213, + /* VPSUBUSWZ128rrkz */ + }, + { /* 13569 */ + 214, + /* VPSUBUSWZ256rm */ + }, + { /* 13570 */ + 218, + /* VPSUBUSWZ256rmk */ + }, + { /* 13571 */ + 219, + /* VPSUBUSWZ256rmkz */ + }, + { /* 13572 */ + 220, + /* VPSUBUSWZ256rr */ + }, + { /* 13573 */ + 221, + /* VPSUBUSWZ256rrk */ + }, + { /* 13574 */ + 222, + /* VPSUBUSWZ256rrkz */ + }, + { /* 13575 */ + 223, + /* VPSUBUSWZrm */ + }, + { /* 13576 */ + 227, + /* VPSUBUSWZrmk */ + }, + { /* 13577 */ + 228, + /* VPSUBUSWZrmkz */ + }, + { /* 13578 */ + 229, + /* VPSUBUSWZrr */ + }, + { /* 13579 */ + 233, + /* VPSUBUSWZrrk */ + }, + { /* 13580 */ + 234, + /* VPSUBUSWZrrkz */ + }, + { /* 13581 */ + 235, + /* VPSUBUSWrm */ + }, + { /* 13582 */ + 236, + /* VPSUBUSWrr */ + }, + { /* 13583 */ + 204, + /* VPSUBWYrm */ + }, + { /* 13584 */ + 205, + /* VPSUBWYrr */ + }, + { /* 13585 */ + 206, + /* VPSUBWZ128rm */ + }, + { /* 13586 */ + 203, + /* VPSUBWZ128rmk */ + }, + { /* 13587 */ + 210, + /* VPSUBWZ128rmkz */ + }, + { /* 13588 */ + 211, + /* VPSUBWZ128rr */ + }, + { /* 13589 */ + 212, + /* VPSUBWZ128rrk */ + }, + { /* 13590 */ + 213, + /* VPSUBWZ128rrkz */ + }, + { /* 13591 */ + 214, + /* VPSUBWZ256rm */ + }, + { /* 13592 */ + 218, + /* VPSUBWZ256rmk */ + }, + { /* 13593 */ + 219, + /* VPSUBWZ256rmkz */ + }, + { /* 13594 */ + 220, + /* VPSUBWZ256rr */ + }, + { /* 13595 */ + 221, + /* VPSUBWZ256rrk */ + }, + { /* 13596 */ + 222, + /* VPSUBWZ256rrkz */ + }, + { /* 13597 */ + 223, + /* VPSUBWZrm */ + }, + { /* 13598 */ + 227, + /* VPSUBWZrmk */ + }, + { /* 13599 */ + 228, + /* VPSUBWZrmkz */ + }, + { /* 13600 */ + 229, + /* VPSUBWZrr */ + }, + { /* 13601 */ + 233, + /* VPSUBWZrrk */ + }, + { /* 13602 */ + 234, + /* VPSUBWZrrkz */ + }, + { /* 13603 */ + 235, + /* VPSUBWrm */ + }, + { /* 13604 */ + 236, + /* VPSUBWrr */ + }, + { /* 13605 */ + 518, + /* VPTERNLOGDZ128rmbi */ + }, + { /* 13606 */ + 262, + /* VPTERNLOGDZ128rmbik */ + }, + { /* 13607 */ + 262, + /* VPTERNLOGDZ128rmbikz */ + }, + { /* 13608 */ + 508, + /* VPTERNLOGDZ128rmi */ + }, + { /* 13609 */ + 265, + /* VPTERNLOGDZ128rmik */ + }, + { /* 13610 */ + 265, + /* VPTERNLOGDZ128rmikz */ + }, + { /* 13611 */ + 509, + /* VPTERNLOGDZ128rri */ + }, + { /* 13612 */ + 268, + /* VPTERNLOGDZ128rrik */ + }, + { /* 13613 */ + 268, + /* VPTERNLOGDZ128rrikz */ + }, + { /* 13614 */ + 519, + /* VPTERNLOGDZ256rmbi */ + }, + { /* 13615 */ + 271, + /* VPTERNLOGDZ256rmbik */ + }, + { /* 13616 */ + 271, + /* VPTERNLOGDZ256rmbikz */ + }, + { /* 13617 */ + 511, + /* VPTERNLOGDZ256rmi */ + }, + { /* 13618 */ + 274, + /* VPTERNLOGDZ256rmik */ + }, + { /* 13619 */ + 274, + /* VPTERNLOGDZ256rmikz */ + }, + { /* 13620 */ + 512, + /* VPTERNLOGDZ256rri */ + }, + { /* 13621 */ + 277, + /* VPTERNLOGDZ256rrik */ + }, + { /* 13622 */ + 277, + /* VPTERNLOGDZ256rrikz */ + }, + { /* 13623 */ + 520, + /* VPTERNLOGDZrmbi */ + }, + { /* 13624 */ + 280, + /* VPTERNLOGDZrmbik */ + }, + { /* 13625 */ + 280, + /* VPTERNLOGDZrmbikz */ + }, + { /* 13626 */ + 514, + /* VPTERNLOGDZrmi */ + }, + { /* 13627 */ + 283, + /* VPTERNLOGDZrmik */ + }, + { /* 13628 */ + 283, + /* VPTERNLOGDZrmikz */ + }, + { /* 13629 */ + 515, + /* VPTERNLOGDZrri */ + }, + { /* 13630 */ + 286, + /* VPTERNLOGDZrrik */ + }, + { /* 13631 */ + 286, + /* VPTERNLOGDZrrikz */ + }, + { /* 13632 */ + 507, + /* VPTERNLOGQZ128rmbi */ + }, + { /* 13633 */ + 289, + /* VPTERNLOGQZ128rmbik */ + }, + { /* 13634 */ + 289, + /* VPTERNLOGQZ128rmbikz */ + }, + { /* 13635 */ + 508, + /* VPTERNLOGQZ128rmi */ + }, + { /* 13636 */ + 265, + /* VPTERNLOGQZ128rmik */ + }, + { /* 13637 */ + 265, + /* VPTERNLOGQZ128rmikz */ + }, + { /* 13638 */ + 509, + /* VPTERNLOGQZ128rri */ + }, + { /* 13639 */ + 268, + /* VPTERNLOGQZ128rrik */ + }, + { /* 13640 */ + 268, + /* VPTERNLOGQZ128rrikz */ + }, + { /* 13641 */ + 510, + /* VPTERNLOGQZ256rmbi */ + }, + { /* 13642 */ + 292, + /* VPTERNLOGQZ256rmbik */ + }, + { /* 13643 */ + 292, + /* VPTERNLOGQZ256rmbikz */ + }, + { /* 13644 */ + 511, + /* VPTERNLOGQZ256rmi */ + }, + { /* 13645 */ + 274, + /* VPTERNLOGQZ256rmik */ + }, + { /* 13646 */ + 274, + /* VPTERNLOGQZ256rmikz */ + }, + { /* 13647 */ + 512, + /* VPTERNLOGQZ256rri */ + }, + { /* 13648 */ + 277, + /* VPTERNLOGQZ256rrik */ + }, + { /* 13649 */ + 277, + /* VPTERNLOGQZ256rrikz */ + }, + { /* 13650 */ + 513, + /* VPTERNLOGQZrmbi */ + }, + { /* 13651 */ + 295, + /* VPTERNLOGQZrmbik */ + }, + { /* 13652 */ + 295, + /* VPTERNLOGQZrmbikz */ + }, + { /* 13653 */ + 514, + /* VPTERNLOGQZrmi */ + }, + { /* 13654 */ + 283, + /* VPTERNLOGQZrmik */ + }, + { /* 13655 */ + 283, + /* VPTERNLOGQZrmikz */ + }, + { /* 13656 */ + 515, + /* VPTERNLOGQZrri */ + }, + { /* 13657 */ + 286, + /* VPTERNLOGQZrrik */ + }, + { /* 13658 */ + 286, + /* VPTERNLOGQZrrikz */ + }, + { /* 13659 */ + 741, + /* VPTESTMBZ128rm */ + }, + { /* 13660 */ + 742, + /* VPTESTMBZ128rmk */ + }, + { /* 13661 */ + 743, + /* VPTESTMBZ128rr */ + }, + { /* 13662 */ + 744, + /* VPTESTMBZ128rrk */ + }, + { /* 13663 */ + 745, + /* VPTESTMBZ256rm */ + }, + { /* 13664 */ + 746, + /* VPTESTMBZ256rmk */ + }, + { /* 13665 */ + 747, + /* VPTESTMBZ256rr */ + }, + { /* 13666 */ + 748, + /* VPTESTMBZ256rrk */ + }, + { /* 13667 */ + 749, + /* VPTESTMBZrm */ + }, + { /* 13668 */ + 750, + /* VPTESTMBZrmk */ + }, + { /* 13669 */ + 751, + /* VPTESTMBZrr */ + }, + { /* 13670 */ + 752, + /* VPTESTMBZrrk */ + }, + { /* 13671 */ + 741, + /* VPTESTMDZ128rm */ + }, + { /* 13672 */ + 753, + /* VPTESTMDZ128rmb */ + }, + { /* 13673 */ + 754, + /* VPTESTMDZ128rmbk */ + }, + { /* 13674 */ + 742, + /* VPTESTMDZ128rmk */ + }, + { /* 13675 */ + 743, + /* VPTESTMDZ128rr */ + }, + { /* 13676 */ + 744, + /* VPTESTMDZ128rrk */ + }, + { /* 13677 */ + 745, + /* VPTESTMDZ256rm */ + }, + { /* 13678 */ + 755, + /* VPTESTMDZ256rmb */ + }, + { /* 13679 */ + 756, + /* VPTESTMDZ256rmbk */ + }, + { /* 13680 */ + 746, + /* VPTESTMDZ256rmk */ + }, + { /* 13681 */ + 747, + /* VPTESTMDZ256rr */ + }, + { /* 13682 */ + 748, + /* VPTESTMDZ256rrk */ + }, + { /* 13683 */ + 749, + /* VPTESTMDZrm */ + }, + { /* 13684 */ + 757, + /* VPTESTMDZrmb */ + }, + { /* 13685 */ + 758, + /* VPTESTMDZrmbk */ + }, + { /* 13686 */ + 750, + /* VPTESTMDZrmk */ + }, + { /* 13687 */ + 751, + /* VPTESTMDZrr */ + }, + { /* 13688 */ + 752, + /* VPTESTMDZrrk */ + }, + { /* 13689 */ + 741, + /* VPTESTMQZ128rm */ + }, + { /* 13690 */ + 759, + /* VPTESTMQZ128rmb */ + }, + { /* 13691 */ + 760, + /* VPTESTMQZ128rmbk */ + }, + { /* 13692 */ + 742, + /* VPTESTMQZ128rmk */ + }, + { /* 13693 */ + 743, + /* VPTESTMQZ128rr */ + }, + { /* 13694 */ + 744, + /* VPTESTMQZ128rrk */ + }, + { /* 13695 */ + 745, + /* VPTESTMQZ256rm */ + }, + { /* 13696 */ + 761, + /* VPTESTMQZ256rmb */ + }, + { /* 13697 */ + 762, + /* VPTESTMQZ256rmbk */ + }, + { /* 13698 */ + 746, + /* VPTESTMQZ256rmk */ + }, + { /* 13699 */ + 747, + /* VPTESTMQZ256rr */ + }, + { /* 13700 */ + 748, + /* VPTESTMQZ256rrk */ + }, + { /* 13701 */ + 749, + /* VPTESTMQZrm */ + }, + { /* 13702 */ + 763, + /* VPTESTMQZrmb */ + }, + { /* 13703 */ + 764, + /* VPTESTMQZrmbk */ + }, + { /* 13704 */ + 750, + /* VPTESTMQZrmk */ + }, + { /* 13705 */ + 751, + /* VPTESTMQZrr */ + }, + { /* 13706 */ + 752, + /* VPTESTMQZrrk */ + }, + { /* 13707 */ + 741, + /* VPTESTMWZ128rm */ + }, + { /* 13708 */ + 742, + /* VPTESTMWZ128rmk */ + }, + { /* 13709 */ + 743, + /* VPTESTMWZ128rr */ + }, + { /* 13710 */ + 744, + /* VPTESTMWZ128rrk */ + }, + { /* 13711 */ + 745, + /* VPTESTMWZ256rm */ + }, + { /* 13712 */ + 746, + /* VPTESTMWZ256rmk */ + }, + { /* 13713 */ + 747, + /* VPTESTMWZ256rr */ + }, + { /* 13714 */ + 748, + /* VPTESTMWZ256rrk */ + }, + { /* 13715 */ + 749, + /* VPTESTMWZrm */ + }, + { /* 13716 */ + 750, + /* VPTESTMWZrmk */ + }, + { /* 13717 */ + 751, + /* VPTESTMWZrr */ + }, + { /* 13718 */ + 752, + /* VPTESTMWZrrk */ + }, + { /* 13719 */ + 741, + /* VPTESTNMBZ128rm */ + }, + { /* 13720 */ + 742, + /* VPTESTNMBZ128rmk */ + }, + { /* 13721 */ + 743, + /* VPTESTNMBZ128rr */ + }, + { /* 13722 */ + 744, + /* VPTESTNMBZ128rrk */ + }, + { /* 13723 */ + 745, + /* VPTESTNMBZ256rm */ + }, + { /* 13724 */ + 746, + /* VPTESTNMBZ256rmk */ + }, + { /* 13725 */ + 747, + /* VPTESTNMBZ256rr */ + }, + { /* 13726 */ + 748, + /* VPTESTNMBZ256rrk */ + }, + { /* 13727 */ + 749, + /* VPTESTNMBZrm */ + }, + { /* 13728 */ + 750, + /* VPTESTNMBZrmk */ + }, + { /* 13729 */ + 751, + /* VPTESTNMBZrr */ + }, + { /* 13730 */ + 752, + /* VPTESTNMBZrrk */ + }, + { /* 13731 */ + 741, + /* VPTESTNMDZ128rm */ + }, + { /* 13732 */ + 753, + /* VPTESTNMDZ128rmb */ + }, + { /* 13733 */ + 754, + /* VPTESTNMDZ128rmbk */ + }, + { /* 13734 */ + 742, + /* VPTESTNMDZ128rmk */ + }, + { /* 13735 */ + 743, + /* VPTESTNMDZ128rr */ + }, + { /* 13736 */ + 744, + /* VPTESTNMDZ128rrk */ + }, + { /* 13737 */ + 745, + /* VPTESTNMDZ256rm */ + }, + { /* 13738 */ + 755, + /* VPTESTNMDZ256rmb */ + }, + { /* 13739 */ + 756, + /* VPTESTNMDZ256rmbk */ + }, + { /* 13740 */ + 746, + /* VPTESTNMDZ256rmk */ + }, + { /* 13741 */ + 747, + /* VPTESTNMDZ256rr */ + }, + { /* 13742 */ + 748, + /* VPTESTNMDZ256rrk */ + }, + { /* 13743 */ + 749, + /* VPTESTNMDZrm */ + }, + { /* 13744 */ + 757, + /* VPTESTNMDZrmb */ + }, + { /* 13745 */ + 758, + /* VPTESTNMDZrmbk */ + }, + { /* 13746 */ + 750, + /* VPTESTNMDZrmk */ + }, + { /* 13747 */ + 751, + /* VPTESTNMDZrr */ + }, + { /* 13748 */ + 752, + /* VPTESTNMDZrrk */ + }, + { /* 13749 */ + 741, + /* VPTESTNMQZ128rm */ + }, + { /* 13750 */ + 759, + /* VPTESTNMQZ128rmb */ + }, + { /* 13751 */ + 760, + /* VPTESTNMQZ128rmbk */ + }, + { /* 13752 */ + 742, + /* VPTESTNMQZ128rmk */ + }, + { /* 13753 */ + 743, + /* VPTESTNMQZ128rr */ + }, + { /* 13754 */ + 744, + /* VPTESTNMQZ128rrk */ + }, + { /* 13755 */ + 745, + /* VPTESTNMQZ256rm */ + }, + { /* 13756 */ + 761, + /* VPTESTNMQZ256rmb */ + }, + { /* 13757 */ + 762, + /* VPTESTNMQZ256rmbk */ + }, + { /* 13758 */ + 746, + /* VPTESTNMQZ256rmk */ + }, + { /* 13759 */ + 747, + /* VPTESTNMQZ256rr */ + }, + { /* 13760 */ + 748, + /* VPTESTNMQZ256rrk */ + }, + { /* 13761 */ + 749, + /* VPTESTNMQZrm */ + }, + { /* 13762 */ + 763, + /* VPTESTNMQZrmb */ + }, + { /* 13763 */ + 764, + /* VPTESTNMQZrmbk */ + }, + { /* 13764 */ + 750, + /* VPTESTNMQZrmk */ + }, + { /* 13765 */ + 751, + /* VPTESTNMQZrr */ + }, + { /* 13766 */ + 752, + /* VPTESTNMQZrrk */ + }, + { /* 13767 */ + 741, + /* VPTESTNMWZ128rm */ + }, + { /* 13768 */ + 742, + /* VPTESTNMWZ128rmk */ + }, + { /* 13769 */ + 743, + /* VPTESTNMWZ128rr */ + }, + { /* 13770 */ + 744, + /* VPTESTNMWZ128rrk */ + }, + { /* 13771 */ + 745, + /* VPTESTNMWZ256rm */ + }, + { /* 13772 */ + 746, + /* VPTESTNMWZ256rmk */ + }, + { /* 13773 */ + 747, + /* VPTESTNMWZ256rr */ + }, + { /* 13774 */ + 748, + /* VPTESTNMWZ256rrk */ + }, + { /* 13775 */ + 749, + /* VPTESTNMWZrm */ + }, + { /* 13776 */ + 750, + /* VPTESTNMWZrmk */ + }, + { /* 13777 */ + 751, + /* VPTESTNMWZrr */ + }, + { /* 13778 */ + 752, + /* VPTESTNMWZrrk */ + }, + { /* 13779 */ + 305, + /* VPTESTYrm */ + }, + { /* 13780 */ + 408, + /* VPTESTYrr */ + }, + { /* 13781 */ + 30, + /* VPTESTrm */ + }, + { /* 13782 */ + 31, + /* VPTESTrr */ + }, + { /* 13783 */ + 204, + /* VPUNPCKHBWYrm */ + }, + { /* 13784 */ + 205, + /* VPUNPCKHBWYrr */ + }, + { /* 13785 */ + 206, + /* VPUNPCKHBWZ128rm */ + }, + { /* 13786 */ + 203, + /* VPUNPCKHBWZ128rmk */ + }, + { /* 13787 */ + 210, + /* VPUNPCKHBWZ128rmkz */ + }, + { /* 13788 */ + 211, + /* VPUNPCKHBWZ128rr */ + }, + { /* 13789 */ + 212, + /* VPUNPCKHBWZ128rrk */ + }, + { /* 13790 */ + 213, + /* VPUNPCKHBWZ128rrkz */ + }, + { /* 13791 */ + 214, + /* VPUNPCKHBWZ256rm */ + }, + { /* 13792 */ + 218, + /* VPUNPCKHBWZ256rmk */ + }, + { /* 13793 */ + 219, + /* VPUNPCKHBWZ256rmkz */ + }, + { /* 13794 */ + 220, + /* VPUNPCKHBWZ256rr */ + }, + { /* 13795 */ + 221, + /* VPUNPCKHBWZ256rrk */ + }, + { /* 13796 */ + 222, + /* VPUNPCKHBWZ256rrkz */ + }, + { /* 13797 */ + 223, + /* VPUNPCKHBWZrm */ + }, + { /* 13798 */ + 227, + /* VPUNPCKHBWZrmk */ + }, + { /* 13799 */ + 228, + /* VPUNPCKHBWZrmkz */ + }, + { /* 13800 */ + 229, + /* VPUNPCKHBWZrr */ + }, + { /* 13801 */ + 233, + /* VPUNPCKHBWZrrk */ + }, + { /* 13802 */ + 234, + /* VPUNPCKHBWZrrkz */ + }, + { /* 13803 */ + 235, + /* VPUNPCKHBWrm */ + }, + { /* 13804 */ + 236, + /* VPUNPCKHBWrr */ + }, + { /* 13805 */ + 204, + /* VPUNPCKHDQYrm */ + }, + { /* 13806 */ + 205, + /* VPUNPCKHDQYrr */ + }, + { /* 13807 */ + 206, + /* VPUNPCKHDQZ128rm */ + }, + { /* 13808 */ + 237, + /* VPUNPCKHDQZ128rmb */ + }, + { /* 13809 */ + 238, + /* VPUNPCKHDQZ128rmbk */ + }, + { /* 13810 */ + 239, + /* VPUNPCKHDQZ128rmbkz */ + }, + { /* 13811 */ + 203, + /* VPUNPCKHDQZ128rmk */ + }, + { /* 13812 */ + 210, + /* VPUNPCKHDQZ128rmkz */ + }, + { /* 13813 */ + 211, + /* VPUNPCKHDQZ128rr */ + }, + { /* 13814 */ + 212, + /* VPUNPCKHDQZ128rrk */ + }, + { /* 13815 */ + 213, + /* VPUNPCKHDQZ128rrkz */ + }, + { /* 13816 */ + 214, + /* VPUNPCKHDQZ256rm */ + }, + { /* 13817 */ + 240, + /* VPUNPCKHDQZ256rmb */ + }, + { /* 13818 */ + 241, + /* VPUNPCKHDQZ256rmbk */ + }, + { /* 13819 */ + 242, + /* VPUNPCKHDQZ256rmbkz */ + }, + { /* 13820 */ + 218, + /* VPUNPCKHDQZ256rmk */ + }, + { /* 13821 */ + 219, + /* VPUNPCKHDQZ256rmkz */ + }, + { /* 13822 */ + 220, + /* VPUNPCKHDQZ256rr */ + }, + { /* 13823 */ + 221, + /* VPUNPCKHDQZ256rrk */ + }, + { /* 13824 */ + 222, + /* VPUNPCKHDQZ256rrkz */ + }, + { /* 13825 */ + 223, + /* VPUNPCKHDQZrm */ + }, + { /* 13826 */ + 243, + /* VPUNPCKHDQZrmb */ + }, + { /* 13827 */ + 244, + /* VPUNPCKHDQZrmbk */ + }, + { /* 13828 */ + 245, + /* VPUNPCKHDQZrmbkz */ + }, + { /* 13829 */ + 227, + /* VPUNPCKHDQZrmk */ + }, + { /* 13830 */ + 228, + /* VPUNPCKHDQZrmkz */ + }, + { /* 13831 */ + 229, + /* VPUNPCKHDQZrr */ + }, + { /* 13832 */ + 233, + /* VPUNPCKHDQZrrk */ + }, + { /* 13833 */ + 234, + /* VPUNPCKHDQZrrkz */ + }, + { /* 13834 */ + 235, + /* VPUNPCKHDQrm */ + }, + { /* 13835 */ + 236, + /* VPUNPCKHDQrr */ + }, + { /* 13836 */ + 204, + /* VPUNPCKHQDQYrm */ + }, + { /* 13837 */ + 205, + /* VPUNPCKHQDQYrr */ + }, + { /* 13838 */ + 206, + /* VPUNPCKHQDQZ128rm */ + }, + { /* 13839 */ + 207, + /* VPUNPCKHQDQZ128rmb */ + }, + { /* 13840 */ + 208, + /* VPUNPCKHQDQZ128rmbk */ + }, + { /* 13841 */ + 209, + /* VPUNPCKHQDQZ128rmbkz */ + }, + { /* 13842 */ + 203, + /* VPUNPCKHQDQZ128rmk */ + }, + { /* 13843 */ + 210, + /* VPUNPCKHQDQZ128rmkz */ + }, + { /* 13844 */ + 211, + /* VPUNPCKHQDQZ128rr */ + }, + { /* 13845 */ + 212, + /* VPUNPCKHQDQZ128rrk */ + }, + { /* 13846 */ + 213, + /* VPUNPCKHQDQZ128rrkz */ + }, + { /* 13847 */ + 214, + /* VPUNPCKHQDQZ256rm */ + }, + { /* 13848 */ + 215, + /* VPUNPCKHQDQZ256rmb */ + }, + { /* 13849 */ + 216, + /* VPUNPCKHQDQZ256rmbk */ + }, + { /* 13850 */ + 217, + /* VPUNPCKHQDQZ256rmbkz */ + }, + { /* 13851 */ + 218, + /* VPUNPCKHQDQZ256rmk */ + }, + { /* 13852 */ + 219, + /* VPUNPCKHQDQZ256rmkz */ + }, + { /* 13853 */ + 220, + /* VPUNPCKHQDQZ256rr */ + }, + { /* 13854 */ + 221, + /* VPUNPCKHQDQZ256rrk */ + }, + { /* 13855 */ + 222, + /* VPUNPCKHQDQZ256rrkz */ + }, + { /* 13856 */ + 223, + /* VPUNPCKHQDQZrm */ + }, + { /* 13857 */ + 224, + /* VPUNPCKHQDQZrmb */ + }, + { /* 13858 */ + 225, + /* VPUNPCKHQDQZrmbk */ + }, + { /* 13859 */ + 226, + /* VPUNPCKHQDQZrmbkz */ + }, + { /* 13860 */ + 227, + /* VPUNPCKHQDQZrmk */ + }, + { /* 13861 */ + 228, + /* VPUNPCKHQDQZrmkz */ + }, + { /* 13862 */ + 229, + /* VPUNPCKHQDQZrr */ + }, + { /* 13863 */ + 233, + /* VPUNPCKHQDQZrrk */ + }, + { /* 13864 */ + 234, + /* VPUNPCKHQDQZrrkz */ + }, + { /* 13865 */ + 235, + /* VPUNPCKHQDQrm */ + }, + { /* 13866 */ + 236, + /* VPUNPCKHQDQrr */ + }, + { /* 13867 */ + 204, + /* VPUNPCKHWDYrm */ + }, + { /* 13868 */ + 205, + /* VPUNPCKHWDYrr */ + }, + { /* 13869 */ + 206, + /* VPUNPCKHWDZ128rm */ + }, + { /* 13870 */ + 203, + /* VPUNPCKHWDZ128rmk */ + }, + { /* 13871 */ + 210, + /* VPUNPCKHWDZ128rmkz */ + }, + { /* 13872 */ + 211, + /* VPUNPCKHWDZ128rr */ + }, + { /* 13873 */ + 212, + /* VPUNPCKHWDZ128rrk */ + }, + { /* 13874 */ + 213, + /* VPUNPCKHWDZ128rrkz */ + }, + { /* 13875 */ + 214, + /* VPUNPCKHWDZ256rm */ + }, + { /* 13876 */ + 218, + /* VPUNPCKHWDZ256rmk */ + }, + { /* 13877 */ + 219, + /* VPUNPCKHWDZ256rmkz */ + }, + { /* 13878 */ + 220, + /* VPUNPCKHWDZ256rr */ + }, + { /* 13879 */ + 221, + /* VPUNPCKHWDZ256rrk */ + }, + { /* 13880 */ + 222, + /* VPUNPCKHWDZ256rrkz */ + }, + { /* 13881 */ + 223, + /* VPUNPCKHWDZrm */ + }, + { /* 13882 */ + 227, + /* VPUNPCKHWDZrmk */ + }, + { /* 13883 */ + 228, + /* VPUNPCKHWDZrmkz */ + }, + { /* 13884 */ + 229, + /* VPUNPCKHWDZrr */ + }, + { /* 13885 */ + 233, + /* VPUNPCKHWDZrrk */ + }, + { /* 13886 */ + 234, + /* VPUNPCKHWDZrrkz */ + }, + { /* 13887 */ + 235, + /* VPUNPCKHWDrm */ + }, + { /* 13888 */ + 236, + /* VPUNPCKHWDrr */ + }, + { /* 13889 */ + 204, + /* VPUNPCKLBWYrm */ + }, + { /* 13890 */ + 205, + /* VPUNPCKLBWYrr */ + }, + { /* 13891 */ + 206, + /* VPUNPCKLBWZ128rm */ + }, + { /* 13892 */ + 203, + /* VPUNPCKLBWZ128rmk */ + }, + { /* 13893 */ + 210, + /* VPUNPCKLBWZ128rmkz */ + }, + { /* 13894 */ + 211, + /* VPUNPCKLBWZ128rr */ + }, + { /* 13895 */ + 212, + /* VPUNPCKLBWZ128rrk */ + }, + { /* 13896 */ + 213, + /* VPUNPCKLBWZ128rrkz */ + }, + { /* 13897 */ + 214, + /* VPUNPCKLBWZ256rm */ + }, + { /* 13898 */ + 218, + /* VPUNPCKLBWZ256rmk */ + }, + { /* 13899 */ + 219, + /* VPUNPCKLBWZ256rmkz */ + }, + { /* 13900 */ + 220, + /* VPUNPCKLBWZ256rr */ + }, + { /* 13901 */ + 221, + /* VPUNPCKLBWZ256rrk */ + }, + { /* 13902 */ + 222, + /* VPUNPCKLBWZ256rrkz */ + }, + { /* 13903 */ + 223, + /* VPUNPCKLBWZrm */ + }, + { /* 13904 */ + 227, + /* VPUNPCKLBWZrmk */ + }, + { /* 13905 */ + 228, + /* VPUNPCKLBWZrmkz */ + }, + { /* 13906 */ + 229, + /* VPUNPCKLBWZrr */ + }, + { /* 13907 */ + 233, + /* VPUNPCKLBWZrrk */ + }, + { /* 13908 */ + 234, + /* VPUNPCKLBWZrrkz */ + }, + { /* 13909 */ + 235, + /* VPUNPCKLBWrm */ + }, + { /* 13910 */ + 236, + /* VPUNPCKLBWrr */ + }, + { /* 13911 */ + 204, + /* VPUNPCKLDQYrm */ + }, + { /* 13912 */ + 205, + /* VPUNPCKLDQYrr */ + }, + { /* 13913 */ + 206, + /* VPUNPCKLDQZ128rm */ + }, + { /* 13914 */ + 237, + /* VPUNPCKLDQZ128rmb */ + }, + { /* 13915 */ + 238, + /* VPUNPCKLDQZ128rmbk */ + }, + { /* 13916 */ + 239, + /* VPUNPCKLDQZ128rmbkz */ + }, + { /* 13917 */ + 203, + /* VPUNPCKLDQZ128rmk */ + }, + { /* 13918 */ + 210, + /* VPUNPCKLDQZ128rmkz */ + }, + { /* 13919 */ + 211, + /* VPUNPCKLDQZ128rr */ + }, + { /* 13920 */ + 212, + /* VPUNPCKLDQZ128rrk */ + }, + { /* 13921 */ + 213, + /* VPUNPCKLDQZ128rrkz */ + }, + { /* 13922 */ + 214, + /* VPUNPCKLDQZ256rm */ + }, + { /* 13923 */ + 240, + /* VPUNPCKLDQZ256rmb */ + }, + { /* 13924 */ + 241, + /* VPUNPCKLDQZ256rmbk */ + }, + { /* 13925 */ + 242, + /* VPUNPCKLDQZ256rmbkz */ + }, + { /* 13926 */ + 218, + /* VPUNPCKLDQZ256rmk */ + }, + { /* 13927 */ + 219, + /* VPUNPCKLDQZ256rmkz */ + }, + { /* 13928 */ + 220, + /* VPUNPCKLDQZ256rr */ + }, + { /* 13929 */ + 221, + /* VPUNPCKLDQZ256rrk */ + }, + { /* 13930 */ + 222, + /* VPUNPCKLDQZ256rrkz */ + }, + { /* 13931 */ + 223, + /* VPUNPCKLDQZrm */ + }, + { /* 13932 */ + 243, + /* VPUNPCKLDQZrmb */ + }, + { /* 13933 */ + 244, + /* VPUNPCKLDQZrmbk */ + }, + { /* 13934 */ + 245, + /* VPUNPCKLDQZrmbkz */ + }, + { /* 13935 */ + 227, + /* VPUNPCKLDQZrmk */ + }, + { /* 13936 */ + 228, + /* VPUNPCKLDQZrmkz */ + }, + { /* 13937 */ + 229, + /* VPUNPCKLDQZrr */ + }, + { /* 13938 */ + 233, + /* VPUNPCKLDQZrrk */ + }, + { /* 13939 */ + 234, + /* VPUNPCKLDQZrrkz */ + }, + { /* 13940 */ + 235, + /* VPUNPCKLDQrm */ + }, + { /* 13941 */ + 236, + /* VPUNPCKLDQrr */ + }, + { /* 13942 */ + 204, + /* VPUNPCKLQDQYrm */ + }, + { /* 13943 */ + 205, + /* VPUNPCKLQDQYrr */ + }, + { /* 13944 */ + 206, + /* VPUNPCKLQDQZ128rm */ + }, + { /* 13945 */ + 207, + /* VPUNPCKLQDQZ128rmb */ + }, + { /* 13946 */ + 208, + /* VPUNPCKLQDQZ128rmbk */ + }, + { /* 13947 */ + 209, + /* VPUNPCKLQDQZ128rmbkz */ + }, + { /* 13948 */ + 203, + /* VPUNPCKLQDQZ128rmk */ + }, + { /* 13949 */ + 210, + /* VPUNPCKLQDQZ128rmkz */ + }, + { /* 13950 */ + 211, + /* VPUNPCKLQDQZ128rr */ + }, + { /* 13951 */ + 212, + /* VPUNPCKLQDQZ128rrk */ + }, + { /* 13952 */ + 213, + /* VPUNPCKLQDQZ128rrkz */ + }, + { /* 13953 */ + 214, + /* VPUNPCKLQDQZ256rm */ + }, + { /* 13954 */ + 215, + /* VPUNPCKLQDQZ256rmb */ + }, + { /* 13955 */ + 216, + /* VPUNPCKLQDQZ256rmbk */ + }, + { /* 13956 */ + 217, + /* VPUNPCKLQDQZ256rmbkz */ + }, + { /* 13957 */ + 218, + /* VPUNPCKLQDQZ256rmk */ + }, + { /* 13958 */ + 219, + /* VPUNPCKLQDQZ256rmkz */ + }, + { /* 13959 */ + 220, + /* VPUNPCKLQDQZ256rr */ + }, + { /* 13960 */ + 221, + /* VPUNPCKLQDQZ256rrk */ + }, + { /* 13961 */ + 222, + /* VPUNPCKLQDQZ256rrkz */ + }, + { /* 13962 */ + 223, + /* VPUNPCKLQDQZrm */ + }, + { /* 13963 */ + 224, + /* VPUNPCKLQDQZrmb */ + }, + { /* 13964 */ + 225, + /* VPUNPCKLQDQZrmbk */ + }, + { /* 13965 */ + 226, + /* VPUNPCKLQDQZrmbkz */ + }, + { /* 13966 */ + 227, + /* VPUNPCKLQDQZrmk */ + }, + { /* 13967 */ + 228, + /* VPUNPCKLQDQZrmkz */ + }, + { /* 13968 */ + 229, + /* VPUNPCKLQDQZrr */ + }, + { /* 13969 */ + 233, + /* VPUNPCKLQDQZrrk */ + }, + { /* 13970 */ + 234, + /* VPUNPCKLQDQZrrkz */ + }, + { /* 13971 */ + 235, + /* VPUNPCKLQDQrm */ + }, + { /* 13972 */ + 236, + /* VPUNPCKLQDQrr */ + }, + { /* 13973 */ + 204, + /* VPUNPCKLWDYrm */ + }, + { /* 13974 */ + 205, + /* VPUNPCKLWDYrr */ + }, + { /* 13975 */ + 206, + /* VPUNPCKLWDZ128rm */ + }, + { /* 13976 */ + 203, + /* VPUNPCKLWDZ128rmk */ + }, + { /* 13977 */ + 210, + /* VPUNPCKLWDZ128rmkz */ + }, + { /* 13978 */ + 211, + /* VPUNPCKLWDZ128rr */ + }, + { /* 13979 */ + 212, + /* VPUNPCKLWDZ128rrk */ + }, + { /* 13980 */ + 213, + /* VPUNPCKLWDZ128rrkz */ + }, + { /* 13981 */ + 214, + /* VPUNPCKLWDZ256rm */ + }, + { /* 13982 */ + 218, + /* VPUNPCKLWDZ256rmk */ + }, + { /* 13983 */ + 219, + /* VPUNPCKLWDZ256rmkz */ + }, + { /* 13984 */ + 220, + /* VPUNPCKLWDZ256rr */ + }, + { /* 13985 */ + 221, + /* VPUNPCKLWDZ256rrk */ + }, + { /* 13986 */ + 222, + /* VPUNPCKLWDZ256rrkz */ + }, + { /* 13987 */ + 223, + /* VPUNPCKLWDZrm */ + }, + { /* 13988 */ + 227, + /* VPUNPCKLWDZrmk */ + }, + { /* 13989 */ + 228, + /* VPUNPCKLWDZrmkz */ + }, + { /* 13990 */ + 229, + /* VPUNPCKLWDZrr */ + }, + { /* 13991 */ + 233, + /* VPUNPCKLWDZrrk */ + }, + { /* 13992 */ + 234, + /* VPUNPCKLWDZrrkz */ + }, + { /* 13993 */ + 235, + /* VPUNPCKLWDrm */ + }, + { /* 13994 */ + 236, + /* VPUNPCKLWDrr */ + }, + { /* 13995 */ + 206, + /* VPXORDZ128rm */ + }, + { /* 13996 */ + 237, + /* VPXORDZ128rmb */ + }, + { /* 13997 */ + 238, + /* VPXORDZ128rmbk */ + }, + { /* 13998 */ + 239, + /* VPXORDZ128rmbkz */ + }, + { /* 13999 */ + 203, + /* VPXORDZ128rmk */ + }, + { /* 14000 */ + 210, + /* VPXORDZ128rmkz */ + }, + { /* 14001 */ + 211, + /* VPXORDZ128rr */ + }, + { /* 14002 */ + 212, + /* VPXORDZ128rrk */ + }, + { /* 14003 */ + 213, + /* VPXORDZ128rrkz */ + }, + { /* 14004 */ + 214, + /* VPXORDZ256rm */ + }, + { /* 14005 */ + 240, + /* VPXORDZ256rmb */ + }, + { /* 14006 */ + 241, + /* VPXORDZ256rmbk */ + }, + { /* 14007 */ + 242, + /* VPXORDZ256rmbkz */ + }, + { /* 14008 */ + 218, + /* VPXORDZ256rmk */ + }, + { /* 14009 */ + 219, + /* VPXORDZ256rmkz */ + }, + { /* 14010 */ + 220, + /* VPXORDZ256rr */ + }, + { /* 14011 */ + 221, + /* VPXORDZ256rrk */ + }, + { /* 14012 */ + 222, + /* VPXORDZ256rrkz */ + }, + { /* 14013 */ + 223, + /* VPXORDZrm */ + }, + { /* 14014 */ + 243, + /* VPXORDZrmb */ + }, + { /* 14015 */ + 244, + /* VPXORDZrmbk */ + }, + { /* 14016 */ + 245, + /* VPXORDZrmbkz */ + }, + { /* 14017 */ + 227, + /* VPXORDZrmk */ + }, + { /* 14018 */ + 228, + /* VPXORDZrmkz */ + }, + { /* 14019 */ + 229, + /* VPXORDZrr */ + }, + { /* 14020 */ + 233, + /* VPXORDZrrk */ + }, + { /* 14021 */ + 234, + /* VPXORDZrrkz */ + }, + { /* 14022 */ + 206, + /* VPXORQZ128rm */ + }, + { /* 14023 */ + 207, + /* VPXORQZ128rmb */ + }, + { /* 14024 */ + 208, + /* VPXORQZ128rmbk */ + }, + { /* 14025 */ + 209, + /* VPXORQZ128rmbkz */ + }, + { /* 14026 */ + 203, + /* VPXORQZ128rmk */ + }, + { /* 14027 */ + 210, + /* VPXORQZ128rmkz */ + }, + { /* 14028 */ + 211, + /* VPXORQZ128rr */ + }, + { /* 14029 */ + 212, + /* VPXORQZ128rrk */ + }, + { /* 14030 */ + 213, + /* VPXORQZ128rrkz */ + }, + { /* 14031 */ + 214, + /* VPXORQZ256rm */ + }, + { /* 14032 */ + 215, + /* VPXORQZ256rmb */ + }, + { /* 14033 */ + 216, + /* VPXORQZ256rmbk */ + }, + { /* 14034 */ + 217, + /* VPXORQZ256rmbkz */ + }, + { /* 14035 */ + 218, + /* VPXORQZ256rmk */ + }, + { /* 14036 */ + 219, + /* VPXORQZ256rmkz */ + }, + { /* 14037 */ + 220, + /* VPXORQZ256rr */ + }, + { /* 14038 */ + 221, + /* VPXORQZ256rrk */ + }, + { /* 14039 */ + 222, + /* VPXORQZ256rrkz */ + }, + { /* 14040 */ + 223, + /* VPXORQZrm */ + }, + { /* 14041 */ + 224, + /* VPXORQZrmb */ + }, + { /* 14042 */ + 225, + /* VPXORQZrmbk */ + }, + { /* 14043 */ + 226, + /* VPXORQZrmbkz */ + }, + { /* 14044 */ + 227, + /* VPXORQZrmk */ + }, + { /* 14045 */ + 228, + /* VPXORQZrmkz */ + }, + { /* 14046 */ + 229, + /* VPXORQZrr */ + }, + { /* 14047 */ + 233, + /* VPXORQZrrk */ + }, + { /* 14048 */ + 234, + /* VPXORQZrrkz */ + }, + { /* 14049 */ + 204, + /* VPXORYrm */ + }, + { /* 14050 */ + 205, + /* VPXORYrr */ + }, + { /* 14051 */ + 235, + /* VPXORrm */ + }, + { /* 14052 */ + 236, + /* VPXORrr */ + }, + { /* 14053 */ + 288, + /* VRANGEPDZ128rmbi */ + }, + { /* 14054 */ + 289, + /* VRANGEPDZ128rmbik */ + }, + { /* 14055 */ + 290, + /* VRANGEPDZ128rmbikz */ + }, + { /* 14056 */ + 264, + /* VRANGEPDZ128rmi */ + }, + { /* 14057 */ + 265, + /* VRANGEPDZ128rmik */ + }, + { /* 14058 */ + 266, + /* VRANGEPDZ128rmikz */ + }, + { /* 14059 */ + 267, + /* VRANGEPDZ128rri */ + }, + { /* 14060 */ + 268, + /* VRANGEPDZ128rrik */ + }, + { /* 14061 */ + 269, + /* VRANGEPDZ128rrikz */ + }, + { /* 14062 */ + 291, + /* VRANGEPDZ256rmbi */ + }, + { /* 14063 */ + 292, + /* VRANGEPDZ256rmbik */ + }, + { /* 14064 */ + 293, + /* VRANGEPDZ256rmbikz */ + }, + { /* 14065 */ + 273, + /* VRANGEPDZ256rmi */ + }, + { /* 14066 */ + 274, + /* VRANGEPDZ256rmik */ + }, + { /* 14067 */ + 275, + /* VRANGEPDZ256rmikz */ + }, + { /* 14068 */ + 276, + /* VRANGEPDZ256rri */ + }, + { /* 14069 */ + 277, + /* VRANGEPDZ256rrik */ + }, + { /* 14070 */ + 278, + /* VRANGEPDZ256rrikz */ + }, + { /* 14071 */ + 294, + /* VRANGEPDZrmbi */ + }, + { /* 14072 */ + 295, + /* VRANGEPDZrmbik */ + }, + { /* 14073 */ + 296, + /* VRANGEPDZrmbikz */ + }, + { /* 14074 */ + 282, + /* VRANGEPDZrmi */ + }, + { /* 14075 */ + 283, + /* VRANGEPDZrmik */ + }, + { /* 14076 */ + 284, + /* VRANGEPDZrmikz */ + }, + { /* 14077 */ + 285, + /* VRANGEPDZrri */ + }, + { /* 14078 */ + 916, + /* VRANGEPDZrrib */ + }, + { /* 14079 */ + 517, + /* VRANGEPDZrribk */ + }, + { /* 14080 */ + 917, + /* VRANGEPDZrribkz */ + }, + { /* 14081 */ + 286, + /* VRANGEPDZrrik */ + }, + { /* 14082 */ + 287, + /* VRANGEPDZrrikz */ + }, + { /* 14083 */ + 261, + /* VRANGEPSZ128rmbi */ + }, + { /* 14084 */ + 262, + /* VRANGEPSZ128rmbik */ + }, + { /* 14085 */ + 263, + /* VRANGEPSZ128rmbikz */ + }, + { /* 14086 */ + 264, + /* VRANGEPSZ128rmi */ + }, + { /* 14087 */ + 265, + /* VRANGEPSZ128rmik */ + }, + { /* 14088 */ + 266, + /* VRANGEPSZ128rmikz */ + }, + { /* 14089 */ + 267, + /* VRANGEPSZ128rri */ + }, + { /* 14090 */ + 268, + /* VRANGEPSZ128rrik */ + }, + { /* 14091 */ + 269, + /* VRANGEPSZ128rrikz */ + }, + { /* 14092 */ + 270, + /* VRANGEPSZ256rmbi */ + }, + { /* 14093 */ + 271, + /* VRANGEPSZ256rmbik */ + }, + { /* 14094 */ + 272, + /* VRANGEPSZ256rmbikz */ + }, + { /* 14095 */ + 273, + /* VRANGEPSZ256rmi */ + }, + { /* 14096 */ + 274, + /* VRANGEPSZ256rmik */ + }, + { /* 14097 */ + 275, + /* VRANGEPSZ256rmikz */ + }, + { /* 14098 */ + 276, + /* VRANGEPSZ256rri */ + }, + { /* 14099 */ + 277, + /* VRANGEPSZ256rrik */ + }, + { /* 14100 */ + 278, + /* VRANGEPSZ256rrikz */ + }, + { /* 14101 */ + 279, + /* VRANGEPSZrmbi */ + }, + { /* 14102 */ + 280, + /* VRANGEPSZrmbik */ + }, + { /* 14103 */ + 281, + /* VRANGEPSZrmbikz */ + }, + { /* 14104 */ + 282, + /* VRANGEPSZrmi */ + }, + { /* 14105 */ + 283, + /* VRANGEPSZrmik */ + }, + { /* 14106 */ + 284, + /* VRANGEPSZrmikz */ + }, + { /* 14107 */ + 285, + /* VRANGEPSZrri */ + }, + { /* 14108 */ + 918, + /* VRANGEPSZrrib */ + }, + { /* 14109 */ + 522, + /* VRANGEPSZrribk */ + }, + { /* 14110 */ + 919, + /* VRANGEPSZrribkz */ + }, + { /* 14111 */ + 286, + /* VRANGEPSZrrik */ + }, + { /* 14112 */ + 287, + /* VRANGEPSZrrikz */ + }, + { /* 14113 */ + 288, + /* VRANGESDZrmi */ + }, + { /* 14114 */ + 289, + /* VRANGESDZrmik */ + }, + { /* 14115 */ + 290, + /* VRANGESDZrmikz */ + }, + { /* 14116 */ + 631, + /* VRANGESDZrri */ + }, + { /* 14117 */ + 631, + /* VRANGESDZrrib */ + }, + { /* 14118 */ + 524, + /* VRANGESDZrribk */ + }, + { /* 14119 */ + 632, + /* VRANGESDZrribkz */ + }, + { /* 14120 */ + 524, + /* VRANGESDZrrik */ + }, + { /* 14121 */ + 632, + /* VRANGESDZrrikz */ + }, + { /* 14122 */ + 261, + /* VRANGESSZrmi */ + }, + { /* 14123 */ + 262, + /* VRANGESSZrmik */ + }, + { /* 14124 */ + 263, + /* VRANGESSZrmikz */ + }, + { /* 14125 */ + 633, + /* VRANGESSZrri */ + }, + { /* 14126 */ + 633, + /* VRANGESSZrrib */ + }, + { /* 14127 */ + 526, + /* VRANGESSZrribk */ + }, + { /* 14128 */ + 634, + /* VRANGESSZrribkz */ + }, + { /* 14129 */ + 526, + /* VRANGESSZrrik */ + }, + { /* 14130 */ + 634, + /* VRANGESSZrrikz */ + }, + { /* 14131 */ + 409, + /* VRCP14PDZ128m */ + }, + { /* 14132 */ + 327, + /* VRCP14PDZ128mb */ + }, + { /* 14133 */ + 328, + /* VRCP14PDZ128mbk */ + }, + { /* 14134 */ + 329, + /* VRCP14PDZ128mbkz */ + }, + { /* 14135 */ + 410, + /* VRCP14PDZ128mk */ + }, + { /* 14136 */ + 411, + /* VRCP14PDZ128mkz */ + }, + { /* 14137 */ + 330, + /* VRCP14PDZ128r */ + }, + { /* 14138 */ + 331, + /* VRCP14PDZ128rk */ + }, + { /* 14139 */ + 332, + /* VRCP14PDZ128rkz */ + }, + { /* 14140 */ + 412, + /* VRCP14PDZ256m */ + }, + { /* 14141 */ + 306, + /* VRCP14PDZ256mb */ + }, + { /* 14142 */ + 307, + /* VRCP14PDZ256mbk */ + }, + { /* 14143 */ + 308, + /* VRCP14PDZ256mbkz */ + }, + { /* 14144 */ + 413, + /* VRCP14PDZ256mk */ + }, + { /* 14145 */ + 414, + /* VRCP14PDZ256mkz */ + }, + { /* 14146 */ + 415, + /* VRCP14PDZ256r */ + }, + { /* 14147 */ + 416, + /* VRCP14PDZ256rk */ + }, + { /* 14148 */ + 417, + /* VRCP14PDZ256rkz */ + }, + { /* 14149 */ + 418, + /* VRCP14PDZm */ + }, + { /* 14150 */ + 312, + /* VRCP14PDZmb */ + }, + { /* 14151 */ + 313, + /* VRCP14PDZmbk */ + }, + { /* 14152 */ + 314, + /* VRCP14PDZmbkz */ + }, + { /* 14153 */ + 419, + /* VRCP14PDZmk */ + }, + { /* 14154 */ + 420, + /* VRCP14PDZmkz */ + }, + { /* 14155 */ + 421, + /* VRCP14PDZr */ + }, + { /* 14156 */ + 425, + /* VRCP14PDZrk */ + }, + { /* 14157 */ + 426, + /* VRCP14PDZrkz */ + }, + { /* 14158 */ + 409, + /* VRCP14PSZ128m */ + }, + { /* 14159 */ + 334, + /* VRCP14PSZ128mb */ + }, + { /* 14160 */ + 335, + /* VRCP14PSZ128mbk */ + }, + { /* 14161 */ + 336, + /* VRCP14PSZ128mbkz */ + }, + { /* 14162 */ + 410, + /* VRCP14PSZ128mk */ + }, + { /* 14163 */ + 411, + /* VRCP14PSZ128mkz */ + }, + { /* 14164 */ + 330, + /* VRCP14PSZ128r */ + }, + { /* 14165 */ + 331, + /* VRCP14PSZ128rk */ + }, + { /* 14166 */ + 332, + /* VRCP14PSZ128rkz */ + }, + { /* 14167 */ + 412, + /* VRCP14PSZ256m */ + }, + { /* 14168 */ + 337, + /* VRCP14PSZ256mb */ + }, + { /* 14169 */ + 338, + /* VRCP14PSZ256mbk */ + }, + { /* 14170 */ + 339, + /* VRCP14PSZ256mbkz */ + }, + { /* 14171 */ + 413, + /* VRCP14PSZ256mk */ + }, + { /* 14172 */ + 414, + /* VRCP14PSZ256mkz */ + }, + { /* 14173 */ + 415, + /* VRCP14PSZ256r */ + }, + { /* 14174 */ + 416, + /* VRCP14PSZ256rk */ + }, + { /* 14175 */ + 417, + /* VRCP14PSZ256rkz */ + }, + { /* 14176 */ + 418, + /* VRCP14PSZm */ + }, + { /* 14177 */ + 340, + /* VRCP14PSZmb */ + }, + { /* 14178 */ + 341, + /* VRCP14PSZmbk */ + }, + { /* 14179 */ + 342, + /* VRCP14PSZmbkz */ + }, + { /* 14180 */ + 419, + /* VRCP14PSZmk */ + }, + { /* 14181 */ + 420, + /* VRCP14PSZmkz */ + }, + { /* 14182 */ + 421, + /* VRCP14PSZr */ + }, + { /* 14183 */ + 425, + /* VRCP14PSZrk */ + }, + { /* 14184 */ + 426, + /* VRCP14PSZrkz */ + }, + { /* 14185 */ + 207, + /* VRCP14SDZrm */ + }, + { /* 14186 */ + 208, + /* VRCP14SDZrmk */ + }, + { /* 14187 */ + 209, + /* VRCP14SDZrmkz */ + }, + { /* 14188 */ + 249, + /* VRCP14SDZrr */ + }, + { /* 14189 */ + 250, + /* VRCP14SDZrrk */ + }, + { /* 14190 */ + 251, + /* VRCP14SDZrrkz */ + }, + { /* 14191 */ + 237, + /* VRCP14SSZrm */ + }, + { /* 14192 */ + 238, + /* VRCP14SSZrmk */ + }, + { /* 14193 */ + 239, + /* VRCP14SSZrmkz */ + }, + { /* 14194 */ + 255, + /* VRCP14SSZrr */ + }, + { /* 14195 */ + 256, + /* VRCP14SSZrrk */ + }, + { /* 14196 */ + 257, + /* VRCP14SSZrrkz */ + }, + { /* 14197 */ + 418, + /* VRCP28PDZm */ + }, + { /* 14198 */ + 312, + /* VRCP28PDZmb */ + }, + { /* 14199 */ + 313, + /* VRCP28PDZmbk */ + }, + { /* 14200 */ + 314, + /* VRCP28PDZmbkz */ + }, + { /* 14201 */ + 419, + /* VRCP28PDZmk */ + }, + { /* 14202 */ + 420, + /* VRCP28PDZmkz */ + }, + { /* 14203 */ + 421, + /* VRCP28PDZr */ + }, + { /* 14204 */ + 494, + /* VRCP28PDZrb */ + }, + { /* 14205 */ + 495, + /* VRCP28PDZrbk */ + }, + { /* 14206 */ + 496, + /* VRCP28PDZrbkz */ + }, + { /* 14207 */ + 425, + /* VRCP28PDZrk */ + }, + { /* 14208 */ + 426, + /* VRCP28PDZrkz */ + }, + { /* 14209 */ + 418, + /* VRCP28PSZm */ + }, + { /* 14210 */ + 340, + /* VRCP28PSZmb */ + }, + { /* 14211 */ + 341, + /* VRCP28PSZmbk */ + }, + { /* 14212 */ + 342, + /* VRCP28PSZmbkz */ + }, + { /* 14213 */ + 419, + /* VRCP28PSZmk */ + }, + { /* 14214 */ + 420, + /* VRCP28PSZmkz */ + }, + { /* 14215 */ + 421, + /* VRCP28PSZr */ + }, + { /* 14216 */ + 497, + /* VRCP28PSZrb */ + }, + { /* 14217 */ + 498, + /* VRCP28PSZrbk */ + }, + { /* 14218 */ + 499, + /* VRCP28PSZrbkz */ + }, + { /* 14219 */ + 425, + /* VRCP28PSZrk */ + }, + { /* 14220 */ + 426, + /* VRCP28PSZrkz */ + }, + { /* 14221 */ + 207, + /* VRCP28SDZm */ + }, + { /* 14222 */ + 208, + /* VRCP28SDZmk */ + }, + { /* 14223 */ + 209, + /* VRCP28SDZmkz */ + }, + { /* 14224 */ + 249, + /* VRCP28SDZr */ + }, + { /* 14225 */ + 249, + /* VRCP28SDZrb */ + }, + { /* 14226 */ + 250, + /* VRCP28SDZrbk */ + }, + { /* 14227 */ + 251, + /* VRCP28SDZrbkz */ + }, + { /* 14228 */ + 250, + /* VRCP28SDZrk */ + }, + { /* 14229 */ + 251, + /* VRCP28SDZrkz */ + }, + { /* 14230 */ + 237, + /* VRCP28SSZm */ + }, + { /* 14231 */ + 238, + /* VRCP28SSZmk */ + }, + { /* 14232 */ + 239, + /* VRCP28SSZmkz */ + }, + { /* 14233 */ + 255, + /* VRCP28SSZr */ + }, + { /* 14234 */ + 255, + /* VRCP28SSZrb */ + }, + { /* 14235 */ + 256, + /* VRCP28SSZrbk */ + }, + { /* 14236 */ + 257, + /* VRCP28SSZrbkz */ + }, + { /* 14237 */ + 256, + /* VRCP28SSZrk */ + }, + { /* 14238 */ + 257, + /* VRCP28SSZrkz */ + }, + { /* 14239 */ + 305, + /* VRCPPSYm */ + }, + { /* 14240 */ + 408, + /* VRCPPSYr */ + }, + { /* 14241 */ + 30, + /* VRCPPSm */ + }, + { /* 14242 */ + 31, + /* VRCPPSr */ + }, + { /* 14243 */ + 235, + /* VRCPSSm */ + }, + { /* 14244 */ + 0, + /* */ + }, + { /* 14245 */ + 236, + /* VRCPSSr */ + }, + { /* 14246 */ + 0, + /* */ + }, + { /* 14247 */ + 589, + /* VREDUCEPDZ128rmbi */ + }, + { /* 14248 */ + 590, + /* VREDUCEPDZ128rmbik */ + }, + { /* 14249 */ + 591, + /* VREDUCEPDZ128rmbikz */ + }, + { /* 14250 */ + 592, + /* VREDUCEPDZ128rmi */ + }, + { /* 14251 */ + 593, + /* VREDUCEPDZ128rmik */ + }, + { /* 14252 */ + 594, + /* VREDUCEPDZ128rmikz */ + }, + { /* 14253 */ + 595, + /* VREDUCEPDZ128rri */ + }, + { /* 14254 */ + 596, + /* VREDUCEPDZ128rrik */ + }, + { /* 14255 */ + 597, + /* VREDUCEPDZ128rrikz */ + }, + { /* 14256 */ + 598, + /* VREDUCEPDZ256rmbi */ + }, + { /* 14257 */ + 599, + /* VREDUCEPDZ256rmbik */ + }, + { /* 14258 */ + 600, + /* VREDUCEPDZ256rmbikz */ + }, + { /* 14259 */ + 601, + /* VREDUCEPDZ256rmi */ + }, + { /* 14260 */ + 602, + /* VREDUCEPDZ256rmik */ + }, + { /* 14261 */ + 603, + /* VREDUCEPDZ256rmikz */ + }, + { /* 14262 */ + 604, + /* VREDUCEPDZ256rri */ + }, + { /* 14263 */ + 605, + /* VREDUCEPDZ256rrik */ + }, + { /* 14264 */ + 606, + /* VREDUCEPDZ256rrikz */ + }, + { /* 14265 */ + 607, + /* VREDUCEPDZrmbi */ + }, + { /* 14266 */ + 608, + /* VREDUCEPDZrmbik */ + }, + { /* 14267 */ + 609, + /* VREDUCEPDZrmbikz */ + }, + { /* 14268 */ + 610, + /* VREDUCEPDZrmi */ + }, + { /* 14269 */ + 611, + /* VREDUCEPDZrmik */ + }, + { /* 14270 */ + 612, + /* VREDUCEPDZrmikz */ + }, + { /* 14271 */ + 613, + /* VREDUCEPDZrri */ + }, + { /* 14272 */ + 614, + /* VREDUCEPDZrrib */ + }, + { /* 14273 */ + 615, + /* VREDUCEPDZrribk */ + }, + { /* 14274 */ + 616, + /* VREDUCEPDZrribkz */ + }, + { /* 14275 */ + 617, + /* VREDUCEPDZrrik */ + }, + { /* 14276 */ + 618, + /* VREDUCEPDZrrikz */ + }, + { /* 14277 */ + 619, + /* VREDUCEPSZ128rmbi */ + }, + { /* 14278 */ + 620, + /* VREDUCEPSZ128rmbik */ + }, + { /* 14279 */ + 621, + /* VREDUCEPSZ128rmbikz */ + }, + { /* 14280 */ + 592, + /* VREDUCEPSZ128rmi */ + }, + { /* 14281 */ + 593, + /* VREDUCEPSZ128rmik */ + }, + { /* 14282 */ + 594, + /* VREDUCEPSZ128rmikz */ + }, + { /* 14283 */ + 595, + /* VREDUCEPSZ128rri */ + }, + { /* 14284 */ + 596, + /* VREDUCEPSZ128rrik */ + }, + { /* 14285 */ + 597, + /* VREDUCEPSZ128rrikz */ + }, + { /* 14286 */ + 622, + /* VREDUCEPSZ256rmbi */ + }, + { /* 14287 */ + 623, + /* VREDUCEPSZ256rmbik */ + }, + { /* 14288 */ + 624, + /* VREDUCEPSZ256rmbikz */ + }, + { /* 14289 */ + 601, + /* VREDUCEPSZ256rmi */ + }, + { /* 14290 */ + 602, + /* VREDUCEPSZ256rmik */ + }, + { /* 14291 */ + 603, + /* VREDUCEPSZ256rmikz */ + }, + { /* 14292 */ + 604, + /* VREDUCEPSZ256rri */ + }, + { /* 14293 */ + 605, + /* VREDUCEPSZ256rrik */ + }, + { /* 14294 */ + 606, + /* VREDUCEPSZ256rrikz */ + }, + { /* 14295 */ + 625, + /* VREDUCEPSZrmbi */ + }, + { /* 14296 */ + 626, + /* VREDUCEPSZrmbik */ + }, + { /* 14297 */ + 627, + /* VREDUCEPSZrmbikz */ + }, + { /* 14298 */ + 610, + /* VREDUCEPSZrmi */ + }, + { /* 14299 */ + 611, + /* VREDUCEPSZrmik */ + }, + { /* 14300 */ + 612, + /* VREDUCEPSZrmikz */ + }, + { /* 14301 */ + 613, + /* VREDUCEPSZrri */ + }, + { /* 14302 */ + 628, + /* VREDUCEPSZrrib */ + }, + { /* 14303 */ + 629, + /* VREDUCEPSZrribk */ + }, + { /* 14304 */ + 630, + /* VREDUCEPSZrribkz */ + }, + { /* 14305 */ + 617, + /* VREDUCEPSZrrik */ + }, + { /* 14306 */ + 618, + /* VREDUCEPSZrrikz */ + }, + { /* 14307 */ + 288, + /* VREDUCESDZrmi */ + }, + { /* 14308 */ + 289, + /* VREDUCESDZrmik */ + }, + { /* 14309 */ + 290, + /* VREDUCESDZrmikz */ + }, + { /* 14310 */ + 631, + /* VREDUCESDZrri */ + }, + { /* 14311 */ + 631, + /* VREDUCESDZrrib */ + }, + { /* 14312 */ + 524, + /* VREDUCESDZrribk */ + }, + { /* 14313 */ + 632, + /* VREDUCESDZrribkz */ + }, + { /* 14314 */ + 524, + /* VREDUCESDZrrik */ + }, + { /* 14315 */ + 632, + /* VREDUCESDZrrikz */ + }, + { /* 14316 */ + 261, + /* VREDUCESSZrmi */ + }, + { /* 14317 */ + 262, + /* VREDUCESSZrmik */ + }, + { /* 14318 */ + 263, + /* VREDUCESSZrmikz */ + }, + { /* 14319 */ + 633, + /* VREDUCESSZrri */ + }, + { /* 14320 */ + 633, + /* VREDUCESSZrrib */ + }, + { /* 14321 */ + 526, + /* VREDUCESSZrribk */ + }, + { /* 14322 */ + 634, + /* VREDUCESSZrribkz */ + }, + { /* 14323 */ + 526, + /* VREDUCESSZrrik */ + }, + { /* 14324 */ + 634, + /* VREDUCESSZrrikz */ + }, + { /* 14325 */ + 589, + /* VRNDSCALEPDZ128rmbi */ + }, + { /* 14326 */ + 590, + /* VRNDSCALEPDZ128rmbik */ + }, + { /* 14327 */ + 591, + /* VRNDSCALEPDZ128rmbikz */ + }, + { /* 14328 */ + 592, + /* VRNDSCALEPDZ128rmi */ + }, + { /* 14329 */ + 593, + /* VRNDSCALEPDZ128rmik */ + }, + { /* 14330 */ + 594, + /* VRNDSCALEPDZ128rmikz */ + }, + { /* 14331 */ + 595, + /* VRNDSCALEPDZ128rri */ + }, + { /* 14332 */ + 596, + /* VRNDSCALEPDZ128rrik */ + }, + { /* 14333 */ + 597, + /* VRNDSCALEPDZ128rrikz */ + }, + { /* 14334 */ + 598, + /* VRNDSCALEPDZ256rmbi */ + }, + { /* 14335 */ + 599, + /* VRNDSCALEPDZ256rmbik */ + }, + { /* 14336 */ + 600, + /* VRNDSCALEPDZ256rmbikz */ + }, + { /* 14337 */ + 601, + /* VRNDSCALEPDZ256rmi */ + }, + { /* 14338 */ + 602, + /* VRNDSCALEPDZ256rmik */ + }, + { /* 14339 */ + 603, + /* VRNDSCALEPDZ256rmikz */ + }, + { /* 14340 */ + 604, + /* VRNDSCALEPDZ256rri */ + }, + { /* 14341 */ + 605, + /* VRNDSCALEPDZ256rrik */ + }, + { /* 14342 */ + 606, + /* VRNDSCALEPDZ256rrikz */ + }, + { /* 14343 */ + 607, + /* VRNDSCALEPDZrmbi */ + }, + { /* 14344 */ + 608, + /* VRNDSCALEPDZrmbik */ + }, + { /* 14345 */ + 609, + /* VRNDSCALEPDZrmbikz */ + }, + { /* 14346 */ + 610, + /* VRNDSCALEPDZrmi */ + }, + { /* 14347 */ + 611, + /* VRNDSCALEPDZrmik */ + }, + { /* 14348 */ + 612, + /* VRNDSCALEPDZrmikz */ + }, + { /* 14349 */ + 613, + /* VRNDSCALEPDZrri */ + }, + { /* 14350 */ + 614, + /* VRNDSCALEPDZrrib */ + }, + { /* 14351 */ + 615, + /* VRNDSCALEPDZrribk */ + }, + { /* 14352 */ + 616, + /* VRNDSCALEPDZrribkz */ + }, + { /* 14353 */ + 617, + /* VRNDSCALEPDZrrik */ + }, + { /* 14354 */ + 618, + /* VRNDSCALEPDZrrikz */ + }, + { /* 14355 */ + 619, + /* VRNDSCALEPSZ128rmbi */ + }, + { /* 14356 */ + 620, + /* VRNDSCALEPSZ128rmbik */ + }, + { /* 14357 */ + 621, + /* VRNDSCALEPSZ128rmbikz */ + }, + { /* 14358 */ + 592, + /* VRNDSCALEPSZ128rmi */ + }, + { /* 14359 */ + 593, + /* VRNDSCALEPSZ128rmik */ + }, + { /* 14360 */ + 594, + /* VRNDSCALEPSZ128rmikz */ + }, + { /* 14361 */ + 595, + /* VRNDSCALEPSZ128rri */ + }, + { /* 14362 */ + 596, + /* VRNDSCALEPSZ128rrik */ + }, + { /* 14363 */ + 597, + /* VRNDSCALEPSZ128rrikz */ + }, + { /* 14364 */ + 622, + /* VRNDSCALEPSZ256rmbi */ + }, + { /* 14365 */ + 623, + /* VRNDSCALEPSZ256rmbik */ + }, + { /* 14366 */ + 624, + /* VRNDSCALEPSZ256rmbikz */ + }, + { /* 14367 */ + 601, + /* VRNDSCALEPSZ256rmi */ + }, + { /* 14368 */ + 602, + /* VRNDSCALEPSZ256rmik */ + }, + { /* 14369 */ + 603, + /* VRNDSCALEPSZ256rmikz */ + }, + { /* 14370 */ + 604, + /* VRNDSCALEPSZ256rri */ + }, + { /* 14371 */ + 605, + /* VRNDSCALEPSZ256rrik */ + }, + { /* 14372 */ + 606, + /* VRNDSCALEPSZ256rrikz */ + }, + { /* 14373 */ + 625, + /* VRNDSCALEPSZrmbi */ + }, + { /* 14374 */ + 626, + /* VRNDSCALEPSZrmbik */ + }, + { /* 14375 */ + 627, + /* VRNDSCALEPSZrmbikz */ + }, + { /* 14376 */ + 610, + /* VRNDSCALEPSZrmi */ + }, + { /* 14377 */ + 611, + /* VRNDSCALEPSZrmik */ + }, + { /* 14378 */ + 612, + /* VRNDSCALEPSZrmikz */ + }, + { /* 14379 */ + 613, + /* VRNDSCALEPSZrri */ + }, + { /* 14380 */ + 628, + /* VRNDSCALEPSZrrib */ + }, + { /* 14381 */ + 629, + /* VRNDSCALEPSZrribk */ + }, + { /* 14382 */ + 630, + /* VRNDSCALEPSZrribkz */ + }, + { /* 14383 */ + 617, + /* VRNDSCALEPSZrrik */ + }, + { /* 14384 */ + 618, + /* VRNDSCALEPSZrrikz */ + }, + { /* 14385 */ + 0, + /* */ + }, + { /* 14386 */ + 288, + /* VRNDSCALESDZm_Int */ + }, + { /* 14387 */ + 289, + /* VRNDSCALESDZm_Intk */ + }, + { /* 14388 */ + 290, + /* VRNDSCALESDZm_Intkz */ + }, + { /* 14389 */ + 0, + /* */ + }, + { /* 14390 */ + 631, + /* VRNDSCALESDZr_Int */ + }, + { /* 14391 */ + 524, + /* VRNDSCALESDZr_Intk */ + }, + { /* 14392 */ + 632, + /* VRNDSCALESDZr_Intkz */ + }, + { /* 14393 */ + 631, + /* VRNDSCALESDZrb_Int */ + }, + { /* 14394 */ + 524, + /* VRNDSCALESDZrb_Intk */ + }, + { /* 14395 */ + 632, + /* VRNDSCALESDZrb_Intkz */ + }, + { /* 14396 */ + 0, + /* */ + }, + { /* 14397 */ + 261, + /* VRNDSCALESSZm_Int */ + }, + { /* 14398 */ + 262, + /* VRNDSCALESSZm_Intk */ + }, + { /* 14399 */ + 263, + /* VRNDSCALESSZm_Intkz */ + }, + { /* 14400 */ + 0, + /* */ + }, + { /* 14401 */ + 633, + /* VRNDSCALESSZr_Int */ + }, + { /* 14402 */ + 526, + /* VRNDSCALESSZr_Intk */ + }, + { /* 14403 */ + 634, + /* VRNDSCALESSZr_Intkz */ + }, + { /* 14404 */ + 633, + /* VRNDSCALESSZrb_Int */ + }, + { /* 14405 */ + 526, + /* VRNDSCALESSZrb_Intk */ + }, + { /* 14406 */ + 634, + /* VRNDSCALESSZrb_Intkz */ + }, + { /* 14407 */ + 791, + /* VROUNDPDYm */ + }, + { /* 14408 */ + 792, + /* VROUNDPDYr */ + }, + { /* 14409 */ + 32, + /* VROUNDPDm */ + }, + { /* 14410 */ + 33, + /* VROUNDPDr */ + }, + { /* 14411 */ + 791, + /* VROUNDPSYm */ + }, + { /* 14412 */ + 792, + /* VROUNDPSYr */ + }, + { /* 14413 */ + 32, + /* VROUNDPSm */ + }, + { /* 14414 */ + 33, + /* VROUNDPSr */ + }, + { /* 14415 */ + 299, + /* VROUNDSDm */ + }, + { /* 14416 */ + 0, + /* */ + }, + { /* 14417 */ + 300, + /* VROUNDSDr */ + }, + { /* 14418 */ + 0, + /* */ + }, + { /* 14419 */ + 299, + /* VROUNDSSm */ + }, + { /* 14420 */ + 0, + /* */ + }, + { /* 14421 */ + 300, + /* VROUNDSSr */ + }, + { /* 14422 */ + 0, + /* */ + }, + { /* 14423 */ + 409, + /* VRSQRT14PDZ128m */ + }, + { /* 14424 */ + 327, + /* VRSQRT14PDZ128mb */ + }, + { /* 14425 */ + 328, + /* VRSQRT14PDZ128mbk */ + }, + { /* 14426 */ + 329, + /* VRSQRT14PDZ128mbkz */ + }, + { /* 14427 */ + 410, + /* VRSQRT14PDZ128mk */ + }, + { /* 14428 */ + 411, + /* VRSQRT14PDZ128mkz */ + }, + { /* 14429 */ + 330, + /* VRSQRT14PDZ128r */ + }, + { /* 14430 */ + 331, + /* VRSQRT14PDZ128rk */ + }, + { /* 14431 */ + 332, + /* VRSQRT14PDZ128rkz */ + }, + { /* 14432 */ + 412, + /* VRSQRT14PDZ256m */ + }, + { /* 14433 */ + 306, + /* VRSQRT14PDZ256mb */ + }, + { /* 14434 */ + 307, + /* VRSQRT14PDZ256mbk */ + }, + { /* 14435 */ + 308, + /* VRSQRT14PDZ256mbkz */ + }, + { /* 14436 */ + 413, + /* VRSQRT14PDZ256mk */ + }, + { /* 14437 */ + 414, + /* VRSQRT14PDZ256mkz */ + }, + { /* 14438 */ + 415, + /* VRSQRT14PDZ256r */ + }, + { /* 14439 */ + 416, + /* VRSQRT14PDZ256rk */ + }, + { /* 14440 */ + 417, + /* VRSQRT14PDZ256rkz */ + }, + { /* 14441 */ + 418, + /* VRSQRT14PDZm */ + }, + { /* 14442 */ + 312, + /* VRSQRT14PDZmb */ + }, + { /* 14443 */ + 313, + /* VRSQRT14PDZmbk */ + }, + { /* 14444 */ + 314, + /* VRSQRT14PDZmbkz */ + }, + { /* 14445 */ + 419, + /* VRSQRT14PDZmk */ + }, + { /* 14446 */ + 420, + /* VRSQRT14PDZmkz */ + }, + { /* 14447 */ + 421, + /* VRSQRT14PDZr */ + }, + { /* 14448 */ + 425, + /* VRSQRT14PDZrk */ + }, + { /* 14449 */ + 426, + /* VRSQRT14PDZrkz */ + }, + { /* 14450 */ + 409, + /* VRSQRT14PSZ128m */ + }, + { /* 14451 */ + 334, + /* VRSQRT14PSZ128mb */ + }, + { /* 14452 */ + 335, + /* VRSQRT14PSZ128mbk */ + }, + { /* 14453 */ + 336, + /* VRSQRT14PSZ128mbkz */ + }, + { /* 14454 */ + 410, + /* VRSQRT14PSZ128mk */ + }, + { /* 14455 */ + 411, + /* VRSQRT14PSZ128mkz */ + }, + { /* 14456 */ + 330, + /* VRSQRT14PSZ128r */ + }, + { /* 14457 */ + 331, + /* VRSQRT14PSZ128rk */ + }, + { /* 14458 */ + 332, + /* VRSQRT14PSZ128rkz */ + }, + { /* 14459 */ + 412, + /* VRSQRT14PSZ256m */ + }, + { /* 14460 */ + 337, + /* VRSQRT14PSZ256mb */ + }, + { /* 14461 */ + 338, + /* VRSQRT14PSZ256mbk */ + }, + { /* 14462 */ + 339, + /* VRSQRT14PSZ256mbkz */ + }, + { /* 14463 */ + 413, + /* VRSQRT14PSZ256mk */ + }, + { /* 14464 */ + 414, + /* VRSQRT14PSZ256mkz */ + }, + { /* 14465 */ + 415, + /* VRSQRT14PSZ256r */ + }, + { /* 14466 */ + 416, + /* VRSQRT14PSZ256rk */ + }, + { /* 14467 */ + 417, + /* VRSQRT14PSZ256rkz */ + }, + { /* 14468 */ + 418, + /* VRSQRT14PSZm */ + }, + { /* 14469 */ + 340, + /* VRSQRT14PSZmb */ + }, + { /* 14470 */ + 341, + /* VRSQRT14PSZmbk */ + }, + { /* 14471 */ + 342, + /* VRSQRT14PSZmbkz */ + }, + { /* 14472 */ + 419, + /* VRSQRT14PSZmk */ + }, + { /* 14473 */ + 420, + /* VRSQRT14PSZmkz */ + }, + { /* 14474 */ + 421, + /* VRSQRT14PSZr */ + }, + { /* 14475 */ + 425, + /* VRSQRT14PSZrk */ + }, + { /* 14476 */ + 426, + /* VRSQRT14PSZrkz */ + }, + { /* 14477 */ + 207, + /* VRSQRT14SDZrm */ + }, + { /* 14478 */ + 208, + /* VRSQRT14SDZrmk */ + }, + { /* 14479 */ + 209, + /* VRSQRT14SDZrmkz */ + }, + { /* 14480 */ + 249, + /* VRSQRT14SDZrr */ + }, + { /* 14481 */ + 250, + /* VRSQRT14SDZrrk */ + }, + { /* 14482 */ + 251, + /* VRSQRT14SDZrrkz */ + }, + { /* 14483 */ + 237, + /* VRSQRT14SSZrm */ + }, + { /* 14484 */ + 238, + /* VRSQRT14SSZrmk */ + }, + { /* 14485 */ + 239, + /* VRSQRT14SSZrmkz */ + }, + { /* 14486 */ + 255, + /* VRSQRT14SSZrr */ + }, + { /* 14487 */ + 256, + /* VRSQRT14SSZrrk */ + }, + { /* 14488 */ + 257, + /* VRSQRT14SSZrrkz */ + }, + { /* 14489 */ + 418, + /* VRSQRT28PDZm */ + }, + { /* 14490 */ + 312, + /* VRSQRT28PDZmb */ + }, + { /* 14491 */ + 313, + /* VRSQRT28PDZmbk */ + }, + { /* 14492 */ + 314, + /* VRSQRT28PDZmbkz */ + }, + { /* 14493 */ + 419, + /* VRSQRT28PDZmk */ + }, + { /* 14494 */ + 420, + /* VRSQRT28PDZmkz */ + }, + { /* 14495 */ + 421, + /* VRSQRT28PDZr */ + }, + { /* 14496 */ + 494, + /* VRSQRT28PDZrb */ + }, + { /* 14497 */ + 495, + /* VRSQRT28PDZrbk */ + }, + { /* 14498 */ + 496, + /* VRSQRT28PDZrbkz */ + }, + { /* 14499 */ + 425, + /* VRSQRT28PDZrk */ + }, + { /* 14500 */ + 426, + /* VRSQRT28PDZrkz */ + }, + { /* 14501 */ + 418, + /* VRSQRT28PSZm */ + }, + { /* 14502 */ + 340, + /* VRSQRT28PSZmb */ + }, + { /* 14503 */ + 341, + /* VRSQRT28PSZmbk */ + }, + { /* 14504 */ + 342, + /* VRSQRT28PSZmbkz */ + }, + { /* 14505 */ + 419, + /* VRSQRT28PSZmk */ + }, + { /* 14506 */ + 420, + /* VRSQRT28PSZmkz */ + }, + { /* 14507 */ + 421, + /* VRSQRT28PSZr */ + }, + { /* 14508 */ + 497, + /* VRSQRT28PSZrb */ + }, + { /* 14509 */ + 498, + /* VRSQRT28PSZrbk */ + }, + { /* 14510 */ + 499, + /* VRSQRT28PSZrbkz */ + }, + { /* 14511 */ + 425, + /* VRSQRT28PSZrk */ + }, + { /* 14512 */ + 426, + /* VRSQRT28PSZrkz */ + }, + { /* 14513 */ + 207, + /* VRSQRT28SDZm */ + }, + { /* 14514 */ + 208, + /* VRSQRT28SDZmk */ + }, + { /* 14515 */ + 209, + /* VRSQRT28SDZmkz */ + }, + { /* 14516 */ + 249, + /* VRSQRT28SDZr */ + }, + { /* 14517 */ + 249, + /* VRSQRT28SDZrb */ + }, + { /* 14518 */ + 250, + /* VRSQRT28SDZrbk */ + }, + { /* 14519 */ + 251, + /* VRSQRT28SDZrbkz */ + }, + { /* 14520 */ + 250, + /* VRSQRT28SDZrk */ + }, + { /* 14521 */ + 251, + /* VRSQRT28SDZrkz */ + }, + { /* 14522 */ + 237, + /* VRSQRT28SSZm */ + }, + { /* 14523 */ + 238, + /* VRSQRT28SSZmk */ + }, + { /* 14524 */ + 239, + /* VRSQRT28SSZmkz */ + }, + { /* 14525 */ + 255, + /* VRSQRT28SSZr */ + }, + { /* 14526 */ + 255, + /* VRSQRT28SSZrb */ + }, + { /* 14527 */ + 256, + /* VRSQRT28SSZrbk */ + }, + { /* 14528 */ + 257, + /* VRSQRT28SSZrbkz */ + }, + { /* 14529 */ + 256, + /* VRSQRT28SSZrk */ + }, + { /* 14530 */ + 257, + /* VRSQRT28SSZrkz */ + }, + { /* 14531 */ + 305, + /* VRSQRTPSYm */ + }, + { /* 14532 */ + 408, + /* VRSQRTPSYr */ + }, + { /* 14533 */ + 30, + /* VRSQRTPSm */ + }, + { /* 14534 */ + 31, + /* VRSQRTPSr */ + }, + { /* 14535 */ + 235, + /* VRSQRTSSm */ + }, + { /* 14536 */ + 0, + /* */ + }, + { /* 14537 */ + 236, + /* VRSQRTSSr */ + }, + { /* 14538 */ + 0, + /* */ + }, + { /* 14539 */ + 206, + /* VSCALEFPDZ128rm */ + }, + { /* 14540 */ + 207, + /* VSCALEFPDZ128rmb */ + }, + { /* 14541 */ + 208, + /* VSCALEFPDZ128rmbk */ + }, + { /* 14542 */ + 209, + /* VSCALEFPDZ128rmbkz */ + }, + { /* 14543 */ + 203, + /* VSCALEFPDZ128rmk */ + }, + { /* 14544 */ + 210, + /* VSCALEFPDZ128rmkz */ + }, + { /* 14545 */ + 211, + /* VSCALEFPDZ128rr */ + }, + { /* 14546 */ + 212, + /* VSCALEFPDZ128rrk */ + }, + { /* 14547 */ + 213, + /* VSCALEFPDZ128rrkz */ + }, + { /* 14548 */ + 214, + /* VSCALEFPDZ256rm */ + }, + { /* 14549 */ + 215, + /* VSCALEFPDZ256rmb */ + }, + { /* 14550 */ + 216, + /* VSCALEFPDZ256rmbk */ + }, + { /* 14551 */ + 217, + /* VSCALEFPDZ256rmbkz */ + }, + { /* 14552 */ + 218, + /* VSCALEFPDZ256rmk */ + }, + { /* 14553 */ + 219, + /* VSCALEFPDZ256rmkz */ + }, + { /* 14554 */ + 220, + /* VSCALEFPDZ256rr */ + }, + { /* 14555 */ + 221, + /* VSCALEFPDZ256rrk */ + }, + { /* 14556 */ + 222, + /* VSCALEFPDZ256rrkz */ + }, + { /* 14557 */ + 223, + /* VSCALEFPDZrm */ + }, + { /* 14558 */ + 224, + /* VSCALEFPDZrmb */ + }, + { /* 14559 */ + 225, + /* VSCALEFPDZrmbk */ + }, + { /* 14560 */ + 226, + /* VSCALEFPDZrmbkz */ + }, + { /* 14561 */ + 227, + /* VSCALEFPDZrmk */ + }, + { /* 14562 */ + 228, + /* VSCALEFPDZrmkz */ + }, + { /* 14563 */ + 229, + /* VSCALEFPDZrr */ + }, + { /* 14564 */ + 230, + /* VSCALEFPDZrrb */ + }, + { /* 14565 */ + 231, + /* VSCALEFPDZrrbk */ + }, + { /* 14566 */ + 232, + /* VSCALEFPDZrrbkz */ + }, + { /* 14567 */ + 233, + /* VSCALEFPDZrrk */ + }, + { /* 14568 */ + 234, + /* VSCALEFPDZrrkz */ + }, + { /* 14569 */ + 206, + /* VSCALEFPSZ128rm */ + }, + { /* 14570 */ + 237, + /* VSCALEFPSZ128rmb */ + }, + { /* 14571 */ + 238, + /* VSCALEFPSZ128rmbk */ + }, + { /* 14572 */ + 239, + /* VSCALEFPSZ128rmbkz */ + }, + { /* 14573 */ + 203, + /* VSCALEFPSZ128rmk */ + }, + { /* 14574 */ + 210, + /* VSCALEFPSZ128rmkz */ + }, + { /* 14575 */ + 211, + /* VSCALEFPSZ128rr */ + }, + { /* 14576 */ + 212, + /* VSCALEFPSZ128rrk */ + }, + { /* 14577 */ + 213, + /* VSCALEFPSZ128rrkz */ + }, + { /* 14578 */ + 214, + /* VSCALEFPSZ256rm */ + }, + { /* 14579 */ + 240, + /* VSCALEFPSZ256rmb */ + }, + { /* 14580 */ + 241, + /* VSCALEFPSZ256rmbk */ + }, + { /* 14581 */ + 242, + /* VSCALEFPSZ256rmbkz */ + }, + { /* 14582 */ + 218, + /* VSCALEFPSZ256rmk */ + }, + { /* 14583 */ + 219, + /* VSCALEFPSZ256rmkz */ + }, + { /* 14584 */ + 220, + /* VSCALEFPSZ256rr */ + }, + { /* 14585 */ + 221, + /* VSCALEFPSZ256rrk */ + }, + { /* 14586 */ + 222, + /* VSCALEFPSZ256rrkz */ + }, + { /* 14587 */ + 223, + /* VSCALEFPSZrm */ + }, + { /* 14588 */ + 243, + /* VSCALEFPSZrmb */ + }, + { /* 14589 */ + 244, + /* VSCALEFPSZrmbk */ + }, + { /* 14590 */ + 245, + /* VSCALEFPSZrmbkz */ + }, + { /* 14591 */ + 227, + /* VSCALEFPSZrmk */ + }, + { /* 14592 */ + 228, + /* VSCALEFPSZrmkz */ + }, + { /* 14593 */ + 229, + /* VSCALEFPSZrr */ + }, + { /* 14594 */ + 246, + /* VSCALEFPSZrrb */ + }, + { /* 14595 */ + 247, + /* VSCALEFPSZrrbk */ + }, + { /* 14596 */ + 248, + /* VSCALEFPSZrrbkz */ + }, + { /* 14597 */ + 233, + /* VSCALEFPSZrrk */ + }, + { /* 14598 */ + 234, + /* VSCALEFPSZrrkz */ + }, + { /* 14599 */ + 207, + /* VSCALEFSDZrm */ + }, + { /* 14600 */ + 208, + /* VSCALEFSDZrmk */ + }, + { /* 14601 */ + 209, + /* VSCALEFSDZrmkz */ + }, + { /* 14602 */ + 249, + /* VSCALEFSDZrr */ + }, + { /* 14603 */ + 252, + /* VSCALEFSDZrrb_Int */ + }, + { /* 14604 */ + 253, + /* VSCALEFSDZrrb_Intk */ + }, + { /* 14605 */ + 254, + /* VSCALEFSDZrrb_Intkz */ + }, + { /* 14606 */ + 250, + /* VSCALEFSDZrrk */ + }, + { /* 14607 */ + 251, + /* VSCALEFSDZrrkz */ + }, + { /* 14608 */ + 237, + /* VSCALEFSSZrm */ + }, + { /* 14609 */ + 238, + /* VSCALEFSSZrmk */ + }, + { /* 14610 */ + 239, + /* VSCALEFSSZrmkz */ + }, + { /* 14611 */ + 255, + /* VSCALEFSSZrr */ + }, + { /* 14612 */ + 258, + /* VSCALEFSSZrrb_Int */ + }, + { /* 14613 */ + 259, + /* VSCALEFSSZrrb_Intk */ + }, + { /* 14614 */ + 260, + /* VSCALEFSSZrrb_Intkz */ + }, + { /* 14615 */ + 256, + /* VSCALEFSSZrrk */ + }, + { /* 14616 */ + 257, + /* VSCALEFSSZrrkz */ + }, + { /* 14617 */ + 895, + /* VSCATTERDPDZ128mr */ + }, + { /* 14618 */ + 896, + /* VSCATTERDPDZ256mr */ + }, + { /* 14619 */ + 897, + /* VSCATTERDPDZmr */ + }, + { /* 14620 */ + 892, + /* VSCATTERDPSZ128mr */ + }, + { /* 14621 */ + 893, + /* VSCATTERDPSZ256mr */ + }, + { /* 14622 */ + 894, + /* VSCATTERDPSZmr */ + }, + { /* 14623 */ + 581, + /* VSCATTERPF0DPDm */ + }, + { /* 14624 */ + 582, + /* VSCATTERPF0DPSm */ + }, + { /* 14625 */ + 583, + /* VSCATTERPF0QPDm */ + }, + { /* 14626 */ + 583, + /* VSCATTERPF0QPSm */ + }, + { /* 14627 */ + 581, + /* VSCATTERPF1DPDm */ + }, + { /* 14628 */ + 582, + /* VSCATTERPF1DPSm */ + }, + { /* 14629 */ + 583, + /* VSCATTERPF1QPDm */ + }, + { /* 14630 */ + 583, + /* VSCATTERPF1QPSm */ + }, + { /* 14631 */ + 895, + /* VSCATTERQPDZ128mr */ + }, + { /* 14632 */ + 900, + /* VSCATTERQPDZ256mr */ + }, + { /* 14633 */ + 901, + /* VSCATTERQPDZmr */ + }, + { /* 14634 */ + 892, + /* VSCATTERQPSZ128mr */ + }, + { /* 14635 */ + 898, + /* VSCATTERQPSZ256mr */ + }, + { /* 14636 */ + 899, + /* VSCATTERQPSZmr */ + }, + { /* 14637 */ + 270, + /* VSHUFF32X4Z256rmbi */ + }, + { /* 14638 */ + 271, + /* VSHUFF32X4Z256rmbik */ + }, + { /* 14639 */ + 272, + /* VSHUFF32X4Z256rmbikz */ + }, + { /* 14640 */ + 273, + /* VSHUFF32X4Z256rmi */ + }, + { /* 14641 */ + 274, + /* VSHUFF32X4Z256rmik */ + }, + { /* 14642 */ + 275, + /* VSHUFF32X4Z256rmikz */ + }, + { /* 14643 */ + 276, + /* VSHUFF32X4Z256rri */ + }, + { /* 14644 */ + 277, + /* VSHUFF32X4Z256rrik */ + }, + { /* 14645 */ + 278, + /* VSHUFF32X4Z256rrikz */ + }, + { /* 14646 */ + 279, + /* VSHUFF32X4Zrmbi */ + }, + { /* 14647 */ + 280, + /* VSHUFF32X4Zrmbik */ + }, + { /* 14648 */ + 281, + /* VSHUFF32X4Zrmbikz */ + }, + { /* 14649 */ + 282, + /* VSHUFF32X4Zrmi */ + }, + { /* 14650 */ + 283, + /* VSHUFF32X4Zrmik */ + }, + { /* 14651 */ + 284, + /* VSHUFF32X4Zrmikz */ + }, + { /* 14652 */ + 285, + /* VSHUFF32X4Zrri */ + }, + { /* 14653 */ + 286, + /* VSHUFF32X4Zrrik */ + }, + { /* 14654 */ + 287, + /* VSHUFF32X4Zrrikz */ + }, + { /* 14655 */ + 291, + /* VSHUFF64X2Z256rmbi */ + }, + { /* 14656 */ + 292, + /* VSHUFF64X2Z256rmbik */ + }, + { /* 14657 */ + 293, + /* VSHUFF64X2Z256rmbikz */ + }, + { /* 14658 */ + 273, + /* VSHUFF64X2Z256rmi */ + }, + { /* 14659 */ + 274, + /* VSHUFF64X2Z256rmik */ + }, + { /* 14660 */ + 275, + /* VSHUFF64X2Z256rmikz */ + }, + { /* 14661 */ + 276, + /* VSHUFF64X2Z256rri */ + }, + { /* 14662 */ + 277, + /* VSHUFF64X2Z256rrik */ + }, + { /* 14663 */ + 278, + /* VSHUFF64X2Z256rrikz */ + }, + { /* 14664 */ + 294, + /* VSHUFF64X2Zrmbi */ + }, + { /* 14665 */ + 295, + /* VSHUFF64X2Zrmbik */ + }, + { /* 14666 */ + 296, + /* VSHUFF64X2Zrmbikz */ + }, + { /* 14667 */ + 282, + /* VSHUFF64X2Zrmi */ + }, + { /* 14668 */ + 283, + /* VSHUFF64X2Zrmik */ + }, + { /* 14669 */ + 284, + /* VSHUFF64X2Zrmikz */ + }, + { /* 14670 */ + 285, + /* VSHUFF64X2Zrri */ + }, + { /* 14671 */ + 286, + /* VSHUFF64X2Zrrik */ + }, + { /* 14672 */ + 287, + /* VSHUFF64X2Zrrikz */ + }, + { /* 14673 */ + 270, + /* VSHUFI32X4Z256rmbi */ + }, + { /* 14674 */ + 271, + /* VSHUFI32X4Z256rmbik */ + }, + { /* 14675 */ + 272, + /* VSHUFI32X4Z256rmbikz */ + }, + { /* 14676 */ + 273, + /* VSHUFI32X4Z256rmi */ + }, + { /* 14677 */ + 274, + /* VSHUFI32X4Z256rmik */ + }, + { /* 14678 */ + 275, + /* VSHUFI32X4Z256rmikz */ + }, + { /* 14679 */ + 276, + /* VSHUFI32X4Z256rri */ + }, + { /* 14680 */ + 277, + /* VSHUFI32X4Z256rrik */ + }, + { /* 14681 */ + 278, + /* VSHUFI32X4Z256rrikz */ + }, + { /* 14682 */ + 279, + /* VSHUFI32X4Zrmbi */ + }, + { /* 14683 */ + 280, + /* VSHUFI32X4Zrmbik */ + }, + { /* 14684 */ + 281, + /* VSHUFI32X4Zrmbikz */ + }, + { /* 14685 */ + 282, + /* VSHUFI32X4Zrmi */ + }, + { /* 14686 */ + 283, + /* VSHUFI32X4Zrmik */ + }, + { /* 14687 */ + 284, + /* VSHUFI32X4Zrmikz */ + }, + { /* 14688 */ + 285, + /* VSHUFI32X4Zrri */ + }, + { /* 14689 */ + 286, + /* VSHUFI32X4Zrrik */ + }, + { /* 14690 */ + 287, + /* VSHUFI32X4Zrrikz */ + }, + { /* 14691 */ + 291, + /* VSHUFI64X2Z256rmbi */ + }, + { /* 14692 */ + 292, + /* VSHUFI64X2Z256rmbik */ + }, + { /* 14693 */ + 293, + /* VSHUFI64X2Z256rmbikz */ + }, + { /* 14694 */ + 273, + /* VSHUFI64X2Z256rmi */ + }, + { /* 14695 */ + 274, + /* VSHUFI64X2Z256rmik */ + }, + { /* 14696 */ + 275, + /* VSHUFI64X2Z256rmikz */ + }, + { /* 14697 */ + 276, + /* VSHUFI64X2Z256rri */ + }, + { /* 14698 */ + 277, + /* VSHUFI64X2Z256rrik */ + }, + { /* 14699 */ + 278, + /* VSHUFI64X2Z256rrikz */ + }, + { /* 14700 */ + 294, + /* VSHUFI64X2Zrmbi */ + }, + { /* 14701 */ + 295, + /* VSHUFI64X2Zrmbik */ + }, + { /* 14702 */ + 296, + /* VSHUFI64X2Zrmbikz */ + }, + { /* 14703 */ + 282, + /* VSHUFI64X2Zrmi */ + }, + { /* 14704 */ + 283, + /* VSHUFI64X2Zrmik */ + }, + { /* 14705 */ + 284, + /* VSHUFI64X2Zrmikz */ + }, + { /* 14706 */ + 285, + /* VSHUFI64X2Zrri */ + }, + { /* 14707 */ + 286, + /* VSHUFI64X2Zrrik */ + }, + { /* 14708 */ + 287, + /* VSHUFI64X2Zrrikz */ + }, + { /* 14709 */ + 297, + /* VSHUFPDYrmi */ + }, + { /* 14710 */ + 298, + /* VSHUFPDYrri */ + }, + { /* 14711 */ + 288, + /* VSHUFPDZ128rmbi */ + }, + { /* 14712 */ + 289, + /* VSHUFPDZ128rmbik */ + }, + { /* 14713 */ + 290, + /* VSHUFPDZ128rmbikz */ + }, + { /* 14714 */ + 264, + /* VSHUFPDZ128rmi */ + }, + { /* 14715 */ + 265, + /* VSHUFPDZ128rmik */ + }, + { /* 14716 */ + 266, + /* VSHUFPDZ128rmikz */ + }, + { /* 14717 */ + 267, + /* VSHUFPDZ128rri */ + }, + { /* 14718 */ + 268, + /* VSHUFPDZ128rrik */ + }, + { /* 14719 */ + 269, + /* VSHUFPDZ128rrikz */ + }, + { /* 14720 */ + 291, + /* VSHUFPDZ256rmbi */ + }, + { /* 14721 */ + 292, + /* VSHUFPDZ256rmbik */ + }, + { /* 14722 */ + 293, + /* VSHUFPDZ256rmbikz */ + }, + { /* 14723 */ + 273, + /* VSHUFPDZ256rmi */ + }, + { /* 14724 */ + 274, + /* VSHUFPDZ256rmik */ + }, + { /* 14725 */ + 275, + /* VSHUFPDZ256rmikz */ + }, + { /* 14726 */ + 276, + /* VSHUFPDZ256rri */ + }, + { /* 14727 */ + 277, + /* VSHUFPDZ256rrik */ + }, + { /* 14728 */ + 278, + /* VSHUFPDZ256rrikz */ + }, + { /* 14729 */ + 294, + /* VSHUFPDZrmbi */ + }, + { /* 14730 */ + 295, + /* VSHUFPDZrmbik */ + }, + { /* 14731 */ + 296, + /* VSHUFPDZrmbikz */ + }, + { /* 14732 */ + 282, + /* VSHUFPDZrmi */ + }, + { /* 14733 */ + 283, + /* VSHUFPDZrmik */ + }, + { /* 14734 */ + 284, + /* VSHUFPDZrmikz */ + }, + { /* 14735 */ + 285, + /* VSHUFPDZrri */ + }, + { /* 14736 */ + 286, + /* VSHUFPDZrrik */ + }, + { /* 14737 */ + 287, + /* VSHUFPDZrrikz */ + }, + { /* 14738 */ + 299, + /* VSHUFPDrmi */ + }, + { /* 14739 */ + 300, + /* VSHUFPDrri */ + }, + { /* 14740 */ + 297, + /* VSHUFPSYrmi */ + }, + { /* 14741 */ + 298, + /* VSHUFPSYrri */ + }, + { /* 14742 */ + 261, + /* VSHUFPSZ128rmbi */ + }, + { /* 14743 */ + 262, + /* VSHUFPSZ128rmbik */ + }, + { /* 14744 */ + 263, + /* VSHUFPSZ128rmbikz */ + }, + { /* 14745 */ + 264, + /* VSHUFPSZ128rmi */ + }, + { /* 14746 */ + 265, + /* VSHUFPSZ128rmik */ + }, + { /* 14747 */ + 266, + /* VSHUFPSZ128rmikz */ + }, + { /* 14748 */ + 267, + /* VSHUFPSZ128rri */ + }, + { /* 14749 */ + 268, + /* VSHUFPSZ128rrik */ + }, + { /* 14750 */ + 269, + /* VSHUFPSZ128rrikz */ + }, + { /* 14751 */ + 270, + /* VSHUFPSZ256rmbi */ + }, + { /* 14752 */ + 271, + /* VSHUFPSZ256rmbik */ + }, + { /* 14753 */ + 272, + /* VSHUFPSZ256rmbikz */ + }, + { /* 14754 */ + 273, + /* VSHUFPSZ256rmi */ + }, + { /* 14755 */ + 274, + /* VSHUFPSZ256rmik */ + }, + { /* 14756 */ + 275, + /* VSHUFPSZ256rmikz */ + }, + { /* 14757 */ + 276, + /* VSHUFPSZ256rri */ + }, + { /* 14758 */ + 277, + /* VSHUFPSZ256rrik */ + }, + { /* 14759 */ + 278, + /* VSHUFPSZ256rrikz */ + }, + { /* 14760 */ + 279, + /* VSHUFPSZrmbi */ + }, + { /* 14761 */ + 280, + /* VSHUFPSZrmbik */ + }, + { /* 14762 */ + 281, + /* VSHUFPSZrmbikz */ + }, + { /* 14763 */ + 282, + /* VSHUFPSZrmi */ + }, + { /* 14764 */ + 283, + /* VSHUFPSZrmik */ + }, + { /* 14765 */ + 284, + /* VSHUFPSZrmikz */ + }, + { /* 14766 */ + 285, + /* VSHUFPSZrri */ + }, + { /* 14767 */ + 286, + /* VSHUFPSZrrik */ + }, + { /* 14768 */ + 287, + /* VSHUFPSZrrikz */ + }, + { /* 14769 */ + 299, + /* VSHUFPSrmi */ + }, + { /* 14770 */ + 300, + /* VSHUFPSrri */ + }, + { /* 14771 */ + 305, + /* VSQRTPDYm */ + }, + { /* 14772 */ + 408, + /* VSQRTPDYr */ + }, + { /* 14773 */ + 409, + /* VSQRTPDZ128m */ + }, + { /* 14774 */ + 327, + /* VSQRTPDZ128mb */ + }, + { /* 14775 */ + 328, + /* VSQRTPDZ128mbk */ + }, + { /* 14776 */ + 329, + /* VSQRTPDZ128mbkz */ + }, + { /* 14777 */ + 410, + /* VSQRTPDZ128mk */ + }, + { /* 14778 */ + 411, + /* VSQRTPDZ128mkz */ + }, + { /* 14779 */ + 330, + /* VSQRTPDZ128r */ + }, + { /* 14780 */ + 331, + /* VSQRTPDZ128rk */ + }, + { /* 14781 */ + 332, + /* VSQRTPDZ128rkz */ + }, + { /* 14782 */ + 412, + /* VSQRTPDZ256m */ + }, + { /* 14783 */ + 306, + /* VSQRTPDZ256mb */ + }, + { /* 14784 */ + 307, + /* VSQRTPDZ256mbk */ + }, + { /* 14785 */ + 308, + /* VSQRTPDZ256mbkz */ + }, + { /* 14786 */ + 413, + /* VSQRTPDZ256mk */ + }, + { /* 14787 */ + 414, + /* VSQRTPDZ256mkz */ + }, + { /* 14788 */ + 415, + /* VSQRTPDZ256r */ + }, + { /* 14789 */ + 416, + /* VSQRTPDZ256rk */ + }, + { /* 14790 */ + 417, + /* VSQRTPDZ256rkz */ + }, + { /* 14791 */ + 418, + /* VSQRTPDZm */ + }, + { /* 14792 */ + 312, + /* VSQRTPDZmb */ + }, + { /* 14793 */ + 313, + /* VSQRTPDZmbk */ + }, + { /* 14794 */ + 314, + /* VSQRTPDZmbkz */ + }, + { /* 14795 */ + 419, + /* VSQRTPDZmk */ + }, + { /* 14796 */ + 420, + /* VSQRTPDZmkz */ + }, + { /* 14797 */ + 421, + /* VSQRTPDZr */ + }, + { /* 14798 */ + 443, + /* VSQRTPDZrb */ + }, + { /* 14799 */ + 444, + /* VSQRTPDZrbk */ + }, + { /* 14800 */ + 445, + /* VSQRTPDZrbkz */ + }, + { /* 14801 */ + 425, + /* VSQRTPDZrk */ + }, + { /* 14802 */ + 426, + /* VSQRTPDZrkz */ + }, + { /* 14803 */ + 30, + /* VSQRTPDm */ + }, + { /* 14804 */ + 31, + /* VSQRTPDr */ + }, + { /* 14805 */ + 305, + /* VSQRTPSYm */ + }, + { /* 14806 */ + 408, + /* VSQRTPSYr */ + }, + { /* 14807 */ + 409, + /* VSQRTPSZ128m */ + }, + { /* 14808 */ + 334, + /* VSQRTPSZ128mb */ + }, + { /* 14809 */ + 335, + /* VSQRTPSZ128mbk */ + }, + { /* 14810 */ + 336, + /* VSQRTPSZ128mbkz */ + }, + { /* 14811 */ + 410, + /* VSQRTPSZ128mk */ + }, + { /* 14812 */ + 411, + /* VSQRTPSZ128mkz */ + }, + { /* 14813 */ + 330, + /* VSQRTPSZ128r */ + }, + { /* 14814 */ + 331, + /* VSQRTPSZ128rk */ + }, + { /* 14815 */ + 332, + /* VSQRTPSZ128rkz */ + }, + { /* 14816 */ + 412, + /* VSQRTPSZ256m */ + }, + { /* 14817 */ + 337, + /* VSQRTPSZ256mb */ + }, + { /* 14818 */ + 338, + /* VSQRTPSZ256mbk */ + }, + { /* 14819 */ + 339, + /* VSQRTPSZ256mbkz */ + }, + { /* 14820 */ + 413, + /* VSQRTPSZ256mk */ + }, + { /* 14821 */ + 414, + /* VSQRTPSZ256mkz */ + }, + { /* 14822 */ + 415, + /* VSQRTPSZ256r */ + }, + { /* 14823 */ + 416, + /* VSQRTPSZ256rk */ + }, + { /* 14824 */ + 417, + /* VSQRTPSZ256rkz */ + }, + { /* 14825 */ + 418, + /* VSQRTPSZm */ + }, + { /* 14826 */ + 340, + /* VSQRTPSZmb */ + }, + { /* 14827 */ + 341, + /* VSQRTPSZmbk */ + }, + { /* 14828 */ + 342, + /* VSQRTPSZmbkz */ + }, + { /* 14829 */ + 419, + /* VSQRTPSZmk */ + }, + { /* 14830 */ + 420, + /* VSQRTPSZmkz */ + }, + { /* 14831 */ + 421, + /* VSQRTPSZr */ + }, + { /* 14832 */ + 422, + /* VSQRTPSZrb */ + }, + { /* 14833 */ + 423, + /* VSQRTPSZrbk */ + }, + { /* 14834 */ + 424, + /* VSQRTPSZrbkz */ + }, + { /* 14835 */ + 425, + /* VSQRTPSZrk */ + }, + { /* 14836 */ + 426, + /* VSQRTPSZrkz */ + }, + { /* 14837 */ + 30, + /* VSQRTPSm */ + }, + { /* 14838 */ + 31, + /* VSQRTPSr */ + }, + { /* 14839 */ + 0, + /* */ + }, + { /* 14840 */ + 207, + /* VSQRTSDZm_Int */ + }, + { /* 14841 */ + 208, + /* VSQRTSDZm_Intk */ + }, + { /* 14842 */ + 209, + /* VSQRTSDZm_Intkz */ + }, + { /* 14843 */ + 0, + /* */ + }, + { /* 14844 */ + 249, + /* VSQRTSDZr_Int */ + }, + { /* 14845 */ + 250, + /* VSQRTSDZr_Intk */ + }, + { /* 14846 */ + 251, + /* VSQRTSDZr_Intkz */ + }, + { /* 14847 */ + 252, + /* VSQRTSDZrb_Int */ + }, + { /* 14848 */ + 253, + /* VSQRTSDZrb_Intk */ + }, + { /* 14849 */ + 254, + /* VSQRTSDZrb_Intkz */ + }, + { /* 14850 */ + 235, + /* VSQRTSDm */ + }, + { /* 14851 */ + 0, + /* */ + }, + { /* 14852 */ + 236, + /* VSQRTSDr */ + }, + { /* 14853 */ + 0, + /* */ + }, + { /* 14854 */ + 0, + /* */ + }, + { /* 14855 */ + 237, + /* VSQRTSSZm_Int */ + }, + { /* 14856 */ + 238, + /* VSQRTSSZm_Intk */ + }, + { /* 14857 */ + 239, + /* VSQRTSSZm_Intkz */ + }, + { /* 14858 */ + 0, + /* */ + }, + { /* 14859 */ + 255, + /* VSQRTSSZr_Int */ + }, + { /* 14860 */ + 256, + /* VSQRTSSZr_Intk */ + }, + { /* 14861 */ + 257, + /* VSQRTSSZr_Intkz */ + }, + { /* 14862 */ + 258, + /* VSQRTSSZrb_Int */ + }, + { /* 14863 */ + 259, + /* VSQRTSSZrb_Intk */ + }, + { /* 14864 */ + 260, + /* VSQRTSSZrb_Intkz */ + }, + { /* 14865 */ + 235, + /* VSQRTSSm */ + }, + { /* 14866 */ + 0, + /* */ + }, + { /* 14867 */ + 236, + /* VSQRTSSr */ + }, + { /* 14868 */ + 0, + /* */ + }, + { /* 14869 */ + 28, + /* VSTMXCSR */ + }, + { /* 14870 */ + 204, + /* VSUBPDYrm */ + }, + { /* 14871 */ + 205, + /* VSUBPDYrr */ + }, + { /* 14872 */ + 206, + /* VSUBPDZ128rm */ + }, + { /* 14873 */ + 207, + /* VSUBPDZ128rmb */ + }, + { /* 14874 */ + 208, + /* VSUBPDZ128rmbk */ + }, + { /* 14875 */ + 209, + /* VSUBPDZ128rmbkz */ + }, + { /* 14876 */ + 203, + /* VSUBPDZ128rmk */ + }, + { /* 14877 */ + 210, + /* VSUBPDZ128rmkz */ + }, + { /* 14878 */ + 211, + /* VSUBPDZ128rr */ + }, + { /* 14879 */ + 212, + /* VSUBPDZ128rrk */ + }, + { /* 14880 */ + 213, + /* VSUBPDZ128rrkz */ + }, + { /* 14881 */ + 214, + /* VSUBPDZ256rm */ + }, + { /* 14882 */ + 215, + /* VSUBPDZ256rmb */ + }, + { /* 14883 */ + 216, + /* VSUBPDZ256rmbk */ + }, + { /* 14884 */ + 217, + /* VSUBPDZ256rmbkz */ + }, + { /* 14885 */ + 218, + /* VSUBPDZ256rmk */ + }, + { /* 14886 */ + 219, + /* VSUBPDZ256rmkz */ + }, + { /* 14887 */ + 220, + /* VSUBPDZ256rr */ + }, + { /* 14888 */ + 221, + /* VSUBPDZ256rrk */ + }, + { /* 14889 */ + 222, + /* VSUBPDZ256rrkz */ + }, + { /* 14890 */ + 223, + /* VSUBPDZrm */ + }, + { /* 14891 */ + 224, + /* VSUBPDZrmb */ + }, + { /* 14892 */ + 225, + /* VSUBPDZrmbk */ + }, + { /* 14893 */ + 226, + /* VSUBPDZrmbkz */ + }, + { /* 14894 */ + 227, + /* VSUBPDZrmk */ + }, + { /* 14895 */ + 228, + /* VSUBPDZrmkz */ + }, + { /* 14896 */ + 229, + /* VSUBPDZrr */ + }, + { /* 14897 */ + 230, + /* VSUBPDZrrb */ + }, + { /* 14898 */ + 231, + /* VSUBPDZrrbk */ + }, + { /* 14899 */ + 232, + /* VSUBPDZrrbkz */ + }, + { /* 14900 */ + 233, + /* VSUBPDZrrk */ + }, + { /* 14901 */ + 234, + /* VSUBPDZrrkz */ + }, + { /* 14902 */ + 235, + /* VSUBPDrm */ + }, + { /* 14903 */ + 236, + /* VSUBPDrr */ + }, + { /* 14904 */ + 204, + /* VSUBPSYrm */ + }, + { /* 14905 */ + 205, + /* VSUBPSYrr */ + }, + { /* 14906 */ + 206, + /* VSUBPSZ128rm */ + }, + { /* 14907 */ + 237, + /* VSUBPSZ128rmb */ + }, + { /* 14908 */ + 238, + /* VSUBPSZ128rmbk */ + }, + { /* 14909 */ + 239, + /* VSUBPSZ128rmbkz */ + }, + { /* 14910 */ + 203, + /* VSUBPSZ128rmk */ + }, + { /* 14911 */ + 210, + /* VSUBPSZ128rmkz */ + }, + { /* 14912 */ + 211, + /* VSUBPSZ128rr */ + }, + { /* 14913 */ + 212, + /* VSUBPSZ128rrk */ + }, + { /* 14914 */ + 213, + /* VSUBPSZ128rrkz */ + }, + { /* 14915 */ + 214, + /* VSUBPSZ256rm */ + }, + { /* 14916 */ + 240, + /* VSUBPSZ256rmb */ + }, + { /* 14917 */ + 241, + /* VSUBPSZ256rmbk */ + }, + { /* 14918 */ + 242, + /* VSUBPSZ256rmbkz */ + }, + { /* 14919 */ + 218, + /* VSUBPSZ256rmk */ + }, + { /* 14920 */ + 219, + /* VSUBPSZ256rmkz */ + }, + { /* 14921 */ + 220, + /* VSUBPSZ256rr */ + }, + { /* 14922 */ + 221, + /* VSUBPSZ256rrk */ + }, + { /* 14923 */ + 222, + /* VSUBPSZ256rrkz */ + }, + { /* 14924 */ + 223, + /* VSUBPSZrm */ + }, + { /* 14925 */ + 243, + /* VSUBPSZrmb */ + }, + { /* 14926 */ + 244, + /* VSUBPSZrmbk */ + }, + { /* 14927 */ + 245, + /* VSUBPSZrmbkz */ + }, + { /* 14928 */ + 227, + /* VSUBPSZrmk */ + }, + { /* 14929 */ + 228, + /* VSUBPSZrmkz */ + }, + { /* 14930 */ + 229, + /* VSUBPSZrr */ + }, + { /* 14931 */ + 246, + /* VSUBPSZrrb */ + }, + { /* 14932 */ + 247, + /* VSUBPSZrrbk */ + }, + { /* 14933 */ + 248, + /* VSUBPSZrrbkz */ + }, + { /* 14934 */ + 233, + /* VSUBPSZrrk */ + }, + { /* 14935 */ + 234, + /* VSUBPSZrrkz */ + }, + { /* 14936 */ + 235, + /* VSUBPSrm */ + }, + { /* 14937 */ + 236, + /* VSUBPSrr */ + }, + { /* 14938 */ + 0, + /* */ + }, + { /* 14939 */ + 207, + /* VSUBSDZrm_Int */ + }, + { /* 14940 */ + 208, + /* VSUBSDZrm_Intk */ + }, + { /* 14941 */ + 209, + /* VSUBSDZrm_Intkz */ + }, + { /* 14942 */ + 0, + /* */ + }, + { /* 14943 */ + 249, + /* VSUBSDZrr_Int */ + }, + { /* 14944 */ + 250, + /* VSUBSDZrr_Intk */ + }, + { /* 14945 */ + 251, + /* VSUBSDZrr_Intkz */ + }, + { /* 14946 */ + 252, + /* VSUBSDZrrb_Int */ + }, + { /* 14947 */ + 253, + /* VSUBSDZrrb_Intk */ + }, + { /* 14948 */ + 254, + /* VSUBSDZrrb_Intkz */ + }, + { /* 14949 */ + 235, + /* VSUBSDrm */ + }, + { /* 14950 */ + 0, + /* */ + }, + { /* 14951 */ + 236, + /* VSUBSDrr */ + }, + { /* 14952 */ + 0, + /* */ + }, + { /* 14953 */ + 0, + /* */ + }, + { /* 14954 */ + 237, + /* VSUBSSZrm_Int */ + }, + { /* 14955 */ + 238, + /* VSUBSSZrm_Intk */ + }, + { /* 14956 */ + 239, + /* VSUBSSZrm_Intkz */ + }, + { /* 14957 */ + 0, + /* */ + }, + { /* 14958 */ + 255, + /* VSUBSSZrr_Int */ + }, + { /* 14959 */ + 256, + /* VSUBSSZrr_Intk */ + }, + { /* 14960 */ + 257, + /* VSUBSSZrr_Intkz */ + }, + { /* 14961 */ + 258, + /* VSUBSSZrrb_Int */ + }, + { /* 14962 */ + 259, + /* VSUBSSZrrb_Intk */ + }, + { /* 14963 */ + 260, + /* VSUBSSZrrb_Intkz */ + }, + { /* 14964 */ + 235, + /* VSUBSSrm */ + }, + { /* 14965 */ + 0, + /* */ + }, + { /* 14966 */ + 236, + /* VSUBSSrr */ + }, + { /* 14967 */ + 0, + /* */ + }, + { /* 14968 */ + 305, + /* VTESTPDYrm */ + }, + { /* 14969 */ + 408, + /* VTESTPDYrr */ + }, + { /* 14970 */ + 30, + /* VTESTPDrm */ + }, + { /* 14971 */ + 31, + /* VTESTPDrr */ + }, + { /* 14972 */ + 305, + /* VTESTPSYrm */ + }, + { /* 14973 */ + 408, + /* VTESTPSYrr */ + }, + { /* 14974 */ + 30, + /* VTESTPSrm */ + }, + { /* 14975 */ + 31, + /* VTESTPSrr */ + }, + { /* 14976 */ + 327, + /* VUCOMISDZrm */ + }, + { /* 14977 */ + 0, + /* */ + }, + { /* 14978 */ + 377, + /* VUCOMISDZrr */ + }, + { /* 14979 */ + 0, + /* */ + }, + { /* 14980 */ + 377, + /* VUCOMISDZrrb */ + }, + { /* 14981 */ + 30, + /* VUCOMISDrm */ + }, + { /* 14982 */ + 0, + /* */ + }, + { /* 14983 */ + 31, + /* VUCOMISDrr */ + }, + { /* 14984 */ + 0, + /* */ + }, + { /* 14985 */ + 334, + /* VUCOMISSZrm */ + }, + { /* 14986 */ + 0, + /* */ + }, + { /* 14987 */ + 378, + /* VUCOMISSZrr */ + }, + { /* 14988 */ + 0, + /* */ + }, + { /* 14989 */ + 378, + /* VUCOMISSZrrb */ + }, + { /* 14990 */ + 30, + /* VUCOMISSrm */ + }, + { /* 14991 */ + 0, + /* */ + }, + { /* 14992 */ + 31, + /* VUCOMISSrr */ + }, + { /* 14993 */ + 0, + /* */ + }, + { /* 14994 */ + 204, + /* VUNPCKHPDYrm */ + }, + { /* 14995 */ + 205, + /* VUNPCKHPDYrr */ + }, + { /* 14996 */ + 206, + /* VUNPCKHPDZ128rm */ + }, + { /* 14997 */ + 207, + /* VUNPCKHPDZ128rmb */ + }, + { /* 14998 */ + 208, + /* VUNPCKHPDZ128rmbk */ + }, + { /* 14999 */ + 209, + /* VUNPCKHPDZ128rmbkz */ + }, + { /* 15000 */ + 203, + /* VUNPCKHPDZ128rmk */ + }, + { /* 15001 */ + 210, + /* VUNPCKHPDZ128rmkz */ + }, + { /* 15002 */ + 211, + /* VUNPCKHPDZ128rr */ + }, + { /* 15003 */ + 212, + /* VUNPCKHPDZ128rrk */ + }, + { /* 15004 */ + 213, + /* VUNPCKHPDZ128rrkz */ + }, + { /* 15005 */ + 214, + /* VUNPCKHPDZ256rm */ + }, + { /* 15006 */ + 215, + /* VUNPCKHPDZ256rmb */ + }, + { /* 15007 */ + 216, + /* VUNPCKHPDZ256rmbk */ + }, + { /* 15008 */ + 217, + /* VUNPCKHPDZ256rmbkz */ + }, + { /* 15009 */ + 218, + /* VUNPCKHPDZ256rmk */ + }, + { /* 15010 */ + 219, + /* VUNPCKHPDZ256rmkz */ + }, + { /* 15011 */ + 220, + /* VUNPCKHPDZ256rr */ + }, + { /* 15012 */ + 221, + /* VUNPCKHPDZ256rrk */ + }, + { /* 15013 */ + 222, + /* VUNPCKHPDZ256rrkz */ + }, + { /* 15014 */ + 223, + /* VUNPCKHPDZrm */ + }, + { /* 15015 */ + 224, + /* VUNPCKHPDZrmb */ + }, + { /* 15016 */ + 225, + /* VUNPCKHPDZrmbk */ + }, + { /* 15017 */ + 226, + /* VUNPCKHPDZrmbkz */ + }, + { /* 15018 */ + 227, + /* VUNPCKHPDZrmk */ + }, + { /* 15019 */ + 228, + /* VUNPCKHPDZrmkz */ + }, + { /* 15020 */ + 229, + /* VUNPCKHPDZrr */ + }, + { /* 15021 */ + 233, + /* VUNPCKHPDZrrk */ + }, + { /* 15022 */ + 234, + /* VUNPCKHPDZrrkz */ + }, + { /* 15023 */ + 235, + /* VUNPCKHPDrm */ + }, + { /* 15024 */ + 236, + /* VUNPCKHPDrr */ + }, + { /* 15025 */ + 204, + /* VUNPCKHPSYrm */ + }, + { /* 15026 */ + 205, + /* VUNPCKHPSYrr */ + }, + { /* 15027 */ + 206, + /* VUNPCKHPSZ128rm */ + }, + { /* 15028 */ + 237, + /* VUNPCKHPSZ128rmb */ + }, + { /* 15029 */ + 238, + /* VUNPCKHPSZ128rmbk */ + }, + { /* 15030 */ + 239, + /* VUNPCKHPSZ128rmbkz */ + }, + { /* 15031 */ + 203, + /* VUNPCKHPSZ128rmk */ + }, + { /* 15032 */ + 210, + /* VUNPCKHPSZ128rmkz */ + }, + { /* 15033 */ + 211, + /* VUNPCKHPSZ128rr */ + }, + { /* 15034 */ + 212, + /* VUNPCKHPSZ128rrk */ + }, + { /* 15035 */ + 213, + /* VUNPCKHPSZ128rrkz */ + }, + { /* 15036 */ + 214, + /* VUNPCKHPSZ256rm */ + }, + { /* 15037 */ + 240, + /* VUNPCKHPSZ256rmb */ + }, + { /* 15038 */ + 241, + /* VUNPCKHPSZ256rmbk */ + }, + { /* 15039 */ + 242, + /* VUNPCKHPSZ256rmbkz */ + }, + { /* 15040 */ + 218, + /* VUNPCKHPSZ256rmk */ + }, + { /* 15041 */ + 219, + /* VUNPCKHPSZ256rmkz */ + }, + { /* 15042 */ + 220, + /* VUNPCKHPSZ256rr */ + }, + { /* 15043 */ + 221, + /* VUNPCKHPSZ256rrk */ + }, + { /* 15044 */ + 222, + /* VUNPCKHPSZ256rrkz */ + }, + { /* 15045 */ + 223, + /* VUNPCKHPSZrm */ + }, + { /* 15046 */ + 243, + /* VUNPCKHPSZrmb */ + }, + { /* 15047 */ + 244, + /* VUNPCKHPSZrmbk */ + }, + { /* 15048 */ + 245, + /* VUNPCKHPSZrmbkz */ + }, + { /* 15049 */ + 227, + /* VUNPCKHPSZrmk */ + }, + { /* 15050 */ + 228, + /* VUNPCKHPSZrmkz */ + }, + { /* 15051 */ + 229, + /* VUNPCKHPSZrr */ + }, + { /* 15052 */ + 233, + /* VUNPCKHPSZrrk */ + }, + { /* 15053 */ + 234, + /* VUNPCKHPSZrrkz */ + }, + { /* 15054 */ + 235, + /* VUNPCKHPSrm */ + }, + { /* 15055 */ + 236, + /* VUNPCKHPSrr */ + }, + { /* 15056 */ + 204, + /* VUNPCKLPDYrm */ + }, + { /* 15057 */ + 205, + /* VUNPCKLPDYrr */ + }, + { /* 15058 */ + 206, + /* VUNPCKLPDZ128rm */ + }, + { /* 15059 */ + 207, + /* VUNPCKLPDZ128rmb */ + }, + { /* 15060 */ + 208, + /* VUNPCKLPDZ128rmbk */ + }, + { /* 15061 */ + 209, + /* VUNPCKLPDZ128rmbkz */ + }, + { /* 15062 */ + 203, + /* VUNPCKLPDZ128rmk */ + }, + { /* 15063 */ + 210, + /* VUNPCKLPDZ128rmkz */ + }, + { /* 15064 */ + 211, + /* VUNPCKLPDZ128rr */ + }, + { /* 15065 */ + 212, + /* VUNPCKLPDZ128rrk */ + }, + { /* 15066 */ + 213, + /* VUNPCKLPDZ128rrkz */ + }, + { /* 15067 */ + 214, + /* VUNPCKLPDZ256rm */ + }, + { /* 15068 */ + 215, + /* VUNPCKLPDZ256rmb */ + }, + { /* 15069 */ + 216, + /* VUNPCKLPDZ256rmbk */ + }, + { /* 15070 */ + 217, + /* VUNPCKLPDZ256rmbkz */ + }, + { /* 15071 */ + 218, + /* VUNPCKLPDZ256rmk */ + }, + { /* 15072 */ + 219, + /* VUNPCKLPDZ256rmkz */ + }, + { /* 15073 */ + 220, + /* VUNPCKLPDZ256rr */ + }, + { /* 15074 */ + 221, + /* VUNPCKLPDZ256rrk */ + }, + { /* 15075 */ + 222, + /* VUNPCKLPDZ256rrkz */ + }, + { /* 15076 */ + 223, + /* VUNPCKLPDZrm */ + }, + { /* 15077 */ + 224, + /* VUNPCKLPDZrmb */ + }, + { /* 15078 */ + 225, + /* VUNPCKLPDZrmbk */ + }, + { /* 15079 */ + 226, + /* VUNPCKLPDZrmbkz */ + }, + { /* 15080 */ + 227, + /* VUNPCKLPDZrmk */ + }, + { /* 15081 */ + 228, + /* VUNPCKLPDZrmkz */ + }, + { /* 15082 */ + 229, + /* VUNPCKLPDZrr */ + }, + { /* 15083 */ + 233, + /* VUNPCKLPDZrrk */ + }, + { /* 15084 */ + 234, + /* VUNPCKLPDZrrkz */ + }, + { /* 15085 */ + 235, + /* VUNPCKLPDrm */ + }, + { /* 15086 */ + 236, + /* VUNPCKLPDrr */ + }, + { /* 15087 */ + 204, + /* VUNPCKLPSYrm */ + }, + { /* 15088 */ + 205, + /* VUNPCKLPSYrr */ + }, + { /* 15089 */ + 206, + /* VUNPCKLPSZ128rm */ + }, + { /* 15090 */ + 237, + /* VUNPCKLPSZ128rmb */ + }, + { /* 15091 */ + 238, + /* VUNPCKLPSZ128rmbk */ + }, + { /* 15092 */ + 239, + /* VUNPCKLPSZ128rmbkz */ + }, + { /* 15093 */ + 203, + /* VUNPCKLPSZ128rmk */ + }, + { /* 15094 */ + 210, + /* VUNPCKLPSZ128rmkz */ + }, + { /* 15095 */ + 211, + /* VUNPCKLPSZ128rr */ + }, + { /* 15096 */ + 212, + /* VUNPCKLPSZ128rrk */ + }, + { /* 15097 */ + 213, + /* VUNPCKLPSZ128rrkz */ + }, + { /* 15098 */ + 214, + /* VUNPCKLPSZ256rm */ + }, + { /* 15099 */ + 240, + /* VUNPCKLPSZ256rmb */ + }, + { /* 15100 */ + 241, + /* VUNPCKLPSZ256rmbk */ + }, + { /* 15101 */ + 242, + /* VUNPCKLPSZ256rmbkz */ + }, + { /* 15102 */ + 218, + /* VUNPCKLPSZ256rmk */ + }, + { /* 15103 */ + 219, + /* VUNPCKLPSZ256rmkz */ + }, + { /* 15104 */ + 220, + /* VUNPCKLPSZ256rr */ + }, + { /* 15105 */ + 221, + /* VUNPCKLPSZ256rrk */ + }, + { /* 15106 */ + 222, + /* VUNPCKLPSZ256rrkz */ + }, + { /* 15107 */ + 223, + /* VUNPCKLPSZrm */ + }, + { /* 15108 */ + 243, + /* VUNPCKLPSZrmb */ + }, + { /* 15109 */ + 244, + /* VUNPCKLPSZrmbk */ + }, + { /* 15110 */ + 245, + /* VUNPCKLPSZrmbkz */ + }, + { /* 15111 */ + 227, + /* VUNPCKLPSZrmk */ + }, + { /* 15112 */ + 228, + /* VUNPCKLPSZrmkz */ + }, + { /* 15113 */ + 229, + /* VUNPCKLPSZrr */ + }, + { /* 15114 */ + 233, + /* VUNPCKLPSZrrk */ + }, + { /* 15115 */ + 234, + /* VUNPCKLPSZrrkz */ + }, + { /* 15116 */ + 235, + /* VUNPCKLPSrm */ + }, + { /* 15117 */ + 236, + /* VUNPCKLPSrr */ + }, + { /* 15118 */ + 204, + /* VXORPDYrm */ + }, + { /* 15119 */ + 205, + /* VXORPDYrr */ + }, + { /* 15120 */ + 206, + /* VXORPDZ128rm */ + }, + { /* 15121 */ + 207, + /* VXORPDZ128rmb */ + }, + { /* 15122 */ + 208, + /* VXORPDZ128rmbk */ + }, + { /* 15123 */ + 209, + /* VXORPDZ128rmbkz */ + }, + { /* 15124 */ + 203, + /* VXORPDZ128rmk */ + }, + { /* 15125 */ + 210, + /* VXORPDZ128rmkz */ + }, + { /* 15126 */ + 211, + /* VXORPDZ128rr */ + }, + { /* 15127 */ + 212, + /* VXORPDZ128rrk */ + }, + { /* 15128 */ + 213, + /* VXORPDZ128rrkz */ + }, + { /* 15129 */ + 214, + /* VXORPDZ256rm */ + }, + { /* 15130 */ + 215, + /* VXORPDZ256rmb */ + }, + { /* 15131 */ + 216, + /* VXORPDZ256rmbk */ + }, + { /* 15132 */ + 217, + /* VXORPDZ256rmbkz */ + }, + { /* 15133 */ + 218, + /* VXORPDZ256rmk */ + }, + { /* 15134 */ + 219, + /* VXORPDZ256rmkz */ + }, + { /* 15135 */ + 220, + /* VXORPDZ256rr */ + }, + { /* 15136 */ + 221, + /* VXORPDZ256rrk */ + }, + { /* 15137 */ + 222, + /* VXORPDZ256rrkz */ + }, + { /* 15138 */ + 223, + /* VXORPDZrm */ + }, + { /* 15139 */ + 224, + /* VXORPDZrmb */ + }, + { /* 15140 */ + 225, + /* VXORPDZrmbk */ + }, + { /* 15141 */ + 226, + /* VXORPDZrmbkz */ + }, + { /* 15142 */ + 227, + /* VXORPDZrmk */ + }, + { /* 15143 */ + 228, + /* VXORPDZrmkz */ + }, + { /* 15144 */ + 229, + /* VXORPDZrr */ + }, + { /* 15145 */ + 233, + /* VXORPDZrrk */ + }, + { /* 15146 */ + 234, + /* VXORPDZrrkz */ + }, + { /* 15147 */ + 235, + /* VXORPDrm */ + }, + { /* 15148 */ + 236, + /* VXORPDrr */ + }, + { /* 15149 */ + 204, + /* VXORPSYrm */ + }, + { /* 15150 */ + 205, + /* VXORPSYrr */ + }, + { /* 15151 */ + 206, + /* VXORPSZ128rm */ + }, + { /* 15152 */ + 237, + /* VXORPSZ128rmb */ + }, + { /* 15153 */ + 238, + /* VXORPSZ128rmbk */ + }, + { /* 15154 */ + 239, + /* VXORPSZ128rmbkz */ + }, + { /* 15155 */ + 203, + /* VXORPSZ128rmk */ + }, + { /* 15156 */ + 210, + /* VXORPSZ128rmkz */ + }, + { /* 15157 */ + 211, + /* VXORPSZ128rr */ + }, + { /* 15158 */ + 212, + /* VXORPSZ128rrk */ + }, + { /* 15159 */ + 213, + /* VXORPSZ128rrkz */ + }, + { /* 15160 */ + 214, + /* VXORPSZ256rm */ + }, + { /* 15161 */ + 240, + /* VXORPSZ256rmb */ + }, + { /* 15162 */ + 241, + /* VXORPSZ256rmbk */ + }, + { /* 15163 */ + 242, + /* VXORPSZ256rmbkz */ + }, + { /* 15164 */ + 218, + /* VXORPSZ256rmk */ + }, + { /* 15165 */ + 219, + /* VXORPSZ256rmkz */ + }, + { /* 15166 */ + 220, + /* VXORPSZ256rr */ + }, + { /* 15167 */ + 221, + /* VXORPSZ256rrk */ + }, + { /* 15168 */ + 222, + /* VXORPSZ256rrkz */ + }, + { /* 15169 */ + 223, + /* VXORPSZrm */ + }, + { /* 15170 */ + 243, + /* VXORPSZrmb */ + }, + { /* 15171 */ + 244, + /* VXORPSZrmbk */ + }, + { /* 15172 */ + 245, + /* VXORPSZrmbkz */ + }, + { /* 15173 */ + 227, + /* VXORPSZrmk */ + }, + { /* 15174 */ + 228, + /* VXORPSZrmkz */ + }, + { /* 15175 */ + 229, + /* VXORPSZrr */ + }, + { /* 15176 */ + 233, + /* VXORPSZrrk */ + }, + { /* 15177 */ + 234, + /* VXORPSZrrkz */ + }, + { /* 15178 */ + 235, + /* VXORPSrm */ + }, + { /* 15179 */ + 236, + /* VXORPSrr */ + }, + { /* 15180 */ + 0, + /* VZEROALL */ + }, + { /* 15181 */ + 0, + /* VZEROUPPER */ + }, + { /* 15182 */ + 0, + /* WAIT */ + }, + { /* 15183 */ + 0, + /* WBINVD */ + }, + { /* 15184 */ + 0, + /* WBNOINVD */ + }, + { /* 15185 */ + 108, + /* WRFSBASE */ + }, + { /* 15186 */ + 72, + /* WRFSBASE64 */ + }, + { /* 15187 */ + 108, + /* WRGSBASE */ + }, + { /* 15188 */ + 72, + /* WRGSBASE64 */ + }, + { /* 15189 */ + 0, + /* WRMSR */ + }, + { /* 15190 */ + 0, + /* WRPKRUr */ + }, + { /* 15191 */ + 172, + /* WRSSD */ + }, + { /* 15192 */ + 13, + /* WRSSQ */ + }, + { /* 15193 */ + 172, + /* WRUSSD */ + }, + { /* 15194 */ + 13, + /* WRUSSQ */ + }, + { /* 15195 */ + 1, + /* XABORT */ + }, + { /* 15196 */ + 0, + /* */ + }, + { /* 15197 */ + 8, + /* XADD16rm */ + }, + { /* 15198 */ + 920, + /* XADD16rr */ + }, + { /* 15199 */ + 8, + /* XADD32rm */ + }, + { /* 15200 */ + 920, + /* XADD32rr */ + }, + { /* 15201 */ + 16, + /* XADD64rm */ + }, + { /* 15202 */ + 921, + /* XADD64rr */ + }, + { /* 15203 */ + 21, + /* XADD8rm */ + }, + { /* 15204 */ + 922, + /* XADD8rr */ + }, + { /* 15205 */ + 112, + /* XBEGIN_2 */ + }, + { /* 15206 */ + 112, + /* XBEGIN_4 */ + }, + { /* 15207 */ + 64, + /* XCHG16ar */ + }, + { /* 15208 */ + 8, + /* XCHG16rm */ + }, + { /* 15209 */ + 923, + /* XCHG16rr */ + }, + { /* 15210 */ + 64, + /* XCHG32ar */ + }, + { /* 15211 */ + 8, + /* XCHG32rm */ + }, + { /* 15212 */ + 923, + /* XCHG32rr */ + }, + { /* 15213 */ + 65, + /* XCHG64ar */ + }, + { /* 15214 */ + 16, + /* XCHG64rm */ + }, + { /* 15215 */ + 924, + /* XCHG64rr */ + }, + { /* 15216 */ + 21, + /* XCHG8rm */ + }, + { /* 15217 */ + 925, + /* XCHG8rr */ + }, + { /* 15218 */ + 29, + /* XCH_F */ + }, + { /* 15219 */ + 0, + /* XCRYPTCBC */ + }, + { /* 15220 */ + 0, + /* XCRYPTCFB */ + }, + { /* 15221 */ + 0, + /* XCRYPTCTR */ + }, + { /* 15222 */ + 0, + /* XCRYPTECB */ + }, + { /* 15223 */ + 0, + /* XCRYPTOFB */ + }, + { /* 15224 */ + 0, + /* XEND */ + }, + { /* 15225 */ + 0, + /* XGETBV */ + }, + { /* 15226 */ + 0, + /* XLAT */ + }, + { /* 15227 */ + 2, + /* XOR16i16 */ + }, + { /* 15228 */ + 3, + /* XOR16mi */ + }, + { /* 15229 */ + 4, + /* XOR16mi8 */ + }, + { /* 15230 */ + 5, + /* XOR16mr */ + }, + { /* 15231 */ + 6, + /* XOR16ri */ + }, + { /* 15232 */ + 7, + /* XOR16ri8 */ + }, + { /* 15233 */ + 8, + /* XOR16rm */ + }, + { /* 15234 */ + 9, + /* XOR16rr */ + }, + { /* 15235 */ + 10, + /* XOR16rr_REV */ + }, + { /* 15236 */ + 2, + /* XOR32i32 */ + }, + { /* 15237 */ + 3, + /* XOR32mi */ + }, + { /* 15238 */ + 4, + /* XOR32mi8 */ + }, + { /* 15239 */ + 5, + /* XOR32mr */ + }, + { /* 15240 */ + 6, + /* XOR32ri */ + }, + { /* 15241 */ + 7, + /* XOR32ri8 */ + }, + { /* 15242 */ + 8, + /* XOR32rm */ + }, + { /* 15243 */ + 9, + /* XOR32rr */ + }, + { /* 15244 */ + 10, + /* XOR32rr_REV */ + }, + { /* 15245 */ + 11, + /* XOR64i32 */ + }, + { /* 15246 */ + 12, + /* XOR64mi32 */ + }, + { /* 15247 */ + 4, + /* XOR64mi8 */ + }, + { /* 15248 */ + 13, + /* XOR64mr */ + }, + { /* 15249 */ + 14, + /* XOR64ri32 */ + }, + { /* 15250 */ + 15, + /* XOR64ri8 */ + }, + { /* 15251 */ + 16, + /* XOR64rm */ + }, + { /* 15252 */ + 17, + /* XOR64rr */ + }, + { /* 15253 */ + 18, + /* XOR64rr_REV */ + }, + { /* 15254 */ + 1, + /* XOR8i8 */ + }, + { /* 15255 */ + 4, + /* XOR8mi */ + }, + { /* 15256 */ + 4, + /* XOR8mi8 */ + }, + { /* 15257 */ + 19, + /* XOR8mr */ + }, + { /* 15258 */ + 20, + /* XOR8ri */ + }, + { /* 15259 */ + 20, + /* XOR8ri8 */ + }, + { /* 15260 */ + 21, + /* XOR8rm */ + }, + { /* 15261 */ + 22, + /* XOR8rr */ + }, + { /* 15262 */ + 23, + /* XOR8rr_REV */ + }, + { /* 15263 */ + 26, + /* XORPDrm */ + }, + { /* 15264 */ + 27, + /* XORPDrr */ + }, + { /* 15265 */ + 26, + /* XORPSrm */ + }, + { /* 15266 */ + 27, + /* XORPSrr */ + }, + { /* 15267 */ + 0, + /* */ + }, + { /* 15268 */ + 28, + /* XRSTOR */ + }, + { /* 15269 */ + 28, + /* XRSTOR64 */ + }, + { /* 15270 */ + 28, + /* XRSTORS */ + }, + { /* 15271 */ + 28, + /* XRSTORS64 */ + }, + { /* 15272 */ + 28, + /* XSAVE */ + }, + { /* 15273 */ + 28, + /* XSAVE64 */ + }, + { /* 15274 */ + 28, + /* XSAVEC */ + }, + { /* 15275 */ + 28, + /* XSAVEC64 */ + }, + { /* 15276 */ + 28, + /* XSAVEOPT */ + }, + { /* 15277 */ + 28, + /* XSAVEOPT64 */ + }, + { /* 15278 */ + 28, + /* XSAVES */ + }, + { /* 15279 */ + 28, + /* XSAVES64 */ + }, + { /* 15280 */ + 0, + /* XSETBV */ + }, + { /* 15281 */ + 0, + /* XSHA1 */ + }, + { /* 15282 */ + 0, + /* XSHA256 */ + }, + { /* 15283 */ + 0, + /* XSTORE */ + }, + { /* 15284 */ + 0, + /* XTEST */ + }, +}; + +static const uint8_t x86DisassemblerContexts[16384] = { + IC, /* 0 */ + IC_64BIT, /* 1 */ + IC_XS, /* 2 */ + IC_64BIT_XS, /* 3 */ + IC_XD, /* 4 */ + IC_64BIT_XD, /* 5 */ + IC_XS, /* 6 */ + IC_64BIT_XS, /* 7 */ + IC, /* 8 */ + IC_64BIT_REXW, /* 9 */ + IC_XS, /* 10 */ + IC_64BIT_REXW_XS, /* 11 */ + IC_XD, /* 12 */ + IC_64BIT_REXW_XD, /* 13 */ + IC_XS, /* 14 */ + IC_64BIT_REXW_XS, /* 15 */ + IC_OPSIZE, /* 16 */ + IC_64BIT_OPSIZE, /* 17 */ + IC_XS_OPSIZE, /* 18 */ + IC_64BIT_XS_OPSIZE, /* 19 */ + IC_XD_OPSIZE, /* 20 */ + IC_64BIT_XD_OPSIZE, /* 21 */ + IC_XS_OPSIZE, /* 22 */ + IC_64BIT_XD_OPSIZE, /* 23 */ + IC_OPSIZE, /* 24 */ + IC_64BIT_REXW_OPSIZE, /* 25 */ + IC_XS_OPSIZE, /* 26 */ + IC_64BIT_REXW_XS, /* 27 */ + IC_XD_OPSIZE, /* 28 */ + IC_64BIT_REXW_XD, /* 29 */ + IC_XS_OPSIZE, /* 30 */ + IC_64BIT_REXW_XS, /* 31 */ + IC_ADSIZE, /* 32 */ + IC_64BIT_ADSIZE, /* 33 */ + IC_XS_ADSIZE, /* 34 */ + IC_64BIT_XS_ADSIZE, /* 35 */ + IC_XD_ADSIZE, /* 36 */ + IC_64BIT_XD_ADSIZE, /* 37 */ + IC_XS_ADSIZE, /* 38 */ + IC_64BIT_XD_ADSIZE, /* 39 */ + IC_ADSIZE, /* 40 */ + IC_64BIT_REXW_ADSIZE, /* 41 */ + IC_XS_ADSIZE, /* 42 */ + IC_64BIT_REXW_XS, /* 43 */ + IC_XD_ADSIZE, /* 44 */ + IC_64BIT_REXW_XD, /* 45 */ + IC_XS_ADSIZE, /* 46 */ + IC_64BIT_REXW_XS, /* 47 */ + IC_OPSIZE_ADSIZE, /* 48 */ + IC_64BIT_OPSIZE_ADSIZE, /* 49 */ + IC_XS_OPSIZE, /* 50 */ + IC_64BIT_XS_OPSIZE, /* 51 */ + IC_XD_OPSIZE, /* 52 */ + IC_64BIT_XD_OPSIZE, /* 53 */ + IC_XS_OPSIZE, /* 54 */ + IC_64BIT_XD_OPSIZE, /* 55 */ + IC_OPSIZE_ADSIZE, /* 56 */ + IC_64BIT_REXW_OPSIZE, /* 57 */ + IC_XS_OPSIZE, /* 58 */ + IC_64BIT_REXW_XS, /* 59 */ + IC_XD_OPSIZE, /* 60 */ + IC_64BIT_REXW_XD, /* 61 */ + IC_XS_OPSIZE, /* 62 */ + IC_64BIT_REXW_XS, /* 63 */ + IC_VEX, /* 64 */ + IC_VEX, /* 65 */ + IC_VEX_XS, /* 66 */ + IC_VEX_XS, /* 67 */ + IC_VEX_XD, /* 68 */ + IC_VEX_XD, /* 69 */ + IC_VEX_XD, /* 70 */ + IC_VEX_XD, /* 71 */ + IC_VEX_W, /* 72 */ + IC_VEX_W, /* 73 */ + IC_VEX_W_XS, /* 74 */ + IC_VEX_W_XS, /* 75 */ + IC_VEX_W_XD, /* 76 */ + IC_VEX_W_XD, /* 77 */ + IC_VEX_W_XD, /* 78 */ + IC_VEX_W_XD, /* 79 */ + IC_VEX_OPSIZE, /* 80 */ + IC_VEX_OPSIZE, /* 81 */ + IC_VEX_OPSIZE, /* 82 */ + IC_VEX_OPSIZE, /* 83 */ + IC_VEX_OPSIZE, /* 84 */ + IC_VEX_OPSIZE, /* 85 */ + IC_VEX_OPSIZE, /* 86 */ + IC_VEX_OPSIZE, /* 87 */ + IC_VEX_W_OPSIZE, /* 88 */ + IC_VEX_W_OPSIZE, /* 89 */ + IC_VEX_W_OPSIZE, /* 90 */ + IC_VEX_W_OPSIZE, /* 91 */ + IC_VEX_W_OPSIZE, /* 92 */ + IC_VEX_W_OPSIZE, /* 93 */ + IC_VEX_W_OPSIZE, /* 94 */ + IC_VEX_W_OPSIZE, /* 95 */ + IC_VEX, /* 96 */ + IC_VEX, /* 97 */ + IC_VEX_XS, /* 98 */ + IC_VEX_XS, /* 99 */ + IC_VEX_XD, /* 100 */ + IC_VEX_XD, /* 101 */ + IC_VEX_XD, /* 102 */ + IC_VEX_XD, /* 103 */ + IC_VEX_W, /* 104 */ + IC_VEX_W, /* 105 */ + IC_VEX_W_XS, /* 106 */ + IC_VEX_W_XS, /* 107 */ + IC_VEX_W_XD, /* 108 */ + IC_VEX_W_XD, /* 109 */ + IC_VEX_W_XD, /* 110 */ + IC_VEX_W_XD, /* 111 */ + IC_VEX_OPSIZE, /* 112 */ + IC_VEX_OPSIZE, /* 113 */ + IC_VEX_OPSIZE, /* 114 */ + IC_VEX_OPSIZE, /* 115 */ + IC_VEX_OPSIZE, /* 116 */ + IC_VEX_OPSIZE, /* 117 */ + IC_VEX_OPSIZE, /* 118 */ + IC_VEX_OPSIZE, /* 119 */ + IC_VEX_W_OPSIZE, /* 120 */ + IC_VEX_W_OPSIZE, /* 121 */ + IC_VEX_W_OPSIZE, /* 122 */ + IC_VEX_W_OPSIZE, /* 123 */ + IC_VEX_W_OPSIZE, /* 124 */ + IC_VEX_W_OPSIZE, /* 125 */ + IC_VEX_W_OPSIZE, /* 126 */ + IC_VEX_W_OPSIZE, /* 127 */ + IC_VEX_L, /* 128 */ + IC_VEX_L, /* 129 */ + IC_VEX_L_XS, /* 130 */ + IC_VEX_L_XS, /* 131 */ + IC_VEX_L_XD, /* 132 */ + IC_VEX_L_XD, /* 133 */ + IC_VEX_L_XD, /* 134 */ + IC_VEX_L_XD, /* 135 */ + IC_VEX_L_W, /* 136 */ + IC_VEX_L_W, /* 137 */ + IC_VEX_L_W_XS, /* 138 */ + IC_VEX_L_W_XS, /* 139 */ + IC_VEX_L_W_XD, /* 140 */ + IC_VEX_L_W_XD, /* 141 */ + IC_VEX_L_W_XD, /* 142 */ + IC_VEX_L_W_XD, /* 143 */ + IC_VEX_L_OPSIZE, /* 144 */ + IC_VEX_L_OPSIZE, /* 145 */ + IC_VEX_L_OPSIZE, /* 146 */ + IC_VEX_L_OPSIZE, /* 147 */ + IC_VEX_L_OPSIZE, /* 148 */ + IC_VEX_L_OPSIZE, /* 149 */ + IC_VEX_L_OPSIZE, /* 150 */ + IC_VEX_L_OPSIZE, /* 151 */ + IC_VEX_L_W_OPSIZE, /* 152 */ + IC_VEX_L_W_OPSIZE, /* 153 */ + IC_VEX_L_W_OPSIZE, /* 154 */ + IC_VEX_L_W_OPSIZE, /* 155 */ + IC_VEX_L_W_OPSIZE, /* 156 */ + IC_VEX_L_W_OPSIZE, /* 157 */ + IC_VEX_L_W_OPSIZE, /* 158 */ + IC_VEX_L_W_OPSIZE, /* 159 */ + IC_VEX_L, /* 160 */ + IC_VEX_L, /* 161 */ + IC_VEX_L_XS, /* 162 */ + IC_VEX_L_XS, /* 163 */ + IC_VEX_L_XD, /* 164 */ + IC_VEX_L_XD, /* 165 */ + IC_VEX_L_XD, /* 166 */ + IC_VEX_L_XD, /* 167 */ + IC_VEX_L_W, /* 168 */ + IC_VEX_L_W, /* 169 */ + IC_VEX_L_W_XS, /* 170 */ + IC_VEX_L_W_XS, /* 171 */ + IC_VEX_L_W_XD, /* 172 */ + IC_VEX_L_W_XD, /* 173 */ + IC_VEX_L_W_XD, /* 174 */ + IC_VEX_L_W_XD, /* 175 */ + IC_VEX_L_OPSIZE, /* 176 */ + IC_VEX_L_OPSIZE, /* 177 */ + IC_VEX_L_OPSIZE, /* 178 */ + IC_VEX_L_OPSIZE, /* 179 */ + IC_VEX_L_OPSIZE, /* 180 */ + IC_VEX_L_OPSIZE, /* 181 */ + IC_VEX_L_OPSIZE, /* 182 */ + IC_VEX_L_OPSIZE, /* 183 */ + IC_VEX_L_W_OPSIZE, /* 184 */ + IC_VEX_L_W_OPSIZE, /* 185 */ + IC_VEX_L_W_OPSIZE, /* 186 */ + IC_VEX_L_W_OPSIZE, /* 187 */ + IC_VEX_L_W_OPSIZE, /* 188 */ + IC_VEX_L_W_OPSIZE, /* 189 */ + IC_VEX_L_W_OPSIZE, /* 190 */ + IC_VEX_L_W_OPSIZE, /* 191 */ + IC_VEX_L, /* 192 */ + IC_VEX_L, /* 193 */ + IC_VEX_L_XS, /* 194 */ + IC_VEX_L_XS, /* 195 */ + IC_VEX_L_XD, /* 196 */ + IC_VEX_L_XD, /* 197 */ + IC_VEX_L_XD, /* 198 */ + IC_VEX_L_XD, /* 199 */ + IC_VEX_L_W, /* 200 */ + IC_VEX_L_W, /* 201 */ + IC_VEX_L_W_XS, /* 202 */ + IC_VEX_L_W_XS, /* 203 */ + IC_VEX_L_W_XD, /* 204 */ + IC_VEX_L_W_XD, /* 205 */ + IC_VEX_L_W_XD, /* 206 */ + IC_VEX_L_W_XD, /* 207 */ + IC_VEX_L_OPSIZE, /* 208 */ + IC_VEX_L_OPSIZE, /* 209 */ + IC_VEX_L_OPSIZE, /* 210 */ + IC_VEX_L_OPSIZE, /* 211 */ + IC_VEX_L_OPSIZE, /* 212 */ + IC_VEX_L_OPSIZE, /* 213 */ + IC_VEX_L_OPSIZE, /* 214 */ + IC_VEX_L_OPSIZE, /* 215 */ + IC_VEX_L_W_OPSIZE, /* 216 */ + IC_VEX_L_W_OPSIZE, /* 217 */ + IC_VEX_L_W_OPSIZE, /* 218 */ + IC_VEX_L_W_OPSIZE, /* 219 */ + IC_VEX_L_W_OPSIZE, /* 220 */ + IC_VEX_L_W_OPSIZE, /* 221 */ + IC_VEX_L_W_OPSIZE, /* 222 */ + IC_VEX_L_W_OPSIZE, /* 223 */ + IC_VEX_L, /* 224 */ + IC_VEX_L, /* 225 */ + IC_VEX_L_XS, /* 226 */ + IC_VEX_L_XS, /* 227 */ + IC_VEX_L_XD, /* 228 */ + IC_VEX_L_XD, /* 229 */ + IC_VEX_L_XD, /* 230 */ + IC_VEX_L_XD, /* 231 */ + IC_VEX_L_W, /* 232 */ + IC_VEX_L_W, /* 233 */ + IC_VEX_L_W_XS, /* 234 */ + IC_VEX_L_W_XS, /* 235 */ + IC_VEX_L_W_XD, /* 236 */ + IC_VEX_L_W_XD, /* 237 */ + IC_VEX_L_W_XD, /* 238 */ + IC_VEX_L_W_XD, /* 239 */ + IC_VEX_L_OPSIZE, /* 240 */ + IC_VEX_L_OPSIZE, /* 241 */ + IC_VEX_L_OPSIZE, /* 242 */ + IC_VEX_L_OPSIZE, /* 243 */ + IC_VEX_L_OPSIZE, /* 244 */ + IC_VEX_L_OPSIZE, /* 245 */ + IC_VEX_L_OPSIZE, /* 246 */ + IC_VEX_L_OPSIZE, /* 247 */ + IC_VEX_L_W_OPSIZE, /* 248 */ + IC_VEX_L_W_OPSIZE, /* 249 */ + IC_VEX_L_W_OPSIZE, /* 250 */ + IC_VEX_L_W_OPSIZE, /* 251 */ + IC_VEX_L_W_OPSIZE, /* 252 */ + IC_VEX_L_W_OPSIZE, /* 253 */ + IC_VEX_L_W_OPSIZE, /* 254 */ + IC_VEX_L_W_OPSIZE, /* 255 */ + IC_EVEX, /* 256 */ + IC_EVEX, /* 257 */ + IC_EVEX_XS, /* 258 */ + IC_EVEX_XS, /* 259 */ + IC_EVEX_XD, /* 260 */ + IC_EVEX_XD, /* 261 */ + IC_EVEX_XD, /* 262 */ + IC_EVEX_XD, /* 263 */ + IC_EVEX_W, /* 264 */ + IC_EVEX_W, /* 265 */ + IC_EVEX_W_XS, /* 266 */ + IC_EVEX_W_XS, /* 267 */ + IC_EVEX_W_XD, /* 268 */ + IC_EVEX_W_XD, /* 269 */ + IC_EVEX_W_XD, /* 270 */ + IC_EVEX_W_XD, /* 271 */ + IC_EVEX_OPSIZE, /* 272 */ + IC_EVEX_OPSIZE, /* 273 */ + IC_EVEX_OPSIZE, /* 274 */ + IC_EVEX_OPSIZE, /* 275 */ + IC_EVEX_OPSIZE, /* 276 */ + IC_EVEX_OPSIZE, /* 277 */ + IC_EVEX_OPSIZE, /* 278 */ + IC_EVEX_OPSIZE, /* 279 */ + IC_EVEX_W_OPSIZE, /* 280 */ + IC_EVEX_W_OPSIZE, /* 281 */ + IC_EVEX_W_OPSIZE, /* 282 */ + IC_EVEX_W_OPSIZE, /* 283 */ + IC_EVEX_W_OPSIZE, /* 284 */ + IC_EVEX_W_OPSIZE, /* 285 */ + IC_EVEX_W_OPSIZE, /* 286 */ + IC_EVEX_W_OPSIZE, /* 287 */ + IC_EVEX, /* 288 */ + IC_EVEX, /* 289 */ + IC_EVEX_XS, /* 290 */ + IC_EVEX_XS, /* 291 */ + IC_EVEX_XD, /* 292 */ + IC_EVEX_XD, /* 293 */ + IC_EVEX_XD, /* 294 */ + IC_EVEX_XD, /* 295 */ + IC_EVEX_W, /* 296 */ + IC_EVEX_W, /* 297 */ + IC_EVEX_W_XS, /* 298 */ + IC_EVEX_W_XS, /* 299 */ + IC_EVEX_W_XD, /* 300 */ + IC_EVEX_W_XD, /* 301 */ + IC_EVEX_W_XD, /* 302 */ + IC_EVEX_W_XD, /* 303 */ + IC_EVEX_OPSIZE, /* 304 */ + IC_EVEX_OPSIZE, /* 305 */ + IC_EVEX_OPSIZE, /* 306 */ + IC_EVEX_OPSIZE, /* 307 */ + IC_EVEX_OPSIZE, /* 308 */ + IC_EVEX_OPSIZE, /* 309 */ + IC_EVEX_OPSIZE, /* 310 */ + IC_EVEX_OPSIZE, /* 311 */ + IC_EVEX_W_OPSIZE, /* 312 */ + IC_EVEX_W_OPSIZE, /* 313 */ + IC_EVEX_W_OPSIZE, /* 314 */ + IC_EVEX_W_OPSIZE, /* 315 */ + IC_EVEX_W_OPSIZE, /* 316 */ + IC_EVEX_W_OPSIZE, /* 317 */ + IC_EVEX_W_OPSIZE, /* 318 */ + IC_EVEX_W_OPSIZE, /* 319 */ + IC_EVEX, /* 320 */ + IC_EVEX, /* 321 */ + IC_EVEX_XS, /* 322 */ + IC_EVEX_XS, /* 323 */ + IC_EVEX_XD, /* 324 */ + IC_EVEX_XD, /* 325 */ + IC_EVEX_XD, /* 326 */ + IC_EVEX_XD, /* 327 */ + IC_EVEX_W, /* 328 */ + IC_EVEX_W, /* 329 */ + IC_EVEX_W_XS, /* 330 */ + IC_EVEX_W_XS, /* 331 */ + IC_EVEX_W_XD, /* 332 */ + IC_EVEX_W_XD, /* 333 */ + IC_EVEX_W_XD, /* 334 */ + IC_EVEX_W_XD, /* 335 */ + IC_EVEX_OPSIZE, /* 336 */ + IC_EVEX_OPSIZE, /* 337 */ + IC_EVEX_OPSIZE, /* 338 */ + IC_EVEX_OPSIZE, /* 339 */ + IC_EVEX_OPSIZE, /* 340 */ + IC_EVEX_OPSIZE, /* 341 */ + IC_EVEX_OPSIZE, /* 342 */ + IC_EVEX_OPSIZE, /* 343 */ + IC_EVEX_W_OPSIZE, /* 344 */ + IC_EVEX_W_OPSIZE, /* 345 */ + IC_EVEX_W_OPSIZE, /* 346 */ + IC_EVEX_W_OPSIZE, /* 347 */ + IC_EVEX_W_OPSIZE, /* 348 */ + IC_EVEX_W_OPSIZE, /* 349 */ + IC_EVEX_W_OPSIZE, /* 350 */ + IC_EVEX_W_OPSIZE, /* 351 */ + IC_EVEX, /* 352 */ + IC_EVEX, /* 353 */ + IC_EVEX_XS, /* 354 */ + IC_EVEX_XS, /* 355 */ + IC_EVEX_XD, /* 356 */ + IC_EVEX_XD, /* 357 */ + IC_EVEX_XD, /* 358 */ + IC_EVEX_XD, /* 359 */ + IC_EVEX_W, /* 360 */ + IC_EVEX_W, /* 361 */ + IC_EVEX_W_XS, /* 362 */ + IC_EVEX_W_XS, /* 363 */ + IC_EVEX_W_XD, /* 364 */ + IC_EVEX_W_XD, /* 365 */ + IC_EVEX_W_XD, /* 366 */ + IC_EVEX_W_XD, /* 367 */ + IC_EVEX_OPSIZE, /* 368 */ + IC_EVEX_OPSIZE, /* 369 */ + IC_EVEX_OPSIZE, /* 370 */ + IC_EVEX_OPSIZE, /* 371 */ + IC_EVEX_OPSIZE, /* 372 */ + IC_EVEX_OPSIZE, /* 373 */ + IC_EVEX_OPSIZE, /* 374 */ + IC_EVEX_OPSIZE, /* 375 */ + IC_EVEX_W_OPSIZE, /* 376 */ + IC_EVEX_W_OPSIZE, /* 377 */ + IC_EVEX_W_OPSIZE, /* 378 */ + IC_EVEX_W_OPSIZE, /* 379 */ + IC_EVEX_W_OPSIZE, /* 380 */ + IC_EVEX_W_OPSIZE, /* 381 */ + IC_EVEX_W_OPSIZE, /* 382 */ + IC_EVEX_W_OPSIZE, /* 383 */ + IC_EVEX, /* 384 */ + IC_EVEX, /* 385 */ + IC_EVEX_XS, /* 386 */ + IC_EVEX_XS, /* 387 */ + IC_EVEX_XD, /* 388 */ + IC_EVEX_XD, /* 389 */ + IC_EVEX_XD, /* 390 */ + IC_EVEX_XD, /* 391 */ + IC_EVEX_W, /* 392 */ + IC_EVEX_W, /* 393 */ + IC_EVEX_W_XS, /* 394 */ + IC_EVEX_W_XS, /* 395 */ + IC_EVEX_W_XD, /* 396 */ + IC_EVEX_W_XD, /* 397 */ + IC_EVEX_W_XD, /* 398 */ + IC_EVEX_W_XD, /* 399 */ + IC_EVEX_OPSIZE, /* 400 */ + IC_EVEX_OPSIZE, /* 401 */ + IC_EVEX_OPSIZE, /* 402 */ + IC_EVEX_OPSIZE, /* 403 */ + IC_EVEX_OPSIZE, /* 404 */ + IC_EVEX_OPSIZE, /* 405 */ + IC_EVEX_OPSIZE, /* 406 */ + IC_EVEX_OPSIZE, /* 407 */ + IC_EVEX_W_OPSIZE, /* 408 */ + IC_EVEX_W_OPSIZE, /* 409 */ + IC_EVEX_W_OPSIZE, /* 410 */ + IC_EVEX_W_OPSIZE, /* 411 */ + IC_EVEX_W_OPSIZE, /* 412 */ + IC_EVEX_W_OPSIZE, /* 413 */ + IC_EVEX_W_OPSIZE, /* 414 */ + IC_EVEX_W_OPSIZE, /* 415 */ + IC_EVEX, /* 416 */ + IC_EVEX, /* 417 */ + IC_EVEX_XS, /* 418 */ + IC_EVEX_XS, /* 419 */ + IC_EVEX_XD, /* 420 */ + IC_EVEX_XD, /* 421 */ + IC_EVEX_XD, /* 422 */ + IC_EVEX_XD, /* 423 */ + IC_EVEX_W, /* 424 */ + IC_EVEX_W, /* 425 */ + IC_EVEX_W_XS, /* 426 */ + IC_EVEX_W_XS, /* 427 */ + IC_EVEX_W_XD, /* 428 */ + IC_EVEX_W_XD, /* 429 */ + IC_EVEX_W_XD, /* 430 */ + IC_EVEX_W_XD, /* 431 */ + IC_EVEX_OPSIZE, /* 432 */ + IC_EVEX_OPSIZE, /* 433 */ + IC_EVEX_OPSIZE, /* 434 */ + IC_EVEX_OPSIZE, /* 435 */ + IC_EVEX_OPSIZE, /* 436 */ + IC_EVEX_OPSIZE, /* 437 */ + IC_EVEX_OPSIZE, /* 438 */ + IC_EVEX_OPSIZE, /* 439 */ + IC_EVEX_W_OPSIZE, /* 440 */ + IC_EVEX_W_OPSIZE, /* 441 */ + IC_EVEX_W_OPSIZE, /* 442 */ + IC_EVEX_W_OPSIZE, /* 443 */ + IC_EVEX_W_OPSIZE, /* 444 */ + IC_EVEX_W_OPSIZE, /* 445 */ + IC_EVEX_W_OPSIZE, /* 446 */ + IC_EVEX_W_OPSIZE, /* 447 */ + IC_EVEX, /* 448 */ + IC_EVEX, /* 449 */ + IC_EVEX_XS, /* 450 */ + IC_EVEX_XS, /* 451 */ + IC_EVEX_XD, /* 452 */ + IC_EVEX_XD, /* 453 */ + IC_EVEX_XD, /* 454 */ + IC_EVEX_XD, /* 455 */ + IC_EVEX_W, /* 456 */ + IC_EVEX_W, /* 457 */ + IC_EVEX_W_XS, /* 458 */ + IC_EVEX_W_XS, /* 459 */ + IC_EVEX_W_XD, /* 460 */ + IC_EVEX_W_XD, /* 461 */ + IC_EVEX_W_XD, /* 462 */ + IC_EVEX_W_XD, /* 463 */ + IC_EVEX_OPSIZE, /* 464 */ + IC_EVEX_OPSIZE, /* 465 */ + IC_EVEX_OPSIZE, /* 466 */ + IC_EVEX_OPSIZE, /* 467 */ + IC_EVEX_OPSIZE, /* 468 */ + IC_EVEX_OPSIZE, /* 469 */ + IC_EVEX_OPSIZE, /* 470 */ + IC_EVEX_OPSIZE, /* 471 */ + IC_EVEX_W_OPSIZE, /* 472 */ + IC_EVEX_W_OPSIZE, /* 473 */ + IC_EVEX_W_OPSIZE, /* 474 */ + IC_EVEX_W_OPSIZE, /* 475 */ + IC_EVEX_W_OPSIZE, /* 476 */ + IC_EVEX_W_OPSIZE, /* 477 */ + IC_EVEX_W_OPSIZE, /* 478 */ + IC_EVEX_W_OPSIZE, /* 479 */ + IC_EVEX, /* 480 */ + IC_EVEX, /* 481 */ + IC_EVEX_XS, /* 482 */ + IC_EVEX_XS, /* 483 */ + IC_EVEX_XD, /* 484 */ + IC_EVEX_XD, /* 485 */ + IC_EVEX_XD, /* 486 */ + IC_EVEX_XD, /* 487 */ + IC_EVEX_W, /* 488 */ + IC_EVEX_W, /* 489 */ + IC_EVEX_W_XS, /* 490 */ + IC_EVEX_W_XS, /* 491 */ + IC_EVEX_W_XD, /* 492 */ + IC_EVEX_W_XD, /* 493 */ + IC_EVEX_W_XD, /* 494 */ + IC_EVEX_W_XD, /* 495 */ + IC_EVEX_OPSIZE, /* 496 */ + IC_EVEX_OPSIZE, /* 497 */ + IC_EVEX_OPSIZE, /* 498 */ + IC_EVEX_OPSIZE, /* 499 */ + IC_EVEX_OPSIZE, /* 500 */ + IC_EVEX_OPSIZE, /* 501 */ + IC_EVEX_OPSIZE, /* 502 */ + IC_EVEX_OPSIZE, /* 503 */ + IC_EVEX_W_OPSIZE, /* 504 */ + IC_EVEX_W_OPSIZE, /* 505 */ + IC_EVEX_W_OPSIZE, /* 506 */ + IC_EVEX_W_OPSIZE, /* 507 */ + IC_EVEX_W_OPSIZE, /* 508 */ + IC_EVEX_W_OPSIZE, /* 509 */ + IC_EVEX_W_OPSIZE, /* 510 */ + IC_EVEX_W_OPSIZE, /* 511 */ + IC, /* 512 */ + IC_64BIT, /* 513 */ + IC_XS, /* 514 */ + IC_64BIT_XS, /* 515 */ + IC_XD, /* 516 */ + IC_64BIT_XD, /* 517 */ + IC_XS, /* 518 */ + IC_64BIT_XS, /* 519 */ + IC, /* 520 */ + IC_64BIT_REXW, /* 521 */ + IC_XS, /* 522 */ + IC_64BIT_REXW_XS, /* 523 */ + IC_XD, /* 524 */ + IC_64BIT_REXW_XD, /* 525 */ + IC_XS, /* 526 */ + IC_64BIT_REXW_XS, /* 527 */ + IC_OPSIZE, /* 528 */ + IC_64BIT_OPSIZE, /* 529 */ + IC_XS_OPSIZE, /* 530 */ + IC_64BIT_XS_OPSIZE, /* 531 */ + IC_XD_OPSIZE, /* 532 */ + IC_64BIT_XD_OPSIZE, /* 533 */ + IC_XS_OPSIZE, /* 534 */ + IC_64BIT_XD_OPSIZE, /* 535 */ + IC_OPSIZE, /* 536 */ + IC_64BIT_REXW_OPSIZE, /* 537 */ + IC_XS_OPSIZE, /* 538 */ + IC_64BIT_REXW_XS, /* 539 */ + IC_XD_OPSIZE, /* 540 */ + IC_64BIT_REXW_XD, /* 541 */ + IC_XS_OPSIZE, /* 542 */ + IC_64BIT_REXW_XS, /* 543 */ + IC_ADSIZE, /* 544 */ + IC_64BIT_ADSIZE, /* 545 */ + IC_XS_ADSIZE, /* 546 */ + IC_64BIT_XS_ADSIZE, /* 547 */ + IC_XD_ADSIZE, /* 548 */ + IC_64BIT_XD_ADSIZE, /* 549 */ + IC_XS_ADSIZE, /* 550 */ + IC_64BIT_XD_ADSIZE, /* 551 */ + IC_ADSIZE, /* 552 */ + IC_64BIT_REXW_ADSIZE, /* 553 */ + IC_XS_ADSIZE, /* 554 */ + IC_64BIT_REXW_XS, /* 555 */ + IC_XD_ADSIZE, /* 556 */ + IC_64BIT_REXW_XD, /* 557 */ + IC_XS_ADSIZE, /* 558 */ + IC_64BIT_REXW_XS, /* 559 */ + IC_OPSIZE_ADSIZE, /* 560 */ + IC_64BIT_OPSIZE_ADSIZE, /* 561 */ + IC_XS_OPSIZE, /* 562 */ + IC_64BIT_XS_OPSIZE, /* 563 */ + IC_XD_OPSIZE, /* 564 */ + IC_64BIT_XD_OPSIZE, /* 565 */ + IC_XS_OPSIZE, /* 566 */ + IC_64BIT_XD_OPSIZE, /* 567 */ + IC_OPSIZE_ADSIZE, /* 568 */ + IC_64BIT_REXW_OPSIZE, /* 569 */ + IC_XS_OPSIZE, /* 570 */ + IC_64BIT_REXW_XS, /* 571 */ + IC_XD_OPSIZE, /* 572 */ + IC_64BIT_REXW_XD, /* 573 */ + IC_XS_OPSIZE, /* 574 */ + IC_64BIT_REXW_XS, /* 575 */ + IC_VEX, /* 576 */ + IC_VEX, /* 577 */ + IC_VEX_XS, /* 578 */ + IC_VEX_XS, /* 579 */ + IC_VEX_XD, /* 580 */ + IC_VEX_XD, /* 581 */ + IC_VEX_XD, /* 582 */ + IC_VEX_XD, /* 583 */ + IC_VEX_W, /* 584 */ + IC_VEX_W, /* 585 */ + IC_VEX_W_XS, /* 586 */ + IC_VEX_W_XS, /* 587 */ + IC_VEX_W_XD, /* 588 */ + IC_VEX_W_XD, /* 589 */ + IC_VEX_W_XD, /* 590 */ + IC_VEX_W_XD, /* 591 */ + IC_VEX_OPSIZE, /* 592 */ + IC_VEX_OPSIZE, /* 593 */ + IC_VEX_OPSIZE, /* 594 */ + IC_VEX_OPSIZE, /* 595 */ + IC_VEX_OPSIZE, /* 596 */ + IC_VEX_OPSIZE, /* 597 */ + IC_VEX_OPSIZE, /* 598 */ + IC_VEX_OPSIZE, /* 599 */ + IC_VEX_W_OPSIZE, /* 600 */ + IC_VEX_W_OPSIZE, /* 601 */ + IC_VEX_W_OPSIZE, /* 602 */ + IC_VEX_W_OPSIZE, /* 603 */ + IC_VEX_W_OPSIZE, /* 604 */ + IC_VEX_W_OPSIZE, /* 605 */ + IC_VEX_W_OPSIZE, /* 606 */ + IC_VEX_W_OPSIZE, /* 607 */ + IC_VEX, /* 608 */ + IC_VEX, /* 609 */ + IC_VEX_XS, /* 610 */ + IC_VEX_XS, /* 611 */ + IC_VEX_XD, /* 612 */ + IC_VEX_XD, /* 613 */ + IC_VEX_XD, /* 614 */ + IC_VEX_XD, /* 615 */ + IC_VEX_W, /* 616 */ + IC_VEX_W, /* 617 */ + IC_VEX_W_XS, /* 618 */ + IC_VEX_W_XS, /* 619 */ + IC_VEX_W_XD, /* 620 */ + IC_VEX_W_XD, /* 621 */ + IC_VEX_W_XD, /* 622 */ + IC_VEX_W_XD, /* 623 */ + IC_VEX_OPSIZE, /* 624 */ + IC_VEX_OPSIZE, /* 625 */ + IC_VEX_OPSIZE, /* 626 */ + IC_VEX_OPSIZE, /* 627 */ + IC_VEX_OPSIZE, /* 628 */ + IC_VEX_OPSIZE, /* 629 */ + IC_VEX_OPSIZE, /* 630 */ + IC_VEX_OPSIZE, /* 631 */ + IC_VEX_W_OPSIZE, /* 632 */ + IC_VEX_W_OPSIZE, /* 633 */ + IC_VEX_W_OPSIZE, /* 634 */ + IC_VEX_W_OPSIZE, /* 635 */ + IC_VEX_W_OPSIZE, /* 636 */ + IC_VEX_W_OPSIZE, /* 637 */ + IC_VEX_W_OPSIZE, /* 638 */ + IC_VEX_W_OPSIZE, /* 639 */ + IC_VEX_L, /* 640 */ + IC_VEX_L, /* 641 */ + IC_VEX_L_XS, /* 642 */ + IC_VEX_L_XS, /* 643 */ + IC_VEX_L_XD, /* 644 */ + IC_VEX_L_XD, /* 645 */ + IC_VEX_L_XD, /* 646 */ + IC_VEX_L_XD, /* 647 */ + IC_VEX_L_W, /* 648 */ + IC_VEX_L_W, /* 649 */ + IC_VEX_L_W_XS, /* 650 */ + IC_VEX_L_W_XS, /* 651 */ + IC_VEX_L_W_XD, /* 652 */ + IC_VEX_L_W_XD, /* 653 */ + IC_VEX_L_W_XD, /* 654 */ + IC_VEX_L_W_XD, /* 655 */ + IC_VEX_L_OPSIZE, /* 656 */ + IC_VEX_L_OPSIZE, /* 657 */ + IC_VEX_L_OPSIZE, /* 658 */ + IC_VEX_L_OPSIZE, /* 659 */ + IC_VEX_L_OPSIZE, /* 660 */ + IC_VEX_L_OPSIZE, /* 661 */ + IC_VEX_L_OPSIZE, /* 662 */ + IC_VEX_L_OPSIZE, /* 663 */ + IC_VEX_L_W_OPSIZE, /* 664 */ + IC_VEX_L_W_OPSIZE, /* 665 */ + IC_VEX_L_W_OPSIZE, /* 666 */ + IC_VEX_L_W_OPSIZE, /* 667 */ + IC_VEX_L_W_OPSIZE, /* 668 */ + IC_VEX_L_W_OPSIZE, /* 669 */ + IC_VEX_L_W_OPSIZE, /* 670 */ + IC_VEX_L_W_OPSIZE, /* 671 */ + IC_VEX_L, /* 672 */ + IC_VEX_L, /* 673 */ + IC_VEX_L_XS, /* 674 */ + IC_VEX_L_XS, /* 675 */ + IC_VEX_L_XD, /* 676 */ + IC_VEX_L_XD, /* 677 */ + IC_VEX_L_XD, /* 678 */ + IC_VEX_L_XD, /* 679 */ + IC_VEX_L_W, /* 680 */ + IC_VEX_L_W, /* 681 */ + IC_VEX_L_W_XS, /* 682 */ + IC_VEX_L_W_XS, /* 683 */ + IC_VEX_L_W_XD, /* 684 */ + IC_VEX_L_W_XD, /* 685 */ + IC_VEX_L_W_XD, /* 686 */ + IC_VEX_L_W_XD, /* 687 */ + IC_VEX_L_OPSIZE, /* 688 */ + IC_VEX_L_OPSIZE, /* 689 */ + IC_VEX_L_OPSIZE, /* 690 */ + IC_VEX_L_OPSIZE, /* 691 */ + IC_VEX_L_OPSIZE, /* 692 */ + IC_VEX_L_OPSIZE, /* 693 */ + IC_VEX_L_OPSIZE, /* 694 */ + IC_VEX_L_OPSIZE, /* 695 */ + IC_VEX_L_W_OPSIZE, /* 696 */ + IC_VEX_L_W_OPSIZE, /* 697 */ + IC_VEX_L_W_OPSIZE, /* 698 */ + IC_VEX_L_W_OPSIZE, /* 699 */ + IC_VEX_L_W_OPSIZE, /* 700 */ + IC_VEX_L_W_OPSIZE, /* 701 */ + IC_VEX_L_W_OPSIZE, /* 702 */ + IC_VEX_L_W_OPSIZE, /* 703 */ + IC_VEX_L, /* 704 */ + IC_VEX_L, /* 705 */ + IC_VEX_L_XS, /* 706 */ + IC_VEX_L_XS, /* 707 */ + IC_VEX_L_XD, /* 708 */ + IC_VEX_L_XD, /* 709 */ + IC_VEX_L_XD, /* 710 */ + IC_VEX_L_XD, /* 711 */ + IC_VEX_L_W, /* 712 */ + IC_VEX_L_W, /* 713 */ + IC_VEX_L_W_XS, /* 714 */ + IC_VEX_L_W_XS, /* 715 */ + IC_VEX_L_W_XD, /* 716 */ + IC_VEX_L_W_XD, /* 717 */ + IC_VEX_L_W_XD, /* 718 */ + IC_VEX_L_W_XD, /* 719 */ + IC_VEX_L_OPSIZE, /* 720 */ + IC_VEX_L_OPSIZE, /* 721 */ + IC_VEX_L_OPSIZE, /* 722 */ + IC_VEX_L_OPSIZE, /* 723 */ + IC_VEX_L_OPSIZE, /* 724 */ + IC_VEX_L_OPSIZE, /* 725 */ + IC_VEX_L_OPSIZE, /* 726 */ + IC_VEX_L_OPSIZE, /* 727 */ + IC_VEX_L_W_OPSIZE, /* 728 */ + IC_VEX_L_W_OPSIZE, /* 729 */ + IC_VEX_L_W_OPSIZE, /* 730 */ + IC_VEX_L_W_OPSIZE, /* 731 */ + IC_VEX_L_W_OPSIZE, /* 732 */ + IC_VEX_L_W_OPSIZE, /* 733 */ + IC_VEX_L_W_OPSIZE, /* 734 */ + IC_VEX_L_W_OPSIZE, /* 735 */ + IC_VEX_L, /* 736 */ + IC_VEX_L, /* 737 */ + IC_VEX_L_XS, /* 738 */ + IC_VEX_L_XS, /* 739 */ + IC_VEX_L_XD, /* 740 */ + IC_VEX_L_XD, /* 741 */ + IC_VEX_L_XD, /* 742 */ + IC_VEX_L_XD, /* 743 */ + IC_VEX_L_W, /* 744 */ + IC_VEX_L_W, /* 745 */ + IC_VEX_L_W_XS, /* 746 */ + IC_VEX_L_W_XS, /* 747 */ + IC_VEX_L_W_XD, /* 748 */ + IC_VEX_L_W_XD, /* 749 */ + IC_VEX_L_W_XD, /* 750 */ + IC_VEX_L_W_XD, /* 751 */ + IC_VEX_L_OPSIZE, /* 752 */ + IC_VEX_L_OPSIZE, /* 753 */ + IC_VEX_L_OPSIZE, /* 754 */ + IC_VEX_L_OPSIZE, /* 755 */ + IC_VEX_L_OPSIZE, /* 756 */ + IC_VEX_L_OPSIZE, /* 757 */ + IC_VEX_L_OPSIZE, /* 758 */ + IC_VEX_L_OPSIZE, /* 759 */ + IC_VEX_L_W_OPSIZE, /* 760 */ + IC_VEX_L_W_OPSIZE, /* 761 */ + IC_VEX_L_W_OPSIZE, /* 762 */ + IC_VEX_L_W_OPSIZE, /* 763 */ + IC_VEX_L_W_OPSIZE, /* 764 */ + IC_VEX_L_W_OPSIZE, /* 765 */ + IC_VEX_L_W_OPSIZE, /* 766 */ + IC_VEX_L_W_OPSIZE, /* 767 */ + IC_EVEX_L, /* 768 */ + IC_EVEX_L, /* 769 */ + IC_EVEX_L_XS, /* 770 */ + IC_EVEX_L_XS, /* 771 */ + IC_EVEX_L_XD, /* 772 */ + IC_EVEX_L_XD, /* 773 */ + IC_EVEX_L_XD, /* 774 */ + IC_EVEX_L_XD, /* 775 */ + IC_EVEX_L_W, /* 776 */ + IC_EVEX_L_W, /* 777 */ + IC_EVEX_L_W_XS, /* 778 */ + IC_EVEX_L_W_XS, /* 779 */ + IC_EVEX_L_W_XD, /* 780 */ + IC_EVEX_L_W_XD, /* 781 */ + IC_EVEX_L_W_XD, /* 782 */ + IC_EVEX_L_W_XD, /* 783 */ + IC_EVEX_L_OPSIZE, /* 784 */ + IC_EVEX_L_OPSIZE, /* 785 */ + IC_EVEX_L_OPSIZE, /* 786 */ + IC_EVEX_L_OPSIZE, /* 787 */ + IC_EVEX_L_OPSIZE, /* 788 */ + IC_EVEX_L_OPSIZE, /* 789 */ + IC_EVEX_L_OPSIZE, /* 790 */ + IC_EVEX_L_OPSIZE, /* 791 */ + IC_EVEX_L_W_OPSIZE, /* 792 */ + IC_EVEX_L_W_OPSIZE, /* 793 */ + IC_EVEX_L_W_OPSIZE, /* 794 */ + IC_EVEX_L_W_OPSIZE, /* 795 */ + IC_EVEX_L_W_OPSIZE, /* 796 */ + IC_EVEX_L_W_OPSIZE, /* 797 */ + IC_EVEX_L_W_OPSIZE, /* 798 */ + IC_EVEX_L_W_OPSIZE, /* 799 */ + IC_EVEX_L, /* 800 */ + IC_EVEX_L, /* 801 */ + IC_EVEX_L_XS, /* 802 */ + IC_EVEX_L_XS, /* 803 */ + IC_EVEX_L_XD, /* 804 */ + IC_EVEX_L_XD, /* 805 */ + IC_EVEX_L_XD, /* 806 */ + IC_EVEX_L_XD, /* 807 */ + IC_EVEX_L_W, /* 808 */ + IC_EVEX_L_W, /* 809 */ + IC_EVEX_L_W_XS, /* 810 */ + IC_EVEX_L_W_XS, /* 811 */ + IC_EVEX_L_W_XD, /* 812 */ + IC_EVEX_L_W_XD, /* 813 */ + IC_EVEX_L_W_XD, /* 814 */ + IC_EVEX_L_W_XD, /* 815 */ + IC_EVEX_L_OPSIZE, /* 816 */ + IC_EVEX_L_OPSIZE, /* 817 */ + IC_EVEX_L_OPSIZE, /* 818 */ + IC_EVEX_L_OPSIZE, /* 819 */ + IC_EVEX_L_OPSIZE, /* 820 */ + IC_EVEX_L_OPSIZE, /* 821 */ + IC_EVEX_L_OPSIZE, /* 822 */ + IC_EVEX_L_OPSIZE, /* 823 */ + IC_EVEX_L_W_OPSIZE, /* 824 */ + IC_EVEX_L_W_OPSIZE, /* 825 */ + IC_EVEX_L_W_OPSIZE, /* 826 */ + IC_EVEX_L_W_OPSIZE, /* 827 */ + IC_EVEX_L_W_OPSIZE, /* 828 */ + IC_EVEX_L_W_OPSIZE, /* 829 */ + IC_EVEX_L_W_OPSIZE, /* 830 */ + IC_EVEX_L_W_OPSIZE, /* 831 */ + IC_EVEX_L, /* 832 */ + IC_EVEX_L, /* 833 */ + IC_EVEX_L_XS, /* 834 */ + IC_EVEX_L_XS, /* 835 */ + IC_EVEX_L_XD, /* 836 */ + IC_EVEX_L_XD, /* 837 */ + IC_EVEX_L_XD, /* 838 */ + IC_EVEX_L_XD, /* 839 */ + IC_EVEX_L_W, /* 840 */ + IC_EVEX_L_W, /* 841 */ + IC_EVEX_L_W_XS, /* 842 */ + IC_EVEX_L_W_XS, /* 843 */ + IC_EVEX_L_W_XD, /* 844 */ + IC_EVEX_L_W_XD, /* 845 */ + IC_EVEX_L_W_XD, /* 846 */ + IC_EVEX_L_W_XD, /* 847 */ + IC_EVEX_L_OPSIZE, /* 848 */ + IC_EVEX_L_OPSIZE, /* 849 */ + IC_EVEX_L_OPSIZE, /* 850 */ + IC_EVEX_L_OPSIZE, /* 851 */ + IC_EVEX_L_OPSIZE, /* 852 */ + IC_EVEX_L_OPSIZE, /* 853 */ + IC_EVEX_L_OPSIZE, /* 854 */ + IC_EVEX_L_OPSIZE, /* 855 */ + IC_EVEX_L_W_OPSIZE, /* 856 */ + IC_EVEX_L_W_OPSIZE, /* 857 */ + IC_EVEX_L_W_OPSIZE, /* 858 */ + IC_EVEX_L_W_OPSIZE, /* 859 */ + IC_EVEX_L_W_OPSIZE, /* 860 */ + IC_EVEX_L_W_OPSIZE, /* 861 */ + IC_EVEX_L_W_OPSIZE, /* 862 */ + IC_EVEX_L_W_OPSIZE, /* 863 */ + IC_EVEX_L, /* 864 */ + IC_EVEX_L, /* 865 */ + IC_EVEX_L_XS, /* 866 */ + IC_EVEX_L_XS, /* 867 */ + IC_EVEX_L_XD, /* 868 */ + IC_EVEX_L_XD, /* 869 */ + IC_EVEX_L_XD, /* 870 */ + IC_EVEX_L_XD, /* 871 */ + IC_EVEX_L_W, /* 872 */ + IC_EVEX_L_W, /* 873 */ + IC_EVEX_L_W_XS, /* 874 */ + IC_EVEX_L_W_XS, /* 875 */ + IC_EVEX_L_W_XD, /* 876 */ + IC_EVEX_L_W_XD, /* 877 */ + IC_EVEX_L_W_XD, /* 878 */ + IC_EVEX_L_W_XD, /* 879 */ + IC_EVEX_L_OPSIZE, /* 880 */ + IC_EVEX_L_OPSIZE, /* 881 */ + IC_EVEX_L_OPSIZE, /* 882 */ + IC_EVEX_L_OPSIZE, /* 883 */ + IC_EVEX_L_OPSIZE, /* 884 */ + IC_EVEX_L_OPSIZE, /* 885 */ + IC_EVEX_L_OPSIZE, /* 886 */ + IC_EVEX_L_OPSIZE, /* 887 */ + IC_EVEX_L_W_OPSIZE, /* 888 */ + IC_EVEX_L_W_OPSIZE, /* 889 */ + IC_EVEX_L_W_OPSIZE, /* 890 */ + IC_EVEX_L_W_OPSIZE, /* 891 */ + IC_EVEX_L_W_OPSIZE, /* 892 */ + IC_EVEX_L_W_OPSIZE, /* 893 */ + IC_EVEX_L_W_OPSIZE, /* 894 */ + IC_EVEX_L_W_OPSIZE, /* 895 */ + IC_EVEX_L, /* 896 */ + IC_EVEX_L, /* 897 */ + IC_EVEX_L_XS, /* 898 */ + IC_EVEX_L_XS, /* 899 */ + IC_EVEX_L_XD, /* 900 */ + IC_EVEX_L_XD, /* 901 */ + IC_EVEX_L_XD, /* 902 */ + IC_EVEX_L_XD, /* 903 */ + IC_EVEX_L_W, /* 904 */ + IC_EVEX_L_W, /* 905 */ + IC_EVEX_L_W_XS, /* 906 */ + IC_EVEX_L_W_XS, /* 907 */ + IC_EVEX_L_W_XD, /* 908 */ + IC_EVEX_L_W_XD, /* 909 */ + IC_EVEX_L_W_XD, /* 910 */ + IC_EVEX_L_W_XD, /* 911 */ + IC_EVEX_L_OPSIZE, /* 912 */ + IC_EVEX_L_OPSIZE, /* 913 */ + IC_EVEX_L_OPSIZE, /* 914 */ + IC_EVEX_L_OPSIZE, /* 915 */ + IC_EVEX_L_OPSIZE, /* 916 */ + IC_EVEX_L_OPSIZE, /* 917 */ + IC_EVEX_L_OPSIZE, /* 918 */ + IC_EVEX_L_OPSIZE, /* 919 */ + IC_EVEX_L_W_OPSIZE, /* 920 */ + IC_EVEX_L_W_OPSIZE, /* 921 */ + IC_EVEX_L_W_OPSIZE, /* 922 */ + IC_EVEX_L_W_OPSIZE, /* 923 */ + IC_EVEX_L_W_OPSIZE, /* 924 */ + IC_EVEX_L_W_OPSIZE, /* 925 */ + IC_EVEX_L_W_OPSIZE, /* 926 */ + IC_EVEX_L_W_OPSIZE, /* 927 */ + IC_EVEX_L, /* 928 */ + IC_EVEX_L, /* 929 */ + IC_EVEX_L_XS, /* 930 */ + IC_EVEX_L_XS, /* 931 */ + IC_EVEX_L_XD, /* 932 */ + IC_EVEX_L_XD, /* 933 */ + IC_EVEX_L_XD, /* 934 */ + IC_EVEX_L_XD, /* 935 */ + IC_EVEX_L_W, /* 936 */ + IC_EVEX_L_W, /* 937 */ + IC_EVEX_L_W_XS, /* 938 */ + IC_EVEX_L_W_XS, /* 939 */ + IC_EVEX_L_W_XD, /* 940 */ + IC_EVEX_L_W_XD, /* 941 */ + IC_EVEX_L_W_XD, /* 942 */ + IC_EVEX_L_W_XD, /* 943 */ + IC_EVEX_L_OPSIZE, /* 944 */ + IC_EVEX_L_OPSIZE, /* 945 */ + IC_EVEX_L_OPSIZE, /* 946 */ + IC_EVEX_L_OPSIZE, /* 947 */ + IC_EVEX_L_OPSIZE, /* 948 */ + IC_EVEX_L_OPSIZE, /* 949 */ + IC_EVEX_L_OPSIZE, /* 950 */ + IC_EVEX_L_OPSIZE, /* 951 */ + IC_EVEX_L_W_OPSIZE, /* 952 */ + IC_EVEX_L_W_OPSIZE, /* 953 */ + IC_EVEX_L_W_OPSIZE, /* 954 */ + IC_EVEX_L_W_OPSIZE, /* 955 */ + IC_EVEX_L_W_OPSIZE, /* 956 */ + IC_EVEX_L_W_OPSIZE, /* 957 */ + IC_EVEX_L_W_OPSIZE, /* 958 */ + IC_EVEX_L_W_OPSIZE, /* 959 */ + IC_EVEX_L, /* 960 */ + IC_EVEX_L, /* 961 */ + IC_EVEX_L_XS, /* 962 */ + IC_EVEX_L_XS, /* 963 */ + IC_EVEX_L_XD, /* 964 */ + IC_EVEX_L_XD, /* 965 */ + IC_EVEX_L_XD, /* 966 */ + IC_EVEX_L_XD, /* 967 */ + IC_EVEX_L_W, /* 968 */ + IC_EVEX_L_W, /* 969 */ + IC_EVEX_L_W_XS, /* 970 */ + IC_EVEX_L_W_XS, /* 971 */ + IC_EVEX_L_W_XD, /* 972 */ + IC_EVEX_L_W_XD, /* 973 */ + IC_EVEX_L_W_XD, /* 974 */ + IC_EVEX_L_W_XD, /* 975 */ + IC_EVEX_L_OPSIZE, /* 976 */ + IC_EVEX_L_OPSIZE, /* 977 */ + IC_EVEX_L_OPSIZE, /* 978 */ + IC_EVEX_L_OPSIZE, /* 979 */ + IC_EVEX_L_OPSIZE, /* 980 */ + IC_EVEX_L_OPSIZE, /* 981 */ + IC_EVEX_L_OPSIZE, /* 982 */ + IC_EVEX_L_OPSIZE, /* 983 */ + IC_EVEX_L_W_OPSIZE, /* 984 */ + IC_EVEX_L_W_OPSIZE, /* 985 */ + IC_EVEX_L_W_OPSIZE, /* 986 */ + IC_EVEX_L_W_OPSIZE, /* 987 */ + IC_EVEX_L_W_OPSIZE, /* 988 */ + IC_EVEX_L_W_OPSIZE, /* 989 */ + IC_EVEX_L_W_OPSIZE, /* 990 */ + IC_EVEX_L_W_OPSIZE, /* 991 */ + IC_EVEX_L, /* 992 */ + IC_EVEX_L, /* 993 */ + IC_EVEX_L_XS, /* 994 */ + IC_EVEX_L_XS, /* 995 */ + IC_EVEX_L_XD, /* 996 */ + IC_EVEX_L_XD, /* 997 */ + IC_EVEX_L_XD, /* 998 */ + IC_EVEX_L_XD, /* 999 */ + IC_EVEX_L_W, /* 1000 */ + IC_EVEX_L_W, /* 1001 */ + IC_EVEX_L_W_XS, /* 1002 */ + IC_EVEX_L_W_XS, /* 1003 */ + IC_EVEX_L_W_XD, /* 1004 */ + IC_EVEX_L_W_XD, /* 1005 */ + IC_EVEX_L_W_XD, /* 1006 */ + IC_EVEX_L_W_XD, /* 1007 */ + IC_EVEX_L_OPSIZE, /* 1008 */ + IC_EVEX_L_OPSIZE, /* 1009 */ + IC_EVEX_L_OPSIZE, /* 1010 */ + IC_EVEX_L_OPSIZE, /* 1011 */ + IC_EVEX_L_OPSIZE, /* 1012 */ + IC_EVEX_L_OPSIZE, /* 1013 */ + IC_EVEX_L_OPSIZE, /* 1014 */ + IC_EVEX_L_OPSIZE, /* 1015 */ + IC_EVEX_L_W_OPSIZE, /* 1016 */ + IC_EVEX_L_W_OPSIZE, /* 1017 */ + IC_EVEX_L_W_OPSIZE, /* 1018 */ + IC_EVEX_L_W_OPSIZE, /* 1019 */ + IC_EVEX_L_W_OPSIZE, /* 1020 */ + IC_EVEX_L_W_OPSIZE, /* 1021 */ + IC_EVEX_L_W_OPSIZE, /* 1022 */ + IC_EVEX_L_W_OPSIZE, /* 1023 */ + IC, /* 1024 */ + IC_64BIT, /* 1025 */ + IC_XS, /* 1026 */ + IC_64BIT_XS, /* 1027 */ + IC_XD, /* 1028 */ + IC_64BIT_XD, /* 1029 */ + IC_XS, /* 1030 */ + IC_64BIT_XS, /* 1031 */ + IC, /* 1032 */ + IC_64BIT_REXW, /* 1033 */ + IC_XS, /* 1034 */ + IC_64BIT_REXW_XS, /* 1035 */ + IC_XD, /* 1036 */ + IC_64BIT_REXW_XD, /* 1037 */ + IC_XS, /* 1038 */ + IC_64BIT_REXW_XS, /* 1039 */ + IC_OPSIZE, /* 1040 */ + IC_64BIT_OPSIZE, /* 1041 */ + IC_XS_OPSIZE, /* 1042 */ + IC_64BIT_XS_OPSIZE, /* 1043 */ + IC_XD_OPSIZE, /* 1044 */ + IC_64BIT_XD_OPSIZE, /* 1045 */ + IC_XS_OPSIZE, /* 1046 */ + IC_64BIT_XD_OPSIZE, /* 1047 */ + IC_OPSIZE, /* 1048 */ + IC_64BIT_REXW_OPSIZE, /* 1049 */ + IC_XS_OPSIZE, /* 1050 */ + IC_64BIT_REXW_XS, /* 1051 */ + IC_XD_OPSIZE, /* 1052 */ + IC_64BIT_REXW_XD, /* 1053 */ + IC_XS_OPSIZE, /* 1054 */ + IC_64BIT_REXW_XS, /* 1055 */ + IC_ADSIZE, /* 1056 */ + IC_64BIT_ADSIZE, /* 1057 */ + IC_XS_ADSIZE, /* 1058 */ + IC_64BIT_XS_ADSIZE, /* 1059 */ + IC_XD_ADSIZE, /* 1060 */ + IC_64BIT_XD_ADSIZE, /* 1061 */ + IC_XS_ADSIZE, /* 1062 */ + IC_64BIT_XD_ADSIZE, /* 1063 */ + IC_ADSIZE, /* 1064 */ + IC_64BIT_REXW_ADSIZE, /* 1065 */ + IC_XS_ADSIZE, /* 1066 */ + IC_64BIT_REXW_XS, /* 1067 */ + IC_XD_ADSIZE, /* 1068 */ + IC_64BIT_REXW_XD, /* 1069 */ + IC_XS_ADSIZE, /* 1070 */ + IC_64BIT_REXW_XS, /* 1071 */ + IC_OPSIZE_ADSIZE, /* 1072 */ + IC_64BIT_OPSIZE_ADSIZE, /* 1073 */ + IC_XS_OPSIZE, /* 1074 */ + IC_64BIT_XS_OPSIZE, /* 1075 */ + IC_XD_OPSIZE, /* 1076 */ + IC_64BIT_XD_OPSIZE, /* 1077 */ + IC_XS_OPSIZE, /* 1078 */ + IC_64BIT_XD_OPSIZE, /* 1079 */ + IC_OPSIZE_ADSIZE, /* 1080 */ + IC_64BIT_REXW_OPSIZE, /* 1081 */ + IC_XS_OPSIZE, /* 1082 */ + IC_64BIT_REXW_XS, /* 1083 */ + IC_XD_OPSIZE, /* 1084 */ + IC_64BIT_REXW_XD, /* 1085 */ + IC_XS_OPSIZE, /* 1086 */ + IC_64BIT_REXW_XS, /* 1087 */ + IC_VEX, /* 1088 */ + IC_VEX, /* 1089 */ + IC_VEX_XS, /* 1090 */ + IC_VEX_XS, /* 1091 */ + IC_VEX_XD, /* 1092 */ + IC_VEX_XD, /* 1093 */ + IC_VEX_XD, /* 1094 */ + IC_VEX_XD, /* 1095 */ + IC_VEX_W, /* 1096 */ + IC_VEX_W, /* 1097 */ + IC_VEX_W_XS, /* 1098 */ + IC_VEX_W_XS, /* 1099 */ + IC_VEX_W_XD, /* 1100 */ + IC_VEX_W_XD, /* 1101 */ + IC_VEX_W_XD, /* 1102 */ + IC_VEX_W_XD, /* 1103 */ + IC_VEX_OPSIZE, /* 1104 */ + IC_VEX_OPSIZE, /* 1105 */ + IC_VEX_OPSIZE, /* 1106 */ + IC_VEX_OPSIZE, /* 1107 */ + IC_VEX_OPSIZE, /* 1108 */ + IC_VEX_OPSIZE, /* 1109 */ + IC_VEX_OPSIZE, /* 1110 */ + IC_VEX_OPSIZE, /* 1111 */ + IC_VEX_W_OPSIZE, /* 1112 */ + IC_VEX_W_OPSIZE, /* 1113 */ + IC_VEX_W_OPSIZE, /* 1114 */ + IC_VEX_W_OPSIZE, /* 1115 */ + IC_VEX_W_OPSIZE, /* 1116 */ + IC_VEX_W_OPSIZE, /* 1117 */ + IC_VEX_W_OPSIZE, /* 1118 */ + IC_VEX_W_OPSIZE, /* 1119 */ + IC_VEX, /* 1120 */ + IC_VEX, /* 1121 */ + IC_VEX_XS, /* 1122 */ + IC_VEX_XS, /* 1123 */ + IC_VEX_XD, /* 1124 */ + IC_VEX_XD, /* 1125 */ + IC_VEX_XD, /* 1126 */ + IC_VEX_XD, /* 1127 */ + IC_VEX_W, /* 1128 */ + IC_VEX_W, /* 1129 */ + IC_VEX_W_XS, /* 1130 */ + IC_VEX_W_XS, /* 1131 */ + IC_VEX_W_XD, /* 1132 */ + IC_VEX_W_XD, /* 1133 */ + IC_VEX_W_XD, /* 1134 */ + IC_VEX_W_XD, /* 1135 */ + IC_VEX_OPSIZE, /* 1136 */ + IC_VEX_OPSIZE, /* 1137 */ + IC_VEX_OPSIZE, /* 1138 */ + IC_VEX_OPSIZE, /* 1139 */ + IC_VEX_OPSIZE, /* 1140 */ + IC_VEX_OPSIZE, /* 1141 */ + IC_VEX_OPSIZE, /* 1142 */ + IC_VEX_OPSIZE, /* 1143 */ + IC_VEX_W_OPSIZE, /* 1144 */ + IC_VEX_W_OPSIZE, /* 1145 */ + IC_VEX_W_OPSIZE, /* 1146 */ + IC_VEX_W_OPSIZE, /* 1147 */ + IC_VEX_W_OPSIZE, /* 1148 */ + IC_VEX_W_OPSIZE, /* 1149 */ + IC_VEX_W_OPSIZE, /* 1150 */ + IC_VEX_W_OPSIZE, /* 1151 */ + IC_VEX_L, /* 1152 */ + IC_VEX_L, /* 1153 */ + IC_VEX_L_XS, /* 1154 */ + IC_VEX_L_XS, /* 1155 */ + IC_VEX_L_XD, /* 1156 */ + IC_VEX_L_XD, /* 1157 */ + IC_VEX_L_XD, /* 1158 */ + IC_VEX_L_XD, /* 1159 */ + IC_VEX_L_W, /* 1160 */ + IC_VEX_L_W, /* 1161 */ + IC_VEX_L_W_XS, /* 1162 */ + IC_VEX_L_W_XS, /* 1163 */ + IC_VEX_L_W_XD, /* 1164 */ + IC_VEX_L_W_XD, /* 1165 */ + IC_VEX_L_W_XD, /* 1166 */ + IC_VEX_L_W_XD, /* 1167 */ + IC_VEX_L_OPSIZE, /* 1168 */ + IC_VEX_L_OPSIZE, /* 1169 */ + IC_VEX_L_OPSIZE, /* 1170 */ + IC_VEX_L_OPSIZE, /* 1171 */ + IC_VEX_L_OPSIZE, /* 1172 */ + IC_VEX_L_OPSIZE, /* 1173 */ + IC_VEX_L_OPSIZE, /* 1174 */ + IC_VEX_L_OPSIZE, /* 1175 */ + IC_VEX_L_W_OPSIZE, /* 1176 */ + IC_VEX_L_W_OPSIZE, /* 1177 */ + IC_VEX_L_W_OPSIZE, /* 1178 */ + IC_VEX_L_W_OPSIZE, /* 1179 */ + IC_VEX_L_W_OPSIZE, /* 1180 */ + IC_VEX_L_W_OPSIZE, /* 1181 */ + IC_VEX_L_W_OPSIZE, /* 1182 */ + IC_VEX_L_W_OPSIZE, /* 1183 */ + IC_VEX_L, /* 1184 */ + IC_VEX_L, /* 1185 */ + IC_VEX_L_XS, /* 1186 */ + IC_VEX_L_XS, /* 1187 */ + IC_VEX_L_XD, /* 1188 */ + IC_VEX_L_XD, /* 1189 */ + IC_VEX_L_XD, /* 1190 */ + IC_VEX_L_XD, /* 1191 */ + IC_VEX_L_W, /* 1192 */ + IC_VEX_L_W, /* 1193 */ + IC_VEX_L_W_XS, /* 1194 */ + IC_VEX_L_W_XS, /* 1195 */ + IC_VEX_L_W_XD, /* 1196 */ + IC_VEX_L_W_XD, /* 1197 */ + IC_VEX_L_W_XD, /* 1198 */ + IC_VEX_L_W_XD, /* 1199 */ + IC_VEX_L_OPSIZE, /* 1200 */ + IC_VEX_L_OPSIZE, /* 1201 */ + IC_VEX_L_OPSIZE, /* 1202 */ + IC_VEX_L_OPSIZE, /* 1203 */ + IC_VEX_L_OPSIZE, /* 1204 */ + IC_VEX_L_OPSIZE, /* 1205 */ + IC_VEX_L_OPSIZE, /* 1206 */ + IC_VEX_L_OPSIZE, /* 1207 */ + IC_VEX_L_W_OPSIZE, /* 1208 */ + IC_VEX_L_W_OPSIZE, /* 1209 */ + IC_VEX_L_W_OPSIZE, /* 1210 */ + IC_VEX_L_W_OPSIZE, /* 1211 */ + IC_VEX_L_W_OPSIZE, /* 1212 */ + IC_VEX_L_W_OPSIZE, /* 1213 */ + IC_VEX_L_W_OPSIZE, /* 1214 */ + IC_VEX_L_W_OPSIZE, /* 1215 */ + IC_VEX_L, /* 1216 */ + IC_VEX_L, /* 1217 */ + IC_VEX_L_XS, /* 1218 */ + IC_VEX_L_XS, /* 1219 */ + IC_VEX_L_XD, /* 1220 */ + IC_VEX_L_XD, /* 1221 */ + IC_VEX_L_XD, /* 1222 */ + IC_VEX_L_XD, /* 1223 */ + IC_VEX_L_W, /* 1224 */ + IC_VEX_L_W, /* 1225 */ + IC_VEX_L_W_XS, /* 1226 */ + IC_VEX_L_W_XS, /* 1227 */ + IC_VEX_L_W_XD, /* 1228 */ + IC_VEX_L_W_XD, /* 1229 */ + IC_VEX_L_W_XD, /* 1230 */ + IC_VEX_L_W_XD, /* 1231 */ + IC_VEX_L_OPSIZE, /* 1232 */ + IC_VEX_L_OPSIZE, /* 1233 */ + IC_VEX_L_OPSIZE, /* 1234 */ + IC_VEX_L_OPSIZE, /* 1235 */ + IC_VEX_L_OPSIZE, /* 1236 */ + IC_VEX_L_OPSIZE, /* 1237 */ + IC_VEX_L_OPSIZE, /* 1238 */ + IC_VEX_L_OPSIZE, /* 1239 */ + IC_VEX_L_W_OPSIZE, /* 1240 */ + IC_VEX_L_W_OPSIZE, /* 1241 */ + IC_VEX_L_W_OPSIZE, /* 1242 */ + IC_VEX_L_W_OPSIZE, /* 1243 */ + IC_VEX_L_W_OPSIZE, /* 1244 */ + IC_VEX_L_W_OPSIZE, /* 1245 */ + IC_VEX_L_W_OPSIZE, /* 1246 */ + IC_VEX_L_W_OPSIZE, /* 1247 */ + IC_VEX_L, /* 1248 */ + IC_VEX_L, /* 1249 */ + IC_VEX_L_XS, /* 1250 */ + IC_VEX_L_XS, /* 1251 */ + IC_VEX_L_XD, /* 1252 */ + IC_VEX_L_XD, /* 1253 */ + IC_VEX_L_XD, /* 1254 */ + IC_VEX_L_XD, /* 1255 */ + IC_VEX_L_W, /* 1256 */ + IC_VEX_L_W, /* 1257 */ + IC_VEX_L_W_XS, /* 1258 */ + IC_VEX_L_W_XS, /* 1259 */ + IC_VEX_L_W_XD, /* 1260 */ + IC_VEX_L_W_XD, /* 1261 */ + IC_VEX_L_W_XD, /* 1262 */ + IC_VEX_L_W_XD, /* 1263 */ + IC_VEX_L_OPSIZE, /* 1264 */ + IC_VEX_L_OPSIZE, /* 1265 */ + IC_VEX_L_OPSIZE, /* 1266 */ + IC_VEX_L_OPSIZE, /* 1267 */ + IC_VEX_L_OPSIZE, /* 1268 */ + IC_VEX_L_OPSIZE, /* 1269 */ + IC_VEX_L_OPSIZE, /* 1270 */ + IC_VEX_L_OPSIZE, /* 1271 */ + IC_VEX_L_W_OPSIZE, /* 1272 */ + IC_VEX_L_W_OPSIZE, /* 1273 */ + IC_VEX_L_W_OPSIZE, /* 1274 */ + IC_VEX_L_W_OPSIZE, /* 1275 */ + IC_VEX_L_W_OPSIZE, /* 1276 */ + IC_VEX_L_W_OPSIZE, /* 1277 */ + IC_VEX_L_W_OPSIZE, /* 1278 */ + IC_VEX_L_W_OPSIZE, /* 1279 */ + IC_EVEX_L2, /* 1280 */ + IC_EVEX_L2, /* 1281 */ + IC_EVEX_L2_XS, /* 1282 */ + IC_EVEX_L2_XS, /* 1283 */ + IC_EVEX_L2_XD, /* 1284 */ + IC_EVEX_L2_XD, /* 1285 */ + IC_EVEX_L2_XD, /* 1286 */ + IC_EVEX_L2_XD, /* 1287 */ + IC_EVEX_L2_W, /* 1288 */ + IC_EVEX_L2_W, /* 1289 */ + IC_EVEX_L2_W_XS, /* 1290 */ + IC_EVEX_L2_W_XS, /* 1291 */ + IC_EVEX_L2_W_XD, /* 1292 */ + IC_EVEX_L2_W_XD, /* 1293 */ + IC_EVEX_L2_W_XD, /* 1294 */ + IC_EVEX_L2_W_XD, /* 1295 */ + IC_EVEX_L2_OPSIZE, /* 1296 */ + IC_EVEX_L2_OPSIZE, /* 1297 */ + IC_EVEX_L2_OPSIZE, /* 1298 */ + IC_EVEX_L2_OPSIZE, /* 1299 */ + IC_EVEX_L2_OPSIZE, /* 1300 */ + IC_EVEX_L2_OPSIZE, /* 1301 */ + IC_EVEX_L2_OPSIZE, /* 1302 */ + IC_EVEX_L2_OPSIZE, /* 1303 */ + IC_EVEX_L2_W_OPSIZE, /* 1304 */ + IC_EVEX_L2_W_OPSIZE, /* 1305 */ + IC_EVEX_L2_W_OPSIZE, /* 1306 */ + IC_EVEX_L2_W_OPSIZE, /* 1307 */ + IC_EVEX_L2_W_OPSIZE, /* 1308 */ + IC_EVEX_L2_W_OPSIZE, /* 1309 */ + IC_EVEX_L2_W_OPSIZE, /* 1310 */ + IC_EVEX_L2_W_OPSIZE, /* 1311 */ + IC_EVEX_L2, /* 1312 */ + IC_EVEX_L2, /* 1313 */ + IC_EVEX_L2_XS, /* 1314 */ + IC_EVEX_L2_XS, /* 1315 */ + IC_EVEX_L2_XD, /* 1316 */ + IC_EVEX_L2_XD, /* 1317 */ + IC_EVEX_L2_XD, /* 1318 */ + IC_EVEX_L2_XD, /* 1319 */ + IC_EVEX_L2_W, /* 1320 */ + IC_EVEX_L2_W, /* 1321 */ + IC_EVEX_L2_W_XS, /* 1322 */ + IC_EVEX_L2_W_XS, /* 1323 */ + IC_EVEX_L2_W_XD, /* 1324 */ + IC_EVEX_L2_W_XD, /* 1325 */ + IC_EVEX_L2_W_XD, /* 1326 */ + IC_EVEX_L2_W_XD, /* 1327 */ + IC_EVEX_L2_OPSIZE, /* 1328 */ + IC_EVEX_L2_OPSIZE, /* 1329 */ + IC_EVEX_L2_OPSIZE, /* 1330 */ + IC_EVEX_L2_OPSIZE, /* 1331 */ + IC_EVEX_L2_OPSIZE, /* 1332 */ + IC_EVEX_L2_OPSIZE, /* 1333 */ + IC_EVEX_L2_OPSIZE, /* 1334 */ + IC_EVEX_L2_OPSIZE, /* 1335 */ + IC_EVEX_L2_W_OPSIZE, /* 1336 */ + IC_EVEX_L2_W_OPSIZE, /* 1337 */ + IC_EVEX_L2_W_OPSIZE, /* 1338 */ + IC_EVEX_L2_W_OPSIZE, /* 1339 */ + IC_EVEX_L2_W_OPSIZE, /* 1340 */ + IC_EVEX_L2_W_OPSIZE, /* 1341 */ + IC_EVEX_L2_W_OPSIZE, /* 1342 */ + IC_EVEX_L2_W_OPSIZE, /* 1343 */ + IC_EVEX_L2, /* 1344 */ + IC_EVEX_L2, /* 1345 */ + IC_EVEX_L2_XS, /* 1346 */ + IC_EVEX_L2_XS, /* 1347 */ + IC_EVEX_L2_XD, /* 1348 */ + IC_EVEX_L2_XD, /* 1349 */ + IC_EVEX_L2_XD, /* 1350 */ + IC_EVEX_L2_XD, /* 1351 */ + IC_EVEX_L2_W, /* 1352 */ + IC_EVEX_L2_W, /* 1353 */ + IC_EVEX_L2_W_XS, /* 1354 */ + IC_EVEX_L2_W_XS, /* 1355 */ + IC_EVEX_L2_W_XD, /* 1356 */ + IC_EVEX_L2_W_XD, /* 1357 */ + IC_EVEX_L2_W_XD, /* 1358 */ + IC_EVEX_L2_W_XD, /* 1359 */ + IC_EVEX_L2_OPSIZE, /* 1360 */ + IC_EVEX_L2_OPSIZE, /* 1361 */ + IC_EVEX_L2_OPSIZE, /* 1362 */ + IC_EVEX_L2_OPSIZE, /* 1363 */ + IC_EVEX_L2_OPSIZE, /* 1364 */ + IC_EVEX_L2_OPSIZE, /* 1365 */ + IC_EVEX_L2_OPSIZE, /* 1366 */ + IC_EVEX_L2_OPSIZE, /* 1367 */ + IC_EVEX_L2_W_OPSIZE, /* 1368 */ + IC_EVEX_L2_W_OPSIZE, /* 1369 */ + IC_EVEX_L2_W_OPSIZE, /* 1370 */ + IC_EVEX_L2_W_OPSIZE, /* 1371 */ + IC_EVEX_L2_W_OPSIZE, /* 1372 */ + IC_EVEX_L2_W_OPSIZE, /* 1373 */ + IC_EVEX_L2_W_OPSIZE, /* 1374 */ + IC_EVEX_L2_W_OPSIZE, /* 1375 */ + IC_EVEX_L2, /* 1376 */ + IC_EVEX_L2, /* 1377 */ + IC_EVEX_L2_XS, /* 1378 */ + IC_EVEX_L2_XS, /* 1379 */ + IC_EVEX_L2_XD, /* 1380 */ + IC_EVEX_L2_XD, /* 1381 */ + IC_EVEX_L2_XD, /* 1382 */ + IC_EVEX_L2_XD, /* 1383 */ + IC_EVEX_L2_W, /* 1384 */ + IC_EVEX_L2_W, /* 1385 */ + IC_EVEX_L2_W_XS, /* 1386 */ + IC_EVEX_L2_W_XS, /* 1387 */ + IC_EVEX_L2_W_XD, /* 1388 */ + IC_EVEX_L2_W_XD, /* 1389 */ + IC_EVEX_L2_W_XD, /* 1390 */ + IC_EVEX_L2_W_XD, /* 1391 */ + IC_EVEX_L2_OPSIZE, /* 1392 */ + IC_EVEX_L2_OPSIZE, /* 1393 */ + IC_EVEX_L2_OPSIZE, /* 1394 */ + IC_EVEX_L2_OPSIZE, /* 1395 */ + IC_EVEX_L2_OPSIZE, /* 1396 */ + IC_EVEX_L2_OPSIZE, /* 1397 */ + IC_EVEX_L2_OPSIZE, /* 1398 */ + IC_EVEX_L2_OPSIZE, /* 1399 */ + IC_EVEX_L2_W_OPSIZE, /* 1400 */ + IC_EVEX_L2_W_OPSIZE, /* 1401 */ + IC_EVEX_L2_W_OPSIZE, /* 1402 */ + IC_EVEX_L2_W_OPSIZE, /* 1403 */ + IC_EVEX_L2_W_OPSIZE, /* 1404 */ + IC_EVEX_L2_W_OPSIZE, /* 1405 */ + IC_EVEX_L2_W_OPSIZE, /* 1406 */ + IC_EVEX_L2_W_OPSIZE, /* 1407 */ + IC_EVEX_L2, /* 1408 */ + IC_EVEX_L2, /* 1409 */ + IC_EVEX_L2_XS, /* 1410 */ + IC_EVEX_L2_XS, /* 1411 */ + IC_EVEX_L2_XD, /* 1412 */ + IC_EVEX_L2_XD, /* 1413 */ + IC_EVEX_L2_XD, /* 1414 */ + IC_EVEX_L2_XD, /* 1415 */ + IC_EVEX_L2_W, /* 1416 */ + IC_EVEX_L2_W, /* 1417 */ + IC_EVEX_L2_W_XS, /* 1418 */ + IC_EVEX_L2_W_XS, /* 1419 */ + IC_EVEX_L2_W_XD, /* 1420 */ + IC_EVEX_L2_W_XD, /* 1421 */ + IC_EVEX_L2_W_XD, /* 1422 */ + IC_EVEX_L2_W_XD, /* 1423 */ + IC_EVEX_L2_OPSIZE, /* 1424 */ + IC_EVEX_L2_OPSIZE, /* 1425 */ + IC_EVEX_L2_OPSIZE, /* 1426 */ + IC_EVEX_L2_OPSIZE, /* 1427 */ + IC_EVEX_L2_OPSIZE, /* 1428 */ + IC_EVEX_L2_OPSIZE, /* 1429 */ + IC_EVEX_L2_OPSIZE, /* 1430 */ + IC_EVEX_L2_OPSIZE, /* 1431 */ + IC_EVEX_L2_W_OPSIZE, /* 1432 */ + IC_EVEX_L2_W_OPSIZE, /* 1433 */ + IC_EVEX_L2_W_OPSIZE, /* 1434 */ + IC_EVEX_L2_W_OPSIZE, /* 1435 */ + IC_EVEX_L2_W_OPSIZE, /* 1436 */ + IC_EVEX_L2_W_OPSIZE, /* 1437 */ + IC_EVEX_L2_W_OPSIZE, /* 1438 */ + IC_EVEX_L2_W_OPSIZE, /* 1439 */ + IC_EVEX_L2, /* 1440 */ + IC_EVEX_L2, /* 1441 */ + IC_EVEX_L2_XS, /* 1442 */ + IC_EVEX_L2_XS, /* 1443 */ + IC_EVEX_L2_XD, /* 1444 */ + IC_EVEX_L2_XD, /* 1445 */ + IC_EVEX_L2_XD, /* 1446 */ + IC_EVEX_L2_XD, /* 1447 */ + IC_EVEX_L2_W, /* 1448 */ + IC_EVEX_L2_W, /* 1449 */ + IC_EVEX_L2_W_XS, /* 1450 */ + IC_EVEX_L2_W_XS, /* 1451 */ + IC_EVEX_L2_W_XD, /* 1452 */ + IC_EVEX_L2_W_XD, /* 1453 */ + IC_EVEX_L2_W_XD, /* 1454 */ + IC_EVEX_L2_W_XD, /* 1455 */ + IC_EVEX_L2_OPSIZE, /* 1456 */ + IC_EVEX_L2_OPSIZE, /* 1457 */ + IC_EVEX_L2_OPSIZE, /* 1458 */ + IC_EVEX_L2_OPSIZE, /* 1459 */ + IC_EVEX_L2_OPSIZE, /* 1460 */ + IC_EVEX_L2_OPSIZE, /* 1461 */ + IC_EVEX_L2_OPSIZE, /* 1462 */ + IC_EVEX_L2_OPSIZE, /* 1463 */ + IC_EVEX_L2_W_OPSIZE, /* 1464 */ + IC_EVEX_L2_W_OPSIZE, /* 1465 */ + IC_EVEX_L2_W_OPSIZE, /* 1466 */ + IC_EVEX_L2_W_OPSIZE, /* 1467 */ + IC_EVEX_L2_W_OPSIZE, /* 1468 */ + IC_EVEX_L2_W_OPSIZE, /* 1469 */ + IC_EVEX_L2_W_OPSIZE, /* 1470 */ + IC_EVEX_L2_W_OPSIZE, /* 1471 */ + IC_EVEX_L2, /* 1472 */ + IC_EVEX_L2, /* 1473 */ + IC_EVEX_L2_XS, /* 1474 */ + IC_EVEX_L2_XS, /* 1475 */ + IC_EVEX_L2_XD, /* 1476 */ + IC_EVEX_L2_XD, /* 1477 */ + IC_EVEX_L2_XD, /* 1478 */ + IC_EVEX_L2_XD, /* 1479 */ + IC_EVEX_L2_W, /* 1480 */ + IC_EVEX_L2_W, /* 1481 */ + IC_EVEX_L2_W_XS, /* 1482 */ + IC_EVEX_L2_W_XS, /* 1483 */ + IC_EVEX_L2_W_XD, /* 1484 */ + IC_EVEX_L2_W_XD, /* 1485 */ + IC_EVEX_L2_W_XD, /* 1486 */ + IC_EVEX_L2_W_XD, /* 1487 */ + IC_EVEX_L2_OPSIZE, /* 1488 */ + IC_EVEX_L2_OPSIZE, /* 1489 */ + IC_EVEX_L2_OPSIZE, /* 1490 */ + IC_EVEX_L2_OPSIZE, /* 1491 */ + IC_EVEX_L2_OPSIZE, /* 1492 */ + IC_EVEX_L2_OPSIZE, /* 1493 */ + IC_EVEX_L2_OPSIZE, /* 1494 */ + IC_EVEX_L2_OPSIZE, /* 1495 */ + IC_EVEX_L2_W_OPSIZE, /* 1496 */ + IC_EVEX_L2_W_OPSIZE, /* 1497 */ + IC_EVEX_L2_W_OPSIZE, /* 1498 */ + IC_EVEX_L2_W_OPSIZE, /* 1499 */ + IC_EVEX_L2_W_OPSIZE, /* 1500 */ + IC_EVEX_L2_W_OPSIZE, /* 1501 */ + IC_EVEX_L2_W_OPSIZE, /* 1502 */ + IC_EVEX_L2_W_OPSIZE, /* 1503 */ + IC_EVEX_L2, /* 1504 */ + IC_EVEX_L2, /* 1505 */ + IC_EVEX_L2_XS, /* 1506 */ + IC_EVEX_L2_XS, /* 1507 */ + IC_EVEX_L2_XD, /* 1508 */ + IC_EVEX_L2_XD, /* 1509 */ + IC_EVEX_L2_XD, /* 1510 */ + IC_EVEX_L2_XD, /* 1511 */ + IC_EVEX_L2_W, /* 1512 */ + IC_EVEX_L2_W, /* 1513 */ + IC_EVEX_L2_W_XS, /* 1514 */ + IC_EVEX_L2_W_XS, /* 1515 */ + IC_EVEX_L2_W_XD, /* 1516 */ + IC_EVEX_L2_W_XD, /* 1517 */ + IC_EVEX_L2_W_XD, /* 1518 */ + IC_EVEX_L2_W_XD, /* 1519 */ + IC_EVEX_L2_OPSIZE, /* 1520 */ + IC_EVEX_L2_OPSIZE, /* 1521 */ + IC_EVEX_L2_OPSIZE, /* 1522 */ + IC_EVEX_L2_OPSIZE, /* 1523 */ + IC_EVEX_L2_OPSIZE, /* 1524 */ + IC_EVEX_L2_OPSIZE, /* 1525 */ + IC_EVEX_L2_OPSIZE, /* 1526 */ + IC_EVEX_L2_OPSIZE, /* 1527 */ + IC_EVEX_L2_W_OPSIZE, /* 1528 */ + IC_EVEX_L2_W_OPSIZE, /* 1529 */ + IC_EVEX_L2_W_OPSIZE, /* 1530 */ + IC_EVEX_L2_W_OPSIZE, /* 1531 */ + IC_EVEX_L2_W_OPSIZE, /* 1532 */ + IC_EVEX_L2_W_OPSIZE, /* 1533 */ + IC_EVEX_L2_W_OPSIZE, /* 1534 */ + IC_EVEX_L2_W_OPSIZE, /* 1535 */ + IC, /* 1536 */ + IC_64BIT, /* 1537 */ + IC_XS, /* 1538 */ + IC_64BIT_XS, /* 1539 */ + IC_XD, /* 1540 */ + IC_64BIT_XD, /* 1541 */ + IC_XS, /* 1542 */ + IC_64BIT_XS, /* 1543 */ + IC, /* 1544 */ + IC_64BIT_REXW, /* 1545 */ + IC_XS, /* 1546 */ + IC_64BIT_REXW_XS, /* 1547 */ + IC_XD, /* 1548 */ + IC_64BIT_REXW_XD, /* 1549 */ + IC_XS, /* 1550 */ + IC_64BIT_REXW_XS, /* 1551 */ + IC_OPSIZE, /* 1552 */ + IC_64BIT_OPSIZE, /* 1553 */ + IC_XS_OPSIZE, /* 1554 */ + IC_64BIT_XS_OPSIZE, /* 1555 */ + IC_XD_OPSIZE, /* 1556 */ + IC_64BIT_XD_OPSIZE, /* 1557 */ + IC_XS_OPSIZE, /* 1558 */ + IC_64BIT_XD_OPSIZE, /* 1559 */ + IC_OPSIZE, /* 1560 */ + IC_64BIT_REXW_OPSIZE, /* 1561 */ + IC_XS_OPSIZE, /* 1562 */ + IC_64BIT_REXW_XS, /* 1563 */ + IC_XD_OPSIZE, /* 1564 */ + IC_64BIT_REXW_XD, /* 1565 */ + IC_XS_OPSIZE, /* 1566 */ + IC_64BIT_REXW_XS, /* 1567 */ + IC_ADSIZE, /* 1568 */ + IC_64BIT_ADSIZE, /* 1569 */ + IC_XS_ADSIZE, /* 1570 */ + IC_64BIT_XS_ADSIZE, /* 1571 */ + IC_XD_ADSIZE, /* 1572 */ + IC_64BIT_XD_ADSIZE, /* 1573 */ + IC_XS_ADSIZE, /* 1574 */ + IC_64BIT_XD_ADSIZE, /* 1575 */ + IC_ADSIZE, /* 1576 */ + IC_64BIT_REXW_ADSIZE, /* 1577 */ + IC_XS_ADSIZE, /* 1578 */ + IC_64BIT_REXW_XS, /* 1579 */ + IC_XD_ADSIZE, /* 1580 */ + IC_64BIT_REXW_XD, /* 1581 */ + IC_XS_ADSIZE, /* 1582 */ + IC_64BIT_REXW_XS, /* 1583 */ + IC_OPSIZE_ADSIZE, /* 1584 */ + IC_64BIT_OPSIZE_ADSIZE, /* 1585 */ + IC_XS_OPSIZE, /* 1586 */ + IC_64BIT_XS_OPSIZE, /* 1587 */ + IC_XD_OPSIZE, /* 1588 */ + IC_64BIT_XD_OPSIZE, /* 1589 */ + IC_XS_OPSIZE, /* 1590 */ + IC_64BIT_XD_OPSIZE, /* 1591 */ + IC_OPSIZE_ADSIZE, /* 1592 */ + IC_64BIT_REXW_OPSIZE, /* 1593 */ + IC_XS_OPSIZE, /* 1594 */ + IC_64BIT_REXW_XS, /* 1595 */ + IC_XD_OPSIZE, /* 1596 */ + IC_64BIT_REXW_XD, /* 1597 */ + IC_XS_OPSIZE, /* 1598 */ + IC_64BIT_REXW_XS, /* 1599 */ + IC_VEX, /* 1600 */ + IC_VEX, /* 1601 */ + IC_VEX_XS, /* 1602 */ + IC_VEX_XS, /* 1603 */ + IC_VEX_XD, /* 1604 */ + IC_VEX_XD, /* 1605 */ + IC_VEX_XD, /* 1606 */ + IC_VEX_XD, /* 1607 */ + IC_VEX_W, /* 1608 */ + IC_VEX_W, /* 1609 */ + IC_VEX_W_XS, /* 1610 */ + IC_VEX_W_XS, /* 1611 */ + IC_VEX_W_XD, /* 1612 */ + IC_VEX_W_XD, /* 1613 */ + IC_VEX_W_XD, /* 1614 */ + IC_VEX_W_XD, /* 1615 */ + IC_VEX_OPSIZE, /* 1616 */ + IC_VEX_OPSIZE, /* 1617 */ + IC_VEX_OPSIZE, /* 1618 */ + IC_VEX_OPSIZE, /* 1619 */ + IC_VEX_OPSIZE, /* 1620 */ + IC_VEX_OPSIZE, /* 1621 */ + IC_VEX_OPSIZE, /* 1622 */ + IC_VEX_OPSIZE, /* 1623 */ + IC_VEX_W_OPSIZE, /* 1624 */ + IC_VEX_W_OPSIZE, /* 1625 */ + IC_VEX_W_OPSIZE, /* 1626 */ + IC_VEX_W_OPSIZE, /* 1627 */ + IC_VEX_W_OPSIZE, /* 1628 */ + IC_VEX_W_OPSIZE, /* 1629 */ + IC_VEX_W_OPSIZE, /* 1630 */ + IC_VEX_W_OPSIZE, /* 1631 */ + IC_VEX, /* 1632 */ + IC_VEX, /* 1633 */ + IC_VEX_XS, /* 1634 */ + IC_VEX_XS, /* 1635 */ + IC_VEX_XD, /* 1636 */ + IC_VEX_XD, /* 1637 */ + IC_VEX_XD, /* 1638 */ + IC_VEX_XD, /* 1639 */ + IC_VEX_W, /* 1640 */ + IC_VEX_W, /* 1641 */ + IC_VEX_W_XS, /* 1642 */ + IC_VEX_W_XS, /* 1643 */ + IC_VEX_W_XD, /* 1644 */ + IC_VEX_W_XD, /* 1645 */ + IC_VEX_W_XD, /* 1646 */ + IC_VEX_W_XD, /* 1647 */ + IC_VEX_OPSIZE, /* 1648 */ + IC_VEX_OPSIZE, /* 1649 */ + IC_VEX_OPSIZE, /* 1650 */ + IC_VEX_OPSIZE, /* 1651 */ + IC_VEX_OPSIZE, /* 1652 */ + IC_VEX_OPSIZE, /* 1653 */ + IC_VEX_OPSIZE, /* 1654 */ + IC_VEX_OPSIZE, /* 1655 */ + IC_VEX_W_OPSIZE, /* 1656 */ + IC_VEX_W_OPSIZE, /* 1657 */ + IC_VEX_W_OPSIZE, /* 1658 */ + IC_VEX_W_OPSIZE, /* 1659 */ + IC_VEX_W_OPSIZE, /* 1660 */ + IC_VEX_W_OPSIZE, /* 1661 */ + IC_VEX_W_OPSIZE, /* 1662 */ + IC_VEX_W_OPSIZE, /* 1663 */ + IC_VEX_L, /* 1664 */ + IC_VEX_L, /* 1665 */ + IC_VEX_L_XS, /* 1666 */ + IC_VEX_L_XS, /* 1667 */ + IC_VEX_L_XD, /* 1668 */ + IC_VEX_L_XD, /* 1669 */ + IC_VEX_L_XD, /* 1670 */ + IC_VEX_L_XD, /* 1671 */ + IC_VEX_L_W, /* 1672 */ + IC_VEX_L_W, /* 1673 */ + IC_VEX_L_W_XS, /* 1674 */ + IC_VEX_L_W_XS, /* 1675 */ + IC_VEX_L_W_XD, /* 1676 */ + IC_VEX_L_W_XD, /* 1677 */ + IC_VEX_L_W_XD, /* 1678 */ + IC_VEX_L_W_XD, /* 1679 */ + IC_VEX_L_OPSIZE, /* 1680 */ + IC_VEX_L_OPSIZE, /* 1681 */ + IC_VEX_L_OPSIZE, /* 1682 */ + IC_VEX_L_OPSIZE, /* 1683 */ + IC_VEX_L_OPSIZE, /* 1684 */ + IC_VEX_L_OPSIZE, /* 1685 */ + IC_VEX_L_OPSIZE, /* 1686 */ + IC_VEX_L_OPSIZE, /* 1687 */ + IC_VEX_L_W_OPSIZE, /* 1688 */ + IC_VEX_L_W_OPSIZE, /* 1689 */ + IC_VEX_L_W_OPSIZE, /* 1690 */ + IC_VEX_L_W_OPSIZE, /* 1691 */ + IC_VEX_L_W_OPSIZE, /* 1692 */ + IC_VEX_L_W_OPSIZE, /* 1693 */ + IC_VEX_L_W_OPSIZE, /* 1694 */ + IC_VEX_L_W_OPSIZE, /* 1695 */ + IC_VEX_L, /* 1696 */ + IC_VEX_L, /* 1697 */ + IC_VEX_L_XS, /* 1698 */ + IC_VEX_L_XS, /* 1699 */ + IC_VEX_L_XD, /* 1700 */ + IC_VEX_L_XD, /* 1701 */ + IC_VEX_L_XD, /* 1702 */ + IC_VEX_L_XD, /* 1703 */ + IC_VEX_L_W, /* 1704 */ + IC_VEX_L_W, /* 1705 */ + IC_VEX_L_W_XS, /* 1706 */ + IC_VEX_L_W_XS, /* 1707 */ + IC_VEX_L_W_XD, /* 1708 */ + IC_VEX_L_W_XD, /* 1709 */ + IC_VEX_L_W_XD, /* 1710 */ + IC_VEX_L_W_XD, /* 1711 */ + IC_VEX_L_OPSIZE, /* 1712 */ + IC_VEX_L_OPSIZE, /* 1713 */ + IC_VEX_L_OPSIZE, /* 1714 */ + IC_VEX_L_OPSIZE, /* 1715 */ + IC_VEX_L_OPSIZE, /* 1716 */ + IC_VEX_L_OPSIZE, /* 1717 */ + IC_VEX_L_OPSIZE, /* 1718 */ + IC_VEX_L_OPSIZE, /* 1719 */ + IC_VEX_L_W_OPSIZE, /* 1720 */ + IC_VEX_L_W_OPSIZE, /* 1721 */ + IC_VEX_L_W_OPSIZE, /* 1722 */ + IC_VEX_L_W_OPSIZE, /* 1723 */ + IC_VEX_L_W_OPSIZE, /* 1724 */ + IC_VEX_L_W_OPSIZE, /* 1725 */ + IC_VEX_L_W_OPSIZE, /* 1726 */ + IC_VEX_L_W_OPSIZE, /* 1727 */ + IC_VEX_L, /* 1728 */ + IC_VEX_L, /* 1729 */ + IC_VEX_L_XS, /* 1730 */ + IC_VEX_L_XS, /* 1731 */ + IC_VEX_L_XD, /* 1732 */ + IC_VEX_L_XD, /* 1733 */ + IC_VEX_L_XD, /* 1734 */ + IC_VEX_L_XD, /* 1735 */ + IC_VEX_L_W, /* 1736 */ + IC_VEX_L_W, /* 1737 */ + IC_VEX_L_W_XS, /* 1738 */ + IC_VEX_L_W_XS, /* 1739 */ + IC_VEX_L_W_XD, /* 1740 */ + IC_VEX_L_W_XD, /* 1741 */ + IC_VEX_L_W_XD, /* 1742 */ + IC_VEX_L_W_XD, /* 1743 */ + IC_VEX_L_OPSIZE, /* 1744 */ + IC_VEX_L_OPSIZE, /* 1745 */ + IC_VEX_L_OPSIZE, /* 1746 */ + IC_VEX_L_OPSIZE, /* 1747 */ + IC_VEX_L_OPSIZE, /* 1748 */ + IC_VEX_L_OPSIZE, /* 1749 */ + IC_VEX_L_OPSIZE, /* 1750 */ + IC_VEX_L_OPSIZE, /* 1751 */ + IC_VEX_L_W_OPSIZE, /* 1752 */ + IC_VEX_L_W_OPSIZE, /* 1753 */ + IC_VEX_L_W_OPSIZE, /* 1754 */ + IC_VEX_L_W_OPSIZE, /* 1755 */ + IC_VEX_L_W_OPSIZE, /* 1756 */ + IC_VEX_L_W_OPSIZE, /* 1757 */ + IC_VEX_L_W_OPSIZE, /* 1758 */ + IC_VEX_L_W_OPSIZE, /* 1759 */ + IC_VEX_L, /* 1760 */ + IC_VEX_L, /* 1761 */ + IC_VEX_L_XS, /* 1762 */ + IC_VEX_L_XS, /* 1763 */ + IC_VEX_L_XD, /* 1764 */ + IC_VEX_L_XD, /* 1765 */ + IC_VEX_L_XD, /* 1766 */ + IC_VEX_L_XD, /* 1767 */ + IC_VEX_L_W, /* 1768 */ + IC_VEX_L_W, /* 1769 */ + IC_VEX_L_W_XS, /* 1770 */ + IC_VEX_L_W_XS, /* 1771 */ + IC_VEX_L_W_XD, /* 1772 */ + IC_VEX_L_W_XD, /* 1773 */ + IC_VEX_L_W_XD, /* 1774 */ + IC_VEX_L_W_XD, /* 1775 */ + IC_VEX_L_OPSIZE, /* 1776 */ + IC_VEX_L_OPSIZE, /* 1777 */ + IC_VEX_L_OPSIZE, /* 1778 */ + IC_VEX_L_OPSIZE, /* 1779 */ + IC_VEX_L_OPSIZE, /* 1780 */ + IC_VEX_L_OPSIZE, /* 1781 */ + IC_VEX_L_OPSIZE, /* 1782 */ + IC_VEX_L_OPSIZE, /* 1783 */ + IC_VEX_L_W_OPSIZE, /* 1784 */ + IC_VEX_L_W_OPSIZE, /* 1785 */ + IC_VEX_L_W_OPSIZE, /* 1786 */ + IC_VEX_L_W_OPSIZE, /* 1787 */ + IC_VEX_L_W_OPSIZE, /* 1788 */ + IC_VEX_L_W_OPSIZE, /* 1789 */ + IC_VEX_L_W_OPSIZE, /* 1790 */ + IC_VEX_L_W_OPSIZE, /* 1791 */ + IC_EVEX_L2, /* 1792 */ + IC_EVEX_L2, /* 1793 */ + IC_EVEX_L2_XS, /* 1794 */ + IC_EVEX_L2_XS, /* 1795 */ + IC_EVEX_L2_XD, /* 1796 */ + IC_EVEX_L2_XD, /* 1797 */ + IC_EVEX_L2_XD, /* 1798 */ + IC_EVEX_L2_XD, /* 1799 */ + IC_EVEX_L2_W, /* 1800 */ + IC_EVEX_L2_W, /* 1801 */ + IC_EVEX_L2_W_XS, /* 1802 */ + IC_EVEX_L2_W_XS, /* 1803 */ + IC_EVEX_L2_W_XD, /* 1804 */ + IC_EVEX_L2_W_XD, /* 1805 */ + IC_EVEX_L2_W_XD, /* 1806 */ + IC_EVEX_L2_W_XD, /* 1807 */ + IC_EVEX_L2_OPSIZE, /* 1808 */ + IC_EVEX_L2_OPSIZE, /* 1809 */ + IC_EVEX_L2_OPSIZE, /* 1810 */ + IC_EVEX_L2_OPSIZE, /* 1811 */ + IC_EVEX_L2_OPSIZE, /* 1812 */ + IC_EVEX_L2_OPSIZE, /* 1813 */ + IC_EVEX_L2_OPSIZE, /* 1814 */ + IC_EVEX_L2_OPSIZE, /* 1815 */ + IC_EVEX_L2_W_OPSIZE, /* 1816 */ + IC_EVEX_L2_W_OPSIZE, /* 1817 */ + IC_EVEX_L2_W_OPSIZE, /* 1818 */ + IC_EVEX_L2_W_OPSIZE, /* 1819 */ + IC_EVEX_L2_W_OPSIZE, /* 1820 */ + IC_EVEX_L2_W_OPSIZE, /* 1821 */ + IC_EVEX_L2_W_OPSIZE, /* 1822 */ + IC_EVEX_L2_W_OPSIZE, /* 1823 */ + IC_EVEX_L2, /* 1824 */ + IC_EVEX_L2, /* 1825 */ + IC_EVEX_L2_XS, /* 1826 */ + IC_EVEX_L2_XS, /* 1827 */ + IC_EVEX_L2_XD, /* 1828 */ + IC_EVEX_L2_XD, /* 1829 */ + IC_EVEX_L2_XD, /* 1830 */ + IC_EVEX_L2_XD, /* 1831 */ + IC_EVEX_L2_W, /* 1832 */ + IC_EVEX_L2_W, /* 1833 */ + IC_EVEX_L2_W_XS, /* 1834 */ + IC_EVEX_L2_W_XS, /* 1835 */ + IC_EVEX_L2_W_XD, /* 1836 */ + IC_EVEX_L2_W_XD, /* 1837 */ + IC_EVEX_L2_W_XD, /* 1838 */ + IC_EVEX_L2_W_XD, /* 1839 */ + IC_EVEX_L2_OPSIZE, /* 1840 */ + IC_EVEX_L2_OPSIZE, /* 1841 */ + IC_EVEX_L2_OPSIZE, /* 1842 */ + IC_EVEX_L2_OPSIZE, /* 1843 */ + IC_EVEX_L2_OPSIZE, /* 1844 */ + IC_EVEX_L2_OPSIZE, /* 1845 */ + IC_EVEX_L2_OPSIZE, /* 1846 */ + IC_EVEX_L2_OPSIZE, /* 1847 */ + IC_EVEX_L2_W_OPSIZE, /* 1848 */ + IC_EVEX_L2_W_OPSIZE, /* 1849 */ + IC_EVEX_L2_W_OPSIZE, /* 1850 */ + IC_EVEX_L2_W_OPSIZE, /* 1851 */ + IC_EVEX_L2_W_OPSIZE, /* 1852 */ + IC_EVEX_L2_W_OPSIZE, /* 1853 */ + IC_EVEX_L2_W_OPSIZE, /* 1854 */ + IC_EVEX_L2_W_OPSIZE, /* 1855 */ + IC_EVEX_L2, /* 1856 */ + IC_EVEX_L2, /* 1857 */ + IC_EVEX_L2_XS, /* 1858 */ + IC_EVEX_L2_XS, /* 1859 */ + IC_EVEX_L2_XD, /* 1860 */ + IC_EVEX_L2_XD, /* 1861 */ + IC_EVEX_L2_XD, /* 1862 */ + IC_EVEX_L2_XD, /* 1863 */ + IC_EVEX_L2_W, /* 1864 */ + IC_EVEX_L2_W, /* 1865 */ + IC_EVEX_L2_W_XS, /* 1866 */ + IC_EVEX_L2_W_XS, /* 1867 */ + IC_EVEX_L2_W_XD, /* 1868 */ + IC_EVEX_L2_W_XD, /* 1869 */ + IC_EVEX_L2_W_XD, /* 1870 */ + IC_EVEX_L2_W_XD, /* 1871 */ + IC_EVEX_L2_OPSIZE, /* 1872 */ + IC_EVEX_L2_OPSIZE, /* 1873 */ + IC_EVEX_L2_OPSIZE, /* 1874 */ + IC_EVEX_L2_OPSIZE, /* 1875 */ + IC_EVEX_L2_OPSIZE, /* 1876 */ + IC_EVEX_L2_OPSIZE, /* 1877 */ + IC_EVEX_L2_OPSIZE, /* 1878 */ + IC_EVEX_L2_OPSIZE, /* 1879 */ + IC_EVEX_L2_W_OPSIZE, /* 1880 */ + IC_EVEX_L2_W_OPSIZE, /* 1881 */ + IC_EVEX_L2_W_OPSIZE, /* 1882 */ + IC_EVEX_L2_W_OPSIZE, /* 1883 */ + IC_EVEX_L2_W_OPSIZE, /* 1884 */ + IC_EVEX_L2_W_OPSIZE, /* 1885 */ + IC_EVEX_L2_W_OPSIZE, /* 1886 */ + IC_EVEX_L2_W_OPSIZE, /* 1887 */ + IC_EVEX_L2, /* 1888 */ + IC_EVEX_L2, /* 1889 */ + IC_EVEX_L2_XS, /* 1890 */ + IC_EVEX_L2_XS, /* 1891 */ + IC_EVEX_L2_XD, /* 1892 */ + IC_EVEX_L2_XD, /* 1893 */ + IC_EVEX_L2_XD, /* 1894 */ + IC_EVEX_L2_XD, /* 1895 */ + IC_EVEX_L2_W, /* 1896 */ + IC_EVEX_L2_W, /* 1897 */ + IC_EVEX_L2_W_XS, /* 1898 */ + IC_EVEX_L2_W_XS, /* 1899 */ + IC_EVEX_L2_W_XD, /* 1900 */ + IC_EVEX_L2_W_XD, /* 1901 */ + IC_EVEX_L2_W_XD, /* 1902 */ + IC_EVEX_L2_W_XD, /* 1903 */ + IC_EVEX_L2_OPSIZE, /* 1904 */ + IC_EVEX_L2_OPSIZE, /* 1905 */ + IC_EVEX_L2_OPSIZE, /* 1906 */ + IC_EVEX_L2_OPSIZE, /* 1907 */ + IC_EVEX_L2_OPSIZE, /* 1908 */ + IC_EVEX_L2_OPSIZE, /* 1909 */ + IC_EVEX_L2_OPSIZE, /* 1910 */ + IC_EVEX_L2_OPSIZE, /* 1911 */ + IC_EVEX_L2_W_OPSIZE, /* 1912 */ + IC_EVEX_L2_W_OPSIZE, /* 1913 */ + IC_EVEX_L2_W_OPSIZE, /* 1914 */ + IC_EVEX_L2_W_OPSIZE, /* 1915 */ + IC_EVEX_L2_W_OPSIZE, /* 1916 */ + IC_EVEX_L2_W_OPSIZE, /* 1917 */ + IC_EVEX_L2_W_OPSIZE, /* 1918 */ + IC_EVEX_L2_W_OPSIZE, /* 1919 */ + IC_EVEX_L2, /* 1920 */ + IC_EVEX_L2, /* 1921 */ + IC_EVEX_L2_XS, /* 1922 */ + IC_EVEX_L2_XS, /* 1923 */ + IC_EVEX_L2_XD, /* 1924 */ + IC_EVEX_L2_XD, /* 1925 */ + IC_EVEX_L2_XD, /* 1926 */ + IC_EVEX_L2_XD, /* 1927 */ + IC_EVEX_L2_W, /* 1928 */ + IC_EVEX_L2_W, /* 1929 */ + IC_EVEX_L2_W_XS, /* 1930 */ + IC_EVEX_L2_W_XS, /* 1931 */ + IC_EVEX_L2_W_XD, /* 1932 */ + IC_EVEX_L2_W_XD, /* 1933 */ + IC_EVEX_L2_W_XD, /* 1934 */ + IC_EVEX_L2_W_XD, /* 1935 */ + IC_EVEX_L2_OPSIZE, /* 1936 */ + IC_EVEX_L2_OPSIZE, /* 1937 */ + IC_EVEX_L2_OPSIZE, /* 1938 */ + IC_EVEX_L2_OPSIZE, /* 1939 */ + IC_EVEX_L2_OPSIZE, /* 1940 */ + IC_EVEX_L2_OPSIZE, /* 1941 */ + IC_EVEX_L2_OPSIZE, /* 1942 */ + IC_EVEX_L2_OPSIZE, /* 1943 */ + IC_EVEX_L2_W_OPSIZE, /* 1944 */ + IC_EVEX_L2_W_OPSIZE, /* 1945 */ + IC_EVEX_L2_W_OPSIZE, /* 1946 */ + IC_EVEX_L2_W_OPSIZE, /* 1947 */ + IC_EVEX_L2_W_OPSIZE, /* 1948 */ + IC_EVEX_L2_W_OPSIZE, /* 1949 */ + IC_EVEX_L2_W_OPSIZE, /* 1950 */ + IC_EVEX_L2_W_OPSIZE, /* 1951 */ + IC_EVEX_L2, /* 1952 */ + IC_EVEX_L2, /* 1953 */ + IC_EVEX_L2_XS, /* 1954 */ + IC_EVEX_L2_XS, /* 1955 */ + IC_EVEX_L2_XD, /* 1956 */ + IC_EVEX_L2_XD, /* 1957 */ + IC_EVEX_L2_XD, /* 1958 */ + IC_EVEX_L2_XD, /* 1959 */ + IC_EVEX_L2_W, /* 1960 */ + IC_EVEX_L2_W, /* 1961 */ + IC_EVEX_L2_W_XS, /* 1962 */ + IC_EVEX_L2_W_XS, /* 1963 */ + IC_EVEX_L2_W_XD, /* 1964 */ + IC_EVEX_L2_W_XD, /* 1965 */ + IC_EVEX_L2_W_XD, /* 1966 */ + IC_EVEX_L2_W_XD, /* 1967 */ + IC_EVEX_L2_OPSIZE, /* 1968 */ + IC_EVEX_L2_OPSIZE, /* 1969 */ + IC_EVEX_L2_OPSIZE, /* 1970 */ + IC_EVEX_L2_OPSIZE, /* 1971 */ + IC_EVEX_L2_OPSIZE, /* 1972 */ + IC_EVEX_L2_OPSIZE, /* 1973 */ + IC_EVEX_L2_OPSIZE, /* 1974 */ + IC_EVEX_L2_OPSIZE, /* 1975 */ + IC_EVEX_L2_W_OPSIZE, /* 1976 */ + IC_EVEX_L2_W_OPSIZE, /* 1977 */ + IC_EVEX_L2_W_OPSIZE, /* 1978 */ + IC_EVEX_L2_W_OPSIZE, /* 1979 */ + IC_EVEX_L2_W_OPSIZE, /* 1980 */ + IC_EVEX_L2_W_OPSIZE, /* 1981 */ + IC_EVEX_L2_W_OPSIZE, /* 1982 */ + IC_EVEX_L2_W_OPSIZE, /* 1983 */ + IC_EVEX_L2, /* 1984 */ + IC_EVEX_L2, /* 1985 */ + IC_EVEX_L2_XS, /* 1986 */ + IC_EVEX_L2_XS, /* 1987 */ + IC_EVEX_L2_XD, /* 1988 */ + IC_EVEX_L2_XD, /* 1989 */ + IC_EVEX_L2_XD, /* 1990 */ + IC_EVEX_L2_XD, /* 1991 */ + IC_EVEX_L2_W, /* 1992 */ + IC_EVEX_L2_W, /* 1993 */ + IC_EVEX_L2_W_XS, /* 1994 */ + IC_EVEX_L2_W_XS, /* 1995 */ + IC_EVEX_L2_W_XD, /* 1996 */ + IC_EVEX_L2_W_XD, /* 1997 */ + IC_EVEX_L2_W_XD, /* 1998 */ + IC_EVEX_L2_W_XD, /* 1999 */ + IC_EVEX_L2_OPSIZE, /* 2000 */ + IC_EVEX_L2_OPSIZE, /* 2001 */ + IC_EVEX_L2_OPSIZE, /* 2002 */ + IC_EVEX_L2_OPSIZE, /* 2003 */ + IC_EVEX_L2_OPSIZE, /* 2004 */ + IC_EVEX_L2_OPSIZE, /* 2005 */ + IC_EVEX_L2_OPSIZE, /* 2006 */ + IC_EVEX_L2_OPSIZE, /* 2007 */ + IC_EVEX_L2_W_OPSIZE, /* 2008 */ + IC_EVEX_L2_W_OPSIZE, /* 2009 */ + IC_EVEX_L2_W_OPSIZE, /* 2010 */ + IC_EVEX_L2_W_OPSIZE, /* 2011 */ + IC_EVEX_L2_W_OPSIZE, /* 2012 */ + IC_EVEX_L2_W_OPSIZE, /* 2013 */ + IC_EVEX_L2_W_OPSIZE, /* 2014 */ + IC_EVEX_L2_W_OPSIZE, /* 2015 */ + IC_EVEX_L2, /* 2016 */ + IC_EVEX_L2, /* 2017 */ + IC_EVEX_L2_XS, /* 2018 */ + IC_EVEX_L2_XS, /* 2019 */ + IC_EVEX_L2_XD, /* 2020 */ + IC_EVEX_L2_XD, /* 2021 */ + IC_EVEX_L2_XD, /* 2022 */ + IC_EVEX_L2_XD, /* 2023 */ + IC_EVEX_L2_W, /* 2024 */ + IC_EVEX_L2_W, /* 2025 */ + IC_EVEX_L2_W_XS, /* 2026 */ + IC_EVEX_L2_W_XS, /* 2027 */ + IC_EVEX_L2_W_XD, /* 2028 */ + IC_EVEX_L2_W_XD, /* 2029 */ + IC_EVEX_L2_W_XD, /* 2030 */ + IC_EVEX_L2_W_XD, /* 2031 */ + IC_EVEX_L2_OPSIZE, /* 2032 */ + IC_EVEX_L2_OPSIZE, /* 2033 */ + IC_EVEX_L2_OPSIZE, /* 2034 */ + IC_EVEX_L2_OPSIZE, /* 2035 */ + IC_EVEX_L2_OPSIZE, /* 2036 */ + IC_EVEX_L2_OPSIZE, /* 2037 */ + IC_EVEX_L2_OPSIZE, /* 2038 */ + IC_EVEX_L2_OPSIZE, /* 2039 */ + IC_EVEX_L2_W_OPSIZE, /* 2040 */ + IC_EVEX_L2_W_OPSIZE, /* 2041 */ + IC_EVEX_L2_W_OPSIZE, /* 2042 */ + IC_EVEX_L2_W_OPSIZE, /* 2043 */ + IC_EVEX_L2_W_OPSIZE, /* 2044 */ + IC_EVEX_L2_W_OPSIZE, /* 2045 */ + IC_EVEX_L2_W_OPSIZE, /* 2046 */ + IC_EVEX_L2_W_OPSIZE, /* 2047 */ + IC, /* 2048 */ + IC_64BIT, /* 2049 */ + IC_XS, /* 2050 */ + IC_64BIT_XS, /* 2051 */ + IC_XD, /* 2052 */ + IC_64BIT_XD, /* 2053 */ + IC_XS, /* 2054 */ + IC_64BIT_XS, /* 2055 */ + IC, /* 2056 */ + IC_64BIT_REXW, /* 2057 */ + IC_XS, /* 2058 */ + IC_64BIT_REXW_XS, /* 2059 */ + IC_XD, /* 2060 */ + IC_64BIT_REXW_XD, /* 2061 */ + IC_XS, /* 2062 */ + IC_64BIT_REXW_XS, /* 2063 */ + IC_OPSIZE, /* 2064 */ + IC_64BIT_OPSIZE, /* 2065 */ + IC_XS_OPSIZE, /* 2066 */ + IC_64BIT_XS_OPSIZE, /* 2067 */ + IC_XD_OPSIZE, /* 2068 */ + IC_64BIT_XD_OPSIZE, /* 2069 */ + IC_XS_OPSIZE, /* 2070 */ + IC_64BIT_XD_OPSIZE, /* 2071 */ + IC_OPSIZE, /* 2072 */ + IC_64BIT_REXW_OPSIZE, /* 2073 */ + IC_XS_OPSIZE, /* 2074 */ + IC_64BIT_REXW_XS, /* 2075 */ + IC_XD_OPSIZE, /* 2076 */ + IC_64BIT_REXW_XD, /* 2077 */ + IC_XS_OPSIZE, /* 2078 */ + IC_64BIT_REXW_XS, /* 2079 */ + IC_ADSIZE, /* 2080 */ + IC_64BIT_ADSIZE, /* 2081 */ + IC_XS_ADSIZE, /* 2082 */ + IC_64BIT_XS_ADSIZE, /* 2083 */ + IC_XD_ADSIZE, /* 2084 */ + IC_64BIT_XD_ADSIZE, /* 2085 */ + IC_XS_ADSIZE, /* 2086 */ + IC_64BIT_XD_ADSIZE, /* 2087 */ + IC_ADSIZE, /* 2088 */ + IC_64BIT_REXW_ADSIZE, /* 2089 */ + IC_XS_ADSIZE, /* 2090 */ + IC_64BIT_REXW_XS, /* 2091 */ + IC_XD_ADSIZE, /* 2092 */ + IC_64BIT_REXW_XD, /* 2093 */ + IC_XS_ADSIZE, /* 2094 */ + IC_64BIT_REXW_XS, /* 2095 */ + IC_OPSIZE_ADSIZE, /* 2096 */ + IC_64BIT_OPSIZE_ADSIZE, /* 2097 */ + IC_XS_OPSIZE, /* 2098 */ + IC_64BIT_XS_OPSIZE, /* 2099 */ + IC_XD_OPSIZE, /* 2100 */ + IC_64BIT_XD_OPSIZE, /* 2101 */ + IC_XS_OPSIZE, /* 2102 */ + IC_64BIT_XD_OPSIZE, /* 2103 */ + IC_OPSIZE_ADSIZE, /* 2104 */ + IC_64BIT_REXW_OPSIZE, /* 2105 */ + IC_XS_OPSIZE, /* 2106 */ + IC_64BIT_REXW_XS, /* 2107 */ + IC_XD_OPSIZE, /* 2108 */ + IC_64BIT_REXW_XD, /* 2109 */ + IC_XS_OPSIZE, /* 2110 */ + IC_64BIT_REXW_XS, /* 2111 */ + IC_VEX, /* 2112 */ + IC_VEX, /* 2113 */ + IC_VEX_XS, /* 2114 */ + IC_VEX_XS, /* 2115 */ + IC_VEX_XD, /* 2116 */ + IC_VEX_XD, /* 2117 */ + IC_VEX_XD, /* 2118 */ + IC_VEX_XD, /* 2119 */ + IC_VEX_W, /* 2120 */ + IC_VEX_W, /* 2121 */ + IC_VEX_W_XS, /* 2122 */ + IC_VEX_W_XS, /* 2123 */ + IC_VEX_W_XD, /* 2124 */ + IC_VEX_W_XD, /* 2125 */ + IC_VEX_W_XD, /* 2126 */ + IC_VEX_W_XD, /* 2127 */ + IC_VEX_OPSIZE, /* 2128 */ + IC_VEX_OPSIZE, /* 2129 */ + IC_VEX_OPSIZE, /* 2130 */ + IC_VEX_OPSIZE, /* 2131 */ + IC_VEX_OPSIZE, /* 2132 */ + IC_VEX_OPSIZE, /* 2133 */ + IC_VEX_OPSIZE, /* 2134 */ + IC_VEX_OPSIZE, /* 2135 */ + IC_VEX_W_OPSIZE, /* 2136 */ + IC_VEX_W_OPSIZE, /* 2137 */ + IC_VEX_W_OPSIZE, /* 2138 */ + IC_VEX_W_OPSIZE, /* 2139 */ + IC_VEX_W_OPSIZE, /* 2140 */ + IC_VEX_W_OPSIZE, /* 2141 */ + IC_VEX_W_OPSIZE, /* 2142 */ + IC_VEX_W_OPSIZE, /* 2143 */ + IC_VEX, /* 2144 */ + IC_VEX, /* 2145 */ + IC_VEX_XS, /* 2146 */ + IC_VEX_XS, /* 2147 */ + IC_VEX_XD, /* 2148 */ + IC_VEX_XD, /* 2149 */ + IC_VEX_XD, /* 2150 */ + IC_VEX_XD, /* 2151 */ + IC_VEX_W, /* 2152 */ + IC_VEX_W, /* 2153 */ + IC_VEX_W_XS, /* 2154 */ + IC_VEX_W_XS, /* 2155 */ + IC_VEX_W_XD, /* 2156 */ + IC_VEX_W_XD, /* 2157 */ + IC_VEX_W_XD, /* 2158 */ + IC_VEX_W_XD, /* 2159 */ + IC_VEX_OPSIZE, /* 2160 */ + IC_VEX_OPSIZE, /* 2161 */ + IC_VEX_OPSIZE, /* 2162 */ + IC_VEX_OPSIZE, /* 2163 */ + IC_VEX_OPSIZE, /* 2164 */ + IC_VEX_OPSIZE, /* 2165 */ + IC_VEX_OPSIZE, /* 2166 */ + IC_VEX_OPSIZE, /* 2167 */ + IC_VEX_W_OPSIZE, /* 2168 */ + IC_VEX_W_OPSIZE, /* 2169 */ + IC_VEX_W_OPSIZE, /* 2170 */ + IC_VEX_W_OPSIZE, /* 2171 */ + IC_VEX_W_OPSIZE, /* 2172 */ + IC_VEX_W_OPSIZE, /* 2173 */ + IC_VEX_W_OPSIZE, /* 2174 */ + IC_VEX_W_OPSIZE, /* 2175 */ + IC_VEX_L, /* 2176 */ + IC_VEX_L, /* 2177 */ + IC_VEX_L_XS, /* 2178 */ + IC_VEX_L_XS, /* 2179 */ + IC_VEX_L_XD, /* 2180 */ + IC_VEX_L_XD, /* 2181 */ + IC_VEX_L_XD, /* 2182 */ + IC_VEX_L_XD, /* 2183 */ + IC_VEX_L_W, /* 2184 */ + IC_VEX_L_W, /* 2185 */ + IC_VEX_L_W_XS, /* 2186 */ + IC_VEX_L_W_XS, /* 2187 */ + IC_VEX_L_W_XD, /* 2188 */ + IC_VEX_L_W_XD, /* 2189 */ + IC_VEX_L_W_XD, /* 2190 */ + IC_VEX_L_W_XD, /* 2191 */ + IC_VEX_L_OPSIZE, /* 2192 */ + IC_VEX_L_OPSIZE, /* 2193 */ + IC_VEX_L_OPSIZE, /* 2194 */ + IC_VEX_L_OPSIZE, /* 2195 */ + IC_VEX_L_OPSIZE, /* 2196 */ + IC_VEX_L_OPSIZE, /* 2197 */ + IC_VEX_L_OPSIZE, /* 2198 */ + IC_VEX_L_OPSIZE, /* 2199 */ + IC_VEX_L_W_OPSIZE, /* 2200 */ + IC_VEX_L_W_OPSIZE, /* 2201 */ + IC_VEX_L_W_OPSIZE, /* 2202 */ + IC_VEX_L_W_OPSIZE, /* 2203 */ + IC_VEX_L_W_OPSIZE, /* 2204 */ + IC_VEX_L_W_OPSIZE, /* 2205 */ + IC_VEX_L_W_OPSIZE, /* 2206 */ + IC_VEX_L_W_OPSIZE, /* 2207 */ + IC_VEX_L, /* 2208 */ + IC_VEX_L, /* 2209 */ + IC_VEX_L_XS, /* 2210 */ + IC_VEX_L_XS, /* 2211 */ + IC_VEX_L_XD, /* 2212 */ + IC_VEX_L_XD, /* 2213 */ + IC_VEX_L_XD, /* 2214 */ + IC_VEX_L_XD, /* 2215 */ + IC_VEX_L_W, /* 2216 */ + IC_VEX_L_W, /* 2217 */ + IC_VEX_L_W_XS, /* 2218 */ + IC_VEX_L_W_XS, /* 2219 */ + IC_VEX_L_W_XD, /* 2220 */ + IC_VEX_L_W_XD, /* 2221 */ + IC_VEX_L_W_XD, /* 2222 */ + IC_VEX_L_W_XD, /* 2223 */ + IC_VEX_L_OPSIZE, /* 2224 */ + IC_VEX_L_OPSIZE, /* 2225 */ + IC_VEX_L_OPSIZE, /* 2226 */ + IC_VEX_L_OPSIZE, /* 2227 */ + IC_VEX_L_OPSIZE, /* 2228 */ + IC_VEX_L_OPSIZE, /* 2229 */ + IC_VEX_L_OPSIZE, /* 2230 */ + IC_VEX_L_OPSIZE, /* 2231 */ + IC_VEX_L_W_OPSIZE, /* 2232 */ + IC_VEX_L_W_OPSIZE, /* 2233 */ + IC_VEX_L_W_OPSIZE, /* 2234 */ + IC_VEX_L_W_OPSIZE, /* 2235 */ + IC_VEX_L_W_OPSIZE, /* 2236 */ + IC_VEX_L_W_OPSIZE, /* 2237 */ + IC_VEX_L_W_OPSIZE, /* 2238 */ + IC_VEX_L_W_OPSIZE, /* 2239 */ + IC_VEX_L, /* 2240 */ + IC_VEX_L, /* 2241 */ + IC_VEX_L_XS, /* 2242 */ + IC_VEX_L_XS, /* 2243 */ + IC_VEX_L_XD, /* 2244 */ + IC_VEX_L_XD, /* 2245 */ + IC_VEX_L_XD, /* 2246 */ + IC_VEX_L_XD, /* 2247 */ + IC_VEX_L_W, /* 2248 */ + IC_VEX_L_W, /* 2249 */ + IC_VEX_L_W_XS, /* 2250 */ + IC_VEX_L_W_XS, /* 2251 */ + IC_VEX_L_W_XD, /* 2252 */ + IC_VEX_L_W_XD, /* 2253 */ + IC_VEX_L_W_XD, /* 2254 */ + IC_VEX_L_W_XD, /* 2255 */ + IC_VEX_L_OPSIZE, /* 2256 */ + IC_VEX_L_OPSIZE, /* 2257 */ + IC_VEX_L_OPSIZE, /* 2258 */ + IC_VEX_L_OPSIZE, /* 2259 */ + IC_VEX_L_OPSIZE, /* 2260 */ + IC_VEX_L_OPSIZE, /* 2261 */ + IC_VEX_L_OPSIZE, /* 2262 */ + IC_VEX_L_OPSIZE, /* 2263 */ + IC_VEX_L_W_OPSIZE, /* 2264 */ + IC_VEX_L_W_OPSIZE, /* 2265 */ + IC_VEX_L_W_OPSIZE, /* 2266 */ + IC_VEX_L_W_OPSIZE, /* 2267 */ + IC_VEX_L_W_OPSIZE, /* 2268 */ + IC_VEX_L_W_OPSIZE, /* 2269 */ + IC_VEX_L_W_OPSIZE, /* 2270 */ + IC_VEX_L_W_OPSIZE, /* 2271 */ + IC_VEX_L, /* 2272 */ + IC_VEX_L, /* 2273 */ + IC_VEX_L_XS, /* 2274 */ + IC_VEX_L_XS, /* 2275 */ + IC_VEX_L_XD, /* 2276 */ + IC_VEX_L_XD, /* 2277 */ + IC_VEX_L_XD, /* 2278 */ + IC_VEX_L_XD, /* 2279 */ + IC_VEX_L_W, /* 2280 */ + IC_VEX_L_W, /* 2281 */ + IC_VEX_L_W_XS, /* 2282 */ + IC_VEX_L_W_XS, /* 2283 */ + IC_VEX_L_W_XD, /* 2284 */ + IC_VEX_L_W_XD, /* 2285 */ + IC_VEX_L_W_XD, /* 2286 */ + IC_VEX_L_W_XD, /* 2287 */ + IC_VEX_L_OPSIZE, /* 2288 */ + IC_VEX_L_OPSIZE, /* 2289 */ + IC_VEX_L_OPSIZE, /* 2290 */ + IC_VEX_L_OPSIZE, /* 2291 */ + IC_VEX_L_OPSIZE, /* 2292 */ + IC_VEX_L_OPSIZE, /* 2293 */ + IC_VEX_L_OPSIZE, /* 2294 */ + IC_VEX_L_OPSIZE, /* 2295 */ + IC_VEX_L_W_OPSIZE, /* 2296 */ + IC_VEX_L_W_OPSIZE, /* 2297 */ + IC_VEX_L_W_OPSIZE, /* 2298 */ + IC_VEX_L_W_OPSIZE, /* 2299 */ + IC_VEX_L_W_OPSIZE, /* 2300 */ + IC_VEX_L_W_OPSIZE, /* 2301 */ + IC_VEX_L_W_OPSIZE, /* 2302 */ + IC_VEX_L_W_OPSIZE, /* 2303 */ + IC_EVEX_K, /* 2304 */ + IC_EVEX_K, /* 2305 */ + IC_EVEX_XS_K, /* 2306 */ + IC_EVEX_XS_K, /* 2307 */ + IC_EVEX_XD_K, /* 2308 */ + IC_EVEX_XD_K, /* 2309 */ + IC_EVEX_XD_K, /* 2310 */ + IC_EVEX_XD_K, /* 2311 */ + IC_EVEX_W_K, /* 2312 */ + IC_EVEX_W_K, /* 2313 */ + IC_EVEX_W_XS_K, /* 2314 */ + IC_EVEX_W_XS_K, /* 2315 */ + IC_EVEX_W_XD_K, /* 2316 */ + IC_EVEX_W_XD_K, /* 2317 */ + IC_EVEX_W_XD_K, /* 2318 */ + IC_EVEX_W_XD_K, /* 2319 */ + IC_EVEX_OPSIZE_K, /* 2320 */ + IC_EVEX_OPSIZE_K, /* 2321 */ + IC_EVEX_OPSIZE_K, /* 2322 */ + IC_EVEX_OPSIZE_K, /* 2323 */ + IC_EVEX_OPSIZE_K, /* 2324 */ + IC_EVEX_OPSIZE_K, /* 2325 */ + IC_EVEX_OPSIZE_K, /* 2326 */ + IC_EVEX_OPSIZE_K, /* 2327 */ + IC_EVEX_W_OPSIZE_K, /* 2328 */ + IC_EVEX_W_OPSIZE_K, /* 2329 */ + IC_EVEX_W_OPSIZE_K, /* 2330 */ + IC_EVEX_W_OPSIZE_K, /* 2331 */ + IC_EVEX_W_OPSIZE_K, /* 2332 */ + IC_EVEX_W_OPSIZE_K, /* 2333 */ + IC_EVEX_W_OPSIZE_K, /* 2334 */ + IC_EVEX_W_OPSIZE_K, /* 2335 */ + IC_EVEX_K, /* 2336 */ + IC_EVEX_K, /* 2337 */ + IC_EVEX_XS_K, /* 2338 */ + IC_EVEX_XS_K, /* 2339 */ + IC_EVEX_XD_K, /* 2340 */ + IC_EVEX_XD_K, /* 2341 */ + IC_EVEX_XD_K, /* 2342 */ + IC_EVEX_XD_K, /* 2343 */ + IC_EVEX_W_K, /* 2344 */ + IC_EVEX_W_K, /* 2345 */ + IC_EVEX_W_XS_K, /* 2346 */ + IC_EVEX_W_XS_K, /* 2347 */ + IC_EVEX_W_XD_K, /* 2348 */ + IC_EVEX_W_XD_K, /* 2349 */ + IC_EVEX_W_XD_K, /* 2350 */ + IC_EVEX_W_XD_K, /* 2351 */ + IC_EVEX_OPSIZE_K, /* 2352 */ + IC_EVEX_OPSIZE_K, /* 2353 */ + IC_EVEX_OPSIZE_K, /* 2354 */ + IC_EVEX_OPSIZE_K, /* 2355 */ + IC_EVEX_OPSIZE_K, /* 2356 */ + IC_EVEX_OPSIZE_K, /* 2357 */ + IC_EVEX_OPSIZE_K, /* 2358 */ + IC_EVEX_OPSIZE_K, /* 2359 */ + IC_EVEX_W_OPSIZE_K, /* 2360 */ + IC_EVEX_W_OPSIZE_K, /* 2361 */ + IC_EVEX_W_OPSIZE_K, /* 2362 */ + IC_EVEX_W_OPSIZE_K, /* 2363 */ + IC_EVEX_W_OPSIZE_K, /* 2364 */ + IC_EVEX_W_OPSIZE_K, /* 2365 */ + IC_EVEX_W_OPSIZE_K, /* 2366 */ + IC_EVEX_W_OPSIZE_K, /* 2367 */ + IC_EVEX_K, /* 2368 */ + IC_EVEX_K, /* 2369 */ + IC_EVEX_XS_K, /* 2370 */ + IC_EVEX_XS_K, /* 2371 */ + IC_EVEX_XD_K, /* 2372 */ + IC_EVEX_XD_K, /* 2373 */ + IC_EVEX_XD_K, /* 2374 */ + IC_EVEX_XD_K, /* 2375 */ + IC_EVEX_W_K, /* 2376 */ + IC_EVEX_W_K, /* 2377 */ + IC_EVEX_W_XS_K, /* 2378 */ + IC_EVEX_W_XS_K, /* 2379 */ + IC_EVEX_W_XD_K, /* 2380 */ + IC_EVEX_W_XD_K, /* 2381 */ + IC_EVEX_W_XD_K, /* 2382 */ + IC_EVEX_W_XD_K, /* 2383 */ + IC_EVEX_OPSIZE_K, /* 2384 */ + IC_EVEX_OPSIZE_K, /* 2385 */ + IC_EVEX_OPSIZE_K, /* 2386 */ + IC_EVEX_OPSIZE_K, /* 2387 */ + IC_EVEX_OPSIZE_K, /* 2388 */ + IC_EVEX_OPSIZE_K, /* 2389 */ + IC_EVEX_OPSIZE_K, /* 2390 */ + IC_EVEX_OPSIZE_K, /* 2391 */ + IC_EVEX_W_OPSIZE_K, /* 2392 */ + IC_EVEX_W_OPSIZE_K, /* 2393 */ + IC_EVEX_W_OPSIZE_K, /* 2394 */ + IC_EVEX_W_OPSIZE_K, /* 2395 */ + IC_EVEX_W_OPSIZE_K, /* 2396 */ + IC_EVEX_W_OPSIZE_K, /* 2397 */ + IC_EVEX_W_OPSIZE_K, /* 2398 */ + IC_EVEX_W_OPSIZE_K, /* 2399 */ + IC_EVEX_K, /* 2400 */ + IC_EVEX_K, /* 2401 */ + IC_EVEX_XS_K, /* 2402 */ + IC_EVEX_XS_K, /* 2403 */ + IC_EVEX_XD_K, /* 2404 */ + IC_EVEX_XD_K, /* 2405 */ + IC_EVEX_XD_K, /* 2406 */ + IC_EVEX_XD_K, /* 2407 */ + IC_EVEX_W_K, /* 2408 */ + IC_EVEX_W_K, /* 2409 */ + IC_EVEX_W_XS_K, /* 2410 */ + IC_EVEX_W_XS_K, /* 2411 */ + IC_EVEX_W_XD_K, /* 2412 */ + IC_EVEX_W_XD_K, /* 2413 */ + IC_EVEX_W_XD_K, /* 2414 */ + IC_EVEX_W_XD_K, /* 2415 */ + IC_EVEX_OPSIZE_K, /* 2416 */ + IC_EVEX_OPSIZE_K, /* 2417 */ + IC_EVEX_OPSIZE_K, /* 2418 */ + IC_EVEX_OPSIZE_K, /* 2419 */ + IC_EVEX_OPSIZE_K, /* 2420 */ + IC_EVEX_OPSIZE_K, /* 2421 */ + IC_EVEX_OPSIZE_K, /* 2422 */ + IC_EVEX_OPSIZE_K, /* 2423 */ + IC_EVEX_W_OPSIZE_K, /* 2424 */ + IC_EVEX_W_OPSIZE_K, /* 2425 */ + IC_EVEX_W_OPSIZE_K, /* 2426 */ + IC_EVEX_W_OPSIZE_K, /* 2427 */ + IC_EVEX_W_OPSIZE_K, /* 2428 */ + IC_EVEX_W_OPSIZE_K, /* 2429 */ + IC_EVEX_W_OPSIZE_K, /* 2430 */ + IC_EVEX_W_OPSIZE_K, /* 2431 */ + IC_EVEX_K, /* 2432 */ + IC_EVEX_K, /* 2433 */ + IC_EVEX_XS_K, /* 2434 */ + IC_EVEX_XS_K, /* 2435 */ + IC_EVEX_XD_K, /* 2436 */ + IC_EVEX_XD_K, /* 2437 */ + IC_EVEX_XD_K, /* 2438 */ + IC_EVEX_XD_K, /* 2439 */ + IC_EVEX_W_K, /* 2440 */ + IC_EVEX_W_K, /* 2441 */ + IC_EVEX_W_XS_K, /* 2442 */ + IC_EVEX_W_XS_K, /* 2443 */ + IC_EVEX_W_XD_K, /* 2444 */ + IC_EVEX_W_XD_K, /* 2445 */ + IC_EVEX_W_XD_K, /* 2446 */ + IC_EVEX_W_XD_K, /* 2447 */ + IC_EVEX_OPSIZE_K, /* 2448 */ + IC_EVEX_OPSIZE_K, /* 2449 */ + IC_EVEX_OPSIZE_K, /* 2450 */ + IC_EVEX_OPSIZE_K, /* 2451 */ + IC_EVEX_OPSIZE_K, /* 2452 */ + IC_EVEX_OPSIZE_K, /* 2453 */ + IC_EVEX_OPSIZE_K, /* 2454 */ + IC_EVEX_OPSIZE_K, /* 2455 */ + IC_EVEX_W_OPSIZE_K, /* 2456 */ + IC_EVEX_W_OPSIZE_K, /* 2457 */ + IC_EVEX_W_OPSIZE_K, /* 2458 */ + IC_EVEX_W_OPSIZE_K, /* 2459 */ + IC_EVEX_W_OPSIZE_K, /* 2460 */ + IC_EVEX_W_OPSIZE_K, /* 2461 */ + IC_EVEX_W_OPSIZE_K, /* 2462 */ + IC_EVEX_W_OPSIZE_K, /* 2463 */ + IC_EVEX_K, /* 2464 */ + IC_EVEX_K, /* 2465 */ + IC_EVEX_XS_K, /* 2466 */ + IC_EVEX_XS_K, /* 2467 */ + IC_EVEX_XD_K, /* 2468 */ + IC_EVEX_XD_K, /* 2469 */ + IC_EVEX_XD_K, /* 2470 */ + IC_EVEX_XD_K, /* 2471 */ + IC_EVEX_W_K, /* 2472 */ + IC_EVEX_W_K, /* 2473 */ + IC_EVEX_W_XS_K, /* 2474 */ + IC_EVEX_W_XS_K, /* 2475 */ + IC_EVEX_W_XD_K, /* 2476 */ + IC_EVEX_W_XD_K, /* 2477 */ + IC_EVEX_W_XD_K, /* 2478 */ + IC_EVEX_W_XD_K, /* 2479 */ + IC_EVEX_OPSIZE_K, /* 2480 */ + IC_EVEX_OPSIZE_K, /* 2481 */ + IC_EVEX_OPSIZE_K, /* 2482 */ + IC_EVEX_OPSIZE_K, /* 2483 */ + IC_EVEX_OPSIZE_K, /* 2484 */ + IC_EVEX_OPSIZE_K, /* 2485 */ + IC_EVEX_OPSIZE_K, /* 2486 */ + IC_EVEX_OPSIZE_K, /* 2487 */ + IC_EVEX_W_OPSIZE_K, /* 2488 */ + IC_EVEX_W_OPSIZE_K, /* 2489 */ + IC_EVEX_W_OPSIZE_K, /* 2490 */ + IC_EVEX_W_OPSIZE_K, /* 2491 */ + IC_EVEX_W_OPSIZE_K, /* 2492 */ + IC_EVEX_W_OPSIZE_K, /* 2493 */ + IC_EVEX_W_OPSIZE_K, /* 2494 */ + IC_EVEX_W_OPSIZE_K, /* 2495 */ + IC_EVEX_K, /* 2496 */ + IC_EVEX_K, /* 2497 */ + IC_EVEX_XS_K, /* 2498 */ + IC_EVEX_XS_K, /* 2499 */ + IC_EVEX_XD_K, /* 2500 */ + IC_EVEX_XD_K, /* 2501 */ + IC_EVEX_XD_K, /* 2502 */ + IC_EVEX_XD_K, /* 2503 */ + IC_EVEX_W_K, /* 2504 */ + IC_EVEX_W_K, /* 2505 */ + IC_EVEX_W_XS_K, /* 2506 */ + IC_EVEX_W_XS_K, /* 2507 */ + IC_EVEX_W_XD_K, /* 2508 */ + IC_EVEX_W_XD_K, /* 2509 */ + IC_EVEX_W_XD_K, /* 2510 */ + IC_EVEX_W_XD_K, /* 2511 */ + IC_EVEX_OPSIZE_K, /* 2512 */ + IC_EVEX_OPSIZE_K, /* 2513 */ + IC_EVEX_OPSIZE_K, /* 2514 */ + IC_EVEX_OPSIZE_K, /* 2515 */ + IC_EVEX_OPSIZE_K, /* 2516 */ + IC_EVEX_OPSIZE_K, /* 2517 */ + IC_EVEX_OPSIZE_K, /* 2518 */ + IC_EVEX_OPSIZE_K, /* 2519 */ + IC_EVEX_W_OPSIZE_K, /* 2520 */ + IC_EVEX_W_OPSIZE_K, /* 2521 */ + IC_EVEX_W_OPSIZE_K, /* 2522 */ + IC_EVEX_W_OPSIZE_K, /* 2523 */ + IC_EVEX_W_OPSIZE_K, /* 2524 */ + IC_EVEX_W_OPSIZE_K, /* 2525 */ + IC_EVEX_W_OPSIZE_K, /* 2526 */ + IC_EVEX_W_OPSIZE_K, /* 2527 */ + IC_EVEX_K, /* 2528 */ + IC_EVEX_K, /* 2529 */ + IC_EVEX_XS_K, /* 2530 */ + IC_EVEX_XS_K, /* 2531 */ + IC_EVEX_XD_K, /* 2532 */ + IC_EVEX_XD_K, /* 2533 */ + IC_EVEX_XD_K, /* 2534 */ + IC_EVEX_XD_K, /* 2535 */ + IC_EVEX_W_K, /* 2536 */ + IC_EVEX_W_K, /* 2537 */ + IC_EVEX_W_XS_K, /* 2538 */ + IC_EVEX_W_XS_K, /* 2539 */ + IC_EVEX_W_XD_K, /* 2540 */ + IC_EVEX_W_XD_K, /* 2541 */ + IC_EVEX_W_XD_K, /* 2542 */ + IC_EVEX_W_XD_K, /* 2543 */ + IC_EVEX_OPSIZE_K, /* 2544 */ + IC_EVEX_OPSIZE_K, /* 2545 */ + IC_EVEX_OPSIZE_K, /* 2546 */ + IC_EVEX_OPSIZE_K, /* 2547 */ + IC_EVEX_OPSIZE_K, /* 2548 */ + IC_EVEX_OPSIZE_K, /* 2549 */ + IC_EVEX_OPSIZE_K, /* 2550 */ + IC_EVEX_OPSIZE_K, /* 2551 */ + IC_EVEX_W_OPSIZE_K, /* 2552 */ + IC_EVEX_W_OPSIZE_K, /* 2553 */ + IC_EVEX_W_OPSIZE_K, /* 2554 */ + IC_EVEX_W_OPSIZE_K, /* 2555 */ + IC_EVEX_W_OPSIZE_K, /* 2556 */ + IC_EVEX_W_OPSIZE_K, /* 2557 */ + IC_EVEX_W_OPSIZE_K, /* 2558 */ + IC_EVEX_W_OPSIZE_K, /* 2559 */ + IC, /* 2560 */ + IC_64BIT, /* 2561 */ + IC_XS, /* 2562 */ + IC_64BIT_XS, /* 2563 */ + IC_XD, /* 2564 */ + IC_64BIT_XD, /* 2565 */ + IC_XS, /* 2566 */ + IC_64BIT_XS, /* 2567 */ + IC, /* 2568 */ + IC_64BIT_REXW, /* 2569 */ + IC_XS, /* 2570 */ + IC_64BIT_REXW_XS, /* 2571 */ + IC_XD, /* 2572 */ + IC_64BIT_REXW_XD, /* 2573 */ + IC_XS, /* 2574 */ + IC_64BIT_REXW_XS, /* 2575 */ + IC_OPSIZE, /* 2576 */ + IC_64BIT_OPSIZE, /* 2577 */ + IC_XS_OPSIZE, /* 2578 */ + IC_64BIT_XS_OPSIZE, /* 2579 */ + IC_XD_OPSIZE, /* 2580 */ + IC_64BIT_XD_OPSIZE, /* 2581 */ + IC_XS_OPSIZE, /* 2582 */ + IC_64BIT_XD_OPSIZE, /* 2583 */ + IC_OPSIZE, /* 2584 */ + IC_64BIT_REXW_OPSIZE, /* 2585 */ + IC_XS_OPSIZE, /* 2586 */ + IC_64BIT_REXW_XS, /* 2587 */ + IC_XD_OPSIZE, /* 2588 */ + IC_64BIT_REXW_XD, /* 2589 */ + IC_XS_OPSIZE, /* 2590 */ + IC_64BIT_REXW_XS, /* 2591 */ + IC_ADSIZE, /* 2592 */ + IC_64BIT_ADSIZE, /* 2593 */ + IC_XS_ADSIZE, /* 2594 */ + IC_64BIT_XS_ADSIZE, /* 2595 */ + IC_XD_ADSIZE, /* 2596 */ + IC_64BIT_XD_ADSIZE, /* 2597 */ + IC_XS_ADSIZE, /* 2598 */ + IC_64BIT_XD_ADSIZE, /* 2599 */ + IC_ADSIZE, /* 2600 */ + IC_64BIT_REXW_ADSIZE, /* 2601 */ + IC_XS_ADSIZE, /* 2602 */ + IC_64BIT_REXW_XS, /* 2603 */ + IC_XD_ADSIZE, /* 2604 */ + IC_64BIT_REXW_XD, /* 2605 */ + IC_XS_ADSIZE, /* 2606 */ + IC_64BIT_REXW_XS, /* 2607 */ + IC_OPSIZE_ADSIZE, /* 2608 */ + IC_64BIT_OPSIZE_ADSIZE, /* 2609 */ + IC_XS_OPSIZE, /* 2610 */ + IC_64BIT_XS_OPSIZE, /* 2611 */ + IC_XD_OPSIZE, /* 2612 */ + IC_64BIT_XD_OPSIZE, /* 2613 */ + IC_XS_OPSIZE, /* 2614 */ + IC_64BIT_XD_OPSIZE, /* 2615 */ + IC_OPSIZE_ADSIZE, /* 2616 */ + IC_64BIT_REXW_OPSIZE, /* 2617 */ + IC_XS_OPSIZE, /* 2618 */ + IC_64BIT_REXW_XS, /* 2619 */ + IC_XD_OPSIZE, /* 2620 */ + IC_64BIT_REXW_XD, /* 2621 */ + IC_XS_OPSIZE, /* 2622 */ + IC_64BIT_REXW_XS, /* 2623 */ + IC_VEX, /* 2624 */ + IC_VEX, /* 2625 */ + IC_VEX_XS, /* 2626 */ + IC_VEX_XS, /* 2627 */ + IC_VEX_XD, /* 2628 */ + IC_VEX_XD, /* 2629 */ + IC_VEX_XD, /* 2630 */ + IC_VEX_XD, /* 2631 */ + IC_VEX_W, /* 2632 */ + IC_VEX_W, /* 2633 */ + IC_VEX_W_XS, /* 2634 */ + IC_VEX_W_XS, /* 2635 */ + IC_VEX_W_XD, /* 2636 */ + IC_VEX_W_XD, /* 2637 */ + IC_VEX_W_XD, /* 2638 */ + IC_VEX_W_XD, /* 2639 */ + IC_VEX_OPSIZE, /* 2640 */ + IC_VEX_OPSIZE, /* 2641 */ + IC_VEX_OPSIZE, /* 2642 */ + IC_VEX_OPSIZE, /* 2643 */ + IC_VEX_OPSIZE, /* 2644 */ + IC_VEX_OPSIZE, /* 2645 */ + IC_VEX_OPSIZE, /* 2646 */ + IC_VEX_OPSIZE, /* 2647 */ + IC_VEX_W_OPSIZE, /* 2648 */ + IC_VEX_W_OPSIZE, /* 2649 */ + IC_VEX_W_OPSIZE, /* 2650 */ + IC_VEX_W_OPSIZE, /* 2651 */ + IC_VEX_W_OPSIZE, /* 2652 */ + IC_VEX_W_OPSIZE, /* 2653 */ + IC_VEX_W_OPSIZE, /* 2654 */ + IC_VEX_W_OPSIZE, /* 2655 */ + IC_VEX, /* 2656 */ + IC_VEX, /* 2657 */ + IC_VEX_XS, /* 2658 */ + IC_VEX_XS, /* 2659 */ + IC_VEX_XD, /* 2660 */ + IC_VEX_XD, /* 2661 */ + IC_VEX_XD, /* 2662 */ + IC_VEX_XD, /* 2663 */ + IC_VEX_W, /* 2664 */ + IC_VEX_W, /* 2665 */ + IC_VEX_W_XS, /* 2666 */ + IC_VEX_W_XS, /* 2667 */ + IC_VEX_W_XD, /* 2668 */ + IC_VEX_W_XD, /* 2669 */ + IC_VEX_W_XD, /* 2670 */ + IC_VEX_W_XD, /* 2671 */ + IC_VEX_OPSIZE, /* 2672 */ + IC_VEX_OPSIZE, /* 2673 */ + IC_VEX_OPSIZE, /* 2674 */ + IC_VEX_OPSIZE, /* 2675 */ + IC_VEX_OPSIZE, /* 2676 */ + IC_VEX_OPSIZE, /* 2677 */ + IC_VEX_OPSIZE, /* 2678 */ + IC_VEX_OPSIZE, /* 2679 */ + IC_VEX_W_OPSIZE, /* 2680 */ + IC_VEX_W_OPSIZE, /* 2681 */ + IC_VEX_W_OPSIZE, /* 2682 */ + IC_VEX_W_OPSIZE, /* 2683 */ + IC_VEX_W_OPSIZE, /* 2684 */ + IC_VEX_W_OPSIZE, /* 2685 */ + IC_VEX_W_OPSIZE, /* 2686 */ + IC_VEX_W_OPSIZE, /* 2687 */ + IC_VEX_L, /* 2688 */ + IC_VEX_L, /* 2689 */ + IC_VEX_L_XS, /* 2690 */ + IC_VEX_L_XS, /* 2691 */ + IC_VEX_L_XD, /* 2692 */ + IC_VEX_L_XD, /* 2693 */ + IC_VEX_L_XD, /* 2694 */ + IC_VEX_L_XD, /* 2695 */ + IC_VEX_L_W, /* 2696 */ + IC_VEX_L_W, /* 2697 */ + IC_VEX_L_W_XS, /* 2698 */ + IC_VEX_L_W_XS, /* 2699 */ + IC_VEX_L_W_XD, /* 2700 */ + IC_VEX_L_W_XD, /* 2701 */ + IC_VEX_L_W_XD, /* 2702 */ + IC_VEX_L_W_XD, /* 2703 */ + IC_VEX_L_OPSIZE, /* 2704 */ + IC_VEX_L_OPSIZE, /* 2705 */ + IC_VEX_L_OPSIZE, /* 2706 */ + IC_VEX_L_OPSIZE, /* 2707 */ + IC_VEX_L_OPSIZE, /* 2708 */ + IC_VEX_L_OPSIZE, /* 2709 */ + IC_VEX_L_OPSIZE, /* 2710 */ + IC_VEX_L_OPSIZE, /* 2711 */ + IC_VEX_L_W_OPSIZE, /* 2712 */ + IC_VEX_L_W_OPSIZE, /* 2713 */ + IC_VEX_L_W_OPSIZE, /* 2714 */ + IC_VEX_L_W_OPSIZE, /* 2715 */ + IC_VEX_L_W_OPSIZE, /* 2716 */ + IC_VEX_L_W_OPSIZE, /* 2717 */ + IC_VEX_L_W_OPSIZE, /* 2718 */ + IC_VEX_L_W_OPSIZE, /* 2719 */ + IC_VEX_L, /* 2720 */ + IC_VEX_L, /* 2721 */ + IC_VEX_L_XS, /* 2722 */ + IC_VEX_L_XS, /* 2723 */ + IC_VEX_L_XD, /* 2724 */ + IC_VEX_L_XD, /* 2725 */ + IC_VEX_L_XD, /* 2726 */ + IC_VEX_L_XD, /* 2727 */ + IC_VEX_L_W, /* 2728 */ + IC_VEX_L_W, /* 2729 */ + IC_VEX_L_W_XS, /* 2730 */ + IC_VEX_L_W_XS, /* 2731 */ + IC_VEX_L_W_XD, /* 2732 */ + IC_VEX_L_W_XD, /* 2733 */ + IC_VEX_L_W_XD, /* 2734 */ + IC_VEX_L_W_XD, /* 2735 */ + IC_VEX_L_OPSIZE, /* 2736 */ + IC_VEX_L_OPSIZE, /* 2737 */ + IC_VEX_L_OPSIZE, /* 2738 */ + IC_VEX_L_OPSIZE, /* 2739 */ + IC_VEX_L_OPSIZE, /* 2740 */ + IC_VEX_L_OPSIZE, /* 2741 */ + IC_VEX_L_OPSIZE, /* 2742 */ + IC_VEX_L_OPSIZE, /* 2743 */ + IC_VEX_L_W_OPSIZE, /* 2744 */ + IC_VEX_L_W_OPSIZE, /* 2745 */ + IC_VEX_L_W_OPSIZE, /* 2746 */ + IC_VEX_L_W_OPSIZE, /* 2747 */ + IC_VEX_L_W_OPSIZE, /* 2748 */ + IC_VEX_L_W_OPSIZE, /* 2749 */ + IC_VEX_L_W_OPSIZE, /* 2750 */ + IC_VEX_L_W_OPSIZE, /* 2751 */ + IC_VEX_L, /* 2752 */ + IC_VEX_L, /* 2753 */ + IC_VEX_L_XS, /* 2754 */ + IC_VEX_L_XS, /* 2755 */ + IC_VEX_L_XD, /* 2756 */ + IC_VEX_L_XD, /* 2757 */ + IC_VEX_L_XD, /* 2758 */ + IC_VEX_L_XD, /* 2759 */ + IC_VEX_L_W, /* 2760 */ + IC_VEX_L_W, /* 2761 */ + IC_VEX_L_W_XS, /* 2762 */ + IC_VEX_L_W_XS, /* 2763 */ + IC_VEX_L_W_XD, /* 2764 */ + IC_VEX_L_W_XD, /* 2765 */ + IC_VEX_L_W_XD, /* 2766 */ + IC_VEX_L_W_XD, /* 2767 */ + IC_VEX_L_OPSIZE, /* 2768 */ + IC_VEX_L_OPSIZE, /* 2769 */ + IC_VEX_L_OPSIZE, /* 2770 */ + IC_VEX_L_OPSIZE, /* 2771 */ + IC_VEX_L_OPSIZE, /* 2772 */ + IC_VEX_L_OPSIZE, /* 2773 */ + IC_VEX_L_OPSIZE, /* 2774 */ + IC_VEX_L_OPSIZE, /* 2775 */ + IC_VEX_L_W_OPSIZE, /* 2776 */ + IC_VEX_L_W_OPSIZE, /* 2777 */ + IC_VEX_L_W_OPSIZE, /* 2778 */ + IC_VEX_L_W_OPSIZE, /* 2779 */ + IC_VEX_L_W_OPSIZE, /* 2780 */ + IC_VEX_L_W_OPSIZE, /* 2781 */ + IC_VEX_L_W_OPSIZE, /* 2782 */ + IC_VEX_L_W_OPSIZE, /* 2783 */ + IC_VEX_L, /* 2784 */ + IC_VEX_L, /* 2785 */ + IC_VEX_L_XS, /* 2786 */ + IC_VEX_L_XS, /* 2787 */ + IC_VEX_L_XD, /* 2788 */ + IC_VEX_L_XD, /* 2789 */ + IC_VEX_L_XD, /* 2790 */ + IC_VEX_L_XD, /* 2791 */ + IC_VEX_L_W, /* 2792 */ + IC_VEX_L_W, /* 2793 */ + IC_VEX_L_W_XS, /* 2794 */ + IC_VEX_L_W_XS, /* 2795 */ + IC_VEX_L_W_XD, /* 2796 */ + IC_VEX_L_W_XD, /* 2797 */ + IC_VEX_L_W_XD, /* 2798 */ + IC_VEX_L_W_XD, /* 2799 */ + IC_VEX_L_OPSIZE, /* 2800 */ + IC_VEX_L_OPSIZE, /* 2801 */ + IC_VEX_L_OPSIZE, /* 2802 */ + IC_VEX_L_OPSIZE, /* 2803 */ + IC_VEX_L_OPSIZE, /* 2804 */ + IC_VEX_L_OPSIZE, /* 2805 */ + IC_VEX_L_OPSIZE, /* 2806 */ + IC_VEX_L_OPSIZE, /* 2807 */ + IC_VEX_L_W_OPSIZE, /* 2808 */ + IC_VEX_L_W_OPSIZE, /* 2809 */ + IC_VEX_L_W_OPSIZE, /* 2810 */ + IC_VEX_L_W_OPSIZE, /* 2811 */ + IC_VEX_L_W_OPSIZE, /* 2812 */ + IC_VEX_L_W_OPSIZE, /* 2813 */ + IC_VEX_L_W_OPSIZE, /* 2814 */ + IC_VEX_L_W_OPSIZE, /* 2815 */ + IC_EVEX_L_K, /* 2816 */ + IC_EVEX_L_K, /* 2817 */ + IC_EVEX_L_XS_K, /* 2818 */ + IC_EVEX_L_XS_K, /* 2819 */ + IC_EVEX_L_XD_K, /* 2820 */ + IC_EVEX_L_XD_K, /* 2821 */ + IC_EVEX_L_XD_K, /* 2822 */ + IC_EVEX_L_XD_K, /* 2823 */ + IC_EVEX_L_W_K, /* 2824 */ + IC_EVEX_L_W_K, /* 2825 */ + IC_EVEX_L_W_XS_K, /* 2826 */ + IC_EVEX_L_W_XS_K, /* 2827 */ + IC_EVEX_L_W_XD_K, /* 2828 */ + IC_EVEX_L_W_XD_K, /* 2829 */ + IC_EVEX_L_W_XD_K, /* 2830 */ + IC_EVEX_L_W_XD_K, /* 2831 */ + IC_EVEX_L_OPSIZE_K, /* 2832 */ + IC_EVEX_L_OPSIZE_K, /* 2833 */ + IC_EVEX_L_OPSIZE_K, /* 2834 */ + IC_EVEX_L_OPSIZE_K, /* 2835 */ + IC_EVEX_L_OPSIZE_K, /* 2836 */ + IC_EVEX_L_OPSIZE_K, /* 2837 */ + IC_EVEX_L_OPSIZE_K, /* 2838 */ + IC_EVEX_L_OPSIZE_K, /* 2839 */ + IC_EVEX_L_W_OPSIZE_K, /* 2840 */ + IC_EVEX_L_W_OPSIZE_K, /* 2841 */ + IC_EVEX_L_W_OPSIZE_K, /* 2842 */ + IC_EVEX_L_W_OPSIZE_K, /* 2843 */ + IC_EVEX_L_W_OPSIZE_K, /* 2844 */ + IC_EVEX_L_W_OPSIZE_K, /* 2845 */ + IC_EVEX_L_W_OPSIZE_K, /* 2846 */ + IC_EVEX_L_W_OPSIZE_K, /* 2847 */ + IC_EVEX_L_K, /* 2848 */ + IC_EVEX_L_K, /* 2849 */ + IC_EVEX_L_XS_K, /* 2850 */ + IC_EVEX_L_XS_K, /* 2851 */ + IC_EVEX_L_XD_K, /* 2852 */ + IC_EVEX_L_XD_K, /* 2853 */ + IC_EVEX_L_XD_K, /* 2854 */ + IC_EVEX_L_XD_K, /* 2855 */ + IC_EVEX_L_W_K, /* 2856 */ + IC_EVEX_L_W_K, /* 2857 */ + IC_EVEX_L_W_XS_K, /* 2858 */ + IC_EVEX_L_W_XS_K, /* 2859 */ + IC_EVEX_L_W_XD_K, /* 2860 */ + IC_EVEX_L_W_XD_K, /* 2861 */ + IC_EVEX_L_W_XD_K, /* 2862 */ + IC_EVEX_L_W_XD_K, /* 2863 */ + IC_EVEX_L_OPSIZE_K, /* 2864 */ + IC_EVEX_L_OPSIZE_K, /* 2865 */ + IC_EVEX_L_OPSIZE_K, /* 2866 */ + IC_EVEX_L_OPSIZE_K, /* 2867 */ + IC_EVEX_L_OPSIZE_K, /* 2868 */ + IC_EVEX_L_OPSIZE_K, /* 2869 */ + IC_EVEX_L_OPSIZE_K, /* 2870 */ + IC_EVEX_L_OPSIZE_K, /* 2871 */ + IC_EVEX_L_W_OPSIZE_K, /* 2872 */ + IC_EVEX_L_W_OPSIZE_K, /* 2873 */ + IC_EVEX_L_W_OPSIZE_K, /* 2874 */ + IC_EVEX_L_W_OPSIZE_K, /* 2875 */ + IC_EVEX_L_W_OPSIZE_K, /* 2876 */ + IC_EVEX_L_W_OPSIZE_K, /* 2877 */ + IC_EVEX_L_W_OPSIZE_K, /* 2878 */ + IC_EVEX_L_W_OPSIZE_K, /* 2879 */ + IC_EVEX_L_K, /* 2880 */ + IC_EVEX_L_K, /* 2881 */ + IC_EVEX_L_XS_K, /* 2882 */ + IC_EVEX_L_XS_K, /* 2883 */ + IC_EVEX_L_XD_K, /* 2884 */ + IC_EVEX_L_XD_K, /* 2885 */ + IC_EVEX_L_XD_K, /* 2886 */ + IC_EVEX_L_XD_K, /* 2887 */ + IC_EVEX_L_W_K, /* 2888 */ + IC_EVEX_L_W_K, /* 2889 */ + IC_EVEX_L_W_XS_K, /* 2890 */ + IC_EVEX_L_W_XS_K, /* 2891 */ + IC_EVEX_L_W_XD_K, /* 2892 */ + IC_EVEX_L_W_XD_K, /* 2893 */ + IC_EVEX_L_W_XD_K, /* 2894 */ + IC_EVEX_L_W_XD_K, /* 2895 */ + IC_EVEX_L_OPSIZE_K, /* 2896 */ + IC_EVEX_L_OPSIZE_K, /* 2897 */ + IC_EVEX_L_OPSIZE_K, /* 2898 */ + IC_EVEX_L_OPSIZE_K, /* 2899 */ + IC_EVEX_L_OPSIZE_K, /* 2900 */ + IC_EVEX_L_OPSIZE_K, /* 2901 */ + IC_EVEX_L_OPSIZE_K, /* 2902 */ + IC_EVEX_L_OPSIZE_K, /* 2903 */ + IC_EVEX_L_W_OPSIZE_K, /* 2904 */ + IC_EVEX_L_W_OPSIZE_K, /* 2905 */ + IC_EVEX_L_W_OPSIZE_K, /* 2906 */ + IC_EVEX_L_W_OPSIZE_K, /* 2907 */ + IC_EVEX_L_W_OPSIZE_K, /* 2908 */ + IC_EVEX_L_W_OPSIZE_K, /* 2909 */ + IC_EVEX_L_W_OPSIZE_K, /* 2910 */ + IC_EVEX_L_W_OPSIZE_K, /* 2911 */ + IC_EVEX_L_K, /* 2912 */ + IC_EVEX_L_K, /* 2913 */ + IC_EVEX_L_XS_K, /* 2914 */ + IC_EVEX_L_XS_K, /* 2915 */ + IC_EVEX_L_XD_K, /* 2916 */ + IC_EVEX_L_XD_K, /* 2917 */ + IC_EVEX_L_XD_K, /* 2918 */ + IC_EVEX_L_XD_K, /* 2919 */ + IC_EVEX_L_W_K, /* 2920 */ + IC_EVEX_L_W_K, /* 2921 */ + IC_EVEX_L_W_XS_K, /* 2922 */ + IC_EVEX_L_W_XS_K, /* 2923 */ + IC_EVEX_L_W_XD_K, /* 2924 */ + IC_EVEX_L_W_XD_K, /* 2925 */ + IC_EVEX_L_W_XD_K, /* 2926 */ + IC_EVEX_L_W_XD_K, /* 2927 */ + IC_EVEX_L_OPSIZE_K, /* 2928 */ + IC_EVEX_L_OPSIZE_K, /* 2929 */ + IC_EVEX_L_OPSIZE_K, /* 2930 */ + IC_EVEX_L_OPSIZE_K, /* 2931 */ + IC_EVEX_L_OPSIZE_K, /* 2932 */ + IC_EVEX_L_OPSIZE_K, /* 2933 */ + IC_EVEX_L_OPSIZE_K, /* 2934 */ + IC_EVEX_L_OPSIZE_K, /* 2935 */ + IC_EVEX_L_W_OPSIZE_K, /* 2936 */ + IC_EVEX_L_W_OPSIZE_K, /* 2937 */ + IC_EVEX_L_W_OPSIZE_K, /* 2938 */ + IC_EVEX_L_W_OPSIZE_K, /* 2939 */ + IC_EVEX_L_W_OPSIZE_K, /* 2940 */ + IC_EVEX_L_W_OPSIZE_K, /* 2941 */ + IC_EVEX_L_W_OPSIZE_K, /* 2942 */ + IC_EVEX_L_W_OPSIZE_K, /* 2943 */ + IC_EVEX_L_K, /* 2944 */ + IC_EVEX_L_K, /* 2945 */ + IC_EVEX_L_XS_K, /* 2946 */ + IC_EVEX_L_XS_K, /* 2947 */ + IC_EVEX_L_XD_K, /* 2948 */ + IC_EVEX_L_XD_K, /* 2949 */ + IC_EVEX_L_XD_K, /* 2950 */ + IC_EVEX_L_XD_K, /* 2951 */ + IC_EVEX_L_W_K, /* 2952 */ + IC_EVEX_L_W_K, /* 2953 */ + IC_EVEX_L_W_XS_K, /* 2954 */ + IC_EVEX_L_W_XS_K, /* 2955 */ + IC_EVEX_L_W_XD_K, /* 2956 */ + IC_EVEX_L_W_XD_K, /* 2957 */ + IC_EVEX_L_W_XD_K, /* 2958 */ + IC_EVEX_L_W_XD_K, /* 2959 */ + IC_EVEX_L_OPSIZE_K, /* 2960 */ + IC_EVEX_L_OPSIZE_K, /* 2961 */ + IC_EVEX_L_OPSIZE_K, /* 2962 */ + IC_EVEX_L_OPSIZE_K, /* 2963 */ + IC_EVEX_L_OPSIZE_K, /* 2964 */ + IC_EVEX_L_OPSIZE_K, /* 2965 */ + IC_EVEX_L_OPSIZE_K, /* 2966 */ + IC_EVEX_L_OPSIZE_K, /* 2967 */ + IC_EVEX_L_W_OPSIZE_K, /* 2968 */ + IC_EVEX_L_W_OPSIZE_K, /* 2969 */ + IC_EVEX_L_W_OPSIZE_K, /* 2970 */ + IC_EVEX_L_W_OPSIZE_K, /* 2971 */ + IC_EVEX_L_W_OPSIZE_K, /* 2972 */ + IC_EVEX_L_W_OPSIZE_K, /* 2973 */ + IC_EVEX_L_W_OPSIZE_K, /* 2974 */ + IC_EVEX_L_W_OPSIZE_K, /* 2975 */ + IC_EVEX_L_K, /* 2976 */ + IC_EVEX_L_K, /* 2977 */ + IC_EVEX_L_XS_K, /* 2978 */ + IC_EVEX_L_XS_K, /* 2979 */ + IC_EVEX_L_XD_K, /* 2980 */ + IC_EVEX_L_XD_K, /* 2981 */ + IC_EVEX_L_XD_K, /* 2982 */ + IC_EVEX_L_XD_K, /* 2983 */ + IC_EVEX_L_W_K, /* 2984 */ + IC_EVEX_L_W_K, /* 2985 */ + IC_EVEX_L_W_XS_K, /* 2986 */ + IC_EVEX_L_W_XS_K, /* 2987 */ + IC_EVEX_L_W_XD_K, /* 2988 */ + IC_EVEX_L_W_XD_K, /* 2989 */ + IC_EVEX_L_W_XD_K, /* 2990 */ + IC_EVEX_L_W_XD_K, /* 2991 */ + IC_EVEX_L_OPSIZE_K, /* 2992 */ + IC_EVEX_L_OPSIZE_K, /* 2993 */ + IC_EVEX_L_OPSIZE_K, /* 2994 */ + IC_EVEX_L_OPSIZE_K, /* 2995 */ + IC_EVEX_L_OPSIZE_K, /* 2996 */ + IC_EVEX_L_OPSIZE_K, /* 2997 */ + IC_EVEX_L_OPSIZE_K, /* 2998 */ + IC_EVEX_L_OPSIZE_K, /* 2999 */ + IC_EVEX_L_W_OPSIZE_K, /* 3000 */ + IC_EVEX_L_W_OPSIZE_K, /* 3001 */ + IC_EVEX_L_W_OPSIZE_K, /* 3002 */ + IC_EVEX_L_W_OPSIZE_K, /* 3003 */ + IC_EVEX_L_W_OPSIZE_K, /* 3004 */ + IC_EVEX_L_W_OPSIZE_K, /* 3005 */ + IC_EVEX_L_W_OPSIZE_K, /* 3006 */ + IC_EVEX_L_W_OPSIZE_K, /* 3007 */ + IC_EVEX_L_K, /* 3008 */ + IC_EVEX_L_K, /* 3009 */ + IC_EVEX_L_XS_K, /* 3010 */ + IC_EVEX_L_XS_K, /* 3011 */ + IC_EVEX_L_XD_K, /* 3012 */ + IC_EVEX_L_XD_K, /* 3013 */ + IC_EVEX_L_XD_K, /* 3014 */ + IC_EVEX_L_XD_K, /* 3015 */ + IC_EVEX_L_W_K, /* 3016 */ + IC_EVEX_L_W_K, /* 3017 */ + IC_EVEX_L_W_XS_K, /* 3018 */ + IC_EVEX_L_W_XS_K, /* 3019 */ + IC_EVEX_L_W_XD_K, /* 3020 */ + IC_EVEX_L_W_XD_K, /* 3021 */ + IC_EVEX_L_W_XD_K, /* 3022 */ + IC_EVEX_L_W_XD_K, /* 3023 */ + IC_EVEX_L_OPSIZE_K, /* 3024 */ + IC_EVEX_L_OPSIZE_K, /* 3025 */ + IC_EVEX_L_OPSIZE_K, /* 3026 */ + IC_EVEX_L_OPSIZE_K, /* 3027 */ + IC_EVEX_L_OPSIZE_K, /* 3028 */ + IC_EVEX_L_OPSIZE_K, /* 3029 */ + IC_EVEX_L_OPSIZE_K, /* 3030 */ + IC_EVEX_L_OPSIZE_K, /* 3031 */ + IC_EVEX_L_W_OPSIZE_K, /* 3032 */ + IC_EVEX_L_W_OPSIZE_K, /* 3033 */ + IC_EVEX_L_W_OPSIZE_K, /* 3034 */ + IC_EVEX_L_W_OPSIZE_K, /* 3035 */ + IC_EVEX_L_W_OPSIZE_K, /* 3036 */ + IC_EVEX_L_W_OPSIZE_K, /* 3037 */ + IC_EVEX_L_W_OPSIZE_K, /* 3038 */ + IC_EVEX_L_W_OPSIZE_K, /* 3039 */ + IC_EVEX_L_K, /* 3040 */ + IC_EVEX_L_K, /* 3041 */ + IC_EVEX_L_XS_K, /* 3042 */ + IC_EVEX_L_XS_K, /* 3043 */ + IC_EVEX_L_XD_K, /* 3044 */ + IC_EVEX_L_XD_K, /* 3045 */ + IC_EVEX_L_XD_K, /* 3046 */ + IC_EVEX_L_XD_K, /* 3047 */ + IC_EVEX_L_W_K, /* 3048 */ + IC_EVEX_L_W_K, /* 3049 */ + IC_EVEX_L_W_XS_K, /* 3050 */ + IC_EVEX_L_W_XS_K, /* 3051 */ + IC_EVEX_L_W_XD_K, /* 3052 */ + IC_EVEX_L_W_XD_K, /* 3053 */ + IC_EVEX_L_W_XD_K, /* 3054 */ + IC_EVEX_L_W_XD_K, /* 3055 */ + IC_EVEX_L_OPSIZE_K, /* 3056 */ + IC_EVEX_L_OPSIZE_K, /* 3057 */ + IC_EVEX_L_OPSIZE_K, /* 3058 */ + IC_EVEX_L_OPSIZE_K, /* 3059 */ + IC_EVEX_L_OPSIZE_K, /* 3060 */ + IC_EVEX_L_OPSIZE_K, /* 3061 */ + IC_EVEX_L_OPSIZE_K, /* 3062 */ + IC_EVEX_L_OPSIZE_K, /* 3063 */ + IC_EVEX_L_W_OPSIZE_K, /* 3064 */ + IC_EVEX_L_W_OPSIZE_K, /* 3065 */ + IC_EVEX_L_W_OPSIZE_K, /* 3066 */ + IC_EVEX_L_W_OPSIZE_K, /* 3067 */ + IC_EVEX_L_W_OPSIZE_K, /* 3068 */ + IC_EVEX_L_W_OPSIZE_K, /* 3069 */ + IC_EVEX_L_W_OPSIZE_K, /* 3070 */ + IC_EVEX_L_W_OPSIZE_K, /* 3071 */ + IC, /* 3072 */ + IC_64BIT, /* 3073 */ + IC_XS, /* 3074 */ + IC_64BIT_XS, /* 3075 */ + IC_XD, /* 3076 */ + IC_64BIT_XD, /* 3077 */ + IC_XS, /* 3078 */ + IC_64BIT_XS, /* 3079 */ + IC, /* 3080 */ + IC_64BIT_REXW, /* 3081 */ + IC_XS, /* 3082 */ + IC_64BIT_REXW_XS, /* 3083 */ + IC_XD, /* 3084 */ + IC_64BIT_REXW_XD, /* 3085 */ + IC_XS, /* 3086 */ + IC_64BIT_REXW_XS, /* 3087 */ + IC_OPSIZE, /* 3088 */ + IC_64BIT_OPSIZE, /* 3089 */ + IC_XS_OPSIZE, /* 3090 */ + IC_64BIT_XS_OPSIZE, /* 3091 */ + IC_XD_OPSIZE, /* 3092 */ + IC_64BIT_XD_OPSIZE, /* 3093 */ + IC_XS_OPSIZE, /* 3094 */ + IC_64BIT_XD_OPSIZE, /* 3095 */ + IC_OPSIZE, /* 3096 */ + IC_64BIT_REXW_OPSIZE, /* 3097 */ + IC_XS_OPSIZE, /* 3098 */ + IC_64BIT_REXW_XS, /* 3099 */ + IC_XD_OPSIZE, /* 3100 */ + IC_64BIT_REXW_XD, /* 3101 */ + IC_XS_OPSIZE, /* 3102 */ + IC_64BIT_REXW_XS, /* 3103 */ + IC_ADSIZE, /* 3104 */ + IC_64BIT_ADSIZE, /* 3105 */ + IC_XS_ADSIZE, /* 3106 */ + IC_64BIT_XS_ADSIZE, /* 3107 */ + IC_XD_ADSIZE, /* 3108 */ + IC_64BIT_XD_ADSIZE, /* 3109 */ + IC_XS_ADSIZE, /* 3110 */ + IC_64BIT_XD_ADSIZE, /* 3111 */ + IC_ADSIZE, /* 3112 */ + IC_64BIT_REXW_ADSIZE, /* 3113 */ + IC_XS_ADSIZE, /* 3114 */ + IC_64BIT_REXW_XS, /* 3115 */ + IC_XD_ADSIZE, /* 3116 */ + IC_64BIT_REXW_XD, /* 3117 */ + IC_XS_ADSIZE, /* 3118 */ + IC_64BIT_REXW_XS, /* 3119 */ + IC_OPSIZE_ADSIZE, /* 3120 */ + IC_64BIT_OPSIZE_ADSIZE, /* 3121 */ + IC_XS_OPSIZE, /* 3122 */ + IC_64BIT_XS_OPSIZE, /* 3123 */ + IC_XD_OPSIZE, /* 3124 */ + IC_64BIT_XD_OPSIZE, /* 3125 */ + IC_XS_OPSIZE, /* 3126 */ + IC_64BIT_XD_OPSIZE, /* 3127 */ + IC_OPSIZE_ADSIZE, /* 3128 */ + IC_64BIT_REXW_OPSIZE, /* 3129 */ + IC_XS_OPSIZE, /* 3130 */ + IC_64BIT_REXW_XS, /* 3131 */ + IC_XD_OPSIZE, /* 3132 */ + IC_64BIT_REXW_XD, /* 3133 */ + IC_XS_OPSIZE, /* 3134 */ + IC_64BIT_REXW_XS, /* 3135 */ + IC_VEX, /* 3136 */ + IC_VEX, /* 3137 */ + IC_VEX_XS, /* 3138 */ + IC_VEX_XS, /* 3139 */ + IC_VEX_XD, /* 3140 */ + IC_VEX_XD, /* 3141 */ + IC_VEX_XD, /* 3142 */ + IC_VEX_XD, /* 3143 */ + IC_VEX_W, /* 3144 */ + IC_VEX_W, /* 3145 */ + IC_VEX_W_XS, /* 3146 */ + IC_VEX_W_XS, /* 3147 */ + IC_VEX_W_XD, /* 3148 */ + IC_VEX_W_XD, /* 3149 */ + IC_VEX_W_XD, /* 3150 */ + IC_VEX_W_XD, /* 3151 */ + IC_VEX_OPSIZE, /* 3152 */ + IC_VEX_OPSIZE, /* 3153 */ + IC_VEX_OPSIZE, /* 3154 */ + IC_VEX_OPSIZE, /* 3155 */ + IC_VEX_OPSIZE, /* 3156 */ + IC_VEX_OPSIZE, /* 3157 */ + IC_VEX_OPSIZE, /* 3158 */ + IC_VEX_OPSIZE, /* 3159 */ + IC_VEX_W_OPSIZE, /* 3160 */ + IC_VEX_W_OPSIZE, /* 3161 */ + IC_VEX_W_OPSIZE, /* 3162 */ + IC_VEX_W_OPSIZE, /* 3163 */ + IC_VEX_W_OPSIZE, /* 3164 */ + IC_VEX_W_OPSIZE, /* 3165 */ + IC_VEX_W_OPSIZE, /* 3166 */ + IC_VEX_W_OPSIZE, /* 3167 */ + IC_VEX, /* 3168 */ + IC_VEX, /* 3169 */ + IC_VEX_XS, /* 3170 */ + IC_VEX_XS, /* 3171 */ + IC_VEX_XD, /* 3172 */ + IC_VEX_XD, /* 3173 */ + IC_VEX_XD, /* 3174 */ + IC_VEX_XD, /* 3175 */ + IC_VEX_W, /* 3176 */ + IC_VEX_W, /* 3177 */ + IC_VEX_W_XS, /* 3178 */ + IC_VEX_W_XS, /* 3179 */ + IC_VEX_W_XD, /* 3180 */ + IC_VEX_W_XD, /* 3181 */ + IC_VEX_W_XD, /* 3182 */ + IC_VEX_W_XD, /* 3183 */ + IC_VEX_OPSIZE, /* 3184 */ + IC_VEX_OPSIZE, /* 3185 */ + IC_VEX_OPSIZE, /* 3186 */ + IC_VEX_OPSIZE, /* 3187 */ + IC_VEX_OPSIZE, /* 3188 */ + IC_VEX_OPSIZE, /* 3189 */ + IC_VEX_OPSIZE, /* 3190 */ + IC_VEX_OPSIZE, /* 3191 */ + IC_VEX_W_OPSIZE, /* 3192 */ + IC_VEX_W_OPSIZE, /* 3193 */ + IC_VEX_W_OPSIZE, /* 3194 */ + IC_VEX_W_OPSIZE, /* 3195 */ + IC_VEX_W_OPSIZE, /* 3196 */ + IC_VEX_W_OPSIZE, /* 3197 */ + IC_VEX_W_OPSIZE, /* 3198 */ + IC_VEX_W_OPSIZE, /* 3199 */ + IC_VEX_L, /* 3200 */ + IC_VEX_L, /* 3201 */ + IC_VEX_L_XS, /* 3202 */ + IC_VEX_L_XS, /* 3203 */ + IC_VEX_L_XD, /* 3204 */ + IC_VEX_L_XD, /* 3205 */ + IC_VEX_L_XD, /* 3206 */ + IC_VEX_L_XD, /* 3207 */ + IC_VEX_L_W, /* 3208 */ + IC_VEX_L_W, /* 3209 */ + IC_VEX_L_W_XS, /* 3210 */ + IC_VEX_L_W_XS, /* 3211 */ + IC_VEX_L_W_XD, /* 3212 */ + IC_VEX_L_W_XD, /* 3213 */ + IC_VEX_L_W_XD, /* 3214 */ + IC_VEX_L_W_XD, /* 3215 */ + IC_VEX_L_OPSIZE, /* 3216 */ + IC_VEX_L_OPSIZE, /* 3217 */ + IC_VEX_L_OPSIZE, /* 3218 */ + IC_VEX_L_OPSIZE, /* 3219 */ + IC_VEX_L_OPSIZE, /* 3220 */ + IC_VEX_L_OPSIZE, /* 3221 */ + IC_VEX_L_OPSIZE, /* 3222 */ + IC_VEX_L_OPSIZE, /* 3223 */ + IC_VEX_L_W_OPSIZE, /* 3224 */ + IC_VEX_L_W_OPSIZE, /* 3225 */ + IC_VEX_L_W_OPSIZE, /* 3226 */ + IC_VEX_L_W_OPSIZE, /* 3227 */ + IC_VEX_L_W_OPSIZE, /* 3228 */ + IC_VEX_L_W_OPSIZE, /* 3229 */ + IC_VEX_L_W_OPSIZE, /* 3230 */ + IC_VEX_L_W_OPSIZE, /* 3231 */ + IC_VEX_L, /* 3232 */ + IC_VEX_L, /* 3233 */ + IC_VEX_L_XS, /* 3234 */ + IC_VEX_L_XS, /* 3235 */ + IC_VEX_L_XD, /* 3236 */ + IC_VEX_L_XD, /* 3237 */ + IC_VEX_L_XD, /* 3238 */ + IC_VEX_L_XD, /* 3239 */ + IC_VEX_L_W, /* 3240 */ + IC_VEX_L_W, /* 3241 */ + IC_VEX_L_W_XS, /* 3242 */ + IC_VEX_L_W_XS, /* 3243 */ + IC_VEX_L_W_XD, /* 3244 */ + IC_VEX_L_W_XD, /* 3245 */ + IC_VEX_L_W_XD, /* 3246 */ + IC_VEX_L_W_XD, /* 3247 */ + IC_VEX_L_OPSIZE, /* 3248 */ + IC_VEX_L_OPSIZE, /* 3249 */ + IC_VEX_L_OPSIZE, /* 3250 */ + IC_VEX_L_OPSIZE, /* 3251 */ + IC_VEX_L_OPSIZE, /* 3252 */ + IC_VEX_L_OPSIZE, /* 3253 */ + IC_VEX_L_OPSIZE, /* 3254 */ + IC_VEX_L_OPSIZE, /* 3255 */ + IC_VEX_L_W_OPSIZE, /* 3256 */ + IC_VEX_L_W_OPSIZE, /* 3257 */ + IC_VEX_L_W_OPSIZE, /* 3258 */ + IC_VEX_L_W_OPSIZE, /* 3259 */ + IC_VEX_L_W_OPSIZE, /* 3260 */ + IC_VEX_L_W_OPSIZE, /* 3261 */ + IC_VEX_L_W_OPSIZE, /* 3262 */ + IC_VEX_L_W_OPSIZE, /* 3263 */ + IC_VEX_L, /* 3264 */ + IC_VEX_L, /* 3265 */ + IC_VEX_L_XS, /* 3266 */ + IC_VEX_L_XS, /* 3267 */ + IC_VEX_L_XD, /* 3268 */ + IC_VEX_L_XD, /* 3269 */ + IC_VEX_L_XD, /* 3270 */ + IC_VEX_L_XD, /* 3271 */ + IC_VEX_L_W, /* 3272 */ + IC_VEX_L_W, /* 3273 */ + IC_VEX_L_W_XS, /* 3274 */ + IC_VEX_L_W_XS, /* 3275 */ + IC_VEX_L_W_XD, /* 3276 */ + IC_VEX_L_W_XD, /* 3277 */ + IC_VEX_L_W_XD, /* 3278 */ + IC_VEX_L_W_XD, /* 3279 */ + IC_VEX_L_OPSIZE, /* 3280 */ + IC_VEX_L_OPSIZE, /* 3281 */ + IC_VEX_L_OPSIZE, /* 3282 */ + IC_VEX_L_OPSIZE, /* 3283 */ + IC_VEX_L_OPSIZE, /* 3284 */ + IC_VEX_L_OPSIZE, /* 3285 */ + IC_VEX_L_OPSIZE, /* 3286 */ + IC_VEX_L_OPSIZE, /* 3287 */ + IC_VEX_L_W_OPSIZE, /* 3288 */ + IC_VEX_L_W_OPSIZE, /* 3289 */ + IC_VEX_L_W_OPSIZE, /* 3290 */ + IC_VEX_L_W_OPSIZE, /* 3291 */ + IC_VEX_L_W_OPSIZE, /* 3292 */ + IC_VEX_L_W_OPSIZE, /* 3293 */ + IC_VEX_L_W_OPSIZE, /* 3294 */ + IC_VEX_L_W_OPSIZE, /* 3295 */ + IC_VEX_L, /* 3296 */ + IC_VEX_L, /* 3297 */ + IC_VEX_L_XS, /* 3298 */ + IC_VEX_L_XS, /* 3299 */ + IC_VEX_L_XD, /* 3300 */ + IC_VEX_L_XD, /* 3301 */ + IC_VEX_L_XD, /* 3302 */ + IC_VEX_L_XD, /* 3303 */ + IC_VEX_L_W, /* 3304 */ + IC_VEX_L_W, /* 3305 */ + IC_VEX_L_W_XS, /* 3306 */ + IC_VEX_L_W_XS, /* 3307 */ + IC_VEX_L_W_XD, /* 3308 */ + IC_VEX_L_W_XD, /* 3309 */ + IC_VEX_L_W_XD, /* 3310 */ + IC_VEX_L_W_XD, /* 3311 */ + IC_VEX_L_OPSIZE, /* 3312 */ + IC_VEX_L_OPSIZE, /* 3313 */ + IC_VEX_L_OPSIZE, /* 3314 */ + IC_VEX_L_OPSIZE, /* 3315 */ + IC_VEX_L_OPSIZE, /* 3316 */ + IC_VEX_L_OPSIZE, /* 3317 */ + IC_VEX_L_OPSIZE, /* 3318 */ + IC_VEX_L_OPSIZE, /* 3319 */ + IC_VEX_L_W_OPSIZE, /* 3320 */ + IC_VEX_L_W_OPSIZE, /* 3321 */ + IC_VEX_L_W_OPSIZE, /* 3322 */ + IC_VEX_L_W_OPSIZE, /* 3323 */ + IC_VEX_L_W_OPSIZE, /* 3324 */ + IC_VEX_L_W_OPSIZE, /* 3325 */ + IC_VEX_L_W_OPSIZE, /* 3326 */ + IC_VEX_L_W_OPSIZE, /* 3327 */ + IC_EVEX_L2_K, /* 3328 */ + IC_EVEX_L2_K, /* 3329 */ + IC_EVEX_L2_XS_K, /* 3330 */ + IC_EVEX_L2_XS_K, /* 3331 */ + IC_EVEX_L2_XD_K, /* 3332 */ + IC_EVEX_L2_XD_K, /* 3333 */ + IC_EVEX_L2_XD_K, /* 3334 */ + IC_EVEX_L2_XD_K, /* 3335 */ + IC_EVEX_L2_W_K, /* 3336 */ + IC_EVEX_L2_W_K, /* 3337 */ + IC_EVEX_L2_W_XS_K, /* 3338 */ + IC_EVEX_L2_W_XS_K, /* 3339 */ + IC_EVEX_L2_W_XD_K, /* 3340 */ + IC_EVEX_L2_W_XD_K, /* 3341 */ + IC_EVEX_L2_W_XD_K, /* 3342 */ + IC_EVEX_L2_W_XD_K, /* 3343 */ + IC_EVEX_L2_OPSIZE_K, /* 3344 */ + IC_EVEX_L2_OPSIZE_K, /* 3345 */ + IC_EVEX_L2_OPSIZE_K, /* 3346 */ + IC_EVEX_L2_OPSIZE_K, /* 3347 */ + IC_EVEX_L2_OPSIZE_K, /* 3348 */ + IC_EVEX_L2_OPSIZE_K, /* 3349 */ + IC_EVEX_L2_OPSIZE_K, /* 3350 */ + IC_EVEX_L2_OPSIZE_K, /* 3351 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3352 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3353 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3354 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3355 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3356 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3357 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3358 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3359 */ + IC_EVEX_L2_K, /* 3360 */ + IC_EVEX_L2_K, /* 3361 */ + IC_EVEX_L2_XS_K, /* 3362 */ + IC_EVEX_L2_XS_K, /* 3363 */ + IC_EVEX_L2_XD_K, /* 3364 */ + IC_EVEX_L2_XD_K, /* 3365 */ + IC_EVEX_L2_XD_K, /* 3366 */ + IC_EVEX_L2_XD_K, /* 3367 */ + IC_EVEX_L2_W_K, /* 3368 */ + IC_EVEX_L2_W_K, /* 3369 */ + IC_EVEX_L2_W_XS_K, /* 3370 */ + IC_EVEX_L2_W_XS_K, /* 3371 */ + IC_EVEX_L2_W_XD_K, /* 3372 */ + IC_EVEX_L2_W_XD_K, /* 3373 */ + IC_EVEX_L2_W_XD_K, /* 3374 */ + IC_EVEX_L2_W_XD_K, /* 3375 */ + IC_EVEX_L2_OPSIZE_K, /* 3376 */ + IC_EVEX_L2_OPSIZE_K, /* 3377 */ + IC_EVEX_L2_OPSIZE_K, /* 3378 */ + IC_EVEX_L2_OPSIZE_K, /* 3379 */ + IC_EVEX_L2_OPSIZE_K, /* 3380 */ + IC_EVEX_L2_OPSIZE_K, /* 3381 */ + IC_EVEX_L2_OPSIZE_K, /* 3382 */ + IC_EVEX_L2_OPSIZE_K, /* 3383 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3384 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3385 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3386 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3387 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3388 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3389 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3390 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3391 */ + IC_EVEX_L2_K, /* 3392 */ + IC_EVEX_L2_K, /* 3393 */ + IC_EVEX_L2_XS_K, /* 3394 */ + IC_EVEX_L2_XS_K, /* 3395 */ + IC_EVEX_L2_XD_K, /* 3396 */ + IC_EVEX_L2_XD_K, /* 3397 */ + IC_EVEX_L2_XD_K, /* 3398 */ + IC_EVEX_L2_XD_K, /* 3399 */ + IC_EVEX_L2_W_K, /* 3400 */ + IC_EVEX_L2_W_K, /* 3401 */ + IC_EVEX_L2_W_XS_K, /* 3402 */ + IC_EVEX_L2_W_XS_K, /* 3403 */ + IC_EVEX_L2_W_XD_K, /* 3404 */ + IC_EVEX_L2_W_XD_K, /* 3405 */ + IC_EVEX_L2_W_XD_K, /* 3406 */ + IC_EVEX_L2_W_XD_K, /* 3407 */ + IC_EVEX_L2_OPSIZE_K, /* 3408 */ + IC_EVEX_L2_OPSIZE_K, /* 3409 */ + IC_EVEX_L2_OPSIZE_K, /* 3410 */ + IC_EVEX_L2_OPSIZE_K, /* 3411 */ + IC_EVEX_L2_OPSIZE_K, /* 3412 */ + IC_EVEX_L2_OPSIZE_K, /* 3413 */ + IC_EVEX_L2_OPSIZE_K, /* 3414 */ + IC_EVEX_L2_OPSIZE_K, /* 3415 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3416 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3417 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3418 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3419 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3420 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3421 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3422 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3423 */ + IC_EVEX_L2_K, /* 3424 */ + IC_EVEX_L2_K, /* 3425 */ + IC_EVEX_L2_XS_K, /* 3426 */ + IC_EVEX_L2_XS_K, /* 3427 */ + IC_EVEX_L2_XD_K, /* 3428 */ + IC_EVEX_L2_XD_K, /* 3429 */ + IC_EVEX_L2_XD_K, /* 3430 */ + IC_EVEX_L2_XD_K, /* 3431 */ + IC_EVEX_L2_W_K, /* 3432 */ + IC_EVEX_L2_W_K, /* 3433 */ + IC_EVEX_L2_W_XS_K, /* 3434 */ + IC_EVEX_L2_W_XS_K, /* 3435 */ + IC_EVEX_L2_W_XD_K, /* 3436 */ + IC_EVEX_L2_W_XD_K, /* 3437 */ + IC_EVEX_L2_W_XD_K, /* 3438 */ + IC_EVEX_L2_W_XD_K, /* 3439 */ + IC_EVEX_L2_OPSIZE_K, /* 3440 */ + IC_EVEX_L2_OPSIZE_K, /* 3441 */ + IC_EVEX_L2_OPSIZE_K, /* 3442 */ + IC_EVEX_L2_OPSIZE_K, /* 3443 */ + IC_EVEX_L2_OPSIZE_K, /* 3444 */ + IC_EVEX_L2_OPSIZE_K, /* 3445 */ + IC_EVEX_L2_OPSIZE_K, /* 3446 */ + IC_EVEX_L2_OPSIZE_K, /* 3447 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3448 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3449 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3450 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3451 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3452 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3453 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3454 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3455 */ + IC_EVEX_L2_K, /* 3456 */ + IC_EVEX_L2_K, /* 3457 */ + IC_EVEX_L2_XS_K, /* 3458 */ + IC_EVEX_L2_XS_K, /* 3459 */ + IC_EVEX_L2_XD_K, /* 3460 */ + IC_EVEX_L2_XD_K, /* 3461 */ + IC_EVEX_L2_XD_K, /* 3462 */ + IC_EVEX_L2_XD_K, /* 3463 */ + IC_EVEX_L2_W_K, /* 3464 */ + IC_EVEX_L2_W_K, /* 3465 */ + IC_EVEX_L2_W_XS_K, /* 3466 */ + IC_EVEX_L2_W_XS_K, /* 3467 */ + IC_EVEX_L2_W_XD_K, /* 3468 */ + IC_EVEX_L2_W_XD_K, /* 3469 */ + IC_EVEX_L2_W_XD_K, /* 3470 */ + IC_EVEX_L2_W_XD_K, /* 3471 */ + IC_EVEX_L2_OPSIZE_K, /* 3472 */ + IC_EVEX_L2_OPSIZE_K, /* 3473 */ + IC_EVEX_L2_OPSIZE_K, /* 3474 */ + IC_EVEX_L2_OPSIZE_K, /* 3475 */ + IC_EVEX_L2_OPSIZE_K, /* 3476 */ + IC_EVEX_L2_OPSIZE_K, /* 3477 */ + IC_EVEX_L2_OPSIZE_K, /* 3478 */ + IC_EVEX_L2_OPSIZE_K, /* 3479 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3480 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3481 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3482 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3483 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3484 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3485 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3486 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3487 */ + IC_EVEX_L2_K, /* 3488 */ + IC_EVEX_L2_K, /* 3489 */ + IC_EVEX_L2_XS_K, /* 3490 */ + IC_EVEX_L2_XS_K, /* 3491 */ + IC_EVEX_L2_XD_K, /* 3492 */ + IC_EVEX_L2_XD_K, /* 3493 */ + IC_EVEX_L2_XD_K, /* 3494 */ + IC_EVEX_L2_XD_K, /* 3495 */ + IC_EVEX_L2_W_K, /* 3496 */ + IC_EVEX_L2_W_K, /* 3497 */ + IC_EVEX_L2_W_XS_K, /* 3498 */ + IC_EVEX_L2_W_XS_K, /* 3499 */ + IC_EVEX_L2_W_XD_K, /* 3500 */ + IC_EVEX_L2_W_XD_K, /* 3501 */ + IC_EVEX_L2_W_XD_K, /* 3502 */ + IC_EVEX_L2_W_XD_K, /* 3503 */ + IC_EVEX_L2_OPSIZE_K, /* 3504 */ + IC_EVEX_L2_OPSIZE_K, /* 3505 */ + IC_EVEX_L2_OPSIZE_K, /* 3506 */ + IC_EVEX_L2_OPSIZE_K, /* 3507 */ + IC_EVEX_L2_OPSIZE_K, /* 3508 */ + IC_EVEX_L2_OPSIZE_K, /* 3509 */ + IC_EVEX_L2_OPSIZE_K, /* 3510 */ + IC_EVEX_L2_OPSIZE_K, /* 3511 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3512 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3513 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3514 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3515 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3516 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3517 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3518 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3519 */ + IC_EVEX_L2_K, /* 3520 */ + IC_EVEX_L2_K, /* 3521 */ + IC_EVEX_L2_XS_K, /* 3522 */ + IC_EVEX_L2_XS_K, /* 3523 */ + IC_EVEX_L2_XD_K, /* 3524 */ + IC_EVEX_L2_XD_K, /* 3525 */ + IC_EVEX_L2_XD_K, /* 3526 */ + IC_EVEX_L2_XD_K, /* 3527 */ + IC_EVEX_L2_W_K, /* 3528 */ + IC_EVEX_L2_W_K, /* 3529 */ + IC_EVEX_L2_W_XS_K, /* 3530 */ + IC_EVEX_L2_W_XS_K, /* 3531 */ + IC_EVEX_L2_W_XD_K, /* 3532 */ + IC_EVEX_L2_W_XD_K, /* 3533 */ + IC_EVEX_L2_W_XD_K, /* 3534 */ + IC_EVEX_L2_W_XD_K, /* 3535 */ + IC_EVEX_L2_OPSIZE_K, /* 3536 */ + IC_EVEX_L2_OPSIZE_K, /* 3537 */ + IC_EVEX_L2_OPSIZE_K, /* 3538 */ + IC_EVEX_L2_OPSIZE_K, /* 3539 */ + IC_EVEX_L2_OPSIZE_K, /* 3540 */ + IC_EVEX_L2_OPSIZE_K, /* 3541 */ + IC_EVEX_L2_OPSIZE_K, /* 3542 */ + IC_EVEX_L2_OPSIZE_K, /* 3543 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3544 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3545 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3546 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3547 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3548 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3549 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3550 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3551 */ + IC_EVEX_L2_K, /* 3552 */ + IC_EVEX_L2_K, /* 3553 */ + IC_EVEX_L2_XS_K, /* 3554 */ + IC_EVEX_L2_XS_K, /* 3555 */ + IC_EVEX_L2_XD_K, /* 3556 */ + IC_EVEX_L2_XD_K, /* 3557 */ + IC_EVEX_L2_XD_K, /* 3558 */ + IC_EVEX_L2_XD_K, /* 3559 */ + IC_EVEX_L2_W_K, /* 3560 */ + IC_EVEX_L2_W_K, /* 3561 */ + IC_EVEX_L2_W_XS_K, /* 3562 */ + IC_EVEX_L2_W_XS_K, /* 3563 */ + IC_EVEX_L2_W_XD_K, /* 3564 */ + IC_EVEX_L2_W_XD_K, /* 3565 */ + IC_EVEX_L2_W_XD_K, /* 3566 */ + IC_EVEX_L2_W_XD_K, /* 3567 */ + IC_EVEX_L2_OPSIZE_K, /* 3568 */ + IC_EVEX_L2_OPSIZE_K, /* 3569 */ + IC_EVEX_L2_OPSIZE_K, /* 3570 */ + IC_EVEX_L2_OPSIZE_K, /* 3571 */ + IC_EVEX_L2_OPSIZE_K, /* 3572 */ + IC_EVEX_L2_OPSIZE_K, /* 3573 */ + IC_EVEX_L2_OPSIZE_K, /* 3574 */ + IC_EVEX_L2_OPSIZE_K, /* 3575 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3576 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3577 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3578 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3579 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3580 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3581 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3582 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3583 */ + IC, /* 3584 */ + IC_64BIT, /* 3585 */ + IC_XS, /* 3586 */ + IC_64BIT_XS, /* 3587 */ + IC_XD, /* 3588 */ + IC_64BIT_XD, /* 3589 */ + IC_XS, /* 3590 */ + IC_64BIT_XS, /* 3591 */ + IC, /* 3592 */ + IC_64BIT_REXW, /* 3593 */ + IC_XS, /* 3594 */ + IC_64BIT_REXW_XS, /* 3595 */ + IC_XD, /* 3596 */ + IC_64BIT_REXW_XD, /* 3597 */ + IC_XS, /* 3598 */ + IC_64BIT_REXW_XS, /* 3599 */ + IC_OPSIZE, /* 3600 */ + IC_64BIT_OPSIZE, /* 3601 */ + IC_XS_OPSIZE, /* 3602 */ + IC_64BIT_XS_OPSIZE, /* 3603 */ + IC_XD_OPSIZE, /* 3604 */ + IC_64BIT_XD_OPSIZE, /* 3605 */ + IC_XS_OPSIZE, /* 3606 */ + IC_64BIT_XD_OPSIZE, /* 3607 */ + IC_OPSIZE, /* 3608 */ + IC_64BIT_REXW_OPSIZE, /* 3609 */ + IC_XS_OPSIZE, /* 3610 */ + IC_64BIT_REXW_XS, /* 3611 */ + IC_XD_OPSIZE, /* 3612 */ + IC_64BIT_REXW_XD, /* 3613 */ + IC_XS_OPSIZE, /* 3614 */ + IC_64BIT_REXW_XS, /* 3615 */ + IC_ADSIZE, /* 3616 */ + IC_64BIT_ADSIZE, /* 3617 */ + IC_XS_ADSIZE, /* 3618 */ + IC_64BIT_XS_ADSIZE, /* 3619 */ + IC_XD_ADSIZE, /* 3620 */ + IC_64BIT_XD_ADSIZE, /* 3621 */ + IC_XS_ADSIZE, /* 3622 */ + IC_64BIT_XD_ADSIZE, /* 3623 */ + IC_ADSIZE, /* 3624 */ + IC_64BIT_REXW_ADSIZE, /* 3625 */ + IC_XS_ADSIZE, /* 3626 */ + IC_64BIT_REXW_XS, /* 3627 */ + IC_XD_ADSIZE, /* 3628 */ + IC_64BIT_REXW_XD, /* 3629 */ + IC_XS_ADSIZE, /* 3630 */ + IC_64BIT_REXW_XS, /* 3631 */ + IC_OPSIZE_ADSIZE, /* 3632 */ + IC_64BIT_OPSIZE_ADSIZE, /* 3633 */ + IC_XS_OPSIZE, /* 3634 */ + IC_64BIT_XS_OPSIZE, /* 3635 */ + IC_XD_OPSIZE, /* 3636 */ + IC_64BIT_XD_OPSIZE, /* 3637 */ + IC_XS_OPSIZE, /* 3638 */ + IC_64BIT_XD_OPSIZE, /* 3639 */ + IC_OPSIZE_ADSIZE, /* 3640 */ + IC_64BIT_REXW_OPSIZE, /* 3641 */ + IC_XS_OPSIZE, /* 3642 */ + IC_64BIT_REXW_XS, /* 3643 */ + IC_XD_OPSIZE, /* 3644 */ + IC_64BIT_REXW_XD, /* 3645 */ + IC_XS_OPSIZE, /* 3646 */ + IC_64BIT_REXW_XS, /* 3647 */ + IC_VEX, /* 3648 */ + IC_VEX, /* 3649 */ + IC_VEX_XS, /* 3650 */ + IC_VEX_XS, /* 3651 */ + IC_VEX_XD, /* 3652 */ + IC_VEX_XD, /* 3653 */ + IC_VEX_XD, /* 3654 */ + IC_VEX_XD, /* 3655 */ + IC_VEX_W, /* 3656 */ + IC_VEX_W, /* 3657 */ + IC_VEX_W_XS, /* 3658 */ + IC_VEX_W_XS, /* 3659 */ + IC_VEX_W_XD, /* 3660 */ + IC_VEX_W_XD, /* 3661 */ + IC_VEX_W_XD, /* 3662 */ + IC_VEX_W_XD, /* 3663 */ + IC_VEX_OPSIZE, /* 3664 */ + IC_VEX_OPSIZE, /* 3665 */ + IC_VEX_OPSIZE, /* 3666 */ + IC_VEX_OPSIZE, /* 3667 */ + IC_VEX_OPSIZE, /* 3668 */ + IC_VEX_OPSIZE, /* 3669 */ + IC_VEX_OPSIZE, /* 3670 */ + IC_VEX_OPSIZE, /* 3671 */ + IC_VEX_W_OPSIZE, /* 3672 */ + IC_VEX_W_OPSIZE, /* 3673 */ + IC_VEX_W_OPSIZE, /* 3674 */ + IC_VEX_W_OPSIZE, /* 3675 */ + IC_VEX_W_OPSIZE, /* 3676 */ + IC_VEX_W_OPSIZE, /* 3677 */ + IC_VEX_W_OPSIZE, /* 3678 */ + IC_VEX_W_OPSIZE, /* 3679 */ + IC_VEX, /* 3680 */ + IC_VEX, /* 3681 */ + IC_VEX_XS, /* 3682 */ + IC_VEX_XS, /* 3683 */ + IC_VEX_XD, /* 3684 */ + IC_VEX_XD, /* 3685 */ + IC_VEX_XD, /* 3686 */ + IC_VEX_XD, /* 3687 */ + IC_VEX_W, /* 3688 */ + IC_VEX_W, /* 3689 */ + IC_VEX_W_XS, /* 3690 */ + IC_VEX_W_XS, /* 3691 */ + IC_VEX_W_XD, /* 3692 */ + IC_VEX_W_XD, /* 3693 */ + IC_VEX_W_XD, /* 3694 */ + IC_VEX_W_XD, /* 3695 */ + IC_VEX_OPSIZE, /* 3696 */ + IC_VEX_OPSIZE, /* 3697 */ + IC_VEX_OPSIZE, /* 3698 */ + IC_VEX_OPSIZE, /* 3699 */ + IC_VEX_OPSIZE, /* 3700 */ + IC_VEX_OPSIZE, /* 3701 */ + IC_VEX_OPSIZE, /* 3702 */ + IC_VEX_OPSIZE, /* 3703 */ + IC_VEX_W_OPSIZE, /* 3704 */ + IC_VEX_W_OPSIZE, /* 3705 */ + IC_VEX_W_OPSIZE, /* 3706 */ + IC_VEX_W_OPSIZE, /* 3707 */ + IC_VEX_W_OPSIZE, /* 3708 */ + IC_VEX_W_OPSIZE, /* 3709 */ + IC_VEX_W_OPSIZE, /* 3710 */ + IC_VEX_W_OPSIZE, /* 3711 */ + IC_VEX_L, /* 3712 */ + IC_VEX_L, /* 3713 */ + IC_VEX_L_XS, /* 3714 */ + IC_VEX_L_XS, /* 3715 */ + IC_VEX_L_XD, /* 3716 */ + IC_VEX_L_XD, /* 3717 */ + IC_VEX_L_XD, /* 3718 */ + IC_VEX_L_XD, /* 3719 */ + IC_VEX_L_W, /* 3720 */ + IC_VEX_L_W, /* 3721 */ + IC_VEX_L_W_XS, /* 3722 */ + IC_VEX_L_W_XS, /* 3723 */ + IC_VEX_L_W_XD, /* 3724 */ + IC_VEX_L_W_XD, /* 3725 */ + IC_VEX_L_W_XD, /* 3726 */ + IC_VEX_L_W_XD, /* 3727 */ + IC_VEX_L_OPSIZE, /* 3728 */ + IC_VEX_L_OPSIZE, /* 3729 */ + IC_VEX_L_OPSIZE, /* 3730 */ + IC_VEX_L_OPSIZE, /* 3731 */ + IC_VEX_L_OPSIZE, /* 3732 */ + IC_VEX_L_OPSIZE, /* 3733 */ + IC_VEX_L_OPSIZE, /* 3734 */ + IC_VEX_L_OPSIZE, /* 3735 */ + IC_VEX_L_W_OPSIZE, /* 3736 */ + IC_VEX_L_W_OPSIZE, /* 3737 */ + IC_VEX_L_W_OPSIZE, /* 3738 */ + IC_VEX_L_W_OPSIZE, /* 3739 */ + IC_VEX_L_W_OPSIZE, /* 3740 */ + IC_VEX_L_W_OPSIZE, /* 3741 */ + IC_VEX_L_W_OPSIZE, /* 3742 */ + IC_VEX_L_W_OPSIZE, /* 3743 */ + IC_VEX_L, /* 3744 */ + IC_VEX_L, /* 3745 */ + IC_VEX_L_XS, /* 3746 */ + IC_VEX_L_XS, /* 3747 */ + IC_VEX_L_XD, /* 3748 */ + IC_VEX_L_XD, /* 3749 */ + IC_VEX_L_XD, /* 3750 */ + IC_VEX_L_XD, /* 3751 */ + IC_VEX_L_W, /* 3752 */ + IC_VEX_L_W, /* 3753 */ + IC_VEX_L_W_XS, /* 3754 */ + IC_VEX_L_W_XS, /* 3755 */ + IC_VEX_L_W_XD, /* 3756 */ + IC_VEX_L_W_XD, /* 3757 */ + IC_VEX_L_W_XD, /* 3758 */ + IC_VEX_L_W_XD, /* 3759 */ + IC_VEX_L_OPSIZE, /* 3760 */ + IC_VEX_L_OPSIZE, /* 3761 */ + IC_VEX_L_OPSIZE, /* 3762 */ + IC_VEX_L_OPSIZE, /* 3763 */ + IC_VEX_L_OPSIZE, /* 3764 */ + IC_VEX_L_OPSIZE, /* 3765 */ + IC_VEX_L_OPSIZE, /* 3766 */ + IC_VEX_L_OPSIZE, /* 3767 */ + IC_VEX_L_W_OPSIZE, /* 3768 */ + IC_VEX_L_W_OPSIZE, /* 3769 */ + IC_VEX_L_W_OPSIZE, /* 3770 */ + IC_VEX_L_W_OPSIZE, /* 3771 */ + IC_VEX_L_W_OPSIZE, /* 3772 */ + IC_VEX_L_W_OPSIZE, /* 3773 */ + IC_VEX_L_W_OPSIZE, /* 3774 */ + IC_VEX_L_W_OPSIZE, /* 3775 */ + IC_VEX_L, /* 3776 */ + IC_VEX_L, /* 3777 */ + IC_VEX_L_XS, /* 3778 */ + IC_VEX_L_XS, /* 3779 */ + IC_VEX_L_XD, /* 3780 */ + IC_VEX_L_XD, /* 3781 */ + IC_VEX_L_XD, /* 3782 */ + IC_VEX_L_XD, /* 3783 */ + IC_VEX_L_W, /* 3784 */ + IC_VEX_L_W, /* 3785 */ + IC_VEX_L_W_XS, /* 3786 */ + IC_VEX_L_W_XS, /* 3787 */ + IC_VEX_L_W_XD, /* 3788 */ + IC_VEX_L_W_XD, /* 3789 */ + IC_VEX_L_W_XD, /* 3790 */ + IC_VEX_L_W_XD, /* 3791 */ + IC_VEX_L_OPSIZE, /* 3792 */ + IC_VEX_L_OPSIZE, /* 3793 */ + IC_VEX_L_OPSIZE, /* 3794 */ + IC_VEX_L_OPSIZE, /* 3795 */ + IC_VEX_L_OPSIZE, /* 3796 */ + IC_VEX_L_OPSIZE, /* 3797 */ + IC_VEX_L_OPSIZE, /* 3798 */ + IC_VEX_L_OPSIZE, /* 3799 */ + IC_VEX_L_W_OPSIZE, /* 3800 */ + IC_VEX_L_W_OPSIZE, /* 3801 */ + IC_VEX_L_W_OPSIZE, /* 3802 */ + IC_VEX_L_W_OPSIZE, /* 3803 */ + IC_VEX_L_W_OPSIZE, /* 3804 */ + IC_VEX_L_W_OPSIZE, /* 3805 */ + IC_VEX_L_W_OPSIZE, /* 3806 */ + IC_VEX_L_W_OPSIZE, /* 3807 */ + IC_VEX_L, /* 3808 */ + IC_VEX_L, /* 3809 */ + IC_VEX_L_XS, /* 3810 */ + IC_VEX_L_XS, /* 3811 */ + IC_VEX_L_XD, /* 3812 */ + IC_VEX_L_XD, /* 3813 */ + IC_VEX_L_XD, /* 3814 */ + IC_VEX_L_XD, /* 3815 */ + IC_VEX_L_W, /* 3816 */ + IC_VEX_L_W, /* 3817 */ + IC_VEX_L_W_XS, /* 3818 */ + IC_VEX_L_W_XS, /* 3819 */ + IC_VEX_L_W_XD, /* 3820 */ + IC_VEX_L_W_XD, /* 3821 */ + IC_VEX_L_W_XD, /* 3822 */ + IC_VEX_L_W_XD, /* 3823 */ + IC_VEX_L_OPSIZE, /* 3824 */ + IC_VEX_L_OPSIZE, /* 3825 */ + IC_VEX_L_OPSIZE, /* 3826 */ + IC_VEX_L_OPSIZE, /* 3827 */ + IC_VEX_L_OPSIZE, /* 3828 */ + IC_VEX_L_OPSIZE, /* 3829 */ + IC_VEX_L_OPSIZE, /* 3830 */ + IC_VEX_L_OPSIZE, /* 3831 */ + IC_VEX_L_W_OPSIZE, /* 3832 */ + IC_VEX_L_W_OPSIZE, /* 3833 */ + IC_VEX_L_W_OPSIZE, /* 3834 */ + IC_VEX_L_W_OPSIZE, /* 3835 */ + IC_VEX_L_W_OPSIZE, /* 3836 */ + IC_VEX_L_W_OPSIZE, /* 3837 */ + IC_VEX_L_W_OPSIZE, /* 3838 */ + IC_VEX_L_W_OPSIZE, /* 3839 */ + IC_EVEX_L2_K, /* 3840 */ + IC_EVEX_L2_K, /* 3841 */ + IC_EVEX_L2_XS_K, /* 3842 */ + IC_EVEX_L2_XS_K, /* 3843 */ + IC_EVEX_L2_XD_K, /* 3844 */ + IC_EVEX_L2_XD_K, /* 3845 */ + IC_EVEX_L2_XD_K, /* 3846 */ + IC_EVEX_L2_XD_K, /* 3847 */ + IC_EVEX_L2_W_K, /* 3848 */ + IC_EVEX_L2_W_K, /* 3849 */ + IC_EVEX_L2_W_XS_K, /* 3850 */ + IC_EVEX_L2_W_XS_K, /* 3851 */ + IC_EVEX_L2_W_XD_K, /* 3852 */ + IC_EVEX_L2_W_XD_K, /* 3853 */ + IC_EVEX_L2_W_XD_K, /* 3854 */ + IC_EVEX_L2_W_XD_K, /* 3855 */ + IC_EVEX_L2_OPSIZE_K, /* 3856 */ + IC_EVEX_L2_OPSIZE_K, /* 3857 */ + IC_EVEX_L2_OPSIZE_K, /* 3858 */ + IC_EVEX_L2_OPSIZE_K, /* 3859 */ + IC_EVEX_L2_OPSIZE_K, /* 3860 */ + IC_EVEX_L2_OPSIZE_K, /* 3861 */ + IC_EVEX_L2_OPSIZE_K, /* 3862 */ + IC_EVEX_L2_OPSIZE_K, /* 3863 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3864 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3865 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3866 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3867 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3868 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3869 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3870 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3871 */ + IC_EVEX_L2_K, /* 3872 */ + IC_EVEX_L2_K, /* 3873 */ + IC_EVEX_L2_XS_K, /* 3874 */ + IC_EVEX_L2_XS_K, /* 3875 */ + IC_EVEX_L2_XD_K, /* 3876 */ + IC_EVEX_L2_XD_K, /* 3877 */ + IC_EVEX_L2_XD_K, /* 3878 */ + IC_EVEX_L2_XD_K, /* 3879 */ + IC_EVEX_L2_W_K, /* 3880 */ + IC_EVEX_L2_W_K, /* 3881 */ + IC_EVEX_L2_W_XS_K, /* 3882 */ + IC_EVEX_L2_W_XS_K, /* 3883 */ + IC_EVEX_L2_W_XD_K, /* 3884 */ + IC_EVEX_L2_W_XD_K, /* 3885 */ + IC_EVEX_L2_W_XD_K, /* 3886 */ + IC_EVEX_L2_W_XD_K, /* 3887 */ + IC_EVEX_L2_OPSIZE_K, /* 3888 */ + IC_EVEX_L2_OPSIZE_K, /* 3889 */ + IC_EVEX_L2_OPSIZE_K, /* 3890 */ + IC_EVEX_L2_OPSIZE_K, /* 3891 */ + IC_EVEX_L2_OPSIZE_K, /* 3892 */ + IC_EVEX_L2_OPSIZE_K, /* 3893 */ + IC_EVEX_L2_OPSIZE_K, /* 3894 */ + IC_EVEX_L2_OPSIZE_K, /* 3895 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3896 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3897 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3898 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3899 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3900 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3901 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3902 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3903 */ + IC_EVEX_L2_K, /* 3904 */ + IC_EVEX_L2_K, /* 3905 */ + IC_EVEX_L2_XS_K, /* 3906 */ + IC_EVEX_L2_XS_K, /* 3907 */ + IC_EVEX_L2_XD_K, /* 3908 */ + IC_EVEX_L2_XD_K, /* 3909 */ + IC_EVEX_L2_XD_K, /* 3910 */ + IC_EVEX_L2_XD_K, /* 3911 */ + IC_EVEX_L2_W_K, /* 3912 */ + IC_EVEX_L2_W_K, /* 3913 */ + IC_EVEX_L2_W_XS_K, /* 3914 */ + IC_EVEX_L2_W_XS_K, /* 3915 */ + IC_EVEX_L2_W_XD_K, /* 3916 */ + IC_EVEX_L2_W_XD_K, /* 3917 */ + IC_EVEX_L2_W_XD_K, /* 3918 */ + IC_EVEX_L2_W_XD_K, /* 3919 */ + IC_EVEX_L2_OPSIZE_K, /* 3920 */ + IC_EVEX_L2_OPSIZE_K, /* 3921 */ + IC_EVEX_L2_OPSIZE_K, /* 3922 */ + IC_EVEX_L2_OPSIZE_K, /* 3923 */ + IC_EVEX_L2_OPSIZE_K, /* 3924 */ + IC_EVEX_L2_OPSIZE_K, /* 3925 */ + IC_EVEX_L2_OPSIZE_K, /* 3926 */ + IC_EVEX_L2_OPSIZE_K, /* 3927 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3928 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3929 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3930 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3931 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3932 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3933 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3934 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3935 */ + IC_EVEX_L2_K, /* 3936 */ + IC_EVEX_L2_K, /* 3937 */ + IC_EVEX_L2_XS_K, /* 3938 */ + IC_EVEX_L2_XS_K, /* 3939 */ + IC_EVEX_L2_XD_K, /* 3940 */ + IC_EVEX_L2_XD_K, /* 3941 */ + IC_EVEX_L2_XD_K, /* 3942 */ + IC_EVEX_L2_XD_K, /* 3943 */ + IC_EVEX_L2_W_K, /* 3944 */ + IC_EVEX_L2_W_K, /* 3945 */ + IC_EVEX_L2_W_XS_K, /* 3946 */ + IC_EVEX_L2_W_XS_K, /* 3947 */ + IC_EVEX_L2_W_XD_K, /* 3948 */ + IC_EVEX_L2_W_XD_K, /* 3949 */ + IC_EVEX_L2_W_XD_K, /* 3950 */ + IC_EVEX_L2_W_XD_K, /* 3951 */ + IC_EVEX_L2_OPSIZE_K, /* 3952 */ + IC_EVEX_L2_OPSIZE_K, /* 3953 */ + IC_EVEX_L2_OPSIZE_K, /* 3954 */ + IC_EVEX_L2_OPSIZE_K, /* 3955 */ + IC_EVEX_L2_OPSIZE_K, /* 3956 */ + IC_EVEX_L2_OPSIZE_K, /* 3957 */ + IC_EVEX_L2_OPSIZE_K, /* 3958 */ + IC_EVEX_L2_OPSIZE_K, /* 3959 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3960 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3961 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3962 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3963 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3964 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3965 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3966 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3967 */ + IC_EVEX_L2_K, /* 3968 */ + IC_EVEX_L2_K, /* 3969 */ + IC_EVEX_L2_XS_K, /* 3970 */ + IC_EVEX_L2_XS_K, /* 3971 */ + IC_EVEX_L2_XD_K, /* 3972 */ + IC_EVEX_L2_XD_K, /* 3973 */ + IC_EVEX_L2_XD_K, /* 3974 */ + IC_EVEX_L2_XD_K, /* 3975 */ + IC_EVEX_L2_W_K, /* 3976 */ + IC_EVEX_L2_W_K, /* 3977 */ + IC_EVEX_L2_W_XS_K, /* 3978 */ + IC_EVEX_L2_W_XS_K, /* 3979 */ + IC_EVEX_L2_W_XD_K, /* 3980 */ + IC_EVEX_L2_W_XD_K, /* 3981 */ + IC_EVEX_L2_W_XD_K, /* 3982 */ + IC_EVEX_L2_W_XD_K, /* 3983 */ + IC_EVEX_L2_OPSIZE_K, /* 3984 */ + IC_EVEX_L2_OPSIZE_K, /* 3985 */ + IC_EVEX_L2_OPSIZE_K, /* 3986 */ + IC_EVEX_L2_OPSIZE_K, /* 3987 */ + IC_EVEX_L2_OPSIZE_K, /* 3988 */ + IC_EVEX_L2_OPSIZE_K, /* 3989 */ + IC_EVEX_L2_OPSIZE_K, /* 3990 */ + IC_EVEX_L2_OPSIZE_K, /* 3991 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3992 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3993 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3994 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3995 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3996 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3997 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3998 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3999 */ + IC_EVEX_L2_K, /* 4000 */ + IC_EVEX_L2_K, /* 4001 */ + IC_EVEX_L2_XS_K, /* 4002 */ + IC_EVEX_L2_XS_K, /* 4003 */ + IC_EVEX_L2_XD_K, /* 4004 */ + IC_EVEX_L2_XD_K, /* 4005 */ + IC_EVEX_L2_XD_K, /* 4006 */ + IC_EVEX_L2_XD_K, /* 4007 */ + IC_EVEX_L2_W_K, /* 4008 */ + IC_EVEX_L2_W_K, /* 4009 */ + IC_EVEX_L2_W_XS_K, /* 4010 */ + IC_EVEX_L2_W_XS_K, /* 4011 */ + IC_EVEX_L2_W_XD_K, /* 4012 */ + IC_EVEX_L2_W_XD_K, /* 4013 */ + IC_EVEX_L2_W_XD_K, /* 4014 */ + IC_EVEX_L2_W_XD_K, /* 4015 */ + IC_EVEX_L2_OPSIZE_K, /* 4016 */ + IC_EVEX_L2_OPSIZE_K, /* 4017 */ + IC_EVEX_L2_OPSIZE_K, /* 4018 */ + IC_EVEX_L2_OPSIZE_K, /* 4019 */ + IC_EVEX_L2_OPSIZE_K, /* 4020 */ + IC_EVEX_L2_OPSIZE_K, /* 4021 */ + IC_EVEX_L2_OPSIZE_K, /* 4022 */ + IC_EVEX_L2_OPSIZE_K, /* 4023 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4024 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4025 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4026 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4027 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4028 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4029 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4030 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4031 */ + IC_EVEX_L2_K, /* 4032 */ + IC_EVEX_L2_K, /* 4033 */ + IC_EVEX_L2_XS_K, /* 4034 */ + IC_EVEX_L2_XS_K, /* 4035 */ + IC_EVEX_L2_XD_K, /* 4036 */ + IC_EVEX_L2_XD_K, /* 4037 */ + IC_EVEX_L2_XD_K, /* 4038 */ + IC_EVEX_L2_XD_K, /* 4039 */ + IC_EVEX_L2_W_K, /* 4040 */ + IC_EVEX_L2_W_K, /* 4041 */ + IC_EVEX_L2_W_XS_K, /* 4042 */ + IC_EVEX_L2_W_XS_K, /* 4043 */ + IC_EVEX_L2_W_XD_K, /* 4044 */ + IC_EVEX_L2_W_XD_K, /* 4045 */ + IC_EVEX_L2_W_XD_K, /* 4046 */ + IC_EVEX_L2_W_XD_K, /* 4047 */ + IC_EVEX_L2_OPSIZE_K, /* 4048 */ + IC_EVEX_L2_OPSIZE_K, /* 4049 */ + IC_EVEX_L2_OPSIZE_K, /* 4050 */ + IC_EVEX_L2_OPSIZE_K, /* 4051 */ + IC_EVEX_L2_OPSIZE_K, /* 4052 */ + IC_EVEX_L2_OPSIZE_K, /* 4053 */ + IC_EVEX_L2_OPSIZE_K, /* 4054 */ + IC_EVEX_L2_OPSIZE_K, /* 4055 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4056 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4057 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4058 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4059 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4060 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4061 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4062 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4063 */ + IC_EVEX_L2_K, /* 4064 */ + IC_EVEX_L2_K, /* 4065 */ + IC_EVEX_L2_XS_K, /* 4066 */ + IC_EVEX_L2_XS_K, /* 4067 */ + IC_EVEX_L2_XD_K, /* 4068 */ + IC_EVEX_L2_XD_K, /* 4069 */ + IC_EVEX_L2_XD_K, /* 4070 */ + IC_EVEX_L2_XD_K, /* 4071 */ + IC_EVEX_L2_W_K, /* 4072 */ + IC_EVEX_L2_W_K, /* 4073 */ + IC_EVEX_L2_W_XS_K, /* 4074 */ + IC_EVEX_L2_W_XS_K, /* 4075 */ + IC_EVEX_L2_W_XD_K, /* 4076 */ + IC_EVEX_L2_W_XD_K, /* 4077 */ + IC_EVEX_L2_W_XD_K, /* 4078 */ + IC_EVEX_L2_W_XD_K, /* 4079 */ + IC_EVEX_L2_OPSIZE_K, /* 4080 */ + IC_EVEX_L2_OPSIZE_K, /* 4081 */ + IC_EVEX_L2_OPSIZE_K, /* 4082 */ + IC_EVEX_L2_OPSIZE_K, /* 4083 */ + IC_EVEX_L2_OPSIZE_K, /* 4084 */ + IC_EVEX_L2_OPSIZE_K, /* 4085 */ + IC_EVEX_L2_OPSIZE_K, /* 4086 */ + IC_EVEX_L2_OPSIZE_K, /* 4087 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4088 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4089 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4090 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4091 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4092 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4093 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4094 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4095 */ + IC, /* 4096 */ + IC_64BIT, /* 4097 */ + IC_XS, /* 4098 */ + IC_64BIT_XS, /* 4099 */ + IC_XD, /* 4100 */ + IC_64BIT_XD, /* 4101 */ + IC_XS, /* 4102 */ + IC_64BIT_XS, /* 4103 */ + IC, /* 4104 */ + IC_64BIT_REXW, /* 4105 */ + IC_XS, /* 4106 */ + IC_64BIT_REXW_XS, /* 4107 */ + IC_XD, /* 4108 */ + IC_64BIT_REXW_XD, /* 4109 */ + IC_XS, /* 4110 */ + IC_64BIT_REXW_XS, /* 4111 */ + IC_OPSIZE, /* 4112 */ + IC_64BIT_OPSIZE, /* 4113 */ + IC_XS_OPSIZE, /* 4114 */ + IC_64BIT_XS_OPSIZE, /* 4115 */ + IC_XD_OPSIZE, /* 4116 */ + IC_64BIT_XD_OPSIZE, /* 4117 */ + IC_XS_OPSIZE, /* 4118 */ + IC_64BIT_XD_OPSIZE, /* 4119 */ + IC_OPSIZE, /* 4120 */ + IC_64BIT_REXW_OPSIZE, /* 4121 */ + IC_XS_OPSIZE, /* 4122 */ + IC_64BIT_REXW_XS, /* 4123 */ + IC_XD_OPSIZE, /* 4124 */ + IC_64BIT_REXW_XD, /* 4125 */ + IC_XS_OPSIZE, /* 4126 */ + IC_64BIT_REXW_XS, /* 4127 */ + IC_ADSIZE, /* 4128 */ + IC_64BIT_ADSIZE, /* 4129 */ + IC_XS_ADSIZE, /* 4130 */ + IC_64BIT_XS_ADSIZE, /* 4131 */ + IC_XD_ADSIZE, /* 4132 */ + IC_64BIT_XD_ADSIZE, /* 4133 */ + IC_XS_ADSIZE, /* 4134 */ + IC_64BIT_XD_ADSIZE, /* 4135 */ + IC_ADSIZE, /* 4136 */ + IC_64BIT_REXW_ADSIZE, /* 4137 */ + IC_XS_ADSIZE, /* 4138 */ + IC_64BIT_REXW_XS, /* 4139 */ + IC_XD_ADSIZE, /* 4140 */ + IC_64BIT_REXW_XD, /* 4141 */ + IC_XS_ADSIZE, /* 4142 */ + IC_64BIT_REXW_XS, /* 4143 */ + IC_OPSIZE_ADSIZE, /* 4144 */ + IC_64BIT_OPSIZE_ADSIZE, /* 4145 */ + IC_XS_OPSIZE, /* 4146 */ + IC_64BIT_XS_OPSIZE, /* 4147 */ + IC_XD_OPSIZE, /* 4148 */ + IC_64BIT_XD_OPSIZE, /* 4149 */ + IC_XS_OPSIZE, /* 4150 */ + IC_64BIT_XD_OPSIZE, /* 4151 */ + IC_OPSIZE_ADSIZE, /* 4152 */ + IC_64BIT_REXW_OPSIZE, /* 4153 */ + IC_XS_OPSIZE, /* 4154 */ + IC_64BIT_REXW_XS, /* 4155 */ + IC_XD_OPSIZE, /* 4156 */ + IC_64BIT_REXW_XD, /* 4157 */ + IC_XS_OPSIZE, /* 4158 */ + IC_64BIT_REXW_XS, /* 4159 */ + IC_VEX, /* 4160 */ + IC_VEX, /* 4161 */ + IC_VEX_XS, /* 4162 */ + IC_VEX_XS, /* 4163 */ + IC_VEX_XD, /* 4164 */ + IC_VEX_XD, /* 4165 */ + IC_VEX_XD, /* 4166 */ + IC_VEX_XD, /* 4167 */ + IC_VEX_W, /* 4168 */ + IC_VEX_W, /* 4169 */ + IC_VEX_W_XS, /* 4170 */ + IC_VEX_W_XS, /* 4171 */ + IC_VEX_W_XD, /* 4172 */ + IC_VEX_W_XD, /* 4173 */ + IC_VEX_W_XD, /* 4174 */ + IC_VEX_W_XD, /* 4175 */ + IC_VEX_OPSIZE, /* 4176 */ + IC_VEX_OPSIZE, /* 4177 */ + IC_VEX_OPSIZE, /* 4178 */ + IC_VEX_OPSIZE, /* 4179 */ + IC_VEX_OPSIZE, /* 4180 */ + IC_VEX_OPSIZE, /* 4181 */ + IC_VEX_OPSIZE, /* 4182 */ + IC_VEX_OPSIZE, /* 4183 */ + IC_VEX_W_OPSIZE, /* 4184 */ + IC_VEX_W_OPSIZE, /* 4185 */ + IC_VEX_W_OPSIZE, /* 4186 */ + IC_VEX_W_OPSIZE, /* 4187 */ + IC_VEX_W_OPSIZE, /* 4188 */ + IC_VEX_W_OPSIZE, /* 4189 */ + IC_VEX_W_OPSIZE, /* 4190 */ + IC_VEX_W_OPSIZE, /* 4191 */ + IC_VEX, /* 4192 */ + IC_VEX, /* 4193 */ + IC_VEX_XS, /* 4194 */ + IC_VEX_XS, /* 4195 */ + IC_VEX_XD, /* 4196 */ + IC_VEX_XD, /* 4197 */ + IC_VEX_XD, /* 4198 */ + IC_VEX_XD, /* 4199 */ + IC_VEX_W, /* 4200 */ + IC_VEX_W, /* 4201 */ + IC_VEX_W_XS, /* 4202 */ + IC_VEX_W_XS, /* 4203 */ + IC_VEX_W_XD, /* 4204 */ + IC_VEX_W_XD, /* 4205 */ + IC_VEX_W_XD, /* 4206 */ + IC_VEX_W_XD, /* 4207 */ + IC_VEX_OPSIZE, /* 4208 */ + IC_VEX_OPSIZE, /* 4209 */ + IC_VEX_OPSIZE, /* 4210 */ + IC_VEX_OPSIZE, /* 4211 */ + IC_VEX_OPSIZE, /* 4212 */ + IC_VEX_OPSIZE, /* 4213 */ + IC_VEX_OPSIZE, /* 4214 */ + IC_VEX_OPSIZE, /* 4215 */ + IC_VEX_W_OPSIZE, /* 4216 */ + IC_VEX_W_OPSIZE, /* 4217 */ + IC_VEX_W_OPSIZE, /* 4218 */ + IC_VEX_W_OPSIZE, /* 4219 */ + IC_VEX_W_OPSIZE, /* 4220 */ + IC_VEX_W_OPSIZE, /* 4221 */ + IC_VEX_W_OPSIZE, /* 4222 */ + IC_VEX_W_OPSIZE, /* 4223 */ + IC_VEX_L, /* 4224 */ + IC_VEX_L, /* 4225 */ + IC_VEX_L_XS, /* 4226 */ + IC_VEX_L_XS, /* 4227 */ + IC_VEX_L_XD, /* 4228 */ + IC_VEX_L_XD, /* 4229 */ + IC_VEX_L_XD, /* 4230 */ + IC_VEX_L_XD, /* 4231 */ + IC_VEX_L_W, /* 4232 */ + IC_VEX_L_W, /* 4233 */ + IC_VEX_L_W_XS, /* 4234 */ + IC_VEX_L_W_XS, /* 4235 */ + IC_VEX_L_W_XD, /* 4236 */ + IC_VEX_L_W_XD, /* 4237 */ + IC_VEX_L_W_XD, /* 4238 */ + IC_VEX_L_W_XD, /* 4239 */ + IC_VEX_L_OPSIZE, /* 4240 */ + IC_VEX_L_OPSIZE, /* 4241 */ + IC_VEX_L_OPSIZE, /* 4242 */ + IC_VEX_L_OPSIZE, /* 4243 */ + IC_VEX_L_OPSIZE, /* 4244 */ + IC_VEX_L_OPSIZE, /* 4245 */ + IC_VEX_L_OPSIZE, /* 4246 */ + IC_VEX_L_OPSIZE, /* 4247 */ + IC_VEX_L_W_OPSIZE, /* 4248 */ + IC_VEX_L_W_OPSIZE, /* 4249 */ + IC_VEX_L_W_OPSIZE, /* 4250 */ + IC_VEX_L_W_OPSIZE, /* 4251 */ + IC_VEX_L_W_OPSIZE, /* 4252 */ + IC_VEX_L_W_OPSIZE, /* 4253 */ + IC_VEX_L_W_OPSIZE, /* 4254 */ + IC_VEX_L_W_OPSIZE, /* 4255 */ + IC_VEX_L, /* 4256 */ + IC_VEX_L, /* 4257 */ + IC_VEX_L_XS, /* 4258 */ + IC_VEX_L_XS, /* 4259 */ + IC_VEX_L_XD, /* 4260 */ + IC_VEX_L_XD, /* 4261 */ + IC_VEX_L_XD, /* 4262 */ + IC_VEX_L_XD, /* 4263 */ + IC_VEX_L_W, /* 4264 */ + IC_VEX_L_W, /* 4265 */ + IC_VEX_L_W_XS, /* 4266 */ + IC_VEX_L_W_XS, /* 4267 */ + IC_VEX_L_W_XD, /* 4268 */ + IC_VEX_L_W_XD, /* 4269 */ + IC_VEX_L_W_XD, /* 4270 */ + IC_VEX_L_W_XD, /* 4271 */ + IC_VEX_L_OPSIZE, /* 4272 */ + IC_VEX_L_OPSIZE, /* 4273 */ + IC_VEX_L_OPSIZE, /* 4274 */ + IC_VEX_L_OPSIZE, /* 4275 */ + IC_VEX_L_OPSIZE, /* 4276 */ + IC_VEX_L_OPSIZE, /* 4277 */ + IC_VEX_L_OPSIZE, /* 4278 */ + IC_VEX_L_OPSIZE, /* 4279 */ + IC_VEX_L_W_OPSIZE, /* 4280 */ + IC_VEX_L_W_OPSIZE, /* 4281 */ + IC_VEX_L_W_OPSIZE, /* 4282 */ + IC_VEX_L_W_OPSIZE, /* 4283 */ + IC_VEX_L_W_OPSIZE, /* 4284 */ + IC_VEX_L_W_OPSIZE, /* 4285 */ + IC_VEX_L_W_OPSIZE, /* 4286 */ + IC_VEX_L_W_OPSIZE, /* 4287 */ + IC_VEX_L, /* 4288 */ + IC_VEX_L, /* 4289 */ + IC_VEX_L_XS, /* 4290 */ + IC_VEX_L_XS, /* 4291 */ + IC_VEX_L_XD, /* 4292 */ + IC_VEX_L_XD, /* 4293 */ + IC_VEX_L_XD, /* 4294 */ + IC_VEX_L_XD, /* 4295 */ + IC_VEX_L_W, /* 4296 */ + IC_VEX_L_W, /* 4297 */ + IC_VEX_L_W_XS, /* 4298 */ + IC_VEX_L_W_XS, /* 4299 */ + IC_VEX_L_W_XD, /* 4300 */ + IC_VEX_L_W_XD, /* 4301 */ + IC_VEX_L_W_XD, /* 4302 */ + IC_VEX_L_W_XD, /* 4303 */ + IC_VEX_L_OPSIZE, /* 4304 */ + IC_VEX_L_OPSIZE, /* 4305 */ + IC_VEX_L_OPSIZE, /* 4306 */ + IC_VEX_L_OPSIZE, /* 4307 */ + IC_VEX_L_OPSIZE, /* 4308 */ + IC_VEX_L_OPSIZE, /* 4309 */ + IC_VEX_L_OPSIZE, /* 4310 */ + IC_VEX_L_OPSIZE, /* 4311 */ + IC_VEX_L_W_OPSIZE, /* 4312 */ + IC_VEX_L_W_OPSIZE, /* 4313 */ + IC_VEX_L_W_OPSIZE, /* 4314 */ + IC_VEX_L_W_OPSIZE, /* 4315 */ + IC_VEX_L_W_OPSIZE, /* 4316 */ + IC_VEX_L_W_OPSIZE, /* 4317 */ + IC_VEX_L_W_OPSIZE, /* 4318 */ + IC_VEX_L_W_OPSIZE, /* 4319 */ + IC_VEX_L, /* 4320 */ + IC_VEX_L, /* 4321 */ + IC_VEX_L_XS, /* 4322 */ + IC_VEX_L_XS, /* 4323 */ + IC_VEX_L_XD, /* 4324 */ + IC_VEX_L_XD, /* 4325 */ + IC_VEX_L_XD, /* 4326 */ + IC_VEX_L_XD, /* 4327 */ + IC_VEX_L_W, /* 4328 */ + IC_VEX_L_W, /* 4329 */ + IC_VEX_L_W_XS, /* 4330 */ + IC_VEX_L_W_XS, /* 4331 */ + IC_VEX_L_W_XD, /* 4332 */ + IC_VEX_L_W_XD, /* 4333 */ + IC_VEX_L_W_XD, /* 4334 */ + IC_VEX_L_W_XD, /* 4335 */ + IC_VEX_L_OPSIZE, /* 4336 */ + IC_VEX_L_OPSIZE, /* 4337 */ + IC_VEX_L_OPSIZE, /* 4338 */ + IC_VEX_L_OPSIZE, /* 4339 */ + IC_VEX_L_OPSIZE, /* 4340 */ + IC_VEX_L_OPSIZE, /* 4341 */ + IC_VEX_L_OPSIZE, /* 4342 */ + IC_VEX_L_OPSIZE, /* 4343 */ + IC_VEX_L_W_OPSIZE, /* 4344 */ + IC_VEX_L_W_OPSIZE, /* 4345 */ + IC_VEX_L_W_OPSIZE, /* 4346 */ + IC_VEX_L_W_OPSIZE, /* 4347 */ + IC_VEX_L_W_OPSIZE, /* 4348 */ + IC_VEX_L_W_OPSIZE, /* 4349 */ + IC_VEX_L_W_OPSIZE, /* 4350 */ + IC_VEX_L_W_OPSIZE, /* 4351 */ + IC_EVEX_KZ, /* 4352 */ + IC_EVEX_KZ, /* 4353 */ + IC_EVEX_XS_KZ, /* 4354 */ + IC_EVEX_XS_KZ, /* 4355 */ + IC_EVEX_XD_KZ, /* 4356 */ + IC_EVEX_XD_KZ, /* 4357 */ + IC_EVEX_XD_KZ, /* 4358 */ + IC_EVEX_XD_KZ, /* 4359 */ + IC_EVEX_W_KZ, /* 4360 */ + IC_EVEX_W_KZ, /* 4361 */ + IC_EVEX_W_XS_KZ, /* 4362 */ + IC_EVEX_W_XS_KZ, /* 4363 */ + IC_EVEX_W_XD_KZ, /* 4364 */ + IC_EVEX_W_XD_KZ, /* 4365 */ + IC_EVEX_W_XD_KZ, /* 4366 */ + IC_EVEX_W_XD_KZ, /* 4367 */ + IC_EVEX_OPSIZE_KZ, /* 4368 */ + IC_EVEX_OPSIZE_KZ, /* 4369 */ + IC_EVEX_OPSIZE_KZ, /* 4370 */ + IC_EVEX_OPSIZE_KZ, /* 4371 */ + IC_EVEX_OPSIZE_KZ, /* 4372 */ + IC_EVEX_OPSIZE_KZ, /* 4373 */ + IC_EVEX_OPSIZE_KZ, /* 4374 */ + IC_EVEX_OPSIZE_KZ, /* 4375 */ + IC_EVEX_W_OPSIZE_KZ, /* 4376 */ + IC_EVEX_W_OPSIZE_KZ, /* 4377 */ + IC_EVEX_W_OPSIZE_KZ, /* 4378 */ + IC_EVEX_W_OPSIZE_KZ, /* 4379 */ + IC_EVEX_W_OPSIZE_KZ, /* 4380 */ + IC_EVEX_W_OPSIZE_KZ, /* 4381 */ + IC_EVEX_W_OPSIZE_KZ, /* 4382 */ + IC_EVEX_W_OPSIZE_KZ, /* 4383 */ + IC_EVEX_KZ, /* 4384 */ + IC_EVEX_KZ, /* 4385 */ + IC_EVEX_XS_KZ, /* 4386 */ + IC_EVEX_XS_KZ, /* 4387 */ + IC_EVEX_XD_KZ, /* 4388 */ + IC_EVEX_XD_KZ, /* 4389 */ + IC_EVEX_XD_KZ, /* 4390 */ + IC_EVEX_XD_KZ, /* 4391 */ + IC_EVEX_W_KZ, /* 4392 */ + IC_EVEX_W_KZ, /* 4393 */ + IC_EVEX_W_XS_KZ, /* 4394 */ + IC_EVEX_W_XS_KZ, /* 4395 */ + IC_EVEX_W_XD_KZ, /* 4396 */ + IC_EVEX_W_XD_KZ, /* 4397 */ + IC_EVEX_W_XD_KZ, /* 4398 */ + IC_EVEX_W_XD_KZ, /* 4399 */ + IC_EVEX_OPSIZE_KZ, /* 4400 */ + IC_EVEX_OPSIZE_KZ, /* 4401 */ + IC_EVEX_OPSIZE_KZ, /* 4402 */ + IC_EVEX_OPSIZE_KZ, /* 4403 */ + IC_EVEX_OPSIZE_KZ, /* 4404 */ + IC_EVEX_OPSIZE_KZ, /* 4405 */ + IC_EVEX_OPSIZE_KZ, /* 4406 */ + IC_EVEX_OPSIZE_KZ, /* 4407 */ + IC_EVEX_W_OPSIZE_KZ, /* 4408 */ + IC_EVEX_W_OPSIZE_KZ, /* 4409 */ + IC_EVEX_W_OPSIZE_KZ, /* 4410 */ + IC_EVEX_W_OPSIZE_KZ, /* 4411 */ + IC_EVEX_W_OPSIZE_KZ, /* 4412 */ + IC_EVEX_W_OPSIZE_KZ, /* 4413 */ + IC_EVEX_W_OPSIZE_KZ, /* 4414 */ + IC_EVEX_W_OPSIZE_KZ, /* 4415 */ + IC_EVEX_KZ, /* 4416 */ + IC_EVEX_KZ, /* 4417 */ + IC_EVEX_XS_KZ, /* 4418 */ + IC_EVEX_XS_KZ, /* 4419 */ + IC_EVEX_XD_KZ, /* 4420 */ + IC_EVEX_XD_KZ, /* 4421 */ + IC_EVEX_XD_KZ, /* 4422 */ + IC_EVEX_XD_KZ, /* 4423 */ + IC_EVEX_W_KZ, /* 4424 */ + IC_EVEX_W_KZ, /* 4425 */ + IC_EVEX_W_XS_KZ, /* 4426 */ + IC_EVEX_W_XS_KZ, /* 4427 */ + IC_EVEX_W_XD_KZ, /* 4428 */ + IC_EVEX_W_XD_KZ, /* 4429 */ + IC_EVEX_W_XD_KZ, /* 4430 */ + IC_EVEX_W_XD_KZ, /* 4431 */ + IC_EVEX_OPSIZE_KZ, /* 4432 */ + IC_EVEX_OPSIZE_KZ, /* 4433 */ + IC_EVEX_OPSIZE_KZ, /* 4434 */ + IC_EVEX_OPSIZE_KZ, /* 4435 */ + IC_EVEX_OPSIZE_KZ, /* 4436 */ + IC_EVEX_OPSIZE_KZ, /* 4437 */ + IC_EVEX_OPSIZE_KZ, /* 4438 */ + IC_EVEX_OPSIZE_KZ, /* 4439 */ + IC_EVEX_W_OPSIZE_KZ, /* 4440 */ + IC_EVEX_W_OPSIZE_KZ, /* 4441 */ + IC_EVEX_W_OPSIZE_KZ, /* 4442 */ + IC_EVEX_W_OPSIZE_KZ, /* 4443 */ + IC_EVEX_W_OPSIZE_KZ, /* 4444 */ + IC_EVEX_W_OPSIZE_KZ, /* 4445 */ + IC_EVEX_W_OPSIZE_KZ, /* 4446 */ + IC_EVEX_W_OPSIZE_KZ, /* 4447 */ + IC_EVEX_KZ, /* 4448 */ + IC_EVEX_KZ, /* 4449 */ + IC_EVEX_XS_KZ, /* 4450 */ + IC_EVEX_XS_KZ, /* 4451 */ + IC_EVEX_XD_KZ, /* 4452 */ + IC_EVEX_XD_KZ, /* 4453 */ + IC_EVEX_XD_KZ, /* 4454 */ + IC_EVEX_XD_KZ, /* 4455 */ + IC_EVEX_W_KZ, /* 4456 */ + IC_EVEX_W_KZ, /* 4457 */ + IC_EVEX_W_XS_KZ, /* 4458 */ + IC_EVEX_W_XS_KZ, /* 4459 */ + IC_EVEX_W_XD_KZ, /* 4460 */ + IC_EVEX_W_XD_KZ, /* 4461 */ + IC_EVEX_W_XD_KZ, /* 4462 */ + IC_EVEX_W_XD_KZ, /* 4463 */ + IC_EVEX_OPSIZE_KZ, /* 4464 */ + IC_EVEX_OPSIZE_KZ, /* 4465 */ + IC_EVEX_OPSIZE_KZ, /* 4466 */ + IC_EVEX_OPSIZE_KZ, /* 4467 */ + IC_EVEX_OPSIZE_KZ, /* 4468 */ + IC_EVEX_OPSIZE_KZ, /* 4469 */ + IC_EVEX_OPSIZE_KZ, /* 4470 */ + IC_EVEX_OPSIZE_KZ, /* 4471 */ + IC_EVEX_W_OPSIZE_KZ, /* 4472 */ + IC_EVEX_W_OPSIZE_KZ, /* 4473 */ + IC_EVEX_W_OPSIZE_KZ, /* 4474 */ + IC_EVEX_W_OPSIZE_KZ, /* 4475 */ + IC_EVEX_W_OPSIZE_KZ, /* 4476 */ + IC_EVEX_W_OPSIZE_KZ, /* 4477 */ + IC_EVEX_W_OPSIZE_KZ, /* 4478 */ + IC_EVEX_W_OPSIZE_KZ, /* 4479 */ + IC_EVEX_KZ, /* 4480 */ + IC_EVEX_KZ, /* 4481 */ + IC_EVEX_XS_KZ, /* 4482 */ + IC_EVEX_XS_KZ, /* 4483 */ + IC_EVEX_XD_KZ, /* 4484 */ + IC_EVEX_XD_KZ, /* 4485 */ + IC_EVEX_XD_KZ, /* 4486 */ + IC_EVEX_XD_KZ, /* 4487 */ + IC_EVEX_W_KZ, /* 4488 */ + IC_EVEX_W_KZ, /* 4489 */ + IC_EVEX_W_XS_KZ, /* 4490 */ + IC_EVEX_W_XS_KZ, /* 4491 */ + IC_EVEX_W_XD_KZ, /* 4492 */ + IC_EVEX_W_XD_KZ, /* 4493 */ + IC_EVEX_W_XD_KZ, /* 4494 */ + IC_EVEX_W_XD_KZ, /* 4495 */ + IC_EVEX_OPSIZE_KZ, /* 4496 */ + IC_EVEX_OPSIZE_KZ, /* 4497 */ + IC_EVEX_OPSIZE_KZ, /* 4498 */ + IC_EVEX_OPSIZE_KZ, /* 4499 */ + IC_EVEX_OPSIZE_KZ, /* 4500 */ + IC_EVEX_OPSIZE_KZ, /* 4501 */ + IC_EVEX_OPSIZE_KZ, /* 4502 */ + IC_EVEX_OPSIZE_KZ, /* 4503 */ + IC_EVEX_W_OPSIZE_KZ, /* 4504 */ + IC_EVEX_W_OPSIZE_KZ, /* 4505 */ + IC_EVEX_W_OPSIZE_KZ, /* 4506 */ + IC_EVEX_W_OPSIZE_KZ, /* 4507 */ + IC_EVEX_W_OPSIZE_KZ, /* 4508 */ + IC_EVEX_W_OPSIZE_KZ, /* 4509 */ + IC_EVEX_W_OPSIZE_KZ, /* 4510 */ + IC_EVEX_W_OPSIZE_KZ, /* 4511 */ + IC_EVEX_KZ, /* 4512 */ + IC_EVEX_KZ, /* 4513 */ + IC_EVEX_XS_KZ, /* 4514 */ + IC_EVEX_XS_KZ, /* 4515 */ + IC_EVEX_XD_KZ, /* 4516 */ + IC_EVEX_XD_KZ, /* 4517 */ + IC_EVEX_XD_KZ, /* 4518 */ + IC_EVEX_XD_KZ, /* 4519 */ + IC_EVEX_W_KZ, /* 4520 */ + IC_EVEX_W_KZ, /* 4521 */ + IC_EVEX_W_XS_KZ, /* 4522 */ + IC_EVEX_W_XS_KZ, /* 4523 */ + IC_EVEX_W_XD_KZ, /* 4524 */ + IC_EVEX_W_XD_KZ, /* 4525 */ + IC_EVEX_W_XD_KZ, /* 4526 */ + IC_EVEX_W_XD_KZ, /* 4527 */ + IC_EVEX_OPSIZE_KZ, /* 4528 */ + IC_EVEX_OPSIZE_KZ, /* 4529 */ + IC_EVEX_OPSIZE_KZ, /* 4530 */ + IC_EVEX_OPSIZE_KZ, /* 4531 */ + IC_EVEX_OPSIZE_KZ, /* 4532 */ + IC_EVEX_OPSIZE_KZ, /* 4533 */ + IC_EVEX_OPSIZE_KZ, /* 4534 */ + IC_EVEX_OPSIZE_KZ, /* 4535 */ + IC_EVEX_W_OPSIZE_KZ, /* 4536 */ + IC_EVEX_W_OPSIZE_KZ, /* 4537 */ + IC_EVEX_W_OPSIZE_KZ, /* 4538 */ + IC_EVEX_W_OPSIZE_KZ, /* 4539 */ + IC_EVEX_W_OPSIZE_KZ, /* 4540 */ + IC_EVEX_W_OPSIZE_KZ, /* 4541 */ + IC_EVEX_W_OPSIZE_KZ, /* 4542 */ + IC_EVEX_W_OPSIZE_KZ, /* 4543 */ + IC_EVEX_KZ, /* 4544 */ + IC_EVEX_KZ, /* 4545 */ + IC_EVEX_XS_KZ, /* 4546 */ + IC_EVEX_XS_KZ, /* 4547 */ + IC_EVEX_XD_KZ, /* 4548 */ + IC_EVEX_XD_KZ, /* 4549 */ + IC_EVEX_XD_KZ, /* 4550 */ + IC_EVEX_XD_KZ, /* 4551 */ + IC_EVEX_W_KZ, /* 4552 */ + IC_EVEX_W_KZ, /* 4553 */ + IC_EVEX_W_XS_KZ, /* 4554 */ + IC_EVEX_W_XS_KZ, /* 4555 */ + IC_EVEX_W_XD_KZ, /* 4556 */ + IC_EVEX_W_XD_KZ, /* 4557 */ + IC_EVEX_W_XD_KZ, /* 4558 */ + IC_EVEX_W_XD_KZ, /* 4559 */ + IC_EVEX_OPSIZE_KZ, /* 4560 */ + IC_EVEX_OPSIZE_KZ, /* 4561 */ + IC_EVEX_OPSIZE_KZ, /* 4562 */ + IC_EVEX_OPSIZE_KZ, /* 4563 */ + IC_EVEX_OPSIZE_KZ, /* 4564 */ + IC_EVEX_OPSIZE_KZ, /* 4565 */ + IC_EVEX_OPSIZE_KZ, /* 4566 */ + IC_EVEX_OPSIZE_KZ, /* 4567 */ + IC_EVEX_W_OPSIZE_KZ, /* 4568 */ + IC_EVEX_W_OPSIZE_KZ, /* 4569 */ + IC_EVEX_W_OPSIZE_KZ, /* 4570 */ + IC_EVEX_W_OPSIZE_KZ, /* 4571 */ + IC_EVEX_W_OPSIZE_KZ, /* 4572 */ + IC_EVEX_W_OPSIZE_KZ, /* 4573 */ + IC_EVEX_W_OPSIZE_KZ, /* 4574 */ + IC_EVEX_W_OPSIZE_KZ, /* 4575 */ + IC_EVEX_KZ, /* 4576 */ + IC_EVEX_KZ, /* 4577 */ + IC_EVEX_XS_KZ, /* 4578 */ + IC_EVEX_XS_KZ, /* 4579 */ + IC_EVEX_XD_KZ, /* 4580 */ + IC_EVEX_XD_KZ, /* 4581 */ + IC_EVEX_XD_KZ, /* 4582 */ + IC_EVEX_XD_KZ, /* 4583 */ + IC_EVEX_W_KZ, /* 4584 */ + IC_EVEX_W_KZ, /* 4585 */ + IC_EVEX_W_XS_KZ, /* 4586 */ + IC_EVEX_W_XS_KZ, /* 4587 */ + IC_EVEX_W_XD_KZ, /* 4588 */ + IC_EVEX_W_XD_KZ, /* 4589 */ + IC_EVEX_W_XD_KZ, /* 4590 */ + IC_EVEX_W_XD_KZ, /* 4591 */ + IC_EVEX_OPSIZE_KZ, /* 4592 */ + IC_EVEX_OPSIZE_KZ, /* 4593 */ + IC_EVEX_OPSIZE_KZ, /* 4594 */ + IC_EVEX_OPSIZE_KZ, /* 4595 */ + IC_EVEX_OPSIZE_KZ, /* 4596 */ + IC_EVEX_OPSIZE_KZ, /* 4597 */ + IC_EVEX_OPSIZE_KZ, /* 4598 */ + IC_EVEX_OPSIZE_KZ, /* 4599 */ + IC_EVEX_W_OPSIZE_KZ, /* 4600 */ + IC_EVEX_W_OPSIZE_KZ, /* 4601 */ + IC_EVEX_W_OPSIZE_KZ, /* 4602 */ + IC_EVEX_W_OPSIZE_KZ, /* 4603 */ + IC_EVEX_W_OPSIZE_KZ, /* 4604 */ + IC_EVEX_W_OPSIZE_KZ, /* 4605 */ + IC_EVEX_W_OPSIZE_KZ, /* 4606 */ + IC_EVEX_W_OPSIZE_KZ, /* 4607 */ + IC, /* 4608 */ + IC_64BIT, /* 4609 */ + IC_XS, /* 4610 */ + IC_64BIT_XS, /* 4611 */ + IC_XD, /* 4612 */ + IC_64BIT_XD, /* 4613 */ + IC_XS, /* 4614 */ + IC_64BIT_XS, /* 4615 */ + IC, /* 4616 */ + IC_64BIT_REXW, /* 4617 */ + IC_XS, /* 4618 */ + IC_64BIT_REXW_XS, /* 4619 */ + IC_XD, /* 4620 */ + IC_64BIT_REXW_XD, /* 4621 */ + IC_XS, /* 4622 */ + IC_64BIT_REXW_XS, /* 4623 */ + IC_OPSIZE, /* 4624 */ + IC_64BIT_OPSIZE, /* 4625 */ + IC_XS_OPSIZE, /* 4626 */ + IC_64BIT_XS_OPSIZE, /* 4627 */ + IC_XD_OPSIZE, /* 4628 */ + IC_64BIT_XD_OPSIZE, /* 4629 */ + IC_XS_OPSIZE, /* 4630 */ + IC_64BIT_XD_OPSIZE, /* 4631 */ + IC_OPSIZE, /* 4632 */ + IC_64BIT_REXW_OPSIZE, /* 4633 */ + IC_XS_OPSIZE, /* 4634 */ + IC_64BIT_REXW_XS, /* 4635 */ + IC_XD_OPSIZE, /* 4636 */ + IC_64BIT_REXW_XD, /* 4637 */ + IC_XS_OPSIZE, /* 4638 */ + IC_64BIT_REXW_XS, /* 4639 */ + IC_ADSIZE, /* 4640 */ + IC_64BIT_ADSIZE, /* 4641 */ + IC_XS_ADSIZE, /* 4642 */ + IC_64BIT_XS_ADSIZE, /* 4643 */ + IC_XD_ADSIZE, /* 4644 */ + IC_64BIT_XD_ADSIZE, /* 4645 */ + IC_XS_ADSIZE, /* 4646 */ + IC_64BIT_XD_ADSIZE, /* 4647 */ + IC_ADSIZE, /* 4648 */ + IC_64BIT_REXW_ADSIZE, /* 4649 */ + IC_XS_ADSIZE, /* 4650 */ + IC_64BIT_REXW_XS, /* 4651 */ + IC_XD_ADSIZE, /* 4652 */ + IC_64BIT_REXW_XD, /* 4653 */ + IC_XS_ADSIZE, /* 4654 */ + IC_64BIT_REXW_XS, /* 4655 */ + IC_OPSIZE_ADSIZE, /* 4656 */ + IC_64BIT_OPSIZE_ADSIZE, /* 4657 */ + IC_XS_OPSIZE, /* 4658 */ + IC_64BIT_XS_OPSIZE, /* 4659 */ + IC_XD_OPSIZE, /* 4660 */ + IC_64BIT_XD_OPSIZE, /* 4661 */ + IC_XS_OPSIZE, /* 4662 */ + IC_64BIT_XD_OPSIZE, /* 4663 */ + IC_OPSIZE_ADSIZE, /* 4664 */ + IC_64BIT_REXW_OPSIZE, /* 4665 */ + IC_XS_OPSIZE, /* 4666 */ + IC_64BIT_REXW_XS, /* 4667 */ + IC_XD_OPSIZE, /* 4668 */ + IC_64BIT_REXW_XD, /* 4669 */ + IC_XS_OPSIZE, /* 4670 */ + IC_64BIT_REXW_XS, /* 4671 */ + IC_VEX, /* 4672 */ + IC_VEX, /* 4673 */ + IC_VEX_XS, /* 4674 */ + IC_VEX_XS, /* 4675 */ + IC_VEX_XD, /* 4676 */ + IC_VEX_XD, /* 4677 */ + IC_VEX_XD, /* 4678 */ + IC_VEX_XD, /* 4679 */ + IC_VEX_W, /* 4680 */ + IC_VEX_W, /* 4681 */ + IC_VEX_W_XS, /* 4682 */ + IC_VEX_W_XS, /* 4683 */ + IC_VEX_W_XD, /* 4684 */ + IC_VEX_W_XD, /* 4685 */ + IC_VEX_W_XD, /* 4686 */ + IC_VEX_W_XD, /* 4687 */ + IC_VEX_OPSIZE, /* 4688 */ + IC_VEX_OPSIZE, /* 4689 */ + IC_VEX_OPSIZE, /* 4690 */ + IC_VEX_OPSIZE, /* 4691 */ + IC_VEX_OPSIZE, /* 4692 */ + IC_VEX_OPSIZE, /* 4693 */ + IC_VEX_OPSIZE, /* 4694 */ + IC_VEX_OPSIZE, /* 4695 */ + IC_VEX_W_OPSIZE, /* 4696 */ + IC_VEX_W_OPSIZE, /* 4697 */ + IC_VEX_W_OPSIZE, /* 4698 */ + IC_VEX_W_OPSIZE, /* 4699 */ + IC_VEX_W_OPSIZE, /* 4700 */ + IC_VEX_W_OPSIZE, /* 4701 */ + IC_VEX_W_OPSIZE, /* 4702 */ + IC_VEX_W_OPSIZE, /* 4703 */ + IC_VEX, /* 4704 */ + IC_VEX, /* 4705 */ + IC_VEX_XS, /* 4706 */ + IC_VEX_XS, /* 4707 */ + IC_VEX_XD, /* 4708 */ + IC_VEX_XD, /* 4709 */ + IC_VEX_XD, /* 4710 */ + IC_VEX_XD, /* 4711 */ + IC_VEX_W, /* 4712 */ + IC_VEX_W, /* 4713 */ + IC_VEX_W_XS, /* 4714 */ + IC_VEX_W_XS, /* 4715 */ + IC_VEX_W_XD, /* 4716 */ + IC_VEX_W_XD, /* 4717 */ + IC_VEX_W_XD, /* 4718 */ + IC_VEX_W_XD, /* 4719 */ + IC_VEX_OPSIZE, /* 4720 */ + IC_VEX_OPSIZE, /* 4721 */ + IC_VEX_OPSIZE, /* 4722 */ + IC_VEX_OPSIZE, /* 4723 */ + IC_VEX_OPSIZE, /* 4724 */ + IC_VEX_OPSIZE, /* 4725 */ + IC_VEX_OPSIZE, /* 4726 */ + IC_VEX_OPSIZE, /* 4727 */ + IC_VEX_W_OPSIZE, /* 4728 */ + IC_VEX_W_OPSIZE, /* 4729 */ + IC_VEX_W_OPSIZE, /* 4730 */ + IC_VEX_W_OPSIZE, /* 4731 */ + IC_VEX_W_OPSIZE, /* 4732 */ + IC_VEX_W_OPSIZE, /* 4733 */ + IC_VEX_W_OPSIZE, /* 4734 */ + IC_VEX_W_OPSIZE, /* 4735 */ + IC_VEX_L, /* 4736 */ + IC_VEX_L, /* 4737 */ + IC_VEX_L_XS, /* 4738 */ + IC_VEX_L_XS, /* 4739 */ + IC_VEX_L_XD, /* 4740 */ + IC_VEX_L_XD, /* 4741 */ + IC_VEX_L_XD, /* 4742 */ + IC_VEX_L_XD, /* 4743 */ + IC_VEX_L_W, /* 4744 */ + IC_VEX_L_W, /* 4745 */ + IC_VEX_L_W_XS, /* 4746 */ + IC_VEX_L_W_XS, /* 4747 */ + IC_VEX_L_W_XD, /* 4748 */ + IC_VEX_L_W_XD, /* 4749 */ + IC_VEX_L_W_XD, /* 4750 */ + IC_VEX_L_W_XD, /* 4751 */ + IC_VEX_L_OPSIZE, /* 4752 */ + IC_VEX_L_OPSIZE, /* 4753 */ + IC_VEX_L_OPSIZE, /* 4754 */ + IC_VEX_L_OPSIZE, /* 4755 */ + IC_VEX_L_OPSIZE, /* 4756 */ + IC_VEX_L_OPSIZE, /* 4757 */ + IC_VEX_L_OPSIZE, /* 4758 */ + IC_VEX_L_OPSIZE, /* 4759 */ + IC_VEX_L_W_OPSIZE, /* 4760 */ + IC_VEX_L_W_OPSIZE, /* 4761 */ + IC_VEX_L_W_OPSIZE, /* 4762 */ + IC_VEX_L_W_OPSIZE, /* 4763 */ + IC_VEX_L_W_OPSIZE, /* 4764 */ + IC_VEX_L_W_OPSIZE, /* 4765 */ + IC_VEX_L_W_OPSIZE, /* 4766 */ + IC_VEX_L_W_OPSIZE, /* 4767 */ + IC_VEX_L, /* 4768 */ + IC_VEX_L, /* 4769 */ + IC_VEX_L_XS, /* 4770 */ + IC_VEX_L_XS, /* 4771 */ + IC_VEX_L_XD, /* 4772 */ + IC_VEX_L_XD, /* 4773 */ + IC_VEX_L_XD, /* 4774 */ + IC_VEX_L_XD, /* 4775 */ + IC_VEX_L_W, /* 4776 */ + IC_VEX_L_W, /* 4777 */ + IC_VEX_L_W_XS, /* 4778 */ + IC_VEX_L_W_XS, /* 4779 */ + IC_VEX_L_W_XD, /* 4780 */ + IC_VEX_L_W_XD, /* 4781 */ + IC_VEX_L_W_XD, /* 4782 */ + IC_VEX_L_W_XD, /* 4783 */ + IC_VEX_L_OPSIZE, /* 4784 */ + IC_VEX_L_OPSIZE, /* 4785 */ + IC_VEX_L_OPSIZE, /* 4786 */ + IC_VEX_L_OPSIZE, /* 4787 */ + IC_VEX_L_OPSIZE, /* 4788 */ + IC_VEX_L_OPSIZE, /* 4789 */ + IC_VEX_L_OPSIZE, /* 4790 */ + IC_VEX_L_OPSIZE, /* 4791 */ + IC_VEX_L_W_OPSIZE, /* 4792 */ + IC_VEX_L_W_OPSIZE, /* 4793 */ + IC_VEX_L_W_OPSIZE, /* 4794 */ + IC_VEX_L_W_OPSIZE, /* 4795 */ + IC_VEX_L_W_OPSIZE, /* 4796 */ + IC_VEX_L_W_OPSIZE, /* 4797 */ + IC_VEX_L_W_OPSIZE, /* 4798 */ + IC_VEX_L_W_OPSIZE, /* 4799 */ + IC_VEX_L, /* 4800 */ + IC_VEX_L, /* 4801 */ + IC_VEX_L_XS, /* 4802 */ + IC_VEX_L_XS, /* 4803 */ + IC_VEX_L_XD, /* 4804 */ + IC_VEX_L_XD, /* 4805 */ + IC_VEX_L_XD, /* 4806 */ + IC_VEX_L_XD, /* 4807 */ + IC_VEX_L_W, /* 4808 */ + IC_VEX_L_W, /* 4809 */ + IC_VEX_L_W_XS, /* 4810 */ + IC_VEX_L_W_XS, /* 4811 */ + IC_VEX_L_W_XD, /* 4812 */ + IC_VEX_L_W_XD, /* 4813 */ + IC_VEX_L_W_XD, /* 4814 */ + IC_VEX_L_W_XD, /* 4815 */ + IC_VEX_L_OPSIZE, /* 4816 */ + IC_VEX_L_OPSIZE, /* 4817 */ + IC_VEX_L_OPSIZE, /* 4818 */ + IC_VEX_L_OPSIZE, /* 4819 */ + IC_VEX_L_OPSIZE, /* 4820 */ + IC_VEX_L_OPSIZE, /* 4821 */ + IC_VEX_L_OPSIZE, /* 4822 */ + IC_VEX_L_OPSIZE, /* 4823 */ + IC_VEX_L_W_OPSIZE, /* 4824 */ + IC_VEX_L_W_OPSIZE, /* 4825 */ + IC_VEX_L_W_OPSIZE, /* 4826 */ + IC_VEX_L_W_OPSIZE, /* 4827 */ + IC_VEX_L_W_OPSIZE, /* 4828 */ + IC_VEX_L_W_OPSIZE, /* 4829 */ + IC_VEX_L_W_OPSIZE, /* 4830 */ + IC_VEX_L_W_OPSIZE, /* 4831 */ + IC_VEX_L, /* 4832 */ + IC_VEX_L, /* 4833 */ + IC_VEX_L_XS, /* 4834 */ + IC_VEX_L_XS, /* 4835 */ + IC_VEX_L_XD, /* 4836 */ + IC_VEX_L_XD, /* 4837 */ + IC_VEX_L_XD, /* 4838 */ + IC_VEX_L_XD, /* 4839 */ + IC_VEX_L_W, /* 4840 */ + IC_VEX_L_W, /* 4841 */ + IC_VEX_L_W_XS, /* 4842 */ + IC_VEX_L_W_XS, /* 4843 */ + IC_VEX_L_W_XD, /* 4844 */ + IC_VEX_L_W_XD, /* 4845 */ + IC_VEX_L_W_XD, /* 4846 */ + IC_VEX_L_W_XD, /* 4847 */ + IC_VEX_L_OPSIZE, /* 4848 */ + IC_VEX_L_OPSIZE, /* 4849 */ + IC_VEX_L_OPSIZE, /* 4850 */ + IC_VEX_L_OPSIZE, /* 4851 */ + IC_VEX_L_OPSIZE, /* 4852 */ + IC_VEX_L_OPSIZE, /* 4853 */ + IC_VEX_L_OPSIZE, /* 4854 */ + IC_VEX_L_OPSIZE, /* 4855 */ + IC_VEX_L_W_OPSIZE, /* 4856 */ + IC_VEX_L_W_OPSIZE, /* 4857 */ + IC_VEX_L_W_OPSIZE, /* 4858 */ + IC_VEX_L_W_OPSIZE, /* 4859 */ + IC_VEX_L_W_OPSIZE, /* 4860 */ + IC_VEX_L_W_OPSIZE, /* 4861 */ + IC_VEX_L_W_OPSIZE, /* 4862 */ + IC_VEX_L_W_OPSIZE, /* 4863 */ + IC_EVEX_L_KZ, /* 4864 */ + IC_EVEX_L_KZ, /* 4865 */ + IC_EVEX_L_XS_KZ, /* 4866 */ + IC_EVEX_L_XS_KZ, /* 4867 */ + IC_EVEX_L_XD_KZ, /* 4868 */ + IC_EVEX_L_XD_KZ, /* 4869 */ + IC_EVEX_L_XD_KZ, /* 4870 */ + IC_EVEX_L_XD_KZ, /* 4871 */ + IC_EVEX_L_W_KZ, /* 4872 */ + IC_EVEX_L_W_KZ, /* 4873 */ + IC_EVEX_L_W_XS_KZ, /* 4874 */ + IC_EVEX_L_W_XS_KZ, /* 4875 */ + IC_EVEX_L_W_XD_KZ, /* 4876 */ + IC_EVEX_L_W_XD_KZ, /* 4877 */ + IC_EVEX_L_W_XD_KZ, /* 4878 */ + IC_EVEX_L_W_XD_KZ, /* 4879 */ + IC_EVEX_L_OPSIZE_KZ, /* 4880 */ + IC_EVEX_L_OPSIZE_KZ, /* 4881 */ + IC_EVEX_L_OPSIZE_KZ, /* 4882 */ + IC_EVEX_L_OPSIZE_KZ, /* 4883 */ + IC_EVEX_L_OPSIZE_KZ, /* 4884 */ + IC_EVEX_L_OPSIZE_KZ, /* 4885 */ + IC_EVEX_L_OPSIZE_KZ, /* 4886 */ + IC_EVEX_L_OPSIZE_KZ, /* 4887 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4888 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4889 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4890 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4891 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4892 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4893 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4894 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4895 */ + IC_EVEX_L_KZ, /* 4896 */ + IC_EVEX_L_KZ, /* 4897 */ + IC_EVEX_L_XS_KZ, /* 4898 */ + IC_EVEX_L_XS_KZ, /* 4899 */ + IC_EVEX_L_XD_KZ, /* 4900 */ + IC_EVEX_L_XD_KZ, /* 4901 */ + IC_EVEX_L_XD_KZ, /* 4902 */ + IC_EVEX_L_XD_KZ, /* 4903 */ + IC_EVEX_L_W_KZ, /* 4904 */ + IC_EVEX_L_W_KZ, /* 4905 */ + IC_EVEX_L_W_XS_KZ, /* 4906 */ + IC_EVEX_L_W_XS_KZ, /* 4907 */ + IC_EVEX_L_W_XD_KZ, /* 4908 */ + IC_EVEX_L_W_XD_KZ, /* 4909 */ + IC_EVEX_L_W_XD_KZ, /* 4910 */ + IC_EVEX_L_W_XD_KZ, /* 4911 */ + IC_EVEX_L_OPSIZE_KZ, /* 4912 */ + IC_EVEX_L_OPSIZE_KZ, /* 4913 */ + IC_EVEX_L_OPSIZE_KZ, /* 4914 */ + IC_EVEX_L_OPSIZE_KZ, /* 4915 */ + IC_EVEX_L_OPSIZE_KZ, /* 4916 */ + IC_EVEX_L_OPSIZE_KZ, /* 4917 */ + IC_EVEX_L_OPSIZE_KZ, /* 4918 */ + IC_EVEX_L_OPSIZE_KZ, /* 4919 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4920 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4921 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4922 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4923 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4924 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4925 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4926 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4927 */ + IC_EVEX_L_KZ, /* 4928 */ + IC_EVEX_L_KZ, /* 4929 */ + IC_EVEX_L_XS_KZ, /* 4930 */ + IC_EVEX_L_XS_KZ, /* 4931 */ + IC_EVEX_L_XD_KZ, /* 4932 */ + IC_EVEX_L_XD_KZ, /* 4933 */ + IC_EVEX_L_XD_KZ, /* 4934 */ + IC_EVEX_L_XD_KZ, /* 4935 */ + IC_EVEX_L_W_KZ, /* 4936 */ + IC_EVEX_L_W_KZ, /* 4937 */ + IC_EVEX_L_W_XS_KZ, /* 4938 */ + IC_EVEX_L_W_XS_KZ, /* 4939 */ + IC_EVEX_L_W_XD_KZ, /* 4940 */ + IC_EVEX_L_W_XD_KZ, /* 4941 */ + IC_EVEX_L_W_XD_KZ, /* 4942 */ + IC_EVEX_L_W_XD_KZ, /* 4943 */ + IC_EVEX_L_OPSIZE_KZ, /* 4944 */ + IC_EVEX_L_OPSIZE_KZ, /* 4945 */ + IC_EVEX_L_OPSIZE_KZ, /* 4946 */ + IC_EVEX_L_OPSIZE_KZ, /* 4947 */ + IC_EVEX_L_OPSIZE_KZ, /* 4948 */ + IC_EVEX_L_OPSIZE_KZ, /* 4949 */ + IC_EVEX_L_OPSIZE_KZ, /* 4950 */ + IC_EVEX_L_OPSIZE_KZ, /* 4951 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4952 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4953 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4954 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4955 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4956 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4957 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4958 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4959 */ + IC_EVEX_L_KZ, /* 4960 */ + IC_EVEX_L_KZ, /* 4961 */ + IC_EVEX_L_XS_KZ, /* 4962 */ + IC_EVEX_L_XS_KZ, /* 4963 */ + IC_EVEX_L_XD_KZ, /* 4964 */ + IC_EVEX_L_XD_KZ, /* 4965 */ + IC_EVEX_L_XD_KZ, /* 4966 */ + IC_EVEX_L_XD_KZ, /* 4967 */ + IC_EVEX_L_W_KZ, /* 4968 */ + IC_EVEX_L_W_KZ, /* 4969 */ + IC_EVEX_L_W_XS_KZ, /* 4970 */ + IC_EVEX_L_W_XS_KZ, /* 4971 */ + IC_EVEX_L_W_XD_KZ, /* 4972 */ + IC_EVEX_L_W_XD_KZ, /* 4973 */ + IC_EVEX_L_W_XD_KZ, /* 4974 */ + IC_EVEX_L_W_XD_KZ, /* 4975 */ + IC_EVEX_L_OPSIZE_KZ, /* 4976 */ + IC_EVEX_L_OPSIZE_KZ, /* 4977 */ + IC_EVEX_L_OPSIZE_KZ, /* 4978 */ + IC_EVEX_L_OPSIZE_KZ, /* 4979 */ + IC_EVEX_L_OPSIZE_KZ, /* 4980 */ + IC_EVEX_L_OPSIZE_KZ, /* 4981 */ + IC_EVEX_L_OPSIZE_KZ, /* 4982 */ + IC_EVEX_L_OPSIZE_KZ, /* 4983 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4984 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4985 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4986 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4987 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4988 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4989 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4990 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4991 */ + IC_EVEX_L_KZ, /* 4992 */ + IC_EVEX_L_KZ, /* 4993 */ + IC_EVEX_L_XS_KZ, /* 4994 */ + IC_EVEX_L_XS_KZ, /* 4995 */ + IC_EVEX_L_XD_KZ, /* 4996 */ + IC_EVEX_L_XD_KZ, /* 4997 */ + IC_EVEX_L_XD_KZ, /* 4998 */ + IC_EVEX_L_XD_KZ, /* 4999 */ + IC_EVEX_L_W_KZ, /* 5000 */ + IC_EVEX_L_W_KZ, /* 5001 */ + IC_EVEX_L_W_XS_KZ, /* 5002 */ + IC_EVEX_L_W_XS_KZ, /* 5003 */ + IC_EVEX_L_W_XD_KZ, /* 5004 */ + IC_EVEX_L_W_XD_KZ, /* 5005 */ + IC_EVEX_L_W_XD_KZ, /* 5006 */ + IC_EVEX_L_W_XD_KZ, /* 5007 */ + IC_EVEX_L_OPSIZE_KZ, /* 5008 */ + IC_EVEX_L_OPSIZE_KZ, /* 5009 */ + IC_EVEX_L_OPSIZE_KZ, /* 5010 */ + IC_EVEX_L_OPSIZE_KZ, /* 5011 */ + IC_EVEX_L_OPSIZE_KZ, /* 5012 */ + IC_EVEX_L_OPSIZE_KZ, /* 5013 */ + IC_EVEX_L_OPSIZE_KZ, /* 5014 */ + IC_EVEX_L_OPSIZE_KZ, /* 5015 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5016 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5017 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5018 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5019 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5020 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5021 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5022 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5023 */ + IC_EVEX_L_KZ, /* 5024 */ + IC_EVEX_L_KZ, /* 5025 */ + IC_EVEX_L_XS_KZ, /* 5026 */ + IC_EVEX_L_XS_KZ, /* 5027 */ + IC_EVEX_L_XD_KZ, /* 5028 */ + IC_EVEX_L_XD_KZ, /* 5029 */ + IC_EVEX_L_XD_KZ, /* 5030 */ + IC_EVEX_L_XD_KZ, /* 5031 */ + IC_EVEX_L_W_KZ, /* 5032 */ + IC_EVEX_L_W_KZ, /* 5033 */ + IC_EVEX_L_W_XS_KZ, /* 5034 */ + IC_EVEX_L_W_XS_KZ, /* 5035 */ + IC_EVEX_L_W_XD_KZ, /* 5036 */ + IC_EVEX_L_W_XD_KZ, /* 5037 */ + IC_EVEX_L_W_XD_KZ, /* 5038 */ + IC_EVEX_L_W_XD_KZ, /* 5039 */ + IC_EVEX_L_OPSIZE_KZ, /* 5040 */ + IC_EVEX_L_OPSIZE_KZ, /* 5041 */ + IC_EVEX_L_OPSIZE_KZ, /* 5042 */ + IC_EVEX_L_OPSIZE_KZ, /* 5043 */ + IC_EVEX_L_OPSIZE_KZ, /* 5044 */ + IC_EVEX_L_OPSIZE_KZ, /* 5045 */ + IC_EVEX_L_OPSIZE_KZ, /* 5046 */ + IC_EVEX_L_OPSIZE_KZ, /* 5047 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5048 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5049 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5050 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5051 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5052 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5053 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5054 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5055 */ + IC_EVEX_L_KZ, /* 5056 */ + IC_EVEX_L_KZ, /* 5057 */ + IC_EVEX_L_XS_KZ, /* 5058 */ + IC_EVEX_L_XS_KZ, /* 5059 */ + IC_EVEX_L_XD_KZ, /* 5060 */ + IC_EVEX_L_XD_KZ, /* 5061 */ + IC_EVEX_L_XD_KZ, /* 5062 */ + IC_EVEX_L_XD_KZ, /* 5063 */ + IC_EVEX_L_W_KZ, /* 5064 */ + IC_EVEX_L_W_KZ, /* 5065 */ + IC_EVEX_L_W_XS_KZ, /* 5066 */ + IC_EVEX_L_W_XS_KZ, /* 5067 */ + IC_EVEX_L_W_XD_KZ, /* 5068 */ + IC_EVEX_L_W_XD_KZ, /* 5069 */ + IC_EVEX_L_W_XD_KZ, /* 5070 */ + IC_EVEX_L_W_XD_KZ, /* 5071 */ + IC_EVEX_L_OPSIZE_KZ, /* 5072 */ + IC_EVEX_L_OPSIZE_KZ, /* 5073 */ + IC_EVEX_L_OPSIZE_KZ, /* 5074 */ + IC_EVEX_L_OPSIZE_KZ, /* 5075 */ + IC_EVEX_L_OPSIZE_KZ, /* 5076 */ + IC_EVEX_L_OPSIZE_KZ, /* 5077 */ + IC_EVEX_L_OPSIZE_KZ, /* 5078 */ + IC_EVEX_L_OPSIZE_KZ, /* 5079 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5080 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5081 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5082 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5083 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5084 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5085 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5086 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5087 */ + IC_EVEX_L_KZ, /* 5088 */ + IC_EVEX_L_KZ, /* 5089 */ + IC_EVEX_L_XS_KZ, /* 5090 */ + IC_EVEX_L_XS_KZ, /* 5091 */ + IC_EVEX_L_XD_KZ, /* 5092 */ + IC_EVEX_L_XD_KZ, /* 5093 */ + IC_EVEX_L_XD_KZ, /* 5094 */ + IC_EVEX_L_XD_KZ, /* 5095 */ + IC_EVEX_L_W_KZ, /* 5096 */ + IC_EVEX_L_W_KZ, /* 5097 */ + IC_EVEX_L_W_XS_KZ, /* 5098 */ + IC_EVEX_L_W_XS_KZ, /* 5099 */ + IC_EVEX_L_W_XD_KZ, /* 5100 */ + IC_EVEX_L_W_XD_KZ, /* 5101 */ + IC_EVEX_L_W_XD_KZ, /* 5102 */ + IC_EVEX_L_W_XD_KZ, /* 5103 */ + IC_EVEX_L_OPSIZE_KZ, /* 5104 */ + IC_EVEX_L_OPSIZE_KZ, /* 5105 */ + IC_EVEX_L_OPSIZE_KZ, /* 5106 */ + IC_EVEX_L_OPSIZE_KZ, /* 5107 */ + IC_EVEX_L_OPSIZE_KZ, /* 5108 */ + IC_EVEX_L_OPSIZE_KZ, /* 5109 */ + IC_EVEX_L_OPSIZE_KZ, /* 5110 */ + IC_EVEX_L_OPSIZE_KZ, /* 5111 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5112 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5113 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5114 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5115 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5116 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5117 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5118 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5119 */ + IC, /* 5120 */ + IC_64BIT, /* 5121 */ + IC_XS, /* 5122 */ + IC_64BIT_XS, /* 5123 */ + IC_XD, /* 5124 */ + IC_64BIT_XD, /* 5125 */ + IC_XS, /* 5126 */ + IC_64BIT_XS, /* 5127 */ + IC, /* 5128 */ + IC_64BIT_REXW, /* 5129 */ + IC_XS, /* 5130 */ + IC_64BIT_REXW_XS, /* 5131 */ + IC_XD, /* 5132 */ + IC_64BIT_REXW_XD, /* 5133 */ + IC_XS, /* 5134 */ + IC_64BIT_REXW_XS, /* 5135 */ + IC_OPSIZE, /* 5136 */ + IC_64BIT_OPSIZE, /* 5137 */ + IC_XS_OPSIZE, /* 5138 */ + IC_64BIT_XS_OPSIZE, /* 5139 */ + IC_XD_OPSIZE, /* 5140 */ + IC_64BIT_XD_OPSIZE, /* 5141 */ + IC_XS_OPSIZE, /* 5142 */ + IC_64BIT_XD_OPSIZE, /* 5143 */ + IC_OPSIZE, /* 5144 */ + IC_64BIT_REXW_OPSIZE, /* 5145 */ + IC_XS_OPSIZE, /* 5146 */ + IC_64BIT_REXW_XS, /* 5147 */ + IC_XD_OPSIZE, /* 5148 */ + IC_64BIT_REXW_XD, /* 5149 */ + IC_XS_OPSIZE, /* 5150 */ + IC_64BIT_REXW_XS, /* 5151 */ + IC_ADSIZE, /* 5152 */ + IC_64BIT_ADSIZE, /* 5153 */ + IC_XS_ADSIZE, /* 5154 */ + IC_64BIT_XS_ADSIZE, /* 5155 */ + IC_XD_ADSIZE, /* 5156 */ + IC_64BIT_XD_ADSIZE, /* 5157 */ + IC_XS_ADSIZE, /* 5158 */ + IC_64BIT_XD_ADSIZE, /* 5159 */ + IC_ADSIZE, /* 5160 */ + IC_64BIT_REXW_ADSIZE, /* 5161 */ + IC_XS_ADSIZE, /* 5162 */ + IC_64BIT_REXW_XS, /* 5163 */ + IC_XD_ADSIZE, /* 5164 */ + IC_64BIT_REXW_XD, /* 5165 */ + IC_XS_ADSIZE, /* 5166 */ + IC_64BIT_REXW_XS, /* 5167 */ + IC_OPSIZE_ADSIZE, /* 5168 */ + IC_64BIT_OPSIZE_ADSIZE, /* 5169 */ + IC_XS_OPSIZE, /* 5170 */ + IC_64BIT_XS_OPSIZE, /* 5171 */ + IC_XD_OPSIZE, /* 5172 */ + IC_64BIT_XD_OPSIZE, /* 5173 */ + IC_XS_OPSIZE, /* 5174 */ + IC_64BIT_XD_OPSIZE, /* 5175 */ + IC_OPSIZE_ADSIZE, /* 5176 */ + IC_64BIT_REXW_OPSIZE, /* 5177 */ + IC_XS_OPSIZE, /* 5178 */ + IC_64BIT_REXW_XS, /* 5179 */ + IC_XD_OPSIZE, /* 5180 */ + IC_64BIT_REXW_XD, /* 5181 */ + IC_XS_OPSIZE, /* 5182 */ + IC_64BIT_REXW_XS, /* 5183 */ + IC_VEX, /* 5184 */ + IC_VEX, /* 5185 */ + IC_VEX_XS, /* 5186 */ + IC_VEX_XS, /* 5187 */ + IC_VEX_XD, /* 5188 */ + IC_VEX_XD, /* 5189 */ + IC_VEX_XD, /* 5190 */ + IC_VEX_XD, /* 5191 */ + IC_VEX_W, /* 5192 */ + IC_VEX_W, /* 5193 */ + IC_VEX_W_XS, /* 5194 */ + IC_VEX_W_XS, /* 5195 */ + IC_VEX_W_XD, /* 5196 */ + IC_VEX_W_XD, /* 5197 */ + IC_VEX_W_XD, /* 5198 */ + IC_VEX_W_XD, /* 5199 */ + IC_VEX_OPSIZE, /* 5200 */ + IC_VEX_OPSIZE, /* 5201 */ + IC_VEX_OPSIZE, /* 5202 */ + IC_VEX_OPSIZE, /* 5203 */ + IC_VEX_OPSIZE, /* 5204 */ + IC_VEX_OPSIZE, /* 5205 */ + IC_VEX_OPSIZE, /* 5206 */ + IC_VEX_OPSIZE, /* 5207 */ + IC_VEX_W_OPSIZE, /* 5208 */ + IC_VEX_W_OPSIZE, /* 5209 */ + IC_VEX_W_OPSIZE, /* 5210 */ + IC_VEX_W_OPSIZE, /* 5211 */ + IC_VEX_W_OPSIZE, /* 5212 */ + IC_VEX_W_OPSIZE, /* 5213 */ + IC_VEX_W_OPSIZE, /* 5214 */ + IC_VEX_W_OPSIZE, /* 5215 */ + IC_VEX, /* 5216 */ + IC_VEX, /* 5217 */ + IC_VEX_XS, /* 5218 */ + IC_VEX_XS, /* 5219 */ + IC_VEX_XD, /* 5220 */ + IC_VEX_XD, /* 5221 */ + IC_VEX_XD, /* 5222 */ + IC_VEX_XD, /* 5223 */ + IC_VEX_W, /* 5224 */ + IC_VEX_W, /* 5225 */ + IC_VEX_W_XS, /* 5226 */ + IC_VEX_W_XS, /* 5227 */ + IC_VEX_W_XD, /* 5228 */ + IC_VEX_W_XD, /* 5229 */ + IC_VEX_W_XD, /* 5230 */ + IC_VEX_W_XD, /* 5231 */ + IC_VEX_OPSIZE, /* 5232 */ + IC_VEX_OPSIZE, /* 5233 */ + IC_VEX_OPSIZE, /* 5234 */ + IC_VEX_OPSIZE, /* 5235 */ + IC_VEX_OPSIZE, /* 5236 */ + IC_VEX_OPSIZE, /* 5237 */ + IC_VEX_OPSIZE, /* 5238 */ + IC_VEX_OPSIZE, /* 5239 */ + IC_VEX_W_OPSIZE, /* 5240 */ + IC_VEX_W_OPSIZE, /* 5241 */ + IC_VEX_W_OPSIZE, /* 5242 */ + IC_VEX_W_OPSIZE, /* 5243 */ + IC_VEX_W_OPSIZE, /* 5244 */ + IC_VEX_W_OPSIZE, /* 5245 */ + IC_VEX_W_OPSIZE, /* 5246 */ + IC_VEX_W_OPSIZE, /* 5247 */ + IC_VEX_L, /* 5248 */ + IC_VEX_L, /* 5249 */ + IC_VEX_L_XS, /* 5250 */ + IC_VEX_L_XS, /* 5251 */ + IC_VEX_L_XD, /* 5252 */ + IC_VEX_L_XD, /* 5253 */ + IC_VEX_L_XD, /* 5254 */ + IC_VEX_L_XD, /* 5255 */ + IC_VEX_L_W, /* 5256 */ + IC_VEX_L_W, /* 5257 */ + IC_VEX_L_W_XS, /* 5258 */ + IC_VEX_L_W_XS, /* 5259 */ + IC_VEX_L_W_XD, /* 5260 */ + IC_VEX_L_W_XD, /* 5261 */ + IC_VEX_L_W_XD, /* 5262 */ + IC_VEX_L_W_XD, /* 5263 */ + IC_VEX_L_OPSIZE, /* 5264 */ + IC_VEX_L_OPSIZE, /* 5265 */ + IC_VEX_L_OPSIZE, /* 5266 */ + IC_VEX_L_OPSIZE, /* 5267 */ + IC_VEX_L_OPSIZE, /* 5268 */ + IC_VEX_L_OPSIZE, /* 5269 */ + IC_VEX_L_OPSIZE, /* 5270 */ + IC_VEX_L_OPSIZE, /* 5271 */ + IC_VEX_L_W_OPSIZE, /* 5272 */ + IC_VEX_L_W_OPSIZE, /* 5273 */ + IC_VEX_L_W_OPSIZE, /* 5274 */ + IC_VEX_L_W_OPSIZE, /* 5275 */ + IC_VEX_L_W_OPSIZE, /* 5276 */ + IC_VEX_L_W_OPSIZE, /* 5277 */ + IC_VEX_L_W_OPSIZE, /* 5278 */ + IC_VEX_L_W_OPSIZE, /* 5279 */ + IC_VEX_L, /* 5280 */ + IC_VEX_L, /* 5281 */ + IC_VEX_L_XS, /* 5282 */ + IC_VEX_L_XS, /* 5283 */ + IC_VEX_L_XD, /* 5284 */ + IC_VEX_L_XD, /* 5285 */ + IC_VEX_L_XD, /* 5286 */ + IC_VEX_L_XD, /* 5287 */ + IC_VEX_L_W, /* 5288 */ + IC_VEX_L_W, /* 5289 */ + IC_VEX_L_W_XS, /* 5290 */ + IC_VEX_L_W_XS, /* 5291 */ + IC_VEX_L_W_XD, /* 5292 */ + IC_VEX_L_W_XD, /* 5293 */ + IC_VEX_L_W_XD, /* 5294 */ + IC_VEX_L_W_XD, /* 5295 */ + IC_VEX_L_OPSIZE, /* 5296 */ + IC_VEX_L_OPSIZE, /* 5297 */ + IC_VEX_L_OPSIZE, /* 5298 */ + IC_VEX_L_OPSIZE, /* 5299 */ + IC_VEX_L_OPSIZE, /* 5300 */ + IC_VEX_L_OPSIZE, /* 5301 */ + IC_VEX_L_OPSIZE, /* 5302 */ + IC_VEX_L_OPSIZE, /* 5303 */ + IC_VEX_L_W_OPSIZE, /* 5304 */ + IC_VEX_L_W_OPSIZE, /* 5305 */ + IC_VEX_L_W_OPSIZE, /* 5306 */ + IC_VEX_L_W_OPSIZE, /* 5307 */ + IC_VEX_L_W_OPSIZE, /* 5308 */ + IC_VEX_L_W_OPSIZE, /* 5309 */ + IC_VEX_L_W_OPSIZE, /* 5310 */ + IC_VEX_L_W_OPSIZE, /* 5311 */ + IC_VEX_L, /* 5312 */ + IC_VEX_L, /* 5313 */ + IC_VEX_L_XS, /* 5314 */ + IC_VEX_L_XS, /* 5315 */ + IC_VEX_L_XD, /* 5316 */ + IC_VEX_L_XD, /* 5317 */ + IC_VEX_L_XD, /* 5318 */ + IC_VEX_L_XD, /* 5319 */ + IC_VEX_L_W, /* 5320 */ + IC_VEX_L_W, /* 5321 */ + IC_VEX_L_W_XS, /* 5322 */ + IC_VEX_L_W_XS, /* 5323 */ + IC_VEX_L_W_XD, /* 5324 */ + IC_VEX_L_W_XD, /* 5325 */ + IC_VEX_L_W_XD, /* 5326 */ + IC_VEX_L_W_XD, /* 5327 */ + IC_VEX_L_OPSIZE, /* 5328 */ + IC_VEX_L_OPSIZE, /* 5329 */ + IC_VEX_L_OPSIZE, /* 5330 */ + IC_VEX_L_OPSIZE, /* 5331 */ + IC_VEX_L_OPSIZE, /* 5332 */ + IC_VEX_L_OPSIZE, /* 5333 */ + IC_VEX_L_OPSIZE, /* 5334 */ + IC_VEX_L_OPSIZE, /* 5335 */ + IC_VEX_L_W_OPSIZE, /* 5336 */ + IC_VEX_L_W_OPSIZE, /* 5337 */ + IC_VEX_L_W_OPSIZE, /* 5338 */ + IC_VEX_L_W_OPSIZE, /* 5339 */ + IC_VEX_L_W_OPSIZE, /* 5340 */ + IC_VEX_L_W_OPSIZE, /* 5341 */ + IC_VEX_L_W_OPSIZE, /* 5342 */ + IC_VEX_L_W_OPSIZE, /* 5343 */ + IC_VEX_L, /* 5344 */ + IC_VEX_L, /* 5345 */ + IC_VEX_L_XS, /* 5346 */ + IC_VEX_L_XS, /* 5347 */ + IC_VEX_L_XD, /* 5348 */ + IC_VEX_L_XD, /* 5349 */ + IC_VEX_L_XD, /* 5350 */ + IC_VEX_L_XD, /* 5351 */ + IC_VEX_L_W, /* 5352 */ + IC_VEX_L_W, /* 5353 */ + IC_VEX_L_W_XS, /* 5354 */ + IC_VEX_L_W_XS, /* 5355 */ + IC_VEX_L_W_XD, /* 5356 */ + IC_VEX_L_W_XD, /* 5357 */ + IC_VEX_L_W_XD, /* 5358 */ + IC_VEX_L_W_XD, /* 5359 */ + IC_VEX_L_OPSIZE, /* 5360 */ + IC_VEX_L_OPSIZE, /* 5361 */ + IC_VEX_L_OPSIZE, /* 5362 */ + IC_VEX_L_OPSIZE, /* 5363 */ + IC_VEX_L_OPSIZE, /* 5364 */ + IC_VEX_L_OPSIZE, /* 5365 */ + IC_VEX_L_OPSIZE, /* 5366 */ + IC_VEX_L_OPSIZE, /* 5367 */ + IC_VEX_L_W_OPSIZE, /* 5368 */ + IC_VEX_L_W_OPSIZE, /* 5369 */ + IC_VEX_L_W_OPSIZE, /* 5370 */ + IC_VEX_L_W_OPSIZE, /* 5371 */ + IC_VEX_L_W_OPSIZE, /* 5372 */ + IC_VEX_L_W_OPSIZE, /* 5373 */ + IC_VEX_L_W_OPSIZE, /* 5374 */ + IC_VEX_L_W_OPSIZE, /* 5375 */ + IC_EVEX_L2_KZ, /* 5376 */ + IC_EVEX_L2_KZ, /* 5377 */ + IC_EVEX_L2_XS_KZ, /* 5378 */ + IC_EVEX_L2_XS_KZ, /* 5379 */ + IC_EVEX_L2_XD_KZ, /* 5380 */ + IC_EVEX_L2_XD_KZ, /* 5381 */ + IC_EVEX_L2_XD_KZ, /* 5382 */ + IC_EVEX_L2_XD_KZ, /* 5383 */ + IC_EVEX_L2_W_KZ, /* 5384 */ + IC_EVEX_L2_W_KZ, /* 5385 */ + IC_EVEX_L2_W_XS_KZ, /* 5386 */ + IC_EVEX_L2_W_XS_KZ, /* 5387 */ + IC_EVEX_L2_W_XD_KZ, /* 5388 */ + IC_EVEX_L2_W_XD_KZ, /* 5389 */ + IC_EVEX_L2_W_XD_KZ, /* 5390 */ + IC_EVEX_L2_W_XD_KZ, /* 5391 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5392 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5393 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5394 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5395 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5396 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5397 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5398 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5399 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5400 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5401 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5402 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5403 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5404 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5405 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5406 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5407 */ + IC_EVEX_L2_KZ, /* 5408 */ + IC_EVEX_L2_KZ, /* 5409 */ + IC_EVEX_L2_XS_KZ, /* 5410 */ + IC_EVEX_L2_XS_KZ, /* 5411 */ + IC_EVEX_L2_XD_KZ, /* 5412 */ + IC_EVEX_L2_XD_KZ, /* 5413 */ + IC_EVEX_L2_XD_KZ, /* 5414 */ + IC_EVEX_L2_XD_KZ, /* 5415 */ + IC_EVEX_L2_W_KZ, /* 5416 */ + IC_EVEX_L2_W_KZ, /* 5417 */ + IC_EVEX_L2_W_XS_KZ, /* 5418 */ + IC_EVEX_L2_W_XS_KZ, /* 5419 */ + IC_EVEX_L2_W_XD_KZ, /* 5420 */ + IC_EVEX_L2_W_XD_KZ, /* 5421 */ + IC_EVEX_L2_W_XD_KZ, /* 5422 */ + IC_EVEX_L2_W_XD_KZ, /* 5423 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5424 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5425 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5426 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5427 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5428 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5429 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5430 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5431 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5432 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5433 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5434 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5435 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5436 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5437 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5438 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5439 */ + IC_EVEX_L2_KZ, /* 5440 */ + IC_EVEX_L2_KZ, /* 5441 */ + IC_EVEX_L2_XS_KZ, /* 5442 */ + IC_EVEX_L2_XS_KZ, /* 5443 */ + IC_EVEX_L2_XD_KZ, /* 5444 */ + IC_EVEX_L2_XD_KZ, /* 5445 */ + IC_EVEX_L2_XD_KZ, /* 5446 */ + IC_EVEX_L2_XD_KZ, /* 5447 */ + IC_EVEX_L2_W_KZ, /* 5448 */ + IC_EVEX_L2_W_KZ, /* 5449 */ + IC_EVEX_L2_W_XS_KZ, /* 5450 */ + IC_EVEX_L2_W_XS_KZ, /* 5451 */ + IC_EVEX_L2_W_XD_KZ, /* 5452 */ + IC_EVEX_L2_W_XD_KZ, /* 5453 */ + IC_EVEX_L2_W_XD_KZ, /* 5454 */ + IC_EVEX_L2_W_XD_KZ, /* 5455 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5456 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5457 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5458 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5459 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5460 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5461 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5462 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5463 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5464 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5465 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5466 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5467 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5468 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5469 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5470 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5471 */ + IC_EVEX_L2_KZ, /* 5472 */ + IC_EVEX_L2_KZ, /* 5473 */ + IC_EVEX_L2_XS_KZ, /* 5474 */ + IC_EVEX_L2_XS_KZ, /* 5475 */ + IC_EVEX_L2_XD_KZ, /* 5476 */ + IC_EVEX_L2_XD_KZ, /* 5477 */ + IC_EVEX_L2_XD_KZ, /* 5478 */ + IC_EVEX_L2_XD_KZ, /* 5479 */ + IC_EVEX_L2_W_KZ, /* 5480 */ + IC_EVEX_L2_W_KZ, /* 5481 */ + IC_EVEX_L2_W_XS_KZ, /* 5482 */ + IC_EVEX_L2_W_XS_KZ, /* 5483 */ + IC_EVEX_L2_W_XD_KZ, /* 5484 */ + IC_EVEX_L2_W_XD_KZ, /* 5485 */ + IC_EVEX_L2_W_XD_KZ, /* 5486 */ + IC_EVEX_L2_W_XD_KZ, /* 5487 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5488 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5489 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5490 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5491 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5492 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5493 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5494 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5495 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5496 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5497 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5498 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5499 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5500 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5501 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5502 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5503 */ + IC_EVEX_L2_KZ, /* 5504 */ + IC_EVEX_L2_KZ, /* 5505 */ + IC_EVEX_L2_XS_KZ, /* 5506 */ + IC_EVEX_L2_XS_KZ, /* 5507 */ + IC_EVEX_L2_XD_KZ, /* 5508 */ + IC_EVEX_L2_XD_KZ, /* 5509 */ + IC_EVEX_L2_XD_KZ, /* 5510 */ + IC_EVEX_L2_XD_KZ, /* 5511 */ + IC_EVEX_L2_W_KZ, /* 5512 */ + IC_EVEX_L2_W_KZ, /* 5513 */ + IC_EVEX_L2_W_XS_KZ, /* 5514 */ + IC_EVEX_L2_W_XS_KZ, /* 5515 */ + IC_EVEX_L2_W_XD_KZ, /* 5516 */ + IC_EVEX_L2_W_XD_KZ, /* 5517 */ + IC_EVEX_L2_W_XD_KZ, /* 5518 */ + IC_EVEX_L2_W_XD_KZ, /* 5519 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5520 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5521 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5522 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5523 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5524 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5525 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5526 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5527 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5528 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5529 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5530 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5531 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5532 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5533 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5534 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5535 */ + IC_EVEX_L2_KZ, /* 5536 */ + IC_EVEX_L2_KZ, /* 5537 */ + IC_EVEX_L2_XS_KZ, /* 5538 */ + IC_EVEX_L2_XS_KZ, /* 5539 */ + IC_EVEX_L2_XD_KZ, /* 5540 */ + IC_EVEX_L2_XD_KZ, /* 5541 */ + IC_EVEX_L2_XD_KZ, /* 5542 */ + IC_EVEX_L2_XD_KZ, /* 5543 */ + IC_EVEX_L2_W_KZ, /* 5544 */ + IC_EVEX_L2_W_KZ, /* 5545 */ + IC_EVEX_L2_W_XS_KZ, /* 5546 */ + IC_EVEX_L2_W_XS_KZ, /* 5547 */ + IC_EVEX_L2_W_XD_KZ, /* 5548 */ + IC_EVEX_L2_W_XD_KZ, /* 5549 */ + IC_EVEX_L2_W_XD_KZ, /* 5550 */ + IC_EVEX_L2_W_XD_KZ, /* 5551 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5552 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5553 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5554 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5555 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5556 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5557 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5558 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5559 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5560 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5561 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5562 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5563 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5564 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5565 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5566 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5567 */ + IC_EVEX_L2_KZ, /* 5568 */ + IC_EVEX_L2_KZ, /* 5569 */ + IC_EVEX_L2_XS_KZ, /* 5570 */ + IC_EVEX_L2_XS_KZ, /* 5571 */ + IC_EVEX_L2_XD_KZ, /* 5572 */ + IC_EVEX_L2_XD_KZ, /* 5573 */ + IC_EVEX_L2_XD_KZ, /* 5574 */ + IC_EVEX_L2_XD_KZ, /* 5575 */ + IC_EVEX_L2_W_KZ, /* 5576 */ + IC_EVEX_L2_W_KZ, /* 5577 */ + IC_EVEX_L2_W_XS_KZ, /* 5578 */ + IC_EVEX_L2_W_XS_KZ, /* 5579 */ + IC_EVEX_L2_W_XD_KZ, /* 5580 */ + IC_EVEX_L2_W_XD_KZ, /* 5581 */ + IC_EVEX_L2_W_XD_KZ, /* 5582 */ + IC_EVEX_L2_W_XD_KZ, /* 5583 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5584 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5585 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5586 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5587 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5588 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5589 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5590 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5591 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5592 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5593 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5594 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5595 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5596 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5597 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5598 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5599 */ + IC_EVEX_L2_KZ, /* 5600 */ + IC_EVEX_L2_KZ, /* 5601 */ + IC_EVEX_L2_XS_KZ, /* 5602 */ + IC_EVEX_L2_XS_KZ, /* 5603 */ + IC_EVEX_L2_XD_KZ, /* 5604 */ + IC_EVEX_L2_XD_KZ, /* 5605 */ + IC_EVEX_L2_XD_KZ, /* 5606 */ + IC_EVEX_L2_XD_KZ, /* 5607 */ + IC_EVEX_L2_W_KZ, /* 5608 */ + IC_EVEX_L2_W_KZ, /* 5609 */ + IC_EVEX_L2_W_XS_KZ, /* 5610 */ + IC_EVEX_L2_W_XS_KZ, /* 5611 */ + IC_EVEX_L2_W_XD_KZ, /* 5612 */ + IC_EVEX_L2_W_XD_KZ, /* 5613 */ + IC_EVEX_L2_W_XD_KZ, /* 5614 */ + IC_EVEX_L2_W_XD_KZ, /* 5615 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5616 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5617 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5618 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5619 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5620 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5621 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5622 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5623 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5624 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5625 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5626 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5627 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5628 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5629 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5630 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5631 */ + IC, /* 5632 */ + IC_64BIT, /* 5633 */ + IC_XS, /* 5634 */ + IC_64BIT_XS, /* 5635 */ + IC_XD, /* 5636 */ + IC_64BIT_XD, /* 5637 */ + IC_XS, /* 5638 */ + IC_64BIT_XS, /* 5639 */ + IC, /* 5640 */ + IC_64BIT_REXW, /* 5641 */ + IC_XS, /* 5642 */ + IC_64BIT_REXW_XS, /* 5643 */ + IC_XD, /* 5644 */ + IC_64BIT_REXW_XD, /* 5645 */ + IC_XS, /* 5646 */ + IC_64BIT_REXW_XS, /* 5647 */ + IC_OPSIZE, /* 5648 */ + IC_64BIT_OPSIZE, /* 5649 */ + IC_XS_OPSIZE, /* 5650 */ + IC_64BIT_XS_OPSIZE, /* 5651 */ + IC_XD_OPSIZE, /* 5652 */ + IC_64BIT_XD_OPSIZE, /* 5653 */ + IC_XS_OPSIZE, /* 5654 */ + IC_64BIT_XD_OPSIZE, /* 5655 */ + IC_OPSIZE, /* 5656 */ + IC_64BIT_REXW_OPSIZE, /* 5657 */ + IC_XS_OPSIZE, /* 5658 */ + IC_64BIT_REXW_XS, /* 5659 */ + IC_XD_OPSIZE, /* 5660 */ + IC_64BIT_REXW_XD, /* 5661 */ + IC_XS_OPSIZE, /* 5662 */ + IC_64BIT_REXW_XS, /* 5663 */ + IC_ADSIZE, /* 5664 */ + IC_64BIT_ADSIZE, /* 5665 */ + IC_XS_ADSIZE, /* 5666 */ + IC_64BIT_XS_ADSIZE, /* 5667 */ + IC_XD_ADSIZE, /* 5668 */ + IC_64BIT_XD_ADSIZE, /* 5669 */ + IC_XS_ADSIZE, /* 5670 */ + IC_64BIT_XD_ADSIZE, /* 5671 */ + IC_ADSIZE, /* 5672 */ + IC_64BIT_REXW_ADSIZE, /* 5673 */ + IC_XS_ADSIZE, /* 5674 */ + IC_64BIT_REXW_XS, /* 5675 */ + IC_XD_ADSIZE, /* 5676 */ + IC_64BIT_REXW_XD, /* 5677 */ + IC_XS_ADSIZE, /* 5678 */ + IC_64BIT_REXW_XS, /* 5679 */ + IC_OPSIZE_ADSIZE, /* 5680 */ + IC_64BIT_OPSIZE_ADSIZE, /* 5681 */ + IC_XS_OPSIZE, /* 5682 */ + IC_64BIT_XS_OPSIZE, /* 5683 */ + IC_XD_OPSIZE, /* 5684 */ + IC_64BIT_XD_OPSIZE, /* 5685 */ + IC_XS_OPSIZE, /* 5686 */ + IC_64BIT_XD_OPSIZE, /* 5687 */ + IC_OPSIZE_ADSIZE, /* 5688 */ + IC_64BIT_REXW_OPSIZE, /* 5689 */ + IC_XS_OPSIZE, /* 5690 */ + IC_64BIT_REXW_XS, /* 5691 */ + IC_XD_OPSIZE, /* 5692 */ + IC_64BIT_REXW_XD, /* 5693 */ + IC_XS_OPSIZE, /* 5694 */ + IC_64BIT_REXW_XS, /* 5695 */ + IC_VEX, /* 5696 */ + IC_VEX, /* 5697 */ + IC_VEX_XS, /* 5698 */ + IC_VEX_XS, /* 5699 */ + IC_VEX_XD, /* 5700 */ + IC_VEX_XD, /* 5701 */ + IC_VEX_XD, /* 5702 */ + IC_VEX_XD, /* 5703 */ + IC_VEX_W, /* 5704 */ + IC_VEX_W, /* 5705 */ + IC_VEX_W_XS, /* 5706 */ + IC_VEX_W_XS, /* 5707 */ + IC_VEX_W_XD, /* 5708 */ + IC_VEX_W_XD, /* 5709 */ + IC_VEX_W_XD, /* 5710 */ + IC_VEX_W_XD, /* 5711 */ + IC_VEX_OPSIZE, /* 5712 */ + IC_VEX_OPSIZE, /* 5713 */ + IC_VEX_OPSIZE, /* 5714 */ + IC_VEX_OPSIZE, /* 5715 */ + IC_VEX_OPSIZE, /* 5716 */ + IC_VEX_OPSIZE, /* 5717 */ + IC_VEX_OPSIZE, /* 5718 */ + IC_VEX_OPSIZE, /* 5719 */ + IC_VEX_W_OPSIZE, /* 5720 */ + IC_VEX_W_OPSIZE, /* 5721 */ + IC_VEX_W_OPSIZE, /* 5722 */ + IC_VEX_W_OPSIZE, /* 5723 */ + IC_VEX_W_OPSIZE, /* 5724 */ + IC_VEX_W_OPSIZE, /* 5725 */ + IC_VEX_W_OPSIZE, /* 5726 */ + IC_VEX_W_OPSIZE, /* 5727 */ + IC_VEX, /* 5728 */ + IC_VEX, /* 5729 */ + IC_VEX_XS, /* 5730 */ + IC_VEX_XS, /* 5731 */ + IC_VEX_XD, /* 5732 */ + IC_VEX_XD, /* 5733 */ + IC_VEX_XD, /* 5734 */ + IC_VEX_XD, /* 5735 */ + IC_VEX_W, /* 5736 */ + IC_VEX_W, /* 5737 */ + IC_VEX_W_XS, /* 5738 */ + IC_VEX_W_XS, /* 5739 */ + IC_VEX_W_XD, /* 5740 */ + IC_VEX_W_XD, /* 5741 */ + IC_VEX_W_XD, /* 5742 */ + IC_VEX_W_XD, /* 5743 */ + IC_VEX_OPSIZE, /* 5744 */ + IC_VEX_OPSIZE, /* 5745 */ + IC_VEX_OPSIZE, /* 5746 */ + IC_VEX_OPSIZE, /* 5747 */ + IC_VEX_OPSIZE, /* 5748 */ + IC_VEX_OPSIZE, /* 5749 */ + IC_VEX_OPSIZE, /* 5750 */ + IC_VEX_OPSIZE, /* 5751 */ + IC_VEX_W_OPSIZE, /* 5752 */ + IC_VEX_W_OPSIZE, /* 5753 */ + IC_VEX_W_OPSIZE, /* 5754 */ + IC_VEX_W_OPSIZE, /* 5755 */ + IC_VEX_W_OPSIZE, /* 5756 */ + IC_VEX_W_OPSIZE, /* 5757 */ + IC_VEX_W_OPSIZE, /* 5758 */ + IC_VEX_W_OPSIZE, /* 5759 */ + IC_VEX_L, /* 5760 */ + IC_VEX_L, /* 5761 */ + IC_VEX_L_XS, /* 5762 */ + IC_VEX_L_XS, /* 5763 */ + IC_VEX_L_XD, /* 5764 */ + IC_VEX_L_XD, /* 5765 */ + IC_VEX_L_XD, /* 5766 */ + IC_VEX_L_XD, /* 5767 */ + IC_VEX_L_W, /* 5768 */ + IC_VEX_L_W, /* 5769 */ + IC_VEX_L_W_XS, /* 5770 */ + IC_VEX_L_W_XS, /* 5771 */ + IC_VEX_L_W_XD, /* 5772 */ + IC_VEX_L_W_XD, /* 5773 */ + IC_VEX_L_W_XD, /* 5774 */ + IC_VEX_L_W_XD, /* 5775 */ + IC_VEX_L_OPSIZE, /* 5776 */ + IC_VEX_L_OPSIZE, /* 5777 */ + IC_VEX_L_OPSIZE, /* 5778 */ + IC_VEX_L_OPSIZE, /* 5779 */ + IC_VEX_L_OPSIZE, /* 5780 */ + IC_VEX_L_OPSIZE, /* 5781 */ + IC_VEX_L_OPSIZE, /* 5782 */ + IC_VEX_L_OPSIZE, /* 5783 */ + IC_VEX_L_W_OPSIZE, /* 5784 */ + IC_VEX_L_W_OPSIZE, /* 5785 */ + IC_VEX_L_W_OPSIZE, /* 5786 */ + IC_VEX_L_W_OPSIZE, /* 5787 */ + IC_VEX_L_W_OPSIZE, /* 5788 */ + IC_VEX_L_W_OPSIZE, /* 5789 */ + IC_VEX_L_W_OPSIZE, /* 5790 */ + IC_VEX_L_W_OPSIZE, /* 5791 */ + IC_VEX_L, /* 5792 */ + IC_VEX_L, /* 5793 */ + IC_VEX_L_XS, /* 5794 */ + IC_VEX_L_XS, /* 5795 */ + IC_VEX_L_XD, /* 5796 */ + IC_VEX_L_XD, /* 5797 */ + IC_VEX_L_XD, /* 5798 */ + IC_VEX_L_XD, /* 5799 */ + IC_VEX_L_W, /* 5800 */ + IC_VEX_L_W, /* 5801 */ + IC_VEX_L_W_XS, /* 5802 */ + IC_VEX_L_W_XS, /* 5803 */ + IC_VEX_L_W_XD, /* 5804 */ + IC_VEX_L_W_XD, /* 5805 */ + IC_VEX_L_W_XD, /* 5806 */ + IC_VEX_L_W_XD, /* 5807 */ + IC_VEX_L_OPSIZE, /* 5808 */ + IC_VEX_L_OPSIZE, /* 5809 */ + IC_VEX_L_OPSIZE, /* 5810 */ + IC_VEX_L_OPSIZE, /* 5811 */ + IC_VEX_L_OPSIZE, /* 5812 */ + IC_VEX_L_OPSIZE, /* 5813 */ + IC_VEX_L_OPSIZE, /* 5814 */ + IC_VEX_L_OPSIZE, /* 5815 */ + IC_VEX_L_W_OPSIZE, /* 5816 */ + IC_VEX_L_W_OPSIZE, /* 5817 */ + IC_VEX_L_W_OPSIZE, /* 5818 */ + IC_VEX_L_W_OPSIZE, /* 5819 */ + IC_VEX_L_W_OPSIZE, /* 5820 */ + IC_VEX_L_W_OPSIZE, /* 5821 */ + IC_VEX_L_W_OPSIZE, /* 5822 */ + IC_VEX_L_W_OPSIZE, /* 5823 */ + IC_VEX_L, /* 5824 */ + IC_VEX_L, /* 5825 */ + IC_VEX_L_XS, /* 5826 */ + IC_VEX_L_XS, /* 5827 */ + IC_VEX_L_XD, /* 5828 */ + IC_VEX_L_XD, /* 5829 */ + IC_VEX_L_XD, /* 5830 */ + IC_VEX_L_XD, /* 5831 */ + IC_VEX_L_W, /* 5832 */ + IC_VEX_L_W, /* 5833 */ + IC_VEX_L_W_XS, /* 5834 */ + IC_VEX_L_W_XS, /* 5835 */ + IC_VEX_L_W_XD, /* 5836 */ + IC_VEX_L_W_XD, /* 5837 */ + IC_VEX_L_W_XD, /* 5838 */ + IC_VEX_L_W_XD, /* 5839 */ + IC_VEX_L_OPSIZE, /* 5840 */ + IC_VEX_L_OPSIZE, /* 5841 */ + IC_VEX_L_OPSIZE, /* 5842 */ + IC_VEX_L_OPSIZE, /* 5843 */ + IC_VEX_L_OPSIZE, /* 5844 */ + IC_VEX_L_OPSIZE, /* 5845 */ + IC_VEX_L_OPSIZE, /* 5846 */ + IC_VEX_L_OPSIZE, /* 5847 */ + IC_VEX_L_W_OPSIZE, /* 5848 */ + IC_VEX_L_W_OPSIZE, /* 5849 */ + IC_VEX_L_W_OPSIZE, /* 5850 */ + IC_VEX_L_W_OPSIZE, /* 5851 */ + IC_VEX_L_W_OPSIZE, /* 5852 */ + IC_VEX_L_W_OPSIZE, /* 5853 */ + IC_VEX_L_W_OPSIZE, /* 5854 */ + IC_VEX_L_W_OPSIZE, /* 5855 */ + IC_VEX_L, /* 5856 */ + IC_VEX_L, /* 5857 */ + IC_VEX_L_XS, /* 5858 */ + IC_VEX_L_XS, /* 5859 */ + IC_VEX_L_XD, /* 5860 */ + IC_VEX_L_XD, /* 5861 */ + IC_VEX_L_XD, /* 5862 */ + IC_VEX_L_XD, /* 5863 */ + IC_VEX_L_W, /* 5864 */ + IC_VEX_L_W, /* 5865 */ + IC_VEX_L_W_XS, /* 5866 */ + IC_VEX_L_W_XS, /* 5867 */ + IC_VEX_L_W_XD, /* 5868 */ + IC_VEX_L_W_XD, /* 5869 */ + IC_VEX_L_W_XD, /* 5870 */ + IC_VEX_L_W_XD, /* 5871 */ + IC_VEX_L_OPSIZE, /* 5872 */ + IC_VEX_L_OPSIZE, /* 5873 */ + IC_VEX_L_OPSIZE, /* 5874 */ + IC_VEX_L_OPSIZE, /* 5875 */ + IC_VEX_L_OPSIZE, /* 5876 */ + IC_VEX_L_OPSIZE, /* 5877 */ + IC_VEX_L_OPSIZE, /* 5878 */ + IC_VEX_L_OPSIZE, /* 5879 */ + IC_VEX_L_W_OPSIZE, /* 5880 */ + IC_VEX_L_W_OPSIZE, /* 5881 */ + IC_VEX_L_W_OPSIZE, /* 5882 */ + IC_VEX_L_W_OPSIZE, /* 5883 */ + IC_VEX_L_W_OPSIZE, /* 5884 */ + IC_VEX_L_W_OPSIZE, /* 5885 */ + IC_VEX_L_W_OPSIZE, /* 5886 */ + IC_VEX_L_W_OPSIZE, /* 5887 */ + IC_EVEX_L2_KZ, /* 5888 */ + IC_EVEX_L2_KZ, /* 5889 */ + IC_EVEX_L2_XS_KZ, /* 5890 */ + IC_EVEX_L2_XS_KZ, /* 5891 */ + IC_EVEX_L2_XD_KZ, /* 5892 */ + IC_EVEX_L2_XD_KZ, /* 5893 */ + IC_EVEX_L2_XD_KZ, /* 5894 */ + IC_EVEX_L2_XD_KZ, /* 5895 */ + IC_EVEX_L2_W_KZ, /* 5896 */ + IC_EVEX_L2_W_KZ, /* 5897 */ + IC_EVEX_L2_W_XS_KZ, /* 5898 */ + IC_EVEX_L2_W_XS_KZ, /* 5899 */ + IC_EVEX_L2_W_XD_KZ, /* 5900 */ + IC_EVEX_L2_W_XD_KZ, /* 5901 */ + IC_EVEX_L2_W_XD_KZ, /* 5902 */ + IC_EVEX_L2_W_XD_KZ, /* 5903 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5904 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5905 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5906 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5907 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5908 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5909 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5910 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5911 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5912 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5913 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5914 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5915 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5916 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5917 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5918 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5919 */ + IC_EVEX_L2_KZ, /* 5920 */ + IC_EVEX_L2_KZ, /* 5921 */ + IC_EVEX_L2_XS_KZ, /* 5922 */ + IC_EVEX_L2_XS_KZ, /* 5923 */ + IC_EVEX_L2_XD_KZ, /* 5924 */ + IC_EVEX_L2_XD_KZ, /* 5925 */ + IC_EVEX_L2_XD_KZ, /* 5926 */ + IC_EVEX_L2_XD_KZ, /* 5927 */ + IC_EVEX_L2_W_KZ, /* 5928 */ + IC_EVEX_L2_W_KZ, /* 5929 */ + IC_EVEX_L2_W_XS_KZ, /* 5930 */ + IC_EVEX_L2_W_XS_KZ, /* 5931 */ + IC_EVEX_L2_W_XD_KZ, /* 5932 */ + IC_EVEX_L2_W_XD_KZ, /* 5933 */ + IC_EVEX_L2_W_XD_KZ, /* 5934 */ + IC_EVEX_L2_W_XD_KZ, /* 5935 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5936 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5937 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5938 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5939 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5940 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5941 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5942 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5943 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5944 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5945 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5946 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5947 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5948 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5949 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5950 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5951 */ + IC_EVEX_L2_KZ, /* 5952 */ + IC_EVEX_L2_KZ, /* 5953 */ + IC_EVEX_L2_XS_KZ, /* 5954 */ + IC_EVEX_L2_XS_KZ, /* 5955 */ + IC_EVEX_L2_XD_KZ, /* 5956 */ + IC_EVEX_L2_XD_KZ, /* 5957 */ + IC_EVEX_L2_XD_KZ, /* 5958 */ + IC_EVEX_L2_XD_KZ, /* 5959 */ + IC_EVEX_L2_W_KZ, /* 5960 */ + IC_EVEX_L2_W_KZ, /* 5961 */ + IC_EVEX_L2_W_XS_KZ, /* 5962 */ + IC_EVEX_L2_W_XS_KZ, /* 5963 */ + IC_EVEX_L2_W_XD_KZ, /* 5964 */ + IC_EVEX_L2_W_XD_KZ, /* 5965 */ + IC_EVEX_L2_W_XD_KZ, /* 5966 */ + IC_EVEX_L2_W_XD_KZ, /* 5967 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5968 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5969 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5970 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5971 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5972 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5973 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5974 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5975 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5976 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5977 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5978 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5979 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5980 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5981 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5982 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5983 */ + IC_EVEX_L2_KZ, /* 5984 */ + IC_EVEX_L2_KZ, /* 5985 */ + IC_EVEX_L2_XS_KZ, /* 5986 */ + IC_EVEX_L2_XS_KZ, /* 5987 */ + IC_EVEX_L2_XD_KZ, /* 5988 */ + IC_EVEX_L2_XD_KZ, /* 5989 */ + IC_EVEX_L2_XD_KZ, /* 5990 */ + IC_EVEX_L2_XD_KZ, /* 5991 */ + IC_EVEX_L2_W_KZ, /* 5992 */ + IC_EVEX_L2_W_KZ, /* 5993 */ + IC_EVEX_L2_W_XS_KZ, /* 5994 */ + IC_EVEX_L2_W_XS_KZ, /* 5995 */ + IC_EVEX_L2_W_XD_KZ, /* 5996 */ + IC_EVEX_L2_W_XD_KZ, /* 5997 */ + IC_EVEX_L2_W_XD_KZ, /* 5998 */ + IC_EVEX_L2_W_XD_KZ, /* 5999 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6000 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6001 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6002 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6003 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6004 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6005 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6006 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6007 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6008 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6009 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6010 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6011 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6012 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6013 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6014 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6015 */ + IC_EVEX_L2_KZ, /* 6016 */ + IC_EVEX_L2_KZ, /* 6017 */ + IC_EVEX_L2_XS_KZ, /* 6018 */ + IC_EVEX_L2_XS_KZ, /* 6019 */ + IC_EVEX_L2_XD_KZ, /* 6020 */ + IC_EVEX_L2_XD_KZ, /* 6021 */ + IC_EVEX_L2_XD_KZ, /* 6022 */ + IC_EVEX_L2_XD_KZ, /* 6023 */ + IC_EVEX_L2_W_KZ, /* 6024 */ + IC_EVEX_L2_W_KZ, /* 6025 */ + IC_EVEX_L2_W_XS_KZ, /* 6026 */ + IC_EVEX_L2_W_XS_KZ, /* 6027 */ + IC_EVEX_L2_W_XD_KZ, /* 6028 */ + IC_EVEX_L2_W_XD_KZ, /* 6029 */ + IC_EVEX_L2_W_XD_KZ, /* 6030 */ + IC_EVEX_L2_W_XD_KZ, /* 6031 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6032 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6033 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6034 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6035 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6036 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6037 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6038 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6039 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6040 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6041 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6042 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6043 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6044 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6045 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6046 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6047 */ + IC_EVEX_L2_KZ, /* 6048 */ + IC_EVEX_L2_KZ, /* 6049 */ + IC_EVEX_L2_XS_KZ, /* 6050 */ + IC_EVEX_L2_XS_KZ, /* 6051 */ + IC_EVEX_L2_XD_KZ, /* 6052 */ + IC_EVEX_L2_XD_KZ, /* 6053 */ + IC_EVEX_L2_XD_KZ, /* 6054 */ + IC_EVEX_L2_XD_KZ, /* 6055 */ + IC_EVEX_L2_W_KZ, /* 6056 */ + IC_EVEX_L2_W_KZ, /* 6057 */ + IC_EVEX_L2_W_XS_KZ, /* 6058 */ + IC_EVEX_L2_W_XS_KZ, /* 6059 */ + IC_EVEX_L2_W_XD_KZ, /* 6060 */ + IC_EVEX_L2_W_XD_KZ, /* 6061 */ + IC_EVEX_L2_W_XD_KZ, /* 6062 */ + IC_EVEX_L2_W_XD_KZ, /* 6063 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6064 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6065 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6066 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6067 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6068 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6069 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6070 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6071 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6072 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6073 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6074 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6075 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6076 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6077 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6078 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6079 */ + IC_EVEX_L2_KZ, /* 6080 */ + IC_EVEX_L2_KZ, /* 6081 */ + IC_EVEX_L2_XS_KZ, /* 6082 */ + IC_EVEX_L2_XS_KZ, /* 6083 */ + IC_EVEX_L2_XD_KZ, /* 6084 */ + IC_EVEX_L2_XD_KZ, /* 6085 */ + IC_EVEX_L2_XD_KZ, /* 6086 */ + IC_EVEX_L2_XD_KZ, /* 6087 */ + IC_EVEX_L2_W_KZ, /* 6088 */ + IC_EVEX_L2_W_KZ, /* 6089 */ + IC_EVEX_L2_W_XS_KZ, /* 6090 */ + IC_EVEX_L2_W_XS_KZ, /* 6091 */ + IC_EVEX_L2_W_XD_KZ, /* 6092 */ + IC_EVEX_L2_W_XD_KZ, /* 6093 */ + IC_EVEX_L2_W_XD_KZ, /* 6094 */ + IC_EVEX_L2_W_XD_KZ, /* 6095 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6096 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6097 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6098 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6099 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6100 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6101 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6102 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6103 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6104 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6105 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6106 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6107 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6108 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6109 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6110 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6111 */ + IC_EVEX_L2_KZ, /* 6112 */ + IC_EVEX_L2_KZ, /* 6113 */ + IC_EVEX_L2_XS_KZ, /* 6114 */ + IC_EVEX_L2_XS_KZ, /* 6115 */ + IC_EVEX_L2_XD_KZ, /* 6116 */ + IC_EVEX_L2_XD_KZ, /* 6117 */ + IC_EVEX_L2_XD_KZ, /* 6118 */ + IC_EVEX_L2_XD_KZ, /* 6119 */ + IC_EVEX_L2_W_KZ, /* 6120 */ + IC_EVEX_L2_W_KZ, /* 6121 */ + IC_EVEX_L2_W_XS_KZ, /* 6122 */ + IC_EVEX_L2_W_XS_KZ, /* 6123 */ + IC_EVEX_L2_W_XD_KZ, /* 6124 */ + IC_EVEX_L2_W_XD_KZ, /* 6125 */ + IC_EVEX_L2_W_XD_KZ, /* 6126 */ + IC_EVEX_L2_W_XD_KZ, /* 6127 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6128 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6129 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6130 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6131 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6132 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6133 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6134 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6135 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6136 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6137 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6138 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6139 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6140 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6141 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6142 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6143 */ + IC, /* 6144 */ + IC_64BIT, /* 6145 */ + IC_XS, /* 6146 */ + IC_64BIT_XS, /* 6147 */ + IC_XD, /* 6148 */ + IC_64BIT_XD, /* 6149 */ + IC_XS, /* 6150 */ + IC_64BIT_XS, /* 6151 */ + IC, /* 6152 */ + IC_64BIT_REXW, /* 6153 */ + IC_XS, /* 6154 */ + IC_64BIT_REXW_XS, /* 6155 */ + IC_XD, /* 6156 */ + IC_64BIT_REXW_XD, /* 6157 */ + IC_XS, /* 6158 */ + IC_64BIT_REXW_XS, /* 6159 */ + IC_OPSIZE, /* 6160 */ + IC_64BIT_OPSIZE, /* 6161 */ + IC_XS_OPSIZE, /* 6162 */ + IC_64BIT_XS_OPSIZE, /* 6163 */ + IC_XD_OPSIZE, /* 6164 */ + IC_64BIT_XD_OPSIZE, /* 6165 */ + IC_XS_OPSIZE, /* 6166 */ + IC_64BIT_XD_OPSIZE, /* 6167 */ + IC_OPSIZE, /* 6168 */ + IC_64BIT_REXW_OPSIZE, /* 6169 */ + IC_XS_OPSIZE, /* 6170 */ + IC_64BIT_REXW_XS, /* 6171 */ + IC_XD_OPSIZE, /* 6172 */ + IC_64BIT_REXW_XD, /* 6173 */ + IC_XS_OPSIZE, /* 6174 */ + IC_64BIT_REXW_XS, /* 6175 */ + IC_ADSIZE, /* 6176 */ + IC_64BIT_ADSIZE, /* 6177 */ + IC_XS_ADSIZE, /* 6178 */ + IC_64BIT_XS_ADSIZE, /* 6179 */ + IC_XD_ADSIZE, /* 6180 */ + IC_64BIT_XD_ADSIZE, /* 6181 */ + IC_XS_ADSIZE, /* 6182 */ + IC_64BIT_XD_ADSIZE, /* 6183 */ + IC_ADSIZE, /* 6184 */ + IC_64BIT_REXW_ADSIZE, /* 6185 */ + IC_XS_ADSIZE, /* 6186 */ + IC_64BIT_REXW_XS, /* 6187 */ + IC_XD_ADSIZE, /* 6188 */ + IC_64BIT_REXW_XD, /* 6189 */ + IC_XS_ADSIZE, /* 6190 */ + IC_64BIT_REXW_XS, /* 6191 */ + IC_OPSIZE_ADSIZE, /* 6192 */ + IC_64BIT_OPSIZE_ADSIZE, /* 6193 */ + IC_XS_OPSIZE, /* 6194 */ + IC_64BIT_XS_OPSIZE, /* 6195 */ + IC_XD_OPSIZE, /* 6196 */ + IC_64BIT_XD_OPSIZE, /* 6197 */ + IC_XS_OPSIZE, /* 6198 */ + IC_64BIT_XD_OPSIZE, /* 6199 */ + IC_OPSIZE_ADSIZE, /* 6200 */ + IC_64BIT_REXW_OPSIZE, /* 6201 */ + IC_XS_OPSIZE, /* 6202 */ + IC_64BIT_REXW_XS, /* 6203 */ + IC_XD_OPSIZE, /* 6204 */ + IC_64BIT_REXW_XD, /* 6205 */ + IC_XS_OPSIZE, /* 6206 */ + IC_64BIT_REXW_XS, /* 6207 */ + IC_VEX, /* 6208 */ + IC_VEX, /* 6209 */ + IC_VEX_XS, /* 6210 */ + IC_VEX_XS, /* 6211 */ + IC_VEX_XD, /* 6212 */ + IC_VEX_XD, /* 6213 */ + IC_VEX_XD, /* 6214 */ + IC_VEX_XD, /* 6215 */ + IC_VEX_W, /* 6216 */ + IC_VEX_W, /* 6217 */ + IC_VEX_W_XS, /* 6218 */ + IC_VEX_W_XS, /* 6219 */ + IC_VEX_W_XD, /* 6220 */ + IC_VEX_W_XD, /* 6221 */ + IC_VEX_W_XD, /* 6222 */ + IC_VEX_W_XD, /* 6223 */ + IC_VEX_OPSIZE, /* 6224 */ + IC_VEX_OPSIZE, /* 6225 */ + IC_VEX_OPSIZE, /* 6226 */ + IC_VEX_OPSIZE, /* 6227 */ + IC_VEX_OPSIZE, /* 6228 */ + IC_VEX_OPSIZE, /* 6229 */ + IC_VEX_OPSIZE, /* 6230 */ + IC_VEX_OPSIZE, /* 6231 */ + IC_VEX_W_OPSIZE, /* 6232 */ + IC_VEX_W_OPSIZE, /* 6233 */ + IC_VEX_W_OPSIZE, /* 6234 */ + IC_VEX_W_OPSIZE, /* 6235 */ + IC_VEX_W_OPSIZE, /* 6236 */ + IC_VEX_W_OPSIZE, /* 6237 */ + IC_VEX_W_OPSIZE, /* 6238 */ + IC_VEX_W_OPSIZE, /* 6239 */ + IC_VEX, /* 6240 */ + IC_VEX, /* 6241 */ + IC_VEX_XS, /* 6242 */ + IC_VEX_XS, /* 6243 */ + IC_VEX_XD, /* 6244 */ + IC_VEX_XD, /* 6245 */ + IC_VEX_XD, /* 6246 */ + IC_VEX_XD, /* 6247 */ + IC_VEX_W, /* 6248 */ + IC_VEX_W, /* 6249 */ + IC_VEX_W_XS, /* 6250 */ + IC_VEX_W_XS, /* 6251 */ + IC_VEX_W_XD, /* 6252 */ + IC_VEX_W_XD, /* 6253 */ + IC_VEX_W_XD, /* 6254 */ + IC_VEX_W_XD, /* 6255 */ + IC_VEX_OPSIZE, /* 6256 */ + IC_VEX_OPSIZE, /* 6257 */ + IC_VEX_OPSIZE, /* 6258 */ + IC_VEX_OPSIZE, /* 6259 */ + IC_VEX_OPSIZE, /* 6260 */ + IC_VEX_OPSIZE, /* 6261 */ + IC_VEX_OPSIZE, /* 6262 */ + IC_VEX_OPSIZE, /* 6263 */ + IC_VEX_W_OPSIZE, /* 6264 */ + IC_VEX_W_OPSIZE, /* 6265 */ + IC_VEX_W_OPSIZE, /* 6266 */ + IC_VEX_W_OPSIZE, /* 6267 */ + IC_VEX_W_OPSIZE, /* 6268 */ + IC_VEX_W_OPSIZE, /* 6269 */ + IC_VEX_W_OPSIZE, /* 6270 */ + IC_VEX_W_OPSIZE, /* 6271 */ + IC_VEX_L, /* 6272 */ + IC_VEX_L, /* 6273 */ + IC_VEX_L_XS, /* 6274 */ + IC_VEX_L_XS, /* 6275 */ + IC_VEX_L_XD, /* 6276 */ + IC_VEX_L_XD, /* 6277 */ + IC_VEX_L_XD, /* 6278 */ + IC_VEX_L_XD, /* 6279 */ + IC_VEX_L_W, /* 6280 */ + IC_VEX_L_W, /* 6281 */ + IC_VEX_L_W_XS, /* 6282 */ + IC_VEX_L_W_XS, /* 6283 */ + IC_VEX_L_W_XD, /* 6284 */ + IC_VEX_L_W_XD, /* 6285 */ + IC_VEX_L_W_XD, /* 6286 */ + IC_VEX_L_W_XD, /* 6287 */ + IC_VEX_L_OPSIZE, /* 6288 */ + IC_VEX_L_OPSIZE, /* 6289 */ + IC_VEX_L_OPSIZE, /* 6290 */ + IC_VEX_L_OPSIZE, /* 6291 */ + IC_VEX_L_OPSIZE, /* 6292 */ + IC_VEX_L_OPSIZE, /* 6293 */ + IC_VEX_L_OPSIZE, /* 6294 */ + IC_VEX_L_OPSIZE, /* 6295 */ + IC_VEX_L_W_OPSIZE, /* 6296 */ + IC_VEX_L_W_OPSIZE, /* 6297 */ + IC_VEX_L_W_OPSIZE, /* 6298 */ + IC_VEX_L_W_OPSIZE, /* 6299 */ + IC_VEX_L_W_OPSIZE, /* 6300 */ + IC_VEX_L_W_OPSIZE, /* 6301 */ + IC_VEX_L_W_OPSIZE, /* 6302 */ + IC_VEX_L_W_OPSIZE, /* 6303 */ + IC_VEX_L, /* 6304 */ + IC_VEX_L, /* 6305 */ + IC_VEX_L_XS, /* 6306 */ + IC_VEX_L_XS, /* 6307 */ + IC_VEX_L_XD, /* 6308 */ + IC_VEX_L_XD, /* 6309 */ + IC_VEX_L_XD, /* 6310 */ + IC_VEX_L_XD, /* 6311 */ + IC_VEX_L_W, /* 6312 */ + IC_VEX_L_W, /* 6313 */ + IC_VEX_L_W_XS, /* 6314 */ + IC_VEX_L_W_XS, /* 6315 */ + IC_VEX_L_W_XD, /* 6316 */ + IC_VEX_L_W_XD, /* 6317 */ + IC_VEX_L_W_XD, /* 6318 */ + IC_VEX_L_W_XD, /* 6319 */ + IC_VEX_L_OPSIZE, /* 6320 */ + IC_VEX_L_OPSIZE, /* 6321 */ + IC_VEX_L_OPSIZE, /* 6322 */ + IC_VEX_L_OPSIZE, /* 6323 */ + IC_VEX_L_OPSIZE, /* 6324 */ + IC_VEX_L_OPSIZE, /* 6325 */ + IC_VEX_L_OPSIZE, /* 6326 */ + IC_VEX_L_OPSIZE, /* 6327 */ + IC_VEX_L_W_OPSIZE, /* 6328 */ + IC_VEX_L_W_OPSIZE, /* 6329 */ + IC_VEX_L_W_OPSIZE, /* 6330 */ + IC_VEX_L_W_OPSIZE, /* 6331 */ + IC_VEX_L_W_OPSIZE, /* 6332 */ + IC_VEX_L_W_OPSIZE, /* 6333 */ + IC_VEX_L_W_OPSIZE, /* 6334 */ + IC_VEX_L_W_OPSIZE, /* 6335 */ + IC_VEX_L, /* 6336 */ + IC_VEX_L, /* 6337 */ + IC_VEX_L_XS, /* 6338 */ + IC_VEX_L_XS, /* 6339 */ + IC_VEX_L_XD, /* 6340 */ + IC_VEX_L_XD, /* 6341 */ + IC_VEX_L_XD, /* 6342 */ + IC_VEX_L_XD, /* 6343 */ + IC_VEX_L_W, /* 6344 */ + IC_VEX_L_W, /* 6345 */ + IC_VEX_L_W_XS, /* 6346 */ + IC_VEX_L_W_XS, /* 6347 */ + IC_VEX_L_W_XD, /* 6348 */ + IC_VEX_L_W_XD, /* 6349 */ + IC_VEX_L_W_XD, /* 6350 */ + IC_VEX_L_W_XD, /* 6351 */ + IC_VEX_L_OPSIZE, /* 6352 */ + IC_VEX_L_OPSIZE, /* 6353 */ + IC_VEX_L_OPSIZE, /* 6354 */ + IC_VEX_L_OPSIZE, /* 6355 */ + IC_VEX_L_OPSIZE, /* 6356 */ + IC_VEX_L_OPSIZE, /* 6357 */ + IC_VEX_L_OPSIZE, /* 6358 */ + IC_VEX_L_OPSIZE, /* 6359 */ + IC_VEX_L_W_OPSIZE, /* 6360 */ + IC_VEX_L_W_OPSIZE, /* 6361 */ + IC_VEX_L_W_OPSIZE, /* 6362 */ + IC_VEX_L_W_OPSIZE, /* 6363 */ + IC_VEX_L_W_OPSIZE, /* 6364 */ + IC_VEX_L_W_OPSIZE, /* 6365 */ + IC_VEX_L_W_OPSIZE, /* 6366 */ + IC_VEX_L_W_OPSIZE, /* 6367 */ + IC_VEX_L, /* 6368 */ + IC_VEX_L, /* 6369 */ + IC_VEX_L_XS, /* 6370 */ + IC_VEX_L_XS, /* 6371 */ + IC_VEX_L_XD, /* 6372 */ + IC_VEX_L_XD, /* 6373 */ + IC_VEX_L_XD, /* 6374 */ + IC_VEX_L_XD, /* 6375 */ + IC_VEX_L_W, /* 6376 */ + IC_VEX_L_W, /* 6377 */ + IC_VEX_L_W_XS, /* 6378 */ + IC_VEX_L_W_XS, /* 6379 */ + IC_VEX_L_W_XD, /* 6380 */ + IC_VEX_L_W_XD, /* 6381 */ + IC_VEX_L_W_XD, /* 6382 */ + IC_VEX_L_W_XD, /* 6383 */ + IC_VEX_L_OPSIZE, /* 6384 */ + IC_VEX_L_OPSIZE, /* 6385 */ + IC_VEX_L_OPSIZE, /* 6386 */ + IC_VEX_L_OPSIZE, /* 6387 */ + IC_VEX_L_OPSIZE, /* 6388 */ + IC_VEX_L_OPSIZE, /* 6389 */ + IC_VEX_L_OPSIZE, /* 6390 */ + IC_VEX_L_OPSIZE, /* 6391 */ + IC_VEX_L_W_OPSIZE, /* 6392 */ + IC_VEX_L_W_OPSIZE, /* 6393 */ + IC_VEX_L_W_OPSIZE, /* 6394 */ + IC_VEX_L_W_OPSIZE, /* 6395 */ + IC_VEX_L_W_OPSIZE, /* 6396 */ + IC_VEX_L_W_OPSIZE, /* 6397 */ + IC_VEX_L_W_OPSIZE, /* 6398 */ + IC_VEX_L_W_OPSIZE, /* 6399 */ + IC_EVEX_KZ, /* 6400 */ + IC_EVEX_KZ, /* 6401 */ + IC_EVEX_XS_KZ, /* 6402 */ + IC_EVEX_XS_KZ, /* 6403 */ + IC_EVEX_XD_KZ, /* 6404 */ + IC_EVEX_XD_KZ, /* 6405 */ + IC_EVEX_XD_KZ, /* 6406 */ + IC_EVEX_XD_KZ, /* 6407 */ + IC_EVEX_W_KZ, /* 6408 */ + IC_EVEX_W_KZ, /* 6409 */ + IC_EVEX_W_XS_KZ, /* 6410 */ + IC_EVEX_W_XS_KZ, /* 6411 */ + IC_EVEX_W_XD_KZ, /* 6412 */ + IC_EVEX_W_XD_KZ, /* 6413 */ + IC_EVEX_W_XD_KZ, /* 6414 */ + IC_EVEX_W_XD_KZ, /* 6415 */ + IC_EVEX_OPSIZE_KZ, /* 6416 */ + IC_EVEX_OPSIZE_KZ, /* 6417 */ + IC_EVEX_OPSIZE_KZ, /* 6418 */ + IC_EVEX_OPSIZE_KZ, /* 6419 */ + IC_EVEX_OPSIZE_KZ, /* 6420 */ + IC_EVEX_OPSIZE_KZ, /* 6421 */ + IC_EVEX_OPSIZE_KZ, /* 6422 */ + IC_EVEX_OPSIZE_KZ, /* 6423 */ + IC_EVEX_W_OPSIZE_KZ, /* 6424 */ + IC_EVEX_W_OPSIZE_KZ, /* 6425 */ + IC_EVEX_W_OPSIZE_KZ, /* 6426 */ + IC_EVEX_W_OPSIZE_KZ, /* 6427 */ + IC_EVEX_W_OPSIZE_KZ, /* 6428 */ + IC_EVEX_W_OPSIZE_KZ, /* 6429 */ + IC_EVEX_W_OPSIZE_KZ, /* 6430 */ + IC_EVEX_W_OPSIZE_KZ, /* 6431 */ + IC_EVEX_KZ, /* 6432 */ + IC_EVEX_KZ, /* 6433 */ + IC_EVEX_XS_KZ, /* 6434 */ + IC_EVEX_XS_KZ, /* 6435 */ + IC_EVEX_XD_KZ, /* 6436 */ + IC_EVEX_XD_KZ, /* 6437 */ + IC_EVEX_XD_KZ, /* 6438 */ + IC_EVEX_XD_KZ, /* 6439 */ + IC_EVEX_W_KZ, /* 6440 */ + IC_EVEX_W_KZ, /* 6441 */ + IC_EVEX_W_XS_KZ, /* 6442 */ + IC_EVEX_W_XS_KZ, /* 6443 */ + IC_EVEX_W_XD_KZ, /* 6444 */ + IC_EVEX_W_XD_KZ, /* 6445 */ + IC_EVEX_W_XD_KZ, /* 6446 */ + IC_EVEX_W_XD_KZ, /* 6447 */ + IC_EVEX_OPSIZE_KZ, /* 6448 */ + IC_EVEX_OPSIZE_KZ, /* 6449 */ + IC_EVEX_OPSIZE_KZ, /* 6450 */ + IC_EVEX_OPSIZE_KZ, /* 6451 */ + IC_EVEX_OPSIZE_KZ, /* 6452 */ + IC_EVEX_OPSIZE_KZ, /* 6453 */ + IC_EVEX_OPSIZE_KZ, /* 6454 */ + IC_EVEX_OPSIZE_KZ, /* 6455 */ + IC_EVEX_W_OPSIZE_KZ, /* 6456 */ + IC_EVEX_W_OPSIZE_KZ, /* 6457 */ + IC_EVEX_W_OPSIZE_KZ, /* 6458 */ + IC_EVEX_W_OPSIZE_KZ, /* 6459 */ + IC_EVEX_W_OPSIZE_KZ, /* 6460 */ + IC_EVEX_W_OPSIZE_KZ, /* 6461 */ + IC_EVEX_W_OPSIZE_KZ, /* 6462 */ + IC_EVEX_W_OPSIZE_KZ, /* 6463 */ + IC_EVEX_KZ, /* 6464 */ + IC_EVEX_KZ, /* 6465 */ + IC_EVEX_XS_KZ, /* 6466 */ + IC_EVEX_XS_KZ, /* 6467 */ + IC_EVEX_XD_KZ, /* 6468 */ + IC_EVEX_XD_KZ, /* 6469 */ + IC_EVEX_XD_KZ, /* 6470 */ + IC_EVEX_XD_KZ, /* 6471 */ + IC_EVEX_W_KZ, /* 6472 */ + IC_EVEX_W_KZ, /* 6473 */ + IC_EVEX_W_XS_KZ, /* 6474 */ + IC_EVEX_W_XS_KZ, /* 6475 */ + IC_EVEX_W_XD_KZ, /* 6476 */ + IC_EVEX_W_XD_KZ, /* 6477 */ + IC_EVEX_W_XD_KZ, /* 6478 */ + IC_EVEX_W_XD_KZ, /* 6479 */ + IC_EVEX_OPSIZE_KZ, /* 6480 */ + IC_EVEX_OPSIZE_KZ, /* 6481 */ + IC_EVEX_OPSIZE_KZ, /* 6482 */ + IC_EVEX_OPSIZE_KZ, /* 6483 */ + IC_EVEX_OPSIZE_KZ, /* 6484 */ + IC_EVEX_OPSIZE_KZ, /* 6485 */ + IC_EVEX_OPSIZE_KZ, /* 6486 */ + IC_EVEX_OPSIZE_KZ, /* 6487 */ + IC_EVEX_W_OPSIZE_KZ, /* 6488 */ + IC_EVEX_W_OPSIZE_KZ, /* 6489 */ + IC_EVEX_W_OPSIZE_KZ, /* 6490 */ + IC_EVEX_W_OPSIZE_KZ, /* 6491 */ + IC_EVEX_W_OPSIZE_KZ, /* 6492 */ + IC_EVEX_W_OPSIZE_KZ, /* 6493 */ + IC_EVEX_W_OPSIZE_KZ, /* 6494 */ + IC_EVEX_W_OPSIZE_KZ, /* 6495 */ + IC_EVEX_KZ, /* 6496 */ + IC_EVEX_KZ, /* 6497 */ + IC_EVEX_XS_KZ, /* 6498 */ + IC_EVEX_XS_KZ, /* 6499 */ + IC_EVEX_XD_KZ, /* 6500 */ + IC_EVEX_XD_KZ, /* 6501 */ + IC_EVEX_XD_KZ, /* 6502 */ + IC_EVEX_XD_KZ, /* 6503 */ + IC_EVEX_W_KZ, /* 6504 */ + IC_EVEX_W_KZ, /* 6505 */ + IC_EVEX_W_XS_KZ, /* 6506 */ + IC_EVEX_W_XS_KZ, /* 6507 */ + IC_EVEX_W_XD_KZ, /* 6508 */ + IC_EVEX_W_XD_KZ, /* 6509 */ + IC_EVEX_W_XD_KZ, /* 6510 */ + IC_EVEX_W_XD_KZ, /* 6511 */ + IC_EVEX_OPSIZE_KZ, /* 6512 */ + IC_EVEX_OPSIZE_KZ, /* 6513 */ + IC_EVEX_OPSIZE_KZ, /* 6514 */ + IC_EVEX_OPSIZE_KZ, /* 6515 */ + IC_EVEX_OPSIZE_KZ, /* 6516 */ + IC_EVEX_OPSIZE_KZ, /* 6517 */ + IC_EVEX_OPSIZE_KZ, /* 6518 */ + IC_EVEX_OPSIZE_KZ, /* 6519 */ + IC_EVEX_W_OPSIZE_KZ, /* 6520 */ + IC_EVEX_W_OPSIZE_KZ, /* 6521 */ + IC_EVEX_W_OPSIZE_KZ, /* 6522 */ + IC_EVEX_W_OPSIZE_KZ, /* 6523 */ + IC_EVEX_W_OPSIZE_KZ, /* 6524 */ + IC_EVEX_W_OPSIZE_KZ, /* 6525 */ + IC_EVEX_W_OPSIZE_KZ, /* 6526 */ + IC_EVEX_W_OPSIZE_KZ, /* 6527 */ + IC_EVEX_KZ, /* 6528 */ + IC_EVEX_KZ, /* 6529 */ + IC_EVEX_XS_KZ, /* 6530 */ + IC_EVEX_XS_KZ, /* 6531 */ + IC_EVEX_XD_KZ, /* 6532 */ + IC_EVEX_XD_KZ, /* 6533 */ + IC_EVEX_XD_KZ, /* 6534 */ + IC_EVEX_XD_KZ, /* 6535 */ + IC_EVEX_W_KZ, /* 6536 */ + IC_EVEX_W_KZ, /* 6537 */ + IC_EVEX_W_XS_KZ, /* 6538 */ + IC_EVEX_W_XS_KZ, /* 6539 */ + IC_EVEX_W_XD_KZ, /* 6540 */ + IC_EVEX_W_XD_KZ, /* 6541 */ + IC_EVEX_W_XD_KZ, /* 6542 */ + IC_EVEX_W_XD_KZ, /* 6543 */ + IC_EVEX_OPSIZE_KZ, /* 6544 */ + IC_EVEX_OPSIZE_KZ, /* 6545 */ + IC_EVEX_OPSIZE_KZ, /* 6546 */ + IC_EVEX_OPSIZE_KZ, /* 6547 */ + IC_EVEX_OPSIZE_KZ, /* 6548 */ + IC_EVEX_OPSIZE_KZ, /* 6549 */ + IC_EVEX_OPSIZE_KZ, /* 6550 */ + IC_EVEX_OPSIZE_KZ, /* 6551 */ + IC_EVEX_W_OPSIZE_KZ, /* 6552 */ + IC_EVEX_W_OPSIZE_KZ, /* 6553 */ + IC_EVEX_W_OPSIZE_KZ, /* 6554 */ + IC_EVEX_W_OPSIZE_KZ, /* 6555 */ + IC_EVEX_W_OPSIZE_KZ, /* 6556 */ + IC_EVEX_W_OPSIZE_KZ, /* 6557 */ + IC_EVEX_W_OPSIZE_KZ, /* 6558 */ + IC_EVEX_W_OPSIZE_KZ, /* 6559 */ + IC_EVEX_KZ, /* 6560 */ + IC_EVEX_KZ, /* 6561 */ + IC_EVEX_XS_KZ, /* 6562 */ + IC_EVEX_XS_KZ, /* 6563 */ + IC_EVEX_XD_KZ, /* 6564 */ + IC_EVEX_XD_KZ, /* 6565 */ + IC_EVEX_XD_KZ, /* 6566 */ + IC_EVEX_XD_KZ, /* 6567 */ + IC_EVEX_W_KZ, /* 6568 */ + IC_EVEX_W_KZ, /* 6569 */ + IC_EVEX_W_XS_KZ, /* 6570 */ + IC_EVEX_W_XS_KZ, /* 6571 */ + IC_EVEX_W_XD_KZ, /* 6572 */ + IC_EVEX_W_XD_KZ, /* 6573 */ + IC_EVEX_W_XD_KZ, /* 6574 */ + IC_EVEX_W_XD_KZ, /* 6575 */ + IC_EVEX_OPSIZE_KZ, /* 6576 */ + IC_EVEX_OPSIZE_KZ, /* 6577 */ + IC_EVEX_OPSIZE_KZ, /* 6578 */ + IC_EVEX_OPSIZE_KZ, /* 6579 */ + IC_EVEX_OPSIZE_KZ, /* 6580 */ + IC_EVEX_OPSIZE_KZ, /* 6581 */ + IC_EVEX_OPSIZE_KZ, /* 6582 */ + IC_EVEX_OPSIZE_KZ, /* 6583 */ + IC_EVEX_W_OPSIZE_KZ, /* 6584 */ + IC_EVEX_W_OPSIZE_KZ, /* 6585 */ + IC_EVEX_W_OPSIZE_KZ, /* 6586 */ + IC_EVEX_W_OPSIZE_KZ, /* 6587 */ + IC_EVEX_W_OPSIZE_KZ, /* 6588 */ + IC_EVEX_W_OPSIZE_KZ, /* 6589 */ + IC_EVEX_W_OPSIZE_KZ, /* 6590 */ + IC_EVEX_W_OPSIZE_KZ, /* 6591 */ + IC_EVEX_KZ, /* 6592 */ + IC_EVEX_KZ, /* 6593 */ + IC_EVEX_XS_KZ, /* 6594 */ + IC_EVEX_XS_KZ, /* 6595 */ + IC_EVEX_XD_KZ, /* 6596 */ + IC_EVEX_XD_KZ, /* 6597 */ + IC_EVEX_XD_KZ, /* 6598 */ + IC_EVEX_XD_KZ, /* 6599 */ + IC_EVEX_W_KZ, /* 6600 */ + IC_EVEX_W_KZ, /* 6601 */ + IC_EVEX_W_XS_KZ, /* 6602 */ + IC_EVEX_W_XS_KZ, /* 6603 */ + IC_EVEX_W_XD_KZ, /* 6604 */ + IC_EVEX_W_XD_KZ, /* 6605 */ + IC_EVEX_W_XD_KZ, /* 6606 */ + IC_EVEX_W_XD_KZ, /* 6607 */ + IC_EVEX_OPSIZE_KZ, /* 6608 */ + IC_EVEX_OPSIZE_KZ, /* 6609 */ + IC_EVEX_OPSIZE_KZ, /* 6610 */ + IC_EVEX_OPSIZE_KZ, /* 6611 */ + IC_EVEX_OPSIZE_KZ, /* 6612 */ + IC_EVEX_OPSIZE_KZ, /* 6613 */ + IC_EVEX_OPSIZE_KZ, /* 6614 */ + IC_EVEX_OPSIZE_KZ, /* 6615 */ + IC_EVEX_W_OPSIZE_KZ, /* 6616 */ + IC_EVEX_W_OPSIZE_KZ, /* 6617 */ + IC_EVEX_W_OPSIZE_KZ, /* 6618 */ + IC_EVEX_W_OPSIZE_KZ, /* 6619 */ + IC_EVEX_W_OPSIZE_KZ, /* 6620 */ + IC_EVEX_W_OPSIZE_KZ, /* 6621 */ + IC_EVEX_W_OPSIZE_KZ, /* 6622 */ + IC_EVEX_W_OPSIZE_KZ, /* 6623 */ + IC_EVEX_KZ, /* 6624 */ + IC_EVEX_KZ, /* 6625 */ + IC_EVEX_XS_KZ, /* 6626 */ + IC_EVEX_XS_KZ, /* 6627 */ + IC_EVEX_XD_KZ, /* 6628 */ + IC_EVEX_XD_KZ, /* 6629 */ + IC_EVEX_XD_KZ, /* 6630 */ + IC_EVEX_XD_KZ, /* 6631 */ + IC_EVEX_W_KZ, /* 6632 */ + IC_EVEX_W_KZ, /* 6633 */ + IC_EVEX_W_XS_KZ, /* 6634 */ + IC_EVEX_W_XS_KZ, /* 6635 */ + IC_EVEX_W_XD_KZ, /* 6636 */ + IC_EVEX_W_XD_KZ, /* 6637 */ + IC_EVEX_W_XD_KZ, /* 6638 */ + IC_EVEX_W_XD_KZ, /* 6639 */ + IC_EVEX_OPSIZE_KZ, /* 6640 */ + IC_EVEX_OPSIZE_KZ, /* 6641 */ + IC_EVEX_OPSIZE_KZ, /* 6642 */ + IC_EVEX_OPSIZE_KZ, /* 6643 */ + IC_EVEX_OPSIZE_KZ, /* 6644 */ + IC_EVEX_OPSIZE_KZ, /* 6645 */ + IC_EVEX_OPSIZE_KZ, /* 6646 */ + IC_EVEX_OPSIZE_KZ, /* 6647 */ + IC_EVEX_W_OPSIZE_KZ, /* 6648 */ + IC_EVEX_W_OPSIZE_KZ, /* 6649 */ + IC_EVEX_W_OPSIZE_KZ, /* 6650 */ + IC_EVEX_W_OPSIZE_KZ, /* 6651 */ + IC_EVEX_W_OPSIZE_KZ, /* 6652 */ + IC_EVEX_W_OPSIZE_KZ, /* 6653 */ + IC_EVEX_W_OPSIZE_KZ, /* 6654 */ + IC_EVEX_W_OPSIZE_KZ, /* 6655 */ + IC, /* 6656 */ + IC_64BIT, /* 6657 */ + IC_XS, /* 6658 */ + IC_64BIT_XS, /* 6659 */ + IC_XD, /* 6660 */ + IC_64BIT_XD, /* 6661 */ + IC_XS, /* 6662 */ + IC_64BIT_XS, /* 6663 */ + IC, /* 6664 */ + IC_64BIT_REXW, /* 6665 */ + IC_XS, /* 6666 */ + IC_64BIT_REXW_XS, /* 6667 */ + IC_XD, /* 6668 */ + IC_64BIT_REXW_XD, /* 6669 */ + IC_XS, /* 6670 */ + IC_64BIT_REXW_XS, /* 6671 */ + IC_OPSIZE, /* 6672 */ + IC_64BIT_OPSIZE, /* 6673 */ + IC_XS_OPSIZE, /* 6674 */ + IC_64BIT_XS_OPSIZE, /* 6675 */ + IC_XD_OPSIZE, /* 6676 */ + IC_64BIT_XD_OPSIZE, /* 6677 */ + IC_XS_OPSIZE, /* 6678 */ + IC_64BIT_XD_OPSIZE, /* 6679 */ + IC_OPSIZE, /* 6680 */ + IC_64BIT_REXW_OPSIZE, /* 6681 */ + IC_XS_OPSIZE, /* 6682 */ + IC_64BIT_REXW_XS, /* 6683 */ + IC_XD_OPSIZE, /* 6684 */ + IC_64BIT_REXW_XD, /* 6685 */ + IC_XS_OPSIZE, /* 6686 */ + IC_64BIT_REXW_XS, /* 6687 */ + IC_ADSIZE, /* 6688 */ + IC_64BIT_ADSIZE, /* 6689 */ + IC_XS_ADSIZE, /* 6690 */ + IC_64BIT_XS_ADSIZE, /* 6691 */ + IC_XD_ADSIZE, /* 6692 */ + IC_64BIT_XD_ADSIZE, /* 6693 */ + IC_XS_ADSIZE, /* 6694 */ + IC_64BIT_XD_ADSIZE, /* 6695 */ + IC_ADSIZE, /* 6696 */ + IC_64BIT_REXW_ADSIZE, /* 6697 */ + IC_XS_ADSIZE, /* 6698 */ + IC_64BIT_REXW_XS, /* 6699 */ + IC_XD_ADSIZE, /* 6700 */ + IC_64BIT_REXW_XD, /* 6701 */ + IC_XS_ADSIZE, /* 6702 */ + IC_64BIT_REXW_XS, /* 6703 */ + IC_OPSIZE_ADSIZE, /* 6704 */ + IC_64BIT_OPSIZE_ADSIZE, /* 6705 */ + IC_XS_OPSIZE, /* 6706 */ + IC_64BIT_XS_OPSIZE, /* 6707 */ + IC_XD_OPSIZE, /* 6708 */ + IC_64BIT_XD_OPSIZE, /* 6709 */ + IC_XS_OPSIZE, /* 6710 */ + IC_64BIT_XD_OPSIZE, /* 6711 */ + IC_OPSIZE_ADSIZE, /* 6712 */ + IC_64BIT_REXW_OPSIZE, /* 6713 */ + IC_XS_OPSIZE, /* 6714 */ + IC_64BIT_REXW_XS, /* 6715 */ + IC_XD_OPSIZE, /* 6716 */ + IC_64BIT_REXW_XD, /* 6717 */ + IC_XS_OPSIZE, /* 6718 */ + IC_64BIT_REXW_XS, /* 6719 */ + IC_VEX, /* 6720 */ + IC_VEX, /* 6721 */ + IC_VEX_XS, /* 6722 */ + IC_VEX_XS, /* 6723 */ + IC_VEX_XD, /* 6724 */ + IC_VEX_XD, /* 6725 */ + IC_VEX_XD, /* 6726 */ + IC_VEX_XD, /* 6727 */ + IC_VEX_W, /* 6728 */ + IC_VEX_W, /* 6729 */ + IC_VEX_W_XS, /* 6730 */ + IC_VEX_W_XS, /* 6731 */ + IC_VEX_W_XD, /* 6732 */ + IC_VEX_W_XD, /* 6733 */ + IC_VEX_W_XD, /* 6734 */ + IC_VEX_W_XD, /* 6735 */ + IC_VEX_OPSIZE, /* 6736 */ + IC_VEX_OPSIZE, /* 6737 */ + IC_VEX_OPSIZE, /* 6738 */ + IC_VEX_OPSIZE, /* 6739 */ + IC_VEX_OPSIZE, /* 6740 */ + IC_VEX_OPSIZE, /* 6741 */ + IC_VEX_OPSIZE, /* 6742 */ + IC_VEX_OPSIZE, /* 6743 */ + IC_VEX_W_OPSIZE, /* 6744 */ + IC_VEX_W_OPSIZE, /* 6745 */ + IC_VEX_W_OPSIZE, /* 6746 */ + IC_VEX_W_OPSIZE, /* 6747 */ + IC_VEX_W_OPSIZE, /* 6748 */ + IC_VEX_W_OPSIZE, /* 6749 */ + IC_VEX_W_OPSIZE, /* 6750 */ + IC_VEX_W_OPSIZE, /* 6751 */ + IC_VEX, /* 6752 */ + IC_VEX, /* 6753 */ + IC_VEX_XS, /* 6754 */ + IC_VEX_XS, /* 6755 */ + IC_VEX_XD, /* 6756 */ + IC_VEX_XD, /* 6757 */ + IC_VEX_XD, /* 6758 */ + IC_VEX_XD, /* 6759 */ + IC_VEX_W, /* 6760 */ + IC_VEX_W, /* 6761 */ + IC_VEX_W_XS, /* 6762 */ + IC_VEX_W_XS, /* 6763 */ + IC_VEX_W_XD, /* 6764 */ + IC_VEX_W_XD, /* 6765 */ + IC_VEX_W_XD, /* 6766 */ + IC_VEX_W_XD, /* 6767 */ + IC_VEX_OPSIZE, /* 6768 */ + IC_VEX_OPSIZE, /* 6769 */ + IC_VEX_OPSIZE, /* 6770 */ + IC_VEX_OPSIZE, /* 6771 */ + IC_VEX_OPSIZE, /* 6772 */ + IC_VEX_OPSIZE, /* 6773 */ + IC_VEX_OPSIZE, /* 6774 */ + IC_VEX_OPSIZE, /* 6775 */ + IC_VEX_W_OPSIZE, /* 6776 */ + IC_VEX_W_OPSIZE, /* 6777 */ + IC_VEX_W_OPSIZE, /* 6778 */ + IC_VEX_W_OPSIZE, /* 6779 */ + IC_VEX_W_OPSIZE, /* 6780 */ + IC_VEX_W_OPSIZE, /* 6781 */ + IC_VEX_W_OPSIZE, /* 6782 */ + IC_VEX_W_OPSIZE, /* 6783 */ + IC_VEX_L, /* 6784 */ + IC_VEX_L, /* 6785 */ + IC_VEX_L_XS, /* 6786 */ + IC_VEX_L_XS, /* 6787 */ + IC_VEX_L_XD, /* 6788 */ + IC_VEX_L_XD, /* 6789 */ + IC_VEX_L_XD, /* 6790 */ + IC_VEX_L_XD, /* 6791 */ + IC_VEX_L_W, /* 6792 */ + IC_VEX_L_W, /* 6793 */ + IC_VEX_L_W_XS, /* 6794 */ + IC_VEX_L_W_XS, /* 6795 */ + IC_VEX_L_W_XD, /* 6796 */ + IC_VEX_L_W_XD, /* 6797 */ + IC_VEX_L_W_XD, /* 6798 */ + IC_VEX_L_W_XD, /* 6799 */ + IC_VEX_L_OPSIZE, /* 6800 */ + IC_VEX_L_OPSIZE, /* 6801 */ + IC_VEX_L_OPSIZE, /* 6802 */ + IC_VEX_L_OPSIZE, /* 6803 */ + IC_VEX_L_OPSIZE, /* 6804 */ + IC_VEX_L_OPSIZE, /* 6805 */ + IC_VEX_L_OPSIZE, /* 6806 */ + IC_VEX_L_OPSIZE, /* 6807 */ + IC_VEX_L_W_OPSIZE, /* 6808 */ + IC_VEX_L_W_OPSIZE, /* 6809 */ + IC_VEX_L_W_OPSIZE, /* 6810 */ + IC_VEX_L_W_OPSIZE, /* 6811 */ + IC_VEX_L_W_OPSIZE, /* 6812 */ + IC_VEX_L_W_OPSIZE, /* 6813 */ + IC_VEX_L_W_OPSIZE, /* 6814 */ + IC_VEX_L_W_OPSIZE, /* 6815 */ + IC_VEX_L, /* 6816 */ + IC_VEX_L, /* 6817 */ + IC_VEX_L_XS, /* 6818 */ + IC_VEX_L_XS, /* 6819 */ + IC_VEX_L_XD, /* 6820 */ + IC_VEX_L_XD, /* 6821 */ + IC_VEX_L_XD, /* 6822 */ + IC_VEX_L_XD, /* 6823 */ + IC_VEX_L_W, /* 6824 */ + IC_VEX_L_W, /* 6825 */ + IC_VEX_L_W_XS, /* 6826 */ + IC_VEX_L_W_XS, /* 6827 */ + IC_VEX_L_W_XD, /* 6828 */ + IC_VEX_L_W_XD, /* 6829 */ + IC_VEX_L_W_XD, /* 6830 */ + IC_VEX_L_W_XD, /* 6831 */ + IC_VEX_L_OPSIZE, /* 6832 */ + IC_VEX_L_OPSIZE, /* 6833 */ + IC_VEX_L_OPSIZE, /* 6834 */ + IC_VEX_L_OPSIZE, /* 6835 */ + IC_VEX_L_OPSIZE, /* 6836 */ + IC_VEX_L_OPSIZE, /* 6837 */ + IC_VEX_L_OPSIZE, /* 6838 */ + IC_VEX_L_OPSIZE, /* 6839 */ + IC_VEX_L_W_OPSIZE, /* 6840 */ + IC_VEX_L_W_OPSIZE, /* 6841 */ + IC_VEX_L_W_OPSIZE, /* 6842 */ + IC_VEX_L_W_OPSIZE, /* 6843 */ + IC_VEX_L_W_OPSIZE, /* 6844 */ + IC_VEX_L_W_OPSIZE, /* 6845 */ + IC_VEX_L_W_OPSIZE, /* 6846 */ + IC_VEX_L_W_OPSIZE, /* 6847 */ + IC_VEX_L, /* 6848 */ + IC_VEX_L, /* 6849 */ + IC_VEX_L_XS, /* 6850 */ + IC_VEX_L_XS, /* 6851 */ + IC_VEX_L_XD, /* 6852 */ + IC_VEX_L_XD, /* 6853 */ + IC_VEX_L_XD, /* 6854 */ + IC_VEX_L_XD, /* 6855 */ + IC_VEX_L_W, /* 6856 */ + IC_VEX_L_W, /* 6857 */ + IC_VEX_L_W_XS, /* 6858 */ + IC_VEX_L_W_XS, /* 6859 */ + IC_VEX_L_W_XD, /* 6860 */ + IC_VEX_L_W_XD, /* 6861 */ + IC_VEX_L_W_XD, /* 6862 */ + IC_VEX_L_W_XD, /* 6863 */ + IC_VEX_L_OPSIZE, /* 6864 */ + IC_VEX_L_OPSIZE, /* 6865 */ + IC_VEX_L_OPSIZE, /* 6866 */ + IC_VEX_L_OPSIZE, /* 6867 */ + IC_VEX_L_OPSIZE, /* 6868 */ + IC_VEX_L_OPSIZE, /* 6869 */ + IC_VEX_L_OPSIZE, /* 6870 */ + IC_VEX_L_OPSIZE, /* 6871 */ + IC_VEX_L_W_OPSIZE, /* 6872 */ + IC_VEX_L_W_OPSIZE, /* 6873 */ + IC_VEX_L_W_OPSIZE, /* 6874 */ + IC_VEX_L_W_OPSIZE, /* 6875 */ + IC_VEX_L_W_OPSIZE, /* 6876 */ + IC_VEX_L_W_OPSIZE, /* 6877 */ + IC_VEX_L_W_OPSIZE, /* 6878 */ + IC_VEX_L_W_OPSIZE, /* 6879 */ + IC_VEX_L, /* 6880 */ + IC_VEX_L, /* 6881 */ + IC_VEX_L_XS, /* 6882 */ + IC_VEX_L_XS, /* 6883 */ + IC_VEX_L_XD, /* 6884 */ + IC_VEX_L_XD, /* 6885 */ + IC_VEX_L_XD, /* 6886 */ + IC_VEX_L_XD, /* 6887 */ + IC_VEX_L_W, /* 6888 */ + IC_VEX_L_W, /* 6889 */ + IC_VEX_L_W_XS, /* 6890 */ + IC_VEX_L_W_XS, /* 6891 */ + IC_VEX_L_W_XD, /* 6892 */ + IC_VEX_L_W_XD, /* 6893 */ + IC_VEX_L_W_XD, /* 6894 */ + IC_VEX_L_W_XD, /* 6895 */ + IC_VEX_L_OPSIZE, /* 6896 */ + IC_VEX_L_OPSIZE, /* 6897 */ + IC_VEX_L_OPSIZE, /* 6898 */ + IC_VEX_L_OPSIZE, /* 6899 */ + IC_VEX_L_OPSIZE, /* 6900 */ + IC_VEX_L_OPSIZE, /* 6901 */ + IC_VEX_L_OPSIZE, /* 6902 */ + IC_VEX_L_OPSIZE, /* 6903 */ + IC_VEX_L_W_OPSIZE, /* 6904 */ + IC_VEX_L_W_OPSIZE, /* 6905 */ + IC_VEX_L_W_OPSIZE, /* 6906 */ + IC_VEX_L_W_OPSIZE, /* 6907 */ + IC_VEX_L_W_OPSIZE, /* 6908 */ + IC_VEX_L_W_OPSIZE, /* 6909 */ + IC_VEX_L_W_OPSIZE, /* 6910 */ + IC_VEX_L_W_OPSIZE, /* 6911 */ + IC_EVEX_L_KZ, /* 6912 */ + IC_EVEX_L_KZ, /* 6913 */ + IC_EVEX_L_XS_KZ, /* 6914 */ + IC_EVEX_L_XS_KZ, /* 6915 */ + IC_EVEX_L_XD_KZ, /* 6916 */ + IC_EVEX_L_XD_KZ, /* 6917 */ + IC_EVEX_L_XD_KZ, /* 6918 */ + IC_EVEX_L_XD_KZ, /* 6919 */ + IC_EVEX_L_W_KZ, /* 6920 */ + IC_EVEX_L_W_KZ, /* 6921 */ + IC_EVEX_L_W_XS_KZ, /* 6922 */ + IC_EVEX_L_W_XS_KZ, /* 6923 */ + IC_EVEX_L_W_XD_KZ, /* 6924 */ + IC_EVEX_L_W_XD_KZ, /* 6925 */ + IC_EVEX_L_W_XD_KZ, /* 6926 */ + IC_EVEX_L_W_XD_KZ, /* 6927 */ + IC_EVEX_L_OPSIZE_KZ, /* 6928 */ + IC_EVEX_L_OPSIZE_KZ, /* 6929 */ + IC_EVEX_L_OPSIZE_KZ, /* 6930 */ + IC_EVEX_L_OPSIZE_KZ, /* 6931 */ + IC_EVEX_L_OPSIZE_KZ, /* 6932 */ + IC_EVEX_L_OPSIZE_KZ, /* 6933 */ + IC_EVEX_L_OPSIZE_KZ, /* 6934 */ + IC_EVEX_L_OPSIZE_KZ, /* 6935 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6936 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6937 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6938 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6939 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6940 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6941 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6942 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6943 */ + IC_EVEX_L_KZ, /* 6944 */ + IC_EVEX_L_KZ, /* 6945 */ + IC_EVEX_L_XS_KZ, /* 6946 */ + IC_EVEX_L_XS_KZ, /* 6947 */ + IC_EVEX_L_XD_KZ, /* 6948 */ + IC_EVEX_L_XD_KZ, /* 6949 */ + IC_EVEX_L_XD_KZ, /* 6950 */ + IC_EVEX_L_XD_KZ, /* 6951 */ + IC_EVEX_L_W_KZ, /* 6952 */ + IC_EVEX_L_W_KZ, /* 6953 */ + IC_EVEX_L_W_XS_KZ, /* 6954 */ + IC_EVEX_L_W_XS_KZ, /* 6955 */ + IC_EVEX_L_W_XD_KZ, /* 6956 */ + IC_EVEX_L_W_XD_KZ, /* 6957 */ + IC_EVEX_L_W_XD_KZ, /* 6958 */ + IC_EVEX_L_W_XD_KZ, /* 6959 */ + IC_EVEX_L_OPSIZE_KZ, /* 6960 */ + IC_EVEX_L_OPSIZE_KZ, /* 6961 */ + IC_EVEX_L_OPSIZE_KZ, /* 6962 */ + IC_EVEX_L_OPSIZE_KZ, /* 6963 */ + IC_EVEX_L_OPSIZE_KZ, /* 6964 */ + IC_EVEX_L_OPSIZE_KZ, /* 6965 */ + IC_EVEX_L_OPSIZE_KZ, /* 6966 */ + IC_EVEX_L_OPSIZE_KZ, /* 6967 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6968 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6969 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6970 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6971 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6972 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6973 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6974 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6975 */ + IC_EVEX_L_KZ, /* 6976 */ + IC_EVEX_L_KZ, /* 6977 */ + IC_EVEX_L_XS_KZ, /* 6978 */ + IC_EVEX_L_XS_KZ, /* 6979 */ + IC_EVEX_L_XD_KZ, /* 6980 */ + IC_EVEX_L_XD_KZ, /* 6981 */ + IC_EVEX_L_XD_KZ, /* 6982 */ + IC_EVEX_L_XD_KZ, /* 6983 */ + IC_EVEX_L_W_KZ, /* 6984 */ + IC_EVEX_L_W_KZ, /* 6985 */ + IC_EVEX_L_W_XS_KZ, /* 6986 */ + IC_EVEX_L_W_XS_KZ, /* 6987 */ + IC_EVEX_L_W_XD_KZ, /* 6988 */ + IC_EVEX_L_W_XD_KZ, /* 6989 */ + IC_EVEX_L_W_XD_KZ, /* 6990 */ + IC_EVEX_L_W_XD_KZ, /* 6991 */ + IC_EVEX_L_OPSIZE_KZ, /* 6992 */ + IC_EVEX_L_OPSIZE_KZ, /* 6993 */ + IC_EVEX_L_OPSIZE_KZ, /* 6994 */ + IC_EVEX_L_OPSIZE_KZ, /* 6995 */ + IC_EVEX_L_OPSIZE_KZ, /* 6996 */ + IC_EVEX_L_OPSIZE_KZ, /* 6997 */ + IC_EVEX_L_OPSIZE_KZ, /* 6998 */ + IC_EVEX_L_OPSIZE_KZ, /* 6999 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7000 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7001 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7002 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7003 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7004 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7005 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7006 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7007 */ + IC_EVEX_L_KZ, /* 7008 */ + IC_EVEX_L_KZ, /* 7009 */ + IC_EVEX_L_XS_KZ, /* 7010 */ + IC_EVEX_L_XS_KZ, /* 7011 */ + IC_EVEX_L_XD_KZ, /* 7012 */ + IC_EVEX_L_XD_KZ, /* 7013 */ + IC_EVEX_L_XD_KZ, /* 7014 */ + IC_EVEX_L_XD_KZ, /* 7015 */ + IC_EVEX_L_W_KZ, /* 7016 */ + IC_EVEX_L_W_KZ, /* 7017 */ + IC_EVEX_L_W_XS_KZ, /* 7018 */ + IC_EVEX_L_W_XS_KZ, /* 7019 */ + IC_EVEX_L_W_XD_KZ, /* 7020 */ + IC_EVEX_L_W_XD_KZ, /* 7021 */ + IC_EVEX_L_W_XD_KZ, /* 7022 */ + IC_EVEX_L_W_XD_KZ, /* 7023 */ + IC_EVEX_L_OPSIZE_KZ, /* 7024 */ + IC_EVEX_L_OPSIZE_KZ, /* 7025 */ + IC_EVEX_L_OPSIZE_KZ, /* 7026 */ + IC_EVEX_L_OPSIZE_KZ, /* 7027 */ + IC_EVEX_L_OPSIZE_KZ, /* 7028 */ + IC_EVEX_L_OPSIZE_KZ, /* 7029 */ + IC_EVEX_L_OPSIZE_KZ, /* 7030 */ + IC_EVEX_L_OPSIZE_KZ, /* 7031 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7032 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7033 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7034 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7035 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7036 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7037 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7038 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7039 */ + IC_EVEX_L_KZ, /* 7040 */ + IC_EVEX_L_KZ, /* 7041 */ + IC_EVEX_L_XS_KZ, /* 7042 */ + IC_EVEX_L_XS_KZ, /* 7043 */ + IC_EVEX_L_XD_KZ, /* 7044 */ + IC_EVEX_L_XD_KZ, /* 7045 */ + IC_EVEX_L_XD_KZ, /* 7046 */ + IC_EVEX_L_XD_KZ, /* 7047 */ + IC_EVEX_L_W_KZ, /* 7048 */ + IC_EVEX_L_W_KZ, /* 7049 */ + IC_EVEX_L_W_XS_KZ, /* 7050 */ + IC_EVEX_L_W_XS_KZ, /* 7051 */ + IC_EVEX_L_W_XD_KZ, /* 7052 */ + IC_EVEX_L_W_XD_KZ, /* 7053 */ + IC_EVEX_L_W_XD_KZ, /* 7054 */ + IC_EVEX_L_W_XD_KZ, /* 7055 */ + IC_EVEX_L_OPSIZE_KZ, /* 7056 */ + IC_EVEX_L_OPSIZE_KZ, /* 7057 */ + IC_EVEX_L_OPSIZE_KZ, /* 7058 */ + IC_EVEX_L_OPSIZE_KZ, /* 7059 */ + IC_EVEX_L_OPSIZE_KZ, /* 7060 */ + IC_EVEX_L_OPSIZE_KZ, /* 7061 */ + IC_EVEX_L_OPSIZE_KZ, /* 7062 */ + IC_EVEX_L_OPSIZE_KZ, /* 7063 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7064 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7065 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7066 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7067 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7068 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7069 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7070 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7071 */ + IC_EVEX_L_KZ, /* 7072 */ + IC_EVEX_L_KZ, /* 7073 */ + IC_EVEX_L_XS_KZ, /* 7074 */ + IC_EVEX_L_XS_KZ, /* 7075 */ + IC_EVEX_L_XD_KZ, /* 7076 */ + IC_EVEX_L_XD_KZ, /* 7077 */ + IC_EVEX_L_XD_KZ, /* 7078 */ + IC_EVEX_L_XD_KZ, /* 7079 */ + IC_EVEX_L_W_KZ, /* 7080 */ + IC_EVEX_L_W_KZ, /* 7081 */ + IC_EVEX_L_W_XS_KZ, /* 7082 */ + IC_EVEX_L_W_XS_KZ, /* 7083 */ + IC_EVEX_L_W_XD_KZ, /* 7084 */ + IC_EVEX_L_W_XD_KZ, /* 7085 */ + IC_EVEX_L_W_XD_KZ, /* 7086 */ + IC_EVEX_L_W_XD_KZ, /* 7087 */ + IC_EVEX_L_OPSIZE_KZ, /* 7088 */ + IC_EVEX_L_OPSIZE_KZ, /* 7089 */ + IC_EVEX_L_OPSIZE_KZ, /* 7090 */ + IC_EVEX_L_OPSIZE_KZ, /* 7091 */ + IC_EVEX_L_OPSIZE_KZ, /* 7092 */ + IC_EVEX_L_OPSIZE_KZ, /* 7093 */ + IC_EVEX_L_OPSIZE_KZ, /* 7094 */ + IC_EVEX_L_OPSIZE_KZ, /* 7095 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7096 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7097 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7098 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7099 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7100 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7101 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7102 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7103 */ + IC_EVEX_L_KZ, /* 7104 */ + IC_EVEX_L_KZ, /* 7105 */ + IC_EVEX_L_XS_KZ, /* 7106 */ + IC_EVEX_L_XS_KZ, /* 7107 */ + IC_EVEX_L_XD_KZ, /* 7108 */ + IC_EVEX_L_XD_KZ, /* 7109 */ + IC_EVEX_L_XD_KZ, /* 7110 */ + IC_EVEX_L_XD_KZ, /* 7111 */ + IC_EVEX_L_W_KZ, /* 7112 */ + IC_EVEX_L_W_KZ, /* 7113 */ + IC_EVEX_L_W_XS_KZ, /* 7114 */ + IC_EVEX_L_W_XS_KZ, /* 7115 */ + IC_EVEX_L_W_XD_KZ, /* 7116 */ + IC_EVEX_L_W_XD_KZ, /* 7117 */ + IC_EVEX_L_W_XD_KZ, /* 7118 */ + IC_EVEX_L_W_XD_KZ, /* 7119 */ + IC_EVEX_L_OPSIZE_KZ, /* 7120 */ + IC_EVEX_L_OPSIZE_KZ, /* 7121 */ + IC_EVEX_L_OPSIZE_KZ, /* 7122 */ + IC_EVEX_L_OPSIZE_KZ, /* 7123 */ + IC_EVEX_L_OPSIZE_KZ, /* 7124 */ + IC_EVEX_L_OPSIZE_KZ, /* 7125 */ + IC_EVEX_L_OPSIZE_KZ, /* 7126 */ + IC_EVEX_L_OPSIZE_KZ, /* 7127 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7128 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7129 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7130 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7131 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7132 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7133 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7134 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7135 */ + IC_EVEX_L_KZ, /* 7136 */ + IC_EVEX_L_KZ, /* 7137 */ + IC_EVEX_L_XS_KZ, /* 7138 */ + IC_EVEX_L_XS_KZ, /* 7139 */ + IC_EVEX_L_XD_KZ, /* 7140 */ + IC_EVEX_L_XD_KZ, /* 7141 */ + IC_EVEX_L_XD_KZ, /* 7142 */ + IC_EVEX_L_XD_KZ, /* 7143 */ + IC_EVEX_L_W_KZ, /* 7144 */ + IC_EVEX_L_W_KZ, /* 7145 */ + IC_EVEX_L_W_XS_KZ, /* 7146 */ + IC_EVEX_L_W_XS_KZ, /* 7147 */ + IC_EVEX_L_W_XD_KZ, /* 7148 */ + IC_EVEX_L_W_XD_KZ, /* 7149 */ + IC_EVEX_L_W_XD_KZ, /* 7150 */ + IC_EVEX_L_W_XD_KZ, /* 7151 */ + IC_EVEX_L_OPSIZE_KZ, /* 7152 */ + IC_EVEX_L_OPSIZE_KZ, /* 7153 */ + IC_EVEX_L_OPSIZE_KZ, /* 7154 */ + IC_EVEX_L_OPSIZE_KZ, /* 7155 */ + IC_EVEX_L_OPSIZE_KZ, /* 7156 */ + IC_EVEX_L_OPSIZE_KZ, /* 7157 */ + IC_EVEX_L_OPSIZE_KZ, /* 7158 */ + IC_EVEX_L_OPSIZE_KZ, /* 7159 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7160 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7161 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7162 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7163 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7164 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7165 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7166 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7167 */ + IC, /* 7168 */ + IC_64BIT, /* 7169 */ + IC_XS, /* 7170 */ + IC_64BIT_XS, /* 7171 */ + IC_XD, /* 7172 */ + IC_64BIT_XD, /* 7173 */ + IC_XS, /* 7174 */ + IC_64BIT_XS, /* 7175 */ + IC, /* 7176 */ + IC_64BIT_REXW, /* 7177 */ + IC_XS, /* 7178 */ + IC_64BIT_REXW_XS, /* 7179 */ + IC_XD, /* 7180 */ + IC_64BIT_REXW_XD, /* 7181 */ + IC_XS, /* 7182 */ + IC_64BIT_REXW_XS, /* 7183 */ + IC_OPSIZE, /* 7184 */ + IC_64BIT_OPSIZE, /* 7185 */ + IC_XS_OPSIZE, /* 7186 */ + IC_64BIT_XS_OPSIZE, /* 7187 */ + IC_XD_OPSIZE, /* 7188 */ + IC_64BIT_XD_OPSIZE, /* 7189 */ + IC_XS_OPSIZE, /* 7190 */ + IC_64BIT_XD_OPSIZE, /* 7191 */ + IC_OPSIZE, /* 7192 */ + IC_64BIT_REXW_OPSIZE, /* 7193 */ + IC_XS_OPSIZE, /* 7194 */ + IC_64BIT_REXW_XS, /* 7195 */ + IC_XD_OPSIZE, /* 7196 */ + IC_64BIT_REXW_XD, /* 7197 */ + IC_XS_OPSIZE, /* 7198 */ + IC_64BIT_REXW_XS, /* 7199 */ + IC_ADSIZE, /* 7200 */ + IC_64BIT_ADSIZE, /* 7201 */ + IC_XS_ADSIZE, /* 7202 */ + IC_64BIT_XS_ADSIZE, /* 7203 */ + IC_XD_ADSIZE, /* 7204 */ + IC_64BIT_XD_ADSIZE, /* 7205 */ + IC_XS_ADSIZE, /* 7206 */ + IC_64BIT_XD_ADSIZE, /* 7207 */ + IC_ADSIZE, /* 7208 */ + IC_64BIT_REXW_ADSIZE, /* 7209 */ + IC_XS_ADSIZE, /* 7210 */ + IC_64BIT_REXW_XS, /* 7211 */ + IC_XD_ADSIZE, /* 7212 */ + IC_64BIT_REXW_XD, /* 7213 */ + IC_XS_ADSIZE, /* 7214 */ + IC_64BIT_REXW_XS, /* 7215 */ + IC_OPSIZE_ADSIZE, /* 7216 */ + IC_64BIT_OPSIZE_ADSIZE, /* 7217 */ + IC_XS_OPSIZE, /* 7218 */ + IC_64BIT_XS_OPSIZE, /* 7219 */ + IC_XD_OPSIZE, /* 7220 */ + IC_64BIT_XD_OPSIZE, /* 7221 */ + IC_XS_OPSIZE, /* 7222 */ + IC_64BIT_XD_OPSIZE, /* 7223 */ + IC_OPSIZE_ADSIZE, /* 7224 */ + IC_64BIT_REXW_OPSIZE, /* 7225 */ + IC_XS_OPSIZE, /* 7226 */ + IC_64BIT_REXW_XS, /* 7227 */ + IC_XD_OPSIZE, /* 7228 */ + IC_64BIT_REXW_XD, /* 7229 */ + IC_XS_OPSIZE, /* 7230 */ + IC_64BIT_REXW_XS, /* 7231 */ + IC_VEX, /* 7232 */ + IC_VEX, /* 7233 */ + IC_VEX_XS, /* 7234 */ + IC_VEX_XS, /* 7235 */ + IC_VEX_XD, /* 7236 */ + IC_VEX_XD, /* 7237 */ + IC_VEX_XD, /* 7238 */ + IC_VEX_XD, /* 7239 */ + IC_VEX_W, /* 7240 */ + IC_VEX_W, /* 7241 */ + IC_VEX_W_XS, /* 7242 */ + IC_VEX_W_XS, /* 7243 */ + IC_VEX_W_XD, /* 7244 */ + IC_VEX_W_XD, /* 7245 */ + IC_VEX_W_XD, /* 7246 */ + IC_VEX_W_XD, /* 7247 */ + IC_VEX_OPSIZE, /* 7248 */ + IC_VEX_OPSIZE, /* 7249 */ + IC_VEX_OPSIZE, /* 7250 */ + IC_VEX_OPSIZE, /* 7251 */ + IC_VEX_OPSIZE, /* 7252 */ + IC_VEX_OPSIZE, /* 7253 */ + IC_VEX_OPSIZE, /* 7254 */ + IC_VEX_OPSIZE, /* 7255 */ + IC_VEX_W_OPSIZE, /* 7256 */ + IC_VEX_W_OPSIZE, /* 7257 */ + IC_VEX_W_OPSIZE, /* 7258 */ + IC_VEX_W_OPSIZE, /* 7259 */ + IC_VEX_W_OPSIZE, /* 7260 */ + IC_VEX_W_OPSIZE, /* 7261 */ + IC_VEX_W_OPSIZE, /* 7262 */ + IC_VEX_W_OPSIZE, /* 7263 */ + IC_VEX, /* 7264 */ + IC_VEX, /* 7265 */ + IC_VEX_XS, /* 7266 */ + IC_VEX_XS, /* 7267 */ + IC_VEX_XD, /* 7268 */ + IC_VEX_XD, /* 7269 */ + IC_VEX_XD, /* 7270 */ + IC_VEX_XD, /* 7271 */ + IC_VEX_W, /* 7272 */ + IC_VEX_W, /* 7273 */ + IC_VEX_W_XS, /* 7274 */ + IC_VEX_W_XS, /* 7275 */ + IC_VEX_W_XD, /* 7276 */ + IC_VEX_W_XD, /* 7277 */ + IC_VEX_W_XD, /* 7278 */ + IC_VEX_W_XD, /* 7279 */ + IC_VEX_OPSIZE, /* 7280 */ + IC_VEX_OPSIZE, /* 7281 */ + IC_VEX_OPSIZE, /* 7282 */ + IC_VEX_OPSIZE, /* 7283 */ + IC_VEX_OPSIZE, /* 7284 */ + IC_VEX_OPSIZE, /* 7285 */ + IC_VEX_OPSIZE, /* 7286 */ + IC_VEX_OPSIZE, /* 7287 */ + IC_VEX_W_OPSIZE, /* 7288 */ + IC_VEX_W_OPSIZE, /* 7289 */ + IC_VEX_W_OPSIZE, /* 7290 */ + IC_VEX_W_OPSIZE, /* 7291 */ + IC_VEX_W_OPSIZE, /* 7292 */ + IC_VEX_W_OPSIZE, /* 7293 */ + IC_VEX_W_OPSIZE, /* 7294 */ + IC_VEX_W_OPSIZE, /* 7295 */ + IC_VEX_L, /* 7296 */ + IC_VEX_L, /* 7297 */ + IC_VEX_L_XS, /* 7298 */ + IC_VEX_L_XS, /* 7299 */ + IC_VEX_L_XD, /* 7300 */ + IC_VEX_L_XD, /* 7301 */ + IC_VEX_L_XD, /* 7302 */ + IC_VEX_L_XD, /* 7303 */ + IC_VEX_L_W, /* 7304 */ + IC_VEX_L_W, /* 7305 */ + IC_VEX_L_W_XS, /* 7306 */ + IC_VEX_L_W_XS, /* 7307 */ + IC_VEX_L_W_XD, /* 7308 */ + IC_VEX_L_W_XD, /* 7309 */ + IC_VEX_L_W_XD, /* 7310 */ + IC_VEX_L_W_XD, /* 7311 */ + IC_VEX_L_OPSIZE, /* 7312 */ + IC_VEX_L_OPSIZE, /* 7313 */ + IC_VEX_L_OPSIZE, /* 7314 */ + IC_VEX_L_OPSIZE, /* 7315 */ + IC_VEX_L_OPSIZE, /* 7316 */ + IC_VEX_L_OPSIZE, /* 7317 */ + IC_VEX_L_OPSIZE, /* 7318 */ + IC_VEX_L_OPSIZE, /* 7319 */ + IC_VEX_L_W_OPSIZE, /* 7320 */ + IC_VEX_L_W_OPSIZE, /* 7321 */ + IC_VEX_L_W_OPSIZE, /* 7322 */ + IC_VEX_L_W_OPSIZE, /* 7323 */ + IC_VEX_L_W_OPSIZE, /* 7324 */ + IC_VEX_L_W_OPSIZE, /* 7325 */ + IC_VEX_L_W_OPSIZE, /* 7326 */ + IC_VEX_L_W_OPSIZE, /* 7327 */ + IC_VEX_L, /* 7328 */ + IC_VEX_L, /* 7329 */ + IC_VEX_L_XS, /* 7330 */ + IC_VEX_L_XS, /* 7331 */ + IC_VEX_L_XD, /* 7332 */ + IC_VEX_L_XD, /* 7333 */ + IC_VEX_L_XD, /* 7334 */ + IC_VEX_L_XD, /* 7335 */ + IC_VEX_L_W, /* 7336 */ + IC_VEX_L_W, /* 7337 */ + IC_VEX_L_W_XS, /* 7338 */ + IC_VEX_L_W_XS, /* 7339 */ + IC_VEX_L_W_XD, /* 7340 */ + IC_VEX_L_W_XD, /* 7341 */ + IC_VEX_L_W_XD, /* 7342 */ + IC_VEX_L_W_XD, /* 7343 */ + IC_VEX_L_OPSIZE, /* 7344 */ + IC_VEX_L_OPSIZE, /* 7345 */ + IC_VEX_L_OPSIZE, /* 7346 */ + IC_VEX_L_OPSIZE, /* 7347 */ + IC_VEX_L_OPSIZE, /* 7348 */ + IC_VEX_L_OPSIZE, /* 7349 */ + IC_VEX_L_OPSIZE, /* 7350 */ + IC_VEX_L_OPSIZE, /* 7351 */ + IC_VEX_L_W_OPSIZE, /* 7352 */ + IC_VEX_L_W_OPSIZE, /* 7353 */ + IC_VEX_L_W_OPSIZE, /* 7354 */ + IC_VEX_L_W_OPSIZE, /* 7355 */ + IC_VEX_L_W_OPSIZE, /* 7356 */ + IC_VEX_L_W_OPSIZE, /* 7357 */ + IC_VEX_L_W_OPSIZE, /* 7358 */ + IC_VEX_L_W_OPSIZE, /* 7359 */ + IC_VEX_L, /* 7360 */ + IC_VEX_L, /* 7361 */ + IC_VEX_L_XS, /* 7362 */ + IC_VEX_L_XS, /* 7363 */ + IC_VEX_L_XD, /* 7364 */ + IC_VEX_L_XD, /* 7365 */ + IC_VEX_L_XD, /* 7366 */ + IC_VEX_L_XD, /* 7367 */ + IC_VEX_L_W, /* 7368 */ + IC_VEX_L_W, /* 7369 */ + IC_VEX_L_W_XS, /* 7370 */ + IC_VEX_L_W_XS, /* 7371 */ + IC_VEX_L_W_XD, /* 7372 */ + IC_VEX_L_W_XD, /* 7373 */ + IC_VEX_L_W_XD, /* 7374 */ + IC_VEX_L_W_XD, /* 7375 */ + IC_VEX_L_OPSIZE, /* 7376 */ + IC_VEX_L_OPSIZE, /* 7377 */ + IC_VEX_L_OPSIZE, /* 7378 */ + IC_VEX_L_OPSIZE, /* 7379 */ + IC_VEX_L_OPSIZE, /* 7380 */ + IC_VEX_L_OPSIZE, /* 7381 */ + IC_VEX_L_OPSIZE, /* 7382 */ + IC_VEX_L_OPSIZE, /* 7383 */ + IC_VEX_L_W_OPSIZE, /* 7384 */ + IC_VEX_L_W_OPSIZE, /* 7385 */ + IC_VEX_L_W_OPSIZE, /* 7386 */ + IC_VEX_L_W_OPSIZE, /* 7387 */ + IC_VEX_L_W_OPSIZE, /* 7388 */ + IC_VEX_L_W_OPSIZE, /* 7389 */ + IC_VEX_L_W_OPSIZE, /* 7390 */ + IC_VEX_L_W_OPSIZE, /* 7391 */ + IC_VEX_L, /* 7392 */ + IC_VEX_L, /* 7393 */ + IC_VEX_L_XS, /* 7394 */ + IC_VEX_L_XS, /* 7395 */ + IC_VEX_L_XD, /* 7396 */ + IC_VEX_L_XD, /* 7397 */ + IC_VEX_L_XD, /* 7398 */ + IC_VEX_L_XD, /* 7399 */ + IC_VEX_L_W, /* 7400 */ + IC_VEX_L_W, /* 7401 */ + IC_VEX_L_W_XS, /* 7402 */ + IC_VEX_L_W_XS, /* 7403 */ + IC_VEX_L_W_XD, /* 7404 */ + IC_VEX_L_W_XD, /* 7405 */ + IC_VEX_L_W_XD, /* 7406 */ + IC_VEX_L_W_XD, /* 7407 */ + IC_VEX_L_OPSIZE, /* 7408 */ + IC_VEX_L_OPSIZE, /* 7409 */ + IC_VEX_L_OPSIZE, /* 7410 */ + IC_VEX_L_OPSIZE, /* 7411 */ + IC_VEX_L_OPSIZE, /* 7412 */ + IC_VEX_L_OPSIZE, /* 7413 */ + IC_VEX_L_OPSIZE, /* 7414 */ + IC_VEX_L_OPSIZE, /* 7415 */ + IC_VEX_L_W_OPSIZE, /* 7416 */ + IC_VEX_L_W_OPSIZE, /* 7417 */ + IC_VEX_L_W_OPSIZE, /* 7418 */ + IC_VEX_L_W_OPSIZE, /* 7419 */ + IC_VEX_L_W_OPSIZE, /* 7420 */ + IC_VEX_L_W_OPSIZE, /* 7421 */ + IC_VEX_L_W_OPSIZE, /* 7422 */ + IC_VEX_L_W_OPSIZE, /* 7423 */ + IC_EVEX_L2_KZ, /* 7424 */ + IC_EVEX_L2_KZ, /* 7425 */ + IC_EVEX_L2_XS_KZ, /* 7426 */ + IC_EVEX_L2_XS_KZ, /* 7427 */ + IC_EVEX_L2_XD_KZ, /* 7428 */ + IC_EVEX_L2_XD_KZ, /* 7429 */ + IC_EVEX_L2_XD_KZ, /* 7430 */ + IC_EVEX_L2_XD_KZ, /* 7431 */ + IC_EVEX_L2_W_KZ, /* 7432 */ + IC_EVEX_L2_W_KZ, /* 7433 */ + IC_EVEX_L2_W_XS_KZ, /* 7434 */ + IC_EVEX_L2_W_XS_KZ, /* 7435 */ + IC_EVEX_L2_W_XD_KZ, /* 7436 */ + IC_EVEX_L2_W_XD_KZ, /* 7437 */ + IC_EVEX_L2_W_XD_KZ, /* 7438 */ + IC_EVEX_L2_W_XD_KZ, /* 7439 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7440 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7441 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7442 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7443 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7444 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7445 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7446 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7447 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7448 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7449 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7450 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7451 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7452 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7453 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7454 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7455 */ + IC_EVEX_L2_KZ, /* 7456 */ + IC_EVEX_L2_KZ, /* 7457 */ + IC_EVEX_L2_XS_KZ, /* 7458 */ + IC_EVEX_L2_XS_KZ, /* 7459 */ + IC_EVEX_L2_XD_KZ, /* 7460 */ + IC_EVEX_L2_XD_KZ, /* 7461 */ + IC_EVEX_L2_XD_KZ, /* 7462 */ + IC_EVEX_L2_XD_KZ, /* 7463 */ + IC_EVEX_L2_W_KZ, /* 7464 */ + IC_EVEX_L2_W_KZ, /* 7465 */ + IC_EVEX_L2_W_XS_KZ, /* 7466 */ + IC_EVEX_L2_W_XS_KZ, /* 7467 */ + IC_EVEX_L2_W_XD_KZ, /* 7468 */ + IC_EVEX_L2_W_XD_KZ, /* 7469 */ + IC_EVEX_L2_W_XD_KZ, /* 7470 */ + IC_EVEX_L2_W_XD_KZ, /* 7471 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7472 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7473 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7474 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7475 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7476 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7477 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7478 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7479 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7480 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7481 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7482 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7483 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7484 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7485 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7486 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7487 */ + IC_EVEX_L2_KZ, /* 7488 */ + IC_EVEX_L2_KZ, /* 7489 */ + IC_EVEX_L2_XS_KZ, /* 7490 */ + IC_EVEX_L2_XS_KZ, /* 7491 */ + IC_EVEX_L2_XD_KZ, /* 7492 */ + IC_EVEX_L2_XD_KZ, /* 7493 */ + IC_EVEX_L2_XD_KZ, /* 7494 */ + IC_EVEX_L2_XD_KZ, /* 7495 */ + IC_EVEX_L2_W_KZ, /* 7496 */ + IC_EVEX_L2_W_KZ, /* 7497 */ + IC_EVEX_L2_W_XS_KZ, /* 7498 */ + IC_EVEX_L2_W_XS_KZ, /* 7499 */ + IC_EVEX_L2_W_XD_KZ, /* 7500 */ + IC_EVEX_L2_W_XD_KZ, /* 7501 */ + IC_EVEX_L2_W_XD_KZ, /* 7502 */ + IC_EVEX_L2_W_XD_KZ, /* 7503 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7504 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7505 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7506 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7507 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7508 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7509 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7510 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7511 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7512 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7513 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7514 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7515 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7516 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7517 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7518 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7519 */ + IC_EVEX_L2_KZ, /* 7520 */ + IC_EVEX_L2_KZ, /* 7521 */ + IC_EVEX_L2_XS_KZ, /* 7522 */ + IC_EVEX_L2_XS_KZ, /* 7523 */ + IC_EVEX_L2_XD_KZ, /* 7524 */ + IC_EVEX_L2_XD_KZ, /* 7525 */ + IC_EVEX_L2_XD_KZ, /* 7526 */ + IC_EVEX_L2_XD_KZ, /* 7527 */ + IC_EVEX_L2_W_KZ, /* 7528 */ + IC_EVEX_L2_W_KZ, /* 7529 */ + IC_EVEX_L2_W_XS_KZ, /* 7530 */ + IC_EVEX_L2_W_XS_KZ, /* 7531 */ + IC_EVEX_L2_W_XD_KZ, /* 7532 */ + IC_EVEX_L2_W_XD_KZ, /* 7533 */ + IC_EVEX_L2_W_XD_KZ, /* 7534 */ + IC_EVEX_L2_W_XD_KZ, /* 7535 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7536 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7537 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7538 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7539 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7540 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7541 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7542 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7543 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7544 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7545 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7546 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7547 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7548 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7549 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7550 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7551 */ + IC_EVEX_L2_KZ, /* 7552 */ + IC_EVEX_L2_KZ, /* 7553 */ + IC_EVEX_L2_XS_KZ, /* 7554 */ + IC_EVEX_L2_XS_KZ, /* 7555 */ + IC_EVEX_L2_XD_KZ, /* 7556 */ + IC_EVEX_L2_XD_KZ, /* 7557 */ + IC_EVEX_L2_XD_KZ, /* 7558 */ + IC_EVEX_L2_XD_KZ, /* 7559 */ + IC_EVEX_L2_W_KZ, /* 7560 */ + IC_EVEX_L2_W_KZ, /* 7561 */ + IC_EVEX_L2_W_XS_KZ, /* 7562 */ + IC_EVEX_L2_W_XS_KZ, /* 7563 */ + IC_EVEX_L2_W_XD_KZ, /* 7564 */ + IC_EVEX_L2_W_XD_KZ, /* 7565 */ + IC_EVEX_L2_W_XD_KZ, /* 7566 */ + IC_EVEX_L2_W_XD_KZ, /* 7567 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7568 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7569 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7570 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7571 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7572 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7573 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7574 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7575 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7576 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7577 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7578 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7579 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7580 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7581 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7582 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7583 */ + IC_EVEX_L2_KZ, /* 7584 */ + IC_EVEX_L2_KZ, /* 7585 */ + IC_EVEX_L2_XS_KZ, /* 7586 */ + IC_EVEX_L2_XS_KZ, /* 7587 */ + IC_EVEX_L2_XD_KZ, /* 7588 */ + IC_EVEX_L2_XD_KZ, /* 7589 */ + IC_EVEX_L2_XD_KZ, /* 7590 */ + IC_EVEX_L2_XD_KZ, /* 7591 */ + IC_EVEX_L2_W_KZ, /* 7592 */ + IC_EVEX_L2_W_KZ, /* 7593 */ + IC_EVEX_L2_W_XS_KZ, /* 7594 */ + IC_EVEX_L2_W_XS_KZ, /* 7595 */ + IC_EVEX_L2_W_XD_KZ, /* 7596 */ + IC_EVEX_L2_W_XD_KZ, /* 7597 */ + IC_EVEX_L2_W_XD_KZ, /* 7598 */ + IC_EVEX_L2_W_XD_KZ, /* 7599 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7600 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7601 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7602 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7603 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7604 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7605 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7606 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7607 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7608 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7609 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7610 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7611 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7612 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7613 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7614 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7615 */ + IC_EVEX_L2_KZ, /* 7616 */ + IC_EVEX_L2_KZ, /* 7617 */ + IC_EVEX_L2_XS_KZ, /* 7618 */ + IC_EVEX_L2_XS_KZ, /* 7619 */ + IC_EVEX_L2_XD_KZ, /* 7620 */ + IC_EVEX_L2_XD_KZ, /* 7621 */ + IC_EVEX_L2_XD_KZ, /* 7622 */ + IC_EVEX_L2_XD_KZ, /* 7623 */ + IC_EVEX_L2_W_KZ, /* 7624 */ + IC_EVEX_L2_W_KZ, /* 7625 */ + IC_EVEX_L2_W_XS_KZ, /* 7626 */ + IC_EVEX_L2_W_XS_KZ, /* 7627 */ + IC_EVEX_L2_W_XD_KZ, /* 7628 */ + IC_EVEX_L2_W_XD_KZ, /* 7629 */ + IC_EVEX_L2_W_XD_KZ, /* 7630 */ + IC_EVEX_L2_W_XD_KZ, /* 7631 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7632 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7633 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7634 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7635 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7636 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7637 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7638 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7639 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7640 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7641 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7642 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7643 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7644 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7645 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7646 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7647 */ + IC_EVEX_L2_KZ, /* 7648 */ + IC_EVEX_L2_KZ, /* 7649 */ + IC_EVEX_L2_XS_KZ, /* 7650 */ + IC_EVEX_L2_XS_KZ, /* 7651 */ + IC_EVEX_L2_XD_KZ, /* 7652 */ + IC_EVEX_L2_XD_KZ, /* 7653 */ + IC_EVEX_L2_XD_KZ, /* 7654 */ + IC_EVEX_L2_XD_KZ, /* 7655 */ + IC_EVEX_L2_W_KZ, /* 7656 */ + IC_EVEX_L2_W_KZ, /* 7657 */ + IC_EVEX_L2_W_XS_KZ, /* 7658 */ + IC_EVEX_L2_W_XS_KZ, /* 7659 */ + IC_EVEX_L2_W_XD_KZ, /* 7660 */ + IC_EVEX_L2_W_XD_KZ, /* 7661 */ + IC_EVEX_L2_W_XD_KZ, /* 7662 */ + IC_EVEX_L2_W_XD_KZ, /* 7663 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7664 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7665 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7666 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7667 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7668 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7669 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7670 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7671 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7672 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7673 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7674 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7675 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7676 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7677 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7678 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7679 */ + IC, /* 7680 */ + IC_64BIT, /* 7681 */ + IC_XS, /* 7682 */ + IC_64BIT_XS, /* 7683 */ + IC_XD, /* 7684 */ + IC_64BIT_XD, /* 7685 */ + IC_XS, /* 7686 */ + IC_64BIT_XS, /* 7687 */ + IC, /* 7688 */ + IC_64BIT_REXW, /* 7689 */ + IC_XS, /* 7690 */ + IC_64BIT_REXW_XS, /* 7691 */ + IC_XD, /* 7692 */ + IC_64BIT_REXW_XD, /* 7693 */ + IC_XS, /* 7694 */ + IC_64BIT_REXW_XS, /* 7695 */ + IC_OPSIZE, /* 7696 */ + IC_64BIT_OPSIZE, /* 7697 */ + IC_XS_OPSIZE, /* 7698 */ + IC_64BIT_XS_OPSIZE, /* 7699 */ + IC_XD_OPSIZE, /* 7700 */ + IC_64BIT_XD_OPSIZE, /* 7701 */ + IC_XS_OPSIZE, /* 7702 */ + IC_64BIT_XD_OPSIZE, /* 7703 */ + IC_OPSIZE, /* 7704 */ + IC_64BIT_REXW_OPSIZE, /* 7705 */ + IC_XS_OPSIZE, /* 7706 */ + IC_64BIT_REXW_XS, /* 7707 */ + IC_XD_OPSIZE, /* 7708 */ + IC_64BIT_REXW_XD, /* 7709 */ + IC_XS_OPSIZE, /* 7710 */ + IC_64BIT_REXW_XS, /* 7711 */ + IC_ADSIZE, /* 7712 */ + IC_64BIT_ADSIZE, /* 7713 */ + IC_XS_ADSIZE, /* 7714 */ + IC_64BIT_XS_ADSIZE, /* 7715 */ + IC_XD_ADSIZE, /* 7716 */ + IC_64BIT_XD_ADSIZE, /* 7717 */ + IC_XS_ADSIZE, /* 7718 */ + IC_64BIT_XD_ADSIZE, /* 7719 */ + IC_ADSIZE, /* 7720 */ + IC_64BIT_REXW_ADSIZE, /* 7721 */ + IC_XS_ADSIZE, /* 7722 */ + IC_64BIT_REXW_XS, /* 7723 */ + IC_XD_ADSIZE, /* 7724 */ + IC_64BIT_REXW_XD, /* 7725 */ + IC_XS_ADSIZE, /* 7726 */ + IC_64BIT_REXW_XS, /* 7727 */ + IC_OPSIZE_ADSIZE, /* 7728 */ + IC_64BIT_OPSIZE_ADSIZE, /* 7729 */ + IC_XS_OPSIZE, /* 7730 */ + IC_64BIT_XS_OPSIZE, /* 7731 */ + IC_XD_OPSIZE, /* 7732 */ + IC_64BIT_XD_OPSIZE, /* 7733 */ + IC_XS_OPSIZE, /* 7734 */ + IC_64BIT_XD_OPSIZE, /* 7735 */ + IC_OPSIZE_ADSIZE, /* 7736 */ + IC_64BIT_REXW_OPSIZE, /* 7737 */ + IC_XS_OPSIZE, /* 7738 */ + IC_64BIT_REXW_XS, /* 7739 */ + IC_XD_OPSIZE, /* 7740 */ + IC_64BIT_REXW_XD, /* 7741 */ + IC_XS_OPSIZE, /* 7742 */ + IC_64BIT_REXW_XS, /* 7743 */ + IC_VEX, /* 7744 */ + IC_VEX, /* 7745 */ + IC_VEX_XS, /* 7746 */ + IC_VEX_XS, /* 7747 */ + IC_VEX_XD, /* 7748 */ + IC_VEX_XD, /* 7749 */ + IC_VEX_XD, /* 7750 */ + IC_VEX_XD, /* 7751 */ + IC_VEX_W, /* 7752 */ + IC_VEX_W, /* 7753 */ + IC_VEX_W_XS, /* 7754 */ + IC_VEX_W_XS, /* 7755 */ + IC_VEX_W_XD, /* 7756 */ + IC_VEX_W_XD, /* 7757 */ + IC_VEX_W_XD, /* 7758 */ + IC_VEX_W_XD, /* 7759 */ + IC_VEX_OPSIZE, /* 7760 */ + IC_VEX_OPSIZE, /* 7761 */ + IC_VEX_OPSIZE, /* 7762 */ + IC_VEX_OPSIZE, /* 7763 */ + IC_VEX_OPSIZE, /* 7764 */ + IC_VEX_OPSIZE, /* 7765 */ + IC_VEX_OPSIZE, /* 7766 */ + IC_VEX_OPSIZE, /* 7767 */ + IC_VEX_W_OPSIZE, /* 7768 */ + IC_VEX_W_OPSIZE, /* 7769 */ + IC_VEX_W_OPSIZE, /* 7770 */ + IC_VEX_W_OPSIZE, /* 7771 */ + IC_VEX_W_OPSIZE, /* 7772 */ + IC_VEX_W_OPSIZE, /* 7773 */ + IC_VEX_W_OPSIZE, /* 7774 */ + IC_VEX_W_OPSIZE, /* 7775 */ + IC_VEX, /* 7776 */ + IC_VEX, /* 7777 */ + IC_VEX_XS, /* 7778 */ + IC_VEX_XS, /* 7779 */ + IC_VEX_XD, /* 7780 */ + IC_VEX_XD, /* 7781 */ + IC_VEX_XD, /* 7782 */ + IC_VEX_XD, /* 7783 */ + IC_VEX_W, /* 7784 */ + IC_VEX_W, /* 7785 */ + IC_VEX_W_XS, /* 7786 */ + IC_VEX_W_XS, /* 7787 */ + IC_VEX_W_XD, /* 7788 */ + IC_VEX_W_XD, /* 7789 */ + IC_VEX_W_XD, /* 7790 */ + IC_VEX_W_XD, /* 7791 */ + IC_VEX_OPSIZE, /* 7792 */ + IC_VEX_OPSIZE, /* 7793 */ + IC_VEX_OPSIZE, /* 7794 */ + IC_VEX_OPSIZE, /* 7795 */ + IC_VEX_OPSIZE, /* 7796 */ + IC_VEX_OPSIZE, /* 7797 */ + IC_VEX_OPSIZE, /* 7798 */ + IC_VEX_OPSIZE, /* 7799 */ + IC_VEX_W_OPSIZE, /* 7800 */ + IC_VEX_W_OPSIZE, /* 7801 */ + IC_VEX_W_OPSIZE, /* 7802 */ + IC_VEX_W_OPSIZE, /* 7803 */ + IC_VEX_W_OPSIZE, /* 7804 */ + IC_VEX_W_OPSIZE, /* 7805 */ + IC_VEX_W_OPSIZE, /* 7806 */ + IC_VEX_W_OPSIZE, /* 7807 */ + IC_VEX_L, /* 7808 */ + IC_VEX_L, /* 7809 */ + IC_VEX_L_XS, /* 7810 */ + IC_VEX_L_XS, /* 7811 */ + IC_VEX_L_XD, /* 7812 */ + IC_VEX_L_XD, /* 7813 */ + IC_VEX_L_XD, /* 7814 */ + IC_VEX_L_XD, /* 7815 */ + IC_VEX_L_W, /* 7816 */ + IC_VEX_L_W, /* 7817 */ + IC_VEX_L_W_XS, /* 7818 */ + IC_VEX_L_W_XS, /* 7819 */ + IC_VEX_L_W_XD, /* 7820 */ + IC_VEX_L_W_XD, /* 7821 */ + IC_VEX_L_W_XD, /* 7822 */ + IC_VEX_L_W_XD, /* 7823 */ + IC_VEX_L_OPSIZE, /* 7824 */ + IC_VEX_L_OPSIZE, /* 7825 */ + IC_VEX_L_OPSIZE, /* 7826 */ + IC_VEX_L_OPSIZE, /* 7827 */ + IC_VEX_L_OPSIZE, /* 7828 */ + IC_VEX_L_OPSIZE, /* 7829 */ + IC_VEX_L_OPSIZE, /* 7830 */ + IC_VEX_L_OPSIZE, /* 7831 */ + IC_VEX_L_W_OPSIZE, /* 7832 */ + IC_VEX_L_W_OPSIZE, /* 7833 */ + IC_VEX_L_W_OPSIZE, /* 7834 */ + IC_VEX_L_W_OPSIZE, /* 7835 */ + IC_VEX_L_W_OPSIZE, /* 7836 */ + IC_VEX_L_W_OPSIZE, /* 7837 */ + IC_VEX_L_W_OPSIZE, /* 7838 */ + IC_VEX_L_W_OPSIZE, /* 7839 */ + IC_VEX_L, /* 7840 */ + IC_VEX_L, /* 7841 */ + IC_VEX_L_XS, /* 7842 */ + IC_VEX_L_XS, /* 7843 */ + IC_VEX_L_XD, /* 7844 */ + IC_VEX_L_XD, /* 7845 */ + IC_VEX_L_XD, /* 7846 */ + IC_VEX_L_XD, /* 7847 */ + IC_VEX_L_W, /* 7848 */ + IC_VEX_L_W, /* 7849 */ + IC_VEX_L_W_XS, /* 7850 */ + IC_VEX_L_W_XS, /* 7851 */ + IC_VEX_L_W_XD, /* 7852 */ + IC_VEX_L_W_XD, /* 7853 */ + IC_VEX_L_W_XD, /* 7854 */ + IC_VEX_L_W_XD, /* 7855 */ + IC_VEX_L_OPSIZE, /* 7856 */ + IC_VEX_L_OPSIZE, /* 7857 */ + IC_VEX_L_OPSIZE, /* 7858 */ + IC_VEX_L_OPSIZE, /* 7859 */ + IC_VEX_L_OPSIZE, /* 7860 */ + IC_VEX_L_OPSIZE, /* 7861 */ + IC_VEX_L_OPSIZE, /* 7862 */ + IC_VEX_L_OPSIZE, /* 7863 */ + IC_VEX_L_W_OPSIZE, /* 7864 */ + IC_VEX_L_W_OPSIZE, /* 7865 */ + IC_VEX_L_W_OPSIZE, /* 7866 */ + IC_VEX_L_W_OPSIZE, /* 7867 */ + IC_VEX_L_W_OPSIZE, /* 7868 */ + IC_VEX_L_W_OPSIZE, /* 7869 */ + IC_VEX_L_W_OPSIZE, /* 7870 */ + IC_VEX_L_W_OPSIZE, /* 7871 */ + IC_VEX_L, /* 7872 */ + IC_VEX_L, /* 7873 */ + IC_VEX_L_XS, /* 7874 */ + IC_VEX_L_XS, /* 7875 */ + IC_VEX_L_XD, /* 7876 */ + IC_VEX_L_XD, /* 7877 */ + IC_VEX_L_XD, /* 7878 */ + IC_VEX_L_XD, /* 7879 */ + IC_VEX_L_W, /* 7880 */ + IC_VEX_L_W, /* 7881 */ + IC_VEX_L_W_XS, /* 7882 */ + IC_VEX_L_W_XS, /* 7883 */ + IC_VEX_L_W_XD, /* 7884 */ + IC_VEX_L_W_XD, /* 7885 */ + IC_VEX_L_W_XD, /* 7886 */ + IC_VEX_L_W_XD, /* 7887 */ + IC_VEX_L_OPSIZE, /* 7888 */ + IC_VEX_L_OPSIZE, /* 7889 */ + IC_VEX_L_OPSIZE, /* 7890 */ + IC_VEX_L_OPSIZE, /* 7891 */ + IC_VEX_L_OPSIZE, /* 7892 */ + IC_VEX_L_OPSIZE, /* 7893 */ + IC_VEX_L_OPSIZE, /* 7894 */ + IC_VEX_L_OPSIZE, /* 7895 */ + IC_VEX_L_W_OPSIZE, /* 7896 */ + IC_VEX_L_W_OPSIZE, /* 7897 */ + IC_VEX_L_W_OPSIZE, /* 7898 */ + IC_VEX_L_W_OPSIZE, /* 7899 */ + IC_VEX_L_W_OPSIZE, /* 7900 */ + IC_VEX_L_W_OPSIZE, /* 7901 */ + IC_VEX_L_W_OPSIZE, /* 7902 */ + IC_VEX_L_W_OPSIZE, /* 7903 */ + IC_VEX_L, /* 7904 */ + IC_VEX_L, /* 7905 */ + IC_VEX_L_XS, /* 7906 */ + IC_VEX_L_XS, /* 7907 */ + IC_VEX_L_XD, /* 7908 */ + IC_VEX_L_XD, /* 7909 */ + IC_VEX_L_XD, /* 7910 */ + IC_VEX_L_XD, /* 7911 */ + IC_VEX_L_W, /* 7912 */ + IC_VEX_L_W, /* 7913 */ + IC_VEX_L_W_XS, /* 7914 */ + IC_VEX_L_W_XS, /* 7915 */ + IC_VEX_L_W_XD, /* 7916 */ + IC_VEX_L_W_XD, /* 7917 */ + IC_VEX_L_W_XD, /* 7918 */ + IC_VEX_L_W_XD, /* 7919 */ + IC_VEX_L_OPSIZE, /* 7920 */ + IC_VEX_L_OPSIZE, /* 7921 */ + IC_VEX_L_OPSIZE, /* 7922 */ + IC_VEX_L_OPSIZE, /* 7923 */ + IC_VEX_L_OPSIZE, /* 7924 */ + IC_VEX_L_OPSIZE, /* 7925 */ + IC_VEX_L_OPSIZE, /* 7926 */ + IC_VEX_L_OPSIZE, /* 7927 */ + IC_VEX_L_W_OPSIZE, /* 7928 */ + IC_VEX_L_W_OPSIZE, /* 7929 */ + IC_VEX_L_W_OPSIZE, /* 7930 */ + IC_VEX_L_W_OPSIZE, /* 7931 */ + IC_VEX_L_W_OPSIZE, /* 7932 */ + IC_VEX_L_W_OPSIZE, /* 7933 */ + IC_VEX_L_W_OPSIZE, /* 7934 */ + IC_VEX_L_W_OPSIZE, /* 7935 */ + IC_EVEX_L2_KZ, /* 7936 */ + IC_EVEX_L2_KZ, /* 7937 */ + IC_EVEX_L2_XS_KZ, /* 7938 */ + IC_EVEX_L2_XS_KZ, /* 7939 */ + IC_EVEX_L2_XD_KZ, /* 7940 */ + IC_EVEX_L2_XD_KZ, /* 7941 */ + IC_EVEX_L2_XD_KZ, /* 7942 */ + IC_EVEX_L2_XD_KZ, /* 7943 */ + IC_EVEX_L2_W_KZ, /* 7944 */ + IC_EVEX_L2_W_KZ, /* 7945 */ + IC_EVEX_L2_W_XS_KZ, /* 7946 */ + IC_EVEX_L2_W_XS_KZ, /* 7947 */ + IC_EVEX_L2_W_XD_KZ, /* 7948 */ + IC_EVEX_L2_W_XD_KZ, /* 7949 */ + IC_EVEX_L2_W_XD_KZ, /* 7950 */ + IC_EVEX_L2_W_XD_KZ, /* 7951 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7952 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7953 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7954 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7955 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7956 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7957 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7958 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7959 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7960 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7961 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7962 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7963 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7964 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7965 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7966 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7967 */ + IC_EVEX_L2_KZ, /* 7968 */ + IC_EVEX_L2_KZ, /* 7969 */ + IC_EVEX_L2_XS_KZ, /* 7970 */ + IC_EVEX_L2_XS_KZ, /* 7971 */ + IC_EVEX_L2_XD_KZ, /* 7972 */ + IC_EVEX_L2_XD_KZ, /* 7973 */ + IC_EVEX_L2_XD_KZ, /* 7974 */ + IC_EVEX_L2_XD_KZ, /* 7975 */ + IC_EVEX_L2_W_KZ, /* 7976 */ + IC_EVEX_L2_W_KZ, /* 7977 */ + IC_EVEX_L2_W_XS_KZ, /* 7978 */ + IC_EVEX_L2_W_XS_KZ, /* 7979 */ + IC_EVEX_L2_W_XD_KZ, /* 7980 */ + IC_EVEX_L2_W_XD_KZ, /* 7981 */ + IC_EVEX_L2_W_XD_KZ, /* 7982 */ + IC_EVEX_L2_W_XD_KZ, /* 7983 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7984 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7985 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7986 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7987 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7988 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7989 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7990 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7991 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7992 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7993 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7994 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7995 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7996 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7997 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7998 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7999 */ + IC_EVEX_L2_KZ, /* 8000 */ + IC_EVEX_L2_KZ, /* 8001 */ + IC_EVEX_L2_XS_KZ, /* 8002 */ + IC_EVEX_L2_XS_KZ, /* 8003 */ + IC_EVEX_L2_XD_KZ, /* 8004 */ + IC_EVEX_L2_XD_KZ, /* 8005 */ + IC_EVEX_L2_XD_KZ, /* 8006 */ + IC_EVEX_L2_XD_KZ, /* 8007 */ + IC_EVEX_L2_W_KZ, /* 8008 */ + IC_EVEX_L2_W_KZ, /* 8009 */ + IC_EVEX_L2_W_XS_KZ, /* 8010 */ + IC_EVEX_L2_W_XS_KZ, /* 8011 */ + IC_EVEX_L2_W_XD_KZ, /* 8012 */ + IC_EVEX_L2_W_XD_KZ, /* 8013 */ + IC_EVEX_L2_W_XD_KZ, /* 8014 */ + IC_EVEX_L2_W_XD_KZ, /* 8015 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8016 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8017 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8018 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8019 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8020 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8021 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8022 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8023 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8024 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8025 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8026 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8027 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8028 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8029 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8030 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8031 */ + IC_EVEX_L2_KZ, /* 8032 */ + IC_EVEX_L2_KZ, /* 8033 */ + IC_EVEX_L2_XS_KZ, /* 8034 */ + IC_EVEX_L2_XS_KZ, /* 8035 */ + IC_EVEX_L2_XD_KZ, /* 8036 */ + IC_EVEX_L2_XD_KZ, /* 8037 */ + IC_EVEX_L2_XD_KZ, /* 8038 */ + IC_EVEX_L2_XD_KZ, /* 8039 */ + IC_EVEX_L2_W_KZ, /* 8040 */ + IC_EVEX_L2_W_KZ, /* 8041 */ + IC_EVEX_L2_W_XS_KZ, /* 8042 */ + IC_EVEX_L2_W_XS_KZ, /* 8043 */ + IC_EVEX_L2_W_XD_KZ, /* 8044 */ + IC_EVEX_L2_W_XD_KZ, /* 8045 */ + IC_EVEX_L2_W_XD_KZ, /* 8046 */ + IC_EVEX_L2_W_XD_KZ, /* 8047 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8048 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8049 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8050 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8051 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8052 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8053 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8054 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8055 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8056 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8057 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8058 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8059 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8060 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8061 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8062 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8063 */ + IC_EVEX_L2_KZ, /* 8064 */ + IC_EVEX_L2_KZ, /* 8065 */ + IC_EVEX_L2_XS_KZ, /* 8066 */ + IC_EVEX_L2_XS_KZ, /* 8067 */ + IC_EVEX_L2_XD_KZ, /* 8068 */ + IC_EVEX_L2_XD_KZ, /* 8069 */ + IC_EVEX_L2_XD_KZ, /* 8070 */ + IC_EVEX_L2_XD_KZ, /* 8071 */ + IC_EVEX_L2_W_KZ, /* 8072 */ + IC_EVEX_L2_W_KZ, /* 8073 */ + IC_EVEX_L2_W_XS_KZ, /* 8074 */ + IC_EVEX_L2_W_XS_KZ, /* 8075 */ + IC_EVEX_L2_W_XD_KZ, /* 8076 */ + IC_EVEX_L2_W_XD_KZ, /* 8077 */ + IC_EVEX_L2_W_XD_KZ, /* 8078 */ + IC_EVEX_L2_W_XD_KZ, /* 8079 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8080 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8081 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8082 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8083 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8084 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8085 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8086 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8087 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8088 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8089 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8090 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8091 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8092 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8093 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8094 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8095 */ + IC_EVEX_L2_KZ, /* 8096 */ + IC_EVEX_L2_KZ, /* 8097 */ + IC_EVEX_L2_XS_KZ, /* 8098 */ + IC_EVEX_L2_XS_KZ, /* 8099 */ + IC_EVEX_L2_XD_KZ, /* 8100 */ + IC_EVEX_L2_XD_KZ, /* 8101 */ + IC_EVEX_L2_XD_KZ, /* 8102 */ + IC_EVEX_L2_XD_KZ, /* 8103 */ + IC_EVEX_L2_W_KZ, /* 8104 */ + IC_EVEX_L2_W_KZ, /* 8105 */ + IC_EVEX_L2_W_XS_KZ, /* 8106 */ + IC_EVEX_L2_W_XS_KZ, /* 8107 */ + IC_EVEX_L2_W_XD_KZ, /* 8108 */ + IC_EVEX_L2_W_XD_KZ, /* 8109 */ + IC_EVEX_L2_W_XD_KZ, /* 8110 */ + IC_EVEX_L2_W_XD_KZ, /* 8111 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8112 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8113 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8114 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8115 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8116 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8117 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8118 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8119 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8120 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8121 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8122 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8123 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8124 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8125 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8126 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8127 */ + IC_EVEX_L2_KZ, /* 8128 */ + IC_EVEX_L2_KZ, /* 8129 */ + IC_EVEX_L2_XS_KZ, /* 8130 */ + IC_EVEX_L2_XS_KZ, /* 8131 */ + IC_EVEX_L2_XD_KZ, /* 8132 */ + IC_EVEX_L2_XD_KZ, /* 8133 */ + IC_EVEX_L2_XD_KZ, /* 8134 */ + IC_EVEX_L2_XD_KZ, /* 8135 */ + IC_EVEX_L2_W_KZ, /* 8136 */ + IC_EVEX_L2_W_KZ, /* 8137 */ + IC_EVEX_L2_W_XS_KZ, /* 8138 */ + IC_EVEX_L2_W_XS_KZ, /* 8139 */ + IC_EVEX_L2_W_XD_KZ, /* 8140 */ + IC_EVEX_L2_W_XD_KZ, /* 8141 */ + IC_EVEX_L2_W_XD_KZ, /* 8142 */ + IC_EVEX_L2_W_XD_KZ, /* 8143 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8144 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8145 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8146 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8147 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8148 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8149 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8150 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8151 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8152 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8153 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8154 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8155 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8156 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8157 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8158 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8159 */ + IC_EVEX_L2_KZ, /* 8160 */ + IC_EVEX_L2_KZ, /* 8161 */ + IC_EVEX_L2_XS_KZ, /* 8162 */ + IC_EVEX_L2_XS_KZ, /* 8163 */ + IC_EVEX_L2_XD_KZ, /* 8164 */ + IC_EVEX_L2_XD_KZ, /* 8165 */ + IC_EVEX_L2_XD_KZ, /* 8166 */ + IC_EVEX_L2_XD_KZ, /* 8167 */ + IC_EVEX_L2_W_KZ, /* 8168 */ + IC_EVEX_L2_W_KZ, /* 8169 */ + IC_EVEX_L2_W_XS_KZ, /* 8170 */ + IC_EVEX_L2_W_XS_KZ, /* 8171 */ + IC_EVEX_L2_W_XD_KZ, /* 8172 */ + IC_EVEX_L2_W_XD_KZ, /* 8173 */ + IC_EVEX_L2_W_XD_KZ, /* 8174 */ + IC_EVEX_L2_W_XD_KZ, /* 8175 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8176 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8177 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8178 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8179 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8180 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8181 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8182 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8183 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8184 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8185 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8186 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8187 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8188 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8189 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8190 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8191 */ + IC, /* 8192 */ + IC_64BIT, /* 8193 */ + IC_XS, /* 8194 */ + IC_64BIT_XS, /* 8195 */ + IC_XD, /* 8196 */ + IC_64BIT_XD, /* 8197 */ + IC_XS, /* 8198 */ + IC_64BIT_XS, /* 8199 */ + IC, /* 8200 */ + IC_64BIT_REXW, /* 8201 */ + IC_XS, /* 8202 */ + IC_64BIT_REXW_XS, /* 8203 */ + IC_XD, /* 8204 */ + IC_64BIT_REXW_XD, /* 8205 */ + IC_XS, /* 8206 */ + IC_64BIT_REXW_XS, /* 8207 */ + IC_OPSIZE, /* 8208 */ + IC_64BIT_OPSIZE, /* 8209 */ + IC_XS_OPSIZE, /* 8210 */ + IC_64BIT_XS_OPSIZE, /* 8211 */ + IC_XD_OPSIZE, /* 8212 */ + IC_64BIT_XD_OPSIZE, /* 8213 */ + IC_XS_OPSIZE, /* 8214 */ + IC_64BIT_XD_OPSIZE, /* 8215 */ + IC_OPSIZE, /* 8216 */ + IC_64BIT_REXW_OPSIZE, /* 8217 */ + IC_XS_OPSIZE, /* 8218 */ + IC_64BIT_REXW_XS, /* 8219 */ + IC_XD_OPSIZE, /* 8220 */ + IC_64BIT_REXW_XD, /* 8221 */ + IC_XS_OPSIZE, /* 8222 */ + IC_64BIT_REXW_XS, /* 8223 */ + IC_ADSIZE, /* 8224 */ + IC_64BIT_ADSIZE, /* 8225 */ + IC_XS_ADSIZE, /* 8226 */ + IC_64BIT_XS_ADSIZE, /* 8227 */ + IC_XD_ADSIZE, /* 8228 */ + IC_64BIT_XD_ADSIZE, /* 8229 */ + IC_XS_ADSIZE, /* 8230 */ + IC_64BIT_XD_ADSIZE, /* 8231 */ + IC_ADSIZE, /* 8232 */ + IC_64BIT_REXW_ADSIZE, /* 8233 */ + IC_XS_ADSIZE, /* 8234 */ + IC_64BIT_REXW_XS, /* 8235 */ + IC_XD_ADSIZE, /* 8236 */ + IC_64BIT_REXW_XD, /* 8237 */ + IC_XS_ADSIZE, /* 8238 */ + IC_64BIT_REXW_XS, /* 8239 */ + IC_OPSIZE_ADSIZE, /* 8240 */ + IC_64BIT_OPSIZE_ADSIZE, /* 8241 */ + IC_XS_OPSIZE, /* 8242 */ + IC_64BIT_XS_OPSIZE, /* 8243 */ + IC_XD_OPSIZE, /* 8244 */ + IC_64BIT_XD_OPSIZE, /* 8245 */ + IC_XS_OPSIZE, /* 8246 */ + IC_64BIT_XD_OPSIZE, /* 8247 */ + IC_OPSIZE_ADSIZE, /* 8248 */ + IC_64BIT_REXW_OPSIZE, /* 8249 */ + IC_XS_OPSIZE, /* 8250 */ + IC_64BIT_REXW_XS, /* 8251 */ + IC_XD_OPSIZE, /* 8252 */ + IC_64BIT_REXW_XD, /* 8253 */ + IC_XS_OPSIZE, /* 8254 */ + IC_64BIT_REXW_XS, /* 8255 */ + IC_VEX, /* 8256 */ + IC_VEX, /* 8257 */ + IC_VEX_XS, /* 8258 */ + IC_VEX_XS, /* 8259 */ + IC_VEX_XD, /* 8260 */ + IC_VEX_XD, /* 8261 */ + IC_VEX_XD, /* 8262 */ + IC_VEX_XD, /* 8263 */ + IC_VEX_W, /* 8264 */ + IC_VEX_W, /* 8265 */ + IC_VEX_W_XS, /* 8266 */ + IC_VEX_W_XS, /* 8267 */ + IC_VEX_W_XD, /* 8268 */ + IC_VEX_W_XD, /* 8269 */ + IC_VEX_W_XD, /* 8270 */ + IC_VEX_W_XD, /* 8271 */ + IC_VEX_OPSIZE, /* 8272 */ + IC_VEX_OPSIZE, /* 8273 */ + IC_VEX_OPSIZE, /* 8274 */ + IC_VEX_OPSIZE, /* 8275 */ + IC_VEX_OPSIZE, /* 8276 */ + IC_VEX_OPSIZE, /* 8277 */ + IC_VEX_OPSIZE, /* 8278 */ + IC_VEX_OPSIZE, /* 8279 */ + IC_VEX_W_OPSIZE, /* 8280 */ + IC_VEX_W_OPSIZE, /* 8281 */ + IC_VEX_W_OPSIZE, /* 8282 */ + IC_VEX_W_OPSIZE, /* 8283 */ + IC_VEX_W_OPSIZE, /* 8284 */ + IC_VEX_W_OPSIZE, /* 8285 */ + IC_VEX_W_OPSIZE, /* 8286 */ + IC_VEX_W_OPSIZE, /* 8287 */ + IC_VEX, /* 8288 */ + IC_VEX, /* 8289 */ + IC_VEX_XS, /* 8290 */ + IC_VEX_XS, /* 8291 */ + IC_VEX_XD, /* 8292 */ + IC_VEX_XD, /* 8293 */ + IC_VEX_XD, /* 8294 */ + IC_VEX_XD, /* 8295 */ + IC_VEX_W, /* 8296 */ + IC_VEX_W, /* 8297 */ + IC_VEX_W_XS, /* 8298 */ + IC_VEX_W_XS, /* 8299 */ + IC_VEX_W_XD, /* 8300 */ + IC_VEX_W_XD, /* 8301 */ + IC_VEX_W_XD, /* 8302 */ + IC_VEX_W_XD, /* 8303 */ + IC_VEX_OPSIZE, /* 8304 */ + IC_VEX_OPSIZE, /* 8305 */ + IC_VEX_OPSIZE, /* 8306 */ + IC_VEX_OPSIZE, /* 8307 */ + IC_VEX_OPSIZE, /* 8308 */ + IC_VEX_OPSIZE, /* 8309 */ + IC_VEX_OPSIZE, /* 8310 */ + IC_VEX_OPSIZE, /* 8311 */ + IC_VEX_W_OPSIZE, /* 8312 */ + IC_VEX_W_OPSIZE, /* 8313 */ + IC_VEX_W_OPSIZE, /* 8314 */ + IC_VEX_W_OPSIZE, /* 8315 */ + IC_VEX_W_OPSIZE, /* 8316 */ + IC_VEX_W_OPSIZE, /* 8317 */ + IC_VEX_W_OPSIZE, /* 8318 */ + IC_VEX_W_OPSIZE, /* 8319 */ + IC_VEX_L, /* 8320 */ + IC_VEX_L, /* 8321 */ + IC_VEX_L_XS, /* 8322 */ + IC_VEX_L_XS, /* 8323 */ + IC_VEX_L_XD, /* 8324 */ + IC_VEX_L_XD, /* 8325 */ + IC_VEX_L_XD, /* 8326 */ + IC_VEX_L_XD, /* 8327 */ + IC_VEX_L_W, /* 8328 */ + IC_VEX_L_W, /* 8329 */ + IC_VEX_L_W_XS, /* 8330 */ + IC_VEX_L_W_XS, /* 8331 */ + IC_VEX_L_W_XD, /* 8332 */ + IC_VEX_L_W_XD, /* 8333 */ + IC_VEX_L_W_XD, /* 8334 */ + IC_VEX_L_W_XD, /* 8335 */ + IC_VEX_L_OPSIZE, /* 8336 */ + IC_VEX_L_OPSIZE, /* 8337 */ + IC_VEX_L_OPSIZE, /* 8338 */ + IC_VEX_L_OPSIZE, /* 8339 */ + IC_VEX_L_OPSIZE, /* 8340 */ + IC_VEX_L_OPSIZE, /* 8341 */ + IC_VEX_L_OPSIZE, /* 8342 */ + IC_VEX_L_OPSIZE, /* 8343 */ + IC_VEX_L_W_OPSIZE, /* 8344 */ + IC_VEX_L_W_OPSIZE, /* 8345 */ + IC_VEX_L_W_OPSIZE, /* 8346 */ + IC_VEX_L_W_OPSIZE, /* 8347 */ + IC_VEX_L_W_OPSIZE, /* 8348 */ + IC_VEX_L_W_OPSIZE, /* 8349 */ + IC_VEX_L_W_OPSIZE, /* 8350 */ + IC_VEX_L_W_OPSIZE, /* 8351 */ + IC_VEX_L, /* 8352 */ + IC_VEX_L, /* 8353 */ + IC_VEX_L_XS, /* 8354 */ + IC_VEX_L_XS, /* 8355 */ + IC_VEX_L_XD, /* 8356 */ + IC_VEX_L_XD, /* 8357 */ + IC_VEX_L_XD, /* 8358 */ + IC_VEX_L_XD, /* 8359 */ + IC_VEX_L_W, /* 8360 */ + IC_VEX_L_W, /* 8361 */ + IC_VEX_L_W_XS, /* 8362 */ + IC_VEX_L_W_XS, /* 8363 */ + IC_VEX_L_W_XD, /* 8364 */ + IC_VEX_L_W_XD, /* 8365 */ + IC_VEX_L_W_XD, /* 8366 */ + IC_VEX_L_W_XD, /* 8367 */ + IC_VEX_L_OPSIZE, /* 8368 */ + IC_VEX_L_OPSIZE, /* 8369 */ + IC_VEX_L_OPSIZE, /* 8370 */ + IC_VEX_L_OPSIZE, /* 8371 */ + IC_VEX_L_OPSIZE, /* 8372 */ + IC_VEX_L_OPSIZE, /* 8373 */ + IC_VEX_L_OPSIZE, /* 8374 */ + IC_VEX_L_OPSIZE, /* 8375 */ + IC_VEX_L_W_OPSIZE, /* 8376 */ + IC_VEX_L_W_OPSIZE, /* 8377 */ + IC_VEX_L_W_OPSIZE, /* 8378 */ + IC_VEX_L_W_OPSIZE, /* 8379 */ + IC_VEX_L_W_OPSIZE, /* 8380 */ + IC_VEX_L_W_OPSIZE, /* 8381 */ + IC_VEX_L_W_OPSIZE, /* 8382 */ + IC_VEX_L_W_OPSIZE, /* 8383 */ + IC_VEX_L, /* 8384 */ + IC_VEX_L, /* 8385 */ + IC_VEX_L_XS, /* 8386 */ + IC_VEX_L_XS, /* 8387 */ + IC_VEX_L_XD, /* 8388 */ + IC_VEX_L_XD, /* 8389 */ + IC_VEX_L_XD, /* 8390 */ + IC_VEX_L_XD, /* 8391 */ + IC_VEX_L_W, /* 8392 */ + IC_VEX_L_W, /* 8393 */ + IC_VEX_L_W_XS, /* 8394 */ + IC_VEX_L_W_XS, /* 8395 */ + IC_VEX_L_W_XD, /* 8396 */ + IC_VEX_L_W_XD, /* 8397 */ + IC_VEX_L_W_XD, /* 8398 */ + IC_VEX_L_W_XD, /* 8399 */ + IC_VEX_L_OPSIZE, /* 8400 */ + IC_VEX_L_OPSIZE, /* 8401 */ + IC_VEX_L_OPSIZE, /* 8402 */ + IC_VEX_L_OPSIZE, /* 8403 */ + IC_VEX_L_OPSIZE, /* 8404 */ + IC_VEX_L_OPSIZE, /* 8405 */ + IC_VEX_L_OPSIZE, /* 8406 */ + IC_VEX_L_OPSIZE, /* 8407 */ + IC_VEX_L_W_OPSIZE, /* 8408 */ + IC_VEX_L_W_OPSIZE, /* 8409 */ + IC_VEX_L_W_OPSIZE, /* 8410 */ + IC_VEX_L_W_OPSIZE, /* 8411 */ + IC_VEX_L_W_OPSIZE, /* 8412 */ + IC_VEX_L_W_OPSIZE, /* 8413 */ + IC_VEX_L_W_OPSIZE, /* 8414 */ + IC_VEX_L_W_OPSIZE, /* 8415 */ + IC_VEX_L, /* 8416 */ + IC_VEX_L, /* 8417 */ + IC_VEX_L_XS, /* 8418 */ + IC_VEX_L_XS, /* 8419 */ + IC_VEX_L_XD, /* 8420 */ + IC_VEX_L_XD, /* 8421 */ + IC_VEX_L_XD, /* 8422 */ + IC_VEX_L_XD, /* 8423 */ + IC_VEX_L_W, /* 8424 */ + IC_VEX_L_W, /* 8425 */ + IC_VEX_L_W_XS, /* 8426 */ + IC_VEX_L_W_XS, /* 8427 */ + IC_VEX_L_W_XD, /* 8428 */ + IC_VEX_L_W_XD, /* 8429 */ + IC_VEX_L_W_XD, /* 8430 */ + IC_VEX_L_W_XD, /* 8431 */ + IC_VEX_L_OPSIZE, /* 8432 */ + IC_VEX_L_OPSIZE, /* 8433 */ + IC_VEX_L_OPSIZE, /* 8434 */ + IC_VEX_L_OPSIZE, /* 8435 */ + IC_VEX_L_OPSIZE, /* 8436 */ + IC_VEX_L_OPSIZE, /* 8437 */ + IC_VEX_L_OPSIZE, /* 8438 */ + IC_VEX_L_OPSIZE, /* 8439 */ + IC_VEX_L_W_OPSIZE, /* 8440 */ + IC_VEX_L_W_OPSIZE, /* 8441 */ + IC_VEX_L_W_OPSIZE, /* 8442 */ + IC_VEX_L_W_OPSIZE, /* 8443 */ + IC_VEX_L_W_OPSIZE, /* 8444 */ + IC_VEX_L_W_OPSIZE, /* 8445 */ + IC_VEX_L_W_OPSIZE, /* 8446 */ + IC_VEX_L_W_OPSIZE, /* 8447 */ + IC_EVEX_B, /* 8448 */ + IC_EVEX_B, /* 8449 */ + IC_EVEX_XS_B, /* 8450 */ + IC_EVEX_XS_B, /* 8451 */ + IC_EVEX_XD_B, /* 8452 */ + IC_EVEX_XD_B, /* 8453 */ + IC_EVEX_XD_B, /* 8454 */ + IC_EVEX_XD_B, /* 8455 */ + IC_EVEX_W_B, /* 8456 */ + IC_EVEX_W_B, /* 8457 */ + IC_EVEX_W_XS_B, /* 8458 */ + IC_EVEX_W_XS_B, /* 8459 */ + IC_EVEX_W_XD_B, /* 8460 */ + IC_EVEX_W_XD_B, /* 8461 */ + IC_EVEX_W_XD_B, /* 8462 */ + IC_EVEX_W_XD_B, /* 8463 */ + IC_EVEX_OPSIZE_B, /* 8464 */ + IC_EVEX_OPSIZE_B, /* 8465 */ + IC_EVEX_OPSIZE_B, /* 8466 */ + IC_EVEX_OPSIZE_B, /* 8467 */ + IC_EVEX_OPSIZE_B, /* 8468 */ + IC_EVEX_OPSIZE_B, /* 8469 */ + IC_EVEX_OPSIZE_B, /* 8470 */ + IC_EVEX_OPSIZE_B, /* 8471 */ + IC_EVEX_W_OPSIZE_B, /* 8472 */ + IC_EVEX_W_OPSIZE_B, /* 8473 */ + IC_EVEX_W_OPSIZE_B, /* 8474 */ + IC_EVEX_W_OPSIZE_B, /* 8475 */ + IC_EVEX_W_OPSIZE_B, /* 8476 */ + IC_EVEX_W_OPSIZE_B, /* 8477 */ + IC_EVEX_W_OPSIZE_B, /* 8478 */ + IC_EVEX_W_OPSIZE_B, /* 8479 */ + IC_EVEX_B, /* 8480 */ + IC_EVEX_B, /* 8481 */ + IC_EVEX_XS_B, /* 8482 */ + IC_EVEX_XS_B, /* 8483 */ + IC_EVEX_XD_B, /* 8484 */ + IC_EVEX_XD_B, /* 8485 */ + IC_EVEX_XD_B, /* 8486 */ + IC_EVEX_XD_B, /* 8487 */ + IC_EVEX_W_B, /* 8488 */ + IC_EVEX_W_B, /* 8489 */ + IC_EVEX_W_XS_B, /* 8490 */ + IC_EVEX_W_XS_B, /* 8491 */ + IC_EVEX_W_XD_B, /* 8492 */ + IC_EVEX_W_XD_B, /* 8493 */ + IC_EVEX_W_XD_B, /* 8494 */ + IC_EVEX_W_XD_B, /* 8495 */ + IC_EVEX_OPSIZE_B, /* 8496 */ + IC_EVEX_OPSIZE_B, /* 8497 */ + IC_EVEX_OPSIZE_B, /* 8498 */ + IC_EVEX_OPSIZE_B, /* 8499 */ + IC_EVEX_OPSIZE_B, /* 8500 */ + IC_EVEX_OPSIZE_B, /* 8501 */ + IC_EVEX_OPSIZE_B, /* 8502 */ + IC_EVEX_OPSIZE_B, /* 8503 */ + IC_EVEX_W_OPSIZE_B, /* 8504 */ + IC_EVEX_W_OPSIZE_B, /* 8505 */ + IC_EVEX_W_OPSIZE_B, /* 8506 */ + IC_EVEX_W_OPSIZE_B, /* 8507 */ + IC_EVEX_W_OPSIZE_B, /* 8508 */ + IC_EVEX_W_OPSIZE_B, /* 8509 */ + IC_EVEX_W_OPSIZE_B, /* 8510 */ + IC_EVEX_W_OPSIZE_B, /* 8511 */ + IC_EVEX_B, /* 8512 */ + IC_EVEX_B, /* 8513 */ + IC_EVEX_XS_B, /* 8514 */ + IC_EVEX_XS_B, /* 8515 */ + IC_EVEX_XD_B, /* 8516 */ + IC_EVEX_XD_B, /* 8517 */ + IC_EVEX_XD_B, /* 8518 */ + IC_EVEX_XD_B, /* 8519 */ + IC_EVEX_W_B, /* 8520 */ + IC_EVEX_W_B, /* 8521 */ + IC_EVEX_W_XS_B, /* 8522 */ + IC_EVEX_W_XS_B, /* 8523 */ + IC_EVEX_W_XD_B, /* 8524 */ + IC_EVEX_W_XD_B, /* 8525 */ + IC_EVEX_W_XD_B, /* 8526 */ + IC_EVEX_W_XD_B, /* 8527 */ + IC_EVEX_OPSIZE_B, /* 8528 */ + IC_EVEX_OPSIZE_B, /* 8529 */ + IC_EVEX_OPSIZE_B, /* 8530 */ + IC_EVEX_OPSIZE_B, /* 8531 */ + IC_EVEX_OPSIZE_B, /* 8532 */ + IC_EVEX_OPSIZE_B, /* 8533 */ + IC_EVEX_OPSIZE_B, /* 8534 */ + IC_EVEX_OPSIZE_B, /* 8535 */ + IC_EVEX_W_OPSIZE_B, /* 8536 */ + IC_EVEX_W_OPSIZE_B, /* 8537 */ + IC_EVEX_W_OPSIZE_B, /* 8538 */ + IC_EVEX_W_OPSIZE_B, /* 8539 */ + IC_EVEX_W_OPSIZE_B, /* 8540 */ + IC_EVEX_W_OPSIZE_B, /* 8541 */ + IC_EVEX_W_OPSIZE_B, /* 8542 */ + IC_EVEX_W_OPSIZE_B, /* 8543 */ + IC_EVEX_B, /* 8544 */ + IC_EVEX_B, /* 8545 */ + IC_EVEX_XS_B, /* 8546 */ + IC_EVEX_XS_B, /* 8547 */ + IC_EVEX_XD_B, /* 8548 */ + IC_EVEX_XD_B, /* 8549 */ + IC_EVEX_XD_B, /* 8550 */ + IC_EVEX_XD_B, /* 8551 */ + IC_EVEX_W_B, /* 8552 */ + IC_EVEX_W_B, /* 8553 */ + IC_EVEX_W_XS_B, /* 8554 */ + IC_EVEX_W_XS_B, /* 8555 */ + IC_EVEX_W_XD_B, /* 8556 */ + IC_EVEX_W_XD_B, /* 8557 */ + IC_EVEX_W_XD_B, /* 8558 */ + IC_EVEX_W_XD_B, /* 8559 */ + IC_EVEX_OPSIZE_B, /* 8560 */ + IC_EVEX_OPSIZE_B, /* 8561 */ + IC_EVEX_OPSIZE_B, /* 8562 */ + IC_EVEX_OPSIZE_B, /* 8563 */ + IC_EVEX_OPSIZE_B, /* 8564 */ + IC_EVEX_OPSIZE_B, /* 8565 */ + IC_EVEX_OPSIZE_B, /* 8566 */ + IC_EVEX_OPSIZE_B, /* 8567 */ + IC_EVEX_W_OPSIZE_B, /* 8568 */ + IC_EVEX_W_OPSIZE_B, /* 8569 */ + IC_EVEX_W_OPSIZE_B, /* 8570 */ + IC_EVEX_W_OPSIZE_B, /* 8571 */ + IC_EVEX_W_OPSIZE_B, /* 8572 */ + IC_EVEX_W_OPSIZE_B, /* 8573 */ + IC_EVEX_W_OPSIZE_B, /* 8574 */ + IC_EVEX_W_OPSIZE_B, /* 8575 */ + IC_EVEX_B, /* 8576 */ + IC_EVEX_B, /* 8577 */ + IC_EVEX_XS_B, /* 8578 */ + IC_EVEX_XS_B, /* 8579 */ + IC_EVEX_XD_B, /* 8580 */ + IC_EVEX_XD_B, /* 8581 */ + IC_EVEX_XD_B, /* 8582 */ + IC_EVEX_XD_B, /* 8583 */ + IC_EVEX_W_B, /* 8584 */ + IC_EVEX_W_B, /* 8585 */ + IC_EVEX_W_XS_B, /* 8586 */ + IC_EVEX_W_XS_B, /* 8587 */ + IC_EVEX_W_XD_B, /* 8588 */ + IC_EVEX_W_XD_B, /* 8589 */ + IC_EVEX_W_XD_B, /* 8590 */ + IC_EVEX_W_XD_B, /* 8591 */ + IC_EVEX_OPSIZE_B, /* 8592 */ + IC_EVEX_OPSIZE_B, /* 8593 */ + IC_EVEX_OPSIZE_B, /* 8594 */ + IC_EVEX_OPSIZE_B, /* 8595 */ + IC_EVEX_OPSIZE_B, /* 8596 */ + IC_EVEX_OPSIZE_B, /* 8597 */ + IC_EVEX_OPSIZE_B, /* 8598 */ + IC_EVEX_OPSIZE_B, /* 8599 */ + IC_EVEX_W_OPSIZE_B, /* 8600 */ + IC_EVEX_W_OPSIZE_B, /* 8601 */ + IC_EVEX_W_OPSIZE_B, /* 8602 */ + IC_EVEX_W_OPSIZE_B, /* 8603 */ + IC_EVEX_W_OPSIZE_B, /* 8604 */ + IC_EVEX_W_OPSIZE_B, /* 8605 */ + IC_EVEX_W_OPSIZE_B, /* 8606 */ + IC_EVEX_W_OPSIZE_B, /* 8607 */ + IC_EVEX_B, /* 8608 */ + IC_EVEX_B, /* 8609 */ + IC_EVEX_XS_B, /* 8610 */ + IC_EVEX_XS_B, /* 8611 */ + IC_EVEX_XD_B, /* 8612 */ + IC_EVEX_XD_B, /* 8613 */ + IC_EVEX_XD_B, /* 8614 */ + IC_EVEX_XD_B, /* 8615 */ + IC_EVEX_W_B, /* 8616 */ + IC_EVEX_W_B, /* 8617 */ + IC_EVEX_W_XS_B, /* 8618 */ + IC_EVEX_W_XS_B, /* 8619 */ + IC_EVEX_W_XD_B, /* 8620 */ + IC_EVEX_W_XD_B, /* 8621 */ + IC_EVEX_W_XD_B, /* 8622 */ + IC_EVEX_W_XD_B, /* 8623 */ + IC_EVEX_OPSIZE_B, /* 8624 */ + IC_EVEX_OPSIZE_B, /* 8625 */ + IC_EVEX_OPSIZE_B, /* 8626 */ + IC_EVEX_OPSIZE_B, /* 8627 */ + IC_EVEX_OPSIZE_B, /* 8628 */ + IC_EVEX_OPSIZE_B, /* 8629 */ + IC_EVEX_OPSIZE_B, /* 8630 */ + IC_EVEX_OPSIZE_B, /* 8631 */ + IC_EVEX_W_OPSIZE_B, /* 8632 */ + IC_EVEX_W_OPSIZE_B, /* 8633 */ + IC_EVEX_W_OPSIZE_B, /* 8634 */ + IC_EVEX_W_OPSIZE_B, /* 8635 */ + IC_EVEX_W_OPSIZE_B, /* 8636 */ + IC_EVEX_W_OPSIZE_B, /* 8637 */ + IC_EVEX_W_OPSIZE_B, /* 8638 */ + IC_EVEX_W_OPSIZE_B, /* 8639 */ + IC_EVEX_B, /* 8640 */ + IC_EVEX_B, /* 8641 */ + IC_EVEX_XS_B, /* 8642 */ + IC_EVEX_XS_B, /* 8643 */ + IC_EVEX_XD_B, /* 8644 */ + IC_EVEX_XD_B, /* 8645 */ + IC_EVEX_XD_B, /* 8646 */ + IC_EVEX_XD_B, /* 8647 */ + IC_EVEX_W_B, /* 8648 */ + IC_EVEX_W_B, /* 8649 */ + IC_EVEX_W_XS_B, /* 8650 */ + IC_EVEX_W_XS_B, /* 8651 */ + IC_EVEX_W_XD_B, /* 8652 */ + IC_EVEX_W_XD_B, /* 8653 */ + IC_EVEX_W_XD_B, /* 8654 */ + IC_EVEX_W_XD_B, /* 8655 */ + IC_EVEX_OPSIZE_B, /* 8656 */ + IC_EVEX_OPSIZE_B, /* 8657 */ + IC_EVEX_OPSIZE_B, /* 8658 */ + IC_EVEX_OPSIZE_B, /* 8659 */ + IC_EVEX_OPSIZE_B, /* 8660 */ + IC_EVEX_OPSIZE_B, /* 8661 */ + IC_EVEX_OPSIZE_B, /* 8662 */ + IC_EVEX_OPSIZE_B, /* 8663 */ + IC_EVEX_W_OPSIZE_B, /* 8664 */ + IC_EVEX_W_OPSIZE_B, /* 8665 */ + IC_EVEX_W_OPSIZE_B, /* 8666 */ + IC_EVEX_W_OPSIZE_B, /* 8667 */ + IC_EVEX_W_OPSIZE_B, /* 8668 */ + IC_EVEX_W_OPSIZE_B, /* 8669 */ + IC_EVEX_W_OPSIZE_B, /* 8670 */ + IC_EVEX_W_OPSIZE_B, /* 8671 */ + IC_EVEX_B, /* 8672 */ + IC_EVEX_B, /* 8673 */ + IC_EVEX_XS_B, /* 8674 */ + IC_EVEX_XS_B, /* 8675 */ + IC_EVEX_XD_B, /* 8676 */ + IC_EVEX_XD_B, /* 8677 */ + IC_EVEX_XD_B, /* 8678 */ + IC_EVEX_XD_B, /* 8679 */ + IC_EVEX_W_B, /* 8680 */ + IC_EVEX_W_B, /* 8681 */ + IC_EVEX_W_XS_B, /* 8682 */ + IC_EVEX_W_XS_B, /* 8683 */ + IC_EVEX_W_XD_B, /* 8684 */ + IC_EVEX_W_XD_B, /* 8685 */ + IC_EVEX_W_XD_B, /* 8686 */ + IC_EVEX_W_XD_B, /* 8687 */ + IC_EVEX_OPSIZE_B, /* 8688 */ + IC_EVEX_OPSIZE_B, /* 8689 */ + IC_EVEX_OPSIZE_B, /* 8690 */ + IC_EVEX_OPSIZE_B, /* 8691 */ + IC_EVEX_OPSIZE_B, /* 8692 */ + IC_EVEX_OPSIZE_B, /* 8693 */ + IC_EVEX_OPSIZE_B, /* 8694 */ + IC_EVEX_OPSIZE_B, /* 8695 */ + IC_EVEX_W_OPSIZE_B, /* 8696 */ + IC_EVEX_W_OPSIZE_B, /* 8697 */ + IC_EVEX_W_OPSIZE_B, /* 8698 */ + IC_EVEX_W_OPSIZE_B, /* 8699 */ + IC_EVEX_W_OPSIZE_B, /* 8700 */ + IC_EVEX_W_OPSIZE_B, /* 8701 */ + IC_EVEX_W_OPSIZE_B, /* 8702 */ + IC_EVEX_W_OPSIZE_B, /* 8703 */ + IC, /* 8704 */ + IC_64BIT, /* 8705 */ + IC_XS, /* 8706 */ + IC_64BIT_XS, /* 8707 */ + IC_XD, /* 8708 */ + IC_64BIT_XD, /* 8709 */ + IC_XS, /* 8710 */ + IC_64BIT_XS, /* 8711 */ + IC, /* 8712 */ + IC_64BIT_REXW, /* 8713 */ + IC_XS, /* 8714 */ + IC_64BIT_REXW_XS, /* 8715 */ + IC_XD, /* 8716 */ + IC_64BIT_REXW_XD, /* 8717 */ + IC_XS, /* 8718 */ + IC_64BIT_REXW_XS, /* 8719 */ + IC_OPSIZE, /* 8720 */ + IC_64BIT_OPSIZE, /* 8721 */ + IC_XS_OPSIZE, /* 8722 */ + IC_64BIT_XS_OPSIZE, /* 8723 */ + IC_XD_OPSIZE, /* 8724 */ + IC_64BIT_XD_OPSIZE, /* 8725 */ + IC_XS_OPSIZE, /* 8726 */ + IC_64BIT_XD_OPSIZE, /* 8727 */ + IC_OPSIZE, /* 8728 */ + IC_64BIT_REXW_OPSIZE, /* 8729 */ + IC_XS_OPSIZE, /* 8730 */ + IC_64BIT_REXW_XS, /* 8731 */ + IC_XD_OPSIZE, /* 8732 */ + IC_64BIT_REXW_XD, /* 8733 */ + IC_XS_OPSIZE, /* 8734 */ + IC_64BIT_REXW_XS, /* 8735 */ + IC_ADSIZE, /* 8736 */ + IC_64BIT_ADSIZE, /* 8737 */ + IC_XS_ADSIZE, /* 8738 */ + IC_64BIT_XS_ADSIZE, /* 8739 */ + IC_XD_ADSIZE, /* 8740 */ + IC_64BIT_XD_ADSIZE, /* 8741 */ + IC_XS_ADSIZE, /* 8742 */ + IC_64BIT_XD_ADSIZE, /* 8743 */ + IC_ADSIZE, /* 8744 */ + IC_64BIT_REXW_ADSIZE, /* 8745 */ + IC_XS_ADSIZE, /* 8746 */ + IC_64BIT_REXW_XS, /* 8747 */ + IC_XD_ADSIZE, /* 8748 */ + IC_64BIT_REXW_XD, /* 8749 */ + IC_XS_ADSIZE, /* 8750 */ + IC_64BIT_REXW_XS, /* 8751 */ + IC_OPSIZE_ADSIZE, /* 8752 */ + IC_64BIT_OPSIZE_ADSIZE, /* 8753 */ + IC_XS_OPSIZE, /* 8754 */ + IC_64BIT_XS_OPSIZE, /* 8755 */ + IC_XD_OPSIZE, /* 8756 */ + IC_64BIT_XD_OPSIZE, /* 8757 */ + IC_XS_OPSIZE, /* 8758 */ + IC_64BIT_XD_OPSIZE, /* 8759 */ + IC_OPSIZE_ADSIZE, /* 8760 */ + IC_64BIT_REXW_OPSIZE, /* 8761 */ + IC_XS_OPSIZE, /* 8762 */ + IC_64BIT_REXW_XS, /* 8763 */ + IC_XD_OPSIZE, /* 8764 */ + IC_64BIT_REXW_XD, /* 8765 */ + IC_XS_OPSIZE, /* 8766 */ + IC_64BIT_REXW_XS, /* 8767 */ + IC_VEX, /* 8768 */ + IC_VEX, /* 8769 */ + IC_VEX_XS, /* 8770 */ + IC_VEX_XS, /* 8771 */ + IC_VEX_XD, /* 8772 */ + IC_VEX_XD, /* 8773 */ + IC_VEX_XD, /* 8774 */ + IC_VEX_XD, /* 8775 */ + IC_VEX_W, /* 8776 */ + IC_VEX_W, /* 8777 */ + IC_VEX_W_XS, /* 8778 */ + IC_VEX_W_XS, /* 8779 */ + IC_VEX_W_XD, /* 8780 */ + IC_VEX_W_XD, /* 8781 */ + IC_VEX_W_XD, /* 8782 */ + IC_VEX_W_XD, /* 8783 */ + IC_VEX_OPSIZE, /* 8784 */ + IC_VEX_OPSIZE, /* 8785 */ + IC_VEX_OPSIZE, /* 8786 */ + IC_VEX_OPSIZE, /* 8787 */ + IC_VEX_OPSIZE, /* 8788 */ + IC_VEX_OPSIZE, /* 8789 */ + IC_VEX_OPSIZE, /* 8790 */ + IC_VEX_OPSIZE, /* 8791 */ + IC_VEX_W_OPSIZE, /* 8792 */ + IC_VEX_W_OPSIZE, /* 8793 */ + IC_VEX_W_OPSIZE, /* 8794 */ + IC_VEX_W_OPSIZE, /* 8795 */ + IC_VEX_W_OPSIZE, /* 8796 */ + IC_VEX_W_OPSIZE, /* 8797 */ + IC_VEX_W_OPSIZE, /* 8798 */ + IC_VEX_W_OPSIZE, /* 8799 */ + IC_VEX, /* 8800 */ + IC_VEX, /* 8801 */ + IC_VEX_XS, /* 8802 */ + IC_VEX_XS, /* 8803 */ + IC_VEX_XD, /* 8804 */ + IC_VEX_XD, /* 8805 */ + IC_VEX_XD, /* 8806 */ + IC_VEX_XD, /* 8807 */ + IC_VEX_W, /* 8808 */ + IC_VEX_W, /* 8809 */ + IC_VEX_W_XS, /* 8810 */ + IC_VEX_W_XS, /* 8811 */ + IC_VEX_W_XD, /* 8812 */ + IC_VEX_W_XD, /* 8813 */ + IC_VEX_W_XD, /* 8814 */ + IC_VEX_W_XD, /* 8815 */ + IC_VEX_OPSIZE, /* 8816 */ + IC_VEX_OPSIZE, /* 8817 */ + IC_VEX_OPSIZE, /* 8818 */ + IC_VEX_OPSIZE, /* 8819 */ + IC_VEX_OPSIZE, /* 8820 */ + IC_VEX_OPSIZE, /* 8821 */ + IC_VEX_OPSIZE, /* 8822 */ + IC_VEX_OPSIZE, /* 8823 */ + IC_VEX_W_OPSIZE, /* 8824 */ + IC_VEX_W_OPSIZE, /* 8825 */ + IC_VEX_W_OPSIZE, /* 8826 */ + IC_VEX_W_OPSIZE, /* 8827 */ + IC_VEX_W_OPSIZE, /* 8828 */ + IC_VEX_W_OPSIZE, /* 8829 */ + IC_VEX_W_OPSIZE, /* 8830 */ + IC_VEX_W_OPSIZE, /* 8831 */ + IC_VEX_L, /* 8832 */ + IC_VEX_L, /* 8833 */ + IC_VEX_L_XS, /* 8834 */ + IC_VEX_L_XS, /* 8835 */ + IC_VEX_L_XD, /* 8836 */ + IC_VEX_L_XD, /* 8837 */ + IC_VEX_L_XD, /* 8838 */ + IC_VEX_L_XD, /* 8839 */ + IC_VEX_L_W, /* 8840 */ + IC_VEX_L_W, /* 8841 */ + IC_VEX_L_W_XS, /* 8842 */ + IC_VEX_L_W_XS, /* 8843 */ + IC_VEX_L_W_XD, /* 8844 */ + IC_VEX_L_W_XD, /* 8845 */ + IC_VEX_L_W_XD, /* 8846 */ + IC_VEX_L_W_XD, /* 8847 */ + IC_VEX_L_OPSIZE, /* 8848 */ + IC_VEX_L_OPSIZE, /* 8849 */ + IC_VEX_L_OPSIZE, /* 8850 */ + IC_VEX_L_OPSIZE, /* 8851 */ + IC_VEX_L_OPSIZE, /* 8852 */ + IC_VEX_L_OPSIZE, /* 8853 */ + IC_VEX_L_OPSIZE, /* 8854 */ + IC_VEX_L_OPSIZE, /* 8855 */ + IC_VEX_L_W_OPSIZE, /* 8856 */ + IC_VEX_L_W_OPSIZE, /* 8857 */ + IC_VEX_L_W_OPSIZE, /* 8858 */ + IC_VEX_L_W_OPSIZE, /* 8859 */ + IC_VEX_L_W_OPSIZE, /* 8860 */ + IC_VEX_L_W_OPSIZE, /* 8861 */ + IC_VEX_L_W_OPSIZE, /* 8862 */ + IC_VEX_L_W_OPSIZE, /* 8863 */ + IC_VEX_L, /* 8864 */ + IC_VEX_L, /* 8865 */ + IC_VEX_L_XS, /* 8866 */ + IC_VEX_L_XS, /* 8867 */ + IC_VEX_L_XD, /* 8868 */ + IC_VEX_L_XD, /* 8869 */ + IC_VEX_L_XD, /* 8870 */ + IC_VEX_L_XD, /* 8871 */ + IC_VEX_L_W, /* 8872 */ + IC_VEX_L_W, /* 8873 */ + IC_VEX_L_W_XS, /* 8874 */ + IC_VEX_L_W_XS, /* 8875 */ + IC_VEX_L_W_XD, /* 8876 */ + IC_VEX_L_W_XD, /* 8877 */ + IC_VEX_L_W_XD, /* 8878 */ + IC_VEX_L_W_XD, /* 8879 */ + IC_VEX_L_OPSIZE, /* 8880 */ + IC_VEX_L_OPSIZE, /* 8881 */ + IC_VEX_L_OPSIZE, /* 8882 */ + IC_VEX_L_OPSIZE, /* 8883 */ + IC_VEX_L_OPSIZE, /* 8884 */ + IC_VEX_L_OPSIZE, /* 8885 */ + IC_VEX_L_OPSIZE, /* 8886 */ + IC_VEX_L_OPSIZE, /* 8887 */ + IC_VEX_L_W_OPSIZE, /* 8888 */ + IC_VEX_L_W_OPSIZE, /* 8889 */ + IC_VEX_L_W_OPSIZE, /* 8890 */ + IC_VEX_L_W_OPSIZE, /* 8891 */ + IC_VEX_L_W_OPSIZE, /* 8892 */ + IC_VEX_L_W_OPSIZE, /* 8893 */ + IC_VEX_L_W_OPSIZE, /* 8894 */ + IC_VEX_L_W_OPSIZE, /* 8895 */ + IC_VEX_L, /* 8896 */ + IC_VEX_L, /* 8897 */ + IC_VEX_L_XS, /* 8898 */ + IC_VEX_L_XS, /* 8899 */ + IC_VEX_L_XD, /* 8900 */ + IC_VEX_L_XD, /* 8901 */ + IC_VEX_L_XD, /* 8902 */ + IC_VEX_L_XD, /* 8903 */ + IC_VEX_L_W, /* 8904 */ + IC_VEX_L_W, /* 8905 */ + IC_VEX_L_W_XS, /* 8906 */ + IC_VEX_L_W_XS, /* 8907 */ + IC_VEX_L_W_XD, /* 8908 */ + IC_VEX_L_W_XD, /* 8909 */ + IC_VEX_L_W_XD, /* 8910 */ + IC_VEX_L_W_XD, /* 8911 */ + IC_VEX_L_OPSIZE, /* 8912 */ + IC_VEX_L_OPSIZE, /* 8913 */ + IC_VEX_L_OPSIZE, /* 8914 */ + IC_VEX_L_OPSIZE, /* 8915 */ + IC_VEX_L_OPSIZE, /* 8916 */ + IC_VEX_L_OPSIZE, /* 8917 */ + IC_VEX_L_OPSIZE, /* 8918 */ + IC_VEX_L_OPSIZE, /* 8919 */ + IC_VEX_L_W_OPSIZE, /* 8920 */ + IC_VEX_L_W_OPSIZE, /* 8921 */ + IC_VEX_L_W_OPSIZE, /* 8922 */ + IC_VEX_L_W_OPSIZE, /* 8923 */ + IC_VEX_L_W_OPSIZE, /* 8924 */ + IC_VEX_L_W_OPSIZE, /* 8925 */ + IC_VEX_L_W_OPSIZE, /* 8926 */ + IC_VEX_L_W_OPSIZE, /* 8927 */ + IC_VEX_L, /* 8928 */ + IC_VEX_L, /* 8929 */ + IC_VEX_L_XS, /* 8930 */ + IC_VEX_L_XS, /* 8931 */ + IC_VEX_L_XD, /* 8932 */ + IC_VEX_L_XD, /* 8933 */ + IC_VEX_L_XD, /* 8934 */ + IC_VEX_L_XD, /* 8935 */ + IC_VEX_L_W, /* 8936 */ + IC_VEX_L_W, /* 8937 */ + IC_VEX_L_W_XS, /* 8938 */ + IC_VEX_L_W_XS, /* 8939 */ + IC_VEX_L_W_XD, /* 8940 */ + IC_VEX_L_W_XD, /* 8941 */ + IC_VEX_L_W_XD, /* 8942 */ + IC_VEX_L_W_XD, /* 8943 */ + IC_VEX_L_OPSIZE, /* 8944 */ + IC_VEX_L_OPSIZE, /* 8945 */ + IC_VEX_L_OPSIZE, /* 8946 */ + IC_VEX_L_OPSIZE, /* 8947 */ + IC_VEX_L_OPSIZE, /* 8948 */ + IC_VEX_L_OPSIZE, /* 8949 */ + IC_VEX_L_OPSIZE, /* 8950 */ + IC_VEX_L_OPSIZE, /* 8951 */ + IC_VEX_L_W_OPSIZE, /* 8952 */ + IC_VEX_L_W_OPSIZE, /* 8953 */ + IC_VEX_L_W_OPSIZE, /* 8954 */ + IC_VEX_L_W_OPSIZE, /* 8955 */ + IC_VEX_L_W_OPSIZE, /* 8956 */ + IC_VEX_L_W_OPSIZE, /* 8957 */ + IC_VEX_L_W_OPSIZE, /* 8958 */ + IC_VEX_L_W_OPSIZE, /* 8959 */ + IC_EVEX_L_B, /* 8960 */ + IC_EVEX_L_B, /* 8961 */ + IC_EVEX_L_XS_B, /* 8962 */ + IC_EVEX_L_XS_B, /* 8963 */ + IC_EVEX_L_XD_B, /* 8964 */ + IC_EVEX_L_XD_B, /* 8965 */ + IC_EVEX_L_XD_B, /* 8966 */ + IC_EVEX_L_XD_B, /* 8967 */ + IC_EVEX_L_W_B, /* 8968 */ + IC_EVEX_L_W_B, /* 8969 */ + IC_EVEX_L_W_XS_B, /* 8970 */ + IC_EVEX_L_W_XS_B, /* 8971 */ + IC_EVEX_L_W_XD_B, /* 8972 */ + IC_EVEX_L_W_XD_B, /* 8973 */ + IC_EVEX_L_W_XD_B, /* 8974 */ + IC_EVEX_L_W_XD_B, /* 8975 */ + IC_EVEX_L_OPSIZE_B, /* 8976 */ + IC_EVEX_L_OPSIZE_B, /* 8977 */ + IC_EVEX_L_OPSIZE_B, /* 8978 */ + IC_EVEX_L_OPSIZE_B, /* 8979 */ + IC_EVEX_L_OPSIZE_B, /* 8980 */ + IC_EVEX_L_OPSIZE_B, /* 8981 */ + IC_EVEX_L_OPSIZE_B, /* 8982 */ + IC_EVEX_L_OPSIZE_B, /* 8983 */ + IC_EVEX_L_W_OPSIZE_B, /* 8984 */ + IC_EVEX_L_W_OPSIZE_B, /* 8985 */ + IC_EVEX_L_W_OPSIZE_B, /* 8986 */ + IC_EVEX_L_W_OPSIZE_B, /* 8987 */ + IC_EVEX_L_W_OPSIZE_B, /* 8988 */ + IC_EVEX_L_W_OPSIZE_B, /* 8989 */ + IC_EVEX_L_W_OPSIZE_B, /* 8990 */ + IC_EVEX_L_W_OPSIZE_B, /* 8991 */ + IC_EVEX_L_B, /* 8992 */ + IC_EVEX_L_B, /* 8993 */ + IC_EVEX_L_XS_B, /* 8994 */ + IC_EVEX_L_XS_B, /* 8995 */ + IC_EVEX_L_XD_B, /* 8996 */ + IC_EVEX_L_XD_B, /* 8997 */ + IC_EVEX_L_XD_B, /* 8998 */ + IC_EVEX_L_XD_B, /* 8999 */ + IC_EVEX_L_W_B, /* 9000 */ + IC_EVEX_L_W_B, /* 9001 */ + IC_EVEX_L_W_XS_B, /* 9002 */ + IC_EVEX_L_W_XS_B, /* 9003 */ + IC_EVEX_L_W_XD_B, /* 9004 */ + IC_EVEX_L_W_XD_B, /* 9005 */ + IC_EVEX_L_W_XD_B, /* 9006 */ + IC_EVEX_L_W_XD_B, /* 9007 */ + IC_EVEX_L_OPSIZE_B, /* 9008 */ + IC_EVEX_L_OPSIZE_B, /* 9009 */ + IC_EVEX_L_OPSIZE_B, /* 9010 */ + IC_EVEX_L_OPSIZE_B, /* 9011 */ + IC_EVEX_L_OPSIZE_B, /* 9012 */ + IC_EVEX_L_OPSIZE_B, /* 9013 */ + IC_EVEX_L_OPSIZE_B, /* 9014 */ + IC_EVEX_L_OPSIZE_B, /* 9015 */ + IC_EVEX_L_W_OPSIZE_B, /* 9016 */ + IC_EVEX_L_W_OPSIZE_B, /* 9017 */ + IC_EVEX_L_W_OPSIZE_B, /* 9018 */ + IC_EVEX_L_W_OPSIZE_B, /* 9019 */ + IC_EVEX_L_W_OPSIZE_B, /* 9020 */ + IC_EVEX_L_W_OPSIZE_B, /* 9021 */ + IC_EVEX_L_W_OPSIZE_B, /* 9022 */ + IC_EVEX_L_W_OPSIZE_B, /* 9023 */ + IC_EVEX_L_B, /* 9024 */ + IC_EVEX_L_B, /* 9025 */ + IC_EVEX_L_XS_B, /* 9026 */ + IC_EVEX_L_XS_B, /* 9027 */ + IC_EVEX_L_XD_B, /* 9028 */ + IC_EVEX_L_XD_B, /* 9029 */ + IC_EVEX_L_XD_B, /* 9030 */ + IC_EVEX_L_XD_B, /* 9031 */ + IC_EVEX_L_W_B, /* 9032 */ + IC_EVEX_L_W_B, /* 9033 */ + IC_EVEX_L_W_XS_B, /* 9034 */ + IC_EVEX_L_W_XS_B, /* 9035 */ + IC_EVEX_L_W_XD_B, /* 9036 */ + IC_EVEX_L_W_XD_B, /* 9037 */ + IC_EVEX_L_W_XD_B, /* 9038 */ + IC_EVEX_L_W_XD_B, /* 9039 */ + IC_EVEX_L_OPSIZE_B, /* 9040 */ + IC_EVEX_L_OPSIZE_B, /* 9041 */ + IC_EVEX_L_OPSIZE_B, /* 9042 */ + IC_EVEX_L_OPSIZE_B, /* 9043 */ + IC_EVEX_L_OPSIZE_B, /* 9044 */ + IC_EVEX_L_OPSIZE_B, /* 9045 */ + IC_EVEX_L_OPSIZE_B, /* 9046 */ + IC_EVEX_L_OPSIZE_B, /* 9047 */ + IC_EVEX_L_W_OPSIZE_B, /* 9048 */ + IC_EVEX_L_W_OPSIZE_B, /* 9049 */ + IC_EVEX_L_W_OPSIZE_B, /* 9050 */ + IC_EVEX_L_W_OPSIZE_B, /* 9051 */ + IC_EVEX_L_W_OPSIZE_B, /* 9052 */ + IC_EVEX_L_W_OPSIZE_B, /* 9053 */ + IC_EVEX_L_W_OPSIZE_B, /* 9054 */ + IC_EVEX_L_W_OPSIZE_B, /* 9055 */ + IC_EVEX_L_B, /* 9056 */ + IC_EVEX_L_B, /* 9057 */ + IC_EVEX_L_XS_B, /* 9058 */ + IC_EVEX_L_XS_B, /* 9059 */ + IC_EVEX_L_XD_B, /* 9060 */ + IC_EVEX_L_XD_B, /* 9061 */ + IC_EVEX_L_XD_B, /* 9062 */ + IC_EVEX_L_XD_B, /* 9063 */ + IC_EVEX_L_W_B, /* 9064 */ + IC_EVEX_L_W_B, /* 9065 */ + IC_EVEX_L_W_XS_B, /* 9066 */ + IC_EVEX_L_W_XS_B, /* 9067 */ + IC_EVEX_L_W_XD_B, /* 9068 */ + IC_EVEX_L_W_XD_B, /* 9069 */ + IC_EVEX_L_W_XD_B, /* 9070 */ + IC_EVEX_L_W_XD_B, /* 9071 */ + IC_EVEX_L_OPSIZE_B, /* 9072 */ + IC_EVEX_L_OPSIZE_B, /* 9073 */ + IC_EVEX_L_OPSIZE_B, /* 9074 */ + IC_EVEX_L_OPSIZE_B, /* 9075 */ + IC_EVEX_L_OPSIZE_B, /* 9076 */ + IC_EVEX_L_OPSIZE_B, /* 9077 */ + IC_EVEX_L_OPSIZE_B, /* 9078 */ + IC_EVEX_L_OPSIZE_B, /* 9079 */ + IC_EVEX_L_W_OPSIZE_B, /* 9080 */ + IC_EVEX_L_W_OPSIZE_B, /* 9081 */ + IC_EVEX_L_W_OPSIZE_B, /* 9082 */ + IC_EVEX_L_W_OPSIZE_B, /* 9083 */ + IC_EVEX_L_W_OPSIZE_B, /* 9084 */ + IC_EVEX_L_W_OPSIZE_B, /* 9085 */ + IC_EVEX_L_W_OPSIZE_B, /* 9086 */ + IC_EVEX_L_W_OPSIZE_B, /* 9087 */ + IC_EVEX_L_B, /* 9088 */ + IC_EVEX_L_B, /* 9089 */ + IC_EVEX_L_XS_B, /* 9090 */ + IC_EVEX_L_XS_B, /* 9091 */ + IC_EVEX_L_XD_B, /* 9092 */ + IC_EVEX_L_XD_B, /* 9093 */ + IC_EVEX_L_XD_B, /* 9094 */ + IC_EVEX_L_XD_B, /* 9095 */ + IC_EVEX_L_W_B, /* 9096 */ + IC_EVEX_L_W_B, /* 9097 */ + IC_EVEX_L_W_XS_B, /* 9098 */ + IC_EVEX_L_W_XS_B, /* 9099 */ + IC_EVEX_L_W_XD_B, /* 9100 */ + IC_EVEX_L_W_XD_B, /* 9101 */ + IC_EVEX_L_W_XD_B, /* 9102 */ + IC_EVEX_L_W_XD_B, /* 9103 */ + IC_EVEX_L_OPSIZE_B, /* 9104 */ + IC_EVEX_L_OPSIZE_B, /* 9105 */ + IC_EVEX_L_OPSIZE_B, /* 9106 */ + IC_EVEX_L_OPSIZE_B, /* 9107 */ + IC_EVEX_L_OPSIZE_B, /* 9108 */ + IC_EVEX_L_OPSIZE_B, /* 9109 */ + IC_EVEX_L_OPSIZE_B, /* 9110 */ + IC_EVEX_L_OPSIZE_B, /* 9111 */ + IC_EVEX_L_W_OPSIZE_B, /* 9112 */ + IC_EVEX_L_W_OPSIZE_B, /* 9113 */ + IC_EVEX_L_W_OPSIZE_B, /* 9114 */ + IC_EVEX_L_W_OPSIZE_B, /* 9115 */ + IC_EVEX_L_W_OPSIZE_B, /* 9116 */ + IC_EVEX_L_W_OPSIZE_B, /* 9117 */ + IC_EVEX_L_W_OPSIZE_B, /* 9118 */ + IC_EVEX_L_W_OPSIZE_B, /* 9119 */ + IC_EVEX_L_B, /* 9120 */ + IC_EVEX_L_B, /* 9121 */ + IC_EVEX_L_XS_B, /* 9122 */ + IC_EVEX_L_XS_B, /* 9123 */ + IC_EVEX_L_XD_B, /* 9124 */ + IC_EVEX_L_XD_B, /* 9125 */ + IC_EVEX_L_XD_B, /* 9126 */ + IC_EVEX_L_XD_B, /* 9127 */ + IC_EVEX_L_W_B, /* 9128 */ + IC_EVEX_L_W_B, /* 9129 */ + IC_EVEX_L_W_XS_B, /* 9130 */ + IC_EVEX_L_W_XS_B, /* 9131 */ + IC_EVEX_L_W_XD_B, /* 9132 */ + IC_EVEX_L_W_XD_B, /* 9133 */ + IC_EVEX_L_W_XD_B, /* 9134 */ + IC_EVEX_L_W_XD_B, /* 9135 */ + IC_EVEX_L_OPSIZE_B, /* 9136 */ + IC_EVEX_L_OPSIZE_B, /* 9137 */ + IC_EVEX_L_OPSIZE_B, /* 9138 */ + IC_EVEX_L_OPSIZE_B, /* 9139 */ + IC_EVEX_L_OPSIZE_B, /* 9140 */ + IC_EVEX_L_OPSIZE_B, /* 9141 */ + IC_EVEX_L_OPSIZE_B, /* 9142 */ + IC_EVEX_L_OPSIZE_B, /* 9143 */ + IC_EVEX_L_W_OPSIZE_B, /* 9144 */ + IC_EVEX_L_W_OPSIZE_B, /* 9145 */ + IC_EVEX_L_W_OPSIZE_B, /* 9146 */ + IC_EVEX_L_W_OPSIZE_B, /* 9147 */ + IC_EVEX_L_W_OPSIZE_B, /* 9148 */ + IC_EVEX_L_W_OPSIZE_B, /* 9149 */ + IC_EVEX_L_W_OPSIZE_B, /* 9150 */ + IC_EVEX_L_W_OPSIZE_B, /* 9151 */ + IC_EVEX_L_B, /* 9152 */ + IC_EVEX_L_B, /* 9153 */ + IC_EVEX_L_XS_B, /* 9154 */ + IC_EVEX_L_XS_B, /* 9155 */ + IC_EVEX_L_XD_B, /* 9156 */ + IC_EVEX_L_XD_B, /* 9157 */ + IC_EVEX_L_XD_B, /* 9158 */ + IC_EVEX_L_XD_B, /* 9159 */ + IC_EVEX_L_W_B, /* 9160 */ + IC_EVEX_L_W_B, /* 9161 */ + IC_EVEX_L_W_XS_B, /* 9162 */ + IC_EVEX_L_W_XS_B, /* 9163 */ + IC_EVEX_L_W_XD_B, /* 9164 */ + IC_EVEX_L_W_XD_B, /* 9165 */ + IC_EVEX_L_W_XD_B, /* 9166 */ + IC_EVEX_L_W_XD_B, /* 9167 */ + IC_EVEX_L_OPSIZE_B, /* 9168 */ + IC_EVEX_L_OPSIZE_B, /* 9169 */ + IC_EVEX_L_OPSIZE_B, /* 9170 */ + IC_EVEX_L_OPSIZE_B, /* 9171 */ + IC_EVEX_L_OPSIZE_B, /* 9172 */ + IC_EVEX_L_OPSIZE_B, /* 9173 */ + IC_EVEX_L_OPSIZE_B, /* 9174 */ + IC_EVEX_L_OPSIZE_B, /* 9175 */ + IC_EVEX_L_W_OPSIZE_B, /* 9176 */ + IC_EVEX_L_W_OPSIZE_B, /* 9177 */ + IC_EVEX_L_W_OPSIZE_B, /* 9178 */ + IC_EVEX_L_W_OPSIZE_B, /* 9179 */ + IC_EVEX_L_W_OPSIZE_B, /* 9180 */ + IC_EVEX_L_W_OPSIZE_B, /* 9181 */ + IC_EVEX_L_W_OPSIZE_B, /* 9182 */ + IC_EVEX_L_W_OPSIZE_B, /* 9183 */ + IC_EVEX_L_B, /* 9184 */ + IC_EVEX_L_B, /* 9185 */ + IC_EVEX_L_XS_B, /* 9186 */ + IC_EVEX_L_XS_B, /* 9187 */ + IC_EVEX_L_XD_B, /* 9188 */ + IC_EVEX_L_XD_B, /* 9189 */ + IC_EVEX_L_XD_B, /* 9190 */ + IC_EVEX_L_XD_B, /* 9191 */ + IC_EVEX_L_W_B, /* 9192 */ + IC_EVEX_L_W_B, /* 9193 */ + IC_EVEX_L_W_XS_B, /* 9194 */ + IC_EVEX_L_W_XS_B, /* 9195 */ + IC_EVEX_L_W_XD_B, /* 9196 */ + IC_EVEX_L_W_XD_B, /* 9197 */ + IC_EVEX_L_W_XD_B, /* 9198 */ + IC_EVEX_L_W_XD_B, /* 9199 */ + IC_EVEX_L_OPSIZE_B, /* 9200 */ + IC_EVEX_L_OPSIZE_B, /* 9201 */ + IC_EVEX_L_OPSIZE_B, /* 9202 */ + IC_EVEX_L_OPSIZE_B, /* 9203 */ + IC_EVEX_L_OPSIZE_B, /* 9204 */ + IC_EVEX_L_OPSIZE_B, /* 9205 */ + IC_EVEX_L_OPSIZE_B, /* 9206 */ + IC_EVEX_L_OPSIZE_B, /* 9207 */ + IC_EVEX_L_W_OPSIZE_B, /* 9208 */ + IC_EVEX_L_W_OPSIZE_B, /* 9209 */ + IC_EVEX_L_W_OPSIZE_B, /* 9210 */ + IC_EVEX_L_W_OPSIZE_B, /* 9211 */ + IC_EVEX_L_W_OPSIZE_B, /* 9212 */ + IC_EVEX_L_W_OPSIZE_B, /* 9213 */ + IC_EVEX_L_W_OPSIZE_B, /* 9214 */ + IC_EVEX_L_W_OPSIZE_B, /* 9215 */ + IC, /* 9216 */ + IC_64BIT, /* 9217 */ + IC_XS, /* 9218 */ + IC_64BIT_XS, /* 9219 */ + IC_XD, /* 9220 */ + IC_64BIT_XD, /* 9221 */ + IC_XS, /* 9222 */ + IC_64BIT_XS, /* 9223 */ + IC, /* 9224 */ + IC_64BIT_REXW, /* 9225 */ + IC_XS, /* 9226 */ + IC_64BIT_REXW_XS, /* 9227 */ + IC_XD, /* 9228 */ + IC_64BIT_REXW_XD, /* 9229 */ + IC_XS, /* 9230 */ + IC_64BIT_REXW_XS, /* 9231 */ + IC_OPSIZE, /* 9232 */ + IC_64BIT_OPSIZE, /* 9233 */ + IC_XS_OPSIZE, /* 9234 */ + IC_64BIT_XS_OPSIZE, /* 9235 */ + IC_XD_OPSIZE, /* 9236 */ + IC_64BIT_XD_OPSIZE, /* 9237 */ + IC_XS_OPSIZE, /* 9238 */ + IC_64BIT_XD_OPSIZE, /* 9239 */ + IC_OPSIZE, /* 9240 */ + IC_64BIT_REXW_OPSIZE, /* 9241 */ + IC_XS_OPSIZE, /* 9242 */ + IC_64BIT_REXW_XS, /* 9243 */ + IC_XD_OPSIZE, /* 9244 */ + IC_64BIT_REXW_XD, /* 9245 */ + IC_XS_OPSIZE, /* 9246 */ + IC_64BIT_REXW_XS, /* 9247 */ + IC_ADSIZE, /* 9248 */ + IC_64BIT_ADSIZE, /* 9249 */ + IC_XS_ADSIZE, /* 9250 */ + IC_64BIT_XS_ADSIZE, /* 9251 */ + IC_XD_ADSIZE, /* 9252 */ + IC_64BIT_XD_ADSIZE, /* 9253 */ + IC_XS_ADSIZE, /* 9254 */ + IC_64BIT_XD_ADSIZE, /* 9255 */ + IC_ADSIZE, /* 9256 */ + IC_64BIT_REXW_ADSIZE, /* 9257 */ + IC_XS_ADSIZE, /* 9258 */ + IC_64BIT_REXW_XS, /* 9259 */ + IC_XD_ADSIZE, /* 9260 */ + IC_64BIT_REXW_XD, /* 9261 */ + IC_XS_ADSIZE, /* 9262 */ + IC_64BIT_REXW_XS, /* 9263 */ + IC_OPSIZE_ADSIZE, /* 9264 */ + IC_64BIT_OPSIZE_ADSIZE, /* 9265 */ + IC_XS_OPSIZE, /* 9266 */ + IC_64BIT_XS_OPSIZE, /* 9267 */ + IC_XD_OPSIZE, /* 9268 */ + IC_64BIT_XD_OPSIZE, /* 9269 */ + IC_XS_OPSIZE, /* 9270 */ + IC_64BIT_XD_OPSIZE, /* 9271 */ + IC_OPSIZE_ADSIZE, /* 9272 */ + IC_64BIT_REXW_OPSIZE, /* 9273 */ + IC_XS_OPSIZE, /* 9274 */ + IC_64BIT_REXW_XS, /* 9275 */ + IC_XD_OPSIZE, /* 9276 */ + IC_64BIT_REXW_XD, /* 9277 */ + IC_XS_OPSIZE, /* 9278 */ + IC_64BIT_REXW_XS, /* 9279 */ + IC_VEX, /* 9280 */ + IC_VEX, /* 9281 */ + IC_VEX_XS, /* 9282 */ + IC_VEX_XS, /* 9283 */ + IC_VEX_XD, /* 9284 */ + IC_VEX_XD, /* 9285 */ + IC_VEX_XD, /* 9286 */ + IC_VEX_XD, /* 9287 */ + IC_VEX_W, /* 9288 */ + IC_VEX_W, /* 9289 */ + IC_VEX_W_XS, /* 9290 */ + IC_VEX_W_XS, /* 9291 */ + IC_VEX_W_XD, /* 9292 */ + IC_VEX_W_XD, /* 9293 */ + IC_VEX_W_XD, /* 9294 */ + IC_VEX_W_XD, /* 9295 */ + IC_VEX_OPSIZE, /* 9296 */ + IC_VEX_OPSIZE, /* 9297 */ + IC_VEX_OPSIZE, /* 9298 */ + IC_VEX_OPSIZE, /* 9299 */ + IC_VEX_OPSIZE, /* 9300 */ + IC_VEX_OPSIZE, /* 9301 */ + IC_VEX_OPSIZE, /* 9302 */ + IC_VEX_OPSIZE, /* 9303 */ + IC_VEX_W_OPSIZE, /* 9304 */ + IC_VEX_W_OPSIZE, /* 9305 */ + IC_VEX_W_OPSIZE, /* 9306 */ + IC_VEX_W_OPSIZE, /* 9307 */ + IC_VEX_W_OPSIZE, /* 9308 */ + IC_VEX_W_OPSIZE, /* 9309 */ + IC_VEX_W_OPSIZE, /* 9310 */ + IC_VEX_W_OPSIZE, /* 9311 */ + IC_VEX, /* 9312 */ + IC_VEX, /* 9313 */ + IC_VEX_XS, /* 9314 */ + IC_VEX_XS, /* 9315 */ + IC_VEX_XD, /* 9316 */ + IC_VEX_XD, /* 9317 */ + IC_VEX_XD, /* 9318 */ + IC_VEX_XD, /* 9319 */ + IC_VEX_W, /* 9320 */ + IC_VEX_W, /* 9321 */ + IC_VEX_W_XS, /* 9322 */ + IC_VEX_W_XS, /* 9323 */ + IC_VEX_W_XD, /* 9324 */ + IC_VEX_W_XD, /* 9325 */ + IC_VEX_W_XD, /* 9326 */ + IC_VEX_W_XD, /* 9327 */ + IC_VEX_OPSIZE, /* 9328 */ + IC_VEX_OPSIZE, /* 9329 */ + IC_VEX_OPSIZE, /* 9330 */ + IC_VEX_OPSIZE, /* 9331 */ + IC_VEX_OPSIZE, /* 9332 */ + IC_VEX_OPSIZE, /* 9333 */ + IC_VEX_OPSIZE, /* 9334 */ + IC_VEX_OPSIZE, /* 9335 */ + IC_VEX_W_OPSIZE, /* 9336 */ + IC_VEX_W_OPSIZE, /* 9337 */ + IC_VEX_W_OPSIZE, /* 9338 */ + IC_VEX_W_OPSIZE, /* 9339 */ + IC_VEX_W_OPSIZE, /* 9340 */ + IC_VEX_W_OPSIZE, /* 9341 */ + IC_VEX_W_OPSIZE, /* 9342 */ + IC_VEX_W_OPSIZE, /* 9343 */ + IC_VEX_L, /* 9344 */ + IC_VEX_L, /* 9345 */ + IC_VEX_L_XS, /* 9346 */ + IC_VEX_L_XS, /* 9347 */ + IC_VEX_L_XD, /* 9348 */ + IC_VEX_L_XD, /* 9349 */ + IC_VEX_L_XD, /* 9350 */ + IC_VEX_L_XD, /* 9351 */ + IC_VEX_L_W, /* 9352 */ + IC_VEX_L_W, /* 9353 */ + IC_VEX_L_W_XS, /* 9354 */ + IC_VEX_L_W_XS, /* 9355 */ + IC_VEX_L_W_XD, /* 9356 */ + IC_VEX_L_W_XD, /* 9357 */ + IC_VEX_L_W_XD, /* 9358 */ + IC_VEX_L_W_XD, /* 9359 */ + IC_VEX_L_OPSIZE, /* 9360 */ + IC_VEX_L_OPSIZE, /* 9361 */ + IC_VEX_L_OPSIZE, /* 9362 */ + IC_VEX_L_OPSIZE, /* 9363 */ + IC_VEX_L_OPSIZE, /* 9364 */ + IC_VEX_L_OPSIZE, /* 9365 */ + IC_VEX_L_OPSIZE, /* 9366 */ + IC_VEX_L_OPSIZE, /* 9367 */ + IC_VEX_L_W_OPSIZE, /* 9368 */ + IC_VEX_L_W_OPSIZE, /* 9369 */ + IC_VEX_L_W_OPSIZE, /* 9370 */ + IC_VEX_L_W_OPSIZE, /* 9371 */ + IC_VEX_L_W_OPSIZE, /* 9372 */ + IC_VEX_L_W_OPSIZE, /* 9373 */ + IC_VEX_L_W_OPSIZE, /* 9374 */ + IC_VEX_L_W_OPSIZE, /* 9375 */ + IC_VEX_L, /* 9376 */ + IC_VEX_L, /* 9377 */ + IC_VEX_L_XS, /* 9378 */ + IC_VEX_L_XS, /* 9379 */ + IC_VEX_L_XD, /* 9380 */ + IC_VEX_L_XD, /* 9381 */ + IC_VEX_L_XD, /* 9382 */ + IC_VEX_L_XD, /* 9383 */ + IC_VEX_L_W, /* 9384 */ + IC_VEX_L_W, /* 9385 */ + IC_VEX_L_W_XS, /* 9386 */ + IC_VEX_L_W_XS, /* 9387 */ + IC_VEX_L_W_XD, /* 9388 */ + IC_VEX_L_W_XD, /* 9389 */ + IC_VEX_L_W_XD, /* 9390 */ + IC_VEX_L_W_XD, /* 9391 */ + IC_VEX_L_OPSIZE, /* 9392 */ + IC_VEX_L_OPSIZE, /* 9393 */ + IC_VEX_L_OPSIZE, /* 9394 */ + IC_VEX_L_OPSIZE, /* 9395 */ + IC_VEX_L_OPSIZE, /* 9396 */ + IC_VEX_L_OPSIZE, /* 9397 */ + IC_VEX_L_OPSIZE, /* 9398 */ + IC_VEX_L_OPSIZE, /* 9399 */ + IC_VEX_L_W_OPSIZE, /* 9400 */ + IC_VEX_L_W_OPSIZE, /* 9401 */ + IC_VEX_L_W_OPSIZE, /* 9402 */ + IC_VEX_L_W_OPSIZE, /* 9403 */ + IC_VEX_L_W_OPSIZE, /* 9404 */ + IC_VEX_L_W_OPSIZE, /* 9405 */ + IC_VEX_L_W_OPSIZE, /* 9406 */ + IC_VEX_L_W_OPSIZE, /* 9407 */ + IC_VEX_L, /* 9408 */ + IC_VEX_L, /* 9409 */ + IC_VEX_L_XS, /* 9410 */ + IC_VEX_L_XS, /* 9411 */ + IC_VEX_L_XD, /* 9412 */ + IC_VEX_L_XD, /* 9413 */ + IC_VEX_L_XD, /* 9414 */ + IC_VEX_L_XD, /* 9415 */ + IC_VEX_L_W, /* 9416 */ + IC_VEX_L_W, /* 9417 */ + IC_VEX_L_W_XS, /* 9418 */ + IC_VEX_L_W_XS, /* 9419 */ + IC_VEX_L_W_XD, /* 9420 */ + IC_VEX_L_W_XD, /* 9421 */ + IC_VEX_L_W_XD, /* 9422 */ + IC_VEX_L_W_XD, /* 9423 */ + IC_VEX_L_OPSIZE, /* 9424 */ + IC_VEX_L_OPSIZE, /* 9425 */ + IC_VEX_L_OPSIZE, /* 9426 */ + IC_VEX_L_OPSIZE, /* 9427 */ + IC_VEX_L_OPSIZE, /* 9428 */ + IC_VEX_L_OPSIZE, /* 9429 */ + IC_VEX_L_OPSIZE, /* 9430 */ + IC_VEX_L_OPSIZE, /* 9431 */ + IC_VEX_L_W_OPSIZE, /* 9432 */ + IC_VEX_L_W_OPSIZE, /* 9433 */ + IC_VEX_L_W_OPSIZE, /* 9434 */ + IC_VEX_L_W_OPSIZE, /* 9435 */ + IC_VEX_L_W_OPSIZE, /* 9436 */ + IC_VEX_L_W_OPSIZE, /* 9437 */ + IC_VEX_L_W_OPSIZE, /* 9438 */ + IC_VEX_L_W_OPSIZE, /* 9439 */ + IC_VEX_L, /* 9440 */ + IC_VEX_L, /* 9441 */ + IC_VEX_L_XS, /* 9442 */ + IC_VEX_L_XS, /* 9443 */ + IC_VEX_L_XD, /* 9444 */ + IC_VEX_L_XD, /* 9445 */ + IC_VEX_L_XD, /* 9446 */ + IC_VEX_L_XD, /* 9447 */ + IC_VEX_L_W, /* 9448 */ + IC_VEX_L_W, /* 9449 */ + IC_VEX_L_W_XS, /* 9450 */ + IC_VEX_L_W_XS, /* 9451 */ + IC_VEX_L_W_XD, /* 9452 */ + IC_VEX_L_W_XD, /* 9453 */ + IC_VEX_L_W_XD, /* 9454 */ + IC_VEX_L_W_XD, /* 9455 */ + IC_VEX_L_OPSIZE, /* 9456 */ + IC_VEX_L_OPSIZE, /* 9457 */ + IC_VEX_L_OPSIZE, /* 9458 */ + IC_VEX_L_OPSIZE, /* 9459 */ + IC_VEX_L_OPSIZE, /* 9460 */ + IC_VEX_L_OPSIZE, /* 9461 */ + IC_VEX_L_OPSIZE, /* 9462 */ + IC_VEX_L_OPSIZE, /* 9463 */ + IC_VEX_L_W_OPSIZE, /* 9464 */ + IC_VEX_L_W_OPSIZE, /* 9465 */ + IC_VEX_L_W_OPSIZE, /* 9466 */ + IC_VEX_L_W_OPSIZE, /* 9467 */ + IC_VEX_L_W_OPSIZE, /* 9468 */ + IC_VEX_L_W_OPSIZE, /* 9469 */ + IC_VEX_L_W_OPSIZE, /* 9470 */ + IC_VEX_L_W_OPSIZE, /* 9471 */ + IC_EVEX_L2_B, /* 9472 */ + IC_EVEX_L2_B, /* 9473 */ + IC_EVEX_L2_XS_B, /* 9474 */ + IC_EVEX_L2_XS_B, /* 9475 */ + IC_EVEX_L2_XD_B, /* 9476 */ + IC_EVEX_L2_XD_B, /* 9477 */ + IC_EVEX_L2_XD_B, /* 9478 */ + IC_EVEX_L2_XD_B, /* 9479 */ + IC_EVEX_L2_W_B, /* 9480 */ + IC_EVEX_L2_W_B, /* 9481 */ + IC_EVEX_L2_W_XS_B, /* 9482 */ + IC_EVEX_L2_W_XS_B, /* 9483 */ + IC_EVEX_L2_W_XD_B, /* 9484 */ + IC_EVEX_L2_W_XD_B, /* 9485 */ + IC_EVEX_L2_W_XD_B, /* 9486 */ + IC_EVEX_L2_W_XD_B, /* 9487 */ + IC_EVEX_L2_OPSIZE_B, /* 9488 */ + IC_EVEX_L2_OPSIZE_B, /* 9489 */ + IC_EVEX_L2_OPSIZE_B, /* 9490 */ + IC_EVEX_L2_OPSIZE_B, /* 9491 */ + IC_EVEX_L2_OPSIZE_B, /* 9492 */ + IC_EVEX_L2_OPSIZE_B, /* 9493 */ + IC_EVEX_L2_OPSIZE_B, /* 9494 */ + IC_EVEX_L2_OPSIZE_B, /* 9495 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9496 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9497 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9498 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9499 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9500 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9501 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9502 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9503 */ + IC_EVEX_L2_B, /* 9504 */ + IC_EVEX_L2_B, /* 9505 */ + IC_EVEX_L2_XS_B, /* 9506 */ + IC_EVEX_L2_XS_B, /* 9507 */ + IC_EVEX_L2_XD_B, /* 9508 */ + IC_EVEX_L2_XD_B, /* 9509 */ + IC_EVEX_L2_XD_B, /* 9510 */ + IC_EVEX_L2_XD_B, /* 9511 */ + IC_EVEX_L2_W_B, /* 9512 */ + IC_EVEX_L2_W_B, /* 9513 */ + IC_EVEX_L2_W_XS_B, /* 9514 */ + IC_EVEX_L2_W_XS_B, /* 9515 */ + IC_EVEX_L2_W_XD_B, /* 9516 */ + IC_EVEX_L2_W_XD_B, /* 9517 */ + IC_EVEX_L2_W_XD_B, /* 9518 */ + IC_EVEX_L2_W_XD_B, /* 9519 */ + IC_EVEX_L2_OPSIZE_B, /* 9520 */ + IC_EVEX_L2_OPSIZE_B, /* 9521 */ + IC_EVEX_L2_OPSIZE_B, /* 9522 */ + IC_EVEX_L2_OPSIZE_B, /* 9523 */ + IC_EVEX_L2_OPSIZE_B, /* 9524 */ + IC_EVEX_L2_OPSIZE_B, /* 9525 */ + IC_EVEX_L2_OPSIZE_B, /* 9526 */ + IC_EVEX_L2_OPSIZE_B, /* 9527 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9528 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9529 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9530 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9531 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9532 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9533 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9534 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9535 */ + IC_EVEX_L2_B, /* 9536 */ + IC_EVEX_L2_B, /* 9537 */ + IC_EVEX_L2_XS_B, /* 9538 */ + IC_EVEX_L2_XS_B, /* 9539 */ + IC_EVEX_L2_XD_B, /* 9540 */ + IC_EVEX_L2_XD_B, /* 9541 */ + IC_EVEX_L2_XD_B, /* 9542 */ + IC_EVEX_L2_XD_B, /* 9543 */ + IC_EVEX_L2_W_B, /* 9544 */ + IC_EVEX_L2_W_B, /* 9545 */ + IC_EVEX_L2_W_XS_B, /* 9546 */ + IC_EVEX_L2_W_XS_B, /* 9547 */ + IC_EVEX_L2_W_XD_B, /* 9548 */ + IC_EVEX_L2_W_XD_B, /* 9549 */ + IC_EVEX_L2_W_XD_B, /* 9550 */ + IC_EVEX_L2_W_XD_B, /* 9551 */ + IC_EVEX_L2_OPSIZE_B, /* 9552 */ + IC_EVEX_L2_OPSIZE_B, /* 9553 */ + IC_EVEX_L2_OPSIZE_B, /* 9554 */ + IC_EVEX_L2_OPSIZE_B, /* 9555 */ + IC_EVEX_L2_OPSIZE_B, /* 9556 */ + IC_EVEX_L2_OPSIZE_B, /* 9557 */ + IC_EVEX_L2_OPSIZE_B, /* 9558 */ + IC_EVEX_L2_OPSIZE_B, /* 9559 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9560 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9561 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9562 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9563 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9564 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9565 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9566 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9567 */ + IC_EVEX_L2_B, /* 9568 */ + IC_EVEX_L2_B, /* 9569 */ + IC_EVEX_L2_XS_B, /* 9570 */ + IC_EVEX_L2_XS_B, /* 9571 */ + IC_EVEX_L2_XD_B, /* 9572 */ + IC_EVEX_L2_XD_B, /* 9573 */ + IC_EVEX_L2_XD_B, /* 9574 */ + IC_EVEX_L2_XD_B, /* 9575 */ + IC_EVEX_L2_W_B, /* 9576 */ + IC_EVEX_L2_W_B, /* 9577 */ + IC_EVEX_L2_W_XS_B, /* 9578 */ + IC_EVEX_L2_W_XS_B, /* 9579 */ + IC_EVEX_L2_W_XD_B, /* 9580 */ + IC_EVEX_L2_W_XD_B, /* 9581 */ + IC_EVEX_L2_W_XD_B, /* 9582 */ + IC_EVEX_L2_W_XD_B, /* 9583 */ + IC_EVEX_L2_OPSIZE_B, /* 9584 */ + IC_EVEX_L2_OPSIZE_B, /* 9585 */ + IC_EVEX_L2_OPSIZE_B, /* 9586 */ + IC_EVEX_L2_OPSIZE_B, /* 9587 */ + IC_EVEX_L2_OPSIZE_B, /* 9588 */ + IC_EVEX_L2_OPSIZE_B, /* 9589 */ + IC_EVEX_L2_OPSIZE_B, /* 9590 */ + IC_EVEX_L2_OPSIZE_B, /* 9591 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9592 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9593 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9594 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9595 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9596 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9597 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9598 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9599 */ + IC_EVEX_L2_B, /* 9600 */ + IC_EVEX_L2_B, /* 9601 */ + IC_EVEX_L2_XS_B, /* 9602 */ + IC_EVEX_L2_XS_B, /* 9603 */ + IC_EVEX_L2_XD_B, /* 9604 */ + IC_EVEX_L2_XD_B, /* 9605 */ + IC_EVEX_L2_XD_B, /* 9606 */ + IC_EVEX_L2_XD_B, /* 9607 */ + IC_EVEX_L2_W_B, /* 9608 */ + IC_EVEX_L2_W_B, /* 9609 */ + IC_EVEX_L2_W_XS_B, /* 9610 */ + IC_EVEX_L2_W_XS_B, /* 9611 */ + IC_EVEX_L2_W_XD_B, /* 9612 */ + IC_EVEX_L2_W_XD_B, /* 9613 */ + IC_EVEX_L2_W_XD_B, /* 9614 */ + IC_EVEX_L2_W_XD_B, /* 9615 */ + IC_EVEX_L2_OPSIZE_B, /* 9616 */ + IC_EVEX_L2_OPSIZE_B, /* 9617 */ + IC_EVEX_L2_OPSIZE_B, /* 9618 */ + IC_EVEX_L2_OPSIZE_B, /* 9619 */ + IC_EVEX_L2_OPSIZE_B, /* 9620 */ + IC_EVEX_L2_OPSIZE_B, /* 9621 */ + IC_EVEX_L2_OPSIZE_B, /* 9622 */ + IC_EVEX_L2_OPSIZE_B, /* 9623 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9624 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9625 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9626 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9627 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9628 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9629 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9630 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9631 */ + IC_EVEX_L2_B, /* 9632 */ + IC_EVEX_L2_B, /* 9633 */ + IC_EVEX_L2_XS_B, /* 9634 */ + IC_EVEX_L2_XS_B, /* 9635 */ + IC_EVEX_L2_XD_B, /* 9636 */ + IC_EVEX_L2_XD_B, /* 9637 */ + IC_EVEX_L2_XD_B, /* 9638 */ + IC_EVEX_L2_XD_B, /* 9639 */ + IC_EVEX_L2_W_B, /* 9640 */ + IC_EVEX_L2_W_B, /* 9641 */ + IC_EVEX_L2_W_XS_B, /* 9642 */ + IC_EVEX_L2_W_XS_B, /* 9643 */ + IC_EVEX_L2_W_XD_B, /* 9644 */ + IC_EVEX_L2_W_XD_B, /* 9645 */ + IC_EVEX_L2_W_XD_B, /* 9646 */ + IC_EVEX_L2_W_XD_B, /* 9647 */ + IC_EVEX_L2_OPSIZE_B, /* 9648 */ + IC_EVEX_L2_OPSIZE_B, /* 9649 */ + IC_EVEX_L2_OPSIZE_B, /* 9650 */ + IC_EVEX_L2_OPSIZE_B, /* 9651 */ + IC_EVEX_L2_OPSIZE_B, /* 9652 */ + IC_EVEX_L2_OPSIZE_B, /* 9653 */ + IC_EVEX_L2_OPSIZE_B, /* 9654 */ + IC_EVEX_L2_OPSIZE_B, /* 9655 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9656 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9657 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9658 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9659 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9660 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9661 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9662 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9663 */ + IC_EVEX_L2_B, /* 9664 */ + IC_EVEX_L2_B, /* 9665 */ + IC_EVEX_L2_XS_B, /* 9666 */ + IC_EVEX_L2_XS_B, /* 9667 */ + IC_EVEX_L2_XD_B, /* 9668 */ + IC_EVEX_L2_XD_B, /* 9669 */ + IC_EVEX_L2_XD_B, /* 9670 */ + IC_EVEX_L2_XD_B, /* 9671 */ + IC_EVEX_L2_W_B, /* 9672 */ + IC_EVEX_L2_W_B, /* 9673 */ + IC_EVEX_L2_W_XS_B, /* 9674 */ + IC_EVEX_L2_W_XS_B, /* 9675 */ + IC_EVEX_L2_W_XD_B, /* 9676 */ + IC_EVEX_L2_W_XD_B, /* 9677 */ + IC_EVEX_L2_W_XD_B, /* 9678 */ + IC_EVEX_L2_W_XD_B, /* 9679 */ + IC_EVEX_L2_OPSIZE_B, /* 9680 */ + IC_EVEX_L2_OPSIZE_B, /* 9681 */ + IC_EVEX_L2_OPSIZE_B, /* 9682 */ + IC_EVEX_L2_OPSIZE_B, /* 9683 */ + IC_EVEX_L2_OPSIZE_B, /* 9684 */ + IC_EVEX_L2_OPSIZE_B, /* 9685 */ + IC_EVEX_L2_OPSIZE_B, /* 9686 */ + IC_EVEX_L2_OPSIZE_B, /* 9687 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9688 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9689 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9690 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9691 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9692 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9693 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9694 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9695 */ + IC_EVEX_L2_B, /* 9696 */ + IC_EVEX_L2_B, /* 9697 */ + IC_EVEX_L2_XS_B, /* 9698 */ + IC_EVEX_L2_XS_B, /* 9699 */ + IC_EVEX_L2_XD_B, /* 9700 */ + IC_EVEX_L2_XD_B, /* 9701 */ + IC_EVEX_L2_XD_B, /* 9702 */ + IC_EVEX_L2_XD_B, /* 9703 */ + IC_EVEX_L2_W_B, /* 9704 */ + IC_EVEX_L2_W_B, /* 9705 */ + IC_EVEX_L2_W_XS_B, /* 9706 */ + IC_EVEX_L2_W_XS_B, /* 9707 */ + IC_EVEX_L2_W_XD_B, /* 9708 */ + IC_EVEX_L2_W_XD_B, /* 9709 */ + IC_EVEX_L2_W_XD_B, /* 9710 */ + IC_EVEX_L2_W_XD_B, /* 9711 */ + IC_EVEX_L2_OPSIZE_B, /* 9712 */ + IC_EVEX_L2_OPSIZE_B, /* 9713 */ + IC_EVEX_L2_OPSIZE_B, /* 9714 */ + IC_EVEX_L2_OPSIZE_B, /* 9715 */ + IC_EVEX_L2_OPSIZE_B, /* 9716 */ + IC_EVEX_L2_OPSIZE_B, /* 9717 */ + IC_EVEX_L2_OPSIZE_B, /* 9718 */ + IC_EVEX_L2_OPSIZE_B, /* 9719 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9720 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9721 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9722 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9723 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9724 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9725 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9726 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9727 */ + IC, /* 9728 */ + IC_64BIT, /* 9729 */ + IC_XS, /* 9730 */ + IC_64BIT_XS, /* 9731 */ + IC_XD, /* 9732 */ + IC_64BIT_XD, /* 9733 */ + IC_XS, /* 9734 */ + IC_64BIT_XS, /* 9735 */ + IC, /* 9736 */ + IC_64BIT_REXW, /* 9737 */ + IC_XS, /* 9738 */ + IC_64BIT_REXW_XS, /* 9739 */ + IC_XD, /* 9740 */ + IC_64BIT_REXW_XD, /* 9741 */ + IC_XS, /* 9742 */ + IC_64BIT_REXW_XS, /* 9743 */ + IC_OPSIZE, /* 9744 */ + IC_64BIT_OPSIZE, /* 9745 */ + IC_XS_OPSIZE, /* 9746 */ + IC_64BIT_XS_OPSIZE, /* 9747 */ + IC_XD_OPSIZE, /* 9748 */ + IC_64BIT_XD_OPSIZE, /* 9749 */ + IC_XS_OPSIZE, /* 9750 */ + IC_64BIT_XD_OPSIZE, /* 9751 */ + IC_OPSIZE, /* 9752 */ + IC_64BIT_REXW_OPSIZE, /* 9753 */ + IC_XS_OPSIZE, /* 9754 */ + IC_64BIT_REXW_XS, /* 9755 */ + IC_XD_OPSIZE, /* 9756 */ + IC_64BIT_REXW_XD, /* 9757 */ + IC_XS_OPSIZE, /* 9758 */ + IC_64BIT_REXW_XS, /* 9759 */ + IC_ADSIZE, /* 9760 */ + IC_64BIT_ADSIZE, /* 9761 */ + IC_XS_ADSIZE, /* 9762 */ + IC_64BIT_XS_ADSIZE, /* 9763 */ + IC_XD_ADSIZE, /* 9764 */ + IC_64BIT_XD_ADSIZE, /* 9765 */ + IC_XS_ADSIZE, /* 9766 */ + IC_64BIT_XD_ADSIZE, /* 9767 */ + IC_ADSIZE, /* 9768 */ + IC_64BIT_REXW_ADSIZE, /* 9769 */ + IC_XS_ADSIZE, /* 9770 */ + IC_64BIT_REXW_XS, /* 9771 */ + IC_XD_ADSIZE, /* 9772 */ + IC_64BIT_REXW_XD, /* 9773 */ + IC_XS_ADSIZE, /* 9774 */ + IC_64BIT_REXW_XS, /* 9775 */ + IC_OPSIZE_ADSIZE, /* 9776 */ + IC_64BIT_OPSIZE_ADSIZE, /* 9777 */ + IC_XS_OPSIZE, /* 9778 */ + IC_64BIT_XS_OPSIZE, /* 9779 */ + IC_XD_OPSIZE, /* 9780 */ + IC_64BIT_XD_OPSIZE, /* 9781 */ + IC_XS_OPSIZE, /* 9782 */ + IC_64BIT_XD_OPSIZE, /* 9783 */ + IC_OPSIZE_ADSIZE, /* 9784 */ + IC_64BIT_REXW_OPSIZE, /* 9785 */ + IC_XS_OPSIZE, /* 9786 */ + IC_64BIT_REXW_XS, /* 9787 */ + IC_XD_OPSIZE, /* 9788 */ + IC_64BIT_REXW_XD, /* 9789 */ + IC_XS_OPSIZE, /* 9790 */ + IC_64BIT_REXW_XS, /* 9791 */ + IC_VEX, /* 9792 */ + IC_VEX, /* 9793 */ + IC_VEX_XS, /* 9794 */ + IC_VEX_XS, /* 9795 */ + IC_VEX_XD, /* 9796 */ + IC_VEX_XD, /* 9797 */ + IC_VEX_XD, /* 9798 */ + IC_VEX_XD, /* 9799 */ + IC_VEX_W, /* 9800 */ + IC_VEX_W, /* 9801 */ + IC_VEX_W_XS, /* 9802 */ + IC_VEX_W_XS, /* 9803 */ + IC_VEX_W_XD, /* 9804 */ + IC_VEX_W_XD, /* 9805 */ + IC_VEX_W_XD, /* 9806 */ + IC_VEX_W_XD, /* 9807 */ + IC_VEX_OPSIZE, /* 9808 */ + IC_VEX_OPSIZE, /* 9809 */ + IC_VEX_OPSIZE, /* 9810 */ + IC_VEX_OPSIZE, /* 9811 */ + IC_VEX_OPSIZE, /* 9812 */ + IC_VEX_OPSIZE, /* 9813 */ + IC_VEX_OPSIZE, /* 9814 */ + IC_VEX_OPSIZE, /* 9815 */ + IC_VEX_W_OPSIZE, /* 9816 */ + IC_VEX_W_OPSIZE, /* 9817 */ + IC_VEX_W_OPSIZE, /* 9818 */ + IC_VEX_W_OPSIZE, /* 9819 */ + IC_VEX_W_OPSIZE, /* 9820 */ + IC_VEX_W_OPSIZE, /* 9821 */ + IC_VEX_W_OPSIZE, /* 9822 */ + IC_VEX_W_OPSIZE, /* 9823 */ + IC_VEX, /* 9824 */ + IC_VEX, /* 9825 */ + IC_VEX_XS, /* 9826 */ + IC_VEX_XS, /* 9827 */ + IC_VEX_XD, /* 9828 */ + IC_VEX_XD, /* 9829 */ + IC_VEX_XD, /* 9830 */ + IC_VEX_XD, /* 9831 */ + IC_VEX_W, /* 9832 */ + IC_VEX_W, /* 9833 */ + IC_VEX_W_XS, /* 9834 */ + IC_VEX_W_XS, /* 9835 */ + IC_VEX_W_XD, /* 9836 */ + IC_VEX_W_XD, /* 9837 */ + IC_VEX_W_XD, /* 9838 */ + IC_VEX_W_XD, /* 9839 */ + IC_VEX_OPSIZE, /* 9840 */ + IC_VEX_OPSIZE, /* 9841 */ + IC_VEX_OPSIZE, /* 9842 */ + IC_VEX_OPSIZE, /* 9843 */ + IC_VEX_OPSIZE, /* 9844 */ + IC_VEX_OPSIZE, /* 9845 */ + IC_VEX_OPSIZE, /* 9846 */ + IC_VEX_OPSIZE, /* 9847 */ + IC_VEX_W_OPSIZE, /* 9848 */ + IC_VEX_W_OPSIZE, /* 9849 */ + IC_VEX_W_OPSIZE, /* 9850 */ + IC_VEX_W_OPSIZE, /* 9851 */ + IC_VEX_W_OPSIZE, /* 9852 */ + IC_VEX_W_OPSIZE, /* 9853 */ + IC_VEX_W_OPSIZE, /* 9854 */ + IC_VEX_W_OPSIZE, /* 9855 */ + IC_VEX_L, /* 9856 */ + IC_VEX_L, /* 9857 */ + IC_VEX_L_XS, /* 9858 */ + IC_VEX_L_XS, /* 9859 */ + IC_VEX_L_XD, /* 9860 */ + IC_VEX_L_XD, /* 9861 */ + IC_VEX_L_XD, /* 9862 */ + IC_VEX_L_XD, /* 9863 */ + IC_VEX_L_W, /* 9864 */ + IC_VEX_L_W, /* 9865 */ + IC_VEX_L_W_XS, /* 9866 */ + IC_VEX_L_W_XS, /* 9867 */ + IC_VEX_L_W_XD, /* 9868 */ + IC_VEX_L_W_XD, /* 9869 */ + IC_VEX_L_W_XD, /* 9870 */ + IC_VEX_L_W_XD, /* 9871 */ + IC_VEX_L_OPSIZE, /* 9872 */ + IC_VEX_L_OPSIZE, /* 9873 */ + IC_VEX_L_OPSIZE, /* 9874 */ + IC_VEX_L_OPSIZE, /* 9875 */ + IC_VEX_L_OPSIZE, /* 9876 */ + IC_VEX_L_OPSIZE, /* 9877 */ + IC_VEX_L_OPSIZE, /* 9878 */ + IC_VEX_L_OPSIZE, /* 9879 */ + IC_VEX_L_W_OPSIZE, /* 9880 */ + IC_VEX_L_W_OPSIZE, /* 9881 */ + IC_VEX_L_W_OPSIZE, /* 9882 */ + IC_VEX_L_W_OPSIZE, /* 9883 */ + IC_VEX_L_W_OPSIZE, /* 9884 */ + IC_VEX_L_W_OPSIZE, /* 9885 */ + IC_VEX_L_W_OPSIZE, /* 9886 */ + IC_VEX_L_W_OPSIZE, /* 9887 */ + IC_VEX_L, /* 9888 */ + IC_VEX_L, /* 9889 */ + IC_VEX_L_XS, /* 9890 */ + IC_VEX_L_XS, /* 9891 */ + IC_VEX_L_XD, /* 9892 */ + IC_VEX_L_XD, /* 9893 */ + IC_VEX_L_XD, /* 9894 */ + IC_VEX_L_XD, /* 9895 */ + IC_VEX_L_W, /* 9896 */ + IC_VEX_L_W, /* 9897 */ + IC_VEX_L_W_XS, /* 9898 */ + IC_VEX_L_W_XS, /* 9899 */ + IC_VEX_L_W_XD, /* 9900 */ + IC_VEX_L_W_XD, /* 9901 */ + IC_VEX_L_W_XD, /* 9902 */ + IC_VEX_L_W_XD, /* 9903 */ + IC_VEX_L_OPSIZE, /* 9904 */ + IC_VEX_L_OPSIZE, /* 9905 */ + IC_VEX_L_OPSIZE, /* 9906 */ + IC_VEX_L_OPSIZE, /* 9907 */ + IC_VEX_L_OPSIZE, /* 9908 */ + IC_VEX_L_OPSIZE, /* 9909 */ + IC_VEX_L_OPSIZE, /* 9910 */ + IC_VEX_L_OPSIZE, /* 9911 */ + IC_VEX_L_W_OPSIZE, /* 9912 */ + IC_VEX_L_W_OPSIZE, /* 9913 */ + IC_VEX_L_W_OPSIZE, /* 9914 */ + IC_VEX_L_W_OPSIZE, /* 9915 */ + IC_VEX_L_W_OPSIZE, /* 9916 */ + IC_VEX_L_W_OPSIZE, /* 9917 */ + IC_VEX_L_W_OPSIZE, /* 9918 */ + IC_VEX_L_W_OPSIZE, /* 9919 */ + IC_VEX_L, /* 9920 */ + IC_VEX_L, /* 9921 */ + IC_VEX_L_XS, /* 9922 */ + IC_VEX_L_XS, /* 9923 */ + IC_VEX_L_XD, /* 9924 */ + IC_VEX_L_XD, /* 9925 */ + IC_VEX_L_XD, /* 9926 */ + IC_VEX_L_XD, /* 9927 */ + IC_VEX_L_W, /* 9928 */ + IC_VEX_L_W, /* 9929 */ + IC_VEX_L_W_XS, /* 9930 */ + IC_VEX_L_W_XS, /* 9931 */ + IC_VEX_L_W_XD, /* 9932 */ + IC_VEX_L_W_XD, /* 9933 */ + IC_VEX_L_W_XD, /* 9934 */ + IC_VEX_L_W_XD, /* 9935 */ + IC_VEX_L_OPSIZE, /* 9936 */ + IC_VEX_L_OPSIZE, /* 9937 */ + IC_VEX_L_OPSIZE, /* 9938 */ + IC_VEX_L_OPSIZE, /* 9939 */ + IC_VEX_L_OPSIZE, /* 9940 */ + IC_VEX_L_OPSIZE, /* 9941 */ + IC_VEX_L_OPSIZE, /* 9942 */ + IC_VEX_L_OPSIZE, /* 9943 */ + IC_VEX_L_W_OPSIZE, /* 9944 */ + IC_VEX_L_W_OPSIZE, /* 9945 */ + IC_VEX_L_W_OPSIZE, /* 9946 */ + IC_VEX_L_W_OPSIZE, /* 9947 */ + IC_VEX_L_W_OPSIZE, /* 9948 */ + IC_VEX_L_W_OPSIZE, /* 9949 */ + IC_VEX_L_W_OPSIZE, /* 9950 */ + IC_VEX_L_W_OPSIZE, /* 9951 */ + IC_VEX_L, /* 9952 */ + IC_VEX_L, /* 9953 */ + IC_VEX_L_XS, /* 9954 */ + IC_VEX_L_XS, /* 9955 */ + IC_VEX_L_XD, /* 9956 */ + IC_VEX_L_XD, /* 9957 */ + IC_VEX_L_XD, /* 9958 */ + IC_VEX_L_XD, /* 9959 */ + IC_VEX_L_W, /* 9960 */ + IC_VEX_L_W, /* 9961 */ + IC_VEX_L_W_XS, /* 9962 */ + IC_VEX_L_W_XS, /* 9963 */ + IC_VEX_L_W_XD, /* 9964 */ + IC_VEX_L_W_XD, /* 9965 */ + IC_VEX_L_W_XD, /* 9966 */ + IC_VEX_L_W_XD, /* 9967 */ + IC_VEX_L_OPSIZE, /* 9968 */ + IC_VEX_L_OPSIZE, /* 9969 */ + IC_VEX_L_OPSIZE, /* 9970 */ + IC_VEX_L_OPSIZE, /* 9971 */ + IC_VEX_L_OPSIZE, /* 9972 */ + IC_VEX_L_OPSIZE, /* 9973 */ + IC_VEX_L_OPSIZE, /* 9974 */ + IC_VEX_L_OPSIZE, /* 9975 */ + IC_VEX_L_W_OPSIZE, /* 9976 */ + IC_VEX_L_W_OPSIZE, /* 9977 */ + IC_VEX_L_W_OPSIZE, /* 9978 */ + IC_VEX_L_W_OPSIZE, /* 9979 */ + IC_VEX_L_W_OPSIZE, /* 9980 */ + IC_VEX_L_W_OPSIZE, /* 9981 */ + IC_VEX_L_W_OPSIZE, /* 9982 */ + IC_VEX_L_W_OPSIZE, /* 9983 */ + IC_EVEX_L2_B, /* 9984 */ + IC_EVEX_L2_B, /* 9985 */ + IC_EVEX_L2_XS_B, /* 9986 */ + IC_EVEX_L2_XS_B, /* 9987 */ + IC_EVEX_L2_XD_B, /* 9988 */ + IC_EVEX_L2_XD_B, /* 9989 */ + IC_EVEX_L2_XD_B, /* 9990 */ + IC_EVEX_L2_XD_B, /* 9991 */ + IC_EVEX_L2_W_B, /* 9992 */ + IC_EVEX_L2_W_B, /* 9993 */ + IC_EVEX_L2_W_XS_B, /* 9994 */ + IC_EVEX_L2_W_XS_B, /* 9995 */ + IC_EVEX_L2_W_XD_B, /* 9996 */ + IC_EVEX_L2_W_XD_B, /* 9997 */ + IC_EVEX_L2_W_XD_B, /* 9998 */ + IC_EVEX_L2_W_XD_B, /* 9999 */ + IC_EVEX_L2_OPSIZE_B, /* 10000 */ + IC_EVEX_L2_OPSIZE_B, /* 10001 */ + IC_EVEX_L2_OPSIZE_B, /* 10002 */ + IC_EVEX_L2_OPSIZE_B, /* 10003 */ + IC_EVEX_L2_OPSIZE_B, /* 10004 */ + IC_EVEX_L2_OPSIZE_B, /* 10005 */ + IC_EVEX_L2_OPSIZE_B, /* 10006 */ + IC_EVEX_L2_OPSIZE_B, /* 10007 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10008 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10009 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10010 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10011 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10012 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10013 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10014 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10015 */ + IC_EVEX_L2_B, /* 10016 */ + IC_EVEX_L2_B, /* 10017 */ + IC_EVEX_L2_XS_B, /* 10018 */ + IC_EVEX_L2_XS_B, /* 10019 */ + IC_EVEX_L2_XD_B, /* 10020 */ + IC_EVEX_L2_XD_B, /* 10021 */ + IC_EVEX_L2_XD_B, /* 10022 */ + IC_EVEX_L2_XD_B, /* 10023 */ + IC_EVEX_L2_W_B, /* 10024 */ + IC_EVEX_L2_W_B, /* 10025 */ + IC_EVEX_L2_W_XS_B, /* 10026 */ + IC_EVEX_L2_W_XS_B, /* 10027 */ + IC_EVEX_L2_W_XD_B, /* 10028 */ + IC_EVEX_L2_W_XD_B, /* 10029 */ + IC_EVEX_L2_W_XD_B, /* 10030 */ + IC_EVEX_L2_W_XD_B, /* 10031 */ + IC_EVEX_L2_OPSIZE_B, /* 10032 */ + IC_EVEX_L2_OPSIZE_B, /* 10033 */ + IC_EVEX_L2_OPSIZE_B, /* 10034 */ + IC_EVEX_L2_OPSIZE_B, /* 10035 */ + IC_EVEX_L2_OPSIZE_B, /* 10036 */ + IC_EVEX_L2_OPSIZE_B, /* 10037 */ + IC_EVEX_L2_OPSIZE_B, /* 10038 */ + IC_EVEX_L2_OPSIZE_B, /* 10039 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10040 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10041 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10042 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10043 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10044 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10045 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10046 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10047 */ + IC_EVEX_L2_B, /* 10048 */ + IC_EVEX_L2_B, /* 10049 */ + IC_EVEX_L2_XS_B, /* 10050 */ + IC_EVEX_L2_XS_B, /* 10051 */ + IC_EVEX_L2_XD_B, /* 10052 */ + IC_EVEX_L2_XD_B, /* 10053 */ + IC_EVEX_L2_XD_B, /* 10054 */ + IC_EVEX_L2_XD_B, /* 10055 */ + IC_EVEX_L2_W_B, /* 10056 */ + IC_EVEX_L2_W_B, /* 10057 */ + IC_EVEX_L2_W_XS_B, /* 10058 */ + IC_EVEX_L2_W_XS_B, /* 10059 */ + IC_EVEX_L2_W_XD_B, /* 10060 */ + IC_EVEX_L2_W_XD_B, /* 10061 */ + IC_EVEX_L2_W_XD_B, /* 10062 */ + IC_EVEX_L2_W_XD_B, /* 10063 */ + IC_EVEX_L2_OPSIZE_B, /* 10064 */ + IC_EVEX_L2_OPSIZE_B, /* 10065 */ + IC_EVEX_L2_OPSIZE_B, /* 10066 */ + IC_EVEX_L2_OPSIZE_B, /* 10067 */ + IC_EVEX_L2_OPSIZE_B, /* 10068 */ + IC_EVEX_L2_OPSIZE_B, /* 10069 */ + IC_EVEX_L2_OPSIZE_B, /* 10070 */ + IC_EVEX_L2_OPSIZE_B, /* 10071 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10072 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10073 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10074 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10075 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10076 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10077 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10078 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10079 */ + IC_EVEX_L2_B, /* 10080 */ + IC_EVEX_L2_B, /* 10081 */ + IC_EVEX_L2_XS_B, /* 10082 */ + IC_EVEX_L2_XS_B, /* 10083 */ + IC_EVEX_L2_XD_B, /* 10084 */ + IC_EVEX_L2_XD_B, /* 10085 */ + IC_EVEX_L2_XD_B, /* 10086 */ + IC_EVEX_L2_XD_B, /* 10087 */ + IC_EVEX_L2_W_B, /* 10088 */ + IC_EVEX_L2_W_B, /* 10089 */ + IC_EVEX_L2_W_XS_B, /* 10090 */ + IC_EVEX_L2_W_XS_B, /* 10091 */ + IC_EVEX_L2_W_XD_B, /* 10092 */ + IC_EVEX_L2_W_XD_B, /* 10093 */ + IC_EVEX_L2_W_XD_B, /* 10094 */ + IC_EVEX_L2_W_XD_B, /* 10095 */ + IC_EVEX_L2_OPSIZE_B, /* 10096 */ + IC_EVEX_L2_OPSIZE_B, /* 10097 */ + IC_EVEX_L2_OPSIZE_B, /* 10098 */ + IC_EVEX_L2_OPSIZE_B, /* 10099 */ + IC_EVEX_L2_OPSIZE_B, /* 10100 */ + IC_EVEX_L2_OPSIZE_B, /* 10101 */ + IC_EVEX_L2_OPSIZE_B, /* 10102 */ + IC_EVEX_L2_OPSIZE_B, /* 10103 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10104 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10105 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10106 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10107 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10108 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10109 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10110 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10111 */ + IC_EVEX_L2_B, /* 10112 */ + IC_EVEX_L2_B, /* 10113 */ + IC_EVEX_L2_XS_B, /* 10114 */ + IC_EVEX_L2_XS_B, /* 10115 */ + IC_EVEX_L2_XD_B, /* 10116 */ + IC_EVEX_L2_XD_B, /* 10117 */ + IC_EVEX_L2_XD_B, /* 10118 */ + IC_EVEX_L2_XD_B, /* 10119 */ + IC_EVEX_L2_W_B, /* 10120 */ + IC_EVEX_L2_W_B, /* 10121 */ + IC_EVEX_L2_W_XS_B, /* 10122 */ + IC_EVEX_L2_W_XS_B, /* 10123 */ + IC_EVEX_L2_W_XD_B, /* 10124 */ + IC_EVEX_L2_W_XD_B, /* 10125 */ + IC_EVEX_L2_W_XD_B, /* 10126 */ + IC_EVEX_L2_W_XD_B, /* 10127 */ + IC_EVEX_L2_OPSIZE_B, /* 10128 */ + IC_EVEX_L2_OPSIZE_B, /* 10129 */ + IC_EVEX_L2_OPSIZE_B, /* 10130 */ + IC_EVEX_L2_OPSIZE_B, /* 10131 */ + IC_EVEX_L2_OPSIZE_B, /* 10132 */ + IC_EVEX_L2_OPSIZE_B, /* 10133 */ + IC_EVEX_L2_OPSIZE_B, /* 10134 */ + IC_EVEX_L2_OPSIZE_B, /* 10135 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10136 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10137 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10138 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10139 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10140 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10141 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10142 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10143 */ + IC_EVEX_L2_B, /* 10144 */ + IC_EVEX_L2_B, /* 10145 */ + IC_EVEX_L2_XS_B, /* 10146 */ + IC_EVEX_L2_XS_B, /* 10147 */ + IC_EVEX_L2_XD_B, /* 10148 */ + IC_EVEX_L2_XD_B, /* 10149 */ + IC_EVEX_L2_XD_B, /* 10150 */ + IC_EVEX_L2_XD_B, /* 10151 */ + IC_EVEX_L2_W_B, /* 10152 */ + IC_EVEX_L2_W_B, /* 10153 */ + IC_EVEX_L2_W_XS_B, /* 10154 */ + IC_EVEX_L2_W_XS_B, /* 10155 */ + IC_EVEX_L2_W_XD_B, /* 10156 */ + IC_EVEX_L2_W_XD_B, /* 10157 */ + IC_EVEX_L2_W_XD_B, /* 10158 */ + IC_EVEX_L2_W_XD_B, /* 10159 */ + IC_EVEX_L2_OPSIZE_B, /* 10160 */ + IC_EVEX_L2_OPSIZE_B, /* 10161 */ + IC_EVEX_L2_OPSIZE_B, /* 10162 */ + IC_EVEX_L2_OPSIZE_B, /* 10163 */ + IC_EVEX_L2_OPSIZE_B, /* 10164 */ + IC_EVEX_L2_OPSIZE_B, /* 10165 */ + IC_EVEX_L2_OPSIZE_B, /* 10166 */ + IC_EVEX_L2_OPSIZE_B, /* 10167 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10168 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10169 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10170 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10171 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10172 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10173 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10174 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10175 */ + IC_EVEX_L2_B, /* 10176 */ + IC_EVEX_L2_B, /* 10177 */ + IC_EVEX_L2_XS_B, /* 10178 */ + IC_EVEX_L2_XS_B, /* 10179 */ + IC_EVEX_L2_XD_B, /* 10180 */ + IC_EVEX_L2_XD_B, /* 10181 */ + IC_EVEX_L2_XD_B, /* 10182 */ + IC_EVEX_L2_XD_B, /* 10183 */ + IC_EVEX_L2_W_B, /* 10184 */ + IC_EVEX_L2_W_B, /* 10185 */ + IC_EVEX_L2_W_XS_B, /* 10186 */ + IC_EVEX_L2_W_XS_B, /* 10187 */ + IC_EVEX_L2_W_XD_B, /* 10188 */ + IC_EVEX_L2_W_XD_B, /* 10189 */ + IC_EVEX_L2_W_XD_B, /* 10190 */ + IC_EVEX_L2_W_XD_B, /* 10191 */ + IC_EVEX_L2_OPSIZE_B, /* 10192 */ + IC_EVEX_L2_OPSIZE_B, /* 10193 */ + IC_EVEX_L2_OPSIZE_B, /* 10194 */ + IC_EVEX_L2_OPSIZE_B, /* 10195 */ + IC_EVEX_L2_OPSIZE_B, /* 10196 */ + IC_EVEX_L2_OPSIZE_B, /* 10197 */ + IC_EVEX_L2_OPSIZE_B, /* 10198 */ + IC_EVEX_L2_OPSIZE_B, /* 10199 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10200 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10201 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10202 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10203 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10204 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10205 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10206 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10207 */ + IC_EVEX_L2_B, /* 10208 */ + IC_EVEX_L2_B, /* 10209 */ + IC_EVEX_L2_XS_B, /* 10210 */ + IC_EVEX_L2_XS_B, /* 10211 */ + IC_EVEX_L2_XD_B, /* 10212 */ + IC_EVEX_L2_XD_B, /* 10213 */ + IC_EVEX_L2_XD_B, /* 10214 */ + IC_EVEX_L2_XD_B, /* 10215 */ + IC_EVEX_L2_W_B, /* 10216 */ + IC_EVEX_L2_W_B, /* 10217 */ + IC_EVEX_L2_W_XS_B, /* 10218 */ + IC_EVEX_L2_W_XS_B, /* 10219 */ + IC_EVEX_L2_W_XD_B, /* 10220 */ + IC_EVEX_L2_W_XD_B, /* 10221 */ + IC_EVEX_L2_W_XD_B, /* 10222 */ + IC_EVEX_L2_W_XD_B, /* 10223 */ + IC_EVEX_L2_OPSIZE_B, /* 10224 */ + IC_EVEX_L2_OPSIZE_B, /* 10225 */ + IC_EVEX_L2_OPSIZE_B, /* 10226 */ + IC_EVEX_L2_OPSIZE_B, /* 10227 */ + IC_EVEX_L2_OPSIZE_B, /* 10228 */ + IC_EVEX_L2_OPSIZE_B, /* 10229 */ + IC_EVEX_L2_OPSIZE_B, /* 10230 */ + IC_EVEX_L2_OPSIZE_B, /* 10231 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10232 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10233 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10234 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10235 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10236 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10237 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10238 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10239 */ + IC, /* 10240 */ + IC_64BIT, /* 10241 */ + IC_XS, /* 10242 */ + IC_64BIT_XS, /* 10243 */ + IC_XD, /* 10244 */ + IC_64BIT_XD, /* 10245 */ + IC_XS, /* 10246 */ + IC_64BIT_XS, /* 10247 */ + IC, /* 10248 */ + IC_64BIT_REXW, /* 10249 */ + IC_XS, /* 10250 */ + IC_64BIT_REXW_XS, /* 10251 */ + IC_XD, /* 10252 */ + IC_64BIT_REXW_XD, /* 10253 */ + IC_XS, /* 10254 */ + IC_64BIT_REXW_XS, /* 10255 */ + IC_OPSIZE, /* 10256 */ + IC_64BIT_OPSIZE, /* 10257 */ + IC_XS_OPSIZE, /* 10258 */ + IC_64BIT_XS_OPSIZE, /* 10259 */ + IC_XD_OPSIZE, /* 10260 */ + IC_64BIT_XD_OPSIZE, /* 10261 */ + IC_XS_OPSIZE, /* 10262 */ + IC_64BIT_XD_OPSIZE, /* 10263 */ + IC_OPSIZE, /* 10264 */ + IC_64BIT_REXW_OPSIZE, /* 10265 */ + IC_XS_OPSIZE, /* 10266 */ + IC_64BIT_REXW_XS, /* 10267 */ + IC_XD_OPSIZE, /* 10268 */ + IC_64BIT_REXW_XD, /* 10269 */ + IC_XS_OPSIZE, /* 10270 */ + IC_64BIT_REXW_XS, /* 10271 */ + IC_ADSIZE, /* 10272 */ + IC_64BIT_ADSIZE, /* 10273 */ + IC_XS_ADSIZE, /* 10274 */ + IC_64BIT_XS_ADSIZE, /* 10275 */ + IC_XD_ADSIZE, /* 10276 */ + IC_64BIT_XD_ADSIZE, /* 10277 */ + IC_XS_ADSIZE, /* 10278 */ + IC_64BIT_XD_ADSIZE, /* 10279 */ + IC_ADSIZE, /* 10280 */ + IC_64BIT_REXW_ADSIZE, /* 10281 */ + IC_XS_ADSIZE, /* 10282 */ + IC_64BIT_REXW_XS, /* 10283 */ + IC_XD_ADSIZE, /* 10284 */ + IC_64BIT_REXW_XD, /* 10285 */ + IC_XS_ADSIZE, /* 10286 */ + IC_64BIT_REXW_XS, /* 10287 */ + IC_OPSIZE_ADSIZE, /* 10288 */ + IC_64BIT_OPSIZE_ADSIZE, /* 10289 */ + IC_XS_OPSIZE, /* 10290 */ + IC_64BIT_XS_OPSIZE, /* 10291 */ + IC_XD_OPSIZE, /* 10292 */ + IC_64BIT_XD_OPSIZE, /* 10293 */ + IC_XS_OPSIZE, /* 10294 */ + IC_64BIT_XD_OPSIZE, /* 10295 */ + IC_OPSIZE_ADSIZE, /* 10296 */ + IC_64BIT_REXW_OPSIZE, /* 10297 */ + IC_XS_OPSIZE, /* 10298 */ + IC_64BIT_REXW_XS, /* 10299 */ + IC_XD_OPSIZE, /* 10300 */ + IC_64BIT_REXW_XD, /* 10301 */ + IC_XS_OPSIZE, /* 10302 */ + IC_64BIT_REXW_XS, /* 10303 */ + IC_VEX, /* 10304 */ + IC_VEX, /* 10305 */ + IC_VEX_XS, /* 10306 */ + IC_VEX_XS, /* 10307 */ + IC_VEX_XD, /* 10308 */ + IC_VEX_XD, /* 10309 */ + IC_VEX_XD, /* 10310 */ + IC_VEX_XD, /* 10311 */ + IC_VEX_W, /* 10312 */ + IC_VEX_W, /* 10313 */ + IC_VEX_W_XS, /* 10314 */ + IC_VEX_W_XS, /* 10315 */ + IC_VEX_W_XD, /* 10316 */ + IC_VEX_W_XD, /* 10317 */ + IC_VEX_W_XD, /* 10318 */ + IC_VEX_W_XD, /* 10319 */ + IC_VEX_OPSIZE, /* 10320 */ + IC_VEX_OPSIZE, /* 10321 */ + IC_VEX_OPSIZE, /* 10322 */ + IC_VEX_OPSIZE, /* 10323 */ + IC_VEX_OPSIZE, /* 10324 */ + IC_VEX_OPSIZE, /* 10325 */ + IC_VEX_OPSIZE, /* 10326 */ + IC_VEX_OPSIZE, /* 10327 */ + IC_VEX_W_OPSIZE, /* 10328 */ + IC_VEX_W_OPSIZE, /* 10329 */ + IC_VEX_W_OPSIZE, /* 10330 */ + IC_VEX_W_OPSIZE, /* 10331 */ + IC_VEX_W_OPSIZE, /* 10332 */ + IC_VEX_W_OPSIZE, /* 10333 */ + IC_VEX_W_OPSIZE, /* 10334 */ + IC_VEX_W_OPSIZE, /* 10335 */ + IC_VEX, /* 10336 */ + IC_VEX, /* 10337 */ + IC_VEX_XS, /* 10338 */ + IC_VEX_XS, /* 10339 */ + IC_VEX_XD, /* 10340 */ + IC_VEX_XD, /* 10341 */ + IC_VEX_XD, /* 10342 */ + IC_VEX_XD, /* 10343 */ + IC_VEX_W, /* 10344 */ + IC_VEX_W, /* 10345 */ + IC_VEX_W_XS, /* 10346 */ + IC_VEX_W_XS, /* 10347 */ + IC_VEX_W_XD, /* 10348 */ + IC_VEX_W_XD, /* 10349 */ + IC_VEX_W_XD, /* 10350 */ + IC_VEX_W_XD, /* 10351 */ + IC_VEX_OPSIZE, /* 10352 */ + IC_VEX_OPSIZE, /* 10353 */ + IC_VEX_OPSIZE, /* 10354 */ + IC_VEX_OPSIZE, /* 10355 */ + IC_VEX_OPSIZE, /* 10356 */ + IC_VEX_OPSIZE, /* 10357 */ + IC_VEX_OPSIZE, /* 10358 */ + IC_VEX_OPSIZE, /* 10359 */ + IC_VEX_W_OPSIZE, /* 10360 */ + IC_VEX_W_OPSIZE, /* 10361 */ + IC_VEX_W_OPSIZE, /* 10362 */ + IC_VEX_W_OPSIZE, /* 10363 */ + IC_VEX_W_OPSIZE, /* 10364 */ + IC_VEX_W_OPSIZE, /* 10365 */ + IC_VEX_W_OPSIZE, /* 10366 */ + IC_VEX_W_OPSIZE, /* 10367 */ + IC_VEX_L, /* 10368 */ + IC_VEX_L, /* 10369 */ + IC_VEX_L_XS, /* 10370 */ + IC_VEX_L_XS, /* 10371 */ + IC_VEX_L_XD, /* 10372 */ + IC_VEX_L_XD, /* 10373 */ + IC_VEX_L_XD, /* 10374 */ + IC_VEX_L_XD, /* 10375 */ + IC_VEX_L_W, /* 10376 */ + IC_VEX_L_W, /* 10377 */ + IC_VEX_L_W_XS, /* 10378 */ + IC_VEX_L_W_XS, /* 10379 */ + IC_VEX_L_W_XD, /* 10380 */ + IC_VEX_L_W_XD, /* 10381 */ + IC_VEX_L_W_XD, /* 10382 */ + IC_VEX_L_W_XD, /* 10383 */ + IC_VEX_L_OPSIZE, /* 10384 */ + IC_VEX_L_OPSIZE, /* 10385 */ + IC_VEX_L_OPSIZE, /* 10386 */ + IC_VEX_L_OPSIZE, /* 10387 */ + IC_VEX_L_OPSIZE, /* 10388 */ + IC_VEX_L_OPSIZE, /* 10389 */ + IC_VEX_L_OPSIZE, /* 10390 */ + IC_VEX_L_OPSIZE, /* 10391 */ + IC_VEX_L_W_OPSIZE, /* 10392 */ + IC_VEX_L_W_OPSIZE, /* 10393 */ + IC_VEX_L_W_OPSIZE, /* 10394 */ + IC_VEX_L_W_OPSIZE, /* 10395 */ + IC_VEX_L_W_OPSIZE, /* 10396 */ + IC_VEX_L_W_OPSIZE, /* 10397 */ + IC_VEX_L_W_OPSIZE, /* 10398 */ + IC_VEX_L_W_OPSIZE, /* 10399 */ + IC_VEX_L, /* 10400 */ + IC_VEX_L, /* 10401 */ + IC_VEX_L_XS, /* 10402 */ + IC_VEX_L_XS, /* 10403 */ + IC_VEX_L_XD, /* 10404 */ + IC_VEX_L_XD, /* 10405 */ + IC_VEX_L_XD, /* 10406 */ + IC_VEX_L_XD, /* 10407 */ + IC_VEX_L_W, /* 10408 */ + IC_VEX_L_W, /* 10409 */ + IC_VEX_L_W_XS, /* 10410 */ + IC_VEX_L_W_XS, /* 10411 */ + IC_VEX_L_W_XD, /* 10412 */ + IC_VEX_L_W_XD, /* 10413 */ + IC_VEX_L_W_XD, /* 10414 */ + IC_VEX_L_W_XD, /* 10415 */ + IC_VEX_L_OPSIZE, /* 10416 */ + IC_VEX_L_OPSIZE, /* 10417 */ + IC_VEX_L_OPSIZE, /* 10418 */ + IC_VEX_L_OPSIZE, /* 10419 */ + IC_VEX_L_OPSIZE, /* 10420 */ + IC_VEX_L_OPSIZE, /* 10421 */ + IC_VEX_L_OPSIZE, /* 10422 */ + IC_VEX_L_OPSIZE, /* 10423 */ + IC_VEX_L_W_OPSIZE, /* 10424 */ + IC_VEX_L_W_OPSIZE, /* 10425 */ + IC_VEX_L_W_OPSIZE, /* 10426 */ + IC_VEX_L_W_OPSIZE, /* 10427 */ + IC_VEX_L_W_OPSIZE, /* 10428 */ + IC_VEX_L_W_OPSIZE, /* 10429 */ + IC_VEX_L_W_OPSIZE, /* 10430 */ + IC_VEX_L_W_OPSIZE, /* 10431 */ + IC_VEX_L, /* 10432 */ + IC_VEX_L, /* 10433 */ + IC_VEX_L_XS, /* 10434 */ + IC_VEX_L_XS, /* 10435 */ + IC_VEX_L_XD, /* 10436 */ + IC_VEX_L_XD, /* 10437 */ + IC_VEX_L_XD, /* 10438 */ + IC_VEX_L_XD, /* 10439 */ + IC_VEX_L_W, /* 10440 */ + IC_VEX_L_W, /* 10441 */ + IC_VEX_L_W_XS, /* 10442 */ + IC_VEX_L_W_XS, /* 10443 */ + IC_VEX_L_W_XD, /* 10444 */ + IC_VEX_L_W_XD, /* 10445 */ + IC_VEX_L_W_XD, /* 10446 */ + IC_VEX_L_W_XD, /* 10447 */ + IC_VEX_L_OPSIZE, /* 10448 */ + IC_VEX_L_OPSIZE, /* 10449 */ + IC_VEX_L_OPSIZE, /* 10450 */ + IC_VEX_L_OPSIZE, /* 10451 */ + IC_VEX_L_OPSIZE, /* 10452 */ + IC_VEX_L_OPSIZE, /* 10453 */ + IC_VEX_L_OPSIZE, /* 10454 */ + IC_VEX_L_OPSIZE, /* 10455 */ + IC_VEX_L_W_OPSIZE, /* 10456 */ + IC_VEX_L_W_OPSIZE, /* 10457 */ + IC_VEX_L_W_OPSIZE, /* 10458 */ + IC_VEX_L_W_OPSIZE, /* 10459 */ + IC_VEX_L_W_OPSIZE, /* 10460 */ + IC_VEX_L_W_OPSIZE, /* 10461 */ + IC_VEX_L_W_OPSIZE, /* 10462 */ + IC_VEX_L_W_OPSIZE, /* 10463 */ + IC_VEX_L, /* 10464 */ + IC_VEX_L, /* 10465 */ + IC_VEX_L_XS, /* 10466 */ + IC_VEX_L_XS, /* 10467 */ + IC_VEX_L_XD, /* 10468 */ + IC_VEX_L_XD, /* 10469 */ + IC_VEX_L_XD, /* 10470 */ + IC_VEX_L_XD, /* 10471 */ + IC_VEX_L_W, /* 10472 */ + IC_VEX_L_W, /* 10473 */ + IC_VEX_L_W_XS, /* 10474 */ + IC_VEX_L_W_XS, /* 10475 */ + IC_VEX_L_W_XD, /* 10476 */ + IC_VEX_L_W_XD, /* 10477 */ + IC_VEX_L_W_XD, /* 10478 */ + IC_VEX_L_W_XD, /* 10479 */ + IC_VEX_L_OPSIZE, /* 10480 */ + IC_VEX_L_OPSIZE, /* 10481 */ + IC_VEX_L_OPSIZE, /* 10482 */ + IC_VEX_L_OPSIZE, /* 10483 */ + IC_VEX_L_OPSIZE, /* 10484 */ + IC_VEX_L_OPSIZE, /* 10485 */ + IC_VEX_L_OPSIZE, /* 10486 */ + IC_VEX_L_OPSIZE, /* 10487 */ + IC_VEX_L_W_OPSIZE, /* 10488 */ + IC_VEX_L_W_OPSIZE, /* 10489 */ + IC_VEX_L_W_OPSIZE, /* 10490 */ + IC_VEX_L_W_OPSIZE, /* 10491 */ + IC_VEX_L_W_OPSIZE, /* 10492 */ + IC_VEX_L_W_OPSIZE, /* 10493 */ + IC_VEX_L_W_OPSIZE, /* 10494 */ + IC_VEX_L_W_OPSIZE, /* 10495 */ + IC_EVEX_K_B, /* 10496 */ + IC_EVEX_K_B, /* 10497 */ + IC_EVEX_XS_K_B, /* 10498 */ + IC_EVEX_XS_K_B, /* 10499 */ + IC_EVEX_XD_K_B, /* 10500 */ + IC_EVEX_XD_K_B, /* 10501 */ + IC_EVEX_XD_K_B, /* 10502 */ + IC_EVEX_XD_K_B, /* 10503 */ + IC_EVEX_W_K_B, /* 10504 */ + IC_EVEX_W_K_B, /* 10505 */ + IC_EVEX_W_XS_K_B, /* 10506 */ + IC_EVEX_W_XS_K_B, /* 10507 */ + IC_EVEX_W_XD_K_B, /* 10508 */ + IC_EVEX_W_XD_K_B, /* 10509 */ + IC_EVEX_W_XD_K_B, /* 10510 */ + IC_EVEX_W_XD_K_B, /* 10511 */ + IC_EVEX_OPSIZE_K_B, /* 10512 */ + IC_EVEX_OPSIZE_K_B, /* 10513 */ + IC_EVEX_OPSIZE_K_B, /* 10514 */ + IC_EVEX_OPSIZE_K_B, /* 10515 */ + IC_EVEX_OPSIZE_K_B, /* 10516 */ + IC_EVEX_OPSIZE_K_B, /* 10517 */ + IC_EVEX_OPSIZE_K_B, /* 10518 */ + IC_EVEX_OPSIZE_K_B, /* 10519 */ + IC_EVEX_W_OPSIZE_K_B, /* 10520 */ + IC_EVEX_W_OPSIZE_K_B, /* 10521 */ + IC_EVEX_W_OPSIZE_K_B, /* 10522 */ + IC_EVEX_W_OPSIZE_K_B, /* 10523 */ + IC_EVEX_W_OPSIZE_K_B, /* 10524 */ + IC_EVEX_W_OPSIZE_K_B, /* 10525 */ + IC_EVEX_W_OPSIZE_K_B, /* 10526 */ + IC_EVEX_W_OPSIZE_K_B, /* 10527 */ + IC_EVEX_K_B, /* 10528 */ + IC_EVEX_K_B, /* 10529 */ + IC_EVEX_XS_K_B, /* 10530 */ + IC_EVEX_XS_K_B, /* 10531 */ + IC_EVEX_XD_K_B, /* 10532 */ + IC_EVEX_XD_K_B, /* 10533 */ + IC_EVEX_XD_K_B, /* 10534 */ + IC_EVEX_XD_K_B, /* 10535 */ + IC_EVEX_W_K_B, /* 10536 */ + IC_EVEX_W_K_B, /* 10537 */ + IC_EVEX_W_XS_K_B, /* 10538 */ + IC_EVEX_W_XS_K_B, /* 10539 */ + IC_EVEX_W_XD_K_B, /* 10540 */ + IC_EVEX_W_XD_K_B, /* 10541 */ + IC_EVEX_W_XD_K_B, /* 10542 */ + IC_EVEX_W_XD_K_B, /* 10543 */ + IC_EVEX_OPSIZE_K_B, /* 10544 */ + IC_EVEX_OPSIZE_K_B, /* 10545 */ + IC_EVEX_OPSIZE_K_B, /* 10546 */ + IC_EVEX_OPSIZE_K_B, /* 10547 */ + IC_EVEX_OPSIZE_K_B, /* 10548 */ + IC_EVEX_OPSIZE_K_B, /* 10549 */ + IC_EVEX_OPSIZE_K_B, /* 10550 */ + IC_EVEX_OPSIZE_K_B, /* 10551 */ + IC_EVEX_W_OPSIZE_K_B, /* 10552 */ + IC_EVEX_W_OPSIZE_K_B, /* 10553 */ + IC_EVEX_W_OPSIZE_K_B, /* 10554 */ + IC_EVEX_W_OPSIZE_K_B, /* 10555 */ + IC_EVEX_W_OPSIZE_K_B, /* 10556 */ + IC_EVEX_W_OPSIZE_K_B, /* 10557 */ + IC_EVEX_W_OPSIZE_K_B, /* 10558 */ + IC_EVEX_W_OPSIZE_K_B, /* 10559 */ + IC_EVEX_K_B, /* 10560 */ + IC_EVEX_K_B, /* 10561 */ + IC_EVEX_XS_K_B, /* 10562 */ + IC_EVEX_XS_K_B, /* 10563 */ + IC_EVEX_XD_K_B, /* 10564 */ + IC_EVEX_XD_K_B, /* 10565 */ + IC_EVEX_XD_K_B, /* 10566 */ + IC_EVEX_XD_K_B, /* 10567 */ + IC_EVEX_W_K_B, /* 10568 */ + IC_EVEX_W_K_B, /* 10569 */ + IC_EVEX_W_XS_K_B, /* 10570 */ + IC_EVEX_W_XS_K_B, /* 10571 */ + IC_EVEX_W_XD_K_B, /* 10572 */ + IC_EVEX_W_XD_K_B, /* 10573 */ + IC_EVEX_W_XD_K_B, /* 10574 */ + IC_EVEX_W_XD_K_B, /* 10575 */ + IC_EVEX_OPSIZE_K_B, /* 10576 */ + IC_EVEX_OPSIZE_K_B, /* 10577 */ + IC_EVEX_OPSIZE_K_B, /* 10578 */ + IC_EVEX_OPSIZE_K_B, /* 10579 */ + IC_EVEX_OPSIZE_K_B, /* 10580 */ + IC_EVEX_OPSIZE_K_B, /* 10581 */ + IC_EVEX_OPSIZE_K_B, /* 10582 */ + IC_EVEX_OPSIZE_K_B, /* 10583 */ + IC_EVEX_W_OPSIZE_K_B, /* 10584 */ + IC_EVEX_W_OPSIZE_K_B, /* 10585 */ + IC_EVEX_W_OPSIZE_K_B, /* 10586 */ + IC_EVEX_W_OPSIZE_K_B, /* 10587 */ + IC_EVEX_W_OPSIZE_K_B, /* 10588 */ + IC_EVEX_W_OPSIZE_K_B, /* 10589 */ + IC_EVEX_W_OPSIZE_K_B, /* 10590 */ + IC_EVEX_W_OPSIZE_K_B, /* 10591 */ + IC_EVEX_K_B, /* 10592 */ + IC_EVEX_K_B, /* 10593 */ + IC_EVEX_XS_K_B, /* 10594 */ + IC_EVEX_XS_K_B, /* 10595 */ + IC_EVEX_XD_K_B, /* 10596 */ + IC_EVEX_XD_K_B, /* 10597 */ + IC_EVEX_XD_K_B, /* 10598 */ + IC_EVEX_XD_K_B, /* 10599 */ + IC_EVEX_W_K_B, /* 10600 */ + IC_EVEX_W_K_B, /* 10601 */ + IC_EVEX_W_XS_K_B, /* 10602 */ + IC_EVEX_W_XS_K_B, /* 10603 */ + IC_EVEX_W_XD_K_B, /* 10604 */ + IC_EVEX_W_XD_K_B, /* 10605 */ + IC_EVEX_W_XD_K_B, /* 10606 */ + IC_EVEX_W_XD_K_B, /* 10607 */ + IC_EVEX_OPSIZE_K_B, /* 10608 */ + IC_EVEX_OPSIZE_K_B, /* 10609 */ + IC_EVEX_OPSIZE_K_B, /* 10610 */ + IC_EVEX_OPSIZE_K_B, /* 10611 */ + IC_EVEX_OPSIZE_K_B, /* 10612 */ + IC_EVEX_OPSIZE_K_B, /* 10613 */ + IC_EVEX_OPSIZE_K_B, /* 10614 */ + IC_EVEX_OPSIZE_K_B, /* 10615 */ + IC_EVEX_W_OPSIZE_K_B, /* 10616 */ + IC_EVEX_W_OPSIZE_K_B, /* 10617 */ + IC_EVEX_W_OPSIZE_K_B, /* 10618 */ + IC_EVEX_W_OPSIZE_K_B, /* 10619 */ + IC_EVEX_W_OPSIZE_K_B, /* 10620 */ + IC_EVEX_W_OPSIZE_K_B, /* 10621 */ + IC_EVEX_W_OPSIZE_K_B, /* 10622 */ + IC_EVEX_W_OPSIZE_K_B, /* 10623 */ + IC_EVEX_K_B, /* 10624 */ + IC_EVEX_K_B, /* 10625 */ + IC_EVEX_XS_K_B, /* 10626 */ + IC_EVEX_XS_K_B, /* 10627 */ + IC_EVEX_XD_K_B, /* 10628 */ + IC_EVEX_XD_K_B, /* 10629 */ + IC_EVEX_XD_K_B, /* 10630 */ + IC_EVEX_XD_K_B, /* 10631 */ + IC_EVEX_W_K_B, /* 10632 */ + IC_EVEX_W_K_B, /* 10633 */ + IC_EVEX_W_XS_K_B, /* 10634 */ + IC_EVEX_W_XS_K_B, /* 10635 */ + IC_EVEX_W_XD_K_B, /* 10636 */ + IC_EVEX_W_XD_K_B, /* 10637 */ + IC_EVEX_W_XD_K_B, /* 10638 */ + IC_EVEX_W_XD_K_B, /* 10639 */ + IC_EVEX_OPSIZE_K_B, /* 10640 */ + IC_EVEX_OPSIZE_K_B, /* 10641 */ + IC_EVEX_OPSIZE_K_B, /* 10642 */ + IC_EVEX_OPSIZE_K_B, /* 10643 */ + IC_EVEX_OPSIZE_K_B, /* 10644 */ + IC_EVEX_OPSIZE_K_B, /* 10645 */ + IC_EVEX_OPSIZE_K_B, /* 10646 */ + IC_EVEX_OPSIZE_K_B, /* 10647 */ + IC_EVEX_W_OPSIZE_K_B, /* 10648 */ + IC_EVEX_W_OPSIZE_K_B, /* 10649 */ + IC_EVEX_W_OPSIZE_K_B, /* 10650 */ + IC_EVEX_W_OPSIZE_K_B, /* 10651 */ + IC_EVEX_W_OPSIZE_K_B, /* 10652 */ + IC_EVEX_W_OPSIZE_K_B, /* 10653 */ + IC_EVEX_W_OPSIZE_K_B, /* 10654 */ + IC_EVEX_W_OPSIZE_K_B, /* 10655 */ + IC_EVEX_K_B, /* 10656 */ + IC_EVEX_K_B, /* 10657 */ + IC_EVEX_XS_K_B, /* 10658 */ + IC_EVEX_XS_K_B, /* 10659 */ + IC_EVEX_XD_K_B, /* 10660 */ + IC_EVEX_XD_K_B, /* 10661 */ + IC_EVEX_XD_K_B, /* 10662 */ + IC_EVEX_XD_K_B, /* 10663 */ + IC_EVEX_W_K_B, /* 10664 */ + IC_EVEX_W_K_B, /* 10665 */ + IC_EVEX_W_XS_K_B, /* 10666 */ + IC_EVEX_W_XS_K_B, /* 10667 */ + IC_EVEX_W_XD_K_B, /* 10668 */ + IC_EVEX_W_XD_K_B, /* 10669 */ + IC_EVEX_W_XD_K_B, /* 10670 */ + IC_EVEX_W_XD_K_B, /* 10671 */ + IC_EVEX_OPSIZE_K_B, /* 10672 */ + IC_EVEX_OPSIZE_K_B, /* 10673 */ + IC_EVEX_OPSIZE_K_B, /* 10674 */ + IC_EVEX_OPSIZE_K_B, /* 10675 */ + IC_EVEX_OPSIZE_K_B, /* 10676 */ + IC_EVEX_OPSIZE_K_B, /* 10677 */ + IC_EVEX_OPSIZE_K_B, /* 10678 */ + IC_EVEX_OPSIZE_K_B, /* 10679 */ + IC_EVEX_W_OPSIZE_K_B, /* 10680 */ + IC_EVEX_W_OPSIZE_K_B, /* 10681 */ + IC_EVEX_W_OPSIZE_K_B, /* 10682 */ + IC_EVEX_W_OPSIZE_K_B, /* 10683 */ + IC_EVEX_W_OPSIZE_K_B, /* 10684 */ + IC_EVEX_W_OPSIZE_K_B, /* 10685 */ + IC_EVEX_W_OPSIZE_K_B, /* 10686 */ + IC_EVEX_W_OPSIZE_K_B, /* 10687 */ + IC_EVEX_K_B, /* 10688 */ + IC_EVEX_K_B, /* 10689 */ + IC_EVEX_XS_K_B, /* 10690 */ + IC_EVEX_XS_K_B, /* 10691 */ + IC_EVEX_XD_K_B, /* 10692 */ + IC_EVEX_XD_K_B, /* 10693 */ + IC_EVEX_XD_K_B, /* 10694 */ + IC_EVEX_XD_K_B, /* 10695 */ + IC_EVEX_W_K_B, /* 10696 */ + IC_EVEX_W_K_B, /* 10697 */ + IC_EVEX_W_XS_K_B, /* 10698 */ + IC_EVEX_W_XS_K_B, /* 10699 */ + IC_EVEX_W_XD_K_B, /* 10700 */ + IC_EVEX_W_XD_K_B, /* 10701 */ + IC_EVEX_W_XD_K_B, /* 10702 */ + IC_EVEX_W_XD_K_B, /* 10703 */ + IC_EVEX_OPSIZE_K_B, /* 10704 */ + IC_EVEX_OPSIZE_K_B, /* 10705 */ + IC_EVEX_OPSIZE_K_B, /* 10706 */ + IC_EVEX_OPSIZE_K_B, /* 10707 */ + IC_EVEX_OPSIZE_K_B, /* 10708 */ + IC_EVEX_OPSIZE_K_B, /* 10709 */ + IC_EVEX_OPSIZE_K_B, /* 10710 */ + IC_EVEX_OPSIZE_K_B, /* 10711 */ + IC_EVEX_W_OPSIZE_K_B, /* 10712 */ + IC_EVEX_W_OPSIZE_K_B, /* 10713 */ + IC_EVEX_W_OPSIZE_K_B, /* 10714 */ + IC_EVEX_W_OPSIZE_K_B, /* 10715 */ + IC_EVEX_W_OPSIZE_K_B, /* 10716 */ + IC_EVEX_W_OPSIZE_K_B, /* 10717 */ + IC_EVEX_W_OPSIZE_K_B, /* 10718 */ + IC_EVEX_W_OPSIZE_K_B, /* 10719 */ + IC_EVEX_K_B, /* 10720 */ + IC_EVEX_K_B, /* 10721 */ + IC_EVEX_XS_K_B, /* 10722 */ + IC_EVEX_XS_K_B, /* 10723 */ + IC_EVEX_XD_K_B, /* 10724 */ + IC_EVEX_XD_K_B, /* 10725 */ + IC_EVEX_XD_K_B, /* 10726 */ + IC_EVEX_XD_K_B, /* 10727 */ + IC_EVEX_W_K_B, /* 10728 */ + IC_EVEX_W_K_B, /* 10729 */ + IC_EVEX_W_XS_K_B, /* 10730 */ + IC_EVEX_W_XS_K_B, /* 10731 */ + IC_EVEX_W_XD_K_B, /* 10732 */ + IC_EVEX_W_XD_K_B, /* 10733 */ + IC_EVEX_W_XD_K_B, /* 10734 */ + IC_EVEX_W_XD_K_B, /* 10735 */ + IC_EVEX_OPSIZE_K_B, /* 10736 */ + IC_EVEX_OPSIZE_K_B, /* 10737 */ + IC_EVEX_OPSIZE_K_B, /* 10738 */ + IC_EVEX_OPSIZE_K_B, /* 10739 */ + IC_EVEX_OPSIZE_K_B, /* 10740 */ + IC_EVEX_OPSIZE_K_B, /* 10741 */ + IC_EVEX_OPSIZE_K_B, /* 10742 */ + IC_EVEX_OPSIZE_K_B, /* 10743 */ + IC_EVEX_W_OPSIZE_K_B, /* 10744 */ + IC_EVEX_W_OPSIZE_K_B, /* 10745 */ + IC_EVEX_W_OPSIZE_K_B, /* 10746 */ + IC_EVEX_W_OPSIZE_K_B, /* 10747 */ + IC_EVEX_W_OPSIZE_K_B, /* 10748 */ + IC_EVEX_W_OPSIZE_K_B, /* 10749 */ + IC_EVEX_W_OPSIZE_K_B, /* 10750 */ + IC_EVEX_W_OPSIZE_K_B, /* 10751 */ + IC, /* 10752 */ + IC_64BIT, /* 10753 */ + IC_XS, /* 10754 */ + IC_64BIT_XS, /* 10755 */ + IC_XD, /* 10756 */ + IC_64BIT_XD, /* 10757 */ + IC_XS, /* 10758 */ + IC_64BIT_XS, /* 10759 */ + IC, /* 10760 */ + IC_64BIT_REXW, /* 10761 */ + IC_XS, /* 10762 */ + IC_64BIT_REXW_XS, /* 10763 */ + IC_XD, /* 10764 */ + IC_64BIT_REXW_XD, /* 10765 */ + IC_XS, /* 10766 */ + IC_64BIT_REXW_XS, /* 10767 */ + IC_OPSIZE, /* 10768 */ + IC_64BIT_OPSIZE, /* 10769 */ + IC_XS_OPSIZE, /* 10770 */ + IC_64BIT_XS_OPSIZE, /* 10771 */ + IC_XD_OPSIZE, /* 10772 */ + IC_64BIT_XD_OPSIZE, /* 10773 */ + IC_XS_OPSIZE, /* 10774 */ + IC_64BIT_XD_OPSIZE, /* 10775 */ + IC_OPSIZE, /* 10776 */ + IC_64BIT_REXW_OPSIZE, /* 10777 */ + IC_XS_OPSIZE, /* 10778 */ + IC_64BIT_REXW_XS, /* 10779 */ + IC_XD_OPSIZE, /* 10780 */ + IC_64BIT_REXW_XD, /* 10781 */ + IC_XS_OPSIZE, /* 10782 */ + IC_64BIT_REXW_XS, /* 10783 */ + IC_ADSIZE, /* 10784 */ + IC_64BIT_ADSIZE, /* 10785 */ + IC_XS_ADSIZE, /* 10786 */ + IC_64BIT_XS_ADSIZE, /* 10787 */ + IC_XD_ADSIZE, /* 10788 */ + IC_64BIT_XD_ADSIZE, /* 10789 */ + IC_XS_ADSIZE, /* 10790 */ + IC_64BIT_XD_ADSIZE, /* 10791 */ + IC_ADSIZE, /* 10792 */ + IC_64BIT_REXW_ADSIZE, /* 10793 */ + IC_XS_ADSIZE, /* 10794 */ + IC_64BIT_REXW_XS, /* 10795 */ + IC_XD_ADSIZE, /* 10796 */ + IC_64BIT_REXW_XD, /* 10797 */ + IC_XS_ADSIZE, /* 10798 */ + IC_64BIT_REXW_XS, /* 10799 */ + IC_OPSIZE_ADSIZE, /* 10800 */ + IC_64BIT_OPSIZE_ADSIZE, /* 10801 */ + IC_XS_OPSIZE, /* 10802 */ + IC_64BIT_XS_OPSIZE, /* 10803 */ + IC_XD_OPSIZE, /* 10804 */ + IC_64BIT_XD_OPSIZE, /* 10805 */ + IC_XS_OPSIZE, /* 10806 */ + IC_64BIT_XD_OPSIZE, /* 10807 */ + IC_OPSIZE_ADSIZE, /* 10808 */ + IC_64BIT_REXW_OPSIZE, /* 10809 */ + IC_XS_OPSIZE, /* 10810 */ + IC_64BIT_REXW_XS, /* 10811 */ + IC_XD_OPSIZE, /* 10812 */ + IC_64BIT_REXW_XD, /* 10813 */ + IC_XS_OPSIZE, /* 10814 */ + IC_64BIT_REXW_XS, /* 10815 */ + IC_VEX, /* 10816 */ + IC_VEX, /* 10817 */ + IC_VEX_XS, /* 10818 */ + IC_VEX_XS, /* 10819 */ + IC_VEX_XD, /* 10820 */ + IC_VEX_XD, /* 10821 */ + IC_VEX_XD, /* 10822 */ + IC_VEX_XD, /* 10823 */ + IC_VEX_W, /* 10824 */ + IC_VEX_W, /* 10825 */ + IC_VEX_W_XS, /* 10826 */ + IC_VEX_W_XS, /* 10827 */ + IC_VEX_W_XD, /* 10828 */ + IC_VEX_W_XD, /* 10829 */ + IC_VEX_W_XD, /* 10830 */ + IC_VEX_W_XD, /* 10831 */ + IC_VEX_OPSIZE, /* 10832 */ + IC_VEX_OPSIZE, /* 10833 */ + IC_VEX_OPSIZE, /* 10834 */ + IC_VEX_OPSIZE, /* 10835 */ + IC_VEX_OPSIZE, /* 10836 */ + IC_VEX_OPSIZE, /* 10837 */ + IC_VEX_OPSIZE, /* 10838 */ + IC_VEX_OPSIZE, /* 10839 */ + IC_VEX_W_OPSIZE, /* 10840 */ + IC_VEX_W_OPSIZE, /* 10841 */ + IC_VEX_W_OPSIZE, /* 10842 */ + IC_VEX_W_OPSIZE, /* 10843 */ + IC_VEX_W_OPSIZE, /* 10844 */ + IC_VEX_W_OPSIZE, /* 10845 */ + IC_VEX_W_OPSIZE, /* 10846 */ + IC_VEX_W_OPSIZE, /* 10847 */ + IC_VEX, /* 10848 */ + IC_VEX, /* 10849 */ + IC_VEX_XS, /* 10850 */ + IC_VEX_XS, /* 10851 */ + IC_VEX_XD, /* 10852 */ + IC_VEX_XD, /* 10853 */ + IC_VEX_XD, /* 10854 */ + IC_VEX_XD, /* 10855 */ + IC_VEX_W, /* 10856 */ + IC_VEX_W, /* 10857 */ + IC_VEX_W_XS, /* 10858 */ + IC_VEX_W_XS, /* 10859 */ + IC_VEX_W_XD, /* 10860 */ + IC_VEX_W_XD, /* 10861 */ + IC_VEX_W_XD, /* 10862 */ + IC_VEX_W_XD, /* 10863 */ + IC_VEX_OPSIZE, /* 10864 */ + IC_VEX_OPSIZE, /* 10865 */ + IC_VEX_OPSIZE, /* 10866 */ + IC_VEX_OPSIZE, /* 10867 */ + IC_VEX_OPSIZE, /* 10868 */ + IC_VEX_OPSIZE, /* 10869 */ + IC_VEX_OPSIZE, /* 10870 */ + IC_VEX_OPSIZE, /* 10871 */ + IC_VEX_W_OPSIZE, /* 10872 */ + IC_VEX_W_OPSIZE, /* 10873 */ + IC_VEX_W_OPSIZE, /* 10874 */ + IC_VEX_W_OPSIZE, /* 10875 */ + IC_VEX_W_OPSIZE, /* 10876 */ + IC_VEX_W_OPSIZE, /* 10877 */ + IC_VEX_W_OPSIZE, /* 10878 */ + IC_VEX_W_OPSIZE, /* 10879 */ + IC_VEX_L, /* 10880 */ + IC_VEX_L, /* 10881 */ + IC_VEX_L_XS, /* 10882 */ + IC_VEX_L_XS, /* 10883 */ + IC_VEX_L_XD, /* 10884 */ + IC_VEX_L_XD, /* 10885 */ + IC_VEX_L_XD, /* 10886 */ + IC_VEX_L_XD, /* 10887 */ + IC_VEX_L_W, /* 10888 */ + IC_VEX_L_W, /* 10889 */ + IC_VEX_L_W_XS, /* 10890 */ + IC_VEX_L_W_XS, /* 10891 */ + IC_VEX_L_W_XD, /* 10892 */ + IC_VEX_L_W_XD, /* 10893 */ + IC_VEX_L_W_XD, /* 10894 */ + IC_VEX_L_W_XD, /* 10895 */ + IC_VEX_L_OPSIZE, /* 10896 */ + IC_VEX_L_OPSIZE, /* 10897 */ + IC_VEX_L_OPSIZE, /* 10898 */ + IC_VEX_L_OPSIZE, /* 10899 */ + IC_VEX_L_OPSIZE, /* 10900 */ + IC_VEX_L_OPSIZE, /* 10901 */ + IC_VEX_L_OPSIZE, /* 10902 */ + IC_VEX_L_OPSIZE, /* 10903 */ + IC_VEX_L_W_OPSIZE, /* 10904 */ + IC_VEX_L_W_OPSIZE, /* 10905 */ + IC_VEX_L_W_OPSIZE, /* 10906 */ + IC_VEX_L_W_OPSIZE, /* 10907 */ + IC_VEX_L_W_OPSIZE, /* 10908 */ + IC_VEX_L_W_OPSIZE, /* 10909 */ + IC_VEX_L_W_OPSIZE, /* 10910 */ + IC_VEX_L_W_OPSIZE, /* 10911 */ + IC_VEX_L, /* 10912 */ + IC_VEX_L, /* 10913 */ + IC_VEX_L_XS, /* 10914 */ + IC_VEX_L_XS, /* 10915 */ + IC_VEX_L_XD, /* 10916 */ + IC_VEX_L_XD, /* 10917 */ + IC_VEX_L_XD, /* 10918 */ + IC_VEX_L_XD, /* 10919 */ + IC_VEX_L_W, /* 10920 */ + IC_VEX_L_W, /* 10921 */ + IC_VEX_L_W_XS, /* 10922 */ + IC_VEX_L_W_XS, /* 10923 */ + IC_VEX_L_W_XD, /* 10924 */ + IC_VEX_L_W_XD, /* 10925 */ + IC_VEX_L_W_XD, /* 10926 */ + IC_VEX_L_W_XD, /* 10927 */ + IC_VEX_L_OPSIZE, /* 10928 */ + IC_VEX_L_OPSIZE, /* 10929 */ + IC_VEX_L_OPSIZE, /* 10930 */ + IC_VEX_L_OPSIZE, /* 10931 */ + IC_VEX_L_OPSIZE, /* 10932 */ + IC_VEX_L_OPSIZE, /* 10933 */ + IC_VEX_L_OPSIZE, /* 10934 */ + IC_VEX_L_OPSIZE, /* 10935 */ + IC_VEX_L_W_OPSIZE, /* 10936 */ + IC_VEX_L_W_OPSIZE, /* 10937 */ + IC_VEX_L_W_OPSIZE, /* 10938 */ + IC_VEX_L_W_OPSIZE, /* 10939 */ + IC_VEX_L_W_OPSIZE, /* 10940 */ + IC_VEX_L_W_OPSIZE, /* 10941 */ + IC_VEX_L_W_OPSIZE, /* 10942 */ + IC_VEX_L_W_OPSIZE, /* 10943 */ + IC_VEX_L, /* 10944 */ + IC_VEX_L, /* 10945 */ + IC_VEX_L_XS, /* 10946 */ + IC_VEX_L_XS, /* 10947 */ + IC_VEX_L_XD, /* 10948 */ + IC_VEX_L_XD, /* 10949 */ + IC_VEX_L_XD, /* 10950 */ + IC_VEX_L_XD, /* 10951 */ + IC_VEX_L_W, /* 10952 */ + IC_VEX_L_W, /* 10953 */ + IC_VEX_L_W_XS, /* 10954 */ + IC_VEX_L_W_XS, /* 10955 */ + IC_VEX_L_W_XD, /* 10956 */ + IC_VEX_L_W_XD, /* 10957 */ + IC_VEX_L_W_XD, /* 10958 */ + IC_VEX_L_W_XD, /* 10959 */ + IC_VEX_L_OPSIZE, /* 10960 */ + IC_VEX_L_OPSIZE, /* 10961 */ + IC_VEX_L_OPSIZE, /* 10962 */ + IC_VEX_L_OPSIZE, /* 10963 */ + IC_VEX_L_OPSIZE, /* 10964 */ + IC_VEX_L_OPSIZE, /* 10965 */ + IC_VEX_L_OPSIZE, /* 10966 */ + IC_VEX_L_OPSIZE, /* 10967 */ + IC_VEX_L_W_OPSIZE, /* 10968 */ + IC_VEX_L_W_OPSIZE, /* 10969 */ + IC_VEX_L_W_OPSIZE, /* 10970 */ + IC_VEX_L_W_OPSIZE, /* 10971 */ + IC_VEX_L_W_OPSIZE, /* 10972 */ + IC_VEX_L_W_OPSIZE, /* 10973 */ + IC_VEX_L_W_OPSIZE, /* 10974 */ + IC_VEX_L_W_OPSIZE, /* 10975 */ + IC_VEX_L, /* 10976 */ + IC_VEX_L, /* 10977 */ + IC_VEX_L_XS, /* 10978 */ + IC_VEX_L_XS, /* 10979 */ + IC_VEX_L_XD, /* 10980 */ + IC_VEX_L_XD, /* 10981 */ + IC_VEX_L_XD, /* 10982 */ + IC_VEX_L_XD, /* 10983 */ + IC_VEX_L_W, /* 10984 */ + IC_VEX_L_W, /* 10985 */ + IC_VEX_L_W_XS, /* 10986 */ + IC_VEX_L_W_XS, /* 10987 */ + IC_VEX_L_W_XD, /* 10988 */ + IC_VEX_L_W_XD, /* 10989 */ + IC_VEX_L_W_XD, /* 10990 */ + IC_VEX_L_W_XD, /* 10991 */ + IC_VEX_L_OPSIZE, /* 10992 */ + IC_VEX_L_OPSIZE, /* 10993 */ + IC_VEX_L_OPSIZE, /* 10994 */ + IC_VEX_L_OPSIZE, /* 10995 */ + IC_VEX_L_OPSIZE, /* 10996 */ + IC_VEX_L_OPSIZE, /* 10997 */ + IC_VEX_L_OPSIZE, /* 10998 */ + IC_VEX_L_OPSIZE, /* 10999 */ + IC_VEX_L_W_OPSIZE, /* 11000 */ + IC_VEX_L_W_OPSIZE, /* 11001 */ + IC_VEX_L_W_OPSIZE, /* 11002 */ + IC_VEX_L_W_OPSIZE, /* 11003 */ + IC_VEX_L_W_OPSIZE, /* 11004 */ + IC_VEX_L_W_OPSIZE, /* 11005 */ + IC_VEX_L_W_OPSIZE, /* 11006 */ + IC_VEX_L_W_OPSIZE, /* 11007 */ + IC_EVEX_L_K_B, /* 11008 */ + IC_EVEX_L_K_B, /* 11009 */ + IC_EVEX_L_XS_K_B, /* 11010 */ + IC_EVEX_L_XS_K_B, /* 11011 */ + IC_EVEX_L_XD_K_B, /* 11012 */ + IC_EVEX_L_XD_K_B, /* 11013 */ + IC_EVEX_L_XD_K_B, /* 11014 */ + IC_EVEX_L_XD_K_B, /* 11015 */ + IC_EVEX_L_W_K_B, /* 11016 */ + IC_EVEX_L_W_K_B, /* 11017 */ + IC_EVEX_L_W_XS_K_B, /* 11018 */ + IC_EVEX_L_W_XS_K_B, /* 11019 */ + IC_EVEX_L_W_XD_K_B, /* 11020 */ + IC_EVEX_L_W_XD_K_B, /* 11021 */ + IC_EVEX_L_W_XD_K_B, /* 11022 */ + IC_EVEX_L_W_XD_K_B, /* 11023 */ + IC_EVEX_L_OPSIZE_K_B, /* 11024 */ + IC_EVEX_L_OPSIZE_K_B, /* 11025 */ + IC_EVEX_L_OPSIZE_K_B, /* 11026 */ + IC_EVEX_L_OPSIZE_K_B, /* 11027 */ + IC_EVEX_L_OPSIZE_K_B, /* 11028 */ + IC_EVEX_L_OPSIZE_K_B, /* 11029 */ + IC_EVEX_L_OPSIZE_K_B, /* 11030 */ + IC_EVEX_L_OPSIZE_K_B, /* 11031 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11032 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11033 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11034 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11035 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11036 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11037 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11038 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11039 */ + IC_EVEX_L_K_B, /* 11040 */ + IC_EVEX_L_K_B, /* 11041 */ + IC_EVEX_L_XS_K_B, /* 11042 */ + IC_EVEX_L_XS_K_B, /* 11043 */ + IC_EVEX_L_XD_K_B, /* 11044 */ + IC_EVEX_L_XD_K_B, /* 11045 */ + IC_EVEX_L_XD_K_B, /* 11046 */ + IC_EVEX_L_XD_K_B, /* 11047 */ + IC_EVEX_L_W_K_B, /* 11048 */ + IC_EVEX_L_W_K_B, /* 11049 */ + IC_EVEX_L_W_XS_K_B, /* 11050 */ + IC_EVEX_L_W_XS_K_B, /* 11051 */ + IC_EVEX_L_W_XD_K_B, /* 11052 */ + IC_EVEX_L_W_XD_K_B, /* 11053 */ + IC_EVEX_L_W_XD_K_B, /* 11054 */ + IC_EVEX_L_W_XD_K_B, /* 11055 */ + IC_EVEX_L_OPSIZE_K_B, /* 11056 */ + IC_EVEX_L_OPSIZE_K_B, /* 11057 */ + IC_EVEX_L_OPSIZE_K_B, /* 11058 */ + IC_EVEX_L_OPSIZE_K_B, /* 11059 */ + IC_EVEX_L_OPSIZE_K_B, /* 11060 */ + IC_EVEX_L_OPSIZE_K_B, /* 11061 */ + IC_EVEX_L_OPSIZE_K_B, /* 11062 */ + IC_EVEX_L_OPSIZE_K_B, /* 11063 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11064 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11065 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11066 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11067 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11068 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11069 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11070 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11071 */ + IC_EVEX_L_K_B, /* 11072 */ + IC_EVEX_L_K_B, /* 11073 */ + IC_EVEX_L_XS_K_B, /* 11074 */ + IC_EVEX_L_XS_K_B, /* 11075 */ + IC_EVEX_L_XD_K_B, /* 11076 */ + IC_EVEX_L_XD_K_B, /* 11077 */ + IC_EVEX_L_XD_K_B, /* 11078 */ + IC_EVEX_L_XD_K_B, /* 11079 */ + IC_EVEX_L_W_K_B, /* 11080 */ + IC_EVEX_L_W_K_B, /* 11081 */ + IC_EVEX_L_W_XS_K_B, /* 11082 */ + IC_EVEX_L_W_XS_K_B, /* 11083 */ + IC_EVEX_L_W_XD_K_B, /* 11084 */ + IC_EVEX_L_W_XD_K_B, /* 11085 */ + IC_EVEX_L_W_XD_K_B, /* 11086 */ + IC_EVEX_L_W_XD_K_B, /* 11087 */ + IC_EVEX_L_OPSIZE_K_B, /* 11088 */ + IC_EVEX_L_OPSIZE_K_B, /* 11089 */ + IC_EVEX_L_OPSIZE_K_B, /* 11090 */ + IC_EVEX_L_OPSIZE_K_B, /* 11091 */ + IC_EVEX_L_OPSIZE_K_B, /* 11092 */ + IC_EVEX_L_OPSIZE_K_B, /* 11093 */ + IC_EVEX_L_OPSIZE_K_B, /* 11094 */ + IC_EVEX_L_OPSIZE_K_B, /* 11095 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11096 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11097 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11098 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11099 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11100 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11101 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11102 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11103 */ + IC_EVEX_L_K_B, /* 11104 */ + IC_EVEX_L_K_B, /* 11105 */ + IC_EVEX_L_XS_K_B, /* 11106 */ + IC_EVEX_L_XS_K_B, /* 11107 */ + IC_EVEX_L_XD_K_B, /* 11108 */ + IC_EVEX_L_XD_K_B, /* 11109 */ + IC_EVEX_L_XD_K_B, /* 11110 */ + IC_EVEX_L_XD_K_B, /* 11111 */ + IC_EVEX_L_W_K_B, /* 11112 */ + IC_EVEX_L_W_K_B, /* 11113 */ + IC_EVEX_L_W_XS_K_B, /* 11114 */ + IC_EVEX_L_W_XS_K_B, /* 11115 */ + IC_EVEX_L_W_XD_K_B, /* 11116 */ + IC_EVEX_L_W_XD_K_B, /* 11117 */ + IC_EVEX_L_W_XD_K_B, /* 11118 */ + IC_EVEX_L_W_XD_K_B, /* 11119 */ + IC_EVEX_L_OPSIZE_K_B, /* 11120 */ + IC_EVEX_L_OPSIZE_K_B, /* 11121 */ + IC_EVEX_L_OPSIZE_K_B, /* 11122 */ + IC_EVEX_L_OPSIZE_K_B, /* 11123 */ + IC_EVEX_L_OPSIZE_K_B, /* 11124 */ + IC_EVEX_L_OPSIZE_K_B, /* 11125 */ + IC_EVEX_L_OPSIZE_K_B, /* 11126 */ + IC_EVEX_L_OPSIZE_K_B, /* 11127 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11128 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11129 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11130 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11131 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11132 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11133 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11134 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11135 */ + IC_EVEX_L_K_B, /* 11136 */ + IC_EVEX_L_K_B, /* 11137 */ + IC_EVEX_L_XS_K_B, /* 11138 */ + IC_EVEX_L_XS_K_B, /* 11139 */ + IC_EVEX_L_XD_K_B, /* 11140 */ + IC_EVEX_L_XD_K_B, /* 11141 */ + IC_EVEX_L_XD_K_B, /* 11142 */ + IC_EVEX_L_XD_K_B, /* 11143 */ + IC_EVEX_L_W_K_B, /* 11144 */ + IC_EVEX_L_W_K_B, /* 11145 */ + IC_EVEX_L_W_XS_K_B, /* 11146 */ + IC_EVEX_L_W_XS_K_B, /* 11147 */ + IC_EVEX_L_W_XD_K_B, /* 11148 */ + IC_EVEX_L_W_XD_K_B, /* 11149 */ + IC_EVEX_L_W_XD_K_B, /* 11150 */ + IC_EVEX_L_W_XD_K_B, /* 11151 */ + IC_EVEX_L_OPSIZE_K_B, /* 11152 */ + IC_EVEX_L_OPSIZE_K_B, /* 11153 */ + IC_EVEX_L_OPSIZE_K_B, /* 11154 */ + IC_EVEX_L_OPSIZE_K_B, /* 11155 */ + IC_EVEX_L_OPSIZE_K_B, /* 11156 */ + IC_EVEX_L_OPSIZE_K_B, /* 11157 */ + IC_EVEX_L_OPSIZE_K_B, /* 11158 */ + IC_EVEX_L_OPSIZE_K_B, /* 11159 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11160 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11161 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11162 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11163 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11164 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11165 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11166 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11167 */ + IC_EVEX_L_K_B, /* 11168 */ + IC_EVEX_L_K_B, /* 11169 */ + IC_EVEX_L_XS_K_B, /* 11170 */ + IC_EVEX_L_XS_K_B, /* 11171 */ + IC_EVEX_L_XD_K_B, /* 11172 */ + IC_EVEX_L_XD_K_B, /* 11173 */ + IC_EVEX_L_XD_K_B, /* 11174 */ + IC_EVEX_L_XD_K_B, /* 11175 */ + IC_EVEX_L_W_K_B, /* 11176 */ + IC_EVEX_L_W_K_B, /* 11177 */ + IC_EVEX_L_W_XS_K_B, /* 11178 */ + IC_EVEX_L_W_XS_K_B, /* 11179 */ + IC_EVEX_L_W_XD_K_B, /* 11180 */ + IC_EVEX_L_W_XD_K_B, /* 11181 */ + IC_EVEX_L_W_XD_K_B, /* 11182 */ + IC_EVEX_L_W_XD_K_B, /* 11183 */ + IC_EVEX_L_OPSIZE_K_B, /* 11184 */ + IC_EVEX_L_OPSIZE_K_B, /* 11185 */ + IC_EVEX_L_OPSIZE_K_B, /* 11186 */ + IC_EVEX_L_OPSIZE_K_B, /* 11187 */ + IC_EVEX_L_OPSIZE_K_B, /* 11188 */ + IC_EVEX_L_OPSIZE_K_B, /* 11189 */ + IC_EVEX_L_OPSIZE_K_B, /* 11190 */ + IC_EVEX_L_OPSIZE_K_B, /* 11191 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11192 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11193 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11194 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11195 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11196 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11197 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11198 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11199 */ + IC_EVEX_L_K_B, /* 11200 */ + IC_EVEX_L_K_B, /* 11201 */ + IC_EVEX_L_XS_K_B, /* 11202 */ + IC_EVEX_L_XS_K_B, /* 11203 */ + IC_EVEX_L_XD_K_B, /* 11204 */ + IC_EVEX_L_XD_K_B, /* 11205 */ + IC_EVEX_L_XD_K_B, /* 11206 */ + IC_EVEX_L_XD_K_B, /* 11207 */ + IC_EVEX_L_W_K_B, /* 11208 */ + IC_EVEX_L_W_K_B, /* 11209 */ + IC_EVEX_L_W_XS_K_B, /* 11210 */ + IC_EVEX_L_W_XS_K_B, /* 11211 */ + IC_EVEX_L_W_XD_K_B, /* 11212 */ + IC_EVEX_L_W_XD_K_B, /* 11213 */ + IC_EVEX_L_W_XD_K_B, /* 11214 */ + IC_EVEX_L_W_XD_K_B, /* 11215 */ + IC_EVEX_L_OPSIZE_K_B, /* 11216 */ + IC_EVEX_L_OPSIZE_K_B, /* 11217 */ + IC_EVEX_L_OPSIZE_K_B, /* 11218 */ + IC_EVEX_L_OPSIZE_K_B, /* 11219 */ + IC_EVEX_L_OPSIZE_K_B, /* 11220 */ + IC_EVEX_L_OPSIZE_K_B, /* 11221 */ + IC_EVEX_L_OPSIZE_K_B, /* 11222 */ + IC_EVEX_L_OPSIZE_K_B, /* 11223 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11224 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11225 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11226 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11227 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11228 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11229 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11230 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11231 */ + IC_EVEX_L_K_B, /* 11232 */ + IC_EVEX_L_K_B, /* 11233 */ + IC_EVEX_L_XS_K_B, /* 11234 */ + IC_EVEX_L_XS_K_B, /* 11235 */ + IC_EVEX_L_XD_K_B, /* 11236 */ + IC_EVEX_L_XD_K_B, /* 11237 */ + IC_EVEX_L_XD_K_B, /* 11238 */ + IC_EVEX_L_XD_K_B, /* 11239 */ + IC_EVEX_L_W_K_B, /* 11240 */ + IC_EVEX_L_W_K_B, /* 11241 */ + IC_EVEX_L_W_XS_K_B, /* 11242 */ + IC_EVEX_L_W_XS_K_B, /* 11243 */ + IC_EVEX_L_W_XD_K_B, /* 11244 */ + IC_EVEX_L_W_XD_K_B, /* 11245 */ + IC_EVEX_L_W_XD_K_B, /* 11246 */ + IC_EVEX_L_W_XD_K_B, /* 11247 */ + IC_EVEX_L_OPSIZE_K_B, /* 11248 */ + IC_EVEX_L_OPSIZE_K_B, /* 11249 */ + IC_EVEX_L_OPSIZE_K_B, /* 11250 */ + IC_EVEX_L_OPSIZE_K_B, /* 11251 */ + IC_EVEX_L_OPSIZE_K_B, /* 11252 */ + IC_EVEX_L_OPSIZE_K_B, /* 11253 */ + IC_EVEX_L_OPSIZE_K_B, /* 11254 */ + IC_EVEX_L_OPSIZE_K_B, /* 11255 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11256 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11257 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11258 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11259 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11260 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11261 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11262 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11263 */ + IC, /* 11264 */ + IC_64BIT, /* 11265 */ + IC_XS, /* 11266 */ + IC_64BIT_XS, /* 11267 */ + IC_XD, /* 11268 */ + IC_64BIT_XD, /* 11269 */ + IC_XS, /* 11270 */ + IC_64BIT_XS, /* 11271 */ + IC, /* 11272 */ + IC_64BIT_REXW, /* 11273 */ + IC_XS, /* 11274 */ + IC_64BIT_REXW_XS, /* 11275 */ + IC_XD, /* 11276 */ + IC_64BIT_REXW_XD, /* 11277 */ + IC_XS, /* 11278 */ + IC_64BIT_REXW_XS, /* 11279 */ + IC_OPSIZE, /* 11280 */ + IC_64BIT_OPSIZE, /* 11281 */ + IC_XS_OPSIZE, /* 11282 */ + IC_64BIT_XS_OPSIZE, /* 11283 */ + IC_XD_OPSIZE, /* 11284 */ + IC_64BIT_XD_OPSIZE, /* 11285 */ + IC_XS_OPSIZE, /* 11286 */ + IC_64BIT_XD_OPSIZE, /* 11287 */ + IC_OPSIZE, /* 11288 */ + IC_64BIT_REXW_OPSIZE, /* 11289 */ + IC_XS_OPSIZE, /* 11290 */ + IC_64BIT_REXW_XS, /* 11291 */ + IC_XD_OPSIZE, /* 11292 */ + IC_64BIT_REXW_XD, /* 11293 */ + IC_XS_OPSIZE, /* 11294 */ + IC_64BIT_REXW_XS, /* 11295 */ + IC_ADSIZE, /* 11296 */ + IC_64BIT_ADSIZE, /* 11297 */ + IC_XS_ADSIZE, /* 11298 */ + IC_64BIT_XS_ADSIZE, /* 11299 */ + IC_XD_ADSIZE, /* 11300 */ + IC_64BIT_XD_ADSIZE, /* 11301 */ + IC_XS_ADSIZE, /* 11302 */ + IC_64BIT_XD_ADSIZE, /* 11303 */ + IC_ADSIZE, /* 11304 */ + IC_64BIT_REXW_ADSIZE, /* 11305 */ + IC_XS_ADSIZE, /* 11306 */ + IC_64BIT_REXW_XS, /* 11307 */ + IC_XD_ADSIZE, /* 11308 */ + IC_64BIT_REXW_XD, /* 11309 */ + IC_XS_ADSIZE, /* 11310 */ + IC_64BIT_REXW_XS, /* 11311 */ + IC_OPSIZE_ADSIZE, /* 11312 */ + IC_64BIT_OPSIZE_ADSIZE, /* 11313 */ + IC_XS_OPSIZE, /* 11314 */ + IC_64BIT_XS_OPSIZE, /* 11315 */ + IC_XD_OPSIZE, /* 11316 */ + IC_64BIT_XD_OPSIZE, /* 11317 */ + IC_XS_OPSIZE, /* 11318 */ + IC_64BIT_XD_OPSIZE, /* 11319 */ + IC_OPSIZE_ADSIZE, /* 11320 */ + IC_64BIT_REXW_OPSIZE, /* 11321 */ + IC_XS_OPSIZE, /* 11322 */ + IC_64BIT_REXW_XS, /* 11323 */ + IC_XD_OPSIZE, /* 11324 */ + IC_64BIT_REXW_XD, /* 11325 */ + IC_XS_OPSIZE, /* 11326 */ + IC_64BIT_REXW_XS, /* 11327 */ + IC_VEX, /* 11328 */ + IC_VEX, /* 11329 */ + IC_VEX_XS, /* 11330 */ + IC_VEX_XS, /* 11331 */ + IC_VEX_XD, /* 11332 */ + IC_VEX_XD, /* 11333 */ + IC_VEX_XD, /* 11334 */ + IC_VEX_XD, /* 11335 */ + IC_VEX_W, /* 11336 */ + IC_VEX_W, /* 11337 */ + IC_VEX_W_XS, /* 11338 */ + IC_VEX_W_XS, /* 11339 */ + IC_VEX_W_XD, /* 11340 */ + IC_VEX_W_XD, /* 11341 */ + IC_VEX_W_XD, /* 11342 */ + IC_VEX_W_XD, /* 11343 */ + IC_VEX_OPSIZE, /* 11344 */ + IC_VEX_OPSIZE, /* 11345 */ + IC_VEX_OPSIZE, /* 11346 */ + IC_VEX_OPSIZE, /* 11347 */ + IC_VEX_OPSIZE, /* 11348 */ + IC_VEX_OPSIZE, /* 11349 */ + IC_VEX_OPSIZE, /* 11350 */ + IC_VEX_OPSIZE, /* 11351 */ + IC_VEX_W_OPSIZE, /* 11352 */ + IC_VEX_W_OPSIZE, /* 11353 */ + IC_VEX_W_OPSIZE, /* 11354 */ + IC_VEX_W_OPSIZE, /* 11355 */ + IC_VEX_W_OPSIZE, /* 11356 */ + IC_VEX_W_OPSIZE, /* 11357 */ + IC_VEX_W_OPSIZE, /* 11358 */ + IC_VEX_W_OPSIZE, /* 11359 */ + IC_VEX, /* 11360 */ + IC_VEX, /* 11361 */ + IC_VEX_XS, /* 11362 */ + IC_VEX_XS, /* 11363 */ + IC_VEX_XD, /* 11364 */ + IC_VEX_XD, /* 11365 */ + IC_VEX_XD, /* 11366 */ + IC_VEX_XD, /* 11367 */ + IC_VEX_W, /* 11368 */ + IC_VEX_W, /* 11369 */ + IC_VEX_W_XS, /* 11370 */ + IC_VEX_W_XS, /* 11371 */ + IC_VEX_W_XD, /* 11372 */ + IC_VEX_W_XD, /* 11373 */ + IC_VEX_W_XD, /* 11374 */ + IC_VEX_W_XD, /* 11375 */ + IC_VEX_OPSIZE, /* 11376 */ + IC_VEX_OPSIZE, /* 11377 */ + IC_VEX_OPSIZE, /* 11378 */ + IC_VEX_OPSIZE, /* 11379 */ + IC_VEX_OPSIZE, /* 11380 */ + IC_VEX_OPSIZE, /* 11381 */ + IC_VEX_OPSIZE, /* 11382 */ + IC_VEX_OPSIZE, /* 11383 */ + IC_VEX_W_OPSIZE, /* 11384 */ + IC_VEX_W_OPSIZE, /* 11385 */ + IC_VEX_W_OPSIZE, /* 11386 */ + IC_VEX_W_OPSIZE, /* 11387 */ + IC_VEX_W_OPSIZE, /* 11388 */ + IC_VEX_W_OPSIZE, /* 11389 */ + IC_VEX_W_OPSIZE, /* 11390 */ + IC_VEX_W_OPSIZE, /* 11391 */ + IC_VEX_L, /* 11392 */ + IC_VEX_L, /* 11393 */ + IC_VEX_L_XS, /* 11394 */ + IC_VEX_L_XS, /* 11395 */ + IC_VEX_L_XD, /* 11396 */ + IC_VEX_L_XD, /* 11397 */ + IC_VEX_L_XD, /* 11398 */ + IC_VEX_L_XD, /* 11399 */ + IC_VEX_L_W, /* 11400 */ + IC_VEX_L_W, /* 11401 */ + IC_VEX_L_W_XS, /* 11402 */ + IC_VEX_L_W_XS, /* 11403 */ + IC_VEX_L_W_XD, /* 11404 */ + IC_VEX_L_W_XD, /* 11405 */ + IC_VEX_L_W_XD, /* 11406 */ + IC_VEX_L_W_XD, /* 11407 */ + IC_VEX_L_OPSIZE, /* 11408 */ + IC_VEX_L_OPSIZE, /* 11409 */ + IC_VEX_L_OPSIZE, /* 11410 */ + IC_VEX_L_OPSIZE, /* 11411 */ + IC_VEX_L_OPSIZE, /* 11412 */ + IC_VEX_L_OPSIZE, /* 11413 */ + IC_VEX_L_OPSIZE, /* 11414 */ + IC_VEX_L_OPSIZE, /* 11415 */ + IC_VEX_L_W_OPSIZE, /* 11416 */ + IC_VEX_L_W_OPSIZE, /* 11417 */ + IC_VEX_L_W_OPSIZE, /* 11418 */ + IC_VEX_L_W_OPSIZE, /* 11419 */ + IC_VEX_L_W_OPSIZE, /* 11420 */ + IC_VEX_L_W_OPSIZE, /* 11421 */ + IC_VEX_L_W_OPSIZE, /* 11422 */ + IC_VEX_L_W_OPSIZE, /* 11423 */ + IC_VEX_L, /* 11424 */ + IC_VEX_L, /* 11425 */ + IC_VEX_L_XS, /* 11426 */ + IC_VEX_L_XS, /* 11427 */ + IC_VEX_L_XD, /* 11428 */ + IC_VEX_L_XD, /* 11429 */ + IC_VEX_L_XD, /* 11430 */ + IC_VEX_L_XD, /* 11431 */ + IC_VEX_L_W, /* 11432 */ + IC_VEX_L_W, /* 11433 */ + IC_VEX_L_W_XS, /* 11434 */ + IC_VEX_L_W_XS, /* 11435 */ + IC_VEX_L_W_XD, /* 11436 */ + IC_VEX_L_W_XD, /* 11437 */ + IC_VEX_L_W_XD, /* 11438 */ + IC_VEX_L_W_XD, /* 11439 */ + IC_VEX_L_OPSIZE, /* 11440 */ + IC_VEX_L_OPSIZE, /* 11441 */ + IC_VEX_L_OPSIZE, /* 11442 */ + IC_VEX_L_OPSIZE, /* 11443 */ + IC_VEX_L_OPSIZE, /* 11444 */ + IC_VEX_L_OPSIZE, /* 11445 */ + IC_VEX_L_OPSIZE, /* 11446 */ + IC_VEX_L_OPSIZE, /* 11447 */ + IC_VEX_L_W_OPSIZE, /* 11448 */ + IC_VEX_L_W_OPSIZE, /* 11449 */ + IC_VEX_L_W_OPSIZE, /* 11450 */ + IC_VEX_L_W_OPSIZE, /* 11451 */ + IC_VEX_L_W_OPSIZE, /* 11452 */ + IC_VEX_L_W_OPSIZE, /* 11453 */ + IC_VEX_L_W_OPSIZE, /* 11454 */ + IC_VEX_L_W_OPSIZE, /* 11455 */ + IC_VEX_L, /* 11456 */ + IC_VEX_L, /* 11457 */ + IC_VEX_L_XS, /* 11458 */ + IC_VEX_L_XS, /* 11459 */ + IC_VEX_L_XD, /* 11460 */ + IC_VEX_L_XD, /* 11461 */ + IC_VEX_L_XD, /* 11462 */ + IC_VEX_L_XD, /* 11463 */ + IC_VEX_L_W, /* 11464 */ + IC_VEX_L_W, /* 11465 */ + IC_VEX_L_W_XS, /* 11466 */ + IC_VEX_L_W_XS, /* 11467 */ + IC_VEX_L_W_XD, /* 11468 */ + IC_VEX_L_W_XD, /* 11469 */ + IC_VEX_L_W_XD, /* 11470 */ + IC_VEX_L_W_XD, /* 11471 */ + IC_VEX_L_OPSIZE, /* 11472 */ + IC_VEX_L_OPSIZE, /* 11473 */ + IC_VEX_L_OPSIZE, /* 11474 */ + IC_VEX_L_OPSIZE, /* 11475 */ + IC_VEX_L_OPSIZE, /* 11476 */ + IC_VEX_L_OPSIZE, /* 11477 */ + IC_VEX_L_OPSIZE, /* 11478 */ + IC_VEX_L_OPSIZE, /* 11479 */ + IC_VEX_L_W_OPSIZE, /* 11480 */ + IC_VEX_L_W_OPSIZE, /* 11481 */ + IC_VEX_L_W_OPSIZE, /* 11482 */ + IC_VEX_L_W_OPSIZE, /* 11483 */ + IC_VEX_L_W_OPSIZE, /* 11484 */ + IC_VEX_L_W_OPSIZE, /* 11485 */ + IC_VEX_L_W_OPSIZE, /* 11486 */ + IC_VEX_L_W_OPSIZE, /* 11487 */ + IC_VEX_L, /* 11488 */ + IC_VEX_L, /* 11489 */ + IC_VEX_L_XS, /* 11490 */ + IC_VEX_L_XS, /* 11491 */ + IC_VEX_L_XD, /* 11492 */ + IC_VEX_L_XD, /* 11493 */ + IC_VEX_L_XD, /* 11494 */ + IC_VEX_L_XD, /* 11495 */ + IC_VEX_L_W, /* 11496 */ + IC_VEX_L_W, /* 11497 */ + IC_VEX_L_W_XS, /* 11498 */ + IC_VEX_L_W_XS, /* 11499 */ + IC_VEX_L_W_XD, /* 11500 */ + IC_VEX_L_W_XD, /* 11501 */ + IC_VEX_L_W_XD, /* 11502 */ + IC_VEX_L_W_XD, /* 11503 */ + IC_VEX_L_OPSIZE, /* 11504 */ + IC_VEX_L_OPSIZE, /* 11505 */ + IC_VEX_L_OPSIZE, /* 11506 */ + IC_VEX_L_OPSIZE, /* 11507 */ + IC_VEX_L_OPSIZE, /* 11508 */ + IC_VEX_L_OPSIZE, /* 11509 */ + IC_VEX_L_OPSIZE, /* 11510 */ + IC_VEX_L_OPSIZE, /* 11511 */ + IC_VEX_L_W_OPSIZE, /* 11512 */ + IC_VEX_L_W_OPSIZE, /* 11513 */ + IC_VEX_L_W_OPSIZE, /* 11514 */ + IC_VEX_L_W_OPSIZE, /* 11515 */ + IC_VEX_L_W_OPSIZE, /* 11516 */ + IC_VEX_L_W_OPSIZE, /* 11517 */ + IC_VEX_L_W_OPSIZE, /* 11518 */ + IC_VEX_L_W_OPSIZE, /* 11519 */ + IC_EVEX_L2_K_B, /* 11520 */ + IC_EVEX_L2_K_B, /* 11521 */ + IC_EVEX_L2_XS_K_B, /* 11522 */ + IC_EVEX_L2_XS_K_B, /* 11523 */ + IC_EVEX_L2_XD_K_B, /* 11524 */ + IC_EVEX_L2_XD_K_B, /* 11525 */ + IC_EVEX_L2_XD_K_B, /* 11526 */ + IC_EVEX_L2_XD_K_B, /* 11527 */ + IC_EVEX_L2_W_K_B, /* 11528 */ + IC_EVEX_L2_W_K_B, /* 11529 */ + IC_EVEX_L2_W_XS_K_B, /* 11530 */ + IC_EVEX_L2_W_XS_K_B, /* 11531 */ + IC_EVEX_L2_W_XD_K_B, /* 11532 */ + IC_EVEX_L2_W_XD_K_B, /* 11533 */ + IC_EVEX_L2_W_XD_K_B, /* 11534 */ + IC_EVEX_L2_W_XD_K_B, /* 11535 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11536 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11537 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11538 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11539 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11540 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11541 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11542 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11543 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11544 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11545 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11546 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11547 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11548 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11549 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11550 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11551 */ + IC_EVEX_L2_K_B, /* 11552 */ + IC_EVEX_L2_K_B, /* 11553 */ + IC_EVEX_L2_XS_K_B, /* 11554 */ + IC_EVEX_L2_XS_K_B, /* 11555 */ + IC_EVEX_L2_XD_K_B, /* 11556 */ + IC_EVEX_L2_XD_K_B, /* 11557 */ + IC_EVEX_L2_XD_K_B, /* 11558 */ + IC_EVEX_L2_XD_K_B, /* 11559 */ + IC_EVEX_L2_W_K_B, /* 11560 */ + IC_EVEX_L2_W_K_B, /* 11561 */ + IC_EVEX_L2_W_XS_K_B, /* 11562 */ + IC_EVEX_L2_W_XS_K_B, /* 11563 */ + IC_EVEX_L2_W_XD_K_B, /* 11564 */ + IC_EVEX_L2_W_XD_K_B, /* 11565 */ + IC_EVEX_L2_W_XD_K_B, /* 11566 */ + IC_EVEX_L2_W_XD_K_B, /* 11567 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11568 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11569 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11570 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11571 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11572 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11573 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11574 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11575 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11576 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11577 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11578 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11579 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11580 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11581 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11582 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11583 */ + IC_EVEX_L2_K_B, /* 11584 */ + IC_EVEX_L2_K_B, /* 11585 */ + IC_EVEX_L2_XS_K_B, /* 11586 */ + IC_EVEX_L2_XS_K_B, /* 11587 */ + IC_EVEX_L2_XD_K_B, /* 11588 */ + IC_EVEX_L2_XD_K_B, /* 11589 */ + IC_EVEX_L2_XD_K_B, /* 11590 */ + IC_EVEX_L2_XD_K_B, /* 11591 */ + IC_EVEX_L2_W_K_B, /* 11592 */ + IC_EVEX_L2_W_K_B, /* 11593 */ + IC_EVEX_L2_W_XS_K_B, /* 11594 */ + IC_EVEX_L2_W_XS_K_B, /* 11595 */ + IC_EVEX_L2_W_XD_K_B, /* 11596 */ + IC_EVEX_L2_W_XD_K_B, /* 11597 */ + IC_EVEX_L2_W_XD_K_B, /* 11598 */ + IC_EVEX_L2_W_XD_K_B, /* 11599 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11600 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11601 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11602 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11603 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11604 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11605 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11606 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11607 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11608 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11609 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11610 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11611 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11612 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11613 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11614 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11615 */ + IC_EVEX_L2_K_B, /* 11616 */ + IC_EVEX_L2_K_B, /* 11617 */ + IC_EVEX_L2_XS_K_B, /* 11618 */ + IC_EVEX_L2_XS_K_B, /* 11619 */ + IC_EVEX_L2_XD_K_B, /* 11620 */ + IC_EVEX_L2_XD_K_B, /* 11621 */ + IC_EVEX_L2_XD_K_B, /* 11622 */ + IC_EVEX_L2_XD_K_B, /* 11623 */ + IC_EVEX_L2_W_K_B, /* 11624 */ + IC_EVEX_L2_W_K_B, /* 11625 */ + IC_EVEX_L2_W_XS_K_B, /* 11626 */ + IC_EVEX_L2_W_XS_K_B, /* 11627 */ + IC_EVEX_L2_W_XD_K_B, /* 11628 */ + IC_EVEX_L2_W_XD_K_B, /* 11629 */ + IC_EVEX_L2_W_XD_K_B, /* 11630 */ + IC_EVEX_L2_W_XD_K_B, /* 11631 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11632 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11633 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11634 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11635 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11636 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11637 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11638 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11639 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11640 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11641 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11642 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11643 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11644 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11645 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11646 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11647 */ + IC_EVEX_L2_K_B, /* 11648 */ + IC_EVEX_L2_K_B, /* 11649 */ + IC_EVEX_L2_XS_K_B, /* 11650 */ + IC_EVEX_L2_XS_K_B, /* 11651 */ + IC_EVEX_L2_XD_K_B, /* 11652 */ + IC_EVEX_L2_XD_K_B, /* 11653 */ + IC_EVEX_L2_XD_K_B, /* 11654 */ + IC_EVEX_L2_XD_K_B, /* 11655 */ + IC_EVEX_L2_W_K_B, /* 11656 */ + IC_EVEX_L2_W_K_B, /* 11657 */ + IC_EVEX_L2_W_XS_K_B, /* 11658 */ + IC_EVEX_L2_W_XS_K_B, /* 11659 */ + IC_EVEX_L2_W_XD_K_B, /* 11660 */ + IC_EVEX_L2_W_XD_K_B, /* 11661 */ + IC_EVEX_L2_W_XD_K_B, /* 11662 */ + IC_EVEX_L2_W_XD_K_B, /* 11663 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11664 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11665 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11666 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11667 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11668 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11669 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11670 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11671 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11672 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11673 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11674 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11675 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11676 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11677 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11678 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11679 */ + IC_EVEX_L2_K_B, /* 11680 */ + IC_EVEX_L2_K_B, /* 11681 */ + IC_EVEX_L2_XS_K_B, /* 11682 */ + IC_EVEX_L2_XS_K_B, /* 11683 */ + IC_EVEX_L2_XD_K_B, /* 11684 */ + IC_EVEX_L2_XD_K_B, /* 11685 */ + IC_EVEX_L2_XD_K_B, /* 11686 */ + IC_EVEX_L2_XD_K_B, /* 11687 */ + IC_EVEX_L2_W_K_B, /* 11688 */ + IC_EVEX_L2_W_K_B, /* 11689 */ + IC_EVEX_L2_W_XS_K_B, /* 11690 */ + IC_EVEX_L2_W_XS_K_B, /* 11691 */ + IC_EVEX_L2_W_XD_K_B, /* 11692 */ + IC_EVEX_L2_W_XD_K_B, /* 11693 */ + IC_EVEX_L2_W_XD_K_B, /* 11694 */ + IC_EVEX_L2_W_XD_K_B, /* 11695 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11696 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11697 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11698 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11699 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11700 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11701 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11702 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11703 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11704 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11705 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11706 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11707 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11708 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11709 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11710 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11711 */ + IC_EVEX_L2_K_B, /* 11712 */ + IC_EVEX_L2_K_B, /* 11713 */ + IC_EVEX_L2_XS_K_B, /* 11714 */ + IC_EVEX_L2_XS_K_B, /* 11715 */ + IC_EVEX_L2_XD_K_B, /* 11716 */ + IC_EVEX_L2_XD_K_B, /* 11717 */ + IC_EVEX_L2_XD_K_B, /* 11718 */ + IC_EVEX_L2_XD_K_B, /* 11719 */ + IC_EVEX_L2_W_K_B, /* 11720 */ + IC_EVEX_L2_W_K_B, /* 11721 */ + IC_EVEX_L2_W_XS_K_B, /* 11722 */ + IC_EVEX_L2_W_XS_K_B, /* 11723 */ + IC_EVEX_L2_W_XD_K_B, /* 11724 */ + IC_EVEX_L2_W_XD_K_B, /* 11725 */ + IC_EVEX_L2_W_XD_K_B, /* 11726 */ + IC_EVEX_L2_W_XD_K_B, /* 11727 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11728 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11729 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11730 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11731 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11732 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11733 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11734 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11735 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11736 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11737 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11738 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11739 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11740 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11741 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11742 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11743 */ + IC_EVEX_L2_K_B, /* 11744 */ + IC_EVEX_L2_K_B, /* 11745 */ + IC_EVEX_L2_XS_K_B, /* 11746 */ + IC_EVEX_L2_XS_K_B, /* 11747 */ + IC_EVEX_L2_XD_K_B, /* 11748 */ + IC_EVEX_L2_XD_K_B, /* 11749 */ + IC_EVEX_L2_XD_K_B, /* 11750 */ + IC_EVEX_L2_XD_K_B, /* 11751 */ + IC_EVEX_L2_W_K_B, /* 11752 */ + IC_EVEX_L2_W_K_B, /* 11753 */ + IC_EVEX_L2_W_XS_K_B, /* 11754 */ + IC_EVEX_L2_W_XS_K_B, /* 11755 */ + IC_EVEX_L2_W_XD_K_B, /* 11756 */ + IC_EVEX_L2_W_XD_K_B, /* 11757 */ + IC_EVEX_L2_W_XD_K_B, /* 11758 */ + IC_EVEX_L2_W_XD_K_B, /* 11759 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11760 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11761 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11762 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11763 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11764 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11765 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11766 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11767 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11768 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11769 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11770 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11771 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11772 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11773 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11774 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11775 */ + IC, /* 11776 */ + IC_64BIT, /* 11777 */ + IC_XS, /* 11778 */ + IC_64BIT_XS, /* 11779 */ + IC_XD, /* 11780 */ + IC_64BIT_XD, /* 11781 */ + IC_XS, /* 11782 */ + IC_64BIT_XS, /* 11783 */ + IC, /* 11784 */ + IC_64BIT_REXW, /* 11785 */ + IC_XS, /* 11786 */ + IC_64BIT_REXW_XS, /* 11787 */ + IC_XD, /* 11788 */ + IC_64BIT_REXW_XD, /* 11789 */ + IC_XS, /* 11790 */ + IC_64BIT_REXW_XS, /* 11791 */ + IC_OPSIZE, /* 11792 */ + IC_64BIT_OPSIZE, /* 11793 */ + IC_XS_OPSIZE, /* 11794 */ + IC_64BIT_XS_OPSIZE, /* 11795 */ + IC_XD_OPSIZE, /* 11796 */ + IC_64BIT_XD_OPSIZE, /* 11797 */ + IC_XS_OPSIZE, /* 11798 */ + IC_64BIT_XD_OPSIZE, /* 11799 */ + IC_OPSIZE, /* 11800 */ + IC_64BIT_REXW_OPSIZE, /* 11801 */ + IC_XS_OPSIZE, /* 11802 */ + IC_64BIT_REXW_XS, /* 11803 */ + IC_XD_OPSIZE, /* 11804 */ + IC_64BIT_REXW_XD, /* 11805 */ + IC_XS_OPSIZE, /* 11806 */ + IC_64BIT_REXW_XS, /* 11807 */ + IC_ADSIZE, /* 11808 */ + IC_64BIT_ADSIZE, /* 11809 */ + IC_XS_ADSIZE, /* 11810 */ + IC_64BIT_XS_ADSIZE, /* 11811 */ + IC_XD_ADSIZE, /* 11812 */ + IC_64BIT_XD_ADSIZE, /* 11813 */ + IC_XS_ADSIZE, /* 11814 */ + IC_64BIT_XD_ADSIZE, /* 11815 */ + IC_ADSIZE, /* 11816 */ + IC_64BIT_REXW_ADSIZE, /* 11817 */ + IC_XS_ADSIZE, /* 11818 */ + IC_64BIT_REXW_XS, /* 11819 */ + IC_XD_ADSIZE, /* 11820 */ + IC_64BIT_REXW_XD, /* 11821 */ + IC_XS_ADSIZE, /* 11822 */ + IC_64BIT_REXW_XS, /* 11823 */ + IC_OPSIZE_ADSIZE, /* 11824 */ + IC_64BIT_OPSIZE_ADSIZE, /* 11825 */ + IC_XS_OPSIZE, /* 11826 */ + IC_64BIT_XS_OPSIZE, /* 11827 */ + IC_XD_OPSIZE, /* 11828 */ + IC_64BIT_XD_OPSIZE, /* 11829 */ + IC_XS_OPSIZE, /* 11830 */ + IC_64BIT_XD_OPSIZE, /* 11831 */ + IC_OPSIZE_ADSIZE, /* 11832 */ + IC_64BIT_REXW_OPSIZE, /* 11833 */ + IC_XS_OPSIZE, /* 11834 */ + IC_64BIT_REXW_XS, /* 11835 */ + IC_XD_OPSIZE, /* 11836 */ + IC_64BIT_REXW_XD, /* 11837 */ + IC_XS_OPSIZE, /* 11838 */ + IC_64BIT_REXW_XS, /* 11839 */ + IC_VEX, /* 11840 */ + IC_VEX, /* 11841 */ + IC_VEX_XS, /* 11842 */ + IC_VEX_XS, /* 11843 */ + IC_VEX_XD, /* 11844 */ + IC_VEX_XD, /* 11845 */ + IC_VEX_XD, /* 11846 */ + IC_VEX_XD, /* 11847 */ + IC_VEX_W, /* 11848 */ + IC_VEX_W, /* 11849 */ + IC_VEX_W_XS, /* 11850 */ + IC_VEX_W_XS, /* 11851 */ + IC_VEX_W_XD, /* 11852 */ + IC_VEX_W_XD, /* 11853 */ + IC_VEX_W_XD, /* 11854 */ + IC_VEX_W_XD, /* 11855 */ + IC_VEX_OPSIZE, /* 11856 */ + IC_VEX_OPSIZE, /* 11857 */ + IC_VEX_OPSIZE, /* 11858 */ + IC_VEX_OPSIZE, /* 11859 */ + IC_VEX_OPSIZE, /* 11860 */ + IC_VEX_OPSIZE, /* 11861 */ + IC_VEX_OPSIZE, /* 11862 */ + IC_VEX_OPSIZE, /* 11863 */ + IC_VEX_W_OPSIZE, /* 11864 */ + IC_VEX_W_OPSIZE, /* 11865 */ + IC_VEX_W_OPSIZE, /* 11866 */ + IC_VEX_W_OPSIZE, /* 11867 */ + IC_VEX_W_OPSIZE, /* 11868 */ + IC_VEX_W_OPSIZE, /* 11869 */ + IC_VEX_W_OPSIZE, /* 11870 */ + IC_VEX_W_OPSIZE, /* 11871 */ + IC_VEX, /* 11872 */ + IC_VEX, /* 11873 */ + IC_VEX_XS, /* 11874 */ + IC_VEX_XS, /* 11875 */ + IC_VEX_XD, /* 11876 */ + IC_VEX_XD, /* 11877 */ + IC_VEX_XD, /* 11878 */ + IC_VEX_XD, /* 11879 */ + IC_VEX_W, /* 11880 */ + IC_VEX_W, /* 11881 */ + IC_VEX_W_XS, /* 11882 */ + IC_VEX_W_XS, /* 11883 */ + IC_VEX_W_XD, /* 11884 */ + IC_VEX_W_XD, /* 11885 */ + IC_VEX_W_XD, /* 11886 */ + IC_VEX_W_XD, /* 11887 */ + IC_VEX_OPSIZE, /* 11888 */ + IC_VEX_OPSIZE, /* 11889 */ + IC_VEX_OPSIZE, /* 11890 */ + IC_VEX_OPSIZE, /* 11891 */ + IC_VEX_OPSIZE, /* 11892 */ + IC_VEX_OPSIZE, /* 11893 */ + IC_VEX_OPSIZE, /* 11894 */ + IC_VEX_OPSIZE, /* 11895 */ + IC_VEX_W_OPSIZE, /* 11896 */ + IC_VEX_W_OPSIZE, /* 11897 */ + IC_VEX_W_OPSIZE, /* 11898 */ + IC_VEX_W_OPSIZE, /* 11899 */ + IC_VEX_W_OPSIZE, /* 11900 */ + IC_VEX_W_OPSIZE, /* 11901 */ + IC_VEX_W_OPSIZE, /* 11902 */ + IC_VEX_W_OPSIZE, /* 11903 */ + IC_VEX_L, /* 11904 */ + IC_VEX_L, /* 11905 */ + IC_VEX_L_XS, /* 11906 */ + IC_VEX_L_XS, /* 11907 */ + IC_VEX_L_XD, /* 11908 */ + IC_VEX_L_XD, /* 11909 */ + IC_VEX_L_XD, /* 11910 */ + IC_VEX_L_XD, /* 11911 */ + IC_VEX_L_W, /* 11912 */ + IC_VEX_L_W, /* 11913 */ + IC_VEX_L_W_XS, /* 11914 */ + IC_VEX_L_W_XS, /* 11915 */ + IC_VEX_L_W_XD, /* 11916 */ + IC_VEX_L_W_XD, /* 11917 */ + IC_VEX_L_W_XD, /* 11918 */ + IC_VEX_L_W_XD, /* 11919 */ + IC_VEX_L_OPSIZE, /* 11920 */ + IC_VEX_L_OPSIZE, /* 11921 */ + IC_VEX_L_OPSIZE, /* 11922 */ + IC_VEX_L_OPSIZE, /* 11923 */ + IC_VEX_L_OPSIZE, /* 11924 */ + IC_VEX_L_OPSIZE, /* 11925 */ + IC_VEX_L_OPSIZE, /* 11926 */ + IC_VEX_L_OPSIZE, /* 11927 */ + IC_VEX_L_W_OPSIZE, /* 11928 */ + IC_VEX_L_W_OPSIZE, /* 11929 */ + IC_VEX_L_W_OPSIZE, /* 11930 */ + IC_VEX_L_W_OPSIZE, /* 11931 */ + IC_VEX_L_W_OPSIZE, /* 11932 */ + IC_VEX_L_W_OPSIZE, /* 11933 */ + IC_VEX_L_W_OPSIZE, /* 11934 */ + IC_VEX_L_W_OPSIZE, /* 11935 */ + IC_VEX_L, /* 11936 */ + IC_VEX_L, /* 11937 */ + IC_VEX_L_XS, /* 11938 */ + IC_VEX_L_XS, /* 11939 */ + IC_VEX_L_XD, /* 11940 */ + IC_VEX_L_XD, /* 11941 */ + IC_VEX_L_XD, /* 11942 */ + IC_VEX_L_XD, /* 11943 */ + IC_VEX_L_W, /* 11944 */ + IC_VEX_L_W, /* 11945 */ + IC_VEX_L_W_XS, /* 11946 */ + IC_VEX_L_W_XS, /* 11947 */ + IC_VEX_L_W_XD, /* 11948 */ + IC_VEX_L_W_XD, /* 11949 */ + IC_VEX_L_W_XD, /* 11950 */ + IC_VEX_L_W_XD, /* 11951 */ + IC_VEX_L_OPSIZE, /* 11952 */ + IC_VEX_L_OPSIZE, /* 11953 */ + IC_VEX_L_OPSIZE, /* 11954 */ + IC_VEX_L_OPSIZE, /* 11955 */ + IC_VEX_L_OPSIZE, /* 11956 */ + IC_VEX_L_OPSIZE, /* 11957 */ + IC_VEX_L_OPSIZE, /* 11958 */ + IC_VEX_L_OPSIZE, /* 11959 */ + IC_VEX_L_W_OPSIZE, /* 11960 */ + IC_VEX_L_W_OPSIZE, /* 11961 */ + IC_VEX_L_W_OPSIZE, /* 11962 */ + IC_VEX_L_W_OPSIZE, /* 11963 */ + IC_VEX_L_W_OPSIZE, /* 11964 */ + IC_VEX_L_W_OPSIZE, /* 11965 */ + IC_VEX_L_W_OPSIZE, /* 11966 */ + IC_VEX_L_W_OPSIZE, /* 11967 */ + IC_VEX_L, /* 11968 */ + IC_VEX_L, /* 11969 */ + IC_VEX_L_XS, /* 11970 */ + IC_VEX_L_XS, /* 11971 */ + IC_VEX_L_XD, /* 11972 */ + IC_VEX_L_XD, /* 11973 */ + IC_VEX_L_XD, /* 11974 */ + IC_VEX_L_XD, /* 11975 */ + IC_VEX_L_W, /* 11976 */ + IC_VEX_L_W, /* 11977 */ + IC_VEX_L_W_XS, /* 11978 */ + IC_VEX_L_W_XS, /* 11979 */ + IC_VEX_L_W_XD, /* 11980 */ + IC_VEX_L_W_XD, /* 11981 */ + IC_VEX_L_W_XD, /* 11982 */ + IC_VEX_L_W_XD, /* 11983 */ + IC_VEX_L_OPSIZE, /* 11984 */ + IC_VEX_L_OPSIZE, /* 11985 */ + IC_VEX_L_OPSIZE, /* 11986 */ + IC_VEX_L_OPSIZE, /* 11987 */ + IC_VEX_L_OPSIZE, /* 11988 */ + IC_VEX_L_OPSIZE, /* 11989 */ + IC_VEX_L_OPSIZE, /* 11990 */ + IC_VEX_L_OPSIZE, /* 11991 */ + IC_VEX_L_W_OPSIZE, /* 11992 */ + IC_VEX_L_W_OPSIZE, /* 11993 */ + IC_VEX_L_W_OPSIZE, /* 11994 */ + IC_VEX_L_W_OPSIZE, /* 11995 */ + IC_VEX_L_W_OPSIZE, /* 11996 */ + IC_VEX_L_W_OPSIZE, /* 11997 */ + IC_VEX_L_W_OPSIZE, /* 11998 */ + IC_VEX_L_W_OPSIZE, /* 11999 */ + IC_VEX_L, /* 12000 */ + IC_VEX_L, /* 12001 */ + IC_VEX_L_XS, /* 12002 */ + IC_VEX_L_XS, /* 12003 */ + IC_VEX_L_XD, /* 12004 */ + IC_VEX_L_XD, /* 12005 */ + IC_VEX_L_XD, /* 12006 */ + IC_VEX_L_XD, /* 12007 */ + IC_VEX_L_W, /* 12008 */ + IC_VEX_L_W, /* 12009 */ + IC_VEX_L_W_XS, /* 12010 */ + IC_VEX_L_W_XS, /* 12011 */ + IC_VEX_L_W_XD, /* 12012 */ + IC_VEX_L_W_XD, /* 12013 */ + IC_VEX_L_W_XD, /* 12014 */ + IC_VEX_L_W_XD, /* 12015 */ + IC_VEX_L_OPSIZE, /* 12016 */ + IC_VEX_L_OPSIZE, /* 12017 */ + IC_VEX_L_OPSIZE, /* 12018 */ + IC_VEX_L_OPSIZE, /* 12019 */ + IC_VEX_L_OPSIZE, /* 12020 */ + IC_VEX_L_OPSIZE, /* 12021 */ + IC_VEX_L_OPSIZE, /* 12022 */ + IC_VEX_L_OPSIZE, /* 12023 */ + IC_VEX_L_W_OPSIZE, /* 12024 */ + IC_VEX_L_W_OPSIZE, /* 12025 */ + IC_VEX_L_W_OPSIZE, /* 12026 */ + IC_VEX_L_W_OPSIZE, /* 12027 */ + IC_VEX_L_W_OPSIZE, /* 12028 */ + IC_VEX_L_W_OPSIZE, /* 12029 */ + IC_VEX_L_W_OPSIZE, /* 12030 */ + IC_VEX_L_W_OPSIZE, /* 12031 */ + IC_EVEX_L2_K_B, /* 12032 */ + IC_EVEX_L2_K_B, /* 12033 */ + IC_EVEX_L2_XS_K_B, /* 12034 */ + IC_EVEX_L2_XS_K_B, /* 12035 */ + IC_EVEX_L2_XD_K_B, /* 12036 */ + IC_EVEX_L2_XD_K_B, /* 12037 */ + IC_EVEX_L2_XD_K_B, /* 12038 */ + IC_EVEX_L2_XD_K_B, /* 12039 */ + IC_EVEX_L2_W_K_B, /* 12040 */ + IC_EVEX_L2_W_K_B, /* 12041 */ + IC_EVEX_L2_W_XS_K_B, /* 12042 */ + IC_EVEX_L2_W_XS_K_B, /* 12043 */ + IC_EVEX_L2_W_XD_K_B, /* 12044 */ + IC_EVEX_L2_W_XD_K_B, /* 12045 */ + IC_EVEX_L2_W_XD_K_B, /* 12046 */ + IC_EVEX_L2_W_XD_K_B, /* 12047 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12048 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12049 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12050 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12051 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12052 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12053 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12054 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12055 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12056 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12057 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12058 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12059 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12060 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12061 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12062 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12063 */ + IC_EVEX_L2_K_B, /* 12064 */ + IC_EVEX_L2_K_B, /* 12065 */ + IC_EVEX_L2_XS_K_B, /* 12066 */ + IC_EVEX_L2_XS_K_B, /* 12067 */ + IC_EVEX_L2_XD_K_B, /* 12068 */ + IC_EVEX_L2_XD_K_B, /* 12069 */ + IC_EVEX_L2_XD_K_B, /* 12070 */ + IC_EVEX_L2_XD_K_B, /* 12071 */ + IC_EVEX_L2_W_K_B, /* 12072 */ + IC_EVEX_L2_W_K_B, /* 12073 */ + IC_EVEX_L2_W_XS_K_B, /* 12074 */ + IC_EVEX_L2_W_XS_K_B, /* 12075 */ + IC_EVEX_L2_W_XD_K_B, /* 12076 */ + IC_EVEX_L2_W_XD_K_B, /* 12077 */ + IC_EVEX_L2_W_XD_K_B, /* 12078 */ + IC_EVEX_L2_W_XD_K_B, /* 12079 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12080 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12081 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12082 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12083 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12084 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12085 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12086 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12087 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12088 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12089 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12090 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12091 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12092 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12093 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12094 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12095 */ + IC_EVEX_L2_K_B, /* 12096 */ + IC_EVEX_L2_K_B, /* 12097 */ + IC_EVEX_L2_XS_K_B, /* 12098 */ + IC_EVEX_L2_XS_K_B, /* 12099 */ + IC_EVEX_L2_XD_K_B, /* 12100 */ + IC_EVEX_L2_XD_K_B, /* 12101 */ + IC_EVEX_L2_XD_K_B, /* 12102 */ + IC_EVEX_L2_XD_K_B, /* 12103 */ + IC_EVEX_L2_W_K_B, /* 12104 */ + IC_EVEX_L2_W_K_B, /* 12105 */ + IC_EVEX_L2_W_XS_K_B, /* 12106 */ + IC_EVEX_L2_W_XS_K_B, /* 12107 */ + IC_EVEX_L2_W_XD_K_B, /* 12108 */ + IC_EVEX_L2_W_XD_K_B, /* 12109 */ + IC_EVEX_L2_W_XD_K_B, /* 12110 */ + IC_EVEX_L2_W_XD_K_B, /* 12111 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12112 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12113 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12114 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12115 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12116 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12117 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12118 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12119 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12120 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12121 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12122 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12123 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12124 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12125 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12126 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12127 */ + IC_EVEX_L2_K_B, /* 12128 */ + IC_EVEX_L2_K_B, /* 12129 */ + IC_EVEX_L2_XS_K_B, /* 12130 */ + IC_EVEX_L2_XS_K_B, /* 12131 */ + IC_EVEX_L2_XD_K_B, /* 12132 */ + IC_EVEX_L2_XD_K_B, /* 12133 */ + IC_EVEX_L2_XD_K_B, /* 12134 */ + IC_EVEX_L2_XD_K_B, /* 12135 */ + IC_EVEX_L2_W_K_B, /* 12136 */ + IC_EVEX_L2_W_K_B, /* 12137 */ + IC_EVEX_L2_W_XS_K_B, /* 12138 */ + IC_EVEX_L2_W_XS_K_B, /* 12139 */ + IC_EVEX_L2_W_XD_K_B, /* 12140 */ + IC_EVEX_L2_W_XD_K_B, /* 12141 */ + IC_EVEX_L2_W_XD_K_B, /* 12142 */ + IC_EVEX_L2_W_XD_K_B, /* 12143 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12144 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12145 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12146 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12147 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12148 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12149 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12150 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12151 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12152 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12153 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12154 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12155 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12156 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12157 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12158 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12159 */ + IC_EVEX_L2_K_B, /* 12160 */ + IC_EVEX_L2_K_B, /* 12161 */ + IC_EVEX_L2_XS_K_B, /* 12162 */ + IC_EVEX_L2_XS_K_B, /* 12163 */ + IC_EVEX_L2_XD_K_B, /* 12164 */ + IC_EVEX_L2_XD_K_B, /* 12165 */ + IC_EVEX_L2_XD_K_B, /* 12166 */ + IC_EVEX_L2_XD_K_B, /* 12167 */ + IC_EVEX_L2_W_K_B, /* 12168 */ + IC_EVEX_L2_W_K_B, /* 12169 */ + IC_EVEX_L2_W_XS_K_B, /* 12170 */ + IC_EVEX_L2_W_XS_K_B, /* 12171 */ + IC_EVEX_L2_W_XD_K_B, /* 12172 */ + IC_EVEX_L2_W_XD_K_B, /* 12173 */ + IC_EVEX_L2_W_XD_K_B, /* 12174 */ + IC_EVEX_L2_W_XD_K_B, /* 12175 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12176 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12177 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12178 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12179 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12180 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12181 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12182 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12183 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12184 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12185 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12186 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12187 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12188 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12189 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12190 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12191 */ + IC_EVEX_L2_K_B, /* 12192 */ + IC_EVEX_L2_K_B, /* 12193 */ + IC_EVEX_L2_XS_K_B, /* 12194 */ + IC_EVEX_L2_XS_K_B, /* 12195 */ + IC_EVEX_L2_XD_K_B, /* 12196 */ + IC_EVEX_L2_XD_K_B, /* 12197 */ + IC_EVEX_L2_XD_K_B, /* 12198 */ + IC_EVEX_L2_XD_K_B, /* 12199 */ + IC_EVEX_L2_W_K_B, /* 12200 */ + IC_EVEX_L2_W_K_B, /* 12201 */ + IC_EVEX_L2_W_XS_K_B, /* 12202 */ + IC_EVEX_L2_W_XS_K_B, /* 12203 */ + IC_EVEX_L2_W_XD_K_B, /* 12204 */ + IC_EVEX_L2_W_XD_K_B, /* 12205 */ + IC_EVEX_L2_W_XD_K_B, /* 12206 */ + IC_EVEX_L2_W_XD_K_B, /* 12207 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12208 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12209 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12210 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12211 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12212 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12213 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12214 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12215 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12216 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12217 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12218 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12219 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12220 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12221 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12222 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12223 */ + IC_EVEX_L2_K_B, /* 12224 */ + IC_EVEX_L2_K_B, /* 12225 */ + IC_EVEX_L2_XS_K_B, /* 12226 */ + IC_EVEX_L2_XS_K_B, /* 12227 */ + IC_EVEX_L2_XD_K_B, /* 12228 */ + IC_EVEX_L2_XD_K_B, /* 12229 */ + IC_EVEX_L2_XD_K_B, /* 12230 */ + IC_EVEX_L2_XD_K_B, /* 12231 */ + IC_EVEX_L2_W_K_B, /* 12232 */ + IC_EVEX_L2_W_K_B, /* 12233 */ + IC_EVEX_L2_W_XS_K_B, /* 12234 */ + IC_EVEX_L2_W_XS_K_B, /* 12235 */ + IC_EVEX_L2_W_XD_K_B, /* 12236 */ + IC_EVEX_L2_W_XD_K_B, /* 12237 */ + IC_EVEX_L2_W_XD_K_B, /* 12238 */ + IC_EVEX_L2_W_XD_K_B, /* 12239 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12240 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12241 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12242 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12243 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12244 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12245 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12246 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12247 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12248 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12249 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12250 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12251 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12252 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12253 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12254 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12255 */ + IC_EVEX_L2_K_B, /* 12256 */ + IC_EVEX_L2_K_B, /* 12257 */ + IC_EVEX_L2_XS_K_B, /* 12258 */ + IC_EVEX_L2_XS_K_B, /* 12259 */ + IC_EVEX_L2_XD_K_B, /* 12260 */ + IC_EVEX_L2_XD_K_B, /* 12261 */ + IC_EVEX_L2_XD_K_B, /* 12262 */ + IC_EVEX_L2_XD_K_B, /* 12263 */ + IC_EVEX_L2_W_K_B, /* 12264 */ + IC_EVEX_L2_W_K_B, /* 12265 */ + IC_EVEX_L2_W_XS_K_B, /* 12266 */ + IC_EVEX_L2_W_XS_K_B, /* 12267 */ + IC_EVEX_L2_W_XD_K_B, /* 12268 */ + IC_EVEX_L2_W_XD_K_B, /* 12269 */ + IC_EVEX_L2_W_XD_K_B, /* 12270 */ + IC_EVEX_L2_W_XD_K_B, /* 12271 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12272 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12273 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12274 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12275 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12276 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12277 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12278 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12279 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12280 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12281 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12282 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12283 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12284 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12285 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12286 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12287 */ + IC, /* 12288 */ + IC_64BIT, /* 12289 */ + IC_XS, /* 12290 */ + IC_64BIT_XS, /* 12291 */ + IC_XD, /* 12292 */ + IC_64BIT_XD, /* 12293 */ + IC_XS, /* 12294 */ + IC_64BIT_XS, /* 12295 */ + IC, /* 12296 */ + IC_64BIT_REXW, /* 12297 */ + IC_XS, /* 12298 */ + IC_64BIT_REXW_XS, /* 12299 */ + IC_XD, /* 12300 */ + IC_64BIT_REXW_XD, /* 12301 */ + IC_XS, /* 12302 */ + IC_64BIT_REXW_XS, /* 12303 */ + IC_OPSIZE, /* 12304 */ + IC_64BIT_OPSIZE, /* 12305 */ + IC_XS_OPSIZE, /* 12306 */ + IC_64BIT_XS_OPSIZE, /* 12307 */ + IC_XD_OPSIZE, /* 12308 */ + IC_64BIT_XD_OPSIZE, /* 12309 */ + IC_XS_OPSIZE, /* 12310 */ + IC_64BIT_XD_OPSIZE, /* 12311 */ + IC_OPSIZE, /* 12312 */ + IC_64BIT_REXW_OPSIZE, /* 12313 */ + IC_XS_OPSIZE, /* 12314 */ + IC_64BIT_REXW_XS, /* 12315 */ + IC_XD_OPSIZE, /* 12316 */ + IC_64BIT_REXW_XD, /* 12317 */ + IC_XS_OPSIZE, /* 12318 */ + IC_64BIT_REXW_XS, /* 12319 */ + IC_ADSIZE, /* 12320 */ + IC_64BIT_ADSIZE, /* 12321 */ + IC_XS_ADSIZE, /* 12322 */ + IC_64BIT_XS_ADSIZE, /* 12323 */ + IC_XD_ADSIZE, /* 12324 */ + IC_64BIT_XD_ADSIZE, /* 12325 */ + IC_XS_ADSIZE, /* 12326 */ + IC_64BIT_XD_ADSIZE, /* 12327 */ + IC_ADSIZE, /* 12328 */ + IC_64BIT_REXW_ADSIZE, /* 12329 */ + IC_XS_ADSIZE, /* 12330 */ + IC_64BIT_REXW_XS, /* 12331 */ + IC_XD_ADSIZE, /* 12332 */ + IC_64BIT_REXW_XD, /* 12333 */ + IC_XS_ADSIZE, /* 12334 */ + IC_64BIT_REXW_XS, /* 12335 */ + IC_OPSIZE_ADSIZE, /* 12336 */ + IC_64BIT_OPSIZE_ADSIZE, /* 12337 */ + IC_XS_OPSIZE, /* 12338 */ + IC_64BIT_XS_OPSIZE, /* 12339 */ + IC_XD_OPSIZE, /* 12340 */ + IC_64BIT_XD_OPSIZE, /* 12341 */ + IC_XS_OPSIZE, /* 12342 */ + IC_64BIT_XD_OPSIZE, /* 12343 */ + IC_OPSIZE_ADSIZE, /* 12344 */ + IC_64BIT_REXW_OPSIZE, /* 12345 */ + IC_XS_OPSIZE, /* 12346 */ + IC_64BIT_REXW_XS, /* 12347 */ + IC_XD_OPSIZE, /* 12348 */ + IC_64BIT_REXW_XD, /* 12349 */ + IC_XS_OPSIZE, /* 12350 */ + IC_64BIT_REXW_XS, /* 12351 */ + IC_VEX, /* 12352 */ + IC_VEX, /* 12353 */ + IC_VEX_XS, /* 12354 */ + IC_VEX_XS, /* 12355 */ + IC_VEX_XD, /* 12356 */ + IC_VEX_XD, /* 12357 */ + IC_VEX_XD, /* 12358 */ + IC_VEX_XD, /* 12359 */ + IC_VEX_W, /* 12360 */ + IC_VEX_W, /* 12361 */ + IC_VEX_W_XS, /* 12362 */ + IC_VEX_W_XS, /* 12363 */ + IC_VEX_W_XD, /* 12364 */ + IC_VEX_W_XD, /* 12365 */ + IC_VEX_W_XD, /* 12366 */ + IC_VEX_W_XD, /* 12367 */ + IC_VEX_OPSIZE, /* 12368 */ + IC_VEX_OPSIZE, /* 12369 */ + IC_VEX_OPSIZE, /* 12370 */ + IC_VEX_OPSIZE, /* 12371 */ + IC_VEX_OPSIZE, /* 12372 */ + IC_VEX_OPSIZE, /* 12373 */ + IC_VEX_OPSIZE, /* 12374 */ + IC_VEX_OPSIZE, /* 12375 */ + IC_VEX_W_OPSIZE, /* 12376 */ + IC_VEX_W_OPSIZE, /* 12377 */ + IC_VEX_W_OPSIZE, /* 12378 */ + IC_VEX_W_OPSIZE, /* 12379 */ + IC_VEX_W_OPSIZE, /* 12380 */ + IC_VEX_W_OPSIZE, /* 12381 */ + IC_VEX_W_OPSIZE, /* 12382 */ + IC_VEX_W_OPSIZE, /* 12383 */ + IC_VEX, /* 12384 */ + IC_VEX, /* 12385 */ + IC_VEX_XS, /* 12386 */ + IC_VEX_XS, /* 12387 */ + IC_VEX_XD, /* 12388 */ + IC_VEX_XD, /* 12389 */ + IC_VEX_XD, /* 12390 */ + IC_VEX_XD, /* 12391 */ + IC_VEX_W, /* 12392 */ + IC_VEX_W, /* 12393 */ + IC_VEX_W_XS, /* 12394 */ + IC_VEX_W_XS, /* 12395 */ + IC_VEX_W_XD, /* 12396 */ + IC_VEX_W_XD, /* 12397 */ + IC_VEX_W_XD, /* 12398 */ + IC_VEX_W_XD, /* 12399 */ + IC_VEX_OPSIZE, /* 12400 */ + IC_VEX_OPSIZE, /* 12401 */ + IC_VEX_OPSIZE, /* 12402 */ + IC_VEX_OPSIZE, /* 12403 */ + IC_VEX_OPSIZE, /* 12404 */ + IC_VEX_OPSIZE, /* 12405 */ + IC_VEX_OPSIZE, /* 12406 */ + IC_VEX_OPSIZE, /* 12407 */ + IC_VEX_W_OPSIZE, /* 12408 */ + IC_VEX_W_OPSIZE, /* 12409 */ + IC_VEX_W_OPSIZE, /* 12410 */ + IC_VEX_W_OPSIZE, /* 12411 */ + IC_VEX_W_OPSIZE, /* 12412 */ + IC_VEX_W_OPSIZE, /* 12413 */ + IC_VEX_W_OPSIZE, /* 12414 */ + IC_VEX_W_OPSIZE, /* 12415 */ + IC_VEX_L, /* 12416 */ + IC_VEX_L, /* 12417 */ + IC_VEX_L_XS, /* 12418 */ + IC_VEX_L_XS, /* 12419 */ + IC_VEX_L_XD, /* 12420 */ + IC_VEX_L_XD, /* 12421 */ + IC_VEX_L_XD, /* 12422 */ + IC_VEX_L_XD, /* 12423 */ + IC_VEX_L_W, /* 12424 */ + IC_VEX_L_W, /* 12425 */ + IC_VEX_L_W_XS, /* 12426 */ + IC_VEX_L_W_XS, /* 12427 */ + IC_VEX_L_W_XD, /* 12428 */ + IC_VEX_L_W_XD, /* 12429 */ + IC_VEX_L_W_XD, /* 12430 */ + IC_VEX_L_W_XD, /* 12431 */ + IC_VEX_L_OPSIZE, /* 12432 */ + IC_VEX_L_OPSIZE, /* 12433 */ + IC_VEX_L_OPSIZE, /* 12434 */ + IC_VEX_L_OPSIZE, /* 12435 */ + IC_VEX_L_OPSIZE, /* 12436 */ + IC_VEX_L_OPSIZE, /* 12437 */ + IC_VEX_L_OPSIZE, /* 12438 */ + IC_VEX_L_OPSIZE, /* 12439 */ + IC_VEX_L_W_OPSIZE, /* 12440 */ + IC_VEX_L_W_OPSIZE, /* 12441 */ + IC_VEX_L_W_OPSIZE, /* 12442 */ + IC_VEX_L_W_OPSIZE, /* 12443 */ + IC_VEX_L_W_OPSIZE, /* 12444 */ + IC_VEX_L_W_OPSIZE, /* 12445 */ + IC_VEX_L_W_OPSIZE, /* 12446 */ + IC_VEX_L_W_OPSIZE, /* 12447 */ + IC_VEX_L, /* 12448 */ + IC_VEX_L, /* 12449 */ + IC_VEX_L_XS, /* 12450 */ + IC_VEX_L_XS, /* 12451 */ + IC_VEX_L_XD, /* 12452 */ + IC_VEX_L_XD, /* 12453 */ + IC_VEX_L_XD, /* 12454 */ + IC_VEX_L_XD, /* 12455 */ + IC_VEX_L_W, /* 12456 */ + IC_VEX_L_W, /* 12457 */ + IC_VEX_L_W_XS, /* 12458 */ + IC_VEX_L_W_XS, /* 12459 */ + IC_VEX_L_W_XD, /* 12460 */ + IC_VEX_L_W_XD, /* 12461 */ + IC_VEX_L_W_XD, /* 12462 */ + IC_VEX_L_W_XD, /* 12463 */ + IC_VEX_L_OPSIZE, /* 12464 */ + IC_VEX_L_OPSIZE, /* 12465 */ + IC_VEX_L_OPSIZE, /* 12466 */ + IC_VEX_L_OPSIZE, /* 12467 */ + IC_VEX_L_OPSIZE, /* 12468 */ + IC_VEX_L_OPSIZE, /* 12469 */ + IC_VEX_L_OPSIZE, /* 12470 */ + IC_VEX_L_OPSIZE, /* 12471 */ + IC_VEX_L_W_OPSIZE, /* 12472 */ + IC_VEX_L_W_OPSIZE, /* 12473 */ + IC_VEX_L_W_OPSIZE, /* 12474 */ + IC_VEX_L_W_OPSIZE, /* 12475 */ + IC_VEX_L_W_OPSIZE, /* 12476 */ + IC_VEX_L_W_OPSIZE, /* 12477 */ + IC_VEX_L_W_OPSIZE, /* 12478 */ + IC_VEX_L_W_OPSIZE, /* 12479 */ + IC_VEX_L, /* 12480 */ + IC_VEX_L, /* 12481 */ + IC_VEX_L_XS, /* 12482 */ + IC_VEX_L_XS, /* 12483 */ + IC_VEX_L_XD, /* 12484 */ + IC_VEX_L_XD, /* 12485 */ + IC_VEX_L_XD, /* 12486 */ + IC_VEX_L_XD, /* 12487 */ + IC_VEX_L_W, /* 12488 */ + IC_VEX_L_W, /* 12489 */ + IC_VEX_L_W_XS, /* 12490 */ + IC_VEX_L_W_XS, /* 12491 */ + IC_VEX_L_W_XD, /* 12492 */ + IC_VEX_L_W_XD, /* 12493 */ + IC_VEX_L_W_XD, /* 12494 */ + IC_VEX_L_W_XD, /* 12495 */ + IC_VEX_L_OPSIZE, /* 12496 */ + IC_VEX_L_OPSIZE, /* 12497 */ + IC_VEX_L_OPSIZE, /* 12498 */ + IC_VEX_L_OPSIZE, /* 12499 */ + IC_VEX_L_OPSIZE, /* 12500 */ + IC_VEX_L_OPSIZE, /* 12501 */ + IC_VEX_L_OPSIZE, /* 12502 */ + IC_VEX_L_OPSIZE, /* 12503 */ + IC_VEX_L_W_OPSIZE, /* 12504 */ + IC_VEX_L_W_OPSIZE, /* 12505 */ + IC_VEX_L_W_OPSIZE, /* 12506 */ + IC_VEX_L_W_OPSIZE, /* 12507 */ + IC_VEX_L_W_OPSIZE, /* 12508 */ + IC_VEX_L_W_OPSIZE, /* 12509 */ + IC_VEX_L_W_OPSIZE, /* 12510 */ + IC_VEX_L_W_OPSIZE, /* 12511 */ + IC_VEX_L, /* 12512 */ + IC_VEX_L, /* 12513 */ + IC_VEX_L_XS, /* 12514 */ + IC_VEX_L_XS, /* 12515 */ + IC_VEX_L_XD, /* 12516 */ + IC_VEX_L_XD, /* 12517 */ + IC_VEX_L_XD, /* 12518 */ + IC_VEX_L_XD, /* 12519 */ + IC_VEX_L_W, /* 12520 */ + IC_VEX_L_W, /* 12521 */ + IC_VEX_L_W_XS, /* 12522 */ + IC_VEX_L_W_XS, /* 12523 */ + IC_VEX_L_W_XD, /* 12524 */ + IC_VEX_L_W_XD, /* 12525 */ + IC_VEX_L_W_XD, /* 12526 */ + IC_VEX_L_W_XD, /* 12527 */ + IC_VEX_L_OPSIZE, /* 12528 */ + IC_VEX_L_OPSIZE, /* 12529 */ + IC_VEX_L_OPSIZE, /* 12530 */ + IC_VEX_L_OPSIZE, /* 12531 */ + IC_VEX_L_OPSIZE, /* 12532 */ + IC_VEX_L_OPSIZE, /* 12533 */ + IC_VEX_L_OPSIZE, /* 12534 */ + IC_VEX_L_OPSIZE, /* 12535 */ + IC_VEX_L_W_OPSIZE, /* 12536 */ + IC_VEX_L_W_OPSIZE, /* 12537 */ + IC_VEX_L_W_OPSIZE, /* 12538 */ + IC_VEX_L_W_OPSIZE, /* 12539 */ + IC_VEX_L_W_OPSIZE, /* 12540 */ + IC_VEX_L_W_OPSIZE, /* 12541 */ + IC_VEX_L_W_OPSIZE, /* 12542 */ + IC_VEX_L_W_OPSIZE, /* 12543 */ + IC_EVEX_KZ_B, /* 12544 */ + IC_EVEX_KZ_B, /* 12545 */ + IC_EVEX_XS_KZ_B, /* 12546 */ + IC_EVEX_XS_KZ_B, /* 12547 */ + IC_EVEX_XD_KZ_B, /* 12548 */ + IC_EVEX_XD_KZ_B, /* 12549 */ + IC_EVEX_XD_KZ_B, /* 12550 */ + IC_EVEX_XD_KZ_B, /* 12551 */ + IC_EVEX_W_KZ_B, /* 12552 */ + IC_EVEX_W_KZ_B, /* 12553 */ + IC_EVEX_W_XS_KZ_B, /* 12554 */ + IC_EVEX_W_XS_KZ_B, /* 12555 */ + IC_EVEX_W_XD_KZ_B, /* 12556 */ + IC_EVEX_W_XD_KZ_B, /* 12557 */ + IC_EVEX_W_XD_KZ_B, /* 12558 */ + IC_EVEX_W_XD_KZ_B, /* 12559 */ + IC_EVEX_OPSIZE_KZ_B, /* 12560 */ + IC_EVEX_OPSIZE_KZ_B, /* 12561 */ + IC_EVEX_OPSIZE_KZ_B, /* 12562 */ + IC_EVEX_OPSIZE_KZ_B, /* 12563 */ + IC_EVEX_OPSIZE_KZ_B, /* 12564 */ + IC_EVEX_OPSIZE_KZ_B, /* 12565 */ + IC_EVEX_OPSIZE_KZ_B, /* 12566 */ + IC_EVEX_OPSIZE_KZ_B, /* 12567 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12568 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12569 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12570 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12571 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12572 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12573 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12574 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12575 */ + IC_EVEX_KZ_B, /* 12576 */ + IC_EVEX_KZ_B, /* 12577 */ + IC_EVEX_XS_KZ_B, /* 12578 */ + IC_EVEX_XS_KZ_B, /* 12579 */ + IC_EVEX_XD_KZ_B, /* 12580 */ + IC_EVEX_XD_KZ_B, /* 12581 */ + IC_EVEX_XD_KZ_B, /* 12582 */ + IC_EVEX_XD_KZ_B, /* 12583 */ + IC_EVEX_W_KZ_B, /* 12584 */ + IC_EVEX_W_KZ_B, /* 12585 */ + IC_EVEX_W_XS_KZ_B, /* 12586 */ + IC_EVEX_W_XS_KZ_B, /* 12587 */ + IC_EVEX_W_XD_KZ_B, /* 12588 */ + IC_EVEX_W_XD_KZ_B, /* 12589 */ + IC_EVEX_W_XD_KZ_B, /* 12590 */ + IC_EVEX_W_XD_KZ_B, /* 12591 */ + IC_EVEX_OPSIZE_KZ_B, /* 12592 */ + IC_EVEX_OPSIZE_KZ_B, /* 12593 */ + IC_EVEX_OPSIZE_KZ_B, /* 12594 */ + IC_EVEX_OPSIZE_KZ_B, /* 12595 */ + IC_EVEX_OPSIZE_KZ_B, /* 12596 */ + IC_EVEX_OPSIZE_KZ_B, /* 12597 */ + IC_EVEX_OPSIZE_KZ_B, /* 12598 */ + IC_EVEX_OPSIZE_KZ_B, /* 12599 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12600 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12601 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12602 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12603 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12604 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12605 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12606 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12607 */ + IC_EVEX_KZ_B, /* 12608 */ + IC_EVEX_KZ_B, /* 12609 */ + IC_EVEX_XS_KZ_B, /* 12610 */ + IC_EVEX_XS_KZ_B, /* 12611 */ + IC_EVEX_XD_KZ_B, /* 12612 */ + IC_EVEX_XD_KZ_B, /* 12613 */ + IC_EVEX_XD_KZ_B, /* 12614 */ + IC_EVEX_XD_KZ_B, /* 12615 */ + IC_EVEX_W_KZ_B, /* 12616 */ + IC_EVEX_W_KZ_B, /* 12617 */ + IC_EVEX_W_XS_KZ_B, /* 12618 */ + IC_EVEX_W_XS_KZ_B, /* 12619 */ + IC_EVEX_W_XD_KZ_B, /* 12620 */ + IC_EVEX_W_XD_KZ_B, /* 12621 */ + IC_EVEX_W_XD_KZ_B, /* 12622 */ + IC_EVEX_W_XD_KZ_B, /* 12623 */ + IC_EVEX_OPSIZE_KZ_B, /* 12624 */ + IC_EVEX_OPSIZE_KZ_B, /* 12625 */ + IC_EVEX_OPSIZE_KZ_B, /* 12626 */ + IC_EVEX_OPSIZE_KZ_B, /* 12627 */ + IC_EVEX_OPSIZE_KZ_B, /* 12628 */ + IC_EVEX_OPSIZE_KZ_B, /* 12629 */ + IC_EVEX_OPSIZE_KZ_B, /* 12630 */ + IC_EVEX_OPSIZE_KZ_B, /* 12631 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12632 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12633 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12634 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12635 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12636 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12637 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12638 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12639 */ + IC_EVEX_KZ_B, /* 12640 */ + IC_EVEX_KZ_B, /* 12641 */ + IC_EVEX_XS_KZ_B, /* 12642 */ + IC_EVEX_XS_KZ_B, /* 12643 */ + IC_EVEX_XD_KZ_B, /* 12644 */ + IC_EVEX_XD_KZ_B, /* 12645 */ + IC_EVEX_XD_KZ_B, /* 12646 */ + IC_EVEX_XD_KZ_B, /* 12647 */ + IC_EVEX_W_KZ_B, /* 12648 */ + IC_EVEX_W_KZ_B, /* 12649 */ + IC_EVEX_W_XS_KZ_B, /* 12650 */ + IC_EVEX_W_XS_KZ_B, /* 12651 */ + IC_EVEX_W_XD_KZ_B, /* 12652 */ + IC_EVEX_W_XD_KZ_B, /* 12653 */ + IC_EVEX_W_XD_KZ_B, /* 12654 */ + IC_EVEX_W_XD_KZ_B, /* 12655 */ + IC_EVEX_OPSIZE_KZ_B, /* 12656 */ + IC_EVEX_OPSIZE_KZ_B, /* 12657 */ + IC_EVEX_OPSIZE_KZ_B, /* 12658 */ + IC_EVEX_OPSIZE_KZ_B, /* 12659 */ + IC_EVEX_OPSIZE_KZ_B, /* 12660 */ + IC_EVEX_OPSIZE_KZ_B, /* 12661 */ + IC_EVEX_OPSIZE_KZ_B, /* 12662 */ + IC_EVEX_OPSIZE_KZ_B, /* 12663 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12664 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12665 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12666 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12667 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12668 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12669 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12670 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12671 */ + IC_EVEX_KZ_B, /* 12672 */ + IC_EVEX_KZ_B, /* 12673 */ + IC_EVEX_XS_KZ_B, /* 12674 */ + IC_EVEX_XS_KZ_B, /* 12675 */ + IC_EVEX_XD_KZ_B, /* 12676 */ + IC_EVEX_XD_KZ_B, /* 12677 */ + IC_EVEX_XD_KZ_B, /* 12678 */ + IC_EVEX_XD_KZ_B, /* 12679 */ + IC_EVEX_W_KZ_B, /* 12680 */ + IC_EVEX_W_KZ_B, /* 12681 */ + IC_EVEX_W_XS_KZ_B, /* 12682 */ + IC_EVEX_W_XS_KZ_B, /* 12683 */ + IC_EVEX_W_XD_KZ_B, /* 12684 */ + IC_EVEX_W_XD_KZ_B, /* 12685 */ + IC_EVEX_W_XD_KZ_B, /* 12686 */ + IC_EVEX_W_XD_KZ_B, /* 12687 */ + IC_EVEX_OPSIZE_KZ_B, /* 12688 */ + IC_EVEX_OPSIZE_KZ_B, /* 12689 */ + IC_EVEX_OPSIZE_KZ_B, /* 12690 */ + IC_EVEX_OPSIZE_KZ_B, /* 12691 */ + IC_EVEX_OPSIZE_KZ_B, /* 12692 */ + IC_EVEX_OPSIZE_KZ_B, /* 12693 */ + IC_EVEX_OPSIZE_KZ_B, /* 12694 */ + IC_EVEX_OPSIZE_KZ_B, /* 12695 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12696 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12697 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12698 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12699 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12700 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12701 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12702 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12703 */ + IC_EVEX_KZ_B, /* 12704 */ + IC_EVEX_KZ_B, /* 12705 */ + IC_EVEX_XS_KZ_B, /* 12706 */ + IC_EVEX_XS_KZ_B, /* 12707 */ + IC_EVEX_XD_KZ_B, /* 12708 */ + IC_EVEX_XD_KZ_B, /* 12709 */ + IC_EVEX_XD_KZ_B, /* 12710 */ + IC_EVEX_XD_KZ_B, /* 12711 */ + IC_EVEX_W_KZ_B, /* 12712 */ + IC_EVEX_W_KZ_B, /* 12713 */ + IC_EVEX_W_XS_KZ_B, /* 12714 */ + IC_EVEX_W_XS_KZ_B, /* 12715 */ + IC_EVEX_W_XD_KZ_B, /* 12716 */ + IC_EVEX_W_XD_KZ_B, /* 12717 */ + IC_EVEX_W_XD_KZ_B, /* 12718 */ + IC_EVEX_W_XD_KZ_B, /* 12719 */ + IC_EVEX_OPSIZE_KZ_B, /* 12720 */ + IC_EVEX_OPSIZE_KZ_B, /* 12721 */ + IC_EVEX_OPSIZE_KZ_B, /* 12722 */ + IC_EVEX_OPSIZE_KZ_B, /* 12723 */ + IC_EVEX_OPSIZE_KZ_B, /* 12724 */ + IC_EVEX_OPSIZE_KZ_B, /* 12725 */ + IC_EVEX_OPSIZE_KZ_B, /* 12726 */ + IC_EVEX_OPSIZE_KZ_B, /* 12727 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12728 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12729 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12730 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12731 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12732 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12733 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12734 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12735 */ + IC_EVEX_KZ_B, /* 12736 */ + IC_EVEX_KZ_B, /* 12737 */ + IC_EVEX_XS_KZ_B, /* 12738 */ + IC_EVEX_XS_KZ_B, /* 12739 */ + IC_EVEX_XD_KZ_B, /* 12740 */ + IC_EVEX_XD_KZ_B, /* 12741 */ + IC_EVEX_XD_KZ_B, /* 12742 */ + IC_EVEX_XD_KZ_B, /* 12743 */ + IC_EVEX_W_KZ_B, /* 12744 */ + IC_EVEX_W_KZ_B, /* 12745 */ + IC_EVEX_W_XS_KZ_B, /* 12746 */ + IC_EVEX_W_XS_KZ_B, /* 12747 */ + IC_EVEX_W_XD_KZ_B, /* 12748 */ + IC_EVEX_W_XD_KZ_B, /* 12749 */ + IC_EVEX_W_XD_KZ_B, /* 12750 */ + IC_EVEX_W_XD_KZ_B, /* 12751 */ + IC_EVEX_OPSIZE_KZ_B, /* 12752 */ + IC_EVEX_OPSIZE_KZ_B, /* 12753 */ + IC_EVEX_OPSIZE_KZ_B, /* 12754 */ + IC_EVEX_OPSIZE_KZ_B, /* 12755 */ + IC_EVEX_OPSIZE_KZ_B, /* 12756 */ + IC_EVEX_OPSIZE_KZ_B, /* 12757 */ + IC_EVEX_OPSIZE_KZ_B, /* 12758 */ + IC_EVEX_OPSIZE_KZ_B, /* 12759 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12760 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12761 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12762 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12763 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12764 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12765 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12766 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12767 */ + IC_EVEX_KZ_B, /* 12768 */ + IC_EVEX_KZ_B, /* 12769 */ + IC_EVEX_XS_KZ_B, /* 12770 */ + IC_EVEX_XS_KZ_B, /* 12771 */ + IC_EVEX_XD_KZ_B, /* 12772 */ + IC_EVEX_XD_KZ_B, /* 12773 */ + IC_EVEX_XD_KZ_B, /* 12774 */ + IC_EVEX_XD_KZ_B, /* 12775 */ + IC_EVEX_W_KZ_B, /* 12776 */ + IC_EVEX_W_KZ_B, /* 12777 */ + IC_EVEX_W_XS_KZ_B, /* 12778 */ + IC_EVEX_W_XS_KZ_B, /* 12779 */ + IC_EVEX_W_XD_KZ_B, /* 12780 */ + IC_EVEX_W_XD_KZ_B, /* 12781 */ + IC_EVEX_W_XD_KZ_B, /* 12782 */ + IC_EVEX_W_XD_KZ_B, /* 12783 */ + IC_EVEX_OPSIZE_KZ_B, /* 12784 */ + IC_EVEX_OPSIZE_KZ_B, /* 12785 */ + IC_EVEX_OPSIZE_KZ_B, /* 12786 */ + IC_EVEX_OPSIZE_KZ_B, /* 12787 */ + IC_EVEX_OPSIZE_KZ_B, /* 12788 */ + IC_EVEX_OPSIZE_KZ_B, /* 12789 */ + IC_EVEX_OPSIZE_KZ_B, /* 12790 */ + IC_EVEX_OPSIZE_KZ_B, /* 12791 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12792 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12793 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12794 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12795 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12796 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12797 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12798 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12799 */ + IC, /* 12800 */ + IC_64BIT, /* 12801 */ + IC_XS, /* 12802 */ + IC_64BIT_XS, /* 12803 */ + IC_XD, /* 12804 */ + IC_64BIT_XD, /* 12805 */ + IC_XS, /* 12806 */ + IC_64BIT_XS, /* 12807 */ + IC, /* 12808 */ + IC_64BIT_REXW, /* 12809 */ + IC_XS, /* 12810 */ + IC_64BIT_REXW_XS, /* 12811 */ + IC_XD, /* 12812 */ + IC_64BIT_REXW_XD, /* 12813 */ + IC_XS, /* 12814 */ + IC_64BIT_REXW_XS, /* 12815 */ + IC_OPSIZE, /* 12816 */ + IC_64BIT_OPSIZE, /* 12817 */ + IC_XS_OPSIZE, /* 12818 */ + IC_64BIT_XS_OPSIZE, /* 12819 */ + IC_XD_OPSIZE, /* 12820 */ + IC_64BIT_XD_OPSIZE, /* 12821 */ + IC_XS_OPSIZE, /* 12822 */ + IC_64BIT_XD_OPSIZE, /* 12823 */ + IC_OPSIZE, /* 12824 */ + IC_64BIT_REXW_OPSIZE, /* 12825 */ + IC_XS_OPSIZE, /* 12826 */ + IC_64BIT_REXW_XS, /* 12827 */ + IC_XD_OPSIZE, /* 12828 */ + IC_64BIT_REXW_XD, /* 12829 */ + IC_XS_OPSIZE, /* 12830 */ + IC_64BIT_REXW_XS, /* 12831 */ + IC_ADSIZE, /* 12832 */ + IC_64BIT_ADSIZE, /* 12833 */ + IC_XS_ADSIZE, /* 12834 */ + IC_64BIT_XS_ADSIZE, /* 12835 */ + IC_XD_ADSIZE, /* 12836 */ + IC_64BIT_XD_ADSIZE, /* 12837 */ + IC_XS_ADSIZE, /* 12838 */ + IC_64BIT_XD_ADSIZE, /* 12839 */ + IC_ADSIZE, /* 12840 */ + IC_64BIT_REXW_ADSIZE, /* 12841 */ + IC_XS_ADSIZE, /* 12842 */ + IC_64BIT_REXW_XS, /* 12843 */ + IC_XD_ADSIZE, /* 12844 */ + IC_64BIT_REXW_XD, /* 12845 */ + IC_XS_ADSIZE, /* 12846 */ + IC_64BIT_REXW_XS, /* 12847 */ + IC_OPSIZE_ADSIZE, /* 12848 */ + IC_64BIT_OPSIZE_ADSIZE, /* 12849 */ + IC_XS_OPSIZE, /* 12850 */ + IC_64BIT_XS_OPSIZE, /* 12851 */ + IC_XD_OPSIZE, /* 12852 */ + IC_64BIT_XD_OPSIZE, /* 12853 */ + IC_XS_OPSIZE, /* 12854 */ + IC_64BIT_XD_OPSIZE, /* 12855 */ + IC_OPSIZE_ADSIZE, /* 12856 */ + IC_64BIT_REXW_OPSIZE, /* 12857 */ + IC_XS_OPSIZE, /* 12858 */ + IC_64BIT_REXW_XS, /* 12859 */ + IC_XD_OPSIZE, /* 12860 */ + IC_64BIT_REXW_XD, /* 12861 */ + IC_XS_OPSIZE, /* 12862 */ + IC_64BIT_REXW_XS, /* 12863 */ + IC_VEX, /* 12864 */ + IC_VEX, /* 12865 */ + IC_VEX_XS, /* 12866 */ + IC_VEX_XS, /* 12867 */ + IC_VEX_XD, /* 12868 */ + IC_VEX_XD, /* 12869 */ + IC_VEX_XD, /* 12870 */ + IC_VEX_XD, /* 12871 */ + IC_VEX_W, /* 12872 */ + IC_VEX_W, /* 12873 */ + IC_VEX_W_XS, /* 12874 */ + IC_VEX_W_XS, /* 12875 */ + IC_VEX_W_XD, /* 12876 */ + IC_VEX_W_XD, /* 12877 */ + IC_VEX_W_XD, /* 12878 */ + IC_VEX_W_XD, /* 12879 */ + IC_VEX_OPSIZE, /* 12880 */ + IC_VEX_OPSIZE, /* 12881 */ + IC_VEX_OPSIZE, /* 12882 */ + IC_VEX_OPSIZE, /* 12883 */ + IC_VEX_OPSIZE, /* 12884 */ + IC_VEX_OPSIZE, /* 12885 */ + IC_VEX_OPSIZE, /* 12886 */ + IC_VEX_OPSIZE, /* 12887 */ + IC_VEX_W_OPSIZE, /* 12888 */ + IC_VEX_W_OPSIZE, /* 12889 */ + IC_VEX_W_OPSIZE, /* 12890 */ + IC_VEX_W_OPSIZE, /* 12891 */ + IC_VEX_W_OPSIZE, /* 12892 */ + IC_VEX_W_OPSIZE, /* 12893 */ + IC_VEX_W_OPSIZE, /* 12894 */ + IC_VEX_W_OPSIZE, /* 12895 */ + IC_VEX, /* 12896 */ + IC_VEX, /* 12897 */ + IC_VEX_XS, /* 12898 */ + IC_VEX_XS, /* 12899 */ + IC_VEX_XD, /* 12900 */ + IC_VEX_XD, /* 12901 */ + IC_VEX_XD, /* 12902 */ + IC_VEX_XD, /* 12903 */ + IC_VEX_W, /* 12904 */ + IC_VEX_W, /* 12905 */ + IC_VEX_W_XS, /* 12906 */ + IC_VEX_W_XS, /* 12907 */ + IC_VEX_W_XD, /* 12908 */ + IC_VEX_W_XD, /* 12909 */ + IC_VEX_W_XD, /* 12910 */ + IC_VEX_W_XD, /* 12911 */ + IC_VEX_OPSIZE, /* 12912 */ + IC_VEX_OPSIZE, /* 12913 */ + IC_VEX_OPSIZE, /* 12914 */ + IC_VEX_OPSIZE, /* 12915 */ + IC_VEX_OPSIZE, /* 12916 */ + IC_VEX_OPSIZE, /* 12917 */ + IC_VEX_OPSIZE, /* 12918 */ + IC_VEX_OPSIZE, /* 12919 */ + IC_VEX_W_OPSIZE, /* 12920 */ + IC_VEX_W_OPSIZE, /* 12921 */ + IC_VEX_W_OPSIZE, /* 12922 */ + IC_VEX_W_OPSIZE, /* 12923 */ + IC_VEX_W_OPSIZE, /* 12924 */ + IC_VEX_W_OPSIZE, /* 12925 */ + IC_VEX_W_OPSIZE, /* 12926 */ + IC_VEX_W_OPSIZE, /* 12927 */ + IC_VEX_L, /* 12928 */ + IC_VEX_L, /* 12929 */ + IC_VEX_L_XS, /* 12930 */ + IC_VEX_L_XS, /* 12931 */ + IC_VEX_L_XD, /* 12932 */ + IC_VEX_L_XD, /* 12933 */ + IC_VEX_L_XD, /* 12934 */ + IC_VEX_L_XD, /* 12935 */ + IC_VEX_L_W, /* 12936 */ + IC_VEX_L_W, /* 12937 */ + IC_VEX_L_W_XS, /* 12938 */ + IC_VEX_L_W_XS, /* 12939 */ + IC_VEX_L_W_XD, /* 12940 */ + IC_VEX_L_W_XD, /* 12941 */ + IC_VEX_L_W_XD, /* 12942 */ + IC_VEX_L_W_XD, /* 12943 */ + IC_VEX_L_OPSIZE, /* 12944 */ + IC_VEX_L_OPSIZE, /* 12945 */ + IC_VEX_L_OPSIZE, /* 12946 */ + IC_VEX_L_OPSIZE, /* 12947 */ + IC_VEX_L_OPSIZE, /* 12948 */ + IC_VEX_L_OPSIZE, /* 12949 */ + IC_VEX_L_OPSIZE, /* 12950 */ + IC_VEX_L_OPSIZE, /* 12951 */ + IC_VEX_L_W_OPSIZE, /* 12952 */ + IC_VEX_L_W_OPSIZE, /* 12953 */ + IC_VEX_L_W_OPSIZE, /* 12954 */ + IC_VEX_L_W_OPSIZE, /* 12955 */ + IC_VEX_L_W_OPSIZE, /* 12956 */ + IC_VEX_L_W_OPSIZE, /* 12957 */ + IC_VEX_L_W_OPSIZE, /* 12958 */ + IC_VEX_L_W_OPSIZE, /* 12959 */ + IC_VEX_L, /* 12960 */ + IC_VEX_L, /* 12961 */ + IC_VEX_L_XS, /* 12962 */ + IC_VEX_L_XS, /* 12963 */ + IC_VEX_L_XD, /* 12964 */ + IC_VEX_L_XD, /* 12965 */ + IC_VEX_L_XD, /* 12966 */ + IC_VEX_L_XD, /* 12967 */ + IC_VEX_L_W, /* 12968 */ + IC_VEX_L_W, /* 12969 */ + IC_VEX_L_W_XS, /* 12970 */ + IC_VEX_L_W_XS, /* 12971 */ + IC_VEX_L_W_XD, /* 12972 */ + IC_VEX_L_W_XD, /* 12973 */ + IC_VEX_L_W_XD, /* 12974 */ + IC_VEX_L_W_XD, /* 12975 */ + IC_VEX_L_OPSIZE, /* 12976 */ + IC_VEX_L_OPSIZE, /* 12977 */ + IC_VEX_L_OPSIZE, /* 12978 */ + IC_VEX_L_OPSIZE, /* 12979 */ + IC_VEX_L_OPSIZE, /* 12980 */ + IC_VEX_L_OPSIZE, /* 12981 */ + IC_VEX_L_OPSIZE, /* 12982 */ + IC_VEX_L_OPSIZE, /* 12983 */ + IC_VEX_L_W_OPSIZE, /* 12984 */ + IC_VEX_L_W_OPSIZE, /* 12985 */ + IC_VEX_L_W_OPSIZE, /* 12986 */ + IC_VEX_L_W_OPSIZE, /* 12987 */ + IC_VEX_L_W_OPSIZE, /* 12988 */ + IC_VEX_L_W_OPSIZE, /* 12989 */ + IC_VEX_L_W_OPSIZE, /* 12990 */ + IC_VEX_L_W_OPSIZE, /* 12991 */ + IC_VEX_L, /* 12992 */ + IC_VEX_L, /* 12993 */ + IC_VEX_L_XS, /* 12994 */ + IC_VEX_L_XS, /* 12995 */ + IC_VEX_L_XD, /* 12996 */ + IC_VEX_L_XD, /* 12997 */ + IC_VEX_L_XD, /* 12998 */ + IC_VEX_L_XD, /* 12999 */ + IC_VEX_L_W, /* 13000 */ + IC_VEX_L_W, /* 13001 */ + IC_VEX_L_W_XS, /* 13002 */ + IC_VEX_L_W_XS, /* 13003 */ + IC_VEX_L_W_XD, /* 13004 */ + IC_VEX_L_W_XD, /* 13005 */ + IC_VEX_L_W_XD, /* 13006 */ + IC_VEX_L_W_XD, /* 13007 */ + IC_VEX_L_OPSIZE, /* 13008 */ + IC_VEX_L_OPSIZE, /* 13009 */ + IC_VEX_L_OPSIZE, /* 13010 */ + IC_VEX_L_OPSIZE, /* 13011 */ + IC_VEX_L_OPSIZE, /* 13012 */ + IC_VEX_L_OPSIZE, /* 13013 */ + IC_VEX_L_OPSIZE, /* 13014 */ + IC_VEX_L_OPSIZE, /* 13015 */ + IC_VEX_L_W_OPSIZE, /* 13016 */ + IC_VEX_L_W_OPSIZE, /* 13017 */ + IC_VEX_L_W_OPSIZE, /* 13018 */ + IC_VEX_L_W_OPSIZE, /* 13019 */ + IC_VEX_L_W_OPSIZE, /* 13020 */ + IC_VEX_L_W_OPSIZE, /* 13021 */ + IC_VEX_L_W_OPSIZE, /* 13022 */ + IC_VEX_L_W_OPSIZE, /* 13023 */ + IC_VEX_L, /* 13024 */ + IC_VEX_L, /* 13025 */ + IC_VEX_L_XS, /* 13026 */ + IC_VEX_L_XS, /* 13027 */ + IC_VEX_L_XD, /* 13028 */ + IC_VEX_L_XD, /* 13029 */ + IC_VEX_L_XD, /* 13030 */ + IC_VEX_L_XD, /* 13031 */ + IC_VEX_L_W, /* 13032 */ + IC_VEX_L_W, /* 13033 */ + IC_VEX_L_W_XS, /* 13034 */ + IC_VEX_L_W_XS, /* 13035 */ + IC_VEX_L_W_XD, /* 13036 */ + IC_VEX_L_W_XD, /* 13037 */ + IC_VEX_L_W_XD, /* 13038 */ + IC_VEX_L_W_XD, /* 13039 */ + IC_VEX_L_OPSIZE, /* 13040 */ + IC_VEX_L_OPSIZE, /* 13041 */ + IC_VEX_L_OPSIZE, /* 13042 */ + IC_VEX_L_OPSIZE, /* 13043 */ + IC_VEX_L_OPSIZE, /* 13044 */ + IC_VEX_L_OPSIZE, /* 13045 */ + IC_VEX_L_OPSIZE, /* 13046 */ + IC_VEX_L_OPSIZE, /* 13047 */ + IC_VEX_L_W_OPSIZE, /* 13048 */ + IC_VEX_L_W_OPSIZE, /* 13049 */ + IC_VEX_L_W_OPSIZE, /* 13050 */ + IC_VEX_L_W_OPSIZE, /* 13051 */ + IC_VEX_L_W_OPSIZE, /* 13052 */ + IC_VEX_L_W_OPSIZE, /* 13053 */ + IC_VEX_L_W_OPSIZE, /* 13054 */ + IC_VEX_L_W_OPSIZE, /* 13055 */ + IC_EVEX_L_KZ_B, /* 13056 */ + IC_EVEX_L_KZ_B, /* 13057 */ + IC_EVEX_L_XS_KZ_B, /* 13058 */ + IC_EVEX_L_XS_KZ_B, /* 13059 */ + IC_EVEX_L_XD_KZ_B, /* 13060 */ + IC_EVEX_L_XD_KZ_B, /* 13061 */ + IC_EVEX_L_XD_KZ_B, /* 13062 */ + IC_EVEX_L_XD_KZ_B, /* 13063 */ + IC_EVEX_L_W_KZ_B, /* 13064 */ + IC_EVEX_L_W_KZ_B, /* 13065 */ + IC_EVEX_L_W_XS_KZ_B, /* 13066 */ + IC_EVEX_L_W_XS_KZ_B, /* 13067 */ + IC_EVEX_L_W_XD_KZ_B, /* 13068 */ + IC_EVEX_L_W_XD_KZ_B, /* 13069 */ + IC_EVEX_L_W_XD_KZ_B, /* 13070 */ + IC_EVEX_L_W_XD_KZ_B, /* 13071 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13072 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13073 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13074 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13075 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13076 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13077 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13078 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13079 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13080 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13081 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13082 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13083 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13084 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13085 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13086 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13087 */ + IC_EVEX_L_KZ_B, /* 13088 */ + IC_EVEX_L_KZ_B, /* 13089 */ + IC_EVEX_L_XS_KZ_B, /* 13090 */ + IC_EVEX_L_XS_KZ_B, /* 13091 */ + IC_EVEX_L_XD_KZ_B, /* 13092 */ + IC_EVEX_L_XD_KZ_B, /* 13093 */ + IC_EVEX_L_XD_KZ_B, /* 13094 */ + IC_EVEX_L_XD_KZ_B, /* 13095 */ + IC_EVEX_L_W_KZ_B, /* 13096 */ + IC_EVEX_L_W_KZ_B, /* 13097 */ + IC_EVEX_L_W_XS_KZ_B, /* 13098 */ + IC_EVEX_L_W_XS_KZ_B, /* 13099 */ + IC_EVEX_L_W_XD_KZ_B, /* 13100 */ + IC_EVEX_L_W_XD_KZ_B, /* 13101 */ + IC_EVEX_L_W_XD_KZ_B, /* 13102 */ + IC_EVEX_L_W_XD_KZ_B, /* 13103 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13104 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13105 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13106 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13107 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13108 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13109 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13110 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13111 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13112 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13113 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13114 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13115 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13116 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13117 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13118 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13119 */ + IC_EVEX_L_KZ_B, /* 13120 */ + IC_EVEX_L_KZ_B, /* 13121 */ + IC_EVEX_L_XS_KZ_B, /* 13122 */ + IC_EVEX_L_XS_KZ_B, /* 13123 */ + IC_EVEX_L_XD_KZ_B, /* 13124 */ + IC_EVEX_L_XD_KZ_B, /* 13125 */ + IC_EVEX_L_XD_KZ_B, /* 13126 */ + IC_EVEX_L_XD_KZ_B, /* 13127 */ + IC_EVEX_L_W_KZ_B, /* 13128 */ + IC_EVEX_L_W_KZ_B, /* 13129 */ + IC_EVEX_L_W_XS_KZ_B, /* 13130 */ + IC_EVEX_L_W_XS_KZ_B, /* 13131 */ + IC_EVEX_L_W_XD_KZ_B, /* 13132 */ + IC_EVEX_L_W_XD_KZ_B, /* 13133 */ + IC_EVEX_L_W_XD_KZ_B, /* 13134 */ + IC_EVEX_L_W_XD_KZ_B, /* 13135 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13136 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13137 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13138 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13139 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13140 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13141 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13142 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13143 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13144 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13145 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13146 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13147 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13148 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13149 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13150 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13151 */ + IC_EVEX_L_KZ_B, /* 13152 */ + IC_EVEX_L_KZ_B, /* 13153 */ + IC_EVEX_L_XS_KZ_B, /* 13154 */ + IC_EVEX_L_XS_KZ_B, /* 13155 */ + IC_EVEX_L_XD_KZ_B, /* 13156 */ + IC_EVEX_L_XD_KZ_B, /* 13157 */ + IC_EVEX_L_XD_KZ_B, /* 13158 */ + IC_EVEX_L_XD_KZ_B, /* 13159 */ + IC_EVEX_L_W_KZ_B, /* 13160 */ + IC_EVEX_L_W_KZ_B, /* 13161 */ + IC_EVEX_L_W_XS_KZ_B, /* 13162 */ + IC_EVEX_L_W_XS_KZ_B, /* 13163 */ + IC_EVEX_L_W_XD_KZ_B, /* 13164 */ + IC_EVEX_L_W_XD_KZ_B, /* 13165 */ + IC_EVEX_L_W_XD_KZ_B, /* 13166 */ + IC_EVEX_L_W_XD_KZ_B, /* 13167 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13168 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13169 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13170 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13171 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13172 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13173 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13174 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13175 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13176 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13177 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13178 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13179 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13180 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13181 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13182 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13183 */ + IC_EVEX_L_KZ_B, /* 13184 */ + IC_EVEX_L_KZ_B, /* 13185 */ + IC_EVEX_L_XS_KZ_B, /* 13186 */ + IC_EVEX_L_XS_KZ_B, /* 13187 */ + IC_EVEX_L_XD_KZ_B, /* 13188 */ + IC_EVEX_L_XD_KZ_B, /* 13189 */ + IC_EVEX_L_XD_KZ_B, /* 13190 */ + IC_EVEX_L_XD_KZ_B, /* 13191 */ + IC_EVEX_L_W_KZ_B, /* 13192 */ + IC_EVEX_L_W_KZ_B, /* 13193 */ + IC_EVEX_L_W_XS_KZ_B, /* 13194 */ + IC_EVEX_L_W_XS_KZ_B, /* 13195 */ + IC_EVEX_L_W_XD_KZ_B, /* 13196 */ + IC_EVEX_L_W_XD_KZ_B, /* 13197 */ + IC_EVEX_L_W_XD_KZ_B, /* 13198 */ + IC_EVEX_L_W_XD_KZ_B, /* 13199 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13200 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13201 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13202 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13203 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13204 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13205 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13206 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13207 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13208 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13209 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13210 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13211 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13212 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13213 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13214 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13215 */ + IC_EVEX_L_KZ_B, /* 13216 */ + IC_EVEX_L_KZ_B, /* 13217 */ + IC_EVEX_L_XS_KZ_B, /* 13218 */ + IC_EVEX_L_XS_KZ_B, /* 13219 */ + IC_EVEX_L_XD_KZ_B, /* 13220 */ + IC_EVEX_L_XD_KZ_B, /* 13221 */ + IC_EVEX_L_XD_KZ_B, /* 13222 */ + IC_EVEX_L_XD_KZ_B, /* 13223 */ + IC_EVEX_L_W_KZ_B, /* 13224 */ + IC_EVEX_L_W_KZ_B, /* 13225 */ + IC_EVEX_L_W_XS_KZ_B, /* 13226 */ + IC_EVEX_L_W_XS_KZ_B, /* 13227 */ + IC_EVEX_L_W_XD_KZ_B, /* 13228 */ + IC_EVEX_L_W_XD_KZ_B, /* 13229 */ + IC_EVEX_L_W_XD_KZ_B, /* 13230 */ + IC_EVEX_L_W_XD_KZ_B, /* 13231 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13232 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13233 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13234 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13235 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13236 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13237 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13238 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13239 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13240 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13241 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13242 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13243 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13244 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13245 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13246 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13247 */ + IC_EVEX_L_KZ_B, /* 13248 */ + IC_EVEX_L_KZ_B, /* 13249 */ + IC_EVEX_L_XS_KZ_B, /* 13250 */ + IC_EVEX_L_XS_KZ_B, /* 13251 */ + IC_EVEX_L_XD_KZ_B, /* 13252 */ + IC_EVEX_L_XD_KZ_B, /* 13253 */ + IC_EVEX_L_XD_KZ_B, /* 13254 */ + IC_EVEX_L_XD_KZ_B, /* 13255 */ + IC_EVEX_L_W_KZ_B, /* 13256 */ + IC_EVEX_L_W_KZ_B, /* 13257 */ + IC_EVEX_L_W_XS_KZ_B, /* 13258 */ + IC_EVEX_L_W_XS_KZ_B, /* 13259 */ + IC_EVEX_L_W_XD_KZ_B, /* 13260 */ + IC_EVEX_L_W_XD_KZ_B, /* 13261 */ + IC_EVEX_L_W_XD_KZ_B, /* 13262 */ + IC_EVEX_L_W_XD_KZ_B, /* 13263 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13264 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13265 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13266 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13267 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13268 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13269 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13270 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13271 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13272 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13273 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13274 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13275 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13276 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13277 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13278 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13279 */ + IC_EVEX_L_KZ_B, /* 13280 */ + IC_EVEX_L_KZ_B, /* 13281 */ + IC_EVEX_L_XS_KZ_B, /* 13282 */ + IC_EVEX_L_XS_KZ_B, /* 13283 */ + IC_EVEX_L_XD_KZ_B, /* 13284 */ + IC_EVEX_L_XD_KZ_B, /* 13285 */ + IC_EVEX_L_XD_KZ_B, /* 13286 */ + IC_EVEX_L_XD_KZ_B, /* 13287 */ + IC_EVEX_L_W_KZ_B, /* 13288 */ + IC_EVEX_L_W_KZ_B, /* 13289 */ + IC_EVEX_L_W_XS_KZ_B, /* 13290 */ + IC_EVEX_L_W_XS_KZ_B, /* 13291 */ + IC_EVEX_L_W_XD_KZ_B, /* 13292 */ + IC_EVEX_L_W_XD_KZ_B, /* 13293 */ + IC_EVEX_L_W_XD_KZ_B, /* 13294 */ + IC_EVEX_L_W_XD_KZ_B, /* 13295 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13296 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13297 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13298 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13299 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13300 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13301 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13302 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13303 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13304 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13305 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13306 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13307 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13308 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13309 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13310 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13311 */ + IC, /* 13312 */ + IC_64BIT, /* 13313 */ + IC_XS, /* 13314 */ + IC_64BIT_XS, /* 13315 */ + IC_XD, /* 13316 */ + IC_64BIT_XD, /* 13317 */ + IC_XS, /* 13318 */ + IC_64BIT_XS, /* 13319 */ + IC, /* 13320 */ + IC_64BIT_REXW, /* 13321 */ + IC_XS, /* 13322 */ + IC_64BIT_REXW_XS, /* 13323 */ + IC_XD, /* 13324 */ + IC_64BIT_REXW_XD, /* 13325 */ + IC_XS, /* 13326 */ + IC_64BIT_REXW_XS, /* 13327 */ + IC_OPSIZE, /* 13328 */ + IC_64BIT_OPSIZE, /* 13329 */ + IC_XS_OPSIZE, /* 13330 */ + IC_64BIT_XS_OPSIZE, /* 13331 */ + IC_XD_OPSIZE, /* 13332 */ + IC_64BIT_XD_OPSIZE, /* 13333 */ + IC_XS_OPSIZE, /* 13334 */ + IC_64BIT_XD_OPSIZE, /* 13335 */ + IC_OPSIZE, /* 13336 */ + IC_64BIT_REXW_OPSIZE, /* 13337 */ + IC_XS_OPSIZE, /* 13338 */ + IC_64BIT_REXW_XS, /* 13339 */ + IC_XD_OPSIZE, /* 13340 */ + IC_64BIT_REXW_XD, /* 13341 */ + IC_XS_OPSIZE, /* 13342 */ + IC_64BIT_REXW_XS, /* 13343 */ + IC_ADSIZE, /* 13344 */ + IC_64BIT_ADSIZE, /* 13345 */ + IC_XS_ADSIZE, /* 13346 */ + IC_64BIT_XS_ADSIZE, /* 13347 */ + IC_XD_ADSIZE, /* 13348 */ + IC_64BIT_XD_ADSIZE, /* 13349 */ + IC_XS_ADSIZE, /* 13350 */ + IC_64BIT_XD_ADSIZE, /* 13351 */ + IC_ADSIZE, /* 13352 */ + IC_64BIT_REXW_ADSIZE, /* 13353 */ + IC_XS_ADSIZE, /* 13354 */ + IC_64BIT_REXW_XS, /* 13355 */ + IC_XD_ADSIZE, /* 13356 */ + IC_64BIT_REXW_XD, /* 13357 */ + IC_XS_ADSIZE, /* 13358 */ + IC_64BIT_REXW_XS, /* 13359 */ + IC_OPSIZE_ADSIZE, /* 13360 */ + IC_64BIT_OPSIZE_ADSIZE, /* 13361 */ + IC_XS_OPSIZE, /* 13362 */ + IC_64BIT_XS_OPSIZE, /* 13363 */ + IC_XD_OPSIZE, /* 13364 */ + IC_64BIT_XD_OPSIZE, /* 13365 */ + IC_XS_OPSIZE, /* 13366 */ + IC_64BIT_XD_OPSIZE, /* 13367 */ + IC_OPSIZE_ADSIZE, /* 13368 */ + IC_64BIT_REXW_OPSIZE, /* 13369 */ + IC_XS_OPSIZE, /* 13370 */ + IC_64BIT_REXW_XS, /* 13371 */ + IC_XD_OPSIZE, /* 13372 */ + IC_64BIT_REXW_XD, /* 13373 */ + IC_XS_OPSIZE, /* 13374 */ + IC_64BIT_REXW_XS, /* 13375 */ + IC_VEX, /* 13376 */ + IC_VEX, /* 13377 */ + IC_VEX_XS, /* 13378 */ + IC_VEX_XS, /* 13379 */ + IC_VEX_XD, /* 13380 */ + IC_VEX_XD, /* 13381 */ + IC_VEX_XD, /* 13382 */ + IC_VEX_XD, /* 13383 */ + IC_VEX_W, /* 13384 */ + IC_VEX_W, /* 13385 */ + IC_VEX_W_XS, /* 13386 */ + IC_VEX_W_XS, /* 13387 */ + IC_VEX_W_XD, /* 13388 */ + IC_VEX_W_XD, /* 13389 */ + IC_VEX_W_XD, /* 13390 */ + IC_VEX_W_XD, /* 13391 */ + IC_VEX_OPSIZE, /* 13392 */ + IC_VEX_OPSIZE, /* 13393 */ + IC_VEX_OPSIZE, /* 13394 */ + IC_VEX_OPSIZE, /* 13395 */ + IC_VEX_OPSIZE, /* 13396 */ + IC_VEX_OPSIZE, /* 13397 */ + IC_VEX_OPSIZE, /* 13398 */ + IC_VEX_OPSIZE, /* 13399 */ + IC_VEX_W_OPSIZE, /* 13400 */ + IC_VEX_W_OPSIZE, /* 13401 */ + IC_VEX_W_OPSIZE, /* 13402 */ + IC_VEX_W_OPSIZE, /* 13403 */ + IC_VEX_W_OPSIZE, /* 13404 */ + IC_VEX_W_OPSIZE, /* 13405 */ + IC_VEX_W_OPSIZE, /* 13406 */ + IC_VEX_W_OPSIZE, /* 13407 */ + IC_VEX, /* 13408 */ + IC_VEX, /* 13409 */ + IC_VEX_XS, /* 13410 */ + IC_VEX_XS, /* 13411 */ + IC_VEX_XD, /* 13412 */ + IC_VEX_XD, /* 13413 */ + IC_VEX_XD, /* 13414 */ + IC_VEX_XD, /* 13415 */ + IC_VEX_W, /* 13416 */ + IC_VEX_W, /* 13417 */ + IC_VEX_W_XS, /* 13418 */ + IC_VEX_W_XS, /* 13419 */ + IC_VEX_W_XD, /* 13420 */ + IC_VEX_W_XD, /* 13421 */ + IC_VEX_W_XD, /* 13422 */ + IC_VEX_W_XD, /* 13423 */ + IC_VEX_OPSIZE, /* 13424 */ + IC_VEX_OPSIZE, /* 13425 */ + IC_VEX_OPSIZE, /* 13426 */ + IC_VEX_OPSIZE, /* 13427 */ + IC_VEX_OPSIZE, /* 13428 */ + IC_VEX_OPSIZE, /* 13429 */ + IC_VEX_OPSIZE, /* 13430 */ + IC_VEX_OPSIZE, /* 13431 */ + IC_VEX_W_OPSIZE, /* 13432 */ + IC_VEX_W_OPSIZE, /* 13433 */ + IC_VEX_W_OPSIZE, /* 13434 */ + IC_VEX_W_OPSIZE, /* 13435 */ + IC_VEX_W_OPSIZE, /* 13436 */ + IC_VEX_W_OPSIZE, /* 13437 */ + IC_VEX_W_OPSIZE, /* 13438 */ + IC_VEX_W_OPSIZE, /* 13439 */ + IC_VEX_L, /* 13440 */ + IC_VEX_L, /* 13441 */ + IC_VEX_L_XS, /* 13442 */ + IC_VEX_L_XS, /* 13443 */ + IC_VEX_L_XD, /* 13444 */ + IC_VEX_L_XD, /* 13445 */ + IC_VEX_L_XD, /* 13446 */ + IC_VEX_L_XD, /* 13447 */ + IC_VEX_L_W, /* 13448 */ + IC_VEX_L_W, /* 13449 */ + IC_VEX_L_W_XS, /* 13450 */ + IC_VEX_L_W_XS, /* 13451 */ + IC_VEX_L_W_XD, /* 13452 */ + IC_VEX_L_W_XD, /* 13453 */ + IC_VEX_L_W_XD, /* 13454 */ + IC_VEX_L_W_XD, /* 13455 */ + IC_VEX_L_OPSIZE, /* 13456 */ + IC_VEX_L_OPSIZE, /* 13457 */ + IC_VEX_L_OPSIZE, /* 13458 */ + IC_VEX_L_OPSIZE, /* 13459 */ + IC_VEX_L_OPSIZE, /* 13460 */ + IC_VEX_L_OPSIZE, /* 13461 */ + IC_VEX_L_OPSIZE, /* 13462 */ + IC_VEX_L_OPSIZE, /* 13463 */ + IC_VEX_L_W_OPSIZE, /* 13464 */ + IC_VEX_L_W_OPSIZE, /* 13465 */ + IC_VEX_L_W_OPSIZE, /* 13466 */ + IC_VEX_L_W_OPSIZE, /* 13467 */ + IC_VEX_L_W_OPSIZE, /* 13468 */ + IC_VEX_L_W_OPSIZE, /* 13469 */ + IC_VEX_L_W_OPSIZE, /* 13470 */ + IC_VEX_L_W_OPSIZE, /* 13471 */ + IC_VEX_L, /* 13472 */ + IC_VEX_L, /* 13473 */ + IC_VEX_L_XS, /* 13474 */ + IC_VEX_L_XS, /* 13475 */ + IC_VEX_L_XD, /* 13476 */ + IC_VEX_L_XD, /* 13477 */ + IC_VEX_L_XD, /* 13478 */ + IC_VEX_L_XD, /* 13479 */ + IC_VEX_L_W, /* 13480 */ + IC_VEX_L_W, /* 13481 */ + IC_VEX_L_W_XS, /* 13482 */ + IC_VEX_L_W_XS, /* 13483 */ + IC_VEX_L_W_XD, /* 13484 */ + IC_VEX_L_W_XD, /* 13485 */ + IC_VEX_L_W_XD, /* 13486 */ + IC_VEX_L_W_XD, /* 13487 */ + IC_VEX_L_OPSIZE, /* 13488 */ + IC_VEX_L_OPSIZE, /* 13489 */ + IC_VEX_L_OPSIZE, /* 13490 */ + IC_VEX_L_OPSIZE, /* 13491 */ + IC_VEX_L_OPSIZE, /* 13492 */ + IC_VEX_L_OPSIZE, /* 13493 */ + IC_VEX_L_OPSIZE, /* 13494 */ + IC_VEX_L_OPSIZE, /* 13495 */ + IC_VEX_L_W_OPSIZE, /* 13496 */ + IC_VEX_L_W_OPSIZE, /* 13497 */ + IC_VEX_L_W_OPSIZE, /* 13498 */ + IC_VEX_L_W_OPSIZE, /* 13499 */ + IC_VEX_L_W_OPSIZE, /* 13500 */ + IC_VEX_L_W_OPSIZE, /* 13501 */ + IC_VEX_L_W_OPSIZE, /* 13502 */ + IC_VEX_L_W_OPSIZE, /* 13503 */ + IC_VEX_L, /* 13504 */ + IC_VEX_L, /* 13505 */ + IC_VEX_L_XS, /* 13506 */ + IC_VEX_L_XS, /* 13507 */ + IC_VEX_L_XD, /* 13508 */ + IC_VEX_L_XD, /* 13509 */ + IC_VEX_L_XD, /* 13510 */ + IC_VEX_L_XD, /* 13511 */ + IC_VEX_L_W, /* 13512 */ + IC_VEX_L_W, /* 13513 */ + IC_VEX_L_W_XS, /* 13514 */ + IC_VEX_L_W_XS, /* 13515 */ + IC_VEX_L_W_XD, /* 13516 */ + IC_VEX_L_W_XD, /* 13517 */ + IC_VEX_L_W_XD, /* 13518 */ + IC_VEX_L_W_XD, /* 13519 */ + IC_VEX_L_OPSIZE, /* 13520 */ + IC_VEX_L_OPSIZE, /* 13521 */ + IC_VEX_L_OPSIZE, /* 13522 */ + IC_VEX_L_OPSIZE, /* 13523 */ + IC_VEX_L_OPSIZE, /* 13524 */ + IC_VEX_L_OPSIZE, /* 13525 */ + IC_VEX_L_OPSIZE, /* 13526 */ + IC_VEX_L_OPSIZE, /* 13527 */ + IC_VEX_L_W_OPSIZE, /* 13528 */ + IC_VEX_L_W_OPSIZE, /* 13529 */ + IC_VEX_L_W_OPSIZE, /* 13530 */ + IC_VEX_L_W_OPSIZE, /* 13531 */ + IC_VEX_L_W_OPSIZE, /* 13532 */ + IC_VEX_L_W_OPSIZE, /* 13533 */ + IC_VEX_L_W_OPSIZE, /* 13534 */ + IC_VEX_L_W_OPSIZE, /* 13535 */ + IC_VEX_L, /* 13536 */ + IC_VEX_L, /* 13537 */ + IC_VEX_L_XS, /* 13538 */ + IC_VEX_L_XS, /* 13539 */ + IC_VEX_L_XD, /* 13540 */ + IC_VEX_L_XD, /* 13541 */ + IC_VEX_L_XD, /* 13542 */ + IC_VEX_L_XD, /* 13543 */ + IC_VEX_L_W, /* 13544 */ + IC_VEX_L_W, /* 13545 */ + IC_VEX_L_W_XS, /* 13546 */ + IC_VEX_L_W_XS, /* 13547 */ + IC_VEX_L_W_XD, /* 13548 */ + IC_VEX_L_W_XD, /* 13549 */ + IC_VEX_L_W_XD, /* 13550 */ + IC_VEX_L_W_XD, /* 13551 */ + IC_VEX_L_OPSIZE, /* 13552 */ + IC_VEX_L_OPSIZE, /* 13553 */ + IC_VEX_L_OPSIZE, /* 13554 */ + IC_VEX_L_OPSIZE, /* 13555 */ + IC_VEX_L_OPSIZE, /* 13556 */ + IC_VEX_L_OPSIZE, /* 13557 */ + IC_VEX_L_OPSIZE, /* 13558 */ + IC_VEX_L_OPSIZE, /* 13559 */ + IC_VEX_L_W_OPSIZE, /* 13560 */ + IC_VEX_L_W_OPSIZE, /* 13561 */ + IC_VEX_L_W_OPSIZE, /* 13562 */ + IC_VEX_L_W_OPSIZE, /* 13563 */ + IC_VEX_L_W_OPSIZE, /* 13564 */ + IC_VEX_L_W_OPSIZE, /* 13565 */ + IC_VEX_L_W_OPSIZE, /* 13566 */ + IC_VEX_L_W_OPSIZE, /* 13567 */ + IC_EVEX_L2_KZ_B, /* 13568 */ + IC_EVEX_L2_KZ_B, /* 13569 */ + IC_EVEX_L2_XS_KZ_B, /* 13570 */ + IC_EVEX_L2_XS_KZ_B, /* 13571 */ + IC_EVEX_L2_XD_KZ_B, /* 13572 */ + IC_EVEX_L2_XD_KZ_B, /* 13573 */ + IC_EVEX_L2_XD_KZ_B, /* 13574 */ + IC_EVEX_L2_XD_KZ_B, /* 13575 */ + IC_EVEX_L2_W_KZ_B, /* 13576 */ + IC_EVEX_L2_W_KZ_B, /* 13577 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13578 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13579 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13580 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13581 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13582 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13583 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13584 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13585 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13586 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13587 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13588 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13589 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13590 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13591 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13592 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13593 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13594 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13595 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13596 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13597 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13598 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13599 */ + IC_EVEX_L2_KZ_B, /* 13600 */ + IC_EVEX_L2_KZ_B, /* 13601 */ + IC_EVEX_L2_XS_KZ_B, /* 13602 */ + IC_EVEX_L2_XS_KZ_B, /* 13603 */ + IC_EVEX_L2_XD_KZ_B, /* 13604 */ + IC_EVEX_L2_XD_KZ_B, /* 13605 */ + IC_EVEX_L2_XD_KZ_B, /* 13606 */ + IC_EVEX_L2_XD_KZ_B, /* 13607 */ + IC_EVEX_L2_W_KZ_B, /* 13608 */ + IC_EVEX_L2_W_KZ_B, /* 13609 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13610 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13611 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13612 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13613 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13614 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13615 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13616 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13617 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13618 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13619 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13620 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13621 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13622 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13623 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13624 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13625 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13626 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13627 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13628 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13629 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13630 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13631 */ + IC_EVEX_L2_KZ_B, /* 13632 */ + IC_EVEX_L2_KZ_B, /* 13633 */ + IC_EVEX_L2_XS_KZ_B, /* 13634 */ + IC_EVEX_L2_XS_KZ_B, /* 13635 */ + IC_EVEX_L2_XD_KZ_B, /* 13636 */ + IC_EVEX_L2_XD_KZ_B, /* 13637 */ + IC_EVEX_L2_XD_KZ_B, /* 13638 */ + IC_EVEX_L2_XD_KZ_B, /* 13639 */ + IC_EVEX_L2_W_KZ_B, /* 13640 */ + IC_EVEX_L2_W_KZ_B, /* 13641 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13642 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13643 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13644 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13645 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13646 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13647 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13648 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13649 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13650 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13651 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13652 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13653 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13654 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13655 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13656 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13657 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13658 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13659 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13660 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13661 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13662 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13663 */ + IC_EVEX_L2_KZ_B, /* 13664 */ + IC_EVEX_L2_KZ_B, /* 13665 */ + IC_EVEX_L2_XS_KZ_B, /* 13666 */ + IC_EVEX_L2_XS_KZ_B, /* 13667 */ + IC_EVEX_L2_XD_KZ_B, /* 13668 */ + IC_EVEX_L2_XD_KZ_B, /* 13669 */ + IC_EVEX_L2_XD_KZ_B, /* 13670 */ + IC_EVEX_L2_XD_KZ_B, /* 13671 */ + IC_EVEX_L2_W_KZ_B, /* 13672 */ + IC_EVEX_L2_W_KZ_B, /* 13673 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13674 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13675 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13676 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13677 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13678 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13679 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13680 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13681 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13682 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13683 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13684 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13685 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13686 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13687 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13688 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13689 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13690 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13691 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13692 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13693 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13694 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13695 */ + IC_EVEX_L2_KZ_B, /* 13696 */ + IC_EVEX_L2_KZ_B, /* 13697 */ + IC_EVEX_L2_XS_KZ_B, /* 13698 */ + IC_EVEX_L2_XS_KZ_B, /* 13699 */ + IC_EVEX_L2_XD_KZ_B, /* 13700 */ + IC_EVEX_L2_XD_KZ_B, /* 13701 */ + IC_EVEX_L2_XD_KZ_B, /* 13702 */ + IC_EVEX_L2_XD_KZ_B, /* 13703 */ + IC_EVEX_L2_W_KZ_B, /* 13704 */ + IC_EVEX_L2_W_KZ_B, /* 13705 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13706 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13707 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13708 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13709 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13710 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13711 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13712 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13713 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13714 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13715 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13716 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13717 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13718 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13719 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13720 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13721 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13722 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13723 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13724 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13725 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13726 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13727 */ + IC_EVEX_L2_KZ_B, /* 13728 */ + IC_EVEX_L2_KZ_B, /* 13729 */ + IC_EVEX_L2_XS_KZ_B, /* 13730 */ + IC_EVEX_L2_XS_KZ_B, /* 13731 */ + IC_EVEX_L2_XD_KZ_B, /* 13732 */ + IC_EVEX_L2_XD_KZ_B, /* 13733 */ + IC_EVEX_L2_XD_KZ_B, /* 13734 */ + IC_EVEX_L2_XD_KZ_B, /* 13735 */ + IC_EVEX_L2_W_KZ_B, /* 13736 */ + IC_EVEX_L2_W_KZ_B, /* 13737 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13738 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13739 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13740 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13741 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13742 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13743 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13744 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13745 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13746 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13747 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13748 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13749 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13750 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13751 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13752 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13753 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13754 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13755 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13756 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13757 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13758 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13759 */ + IC_EVEX_L2_KZ_B, /* 13760 */ + IC_EVEX_L2_KZ_B, /* 13761 */ + IC_EVEX_L2_XS_KZ_B, /* 13762 */ + IC_EVEX_L2_XS_KZ_B, /* 13763 */ + IC_EVEX_L2_XD_KZ_B, /* 13764 */ + IC_EVEX_L2_XD_KZ_B, /* 13765 */ + IC_EVEX_L2_XD_KZ_B, /* 13766 */ + IC_EVEX_L2_XD_KZ_B, /* 13767 */ + IC_EVEX_L2_W_KZ_B, /* 13768 */ + IC_EVEX_L2_W_KZ_B, /* 13769 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13770 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13771 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13772 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13773 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13774 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13775 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13776 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13777 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13778 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13779 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13780 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13781 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13782 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13783 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13784 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13785 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13786 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13787 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13788 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13789 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13790 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13791 */ + IC_EVEX_L2_KZ_B, /* 13792 */ + IC_EVEX_L2_KZ_B, /* 13793 */ + IC_EVEX_L2_XS_KZ_B, /* 13794 */ + IC_EVEX_L2_XS_KZ_B, /* 13795 */ + IC_EVEX_L2_XD_KZ_B, /* 13796 */ + IC_EVEX_L2_XD_KZ_B, /* 13797 */ + IC_EVEX_L2_XD_KZ_B, /* 13798 */ + IC_EVEX_L2_XD_KZ_B, /* 13799 */ + IC_EVEX_L2_W_KZ_B, /* 13800 */ + IC_EVEX_L2_W_KZ_B, /* 13801 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13802 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13803 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13804 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13805 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13806 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13807 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13808 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13809 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13810 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13811 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13812 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13813 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13814 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13815 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13816 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13817 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13818 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13819 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13820 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13821 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13822 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13823 */ + IC, /* 13824 */ + IC_64BIT, /* 13825 */ + IC_XS, /* 13826 */ + IC_64BIT_XS, /* 13827 */ + IC_XD, /* 13828 */ + IC_64BIT_XD, /* 13829 */ + IC_XS, /* 13830 */ + IC_64BIT_XS, /* 13831 */ + IC, /* 13832 */ + IC_64BIT_REXW, /* 13833 */ + IC_XS, /* 13834 */ + IC_64BIT_REXW_XS, /* 13835 */ + IC_XD, /* 13836 */ + IC_64BIT_REXW_XD, /* 13837 */ + IC_XS, /* 13838 */ + IC_64BIT_REXW_XS, /* 13839 */ + IC_OPSIZE, /* 13840 */ + IC_64BIT_OPSIZE, /* 13841 */ + IC_XS_OPSIZE, /* 13842 */ + IC_64BIT_XS_OPSIZE, /* 13843 */ + IC_XD_OPSIZE, /* 13844 */ + IC_64BIT_XD_OPSIZE, /* 13845 */ + IC_XS_OPSIZE, /* 13846 */ + IC_64BIT_XD_OPSIZE, /* 13847 */ + IC_OPSIZE, /* 13848 */ + IC_64BIT_REXW_OPSIZE, /* 13849 */ + IC_XS_OPSIZE, /* 13850 */ + IC_64BIT_REXW_XS, /* 13851 */ + IC_XD_OPSIZE, /* 13852 */ + IC_64BIT_REXW_XD, /* 13853 */ + IC_XS_OPSIZE, /* 13854 */ + IC_64BIT_REXW_XS, /* 13855 */ + IC_ADSIZE, /* 13856 */ + IC_64BIT_ADSIZE, /* 13857 */ + IC_XS_ADSIZE, /* 13858 */ + IC_64BIT_XS_ADSIZE, /* 13859 */ + IC_XD_ADSIZE, /* 13860 */ + IC_64BIT_XD_ADSIZE, /* 13861 */ + IC_XS_ADSIZE, /* 13862 */ + IC_64BIT_XD_ADSIZE, /* 13863 */ + IC_ADSIZE, /* 13864 */ + IC_64BIT_REXW_ADSIZE, /* 13865 */ + IC_XS_ADSIZE, /* 13866 */ + IC_64BIT_REXW_XS, /* 13867 */ + IC_XD_ADSIZE, /* 13868 */ + IC_64BIT_REXW_XD, /* 13869 */ + IC_XS_ADSIZE, /* 13870 */ + IC_64BIT_REXW_XS, /* 13871 */ + IC_OPSIZE_ADSIZE, /* 13872 */ + IC_64BIT_OPSIZE_ADSIZE, /* 13873 */ + IC_XS_OPSIZE, /* 13874 */ + IC_64BIT_XS_OPSIZE, /* 13875 */ + IC_XD_OPSIZE, /* 13876 */ + IC_64BIT_XD_OPSIZE, /* 13877 */ + IC_XS_OPSIZE, /* 13878 */ + IC_64BIT_XD_OPSIZE, /* 13879 */ + IC_OPSIZE_ADSIZE, /* 13880 */ + IC_64BIT_REXW_OPSIZE, /* 13881 */ + IC_XS_OPSIZE, /* 13882 */ + IC_64BIT_REXW_XS, /* 13883 */ + IC_XD_OPSIZE, /* 13884 */ + IC_64BIT_REXW_XD, /* 13885 */ + IC_XS_OPSIZE, /* 13886 */ + IC_64BIT_REXW_XS, /* 13887 */ + IC_VEX, /* 13888 */ + IC_VEX, /* 13889 */ + IC_VEX_XS, /* 13890 */ + IC_VEX_XS, /* 13891 */ + IC_VEX_XD, /* 13892 */ + IC_VEX_XD, /* 13893 */ + IC_VEX_XD, /* 13894 */ + IC_VEX_XD, /* 13895 */ + IC_VEX_W, /* 13896 */ + IC_VEX_W, /* 13897 */ + IC_VEX_W_XS, /* 13898 */ + IC_VEX_W_XS, /* 13899 */ + IC_VEX_W_XD, /* 13900 */ + IC_VEX_W_XD, /* 13901 */ + IC_VEX_W_XD, /* 13902 */ + IC_VEX_W_XD, /* 13903 */ + IC_VEX_OPSIZE, /* 13904 */ + IC_VEX_OPSIZE, /* 13905 */ + IC_VEX_OPSIZE, /* 13906 */ + IC_VEX_OPSIZE, /* 13907 */ + IC_VEX_OPSIZE, /* 13908 */ + IC_VEX_OPSIZE, /* 13909 */ + IC_VEX_OPSIZE, /* 13910 */ + IC_VEX_OPSIZE, /* 13911 */ + IC_VEX_W_OPSIZE, /* 13912 */ + IC_VEX_W_OPSIZE, /* 13913 */ + IC_VEX_W_OPSIZE, /* 13914 */ + IC_VEX_W_OPSIZE, /* 13915 */ + IC_VEX_W_OPSIZE, /* 13916 */ + IC_VEX_W_OPSIZE, /* 13917 */ + IC_VEX_W_OPSIZE, /* 13918 */ + IC_VEX_W_OPSIZE, /* 13919 */ + IC_VEX, /* 13920 */ + IC_VEX, /* 13921 */ + IC_VEX_XS, /* 13922 */ + IC_VEX_XS, /* 13923 */ + IC_VEX_XD, /* 13924 */ + IC_VEX_XD, /* 13925 */ + IC_VEX_XD, /* 13926 */ + IC_VEX_XD, /* 13927 */ + IC_VEX_W, /* 13928 */ + IC_VEX_W, /* 13929 */ + IC_VEX_W_XS, /* 13930 */ + IC_VEX_W_XS, /* 13931 */ + IC_VEX_W_XD, /* 13932 */ + IC_VEX_W_XD, /* 13933 */ + IC_VEX_W_XD, /* 13934 */ + IC_VEX_W_XD, /* 13935 */ + IC_VEX_OPSIZE, /* 13936 */ + IC_VEX_OPSIZE, /* 13937 */ + IC_VEX_OPSIZE, /* 13938 */ + IC_VEX_OPSIZE, /* 13939 */ + IC_VEX_OPSIZE, /* 13940 */ + IC_VEX_OPSIZE, /* 13941 */ + IC_VEX_OPSIZE, /* 13942 */ + IC_VEX_OPSIZE, /* 13943 */ + IC_VEX_W_OPSIZE, /* 13944 */ + IC_VEX_W_OPSIZE, /* 13945 */ + IC_VEX_W_OPSIZE, /* 13946 */ + IC_VEX_W_OPSIZE, /* 13947 */ + IC_VEX_W_OPSIZE, /* 13948 */ + IC_VEX_W_OPSIZE, /* 13949 */ + IC_VEX_W_OPSIZE, /* 13950 */ + IC_VEX_W_OPSIZE, /* 13951 */ + IC_VEX_L, /* 13952 */ + IC_VEX_L, /* 13953 */ + IC_VEX_L_XS, /* 13954 */ + IC_VEX_L_XS, /* 13955 */ + IC_VEX_L_XD, /* 13956 */ + IC_VEX_L_XD, /* 13957 */ + IC_VEX_L_XD, /* 13958 */ + IC_VEX_L_XD, /* 13959 */ + IC_VEX_L_W, /* 13960 */ + IC_VEX_L_W, /* 13961 */ + IC_VEX_L_W_XS, /* 13962 */ + IC_VEX_L_W_XS, /* 13963 */ + IC_VEX_L_W_XD, /* 13964 */ + IC_VEX_L_W_XD, /* 13965 */ + IC_VEX_L_W_XD, /* 13966 */ + IC_VEX_L_W_XD, /* 13967 */ + IC_VEX_L_OPSIZE, /* 13968 */ + IC_VEX_L_OPSIZE, /* 13969 */ + IC_VEX_L_OPSIZE, /* 13970 */ + IC_VEX_L_OPSIZE, /* 13971 */ + IC_VEX_L_OPSIZE, /* 13972 */ + IC_VEX_L_OPSIZE, /* 13973 */ + IC_VEX_L_OPSIZE, /* 13974 */ + IC_VEX_L_OPSIZE, /* 13975 */ + IC_VEX_L_W_OPSIZE, /* 13976 */ + IC_VEX_L_W_OPSIZE, /* 13977 */ + IC_VEX_L_W_OPSIZE, /* 13978 */ + IC_VEX_L_W_OPSIZE, /* 13979 */ + IC_VEX_L_W_OPSIZE, /* 13980 */ + IC_VEX_L_W_OPSIZE, /* 13981 */ + IC_VEX_L_W_OPSIZE, /* 13982 */ + IC_VEX_L_W_OPSIZE, /* 13983 */ + IC_VEX_L, /* 13984 */ + IC_VEX_L, /* 13985 */ + IC_VEX_L_XS, /* 13986 */ + IC_VEX_L_XS, /* 13987 */ + IC_VEX_L_XD, /* 13988 */ + IC_VEX_L_XD, /* 13989 */ + IC_VEX_L_XD, /* 13990 */ + IC_VEX_L_XD, /* 13991 */ + IC_VEX_L_W, /* 13992 */ + IC_VEX_L_W, /* 13993 */ + IC_VEX_L_W_XS, /* 13994 */ + IC_VEX_L_W_XS, /* 13995 */ + IC_VEX_L_W_XD, /* 13996 */ + IC_VEX_L_W_XD, /* 13997 */ + IC_VEX_L_W_XD, /* 13998 */ + IC_VEX_L_W_XD, /* 13999 */ + IC_VEX_L_OPSIZE, /* 14000 */ + IC_VEX_L_OPSIZE, /* 14001 */ + IC_VEX_L_OPSIZE, /* 14002 */ + IC_VEX_L_OPSIZE, /* 14003 */ + IC_VEX_L_OPSIZE, /* 14004 */ + IC_VEX_L_OPSIZE, /* 14005 */ + IC_VEX_L_OPSIZE, /* 14006 */ + IC_VEX_L_OPSIZE, /* 14007 */ + IC_VEX_L_W_OPSIZE, /* 14008 */ + IC_VEX_L_W_OPSIZE, /* 14009 */ + IC_VEX_L_W_OPSIZE, /* 14010 */ + IC_VEX_L_W_OPSIZE, /* 14011 */ + IC_VEX_L_W_OPSIZE, /* 14012 */ + IC_VEX_L_W_OPSIZE, /* 14013 */ + IC_VEX_L_W_OPSIZE, /* 14014 */ + IC_VEX_L_W_OPSIZE, /* 14015 */ + IC_VEX_L, /* 14016 */ + IC_VEX_L, /* 14017 */ + IC_VEX_L_XS, /* 14018 */ + IC_VEX_L_XS, /* 14019 */ + IC_VEX_L_XD, /* 14020 */ + IC_VEX_L_XD, /* 14021 */ + IC_VEX_L_XD, /* 14022 */ + IC_VEX_L_XD, /* 14023 */ + IC_VEX_L_W, /* 14024 */ + IC_VEX_L_W, /* 14025 */ + IC_VEX_L_W_XS, /* 14026 */ + IC_VEX_L_W_XS, /* 14027 */ + IC_VEX_L_W_XD, /* 14028 */ + IC_VEX_L_W_XD, /* 14029 */ + IC_VEX_L_W_XD, /* 14030 */ + IC_VEX_L_W_XD, /* 14031 */ + IC_VEX_L_OPSIZE, /* 14032 */ + IC_VEX_L_OPSIZE, /* 14033 */ + IC_VEX_L_OPSIZE, /* 14034 */ + IC_VEX_L_OPSIZE, /* 14035 */ + IC_VEX_L_OPSIZE, /* 14036 */ + IC_VEX_L_OPSIZE, /* 14037 */ + IC_VEX_L_OPSIZE, /* 14038 */ + IC_VEX_L_OPSIZE, /* 14039 */ + IC_VEX_L_W_OPSIZE, /* 14040 */ + IC_VEX_L_W_OPSIZE, /* 14041 */ + IC_VEX_L_W_OPSIZE, /* 14042 */ + IC_VEX_L_W_OPSIZE, /* 14043 */ + IC_VEX_L_W_OPSIZE, /* 14044 */ + IC_VEX_L_W_OPSIZE, /* 14045 */ + IC_VEX_L_W_OPSIZE, /* 14046 */ + IC_VEX_L_W_OPSIZE, /* 14047 */ + IC_VEX_L, /* 14048 */ + IC_VEX_L, /* 14049 */ + IC_VEX_L_XS, /* 14050 */ + IC_VEX_L_XS, /* 14051 */ + IC_VEX_L_XD, /* 14052 */ + IC_VEX_L_XD, /* 14053 */ + IC_VEX_L_XD, /* 14054 */ + IC_VEX_L_XD, /* 14055 */ + IC_VEX_L_W, /* 14056 */ + IC_VEX_L_W, /* 14057 */ + IC_VEX_L_W_XS, /* 14058 */ + IC_VEX_L_W_XS, /* 14059 */ + IC_VEX_L_W_XD, /* 14060 */ + IC_VEX_L_W_XD, /* 14061 */ + IC_VEX_L_W_XD, /* 14062 */ + IC_VEX_L_W_XD, /* 14063 */ + IC_VEX_L_OPSIZE, /* 14064 */ + IC_VEX_L_OPSIZE, /* 14065 */ + IC_VEX_L_OPSIZE, /* 14066 */ + IC_VEX_L_OPSIZE, /* 14067 */ + IC_VEX_L_OPSIZE, /* 14068 */ + IC_VEX_L_OPSIZE, /* 14069 */ + IC_VEX_L_OPSIZE, /* 14070 */ + IC_VEX_L_OPSIZE, /* 14071 */ + IC_VEX_L_W_OPSIZE, /* 14072 */ + IC_VEX_L_W_OPSIZE, /* 14073 */ + IC_VEX_L_W_OPSIZE, /* 14074 */ + IC_VEX_L_W_OPSIZE, /* 14075 */ + IC_VEX_L_W_OPSIZE, /* 14076 */ + IC_VEX_L_W_OPSIZE, /* 14077 */ + IC_VEX_L_W_OPSIZE, /* 14078 */ + IC_VEX_L_W_OPSIZE, /* 14079 */ + IC_EVEX_L2_KZ_B, /* 14080 */ + IC_EVEX_L2_KZ_B, /* 14081 */ + IC_EVEX_L2_XS_KZ_B, /* 14082 */ + IC_EVEX_L2_XS_KZ_B, /* 14083 */ + IC_EVEX_L2_XD_KZ_B, /* 14084 */ + IC_EVEX_L2_XD_KZ_B, /* 14085 */ + IC_EVEX_L2_XD_KZ_B, /* 14086 */ + IC_EVEX_L2_XD_KZ_B, /* 14087 */ + IC_EVEX_L2_W_KZ_B, /* 14088 */ + IC_EVEX_L2_W_KZ_B, /* 14089 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14090 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14091 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14092 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14093 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14094 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14095 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14096 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14097 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14098 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14099 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14100 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14101 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14102 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14103 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14104 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14105 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14106 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14107 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14108 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14109 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14110 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14111 */ + IC_EVEX_L2_KZ_B, /* 14112 */ + IC_EVEX_L2_KZ_B, /* 14113 */ + IC_EVEX_L2_XS_KZ_B, /* 14114 */ + IC_EVEX_L2_XS_KZ_B, /* 14115 */ + IC_EVEX_L2_XD_KZ_B, /* 14116 */ + IC_EVEX_L2_XD_KZ_B, /* 14117 */ + IC_EVEX_L2_XD_KZ_B, /* 14118 */ + IC_EVEX_L2_XD_KZ_B, /* 14119 */ + IC_EVEX_L2_W_KZ_B, /* 14120 */ + IC_EVEX_L2_W_KZ_B, /* 14121 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14122 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14123 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14124 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14125 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14126 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14127 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14128 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14129 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14130 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14131 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14132 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14133 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14134 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14135 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14136 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14137 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14138 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14139 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14140 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14141 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14142 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14143 */ + IC_EVEX_L2_KZ_B, /* 14144 */ + IC_EVEX_L2_KZ_B, /* 14145 */ + IC_EVEX_L2_XS_KZ_B, /* 14146 */ + IC_EVEX_L2_XS_KZ_B, /* 14147 */ + IC_EVEX_L2_XD_KZ_B, /* 14148 */ + IC_EVEX_L2_XD_KZ_B, /* 14149 */ + IC_EVEX_L2_XD_KZ_B, /* 14150 */ + IC_EVEX_L2_XD_KZ_B, /* 14151 */ + IC_EVEX_L2_W_KZ_B, /* 14152 */ + IC_EVEX_L2_W_KZ_B, /* 14153 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14154 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14155 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14156 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14157 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14158 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14159 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14160 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14161 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14162 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14163 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14164 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14165 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14166 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14167 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14168 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14169 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14170 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14171 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14172 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14173 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14174 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14175 */ + IC_EVEX_L2_KZ_B, /* 14176 */ + IC_EVEX_L2_KZ_B, /* 14177 */ + IC_EVEX_L2_XS_KZ_B, /* 14178 */ + IC_EVEX_L2_XS_KZ_B, /* 14179 */ + IC_EVEX_L2_XD_KZ_B, /* 14180 */ + IC_EVEX_L2_XD_KZ_B, /* 14181 */ + IC_EVEX_L2_XD_KZ_B, /* 14182 */ + IC_EVEX_L2_XD_KZ_B, /* 14183 */ + IC_EVEX_L2_W_KZ_B, /* 14184 */ + IC_EVEX_L2_W_KZ_B, /* 14185 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14186 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14187 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14188 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14189 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14190 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14191 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14192 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14193 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14194 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14195 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14196 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14197 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14198 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14199 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14200 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14201 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14202 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14203 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14204 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14205 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14206 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14207 */ + IC_EVEX_L2_KZ_B, /* 14208 */ + IC_EVEX_L2_KZ_B, /* 14209 */ + IC_EVEX_L2_XS_KZ_B, /* 14210 */ + IC_EVEX_L2_XS_KZ_B, /* 14211 */ + IC_EVEX_L2_XD_KZ_B, /* 14212 */ + IC_EVEX_L2_XD_KZ_B, /* 14213 */ + IC_EVEX_L2_XD_KZ_B, /* 14214 */ + IC_EVEX_L2_XD_KZ_B, /* 14215 */ + IC_EVEX_L2_W_KZ_B, /* 14216 */ + IC_EVEX_L2_W_KZ_B, /* 14217 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14218 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14219 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14220 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14221 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14222 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14223 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14224 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14225 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14226 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14227 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14228 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14229 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14230 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14231 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14232 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14233 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14234 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14235 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14236 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14237 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14238 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14239 */ + IC_EVEX_L2_KZ_B, /* 14240 */ + IC_EVEX_L2_KZ_B, /* 14241 */ + IC_EVEX_L2_XS_KZ_B, /* 14242 */ + IC_EVEX_L2_XS_KZ_B, /* 14243 */ + IC_EVEX_L2_XD_KZ_B, /* 14244 */ + IC_EVEX_L2_XD_KZ_B, /* 14245 */ + IC_EVEX_L2_XD_KZ_B, /* 14246 */ + IC_EVEX_L2_XD_KZ_B, /* 14247 */ + IC_EVEX_L2_W_KZ_B, /* 14248 */ + IC_EVEX_L2_W_KZ_B, /* 14249 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14250 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14251 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14252 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14253 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14254 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14255 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14256 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14257 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14258 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14259 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14260 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14261 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14262 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14263 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14264 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14265 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14266 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14267 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14268 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14269 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14270 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14271 */ + IC_EVEX_L2_KZ_B, /* 14272 */ + IC_EVEX_L2_KZ_B, /* 14273 */ + IC_EVEX_L2_XS_KZ_B, /* 14274 */ + IC_EVEX_L2_XS_KZ_B, /* 14275 */ + IC_EVEX_L2_XD_KZ_B, /* 14276 */ + IC_EVEX_L2_XD_KZ_B, /* 14277 */ + IC_EVEX_L2_XD_KZ_B, /* 14278 */ + IC_EVEX_L2_XD_KZ_B, /* 14279 */ + IC_EVEX_L2_W_KZ_B, /* 14280 */ + IC_EVEX_L2_W_KZ_B, /* 14281 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14282 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14283 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14284 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14285 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14286 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14287 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14288 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14289 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14290 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14291 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14292 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14293 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14294 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14295 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14296 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14297 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14298 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14299 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14300 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14301 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14302 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14303 */ + IC_EVEX_L2_KZ_B, /* 14304 */ + IC_EVEX_L2_KZ_B, /* 14305 */ + IC_EVEX_L2_XS_KZ_B, /* 14306 */ + IC_EVEX_L2_XS_KZ_B, /* 14307 */ + IC_EVEX_L2_XD_KZ_B, /* 14308 */ + IC_EVEX_L2_XD_KZ_B, /* 14309 */ + IC_EVEX_L2_XD_KZ_B, /* 14310 */ + IC_EVEX_L2_XD_KZ_B, /* 14311 */ + IC_EVEX_L2_W_KZ_B, /* 14312 */ + IC_EVEX_L2_W_KZ_B, /* 14313 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14314 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14315 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14316 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14317 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14318 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14319 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14320 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14321 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14322 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14323 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14324 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14325 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14326 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14327 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14328 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14329 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14330 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14331 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14332 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14333 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14334 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14335 */ + IC, /* 14336 */ + IC_64BIT, /* 14337 */ + IC_XS, /* 14338 */ + IC_64BIT_XS, /* 14339 */ + IC_XD, /* 14340 */ + IC_64BIT_XD, /* 14341 */ + IC_XS, /* 14342 */ + IC_64BIT_XS, /* 14343 */ + IC, /* 14344 */ + IC_64BIT_REXW, /* 14345 */ + IC_XS, /* 14346 */ + IC_64BIT_REXW_XS, /* 14347 */ + IC_XD, /* 14348 */ + IC_64BIT_REXW_XD, /* 14349 */ + IC_XS, /* 14350 */ + IC_64BIT_REXW_XS, /* 14351 */ + IC_OPSIZE, /* 14352 */ + IC_64BIT_OPSIZE, /* 14353 */ + IC_XS_OPSIZE, /* 14354 */ + IC_64BIT_XS_OPSIZE, /* 14355 */ + IC_XD_OPSIZE, /* 14356 */ + IC_64BIT_XD_OPSIZE, /* 14357 */ + IC_XS_OPSIZE, /* 14358 */ + IC_64BIT_XD_OPSIZE, /* 14359 */ + IC_OPSIZE, /* 14360 */ + IC_64BIT_REXW_OPSIZE, /* 14361 */ + IC_XS_OPSIZE, /* 14362 */ + IC_64BIT_REXW_XS, /* 14363 */ + IC_XD_OPSIZE, /* 14364 */ + IC_64BIT_REXW_XD, /* 14365 */ + IC_XS_OPSIZE, /* 14366 */ + IC_64BIT_REXW_XS, /* 14367 */ + IC_ADSIZE, /* 14368 */ + IC_64BIT_ADSIZE, /* 14369 */ + IC_XS_ADSIZE, /* 14370 */ + IC_64BIT_XS_ADSIZE, /* 14371 */ + IC_XD_ADSIZE, /* 14372 */ + IC_64BIT_XD_ADSIZE, /* 14373 */ + IC_XS_ADSIZE, /* 14374 */ + IC_64BIT_XD_ADSIZE, /* 14375 */ + IC_ADSIZE, /* 14376 */ + IC_64BIT_REXW_ADSIZE, /* 14377 */ + IC_XS_ADSIZE, /* 14378 */ + IC_64BIT_REXW_XS, /* 14379 */ + IC_XD_ADSIZE, /* 14380 */ + IC_64BIT_REXW_XD, /* 14381 */ + IC_XS_ADSIZE, /* 14382 */ + IC_64BIT_REXW_XS, /* 14383 */ + IC_OPSIZE_ADSIZE, /* 14384 */ + IC_64BIT_OPSIZE_ADSIZE, /* 14385 */ + IC_XS_OPSIZE, /* 14386 */ + IC_64BIT_XS_OPSIZE, /* 14387 */ + IC_XD_OPSIZE, /* 14388 */ + IC_64BIT_XD_OPSIZE, /* 14389 */ + IC_XS_OPSIZE, /* 14390 */ + IC_64BIT_XD_OPSIZE, /* 14391 */ + IC_OPSIZE_ADSIZE, /* 14392 */ + IC_64BIT_REXW_OPSIZE, /* 14393 */ + IC_XS_OPSIZE, /* 14394 */ + IC_64BIT_REXW_XS, /* 14395 */ + IC_XD_OPSIZE, /* 14396 */ + IC_64BIT_REXW_XD, /* 14397 */ + IC_XS_OPSIZE, /* 14398 */ + IC_64BIT_REXW_XS, /* 14399 */ + IC_VEX, /* 14400 */ + IC_VEX, /* 14401 */ + IC_VEX_XS, /* 14402 */ + IC_VEX_XS, /* 14403 */ + IC_VEX_XD, /* 14404 */ + IC_VEX_XD, /* 14405 */ + IC_VEX_XD, /* 14406 */ + IC_VEX_XD, /* 14407 */ + IC_VEX_W, /* 14408 */ + IC_VEX_W, /* 14409 */ + IC_VEX_W_XS, /* 14410 */ + IC_VEX_W_XS, /* 14411 */ + IC_VEX_W_XD, /* 14412 */ + IC_VEX_W_XD, /* 14413 */ + IC_VEX_W_XD, /* 14414 */ + IC_VEX_W_XD, /* 14415 */ + IC_VEX_OPSIZE, /* 14416 */ + IC_VEX_OPSIZE, /* 14417 */ + IC_VEX_OPSIZE, /* 14418 */ + IC_VEX_OPSIZE, /* 14419 */ + IC_VEX_OPSIZE, /* 14420 */ + IC_VEX_OPSIZE, /* 14421 */ + IC_VEX_OPSIZE, /* 14422 */ + IC_VEX_OPSIZE, /* 14423 */ + IC_VEX_W_OPSIZE, /* 14424 */ + IC_VEX_W_OPSIZE, /* 14425 */ + IC_VEX_W_OPSIZE, /* 14426 */ + IC_VEX_W_OPSIZE, /* 14427 */ + IC_VEX_W_OPSIZE, /* 14428 */ + IC_VEX_W_OPSIZE, /* 14429 */ + IC_VEX_W_OPSIZE, /* 14430 */ + IC_VEX_W_OPSIZE, /* 14431 */ + IC_VEX, /* 14432 */ + IC_VEX, /* 14433 */ + IC_VEX_XS, /* 14434 */ + IC_VEX_XS, /* 14435 */ + IC_VEX_XD, /* 14436 */ + IC_VEX_XD, /* 14437 */ + IC_VEX_XD, /* 14438 */ + IC_VEX_XD, /* 14439 */ + IC_VEX_W, /* 14440 */ + IC_VEX_W, /* 14441 */ + IC_VEX_W_XS, /* 14442 */ + IC_VEX_W_XS, /* 14443 */ + IC_VEX_W_XD, /* 14444 */ + IC_VEX_W_XD, /* 14445 */ + IC_VEX_W_XD, /* 14446 */ + IC_VEX_W_XD, /* 14447 */ + IC_VEX_OPSIZE, /* 14448 */ + IC_VEX_OPSIZE, /* 14449 */ + IC_VEX_OPSIZE, /* 14450 */ + IC_VEX_OPSIZE, /* 14451 */ + IC_VEX_OPSIZE, /* 14452 */ + IC_VEX_OPSIZE, /* 14453 */ + IC_VEX_OPSIZE, /* 14454 */ + IC_VEX_OPSIZE, /* 14455 */ + IC_VEX_W_OPSIZE, /* 14456 */ + IC_VEX_W_OPSIZE, /* 14457 */ + IC_VEX_W_OPSIZE, /* 14458 */ + IC_VEX_W_OPSIZE, /* 14459 */ + IC_VEX_W_OPSIZE, /* 14460 */ + IC_VEX_W_OPSIZE, /* 14461 */ + IC_VEX_W_OPSIZE, /* 14462 */ + IC_VEX_W_OPSIZE, /* 14463 */ + IC_VEX_L, /* 14464 */ + IC_VEX_L, /* 14465 */ + IC_VEX_L_XS, /* 14466 */ + IC_VEX_L_XS, /* 14467 */ + IC_VEX_L_XD, /* 14468 */ + IC_VEX_L_XD, /* 14469 */ + IC_VEX_L_XD, /* 14470 */ + IC_VEX_L_XD, /* 14471 */ + IC_VEX_L_W, /* 14472 */ + IC_VEX_L_W, /* 14473 */ + IC_VEX_L_W_XS, /* 14474 */ + IC_VEX_L_W_XS, /* 14475 */ + IC_VEX_L_W_XD, /* 14476 */ + IC_VEX_L_W_XD, /* 14477 */ + IC_VEX_L_W_XD, /* 14478 */ + IC_VEX_L_W_XD, /* 14479 */ + IC_VEX_L_OPSIZE, /* 14480 */ + IC_VEX_L_OPSIZE, /* 14481 */ + IC_VEX_L_OPSIZE, /* 14482 */ + IC_VEX_L_OPSIZE, /* 14483 */ + IC_VEX_L_OPSIZE, /* 14484 */ + IC_VEX_L_OPSIZE, /* 14485 */ + IC_VEX_L_OPSIZE, /* 14486 */ + IC_VEX_L_OPSIZE, /* 14487 */ + IC_VEX_L_W_OPSIZE, /* 14488 */ + IC_VEX_L_W_OPSIZE, /* 14489 */ + IC_VEX_L_W_OPSIZE, /* 14490 */ + IC_VEX_L_W_OPSIZE, /* 14491 */ + IC_VEX_L_W_OPSIZE, /* 14492 */ + IC_VEX_L_W_OPSIZE, /* 14493 */ + IC_VEX_L_W_OPSIZE, /* 14494 */ + IC_VEX_L_W_OPSIZE, /* 14495 */ + IC_VEX_L, /* 14496 */ + IC_VEX_L, /* 14497 */ + IC_VEX_L_XS, /* 14498 */ + IC_VEX_L_XS, /* 14499 */ + IC_VEX_L_XD, /* 14500 */ + IC_VEX_L_XD, /* 14501 */ + IC_VEX_L_XD, /* 14502 */ + IC_VEX_L_XD, /* 14503 */ + IC_VEX_L_W, /* 14504 */ + IC_VEX_L_W, /* 14505 */ + IC_VEX_L_W_XS, /* 14506 */ + IC_VEX_L_W_XS, /* 14507 */ + IC_VEX_L_W_XD, /* 14508 */ + IC_VEX_L_W_XD, /* 14509 */ + IC_VEX_L_W_XD, /* 14510 */ + IC_VEX_L_W_XD, /* 14511 */ + IC_VEX_L_OPSIZE, /* 14512 */ + IC_VEX_L_OPSIZE, /* 14513 */ + IC_VEX_L_OPSIZE, /* 14514 */ + IC_VEX_L_OPSIZE, /* 14515 */ + IC_VEX_L_OPSIZE, /* 14516 */ + IC_VEX_L_OPSIZE, /* 14517 */ + IC_VEX_L_OPSIZE, /* 14518 */ + IC_VEX_L_OPSIZE, /* 14519 */ + IC_VEX_L_W_OPSIZE, /* 14520 */ + IC_VEX_L_W_OPSIZE, /* 14521 */ + IC_VEX_L_W_OPSIZE, /* 14522 */ + IC_VEX_L_W_OPSIZE, /* 14523 */ + IC_VEX_L_W_OPSIZE, /* 14524 */ + IC_VEX_L_W_OPSIZE, /* 14525 */ + IC_VEX_L_W_OPSIZE, /* 14526 */ + IC_VEX_L_W_OPSIZE, /* 14527 */ + IC_VEX_L, /* 14528 */ + IC_VEX_L, /* 14529 */ + IC_VEX_L_XS, /* 14530 */ + IC_VEX_L_XS, /* 14531 */ + IC_VEX_L_XD, /* 14532 */ + IC_VEX_L_XD, /* 14533 */ + IC_VEX_L_XD, /* 14534 */ + IC_VEX_L_XD, /* 14535 */ + IC_VEX_L_W, /* 14536 */ + IC_VEX_L_W, /* 14537 */ + IC_VEX_L_W_XS, /* 14538 */ + IC_VEX_L_W_XS, /* 14539 */ + IC_VEX_L_W_XD, /* 14540 */ + IC_VEX_L_W_XD, /* 14541 */ + IC_VEX_L_W_XD, /* 14542 */ + IC_VEX_L_W_XD, /* 14543 */ + IC_VEX_L_OPSIZE, /* 14544 */ + IC_VEX_L_OPSIZE, /* 14545 */ + IC_VEX_L_OPSIZE, /* 14546 */ + IC_VEX_L_OPSIZE, /* 14547 */ + IC_VEX_L_OPSIZE, /* 14548 */ + IC_VEX_L_OPSIZE, /* 14549 */ + IC_VEX_L_OPSIZE, /* 14550 */ + IC_VEX_L_OPSIZE, /* 14551 */ + IC_VEX_L_W_OPSIZE, /* 14552 */ + IC_VEX_L_W_OPSIZE, /* 14553 */ + IC_VEX_L_W_OPSIZE, /* 14554 */ + IC_VEX_L_W_OPSIZE, /* 14555 */ + IC_VEX_L_W_OPSIZE, /* 14556 */ + IC_VEX_L_W_OPSIZE, /* 14557 */ + IC_VEX_L_W_OPSIZE, /* 14558 */ + IC_VEX_L_W_OPSIZE, /* 14559 */ + IC_VEX_L, /* 14560 */ + IC_VEX_L, /* 14561 */ + IC_VEX_L_XS, /* 14562 */ + IC_VEX_L_XS, /* 14563 */ + IC_VEX_L_XD, /* 14564 */ + IC_VEX_L_XD, /* 14565 */ + IC_VEX_L_XD, /* 14566 */ + IC_VEX_L_XD, /* 14567 */ + IC_VEX_L_W, /* 14568 */ + IC_VEX_L_W, /* 14569 */ + IC_VEX_L_W_XS, /* 14570 */ + IC_VEX_L_W_XS, /* 14571 */ + IC_VEX_L_W_XD, /* 14572 */ + IC_VEX_L_W_XD, /* 14573 */ + IC_VEX_L_W_XD, /* 14574 */ + IC_VEX_L_W_XD, /* 14575 */ + IC_VEX_L_OPSIZE, /* 14576 */ + IC_VEX_L_OPSIZE, /* 14577 */ + IC_VEX_L_OPSIZE, /* 14578 */ + IC_VEX_L_OPSIZE, /* 14579 */ + IC_VEX_L_OPSIZE, /* 14580 */ + IC_VEX_L_OPSIZE, /* 14581 */ + IC_VEX_L_OPSIZE, /* 14582 */ + IC_VEX_L_OPSIZE, /* 14583 */ + IC_VEX_L_W_OPSIZE, /* 14584 */ + IC_VEX_L_W_OPSIZE, /* 14585 */ + IC_VEX_L_W_OPSIZE, /* 14586 */ + IC_VEX_L_W_OPSIZE, /* 14587 */ + IC_VEX_L_W_OPSIZE, /* 14588 */ + IC_VEX_L_W_OPSIZE, /* 14589 */ + IC_VEX_L_W_OPSIZE, /* 14590 */ + IC_VEX_L_W_OPSIZE, /* 14591 */ + IC_EVEX_KZ_B, /* 14592 */ + IC_EVEX_KZ_B, /* 14593 */ + IC_EVEX_XS_KZ_B, /* 14594 */ + IC_EVEX_XS_KZ_B, /* 14595 */ + IC_EVEX_XD_KZ_B, /* 14596 */ + IC_EVEX_XD_KZ_B, /* 14597 */ + IC_EVEX_XD_KZ_B, /* 14598 */ + IC_EVEX_XD_KZ_B, /* 14599 */ + IC_EVEX_W_KZ_B, /* 14600 */ + IC_EVEX_W_KZ_B, /* 14601 */ + IC_EVEX_W_XS_KZ_B, /* 14602 */ + IC_EVEX_W_XS_KZ_B, /* 14603 */ + IC_EVEX_W_XD_KZ_B, /* 14604 */ + IC_EVEX_W_XD_KZ_B, /* 14605 */ + IC_EVEX_W_XD_KZ_B, /* 14606 */ + IC_EVEX_W_XD_KZ_B, /* 14607 */ + IC_EVEX_OPSIZE_KZ_B, /* 14608 */ + IC_EVEX_OPSIZE_KZ_B, /* 14609 */ + IC_EVEX_OPSIZE_KZ_B, /* 14610 */ + IC_EVEX_OPSIZE_KZ_B, /* 14611 */ + IC_EVEX_OPSIZE_KZ_B, /* 14612 */ + IC_EVEX_OPSIZE_KZ_B, /* 14613 */ + IC_EVEX_OPSIZE_KZ_B, /* 14614 */ + IC_EVEX_OPSIZE_KZ_B, /* 14615 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14616 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14617 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14618 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14619 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14620 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14621 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14622 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14623 */ + IC_EVEX_KZ_B, /* 14624 */ + IC_EVEX_KZ_B, /* 14625 */ + IC_EVEX_XS_KZ_B, /* 14626 */ + IC_EVEX_XS_KZ_B, /* 14627 */ + IC_EVEX_XD_KZ_B, /* 14628 */ + IC_EVEX_XD_KZ_B, /* 14629 */ + IC_EVEX_XD_KZ_B, /* 14630 */ + IC_EVEX_XD_KZ_B, /* 14631 */ + IC_EVEX_W_KZ_B, /* 14632 */ + IC_EVEX_W_KZ_B, /* 14633 */ + IC_EVEX_W_XS_KZ_B, /* 14634 */ + IC_EVEX_W_XS_KZ_B, /* 14635 */ + IC_EVEX_W_XD_KZ_B, /* 14636 */ + IC_EVEX_W_XD_KZ_B, /* 14637 */ + IC_EVEX_W_XD_KZ_B, /* 14638 */ + IC_EVEX_W_XD_KZ_B, /* 14639 */ + IC_EVEX_OPSIZE_KZ_B, /* 14640 */ + IC_EVEX_OPSIZE_KZ_B, /* 14641 */ + IC_EVEX_OPSIZE_KZ_B, /* 14642 */ + IC_EVEX_OPSIZE_KZ_B, /* 14643 */ + IC_EVEX_OPSIZE_KZ_B, /* 14644 */ + IC_EVEX_OPSIZE_KZ_B, /* 14645 */ + IC_EVEX_OPSIZE_KZ_B, /* 14646 */ + IC_EVEX_OPSIZE_KZ_B, /* 14647 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14648 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14649 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14650 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14651 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14652 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14653 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14654 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14655 */ + IC_EVEX_KZ_B, /* 14656 */ + IC_EVEX_KZ_B, /* 14657 */ + IC_EVEX_XS_KZ_B, /* 14658 */ + IC_EVEX_XS_KZ_B, /* 14659 */ + IC_EVEX_XD_KZ_B, /* 14660 */ + IC_EVEX_XD_KZ_B, /* 14661 */ + IC_EVEX_XD_KZ_B, /* 14662 */ + IC_EVEX_XD_KZ_B, /* 14663 */ + IC_EVEX_W_KZ_B, /* 14664 */ + IC_EVEX_W_KZ_B, /* 14665 */ + IC_EVEX_W_XS_KZ_B, /* 14666 */ + IC_EVEX_W_XS_KZ_B, /* 14667 */ + IC_EVEX_W_XD_KZ_B, /* 14668 */ + IC_EVEX_W_XD_KZ_B, /* 14669 */ + IC_EVEX_W_XD_KZ_B, /* 14670 */ + IC_EVEX_W_XD_KZ_B, /* 14671 */ + IC_EVEX_OPSIZE_KZ_B, /* 14672 */ + IC_EVEX_OPSIZE_KZ_B, /* 14673 */ + IC_EVEX_OPSIZE_KZ_B, /* 14674 */ + IC_EVEX_OPSIZE_KZ_B, /* 14675 */ + IC_EVEX_OPSIZE_KZ_B, /* 14676 */ + IC_EVEX_OPSIZE_KZ_B, /* 14677 */ + IC_EVEX_OPSIZE_KZ_B, /* 14678 */ + IC_EVEX_OPSIZE_KZ_B, /* 14679 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14680 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14681 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14682 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14683 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14684 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14685 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14686 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14687 */ + IC_EVEX_KZ_B, /* 14688 */ + IC_EVEX_KZ_B, /* 14689 */ + IC_EVEX_XS_KZ_B, /* 14690 */ + IC_EVEX_XS_KZ_B, /* 14691 */ + IC_EVEX_XD_KZ_B, /* 14692 */ + IC_EVEX_XD_KZ_B, /* 14693 */ + IC_EVEX_XD_KZ_B, /* 14694 */ + IC_EVEX_XD_KZ_B, /* 14695 */ + IC_EVEX_W_KZ_B, /* 14696 */ + IC_EVEX_W_KZ_B, /* 14697 */ + IC_EVEX_W_XS_KZ_B, /* 14698 */ + IC_EVEX_W_XS_KZ_B, /* 14699 */ + IC_EVEX_W_XD_KZ_B, /* 14700 */ + IC_EVEX_W_XD_KZ_B, /* 14701 */ + IC_EVEX_W_XD_KZ_B, /* 14702 */ + IC_EVEX_W_XD_KZ_B, /* 14703 */ + IC_EVEX_OPSIZE_KZ_B, /* 14704 */ + IC_EVEX_OPSIZE_KZ_B, /* 14705 */ + IC_EVEX_OPSIZE_KZ_B, /* 14706 */ + IC_EVEX_OPSIZE_KZ_B, /* 14707 */ + IC_EVEX_OPSIZE_KZ_B, /* 14708 */ + IC_EVEX_OPSIZE_KZ_B, /* 14709 */ + IC_EVEX_OPSIZE_KZ_B, /* 14710 */ + IC_EVEX_OPSIZE_KZ_B, /* 14711 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14712 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14713 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14714 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14715 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14716 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14717 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14718 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14719 */ + IC_EVEX_KZ_B, /* 14720 */ + IC_EVEX_KZ_B, /* 14721 */ + IC_EVEX_XS_KZ_B, /* 14722 */ + IC_EVEX_XS_KZ_B, /* 14723 */ + IC_EVEX_XD_KZ_B, /* 14724 */ + IC_EVEX_XD_KZ_B, /* 14725 */ + IC_EVEX_XD_KZ_B, /* 14726 */ + IC_EVEX_XD_KZ_B, /* 14727 */ + IC_EVEX_W_KZ_B, /* 14728 */ + IC_EVEX_W_KZ_B, /* 14729 */ + IC_EVEX_W_XS_KZ_B, /* 14730 */ + IC_EVEX_W_XS_KZ_B, /* 14731 */ + IC_EVEX_W_XD_KZ_B, /* 14732 */ + IC_EVEX_W_XD_KZ_B, /* 14733 */ + IC_EVEX_W_XD_KZ_B, /* 14734 */ + IC_EVEX_W_XD_KZ_B, /* 14735 */ + IC_EVEX_OPSIZE_KZ_B, /* 14736 */ + IC_EVEX_OPSIZE_KZ_B, /* 14737 */ + IC_EVEX_OPSIZE_KZ_B, /* 14738 */ + IC_EVEX_OPSIZE_KZ_B, /* 14739 */ + IC_EVEX_OPSIZE_KZ_B, /* 14740 */ + IC_EVEX_OPSIZE_KZ_B, /* 14741 */ + IC_EVEX_OPSIZE_KZ_B, /* 14742 */ + IC_EVEX_OPSIZE_KZ_B, /* 14743 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14744 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14745 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14746 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14747 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14748 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14749 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14750 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14751 */ + IC_EVEX_KZ_B, /* 14752 */ + IC_EVEX_KZ_B, /* 14753 */ + IC_EVEX_XS_KZ_B, /* 14754 */ + IC_EVEX_XS_KZ_B, /* 14755 */ + IC_EVEX_XD_KZ_B, /* 14756 */ + IC_EVEX_XD_KZ_B, /* 14757 */ + IC_EVEX_XD_KZ_B, /* 14758 */ + IC_EVEX_XD_KZ_B, /* 14759 */ + IC_EVEX_W_KZ_B, /* 14760 */ + IC_EVEX_W_KZ_B, /* 14761 */ + IC_EVEX_W_XS_KZ_B, /* 14762 */ + IC_EVEX_W_XS_KZ_B, /* 14763 */ + IC_EVEX_W_XD_KZ_B, /* 14764 */ + IC_EVEX_W_XD_KZ_B, /* 14765 */ + IC_EVEX_W_XD_KZ_B, /* 14766 */ + IC_EVEX_W_XD_KZ_B, /* 14767 */ + IC_EVEX_OPSIZE_KZ_B, /* 14768 */ + IC_EVEX_OPSIZE_KZ_B, /* 14769 */ + IC_EVEX_OPSIZE_KZ_B, /* 14770 */ + IC_EVEX_OPSIZE_KZ_B, /* 14771 */ + IC_EVEX_OPSIZE_KZ_B, /* 14772 */ + IC_EVEX_OPSIZE_KZ_B, /* 14773 */ + IC_EVEX_OPSIZE_KZ_B, /* 14774 */ + IC_EVEX_OPSIZE_KZ_B, /* 14775 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14776 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14777 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14778 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14779 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14780 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14781 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14782 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14783 */ + IC_EVEX_KZ_B, /* 14784 */ + IC_EVEX_KZ_B, /* 14785 */ + IC_EVEX_XS_KZ_B, /* 14786 */ + IC_EVEX_XS_KZ_B, /* 14787 */ + IC_EVEX_XD_KZ_B, /* 14788 */ + IC_EVEX_XD_KZ_B, /* 14789 */ + IC_EVEX_XD_KZ_B, /* 14790 */ + IC_EVEX_XD_KZ_B, /* 14791 */ + IC_EVEX_W_KZ_B, /* 14792 */ + IC_EVEX_W_KZ_B, /* 14793 */ + IC_EVEX_W_XS_KZ_B, /* 14794 */ + IC_EVEX_W_XS_KZ_B, /* 14795 */ + IC_EVEX_W_XD_KZ_B, /* 14796 */ + IC_EVEX_W_XD_KZ_B, /* 14797 */ + IC_EVEX_W_XD_KZ_B, /* 14798 */ + IC_EVEX_W_XD_KZ_B, /* 14799 */ + IC_EVEX_OPSIZE_KZ_B, /* 14800 */ + IC_EVEX_OPSIZE_KZ_B, /* 14801 */ + IC_EVEX_OPSIZE_KZ_B, /* 14802 */ + IC_EVEX_OPSIZE_KZ_B, /* 14803 */ + IC_EVEX_OPSIZE_KZ_B, /* 14804 */ + IC_EVEX_OPSIZE_KZ_B, /* 14805 */ + IC_EVEX_OPSIZE_KZ_B, /* 14806 */ + IC_EVEX_OPSIZE_KZ_B, /* 14807 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14808 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14809 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14810 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14811 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14812 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14813 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14814 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14815 */ + IC_EVEX_KZ_B, /* 14816 */ + IC_EVEX_KZ_B, /* 14817 */ + IC_EVEX_XS_KZ_B, /* 14818 */ + IC_EVEX_XS_KZ_B, /* 14819 */ + IC_EVEX_XD_KZ_B, /* 14820 */ + IC_EVEX_XD_KZ_B, /* 14821 */ + IC_EVEX_XD_KZ_B, /* 14822 */ + IC_EVEX_XD_KZ_B, /* 14823 */ + IC_EVEX_W_KZ_B, /* 14824 */ + IC_EVEX_W_KZ_B, /* 14825 */ + IC_EVEX_W_XS_KZ_B, /* 14826 */ + IC_EVEX_W_XS_KZ_B, /* 14827 */ + IC_EVEX_W_XD_KZ_B, /* 14828 */ + IC_EVEX_W_XD_KZ_B, /* 14829 */ + IC_EVEX_W_XD_KZ_B, /* 14830 */ + IC_EVEX_W_XD_KZ_B, /* 14831 */ + IC_EVEX_OPSIZE_KZ_B, /* 14832 */ + IC_EVEX_OPSIZE_KZ_B, /* 14833 */ + IC_EVEX_OPSIZE_KZ_B, /* 14834 */ + IC_EVEX_OPSIZE_KZ_B, /* 14835 */ + IC_EVEX_OPSIZE_KZ_B, /* 14836 */ + IC_EVEX_OPSIZE_KZ_B, /* 14837 */ + IC_EVEX_OPSIZE_KZ_B, /* 14838 */ + IC_EVEX_OPSIZE_KZ_B, /* 14839 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14840 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14841 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14842 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14843 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14844 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14845 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14846 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14847 */ + IC, /* 14848 */ + IC_64BIT, /* 14849 */ + IC_XS, /* 14850 */ + IC_64BIT_XS, /* 14851 */ + IC_XD, /* 14852 */ + IC_64BIT_XD, /* 14853 */ + IC_XS, /* 14854 */ + IC_64BIT_XS, /* 14855 */ + IC, /* 14856 */ + IC_64BIT_REXW, /* 14857 */ + IC_XS, /* 14858 */ + IC_64BIT_REXW_XS, /* 14859 */ + IC_XD, /* 14860 */ + IC_64BIT_REXW_XD, /* 14861 */ + IC_XS, /* 14862 */ + IC_64BIT_REXW_XS, /* 14863 */ + IC_OPSIZE, /* 14864 */ + IC_64BIT_OPSIZE, /* 14865 */ + IC_XS_OPSIZE, /* 14866 */ + IC_64BIT_XS_OPSIZE, /* 14867 */ + IC_XD_OPSIZE, /* 14868 */ + IC_64BIT_XD_OPSIZE, /* 14869 */ + IC_XS_OPSIZE, /* 14870 */ + IC_64BIT_XD_OPSIZE, /* 14871 */ + IC_OPSIZE, /* 14872 */ + IC_64BIT_REXW_OPSIZE, /* 14873 */ + IC_XS_OPSIZE, /* 14874 */ + IC_64BIT_REXW_XS, /* 14875 */ + IC_XD_OPSIZE, /* 14876 */ + IC_64BIT_REXW_XD, /* 14877 */ + IC_XS_OPSIZE, /* 14878 */ + IC_64BIT_REXW_XS, /* 14879 */ + IC_ADSIZE, /* 14880 */ + IC_64BIT_ADSIZE, /* 14881 */ + IC_XS_ADSIZE, /* 14882 */ + IC_64BIT_XS_ADSIZE, /* 14883 */ + IC_XD_ADSIZE, /* 14884 */ + IC_64BIT_XD_ADSIZE, /* 14885 */ + IC_XS_ADSIZE, /* 14886 */ + IC_64BIT_XD_ADSIZE, /* 14887 */ + IC_ADSIZE, /* 14888 */ + IC_64BIT_REXW_ADSIZE, /* 14889 */ + IC_XS_ADSIZE, /* 14890 */ + IC_64BIT_REXW_XS, /* 14891 */ + IC_XD_ADSIZE, /* 14892 */ + IC_64BIT_REXW_XD, /* 14893 */ + IC_XS_ADSIZE, /* 14894 */ + IC_64BIT_REXW_XS, /* 14895 */ + IC_OPSIZE_ADSIZE, /* 14896 */ + IC_64BIT_OPSIZE_ADSIZE, /* 14897 */ + IC_XS_OPSIZE, /* 14898 */ + IC_64BIT_XS_OPSIZE, /* 14899 */ + IC_XD_OPSIZE, /* 14900 */ + IC_64BIT_XD_OPSIZE, /* 14901 */ + IC_XS_OPSIZE, /* 14902 */ + IC_64BIT_XD_OPSIZE, /* 14903 */ + IC_OPSIZE_ADSIZE, /* 14904 */ + IC_64BIT_REXW_OPSIZE, /* 14905 */ + IC_XS_OPSIZE, /* 14906 */ + IC_64BIT_REXW_XS, /* 14907 */ + IC_XD_OPSIZE, /* 14908 */ + IC_64BIT_REXW_XD, /* 14909 */ + IC_XS_OPSIZE, /* 14910 */ + IC_64BIT_REXW_XS, /* 14911 */ + IC_VEX, /* 14912 */ + IC_VEX, /* 14913 */ + IC_VEX_XS, /* 14914 */ + IC_VEX_XS, /* 14915 */ + IC_VEX_XD, /* 14916 */ + IC_VEX_XD, /* 14917 */ + IC_VEX_XD, /* 14918 */ + IC_VEX_XD, /* 14919 */ + IC_VEX_W, /* 14920 */ + IC_VEX_W, /* 14921 */ + IC_VEX_W_XS, /* 14922 */ + IC_VEX_W_XS, /* 14923 */ + IC_VEX_W_XD, /* 14924 */ + IC_VEX_W_XD, /* 14925 */ + IC_VEX_W_XD, /* 14926 */ + IC_VEX_W_XD, /* 14927 */ + IC_VEX_OPSIZE, /* 14928 */ + IC_VEX_OPSIZE, /* 14929 */ + IC_VEX_OPSIZE, /* 14930 */ + IC_VEX_OPSIZE, /* 14931 */ + IC_VEX_OPSIZE, /* 14932 */ + IC_VEX_OPSIZE, /* 14933 */ + IC_VEX_OPSIZE, /* 14934 */ + IC_VEX_OPSIZE, /* 14935 */ + IC_VEX_W_OPSIZE, /* 14936 */ + IC_VEX_W_OPSIZE, /* 14937 */ + IC_VEX_W_OPSIZE, /* 14938 */ + IC_VEX_W_OPSIZE, /* 14939 */ + IC_VEX_W_OPSIZE, /* 14940 */ + IC_VEX_W_OPSIZE, /* 14941 */ + IC_VEX_W_OPSIZE, /* 14942 */ + IC_VEX_W_OPSIZE, /* 14943 */ + IC_VEX, /* 14944 */ + IC_VEX, /* 14945 */ + IC_VEX_XS, /* 14946 */ + IC_VEX_XS, /* 14947 */ + IC_VEX_XD, /* 14948 */ + IC_VEX_XD, /* 14949 */ + IC_VEX_XD, /* 14950 */ + IC_VEX_XD, /* 14951 */ + IC_VEX_W, /* 14952 */ + IC_VEX_W, /* 14953 */ + IC_VEX_W_XS, /* 14954 */ + IC_VEX_W_XS, /* 14955 */ + IC_VEX_W_XD, /* 14956 */ + IC_VEX_W_XD, /* 14957 */ + IC_VEX_W_XD, /* 14958 */ + IC_VEX_W_XD, /* 14959 */ + IC_VEX_OPSIZE, /* 14960 */ + IC_VEX_OPSIZE, /* 14961 */ + IC_VEX_OPSIZE, /* 14962 */ + IC_VEX_OPSIZE, /* 14963 */ + IC_VEX_OPSIZE, /* 14964 */ + IC_VEX_OPSIZE, /* 14965 */ + IC_VEX_OPSIZE, /* 14966 */ + IC_VEX_OPSIZE, /* 14967 */ + IC_VEX_W_OPSIZE, /* 14968 */ + IC_VEX_W_OPSIZE, /* 14969 */ + IC_VEX_W_OPSIZE, /* 14970 */ + IC_VEX_W_OPSIZE, /* 14971 */ + IC_VEX_W_OPSIZE, /* 14972 */ + IC_VEX_W_OPSIZE, /* 14973 */ + IC_VEX_W_OPSIZE, /* 14974 */ + IC_VEX_W_OPSIZE, /* 14975 */ + IC_VEX_L, /* 14976 */ + IC_VEX_L, /* 14977 */ + IC_VEX_L_XS, /* 14978 */ + IC_VEX_L_XS, /* 14979 */ + IC_VEX_L_XD, /* 14980 */ + IC_VEX_L_XD, /* 14981 */ + IC_VEX_L_XD, /* 14982 */ + IC_VEX_L_XD, /* 14983 */ + IC_VEX_L_W, /* 14984 */ + IC_VEX_L_W, /* 14985 */ + IC_VEX_L_W_XS, /* 14986 */ + IC_VEX_L_W_XS, /* 14987 */ + IC_VEX_L_W_XD, /* 14988 */ + IC_VEX_L_W_XD, /* 14989 */ + IC_VEX_L_W_XD, /* 14990 */ + IC_VEX_L_W_XD, /* 14991 */ + IC_VEX_L_OPSIZE, /* 14992 */ + IC_VEX_L_OPSIZE, /* 14993 */ + IC_VEX_L_OPSIZE, /* 14994 */ + IC_VEX_L_OPSIZE, /* 14995 */ + IC_VEX_L_OPSIZE, /* 14996 */ + IC_VEX_L_OPSIZE, /* 14997 */ + IC_VEX_L_OPSIZE, /* 14998 */ + IC_VEX_L_OPSIZE, /* 14999 */ + IC_VEX_L_W_OPSIZE, /* 15000 */ + IC_VEX_L_W_OPSIZE, /* 15001 */ + IC_VEX_L_W_OPSIZE, /* 15002 */ + IC_VEX_L_W_OPSIZE, /* 15003 */ + IC_VEX_L_W_OPSIZE, /* 15004 */ + IC_VEX_L_W_OPSIZE, /* 15005 */ + IC_VEX_L_W_OPSIZE, /* 15006 */ + IC_VEX_L_W_OPSIZE, /* 15007 */ + IC_VEX_L, /* 15008 */ + IC_VEX_L, /* 15009 */ + IC_VEX_L_XS, /* 15010 */ + IC_VEX_L_XS, /* 15011 */ + IC_VEX_L_XD, /* 15012 */ + IC_VEX_L_XD, /* 15013 */ + IC_VEX_L_XD, /* 15014 */ + IC_VEX_L_XD, /* 15015 */ + IC_VEX_L_W, /* 15016 */ + IC_VEX_L_W, /* 15017 */ + IC_VEX_L_W_XS, /* 15018 */ + IC_VEX_L_W_XS, /* 15019 */ + IC_VEX_L_W_XD, /* 15020 */ + IC_VEX_L_W_XD, /* 15021 */ + IC_VEX_L_W_XD, /* 15022 */ + IC_VEX_L_W_XD, /* 15023 */ + IC_VEX_L_OPSIZE, /* 15024 */ + IC_VEX_L_OPSIZE, /* 15025 */ + IC_VEX_L_OPSIZE, /* 15026 */ + IC_VEX_L_OPSIZE, /* 15027 */ + IC_VEX_L_OPSIZE, /* 15028 */ + IC_VEX_L_OPSIZE, /* 15029 */ + IC_VEX_L_OPSIZE, /* 15030 */ + IC_VEX_L_OPSIZE, /* 15031 */ + IC_VEX_L_W_OPSIZE, /* 15032 */ + IC_VEX_L_W_OPSIZE, /* 15033 */ + IC_VEX_L_W_OPSIZE, /* 15034 */ + IC_VEX_L_W_OPSIZE, /* 15035 */ + IC_VEX_L_W_OPSIZE, /* 15036 */ + IC_VEX_L_W_OPSIZE, /* 15037 */ + IC_VEX_L_W_OPSIZE, /* 15038 */ + IC_VEX_L_W_OPSIZE, /* 15039 */ + IC_VEX_L, /* 15040 */ + IC_VEX_L, /* 15041 */ + IC_VEX_L_XS, /* 15042 */ + IC_VEX_L_XS, /* 15043 */ + IC_VEX_L_XD, /* 15044 */ + IC_VEX_L_XD, /* 15045 */ + IC_VEX_L_XD, /* 15046 */ + IC_VEX_L_XD, /* 15047 */ + IC_VEX_L_W, /* 15048 */ + IC_VEX_L_W, /* 15049 */ + IC_VEX_L_W_XS, /* 15050 */ + IC_VEX_L_W_XS, /* 15051 */ + IC_VEX_L_W_XD, /* 15052 */ + IC_VEX_L_W_XD, /* 15053 */ + IC_VEX_L_W_XD, /* 15054 */ + IC_VEX_L_W_XD, /* 15055 */ + IC_VEX_L_OPSIZE, /* 15056 */ + IC_VEX_L_OPSIZE, /* 15057 */ + IC_VEX_L_OPSIZE, /* 15058 */ + IC_VEX_L_OPSIZE, /* 15059 */ + IC_VEX_L_OPSIZE, /* 15060 */ + IC_VEX_L_OPSIZE, /* 15061 */ + IC_VEX_L_OPSIZE, /* 15062 */ + IC_VEX_L_OPSIZE, /* 15063 */ + IC_VEX_L_W_OPSIZE, /* 15064 */ + IC_VEX_L_W_OPSIZE, /* 15065 */ + IC_VEX_L_W_OPSIZE, /* 15066 */ + IC_VEX_L_W_OPSIZE, /* 15067 */ + IC_VEX_L_W_OPSIZE, /* 15068 */ + IC_VEX_L_W_OPSIZE, /* 15069 */ + IC_VEX_L_W_OPSIZE, /* 15070 */ + IC_VEX_L_W_OPSIZE, /* 15071 */ + IC_VEX_L, /* 15072 */ + IC_VEX_L, /* 15073 */ + IC_VEX_L_XS, /* 15074 */ + IC_VEX_L_XS, /* 15075 */ + IC_VEX_L_XD, /* 15076 */ + IC_VEX_L_XD, /* 15077 */ + IC_VEX_L_XD, /* 15078 */ + IC_VEX_L_XD, /* 15079 */ + IC_VEX_L_W, /* 15080 */ + IC_VEX_L_W, /* 15081 */ + IC_VEX_L_W_XS, /* 15082 */ + IC_VEX_L_W_XS, /* 15083 */ + IC_VEX_L_W_XD, /* 15084 */ + IC_VEX_L_W_XD, /* 15085 */ + IC_VEX_L_W_XD, /* 15086 */ + IC_VEX_L_W_XD, /* 15087 */ + IC_VEX_L_OPSIZE, /* 15088 */ + IC_VEX_L_OPSIZE, /* 15089 */ + IC_VEX_L_OPSIZE, /* 15090 */ + IC_VEX_L_OPSIZE, /* 15091 */ + IC_VEX_L_OPSIZE, /* 15092 */ + IC_VEX_L_OPSIZE, /* 15093 */ + IC_VEX_L_OPSIZE, /* 15094 */ + IC_VEX_L_OPSIZE, /* 15095 */ + IC_VEX_L_W_OPSIZE, /* 15096 */ + IC_VEX_L_W_OPSIZE, /* 15097 */ + IC_VEX_L_W_OPSIZE, /* 15098 */ + IC_VEX_L_W_OPSIZE, /* 15099 */ + IC_VEX_L_W_OPSIZE, /* 15100 */ + IC_VEX_L_W_OPSIZE, /* 15101 */ + IC_VEX_L_W_OPSIZE, /* 15102 */ + IC_VEX_L_W_OPSIZE, /* 15103 */ + IC_EVEX_L_KZ_B, /* 15104 */ + IC_EVEX_L_KZ_B, /* 15105 */ + IC_EVEX_L_XS_KZ_B, /* 15106 */ + IC_EVEX_L_XS_KZ_B, /* 15107 */ + IC_EVEX_L_XD_KZ_B, /* 15108 */ + IC_EVEX_L_XD_KZ_B, /* 15109 */ + IC_EVEX_L_XD_KZ_B, /* 15110 */ + IC_EVEX_L_XD_KZ_B, /* 15111 */ + IC_EVEX_L_W_KZ_B, /* 15112 */ + IC_EVEX_L_W_KZ_B, /* 15113 */ + IC_EVEX_L_W_XS_KZ_B, /* 15114 */ + IC_EVEX_L_W_XS_KZ_B, /* 15115 */ + IC_EVEX_L_W_XD_KZ_B, /* 15116 */ + IC_EVEX_L_W_XD_KZ_B, /* 15117 */ + IC_EVEX_L_W_XD_KZ_B, /* 15118 */ + IC_EVEX_L_W_XD_KZ_B, /* 15119 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15120 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15121 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15122 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15123 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15124 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15125 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15126 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15127 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15128 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15129 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15130 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15131 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15132 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15133 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15134 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15135 */ + IC_EVEX_L_KZ_B, /* 15136 */ + IC_EVEX_L_KZ_B, /* 15137 */ + IC_EVEX_L_XS_KZ_B, /* 15138 */ + IC_EVEX_L_XS_KZ_B, /* 15139 */ + IC_EVEX_L_XD_KZ_B, /* 15140 */ + IC_EVEX_L_XD_KZ_B, /* 15141 */ + IC_EVEX_L_XD_KZ_B, /* 15142 */ + IC_EVEX_L_XD_KZ_B, /* 15143 */ + IC_EVEX_L_W_KZ_B, /* 15144 */ + IC_EVEX_L_W_KZ_B, /* 15145 */ + IC_EVEX_L_W_XS_KZ_B, /* 15146 */ + IC_EVEX_L_W_XS_KZ_B, /* 15147 */ + IC_EVEX_L_W_XD_KZ_B, /* 15148 */ + IC_EVEX_L_W_XD_KZ_B, /* 15149 */ + IC_EVEX_L_W_XD_KZ_B, /* 15150 */ + IC_EVEX_L_W_XD_KZ_B, /* 15151 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15152 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15153 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15154 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15155 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15156 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15157 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15158 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15159 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15160 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15161 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15162 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15163 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15164 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15165 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15166 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15167 */ + IC_EVEX_L_KZ_B, /* 15168 */ + IC_EVEX_L_KZ_B, /* 15169 */ + IC_EVEX_L_XS_KZ_B, /* 15170 */ + IC_EVEX_L_XS_KZ_B, /* 15171 */ + IC_EVEX_L_XD_KZ_B, /* 15172 */ + IC_EVEX_L_XD_KZ_B, /* 15173 */ + IC_EVEX_L_XD_KZ_B, /* 15174 */ + IC_EVEX_L_XD_KZ_B, /* 15175 */ + IC_EVEX_L_W_KZ_B, /* 15176 */ + IC_EVEX_L_W_KZ_B, /* 15177 */ + IC_EVEX_L_W_XS_KZ_B, /* 15178 */ + IC_EVEX_L_W_XS_KZ_B, /* 15179 */ + IC_EVEX_L_W_XD_KZ_B, /* 15180 */ + IC_EVEX_L_W_XD_KZ_B, /* 15181 */ + IC_EVEX_L_W_XD_KZ_B, /* 15182 */ + IC_EVEX_L_W_XD_KZ_B, /* 15183 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15184 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15185 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15186 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15187 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15188 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15189 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15190 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15191 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15192 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15193 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15194 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15195 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15196 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15197 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15198 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15199 */ + IC_EVEX_L_KZ_B, /* 15200 */ + IC_EVEX_L_KZ_B, /* 15201 */ + IC_EVEX_L_XS_KZ_B, /* 15202 */ + IC_EVEX_L_XS_KZ_B, /* 15203 */ + IC_EVEX_L_XD_KZ_B, /* 15204 */ + IC_EVEX_L_XD_KZ_B, /* 15205 */ + IC_EVEX_L_XD_KZ_B, /* 15206 */ + IC_EVEX_L_XD_KZ_B, /* 15207 */ + IC_EVEX_L_W_KZ_B, /* 15208 */ + IC_EVEX_L_W_KZ_B, /* 15209 */ + IC_EVEX_L_W_XS_KZ_B, /* 15210 */ + IC_EVEX_L_W_XS_KZ_B, /* 15211 */ + IC_EVEX_L_W_XD_KZ_B, /* 15212 */ + IC_EVEX_L_W_XD_KZ_B, /* 15213 */ + IC_EVEX_L_W_XD_KZ_B, /* 15214 */ + IC_EVEX_L_W_XD_KZ_B, /* 15215 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15216 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15217 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15218 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15219 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15220 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15221 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15222 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15223 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15224 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15225 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15226 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15227 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15228 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15229 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15230 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15231 */ + IC_EVEX_L_KZ_B, /* 15232 */ + IC_EVEX_L_KZ_B, /* 15233 */ + IC_EVEX_L_XS_KZ_B, /* 15234 */ + IC_EVEX_L_XS_KZ_B, /* 15235 */ + IC_EVEX_L_XD_KZ_B, /* 15236 */ + IC_EVEX_L_XD_KZ_B, /* 15237 */ + IC_EVEX_L_XD_KZ_B, /* 15238 */ + IC_EVEX_L_XD_KZ_B, /* 15239 */ + IC_EVEX_L_W_KZ_B, /* 15240 */ + IC_EVEX_L_W_KZ_B, /* 15241 */ + IC_EVEX_L_W_XS_KZ_B, /* 15242 */ + IC_EVEX_L_W_XS_KZ_B, /* 15243 */ + IC_EVEX_L_W_XD_KZ_B, /* 15244 */ + IC_EVEX_L_W_XD_KZ_B, /* 15245 */ + IC_EVEX_L_W_XD_KZ_B, /* 15246 */ + IC_EVEX_L_W_XD_KZ_B, /* 15247 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15248 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15249 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15250 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15251 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15252 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15253 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15254 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15255 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15256 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15257 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15258 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15259 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15260 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15261 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15262 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15263 */ + IC_EVEX_L_KZ_B, /* 15264 */ + IC_EVEX_L_KZ_B, /* 15265 */ + IC_EVEX_L_XS_KZ_B, /* 15266 */ + IC_EVEX_L_XS_KZ_B, /* 15267 */ + IC_EVEX_L_XD_KZ_B, /* 15268 */ + IC_EVEX_L_XD_KZ_B, /* 15269 */ + IC_EVEX_L_XD_KZ_B, /* 15270 */ + IC_EVEX_L_XD_KZ_B, /* 15271 */ + IC_EVEX_L_W_KZ_B, /* 15272 */ + IC_EVEX_L_W_KZ_B, /* 15273 */ + IC_EVEX_L_W_XS_KZ_B, /* 15274 */ + IC_EVEX_L_W_XS_KZ_B, /* 15275 */ + IC_EVEX_L_W_XD_KZ_B, /* 15276 */ + IC_EVEX_L_W_XD_KZ_B, /* 15277 */ + IC_EVEX_L_W_XD_KZ_B, /* 15278 */ + IC_EVEX_L_W_XD_KZ_B, /* 15279 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15280 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15281 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15282 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15283 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15284 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15285 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15286 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15287 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15288 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15289 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15290 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15291 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15292 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15293 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15294 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15295 */ + IC_EVEX_L_KZ_B, /* 15296 */ + IC_EVEX_L_KZ_B, /* 15297 */ + IC_EVEX_L_XS_KZ_B, /* 15298 */ + IC_EVEX_L_XS_KZ_B, /* 15299 */ + IC_EVEX_L_XD_KZ_B, /* 15300 */ + IC_EVEX_L_XD_KZ_B, /* 15301 */ + IC_EVEX_L_XD_KZ_B, /* 15302 */ + IC_EVEX_L_XD_KZ_B, /* 15303 */ + IC_EVEX_L_W_KZ_B, /* 15304 */ + IC_EVEX_L_W_KZ_B, /* 15305 */ + IC_EVEX_L_W_XS_KZ_B, /* 15306 */ + IC_EVEX_L_W_XS_KZ_B, /* 15307 */ + IC_EVEX_L_W_XD_KZ_B, /* 15308 */ + IC_EVEX_L_W_XD_KZ_B, /* 15309 */ + IC_EVEX_L_W_XD_KZ_B, /* 15310 */ + IC_EVEX_L_W_XD_KZ_B, /* 15311 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15312 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15313 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15314 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15315 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15316 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15317 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15318 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15319 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15320 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15321 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15322 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15323 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15324 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15325 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15326 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15327 */ + IC_EVEX_L_KZ_B, /* 15328 */ + IC_EVEX_L_KZ_B, /* 15329 */ + IC_EVEX_L_XS_KZ_B, /* 15330 */ + IC_EVEX_L_XS_KZ_B, /* 15331 */ + IC_EVEX_L_XD_KZ_B, /* 15332 */ + IC_EVEX_L_XD_KZ_B, /* 15333 */ + IC_EVEX_L_XD_KZ_B, /* 15334 */ + IC_EVEX_L_XD_KZ_B, /* 15335 */ + IC_EVEX_L_W_KZ_B, /* 15336 */ + IC_EVEX_L_W_KZ_B, /* 15337 */ + IC_EVEX_L_W_XS_KZ_B, /* 15338 */ + IC_EVEX_L_W_XS_KZ_B, /* 15339 */ + IC_EVEX_L_W_XD_KZ_B, /* 15340 */ + IC_EVEX_L_W_XD_KZ_B, /* 15341 */ + IC_EVEX_L_W_XD_KZ_B, /* 15342 */ + IC_EVEX_L_W_XD_KZ_B, /* 15343 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15344 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15345 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15346 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15347 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15348 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15349 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15350 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15351 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15352 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15353 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15354 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15355 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15356 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15357 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15358 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15359 */ + IC, /* 15360 */ + IC_64BIT, /* 15361 */ + IC_XS, /* 15362 */ + IC_64BIT_XS, /* 15363 */ + IC_XD, /* 15364 */ + IC_64BIT_XD, /* 15365 */ + IC_XS, /* 15366 */ + IC_64BIT_XS, /* 15367 */ + IC, /* 15368 */ + IC_64BIT_REXW, /* 15369 */ + IC_XS, /* 15370 */ + IC_64BIT_REXW_XS, /* 15371 */ + IC_XD, /* 15372 */ + IC_64BIT_REXW_XD, /* 15373 */ + IC_XS, /* 15374 */ + IC_64BIT_REXW_XS, /* 15375 */ + IC_OPSIZE, /* 15376 */ + IC_64BIT_OPSIZE, /* 15377 */ + IC_XS_OPSIZE, /* 15378 */ + IC_64BIT_XS_OPSIZE, /* 15379 */ + IC_XD_OPSIZE, /* 15380 */ + IC_64BIT_XD_OPSIZE, /* 15381 */ + IC_XS_OPSIZE, /* 15382 */ + IC_64BIT_XD_OPSIZE, /* 15383 */ + IC_OPSIZE, /* 15384 */ + IC_64BIT_REXW_OPSIZE, /* 15385 */ + IC_XS_OPSIZE, /* 15386 */ + IC_64BIT_REXW_XS, /* 15387 */ + IC_XD_OPSIZE, /* 15388 */ + IC_64BIT_REXW_XD, /* 15389 */ + IC_XS_OPSIZE, /* 15390 */ + IC_64BIT_REXW_XS, /* 15391 */ + IC_ADSIZE, /* 15392 */ + IC_64BIT_ADSIZE, /* 15393 */ + IC_XS_ADSIZE, /* 15394 */ + IC_64BIT_XS_ADSIZE, /* 15395 */ + IC_XD_ADSIZE, /* 15396 */ + IC_64BIT_XD_ADSIZE, /* 15397 */ + IC_XS_ADSIZE, /* 15398 */ + IC_64BIT_XD_ADSIZE, /* 15399 */ + IC_ADSIZE, /* 15400 */ + IC_64BIT_REXW_ADSIZE, /* 15401 */ + IC_XS_ADSIZE, /* 15402 */ + IC_64BIT_REXW_XS, /* 15403 */ + IC_XD_ADSIZE, /* 15404 */ + IC_64BIT_REXW_XD, /* 15405 */ + IC_XS_ADSIZE, /* 15406 */ + IC_64BIT_REXW_XS, /* 15407 */ + IC_OPSIZE_ADSIZE, /* 15408 */ + IC_64BIT_OPSIZE_ADSIZE, /* 15409 */ + IC_XS_OPSIZE, /* 15410 */ + IC_64BIT_XS_OPSIZE, /* 15411 */ + IC_XD_OPSIZE, /* 15412 */ + IC_64BIT_XD_OPSIZE, /* 15413 */ + IC_XS_OPSIZE, /* 15414 */ + IC_64BIT_XD_OPSIZE, /* 15415 */ + IC_OPSIZE_ADSIZE, /* 15416 */ + IC_64BIT_REXW_OPSIZE, /* 15417 */ + IC_XS_OPSIZE, /* 15418 */ + IC_64BIT_REXW_XS, /* 15419 */ + IC_XD_OPSIZE, /* 15420 */ + IC_64BIT_REXW_XD, /* 15421 */ + IC_XS_OPSIZE, /* 15422 */ + IC_64BIT_REXW_XS, /* 15423 */ + IC_VEX, /* 15424 */ + IC_VEX, /* 15425 */ + IC_VEX_XS, /* 15426 */ + IC_VEX_XS, /* 15427 */ + IC_VEX_XD, /* 15428 */ + IC_VEX_XD, /* 15429 */ + IC_VEX_XD, /* 15430 */ + IC_VEX_XD, /* 15431 */ + IC_VEX_W, /* 15432 */ + IC_VEX_W, /* 15433 */ + IC_VEX_W_XS, /* 15434 */ + IC_VEX_W_XS, /* 15435 */ + IC_VEX_W_XD, /* 15436 */ + IC_VEX_W_XD, /* 15437 */ + IC_VEX_W_XD, /* 15438 */ + IC_VEX_W_XD, /* 15439 */ + IC_VEX_OPSIZE, /* 15440 */ + IC_VEX_OPSIZE, /* 15441 */ + IC_VEX_OPSIZE, /* 15442 */ + IC_VEX_OPSIZE, /* 15443 */ + IC_VEX_OPSIZE, /* 15444 */ + IC_VEX_OPSIZE, /* 15445 */ + IC_VEX_OPSIZE, /* 15446 */ + IC_VEX_OPSIZE, /* 15447 */ + IC_VEX_W_OPSIZE, /* 15448 */ + IC_VEX_W_OPSIZE, /* 15449 */ + IC_VEX_W_OPSIZE, /* 15450 */ + IC_VEX_W_OPSIZE, /* 15451 */ + IC_VEX_W_OPSIZE, /* 15452 */ + IC_VEX_W_OPSIZE, /* 15453 */ + IC_VEX_W_OPSIZE, /* 15454 */ + IC_VEX_W_OPSIZE, /* 15455 */ + IC_VEX, /* 15456 */ + IC_VEX, /* 15457 */ + IC_VEX_XS, /* 15458 */ + IC_VEX_XS, /* 15459 */ + IC_VEX_XD, /* 15460 */ + IC_VEX_XD, /* 15461 */ + IC_VEX_XD, /* 15462 */ + IC_VEX_XD, /* 15463 */ + IC_VEX_W, /* 15464 */ + IC_VEX_W, /* 15465 */ + IC_VEX_W_XS, /* 15466 */ + IC_VEX_W_XS, /* 15467 */ + IC_VEX_W_XD, /* 15468 */ + IC_VEX_W_XD, /* 15469 */ + IC_VEX_W_XD, /* 15470 */ + IC_VEX_W_XD, /* 15471 */ + IC_VEX_OPSIZE, /* 15472 */ + IC_VEX_OPSIZE, /* 15473 */ + IC_VEX_OPSIZE, /* 15474 */ + IC_VEX_OPSIZE, /* 15475 */ + IC_VEX_OPSIZE, /* 15476 */ + IC_VEX_OPSIZE, /* 15477 */ + IC_VEX_OPSIZE, /* 15478 */ + IC_VEX_OPSIZE, /* 15479 */ + IC_VEX_W_OPSIZE, /* 15480 */ + IC_VEX_W_OPSIZE, /* 15481 */ + IC_VEX_W_OPSIZE, /* 15482 */ + IC_VEX_W_OPSIZE, /* 15483 */ + IC_VEX_W_OPSIZE, /* 15484 */ + IC_VEX_W_OPSIZE, /* 15485 */ + IC_VEX_W_OPSIZE, /* 15486 */ + IC_VEX_W_OPSIZE, /* 15487 */ + IC_VEX_L, /* 15488 */ + IC_VEX_L, /* 15489 */ + IC_VEX_L_XS, /* 15490 */ + IC_VEX_L_XS, /* 15491 */ + IC_VEX_L_XD, /* 15492 */ + IC_VEX_L_XD, /* 15493 */ + IC_VEX_L_XD, /* 15494 */ + IC_VEX_L_XD, /* 15495 */ + IC_VEX_L_W, /* 15496 */ + IC_VEX_L_W, /* 15497 */ + IC_VEX_L_W_XS, /* 15498 */ + IC_VEX_L_W_XS, /* 15499 */ + IC_VEX_L_W_XD, /* 15500 */ + IC_VEX_L_W_XD, /* 15501 */ + IC_VEX_L_W_XD, /* 15502 */ + IC_VEX_L_W_XD, /* 15503 */ + IC_VEX_L_OPSIZE, /* 15504 */ + IC_VEX_L_OPSIZE, /* 15505 */ + IC_VEX_L_OPSIZE, /* 15506 */ + IC_VEX_L_OPSIZE, /* 15507 */ + IC_VEX_L_OPSIZE, /* 15508 */ + IC_VEX_L_OPSIZE, /* 15509 */ + IC_VEX_L_OPSIZE, /* 15510 */ + IC_VEX_L_OPSIZE, /* 15511 */ + IC_VEX_L_W_OPSIZE, /* 15512 */ + IC_VEX_L_W_OPSIZE, /* 15513 */ + IC_VEX_L_W_OPSIZE, /* 15514 */ + IC_VEX_L_W_OPSIZE, /* 15515 */ + IC_VEX_L_W_OPSIZE, /* 15516 */ + IC_VEX_L_W_OPSIZE, /* 15517 */ + IC_VEX_L_W_OPSIZE, /* 15518 */ + IC_VEX_L_W_OPSIZE, /* 15519 */ + IC_VEX_L, /* 15520 */ + IC_VEX_L, /* 15521 */ + IC_VEX_L_XS, /* 15522 */ + IC_VEX_L_XS, /* 15523 */ + IC_VEX_L_XD, /* 15524 */ + IC_VEX_L_XD, /* 15525 */ + IC_VEX_L_XD, /* 15526 */ + IC_VEX_L_XD, /* 15527 */ + IC_VEX_L_W, /* 15528 */ + IC_VEX_L_W, /* 15529 */ + IC_VEX_L_W_XS, /* 15530 */ + IC_VEX_L_W_XS, /* 15531 */ + IC_VEX_L_W_XD, /* 15532 */ + IC_VEX_L_W_XD, /* 15533 */ + IC_VEX_L_W_XD, /* 15534 */ + IC_VEX_L_W_XD, /* 15535 */ + IC_VEX_L_OPSIZE, /* 15536 */ + IC_VEX_L_OPSIZE, /* 15537 */ + IC_VEX_L_OPSIZE, /* 15538 */ + IC_VEX_L_OPSIZE, /* 15539 */ + IC_VEX_L_OPSIZE, /* 15540 */ + IC_VEX_L_OPSIZE, /* 15541 */ + IC_VEX_L_OPSIZE, /* 15542 */ + IC_VEX_L_OPSIZE, /* 15543 */ + IC_VEX_L_W_OPSIZE, /* 15544 */ + IC_VEX_L_W_OPSIZE, /* 15545 */ + IC_VEX_L_W_OPSIZE, /* 15546 */ + IC_VEX_L_W_OPSIZE, /* 15547 */ + IC_VEX_L_W_OPSIZE, /* 15548 */ + IC_VEX_L_W_OPSIZE, /* 15549 */ + IC_VEX_L_W_OPSIZE, /* 15550 */ + IC_VEX_L_W_OPSIZE, /* 15551 */ + IC_VEX_L, /* 15552 */ + IC_VEX_L, /* 15553 */ + IC_VEX_L_XS, /* 15554 */ + IC_VEX_L_XS, /* 15555 */ + IC_VEX_L_XD, /* 15556 */ + IC_VEX_L_XD, /* 15557 */ + IC_VEX_L_XD, /* 15558 */ + IC_VEX_L_XD, /* 15559 */ + IC_VEX_L_W, /* 15560 */ + IC_VEX_L_W, /* 15561 */ + IC_VEX_L_W_XS, /* 15562 */ + IC_VEX_L_W_XS, /* 15563 */ + IC_VEX_L_W_XD, /* 15564 */ + IC_VEX_L_W_XD, /* 15565 */ + IC_VEX_L_W_XD, /* 15566 */ + IC_VEX_L_W_XD, /* 15567 */ + IC_VEX_L_OPSIZE, /* 15568 */ + IC_VEX_L_OPSIZE, /* 15569 */ + IC_VEX_L_OPSIZE, /* 15570 */ + IC_VEX_L_OPSIZE, /* 15571 */ + IC_VEX_L_OPSIZE, /* 15572 */ + IC_VEX_L_OPSIZE, /* 15573 */ + IC_VEX_L_OPSIZE, /* 15574 */ + IC_VEX_L_OPSIZE, /* 15575 */ + IC_VEX_L_W_OPSIZE, /* 15576 */ + IC_VEX_L_W_OPSIZE, /* 15577 */ + IC_VEX_L_W_OPSIZE, /* 15578 */ + IC_VEX_L_W_OPSIZE, /* 15579 */ + IC_VEX_L_W_OPSIZE, /* 15580 */ + IC_VEX_L_W_OPSIZE, /* 15581 */ + IC_VEX_L_W_OPSIZE, /* 15582 */ + IC_VEX_L_W_OPSIZE, /* 15583 */ + IC_VEX_L, /* 15584 */ + IC_VEX_L, /* 15585 */ + IC_VEX_L_XS, /* 15586 */ + IC_VEX_L_XS, /* 15587 */ + IC_VEX_L_XD, /* 15588 */ + IC_VEX_L_XD, /* 15589 */ + IC_VEX_L_XD, /* 15590 */ + IC_VEX_L_XD, /* 15591 */ + IC_VEX_L_W, /* 15592 */ + IC_VEX_L_W, /* 15593 */ + IC_VEX_L_W_XS, /* 15594 */ + IC_VEX_L_W_XS, /* 15595 */ + IC_VEX_L_W_XD, /* 15596 */ + IC_VEX_L_W_XD, /* 15597 */ + IC_VEX_L_W_XD, /* 15598 */ + IC_VEX_L_W_XD, /* 15599 */ + IC_VEX_L_OPSIZE, /* 15600 */ + IC_VEX_L_OPSIZE, /* 15601 */ + IC_VEX_L_OPSIZE, /* 15602 */ + IC_VEX_L_OPSIZE, /* 15603 */ + IC_VEX_L_OPSIZE, /* 15604 */ + IC_VEX_L_OPSIZE, /* 15605 */ + IC_VEX_L_OPSIZE, /* 15606 */ + IC_VEX_L_OPSIZE, /* 15607 */ + IC_VEX_L_W_OPSIZE, /* 15608 */ + IC_VEX_L_W_OPSIZE, /* 15609 */ + IC_VEX_L_W_OPSIZE, /* 15610 */ + IC_VEX_L_W_OPSIZE, /* 15611 */ + IC_VEX_L_W_OPSIZE, /* 15612 */ + IC_VEX_L_W_OPSIZE, /* 15613 */ + IC_VEX_L_W_OPSIZE, /* 15614 */ + IC_VEX_L_W_OPSIZE, /* 15615 */ + IC_EVEX_L2_KZ_B, /* 15616 */ + IC_EVEX_L2_KZ_B, /* 15617 */ + IC_EVEX_L2_XS_KZ_B, /* 15618 */ + IC_EVEX_L2_XS_KZ_B, /* 15619 */ + IC_EVEX_L2_XD_KZ_B, /* 15620 */ + IC_EVEX_L2_XD_KZ_B, /* 15621 */ + IC_EVEX_L2_XD_KZ_B, /* 15622 */ + IC_EVEX_L2_XD_KZ_B, /* 15623 */ + IC_EVEX_L2_W_KZ_B, /* 15624 */ + IC_EVEX_L2_W_KZ_B, /* 15625 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15626 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15627 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15628 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15629 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15630 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15631 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15632 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15633 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15634 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15635 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15636 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15637 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15638 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15639 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15640 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15641 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15642 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15643 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15644 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15645 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15646 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15647 */ + IC_EVEX_L2_KZ_B, /* 15648 */ + IC_EVEX_L2_KZ_B, /* 15649 */ + IC_EVEX_L2_XS_KZ_B, /* 15650 */ + IC_EVEX_L2_XS_KZ_B, /* 15651 */ + IC_EVEX_L2_XD_KZ_B, /* 15652 */ + IC_EVEX_L2_XD_KZ_B, /* 15653 */ + IC_EVEX_L2_XD_KZ_B, /* 15654 */ + IC_EVEX_L2_XD_KZ_B, /* 15655 */ + IC_EVEX_L2_W_KZ_B, /* 15656 */ + IC_EVEX_L2_W_KZ_B, /* 15657 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15658 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15659 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15660 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15661 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15662 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15663 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15664 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15665 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15666 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15667 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15668 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15669 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15670 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15671 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15672 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15673 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15674 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15675 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15676 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15677 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15678 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15679 */ + IC_EVEX_L2_KZ_B, /* 15680 */ + IC_EVEX_L2_KZ_B, /* 15681 */ + IC_EVEX_L2_XS_KZ_B, /* 15682 */ + IC_EVEX_L2_XS_KZ_B, /* 15683 */ + IC_EVEX_L2_XD_KZ_B, /* 15684 */ + IC_EVEX_L2_XD_KZ_B, /* 15685 */ + IC_EVEX_L2_XD_KZ_B, /* 15686 */ + IC_EVEX_L2_XD_KZ_B, /* 15687 */ + IC_EVEX_L2_W_KZ_B, /* 15688 */ + IC_EVEX_L2_W_KZ_B, /* 15689 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15690 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15691 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15692 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15693 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15694 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15695 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15696 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15697 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15698 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15699 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15700 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15701 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15702 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15703 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15704 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15705 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15706 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15707 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15708 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15709 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15710 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15711 */ + IC_EVEX_L2_KZ_B, /* 15712 */ + IC_EVEX_L2_KZ_B, /* 15713 */ + IC_EVEX_L2_XS_KZ_B, /* 15714 */ + IC_EVEX_L2_XS_KZ_B, /* 15715 */ + IC_EVEX_L2_XD_KZ_B, /* 15716 */ + IC_EVEX_L2_XD_KZ_B, /* 15717 */ + IC_EVEX_L2_XD_KZ_B, /* 15718 */ + IC_EVEX_L2_XD_KZ_B, /* 15719 */ + IC_EVEX_L2_W_KZ_B, /* 15720 */ + IC_EVEX_L2_W_KZ_B, /* 15721 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15722 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15723 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15724 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15725 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15726 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15727 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15728 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15729 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15730 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15731 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15732 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15733 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15734 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15735 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15736 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15737 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15738 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15739 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15740 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15741 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15742 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15743 */ + IC_EVEX_L2_KZ_B, /* 15744 */ + IC_EVEX_L2_KZ_B, /* 15745 */ + IC_EVEX_L2_XS_KZ_B, /* 15746 */ + IC_EVEX_L2_XS_KZ_B, /* 15747 */ + IC_EVEX_L2_XD_KZ_B, /* 15748 */ + IC_EVEX_L2_XD_KZ_B, /* 15749 */ + IC_EVEX_L2_XD_KZ_B, /* 15750 */ + IC_EVEX_L2_XD_KZ_B, /* 15751 */ + IC_EVEX_L2_W_KZ_B, /* 15752 */ + IC_EVEX_L2_W_KZ_B, /* 15753 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15754 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15755 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15756 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15757 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15758 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15759 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15760 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15761 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15762 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15763 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15764 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15765 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15766 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15767 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15768 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15769 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15770 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15771 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15772 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15773 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15774 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15775 */ + IC_EVEX_L2_KZ_B, /* 15776 */ + IC_EVEX_L2_KZ_B, /* 15777 */ + IC_EVEX_L2_XS_KZ_B, /* 15778 */ + IC_EVEX_L2_XS_KZ_B, /* 15779 */ + IC_EVEX_L2_XD_KZ_B, /* 15780 */ + IC_EVEX_L2_XD_KZ_B, /* 15781 */ + IC_EVEX_L2_XD_KZ_B, /* 15782 */ + IC_EVEX_L2_XD_KZ_B, /* 15783 */ + IC_EVEX_L2_W_KZ_B, /* 15784 */ + IC_EVEX_L2_W_KZ_B, /* 15785 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15786 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15787 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15788 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15789 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15790 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15791 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15792 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15793 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15794 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15795 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15796 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15797 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15798 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15799 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15800 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15801 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15802 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15803 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15804 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15805 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15806 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15807 */ + IC_EVEX_L2_KZ_B, /* 15808 */ + IC_EVEX_L2_KZ_B, /* 15809 */ + IC_EVEX_L2_XS_KZ_B, /* 15810 */ + IC_EVEX_L2_XS_KZ_B, /* 15811 */ + IC_EVEX_L2_XD_KZ_B, /* 15812 */ + IC_EVEX_L2_XD_KZ_B, /* 15813 */ + IC_EVEX_L2_XD_KZ_B, /* 15814 */ + IC_EVEX_L2_XD_KZ_B, /* 15815 */ + IC_EVEX_L2_W_KZ_B, /* 15816 */ + IC_EVEX_L2_W_KZ_B, /* 15817 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15818 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15819 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15820 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15821 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15822 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15823 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15824 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15825 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15826 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15827 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15828 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15829 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15830 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15831 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15832 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15833 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15834 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15835 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15836 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15837 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15838 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15839 */ + IC_EVEX_L2_KZ_B, /* 15840 */ + IC_EVEX_L2_KZ_B, /* 15841 */ + IC_EVEX_L2_XS_KZ_B, /* 15842 */ + IC_EVEX_L2_XS_KZ_B, /* 15843 */ + IC_EVEX_L2_XD_KZ_B, /* 15844 */ + IC_EVEX_L2_XD_KZ_B, /* 15845 */ + IC_EVEX_L2_XD_KZ_B, /* 15846 */ + IC_EVEX_L2_XD_KZ_B, /* 15847 */ + IC_EVEX_L2_W_KZ_B, /* 15848 */ + IC_EVEX_L2_W_KZ_B, /* 15849 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15850 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15851 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15852 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15853 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15854 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15855 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15856 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15857 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15858 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15859 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15860 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15861 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15862 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15863 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15864 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15865 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15866 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15867 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15868 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15869 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15870 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15871 */ + IC, /* 15872 */ + IC_64BIT, /* 15873 */ + IC_XS, /* 15874 */ + IC_64BIT_XS, /* 15875 */ + IC_XD, /* 15876 */ + IC_64BIT_XD, /* 15877 */ + IC_XS, /* 15878 */ + IC_64BIT_XS, /* 15879 */ + IC, /* 15880 */ + IC_64BIT_REXW, /* 15881 */ + IC_XS, /* 15882 */ + IC_64BIT_REXW_XS, /* 15883 */ + IC_XD, /* 15884 */ + IC_64BIT_REXW_XD, /* 15885 */ + IC_XS, /* 15886 */ + IC_64BIT_REXW_XS, /* 15887 */ + IC_OPSIZE, /* 15888 */ + IC_64BIT_OPSIZE, /* 15889 */ + IC_XS_OPSIZE, /* 15890 */ + IC_64BIT_XS_OPSIZE, /* 15891 */ + IC_XD_OPSIZE, /* 15892 */ + IC_64BIT_XD_OPSIZE, /* 15893 */ + IC_XS_OPSIZE, /* 15894 */ + IC_64BIT_XD_OPSIZE, /* 15895 */ + IC_OPSIZE, /* 15896 */ + IC_64BIT_REXW_OPSIZE, /* 15897 */ + IC_XS_OPSIZE, /* 15898 */ + IC_64BIT_REXW_XS, /* 15899 */ + IC_XD_OPSIZE, /* 15900 */ + IC_64BIT_REXW_XD, /* 15901 */ + IC_XS_OPSIZE, /* 15902 */ + IC_64BIT_REXW_XS, /* 15903 */ + IC_ADSIZE, /* 15904 */ + IC_64BIT_ADSIZE, /* 15905 */ + IC_XS_ADSIZE, /* 15906 */ + IC_64BIT_XS_ADSIZE, /* 15907 */ + IC_XD_ADSIZE, /* 15908 */ + IC_64BIT_XD_ADSIZE, /* 15909 */ + IC_XS_ADSIZE, /* 15910 */ + IC_64BIT_XD_ADSIZE, /* 15911 */ + IC_ADSIZE, /* 15912 */ + IC_64BIT_REXW_ADSIZE, /* 15913 */ + IC_XS_ADSIZE, /* 15914 */ + IC_64BIT_REXW_XS, /* 15915 */ + IC_XD_ADSIZE, /* 15916 */ + IC_64BIT_REXW_XD, /* 15917 */ + IC_XS_ADSIZE, /* 15918 */ + IC_64BIT_REXW_XS, /* 15919 */ + IC_OPSIZE_ADSIZE, /* 15920 */ + IC_64BIT_OPSIZE_ADSIZE, /* 15921 */ + IC_XS_OPSIZE, /* 15922 */ + IC_64BIT_XS_OPSIZE, /* 15923 */ + IC_XD_OPSIZE, /* 15924 */ + IC_64BIT_XD_OPSIZE, /* 15925 */ + IC_XS_OPSIZE, /* 15926 */ + IC_64BIT_XD_OPSIZE, /* 15927 */ + IC_OPSIZE_ADSIZE, /* 15928 */ + IC_64BIT_REXW_OPSIZE, /* 15929 */ + IC_XS_OPSIZE, /* 15930 */ + IC_64BIT_REXW_XS, /* 15931 */ + IC_XD_OPSIZE, /* 15932 */ + IC_64BIT_REXW_XD, /* 15933 */ + IC_XS_OPSIZE, /* 15934 */ + IC_64BIT_REXW_XS, /* 15935 */ + IC_VEX, /* 15936 */ + IC_VEX, /* 15937 */ + IC_VEX_XS, /* 15938 */ + IC_VEX_XS, /* 15939 */ + IC_VEX_XD, /* 15940 */ + IC_VEX_XD, /* 15941 */ + IC_VEX_XD, /* 15942 */ + IC_VEX_XD, /* 15943 */ + IC_VEX_W, /* 15944 */ + IC_VEX_W, /* 15945 */ + IC_VEX_W_XS, /* 15946 */ + IC_VEX_W_XS, /* 15947 */ + IC_VEX_W_XD, /* 15948 */ + IC_VEX_W_XD, /* 15949 */ + IC_VEX_W_XD, /* 15950 */ + IC_VEX_W_XD, /* 15951 */ + IC_VEX_OPSIZE, /* 15952 */ + IC_VEX_OPSIZE, /* 15953 */ + IC_VEX_OPSIZE, /* 15954 */ + IC_VEX_OPSIZE, /* 15955 */ + IC_VEX_OPSIZE, /* 15956 */ + IC_VEX_OPSIZE, /* 15957 */ + IC_VEX_OPSIZE, /* 15958 */ + IC_VEX_OPSIZE, /* 15959 */ + IC_VEX_W_OPSIZE, /* 15960 */ + IC_VEX_W_OPSIZE, /* 15961 */ + IC_VEX_W_OPSIZE, /* 15962 */ + IC_VEX_W_OPSIZE, /* 15963 */ + IC_VEX_W_OPSIZE, /* 15964 */ + IC_VEX_W_OPSIZE, /* 15965 */ + IC_VEX_W_OPSIZE, /* 15966 */ + IC_VEX_W_OPSIZE, /* 15967 */ + IC_VEX, /* 15968 */ + IC_VEX, /* 15969 */ + IC_VEX_XS, /* 15970 */ + IC_VEX_XS, /* 15971 */ + IC_VEX_XD, /* 15972 */ + IC_VEX_XD, /* 15973 */ + IC_VEX_XD, /* 15974 */ + IC_VEX_XD, /* 15975 */ + IC_VEX_W, /* 15976 */ + IC_VEX_W, /* 15977 */ + IC_VEX_W_XS, /* 15978 */ + IC_VEX_W_XS, /* 15979 */ + IC_VEX_W_XD, /* 15980 */ + IC_VEX_W_XD, /* 15981 */ + IC_VEX_W_XD, /* 15982 */ + IC_VEX_W_XD, /* 15983 */ + IC_VEX_OPSIZE, /* 15984 */ + IC_VEX_OPSIZE, /* 15985 */ + IC_VEX_OPSIZE, /* 15986 */ + IC_VEX_OPSIZE, /* 15987 */ + IC_VEX_OPSIZE, /* 15988 */ + IC_VEX_OPSIZE, /* 15989 */ + IC_VEX_OPSIZE, /* 15990 */ + IC_VEX_OPSIZE, /* 15991 */ + IC_VEX_W_OPSIZE, /* 15992 */ + IC_VEX_W_OPSIZE, /* 15993 */ + IC_VEX_W_OPSIZE, /* 15994 */ + IC_VEX_W_OPSIZE, /* 15995 */ + IC_VEX_W_OPSIZE, /* 15996 */ + IC_VEX_W_OPSIZE, /* 15997 */ + IC_VEX_W_OPSIZE, /* 15998 */ + IC_VEX_W_OPSIZE, /* 15999 */ + IC_VEX_L, /* 16000 */ + IC_VEX_L, /* 16001 */ + IC_VEX_L_XS, /* 16002 */ + IC_VEX_L_XS, /* 16003 */ + IC_VEX_L_XD, /* 16004 */ + IC_VEX_L_XD, /* 16005 */ + IC_VEX_L_XD, /* 16006 */ + IC_VEX_L_XD, /* 16007 */ + IC_VEX_L_W, /* 16008 */ + IC_VEX_L_W, /* 16009 */ + IC_VEX_L_W_XS, /* 16010 */ + IC_VEX_L_W_XS, /* 16011 */ + IC_VEX_L_W_XD, /* 16012 */ + IC_VEX_L_W_XD, /* 16013 */ + IC_VEX_L_W_XD, /* 16014 */ + IC_VEX_L_W_XD, /* 16015 */ + IC_VEX_L_OPSIZE, /* 16016 */ + IC_VEX_L_OPSIZE, /* 16017 */ + IC_VEX_L_OPSIZE, /* 16018 */ + IC_VEX_L_OPSIZE, /* 16019 */ + IC_VEX_L_OPSIZE, /* 16020 */ + IC_VEX_L_OPSIZE, /* 16021 */ + IC_VEX_L_OPSIZE, /* 16022 */ + IC_VEX_L_OPSIZE, /* 16023 */ + IC_VEX_L_W_OPSIZE, /* 16024 */ + IC_VEX_L_W_OPSIZE, /* 16025 */ + IC_VEX_L_W_OPSIZE, /* 16026 */ + IC_VEX_L_W_OPSIZE, /* 16027 */ + IC_VEX_L_W_OPSIZE, /* 16028 */ + IC_VEX_L_W_OPSIZE, /* 16029 */ + IC_VEX_L_W_OPSIZE, /* 16030 */ + IC_VEX_L_W_OPSIZE, /* 16031 */ + IC_VEX_L, /* 16032 */ + IC_VEX_L, /* 16033 */ + IC_VEX_L_XS, /* 16034 */ + IC_VEX_L_XS, /* 16035 */ + IC_VEX_L_XD, /* 16036 */ + IC_VEX_L_XD, /* 16037 */ + IC_VEX_L_XD, /* 16038 */ + IC_VEX_L_XD, /* 16039 */ + IC_VEX_L_W, /* 16040 */ + IC_VEX_L_W, /* 16041 */ + IC_VEX_L_W_XS, /* 16042 */ + IC_VEX_L_W_XS, /* 16043 */ + IC_VEX_L_W_XD, /* 16044 */ + IC_VEX_L_W_XD, /* 16045 */ + IC_VEX_L_W_XD, /* 16046 */ + IC_VEX_L_W_XD, /* 16047 */ + IC_VEX_L_OPSIZE, /* 16048 */ + IC_VEX_L_OPSIZE, /* 16049 */ + IC_VEX_L_OPSIZE, /* 16050 */ + IC_VEX_L_OPSIZE, /* 16051 */ + IC_VEX_L_OPSIZE, /* 16052 */ + IC_VEX_L_OPSIZE, /* 16053 */ + IC_VEX_L_OPSIZE, /* 16054 */ + IC_VEX_L_OPSIZE, /* 16055 */ + IC_VEX_L_W_OPSIZE, /* 16056 */ + IC_VEX_L_W_OPSIZE, /* 16057 */ + IC_VEX_L_W_OPSIZE, /* 16058 */ + IC_VEX_L_W_OPSIZE, /* 16059 */ + IC_VEX_L_W_OPSIZE, /* 16060 */ + IC_VEX_L_W_OPSIZE, /* 16061 */ + IC_VEX_L_W_OPSIZE, /* 16062 */ + IC_VEX_L_W_OPSIZE, /* 16063 */ + IC_VEX_L, /* 16064 */ + IC_VEX_L, /* 16065 */ + IC_VEX_L_XS, /* 16066 */ + IC_VEX_L_XS, /* 16067 */ + IC_VEX_L_XD, /* 16068 */ + IC_VEX_L_XD, /* 16069 */ + IC_VEX_L_XD, /* 16070 */ + IC_VEX_L_XD, /* 16071 */ + IC_VEX_L_W, /* 16072 */ + IC_VEX_L_W, /* 16073 */ + IC_VEX_L_W_XS, /* 16074 */ + IC_VEX_L_W_XS, /* 16075 */ + IC_VEX_L_W_XD, /* 16076 */ + IC_VEX_L_W_XD, /* 16077 */ + IC_VEX_L_W_XD, /* 16078 */ + IC_VEX_L_W_XD, /* 16079 */ + IC_VEX_L_OPSIZE, /* 16080 */ + IC_VEX_L_OPSIZE, /* 16081 */ + IC_VEX_L_OPSIZE, /* 16082 */ + IC_VEX_L_OPSIZE, /* 16083 */ + IC_VEX_L_OPSIZE, /* 16084 */ + IC_VEX_L_OPSIZE, /* 16085 */ + IC_VEX_L_OPSIZE, /* 16086 */ + IC_VEX_L_OPSIZE, /* 16087 */ + IC_VEX_L_W_OPSIZE, /* 16088 */ + IC_VEX_L_W_OPSIZE, /* 16089 */ + IC_VEX_L_W_OPSIZE, /* 16090 */ + IC_VEX_L_W_OPSIZE, /* 16091 */ + IC_VEX_L_W_OPSIZE, /* 16092 */ + IC_VEX_L_W_OPSIZE, /* 16093 */ + IC_VEX_L_W_OPSIZE, /* 16094 */ + IC_VEX_L_W_OPSIZE, /* 16095 */ + IC_VEX_L, /* 16096 */ + IC_VEX_L, /* 16097 */ + IC_VEX_L_XS, /* 16098 */ + IC_VEX_L_XS, /* 16099 */ + IC_VEX_L_XD, /* 16100 */ + IC_VEX_L_XD, /* 16101 */ + IC_VEX_L_XD, /* 16102 */ + IC_VEX_L_XD, /* 16103 */ + IC_VEX_L_W, /* 16104 */ + IC_VEX_L_W, /* 16105 */ + IC_VEX_L_W_XS, /* 16106 */ + IC_VEX_L_W_XS, /* 16107 */ + IC_VEX_L_W_XD, /* 16108 */ + IC_VEX_L_W_XD, /* 16109 */ + IC_VEX_L_W_XD, /* 16110 */ + IC_VEX_L_W_XD, /* 16111 */ + IC_VEX_L_OPSIZE, /* 16112 */ + IC_VEX_L_OPSIZE, /* 16113 */ + IC_VEX_L_OPSIZE, /* 16114 */ + IC_VEX_L_OPSIZE, /* 16115 */ + IC_VEX_L_OPSIZE, /* 16116 */ + IC_VEX_L_OPSIZE, /* 16117 */ + IC_VEX_L_OPSIZE, /* 16118 */ + IC_VEX_L_OPSIZE, /* 16119 */ + IC_VEX_L_W_OPSIZE, /* 16120 */ + IC_VEX_L_W_OPSIZE, /* 16121 */ + IC_VEX_L_W_OPSIZE, /* 16122 */ + IC_VEX_L_W_OPSIZE, /* 16123 */ + IC_VEX_L_W_OPSIZE, /* 16124 */ + IC_VEX_L_W_OPSIZE, /* 16125 */ + IC_VEX_L_W_OPSIZE, /* 16126 */ + IC_VEX_L_W_OPSIZE, /* 16127 */ + IC_EVEX_L2_KZ_B, /* 16128 */ + IC_EVEX_L2_KZ_B, /* 16129 */ + IC_EVEX_L2_XS_KZ_B, /* 16130 */ + IC_EVEX_L2_XS_KZ_B, /* 16131 */ + IC_EVEX_L2_XD_KZ_B, /* 16132 */ + IC_EVEX_L2_XD_KZ_B, /* 16133 */ + IC_EVEX_L2_XD_KZ_B, /* 16134 */ + IC_EVEX_L2_XD_KZ_B, /* 16135 */ + IC_EVEX_L2_W_KZ_B, /* 16136 */ + IC_EVEX_L2_W_KZ_B, /* 16137 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16138 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16139 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16140 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16141 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16142 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16143 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16144 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16145 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16146 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16147 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16148 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16149 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16150 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16151 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16152 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16153 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16154 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16155 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16156 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16157 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16158 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16159 */ + IC_EVEX_L2_KZ_B, /* 16160 */ + IC_EVEX_L2_KZ_B, /* 16161 */ + IC_EVEX_L2_XS_KZ_B, /* 16162 */ + IC_EVEX_L2_XS_KZ_B, /* 16163 */ + IC_EVEX_L2_XD_KZ_B, /* 16164 */ + IC_EVEX_L2_XD_KZ_B, /* 16165 */ + IC_EVEX_L2_XD_KZ_B, /* 16166 */ + IC_EVEX_L2_XD_KZ_B, /* 16167 */ + IC_EVEX_L2_W_KZ_B, /* 16168 */ + IC_EVEX_L2_W_KZ_B, /* 16169 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16170 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16171 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16172 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16173 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16174 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16175 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16176 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16177 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16178 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16179 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16180 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16181 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16182 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16183 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16184 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16185 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16186 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16187 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16188 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16189 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16190 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16191 */ + IC_EVEX_L2_KZ_B, /* 16192 */ + IC_EVEX_L2_KZ_B, /* 16193 */ + IC_EVEX_L2_XS_KZ_B, /* 16194 */ + IC_EVEX_L2_XS_KZ_B, /* 16195 */ + IC_EVEX_L2_XD_KZ_B, /* 16196 */ + IC_EVEX_L2_XD_KZ_B, /* 16197 */ + IC_EVEX_L2_XD_KZ_B, /* 16198 */ + IC_EVEX_L2_XD_KZ_B, /* 16199 */ + IC_EVEX_L2_W_KZ_B, /* 16200 */ + IC_EVEX_L2_W_KZ_B, /* 16201 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16202 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16203 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16204 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16205 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16206 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16207 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16208 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16209 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16210 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16211 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16212 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16213 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16214 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16215 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16216 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16217 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16218 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16219 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16220 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16221 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16222 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16223 */ + IC_EVEX_L2_KZ_B, /* 16224 */ + IC_EVEX_L2_KZ_B, /* 16225 */ + IC_EVEX_L2_XS_KZ_B, /* 16226 */ + IC_EVEX_L2_XS_KZ_B, /* 16227 */ + IC_EVEX_L2_XD_KZ_B, /* 16228 */ + IC_EVEX_L2_XD_KZ_B, /* 16229 */ + IC_EVEX_L2_XD_KZ_B, /* 16230 */ + IC_EVEX_L2_XD_KZ_B, /* 16231 */ + IC_EVEX_L2_W_KZ_B, /* 16232 */ + IC_EVEX_L2_W_KZ_B, /* 16233 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16234 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16235 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16236 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16237 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16238 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16239 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16240 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16241 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16242 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16243 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16244 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16245 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16246 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16247 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16248 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16249 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16250 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16251 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16252 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16253 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16254 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16255 */ + IC_EVEX_L2_KZ_B, /* 16256 */ + IC_EVEX_L2_KZ_B, /* 16257 */ + IC_EVEX_L2_XS_KZ_B, /* 16258 */ + IC_EVEX_L2_XS_KZ_B, /* 16259 */ + IC_EVEX_L2_XD_KZ_B, /* 16260 */ + IC_EVEX_L2_XD_KZ_B, /* 16261 */ + IC_EVEX_L2_XD_KZ_B, /* 16262 */ + IC_EVEX_L2_XD_KZ_B, /* 16263 */ + IC_EVEX_L2_W_KZ_B, /* 16264 */ + IC_EVEX_L2_W_KZ_B, /* 16265 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16266 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16267 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16268 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16269 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16270 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16271 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16272 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16273 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16274 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16275 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16276 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16277 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16278 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16279 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16280 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16281 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16282 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16283 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16284 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16285 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16286 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16287 */ + IC_EVEX_L2_KZ_B, /* 16288 */ + IC_EVEX_L2_KZ_B, /* 16289 */ + IC_EVEX_L2_XS_KZ_B, /* 16290 */ + IC_EVEX_L2_XS_KZ_B, /* 16291 */ + IC_EVEX_L2_XD_KZ_B, /* 16292 */ + IC_EVEX_L2_XD_KZ_B, /* 16293 */ + IC_EVEX_L2_XD_KZ_B, /* 16294 */ + IC_EVEX_L2_XD_KZ_B, /* 16295 */ + IC_EVEX_L2_W_KZ_B, /* 16296 */ + IC_EVEX_L2_W_KZ_B, /* 16297 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16298 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16299 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16300 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16301 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16302 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16303 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16304 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16305 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16306 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16307 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16308 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16309 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16310 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16311 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16312 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16313 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16314 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16315 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16316 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16317 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16318 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16319 */ + IC_EVEX_L2_KZ_B, /* 16320 */ + IC_EVEX_L2_KZ_B, /* 16321 */ + IC_EVEX_L2_XS_KZ_B, /* 16322 */ + IC_EVEX_L2_XS_KZ_B, /* 16323 */ + IC_EVEX_L2_XD_KZ_B, /* 16324 */ + IC_EVEX_L2_XD_KZ_B, /* 16325 */ + IC_EVEX_L2_XD_KZ_B, /* 16326 */ + IC_EVEX_L2_XD_KZ_B, /* 16327 */ + IC_EVEX_L2_W_KZ_B, /* 16328 */ + IC_EVEX_L2_W_KZ_B, /* 16329 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16330 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16331 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16332 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16333 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16334 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16335 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16336 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16337 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16338 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16339 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16340 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16341 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16342 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16343 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16344 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16345 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16346 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16347 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16348 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16349 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16350 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16351 */ + IC_EVEX_L2_KZ_B, /* 16352 */ + IC_EVEX_L2_KZ_B, /* 16353 */ + IC_EVEX_L2_XS_KZ_B, /* 16354 */ + IC_EVEX_L2_XS_KZ_B, /* 16355 */ + IC_EVEX_L2_XD_KZ_B, /* 16356 */ + IC_EVEX_L2_XD_KZ_B, /* 16357 */ + IC_EVEX_L2_XD_KZ_B, /* 16358 */ + IC_EVEX_L2_XD_KZ_B, /* 16359 */ + IC_EVEX_L2_W_KZ_B, /* 16360 */ + IC_EVEX_L2_W_KZ_B, /* 16361 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16362 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16363 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16364 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16365 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16366 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16367 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16368 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16369 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16370 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16371 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16372 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16373 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16374 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16375 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16376 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16377 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16378 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16379 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16380 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16381 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16382 */ + IC_EVEX_L2_W_OPSIZE_KZ_B /* 16383 */ +}; + +static const InstrUID modRMTable[] = { +/* EmptyTable */ + 0x0, +/* Table1 */ + 0xe0, /* ADD8mr */ + 0xe4, /* ADD8rr */ +/* Table3 */ + 0xce, /* ADD32mr */ + 0xd2, /* ADD32rr */ +/* Table5 */ + 0xe3, /* ADD8rm */ + 0xe5, /* ADD8rr_REV */ +/* Table7 */ + 0xd1, /* ADD32rm */ + 0xd3, /* ADD32rr_REV */ +/* Table9 */ + 0xdd, /* ADD8i8 */ +/* Table10 */ + 0xcb, /* ADD32i32 */ +/* Table11 */ + 0x8cb, /* PUSHES32 */ +/* Table12 */ + 0x850, /* POPES32 */ +/* Table13 */ + 0x749, /* OR8mr */ + 0x74d, /* OR8rr */ +/* Table15 */ + 0x737, /* OR32mr */ + 0x73b, /* OR32rr */ +/* Table17 */ + 0x74c, /* OR8rm */ + 0x74e, /* OR8rr_REV */ +/* Table19 */ + 0x73a, /* OR32rm */ + 0x73c, /* OR32rr_REV */ +/* Table21 */ + 0x746, /* OR8i8 */ +/* Table22 */ + 0x734, /* OR32i32 */ +/* Table23 */ + 0x8c7, /* PUSHCS32 */ +/* Table24 */ + 0xb8, /* ADC8mr */ + 0xbc, /* ADC8rr */ +/* Table26 */ + 0xa6, /* ADC32mr */ + 0xaa, /* ADC32rr */ +/* Table28 */ + 0xbb, /* ADC8rm */ + 0xbd, /* ADC8rr_REV */ +/* Table30 */ + 0xa9, /* ADC32rm */ + 0xab, /* ADC32rr_REV */ +/* Table32 */ + 0xb5, /* ADC8i8 */ +/* Table33 */ + 0xa3, /* ADC32i32 */ +/* Table34 */ + 0x8d6, /* PUSHSS32 */ +/* Table35 */ + 0x85b, /* POPSS32 */ +/* Table36 */ + 0x9ca, /* SBB8mr */ + 0x9ce, /* SBB8rr */ +/* Table38 */ + 0x9b8, /* SBB32mr */ + 0x9bc, /* SBB32rr */ +/* Table40 */ + 0x9cd, /* SBB8rm */ + 0x9cf, /* SBB8rr_REV */ +/* Table42 */ + 0x9bb, /* SBB32rm */ + 0x9bd, /* SBB32rr_REV */ +/* Table44 */ + 0x9c7, /* SBB8i8 */ +/* Table45 */ + 0x9b5, /* SBB32i32 */ +/* Table46 */ + 0x8c9, /* PUSHDS32 */ +/* Table47 */ + 0x84e, /* POPDS32 */ +/* Table48 */ + 0x139, /* AND8mr */ + 0x13d, /* AND8rr */ +/* Table50 */ + 0x127, /* AND32mr */ + 0x12b, /* AND32rr */ +/* Table52 */ + 0x13c, /* AND8rm */ + 0x13e, /* AND8rr_REV */ +/* Table54 */ + 0x12a, /* AND32rm */ + 0x12c, /* AND32rr_REV */ +/* Table56 */ + 0x136, /* AND8i8 */ +/* Table57 */ + 0x124, /* AND32i32 */ +/* Table58 */ + 0x327, /* DAA */ +/* Table59 */ + 0xabb, /* SUB8mr */ + 0xabf, /* SUB8rr */ +/* Table61 */ + 0xaa9, /* SUB32mr */ + 0xaad, /* SUB32rr */ +/* Table63 */ + 0xabe, /* SUB8rm */ + 0xac0, /* SUB8rr_REV */ +/* Table65 */ + 0xaac, /* SUB32rm */ + 0xaae, /* SUB32rr_REV */ +/* Table67 */ + 0xab8, /* SUB8i8 */ +/* Table68 */ + 0xaa6, /* SUB32i32 */ +/* Table69 */ + 0x328, /* DAS */ +/* Table70 */ + 0x3b99, /* XOR8mr */ + 0x3b9d, /* XOR8rr */ +/* Table72 */ + 0x3b87, /* XOR32mr */ + 0x3b8b, /* XOR32rr */ +/* Table74 */ + 0x3b9c, /* XOR8rm */ + 0x3b9e, /* XOR8rr_REV */ +/* Table76 */ + 0x3b8a, /* XOR32rm */ + 0x3b8c, /* XOR32rr_REV */ +/* Table78 */ + 0x3b96, /* XOR8i8 */ +/* Table79 */ + 0x3b84, /* XOR32i32 */ +/* Table80 */ + 0x92, /* AAA */ +/* Table81 */ + 0x2a1, /* CMP8mr */ + 0x2a5, /* CMP8rr */ +/* Table83 */ + 0x28f, /* CMP32mr */ + 0x293, /* CMP32rr */ +/* Table85 */ + 0x2a4, /* CMP8rm */ + 0x2a6, /* CMP8rr_REV */ +/* Table87 */ + 0x292, /* CMP32rm */ + 0x294, /* CMP32rr_REV */ +/* Table89 */ + 0x29e, /* CMP8i8 */ +/* Table90 */ + 0x28c, /* CMP32i32 */ +/* Table91 */ + 0x95, /* AAS */ +/* Table92 */ + 0x404, /* INC32r_alt */ +/* Table93 */ + 0x32f, /* DEC32r_alt */ +/* Table94 */ + 0x8bc, /* PUSH32r */ +/* Table95 */ + 0x83f, /* POP32r */ +/* Table96 */ + 0x8c5, /* PUSHA32 */ +/* Table97 */ + 0x846, /* POPA32 */ +/* Table98 */ + 0x19c, /* BOUNDS32rm */ + 0x0, /* */ +/* Table100 */ + 0x14b, /* ARPL16mr */ + 0x14c, /* ARPL16rr */ +/* Table102 */ + 0x329, /* DATA16_PREFIX */ +/* Table103 */ + 0x8d8, /* PUSHi32 */ +/* Table104 */ + 0x3ea, /* IMUL32rmi */ + 0x3ed, /* IMUL32rri */ +/* Table106 */ + 0x8bb, /* PUSH32i8 */ +/* Table107 */ + 0x3eb, /* IMUL32rmi8 */ + 0x3ee, /* IMUL32rri8 */ +/* Table109 */ + 0x40b, /* INSB */ +/* Table110 */ + 0x410, /* INSL */ +/* Table111 */ + 0x759, /* OUTSB */ +/* Table112 */ + 0x75a, /* OUTSL */ +/* Table113 */ + 0x475, /* JO_1 */ +/* Table114 */ + 0x46c, /* JNO_1 */ +/* Table115 */ + 0x446, /* JB_1 */ +/* Table116 */ + 0x43d, /* JAE_1 */ +/* Table117 */ + 0x44b, /* JE_1 */ +/* Table118 */ + 0x469, /* JNE_1 */ +/* Table119 */ + 0x443, /* JBE_1 */ +/* Table120 */ + 0x440, /* JA_1 */ +/* Table121 */ + 0x47c, /* JS_1 */ +/* Table122 */ + 0x472, /* JNS_1 */ +/* Table123 */ + 0x478, /* JP_1 */ +/* Table124 */ + 0x46f, /* JNP_1 */ +/* Table125 */ + 0x457, /* JL_1 */ +/* Table126 */ + 0x44e, /* JGE_1 */ +/* Table127 */ + 0x454, /* JLE_1 */ +/* Table128 */ + 0x451, /* JG_1 */ +/* Table129 */ + 0xde, /* ADD8mi */ + 0x747, /* OR8mi */ + 0xb6, /* ADC8mi */ + 0x9c8, /* SBB8mi */ + 0x137, /* AND8mi */ + 0xab9, /* SUB8mi */ + 0x3b97, /* XOR8mi */ + 0x29f, /* CMP8mi */ + 0xe1, /* ADD8ri */ + 0x74a, /* OR8ri */ + 0xb9, /* ADC8ri */ + 0x9cb, /* SBB8ri */ + 0x13a, /* AND8ri */ + 0xabc, /* SUB8ri */ + 0x3b9a, /* XOR8ri */ + 0x2a2, /* CMP8ri */ +/* Table145 */ + 0xcc, /* ADD32mi */ + 0x735, /* OR32mi */ + 0xa4, /* ADC32mi */ + 0x9b6, /* SBB32mi */ + 0x125, /* AND32mi */ + 0xaa7, /* SUB32mi */ + 0x3b85, /* XOR32mi */ + 0x28d, /* CMP32mi */ + 0xcf, /* ADD32ri */ + 0x738, /* OR32ri */ + 0xa7, /* ADC32ri */ + 0x9b9, /* SBB32ri */ + 0x128, /* AND32ri */ + 0xaaa, /* SUB32ri */ + 0x3b88, /* XOR32ri */ + 0x290, /* CMP32ri */ +/* Table161 */ + 0xdf, /* ADD8mi8 */ + 0x748, /* OR8mi8 */ + 0xb7, /* ADC8mi8 */ + 0x9c9, /* SBB8mi8 */ + 0x138, /* AND8mi8 */ + 0xaba, /* SUB8mi8 */ + 0x3b98, /* XOR8mi8 */ + 0x2a0, /* CMP8mi8 */ + 0xe2, /* ADD8ri8 */ + 0x74b, /* OR8ri8 */ + 0xba, /* ADC8ri8 */ + 0x9cc, /* SBB8ri8 */ + 0x13b, /* AND8ri8 */ + 0xabd, /* SUB8ri8 */ + 0x3b9b, /* XOR8ri8 */ + 0x2a3, /* CMP8ri8 */ +/* Table177 */ + 0xcd, /* ADD32mi8 */ + 0x736, /* OR32mi8 */ + 0xa5, /* ADC32mi8 */ + 0x9b7, /* SBB32mi8 */ + 0x126, /* AND32mi8 */ + 0xaa8, /* SUB32mi8 */ + 0x3b86, /* XOR32mi8 */ + 0x28e, /* CMP32mi8 */ + 0xd0, /* ADD32ri8 */ + 0x739, /* OR32ri8 */ + 0xa8, /* ADC32ri8 */ + 0x9ba, /* SBB32ri8 */ + 0x129, /* AND32ri8 */ + 0xaab, /* SUB32ri8 */ + 0x3b89, /* XOR32ri8 */ + 0x291, /* CMP32ri8 */ +/* Table193 */ + 0xb17, /* TEST8mr */ + 0xb1a, /* TEST8rr */ +/* Table195 */ + 0xb09, /* TEST32mr */ + 0xb0c, /* TEST32rr */ +/* Table197 */ + 0x3b70, /* XCHG8rm */ + 0x3b71, /* XCHG8rr */ +/* Table199 */ + 0x3b6b, /* XCHG32rm */ + 0x3b6c, /* XCHG32rr */ +/* Table201 */ + 0x648, /* MOV8mr */ + 0x651, /* MOV8rr */ +/* Table203 */ + 0x622, /* MOV32mr */ + 0x62b, /* MOV32rr */ +/* Table205 */ + 0x64f, /* MOV8rm */ + 0x653, /* MOV8rr_REV */ +/* Table207 */ + 0x62a, /* MOV32rm */ + 0x62c, /* MOV32rr_REV */ +/* Table209 */ + 0x610, /* MOV16ms */ + 0x62d, /* MOV32rs */ +/* Table211 */ + 0x4e0, /* LEA32r */ + 0x0, /* */ +/* Table213 */ + 0x61a, /* MOV16sm */ + 0x62e, /* MOV32sr */ +/* Table215 */ + 0x840, /* POP32rmm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x841, /* POP32rmr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table231 */ + 0x704, /* NOOP */ +/* Table232 */ + 0x3b6a, /* XCHG32ar */ +/* Table233 */ + 0x326, /* CWDE */ +/* Table234 */ + 0x1f0, /* CDQ */ +/* Table235 */ + 0x380, /* FARCALL32i */ +/* Table236 */ + 0x3b4e, /* WAIT */ +/* Table237 */ + 0x8cd, /* PUSHF32 */ +/* Table238 */ + 0x852, /* POPF32 */ +/* Table239 */ + 0x975, /* SAHF */ +/* Table240 */ + 0x4c2, /* LAHF */ +/* Table241 */ + 0x645, /* MOV8ao32 */ +/* Table242 */ + 0x61d, /* MOV32ao32 */ +/* Table243 */ + 0x64b, /* MOV8o32a */ +/* Table244 */ + 0x624, /* MOV32o32a */ +/* Table245 */ + 0x690, /* MOVSB */ +/* Table246 */ + 0x699, /* MOVSL */ +/* Table247 */ + 0x2af, /* CMPSB */ +/* Table248 */ + 0x2b6, /* CMPSL */ +/* Table249 */ + 0xb14, /* TEST8i8 */ +/* Table250 */ + 0xb06, /* TEST32i32 */ +/* Table251 */ + 0xa83, /* STOSB */ +/* Table252 */ + 0xa84, /* STOSL */ +/* Table253 */ + 0x4fb, /* LODSB */ +/* Table254 */ + 0x4fc, /* LODSL */ +/* Table255 */ + 0x9d0, /* SCASB */ +/* Table256 */ + 0x9d1, /* SCASL */ +/* Table257 */ + 0x64d, /* MOV8ri */ +/* Table258 */ + 0x628, /* MOV32ri */ +/* Table259 */ + 0x941, /* ROL8mi */ + 0x959, /* ROR8mi */ + 0x8ef, /* RCL8mi */ + 0x90d, /* RCR8mi */ + 0xa1b, /* SHL8mi */ + 0xa43, /* SHR8mi */ + 0x98a, /* SAL8mi */ + 0x9a3, /* SAR8mi */ + 0x944, /* ROL8ri */ + 0x95c, /* ROR8ri */ + 0x8f2, /* RCL8ri */ + 0x910, /* RCR8ri */ + 0xa1e, /* SHL8ri */ + 0xa46, /* SHR8ri */ + 0x98d, /* SAL8ri */ + 0x9a6, /* SAR8ri */ +/* Table275 */ + 0x935, /* ROL32mi */ + 0x94d, /* ROR32mi */ + 0x8e3, /* RCL32mi */ + 0x901, /* RCR32mi */ + 0xa0f, /* SHL32mi */ + 0xa37, /* SHR32mi */ + 0x97e, /* SAL32mi */ + 0x997, /* SAR32mi */ + 0x938, /* ROL32ri */ + 0x950, /* ROR32ri */ + 0x8e6, /* RCL32ri */ + 0x904, /* RCR32ri */ + 0xa12, /* SHL32ri */ + 0xa3a, /* SHR32ri */ + 0x981, /* SAL32ri */ + 0x99a, /* SAR32ri */ +/* Table291 */ + 0x926, /* RETIL */ +/* Table292 */ + 0x929, /* RETL */ +/* Table293 */ + 0x4e6, /* LES32rm */ + 0x0, /* */ +/* Table295 */ + 0x4cc, /* LDS32rm */ + 0x0, /* */ +/* Table297 */ + 0x647, /* MOV8mi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x64e, /* MOV8ri_alt */ + 0x64e, /* MOV8ri_alt */ + 0x64e, /* MOV8ri_alt */ + 0x64e, /* MOV8ri_alt */ + 0x64e, /* MOV8ri_alt */ + 0x64e, /* MOV8ri_alt */ + 0x64e, /* MOV8ri_alt */ + 0x64e, /* MOV8ri_alt */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3b5b, /* XABORT */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table369 */ + 0x621, /* MOV32mi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x629, /* MOV32ri_alt */ + 0x629, /* MOV32ri_alt */ + 0x629, /* MOV32ri_alt */ + 0x629, /* MOV32ri_alt */ + 0x629, /* MOV32ri_alt */ + 0x629, /* MOV32ri_alt */ + 0x629, /* MOV32ri_alt */ + 0x629, /* MOV32ri_alt */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3b66, /* XBEGIN_4 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table441 */ + 0x378, /* ENTER */ +/* Table442 */ + 0x4e3, /* LEAVE */ +/* Table443 */ + 0x502, /* LRETIL */ +/* Table444 */ + 0x505, /* LRETL */ +/* Table445 */ + 0x414, /* INT3 */ +/* Table446 */ + 0x412, /* INT */ +/* Table447 */ + 0x415, /* INTO */ +/* Table448 */ + 0x421, /* IRET32 */ +/* Table449 */ + 0x93f, /* ROL8m1 */ + 0x957, /* ROR8m1 */ + 0x8ed, /* RCL8m1 */ + 0x90b, /* RCR8m1 */ + 0xa19, /* SHL8m1 */ + 0xa41, /* SHR8m1 */ + 0x988, /* SAL8m1 */ + 0x9a1, /* SAR8m1 */ + 0x942, /* ROL8r1 */ + 0x95a, /* ROR8r1 */ + 0x8f0, /* RCL8r1 */ + 0x90e, /* RCR8r1 */ + 0xa1c, /* SHL8r1 */ + 0xa44, /* SHR8r1 */ + 0x98b, /* SAL8r1 */ + 0x9a4, /* SAR8r1 */ +/* Table465 */ + 0x933, /* ROL32m1 */ + 0x94b, /* ROR32m1 */ + 0x8e1, /* RCL32m1 */ + 0x8ff, /* RCR32m1 */ + 0xa0d, /* SHL32m1 */ + 0xa35, /* SHR32m1 */ + 0x97c, /* SAL32m1 */ + 0x995, /* SAR32m1 */ + 0x936, /* ROL32r1 */ + 0x94e, /* ROR32r1 */ + 0x8e4, /* RCL32r1 */ + 0x902, /* RCR32r1 */ + 0xa10, /* SHL32r1 */ + 0xa38, /* SHR32r1 */ + 0x97f, /* SAL32r1 */ + 0x998, /* SAR32r1 */ +/* Table481 */ + 0x940, /* ROL8mCL */ + 0x958, /* ROR8mCL */ + 0x8ee, /* RCL8mCL */ + 0x90c, /* RCR8mCL */ + 0xa1a, /* SHL8mCL */ + 0xa42, /* SHR8mCL */ + 0x989, /* SAL8mCL */ + 0x9a2, /* SAR8mCL */ + 0x943, /* ROL8rCL */ + 0x95b, /* ROR8rCL */ + 0x8f1, /* RCL8rCL */ + 0x90f, /* RCR8rCL */ + 0xa1d, /* SHL8rCL */ + 0xa45, /* SHR8rCL */ + 0x98c, /* SAL8rCL */ + 0x9a5, /* SAR8rCL */ +/* Table497 */ + 0x934, /* ROL32mCL */ + 0x94c, /* ROR32mCL */ + 0x8e2, /* RCL32mCL */ + 0x900, /* RCR32mCL */ + 0xa0e, /* SHL32mCL */ + 0xa36, /* SHR32mCL */ + 0x97d, /* SAL32mCL */ + 0x996, /* SAR32mCL */ + 0x937, /* ROL32rCL */ + 0x94f, /* ROR32rCL */ + 0x8e5, /* RCL32rCL */ + 0x903, /* RCR32rCL */ + 0xa11, /* SHL32rCL */ + 0xa39, /* SHR32rCL */ + 0x980, /* SAL32rCL */ + 0x999, /* SAR32rCL */ +/* Table513 */ + 0x94, /* AAM8i8 */ +/* Table514 */ + 0x93, /* AAD8i8 */ +/* Table515 */ + 0x98e, /* SALC */ +/* Table516 */ + 0x3b7a, /* XLAT */ +/* Table517 */ + 0xf6, /* ADD_F32m */ + 0x6e5, /* MUL_F32m */ + 0x38a, /* FCOM32m */ + 0x38c, /* FCOMP32m */ + 0xadf, /* SUB_F32m */ + 0xac5, /* SUBR_F32m */ + 0x35a, /* DIV_F32m */ + 0x340, /* DIVR_F32m */ + 0xfb, /* ADD_FST0r */ + 0x6ea, /* MUL_FST0r */ + 0x2d4, /* COM_FST0r */ + 0x2d1, /* COMP_FST0r */ + 0xae4, /* SUB_FST0r */ + 0xaca, /* SUBR_FST0r */ + 0x35f, /* DIV_FST0r */ + 0x345, /* DIVR_FST0r */ +/* Table533 */ + 0x4cf, /* LD_F32m */ + 0x0, /* */ + 0xa8b, /* ST_F32m */ + 0xa8d, /* ST_FP32m */ + 0x39b, /* FLDENVm */ + 0x39a, /* FLDCW16m */ + 0x3b2, /* FSTENVm */ + 0x3a4, /* FNSTCW16m */ + 0x4de, /* LD_Frr */ + 0x4de, /* LD_Frr */ + 0x4de, /* LD_Frr */ + 0x4de, /* LD_Frr */ + 0x4de, /* LD_Frr */ + 0x4de, /* LD_Frr */ + 0x4de, /* LD_Frr */ + 0x4de, /* LD_Frr */ + 0x3b72, /* XCH_F */ + 0x3b72, /* XCH_F */ + 0x3b72, /* XCH_F */ + 0x3b72, /* XCH_F */ + 0x3b72, /* XCH_F */ + 0x3b72, /* XCH_F */ + 0x3b72, /* XCH_F */ + 0x3b72, /* XCH_F */ + 0x3a3, /* FNOP */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3a8, /* FPNCEST0r */ + 0x3a8, /* FPNCEST0r */ + 0x3a8, /* FPNCEST0r */ + 0x3a8, /* FPNCEST0r */ + 0x3a8, /* FPNCEST0r */ + 0x3a8, /* FPNCEST0r */ + 0x3a8, /* FPNCEST0r */ + 0x3a8, /* FPNCEST0r */ + 0x1f2, /* CHS_F */ + 0x96, /* ABS_F */ + 0x0, /* */ + 0x0, /* */ + 0xb1c, /* TST_F */ + 0x3b3, /* FXAM */ + 0x0, /* */ + 0x0, /* */ + 0x4ce, /* LD_F1 */ + 0x39d, /* FLDL2T */ + 0x39c, /* FLDL2E */ + 0x3a0, /* FLDPI */ + 0x39e, /* FLDLG2 */ + 0x39f, /* FLDLN2 */ + 0x4cd, /* LD_F0 */ + 0x0, /* */ + 0x37d, /* F2XM1 */ + 0x3b9, /* FYL2X */ + 0x3ab, /* FPTAN */ + 0x3a7, /* FPATAN */ + 0x3b8, /* FXTRACT */ + 0x3aa, /* FPREM1 */ + 0x38f, /* FDECSTP */ + 0x399, /* FINCSTP */ + 0x3a9, /* FPREM */ + 0x3ba, /* FYL2XP1 */ + 0xa79, /* SQRT_F */ + 0x3b1, /* FSINCOS */ + 0x3ac, /* FRNDINT */ + 0x3af, /* FSCALE */ + 0xa5e, /* SIN_F */ + 0x2d5, /* COS_F */ +/* Table605 */ + 0xf9, /* ADD_FI32m */ + 0x6e8, /* MUL_FI32m */ + 0x396, /* FICOM32m */ + 0x398, /* FICOMP32m */ + 0xae2, /* SUB_FI32m */ + 0xac8, /* SUBR_FI32m */ + 0x35d, /* DIV_FI32m */ + 0x343, /* DIVR_FI32m */ + 0x21f, /* CMOVB_F */ + 0x21f, /* CMOVB_F */ + 0x21f, /* CMOVB_F */ + 0x21f, /* CMOVB_F */ + 0x21f, /* CMOVB_F */ + 0x21f, /* CMOVB_F */ + 0x21f, /* CMOVB_F */ + 0x21f, /* CMOVB_F */ + 0x229, /* CMOVE_F */ + 0x229, /* CMOVE_F */ + 0x229, /* CMOVE_F */ + 0x229, /* CMOVE_F */ + 0x229, /* CMOVE_F */ + 0x229, /* CMOVE_F */ + 0x229, /* CMOVE_F */ + 0x229, /* CMOVE_F */ + 0x21b, /* CMOVBE_F */ + 0x21b, /* CMOVBE_F */ + 0x21b, /* CMOVBE_F */ + 0x21b, /* CMOVBE_F */ + 0x21b, /* CMOVBE_F */ + 0x21b, /* CMOVBE_F */ + 0x21b, /* CMOVBE_F */ + 0x21b, /* CMOVBE_F */ + 0x279, /* CMOVP_F */ + 0x279, /* CMOVP_F */ + 0x279, /* CMOVP_F */ + 0x279, /* CMOVP_F */ + 0x279, /* CMOVP_F */ + 0x279, /* CMOVP_F */ + 0x279, /* CMOVP_F */ + 0x279, /* CMOVP_F */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0xb34, /* UCOM_FPPr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table677 */ + 0x3d4, /* ILD_F32m */ + 0x424, /* ISTT_FP32m */ + 0x430, /* IST_F32m */ + 0x432, /* IST_FP32m */ + 0x0, /* */ + 0x4d1, /* LD_F80m */ + 0x0, /* */ + 0xa8f, /* ST_FP80m */ + 0x249, /* CMOVNB_F */ + 0x249, /* CMOVNB_F */ + 0x249, /* CMOVNB_F */ + 0x249, /* CMOVNB_F */ + 0x249, /* CMOVNB_F */ + 0x249, /* CMOVNB_F */ + 0x249, /* CMOVNB_F */ + 0x249, /* CMOVNB_F */ + 0x253, /* CMOVNE_F */ + 0x253, /* CMOVNE_F */ + 0x253, /* CMOVNE_F */ + 0x253, /* CMOVNE_F */ + 0x253, /* CMOVNE_F */ + 0x253, /* CMOVNE_F */ + 0x253, /* CMOVNE_F */ + 0x253, /* CMOVNE_F */ + 0x245, /* CMOVNBE_F */ + 0x245, /* CMOVNBE_F */ + 0x245, /* CMOVNBE_F */ + 0x245, /* CMOVNBE_F */ + 0x245, /* CMOVNBE_F */ + 0x245, /* CMOVNBE_F */ + 0x245, /* CMOVNBE_F */ + 0x245, /* CMOVNBE_F */ + 0x263, /* CMOVNP_F */ + 0x263, /* CMOVNP_F */ + 0x263, /* CMOVNP_F */ + 0x263, /* CMOVNP_F */ + 0x263, /* CMOVNP_F */ + 0x263, /* CMOVNP_F */ + 0x263, /* CMOVNP_F */ + 0x263, /* CMOVNP_F */ + 0x392, /* FENI8087_NOP */ + 0x390, /* FDISI8087_NOP */ + 0x3a1, /* FNCLEX */ + 0x3a2, /* FNINIT */ + 0x3b0, /* FSETPM */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0xb33, /* UCOM_FIr */ + 0xb33, /* UCOM_FIr */ + 0xb33, /* UCOM_FIr */ + 0xb33, /* UCOM_FIr */ + 0xb33, /* UCOM_FIr */ + 0xb33, /* UCOM_FIr */ + 0xb33, /* UCOM_FIr */ + 0xb33, /* UCOM_FIr */ + 0x2d3, /* COM_FIr */ + 0x2d3, /* COM_FIr */ + 0x2d3, /* COM_FIr */ + 0x2d3, /* COM_FIr */ + 0x2d3, /* COM_FIr */ + 0x2d3, /* COM_FIr */ + 0x2d3, /* COM_FIr */ + 0x2d3, /* COM_FIr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table749 */ + 0xf7, /* ADD_F64m */ + 0x6e6, /* MUL_F64m */ + 0x38b, /* FCOM64m */ + 0x38d, /* FCOMP64m */ + 0xae0, /* SUB_F64m */ + 0xac6, /* SUBR_F64m */ + 0x35b, /* DIV_F64m */ + 0x341, /* DIVR_F64m */ + 0x10a, /* ADD_FrST0 */ + 0x6f9, /* MUL_FrST0 */ + 0x0, /* */ + 0x0, /* */ + 0xad6, /* SUBR_FrST0 */ + 0xaf3, /* SUB_FrST0 */ + 0x351, /* DIVR_FrST0 */ + 0x36e, /* DIV_FrST0 */ +/* Table765 */ + 0x4d0, /* LD_F64m */ + 0x425, /* ISTT_FP64m */ + 0xa8c, /* ST_F64m */ + 0xa8e, /* ST_FP64m */ + 0x3ad, /* FRSTORm */ + 0x0, /* */ + 0x3ae, /* FSAVEm */ + 0x3a6, /* FNSTSWm */ + 0x393, /* FFREE */ + 0x0, /* */ + 0xa9c, /* ST_Frr */ + 0xa90, /* ST_FPrr */ + 0xb3c, /* UCOM_Fr */ + 0xb35, /* UCOM_FPr */ + 0x0, /* */ + 0x0, /* */ +/* Table781 */ + 0xf8, /* ADD_FI16m */ + 0x6e7, /* MUL_FI16m */ + 0x395, /* FICOM16m */ + 0x397, /* FICOMP16m */ + 0xae1, /* SUB_FI16m */ + 0xac7, /* SUBR_FI16m */ + 0x35c, /* DIV_FI16m */ + 0x342, /* DIVR_FI16m */ + 0xfa, /* ADD_FPrST0 */ + 0xfa, /* ADD_FPrST0 */ + 0xfa, /* ADD_FPrST0 */ + 0xfa, /* ADD_FPrST0 */ + 0xfa, /* ADD_FPrST0 */ + 0xfa, /* ADD_FPrST0 */ + 0xfa, /* ADD_FPrST0 */ + 0xfa, /* ADD_FPrST0 */ + 0x6e9, /* MUL_FPrST0 */ + 0x6e9, /* MUL_FPrST0 */ + 0x6e9, /* MUL_FPrST0 */ + 0x6e9, /* MUL_FPrST0 */ + 0x6e9, /* MUL_FPrST0 */ + 0x6e9, /* MUL_FPrST0 */ + 0x6e9, /* MUL_FPrST0 */ + 0x6e9, /* MUL_FPrST0 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x38e, /* FCOMPP */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0xac9, /* SUBR_FPrST0 */ + 0xac9, /* SUBR_FPrST0 */ + 0xac9, /* SUBR_FPrST0 */ + 0xac9, /* SUBR_FPrST0 */ + 0xac9, /* SUBR_FPrST0 */ + 0xac9, /* SUBR_FPrST0 */ + 0xac9, /* SUBR_FPrST0 */ + 0xac9, /* SUBR_FPrST0 */ + 0xae3, /* SUB_FPrST0 */ + 0xae3, /* SUB_FPrST0 */ + 0xae3, /* SUB_FPrST0 */ + 0xae3, /* SUB_FPrST0 */ + 0xae3, /* SUB_FPrST0 */ + 0xae3, /* SUB_FPrST0 */ + 0xae3, /* SUB_FPrST0 */ + 0xae3, /* SUB_FPrST0 */ + 0x344, /* DIVR_FPrST0 */ + 0x344, /* DIVR_FPrST0 */ + 0x344, /* DIVR_FPrST0 */ + 0x344, /* DIVR_FPrST0 */ + 0x344, /* DIVR_FPrST0 */ + 0x344, /* DIVR_FPrST0 */ + 0x344, /* DIVR_FPrST0 */ + 0x344, /* DIVR_FPrST0 */ + 0x35e, /* DIV_FPrST0 */ + 0x35e, /* DIV_FPrST0 */ + 0x35e, /* DIV_FPrST0 */ + 0x35e, /* DIV_FPrST0 */ + 0x35e, /* DIV_FPrST0 */ + 0x35e, /* DIV_FPrST0 */ + 0x35e, /* DIV_FPrST0 */ + 0x35e, /* DIV_FPrST0 */ +/* Table853 */ + 0x3d3, /* ILD_F16m */ + 0x423, /* ISTT_FP16m */ + 0x42f, /* IST_F16m */ + 0x431, /* IST_FP16m */ + 0x388, /* FBLDm */ + 0x3d5, /* ILD_F64m */ + 0x389, /* FBSTPm */ + 0x433, /* IST_FP64m */ + 0x394, /* FFREEP */ + 0x394, /* FFREEP */ + 0x394, /* FFREEP */ + 0x394, /* FFREEP */ + 0x394, /* FFREEP */ + 0x394, /* FFREEP */ + 0x394, /* FFREEP */ + 0x394, /* FFREEP */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3a5, /* FNSTSW16r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0xb32, /* UCOM_FIPr */ + 0xb32, /* UCOM_FIPr */ + 0xb32, /* UCOM_FIPr */ + 0xb32, /* UCOM_FIPr */ + 0xb32, /* UCOM_FIPr */ + 0xb32, /* UCOM_FIPr */ + 0xb32, /* UCOM_FIPr */ + 0xb32, /* UCOM_FIPr */ + 0x2d2, /* COM_FIPr */ + 0x2d2, /* COM_FIPr */ + 0x2d2, /* COM_FIPr */ + 0x2d2, /* COM_FIPr */ + 0x2d2, /* COM_FIPr */ + 0x2d2, /* COM_FIPr */ + 0x2d2, /* COM_FIPr */ + 0x2d2, /* COM_FIPr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table925 */ + 0x501, /* LOOPNE */ +/* Table926 */ + 0x500, /* LOOPE */ +/* Table927 */ + 0x4ff, /* LOOP */ +/* Table928 */ + 0x44a, /* JECXZ */ +/* Table929 */ + 0x3fd, /* IN8ri */ +/* Table930 */ + 0x3fb, /* IN32ri */ +/* Table931 */ + 0x757, /* OUT8ir */ +/* Table932 */ + 0x755, /* OUT32ir */ +/* Table933 */ + 0x1ee, /* CALLpcrel32 */ +/* Table934 */ + 0x468, /* JMP_4 */ +/* Table935 */ + 0x385, /* FARJMP32i */ +/* Table936 */ + 0x466, /* JMP_1 */ +/* Table937 */ + 0x3fe, /* IN8rr */ +/* Table938 */ + 0x3fc, /* IN32rr */ +/* Table939 */ + 0x758, /* OUT8rr */ +/* Table940 */ + 0x756, /* OUT32rr */ +/* Table941 */ + 0x4fa, /* LOCK_PREFIX */ +/* Table942 */ + 0x413, /* INT1 */ +/* Table943 */ + 0x924, /* REPNE_PREFIX */ +/* Table944 */ + 0x925, /* REP_PREFIX */ +/* Table945 */ + 0x3c6, /* HLT */ +/* Table946 */ + 0x202, /* CMC */ +/* Table947 */ + 0xb15, /* TEST8mi */ + 0xb16, /* TEST8mi_alt */ + 0x729, /* NOT8m */ + 0x702, /* NEG8m */ + 0x6d3, /* MUL8m */ + 0x3f7, /* IMUL8m */ + 0x33a, /* DIV8m */ + 0x3d1, /* IDIV8m */ + 0xb18, /* TEST8ri */ + 0xb19, /* TEST8ri_alt */ + 0x72a, /* NOT8r */ + 0x703, /* NEG8r */ + 0x6d4, /* MUL8r */ + 0x3f8, /* IMUL8r */ + 0x33b, /* DIV8r */ + 0x3d2, /* IDIV8r */ +/* Table963 */ + 0xb07, /* TEST32mi */ + 0xb08, /* TEST32mi_alt */ + 0x725, /* NOT32m */ + 0x6fe, /* NEG32m */ + 0x6cf, /* MUL32m */ + 0x3e7, /* IMUL32m */ + 0x336, /* DIV32m */ + 0x3cd, /* IDIV32m */ + 0xb0a, /* TEST32ri */ + 0xb0b, /* TEST32ri_alt */ + 0x726, /* NOT32r */ + 0x6ff, /* NEG32r */ + 0x6d0, /* MUL32r */ + 0x3e8, /* IMUL32r */ + 0x337, /* DIV32r */ + 0x3ce, /* IDIV32r */ +/* Table979 */ + 0x1f7, /* CLC */ +/* Table980 */ + 0xa7e, /* STC */ +/* Table981 */ + 0x1fd, /* CLI */ +/* Table982 */ + 0xa81, /* STI */ +/* Table983 */ + 0x1f8, /* CLD */ +/* Table984 */ + 0xa7f, /* STD */ +/* Table985 */ + 0x407, /* INC8m */ + 0x332, /* DEC8m */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x408, /* INC8r */ + 0x333, /* DEC8r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1001 */ + 0x402, /* INC32m */ + 0x32d, /* DEC32m */ + 0x1e4, /* CALL32m */ + 0x381, /* FARCALL32m */ + 0x45e, /* JMP32m */ + 0x386, /* FARJMP32m */ + 0x8bd, /* PUSH32rmm */ + 0x0, /* */ + 0x403, /* INC32r */ + 0x32e, /* DEC32r */ + 0x1e6, /* CALL32r */ + 0x0, /* */ + 0x460, /* JMP32r */ + 0x0, /* */ + 0x8be, /* PUSH32rmr */ + 0x0, /* */ +/* Table1017 */ + 0x92c, /* REX64_PREFIX */ +/* Table1018 */ + 0x8c1, /* PUSH64r */ +/* Table1019 */ + 0x842, /* POP64r */ +/* Table1020 */ + 0x8bf, /* PUSH64i32 */ +/* Table1021 */ + 0x8c0, /* PUSH64i8 */ +/* Table1022 */ + 0x4e1, /* LEA64_32r */ + 0x0, /* */ +/* Table1024 */ + 0x843, /* POP64rmm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x844, /* POP64rmr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1040 */ + 0x8ce, /* PUSHF64 */ +/* Table1041 */ + 0x853, /* POPF64 */ +/* Table1042 */ + 0x646, /* MOV8ao64 */ +/* Table1043 */ + 0x61e, /* MOV32ao64 */ +/* Table1044 */ + 0x64c, /* MOV8o64a */ +/* Table1045 */ + 0x625, /* MOV32o64a */ +/* Table1046 */ + 0x927, /* RETIQ */ +/* Table1047 */ + 0x92a, /* RETQ */ +/* Table1048 */ + 0x4e4, /* LEAVE64 */ +/* Table1049 */ + 0x47b, /* JRCXZ */ +/* Table1050 */ + 0x1ea, /* CALL64pcrel32 */ +/* Table1051 */ + 0x402, /* INC32m */ + 0x32d, /* DEC32m */ + 0x1e8, /* CALL64m */ + 0x381, /* FARCALL32m */ + 0x462, /* JMP64m */ + 0x386, /* FARJMP32m */ + 0x8c2, /* PUSH64rmm */ + 0x0, /* */ + 0x403, /* INC32r */ + 0x32e, /* DEC32r */ + 0x1eb, /* CALL64r */ + 0x0, /* */ + 0x464, /* JMP64r */ + 0x0, /* */ + 0x8c3, /* PUSH64rmr */ + 0x0, /* */ +/* Table1067 */ + 0xc5, /* ADD16mr */ + 0xc9, /* ADD16rr */ +/* Table1069 */ + 0xc8, /* ADD16rm */ + 0xca, /* ADD16rr_REV */ +/* Table1071 */ + 0xc2, /* ADD16i16 */ +/* Table1072 */ + 0x8ca, /* PUSHES16 */ +/* Table1073 */ + 0x84f, /* POPES16 */ +/* Table1074 */ + 0x72e, /* OR16mr */ + 0x732, /* OR16rr */ +/* Table1076 */ + 0x731, /* OR16rm */ + 0x733, /* OR16rr_REV */ +/* Table1078 */ + 0x72b, /* OR16i16 */ +/* Table1079 */ + 0x8c6, /* PUSHCS16 */ +/* Table1080 */ + 0x9d, /* ADC16mr */ + 0xa1, /* ADC16rr */ +/* Table1082 */ + 0xa0, /* ADC16rm */ + 0xa2, /* ADC16rr_REV */ +/* Table1084 */ + 0x9a, /* ADC16i16 */ +/* Table1085 */ + 0x8d5, /* PUSHSS16 */ +/* Table1086 */ + 0x85a, /* POPSS16 */ +/* Table1087 */ + 0x9af, /* SBB16mr */ + 0x9b3, /* SBB16rr */ +/* Table1089 */ + 0x9b2, /* SBB16rm */ + 0x9b4, /* SBB16rr_REV */ +/* Table1091 */ + 0x9ac, /* SBB16i16 */ +/* Table1092 */ + 0x8c8, /* PUSHDS16 */ +/* Table1093 */ + 0x84d, /* POPDS16 */ +/* Table1094 */ + 0x11e, /* AND16mr */ + 0x122, /* AND16rr */ +/* Table1096 */ + 0x121, /* AND16rm */ + 0x123, /* AND16rr_REV */ +/* Table1098 */ + 0x11b, /* AND16i16 */ +/* Table1099 */ + 0xaa0, /* SUB16mr */ + 0xaa4, /* SUB16rr */ +/* Table1101 */ + 0xaa3, /* SUB16rm */ + 0xaa5, /* SUB16rr_REV */ +/* Table1103 */ + 0xa9d, /* SUB16i16 */ +/* Table1104 */ + 0x3b7e, /* XOR16mr */ + 0x3b82, /* XOR16rr */ +/* Table1106 */ + 0x3b81, /* XOR16rm */ + 0x3b83, /* XOR16rr_REV */ +/* Table1108 */ + 0x3b7b, /* XOR16i16 */ +/* Table1109 */ + 0x286, /* CMP16mr */ + 0x28a, /* CMP16rr */ +/* Table1111 */ + 0x289, /* CMP16rm */ + 0x28b, /* CMP16rr_REV */ +/* Table1113 */ + 0x283, /* CMP16i16 */ +/* Table1114 */ + 0x401, /* INC16r_alt */ +/* Table1115 */ + 0x32c, /* DEC16r_alt */ +/* Table1116 */ + 0x8b8, /* PUSH16r */ +/* Table1117 */ + 0x83c, /* POP16r */ +/* Table1118 */ + 0x8c4, /* PUSHA16 */ +/* Table1119 */ + 0x845, /* POPA16 */ +/* Table1120 */ + 0x19b, /* BOUNDS16rm */ + 0x0, /* */ +/* Table1122 */ + 0x8d7, /* PUSHi16 */ +/* Table1123 */ + 0x3e2, /* IMUL16rmi */ + 0x3e5, /* IMUL16rri */ +/* Table1125 */ + 0x8b7, /* PUSH16i8 */ +/* Table1126 */ + 0x3e3, /* IMUL16rmi8 */ + 0x3e6, /* IMUL16rri8 */ +/* Table1128 */ + 0x411, /* INSW */ +/* Table1129 */ + 0x75b, /* OUTSW */ +/* Table1130 */ + 0xc3, /* ADD16mi */ + 0x72c, /* OR16mi */ + 0x9b, /* ADC16mi */ + 0x9ad, /* SBB16mi */ + 0x11c, /* AND16mi */ + 0xa9e, /* SUB16mi */ + 0x3b7c, /* XOR16mi */ + 0x284, /* CMP16mi */ + 0xc6, /* ADD16ri */ + 0x72f, /* OR16ri */ + 0x9e, /* ADC16ri */ + 0x9b0, /* SBB16ri */ + 0x11f, /* AND16ri */ + 0xaa1, /* SUB16ri */ + 0x3b7f, /* XOR16ri */ + 0x287, /* CMP16ri */ +/* Table1146 */ + 0xc4, /* ADD16mi8 */ + 0x72d, /* OR16mi8 */ + 0x9c, /* ADC16mi8 */ + 0x9ae, /* SBB16mi8 */ + 0x11d, /* AND16mi8 */ + 0xa9f, /* SUB16mi8 */ + 0x3b7d, /* XOR16mi8 */ + 0x285, /* CMP16mi8 */ + 0xc7, /* ADD16ri8 */ + 0x730, /* OR16ri8 */ + 0x9f, /* ADC16ri8 */ + 0x9b1, /* SBB16ri8 */ + 0x120, /* AND16ri8 */ + 0xaa2, /* SUB16ri8 */ + 0x3b80, /* XOR16ri8 */ + 0x288, /* CMP16ri8 */ +/* Table1162 */ + 0xb02, /* TEST16mr */ + 0xb05, /* TEST16rr */ +/* Table1164 */ + 0x3b68, /* XCHG16rm */ + 0x3b69, /* XCHG16rr */ +/* Table1166 */ + 0x60f, /* MOV16mr */ + 0x617, /* MOV16rr */ +/* Table1168 */ + 0x616, /* MOV16rm */ + 0x618, /* MOV16rr_REV */ +/* Table1170 */ + 0x610, /* MOV16ms */ + 0x619, /* MOV16rs */ +/* Table1172 */ + 0x4df, /* LEA16r */ + 0x0, /* */ +/* Table1174 */ + 0x61a, /* MOV16sm */ + 0x61b, /* MOV16sr */ +/* Table1176 */ + 0x83d, /* POP16rmm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x83e, /* POP16rmr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1192 */ + 0x3b67, /* XCHG16ar */ +/* Table1193 */ + 0x1ef, /* CBW */ +/* Table1194 */ + 0x325, /* CWD */ +/* Table1195 */ + 0x37e, /* FARCALL16i */ +/* Table1196 */ + 0x8cc, /* PUSHF16 */ +/* Table1197 */ + 0x851, /* POPF16 */ +/* Table1198 */ + 0x60c, /* MOV16ao32 */ +/* Table1199 */ + 0x612, /* MOV16o32a */ +/* Table1200 */ + 0x6a3, /* MOVSW */ +/* Table1201 */ + 0x2be, /* CMPSW */ +/* Table1202 */ + 0xaff, /* TEST16i16 */ +/* Table1203 */ + 0xa86, /* STOSW */ +/* Table1204 */ + 0x4fe, /* LODSW */ +/* Table1205 */ + 0x9d3, /* SCASW */ +/* Table1206 */ + 0x614, /* MOV16ri */ +/* Table1207 */ + 0x92f, /* ROL16mi */ + 0x947, /* ROR16mi */ + 0x8dd, /* RCL16mi */ + 0x8fb, /* RCR16mi */ + 0xa09, /* SHL16mi */ + 0xa31, /* SHR16mi */ + 0x978, /* SAL16mi */ + 0x991, /* SAR16mi */ + 0x932, /* ROL16ri */ + 0x94a, /* ROR16ri */ + 0x8e0, /* RCL16ri */ + 0x8fe, /* RCR16ri */ + 0xa0c, /* SHL16ri */ + 0xa34, /* SHR16ri */ + 0x97b, /* SAL16ri */ + 0x994, /* SAR16ri */ +/* Table1223 */ + 0x928, /* RETIW */ +/* Table1224 */ + 0x92b, /* RETW */ +/* Table1225 */ + 0x4e5, /* LES16rm */ + 0x0, /* */ +/* Table1227 */ + 0x4cb, /* LDS16rm */ + 0x0, /* */ +/* Table1229 */ + 0x60e, /* MOV16mi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x615, /* MOV16ri_alt */ + 0x615, /* MOV16ri_alt */ + 0x615, /* MOV16ri_alt */ + 0x615, /* MOV16ri_alt */ + 0x615, /* MOV16ri_alt */ + 0x615, /* MOV16ri_alt */ + 0x615, /* MOV16ri_alt */ + 0x615, /* MOV16ri_alt */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3b65, /* XBEGIN_2 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1301 */ + 0x504, /* LRETIW */ +/* Table1302 */ + 0x507, /* LRETW */ +/* Table1303 */ + 0x420, /* IRET16 */ +/* Table1304 */ + 0x92d, /* ROL16m1 */ + 0x945, /* ROR16m1 */ + 0x8db, /* RCL16m1 */ + 0x8f9, /* RCR16m1 */ + 0xa07, /* SHL16m1 */ + 0xa2f, /* SHR16m1 */ + 0x976, /* SAL16m1 */ + 0x98f, /* SAR16m1 */ + 0x930, /* ROL16r1 */ + 0x948, /* ROR16r1 */ + 0x8de, /* RCL16r1 */ + 0x8fc, /* RCR16r1 */ + 0xa0a, /* SHL16r1 */ + 0xa32, /* SHR16r1 */ + 0x979, /* SAL16r1 */ + 0x992, /* SAR16r1 */ +/* Table1320 */ + 0x92e, /* ROL16mCL */ + 0x946, /* ROR16mCL */ + 0x8dc, /* RCL16mCL */ + 0x8fa, /* RCR16mCL */ + 0xa08, /* SHL16mCL */ + 0xa30, /* SHR16mCL */ + 0x977, /* SAL16mCL */ + 0x990, /* SAR16mCL */ + 0x931, /* ROL16rCL */ + 0x949, /* ROR16rCL */ + 0x8df, /* RCL16rCL */ + 0x8fd, /* RCR16rCL */ + 0xa0b, /* SHL16rCL */ + 0xa33, /* SHR16rCL */ + 0x97a, /* SAL16rCL */ + 0x993, /* SAR16rCL */ +/* Table1336 */ + 0x3f9, /* IN16ri */ +/* Table1337 */ + 0x753, /* OUT16ir */ +/* Table1338 */ + 0x1ed, /* CALLpcrel16 */ +/* Table1339 */ + 0x467, /* JMP_2 */ +/* Table1340 */ + 0x383, /* FARJMP16i */ +/* Table1341 */ + 0x3fa, /* IN16rr */ +/* Table1342 */ + 0x754, /* OUT16rr */ +/* Table1343 */ + 0xb00, /* TEST16mi */ + 0xb01, /* TEST16mi_alt */ + 0x723, /* NOT16m */ + 0x6fc, /* NEG16m */ + 0x6cd, /* MUL16m */ + 0x3df, /* IMUL16m */ + 0x334, /* DIV16m */ + 0x3cb, /* IDIV16m */ + 0xb03, /* TEST16ri */ + 0xb04, /* TEST16ri_alt */ + 0x724, /* NOT16r */ + 0x6fd, /* NEG16r */ + 0x6ce, /* MUL16r */ + 0x3e0, /* IMUL16r */ + 0x335, /* DIV16r */ + 0x3cc, /* IDIV16r */ +/* Table1359 */ + 0x3ff, /* INC16m */ + 0x32a, /* DEC16m */ + 0x1e0, /* CALL16m */ + 0x37f, /* FARCALL16m */ + 0x45a, /* JMP16m */ + 0x384, /* FARJMP16m */ + 0x8b9, /* PUSH16rmm */ + 0x0, /* */ + 0x400, /* INC16r */ + 0x32b, /* DEC16r */ + 0x1e2, /* CALL16r */ + 0x0, /* */ + 0x45c, /* JMP16r */ + 0x0, /* */ + 0x8ba, /* PUSH16rmr */ + 0x0, /* */ +/* Table1375 */ + 0x644, /* MOV8ao16 */ +/* Table1376 */ + 0x61c, /* MOV32ao16 */ +/* Table1377 */ + 0x64a, /* MOV8o16a */ +/* Table1378 */ + 0x623, /* MOV32o16a */ +/* Table1379 */ + 0x449, /* JCXZ */ +/* Table1380 */ + 0x60b, /* MOV16ao16 */ +/* Table1381 */ + 0x611, /* MOV16o16a */ +/* Table1382 */ + 0x780, /* PAUSE */ +/* Table1383 */ + 0xd7, /* ADD64mr */ + 0xdb, /* ADD64rr */ +/* Table1385 */ + 0xda, /* ADD64rm */ + 0xdc, /* ADD64rr_REV */ +/* Table1387 */ + 0xd4, /* ADD64i32 */ +/* Table1388 */ + 0x740, /* OR64mr */ + 0x744, /* OR64rr */ +/* Table1390 */ + 0x743, /* OR64rm */ + 0x745, /* OR64rr_REV */ +/* Table1392 */ + 0x73d, /* OR64i32 */ +/* Table1393 */ + 0xaf, /* ADC64mr */ + 0xb3, /* ADC64rr */ +/* Table1395 */ + 0xb2, /* ADC64rm */ + 0xb4, /* ADC64rr_REV */ +/* Table1397 */ + 0xac, /* ADC64i32 */ +/* Table1398 */ + 0x9c1, /* SBB64mr */ + 0x9c5, /* SBB64rr */ +/* Table1400 */ + 0x9c4, /* SBB64rm */ + 0x9c6, /* SBB64rr_REV */ +/* Table1402 */ + 0x9be, /* SBB64i32 */ +/* Table1403 */ + 0x130, /* AND64mr */ + 0x134, /* AND64rr */ +/* Table1405 */ + 0x133, /* AND64rm */ + 0x135, /* AND64rr_REV */ +/* Table1407 */ + 0x12d, /* AND64i32 */ +/* Table1408 */ + 0xab2, /* SUB64mr */ + 0xab6, /* SUB64rr */ +/* Table1410 */ + 0xab5, /* SUB64rm */ + 0xab7, /* SUB64rr_REV */ +/* Table1412 */ + 0xaaf, /* SUB64i32 */ +/* Table1413 */ + 0x3b90, /* XOR64mr */ + 0x3b94, /* XOR64rr */ +/* Table1415 */ + 0x3b93, /* XOR64rm */ + 0x3b95, /* XOR64rr_REV */ +/* Table1417 */ + 0x3b8d, /* XOR64i32 */ +/* Table1418 */ + 0x298, /* CMP64mr */ + 0x29c, /* CMP64rr */ +/* Table1420 */ + 0x29b, /* CMP64rm */ + 0x29d, /* CMP64rr_REV */ +/* Table1422 */ + 0x295, /* CMP64i32 */ +/* Table1423 */ + 0x6af, /* MOVSX64rm32 */ + 0x6b2, /* MOVSX64rr32 */ +/* Table1425 */ + 0x3f2, /* IMUL64rmi32 */ + 0x3f5, /* IMUL64rri32 */ +/* Table1427 */ + 0x3f3, /* IMUL64rmi8 */ + 0x3f6, /* IMUL64rri8 */ +/* Table1429 */ + 0xd5, /* ADD64mi32 */ + 0x73e, /* OR64mi32 */ + 0xad, /* ADC64mi32 */ + 0x9bf, /* SBB64mi32 */ + 0x12e, /* AND64mi32 */ + 0xab0, /* SUB64mi32 */ + 0x3b8e, /* XOR64mi32 */ + 0x296, /* CMP64mi32 */ + 0xd8, /* ADD64ri32 */ + 0x741, /* OR64ri32 */ + 0xb0, /* ADC64ri32 */ + 0x9c2, /* SBB64ri32 */ + 0x131, /* AND64ri32 */ + 0xab3, /* SUB64ri32 */ + 0x3b91, /* XOR64ri32 */ + 0x299, /* CMP64ri32 */ +/* Table1445 */ + 0xd6, /* ADD64mi8 */ + 0x73f, /* OR64mi8 */ + 0xae, /* ADC64mi8 */ + 0x9c0, /* SBB64mi8 */ + 0x12f, /* AND64mi8 */ + 0xab1, /* SUB64mi8 */ + 0x3b8f, /* XOR64mi8 */ + 0x297, /* CMP64mi8 */ + 0xd9, /* ADD64ri8 */ + 0x742, /* OR64ri8 */ + 0xb1, /* ADC64ri8 */ + 0x9c3, /* SBB64ri8 */ + 0x132, /* AND64ri8 */ + 0xab4, /* SUB64ri8 */ + 0x3b92, /* XOR64ri8 */ + 0x29a, /* CMP64ri8 */ +/* Table1461 */ + 0xb10, /* TEST64mr */ + 0xb13, /* TEST64rr */ +/* Table1463 */ + 0x3b6e, /* XCHG64rm */ + 0x3b6f, /* XCHG64rr */ +/* Table1465 */ + 0x634, /* MOV64mr */ + 0x63c, /* MOV64rr */ +/* Table1467 */ + 0x63b, /* MOV64rm */ + 0x63d, /* MOV64rr_REV */ +/* Table1469 */ + 0x610, /* MOV16ms */ + 0x63e, /* MOV64rs */ +/* Table1471 */ + 0x4e2, /* LEA64r */ + 0x0, /* */ +/* Table1473 */ + 0x61a, /* MOV16sm */ + 0x63f, /* MOV64sr */ +/* Table1475 */ + 0x3b6d, /* XCHG64ar */ +/* Table1476 */ + 0x1f1, /* CDQE */ +/* Table1477 */ + 0x2da, /* CQO */ +/* Table1478 */ + 0x630, /* MOV64ao64 */ +/* Table1479 */ + 0x636, /* MOV64o64a */ +/* Table1480 */ + 0x69c, /* MOVSQ */ +/* Table1481 */ + 0x2b7, /* CMPSQ */ +/* Table1482 */ + 0xb0d, /* TEST64i32 */ +/* Table1483 */ + 0xa85, /* STOSQ */ +/* Table1484 */ + 0x4fd, /* LODSQ */ +/* Table1485 */ + 0x9d2, /* SCASQ */ +/* Table1486 */ + 0x639, /* MOV64ri */ +/* Table1487 */ + 0x93b, /* ROL64mi */ + 0x953, /* ROR64mi */ + 0x8e9, /* RCL64mi */ + 0x907, /* RCR64mi */ + 0xa15, /* SHL64mi */ + 0xa3d, /* SHR64mi */ + 0x984, /* SAL64mi */ + 0x99d, /* SAR64mi */ + 0x93e, /* ROL64ri */ + 0x956, /* ROR64ri */ + 0x8ec, /* RCL64ri */ + 0x90a, /* RCR64ri */ + 0xa18, /* SHL64ri */ + 0xa40, /* SHR64ri */ + 0x987, /* SAL64ri */ + 0x9a0, /* SAR64ri */ +/* Table1503 */ + 0x633, /* MOV64mi32 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3b66, /* XBEGIN_4 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1575 */ + 0x503, /* LRETIQ */ +/* Table1576 */ + 0x506, /* LRETQ */ +/* Table1577 */ + 0x422, /* IRET64 */ +/* Table1578 */ + 0x939, /* ROL64m1 */ + 0x951, /* ROR64m1 */ + 0x8e7, /* RCL64m1 */ + 0x905, /* RCR64m1 */ + 0xa13, /* SHL64m1 */ + 0xa3b, /* SHR64m1 */ + 0x982, /* SAL64m1 */ + 0x99b, /* SAR64m1 */ + 0x93c, /* ROL64r1 */ + 0x954, /* ROR64r1 */ + 0x8ea, /* RCL64r1 */ + 0x908, /* RCR64r1 */ + 0xa16, /* SHL64r1 */ + 0xa3e, /* SHR64r1 */ + 0x985, /* SAL64r1 */ + 0x99e, /* SAR64r1 */ +/* Table1594 */ + 0x93a, /* ROL64mCL */ + 0x952, /* ROR64mCL */ + 0x8e8, /* RCL64mCL */ + 0x906, /* RCR64mCL */ + 0xa14, /* SHL64mCL */ + 0xa3c, /* SHR64mCL */ + 0x983, /* SAL64mCL */ + 0x99c, /* SAR64mCL */ + 0x93d, /* ROL64rCL */ + 0x955, /* ROR64rCL */ + 0x8eb, /* RCL64rCL */ + 0x909, /* RCR64rCL */ + 0xa17, /* SHL64rCL */ + 0xa3f, /* SHR64rCL */ + 0x986, /* SAL64rCL */ + 0x99f, /* SAR64rCL */ +/* Table1610 */ + 0xb0e, /* TEST64mi32 */ + 0xb0f, /* TEST64mi32_alt */ + 0x727, /* NOT64m */ + 0x700, /* NEG64m */ + 0x6d1, /* MUL64m */ + 0x3ef, /* IMUL64m */ + 0x338, /* DIV64m */ + 0x3cf, /* IDIV64m */ + 0xb11, /* TEST64ri32 */ + 0xb12, /* TEST64ri32_alt */ + 0x728, /* NOT64r */ + 0x701, /* NEG64r */ + 0x6d2, /* MUL64r */ + 0x3f0, /* IMUL64r */ + 0x339, /* DIV64r */ + 0x3d0, /* IDIV64r */ +/* Table1626 */ + 0x405, /* INC64m */ + 0x330, /* DEC64m */ + 0x1e8, /* CALL64m */ + 0x382, /* FARCALL64 */ + 0x462, /* JMP64m */ + 0x387, /* FARJMP64 */ + 0x8c2, /* PUSH64rmm */ + 0x0, /* */ + 0x406, /* INC64r */ + 0x331, /* DEC64r */ + 0x1eb, /* CALL64r */ + 0x0, /* */ + 0x464, /* JMP64r */ + 0x0, /* */ + 0x8c3, /* PUSH64rmr */ + 0x0, /* */ +/* Table1642 */ + 0x62f, /* MOV64ao32 */ +/* Table1643 */ + 0x635, /* MOV64o32a */ +/* Table1644 */ + 0x633, /* MOV64mi32 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x63a, /* MOV64ri32 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3b65, /* XBEGIN_2 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1716 */ + 0x405, /* INC64m */ + 0x330, /* DEC64m */ + 0x1e8, /* CALL64m */ + 0x382, /* FARCALL64 */ + 0x462, /* JMP64m */ + 0x387, /* FARJMP64 */ + 0x8b9, /* PUSH16rmm */ + 0x0, /* */ + 0x406, /* INC64r */ + 0x331, /* DEC64r */ + 0x1eb, /* CALL64r */ + 0x0, /* */ + 0x464, /* JMP64r */ + 0x0, /* */ + 0x8ba, /* PUSH16rmr */ + 0x0, /* */ +/* Table1732 */ + 0x60d, /* MOV16ao64 */ +/* Table1733 */ + 0x613, /* MOV16o64a */ +/* Table1734 */ + 0x3ff, /* INC16m */ + 0x32a, /* DEC16m */ + 0x1e8, /* CALL64m */ + 0x37f, /* FARCALL16m */ + 0x462, /* JMP64m */ + 0x384, /* FARJMP16m */ + 0x8b9, /* PUSH16rmm */ + 0x0, /* */ + 0x400, /* INC16r */ + 0x32b, /* DEC16r */ + 0x1eb, /* CALL64r */ + 0x0, /* */ + 0x464, /* JMP64r */ + 0x0, /* */ + 0x8ba, /* PUSH16rmr */ + 0x0, /* */ +/* Table1750 */ + 0xa63, /* SLDT16m */ + 0xa8a, /* STRm */ + 0x4f4, /* LLDT16m */ + 0x511, /* LTRm */ + 0x1282, /* VERRm */ + 0x1284, /* VERWm */ + 0x0, /* */ + 0x0, /* */ + 0xa65, /* SLDT32r */ + 0xa88, /* STR32r */ + 0x4f5, /* LLDT16r */ + 0x512, /* LTRr */ + 0x1283, /* VERRr */ + 0x1285, /* VERWr */ + 0x0, /* */ + 0x0, /* */ +/* Table1766 */ + 0x9f7, /* SGDT32m */ + 0xa5c, /* SIDT32m */ + 0x4ec, /* LGDT32m */ + 0x4f2, /* LIDT32m */ + 0xa69, /* SMSW16m */ + 0x0, /* */ + 0x4f8, /* LMSW16m */ + 0x419, /* INVLPG */ + 0x375, /* ENCLV */ + 0x1c95, /* VMCALL */ + 0x1d40, /* VMLAUNCH */ + 0x1f7c, /* VMRESUME */ + 0x1fe7, /* VMXOFF */ + 0x7a5, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x609, /* MONITORrrr */ + 0x6fb, /* MWAITrr */ + 0x1f6, /* CLAC */ + 0xa7d, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x373, /* ENCLS */ + 0x3b79, /* XGETBV */ + 0x3bb0, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x1c97, /* VMFUNC */ + 0x3b78, /* XEND */ + 0x3bb4, /* XTEST */ + 0x374, /* ENCLU */ + 0x1f7d, /* VMRUN32 */ + 0x1d43, /* VMMCALL */ + 0x1d41, /* VMLOAD32 */ + 0x1f7f, /* VMSAVE32 */ + 0xa80, /* STGI */ + 0x1fc, /* CLGI */ + 0xa62, /* SKINIT */ + 0x41a, /* INVLPGA32 */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x918, /* RDPKRUr */ + 0x3b56, /* WRPKRUr */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0xaf4, /* SWAPGS */ + 0x923, /* RDTSCP */ + 0x608, /* MONITORXrrr */ + 0x6fa, /* MWAITXrrr */ + 0x201, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1838 */ + 0x4c5, /* LAR32rm */ + 0x4c6, /* LAR32rr */ +/* Table1840 */ + 0x50a, /* LSL32rm */ + 0x50b, /* LSL32rr */ +/* Table1842 */ + 0xaf5, /* SYSCALL */ +/* Table1843 */ + 0x1ff, /* CLTS */ +/* Table1844 */ + 0xaf9, /* SYSRET */ +/* Table1845 */ + 0x416, /* INVD */ +/* Table1846 */ + 0x3b4f, /* WBINVD */ +/* Table1847 */ + 0xb3f, /* UD2 */ +/* Table1848 */ + 0x85e, /* PREFETCH */ + 0x863, /* PREFETCHW */ + 0x864, /* PREFETCHWT1 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1864 */ + 0x391, /* FEMMS */ +/* Table1865 */ + 0x6b9, /* MOVUPSrm */ + 0x6ba, /* MOVUPSrr */ +/* Table1867 */ + 0x6b8, /* MOVUPSmr */ + 0x6bb, /* MOVUPSrr_REV */ +/* Table1869 */ + 0x67e, /* MOVLPSrm */ + 0x675, /* MOVHLPSrr */ +/* Table1871 */ + 0x67d, /* MOVLPSmr */ + 0x0, /* */ +/* Table1873 */ + 0xb4a, /* UNPCKLPSrm */ + 0xb4b, /* UNPCKLPSrr */ +/* Table1875 */ + 0xb46, /* UNPCKHPSrm */ + 0xb47, /* UNPCKHPSrr */ +/* Table1877 */ + 0x679, /* MOVHPSrm */ + 0x67a, /* MOVLHPSrr */ +/* Table1879 */ + 0x678, /* MOVHPSmr */ + 0x0, /* */ +/* Table1881 */ + 0x85f, /* PREFETCHNTA */ + 0x860, /* PREFETCHT0 */ + 0x861, /* PREFETCHT1 */ + 0x862, /* PREFETCHT2 */ + 0x70d, /* NOOP18_m4 */ + 0x70e, /* NOOP18_m5 */ + 0x70f, /* NOOP18_m6 */ + 0x710, /* NOOP18_m7 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x711, /* NOOP18_r4 */ + 0x712, /* NOOP18_r5 */ + 0x713, /* NOOP18_r6 */ + 0x714, /* NOOP18_r7 */ +/* Table1897 */ + 0x717, /* NOOPL_19 */ + 0x715, /* NOOP19rr */ +/* Table1899 */ + 0x191, /* BNDLDXrm */ + 0x0, /* */ +/* Table1901 */ + 0x19a, /* BNDSTXmr */ + 0x0, /* */ +/* Table1903 */ + 0x1f9, /* CLDEMOTE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1919 */ + 0x718, /* NOOPL_1d */ + 0x0, /* */ +/* Table1921 */ + 0x719, /* NOOPL_1e */ + 0x0, /* */ +/* Table1923 */ + 0x716, /* NOOPL */ + 0x71a, /* NOOPLr */ +/* Table1925 */ + 0x0, /* */ + 0x626, /* MOV32rc */ +/* Table1927 */ + 0x0, /* */ + 0x627, /* MOV32rd */ +/* Table1929 */ + 0x0, /* */ + 0x61f, /* MOV32cr */ +/* Table1931 */ + 0x0, /* */ + 0x620, /* MOV32dr */ +/* Table1933 */ + 0x659, /* MOVAPSrm */ + 0x65a, /* MOVAPSrr */ +/* Table1935 */ + 0x658, /* MOVAPSmr */ + 0x65b, /* MOVAPSrr_REV */ +/* Table1937 */ + 0x550, /* MMX_CVTPI2PSirm */ + 0x551, /* MMX_CVTPI2PSirr */ +/* Table1939 */ + 0x686, /* MOVNTPSmr */ + 0x0, /* */ +/* Table1941 */ + 0x556, /* MMX_CVTTPS2PIirm */ + 0x557, /* MMX_CVTTPS2PIirr */ +/* Table1943 */ + 0x552, /* MMX_CVTPS2PIirm */ + 0x553, /* MMX_CVTPS2PIirr */ +/* Table1945 */ + 0xb2e, /* UCOMISSrm */ + 0xb30, /* UCOMISSrr */ +/* Table1947 */ + 0x2cd, /* COMISSrm */ + 0x2cf, /* COMISSrr */ +/* Table1949 */ + 0x3b55, /* WRMSR */ +/* Table1950 */ + 0x922, /* RDTSC */ +/* Table1951 */ + 0x915, /* RDMSR */ +/* Table1952 */ + 0x919, /* RDPMC */ +/* Table1953 */ + 0xaf6, /* SYSENTER */ +/* Table1954 */ + 0xaf7, /* SYSEXIT */ +/* Table1955 */ + 0x3bb, /* GETSEC */ +/* Table1956 */ + 0x26f, /* CMOVO32rm */ + 0x270, /* CMOVO32rr */ +/* Table1958 */ + 0x259, /* CMOVNO32rm */ + 0x25a, /* CMOVNO32rr */ +/* Table1960 */ + 0x211, /* CMOVB32rm */ + 0x212, /* CMOVB32rr */ +/* Table1962 */ + 0x20b, /* CMOVAE32rm */ + 0x20c, /* CMOVAE32rr */ +/* Table1964 */ + 0x225, /* CMOVE32rm */ + 0x226, /* CMOVE32rr */ +/* Table1966 */ + 0x24f, /* CMOVNE32rm */ + 0x250, /* CMOVNE32rr */ +/* Table1968 */ + 0x217, /* CMOVBE32rm */ + 0x218, /* CMOVBE32rr */ +/* Table1970 */ + 0x205, /* CMOVA32rm */ + 0x206, /* CMOVA32rr */ +/* Table1972 */ + 0x27f, /* CMOVS32rm */ + 0x280, /* CMOVS32rr */ +/* Table1974 */ + 0x269, /* CMOVNS32rm */ + 0x26a, /* CMOVNS32rr */ +/* Table1976 */ + 0x275, /* CMOVP32rm */ + 0x276, /* CMOVP32rr */ +/* Table1978 */ + 0x25f, /* CMOVNP32rm */ + 0x260, /* CMOVNP32rr */ +/* Table1980 */ + 0x23b, /* CMOVL32rm */ + 0x23c, /* CMOVL32rr */ +/* Table1982 */ + 0x235, /* CMOVGE32rm */ + 0x236, /* CMOVGE32rr */ +/* Table1984 */ + 0x241, /* CMOVLE32rm */ + 0x242, /* CMOVLE32rr */ +/* Table1986 */ + 0x22f, /* CMOVG32rm */ + 0x230, /* CMOVG32rr */ +/* Table1988 */ + 0x0, /* */ + 0x680, /* MOVMSKPSrr */ +/* Table1990 */ + 0xa6f, /* SQRTPSm */ + 0xa70, /* SQRTPSr */ +/* Table1992 */ + 0x96e, /* RSQRTPSm */ + 0x96f, /* RSQRTPSr */ +/* Table1994 */ + 0x8f3, /* RCPPSm */ + 0x8f4, /* RCPPSr */ +/* Table1996 */ + 0x149, /* ANDPSrm */ + 0x14a, /* ANDPSrr */ +/* Table1998 */ + 0x145, /* ANDNPSrm */ + 0x146, /* ANDNPSrr */ +/* Table2000 */ + 0x751, /* ORPSrm */ + 0x752, /* ORPSrr */ +/* Table2002 */ + 0x3ba1, /* XORPSrm */ + 0x3ba2, /* XORPSrr */ +/* Table2004 */ + 0xe8, /* ADDPSrm */ + 0xe9, /* ADDPSrr */ +/* Table2006 */ + 0x6d7, /* MULPSrm */ + 0x6d8, /* MULPSrr */ +/* Table2008 */ + 0x2ef, /* CVTPS2PDrm */ + 0x2f0, /* CVTPS2PDrr */ +/* Table2010 */ + 0x2e7, /* CVTDQ2PSrm */ + 0x2e8, /* CVTDQ2PSrr */ +/* Table2012 */ + 0xac3, /* SUBPSrm */ + 0xac4, /* SUBPSrr */ +/* Table2014 */ + 0x542, /* MINPSrm */ + 0x543, /* MINPSrr */ +/* Table2016 */ + 0x33e, /* DIVPSrm */ + 0x33f, /* DIVPSrr */ +/* Table2018 */ + 0x52d, /* MAXPSrm */ + 0x52e, /* MAXPSrr */ +/* Table2020 */ + 0x600, /* MMX_PUNPCKLBWirm */ + 0x601, /* MMX_PUNPCKLBWirr */ +/* Table2022 */ + 0x604, /* MMX_PUNPCKLWDirm */ + 0x605, /* MMX_PUNPCKLWDirr */ +/* Table2024 */ + 0x602, /* MMX_PUNPCKLDQirm */ + 0x603, /* MMX_PUNPCKLDQirr */ +/* Table2026 */ + 0x574, /* MMX_PACKSSWBirm */ + 0x575, /* MMX_PACKSSWBirr */ +/* Table2028 */ + 0x598, /* MMX_PCMPGTBirm */ + 0x599, /* MMX_PCMPGTBirr */ +/* Table2030 */ + 0x59c, /* MMX_PCMPGTWirm */ + 0x59d, /* MMX_PCMPGTWirr */ +/* Table2032 */ + 0x59a, /* MMX_PCMPGTDirm */ + 0x59b, /* MMX_PCMPGTDirr */ +/* Table2034 */ + 0x576, /* MMX_PACKUSWBirm */ + 0x577, /* MMX_PACKUSWBirr */ +/* Table2036 */ + 0x5fa, /* MMX_PUNPCKHBWirm */ + 0x5fb, /* MMX_PUNPCKHBWirr */ +/* Table2038 */ + 0x5fe, /* MMX_PUNPCKHWDirm */ + 0x5ff, /* MMX_PUNPCKHWDirr */ +/* Table2040 */ + 0x5fc, /* MMX_PUNPCKHDQirm */ + 0x5fd, /* MMX_PUNPCKHDQirr */ +/* Table2042 */ + 0x572, /* MMX_PACKSSDWirm */ + 0x573, /* MMX_PACKSSDWirr */ +/* Table2044 */ + 0x55f, /* MMX_MOVD64rm */ + 0x560, /* MMX_MOVD64rr */ +/* Table2046 */ + 0x569, /* MMX_MOVQ64rm */ + 0x56a, /* MMX_MOVQ64rr */ +/* Table2048 */ + 0x5ca, /* MMX_PSHUFWmi */ + 0x5cb, /* MMX_PSHUFWri */ +/* Table2050 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x5e7, /* MMX_PSRLWri */ + 0x0, /* */ + 0x5de, /* MMX_PSRAWri */ + 0x0, /* */ + 0x5d8, /* MMX_PSLLWri */ + 0x0, /* */ +/* Table2066 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x5e1, /* MMX_PSRLDri */ + 0x0, /* */ + 0x5db, /* MMX_PSRADri */ + 0x0, /* */ + 0x5d2, /* MMX_PSLLDri */ + 0x0, /* */ +/* Table2082 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x5e4, /* MMX_PSRLQri */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x5d5, /* MMX_PSLLQri */ + 0x0, /* */ +/* Table2098 */ + 0x592, /* MMX_PCMPEQBirm */ + 0x593, /* MMX_PCMPEQBirr */ +/* Table2100 */ + 0x596, /* MMX_PCMPEQWirm */ + 0x597, /* MMX_PCMPEQWirr */ +/* Table2102 */ + 0x594, /* MMX_PCMPEQDirm */ + 0x595, /* MMX_PCMPEQDirr */ +/* Table2104 */ + 0x558, /* MMX_EMMS */ +/* Table2105 */ + 0x1f78, /* VMREAD32mr */ + 0x1f79, /* VMREAD32rr */ +/* Table2107 */ + 0x1fe3, /* VMWRITE32rm */ + 0x1fe4, /* VMWRITE32rr */ +/* Table2109 */ + 0x55e, /* MMX_MOVD64mr */ + 0x55d, /* MMX_MOVD64grr */ +/* Table2111 */ + 0x568, /* MMX_MOVQ64mr */ + 0x56b, /* MMX_MOVQ64rr_REV */ +/* Table2113 */ + 0x477, /* JO_4 */ +/* Table2114 */ + 0x46e, /* JNO_4 */ +/* Table2115 */ + 0x448, /* JB_4 */ +/* Table2116 */ + 0x43f, /* JAE_4 */ +/* Table2117 */ + 0x44d, /* JE_4 */ +/* Table2118 */ + 0x46b, /* JNE_4 */ +/* Table2119 */ + 0x445, /* JBE_4 */ +/* Table2120 */ + 0x442, /* JA_4 */ +/* Table2121 */ + 0x47e, /* JS_4 */ +/* Table2122 */ + 0x474, /* JNS_4 */ +/* Table2123 */ + 0x47a, /* JP_4 */ +/* Table2124 */ + 0x471, /* JNP_4 */ +/* Table2125 */ + 0x459, /* JL_4 */ +/* Table2126 */ + 0x450, /* JGE_4 */ +/* Table2127 */ + 0x456, /* JLE_4 */ +/* Table2128 */ + 0x453, /* JG_4 */ +/* Table2129 */ + 0x9ee, /* SETOm */ + 0x9ef, /* SETOr */ +/* Table2131 */ + 0x9e8, /* SETNOm */ + 0x9e9, /* SETNOr */ +/* Table2133 */ + 0x9da, /* SETBm */ + 0x9db, /* SETBr */ +/* Table2135 */ + 0x9d4, /* SETAEm */ + 0x9d5, /* SETAEr */ +/* Table2137 */ + 0x9dc, /* SETEm */ + 0x9dd, /* SETEr */ +/* Table2139 */ + 0x9e6, /* SETNEm */ + 0x9e7, /* SETNEr */ +/* Table2141 */ + 0x9d8, /* SETBEm */ + 0x9d9, /* SETBEr */ +/* Table2143 */ + 0x9d6, /* SETAm */ + 0x9d7, /* SETAr */ +/* Table2145 */ + 0x9f3, /* SETSm */ + 0x9f4, /* SETSr */ +/* Table2147 */ + 0x9ec, /* SETNSm */ + 0x9ed, /* SETNSr */ +/* Table2149 */ + 0x9f0, /* SETPm */ + 0x9f1, /* SETPr */ +/* Table2151 */ + 0x9ea, /* SETNPm */ + 0x9eb, /* SETNPr */ +/* Table2153 */ + 0x9e4, /* SETLm */ + 0x9e5, /* SETLr */ +/* Table2155 */ + 0x9de, /* SETGEm */ + 0x9df, /* SETGEr */ +/* Table2157 */ + 0x9e2, /* SETLEm */ + 0x9e3, /* SETLEr */ +/* Table2159 */ + 0x9e0, /* SETGm */ + 0x9e1, /* SETGr */ +/* Table2161 */ + 0x8d0, /* PUSHFS32 */ +/* Table2162 */ + 0x855, /* POPFS32 */ +/* Table2163 */ + 0x2d9, /* CPUID */ +/* Table2164 */ + 0x1b1, /* BT32mr */ + 0x1b3, /* BT32rr */ +/* Table2166 */ + 0xa24, /* SHLD32mri8 */ + 0xa26, /* SHLD32rri8 */ +/* Table2168 */ + 0xa23, /* SHLD32mrCL */ + 0xa25, /* SHLD32rrCL */ +/* Table2170 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x60a, /* MONTMUL */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3bb1, /* XSHA1 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3bb2, /* XSHA256 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2242 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3bb3, /* XSTORE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3b76, /* XCRYPTECB */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3b73, /* XCRYPTCBC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3b75, /* XCRYPTCTR */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3b74, /* XCRYPTCFB */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3b77, /* XCRYPTOFB */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2314 */ + 0x8d3, /* PUSHGS32 */ +/* Table2315 */ + 0x858, /* POPGS32 */ +/* Table2316 */ + 0x96d, /* RSM */ +/* Table2317 */ + 0x1d5, /* BTS32mr */ + 0x1d7, /* BTS32rr */ +/* Table2319 */ + 0xa4c, /* SHRD32mri8 */ + 0xa4e, /* SHRD32rri8 */ +/* Table2321 */ + 0xa4b, /* SHRD32mrCL */ + 0xa4d, /* SHRD32rrCL */ +/* Table2323 */ + 0x3b6, /* FXSAVE */ + 0x3b4, /* FXRSTOR */ + 0x4ca, /* LDMXCSR */ + 0xa82, /* STMXCSR */ + 0x3ba8, /* XSAVE */ + 0x3ba4, /* XRSTOR */ + 0x3bac, /* XSAVEOPT */ + 0x1fa, /* CLFLUSH */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x4e7, /* LFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x537, /* MFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x9f5, /* SFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2395 */ + 0x3e9, /* IMUL32rm */ + 0x3ec, /* IMUL32rr */ +/* Table2397 */ + 0x2c7, /* CMPXCHG8rm */ + 0x2c8, /* CMPXCHG8rr */ +/* Table2399 */ + 0x2c2, /* CMPXCHG32rm */ + 0x2c3, /* CMPXCHG32rr */ +/* Table2401 */ + 0x50f, /* LSS32rm */ + 0x0, /* */ +/* Table2403 */ + 0x1c9, /* BTR32mr */ + 0x1cb, /* BTR32rr */ +/* Table2405 */ + 0x4e9, /* LFS32rm */ + 0x0, /* */ +/* Table2407 */ + 0x4ef, /* LGS32rm */ + 0x0, /* */ +/* Table2409 */ + 0x6c2, /* MOVZX32rm8 */ + 0x6c5, /* MOVZX32rr8 */ +/* Table2411 */ + 0x6c1, /* MOVZX32rm16 */ + 0x6c4, /* MOVZX32rr16 */ +/* Table2413 */ + 0xb3e, /* UD1 */ +/* Table2414 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x1b0, /* BT32mi8 */ + 0x1d4, /* BTS32mi8 */ + 0x1c8, /* BTR32mi8 */ + 0x1bc, /* BTC32mi8 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x1b2, /* BT32ri8 */ + 0x1d6, /* BTS32ri8 */ + 0x1ca, /* BTR32ri8 */ + 0x1be, /* BTC32ri8 */ +/* Table2430 */ + 0x1bd, /* BTC32mr */ + 0x1bf, /* BTC32rr */ +/* Table2432 */ + 0x19f, /* BSF32rm */ + 0x1a0, /* BSF32rr */ +/* Table2434 */ + 0x1a5, /* BSR32rm */ + 0x1a6, /* BSR32rr */ +/* Table2436 */ + 0x6a9, /* MOVSX32rm8 */ + 0x6ac, /* MOVSX32rr8 */ +/* Table2438 */ + 0x6a8, /* MOVSX32rm16 */ + 0x6ab, /* MOVSX32rr16 */ +/* Table2440 */ + 0x3b63, /* XADD8rm */ + 0x3b64, /* XADD8rr */ +/* Table2442 */ + 0x3b5f, /* XADD32rm */ + 0x3b60, /* XADD32rr */ +/* Table2444 */ + 0x2ab, /* CMPPSrmi */ + 0x2ad, /* CMPPSrri */ +/* Table2446 */ + 0x684, /* MOVNTImr */ + 0x0, /* */ +/* Table2448 */ + 0x5ab, /* MMX_PINSRWrm */ + 0x5ac, /* MMX_PINSRWrr */ +/* Table2450 */ + 0x0, /* */ + 0x59e, /* MMX_PEXTRWrr */ +/* Table2452 */ + 0xa59, /* SHUFPSrmi */ + 0xa5a, /* SHUFPSrri */ +/* Table2454 */ + 0x0, /* */ + 0x2c6, /* CMPXCHG8B */ + 0x0, /* */ + 0x3ba6, /* XRSTORS */ + 0x3baa, /* XSAVEC */ + 0x3bae, /* XSAVES */ + 0x1f76, /* VMPTRLDm */ + 0x1f77, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x91b, /* RDRAND32r */ + 0x91e, /* RDSEED32r */ +/* Table2470 */ + 0x1aa, /* BSWAP32r */ +/* Table2471 */ + 0x5e8, /* MMX_PSRLWrm */ + 0x5e9, /* MMX_PSRLWrr */ +/* Table2473 */ + 0x5e2, /* MMX_PSRLDrm */ + 0x5e3, /* MMX_PSRLDrr */ +/* Table2475 */ + 0x5e5, /* MMX_PSRLQrm */ + 0x5e6, /* MMX_PSRLQrr */ +/* Table2477 */ + 0x57c, /* MMX_PADDQirm */ + 0x57d, /* MMX_PADDQirr */ +/* Table2479 */ + 0x5c0, /* MMX_PMULLWirm */ + 0x5c1, /* MMX_PMULLWirr */ +/* Table2481 */ + 0x0, /* */ + 0x5b9, /* MMX_PMOVMSKBrr */ +/* Table2483 */ + 0x5f4, /* MMX_PSUBUSBirm */ + 0x5f5, /* MMX_PSUBUSBirr */ +/* Table2485 */ + 0x5f6, /* MMX_PSUBUSWirm */ + 0x5f7, /* MMX_PSUBUSWirr */ +/* Table2487 */ + 0x5b7, /* MMX_PMINUBirm */ + 0x5b8, /* MMX_PMINUBirr */ +/* Table2489 */ + 0x58c, /* MMX_PANDirm */ + 0x58d, /* MMX_PANDirr */ +/* Table2491 */ + 0x582, /* MMX_PADDUSBirm */ + 0x583, /* MMX_PADDUSBirr */ +/* Table2493 */ + 0x584, /* MMX_PADDUSWirm */ + 0x585, /* MMX_PADDUSWirr */ +/* Table2495 */ + 0x5b3, /* MMX_PMAXUBirm */ + 0x5b4, /* MMX_PMAXUBirr */ +/* Table2497 */ + 0x58a, /* MMX_PANDNirm */ + 0x58b, /* MMX_PANDNirr */ +/* Table2499 */ + 0x58e, /* MMX_PAVGBirm */ + 0x58f, /* MMX_PAVGBirr */ +/* Table2501 */ + 0x5df, /* MMX_PSRAWrm */ + 0x5e0, /* MMX_PSRAWrr */ +/* Table2503 */ + 0x5dc, /* MMX_PSRADrm */ + 0x5dd, /* MMX_PSRADrr */ +/* Table2505 */ + 0x590, /* MMX_PAVGWirm */ + 0x591, /* MMX_PAVGWirr */ +/* Table2507 */ + 0x5bc, /* MMX_PMULHUWirm */ + 0x5bd, /* MMX_PMULHUWirr */ +/* Table2509 */ + 0x5be, /* MMX_PMULHWirm */ + 0x5bf, /* MMX_PMULHWirr */ +/* Table2511 */ + 0x565, /* MMX_MOVNTQmr */ + 0x0, /* */ +/* Table2513 */ + 0x5f0, /* MMX_PSUBSBirm */ + 0x5f1, /* MMX_PSUBSBirr */ +/* Table2515 */ + 0x5f2, /* MMX_PSUBSWirm */ + 0x5f3, /* MMX_PSUBSWirr */ +/* Table2517 */ + 0x5b5, /* MMX_PMINSWirm */ + 0x5b6, /* MMX_PMINSWirr */ +/* Table2519 */ + 0x5c4, /* MMX_PORirm */ + 0x5c5, /* MMX_PORirr */ +/* Table2521 */ + 0x57e, /* MMX_PADDSBirm */ + 0x57f, /* MMX_PADDSBirr */ +/* Table2523 */ + 0x580, /* MMX_PADDSWirm */ + 0x581, /* MMX_PADDSWirr */ +/* Table2525 */ + 0x5b1, /* MMX_PMAXSWirm */ + 0x5b2, /* MMX_PMAXSWirr */ +/* Table2527 */ + 0x606, /* MMX_PXORirm */ + 0x607, /* MMX_PXORirr */ +/* Table2529 */ + 0x5d9, /* MMX_PSLLWrm */ + 0x5da, /* MMX_PSLLWrr */ +/* Table2531 */ + 0x5d3, /* MMX_PSLLDrm */ + 0x5d4, /* MMX_PSLLDrr */ +/* Table2533 */ + 0x5d6, /* MMX_PSLLQrm */ + 0x5d7, /* MMX_PSLLQrr */ +/* Table2535 */ + 0x5c2, /* MMX_PMULUDQirm */ + 0x5c3, /* MMX_PMULUDQirr */ +/* Table2537 */ + 0x5af, /* MMX_PMADDWDirm */ + 0x5b0, /* MMX_PMADDWDirr */ +/* Table2539 */ + 0x5c6, /* MMX_PSADBWirm */ + 0x5c7, /* MMX_PSADBWirr */ +/* Table2541 */ + 0x0, /* */ + 0x559, /* MMX_MASKMOVQ */ +/* Table2543 */ + 0x5ea, /* MMX_PSUBBirm */ + 0x5eb, /* MMX_PSUBBirr */ +/* Table2545 */ + 0x5f8, /* MMX_PSUBWirm */ + 0x5f9, /* MMX_PSUBWirr */ +/* Table2547 */ + 0x5ec, /* MMX_PSUBDirm */ + 0x5ed, /* MMX_PSUBDirr */ +/* Table2549 */ + 0x5ee, /* MMX_PSUBQirm */ + 0x5ef, /* MMX_PSUBQirr */ +/* Table2551 */ + 0x578, /* MMX_PADDBirm */ + 0x579, /* MMX_PADDBirr */ +/* Table2553 */ + 0x586, /* MMX_PADDWirm */ + 0x587, /* MMX_PADDWirr */ +/* Table2555 */ + 0x57a, /* MMX_PADDDirm */ + 0x57b, /* MMX_PADDDirr */ +/* Table2557 */ + 0xb3d, /* UD0 */ +/* Table2558 */ + 0x9f8, /* SGDT64m */ + 0xa5d, /* SIDT64m */ + 0x4ed, /* LGDT64m */ + 0x4f3, /* LIDT64m */ + 0xa69, /* SMSW16m */ + 0x0, /* */ + 0x4f8, /* LMSW16m */ + 0x419, /* INVLPG */ + 0x375, /* ENCLV */ + 0x1c95, /* VMCALL */ + 0x1d40, /* VMLAUNCH */ + 0x1f7c, /* VMRESUME */ + 0x1fe7, /* VMXOFF */ + 0x7a5, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x609, /* MONITORrrr */ + 0x6fb, /* MWAITrr */ + 0x1f6, /* CLAC */ + 0xa7d, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x373, /* ENCLS */ + 0x3b79, /* XGETBV */ + 0x3bb0, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x1c97, /* VMFUNC */ + 0x3b78, /* XEND */ + 0x3bb4, /* XTEST */ + 0x374, /* ENCLU */ + 0x1f7e, /* VMRUN64 */ + 0x1d43, /* VMMCALL */ + 0x1d42, /* VMLOAD64 */ + 0x1f80, /* VMSAVE64 */ + 0xa80, /* STGI */ + 0x1fc, /* CLGI */ + 0xa62, /* SKINIT */ + 0x41b, /* INVLPGA64 */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x918, /* RDPKRUr */ + 0x3b56, /* WRPKRUr */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0xaf4, /* SWAPGS */ + 0x923, /* RDTSCP */ + 0x608, /* MONITORXrrr */ + 0x6fa, /* MWAITXrrr */ + 0x201, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2630 */ + 0x0, /* */ + 0x637, /* MOV64rc */ +/* Table2632 */ + 0x0, /* */ + 0x638, /* MOV64rd */ +/* Table2634 */ + 0x0, /* */ + 0x631, /* MOV64cr */ +/* Table2636 */ + 0x0, /* */ + 0x632, /* MOV64dr */ +/* Table2638 */ + 0x1f7a, /* VMREAD64mr */ + 0x1f7b, /* VMREAD64rr */ +/* Table2640 */ + 0x1fe5, /* VMWRITE64rm */ + 0x1fe6, /* VMWRITE64rr */ +/* Table2642 */ + 0x8d1, /* PUSHFS64 */ +/* Table2643 */ + 0x856, /* POPFS64 */ +/* Table2644 */ + 0x8d4, /* PUSHGS64 */ +/* Table2645 */ + 0x859, /* POPGS64 */ +/* Table2646 */ + 0x0, /* */ + 0x55a, /* MMX_MASKMOVQ64 */ +/* Table2648 */ + 0xa63, /* SLDT16m */ + 0xa8a, /* STRm */ + 0x4f4, /* LLDT16m */ + 0x511, /* LTRm */ + 0x1282, /* VERRm */ + 0x1284, /* VERWm */ + 0x0, /* */ + 0x0, /* */ + 0xa64, /* SLDT16r */ + 0xa87, /* STR16r */ + 0x4f5, /* LLDT16r */ + 0x512, /* LTRr */ + 0x1283, /* VERRr */ + 0x1285, /* VERWr */ + 0x0, /* */ + 0x0, /* */ +/* Table2664 */ + 0x9f6, /* SGDT16m */ + 0xa5b, /* SIDT16m */ + 0x4eb, /* LGDT16m */ + 0x4f1, /* LIDT16m */ + 0xa69, /* SMSW16m */ + 0x0, /* */ + 0x4f8, /* LMSW16m */ + 0x419, /* INVLPG */ + 0x375, /* ENCLV */ + 0x1c95, /* VMCALL */ + 0x1d40, /* VMLAUNCH */ + 0x1f7c, /* VMRESUME */ + 0x1fe7, /* VMXOFF */ + 0x7a5, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x609, /* MONITORrrr */ + 0x6fb, /* MWAITrr */ + 0x1f6, /* CLAC */ + 0xa7d, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x373, /* ENCLS */ + 0x3b79, /* XGETBV */ + 0x3bb0, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x1c97, /* VMFUNC */ + 0x3b78, /* XEND */ + 0x3bb4, /* XTEST */ + 0x374, /* ENCLU */ + 0x1f7d, /* VMRUN32 */ + 0x1d43, /* VMMCALL */ + 0x1d41, /* VMLOAD32 */ + 0x1f7f, /* VMSAVE32 */ + 0xa80, /* STGI */ + 0x1fc, /* CLGI */ + 0xa62, /* SKINIT */ + 0x41a, /* INVLPGA32 */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x918, /* RDPKRUr */ + 0x3b56, /* WRPKRUr */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0xaf4, /* SWAPGS */ + 0x923, /* RDTSCP */ + 0x608, /* MONITORXrrr */ + 0x6fa, /* MWAITXrrr */ + 0x201, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2736 */ + 0x4c3, /* LAR16rm */ + 0x4c4, /* LAR16rr */ +/* Table2738 */ + 0x508, /* LSL16rm */ + 0x509, /* LSL16rr */ +/* Table2740 */ + 0x6b5, /* MOVUPDrm */ + 0x6b6, /* MOVUPDrr */ +/* Table2742 */ + 0x6b4, /* MOVUPDmr */ + 0x6b7, /* MOVUPDrr_REV */ +/* Table2744 */ + 0x67c, /* MOVLPDrm */ + 0x0, /* */ +/* Table2746 */ + 0x67b, /* MOVLPDmr */ + 0x0, /* */ +/* Table2748 */ + 0xb48, /* UNPCKLPDrm */ + 0xb49, /* UNPCKLPDrr */ +/* Table2750 */ + 0xb44, /* UNPCKHPDrm */ + 0xb45, /* UNPCKHPDrr */ +/* Table2752 */ + 0x677, /* MOVHPDrm */ + 0x0, /* */ +/* Table2754 */ + 0x676, /* MOVHPDmr */ + 0x0, /* */ +/* Table2756 */ + 0x85f, /* PREFETCHNTA */ + 0x860, /* PREFETCHT0 */ + 0x861, /* PREFETCHT1 */ + 0x862, /* PREFETCHT2 */ + 0x705, /* NOOP18_16m4 */ + 0x706, /* NOOP18_16m5 */ + 0x707, /* NOOP18_16m6 */ + 0x708, /* NOOP18_16m7 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x709, /* NOOP18_16r4 */ + 0x70a, /* NOOP18_16r5 */ + 0x70b, /* NOOP18_16r6 */ + 0x70c, /* NOOP18_16r7 */ +/* Table2772 */ + 0x71e, /* NOOPW_19 */ + 0x715, /* NOOP19rr */ +/* Table2774 */ + 0x195, /* BNDMOV32rm */ + 0x198, /* BNDMOVrr */ +/* Table2776 */ + 0x194, /* BNDMOV32mr */ + 0x199, /* BNDMOVrr_REV */ +/* Table2778 */ + 0x71f, /* NOOPW_1c */ + 0x0, /* */ +/* Table2780 */ + 0x720, /* NOOPW_1d */ + 0x0, /* */ +/* Table2782 */ + 0x721, /* NOOPW_1e */ + 0x0, /* */ +/* Table2784 */ + 0x71d, /* NOOPW */ + 0x722, /* NOOPWr */ +/* Table2786 */ + 0x655, /* MOVAPDrm */ + 0x656, /* MOVAPDrr */ +/* Table2788 */ + 0x654, /* MOVAPDmr */ + 0x657, /* MOVAPDrr_REV */ +/* Table2790 */ + 0x54e, /* MMX_CVTPI2PDirm */ + 0x54f, /* MMX_CVTPI2PDirr */ +/* Table2792 */ + 0x685, /* MOVNTPDmr */ + 0x0, /* */ +/* Table2794 */ + 0x554, /* MMX_CVTTPD2PIirm */ + 0x555, /* MMX_CVTTPD2PIirr */ +/* Table2796 */ + 0x54c, /* MMX_CVTPD2PIirm */ + 0x54d, /* MMX_CVTPD2PIirr */ +/* Table2798 */ + 0xb2a, /* UCOMISDrm */ + 0xb2c, /* UCOMISDrr */ +/* Table2800 */ + 0x2c9, /* COMISDrm */ + 0x2cb, /* COMISDrr */ +/* Table2802 */ + 0x26d, /* CMOVO16rm */ + 0x26e, /* CMOVO16rr */ +/* Table2804 */ + 0x257, /* CMOVNO16rm */ + 0x258, /* CMOVNO16rr */ +/* Table2806 */ + 0x20f, /* CMOVB16rm */ + 0x210, /* CMOVB16rr */ +/* Table2808 */ + 0x209, /* CMOVAE16rm */ + 0x20a, /* CMOVAE16rr */ +/* Table2810 */ + 0x223, /* CMOVE16rm */ + 0x224, /* CMOVE16rr */ +/* Table2812 */ + 0x24d, /* CMOVNE16rm */ + 0x24e, /* CMOVNE16rr */ +/* Table2814 */ + 0x215, /* CMOVBE16rm */ + 0x216, /* CMOVBE16rr */ +/* Table2816 */ + 0x203, /* CMOVA16rm */ + 0x204, /* CMOVA16rr */ +/* Table2818 */ + 0x27d, /* CMOVS16rm */ + 0x27e, /* CMOVS16rr */ +/* Table2820 */ + 0x267, /* CMOVNS16rm */ + 0x268, /* CMOVNS16rr */ +/* Table2822 */ + 0x273, /* CMOVP16rm */ + 0x274, /* CMOVP16rr */ +/* Table2824 */ + 0x25d, /* CMOVNP16rm */ + 0x25e, /* CMOVNP16rr */ +/* Table2826 */ + 0x239, /* CMOVL16rm */ + 0x23a, /* CMOVL16rr */ +/* Table2828 */ + 0x233, /* CMOVGE16rm */ + 0x234, /* CMOVGE16rr */ +/* Table2830 */ + 0x23f, /* CMOVLE16rm */ + 0x240, /* CMOVLE16rr */ +/* Table2832 */ + 0x22d, /* CMOVG16rm */ + 0x22e, /* CMOVG16rr */ +/* Table2834 */ + 0x0, /* */ + 0x67f, /* MOVMSKPDrr */ +/* Table2836 */ + 0xa6d, /* SQRTPDm */ + 0xa6e, /* SQRTPDr */ +/* Table2838 */ + 0x147, /* ANDPDrm */ + 0x148, /* ANDPDrr */ +/* Table2840 */ + 0x143, /* ANDNPDrm */ + 0x144, /* ANDNPDrr */ +/* Table2842 */ + 0x74f, /* ORPDrm */ + 0x750, /* ORPDrr */ +/* Table2844 */ + 0x3b9f, /* XORPDrm */ + 0x3ba0, /* XORPDrr */ +/* Table2846 */ + 0xe6, /* ADDPDrm */ + 0xe7, /* ADDPDrr */ +/* Table2848 */ + 0x6d5, /* MULPDrm */ + 0x6d6, /* MULPDrr */ +/* Table2850 */ + 0x2eb, /* CVTPD2PSrm */ + 0x2ec, /* CVTPD2PSrr */ +/* Table2852 */ + 0x2ed, /* CVTPS2DQrm */ + 0x2ee, /* CVTPS2DQrr */ +/* Table2854 */ + 0xac1, /* SUBPDrm */ + 0xac2, /* SUBPDrr */ +/* Table2856 */ + 0x540, /* MINPDrm */ + 0x541, /* MINPDrr */ +/* Table2858 */ + 0x33c, /* DIVPDrm */ + 0x33d, /* DIVPDrr */ +/* Table2860 */ + 0x52b, /* MAXPDrm */ + 0x52c, /* MAXPDrr */ +/* Table2862 */ + 0x8af, /* PUNPCKLBWrm */ + 0x8b0, /* PUNPCKLBWrr */ +/* Table2864 */ + 0x8b5, /* PUNPCKLWDrm */ + 0x8b6, /* PUNPCKLWDrr */ +/* Table2866 */ + 0x8b1, /* PUNPCKLDQrm */ + 0x8b2, /* PUNPCKLDQrr */ +/* Table2868 */ + 0x764, /* PACKSSWBrm */ + 0x765, /* PACKSSWBrr */ +/* Table2870 */ + 0x799, /* PCMPGTBrm */ + 0x79a, /* PCMPGTBrr */ +/* Table2872 */ + 0x79f, /* PCMPGTWrm */ + 0x7a0, /* PCMPGTWrr */ +/* Table2874 */ + 0x79b, /* PCMPGTDrm */ + 0x79c, /* PCMPGTDrr */ +/* Table2876 */ + 0x768, /* PACKUSWBrm */ + 0x769, /* PACKUSWBrr */ +/* Table2878 */ + 0x8a7, /* PUNPCKHBWrm */ + 0x8a8, /* PUNPCKHBWrr */ +/* Table2880 */ + 0x8ad, /* PUNPCKHWDrm */ + 0x8ae, /* PUNPCKHWDrr */ +/* Table2882 */ + 0x8a9, /* PUNPCKHDQrm */ + 0x8aa, /* PUNPCKHDQrr */ +/* Table2884 */ + 0x762, /* PACKSSDWrm */ + 0x763, /* PACKSSDWrr */ +/* Table2886 */ + 0x8b3, /* PUNPCKLQDQrm */ + 0x8b4, /* PUNPCKLQDQrr */ +/* Table2888 */ + 0x8ab, /* PUNPCKHQDQrm */ + 0x8ac, /* PUNPCKHQDQrr */ +/* Table2890 */ + 0x664, /* MOVDI2PDIrm */ + 0x665, /* MOVDI2PDIrr */ +/* Table2892 */ + 0x66e, /* MOVDQArm */ + 0x66f, /* MOVDQArr */ +/* Table2894 */ + 0x869, /* PSHUFDmi */ + 0x86a, /* PSHUFDri */ +/* Table2896 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x88c, /* PSRLWri */ + 0x0, /* */ + 0x882, /* PSRAWri */ + 0x0, /* */ + 0x87c, /* PSLLWri */ + 0x0, /* */ +/* Table2912 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x886, /* PSRLDri */ + 0x0, /* */ + 0x87f, /* PSRADri */ + 0x0, /* */ + 0x876, /* PSLLDri */ + 0x0, /* */ +/* Table2928 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x889, /* PSRLQri */ + 0x885, /* PSRLDQri */ + 0x0, /* */ + 0x0, /* */ + 0x879, /* PSLLQri */ + 0x875, /* PSLLDQri */ +/* Table2944 */ + 0x78d, /* PCMPEQBrm */ + 0x78e, /* PCMPEQBrr */ +/* Table2946 */ + 0x793, /* PCMPEQWrm */ + 0x794, /* PCMPEQWrr */ +/* Table2948 */ + 0x78f, /* PCMPEQDrm */ + 0x790, /* PCMPEQDrr */ +/* Table2950 */ + 0x0, /* */ + 0x37c, /* EXTRQI */ +/* Table2952 */ + 0x0, /* */ + 0x37b, /* EXTRQ */ +/* Table2954 */ + 0x3c2, /* HADDPDrm */ + 0x3c3, /* HADDPDrr */ +/* Table2956 */ + 0x3c7, /* HSUBPDrm */ + 0x3c8, /* HSUBPDrr */ +/* Table2958 */ + 0x689, /* MOVPDI2DImr */ + 0x68a, /* MOVPDI2DIrr */ +/* Table2960 */ + 0x66d, /* MOVDQAmr */ + 0x670, /* MOVDQArr_REV */ +/* Table2962 */ + 0x476, /* JO_2 */ +/* Table2963 */ + 0x46d, /* JNO_2 */ +/* Table2964 */ + 0x447, /* JB_2 */ +/* Table2965 */ + 0x43e, /* JAE_2 */ +/* Table2966 */ + 0x44c, /* JE_2 */ +/* Table2967 */ + 0x46a, /* JNE_2 */ +/* Table2968 */ + 0x444, /* JBE_2 */ +/* Table2969 */ + 0x441, /* JA_2 */ +/* Table2970 */ + 0x47d, /* JS_2 */ +/* Table2971 */ + 0x473, /* JNS_2 */ +/* Table2972 */ + 0x479, /* JP_2 */ +/* Table2973 */ + 0x470, /* JNP_2 */ +/* Table2974 */ + 0x458, /* JL_2 */ +/* Table2975 */ + 0x44f, /* JGE_2 */ +/* Table2976 */ + 0x455, /* JLE_2 */ +/* Table2977 */ + 0x452, /* JG_2 */ +/* Table2978 */ + 0x8cf, /* PUSHFS16 */ +/* Table2979 */ + 0x854, /* POPFS16 */ +/* Table2980 */ + 0x1ad, /* BT16mr */ + 0x1af, /* BT16rr */ +/* Table2982 */ + 0xa20, /* SHLD16mri8 */ + 0xa22, /* SHLD16rri8 */ +/* Table2984 */ + 0xa1f, /* SHLD16mrCL */ + 0xa21, /* SHLD16rrCL */ +/* Table2986 */ + 0x8d2, /* PUSHGS16 */ +/* Table2987 */ + 0x857, /* POPGS16 */ +/* Table2988 */ + 0x1d1, /* BTS16mr */ + 0x1d3, /* BTS16rr */ +/* Table2990 */ + 0xa48, /* SHRD16mri8 */ + 0xa4a, /* SHRD16rri8 */ +/* Table2992 */ + 0xa47, /* SHRD16mrCL */ + 0xa49, /* SHRD16rrCL */ +/* Table2994 */ + 0x3b6, /* FXSAVE */ + 0x3b4, /* FXRSTOR */ + 0x4ca, /* LDMXCSR */ + 0xa82, /* STMXCSR */ + 0x0, /* */ + 0x0, /* */ + 0x200, /* CLWB */ + 0x1fb, /* CLFLUSHOPT */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0xb1b, /* TPAUSE */ + 0x0, /* */ +/* Table3010 */ + 0x3e1, /* IMUL16rm */ + 0x3e4, /* IMUL16rr */ +/* Table3012 */ + 0x2c0, /* CMPXCHG16rm */ + 0x2c1, /* CMPXCHG16rr */ +/* Table3014 */ + 0x50e, /* LSS16rm */ + 0x0, /* */ +/* Table3016 */ + 0x1c5, /* BTR16mr */ + 0x1c7, /* BTR16rr */ +/* Table3018 */ + 0x4e8, /* LFS16rm */ + 0x0, /* */ +/* Table3020 */ + 0x4ee, /* LGS16rm */ + 0x0, /* */ +/* Table3022 */ + 0x6be, /* MOVZX16rm8 */ + 0x6c0, /* MOVZX16rr8 */ +/* Table3024 */ + 0x6bd, /* MOVZX16rm16 */ + 0x6bf, /* MOVZX16rr16 */ +/* Table3026 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x1ac, /* BT16mi8 */ + 0x1d0, /* BTS16mi8 */ + 0x1c4, /* BTR16mi8 */ + 0x1b8, /* BTC16mi8 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x1ae, /* BT16ri8 */ + 0x1d2, /* BTS16ri8 */ + 0x1c6, /* BTR16ri8 */ + 0x1ba, /* BTC16ri8 */ +/* Table3042 */ + 0x1b9, /* BTC16mr */ + 0x1bb, /* BTC16rr */ +/* Table3044 */ + 0x19d, /* BSF16rm */ + 0x19e, /* BSF16rr */ +/* Table3046 */ + 0x1a3, /* BSR16rm */ + 0x1a4, /* BSR16rr */ +/* Table3048 */ + 0x6a5, /* MOVSX16rm8 */ + 0x6a7, /* MOVSX16rr8 */ +/* Table3050 */ + 0x6a4, /* MOVSX16rm16 */ + 0x6a6, /* MOVSX16rr16 */ +/* Table3052 */ + 0x3b5d, /* XADD16rm */ + 0x3b5e, /* XADD16rr */ +/* Table3054 */ + 0x2a7, /* CMPPDrmi */ + 0x2a9, /* CMPPDrri */ +/* Table3056 */ + 0x7f5, /* PINSRWrm */ + 0x7f6, /* PINSRWrr */ +/* Table3058 */ + 0x0, /* */ + 0x7b5, /* PEXTRWrr */ +/* Table3060 */ + 0xa57, /* SHUFPDrmi */ + 0xa58, /* SHUFPDrri */ +/* Table3062 */ + 0x0, /* */ + 0x2c6, /* CMPXCHG8B */ + 0x0, /* */ + 0x3ba6, /* XRSTORS */ + 0x3baa, /* XSAVEC */ + 0x3bae, /* XSAVES */ + 0x1c96, /* VMCLEARm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x91a, /* RDRAND16r */ + 0x91d, /* RDSEED16r */ +/* Table3078 */ + 0x1a9, /* BSWAP16r_BAD */ +/* Table3079 */ + 0xf2, /* ADDSUBPDrm */ + 0xf3, /* ADDSUBPDrr */ +/* Table3081 */ + 0x88d, /* PSRLWrm */ + 0x88e, /* PSRLWrr */ +/* Table3083 */ + 0x887, /* PSRLDrm */ + 0x888, /* PSRLDrr */ +/* Table3085 */ + 0x88a, /* PSRLQrm */ + 0x88b, /* PSRLQrr */ +/* Table3087 */ + 0x76e, /* PADDQrm */ + 0x76f, /* PADDQrr */ +/* Table3089 */ + 0x838, /* PMULLWrm */ + 0x839, /* PMULLWrr */ +/* Table3091 */ + 0x68b, /* MOVPQI2QImr */ + 0x68c, /* MOVPQI2QIrr */ +/* Table3093 */ + 0x0, /* */ + 0x813, /* PMOVMSKBrr */ +/* Table3095 */ + 0x899, /* PSUBUSBrm */ + 0x89a, /* PSUBUSBrr */ +/* Table3097 */ + 0x89b, /* PSUBUSWrm */ + 0x89c, /* PSUBUSWrr */ +/* Table3099 */ + 0x80d, /* PMINUBrm */ + 0x80e, /* PMINUBrr */ +/* Table3101 */ + 0x77e, /* PANDrm */ + 0x77f, /* PANDrr */ +/* Table3103 */ + 0x774, /* PADDUSBrm */ + 0x775, /* PADDUSBrr */ +/* Table3105 */ + 0x776, /* PADDUSWrm */ + 0x777, /* PADDUSWrr */ +/* Table3107 */ + 0x801, /* PMAXUBrm */ + 0x802, /* PMAXUBrr */ +/* Table3109 */ + 0x77c, /* PANDNrm */ + 0x77d, /* PANDNrr */ +/* Table3111 */ + 0x781, /* PAVGBrm */ + 0x782, /* PAVGBrr */ +/* Table3113 */ + 0x883, /* PSRAWrm */ + 0x884, /* PSRAWrr */ +/* Table3115 */ + 0x880, /* PSRADrm */ + 0x881, /* PSRADrr */ +/* Table3117 */ + 0x785, /* PAVGWrm */ + 0x786, /* PAVGWrr */ +/* Table3119 */ + 0x832, /* PMULHUWrm */ + 0x833, /* PMULHUWrr */ +/* Table3121 */ + 0x834, /* PMULHWrm */ + 0x835, /* PMULHWrr */ +/* Table3123 */ + 0x311, /* CVTTPD2DQrm */ + 0x312, /* CVTTPD2DQrr */ +/* Table3125 */ + 0x682, /* MOVNTDQmr */ + 0x0, /* */ +/* Table3127 */ + 0x895, /* PSUBSBrm */ + 0x896, /* PSUBSBrr */ +/* Table3129 */ + 0x897, /* PSUBSWrm */ + 0x898, /* PSUBSWrr */ +/* Table3131 */ + 0x80b, /* PMINSWrm */ + 0x80c, /* PMINSWrr */ +/* Table3133 */ + 0x85c, /* PORrm */ + 0x85d, /* PORrr */ +/* Table3135 */ + 0x770, /* PADDSBrm */ + 0x771, /* PADDSBrr */ +/* Table3137 */ + 0x772, /* PADDSWrm */ + 0x773, /* PADDSWrr */ +/* Table3139 */ + 0x7ff, /* PMAXSWrm */ + 0x800, /* PMAXSWrr */ +/* Table3141 */ + 0x8d9, /* PXORrm */ + 0x8da, /* PXORrr */ +/* Table3143 */ + 0x87d, /* PSLLWrm */ + 0x87e, /* PSLLWrr */ +/* Table3145 */ + 0x877, /* PSLLDrm */ + 0x878, /* PSLLDrr */ +/* Table3147 */ + 0x87a, /* PSLLQrm */ + 0x87b, /* PSLLQrr */ +/* Table3149 */ + 0x83a, /* PMULUDQrm */ + 0x83b, /* PMULUDQrr */ +/* Table3151 */ + 0x7f9, /* PMADDWDrm */ + 0x7fa, /* PMADDWDrr */ +/* Table3153 */ + 0x865, /* PSADBWrm */ + 0x866, /* PSADBWrr */ +/* Table3155 */ + 0x0, /* */ + 0x521, /* MASKMOVDQU */ +/* Table3157 */ + 0x88f, /* PSUBBrm */ + 0x890, /* PSUBBrr */ +/* Table3159 */ + 0x89d, /* PSUBWrm */ + 0x89e, /* PSUBWrr */ +/* Table3161 */ + 0x891, /* PSUBDrm */ + 0x892, /* PSUBDrr */ +/* Table3163 */ + 0x893, /* PSUBQrm */ + 0x894, /* PSUBQrr */ +/* Table3165 */ + 0x76a, /* PADDBrm */ + 0x76b, /* PADDBrr */ +/* Table3167 */ + 0x778, /* PADDWrm */ + 0x779, /* PADDWrr */ +/* Table3169 */ + 0x76c, /* PADDDrm */ + 0x76d, /* PADDDrr */ +/* Table3171 */ + 0x67c, /* MOVLPDrm */ + 0x675, /* MOVHLPSrr */ +/* Table3173 */ + 0x677, /* MOVHPDrm */ + 0x67a, /* MOVLHPSrr */ +/* Table3175 */ + 0x1f78, /* VMREAD32mr */ + 0x37c, /* EXTRQI */ +/* Table3177 */ + 0x1fe3, /* VMWRITE32rm */ + 0x37b, /* EXTRQ */ +/* Table3179 */ + 0x3b6, /* FXSAVE */ + 0x3b4, /* FXRSTOR */ + 0x4ca, /* LDMXCSR */ + 0xa82, /* STMXCSR */ + 0x3ba8, /* XSAVE */ + 0x3ba4, /* XRSTOR */ + 0x200, /* CLWB */ + 0x1fb, /* CLFLUSHOPT */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x4e7, /* LFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0x9f5, /* SFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table3251 */ + 0x0, /* */ + 0x2c6, /* CMPXCHG8B */ + 0x0, /* */ + 0x3ba6, /* XRSTORS */ + 0x3baa, /* XSAVEC */ + 0x3bae, /* XSAVES */ + 0x1c96, /* VMCLEARm */ + 0x1f77, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x91a, /* RDRAND16r */ + 0x91d, /* RDSEED16r */ +/* Table3267 */ + 0x692, /* MOVSDrm */ + 0x693, /* MOVSDrr */ +/* Table3269 */ + 0x691, /* MOVSDmr */ + 0x694, /* MOVSDrr_REV */ +/* Table3271 */ + 0x662, /* MOVDDUPrm */ + 0x663, /* MOVDDUPrr */ +/* Table3273 */ + 0x18d, /* BNDCU32rm */ + 0x18e, /* BNDCU32rr */ +/* Table3275 */ + 0x189, /* BNDCN32rm */ + 0x18a, /* BNDCN32rr */ +/* Table3277 */ + 0x2f9, /* CVTSI2SDrm */ + 0x2fb, /* CVTSI2SDrr */ +/* Table3279 */ + 0x687, /* MOVNTSD */ + 0x0, /* */ +/* Table3281 */ + 0x319, /* CVTTSD2SIrm */ + 0x31b, /* CVTTSD2SIrr */ +/* Table3283 */ + 0x2f3, /* CVTSD2SIrm_Int */ + 0x2f4, /* CVTSD2SIrr_Int */ +/* Table3285 */ + 0xa71, /* SQRTSDm */ + 0xa73, /* SQRTSDr */ +/* Table3287 */ + 0xea, /* ADDSDrm */ + 0xec, /* ADDSDrr */ +/* Table3289 */ + 0x6d9, /* MULSDrm */ + 0x6db, /* MULSDrr */ +/* Table3291 */ + 0x2f5, /* CVTSD2SSrm */ + 0x2f7, /* CVTSD2SSrr */ +/* Table3293 */ + 0xad7, /* SUBSDrm */ + 0xad9, /* SUBSDrr */ +/* Table3295 */ + 0x544, /* MINSDrm */ + 0x546, /* MINSDrr */ +/* Table3297 */ + 0x352, /* DIVSDrm */ + 0x354, /* DIVSDrr */ +/* Table3299 */ + 0x52f, /* MAXSDrm */ + 0x531, /* MAXSDrr */ +/* Table3301 */ + 0x86d, /* PSHUFLWmi */ + 0x86e, /* PSHUFLWri */ +/* Table3303 */ + 0x0, /* */ + 0x40f, /* INSERTQI */ +/* Table3305 */ + 0x0, /* */ + 0x40e, /* INSERTQ */ +/* Table3307 */ + 0x3c4, /* HADDPSrm */ + 0x3c5, /* HADDPSrr */ +/* Table3309 */ + 0x3c9, /* HSUBPSrm */ + 0x3ca, /* HSUBPSrr */ +/* Table3311 */ + 0x3b6, /* FXSAVE */ + 0x3b4, /* FXRSTOR */ + 0x4ca, /* LDMXCSR */ + 0xa82, /* STMXCSR */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0xb43, /* UMWAIT */ + 0x0, /* */ +/* Table3327 */ + 0x2b0, /* CMPSDrm */ + 0x2b3, /* CMPSDrr */ +/* Table3329 */ + 0x0, /* */ + 0x2c6, /* CMPXCHG8B */ + 0x0, /* */ + 0x3ba6, /* XRSTORS */ + 0x3baa, /* XSAVEC */ + 0x3bae, /* XSAVES */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table3345 */ + 0xf4, /* ADDSUBPSrm */ + 0xf5, /* ADDSUBPSrr */ +/* Table3347 */ + 0x0, /* */ + 0x563, /* MMX_MOVDQ2Qrr */ +/* Table3349 */ + 0x2e9, /* CVTPD2DQrm */ + 0x2ea, /* CVTPD2DQrr */ +/* Table3351 */ + 0x4c9, /* LDDQUrm */ + 0x0, /* */ +/* Table3353 */ + 0x9f7, /* SGDT32m */ + 0xa5c, /* SIDT32m */ + 0x4ec, /* LGDT32m */ + 0x4f2, /* LIDT32m */ + 0xa69, /* SMSW16m */ + 0x974, /* RSTORSSP */ + 0x4f8, /* LMSW16m */ + 0x419, /* INVLPG */ + 0x375, /* ENCLV */ + 0x1c95, /* VMCALL */ + 0x1d40, /* VMLAUNCH */ + 0x1f7c, /* VMRESUME */ + 0x1fe7, /* VMXOFF */ + 0x7a5, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x609, /* MONITORrrr */ + 0x6fb, /* MWAITrr */ + 0x1f6, /* CLAC */ + 0xa7d, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x373, /* ENCLS */ + 0x3b79, /* XGETBV */ + 0x3bb0, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x1c97, /* VMFUNC */ + 0x3b78, /* XEND */ + 0x3bb4, /* XTEST */ + 0x374, /* ENCLU */ + 0x1f7d, /* VMRUN32 */ + 0x1d43, /* VMMCALL */ + 0x1d41, /* VMLOAD32 */ + 0x1f7f, /* VMSAVE32 */ + 0xa80, /* STGI */ + 0x1fc, /* CLGI */ + 0xa62, /* SKINIT */ + 0x41a, /* INVLPGA32 */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0x9f2, /* SETSSBSY */ + 0x0, /* */ + 0x9ab, /* SAVEPREVSSP */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x918, /* RDPKRUr */ + 0x3b56, /* WRPKRUr */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0xaf4, /* SWAPGS */ + 0x923, /* RDTSCP */ + 0x608, /* MONITORXrrr */ + 0x6fa, /* MWAITXrrr */ + 0x201, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table3425 */ + 0x3b50, /* WBNOINVD */ +/* Table3426 */ + 0x6a0, /* MOVSSrm */ + 0x6a1, /* MOVSSrr */ +/* Table3428 */ + 0x69f, /* MOVSSmr */ + 0x6a2, /* MOVSSrr_REV */ +/* Table3430 */ + 0x69a, /* MOVSLDUPrm */ + 0x69b, /* MOVSLDUPrr */ +/* Table3432 */ + 0x697, /* MOVSHDUPrm */ + 0x698, /* MOVSHDUPrr */ +/* Table3434 */ + 0x185, /* BNDCL32rm */ + 0x186, /* BNDCL32rr */ +/* Table3436 */ + 0x192, /* BNDMK32rm */ + 0x0, /* */ +/* Table3438 */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x920, /* RDSSPD */ + 0x920, /* RDSSPD */ + 0x920, /* RDSSPD */ + 0x920, /* RDSSPD */ + 0x920, /* RDSSPD */ + 0x920, /* RDSSPD */ + 0x920, /* RDSSPD */ + 0x920, /* RDSSPD */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x377, /* ENDBR64 */ + 0x376, /* ENDBR32 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table3510 */ + 0x2fd, /* CVTSI2SSrm */ + 0x2ff, /* CVTSI2SSrr */ +/* Table3512 */ + 0x688, /* MOVNTSS */ + 0x0, /* */ +/* Table3514 */ + 0x321, /* CVTTSS2SIrm */ + 0x323, /* CVTTSS2SIrr */ +/* Table3516 */ + 0x30f, /* CVTSS2SIrm_Int */ + 0x310, /* CVTSS2SIrr_Int */ +/* Table3518 */ + 0xa75, /* SQRTSSm */ + 0xa77, /* SQRTSSr */ +/* Table3520 */ + 0x970, /* RSQRTSSm */ + 0x972, /* RSQRTSSr */ +/* Table3522 */ + 0x8f5, /* RCPSSm */ + 0x8f7, /* RCPSSr */ +/* Table3524 */ + 0xee, /* ADDSSrm */ + 0xf0, /* ADDSSrr */ +/* Table3526 */ + 0x6dd, /* MULSSrm */ + 0x6df, /* MULSSrr */ +/* Table3528 */ + 0x309, /* CVTSS2SDrm */ + 0x30b, /* CVTSS2SDrr */ +/* Table3530 */ + 0x313, /* CVTTPS2DQrm */ + 0x314, /* CVTTPS2DQrr */ +/* Table3532 */ + 0xadb, /* SUBSSrm */ + 0xadd, /* SUBSSrr */ +/* Table3534 */ + 0x548, /* MINSSrm */ + 0x54a, /* MINSSrr */ +/* Table3536 */ + 0x356, /* DIVSSrm */ + 0x358, /* DIVSSrr */ +/* Table3538 */ + 0x533, /* MAXSSrm */ + 0x535, /* MAXSSrr */ +/* Table3540 */ + 0x672, /* MOVDQUrm */ + 0x673, /* MOVDQUrr */ +/* Table3542 */ + 0x86b, /* PSHUFHWmi */ + 0x86c, /* PSHUFHWri */ +/* Table3544 */ + 0x68f, /* MOVQI2PQIrm */ + 0x6bc, /* MOVZPQILo2PQIrr */ +/* Table3546 */ + 0x671, /* MOVDQUmr */ + 0x674, /* MOVDQUrr_REV */ +/* Table3548 */ + 0x3b6, /* FXSAVE */ + 0x3b4, /* FXRSTOR */ + 0x4ca, /* LDMXCSR */ + 0xa82, /* STMXCSR */ + 0x8a5, /* PTWRITEm */ + 0x0, /* */ + 0x1fe, /* CLRSSBSY */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x8a6, /* PTWRITEr */ + 0x409, /* INCSSPD */ + 0xb41, /* UMONITOR32 */ + 0x0, /* */ +/* Table3564 */ + 0x849, /* POPCNT32rm */ + 0x84a, /* POPCNT32rr */ +/* Table3566 */ + 0xb22, /* TZCNT32rm */ + 0xb23, /* TZCNT32rr */ +/* Table3568 */ + 0x51d, /* LZCNT32rm */ + 0x51e, /* LZCNT32rr */ +/* Table3570 */ + 0x2b8, /* CMPSSrm */ + 0x2bb, /* CMPSSrr */ +/* Table3572 */ + 0x0, /* */ + 0x2c6, /* CMPXCHG8B */ + 0x0, /* */ + 0x3ba6, /* XRSTORS */ + 0x3baa, /* XSAVEC */ + 0x3bae, /* XSAVES */ + 0x1fe8, /* VMXON */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x916, /* RDPID32 */ +/* Table3588 */ + 0x0, /* */ + 0x566, /* MMX_MOVQ2DQrr */ +/* Table3590 */ + 0x2e5, /* CVTDQ2PDrm */ + 0x2e6, /* CVTDQ2PDrr */ +/* Table3592 */ + 0x847, /* POPCNT16rm */ + 0x848, /* POPCNT16rr */ +/* Table3594 */ + 0xb20, /* TZCNT16rm */ + 0xb21, /* TZCNT16rr */ +/* Table3596 */ + 0x51b, /* LZCNT16rm */ + 0x51c, /* LZCNT16rr */ +/* Table3598 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0xb40, /* UMONITOR16 */ + 0x0, /* */ +/* Table3614 */ + 0xa63, /* SLDT16m */ + 0xa8a, /* STRm */ + 0x4f4, /* LLDT16m */ + 0x511, /* LTRm */ + 0x1282, /* VERRm */ + 0x1284, /* VERWm */ + 0x0, /* */ + 0x0, /* */ + 0xa66, /* SLDT64r */ + 0xa89, /* STR64r */ + 0x4f5, /* LLDT16r */ + 0x512, /* LTRr */ + 0x1283, /* VERRr */ + 0x1285, /* VERWr */ + 0x0, /* */ + 0x0, /* */ +/* Table3630 */ + 0x9f8, /* SGDT64m */ + 0xa5d, /* SIDT64m */ + 0x4ed, /* LGDT64m */ + 0x4f3, /* LIDT64m */ + 0xa69, /* SMSW16m */ + 0x0, /* */ + 0x4f8, /* LMSW16m */ + 0x419, /* INVLPG */ + 0x375, /* ENCLV */ + 0x1c95, /* VMCALL */ + 0x1d40, /* VMLAUNCH */ + 0x1f7c, /* VMRESUME */ + 0x1fe7, /* VMXOFF */ + 0x7a5, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x609, /* MONITORrrr */ + 0x6fb, /* MWAITrr */ + 0x1f6, /* CLAC */ + 0xa7d, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x373, /* ENCLS */ + 0x3b79, /* XGETBV */ + 0x3bb0, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x1c97, /* VMFUNC */ + 0x3b78, /* XEND */ + 0x3bb4, /* XTEST */ + 0x374, /* ENCLU */ + 0x1f7e, /* VMRUN64 */ + 0x1d43, /* VMMCALL */ + 0x1d42, /* VMLOAD64 */ + 0x1f80, /* VMSAVE64 */ + 0xa80, /* STGI */ + 0x1fc, /* CLGI */ + 0xa62, /* SKINIT */ + 0x41b, /* INVLPGA64 */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x918, /* RDPKRUr */ + 0x3b56, /* WRPKRUr */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0xaf4, /* SWAPGS */ + 0x923, /* RDTSCP */ + 0x608, /* MONITORXrrr */ + 0x6fa, /* MWAITXrrr */ + 0x201, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table3702 */ + 0x4c7, /* LAR64rm */ + 0x4c8, /* LAR64rr */ +/* Table3704 */ + 0x50c, /* LSL64rm */ + 0x50d, /* LSL64rr */ +/* Table3706 */ + 0xafa, /* SYSRET64 */ +/* Table3707 */ + 0x71b, /* NOOPQ */ + 0x71c, /* NOOPQr */ +/* Table3709 */ + 0xaf8, /* SYSEXIT64 */ +/* Table3710 */ + 0x271, /* CMOVO64rm */ + 0x272, /* CMOVO64rr */ +/* Table3712 */ + 0x25b, /* CMOVNO64rm */ + 0x25c, /* CMOVNO64rr */ +/* Table3714 */ + 0x213, /* CMOVB64rm */ + 0x214, /* CMOVB64rr */ +/* Table3716 */ + 0x20d, /* CMOVAE64rm */ + 0x20e, /* CMOVAE64rr */ +/* Table3718 */ + 0x227, /* CMOVE64rm */ + 0x228, /* CMOVE64rr */ +/* Table3720 */ + 0x251, /* CMOVNE64rm */ + 0x252, /* CMOVNE64rr */ +/* Table3722 */ + 0x219, /* CMOVBE64rm */ + 0x21a, /* CMOVBE64rr */ +/* Table3724 */ + 0x207, /* CMOVA64rm */ + 0x208, /* CMOVA64rr */ +/* Table3726 */ + 0x281, /* CMOVS64rm */ + 0x282, /* CMOVS64rr */ +/* Table3728 */ + 0x26b, /* CMOVNS64rm */ + 0x26c, /* CMOVNS64rr */ +/* Table3730 */ + 0x277, /* CMOVP64rm */ + 0x278, /* CMOVP64rr */ +/* Table3732 */ + 0x261, /* CMOVNP64rm */ + 0x262, /* CMOVNP64rr */ +/* Table3734 */ + 0x23d, /* CMOVL64rm */ + 0x23e, /* CMOVL64rr */ +/* Table3736 */ + 0x237, /* CMOVGE64rm */ + 0x238, /* CMOVGE64rr */ +/* Table3738 */ + 0x243, /* CMOVLE64rm */ + 0x244, /* CMOVLE64rr */ +/* Table3740 */ + 0x231, /* CMOVG64rm */ + 0x232, /* CMOVG64rr */ +/* Table3742 */ + 0x561, /* MMX_MOVD64to64rm */ + 0x562, /* MMX_MOVD64to64rr */ +/* Table3744 */ + 0x55b, /* MMX_MOVD64from64rm */ + 0x55c, /* MMX_MOVD64from64rr */ +/* Table3746 */ + 0x1b5, /* BT64mr */ + 0x1b7, /* BT64rr */ +/* Table3748 */ + 0xa28, /* SHLD64mri8 */ + 0xa2a, /* SHLD64rri8 */ +/* Table3750 */ + 0xa27, /* SHLD64mrCL */ + 0xa29, /* SHLD64rrCL */ +/* Table3752 */ + 0x1d9, /* BTS64mr */ + 0x1db, /* BTS64rr */ +/* Table3754 */ + 0xa50, /* SHRD64mri8 */ + 0xa52, /* SHRD64rri8 */ +/* Table3756 */ + 0xa4f, /* SHRD64mrCL */ + 0xa51, /* SHRD64rrCL */ +/* Table3758 */ + 0x3b7, /* FXSAVE64 */ + 0x3b5, /* FXRSTOR64 */ + 0x4ca, /* LDMXCSR */ + 0xa82, /* STMXCSR */ + 0x3ba9, /* XSAVE64 */ + 0x3ba5, /* XRSTOR64 */ + 0x3bad, /* XSAVEOPT64 */ + 0x1fa, /* CLFLUSH */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x4e7, /* LFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x537, /* MFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x9f5, /* SFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table3830 */ + 0x3f1, /* IMUL64rm */ + 0x3f4, /* IMUL64rr */ +/* Table3832 */ + 0x2c4, /* CMPXCHG64rm */ + 0x2c5, /* CMPXCHG64rr */ +/* Table3834 */ + 0x510, /* LSS64rm */ + 0x0, /* */ +/* Table3836 */ + 0x1cd, /* BTR64mr */ + 0x1cf, /* BTR64rr */ +/* Table3838 */ + 0x4ea, /* LFS64rm */ + 0x0, /* */ +/* Table3840 */ + 0x4f0, /* LGS64rm */ + 0x0, /* */ +/* Table3842 */ + 0x6c8, /* MOVZX64rm8 */ + 0x6ca, /* MOVZX64rr8 */ +/* Table3844 */ + 0x6c7, /* MOVZX64rm16 */ + 0x6c9, /* MOVZX64rr16 */ +/* Table3846 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x1b4, /* BT64mi8 */ + 0x1d8, /* BTS64mi8 */ + 0x1cc, /* BTR64mi8 */ + 0x1c0, /* BTC64mi8 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x1b6, /* BT64ri8 */ + 0x1da, /* BTS64ri8 */ + 0x1ce, /* BTR64ri8 */ + 0x1c2, /* BTC64ri8 */ +/* Table3862 */ + 0x1c1, /* BTC64mr */ + 0x1c3, /* BTC64rr */ +/* Table3864 */ + 0x1a1, /* BSF64rm */ + 0x1a2, /* BSF64rr */ +/* Table3866 */ + 0x1a7, /* BSR64rm */ + 0x1a8, /* BSR64rr */ +/* Table3868 */ + 0x6b0, /* MOVSX64rm8 */ + 0x6b3, /* MOVSX64rr8 */ +/* Table3870 */ + 0x6ae, /* MOVSX64rm16 */ + 0x6b1, /* MOVSX64rr16 */ +/* Table3872 */ + 0x3b61, /* XADD64rm */ + 0x3b62, /* XADD64rr */ +/* Table3874 */ + 0x683, /* MOVNTI_64mr */ + 0x0, /* */ +/* Table3876 */ + 0x0, /* */ + 0x2bf, /* CMPXCHG16B */ + 0x0, /* */ + 0x3ba7, /* XRSTORS64 */ + 0x3bab, /* XSAVEC64 */ + 0x3baf, /* XSAVES64 */ + 0x1f76, /* VMPTRLDm */ + 0x1f77, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x91c, /* RDRAND64r */ + 0x91f, /* RDSEED64r */ +/* Table3892 */ + 0x1ab, /* BSWAP64r */ +/* Table3893 */ + 0x197, /* BNDMOV64rm */ + 0x198, /* BNDMOVrr */ +/* Table3895 */ + 0x196, /* BNDMOV64mr */ + 0x199, /* BNDMOVrr_REV */ +/* Table3897 */ + 0x1f7a, /* VMREAD64mr */ + 0x37c, /* EXTRQI */ +/* Table3899 */ + 0x1fe5, /* VMWRITE64rm */ + 0x37b, /* EXTRQ */ +/* Table3901 */ + 0x3b7, /* FXSAVE64 */ + 0x3b5, /* FXRSTOR64 */ + 0x4ca, /* LDMXCSR */ + 0xa82, /* STMXCSR */ + 0x3ba9, /* XSAVE64 */ + 0x3ba5, /* XRSTOR64 */ + 0x3bad, /* XSAVEOPT64 */ + 0x1fb, /* CLFLUSHOPT */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x4e7, /* LFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0x9f5, /* SFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table3973 */ + 0x0, /* */ + 0x2bf, /* CMPXCHG16B */ + 0x0, /* */ + 0x3ba7, /* XRSTORS64 */ + 0x3bab, /* XSAVEC64 */ + 0x3baf, /* XSAVES64 */ + 0x1c96, /* VMCLEARm */ + 0x1f77, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x91c, /* RDRAND64r */ + 0x91f, /* RDSEED64r */ +/* Table3989 */ + 0x0, /* */ + 0x522, /* MASKMOVDQU64 */ +/* Table3991 */ + 0x9f8, /* SGDT64m */ + 0xa5d, /* SIDT64m */ + 0x4ed, /* LGDT64m */ + 0x4f3, /* LIDT64m */ + 0xa69, /* SMSW16m */ + 0x0, /* */ + 0x4f8, /* LMSW16m */ + 0x419, /* INVLPG */ + 0x375, /* ENCLV */ + 0x1c95, /* VMCALL */ + 0x1d40, /* VMLAUNCH */ + 0x1f7c, /* VMRESUME */ + 0x1fe7, /* VMXOFF */ + 0x7a5, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x609, /* MONITORrrr */ + 0x6fb, /* MWAITrr */ + 0x1f6, /* CLAC */ + 0xa7d, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x373, /* ENCLS */ + 0x3b79, /* XGETBV */ + 0x3bb0, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x1c97, /* VMFUNC */ + 0x3b78, /* XEND */ + 0x3bb4, /* XTEST */ + 0x374, /* ENCLU */ + 0x1f7e, /* VMRUN64 */ + 0x1d43, /* VMMCALL */ + 0x1d42, /* VMLOAD64 */ + 0x1f80, /* VMSAVE64 */ + 0xa80, /* STGI */ + 0x1fc, /* CLGI */ + 0xa62, /* SKINIT */ + 0x41b, /* INVLPGA64 */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0xa6a, /* SMSW16r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x918, /* RDPKRUr */ + 0x3b56, /* WRPKRUr */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0xaf4, /* SWAPGS */ + 0x923, /* RDTSCP */ + 0x608, /* MONITORXrrr */ + 0x6fa, /* MWAITXrrr */ + 0x201, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table4063 */ + 0x18f, /* BNDCU64rm */ + 0x190, /* BNDCU64rr */ +/* Table4065 */ + 0x18b, /* BNDCN64rm */ + 0x18c, /* BNDCN64rr */ +/* Table4067 */ + 0x9f8, /* SGDT64m */ + 0xa5d, /* SIDT64m */ + 0x4ed, /* LGDT64m */ + 0x4f3, /* LIDT64m */ + 0xa69, /* SMSW16m */ + 0x974, /* RSTORSSP */ + 0x4f8, /* LMSW16m */ + 0x419, /* INVLPG */ + 0x375, /* ENCLV */ + 0x1c95, /* VMCALL */ + 0x1d40, /* VMLAUNCH */ + 0x1f7c, /* VMRESUME */ + 0x1fe7, /* VMXOFF */ + 0x7a5, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x609, /* MONITORrrr */ + 0x6fb, /* MWAITrr */ + 0x1f6, /* CLAC */ + 0xa7d, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x373, /* ENCLS */ + 0x3b79, /* XGETBV */ + 0x3bb0, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x1c97, /* VMFUNC */ + 0x3b78, /* XEND */ + 0x3bb4, /* XTEST */ + 0x374, /* ENCLU */ + 0x1f7e, /* VMRUN64 */ + 0x1d43, /* VMMCALL */ + 0x1d42, /* VMLOAD64 */ + 0x1f80, /* VMSAVE64 */ + 0xa80, /* STGI */ + 0x1fc, /* CLGI */ + 0xa62, /* SKINIT */ + 0x41b, /* INVLPGA64 */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0xa6b, /* SMSW32r */ + 0x9f2, /* SETSSBSY */ + 0x0, /* */ + 0x9ab, /* SAVEPREVSSP */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x918, /* RDPKRUr */ + 0x3b56, /* WRPKRUr */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0xaf4, /* SWAPGS */ + 0x923, /* RDTSCP */ + 0x608, /* MONITORXrrr */ + 0x6fa, /* MWAITXrrr */ + 0x201, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table4139 */ + 0x187, /* BNDCL64rm */ + 0x188, /* BNDCL64rr */ +/* Table4141 */ + 0x193, /* BNDMK64rm */ + 0x0, /* */ +/* Table4143 */ + 0x3b6, /* FXSAVE */ + 0x3b4, /* FXRSTOR */ + 0x4ca, /* LDMXCSR */ + 0xa82, /* STMXCSR */ + 0x8a5, /* PTWRITEm */ + 0x0, /* */ + 0x1fe, /* CLRSSBSY */ + 0x0, /* */ + 0x911, /* RDFSBASE */ + 0x913, /* RDGSBASE */ + 0x3b51, /* WRFSBASE */ + 0x3b53, /* WRGSBASE */ + 0x8a6, /* PTWRITEr */ + 0x409, /* INCSSPD */ + 0xb42, /* UMONITOR64 */ + 0x0, /* */ +/* Table4159 */ + 0x0, /* */ + 0x2c6, /* CMPXCHG8B */ + 0x0, /* */ + 0x3ba6, /* XRSTORS */ + 0x3baa, /* XSAVEC */ + 0x3bae, /* XSAVES */ + 0x1fe8, /* VMXON */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x917, /* RDPID64 */ +/* Table4175 */ + 0x3b6, /* FXSAVE */ + 0x3b4, /* FXRSTOR */ + 0x4ca, /* LDMXCSR */ + 0xa82, /* STMXCSR */ + 0x8a5, /* PTWRITEm */ + 0x0, /* */ + 0x1fe, /* CLRSSBSY */ + 0x0, /* */ + 0x911, /* RDFSBASE */ + 0x913, /* RDGSBASE */ + 0x3b51, /* WRFSBASE */ + 0x3b53, /* WRGSBASE */ + 0x8a6, /* PTWRITEr */ + 0x409, /* INCSSPD */ + 0xb41, /* UMONITOR32 */ + 0x0, /* */ +/* Table4191 */ + 0x9f8, /* SGDT64m */ + 0xa5d, /* SIDT64m */ + 0x4ed, /* LGDT64m */ + 0x4f3, /* LIDT64m */ + 0xa69, /* SMSW16m */ + 0x974, /* RSTORSSP */ + 0x4f8, /* LMSW16m */ + 0x419, /* INVLPG */ + 0x375, /* ENCLV */ + 0x1c95, /* VMCALL */ + 0x1d40, /* VMLAUNCH */ + 0x1f7c, /* VMRESUME */ + 0x1fe7, /* VMXOFF */ + 0x7a5, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x609, /* MONITORrrr */ + 0x6fb, /* MWAITrr */ + 0x1f6, /* CLAC */ + 0xa7d, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x373, /* ENCLS */ + 0x3b79, /* XGETBV */ + 0x3bb0, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x1c97, /* VMFUNC */ + 0x3b78, /* XEND */ + 0x3bb4, /* XTEST */ + 0x374, /* ENCLU */ + 0x1f7e, /* VMRUN64 */ + 0x1d43, /* VMMCALL */ + 0x1d42, /* VMLOAD64 */ + 0x1f80, /* VMSAVE64 */ + 0xa80, /* STGI */ + 0x1fc, /* CLGI */ + 0xa62, /* SKINIT */ + 0x41b, /* INVLPGA64 */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0xa6c, /* SMSW64r */ + 0x9f2, /* SETSSBSY */ + 0x0, /* */ + 0x9ab, /* SAVEPREVSSP */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x918, /* RDPKRUr */ + 0x3b56, /* WRPKRUr */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0x4f9, /* LMSW16r */ + 0xaf4, /* SWAPGS */ + 0x923, /* RDTSCP */ + 0x608, /* MONITORXrrr */ + 0x6fa, /* MWAITXrrr */ + 0x201, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table4263 */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x719, /* NOOPL_1e */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x921, /* RDSSPQ */ + 0x921, /* RDSSPQ */ + 0x921, /* RDSSPQ */ + 0x921, /* RDSSPQ */ + 0x921, /* RDSSPQ */ + 0x921, /* RDSSPQ */ + 0x921, /* RDSSPQ */ + 0x921, /* RDSSPQ */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x377, /* ENDBR64 */ + 0x376, /* ENDBR32 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table4335 */ + 0x305, /* CVTSI642SSrm */ + 0x307, /* CVTSI642SSrr */ +/* Table4337 */ + 0x31d, /* CVTTSS2SI64rm */ + 0x31f, /* CVTTSS2SI64rr */ +/* Table4339 */ + 0x30d, /* CVTSS2SI64rm_Int */ + 0x30e, /* CVTSS2SI64rr_Int */ +/* Table4341 */ + 0x3b7, /* FXSAVE64 */ + 0x3b5, /* FXRSTOR64 */ + 0x4ca, /* LDMXCSR */ + 0xa82, /* STMXCSR */ + 0x8a3, /* PTWRITE64m */ + 0x3ba4, /* XRSTOR */ + 0x1fe, /* CLRSSBSY */ + 0x1fa, /* CLFLUSH */ + 0x912, /* RDFSBASE64 */ + 0x912, /* RDFSBASE64 */ + 0x912, /* RDFSBASE64 */ + 0x912, /* RDFSBASE64 */ + 0x912, /* RDFSBASE64 */ + 0x912, /* RDFSBASE64 */ + 0x912, /* RDFSBASE64 */ + 0x912, /* RDFSBASE64 */ + 0x914, /* RDGSBASE64 */ + 0x914, /* RDGSBASE64 */ + 0x914, /* RDGSBASE64 */ + 0x914, /* RDGSBASE64 */ + 0x914, /* RDGSBASE64 */ + 0x914, /* RDGSBASE64 */ + 0x914, /* RDGSBASE64 */ + 0x914, /* RDGSBASE64 */ + 0x3b52, /* WRFSBASE64 */ + 0x3b52, /* WRFSBASE64 */ + 0x3b52, /* WRFSBASE64 */ + 0x3b52, /* WRFSBASE64 */ + 0x3b52, /* WRFSBASE64 */ + 0x3b52, /* WRFSBASE64 */ + 0x3b52, /* WRFSBASE64 */ + 0x3b52, /* WRFSBASE64 */ + 0x3b54, /* WRGSBASE64 */ + 0x3b54, /* WRGSBASE64 */ + 0x3b54, /* WRGSBASE64 */ + 0x3b54, /* WRGSBASE64 */ + 0x3b54, /* WRGSBASE64 */ + 0x3b54, /* WRGSBASE64 */ + 0x3b54, /* WRGSBASE64 */ + 0x3b54, /* WRGSBASE64 */ + 0x8a4, /* PTWRITE64r */ + 0x8a4, /* PTWRITE64r */ + 0x8a4, /* PTWRITE64r */ + 0x8a4, /* PTWRITE64r */ + 0x8a4, /* PTWRITE64r */ + 0x8a4, /* PTWRITE64r */ + 0x8a4, /* PTWRITE64r */ + 0x8a4, /* PTWRITE64r */ + 0x40a, /* INCSSPQ */ + 0x40a, /* INCSSPQ */ + 0x40a, /* INCSSPQ */ + 0x40a, /* INCSSPQ */ + 0x40a, /* INCSSPQ */ + 0x40a, /* INCSSPQ */ + 0x40a, /* INCSSPQ */ + 0x40a, /* INCSSPQ */ + 0xb42, /* UMONITOR64 */ + 0xb42, /* UMONITOR64 */ + 0xb42, /* UMONITOR64 */ + 0xb42, /* UMONITOR64 */ + 0xb42, /* UMONITOR64 */ + 0xb42, /* UMONITOR64 */ + 0xb42, /* UMONITOR64 */ + 0xb42, /* UMONITOR64 */ + 0x9f5, /* SFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table4413 */ + 0x84b, /* POPCNT64rm */ + 0x84c, /* POPCNT64rr */ +/* Table4415 */ + 0xb24, /* TZCNT64rm */ + 0xb25, /* TZCNT64rr */ +/* Table4417 */ + 0x51f, /* LZCNT64rm */ + 0x520, /* LZCNT64rr */ +/* Table4419 */ + 0x0, /* */ + 0x2bf, /* CMPXCHG16B */ + 0x0, /* */ + 0x3ba7, /* XRSTORS64 */ + 0x3bab, /* XSAVEC64 */ + 0x3baf, /* XSAVES64 */ + 0x1fe8, /* VMXON */ + 0x1f77, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x91b, /* RDRAND32r */ + 0x917, /* RDPID64 */ +/* Table4435 */ + 0x301, /* CVTSI642SDrm */ + 0x303, /* CVTSI642SDrr */ +/* Table4437 */ + 0x315, /* CVTTSD2SI64rm */ + 0x317, /* CVTTSD2SI64rr */ +/* Table4439 */ + 0x2f1, /* CVTSD2SI64rm_Int */ + 0x2f2, /* CVTSD2SI64rr_Int */ +/* Table4441 */ + 0x1f7a, /* VMREAD64mr */ + 0x40f, /* INSERTQI */ +/* Table4443 */ + 0x1fe5, /* VMWRITE64rm */ + 0x40e, /* INSERTQ */ +/* Table4445 */ + 0x3b7, /* FXSAVE64 */ + 0x3b5, /* FXRSTOR64 */ + 0x4ca, /* LDMXCSR */ + 0xa82, /* STMXCSR */ + 0x3ba8, /* XSAVE */ + 0x3ba4, /* XRSTOR */ + 0x3bac, /* XSAVEOPT */ + 0x1fa, /* CLFLUSH */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x4e7, /* LFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0xb43, /* UMWAIT */ + 0xb43, /* UMWAIT */ + 0xb43, /* UMWAIT */ + 0xb43, /* UMWAIT */ + 0xb43, /* UMWAIT */ + 0xb43, /* UMWAIT */ + 0xb43, /* UMWAIT */ + 0xb43, /* UMWAIT */ + 0x9f5, /* SFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table4517 */ + 0x0, /* */ + 0x2bf, /* CMPXCHG16B */ + 0x0, /* */ + 0x3ba7, /* XRSTORS64 */ + 0x3bab, /* XSAVEC64 */ + 0x3baf, /* XSAVES64 */ + 0x1f76, /* VMPTRLDm */ + 0x1f77, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x91b, /* RDRAND32r */ + 0x91e, /* RDSEED32r */ +/* Table4533 */ + 0x640, /* MOV64toPQIrm */ + 0x641, /* MOV64toPQIrr */ +/* Table4535 */ + 0x68d, /* MOVPQIto64mr */ + 0x68e, /* MOVPQIto64rr */ +/* Table4537 */ + 0x3b7, /* FXSAVE64 */ + 0x3b5, /* FXRSTOR64 */ + 0x4ca, /* LDMXCSR */ + 0xa82, /* STMXCSR */ + 0x3ba8, /* XSAVE */ + 0x3ba4, /* XRSTOR */ + 0x200, /* CLWB */ + 0x1fb, /* CLFLUSHOPT */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x4e7, /* LFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0xb1b, /* TPAUSE */ + 0x9f5, /* SFENCE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table4609 */ + 0x0, /* */ + 0x2bf, /* CMPXCHG16B */ + 0x0, /* */ + 0x3ba7, /* XRSTORS64 */ + 0x3bab, /* XSAVEC64 */ + 0x3baf, /* XSAVES64 */ + 0x1c96, /* VMCLEARm */ + 0x1f77, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x91a, /* RDRAND16r */ + 0x91d, /* RDSEED16r */ +/* Table4625 */ + 0x1f6d, /* VMOVUPSrm */ + 0x1f6e, /* VMOVUPSrr */ +/* Table4627 */ + 0x1f6c, /* VMOVUPSmr */ + 0x1f6f, /* VMOVUPSrr_REV */ +/* Table4629 */ + 0x1ea5, /* VMOVLPSrm */ + 0x1e93, /* VMOVHLPSrr */ +/* Table4631 */ + 0x1ea4, /* VMOVLPSmr */ + 0x0, /* */ +/* Table4633 */ + 0x3b0c, /* VUNPCKLPSrm */ + 0x3b0d, /* VUNPCKLPSrr */ +/* Table4635 */ + 0x3ace, /* VUNPCKHPSrm */ + 0x3acf, /* VUNPCKHPSrr */ +/* Table4637 */ + 0x1e9b, /* VMOVHPSrm */ + 0x1e9d, /* VMOVLHPSrr */ +/* Table4639 */ + 0x1e9a, /* VMOVHPSmr */ + 0x0, /* */ +/* Table4641 */ + 0x1d9b, /* VMOVAPSrm */ + 0x1d9c, /* VMOVAPSrr */ +/* Table4643 */ + 0x1d9a, /* VMOVAPSmr */ + 0x1d9d, /* VMOVAPSrr_REV */ +/* Table4645 */ + 0x1ebd, /* VMOVNTPSmr */ + 0x0, /* */ +/* Table4647 */ + 0x3a8e, /* VUCOMISSrm */ + 0x3a90, /* VUCOMISSrr */ +/* Table4649 */ + 0xde4, /* VCOMISSrm */ + 0xde6, /* VCOMISSrr */ +/* Table4651 */ + 0x0, /* */ + 0x4a2, /* KNOTWrr */ +/* Table4653 */ + 0x0, /* */ + 0x1ea9, /* VMOVMSKPSrr */ +/* Table4655 */ + 0x39f5, /* VSQRTPSm */ + 0x39f6, /* VSQRTPSr */ +/* Table4657 */ + 0x38c5, /* VRSQRTPSm */ + 0x38c6, /* VRSQRTPSr */ +/* Table4659 */ + 0x37a1, /* VRCPPSm */ + 0x37a2, /* VRCPPSr */ +/* Table4661 */ + 0xc9e, /* VANDPSrm */ + 0xc9f, /* VANDPSrr */ +/* Table4663 */ + 0xc60, /* VANDNPSrm */ + 0xc61, /* VANDNPSrr */ +/* Table4665 */ + 0x2025, /* VORPSrm */ + 0x2026, /* VORPSrr */ +/* Table4667 */ + 0x3b4a, /* VXORPSrm */ + 0x3b4b, /* VXORPSrr */ +/* Table4669 */ + 0xb9a, /* VADDPSrm */ + 0xb9b, /* VADDPSrr */ +/* Table4671 */ + 0x1fc3, /* VMULPSrm */ + 0x1fc4, /* VMULPSrr */ +/* Table4673 */ + 0xf40, /* VCVTPS2PDrm */ + 0xf41, /* VCVTPS2PDrr */ +/* Table4675 */ + 0xe45, /* VCVTDQ2PSrm */ + 0xe46, /* VCVTDQ2PSrr */ +/* Table4677 */ + 0x3a58, /* VSUBPSrm */ + 0x3a59, /* VSUBPSrr */ +/* Table4679 */ + 0x1d20, /* VMINPSrm */ + 0x1d21, /* VMINPSrr */ +/* Table4681 */ + 0x125c, /* VDIVPSrm */ + 0x125d, /* VDIVPSrr */ +/* Table4683 */ + 0x1c75, /* VMAXPSrm */ + 0x1c76, /* VMAXPSrr */ +/* Table4685 */ + 0x3b4d, /* VZEROUPPER */ +/* Table4686 */ + 0x49b, /* KMOVWkm */ + 0x49a, /* KMOVWkk */ +/* Table4688 */ + 0x49d, /* KMOVWmk */ + 0x0, /* */ +/* Table4690 */ + 0x0, /* */ + 0x49c, /* KMOVWkr */ +/* Table4692 */ + 0x0, /* */ + 0x49e, /* KMOVWrk */ +/* Table4694 */ + 0x0, /* */ + 0x4a9, /* KORTESTWrr */ +/* Table4696 */ + 0x0, /* */ + 0x4b6, /* KTESTWrr */ +/* Table4698 */ + 0x0, /* */ + 0x0, /* */ + 0x1be2, /* VLDMXCSR */ + 0x3a15, /* VSTMXCSR */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table4714 */ + 0xdaa, /* VCMPPSrmi */ + 0xdac, /* VCMPPSrri */ +/* Table4716 */ + 0x39b1, /* VSHUFPSrmi */ + 0x39b2, /* VSHUFPSrri */ +/* Table4718 */ + 0x1f1b, /* VMOVSSrm */ + 0x1f1c, /* VMOVSSrr */ +/* Table4720 */ + 0x1f1a, /* VMOVSSmr */ + 0x1f1d, /* VMOVSSrr_REV */ +/* Table4722 */ + 0x1f09, /* VMOVSLDUPrm */ + 0x1f0a, /* VMOVSLDUPrr */ +/* Table4724 */ + 0x1ef3, /* VMOVSHDUPrm */ + 0x1ef4, /* VMOVSHDUPrr */ +/* Table4726 */ + 0x101b, /* VCVTSI2SSrm */ + 0x101d, /* VCVTSI2SSrr */ +/* Table4728 */ + 0x1172, /* VCVTTSS2SIrm */ + 0x1174, /* VCVTTSS2SIrr */ +/* Table4730 */ + 0x1048, /* VCVTSS2SIrm_Int */ + 0x1049, /* VCVTSS2SIrr_Int */ +/* Table4732 */ + 0x3a11, /* VSQRTSSm */ + 0x3a13, /* VSQRTSSr */ +/* Table4734 */ + 0x38c7, /* VRSQRTSSm */ + 0x38c9, /* VRSQRTSSr */ +/* Table4736 */ + 0x37a3, /* VRCPSSm */ + 0x37a5, /* VRCPSSr */ +/* Table4738 */ + 0xbb6, /* VADDSSrm */ + 0xbb8, /* VADDSSrr */ +/* Table4740 */ + 0x1fdf, /* VMULSSrm */ + 0x1fe1, /* VMULSSrr */ +/* Table4742 */ + 0x103c, /* VCVTSS2SDrm */ + 0x103e, /* VCVTSS2SDrr */ +/* Table4744 */ + 0x10ec, /* VCVTTPS2DQrm */ + 0x10ed, /* VCVTTPS2DQrr */ +/* Table4746 */ + 0x3a74, /* VSUBSSrm */ + 0x3a76, /* VSUBSSrr */ +/* Table4748 */ + 0x1d3c, /* VMINSSrm */ + 0x1d3e, /* VMINSSrr */ +/* Table4750 */ + 0x1278, /* VDIVSSrm */ + 0x127a, /* VDIVSSrr */ +/* Table4752 */ + 0x1c91, /* VMAXSSrm */ + 0x1c93, /* VMAXSSrr */ +/* Table4754 */ + 0x1e8f, /* VMOVDQUrm */ + 0x1e90, /* VMOVDQUrr */ +/* Table4756 */ + 0x3199, /* VPSHUFHWmi */ + 0x319a, /* VPSHUFHWri */ +/* Table4758 */ + 0x1ecb, /* VMOVQI2PQIrm */ + 0x1f71, /* VMOVZPQILo2PQIrr */ +/* Table4760 */ + 0x1e8e, /* VMOVDQUmr */ + 0x1e91, /* VMOVDQUrr_REV */ +/* Table4762 */ + 0xdd0, /* VCMPSSrm */ + 0xdd3, /* VCMPSSrr */ +/* Table4764 */ + 0xe23, /* VCVTDQ2PDrm */ + 0xe24, /* VCVTDQ2PDrr */ +/* Table4766 */ + 0x1ed8, /* VMOVSDrm */ + 0x1ed9, /* VMOVSDrr */ +/* Table4768 */ + 0x1ed7, /* VMOVSDmr */ + 0x1eda, /* VMOVSDrr_REV */ +/* Table4770 */ + 0x1db2, /* VMOVDDUPrm */ + 0x1db3, /* VMOVDDUPrr */ +/* Table4772 */ + 0x1012, /* VCVTSI2SDrm */ + 0x1014, /* VCVTSI2SDrr */ +/* Table4774 */ + 0x1156, /* VCVTTSD2SIrm */ + 0x1158, /* VCVTTSD2SIrr */ +/* Table4776 */ + 0xff6, /* VCVTSD2SIrm_Int */ + 0xff7, /* VCVTSD2SIrr_Int */ +/* Table4778 */ + 0x3a02, /* VSQRTSDm */ + 0x3a04, /* VSQRTSDr */ +/* Table4780 */ + 0xba7, /* VADDSDrm */ + 0xba9, /* VADDSDrr */ +/* Table4782 */ + 0x1fd0, /* VMULSDrm */ + 0x1fd2, /* VMULSDrr */ +/* Table4784 */ + 0x1003, /* VCVTSD2SSrm */ + 0x1005, /* VCVTSD2SSrr */ +/* Table4786 */ + 0x3a65, /* VSUBSDrm */ + 0x3a67, /* VSUBSDrr */ +/* Table4788 */ + 0x1d2d, /* VMINSDrm */ + 0x1d2f, /* VMINSDrr */ +/* Table4790 */ + 0x1269, /* VDIVSDrm */ + 0x126b, /* VDIVSDrr */ +/* Table4792 */ + 0x1c82, /* VMAXSDrm */ + 0x1c84, /* VMAXSDrr */ +/* Table4794 */ + 0x31af, /* VPSHUFLWmi */ + 0x31b0, /* VPSHUFLWri */ +/* Table4796 */ + 0x1b86, /* VHADDPSrm */ + 0x1b87, /* VHADDPSrr */ +/* Table4798 */ + 0x1b8e, /* VHSUBPSrm */ + 0x1b8f, /* VHSUBPSrr */ +/* Table4800 */ + 0x0, /* */ + 0x492, /* KMOVDkr */ +/* Table4802 */ + 0x0, /* */ + 0x494, /* KMOVDrk */ +/* Table4804 */ + 0xdbc, /* VCMPSDrm */ + 0xdbf, /* VCMPSDrr */ +/* Table4806 */ + 0xbc0, /* VADDSUBPSrm */ + 0xbc1, /* VADDSUBPSrr */ +/* Table4808 */ + 0xe67, /* VCVTPD2DQrm */ + 0xe68, /* VCVTPD2DQrr */ +/* Table4810 */ + 0x1be1, /* VLDDQUrm */ + 0x0, /* */ +/* Table4812 */ + 0x1f44, /* VMOVUPDrm */ + 0x1f45, /* VMOVUPDrr */ +/* Table4814 */ + 0x1f43, /* VMOVUPDmr */ + 0x1f46, /* VMOVUPDrr_REV */ +/* Table4816 */ + 0x1ea1, /* VMOVLPDrm */ + 0x0, /* */ +/* Table4818 */ + 0x1ea0, /* VMOVLPDmr */ + 0x0, /* */ +/* Table4820 */ + 0x3aed, /* VUNPCKLPDrm */ + 0x3aee, /* VUNPCKLPDrr */ +/* Table4822 */ + 0x3aaf, /* VUNPCKHPDrm */ + 0x3ab0, /* VUNPCKHPDrr */ +/* Table4824 */ + 0x1e97, /* VMOVHPDrm */ + 0x0, /* */ +/* Table4826 */ + 0x1e96, /* VMOVHPDmr */ + 0x0, /* */ +/* Table4828 */ + 0x1d72, /* VMOVAPDrm */ + 0x1d73, /* VMOVAPDrr */ +/* Table4830 */ + 0x1d71, /* VMOVAPDmr */ + 0x1d74, /* VMOVAPDrr_REV */ +/* Table4832 */ + 0x1eb8, /* VMOVNTPDmr */ + 0x0, /* */ +/* Table4834 */ + 0x3a85, /* VUCOMISDrm */ + 0x3a87, /* VUCOMISDrr */ +/* Table4836 */ + 0xddb, /* VCOMISDrm */ + 0xddd, /* VCOMISDrr */ +/* Table4838 */ + 0x0, /* */ + 0x49f, /* KNOTBrr */ +/* Table4840 */ + 0x0, /* */ + 0x1ea7, /* VMOVMSKPDrr */ +/* Table4842 */ + 0x39d3, /* VSQRTPDm */ + 0x39d4, /* VSQRTPDr */ +/* Table4844 */ + 0xc7f, /* VANDPDrm */ + 0xc80, /* VANDPDrr */ +/* Table4846 */ + 0xc41, /* VANDNPDrm */ + 0xc42, /* VANDNPDrr */ +/* Table4848 */ + 0x2006, /* VORPDrm */ + 0x2007, /* VORPDrr */ +/* Table4850 */ + 0x3b2b, /* VXORPDrm */ + 0x3b2c, /* VXORPDrr */ +/* Table4852 */ + 0xb78, /* VADDPDrm */ + 0xb79, /* VADDPDrr */ +/* Table4854 */ + 0x1fa1, /* VMULPDrm */ + 0x1fa2, /* VMULPDrr */ +/* Table4856 */ + 0xe89, /* VCVTPD2PSrm */ + 0xe8a, /* VCVTPD2PSrr */ +/* Table4858 */ + 0xf1e, /* VCVTPS2DQrm */ + 0xf1f, /* VCVTPS2DQrr */ +/* Table4860 */ + 0x3a36, /* VSUBPDrm */ + 0x3a37, /* VSUBPDrr */ +/* Table4862 */ + 0x1cfe, /* VMINPDrm */ + 0x1cff, /* VMINPDrr */ +/* Table4864 */ + 0x123a, /* VDIVPDrm */ + 0x123b, /* VDIVPDrr */ +/* Table4866 */ + 0x1c53, /* VMAXPDrm */ + 0x1c54, /* VMAXPDrr */ +/* Table4868 */ + 0x3655, /* VPUNPCKLBWrm */ + 0x3656, /* VPUNPCKLBWrr */ +/* Table4870 */ + 0x36a9, /* VPUNPCKLWDrm */ + 0x36aa, /* VPUNPCKLWDrr */ +/* Table4872 */ + 0x3674, /* VPUNPCKLDQrm */ + 0x3675, /* VPUNPCKLDQrr */ +/* Table4874 */ + 0x20c6, /* VPACKSSWBrm */ + 0x20c7, /* VPACKSSWBrr */ +/* Table4876 */ + 0x2409, /* VPCMPGTBrm */ + 0x240a, /* VPCMPGTBrr */ +/* Table4878 */ + 0x2445, /* VPCMPGTWrm */ + 0x2446, /* VPCMPGTWrr */ +/* Table4880 */ + 0x241f, /* VPCMPGTDrm */ + 0x2420, /* VPCMPGTDrr */ +/* Table4882 */ + 0x20fb, /* VPACKUSWBrm */ + 0x20fc, /* VPACKUSWBrr */ +/* Table4884 */ + 0x35eb, /* VPUNPCKHBWrm */ + 0x35ec, /* VPUNPCKHBWrr */ +/* Table4886 */ + 0x363f, /* VPUNPCKHWDrm */ + 0x3640, /* VPUNPCKHWDrr */ +/* Table4888 */ + 0x360a, /* VPUNPCKHDQrm */ + 0x360b, /* VPUNPCKHDQrr */ +/* Table4890 */ + 0x20b0, /* VPACKSSDWrm */ + 0x20b1, /* VPACKSSDWrr */ +/* Table4892 */ + 0x3693, /* VPUNPCKLQDQrm */ + 0x3694, /* VPUNPCKLQDQrr */ +/* Table4894 */ + 0x3629, /* VPUNPCKHQDQrm */ + 0x362a, /* VPUNPCKHQDQrr */ +/* Table4896 */ + 0x1db6, /* VMOVDI2PDIrm */ + 0x1db7, /* VMOVDI2PDIrr */ +/* Table4898 */ + 0x1e03, /* VMOVDQArm */ + 0x1e04, /* VMOVDQArr */ +/* Table4900 */ + 0x3183, /* VPSHUFDmi */ + 0x3184, /* VPSHUFDri */ +/* Table4902 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3460, /* VPSRLWri */ + 0x0, /* */ + 0x3378, /* VPSRAWri */ + 0x0, /* */ + 0x32a2, /* VPSLLWri */ + 0x0, /* */ +/* Table4918 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x33b3, /* VPSRLDri */ + 0x0, /* */ + 0x32d5, /* VPSRADri */ + 0x0, /* */ + 0x31f5, /* VPSLLDri */ + 0x0, /* */ +/* Table4934 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x33e6, /* VPSRLQri */ + 0x3382, /* VPSRLDQri */ + 0x0, /* */ + 0x0, /* */ + 0x3228, /* VPSLLQri */ + 0x31c4, /* VPSLLDQri */ +/* Table4950 */ + 0x23b9, /* VPCMPEQBrm */ + 0x23ba, /* VPCMPEQBrr */ +/* Table4952 */ + 0x23f5, /* VPCMPEQWrm */ + 0x23f6, /* VPCMPEQWrr */ +/* Table4954 */ + 0x23cf, /* VPCMPEQDrm */ + 0x23d0, /* VPCMPEQDrr */ +/* Table4956 */ + 0x1b82, /* VHADDPDrm */ + 0x1b83, /* VHADDPDrr */ +/* Table4958 */ + 0x1b8a, /* VHSUBPDrm */ + 0x1b8b, /* VHSUBPDrr */ +/* Table4960 */ + 0x1ec0, /* VMOVPDI2DImr */ + 0x1ec1, /* VMOVPDI2DIrr */ +/* Table4962 */ + 0x1e02, /* VMOVDQAmr */ + 0x1e05, /* VMOVDQArr_REV */ +/* Table4964 */ + 0x48c, /* KMOVBkm */ + 0x48b, /* KMOVBkk */ +/* Table4966 */ + 0x48e, /* KMOVBmk */ + 0x0, /* */ +/* Table4968 */ + 0x0, /* */ + 0x48d, /* KMOVBkr */ +/* Table4970 */ + 0x0, /* */ + 0x48f, /* KMOVBrk */ +/* Table4972 */ + 0x0, /* */ + 0x4a6, /* KORTESTBrr */ +/* Table4974 */ + 0x0, /* */ + 0x4b3, /* KTESTBrr */ +/* Table4976 */ + 0xd7a, /* VCMPPDrmi */ + 0xd7c, /* VCMPPDrri */ +/* Table4978 */ + 0x28f9, /* VPINSRWrm */ + 0x28fa, /* VPINSRWrr */ +/* Table4980 */ + 0x0, /* */ + 0x289d, /* VPEXTRWrr */ +/* Table4982 */ + 0x3992, /* VSHUFPDrmi */ + 0x3993, /* VSHUFPDrri */ +/* Table4984 */ + 0xbbc, /* VADDSUBPDrm */ + 0xbbd, /* VADDSUBPDrr */ +/* Table4986 */ + 0x3461, /* VPSRLWrm */ + 0x3462, /* VPSRLWrr */ +/* Table4988 */ + 0x33b4, /* VPSRLDrm */ + 0x33b5, /* VPSRLDrr */ +/* Table4990 */ + 0x33e7, /* VPSRLQrm */ + 0x33e8, /* VPSRLQrr */ +/* Table4992 */ + 0x214f, /* VPADDQrm */ + 0x2150, /* VPADDQrr */ +/* Table4994 */ + 0x2e2a, /* VPMULLWrm */ + 0x2e2b, /* VPMULLWrr */ +/* Table4996 */ + 0x1ec4, /* VMOVPQI2QImr */ + 0x1ec5, /* VMOVPQI2QIrr */ +/* Table4998 */ + 0x0, /* */ + 0x2b7c, /* VPMOVMSKBrr */ +/* Table5000 */ + 0x34f7, /* VPSUBUSBrm */ + 0x34f8, /* VPSUBUSBrr */ +/* Table5002 */ + 0x350d, /* VPSUBUSWrm */ + 0x350e, /* VPSUBUSWrr */ +/* Table5004 */ + 0x2af9, /* VPMINUBrm */ + 0x2afa, /* VPMINUBrr */ +/* Table5006 */ + 0x2247, /* VPANDrm */ + 0x2248, /* VPANDrr */ +/* Table5008 */ + 0x2191, /* VPADDUSBrm */ + 0x2192, /* VPADDUSBrr */ +/* Table5010 */ + 0x21a7, /* VPADDUSWrm */ + 0x21a8, /* VPADDUSWrr */ +/* Table5012 */ + 0x2a2d, /* VPMAXUBrm */ + 0x2a2e, /* VPMAXUBrr */ +/* Table5014 */ + 0x2228, /* VPANDNrm */ + 0x2229, /* VPANDNrr */ +/* Table5016 */ + 0x225d, /* VPAVGBrm */ + 0x225e, /* VPAVGBrr */ +/* Table5018 */ + 0x3379, /* VPSRAWrm */ + 0x337a, /* VPSRAWrr */ +/* Table5020 */ + 0x32d6, /* VPSRADrm */ + 0x32d7, /* VPSRADrr */ +/* Table5022 */ + 0x2273, /* VPAVGWrm */ + 0x2274, /* VPAVGWrr */ +/* Table5024 */ + 0x2dc4, /* VPMULHUWrm */ + 0x2dc5, /* VPMULHUWrr */ +/* Table5026 */ + 0x2dda, /* VPMULHWrm */ + 0x2ddb, /* VPMULHWrr */ +/* Table5028 */ + 0x1070, /* VCVTTPD2DQrm */ + 0x1071, /* VCVTTPD2DQrr */ +/* Table5030 */ + 0x1eb3, /* VMOVNTDQmr */ + 0x0, /* */ +/* Table5032 */ + 0x34cb, /* VPSUBSBrm */ + 0x34cc, /* VPSUBSBrr */ +/* Table5034 */ + 0x34e1, /* VPSUBSWrm */ + 0x34e2, /* VPSUBSWrr */ +/* Table5036 */ + 0x2ae3, /* VPMINSWrm */ + 0x2ae4, /* VPMINSWrr */ +/* Table5038 */ + 0x2ef8, /* VPORrm */ + 0x2ef9, /* VPORrr */ +/* Table5040 */ + 0x2165, /* VPADDSBrm */ + 0x2166, /* VPADDSBrr */ +/* Table5042 */ + 0x217b, /* VPADDSWrm */ + 0x217c, /* VPADDSWrr */ +/* Table5044 */ + 0x2a17, /* VPMAXSWrm */ + 0x2a18, /* VPMAXSWrr */ +/* Table5046 */ + 0x36e3, /* VPXORrm */ + 0x36e4, /* VPXORrr */ +/* Table5048 */ + 0x32a3, /* VPSLLWrm */ + 0x32a4, /* VPSLLWrr */ +/* Table5050 */ + 0x31f6, /* VPSLLDrm */ + 0x31f7, /* VPSLLDrr */ +/* Table5052 */ + 0x3229, /* VPSLLQrm */ + 0x322a, /* VPSLLQrr */ +/* Table5054 */ + 0x2e64, /* VPMULUDQrm */ + 0x2e65, /* VPMULUDQrr */ +/* Table5056 */ + 0x29a9, /* VPMADDWDrm */ + 0x29aa, /* VPMADDWDrr */ +/* Table5058 */ + 0x2ff6, /* VPSADBWrm */ + 0x2ff7, /* VPSADBWrr */ +/* Table5060 */ + 0x0, /* */ + 0x1be3, /* VMASKMOVDQU */ +/* Table5062 */ + 0x3477, /* VPSUBBrm */ + 0x3478, /* VPSUBBrr */ +/* Table5064 */ + 0x3523, /* VPSUBWrm */ + 0x3524, /* VPSUBWrr */ +/* Table5066 */ + 0x3496, /* VPSUBDrm */ + 0x3497, /* VPSUBDrr */ +/* Table5068 */ + 0x34b5, /* VPSUBQrm */ + 0x34b6, /* VPSUBQrr */ +/* Table5070 */ + 0x2111, /* VPADDBrm */ + 0x2112, /* VPADDBrr */ +/* Table5072 */ + 0x21bd, /* VPADDWrm */ + 0x21be, /* VPADDWrr */ +/* Table5074 */ + 0x2130, /* VPADDDrm */ + 0x2131, /* VPADDDrr */ +/* Table5076 */ + 0x0, /* */ + 0x4a1, /* KNOTQrr */ +/* Table5078 */ + 0x496, /* KMOVQkm */ + 0x495, /* KMOVQkk */ +/* Table5080 */ + 0x498, /* KMOVQmk */ + 0x0, /* */ +/* Table5082 */ + 0x0, /* */ + 0x4a8, /* KORTESTQrr */ +/* Table5084 */ + 0x0, /* */ + 0x4b5, /* KTESTQrr */ +/* Table5086 */ + 0x102d, /* VCVTSI642SSrm */ + 0x102f, /* VCVTSI642SSrr */ +/* Table5088 */ + 0x1169, /* VCVTTSS2SI64rm */ + 0x116b, /* VCVTTSS2SI64rr */ +/* Table5090 */ + 0x1043, /* VCVTSS2SI64rm_Int */ + 0x1044, /* VCVTSS2SI64rr_Int */ +/* Table5092 */ + 0x1024, /* VCVTSI642SDrm */ + 0x1026, /* VCVTSI642SDrr */ +/* Table5094 */ + 0x114d, /* VCVTTSD2SI64rm */ + 0x114f, /* VCVTTSD2SI64rr */ +/* Table5096 */ + 0xff1, /* VCVTSD2SI64rm_Int */ + 0xff2, /* VCVTSD2SI64rr_Int */ +/* Table5098 */ + 0x0, /* */ + 0x497, /* KMOVQkr */ +/* Table5100 */ + 0x0, /* */ + 0x499, /* KMOVQrk */ +/* Table5102 */ + 0x0, /* */ + 0x4a0, /* KNOTDrr */ +/* Table5104 */ + 0x1d46, /* VMOV64toPQIrm */ + 0x1d47, /* VMOV64toPQIrr */ +/* Table5106 */ + 0x1ec8, /* VMOVPQIto64mr */ + 0x1ec9, /* VMOVPQIto64rr */ +/* Table5108 */ + 0x491, /* KMOVDkm */ + 0x490, /* KMOVDkk */ +/* Table5110 */ + 0x493, /* KMOVDmk */ + 0x0, /* */ +/* Table5112 */ + 0x0, /* */ + 0x4a7, /* KORTESTDrr */ +/* Table5114 */ + 0x0, /* */ + 0x4b4, /* KTESTDrr */ +/* Table5116 */ + 0x1f48, /* VMOVUPSYrm */ + 0x1f49, /* VMOVUPSYrr */ +/* Table5118 */ + 0x1f47, /* VMOVUPSYmr */ + 0x1f4a, /* VMOVUPSYrr_REV */ +/* Table5120 */ + 0x3aef, /* VUNPCKLPSYrm */ + 0x3af0, /* VUNPCKLPSYrr */ +/* Table5122 */ + 0x3ab1, /* VUNPCKHPSYrm */ + 0x3ab2, /* VUNPCKHPSYrr */ +/* Table5124 */ + 0x1d76, /* VMOVAPSYrm */ + 0x1d77, /* VMOVAPSYrr */ +/* Table5126 */ + 0x1d75, /* VMOVAPSYmr */ + 0x1d78, /* VMOVAPSYrr_REV */ +/* Table5128 */ + 0x1eb9, /* VMOVNTPSYmr */ + 0x0, /* */ +/* Table5130 */ + 0x0, /* */ + 0x48a, /* KANDWrr */ +/* Table5132 */ + 0x0, /* */ + 0x488, /* KANDNWrr */ +/* Table5134 */ + 0x0, /* */ + 0x4aa, /* KORWrr */ +/* Table5136 */ + 0x0, /* */ + 0x4bd, /* KXNORWrr */ +/* Table5138 */ + 0x0, /* */ + 0x4c1, /* KXORWrr */ +/* Table5140 */ + 0x0, /* */ + 0x482, /* KADDWrr */ +/* Table5142 */ + 0x0, /* */ + 0x4b9, /* KUNPCKWDrr */ +/* Table5144 */ + 0x0, /* */ + 0x1ea8, /* VMOVMSKPSYrr */ +/* Table5146 */ + 0x39d5, /* VSQRTPSYm */ + 0x39d6, /* VSQRTPSYr */ +/* Table5148 */ + 0x38c3, /* VRSQRTPSYm */ + 0x38c4, /* VRSQRTPSYr */ +/* Table5150 */ + 0x379f, /* VRCPPSYm */ + 0x37a0, /* VRCPPSYr */ +/* Table5152 */ + 0xc81, /* VANDPSYrm */ + 0xc82, /* VANDPSYrr */ +/* Table5154 */ + 0xc43, /* VANDNPSYrm */ + 0xc44, /* VANDNPSYrr */ +/* Table5156 */ + 0x2008, /* VORPSYrm */ + 0x2009, /* VORPSYrr */ +/* Table5158 */ + 0x3b2d, /* VXORPSYrm */ + 0x3b2e, /* VXORPSYrr */ +/* Table5160 */ + 0xb7a, /* VADDPSYrm */ + 0xb7b, /* VADDPSYrr */ +/* Table5162 */ + 0x1fa3, /* VMULPSYrm */ + 0x1fa4, /* VMULPSYrr */ +/* Table5164 */ + 0xf20, /* VCVTPS2PDYrm */ + 0xf21, /* VCVTPS2PDYrr */ +/* Table5166 */ + 0xe25, /* VCVTDQ2PSYrm */ + 0xe26, /* VCVTDQ2PSYrr */ +/* Table5168 */ + 0x3a38, /* VSUBPSYrm */ + 0x3a39, /* VSUBPSYrr */ +/* Table5170 */ + 0x1d00, /* VMINPSYrm */ + 0x1d01, /* VMINPSYrr */ +/* Table5172 */ + 0x123c, /* VDIVPSYrm */ + 0x123d, /* VDIVPSYrr */ +/* Table5174 */ + 0x1c55, /* VMAXPSYrm */ + 0x1c56, /* VMAXPSYrr */ +/* Table5176 */ + 0x3b4c, /* VZEROALL */ +/* Table5177 */ + 0xd7e, /* VCMPPSYrmi */ + 0xd80, /* VCMPPSYrri */ +/* Table5179 */ + 0x3994, /* VSHUFPSYrmi */ + 0x3995, /* VSHUFPSYrri */ +/* Table5181 */ + 0x1ef5, /* VMOVSLDUPYrm */ + 0x1ef6, /* VMOVSLDUPYrr */ +/* Table5183 */ + 0x1edf, /* VMOVSHDUPYrm */ + 0x1ee0, /* VMOVSHDUPYrr */ +/* Table5185 */ + 0x10cc, /* VCVTTPS2DQYrm */ + 0x10cd, /* VCVTTPS2DQYrr */ +/* Table5187 */ + 0x1e8b, /* VMOVDQUYrm */ + 0x1e8c, /* VMOVDQUYrr */ +/* Table5189 */ + 0x3185, /* VPSHUFHWYmi */ + 0x3186, /* VPSHUFHWYri */ +/* Table5191 */ + 0x1e8a, /* VMOVDQUYmr */ + 0x1e8d, /* VMOVDQUYrr_REV */ +/* Table5193 */ + 0xe06, /* VCVTDQ2PDYrm */ + 0xe07, /* VCVTDQ2PDYrr */ +/* Table5195 */ + 0x1d9e, /* VMOVDDUPYrm */ + 0x1d9f, /* VMOVDDUPYrr */ +/* Table5197 */ + 0x319b, /* VPSHUFLWYmi */ + 0x319c, /* VPSHUFLWYri */ +/* Table5199 */ + 0x1b84, /* VHADDPSYrm */ + 0x1b85, /* VHADDPSYrr */ +/* Table5201 */ + 0x1b8c, /* VHSUBPSYrm */ + 0x1b8d, /* VHSUBPSYrr */ +/* Table5203 */ + 0xbbe, /* VADDSUBPSYrm */ + 0xbbf, /* VADDSUBPSYrr */ +/* Table5205 */ + 0xe47, /* VCVTPD2DQYrm */ + 0xe48, /* VCVTPD2DQYrr */ +/* Table5207 */ + 0x1be0, /* VLDDQUYrm */ + 0x0, /* */ +/* Table5209 */ + 0x1f1f, /* VMOVUPDYrm */ + 0x1f20, /* VMOVUPDYrr */ +/* Table5211 */ + 0x1f1e, /* VMOVUPDYmr */ + 0x1f21, /* VMOVUPDYrr_REV */ +/* Table5213 */ + 0x3ad0, /* VUNPCKLPDYrm */ + 0x3ad1, /* VUNPCKLPDYrr */ +/* Table5215 */ + 0x3a92, /* VUNPCKHPDYrm */ + 0x3a93, /* VUNPCKHPDYrr */ +/* Table5217 */ + 0x1d4d, /* VMOVAPDYrm */ + 0x1d4e, /* VMOVAPDYrr */ +/* Table5219 */ + 0x1d4c, /* VMOVAPDYmr */ + 0x1d4f, /* VMOVAPDYrr_REV */ +/* Table5221 */ + 0x1eb4, /* VMOVNTPDYmr */ + 0x0, /* */ +/* Table5223 */ + 0x0, /* */ + 0x483, /* KANDBrr */ +/* Table5225 */ + 0x0, /* */ + 0x485, /* KANDNBrr */ +/* Table5227 */ + 0x0, /* */ + 0x4a3, /* KORBrr */ +/* Table5229 */ + 0x0, /* */ + 0x4ba, /* KXNORBrr */ +/* Table5231 */ + 0x0, /* */ + 0x4be, /* KXORBrr */ +/* Table5233 */ + 0x0, /* */ + 0x47f, /* KADDBrr */ +/* Table5235 */ + 0x0, /* */ + 0x4b7, /* KUNPCKBWrr */ +/* Table5237 */ + 0x0, /* */ + 0x1ea6, /* VMOVMSKPDYrr */ +/* Table5239 */ + 0x39b3, /* VSQRTPDYm */ + 0x39b4, /* VSQRTPDYr */ +/* Table5241 */ + 0xc62, /* VANDPDYrm */ + 0xc63, /* VANDPDYrr */ +/* Table5243 */ + 0xc24, /* VANDNPDYrm */ + 0xc25, /* VANDNPDYrr */ +/* Table5245 */ + 0x1fe9, /* VORPDYrm */ + 0x1fea, /* VORPDYrr */ +/* Table5247 */ + 0x3b0e, /* VXORPDYrm */ + 0x3b0f, /* VXORPDYrr */ +/* Table5249 */ + 0xb58, /* VADDPDYrm */ + 0xb59, /* VADDPDYrr */ +/* Table5251 */ + 0x1f81, /* VMULPDYrm */ + 0x1f82, /* VMULPDYrr */ +/* Table5253 */ + 0xe69, /* VCVTPD2PSYrm */ + 0xe6a, /* VCVTPD2PSYrr */ +/* Table5255 */ + 0xefe, /* VCVTPS2DQYrm */ + 0xeff, /* VCVTPS2DQYrr */ +/* Table5257 */ + 0x3a16, /* VSUBPDYrm */ + 0x3a17, /* VSUBPDYrr */ +/* Table5259 */ + 0x1cde, /* VMINPDYrm */ + 0x1cdf, /* VMINPDYrr */ +/* Table5261 */ + 0x121a, /* VDIVPDYrm */ + 0x121b, /* VDIVPDYrr */ +/* Table5263 */ + 0x1c33, /* VMAXPDYrm */ + 0x1c34, /* VMAXPDYrr */ +/* Table5265 */ + 0x3641, /* VPUNPCKLBWYrm */ + 0x3642, /* VPUNPCKLBWYrr */ +/* Table5267 */ + 0x3695, /* VPUNPCKLWDYrm */ + 0x3696, /* VPUNPCKLWDYrr */ +/* Table5269 */ + 0x3657, /* VPUNPCKLDQYrm */ + 0x3658, /* VPUNPCKLDQYrr */ +/* Table5271 */ + 0x20b2, /* VPACKSSWBYrm */ + 0x20b3, /* VPACKSSWBYrr */ +/* Table5273 */ + 0x23fb, /* VPCMPGTBYrm */ + 0x23fc, /* VPCMPGTBYrr */ +/* Table5275 */ + 0x2437, /* VPCMPGTWYrm */ + 0x2438, /* VPCMPGTWYrr */ +/* Table5277 */ + 0x240b, /* VPCMPGTDYrm */ + 0x240c, /* VPCMPGTDYrr */ +/* Table5279 */ + 0x20e7, /* VPACKUSWBYrm */ + 0x20e8, /* VPACKUSWBYrr */ +/* Table5281 */ + 0x35d7, /* VPUNPCKHBWYrm */ + 0x35d8, /* VPUNPCKHBWYrr */ +/* Table5283 */ + 0x362b, /* VPUNPCKHWDYrm */ + 0x362c, /* VPUNPCKHWDYrr */ +/* Table5285 */ + 0x35ed, /* VPUNPCKHDQYrm */ + 0x35ee, /* VPUNPCKHDQYrr */ +/* Table5287 */ + 0x2093, /* VPACKSSDWYrm */ + 0x2094, /* VPACKSSDWYrr */ +/* Table5289 */ + 0x3676, /* VPUNPCKLQDQYrm */ + 0x3677, /* VPUNPCKLQDQYrr */ +/* Table5291 */ + 0x360c, /* VPUNPCKHQDQYrm */ + 0x360d, /* VPUNPCKHQDQYrr */ +/* Table5293 */ + 0x1dff, /* VMOVDQAYrm */ + 0x1e00, /* VMOVDQAYrr */ +/* Table5295 */ + 0x3166, /* VPSHUFDYmi */ + 0x3167, /* VPSHUFDYri */ +/* Table5297 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3439, /* VPSRLWYri */ + 0x0, /* */ + 0x3351, /* VPSRAWYri */ + 0x0, /* */ + 0x327b, /* VPSLLWYri */ + 0x0, /* */ +/* Table5313 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3383, /* VPSRLDYri */ + 0x0, /* */ + 0x32a5, /* VPSRADYri */ + 0x0, /* */ + 0x31c5, /* VPSLLDYri */ + 0x0, /* */ +/* Table5329 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x33b6, /* VPSRLQYri */ + 0x337b, /* VPSRLDQYri */ + 0x0, /* */ + 0x0, /* */ + 0x31f8, /* VPSLLQYri */ + 0x31bd, /* VPSLLDQYri */ +/* Table5345 */ + 0x23ab, /* VPCMPEQBYrm */ + 0x23ac, /* VPCMPEQBYrr */ +/* Table5347 */ + 0x23e7, /* VPCMPEQWYrm */ + 0x23e8, /* VPCMPEQWYrr */ +/* Table5349 */ + 0x23bb, /* VPCMPEQDYrm */ + 0x23bc, /* VPCMPEQDYrr */ +/* Table5351 */ + 0x1b80, /* VHADDPDYrm */ + 0x1b81, /* VHADDPDYrr */ +/* Table5353 */ + 0x1b88, /* VHSUBPDYrm */ + 0x1b89, /* VHSUBPDYrr */ +/* Table5355 */ + 0x1dfe, /* VMOVDQAYmr */ + 0x1e01, /* VMOVDQAYrr_REV */ +/* Table5357 */ + 0xd4e, /* VCMPPDYrmi */ + 0xd50, /* VCMPPDYrri */ +/* Table5359 */ + 0x3975, /* VSHUFPDYrmi */ + 0x3976, /* VSHUFPDYrri */ +/* Table5361 */ + 0xbba, /* VADDSUBPDYrm */ + 0xbbb, /* VADDSUBPDYrr */ +/* Table5363 */ + 0x343a, /* VPSRLWYrm */ + 0x343b, /* VPSRLWYrr */ +/* Table5365 */ + 0x3384, /* VPSRLDYrm */ + 0x3385, /* VPSRLDYrr */ +/* Table5367 */ + 0x33b7, /* VPSRLQYrm */ + 0x33b8, /* VPSRLQYrr */ +/* Table5369 */ + 0x2132, /* VPADDQYrm */ + 0x2133, /* VPADDQYrr */ +/* Table5371 */ + 0x2e16, /* VPMULLWYrm */ + 0x2e17, /* VPMULLWYrr */ +/* Table5373 */ + 0x0, /* */ + 0x2b7b, /* VPMOVMSKBYrr */ +/* Table5375 */ + 0x34e3, /* VPSUBUSBYrm */ + 0x34e4, /* VPSUBUSBYrr */ +/* Table5377 */ + 0x34f9, /* VPSUBUSWYrm */ + 0x34fa, /* VPSUBUSWYrr */ +/* Table5379 */ + 0x2ae5, /* VPMINUBYrm */ + 0x2ae6, /* VPMINUBYrr */ +/* Table5381 */ + 0x2245, /* VPANDYrm */ + 0x2246, /* VPANDYrr */ +/* Table5383 */ + 0x217d, /* VPADDUSBYrm */ + 0x217e, /* VPADDUSBYrr */ +/* Table5385 */ + 0x2193, /* VPADDUSWYrm */ + 0x2194, /* VPADDUSWYrr */ +/* Table5387 */ + 0x2a19, /* VPMAXUBYrm */ + 0x2a1a, /* VPMAXUBYrr */ +/* Table5389 */ + 0x2226, /* VPANDNYrm */ + 0x2227, /* VPANDNYrr */ +/* Table5391 */ + 0x2249, /* VPAVGBYrm */ + 0x224a, /* VPAVGBYrr */ +/* Table5393 */ + 0x3352, /* VPSRAWYrm */ + 0x3353, /* VPSRAWYrr */ +/* Table5395 */ + 0x32a6, /* VPSRADYrm */ + 0x32a7, /* VPSRADYrr */ +/* Table5397 */ + 0x225f, /* VPAVGWYrm */ + 0x2260, /* VPAVGWYrr */ +/* Table5399 */ + 0x2db0, /* VPMULHUWYrm */ + 0x2db1, /* VPMULHUWYrr */ +/* Table5401 */ + 0x2dc6, /* VPMULHWYrm */ + 0x2dc7, /* VPMULHWYrr */ +/* Table5403 */ + 0x1050, /* VCVTTPD2DQYrm */ + 0x1051, /* VCVTTPD2DQYrr */ +/* Table5405 */ + 0x1eaf, /* VMOVNTDQYmr */ + 0x0, /* */ +/* Table5407 */ + 0x34b7, /* VPSUBSBYrm */ + 0x34b8, /* VPSUBSBYrr */ +/* Table5409 */ + 0x34cd, /* VPSUBSWYrm */ + 0x34ce, /* VPSUBSWYrr */ +/* Table5411 */ + 0x2acf, /* VPMINSWYrm */ + 0x2ad0, /* VPMINSWYrr */ +/* Table5413 */ + 0x2ef6, /* VPORYrm */ + 0x2ef7, /* VPORYrr */ +/* Table5415 */ + 0x2151, /* VPADDSBYrm */ + 0x2152, /* VPADDSBYrr */ +/* Table5417 */ + 0x2167, /* VPADDSWYrm */ + 0x2168, /* VPADDSWYrr */ +/* Table5419 */ + 0x2a03, /* VPMAXSWYrm */ + 0x2a04, /* VPMAXSWYrr */ +/* Table5421 */ + 0x36e1, /* VPXORYrm */ + 0x36e2, /* VPXORYrr */ +/* Table5423 */ + 0x327c, /* VPSLLWYrm */ + 0x327d, /* VPSLLWYrr */ +/* Table5425 */ + 0x31c6, /* VPSLLDYrm */ + 0x31c7, /* VPSLLDYrr */ +/* Table5427 */ + 0x31f9, /* VPSLLQYrm */ + 0x31fa, /* VPSLLQYrr */ +/* Table5429 */ + 0x2e47, /* VPMULUDQYrm */ + 0x2e48, /* VPMULUDQYrr */ +/* Table5431 */ + 0x2995, /* VPMADDWDYrm */ + 0x2996, /* VPMADDWDYrr */ +/* Table5433 */ + 0x2fee, /* VPSADBWYrm */ + 0x2fef, /* VPSADBWYrr */ +/* Table5435 */ + 0x3463, /* VPSUBBYrm */ + 0x3464, /* VPSUBBYrr */ +/* Table5437 */ + 0x350f, /* VPSUBWYrm */ + 0x3510, /* VPSUBWYrr */ +/* Table5439 */ + 0x3479, /* VPSUBDYrm */ + 0x347a, /* VPSUBDYrr */ +/* Table5441 */ + 0x3498, /* VPSUBQYrm */ + 0x3499, /* VPSUBQYrr */ +/* Table5443 */ + 0x20fd, /* VPADDBYrm */ + 0x20fe, /* VPADDBYrr */ +/* Table5445 */ + 0x21a9, /* VPADDWYrm */ + 0x21aa, /* VPADDWYrr */ +/* Table5447 */ + 0x2113, /* VPADDDYrm */ + 0x2114, /* VPADDDYrr */ +/* Table5449 */ + 0x0, /* */ + 0x489, /* KANDQrr */ +/* Table5451 */ + 0x0, /* */ + 0x487, /* KANDNQrr */ +/* Table5453 */ + 0x0, /* */ + 0x4a5, /* KORQrr */ +/* Table5455 */ + 0x0, /* */ + 0x4bc, /* KXNORQrr */ +/* Table5457 */ + 0x0, /* */ + 0x4c0, /* KXORQrr */ +/* Table5459 */ + 0x0, /* */ + 0x481, /* KADDQrr */ +/* Table5461 */ + 0x0, /* */ + 0x4b8, /* KUNPCKDQrr */ +/* Table5463 */ + 0x0, /* */ + 0x484, /* KANDDrr */ +/* Table5465 */ + 0x0, /* */ + 0x486, /* KANDNDrr */ +/* Table5467 */ + 0x0, /* */ + 0x4a4, /* KORDrr */ +/* Table5469 */ + 0x0, /* */ + 0x4bb, /* KXNORDrr */ +/* Table5471 */ + 0x0, /* */ + 0x4bf, /* KXORDrr */ +/* Table5473 */ + 0x0, /* */ + 0x480, /* KADDDrr */ +/* Table5475 */ + 0x1f4d, /* VMOVUPSZ128rm */ + 0x1f50, /* VMOVUPSZ128rr */ +/* Table5477 */ + 0x1f4b, /* VMOVUPSZ128mr */ + 0x1f51, /* VMOVUPSZ128rr_REV */ +/* Table5479 */ + 0x1ea3, /* VMOVLPSZ128rm */ + 0x1e92, /* VMOVHLPSZrr */ +/* Table5481 */ + 0x1ea2, /* VMOVLPSZ128mr */ + 0x0, /* */ +/* Table5483 */ + 0x3af1, /* VUNPCKLPSZ128rm */ + 0x3af7, /* VUNPCKLPSZ128rr */ +/* Table5485 */ + 0x3ab3, /* VUNPCKHPSZ128rm */ + 0x3ab9, /* VUNPCKHPSZ128rr */ +/* Table5487 */ + 0x1e99, /* VMOVHPSZ128rm */ + 0x1e9c, /* VMOVLHPSZrr */ +/* Table5489 */ + 0x1e98, /* VMOVHPSZ128mr */ + 0x0, /* */ +/* Table5491 */ + 0x1d7b, /* VMOVAPSZ128rm */ + 0x1d7e, /* VMOVAPSZ128rr */ +/* Table5493 */ + 0x1d79, /* VMOVAPSZ128mr */ + 0x1d7f, /* VMOVAPSZ128rr_REV */ +/* Table5495 */ + 0x1eba, /* VMOVNTPSZ128mr */ + 0x0, /* */ +/* Table5497 */ + 0x3a89, /* VUCOMISSZrm */ + 0x3a8b, /* VUCOMISSZrr */ +/* Table5499 */ + 0xddf, /* VCOMISSZrm */ + 0xde1, /* VCOMISSZrr */ +/* Table5501 */ + 0x39d7, /* VSQRTPSZ128m */ + 0x39dd, /* VSQRTPSZ128r */ +/* Table5503 */ + 0xc83, /* VANDPSZ128rm */ + 0xc89, /* VANDPSZ128rr */ +/* Table5505 */ + 0xc45, /* VANDNPSZ128rm */ + 0xc4b, /* VANDNPSZ128rr */ +/* Table5507 */ + 0x200a, /* VORPSZ128rm */ + 0x2010, /* VORPSZ128rr */ +/* Table5509 */ + 0x3b2f, /* VXORPSZ128rm */ + 0x3b35, /* VXORPSZ128rr */ +/* Table5511 */ + 0xb7c, /* VADDPSZ128rm */ + 0xb82, /* VADDPSZ128rr */ +/* Table5513 */ + 0x1fa5, /* VMULPSZ128rm */ + 0x1fab, /* VMULPSZ128rr */ +/* Table5515 */ + 0xf22, /* VCVTPS2PDZ128rm */ + 0xf28, /* VCVTPS2PDZ128rr */ +/* Table5517 */ + 0xe27, /* VCVTDQ2PSZ128rm */ + 0xe2d, /* VCVTDQ2PSZ128rr */ +/* Table5519 */ + 0x3a3a, /* VSUBPSZ128rm */ + 0x3a40, /* VSUBPSZ128rr */ +/* Table5521 */ + 0x1d02, /* VMINPSZ128rm */ + 0x1d08, /* VMINPSZ128rr */ +/* Table5523 */ + 0x123e, /* VDIVPSZ128rm */ + 0x1244, /* VDIVPSZ128rr */ +/* Table5525 */ + 0x1c57, /* VMAXPSZ128rm */ + 0x1c5d, /* VMAXPSZ128rr */ +/* Table5527 */ + 0x110c, /* VCVTTPS2UDQZ128rm */ + 0x1112, /* VCVTTPS2UDQZ128rr */ +/* Table5529 */ + 0xf76, /* VCVTPS2UDQZ128rm */ + 0xf7c, /* VCVTPS2UDQZ128rr */ +/* Table5531 */ + 0xd86, /* VCMPPSZ128rmi */ + 0xd8a, /* VCMPPSZ128rri */ +/* Table5533 */ + 0x3999, /* VSHUFPSZ128rmi */ + 0x399c, /* VSHUFPSZ128rri */ +/* Table5535 */ + 0x1f11, /* VMOVSSZrm */ + 0x1f14, /* VMOVSSZrr */ +/* Table5537 */ + 0x1f0f, /* VMOVSSZmr */ + 0x1f15, /* VMOVSSZrr_REV */ +/* Table5539 */ + 0x1ef7, /* VMOVSLDUPZ128rm */ + 0x1efa, /* VMOVSLDUPZ128rr */ +/* Table5541 */ + 0x1ee1, /* VMOVSHDUPZ128rm */ + 0x1ee4, /* VMOVSHDUPZ128rr */ +/* Table5543 */ + 0x1016, /* VCVTSI2SSZrm */ + 0x1018, /* VCVTSI2SSZrr */ +/* Table5545 */ + 0x116e, /* VCVTTSS2SIZrm_Int */ + 0x1170, /* VCVTTSS2SIZrr_Int */ +/* Table5547 */ + 0x1045, /* VCVTSS2SIZrm_Int */ + 0x1046, /* VCVTSS2SIZrr_Int */ +/* Table5549 */ + 0x3a07, /* VSQRTSSZm_Int */ + 0x3a0b, /* VSQRTSSZr_Int */ +/* Table5551 */ + 0xbac, /* VADDSSZrm_Int */ + 0xbb0, /* VADDSSZrr_Int */ +/* Table5553 */ + 0x1fd5, /* VMULSSZrm_Int */ + 0x1fd9, /* VMULSSZrr_Int */ +/* Table5555 */ + 0x1032, /* VCVTSS2SDZrm_Int */ + 0x1036, /* VCVTSS2SDZrr_Int */ +/* Table5557 */ + 0x10ce, /* VCVTTPS2DQZ128rm */ + 0x10d4, /* VCVTTPS2DQZ128rr */ +/* Table5559 */ + 0x3a6a, /* VSUBSSZrm_Int */ + 0x3a6e, /* VSUBSSZrr_Int */ +/* Table5561 */ + 0x1d32, /* VMINSSZrm_Int */ + 0x1d36, /* VMINSSZrr_Int */ +/* Table5563 */ + 0x126e, /* VDIVSSZrm_Int */ + 0x1272, /* VDIVSSZrr_Int */ +/* Table5565 */ + 0x1c87, /* VMAXSSZrm_Int */ + 0x1c8b, /* VMAXSSZrr_Int */ +/* Table5567 */ + 0x1e29, /* VMOVDQU32Z128rm */ + 0x1e2c, /* VMOVDQU32Z128rr */ +/* Table5569 */ + 0x3187, /* VPSHUFHWZ128mi */ + 0x318a, /* VPSHUFHWZ128ri */ +/* Table5571 */ + 0x117c, /* VCVTTSS2USIZrm_Int */ + 0x117e, /* VCVTTSS2USIZrr_Int */ +/* Table5573 */ + 0x104d, /* VCVTSS2USIZrm_Int */ + 0x104e, /* VCVTSS2USIZrr_Int */ +/* Table5575 */ + 0x1180, /* VCVTUDQ2PDZ128rm */ + 0x1186, /* VCVTUDQ2PDZ128rr */ +/* Table5577 */ + 0x11f9, /* VCVTUSI2SSZrm */ + 0x11fb, /* VCVTUSI2SSZrr */ +/* Table5579 */ + 0x1e27, /* VMOVDQU32Z128mr */ + 0x1e2d, /* VMOVDQU32Z128rr_REV */ +/* Table5581 */ + 0xdc3, /* VCMPSSZrm_Int */ + 0xdc8, /* VCMPSSZrr_Int */ +/* Table5583 */ + 0xe08, /* VCVTDQ2PDZ128rm */ + 0xe0e, /* VCVTDQ2PDZ128rr */ +/* Table5585 */ + 0x100d, /* VCVTSI2SDZrm */ + 0x100f, /* VCVTSI2SDZrr */ +/* Table5587 */ + 0x1152, /* VCVTTSD2SIZrm_Int */ + 0x1154, /* VCVTTSD2SIZrr_Int */ +/* Table5589 */ + 0xff3, /* VCVTSD2SIZrm_Int */ + 0xff4, /* VCVTSD2SIZrr_Int */ +/* Table5591 */ + 0x1e6b, /* VMOVDQU8Z128rm */ + 0x1e6e, /* VMOVDQU8Z128rr */ +/* Table5593 */ + 0x319d, /* VPSHUFLWZ128mi */ + 0x31a0, /* VPSHUFLWZ128ri */ +/* Table5595 */ + 0x1160, /* VCVTTSD2USIZrm_Int */ + 0x1162, /* VCVTTSD2USIZrr_Int */ +/* Table5597 */ + 0x100a, /* VCVTSD2USIZrm_Int */ + 0x100b, /* VCVTSD2USIZrr_Int */ +/* Table5599 */ + 0x119b, /* VCVTUDQ2PSZ128rm */ + 0x11a1, /* VCVTUDQ2PSZ128rr */ +/* Table5601 */ + 0x11f5, /* VCVTUSI2SDZrm */ + 0x11f7, /* VCVTUSI2SDZrr */ +/* Table5603 */ + 0x1e69, /* VMOVDQU8Z128mr */ + 0x1e6f, /* VMOVDQU8Z128rr_REV */ +/* Table5605 */ + 0xf00, /* VCVTPS2DQZ128rm */ + 0xf06, /* VCVTPS2DQZ128rr */ +/* Table5607 */ + 0x3643, /* VPUNPCKLBWZ128rm */ + 0x3646, /* VPUNPCKLBWZ128rr */ +/* Table5609 */ + 0x3697, /* VPUNPCKLWDZ128rm */ + 0x369a, /* VPUNPCKLWDZ128rr */ +/* Table5611 */ + 0x3659, /* VPUNPCKLDQZ128rm */ + 0x365f, /* VPUNPCKLDQZ128rr */ +/* Table5613 */ + 0x20b4, /* VPACKSSWBZ128rm */ + 0x20b7, /* VPACKSSWBZ128rr */ +/* Table5615 */ + 0x23fd, /* VPCMPGTBZ128rm */ + 0x23ff, /* VPCMPGTBZ128rr */ +/* Table5617 */ + 0x2439, /* VPCMPGTWZ128rm */ + 0x243b, /* VPCMPGTWZ128rr */ +/* Table5619 */ + 0x240d, /* VPCMPGTDZ128rm */ + 0x2411, /* VPCMPGTDZ128rr */ +/* Table5621 */ + 0x20e9, /* VPACKUSWBZ128rm */ + 0x20ec, /* VPACKUSWBZ128rr */ +/* Table5623 */ + 0x35d9, /* VPUNPCKHBWZ128rm */ + 0x35dc, /* VPUNPCKHBWZ128rr */ +/* Table5625 */ + 0x362d, /* VPUNPCKHWDZ128rm */ + 0x3630, /* VPUNPCKHWDZ128rr */ +/* Table5627 */ + 0x35ef, /* VPUNPCKHDQZ128rm */ + 0x35f5, /* VPUNPCKHDQZ128rr */ +/* Table5629 */ + 0x2095, /* VPACKSSDWZ128rm */ + 0x209b, /* VPACKSSDWZ128rr */ +/* Table5631 */ + 0x1db4, /* VMOVDI2PDIZrm */ + 0x1db5, /* VMOVDI2PDIZrr */ +/* Table5633 */ + 0x1dbe, /* VMOVDQA32Z128rm */ + 0x1dc1, /* VMOVDQA32Z128rr */ +/* Table5635 */ + 0x316b, /* VPSHUFDZ128mi */ + 0x316e, /* VPSHUFDZ128ri */ +/* Table5637 */ + 0x0, /* */ + 0x0, /* */ + 0x343c, /* VPSRLWZ128mi */ + 0x0, /* */ + 0x3354, /* VPSRAWZ128mi */ + 0x0, /* */ + 0x327e, /* VPSLLWZ128mi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x343f, /* VPSRLWZ128ri */ + 0x0, /* */ + 0x3357, /* VPSRAWZ128ri */ + 0x0, /* */ + 0x3281, /* VPSLLWZ128ri */ + 0x0, /* */ +/* Table5653 */ + 0x2f6d, /* VPRORDZ128mi */ + 0x2f01, /* VPROLDZ128mi */ + 0x3389, /* VPSRLDZ128mi */ + 0x0, /* */ + 0x32ab, /* VPSRADZ128mi */ + 0x0, /* */ + 0x31cb, /* VPSLLDZ128mi */ + 0x0, /* */ + 0x2f70, /* VPRORDZ128ri */ + 0x2f04, /* VPROLDZ128ri */ + 0x338c, /* VPSRLDZ128ri */ + 0x0, /* */ + 0x32ae, /* VPSRADZ128ri */ + 0x0, /* */ + 0x31ce, /* VPSLLDZ128ri */ + 0x0, /* */ +/* Table5669 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x337c, /* VPSRLDQZ128rm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x31be, /* VPSLLDQZ128rm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x337d, /* VPSRLDQZ128rr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x31bf, /* VPSLLDQZ128rr */ +/* Table5685 */ + 0x23ad, /* VPCMPEQBZ128rm */ + 0x23af, /* VPCMPEQBZ128rr */ +/* Table5687 */ + 0x23e9, /* VPCMPEQWZ128rm */ + 0x23eb, /* VPCMPEQWZ128rr */ +/* Table5689 */ + 0x23bd, /* VPCMPEQDZ128rm */ + 0x23c1, /* VPCMPEQDZ128rr */ +/* Table5691 */ + 0x112a, /* VCVTTPS2UQQZ128rm */ + 0x1130, /* VCVTTPS2UQQZ128rr */ +/* Table5693 */ + 0xf94, /* VCVTPS2UQQZ128rm */ + 0xf9a, /* VCVTPS2UQQZ128rr */ +/* Table5695 */ + 0x10ee, /* VCVTTPS2QQZ128rm */ + 0x10f4, /* VCVTTPS2QQZ128rr */ +/* Table5697 */ + 0xf58, /* VCVTPS2QQZ128rm */ + 0xf5e, /* VCVTPS2QQZ128rr */ +/* Table5699 */ + 0x1ebe, /* VMOVPDI2DIZmr */ + 0x1ebf, /* VMOVPDI2DIZrr */ +/* Table5701 */ + 0x1dbc, /* VMOVDQA32Z128mr */ + 0x1dc2, /* VMOVDQA32Z128rr_REV */ +/* Table5703 */ + 0x28f7, /* VPINSRWZrm */ + 0x28f8, /* VPINSRWZrr */ +/* Table5705 */ + 0x0, /* */ + 0x289a, /* VPEXTRWZrr */ +/* Table5707 */ + 0x3442, /* VPSRLWZ128rm */ + 0x3445, /* VPSRLWZ128rr */ +/* Table5709 */ + 0x338f, /* VPSRLDZ128rm */ + 0x3392, /* VPSRLDZ128rr */ +/* Table5711 */ + 0x2e18, /* VPMULLWZ128rm */ + 0x2e1b, /* VPMULLWZ128rr */ +/* Table5713 */ + 0x34e5, /* VPSUBUSBZ128rm */ + 0x34e8, /* VPSUBUSBZ128rr */ +/* Table5715 */ + 0x34fb, /* VPSUBUSWZ128rm */ + 0x34fe, /* VPSUBUSWZ128rr */ +/* Table5717 */ + 0x2ae7, /* VPMINUBZ128rm */ + 0x2aea, /* VPMINUBZ128rr */ +/* Table5719 */ + 0x21d5, /* VPANDDZ128rm */ + 0x21db, /* VPANDDZ128rr */ +/* Table5721 */ + 0x217f, /* VPADDUSBZ128rm */ + 0x2182, /* VPADDUSBZ128rr */ +/* Table5723 */ + 0x2195, /* VPADDUSWZ128rm */ + 0x2198, /* VPADDUSWZ128rr */ +/* Table5725 */ + 0x2a1b, /* VPMAXUBZ128rm */ + 0x2a1e, /* VPMAXUBZ128rr */ +/* Table5727 */ + 0x21f0, /* VPANDNDZ128rm */ + 0x21f6, /* VPANDNDZ128rr */ +/* Table5729 */ + 0x224b, /* VPAVGBZ128rm */ + 0x224e, /* VPAVGBZ128rr */ +/* Table5731 */ + 0x335a, /* VPSRAWZ128rm */ + 0x335d, /* VPSRAWZ128rr */ +/* Table5733 */ + 0x32b1, /* VPSRADZ128rm */ + 0x32b4, /* VPSRADZ128rr */ +/* Table5735 */ + 0x2261, /* VPAVGWZ128rm */ + 0x2264, /* VPAVGWZ128rr */ +/* Table5737 */ + 0x2db2, /* VPMULHUWZ128rm */ + 0x2db5, /* VPMULHUWZ128rr */ +/* Table5739 */ + 0x2dc8, /* VPMULHWZ128rm */ + 0x2dcb, /* VPMULHWZ128rr */ +/* Table5741 */ + 0x1eb0, /* VMOVNTDQZ128mr */ + 0x0, /* */ +/* Table5743 */ + 0x34b9, /* VPSUBSBZ128rm */ + 0x34bc, /* VPSUBSBZ128rr */ +/* Table5745 */ + 0x34cf, /* VPSUBSWZ128rm */ + 0x34d2, /* VPSUBSWZ128rr */ +/* Table5747 */ + 0x2ad1, /* VPMINSWZ128rm */ + 0x2ad4, /* VPMINSWZ128rr */ +/* Table5749 */ + 0x2ec0, /* VPORDZ128rm */ + 0x2ec6, /* VPORDZ128rr */ +/* Table5751 */ + 0x2153, /* VPADDSBZ128rm */ + 0x2156, /* VPADDSBZ128rr */ +/* Table5753 */ + 0x2169, /* VPADDSWZ128rm */ + 0x216c, /* VPADDSWZ128rr */ +/* Table5755 */ + 0x2a05, /* VPMAXSWZ128rm */ + 0x2a08, /* VPMAXSWZ128rr */ +/* Table5757 */ + 0x36ab, /* VPXORDZ128rm */ + 0x36b1, /* VPXORDZ128rr */ +/* Table5759 */ + 0x3284, /* VPSLLWZ128rm */ + 0x3287, /* VPSLLWZ128rr */ +/* Table5761 */ + 0x31d1, /* VPSLLDZ128rm */ + 0x31d4, /* VPSLLDZ128rr */ +/* Table5763 */ + 0x2997, /* VPMADDWDZ128rm */ + 0x299a, /* VPMADDWDZ128rr */ +/* Table5765 */ + 0x2ff0, /* VPSADBWZ128rm */ + 0x2ff1, /* VPSADBWZ128rr */ +/* Table5767 */ + 0x3465, /* VPSUBBZ128rm */ + 0x3468, /* VPSUBBZ128rr */ +/* Table5769 */ + 0x3511, /* VPSUBWZ128rm */ + 0x3514, /* VPSUBWZ128rr */ +/* Table5771 */ + 0x347b, /* VPSUBDZ128rm */ + 0x3481, /* VPSUBDZ128rr */ +/* Table5773 */ + 0x20ff, /* VPADDBZ128rm */ + 0x2102, /* VPADDBZ128rr */ +/* Table5775 */ + 0x21ab, /* VPADDWZ128rm */ + 0x21ae, /* VPADDWZ128rr */ +/* Table5777 */ + 0x2115, /* VPADDDZ128rm */ + 0x211b, /* VPADDDZ128rr */ +/* Table5779 */ + 0xfd0, /* VCVTQQ2PSZ128rm */ + 0xfd6, /* VCVTQQ2PSZ128rr */ +/* Table5781 */ + 0x1090, /* VCVTTPD2UDQZ128rm */ + 0x1096, /* VCVTTPD2UDQZ128rr */ +/* Table5783 */ + 0xea9, /* VCVTPD2UDQZ128rm */ + 0xeaf, /* VCVTPD2UDQZ128rr */ +/* Table5785 */ + 0x1028, /* VCVTSI642SSZrm */ + 0x102a, /* VCVTSI642SSZrr */ +/* Table5787 */ + 0x1165, /* VCVTTSS2SI64Zrm_Int */ + 0x1167, /* VCVTTSS2SI64Zrr_Int */ +/* Table5789 */ + 0x1040, /* VCVTSS2SI64Zrm_Int */ + 0x1041, /* VCVTSS2SI64Zrr_Int */ +/* Table5791 */ + 0x1e4a, /* VMOVDQU64Z128rm */ + 0x1e4d, /* VMOVDQU64Z128rr */ +/* Table5793 */ + 0x1177, /* VCVTTSS2USI64Zrm_Int */ + 0x1179, /* VCVTTSS2USI64Zrr_Int */ +/* Table5795 */ + 0x104a, /* VCVTSS2USI64Zrm_Int */ + 0x104b, /* VCVTSS2USI64Zrr_Int */ +/* Table5797 */ + 0x11b9, /* VCVTUQQ2PDZ128rm */ + 0x11bf, /* VCVTUQQ2PDZ128rr */ +/* Table5799 */ + 0x1203, /* VCVTUSI642SSZrm */ + 0x1205, /* VCVTUSI642SSZrr */ +/* Table5801 */ + 0x1eca, /* VMOVQI2PQIZrm */ + 0x1f70, /* VMOVZPQILo2PQIZrr */ +/* Table5803 */ + 0x1e48, /* VMOVDQU64Z128mr */ + 0x1e4e, /* VMOVDQU64Z128rr_REV */ +/* Table5805 */ + 0xfb2, /* VCVTQQ2PDZ128rm */ + 0xfb8, /* VCVTQQ2PDZ128rr */ +/* Table5807 */ + 0x1ece, /* VMOVSDZrm */ + 0x1ed1, /* VMOVSDZrr */ +/* Table5809 */ + 0x1ecc, /* VMOVSDZmr */ + 0x1ed2, /* VMOVSDZrr_REV */ +/* Table5811 */ + 0x1da0, /* VMOVDDUPZ128rm */ + 0x1da3, /* VMOVDDUPZ128rr */ +/* Table5813 */ + 0x101f, /* VCVTSI642SDZrm */ + 0x1021, /* VCVTSI642SDZrr */ +/* Table5815 */ + 0x1149, /* VCVTTSD2SI64Zrm_Int */ + 0x114b, /* VCVTTSD2SI64Zrr_Int */ +/* Table5817 */ + 0xfee, /* VCVTSD2SI64Zrm_Int */ + 0xfef, /* VCVTSD2SI64Zrr_Int */ +/* Table5819 */ + 0x39f8, /* VSQRTSDZm_Int */ + 0x39fc, /* VSQRTSDZr_Int */ +/* Table5821 */ + 0xb9d, /* VADDSDZrm_Int */ + 0xba1, /* VADDSDZrr_Int */ +/* Table5823 */ + 0x1fc6, /* VMULSDZrm_Int */ + 0x1fca, /* VMULSDZrr_Int */ +/* Table5825 */ + 0xff9, /* VCVTSD2SSZrm_Int */ + 0xffd, /* VCVTSD2SSZrr_Int */ +/* Table5827 */ + 0x3a5b, /* VSUBSDZrm_Int */ + 0x3a5f, /* VSUBSDZrr_Int */ +/* Table5829 */ + 0x1d23, /* VMINSDZrm_Int */ + 0x1d27, /* VMINSDZrr_Int */ +/* Table5831 */ + 0x125f, /* VDIVSDZrm_Int */ + 0x1263, /* VDIVSDZrr_Int */ +/* Table5833 */ + 0x1c78, /* VMAXSDZrm_Int */ + 0x1c7c, /* VMAXSDZrr_Int */ +/* Table5835 */ + 0x1e08, /* VMOVDQU16Z128rm */ + 0x1e0b, /* VMOVDQU16Z128rr */ +/* Table5837 */ + 0x115b, /* VCVTTSD2USI64Zrm_Int */ + 0x115d, /* VCVTTSD2USI64Zrr_Int */ +/* Table5839 */ + 0x1007, /* VCVTSD2USI64Zrm_Int */ + 0x1008, /* VCVTSD2USI64Zrr_Int */ +/* Table5841 */ + 0x11d7, /* VCVTUQQ2PSZ128rm */ + 0x11dd, /* VCVTUQQ2PSZ128rr */ +/* Table5843 */ + 0x11fe, /* VCVTUSI642SDZrm */ + 0x1200, /* VCVTUSI642SDZrr */ +/* Table5845 */ + 0x1e06, /* VMOVDQU16Z128mr */ + 0x1e0c, /* VMOVDQU16Z128rr_REV */ +/* Table5847 */ + 0xdaf, /* VCMPSDZrm_Int */ + 0xdb4, /* VCMPSDZrr_Int */ +/* Table5849 */ + 0xe49, /* VCVTPD2DQZ128rm */ + 0xe4f, /* VCVTPD2DQZ128rr */ +/* Table5851 */ + 0x1f24, /* VMOVUPDZ128rm */ + 0x1f27, /* VMOVUPDZ128rr */ +/* Table5853 */ + 0x1f22, /* VMOVUPDZ128mr */ + 0x1f28, /* VMOVUPDZ128rr_REV */ +/* Table5855 */ + 0x1e9f, /* VMOVLPDZ128rm */ + 0x0, /* */ +/* Table5857 */ + 0x1e9e, /* VMOVLPDZ128mr */ + 0x0, /* */ +/* Table5859 */ + 0x3ad2, /* VUNPCKLPDZ128rm */ + 0x3ad8, /* VUNPCKLPDZ128rr */ +/* Table5861 */ + 0x3a94, /* VUNPCKHPDZ128rm */ + 0x3a9a, /* VUNPCKHPDZ128rr */ +/* Table5863 */ + 0x1e95, /* VMOVHPDZ128rm */ + 0x0, /* */ +/* Table5865 */ + 0x1e94, /* VMOVHPDZ128mr */ + 0x0, /* */ +/* Table5867 */ + 0x1d52, /* VMOVAPDZ128rm */ + 0x1d55, /* VMOVAPDZ128rr */ +/* Table5869 */ + 0x1d50, /* VMOVAPDZ128mr */ + 0x1d56, /* VMOVAPDZ128rr_REV */ +/* Table5871 */ + 0x1eb5, /* VMOVNTPDZ128mr */ + 0x0, /* */ +/* Table5873 */ + 0x3a80, /* VUCOMISDZrm */ + 0x3a82, /* VUCOMISDZrr */ +/* Table5875 */ + 0xdd6, /* VCOMISDZrm */ + 0xdd8, /* VCOMISDZrr */ +/* Table5877 */ + 0x39b5, /* VSQRTPDZ128m */ + 0x39bb, /* VSQRTPDZ128r */ +/* Table5879 */ + 0xc64, /* VANDPDZ128rm */ + 0xc6a, /* VANDPDZ128rr */ +/* Table5881 */ + 0xc26, /* VANDNPDZ128rm */ + 0xc2c, /* VANDNPDZ128rr */ +/* Table5883 */ + 0x1feb, /* VORPDZ128rm */ + 0x1ff1, /* VORPDZ128rr */ +/* Table5885 */ + 0x3b10, /* VXORPDZ128rm */ + 0x3b16, /* VXORPDZ128rr */ +/* Table5887 */ + 0xb5a, /* VADDPDZ128rm */ + 0xb60, /* VADDPDZ128rr */ +/* Table5889 */ + 0x1f83, /* VMULPDZ128rm */ + 0x1f89, /* VMULPDZ128rr */ +/* Table5891 */ + 0xe6b, /* VCVTPD2PSZ128rm */ + 0xe71, /* VCVTPD2PSZ128rr */ +/* Table5893 */ + 0x3a18, /* VSUBPDZ128rm */ + 0x3a1e, /* VSUBPDZ128rr */ +/* Table5895 */ + 0x1ce0, /* VMINPDZ128rm */ + 0x1ce6, /* VMINPDZ128rr */ +/* Table5897 */ + 0x121c, /* VDIVPDZ128rm */ + 0x1222, /* VDIVPDZ128rr */ +/* Table5899 */ + 0x1c35, /* VMAXPDZ128rm */ + 0x1c3b, /* VMAXPDZ128rr */ +/* Table5901 */ + 0x3678, /* VPUNPCKLQDQZ128rm */ + 0x367e, /* VPUNPCKLQDQZ128rr */ +/* Table5903 */ + 0x360e, /* VPUNPCKHQDQZ128rm */ + 0x3614, /* VPUNPCKHQDQZ128rr */ +/* Table5905 */ + 0x1d44, /* VMOV64toPQIZrm */ + 0x1d45, /* VMOV64toPQIZrr */ +/* Table5907 */ + 0x1ddf, /* VMOVDQA64Z128rm */ + 0x1de2, /* VMOVDQA64Z128rr */ +/* Table5909 */ + 0x2f88, /* VPRORQZ128mi */ + 0x2f1c, /* VPROLQZ128mi */ + 0x0, /* */ + 0x0, /* */ + 0x32db, /* VPSRAQZ128mi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x2f8b, /* VPRORQZ128ri */ + 0x2f1f, /* VPROLQZ128ri */ + 0x0, /* */ + 0x0, /* */ + 0x32de, /* VPSRAQZ128ri */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table5925 */ + 0x0, /* */ + 0x0, /* */ + 0x33bc, /* VPSRLQZ128mi */ + 0x337c, /* VPSRLDQZ128rm */ + 0x0, /* */ + 0x0, /* */ + 0x31fe, /* VPSLLQZ128mi */ + 0x31be, /* VPSLLDQZ128rm */ + 0x0, /* */ + 0x0, /* */ + 0x33bf, /* VPSRLQZ128ri */ + 0x337d, /* VPSRLDQZ128rr */ + 0x0, /* */ + 0x0, /* */ + 0x3201, /* VPSLLQZ128ri */ + 0x31bf, /* VPSLLDQZ128rr */ +/* Table5941 */ + 0x10ae, /* VCVTTPD2UQQZ128rm */ + 0x10b4, /* VCVTTPD2UQQZ128rr */ +/* Table5943 */ + 0xec7, /* VCVTPD2UQQZ128rm */ + 0xecd, /* VCVTPD2UQQZ128rr */ +/* Table5945 */ + 0x1072, /* VCVTTPD2QQZ128rm */ + 0x1078, /* VCVTTPD2QQZ128rr */ +/* Table5947 */ + 0xe8b, /* VCVTPD2QQZ128rm */ + 0xe91, /* VCVTPD2QQZ128rr */ +/* Table5949 */ + 0x1ec6, /* VMOVPQIto64Zmr */ + 0x1ec7, /* VMOVPQIto64Zrr */ +/* Table5951 */ + 0x1ddd, /* VMOVDQA64Z128mr */ + 0x1de3, /* VMOVDQA64Z128rr_REV */ +/* Table5953 */ + 0xd56, /* VCMPPDZ128rmi */ + 0xd5a, /* VCMPPDZ128rri */ +/* Table5955 */ + 0x397a, /* VSHUFPDZ128rmi */ + 0x397d, /* VSHUFPDZ128rri */ +/* Table5957 */ + 0x33c2, /* VPSRLQZ128rm */ + 0x33c5, /* VPSRLQZ128rr */ +/* Table5959 */ + 0x2134, /* VPADDQZ128rm */ + 0x213a, /* VPADDQZ128rr */ +/* Table5961 */ + 0x1ec2, /* VMOVPQI2QIZmr */ + 0x1ec3, /* VMOVPQI2QIZrr */ +/* Table5963 */ + 0x222a, /* VPANDQZ128rm */ + 0x2230, /* VPANDQZ128rr */ +/* Table5965 */ + 0x220b, /* VPANDNQZ128rm */ + 0x2211, /* VPANDNQZ128rr */ +/* Table5967 */ + 0x32e1, /* VPSRAQZ128rm */ + 0x32e4, /* VPSRAQZ128rr */ +/* Table5969 */ + 0x1052, /* VCVTTPD2DQZ128rm */ + 0x1058, /* VCVTTPD2DQZ128rr */ +/* Table5971 */ + 0x2edb, /* VPORQZ128rm */ + 0x2ee1, /* VPORQZ128rr */ +/* Table5973 */ + 0x36c6, /* VPXORQZ128rm */ + 0x36cc, /* VPXORQZ128rr */ +/* Table5975 */ + 0x3204, /* VPSLLQZ128rm */ + 0x3207, /* VPSLLQZ128rr */ +/* Table5977 */ + 0x2e49, /* VPMULUDQZ128rm */ + 0x2e4f, /* VPMULUDQZ128rr */ +/* Table5979 */ + 0x349a, /* VPSUBQZ128rm */ + 0x34a0, /* VPSUBQZ128rr */ +/* Table5981 */ + 0x1f58, /* VMOVUPSZ256rm */ + 0x1f5b, /* VMOVUPSZ256rr */ +/* Table5983 */ + 0x1f56, /* VMOVUPSZ256mr */ + 0x1f5c, /* VMOVUPSZ256rr_REV */ +/* Table5985 */ + 0x3afa, /* VUNPCKLPSZ256rm */ + 0x3b00, /* VUNPCKLPSZ256rr */ +/* Table5987 */ + 0x3abc, /* VUNPCKHPSZ256rm */ + 0x3ac2, /* VUNPCKHPSZ256rr */ +/* Table5989 */ + 0x1d86, /* VMOVAPSZ256rm */ + 0x1d89, /* VMOVAPSZ256rr */ +/* Table5991 */ + 0x1d84, /* VMOVAPSZ256mr */ + 0x1d8a, /* VMOVAPSZ256rr_REV */ +/* Table5993 */ + 0x1ebb, /* VMOVNTPSZ256mr */ + 0x0, /* */ +/* Table5995 */ + 0x39e0, /* VSQRTPSZ256m */ + 0x39e6, /* VSQRTPSZ256r */ +/* Table5997 */ + 0xc8c, /* VANDPSZ256rm */ + 0xc92, /* VANDPSZ256rr */ +/* Table5999 */ + 0xc4e, /* VANDNPSZ256rm */ + 0xc54, /* VANDNPSZ256rr */ +/* Table6001 */ + 0x2013, /* VORPSZ256rm */ + 0x2019, /* VORPSZ256rr */ +/* Table6003 */ + 0x3b38, /* VXORPSZ256rm */ + 0x3b3e, /* VXORPSZ256rr */ +/* Table6005 */ + 0xb85, /* VADDPSZ256rm */ + 0xb8b, /* VADDPSZ256rr */ +/* Table6007 */ + 0x1fae, /* VMULPSZ256rm */ + 0x1fb4, /* VMULPSZ256rr */ +/* Table6009 */ + 0xf2b, /* VCVTPS2PDZ256rm */ + 0xf31, /* VCVTPS2PDZ256rr */ +/* Table6011 */ + 0xe30, /* VCVTDQ2PSZ256rm */ + 0xe36, /* VCVTDQ2PSZ256rr */ +/* Table6013 */ + 0x3a43, /* VSUBPSZ256rm */ + 0x3a49, /* VSUBPSZ256rr */ +/* Table6015 */ + 0x1d0b, /* VMINPSZ256rm */ + 0x1d11, /* VMINPSZ256rr */ +/* Table6017 */ + 0x1247, /* VDIVPSZ256rm */ + 0x124d, /* VDIVPSZ256rr */ +/* Table6019 */ + 0x1c60, /* VMAXPSZ256rm */ + 0x1c66, /* VMAXPSZ256rr */ +/* Table6021 */ + 0x1115, /* VCVTTPS2UDQZ256rm */ + 0x111b, /* VCVTTPS2UDQZ256rr */ +/* Table6023 */ + 0xf7f, /* VCVTPS2UDQZ256rm */ + 0xf85, /* VCVTPS2UDQZ256rr */ +/* Table6025 */ + 0xd92, /* VCMPPSZ256rmi */ + 0xd96, /* VCMPPSZ256rri */ +/* Table6027 */ + 0x39a2, /* VSHUFPSZ256rmi */ + 0x39a5, /* VSHUFPSZ256rri */ +/* Table6029 */ + 0x1efd, /* VMOVSLDUPZ256rm */ + 0x1f00, /* VMOVSLDUPZ256rr */ +/* Table6031 */ + 0x1ee7, /* VMOVSHDUPZ256rm */ + 0x1eea, /* VMOVSHDUPZ256rr */ +/* Table6033 */ + 0x10d7, /* VCVTTPS2DQZ256rm */ + 0x10dd, /* VCVTTPS2DQZ256rr */ +/* Table6035 */ + 0x1e34, /* VMOVDQU32Z256rm */ + 0x1e37, /* VMOVDQU32Z256rr */ +/* Table6037 */ + 0x318d, /* VPSHUFHWZ256mi */ + 0x3190, /* VPSHUFHWZ256ri */ +/* Table6039 */ + 0x1189, /* VCVTUDQ2PDZ256rm */ + 0x118f, /* VCVTUDQ2PDZ256rr */ +/* Table6041 */ + 0x1e32, /* VMOVDQU32Z256mr */ + 0x1e38, /* VMOVDQU32Z256rr_REV */ +/* Table6043 */ + 0xe11, /* VCVTDQ2PDZ256rm */ + 0xe17, /* VCVTDQ2PDZ256rr */ +/* Table6045 */ + 0x1e76, /* VMOVDQU8Z256rm */ + 0x1e79, /* VMOVDQU8Z256rr */ +/* Table6047 */ + 0x31a3, /* VPSHUFLWZ256mi */ + 0x31a6, /* VPSHUFLWZ256ri */ +/* Table6049 */ + 0x11a4, /* VCVTUDQ2PSZ256rm */ + 0x11aa, /* VCVTUDQ2PSZ256rr */ +/* Table6051 */ + 0x1e74, /* VMOVDQU8Z256mr */ + 0x1e7a, /* VMOVDQU8Z256rr_REV */ +/* Table6053 */ + 0xf09, /* VCVTPS2DQZ256rm */ + 0xf0f, /* VCVTPS2DQZ256rr */ +/* Table6055 */ + 0x3649, /* VPUNPCKLBWZ256rm */ + 0x364c, /* VPUNPCKLBWZ256rr */ +/* Table6057 */ + 0x369d, /* VPUNPCKLWDZ256rm */ + 0x36a0, /* VPUNPCKLWDZ256rr */ +/* Table6059 */ + 0x3662, /* VPUNPCKLDQZ256rm */ + 0x3668, /* VPUNPCKLDQZ256rr */ +/* Table6061 */ + 0x20ba, /* VPACKSSWBZ256rm */ + 0x20bd, /* VPACKSSWBZ256rr */ +/* Table6063 */ + 0x2401, /* VPCMPGTBZ256rm */ + 0x2403, /* VPCMPGTBZ256rr */ +/* Table6065 */ + 0x243d, /* VPCMPGTWZ256rm */ + 0x243f, /* VPCMPGTWZ256rr */ +/* Table6067 */ + 0x2413, /* VPCMPGTDZ256rm */ + 0x2417, /* VPCMPGTDZ256rr */ +/* Table6069 */ + 0x20ef, /* VPACKUSWBZ256rm */ + 0x20f2, /* VPACKUSWBZ256rr */ +/* Table6071 */ + 0x35df, /* VPUNPCKHBWZ256rm */ + 0x35e2, /* VPUNPCKHBWZ256rr */ +/* Table6073 */ + 0x3633, /* VPUNPCKHWDZ256rm */ + 0x3636, /* VPUNPCKHWDZ256rr */ +/* Table6075 */ + 0x35f8, /* VPUNPCKHDQZ256rm */ + 0x35fe, /* VPUNPCKHDQZ256rr */ +/* Table6077 */ + 0x209e, /* VPACKSSDWZ256rm */ + 0x20a4, /* VPACKSSDWZ256rr */ +/* Table6079 */ + 0x1dc9, /* VMOVDQA32Z256rm */ + 0x1dcc, /* VMOVDQA32Z256rr */ +/* Table6081 */ + 0x3174, /* VPSHUFDZ256mi */ + 0x3177, /* VPSHUFDZ256ri */ +/* Table6083 */ + 0x0, /* */ + 0x0, /* */ + 0x3448, /* VPSRLWZ256mi */ + 0x0, /* */ + 0x3360, /* VPSRAWZ256mi */ + 0x0, /* */ + 0x328a, /* VPSLLWZ256mi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x344b, /* VPSRLWZ256ri */ + 0x0, /* */ + 0x3363, /* VPSRAWZ256ri */ + 0x0, /* */ + 0x328d, /* VPSLLWZ256ri */ + 0x0, /* */ +/* Table6099 */ + 0x2f76, /* VPRORDZ256mi */ + 0x2f0a, /* VPROLDZ256mi */ + 0x3398, /* VPSRLDZ256mi */ + 0x0, /* */ + 0x32ba, /* VPSRADZ256mi */ + 0x0, /* */ + 0x31da, /* VPSLLDZ256mi */ + 0x0, /* */ + 0x2f79, /* VPRORDZ256ri */ + 0x2f0d, /* VPROLDZ256ri */ + 0x339b, /* VPSRLDZ256ri */ + 0x0, /* */ + 0x32bd, /* VPSRADZ256ri */ + 0x0, /* */ + 0x31dd, /* VPSLLDZ256ri */ + 0x0, /* */ +/* Table6115 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x337e, /* VPSRLDQZ256rm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x31c0, /* VPSLLDQZ256rm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x337f, /* VPSRLDQZ256rr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x31c1, /* VPSLLDQZ256rr */ +/* Table6131 */ + 0x23b1, /* VPCMPEQBZ256rm */ + 0x23b3, /* VPCMPEQBZ256rr */ +/* Table6133 */ + 0x23ed, /* VPCMPEQWZ256rm */ + 0x23ef, /* VPCMPEQWZ256rr */ +/* Table6135 */ + 0x23c3, /* VPCMPEQDZ256rm */ + 0x23c7, /* VPCMPEQDZ256rr */ +/* Table6137 */ + 0x1133, /* VCVTTPS2UQQZ256rm */ + 0x1139, /* VCVTTPS2UQQZ256rr */ +/* Table6139 */ + 0xf9d, /* VCVTPS2UQQZ256rm */ + 0xfa3, /* VCVTPS2UQQZ256rr */ +/* Table6141 */ + 0x10f7, /* VCVTTPS2QQZ256rm */ + 0x10fd, /* VCVTTPS2QQZ256rr */ +/* Table6143 */ + 0xf61, /* VCVTPS2QQZ256rm */ + 0xf67, /* VCVTPS2QQZ256rr */ +/* Table6145 */ + 0x1dc7, /* VMOVDQA32Z256mr */ + 0x1dcd, /* VMOVDQA32Z256rr_REV */ +/* Table6147 */ + 0x344e, /* VPSRLWZ256rm */ + 0x3451, /* VPSRLWZ256rr */ +/* Table6149 */ + 0x339e, /* VPSRLDZ256rm */ + 0x33a1, /* VPSRLDZ256rr */ +/* Table6151 */ + 0x2e1e, /* VPMULLWZ256rm */ + 0x2e21, /* VPMULLWZ256rr */ +/* Table6153 */ + 0x34eb, /* VPSUBUSBZ256rm */ + 0x34ee, /* VPSUBUSBZ256rr */ +/* Table6155 */ + 0x3501, /* VPSUBUSWZ256rm */ + 0x3504, /* VPSUBUSWZ256rr */ +/* Table6157 */ + 0x2aed, /* VPMINUBZ256rm */ + 0x2af0, /* VPMINUBZ256rr */ +/* Table6159 */ + 0x21de, /* VPANDDZ256rm */ + 0x21e4, /* VPANDDZ256rr */ +/* Table6161 */ + 0x2185, /* VPADDUSBZ256rm */ + 0x2188, /* VPADDUSBZ256rr */ +/* Table6163 */ + 0x219b, /* VPADDUSWZ256rm */ + 0x219e, /* VPADDUSWZ256rr */ +/* Table6165 */ + 0x2a21, /* VPMAXUBZ256rm */ + 0x2a24, /* VPMAXUBZ256rr */ +/* Table6167 */ + 0x21f9, /* VPANDNDZ256rm */ + 0x21ff, /* VPANDNDZ256rr */ +/* Table6169 */ + 0x2251, /* VPAVGBZ256rm */ + 0x2254, /* VPAVGBZ256rr */ +/* Table6171 */ + 0x3366, /* VPSRAWZ256rm */ + 0x3369, /* VPSRAWZ256rr */ +/* Table6173 */ + 0x32c0, /* VPSRADZ256rm */ + 0x32c3, /* VPSRADZ256rr */ +/* Table6175 */ + 0x2267, /* VPAVGWZ256rm */ + 0x226a, /* VPAVGWZ256rr */ +/* Table6177 */ + 0x2db8, /* VPMULHUWZ256rm */ + 0x2dbb, /* VPMULHUWZ256rr */ +/* Table6179 */ + 0x2dce, /* VPMULHWZ256rm */ + 0x2dd1, /* VPMULHWZ256rr */ +/* Table6181 */ + 0x1eb1, /* VMOVNTDQZ256mr */ + 0x0, /* */ +/* Table6183 */ + 0x34bf, /* VPSUBSBZ256rm */ + 0x34c2, /* VPSUBSBZ256rr */ +/* Table6185 */ + 0x34d5, /* VPSUBSWZ256rm */ + 0x34d8, /* VPSUBSWZ256rr */ +/* Table6187 */ + 0x2ad7, /* VPMINSWZ256rm */ + 0x2ada, /* VPMINSWZ256rr */ +/* Table6189 */ + 0x2ec9, /* VPORDZ256rm */ + 0x2ecf, /* VPORDZ256rr */ +/* Table6191 */ + 0x2159, /* VPADDSBZ256rm */ + 0x215c, /* VPADDSBZ256rr */ +/* Table6193 */ + 0x216f, /* VPADDSWZ256rm */ + 0x2172, /* VPADDSWZ256rr */ +/* Table6195 */ + 0x2a0b, /* VPMAXSWZ256rm */ + 0x2a0e, /* VPMAXSWZ256rr */ +/* Table6197 */ + 0x36b4, /* VPXORDZ256rm */ + 0x36ba, /* VPXORDZ256rr */ +/* Table6199 */ + 0x3290, /* VPSLLWZ256rm */ + 0x3293, /* VPSLLWZ256rr */ +/* Table6201 */ + 0x31e0, /* VPSLLDZ256rm */ + 0x31e3, /* VPSLLDZ256rr */ +/* Table6203 */ + 0x299d, /* VPMADDWDZ256rm */ + 0x29a0, /* VPMADDWDZ256rr */ +/* Table6205 */ + 0x2ff2, /* VPSADBWZ256rm */ + 0x2ff3, /* VPSADBWZ256rr */ +/* Table6207 */ + 0x346b, /* VPSUBBZ256rm */ + 0x346e, /* VPSUBBZ256rr */ +/* Table6209 */ + 0x3517, /* VPSUBWZ256rm */ + 0x351a, /* VPSUBWZ256rr */ +/* Table6211 */ + 0x3484, /* VPSUBDZ256rm */ + 0x348a, /* VPSUBDZ256rr */ +/* Table6213 */ + 0x2105, /* VPADDBZ256rm */ + 0x2108, /* VPADDBZ256rr */ +/* Table6215 */ + 0x21b1, /* VPADDWZ256rm */ + 0x21b4, /* VPADDWZ256rr */ +/* Table6217 */ + 0x211e, /* VPADDDZ256rm */ + 0x2124, /* VPADDDZ256rr */ +/* Table6219 */ + 0xfd9, /* VCVTQQ2PSZ256rm */ + 0xfdf, /* VCVTQQ2PSZ256rr */ +/* Table6221 */ + 0x1099, /* VCVTTPD2UDQZ256rm */ + 0x109f, /* VCVTTPD2UDQZ256rr */ +/* Table6223 */ + 0xeb2, /* VCVTPD2UDQZ256rm */ + 0xeb8, /* VCVTPD2UDQZ256rr */ +/* Table6225 */ + 0x1e55, /* VMOVDQU64Z256rm */ + 0x1e58, /* VMOVDQU64Z256rr */ +/* Table6227 */ + 0x11c2, /* VCVTUQQ2PDZ256rm */ + 0x11c8, /* VCVTUQQ2PDZ256rr */ +/* Table6229 */ + 0x1e53, /* VMOVDQU64Z256mr */ + 0x1e59, /* VMOVDQU64Z256rr_REV */ +/* Table6231 */ + 0xfbb, /* VCVTQQ2PDZ256rm */ + 0xfc1, /* VCVTQQ2PDZ256rr */ +/* Table6233 */ + 0x1da6, /* VMOVDDUPZ256rm */ + 0x1da9, /* VMOVDDUPZ256rr */ +/* Table6235 */ + 0x1e13, /* VMOVDQU16Z256rm */ + 0x1e16, /* VMOVDQU16Z256rr */ +/* Table6237 */ + 0x11e0, /* VCVTUQQ2PSZ256rm */ + 0x11e6, /* VCVTUQQ2PSZ256rr */ +/* Table6239 */ + 0x1e11, /* VMOVDQU16Z256mr */ + 0x1e17, /* VMOVDQU16Z256rr_REV */ +/* Table6241 */ + 0xe52, /* VCVTPD2DQZ256rm */ + 0xe58, /* VCVTPD2DQZ256rr */ +/* Table6243 */ + 0x1f2f, /* VMOVUPDZ256rm */ + 0x1f32, /* VMOVUPDZ256rr */ +/* Table6245 */ + 0x1f2d, /* VMOVUPDZ256mr */ + 0x1f33, /* VMOVUPDZ256rr_REV */ +/* Table6247 */ + 0x3adb, /* VUNPCKLPDZ256rm */ + 0x3ae1, /* VUNPCKLPDZ256rr */ +/* Table6249 */ + 0x3a9d, /* VUNPCKHPDZ256rm */ + 0x3aa3, /* VUNPCKHPDZ256rr */ +/* Table6251 */ + 0x1d5d, /* VMOVAPDZ256rm */ + 0x1d60, /* VMOVAPDZ256rr */ +/* Table6253 */ + 0x1d5b, /* VMOVAPDZ256mr */ + 0x1d61, /* VMOVAPDZ256rr_REV */ +/* Table6255 */ + 0x1eb6, /* VMOVNTPDZ256mr */ + 0x0, /* */ +/* Table6257 */ + 0x39be, /* VSQRTPDZ256m */ + 0x39c4, /* VSQRTPDZ256r */ +/* Table6259 */ + 0xc6d, /* VANDPDZ256rm */ + 0xc73, /* VANDPDZ256rr */ +/* Table6261 */ + 0xc2f, /* VANDNPDZ256rm */ + 0xc35, /* VANDNPDZ256rr */ +/* Table6263 */ + 0x1ff4, /* VORPDZ256rm */ + 0x1ffa, /* VORPDZ256rr */ +/* Table6265 */ + 0x3b19, /* VXORPDZ256rm */ + 0x3b1f, /* VXORPDZ256rr */ +/* Table6267 */ + 0xb63, /* VADDPDZ256rm */ + 0xb69, /* VADDPDZ256rr */ +/* Table6269 */ + 0x1f8c, /* VMULPDZ256rm */ + 0x1f92, /* VMULPDZ256rr */ +/* Table6271 */ + 0xe74, /* VCVTPD2PSZ256rm */ + 0xe7a, /* VCVTPD2PSZ256rr */ +/* Table6273 */ + 0x3a21, /* VSUBPDZ256rm */ + 0x3a27, /* VSUBPDZ256rr */ +/* Table6275 */ + 0x1ce9, /* VMINPDZ256rm */ + 0x1cef, /* VMINPDZ256rr */ +/* Table6277 */ + 0x1225, /* VDIVPDZ256rm */ + 0x122b, /* VDIVPDZ256rr */ +/* Table6279 */ + 0x1c3e, /* VMAXPDZ256rm */ + 0x1c44, /* VMAXPDZ256rr */ +/* Table6281 */ + 0x3681, /* VPUNPCKLQDQZ256rm */ + 0x3687, /* VPUNPCKLQDQZ256rr */ +/* Table6283 */ + 0x3617, /* VPUNPCKHQDQZ256rm */ + 0x361d, /* VPUNPCKHQDQZ256rr */ +/* Table6285 */ + 0x1dea, /* VMOVDQA64Z256rm */ + 0x1ded, /* VMOVDQA64Z256rr */ +/* Table6287 */ + 0x2f91, /* VPRORQZ256mi */ + 0x2f25, /* VPROLQZ256mi */ + 0x0, /* */ + 0x0, /* */ + 0x32ea, /* VPSRAQZ256mi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x2f94, /* VPRORQZ256ri */ + 0x2f28, /* VPROLQZ256ri */ + 0x0, /* */ + 0x0, /* */ + 0x32ed, /* VPSRAQZ256ri */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table6303 */ + 0x0, /* */ + 0x0, /* */ + 0x33cb, /* VPSRLQZ256mi */ + 0x337e, /* VPSRLDQZ256rm */ + 0x0, /* */ + 0x0, /* */ + 0x320d, /* VPSLLQZ256mi */ + 0x31c0, /* VPSLLDQZ256rm */ + 0x0, /* */ + 0x0, /* */ + 0x33ce, /* VPSRLQZ256ri */ + 0x337f, /* VPSRLDQZ256rr */ + 0x0, /* */ + 0x0, /* */ + 0x3210, /* VPSLLQZ256ri */ + 0x31c1, /* VPSLLDQZ256rr */ +/* Table6319 */ + 0x10b7, /* VCVTTPD2UQQZ256rm */ + 0x10bd, /* VCVTTPD2UQQZ256rr */ +/* Table6321 */ + 0xed0, /* VCVTPD2UQQZ256rm */ + 0xed6, /* VCVTPD2UQQZ256rr */ +/* Table6323 */ + 0x107b, /* VCVTTPD2QQZ256rm */ + 0x1081, /* VCVTTPD2QQZ256rr */ +/* Table6325 */ + 0xe94, /* VCVTPD2QQZ256rm */ + 0xe9a, /* VCVTPD2QQZ256rr */ +/* Table6327 */ + 0x1de8, /* VMOVDQA64Z256mr */ + 0x1dee, /* VMOVDQA64Z256rr_REV */ +/* Table6329 */ + 0xd62, /* VCMPPDZ256rmi */ + 0xd66, /* VCMPPDZ256rri */ +/* Table6331 */ + 0x3983, /* VSHUFPDZ256rmi */ + 0x3986, /* VSHUFPDZ256rri */ +/* Table6333 */ + 0x33d1, /* VPSRLQZ256rm */ + 0x33d4, /* VPSRLQZ256rr */ +/* Table6335 */ + 0x213d, /* VPADDQZ256rm */ + 0x2143, /* VPADDQZ256rr */ +/* Table6337 */ + 0x2233, /* VPANDQZ256rm */ + 0x2239, /* VPANDQZ256rr */ +/* Table6339 */ + 0x2214, /* VPANDNQZ256rm */ + 0x221a, /* VPANDNQZ256rr */ +/* Table6341 */ + 0x32f0, /* VPSRAQZ256rm */ + 0x32f3, /* VPSRAQZ256rr */ +/* Table6343 */ + 0x105b, /* VCVTTPD2DQZ256rm */ + 0x1061, /* VCVTTPD2DQZ256rr */ +/* Table6345 */ + 0x2ee4, /* VPORQZ256rm */ + 0x2eea, /* VPORQZ256rr */ +/* Table6347 */ + 0x36cf, /* VPXORQZ256rm */ + 0x36d5, /* VPXORQZ256rr */ +/* Table6349 */ + 0x3213, /* VPSLLQZ256rm */ + 0x3216, /* VPSLLQZ256rr */ +/* Table6351 */ + 0x2e52, /* VPMULUDQZ256rm */ + 0x2e58, /* VPMULUDQZ256rr */ +/* Table6353 */ + 0x34a3, /* VPSUBQZ256rm */ + 0x34a9, /* VPSUBQZ256rr */ +/* Table6355 */ + 0x1f63, /* VMOVUPSZrm */ + 0x1f66, /* VMOVUPSZrr */ +/* Table6357 */ + 0x1f61, /* VMOVUPSZmr */ + 0x1f67, /* VMOVUPSZrr_REV */ +/* Table6359 */ + 0x3b03, /* VUNPCKLPSZrm */ + 0x3b09, /* VUNPCKLPSZrr */ +/* Table6361 */ + 0x3ac5, /* VUNPCKHPSZrm */ + 0x3acb, /* VUNPCKHPSZrr */ +/* Table6363 */ + 0x1d91, /* VMOVAPSZrm */ + 0x1d94, /* VMOVAPSZrr */ +/* Table6365 */ + 0x1d8f, /* VMOVAPSZmr */ + 0x1d95, /* VMOVAPSZrr_REV */ +/* Table6367 */ + 0x1ebc, /* VMOVNTPSZmr */ + 0x0, /* */ +/* Table6369 */ + 0x39e9, /* VSQRTPSZm */ + 0x39ef, /* VSQRTPSZr */ +/* Table6371 */ + 0xc95, /* VANDPSZrm */ + 0xc9b, /* VANDPSZrr */ +/* Table6373 */ + 0xc57, /* VANDNPSZrm */ + 0xc5d, /* VANDNPSZrr */ +/* Table6375 */ + 0x201c, /* VORPSZrm */ + 0x2022, /* VORPSZrr */ +/* Table6377 */ + 0x3b41, /* VXORPSZrm */ + 0x3b47, /* VXORPSZrr */ +/* Table6379 */ + 0xb8e, /* VADDPSZrm */ + 0xb94, /* VADDPSZrr */ +/* Table6381 */ + 0x1fb7, /* VMULPSZrm */ + 0x1fbd, /* VMULPSZrr */ +/* Table6383 */ + 0xf34, /* VCVTPS2PDZrm */ + 0xf3a, /* VCVTPS2PDZrr */ +/* Table6385 */ + 0xe39, /* VCVTDQ2PSZrm */ + 0xe3f, /* VCVTDQ2PSZrr */ +/* Table6387 */ + 0x3a4c, /* VSUBPSZrm */ + 0x3a52, /* VSUBPSZrr */ +/* Table6389 */ + 0x1d14, /* VMINPSZrm */ + 0x1d1a, /* VMINPSZrr */ +/* Table6391 */ + 0x1250, /* VDIVPSZrm */ + 0x1256, /* VDIVPSZrr */ +/* Table6393 */ + 0x1c69, /* VMAXPSZrm */ + 0x1c6f, /* VMAXPSZrr */ +/* Table6395 */ + 0x111e, /* VCVTTPS2UDQZrm */ + 0x1124, /* VCVTTPS2UDQZrr */ +/* Table6397 */ + 0xf88, /* VCVTPS2UDQZrm */ + 0xf8e, /* VCVTPS2UDQZrr */ +/* Table6399 */ + 0xd9e, /* VCMPPSZrmi */ + 0xda2, /* VCMPPSZrri */ +/* Table6401 */ + 0x39ab, /* VSHUFPSZrmi */ + 0x39ae, /* VSHUFPSZrri */ +/* Table6403 */ + 0x1f03, /* VMOVSLDUPZrm */ + 0x1f06, /* VMOVSLDUPZrr */ +/* Table6405 */ + 0x1eed, /* VMOVSHDUPZrm */ + 0x1ef0, /* VMOVSHDUPZrr */ +/* Table6407 */ + 0x10e0, /* VCVTTPS2DQZrm */ + 0x10e6, /* VCVTTPS2DQZrr */ +/* Table6409 */ + 0x1e3f, /* VMOVDQU32Zrm */ + 0x1e42, /* VMOVDQU32Zrr */ +/* Table6411 */ + 0x3193, /* VPSHUFHWZmi */ + 0x3196, /* VPSHUFHWZri */ +/* Table6413 */ + 0x1192, /* VCVTUDQ2PDZrm */ + 0x1198, /* VCVTUDQ2PDZrr */ +/* Table6415 */ + 0x1e3d, /* VMOVDQU32Zmr */ + 0x1e43, /* VMOVDQU32Zrr_REV */ +/* Table6417 */ + 0xe1a, /* VCVTDQ2PDZrm */ + 0xe20, /* VCVTDQ2PDZrr */ +/* Table6419 */ + 0x1e81, /* VMOVDQU8Zrm */ + 0x1e84, /* VMOVDQU8Zrr */ +/* Table6421 */ + 0x31a9, /* VPSHUFLWZmi */ + 0x31ac, /* VPSHUFLWZri */ +/* Table6423 */ + 0x11ad, /* VCVTUDQ2PSZrm */ + 0x11b3, /* VCVTUDQ2PSZrr */ +/* Table6425 */ + 0x1e7f, /* VMOVDQU8Zmr */ + 0x1e85, /* VMOVDQU8Zrr_REV */ +/* Table6427 */ + 0xf12, /* VCVTPS2DQZrm */ + 0xf18, /* VCVTPS2DQZrr */ +/* Table6429 */ + 0x364f, /* VPUNPCKLBWZrm */ + 0x3652, /* VPUNPCKLBWZrr */ +/* Table6431 */ + 0x36a3, /* VPUNPCKLWDZrm */ + 0x36a6, /* VPUNPCKLWDZrr */ +/* Table6433 */ + 0x366b, /* VPUNPCKLDQZrm */ + 0x3671, /* VPUNPCKLDQZrr */ +/* Table6435 */ + 0x20c0, /* VPACKSSWBZrm */ + 0x20c3, /* VPACKSSWBZrr */ +/* Table6437 */ + 0x2405, /* VPCMPGTBZrm */ + 0x2407, /* VPCMPGTBZrr */ +/* Table6439 */ + 0x2441, /* VPCMPGTWZrm */ + 0x2443, /* VPCMPGTWZrr */ +/* Table6441 */ + 0x2419, /* VPCMPGTDZrm */ + 0x241d, /* VPCMPGTDZrr */ +/* Table6443 */ + 0x20f5, /* VPACKUSWBZrm */ + 0x20f8, /* VPACKUSWBZrr */ +/* Table6445 */ + 0x35e5, /* VPUNPCKHBWZrm */ + 0x35e8, /* VPUNPCKHBWZrr */ +/* Table6447 */ + 0x3639, /* VPUNPCKHWDZrm */ + 0x363c, /* VPUNPCKHWDZrr */ +/* Table6449 */ + 0x3601, /* VPUNPCKHDQZrm */ + 0x3607, /* VPUNPCKHDQZrr */ +/* Table6451 */ + 0x20a7, /* VPACKSSDWZrm */ + 0x20ad, /* VPACKSSDWZrr */ +/* Table6453 */ + 0x1dd4, /* VMOVDQA32Zrm */ + 0x1dd7, /* VMOVDQA32Zrr */ +/* Table6455 */ + 0x317d, /* VPSHUFDZmi */ + 0x3180, /* VPSHUFDZri */ +/* Table6457 */ + 0x0, /* */ + 0x0, /* */ + 0x3454, /* VPSRLWZmi */ + 0x0, /* */ + 0x336c, /* VPSRAWZmi */ + 0x0, /* */ + 0x3296, /* VPSLLWZmi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3457, /* VPSRLWZri */ + 0x0, /* */ + 0x336f, /* VPSRAWZri */ + 0x0, /* */ + 0x3299, /* VPSLLWZri */ + 0x0, /* */ +/* Table6473 */ + 0x2f7f, /* VPRORDZmi */ + 0x2f13, /* VPROLDZmi */ + 0x33a7, /* VPSRLDZmi */ + 0x0, /* */ + 0x32c9, /* VPSRADZmi */ + 0x0, /* */ + 0x31e9, /* VPSLLDZmi */ + 0x0, /* */ + 0x2f82, /* VPRORDZri */ + 0x2f16, /* VPROLDZri */ + 0x33aa, /* VPSRLDZri */ + 0x0, /* */ + 0x32cc, /* VPSRADZri */ + 0x0, /* */ + 0x31ec, /* VPSLLDZri */ + 0x0, /* */ +/* Table6489 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3380, /* VPSRLDQZrm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x31c2, /* VPSLLDQZrm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3381, /* VPSRLDQZrr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x31c3, /* VPSLLDQZrr */ +/* Table6505 */ + 0x23b5, /* VPCMPEQBZrm */ + 0x23b7, /* VPCMPEQBZrr */ +/* Table6507 */ + 0x23f1, /* VPCMPEQWZrm */ + 0x23f3, /* VPCMPEQWZrr */ +/* Table6509 */ + 0x23c9, /* VPCMPEQDZrm */ + 0x23cd, /* VPCMPEQDZrr */ +/* Table6511 */ + 0x113c, /* VCVTTPS2UQQZrm */ + 0x1142, /* VCVTTPS2UQQZrr */ +/* Table6513 */ + 0xfa6, /* VCVTPS2UQQZrm */ + 0xfac, /* VCVTPS2UQQZrr */ +/* Table6515 */ + 0x1100, /* VCVTTPS2QQZrm */ + 0x1106, /* VCVTTPS2QQZrr */ +/* Table6517 */ + 0xf6a, /* VCVTPS2QQZrm */ + 0xf70, /* VCVTPS2QQZrr */ +/* Table6519 */ + 0x1dd2, /* VMOVDQA32Zmr */ + 0x1dd8, /* VMOVDQA32Zrr_REV */ +/* Table6521 */ + 0x345a, /* VPSRLWZrm */ + 0x345d, /* VPSRLWZrr */ +/* Table6523 */ + 0x33ad, /* VPSRLDZrm */ + 0x33b0, /* VPSRLDZrr */ +/* Table6525 */ + 0x2e24, /* VPMULLWZrm */ + 0x2e27, /* VPMULLWZrr */ +/* Table6527 */ + 0x34f1, /* VPSUBUSBZrm */ + 0x34f4, /* VPSUBUSBZrr */ +/* Table6529 */ + 0x3507, /* VPSUBUSWZrm */ + 0x350a, /* VPSUBUSWZrr */ +/* Table6531 */ + 0x2af3, /* VPMINUBZrm */ + 0x2af6, /* VPMINUBZrr */ +/* Table6533 */ + 0x21e7, /* VPANDDZrm */ + 0x21ed, /* VPANDDZrr */ +/* Table6535 */ + 0x218b, /* VPADDUSBZrm */ + 0x218e, /* VPADDUSBZrr */ +/* Table6537 */ + 0x21a1, /* VPADDUSWZrm */ + 0x21a4, /* VPADDUSWZrr */ +/* Table6539 */ + 0x2a27, /* VPMAXUBZrm */ + 0x2a2a, /* VPMAXUBZrr */ +/* Table6541 */ + 0x2202, /* VPANDNDZrm */ + 0x2208, /* VPANDNDZrr */ +/* Table6543 */ + 0x2257, /* VPAVGBZrm */ + 0x225a, /* VPAVGBZrr */ +/* Table6545 */ + 0x3372, /* VPSRAWZrm */ + 0x3375, /* VPSRAWZrr */ +/* Table6547 */ + 0x32cf, /* VPSRADZrm */ + 0x32d2, /* VPSRADZrr */ +/* Table6549 */ + 0x226d, /* VPAVGWZrm */ + 0x2270, /* VPAVGWZrr */ +/* Table6551 */ + 0x2dbe, /* VPMULHUWZrm */ + 0x2dc1, /* VPMULHUWZrr */ +/* Table6553 */ + 0x2dd4, /* VPMULHWZrm */ + 0x2dd7, /* VPMULHWZrr */ +/* Table6555 */ + 0x1eb2, /* VMOVNTDQZmr */ + 0x0, /* */ +/* Table6557 */ + 0x34c5, /* VPSUBSBZrm */ + 0x34c8, /* VPSUBSBZrr */ +/* Table6559 */ + 0x34db, /* VPSUBSWZrm */ + 0x34de, /* VPSUBSWZrr */ +/* Table6561 */ + 0x2add, /* VPMINSWZrm */ + 0x2ae0, /* VPMINSWZrr */ +/* Table6563 */ + 0x2ed2, /* VPORDZrm */ + 0x2ed8, /* VPORDZrr */ +/* Table6565 */ + 0x215f, /* VPADDSBZrm */ + 0x2162, /* VPADDSBZrr */ +/* Table6567 */ + 0x2175, /* VPADDSWZrm */ + 0x2178, /* VPADDSWZrr */ +/* Table6569 */ + 0x2a11, /* VPMAXSWZrm */ + 0x2a14, /* VPMAXSWZrr */ +/* Table6571 */ + 0x36bd, /* VPXORDZrm */ + 0x36c3, /* VPXORDZrr */ +/* Table6573 */ + 0x329c, /* VPSLLWZrm */ + 0x329f, /* VPSLLWZrr */ +/* Table6575 */ + 0x31ef, /* VPSLLDZrm */ + 0x31f2, /* VPSLLDZrr */ +/* Table6577 */ + 0x29a3, /* VPMADDWDZrm */ + 0x29a6, /* VPMADDWDZrr */ +/* Table6579 */ + 0x2ff4, /* VPSADBWZrm */ + 0x2ff5, /* VPSADBWZrr */ +/* Table6581 */ + 0x3471, /* VPSUBBZrm */ + 0x3474, /* VPSUBBZrr */ +/* Table6583 */ + 0x351d, /* VPSUBWZrm */ + 0x3520, /* VPSUBWZrr */ +/* Table6585 */ + 0x348d, /* VPSUBDZrm */ + 0x3493, /* VPSUBDZrr */ +/* Table6587 */ + 0x210b, /* VPADDBZrm */ + 0x210e, /* VPADDBZrr */ +/* Table6589 */ + 0x21b7, /* VPADDWZrm */ + 0x21ba, /* VPADDWZrr */ +/* Table6591 */ + 0x2127, /* VPADDDZrm */ + 0x212d, /* VPADDDZrr */ +/* Table6593 */ + 0xfe2, /* VCVTQQ2PSZrm */ + 0xfe8, /* VCVTQQ2PSZrr */ +/* Table6595 */ + 0x10a2, /* VCVTTPD2UDQZrm */ + 0x10a8, /* VCVTTPD2UDQZrr */ +/* Table6597 */ + 0xebb, /* VCVTPD2UDQZrm */ + 0xec1, /* VCVTPD2UDQZrr */ +/* Table6599 */ + 0x1e60, /* VMOVDQU64Zrm */ + 0x1e63, /* VMOVDQU64Zrr */ +/* Table6601 */ + 0x11cb, /* VCVTUQQ2PDZrm */ + 0x11d1, /* VCVTUQQ2PDZrr */ +/* Table6603 */ + 0x1e5e, /* VMOVDQU64Zmr */ + 0x1e64, /* VMOVDQU64Zrr_REV */ +/* Table6605 */ + 0xfc4, /* VCVTQQ2PDZrm */ + 0xfca, /* VCVTQQ2PDZrr */ +/* Table6607 */ + 0x1dac, /* VMOVDDUPZrm */ + 0x1daf, /* VMOVDDUPZrr */ +/* Table6609 */ + 0x1e1e, /* VMOVDQU16Zrm */ + 0x1e21, /* VMOVDQU16Zrr */ +/* Table6611 */ + 0x11e9, /* VCVTUQQ2PSZrm */ + 0x11ef, /* VCVTUQQ2PSZrr */ +/* Table6613 */ + 0x1e1c, /* VMOVDQU16Zmr */ + 0x1e22, /* VMOVDQU16Zrr_REV */ +/* Table6615 */ + 0xe5b, /* VCVTPD2DQZrm */ + 0xe61, /* VCVTPD2DQZrr */ +/* Table6617 */ + 0x1f3a, /* VMOVUPDZrm */ + 0x1f3d, /* VMOVUPDZrr */ +/* Table6619 */ + 0x1f38, /* VMOVUPDZmr */ + 0x1f3e, /* VMOVUPDZrr_REV */ +/* Table6621 */ + 0x3ae4, /* VUNPCKLPDZrm */ + 0x3aea, /* VUNPCKLPDZrr */ +/* Table6623 */ + 0x3aa6, /* VUNPCKHPDZrm */ + 0x3aac, /* VUNPCKHPDZrr */ +/* Table6625 */ + 0x1d68, /* VMOVAPDZrm */ + 0x1d6b, /* VMOVAPDZrr */ +/* Table6627 */ + 0x1d66, /* VMOVAPDZmr */ + 0x1d6c, /* VMOVAPDZrr_REV */ +/* Table6629 */ + 0x1eb7, /* VMOVNTPDZmr */ + 0x0, /* */ +/* Table6631 */ + 0x39c7, /* VSQRTPDZm */ + 0x39cd, /* VSQRTPDZr */ +/* Table6633 */ + 0xc76, /* VANDPDZrm */ + 0xc7c, /* VANDPDZrr */ +/* Table6635 */ + 0xc38, /* VANDNPDZrm */ + 0xc3e, /* VANDNPDZrr */ +/* Table6637 */ + 0x1ffd, /* VORPDZrm */ + 0x2003, /* VORPDZrr */ +/* Table6639 */ + 0x3b22, /* VXORPDZrm */ + 0x3b28, /* VXORPDZrr */ +/* Table6641 */ + 0xb6c, /* VADDPDZrm */ + 0xb72, /* VADDPDZrr */ +/* Table6643 */ + 0x1f95, /* VMULPDZrm */ + 0x1f9b, /* VMULPDZrr */ +/* Table6645 */ + 0xe7d, /* VCVTPD2PSZrm */ + 0xe83, /* VCVTPD2PSZrr */ +/* Table6647 */ + 0x3a2a, /* VSUBPDZrm */ + 0x3a30, /* VSUBPDZrr */ +/* Table6649 */ + 0x1cf2, /* VMINPDZrm */ + 0x1cf8, /* VMINPDZrr */ +/* Table6651 */ + 0x122e, /* VDIVPDZrm */ + 0x1234, /* VDIVPDZrr */ +/* Table6653 */ + 0x1c47, /* VMAXPDZrm */ + 0x1c4d, /* VMAXPDZrr */ +/* Table6655 */ + 0x368a, /* VPUNPCKLQDQZrm */ + 0x3690, /* VPUNPCKLQDQZrr */ +/* Table6657 */ + 0x3620, /* VPUNPCKHQDQZrm */ + 0x3626, /* VPUNPCKHQDQZrr */ +/* Table6659 */ + 0x1df5, /* VMOVDQA64Zrm */ + 0x1df8, /* VMOVDQA64Zrr */ +/* Table6661 */ + 0x2f9a, /* VPRORQZmi */ + 0x2f2e, /* VPROLQZmi */ + 0x0, /* */ + 0x0, /* */ + 0x32f9, /* VPSRAQZmi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x2f9d, /* VPRORQZri */ + 0x2f31, /* VPROLQZri */ + 0x0, /* */ + 0x0, /* */ + 0x32fc, /* VPSRAQZri */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table6677 */ + 0x0, /* */ + 0x0, /* */ + 0x33da, /* VPSRLQZmi */ + 0x3380, /* VPSRLDQZrm */ + 0x0, /* */ + 0x0, /* */ + 0x321c, /* VPSLLQZmi */ + 0x31c2, /* VPSLLDQZrm */ + 0x0, /* */ + 0x0, /* */ + 0x33dd, /* VPSRLQZri */ + 0x3381, /* VPSRLDQZrr */ + 0x0, /* */ + 0x0, /* */ + 0x321f, /* VPSLLQZri */ + 0x31c3, /* VPSLLDQZrr */ +/* Table6693 */ + 0x10c0, /* VCVTTPD2UQQZrm */ + 0x10c6, /* VCVTTPD2UQQZrr */ +/* Table6695 */ + 0xed9, /* VCVTPD2UQQZrm */ + 0xedf, /* VCVTPD2UQQZrr */ +/* Table6697 */ + 0x1084, /* VCVTTPD2QQZrm */ + 0x108a, /* VCVTTPD2QQZrr */ +/* Table6699 */ + 0xe9d, /* VCVTPD2QQZrm */ + 0xea3, /* VCVTPD2QQZrr */ +/* Table6701 */ + 0x1df3, /* VMOVDQA64Zmr */ + 0x1df9, /* VMOVDQA64Zrr_REV */ +/* Table6703 */ + 0xd6e, /* VCMPPDZrmi */ + 0xd72, /* VCMPPDZrri */ +/* Table6705 */ + 0x398c, /* VSHUFPDZrmi */ + 0x398f, /* VSHUFPDZrri */ +/* Table6707 */ + 0x33e0, /* VPSRLQZrm */ + 0x33e3, /* VPSRLQZrr */ +/* Table6709 */ + 0x2146, /* VPADDQZrm */ + 0x214c, /* VPADDQZrr */ +/* Table6711 */ + 0x223c, /* VPANDQZrm */ + 0x2242, /* VPANDQZrr */ +/* Table6713 */ + 0x221d, /* VPANDNQZrm */ + 0x2223, /* VPANDNQZrr */ +/* Table6715 */ + 0x32ff, /* VPSRAQZrm */ + 0x3302, /* VPSRAQZrr */ +/* Table6717 */ + 0x1064, /* VCVTTPD2DQZrm */ + 0x106a, /* VCVTTPD2DQZrr */ +/* Table6719 */ + 0x2eed, /* VPORQZrm */ + 0x2ef3, /* VPORQZrr */ +/* Table6721 */ + 0x36d8, /* VPXORQZrm */ + 0x36de, /* VPXORQZrr */ +/* Table6723 */ + 0x3222, /* VPSLLQZrm */ + 0x3225, /* VPSLLQZrr */ +/* Table6725 */ + 0x2e5b, /* VPMULUDQZrm */ + 0x2e61, /* VPMULUDQZrr */ +/* Table6727 */ + 0x34ac, /* VPSUBQZrm */ + 0x34b2, /* VPSUBQZrr */ +/* Table6729 */ + 0x1f4e, /* VMOVUPSZ128rmk */ + 0x1f52, /* VMOVUPSZ128rrk */ +/* Table6731 */ + 0x1f4c, /* VMOVUPSZ128mrk */ + 0x1f53, /* VMOVUPSZ128rrk_REV */ +/* Table6733 */ + 0x3af5, /* VUNPCKLPSZ128rmk */ + 0x3af8, /* VUNPCKLPSZ128rrk */ +/* Table6735 */ + 0x3ab7, /* VUNPCKHPSZ128rmk */ + 0x3aba, /* VUNPCKHPSZ128rrk */ +/* Table6737 */ + 0x1d7c, /* VMOVAPSZ128rmk */ + 0x1d80, /* VMOVAPSZ128rrk */ +/* Table6739 */ + 0x1d7a, /* VMOVAPSZ128mrk */ + 0x1d81, /* VMOVAPSZ128rrk_REV */ +/* Table6741 */ + 0x39db, /* VSQRTPSZ128mk */ + 0x39de, /* VSQRTPSZ128rk */ +/* Table6743 */ + 0xc87, /* VANDPSZ128rmk */ + 0xc8a, /* VANDPSZ128rrk */ +/* Table6745 */ + 0xc49, /* VANDNPSZ128rmk */ + 0xc4c, /* VANDNPSZ128rrk */ +/* Table6747 */ + 0x200e, /* VORPSZ128rmk */ + 0x2011, /* VORPSZ128rrk */ +/* Table6749 */ + 0x3b33, /* VXORPSZ128rmk */ + 0x3b36, /* VXORPSZ128rrk */ +/* Table6751 */ + 0xb80, /* VADDPSZ128rmk */ + 0xb83, /* VADDPSZ128rrk */ +/* Table6753 */ + 0x1fa9, /* VMULPSZ128rmk */ + 0x1fac, /* VMULPSZ128rrk */ +/* Table6755 */ + 0xf26, /* VCVTPS2PDZ128rmk */ + 0xf29, /* VCVTPS2PDZ128rrk */ +/* Table6757 */ + 0xe2b, /* VCVTDQ2PSZ128rmk */ + 0xe2e, /* VCVTDQ2PSZ128rrk */ +/* Table6759 */ + 0x3a3e, /* VSUBPSZ128rmk */ + 0x3a41, /* VSUBPSZ128rrk */ +/* Table6761 */ + 0x1d06, /* VMINPSZ128rmk */ + 0x1d09, /* VMINPSZ128rrk */ +/* Table6763 */ + 0x1242, /* VDIVPSZ128rmk */ + 0x1245, /* VDIVPSZ128rrk */ +/* Table6765 */ + 0x1c5b, /* VMAXPSZ128rmk */ + 0x1c5e, /* VMAXPSZ128rrk */ +/* Table6767 */ + 0x1110, /* VCVTTPS2UDQZ128rmk */ + 0x1113, /* VCVTTPS2UDQZ128rrk */ +/* Table6769 */ + 0xf7a, /* VCVTPS2UDQZ128rmk */ + 0xf7d, /* VCVTPS2UDQZ128rrk */ +/* Table6771 */ + 0xd89, /* VCMPPSZ128rmik */ + 0xd8d, /* VCMPPSZ128rrik */ +/* Table6773 */ + 0x399a, /* VSHUFPSZ128rmik */ + 0x399d, /* VSHUFPSZ128rrik */ +/* Table6775 */ + 0x1f12, /* VMOVSSZrmk */ + 0x1f16, /* VMOVSSZrrk */ +/* Table6777 */ + 0x1f10, /* VMOVSSZmrk */ + 0x1f17, /* VMOVSSZrrk_REV */ +/* Table6779 */ + 0x1ef8, /* VMOVSLDUPZ128rmk */ + 0x1efb, /* VMOVSLDUPZ128rrk */ +/* Table6781 */ + 0x1ee2, /* VMOVSHDUPZ128rmk */ + 0x1ee5, /* VMOVSHDUPZ128rrk */ +/* Table6783 */ + 0x3a08, /* VSQRTSSZm_Intk */ + 0x3a0c, /* VSQRTSSZr_Intk */ +/* Table6785 */ + 0xbad, /* VADDSSZrm_Intk */ + 0xbb1, /* VADDSSZrr_Intk */ +/* Table6787 */ + 0x1fd6, /* VMULSSZrm_Intk */ + 0x1fda, /* VMULSSZrr_Intk */ +/* Table6789 */ + 0x1033, /* VCVTSS2SDZrm_Intk */ + 0x1037, /* VCVTSS2SDZrr_Intk */ +/* Table6791 */ + 0x10d2, /* VCVTTPS2DQZ128rmk */ + 0x10d5, /* VCVTTPS2DQZ128rrk */ +/* Table6793 */ + 0x3a6b, /* VSUBSSZrm_Intk */ + 0x3a6f, /* VSUBSSZrr_Intk */ +/* Table6795 */ + 0x1d33, /* VMINSSZrm_Intk */ + 0x1d37, /* VMINSSZrr_Intk */ +/* Table6797 */ + 0x126f, /* VDIVSSZrm_Intk */ + 0x1273, /* VDIVSSZrr_Intk */ +/* Table6799 */ + 0x1c88, /* VMAXSSZrm_Intk */ + 0x1c8c, /* VMAXSSZrr_Intk */ +/* Table6801 */ + 0x1e2a, /* VMOVDQU32Z128rmk */ + 0x1e2e, /* VMOVDQU32Z128rrk */ +/* Table6803 */ + 0x3188, /* VPSHUFHWZ128mik */ + 0x318b, /* VPSHUFHWZ128rik */ +/* Table6805 */ + 0x1184, /* VCVTUDQ2PDZ128rmk */ + 0x1187, /* VCVTUDQ2PDZ128rrk */ +/* Table6807 */ + 0x1e28, /* VMOVDQU32Z128mrk */ + 0x1e2f, /* VMOVDQU32Z128rrk_REV */ +/* Table6809 */ + 0xdc4, /* VCMPSSZrm_Intk */ + 0xdc9, /* VCMPSSZrr_Intk */ +/* Table6811 */ + 0xe0c, /* VCVTDQ2PDZ128rmk */ + 0xe0f, /* VCVTDQ2PDZ128rrk */ +/* Table6813 */ + 0x1e6c, /* VMOVDQU8Z128rmk */ + 0x1e70, /* VMOVDQU8Z128rrk */ +/* Table6815 */ + 0x319e, /* VPSHUFLWZ128mik */ + 0x31a1, /* VPSHUFLWZ128rik */ +/* Table6817 */ + 0x119f, /* VCVTUDQ2PSZ128rmk */ + 0x11a2, /* VCVTUDQ2PSZ128rrk */ +/* Table6819 */ + 0x1e6a, /* VMOVDQU8Z128mrk */ + 0x1e71, /* VMOVDQU8Z128rrk_REV */ +/* Table6821 */ + 0xf04, /* VCVTPS2DQZ128rmk */ + 0xf07, /* VCVTPS2DQZ128rrk */ +/* Table6823 */ + 0x3644, /* VPUNPCKLBWZ128rmk */ + 0x3647, /* VPUNPCKLBWZ128rrk */ +/* Table6825 */ + 0x3698, /* VPUNPCKLWDZ128rmk */ + 0x369b, /* VPUNPCKLWDZ128rrk */ +/* Table6827 */ + 0x365d, /* VPUNPCKLDQZ128rmk */ + 0x3660, /* VPUNPCKLDQZ128rrk */ +/* Table6829 */ + 0x20b5, /* VPACKSSWBZ128rmk */ + 0x20b8, /* VPACKSSWBZ128rrk */ +/* Table6831 */ + 0x23fe, /* VPCMPGTBZ128rmk */ + 0x2400, /* VPCMPGTBZ128rrk */ +/* Table6833 */ + 0x243a, /* VPCMPGTWZ128rmk */ + 0x243c, /* VPCMPGTWZ128rrk */ +/* Table6835 */ + 0x2410, /* VPCMPGTDZ128rmk */ + 0x2412, /* VPCMPGTDZ128rrk */ +/* Table6837 */ + 0x20ea, /* VPACKUSWBZ128rmk */ + 0x20ed, /* VPACKUSWBZ128rrk */ +/* Table6839 */ + 0x35da, /* VPUNPCKHBWZ128rmk */ + 0x35dd, /* VPUNPCKHBWZ128rrk */ +/* Table6841 */ + 0x362e, /* VPUNPCKHWDZ128rmk */ + 0x3631, /* VPUNPCKHWDZ128rrk */ +/* Table6843 */ + 0x35f3, /* VPUNPCKHDQZ128rmk */ + 0x35f6, /* VPUNPCKHDQZ128rrk */ +/* Table6845 */ + 0x2099, /* VPACKSSDWZ128rmk */ + 0x209c, /* VPACKSSDWZ128rrk */ +/* Table6847 */ + 0x1dbf, /* VMOVDQA32Z128rmk */ + 0x1dc3, /* VMOVDQA32Z128rrk */ +/* Table6849 */ + 0x316c, /* VPSHUFDZ128mik */ + 0x316f, /* VPSHUFDZ128rik */ +/* Table6851 */ + 0x0, /* */ + 0x0, /* */ + 0x343d, /* VPSRLWZ128mik */ + 0x0, /* */ + 0x3355, /* VPSRAWZ128mik */ + 0x0, /* */ + 0x327f, /* VPSLLWZ128mik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3440, /* VPSRLWZ128rik */ + 0x0, /* */ + 0x3358, /* VPSRAWZ128rik */ + 0x0, /* */ + 0x3282, /* VPSLLWZ128rik */ + 0x0, /* */ +/* Table6867 */ + 0x2f6e, /* VPRORDZ128mik */ + 0x2f02, /* VPROLDZ128mik */ + 0x338a, /* VPSRLDZ128mik */ + 0x0, /* */ + 0x32ac, /* VPSRADZ128mik */ + 0x0, /* */ + 0x31cc, /* VPSLLDZ128mik */ + 0x0, /* */ + 0x2f71, /* VPRORDZ128rik */ + 0x2f05, /* VPROLDZ128rik */ + 0x338d, /* VPSRLDZ128rik */ + 0x0, /* */ + 0x32af, /* VPSRADZ128rik */ + 0x0, /* */ + 0x31cf, /* VPSLLDZ128rik */ + 0x0, /* */ +/* Table6883 */ + 0x23ae, /* VPCMPEQBZ128rmk */ + 0x23b0, /* VPCMPEQBZ128rrk */ +/* Table6885 */ + 0x23ea, /* VPCMPEQWZ128rmk */ + 0x23ec, /* VPCMPEQWZ128rrk */ +/* Table6887 */ + 0x23c0, /* VPCMPEQDZ128rmk */ + 0x23c2, /* VPCMPEQDZ128rrk */ +/* Table6889 */ + 0x112e, /* VCVTTPS2UQQZ128rmk */ + 0x1131, /* VCVTTPS2UQQZ128rrk */ +/* Table6891 */ + 0xf98, /* VCVTPS2UQQZ128rmk */ + 0xf9b, /* VCVTPS2UQQZ128rrk */ +/* Table6893 */ + 0x10f2, /* VCVTTPS2QQZ128rmk */ + 0x10f5, /* VCVTTPS2QQZ128rrk */ +/* Table6895 */ + 0xf5c, /* VCVTPS2QQZ128rmk */ + 0xf5f, /* VCVTPS2QQZ128rrk */ +/* Table6897 */ + 0x1dbd, /* VMOVDQA32Z128mrk */ + 0x1dc4, /* VMOVDQA32Z128rrk_REV */ +/* Table6899 */ + 0x3443, /* VPSRLWZ128rmk */ + 0x3446, /* VPSRLWZ128rrk */ +/* Table6901 */ + 0x3390, /* VPSRLDZ128rmk */ + 0x3393, /* VPSRLDZ128rrk */ +/* Table6903 */ + 0x2e19, /* VPMULLWZ128rmk */ + 0x2e1c, /* VPMULLWZ128rrk */ +/* Table6905 */ + 0x34e6, /* VPSUBUSBZ128rmk */ + 0x34e9, /* VPSUBUSBZ128rrk */ +/* Table6907 */ + 0x34fc, /* VPSUBUSWZ128rmk */ + 0x34ff, /* VPSUBUSWZ128rrk */ +/* Table6909 */ + 0x2ae8, /* VPMINUBZ128rmk */ + 0x2aeb, /* VPMINUBZ128rrk */ +/* Table6911 */ + 0x21d9, /* VPANDDZ128rmk */ + 0x21dc, /* VPANDDZ128rrk */ +/* Table6913 */ + 0x2180, /* VPADDUSBZ128rmk */ + 0x2183, /* VPADDUSBZ128rrk */ +/* Table6915 */ + 0x2196, /* VPADDUSWZ128rmk */ + 0x2199, /* VPADDUSWZ128rrk */ +/* Table6917 */ + 0x2a1c, /* VPMAXUBZ128rmk */ + 0x2a1f, /* VPMAXUBZ128rrk */ +/* Table6919 */ + 0x21f4, /* VPANDNDZ128rmk */ + 0x21f7, /* VPANDNDZ128rrk */ +/* Table6921 */ + 0x224c, /* VPAVGBZ128rmk */ + 0x224f, /* VPAVGBZ128rrk */ +/* Table6923 */ + 0x335b, /* VPSRAWZ128rmk */ + 0x335e, /* VPSRAWZ128rrk */ +/* Table6925 */ + 0x32b2, /* VPSRADZ128rmk */ + 0x32b5, /* VPSRADZ128rrk */ +/* Table6927 */ + 0x2262, /* VPAVGWZ128rmk */ + 0x2265, /* VPAVGWZ128rrk */ +/* Table6929 */ + 0x2db3, /* VPMULHUWZ128rmk */ + 0x2db6, /* VPMULHUWZ128rrk */ +/* Table6931 */ + 0x2dc9, /* VPMULHWZ128rmk */ + 0x2dcc, /* VPMULHWZ128rrk */ +/* Table6933 */ + 0x34ba, /* VPSUBSBZ128rmk */ + 0x34bd, /* VPSUBSBZ128rrk */ +/* Table6935 */ + 0x34d0, /* VPSUBSWZ128rmk */ + 0x34d3, /* VPSUBSWZ128rrk */ +/* Table6937 */ + 0x2ad2, /* VPMINSWZ128rmk */ + 0x2ad5, /* VPMINSWZ128rrk */ +/* Table6939 */ + 0x2ec4, /* VPORDZ128rmk */ + 0x2ec7, /* VPORDZ128rrk */ +/* Table6941 */ + 0x2154, /* VPADDSBZ128rmk */ + 0x2157, /* VPADDSBZ128rrk */ +/* Table6943 */ + 0x216a, /* VPADDSWZ128rmk */ + 0x216d, /* VPADDSWZ128rrk */ +/* Table6945 */ + 0x2a06, /* VPMAXSWZ128rmk */ + 0x2a09, /* VPMAXSWZ128rrk */ +/* Table6947 */ + 0x36af, /* VPXORDZ128rmk */ + 0x36b2, /* VPXORDZ128rrk */ +/* Table6949 */ + 0x3285, /* VPSLLWZ128rmk */ + 0x3288, /* VPSLLWZ128rrk */ +/* Table6951 */ + 0x31d2, /* VPSLLDZ128rmk */ + 0x31d5, /* VPSLLDZ128rrk */ +/* Table6953 */ + 0x2998, /* VPMADDWDZ128rmk */ + 0x299b, /* VPMADDWDZ128rrk */ +/* Table6955 */ + 0x3466, /* VPSUBBZ128rmk */ + 0x3469, /* VPSUBBZ128rrk */ +/* Table6957 */ + 0x3512, /* VPSUBWZ128rmk */ + 0x3515, /* VPSUBWZ128rrk */ +/* Table6959 */ + 0x347f, /* VPSUBDZ128rmk */ + 0x3482, /* VPSUBDZ128rrk */ +/* Table6961 */ + 0x2100, /* VPADDBZ128rmk */ + 0x2103, /* VPADDBZ128rrk */ +/* Table6963 */ + 0x21ac, /* VPADDWZ128rmk */ + 0x21af, /* VPADDWZ128rrk */ +/* Table6965 */ + 0x2119, /* VPADDDZ128rmk */ + 0x211c, /* VPADDDZ128rrk */ +/* Table6967 */ + 0xfd4, /* VCVTQQ2PSZ128rmk */ + 0xfd7, /* VCVTQQ2PSZ128rrk */ +/* Table6969 */ + 0x1094, /* VCVTTPD2UDQZ128rmk */ + 0x1097, /* VCVTTPD2UDQZ128rrk */ +/* Table6971 */ + 0xead, /* VCVTPD2UDQZ128rmk */ + 0xeb0, /* VCVTPD2UDQZ128rrk */ +/* Table6973 */ + 0x1e4b, /* VMOVDQU64Z128rmk */ + 0x1e4f, /* VMOVDQU64Z128rrk */ +/* Table6975 */ + 0x11bd, /* VCVTUQQ2PDZ128rmk */ + 0x11c0, /* VCVTUQQ2PDZ128rrk */ +/* Table6977 */ + 0x1e49, /* VMOVDQU64Z128mrk */ + 0x1e50, /* VMOVDQU64Z128rrk_REV */ +/* Table6979 */ + 0xfb6, /* VCVTQQ2PDZ128rmk */ + 0xfb9, /* VCVTQQ2PDZ128rrk */ +/* Table6981 */ + 0x1ecf, /* VMOVSDZrmk */ + 0x1ed3, /* VMOVSDZrrk */ +/* Table6983 */ + 0x1ecd, /* VMOVSDZmrk */ + 0x1ed4, /* VMOVSDZrrk_REV */ +/* Table6985 */ + 0x1da1, /* VMOVDDUPZ128rmk */ + 0x1da4, /* VMOVDDUPZ128rrk */ +/* Table6987 */ + 0x39f9, /* VSQRTSDZm_Intk */ + 0x39fd, /* VSQRTSDZr_Intk */ +/* Table6989 */ + 0xb9e, /* VADDSDZrm_Intk */ + 0xba2, /* VADDSDZrr_Intk */ +/* Table6991 */ + 0x1fc7, /* VMULSDZrm_Intk */ + 0x1fcb, /* VMULSDZrr_Intk */ +/* Table6993 */ + 0xffa, /* VCVTSD2SSZrm_Intk */ + 0xffe, /* VCVTSD2SSZrr_Intk */ +/* Table6995 */ + 0x3a5c, /* VSUBSDZrm_Intk */ + 0x3a60, /* VSUBSDZrr_Intk */ +/* Table6997 */ + 0x1d24, /* VMINSDZrm_Intk */ + 0x1d28, /* VMINSDZrr_Intk */ +/* Table6999 */ + 0x1260, /* VDIVSDZrm_Intk */ + 0x1264, /* VDIVSDZrr_Intk */ +/* Table7001 */ + 0x1c79, /* VMAXSDZrm_Intk */ + 0x1c7d, /* VMAXSDZrr_Intk */ +/* Table7003 */ + 0x1e09, /* VMOVDQU16Z128rmk */ + 0x1e0d, /* VMOVDQU16Z128rrk */ +/* Table7005 */ + 0x11db, /* VCVTUQQ2PSZ128rmk */ + 0x11de, /* VCVTUQQ2PSZ128rrk */ +/* Table7007 */ + 0x1e07, /* VMOVDQU16Z128mrk */ + 0x1e0e, /* VMOVDQU16Z128rrk_REV */ +/* Table7009 */ + 0xdb0, /* VCMPSDZrm_Intk */ + 0xdb5, /* VCMPSDZrr_Intk */ +/* Table7011 */ + 0xe4d, /* VCVTPD2DQZ128rmk */ + 0xe50, /* VCVTPD2DQZ128rrk */ +/* Table7013 */ + 0x1f25, /* VMOVUPDZ128rmk */ + 0x1f29, /* VMOVUPDZ128rrk */ +/* Table7015 */ + 0x1f23, /* VMOVUPDZ128mrk */ + 0x1f2a, /* VMOVUPDZ128rrk_REV */ +/* Table7017 */ + 0x3ad6, /* VUNPCKLPDZ128rmk */ + 0x3ad9, /* VUNPCKLPDZ128rrk */ +/* Table7019 */ + 0x3a98, /* VUNPCKHPDZ128rmk */ + 0x3a9b, /* VUNPCKHPDZ128rrk */ +/* Table7021 */ + 0x1d53, /* VMOVAPDZ128rmk */ + 0x1d57, /* VMOVAPDZ128rrk */ +/* Table7023 */ + 0x1d51, /* VMOVAPDZ128mrk */ + 0x1d58, /* VMOVAPDZ128rrk_REV */ +/* Table7025 */ + 0x39b9, /* VSQRTPDZ128mk */ + 0x39bc, /* VSQRTPDZ128rk */ +/* Table7027 */ + 0xc68, /* VANDPDZ128rmk */ + 0xc6b, /* VANDPDZ128rrk */ +/* Table7029 */ + 0xc2a, /* VANDNPDZ128rmk */ + 0xc2d, /* VANDNPDZ128rrk */ +/* Table7031 */ + 0x1fef, /* VORPDZ128rmk */ + 0x1ff2, /* VORPDZ128rrk */ +/* Table7033 */ + 0x3b14, /* VXORPDZ128rmk */ + 0x3b17, /* VXORPDZ128rrk */ +/* Table7035 */ + 0xb5e, /* VADDPDZ128rmk */ + 0xb61, /* VADDPDZ128rrk */ +/* Table7037 */ + 0x1f87, /* VMULPDZ128rmk */ + 0x1f8a, /* VMULPDZ128rrk */ +/* Table7039 */ + 0xe6f, /* VCVTPD2PSZ128rmk */ + 0xe72, /* VCVTPD2PSZ128rrk */ +/* Table7041 */ + 0x3a1c, /* VSUBPDZ128rmk */ + 0x3a1f, /* VSUBPDZ128rrk */ +/* Table7043 */ + 0x1ce4, /* VMINPDZ128rmk */ + 0x1ce7, /* VMINPDZ128rrk */ +/* Table7045 */ + 0x1220, /* VDIVPDZ128rmk */ + 0x1223, /* VDIVPDZ128rrk */ +/* Table7047 */ + 0x1c39, /* VMAXPDZ128rmk */ + 0x1c3c, /* VMAXPDZ128rrk */ +/* Table7049 */ + 0x367c, /* VPUNPCKLQDQZ128rmk */ + 0x367f, /* VPUNPCKLQDQZ128rrk */ +/* Table7051 */ + 0x3612, /* VPUNPCKHQDQZ128rmk */ + 0x3615, /* VPUNPCKHQDQZ128rrk */ +/* Table7053 */ + 0x1de0, /* VMOVDQA64Z128rmk */ + 0x1de4, /* VMOVDQA64Z128rrk */ +/* Table7055 */ + 0x2f89, /* VPRORQZ128mik */ + 0x2f1d, /* VPROLQZ128mik */ + 0x0, /* */ + 0x0, /* */ + 0x32dc, /* VPSRAQZ128mik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x2f8c, /* VPRORQZ128rik */ + 0x2f20, /* VPROLQZ128rik */ + 0x0, /* */ + 0x0, /* */ + 0x32df, /* VPSRAQZ128rik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table7071 */ + 0x0, /* */ + 0x0, /* */ + 0x33bd, /* VPSRLQZ128mik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x31ff, /* VPSLLQZ128mik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x33c0, /* VPSRLQZ128rik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3202, /* VPSLLQZ128rik */ + 0x0, /* */ +/* Table7087 */ + 0x10b2, /* VCVTTPD2UQQZ128rmk */ + 0x10b5, /* VCVTTPD2UQQZ128rrk */ +/* Table7089 */ + 0xecb, /* VCVTPD2UQQZ128rmk */ + 0xece, /* VCVTPD2UQQZ128rrk */ +/* Table7091 */ + 0x1076, /* VCVTTPD2QQZ128rmk */ + 0x1079, /* VCVTTPD2QQZ128rrk */ +/* Table7093 */ + 0xe8f, /* VCVTPD2QQZ128rmk */ + 0xe92, /* VCVTPD2QQZ128rrk */ +/* Table7095 */ + 0x1dde, /* VMOVDQA64Z128mrk */ + 0x1de5, /* VMOVDQA64Z128rrk_REV */ +/* Table7097 */ + 0xd59, /* VCMPPDZ128rmik */ + 0xd5d, /* VCMPPDZ128rrik */ +/* Table7099 */ + 0x397b, /* VSHUFPDZ128rmik */ + 0x397e, /* VSHUFPDZ128rrik */ +/* Table7101 */ + 0x33c3, /* VPSRLQZ128rmk */ + 0x33c6, /* VPSRLQZ128rrk */ +/* Table7103 */ + 0x2138, /* VPADDQZ128rmk */ + 0x213b, /* VPADDQZ128rrk */ +/* Table7105 */ + 0x222e, /* VPANDQZ128rmk */ + 0x2231, /* VPANDQZ128rrk */ +/* Table7107 */ + 0x220f, /* VPANDNQZ128rmk */ + 0x2212, /* VPANDNQZ128rrk */ +/* Table7109 */ + 0x32e2, /* VPSRAQZ128rmk */ + 0x32e5, /* VPSRAQZ128rrk */ +/* Table7111 */ + 0x1056, /* VCVTTPD2DQZ128rmk */ + 0x1059, /* VCVTTPD2DQZ128rrk */ +/* Table7113 */ + 0x2edf, /* VPORQZ128rmk */ + 0x2ee2, /* VPORQZ128rrk */ +/* Table7115 */ + 0x36ca, /* VPXORQZ128rmk */ + 0x36cd, /* VPXORQZ128rrk */ +/* Table7117 */ + 0x3205, /* VPSLLQZ128rmk */ + 0x3208, /* VPSLLQZ128rrk */ +/* Table7119 */ + 0x2e4d, /* VPMULUDQZ128rmk */ + 0x2e50, /* VPMULUDQZ128rrk */ +/* Table7121 */ + 0x349e, /* VPSUBQZ128rmk */ + 0x34a1, /* VPSUBQZ128rrk */ +/* Table7123 */ + 0x1f59, /* VMOVUPSZ256rmk */ + 0x1f5d, /* VMOVUPSZ256rrk */ +/* Table7125 */ + 0x1f57, /* VMOVUPSZ256mrk */ + 0x1f5e, /* VMOVUPSZ256rrk_REV */ +/* Table7127 */ + 0x3afe, /* VUNPCKLPSZ256rmk */ + 0x3b01, /* VUNPCKLPSZ256rrk */ +/* Table7129 */ + 0x3ac0, /* VUNPCKHPSZ256rmk */ + 0x3ac3, /* VUNPCKHPSZ256rrk */ +/* Table7131 */ + 0x1d87, /* VMOVAPSZ256rmk */ + 0x1d8b, /* VMOVAPSZ256rrk */ +/* Table7133 */ + 0x1d85, /* VMOVAPSZ256mrk */ + 0x1d8c, /* VMOVAPSZ256rrk_REV */ +/* Table7135 */ + 0x39e4, /* VSQRTPSZ256mk */ + 0x39e7, /* VSQRTPSZ256rk */ +/* Table7137 */ + 0xc90, /* VANDPSZ256rmk */ + 0xc93, /* VANDPSZ256rrk */ +/* Table7139 */ + 0xc52, /* VANDNPSZ256rmk */ + 0xc55, /* VANDNPSZ256rrk */ +/* Table7141 */ + 0x2017, /* VORPSZ256rmk */ + 0x201a, /* VORPSZ256rrk */ +/* Table7143 */ + 0x3b3c, /* VXORPSZ256rmk */ + 0x3b3f, /* VXORPSZ256rrk */ +/* Table7145 */ + 0xb89, /* VADDPSZ256rmk */ + 0xb8c, /* VADDPSZ256rrk */ +/* Table7147 */ + 0x1fb2, /* VMULPSZ256rmk */ + 0x1fb5, /* VMULPSZ256rrk */ +/* Table7149 */ + 0xf2f, /* VCVTPS2PDZ256rmk */ + 0xf32, /* VCVTPS2PDZ256rrk */ +/* Table7151 */ + 0xe34, /* VCVTDQ2PSZ256rmk */ + 0xe37, /* VCVTDQ2PSZ256rrk */ +/* Table7153 */ + 0x3a47, /* VSUBPSZ256rmk */ + 0x3a4a, /* VSUBPSZ256rrk */ +/* Table7155 */ + 0x1d0f, /* VMINPSZ256rmk */ + 0x1d12, /* VMINPSZ256rrk */ +/* Table7157 */ + 0x124b, /* VDIVPSZ256rmk */ + 0x124e, /* VDIVPSZ256rrk */ +/* Table7159 */ + 0x1c64, /* VMAXPSZ256rmk */ + 0x1c67, /* VMAXPSZ256rrk */ +/* Table7161 */ + 0x1119, /* VCVTTPS2UDQZ256rmk */ + 0x111c, /* VCVTTPS2UDQZ256rrk */ +/* Table7163 */ + 0xf83, /* VCVTPS2UDQZ256rmk */ + 0xf86, /* VCVTPS2UDQZ256rrk */ +/* Table7165 */ + 0xd95, /* VCMPPSZ256rmik */ + 0xd99, /* VCMPPSZ256rrik */ +/* Table7167 */ + 0x39a3, /* VSHUFPSZ256rmik */ + 0x39a6, /* VSHUFPSZ256rrik */ +/* Table7169 */ + 0x1efe, /* VMOVSLDUPZ256rmk */ + 0x1f01, /* VMOVSLDUPZ256rrk */ +/* Table7171 */ + 0x1ee8, /* VMOVSHDUPZ256rmk */ + 0x1eeb, /* VMOVSHDUPZ256rrk */ +/* Table7173 */ + 0x10db, /* VCVTTPS2DQZ256rmk */ + 0x10de, /* VCVTTPS2DQZ256rrk */ +/* Table7175 */ + 0x1e35, /* VMOVDQU32Z256rmk */ + 0x1e39, /* VMOVDQU32Z256rrk */ +/* Table7177 */ + 0x318e, /* VPSHUFHWZ256mik */ + 0x3191, /* VPSHUFHWZ256rik */ +/* Table7179 */ + 0x118d, /* VCVTUDQ2PDZ256rmk */ + 0x1190, /* VCVTUDQ2PDZ256rrk */ +/* Table7181 */ + 0x1e33, /* VMOVDQU32Z256mrk */ + 0x1e3a, /* VMOVDQU32Z256rrk_REV */ +/* Table7183 */ + 0xe15, /* VCVTDQ2PDZ256rmk */ + 0xe18, /* VCVTDQ2PDZ256rrk */ +/* Table7185 */ + 0x1e77, /* VMOVDQU8Z256rmk */ + 0x1e7b, /* VMOVDQU8Z256rrk */ +/* Table7187 */ + 0x31a4, /* VPSHUFLWZ256mik */ + 0x31a7, /* VPSHUFLWZ256rik */ +/* Table7189 */ + 0x11a8, /* VCVTUDQ2PSZ256rmk */ + 0x11ab, /* VCVTUDQ2PSZ256rrk */ +/* Table7191 */ + 0x1e75, /* VMOVDQU8Z256mrk */ + 0x1e7c, /* VMOVDQU8Z256rrk_REV */ +/* Table7193 */ + 0xf0d, /* VCVTPS2DQZ256rmk */ + 0xf10, /* VCVTPS2DQZ256rrk */ +/* Table7195 */ + 0x364a, /* VPUNPCKLBWZ256rmk */ + 0x364d, /* VPUNPCKLBWZ256rrk */ +/* Table7197 */ + 0x369e, /* VPUNPCKLWDZ256rmk */ + 0x36a1, /* VPUNPCKLWDZ256rrk */ +/* Table7199 */ + 0x3666, /* VPUNPCKLDQZ256rmk */ + 0x3669, /* VPUNPCKLDQZ256rrk */ +/* Table7201 */ + 0x20bb, /* VPACKSSWBZ256rmk */ + 0x20be, /* VPACKSSWBZ256rrk */ +/* Table7203 */ + 0x2402, /* VPCMPGTBZ256rmk */ + 0x2404, /* VPCMPGTBZ256rrk */ +/* Table7205 */ + 0x243e, /* VPCMPGTWZ256rmk */ + 0x2440, /* VPCMPGTWZ256rrk */ +/* Table7207 */ + 0x2416, /* VPCMPGTDZ256rmk */ + 0x2418, /* VPCMPGTDZ256rrk */ +/* Table7209 */ + 0x20f0, /* VPACKUSWBZ256rmk */ + 0x20f3, /* VPACKUSWBZ256rrk */ +/* Table7211 */ + 0x35e0, /* VPUNPCKHBWZ256rmk */ + 0x35e3, /* VPUNPCKHBWZ256rrk */ +/* Table7213 */ + 0x3634, /* VPUNPCKHWDZ256rmk */ + 0x3637, /* VPUNPCKHWDZ256rrk */ +/* Table7215 */ + 0x35fc, /* VPUNPCKHDQZ256rmk */ + 0x35ff, /* VPUNPCKHDQZ256rrk */ +/* Table7217 */ + 0x20a2, /* VPACKSSDWZ256rmk */ + 0x20a5, /* VPACKSSDWZ256rrk */ +/* Table7219 */ + 0x1dca, /* VMOVDQA32Z256rmk */ + 0x1dce, /* VMOVDQA32Z256rrk */ +/* Table7221 */ + 0x3175, /* VPSHUFDZ256mik */ + 0x3178, /* VPSHUFDZ256rik */ +/* Table7223 */ + 0x0, /* */ + 0x0, /* */ + 0x3449, /* VPSRLWZ256mik */ + 0x0, /* */ + 0x3361, /* VPSRAWZ256mik */ + 0x0, /* */ + 0x328b, /* VPSLLWZ256mik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x344c, /* VPSRLWZ256rik */ + 0x0, /* */ + 0x3364, /* VPSRAWZ256rik */ + 0x0, /* */ + 0x328e, /* VPSLLWZ256rik */ + 0x0, /* */ +/* Table7239 */ + 0x2f77, /* VPRORDZ256mik */ + 0x2f0b, /* VPROLDZ256mik */ + 0x3399, /* VPSRLDZ256mik */ + 0x0, /* */ + 0x32bb, /* VPSRADZ256mik */ + 0x0, /* */ + 0x31db, /* VPSLLDZ256mik */ + 0x0, /* */ + 0x2f7a, /* VPRORDZ256rik */ + 0x2f0e, /* VPROLDZ256rik */ + 0x339c, /* VPSRLDZ256rik */ + 0x0, /* */ + 0x32be, /* VPSRADZ256rik */ + 0x0, /* */ + 0x31de, /* VPSLLDZ256rik */ + 0x0, /* */ +/* Table7255 */ + 0x23b2, /* VPCMPEQBZ256rmk */ + 0x23b4, /* VPCMPEQBZ256rrk */ +/* Table7257 */ + 0x23ee, /* VPCMPEQWZ256rmk */ + 0x23f0, /* VPCMPEQWZ256rrk */ +/* Table7259 */ + 0x23c6, /* VPCMPEQDZ256rmk */ + 0x23c8, /* VPCMPEQDZ256rrk */ +/* Table7261 */ + 0x1137, /* VCVTTPS2UQQZ256rmk */ + 0x113a, /* VCVTTPS2UQQZ256rrk */ +/* Table7263 */ + 0xfa1, /* VCVTPS2UQQZ256rmk */ + 0xfa4, /* VCVTPS2UQQZ256rrk */ +/* Table7265 */ + 0x10fb, /* VCVTTPS2QQZ256rmk */ + 0x10fe, /* VCVTTPS2QQZ256rrk */ +/* Table7267 */ + 0xf65, /* VCVTPS2QQZ256rmk */ + 0xf68, /* VCVTPS2QQZ256rrk */ +/* Table7269 */ + 0x1dc8, /* VMOVDQA32Z256mrk */ + 0x1dcf, /* VMOVDQA32Z256rrk_REV */ +/* Table7271 */ + 0x344f, /* VPSRLWZ256rmk */ + 0x3452, /* VPSRLWZ256rrk */ +/* Table7273 */ + 0x339f, /* VPSRLDZ256rmk */ + 0x33a2, /* VPSRLDZ256rrk */ +/* Table7275 */ + 0x2e1f, /* VPMULLWZ256rmk */ + 0x2e22, /* VPMULLWZ256rrk */ +/* Table7277 */ + 0x34ec, /* VPSUBUSBZ256rmk */ + 0x34ef, /* VPSUBUSBZ256rrk */ +/* Table7279 */ + 0x3502, /* VPSUBUSWZ256rmk */ + 0x3505, /* VPSUBUSWZ256rrk */ +/* Table7281 */ + 0x2aee, /* VPMINUBZ256rmk */ + 0x2af1, /* VPMINUBZ256rrk */ +/* Table7283 */ + 0x21e2, /* VPANDDZ256rmk */ + 0x21e5, /* VPANDDZ256rrk */ +/* Table7285 */ + 0x2186, /* VPADDUSBZ256rmk */ + 0x2189, /* VPADDUSBZ256rrk */ +/* Table7287 */ + 0x219c, /* VPADDUSWZ256rmk */ + 0x219f, /* VPADDUSWZ256rrk */ +/* Table7289 */ + 0x2a22, /* VPMAXUBZ256rmk */ + 0x2a25, /* VPMAXUBZ256rrk */ +/* Table7291 */ + 0x21fd, /* VPANDNDZ256rmk */ + 0x2200, /* VPANDNDZ256rrk */ +/* Table7293 */ + 0x2252, /* VPAVGBZ256rmk */ + 0x2255, /* VPAVGBZ256rrk */ +/* Table7295 */ + 0x3367, /* VPSRAWZ256rmk */ + 0x336a, /* VPSRAWZ256rrk */ +/* Table7297 */ + 0x32c1, /* VPSRADZ256rmk */ + 0x32c4, /* VPSRADZ256rrk */ +/* Table7299 */ + 0x2268, /* VPAVGWZ256rmk */ + 0x226b, /* VPAVGWZ256rrk */ +/* Table7301 */ + 0x2db9, /* VPMULHUWZ256rmk */ + 0x2dbc, /* VPMULHUWZ256rrk */ +/* Table7303 */ + 0x2dcf, /* VPMULHWZ256rmk */ + 0x2dd2, /* VPMULHWZ256rrk */ +/* Table7305 */ + 0x34c0, /* VPSUBSBZ256rmk */ + 0x34c3, /* VPSUBSBZ256rrk */ +/* Table7307 */ + 0x34d6, /* VPSUBSWZ256rmk */ + 0x34d9, /* VPSUBSWZ256rrk */ +/* Table7309 */ + 0x2ad8, /* VPMINSWZ256rmk */ + 0x2adb, /* VPMINSWZ256rrk */ +/* Table7311 */ + 0x2ecd, /* VPORDZ256rmk */ + 0x2ed0, /* VPORDZ256rrk */ +/* Table7313 */ + 0x215a, /* VPADDSBZ256rmk */ + 0x215d, /* VPADDSBZ256rrk */ +/* Table7315 */ + 0x2170, /* VPADDSWZ256rmk */ + 0x2173, /* VPADDSWZ256rrk */ +/* Table7317 */ + 0x2a0c, /* VPMAXSWZ256rmk */ + 0x2a0f, /* VPMAXSWZ256rrk */ +/* Table7319 */ + 0x36b8, /* VPXORDZ256rmk */ + 0x36bb, /* VPXORDZ256rrk */ +/* Table7321 */ + 0x3291, /* VPSLLWZ256rmk */ + 0x3294, /* VPSLLWZ256rrk */ +/* Table7323 */ + 0x31e1, /* VPSLLDZ256rmk */ + 0x31e4, /* VPSLLDZ256rrk */ +/* Table7325 */ + 0x299e, /* VPMADDWDZ256rmk */ + 0x29a1, /* VPMADDWDZ256rrk */ +/* Table7327 */ + 0x346c, /* VPSUBBZ256rmk */ + 0x346f, /* VPSUBBZ256rrk */ +/* Table7329 */ + 0x3518, /* VPSUBWZ256rmk */ + 0x351b, /* VPSUBWZ256rrk */ +/* Table7331 */ + 0x3488, /* VPSUBDZ256rmk */ + 0x348b, /* VPSUBDZ256rrk */ +/* Table7333 */ + 0x2106, /* VPADDBZ256rmk */ + 0x2109, /* VPADDBZ256rrk */ +/* Table7335 */ + 0x21b2, /* VPADDWZ256rmk */ + 0x21b5, /* VPADDWZ256rrk */ +/* Table7337 */ + 0x2122, /* VPADDDZ256rmk */ + 0x2125, /* VPADDDZ256rrk */ +/* Table7339 */ + 0xfdd, /* VCVTQQ2PSZ256rmk */ + 0xfe0, /* VCVTQQ2PSZ256rrk */ +/* Table7341 */ + 0x109d, /* VCVTTPD2UDQZ256rmk */ + 0x10a0, /* VCVTTPD2UDQZ256rrk */ +/* Table7343 */ + 0xeb6, /* VCVTPD2UDQZ256rmk */ + 0xeb9, /* VCVTPD2UDQZ256rrk */ +/* Table7345 */ + 0x1e56, /* VMOVDQU64Z256rmk */ + 0x1e5a, /* VMOVDQU64Z256rrk */ +/* Table7347 */ + 0x11c6, /* VCVTUQQ2PDZ256rmk */ + 0x11c9, /* VCVTUQQ2PDZ256rrk */ +/* Table7349 */ + 0x1e54, /* VMOVDQU64Z256mrk */ + 0x1e5b, /* VMOVDQU64Z256rrk_REV */ +/* Table7351 */ + 0xfbf, /* VCVTQQ2PDZ256rmk */ + 0xfc2, /* VCVTQQ2PDZ256rrk */ +/* Table7353 */ + 0x1da7, /* VMOVDDUPZ256rmk */ + 0x1daa, /* VMOVDDUPZ256rrk */ +/* Table7355 */ + 0x1e14, /* VMOVDQU16Z256rmk */ + 0x1e18, /* VMOVDQU16Z256rrk */ +/* Table7357 */ + 0x11e4, /* VCVTUQQ2PSZ256rmk */ + 0x11e7, /* VCVTUQQ2PSZ256rrk */ +/* Table7359 */ + 0x1e12, /* VMOVDQU16Z256mrk */ + 0x1e19, /* VMOVDQU16Z256rrk_REV */ +/* Table7361 */ + 0xe56, /* VCVTPD2DQZ256rmk */ + 0xe59, /* VCVTPD2DQZ256rrk */ +/* Table7363 */ + 0x1f30, /* VMOVUPDZ256rmk */ + 0x1f34, /* VMOVUPDZ256rrk */ +/* Table7365 */ + 0x1f2e, /* VMOVUPDZ256mrk */ + 0x1f35, /* VMOVUPDZ256rrk_REV */ +/* Table7367 */ + 0x3adf, /* VUNPCKLPDZ256rmk */ + 0x3ae2, /* VUNPCKLPDZ256rrk */ +/* Table7369 */ + 0x3aa1, /* VUNPCKHPDZ256rmk */ + 0x3aa4, /* VUNPCKHPDZ256rrk */ +/* Table7371 */ + 0x1d5e, /* VMOVAPDZ256rmk */ + 0x1d62, /* VMOVAPDZ256rrk */ +/* Table7373 */ + 0x1d5c, /* VMOVAPDZ256mrk */ + 0x1d63, /* VMOVAPDZ256rrk_REV */ +/* Table7375 */ + 0x39c2, /* VSQRTPDZ256mk */ + 0x39c5, /* VSQRTPDZ256rk */ +/* Table7377 */ + 0xc71, /* VANDPDZ256rmk */ + 0xc74, /* VANDPDZ256rrk */ +/* Table7379 */ + 0xc33, /* VANDNPDZ256rmk */ + 0xc36, /* VANDNPDZ256rrk */ +/* Table7381 */ + 0x1ff8, /* VORPDZ256rmk */ + 0x1ffb, /* VORPDZ256rrk */ +/* Table7383 */ + 0x3b1d, /* VXORPDZ256rmk */ + 0x3b20, /* VXORPDZ256rrk */ +/* Table7385 */ + 0xb67, /* VADDPDZ256rmk */ + 0xb6a, /* VADDPDZ256rrk */ +/* Table7387 */ + 0x1f90, /* VMULPDZ256rmk */ + 0x1f93, /* VMULPDZ256rrk */ +/* Table7389 */ + 0xe78, /* VCVTPD2PSZ256rmk */ + 0xe7b, /* VCVTPD2PSZ256rrk */ +/* Table7391 */ + 0x3a25, /* VSUBPDZ256rmk */ + 0x3a28, /* VSUBPDZ256rrk */ +/* Table7393 */ + 0x1ced, /* VMINPDZ256rmk */ + 0x1cf0, /* VMINPDZ256rrk */ +/* Table7395 */ + 0x1229, /* VDIVPDZ256rmk */ + 0x122c, /* VDIVPDZ256rrk */ +/* Table7397 */ + 0x1c42, /* VMAXPDZ256rmk */ + 0x1c45, /* VMAXPDZ256rrk */ +/* Table7399 */ + 0x3685, /* VPUNPCKLQDQZ256rmk */ + 0x3688, /* VPUNPCKLQDQZ256rrk */ +/* Table7401 */ + 0x361b, /* VPUNPCKHQDQZ256rmk */ + 0x361e, /* VPUNPCKHQDQZ256rrk */ +/* Table7403 */ + 0x1deb, /* VMOVDQA64Z256rmk */ + 0x1def, /* VMOVDQA64Z256rrk */ +/* Table7405 */ + 0x2f92, /* VPRORQZ256mik */ + 0x2f26, /* VPROLQZ256mik */ + 0x0, /* */ + 0x0, /* */ + 0x32eb, /* VPSRAQZ256mik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x2f95, /* VPRORQZ256rik */ + 0x2f29, /* VPROLQZ256rik */ + 0x0, /* */ + 0x0, /* */ + 0x32ee, /* VPSRAQZ256rik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table7421 */ + 0x0, /* */ + 0x0, /* */ + 0x33cc, /* VPSRLQZ256mik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x320e, /* VPSLLQZ256mik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x33cf, /* VPSRLQZ256rik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3211, /* VPSLLQZ256rik */ + 0x0, /* */ +/* Table7437 */ + 0x10bb, /* VCVTTPD2UQQZ256rmk */ + 0x10be, /* VCVTTPD2UQQZ256rrk */ +/* Table7439 */ + 0xed4, /* VCVTPD2UQQZ256rmk */ + 0xed7, /* VCVTPD2UQQZ256rrk */ +/* Table7441 */ + 0x107f, /* VCVTTPD2QQZ256rmk */ + 0x1082, /* VCVTTPD2QQZ256rrk */ +/* Table7443 */ + 0xe98, /* VCVTPD2QQZ256rmk */ + 0xe9b, /* VCVTPD2QQZ256rrk */ +/* Table7445 */ + 0x1de9, /* VMOVDQA64Z256mrk */ + 0x1df0, /* VMOVDQA64Z256rrk_REV */ +/* Table7447 */ + 0xd65, /* VCMPPDZ256rmik */ + 0xd69, /* VCMPPDZ256rrik */ +/* Table7449 */ + 0x3984, /* VSHUFPDZ256rmik */ + 0x3987, /* VSHUFPDZ256rrik */ +/* Table7451 */ + 0x33d2, /* VPSRLQZ256rmk */ + 0x33d5, /* VPSRLQZ256rrk */ +/* Table7453 */ + 0x2141, /* VPADDQZ256rmk */ + 0x2144, /* VPADDQZ256rrk */ +/* Table7455 */ + 0x2237, /* VPANDQZ256rmk */ + 0x223a, /* VPANDQZ256rrk */ +/* Table7457 */ + 0x2218, /* VPANDNQZ256rmk */ + 0x221b, /* VPANDNQZ256rrk */ +/* Table7459 */ + 0x32f1, /* VPSRAQZ256rmk */ + 0x32f4, /* VPSRAQZ256rrk */ +/* Table7461 */ + 0x105f, /* VCVTTPD2DQZ256rmk */ + 0x1062, /* VCVTTPD2DQZ256rrk */ +/* Table7463 */ + 0x2ee8, /* VPORQZ256rmk */ + 0x2eeb, /* VPORQZ256rrk */ +/* Table7465 */ + 0x36d3, /* VPXORQZ256rmk */ + 0x36d6, /* VPXORQZ256rrk */ +/* Table7467 */ + 0x3214, /* VPSLLQZ256rmk */ + 0x3217, /* VPSLLQZ256rrk */ +/* Table7469 */ + 0x2e56, /* VPMULUDQZ256rmk */ + 0x2e59, /* VPMULUDQZ256rrk */ +/* Table7471 */ + 0x34a7, /* VPSUBQZ256rmk */ + 0x34aa, /* VPSUBQZ256rrk */ +/* Table7473 */ + 0x1f64, /* VMOVUPSZrmk */ + 0x1f68, /* VMOVUPSZrrk */ +/* Table7475 */ + 0x1f62, /* VMOVUPSZmrk */ + 0x1f69, /* VMOVUPSZrrk_REV */ +/* Table7477 */ + 0x3b07, /* VUNPCKLPSZrmk */ + 0x3b0a, /* VUNPCKLPSZrrk */ +/* Table7479 */ + 0x3ac9, /* VUNPCKHPSZrmk */ + 0x3acc, /* VUNPCKHPSZrrk */ +/* Table7481 */ + 0x1d92, /* VMOVAPSZrmk */ + 0x1d96, /* VMOVAPSZrrk */ +/* Table7483 */ + 0x1d90, /* VMOVAPSZmrk */ + 0x1d97, /* VMOVAPSZrrk_REV */ +/* Table7485 */ + 0x39ed, /* VSQRTPSZmk */ + 0x39f3, /* VSQRTPSZrk */ +/* Table7487 */ + 0xc99, /* VANDPSZrmk */ + 0xc9c, /* VANDPSZrrk */ +/* Table7489 */ + 0xc5b, /* VANDNPSZrmk */ + 0xc5e, /* VANDNPSZrrk */ +/* Table7491 */ + 0x2020, /* VORPSZrmk */ + 0x2023, /* VORPSZrrk */ +/* Table7493 */ + 0x3b45, /* VXORPSZrmk */ + 0x3b48, /* VXORPSZrrk */ +/* Table7495 */ + 0xb92, /* VADDPSZrmk */ + 0xb98, /* VADDPSZrrk */ +/* Table7497 */ + 0x1fbb, /* VMULPSZrmk */ + 0x1fc1, /* VMULPSZrrk */ +/* Table7499 */ + 0xf38, /* VCVTPS2PDZrmk */ + 0xf3e, /* VCVTPS2PDZrrk */ +/* Table7501 */ + 0xe3d, /* VCVTDQ2PSZrmk */ + 0xe43, /* VCVTDQ2PSZrrk */ +/* Table7503 */ + 0x3a50, /* VSUBPSZrmk */ + 0x3a56, /* VSUBPSZrrk */ +/* Table7505 */ + 0x1d18, /* VMINPSZrmk */ + 0x1d1e, /* VMINPSZrrk */ +/* Table7507 */ + 0x1254, /* VDIVPSZrmk */ + 0x125a, /* VDIVPSZrrk */ +/* Table7509 */ + 0x1c6d, /* VMAXPSZrmk */ + 0x1c73, /* VMAXPSZrrk */ +/* Table7511 */ + 0x1122, /* VCVTTPS2UDQZrmk */ + 0x1128, /* VCVTTPS2UDQZrrk */ +/* Table7513 */ + 0xf8c, /* VCVTPS2UDQZrmk */ + 0xf92, /* VCVTPS2UDQZrrk */ +/* Table7515 */ + 0xda1, /* VCMPPSZrmik */ + 0xda9, /* VCMPPSZrrik */ +/* Table7517 */ + 0x39ac, /* VSHUFPSZrmik */ + 0x39af, /* VSHUFPSZrrik */ +/* Table7519 */ + 0x1f04, /* VMOVSLDUPZrmk */ + 0x1f07, /* VMOVSLDUPZrrk */ +/* Table7521 */ + 0x1eee, /* VMOVSHDUPZrmk */ + 0x1ef1, /* VMOVSHDUPZrrk */ +/* Table7523 */ + 0x10e4, /* VCVTTPS2DQZrmk */ + 0x10ea, /* VCVTTPS2DQZrrk */ +/* Table7525 */ + 0x1e40, /* VMOVDQU32Zrmk */ + 0x1e44, /* VMOVDQU32Zrrk */ +/* Table7527 */ + 0x3194, /* VPSHUFHWZmik */ + 0x3197, /* VPSHUFHWZrik */ +/* Table7529 */ + 0x1196, /* VCVTUDQ2PDZrmk */ + 0x1199, /* VCVTUDQ2PDZrrk */ +/* Table7531 */ + 0x1e3e, /* VMOVDQU32Zmrk */ + 0x1e45, /* VMOVDQU32Zrrk_REV */ +/* Table7533 */ + 0xe1e, /* VCVTDQ2PDZrmk */ + 0xe21, /* VCVTDQ2PDZrrk */ +/* Table7535 */ + 0x1e82, /* VMOVDQU8Zrmk */ + 0x1e86, /* VMOVDQU8Zrrk */ +/* Table7537 */ + 0x31aa, /* VPSHUFLWZmik */ + 0x31ad, /* VPSHUFLWZrik */ +/* Table7539 */ + 0x11b1, /* VCVTUDQ2PSZrmk */ + 0x11b7, /* VCVTUDQ2PSZrrk */ +/* Table7541 */ + 0x1e80, /* VMOVDQU8Zmrk */ + 0x1e87, /* VMOVDQU8Zrrk_REV */ +/* Table7543 */ + 0xf16, /* VCVTPS2DQZrmk */ + 0xf1c, /* VCVTPS2DQZrrk */ +/* Table7545 */ + 0x3650, /* VPUNPCKLBWZrmk */ + 0x3653, /* VPUNPCKLBWZrrk */ +/* Table7547 */ + 0x36a4, /* VPUNPCKLWDZrmk */ + 0x36a7, /* VPUNPCKLWDZrrk */ +/* Table7549 */ + 0x366f, /* VPUNPCKLDQZrmk */ + 0x3672, /* VPUNPCKLDQZrrk */ +/* Table7551 */ + 0x20c1, /* VPACKSSWBZrmk */ + 0x20c4, /* VPACKSSWBZrrk */ +/* Table7553 */ + 0x2406, /* VPCMPGTBZrmk */ + 0x2408, /* VPCMPGTBZrrk */ +/* Table7555 */ + 0x2442, /* VPCMPGTWZrmk */ + 0x2444, /* VPCMPGTWZrrk */ +/* Table7557 */ + 0x241c, /* VPCMPGTDZrmk */ + 0x241e, /* VPCMPGTDZrrk */ +/* Table7559 */ + 0x20f6, /* VPACKUSWBZrmk */ + 0x20f9, /* VPACKUSWBZrrk */ +/* Table7561 */ + 0x35e6, /* VPUNPCKHBWZrmk */ + 0x35e9, /* VPUNPCKHBWZrrk */ +/* Table7563 */ + 0x363a, /* VPUNPCKHWDZrmk */ + 0x363d, /* VPUNPCKHWDZrrk */ +/* Table7565 */ + 0x3605, /* VPUNPCKHDQZrmk */ + 0x3608, /* VPUNPCKHDQZrrk */ +/* Table7567 */ + 0x20ab, /* VPACKSSDWZrmk */ + 0x20ae, /* VPACKSSDWZrrk */ +/* Table7569 */ + 0x1dd5, /* VMOVDQA32Zrmk */ + 0x1dd9, /* VMOVDQA32Zrrk */ +/* Table7571 */ + 0x317e, /* VPSHUFDZmik */ + 0x3181, /* VPSHUFDZrik */ +/* Table7573 */ + 0x0, /* */ + 0x0, /* */ + 0x3455, /* VPSRLWZmik */ + 0x0, /* */ + 0x336d, /* VPSRAWZmik */ + 0x0, /* */ + 0x3297, /* VPSLLWZmik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3458, /* VPSRLWZrik */ + 0x0, /* */ + 0x3370, /* VPSRAWZrik */ + 0x0, /* */ + 0x329a, /* VPSLLWZrik */ + 0x0, /* */ +/* Table7589 */ + 0x2f80, /* VPRORDZmik */ + 0x2f14, /* VPROLDZmik */ + 0x33a8, /* VPSRLDZmik */ + 0x0, /* */ + 0x32ca, /* VPSRADZmik */ + 0x0, /* */ + 0x31ea, /* VPSLLDZmik */ + 0x0, /* */ + 0x2f83, /* VPRORDZrik */ + 0x2f17, /* VPROLDZrik */ + 0x33ab, /* VPSRLDZrik */ + 0x0, /* */ + 0x32cd, /* VPSRADZrik */ + 0x0, /* */ + 0x31ed, /* VPSLLDZrik */ + 0x0, /* */ +/* Table7605 */ + 0x23b6, /* VPCMPEQBZrmk */ + 0x23b8, /* VPCMPEQBZrrk */ +/* Table7607 */ + 0x23f2, /* VPCMPEQWZrmk */ + 0x23f4, /* VPCMPEQWZrrk */ +/* Table7609 */ + 0x23cc, /* VPCMPEQDZrmk */ + 0x23ce, /* VPCMPEQDZrrk */ +/* Table7611 */ + 0x1140, /* VCVTTPS2UQQZrmk */ + 0x1146, /* VCVTTPS2UQQZrrk */ +/* Table7613 */ + 0xfaa, /* VCVTPS2UQQZrmk */ + 0xfb0, /* VCVTPS2UQQZrrk */ +/* Table7615 */ + 0x1104, /* VCVTTPS2QQZrmk */ + 0x110a, /* VCVTTPS2QQZrrk */ +/* Table7617 */ + 0xf6e, /* VCVTPS2QQZrmk */ + 0xf74, /* VCVTPS2QQZrrk */ +/* Table7619 */ + 0x1dd3, /* VMOVDQA32Zmrk */ + 0x1dda, /* VMOVDQA32Zrrk_REV */ +/* Table7621 */ + 0x345b, /* VPSRLWZrmk */ + 0x345e, /* VPSRLWZrrk */ +/* Table7623 */ + 0x33ae, /* VPSRLDZrmk */ + 0x33b1, /* VPSRLDZrrk */ +/* Table7625 */ + 0x2e25, /* VPMULLWZrmk */ + 0x2e28, /* VPMULLWZrrk */ +/* Table7627 */ + 0x34f2, /* VPSUBUSBZrmk */ + 0x34f5, /* VPSUBUSBZrrk */ +/* Table7629 */ + 0x3508, /* VPSUBUSWZrmk */ + 0x350b, /* VPSUBUSWZrrk */ +/* Table7631 */ + 0x2af4, /* VPMINUBZrmk */ + 0x2af7, /* VPMINUBZrrk */ +/* Table7633 */ + 0x21eb, /* VPANDDZrmk */ + 0x21ee, /* VPANDDZrrk */ +/* Table7635 */ + 0x218c, /* VPADDUSBZrmk */ + 0x218f, /* VPADDUSBZrrk */ +/* Table7637 */ + 0x21a2, /* VPADDUSWZrmk */ + 0x21a5, /* VPADDUSWZrrk */ +/* Table7639 */ + 0x2a28, /* VPMAXUBZrmk */ + 0x2a2b, /* VPMAXUBZrrk */ +/* Table7641 */ + 0x2206, /* VPANDNDZrmk */ + 0x2209, /* VPANDNDZrrk */ +/* Table7643 */ + 0x2258, /* VPAVGBZrmk */ + 0x225b, /* VPAVGBZrrk */ +/* Table7645 */ + 0x3373, /* VPSRAWZrmk */ + 0x3376, /* VPSRAWZrrk */ +/* Table7647 */ + 0x32d0, /* VPSRADZrmk */ + 0x32d3, /* VPSRADZrrk */ +/* Table7649 */ + 0x226e, /* VPAVGWZrmk */ + 0x2271, /* VPAVGWZrrk */ +/* Table7651 */ + 0x2dbf, /* VPMULHUWZrmk */ + 0x2dc2, /* VPMULHUWZrrk */ +/* Table7653 */ + 0x2dd5, /* VPMULHWZrmk */ + 0x2dd8, /* VPMULHWZrrk */ +/* Table7655 */ + 0x34c6, /* VPSUBSBZrmk */ + 0x34c9, /* VPSUBSBZrrk */ +/* Table7657 */ + 0x34dc, /* VPSUBSWZrmk */ + 0x34df, /* VPSUBSWZrrk */ +/* Table7659 */ + 0x2ade, /* VPMINSWZrmk */ + 0x2ae1, /* VPMINSWZrrk */ +/* Table7661 */ + 0x2ed6, /* VPORDZrmk */ + 0x2ed9, /* VPORDZrrk */ +/* Table7663 */ + 0x2160, /* VPADDSBZrmk */ + 0x2163, /* VPADDSBZrrk */ +/* Table7665 */ + 0x2176, /* VPADDSWZrmk */ + 0x2179, /* VPADDSWZrrk */ +/* Table7667 */ + 0x2a12, /* VPMAXSWZrmk */ + 0x2a15, /* VPMAXSWZrrk */ +/* Table7669 */ + 0x36c1, /* VPXORDZrmk */ + 0x36c4, /* VPXORDZrrk */ +/* Table7671 */ + 0x329d, /* VPSLLWZrmk */ + 0x32a0, /* VPSLLWZrrk */ +/* Table7673 */ + 0x31f0, /* VPSLLDZrmk */ + 0x31f3, /* VPSLLDZrrk */ +/* Table7675 */ + 0x29a4, /* VPMADDWDZrmk */ + 0x29a7, /* VPMADDWDZrrk */ +/* Table7677 */ + 0x3472, /* VPSUBBZrmk */ + 0x3475, /* VPSUBBZrrk */ +/* Table7679 */ + 0x351e, /* VPSUBWZrmk */ + 0x3521, /* VPSUBWZrrk */ +/* Table7681 */ + 0x3491, /* VPSUBDZrmk */ + 0x3494, /* VPSUBDZrrk */ +/* Table7683 */ + 0x210c, /* VPADDBZrmk */ + 0x210f, /* VPADDBZrrk */ +/* Table7685 */ + 0x21b8, /* VPADDWZrmk */ + 0x21bb, /* VPADDWZrrk */ +/* Table7687 */ + 0x212b, /* VPADDDZrmk */ + 0x212e, /* VPADDDZrrk */ +/* Table7689 */ + 0xfe6, /* VCVTQQ2PSZrmk */ + 0xfec, /* VCVTQQ2PSZrrk */ +/* Table7691 */ + 0x10a6, /* VCVTTPD2UDQZrmk */ + 0x10ac, /* VCVTTPD2UDQZrrk */ +/* Table7693 */ + 0xebf, /* VCVTPD2UDQZrmk */ + 0xec5, /* VCVTPD2UDQZrrk */ +/* Table7695 */ + 0x1e61, /* VMOVDQU64Zrmk */ + 0x1e65, /* VMOVDQU64Zrrk */ +/* Table7697 */ + 0x11cf, /* VCVTUQQ2PDZrmk */ + 0x11d5, /* VCVTUQQ2PDZrrk */ +/* Table7699 */ + 0x1e5f, /* VMOVDQU64Zmrk */ + 0x1e66, /* VMOVDQU64Zrrk_REV */ +/* Table7701 */ + 0xfc8, /* VCVTQQ2PDZrmk */ + 0xfce, /* VCVTQQ2PDZrrk */ +/* Table7703 */ + 0x1dad, /* VMOVDDUPZrmk */ + 0x1db0, /* VMOVDDUPZrrk */ +/* Table7705 */ + 0x1e1f, /* VMOVDQU16Zrmk */ + 0x1e23, /* VMOVDQU16Zrrk */ +/* Table7707 */ + 0x11ed, /* VCVTUQQ2PSZrmk */ + 0x11f3, /* VCVTUQQ2PSZrrk */ +/* Table7709 */ + 0x1e1d, /* VMOVDQU16Zmrk */ + 0x1e24, /* VMOVDQU16Zrrk_REV */ +/* Table7711 */ + 0xe5f, /* VCVTPD2DQZrmk */ + 0xe65, /* VCVTPD2DQZrrk */ +/* Table7713 */ + 0x1f3b, /* VMOVUPDZrmk */ + 0x1f3f, /* VMOVUPDZrrk */ +/* Table7715 */ + 0x1f39, /* VMOVUPDZmrk */ + 0x1f40, /* VMOVUPDZrrk_REV */ +/* Table7717 */ + 0x3ae8, /* VUNPCKLPDZrmk */ + 0x3aeb, /* VUNPCKLPDZrrk */ +/* Table7719 */ + 0x3aaa, /* VUNPCKHPDZrmk */ + 0x3aad, /* VUNPCKHPDZrrk */ +/* Table7721 */ + 0x1d69, /* VMOVAPDZrmk */ + 0x1d6d, /* VMOVAPDZrrk */ +/* Table7723 */ + 0x1d67, /* VMOVAPDZmrk */ + 0x1d6e, /* VMOVAPDZrrk_REV */ +/* Table7725 */ + 0x39cb, /* VSQRTPDZmk */ + 0x39d1, /* VSQRTPDZrk */ +/* Table7727 */ + 0xc7a, /* VANDPDZrmk */ + 0xc7d, /* VANDPDZrrk */ +/* Table7729 */ + 0xc3c, /* VANDNPDZrmk */ + 0xc3f, /* VANDNPDZrrk */ +/* Table7731 */ + 0x2001, /* VORPDZrmk */ + 0x2004, /* VORPDZrrk */ +/* Table7733 */ + 0x3b26, /* VXORPDZrmk */ + 0x3b29, /* VXORPDZrrk */ +/* Table7735 */ + 0xb70, /* VADDPDZrmk */ + 0xb76, /* VADDPDZrrk */ +/* Table7737 */ + 0x1f99, /* VMULPDZrmk */ + 0x1f9f, /* VMULPDZrrk */ +/* Table7739 */ + 0xe81, /* VCVTPD2PSZrmk */ + 0xe87, /* VCVTPD2PSZrrk */ +/* Table7741 */ + 0x3a2e, /* VSUBPDZrmk */ + 0x3a34, /* VSUBPDZrrk */ +/* Table7743 */ + 0x1cf6, /* VMINPDZrmk */ + 0x1cfc, /* VMINPDZrrk */ +/* Table7745 */ + 0x1232, /* VDIVPDZrmk */ + 0x1238, /* VDIVPDZrrk */ +/* Table7747 */ + 0x1c4b, /* VMAXPDZrmk */ + 0x1c51, /* VMAXPDZrrk */ +/* Table7749 */ + 0x368e, /* VPUNPCKLQDQZrmk */ + 0x3691, /* VPUNPCKLQDQZrrk */ +/* Table7751 */ + 0x3624, /* VPUNPCKHQDQZrmk */ + 0x3627, /* VPUNPCKHQDQZrrk */ +/* Table7753 */ + 0x1df6, /* VMOVDQA64Zrmk */ + 0x1dfa, /* VMOVDQA64Zrrk */ +/* Table7755 */ + 0x2f9b, /* VPRORQZmik */ + 0x2f2f, /* VPROLQZmik */ + 0x0, /* */ + 0x0, /* */ + 0x32fa, /* VPSRAQZmik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x2f9e, /* VPRORQZrik */ + 0x2f32, /* VPROLQZrik */ + 0x0, /* */ + 0x0, /* */ + 0x32fd, /* VPSRAQZrik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table7771 */ + 0x0, /* */ + 0x0, /* */ + 0x33db, /* VPSRLQZmik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x321d, /* VPSLLQZmik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x33de, /* VPSRLQZrik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3220, /* VPSLLQZrik */ + 0x0, /* */ +/* Table7787 */ + 0x10c4, /* VCVTTPD2UQQZrmk */ + 0x10ca, /* VCVTTPD2UQQZrrk */ +/* Table7789 */ + 0xedd, /* VCVTPD2UQQZrmk */ + 0xee3, /* VCVTPD2UQQZrrk */ +/* Table7791 */ + 0x1088, /* VCVTTPD2QQZrmk */ + 0x108e, /* VCVTTPD2QQZrrk */ +/* Table7793 */ + 0xea1, /* VCVTPD2QQZrmk */ + 0xea7, /* VCVTPD2QQZrrk */ +/* Table7795 */ + 0x1df4, /* VMOVDQA64Zmrk */ + 0x1dfb, /* VMOVDQA64Zrrk_REV */ +/* Table7797 */ + 0xd71, /* VCMPPDZrmik */ + 0xd79, /* VCMPPDZrrik */ +/* Table7799 */ + 0x398d, /* VSHUFPDZrmik */ + 0x3990, /* VSHUFPDZrrik */ +/* Table7801 */ + 0x33e1, /* VPSRLQZrmk */ + 0x33e4, /* VPSRLQZrrk */ +/* Table7803 */ + 0x214a, /* VPADDQZrmk */ + 0x214d, /* VPADDQZrrk */ +/* Table7805 */ + 0x2240, /* VPANDQZrmk */ + 0x2243, /* VPANDQZrrk */ +/* Table7807 */ + 0x2221, /* VPANDNQZrmk */ + 0x2224, /* VPANDNQZrrk */ +/* Table7809 */ + 0x3300, /* VPSRAQZrmk */ + 0x3303, /* VPSRAQZrrk */ +/* Table7811 */ + 0x1068, /* VCVTTPD2DQZrmk */ + 0x106e, /* VCVTTPD2DQZrrk */ +/* Table7813 */ + 0x2ef1, /* VPORQZrmk */ + 0x2ef4, /* VPORQZrrk */ +/* Table7815 */ + 0x36dc, /* VPXORQZrmk */ + 0x36df, /* VPXORQZrrk */ +/* Table7817 */ + 0x3223, /* VPSLLQZrmk */ + 0x3226, /* VPSLLQZrrk */ +/* Table7819 */ + 0x2e5f, /* VPMULUDQZrmk */ + 0x2e62, /* VPMULUDQZrrk */ +/* Table7821 */ + 0x34b0, /* VPSUBQZrmk */ + 0x34b3, /* VPSUBQZrrk */ +/* Table7823 */ + 0x3af2, /* VUNPCKLPSZ128rmb */ + 0x0, /* */ +/* Table7825 */ + 0x3ab4, /* VUNPCKHPSZ128rmb */ + 0x0, /* */ +/* Table7827 */ + 0x0, /* */ + 0x3a8d, /* VUCOMISSZrrb */ +/* Table7829 */ + 0x0, /* */ + 0xde3, /* VCOMISSZrrb */ +/* Table7831 */ + 0x39d8, /* VSQRTPSZ128mb */ + 0x39f0, /* VSQRTPSZrb */ +/* Table7833 */ + 0xc84, /* VANDPSZ128rmb */ + 0x0, /* */ +/* Table7835 */ + 0xc46, /* VANDNPSZ128rmb */ + 0x0, /* */ +/* Table7837 */ + 0x200b, /* VORPSZ128rmb */ + 0x0, /* */ +/* Table7839 */ + 0x3b30, /* VXORPSZ128rmb */ + 0x0, /* */ +/* Table7841 */ + 0xb7d, /* VADDPSZ128rmb */ + 0xb95, /* VADDPSZrrb */ +/* Table7843 */ + 0x1fa6, /* VMULPSZ128rmb */ + 0x1fbe, /* VMULPSZrrb */ +/* Table7845 */ + 0xf23, /* VCVTPS2PDZ128rmb */ + 0xf3b, /* VCVTPS2PDZrrb */ +/* Table7847 */ + 0xe28, /* VCVTDQ2PSZ128rmb */ + 0xe40, /* VCVTDQ2PSZrrb */ +/* Table7849 */ + 0x3a3b, /* VSUBPSZ128rmb */ + 0x3a53, /* VSUBPSZrrb */ +/* Table7851 */ + 0x1d03, /* VMINPSZ128rmb */ + 0x1d1b, /* VMINPSZrrb */ +/* Table7853 */ + 0x123f, /* VDIVPSZ128rmb */ + 0x1257, /* VDIVPSZrrb */ +/* Table7855 */ + 0x1c58, /* VMAXPSZ128rmb */ + 0x1c70, /* VMAXPSZrrb */ +/* Table7857 */ + 0x110d, /* VCVTTPS2UDQZ128rmb */ + 0x1125, /* VCVTTPS2UDQZrrb */ +/* Table7859 */ + 0xf77, /* VCVTPS2UDQZ128rmb */ + 0xf8f, /* VCVTPS2UDQZrrb */ +/* Table7861 */ + 0xd82, /* VCMPPSZ128rmbi */ + 0xda5, /* VCMPPSZrrib */ +/* Table7863 */ + 0x3996, /* VSHUFPSZ128rmbi */ + 0x0, /* */ +/* Table7865 */ + 0x0, /* */ + 0x101a, /* VCVTSI2SSZrrb_Int */ +/* Table7867 */ + 0x0, /* */ + 0x1171, /* VCVTTSS2SIZrrb_Int */ +/* Table7869 */ + 0x0, /* */ + 0x1047, /* VCVTSS2SIZrrb_Int */ +/* Table7871 */ + 0x0, /* */ + 0x3a0e, /* VSQRTSSZrb_Int */ +/* Table7873 */ + 0x0, /* */ + 0xbb3, /* VADDSSZrrb_Int */ +/* Table7875 */ + 0x0, /* */ + 0x1fdc, /* VMULSSZrrb_Int */ +/* Table7877 */ + 0x0, /* */ + 0x1039, /* VCVTSS2SDZrrb_Int */ +/* Table7879 */ + 0x10cf, /* VCVTTPS2DQZ128rmb */ + 0x10e7, /* VCVTTPS2DQZrrb */ +/* Table7881 */ + 0x0, /* */ + 0x3a71, /* VSUBSSZrrb_Int */ +/* Table7883 */ + 0x0, /* */ + 0x1d39, /* VMINSSZrrb_Int */ +/* Table7885 */ + 0x0, /* */ + 0x1275, /* VDIVSSZrrb_Int */ +/* Table7887 */ + 0x0, /* */ + 0x1c8e, /* VMAXSSZrrb_Int */ +/* Table7889 */ + 0x0, /* */ + 0x117f, /* VCVTTSS2USIZrrb_Int */ +/* Table7891 */ + 0x0, /* */ + 0x104f, /* VCVTSS2USIZrrb_Int */ +/* Table7893 */ + 0x1181, /* VCVTUDQ2PDZ128rmb */ + 0x0, /* */ +/* Table7895 */ + 0x0, /* */ + 0x11fd, /* VCVTUSI2SSZrrb_Int */ +/* Table7897 */ + 0x0, /* */ + 0xdca, /* VCMPSSZrrb_Int */ +/* Table7899 */ + 0xe09, /* VCVTDQ2PDZ128rmb */ + 0x0, /* */ +/* Table7901 */ + 0x0, /* */ + 0x1011, /* VCVTSI2SDZrrb_Int */ +/* Table7903 */ + 0x0, /* */ + 0x1155, /* VCVTTSD2SIZrrb_Int */ +/* Table7905 */ + 0x0, /* */ + 0xff5, /* VCVTSD2SIZrrb_Int */ +/* Table7907 */ + 0x0, /* */ + 0x1163, /* VCVTTSD2USIZrrb_Int */ +/* Table7909 */ + 0x0, /* */ + 0x100c, /* VCVTSD2USIZrrb_Int */ +/* Table7911 */ + 0x119c, /* VCVTUDQ2PSZ128rmb */ + 0x11b4, /* VCVTUDQ2PSZrrb */ +/* Table7913 */ + 0xf01, /* VCVTPS2DQZ128rmb */ + 0xf19, /* VCVTPS2DQZrrb */ +/* Table7915 */ + 0x365a, /* VPUNPCKLDQZ128rmb */ + 0x0, /* */ +/* Table7917 */ + 0x240e, /* VPCMPGTDZ128rmb */ + 0x0, /* */ +/* Table7919 */ + 0x35f0, /* VPUNPCKHDQZ128rmb */ + 0x0, /* */ +/* Table7921 */ + 0x2096, /* VPACKSSDWZ128rmb */ + 0x0, /* */ +/* Table7923 */ + 0x3168, /* VPSHUFDZ128mbi */ + 0x0, /* */ +/* Table7925 */ + 0x2f6a, /* VPRORDZ128mbi */ + 0x2efe, /* VPROLDZ128mbi */ + 0x3386, /* VPSRLDZ128mbi */ + 0x0, /* */ + 0x32a8, /* VPSRADZ128mbi */ + 0x0, /* */ + 0x31c8, /* VPSLLDZ128mbi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table7941 */ + 0x23be, /* VPCMPEQDZ128rmb */ + 0x0, /* */ +/* Table7943 */ + 0x112b, /* VCVTTPS2UQQZ128rmb */ + 0x1143, /* VCVTTPS2UQQZrrb */ +/* Table7945 */ + 0xf95, /* VCVTPS2UQQZ128rmb */ + 0xfad, /* VCVTPS2UQQZrrb */ +/* Table7947 */ + 0x10ef, /* VCVTTPS2QQZ128rmb */ + 0x1107, /* VCVTTPS2QQZrrb */ +/* Table7949 */ + 0xf59, /* VCVTPS2QQZ128rmb */ + 0xf71, /* VCVTPS2QQZrrb */ +/* Table7951 */ + 0x21d6, /* VPANDDZ128rmb */ + 0x0, /* */ +/* Table7953 */ + 0x21f1, /* VPANDNDZ128rmb */ + 0x0, /* */ +/* Table7955 */ + 0x2ec1, /* VPORDZ128rmb */ + 0x0, /* */ +/* Table7957 */ + 0x36ac, /* VPXORDZ128rmb */ + 0x0, /* */ +/* Table7959 */ + 0x347c, /* VPSUBDZ128rmb */ + 0x0, /* */ +/* Table7961 */ + 0x2116, /* VPADDDZ128rmb */ + 0x0, /* */ +/* Table7963 */ + 0xfd1, /* VCVTQQ2PSZ128rmb */ + 0xfe9, /* VCVTQQ2PSZrrb */ +/* Table7965 */ + 0x1091, /* VCVTTPD2UDQZ128rmb */ + 0x10a9, /* VCVTTPD2UDQZrrb */ +/* Table7967 */ + 0xeaa, /* VCVTPD2UDQZ128rmb */ + 0xec2, /* VCVTPD2UDQZrrb */ +/* Table7969 */ + 0x0, /* */ + 0x102c, /* VCVTSI642SSZrrb_Int */ +/* Table7971 */ + 0x0, /* */ + 0x1168, /* VCVTTSS2SI64Zrrb_Int */ +/* Table7973 */ + 0x0, /* */ + 0x1042, /* VCVTSS2SI64Zrrb_Int */ +/* Table7975 */ + 0x0, /* */ + 0x117a, /* VCVTTSS2USI64Zrrb_Int */ +/* Table7977 */ + 0x0, /* */ + 0x104c, /* VCVTSS2USI64Zrrb_Int */ +/* Table7979 */ + 0x11ba, /* VCVTUQQ2PDZ128rmb */ + 0x11d2, /* VCVTUQQ2PDZrrb */ +/* Table7981 */ + 0x0, /* */ + 0x1207, /* VCVTUSI642SSZrrb_Int */ +/* Table7983 */ + 0xfb3, /* VCVTQQ2PDZ128rmb */ + 0xfcb, /* VCVTQQ2PDZrrb */ +/* Table7985 */ + 0x0, /* */ + 0x1023, /* VCVTSI642SDZrrb_Int */ +/* Table7987 */ + 0x0, /* */ + 0x114c, /* VCVTTSD2SI64Zrrb_Int */ +/* Table7989 */ + 0x0, /* */ + 0xff0, /* VCVTSD2SI64Zrrb_Int */ +/* Table7991 */ + 0x0, /* */ + 0x39ff, /* VSQRTSDZrb_Int */ +/* Table7993 */ + 0x0, /* */ + 0xba4, /* VADDSDZrrb_Int */ +/* Table7995 */ + 0x0, /* */ + 0x1fcd, /* VMULSDZrrb_Int */ +/* Table7997 */ + 0x0, /* */ + 0x1000, /* VCVTSD2SSZrrb_Int */ +/* Table7999 */ + 0x0, /* */ + 0x3a62, /* VSUBSDZrrb_Int */ +/* Table8001 */ + 0x0, /* */ + 0x1d2a, /* VMINSDZrrb_Int */ +/* Table8003 */ + 0x0, /* */ + 0x1266, /* VDIVSDZrrb_Int */ +/* Table8005 */ + 0x0, /* */ + 0x1c7f, /* VMAXSDZrrb_Int */ +/* Table8007 */ + 0x0, /* */ + 0x115e, /* VCVTTSD2USI64Zrrb_Int */ +/* Table8009 */ + 0x0, /* */ + 0x1009, /* VCVTSD2USI64Zrrb_Int */ +/* Table8011 */ + 0x11d8, /* VCVTUQQ2PSZ128rmb */ + 0x11f0, /* VCVTUQQ2PSZrrb */ +/* Table8013 */ + 0x0, /* */ + 0x1202, /* VCVTUSI642SDZrrb_Int */ +/* Table8015 */ + 0x0, /* */ + 0xdb6, /* VCMPSDZrrb_Int */ +/* Table8017 */ + 0xe4a, /* VCVTPD2DQZ128rmb */ + 0xe62, /* VCVTPD2DQZrrb */ +/* Table8019 */ + 0x3ad3, /* VUNPCKLPDZ128rmb */ + 0x0, /* */ +/* Table8021 */ + 0x3a95, /* VUNPCKHPDZ128rmb */ + 0x0, /* */ +/* Table8023 */ + 0x0, /* */ + 0x3a84, /* VUCOMISDZrrb */ +/* Table8025 */ + 0x0, /* */ + 0xdda, /* VCOMISDZrrb */ +/* Table8027 */ + 0x39b6, /* VSQRTPDZ128mb */ + 0x39ce, /* VSQRTPDZrb */ +/* Table8029 */ + 0xc65, /* VANDPDZ128rmb */ + 0x0, /* */ +/* Table8031 */ + 0xc27, /* VANDNPDZ128rmb */ + 0x0, /* */ +/* Table8033 */ + 0x1fec, /* VORPDZ128rmb */ + 0x0, /* */ +/* Table8035 */ + 0x3b11, /* VXORPDZ128rmb */ + 0x0, /* */ +/* Table8037 */ + 0xb5b, /* VADDPDZ128rmb */ + 0xb73, /* VADDPDZrrb */ +/* Table8039 */ + 0x1f84, /* VMULPDZ128rmb */ + 0x1f9c, /* VMULPDZrrb */ +/* Table8041 */ + 0xe6c, /* VCVTPD2PSZ128rmb */ + 0xe84, /* VCVTPD2PSZrrb */ +/* Table8043 */ + 0x3a19, /* VSUBPDZ128rmb */ + 0x3a31, /* VSUBPDZrrb */ +/* Table8045 */ + 0x1ce1, /* VMINPDZ128rmb */ + 0x1cf9, /* VMINPDZrrb */ +/* Table8047 */ + 0x121d, /* VDIVPDZ128rmb */ + 0x1235, /* VDIVPDZrrb */ +/* Table8049 */ + 0x1c36, /* VMAXPDZ128rmb */ + 0x1c4e, /* VMAXPDZrrb */ +/* Table8051 */ + 0x3679, /* VPUNPCKLQDQZ128rmb */ + 0x0, /* */ +/* Table8053 */ + 0x360f, /* VPUNPCKHQDQZ128rmb */ + 0x0, /* */ +/* Table8055 */ + 0x2f85, /* VPRORQZ128mbi */ + 0x2f19, /* VPROLQZ128mbi */ + 0x0, /* */ + 0x0, /* */ + 0x32d8, /* VPSRAQZ128mbi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8071 */ + 0x0, /* */ + 0x0, /* */ + 0x33b9, /* VPSRLQZ128mbi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x31fb, /* VPSLLQZ128mbi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8087 */ + 0x10af, /* VCVTTPD2UQQZ128rmb */ + 0x10c7, /* VCVTTPD2UQQZrrb */ +/* Table8089 */ + 0xec8, /* VCVTPD2UQQZ128rmb */ + 0xee0, /* VCVTPD2UQQZrrb */ +/* Table8091 */ + 0x1073, /* VCVTTPD2QQZ128rmb */ + 0x108b, /* VCVTTPD2QQZrrb */ +/* Table8093 */ + 0xe8c, /* VCVTPD2QQZ128rmb */ + 0xea4, /* VCVTPD2QQZrrb */ +/* Table8095 */ + 0xd52, /* VCMPPDZ128rmbi */ + 0xd75, /* VCMPPDZrrib */ +/* Table8097 */ + 0x3977, /* VSHUFPDZ128rmbi */ + 0x0, /* */ +/* Table8099 */ + 0x2135, /* VPADDQZ128rmb */ + 0x0, /* */ +/* Table8101 */ + 0x222b, /* VPANDQZ128rmb */ + 0x0, /* */ +/* Table8103 */ + 0x220c, /* VPANDNQZ128rmb */ + 0x0, /* */ +/* Table8105 */ + 0x1053, /* VCVTTPD2DQZ128rmb */ + 0x106b, /* VCVTTPD2DQZrrb */ +/* Table8107 */ + 0x2edc, /* VPORQZ128rmb */ + 0x0, /* */ +/* Table8109 */ + 0x36c7, /* VPXORQZ128rmb */ + 0x0, /* */ +/* Table8111 */ + 0x2e4a, /* VPMULUDQZ128rmb */ + 0x0, /* */ +/* Table8113 */ + 0x349b, /* VPSUBQZ128rmb */ + 0x0, /* */ +/* Table8115 */ + 0x3afb, /* VUNPCKLPSZ256rmb */ + 0x0, /* */ +/* Table8117 */ + 0x3abd, /* VUNPCKHPSZ256rmb */ + 0x0, /* */ +/* Table8119 */ + 0x39e1, /* VSQRTPSZ256mb */ + 0x39f0, /* VSQRTPSZrb */ +/* Table8121 */ + 0xc8d, /* VANDPSZ256rmb */ + 0x0, /* */ +/* Table8123 */ + 0xc4f, /* VANDNPSZ256rmb */ + 0x0, /* */ +/* Table8125 */ + 0x2014, /* VORPSZ256rmb */ + 0x0, /* */ +/* Table8127 */ + 0x3b39, /* VXORPSZ256rmb */ + 0x0, /* */ +/* Table8129 */ + 0xb86, /* VADDPSZ256rmb */ + 0xb95, /* VADDPSZrrb */ +/* Table8131 */ + 0x1faf, /* VMULPSZ256rmb */ + 0x1fbe, /* VMULPSZrrb */ +/* Table8133 */ + 0xf2c, /* VCVTPS2PDZ256rmb */ + 0xf3b, /* VCVTPS2PDZrrb */ +/* Table8135 */ + 0xe31, /* VCVTDQ2PSZ256rmb */ + 0xe40, /* VCVTDQ2PSZrrb */ +/* Table8137 */ + 0x3a44, /* VSUBPSZ256rmb */ + 0x3a53, /* VSUBPSZrrb */ +/* Table8139 */ + 0x1d0c, /* VMINPSZ256rmb */ + 0x1d1b, /* VMINPSZrrb */ +/* Table8141 */ + 0x1248, /* VDIVPSZ256rmb */ + 0x1257, /* VDIVPSZrrb */ +/* Table8143 */ + 0x1c61, /* VMAXPSZ256rmb */ + 0x1c70, /* VMAXPSZrrb */ +/* Table8145 */ + 0x1116, /* VCVTTPS2UDQZ256rmb */ + 0x1125, /* VCVTTPS2UDQZrrb */ +/* Table8147 */ + 0xf80, /* VCVTPS2UDQZ256rmb */ + 0xf8f, /* VCVTPS2UDQZrrb */ +/* Table8149 */ + 0xd8e, /* VCMPPSZ256rmbi */ + 0xda5, /* VCMPPSZrrib */ +/* Table8151 */ + 0x399f, /* VSHUFPSZ256rmbi */ + 0x0, /* */ +/* Table8153 */ + 0x10d8, /* VCVTTPS2DQZ256rmb */ + 0x10e7, /* VCVTTPS2DQZrrb */ +/* Table8155 */ + 0x118a, /* VCVTUDQ2PDZ256rmb */ + 0x0, /* */ +/* Table8157 */ + 0xe12, /* VCVTDQ2PDZ256rmb */ + 0x0, /* */ +/* Table8159 */ + 0x11a5, /* VCVTUDQ2PSZ256rmb */ + 0x11b4, /* VCVTUDQ2PSZrrb */ +/* Table8161 */ + 0xf0a, /* VCVTPS2DQZ256rmb */ + 0xf19, /* VCVTPS2DQZrrb */ +/* Table8163 */ + 0x3663, /* VPUNPCKLDQZ256rmb */ + 0x0, /* */ +/* Table8165 */ + 0x2414, /* VPCMPGTDZ256rmb */ + 0x0, /* */ +/* Table8167 */ + 0x35f9, /* VPUNPCKHDQZ256rmb */ + 0x0, /* */ +/* Table8169 */ + 0x209f, /* VPACKSSDWZ256rmb */ + 0x0, /* */ +/* Table8171 */ + 0x3171, /* VPSHUFDZ256mbi */ + 0x0, /* */ +/* Table8173 */ + 0x2f73, /* VPRORDZ256mbi */ + 0x2f07, /* VPROLDZ256mbi */ + 0x3395, /* VPSRLDZ256mbi */ + 0x0, /* */ + 0x32b7, /* VPSRADZ256mbi */ + 0x0, /* */ + 0x31d7, /* VPSLLDZ256mbi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8189 */ + 0x23c4, /* VPCMPEQDZ256rmb */ + 0x0, /* */ +/* Table8191 */ + 0x1134, /* VCVTTPS2UQQZ256rmb */ + 0x1143, /* VCVTTPS2UQQZrrb */ +/* Table8193 */ + 0xf9e, /* VCVTPS2UQQZ256rmb */ + 0xfad, /* VCVTPS2UQQZrrb */ +/* Table8195 */ + 0x10f8, /* VCVTTPS2QQZ256rmb */ + 0x1107, /* VCVTTPS2QQZrrb */ +/* Table8197 */ + 0xf62, /* VCVTPS2QQZ256rmb */ + 0xf71, /* VCVTPS2QQZrrb */ +/* Table8199 */ + 0x21df, /* VPANDDZ256rmb */ + 0x0, /* */ +/* Table8201 */ + 0x21fa, /* VPANDNDZ256rmb */ + 0x0, /* */ +/* Table8203 */ + 0x2eca, /* VPORDZ256rmb */ + 0x0, /* */ +/* Table8205 */ + 0x36b5, /* VPXORDZ256rmb */ + 0x0, /* */ +/* Table8207 */ + 0x3485, /* VPSUBDZ256rmb */ + 0x0, /* */ +/* Table8209 */ + 0x211f, /* VPADDDZ256rmb */ + 0x0, /* */ +/* Table8211 */ + 0xfda, /* VCVTQQ2PSZ256rmb */ + 0xfe9, /* VCVTQQ2PSZrrb */ +/* Table8213 */ + 0x109a, /* VCVTTPD2UDQZ256rmb */ + 0x10a9, /* VCVTTPD2UDQZrrb */ +/* Table8215 */ + 0xeb3, /* VCVTPD2UDQZ256rmb */ + 0xec2, /* VCVTPD2UDQZrrb */ +/* Table8217 */ + 0x11c3, /* VCVTUQQ2PDZ256rmb */ + 0x11d2, /* VCVTUQQ2PDZrrb */ +/* Table8219 */ + 0xfbc, /* VCVTQQ2PDZ256rmb */ + 0xfcb, /* VCVTQQ2PDZrrb */ +/* Table8221 */ + 0x11e1, /* VCVTUQQ2PSZ256rmb */ + 0x11f0, /* VCVTUQQ2PSZrrb */ +/* Table8223 */ + 0xe53, /* VCVTPD2DQZ256rmb */ + 0xe62, /* VCVTPD2DQZrrb */ +/* Table8225 */ + 0x3adc, /* VUNPCKLPDZ256rmb */ + 0x0, /* */ +/* Table8227 */ + 0x3a9e, /* VUNPCKHPDZ256rmb */ + 0x0, /* */ +/* Table8229 */ + 0x39bf, /* VSQRTPDZ256mb */ + 0x39ce, /* VSQRTPDZrb */ +/* Table8231 */ + 0xc6e, /* VANDPDZ256rmb */ + 0x0, /* */ +/* Table8233 */ + 0xc30, /* VANDNPDZ256rmb */ + 0x0, /* */ +/* Table8235 */ + 0x1ff5, /* VORPDZ256rmb */ + 0x0, /* */ +/* Table8237 */ + 0x3b1a, /* VXORPDZ256rmb */ + 0x0, /* */ +/* Table8239 */ + 0xb64, /* VADDPDZ256rmb */ + 0xb73, /* VADDPDZrrb */ +/* Table8241 */ + 0x1f8d, /* VMULPDZ256rmb */ + 0x1f9c, /* VMULPDZrrb */ +/* Table8243 */ + 0xe75, /* VCVTPD2PSZ256rmb */ + 0xe84, /* VCVTPD2PSZrrb */ +/* Table8245 */ + 0x3a22, /* VSUBPDZ256rmb */ + 0x3a31, /* VSUBPDZrrb */ +/* Table8247 */ + 0x1cea, /* VMINPDZ256rmb */ + 0x1cf9, /* VMINPDZrrb */ +/* Table8249 */ + 0x1226, /* VDIVPDZ256rmb */ + 0x1235, /* VDIVPDZrrb */ +/* Table8251 */ + 0x1c3f, /* VMAXPDZ256rmb */ + 0x1c4e, /* VMAXPDZrrb */ +/* Table8253 */ + 0x3682, /* VPUNPCKLQDQZ256rmb */ + 0x0, /* */ +/* Table8255 */ + 0x3618, /* VPUNPCKHQDQZ256rmb */ + 0x0, /* */ +/* Table8257 */ + 0x2f8e, /* VPRORQZ256mbi */ + 0x2f22, /* VPROLQZ256mbi */ + 0x0, /* */ + 0x0, /* */ + 0x32e7, /* VPSRAQZ256mbi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8273 */ + 0x0, /* */ + 0x0, /* */ + 0x33c8, /* VPSRLQZ256mbi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x320a, /* VPSLLQZ256mbi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8289 */ + 0x10b8, /* VCVTTPD2UQQZ256rmb */ + 0x10c7, /* VCVTTPD2UQQZrrb */ +/* Table8291 */ + 0xed1, /* VCVTPD2UQQZ256rmb */ + 0xee0, /* VCVTPD2UQQZrrb */ +/* Table8293 */ + 0x107c, /* VCVTTPD2QQZ256rmb */ + 0x108b, /* VCVTTPD2QQZrrb */ +/* Table8295 */ + 0xe95, /* VCVTPD2QQZ256rmb */ + 0xea4, /* VCVTPD2QQZrrb */ +/* Table8297 */ + 0xd5e, /* VCMPPDZ256rmbi */ + 0xd75, /* VCMPPDZrrib */ +/* Table8299 */ + 0x3980, /* VSHUFPDZ256rmbi */ + 0x0, /* */ +/* Table8301 */ + 0x213e, /* VPADDQZ256rmb */ + 0x0, /* */ +/* Table8303 */ + 0x2234, /* VPANDQZ256rmb */ + 0x0, /* */ +/* Table8305 */ + 0x2215, /* VPANDNQZ256rmb */ + 0x0, /* */ +/* Table8307 */ + 0x105c, /* VCVTTPD2DQZ256rmb */ + 0x106b, /* VCVTTPD2DQZrrb */ +/* Table8309 */ + 0x2ee5, /* VPORQZ256rmb */ + 0x0, /* */ +/* Table8311 */ + 0x36d0, /* VPXORQZ256rmb */ + 0x0, /* */ +/* Table8313 */ + 0x2e53, /* VPMULUDQZ256rmb */ + 0x0, /* */ +/* Table8315 */ + 0x34a4, /* VPSUBQZ256rmb */ + 0x0, /* */ +/* Table8317 */ + 0x3b04, /* VUNPCKLPSZrmb */ + 0x0, /* */ +/* Table8319 */ + 0x3ac6, /* VUNPCKHPSZrmb */ + 0x0, /* */ +/* Table8321 */ + 0x39ea, /* VSQRTPSZmb */ + 0x39f0, /* VSQRTPSZrb */ +/* Table8323 */ + 0xc96, /* VANDPSZrmb */ + 0x0, /* */ +/* Table8325 */ + 0xc58, /* VANDNPSZrmb */ + 0x0, /* */ +/* Table8327 */ + 0x201d, /* VORPSZrmb */ + 0x0, /* */ +/* Table8329 */ + 0x3b42, /* VXORPSZrmb */ + 0x0, /* */ +/* Table8331 */ + 0xb8f, /* VADDPSZrmb */ + 0xb95, /* VADDPSZrrb */ +/* Table8333 */ + 0x1fb8, /* VMULPSZrmb */ + 0x1fbe, /* VMULPSZrrb */ +/* Table8335 */ + 0xf35, /* VCVTPS2PDZrmb */ + 0xf3b, /* VCVTPS2PDZrrb */ +/* Table8337 */ + 0xe3a, /* VCVTDQ2PSZrmb */ + 0xe40, /* VCVTDQ2PSZrrb */ +/* Table8339 */ + 0x3a4d, /* VSUBPSZrmb */ + 0x3a53, /* VSUBPSZrrb */ +/* Table8341 */ + 0x1d15, /* VMINPSZrmb */ + 0x1d1b, /* VMINPSZrrb */ +/* Table8343 */ + 0x1251, /* VDIVPSZrmb */ + 0x1257, /* VDIVPSZrrb */ +/* Table8345 */ + 0x1c6a, /* VMAXPSZrmb */ + 0x1c70, /* VMAXPSZrrb */ +/* Table8347 */ + 0x111f, /* VCVTTPS2UDQZrmb */ + 0x1125, /* VCVTTPS2UDQZrrb */ +/* Table8349 */ + 0xf89, /* VCVTPS2UDQZrmb */ + 0xf8f, /* VCVTPS2UDQZrrb */ +/* Table8351 */ + 0xd9a, /* VCMPPSZrmbi */ + 0xda5, /* VCMPPSZrrib */ +/* Table8353 */ + 0x39a8, /* VSHUFPSZrmbi */ + 0x0, /* */ +/* Table8355 */ + 0x10e1, /* VCVTTPS2DQZrmb */ + 0x10e7, /* VCVTTPS2DQZrrb */ +/* Table8357 */ + 0x1193, /* VCVTUDQ2PDZrmb */ + 0x0, /* */ +/* Table8359 */ + 0xe1b, /* VCVTDQ2PDZrmb */ + 0x0, /* */ +/* Table8361 */ + 0x11ae, /* VCVTUDQ2PSZrmb */ + 0x11b4, /* VCVTUDQ2PSZrrb */ +/* Table8363 */ + 0xf13, /* VCVTPS2DQZrmb */ + 0xf19, /* VCVTPS2DQZrrb */ +/* Table8365 */ + 0x366c, /* VPUNPCKLDQZrmb */ + 0x0, /* */ +/* Table8367 */ + 0x241a, /* VPCMPGTDZrmb */ + 0x0, /* */ +/* Table8369 */ + 0x3602, /* VPUNPCKHDQZrmb */ + 0x0, /* */ +/* Table8371 */ + 0x20a8, /* VPACKSSDWZrmb */ + 0x0, /* */ +/* Table8373 */ + 0x317a, /* VPSHUFDZmbi */ + 0x0, /* */ +/* Table8375 */ + 0x2f7c, /* VPRORDZmbi */ + 0x2f10, /* VPROLDZmbi */ + 0x33a4, /* VPSRLDZmbi */ + 0x0, /* */ + 0x32c6, /* VPSRADZmbi */ + 0x0, /* */ + 0x31e6, /* VPSLLDZmbi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8391 */ + 0x23ca, /* VPCMPEQDZrmb */ + 0x0, /* */ +/* Table8393 */ + 0x113d, /* VCVTTPS2UQQZrmb */ + 0x1143, /* VCVTTPS2UQQZrrb */ +/* Table8395 */ + 0xfa7, /* VCVTPS2UQQZrmb */ + 0xfad, /* VCVTPS2UQQZrrb */ +/* Table8397 */ + 0x1101, /* VCVTTPS2QQZrmb */ + 0x1107, /* VCVTTPS2QQZrrb */ +/* Table8399 */ + 0xf6b, /* VCVTPS2QQZrmb */ + 0xf71, /* VCVTPS2QQZrrb */ +/* Table8401 */ + 0x21e8, /* VPANDDZrmb */ + 0x0, /* */ +/* Table8403 */ + 0x2203, /* VPANDNDZrmb */ + 0x0, /* */ +/* Table8405 */ + 0x2ed3, /* VPORDZrmb */ + 0x0, /* */ +/* Table8407 */ + 0x36be, /* VPXORDZrmb */ + 0x0, /* */ +/* Table8409 */ + 0x348e, /* VPSUBDZrmb */ + 0x0, /* */ +/* Table8411 */ + 0x2128, /* VPADDDZrmb */ + 0x0, /* */ +/* Table8413 */ + 0xfe3, /* VCVTQQ2PSZrmb */ + 0xfe9, /* VCVTQQ2PSZrrb */ +/* Table8415 */ + 0x10a3, /* VCVTTPD2UDQZrmb */ + 0x10a9, /* VCVTTPD2UDQZrrb */ +/* Table8417 */ + 0xebc, /* VCVTPD2UDQZrmb */ + 0xec2, /* VCVTPD2UDQZrrb */ +/* Table8419 */ + 0x11cc, /* VCVTUQQ2PDZrmb */ + 0x11d2, /* VCVTUQQ2PDZrrb */ +/* Table8421 */ + 0xfc5, /* VCVTQQ2PDZrmb */ + 0xfcb, /* VCVTQQ2PDZrrb */ +/* Table8423 */ + 0x11ea, /* VCVTUQQ2PSZrmb */ + 0x11f0, /* VCVTUQQ2PSZrrb */ +/* Table8425 */ + 0xe5c, /* VCVTPD2DQZrmb */ + 0xe62, /* VCVTPD2DQZrrb */ +/* Table8427 */ + 0x3ae5, /* VUNPCKLPDZrmb */ + 0x0, /* */ +/* Table8429 */ + 0x3aa7, /* VUNPCKHPDZrmb */ + 0x0, /* */ +/* Table8431 */ + 0x39c8, /* VSQRTPDZmb */ + 0x39ce, /* VSQRTPDZrb */ +/* Table8433 */ + 0xc77, /* VANDPDZrmb */ + 0x0, /* */ +/* Table8435 */ + 0xc39, /* VANDNPDZrmb */ + 0x0, /* */ +/* Table8437 */ + 0x1ffe, /* VORPDZrmb */ + 0x0, /* */ +/* Table8439 */ + 0x3b23, /* VXORPDZrmb */ + 0x0, /* */ +/* Table8441 */ + 0xb6d, /* VADDPDZrmb */ + 0xb73, /* VADDPDZrrb */ +/* Table8443 */ + 0x1f96, /* VMULPDZrmb */ + 0x1f9c, /* VMULPDZrrb */ +/* Table8445 */ + 0xe7e, /* VCVTPD2PSZrmb */ + 0xe84, /* VCVTPD2PSZrrb */ +/* Table8447 */ + 0x3a2b, /* VSUBPDZrmb */ + 0x3a31, /* VSUBPDZrrb */ +/* Table8449 */ + 0x1cf3, /* VMINPDZrmb */ + 0x1cf9, /* VMINPDZrrb */ +/* Table8451 */ + 0x122f, /* VDIVPDZrmb */ + 0x1235, /* VDIVPDZrrb */ +/* Table8453 */ + 0x1c48, /* VMAXPDZrmb */ + 0x1c4e, /* VMAXPDZrrb */ +/* Table8455 */ + 0x368b, /* VPUNPCKLQDQZrmb */ + 0x0, /* */ +/* Table8457 */ + 0x3621, /* VPUNPCKHQDQZrmb */ + 0x0, /* */ +/* Table8459 */ + 0x2f97, /* VPRORQZmbi */ + 0x2f2b, /* VPROLQZmbi */ + 0x0, /* */ + 0x0, /* */ + 0x32f6, /* VPSRAQZmbi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8475 */ + 0x0, /* */ + 0x0, /* */ + 0x33d7, /* VPSRLQZmbi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3219, /* VPSLLQZmbi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8491 */ + 0x10c1, /* VCVTTPD2UQQZrmb */ + 0x10c7, /* VCVTTPD2UQQZrrb */ +/* Table8493 */ + 0xeda, /* VCVTPD2UQQZrmb */ + 0xee0, /* VCVTPD2UQQZrrb */ +/* Table8495 */ + 0x1085, /* VCVTTPD2QQZrmb */ + 0x108b, /* VCVTTPD2QQZrrb */ +/* Table8497 */ + 0xe9e, /* VCVTPD2QQZrmb */ + 0xea4, /* VCVTPD2QQZrrb */ +/* Table8499 */ + 0xd6a, /* VCMPPDZrmbi */ + 0xd75, /* VCMPPDZrrib */ +/* Table8501 */ + 0x3989, /* VSHUFPDZrmbi */ + 0x0, /* */ +/* Table8503 */ + 0x2147, /* VPADDQZrmb */ + 0x0, /* */ +/* Table8505 */ + 0x223d, /* VPANDQZrmb */ + 0x0, /* */ +/* Table8507 */ + 0x221e, /* VPANDNQZrmb */ + 0x0, /* */ +/* Table8509 */ + 0x1065, /* VCVTTPD2DQZrmb */ + 0x106b, /* VCVTTPD2DQZrrb */ +/* Table8511 */ + 0x2eee, /* VPORQZrmb */ + 0x0, /* */ +/* Table8513 */ + 0x36d9, /* VPXORQZrmb */ + 0x0, /* */ +/* Table8515 */ + 0x2e5c, /* VPMULUDQZrmb */ + 0x0, /* */ +/* Table8517 */ + 0x34ad, /* VPSUBQZrmb */ + 0x0, /* */ +/* Table8519 */ + 0x3af3, /* VUNPCKLPSZ128rmbk */ + 0x0, /* */ +/* Table8521 */ + 0x3ab5, /* VUNPCKHPSZ128rmbk */ + 0x0, /* */ +/* Table8523 */ + 0x39d9, /* VSQRTPSZ128mbk */ + 0x39f1, /* VSQRTPSZrbk */ +/* Table8525 */ + 0xc85, /* VANDPSZ128rmbk */ + 0x0, /* */ +/* Table8527 */ + 0xc47, /* VANDNPSZ128rmbk */ + 0x0, /* */ +/* Table8529 */ + 0x200c, /* VORPSZ128rmbk */ + 0x0, /* */ +/* Table8531 */ + 0x3b31, /* VXORPSZ128rmbk */ + 0x0, /* */ +/* Table8533 */ + 0xb7e, /* VADDPSZ128rmbk */ + 0xb96, /* VADDPSZrrbk */ +/* Table8535 */ + 0x1fa7, /* VMULPSZ128rmbk */ + 0x1fbf, /* VMULPSZrrbk */ +/* Table8537 */ + 0xf24, /* VCVTPS2PDZ128rmbk */ + 0xf3c, /* VCVTPS2PDZrrbk */ +/* Table8539 */ + 0xe29, /* VCVTDQ2PSZ128rmbk */ + 0xe41, /* VCVTDQ2PSZrrbk */ +/* Table8541 */ + 0x3a3c, /* VSUBPSZ128rmbk */ + 0x3a54, /* VSUBPSZrrbk */ +/* Table8543 */ + 0x1d04, /* VMINPSZ128rmbk */ + 0x1d1c, /* VMINPSZrrbk */ +/* Table8545 */ + 0x1240, /* VDIVPSZ128rmbk */ + 0x1258, /* VDIVPSZrrbk */ +/* Table8547 */ + 0x1c59, /* VMAXPSZ128rmbk */ + 0x1c71, /* VMAXPSZrrbk */ +/* Table8549 */ + 0x110e, /* VCVTTPS2UDQZ128rmbk */ + 0x1126, /* VCVTTPS2UDQZrrbk */ +/* Table8551 */ + 0xf78, /* VCVTPS2UDQZ128rmbk */ + 0xf90, /* VCVTPS2UDQZrrbk */ +/* Table8553 */ + 0xd85, /* VCMPPSZ128rmbik */ + 0xda8, /* VCMPPSZrribk */ +/* Table8555 */ + 0x3997, /* VSHUFPSZ128rmbik */ + 0x0, /* */ +/* Table8557 */ + 0x0, /* */ + 0x3a0f, /* VSQRTSSZrb_Intk */ +/* Table8559 */ + 0x0, /* */ + 0xbb4, /* VADDSSZrrb_Intk */ +/* Table8561 */ + 0x0, /* */ + 0x1fdd, /* VMULSSZrrb_Intk */ +/* Table8563 */ + 0x0, /* */ + 0x103a, /* VCVTSS2SDZrrb_Intk */ +/* Table8565 */ + 0x10d0, /* VCVTTPS2DQZ128rmbk */ + 0x10e8, /* VCVTTPS2DQZrrbk */ +/* Table8567 */ + 0x0, /* */ + 0x3a72, /* VSUBSSZrrb_Intk */ +/* Table8569 */ + 0x0, /* */ + 0x1d3a, /* VMINSSZrrb_Intk */ +/* Table8571 */ + 0x0, /* */ + 0x1276, /* VDIVSSZrrb_Intk */ +/* Table8573 */ + 0x0, /* */ + 0x1c8f, /* VMAXSSZrrb_Intk */ +/* Table8575 */ + 0x1182, /* VCVTUDQ2PDZ128rmbk */ + 0x0, /* */ +/* Table8577 */ + 0x0, /* */ + 0xdcb, /* VCMPSSZrrb_Intk */ +/* Table8579 */ + 0xe0a, /* VCVTDQ2PDZ128rmbk */ + 0x0, /* */ +/* Table8581 */ + 0x119d, /* VCVTUDQ2PSZ128rmbk */ + 0x11b5, /* VCVTUDQ2PSZrrbk */ +/* Table8583 */ + 0xf02, /* VCVTPS2DQZ128rmbk */ + 0xf1a, /* VCVTPS2DQZrrbk */ +/* Table8585 */ + 0x365b, /* VPUNPCKLDQZ128rmbk */ + 0x0, /* */ +/* Table8587 */ + 0x240f, /* VPCMPGTDZ128rmbk */ + 0x0, /* */ +/* Table8589 */ + 0x35f1, /* VPUNPCKHDQZ128rmbk */ + 0x0, /* */ +/* Table8591 */ + 0x2097, /* VPACKSSDWZ128rmbk */ + 0x0, /* */ +/* Table8593 */ + 0x3169, /* VPSHUFDZ128mbik */ + 0x0, /* */ +/* Table8595 */ + 0x2f6b, /* VPRORDZ128mbik */ + 0x2eff, /* VPROLDZ128mbik */ + 0x3387, /* VPSRLDZ128mbik */ + 0x0, /* */ + 0x32a9, /* VPSRADZ128mbik */ + 0x0, /* */ + 0x31c9, /* VPSLLDZ128mbik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8611 */ + 0x23bf, /* VPCMPEQDZ128rmbk */ + 0x0, /* */ +/* Table8613 */ + 0x112c, /* VCVTTPS2UQQZ128rmbk */ + 0x1144, /* VCVTTPS2UQQZrrbk */ +/* Table8615 */ + 0xf96, /* VCVTPS2UQQZ128rmbk */ + 0xfae, /* VCVTPS2UQQZrrbk */ +/* Table8617 */ + 0x10f0, /* VCVTTPS2QQZ128rmbk */ + 0x1108, /* VCVTTPS2QQZrrbk */ +/* Table8619 */ + 0xf5a, /* VCVTPS2QQZ128rmbk */ + 0xf72, /* VCVTPS2QQZrrbk */ +/* Table8621 */ + 0x21d7, /* VPANDDZ128rmbk */ + 0x0, /* */ +/* Table8623 */ + 0x21f2, /* VPANDNDZ128rmbk */ + 0x0, /* */ +/* Table8625 */ + 0x2ec2, /* VPORDZ128rmbk */ + 0x0, /* */ +/* Table8627 */ + 0x36ad, /* VPXORDZ128rmbk */ + 0x0, /* */ +/* Table8629 */ + 0x347d, /* VPSUBDZ128rmbk */ + 0x0, /* */ +/* Table8631 */ + 0x2117, /* VPADDDZ128rmbk */ + 0x0, /* */ +/* Table8633 */ + 0xfd2, /* VCVTQQ2PSZ128rmbk */ + 0xfea, /* VCVTQQ2PSZrrbk */ +/* Table8635 */ + 0x1092, /* VCVTTPD2UDQZ128rmbk */ + 0x10aa, /* VCVTTPD2UDQZrrbk */ +/* Table8637 */ + 0xeab, /* VCVTPD2UDQZ128rmbk */ + 0xec3, /* VCVTPD2UDQZrrbk */ +/* Table8639 */ + 0x11bb, /* VCVTUQQ2PDZ128rmbk */ + 0x11d3, /* VCVTUQQ2PDZrrbk */ +/* Table8641 */ + 0xfb4, /* VCVTQQ2PDZ128rmbk */ + 0xfcc, /* VCVTQQ2PDZrrbk */ +/* Table8643 */ + 0x0, /* */ + 0x3a00, /* VSQRTSDZrb_Intk */ +/* Table8645 */ + 0x0, /* */ + 0xba5, /* VADDSDZrrb_Intk */ +/* Table8647 */ + 0x0, /* */ + 0x1fce, /* VMULSDZrrb_Intk */ +/* Table8649 */ + 0x0, /* */ + 0x1001, /* VCVTSD2SSZrrb_Intk */ +/* Table8651 */ + 0x0, /* */ + 0x3a63, /* VSUBSDZrrb_Intk */ +/* Table8653 */ + 0x0, /* */ + 0x1d2b, /* VMINSDZrrb_Intk */ +/* Table8655 */ + 0x0, /* */ + 0x1267, /* VDIVSDZrrb_Intk */ +/* Table8657 */ + 0x0, /* */ + 0x1c80, /* VMAXSDZrrb_Intk */ +/* Table8659 */ + 0x11d9, /* VCVTUQQ2PSZ128rmbk */ + 0x11f1, /* VCVTUQQ2PSZrrbk */ +/* Table8661 */ + 0x0, /* */ + 0xdb7, /* VCMPSDZrrb_Intk */ +/* Table8663 */ + 0xe4b, /* VCVTPD2DQZ128rmbk */ + 0xe63, /* VCVTPD2DQZrrbk */ +/* Table8665 */ + 0x3ad4, /* VUNPCKLPDZ128rmbk */ + 0x0, /* */ +/* Table8667 */ + 0x3a96, /* VUNPCKHPDZ128rmbk */ + 0x0, /* */ +/* Table8669 */ + 0x39b7, /* VSQRTPDZ128mbk */ + 0x39cf, /* VSQRTPDZrbk */ +/* Table8671 */ + 0xc66, /* VANDPDZ128rmbk */ + 0x0, /* */ +/* Table8673 */ + 0xc28, /* VANDNPDZ128rmbk */ + 0x0, /* */ +/* Table8675 */ + 0x1fed, /* VORPDZ128rmbk */ + 0x0, /* */ +/* Table8677 */ + 0x3b12, /* VXORPDZ128rmbk */ + 0x0, /* */ +/* Table8679 */ + 0xb5c, /* VADDPDZ128rmbk */ + 0xb74, /* VADDPDZrrbk */ +/* Table8681 */ + 0x1f85, /* VMULPDZ128rmbk */ + 0x1f9d, /* VMULPDZrrbk */ +/* Table8683 */ + 0xe6d, /* VCVTPD2PSZ128rmbk */ + 0xe85, /* VCVTPD2PSZrrbk */ +/* Table8685 */ + 0x3a1a, /* VSUBPDZ128rmbk */ + 0x3a32, /* VSUBPDZrrbk */ +/* Table8687 */ + 0x1ce2, /* VMINPDZ128rmbk */ + 0x1cfa, /* VMINPDZrrbk */ +/* Table8689 */ + 0x121e, /* VDIVPDZ128rmbk */ + 0x1236, /* VDIVPDZrrbk */ +/* Table8691 */ + 0x1c37, /* VMAXPDZ128rmbk */ + 0x1c4f, /* VMAXPDZrrbk */ +/* Table8693 */ + 0x367a, /* VPUNPCKLQDQZ128rmbk */ + 0x0, /* */ +/* Table8695 */ + 0x3610, /* VPUNPCKHQDQZ128rmbk */ + 0x0, /* */ +/* Table8697 */ + 0x2f86, /* VPRORQZ128mbik */ + 0x2f1a, /* VPROLQZ128mbik */ + 0x0, /* */ + 0x0, /* */ + 0x32d9, /* VPSRAQZ128mbik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8713 */ + 0x0, /* */ + 0x0, /* */ + 0x33ba, /* VPSRLQZ128mbik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x31fc, /* VPSLLQZ128mbik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8729 */ + 0x10b0, /* VCVTTPD2UQQZ128rmbk */ + 0x10c8, /* VCVTTPD2UQQZrrbk */ +/* Table8731 */ + 0xec9, /* VCVTPD2UQQZ128rmbk */ + 0xee1, /* VCVTPD2UQQZrrbk */ +/* Table8733 */ + 0x1074, /* VCVTTPD2QQZ128rmbk */ + 0x108c, /* VCVTTPD2QQZrrbk */ +/* Table8735 */ + 0xe8d, /* VCVTPD2QQZ128rmbk */ + 0xea5, /* VCVTPD2QQZrrbk */ +/* Table8737 */ + 0xd55, /* VCMPPDZ128rmbik */ + 0xd78, /* VCMPPDZrribk */ +/* Table8739 */ + 0x3978, /* VSHUFPDZ128rmbik */ + 0x0, /* */ +/* Table8741 */ + 0x2136, /* VPADDQZ128rmbk */ + 0x0, /* */ +/* Table8743 */ + 0x222c, /* VPANDQZ128rmbk */ + 0x0, /* */ +/* Table8745 */ + 0x220d, /* VPANDNQZ128rmbk */ + 0x0, /* */ +/* Table8747 */ + 0x1054, /* VCVTTPD2DQZ128rmbk */ + 0x106c, /* VCVTTPD2DQZrrbk */ +/* Table8749 */ + 0x2edd, /* VPORQZ128rmbk */ + 0x0, /* */ +/* Table8751 */ + 0x36c8, /* VPXORQZ128rmbk */ + 0x0, /* */ +/* Table8753 */ + 0x2e4b, /* VPMULUDQZ128rmbk */ + 0x0, /* */ +/* Table8755 */ + 0x349c, /* VPSUBQZ128rmbk */ + 0x0, /* */ +/* Table8757 */ + 0x3afc, /* VUNPCKLPSZ256rmbk */ + 0x0, /* */ +/* Table8759 */ + 0x3abe, /* VUNPCKHPSZ256rmbk */ + 0x0, /* */ +/* Table8761 */ + 0x39e2, /* VSQRTPSZ256mbk */ + 0x39f1, /* VSQRTPSZrbk */ +/* Table8763 */ + 0xc8e, /* VANDPSZ256rmbk */ + 0x0, /* */ +/* Table8765 */ + 0xc50, /* VANDNPSZ256rmbk */ + 0x0, /* */ +/* Table8767 */ + 0x2015, /* VORPSZ256rmbk */ + 0x0, /* */ +/* Table8769 */ + 0x3b3a, /* VXORPSZ256rmbk */ + 0x0, /* */ +/* Table8771 */ + 0xb87, /* VADDPSZ256rmbk */ + 0xb96, /* VADDPSZrrbk */ +/* Table8773 */ + 0x1fb0, /* VMULPSZ256rmbk */ + 0x1fbf, /* VMULPSZrrbk */ +/* Table8775 */ + 0xf2d, /* VCVTPS2PDZ256rmbk */ + 0xf3c, /* VCVTPS2PDZrrbk */ +/* Table8777 */ + 0xe32, /* VCVTDQ2PSZ256rmbk */ + 0xe41, /* VCVTDQ2PSZrrbk */ +/* Table8779 */ + 0x3a45, /* VSUBPSZ256rmbk */ + 0x3a54, /* VSUBPSZrrbk */ +/* Table8781 */ + 0x1d0d, /* VMINPSZ256rmbk */ + 0x1d1c, /* VMINPSZrrbk */ +/* Table8783 */ + 0x1249, /* VDIVPSZ256rmbk */ + 0x1258, /* VDIVPSZrrbk */ +/* Table8785 */ + 0x1c62, /* VMAXPSZ256rmbk */ + 0x1c71, /* VMAXPSZrrbk */ +/* Table8787 */ + 0x1117, /* VCVTTPS2UDQZ256rmbk */ + 0x1126, /* VCVTTPS2UDQZrrbk */ +/* Table8789 */ + 0xf81, /* VCVTPS2UDQZ256rmbk */ + 0xf90, /* VCVTPS2UDQZrrbk */ +/* Table8791 */ + 0xd91, /* VCMPPSZ256rmbik */ + 0xda8, /* VCMPPSZrribk */ +/* Table8793 */ + 0x39a0, /* VSHUFPSZ256rmbik */ + 0x0, /* */ +/* Table8795 */ + 0x10d9, /* VCVTTPS2DQZ256rmbk */ + 0x10e8, /* VCVTTPS2DQZrrbk */ +/* Table8797 */ + 0x118b, /* VCVTUDQ2PDZ256rmbk */ + 0x0, /* */ +/* Table8799 */ + 0xe13, /* VCVTDQ2PDZ256rmbk */ + 0x0, /* */ +/* Table8801 */ + 0x11a6, /* VCVTUDQ2PSZ256rmbk */ + 0x11b5, /* VCVTUDQ2PSZrrbk */ +/* Table8803 */ + 0xf0b, /* VCVTPS2DQZ256rmbk */ + 0xf1a, /* VCVTPS2DQZrrbk */ +/* Table8805 */ + 0x3664, /* VPUNPCKLDQZ256rmbk */ + 0x0, /* */ +/* Table8807 */ + 0x2415, /* VPCMPGTDZ256rmbk */ + 0x0, /* */ +/* Table8809 */ + 0x35fa, /* VPUNPCKHDQZ256rmbk */ + 0x0, /* */ +/* Table8811 */ + 0x20a0, /* VPACKSSDWZ256rmbk */ + 0x0, /* */ +/* Table8813 */ + 0x3172, /* VPSHUFDZ256mbik */ + 0x0, /* */ +/* Table8815 */ + 0x2f74, /* VPRORDZ256mbik */ + 0x2f08, /* VPROLDZ256mbik */ + 0x3396, /* VPSRLDZ256mbik */ + 0x0, /* */ + 0x32b8, /* VPSRADZ256mbik */ + 0x0, /* */ + 0x31d8, /* VPSLLDZ256mbik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8831 */ + 0x23c5, /* VPCMPEQDZ256rmbk */ + 0x0, /* */ +/* Table8833 */ + 0x1135, /* VCVTTPS2UQQZ256rmbk */ + 0x1144, /* VCVTTPS2UQQZrrbk */ +/* Table8835 */ + 0xf9f, /* VCVTPS2UQQZ256rmbk */ + 0xfae, /* VCVTPS2UQQZrrbk */ +/* Table8837 */ + 0x10f9, /* VCVTTPS2QQZ256rmbk */ + 0x1108, /* VCVTTPS2QQZrrbk */ +/* Table8839 */ + 0xf63, /* VCVTPS2QQZ256rmbk */ + 0xf72, /* VCVTPS2QQZrrbk */ +/* Table8841 */ + 0x21e0, /* VPANDDZ256rmbk */ + 0x0, /* */ +/* Table8843 */ + 0x21fb, /* VPANDNDZ256rmbk */ + 0x0, /* */ +/* Table8845 */ + 0x2ecb, /* VPORDZ256rmbk */ + 0x0, /* */ +/* Table8847 */ + 0x36b6, /* VPXORDZ256rmbk */ + 0x0, /* */ +/* Table8849 */ + 0x3486, /* VPSUBDZ256rmbk */ + 0x0, /* */ +/* Table8851 */ + 0x2120, /* VPADDDZ256rmbk */ + 0x0, /* */ +/* Table8853 */ + 0xfdb, /* VCVTQQ2PSZ256rmbk */ + 0xfea, /* VCVTQQ2PSZrrbk */ +/* Table8855 */ + 0x109b, /* VCVTTPD2UDQZ256rmbk */ + 0x10aa, /* VCVTTPD2UDQZrrbk */ +/* Table8857 */ + 0xeb4, /* VCVTPD2UDQZ256rmbk */ + 0xec3, /* VCVTPD2UDQZrrbk */ +/* Table8859 */ + 0x11c4, /* VCVTUQQ2PDZ256rmbk */ + 0x11d3, /* VCVTUQQ2PDZrrbk */ +/* Table8861 */ + 0xfbd, /* VCVTQQ2PDZ256rmbk */ + 0xfcc, /* VCVTQQ2PDZrrbk */ +/* Table8863 */ + 0x11e2, /* VCVTUQQ2PSZ256rmbk */ + 0x11f1, /* VCVTUQQ2PSZrrbk */ +/* Table8865 */ + 0xe54, /* VCVTPD2DQZ256rmbk */ + 0xe63, /* VCVTPD2DQZrrbk */ +/* Table8867 */ + 0x3add, /* VUNPCKLPDZ256rmbk */ + 0x0, /* */ +/* Table8869 */ + 0x3a9f, /* VUNPCKHPDZ256rmbk */ + 0x0, /* */ +/* Table8871 */ + 0x39c0, /* VSQRTPDZ256mbk */ + 0x39cf, /* VSQRTPDZrbk */ +/* Table8873 */ + 0xc6f, /* VANDPDZ256rmbk */ + 0x0, /* */ +/* Table8875 */ + 0xc31, /* VANDNPDZ256rmbk */ + 0x0, /* */ +/* Table8877 */ + 0x1ff6, /* VORPDZ256rmbk */ + 0x0, /* */ +/* Table8879 */ + 0x3b1b, /* VXORPDZ256rmbk */ + 0x0, /* */ +/* Table8881 */ + 0xb65, /* VADDPDZ256rmbk */ + 0xb74, /* VADDPDZrrbk */ +/* Table8883 */ + 0x1f8e, /* VMULPDZ256rmbk */ + 0x1f9d, /* VMULPDZrrbk */ +/* Table8885 */ + 0xe76, /* VCVTPD2PSZ256rmbk */ + 0xe85, /* VCVTPD2PSZrrbk */ +/* Table8887 */ + 0x3a23, /* VSUBPDZ256rmbk */ + 0x3a32, /* VSUBPDZrrbk */ +/* Table8889 */ + 0x1ceb, /* VMINPDZ256rmbk */ + 0x1cfa, /* VMINPDZrrbk */ +/* Table8891 */ + 0x1227, /* VDIVPDZ256rmbk */ + 0x1236, /* VDIVPDZrrbk */ +/* Table8893 */ + 0x1c40, /* VMAXPDZ256rmbk */ + 0x1c4f, /* VMAXPDZrrbk */ +/* Table8895 */ + 0x3683, /* VPUNPCKLQDQZ256rmbk */ + 0x0, /* */ +/* Table8897 */ + 0x3619, /* VPUNPCKHQDQZ256rmbk */ + 0x0, /* */ +/* Table8899 */ + 0x2f8f, /* VPRORQZ256mbik */ + 0x2f23, /* VPROLQZ256mbik */ + 0x0, /* */ + 0x0, /* */ + 0x32e8, /* VPSRAQZ256mbik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8915 */ + 0x0, /* */ + 0x0, /* */ + 0x33c9, /* VPSRLQZ256mbik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x320b, /* VPSLLQZ256mbik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table8931 */ + 0x10b9, /* VCVTTPD2UQQZ256rmbk */ + 0x10c8, /* VCVTTPD2UQQZrrbk */ +/* Table8933 */ + 0xed2, /* VCVTPD2UQQZ256rmbk */ + 0xee1, /* VCVTPD2UQQZrrbk */ +/* Table8935 */ + 0x107d, /* VCVTTPD2QQZ256rmbk */ + 0x108c, /* VCVTTPD2QQZrrbk */ +/* Table8937 */ + 0xe96, /* VCVTPD2QQZ256rmbk */ + 0xea5, /* VCVTPD2QQZrrbk */ +/* Table8939 */ + 0xd61, /* VCMPPDZ256rmbik */ + 0xd78, /* VCMPPDZrribk */ +/* Table8941 */ + 0x3981, /* VSHUFPDZ256rmbik */ + 0x0, /* */ +/* Table8943 */ + 0x213f, /* VPADDQZ256rmbk */ + 0x0, /* */ +/* Table8945 */ + 0x2235, /* VPANDQZ256rmbk */ + 0x0, /* */ +/* Table8947 */ + 0x2216, /* VPANDNQZ256rmbk */ + 0x0, /* */ +/* Table8949 */ + 0x105d, /* VCVTTPD2DQZ256rmbk */ + 0x106c, /* VCVTTPD2DQZrrbk */ +/* Table8951 */ + 0x2ee6, /* VPORQZ256rmbk */ + 0x0, /* */ +/* Table8953 */ + 0x36d1, /* VPXORQZ256rmbk */ + 0x0, /* */ +/* Table8955 */ + 0x2e54, /* VPMULUDQZ256rmbk */ + 0x0, /* */ +/* Table8957 */ + 0x34a5, /* VPSUBQZ256rmbk */ + 0x0, /* */ +/* Table8959 */ + 0x3b05, /* VUNPCKLPSZrmbk */ + 0x0, /* */ +/* Table8961 */ + 0x3ac7, /* VUNPCKHPSZrmbk */ + 0x0, /* */ +/* Table8963 */ + 0x39eb, /* VSQRTPSZmbk */ + 0x39f1, /* VSQRTPSZrbk */ +/* Table8965 */ + 0xc97, /* VANDPSZrmbk */ + 0x0, /* */ +/* Table8967 */ + 0xc59, /* VANDNPSZrmbk */ + 0x0, /* */ +/* Table8969 */ + 0x201e, /* VORPSZrmbk */ + 0x0, /* */ +/* Table8971 */ + 0x3b43, /* VXORPSZrmbk */ + 0x0, /* */ +/* Table8973 */ + 0xb90, /* VADDPSZrmbk */ + 0xb96, /* VADDPSZrrbk */ +/* Table8975 */ + 0x1fb9, /* VMULPSZrmbk */ + 0x1fbf, /* VMULPSZrrbk */ +/* Table8977 */ + 0xf36, /* VCVTPS2PDZrmbk */ + 0xf3c, /* VCVTPS2PDZrrbk */ +/* Table8979 */ + 0xe3b, /* VCVTDQ2PSZrmbk */ + 0xe41, /* VCVTDQ2PSZrrbk */ +/* Table8981 */ + 0x3a4e, /* VSUBPSZrmbk */ + 0x3a54, /* VSUBPSZrrbk */ +/* Table8983 */ + 0x1d16, /* VMINPSZrmbk */ + 0x1d1c, /* VMINPSZrrbk */ +/* Table8985 */ + 0x1252, /* VDIVPSZrmbk */ + 0x1258, /* VDIVPSZrrbk */ +/* Table8987 */ + 0x1c6b, /* VMAXPSZrmbk */ + 0x1c71, /* VMAXPSZrrbk */ +/* Table8989 */ + 0x1120, /* VCVTTPS2UDQZrmbk */ + 0x1126, /* VCVTTPS2UDQZrrbk */ +/* Table8991 */ + 0xf8a, /* VCVTPS2UDQZrmbk */ + 0xf90, /* VCVTPS2UDQZrrbk */ +/* Table8993 */ + 0xd9d, /* VCMPPSZrmbik */ + 0xda8, /* VCMPPSZrribk */ +/* Table8995 */ + 0x39a9, /* VSHUFPSZrmbik */ + 0x0, /* */ +/* Table8997 */ + 0x10e2, /* VCVTTPS2DQZrmbk */ + 0x10e8, /* VCVTTPS2DQZrrbk */ +/* Table8999 */ + 0x1194, /* VCVTUDQ2PDZrmbk */ + 0x0, /* */ +/* Table9001 */ + 0xe1c, /* VCVTDQ2PDZrmbk */ + 0x0, /* */ +/* Table9003 */ + 0x11af, /* VCVTUDQ2PSZrmbk */ + 0x11b5, /* VCVTUDQ2PSZrrbk */ +/* Table9005 */ + 0xf14, /* VCVTPS2DQZrmbk */ + 0xf1a, /* VCVTPS2DQZrrbk */ +/* Table9007 */ + 0x366d, /* VPUNPCKLDQZrmbk */ + 0x0, /* */ +/* Table9009 */ + 0x241b, /* VPCMPGTDZrmbk */ + 0x0, /* */ +/* Table9011 */ + 0x3603, /* VPUNPCKHDQZrmbk */ + 0x0, /* */ +/* Table9013 */ + 0x20a9, /* VPACKSSDWZrmbk */ + 0x0, /* */ +/* Table9015 */ + 0x317b, /* VPSHUFDZmbik */ + 0x0, /* */ +/* Table9017 */ + 0x2f7d, /* VPRORDZmbik */ + 0x2f11, /* VPROLDZmbik */ + 0x33a5, /* VPSRLDZmbik */ + 0x0, /* */ + 0x32c7, /* VPSRADZmbik */ + 0x0, /* */ + 0x31e7, /* VPSLLDZmbik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table9033 */ + 0x23cb, /* VPCMPEQDZrmbk */ + 0x0, /* */ +/* Table9035 */ + 0x113e, /* VCVTTPS2UQQZrmbk */ + 0x1144, /* VCVTTPS2UQQZrrbk */ +/* Table9037 */ + 0xfa8, /* VCVTPS2UQQZrmbk */ + 0xfae, /* VCVTPS2UQQZrrbk */ +/* Table9039 */ + 0x1102, /* VCVTTPS2QQZrmbk */ + 0x1108, /* VCVTTPS2QQZrrbk */ +/* Table9041 */ + 0xf6c, /* VCVTPS2QQZrmbk */ + 0xf72, /* VCVTPS2QQZrrbk */ +/* Table9043 */ + 0x21e9, /* VPANDDZrmbk */ + 0x0, /* */ +/* Table9045 */ + 0x2204, /* VPANDNDZrmbk */ + 0x0, /* */ +/* Table9047 */ + 0x2ed4, /* VPORDZrmbk */ + 0x0, /* */ +/* Table9049 */ + 0x36bf, /* VPXORDZrmbk */ + 0x0, /* */ +/* Table9051 */ + 0x348f, /* VPSUBDZrmbk */ + 0x0, /* */ +/* Table9053 */ + 0x2129, /* VPADDDZrmbk */ + 0x0, /* */ +/* Table9055 */ + 0xfe4, /* VCVTQQ2PSZrmbk */ + 0xfea, /* VCVTQQ2PSZrrbk */ +/* Table9057 */ + 0x10a4, /* VCVTTPD2UDQZrmbk */ + 0x10aa, /* VCVTTPD2UDQZrrbk */ +/* Table9059 */ + 0xebd, /* VCVTPD2UDQZrmbk */ + 0xec3, /* VCVTPD2UDQZrrbk */ +/* Table9061 */ + 0x11cd, /* VCVTUQQ2PDZrmbk */ + 0x11d3, /* VCVTUQQ2PDZrrbk */ +/* Table9063 */ + 0xfc6, /* VCVTQQ2PDZrmbk */ + 0xfcc, /* VCVTQQ2PDZrrbk */ +/* Table9065 */ + 0x11eb, /* VCVTUQQ2PSZrmbk */ + 0x11f1, /* VCVTUQQ2PSZrrbk */ +/* Table9067 */ + 0xe5d, /* VCVTPD2DQZrmbk */ + 0xe63, /* VCVTPD2DQZrrbk */ +/* Table9069 */ + 0x3ae6, /* VUNPCKLPDZrmbk */ + 0x0, /* */ +/* Table9071 */ + 0x3aa8, /* VUNPCKHPDZrmbk */ + 0x0, /* */ +/* Table9073 */ + 0x39c9, /* VSQRTPDZmbk */ + 0x39cf, /* VSQRTPDZrbk */ +/* Table9075 */ + 0xc78, /* VANDPDZrmbk */ + 0x0, /* */ +/* Table9077 */ + 0xc3a, /* VANDNPDZrmbk */ + 0x0, /* */ +/* Table9079 */ + 0x1fff, /* VORPDZrmbk */ + 0x0, /* */ +/* Table9081 */ + 0x3b24, /* VXORPDZrmbk */ + 0x0, /* */ +/* Table9083 */ + 0xb6e, /* VADDPDZrmbk */ + 0xb74, /* VADDPDZrrbk */ +/* Table9085 */ + 0x1f97, /* VMULPDZrmbk */ + 0x1f9d, /* VMULPDZrrbk */ +/* Table9087 */ + 0xe7f, /* VCVTPD2PSZrmbk */ + 0xe85, /* VCVTPD2PSZrrbk */ +/* Table9089 */ + 0x3a2c, /* VSUBPDZrmbk */ + 0x3a32, /* VSUBPDZrrbk */ +/* Table9091 */ + 0x1cf4, /* VMINPDZrmbk */ + 0x1cfa, /* VMINPDZrrbk */ +/* Table9093 */ + 0x1230, /* VDIVPDZrmbk */ + 0x1236, /* VDIVPDZrrbk */ +/* Table9095 */ + 0x1c49, /* VMAXPDZrmbk */ + 0x1c4f, /* VMAXPDZrrbk */ +/* Table9097 */ + 0x368c, /* VPUNPCKLQDQZrmbk */ + 0x0, /* */ +/* Table9099 */ + 0x3622, /* VPUNPCKHQDQZrmbk */ + 0x0, /* */ +/* Table9101 */ + 0x2f98, /* VPRORQZmbik */ + 0x2f2c, /* VPROLQZmbik */ + 0x0, /* */ + 0x0, /* */ + 0x32f7, /* VPSRAQZmbik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table9117 */ + 0x0, /* */ + 0x0, /* */ + 0x33d8, /* VPSRLQZmbik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x321a, /* VPSLLQZmbik */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table9133 */ + 0x10c2, /* VCVTTPD2UQQZrmbk */ + 0x10c8, /* VCVTTPD2UQQZrrbk */ +/* Table9135 */ + 0xedb, /* VCVTPD2UQQZrmbk */ + 0xee1, /* VCVTPD2UQQZrrbk */ +/* Table9137 */ + 0x1086, /* VCVTTPD2QQZrmbk */ + 0x108c, /* VCVTTPD2QQZrrbk */ +/* Table9139 */ + 0xe9f, /* VCVTPD2QQZrmbk */ + 0xea5, /* VCVTPD2QQZrrbk */ +/* Table9141 */ + 0xd6d, /* VCMPPDZrmbik */ + 0xd78, /* VCMPPDZrribk */ +/* Table9143 */ + 0x398a, /* VSHUFPDZrmbik */ + 0x0, /* */ +/* Table9145 */ + 0x2148, /* VPADDQZrmbk */ + 0x0, /* */ +/* Table9147 */ + 0x223e, /* VPANDQZrmbk */ + 0x0, /* */ +/* Table9149 */ + 0x221f, /* VPANDNQZrmbk */ + 0x0, /* */ +/* Table9151 */ + 0x1066, /* VCVTTPD2DQZrmbk */ + 0x106c, /* VCVTTPD2DQZrrbk */ +/* Table9153 */ + 0x2eef, /* VPORQZrmbk */ + 0x0, /* */ +/* Table9155 */ + 0x36da, /* VPXORQZrmbk */ + 0x0, /* */ +/* Table9157 */ + 0x2e5d, /* VPMULUDQZrmbk */ + 0x0, /* */ +/* Table9159 */ + 0x34ae, /* VPSUBQZrmbk */ + 0x0, /* */ +/* Table9161 */ + 0x3af4, /* VUNPCKLPSZ128rmbkz */ + 0x0, /* */ +/* Table9163 */ + 0x3ab6, /* VUNPCKHPSZ128rmbkz */ + 0x0, /* */ +/* Table9165 */ + 0x39da, /* VSQRTPSZ128mbkz */ + 0x39f2, /* VSQRTPSZrbkz */ +/* Table9167 */ + 0xc86, /* VANDPSZ128rmbkz */ + 0x0, /* */ +/* Table9169 */ + 0xc48, /* VANDNPSZ128rmbkz */ + 0x0, /* */ +/* Table9171 */ + 0x200d, /* VORPSZ128rmbkz */ + 0x0, /* */ +/* Table9173 */ + 0x3b32, /* VXORPSZ128rmbkz */ + 0x0, /* */ +/* Table9175 */ + 0xb7f, /* VADDPSZ128rmbkz */ + 0xb97, /* VADDPSZrrbkz */ +/* Table9177 */ + 0x1fa8, /* VMULPSZ128rmbkz */ + 0x1fc0, /* VMULPSZrrbkz */ +/* Table9179 */ + 0xf25, /* VCVTPS2PDZ128rmbkz */ + 0xf3d, /* VCVTPS2PDZrrbkz */ +/* Table9181 */ + 0xe2a, /* VCVTDQ2PSZ128rmbkz */ + 0xe42, /* VCVTDQ2PSZrrbkz */ +/* Table9183 */ + 0x3a3d, /* VSUBPSZ128rmbkz */ + 0x3a55, /* VSUBPSZrrbkz */ +/* Table9185 */ + 0x1d05, /* VMINPSZ128rmbkz */ + 0x1d1d, /* VMINPSZrrbkz */ +/* Table9187 */ + 0x1241, /* VDIVPSZ128rmbkz */ + 0x1259, /* VDIVPSZrrbkz */ +/* Table9189 */ + 0x1c5a, /* VMAXPSZ128rmbkz */ + 0x1c72, /* VMAXPSZrrbkz */ +/* Table9191 */ + 0x110f, /* VCVTTPS2UDQZ128rmbkz */ + 0x1127, /* VCVTTPS2UDQZrrbkz */ +/* Table9193 */ + 0xf79, /* VCVTPS2UDQZ128rmbkz */ + 0xf91, /* VCVTPS2UDQZrrbkz */ +/* Table9195 */ + 0x3998, /* VSHUFPSZ128rmbikz */ + 0x0, /* */ +/* Table9197 */ + 0x0, /* */ + 0x3a10, /* VSQRTSSZrb_Intkz */ +/* Table9199 */ + 0x0, /* */ + 0xbb5, /* VADDSSZrrb_Intkz */ +/* Table9201 */ + 0x0, /* */ + 0x1fde, /* VMULSSZrrb_Intkz */ +/* Table9203 */ + 0x0, /* */ + 0x103b, /* VCVTSS2SDZrrb_Intkz */ +/* Table9205 */ + 0x10d1, /* VCVTTPS2DQZ128rmbkz */ + 0x10e9, /* VCVTTPS2DQZrrbkz */ +/* Table9207 */ + 0x0, /* */ + 0x3a73, /* VSUBSSZrrb_Intkz */ +/* Table9209 */ + 0x0, /* */ + 0x1d3b, /* VMINSSZrrb_Intkz */ +/* Table9211 */ + 0x0, /* */ + 0x1277, /* VDIVSSZrrb_Intkz */ +/* Table9213 */ + 0x0, /* */ + 0x1c90, /* VMAXSSZrrb_Intkz */ +/* Table9215 */ + 0x1183, /* VCVTUDQ2PDZ128rmbkz */ + 0x0, /* */ +/* Table9217 */ + 0xe0b, /* VCVTDQ2PDZ128rmbkz */ + 0x0, /* */ +/* Table9219 */ + 0x119e, /* VCVTUDQ2PSZ128rmbkz */ + 0x11b6, /* VCVTUDQ2PSZrrbkz */ +/* Table9221 */ + 0xf03, /* VCVTPS2DQZ128rmbkz */ + 0xf1b, /* VCVTPS2DQZrrbkz */ +/* Table9223 */ + 0x365c, /* VPUNPCKLDQZ128rmbkz */ + 0x0, /* */ +/* Table9225 */ + 0x35f2, /* VPUNPCKHDQZ128rmbkz */ + 0x0, /* */ +/* Table9227 */ + 0x2098, /* VPACKSSDWZ128rmbkz */ + 0x0, /* */ +/* Table9229 */ + 0x316a, /* VPSHUFDZ128mbikz */ + 0x0, /* */ +/* Table9231 */ + 0x2f6c, /* VPRORDZ128mbikz */ + 0x2f00, /* VPROLDZ128mbikz */ + 0x3388, /* VPSRLDZ128mbikz */ + 0x0, /* */ + 0x32aa, /* VPSRADZ128mbikz */ + 0x0, /* */ + 0x31ca, /* VPSLLDZ128mbikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table9247 */ + 0x112d, /* VCVTTPS2UQQZ128rmbkz */ + 0x1145, /* VCVTTPS2UQQZrrbkz */ +/* Table9249 */ + 0xf97, /* VCVTPS2UQQZ128rmbkz */ + 0xfaf, /* VCVTPS2UQQZrrbkz */ +/* Table9251 */ + 0x10f1, /* VCVTTPS2QQZ128rmbkz */ + 0x1109, /* VCVTTPS2QQZrrbkz */ +/* Table9253 */ + 0xf5b, /* VCVTPS2QQZ128rmbkz */ + 0xf73, /* VCVTPS2QQZrrbkz */ +/* Table9255 */ + 0x21d8, /* VPANDDZ128rmbkz */ + 0x0, /* */ +/* Table9257 */ + 0x21f3, /* VPANDNDZ128rmbkz */ + 0x0, /* */ +/* Table9259 */ + 0x2ec3, /* VPORDZ128rmbkz */ + 0x0, /* */ +/* Table9261 */ + 0x36ae, /* VPXORDZ128rmbkz */ + 0x0, /* */ +/* Table9263 */ + 0x347e, /* VPSUBDZ128rmbkz */ + 0x0, /* */ +/* Table9265 */ + 0x2118, /* VPADDDZ128rmbkz */ + 0x0, /* */ +/* Table9267 */ + 0xfd3, /* VCVTQQ2PSZ128rmbkz */ + 0xfeb, /* VCVTQQ2PSZrrbkz */ +/* Table9269 */ + 0x1093, /* VCVTTPD2UDQZ128rmbkz */ + 0x10ab, /* VCVTTPD2UDQZrrbkz */ +/* Table9271 */ + 0xeac, /* VCVTPD2UDQZ128rmbkz */ + 0xec4, /* VCVTPD2UDQZrrbkz */ +/* Table9273 */ + 0x11bc, /* VCVTUQQ2PDZ128rmbkz */ + 0x11d4, /* VCVTUQQ2PDZrrbkz */ +/* Table9275 */ + 0xfb5, /* VCVTQQ2PDZ128rmbkz */ + 0xfcd, /* VCVTQQ2PDZrrbkz */ +/* Table9277 */ + 0x0, /* */ + 0x3a01, /* VSQRTSDZrb_Intkz */ +/* Table9279 */ + 0x0, /* */ + 0xba6, /* VADDSDZrrb_Intkz */ +/* Table9281 */ + 0x0, /* */ + 0x1fcf, /* VMULSDZrrb_Intkz */ +/* Table9283 */ + 0x0, /* */ + 0x1002, /* VCVTSD2SSZrrb_Intkz */ +/* Table9285 */ + 0x0, /* */ + 0x3a64, /* VSUBSDZrrb_Intkz */ +/* Table9287 */ + 0x0, /* */ + 0x1d2c, /* VMINSDZrrb_Intkz */ +/* Table9289 */ + 0x0, /* */ + 0x1268, /* VDIVSDZrrb_Intkz */ +/* Table9291 */ + 0x0, /* */ + 0x1c81, /* VMAXSDZrrb_Intkz */ +/* Table9293 */ + 0x11da, /* VCVTUQQ2PSZ128rmbkz */ + 0x11f2, /* VCVTUQQ2PSZrrbkz */ +/* Table9295 */ + 0xe4c, /* VCVTPD2DQZ128rmbkz */ + 0xe64, /* VCVTPD2DQZrrbkz */ +/* Table9297 */ + 0x3ad5, /* VUNPCKLPDZ128rmbkz */ + 0x0, /* */ +/* Table9299 */ + 0x3a97, /* VUNPCKHPDZ128rmbkz */ + 0x0, /* */ +/* Table9301 */ + 0x39b8, /* VSQRTPDZ128mbkz */ + 0x39d0, /* VSQRTPDZrbkz */ +/* Table9303 */ + 0xc67, /* VANDPDZ128rmbkz */ + 0x0, /* */ +/* Table9305 */ + 0xc29, /* VANDNPDZ128rmbkz */ + 0x0, /* */ +/* Table9307 */ + 0x1fee, /* VORPDZ128rmbkz */ + 0x0, /* */ +/* Table9309 */ + 0x3b13, /* VXORPDZ128rmbkz */ + 0x0, /* */ +/* Table9311 */ + 0xb5d, /* VADDPDZ128rmbkz */ + 0xb75, /* VADDPDZrrbkz */ +/* Table9313 */ + 0x1f86, /* VMULPDZ128rmbkz */ + 0x1f9e, /* VMULPDZrrbkz */ +/* Table9315 */ + 0xe6e, /* VCVTPD2PSZ128rmbkz */ + 0xe86, /* VCVTPD2PSZrrbkz */ +/* Table9317 */ + 0x3a1b, /* VSUBPDZ128rmbkz */ + 0x3a33, /* VSUBPDZrrbkz */ +/* Table9319 */ + 0x1ce3, /* VMINPDZ128rmbkz */ + 0x1cfb, /* VMINPDZrrbkz */ +/* Table9321 */ + 0x121f, /* VDIVPDZ128rmbkz */ + 0x1237, /* VDIVPDZrrbkz */ +/* Table9323 */ + 0x1c38, /* VMAXPDZ128rmbkz */ + 0x1c50, /* VMAXPDZrrbkz */ +/* Table9325 */ + 0x367b, /* VPUNPCKLQDQZ128rmbkz */ + 0x0, /* */ +/* Table9327 */ + 0x3611, /* VPUNPCKHQDQZ128rmbkz */ + 0x0, /* */ +/* Table9329 */ + 0x2f87, /* VPRORQZ128mbikz */ + 0x2f1b, /* VPROLQZ128mbikz */ + 0x0, /* */ + 0x0, /* */ + 0x32da, /* VPSRAQZ128mbikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table9345 */ + 0x0, /* */ + 0x0, /* */ + 0x33bb, /* VPSRLQZ128mbikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x31fd, /* VPSLLQZ128mbikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table9361 */ + 0x10b1, /* VCVTTPD2UQQZ128rmbkz */ + 0x10c9, /* VCVTTPD2UQQZrrbkz */ +/* Table9363 */ + 0xeca, /* VCVTPD2UQQZ128rmbkz */ + 0xee2, /* VCVTPD2UQQZrrbkz */ +/* Table9365 */ + 0x1075, /* VCVTTPD2QQZ128rmbkz */ + 0x108d, /* VCVTTPD2QQZrrbkz */ +/* Table9367 */ + 0xe8e, /* VCVTPD2QQZ128rmbkz */ + 0xea6, /* VCVTPD2QQZrrbkz */ +/* Table9369 */ + 0x3979, /* VSHUFPDZ128rmbikz */ + 0x0, /* */ +/* Table9371 */ + 0x2137, /* VPADDQZ128rmbkz */ + 0x0, /* */ +/* Table9373 */ + 0x222d, /* VPANDQZ128rmbkz */ + 0x0, /* */ +/* Table9375 */ + 0x220e, /* VPANDNQZ128rmbkz */ + 0x0, /* */ +/* Table9377 */ + 0x1055, /* VCVTTPD2DQZ128rmbkz */ + 0x106d, /* VCVTTPD2DQZrrbkz */ +/* Table9379 */ + 0x2ede, /* VPORQZ128rmbkz */ + 0x0, /* */ +/* Table9381 */ + 0x36c9, /* VPXORQZ128rmbkz */ + 0x0, /* */ +/* Table9383 */ + 0x2e4c, /* VPMULUDQZ128rmbkz */ + 0x0, /* */ +/* Table9385 */ + 0x349d, /* VPSUBQZ128rmbkz */ + 0x0, /* */ +/* Table9387 */ + 0x3afd, /* VUNPCKLPSZ256rmbkz */ + 0x0, /* */ +/* Table9389 */ + 0x3abf, /* VUNPCKHPSZ256rmbkz */ + 0x0, /* */ +/* Table9391 */ + 0x39e3, /* VSQRTPSZ256mbkz */ + 0x39f2, /* VSQRTPSZrbkz */ +/* Table9393 */ + 0xc8f, /* VANDPSZ256rmbkz */ + 0x0, /* */ +/* Table9395 */ + 0xc51, /* VANDNPSZ256rmbkz */ + 0x0, /* */ +/* Table9397 */ + 0x2016, /* VORPSZ256rmbkz */ + 0x0, /* */ +/* Table9399 */ + 0x3b3b, /* VXORPSZ256rmbkz */ + 0x0, /* */ +/* Table9401 */ + 0xb88, /* VADDPSZ256rmbkz */ + 0xb97, /* VADDPSZrrbkz */ +/* Table9403 */ + 0x1fb1, /* VMULPSZ256rmbkz */ + 0x1fc0, /* VMULPSZrrbkz */ +/* Table9405 */ + 0xf2e, /* VCVTPS2PDZ256rmbkz */ + 0xf3d, /* VCVTPS2PDZrrbkz */ +/* Table9407 */ + 0xe33, /* VCVTDQ2PSZ256rmbkz */ + 0xe42, /* VCVTDQ2PSZrrbkz */ +/* Table9409 */ + 0x3a46, /* VSUBPSZ256rmbkz */ + 0x3a55, /* VSUBPSZrrbkz */ +/* Table9411 */ + 0x1d0e, /* VMINPSZ256rmbkz */ + 0x1d1d, /* VMINPSZrrbkz */ +/* Table9413 */ + 0x124a, /* VDIVPSZ256rmbkz */ + 0x1259, /* VDIVPSZrrbkz */ +/* Table9415 */ + 0x1c63, /* VMAXPSZ256rmbkz */ + 0x1c72, /* VMAXPSZrrbkz */ +/* Table9417 */ + 0x1118, /* VCVTTPS2UDQZ256rmbkz */ + 0x1127, /* VCVTTPS2UDQZrrbkz */ +/* Table9419 */ + 0xf82, /* VCVTPS2UDQZ256rmbkz */ + 0xf91, /* VCVTPS2UDQZrrbkz */ +/* Table9421 */ + 0x39a1, /* VSHUFPSZ256rmbikz */ + 0x0, /* */ +/* Table9423 */ + 0x10da, /* VCVTTPS2DQZ256rmbkz */ + 0x10e9, /* VCVTTPS2DQZrrbkz */ +/* Table9425 */ + 0x118c, /* VCVTUDQ2PDZ256rmbkz */ + 0x0, /* */ +/* Table9427 */ + 0xe14, /* VCVTDQ2PDZ256rmbkz */ + 0x0, /* */ +/* Table9429 */ + 0x11a7, /* VCVTUDQ2PSZ256rmbkz */ + 0x11b6, /* VCVTUDQ2PSZrrbkz */ +/* Table9431 */ + 0xf0c, /* VCVTPS2DQZ256rmbkz */ + 0xf1b, /* VCVTPS2DQZrrbkz */ +/* Table9433 */ + 0x3665, /* VPUNPCKLDQZ256rmbkz */ + 0x0, /* */ +/* Table9435 */ + 0x35fb, /* VPUNPCKHDQZ256rmbkz */ + 0x0, /* */ +/* Table9437 */ + 0x20a1, /* VPACKSSDWZ256rmbkz */ + 0x0, /* */ +/* Table9439 */ + 0x3173, /* VPSHUFDZ256mbikz */ + 0x0, /* */ +/* Table9441 */ + 0x2f75, /* VPRORDZ256mbikz */ + 0x2f09, /* VPROLDZ256mbikz */ + 0x3397, /* VPSRLDZ256mbikz */ + 0x0, /* */ + 0x32b9, /* VPSRADZ256mbikz */ + 0x0, /* */ + 0x31d9, /* VPSLLDZ256mbikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table9457 */ + 0x1136, /* VCVTTPS2UQQZ256rmbkz */ + 0x1145, /* VCVTTPS2UQQZrrbkz */ +/* Table9459 */ + 0xfa0, /* VCVTPS2UQQZ256rmbkz */ + 0xfaf, /* VCVTPS2UQQZrrbkz */ +/* Table9461 */ + 0x10fa, /* VCVTTPS2QQZ256rmbkz */ + 0x1109, /* VCVTTPS2QQZrrbkz */ +/* Table9463 */ + 0xf64, /* VCVTPS2QQZ256rmbkz */ + 0xf73, /* VCVTPS2QQZrrbkz */ +/* Table9465 */ + 0x21e1, /* VPANDDZ256rmbkz */ + 0x0, /* */ +/* Table9467 */ + 0x21fc, /* VPANDNDZ256rmbkz */ + 0x0, /* */ +/* Table9469 */ + 0x2ecc, /* VPORDZ256rmbkz */ + 0x0, /* */ +/* Table9471 */ + 0x36b7, /* VPXORDZ256rmbkz */ + 0x0, /* */ +/* Table9473 */ + 0x3487, /* VPSUBDZ256rmbkz */ + 0x0, /* */ +/* Table9475 */ + 0x2121, /* VPADDDZ256rmbkz */ + 0x0, /* */ +/* Table9477 */ + 0xfdc, /* VCVTQQ2PSZ256rmbkz */ + 0xfeb, /* VCVTQQ2PSZrrbkz */ +/* Table9479 */ + 0x109c, /* VCVTTPD2UDQZ256rmbkz */ + 0x10ab, /* VCVTTPD2UDQZrrbkz */ +/* Table9481 */ + 0xeb5, /* VCVTPD2UDQZ256rmbkz */ + 0xec4, /* VCVTPD2UDQZrrbkz */ +/* Table9483 */ + 0x11c5, /* VCVTUQQ2PDZ256rmbkz */ + 0x11d4, /* VCVTUQQ2PDZrrbkz */ +/* Table9485 */ + 0xfbe, /* VCVTQQ2PDZ256rmbkz */ + 0xfcd, /* VCVTQQ2PDZrrbkz */ +/* Table9487 */ + 0x11e3, /* VCVTUQQ2PSZ256rmbkz */ + 0x11f2, /* VCVTUQQ2PSZrrbkz */ +/* Table9489 */ + 0xe55, /* VCVTPD2DQZ256rmbkz */ + 0xe64, /* VCVTPD2DQZrrbkz */ +/* Table9491 */ + 0x3ade, /* VUNPCKLPDZ256rmbkz */ + 0x0, /* */ +/* Table9493 */ + 0x3aa0, /* VUNPCKHPDZ256rmbkz */ + 0x0, /* */ +/* Table9495 */ + 0x39c1, /* VSQRTPDZ256mbkz */ + 0x39d0, /* VSQRTPDZrbkz */ +/* Table9497 */ + 0xc70, /* VANDPDZ256rmbkz */ + 0x0, /* */ +/* Table9499 */ + 0xc32, /* VANDNPDZ256rmbkz */ + 0x0, /* */ +/* Table9501 */ + 0x1ff7, /* VORPDZ256rmbkz */ + 0x0, /* */ +/* Table9503 */ + 0x3b1c, /* VXORPDZ256rmbkz */ + 0x0, /* */ +/* Table9505 */ + 0xb66, /* VADDPDZ256rmbkz */ + 0xb75, /* VADDPDZrrbkz */ +/* Table9507 */ + 0x1f8f, /* VMULPDZ256rmbkz */ + 0x1f9e, /* VMULPDZrrbkz */ +/* Table9509 */ + 0xe77, /* VCVTPD2PSZ256rmbkz */ + 0xe86, /* VCVTPD2PSZrrbkz */ +/* Table9511 */ + 0x3a24, /* VSUBPDZ256rmbkz */ + 0x3a33, /* VSUBPDZrrbkz */ +/* Table9513 */ + 0x1cec, /* VMINPDZ256rmbkz */ + 0x1cfb, /* VMINPDZrrbkz */ +/* Table9515 */ + 0x1228, /* VDIVPDZ256rmbkz */ + 0x1237, /* VDIVPDZrrbkz */ +/* Table9517 */ + 0x1c41, /* VMAXPDZ256rmbkz */ + 0x1c50, /* VMAXPDZrrbkz */ +/* Table9519 */ + 0x3684, /* VPUNPCKLQDQZ256rmbkz */ + 0x0, /* */ +/* Table9521 */ + 0x361a, /* VPUNPCKHQDQZ256rmbkz */ + 0x0, /* */ +/* Table9523 */ + 0x2f90, /* VPRORQZ256mbikz */ + 0x2f24, /* VPROLQZ256mbikz */ + 0x0, /* */ + 0x0, /* */ + 0x32e9, /* VPSRAQZ256mbikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table9539 */ + 0x0, /* */ + 0x0, /* */ + 0x33ca, /* VPSRLQZ256mbikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x320c, /* VPSLLQZ256mbikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table9555 */ + 0x10ba, /* VCVTTPD2UQQZ256rmbkz */ + 0x10c9, /* VCVTTPD2UQQZrrbkz */ +/* Table9557 */ + 0xed3, /* VCVTPD2UQQZ256rmbkz */ + 0xee2, /* VCVTPD2UQQZrrbkz */ +/* Table9559 */ + 0x107e, /* VCVTTPD2QQZ256rmbkz */ + 0x108d, /* VCVTTPD2QQZrrbkz */ +/* Table9561 */ + 0xe97, /* VCVTPD2QQZ256rmbkz */ + 0xea6, /* VCVTPD2QQZrrbkz */ +/* Table9563 */ + 0x3982, /* VSHUFPDZ256rmbikz */ + 0x0, /* */ +/* Table9565 */ + 0x2140, /* VPADDQZ256rmbkz */ + 0x0, /* */ +/* Table9567 */ + 0x2236, /* VPANDQZ256rmbkz */ + 0x0, /* */ +/* Table9569 */ + 0x2217, /* VPANDNQZ256rmbkz */ + 0x0, /* */ +/* Table9571 */ + 0x105e, /* VCVTTPD2DQZ256rmbkz */ + 0x106d, /* VCVTTPD2DQZrrbkz */ +/* Table9573 */ + 0x2ee7, /* VPORQZ256rmbkz */ + 0x0, /* */ +/* Table9575 */ + 0x36d2, /* VPXORQZ256rmbkz */ + 0x0, /* */ +/* Table9577 */ + 0x2e55, /* VPMULUDQZ256rmbkz */ + 0x0, /* */ +/* Table9579 */ + 0x34a6, /* VPSUBQZ256rmbkz */ + 0x0, /* */ +/* Table9581 */ + 0x3b06, /* VUNPCKLPSZrmbkz */ + 0x0, /* */ +/* Table9583 */ + 0x3ac8, /* VUNPCKHPSZrmbkz */ + 0x0, /* */ +/* Table9585 */ + 0x39ec, /* VSQRTPSZmbkz */ + 0x39f2, /* VSQRTPSZrbkz */ +/* Table9587 */ + 0xc98, /* VANDPSZrmbkz */ + 0x0, /* */ +/* Table9589 */ + 0xc5a, /* VANDNPSZrmbkz */ + 0x0, /* */ +/* Table9591 */ + 0x201f, /* VORPSZrmbkz */ + 0x0, /* */ +/* Table9593 */ + 0x3b44, /* VXORPSZrmbkz */ + 0x0, /* */ +/* Table9595 */ + 0xb91, /* VADDPSZrmbkz */ + 0xb97, /* VADDPSZrrbkz */ +/* Table9597 */ + 0x1fba, /* VMULPSZrmbkz */ + 0x1fc0, /* VMULPSZrrbkz */ +/* Table9599 */ + 0xf37, /* VCVTPS2PDZrmbkz */ + 0xf3d, /* VCVTPS2PDZrrbkz */ +/* Table9601 */ + 0xe3c, /* VCVTDQ2PSZrmbkz */ + 0xe42, /* VCVTDQ2PSZrrbkz */ +/* Table9603 */ + 0x3a4f, /* VSUBPSZrmbkz */ + 0x3a55, /* VSUBPSZrrbkz */ +/* Table9605 */ + 0x1d17, /* VMINPSZrmbkz */ + 0x1d1d, /* VMINPSZrrbkz */ +/* Table9607 */ + 0x1253, /* VDIVPSZrmbkz */ + 0x1259, /* VDIVPSZrrbkz */ +/* Table9609 */ + 0x1c6c, /* VMAXPSZrmbkz */ + 0x1c72, /* VMAXPSZrrbkz */ +/* Table9611 */ + 0x1121, /* VCVTTPS2UDQZrmbkz */ + 0x1127, /* VCVTTPS2UDQZrrbkz */ +/* Table9613 */ + 0xf8b, /* VCVTPS2UDQZrmbkz */ + 0xf91, /* VCVTPS2UDQZrrbkz */ +/* Table9615 */ + 0x39aa, /* VSHUFPSZrmbikz */ + 0x0, /* */ +/* Table9617 */ + 0x10e3, /* VCVTTPS2DQZrmbkz */ + 0x10e9, /* VCVTTPS2DQZrrbkz */ +/* Table9619 */ + 0x1195, /* VCVTUDQ2PDZrmbkz */ + 0x0, /* */ +/* Table9621 */ + 0xe1d, /* VCVTDQ2PDZrmbkz */ + 0x0, /* */ +/* Table9623 */ + 0x11b0, /* VCVTUDQ2PSZrmbkz */ + 0x11b6, /* VCVTUDQ2PSZrrbkz */ +/* Table9625 */ + 0xf15, /* VCVTPS2DQZrmbkz */ + 0xf1b, /* VCVTPS2DQZrrbkz */ +/* Table9627 */ + 0x366e, /* VPUNPCKLDQZrmbkz */ + 0x0, /* */ +/* Table9629 */ + 0x3604, /* VPUNPCKHDQZrmbkz */ + 0x0, /* */ +/* Table9631 */ + 0x20aa, /* VPACKSSDWZrmbkz */ + 0x0, /* */ +/* Table9633 */ + 0x317c, /* VPSHUFDZmbikz */ + 0x0, /* */ +/* Table9635 */ + 0x2f7e, /* VPRORDZmbikz */ + 0x2f12, /* VPROLDZmbikz */ + 0x33a6, /* VPSRLDZmbikz */ + 0x0, /* */ + 0x32c8, /* VPSRADZmbikz */ + 0x0, /* */ + 0x31e8, /* VPSLLDZmbikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table9651 */ + 0x113f, /* VCVTTPS2UQQZrmbkz */ + 0x1145, /* VCVTTPS2UQQZrrbkz */ +/* Table9653 */ + 0xfa9, /* VCVTPS2UQQZrmbkz */ + 0xfaf, /* VCVTPS2UQQZrrbkz */ +/* Table9655 */ + 0x1103, /* VCVTTPS2QQZrmbkz */ + 0x1109, /* VCVTTPS2QQZrrbkz */ +/* Table9657 */ + 0xf6d, /* VCVTPS2QQZrmbkz */ + 0xf73, /* VCVTPS2QQZrrbkz */ +/* Table9659 */ + 0x21ea, /* VPANDDZrmbkz */ + 0x0, /* */ +/* Table9661 */ + 0x2205, /* VPANDNDZrmbkz */ + 0x0, /* */ +/* Table9663 */ + 0x2ed5, /* VPORDZrmbkz */ + 0x0, /* */ +/* Table9665 */ + 0x36c0, /* VPXORDZrmbkz */ + 0x0, /* */ +/* Table9667 */ + 0x3490, /* VPSUBDZrmbkz */ + 0x0, /* */ +/* Table9669 */ + 0x212a, /* VPADDDZrmbkz */ + 0x0, /* */ +/* Table9671 */ + 0xfe5, /* VCVTQQ2PSZrmbkz */ + 0xfeb, /* VCVTQQ2PSZrrbkz */ +/* Table9673 */ + 0x10a5, /* VCVTTPD2UDQZrmbkz */ + 0x10ab, /* VCVTTPD2UDQZrrbkz */ +/* Table9675 */ + 0xebe, /* VCVTPD2UDQZrmbkz */ + 0xec4, /* VCVTPD2UDQZrrbkz */ +/* Table9677 */ + 0x11ce, /* VCVTUQQ2PDZrmbkz */ + 0x11d4, /* VCVTUQQ2PDZrrbkz */ +/* Table9679 */ + 0xfc7, /* VCVTQQ2PDZrmbkz */ + 0xfcd, /* VCVTQQ2PDZrrbkz */ +/* Table9681 */ + 0x11ec, /* VCVTUQQ2PSZrmbkz */ + 0x11f2, /* VCVTUQQ2PSZrrbkz */ +/* Table9683 */ + 0xe5e, /* VCVTPD2DQZrmbkz */ + 0xe64, /* VCVTPD2DQZrrbkz */ +/* Table9685 */ + 0x3ae7, /* VUNPCKLPDZrmbkz */ + 0x0, /* */ +/* Table9687 */ + 0x3aa9, /* VUNPCKHPDZrmbkz */ + 0x0, /* */ +/* Table9689 */ + 0x39ca, /* VSQRTPDZmbkz */ + 0x39d0, /* VSQRTPDZrbkz */ +/* Table9691 */ + 0xc79, /* VANDPDZrmbkz */ + 0x0, /* */ +/* Table9693 */ + 0xc3b, /* VANDNPDZrmbkz */ + 0x0, /* */ +/* Table9695 */ + 0x2000, /* VORPDZrmbkz */ + 0x0, /* */ +/* Table9697 */ + 0x3b25, /* VXORPDZrmbkz */ + 0x0, /* */ +/* Table9699 */ + 0xb6f, /* VADDPDZrmbkz */ + 0xb75, /* VADDPDZrrbkz */ +/* Table9701 */ + 0x1f98, /* VMULPDZrmbkz */ + 0x1f9e, /* VMULPDZrrbkz */ +/* Table9703 */ + 0xe80, /* VCVTPD2PSZrmbkz */ + 0xe86, /* VCVTPD2PSZrrbkz */ +/* Table9705 */ + 0x3a2d, /* VSUBPDZrmbkz */ + 0x3a33, /* VSUBPDZrrbkz */ +/* Table9707 */ + 0x1cf5, /* VMINPDZrmbkz */ + 0x1cfb, /* VMINPDZrrbkz */ +/* Table9709 */ + 0x1231, /* VDIVPDZrmbkz */ + 0x1237, /* VDIVPDZrrbkz */ +/* Table9711 */ + 0x1c4a, /* VMAXPDZrmbkz */ + 0x1c50, /* VMAXPDZrrbkz */ +/* Table9713 */ + 0x368d, /* VPUNPCKLQDQZrmbkz */ + 0x0, /* */ +/* Table9715 */ + 0x3623, /* VPUNPCKHQDQZrmbkz */ + 0x0, /* */ +/* Table9717 */ + 0x2f99, /* VPRORQZmbikz */ + 0x2f2d, /* VPROLQZmbikz */ + 0x0, /* */ + 0x0, /* */ + 0x32f8, /* VPSRAQZmbikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table9733 */ + 0x0, /* */ + 0x0, /* */ + 0x33d9, /* VPSRLQZmbikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x321b, /* VPSLLQZmbikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table9749 */ + 0x10c3, /* VCVTTPD2UQQZrmbkz */ + 0x10c9, /* VCVTTPD2UQQZrrbkz */ +/* Table9751 */ + 0xedc, /* VCVTPD2UQQZrmbkz */ + 0xee2, /* VCVTPD2UQQZrrbkz */ +/* Table9753 */ + 0x1087, /* VCVTTPD2QQZrmbkz */ + 0x108d, /* VCVTTPD2QQZrrbkz */ +/* Table9755 */ + 0xea0, /* VCVTPD2QQZrmbkz */ + 0xea6, /* VCVTPD2QQZrrbkz */ +/* Table9757 */ + 0x398b, /* VSHUFPDZrmbikz */ + 0x0, /* */ +/* Table9759 */ + 0x2149, /* VPADDQZrmbkz */ + 0x0, /* */ +/* Table9761 */ + 0x223f, /* VPANDQZrmbkz */ + 0x0, /* */ +/* Table9763 */ + 0x2220, /* VPANDNQZrmbkz */ + 0x0, /* */ +/* Table9765 */ + 0x1067, /* VCVTTPD2DQZrmbkz */ + 0x106d, /* VCVTTPD2DQZrrbkz */ +/* Table9767 */ + 0x2ef0, /* VPORQZrmbkz */ + 0x0, /* */ +/* Table9769 */ + 0x36db, /* VPXORQZrmbkz */ + 0x0, /* */ +/* Table9771 */ + 0x2e5e, /* VPMULUDQZrmbkz */ + 0x0, /* */ +/* Table9773 */ + 0x34af, /* VPSUBQZrmbkz */ + 0x0, /* */ +/* Table9775 */ + 0x1f4f, /* VMOVUPSZ128rmkz */ + 0x1f54, /* VMOVUPSZ128rrkz */ +/* Table9777 */ + 0x0, /* */ + 0x1f55, /* VMOVUPSZ128rrkz_REV */ +/* Table9779 */ + 0x3af6, /* VUNPCKLPSZ128rmkz */ + 0x3af9, /* VUNPCKLPSZ128rrkz */ +/* Table9781 */ + 0x3ab8, /* VUNPCKHPSZ128rmkz */ + 0x3abb, /* VUNPCKHPSZ128rrkz */ +/* Table9783 */ + 0x1d7d, /* VMOVAPSZ128rmkz */ + 0x1d82, /* VMOVAPSZ128rrkz */ +/* Table9785 */ + 0x0, /* */ + 0x1d83, /* VMOVAPSZ128rrkz_REV */ +/* Table9787 */ + 0x39dc, /* VSQRTPSZ128mkz */ + 0x39df, /* VSQRTPSZ128rkz */ +/* Table9789 */ + 0xc88, /* VANDPSZ128rmkz */ + 0xc8b, /* VANDPSZ128rrkz */ +/* Table9791 */ + 0xc4a, /* VANDNPSZ128rmkz */ + 0xc4d, /* VANDNPSZ128rrkz */ +/* Table9793 */ + 0x200f, /* VORPSZ128rmkz */ + 0x2012, /* VORPSZ128rrkz */ +/* Table9795 */ + 0x3b34, /* VXORPSZ128rmkz */ + 0x3b37, /* VXORPSZ128rrkz */ +/* Table9797 */ + 0xb81, /* VADDPSZ128rmkz */ + 0xb84, /* VADDPSZ128rrkz */ +/* Table9799 */ + 0x1faa, /* VMULPSZ128rmkz */ + 0x1fad, /* VMULPSZ128rrkz */ +/* Table9801 */ + 0xf27, /* VCVTPS2PDZ128rmkz */ + 0xf2a, /* VCVTPS2PDZ128rrkz */ +/* Table9803 */ + 0xe2c, /* VCVTDQ2PSZ128rmkz */ + 0xe2f, /* VCVTDQ2PSZ128rrkz */ +/* Table9805 */ + 0x3a3f, /* VSUBPSZ128rmkz */ + 0x3a42, /* VSUBPSZ128rrkz */ +/* Table9807 */ + 0x1d07, /* VMINPSZ128rmkz */ + 0x1d0a, /* VMINPSZ128rrkz */ +/* Table9809 */ + 0x1243, /* VDIVPSZ128rmkz */ + 0x1246, /* VDIVPSZ128rrkz */ +/* Table9811 */ + 0x1c5c, /* VMAXPSZ128rmkz */ + 0x1c5f, /* VMAXPSZ128rrkz */ +/* Table9813 */ + 0x1111, /* VCVTTPS2UDQZ128rmkz */ + 0x1114, /* VCVTTPS2UDQZ128rrkz */ +/* Table9815 */ + 0xf7b, /* VCVTPS2UDQZ128rmkz */ + 0xf7e, /* VCVTPS2UDQZ128rrkz */ +/* Table9817 */ + 0x399b, /* VSHUFPSZ128rmikz */ + 0x399e, /* VSHUFPSZ128rrikz */ +/* Table9819 */ + 0x1f13, /* VMOVSSZrmkz */ + 0x1f18, /* VMOVSSZrrkz */ +/* Table9821 */ + 0x0, /* */ + 0x1f19, /* VMOVSSZrrkz_REV */ +/* Table9823 */ + 0x1ef9, /* VMOVSLDUPZ128rmkz */ + 0x1efc, /* VMOVSLDUPZ128rrkz */ +/* Table9825 */ + 0x1ee3, /* VMOVSHDUPZ128rmkz */ + 0x1ee6, /* VMOVSHDUPZ128rrkz */ +/* Table9827 */ + 0x3a09, /* VSQRTSSZm_Intkz */ + 0x3a0d, /* VSQRTSSZr_Intkz */ +/* Table9829 */ + 0xbae, /* VADDSSZrm_Intkz */ + 0xbb2, /* VADDSSZrr_Intkz */ +/* Table9831 */ + 0x1fd7, /* VMULSSZrm_Intkz */ + 0x1fdb, /* VMULSSZrr_Intkz */ +/* Table9833 */ + 0x1034, /* VCVTSS2SDZrm_Intkz */ + 0x1038, /* VCVTSS2SDZrr_Intkz */ +/* Table9835 */ + 0x10d3, /* VCVTTPS2DQZ128rmkz */ + 0x10d6, /* VCVTTPS2DQZ128rrkz */ +/* Table9837 */ + 0x3a6c, /* VSUBSSZrm_Intkz */ + 0x3a70, /* VSUBSSZrr_Intkz */ +/* Table9839 */ + 0x1d34, /* VMINSSZrm_Intkz */ + 0x1d38, /* VMINSSZrr_Intkz */ +/* Table9841 */ + 0x1270, /* VDIVSSZrm_Intkz */ + 0x1274, /* VDIVSSZrr_Intkz */ +/* Table9843 */ + 0x1c89, /* VMAXSSZrm_Intkz */ + 0x1c8d, /* VMAXSSZrr_Intkz */ +/* Table9845 */ + 0x1e2b, /* VMOVDQU32Z128rmkz */ + 0x1e30, /* VMOVDQU32Z128rrkz */ +/* Table9847 */ + 0x3189, /* VPSHUFHWZ128mikz */ + 0x318c, /* VPSHUFHWZ128rikz */ +/* Table9849 */ + 0x1185, /* VCVTUDQ2PDZ128rmkz */ + 0x1188, /* VCVTUDQ2PDZ128rrkz */ +/* Table9851 */ + 0x0, /* */ + 0x1e31, /* VMOVDQU32Z128rrkz_REV */ +/* Table9853 */ + 0xe0d, /* VCVTDQ2PDZ128rmkz */ + 0xe10, /* VCVTDQ2PDZ128rrkz */ +/* Table9855 */ + 0x1e6d, /* VMOVDQU8Z128rmkz */ + 0x1e72, /* VMOVDQU8Z128rrkz */ +/* Table9857 */ + 0x319f, /* VPSHUFLWZ128mikz */ + 0x31a2, /* VPSHUFLWZ128rikz */ +/* Table9859 */ + 0x11a0, /* VCVTUDQ2PSZ128rmkz */ + 0x11a3, /* VCVTUDQ2PSZ128rrkz */ +/* Table9861 */ + 0x0, /* */ + 0x1e73, /* VMOVDQU8Z128rrkz_REV */ +/* Table9863 */ + 0xf05, /* VCVTPS2DQZ128rmkz */ + 0xf08, /* VCVTPS2DQZ128rrkz */ +/* Table9865 */ + 0x3645, /* VPUNPCKLBWZ128rmkz */ + 0x3648, /* VPUNPCKLBWZ128rrkz */ +/* Table9867 */ + 0x3699, /* VPUNPCKLWDZ128rmkz */ + 0x369c, /* VPUNPCKLWDZ128rrkz */ +/* Table9869 */ + 0x365e, /* VPUNPCKLDQZ128rmkz */ + 0x3661, /* VPUNPCKLDQZ128rrkz */ +/* Table9871 */ + 0x20b6, /* VPACKSSWBZ128rmkz */ + 0x20b9, /* VPACKSSWBZ128rrkz */ +/* Table9873 */ + 0x20eb, /* VPACKUSWBZ128rmkz */ + 0x20ee, /* VPACKUSWBZ128rrkz */ +/* Table9875 */ + 0x35db, /* VPUNPCKHBWZ128rmkz */ + 0x35de, /* VPUNPCKHBWZ128rrkz */ +/* Table9877 */ + 0x362f, /* VPUNPCKHWDZ128rmkz */ + 0x3632, /* VPUNPCKHWDZ128rrkz */ +/* Table9879 */ + 0x35f4, /* VPUNPCKHDQZ128rmkz */ + 0x35f7, /* VPUNPCKHDQZ128rrkz */ +/* Table9881 */ + 0x209a, /* VPACKSSDWZ128rmkz */ + 0x209d, /* VPACKSSDWZ128rrkz */ +/* Table9883 */ + 0x1dc0, /* VMOVDQA32Z128rmkz */ + 0x1dc5, /* VMOVDQA32Z128rrkz */ +/* Table9885 */ + 0x316d, /* VPSHUFDZ128mikz */ + 0x3170, /* VPSHUFDZ128rikz */ +/* Table9887 */ + 0x0, /* */ + 0x0, /* */ + 0x343e, /* VPSRLWZ128mikz */ + 0x0, /* */ + 0x3356, /* VPSRAWZ128mikz */ + 0x0, /* */ + 0x3280, /* VPSLLWZ128mikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3441, /* VPSRLWZ128rikz */ + 0x0, /* */ + 0x3359, /* VPSRAWZ128rikz */ + 0x0, /* */ + 0x3283, /* VPSLLWZ128rikz */ + 0x0, /* */ +/* Table9903 */ + 0x2f6f, /* VPRORDZ128mikz */ + 0x2f03, /* VPROLDZ128mikz */ + 0x338b, /* VPSRLDZ128mikz */ + 0x0, /* */ + 0x32ad, /* VPSRADZ128mikz */ + 0x0, /* */ + 0x31cd, /* VPSLLDZ128mikz */ + 0x0, /* */ + 0x2f72, /* VPRORDZ128rikz */ + 0x2f06, /* VPROLDZ128rikz */ + 0x338e, /* VPSRLDZ128rikz */ + 0x0, /* */ + 0x32b0, /* VPSRADZ128rikz */ + 0x0, /* */ + 0x31d0, /* VPSLLDZ128rikz */ + 0x0, /* */ +/* Table9919 */ + 0x112f, /* VCVTTPS2UQQZ128rmkz */ + 0x1132, /* VCVTTPS2UQQZ128rrkz */ +/* Table9921 */ + 0xf99, /* VCVTPS2UQQZ128rmkz */ + 0xf9c, /* VCVTPS2UQQZ128rrkz */ +/* Table9923 */ + 0x10f3, /* VCVTTPS2QQZ128rmkz */ + 0x10f6, /* VCVTTPS2QQZ128rrkz */ +/* Table9925 */ + 0xf5d, /* VCVTPS2QQZ128rmkz */ + 0xf60, /* VCVTPS2QQZ128rrkz */ +/* Table9927 */ + 0x0, /* */ + 0x1dc6, /* VMOVDQA32Z128rrkz_REV */ +/* Table9929 */ + 0x3444, /* VPSRLWZ128rmkz */ + 0x3447, /* VPSRLWZ128rrkz */ +/* Table9931 */ + 0x3391, /* VPSRLDZ128rmkz */ + 0x3394, /* VPSRLDZ128rrkz */ +/* Table9933 */ + 0x2e1a, /* VPMULLWZ128rmkz */ + 0x2e1d, /* VPMULLWZ128rrkz */ +/* Table9935 */ + 0x34e7, /* VPSUBUSBZ128rmkz */ + 0x34ea, /* VPSUBUSBZ128rrkz */ +/* Table9937 */ + 0x34fd, /* VPSUBUSWZ128rmkz */ + 0x3500, /* VPSUBUSWZ128rrkz */ +/* Table9939 */ + 0x2ae9, /* VPMINUBZ128rmkz */ + 0x2aec, /* VPMINUBZ128rrkz */ +/* Table9941 */ + 0x21da, /* VPANDDZ128rmkz */ + 0x21dd, /* VPANDDZ128rrkz */ +/* Table9943 */ + 0x2181, /* VPADDUSBZ128rmkz */ + 0x2184, /* VPADDUSBZ128rrkz */ +/* Table9945 */ + 0x2197, /* VPADDUSWZ128rmkz */ + 0x219a, /* VPADDUSWZ128rrkz */ +/* Table9947 */ + 0x2a1d, /* VPMAXUBZ128rmkz */ + 0x2a20, /* VPMAXUBZ128rrkz */ +/* Table9949 */ + 0x21f5, /* VPANDNDZ128rmkz */ + 0x21f8, /* VPANDNDZ128rrkz */ +/* Table9951 */ + 0x224d, /* VPAVGBZ128rmkz */ + 0x2250, /* VPAVGBZ128rrkz */ +/* Table9953 */ + 0x335c, /* VPSRAWZ128rmkz */ + 0x335f, /* VPSRAWZ128rrkz */ +/* Table9955 */ + 0x32b3, /* VPSRADZ128rmkz */ + 0x32b6, /* VPSRADZ128rrkz */ +/* Table9957 */ + 0x2263, /* VPAVGWZ128rmkz */ + 0x2266, /* VPAVGWZ128rrkz */ +/* Table9959 */ + 0x2db4, /* VPMULHUWZ128rmkz */ + 0x2db7, /* VPMULHUWZ128rrkz */ +/* Table9961 */ + 0x2dca, /* VPMULHWZ128rmkz */ + 0x2dcd, /* VPMULHWZ128rrkz */ +/* Table9963 */ + 0x34bb, /* VPSUBSBZ128rmkz */ + 0x34be, /* VPSUBSBZ128rrkz */ +/* Table9965 */ + 0x34d1, /* VPSUBSWZ128rmkz */ + 0x34d4, /* VPSUBSWZ128rrkz */ +/* Table9967 */ + 0x2ad3, /* VPMINSWZ128rmkz */ + 0x2ad6, /* VPMINSWZ128rrkz */ +/* Table9969 */ + 0x2ec5, /* VPORDZ128rmkz */ + 0x2ec8, /* VPORDZ128rrkz */ +/* Table9971 */ + 0x2155, /* VPADDSBZ128rmkz */ + 0x2158, /* VPADDSBZ128rrkz */ +/* Table9973 */ + 0x216b, /* VPADDSWZ128rmkz */ + 0x216e, /* VPADDSWZ128rrkz */ +/* Table9975 */ + 0x2a07, /* VPMAXSWZ128rmkz */ + 0x2a0a, /* VPMAXSWZ128rrkz */ +/* Table9977 */ + 0x36b0, /* VPXORDZ128rmkz */ + 0x36b3, /* VPXORDZ128rrkz */ +/* Table9979 */ + 0x3286, /* VPSLLWZ128rmkz */ + 0x3289, /* VPSLLWZ128rrkz */ +/* Table9981 */ + 0x31d3, /* VPSLLDZ128rmkz */ + 0x31d6, /* VPSLLDZ128rrkz */ +/* Table9983 */ + 0x2999, /* VPMADDWDZ128rmkz */ + 0x299c, /* VPMADDWDZ128rrkz */ +/* Table9985 */ + 0x3467, /* VPSUBBZ128rmkz */ + 0x346a, /* VPSUBBZ128rrkz */ +/* Table9987 */ + 0x3513, /* VPSUBWZ128rmkz */ + 0x3516, /* VPSUBWZ128rrkz */ +/* Table9989 */ + 0x3480, /* VPSUBDZ128rmkz */ + 0x3483, /* VPSUBDZ128rrkz */ +/* Table9991 */ + 0x2101, /* VPADDBZ128rmkz */ + 0x2104, /* VPADDBZ128rrkz */ +/* Table9993 */ + 0x21ad, /* VPADDWZ128rmkz */ + 0x21b0, /* VPADDWZ128rrkz */ +/* Table9995 */ + 0x211a, /* VPADDDZ128rmkz */ + 0x211d, /* VPADDDZ128rrkz */ +/* Table9997 */ + 0xfd5, /* VCVTQQ2PSZ128rmkz */ + 0xfd8, /* VCVTQQ2PSZ128rrkz */ +/* Table9999 */ + 0x1095, /* VCVTTPD2UDQZ128rmkz */ + 0x1098, /* VCVTTPD2UDQZ128rrkz */ +/* Table10001 */ + 0xeae, /* VCVTPD2UDQZ128rmkz */ + 0xeb1, /* VCVTPD2UDQZ128rrkz */ +/* Table10003 */ + 0x1e4c, /* VMOVDQU64Z128rmkz */ + 0x1e51, /* VMOVDQU64Z128rrkz */ +/* Table10005 */ + 0x11be, /* VCVTUQQ2PDZ128rmkz */ + 0x11c1, /* VCVTUQQ2PDZ128rrkz */ +/* Table10007 */ + 0x0, /* */ + 0x1e52, /* VMOVDQU64Z128rrkz_REV */ +/* Table10009 */ + 0xfb7, /* VCVTQQ2PDZ128rmkz */ + 0xfba, /* VCVTQQ2PDZ128rrkz */ +/* Table10011 */ + 0x1ed0, /* VMOVSDZrmkz */ + 0x1ed5, /* VMOVSDZrrkz */ +/* Table10013 */ + 0x0, /* */ + 0x1ed6, /* VMOVSDZrrkz_REV */ +/* Table10015 */ + 0x1da2, /* VMOVDDUPZ128rmkz */ + 0x1da5, /* VMOVDDUPZ128rrkz */ +/* Table10017 */ + 0x39fa, /* VSQRTSDZm_Intkz */ + 0x39fe, /* VSQRTSDZr_Intkz */ +/* Table10019 */ + 0xb9f, /* VADDSDZrm_Intkz */ + 0xba3, /* VADDSDZrr_Intkz */ +/* Table10021 */ + 0x1fc8, /* VMULSDZrm_Intkz */ + 0x1fcc, /* VMULSDZrr_Intkz */ +/* Table10023 */ + 0xffb, /* VCVTSD2SSZrm_Intkz */ + 0xfff, /* VCVTSD2SSZrr_Intkz */ +/* Table10025 */ + 0x3a5d, /* VSUBSDZrm_Intkz */ + 0x3a61, /* VSUBSDZrr_Intkz */ +/* Table10027 */ + 0x1d25, /* VMINSDZrm_Intkz */ + 0x1d29, /* VMINSDZrr_Intkz */ +/* Table10029 */ + 0x1261, /* VDIVSDZrm_Intkz */ + 0x1265, /* VDIVSDZrr_Intkz */ +/* Table10031 */ + 0x1c7a, /* VMAXSDZrm_Intkz */ + 0x1c7e, /* VMAXSDZrr_Intkz */ +/* Table10033 */ + 0x1e0a, /* VMOVDQU16Z128rmkz */ + 0x1e0f, /* VMOVDQU16Z128rrkz */ +/* Table10035 */ + 0x11dc, /* VCVTUQQ2PSZ128rmkz */ + 0x11df, /* VCVTUQQ2PSZ128rrkz */ +/* Table10037 */ + 0x0, /* */ + 0x1e10, /* VMOVDQU16Z128rrkz_REV */ +/* Table10039 */ + 0xe4e, /* VCVTPD2DQZ128rmkz */ + 0xe51, /* VCVTPD2DQZ128rrkz */ +/* Table10041 */ + 0x1f26, /* VMOVUPDZ128rmkz */ + 0x1f2b, /* VMOVUPDZ128rrkz */ +/* Table10043 */ + 0x0, /* */ + 0x1f2c, /* VMOVUPDZ128rrkz_REV */ +/* Table10045 */ + 0x3ad7, /* VUNPCKLPDZ128rmkz */ + 0x3ada, /* VUNPCKLPDZ128rrkz */ +/* Table10047 */ + 0x3a99, /* VUNPCKHPDZ128rmkz */ + 0x3a9c, /* VUNPCKHPDZ128rrkz */ +/* Table10049 */ + 0x1d54, /* VMOVAPDZ128rmkz */ + 0x1d59, /* VMOVAPDZ128rrkz */ +/* Table10051 */ + 0x0, /* */ + 0x1d5a, /* VMOVAPDZ128rrkz_REV */ +/* Table10053 */ + 0x39ba, /* VSQRTPDZ128mkz */ + 0x39bd, /* VSQRTPDZ128rkz */ +/* Table10055 */ + 0xc69, /* VANDPDZ128rmkz */ + 0xc6c, /* VANDPDZ128rrkz */ +/* Table10057 */ + 0xc2b, /* VANDNPDZ128rmkz */ + 0xc2e, /* VANDNPDZ128rrkz */ +/* Table10059 */ + 0x1ff0, /* VORPDZ128rmkz */ + 0x1ff3, /* VORPDZ128rrkz */ +/* Table10061 */ + 0x3b15, /* VXORPDZ128rmkz */ + 0x3b18, /* VXORPDZ128rrkz */ +/* Table10063 */ + 0xb5f, /* VADDPDZ128rmkz */ + 0xb62, /* VADDPDZ128rrkz */ +/* Table10065 */ + 0x1f88, /* VMULPDZ128rmkz */ + 0x1f8b, /* VMULPDZ128rrkz */ +/* Table10067 */ + 0xe70, /* VCVTPD2PSZ128rmkz */ + 0xe73, /* VCVTPD2PSZ128rrkz */ +/* Table10069 */ + 0x3a1d, /* VSUBPDZ128rmkz */ + 0x3a20, /* VSUBPDZ128rrkz */ +/* Table10071 */ + 0x1ce5, /* VMINPDZ128rmkz */ + 0x1ce8, /* VMINPDZ128rrkz */ +/* Table10073 */ + 0x1221, /* VDIVPDZ128rmkz */ + 0x1224, /* VDIVPDZ128rrkz */ +/* Table10075 */ + 0x1c3a, /* VMAXPDZ128rmkz */ + 0x1c3d, /* VMAXPDZ128rrkz */ +/* Table10077 */ + 0x367d, /* VPUNPCKLQDQZ128rmkz */ + 0x3680, /* VPUNPCKLQDQZ128rrkz */ +/* Table10079 */ + 0x3613, /* VPUNPCKHQDQZ128rmkz */ + 0x3616, /* VPUNPCKHQDQZ128rrkz */ +/* Table10081 */ + 0x1de1, /* VMOVDQA64Z128rmkz */ + 0x1de6, /* VMOVDQA64Z128rrkz */ +/* Table10083 */ + 0x2f8a, /* VPRORQZ128mikz */ + 0x2f1e, /* VPROLQZ128mikz */ + 0x0, /* */ + 0x0, /* */ + 0x32dd, /* VPSRAQZ128mikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x2f8d, /* VPRORQZ128rikz */ + 0x2f21, /* VPROLQZ128rikz */ + 0x0, /* */ + 0x0, /* */ + 0x32e0, /* VPSRAQZ128rikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table10099 */ + 0x0, /* */ + 0x0, /* */ + 0x33be, /* VPSRLQZ128mikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3200, /* VPSLLQZ128mikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x33c1, /* VPSRLQZ128rikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3203, /* VPSLLQZ128rikz */ + 0x0, /* */ +/* Table10115 */ + 0x10b3, /* VCVTTPD2UQQZ128rmkz */ + 0x10b6, /* VCVTTPD2UQQZ128rrkz */ +/* Table10117 */ + 0xecc, /* VCVTPD2UQQZ128rmkz */ + 0xecf, /* VCVTPD2UQQZ128rrkz */ +/* Table10119 */ + 0x1077, /* VCVTTPD2QQZ128rmkz */ + 0x107a, /* VCVTTPD2QQZ128rrkz */ +/* Table10121 */ + 0xe90, /* VCVTPD2QQZ128rmkz */ + 0xe93, /* VCVTPD2QQZ128rrkz */ +/* Table10123 */ + 0x0, /* */ + 0x1de7, /* VMOVDQA64Z128rrkz_REV */ +/* Table10125 */ + 0x397c, /* VSHUFPDZ128rmikz */ + 0x397f, /* VSHUFPDZ128rrikz */ +/* Table10127 */ + 0x33c4, /* VPSRLQZ128rmkz */ + 0x33c7, /* VPSRLQZ128rrkz */ +/* Table10129 */ + 0x2139, /* VPADDQZ128rmkz */ + 0x213c, /* VPADDQZ128rrkz */ +/* Table10131 */ + 0x222f, /* VPANDQZ128rmkz */ + 0x2232, /* VPANDQZ128rrkz */ +/* Table10133 */ + 0x2210, /* VPANDNQZ128rmkz */ + 0x2213, /* VPANDNQZ128rrkz */ +/* Table10135 */ + 0x32e3, /* VPSRAQZ128rmkz */ + 0x32e6, /* VPSRAQZ128rrkz */ +/* Table10137 */ + 0x1057, /* VCVTTPD2DQZ128rmkz */ + 0x105a, /* VCVTTPD2DQZ128rrkz */ +/* Table10139 */ + 0x2ee0, /* VPORQZ128rmkz */ + 0x2ee3, /* VPORQZ128rrkz */ +/* Table10141 */ + 0x36cb, /* VPXORQZ128rmkz */ + 0x36ce, /* VPXORQZ128rrkz */ +/* Table10143 */ + 0x3206, /* VPSLLQZ128rmkz */ + 0x3209, /* VPSLLQZ128rrkz */ +/* Table10145 */ + 0x2e4e, /* VPMULUDQZ128rmkz */ + 0x2e51, /* VPMULUDQZ128rrkz */ +/* Table10147 */ + 0x349f, /* VPSUBQZ128rmkz */ + 0x34a2, /* VPSUBQZ128rrkz */ +/* Table10149 */ + 0x1f5a, /* VMOVUPSZ256rmkz */ + 0x1f5f, /* VMOVUPSZ256rrkz */ +/* Table10151 */ + 0x0, /* */ + 0x1f60, /* VMOVUPSZ256rrkz_REV */ +/* Table10153 */ + 0x3aff, /* VUNPCKLPSZ256rmkz */ + 0x3b02, /* VUNPCKLPSZ256rrkz */ +/* Table10155 */ + 0x3ac1, /* VUNPCKHPSZ256rmkz */ + 0x3ac4, /* VUNPCKHPSZ256rrkz */ +/* Table10157 */ + 0x1d88, /* VMOVAPSZ256rmkz */ + 0x1d8d, /* VMOVAPSZ256rrkz */ +/* Table10159 */ + 0x0, /* */ + 0x1d8e, /* VMOVAPSZ256rrkz_REV */ +/* Table10161 */ + 0x39e5, /* VSQRTPSZ256mkz */ + 0x39e8, /* VSQRTPSZ256rkz */ +/* Table10163 */ + 0xc91, /* VANDPSZ256rmkz */ + 0xc94, /* VANDPSZ256rrkz */ +/* Table10165 */ + 0xc53, /* VANDNPSZ256rmkz */ + 0xc56, /* VANDNPSZ256rrkz */ +/* Table10167 */ + 0x2018, /* VORPSZ256rmkz */ + 0x201b, /* VORPSZ256rrkz */ +/* Table10169 */ + 0x3b3d, /* VXORPSZ256rmkz */ + 0x3b40, /* VXORPSZ256rrkz */ +/* Table10171 */ + 0xb8a, /* VADDPSZ256rmkz */ + 0xb8d, /* VADDPSZ256rrkz */ +/* Table10173 */ + 0x1fb3, /* VMULPSZ256rmkz */ + 0x1fb6, /* VMULPSZ256rrkz */ +/* Table10175 */ + 0xf30, /* VCVTPS2PDZ256rmkz */ + 0xf33, /* VCVTPS2PDZ256rrkz */ +/* Table10177 */ + 0xe35, /* VCVTDQ2PSZ256rmkz */ + 0xe38, /* VCVTDQ2PSZ256rrkz */ +/* Table10179 */ + 0x3a48, /* VSUBPSZ256rmkz */ + 0x3a4b, /* VSUBPSZ256rrkz */ +/* Table10181 */ + 0x1d10, /* VMINPSZ256rmkz */ + 0x1d13, /* VMINPSZ256rrkz */ +/* Table10183 */ + 0x124c, /* VDIVPSZ256rmkz */ + 0x124f, /* VDIVPSZ256rrkz */ +/* Table10185 */ + 0x1c65, /* VMAXPSZ256rmkz */ + 0x1c68, /* VMAXPSZ256rrkz */ +/* Table10187 */ + 0x111a, /* VCVTTPS2UDQZ256rmkz */ + 0x111d, /* VCVTTPS2UDQZ256rrkz */ +/* Table10189 */ + 0xf84, /* VCVTPS2UDQZ256rmkz */ + 0xf87, /* VCVTPS2UDQZ256rrkz */ +/* Table10191 */ + 0x39a4, /* VSHUFPSZ256rmikz */ + 0x39a7, /* VSHUFPSZ256rrikz */ +/* Table10193 */ + 0x1eff, /* VMOVSLDUPZ256rmkz */ + 0x1f02, /* VMOVSLDUPZ256rrkz */ +/* Table10195 */ + 0x1ee9, /* VMOVSHDUPZ256rmkz */ + 0x1eec, /* VMOVSHDUPZ256rrkz */ +/* Table10197 */ + 0x10dc, /* VCVTTPS2DQZ256rmkz */ + 0x10df, /* VCVTTPS2DQZ256rrkz */ +/* Table10199 */ + 0x1e36, /* VMOVDQU32Z256rmkz */ + 0x1e3b, /* VMOVDQU32Z256rrkz */ +/* Table10201 */ + 0x318f, /* VPSHUFHWZ256mikz */ + 0x3192, /* VPSHUFHWZ256rikz */ +/* Table10203 */ + 0x118e, /* VCVTUDQ2PDZ256rmkz */ + 0x1191, /* VCVTUDQ2PDZ256rrkz */ +/* Table10205 */ + 0x0, /* */ + 0x1e3c, /* VMOVDQU32Z256rrkz_REV */ +/* Table10207 */ + 0xe16, /* VCVTDQ2PDZ256rmkz */ + 0xe19, /* VCVTDQ2PDZ256rrkz */ +/* Table10209 */ + 0x1e78, /* VMOVDQU8Z256rmkz */ + 0x1e7d, /* VMOVDQU8Z256rrkz */ +/* Table10211 */ + 0x31a5, /* VPSHUFLWZ256mikz */ + 0x31a8, /* VPSHUFLWZ256rikz */ +/* Table10213 */ + 0x11a9, /* VCVTUDQ2PSZ256rmkz */ + 0x11ac, /* VCVTUDQ2PSZ256rrkz */ +/* Table10215 */ + 0x0, /* */ + 0x1e7e, /* VMOVDQU8Z256rrkz_REV */ +/* Table10217 */ + 0xf0e, /* VCVTPS2DQZ256rmkz */ + 0xf11, /* VCVTPS2DQZ256rrkz */ +/* Table10219 */ + 0x364b, /* VPUNPCKLBWZ256rmkz */ + 0x364e, /* VPUNPCKLBWZ256rrkz */ +/* Table10221 */ + 0x369f, /* VPUNPCKLWDZ256rmkz */ + 0x36a2, /* VPUNPCKLWDZ256rrkz */ +/* Table10223 */ + 0x3667, /* VPUNPCKLDQZ256rmkz */ + 0x366a, /* VPUNPCKLDQZ256rrkz */ +/* Table10225 */ + 0x20bc, /* VPACKSSWBZ256rmkz */ + 0x20bf, /* VPACKSSWBZ256rrkz */ +/* Table10227 */ + 0x20f1, /* VPACKUSWBZ256rmkz */ + 0x20f4, /* VPACKUSWBZ256rrkz */ +/* Table10229 */ + 0x35e1, /* VPUNPCKHBWZ256rmkz */ + 0x35e4, /* VPUNPCKHBWZ256rrkz */ +/* Table10231 */ + 0x3635, /* VPUNPCKHWDZ256rmkz */ + 0x3638, /* VPUNPCKHWDZ256rrkz */ +/* Table10233 */ + 0x35fd, /* VPUNPCKHDQZ256rmkz */ + 0x3600, /* VPUNPCKHDQZ256rrkz */ +/* Table10235 */ + 0x20a3, /* VPACKSSDWZ256rmkz */ + 0x20a6, /* VPACKSSDWZ256rrkz */ +/* Table10237 */ + 0x1dcb, /* VMOVDQA32Z256rmkz */ + 0x1dd0, /* VMOVDQA32Z256rrkz */ +/* Table10239 */ + 0x3176, /* VPSHUFDZ256mikz */ + 0x3179, /* VPSHUFDZ256rikz */ +/* Table10241 */ + 0x0, /* */ + 0x0, /* */ + 0x344a, /* VPSRLWZ256mikz */ + 0x0, /* */ + 0x3362, /* VPSRAWZ256mikz */ + 0x0, /* */ + 0x328c, /* VPSLLWZ256mikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x344d, /* VPSRLWZ256rikz */ + 0x0, /* */ + 0x3365, /* VPSRAWZ256rikz */ + 0x0, /* */ + 0x328f, /* VPSLLWZ256rikz */ + 0x0, /* */ +/* Table10257 */ + 0x2f78, /* VPRORDZ256mikz */ + 0x2f0c, /* VPROLDZ256mikz */ + 0x339a, /* VPSRLDZ256mikz */ + 0x0, /* */ + 0x32bc, /* VPSRADZ256mikz */ + 0x0, /* */ + 0x31dc, /* VPSLLDZ256mikz */ + 0x0, /* */ + 0x2f7b, /* VPRORDZ256rikz */ + 0x2f0f, /* VPROLDZ256rikz */ + 0x339d, /* VPSRLDZ256rikz */ + 0x0, /* */ + 0x32bf, /* VPSRADZ256rikz */ + 0x0, /* */ + 0x31df, /* VPSLLDZ256rikz */ + 0x0, /* */ +/* Table10273 */ + 0x1138, /* VCVTTPS2UQQZ256rmkz */ + 0x113b, /* VCVTTPS2UQQZ256rrkz */ +/* Table10275 */ + 0xfa2, /* VCVTPS2UQQZ256rmkz */ + 0xfa5, /* VCVTPS2UQQZ256rrkz */ +/* Table10277 */ + 0x10fc, /* VCVTTPS2QQZ256rmkz */ + 0x10ff, /* VCVTTPS2QQZ256rrkz */ +/* Table10279 */ + 0xf66, /* VCVTPS2QQZ256rmkz */ + 0xf69, /* VCVTPS2QQZ256rrkz */ +/* Table10281 */ + 0x0, /* */ + 0x1dd1, /* VMOVDQA32Z256rrkz_REV */ +/* Table10283 */ + 0x3450, /* VPSRLWZ256rmkz */ + 0x3453, /* VPSRLWZ256rrkz */ +/* Table10285 */ + 0x33a0, /* VPSRLDZ256rmkz */ + 0x33a3, /* VPSRLDZ256rrkz */ +/* Table10287 */ + 0x2e20, /* VPMULLWZ256rmkz */ + 0x2e23, /* VPMULLWZ256rrkz */ +/* Table10289 */ + 0x34ed, /* VPSUBUSBZ256rmkz */ + 0x34f0, /* VPSUBUSBZ256rrkz */ +/* Table10291 */ + 0x3503, /* VPSUBUSWZ256rmkz */ + 0x3506, /* VPSUBUSWZ256rrkz */ +/* Table10293 */ + 0x2aef, /* VPMINUBZ256rmkz */ + 0x2af2, /* VPMINUBZ256rrkz */ +/* Table10295 */ + 0x21e3, /* VPANDDZ256rmkz */ + 0x21e6, /* VPANDDZ256rrkz */ +/* Table10297 */ + 0x2187, /* VPADDUSBZ256rmkz */ + 0x218a, /* VPADDUSBZ256rrkz */ +/* Table10299 */ + 0x219d, /* VPADDUSWZ256rmkz */ + 0x21a0, /* VPADDUSWZ256rrkz */ +/* Table10301 */ + 0x2a23, /* VPMAXUBZ256rmkz */ + 0x2a26, /* VPMAXUBZ256rrkz */ +/* Table10303 */ + 0x21fe, /* VPANDNDZ256rmkz */ + 0x2201, /* VPANDNDZ256rrkz */ +/* Table10305 */ + 0x2253, /* VPAVGBZ256rmkz */ + 0x2256, /* VPAVGBZ256rrkz */ +/* Table10307 */ + 0x3368, /* VPSRAWZ256rmkz */ + 0x336b, /* VPSRAWZ256rrkz */ +/* Table10309 */ + 0x32c2, /* VPSRADZ256rmkz */ + 0x32c5, /* VPSRADZ256rrkz */ +/* Table10311 */ + 0x2269, /* VPAVGWZ256rmkz */ + 0x226c, /* VPAVGWZ256rrkz */ +/* Table10313 */ + 0x2dba, /* VPMULHUWZ256rmkz */ + 0x2dbd, /* VPMULHUWZ256rrkz */ +/* Table10315 */ + 0x2dd0, /* VPMULHWZ256rmkz */ + 0x2dd3, /* VPMULHWZ256rrkz */ +/* Table10317 */ + 0x34c1, /* VPSUBSBZ256rmkz */ + 0x34c4, /* VPSUBSBZ256rrkz */ +/* Table10319 */ + 0x34d7, /* VPSUBSWZ256rmkz */ + 0x34da, /* VPSUBSWZ256rrkz */ +/* Table10321 */ + 0x2ad9, /* VPMINSWZ256rmkz */ + 0x2adc, /* VPMINSWZ256rrkz */ +/* Table10323 */ + 0x2ece, /* VPORDZ256rmkz */ + 0x2ed1, /* VPORDZ256rrkz */ +/* Table10325 */ + 0x215b, /* VPADDSBZ256rmkz */ + 0x215e, /* VPADDSBZ256rrkz */ +/* Table10327 */ + 0x2171, /* VPADDSWZ256rmkz */ + 0x2174, /* VPADDSWZ256rrkz */ +/* Table10329 */ + 0x2a0d, /* VPMAXSWZ256rmkz */ + 0x2a10, /* VPMAXSWZ256rrkz */ +/* Table10331 */ + 0x36b9, /* VPXORDZ256rmkz */ + 0x36bc, /* VPXORDZ256rrkz */ +/* Table10333 */ + 0x3292, /* VPSLLWZ256rmkz */ + 0x3295, /* VPSLLWZ256rrkz */ +/* Table10335 */ + 0x31e2, /* VPSLLDZ256rmkz */ + 0x31e5, /* VPSLLDZ256rrkz */ +/* Table10337 */ + 0x299f, /* VPMADDWDZ256rmkz */ + 0x29a2, /* VPMADDWDZ256rrkz */ +/* Table10339 */ + 0x346d, /* VPSUBBZ256rmkz */ + 0x3470, /* VPSUBBZ256rrkz */ +/* Table10341 */ + 0x3519, /* VPSUBWZ256rmkz */ + 0x351c, /* VPSUBWZ256rrkz */ +/* Table10343 */ + 0x3489, /* VPSUBDZ256rmkz */ + 0x348c, /* VPSUBDZ256rrkz */ +/* Table10345 */ + 0x2107, /* VPADDBZ256rmkz */ + 0x210a, /* VPADDBZ256rrkz */ +/* Table10347 */ + 0x21b3, /* VPADDWZ256rmkz */ + 0x21b6, /* VPADDWZ256rrkz */ +/* Table10349 */ + 0x2123, /* VPADDDZ256rmkz */ + 0x2126, /* VPADDDZ256rrkz */ +/* Table10351 */ + 0xfde, /* VCVTQQ2PSZ256rmkz */ + 0xfe1, /* VCVTQQ2PSZ256rrkz */ +/* Table10353 */ + 0x109e, /* VCVTTPD2UDQZ256rmkz */ + 0x10a1, /* VCVTTPD2UDQZ256rrkz */ +/* Table10355 */ + 0xeb7, /* VCVTPD2UDQZ256rmkz */ + 0xeba, /* VCVTPD2UDQZ256rrkz */ +/* Table10357 */ + 0x1e57, /* VMOVDQU64Z256rmkz */ + 0x1e5c, /* VMOVDQU64Z256rrkz */ +/* Table10359 */ + 0x11c7, /* VCVTUQQ2PDZ256rmkz */ + 0x11ca, /* VCVTUQQ2PDZ256rrkz */ +/* Table10361 */ + 0x0, /* */ + 0x1e5d, /* VMOVDQU64Z256rrkz_REV */ +/* Table10363 */ + 0xfc0, /* VCVTQQ2PDZ256rmkz */ + 0xfc3, /* VCVTQQ2PDZ256rrkz */ +/* Table10365 */ + 0x1da8, /* VMOVDDUPZ256rmkz */ + 0x1dab, /* VMOVDDUPZ256rrkz */ +/* Table10367 */ + 0x1e15, /* VMOVDQU16Z256rmkz */ + 0x1e1a, /* VMOVDQU16Z256rrkz */ +/* Table10369 */ + 0x11e5, /* VCVTUQQ2PSZ256rmkz */ + 0x11e8, /* VCVTUQQ2PSZ256rrkz */ +/* Table10371 */ + 0x0, /* */ + 0x1e1b, /* VMOVDQU16Z256rrkz_REV */ +/* Table10373 */ + 0xe57, /* VCVTPD2DQZ256rmkz */ + 0xe5a, /* VCVTPD2DQZ256rrkz */ +/* Table10375 */ + 0x1f31, /* VMOVUPDZ256rmkz */ + 0x1f36, /* VMOVUPDZ256rrkz */ +/* Table10377 */ + 0x0, /* */ + 0x1f37, /* VMOVUPDZ256rrkz_REV */ +/* Table10379 */ + 0x3ae0, /* VUNPCKLPDZ256rmkz */ + 0x3ae3, /* VUNPCKLPDZ256rrkz */ +/* Table10381 */ + 0x3aa2, /* VUNPCKHPDZ256rmkz */ + 0x3aa5, /* VUNPCKHPDZ256rrkz */ +/* Table10383 */ + 0x1d5f, /* VMOVAPDZ256rmkz */ + 0x1d64, /* VMOVAPDZ256rrkz */ +/* Table10385 */ + 0x0, /* */ + 0x1d65, /* VMOVAPDZ256rrkz_REV */ +/* Table10387 */ + 0x39c3, /* VSQRTPDZ256mkz */ + 0x39c6, /* VSQRTPDZ256rkz */ +/* Table10389 */ + 0xc72, /* VANDPDZ256rmkz */ + 0xc75, /* VANDPDZ256rrkz */ +/* Table10391 */ + 0xc34, /* VANDNPDZ256rmkz */ + 0xc37, /* VANDNPDZ256rrkz */ +/* Table10393 */ + 0x1ff9, /* VORPDZ256rmkz */ + 0x1ffc, /* VORPDZ256rrkz */ +/* Table10395 */ + 0x3b1e, /* VXORPDZ256rmkz */ + 0x3b21, /* VXORPDZ256rrkz */ +/* Table10397 */ + 0xb68, /* VADDPDZ256rmkz */ + 0xb6b, /* VADDPDZ256rrkz */ +/* Table10399 */ + 0x1f91, /* VMULPDZ256rmkz */ + 0x1f94, /* VMULPDZ256rrkz */ +/* Table10401 */ + 0xe79, /* VCVTPD2PSZ256rmkz */ + 0xe7c, /* VCVTPD2PSZ256rrkz */ +/* Table10403 */ + 0x3a26, /* VSUBPDZ256rmkz */ + 0x3a29, /* VSUBPDZ256rrkz */ +/* Table10405 */ + 0x1cee, /* VMINPDZ256rmkz */ + 0x1cf1, /* VMINPDZ256rrkz */ +/* Table10407 */ + 0x122a, /* VDIVPDZ256rmkz */ + 0x122d, /* VDIVPDZ256rrkz */ +/* Table10409 */ + 0x1c43, /* VMAXPDZ256rmkz */ + 0x1c46, /* VMAXPDZ256rrkz */ +/* Table10411 */ + 0x3686, /* VPUNPCKLQDQZ256rmkz */ + 0x3689, /* VPUNPCKLQDQZ256rrkz */ +/* Table10413 */ + 0x361c, /* VPUNPCKHQDQZ256rmkz */ + 0x361f, /* VPUNPCKHQDQZ256rrkz */ +/* Table10415 */ + 0x1dec, /* VMOVDQA64Z256rmkz */ + 0x1df1, /* VMOVDQA64Z256rrkz */ +/* Table10417 */ + 0x2f93, /* VPRORQZ256mikz */ + 0x2f27, /* VPROLQZ256mikz */ + 0x0, /* */ + 0x0, /* */ + 0x32ec, /* VPSRAQZ256mikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x2f96, /* VPRORQZ256rikz */ + 0x2f2a, /* VPROLQZ256rikz */ + 0x0, /* */ + 0x0, /* */ + 0x32ef, /* VPSRAQZ256rikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table10433 */ + 0x0, /* */ + 0x0, /* */ + 0x33cd, /* VPSRLQZ256mikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x320f, /* VPSLLQZ256mikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x33d0, /* VPSRLQZ256rikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3212, /* VPSLLQZ256rikz */ + 0x0, /* */ +/* Table10449 */ + 0x10bc, /* VCVTTPD2UQQZ256rmkz */ + 0x10bf, /* VCVTTPD2UQQZ256rrkz */ +/* Table10451 */ + 0xed5, /* VCVTPD2UQQZ256rmkz */ + 0xed8, /* VCVTPD2UQQZ256rrkz */ +/* Table10453 */ + 0x1080, /* VCVTTPD2QQZ256rmkz */ + 0x1083, /* VCVTTPD2QQZ256rrkz */ +/* Table10455 */ + 0xe99, /* VCVTPD2QQZ256rmkz */ + 0xe9c, /* VCVTPD2QQZ256rrkz */ +/* Table10457 */ + 0x0, /* */ + 0x1df2, /* VMOVDQA64Z256rrkz_REV */ +/* Table10459 */ + 0x3985, /* VSHUFPDZ256rmikz */ + 0x3988, /* VSHUFPDZ256rrikz */ +/* Table10461 */ + 0x33d3, /* VPSRLQZ256rmkz */ + 0x33d6, /* VPSRLQZ256rrkz */ +/* Table10463 */ + 0x2142, /* VPADDQZ256rmkz */ + 0x2145, /* VPADDQZ256rrkz */ +/* Table10465 */ + 0x2238, /* VPANDQZ256rmkz */ + 0x223b, /* VPANDQZ256rrkz */ +/* Table10467 */ + 0x2219, /* VPANDNQZ256rmkz */ + 0x221c, /* VPANDNQZ256rrkz */ +/* Table10469 */ + 0x32f2, /* VPSRAQZ256rmkz */ + 0x32f5, /* VPSRAQZ256rrkz */ +/* Table10471 */ + 0x1060, /* VCVTTPD2DQZ256rmkz */ + 0x1063, /* VCVTTPD2DQZ256rrkz */ +/* Table10473 */ + 0x2ee9, /* VPORQZ256rmkz */ + 0x2eec, /* VPORQZ256rrkz */ +/* Table10475 */ + 0x36d4, /* VPXORQZ256rmkz */ + 0x36d7, /* VPXORQZ256rrkz */ +/* Table10477 */ + 0x3215, /* VPSLLQZ256rmkz */ + 0x3218, /* VPSLLQZ256rrkz */ +/* Table10479 */ + 0x2e57, /* VPMULUDQZ256rmkz */ + 0x2e5a, /* VPMULUDQZ256rrkz */ +/* Table10481 */ + 0x34a8, /* VPSUBQZ256rmkz */ + 0x34ab, /* VPSUBQZ256rrkz */ +/* Table10483 */ + 0x1f65, /* VMOVUPSZrmkz */ + 0x1f6a, /* VMOVUPSZrrkz */ +/* Table10485 */ + 0x0, /* */ + 0x1f6b, /* VMOVUPSZrrkz_REV */ +/* Table10487 */ + 0x3b08, /* VUNPCKLPSZrmkz */ + 0x3b0b, /* VUNPCKLPSZrrkz */ +/* Table10489 */ + 0x3aca, /* VUNPCKHPSZrmkz */ + 0x3acd, /* VUNPCKHPSZrrkz */ +/* Table10491 */ + 0x1d93, /* VMOVAPSZrmkz */ + 0x1d98, /* VMOVAPSZrrkz */ +/* Table10493 */ + 0x0, /* */ + 0x1d99, /* VMOVAPSZrrkz_REV */ +/* Table10495 */ + 0x39ee, /* VSQRTPSZmkz */ + 0x39f4, /* VSQRTPSZrkz */ +/* Table10497 */ + 0xc9a, /* VANDPSZrmkz */ + 0xc9d, /* VANDPSZrrkz */ +/* Table10499 */ + 0xc5c, /* VANDNPSZrmkz */ + 0xc5f, /* VANDNPSZrrkz */ +/* Table10501 */ + 0x2021, /* VORPSZrmkz */ + 0x2024, /* VORPSZrrkz */ +/* Table10503 */ + 0x3b46, /* VXORPSZrmkz */ + 0x3b49, /* VXORPSZrrkz */ +/* Table10505 */ + 0xb93, /* VADDPSZrmkz */ + 0xb99, /* VADDPSZrrkz */ +/* Table10507 */ + 0x1fbc, /* VMULPSZrmkz */ + 0x1fc2, /* VMULPSZrrkz */ +/* Table10509 */ + 0xf39, /* VCVTPS2PDZrmkz */ + 0xf3f, /* VCVTPS2PDZrrkz */ +/* Table10511 */ + 0xe3e, /* VCVTDQ2PSZrmkz */ + 0xe44, /* VCVTDQ2PSZrrkz */ +/* Table10513 */ + 0x3a51, /* VSUBPSZrmkz */ + 0x3a57, /* VSUBPSZrrkz */ +/* Table10515 */ + 0x1d19, /* VMINPSZrmkz */ + 0x1d1f, /* VMINPSZrrkz */ +/* Table10517 */ + 0x1255, /* VDIVPSZrmkz */ + 0x125b, /* VDIVPSZrrkz */ +/* Table10519 */ + 0x1c6e, /* VMAXPSZrmkz */ + 0x1c74, /* VMAXPSZrrkz */ +/* Table10521 */ + 0x1123, /* VCVTTPS2UDQZrmkz */ + 0x1129, /* VCVTTPS2UDQZrrkz */ +/* Table10523 */ + 0xf8d, /* VCVTPS2UDQZrmkz */ + 0xf93, /* VCVTPS2UDQZrrkz */ +/* Table10525 */ + 0x39ad, /* VSHUFPSZrmikz */ + 0x39b0, /* VSHUFPSZrrikz */ +/* Table10527 */ + 0x1f05, /* VMOVSLDUPZrmkz */ + 0x1f08, /* VMOVSLDUPZrrkz */ +/* Table10529 */ + 0x1eef, /* VMOVSHDUPZrmkz */ + 0x1ef2, /* VMOVSHDUPZrrkz */ +/* Table10531 */ + 0x10e5, /* VCVTTPS2DQZrmkz */ + 0x10eb, /* VCVTTPS2DQZrrkz */ +/* Table10533 */ + 0x1e41, /* VMOVDQU32Zrmkz */ + 0x1e46, /* VMOVDQU32Zrrkz */ +/* Table10535 */ + 0x3195, /* VPSHUFHWZmikz */ + 0x3198, /* VPSHUFHWZrikz */ +/* Table10537 */ + 0x1197, /* VCVTUDQ2PDZrmkz */ + 0x119a, /* VCVTUDQ2PDZrrkz */ +/* Table10539 */ + 0x0, /* */ + 0x1e47, /* VMOVDQU32Zrrkz_REV */ +/* Table10541 */ + 0xe1f, /* VCVTDQ2PDZrmkz */ + 0xe22, /* VCVTDQ2PDZrrkz */ +/* Table10543 */ + 0x1e83, /* VMOVDQU8Zrmkz */ + 0x1e88, /* VMOVDQU8Zrrkz */ +/* Table10545 */ + 0x31ab, /* VPSHUFLWZmikz */ + 0x31ae, /* VPSHUFLWZrikz */ +/* Table10547 */ + 0x11b2, /* VCVTUDQ2PSZrmkz */ + 0x11b8, /* VCVTUDQ2PSZrrkz */ +/* Table10549 */ + 0x0, /* */ + 0x1e89, /* VMOVDQU8Zrrkz_REV */ +/* Table10551 */ + 0xf17, /* VCVTPS2DQZrmkz */ + 0xf1d, /* VCVTPS2DQZrrkz */ +/* Table10553 */ + 0x3651, /* VPUNPCKLBWZrmkz */ + 0x3654, /* VPUNPCKLBWZrrkz */ +/* Table10555 */ + 0x36a5, /* VPUNPCKLWDZrmkz */ + 0x36a8, /* VPUNPCKLWDZrrkz */ +/* Table10557 */ + 0x3670, /* VPUNPCKLDQZrmkz */ + 0x3673, /* VPUNPCKLDQZrrkz */ +/* Table10559 */ + 0x20c2, /* VPACKSSWBZrmkz */ + 0x20c5, /* VPACKSSWBZrrkz */ +/* Table10561 */ + 0x20f7, /* VPACKUSWBZrmkz */ + 0x20fa, /* VPACKUSWBZrrkz */ +/* Table10563 */ + 0x35e7, /* VPUNPCKHBWZrmkz */ + 0x35ea, /* VPUNPCKHBWZrrkz */ +/* Table10565 */ + 0x363b, /* VPUNPCKHWDZrmkz */ + 0x363e, /* VPUNPCKHWDZrrkz */ +/* Table10567 */ + 0x3606, /* VPUNPCKHDQZrmkz */ + 0x3609, /* VPUNPCKHDQZrrkz */ +/* Table10569 */ + 0x20ac, /* VPACKSSDWZrmkz */ + 0x20af, /* VPACKSSDWZrrkz */ +/* Table10571 */ + 0x1dd6, /* VMOVDQA32Zrmkz */ + 0x1ddb, /* VMOVDQA32Zrrkz */ +/* Table10573 */ + 0x317f, /* VPSHUFDZmikz */ + 0x3182, /* VPSHUFDZrikz */ +/* Table10575 */ + 0x0, /* */ + 0x0, /* */ + 0x3456, /* VPSRLWZmikz */ + 0x0, /* */ + 0x336e, /* VPSRAWZmikz */ + 0x0, /* */ + 0x3298, /* VPSLLWZmikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3459, /* VPSRLWZrikz */ + 0x0, /* */ + 0x3371, /* VPSRAWZrikz */ + 0x0, /* */ + 0x329b, /* VPSLLWZrikz */ + 0x0, /* */ +/* Table10591 */ + 0x2f81, /* VPRORDZmikz */ + 0x2f15, /* VPROLDZmikz */ + 0x33a9, /* VPSRLDZmikz */ + 0x0, /* */ + 0x32cb, /* VPSRADZmikz */ + 0x0, /* */ + 0x31eb, /* VPSLLDZmikz */ + 0x0, /* */ + 0x2f84, /* VPRORDZrikz */ + 0x2f18, /* VPROLDZrikz */ + 0x33ac, /* VPSRLDZrikz */ + 0x0, /* */ + 0x32ce, /* VPSRADZrikz */ + 0x0, /* */ + 0x31ee, /* VPSLLDZrikz */ + 0x0, /* */ +/* Table10607 */ + 0x1141, /* VCVTTPS2UQQZrmkz */ + 0x1147, /* VCVTTPS2UQQZrrkz */ +/* Table10609 */ + 0xfab, /* VCVTPS2UQQZrmkz */ + 0xfb1, /* VCVTPS2UQQZrrkz */ +/* Table10611 */ + 0x1105, /* VCVTTPS2QQZrmkz */ + 0x110b, /* VCVTTPS2QQZrrkz */ +/* Table10613 */ + 0xf6f, /* VCVTPS2QQZrmkz */ + 0xf75, /* VCVTPS2QQZrrkz */ +/* Table10615 */ + 0x0, /* */ + 0x1ddc, /* VMOVDQA32Zrrkz_REV */ +/* Table10617 */ + 0x345c, /* VPSRLWZrmkz */ + 0x345f, /* VPSRLWZrrkz */ +/* Table10619 */ + 0x33af, /* VPSRLDZrmkz */ + 0x33b2, /* VPSRLDZrrkz */ +/* Table10621 */ + 0x2e26, /* VPMULLWZrmkz */ + 0x2e29, /* VPMULLWZrrkz */ +/* Table10623 */ + 0x34f3, /* VPSUBUSBZrmkz */ + 0x34f6, /* VPSUBUSBZrrkz */ +/* Table10625 */ + 0x3509, /* VPSUBUSWZrmkz */ + 0x350c, /* VPSUBUSWZrrkz */ +/* Table10627 */ + 0x2af5, /* VPMINUBZrmkz */ + 0x2af8, /* VPMINUBZrrkz */ +/* Table10629 */ + 0x21ec, /* VPANDDZrmkz */ + 0x21ef, /* VPANDDZrrkz */ +/* Table10631 */ + 0x218d, /* VPADDUSBZrmkz */ + 0x2190, /* VPADDUSBZrrkz */ +/* Table10633 */ + 0x21a3, /* VPADDUSWZrmkz */ + 0x21a6, /* VPADDUSWZrrkz */ +/* Table10635 */ + 0x2a29, /* VPMAXUBZrmkz */ + 0x2a2c, /* VPMAXUBZrrkz */ +/* Table10637 */ + 0x2207, /* VPANDNDZrmkz */ + 0x220a, /* VPANDNDZrrkz */ +/* Table10639 */ + 0x2259, /* VPAVGBZrmkz */ + 0x225c, /* VPAVGBZrrkz */ +/* Table10641 */ + 0x3374, /* VPSRAWZrmkz */ + 0x3377, /* VPSRAWZrrkz */ +/* Table10643 */ + 0x32d1, /* VPSRADZrmkz */ + 0x32d4, /* VPSRADZrrkz */ +/* Table10645 */ + 0x226f, /* VPAVGWZrmkz */ + 0x2272, /* VPAVGWZrrkz */ +/* Table10647 */ + 0x2dc0, /* VPMULHUWZrmkz */ + 0x2dc3, /* VPMULHUWZrrkz */ +/* Table10649 */ + 0x2dd6, /* VPMULHWZrmkz */ + 0x2dd9, /* VPMULHWZrrkz */ +/* Table10651 */ + 0x34c7, /* VPSUBSBZrmkz */ + 0x34ca, /* VPSUBSBZrrkz */ +/* Table10653 */ + 0x34dd, /* VPSUBSWZrmkz */ + 0x34e0, /* VPSUBSWZrrkz */ +/* Table10655 */ + 0x2adf, /* VPMINSWZrmkz */ + 0x2ae2, /* VPMINSWZrrkz */ +/* Table10657 */ + 0x2ed7, /* VPORDZrmkz */ + 0x2eda, /* VPORDZrrkz */ +/* Table10659 */ + 0x2161, /* VPADDSBZrmkz */ + 0x2164, /* VPADDSBZrrkz */ +/* Table10661 */ + 0x2177, /* VPADDSWZrmkz */ + 0x217a, /* VPADDSWZrrkz */ +/* Table10663 */ + 0x2a13, /* VPMAXSWZrmkz */ + 0x2a16, /* VPMAXSWZrrkz */ +/* Table10665 */ + 0x36c2, /* VPXORDZrmkz */ + 0x36c5, /* VPXORDZrrkz */ +/* Table10667 */ + 0x329e, /* VPSLLWZrmkz */ + 0x32a1, /* VPSLLWZrrkz */ +/* Table10669 */ + 0x31f1, /* VPSLLDZrmkz */ + 0x31f4, /* VPSLLDZrrkz */ +/* Table10671 */ + 0x29a5, /* VPMADDWDZrmkz */ + 0x29a8, /* VPMADDWDZrrkz */ +/* Table10673 */ + 0x3473, /* VPSUBBZrmkz */ + 0x3476, /* VPSUBBZrrkz */ +/* Table10675 */ + 0x351f, /* VPSUBWZrmkz */ + 0x3522, /* VPSUBWZrrkz */ +/* Table10677 */ + 0x3492, /* VPSUBDZrmkz */ + 0x3495, /* VPSUBDZrrkz */ +/* Table10679 */ + 0x210d, /* VPADDBZrmkz */ + 0x2110, /* VPADDBZrrkz */ +/* Table10681 */ + 0x21b9, /* VPADDWZrmkz */ + 0x21bc, /* VPADDWZrrkz */ +/* Table10683 */ + 0x212c, /* VPADDDZrmkz */ + 0x212f, /* VPADDDZrrkz */ +/* Table10685 */ + 0xfe7, /* VCVTQQ2PSZrmkz */ + 0xfed, /* VCVTQQ2PSZrrkz */ +/* Table10687 */ + 0x10a7, /* VCVTTPD2UDQZrmkz */ + 0x10ad, /* VCVTTPD2UDQZrrkz */ +/* Table10689 */ + 0xec0, /* VCVTPD2UDQZrmkz */ + 0xec6, /* VCVTPD2UDQZrrkz */ +/* Table10691 */ + 0x1e62, /* VMOVDQU64Zrmkz */ + 0x1e67, /* VMOVDQU64Zrrkz */ +/* Table10693 */ + 0x11d0, /* VCVTUQQ2PDZrmkz */ + 0x11d6, /* VCVTUQQ2PDZrrkz */ +/* Table10695 */ + 0x0, /* */ + 0x1e68, /* VMOVDQU64Zrrkz_REV */ +/* Table10697 */ + 0xfc9, /* VCVTQQ2PDZrmkz */ + 0xfcf, /* VCVTQQ2PDZrrkz */ +/* Table10699 */ + 0x1dae, /* VMOVDDUPZrmkz */ + 0x1db1, /* VMOVDDUPZrrkz */ +/* Table10701 */ + 0x1e20, /* VMOVDQU16Zrmkz */ + 0x1e25, /* VMOVDQU16Zrrkz */ +/* Table10703 */ + 0x11ee, /* VCVTUQQ2PSZrmkz */ + 0x11f4, /* VCVTUQQ2PSZrrkz */ +/* Table10705 */ + 0x0, /* */ + 0x1e26, /* VMOVDQU16Zrrkz_REV */ +/* Table10707 */ + 0xe60, /* VCVTPD2DQZrmkz */ + 0xe66, /* VCVTPD2DQZrrkz */ +/* Table10709 */ + 0x1f3c, /* VMOVUPDZrmkz */ + 0x1f41, /* VMOVUPDZrrkz */ +/* Table10711 */ + 0x0, /* */ + 0x1f42, /* VMOVUPDZrrkz_REV */ +/* Table10713 */ + 0x3ae9, /* VUNPCKLPDZrmkz */ + 0x3aec, /* VUNPCKLPDZrrkz */ +/* Table10715 */ + 0x3aab, /* VUNPCKHPDZrmkz */ + 0x3aae, /* VUNPCKHPDZrrkz */ +/* Table10717 */ + 0x1d6a, /* VMOVAPDZrmkz */ + 0x1d6f, /* VMOVAPDZrrkz */ +/* Table10719 */ + 0x0, /* */ + 0x1d70, /* VMOVAPDZrrkz_REV */ +/* Table10721 */ + 0x39cc, /* VSQRTPDZmkz */ + 0x39d2, /* VSQRTPDZrkz */ +/* Table10723 */ + 0xc7b, /* VANDPDZrmkz */ + 0xc7e, /* VANDPDZrrkz */ +/* Table10725 */ + 0xc3d, /* VANDNPDZrmkz */ + 0xc40, /* VANDNPDZrrkz */ +/* Table10727 */ + 0x2002, /* VORPDZrmkz */ + 0x2005, /* VORPDZrrkz */ +/* Table10729 */ + 0x3b27, /* VXORPDZrmkz */ + 0x3b2a, /* VXORPDZrrkz */ +/* Table10731 */ + 0xb71, /* VADDPDZrmkz */ + 0xb77, /* VADDPDZrrkz */ +/* Table10733 */ + 0x1f9a, /* VMULPDZrmkz */ + 0x1fa0, /* VMULPDZrrkz */ +/* Table10735 */ + 0xe82, /* VCVTPD2PSZrmkz */ + 0xe88, /* VCVTPD2PSZrrkz */ +/* Table10737 */ + 0x3a2f, /* VSUBPDZrmkz */ + 0x3a35, /* VSUBPDZrrkz */ +/* Table10739 */ + 0x1cf7, /* VMINPDZrmkz */ + 0x1cfd, /* VMINPDZrrkz */ +/* Table10741 */ + 0x1233, /* VDIVPDZrmkz */ + 0x1239, /* VDIVPDZrrkz */ +/* Table10743 */ + 0x1c4c, /* VMAXPDZrmkz */ + 0x1c52, /* VMAXPDZrrkz */ +/* Table10745 */ + 0x368f, /* VPUNPCKLQDQZrmkz */ + 0x3692, /* VPUNPCKLQDQZrrkz */ +/* Table10747 */ + 0x3625, /* VPUNPCKHQDQZrmkz */ + 0x3628, /* VPUNPCKHQDQZrrkz */ +/* Table10749 */ + 0x1df7, /* VMOVDQA64Zrmkz */ + 0x1dfc, /* VMOVDQA64Zrrkz */ +/* Table10751 */ + 0x2f9c, /* VPRORQZmikz */ + 0x2f30, /* VPROLQZmikz */ + 0x0, /* */ + 0x0, /* */ + 0x32fb, /* VPSRAQZmikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x2f9f, /* VPRORQZrikz */ + 0x2f33, /* VPROLQZrikz */ + 0x0, /* */ + 0x0, /* */ + 0x32fe, /* VPSRAQZrikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table10767 */ + 0x0, /* */ + 0x0, /* */ + 0x33dc, /* VPSRLQZmikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x321e, /* VPSLLQZmikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x33df, /* VPSRLQZrikz */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3221, /* VPSLLQZrikz */ + 0x0, /* */ +/* Table10783 */ + 0x10c5, /* VCVTTPD2UQQZrmkz */ + 0x10cb, /* VCVTTPD2UQQZrrkz */ +/* Table10785 */ + 0xede, /* VCVTPD2UQQZrmkz */ + 0xee4, /* VCVTPD2UQQZrrkz */ +/* Table10787 */ + 0x1089, /* VCVTTPD2QQZrmkz */ + 0x108f, /* VCVTTPD2QQZrrkz */ +/* Table10789 */ + 0xea2, /* VCVTPD2QQZrmkz */ + 0xea8, /* VCVTPD2QQZrrkz */ +/* Table10791 */ + 0x0, /* */ + 0x1dfd, /* VMOVDQA64Zrrkz_REV */ +/* Table10793 */ + 0x398e, /* VSHUFPDZrmikz */ + 0x3991, /* VSHUFPDZrrikz */ +/* Table10795 */ + 0x33e2, /* VPSRLQZrmkz */ + 0x33e5, /* VPSRLQZrrkz */ +/* Table10797 */ + 0x214b, /* VPADDQZrmkz */ + 0x214e, /* VPADDQZrrkz */ +/* Table10799 */ + 0x2241, /* VPANDQZrmkz */ + 0x2244, /* VPANDQZrrkz */ +/* Table10801 */ + 0x2222, /* VPANDNQZrmkz */ + 0x2225, /* VPANDNQZrrkz */ +/* Table10803 */ + 0x3301, /* VPSRAQZrmkz */ + 0x3304, /* VPSRAQZrrkz */ +/* Table10805 */ + 0x1069, /* VCVTTPD2DQZrmkz */ + 0x106f, /* VCVTTPD2DQZrrkz */ +/* Table10807 */ + 0x2ef2, /* VPORQZrmkz */ + 0x2ef5, /* VPORQZrrkz */ +/* Table10809 */ + 0x36dd, /* VPXORQZrmkz */ + 0x36e0, /* VPXORQZrrkz */ +/* Table10811 */ + 0x3224, /* VPSLLQZrmkz */ + 0x3227, /* VPSLLQZrrkz */ +/* Table10813 */ + 0x2e60, /* VPMULUDQZrmkz */ + 0x2e63, /* VPMULUDQZrrkz */ +/* Table10815 */ + 0x34b1, /* VPSUBQZrmkz */ + 0x34b4, /* VPSUBQZrrkz */ +/* Table10817 */ + 0x5c8, /* MMX_PSHUFBrm */ + 0x5c9, /* MMX_PSHUFBrr */ +/* Table10819 */ + 0x5a3, /* MMX_PHADDWrm */ + 0x5a4, /* MMX_PHADDWrr */ +/* Table10821 */ + 0x59f, /* MMX_PHADDDrm */ + 0x5a0, /* MMX_PHADDDrr */ +/* Table10823 */ + 0x5a1, /* MMX_PHADDSWrm */ + 0x5a2, /* MMX_PHADDSWrr */ +/* Table10825 */ + 0x5ad, /* MMX_PMADDUBSWrm */ + 0x5ae, /* MMX_PMADDUBSWrr */ +/* Table10827 */ + 0x5a9, /* MMX_PHSUBWrm */ + 0x5aa, /* MMX_PHSUBWrr */ +/* Table10829 */ + 0x5a5, /* MMX_PHSUBDrm */ + 0x5a6, /* MMX_PHSUBDrr */ +/* Table10831 */ + 0x5a7, /* MMX_PHSUBSWrm */ + 0x5a8, /* MMX_PHSUBSWrr */ +/* Table10833 */ + 0x5cc, /* MMX_PSIGNBrm */ + 0x5cd, /* MMX_PSIGNBrr */ +/* Table10835 */ + 0x5d0, /* MMX_PSIGNWrm */ + 0x5d1, /* MMX_PSIGNWrr */ +/* Table10837 */ + 0x5ce, /* MMX_PSIGNDrm */ + 0x5cf, /* MMX_PSIGNDrr */ +/* Table10839 */ + 0x5ba, /* MMX_PMULHRSWrm */ + 0x5bb, /* MMX_PMULHRSWrr */ +/* Table10841 */ + 0x56c, /* MMX_PABSBrm */ + 0x56d, /* MMX_PABSBrr */ +/* Table10843 */ + 0x570, /* MMX_PABSWrm */ + 0x571, /* MMX_PABSWrr */ +/* Table10845 */ + 0x56e, /* MMX_PABSDrm */ + 0x56f, /* MMX_PABSDrr */ +/* Table10847 */ + 0x9fd, /* SHA1NEXTErm */ + 0x9fe, /* SHA1NEXTErr */ +/* Table10849 */ + 0x9f9, /* SHA1MSG1rm */ + 0x9fa, /* SHA1MSG1rr */ +/* Table10851 */ + 0x9fb, /* SHA1MSG2rm */ + 0x9fc, /* SHA1MSG2rr */ +/* Table10853 */ + 0xa05, /* SHA256RNDS2rm */ + 0xa06, /* SHA256RNDS2rr */ +/* Table10855 */ + 0xa01, /* SHA256MSG1rm */ + 0xa02, /* SHA256MSG1rr */ +/* Table10857 */ + 0xa03, /* SHA256MSG2rm */ + 0xa04, /* SHA256MSG2rr */ +/* Table10859 */ + 0x65f, /* MOVBE32rm */ + 0x0, /* */ +/* Table10861 */ + 0x65e, /* MOVBE32mr */ + 0x0, /* */ +/* Table10863 */ + 0x3b57, /* WRSSD */ + 0x0, /* */ +/* Table10865 */ + 0x66b, /* MOVDIRI32 */ + 0x0, /* */ +/* Table10867 */ + 0x867, /* PSHUFBrm */ + 0x868, /* PSHUFBrr */ +/* Table10869 */ + 0x7e1, /* PHADDWrm */ + 0x7e2, /* PHADDWrr */ +/* Table10871 */ + 0x7dd, /* PHADDDrm */ + 0x7de, /* PHADDDrr */ +/* Table10873 */ + 0x7df, /* PHADDSWrm */ + 0x7e0, /* PHADDSWrr */ +/* Table10875 */ + 0x7f7, /* PMADDUBSWrm */ + 0x7f8, /* PMADDUBSWrr */ +/* Table10877 */ + 0x7e9, /* PHSUBWrm */ + 0x7ea, /* PHSUBWrr */ +/* Table10879 */ + 0x7e5, /* PHSUBDrm */ + 0x7e6, /* PHSUBDrr */ +/* Table10881 */ + 0x7e7, /* PHSUBSWrm */ + 0x7e8, /* PHSUBSWrr */ +/* Table10883 */ + 0x86f, /* PSIGNBrm */ + 0x870, /* PSIGNBrr */ +/* Table10885 */ + 0x873, /* PSIGNWrm */ + 0x874, /* PSIGNWrr */ +/* Table10887 */ + 0x871, /* PSIGNDrm */ + 0x872, /* PSIGNDrr */ +/* Table10889 */ + 0x82e, /* PMULHRSWrm */ + 0x82f, /* PMULHRSWrr */ +/* Table10891 */ + 0x787, /* PBLENDVBrm0 */ + 0x788, /* PBLENDVBrr0 */ +/* Table10893 */ + 0x16f, /* BLENDVPSrm0 */ + 0x170, /* BLENDVPSrr0 */ +/* Table10895 */ + 0x16d, /* BLENDVPDrm0 */ + 0x16e, /* BLENDVPDrr0 */ +/* Table10897 */ + 0x8a1, /* PTESTrm */ + 0x8a2, /* PTESTrr */ +/* Table10899 */ + 0x75c, /* PABSBrm */ + 0x75d, /* PABSBrr */ +/* Table10901 */ + 0x760, /* PABSWrm */ + 0x761, /* PABSWrr */ +/* Table10903 */ + 0x75e, /* PABSDrm */ + 0x75f, /* PABSDrr */ +/* Table10905 */ + 0x818, /* PMOVSXBWrm */ + 0x819, /* PMOVSXBWrr */ +/* Table10907 */ + 0x814, /* PMOVSXBDrm */ + 0x815, /* PMOVSXBDrr */ +/* Table10909 */ + 0x816, /* PMOVSXBQrm */ + 0x817, /* PMOVSXBQrr */ +/* Table10911 */ + 0x81c, /* PMOVSXWDrm */ + 0x81d, /* PMOVSXWDrr */ +/* Table10913 */ + 0x81e, /* PMOVSXWQrm */ + 0x81f, /* PMOVSXWQrr */ +/* Table10915 */ + 0x81a, /* PMOVSXDQrm */ + 0x81b, /* PMOVSXDQrr */ +/* Table10917 */ + 0x82c, /* PMULDQrm */ + 0x82d, /* PMULDQrr */ +/* Table10919 */ + 0x791, /* PCMPEQQrm */ + 0x792, /* PCMPEQQrr */ +/* Table10921 */ + 0x681, /* MOVNTDQArm */ + 0x0, /* */ +/* Table10923 */ + 0x766, /* PACKUSDWrm */ + 0x767, /* PACKUSDWrr */ +/* Table10925 */ + 0x824, /* PMOVZXBWrm */ + 0x825, /* PMOVZXBWrr */ +/* Table10927 */ + 0x820, /* PMOVZXBDrm */ + 0x821, /* PMOVZXBDrr */ +/* Table10929 */ + 0x822, /* PMOVZXBQrm */ + 0x823, /* PMOVZXBQrr */ +/* Table10931 */ + 0x828, /* PMOVZXWDrm */ + 0x829, /* PMOVZXWDrr */ +/* Table10933 */ + 0x82a, /* PMOVZXWQrm */ + 0x82b, /* PMOVZXWQrr */ +/* Table10935 */ + 0x826, /* PMOVZXDQrm */ + 0x827, /* PMOVZXDQrr */ +/* Table10937 */ + 0x79d, /* PCMPGTQrm */ + 0x79e, /* PCMPGTQrr */ +/* Table10939 */ + 0x807, /* PMINSBrm */ + 0x808, /* PMINSBrr */ +/* Table10941 */ + 0x809, /* PMINSDrm */ + 0x80a, /* PMINSDrr */ +/* Table10943 */ + 0x811, /* PMINUWrm */ + 0x812, /* PMINUWrr */ +/* Table10945 */ + 0x80f, /* PMINUDrm */ + 0x810, /* PMINUDrr */ +/* Table10947 */ + 0x7fb, /* PMAXSBrm */ + 0x7fc, /* PMAXSBrr */ +/* Table10949 */ + 0x7fd, /* PMAXSDrm */ + 0x7fe, /* PMAXSDrr */ +/* Table10951 */ + 0x805, /* PMAXUWrm */ + 0x806, /* PMAXUWrr */ +/* Table10953 */ + 0x803, /* PMAXUDrm */ + 0x804, /* PMAXUDrr */ +/* Table10955 */ + 0x836, /* PMULLDrm */ + 0x837, /* PMULLDrr */ +/* Table10957 */ + 0x7e3, /* PHMINPOSUWrm */ + 0x7e4, /* PHMINPOSUWrr */ +/* Table10959 */ + 0x417, /* INVEPT32 */ + 0x0, /* */ +/* Table10961 */ + 0x41e, /* INVVPID32 */ + 0x0, /* */ +/* Table10963 */ + 0x41c, /* INVPCID32 */ + 0x0, /* */ +/* Table10965 */ + 0x3c0, /* GF2P8MULBrm */ + 0x3c1, /* GF2P8MULBrr */ +/* Table10967 */ + 0x117, /* AESIMCrm */ + 0x118, /* AESIMCrr */ +/* Table10969 */ + 0x115, /* AESENCrm */ + 0x116, /* AESENCrr */ +/* Table10971 */ + 0x113, /* AESENCLASTrm */ + 0x114, /* AESENCLASTrr */ +/* Table10973 */ + 0x111, /* AESDECrm */ + 0x112, /* AESDECrr */ +/* Table10975 */ + 0x10f, /* AESDECLASTrm */ + 0x110, /* AESDECLASTrr */ +/* Table10977 */ + 0x65d, /* MOVBE16rm */ + 0x0, /* */ +/* Table10979 */ + 0x65c, /* MOVBE16mr */ + 0x0, /* */ +/* Table10981 */ + 0x3b59, /* WRUSSD */ + 0x0, /* */ +/* Table10983 */ + 0xbe, /* ADCX32rm */ + 0xbf, /* ADCX32rr */ +/* Table10985 */ + 0x669, /* MOVDIR64B32 */ + 0x0, /* */ +/* Table10987 */ + 0x668, /* MOVDIR64B16 */ + 0x0, /* */ +/* Table10989 */ + 0x2dd, /* CRC32r32m8 */ + 0x2e0, /* CRC32r32r8 */ +/* Table10991 */ + 0x2dc, /* CRC32r32m32 */ + 0x2df, /* CRC32r32r32 */ +/* Table10993 */ + 0x10b, /* ADOX32rm */ + 0x10c, /* ADOX32rr */ +/* Table10995 */ + 0x2db, /* CRC32r32m16 */ + 0x2de, /* CRC32r32r16 */ +/* Table10997 */ + 0x661, /* MOVBE64rm */ + 0x0, /* */ +/* Table10999 */ + 0x660, /* MOVBE64mr */ + 0x0, /* */ +/* Table11001 */ + 0x3b58, /* WRSSQ */ + 0x0, /* */ +/* Table11003 */ + 0x66c, /* MOVDIRI64 */ + 0x0, /* */ +/* Table11005 */ + 0x418, /* INVEPT64 */ + 0x0, /* */ +/* Table11007 */ + 0x41f, /* INVVPID64 */ + 0x0, /* */ +/* Table11009 */ + 0x41d, /* INVPCID64 */ + 0x0, /* */ +/* Table11011 */ + 0x3b58, /* WRSSQ */ + 0xbf, /* ADCX32rr */ +/* Table11013 */ + 0x66a, /* MOVDIR64B64 */ + 0x0, /* */ +/* Table11015 */ + 0x10d, /* ADOX64rm */ + 0x10e, /* ADOX64rr */ +/* Table11017 */ + 0x2e2, /* CRC32r64m8 */ + 0x2e4, /* CRC32r64r8 */ +/* Table11019 */ + 0x2e1, /* CRC32r64m64 */ + 0x2e3, /* CRC32r64r64 */ +/* Table11021 */ + 0x3b5a, /* WRUSSQ */ + 0x0, /* */ +/* Table11023 */ + 0xc0, /* ADCX64rm */ + 0xc1, /* ADCX64rr */ +/* Table11025 */ + 0x13f, /* ANDN32rm */ + 0x140, /* ANDN32rr */ +/* Table11027 */ + 0x0, /* */ + 0x181, /* BLSR32rm */ + 0x17d, /* BLSMSK32rm */ + 0x175, /* BLSI32rm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x182, /* BLSR32rr */ + 0x17e, /* BLSMSK32rr */ + 0x176, /* BLSI32rr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table11043 */ + 0x1dc, /* BZHI32rm */ + 0x1dd, /* BZHI32rr */ +/* Table11045 */ + 0x14d, /* BEXTR32rm */ + 0x14e, /* BEXTR32rr */ +/* Table11047 */ + 0x7aa, /* PEXT32rm */ + 0x7ab, /* PEXT32rr */ +/* Table11049 */ + 0x9a7, /* SARX32rm */ + 0x9a8, /* SARX32rr */ +/* Table11051 */ + 0x7a6, /* PDEP32rm */ + 0x7a7, /* PDEP32rr */ +/* Table11053 */ + 0x6e1, /* MULX32rm */ + 0x6e2, /* MULX32rr */ +/* Table11055 */ + 0xa53, /* SHRX32rm */ + 0xa54, /* SHRX32rr */ +/* Table11057 */ + 0x3164, /* VPSHUFBrm */ + 0x3165, /* VPSHUFBrr */ +/* Table11059 */ + 0x28d5, /* VPHADDWrm */ + 0x28d6, /* VPHADDWrr */ +/* Table11061 */ + 0x28bd, /* VPHADDDrm */ + 0x28be, /* VPHADDDrr */ +/* Table11063 */ + 0x28c1, /* VPHADDSWrm */ + 0x28c2, /* VPHADDSWrr */ +/* Table11065 */ + 0x2993, /* VPMADDUBSWrm */ + 0x2994, /* VPMADDUBSWrr */ +/* Table11067 */ + 0x28e9, /* VPHSUBWrm */ + 0x28ea, /* VPHSUBWrr */ +/* Table11069 */ + 0x28df, /* VPHSUBDrm */ + 0x28e0, /* VPHSUBDrr */ +/* Table11071 */ + 0x28e3, /* VPHSUBSWrm */ + 0x28e4, /* VPHSUBSWrr */ +/* Table11073 */ + 0x31b3, /* VPSIGNBrm */ + 0x31b4, /* VPSIGNBrr */ +/* Table11075 */ + 0x31bb, /* VPSIGNWrm */ + 0x31bc, /* VPSIGNWrr */ +/* Table11077 */ + 0x31b7, /* VPSIGNDrm */ + 0x31b8, /* VPSIGNDrr */ +/* Table11079 */ + 0x2dae, /* VPMULHRSWrm */ + 0x2daf, /* VPMULHRSWrr */ +/* Table11081 */ + 0x2741, /* VPERMILPSrm */ + 0x2742, /* VPERMILPSrr */ +/* Table11083 */ + 0x2703, /* VPERMILPDrm */ + 0x2704, /* VPERMILPDrr */ +/* Table11085 */ + 0x3a7e, /* VTESTPSrm */ + 0x3a7f, /* VTESTPSrr */ +/* Table11087 */ + 0x3a7a, /* VTESTPDrm */ + 0x3a7b, /* VTESTPDrr */ +/* Table11089 */ + 0xefc, /* VCVTPH2PSrm */ + 0xefd, /* VCVTPH2PSrr */ +/* Table11091 */ + 0x35d5, /* VPTESTrm */ + 0x35d6, /* VPTESTrr */ +/* Table11093 */ + 0xd4c, /* VBROADCASTSSrm */ + 0xd4d, /* VBROADCASTSSrr */ +/* Table11095 */ + 0x2041, /* VPABSBrm */ + 0x2042, /* VPABSBrr */ +/* Table11097 */ + 0x2091, /* VPABSWrm */ + 0x2092, /* VPABSWrr */ +/* Table11099 */ + 0x2060, /* VPABSDrm */ + 0x2061, /* VPABSDrr */ +/* Table11101 */ + 0x2c47, /* VPMOVSXBWrm */ + 0x2c48, /* VPMOVSXBWrr */ +/* Table11103 */ + 0x2c1b, /* VPMOVSXBDrm */ + 0x2c1c, /* VPMOVSXBDrr */ +/* Table11105 */ + 0x2c31, /* VPMOVSXBQrm */ + 0x2c32, /* VPMOVSXBQrr */ +/* Table11107 */ + 0x2c73, /* VPMOVSXWDrm */ + 0x2c74, /* VPMOVSXWDrr */ +/* Table11109 */ + 0x2c89, /* VPMOVSXWQrm */ + 0x2c8a, /* VPMOVSXWQrr */ +/* Table11111 */ + 0x2c5d, /* VPMOVSXDQrm */ + 0x2c5e, /* VPMOVSXDQrr */ +/* Table11113 */ + 0x2d98, /* VPMULDQrm */ + 0x2d99, /* VPMULDQrr */ +/* Table11115 */ + 0x23e5, /* VPCMPEQQrm */ + 0x23e6, /* VPCMPEQQrr */ +/* Table11117 */ + 0x1eae, /* VMOVNTDQArm */ + 0x0, /* */ +/* Table11119 */ + 0x20e5, /* VPACKUSDWrm */ + 0x20e6, /* VPACKUSDWrr */ +/* Table11121 */ + 0x1bec, /* VMASKMOVPSrm */ + 0x0, /* */ +/* Table11123 */ + 0x1be8, /* VMASKMOVPDrm */ + 0x0, /* */ +/* Table11125 */ + 0x1beb, /* VMASKMOVPSmr */ + 0x0, /* */ +/* Table11127 */ + 0x1be7, /* VMASKMOVPDmr */ + 0x0, /* */ +/* Table11129 */ + 0x2d37, /* VPMOVZXBWrm */ + 0x2d38, /* VPMOVZXBWrr */ +/* Table11131 */ + 0x2d0b, /* VPMOVZXBDrm */ + 0x2d0c, /* VPMOVZXBDrr */ +/* Table11133 */ + 0x2d21, /* VPMOVZXBQrm */ + 0x2d22, /* VPMOVZXBQrr */ +/* Table11135 */ + 0x2d63, /* VPMOVZXWDrm */ + 0x2d64, /* VPMOVZXWDrr */ +/* Table11137 */ + 0x2d79, /* VPMOVZXWQrm */ + 0x2d7a, /* VPMOVZXWQrr */ +/* Table11139 */ + 0x2d4d, /* VPMOVZXDQrm */ + 0x2d4e, /* VPMOVZXDQrr */ +/* Table11141 */ + 0x2435, /* VPCMPGTQrm */ + 0x2436, /* VPCMPGTQrr */ +/* Table11143 */ + 0x2a93, /* VPMINSBrm */ + 0x2a94, /* VPMINSBrr */ +/* Table11145 */ + 0x2ab2, /* VPMINSDrm */ + 0x2ab3, /* VPMINSDrr */ +/* Table11147 */ + 0x2b49, /* VPMINUWrm */ + 0x2b4a, /* VPMINUWrr */ +/* Table11149 */ + 0x2b18, /* VPMINUDrm */ + 0x2b19, /* VPMINUDrr */ +/* Table11151 */ + 0x29c7, /* VPMAXSBrm */ + 0x29c8, /* VPMAXSBrr */ +/* Table11153 */ + 0x29e6, /* VPMAXSDrm */ + 0x29e7, /* VPMAXSDrr */ +/* Table11155 */ + 0x2a7d, /* VPMAXUWrm */ + 0x2a7e, /* VPMAXUWrr */ +/* Table11157 */ + 0x2a4c, /* VPMAXUDrm */ + 0x2a4d, /* VPMAXUDrr */ +/* Table11159 */ + 0x2df9, /* VPMULLDrm */ + 0x2dfa, /* VPMULLDrr */ +/* Table11161 */ + 0x28d7, /* VPHMINPOSUWrm */ + 0x28d8, /* VPHMINPOSUWrr */ +/* Table11163 */ + 0x3406, /* VPSRLVDrm */ + 0x3407, /* VPSRLVDrr */ +/* Table11165 */ + 0x3322, /* VPSRAVDrm */ + 0x3323, /* VPSRAVDrr */ +/* Table11167 */ + 0x3248, /* VPSLLVDrm */ + 0x3249, /* VPSLLVDrr */ +/* Table11169 */ + 0x2317, /* VPBROADCASTDrm */ + 0x2318, /* VPBROADCASTDrr */ +/* Table11171 */ + 0x233c, /* VPBROADCASTQrm */ + 0x233d, /* VPBROADCASTQrr */ +/* Table11173 */ + 0x22f8, /* VPBROADCASTBrm */ + 0x22f9, /* VPBROADCASTBrr */ +/* Table11175 */ + 0x235b, /* VPBROADCASTWrm */ + 0x235c, /* VPBROADCASTWrr */ +/* Table11177 */ + 0x29ae, /* VPMASKMOVDrm */ + 0x0, /* */ +/* Table11179 */ + 0x29ad, /* VPMASKMOVDmr */ + 0x0, /* */ +/* Table11181 */ + 0x28a3, /* VPGATHERDDrm */ + 0x0, /* */ +/* Table11183 */ + 0x28ad, /* VPGATHERQDrm */ + 0x0, /* */ +/* Table11185 */ + 0x1a7d, /* VGATHERDPSrm */ + 0x0, /* */ +/* Table11187 */ + 0x1a8f, /* VGATHERQPSrm */ + 0x0, /* */ +/* Table11189 */ + 0x14e2, /* VFMADDSUB132PSm */ + 0x14e3, /* VFMADDSUB132PSr */ +/* Table11191 */ + 0x16ea, /* VFMSUBADD132PSm */ + 0x16eb, /* VFMSUBADD132PSr */ +/* Table11193 */ + 0x1396, /* VFMADD132PSm */ + 0x1397, /* VFMADD132PSr */ +/* Table11195 */ + 0x13b4, /* VFMADD132SSm */ + 0x13b6, /* VFMADD132SSr */ +/* Table11197 */ + 0x15be, /* VFMSUB132PSm */ + 0x15bf, /* VFMSUB132PSr */ +/* Table11199 */ + 0x15dc, /* VFMSUB132SSm */ + 0x15de, /* VFMSUB132SSr */ +/* Table11201 */ + 0x17e6, /* VFNMADD132PSm */ + 0x17e7, /* VFNMADD132PSr */ +/* Table11203 */ + 0x1804, /* VFNMADD132SSm */ + 0x1806, /* VFNMADD132SSr */ +/* Table11205 */ + 0x1932, /* VFNMSUB132PSm */ + 0x1933, /* VFNMSUB132PSr */ +/* Table11207 */ + 0x1950, /* VFNMSUB132SSm */ + 0x1952, /* VFNMSUB132SSr */ +/* Table11209 */ + 0x1526, /* VFMADDSUB213PSm */ + 0x1527, /* VFMADDSUB213PSr */ +/* Table11211 */ + 0x172e, /* VFMSUBADD213PSm */ + 0x172f, /* VFMSUBADD213PSr */ +/* Table11213 */ + 0x13fa, /* VFMADD213PSm */ + 0x13fb, /* VFMADD213PSr */ +/* Table11215 */ + 0x1418, /* VFMADD213SSm */ + 0x141a, /* VFMADD213SSr */ +/* Table11217 */ + 0x1622, /* VFMSUB213PSm */ + 0x1623, /* VFMSUB213PSr */ +/* Table11219 */ + 0x1640, /* VFMSUB213SSm */ + 0x1642, /* VFMSUB213SSr */ +/* Table11221 */ + 0x184a, /* VFNMADD213PSm */ + 0x184b, /* VFNMADD213PSr */ +/* Table11223 */ + 0x1868, /* VFNMADD213SSm */ + 0x186a, /* VFNMADD213SSr */ +/* Table11225 */ + 0x1996, /* VFNMSUB213PSm */ + 0x1997, /* VFNMSUB213PSr */ +/* Table11227 */ + 0x19b4, /* VFNMSUB213SSm */ + 0x19b6, /* VFNMSUB213SSr */ +/* Table11229 */ + 0x156a, /* VFMADDSUB231PSm */ + 0x156b, /* VFMADDSUB231PSr */ +/* Table11231 */ + 0x1772, /* VFMSUBADD231PSm */ + 0x1773, /* VFMSUBADD231PSr */ +/* Table11233 */ + 0x145e, /* VFMADD231PSm */ + 0x145f, /* VFMADD231PSr */ +/* Table11235 */ + 0x147c, /* VFMADD231SSm */ + 0x147e, /* VFMADD231SSr */ +/* Table11237 */ + 0x1686, /* VFMSUB231PSm */ + 0x1687, /* VFMSUB231PSr */ +/* Table11239 */ + 0x16a4, /* VFMSUB231SSm */ + 0x16a6, /* VFMSUB231SSr */ +/* Table11241 */ + 0x18ae, /* VFNMADD231PSm */ + 0x18af, /* VFNMADD231PSr */ +/* Table11243 */ + 0x18cc, /* VFNMADD231SSm */ + 0x18ce, /* VFNMADD231SSr */ +/* Table11245 */ + 0x19fa, /* VFNMSUB231PSm */ + 0x19fb, /* VFNMSUB231PSr */ +/* Table11247 */ + 0x1a18, /* VFNMSUB231SSm */ + 0x1a1a, /* VFNMSUB231SSr */ +/* Table11249 */ + 0x1b7e, /* VGF2P8MULBrm */ + 0x1b7f, /* VGF2P8MULBrr */ +/* Table11251 */ + 0xbea, /* VAESIMCrm */ + 0xbeb, /* VAESIMCrr */ +/* Table11253 */ + 0xbe8, /* VAESENCrm */ + 0xbe9, /* VAESENCrr */ +/* Table11255 */ + 0xbde, /* VAESENCLASTrm */ + 0xbdf, /* VAESENCLASTrr */ +/* Table11257 */ + 0xbd4, /* VAESDECrm */ + 0xbd5, /* VAESDECrr */ +/* Table11259 */ + 0xbca, /* VAESDECLASTrm */ + 0xbcb, /* VAESDECLASTrr */ +/* Table11261 */ + 0xa2b, /* SHLX32rm */ + 0xa2c, /* SHLX32rr */ +/* Table11263 */ + 0x141, /* ANDN64rm */ + 0x142, /* ANDN64rr */ +/* Table11265 */ + 0x0, /* */ + 0x183, /* BLSR64rm */ + 0x17f, /* BLSMSK64rm */ + 0x177, /* BLSI64rm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x184, /* BLSR64rr */ + 0x180, /* BLSMSK64rr */ + 0x178, /* BLSI64rr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table11281 */ + 0x1de, /* BZHI64rm */ + 0x1df, /* BZHI64rr */ +/* Table11283 */ + 0x14f, /* BEXTR64rm */ + 0x150, /* BEXTR64rr */ +/* Table11285 */ + 0x7ac, /* PEXT64rm */ + 0x7ad, /* PEXT64rr */ +/* Table11287 */ + 0x9a9, /* SARX64rm */ + 0x9aa, /* SARX64rr */ +/* Table11289 */ + 0x7a8, /* PDEP64rm */ + 0x7a9, /* PDEP64rr */ +/* Table11291 */ + 0x6e3, /* MULX64rm */ + 0x6e4, /* MULX64rr */ +/* Table11293 */ + 0xa55, /* SHRX64rm */ + 0xa56, /* SHRX64rr */ +/* Table11295 */ + 0x3425, /* VPSRLVQrm */ + 0x3426, /* VPSRLVQrr */ +/* Table11297 */ + 0x3267, /* VPSLLVQrm */ + 0x3268, /* VPSLLVQrr */ +/* Table11299 */ + 0x29b2, /* VPMASKMOVQrm */ + 0x0, /* */ +/* Table11301 */ + 0x29b1, /* VPMASKMOVQmr */ + 0x0, /* */ +/* Table11303 */ + 0x28a8, /* VPGATHERDQrm */ + 0x0, /* */ +/* Table11305 */ + 0x28b2, /* VPGATHERQQrm */ + 0x0, /* */ +/* Table11307 */ + 0x1a78, /* VGATHERDPDrm */ + 0x0, /* */ +/* Table11309 */ + 0x1a8a, /* VGATHERQPDrm */ + 0x0, /* */ +/* Table11311 */ + 0x14c0, /* VFMADDSUB132PDm */ + 0x14c1, /* VFMADDSUB132PDr */ +/* Table11313 */ + 0x16c8, /* VFMSUBADD132PDm */ + 0x16c9, /* VFMSUBADD132PDr */ +/* Table11315 */ + 0x1374, /* VFMADD132PDm */ + 0x1375, /* VFMADD132PDr */ +/* Table11317 */ + 0x13a4, /* VFMADD132SDm */ + 0x13a6, /* VFMADD132SDr */ +/* Table11319 */ + 0x159c, /* VFMSUB132PDm */ + 0x159d, /* VFMSUB132PDr */ +/* Table11321 */ + 0x15cc, /* VFMSUB132SDm */ + 0x15ce, /* VFMSUB132SDr */ +/* Table11323 */ + 0x17c4, /* VFNMADD132PDm */ + 0x17c5, /* VFNMADD132PDr */ +/* Table11325 */ + 0x17f4, /* VFNMADD132SDm */ + 0x17f6, /* VFNMADD132SDr */ +/* Table11327 */ + 0x1910, /* VFNMSUB132PDm */ + 0x1911, /* VFNMSUB132PDr */ +/* Table11329 */ + 0x1940, /* VFNMSUB132SDm */ + 0x1942, /* VFNMSUB132SDr */ +/* Table11331 */ + 0x1504, /* VFMADDSUB213PDm */ + 0x1505, /* VFMADDSUB213PDr */ +/* Table11333 */ + 0x170c, /* VFMSUBADD213PDm */ + 0x170d, /* VFMSUBADD213PDr */ +/* Table11335 */ + 0x13d8, /* VFMADD213PDm */ + 0x13d9, /* VFMADD213PDr */ +/* Table11337 */ + 0x1408, /* VFMADD213SDm */ + 0x140a, /* VFMADD213SDr */ +/* Table11339 */ + 0x1600, /* VFMSUB213PDm */ + 0x1601, /* VFMSUB213PDr */ +/* Table11341 */ + 0x1630, /* VFMSUB213SDm */ + 0x1632, /* VFMSUB213SDr */ +/* Table11343 */ + 0x1828, /* VFNMADD213PDm */ + 0x1829, /* VFNMADD213PDr */ +/* Table11345 */ + 0x1858, /* VFNMADD213SDm */ + 0x185a, /* VFNMADD213SDr */ +/* Table11347 */ + 0x1974, /* VFNMSUB213PDm */ + 0x1975, /* VFNMSUB213PDr */ +/* Table11349 */ + 0x19a4, /* VFNMSUB213SDm */ + 0x19a6, /* VFNMSUB213SDr */ +/* Table11351 */ + 0x1548, /* VFMADDSUB231PDm */ + 0x1549, /* VFMADDSUB231PDr */ +/* Table11353 */ + 0x1750, /* VFMSUBADD231PDm */ + 0x1751, /* VFMSUBADD231PDr */ +/* Table11355 */ + 0x143c, /* VFMADD231PDm */ + 0x143d, /* VFMADD231PDr */ +/* Table11357 */ + 0x146c, /* VFMADD231SDm */ + 0x146e, /* VFMADD231SDr */ +/* Table11359 */ + 0x1664, /* VFMSUB231PDm */ + 0x1665, /* VFMSUB231PDr */ +/* Table11361 */ + 0x1694, /* VFMSUB231SDm */ + 0x1696, /* VFMSUB231SDr */ +/* Table11363 */ + 0x188c, /* VFNMADD231PDm */ + 0x188d, /* VFNMADD231PDr */ +/* Table11365 */ + 0x18bc, /* VFNMADD231SDm */ + 0x18be, /* VFNMADD231SDr */ +/* Table11367 */ + 0x19d8, /* VFNMSUB231PDm */ + 0x19d9, /* VFNMSUB231PDr */ +/* Table11369 */ + 0x1a08, /* VFNMSUB231SDm */ + 0x1a0a, /* VFNMSUB231SDr */ +/* Table11371 */ + 0xa2d, /* SHLX64rm */ + 0xa2e, /* SHLX64rr */ +/* Table11373 */ + 0x3150, /* VPSHUFBYrm */ + 0x3151, /* VPSHUFBYrr */ +/* Table11375 */ + 0x28d3, /* VPHADDWYrm */ + 0x28d4, /* VPHADDWYrr */ +/* Table11377 */ + 0x28bb, /* VPHADDDYrm */ + 0x28bc, /* VPHADDDYrr */ +/* Table11379 */ + 0x28bf, /* VPHADDSWYrm */ + 0x28c0, /* VPHADDSWYrr */ +/* Table11381 */ + 0x297f, /* VPMADDUBSWYrm */ + 0x2980, /* VPMADDUBSWYrr */ +/* Table11383 */ + 0x28e7, /* VPHSUBWYrm */ + 0x28e8, /* VPHSUBWYrr */ +/* Table11385 */ + 0x28dd, /* VPHSUBDYrm */ + 0x28de, /* VPHSUBDYrr */ +/* Table11387 */ + 0x28e1, /* VPHSUBSWYrm */ + 0x28e2, /* VPHSUBSWYrr */ +/* Table11389 */ + 0x31b1, /* VPSIGNBYrm */ + 0x31b2, /* VPSIGNBYrr */ +/* Table11391 */ + 0x31b9, /* VPSIGNWYrm */ + 0x31ba, /* VPSIGNWYrr */ +/* Table11393 */ + 0x31b5, /* VPSIGNDYrm */ + 0x31b6, /* VPSIGNDYrr */ +/* Table11395 */ + 0x2d9a, /* VPMULHRSWYrm */ + 0x2d9b, /* VPMULHRSWYrr */ +/* Table11397 */ + 0x2707, /* VPERMILPSYrm */ + 0x2708, /* VPERMILPSYrr */ +/* Table11399 */ + 0x26c9, /* VPERMILPDYrm */ + 0x26ca, /* VPERMILPDYrr */ +/* Table11401 */ + 0x3a7c, /* VTESTPSYrm */ + 0x3a7d, /* VTESTPSYrr */ +/* Table11403 */ + 0x3a78, /* VTESTPDYrm */ + 0x3a79, /* VTESTPDYrr */ +/* Table11405 */ + 0xee5, /* VCVTPH2PSYrm */ + 0xee6, /* VCVTPH2PSYrr */ +/* Table11407 */ + 0x2769, /* VPERMPSYrm */ + 0x276a, /* VPERMPSYrr */ +/* Table11409 */ + 0x35d3, /* VPTESTYrm */ + 0x35d4, /* VPTESTYrr */ +/* Table11411 */ + 0xd38, /* VBROADCASTSSYrm */ + 0xd39, /* VBROADCASTSSYrr */ +/* Table11413 */ + 0xd2a, /* VBROADCASTSDYrm */ + 0xd2b, /* VBROADCASTSDYrr */ +/* Table11415 */ + 0xce6, /* VBROADCASTF128 */ + 0x0, /* */ +/* Table11417 */ + 0x202d, /* VPABSBYrm */ + 0x202e, /* VPABSBYrr */ +/* Table11419 */ + 0x207d, /* VPABSWYrm */ + 0x207e, /* VPABSWYrr */ +/* Table11421 */ + 0x2043, /* VPABSDYrm */ + 0x2044, /* VPABSDYrr */ +/* Table11423 */ + 0x2c33, /* VPMOVSXBWYrm */ + 0x2c34, /* VPMOVSXBWYrr */ +/* Table11425 */ + 0x2c07, /* VPMOVSXBDYrm */ + 0x2c08, /* VPMOVSXBDYrr */ +/* Table11427 */ + 0x2c1d, /* VPMOVSXBQYrm */ + 0x2c1e, /* VPMOVSXBQYrr */ +/* Table11429 */ + 0x2c5f, /* VPMOVSXWDYrm */ + 0x2c60, /* VPMOVSXWDYrr */ +/* Table11431 */ + 0x2c75, /* VPMOVSXWQYrm */ + 0x2c76, /* VPMOVSXWQYrr */ +/* Table11433 */ + 0x2c49, /* VPMOVSXDQYrm */ + 0x2c4a, /* VPMOVSXDQYrr */ +/* Table11435 */ + 0x2d7b, /* VPMULDQYrm */ + 0x2d7c, /* VPMULDQYrr */ +/* Table11437 */ + 0x23d1, /* VPCMPEQQYrm */ + 0x23d2, /* VPCMPEQQYrr */ +/* Table11439 */ + 0x1eaa, /* VMOVNTDQAYrm */ + 0x0, /* */ +/* Table11441 */ + 0x20c8, /* VPACKUSDWYrm */ + 0x20c9, /* VPACKUSDWYrr */ +/* Table11443 */ + 0x1bea, /* VMASKMOVPSYrm */ + 0x0, /* */ +/* Table11445 */ + 0x1be6, /* VMASKMOVPDYrm */ + 0x0, /* */ +/* Table11447 */ + 0x1be9, /* VMASKMOVPSYmr */ + 0x0, /* */ +/* Table11449 */ + 0x1be5, /* VMASKMOVPDYmr */ + 0x0, /* */ +/* Table11451 */ + 0x2d23, /* VPMOVZXBWYrm */ + 0x2d24, /* VPMOVZXBWYrr */ +/* Table11453 */ + 0x2cf7, /* VPMOVZXBDYrm */ + 0x2cf8, /* VPMOVZXBDYrr */ +/* Table11455 */ + 0x2d0d, /* VPMOVZXBQYrm */ + 0x2d0e, /* VPMOVZXBQYrr */ +/* Table11457 */ + 0x2d4f, /* VPMOVZXWDYrm */ + 0x2d50, /* VPMOVZXWDYrr */ +/* Table11459 */ + 0x2d65, /* VPMOVZXWQYrm */ + 0x2d66, /* VPMOVZXWQYrr */ +/* Table11461 */ + 0x2d39, /* VPMOVZXDQYrm */ + 0x2d3a, /* VPMOVZXDQYrr */ +/* Table11463 */ + 0x2613, /* VPERMDYrm */ + 0x2614, /* VPERMDYrr */ +/* Table11465 */ + 0x2421, /* VPCMPGTQYrm */ + 0x2422, /* VPCMPGTQYrr */ +/* Table11467 */ + 0x2a7f, /* VPMINSBYrm */ + 0x2a80, /* VPMINSBYrr */ +/* Table11469 */ + 0x2a95, /* VPMINSDYrm */ + 0x2a96, /* VPMINSDYrr */ +/* Table11471 */ + 0x2b35, /* VPMINUWYrm */ + 0x2b36, /* VPMINUWYrr */ +/* Table11473 */ + 0x2afb, /* VPMINUDYrm */ + 0x2afc, /* VPMINUDYrr */ +/* Table11475 */ + 0x29b3, /* VPMAXSBYrm */ + 0x29b4, /* VPMAXSBYrr */ +/* Table11477 */ + 0x29c9, /* VPMAXSDYrm */ + 0x29ca, /* VPMAXSDYrr */ +/* Table11479 */ + 0x2a69, /* VPMAXUWYrm */ + 0x2a6a, /* VPMAXUWYrr */ +/* Table11481 */ + 0x2a2f, /* VPMAXUDYrm */ + 0x2a30, /* VPMAXUDYrr */ +/* Table11483 */ + 0x2ddc, /* VPMULLDYrm */ + 0x2ddd, /* VPMULLDYrr */ +/* Table11485 */ + 0x33e9, /* VPSRLVDYrm */ + 0x33ea, /* VPSRLVDYrr */ +/* Table11487 */ + 0x3305, /* VPSRAVDYrm */ + 0x3306, /* VPSRAVDYrr */ +/* Table11489 */ + 0x322b, /* VPSLLVDYrm */ + 0x322c, /* VPSLLVDYrr */ +/* Table11491 */ + 0x22fa, /* VPBROADCASTDYrm */ + 0x22fb, /* VPBROADCASTDYrr */ +/* Table11493 */ + 0x231f, /* VPBROADCASTQYrm */ + 0x2320, /* VPBROADCASTQYrr */ +/* Table11495 */ + 0xd05, /* VBROADCASTI128 */ + 0x0, /* */ +/* Table11497 */ + 0x22db, /* VPBROADCASTBYrm */ + 0x22dc, /* VPBROADCASTBYrr */ +/* Table11499 */ + 0x233e, /* VPBROADCASTWYrm */ + 0x233f, /* VPBROADCASTWYrr */ +/* Table11501 */ + 0x29ac, /* VPMASKMOVDYrm */ + 0x0, /* */ +/* Table11503 */ + 0x29ab, /* VPMASKMOVDYmr */ + 0x0, /* */ +/* Table11505 */ + 0x289f, /* VPGATHERDDYrm */ + 0x0, /* */ +/* Table11507 */ + 0x28a9, /* VPGATHERQDYrm */ + 0x0, /* */ +/* Table11509 */ + 0x1a79, /* VGATHERDPSYrm */ + 0x0, /* */ +/* Table11511 */ + 0x1a8b, /* VGATHERQPSYrm */ + 0x0, /* */ +/* Table11513 */ + 0x14c2, /* VFMADDSUB132PSYm */ + 0x14c3, /* VFMADDSUB132PSYr */ +/* Table11515 */ + 0x16ca, /* VFMSUBADD132PSYm */ + 0x16cb, /* VFMSUBADD132PSYr */ +/* Table11517 */ + 0x1376, /* VFMADD132PSYm */ + 0x1377, /* VFMADD132PSYr */ +/* Table11519 */ + 0x159e, /* VFMSUB132PSYm */ + 0x159f, /* VFMSUB132PSYr */ +/* Table11521 */ + 0x17c6, /* VFNMADD132PSYm */ + 0x17c7, /* VFNMADD132PSYr */ +/* Table11523 */ + 0x1912, /* VFNMSUB132PSYm */ + 0x1913, /* VFNMSUB132PSYr */ +/* Table11525 */ + 0x1506, /* VFMADDSUB213PSYm */ + 0x1507, /* VFMADDSUB213PSYr */ +/* Table11527 */ + 0x170e, /* VFMSUBADD213PSYm */ + 0x170f, /* VFMSUBADD213PSYr */ +/* Table11529 */ + 0x13da, /* VFMADD213PSYm */ + 0x13db, /* VFMADD213PSYr */ +/* Table11531 */ + 0x1602, /* VFMSUB213PSYm */ + 0x1603, /* VFMSUB213PSYr */ +/* Table11533 */ + 0x182a, /* VFNMADD213PSYm */ + 0x182b, /* VFNMADD213PSYr */ +/* Table11535 */ + 0x1976, /* VFNMSUB213PSYm */ + 0x1977, /* VFNMSUB213PSYr */ +/* Table11537 */ + 0x154a, /* VFMADDSUB231PSYm */ + 0x154b, /* VFMADDSUB231PSYr */ +/* Table11539 */ + 0x1752, /* VFMSUBADD231PSYm */ + 0x1753, /* VFMSUBADD231PSYr */ +/* Table11541 */ + 0x143e, /* VFMADD231PSYm */ + 0x143f, /* VFMADD231PSYr */ +/* Table11543 */ + 0x1666, /* VFMSUB231PSYm */ + 0x1667, /* VFMSUB231PSYr */ +/* Table11545 */ + 0x188e, /* VFNMADD231PSYm */ + 0x188f, /* VFNMADD231PSYr */ +/* Table11547 */ + 0x19da, /* VFNMSUB231PSYm */ + 0x19db, /* VFNMSUB231PSYr */ +/* Table11549 */ + 0x1b6a, /* VGF2P8MULBYrm */ + 0x1b6b, /* VGF2P8MULBYrr */ +/* Table11551 */ + 0xbe0, /* VAESENCYrm */ + 0xbe1, /* VAESENCYrr */ +/* Table11553 */ + 0xbd6, /* VAESENCLASTYrm */ + 0xbd7, /* VAESENCLASTYrr */ +/* Table11555 */ + 0xbcc, /* VAESDECYrm */ + 0xbcd, /* VAESDECYrr */ +/* Table11557 */ + 0xbc2, /* VAESDECLASTYrm */ + 0xbc3, /* VAESDECLASTYrr */ +/* Table11559 */ + 0x3408, /* VPSRLVQYrm */ + 0x3409, /* VPSRLVQYrr */ +/* Table11561 */ + 0x324a, /* VPSLLVQYrm */ + 0x324b, /* VPSLLVQYrr */ +/* Table11563 */ + 0x29b0, /* VPMASKMOVQYrm */ + 0x0, /* */ +/* Table11565 */ + 0x29af, /* VPMASKMOVQYmr */ + 0x0, /* */ +/* Table11567 */ + 0x28a4, /* VPGATHERDQYrm */ + 0x0, /* */ +/* Table11569 */ + 0x28ae, /* VPGATHERQQYrm */ + 0x0, /* */ +/* Table11571 */ + 0x1a74, /* VGATHERDPDYrm */ + 0x0, /* */ +/* Table11573 */ + 0x1a86, /* VGATHERQPDYrm */ + 0x0, /* */ +/* Table11575 */ + 0x14a0, /* VFMADDSUB132PDYm */ + 0x14a1, /* VFMADDSUB132PDYr */ +/* Table11577 */ + 0x16a8, /* VFMSUBADD132PDYm */ + 0x16a9, /* VFMSUBADD132PDYr */ +/* Table11579 */ + 0x1354, /* VFMADD132PDYm */ + 0x1355, /* VFMADD132PDYr */ +/* Table11581 */ + 0x157c, /* VFMSUB132PDYm */ + 0x157d, /* VFMSUB132PDYr */ +/* Table11583 */ + 0x17a4, /* VFNMADD132PDYm */ + 0x17a5, /* VFNMADD132PDYr */ +/* Table11585 */ + 0x18f0, /* VFNMSUB132PDYm */ + 0x18f1, /* VFNMSUB132PDYr */ +/* Table11587 */ + 0x14e4, /* VFMADDSUB213PDYm */ + 0x14e5, /* VFMADDSUB213PDYr */ +/* Table11589 */ + 0x16ec, /* VFMSUBADD213PDYm */ + 0x16ed, /* VFMSUBADD213PDYr */ +/* Table11591 */ + 0x13b8, /* VFMADD213PDYm */ + 0x13b9, /* VFMADD213PDYr */ +/* Table11593 */ + 0x15e0, /* VFMSUB213PDYm */ + 0x15e1, /* VFMSUB213PDYr */ +/* Table11595 */ + 0x1808, /* VFNMADD213PDYm */ + 0x1809, /* VFNMADD213PDYr */ +/* Table11597 */ + 0x1954, /* VFNMSUB213PDYm */ + 0x1955, /* VFNMSUB213PDYr */ +/* Table11599 */ + 0x1528, /* VFMADDSUB231PDYm */ + 0x1529, /* VFMADDSUB231PDYr */ +/* Table11601 */ + 0x1730, /* VFMSUBADD231PDYm */ + 0x1731, /* VFMSUBADD231PDYr */ +/* Table11603 */ + 0x141c, /* VFMADD231PDYm */ + 0x141d, /* VFMADD231PDYr */ +/* Table11605 */ + 0x1644, /* VFMSUB231PDYm */ + 0x1645, /* VFMSUB231PDYr */ +/* Table11607 */ + 0x186c, /* VFNMADD231PDYm */ + 0x186d, /* VFNMADD231PDYr */ +/* Table11609 */ + 0x19b8, /* VFNMSUB231PDYm */ + 0x19b9, /* VFNMSUB231PDYr */ +/* Table11611 */ + 0x2cd6, /* VPMOVUSWBZ128mr */ + 0x2cd8, /* VPMOVUSWBZ128rr */ +/* Table11613 */ + 0x2c8b, /* VPMOVUSDBZ128mr */ + 0x2c8d, /* VPMOVUSDBZ128rr */ +/* Table11615 */ + 0x2ca9, /* VPMOVUSQBZ128mr */ + 0x2cab, /* VPMOVUSQBZ128rr */ +/* Table11617 */ + 0x2c9a, /* VPMOVUSDWZ128mr */ + 0x2c9c, /* VPMOVUSDWZ128rr */ +/* Table11619 */ + 0x2cc7, /* VPMOVUSQWZ128mr */ + 0x2cc9, /* VPMOVUSQWZ128rr */ +/* Table11621 */ + 0x2cb8, /* VPMOVUSQDZ128mr */ + 0x2cba, /* VPMOVUSQDZ128rr */ +/* Table11623 */ + 0x2bf8, /* VPMOVSWBZ128mr */ + 0x2bfa, /* VPMOVSWBZ128rr */ +/* Table11625 */ + 0x2bad, /* VPMOVSDBZ128mr */ + 0x2baf, /* VPMOVSDBZ128rr */ +/* Table11627 */ + 0x2bcb, /* VPMOVSQBZ128mr */ + 0x2bcd, /* VPMOVSQBZ128rr */ +/* Table11629 */ + 0x2bbc, /* VPMOVSDWZ128mr */ + 0x2bbe, /* VPMOVSDWZ128rr */ +/* Table11631 */ + 0x2be9, /* VPMOVSQWZ128mr */ + 0x2beb, /* VPMOVSQWZ128rr */ +/* Table11633 */ + 0x2bda, /* VPMOVSQDZ128mr */ + 0x2bdc, /* VPMOVSQDZ128rr */ +/* Table11635 */ + 0x3597, /* VPTESTNMBZ128rm */ + 0x3599, /* VPTESTNMBZ128rr */ +/* Table11637 */ + 0x35a3, /* VPTESTNMDZ128rm */ + 0x35a7, /* VPTESTNMDZ128rr */ +/* Table11639 */ + 0x0, /* */ + 0x2b6f, /* VPMOVM2BZ128rr */ +/* Table11641 */ + 0x0, /* */ + 0x2b4b, /* VPMOVB2MZ128rr */ +/* Table11643 */ + 0x2ce8, /* VPMOVWBZ128mr */ + 0x2cea, /* VPMOVWBZ128rr */ +/* Table11645 */ + 0x2b51, /* VPMOVDBZ128mr */ + 0x2b53, /* VPMOVDBZ128rr */ +/* Table11647 */ + 0x2b80, /* VPMOVQBZ128mr */ + 0x2b82, /* VPMOVQBZ128rr */ +/* Table11649 */ + 0x2b60, /* VPMOVDWZ128mr */ + 0x2b62, /* VPMOVDWZ128rr */ +/* Table11651 */ + 0x2b9e, /* VPMOVQWZ128mr */ + 0x2ba0, /* VPMOVQWZ128rr */ +/* Table11653 */ + 0x2b8f, /* VPMOVQDZ128mr */ + 0x2b91, /* VPMOVQDZ128rr */ +/* Table11655 */ + 0x0, /* */ + 0x2b72, /* VPMOVM2DZ128rr */ +/* Table11657 */ + 0x0, /* */ + 0x2b4e, /* VPMOVD2MZ128rr */ +/* Table11659 */ + 0x0, /* */ + 0x231c, /* VPBROADCASTMW2DZ128rr */ +/* Table11661 */ + 0xb4f, /* V4FMADDSSrm */ + 0x0, /* */ +/* Table11663 */ + 0xb55, /* V4FNMADDSSrm */ + 0x0, /* */ +/* Table11665 */ + 0x3152, /* VPSHUFBZ128rm */ + 0x3155, /* VPSHUFBZ128rr */ +/* Table11667 */ + 0x2981, /* VPMADDUBSWZ128rm */ + 0x2984, /* VPMADDUBSWZ128rr */ +/* Table11669 */ + 0x2d9c, /* VPMULHRSWZ128rm */ + 0x2d9f, /* VPMULHRSWZ128rr */ +/* Table11671 */ + 0x2712, /* VPERMILPSZ128rm */ + 0x2718, /* VPERMILPSZ128rr */ +/* Table11673 */ + 0xee7, /* VCVTPH2PSZ128rm */ + 0xeea, /* VCVTPH2PSZ128rr */ +/* Table11675 */ + 0x2fa0, /* VPRORVDZ128rm */ + 0x2fa6, /* VPRORVDZ128rr */ +/* Table11677 */ + 0x2f34, /* VPROLVDZ128rm */ + 0x2f3a, /* VPROLVDZ128rr */ +/* Table11679 */ + 0xd3a, /* VBROADCASTSSZ128m */ + 0xd3d, /* VBROADCASTSSZ128r */ +/* Table11681 */ + 0x202f, /* VPABSBZ128rm */ + 0x2032, /* VPABSBZ128rr */ +/* Table11683 */ + 0x207f, /* VPABSWZ128rm */ + 0x2082, /* VPABSWZ128rr */ +/* Table11685 */ + 0x2045, /* VPABSDZ128rm */ + 0x204b, /* VPABSDZ128rr */ +/* Table11687 */ + 0x2c35, /* VPMOVSXBWZ128rm */ + 0x2c38, /* VPMOVSXBWZ128rr */ +/* Table11689 */ + 0x2c09, /* VPMOVSXBDZ128rm */ + 0x2c0c, /* VPMOVSXBDZ128rr */ +/* Table11691 */ + 0x2c1f, /* VPMOVSXBQZ128rm */ + 0x2c22, /* VPMOVSXBQZ128rr */ +/* Table11693 */ + 0x2c61, /* VPMOVSXWDZ128rm */ + 0x2c64, /* VPMOVSXWDZ128rr */ +/* Table11695 */ + 0x2c77, /* VPMOVSXWQZ128rm */ + 0x2c7a, /* VPMOVSXWQZ128rr */ +/* Table11697 */ + 0x2c4b, /* VPMOVSXDQZ128rm */ + 0x2c4e, /* VPMOVSXDQZ128rr */ +/* Table11699 */ + 0x355b, /* VPTESTMBZ128rm */ + 0x355d, /* VPTESTMBZ128rr */ +/* Table11701 */ + 0x3567, /* VPTESTMDZ128rm */ + 0x356b, /* VPTESTMDZ128rr */ +/* Table11703 */ + 0x1eab, /* VMOVNTDQAZ128rm */ + 0x0, /* */ +/* Table11705 */ + 0x20ca, /* VPACKUSDWZ128rm */ + 0x20d0, /* VPACKUSDWZ128rr */ +/* Table11707 */ + 0x38e9, /* VSCALEFPSZ128rm */ + 0x38ef, /* VSCALEFPSZ128rr */ +/* Table11709 */ + 0x3910, /* VSCALEFSSZrm */ + 0x3913, /* VSCALEFSSZrr */ +/* Table11711 */ + 0x2d25, /* VPMOVZXBWZ128rm */ + 0x2d28, /* VPMOVZXBWZ128rr */ +/* Table11713 */ + 0x2cf9, /* VPMOVZXBDZ128rm */ + 0x2cfc, /* VPMOVZXBDZ128rr */ +/* Table11715 */ + 0x2d0f, /* VPMOVZXBQZ128rm */ + 0x2d12, /* VPMOVZXBQZ128rr */ +/* Table11717 */ + 0x2d51, /* VPMOVZXWDZ128rm */ + 0x2d54, /* VPMOVZXWDZ128rr */ +/* Table11719 */ + 0x2d67, /* VPMOVZXWQZ128rm */ + 0x2d6a, /* VPMOVZXWQZ128rr */ +/* Table11721 */ + 0x2d3b, /* VPMOVZXDQZ128rm */ + 0x2d3e, /* VPMOVZXDQZ128rr */ +/* Table11723 */ + 0x2a81, /* VPMINSBZ128rm */ + 0x2a84, /* VPMINSBZ128rr */ +/* Table11725 */ + 0x2a97, /* VPMINSDZ128rm */ + 0x2a9d, /* VPMINSDZ128rr */ +/* Table11727 */ + 0x2b37, /* VPMINUWZ128rm */ + 0x2b3a, /* VPMINUWZ128rr */ +/* Table11729 */ + 0x2afd, /* VPMINUDZ128rm */ + 0x2b03, /* VPMINUDZ128rr */ +/* Table11731 */ + 0x29b5, /* VPMAXSBZ128rm */ + 0x29b8, /* VPMAXSBZ128rr */ +/* Table11733 */ + 0x29cb, /* VPMAXSDZ128rm */ + 0x29d1, /* VPMAXSDZ128rr */ +/* Table11735 */ + 0x2a6b, /* VPMAXUWZ128rm */ + 0x2a6e, /* VPMAXUWZ128rr */ +/* Table11737 */ + 0x2a31, /* VPMAXUDZ128rm */ + 0x2a37, /* VPMAXUDZ128rr */ +/* Table11739 */ + 0x2dde, /* VPMULLDZ128rm */ + 0x2de4, /* VPMULLDZ128rr */ +/* Table11741 */ + 0x1aae, /* VGETEXPPSZ128m */ + 0x1ab4, /* VGETEXPPSZ128r */ +/* Table11743 */ + 0x1ad5, /* VGETEXPSSZm */ + 0x1ad8, /* VGETEXPSSZr */ +/* Table11745 */ + 0x28fb, /* VPLZCNTDZ128rm */ + 0x2901, /* VPLZCNTDZ128rr */ +/* Table11747 */ + 0x33eb, /* VPSRLVDZ128rm */ + 0x33f1, /* VPSRLVDZ128rr */ +/* Table11749 */ + 0x3307, /* VPSRAVDZ128rm */ + 0x330d, /* VPSRAVDZ128rr */ +/* Table11751 */ + 0x322d, /* VPSLLVDZ128rm */ + 0x3233, /* VPSLLVDZ128rr */ +/* Table11753 */ + 0x374e, /* VRCP14PSZ128m */ + 0x3754, /* VRCP14PSZ128r */ +/* Table11755 */ + 0x376f, /* VRCP14SSZrm */ + 0x3772, /* VRCP14SSZrr */ +/* Table11757 */ + 0x3872, /* VRSQRT14PSZ128m */ + 0x3878, /* VRSQRT14PSZ128r */ +/* Table11759 */ + 0x3893, /* VRSQRT14SSZrm */ + 0x3896, /* VRSQRT14SSZrr */ +/* Table11761 */ + 0x25ac, /* VPDPBUSDZ128m */ + 0x25b2, /* VPDPBUSDZ128r */ +/* Table11763 */ + 0x2591, /* VPDPBUSDSZ128m */ + 0x2597, /* VPDPBUSDSZ128r */ +/* Table11765 */ + 0x25e2, /* VPDPWSSDZ128m */ + 0x25e8, /* VPDPWSSDZ128r */ +/* Table11767 */ + 0x25c7, /* VPDPWSSDSZ128m */ + 0x25cd, /* VPDPWSSDSZ128r */ +/* Table11769 */ + 0x2e66, /* VPOPCNTBZ128rm */ + 0x2e69, /* VPOPCNTBZ128rr */ +/* Table11771 */ + 0x2e78, /* VPOPCNTDZ128rm */ + 0x2e7e, /* VPOPCNTDZ128rr */ +/* Table11773 */ + 0x22fc, /* VPBROADCASTDZ128m */ + 0x22ff, /* VPBROADCASTDZ128r */ +/* Table11775 */ + 0xd06, /* VBROADCASTI32X2Z128m */ + 0xd09, /* VBROADCASTI32X2Z128r */ +/* Table11777 */ + 0x2845, /* VPEXPANDBZ128rm */ + 0x2848, /* VPEXPANDBZ128rr */ +/* Table11779 */ + 0x2507, /* VPCOMPRESSBZ128mr */ + 0x2509, /* VPCOMPRESSBZ128rr */ +/* Table11781 */ + 0x228b, /* VPBLENDMDZ128rm */ + 0x2291, /* VPBLENDMDZ128rr */ +/* Table11783 */ + 0xcbb, /* VBLENDMPSZ128rm */ + 0xcc1, /* VBLENDMPSZ128rr */ +/* Table11785 */ + 0x2279, /* VPBLENDMBZ128rm */ + 0x227c, /* VPBLENDMBZ128rr */ +/* Table11787 */ + 0x304e, /* VPSHLDVDZ128m */ + 0x3054, /* VPSHLDVDZ128r */ +/* Table11789 */ + 0x30ea, /* VPSHRDVDZ128m */ + 0x30f0, /* VPSHRDVDZ128r */ +/* Table11791 */ + 0x2627, /* VPERMI2B128rm */ + 0x262a, /* VPERMI2B128rr */ +/* Table11793 */ + 0x2639, /* VPERMI2D128rm */ + 0x263f, /* VPERMI2D128rr */ +/* Table11795 */ + 0x266f, /* VPERMI2PS128rm */ + 0x2675, /* VPERMI2PS128rr */ +/* Table11797 */ + 0x22dd, /* VPBROADCASTBZ128m */ + 0x22e0, /* VPBROADCASTBZ128r */ +/* Table11799 */ + 0x2340, /* VPBROADCASTWZ128m */ + 0x2343, /* VPBROADCASTWZ128r */ +/* Table11801 */ + 0x0, /* */ + 0x22ef, /* VPBROADCASTBrZ128r */ +/* Table11803 */ + 0x0, /* */ + 0x2352, /* VPBROADCASTWrZ128r */ +/* Table11805 */ + 0x0, /* */ + 0x230e, /* VPBROADCASTDrZ128r */ +/* Table11807 */ + 0x27a3, /* VPERMT2B128rm */ + 0x27a6, /* VPERMT2B128rr */ +/* Table11809 */ + 0x27b5, /* VPERMT2D128rm */ + 0x27bb, /* VPERMT2D128rr */ +/* Table11811 */ + 0x27eb, /* VPERMT2PS128rm */ + 0x27f1, /* VPERMT2PS128rr */ +/* Table11813 */ + 0x12b0, /* VEXPANDPSZ128rm */ + 0x12b3, /* VEXPANDPSZ128rr */ +/* Table11815 */ + 0x2857, /* VPEXPANDDZ128rm */ + 0x285a, /* VPEXPANDDZ128rr */ +/* Table11817 */ + 0xdf7, /* VCOMPRESSPSZ128mr */ + 0xdf9, /* VCOMPRESSPSZ128rr */ +/* Table11819 */ + 0x2516, /* VPCOMPRESSDZ128mr */ + 0x2518, /* VPCOMPRESSDZ128rr */ +/* Table11821 */ + 0x2601, /* VPERMBZ128rm */ + 0x2604, /* VPERMBZ128rr */ +/* Table11823 */ + 0x3144, /* VPSHUFBITQMBZ128rm */ + 0x3146, /* VPSHUFBITQMBZ128rr */ +/* Table11825 */ + 0x14c4, /* VFMADDSUB132PSZ128m */ + 0x14ca, /* VFMADDSUB132PSZ128r */ +/* Table11827 */ + 0x16cc, /* VFMSUBADD132PSZ128m */ + 0x16d2, /* VFMSUBADD132PSZ128r */ +/* Table11829 */ + 0x1378, /* VFMADD132PSZ128m */ + 0x137e, /* VFMADD132PSZ128r */ +/* Table11831 */ + 0x13a9, /* VFMADD132SSZm_Int */ + 0x13ad, /* VFMADD132SSZr_Int */ +/* Table11833 */ + 0x15a0, /* VFMSUB132PSZ128m */ + 0x15a6, /* VFMSUB132PSZ128r */ +/* Table11835 */ + 0x15d1, /* VFMSUB132SSZm_Int */ + 0x15d5, /* VFMSUB132SSZr_Int */ +/* Table11837 */ + 0x17c8, /* VFNMADD132PSZ128m */ + 0x17ce, /* VFNMADD132PSZ128r */ +/* Table11839 */ + 0x17f9, /* VFNMADD132SSZm_Int */ + 0x17fd, /* VFNMADD132SSZr_Int */ +/* Table11841 */ + 0x1914, /* VFNMSUB132PSZ128m */ + 0x191a, /* VFNMSUB132PSZ128r */ +/* Table11843 */ + 0x1945, /* VFNMSUB132SSZm_Int */ + 0x1949, /* VFNMSUB132SSZr_Int */ +/* Table11845 */ + 0x1508, /* VFMADDSUB213PSZ128m */ + 0x150e, /* VFMADDSUB213PSZ128r */ +/* Table11847 */ + 0x1710, /* VFMSUBADD213PSZ128m */ + 0x1716, /* VFMSUBADD213PSZ128r */ +/* Table11849 */ + 0x13dc, /* VFMADD213PSZ128m */ + 0x13e2, /* VFMADD213PSZ128r */ +/* Table11851 */ + 0x140d, /* VFMADD213SSZm_Int */ + 0x1411, /* VFMADD213SSZr_Int */ +/* Table11853 */ + 0x1604, /* VFMSUB213PSZ128m */ + 0x160a, /* VFMSUB213PSZ128r */ +/* Table11855 */ + 0x1635, /* VFMSUB213SSZm_Int */ + 0x1639, /* VFMSUB213SSZr_Int */ +/* Table11857 */ + 0x182c, /* VFNMADD213PSZ128m */ + 0x1832, /* VFNMADD213PSZ128r */ +/* Table11859 */ + 0x185d, /* VFNMADD213SSZm_Int */ + 0x1861, /* VFNMADD213SSZr_Int */ +/* Table11861 */ + 0x1978, /* VFNMSUB213PSZ128m */ + 0x197e, /* VFNMSUB213PSZ128r */ +/* Table11863 */ + 0x19a9, /* VFNMSUB213SSZm_Int */ + 0x19ad, /* VFNMSUB213SSZr_Int */ +/* Table11865 */ + 0x154c, /* VFMADDSUB231PSZ128m */ + 0x1552, /* VFMADDSUB231PSZ128r */ +/* Table11867 */ + 0x1754, /* VFMSUBADD231PSZ128m */ + 0x175a, /* VFMSUBADD231PSZ128r */ +/* Table11869 */ + 0x1440, /* VFMADD231PSZ128m */ + 0x1446, /* VFMADD231PSZ128r */ +/* Table11871 */ + 0x1471, /* VFMADD231SSZm_Int */ + 0x1475, /* VFMADD231SSZr_Int */ +/* Table11873 */ + 0x1668, /* VFMSUB231PSZ128m */ + 0x166e, /* VFMSUB231PSZ128r */ +/* Table11875 */ + 0x1699, /* VFMSUB231SSZm_Int */ + 0x169d, /* VFMSUB231SSZr_Int */ +/* Table11877 */ + 0x1890, /* VFNMADD231PSZ128m */ + 0x1896, /* VFNMADD231PSZ128r */ +/* Table11879 */ + 0x18c1, /* VFNMADD231SSZm_Int */ + 0x18c5, /* VFNMADD231SSZr_Int */ +/* Table11881 */ + 0x19dc, /* VFNMSUB231PSZ128m */ + 0x19e2, /* VFNMSUB231PSZ128r */ +/* Table11883 */ + 0x1a0d, /* VFNMSUB231SSZm_Int */ + 0x1a11, /* VFNMSUB231SSZr_Int */ +/* Table11885 */ + 0x255b, /* VPCONFLICTDZ128rm */ + 0x2561, /* VPCONFLICTDZ128rr */ +/* Table11887 */ + 0x3796, /* VRCP28SSZm */ + 0x3799, /* VRCP28SSZr */ +/* Table11889 */ + 0x38ba, /* VRSQRT28SSZm */ + 0x38bd, /* VRSQRT28SSZr */ +/* Table11891 */ + 0x1b6c, /* VGF2P8MULBZ128rm */ + 0x1b6f, /* VGF2P8MULBZ128rr */ +/* Table11893 */ + 0xbe2, /* VAESENCZ128rm */ + 0xbe3, /* VAESENCZ128rr */ +/* Table11895 */ + 0xbd8, /* VAESENCLASTZ128rm */ + 0xbd9, /* VAESENCLASTZ128rr */ +/* Table11897 */ + 0xbce, /* VAESDECZ128rm */ + 0xbcf, /* VAESDECZ128rr */ +/* Table11899 */ + 0xbc4, /* VAESDECLASTZ128rm */ + 0xbc5, /* VAESDECLASTZ128rr */ +/* Table11901 */ + 0x35c7, /* VPTESTNMWZ128rm */ + 0x35c9, /* VPTESTNMWZ128rr */ +/* Table11903 */ + 0x35b5, /* VPTESTNMQZ128rm */ + 0x35b9, /* VPTESTNMQZ128rr */ +/* Table11905 */ + 0x0, /* */ + 0x2b78, /* VPMOVM2WZ128rr */ +/* Table11907 */ + 0x0, /* */ + 0x2ce5, /* VPMOVW2MZ128rr */ +/* Table11909 */ + 0x0, /* */ + 0x2319, /* VPBROADCASTMB2QZ128rr */ +/* Table11911 */ + 0x0, /* */ + 0x2b75, /* VPMOVM2QZ128rr */ +/* Table11913 */ + 0x0, /* */ + 0x2b7d, /* VPMOVQ2MZ128rr */ +/* Table11915 */ + 0x26d4, /* VPERMILPDZ128rm */ + 0x26da, /* VPERMILPDZ128rr */ +/* Table11917 */ + 0x3427, /* VPSRLVWZ128rm */ + 0x342a, /* VPSRLVWZ128rr */ +/* Table11919 */ + 0x333f, /* VPSRAVWZ128rm */ + 0x3342, /* VPSRAVWZ128rr */ +/* Table11921 */ + 0x3269, /* VPSLLVWZ128rm */ + 0x326c, /* VPSLLVWZ128rr */ +/* Table11923 */ + 0x2fbb, /* VPRORVQZ128rm */ + 0x2fc1, /* VPRORVQZ128rr */ +/* Table11925 */ + 0x2f4f, /* VPROLVQZ128rm */ + 0x2f55, /* VPROLVQZ128rr */ +/* Table11927 */ + 0x2062, /* VPABSQZ128rm */ + 0x2068, /* VPABSQZ128rr */ +/* Table11929 */ + 0x358b, /* VPTESTMWZ128rm */ + 0x358d, /* VPTESTMWZ128rr */ +/* Table11931 */ + 0x3579, /* VPTESTMQZ128rm */ + 0x357d, /* VPTESTMQZ128rr */ +/* Table11933 */ + 0x2d7d, /* VPMULDQZ128rm */ + 0x2d83, /* VPMULDQZ128rr */ +/* Table11935 */ + 0x23d3, /* VPCMPEQQZ128rm */ + 0x23d7, /* VPCMPEQQZ128rr */ +/* Table11937 */ + 0x38cb, /* VSCALEFPDZ128rm */ + 0x38d1, /* VSCALEFPDZ128rr */ +/* Table11939 */ + 0x3907, /* VSCALEFSDZrm */ + 0x390a, /* VSCALEFSDZrr */ +/* Table11941 */ + 0x2423, /* VPCMPGTQZ128rm */ + 0x2427, /* VPCMPGTQZ128rr */ +/* Table11943 */ + 0x2ab4, /* VPMINSQZ128rm */ + 0x2aba, /* VPMINSQZ128rr */ +/* Table11945 */ + 0x2b1a, /* VPMINUQZ128rm */ + 0x2b20, /* VPMINUQZ128rr */ +/* Table11947 */ + 0x29e8, /* VPMAXSQZ128rm */ + 0x29ee, /* VPMAXSQZ128rr */ +/* Table11949 */ + 0x2a4e, /* VPMAXUQZ128rm */ + 0x2a54, /* VPMAXUQZ128rr */ +/* Table11951 */ + 0x2dfb, /* VPMULLQZ128rm */ + 0x2e01, /* VPMULLQZ128rr */ +/* Table11953 */ + 0x1a90, /* VGETEXPPDZ128m */ + 0x1a96, /* VGETEXPPDZ128r */ +/* Table11955 */ + 0x1acc, /* VGETEXPSDZm */ + 0x1acf, /* VGETEXPSDZr */ +/* Table11957 */ + 0x2916, /* VPLZCNTQZ128rm */ + 0x291c, /* VPLZCNTQZ128rr */ +/* Table11959 */ + 0x340a, /* VPSRLVQZ128rm */ + 0x3410, /* VPSRLVQZ128rr */ +/* Table11961 */ + 0x3324, /* VPSRAVQZ128rm */ + 0x332a, /* VPSRAVQZ128rr */ +/* Table11963 */ + 0x324c, /* VPSLLVQZ128rm */ + 0x3252, /* VPSLLVQZ128rr */ +/* Table11965 */ + 0x3733, /* VRCP14PDZ128m */ + 0x3739, /* VRCP14PDZ128r */ +/* Table11967 */ + 0x3769, /* VRCP14SDZrm */ + 0x376c, /* VRCP14SDZrr */ +/* Table11969 */ + 0x3857, /* VRSQRT14PDZ128m */ + 0x385d, /* VRSQRT14PDZ128r */ +/* Table11971 */ + 0x388d, /* VRSQRT14SDZrm */ + 0x3890, /* VRSQRT14SDZrr */ +/* Table11973 */ + 0x2eae, /* VPOPCNTWZ128rm */ + 0x2eb1, /* VPOPCNTWZ128rr */ +/* Table11975 */ + 0x2e93, /* VPOPCNTQZ128rm */ + 0x2e99, /* VPOPCNTQZ128rr */ +/* Table11977 */ + 0x2321, /* VPBROADCASTQZ128m */ + 0x2324, /* VPBROADCASTQZ128r */ +/* Table11979 */ + 0x287b, /* VPEXPANDWZ128rm */ + 0x287e, /* VPEXPANDWZ128rr */ +/* Table11981 */ + 0x2534, /* VPCOMPRESSWZ128mr */ + 0x2536, /* VPCOMPRESSWZ128rr */ +/* Table11983 */ + 0x22a6, /* VPBLENDMQZ128rm */ + 0x22ac, /* VPBLENDMQZ128rr */ +/* Table11985 */ + 0xca0, /* VBLENDMPDZ128rm */ + 0xca6, /* VBLENDMPDZ128rr */ +/* Table11987 */ + 0x22c1, /* VPBLENDMWZ128rm */ + 0x22c4, /* VPBLENDMWZ128rr */ +/* Table11989 */ + 0x3084, /* VPSHLDVWZ128m */ + 0x3087, /* VPSHLDVWZ128r */ +/* Table11991 */ + 0x3069, /* VPSHLDVQZ128m */ + 0x306f, /* VPSHLDVQZ128r */ +/* Table11993 */ + 0x3120, /* VPSHRDVWZ128m */ + 0x3123, /* VPSHRDVWZ128r */ +/* Table11995 */ + 0x3105, /* VPSHRDVQZ128m */ + 0x310b, /* VPSHRDVQZ128r */ +/* Table11997 */ + 0x26a5, /* VPERMI2W128rm */ + 0x26a8, /* VPERMI2W128rr */ +/* Table11999 */ + 0x268a, /* VPERMI2Q128rm */ + 0x2690, /* VPERMI2Q128rr */ +/* Table12001 */ + 0x2654, /* VPERMI2PD128rm */ + 0x265a, /* VPERMI2PD128rr */ +/* Table12003 */ + 0x0, /* */ + 0x2333, /* VPBROADCASTQrZ128r */ +/* Table12005 */ + 0x2821, /* VPERMT2W128rm */ + 0x2824, /* VPERMT2W128rr */ +/* Table12007 */ + 0x2806, /* VPERMT2Q128rm */ + 0x280c, /* VPERMT2Q128rr */ +/* Table12009 */ + 0x27d0, /* VPERMT2PD128rm */ + 0x27d6, /* VPERMT2PD128rr */ +/* Table12011 */ + 0x2e2c, /* VPMULTISHIFTQBZ128rm */ + 0x2e32, /* VPMULTISHIFTQBZ128rr */ +/* Table12013 */ + 0x129e, /* VEXPANDPDZ128rm */ + 0x12a1, /* VEXPANDPDZ128rr */ +/* Table12015 */ + 0x2869, /* VPEXPANDQZ128rm */ + 0x286c, /* VPEXPANDQZ128rr */ +/* Table12017 */ + 0xde8, /* VCOMPRESSPDZ128mr */ + 0xdea, /* VCOMPRESSPDZ128rr */ +/* Table12019 */ + 0x2525, /* VPCOMPRESSQZ128mr */ + 0x2527, /* VPCOMPRESSQZ128rr */ +/* Table12021 */ + 0x2833, /* VPERMWZ128rm */ + 0x2836, /* VPERMWZ128rr */ +/* Table12023 */ + 0x14a2, /* VFMADDSUB132PDZ128m */ + 0x14a8, /* VFMADDSUB132PDZ128r */ +/* Table12025 */ + 0x16aa, /* VFMSUBADD132PDZ128m */ + 0x16b0, /* VFMSUBADD132PDZ128r */ +/* Table12027 */ + 0x1356, /* VFMADD132PDZ128m */ + 0x135c, /* VFMADD132PDZ128r */ +/* Table12029 */ + 0x1399, /* VFMADD132SDZm_Int */ + 0x139d, /* VFMADD132SDZr_Int */ +/* Table12031 */ + 0x157e, /* VFMSUB132PDZ128m */ + 0x1584, /* VFMSUB132PDZ128r */ +/* Table12033 */ + 0x15c1, /* VFMSUB132SDZm_Int */ + 0x15c5, /* VFMSUB132SDZr_Int */ +/* Table12035 */ + 0x17a6, /* VFNMADD132PDZ128m */ + 0x17ac, /* VFNMADD132PDZ128r */ +/* Table12037 */ + 0x17e9, /* VFNMADD132SDZm_Int */ + 0x17ed, /* VFNMADD132SDZr_Int */ +/* Table12039 */ + 0x18f2, /* VFNMSUB132PDZ128m */ + 0x18f8, /* VFNMSUB132PDZ128r */ +/* Table12041 */ + 0x1935, /* VFNMSUB132SDZm_Int */ + 0x1939, /* VFNMSUB132SDZr_Int */ +/* Table12043 */ + 0x14e6, /* VFMADDSUB213PDZ128m */ + 0x14ec, /* VFMADDSUB213PDZ128r */ +/* Table12045 */ + 0x16ee, /* VFMSUBADD213PDZ128m */ + 0x16f4, /* VFMSUBADD213PDZ128r */ +/* Table12047 */ + 0x13ba, /* VFMADD213PDZ128m */ + 0x13c0, /* VFMADD213PDZ128r */ +/* Table12049 */ + 0x13fd, /* VFMADD213SDZm_Int */ + 0x1401, /* VFMADD213SDZr_Int */ +/* Table12051 */ + 0x15e2, /* VFMSUB213PDZ128m */ + 0x15e8, /* VFMSUB213PDZ128r */ +/* Table12053 */ + 0x1625, /* VFMSUB213SDZm_Int */ + 0x1629, /* VFMSUB213SDZr_Int */ +/* Table12055 */ + 0x180a, /* VFNMADD213PDZ128m */ + 0x1810, /* VFNMADD213PDZ128r */ +/* Table12057 */ + 0x184d, /* VFNMADD213SDZm_Int */ + 0x1851, /* VFNMADD213SDZr_Int */ +/* Table12059 */ + 0x1956, /* VFNMSUB213PDZ128m */ + 0x195c, /* VFNMSUB213PDZ128r */ +/* Table12061 */ + 0x1999, /* VFNMSUB213SDZm_Int */ + 0x199d, /* VFNMSUB213SDZr_Int */ +/* Table12063 */ + 0x2964, /* VPMADD52LUQZ128m */ + 0x296a, /* VPMADD52LUQZ128r */ +/* Table12065 */ + 0x2949, /* VPMADD52HUQZ128m */ + 0x294f, /* VPMADD52HUQZ128r */ +/* Table12067 */ + 0x152a, /* VFMADDSUB231PDZ128m */ + 0x1530, /* VFMADDSUB231PDZ128r */ +/* Table12069 */ + 0x1732, /* VFMSUBADD231PDZ128m */ + 0x1738, /* VFMSUBADD231PDZ128r */ +/* Table12071 */ + 0x141e, /* VFMADD231PDZ128m */ + 0x1424, /* VFMADD231PDZ128r */ +/* Table12073 */ + 0x1461, /* VFMADD231SDZm_Int */ + 0x1465, /* VFMADD231SDZr_Int */ +/* Table12075 */ + 0x1646, /* VFMSUB231PDZ128m */ + 0x164c, /* VFMSUB231PDZ128r */ +/* Table12077 */ + 0x1689, /* VFMSUB231SDZm_Int */ + 0x168d, /* VFMSUB231SDZr_Int */ +/* Table12079 */ + 0x186e, /* VFNMADD231PDZ128m */ + 0x1874, /* VFNMADD231PDZ128r */ +/* Table12081 */ + 0x18b1, /* VFNMADD231SDZm_Int */ + 0x18b5, /* VFNMADD231SDZr_Int */ +/* Table12083 */ + 0x19ba, /* VFNMSUB231PDZ128m */ + 0x19c0, /* VFNMSUB231PDZ128r */ +/* Table12085 */ + 0x19fd, /* VFNMSUB231SDZm_Int */ + 0x1a01, /* VFNMSUB231SDZr_Int */ +/* Table12087 */ + 0x2576, /* VPCONFLICTQZ128rm */ + 0x257c, /* VPCONFLICTQZ128rr */ +/* Table12089 */ + 0x378d, /* VRCP28SDZm */ + 0x3790, /* VRCP28SDZr */ +/* Table12091 */ + 0x38b1, /* VRSQRT28SDZm */ + 0x38b4, /* VRSQRT28SDZr */ +/* Table12093 */ + 0x2cdb, /* VPMOVUSWBZ256mr */ + 0x2cdd, /* VPMOVUSWBZ256rr */ +/* Table12095 */ + 0x2c90, /* VPMOVUSDBZ256mr */ + 0x2c92, /* VPMOVUSDBZ256rr */ +/* Table12097 */ + 0x2cae, /* VPMOVUSQBZ256mr */ + 0x2cb0, /* VPMOVUSQBZ256rr */ +/* Table12099 */ + 0x2c9f, /* VPMOVUSDWZ256mr */ + 0x2ca1, /* VPMOVUSDWZ256rr */ +/* Table12101 */ + 0x2ccc, /* VPMOVUSQWZ256mr */ + 0x2cce, /* VPMOVUSQWZ256rr */ +/* Table12103 */ + 0x2cbd, /* VPMOVUSQDZ256mr */ + 0x2cbf, /* VPMOVUSQDZ256rr */ +/* Table12105 */ + 0x2bfd, /* VPMOVSWBZ256mr */ + 0x2bff, /* VPMOVSWBZ256rr */ +/* Table12107 */ + 0x2bb2, /* VPMOVSDBZ256mr */ + 0x2bb4, /* VPMOVSDBZ256rr */ +/* Table12109 */ + 0x2bd0, /* VPMOVSQBZ256mr */ + 0x2bd2, /* VPMOVSQBZ256rr */ +/* Table12111 */ + 0x2bc1, /* VPMOVSDWZ256mr */ + 0x2bc3, /* VPMOVSDWZ256rr */ +/* Table12113 */ + 0x2bee, /* VPMOVSQWZ256mr */ + 0x2bf0, /* VPMOVSQWZ256rr */ +/* Table12115 */ + 0x2bdf, /* VPMOVSQDZ256mr */ + 0x2be1, /* VPMOVSQDZ256rr */ +/* Table12117 */ + 0x359b, /* VPTESTNMBZ256rm */ + 0x359d, /* VPTESTNMBZ256rr */ +/* Table12119 */ + 0x35a9, /* VPTESTNMDZ256rm */ + 0x35ad, /* VPTESTNMDZ256rr */ +/* Table12121 */ + 0x0, /* */ + 0x2b70, /* VPMOVM2BZ256rr */ +/* Table12123 */ + 0x0, /* */ + 0x2b4c, /* VPMOVB2MZ256rr */ +/* Table12125 */ + 0x2ced, /* VPMOVWBZ256mr */ + 0x2cef, /* VPMOVWBZ256rr */ +/* Table12127 */ + 0x2b56, /* VPMOVDBZ256mr */ + 0x2b58, /* VPMOVDBZ256rr */ +/* Table12129 */ + 0x2b85, /* VPMOVQBZ256mr */ + 0x2b87, /* VPMOVQBZ256rr */ +/* Table12131 */ + 0x2b65, /* VPMOVDWZ256mr */ + 0x2b67, /* VPMOVDWZ256rr */ +/* Table12133 */ + 0x2ba3, /* VPMOVQWZ256mr */ + 0x2ba5, /* VPMOVQWZ256rr */ +/* Table12135 */ + 0x2b94, /* VPMOVQDZ256mr */ + 0x2b96, /* VPMOVQDZ256rr */ +/* Table12137 */ + 0x0, /* */ + 0x2b73, /* VPMOVM2DZ256rr */ +/* Table12139 */ + 0x0, /* */ + 0x2b4f, /* VPMOVD2MZ256rr */ +/* Table12141 */ + 0x0, /* */ + 0x231d, /* VPBROADCASTMW2DZ256rr */ +/* Table12143 */ + 0x3158, /* VPSHUFBZ256rm */ + 0x315b, /* VPSHUFBZ256rr */ +/* Table12145 */ + 0x2987, /* VPMADDUBSWZ256rm */ + 0x298a, /* VPMADDUBSWZ256rr */ +/* Table12147 */ + 0x2da2, /* VPMULHRSWZ256rm */ + 0x2da5, /* VPMULHRSWZ256rr */ +/* Table12149 */ + 0x2724, /* VPERMILPSZ256rm */ + 0x272a, /* VPERMILPSZ256rr */ +/* Table12151 */ + 0xeed, /* VCVTPH2PSZ256rm */ + 0xef0, /* VCVTPH2PSZ256rr */ +/* Table12153 */ + 0x2fa9, /* VPRORVDZ256rm */ + 0x2faf, /* VPRORVDZ256rr */ +/* Table12155 */ + 0x2f3d, /* VPROLVDZ256rm */ + 0x2f43, /* VPROLVDZ256rr */ +/* Table12157 */ + 0x276b, /* VPERMPSZ256rm */ + 0x2771, /* VPERMPSZ256rr */ +/* Table12159 */ + 0xd40, /* VBROADCASTSSZ256m */ + 0xd43, /* VBROADCASTSSZ256r */ +/* Table12161 */ + 0xce7, /* VBROADCASTF32X2Z256m */ + 0xcea, /* VBROADCASTF32X2Z256r */ +/* Table12163 */ + 0xcf3, /* VBROADCASTF32X4Z256rm */ + 0x0, /* */ +/* Table12165 */ + 0x2035, /* VPABSBZ256rm */ + 0x2038, /* VPABSBZ256rr */ +/* Table12167 */ + 0x2085, /* VPABSWZ256rm */ + 0x2088, /* VPABSWZ256rr */ +/* Table12169 */ + 0x204e, /* VPABSDZ256rm */ + 0x2054, /* VPABSDZ256rr */ +/* Table12171 */ + 0x2c3b, /* VPMOVSXBWZ256rm */ + 0x2c3e, /* VPMOVSXBWZ256rr */ +/* Table12173 */ + 0x2c0f, /* VPMOVSXBDZ256rm */ + 0x2c12, /* VPMOVSXBDZ256rr */ +/* Table12175 */ + 0x2c25, /* VPMOVSXBQZ256rm */ + 0x2c28, /* VPMOVSXBQZ256rr */ +/* Table12177 */ + 0x2c67, /* VPMOVSXWDZ256rm */ + 0x2c6a, /* VPMOVSXWDZ256rr */ +/* Table12179 */ + 0x2c7d, /* VPMOVSXWQZ256rm */ + 0x2c80, /* VPMOVSXWQZ256rr */ +/* Table12181 */ + 0x2c51, /* VPMOVSXDQZ256rm */ + 0x2c54, /* VPMOVSXDQZ256rr */ +/* Table12183 */ + 0x355f, /* VPTESTMBZ256rm */ + 0x3561, /* VPTESTMBZ256rr */ +/* Table12185 */ + 0x356d, /* VPTESTMDZ256rm */ + 0x3571, /* VPTESTMDZ256rr */ +/* Table12187 */ + 0x1eac, /* VMOVNTDQAZ256rm */ + 0x0, /* */ +/* Table12189 */ + 0x20d3, /* VPACKUSDWZ256rm */ + 0x20d9, /* VPACKUSDWZ256rr */ +/* Table12191 */ + 0x38f2, /* VSCALEFPSZ256rm */ + 0x38f8, /* VSCALEFPSZ256rr */ +/* Table12193 */ + 0x2d2b, /* VPMOVZXBWZ256rm */ + 0x2d2e, /* VPMOVZXBWZ256rr */ +/* Table12195 */ + 0x2cff, /* VPMOVZXBDZ256rm */ + 0x2d02, /* VPMOVZXBDZ256rr */ +/* Table12197 */ + 0x2d15, /* VPMOVZXBQZ256rm */ + 0x2d18, /* VPMOVZXBQZ256rr */ +/* Table12199 */ + 0x2d57, /* VPMOVZXWDZ256rm */ + 0x2d5a, /* VPMOVZXWDZ256rr */ +/* Table12201 */ + 0x2d6d, /* VPMOVZXWQZ256rm */ + 0x2d70, /* VPMOVZXWQZ256rr */ +/* Table12203 */ + 0x2d41, /* VPMOVZXDQZ256rm */ + 0x2d44, /* VPMOVZXDQZ256rr */ +/* Table12205 */ + 0x2615, /* VPERMDZ256rm */ + 0x261b, /* VPERMDZ256rr */ +/* Table12207 */ + 0x2a87, /* VPMINSBZ256rm */ + 0x2a8a, /* VPMINSBZ256rr */ +/* Table12209 */ + 0x2aa0, /* VPMINSDZ256rm */ + 0x2aa6, /* VPMINSDZ256rr */ +/* Table12211 */ + 0x2b3d, /* VPMINUWZ256rm */ + 0x2b40, /* VPMINUWZ256rr */ +/* Table12213 */ + 0x2b06, /* VPMINUDZ256rm */ + 0x2b0c, /* VPMINUDZ256rr */ +/* Table12215 */ + 0x29bb, /* VPMAXSBZ256rm */ + 0x29be, /* VPMAXSBZ256rr */ +/* Table12217 */ + 0x29d4, /* VPMAXSDZ256rm */ + 0x29da, /* VPMAXSDZ256rr */ +/* Table12219 */ + 0x2a71, /* VPMAXUWZ256rm */ + 0x2a74, /* VPMAXUWZ256rr */ +/* Table12221 */ + 0x2a3a, /* VPMAXUDZ256rm */ + 0x2a40, /* VPMAXUDZ256rr */ +/* Table12223 */ + 0x2de7, /* VPMULLDZ256rm */ + 0x2ded, /* VPMULLDZ256rr */ +/* Table12225 */ + 0x1ab7, /* VGETEXPPSZ256m */ + 0x1abd, /* VGETEXPPSZ256r */ +/* Table12227 */ + 0x2904, /* VPLZCNTDZ256rm */ + 0x290a, /* VPLZCNTDZ256rr */ +/* Table12229 */ + 0x33f4, /* VPSRLVDZ256rm */ + 0x33fa, /* VPSRLVDZ256rr */ +/* Table12231 */ + 0x3310, /* VPSRAVDZ256rm */ + 0x3316, /* VPSRAVDZ256rr */ +/* Table12233 */ + 0x3236, /* VPSLLVDZ256rm */ + 0x323c, /* VPSLLVDZ256rr */ +/* Table12235 */ + 0x3757, /* VRCP14PSZ256m */ + 0x375d, /* VRCP14PSZ256r */ +/* Table12237 */ + 0x387b, /* VRSQRT14PSZ256m */ + 0x3881, /* VRSQRT14PSZ256r */ +/* Table12239 */ + 0x25b5, /* VPDPBUSDZ256m */ + 0x25bb, /* VPDPBUSDZ256r */ +/* Table12241 */ + 0x259a, /* VPDPBUSDSZ256m */ + 0x25a0, /* VPDPBUSDSZ256r */ +/* Table12243 */ + 0x25eb, /* VPDPWSSDZ256m */ + 0x25f1, /* VPDPWSSDZ256r */ +/* Table12245 */ + 0x25d0, /* VPDPWSSDSZ256m */ + 0x25d6, /* VPDPWSSDSZ256r */ +/* Table12247 */ + 0x2e6c, /* VPOPCNTBZ256rm */ + 0x2e6f, /* VPOPCNTBZ256rr */ +/* Table12249 */ + 0x2e81, /* VPOPCNTDZ256rm */ + 0x2e87, /* VPOPCNTDZ256rr */ +/* Table12251 */ + 0x2302, /* VPBROADCASTDZ256m */ + 0x2305, /* VPBROADCASTDZ256r */ +/* Table12253 */ + 0xd0c, /* VBROADCASTI32X2Z256m */ + 0xd0f, /* VBROADCASTI32X2Z256r */ +/* Table12255 */ + 0xd18, /* VBROADCASTI32X4Z256rm */ + 0x0, /* */ +/* Table12257 */ + 0x284b, /* VPEXPANDBZ256rm */ + 0x284e, /* VPEXPANDBZ256rr */ +/* Table12259 */ + 0x250c, /* VPCOMPRESSBZ256mr */ + 0x250e, /* VPCOMPRESSBZ256rr */ +/* Table12261 */ + 0x2294, /* VPBLENDMDZ256rm */ + 0x229a, /* VPBLENDMDZ256rr */ +/* Table12263 */ + 0xcc4, /* VBLENDMPSZ256rm */ + 0xcca, /* VBLENDMPSZ256rr */ +/* Table12265 */ + 0x227f, /* VPBLENDMBZ256rm */ + 0x2282, /* VPBLENDMBZ256rr */ +/* Table12267 */ + 0x3057, /* VPSHLDVDZ256m */ + 0x305d, /* VPSHLDVDZ256r */ +/* Table12269 */ + 0x30f3, /* VPSHRDVDZ256m */ + 0x30f9, /* VPSHRDVDZ256r */ +/* Table12271 */ + 0x262d, /* VPERMI2B256rm */ + 0x2630, /* VPERMI2B256rr */ +/* Table12273 */ + 0x2642, /* VPERMI2D256rm */ + 0x2648, /* VPERMI2D256rr */ +/* Table12275 */ + 0x2678, /* VPERMI2PS256rm */ + 0x267e, /* VPERMI2PS256rr */ +/* Table12277 */ + 0x22e3, /* VPBROADCASTBZ256m */ + 0x22e6, /* VPBROADCASTBZ256r */ +/* Table12279 */ + 0x2346, /* VPBROADCASTWZ256m */ + 0x2349, /* VPBROADCASTWZ256r */ +/* Table12281 */ + 0x0, /* */ + 0x22f2, /* VPBROADCASTBrZ256r */ +/* Table12283 */ + 0x0, /* */ + 0x2355, /* VPBROADCASTWrZ256r */ +/* Table12285 */ + 0x0, /* */ + 0x2311, /* VPBROADCASTDrZ256r */ +/* Table12287 */ + 0x27a9, /* VPERMT2B256rm */ + 0x27ac, /* VPERMT2B256rr */ +/* Table12289 */ + 0x27be, /* VPERMT2D256rm */ + 0x27c4, /* VPERMT2D256rr */ +/* Table12291 */ + 0x27f4, /* VPERMT2PS256rm */ + 0x27fa, /* VPERMT2PS256rr */ +/* Table12293 */ + 0x12b6, /* VEXPANDPSZ256rm */ + 0x12b9, /* VEXPANDPSZ256rr */ +/* Table12295 */ + 0x285d, /* VPEXPANDDZ256rm */ + 0x2860, /* VPEXPANDDZ256rr */ +/* Table12297 */ + 0xdfc, /* VCOMPRESSPSZ256mr */ + 0xdfe, /* VCOMPRESSPSZ256rr */ +/* Table12299 */ + 0x251b, /* VPCOMPRESSDZ256mr */ + 0x251d, /* VPCOMPRESSDZ256rr */ +/* Table12301 */ + 0x2607, /* VPERMBZ256rm */ + 0x260a, /* VPERMBZ256rr */ +/* Table12303 */ + 0x3148, /* VPSHUFBITQMBZ256rm */ + 0x314a, /* VPSHUFBITQMBZ256rr */ +/* Table12305 */ + 0x14cd, /* VFMADDSUB132PSZ256m */ + 0x14d3, /* VFMADDSUB132PSZ256r */ +/* Table12307 */ + 0x16d5, /* VFMSUBADD132PSZ256m */ + 0x16db, /* VFMSUBADD132PSZ256r */ +/* Table12309 */ + 0x1381, /* VFMADD132PSZ256m */ + 0x1387, /* VFMADD132PSZ256r */ +/* Table12311 */ + 0x15a9, /* VFMSUB132PSZ256m */ + 0x15af, /* VFMSUB132PSZ256r */ +/* Table12313 */ + 0x17d1, /* VFNMADD132PSZ256m */ + 0x17d7, /* VFNMADD132PSZ256r */ +/* Table12315 */ + 0x191d, /* VFNMSUB132PSZ256m */ + 0x1923, /* VFNMSUB132PSZ256r */ +/* Table12317 */ + 0x1511, /* VFMADDSUB213PSZ256m */ + 0x1517, /* VFMADDSUB213PSZ256r */ +/* Table12319 */ + 0x1719, /* VFMSUBADD213PSZ256m */ + 0x171f, /* VFMSUBADD213PSZ256r */ +/* Table12321 */ + 0x13e5, /* VFMADD213PSZ256m */ + 0x13eb, /* VFMADD213PSZ256r */ +/* Table12323 */ + 0x160d, /* VFMSUB213PSZ256m */ + 0x1613, /* VFMSUB213PSZ256r */ +/* Table12325 */ + 0x1835, /* VFNMADD213PSZ256m */ + 0x183b, /* VFNMADD213PSZ256r */ +/* Table12327 */ + 0x1981, /* VFNMSUB213PSZ256m */ + 0x1987, /* VFNMSUB213PSZ256r */ +/* Table12329 */ + 0x1555, /* VFMADDSUB231PSZ256m */ + 0x155b, /* VFMADDSUB231PSZ256r */ +/* Table12331 */ + 0x175d, /* VFMSUBADD231PSZ256m */ + 0x1763, /* VFMSUBADD231PSZ256r */ +/* Table12333 */ + 0x1449, /* VFMADD231PSZ256m */ + 0x144f, /* VFMADD231PSZ256r */ +/* Table12335 */ + 0x1671, /* VFMSUB231PSZ256m */ + 0x1677, /* VFMSUB231PSZ256r */ +/* Table12337 */ + 0x1899, /* VFNMADD231PSZ256m */ + 0x189f, /* VFNMADD231PSZ256r */ +/* Table12339 */ + 0x19e5, /* VFNMSUB231PSZ256m */ + 0x19eb, /* VFNMSUB231PSZ256r */ +/* Table12341 */ + 0x2564, /* VPCONFLICTDZ256rm */ + 0x256a, /* VPCONFLICTDZ256rr */ +/* Table12343 */ + 0x1b72, /* VGF2P8MULBZ256rm */ + 0x1b75, /* VGF2P8MULBZ256rr */ +/* Table12345 */ + 0xbe4, /* VAESENCZ256rm */ + 0xbe5, /* VAESENCZ256rr */ +/* Table12347 */ + 0xbda, /* VAESENCLASTZ256rm */ + 0xbdb, /* VAESENCLASTZ256rr */ +/* Table12349 */ + 0xbd0, /* VAESDECZ256rm */ + 0xbd1, /* VAESDECZ256rr */ +/* Table12351 */ + 0xbc6, /* VAESDECLASTZ256rm */ + 0xbc7, /* VAESDECLASTZ256rr */ +/* Table12353 */ + 0x35cb, /* VPTESTNMWZ256rm */ + 0x35cd, /* VPTESTNMWZ256rr */ +/* Table12355 */ + 0x35bb, /* VPTESTNMQZ256rm */ + 0x35bf, /* VPTESTNMQZ256rr */ +/* Table12357 */ + 0x0, /* */ + 0x2b79, /* VPMOVM2WZ256rr */ +/* Table12359 */ + 0x0, /* */ + 0x2ce6, /* VPMOVW2MZ256rr */ +/* Table12361 */ + 0x0, /* */ + 0x231a, /* VPBROADCASTMB2QZ256rr */ +/* Table12363 */ + 0x0, /* */ + 0x2b76, /* VPMOVM2QZ256rr */ +/* Table12365 */ + 0x0, /* */ + 0x2b7e, /* VPMOVQ2MZ256rr */ +/* Table12367 */ + 0x26e6, /* VPERMILPDZ256rm */ + 0x26ec, /* VPERMILPDZ256rr */ +/* Table12369 */ + 0x342d, /* VPSRLVWZ256rm */ + 0x3430, /* VPSRLVWZ256rr */ +/* Table12371 */ + 0x3345, /* VPSRAVWZ256rm */ + 0x3348, /* VPSRAVWZ256rr */ +/* Table12373 */ + 0x326f, /* VPSLLVWZ256rm */ + 0x3272, /* VPSLLVWZ256rr */ +/* Table12375 */ + 0x2fc4, /* VPRORVQZ256rm */ + 0x2fca, /* VPRORVQZ256rr */ +/* Table12377 */ + 0x2f58, /* VPROLVQZ256rm */ + 0x2f5e, /* VPROLVQZ256rr */ +/* Table12379 */ + 0x274e, /* VPERMPDZ256rm */ + 0x2754, /* VPERMPDZ256rr */ +/* Table12381 */ + 0xd2c, /* VBROADCASTSDZ256m */ + 0xd2f, /* VBROADCASTSDZ256r */ +/* Table12383 */ + 0xcfc, /* VBROADCASTF64X2Z128rm */ + 0x0, /* */ +/* Table12385 */ + 0x206b, /* VPABSQZ256rm */ + 0x2071, /* VPABSQZ256rr */ +/* Table12387 */ + 0x358f, /* VPTESTMWZ256rm */ + 0x3591, /* VPTESTMWZ256rr */ +/* Table12389 */ + 0x357f, /* VPTESTMQZ256rm */ + 0x3583, /* VPTESTMQZ256rr */ +/* Table12391 */ + 0x2d86, /* VPMULDQZ256rm */ + 0x2d8c, /* VPMULDQZ256rr */ +/* Table12393 */ + 0x23d9, /* VPCMPEQQZ256rm */ + 0x23dd, /* VPCMPEQQZ256rr */ +/* Table12395 */ + 0x38d4, /* VSCALEFPDZ256rm */ + 0x38da, /* VSCALEFPDZ256rr */ +/* Table12397 */ + 0x2788, /* VPERMQZ256rm */ + 0x278e, /* VPERMQZ256rr */ +/* Table12399 */ + 0x2429, /* VPCMPGTQZ256rm */ + 0x242d, /* VPCMPGTQZ256rr */ +/* Table12401 */ + 0x2abd, /* VPMINSQZ256rm */ + 0x2ac3, /* VPMINSQZ256rr */ +/* Table12403 */ + 0x2b23, /* VPMINUQZ256rm */ + 0x2b29, /* VPMINUQZ256rr */ +/* Table12405 */ + 0x29f1, /* VPMAXSQZ256rm */ + 0x29f7, /* VPMAXSQZ256rr */ +/* Table12407 */ + 0x2a57, /* VPMAXUQZ256rm */ + 0x2a5d, /* VPMAXUQZ256rr */ +/* Table12409 */ + 0x2e04, /* VPMULLQZ256rm */ + 0x2e0a, /* VPMULLQZ256rr */ +/* Table12411 */ + 0x1a99, /* VGETEXPPDZ256m */ + 0x1a9f, /* VGETEXPPDZ256r */ +/* Table12413 */ + 0x291f, /* VPLZCNTQZ256rm */ + 0x2925, /* VPLZCNTQZ256rr */ +/* Table12415 */ + 0x3413, /* VPSRLVQZ256rm */ + 0x3419, /* VPSRLVQZ256rr */ +/* Table12417 */ + 0x332d, /* VPSRAVQZ256rm */ + 0x3333, /* VPSRAVQZ256rr */ +/* Table12419 */ + 0x3255, /* VPSLLVQZ256rm */ + 0x325b, /* VPSLLVQZ256rr */ +/* Table12421 */ + 0x373c, /* VRCP14PDZ256m */ + 0x3742, /* VRCP14PDZ256r */ +/* Table12423 */ + 0x3860, /* VRSQRT14PDZ256m */ + 0x3866, /* VRSQRT14PDZ256r */ +/* Table12425 */ + 0x2eb4, /* VPOPCNTWZ256rm */ + 0x2eb7, /* VPOPCNTWZ256rr */ +/* Table12427 */ + 0x2e9c, /* VPOPCNTQZ256rm */ + 0x2ea2, /* VPOPCNTQZ256rr */ +/* Table12429 */ + 0x2327, /* VPBROADCASTQZ256m */ + 0x232a, /* VPBROADCASTQZ256r */ +/* Table12431 */ + 0xd21, /* VBROADCASTI64X2Z128rm */ + 0x0, /* */ +/* Table12433 */ + 0x2881, /* VPEXPANDWZ256rm */ + 0x2884, /* VPEXPANDWZ256rr */ +/* Table12435 */ + 0x2539, /* VPCOMPRESSWZ256mr */ + 0x253b, /* VPCOMPRESSWZ256rr */ +/* Table12437 */ + 0x22af, /* VPBLENDMQZ256rm */ + 0x22b5, /* VPBLENDMQZ256rr */ +/* Table12439 */ + 0xca9, /* VBLENDMPDZ256rm */ + 0xcaf, /* VBLENDMPDZ256rr */ +/* Table12441 */ + 0x22c7, /* VPBLENDMWZ256rm */ + 0x22ca, /* VPBLENDMWZ256rr */ +/* Table12443 */ + 0x308a, /* VPSHLDVWZ256m */ + 0x308d, /* VPSHLDVWZ256r */ +/* Table12445 */ + 0x3072, /* VPSHLDVQZ256m */ + 0x3078, /* VPSHLDVQZ256r */ +/* Table12447 */ + 0x3126, /* VPSHRDVWZ256m */ + 0x3129, /* VPSHRDVWZ256r */ +/* Table12449 */ + 0x310e, /* VPSHRDVQZ256m */ + 0x3114, /* VPSHRDVQZ256r */ +/* Table12451 */ + 0x26ab, /* VPERMI2W256rm */ + 0x26ae, /* VPERMI2W256rr */ +/* Table12453 */ + 0x2693, /* VPERMI2Q256rm */ + 0x2699, /* VPERMI2Q256rr */ +/* Table12455 */ + 0x265d, /* VPERMI2PD256rm */ + 0x2663, /* VPERMI2PD256rr */ +/* Table12457 */ + 0x0, /* */ + 0x2336, /* VPBROADCASTQrZ256r */ +/* Table12459 */ + 0x2827, /* VPERMT2W256rm */ + 0x282a, /* VPERMT2W256rr */ +/* Table12461 */ + 0x280f, /* VPERMT2Q256rm */ + 0x2815, /* VPERMT2Q256rr */ +/* Table12463 */ + 0x27d9, /* VPERMT2PD256rm */ + 0x27df, /* VPERMT2PD256rr */ +/* Table12465 */ + 0x2e35, /* VPMULTISHIFTQBZ256rm */ + 0x2e3b, /* VPMULTISHIFTQBZ256rr */ +/* Table12467 */ + 0x12a4, /* VEXPANDPDZ256rm */ + 0x12a7, /* VEXPANDPDZ256rr */ +/* Table12469 */ + 0x286f, /* VPEXPANDQZ256rm */ + 0x2872, /* VPEXPANDQZ256rr */ +/* Table12471 */ + 0xded, /* VCOMPRESSPDZ256mr */ + 0xdef, /* VCOMPRESSPDZ256rr */ +/* Table12473 */ + 0x252a, /* VPCOMPRESSQZ256mr */ + 0x252c, /* VPCOMPRESSQZ256rr */ +/* Table12475 */ + 0x2839, /* VPERMWZ256rm */ + 0x283c, /* VPERMWZ256rr */ +/* Table12477 */ + 0x14ab, /* VFMADDSUB132PDZ256m */ + 0x14b1, /* VFMADDSUB132PDZ256r */ +/* Table12479 */ + 0x16b3, /* VFMSUBADD132PDZ256m */ + 0x16b9, /* VFMSUBADD132PDZ256r */ +/* Table12481 */ + 0x135f, /* VFMADD132PDZ256m */ + 0x1365, /* VFMADD132PDZ256r */ +/* Table12483 */ + 0x1587, /* VFMSUB132PDZ256m */ + 0x158d, /* VFMSUB132PDZ256r */ +/* Table12485 */ + 0x17af, /* VFNMADD132PDZ256m */ + 0x17b5, /* VFNMADD132PDZ256r */ +/* Table12487 */ + 0x18fb, /* VFNMSUB132PDZ256m */ + 0x1901, /* VFNMSUB132PDZ256r */ +/* Table12489 */ + 0x14ef, /* VFMADDSUB213PDZ256m */ + 0x14f5, /* VFMADDSUB213PDZ256r */ +/* Table12491 */ + 0x16f7, /* VFMSUBADD213PDZ256m */ + 0x16fd, /* VFMSUBADD213PDZ256r */ +/* Table12493 */ + 0x13c3, /* VFMADD213PDZ256m */ + 0x13c9, /* VFMADD213PDZ256r */ +/* Table12495 */ + 0x15eb, /* VFMSUB213PDZ256m */ + 0x15f1, /* VFMSUB213PDZ256r */ +/* Table12497 */ + 0x1813, /* VFNMADD213PDZ256m */ + 0x1819, /* VFNMADD213PDZ256r */ +/* Table12499 */ + 0x195f, /* VFNMSUB213PDZ256m */ + 0x1965, /* VFNMSUB213PDZ256r */ +/* Table12501 */ + 0x296d, /* VPMADD52LUQZ256m */ + 0x2973, /* VPMADD52LUQZ256r */ +/* Table12503 */ + 0x2952, /* VPMADD52HUQZ256m */ + 0x2958, /* VPMADD52HUQZ256r */ +/* Table12505 */ + 0x1533, /* VFMADDSUB231PDZ256m */ + 0x1539, /* VFMADDSUB231PDZ256r */ +/* Table12507 */ + 0x173b, /* VFMSUBADD231PDZ256m */ + 0x1741, /* VFMSUBADD231PDZ256r */ +/* Table12509 */ + 0x1427, /* VFMADD231PDZ256m */ + 0x142d, /* VFMADD231PDZ256r */ +/* Table12511 */ + 0x164f, /* VFMSUB231PDZ256m */ + 0x1655, /* VFMSUB231PDZ256r */ +/* Table12513 */ + 0x1877, /* VFNMADD231PDZ256m */ + 0x187d, /* VFNMADD231PDZ256r */ +/* Table12515 */ + 0x19c3, /* VFNMSUB231PDZ256m */ + 0x19c9, /* VFNMSUB231PDZ256r */ +/* Table12517 */ + 0x257f, /* VPCONFLICTQZ256rm */ + 0x2585, /* VPCONFLICTQZ256rr */ +/* Table12519 */ + 0x2ce0, /* VPMOVUSWBZmr */ + 0x2ce2, /* VPMOVUSWBZrr */ +/* Table12521 */ + 0x2c95, /* VPMOVUSDBZmr */ + 0x2c97, /* VPMOVUSDBZrr */ +/* Table12523 */ + 0x2cb3, /* VPMOVUSQBZmr */ + 0x2cb5, /* VPMOVUSQBZrr */ +/* Table12525 */ + 0x2ca4, /* VPMOVUSDWZmr */ + 0x2ca6, /* VPMOVUSDWZrr */ +/* Table12527 */ + 0x2cd1, /* VPMOVUSQWZmr */ + 0x2cd3, /* VPMOVUSQWZrr */ +/* Table12529 */ + 0x2cc2, /* VPMOVUSQDZmr */ + 0x2cc4, /* VPMOVUSQDZrr */ +/* Table12531 */ + 0x2c02, /* VPMOVSWBZmr */ + 0x2c04, /* VPMOVSWBZrr */ +/* Table12533 */ + 0x2bb7, /* VPMOVSDBZmr */ + 0x2bb9, /* VPMOVSDBZrr */ +/* Table12535 */ + 0x2bd5, /* VPMOVSQBZmr */ + 0x2bd7, /* VPMOVSQBZrr */ +/* Table12537 */ + 0x2bc6, /* VPMOVSDWZmr */ + 0x2bc8, /* VPMOVSDWZrr */ +/* Table12539 */ + 0x2bf3, /* VPMOVSQWZmr */ + 0x2bf5, /* VPMOVSQWZrr */ +/* Table12541 */ + 0x2be4, /* VPMOVSQDZmr */ + 0x2be6, /* VPMOVSQDZrr */ +/* Table12543 */ + 0x359f, /* VPTESTNMBZrm */ + 0x35a1, /* VPTESTNMBZrr */ +/* Table12545 */ + 0x35af, /* VPTESTNMDZrm */ + 0x35b3, /* VPTESTNMDZrr */ +/* Table12547 */ + 0x0, /* */ + 0x2b71, /* VPMOVM2BZrr */ +/* Table12549 */ + 0x0, /* */ + 0x2b4d, /* VPMOVB2MZrr */ +/* Table12551 */ + 0x2cf2, /* VPMOVWBZmr */ + 0x2cf4, /* VPMOVWBZrr */ +/* Table12553 */ + 0x2b5b, /* VPMOVDBZmr */ + 0x2b5d, /* VPMOVDBZrr */ +/* Table12555 */ + 0x2b8a, /* VPMOVQBZmr */ + 0x2b8c, /* VPMOVQBZrr */ +/* Table12557 */ + 0x2b6a, /* VPMOVDWZmr */ + 0x2b6c, /* VPMOVDWZrr */ +/* Table12559 */ + 0x2ba8, /* VPMOVQWZmr */ + 0x2baa, /* VPMOVQWZrr */ +/* Table12561 */ + 0x2b99, /* VPMOVQDZmr */ + 0x2b9b, /* VPMOVQDZrr */ +/* Table12563 */ + 0x0, /* */ + 0x2b74, /* VPMOVM2DZrr */ +/* Table12565 */ + 0x0, /* */ + 0x2b50, /* VPMOVD2MZrr */ +/* Table12567 */ + 0x0, /* */ + 0x231e, /* VPBROADCASTMW2DZrr */ +/* Table12569 */ + 0x202a, /* VP4DPWSSDrm */ + 0x0, /* */ +/* Table12571 */ + 0x2027, /* VP4DPWSSDSrm */ + 0x0, /* */ +/* Table12573 */ + 0xb4c, /* V4FMADDPSrm */ + 0x0, /* */ +/* Table12575 */ + 0xb52, /* V4FNMADDPSrm */ + 0x0, /* */ +/* Table12577 */ + 0x315e, /* VPSHUFBZrm */ + 0x3161, /* VPSHUFBZrr */ +/* Table12579 */ + 0x298d, /* VPMADDUBSWZrm */ + 0x2990, /* VPMADDUBSWZrr */ +/* Table12581 */ + 0x2da8, /* VPMULHRSWZrm */ + 0x2dab, /* VPMULHRSWZrr */ +/* Table12583 */ + 0x2736, /* VPERMILPSZrm */ + 0x273c, /* VPERMILPSZrr */ +/* Table12585 */ + 0xef3, /* VCVTPH2PSZrm */ + 0xef6, /* VCVTPH2PSZrr */ +/* Table12587 */ + 0x2fb2, /* VPRORVDZrm */ + 0x2fb8, /* VPRORVDZrr */ +/* Table12589 */ + 0x2f46, /* VPROLVDZrm */ + 0x2f4c, /* VPROLVDZrr */ +/* Table12591 */ + 0x2774, /* VPERMPSZrm */ + 0x277a, /* VPERMPSZrr */ +/* Table12593 */ + 0xd46, /* VBROADCASTSSZm */ + 0xd49, /* VBROADCASTSSZr */ +/* Table12595 */ + 0xced, /* VBROADCASTF32X2Zm */ + 0xcf0, /* VBROADCASTF32X2Zr */ +/* Table12597 */ + 0xcf6, /* VBROADCASTF32X4rm */ + 0x0, /* */ +/* Table12599 */ + 0xcf9, /* VBROADCASTF32X8rm */ + 0x0, /* */ +/* Table12601 */ + 0x203b, /* VPABSBZrm */ + 0x203e, /* VPABSBZrr */ +/* Table12603 */ + 0x208b, /* VPABSWZrm */ + 0x208e, /* VPABSWZrr */ +/* Table12605 */ + 0x2057, /* VPABSDZrm */ + 0x205d, /* VPABSDZrr */ +/* Table12607 */ + 0x2c41, /* VPMOVSXBWZrm */ + 0x2c44, /* VPMOVSXBWZrr */ +/* Table12609 */ + 0x2c15, /* VPMOVSXBDZrm */ + 0x2c18, /* VPMOVSXBDZrr */ +/* Table12611 */ + 0x2c2b, /* VPMOVSXBQZrm */ + 0x2c2e, /* VPMOVSXBQZrr */ +/* Table12613 */ + 0x2c6d, /* VPMOVSXWDZrm */ + 0x2c70, /* VPMOVSXWDZrr */ +/* Table12615 */ + 0x2c83, /* VPMOVSXWQZrm */ + 0x2c86, /* VPMOVSXWQZrr */ +/* Table12617 */ + 0x2c57, /* VPMOVSXDQZrm */ + 0x2c5a, /* VPMOVSXDQZrr */ +/* Table12619 */ + 0x3563, /* VPTESTMBZrm */ + 0x3565, /* VPTESTMBZrr */ +/* Table12621 */ + 0x3573, /* VPTESTMDZrm */ + 0x3577, /* VPTESTMDZrr */ +/* Table12623 */ + 0x1ead, /* VMOVNTDQAZrm */ + 0x0, /* */ +/* Table12625 */ + 0x20dc, /* VPACKUSDWZrm */ + 0x20e2, /* VPACKUSDWZrr */ +/* Table12627 */ + 0x38fb, /* VSCALEFPSZrm */ + 0x3901, /* VSCALEFPSZrr */ +/* Table12629 */ + 0x2d31, /* VPMOVZXBWZrm */ + 0x2d34, /* VPMOVZXBWZrr */ +/* Table12631 */ + 0x2d05, /* VPMOVZXBDZrm */ + 0x2d08, /* VPMOVZXBDZrr */ +/* Table12633 */ + 0x2d1b, /* VPMOVZXBQZrm */ + 0x2d1e, /* VPMOVZXBQZrr */ +/* Table12635 */ + 0x2d5d, /* VPMOVZXWDZrm */ + 0x2d60, /* VPMOVZXWDZrr */ +/* Table12637 */ + 0x2d73, /* VPMOVZXWQZrm */ + 0x2d76, /* VPMOVZXWQZrr */ +/* Table12639 */ + 0x2d47, /* VPMOVZXDQZrm */ + 0x2d4a, /* VPMOVZXDQZrr */ +/* Table12641 */ + 0x261e, /* VPERMDZrm */ + 0x2624, /* VPERMDZrr */ +/* Table12643 */ + 0x2a8d, /* VPMINSBZrm */ + 0x2a90, /* VPMINSBZrr */ +/* Table12645 */ + 0x2aa9, /* VPMINSDZrm */ + 0x2aaf, /* VPMINSDZrr */ +/* Table12647 */ + 0x2b43, /* VPMINUWZrm */ + 0x2b46, /* VPMINUWZrr */ +/* Table12649 */ + 0x2b0f, /* VPMINUDZrm */ + 0x2b15, /* VPMINUDZrr */ +/* Table12651 */ + 0x29c1, /* VPMAXSBZrm */ + 0x29c4, /* VPMAXSBZrr */ +/* Table12653 */ + 0x29dd, /* VPMAXSDZrm */ + 0x29e3, /* VPMAXSDZrr */ +/* Table12655 */ + 0x2a77, /* VPMAXUWZrm */ + 0x2a7a, /* VPMAXUWZrr */ +/* Table12657 */ + 0x2a43, /* VPMAXUDZrm */ + 0x2a49, /* VPMAXUDZrr */ +/* Table12659 */ + 0x2df0, /* VPMULLDZrm */ + 0x2df6, /* VPMULLDZrr */ +/* Table12661 */ + 0x1ac0, /* VGETEXPPSZm */ + 0x1ac6, /* VGETEXPPSZr */ +/* Table12663 */ + 0x290d, /* VPLZCNTDZrm */ + 0x2913, /* VPLZCNTDZrr */ +/* Table12665 */ + 0x33fd, /* VPSRLVDZrm */ + 0x3403, /* VPSRLVDZrr */ +/* Table12667 */ + 0x3319, /* VPSRAVDZrm */ + 0x331f, /* VPSRAVDZrr */ +/* Table12669 */ + 0x323f, /* VPSLLVDZrm */ + 0x3245, /* VPSLLVDZrr */ +/* Table12671 */ + 0x3760, /* VRCP14PSZm */ + 0x3766, /* VRCP14PSZr */ +/* Table12673 */ + 0x3884, /* VRSQRT14PSZm */ + 0x388a, /* VRSQRT14PSZr */ +/* Table12675 */ + 0x25be, /* VPDPBUSDZm */ + 0x25c4, /* VPDPBUSDZr */ +/* Table12677 */ + 0x25a3, /* VPDPBUSDSZm */ + 0x25a9, /* VPDPBUSDSZr */ +/* Table12679 */ + 0x25f4, /* VPDPWSSDZm */ + 0x25fa, /* VPDPWSSDZr */ +/* Table12681 */ + 0x25d9, /* VPDPWSSDSZm */ + 0x25df, /* VPDPWSSDSZr */ +/* Table12683 */ + 0x2e72, /* VPOPCNTBZrm */ + 0x2e75, /* VPOPCNTBZrr */ +/* Table12685 */ + 0x2e8a, /* VPOPCNTDZrm */ + 0x2e90, /* VPOPCNTDZrr */ +/* Table12687 */ + 0x2308, /* VPBROADCASTDZm */ + 0x230b, /* VPBROADCASTDZr */ +/* Table12689 */ + 0xd12, /* VBROADCASTI32X2Zm */ + 0xd15, /* VBROADCASTI32X2Zr */ +/* Table12691 */ + 0xd1b, /* VBROADCASTI32X4rm */ + 0x0, /* */ +/* Table12693 */ + 0xd1e, /* VBROADCASTI32X8rm */ + 0x0, /* */ +/* Table12695 */ + 0x2851, /* VPEXPANDBZrm */ + 0x2854, /* VPEXPANDBZrr */ +/* Table12697 */ + 0x2511, /* VPCOMPRESSBZmr */ + 0x2513, /* VPCOMPRESSBZrr */ +/* Table12699 */ + 0x229d, /* VPBLENDMDZrm */ + 0x22a3, /* VPBLENDMDZrr */ +/* Table12701 */ + 0xccd, /* VBLENDMPSZrm */ + 0xcd3, /* VBLENDMPSZrr */ +/* Table12703 */ + 0x2285, /* VPBLENDMBZrm */ + 0x2288, /* VPBLENDMBZrr */ +/* Table12705 */ + 0x3060, /* VPSHLDVDZm */ + 0x3066, /* VPSHLDVDZr */ +/* Table12707 */ + 0x30fc, /* VPSHRDVDZm */ + 0x3102, /* VPSHRDVDZr */ +/* Table12709 */ + 0x2633, /* VPERMI2Brm */ + 0x2636, /* VPERMI2Brr */ +/* Table12711 */ + 0x264b, /* VPERMI2Drm */ + 0x2651, /* VPERMI2Drr */ +/* Table12713 */ + 0x2681, /* VPERMI2PSrm */ + 0x2687, /* VPERMI2PSrr */ +/* Table12715 */ + 0x22e9, /* VPBROADCASTBZm */ + 0x22ec, /* VPBROADCASTBZr */ +/* Table12717 */ + 0x234c, /* VPBROADCASTWZm */ + 0x234f, /* VPBROADCASTWZr */ +/* Table12719 */ + 0x0, /* */ + 0x22f5, /* VPBROADCASTBrZr */ +/* Table12721 */ + 0x0, /* */ + 0x2358, /* VPBROADCASTWrZr */ +/* Table12723 */ + 0x0, /* */ + 0x2314, /* VPBROADCASTDrZr */ +/* Table12725 */ + 0x27af, /* VPERMT2Brm */ + 0x27b2, /* VPERMT2Brr */ +/* Table12727 */ + 0x27c7, /* VPERMT2Drm */ + 0x27cd, /* VPERMT2Drr */ +/* Table12729 */ + 0x27fd, /* VPERMT2PSrm */ + 0x2803, /* VPERMT2PSrr */ +/* Table12731 */ + 0x12bc, /* VEXPANDPSZrm */ + 0x12bf, /* VEXPANDPSZrr */ +/* Table12733 */ + 0x2863, /* VPEXPANDDZrm */ + 0x2866, /* VPEXPANDDZrr */ +/* Table12735 */ + 0xe01, /* VCOMPRESSPSZmr */ + 0xe03, /* VCOMPRESSPSZrr */ +/* Table12737 */ + 0x2520, /* VPCOMPRESSDZmr */ + 0x2522, /* VPCOMPRESSDZrr */ +/* Table12739 */ + 0x260d, /* VPERMBZrm */ + 0x2610, /* VPERMBZrr */ +/* Table12741 */ + 0x314c, /* VPSHUFBITQMBZrm */ + 0x314e, /* VPSHUFBITQMBZrr */ +/* Table12743 */ + 0x14d6, /* VFMADDSUB132PSZm */ + 0x14dc, /* VFMADDSUB132PSZr */ +/* Table12745 */ + 0x16de, /* VFMSUBADD132PSZm */ + 0x16e4, /* VFMSUBADD132PSZr */ +/* Table12747 */ + 0x138a, /* VFMADD132PSZm */ + 0x1390, /* VFMADD132PSZr */ +/* Table12749 */ + 0x15b2, /* VFMSUB132PSZm */ + 0x15b8, /* VFMSUB132PSZr */ +/* Table12751 */ + 0x17da, /* VFNMADD132PSZm */ + 0x17e0, /* VFNMADD132PSZr */ +/* Table12753 */ + 0x1926, /* VFNMSUB132PSZm */ + 0x192c, /* VFNMSUB132PSZr */ +/* Table12755 */ + 0x151a, /* VFMADDSUB213PSZm */ + 0x1520, /* VFMADDSUB213PSZr */ +/* Table12757 */ + 0x1722, /* VFMSUBADD213PSZm */ + 0x1728, /* VFMSUBADD213PSZr */ +/* Table12759 */ + 0x13ee, /* VFMADD213PSZm */ + 0x13f4, /* VFMADD213PSZr */ +/* Table12761 */ + 0x1616, /* VFMSUB213PSZm */ + 0x161c, /* VFMSUB213PSZr */ +/* Table12763 */ + 0x183e, /* VFNMADD213PSZm */ + 0x1844, /* VFNMADD213PSZr */ +/* Table12765 */ + 0x198a, /* VFNMSUB213PSZm */ + 0x1990, /* VFNMSUB213PSZr */ +/* Table12767 */ + 0x155e, /* VFMADDSUB231PSZm */ + 0x1564, /* VFMADDSUB231PSZr */ +/* Table12769 */ + 0x1766, /* VFMSUBADD231PSZm */ + 0x176c, /* VFMSUBADD231PSZr */ +/* Table12771 */ + 0x1452, /* VFMADD231PSZm */ + 0x1458, /* VFMADD231PSZr */ +/* Table12773 */ + 0x167a, /* VFMSUB231PSZm */ + 0x1680, /* VFMSUB231PSZr */ +/* Table12775 */ + 0x18a2, /* VFNMADD231PSZm */ + 0x18a8, /* VFNMADD231PSZr */ +/* Table12777 */ + 0x19ee, /* VFNMSUB231PSZm */ + 0x19f4, /* VFNMSUB231PSZr */ +/* Table12779 */ + 0x256d, /* VPCONFLICTDZrm */ + 0x2573, /* VPCONFLICTDZrr */ +/* Table12781 */ + 0x1292, /* VEXP2PSZm */ + 0x1298, /* VEXP2PSZr */ +/* Table12783 */ + 0x3781, /* VRCP28PSZm */ + 0x3787, /* VRCP28PSZr */ +/* Table12785 */ + 0x38a5, /* VRSQRT28PSZm */ + 0x38ab, /* VRSQRT28PSZr */ +/* Table12787 */ + 0x1b78, /* VGF2P8MULBZrm */ + 0x1b7b, /* VGF2P8MULBZrr */ +/* Table12789 */ + 0xbe6, /* VAESENCZrm */ + 0xbe7, /* VAESENCZrr */ +/* Table12791 */ + 0xbdc, /* VAESENCLASTZrm */ + 0xbdd, /* VAESENCLASTZrr */ +/* Table12793 */ + 0xbd2, /* VAESDECZrm */ + 0xbd3, /* VAESDECZrr */ +/* Table12795 */ + 0xbc8, /* VAESDECLASTZrm */ + 0xbc9, /* VAESDECLASTZrr */ +/* Table12797 */ + 0x35cf, /* VPTESTNMWZrm */ + 0x35d1, /* VPTESTNMWZrr */ +/* Table12799 */ + 0x35c1, /* VPTESTNMQZrm */ + 0x35c5, /* VPTESTNMQZrr */ +/* Table12801 */ + 0x0, /* */ + 0x2b7a, /* VPMOVM2WZrr */ +/* Table12803 */ + 0x0, /* */ + 0x2ce7, /* VPMOVW2MZrr */ +/* Table12805 */ + 0x0, /* */ + 0x231b, /* VPBROADCASTMB2QZrr */ +/* Table12807 */ + 0x0, /* */ + 0x2b77, /* VPMOVM2QZrr */ +/* Table12809 */ + 0x0, /* */ + 0x2b7f, /* VPMOVQ2MZrr */ +/* Table12811 */ + 0x26f8, /* VPERMILPDZrm */ + 0x26fe, /* VPERMILPDZrr */ +/* Table12813 */ + 0x3433, /* VPSRLVWZrm */ + 0x3436, /* VPSRLVWZrr */ +/* Table12815 */ + 0x334b, /* VPSRAVWZrm */ + 0x334e, /* VPSRAVWZrr */ +/* Table12817 */ + 0x3275, /* VPSLLVWZrm */ + 0x3278, /* VPSLLVWZrr */ +/* Table12819 */ + 0x2fcd, /* VPRORVQZrm */ + 0x2fd3, /* VPRORVQZrr */ +/* Table12821 */ + 0x2f61, /* VPROLVQZrm */ + 0x2f67, /* VPROLVQZrr */ +/* Table12823 */ + 0x2760, /* VPERMPDZrm */ + 0x2766, /* VPERMPDZrr */ +/* Table12825 */ + 0xd32, /* VBROADCASTSDZm */ + 0xd35, /* VBROADCASTSDZr */ +/* Table12827 */ + 0xcff, /* VBROADCASTF64X2rm */ + 0x0, /* */ +/* Table12829 */ + 0xd02, /* VBROADCASTF64X4rm */ + 0x0, /* */ +/* Table12831 */ + 0x2074, /* VPABSQZrm */ + 0x207a, /* VPABSQZrr */ +/* Table12833 */ + 0x3593, /* VPTESTMWZrm */ + 0x3595, /* VPTESTMWZrr */ +/* Table12835 */ + 0x3585, /* VPTESTMQZrm */ + 0x3589, /* VPTESTMQZrr */ +/* Table12837 */ + 0x2d8f, /* VPMULDQZrm */ + 0x2d95, /* VPMULDQZrr */ +/* Table12839 */ + 0x23df, /* VPCMPEQQZrm */ + 0x23e3, /* VPCMPEQQZrr */ +/* Table12841 */ + 0x38dd, /* VSCALEFPDZrm */ + 0x38e3, /* VSCALEFPDZrr */ +/* Table12843 */ + 0x279a, /* VPERMQZrm */ + 0x27a0, /* VPERMQZrr */ +/* Table12845 */ + 0x242f, /* VPCMPGTQZrm */ + 0x2433, /* VPCMPGTQZrr */ +/* Table12847 */ + 0x2ac6, /* VPMINSQZrm */ + 0x2acc, /* VPMINSQZrr */ +/* Table12849 */ + 0x2b2c, /* VPMINUQZrm */ + 0x2b32, /* VPMINUQZrr */ +/* Table12851 */ + 0x29fa, /* VPMAXSQZrm */ + 0x2a00, /* VPMAXSQZrr */ +/* Table12853 */ + 0x2a60, /* VPMAXUQZrm */ + 0x2a66, /* VPMAXUQZrr */ +/* Table12855 */ + 0x2e0d, /* VPMULLQZrm */ + 0x2e13, /* VPMULLQZrr */ +/* Table12857 */ + 0x1aa2, /* VGETEXPPDZm */ + 0x1aa8, /* VGETEXPPDZr */ +/* Table12859 */ + 0x2928, /* VPLZCNTQZrm */ + 0x292e, /* VPLZCNTQZrr */ +/* Table12861 */ + 0x341c, /* VPSRLVQZrm */ + 0x3422, /* VPSRLVQZrr */ +/* Table12863 */ + 0x3336, /* VPSRAVQZrm */ + 0x333c, /* VPSRAVQZrr */ +/* Table12865 */ + 0x325e, /* VPSLLVQZrm */ + 0x3264, /* VPSLLVQZrr */ +/* Table12867 */ + 0x3745, /* VRCP14PDZm */ + 0x374b, /* VRCP14PDZr */ +/* Table12869 */ + 0x3869, /* VRSQRT14PDZm */ + 0x386f, /* VRSQRT14PDZr */ +/* Table12871 */ + 0x2eba, /* VPOPCNTWZrm */ + 0x2ebd, /* VPOPCNTWZrr */ +/* Table12873 */ + 0x2ea5, /* VPOPCNTQZrm */ + 0x2eab, /* VPOPCNTQZrr */ +/* Table12875 */ + 0x232d, /* VPBROADCASTQZm */ + 0x2330, /* VPBROADCASTQZr */ +/* Table12877 */ + 0xd24, /* VBROADCASTI64X2rm */ + 0x0, /* */ +/* Table12879 */ + 0xd27, /* VBROADCASTI64X4rm */ + 0x0, /* */ +/* Table12881 */ + 0x2887, /* VPEXPANDWZrm */ + 0x288a, /* VPEXPANDWZrr */ +/* Table12883 */ + 0x253e, /* VPCOMPRESSWZmr */ + 0x2540, /* VPCOMPRESSWZrr */ +/* Table12885 */ + 0x22b8, /* VPBLENDMQZrm */ + 0x22be, /* VPBLENDMQZrr */ +/* Table12887 */ + 0xcb2, /* VBLENDMPDZrm */ + 0xcb8, /* VBLENDMPDZrr */ +/* Table12889 */ + 0x22cd, /* VPBLENDMWZrm */ + 0x22d0, /* VPBLENDMWZrr */ +/* Table12891 */ + 0x3090, /* VPSHLDVWZm */ + 0x3093, /* VPSHLDVWZr */ +/* Table12893 */ + 0x307b, /* VPSHLDVQZm */ + 0x3081, /* VPSHLDVQZr */ +/* Table12895 */ + 0x312c, /* VPSHRDVWZm */ + 0x312f, /* VPSHRDVWZr */ +/* Table12897 */ + 0x3117, /* VPSHRDVQZm */ + 0x311d, /* VPSHRDVQZr */ +/* Table12899 */ + 0x26b1, /* VPERMI2Wrm */ + 0x26b4, /* VPERMI2Wrr */ +/* Table12901 */ + 0x269c, /* VPERMI2Qrm */ + 0x26a2, /* VPERMI2Qrr */ +/* Table12903 */ + 0x2666, /* VPERMI2PDrm */ + 0x266c, /* VPERMI2PDrr */ +/* Table12905 */ + 0x0, /* */ + 0x2339, /* VPBROADCASTQrZr */ +/* Table12907 */ + 0x282d, /* VPERMT2Wrm */ + 0x2830, /* VPERMT2Wrr */ +/* Table12909 */ + 0x2818, /* VPERMT2Qrm */ + 0x281e, /* VPERMT2Qrr */ +/* Table12911 */ + 0x27e2, /* VPERMT2PDrm */ + 0x27e8, /* VPERMT2PDrr */ +/* Table12913 */ + 0x2e3e, /* VPMULTISHIFTQBZrm */ + 0x2e44, /* VPMULTISHIFTQBZrr */ +/* Table12915 */ + 0x12aa, /* VEXPANDPDZrm */ + 0x12ad, /* VEXPANDPDZrr */ +/* Table12917 */ + 0x2875, /* VPEXPANDQZrm */ + 0x2878, /* VPEXPANDQZrr */ +/* Table12919 */ + 0xdf2, /* VCOMPRESSPDZmr */ + 0xdf4, /* VCOMPRESSPDZrr */ +/* Table12921 */ + 0x252f, /* VPCOMPRESSQZmr */ + 0x2531, /* VPCOMPRESSQZrr */ +/* Table12923 */ + 0x283f, /* VPERMWZrm */ + 0x2842, /* VPERMWZrr */ +/* Table12925 */ + 0x14b4, /* VFMADDSUB132PDZm */ + 0x14ba, /* VFMADDSUB132PDZr */ +/* Table12927 */ + 0x16bc, /* VFMSUBADD132PDZm */ + 0x16c2, /* VFMSUBADD132PDZr */ +/* Table12929 */ + 0x1368, /* VFMADD132PDZm */ + 0x136e, /* VFMADD132PDZr */ +/* Table12931 */ + 0x1590, /* VFMSUB132PDZm */ + 0x1596, /* VFMSUB132PDZr */ +/* Table12933 */ + 0x17b8, /* VFNMADD132PDZm */ + 0x17be, /* VFNMADD132PDZr */ +/* Table12935 */ + 0x1904, /* VFNMSUB132PDZm */ + 0x190a, /* VFNMSUB132PDZr */ +/* Table12937 */ + 0x14f8, /* VFMADDSUB213PDZm */ + 0x14fe, /* VFMADDSUB213PDZr */ +/* Table12939 */ + 0x1700, /* VFMSUBADD213PDZm */ + 0x1706, /* VFMSUBADD213PDZr */ +/* Table12941 */ + 0x13cc, /* VFMADD213PDZm */ + 0x13d2, /* VFMADD213PDZr */ +/* Table12943 */ + 0x15f4, /* VFMSUB213PDZm */ + 0x15fa, /* VFMSUB213PDZr */ +/* Table12945 */ + 0x181c, /* VFNMADD213PDZm */ + 0x1822, /* VFNMADD213PDZr */ +/* Table12947 */ + 0x1968, /* VFNMSUB213PDZm */ + 0x196e, /* VFNMSUB213PDZr */ +/* Table12949 */ + 0x2976, /* VPMADD52LUQZm */ + 0x297c, /* VPMADD52LUQZr */ +/* Table12951 */ + 0x295b, /* VPMADD52HUQZm */ + 0x2961, /* VPMADD52HUQZr */ +/* Table12953 */ + 0x153c, /* VFMADDSUB231PDZm */ + 0x1542, /* VFMADDSUB231PDZr */ +/* Table12955 */ + 0x1744, /* VFMSUBADD231PDZm */ + 0x174a, /* VFMSUBADD231PDZr */ +/* Table12957 */ + 0x1430, /* VFMADD231PDZm */ + 0x1436, /* VFMADD231PDZr */ +/* Table12959 */ + 0x1658, /* VFMSUB231PDZm */ + 0x165e, /* VFMSUB231PDZr */ +/* Table12961 */ + 0x1880, /* VFNMADD231PDZm */ + 0x1886, /* VFNMADD231PDZr */ +/* Table12963 */ + 0x19cc, /* VFNMSUB231PDZm */ + 0x19d2, /* VFNMSUB231PDZr */ +/* Table12965 */ + 0x2588, /* VPCONFLICTQZrm */ + 0x258e, /* VPCONFLICTQZrr */ +/* Table12967 */ + 0x1286, /* VEXP2PDZm */ + 0x128c, /* VEXP2PDZr */ +/* Table12969 */ + 0x3775, /* VRCP28PDZm */ + 0x377b, /* VRCP28PDZr */ +/* Table12971 */ + 0x3899, /* VRSQRT28PDZm */ + 0x389f, /* VRSQRT28PDZr */ +/* Table12973 */ + 0x2cd7, /* VPMOVUSWBZ128mrk */ + 0x2cd9, /* VPMOVUSWBZ128rrk */ +/* Table12975 */ + 0x2c8c, /* VPMOVUSDBZ128mrk */ + 0x2c8e, /* VPMOVUSDBZ128rrk */ +/* Table12977 */ + 0x2caa, /* VPMOVUSQBZ128mrk */ + 0x2cac, /* VPMOVUSQBZ128rrk */ +/* Table12979 */ + 0x2c9b, /* VPMOVUSDWZ128mrk */ + 0x2c9d, /* VPMOVUSDWZ128rrk */ +/* Table12981 */ + 0x2cc8, /* VPMOVUSQWZ128mrk */ + 0x2cca, /* VPMOVUSQWZ128rrk */ +/* Table12983 */ + 0x2cb9, /* VPMOVUSQDZ128mrk */ + 0x2cbb, /* VPMOVUSQDZ128rrk */ +/* Table12985 */ + 0x2bf9, /* VPMOVSWBZ128mrk */ + 0x2bfb, /* VPMOVSWBZ128rrk */ +/* Table12987 */ + 0x2bae, /* VPMOVSDBZ128mrk */ + 0x2bb0, /* VPMOVSDBZ128rrk */ +/* Table12989 */ + 0x2bcc, /* VPMOVSQBZ128mrk */ + 0x2bce, /* VPMOVSQBZ128rrk */ +/* Table12991 */ + 0x2bbd, /* VPMOVSDWZ128mrk */ + 0x2bbf, /* VPMOVSDWZ128rrk */ +/* Table12993 */ + 0x2bea, /* VPMOVSQWZ128mrk */ + 0x2bec, /* VPMOVSQWZ128rrk */ +/* Table12995 */ + 0x2bdb, /* VPMOVSQDZ128mrk */ + 0x2bdd, /* VPMOVSQDZ128rrk */ +/* Table12997 */ + 0x3598, /* VPTESTNMBZ128rmk */ + 0x359a, /* VPTESTNMBZ128rrk */ +/* Table12999 */ + 0x35a6, /* VPTESTNMDZ128rmk */ + 0x35a8, /* VPTESTNMDZ128rrk */ +/* Table13001 */ + 0x2ce9, /* VPMOVWBZ128mrk */ + 0x2ceb, /* VPMOVWBZ128rrk */ +/* Table13003 */ + 0x2b52, /* VPMOVDBZ128mrk */ + 0x2b54, /* VPMOVDBZ128rrk */ +/* Table13005 */ + 0x2b81, /* VPMOVQBZ128mrk */ + 0x2b83, /* VPMOVQBZ128rrk */ +/* Table13007 */ + 0x2b61, /* VPMOVDWZ128mrk */ + 0x2b63, /* VPMOVDWZ128rrk */ +/* Table13009 */ + 0x2b9f, /* VPMOVQWZ128mrk */ + 0x2ba1, /* VPMOVQWZ128rrk */ +/* Table13011 */ + 0x2b90, /* VPMOVQDZ128mrk */ + 0x2b92, /* VPMOVQDZ128rrk */ +/* Table13013 */ + 0xb50, /* V4FMADDSSrmk */ + 0x0, /* */ +/* Table13015 */ + 0xb56, /* V4FNMADDSSrmk */ + 0x0, /* */ +/* Table13017 */ + 0x3153, /* VPSHUFBZ128rmk */ + 0x3156, /* VPSHUFBZ128rrk */ +/* Table13019 */ + 0x2982, /* VPMADDUBSWZ128rmk */ + 0x2985, /* VPMADDUBSWZ128rrk */ +/* Table13021 */ + 0x2d9d, /* VPMULHRSWZ128rmk */ + 0x2da0, /* VPMULHRSWZ128rrk */ +/* Table13023 */ + 0x2716, /* VPERMILPSZ128rmk */ + 0x2719, /* VPERMILPSZ128rrk */ +/* Table13025 */ + 0xee8, /* VCVTPH2PSZ128rmk */ + 0xeeb, /* VCVTPH2PSZ128rrk */ +/* Table13027 */ + 0x2fa4, /* VPRORVDZ128rmk */ + 0x2fa7, /* VPRORVDZ128rrk */ +/* Table13029 */ + 0x2f38, /* VPROLVDZ128rmk */ + 0x2f3b, /* VPROLVDZ128rrk */ +/* Table13031 */ + 0xd3b, /* VBROADCASTSSZ128mk */ + 0xd3e, /* VBROADCASTSSZ128rk */ +/* Table13033 */ + 0x2030, /* VPABSBZ128rmk */ + 0x2033, /* VPABSBZ128rrk */ +/* Table13035 */ + 0x2080, /* VPABSWZ128rmk */ + 0x2083, /* VPABSWZ128rrk */ +/* Table13037 */ + 0x2049, /* VPABSDZ128rmk */ + 0x204c, /* VPABSDZ128rrk */ +/* Table13039 */ + 0x2c36, /* VPMOVSXBWZ128rmk */ + 0x2c39, /* VPMOVSXBWZ128rrk */ +/* Table13041 */ + 0x2c0a, /* VPMOVSXBDZ128rmk */ + 0x2c0d, /* VPMOVSXBDZ128rrk */ +/* Table13043 */ + 0x2c20, /* VPMOVSXBQZ128rmk */ + 0x2c23, /* VPMOVSXBQZ128rrk */ +/* Table13045 */ + 0x2c62, /* VPMOVSXWDZ128rmk */ + 0x2c65, /* VPMOVSXWDZ128rrk */ +/* Table13047 */ + 0x2c78, /* VPMOVSXWQZ128rmk */ + 0x2c7b, /* VPMOVSXWQZ128rrk */ +/* Table13049 */ + 0x2c4c, /* VPMOVSXDQZ128rmk */ + 0x2c4f, /* VPMOVSXDQZ128rrk */ +/* Table13051 */ + 0x355c, /* VPTESTMBZ128rmk */ + 0x355e, /* VPTESTMBZ128rrk */ +/* Table13053 */ + 0x356a, /* VPTESTMDZ128rmk */ + 0x356c, /* VPTESTMDZ128rrk */ +/* Table13055 */ + 0x20ce, /* VPACKUSDWZ128rmk */ + 0x20d1, /* VPACKUSDWZ128rrk */ +/* Table13057 */ + 0x38ed, /* VSCALEFPSZ128rmk */ + 0x38f0, /* VSCALEFPSZ128rrk */ +/* Table13059 */ + 0x3911, /* VSCALEFSSZrmk */ + 0x3917, /* VSCALEFSSZrrk */ +/* Table13061 */ + 0x2d26, /* VPMOVZXBWZ128rmk */ + 0x2d29, /* VPMOVZXBWZ128rrk */ +/* Table13063 */ + 0x2cfa, /* VPMOVZXBDZ128rmk */ + 0x2cfd, /* VPMOVZXBDZ128rrk */ +/* Table13065 */ + 0x2d10, /* VPMOVZXBQZ128rmk */ + 0x2d13, /* VPMOVZXBQZ128rrk */ +/* Table13067 */ + 0x2d52, /* VPMOVZXWDZ128rmk */ + 0x2d55, /* VPMOVZXWDZ128rrk */ +/* Table13069 */ + 0x2d68, /* VPMOVZXWQZ128rmk */ + 0x2d6b, /* VPMOVZXWQZ128rrk */ +/* Table13071 */ + 0x2d3c, /* VPMOVZXDQZ128rmk */ + 0x2d3f, /* VPMOVZXDQZ128rrk */ +/* Table13073 */ + 0x2a82, /* VPMINSBZ128rmk */ + 0x2a85, /* VPMINSBZ128rrk */ +/* Table13075 */ + 0x2a9b, /* VPMINSDZ128rmk */ + 0x2a9e, /* VPMINSDZ128rrk */ +/* Table13077 */ + 0x2b38, /* VPMINUWZ128rmk */ + 0x2b3b, /* VPMINUWZ128rrk */ +/* Table13079 */ + 0x2b01, /* VPMINUDZ128rmk */ + 0x2b04, /* VPMINUDZ128rrk */ +/* Table13081 */ + 0x29b6, /* VPMAXSBZ128rmk */ + 0x29b9, /* VPMAXSBZ128rrk */ +/* Table13083 */ + 0x29cf, /* VPMAXSDZ128rmk */ + 0x29d2, /* VPMAXSDZ128rrk */ +/* Table13085 */ + 0x2a6c, /* VPMAXUWZ128rmk */ + 0x2a6f, /* VPMAXUWZ128rrk */ +/* Table13087 */ + 0x2a35, /* VPMAXUDZ128rmk */ + 0x2a38, /* VPMAXUDZ128rrk */ +/* Table13089 */ + 0x2de2, /* VPMULLDZ128rmk */ + 0x2de5, /* VPMULLDZ128rrk */ +/* Table13091 */ + 0x1ab2, /* VGETEXPPSZ128mk */ + 0x1ab5, /* VGETEXPPSZ128rk */ +/* Table13093 */ + 0x1ad6, /* VGETEXPSSZmk */ + 0x1adc, /* VGETEXPSSZrk */ +/* Table13095 */ + 0x28ff, /* VPLZCNTDZ128rmk */ + 0x2902, /* VPLZCNTDZ128rrk */ +/* Table13097 */ + 0x33ef, /* VPSRLVDZ128rmk */ + 0x33f2, /* VPSRLVDZ128rrk */ +/* Table13099 */ + 0x330b, /* VPSRAVDZ128rmk */ + 0x330e, /* VPSRAVDZ128rrk */ +/* Table13101 */ + 0x3231, /* VPSLLVDZ128rmk */ + 0x3234, /* VPSLLVDZ128rrk */ +/* Table13103 */ + 0x3752, /* VRCP14PSZ128mk */ + 0x3755, /* VRCP14PSZ128rk */ +/* Table13105 */ + 0x3770, /* VRCP14SSZrmk */ + 0x3773, /* VRCP14SSZrrk */ +/* Table13107 */ + 0x3876, /* VRSQRT14PSZ128mk */ + 0x3879, /* VRSQRT14PSZ128rk */ +/* Table13109 */ + 0x3894, /* VRSQRT14SSZrmk */ + 0x3897, /* VRSQRT14SSZrrk */ +/* Table13111 */ + 0x25b0, /* VPDPBUSDZ128mk */ + 0x25b3, /* VPDPBUSDZ128rk */ +/* Table13113 */ + 0x2595, /* VPDPBUSDSZ128mk */ + 0x2598, /* VPDPBUSDSZ128rk */ +/* Table13115 */ + 0x25e6, /* VPDPWSSDZ128mk */ + 0x25e9, /* VPDPWSSDZ128rk */ +/* Table13117 */ + 0x25cb, /* VPDPWSSDSZ128mk */ + 0x25ce, /* VPDPWSSDSZ128rk */ +/* Table13119 */ + 0x2e67, /* VPOPCNTBZ128rmk */ + 0x2e6a, /* VPOPCNTBZ128rrk */ +/* Table13121 */ + 0x2e7c, /* VPOPCNTDZ128rmk */ + 0x2e7f, /* VPOPCNTDZ128rrk */ +/* Table13123 */ + 0x22fd, /* VPBROADCASTDZ128mk */ + 0x2300, /* VPBROADCASTDZ128rk */ +/* Table13125 */ + 0xd07, /* VBROADCASTI32X2Z128mk */ + 0xd0a, /* VBROADCASTI32X2Z128rk */ +/* Table13127 */ + 0x2846, /* VPEXPANDBZ128rmk */ + 0x2849, /* VPEXPANDBZ128rrk */ +/* Table13129 */ + 0x2508, /* VPCOMPRESSBZ128mrk */ + 0x250a, /* VPCOMPRESSBZ128rrk */ +/* Table13131 */ + 0x228f, /* VPBLENDMDZ128rmk */ + 0x2292, /* VPBLENDMDZ128rrk */ +/* Table13133 */ + 0xcbf, /* VBLENDMPSZ128rmk */ + 0xcc2, /* VBLENDMPSZ128rrk */ +/* Table13135 */ + 0x227a, /* VPBLENDMBZ128rmk */ + 0x227d, /* VPBLENDMBZ128rrk */ +/* Table13137 */ + 0x3052, /* VPSHLDVDZ128mk */ + 0x3055, /* VPSHLDVDZ128rk */ +/* Table13139 */ + 0x30ee, /* VPSHRDVDZ128mk */ + 0x30f1, /* VPSHRDVDZ128rk */ +/* Table13141 */ + 0x2628, /* VPERMI2B128rmk */ + 0x262b, /* VPERMI2B128rrk */ +/* Table13143 */ + 0x263d, /* VPERMI2D128rmk */ + 0x2640, /* VPERMI2D128rrk */ +/* Table13145 */ + 0x2673, /* VPERMI2PS128rmk */ + 0x2676, /* VPERMI2PS128rrk */ +/* Table13147 */ + 0x22de, /* VPBROADCASTBZ128mk */ + 0x22e1, /* VPBROADCASTBZ128rk */ +/* Table13149 */ + 0x2341, /* VPBROADCASTWZ128mk */ + 0x2344, /* VPBROADCASTWZ128rk */ +/* Table13151 */ + 0x0, /* */ + 0x22f0, /* VPBROADCASTBrZ128rk */ +/* Table13153 */ + 0x0, /* */ + 0x2353, /* VPBROADCASTWrZ128rk */ +/* Table13155 */ + 0x0, /* */ + 0x230f, /* VPBROADCASTDrZ128rk */ +/* Table13157 */ + 0x27a4, /* VPERMT2B128rmk */ + 0x27a7, /* VPERMT2B128rrk */ +/* Table13159 */ + 0x27b9, /* VPERMT2D128rmk */ + 0x27bc, /* VPERMT2D128rrk */ +/* Table13161 */ + 0x27ef, /* VPERMT2PS128rmk */ + 0x27f2, /* VPERMT2PS128rrk */ +/* Table13163 */ + 0x12b1, /* VEXPANDPSZ128rmk */ + 0x12b4, /* VEXPANDPSZ128rrk */ +/* Table13165 */ + 0x2858, /* VPEXPANDDZ128rmk */ + 0x285b, /* VPEXPANDDZ128rrk */ +/* Table13167 */ + 0xdf8, /* VCOMPRESSPSZ128mrk */ + 0xdfa, /* VCOMPRESSPSZ128rrk */ +/* Table13169 */ + 0x2517, /* VPCOMPRESSDZ128mrk */ + 0x2519, /* VPCOMPRESSDZ128rrk */ +/* Table13171 */ + 0x2602, /* VPERMBZ128rmk */ + 0x2605, /* VPERMBZ128rrk */ +/* Table13173 */ + 0x3145, /* VPSHUFBITQMBZ128rmk */ + 0x3147, /* VPSHUFBITQMBZ128rrk */ +/* Table13175 */ + 0x28a0, /* VPGATHERDDZ128rm */ + 0x0, /* */ +/* Table13177 */ + 0x28aa, /* VPGATHERQDZ128rm */ + 0x0, /* */ +/* Table13179 */ + 0x1a7a, /* VGATHERDPSZ128rm */ + 0x0, /* */ +/* Table13181 */ + 0x1a8c, /* VGATHERQPSZ128rm */ + 0x0, /* */ +/* Table13183 */ + 0x14c8, /* VFMADDSUB132PSZ128mk */ + 0x14cb, /* VFMADDSUB132PSZ128rk */ +/* Table13185 */ + 0x16d0, /* VFMSUBADD132PSZ128mk */ + 0x16d3, /* VFMSUBADD132PSZ128rk */ +/* Table13187 */ + 0x137c, /* VFMADD132PSZ128mk */ + 0x137f, /* VFMADD132PSZ128rk */ +/* Table13189 */ + 0x13aa, /* VFMADD132SSZm_Intk */ + 0x13ae, /* VFMADD132SSZr_Intk */ +/* Table13191 */ + 0x15a4, /* VFMSUB132PSZ128mk */ + 0x15a7, /* VFMSUB132PSZ128rk */ +/* Table13193 */ + 0x15d2, /* VFMSUB132SSZm_Intk */ + 0x15d6, /* VFMSUB132SSZr_Intk */ +/* Table13195 */ + 0x17cc, /* VFNMADD132PSZ128mk */ + 0x17cf, /* VFNMADD132PSZ128rk */ +/* Table13197 */ + 0x17fa, /* VFNMADD132SSZm_Intk */ + 0x17fe, /* VFNMADD132SSZr_Intk */ +/* Table13199 */ + 0x1918, /* VFNMSUB132PSZ128mk */ + 0x191b, /* VFNMSUB132PSZ128rk */ +/* Table13201 */ + 0x1946, /* VFNMSUB132SSZm_Intk */ + 0x194a, /* VFNMSUB132SSZr_Intk */ +/* Table13203 */ + 0x2ff8, /* VPSCATTERDDZ128mr */ + 0x0, /* */ +/* Table13205 */ + 0x2ffe, /* VPSCATTERQDZ128mr */ + 0x0, /* */ +/* Table13207 */ + 0x391c, /* VSCATTERDPSZ128mr */ + 0x0, /* */ +/* Table13209 */ + 0x392a, /* VSCATTERQPSZ128mr */ + 0x0, /* */ +/* Table13211 */ + 0x150c, /* VFMADDSUB213PSZ128mk */ + 0x150f, /* VFMADDSUB213PSZ128rk */ +/* Table13213 */ + 0x1714, /* VFMSUBADD213PSZ128mk */ + 0x1717, /* VFMSUBADD213PSZ128rk */ +/* Table13215 */ + 0x13e0, /* VFMADD213PSZ128mk */ + 0x13e3, /* VFMADD213PSZ128rk */ +/* Table13217 */ + 0x140e, /* VFMADD213SSZm_Intk */ + 0x1412, /* VFMADD213SSZr_Intk */ +/* Table13219 */ + 0x1608, /* VFMSUB213PSZ128mk */ + 0x160b, /* VFMSUB213PSZ128rk */ +/* Table13221 */ + 0x1636, /* VFMSUB213SSZm_Intk */ + 0x163a, /* VFMSUB213SSZr_Intk */ +/* Table13223 */ + 0x1830, /* VFNMADD213PSZ128mk */ + 0x1833, /* VFNMADD213PSZ128rk */ +/* Table13225 */ + 0x185e, /* VFNMADD213SSZm_Intk */ + 0x1862, /* VFNMADD213SSZr_Intk */ +/* Table13227 */ + 0x197c, /* VFNMSUB213PSZ128mk */ + 0x197f, /* VFNMSUB213PSZ128rk */ +/* Table13229 */ + 0x19aa, /* VFNMSUB213SSZm_Intk */ + 0x19ae, /* VFNMSUB213SSZr_Intk */ +/* Table13231 */ + 0x1550, /* VFMADDSUB231PSZ128mk */ + 0x1553, /* VFMADDSUB231PSZ128rk */ +/* Table13233 */ + 0x1758, /* VFMSUBADD231PSZ128mk */ + 0x175b, /* VFMSUBADD231PSZ128rk */ +/* Table13235 */ + 0x1444, /* VFMADD231PSZ128mk */ + 0x1447, /* VFMADD231PSZ128rk */ +/* Table13237 */ + 0x1472, /* VFMADD231SSZm_Intk */ + 0x1476, /* VFMADD231SSZr_Intk */ +/* Table13239 */ + 0x166c, /* VFMSUB231PSZ128mk */ + 0x166f, /* VFMSUB231PSZ128rk */ +/* Table13241 */ + 0x169a, /* VFMSUB231SSZm_Intk */ + 0x169e, /* VFMSUB231SSZr_Intk */ +/* Table13243 */ + 0x1894, /* VFNMADD231PSZ128mk */ + 0x1897, /* VFNMADD231PSZ128rk */ +/* Table13245 */ + 0x18c2, /* VFNMADD231SSZm_Intk */ + 0x18c6, /* VFNMADD231SSZr_Intk */ +/* Table13247 */ + 0x19e0, /* VFNMSUB231PSZ128mk */ + 0x19e3, /* VFNMSUB231PSZ128rk */ +/* Table13249 */ + 0x1a0e, /* VFNMSUB231SSZm_Intk */ + 0x1a12, /* VFNMSUB231SSZr_Intk */ +/* Table13251 */ + 0x255f, /* VPCONFLICTDZ128rmk */ + 0x2562, /* VPCONFLICTDZ128rrk */ +/* Table13253 */ + 0x3797, /* VRCP28SSZmk */ + 0x379d, /* VRCP28SSZrk */ +/* Table13255 */ + 0x38bb, /* VRSQRT28SSZmk */ + 0x38c1, /* VRSQRT28SSZrk */ +/* Table13257 */ + 0x1b6d, /* VGF2P8MULBZ128rmk */ + 0x1b70, /* VGF2P8MULBZ128rrk */ +/* Table13259 */ + 0x35c8, /* VPTESTNMWZ128rmk */ + 0x35ca, /* VPTESTNMWZ128rrk */ +/* Table13261 */ + 0x35b8, /* VPTESTNMQZ128rmk */ + 0x35ba, /* VPTESTNMQZ128rrk */ +/* Table13263 */ + 0x26d8, /* VPERMILPDZ128rmk */ + 0x26db, /* VPERMILPDZ128rrk */ +/* Table13265 */ + 0x3428, /* VPSRLVWZ128rmk */ + 0x342b, /* VPSRLVWZ128rrk */ +/* Table13267 */ + 0x3340, /* VPSRAVWZ128rmk */ + 0x3343, /* VPSRAVWZ128rrk */ +/* Table13269 */ + 0x326a, /* VPSLLVWZ128rmk */ + 0x326d, /* VPSLLVWZ128rrk */ +/* Table13271 */ + 0x2fbf, /* VPRORVQZ128rmk */ + 0x2fc2, /* VPRORVQZ128rrk */ +/* Table13273 */ + 0x2f53, /* VPROLVQZ128rmk */ + 0x2f56, /* VPROLVQZ128rrk */ +/* Table13275 */ + 0x2066, /* VPABSQZ128rmk */ + 0x2069, /* VPABSQZ128rrk */ +/* Table13277 */ + 0x358c, /* VPTESTMWZ128rmk */ + 0x358e, /* VPTESTMWZ128rrk */ +/* Table13279 */ + 0x357c, /* VPTESTMQZ128rmk */ + 0x357e, /* VPTESTMQZ128rrk */ +/* Table13281 */ + 0x2d81, /* VPMULDQZ128rmk */ + 0x2d84, /* VPMULDQZ128rrk */ +/* Table13283 */ + 0x23d6, /* VPCMPEQQZ128rmk */ + 0x23d8, /* VPCMPEQQZ128rrk */ +/* Table13285 */ + 0x38cf, /* VSCALEFPDZ128rmk */ + 0x38d2, /* VSCALEFPDZ128rrk */ +/* Table13287 */ + 0x3908, /* VSCALEFSDZrmk */ + 0x390e, /* VSCALEFSDZrrk */ +/* Table13289 */ + 0x2426, /* VPCMPGTQZ128rmk */ + 0x2428, /* VPCMPGTQZ128rrk */ +/* Table13291 */ + 0x2ab8, /* VPMINSQZ128rmk */ + 0x2abb, /* VPMINSQZ128rrk */ +/* Table13293 */ + 0x2b1e, /* VPMINUQZ128rmk */ + 0x2b21, /* VPMINUQZ128rrk */ +/* Table13295 */ + 0x29ec, /* VPMAXSQZ128rmk */ + 0x29ef, /* VPMAXSQZ128rrk */ +/* Table13297 */ + 0x2a52, /* VPMAXUQZ128rmk */ + 0x2a55, /* VPMAXUQZ128rrk */ +/* Table13299 */ + 0x2dff, /* VPMULLQZ128rmk */ + 0x2e02, /* VPMULLQZ128rrk */ +/* Table13301 */ + 0x1a94, /* VGETEXPPDZ128mk */ + 0x1a97, /* VGETEXPPDZ128rk */ +/* Table13303 */ + 0x1acd, /* VGETEXPSDZmk */ + 0x1ad3, /* VGETEXPSDZrk */ +/* Table13305 */ + 0x291a, /* VPLZCNTQZ128rmk */ + 0x291d, /* VPLZCNTQZ128rrk */ +/* Table13307 */ + 0x340e, /* VPSRLVQZ128rmk */ + 0x3411, /* VPSRLVQZ128rrk */ +/* Table13309 */ + 0x3328, /* VPSRAVQZ128rmk */ + 0x332b, /* VPSRAVQZ128rrk */ +/* Table13311 */ + 0x3250, /* VPSLLVQZ128rmk */ + 0x3253, /* VPSLLVQZ128rrk */ +/* Table13313 */ + 0x3737, /* VRCP14PDZ128mk */ + 0x373a, /* VRCP14PDZ128rk */ +/* Table13315 */ + 0x376a, /* VRCP14SDZrmk */ + 0x376d, /* VRCP14SDZrrk */ +/* Table13317 */ + 0x385b, /* VRSQRT14PDZ128mk */ + 0x385e, /* VRSQRT14PDZ128rk */ +/* Table13319 */ + 0x388e, /* VRSQRT14SDZrmk */ + 0x3891, /* VRSQRT14SDZrrk */ +/* Table13321 */ + 0x2eaf, /* VPOPCNTWZ128rmk */ + 0x2eb2, /* VPOPCNTWZ128rrk */ +/* Table13323 */ + 0x2e97, /* VPOPCNTQZ128rmk */ + 0x2e9a, /* VPOPCNTQZ128rrk */ +/* Table13325 */ + 0x2322, /* VPBROADCASTQZ128mk */ + 0x2325, /* VPBROADCASTQZ128rk */ +/* Table13327 */ + 0x287c, /* VPEXPANDWZ128rmk */ + 0x287f, /* VPEXPANDWZ128rrk */ +/* Table13329 */ + 0x2535, /* VPCOMPRESSWZ128mrk */ + 0x2537, /* VPCOMPRESSWZ128rrk */ +/* Table13331 */ + 0x22aa, /* VPBLENDMQZ128rmk */ + 0x22ad, /* VPBLENDMQZ128rrk */ +/* Table13333 */ + 0xca4, /* VBLENDMPDZ128rmk */ + 0xca7, /* VBLENDMPDZ128rrk */ +/* Table13335 */ + 0x22c2, /* VPBLENDMWZ128rmk */ + 0x22c5, /* VPBLENDMWZ128rrk */ +/* Table13337 */ + 0x3085, /* VPSHLDVWZ128mk */ + 0x3088, /* VPSHLDVWZ128rk */ +/* Table13339 */ + 0x306d, /* VPSHLDVQZ128mk */ + 0x3070, /* VPSHLDVQZ128rk */ +/* Table13341 */ + 0x3121, /* VPSHRDVWZ128mk */ + 0x3124, /* VPSHRDVWZ128rk */ +/* Table13343 */ + 0x3109, /* VPSHRDVQZ128mk */ + 0x310c, /* VPSHRDVQZ128rk */ +/* Table13345 */ + 0x26a6, /* VPERMI2W128rmk */ + 0x26a9, /* VPERMI2W128rrk */ +/* Table13347 */ + 0x268e, /* VPERMI2Q128rmk */ + 0x2691, /* VPERMI2Q128rrk */ +/* Table13349 */ + 0x2658, /* VPERMI2PD128rmk */ + 0x265b, /* VPERMI2PD128rrk */ +/* Table13351 */ + 0x0, /* */ + 0x2334, /* VPBROADCASTQrZ128rk */ +/* Table13353 */ + 0x2822, /* VPERMT2W128rmk */ + 0x2825, /* VPERMT2W128rrk */ +/* Table13355 */ + 0x280a, /* VPERMT2Q128rmk */ + 0x280d, /* VPERMT2Q128rrk */ +/* Table13357 */ + 0x27d4, /* VPERMT2PD128rmk */ + 0x27d7, /* VPERMT2PD128rrk */ +/* Table13359 */ + 0x2e30, /* VPMULTISHIFTQBZ128rmk */ + 0x2e33, /* VPMULTISHIFTQBZ128rrk */ +/* Table13361 */ + 0x129f, /* VEXPANDPDZ128rmk */ + 0x12a2, /* VEXPANDPDZ128rrk */ +/* Table13363 */ + 0x286a, /* VPEXPANDQZ128rmk */ + 0x286d, /* VPEXPANDQZ128rrk */ +/* Table13365 */ + 0xde9, /* VCOMPRESSPDZ128mrk */ + 0xdeb, /* VCOMPRESSPDZ128rrk */ +/* Table13367 */ + 0x2526, /* VPCOMPRESSQZ128mrk */ + 0x2528, /* VPCOMPRESSQZ128rrk */ +/* Table13369 */ + 0x2834, /* VPERMWZ128rmk */ + 0x2837, /* VPERMWZ128rrk */ +/* Table13371 */ + 0x28a5, /* VPGATHERDQZ128rm */ + 0x0, /* */ +/* Table13373 */ + 0x28af, /* VPGATHERQQZ128rm */ + 0x0, /* */ +/* Table13375 */ + 0x1a75, /* VGATHERDPDZ128rm */ + 0x0, /* */ +/* Table13377 */ + 0x1a87, /* VGATHERQPDZ128rm */ + 0x0, /* */ +/* Table13379 */ + 0x14a6, /* VFMADDSUB132PDZ128mk */ + 0x14a9, /* VFMADDSUB132PDZ128rk */ +/* Table13381 */ + 0x16ae, /* VFMSUBADD132PDZ128mk */ + 0x16b1, /* VFMSUBADD132PDZ128rk */ +/* Table13383 */ + 0x135a, /* VFMADD132PDZ128mk */ + 0x135d, /* VFMADD132PDZ128rk */ +/* Table13385 */ + 0x139a, /* VFMADD132SDZm_Intk */ + 0x139e, /* VFMADD132SDZr_Intk */ +/* Table13387 */ + 0x1582, /* VFMSUB132PDZ128mk */ + 0x1585, /* VFMSUB132PDZ128rk */ +/* Table13389 */ + 0x15c2, /* VFMSUB132SDZm_Intk */ + 0x15c6, /* VFMSUB132SDZr_Intk */ +/* Table13391 */ + 0x17aa, /* VFNMADD132PDZ128mk */ + 0x17ad, /* VFNMADD132PDZ128rk */ +/* Table13393 */ + 0x17ea, /* VFNMADD132SDZm_Intk */ + 0x17ee, /* VFNMADD132SDZr_Intk */ +/* Table13395 */ + 0x18f6, /* VFNMSUB132PDZ128mk */ + 0x18f9, /* VFNMSUB132PDZ128rk */ +/* Table13397 */ + 0x1936, /* VFNMSUB132SDZm_Intk */ + 0x193a, /* VFNMSUB132SDZr_Intk */ +/* Table13399 */ + 0x2ffb, /* VPSCATTERDQZ128mr */ + 0x0, /* */ +/* Table13401 */ + 0x3001, /* VPSCATTERQQZ128mr */ + 0x0, /* */ +/* Table13403 */ + 0x3919, /* VSCATTERDPDZ128mr */ + 0x0, /* */ +/* Table13405 */ + 0x3927, /* VSCATTERQPDZ128mr */ + 0x0, /* */ +/* Table13407 */ + 0x14ea, /* VFMADDSUB213PDZ128mk */ + 0x14ed, /* VFMADDSUB213PDZ128rk */ +/* Table13409 */ + 0x16f2, /* VFMSUBADD213PDZ128mk */ + 0x16f5, /* VFMSUBADD213PDZ128rk */ +/* Table13411 */ + 0x13be, /* VFMADD213PDZ128mk */ + 0x13c1, /* VFMADD213PDZ128rk */ +/* Table13413 */ + 0x13fe, /* VFMADD213SDZm_Intk */ + 0x1402, /* VFMADD213SDZr_Intk */ +/* Table13415 */ + 0x15e6, /* VFMSUB213PDZ128mk */ + 0x15e9, /* VFMSUB213PDZ128rk */ +/* Table13417 */ + 0x1626, /* VFMSUB213SDZm_Intk */ + 0x162a, /* VFMSUB213SDZr_Intk */ +/* Table13419 */ + 0x180e, /* VFNMADD213PDZ128mk */ + 0x1811, /* VFNMADD213PDZ128rk */ +/* Table13421 */ + 0x184e, /* VFNMADD213SDZm_Intk */ + 0x1852, /* VFNMADD213SDZr_Intk */ +/* Table13423 */ + 0x195a, /* VFNMSUB213PDZ128mk */ + 0x195d, /* VFNMSUB213PDZ128rk */ +/* Table13425 */ + 0x199a, /* VFNMSUB213SDZm_Intk */ + 0x199e, /* VFNMSUB213SDZr_Intk */ +/* Table13427 */ + 0x2968, /* VPMADD52LUQZ128mk */ + 0x296b, /* VPMADD52LUQZ128rk */ +/* Table13429 */ + 0x294d, /* VPMADD52HUQZ128mk */ + 0x2950, /* VPMADD52HUQZ128rk */ +/* Table13431 */ + 0x152e, /* VFMADDSUB231PDZ128mk */ + 0x1531, /* VFMADDSUB231PDZ128rk */ +/* Table13433 */ + 0x1736, /* VFMSUBADD231PDZ128mk */ + 0x1739, /* VFMSUBADD231PDZ128rk */ +/* Table13435 */ + 0x1422, /* VFMADD231PDZ128mk */ + 0x1425, /* VFMADD231PDZ128rk */ +/* Table13437 */ + 0x1462, /* VFMADD231SDZm_Intk */ + 0x1466, /* VFMADD231SDZr_Intk */ +/* Table13439 */ + 0x164a, /* VFMSUB231PDZ128mk */ + 0x164d, /* VFMSUB231PDZ128rk */ +/* Table13441 */ + 0x168a, /* VFMSUB231SDZm_Intk */ + 0x168e, /* VFMSUB231SDZr_Intk */ +/* Table13443 */ + 0x1872, /* VFNMADD231PDZ128mk */ + 0x1875, /* VFNMADD231PDZ128rk */ +/* Table13445 */ + 0x18b2, /* VFNMADD231SDZm_Intk */ + 0x18b6, /* VFNMADD231SDZr_Intk */ +/* Table13447 */ + 0x19be, /* VFNMSUB231PDZ128mk */ + 0x19c1, /* VFNMSUB231PDZ128rk */ +/* Table13449 */ + 0x19fe, /* VFNMSUB231SDZm_Intk */ + 0x1a02, /* VFNMSUB231SDZr_Intk */ +/* Table13451 */ + 0x257a, /* VPCONFLICTQZ128rmk */ + 0x257d, /* VPCONFLICTQZ128rrk */ +/* Table13453 */ + 0x378e, /* VRCP28SDZmk */ + 0x3794, /* VRCP28SDZrk */ +/* Table13455 */ + 0x38b2, /* VRSQRT28SDZmk */ + 0x38b8, /* VRSQRT28SDZrk */ +/* Table13457 */ + 0x2cdc, /* VPMOVUSWBZ256mrk */ + 0x2cde, /* VPMOVUSWBZ256rrk */ +/* Table13459 */ + 0x2c91, /* VPMOVUSDBZ256mrk */ + 0x2c93, /* VPMOVUSDBZ256rrk */ +/* Table13461 */ + 0x2caf, /* VPMOVUSQBZ256mrk */ + 0x2cb1, /* VPMOVUSQBZ256rrk */ +/* Table13463 */ + 0x2ca0, /* VPMOVUSDWZ256mrk */ + 0x2ca2, /* VPMOVUSDWZ256rrk */ +/* Table13465 */ + 0x2ccd, /* VPMOVUSQWZ256mrk */ + 0x2ccf, /* VPMOVUSQWZ256rrk */ +/* Table13467 */ + 0x2cbe, /* VPMOVUSQDZ256mrk */ + 0x2cc0, /* VPMOVUSQDZ256rrk */ +/* Table13469 */ + 0x2bfe, /* VPMOVSWBZ256mrk */ + 0x2c00, /* VPMOVSWBZ256rrk */ +/* Table13471 */ + 0x2bb3, /* VPMOVSDBZ256mrk */ + 0x2bb5, /* VPMOVSDBZ256rrk */ +/* Table13473 */ + 0x2bd1, /* VPMOVSQBZ256mrk */ + 0x2bd3, /* VPMOVSQBZ256rrk */ +/* Table13475 */ + 0x2bc2, /* VPMOVSDWZ256mrk */ + 0x2bc4, /* VPMOVSDWZ256rrk */ +/* Table13477 */ + 0x2bef, /* VPMOVSQWZ256mrk */ + 0x2bf1, /* VPMOVSQWZ256rrk */ +/* Table13479 */ + 0x2be0, /* VPMOVSQDZ256mrk */ + 0x2be2, /* VPMOVSQDZ256rrk */ +/* Table13481 */ + 0x359c, /* VPTESTNMBZ256rmk */ + 0x359e, /* VPTESTNMBZ256rrk */ +/* Table13483 */ + 0x35ac, /* VPTESTNMDZ256rmk */ + 0x35ae, /* VPTESTNMDZ256rrk */ +/* Table13485 */ + 0x2cee, /* VPMOVWBZ256mrk */ + 0x2cf0, /* VPMOVWBZ256rrk */ +/* Table13487 */ + 0x2b57, /* VPMOVDBZ256mrk */ + 0x2b59, /* VPMOVDBZ256rrk */ +/* Table13489 */ + 0x2b86, /* VPMOVQBZ256mrk */ + 0x2b88, /* VPMOVQBZ256rrk */ +/* Table13491 */ + 0x2b66, /* VPMOVDWZ256mrk */ + 0x2b68, /* VPMOVDWZ256rrk */ +/* Table13493 */ + 0x2ba4, /* VPMOVQWZ256mrk */ + 0x2ba6, /* VPMOVQWZ256rrk */ +/* Table13495 */ + 0x2b95, /* VPMOVQDZ256mrk */ + 0x2b97, /* VPMOVQDZ256rrk */ +/* Table13497 */ + 0x3159, /* VPSHUFBZ256rmk */ + 0x315c, /* VPSHUFBZ256rrk */ +/* Table13499 */ + 0x2988, /* VPMADDUBSWZ256rmk */ + 0x298b, /* VPMADDUBSWZ256rrk */ +/* Table13501 */ + 0x2da3, /* VPMULHRSWZ256rmk */ + 0x2da6, /* VPMULHRSWZ256rrk */ +/* Table13503 */ + 0x2728, /* VPERMILPSZ256rmk */ + 0x272b, /* VPERMILPSZ256rrk */ +/* Table13505 */ + 0xeee, /* VCVTPH2PSZ256rmk */ + 0xef1, /* VCVTPH2PSZ256rrk */ +/* Table13507 */ + 0x2fad, /* VPRORVDZ256rmk */ + 0x2fb0, /* VPRORVDZ256rrk */ +/* Table13509 */ + 0x2f41, /* VPROLVDZ256rmk */ + 0x2f44, /* VPROLVDZ256rrk */ +/* Table13511 */ + 0x276f, /* VPERMPSZ256rmk */ + 0x2772, /* VPERMPSZ256rrk */ +/* Table13513 */ + 0xd41, /* VBROADCASTSSZ256mk */ + 0xd44, /* VBROADCASTSSZ256rk */ +/* Table13515 */ + 0xce8, /* VBROADCASTF32X2Z256mk */ + 0xceb, /* VBROADCASTF32X2Z256rk */ +/* Table13517 */ + 0xcf4, /* VBROADCASTF32X4Z256rmk */ + 0x0, /* */ +/* Table13519 */ + 0x2036, /* VPABSBZ256rmk */ + 0x2039, /* VPABSBZ256rrk */ +/* Table13521 */ + 0x2086, /* VPABSWZ256rmk */ + 0x2089, /* VPABSWZ256rrk */ +/* Table13523 */ + 0x2052, /* VPABSDZ256rmk */ + 0x2055, /* VPABSDZ256rrk */ +/* Table13525 */ + 0x2c3c, /* VPMOVSXBWZ256rmk */ + 0x2c3f, /* VPMOVSXBWZ256rrk */ +/* Table13527 */ + 0x2c10, /* VPMOVSXBDZ256rmk */ + 0x2c13, /* VPMOVSXBDZ256rrk */ +/* Table13529 */ + 0x2c26, /* VPMOVSXBQZ256rmk */ + 0x2c29, /* VPMOVSXBQZ256rrk */ +/* Table13531 */ + 0x2c68, /* VPMOVSXWDZ256rmk */ + 0x2c6b, /* VPMOVSXWDZ256rrk */ +/* Table13533 */ + 0x2c7e, /* VPMOVSXWQZ256rmk */ + 0x2c81, /* VPMOVSXWQZ256rrk */ +/* Table13535 */ + 0x2c52, /* VPMOVSXDQZ256rmk */ + 0x2c55, /* VPMOVSXDQZ256rrk */ +/* Table13537 */ + 0x3560, /* VPTESTMBZ256rmk */ + 0x3562, /* VPTESTMBZ256rrk */ +/* Table13539 */ + 0x3570, /* VPTESTMDZ256rmk */ + 0x3572, /* VPTESTMDZ256rrk */ +/* Table13541 */ + 0x20d7, /* VPACKUSDWZ256rmk */ + 0x20da, /* VPACKUSDWZ256rrk */ +/* Table13543 */ + 0x38f6, /* VSCALEFPSZ256rmk */ + 0x38f9, /* VSCALEFPSZ256rrk */ +/* Table13545 */ + 0x2d2c, /* VPMOVZXBWZ256rmk */ + 0x2d2f, /* VPMOVZXBWZ256rrk */ +/* Table13547 */ + 0x2d00, /* VPMOVZXBDZ256rmk */ + 0x2d03, /* VPMOVZXBDZ256rrk */ +/* Table13549 */ + 0x2d16, /* VPMOVZXBQZ256rmk */ + 0x2d19, /* VPMOVZXBQZ256rrk */ +/* Table13551 */ + 0x2d58, /* VPMOVZXWDZ256rmk */ + 0x2d5b, /* VPMOVZXWDZ256rrk */ +/* Table13553 */ + 0x2d6e, /* VPMOVZXWQZ256rmk */ + 0x2d71, /* VPMOVZXWQZ256rrk */ +/* Table13555 */ + 0x2d42, /* VPMOVZXDQZ256rmk */ + 0x2d45, /* VPMOVZXDQZ256rrk */ +/* Table13557 */ + 0x2619, /* VPERMDZ256rmk */ + 0x261c, /* VPERMDZ256rrk */ +/* Table13559 */ + 0x2a88, /* VPMINSBZ256rmk */ + 0x2a8b, /* VPMINSBZ256rrk */ +/* Table13561 */ + 0x2aa4, /* VPMINSDZ256rmk */ + 0x2aa7, /* VPMINSDZ256rrk */ +/* Table13563 */ + 0x2b3e, /* VPMINUWZ256rmk */ + 0x2b41, /* VPMINUWZ256rrk */ +/* Table13565 */ + 0x2b0a, /* VPMINUDZ256rmk */ + 0x2b0d, /* VPMINUDZ256rrk */ +/* Table13567 */ + 0x29bc, /* VPMAXSBZ256rmk */ + 0x29bf, /* VPMAXSBZ256rrk */ +/* Table13569 */ + 0x29d8, /* VPMAXSDZ256rmk */ + 0x29db, /* VPMAXSDZ256rrk */ +/* Table13571 */ + 0x2a72, /* VPMAXUWZ256rmk */ + 0x2a75, /* VPMAXUWZ256rrk */ +/* Table13573 */ + 0x2a3e, /* VPMAXUDZ256rmk */ + 0x2a41, /* VPMAXUDZ256rrk */ +/* Table13575 */ + 0x2deb, /* VPMULLDZ256rmk */ + 0x2dee, /* VPMULLDZ256rrk */ +/* Table13577 */ + 0x1abb, /* VGETEXPPSZ256mk */ + 0x1abe, /* VGETEXPPSZ256rk */ +/* Table13579 */ + 0x2908, /* VPLZCNTDZ256rmk */ + 0x290b, /* VPLZCNTDZ256rrk */ +/* Table13581 */ + 0x33f8, /* VPSRLVDZ256rmk */ + 0x33fb, /* VPSRLVDZ256rrk */ +/* Table13583 */ + 0x3314, /* VPSRAVDZ256rmk */ + 0x3317, /* VPSRAVDZ256rrk */ +/* Table13585 */ + 0x323a, /* VPSLLVDZ256rmk */ + 0x323d, /* VPSLLVDZ256rrk */ +/* Table13587 */ + 0x375b, /* VRCP14PSZ256mk */ + 0x375e, /* VRCP14PSZ256rk */ +/* Table13589 */ + 0x387f, /* VRSQRT14PSZ256mk */ + 0x3882, /* VRSQRT14PSZ256rk */ +/* Table13591 */ + 0x25b9, /* VPDPBUSDZ256mk */ + 0x25bc, /* VPDPBUSDZ256rk */ +/* Table13593 */ + 0x259e, /* VPDPBUSDSZ256mk */ + 0x25a1, /* VPDPBUSDSZ256rk */ +/* Table13595 */ + 0x25ef, /* VPDPWSSDZ256mk */ + 0x25f2, /* VPDPWSSDZ256rk */ +/* Table13597 */ + 0x25d4, /* VPDPWSSDSZ256mk */ + 0x25d7, /* VPDPWSSDSZ256rk */ +/* Table13599 */ + 0x2e6d, /* VPOPCNTBZ256rmk */ + 0x2e70, /* VPOPCNTBZ256rrk */ +/* Table13601 */ + 0x2e85, /* VPOPCNTDZ256rmk */ + 0x2e88, /* VPOPCNTDZ256rrk */ +/* Table13603 */ + 0x2303, /* VPBROADCASTDZ256mk */ + 0x2306, /* VPBROADCASTDZ256rk */ +/* Table13605 */ + 0xd0d, /* VBROADCASTI32X2Z256mk */ + 0xd10, /* VBROADCASTI32X2Z256rk */ +/* Table13607 */ + 0xd19, /* VBROADCASTI32X4Z256rmk */ + 0x0, /* */ +/* Table13609 */ + 0x284c, /* VPEXPANDBZ256rmk */ + 0x284f, /* VPEXPANDBZ256rrk */ +/* Table13611 */ + 0x250d, /* VPCOMPRESSBZ256mrk */ + 0x250f, /* VPCOMPRESSBZ256rrk */ +/* Table13613 */ + 0x2298, /* VPBLENDMDZ256rmk */ + 0x229b, /* VPBLENDMDZ256rrk */ +/* Table13615 */ + 0xcc8, /* VBLENDMPSZ256rmk */ + 0xccb, /* VBLENDMPSZ256rrk */ +/* Table13617 */ + 0x2280, /* VPBLENDMBZ256rmk */ + 0x2283, /* VPBLENDMBZ256rrk */ +/* Table13619 */ + 0x305b, /* VPSHLDVDZ256mk */ + 0x305e, /* VPSHLDVDZ256rk */ +/* Table13621 */ + 0x30f7, /* VPSHRDVDZ256mk */ + 0x30fa, /* VPSHRDVDZ256rk */ +/* Table13623 */ + 0x262e, /* VPERMI2B256rmk */ + 0x2631, /* VPERMI2B256rrk */ +/* Table13625 */ + 0x2646, /* VPERMI2D256rmk */ + 0x2649, /* VPERMI2D256rrk */ +/* Table13627 */ + 0x267c, /* VPERMI2PS256rmk */ + 0x267f, /* VPERMI2PS256rrk */ +/* Table13629 */ + 0x22e4, /* VPBROADCASTBZ256mk */ + 0x22e7, /* VPBROADCASTBZ256rk */ +/* Table13631 */ + 0x2347, /* VPBROADCASTWZ256mk */ + 0x234a, /* VPBROADCASTWZ256rk */ +/* Table13633 */ + 0x0, /* */ + 0x22f3, /* VPBROADCASTBrZ256rk */ +/* Table13635 */ + 0x0, /* */ + 0x2356, /* VPBROADCASTWrZ256rk */ +/* Table13637 */ + 0x0, /* */ + 0x2312, /* VPBROADCASTDrZ256rk */ +/* Table13639 */ + 0x27aa, /* VPERMT2B256rmk */ + 0x27ad, /* VPERMT2B256rrk */ +/* Table13641 */ + 0x27c2, /* VPERMT2D256rmk */ + 0x27c5, /* VPERMT2D256rrk */ +/* Table13643 */ + 0x27f8, /* VPERMT2PS256rmk */ + 0x27fb, /* VPERMT2PS256rrk */ +/* Table13645 */ + 0x12b7, /* VEXPANDPSZ256rmk */ + 0x12ba, /* VEXPANDPSZ256rrk */ +/* Table13647 */ + 0x285e, /* VPEXPANDDZ256rmk */ + 0x2861, /* VPEXPANDDZ256rrk */ +/* Table13649 */ + 0xdfd, /* VCOMPRESSPSZ256mrk */ + 0xdff, /* VCOMPRESSPSZ256rrk */ +/* Table13651 */ + 0x251c, /* VPCOMPRESSDZ256mrk */ + 0x251e, /* VPCOMPRESSDZ256rrk */ +/* Table13653 */ + 0x2608, /* VPERMBZ256rmk */ + 0x260b, /* VPERMBZ256rrk */ +/* Table13655 */ + 0x3149, /* VPSHUFBITQMBZ256rmk */ + 0x314b, /* VPSHUFBITQMBZ256rrk */ +/* Table13657 */ + 0x28a1, /* VPGATHERDDZ256rm */ + 0x0, /* */ +/* Table13659 */ + 0x28ab, /* VPGATHERQDZ256rm */ + 0x0, /* */ +/* Table13661 */ + 0x1a7b, /* VGATHERDPSZ256rm */ + 0x0, /* */ +/* Table13663 */ + 0x1a8d, /* VGATHERQPSZ256rm */ + 0x0, /* */ +/* Table13665 */ + 0x14d1, /* VFMADDSUB132PSZ256mk */ + 0x14d4, /* VFMADDSUB132PSZ256rk */ +/* Table13667 */ + 0x16d9, /* VFMSUBADD132PSZ256mk */ + 0x16dc, /* VFMSUBADD132PSZ256rk */ +/* Table13669 */ + 0x1385, /* VFMADD132PSZ256mk */ + 0x1388, /* VFMADD132PSZ256rk */ +/* Table13671 */ + 0x15ad, /* VFMSUB132PSZ256mk */ + 0x15b0, /* VFMSUB132PSZ256rk */ +/* Table13673 */ + 0x17d5, /* VFNMADD132PSZ256mk */ + 0x17d8, /* VFNMADD132PSZ256rk */ +/* Table13675 */ + 0x1921, /* VFNMSUB132PSZ256mk */ + 0x1924, /* VFNMSUB132PSZ256rk */ +/* Table13677 */ + 0x2ff9, /* VPSCATTERDDZ256mr */ + 0x0, /* */ +/* Table13679 */ + 0x2fff, /* VPSCATTERQDZ256mr */ + 0x0, /* */ +/* Table13681 */ + 0x391d, /* VSCATTERDPSZ256mr */ + 0x0, /* */ +/* Table13683 */ + 0x392b, /* VSCATTERQPSZ256mr */ + 0x0, /* */ +/* Table13685 */ + 0x1515, /* VFMADDSUB213PSZ256mk */ + 0x1518, /* VFMADDSUB213PSZ256rk */ +/* Table13687 */ + 0x171d, /* VFMSUBADD213PSZ256mk */ + 0x1720, /* VFMSUBADD213PSZ256rk */ +/* Table13689 */ + 0x13e9, /* VFMADD213PSZ256mk */ + 0x13ec, /* VFMADD213PSZ256rk */ +/* Table13691 */ + 0x1611, /* VFMSUB213PSZ256mk */ + 0x1614, /* VFMSUB213PSZ256rk */ +/* Table13693 */ + 0x1839, /* VFNMADD213PSZ256mk */ + 0x183c, /* VFNMADD213PSZ256rk */ +/* Table13695 */ + 0x1985, /* VFNMSUB213PSZ256mk */ + 0x1988, /* VFNMSUB213PSZ256rk */ +/* Table13697 */ + 0x1559, /* VFMADDSUB231PSZ256mk */ + 0x155c, /* VFMADDSUB231PSZ256rk */ +/* Table13699 */ + 0x1761, /* VFMSUBADD231PSZ256mk */ + 0x1764, /* VFMSUBADD231PSZ256rk */ +/* Table13701 */ + 0x144d, /* VFMADD231PSZ256mk */ + 0x1450, /* VFMADD231PSZ256rk */ +/* Table13703 */ + 0x1675, /* VFMSUB231PSZ256mk */ + 0x1678, /* VFMSUB231PSZ256rk */ +/* Table13705 */ + 0x189d, /* VFNMADD231PSZ256mk */ + 0x18a0, /* VFNMADD231PSZ256rk */ +/* Table13707 */ + 0x19e9, /* VFNMSUB231PSZ256mk */ + 0x19ec, /* VFNMSUB231PSZ256rk */ +/* Table13709 */ + 0x2568, /* VPCONFLICTDZ256rmk */ + 0x256b, /* VPCONFLICTDZ256rrk */ +/* Table13711 */ + 0x1b73, /* VGF2P8MULBZ256rmk */ + 0x1b76, /* VGF2P8MULBZ256rrk */ +/* Table13713 */ + 0x35cc, /* VPTESTNMWZ256rmk */ + 0x35ce, /* VPTESTNMWZ256rrk */ +/* Table13715 */ + 0x35be, /* VPTESTNMQZ256rmk */ + 0x35c0, /* VPTESTNMQZ256rrk */ +/* Table13717 */ + 0x26ea, /* VPERMILPDZ256rmk */ + 0x26ed, /* VPERMILPDZ256rrk */ +/* Table13719 */ + 0x342e, /* VPSRLVWZ256rmk */ + 0x3431, /* VPSRLVWZ256rrk */ +/* Table13721 */ + 0x3346, /* VPSRAVWZ256rmk */ + 0x3349, /* VPSRAVWZ256rrk */ +/* Table13723 */ + 0x3270, /* VPSLLVWZ256rmk */ + 0x3273, /* VPSLLVWZ256rrk */ +/* Table13725 */ + 0x2fc8, /* VPRORVQZ256rmk */ + 0x2fcb, /* VPRORVQZ256rrk */ +/* Table13727 */ + 0x2f5c, /* VPROLVQZ256rmk */ + 0x2f5f, /* VPROLVQZ256rrk */ +/* Table13729 */ + 0x2752, /* VPERMPDZ256rmk */ + 0x2755, /* VPERMPDZ256rrk */ +/* Table13731 */ + 0xd2d, /* VBROADCASTSDZ256mk */ + 0xd30, /* VBROADCASTSDZ256rk */ +/* Table13733 */ + 0xcfd, /* VBROADCASTF64X2Z128rmk */ + 0x0, /* */ +/* Table13735 */ + 0x206f, /* VPABSQZ256rmk */ + 0x2072, /* VPABSQZ256rrk */ +/* Table13737 */ + 0x3590, /* VPTESTMWZ256rmk */ + 0x3592, /* VPTESTMWZ256rrk */ +/* Table13739 */ + 0x3582, /* VPTESTMQZ256rmk */ + 0x3584, /* VPTESTMQZ256rrk */ +/* Table13741 */ + 0x2d8a, /* VPMULDQZ256rmk */ + 0x2d8d, /* VPMULDQZ256rrk */ +/* Table13743 */ + 0x23dc, /* VPCMPEQQZ256rmk */ + 0x23de, /* VPCMPEQQZ256rrk */ +/* Table13745 */ + 0x38d8, /* VSCALEFPDZ256rmk */ + 0x38db, /* VSCALEFPDZ256rrk */ +/* Table13747 */ + 0x278c, /* VPERMQZ256rmk */ + 0x278f, /* VPERMQZ256rrk */ +/* Table13749 */ + 0x242c, /* VPCMPGTQZ256rmk */ + 0x242e, /* VPCMPGTQZ256rrk */ +/* Table13751 */ + 0x2ac1, /* VPMINSQZ256rmk */ + 0x2ac4, /* VPMINSQZ256rrk */ +/* Table13753 */ + 0x2b27, /* VPMINUQZ256rmk */ + 0x2b2a, /* VPMINUQZ256rrk */ +/* Table13755 */ + 0x29f5, /* VPMAXSQZ256rmk */ + 0x29f8, /* VPMAXSQZ256rrk */ +/* Table13757 */ + 0x2a5b, /* VPMAXUQZ256rmk */ + 0x2a5e, /* VPMAXUQZ256rrk */ +/* Table13759 */ + 0x2e08, /* VPMULLQZ256rmk */ + 0x2e0b, /* VPMULLQZ256rrk */ +/* Table13761 */ + 0x1a9d, /* VGETEXPPDZ256mk */ + 0x1aa0, /* VGETEXPPDZ256rk */ +/* Table13763 */ + 0x2923, /* VPLZCNTQZ256rmk */ + 0x2926, /* VPLZCNTQZ256rrk */ +/* Table13765 */ + 0x3417, /* VPSRLVQZ256rmk */ + 0x341a, /* VPSRLVQZ256rrk */ +/* Table13767 */ + 0x3331, /* VPSRAVQZ256rmk */ + 0x3334, /* VPSRAVQZ256rrk */ +/* Table13769 */ + 0x3259, /* VPSLLVQZ256rmk */ + 0x325c, /* VPSLLVQZ256rrk */ +/* Table13771 */ + 0x3740, /* VRCP14PDZ256mk */ + 0x3743, /* VRCP14PDZ256rk */ +/* Table13773 */ + 0x3864, /* VRSQRT14PDZ256mk */ + 0x3867, /* VRSQRT14PDZ256rk */ +/* Table13775 */ + 0x2eb5, /* VPOPCNTWZ256rmk */ + 0x2eb8, /* VPOPCNTWZ256rrk */ +/* Table13777 */ + 0x2ea0, /* VPOPCNTQZ256rmk */ + 0x2ea3, /* VPOPCNTQZ256rrk */ +/* Table13779 */ + 0x2328, /* VPBROADCASTQZ256mk */ + 0x232b, /* VPBROADCASTQZ256rk */ +/* Table13781 */ + 0xd22, /* VBROADCASTI64X2Z128rmk */ + 0x0, /* */ +/* Table13783 */ + 0x2882, /* VPEXPANDWZ256rmk */ + 0x2885, /* VPEXPANDWZ256rrk */ +/* Table13785 */ + 0x253a, /* VPCOMPRESSWZ256mrk */ + 0x253c, /* VPCOMPRESSWZ256rrk */ +/* Table13787 */ + 0x22b3, /* VPBLENDMQZ256rmk */ + 0x22b6, /* VPBLENDMQZ256rrk */ +/* Table13789 */ + 0xcad, /* VBLENDMPDZ256rmk */ + 0xcb0, /* VBLENDMPDZ256rrk */ +/* Table13791 */ + 0x22c8, /* VPBLENDMWZ256rmk */ + 0x22cb, /* VPBLENDMWZ256rrk */ +/* Table13793 */ + 0x308b, /* VPSHLDVWZ256mk */ + 0x308e, /* VPSHLDVWZ256rk */ +/* Table13795 */ + 0x3076, /* VPSHLDVQZ256mk */ + 0x3079, /* VPSHLDVQZ256rk */ +/* Table13797 */ + 0x3127, /* VPSHRDVWZ256mk */ + 0x312a, /* VPSHRDVWZ256rk */ +/* Table13799 */ + 0x3112, /* VPSHRDVQZ256mk */ + 0x3115, /* VPSHRDVQZ256rk */ +/* Table13801 */ + 0x26ac, /* VPERMI2W256rmk */ + 0x26af, /* VPERMI2W256rrk */ +/* Table13803 */ + 0x2697, /* VPERMI2Q256rmk */ + 0x269a, /* VPERMI2Q256rrk */ +/* Table13805 */ + 0x2661, /* VPERMI2PD256rmk */ + 0x2664, /* VPERMI2PD256rrk */ +/* Table13807 */ + 0x0, /* */ + 0x2337, /* VPBROADCASTQrZ256rk */ +/* Table13809 */ + 0x2828, /* VPERMT2W256rmk */ + 0x282b, /* VPERMT2W256rrk */ +/* Table13811 */ + 0x2813, /* VPERMT2Q256rmk */ + 0x2816, /* VPERMT2Q256rrk */ +/* Table13813 */ + 0x27dd, /* VPERMT2PD256rmk */ + 0x27e0, /* VPERMT2PD256rrk */ +/* Table13815 */ + 0x2e39, /* VPMULTISHIFTQBZ256rmk */ + 0x2e3c, /* VPMULTISHIFTQBZ256rrk */ +/* Table13817 */ + 0x12a5, /* VEXPANDPDZ256rmk */ + 0x12a8, /* VEXPANDPDZ256rrk */ +/* Table13819 */ + 0x2870, /* VPEXPANDQZ256rmk */ + 0x2873, /* VPEXPANDQZ256rrk */ +/* Table13821 */ + 0xdee, /* VCOMPRESSPDZ256mrk */ + 0xdf0, /* VCOMPRESSPDZ256rrk */ +/* Table13823 */ + 0x252b, /* VPCOMPRESSQZ256mrk */ + 0x252d, /* VPCOMPRESSQZ256rrk */ +/* Table13825 */ + 0x283a, /* VPERMWZ256rmk */ + 0x283d, /* VPERMWZ256rrk */ +/* Table13827 */ + 0x28a6, /* VPGATHERDQZ256rm */ + 0x0, /* */ +/* Table13829 */ + 0x28b0, /* VPGATHERQQZ256rm */ + 0x0, /* */ +/* Table13831 */ + 0x1a76, /* VGATHERDPDZ256rm */ + 0x0, /* */ +/* Table13833 */ + 0x1a88, /* VGATHERQPDZ256rm */ + 0x0, /* */ +/* Table13835 */ + 0x14af, /* VFMADDSUB132PDZ256mk */ + 0x14b2, /* VFMADDSUB132PDZ256rk */ +/* Table13837 */ + 0x16b7, /* VFMSUBADD132PDZ256mk */ + 0x16ba, /* VFMSUBADD132PDZ256rk */ +/* Table13839 */ + 0x1363, /* VFMADD132PDZ256mk */ + 0x1366, /* VFMADD132PDZ256rk */ +/* Table13841 */ + 0x158b, /* VFMSUB132PDZ256mk */ + 0x158e, /* VFMSUB132PDZ256rk */ +/* Table13843 */ + 0x17b3, /* VFNMADD132PDZ256mk */ + 0x17b6, /* VFNMADD132PDZ256rk */ +/* Table13845 */ + 0x18ff, /* VFNMSUB132PDZ256mk */ + 0x1902, /* VFNMSUB132PDZ256rk */ +/* Table13847 */ + 0x2ffc, /* VPSCATTERDQZ256mr */ + 0x0, /* */ +/* Table13849 */ + 0x3002, /* VPSCATTERQQZ256mr */ + 0x0, /* */ +/* Table13851 */ + 0x391a, /* VSCATTERDPDZ256mr */ + 0x0, /* */ +/* Table13853 */ + 0x3928, /* VSCATTERQPDZ256mr */ + 0x0, /* */ +/* Table13855 */ + 0x14f3, /* VFMADDSUB213PDZ256mk */ + 0x14f6, /* VFMADDSUB213PDZ256rk */ +/* Table13857 */ + 0x16fb, /* VFMSUBADD213PDZ256mk */ + 0x16fe, /* VFMSUBADD213PDZ256rk */ +/* Table13859 */ + 0x13c7, /* VFMADD213PDZ256mk */ + 0x13ca, /* VFMADD213PDZ256rk */ +/* Table13861 */ + 0x15ef, /* VFMSUB213PDZ256mk */ + 0x15f2, /* VFMSUB213PDZ256rk */ +/* Table13863 */ + 0x1817, /* VFNMADD213PDZ256mk */ + 0x181a, /* VFNMADD213PDZ256rk */ +/* Table13865 */ + 0x1963, /* VFNMSUB213PDZ256mk */ + 0x1966, /* VFNMSUB213PDZ256rk */ +/* Table13867 */ + 0x2971, /* VPMADD52LUQZ256mk */ + 0x2974, /* VPMADD52LUQZ256rk */ +/* Table13869 */ + 0x2956, /* VPMADD52HUQZ256mk */ + 0x2959, /* VPMADD52HUQZ256rk */ +/* Table13871 */ + 0x1537, /* VFMADDSUB231PDZ256mk */ + 0x153a, /* VFMADDSUB231PDZ256rk */ +/* Table13873 */ + 0x173f, /* VFMSUBADD231PDZ256mk */ + 0x1742, /* VFMSUBADD231PDZ256rk */ +/* Table13875 */ + 0x142b, /* VFMADD231PDZ256mk */ + 0x142e, /* VFMADD231PDZ256rk */ +/* Table13877 */ + 0x1653, /* VFMSUB231PDZ256mk */ + 0x1656, /* VFMSUB231PDZ256rk */ +/* Table13879 */ + 0x187b, /* VFNMADD231PDZ256mk */ + 0x187e, /* VFNMADD231PDZ256rk */ +/* Table13881 */ + 0x19c7, /* VFNMSUB231PDZ256mk */ + 0x19ca, /* VFNMSUB231PDZ256rk */ +/* Table13883 */ + 0x2583, /* VPCONFLICTQZ256rmk */ + 0x2586, /* VPCONFLICTQZ256rrk */ +/* Table13885 */ + 0x2ce1, /* VPMOVUSWBZmrk */ + 0x2ce3, /* VPMOVUSWBZrrk */ +/* Table13887 */ + 0x2c96, /* VPMOVUSDBZmrk */ + 0x2c98, /* VPMOVUSDBZrrk */ +/* Table13889 */ + 0x2cb4, /* VPMOVUSQBZmrk */ + 0x2cb6, /* VPMOVUSQBZrrk */ +/* Table13891 */ + 0x2ca5, /* VPMOVUSDWZmrk */ + 0x2ca7, /* VPMOVUSDWZrrk */ +/* Table13893 */ + 0x2cd2, /* VPMOVUSQWZmrk */ + 0x2cd4, /* VPMOVUSQWZrrk */ +/* Table13895 */ + 0x2cc3, /* VPMOVUSQDZmrk */ + 0x2cc5, /* VPMOVUSQDZrrk */ +/* Table13897 */ + 0x2c03, /* VPMOVSWBZmrk */ + 0x2c05, /* VPMOVSWBZrrk */ +/* Table13899 */ + 0x2bb8, /* VPMOVSDBZmrk */ + 0x2bba, /* VPMOVSDBZrrk */ +/* Table13901 */ + 0x2bd6, /* VPMOVSQBZmrk */ + 0x2bd8, /* VPMOVSQBZrrk */ +/* Table13903 */ + 0x2bc7, /* VPMOVSDWZmrk */ + 0x2bc9, /* VPMOVSDWZrrk */ +/* Table13905 */ + 0x2bf4, /* VPMOVSQWZmrk */ + 0x2bf6, /* VPMOVSQWZrrk */ +/* Table13907 */ + 0x2be5, /* VPMOVSQDZmrk */ + 0x2be7, /* VPMOVSQDZrrk */ +/* Table13909 */ + 0x35a0, /* VPTESTNMBZrmk */ + 0x35a2, /* VPTESTNMBZrrk */ +/* Table13911 */ + 0x35b2, /* VPTESTNMDZrmk */ + 0x35b4, /* VPTESTNMDZrrk */ +/* Table13913 */ + 0x2cf3, /* VPMOVWBZmrk */ + 0x2cf5, /* VPMOVWBZrrk */ +/* Table13915 */ + 0x2b5c, /* VPMOVDBZmrk */ + 0x2b5e, /* VPMOVDBZrrk */ +/* Table13917 */ + 0x2b8b, /* VPMOVQBZmrk */ + 0x2b8d, /* VPMOVQBZrrk */ +/* Table13919 */ + 0x2b6b, /* VPMOVDWZmrk */ + 0x2b6d, /* VPMOVDWZrrk */ +/* Table13921 */ + 0x2ba9, /* VPMOVQWZmrk */ + 0x2bab, /* VPMOVQWZrrk */ +/* Table13923 */ + 0x2b9a, /* VPMOVQDZmrk */ + 0x2b9c, /* VPMOVQDZrrk */ +/* Table13925 */ + 0x202b, /* VP4DPWSSDrmk */ + 0x0, /* */ +/* Table13927 */ + 0x2028, /* VP4DPWSSDSrmk */ + 0x0, /* */ +/* Table13929 */ + 0xb4d, /* V4FMADDPSrmk */ + 0x0, /* */ +/* Table13931 */ + 0xb53, /* V4FNMADDPSrmk */ + 0x0, /* */ +/* Table13933 */ + 0x315f, /* VPSHUFBZrmk */ + 0x3162, /* VPSHUFBZrrk */ +/* Table13935 */ + 0x298e, /* VPMADDUBSWZrmk */ + 0x2991, /* VPMADDUBSWZrrk */ +/* Table13937 */ + 0x2da9, /* VPMULHRSWZrmk */ + 0x2dac, /* VPMULHRSWZrrk */ +/* Table13939 */ + 0x273a, /* VPERMILPSZrmk */ + 0x273d, /* VPERMILPSZrrk */ +/* Table13941 */ + 0xef4, /* VCVTPH2PSZrmk */ + 0xefa, /* VCVTPH2PSZrrk */ +/* Table13943 */ + 0x2fb6, /* VPRORVDZrmk */ + 0x2fb9, /* VPRORVDZrrk */ +/* Table13945 */ + 0x2f4a, /* VPROLVDZrmk */ + 0x2f4d, /* VPROLVDZrrk */ +/* Table13947 */ + 0x2778, /* VPERMPSZrmk */ + 0x277b, /* VPERMPSZrrk */ +/* Table13949 */ + 0xd47, /* VBROADCASTSSZmk */ + 0xd4a, /* VBROADCASTSSZrk */ +/* Table13951 */ + 0xcee, /* VBROADCASTF32X2Zmk */ + 0xcf1, /* VBROADCASTF32X2Zrk */ +/* Table13953 */ + 0xcf7, /* VBROADCASTF32X4rmk */ + 0x0, /* */ +/* Table13955 */ + 0xcfa, /* VBROADCASTF32X8rmk */ + 0x0, /* */ +/* Table13957 */ + 0x203c, /* VPABSBZrmk */ + 0x203f, /* VPABSBZrrk */ +/* Table13959 */ + 0x208c, /* VPABSWZrmk */ + 0x208f, /* VPABSWZrrk */ +/* Table13961 */ + 0x205b, /* VPABSDZrmk */ + 0x205e, /* VPABSDZrrk */ +/* Table13963 */ + 0x2c42, /* VPMOVSXBWZrmk */ + 0x2c45, /* VPMOVSXBWZrrk */ +/* Table13965 */ + 0x2c16, /* VPMOVSXBDZrmk */ + 0x2c19, /* VPMOVSXBDZrrk */ +/* Table13967 */ + 0x2c2c, /* VPMOVSXBQZrmk */ + 0x2c2f, /* VPMOVSXBQZrrk */ +/* Table13969 */ + 0x2c6e, /* VPMOVSXWDZrmk */ + 0x2c71, /* VPMOVSXWDZrrk */ +/* Table13971 */ + 0x2c84, /* VPMOVSXWQZrmk */ + 0x2c87, /* VPMOVSXWQZrrk */ +/* Table13973 */ + 0x2c58, /* VPMOVSXDQZrmk */ + 0x2c5b, /* VPMOVSXDQZrrk */ +/* Table13975 */ + 0x3564, /* VPTESTMBZrmk */ + 0x3566, /* VPTESTMBZrrk */ +/* Table13977 */ + 0x3576, /* VPTESTMDZrmk */ + 0x3578, /* VPTESTMDZrrk */ +/* Table13979 */ + 0x20e0, /* VPACKUSDWZrmk */ + 0x20e3, /* VPACKUSDWZrrk */ +/* Table13981 */ + 0x38ff, /* VSCALEFPSZrmk */ + 0x3905, /* VSCALEFPSZrrk */ +/* Table13983 */ + 0x2d32, /* VPMOVZXBWZrmk */ + 0x2d35, /* VPMOVZXBWZrrk */ +/* Table13985 */ + 0x2d06, /* VPMOVZXBDZrmk */ + 0x2d09, /* VPMOVZXBDZrrk */ +/* Table13987 */ + 0x2d1c, /* VPMOVZXBQZrmk */ + 0x2d1f, /* VPMOVZXBQZrrk */ +/* Table13989 */ + 0x2d5e, /* VPMOVZXWDZrmk */ + 0x2d61, /* VPMOVZXWDZrrk */ +/* Table13991 */ + 0x2d74, /* VPMOVZXWQZrmk */ + 0x2d77, /* VPMOVZXWQZrrk */ +/* Table13993 */ + 0x2d48, /* VPMOVZXDQZrmk */ + 0x2d4b, /* VPMOVZXDQZrrk */ +/* Table13995 */ + 0x2622, /* VPERMDZrmk */ + 0x2625, /* VPERMDZrrk */ +/* Table13997 */ + 0x2a8e, /* VPMINSBZrmk */ + 0x2a91, /* VPMINSBZrrk */ +/* Table13999 */ + 0x2aad, /* VPMINSDZrmk */ + 0x2ab0, /* VPMINSDZrrk */ +/* Table14001 */ + 0x2b44, /* VPMINUWZrmk */ + 0x2b47, /* VPMINUWZrrk */ +/* Table14003 */ + 0x2b13, /* VPMINUDZrmk */ + 0x2b16, /* VPMINUDZrrk */ +/* Table14005 */ + 0x29c2, /* VPMAXSBZrmk */ + 0x29c5, /* VPMAXSBZrrk */ +/* Table14007 */ + 0x29e1, /* VPMAXSDZrmk */ + 0x29e4, /* VPMAXSDZrrk */ +/* Table14009 */ + 0x2a78, /* VPMAXUWZrmk */ + 0x2a7b, /* VPMAXUWZrrk */ +/* Table14011 */ + 0x2a47, /* VPMAXUDZrmk */ + 0x2a4a, /* VPMAXUDZrrk */ +/* Table14013 */ + 0x2df4, /* VPMULLDZrmk */ + 0x2df7, /* VPMULLDZrrk */ +/* Table14015 */ + 0x1ac4, /* VGETEXPPSZmk */ + 0x1aca, /* VGETEXPPSZrk */ +/* Table14017 */ + 0x2911, /* VPLZCNTDZrmk */ + 0x2914, /* VPLZCNTDZrrk */ +/* Table14019 */ + 0x3401, /* VPSRLVDZrmk */ + 0x3404, /* VPSRLVDZrrk */ +/* Table14021 */ + 0x331d, /* VPSRAVDZrmk */ + 0x3320, /* VPSRAVDZrrk */ +/* Table14023 */ + 0x3243, /* VPSLLVDZrmk */ + 0x3246, /* VPSLLVDZrrk */ +/* Table14025 */ + 0x3764, /* VRCP14PSZmk */ + 0x3767, /* VRCP14PSZrk */ +/* Table14027 */ + 0x3888, /* VRSQRT14PSZmk */ + 0x388b, /* VRSQRT14PSZrk */ +/* Table14029 */ + 0x25c2, /* VPDPBUSDZmk */ + 0x25c5, /* VPDPBUSDZrk */ +/* Table14031 */ + 0x25a7, /* VPDPBUSDSZmk */ + 0x25aa, /* VPDPBUSDSZrk */ +/* Table14033 */ + 0x25f8, /* VPDPWSSDZmk */ + 0x25fb, /* VPDPWSSDZrk */ +/* Table14035 */ + 0x25dd, /* VPDPWSSDSZmk */ + 0x25e0, /* VPDPWSSDSZrk */ +/* Table14037 */ + 0x2e73, /* VPOPCNTBZrmk */ + 0x2e76, /* VPOPCNTBZrrk */ +/* Table14039 */ + 0x2e8e, /* VPOPCNTDZrmk */ + 0x2e91, /* VPOPCNTDZrrk */ +/* Table14041 */ + 0x2309, /* VPBROADCASTDZmk */ + 0x230c, /* VPBROADCASTDZrk */ +/* Table14043 */ + 0xd13, /* VBROADCASTI32X2Zmk */ + 0xd16, /* VBROADCASTI32X2Zrk */ +/* Table14045 */ + 0xd1c, /* VBROADCASTI32X4rmk */ + 0x0, /* */ +/* Table14047 */ + 0xd1f, /* VBROADCASTI32X8rmk */ + 0x0, /* */ +/* Table14049 */ + 0x2852, /* VPEXPANDBZrmk */ + 0x2855, /* VPEXPANDBZrrk */ +/* Table14051 */ + 0x2512, /* VPCOMPRESSBZmrk */ + 0x2514, /* VPCOMPRESSBZrrk */ +/* Table14053 */ + 0x22a1, /* VPBLENDMDZrmk */ + 0x22a4, /* VPBLENDMDZrrk */ +/* Table14055 */ + 0xcd1, /* VBLENDMPSZrmk */ + 0xcd4, /* VBLENDMPSZrrk */ +/* Table14057 */ + 0x2286, /* VPBLENDMBZrmk */ + 0x2289, /* VPBLENDMBZrrk */ +/* Table14059 */ + 0x3064, /* VPSHLDVDZmk */ + 0x3067, /* VPSHLDVDZrk */ +/* Table14061 */ + 0x3100, /* VPSHRDVDZmk */ + 0x3103, /* VPSHRDVDZrk */ +/* Table14063 */ + 0x2634, /* VPERMI2Brmk */ + 0x2637, /* VPERMI2Brrk */ +/* Table14065 */ + 0x264f, /* VPERMI2Drmk */ + 0x2652, /* VPERMI2Drrk */ +/* Table14067 */ + 0x2685, /* VPERMI2PSrmk */ + 0x2688, /* VPERMI2PSrrk */ +/* Table14069 */ + 0x22ea, /* VPBROADCASTBZmk */ + 0x22ed, /* VPBROADCASTBZrk */ +/* Table14071 */ + 0x234d, /* VPBROADCASTWZmk */ + 0x2350, /* VPBROADCASTWZrk */ +/* Table14073 */ + 0x0, /* */ + 0x22f6, /* VPBROADCASTBrZrk */ +/* Table14075 */ + 0x0, /* */ + 0x2359, /* VPBROADCASTWrZrk */ +/* Table14077 */ + 0x0, /* */ + 0x2315, /* VPBROADCASTDrZrk */ +/* Table14079 */ + 0x27b0, /* VPERMT2Brmk */ + 0x27b3, /* VPERMT2Brrk */ +/* Table14081 */ + 0x27cb, /* VPERMT2Drmk */ + 0x27ce, /* VPERMT2Drrk */ +/* Table14083 */ + 0x2801, /* VPERMT2PSrmk */ + 0x2804, /* VPERMT2PSrrk */ +/* Table14085 */ + 0x12bd, /* VEXPANDPSZrmk */ + 0x12c0, /* VEXPANDPSZrrk */ +/* Table14087 */ + 0x2864, /* VPEXPANDDZrmk */ + 0x2867, /* VPEXPANDDZrrk */ +/* Table14089 */ + 0xe02, /* VCOMPRESSPSZmrk */ + 0xe04, /* VCOMPRESSPSZrrk */ +/* Table14091 */ + 0x2521, /* VPCOMPRESSDZmrk */ + 0x2523, /* VPCOMPRESSDZrrk */ +/* Table14093 */ + 0x260e, /* VPERMBZrmk */ + 0x2611, /* VPERMBZrrk */ +/* Table14095 */ + 0x314d, /* VPSHUFBITQMBZrmk */ + 0x314f, /* VPSHUFBITQMBZrrk */ +/* Table14097 */ + 0x28a2, /* VPGATHERDDZrm */ + 0x0, /* */ +/* Table14099 */ + 0x28ac, /* VPGATHERQDZrm */ + 0x0, /* */ +/* Table14101 */ + 0x1a7c, /* VGATHERDPSZrm */ + 0x0, /* */ +/* Table14103 */ + 0x1a8e, /* VGATHERQPSZrm */ + 0x0, /* */ +/* Table14105 */ + 0x14da, /* VFMADDSUB132PSZmk */ + 0x14e0, /* VFMADDSUB132PSZrk */ +/* Table14107 */ + 0x16e2, /* VFMSUBADD132PSZmk */ + 0x16e8, /* VFMSUBADD132PSZrk */ +/* Table14109 */ + 0x138e, /* VFMADD132PSZmk */ + 0x1394, /* VFMADD132PSZrk */ +/* Table14111 */ + 0x15b6, /* VFMSUB132PSZmk */ + 0x15bc, /* VFMSUB132PSZrk */ +/* Table14113 */ + 0x17de, /* VFNMADD132PSZmk */ + 0x17e4, /* VFNMADD132PSZrk */ +/* Table14115 */ + 0x192a, /* VFNMSUB132PSZmk */ + 0x1930, /* VFNMSUB132PSZrk */ +/* Table14117 */ + 0x2ffa, /* VPSCATTERDDZmr */ + 0x0, /* */ +/* Table14119 */ + 0x3000, /* VPSCATTERQDZmr */ + 0x0, /* */ +/* Table14121 */ + 0x391e, /* VSCATTERDPSZmr */ + 0x0, /* */ +/* Table14123 */ + 0x392c, /* VSCATTERQPSZmr */ + 0x0, /* */ +/* Table14125 */ + 0x151e, /* VFMADDSUB213PSZmk */ + 0x1524, /* VFMADDSUB213PSZrk */ +/* Table14127 */ + 0x1726, /* VFMSUBADD213PSZmk */ + 0x172c, /* VFMSUBADD213PSZrk */ +/* Table14129 */ + 0x13f2, /* VFMADD213PSZmk */ + 0x13f8, /* VFMADD213PSZrk */ +/* Table14131 */ + 0x161a, /* VFMSUB213PSZmk */ + 0x1620, /* VFMSUB213PSZrk */ +/* Table14133 */ + 0x1842, /* VFNMADD213PSZmk */ + 0x1848, /* VFNMADD213PSZrk */ +/* Table14135 */ + 0x198e, /* VFNMSUB213PSZmk */ + 0x1994, /* VFNMSUB213PSZrk */ +/* Table14137 */ + 0x1562, /* VFMADDSUB231PSZmk */ + 0x1568, /* VFMADDSUB231PSZrk */ +/* Table14139 */ + 0x176a, /* VFMSUBADD231PSZmk */ + 0x1770, /* VFMSUBADD231PSZrk */ +/* Table14141 */ + 0x1456, /* VFMADD231PSZmk */ + 0x145c, /* VFMADD231PSZrk */ +/* Table14143 */ + 0x167e, /* VFMSUB231PSZmk */ + 0x1684, /* VFMSUB231PSZrk */ +/* Table14145 */ + 0x18a6, /* VFNMADD231PSZmk */ + 0x18ac, /* VFNMADD231PSZrk */ +/* Table14147 */ + 0x19f2, /* VFNMSUB231PSZmk */ + 0x19f8, /* VFNMSUB231PSZrk */ +/* Table14149 */ + 0x2571, /* VPCONFLICTDZrmk */ + 0x2574, /* VPCONFLICTDZrrk */ +/* Table14151 */ + 0x0, /* */ + 0x1a7f, /* VGATHERPF0DPSm */ + 0x1a83, /* VGATHERPF1DPSm */ + 0x0, /* */ + 0x0, /* */ + 0x3920, /* VSCATTERPF0DPSm */ + 0x3924, /* VSCATTERPF1DPSm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table14167 */ + 0x0, /* */ + 0x1a81, /* VGATHERPF0QPSm */ + 0x1a85, /* VGATHERPF1QPSm */ + 0x0, /* */ + 0x0, /* */ + 0x3922, /* VSCATTERPF0QPSm */ + 0x3926, /* VSCATTERPF1QPSm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table14183 */ + 0x1296, /* VEXP2PSZmk */ + 0x129c, /* VEXP2PSZrk */ +/* Table14185 */ + 0x3785, /* VRCP28PSZmk */ + 0x378b, /* VRCP28PSZrk */ +/* Table14187 */ + 0x38a9, /* VRSQRT28PSZmk */ + 0x38af, /* VRSQRT28PSZrk */ +/* Table14189 */ + 0x1b79, /* VGF2P8MULBZrmk */ + 0x1b7c, /* VGF2P8MULBZrrk */ +/* Table14191 */ + 0x35d0, /* VPTESTNMWZrmk */ + 0x35d2, /* VPTESTNMWZrrk */ +/* Table14193 */ + 0x35c4, /* VPTESTNMQZrmk */ + 0x35c6, /* VPTESTNMQZrrk */ +/* Table14195 */ + 0x26fc, /* VPERMILPDZrmk */ + 0x26ff, /* VPERMILPDZrrk */ +/* Table14197 */ + 0x3434, /* VPSRLVWZrmk */ + 0x3437, /* VPSRLVWZrrk */ +/* Table14199 */ + 0x334c, /* VPSRAVWZrmk */ + 0x334f, /* VPSRAVWZrrk */ +/* Table14201 */ + 0x3276, /* VPSLLVWZrmk */ + 0x3279, /* VPSLLVWZrrk */ +/* Table14203 */ + 0x2fd1, /* VPRORVQZrmk */ + 0x2fd4, /* VPRORVQZrrk */ +/* Table14205 */ + 0x2f65, /* VPROLVQZrmk */ + 0x2f68, /* VPROLVQZrrk */ +/* Table14207 */ + 0x2764, /* VPERMPDZrmk */ + 0x2767, /* VPERMPDZrrk */ +/* Table14209 */ + 0xd33, /* VBROADCASTSDZmk */ + 0xd36, /* VBROADCASTSDZrk */ +/* Table14211 */ + 0xd00, /* VBROADCASTF64X2rmk */ + 0x0, /* */ +/* Table14213 */ + 0xd03, /* VBROADCASTF64X4rmk */ + 0x0, /* */ +/* Table14215 */ + 0x2078, /* VPABSQZrmk */ + 0x207b, /* VPABSQZrrk */ +/* Table14217 */ + 0x3594, /* VPTESTMWZrmk */ + 0x3596, /* VPTESTMWZrrk */ +/* Table14219 */ + 0x3588, /* VPTESTMQZrmk */ + 0x358a, /* VPTESTMQZrrk */ +/* Table14221 */ + 0x2d93, /* VPMULDQZrmk */ + 0x2d96, /* VPMULDQZrrk */ +/* Table14223 */ + 0x23e2, /* VPCMPEQQZrmk */ + 0x23e4, /* VPCMPEQQZrrk */ +/* Table14225 */ + 0x38e1, /* VSCALEFPDZrmk */ + 0x38e7, /* VSCALEFPDZrrk */ +/* Table14227 */ + 0x279e, /* VPERMQZrmk */ + 0x27a1, /* VPERMQZrrk */ +/* Table14229 */ + 0x2432, /* VPCMPGTQZrmk */ + 0x2434, /* VPCMPGTQZrrk */ +/* Table14231 */ + 0x2aca, /* VPMINSQZrmk */ + 0x2acd, /* VPMINSQZrrk */ +/* Table14233 */ + 0x2b30, /* VPMINUQZrmk */ + 0x2b33, /* VPMINUQZrrk */ +/* Table14235 */ + 0x29fe, /* VPMAXSQZrmk */ + 0x2a01, /* VPMAXSQZrrk */ +/* Table14237 */ + 0x2a64, /* VPMAXUQZrmk */ + 0x2a67, /* VPMAXUQZrrk */ +/* Table14239 */ + 0x2e11, /* VPMULLQZrmk */ + 0x2e14, /* VPMULLQZrrk */ +/* Table14241 */ + 0x1aa6, /* VGETEXPPDZmk */ + 0x1aac, /* VGETEXPPDZrk */ +/* Table14243 */ + 0x292c, /* VPLZCNTQZrmk */ + 0x292f, /* VPLZCNTQZrrk */ +/* Table14245 */ + 0x3420, /* VPSRLVQZrmk */ + 0x3423, /* VPSRLVQZrrk */ +/* Table14247 */ + 0x333a, /* VPSRAVQZrmk */ + 0x333d, /* VPSRAVQZrrk */ +/* Table14249 */ + 0x3262, /* VPSLLVQZrmk */ + 0x3265, /* VPSLLVQZrrk */ +/* Table14251 */ + 0x3749, /* VRCP14PDZmk */ + 0x374c, /* VRCP14PDZrk */ +/* Table14253 */ + 0x386d, /* VRSQRT14PDZmk */ + 0x3870, /* VRSQRT14PDZrk */ +/* Table14255 */ + 0x2ebb, /* VPOPCNTWZrmk */ + 0x2ebe, /* VPOPCNTWZrrk */ +/* Table14257 */ + 0x2ea9, /* VPOPCNTQZrmk */ + 0x2eac, /* VPOPCNTQZrrk */ +/* Table14259 */ + 0x232e, /* VPBROADCASTQZmk */ + 0x2331, /* VPBROADCASTQZrk */ +/* Table14261 */ + 0xd25, /* VBROADCASTI64X2rmk */ + 0x0, /* */ +/* Table14263 */ + 0xd28, /* VBROADCASTI64X4rmk */ + 0x0, /* */ +/* Table14265 */ + 0x2888, /* VPEXPANDWZrmk */ + 0x288b, /* VPEXPANDWZrrk */ +/* Table14267 */ + 0x253f, /* VPCOMPRESSWZmrk */ + 0x2541, /* VPCOMPRESSWZrrk */ +/* Table14269 */ + 0x22bc, /* VPBLENDMQZrmk */ + 0x22bf, /* VPBLENDMQZrrk */ +/* Table14271 */ + 0xcb6, /* VBLENDMPDZrmk */ + 0xcb9, /* VBLENDMPDZrrk */ +/* Table14273 */ + 0x22ce, /* VPBLENDMWZrmk */ + 0x22d1, /* VPBLENDMWZrrk */ +/* Table14275 */ + 0x3091, /* VPSHLDVWZmk */ + 0x3094, /* VPSHLDVWZrk */ +/* Table14277 */ + 0x307f, /* VPSHLDVQZmk */ + 0x3082, /* VPSHLDVQZrk */ +/* Table14279 */ + 0x312d, /* VPSHRDVWZmk */ + 0x3130, /* VPSHRDVWZrk */ +/* Table14281 */ + 0x311b, /* VPSHRDVQZmk */ + 0x311e, /* VPSHRDVQZrk */ +/* Table14283 */ + 0x26b2, /* VPERMI2Wrmk */ + 0x26b5, /* VPERMI2Wrrk */ +/* Table14285 */ + 0x26a0, /* VPERMI2Qrmk */ + 0x26a3, /* VPERMI2Qrrk */ +/* Table14287 */ + 0x266a, /* VPERMI2PDrmk */ + 0x266d, /* VPERMI2PDrrk */ +/* Table14289 */ + 0x0, /* */ + 0x233a, /* VPBROADCASTQrZrk */ +/* Table14291 */ + 0x282e, /* VPERMT2Wrmk */ + 0x2831, /* VPERMT2Wrrk */ +/* Table14293 */ + 0x281c, /* VPERMT2Qrmk */ + 0x281f, /* VPERMT2Qrrk */ +/* Table14295 */ + 0x27e6, /* VPERMT2PDrmk */ + 0x27e9, /* VPERMT2PDrrk */ +/* Table14297 */ + 0x2e42, /* VPMULTISHIFTQBZrmk */ + 0x2e45, /* VPMULTISHIFTQBZrrk */ +/* Table14299 */ + 0x12ab, /* VEXPANDPDZrmk */ + 0x12ae, /* VEXPANDPDZrrk */ +/* Table14301 */ + 0x2876, /* VPEXPANDQZrmk */ + 0x2879, /* VPEXPANDQZrrk */ +/* Table14303 */ + 0xdf3, /* VCOMPRESSPDZmrk */ + 0xdf5, /* VCOMPRESSPDZrrk */ +/* Table14305 */ + 0x2530, /* VPCOMPRESSQZmrk */ + 0x2532, /* VPCOMPRESSQZrrk */ +/* Table14307 */ + 0x2840, /* VPERMWZrmk */ + 0x2843, /* VPERMWZrrk */ +/* Table14309 */ + 0x28a7, /* VPGATHERDQZrm */ + 0x0, /* */ +/* Table14311 */ + 0x28b1, /* VPGATHERQQZrm */ + 0x0, /* */ +/* Table14313 */ + 0x1a77, /* VGATHERDPDZrm */ + 0x0, /* */ +/* Table14315 */ + 0x1a89, /* VGATHERQPDZrm */ + 0x0, /* */ +/* Table14317 */ + 0x14b8, /* VFMADDSUB132PDZmk */ + 0x14be, /* VFMADDSUB132PDZrk */ +/* Table14319 */ + 0x16c0, /* VFMSUBADD132PDZmk */ + 0x16c6, /* VFMSUBADD132PDZrk */ +/* Table14321 */ + 0x136c, /* VFMADD132PDZmk */ + 0x1372, /* VFMADD132PDZrk */ +/* Table14323 */ + 0x1594, /* VFMSUB132PDZmk */ + 0x159a, /* VFMSUB132PDZrk */ +/* Table14325 */ + 0x17bc, /* VFNMADD132PDZmk */ + 0x17c2, /* VFNMADD132PDZrk */ +/* Table14327 */ + 0x1908, /* VFNMSUB132PDZmk */ + 0x190e, /* VFNMSUB132PDZrk */ +/* Table14329 */ + 0x2ffd, /* VPSCATTERDQZmr */ + 0x0, /* */ +/* Table14331 */ + 0x3003, /* VPSCATTERQQZmr */ + 0x0, /* */ +/* Table14333 */ + 0x391b, /* VSCATTERDPDZmr */ + 0x0, /* */ +/* Table14335 */ + 0x3929, /* VSCATTERQPDZmr */ + 0x0, /* */ +/* Table14337 */ + 0x14fc, /* VFMADDSUB213PDZmk */ + 0x1502, /* VFMADDSUB213PDZrk */ +/* Table14339 */ + 0x1704, /* VFMSUBADD213PDZmk */ + 0x170a, /* VFMSUBADD213PDZrk */ +/* Table14341 */ + 0x13d0, /* VFMADD213PDZmk */ + 0x13d6, /* VFMADD213PDZrk */ +/* Table14343 */ + 0x15f8, /* VFMSUB213PDZmk */ + 0x15fe, /* VFMSUB213PDZrk */ +/* Table14345 */ + 0x1820, /* VFNMADD213PDZmk */ + 0x1826, /* VFNMADD213PDZrk */ +/* Table14347 */ + 0x196c, /* VFNMSUB213PDZmk */ + 0x1972, /* VFNMSUB213PDZrk */ +/* Table14349 */ + 0x297a, /* VPMADD52LUQZmk */ + 0x297d, /* VPMADD52LUQZrk */ +/* Table14351 */ + 0x295f, /* VPMADD52HUQZmk */ + 0x2962, /* VPMADD52HUQZrk */ +/* Table14353 */ + 0x1540, /* VFMADDSUB231PDZmk */ + 0x1546, /* VFMADDSUB231PDZrk */ +/* Table14355 */ + 0x1748, /* VFMSUBADD231PDZmk */ + 0x174e, /* VFMSUBADD231PDZrk */ +/* Table14357 */ + 0x1434, /* VFMADD231PDZmk */ + 0x143a, /* VFMADD231PDZrk */ +/* Table14359 */ + 0x165c, /* VFMSUB231PDZmk */ + 0x1662, /* VFMSUB231PDZrk */ +/* Table14361 */ + 0x1884, /* VFNMADD231PDZmk */ + 0x188a, /* VFNMADD231PDZrk */ +/* Table14363 */ + 0x19d0, /* VFNMSUB231PDZmk */ + 0x19d6, /* VFNMSUB231PDZrk */ +/* Table14365 */ + 0x258c, /* VPCONFLICTQZrmk */ + 0x258f, /* VPCONFLICTQZrrk */ +/* Table14367 */ + 0x0, /* */ + 0x1a7e, /* VGATHERPF0DPDm */ + 0x1a82, /* VGATHERPF1DPDm */ + 0x0, /* */ + 0x0, /* */ + 0x391f, /* VSCATTERPF0DPDm */ + 0x3923, /* VSCATTERPF1DPDm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table14383 */ + 0x0, /* */ + 0x1a80, /* VGATHERPF0QPDm */ + 0x1a84, /* VGATHERPF1QPDm */ + 0x0, /* */ + 0x0, /* */ + 0x3921, /* VSCATTERPF0QPDm */ + 0x3925, /* VSCATTERPF1QPDm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table14399 */ + 0x128a, /* VEXP2PDZmk */ + 0x1290, /* VEXP2PDZrk */ +/* Table14401 */ + 0x3779, /* VRCP28PDZmk */ + 0x377f, /* VRCP28PDZrk */ +/* Table14403 */ + 0x389d, /* VRSQRT28PDZmk */ + 0x38a3, /* VRSQRT28PDZrk */ +/* Table14405 */ + 0x35a4, /* VPTESTNMDZ128rmb */ + 0x0, /* */ +/* Table14407 */ + 0x2713, /* VPERMILPSZ128rmb */ + 0x0, /* */ +/* Table14409 */ + 0x0, /* */ + 0xef7, /* VCVTPH2PSZrrb */ +/* Table14411 */ + 0x2fa1, /* VPRORVDZ128rmb */ + 0x0, /* */ +/* Table14413 */ + 0x2f35, /* VPROLVDZ128rmb */ + 0x0, /* */ +/* Table14415 */ + 0x2046, /* VPABSDZ128rmb */ + 0x0, /* */ +/* Table14417 */ + 0x3568, /* VPTESTMDZ128rmb */ + 0x0, /* */ +/* Table14419 */ + 0x20cb, /* VPACKUSDWZ128rmb */ + 0x0, /* */ +/* Table14421 */ + 0x38ea, /* VSCALEFPSZ128rmb */ + 0x3902, /* VSCALEFPSZrrb */ +/* Table14423 */ + 0x0, /* */ + 0x3914, /* VSCALEFSSZrrb_Int */ +/* Table14425 */ + 0x2a98, /* VPMINSDZ128rmb */ + 0x0, /* */ +/* Table14427 */ + 0x2afe, /* VPMINUDZ128rmb */ + 0x0, /* */ +/* Table14429 */ + 0x29cc, /* VPMAXSDZ128rmb */ + 0x0, /* */ +/* Table14431 */ + 0x2a32, /* VPMAXUDZ128rmb */ + 0x0, /* */ +/* Table14433 */ + 0x2ddf, /* VPMULLDZ128rmb */ + 0x0, /* */ +/* Table14435 */ + 0x1aaf, /* VGETEXPPSZ128mb */ + 0x1ac7, /* VGETEXPPSZrb */ +/* Table14437 */ + 0x0, /* */ + 0x1ad9, /* VGETEXPSSZrb */ +/* Table14439 */ + 0x28fc, /* VPLZCNTDZ128rmb */ + 0x0, /* */ +/* Table14441 */ + 0x33ec, /* VPSRLVDZ128rmb */ + 0x0, /* */ +/* Table14443 */ + 0x3308, /* VPSRAVDZ128rmb */ + 0x0, /* */ +/* Table14445 */ + 0x322e, /* VPSLLVDZ128rmb */ + 0x0, /* */ +/* Table14447 */ + 0x374f, /* VRCP14PSZ128mb */ + 0x0, /* */ +/* Table14449 */ + 0x3873, /* VRSQRT14PSZ128mb */ + 0x0, /* */ +/* Table14451 */ + 0x25ad, /* VPDPBUSDZ128mb */ + 0x0, /* */ +/* Table14453 */ + 0x2592, /* VPDPBUSDSZ128mb */ + 0x0, /* */ +/* Table14455 */ + 0x25e3, /* VPDPWSSDZ128mb */ + 0x0, /* */ +/* Table14457 */ + 0x25c8, /* VPDPWSSDSZ128mb */ + 0x0, /* */ +/* Table14459 */ + 0x2e79, /* VPOPCNTDZ128rmb */ + 0x0, /* */ +/* Table14461 */ + 0x228c, /* VPBLENDMDZ128rmb */ + 0x0, /* */ +/* Table14463 */ + 0xcbc, /* VBLENDMPSZ128rmb */ + 0x0, /* */ +/* Table14465 */ + 0x304f, /* VPSHLDVDZ128mb */ + 0x0, /* */ +/* Table14467 */ + 0x30eb, /* VPSHRDVDZ128mb */ + 0x0, /* */ +/* Table14469 */ + 0x263a, /* VPERMI2D128rmb */ + 0x0, /* */ +/* Table14471 */ + 0x2670, /* VPERMI2PS128rmb */ + 0x0, /* */ +/* Table14473 */ + 0x27b6, /* VPERMT2D128rmb */ + 0x0, /* */ +/* Table14475 */ + 0x27ec, /* VPERMT2PS128rmb */ + 0x0, /* */ +/* Table14477 */ + 0x14c5, /* VFMADDSUB132PSZ128mb */ + 0x14dd, /* VFMADDSUB132PSZrb */ +/* Table14479 */ + 0x16cd, /* VFMSUBADD132PSZ128mb */ + 0x16e5, /* VFMSUBADD132PSZrb */ +/* Table14481 */ + 0x1379, /* VFMADD132PSZ128mb */ + 0x1391, /* VFMADD132PSZrb */ +/* Table14483 */ + 0x0, /* */ + 0x13b1, /* VFMADD132SSZrb_Int */ +/* Table14485 */ + 0x15a1, /* VFMSUB132PSZ128mb */ + 0x15b9, /* VFMSUB132PSZrb */ +/* Table14487 */ + 0x0, /* */ + 0x15d9, /* VFMSUB132SSZrb_Int */ +/* Table14489 */ + 0x17c9, /* VFNMADD132PSZ128mb */ + 0x17e1, /* VFNMADD132PSZrb */ +/* Table14491 */ + 0x0, /* */ + 0x1801, /* VFNMADD132SSZrb_Int */ +/* Table14493 */ + 0x1915, /* VFNMSUB132PSZ128mb */ + 0x192d, /* VFNMSUB132PSZrb */ +/* Table14495 */ + 0x0, /* */ + 0x194d, /* VFNMSUB132SSZrb_Int */ +/* Table14497 */ + 0x1509, /* VFMADDSUB213PSZ128mb */ + 0x1521, /* VFMADDSUB213PSZrb */ +/* Table14499 */ + 0x1711, /* VFMSUBADD213PSZ128mb */ + 0x1729, /* VFMSUBADD213PSZrb */ +/* Table14501 */ + 0x13dd, /* VFMADD213PSZ128mb */ + 0x13f5, /* VFMADD213PSZrb */ +/* Table14503 */ + 0x0, /* */ + 0x1415, /* VFMADD213SSZrb_Int */ +/* Table14505 */ + 0x1605, /* VFMSUB213PSZ128mb */ + 0x161d, /* VFMSUB213PSZrb */ +/* Table14507 */ + 0x0, /* */ + 0x163d, /* VFMSUB213SSZrb_Int */ +/* Table14509 */ + 0x182d, /* VFNMADD213PSZ128mb */ + 0x1845, /* VFNMADD213PSZrb */ +/* Table14511 */ + 0x0, /* */ + 0x1865, /* VFNMADD213SSZrb_Int */ +/* Table14513 */ + 0x1979, /* VFNMSUB213PSZ128mb */ + 0x1991, /* VFNMSUB213PSZrb */ +/* Table14515 */ + 0x0, /* */ + 0x19b1, /* VFNMSUB213SSZrb_Int */ +/* Table14517 */ + 0x154d, /* VFMADDSUB231PSZ128mb */ + 0x1565, /* VFMADDSUB231PSZrb */ +/* Table14519 */ + 0x1755, /* VFMSUBADD231PSZ128mb */ + 0x176d, /* VFMSUBADD231PSZrb */ +/* Table14521 */ + 0x1441, /* VFMADD231PSZ128mb */ + 0x1459, /* VFMADD231PSZrb */ +/* Table14523 */ + 0x0, /* */ + 0x1479, /* VFMADD231SSZrb_Int */ +/* Table14525 */ + 0x1669, /* VFMSUB231PSZ128mb */ + 0x1681, /* VFMSUB231PSZrb */ +/* Table14527 */ + 0x0, /* */ + 0x16a1, /* VFMSUB231SSZrb_Int */ +/* Table14529 */ + 0x1891, /* VFNMADD231PSZ128mb */ + 0x18a9, /* VFNMADD231PSZrb */ +/* Table14531 */ + 0x0, /* */ + 0x18c9, /* VFNMADD231SSZrb_Int */ +/* Table14533 */ + 0x19dd, /* VFNMSUB231PSZ128mb */ + 0x19f5, /* VFNMSUB231PSZrb */ +/* Table14535 */ + 0x0, /* */ + 0x1a15, /* VFNMSUB231SSZrb_Int */ +/* Table14537 */ + 0x255c, /* VPCONFLICTDZ128rmb */ + 0x0, /* */ +/* Table14539 */ + 0x0, /* */ + 0x1299, /* VEXP2PSZrb */ +/* Table14541 */ + 0x0, /* */ + 0x3788, /* VRCP28PSZrb */ +/* Table14543 */ + 0x0, /* */ + 0x379a, /* VRCP28SSZrb */ +/* Table14545 */ + 0x0, /* */ + 0x38ac, /* VRSQRT28PSZrb */ +/* Table14547 */ + 0x0, /* */ + 0x38be, /* VRSQRT28SSZrb */ +/* Table14549 */ + 0x35b6, /* VPTESTNMQZ128rmb */ + 0x0, /* */ +/* Table14551 */ + 0x26d5, /* VPERMILPDZ128rmb */ + 0x0, /* */ +/* Table14553 */ + 0x2fbc, /* VPRORVQZ128rmb */ + 0x0, /* */ +/* Table14555 */ + 0x2f50, /* VPROLVQZ128rmb */ + 0x0, /* */ +/* Table14557 */ + 0x2063, /* VPABSQZ128rmb */ + 0x0, /* */ +/* Table14559 */ + 0x357a, /* VPTESTMQZ128rmb */ + 0x0, /* */ +/* Table14561 */ + 0x2d7e, /* VPMULDQZ128rmb */ + 0x0, /* */ +/* Table14563 */ + 0x23d4, /* VPCMPEQQZ128rmb */ + 0x0, /* */ +/* Table14565 */ + 0x38cc, /* VSCALEFPDZ128rmb */ + 0x38e4, /* VSCALEFPDZrrb */ +/* Table14567 */ + 0x0, /* */ + 0x390b, /* VSCALEFSDZrrb_Int */ +/* Table14569 */ + 0x2424, /* VPCMPGTQZ128rmb */ + 0x0, /* */ +/* Table14571 */ + 0x2ab5, /* VPMINSQZ128rmb */ + 0x0, /* */ +/* Table14573 */ + 0x2b1b, /* VPMINUQZ128rmb */ + 0x0, /* */ +/* Table14575 */ + 0x29e9, /* VPMAXSQZ128rmb */ + 0x0, /* */ +/* Table14577 */ + 0x2a4f, /* VPMAXUQZ128rmb */ + 0x0, /* */ +/* Table14579 */ + 0x2dfc, /* VPMULLQZ128rmb */ + 0x0, /* */ +/* Table14581 */ + 0x1a91, /* VGETEXPPDZ128mb */ + 0x1aa9, /* VGETEXPPDZrb */ +/* Table14583 */ + 0x0, /* */ + 0x1ad0, /* VGETEXPSDZrb */ +/* Table14585 */ + 0x2917, /* VPLZCNTQZ128rmb */ + 0x0, /* */ +/* Table14587 */ + 0x340b, /* VPSRLVQZ128rmb */ + 0x0, /* */ +/* Table14589 */ + 0x3325, /* VPSRAVQZ128rmb */ + 0x0, /* */ +/* Table14591 */ + 0x324d, /* VPSLLVQZ128rmb */ + 0x0, /* */ +/* Table14593 */ + 0x3734, /* VRCP14PDZ128mb */ + 0x0, /* */ +/* Table14595 */ + 0x3858, /* VRSQRT14PDZ128mb */ + 0x0, /* */ +/* Table14597 */ + 0x2e94, /* VPOPCNTQZ128rmb */ + 0x0, /* */ +/* Table14599 */ + 0x22a7, /* VPBLENDMQZ128rmb */ + 0x0, /* */ +/* Table14601 */ + 0xca1, /* VBLENDMPDZ128rmb */ + 0x0, /* */ +/* Table14603 */ + 0x306a, /* VPSHLDVQZ128mb */ + 0x0, /* */ +/* Table14605 */ + 0x3106, /* VPSHRDVQZ128mb */ + 0x0, /* */ +/* Table14607 */ + 0x268b, /* VPERMI2Q128rmb */ + 0x0, /* */ +/* Table14609 */ + 0x2655, /* VPERMI2PD128rmb */ + 0x0, /* */ +/* Table14611 */ + 0x2807, /* VPERMT2Q128rmb */ + 0x0, /* */ +/* Table14613 */ + 0x27d1, /* VPERMT2PD128rmb */ + 0x0, /* */ +/* Table14615 */ + 0x2e2d, /* VPMULTISHIFTQBZ128rmb */ + 0x0, /* */ +/* Table14617 */ + 0x14a3, /* VFMADDSUB132PDZ128mb */ + 0x14bb, /* VFMADDSUB132PDZrb */ +/* Table14619 */ + 0x16ab, /* VFMSUBADD132PDZ128mb */ + 0x16c3, /* VFMSUBADD132PDZrb */ +/* Table14621 */ + 0x1357, /* VFMADD132PDZ128mb */ + 0x136f, /* VFMADD132PDZrb */ +/* Table14623 */ + 0x0, /* */ + 0x13a1, /* VFMADD132SDZrb_Int */ +/* Table14625 */ + 0x157f, /* VFMSUB132PDZ128mb */ + 0x1597, /* VFMSUB132PDZrb */ +/* Table14627 */ + 0x0, /* */ + 0x15c9, /* VFMSUB132SDZrb_Int */ +/* Table14629 */ + 0x17a7, /* VFNMADD132PDZ128mb */ + 0x17bf, /* VFNMADD132PDZrb */ +/* Table14631 */ + 0x0, /* */ + 0x17f1, /* VFNMADD132SDZrb_Int */ +/* Table14633 */ + 0x18f3, /* VFNMSUB132PDZ128mb */ + 0x190b, /* VFNMSUB132PDZrb */ +/* Table14635 */ + 0x0, /* */ + 0x193d, /* VFNMSUB132SDZrb_Int */ +/* Table14637 */ + 0x14e7, /* VFMADDSUB213PDZ128mb */ + 0x14ff, /* VFMADDSUB213PDZrb */ +/* Table14639 */ + 0x16ef, /* VFMSUBADD213PDZ128mb */ + 0x1707, /* VFMSUBADD213PDZrb */ +/* Table14641 */ + 0x13bb, /* VFMADD213PDZ128mb */ + 0x13d3, /* VFMADD213PDZrb */ +/* Table14643 */ + 0x0, /* */ + 0x1405, /* VFMADD213SDZrb_Int */ +/* Table14645 */ + 0x15e3, /* VFMSUB213PDZ128mb */ + 0x15fb, /* VFMSUB213PDZrb */ +/* Table14647 */ + 0x0, /* */ + 0x162d, /* VFMSUB213SDZrb_Int */ +/* Table14649 */ + 0x180b, /* VFNMADD213PDZ128mb */ + 0x1823, /* VFNMADD213PDZrb */ +/* Table14651 */ + 0x0, /* */ + 0x1855, /* VFNMADD213SDZrb_Int */ +/* Table14653 */ + 0x1957, /* VFNMSUB213PDZ128mb */ + 0x196f, /* VFNMSUB213PDZrb */ +/* Table14655 */ + 0x0, /* */ + 0x19a1, /* VFNMSUB213SDZrb_Int */ +/* Table14657 */ + 0x2965, /* VPMADD52LUQZ128mb */ + 0x0, /* */ +/* Table14659 */ + 0x294a, /* VPMADD52HUQZ128mb */ + 0x0, /* */ +/* Table14661 */ + 0x152b, /* VFMADDSUB231PDZ128mb */ + 0x1543, /* VFMADDSUB231PDZrb */ +/* Table14663 */ + 0x1733, /* VFMSUBADD231PDZ128mb */ + 0x174b, /* VFMSUBADD231PDZrb */ +/* Table14665 */ + 0x141f, /* VFMADD231PDZ128mb */ + 0x1437, /* VFMADD231PDZrb */ +/* Table14667 */ + 0x0, /* */ + 0x1469, /* VFMADD231SDZrb_Int */ +/* Table14669 */ + 0x1647, /* VFMSUB231PDZ128mb */ + 0x165f, /* VFMSUB231PDZrb */ +/* Table14671 */ + 0x0, /* */ + 0x1691, /* VFMSUB231SDZrb_Int */ +/* Table14673 */ + 0x186f, /* VFNMADD231PDZ128mb */ + 0x1887, /* VFNMADD231PDZrb */ +/* Table14675 */ + 0x0, /* */ + 0x18b9, /* VFNMADD231SDZrb_Int */ +/* Table14677 */ + 0x19bb, /* VFNMSUB231PDZ128mb */ + 0x19d3, /* VFNMSUB231PDZrb */ +/* Table14679 */ + 0x0, /* */ + 0x1a05, /* VFNMSUB231SDZrb_Int */ +/* Table14681 */ + 0x2577, /* VPCONFLICTQZ128rmb */ + 0x0, /* */ +/* Table14683 */ + 0x0, /* */ + 0x128d, /* VEXP2PDZrb */ +/* Table14685 */ + 0x0, /* */ + 0x377c, /* VRCP28PDZrb */ +/* Table14687 */ + 0x0, /* */ + 0x3791, /* VRCP28SDZrb */ +/* Table14689 */ + 0x0, /* */ + 0x38a0, /* VRSQRT28PDZrb */ +/* Table14691 */ + 0x0, /* */ + 0x38b5, /* VRSQRT28SDZrb */ +/* Table14693 */ + 0x35aa, /* VPTESTNMDZ256rmb */ + 0x0, /* */ +/* Table14695 */ + 0x2725, /* VPERMILPSZ256rmb */ + 0x0, /* */ +/* Table14697 */ + 0x2faa, /* VPRORVDZ256rmb */ + 0x0, /* */ +/* Table14699 */ + 0x2f3e, /* VPROLVDZ256rmb */ + 0x0, /* */ +/* Table14701 */ + 0x276c, /* VPERMPSZ256rmb */ + 0x0, /* */ +/* Table14703 */ + 0x204f, /* VPABSDZ256rmb */ + 0x0, /* */ +/* Table14705 */ + 0x356e, /* VPTESTMDZ256rmb */ + 0x0, /* */ +/* Table14707 */ + 0x20d4, /* VPACKUSDWZ256rmb */ + 0x0, /* */ +/* Table14709 */ + 0x38f3, /* VSCALEFPSZ256rmb */ + 0x3902, /* VSCALEFPSZrrb */ +/* Table14711 */ + 0x2616, /* VPERMDZ256rmb */ + 0x0, /* */ +/* Table14713 */ + 0x2aa1, /* VPMINSDZ256rmb */ + 0x0, /* */ +/* Table14715 */ + 0x2b07, /* VPMINUDZ256rmb */ + 0x0, /* */ +/* Table14717 */ + 0x29d5, /* VPMAXSDZ256rmb */ + 0x0, /* */ +/* Table14719 */ + 0x2a3b, /* VPMAXUDZ256rmb */ + 0x0, /* */ +/* Table14721 */ + 0x2de8, /* VPMULLDZ256rmb */ + 0x0, /* */ +/* Table14723 */ + 0x1ab8, /* VGETEXPPSZ256mb */ + 0x1ac7, /* VGETEXPPSZrb */ +/* Table14725 */ + 0x2905, /* VPLZCNTDZ256rmb */ + 0x0, /* */ +/* Table14727 */ + 0x33f5, /* VPSRLVDZ256rmb */ + 0x0, /* */ +/* Table14729 */ + 0x3311, /* VPSRAVDZ256rmb */ + 0x0, /* */ +/* Table14731 */ + 0x3237, /* VPSLLVDZ256rmb */ + 0x0, /* */ +/* Table14733 */ + 0x3758, /* VRCP14PSZ256mb */ + 0x0, /* */ +/* Table14735 */ + 0x387c, /* VRSQRT14PSZ256mb */ + 0x0, /* */ +/* Table14737 */ + 0x25b6, /* VPDPBUSDZ256mb */ + 0x0, /* */ +/* Table14739 */ + 0x259b, /* VPDPBUSDSZ256mb */ + 0x0, /* */ +/* Table14741 */ + 0x25ec, /* VPDPWSSDZ256mb */ + 0x0, /* */ +/* Table14743 */ + 0x25d1, /* VPDPWSSDSZ256mb */ + 0x0, /* */ +/* Table14745 */ + 0x2e82, /* VPOPCNTDZ256rmb */ + 0x0, /* */ +/* Table14747 */ + 0x2295, /* VPBLENDMDZ256rmb */ + 0x0, /* */ +/* Table14749 */ + 0xcc5, /* VBLENDMPSZ256rmb */ + 0x0, /* */ +/* Table14751 */ + 0x3058, /* VPSHLDVDZ256mb */ + 0x0, /* */ +/* Table14753 */ + 0x30f4, /* VPSHRDVDZ256mb */ + 0x0, /* */ +/* Table14755 */ + 0x2643, /* VPERMI2D256rmb */ + 0x0, /* */ +/* Table14757 */ + 0x2679, /* VPERMI2PS256rmb */ + 0x0, /* */ +/* Table14759 */ + 0x27bf, /* VPERMT2D256rmb */ + 0x0, /* */ +/* Table14761 */ + 0x27f5, /* VPERMT2PS256rmb */ + 0x0, /* */ +/* Table14763 */ + 0x14ce, /* VFMADDSUB132PSZ256mb */ + 0x14dd, /* VFMADDSUB132PSZrb */ +/* Table14765 */ + 0x16d6, /* VFMSUBADD132PSZ256mb */ + 0x16e5, /* VFMSUBADD132PSZrb */ +/* Table14767 */ + 0x1382, /* VFMADD132PSZ256mb */ + 0x1391, /* VFMADD132PSZrb */ +/* Table14769 */ + 0x15aa, /* VFMSUB132PSZ256mb */ + 0x15b9, /* VFMSUB132PSZrb */ +/* Table14771 */ + 0x17d2, /* VFNMADD132PSZ256mb */ + 0x17e1, /* VFNMADD132PSZrb */ +/* Table14773 */ + 0x191e, /* VFNMSUB132PSZ256mb */ + 0x192d, /* VFNMSUB132PSZrb */ +/* Table14775 */ + 0x1512, /* VFMADDSUB213PSZ256mb */ + 0x1521, /* VFMADDSUB213PSZrb */ +/* Table14777 */ + 0x171a, /* VFMSUBADD213PSZ256mb */ + 0x1729, /* VFMSUBADD213PSZrb */ +/* Table14779 */ + 0x13e6, /* VFMADD213PSZ256mb */ + 0x13f5, /* VFMADD213PSZrb */ +/* Table14781 */ + 0x160e, /* VFMSUB213PSZ256mb */ + 0x161d, /* VFMSUB213PSZrb */ +/* Table14783 */ + 0x1836, /* VFNMADD213PSZ256mb */ + 0x1845, /* VFNMADD213PSZrb */ +/* Table14785 */ + 0x1982, /* VFNMSUB213PSZ256mb */ + 0x1991, /* VFNMSUB213PSZrb */ +/* Table14787 */ + 0x1556, /* VFMADDSUB231PSZ256mb */ + 0x1565, /* VFMADDSUB231PSZrb */ +/* Table14789 */ + 0x175e, /* VFMSUBADD231PSZ256mb */ + 0x176d, /* VFMSUBADD231PSZrb */ +/* Table14791 */ + 0x144a, /* VFMADD231PSZ256mb */ + 0x1459, /* VFMADD231PSZrb */ +/* Table14793 */ + 0x1672, /* VFMSUB231PSZ256mb */ + 0x1681, /* VFMSUB231PSZrb */ +/* Table14795 */ + 0x189a, /* VFNMADD231PSZ256mb */ + 0x18a9, /* VFNMADD231PSZrb */ +/* Table14797 */ + 0x19e6, /* VFNMSUB231PSZ256mb */ + 0x19f5, /* VFNMSUB231PSZrb */ +/* Table14799 */ + 0x2565, /* VPCONFLICTDZ256rmb */ + 0x0, /* */ +/* Table14801 */ + 0x35bc, /* VPTESTNMQZ256rmb */ + 0x0, /* */ +/* Table14803 */ + 0x26e7, /* VPERMILPDZ256rmb */ + 0x0, /* */ +/* Table14805 */ + 0x2fc5, /* VPRORVQZ256rmb */ + 0x0, /* */ +/* Table14807 */ + 0x2f59, /* VPROLVQZ256rmb */ + 0x0, /* */ +/* Table14809 */ + 0x274f, /* VPERMPDZ256rmb */ + 0x0, /* */ +/* Table14811 */ + 0x206c, /* VPABSQZ256rmb */ + 0x0, /* */ +/* Table14813 */ + 0x3580, /* VPTESTMQZ256rmb */ + 0x0, /* */ +/* Table14815 */ + 0x2d87, /* VPMULDQZ256rmb */ + 0x0, /* */ +/* Table14817 */ + 0x23da, /* VPCMPEQQZ256rmb */ + 0x0, /* */ +/* Table14819 */ + 0x38d5, /* VSCALEFPDZ256rmb */ + 0x38e4, /* VSCALEFPDZrrb */ +/* Table14821 */ + 0x2789, /* VPERMQZ256rmb */ + 0x0, /* */ +/* Table14823 */ + 0x242a, /* VPCMPGTQZ256rmb */ + 0x0, /* */ +/* Table14825 */ + 0x2abe, /* VPMINSQZ256rmb */ + 0x0, /* */ +/* Table14827 */ + 0x2b24, /* VPMINUQZ256rmb */ + 0x0, /* */ +/* Table14829 */ + 0x29f2, /* VPMAXSQZ256rmb */ + 0x0, /* */ +/* Table14831 */ + 0x2a58, /* VPMAXUQZ256rmb */ + 0x0, /* */ +/* Table14833 */ + 0x2e05, /* VPMULLQZ256rmb */ + 0x0, /* */ +/* Table14835 */ + 0x1a9a, /* VGETEXPPDZ256mb */ + 0x1aa9, /* VGETEXPPDZrb */ +/* Table14837 */ + 0x2920, /* VPLZCNTQZ256rmb */ + 0x0, /* */ +/* Table14839 */ + 0x3414, /* VPSRLVQZ256rmb */ + 0x0, /* */ +/* Table14841 */ + 0x332e, /* VPSRAVQZ256rmb */ + 0x0, /* */ +/* Table14843 */ + 0x3256, /* VPSLLVQZ256rmb */ + 0x0, /* */ +/* Table14845 */ + 0x373d, /* VRCP14PDZ256mb */ + 0x0, /* */ +/* Table14847 */ + 0x3861, /* VRSQRT14PDZ256mb */ + 0x0, /* */ +/* Table14849 */ + 0x2e9d, /* VPOPCNTQZ256rmb */ + 0x0, /* */ +/* Table14851 */ + 0x22b0, /* VPBLENDMQZ256rmb */ + 0x0, /* */ +/* Table14853 */ + 0xcaa, /* VBLENDMPDZ256rmb */ + 0x0, /* */ +/* Table14855 */ + 0x3073, /* VPSHLDVQZ256mb */ + 0x0, /* */ +/* Table14857 */ + 0x310f, /* VPSHRDVQZ256mb */ + 0x0, /* */ +/* Table14859 */ + 0x2694, /* VPERMI2Q256rmb */ + 0x0, /* */ +/* Table14861 */ + 0x265e, /* VPERMI2PD256rmb */ + 0x0, /* */ +/* Table14863 */ + 0x2810, /* VPERMT2Q256rmb */ + 0x0, /* */ +/* Table14865 */ + 0x27da, /* VPERMT2PD256rmb */ + 0x0, /* */ +/* Table14867 */ + 0x2e36, /* VPMULTISHIFTQBZ256rmb */ + 0x0, /* */ +/* Table14869 */ + 0x14ac, /* VFMADDSUB132PDZ256mb */ + 0x14bb, /* VFMADDSUB132PDZrb */ +/* Table14871 */ + 0x16b4, /* VFMSUBADD132PDZ256mb */ + 0x16c3, /* VFMSUBADD132PDZrb */ +/* Table14873 */ + 0x1360, /* VFMADD132PDZ256mb */ + 0x136f, /* VFMADD132PDZrb */ +/* Table14875 */ + 0x1588, /* VFMSUB132PDZ256mb */ + 0x1597, /* VFMSUB132PDZrb */ +/* Table14877 */ + 0x17b0, /* VFNMADD132PDZ256mb */ + 0x17bf, /* VFNMADD132PDZrb */ +/* Table14879 */ + 0x18fc, /* VFNMSUB132PDZ256mb */ + 0x190b, /* VFNMSUB132PDZrb */ +/* Table14881 */ + 0x14f0, /* VFMADDSUB213PDZ256mb */ + 0x14ff, /* VFMADDSUB213PDZrb */ +/* Table14883 */ + 0x16f8, /* VFMSUBADD213PDZ256mb */ + 0x1707, /* VFMSUBADD213PDZrb */ +/* Table14885 */ + 0x13c4, /* VFMADD213PDZ256mb */ + 0x13d3, /* VFMADD213PDZrb */ +/* Table14887 */ + 0x15ec, /* VFMSUB213PDZ256mb */ + 0x15fb, /* VFMSUB213PDZrb */ +/* Table14889 */ + 0x1814, /* VFNMADD213PDZ256mb */ + 0x1823, /* VFNMADD213PDZrb */ +/* Table14891 */ + 0x1960, /* VFNMSUB213PDZ256mb */ + 0x196f, /* VFNMSUB213PDZrb */ +/* Table14893 */ + 0x296e, /* VPMADD52LUQZ256mb */ + 0x0, /* */ +/* Table14895 */ + 0x2953, /* VPMADD52HUQZ256mb */ + 0x0, /* */ +/* Table14897 */ + 0x1534, /* VFMADDSUB231PDZ256mb */ + 0x1543, /* VFMADDSUB231PDZrb */ +/* Table14899 */ + 0x173c, /* VFMSUBADD231PDZ256mb */ + 0x174b, /* VFMSUBADD231PDZrb */ +/* Table14901 */ + 0x1428, /* VFMADD231PDZ256mb */ + 0x1437, /* VFMADD231PDZrb */ +/* Table14903 */ + 0x1650, /* VFMSUB231PDZ256mb */ + 0x165f, /* VFMSUB231PDZrb */ +/* Table14905 */ + 0x1878, /* VFNMADD231PDZ256mb */ + 0x1887, /* VFNMADD231PDZrb */ +/* Table14907 */ + 0x19c4, /* VFNMSUB231PDZ256mb */ + 0x19d3, /* VFNMSUB231PDZrb */ +/* Table14909 */ + 0x2580, /* VPCONFLICTQZ256rmb */ + 0x0, /* */ +/* Table14911 */ + 0x35b0, /* VPTESTNMDZrmb */ + 0x0, /* */ +/* Table14913 */ + 0x2737, /* VPERMILPSZrmb */ + 0x0, /* */ +/* Table14915 */ + 0x2fb3, /* VPRORVDZrmb */ + 0x0, /* */ +/* Table14917 */ + 0x2f47, /* VPROLVDZrmb */ + 0x0, /* */ +/* Table14919 */ + 0x2775, /* VPERMPSZrmb */ + 0x0, /* */ +/* Table14921 */ + 0x2058, /* VPABSDZrmb */ + 0x0, /* */ +/* Table14923 */ + 0x3574, /* VPTESTMDZrmb */ + 0x0, /* */ +/* Table14925 */ + 0x20dd, /* VPACKUSDWZrmb */ + 0x0, /* */ +/* Table14927 */ + 0x38fc, /* VSCALEFPSZrmb */ + 0x3902, /* VSCALEFPSZrrb */ +/* Table14929 */ + 0x261f, /* VPERMDZrmb */ + 0x0, /* */ +/* Table14931 */ + 0x2aaa, /* VPMINSDZrmb */ + 0x0, /* */ +/* Table14933 */ + 0x2b10, /* VPMINUDZrmb */ + 0x0, /* */ +/* Table14935 */ + 0x29de, /* VPMAXSDZrmb */ + 0x0, /* */ +/* Table14937 */ + 0x2a44, /* VPMAXUDZrmb */ + 0x0, /* */ +/* Table14939 */ + 0x2df1, /* VPMULLDZrmb */ + 0x0, /* */ +/* Table14941 */ + 0x1ac1, /* VGETEXPPSZmb */ + 0x1ac7, /* VGETEXPPSZrb */ +/* Table14943 */ + 0x290e, /* VPLZCNTDZrmb */ + 0x0, /* */ +/* Table14945 */ + 0x33fe, /* VPSRLVDZrmb */ + 0x0, /* */ +/* Table14947 */ + 0x331a, /* VPSRAVDZrmb */ + 0x0, /* */ +/* Table14949 */ + 0x3240, /* VPSLLVDZrmb */ + 0x0, /* */ +/* Table14951 */ + 0x3761, /* VRCP14PSZmb */ + 0x0, /* */ +/* Table14953 */ + 0x3885, /* VRSQRT14PSZmb */ + 0x0, /* */ +/* Table14955 */ + 0x25bf, /* VPDPBUSDZmb */ + 0x0, /* */ +/* Table14957 */ + 0x25a4, /* VPDPBUSDSZmb */ + 0x0, /* */ +/* Table14959 */ + 0x25f5, /* VPDPWSSDZmb */ + 0x0, /* */ +/* Table14961 */ + 0x25da, /* VPDPWSSDSZmb */ + 0x0, /* */ +/* Table14963 */ + 0x2e8b, /* VPOPCNTDZrmb */ + 0x0, /* */ +/* Table14965 */ + 0x229e, /* VPBLENDMDZrmb */ + 0x0, /* */ +/* Table14967 */ + 0xcce, /* VBLENDMPSZrmb */ + 0x0, /* */ +/* Table14969 */ + 0x3061, /* VPSHLDVDZmb */ + 0x0, /* */ +/* Table14971 */ + 0x30fd, /* VPSHRDVDZmb */ + 0x0, /* */ +/* Table14973 */ + 0x264c, /* VPERMI2Drmb */ + 0x0, /* */ +/* Table14975 */ + 0x2682, /* VPERMI2PSrmb */ + 0x0, /* */ +/* Table14977 */ + 0x27c8, /* VPERMT2Drmb */ + 0x0, /* */ +/* Table14979 */ + 0x27fe, /* VPERMT2PSrmb */ + 0x0, /* */ +/* Table14981 */ + 0x14d7, /* VFMADDSUB132PSZmb */ + 0x14dd, /* VFMADDSUB132PSZrb */ +/* Table14983 */ + 0x16df, /* VFMSUBADD132PSZmb */ + 0x16e5, /* VFMSUBADD132PSZrb */ +/* Table14985 */ + 0x138b, /* VFMADD132PSZmb */ + 0x1391, /* VFMADD132PSZrb */ +/* Table14987 */ + 0x15b3, /* VFMSUB132PSZmb */ + 0x15b9, /* VFMSUB132PSZrb */ +/* Table14989 */ + 0x17db, /* VFNMADD132PSZmb */ + 0x17e1, /* VFNMADD132PSZrb */ +/* Table14991 */ + 0x1927, /* VFNMSUB132PSZmb */ + 0x192d, /* VFNMSUB132PSZrb */ +/* Table14993 */ + 0x151b, /* VFMADDSUB213PSZmb */ + 0x1521, /* VFMADDSUB213PSZrb */ +/* Table14995 */ + 0x1723, /* VFMSUBADD213PSZmb */ + 0x1729, /* VFMSUBADD213PSZrb */ +/* Table14997 */ + 0x13ef, /* VFMADD213PSZmb */ + 0x13f5, /* VFMADD213PSZrb */ +/* Table14999 */ + 0x1617, /* VFMSUB213PSZmb */ + 0x161d, /* VFMSUB213PSZrb */ +/* Table15001 */ + 0x183f, /* VFNMADD213PSZmb */ + 0x1845, /* VFNMADD213PSZrb */ +/* Table15003 */ + 0x198b, /* VFNMSUB213PSZmb */ + 0x1991, /* VFNMSUB213PSZrb */ +/* Table15005 */ + 0x155f, /* VFMADDSUB231PSZmb */ + 0x1565, /* VFMADDSUB231PSZrb */ +/* Table15007 */ + 0x1767, /* VFMSUBADD231PSZmb */ + 0x176d, /* VFMSUBADD231PSZrb */ +/* Table15009 */ + 0x1453, /* VFMADD231PSZmb */ + 0x1459, /* VFMADD231PSZrb */ +/* Table15011 */ + 0x167b, /* VFMSUB231PSZmb */ + 0x1681, /* VFMSUB231PSZrb */ +/* Table15013 */ + 0x18a3, /* VFNMADD231PSZmb */ + 0x18a9, /* VFNMADD231PSZrb */ +/* Table15015 */ + 0x19ef, /* VFNMSUB231PSZmb */ + 0x19f5, /* VFNMSUB231PSZrb */ +/* Table15017 */ + 0x256e, /* VPCONFLICTDZrmb */ + 0x0, /* */ +/* Table15019 */ + 0x1293, /* VEXP2PSZmb */ + 0x1299, /* VEXP2PSZrb */ +/* Table15021 */ + 0x3782, /* VRCP28PSZmb */ + 0x3788, /* VRCP28PSZrb */ +/* Table15023 */ + 0x38a6, /* VRSQRT28PSZmb */ + 0x38ac, /* VRSQRT28PSZrb */ +/* Table15025 */ + 0x35c2, /* VPTESTNMQZrmb */ + 0x0, /* */ +/* Table15027 */ + 0x26f9, /* VPERMILPDZrmb */ + 0x0, /* */ +/* Table15029 */ + 0x2fce, /* VPRORVQZrmb */ + 0x0, /* */ +/* Table15031 */ + 0x2f62, /* VPROLVQZrmb */ + 0x0, /* */ +/* Table15033 */ + 0x2761, /* VPERMPDZrmb */ + 0x0, /* */ +/* Table15035 */ + 0x2075, /* VPABSQZrmb */ + 0x0, /* */ +/* Table15037 */ + 0x3586, /* VPTESTMQZrmb */ + 0x0, /* */ +/* Table15039 */ + 0x2d90, /* VPMULDQZrmb */ + 0x0, /* */ +/* Table15041 */ + 0x23e0, /* VPCMPEQQZrmb */ + 0x0, /* */ +/* Table15043 */ + 0x38de, /* VSCALEFPDZrmb */ + 0x38e4, /* VSCALEFPDZrrb */ +/* Table15045 */ + 0x279b, /* VPERMQZrmb */ + 0x0, /* */ +/* Table15047 */ + 0x2430, /* VPCMPGTQZrmb */ + 0x0, /* */ +/* Table15049 */ + 0x2ac7, /* VPMINSQZrmb */ + 0x0, /* */ +/* Table15051 */ + 0x2b2d, /* VPMINUQZrmb */ + 0x0, /* */ +/* Table15053 */ + 0x29fb, /* VPMAXSQZrmb */ + 0x0, /* */ +/* Table15055 */ + 0x2a61, /* VPMAXUQZrmb */ + 0x0, /* */ +/* Table15057 */ + 0x2e0e, /* VPMULLQZrmb */ + 0x0, /* */ +/* Table15059 */ + 0x1aa3, /* VGETEXPPDZmb */ + 0x1aa9, /* VGETEXPPDZrb */ +/* Table15061 */ + 0x2929, /* VPLZCNTQZrmb */ + 0x0, /* */ +/* Table15063 */ + 0x341d, /* VPSRLVQZrmb */ + 0x0, /* */ +/* Table15065 */ + 0x3337, /* VPSRAVQZrmb */ + 0x0, /* */ +/* Table15067 */ + 0x325f, /* VPSLLVQZrmb */ + 0x0, /* */ +/* Table15069 */ + 0x3746, /* VRCP14PDZmb */ + 0x0, /* */ +/* Table15071 */ + 0x386a, /* VRSQRT14PDZmb */ + 0x0, /* */ +/* Table15073 */ + 0x2ea6, /* VPOPCNTQZrmb */ + 0x0, /* */ +/* Table15075 */ + 0x22b9, /* VPBLENDMQZrmb */ + 0x0, /* */ +/* Table15077 */ + 0xcb3, /* VBLENDMPDZrmb */ + 0x0, /* */ +/* Table15079 */ + 0x307c, /* VPSHLDVQZmb */ + 0x0, /* */ +/* Table15081 */ + 0x3118, /* VPSHRDVQZmb */ + 0x0, /* */ +/* Table15083 */ + 0x269d, /* VPERMI2Qrmb */ + 0x0, /* */ +/* Table15085 */ + 0x2667, /* VPERMI2PDrmb */ + 0x0, /* */ +/* Table15087 */ + 0x2819, /* VPERMT2Qrmb */ + 0x0, /* */ +/* Table15089 */ + 0x27e3, /* VPERMT2PDrmb */ + 0x0, /* */ +/* Table15091 */ + 0x2e3f, /* VPMULTISHIFTQBZrmb */ + 0x0, /* */ +/* Table15093 */ + 0x14b5, /* VFMADDSUB132PDZmb */ + 0x14bb, /* VFMADDSUB132PDZrb */ +/* Table15095 */ + 0x16bd, /* VFMSUBADD132PDZmb */ + 0x16c3, /* VFMSUBADD132PDZrb */ +/* Table15097 */ + 0x1369, /* VFMADD132PDZmb */ + 0x136f, /* VFMADD132PDZrb */ +/* Table15099 */ + 0x1591, /* VFMSUB132PDZmb */ + 0x1597, /* VFMSUB132PDZrb */ +/* Table15101 */ + 0x17b9, /* VFNMADD132PDZmb */ + 0x17bf, /* VFNMADD132PDZrb */ +/* Table15103 */ + 0x1905, /* VFNMSUB132PDZmb */ + 0x190b, /* VFNMSUB132PDZrb */ +/* Table15105 */ + 0x14f9, /* VFMADDSUB213PDZmb */ + 0x14ff, /* VFMADDSUB213PDZrb */ +/* Table15107 */ + 0x1701, /* VFMSUBADD213PDZmb */ + 0x1707, /* VFMSUBADD213PDZrb */ +/* Table15109 */ + 0x13cd, /* VFMADD213PDZmb */ + 0x13d3, /* VFMADD213PDZrb */ +/* Table15111 */ + 0x15f5, /* VFMSUB213PDZmb */ + 0x15fb, /* VFMSUB213PDZrb */ +/* Table15113 */ + 0x181d, /* VFNMADD213PDZmb */ + 0x1823, /* VFNMADD213PDZrb */ +/* Table15115 */ + 0x1969, /* VFNMSUB213PDZmb */ + 0x196f, /* VFNMSUB213PDZrb */ +/* Table15117 */ + 0x2977, /* VPMADD52LUQZmb */ + 0x0, /* */ +/* Table15119 */ + 0x295c, /* VPMADD52HUQZmb */ + 0x0, /* */ +/* Table15121 */ + 0x153d, /* VFMADDSUB231PDZmb */ + 0x1543, /* VFMADDSUB231PDZrb */ +/* Table15123 */ + 0x1745, /* VFMSUBADD231PDZmb */ + 0x174b, /* VFMSUBADD231PDZrb */ +/* Table15125 */ + 0x1431, /* VFMADD231PDZmb */ + 0x1437, /* VFMADD231PDZrb */ +/* Table15127 */ + 0x1659, /* VFMSUB231PDZmb */ + 0x165f, /* VFMSUB231PDZrb */ +/* Table15129 */ + 0x1881, /* VFNMADD231PDZmb */ + 0x1887, /* VFNMADD231PDZrb */ +/* Table15131 */ + 0x19cd, /* VFNMSUB231PDZmb */ + 0x19d3, /* VFNMSUB231PDZrb */ +/* Table15133 */ + 0x2589, /* VPCONFLICTQZrmb */ + 0x0, /* */ +/* Table15135 */ + 0x1287, /* VEXP2PDZmb */ + 0x128d, /* VEXP2PDZrb */ +/* Table15137 */ + 0x3776, /* VRCP28PDZmb */ + 0x377c, /* VRCP28PDZrb */ +/* Table15139 */ + 0x389a, /* VRSQRT28PDZmb */ + 0x38a0, /* VRSQRT28PDZrb */ +/* Table15141 */ + 0x35a5, /* VPTESTNMDZ128rmbk */ + 0x0, /* */ +/* Table15143 */ + 0x2714, /* VPERMILPSZ128rmbk */ + 0x0, /* */ +/* Table15145 */ + 0x0, /* */ + 0xef8, /* VCVTPH2PSZrrbk */ +/* Table15147 */ + 0x2fa2, /* VPRORVDZ128rmbk */ + 0x0, /* */ +/* Table15149 */ + 0x2f36, /* VPROLVDZ128rmbk */ + 0x0, /* */ +/* Table15151 */ + 0x2047, /* VPABSDZ128rmbk */ + 0x0, /* */ +/* Table15153 */ + 0x3569, /* VPTESTMDZ128rmbk */ + 0x0, /* */ +/* Table15155 */ + 0x20cc, /* VPACKUSDWZ128rmbk */ + 0x0, /* */ +/* Table15157 */ + 0x38eb, /* VSCALEFPSZ128rmbk */ + 0x3903, /* VSCALEFPSZrrbk */ +/* Table15159 */ + 0x0, /* */ + 0x3915, /* VSCALEFSSZrrb_Intk */ +/* Table15161 */ + 0x2a99, /* VPMINSDZ128rmbk */ + 0x0, /* */ +/* Table15163 */ + 0x2aff, /* VPMINUDZ128rmbk */ + 0x0, /* */ +/* Table15165 */ + 0x29cd, /* VPMAXSDZ128rmbk */ + 0x0, /* */ +/* Table15167 */ + 0x2a33, /* VPMAXUDZ128rmbk */ + 0x0, /* */ +/* Table15169 */ + 0x2de0, /* VPMULLDZ128rmbk */ + 0x0, /* */ +/* Table15171 */ + 0x1ab0, /* VGETEXPPSZ128mbk */ + 0x1ac8, /* VGETEXPPSZrbk */ +/* Table15173 */ + 0x0, /* */ + 0x1ada, /* VGETEXPSSZrbk */ +/* Table15175 */ + 0x28fd, /* VPLZCNTDZ128rmbk */ + 0x0, /* */ +/* Table15177 */ + 0x33ed, /* VPSRLVDZ128rmbk */ + 0x0, /* */ +/* Table15179 */ + 0x3309, /* VPSRAVDZ128rmbk */ + 0x0, /* */ +/* Table15181 */ + 0x322f, /* VPSLLVDZ128rmbk */ + 0x0, /* */ +/* Table15183 */ + 0x3750, /* VRCP14PSZ128mbk */ + 0x0, /* */ +/* Table15185 */ + 0x3874, /* VRSQRT14PSZ128mbk */ + 0x0, /* */ +/* Table15187 */ + 0x25ae, /* VPDPBUSDZ128mbk */ + 0x0, /* */ +/* Table15189 */ + 0x2593, /* VPDPBUSDSZ128mbk */ + 0x0, /* */ +/* Table15191 */ + 0x25e4, /* VPDPWSSDZ128mbk */ + 0x0, /* */ +/* Table15193 */ + 0x25c9, /* VPDPWSSDSZ128mbk */ + 0x0, /* */ +/* Table15195 */ + 0x2e7a, /* VPOPCNTDZ128rmbk */ + 0x0, /* */ +/* Table15197 */ + 0x228d, /* VPBLENDMDZ128rmbk */ + 0x0, /* */ +/* Table15199 */ + 0xcbd, /* VBLENDMPSZ128rmbk */ + 0x0, /* */ +/* Table15201 */ + 0x3050, /* VPSHLDVDZ128mbk */ + 0x0, /* */ +/* Table15203 */ + 0x30ec, /* VPSHRDVDZ128mbk */ + 0x0, /* */ +/* Table15205 */ + 0x263b, /* VPERMI2D128rmbk */ + 0x0, /* */ +/* Table15207 */ + 0x2671, /* VPERMI2PS128rmbk */ + 0x0, /* */ +/* Table15209 */ + 0x27b7, /* VPERMT2D128rmbk */ + 0x0, /* */ +/* Table15211 */ + 0x27ed, /* VPERMT2PS128rmbk */ + 0x0, /* */ +/* Table15213 */ + 0x14c6, /* VFMADDSUB132PSZ128mbk */ + 0x14de, /* VFMADDSUB132PSZrbk */ +/* Table15215 */ + 0x16ce, /* VFMSUBADD132PSZ128mbk */ + 0x16e6, /* VFMSUBADD132PSZrbk */ +/* Table15217 */ + 0x137a, /* VFMADD132PSZ128mbk */ + 0x1392, /* VFMADD132PSZrbk */ +/* Table15219 */ + 0x0, /* */ + 0x13b2, /* VFMADD132SSZrb_Intk */ +/* Table15221 */ + 0x15a2, /* VFMSUB132PSZ128mbk */ + 0x15ba, /* VFMSUB132PSZrbk */ +/* Table15223 */ + 0x0, /* */ + 0x15da, /* VFMSUB132SSZrb_Intk */ +/* Table15225 */ + 0x17ca, /* VFNMADD132PSZ128mbk */ + 0x17e2, /* VFNMADD132PSZrbk */ +/* Table15227 */ + 0x0, /* */ + 0x1802, /* VFNMADD132SSZrb_Intk */ +/* Table15229 */ + 0x1916, /* VFNMSUB132PSZ128mbk */ + 0x192e, /* VFNMSUB132PSZrbk */ +/* Table15231 */ + 0x0, /* */ + 0x194e, /* VFNMSUB132SSZrb_Intk */ +/* Table15233 */ + 0x150a, /* VFMADDSUB213PSZ128mbk */ + 0x1522, /* VFMADDSUB213PSZrbk */ +/* Table15235 */ + 0x1712, /* VFMSUBADD213PSZ128mbk */ + 0x172a, /* VFMSUBADD213PSZrbk */ +/* Table15237 */ + 0x13de, /* VFMADD213PSZ128mbk */ + 0x13f6, /* VFMADD213PSZrbk */ +/* Table15239 */ + 0x0, /* */ + 0x1416, /* VFMADD213SSZrb_Intk */ +/* Table15241 */ + 0x1606, /* VFMSUB213PSZ128mbk */ + 0x161e, /* VFMSUB213PSZrbk */ +/* Table15243 */ + 0x0, /* */ + 0x163e, /* VFMSUB213SSZrb_Intk */ +/* Table15245 */ + 0x182e, /* VFNMADD213PSZ128mbk */ + 0x1846, /* VFNMADD213PSZrbk */ +/* Table15247 */ + 0x0, /* */ + 0x1866, /* VFNMADD213SSZrb_Intk */ +/* Table15249 */ + 0x197a, /* VFNMSUB213PSZ128mbk */ + 0x1992, /* VFNMSUB213PSZrbk */ +/* Table15251 */ + 0x0, /* */ + 0x19b2, /* VFNMSUB213SSZrb_Intk */ +/* Table15253 */ + 0x154e, /* VFMADDSUB231PSZ128mbk */ + 0x1566, /* VFMADDSUB231PSZrbk */ +/* Table15255 */ + 0x1756, /* VFMSUBADD231PSZ128mbk */ + 0x176e, /* VFMSUBADD231PSZrbk */ +/* Table15257 */ + 0x1442, /* VFMADD231PSZ128mbk */ + 0x145a, /* VFMADD231PSZrbk */ +/* Table15259 */ + 0x0, /* */ + 0x147a, /* VFMADD231SSZrb_Intk */ +/* Table15261 */ + 0x166a, /* VFMSUB231PSZ128mbk */ + 0x1682, /* VFMSUB231PSZrbk */ +/* Table15263 */ + 0x0, /* */ + 0x16a2, /* VFMSUB231SSZrb_Intk */ +/* Table15265 */ + 0x1892, /* VFNMADD231PSZ128mbk */ + 0x18aa, /* VFNMADD231PSZrbk */ +/* Table15267 */ + 0x0, /* */ + 0x18ca, /* VFNMADD231SSZrb_Intk */ +/* Table15269 */ + 0x19de, /* VFNMSUB231PSZ128mbk */ + 0x19f6, /* VFNMSUB231PSZrbk */ +/* Table15271 */ + 0x0, /* */ + 0x1a16, /* VFNMSUB231SSZrb_Intk */ +/* Table15273 */ + 0x255d, /* VPCONFLICTDZ128rmbk */ + 0x0, /* */ +/* Table15275 */ + 0x0, /* */ + 0x129a, /* VEXP2PSZrbk */ +/* Table15277 */ + 0x0, /* */ + 0x3789, /* VRCP28PSZrbk */ +/* Table15279 */ + 0x0, /* */ + 0x379b, /* VRCP28SSZrbk */ +/* Table15281 */ + 0x0, /* */ + 0x38ad, /* VRSQRT28PSZrbk */ +/* Table15283 */ + 0x0, /* */ + 0x38bf, /* VRSQRT28SSZrbk */ +/* Table15285 */ + 0x35b7, /* VPTESTNMQZ128rmbk */ + 0x0, /* */ +/* Table15287 */ + 0x26d6, /* VPERMILPDZ128rmbk */ + 0x0, /* */ +/* Table15289 */ + 0x2fbd, /* VPRORVQZ128rmbk */ + 0x0, /* */ +/* Table15291 */ + 0x2f51, /* VPROLVQZ128rmbk */ + 0x0, /* */ +/* Table15293 */ + 0x2064, /* VPABSQZ128rmbk */ + 0x0, /* */ +/* Table15295 */ + 0x357b, /* VPTESTMQZ128rmbk */ + 0x0, /* */ +/* Table15297 */ + 0x2d7f, /* VPMULDQZ128rmbk */ + 0x0, /* */ +/* Table15299 */ + 0x23d5, /* VPCMPEQQZ128rmbk */ + 0x0, /* */ +/* Table15301 */ + 0x38cd, /* VSCALEFPDZ128rmbk */ + 0x38e5, /* VSCALEFPDZrrbk */ +/* Table15303 */ + 0x0, /* */ + 0x390c, /* VSCALEFSDZrrb_Intk */ +/* Table15305 */ + 0x2425, /* VPCMPGTQZ128rmbk */ + 0x0, /* */ +/* Table15307 */ + 0x2ab6, /* VPMINSQZ128rmbk */ + 0x0, /* */ +/* Table15309 */ + 0x2b1c, /* VPMINUQZ128rmbk */ + 0x0, /* */ +/* Table15311 */ + 0x29ea, /* VPMAXSQZ128rmbk */ + 0x0, /* */ +/* Table15313 */ + 0x2a50, /* VPMAXUQZ128rmbk */ + 0x0, /* */ +/* Table15315 */ + 0x2dfd, /* VPMULLQZ128rmbk */ + 0x0, /* */ +/* Table15317 */ + 0x1a92, /* VGETEXPPDZ128mbk */ + 0x1aaa, /* VGETEXPPDZrbk */ +/* Table15319 */ + 0x0, /* */ + 0x1ad1, /* VGETEXPSDZrbk */ +/* Table15321 */ + 0x2918, /* VPLZCNTQZ128rmbk */ + 0x0, /* */ +/* Table15323 */ + 0x340c, /* VPSRLVQZ128rmbk */ + 0x0, /* */ +/* Table15325 */ + 0x3326, /* VPSRAVQZ128rmbk */ + 0x0, /* */ +/* Table15327 */ + 0x324e, /* VPSLLVQZ128rmbk */ + 0x0, /* */ +/* Table15329 */ + 0x3735, /* VRCP14PDZ128mbk */ + 0x0, /* */ +/* Table15331 */ + 0x3859, /* VRSQRT14PDZ128mbk */ + 0x0, /* */ +/* Table15333 */ + 0x2e95, /* VPOPCNTQZ128rmbk */ + 0x0, /* */ +/* Table15335 */ + 0x22a8, /* VPBLENDMQZ128rmbk */ + 0x0, /* */ +/* Table15337 */ + 0xca2, /* VBLENDMPDZ128rmbk */ + 0x0, /* */ +/* Table15339 */ + 0x306b, /* VPSHLDVQZ128mbk */ + 0x0, /* */ +/* Table15341 */ + 0x3107, /* VPSHRDVQZ128mbk */ + 0x0, /* */ +/* Table15343 */ + 0x268c, /* VPERMI2Q128rmbk */ + 0x0, /* */ +/* Table15345 */ + 0x2656, /* VPERMI2PD128rmbk */ + 0x0, /* */ +/* Table15347 */ + 0x2808, /* VPERMT2Q128rmbk */ + 0x0, /* */ +/* Table15349 */ + 0x27d2, /* VPERMT2PD128rmbk */ + 0x0, /* */ +/* Table15351 */ + 0x2e2e, /* VPMULTISHIFTQBZ128rmbk */ + 0x0, /* */ +/* Table15353 */ + 0x14a4, /* VFMADDSUB132PDZ128mbk */ + 0x14bc, /* VFMADDSUB132PDZrbk */ +/* Table15355 */ + 0x16ac, /* VFMSUBADD132PDZ128mbk */ + 0x16c4, /* VFMSUBADD132PDZrbk */ +/* Table15357 */ + 0x1358, /* VFMADD132PDZ128mbk */ + 0x1370, /* VFMADD132PDZrbk */ +/* Table15359 */ + 0x0, /* */ + 0x13a2, /* VFMADD132SDZrb_Intk */ +/* Table15361 */ + 0x1580, /* VFMSUB132PDZ128mbk */ + 0x1598, /* VFMSUB132PDZrbk */ +/* Table15363 */ + 0x0, /* */ + 0x15ca, /* VFMSUB132SDZrb_Intk */ +/* Table15365 */ + 0x17a8, /* VFNMADD132PDZ128mbk */ + 0x17c0, /* VFNMADD132PDZrbk */ +/* Table15367 */ + 0x0, /* */ + 0x17f2, /* VFNMADD132SDZrb_Intk */ +/* Table15369 */ + 0x18f4, /* VFNMSUB132PDZ128mbk */ + 0x190c, /* VFNMSUB132PDZrbk */ +/* Table15371 */ + 0x0, /* */ + 0x193e, /* VFNMSUB132SDZrb_Intk */ +/* Table15373 */ + 0x14e8, /* VFMADDSUB213PDZ128mbk */ + 0x1500, /* VFMADDSUB213PDZrbk */ +/* Table15375 */ + 0x16f0, /* VFMSUBADD213PDZ128mbk */ + 0x1708, /* VFMSUBADD213PDZrbk */ +/* Table15377 */ + 0x13bc, /* VFMADD213PDZ128mbk */ + 0x13d4, /* VFMADD213PDZrbk */ +/* Table15379 */ + 0x0, /* */ + 0x1406, /* VFMADD213SDZrb_Intk */ +/* Table15381 */ + 0x15e4, /* VFMSUB213PDZ128mbk */ + 0x15fc, /* VFMSUB213PDZrbk */ +/* Table15383 */ + 0x0, /* */ + 0x162e, /* VFMSUB213SDZrb_Intk */ +/* Table15385 */ + 0x180c, /* VFNMADD213PDZ128mbk */ + 0x1824, /* VFNMADD213PDZrbk */ +/* Table15387 */ + 0x0, /* */ + 0x1856, /* VFNMADD213SDZrb_Intk */ +/* Table15389 */ + 0x1958, /* VFNMSUB213PDZ128mbk */ + 0x1970, /* VFNMSUB213PDZrbk */ +/* Table15391 */ + 0x0, /* */ + 0x19a2, /* VFNMSUB213SDZrb_Intk */ +/* Table15393 */ + 0x2966, /* VPMADD52LUQZ128mbk */ + 0x0, /* */ +/* Table15395 */ + 0x294b, /* VPMADD52HUQZ128mbk */ + 0x0, /* */ +/* Table15397 */ + 0x152c, /* VFMADDSUB231PDZ128mbk */ + 0x1544, /* VFMADDSUB231PDZrbk */ +/* Table15399 */ + 0x1734, /* VFMSUBADD231PDZ128mbk */ + 0x174c, /* VFMSUBADD231PDZrbk */ +/* Table15401 */ + 0x1420, /* VFMADD231PDZ128mbk */ + 0x1438, /* VFMADD231PDZrbk */ +/* Table15403 */ + 0x0, /* */ + 0x146a, /* VFMADD231SDZrb_Intk */ +/* Table15405 */ + 0x1648, /* VFMSUB231PDZ128mbk */ + 0x1660, /* VFMSUB231PDZrbk */ +/* Table15407 */ + 0x0, /* */ + 0x1692, /* VFMSUB231SDZrb_Intk */ +/* Table15409 */ + 0x1870, /* VFNMADD231PDZ128mbk */ + 0x1888, /* VFNMADD231PDZrbk */ +/* Table15411 */ + 0x0, /* */ + 0x18ba, /* VFNMADD231SDZrb_Intk */ +/* Table15413 */ + 0x19bc, /* VFNMSUB231PDZ128mbk */ + 0x19d4, /* VFNMSUB231PDZrbk */ +/* Table15415 */ + 0x0, /* */ + 0x1a06, /* VFNMSUB231SDZrb_Intk */ +/* Table15417 */ + 0x2578, /* VPCONFLICTQZ128rmbk */ + 0x0, /* */ +/* Table15419 */ + 0x0, /* */ + 0x128e, /* VEXP2PDZrbk */ +/* Table15421 */ + 0x0, /* */ + 0x377d, /* VRCP28PDZrbk */ +/* Table15423 */ + 0x0, /* */ + 0x3792, /* VRCP28SDZrbk */ +/* Table15425 */ + 0x0, /* */ + 0x38a1, /* VRSQRT28PDZrbk */ +/* Table15427 */ + 0x0, /* */ + 0x38b6, /* VRSQRT28SDZrbk */ +/* Table15429 */ + 0x35ab, /* VPTESTNMDZ256rmbk */ + 0x0, /* */ +/* Table15431 */ + 0x2726, /* VPERMILPSZ256rmbk */ + 0x0, /* */ +/* Table15433 */ + 0x2fab, /* VPRORVDZ256rmbk */ + 0x0, /* */ +/* Table15435 */ + 0x2f3f, /* VPROLVDZ256rmbk */ + 0x0, /* */ +/* Table15437 */ + 0x276d, /* VPERMPSZ256rmbk */ + 0x0, /* */ +/* Table15439 */ + 0x2050, /* VPABSDZ256rmbk */ + 0x0, /* */ +/* Table15441 */ + 0x356f, /* VPTESTMDZ256rmbk */ + 0x0, /* */ +/* Table15443 */ + 0x20d5, /* VPACKUSDWZ256rmbk */ + 0x0, /* */ +/* Table15445 */ + 0x38f4, /* VSCALEFPSZ256rmbk */ + 0x3903, /* VSCALEFPSZrrbk */ +/* Table15447 */ + 0x2617, /* VPERMDZ256rmbk */ + 0x0, /* */ +/* Table15449 */ + 0x2aa2, /* VPMINSDZ256rmbk */ + 0x0, /* */ +/* Table15451 */ + 0x2b08, /* VPMINUDZ256rmbk */ + 0x0, /* */ +/* Table15453 */ + 0x29d6, /* VPMAXSDZ256rmbk */ + 0x0, /* */ +/* Table15455 */ + 0x2a3c, /* VPMAXUDZ256rmbk */ + 0x0, /* */ +/* Table15457 */ + 0x2de9, /* VPMULLDZ256rmbk */ + 0x0, /* */ +/* Table15459 */ + 0x1ab9, /* VGETEXPPSZ256mbk */ + 0x1ac8, /* VGETEXPPSZrbk */ +/* Table15461 */ + 0x2906, /* VPLZCNTDZ256rmbk */ + 0x0, /* */ +/* Table15463 */ + 0x33f6, /* VPSRLVDZ256rmbk */ + 0x0, /* */ +/* Table15465 */ + 0x3312, /* VPSRAVDZ256rmbk */ + 0x0, /* */ +/* Table15467 */ + 0x3238, /* VPSLLVDZ256rmbk */ + 0x0, /* */ +/* Table15469 */ + 0x3759, /* VRCP14PSZ256mbk */ + 0x0, /* */ +/* Table15471 */ + 0x387d, /* VRSQRT14PSZ256mbk */ + 0x0, /* */ +/* Table15473 */ + 0x25b7, /* VPDPBUSDZ256mbk */ + 0x0, /* */ +/* Table15475 */ + 0x259c, /* VPDPBUSDSZ256mbk */ + 0x0, /* */ +/* Table15477 */ + 0x25ed, /* VPDPWSSDZ256mbk */ + 0x0, /* */ +/* Table15479 */ + 0x25d2, /* VPDPWSSDSZ256mbk */ + 0x0, /* */ +/* Table15481 */ + 0x2e83, /* VPOPCNTDZ256rmbk */ + 0x0, /* */ +/* Table15483 */ + 0x2296, /* VPBLENDMDZ256rmbk */ + 0x0, /* */ +/* Table15485 */ + 0xcc6, /* VBLENDMPSZ256rmbk */ + 0x0, /* */ +/* Table15487 */ + 0x3059, /* VPSHLDVDZ256mbk */ + 0x0, /* */ +/* Table15489 */ + 0x30f5, /* VPSHRDVDZ256mbk */ + 0x0, /* */ +/* Table15491 */ + 0x2644, /* VPERMI2D256rmbk */ + 0x0, /* */ +/* Table15493 */ + 0x267a, /* VPERMI2PS256rmbk */ + 0x0, /* */ +/* Table15495 */ + 0x27c0, /* VPERMT2D256rmbk */ + 0x0, /* */ +/* Table15497 */ + 0x27f6, /* VPERMT2PS256rmbk */ + 0x0, /* */ +/* Table15499 */ + 0x14cf, /* VFMADDSUB132PSZ256mbk */ + 0x14de, /* VFMADDSUB132PSZrbk */ +/* Table15501 */ + 0x16d7, /* VFMSUBADD132PSZ256mbk */ + 0x16e6, /* VFMSUBADD132PSZrbk */ +/* Table15503 */ + 0x1383, /* VFMADD132PSZ256mbk */ + 0x1392, /* VFMADD132PSZrbk */ +/* Table15505 */ + 0x15ab, /* VFMSUB132PSZ256mbk */ + 0x15ba, /* VFMSUB132PSZrbk */ +/* Table15507 */ + 0x17d3, /* VFNMADD132PSZ256mbk */ + 0x17e2, /* VFNMADD132PSZrbk */ +/* Table15509 */ + 0x191f, /* VFNMSUB132PSZ256mbk */ + 0x192e, /* VFNMSUB132PSZrbk */ +/* Table15511 */ + 0x1513, /* VFMADDSUB213PSZ256mbk */ + 0x1522, /* VFMADDSUB213PSZrbk */ +/* Table15513 */ + 0x171b, /* VFMSUBADD213PSZ256mbk */ + 0x172a, /* VFMSUBADD213PSZrbk */ +/* Table15515 */ + 0x13e7, /* VFMADD213PSZ256mbk */ + 0x13f6, /* VFMADD213PSZrbk */ +/* Table15517 */ + 0x160f, /* VFMSUB213PSZ256mbk */ + 0x161e, /* VFMSUB213PSZrbk */ +/* Table15519 */ + 0x1837, /* VFNMADD213PSZ256mbk */ + 0x1846, /* VFNMADD213PSZrbk */ +/* Table15521 */ + 0x1983, /* VFNMSUB213PSZ256mbk */ + 0x1992, /* VFNMSUB213PSZrbk */ +/* Table15523 */ + 0x1557, /* VFMADDSUB231PSZ256mbk */ + 0x1566, /* VFMADDSUB231PSZrbk */ +/* Table15525 */ + 0x175f, /* VFMSUBADD231PSZ256mbk */ + 0x176e, /* VFMSUBADD231PSZrbk */ +/* Table15527 */ + 0x144b, /* VFMADD231PSZ256mbk */ + 0x145a, /* VFMADD231PSZrbk */ +/* Table15529 */ + 0x1673, /* VFMSUB231PSZ256mbk */ + 0x1682, /* VFMSUB231PSZrbk */ +/* Table15531 */ + 0x189b, /* VFNMADD231PSZ256mbk */ + 0x18aa, /* VFNMADD231PSZrbk */ +/* Table15533 */ + 0x19e7, /* VFNMSUB231PSZ256mbk */ + 0x19f6, /* VFNMSUB231PSZrbk */ +/* Table15535 */ + 0x2566, /* VPCONFLICTDZ256rmbk */ + 0x0, /* */ +/* Table15537 */ + 0x35bd, /* VPTESTNMQZ256rmbk */ + 0x0, /* */ +/* Table15539 */ + 0x26e8, /* VPERMILPDZ256rmbk */ + 0x0, /* */ +/* Table15541 */ + 0x2fc6, /* VPRORVQZ256rmbk */ + 0x0, /* */ +/* Table15543 */ + 0x2f5a, /* VPROLVQZ256rmbk */ + 0x0, /* */ +/* Table15545 */ + 0x2750, /* VPERMPDZ256rmbk */ + 0x0, /* */ +/* Table15547 */ + 0x206d, /* VPABSQZ256rmbk */ + 0x0, /* */ +/* Table15549 */ + 0x3581, /* VPTESTMQZ256rmbk */ + 0x0, /* */ +/* Table15551 */ + 0x2d88, /* VPMULDQZ256rmbk */ + 0x0, /* */ +/* Table15553 */ + 0x23db, /* VPCMPEQQZ256rmbk */ + 0x0, /* */ +/* Table15555 */ + 0x38d6, /* VSCALEFPDZ256rmbk */ + 0x38e5, /* VSCALEFPDZrrbk */ +/* Table15557 */ + 0x278a, /* VPERMQZ256rmbk */ + 0x0, /* */ +/* Table15559 */ + 0x242b, /* VPCMPGTQZ256rmbk */ + 0x0, /* */ +/* Table15561 */ + 0x2abf, /* VPMINSQZ256rmbk */ + 0x0, /* */ +/* Table15563 */ + 0x2b25, /* VPMINUQZ256rmbk */ + 0x0, /* */ +/* Table15565 */ + 0x29f3, /* VPMAXSQZ256rmbk */ + 0x0, /* */ +/* Table15567 */ + 0x2a59, /* VPMAXUQZ256rmbk */ + 0x0, /* */ +/* Table15569 */ + 0x2e06, /* VPMULLQZ256rmbk */ + 0x0, /* */ +/* Table15571 */ + 0x1a9b, /* VGETEXPPDZ256mbk */ + 0x1aaa, /* VGETEXPPDZrbk */ +/* Table15573 */ + 0x2921, /* VPLZCNTQZ256rmbk */ + 0x0, /* */ +/* Table15575 */ + 0x3415, /* VPSRLVQZ256rmbk */ + 0x0, /* */ +/* Table15577 */ + 0x332f, /* VPSRAVQZ256rmbk */ + 0x0, /* */ +/* Table15579 */ + 0x3257, /* VPSLLVQZ256rmbk */ + 0x0, /* */ +/* Table15581 */ + 0x373e, /* VRCP14PDZ256mbk */ + 0x0, /* */ +/* Table15583 */ + 0x3862, /* VRSQRT14PDZ256mbk */ + 0x0, /* */ +/* Table15585 */ + 0x2e9e, /* VPOPCNTQZ256rmbk */ + 0x0, /* */ +/* Table15587 */ + 0x22b1, /* VPBLENDMQZ256rmbk */ + 0x0, /* */ +/* Table15589 */ + 0xcab, /* VBLENDMPDZ256rmbk */ + 0x0, /* */ +/* Table15591 */ + 0x3074, /* VPSHLDVQZ256mbk */ + 0x0, /* */ +/* Table15593 */ + 0x3110, /* VPSHRDVQZ256mbk */ + 0x0, /* */ +/* Table15595 */ + 0x2695, /* VPERMI2Q256rmbk */ + 0x0, /* */ +/* Table15597 */ + 0x265f, /* VPERMI2PD256rmbk */ + 0x0, /* */ +/* Table15599 */ + 0x2811, /* VPERMT2Q256rmbk */ + 0x0, /* */ +/* Table15601 */ + 0x27db, /* VPERMT2PD256rmbk */ + 0x0, /* */ +/* Table15603 */ + 0x2e37, /* VPMULTISHIFTQBZ256rmbk */ + 0x0, /* */ +/* Table15605 */ + 0x14ad, /* VFMADDSUB132PDZ256mbk */ + 0x14bc, /* VFMADDSUB132PDZrbk */ +/* Table15607 */ + 0x16b5, /* VFMSUBADD132PDZ256mbk */ + 0x16c4, /* VFMSUBADD132PDZrbk */ +/* Table15609 */ + 0x1361, /* VFMADD132PDZ256mbk */ + 0x1370, /* VFMADD132PDZrbk */ +/* Table15611 */ + 0x1589, /* VFMSUB132PDZ256mbk */ + 0x1598, /* VFMSUB132PDZrbk */ +/* Table15613 */ + 0x17b1, /* VFNMADD132PDZ256mbk */ + 0x17c0, /* VFNMADD132PDZrbk */ +/* Table15615 */ + 0x18fd, /* VFNMSUB132PDZ256mbk */ + 0x190c, /* VFNMSUB132PDZrbk */ +/* Table15617 */ + 0x14f1, /* VFMADDSUB213PDZ256mbk */ + 0x1500, /* VFMADDSUB213PDZrbk */ +/* Table15619 */ + 0x16f9, /* VFMSUBADD213PDZ256mbk */ + 0x1708, /* VFMSUBADD213PDZrbk */ +/* Table15621 */ + 0x13c5, /* VFMADD213PDZ256mbk */ + 0x13d4, /* VFMADD213PDZrbk */ +/* Table15623 */ + 0x15ed, /* VFMSUB213PDZ256mbk */ + 0x15fc, /* VFMSUB213PDZrbk */ +/* Table15625 */ + 0x1815, /* VFNMADD213PDZ256mbk */ + 0x1824, /* VFNMADD213PDZrbk */ +/* Table15627 */ + 0x1961, /* VFNMSUB213PDZ256mbk */ + 0x1970, /* VFNMSUB213PDZrbk */ +/* Table15629 */ + 0x296f, /* VPMADD52LUQZ256mbk */ + 0x0, /* */ +/* Table15631 */ + 0x2954, /* VPMADD52HUQZ256mbk */ + 0x0, /* */ +/* Table15633 */ + 0x1535, /* VFMADDSUB231PDZ256mbk */ + 0x1544, /* VFMADDSUB231PDZrbk */ +/* Table15635 */ + 0x173d, /* VFMSUBADD231PDZ256mbk */ + 0x174c, /* VFMSUBADD231PDZrbk */ +/* Table15637 */ + 0x1429, /* VFMADD231PDZ256mbk */ + 0x1438, /* VFMADD231PDZrbk */ +/* Table15639 */ + 0x1651, /* VFMSUB231PDZ256mbk */ + 0x1660, /* VFMSUB231PDZrbk */ +/* Table15641 */ + 0x1879, /* VFNMADD231PDZ256mbk */ + 0x1888, /* VFNMADD231PDZrbk */ +/* Table15643 */ + 0x19c5, /* VFNMSUB231PDZ256mbk */ + 0x19d4, /* VFNMSUB231PDZrbk */ +/* Table15645 */ + 0x2581, /* VPCONFLICTQZ256rmbk */ + 0x0, /* */ +/* Table15647 */ + 0x35b1, /* VPTESTNMDZrmbk */ + 0x0, /* */ +/* Table15649 */ + 0x2738, /* VPERMILPSZrmbk */ + 0x0, /* */ +/* Table15651 */ + 0x2fb4, /* VPRORVDZrmbk */ + 0x0, /* */ +/* Table15653 */ + 0x2f48, /* VPROLVDZrmbk */ + 0x0, /* */ +/* Table15655 */ + 0x2776, /* VPERMPSZrmbk */ + 0x0, /* */ +/* Table15657 */ + 0x2059, /* VPABSDZrmbk */ + 0x0, /* */ +/* Table15659 */ + 0x3575, /* VPTESTMDZrmbk */ + 0x0, /* */ +/* Table15661 */ + 0x20de, /* VPACKUSDWZrmbk */ + 0x0, /* */ +/* Table15663 */ + 0x38fd, /* VSCALEFPSZrmbk */ + 0x3903, /* VSCALEFPSZrrbk */ +/* Table15665 */ + 0x2620, /* VPERMDZrmbk */ + 0x0, /* */ +/* Table15667 */ + 0x2aab, /* VPMINSDZrmbk */ + 0x0, /* */ +/* Table15669 */ + 0x2b11, /* VPMINUDZrmbk */ + 0x0, /* */ +/* Table15671 */ + 0x29df, /* VPMAXSDZrmbk */ + 0x0, /* */ +/* Table15673 */ + 0x2a45, /* VPMAXUDZrmbk */ + 0x0, /* */ +/* Table15675 */ + 0x2df2, /* VPMULLDZrmbk */ + 0x0, /* */ +/* Table15677 */ + 0x1ac2, /* VGETEXPPSZmbk */ + 0x1ac8, /* VGETEXPPSZrbk */ +/* Table15679 */ + 0x290f, /* VPLZCNTDZrmbk */ + 0x0, /* */ +/* Table15681 */ + 0x33ff, /* VPSRLVDZrmbk */ + 0x0, /* */ +/* Table15683 */ + 0x331b, /* VPSRAVDZrmbk */ + 0x0, /* */ +/* Table15685 */ + 0x3241, /* VPSLLVDZrmbk */ + 0x0, /* */ +/* Table15687 */ + 0x3762, /* VRCP14PSZmbk */ + 0x0, /* */ +/* Table15689 */ + 0x3886, /* VRSQRT14PSZmbk */ + 0x0, /* */ +/* Table15691 */ + 0x25c0, /* VPDPBUSDZmbk */ + 0x0, /* */ +/* Table15693 */ + 0x25a5, /* VPDPBUSDSZmbk */ + 0x0, /* */ +/* Table15695 */ + 0x25f6, /* VPDPWSSDZmbk */ + 0x0, /* */ +/* Table15697 */ + 0x25db, /* VPDPWSSDSZmbk */ + 0x0, /* */ +/* Table15699 */ + 0x2e8c, /* VPOPCNTDZrmbk */ + 0x0, /* */ +/* Table15701 */ + 0x229f, /* VPBLENDMDZrmbk */ + 0x0, /* */ +/* Table15703 */ + 0xccf, /* VBLENDMPSZrmbk */ + 0x0, /* */ +/* Table15705 */ + 0x3062, /* VPSHLDVDZmbk */ + 0x0, /* */ +/* Table15707 */ + 0x30fe, /* VPSHRDVDZmbk */ + 0x0, /* */ +/* Table15709 */ + 0x264d, /* VPERMI2Drmbk */ + 0x0, /* */ +/* Table15711 */ + 0x2683, /* VPERMI2PSrmbk */ + 0x0, /* */ +/* Table15713 */ + 0x27c9, /* VPERMT2Drmbk */ + 0x0, /* */ +/* Table15715 */ + 0x27ff, /* VPERMT2PSrmbk */ + 0x0, /* */ +/* Table15717 */ + 0x14d8, /* VFMADDSUB132PSZmbk */ + 0x14de, /* VFMADDSUB132PSZrbk */ +/* Table15719 */ + 0x16e0, /* VFMSUBADD132PSZmbk */ + 0x16e6, /* VFMSUBADD132PSZrbk */ +/* Table15721 */ + 0x138c, /* VFMADD132PSZmbk */ + 0x1392, /* VFMADD132PSZrbk */ +/* Table15723 */ + 0x15b4, /* VFMSUB132PSZmbk */ + 0x15ba, /* VFMSUB132PSZrbk */ +/* Table15725 */ + 0x17dc, /* VFNMADD132PSZmbk */ + 0x17e2, /* VFNMADD132PSZrbk */ +/* Table15727 */ + 0x1928, /* VFNMSUB132PSZmbk */ + 0x192e, /* VFNMSUB132PSZrbk */ +/* Table15729 */ + 0x151c, /* VFMADDSUB213PSZmbk */ + 0x1522, /* VFMADDSUB213PSZrbk */ +/* Table15731 */ + 0x1724, /* VFMSUBADD213PSZmbk */ + 0x172a, /* VFMSUBADD213PSZrbk */ +/* Table15733 */ + 0x13f0, /* VFMADD213PSZmbk */ + 0x13f6, /* VFMADD213PSZrbk */ +/* Table15735 */ + 0x1618, /* VFMSUB213PSZmbk */ + 0x161e, /* VFMSUB213PSZrbk */ +/* Table15737 */ + 0x1840, /* VFNMADD213PSZmbk */ + 0x1846, /* VFNMADD213PSZrbk */ +/* Table15739 */ + 0x198c, /* VFNMSUB213PSZmbk */ + 0x1992, /* VFNMSUB213PSZrbk */ +/* Table15741 */ + 0x1560, /* VFMADDSUB231PSZmbk */ + 0x1566, /* VFMADDSUB231PSZrbk */ +/* Table15743 */ + 0x1768, /* VFMSUBADD231PSZmbk */ + 0x176e, /* VFMSUBADD231PSZrbk */ +/* Table15745 */ + 0x1454, /* VFMADD231PSZmbk */ + 0x145a, /* VFMADD231PSZrbk */ +/* Table15747 */ + 0x167c, /* VFMSUB231PSZmbk */ + 0x1682, /* VFMSUB231PSZrbk */ +/* Table15749 */ + 0x18a4, /* VFNMADD231PSZmbk */ + 0x18aa, /* VFNMADD231PSZrbk */ +/* Table15751 */ + 0x19f0, /* VFNMSUB231PSZmbk */ + 0x19f6, /* VFNMSUB231PSZrbk */ +/* Table15753 */ + 0x256f, /* VPCONFLICTDZrmbk */ + 0x0, /* */ +/* Table15755 */ + 0x1294, /* VEXP2PSZmbk */ + 0x129a, /* VEXP2PSZrbk */ +/* Table15757 */ + 0x3783, /* VRCP28PSZmbk */ + 0x3789, /* VRCP28PSZrbk */ +/* Table15759 */ + 0x38a7, /* VRSQRT28PSZmbk */ + 0x38ad, /* VRSQRT28PSZrbk */ +/* Table15761 */ + 0x35c3, /* VPTESTNMQZrmbk */ + 0x0, /* */ +/* Table15763 */ + 0x26fa, /* VPERMILPDZrmbk */ + 0x0, /* */ +/* Table15765 */ + 0x2fcf, /* VPRORVQZrmbk */ + 0x0, /* */ +/* Table15767 */ + 0x2f63, /* VPROLVQZrmbk */ + 0x0, /* */ +/* Table15769 */ + 0x2762, /* VPERMPDZrmbk */ + 0x0, /* */ +/* Table15771 */ + 0x2076, /* VPABSQZrmbk */ + 0x0, /* */ +/* Table15773 */ + 0x3587, /* VPTESTMQZrmbk */ + 0x0, /* */ +/* Table15775 */ + 0x2d91, /* VPMULDQZrmbk */ + 0x0, /* */ +/* Table15777 */ + 0x23e1, /* VPCMPEQQZrmbk */ + 0x0, /* */ +/* Table15779 */ + 0x38df, /* VSCALEFPDZrmbk */ + 0x38e5, /* VSCALEFPDZrrbk */ +/* Table15781 */ + 0x279c, /* VPERMQZrmbk */ + 0x0, /* */ +/* Table15783 */ + 0x2431, /* VPCMPGTQZrmbk */ + 0x0, /* */ +/* Table15785 */ + 0x2ac8, /* VPMINSQZrmbk */ + 0x0, /* */ +/* Table15787 */ + 0x2b2e, /* VPMINUQZrmbk */ + 0x0, /* */ +/* Table15789 */ + 0x29fc, /* VPMAXSQZrmbk */ + 0x0, /* */ +/* Table15791 */ + 0x2a62, /* VPMAXUQZrmbk */ + 0x0, /* */ +/* Table15793 */ + 0x2e0f, /* VPMULLQZrmbk */ + 0x0, /* */ +/* Table15795 */ + 0x1aa4, /* VGETEXPPDZmbk */ + 0x1aaa, /* VGETEXPPDZrbk */ +/* Table15797 */ + 0x292a, /* VPLZCNTQZrmbk */ + 0x0, /* */ +/* Table15799 */ + 0x341e, /* VPSRLVQZrmbk */ + 0x0, /* */ +/* Table15801 */ + 0x3338, /* VPSRAVQZrmbk */ + 0x0, /* */ +/* Table15803 */ + 0x3260, /* VPSLLVQZrmbk */ + 0x0, /* */ +/* Table15805 */ + 0x3747, /* VRCP14PDZmbk */ + 0x0, /* */ +/* Table15807 */ + 0x386b, /* VRSQRT14PDZmbk */ + 0x0, /* */ +/* Table15809 */ + 0x2ea7, /* VPOPCNTQZrmbk */ + 0x0, /* */ +/* Table15811 */ + 0x22ba, /* VPBLENDMQZrmbk */ + 0x0, /* */ +/* Table15813 */ + 0xcb4, /* VBLENDMPDZrmbk */ + 0x0, /* */ +/* Table15815 */ + 0x307d, /* VPSHLDVQZmbk */ + 0x0, /* */ +/* Table15817 */ + 0x3119, /* VPSHRDVQZmbk */ + 0x0, /* */ +/* Table15819 */ + 0x269e, /* VPERMI2Qrmbk */ + 0x0, /* */ +/* Table15821 */ + 0x2668, /* VPERMI2PDrmbk */ + 0x0, /* */ +/* Table15823 */ + 0x281a, /* VPERMT2Qrmbk */ + 0x0, /* */ +/* Table15825 */ + 0x27e4, /* VPERMT2PDrmbk */ + 0x0, /* */ +/* Table15827 */ + 0x2e40, /* VPMULTISHIFTQBZrmbk */ + 0x0, /* */ +/* Table15829 */ + 0x14b6, /* VFMADDSUB132PDZmbk */ + 0x14bc, /* VFMADDSUB132PDZrbk */ +/* Table15831 */ + 0x16be, /* VFMSUBADD132PDZmbk */ + 0x16c4, /* VFMSUBADD132PDZrbk */ +/* Table15833 */ + 0x136a, /* VFMADD132PDZmbk */ + 0x1370, /* VFMADD132PDZrbk */ +/* Table15835 */ + 0x1592, /* VFMSUB132PDZmbk */ + 0x1598, /* VFMSUB132PDZrbk */ +/* Table15837 */ + 0x17ba, /* VFNMADD132PDZmbk */ + 0x17c0, /* VFNMADD132PDZrbk */ +/* Table15839 */ + 0x1906, /* VFNMSUB132PDZmbk */ + 0x190c, /* VFNMSUB132PDZrbk */ +/* Table15841 */ + 0x14fa, /* VFMADDSUB213PDZmbk */ + 0x1500, /* VFMADDSUB213PDZrbk */ +/* Table15843 */ + 0x1702, /* VFMSUBADD213PDZmbk */ + 0x1708, /* VFMSUBADD213PDZrbk */ +/* Table15845 */ + 0x13ce, /* VFMADD213PDZmbk */ + 0x13d4, /* VFMADD213PDZrbk */ +/* Table15847 */ + 0x15f6, /* VFMSUB213PDZmbk */ + 0x15fc, /* VFMSUB213PDZrbk */ +/* Table15849 */ + 0x181e, /* VFNMADD213PDZmbk */ + 0x1824, /* VFNMADD213PDZrbk */ +/* Table15851 */ + 0x196a, /* VFNMSUB213PDZmbk */ + 0x1970, /* VFNMSUB213PDZrbk */ +/* Table15853 */ + 0x2978, /* VPMADD52LUQZmbk */ + 0x0, /* */ +/* Table15855 */ + 0x295d, /* VPMADD52HUQZmbk */ + 0x0, /* */ +/* Table15857 */ + 0x153e, /* VFMADDSUB231PDZmbk */ + 0x1544, /* VFMADDSUB231PDZrbk */ +/* Table15859 */ + 0x1746, /* VFMSUBADD231PDZmbk */ + 0x174c, /* VFMSUBADD231PDZrbk */ +/* Table15861 */ + 0x1432, /* VFMADD231PDZmbk */ + 0x1438, /* VFMADD231PDZrbk */ +/* Table15863 */ + 0x165a, /* VFMSUB231PDZmbk */ + 0x1660, /* VFMSUB231PDZrbk */ +/* Table15865 */ + 0x1882, /* VFNMADD231PDZmbk */ + 0x1888, /* VFNMADD231PDZrbk */ +/* Table15867 */ + 0x19ce, /* VFNMSUB231PDZmbk */ + 0x19d4, /* VFNMSUB231PDZrbk */ +/* Table15869 */ + 0x258a, /* VPCONFLICTQZrmbk */ + 0x0, /* */ +/* Table15871 */ + 0x1288, /* VEXP2PDZmbk */ + 0x128e, /* VEXP2PDZrbk */ +/* Table15873 */ + 0x3777, /* VRCP28PDZmbk */ + 0x377d, /* VRCP28PDZrbk */ +/* Table15875 */ + 0x389b, /* VRSQRT28PDZmbk */ + 0x38a1, /* VRSQRT28PDZrbk */ +/* Table15877 */ + 0x2715, /* VPERMILPSZ128rmbkz */ + 0x0, /* */ +/* Table15879 */ + 0x0, /* */ + 0xef9, /* VCVTPH2PSZrrbkz */ +/* Table15881 */ + 0x2fa3, /* VPRORVDZ128rmbkz */ + 0x0, /* */ +/* Table15883 */ + 0x2f37, /* VPROLVDZ128rmbkz */ + 0x0, /* */ +/* Table15885 */ + 0x2048, /* VPABSDZ128rmbkz */ + 0x0, /* */ +/* Table15887 */ + 0x20cd, /* VPACKUSDWZ128rmbkz */ + 0x0, /* */ +/* Table15889 */ + 0x38ec, /* VSCALEFPSZ128rmbkz */ + 0x3904, /* VSCALEFPSZrrbkz */ +/* Table15891 */ + 0x0, /* */ + 0x3916, /* VSCALEFSSZrrb_Intkz */ +/* Table15893 */ + 0x2a9a, /* VPMINSDZ128rmbkz */ + 0x0, /* */ +/* Table15895 */ + 0x2b00, /* VPMINUDZ128rmbkz */ + 0x0, /* */ +/* Table15897 */ + 0x29ce, /* VPMAXSDZ128rmbkz */ + 0x0, /* */ +/* Table15899 */ + 0x2a34, /* VPMAXUDZ128rmbkz */ + 0x0, /* */ +/* Table15901 */ + 0x2de1, /* VPMULLDZ128rmbkz */ + 0x0, /* */ +/* Table15903 */ + 0x1ab1, /* VGETEXPPSZ128mbkz */ + 0x1ac9, /* VGETEXPPSZrbkz */ +/* Table15905 */ + 0x0, /* */ + 0x1adb, /* VGETEXPSSZrbkz */ +/* Table15907 */ + 0x28fe, /* VPLZCNTDZ128rmbkz */ + 0x0, /* */ +/* Table15909 */ + 0x33ee, /* VPSRLVDZ128rmbkz */ + 0x0, /* */ +/* Table15911 */ + 0x330a, /* VPSRAVDZ128rmbkz */ + 0x0, /* */ +/* Table15913 */ + 0x3230, /* VPSLLVDZ128rmbkz */ + 0x0, /* */ +/* Table15915 */ + 0x3751, /* VRCP14PSZ128mbkz */ + 0x0, /* */ +/* Table15917 */ + 0x3875, /* VRSQRT14PSZ128mbkz */ + 0x0, /* */ +/* Table15919 */ + 0x25af, /* VPDPBUSDZ128mbkz */ + 0x0, /* */ +/* Table15921 */ + 0x2594, /* VPDPBUSDSZ128mbkz */ + 0x0, /* */ +/* Table15923 */ + 0x25e5, /* VPDPWSSDZ128mbkz */ + 0x0, /* */ +/* Table15925 */ + 0x25ca, /* VPDPWSSDSZ128mbkz */ + 0x0, /* */ +/* Table15927 */ + 0x2e7b, /* VPOPCNTDZ128rmbkz */ + 0x0, /* */ +/* Table15929 */ + 0x228e, /* VPBLENDMDZ128rmbkz */ + 0x0, /* */ +/* Table15931 */ + 0xcbe, /* VBLENDMPSZ128rmbkz */ + 0x0, /* */ +/* Table15933 */ + 0x3051, /* VPSHLDVDZ128mbkz */ + 0x0, /* */ +/* Table15935 */ + 0x30ed, /* VPSHRDVDZ128mbkz */ + 0x0, /* */ +/* Table15937 */ + 0x263c, /* VPERMI2D128rmbkz */ + 0x0, /* */ +/* Table15939 */ + 0x2672, /* VPERMI2PS128rmbkz */ + 0x0, /* */ +/* Table15941 */ + 0x27b8, /* VPERMT2D128rmbkz */ + 0x0, /* */ +/* Table15943 */ + 0x27ee, /* VPERMT2PS128rmbkz */ + 0x0, /* */ +/* Table15945 */ + 0x14c7, /* VFMADDSUB132PSZ128mbkz */ + 0x14df, /* VFMADDSUB132PSZrbkz */ +/* Table15947 */ + 0x16cf, /* VFMSUBADD132PSZ128mbkz */ + 0x16e7, /* VFMSUBADD132PSZrbkz */ +/* Table15949 */ + 0x137b, /* VFMADD132PSZ128mbkz */ + 0x1393, /* VFMADD132PSZrbkz */ +/* Table15951 */ + 0x0, /* */ + 0x13b3, /* VFMADD132SSZrb_Intkz */ +/* Table15953 */ + 0x15a3, /* VFMSUB132PSZ128mbkz */ + 0x15bb, /* VFMSUB132PSZrbkz */ +/* Table15955 */ + 0x0, /* */ + 0x15db, /* VFMSUB132SSZrb_Intkz */ +/* Table15957 */ + 0x17cb, /* VFNMADD132PSZ128mbkz */ + 0x17e3, /* VFNMADD132PSZrbkz */ +/* Table15959 */ + 0x0, /* */ + 0x1803, /* VFNMADD132SSZrb_Intkz */ +/* Table15961 */ + 0x1917, /* VFNMSUB132PSZ128mbkz */ + 0x192f, /* VFNMSUB132PSZrbkz */ +/* Table15963 */ + 0x0, /* */ + 0x194f, /* VFNMSUB132SSZrb_Intkz */ +/* Table15965 */ + 0x150b, /* VFMADDSUB213PSZ128mbkz */ + 0x1523, /* VFMADDSUB213PSZrbkz */ +/* Table15967 */ + 0x1713, /* VFMSUBADD213PSZ128mbkz */ + 0x172b, /* VFMSUBADD213PSZrbkz */ +/* Table15969 */ + 0x13df, /* VFMADD213PSZ128mbkz */ + 0x13f7, /* VFMADD213PSZrbkz */ +/* Table15971 */ + 0x0, /* */ + 0x1417, /* VFMADD213SSZrb_Intkz */ +/* Table15973 */ + 0x1607, /* VFMSUB213PSZ128mbkz */ + 0x161f, /* VFMSUB213PSZrbkz */ +/* Table15975 */ + 0x0, /* */ + 0x163f, /* VFMSUB213SSZrb_Intkz */ +/* Table15977 */ + 0x182f, /* VFNMADD213PSZ128mbkz */ + 0x1847, /* VFNMADD213PSZrbkz */ +/* Table15979 */ + 0x0, /* */ + 0x1867, /* VFNMADD213SSZrb_Intkz */ +/* Table15981 */ + 0x197b, /* VFNMSUB213PSZ128mbkz */ + 0x1993, /* VFNMSUB213PSZrbkz */ +/* Table15983 */ + 0x0, /* */ + 0x19b3, /* VFNMSUB213SSZrb_Intkz */ +/* Table15985 */ + 0x154f, /* VFMADDSUB231PSZ128mbkz */ + 0x1567, /* VFMADDSUB231PSZrbkz */ +/* Table15987 */ + 0x1757, /* VFMSUBADD231PSZ128mbkz */ + 0x176f, /* VFMSUBADD231PSZrbkz */ +/* Table15989 */ + 0x1443, /* VFMADD231PSZ128mbkz */ + 0x145b, /* VFMADD231PSZrbkz */ +/* Table15991 */ + 0x0, /* */ + 0x147b, /* VFMADD231SSZrb_Intkz */ +/* Table15993 */ + 0x166b, /* VFMSUB231PSZ128mbkz */ + 0x1683, /* VFMSUB231PSZrbkz */ +/* Table15995 */ + 0x0, /* */ + 0x16a3, /* VFMSUB231SSZrb_Intkz */ +/* Table15997 */ + 0x1893, /* VFNMADD231PSZ128mbkz */ + 0x18ab, /* VFNMADD231PSZrbkz */ +/* Table15999 */ + 0x0, /* */ + 0x18cb, /* VFNMADD231SSZrb_Intkz */ +/* Table16001 */ + 0x19df, /* VFNMSUB231PSZ128mbkz */ + 0x19f7, /* VFNMSUB231PSZrbkz */ +/* Table16003 */ + 0x0, /* */ + 0x1a17, /* VFNMSUB231SSZrb_Intkz */ +/* Table16005 */ + 0x255e, /* VPCONFLICTDZ128rmbkz */ + 0x0, /* */ +/* Table16007 */ + 0x0, /* */ + 0x129b, /* VEXP2PSZrbkz */ +/* Table16009 */ + 0x0, /* */ + 0x378a, /* VRCP28PSZrbkz */ +/* Table16011 */ + 0x0, /* */ + 0x379c, /* VRCP28SSZrbkz */ +/* Table16013 */ + 0x0, /* */ + 0x38ae, /* VRSQRT28PSZrbkz */ +/* Table16015 */ + 0x0, /* */ + 0x38c0, /* VRSQRT28SSZrbkz */ +/* Table16017 */ + 0x26d7, /* VPERMILPDZ128rmbkz */ + 0x0, /* */ +/* Table16019 */ + 0x2fbe, /* VPRORVQZ128rmbkz */ + 0x0, /* */ +/* Table16021 */ + 0x2f52, /* VPROLVQZ128rmbkz */ + 0x0, /* */ +/* Table16023 */ + 0x2065, /* VPABSQZ128rmbkz */ + 0x0, /* */ +/* Table16025 */ + 0x2d80, /* VPMULDQZ128rmbkz */ + 0x0, /* */ +/* Table16027 */ + 0x38ce, /* VSCALEFPDZ128rmbkz */ + 0x38e6, /* VSCALEFPDZrrbkz */ +/* Table16029 */ + 0x0, /* */ + 0x390d, /* VSCALEFSDZrrb_Intkz */ +/* Table16031 */ + 0x2ab7, /* VPMINSQZ128rmbkz */ + 0x0, /* */ +/* Table16033 */ + 0x2b1d, /* VPMINUQZ128rmbkz */ + 0x0, /* */ +/* Table16035 */ + 0x29eb, /* VPMAXSQZ128rmbkz */ + 0x0, /* */ +/* Table16037 */ + 0x2a51, /* VPMAXUQZ128rmbkz */ + 0x0, /* */ +/* Table16039 */ + 0x2dfe, /* VPMULLQZ128rmbkz */ + 0x0, /* */ +/* Table16041 */ + 0x1a93, /* VGETEXPPDZ128mbkz */ + 0x1aab, /* VGETEXPPDZrbkz */ +/* Table16043 */ + 0x0, /* */ + 0x1ad2, /* VGETEXPSDZrbkz */ +/* Table16045 */ + 0x2919, /* VPLZCNTQZ128rmbkz */ + 0x0, /* */ +/* Table16047 */ + 0x340d, /* VPSRLVQZ128rmbkz */ + 0x0, /* */ +/* Table16049 */ + 0x3327, /* VPSRAVQZ128rmbkz */ + 0x0, /* */ +/* Table16051 */ + 0x324f, /* VPSLLVQZ128rmbkz */ + 0x0, /* */ +/* Table16053 */ + 0x3736, /* VRCP14PDZ128mbkz */ + 0x0, /* */ +/* Table16055 */ + 0x385a, /* VRSQRT14PDZ128mbkz */ + 0x0, /* */ +/* Table16057 */ + 0x2e96, /* VPOPCNTQZ128rmbkz */ + 0x0, /* */ +/* Table16059 */ + 0x22a9, /* VPBLENDMQZ128rmbkz */ + 0x0, /* */ +/* Table16061 */ + 0xca3, /* VBLENDMPDZ128rmbkz */ + 0x0, /* */ +/* Table16063 */ + 0x306c, /* VPSHLDVQZ128mbkz */ + 0x0, /* */ +/* Table16065 */ + 0x3108, /* VPSHRDVQZ128mbkz */ + 0x0, /* */ +/* Table16067 */ + 0x268d, /* VPERMI2Q128rmbkz */ + 0x0, /* */ +/* Table16069 */ + 0x2657, /* VPERMI2PD128rmbkz */ + 0x0, /* */ +/* Table16071 */ + 0x2809, /* VPERMT2Q128rmbkz */ + 0x0, /* */ +/* Table16073 */ + 0x27d3, /* VPERMT2PD128rmbkz */ + 0x0, /* */ +/* Table16075 */ + 0x2e2f, /* VPMULTISHIFTQBZ128rmbkz */ + 0x0, /* */ +/* Table16077 */ + 0x14a5, /* VFMADDSUB132PDZ128mbkz */ + 0x14bd, /* VFMADDSUB132PDZrbkz */ +/* Table16079 */ + 0x16ad, /* VFMSUBADD132PDZ128mbkz */ + 0x16c5, /* VFMSUBADD132PDZrbkz */ +/* Table16081 */ + 0x1359, /* VFMADD132PDZ128mbkz */ + 0x1371, /* VFMADD132PDZrbkz */ +/* Table16083 */ + 0x0, /* */ + 0x13a3, /* VFMADD132SDZrb_Intkz */ +/* Table16085 */ + 0x1581, /* VFMSUB132PDZ128mbkz */ + 0x1599, /* VFMSUB132PDZrbkz */ +/* Table16087 */ + 0x0, /* */ + 0x15cb, /* VFMSUB132SDZrb_Intkz */ +/* Table16089 */ + 0x17a9, /* VFNMADD132PDZ128mbkz */ + 0x17c1, /* VFNMADD132PDZrbkz */ +/* Table16091 */ + 0x0, /* */ + 0x17f3, /* VFNMADD132SDZrb_Intkz */ +/* Table16093 */ + 0x18f5, /* VFNMSUB132PDZ128mbkz */ + 0x190d, /* VFNMSUB132PDZrbkz */ +/* Table16095 */ + 0x0, /* */ + 0x193f, /* VFNMSUB132SDZrb_Intkz */ +/* Table16097 */ + 0x14e9, /* VFMADDSUB213PDZ128mbkz */ + 0x1501, /* VFMADDSUB213PDZrbkz */ +/* Table16099 */ + 0x16f1, /* VFMSUBADD213PDZ128mbkz */ + 0x1709, /* VFMSUBADD213PDZrbkz */ +/* Table16101 */ + 0x13bd, /* VFMADD213PDZ128mbkz */ + 0x13d5, /* VFMADD213PDZrbkz */ +/* Table16103 */ + 0x0, /* */ + 0x1407, /* VFMADD213SDZrb_Intkz */ +/* Table16105 */ + 0x15e5, /* VFMSUB213PDZ128mbkz */ + 0x15fd, /* VFMSUB213PDZrbkz */ +/* Table16107 */ + 0x0, /* */ + 0x162f, /* VFMSUB213SDZrb_Intkz */ +/* Table16109 */ + 0x180d, /* VFNMADD213PDZ128mbkz */ + 0x1825, /* VFNMADD213PDZrbkz */ +/* Table16111 */ + 0x0, /* */ + 0x1857, /* VFNMADD213SDZrb_Intkz */ +/* Table16113 */ + 0x1959, /* VFNMSUB213PDZ128mbkz */ + 0x1971, /* VFNMSUB213PDZrbkz */ +/* Table16115 */ + 0x0, /* */ + 0x19a3, /* VFNMSUB213SDZrb_Intkz */ +/* Table16117 */ + 0x2967, /* VPMADD52LUQZ128mbkz */ + 0x0, /* */ +/* Table16119 */ + 0x294c, /* VPMADD52HUQZ128mbkz */ + 0x0, /* */ +/* Table16121 */ + 0x152d, /* VFMADDSUB231PDZ128mbkz */ + 0x1545, /* VFMADDSUB231PDZrbkz */ +/* Table16123 */ + 0x1735, /* VFMSUBADD231PDZ128mbkz */ + 0x174d, /* VFMSUBADD231PDZrbkz */ +/* Table16125 */ + 0x1421, /* VFMADD231PDZ128mbkz */ + 0x1439, /* VFMADD231PDZrbkz */ +/* Table16127 */ + 0x0, /* */ + 0x146b, /* VFMADD231SDZrb_Intkz */ +/* Table16129 */ + 0x1649, /* VFMSUB231PDZ128mbkz */ + 0x1661, /* VFMSUB231PDZrbkz */ +/* Table16131 */ + 0x0, /* */ + 0x1693, /* VFMSUB231SDZrb_Intkz */ +/* Table16133 */ + 0x1871, /* VFNMADD231PDZ128mbkz */ + 0x1889, /* VFNMADD231PDZrbkz */ +/* Table16135 */ + 0x0, /* */ + 0x18bb, /* VFNMADD231SDZrb_Intkz */ +/* Table16137 */ + 0x19bd, /* VFNMSUB231PDZ128mbkz */ + 0x19d5, /* VFNMSUB231PDZrbkz */ +/* Table16139 */ + 0x0, /* */ + 0x1a07, /* VFNMSUB231SDZrb_Intkz */ +/* Table16141 */ + 0x2579, /* VPCONFLICTQZ128rmbkz */ + 0x0, /* */ +/* Table16143 */ + 0x0, /* */ + 0x128f, /* VEXP2PDZrbkz */ +/* Table16145 */ + 0x0, /* */ + 0x377e, /* VRCP28PDZrbkz */ +/* Table16147 */ + 0x0, /* */ + 0x3793, /* VRCP28SDZrbkz */ +/* Table16149 */ + 0x0, /* */ + 0x38a2, /* VRSQRT28PDZrbkz */ +/* Table16151 */ + 0x0, /* */ + 0x38b7, /* VRSQRT28SDZrbkz */ +/* Table16153 */ + 0x2727, /* VPERMILPSZ256rmbkz */ + 0x0, /* */ +/* Table16155 */ + 0x2fac, /* VPRORVDZ256rmbkz */ + 0x0, /* */ +/* Table16157 */ + 0x2f40, /* VPROLVDZ256rmbkz */ + 0x0, /* */ +/* Table16159 */ + 0x276e, /* VPERMPSZ256rmbkz */ + 0x0, /* */ +/* Table16161 */ + 0x2051, /* VPABSDZ256rmbkz */ + 0x0, /* */ +/* Table16163 */ + 0x20d6, /* VPACKUSDWZ256rmbkz */ + 0x0, /* */ +/* Table16165 */ + 0x38f5, /* VSCALEFPSZ256rmbkz */ + 0x3904, /* VSCALEFPSZrrbkz */ +/* Table16167 */ + 0x2618, /* VPERMDZ256rmbkz */ + 0x0, /* */ +/* Table16169 */ + 0x2aa3, /* VPMINSDZ256rmbkz */ + 0x0, /* */ +/* Table16171 */ + 0x2b09, /* VPMINUDZ256rmbkz */ + 0x0, /* */ +/* Table16173 */ + 0x29d7, /* VPMAXSDZ256rmbkz */ + 0x0, /* */ +/* Table16175 */ + 0x2a3d, /* VPMAXUDZ256rmbkz */ + 0x0, /* */ +/* Table16177 */ + 0x2dea, /* VPMULLDZ256rmbkz */ + 0x0, /* */ +/* Table16179 */ + 0x1aba, /* VGETEXPPSZ256mbkz */ + 0x1ac9, /* VGETEXPPSZrbkz */ +/* Table16181 */ + 0x2907, /* VPLZCNTDZ256rmbkz */ + 0x0, /* */ +/* Table16183 */ + 0x33f7, /* VPSRLVDZ256rmbkz */ + 0x0, /* */ +/* Table16185 */ + 0x3313, /* VPSRAVDZ256rmbkz */ + 0x0, /* */ +/* Table16187 */ + 0x3239, /* VPSLLVDZ256rmbkz */ + 0x0, /* */ +/* Table16189 */ + 0x375a, /* VRCP14PSZ256mbkz */ + 0x0, /* */ +/* Table16191 */ + 0x387e, /* VRSQRT14PSZ256mbkz */ + 0x0, /* */ +/* Table16193 */ + 0x25b8, /* VPDPBUSDZ256mbkz */ + 0x0, /* */ +/* Table16195 */ + 0x259d, /* VPDPBUSDSZ256mbkz */ + 0x0, /* */ +/* Table16197 */ + 0x25ee, /* VPDPWSSDZ256mbkz */ + 0x0, /* */ +/* Table16199 */ + 0x25d3, /* VPDPWSSDSZ256mbkz */ + 0x0, /* */ +/* Table16201 */ + 0x2e84, /* VPOPCNTDZ256rmbkz */ + 0x0, /* */ +/* Table16203 */ + 0x2297, /* VPBLENDMDZ256rmbkz */ + 0x0, /* */ +/* Table16205 */ + 0xcc7, /* VBLENDMPSZ256rmbkz */ + 0x0, /* */ +/* Table16207 */ + 0x305a, /* VPSHLDVDZ256mbkz */ + 0x0, /* */ +/* Table16209 */ + 0x30f6, /* VPSHRDVDZ256mbkz */ + 0x0, /* */ +/* Table16211 */ + 0x2645, /* VPERMI2D256rmbkz */ + 0x0, /* */ +/* Table16213 */ + 0x267b, /* VPERMI2PS256rmbkz */ + 0x0, /* */ +/* Table16215 */ + 0x27c1, /* VPERMT2D256rmbkz */ + 0x0, /* */ +/* Table16217 */ + 0x27f7, /* VPERMT2PS256rmbkz */ + 0x0, /* */ +/* Table16219 */ + 0x14d0, /* VFMADDSUB132PSZ256mbkz */ + 0x14df, /* VFMADDSUB132PSZrbkz */ +/* Table16221 */ + 0x16d8, /* VFMSUBADD132PSZ256mbkz */ + 0x16e7, /* VFMSUBADD132PSZrbkz */ +/* Table16223 */ + 0x1384, /* VFMADD132PSZ256mbkz */ + 0x1393, /* VFMADD132PSZrbkz */ +/* Table16225 */ + 0x15ac, /* VFMSUB132PSZ256mbkz */ + 0x15bb, /* VFMSUB132PSZrbkz */ +/* Table16227 */ + 0x17d4, /* VFNMADD132PSZ256mbkz */ + 0x17e3, /* VFNMADD132PSZrbkz */ +/* Table16229 */ + 0x1920, /* VFNMSUB132PSZ256mbkz */ + 0x192f, /* VFNMSUB132PSZrbkz */ +/* Table16231 */ + 0x1514, /* VFMADDSUB213PSZ256mbkz */ + 0x1523, /* VFMADDSUB213PSZrbkz */ +/* Table16233 */ + 0x171c, /* VFMSUBADD213PSZ256mbkz */ + 0x172b, /* VFMSUBADD213PSZrbkz */ +/* Table16235 */ + 0x13e8, /* VFMADD213PSZ256mbkz */ + 0x13f7, /* VFMADD213PSZrbkz */ +/* Table16237 */ + 0x1610, /* VFMSUB213PSZ256mbkz */ + 0x161f, /* VFMSUB213PSZrbkz */ +/* Table16239 */ + 0x1838, /* VFNMADD213PSZ256mbkz */ + 0x1847, /* VFNMADD213PSZrbkz */ +/* Table16241 */ + 0x1984, /* VFNMSUB213PSZ256mbkz */ + 0x1993, /* VFNMSUB213PSZrbkz */ +/* Table16243 */ + 0x1558, /* VFMADDSUB231PSZ256mbkz */ + 0x1567, /* VFMADDSUB231PSZrbkz */ +/* Table16245 */ + 0x1760, /* VFMSUBADD231PSZ256mbkz */ + 0x176f, /* VFMSUBADD231PSZrbkz */ +/* Table16247 */ + 0x144c, /* VFMADD231PSZ256mbkz */ + 0x145b, /* VFMADD231PSZrbkz */ +/* Table16249 */ + 0x1674, /* VFMSUB231PSZ256mbkz */ + 0x1683, /* VFMSUB231PSZrbkz */ +/* Table16251 */ + 0x189c, /* VFNMADD231PSZ256mbkz */ + 0x18ab, /* VFNMADD231PSZrbkz */ +/* Table16253 */ + 0x19e8, /* VFNMSUB231PSZ256mbkz */ + 0x19f7, /* VFNMSUB231PSZrbkz */ +/* Table16255 */ + 0x2567, /* VPCONFLICTDZ256rmbkz */ + 0x0, /* */ +/* Table16257 */ + 0x26e9, /* VPERMILPDZ256rmbkz */ + 0x0, /* */ +/* Table16259 */ + 0x2fc7, /* VPRORVQZ256rmbkz */ + 0x0, /* */ +/* Table16261 */ + 0x2f5b, /* VPROLVQZ256rmbkz */ + 0x0, /* */ +/* Table16263 */ + 0x2751, /* VPERMPDZ256rmbkz */ + 0x0, /* */ +/* Table16265 */ + 0x206e, /* VPABSQZ256rmbkz */ + 0x0, /* */ +/* Table16267 */ + 0x2d89, /* VPMULDQZ256rmbkz */ + 0x0, /* */ +/* Table16269 */ + 0x38d7, /* VSCALEFPDZ256rmbkz */ + 0x38e6, /* VSCALEFPDZrrbkz */ +/* Table16271 */ + 0x278b, /* VPERMQZ256rmbkz */ + 0x0, /* */ +/* Table16273 */ + 0x2ac0, /* VPMINSQZ256rmbkz */ + 0x0, /* */ +/* Table16275 */ + 0x2b26, /* VPMINUQZ256rmbkz */ + 0x0, /* */ +/* Table16277 */ + 0x29f4, /* VPMAXSQZ256rmbkz */ + 0x0, /* */ +/* Table16279 */ + 0x2a5a, /* VPMAXUQZ256rmbkz */ + 0x0, /* */ +/* Table16281 */ + 0x2e07, /* VPMULLQZ256rmbkz */ + 0x0, /* */ +/* Table16283 */ + 0x1a9c, /* VGETEXPPDZ256mbkz */ + 0x1aab, /* VGETEXPPDZrbkz */ +/* Table16285 */ + 0x2922, /* VPLZCNTQZ256rmbkz */ + 0x0, /* */ +/* Table16287 */ + 0x3416, /* VPSRLVQZ256rmbkz */ + 0x0, /* */ +/* Table16289 */ + 0x3330, /* VPSRAVQZ256rmbkz */ + 0x0, /* */ +/* Table16291 */ + 0x3258, /* VPSLLVQZ256rmbkz */ + 0x0, /* */ +/* Table16293 */ + 0x373f, /* VRCP14PDZ256mbkz */ + 0x0, /* */ +/* Table16295 */ + 0x3863, /* VRSQRT14PDZ256mbkz */ + 0x0, /* */ +/* Table16297 */ + 0x2e9f, /* VPOPCNTQZ256rmbkz */ + 0x0, /* */ +/* Table16299 */ + 0x22b2, /* VPBLENDMQZ256rmbkz */ + 0x0, /* */ +/* Table16301 */ + 0xcac, /* VBLENDMPDZ256rmbkz */ + 0x0, /* */ +/* Table16303 */ + 0x3075, /* VPSHLDVQZ256mbkz */ + 0x0, /* */ +/* Table16305 */ + 0x3111, /* VPSHRDVQZ256mbkz */ + 0x0, /* */ +/* Table16307 */ + 0x2696, /* VPERMI2Q256rmbkz */ + 0x0, /* */ +/* Table16309 */ + 0x2660, /* VPERMI2PD256rmbkz */ + 0x0, /* */ +/* Table16311 */ + 0x2812, /* VPERMT2Q256rmbkz */ + 0x0, /* */ +/* Table16313 */ + 0x27dc, /* VPERMT2PD256rmbkz */ + 0x0, /* */ +/* Table16315 */ + 0x2e38, /* VPMULTISHIFTQBZ256rmbkz */ + 0x0, /* */ +/* Table16317 */ + 0x14ae, /* VFMADDSUB132PDZ256mbkz */ + 0x14bd, /* VFMADDSUB132PDZrbkz */ +/* Table16319 */ + 0x16b6, /* VFMSUBADD132PDZ256mbkz */ + 0x16c5, /* VFMSUBADD132PDZrbkz */ +/* Table16321 */ + 0x1362, /* VFMADD132PDZ256mbkz */ + 0x1371, /* VFMADD132PDZrbkz */ +/* Table16323 */ + 0x158a, /* VFMSUB132PDZ256mbkz */ + 0x1599, /* VFMSUB132PDZrbkz */ +/* Table16325 */ + 0x17b2, /* VFNMADD132PDZ256mbkz */ + 0x17c1, /* VFNMADD132PDZrbkz */ +/* Table16327 */ + 0x18fe, /* VFNMSUB132PDZ256mbkz */ + 0x190d, /* VFNMSUB132PDZrbkz */ +/* Table16329 */ + 0x14f2, /* VFMADDSUB213PDZ256mbkz */ + 0x1501, /* VFMADDSUB213PDZrbkz */ +/* Table16331 */ + 0x16fa, /* VFMSUBADD213PDZ256mbkz */ + 0x1709, /* VFMSUBADD213PDZrbkz */ +/* Table16333 */ + 0x13c6, /* VFMADD213PDZ256mbkz */ + 0x13d5, /* VFMADD213PDZrbkz */ +/* Table16335 */ + 0x15ee, /* VFMSUB213PDZ256mbkz */ + 0x15fd, /* VFMSUB213PDZrbkz */ +/* Table16337 */ + 0x1816, /* VFNMADD213PDZ256mbkz */ + 0x1825, /* VFNMADD213PDZrbkz */ +/* Table16339 */ + 0x1962, /* VFNMSUB213PDZ256mbkz */ + 0x1971, /* VFNMSUB213PDZrbkz */ +/* Table16341 */ + 0x2970, /* VPMADD52LUQZ256mbkz */ + 0x0, /* */ +/* Table16343 */ + 0x2955, /* VPMADD52HUQZ256mbkz */ + 0x0, /* */ +/* Table16345 */ + 0x1536, /* VFMADDSUB231PDZ256mbkz */ + 0x1545, /* VFMADDSUB231PDZrbkz */ +/* Table16347 */ + 0x173e, /* VFMSUBADD231PDZ256mbkz */ + 0x174d, /* VFMSUBADD231PDZrbkz */ +/* Table16349 */ + 0x142a, /* VFMADD231PDZ256mbkz */ + 0x1439, /* VFMADD231PDZrbkz */ +/* Table16351 */ + 0x1652, /* VFMSUB231PDZ256mbkz */ + 0x1661, /* VFMSUB231PDZrbkz */ +/* Table16353 */ + 0x187a, /* VFNMADD231PDZ256mbkz */ + 0x1889, /* VFNMADD231PDZrbkz */ +/* Table16355 */ + 0x19c6, /* VFNMSUB231PDZ256mbkz */ + 0x19d5, /* VFNMSUB231PDZrbkz */ +/* Table16357 */ + 0x2582, /* VPCONFLICTQZ256rmbkz */ + 0x0, /* */ +/* Table16359 */ + 0x2739, /* VPERMILPSZrmbkz */ + 0x0, /* */ +/* Table16361 */ + 0x2fb5, /* VPRORVDZrmbkz */ + 0x0, /* */ +/* Table16363 */ + 0x2f49, /* VPROLVDZrmbkz */ + 0x0, /* */ +/* Table16365 */ + 0x2777, /* VPERMPSZrmbkz */ + 0x0, /* */ +/* Table16367 */ + 0x205a, /* VPABSDZrmbkz */ + 0x0, /* */ +/* Table16369 */ + 0x20df, /* VPACKUSDWZrmbkz */ + 0x0, /* */ +/* Table16371 */ + 0x38fe, /* VSCALEFPSZrmbkz */ + 0x3904, /* VSCALEFPSZrrbkz */ +/* Table16373 */ + 0x2621, /* VPERMDZrmbkz */ + 0x0, /* */ +/* Table16375 */ + 0x2aac, /* VPMINSDZrmbkz */ + 0x0, /* */ +/* Table16377 */ + 0x2b12, /* VPMINUDZrmbkz */ + 0x0, /* */ +/* Table16379 */ + 0x29e0, /* VPMAXSDZrmbkz */ + 0x0, /* */ +/* Table16381 */ + 0x2a46, /* VPMAXUDZrmbkz */ + 0x0, /* */ +/* Table16383 */ + 0x2df3, /* VPMULLDZrmbkz */ + 0x0, /* */ +/* Table16385 */ + 0x1ac3, /* VGETEXPPSZmbkz */ + 0x1ac9, /* VGETEXPPSZrbkz */ +/* Table16387 */ + 0x2910, /* VPLZCNTDZrmbkz */ + 0x0, /* */ +/* Table16389 */ + 0x3400, /* VPSRLVDZrmbkz */ + 0x0, /* */ +/* Table16391 */ + 0x331c, /* VPSRAVDZrmbkz */ + 0x0, /* */ +/* Table16393 */ + 0x3242, /* VPSLLVDZrmbkz */ + 0x0, /* */ +/* Table16395 */ + 0x3763, /* VRCP14PSZmbkz */ + 0x0, /* */ +/* Table16397 */ + 0x3887, /* VRSQRT14PSZmbkz */ + 0x0, /* */ +/* Table16399 */ + 0x25c1, /* VPDPBUSDZmbkz */ + 0x0, /* */ +/* Table16401 */ + 0x25a6, /* VPDPBUSDSZmbkz */ + 0x0, /* */ +/* Table16403 */ + 0x25f7, /* VPDPWSSDZmbkz */ + 0x0, /* */ +/* Table16405 */ + 0x25dc, /* VPDPWSSDSZmbkz */ + 0x0, /* */ +/* Table16407 */ + 0x2e8d, /* VPOPCNTDZrmbkz */ + 0x0, /* */ +/* Table16409 */ + 0x22a0, /* VPBLENDMDZrmbkz */ + 0x0, /* */ +/* Table16411 */ + 0xcd0, /* VBLENDMPSZrmbkz */ + 0x0, /* */ +/* Table16413 */ + 0x3063, /* VPSHLDVDZmbkz */ + 0x0, /* */ +/* Table16415 */ + 0x30ff, /* VPSHRDVDZmbkz */ + 0x0, /* */ +/* Table16417 */ + 0x264e, /* VPERMI2Drmbkz */ + 0x0, /* */ +/* Table16419 */ + 0x2684, /* VPERMI2PSrmbkz */ + 0x0, /* */ +/* Table16421 */ + 0x27ca, /* VPERMT2Drmbkz */ + 0x0, /* */ +/* Table16423 */ + 0x2800, /* VPERMT2PSrmbkz */ + 0x0, /* */ +/* Table16425 */ + 0x14d9, /* VFMADDSUB132PSZmbkz */ + 0x14df, /* VFMADDSUB132PSZrbkz */ +/* Table16427 */ + 0x16e1, /* VFMSUBADD132PSZmbkz */ + 0x16e7, /* VFMSUBADD132PSZrbkz */ +/* Table16429 */ + 0x138d, /* VFMADD132PSZmbkz */ + 0x1393, /* VFMADD132PSZrbkz */ +/* Table16431 */ + 0x15b5, /* VFMSUB132PSZmbkz */ + 0x15bb, /* VFMSUB132PSZrbkz */ +/* Table16433 */ + 0x17dd, /* VFNMADD132PSZmbkz */ + 0x17e3, /* VFNMADD132PSZrbkz */ +/* Table16435 */ + 0x1929, /* VFNMSUB132PSZmbkz */ + 0x192f, /* VFNMSUB132PSZrbkz */ +/* Table16437 */ + 0x151d, /* VFMADDSUB213PSZmbkz */ + 0x1523, /* VFMADDSUB213PSZrbkz */ +/* Table16439 */ + 0x1725, /* VFMSUBADD213PSZmbkz */ + 0x172b, /* VFMSUBADD213PSZrbkz */ +/* Table16441 */ + 0x13f1, /* VFMADD213PSZmbkz */ + 0x13f7, /* VFMADD213PSZrbkz */ +/* Table16443 */ + 0x1619, /* VFMSUB213PSZmbkz */ + 0x161f, /* VFMSUB213PSZrbkz */ +/* Table16445 */ + 0x1841, /* VFNMADD213PSZmbkz */ + 0x1847, /* VFNMADD213PSZrbkz */ +/* Table16447 */ + 0x198d, /* VFNMSUB213PSZmbkz */ + 0x1993, /* VFNMSUB213PSZrbkz */ +/* Table16449 */ + 0x1561, /* VFMADDSUB231PSZmbkz */ + 0x1567, /* VFMADDSUB231PSZrbkz */ +/* Table16451 */ + 0x1769, /* VFMSUBADD231PSZmbkz */ + 0x176f, /* VFMSUBADD231PSZrbkz */ +/* Table16453 */ + 0x1455, /* VFMADD231PSZmbkz */ + 0x145b, /* VFMADD231PSZrbkz */ +/* Table16455 */ + 0x167d, /* VFMSUB231PSZmbkz */ + 0x1683, /* VFMSUB231PSZrbkz */ +/* Table16457 */ + 0x18a5, /* VFNMADD231PSZmbkz */ + 0x18ab, /* VFNMADD231PSZrbkz */ +/* Table16459 */ + 0x19f1, /* VFNMSUB231PSZmbkz */ + 0x19f7, /* VFNMSUB231PSZrbkz */ +/* Table16461 */ + 0x2570, /* VPCONFLICTDZrmbkz */ + 0x0, /* */ +/* Table16463 */ + 0x1295, /* VEXP2PSZmbkz */ + 0x129b, /* VEXP2PSZrbkz */ +/* Table16465 */ + 0x3784, /* VRCP28PSZmbkz */ + 0x378a, /* VRCP28PSZrbkz */ +/* Table16467 */ + 0x38a8, /* VRSQRT28PSZmbkz */ + 0x38ae, /* VRSQRT28PSZrbkz */ +/* Table16469 */ + 0x26fb, /* VPERMILPDZrmbkz */ + 0x0, /* */ +/* Table16471 */ + 0x2fd0, /* VPRORVQZrmbkz */ + 0x0, /* */ +/* Table16473 */ + 0x2f64, /* VPROLVQZrmbkz */ + 0x0, /* */ +/* Table16475 */ + 0x2763, /* VPERMPDZrmbkz */ + 0x0, /* */ +/* Table16477 */ + 0x2077, /* VPABSQZrmbkz */ + 0x0, /* */ +/* Table16479 */ + 0x2d92, /* VPMULDQZrmbkz */ + 0x0, /* */ +/* Table16481 */ + 0x38e0, /* VSCALEFPDZrmbkz */ + 0x38e6, /* VSCALEFPDZrrbkz */ +/* Table16483 */ + 0x279d, /* VPERMQZrmbkz */ + 0x0, /* */ +/* Table16485 */ + 0x2ac9, /* VPMINSQZrmbkz */ + 0x0, /* */ +/* Table16487 */ + 0x2b2f, /* VPMINUQZrmbkz */ + 0x0, /* */ +/* Table16489 */ + 0x29fd, /* VPMAXSQZrmbkz */ + 0x0, /* */ +/* Table16491 */ + 0x2a63, /* VPMAXUQZrmbkz */ + 0x0, /* */ +/* Table16493 */ + 0x2e10, /* VPMULLQZrmbkz */ + 0x0, /* */ +/* Table16495 */ + 0x1aa5, /* VGETEXPPDZmbkz */ + 0x1aab, /* VGETEXPPDZrbkz */ +/* Table16497 */ + 0x292b, /* VPLZCNTQZrmbkz */ + 0x0, /* */ +/* Table16499 */ + 0x341f, /* VPSRLVQZrmbkz */ + 0x0, /* */ +/* Table16501 */ + 0x3339, /* VPSRAVQZrmbkz */ + 0x0, /* */ +/* Table16503 */ + 0x3261, /* VPSLLVQZrmbkz */ + 0x0, /* */ +/* Table16505 */ + 0x3748, /* VRCP14PDZmbkz */ + 0x0, /* */ +/* Table16507 */ + 0x386c, /* VRSQRT14PDZmbkz */ + 0x0, /* */ +/* Table16509 */ + 0x2ea8, /* VPOPCNTQZrmbkz */ + 0x0, /* */ +/* Table16511 */ + 0x22bb, /* VPBLENDMQZrmbkz */ + 0x0, /* */ +/* Table16513 */ + 0xcb5, /* VBLENDMPDZrmbkz */ + 0x0, /* */ +/* Table16515 */ + 0x307e, /* VPSHLDVQZmbkz */ + 0x0, /* */ +/* Table16517 */ + 0x311a, /* VPSHRDVQZmbkz */ + 0x0, /* */ +/* Table16519 */ + 0x269f, /* VPERMI2Qrmbkz */ + 0x0, /* */ +/* Table16521 */ + 0x2669, /* VPERMI2PDrmbkz */ + 0x0, /* */ +/* Table16523 */ + 0x281b, /* VPERMT2Qrmbkz */ + 0x0, /* */ +/* Table16525 */ + 0x27e5, /* VPERMT2PDrmbkz */ + 0x0, /* */ +/* Table16527 */ + 0x2e41, /* VPMULTISHIFTQBZrmbkz */ + 0x0, /* */ +/* Table16529 */ + 0x14b7, /* VFMADDSUB132PDZmbkz */ + 0x14bd, /* VFMADDSUB132PDZrbkz */ +/* Table16531 */ + 0x16bf, /* VFMSUBADD132PDZmbkz */ + 0x16c5, /* VFMSUBADD132PDZrbkz */ +/* Table16533 */ + 0x136b, /* VFMADD132PDZmbkz */ + 0x1371, /* VFMADD132PDZrbkz */ +/* Table16535 */ + 0x1593, /* VFMSUB132PDZmbkz */ + 0x1599, /* VFMSUB132PDZrbkz */ +/* Table16537 */ + 0x17bb, /* VFNMADD132PDZmbkz */ + 0x17c1, /* VFNMADD132PDZrbkz */ +/* Table16539 */ + 0x1907, /* VFNMSUB132PDZmbkz */ + 0x190d, /* VFNMSUB132PDZrbkz */ +/* Table16541 */ + 0x14fb, /* VFMADDSUB213PDZmbkz */ + 0x1501, /* VFMADDSUB213PDZrbkz */ +/* Table16543 */ + 0x1703, /* VFMSUBADD213PDZmbkz */ + 0x1709, /* VFMSUBADD213PDZrbkz */ +/* Table16545 */ + 0x13cf, /* VFMADD213PDZmbkz */ + 0x13d5, /* VFMADD213PDZrbkz */ +/* Table16547 */ + 0x15f7, /* VFMSUB213PDZmbkz */ + 0x15fd, /* VFMSUB213PDZrbkz */ +/* Table16549 */ + 0x181f, /* VFNMADD213PDZmbkz */ + 0x1825, /* VFNMADD213PDZrbkz */ +/* Table16551 */ + 0x196b, /* VFNMSUB213PDZmbkz */ + 0x1971, /* VFNMSUB213PDZrbkz */ +/* Table16553 */ + 0x2979, /* VPMADD52LUQZmbkz */ + 0x0, /* */ +/* Table16555 */ + 0x295e, /* VPMADD52HUQZmbkz */ + 0x0, /* */ +/* Table16557 */ + 0x153f, /* VFMADDSUB231PDZmbkz */ + 0x1545, /* VFMADDSUB231PDZrbkz */ +/* Table16559 */ + 0x1747, /* VFMSUBADD231PDZmbkz */ + 0x174d, /* VFMSUBADD231PDZrbkz */ +/* Table16561 */ + 0x1433, /* VFMADD231PDZmbkz */ + 0x1439, /* VFMADD231PDZrbkz */ +/* Table16563 */ + 0x165b, /* VFMSUB231PDZmbkz */ + 0x1661, /* VFMSUB231PDZrbkz */ +/* Table16565 */ + 0x1883, /* VFNMADD231PDZmbkz */ + 0x1889, /* VFNMADD231PDZrbkz */ +/* Table16567 */ + 0x19cf, /* VFNMSUB231PDZmbkz */ + 0x19d5, /* VFNMSUB231PDZrbkz */ +/* Table16569 */ + 0x258b, /* VPCONFLICTQZrmbkz */ + 0x0, /* */ +/* Table16571 */ + 0x1289, /* VEXP2PDZmbkz */ + 0x128f, /* VEXP2PDZrbkz */ +/* Table16573 */ + 0x3778, /* VRCP28PDZmbkz */ + 0x377e, /* VRCP28PDZrbkz */ +/* Table16575 */ + 0x389c, /* VRSQRT28PDZmbkz */ + 0x38a2, /* VRSQRT28PDZrbkz */ +/* Table16577 */ + 0x0, /* */ + 0x2cda, /* VPMOVUSWBZ128rrkz */ +/* Table16579 */ + 0x0, /* */ + 0x2c8f, /* VPMOVUSDBZ128rrkz */ +/* Table16581 */ + 0x0, /* */ + 0x2cad, /* VPMOVUSQBZ128rrkz */ +/* Table16583 */ + 0x0, /* */ + 0x2c9e, /* VPMOVUSDWZ128rrkz */ +/* Table16585 */ + 0x0, /* */ + 0x2ccb, /* VPMOVUSQWZ128rrkz */ +/* Table16587 */ + 0x0, /* */ + 0x2cbc, /* VPMOVUSQDZ128rrkz */ +/* Table16589 */ + 0x0, /* */ + 0x2bfc, /* VPMOVSWBZ128rrkz */ +/* Table16591 */ + 0x0, /* */ + 0x2bb1, /* VPMOVSDBZ128rrkz */ +/* Table16593 */ + 0x0, /* */ + 0x2bcf, /* VPMOVSQBZ128rrkz */ +/* Table16595 */ + 0x0, /* */ + 0x2bc0, /* VPMOVSDWZ128rrkz */ +/* Table16597 */ + 0x0, /* */ + 0x2bed, /* VPMOVSQWZ128rrkz */ +/* Table16599 */ + 0x0, /* */ + 0x2bde, /* VPMOVSQDZ128rrkz */ +/* Table16601 */ + 0x0, /* */ + 0x2cec, /* VPMOVWBZ128rrkz */ +/* Table16603 */ + 0x0, /* */ + 0x2b55, /* VPMOVDBZ128rrkz */ +/* Table16605 */ + 0x0, /* */ + 0x2b84, /* VPMOVQBZ128rrkz */ +/* Table16607 */ + 0x0, /* */ + 0x2b64, /* VPMOVDWZ128rrkz */ +/* Table16609 */ + 0x0, /* */ + 0x2ba2, /* VPMOVQWZ128rrkz */ +/* Table16611 */ + 0x0, /* */ + 0x2b93, /* VPMOVQDZ128rrkz */ +/* Table16613 */ + 0xb51, /* V4FMADDSSrmkz */ + 0x0, /* */ +/* Table16615 */ + 0xb57, /* V4FNMADDSSrmkz */ + 0x0, /* */ +/* Table16617 */ + 0x3154, /* VPSHUFBZ128rmkz */ + 0x3157, /* VPSHUFBZ128rrkz */ +/* Table16619 */ + 0x2983, /* VPMADDUBSWZ128rmkz */ + 0x2986, /* VPMADDUBSWZ128rrkz */ +/* Table16621 */ + 0x2d9e, /* VPMULHRSWZ128rmkz */ + 0x2da1, /* VPMULHRSWZ128rrkz */ +/* Table16623 */ + 0x2717, /* VPERMILPSZ128rmkz */ + 0x271a, /* VPERMILPSZ128rrkz */ +/* Table16625 */ + 0xee9, /* VCVTPH2PSZ128rmkz */ + 0xeec, /* VCVTPH2PSZ128rrkz */ +/* Table16627 */ + 0x2fa5, /* VPRORVDZ128rmkz */ + 0x2fa8, /* VPRORVDZ128rrkz */ +/* Table16629 */ + 0x2f39, /* VPROLVDZ128rmkz */ + 0x2f3c, /* VPROLVDZ128rrkz */ +/* Table16631 */ + 0xd3c, /* VBROADCASTSSZ128mkz */ + 0xd3f, /* VBROADCASTSSZ128rkz */ +/* Table16633 */ + 0x2031, /* VPABSBZ128rmkz */ + 0x2034, /* VPABSBZ128rrkz */ +/* Table16635 */ + 0x2081, /* VPABSWZ128rmkz */ + 0x2084, /* VPABSWZ128rrkz */ +/* Table16637 */ + 0x204a, /* VPABSDZ128rmkz */ + 0x204d, /* VPABSDZ128rrkz */ +/* Table16639 */ + 0x2c37, /* VPMOVSXBWZ128rmkz */ + 0x2c3a, /* VPMOVSXBWZ128rrkz */ +/* Table16641 */ + 0x2c0b, /* VPMOVSXBDZ128rmkz */ + 0x2c0e, /* VPMOVSXBDZ128rrkz */ +/* Table16643 */ + 0x2c21, /* VPMOVSXBQZ128rmkz */ + 0x2c24, /* VPMOVSXBQZ128rrkz */ +/* Table16645 */ + 0x2c63, /* VPMOVSXWDZ128rmkz */ + 0x2c66, /* VPMOVSXWDZ128rrkz */ +/* Table16647 */ + 0x2c79, /* VPMOVSXWQZ128rmkz */ + 0x2c7c, /* VPMOVSXWQZ128rrkz */ +/* Table16649 */ + 0x2c4d, /* VPMOVSXDQZ128rmkz */ + 0x2c50, /* VPMOVSXDQZ128rrkz */ +/* Table16651 */ + 0x20cf, /* VPACKUSDWZ128rmkz */ + 0x20d2, /* VPACKUSDWZ128rrkz */ +/* Table16653 */ + 0x38ee, /* VSCALEFPSZ128rmkz */ + 0x38f1, /* VSCALEFPSZ128rrkz */ +/* Table16655 */ + 0x3912, /* VSCALEFSSZrmkz */ + 0x3918, /* VSCALEFSSZrrkz */ +/* Table16657 */ + 0x2d27, /* VPMOVZXBWZ128rmkz */ + 0x2d2a, /* VPMOVZXBWZ128rrkz */ +/* Table16659 */ + 0x2cfb, /* VPMOVZXBDZ128rmkz */ + 0x2cfe, /* VPMOVZXBDZ128rrkz */ +/* Table16661 */ + 0x2d11, /* VPMOVZXBQZ128rmkz */ + 0x2d14, /* VPMOVZXBQZ128rrkz */ +/* Table16663 */ + 0x2d53, /* VPMOVZXWDZ128rmkz */ + 0x2d56, /* VPMOVZXWDZ128rrkz */ +/* Table16665 */ + 0x2d69, /* VPMOVZXWQZ128rmkz */ + 0x2d6c, /* VPMOVZXWQZ128rrkz */ +/* Table16667 */ + 0x2d3d, /* VPMOVZXDQZ128rmkz */ + 0x2d40, /* VPMOVZXDQZ128rrkz */ +/* Table16669 */ + 0x2a83, /* VPMINSBZ128rmkz */ + 0x2a86, /* VPMINSBZ128rrkz */ +/* Table16671 */ + 0x2a9c, /* VPMINSDZ128rmkz */ + 0x2a9f, /* VPMINSDZ128rrkz */ +/* Table16673 */ + 0x2b39, /* VPMINUWZ128rmkz */ + 0x2b3c, /* VPMINUWZ128rrkz */ +/* Table16675 */ + 0x2b02, /* VPMINUDZ128rmkz */ + 0x2b05, /* VPMINUDZ128rrkz */ +/* Table16677 */ + 0x29b7, /* VPMAXSBZ128rmkz */ + 0x29ba, /* VPMAXSBZ128rrkz */ +/* Table16679 */ + 0x29d0, /* VPMAXSDZ128rmkz */ + 0x29d3, /* VPMAXSDZ128rrkz */ +/* Table16681 */ + 0x2a6d, /* VPMAXUWZ128rmkz */ + 0x2a70, /* VPMAXUWZ128rrkz */ +/* Table16683 */ + 0x2a36, /* VPMAXUDZ128rmkz */ + 0x2a39, /* VPMAXUDZ128rrkz */ +/* Table16685 */ + 0x2de3, /* VPMULLDZ128rmkz */ + 0x2de6, /* VPMULLDZ128rrkz */ +/* Table16687 */ + 0x1ab3, /* VGETEXPPSZ128mkz */ + 0x1ab6, /* VGETEXPPSZ128rkz */ +/* Table16689 */ + 0x1ad7, /* VGETEXPSSZmkz */ + 0x1add, /* VGETEXPSSZrkz */ +/* Table16691 */ + 0x2900, /* VPLZCNTDZ128rmkz */ + 0x2903, /* VPLZCNTDZ128rrkz */ +/* Table16693 */ + 0x33f0, /* VPSRLVDZ128rmkz */ + 0x33f3, /* VPSRLVDZ128rrkz */ +/* Table16695 */ + 0x330c, /* VPSRAVDZ128rmkz */ + 0x330f, /* VPSRAVDZ128rrkz */ +/* Table16697 */ + 0x3232, /* VPSLLVDZ128rmkz */ + 0x3235, /* VPSLLVDZ128rrkz */ +/* Table16699 */ + 0x3753, /* VRCP14PSZ128mkz */ + 0x3756, /* VRCP14PSZ128rkz */ +/* Table16701 */ + 0x3771, /* VRCP14SSZrmkz */ + 0x3774, /* VRCP14SSZrrkz */ +/* Table16703 */ + 0x3877, /* VRSQRT14PSZ128mkz */ + 0x387a, /* VRSQRT14PSZ128rkz */ +/* Table16705 */ + 0x3895, /* VRSQRT14SSZrmkz */ + 0x3898, /* VRSQRT14SSZrrkz */ +/* Table16707 */ + 0x25b1, /* VPDPBUSDZ128mkz */ + 0x25b4, /* VPDPBUSDZ128rkz */ +/* Table16709 */ + 0x2596, /* VPDPBUSDSZ128mkz */ + 0x2599, /* VPDPBUSDSZ128rkz */ +/* Table16711 */ + 0x25e7, /* VPDPWSSDZ128mkz */ + 0x25ea, /* VPDPWSSDZ128rkz */ +/* Table16713 */ + 0x25cc, /* VPDPWSSDSZ128mkz */ + 0x25cf, /* VPDPWSSDSZ128rkz */ +/* Table16715 */ + 0x2e68, /* VPOPCNTBZ128rmkz */ + 0x2e6b, /* VPOPCNTBZ128rrkz */ +/* Table16717 */ + 0x2e7d, /* VPOPCNTDZ128rmkz */ + 0x2e80, /* VPOPCNTDZ128rrkz */ +/* Table16719 */ + 0x22fe, /* VPBROADCASTDZ128mkz */ + 0x2301, /* VPBROADCASTDZ128rkz */ +/* Table16721 */ + 0xd08, /* VBROADCASTI32X2Z128mkz */ + 0xd0b, /* VBROADCASTI32X2Z128rkz */ +/* Table16723 */ + 0x2847, /* VPEXPANDBZ128rmkz */ + 0x284a, /* VPEXPANDBZ128rrkz */ +/* Table16725 */ + 0x0, /* */ + 0x250b, /* VPCOMPRESSBZ128rrkz */ +/* Table16727 */ + 0x2290, /* VPBLENDMDZ128rmkz */ + 0x2293, /* VPBLENDMDZ128rrkz */ +/* Table16729 */ + 0xcc0, /* VBLENDMPSZ128rmkz */ + 0xcc3, /* VBLENDMPSZ128rrkz */ +/* Table16731 */ + 0x227b, /* VPBLENDMBZ128rmkz */ + 0x227e, /* VPBLENDMBZ128rrkz */ +/* Table16733 */ + 0x3053, /* VPSHLDVDZ128mkz */ + 0x3056, /* VPSHLDVDZ128rkz */ +/* Table16735 */ + 0x30ef, /* VPSHRDVDZ128mkz */ + 0x30f2, /* VPSHRDVDZ128rkz */ +/* Table16737 */ + 0x2629, /* VPERMI2B128rmkz */ + 0x262c, /* VPERMI2B128rrkz */ +/* Table16739 */ + 0x263e, /* VPERMI2D128rmkz */ + 0x2641, /* VPERMI2D128rrkz */ +/* Table16741 */ + 0x2674, /* VPERMI2PS128rmkz */ + 0x2677, /* VPERMI2PS128rrkz */ +/* Table16743 */ + 0x22df, /* VPBROADCASTBZ128mkz */ + 0x22e2, /* VPBROADCASTBZ128rkz */ +/* Table16745 */ + 0x2342, /* VPBROADCASTWZ128mkz */ + 0x2345, /* VPBROADCASTWZ128rkz */ +/* Table16747 */ + 0x0, /* */ + 0x22f1, /* VPBROADCASTBrZ128rkz */ +/* Table16749 */ + 0x0, /* */ + 0x2354, /* VPBROADCASTWrZ128rkz */ +/* Table16751 */ + 0x0, /* */ + 0x2310, /* VPBROADCASTDrZ128rkz */ +/* Table16753 */ + 0x27a5, /* VPERMT2B128rmkz */ + 0x27a8, /* VPERMT2B128rrkz */ +/* Table16755 */ + 0x27ba, /* VPERMT2D128rmkz */ + 0x27bd, /* VPERMT2D128rrkz */ +/* Table16757 */ + 0x27f0, /* VPERMT2PS128rmkz */ + 0x27f3, /* VPERMT2PS128rrkz */ +/* Table16759 */ + 0x12b2, /* VEXPANDPSZ128rmkz */ + 0x12b5, /* VEXPANDPSZ128rrkz */ +/* Table16761 */ + 0x2859, /* VPEXPANDDZ128rmkz */ + 0x285c, /* VPEXPANDDZ128rrkz */ +/* Table16763 */ + 0x0, /* */ + 0xdfb, /* VCOMPRESSPSZ128rrkz */ +/* Table16765 */ + 0x0, /* */ + 0x251a, /* VPCOMPRESSDZ128rrkz */ +/* Table16767 */ + 0x2603, /* VPERMBZ128rmkz */ + 0x2606, /* VPERMBZ128rrkz */ +/* Table16769 */ + 0x14c9, /* VFMADDSUB132PSZ128mkz */ + 0x14cc, /* VFMADDSUB132PSZ128rkz */ +/* Table16771 */ + 0x16d1, /* VFMSUBADD132PSZ128mkz */ + 0x16d4, /* VFMSUBADD132PSZ128rkz */ +/* Table16773 */ + 0x137d, /* VFMADD132PSZ128mkz */ + 0x1380, /* VFMADD132PSZ128rkz */ +/* Table16775 */ + 0x13ab, /* VFMADD132SSZm_Intkz */ + 0x13af, /* VFMADD132SSZr_Intkz */ +/* Table16777 */ + 0x15a5, /* VFMSUB132PSZ128mkz */ + 0x15a8, /* VFMSUB132PSZ128rkz */ +/* Table16779 */ + 0x15d3, /* VFMSUB132SSZm_Intkz */ + 0x15d7, /* VFMSUB132SSZr_Intkz */ +/* Table16781 */ + 0x17cd, /* VFNMADD132PSZ128mkz */ + 0x17d0, /* VFNMADD132PSZ128rkz */ +/* Table16783 */ + 0x17fb, /* VFNMADD132SSZm_Intkz */ + 0x17ff, /* VFNMADD132SSZr_Intkz */ +/* Table16785 */ + 0x1919, /* VFNMSUB132PSZ128mkz */ + 0x191c, /* VFNMSUB132PSZ128rkz */ +/* Table16787 */ + 0x1947, /* VFNMSUB132SSZm_Intkz */ + 0x194b, /* VFNMSUB132SSZr_Intkz */ +/* Table16789 */ + 0x150d, /* VFMADDSUB213PSZ128mkz */ + 0x1510, /* VFMADDSUB213PSZ128rkz */ +/* Table16791 */ + 0x1715, /* VFMSUBADD213PSZ128mkz */ + 0x1718, /* VFMSUBADD213PSZ128rkz */ +/* Table16793 */ + 0x13e1, /* VFMADD213PSZ128mkz */ + 0x13e4, /* VFMADD213PSZ128rkz */ +/* Table16795 */ + 0x140f, /* VFMADD213SSZm_Intkz */ + 0x1413, /* VFMADD213SSZr_Intkz */ +/* Table16797 */ + 0x1609, /* VFMSUB213PSZ128mkz */ + 0x160c, /* VFMSUB213PSZ128rkz */ +/* Table16799 */ + 0x1637, /* VFMSUB213SSZm_Intkz */ + 0x163b, /* VFMSUB213SSZr_Intkz */ +/* Table16801 */ + 0x1831, /* VFNMADD213PSZ128mkz */ + 0x1834, /* VFNMADD213PSZ128rkz */ +/* Table16803 */ + 0x185f, /* VFNMADD213SSZm_Intkz */ + 0x1863, /* VFNMADD213SSZr_Intkz */ +/* Table16805 */ + 0x197d, /* VFNMSUB213PSZ128mkz */ + 0x1980, /* VFNMSUB213PSZ128rkz */ +/* Table16807 */ + 0x19ab, /* VFNMSUB213SSZm_Intkz */ + 0x19af, /* VFNMSUB213SSZr_Intkz */ +/* Table16809 */ + 0x1551, /* VFMADDSUB231PSZ128mkz */ + 0x1554, /* VFMADDSUB231PSZ128rkz */ +/* Table16811 */ + 0x1759, /* VFMSUBADD231PSZ128mkz */ + 0x175c, /* VFMSUBADD231PSZ128rkz */ +/* Table16813 */ + 0x1445, /* VFMADD231PSZ128mkz */ + 0x1448, /* VFMADD231PSZ128rkz */ +/* Table16815 */ + 0x1473, /* VFMADD231SSZm_Intkz */ + 0x1477, /* VFMADD231SSZr_Intkz */ +/* Table16817 */ + 0x166d, /* VFMSUB231PSZ128mkz */ + 0x1670, /* VFMSUB231PSZ128rkz */ +/* Table16819 */ + 0x169b, /* VFMSUB231SSZm_Intkz */ + 0x169f, /* VFMSUB231SSZr_Intkz */ +/* Table16821 */ + 0x1895, /* VFNMADD231PSZ128mkz */ + 0x1898, /* VFNMADD231PSZ128rkz */ +/* Table16823 */ + 0x18c3, /* VFNMADD231SSZm_Intkz */ + 0x18c7, /* VFNMADD231SSZr_Intkz */ +/* Table16825 */ + 0x19e1, /* VFNMSUB231PSZ128mkz */ + 0x19e4, /* VFNMSUB231PSZ128rkz */ +/* Table16827 */ + 0x1a0f, /* VFNMSUB231SSZm_Intkz */ + 0x1a13, /* VFNMSUB231SSZr_Intkz */ +/* Table16829 */ + 0x2560, /* VPCONFLICTDZ128rmkz */ + 0x2563, /* VPCONFLICTDZ128rrkz */ +/* Table16831 */ + 0x3798, /* VRCP28SSZmkz */ + 0x379e, /* VRCP28SSZrkz */ +/* Table16833 */ + 0x38bc, /* VRSQRT28SSZmkz */ + 0x38c2, /* VRSQRT28SSZrkz */ +/* Table16835 */ + 0x1b6e, /* VGF2P8MULBZ128rmkz */ + 0x1b71, /* VGF2P8MULBZ128rrkz */ +/* Table16837 */ + 0x26d9, /* VPERMILPDZ128rmkz */ + 0x26dc, /* VPERMILPDZ128rrkz */ +/* Table16839 */ + 0x3429, /* VPSRLVWZ128rmkz */ + 0x342c, /* VPSRLVWZ128rrkz */ +/* Table16841 */ + 0x3341, /* VPSRAVWZ128rmkz */ + 0x3344, /* VPSRAVWZ128rrkz */ +/* Table16843 */ + 0x326b, /* VPSLLVWZ128rmkz */ + 0x326e, /* VPSLLVWZ128rrkz */ +/* Table16845 */ + 0x2fc0, /* VPRORVQZ128rmkz */ + 0x2fc3, /* VPRORVQZ128rrkz */ +/* Table16847 */ + 0x2f54, /* VPROLVQZ128rmkz */ + 0x2f57, /* VPROLVQZ128rrkz */ +/* Table16849 */ + 0x2067, /* VPABSQZ128rmkz */ + 0x206a, /* VPABSQZ128rrkz */ +/* Table16851 */ + 0x2d82, /* VPMULDQZ128rmkz */ + 0x2d85, /* VPMULDQZ128rrkz */ +/* Table16853 */ + 0x38d0, /* VSCALEFPDZ128rmkz */ + 0x38d3, /* VSCALEFPDZ128rrkz */ +/* Table16855 */ + 0x3909, /* VSCALEFSDZrmkz */ + 0x390f, /* VSCALEFSDZrrkz */ +/* Table16857 */ + 0x2ab9, /* VPMINSQZ128rmkz */ + 0x2abc, /* VPMINSQZ128rrkz */ +/* Table16859 */ + 0x2b1f, /* VPMINUQZ128rmkz */ + 0x2b22, /* VPMINUQZ128rrkz */ +/* Table16861 */ + 0x29ed, /* VPMAXSQZ128rmkz */ + 0x29f0, /* VPMAXSQZ128rrkz */ +/* Table16863 */ + 0x2a53, /* VPMAXUQZ128rmkz */ + 0x2a56, /* VPMAXUQZ128rrkz */ +/* Table16865 */ + 0x2e00, /* VPMULLQZ128rmkz */ + 0x2e03, /* VPMULLQZ128rrkz */ +/* Table16867 */ + 0x1a95, /* VGETEXPPDZ128mkz */ + 0x1a98, /* VGETEXPPDZ128rkz */ +/* Table16869 */ + 0x1ace, /* VGETEXPSDZmkz */ + 0x1ad4, /* VGETEXPSDZrkz */ +/* Table16871 */ + 0x291b, /* VPLZCNTQZ128rmkz */ + 0x291e, /* VPLZCNTQZ128rrkz */ +/* Table16873 */ + 0x340f, /* VPSRLVQZ128rmkz */ + 0x3412, /* VPSRLVQZ128rrkz */ +/* Table16875 */ + 0x3329, /* VPSRAVQZ128rmkz */ + 0x332c, /* VPSRAVQZ128rrkz */ +/* Table16877 */ + 0x3251, /* VPSLLVQZ128rmkz */ + 0x3254, /* VPSLLVQZ128rrkz */ +/* Table16879 */ + 0x3738, /* VRCP14PDZ128mkz */ + 0x373b, /* VRCP14PDZ128rkz */ +/* Table16881 */ + 0x376b, /* VRCP14SDZrmkz */ + 0x376e, /* VRCP14SDZrrkz */ +/* Table16883 */ + 0x385c, /* VRSQRT14PDZ128mkz */ + 0x385f, /* VRSQRT14PDZ128rkz */ +/* Table16885 */ + 0x388f, /* VRSQRT14SDZrmkz */ + 0x3892, /* VRSQRT14SDZrrkz */ +/* Table16887 */ + 0x2eb0, /* VPOPCNTWZ128rmkz */ + 0x2eb3, /* VPOPCNTWZ128rrkz */ +/* Table16889 */ + 0x2e98, /* VPOPCNTQZ128rmkz */ + 0x2e9b, /* VPOPCNTQZ128rrkz */ +/* Table16891 */ + 0x2323, /* VPBROADCASTQZ128mkz */ + 0x2326, /* VPBROADCASTQZ128rkz */ +/* Table16893 */ + 0x287d, /* VPEXPANDWZ128rmkz */ + 0x2880, /* VPEXPANDWZ128rrkz */ +/* Table16895 */ + 0x0, /* */ + 0x2538, /* VPCOMPRESSWZ128rrkz */ +/* Table16897 */ + 0x22ab, /* VPBLENDMQZ128rmkz */ + 0x22ae, /* VPBLENDMQZ128rrkz */ +/* Table16899 */ + 0xca5, /* VBLENDMPDZ128rmkz */ + 0xca8, /* VBLENDMPDZ128rrkz */ +/* Table16901 */ + 0x22c3, /* VPBLENDMWZ128rmkz */ + 0x22c6, /* VPBLENDMWZ128rrkz */ +/* Table16903 */ + 0x3086, /* VPSHLDVWZ128mkz */ + 0x3089, /* VPSHLDVWZ128rkz */ +/* Table16905 */ + 0x306e, /* VPSHLDVQZ128mkz */ + 0x3071, /* VPSHLDVQZ128rkz */ +/* Table16907 */ + 0x3122, /* VPSHRDVWZ128mkz */ + 0x3125, /* VPSHRDVWZ128rkz */ +/* Table16909 */ + 0x310a, /* VPSHRDVQZ128mkz */ + 0x310d, /* VPSHRDVQZ128rkz */ +/* Table16911 */ + 0x26a7, /* VPERMI2W128rmkz */ + 0x26aa, /* VPERMI2W128rrkz */ +/* Table16913 */ + 0x268f, /* VPERMI2Q128rmkz */ + 0x2692, /* VPERMI2Q128rrkz */ +/* Table16915 */ + 0x2659, /* VPERMI2PD128rmkz */ + 0x265c, /* VPERMI2PD128rrkz */ +/* Table16917 */ + 0x0, /* */ + 0x2335, /* VPBROADCASTQrZ128rkz */ +/* Table16919 */ + 0x2823, /* VPERMT2W128rmkz */ + 0x2826, /* VPERMT2W128rrkz */ +/* Table16921 */ + 0x280b, /* VPERMT2Q128rmkz */ + 0x280e, /* VPERMT2Q128rrkz */ +/* Table16923 */ + 0x27d5, /* VPERMT2PD128rmkz */ + 0x27d8, /* VPERMT2PD128rrkz */ +/* Table16925 */ + 0x2e31, /* VPMULTISHIFTQBZ128rmkz */ + 0x2e34, /* VPMULTISHIFTQBZ128rrkz */ +/* Table16927 */ + 0x12a0, /* VEXPANDPDZ128rmkz */ + 0x12a3, /* VEXPANDPDZ128rrkz */ +/* Table16929 */ + 0x286b, /* VPEXPANDQZ128rmkz */ + 0x286e, /* VPEXPANDQZ128rrkz */ +/* Table16931 */ + 0x0, /* */ + 0xdec, /* VCOMPRESSPDZ128rrkz */ +/* Table16933 */ + 0x0, /* */ + 0x2529, /* VPCOMPRESSQZ128rrkz */ +/* Table16935 */ + 0x2835, /* VPERMWZ128rmkz */ + 0x2838, /* VPERMWZ128rrkz */ +/* Table16937 */ + 0x14a7, /* VFMADDSUB132PDZ128mkz */ + 0x14aa, /* VFMADDSUB132PDZ128rkz */ +/* Table16939 */ + 0x16af, /* VFMSUBADD132PDZ128mkz */ + 0x16b2, /* VFMSUBADD132PDZ128rkz */ +/* Table16941 */ + 0x135b, /* VFMADD132PDZ128mkz */ + 0x135e, /* VFMADD132PDZ128rkz */ +/* Table16943 */ + 0x139b, /* VFMADD132SDZm_Intkz */ + 0x139f, /* VFMADD132SDZr_Intkz */ +/* Table16945 */ + 0x1583, /* VFMSUB132PDZ128mkz */ + 0x1586, /* VFMSUB132PDZ128rkz */ +/* Table16947 */ + 0x15c3, /* VFMSUB132SDZm_Intkz */ + 0x15c7, /* VFMSUB132SDZr_Intkz */ +/* Table16949 */ + 0x17ab, /* VFNMADD132PDZ128mkz */ + 0x17ae, /* VFNMADD132PDZ128rkz */ +/* Table16951 */ + 0x17eb, /* VFNMADD132SDZm_Intkz */ + 0x17ef, /* VFNMADD132SDZr_Intkz */ +/* Table16953 */ + 0x18f7, /* VFNMSUB132PDZ128mkz */ + 0x18fa, /* VFNMSUB132PDZ128rkz */ +/* Table16955 */ + 0x1937, /* VFNMSUB132SDZm_Intkz */ + 0x193b, /* VFNMSUB132SDZr_Intkz */ +/* Table16957 */ + 0x14eb, /* VFMADDSUB213PDZ128mkz */ + 0x14ee, /* VFMADDSUB213PDZ128rkz */ +/* Table16959 */ + 0x16f3, /* VFMSUBADD213PDZ128mkz */ + 0x16f6, /* VFMSUBADD213PDZ128rkz */ +/* Table16961 */ + 0x13bf, /* VFMADD213PDZ128mkz */ + 0x13c2, /* VFMADD213PDZ128rkz */ +/* Table16963 */ + 0x13ff, /* VFMADD213SDZm_Intkz */ + 0x1403, /* VFMADD213SDZr_Intkz */ +/* Table16965 */ + 0x15e7, /* VFMSUB213PDZ128mkz */ + 0x15ea, /* VFMSUB213PDZ128rkz */ +/* Table16967 */ + 0x1627, /* VFMSUB213SDZm_Intkz */ + 0x162b, /* VFMSUB213SDZr_Intkz */ +/* Table16969 */ + 0x180f, /* VFNMADD213PDZ128mkz */ + 0x1812, /* VFNMADD213PDZ128rkz */ +/* Table16971 */ + 0x184f, /* VFNMADD213SDZm_Intkz */ + 0x1853, /* VFNMADD213SDZr_Intkz */ +/* Table16973 */ + 0x195b, /* VFNMSUB213PDZ128mkz */ + 0x195e, /* VFNMSUB213PDZ128rkz */ +/* Table16975 */ + 0x199b, /* VFNMSUB213SDZm_Intkz */ + 0x199f, /* VFNMSUB213SDZr_Intkz */ +/* Table16977 */ + 0x2969, /* VPMADD52LUQZ128mkz */ + 0x296c, /* VPMADD52LUQZ128rkz */ +/* Table16979 */ + 0x294e, /* VPMADD52HUQZ128mkz */ + 0x2951, /* VPMADD52HUQZ128rkz */ +/* Table16981 */ + 0x152f, /* VFMADDSUB231PDZ128mkz */ + 0x1532, /* VFMADDSUB231PDZ128rkz */ +/* Table16983 */ + 0x1737, /* VFMSUBADD231PDZ128mkz */ + 0x173a, /* VFMSUBADD231PDZ128rkz */ +/* Table16985 */ + 0x1423, /* VFMADD231PDZ128mkz */ + 0x1426, /* VFMADD231PDZ128rkz */ +/* Table16987 */ + 0x1463, /* VFMADD231SDZm_Intkz */ + 0x1467, /* VFMADD231SDZr_Intkz */ +/* Table16989 */ + 0x164b, /* VFMSUB231PDZ128mkz */ + 0x164e, /* VFMSUB231PDZ128rkz */ +/* Table16991 */ + 0x168b, /* VFMSUB231SDZm_Intkz */ + 0x168f, /* VFMSUB231SDZr_Intkz */ +/* Table16993 */ + 0x1873, /* VFNMADD231PDZ128mkz */ + 0x1876, /* VFNMADD231PDZ128rkz */ +/* Table16995 */ + 0x18b3, /* VFNMADD231SDZm_Intkz */ + 0x18b7, /* VFNMADD231SDZr_Intkz */ +/* Table16997 */ + 0x19bf, /* VFNMSUB231PDZ128mkz */ + 0x19c2, /* VFNMSUB231PDZ128rkz */ +/* Table16999 */ + 0x19ff, /* VFNMSUB231SDZm_Intkz */ + 0x1a03, /* VFNMSUB231SDZr_Intkz */ +/* Table17001 */ + 0x257b, /* VPCONFLICTQZ128rmkz */ + 0x257e, /* VPCONFLICTQZ128rrkz */ +/* Table17003 */ + 0x378f, /* VRCP28SDZmkz */ + 0x3795, /* VRCP28SDZrkz */ +/* Table17005 */ + 0x38b3, /* VRSQRT28SDZmkz */ + 0x38b9, /* VRSQRT28SDZrkz */ +/* Table17007 */ + 0x0, /* */ + 0x2cdf, /* VPMOVUSWBZ256rrkz */ +/* Table17009 */ + 0x0, /* */ + 0x2c94, /* VPMOVUSDBZ256rrkz */ +/* Table17011 */ + 0x0, /* */ + 0x2cb2, /* VPMOVUSQBZ256rrkz */ +/* Table17013 */ + 0x0, /* */ + 0x2ca3, /* VPMOVUSDWZ256rrkz */ +/* Table17015 */ + 0x0, /* */ + 0x2cd0, /* VPMOVUSQWZ256rrkz */ +/* Table17017 */ + 0x0, /* */ + 0x2cc1, /* VPMOVUSQDZ256rrkz */ +/* Table17019 */ + 0x0, /* */ + 0x2c01, /* VPMOVSWBZ256rrkz */ +/* Table17021 */ + 0x0, /* */ + 0x2bb6, /* VPMOVSDBZ256rrkz */ +/* Table17023 */ + 0x0, /* */ + 0x2bd4, /* VPMOVSQBZ256rrkz */ +/* Table17025 */ + 0x0, /* */ + 0x2bc5, /* VPMOVSDWZ256rrkz */ +/* Table17027 */ + 0x0, /* */ + 0x2bf2, /* VPMOVSQWZ256rrkz */ +/* Table17029 */ + 0x0, /* */ + 0x2be3, /* VPMOVSQDZ256rrkz */ +/* Table17031 */ + 0x0, /* */ + 0x2cf1, /* VPMOVWBZ256rrkz */ +/* Table17033 */ + 0x0, /* */ + 0x2b5a, /* VPMOVDBZ256rrkz */ +/* Table17035 */ + 0x0, /* */ + 0x2b89, /* VPMOVQBZ256rrkz */ +/* Table17037 */ + 0x0, /* */ + 0x2b69, /* VPMOVDWZ256rrkz */ +/* Table17039 */ + 0x0, /* */ + 0x2ba7, /* VPMOVQWZ256rrkz */ +/* Table17041 */ + 0x0, /* */ + 0x2b98, /* VPMOVQDZ256rrkz */ +/* Table17043 */ + 0x315a, /* VPSHUFBZ256rmkz */ + 0x315d, /* VPSHUFBZ256rrkz */ +/* Table17045 */ + 0x2989, /* VPMADDUBSWZ256rmkz */ + 0x298c, /* VPMADDUBSWZ256rrkz */ +/* Table17047 */ + 0x2da4, /* VPMULHRSWZ256rmkz */ + 0x2da7, /* VPMULHRSWZ256rrkz */ +/* Table17049 */ + 0x2729, /* VPERMILPSZ256rmkz */ + 0x272c, /* VPERMILPSZ256rrkz */ +/* Table17051 */ + 0xeef, /* VCVTPH2PSZ256rmkz */ + 0xef2, /* VCVTPH2PSZ256rrkz */ +/* Table17053 */ + 0x2fae, /* VPRORVDZ256rmkz */ + 0x2fb1, /* VPRORVDZ256rrkz */ +/* Table17055 */ + 0x2f42, /* VPROLVDZ256rmkz */ + 0x2f45, /* VPROLVDZ256rrkz */ +/* Table17057 */ + 0x2770, /* VPERMPSZ256rmkz */ + 0x2773, /* VPERMPSZ256rrkz */ +/* Table17059 */ + 0xd42, /* VBROADCASTSSZ256mkz */ + 0xd45, /* VBROADCASTSSZ256rkz */ +/* Table17061 */ + 0xce9, /* VBROADCASTF32X2Z256mkz */ + 0xcec, /* VBROADCASTF32X2Z256rkz */ +/* Table17063 */ + 0xcf5, /* VBROADCASTF32X4Z256rmkz */ + 0x0, /* */ +/* Table17065 */ + 0x2037, /* VPABSBZ256rmkz */ + 0x203a, /* VPABSBZ256rrkz */ +/* Table17067 */ + 0x2087, /* VPABSWZ256rmkz */ + 0x208a, /* VPABSWZ256rrkz */ +/* Table17069 */ + 0x2053, /* VPABSDZ256rmkz */ + 0x2056, /* VPABSDZ256rrkz */ +/* Table17071 */ + 0x2c3d, /* VPMOVSXBWZ256rmkz */ + 0x2c40, /* VPMOVSXBWZ256rrkz */ +/* Table17073 */ + 0x2c11, /* VPMOVSXBDZ256rmkz */ + 0x2c14, /* VPMOVSXBDZ256rrkz */ +/* Table17075 */ + 0x2c27, /* VPMOVSXBQZ256rmkz */ + 0x2c2a, /* VPMOVSXBQZ256rrkz */ +/* Table17077 */ + 0x2c69, /* VPMOVSXWDZ256rmkz */ + 0x2c6c, /* VPMOVSXWDZ256rrkz */ +/* Table17079 */ + 0x2c7f, /* VPMOVSXWQZ256rmkz */ + 0x2c82, /* VPMOVSXWQZ256rrkz */ +/* Table17081 */ + 0x2c53, /* VPMOVSXDQZ256rmkz */ + 0x2c56, /* VPMOVSXDQZ256rrkz */ +/* Table17083 */ + 0x20d8, /* VPACKUSDWZ256rmkz */ + 0x20db, /* VPACKUSDWZ256rrkz */ +/* Table17085 */ + 0x38f7, /* VSCALEFPSZ256rmkz */ + 0x38fa, /* VSCALEFPSZ256rrkz */ +/* Table17087 */ + 0x2d2d, /* VPMOVZXBWZ256rmkz */ + 0x2d30, /* VPMOVZXBWZ256rrkz */ +/* Table17089 */ + 0x2d01, /* VPMOVZXBDZ256rmkz */ + 0x2d04, /* VPMOVZXBDZ256rrkz */ +/* Table17091 */ + 0x2d17, /* VPMOVZXBQZ256rmkz */ + 0x2d1a, /* VPMOVZXBQZ256rrkz */ +/* Table17093 */ + 0x2d59, /* VPMOVZXWDZ256rmkz */ + 0x2d5c, /* VPMOVZXWDZ256rrkz */ +/* Table17095 */ + 0x2d6f, /* VPMOVZXWQZ256rmkz */ + 0x2d72, /* VPMOVZXWQZ256rrkz */ +/* Table17097 */ + 0x2d43, /* VPMOVZXDQZ256rmkz */ + 0x2d46, /* VPMOVZXDQZ256rrkz */ +/* Table17099 */ + 0x261a, /* VPERMDZ256rmkz */ + 0x261d, /* VPERMDZ256rrkz */ +/* Table17101 */ + 0x2a89, /* VPMINSBZ256rmkz */ + 0x2a8c, /* VPMINSBZ256rrkz */ +/* Table17103 */ + 0x2aa5, /* VPMINSDZ256rmkz */ + 0x2aa8, /* VPMINSDZ256rrkz */ +/* Table17105 */ + 0x2b3f, /* VPMINUWZ256rmkz */ + 0x2b42, /* VPMINUWZ256rrkz */ +/* Table17107 */ + 0x2b0b, /* VPMINUDZ256rmkz */ + 0x2b0e, /* VPMINUDZ256rrkz */ +/* Table17109 */ + 0x29bd, /* VPMAXSBZ256rmkz */ + 0x29c0, /* VPMAXSBZ256rrkz */ +/* Table17111 */ + 0x29d9, /* VPMAXSDZ256rmkz */ + 0x29dc, /* VPMAXSDZ256rrkz */ +/* Table17113 */ + 0x2a73, /* VPMAXUWZ256rmkz */ + 0x2a76, /* VPMAXUWZ256rrkz */ +/* Table17115 */ + 0x2a3f, /* VPMAXUDZ256rmkz */ + 0x2a42, /* VPMAXUDZ256rrkz */ +/* Table17117 */ + 0x2dec, /* VPMULLDZ256rmkz */ + 0x2def, /* VPMULLDZ256rrkz */ +/* Table17119 */ + 0x1abc, /* VGETEXPPSZ256mkz */ + 0x1abf, /* VGETEXPPSZ256rkz */ +/* Table17121 */ + 0x2909, /* VPLZCNTDZ256rmkz */ + 0x290c, /* VPLZCNTDZ256rrkz */ +/* Table17123 */ + 0x33f9, /* VPSRLVDZ256rmkz */ + 0x33fc, /* VPSRLVDZ256rrkz */ +/* Table17125 */ + 0x3315, /* VPSRAVDZ256rmkz */ + 0x3318, /* VPSRAVDZ256rrkz */ +/* Table17127 */ + 0x323b, /* VPSLLVDZ256rmkz */ + 0x323e, /* VPSLLVDZ256rrkz */ +/* Table17129 */ + 0x375c, /* VRCP14PSZ256mkz */ + 0x375f, /* VRCP14PSZ256rkz */ +/* Table17131 */ + 0x3880, /* VRSQRT14PSZ256mkz */ + 0x3883, /* VRSQRT14PSZ256rkz */ +/* Table17133 */ + 0x25ba, /* VPDPBUSDZ256mkz */ + 0x25bd, /* VPDPBUSDZ256rkz */ +/* Table17135 */ + 0x259f, /* VPDPBUSDSZ256mkz */ + 0x25a2, /* VPDPBUSDSZ256rkz */ +/* Table17137 */ + 0x25f0, /* VPDPWSSDZ256mkz */ + 0x25f3, /* VPDPWSSDZ256rkz */ +/* Table17139 */ + 0x25d5, /* VPDPWSSDSZ256mkz */ + 0x25d8, /* VPDPWSSDSZ256rkz */ +/* Table17141 */ + 0x2e6e, /* VPOPCNTBZ256rmkz */ + 0x2e71, /* VPOPCNTBZ256rrkz */ +/* Table17143 */ + 0x2e86, /* VPOPCNTDZ256rmkz */ + 0x2e89, /* VPOPCNTDZ256rrkz */ +/* Table17145 */ + 0x2304, /* VPBROADCASTDZ256mkz */ + 0x2307, /* VPBROADCASTDZ256rkz */ +/* Table17147 */ + 0xd0e, /* VBROADCASTI32X2Z256mkz */ + 0xd11, /* VBROADCASTI32X2Z256rkz */ +/* Table17149 */ + 0xd1a, /* VBROADCASTI32X4Z256rmkz */ + 0x0, /* */ +/* Table17151 */ + 0x284d, /* VPEXPANDBZ256rmkz */ + 0x2850, /* VPEXPANDBZ256rrkz */ +/* Table17153 */ + 0x0, /* */ + 0x2510, /* VPCOMPRESSBZ256rrkz */ +/* Table17155 */ + 0x2299, /* VPBLENDMDZ256rmkz */ + 0x229c, /* VPBLENDMDZ256rrkz */ +/* Table17157 */ + 0xcc9, /* VBLENDMPSZ256rmkz */ + 0xccc, /* VBLENDMPSZ256rrkz */ +/* Table17159 */ + 0x2281, /* VPBLENDMBZ256rmkz */ + 0x2284, /* VPBLENDMBZ256rrkz */ +/* Table17161 */ + 0x305c, /* VPSHLDVDZ256mkz */ + 0x305f, /* VPSHLDVDZ256rkz */ +/* Table17163 */ + 0x30f8, /* VPSHRDVDZ256mkz */ + 0x30fb, /* VPSHRDVDZ256rkz */ +/* Table17165 */ + 0x262f, /* VPERMI2B256rmkz */ + 0x2632, /* VPERMI2B256rrkz */ +/* Table17167 */ + 0x2647, /* VPERMI2D256rmkz */ + 0x264a, /* VPERMI2D256rrkz */ +/* Table17169 */ + 0x267d, /* VPERMI2PS256rmkz */ + 0x2680, /* VPERMI2PS256rrkz */ +/* Table17171 */ + 0x22e5, /* VPBROADCASTBZ256mkz */ + 0x22e8, /* VPBROADCASTBZ256rkz */ +/* Table17173 */ + 0x2348, /* VPBROADCASTWZ256mkz */ + 0x234b, /* VPBROADCASTWZ256rkz */ +/* Table17175 */ + 0x0, /* */ + 0x22f4, /* VPBROADCASTBrZ256rkz */ +/* Table17177 */ + 0x0, /* */ + 0x2357, /* VPBROADCASTWrZ256rkz */ +/* Table17179 */ + 0x0, /* */ + 0x2313, /* VPBROADCASTDrZ256rkz */ +/* Table17181 */ + 0x27ab, /* VPERMT2B256rmkz */ + 0x27ae, /* VPERMT2B256rrkz */ +/* Table17183 */ + 0x27c3, /* VPERMT2D256rmkz */ + 0x27c6, /* VPERMT2D256rrkz */ +/* Table17185 */ + 0x27f9, /* VPERMT2PS256rmkz */ + 0x27fc, /* VPERMT2PS256rrkz */ +/* Table17187 */ + 0x12b8, /* VEXPANDPSZ256rmkz */ + 0x12bb, /* VEXPANDPSZ256rrkz */ +/* Table17189 */ + 0x285f, /* VPEXPANDDZ256rmkz */ + 0x2862, /* VPEXPANDDZ256rrkz */ +/* Table17191 */ + 0x0, /* */ + 0xe00, /* VCOMPRESSPSZ256rrkz */ +/* Table17193 */ + 0x0, /* */ + 0x251f, /* VPCOMPRESSDZ256rrkz */ +/* Table17195 */ + 0x2609, /* VPERMBZ256rmkz */ + 0x260c, /* VPERMBZ256rrkz */ +/* Table17197 */ + 0x14d2, /* VFMADDSUB132PSZ256mkz */ + 0x14d5, /* VFMADDSUB132PSZ256rkz */ +/* Table17199 */ + 0x16da, /* VFMSUBADD132PSZ256mkz */ + 0x16dd, /* VFMSUBADD132PSZ256rkz */ +/* Table17201 */ + 0x1386, /* VFMADD132PSZ256mkz */ + 0x1389, /* VFMADD132PSZ256rkz */ +/* Table17203 */ + 0x15ae, /* VFMSUB132PSZ256mkz */ + 0x15b1, /* VFMSUB132PSZ256rkz */ +/* Table17205 */ + 0x17d6, /* VFNMADD132PSZ256mkz */ + 0x17d9, /* VFNMADD132PSZ256rkz */ +/* Table17207 */ + 0x1922, /* VFNMSUB132PSZ256mkz */ + 0x1925, /* VFNMSUB132PSZ256rkz */ +/* Table17209 */ + 0x1516, /* VFMADDSUB213PSZ256mkz */ + 0x1519, /* VFMADDSUB213PSZ256rkz */ +/* Table17211 */ + 0x171e, /* VFMSUBADD213PSZ256mkz */ + 0x1721, /* VFMSUBADD213PSZ256rkz */ +/* Table17213 */ + 0x13ea, /* VFMADD213PSZ256mkz */ + 0x13ed, /* VFMADD213PSZ256rkz */ +/* Table17215 */ + 0x1612, /* VFMSUB213PSZ256mkz */ + 0x1615, /* VFMSUB213PSZ256rkz */ +/* Table17217 */ + 0x183a, /* VFNMADD213PSZ256mkz */ + 0x183d, /* VFNMADD213PSZ256rkz */ +/* Table17219 */ + 0x1986, /* VFNMSUB213PSZ256mkz */ + 0x1989, /* VFNMSUB213PSZ256rkz */ +/* Table17221 */ + 0x155a, /* VFMADDSUB231PSZ256mkz */ + 0x155d, /* VFMADDSUB231PSZ256rkz */ +/* Table17223 */ + 0x1762, /* VFMSUBADD231PSZ256mkz */ + 0x1765, /* VFMSUBADD231PSZ256rkz */ +/* Table17225 */ + 0x144e, /* VFMADD231PSZ256mkz */ + 0x1451, /* VFMADD231PSZ256rkz */ +/* Table17227 */ + 0x1676, /* VFMSUB231PSZ256mkz */ + 0x1679, /* VFMSUB231PSZ256rkz */ +/* Table17229 */ + 0x189e, /* VFNMADD231PSZ256mkz */ + 0x18a1, /* VFNMADD231PSZ256rkz */ +/* Table17231 */ + 0x19ea, /* VFNMSUB231PSZ256mkz */ + 0x19ed, /* VFNMSUB231PSZ256rkz */ +/* Table17233 */ + 0x2569, /* VPCONFLICTDZ256rmkz */ + 0x256c, /* VPCONFLICTDZ256rrkz */ +/* Table17235 */ + 0x1b74, /* VGF2P8MULBZ256rmkz */ + 0x1b77, /* VGF2P8MULBZ256rrkz */ +/* Table17237 */ + 0x26eb, /* VPERMILPDZ256rmkz */ + 0x26ee, /* VPERMILPDZ256rrkz */ +/* Table17239 */ + 0x342f, /* VPSRLVWZ256rmkz */ + 0x3432, /* VPSRLVWZ256rrkz */ +/* Table17241 */ + 0x3347, /* VPSRAVWZ256rmkz */ + 0x334a, /* VPSRAVWZ256rrkz */ +/* Table17243 */ + 0x3271, /* VPSLLVWZ256rmkz */ + 0x3274, /* VPSLLVWZ256rrkz */ +/* Table17245 */ + 0x2fc9, /* VPRORVQZ256rmkz */ + 0x2fcc, /* VPRORVQZ256rrkz */ +/* Table17247 */ + 0x2f5d, /* VPROLVQZ256rmkz */ + 0x2f60, /* VPROLVQZ256rrkz */ +/* Table17249 */ + 0x2753, /* VPERMPDZ256rmkz */ + 0x2756, /* VPERMPDZ256rrkz */ +/* Table17251 */ + 0xd2e, /* VBROADCASTSDZ256mkz */ + 0xd31, /* VBROADCASTSDZ256rkz */ +/* Table17253 */ + 0xcfe, /* VBROADCASTF64X2Z128rmkz */ + 0x0, /* */ +/* Table17255 */ + 0x2070, /* VPABSQZ256rmkz */ + 0x2073, /* VPABSQZ256rrkz */ +/* Table17257 */ + 0x2d8b, /* VPMULDQZ256rmkz */ + 0x2d8e, /* VPMULDQZ256rrkz */ +/* Table17259 */ + 0x38d9, /* VSCALEFPDZ256rmkz */ + 0x38dc, /* VSCALEFPDZ256rrkz */ +/* Table17261 */ + 0x278d, /* VPERMQZ256rmkz */ + 0x2790, /* VPERMQZ256rrkz */ +/* Table17263 */ + 0x2ac2, /* VPMINSQZ256rmkz */ + 0x2ac5, /* VPMINSQZ256rrkz */ +/* Table17265 */ + 0x2b28, /* VPMINUQZ256rmkz */ + 0x2b2b, /* VPMINUQZ256rrkz */ +/* Table17267 */ + 0x29f6, /* VPMAXSQZ256rmkz */ + 0x29f9, /* VPMAXSQZ256rrkz */ +/* Table17269 */ + 0x2a5c, /* VPMAXUQZ256rmkz */ + 0x2a5f, /* VPMAXUQZ256rrkz */ +/* Table17271 */ + 0x2e09, /* VPMULLQZ256rmkz */ + 0x2e0c, /* VPMULLQZ256rrkz */ +/* Table17273 */ + 0x1a9e, /* VGETEXPPDZ256mkz */ + 0x1aa1, /* VGETEXPPDZ256rkz */ +/* Table17275 */ + 0x2924, /* VPLZCNTQZ256rmkz */ + 0x2927, /* VPLZCNTQZ256rrkz */ +/* Table17277 */ + 0x3418, /* VPSRLVQZ256rmkz */ + 0x341b, /* VPSRLVQZ256rrkz */ +/* Table17279 */ + 0x3332, /* VPSRAVQZ256rmkz */ + 0x3335, /* VPSRAVQZ256rrkz */ +/* Table17281 */ + 0x325a, /* VPSLLVQZ256rmkz */ + 0x325d, /* VPSLLVQZ256rrkz */ +/* Table17283 */ + 0x3741, /* VRCP14PDZ256mkz */ + 0x3744, /* VRCP14PDZ256rkz */ +/* Table17285 */ + 0x3865, /* VRSQRT14PDZ256mkz */ + 0x3868, /* VRSQRT14PDZ256rkz */ +/* Table17287 */ + 0x2eb6, /* VPOPCNTWZ256rmkz */ + 0x2eb9, /* VPOPCNTWZ256rrkz */ +/* Table17289 */ + 0x2ea1, /* VPOPCNTQZ256rmkz */ + 0x2ea4, /* VPOPCNTQZ256rrkz */ +/* Table17291 */ + 0x2329, /* VPBROADCASTQZ256mkz */ + 0x232c, /* VPBROADCASTQZ256rkz */ +/* Table17293 */ + 0xd23, /* VBROADCASTI64X2Z128rmkz */ + 0x0, /* */ +/* Table17295 */ + 0x2883, /* VPEXPANDWZ256rmkz */ + 0x2886, /* VPEXPANDWZ256rrkz */ +/* Table17297 */ + 0x0, /* */ + 0x253d, /* VPCOMPRESSWZ256rrkz */ +/* Table17299 */ + 0x22b4, /* VPBLENDMQZ256rmkz */ + 0x22b7, /* VPBLENDMQZ256rrkz */ +/* Table17301 */ + 0xcae, /* VBLENDMPDZ256rmkz */ + 0xcb1, /* VBLENDMPDZ256rrkz */ +/* Table17303 */ + 0x22c9, /* VPBLENDMWZ256rmkz */ + 0x22cc, /* VPBLENDMWZ256rrkz */ +/* Table17305 */ + 0x308c, /* VPSHLDVWZ256mkz */ + 0x308f, /* VPSHLDVWZ256rkz */ +/* Table17307 */ + 0x3077, /* VPSHLDVQZ256mkz */ + 0x307a, /* VPSHLDVQZ256rkz */ +/* Table17309 */ + 0x3128, /* VPSHRDVWZ256mkz */ + 0x312b, /* VPSHRDVWZ256rkz */ +/* Table17311 */ + 0x3113, /* VPSHRDVQZ256mkz */ + 0x3116, /* VPSHRDVQZ256rkz */ +/* Table17313 */ + 0x26ad, /* VPERMI2W256rmkz */ + 0x26b0, /* VPERMI2W256rrkz */ +/* Table17315 */ + 0x2698, /* VPERMI2Q256rmkz */ + 0x269b, /* VPERMI2Q256rrkz */ +/* Table17317 */ + 0x2662, /* VPERMI2PD256rmkz */ + 0x2665, /* VPERMI2PD256rrkz */ +/* Table17319 */ + 0x0, /* */ + 0x2338, /* VPBROADCASTQrZ256rkz */ +/* Table17321 */ + 0x2829, /* VPERMT2W256rmkz */ + 0x282c, /* VPERMT2W256rrkz */ +/* Table17323 */ + 0x2814, /* VPERMT2Q256rmkz */ + 0x2817, /* VPERMT2Q256rrkz */ +/* Table17325 */ + 0x27de, /* VPERMT2PD256rmkz */ + 0x27e1, /* VPERMT2PD256rrkz */ +/* Table17327 */ + 0x2e3a, /* VPMULTISHIFTQBZ256rmkz */ + 0x2e3d, /* VPMULTISHIFTQBZ256rrkz */ +/* Table17329 */ + 0x12a6, /* VEXPANDPDZ256rmkz */ + 0x12a9, /* VEXPANDPDZ256rrkz */ +/* Table17331 */ + 0x2871, /* VPEXPANDQZ256rmkz */ + 0x2874, /* VPEXPANDQZ256rrkz */ +/* Table17333 */ + 0x0, /* */ + 0xdf1, /* VCOMPRESSPDZ256rrkz */ +/* Table17335 */ + 0x0, /* */ + 0x252e, /* VPCOMPRESSQZ256rrkz */ +/* Table17337 */ + 0x283b, /* VPERMWZ256rmkz */ + 0x283e, /* VPERMWZ256rrkz */ +/* Table17339 */ + 0x14b0, /* VFMADDSUB132PDZ256mkz */ + 0x14b3, /* VFMADDSUB132PDZ256rkz */ +/* Table17341 */ + 0x16b8, /* VFMSUBADD132PDZ256mkz */ + 0x16bb, /* VFMSUBADD132PDZ256rkz */ +/* Table17343 */ + 0x1364, /* VFMADD132PDZ256mkz */ + 0x1367, /* VFMADD132PDZ256rkz */ +/* Table17345 */ + 0x158c, /* VFMSUB132PDZ256mkz */ + 0x158f, /* VFMSUB132PDZ256rkz */ +/* Table17347 */ + 0x17b4, /* VFNMADD132PDZ256mkz */ + 0x17b7, /* VFNMADD132PDZ256rkz */ +/* Table17349 */ + 0x1900, /* VFNMSUB132PDZ256mkz */ + 0x1903, /* VFNMSUB132PDZ256rkz */ +/* Table17351 */ + 0x14f4, /* VFMADDSUB213PDZ256mkz */ + 0x14f7, /* VFMADDSUB213PDZ256rkz */ +/* Table17353 */ + 0x16fc, /* VFMSUBADD213PDZ256mkz */ + 0x16ff, /* VFMSUBADD213PDZ256rkz */ +/* Table17355 */ + 0x13c8, /* VFMADD213PDZ256mkz */ + 0x13cb, /* VFMADD213PDZ256rkz */ +/* Table17357 */ + 0x15f0, /* VFMSUB213PDZ256mkz */ + 0x15f3, /* VFMSUB213PDZ256rkz */ +/* Table17359 */ + 0x1818, /* VFNMADD213PDZ256mkz */ + 0x181b, /* VFNMADD213PDZ256rkz */ +/* Table17361 */ + 0x1964, /* VFNMSUB213PDZ256mkz */ + 0x1967, /* VFNMSUB213PDZ256rkz */ +/* Table17363 */ + 0x2972, /* VPMADD52LUQZ256mkz */ + 0x2975, /* VPMADD52LUQZ256rkz */ +/* Table17365 */ + 0x2957, /* VPMADD52HUQZ256mkz */ + 0x295a, /* VPMADD52HUQZ256rkz */ +/* Table17367 */ + 0x1538, /* VFMADDSUB231PDZ256mkz */ + 0x153b, /* VFMADDSUB231PDZ256rkz */ +/* Table17369 */ + 0x1740, /* VFMSUBADD231PDZ256mkz */ + 0x1743, /* VFMSUBADD231PDZ256rkz */ +/* Table17371 */ + 0x142c, /* VFMADD231PDZ256mkz */ + 0x142f, /* VFMADD231PDZ256rkz */ +/* Table17373 */ + 0x1654, /* VFMSUB231PDZ256mkz */ + 0x1657, /* VFMSUB231PDZ256rkz */ +/* Table17375 */ + 0x187c, /* VFNMADD231PDZ256mkz */ + 0x187f, /* VFNMADD231PDZ256rkz */ +/* Table17377 */ + 0x19c8, /* VFNMSUB231PDZ256mkz */ + 0x19cb, /* VFNMSUB231PDZ256rkz */ +/* Table17379 */ + 0x2584, /* VPCONFLICTQZ256rmkz */ + 0x2587, /* VPCONFLICTQZ256rrkz */ +/* Table17381 */ + 0x0, /* */ + 0x2ce4, /* VPMOVUSWBZrrkz */ +/* Table17383 */ + 0x0, /* */ + 0x2c99, /* VPMOVUSDBZrrkz */ +/* Table17385 */ + 0x0, /* */ + 0x2cb7, /* VPMOVUSQBZrrkz */ +/* Table17387 */ + 0x0, /* */ + 0x2ca8, /* VPMOVUSDWZrrkz */ +/* Table17389 */ + 0x0, /* */ + 0x2cd5, /* VPMOVUSQWZrrkz */ +/* Table17391 */ + 0x0, /* */ + 0x2cc6, /* VPMOVUSQDZrrkz */ +/* Table17393 */ + 0x0, /* */ + 0x2c06, /* VPMOVSWBZrrkz */ +/* Table17395 */ + 0x0, /* */ + 0x2bbb, /* VPMOVSDBZrrkz */ +/* Table17397 */ + 0x0, /* */ + 0x2bd9, /* VPMOVSQBZrrkz */ +/* Table17399 */ + 0x0, /* */ + 0x2bca, /* VPMOVSDWZrrkz */ +/* Table17401 */ + 0x0, /* */ + 0x2bf7, /* VPMOVSQWZrrkz */ +/* Table17403 */ + 0x0, /* */ + 0x2be8, /* VPMOVSQDZrrkz */ +/* Table17405 */ + 0x0, /* */ + 0x2cf6, /* VPMOVWBZrrkz */ +/* Table17407 */ + 0x0, /* */ + 0x2b5f, /* VPMOVDBZrrkz */ +/* Table17409 */ + 0x0, /* */ + 0x2b8e, /* VPMOVQBZrrkz */ +/* Table17411 */ + 0x0, /* */ + 0x2b6e, /* VPMOVDWZrrkz */ +/* Table17413 */ + 0x0, /* */ + 0x2bac, /* VPMOVQWZrrkz */ +/* Table17415 */ + 0x0, /* */ + 0x2b9d, /* VPMOVQDZrrkz */ +/* Table17417 */ + 0x202c, /* VP4DPWSSDrmkz */ + 0x0, /* */ +/* Table17419 */ + 0x2029, /* VP4DPWSSDSrmkz */ + 0x0, /* */ +/* Table17421 */ + 0xb4e, /* V4FMADDPSrmkz */ + 0x0, /* */ +/* Table17423 */ + 0xb54, /* V4FNMADDPSrmkz */ + 0x0, /* */ +/* Table17425 */ + 0x3160, /* VPSHUFBZrmkz */ + 0x3163, /* VPSHUFBZrrkz */ +/* Table17427 */ + 0x298f, /* VPMADDUBSWZrmkz */ + 0x2992, /* VPMADDUBSWZrrkz */ +/* Table17429 */ + 0x2daa, /* VPMULHRSWZrmkz */ + 0x2dad, /* VPMULHRSWZrrkz */ +/* Table17431 */ + 0x273b, /* VPERMILPSZrmkz */ + 0x273e, /* VPERMILPSZrrkz */ +/* Table17433 */ + 0xef5, /* VCVTPH2PSZrmkz */ + 0xefb, /* VCVTPH2PSZrrkz */ +/* Table17435 */ + 0x2fb7, /* VPRORVDZrmkz */ + 0x2fba, /* VPRORVDZrrkz */ +/* Table17437 */ + 0x2f4b, /* VPROLVDZrmkz */ + 0x2f4e, /* VPROLVDZrrkz */ +/* Table17439 */ + 0x2779, /* VPERMPSZrmkz */ + 0x277c, /* VPERMPSZrrkz */ +/* Table17441 */ + 0xd48, /* VBROADCASTSSZmkz */ + 0xd4b, /* VBROADCASTSSZrkz */ +/* Table17443 */ + 0xcef, /* VBROADCASTF32X2Zmkz */ + 0xcf2, /* VBROADCASTF32X2Zrkz */ +/* Table17445 */ + 0xcf8, /* VBROADCASTF32X4rmkz */ + 0x0, /* */ +/* Table17447 */ + 0xcfb, /* VBROADCASTF32X8rmkz */ + 0x0, /* */ +/* Table17449 */ + 0x203d, /* VPABSBZrmkz */ + 0x2040, /* VPABSBZrrkz */ +/* Table17451 */ + 0x208d, /* VPABSWZrmkz */ + 0x2090, /* VPABSWZrrkz */ +/* Table17453 */ + 0x205c, /* VPABSDZrmkz */ + 0x205f, /* VPABSDZrrkz */ +/* Table17455 */ + 0x2c43, /* VPMOVSXBWZrmkz */ + 0x2c46, /* VPMOVSXBWZrrkz */ +/* Table17457 */ + 0x2c17, /* VPMOVSXBDZrmkz */ + 0x2c1a, /* VPMOVSXBDZrrkz */ +/* Table17459 */ + 0x2c2d, /* VPMOVSXBQZrmkz */ + 0x2c30, /* VPMOVSXBQZrrkz */ +/* Table17461 */ + 0x2c6f, /* VPMOVSXWDZrmkz */ + 0x2c72, /* VPMOVSXWDZrrkz */ +/* Table17463 */ + 0x2c85, /* VPMOVSXWQZrmkz */ + 0x2c88, /* VPMOVSXWQZrrkz */ +/* Table17465 */ + 0x2c59, /* VPMOVSXDQZrmkz */ + 0x2c5c, /* VPMOVSXDQZrrkz */ +/* Table17467 */ + 0x20e1, /* VPACKUSDWZrmkz */ + 0x20e4, /* VPACKUSDWZrrkz */ +/* Table17469 */ + 0x3900, /* VSCALEFPSZrmkz */ + 0x3906, /* VSCALEFPSZrrkz */ +/* Table17471 */ + 0x2d33, /* VPMOVZXBWZrmkz */ + 0x2d36, /* VPMOVZXBWZrrkz */ +/* Table17473 */ + 0x2d07, /* VPMOVZXBDZrmkz */ + 0x2d0a, /* VPMOVZXBDZrrkz */ +/* Table17475 */ + 0x2d1d, /* VPMOVZXBQZrmkz */ + 0x2d20, /* VPMOVZXBQZrrkz */ +/* Table17477 */ + 0x2d5f, /* VPMOVZXWDZrmkz */ + 0x2d62, /* VPMOVZXWDZrrkz */ +/* Table17479 */ + 0x2d75, /* VPMOVZXWQZrmkz */ + 0x2d78, /* VPMOVZXWQZrrkz */ +/* Table17481 */ + 0x2d49, /* VPMOVZXDQZrmkz */ + 0x2d4c, /* VPMOVZXDQZrrkz */ +/* Table17483 */ + 0x2623, /* VPERMDZrmkz */ + 0x2626, /* VPERMDZrrkz */ +/* Table17485 */ + 0x2a8f, /* VPMINSBZrmkz */ + 0x2a92, /* VPMINSBZrrkz */ +/* Table17487 */ + 0x2aae, /* VPMINSDZrmkz */ + 0x2ab1, /* VPMINSDZrrkz */ +/* Table17489 */ + 0x2b45, /* VPMINUWZrmkz */ + 0x2b48, /* VPMINUWZrrkz */ +/* Table17491 */ + 0x2b14, /* VPMINUDZrmkz */ + 0x2b17, /* VPMINUDZrrkz */ +/* Table17493 */ + 0x29c3, /* VPMAXSBZrmkz */ + 0x29c6, /* VPMAXSBZrrkz */ +/* Table17495 */ + 0x29e2, /* VPMAXSDZrmkz */ + 0x29e5, /* VPMAXSDZrrkz */ +/* Table17497 */ + 0x2a79, /* VPMAXUWZrmkz */ + 0x2a7c, /* VPMAXUWZrrkz */ +/* Table17499 */ + 0x2a48, /* VPMAXUDZrmkz */ + 0x2a4b, /* VPMAXUDZrrkz */ +/* Table17501 */ + 0x2df5, /* VPMULLDZrmkz */ + 0x2df8, /* VPMULLDZrrkz */ +/* Table17503 */ + 0x1ac5, /* VGETEXPPSZmkz */ + 0x1acb, /* VGETEXPPSZrkz */ +/* Table17505 */ + 0x2912, /* VPLZCNTDZrmkz */ + 0x2915, /* VPLZCNTDZrrkz */ +/* Table17507 */ + 0x3402, /* VPSRLVDZrmkz */ + 0x3405, /* VPSRLVDZrrkz */ +/* Table17509 */ + 0x331e, /* VPSRAVDZrmkz */ + 0x3321, /* VPSRAVDZrrkz */ +/* Table17511 */ + 0x3244, /* VPSLLVDZrmkz */ + 0x3247, /* VPSLLVDZrrkz */ +/* Table17513 */ + 0x3765, /* VRCP14PSZmkz */ + 0x3768, /* VRCP14PSZrkz */ +/* Table17515 */ + 0x3889, /* VRSQRT14PSZmkz */ + 0x388c, /* VRSQRT14PSZrkz */ +/* Table17517 */ + 0x25c3, /* VPDPBUSDZmkz */ + 0x25c6, /* VPDPBUSDZrkz */ +/* Table17519 */ + 0x25a8, /* VPDPBUSDSZmkz */ + 0x25ab, /* VPDPBUSDSZrkz */ +/* Table17521 */ + 0x25f9, /* VPDPWSSDZmkz */ + 0x25fc, /* VPDPWSSDZrkz */ +/* Table17523 */ + 0x25de, /* VPDPWSSDSZmkz */ + 0x25e1, /* VPDPWSSDSZrkz */ +/* Table17525 */ + 0x2e74, /* VPOPCNTBZrmkz */ + 0x2e77, /* VPOPCNTBZrrkz */ +/* Table17527 */ + 0x2e8f, /* VPOPCNTDZrmkz */ + 0x2e92, /* VPOPCNTDZrrkz */ +/* Table17529 */ + 0x230a, /* VPBROADCASTDZmkz */ + 0x230d, /* VPBROADCASTDZrkz */ +/* Table17531 */ + 0xd14, /* VBROADCASTI32X2Zmkz */ + 0xd17, /* VBROADCASTI32X2Zrkz */ +/* Table17533 */ + 0xd1d, /* VBROADCASTI32X4rmkz */ + 0x0, /* */ +/* Table17535 */ + 0xd20, /* VBROADCASTI32X8rmkz */ + 0x0, /* */ +/* Table17537 */ + 0x2853, /* VPEXPANDBZrmkz */ + 0x2856, /* VPEXPANDBZrrkz */ +/* Table17539 */ + 0x0, /* */ + 0x2515, /* VPCOMPRESSBZrrkz */ +/* Table17541 */ + 0x22a2, /* VPBLENDMDZrmkz */ + 0x22a5, /* VPBLENDMDZrrkz */ +/* Table17543 */ + 0xcd2, /* VBLENDMPSZrmkz */ + 0xcd5, /* VBLENDMPSZrrkz */ +/* Table17545 */ + 0x2287, /* VPBLENDMBZrmkz */ + 0x228a, /* VPBLENDMBZrrkz */ +/* Table17547 */ + 0x3065, /* VPSHLDVDZmkz */ + 0x3068, /* VPSHLDVDZrkz */ +/* Table17549 */ + 0x3101, /* VPSHRDVDZmkz */ + 0x3104, /* VPSHRDVDZrkz */ +/* Table17551 */ + 0x2635, /* VPERMI2Brmkz */ + 0x2638, /* VPERMI2Brrkz */ +/* Table17553 */ + 0x2650, /* VPERMI2Drmkz */ + 0x2653, /* VPERMI2Drrkz */ +/* Table17555 */ + 0x2686, /* VPERMI2PSrmkz */ + 0x2689, /* VPERMI2PSrrkz */ +/* Table17557 */ + 0x22eb, /* VPBROADCASTBZmkz */ + 0x22ee, /* VPBROADCASTBZrkz */ +/* Table17559 */ + 0x234e, /* VPBROADCASTWZmkz */ + 0x2351, /* VPBROADCASTWZrkz */ +/* Table17561 */ + 0x0, /* */ + 0x22f7, /* VPBROADCASTBrZrkz */ +/* Table17563 */ + 0x0, /* */ + 0x235a, /* VPBROADCASTWrZrkz */ +/* Table17565 */ + 0x0, /* */ + 0x2316, /* VPBROADCASTDrZrkz */ +/* Table17567 */ + 0x27b1, /* VPERMT2Brmkz */ + 0x27b4, /* VPERMT2Brrkz */ +/* Table17569 */ + 0x27cc, /* VPERMT2Drmkz */ + 0x27cf, /* VPERMT2Drrkz */ +/* Table17571 */ + 0x2802, /* VPERMT2PSrmkz */ + 0x2805, /* VPERMT2PSrrkz */ +/* Table17573 */ + 0x12be, /* VEXPANDPSZrmkz */ + 0x12c1, /* VEXPANDPSZrrkz */ +/* Table17575 */ + 0x2865, /* VPEXPANDDZrmkz */ + 0x2868, /* VPEXPANDDZrrkz */ +/* Table17577 */ + 0x0, /* */ + 0xe05, /* VCOMPRESSPSZrrkz */ +/* Table17579 */ + 0x0, /* */ + 0x2524, /* VPCOMPRESSDZrrkz */ +/* Table17581 */ + 0x260f, /* VPERMBZrmkz */ + 0x2612, /* VPERMBZrrkz */ +/* Table17583 */ + 0x14db, /* VFMADDSUB132PSZmkz */ + 0x14e1, /* VFMADDSUB132PSZrkz */ +/* Table17585 */ + 0x16e3, /* VFMSUBADD132PSZmkz */ + 0x16e9, /* VFMSUBADD132PSZrkz */ +/* Table17587 */ + 0x138f, /* VFMADD132PSZmkz */ + 0x1395, /* VFMADD132PSZrkz */ +/* Table17589 */ + 0x15b7, /* VFMSUB132PSZmkz */ + 0x15bd, /* VFMSUB132PSZrkz */ +/* Table17591 */ + 0x17df, /* VFNMADD132PSZmkz */ + 0x17e5, /* VFNMADD132PSZrkz */ +/* Table17593 */ + 0x192b, /* VFNMSUB132PSZmkz */ + 0x1931, /* VFNMSUB132PSZrkz */ +/* Table17595 */ + 0x151f, /* VFMADDSUB213PSZmkz */ + 0x1525, /* VFMADDSUB213PSZrkz */ +/* Table17597 */ + 0x1727, /* VFMSUBADD213PSZmkz */ + 0x172d, /* VFMSUBADD213PSZrkz */ +/* Table17599 */ + 0x13f3, /* VFMADD213PSZmkz */ + 0x13f9, /* VFMADD213PSZrkz */ +/* Table17601 */ + 0x161b, /* VFMSUB213PSZmkz */ + 0x1621, /* VFMSUB213PSZrkz */ +/* Table17603 */ + 0x1843, /* VFNMADD213PSZmkz */ + 0x1849, /* VFNMADD213PSZrkz */ +/* Table17605 */ + 0x198f, /* VFNMSUB213PSZmkz */ + 0x1995, /* VFNMSUB213PSZrkz */ +/* Table17607 */ + 0x1563, /* VFMADDSUB231PSZmkz */ + 0x1569, /* VFMADDSUB231PSZrkz */ +/* Table17609 */ + 0x176b, /* VFMSUBADD231PSZmkz */ + 0x1771, /* VFMSUBADD231PSZrkz */ +/* Table17611 */ + 0x1457, /* VFMADD231PSZmkz */ + 0x145d, /* VFMADD231PSZrkz */ +/* Table17613 */ + 0x167f, /* VFMSUB231PSZmkz */ + 0x1685, /* VFMSUB231PSZrkz */ +/* Table17615 */ + 0x18a7, /* VFNMADD231PSZmkz */ + 0x18ad, /* VFNMADD231PSZrkz */ +/* Table17617 */ + 0x19f3, /* VFNMSUB231PSZmkz */ + 0x19f9, /* VFNMSUB231PSZrkz */ +/* Table17619 */ + 0x2572, /* VPCONFLICTDZrmkz */ + 0x2575, /* VPCONFLICTDZrrkz */ +/* Table17621 */ + 0x1297, /* VEXP2PSZmkz */ + 0x129d, /* VEXP2PSZrkz */ +/* Table17623 */ + 0x3786, /* VRCP28PSZmkz */ + 0x378c, /* VRCP28PSZrkz */ +/* Table17625 */ + 0x38aa, /* VRSQRT28PSZmkz */ + 0x38b0, /* VRSQRT28PSZrkz */ +/* Table17627 */ + 0x1b7a, /* VGF2P8MULBZrmkz */ + 0x1b7d, /* VGF2P8MULBZrrkz */ +/* Table17629 */ + 0x26fd, /* VPERMILPDZrmkz */ + 0x2700, /* VPERMILPDZrrkz */ +/* Table17631 */ + 0x3435, /* VPSRLVWZrmkz */ + 0x3438, /* VPSRLVWZrrkz */ +/* Table17633 */ + 0x334d, /* VPSRAVWZrmkz */ + 0x3350, /* VPSRAVWZrrkz */ +/* Table17635 */ + 0x3277, /* VPSLLVWZrmkz */ + 0x327a, /* VPSLLVWZrrkz */ +/* Table17637 */ + 0x2fd2, /* VPRORVQZrmkz */ + 0x2fd5, /* VPRORVQZrrkz */ +/* Table17639 */ + 0x2f66, /* VPROLVQZrmkz */ + 0x2f69, /* VPROLVQZrrkz */ +/* Table17641 */ + 0x2765, /* VPERMPDZrmkz */ + 0x2768, /* VPERMPDZrrkz */ +/* Table17643 */ + 0xd34, /* VBROADCASTSDZmkz */ + 0xd37, /* VBROADCASTSDZrkz */ +/* Table17645 */ + 0xd01, /* VBROADCASTF64X2rmkz */ + 0x0, /* */ +/* Table17647 */ + 0xd04, /* VBROADCASTF64X4rmkz */ + 0x0, /* */ +/* Table17649 */ + 0x2079, /* VPABSQZrmkz */ + 0x207c, /* VPABSQZrrkz */ +/* Table17651 */ + 0x2d94, /* VPMULDQZrmkz */ + 0x2d97, /* VPMULDQZrrkz */ +/* Table17653 */ + 0x38e2, /* VSCALEFPDZrmkz */ + 0x38e8, /* VSCALEFPDZrrkz */ +/* Table17655 */ + 0x279f, /* VPERMQZrmkz */ + 0x27a2, /* VPERMQZrrkz */ +/* Table17657 */ + 0x2acb, /* VPMINSQZrmkz */ + 0x2ace, /* VPMINSQZrrkz */ +/* Table17659 */ + 0x2b31, /* VPMINUQZrmkz */ + 0x2b34, /* VPMINUQZrrkz */ +/* Table17661 */ + 0x29ff, /* VPMAXSQZrmkz */ + 0x2a02, /* VPMAXSQZrrkz */ +/* Table17663 */ + 0x2a65, /* VPMAXUQZrmkz */ + 0x2a68, /* VPMAXUQZrrkz */ +/* Table17665 */ + 0x2e12, /* VPMULLQZrmkz */ + 0x2e15, /* VPMULLQZrrkz */ +/* Table17667 */ + 0x1aa7, /* VGETEXPPDZmkz */ + 0x1aad, /* VGETEXPPDZrkz */ +/* Table17669 */ + 0x292d, /* VPLZCNTQZrmkz */ + 0x2930, /* VPLZCNTQZrrkz */ +/* Table17671 */ + 0x3421, /* VPSRLVQZrmkz */ + 0x3424, /* VPSRLVQZrrkz */ +/* Table17673 */ + 0x333b, /* VPSRAVQZrmkz */ + 0x333e, /* VPSRAVQZrrkz */ +/* Table17675 */ + 0x3263, /* VPSLLVQZrmkz */ + 0x3266, /* VPSLLVQZrrkz */ +/* Table17677 */ + 0x374a, /* VRCP14PDZmkz */ + 0x374d, /* VRCP14PDZrkz */ +/* Table17679 */ + 0x386e, /* VRSQRT14PDZmkz */ + 0x3871, /* VRSQRT14PDZrkz */ +/* Table17681 */ + 0x2ebc, /* VPOPCNTWZrmkz */ + 0x2ebf, /* VPOPCNTWZrrkz */ +/* Table17683 */ + 0x2eaa, /* VPOPCNTQZrmkz */ + 0x2ead, /* VPOPCNTQZrrkz */ +/* Table17685 */ + 0x232f, /* VPBROADCASTQZmkz */ + 0x2332, /* VPBROADCASTQZrkz */ +/* Table17687 */ + 0xd26, /* VBROADCASTI64X2rmkz */ + 0x0, /* */ +/* Table17689 */ + 0xd29, /* VBROADCASTI64X4rmkz */ + 0x0, /* */ +/* Table17691 */ + 0x2889, /* VPEXPANDWZrmkz */ + 0x288c, /* VPEXPANDWZrrkz */ +/* Table17693 */ + 0x0, /* */ + 0x2542, /* VPCOMPRESSWZrrkz */ +/* Table17695 */ + 0x22bd, /* VPBLENDMQZrmkz */ + 0x22c0, /* VPBLENDMQZrrkz */ +/* Table17697 */ + 0xcb7, /* VBLENDMPDZrmkz */ + 0xcba, /* VBLENDMPDZrrkz */ +/* Table17699 */ + 0x22cf, /* VPBLENDMWZrmkz */ + 0x22d2, /* VPBLENDMWZrrkz */ +/* Table17701 */ + 0x3092, /* VPSHLDVWZmkz */ + 0x3095, /* VPSHLDVWZrkz */ +/* Table17703 */ + 0x3080, /* VPSHLDVQZmkz */ + 0x3083, /* VPSHLDVQZrkz */ +/* Table17705 */ + 0x312e, /* VPSHRDVWZmkz */ + 0x3131, /* VPSHRDVWZrkz */ +/* Table17707 */ + 0x311c, /* VPSHRDVQZmkz */ + 0x311f, /* VPSHRDVQZrkz */ +/* Table17709 */ + 0x26b3, /* VPERMI2Wrmkz */ + 0x26b6, /* VPERMI2Wrrkz */ +/* Table17711 */ + 0x26a1, /* VPERMI2Qrmkz */ + 0x26a4, /* VPERMI2Qrrkz */ +/* Table17713 */ + 0x266b, /* VPERMI2PDrmkz */ + 0x266e, /* VPERMI2PDrrkz */ +/* Table17715 */ + 0x0, /* */ + 0x233b, /* VPBROADCASTQrZrkz */ +/* Table17717 */ + 0x282f, /* VPERMT2Wrmkz */ + 0x2832, /* VPERMT2Wrrkz */ +/* Table17719 */ + 0x281d, /* VPERMT2Qrmkz */ + 0x2820, /* VPERMT2Qrrkz */ +/* Table17721 */ + 0x27e7, /* VPERMT2PDrmkz */ + 0x27ea, /* VPERMT2PDrrkz */ +/* Table17723 */ + 0x2e43, /* VPMULTISHIFTQBZrmkz */ + 0x2e46, /* VPMULTISHIFTQBZrrkz */ +/* Table17725 */ + 0x12ac, /* VEXPANDPDZrmkz */ + 0x12af, /* VEXPANDPDZrrkz */ +/* Table17727 */ + 0x2877, /* VPEXPANDQZrmkz */ + 0x287a, /* VPEXPANDQZrrkz */ +/* Table17729 */ + 0x0, /* */ + 0xdf6, /* VCOMPRESSPDZrrkz */ +/* Table17731 */ + 0x0, /* */ + 0x2533, /* VPCOMPRESSQZrrkz */ +/* Table17733 */ + 0x2841, /* VPERMWZrmkz */ + 0x2844, /* VPERMWZrrkz */ +/* Table17735 */ + 0x14b9, /* VFMADDSUB132PDZmkz */ + 0x14bf, /* VFMADDSUB132PDZrkz */ +/* Table17737 */ + 0x16c1, /* VFMSUBADD132PDZmkz */ + 0x16c7, /* VFMSUBADD132PDZrkz */ +/* Table17739 */ + 0x136d, /* VFMADD132PDZmkz */ + 0x1373, /* VFMADD132PDZrkz */ +/* Table17741 */ + 0x1595, /* VFMSUB132PDZmkz */ + 0x159b, /* VFMSUB132PDZrkz */ +/* Table17743 */ + 0x17bd, /* VFNMADD132PDZmkz */ + 0x17c3, /* VFNMADD132PDZrkz */ +/* Table17745 */ + 0x1909, /* VFNMSUB132PDZmkz */ + 0x190f, /* VFNMSUB132PDZrkz */ +/* Table17747 */ + 0x14fd, /* VFMADDSUB213PDZmkz */ + 0x1503, /* VFMADDSUB213PDZrkz */ +/* Table17749 */ + 0x1705, /* VFMSUBADD213PDZmkz */ + 0x170b, /* VFMSUBADD213PDZrkz */ +/* Table17751 */ + 0x13d1, /* VFMADD213PDZmkz */ + 0x13d7, /* VFMADD213PDZrkz */ +/* Table17753 */ + 0x15f9, /* VFMSUB213PDZmkz */ + 0x15ff, /* VFMSUB213PDZrkz */ +/* Table17755 */ + 0x1821, /* VFNMADD213PDZmkz */ + 0x1827, /* VFNMADD213PDZrkz */ +/* Table17757 */ + 0x196d, /* VFNMSUB213PDZmkz */ + 0x1973, /* VFNMSUB213PDZrkz */ +/* Table17759 */ + 0x297b, /* VPMADD52LUQZmkz */ + 0x297e, /* VPMADD52LUQZrkz */ +/* Table17761 */ + 0x2960, /* VPMADD52HUQZmkz */ + 0x2963, /* VPMADD52HUQZrkz */ +/* Table17763 */ + 0x1541, /* VFMADDSUB231PDZmkz */ + 0x1547, /* VFMADDSUB231PDZrkz */ +/* Table17765 */ + 0x1749, /* VFMSUBADD231PDZmkz */ + 0x174f, /* VFMSUBADD231PDZrkz */ +/* Table17767 */ + 0x1435, /* VFMADD231PDZmkz */ + 0x143b, /* VFMADD231PDZrkz */ +/* Table17769 */ + 0x165d, /* VFMSUB231PDZmkz */ + 0x1663, /* VFMSUB231PDZrkz */ +/* Table17771 */ + 0x1885, /* VFNMADD231PDZmkz */ + 0x188b, /* VFNMADD231PDZrkz */ +/* Table17773 */ + 0x19d1, /* VFNMSUB231PDZmkz */ + 0x19d7, /* VFNMSUB231PDZrkz */ +/* Table17775 */ + 0x258d, /* VPCONFLICTQZrmkz */ + 0x2590, /* VPCONFLICTQZrrkz */ +/* Table17777 */ + 0x128b, /* VEXP2PDZmkz */ + 0x1291, /* VEXP2PDZrkz */ +/* Table17779 */ + 0x377a, /* VRCP28PDZmkz */ + 0x3780, /* VRCP28PDZrkz */ +/* Table17781 */ + 0x389e, /* VRSQRT28PDZmkz */ + 0x38a4, /* VRSQRT28PDZrkz */ +/* Table17783 */ + 0x588, /* MMX_PALIGNRrmi */ + 0x589, /* MMX_PALIGNRrri */ +/* Table17785 */ + 0x9ff, /* SHA1RNDS4rmi */ + 0xa00, /* SHA1RNDS4rri */ +/* Table17787 */ + 0x963, /* ROUNDPSm */ + 0x964, /* ROUNDPSr */ +/* Table17789 */ + 0x961, /* ROUNDPDm */ + 0x962, /* ROUNDPDr */ +/* Table17791 */ + 0x969, /* ROUNDSSm */ + 0x96b, /* ROUNDSSr */ +/* Table17793 */ + 0x965, /* ROUNDSDm */ + 0x967, /* ROUNDSDr */ +/* Table17795 */ + 0x16b, /* BLENDPSrmi */ + 0x16c, /* BLENDPSrri */ +/* Table17797 */ + 0x169, /* BLENDPDrmi */ + 0x16a, /* BLENDPDrri */ +/* Table17799 */ + 0x789, /* PBLENDWrmi */ + 0x78a, /* PBLENDWrri */ +/* Table17801 */ + 0x77a, /* PALIGNRrmi */ + 0x77b, /* PALIGNRrri */ +/* Table17803 */ + 0x7ae, /* PEXTRBmr */ + 0x7af, /* PEXTRBrr */ +/* Table17805 */ + 0x7b4, /* PEXTRWmr */ + 0x7b6, /* PEXTRWrr_REV */ +/* Table17807 */ + 0x7b0, /* PEXTRDmr */ + 0x7b1, /* PEXTRDrr */ +/* Table17809 */ + 0x379, /* EXTRACTPSmr */ + 0x37a, /* EXTRACTPSrr */ +/* Table17811 */ + 0x7ef, /* PINSRBrm */ + 0x7f0, /* PINSRBrr */ +/* Table17813 */ + 0x40c, /* INSERTPSrm */ + 0x40d, /* INSERTPSrr */ +/* Table17815 */ + 0x7f1, /* PINSRDrm */ + 0x7f2, /* PINSRDrr */ +/* Table17817 */ + 0x371, /* DPPSrmi */ + 0x372, /* DPPSrri */ +/* Table17819 */ + 0x36f, /* DPPDrmi */ + 0x370, /* DPPDrri */ +/* Table17821 */ + 0x6cb, /* MPSADBWrmi */ + 0x6cc, /* MPSADBWrri */ +/* Table17823 */ + 0x78b, /* PCLMULQDQrm */ + 0x78c, /* PCLMULQDQrr */ +/* Table17825 */ + 0x797, /* PCMPESTRMrm */ + 0x798, /* PCMPESTRMrr */ +/* Table17827 */ + 0x795, /* PCMPESTRIrm */ + 0x796, /* PCMPESTRIrr */ +/* Table17829 */ + 0x7a3, /* PCMPISTRMrm */ + 0x7a4, /* PCMPISTRMrr */ +/* Table17831 */ + 0x7a1, /* PCMPISTRIrm */ + 0x7a2, /* PCMPISTRIrr */ +/* Table17833 */ + 0x3be, /* GF2P8AFFINEQBrmi */ + 0x3bf, /* GF2P8AFFINEQBrri */ +/* Table17835 */ + 0x3bc, /* GF2P8AFFINEINVQBrmi */ + 0x3bd, /* GF2P8AFFINEINVQBrri */ +/* Table17837 */ + 0x119, /* AESKEYGENASSIST128rm */ + 0x11a, /* AESKEYGENASSIST128rr */ +/* Table17839 */ + 0x7b2, /* PEXTRQmr */ + 0x7b3, /* PEXTRQrr */ +/* Table17841 */ + 0x7f3, /* PINSRQrm */ + 0x7f4, /* PINSRQrr */ +/* Table17843 */ + 0x95d, /* RORX32mi */ + 0x95e, /* RORX32ri */ +/* Table17845 */ + 0x2277, /* VPBLENDDrmi */ + 0x2278, /* VPBLENDDrri */ +/* Table17847 */ + 0x273f, /* VPERMILPSmi */ + 0x2740, /* VPERMILPSri */ +/* Table17849 */ + 0x2701, /* VPERMILPDmi */ + 0x2702, /* VPERMILPDri */ +/* Table17851 */ + 0x384d, /* VROUNDPSm */ + 0x384e, /* VROUNDPSr */ +/* Table17853 */ + 0x3849, /* VROUNDPDm */ + 0x384a, /* VROUNDPDr */ +/* Table17855 */ + 0x3853, /* VROUNDSSm */ + 0x3855, /* VROUNDSSr */ +/* Table17857 */ + 0x384f, /* VROUNDSDm */ + 0x3851, /* VROUNDSDr */ +/* Table17859 */ + 0xcdc, /* VBLENDPSrmi */ + 0xcdd, /* VBLENDPSrri */ +/* Table17861 */ + 0xcd8, /* VBLENDPDrmi */ + 0xcd9, /* VBLENDPDrri */ +/* Table17863 */ + 0x22d9, /* VPBLENDWrmi */ + 0x22da, /* VPBLENDWrri */ +/* Table17865 */ + 0x21d3, /* VPALIGNRrmi */ + 0x21d4, /* VPALIGNRrri */ +/* Table17867 */ + 0x288f, /* VPEXTRBmr */ + 0x2890, /* VPEXTRBrr */ +/* Table17869 */ + 0x289c, /* VPEXTRWmr */ + 0x289e, /* VPEXTRWrr_REV */ +/* Table17871 */ + 0x2893, /* VPEXTRDmr */ + 0x2894, /* VPEXTRDrr */ +/* Table17873 */ + 0x1304, /* VEXTRACTPSmr */ + 0x1305, /* VEXTRACTPSrr */ +/* Table17875 */ + 0xf56, /* VCVTPS2PHmr */ + 0xf57, /* VCVTPS2PHrr */ +/* Table17877 */ + 0x28ed, /* VPINSRBrm */ + 0x28ee, /* VPINSRBrr */ +/* Table17879 */ + 0x1bde, /* VINSERTPSrm */ + 0x1bdf, /* VINSERTPSrr */ +/* Table17881 */ + 0x28f1, /* VPINSRDrm */ + 0x28f2, /* VPINSRDrr */ +/* Table17883 */ + 0x0, /* */ + 0x4af, /* KSHIFTRBri */ +/* Table17885 */ + 0x0, /* */ + 0x4b0, /* KSHIFTRDri */ +/* Table17887 */ + 0x0, /* */ + 0x4ab, /* KSHIFTLBri */ +/* Table17889 */ + 0x0, /* */ + 0x4ac, /* KSHIFTLDri */ +/* Table17891 */ + 0x1280, /* VDPPSrmi */ + 0x1281, /* VDPPSrri */ +/* Table17893 */ + 0x127c, /* VDPPDrmi */ + 0x127d, /* VDPPDrri */ +/* Table17895 */ + 0x1f74, /* VMPSADBWrmi */ + 0x1f75, /* VMPSADBWrri */ +/* Table17897 */ + 0x2365, /* VPCLMULQDQrm */ + 0x2366, /* VPCLMULQDQrr */ +/* Table17899 */ + 0x26c3, /* VPERMIL2PSmr */ + 0x26c5, /* VPERMIL2PSrr */ +/* Table17901 */ + 0x26bb, /* VPERMIL2PDmr */ + 0x26bd, /* VPERMIL2PDrr */ +/* Table17903 */ + 0xce4, /* VBLENDVPSrm */ + 0xce5, /* VBLENDVPSrr */ +/* Table17905 */ + 0xce0, /* VBLENDVPDrm */ + 0xce1, /* VBLENDVPDrr */ +/* Table17907 */ + 0x22d5, /* VPBLENDVBrm */ + 0x22d6, /* VPBLENDVBrr */ +/* Table17909 */ + 0x1578, /* VFMADDSUBPS4mr */ + 0x157b, /* VFMADDSUBPS4rr_REV */ +/* Table17911 */ + 0x1570, /* VFMADDSUBPD4mr */ + 0x1573, /* VFMADDSUBPD4rr_REV */ +/* Table17913 */ + 0x1780, /* VFMSUBADDPS4mr */ + 0x1783, /* VFMSUBADDPS4rr_REV */ +/* Table17915 */ + 0x1778, /* VFMSUBADDPD4mr */ + 0x177b, /* VFMSUBADDPD4rr_REV */ +/* Table17917 */ + 0x23f9, /* VPCMPESTRMrm */ + 0x23fa, /* VPCMPESTRMrr */ +/* Table17919 */ + 0x23f7, /* VPCMPESTRIrm */ + 0x23f8, /* VPCMPESTRIrr */ +/* Table17921 */ + 0x2449, /* VPCMPISTRMrm */ + 0x244a, /* VPCMPISTRMrr */ +/* Table17923 */ + 0x2447, /* VPCMPISTRIrm */ + 0x2448, /* VPCMPISTRIrr */ +/* Table17925 */ + 0x148c, /* VFMADDPS4mr */ + 0x148f, /* VFMADDPS4rr_REV */ +/* Table17927 */ + 0x1484, /* VFMADDPD4mr */ + 0x1487, /* VFMADDPD4rr_REV */ +/* Table17929 */ + 0x1498, /* VFMADDSS4mr */ + 0x149f, /* VFMADDSS4rr_REV */ +/* Table17931 */ + 0x1490, /* VFMADDSD4mr */ + 0x1497, /* VFMADDSD4rr_REV */ +/* Table17933 */ + 0x1790, /* VFMSUBPS4mr */ + 0x1793, /* VFMSUBPS4rr_REV */ +/* Table17935 */ + 0x1788, /* VFMSUBPD4mr */ + 0x178b, /* VFMSUBPD4rr_REV */ +/* Table17937 */ + 0x179c, /* VFMSUBSS4mr */ + 0x17a3, /* VFMSUBSS4rr_REV */ +/* Table17939 */ + 0x1794, /* VFMSUBSD4mr */ + 0x179b, /* VFMSUBSD4rr_REV */ +/* Table17941 */ + 0x18dc, /* VFNMADDPS4mr */ + 0x18df, /* VFNMADDPS4rr_REV */ +/* Table17943 */ + 0x18d4, /* VFNMADDPD4mr */ + 0x18d7, /* VFNMADDPD4rr_REV */ +/* Table17945 */ + 0x18e8, /* VFNMADDSS4mr */ + 0x18ef, /* VFNMADDSS4rr_REV */ +/* Table17947 */ + 0x18e0, /* VFNMADDSD4mr */ + 0x18e7, /* VFNMADDSD4rr_REV */ +/* Table17949 */ + 0x1a28, /* VFNMSUBPS4mr */ + 0x1a2b, /* VFNMSUBPS4rr_REV */ +/* Table17951 */ + 0x1a20, /* VFNMSUBPD4mr */ + 0x1a23, /* VFNMSUBPD4rr_REV */ +/* Table17953 */ + 0x1a34, /* VFNMSUBSS4mr */ + 0x1a3b, /* VFNMSUBSS4rr_REV */ +/* Table17955 */ + 0x1a2c, /* VFNMSUBSD4mr */ + 0x1a33, /* VFNMSUBSD4rr_REV */ +/* Table17957 */ + 0xbec, /* VAESKEYGENASSIST128rm */ + 0xbed, /* VAESKEYGENASSIST128rr */ +/* Table17959 */ + 0x95f, /* RORX64mi */ + 0x960, /* RORX64ri */ +/* Table17961 */ + 0x2897, /* VPEXTRQmr */ + 0x2898, /* VPEXTRQrr */ +/* Table17963 */ + 0x28f5, /* VPINSRQrm */ + 0x28f6, /* VPINSRQrr */ +/* Table17965 */ + 0x0, /* */ + 0x4b2, /* KSHIFTRWri */ +/* Table17967 */ + 0x0, /* */ + 0x4b1, /* KSHIFTRQri */ +/* Table17969 */ + 0x0, /* */ + 0x4ae, /* KSHIFTLWri */ +/* Table17971 */ + 0x0, /* */ + 0x4ad, /* KSHIFTLQri */ +/* Table17973 */ + 0x26c4, /* VPERMIL2PSrm */ + 0x26c6, /* VPERMIL2PSrr_REV */ +/* Table17975 */ + 0x26bc, /* VPERMIL2PDrm */ + 0x26be, /* VPERMIL2PDrr_REV */ +/* Table17977 */ + 0x1579, /* VFMADDSUBPS4rm */ + 0x157a, /* VFMADDSUBPS4rr */ +/* Table17979 */ + 0x1571, /* VFMADDSUBPD4rm */ + 0x1572, /* VFMADDSUBPD4rr */ +/* Table17981 */ + 0x1781, /* VFMSUBADDPS4rm */ + 0x1782, /* VFMSUBADDPS4rr */ +/* Table17983 */ + 0x1779, /* VFMSUBADDPD4rm */ + 0x177a, /* VFMSUBADDPD4rr */ +/* Table17985 */ + 0x148d, /* VFMADDPS4rm */ + 0x148e, /* VFMADDPS4rr */ +/* Table17987 */ + 0x1485, /* VFMADDPD4rm */ + 0x1486, /* VFMADDPD4rr */ +/* Table17989 */ + 0x149a, /* VFMADDSS4rm */ + 0x149c, /* VFMADDSS4rr */ +/* Table17991 */ + 0x1492, /* VFMADDSD4rm */ + 0x1494, /* VFMADDSD4rr */ +/* Table17993 */ + 0x1791, /* VFMSUBPS4rm */ + 0x1792, /* VFMSUBPS4rr */ +/* Table17995 */ + 0x1789, /* VFMSUBPD4rm */ + 0x178a, /* VFMSUBPD4rr */ +/* Table17997 */ + 0x179e, /* VFMSUBSS4rm */ + 0x17a0, /* VFMSUBSS4rr */ +/* Table17999 */ + 0x1796, /* VFMSUBSD4rm */ + 0x1798, /* VFMSUBSD4rr */ +/* Table18001 */ + 0x18dd, /* VFNMADDPS4rm */ + 0x18de, /* VFNMADDPS4rr */ +/* Table18003 */ + 0x18d5, /* VFNMADDPD4rm */ + 0x18d6, /* VFNMADDPD4rr */ +/* Table18005 */ + 0x18ea, /* VFNMADDSS4rm */ + 0x18ec, /* VFNMADDSS4rr */ +/* Table18007 */ + 0x18e2, /* VFNMADDSD4rm */ + 0x18e4, /* VFNMADDSD4rr */ +/* Table18009 */ + 0x1a29, /* VFNMSUBPS4rm */ + 0x1a2a, /* VFNMSUBPS4rr */ +/* Table18011 */ + 0x1a21, /* VFNMSUBPD4rm */ + 0x1a22, /* VFNMSUBPD4rr */ +/* Table18013 */ + 0x1a36, /* VFNMSUBSS4rm */ + 0x1a38, /* VFNMSUBSS4rr */ +/* Table18015 */ + 0x1a2e, /* VFNMSUBSD4rm */ + 0x1a30, /* VFNMSUBSD4rr */ +/* Table18017 */ + 0x1b68, /* VGF2P8AFFINEQBrmi */ + 0x1b69, /* VGF2P8AFFINEQBrri */ +/* Table18019 */ + 0x1b49, /* VGF2P8AFFINEINVQBrmi */ + 0x1b4a, /* VGF2P8AFFINEINVQBrri */ +/* Table18021 */ + 0x2275, /* VPBLENDDYrmi */ + 0x2276, /* VPBLENDDYrri */ +/* Table18023 */ + 0x2705, /* VPERMILPSYmi */ + 0x2706, /* VPERMILPSYri */ +/* Table18025 */ + 0x26c7, /* VPERMILPDYmi */ + 0x26c8, /* VPERMILPDYri */ +/* Table18027 */ + 0x25fd, /* VPERM2F128rm */ + 0x25fe, /* VPERM2F128rr */ +/* Table18029 */ + 0x384b, /* VROUNDPSYm */ + 0x384c, /* VROUNDPSYr */ +/* Table18031 */ + 0x3847, /* VROUNDPDYm */ + 0x3848, /* VROUNDPDYr */ +/* Table18033 */ + 0xcda, /* VBLENDPSYrmi */ + 0xcdb, /* VBLENDPSYrri */ +/* Table18035 */ + 0xcd6, /* VBLENDPDYrmi */ + 0xcd7, /* VBLENDPDYrri */ +/* Table18037 */ + 0x22d7, /* VPBLENDWYrmi */ + 0x22d8, /* VPBLENDWYrri */ +/* Table18039 */ + 0x21bf, /* VPALIGNRYrmi */ + 0x21c0, /* VPALIGNRYrri */ +/* Table18041 */ + 0x1b90, /* VINSERTF128rm */ + 0x1b91, /* VINSERTF128rr */ +/* Table18043 */ + 0x12c2, /* VEXTRACTF128mr */ + 0x12c3, /* VEXTRACTF128rr */ +/* Table18045 */ + 0xf42, /* VCVTPS2PHYmr */ + 0xf43, /* VCVTPS2PHYrr */ +/* Table18047 */ + 0x1bb6, /* VINSERTI128rm */ + 0x1bb7, /* VINSERTI128rr */ +/* Table18049 */ + 0x12e2, /* VEXTRACTI128mr */ + 0x12e3, /* VEXTRACTI128rr */ +/* Table18051 */ + 0x127e, /* VDPPSYrmi */ + 0x127f, /* VDPPSYrri */ +/* Table18053 */ + 0x1f72, /* VMPSADBWYrmi */ + 0x1f73, /* VMPSADBWYrri */ +/* Table18055 */ + 0x235d, /* VPCLMULQDQYrm */ + 0x235e, /* VPCLMULQDQYrr */ +/* Table18057 */ + 0x25ff, /* VPERM2I128rm */ + 0x2600, /* VPERM2I128rr */ +/* Table18059 */ + 0x26bf, /* VPERMIL2PSYmr */ + 0x26c1, /* VPERMIL2PSYrr */ +/* Table18061 */ + 0x26b7, /* VPERMIL2PDYmr */ + 0x26b9, /* VPERMIL2PDYrr */ +/* Table18063 */ + 0xce2, /* VBLENDVPSYrm */ + 0xce3, /* VBLENDVPSYrr */ +/* Table18065 */ + 0xcde, /* VBLENDVPDYrm */ + 0xcdf, /* VBLENDVPDYrr */ +/* Table18067 */ + 0x22d3, /* VPBLENDVBYrm */ + 0x22d4, /* VPBLENDVBYrr */ +/* Table18069 */ + 0x1574, /* VFMADDSUBPS4Ymr */ + 0x1577, /* VFMADDSUBPS4Yrr_REV */ +/* Table18071 */ + 0x156c, /* VFMADDSUBPD4Ymr */ + 0x156f, /* VFMADDSUBPD4Yrr_REV */ +/* Table18073 */ + 0x177c, /* VFMSUBADDPS4Ymr */ + 0x177f, /* VFMSUBADDPS4Yrr_REV */ +/* Table18075 */ + 0x1774, /* VFMSUBADDPD4Ymr */ + 0x1777, /* VFMSUBADDPD4Yrr_REV */ +/* Table18077 */ + 0x1488, /* VFMADDPS4Ymr */ + 0x148b, /* VFMADDPS4Yrr_REV */ +/* Table18079 */ + 0x1480, /* VFMADDPD4Ymr */ + 0x1483, /* VFMADDPD4Yrr_REV */ +/* Table18081 */ + 0x178c, /* VFMSUBPS4Ymr */ + 0x178f, /* VFMSUBPS4Yrr_REV */ +/* Table18083 */ + 0x1784, /* VFMSUBPD4Ymr */ + 0x1787, /* VFMSUBPD4Yrr_REV */ +/* Table18085 */ + 0x18d8, /* VFNMADDPS4Ymr */ + 0x18db, /* VFNMADDPS4Yrr_REV */ +/* Table18087 */ + 0x18d0, /* VFNMADDPD4Ymr */ + 0x18d3, /* VFNMADDPD4Yrr_REV */ +/* Table18089 */ + 0x1a24, /* VFNMSUBPS4Ymr */ + 0x1a27, /* VFNMSUBPS4Yrr_REV */ +/* Table18091 */ + 0x1a1c, /* VFNMSUBPD4Ymr */ + 0x1a1f, /* VFNMSUBPD4Yrr_REV */ +/* Table18093 */ + 0x277d, /* VPERMQYmi */ + 0x277e, /* VPERMQYri */ +/* Table18095 */ + 0x2743, /* VPERMPDYmi */ + 0x2744, /* VPERMPDYri */ +/* Table18097 */ + 0x26c0, /* VPERMIL2PSYrm */ + 0x26c2, /* VPERMIL2PSYrr_REV */ +/* Table18099 */ + 0x26b8, /* VPERMIL2PDYrm */ + 0x26ba, /* VPERMIL2PDYrr_REV */ +/* Table18101 */ + 0x1575, /* VFMADDSUBPS4Yrm */ + 0x1576, /* VFMADDSUBPS4Yrr */ +/* Table18103 */ + 0x156d, /* VFMADDSUBPD4Yrm */ + 0x156e, /* VFMADDSUBPD4Yrr */ +/* Table18105 */ + 0x177d, /* VFMSUBADDPS4Yrm */ + 0x177e, /* VFMSUBADDPS4Yrr */ +/* Table18107 */ + 0x1775, /* VFMSUBADDPD4Yrm */ + 0x1776, /* VFMSUBADDPD4Yrr */ +/* Table18109 */ + 0x1489, /* VFMADDPS4Yrm */ + 0x148a, /* VFMADDPS4Yrr */ +/* Table18111 */ + 0x1481, /* VFMADDPD4Yrm */ + 0x1482, /* VFMADDPD4Yrr */ +/* Table18113 */ + 0x178d, /* VFMSUBPS4Yrm */ + 0x178e, /* VFMSUBPS4Yrr */ +/* Table18115 */ + 0x1785, /* VFMSUBPD4Yrm */ + 0x1786, /* VFMSUBPD4Yrr */ +/* Table18117 */ + 0x18d9, /* VFNMADDPS4Yrm */ + 0x18da, /* VFNMADDPS4Yrr */ +/* Table18119 */ + 0x18d1, /* VFNMADDPD4Yrm */ + 0x18d2, /* VFNMADDPD4Yrr */ +/* Table18121 */ + 0x1a25, /* VFNMSUBPS4Yrm */ + 0x1a26, /* VFNMSUBPS4Yrr */ +/* Table18123 */ + 0x1a1d, /* VFNMSUBPD4Yrm */ + 0x1a1e, /* VFNMSUBPD4Yrr */ +/* Table18125 */ + 0x1b4b, /* VGF2P8AFFINEQBYrmi */ + 0x1b4c, /* VGF2P8AFFINEQBYrri */ +/* Table18127 */ + 0x1b2c, /* VGF2P8AFFINEINVQBYrmi */ + 0x1b2d, /* VGF2P8AFFINEINVQBYrri */ +/* Table18129 */ + 0xbf1, /* VALIGNDZ128rmi */ + 0xbf4, /* VALIGNDZ128rri */ +/* Table18131 */ + 0x270c, /* VPERMILPSZ128mi */ + 0x270f, /* VPERMILPSZ128ri */ +/* Table18133 */ + 0x3816, /* VRNDSCALEPSZ128rmi */ + 0x3819, /* VRNDSCALEPSZ128rri */ +/* Table18135 */ + 0x383d, /* VRNDSCALESSZm_Int */ + 0x3841, /* VRNDSCALESSZr_Int */ +/* Table18137 */ + 0x21c1, /* VPALIGNRZ128rmi */ + 0x21c4, /* VPALIGNRZ128rri */ +/* Table18139 */ + 0x288d, /* VPEXTRBZmr */ + 0x288e, /* VPEXTRBZrr */ +/* Table18141 */ + 0x2899, /* VPEXTRWZmr */ + 0x289b, /* VPEXTRWZrr_REV */ +/* Table18143 */ + 0x2891, /* VPEXTRDZmr */ + 0x2892, /* VPEXTRDZrr */ +/* Table18145 */ + 0x1302, /* VEXTRACTPSZmr */ + 0x1303, /* VEXTRACTPSZrr */ +/* Table18147 */ + 0xf44, /* VCVTPS2PHZ128mr */ + 0xf46, /* VCVTPS2PHZ128rr */ +/* Table18149 */ + 0x2487, /* VPCMPUDZ128rmi */ + 0x248f, /* VPCMPUDZ128rri */ +/* Table18151 */ + 0x2387, /* VPCMPDZ128rmi */ + 0x238f, /* VPCMPDZ128rri */ +/* Table18153 */ + 0x28eb, /* VPINSRBZrm */ + 0x28ec, /* VPINSRBZrr */ +/* Table18155 */ + 0x1bdc, /* VINSERTPSZrm */ + 0x1bdd, /* VINSERTPSZrr */ +/* Table18157 */ + 0x28ef, /* VPINSRDZrm */ + 0x28f0, /* VPINSRDZrr */ +/* Table18159 */ + 0x3528, /* VPTERNLOGDZ128rmi */ + 0x352b, /* VPTERNLOGDZ128rri */ +/* Table18161 */ + 0x1aff, /* VGETMANTPSZ128rmi */ + 0x1b02, /* VGETMANTPSZ128rri */ +/* Table18163 */ + 0x1b23, /* VGETMANTSSZrmi */ + 0x1b26, /* VGETMANTSSZrri */ +/* Table18165 */ + 0x246f, /* VPCMPUBZ128rmi */ + 0x2473, /* VPCMPUBZ128rri */ +/* Table18167 */ + 0x236f, /* VPCMPBZ128rmi */ + 0x2373, /* VPCMPBZ128rri */ +/* Table18169 */ + 0x1208, /* VDBPSADBWZ128rmi */ + 0x120b, /* VDBPSADBWZ128rri */ +/* Table18171 */ + 0x235f, /* VPCLMULQDQZ128rm */ + 0x2360, /* VPCLMULQDQZ128rr */ +/* Table18173 */ + 0x3706, /* VRANGEPSZ128rmi */ + 0x3709, /* VRANGEPSZ128rri */ +/* Table18175 */ + 0x372a, /* VRANGESSZrmi */ + 0x372d, /* VRANGESSZrri */ +/* Table18177 */ + 0x1327, /* VFIXUPIMMPSZ128rmi */ + 0x132a, /* VFIXUPIMMPSZ128rri */ +/* Table18179 */ + 0x134b, /* VFIXUPIMMSSZrmi */ + 0x134e, /* VFIXUPIMMSSZrri */ +/* Table18181 */ + 0x37c8, /* VREDUCEPSZ128rmi */ + 0x37cb, /* VREDUCEPSZ128rri */ +/* Table18183 */ + 0x37ec, /* VREDUCESSZrmi */ + 0x37ef, /* VREDUCESSZrri */ +/* Table18185 */ + 0x1a4e, /* VFPCLASSPSZ128rm */ + 0x1a52, /* VFPCLASSPSZ128rr */ +/* Table18187 */ + 0x1a64, /* VFPCLASSSSZrm */ + 0x1a66, /* VFPCLASSSSZrr */ +/* Table18189 */ + 0x301b, /* VPSHLDDZ128rmi */ + 0x301e, /* VPSHLDDZ128rri */ +/* Table18191 */ + 0x30b7, /* VPSHRDDZ128rmi */ + 0x30ba, /* VPSHRDDZ128rri */ +/* Table18193 */ + 0xc0c, /* VALIGNQZ128rmi */ + 0xc0f, /* VALIGNQZ128rri */ +/* Table18195 */ + 0x26ce, /* VPERMILPDZ128mi */ + 0x26d1, /* VPERMILPDZ128ri */ +/* Table18197 */ + 0x37f8, /* VRNDSCALEPDZ128rmi */ + 0x37fb, /* VRNDSCALEPDZ128rri */ +/* Table18199 */ + 0x3832, /* VRNDSCALESDZm_Int */ + 0x3836, /* VRNDSCALESDZr_Int */ +/* Table18201 */ + 0x2895, /* VPEXTRQZmr */ + 0x2896, /* VPEXTRQZrr */ +/* Table18203 */ + 0x24ab, /* VPCMPUQZ128rmi */ + 0x24b3, /* VPCMPUQZ128rri */ +/* Table18205 */ + 0x244b, /* VPCMPQZ128rmi */ + 0x2453, /* VPCMPQZ128rri */ +/* Table18207 */ + 0x28f3, /* VPINSRQZrm */ + 0x28f4, /* VPINSRQZrr */ +/* Table18209 */ + 0x3543, /* VPTERNLOGQZ128rmi */ + 0x3546, /* VPTERNLOGQZ128rri */ +/* Table18211 */ + 0x1ae1, /* VGETMANTPDZ128rmi */ + 0x1ae4, /* VGETMANTPDZ128rri */ +/* Table18213 */ + 0x1b1a, /* VGETMANTSDZrmi */ + 0x1b1d, /* VGETMANTSDZrri */ +/* Table18215 */ + 0x24cf, /* VPCMPUWZ128rmi */ + 0x24d3, /* VPCMPUWZ128rri */ +/* Table18217 */ + 0x24e7, /* VPCMPWZ128rmi */ + 0x24eb, /* VPCMPWZ128rri */ +/* Table18219 */ + 0x36e8, /* VRANGEPDZ128rmi */ + 0x36eb, /* VRANGEPDZ128rri */ +/* Table18221 */ + 0x3721, /* VRANGESDZrmi */ + 0x3724, /* VRANGESDZrri */ +/* Table18223 */ + 0x1309, /* VFIXUPIMMPDZ128rmi */ + 0x130c, /* VFIXUPIMMPDZ128rri */ +/* Table18225 */ + 0x1342, /* VFIXUPIMMSDZrmi */ + 0x1345, /* VFIXUPIMMSDZrri */ +/* Table18227 */ + 0x37aa, /* VREDUCEPDZ128rmi */ + 0x37ad, /* VREDUCEPDZ128rri */ +/* Table18229 */ + 0x37e3, /* VREDUCESDZrmi */ + 0x37e6, /* VREDUCESDZrri */ +/* Table18231 */ + 0x1a3c, /* VFPCLASSPDZ128rm */ + 0x1a40, /* VFPCLASSPDZ128rr */ +/* Table18233 */ + 0x1a60, /* VFPCLASSSDZrm */ + 0x1a62, /* VFPCLASSSDZrr */ +/* Table18235 */ + 0x3096, /* VPSHLDWZ128rmi */ + 0x3099, /* VPSHLDWZ128rri */ +/* Table18237 */ + 0x3036, /* VPSHLDQZ128rmi */ + 0x3039, /* VPSHLDQZ128rri */ +/* Table18239 */ + 0x3132, /* VPSHRDWZ128rmi */ + 0x3135, /* VPSHRDWZ128rri */ +/* Table18241 */ + 0x30d2, /* VPSHRDQZ128rmi */ + 0x30d5, /* VPSHRDQZ128rri */ +/* Table18243 */ + 0x1b50, /* VGF2P8AFFINEQBZ128rmi */ + 0x1b53, /* VGF2P8AFFINEQBZ128rri */ +/* Table18245 */ + 0x1b31, /* VGF2P8AFFINEINVQBZ128rmi */ + 0x1b34, /* VGF2P8AFFINEINVQBZ128rri */ +/* Table18247 */ + 0xbfa, /* VALIGNDZ256rmi */ + 0xbfd, /* VALIGNDZ256rri */ +/* Table18249 */ + 0x271e, /* VPERMILPSZ256mi */ + 0x2721, /* VPERMILPSZ256ri */ +/* Table18251 */ + 0x381f, /* VRNDSCALEPSZ256rmi */ + 0x3822, /* VRNDSCALEPSZ256rri */ +/* Table18253 */ + 0x21c7, /* VPALIGNRZ256rmi */ + 0x21ca, /* VPALIGNRZ256rri */ +/* Table18255 */ + 0x1b92, /* VINSERTF32x4Z256rm */ + 0x1b95, /* VINSERTF32x4Z256rr */ +/* Table18257 */ + 0x12c4, /* VEXTRACTF32x4Z256mr */ + 0x12c6, /* VEXTRACTF32x4Z256rr */ +/* Table18259 */ + 0xf49, /* VCVTPS2PHZ256mr */ + 0xf4b, /* VCVTPS2PHZ256rr */ +/* Table18261 */ + 0x2493, /* VPCMPUDZ256rmi */ + 0x249b, /* VPCMPUDZ256rri */ +/* Table18263 */ + 0x2393, /* VPCMPDZ256rmi */ + 0x239b, /* VPCMPDZ256rri */ +/* Table18265 */ + 0x3930, /* VSHUFF32X4Z256rmi */ + 0x3933, /* VSHUFF32X4Z256rri */ +/* Table18267 */ + 0x3531, /* VPTERNLOGDZ256rmi */ + 0x3534, /* VPTERNLOGDZ256rri */ +/* Table18269 */ + 0x1b08, /* VGETMANTPSZ256rmi */ + 0x1b0b, /* VGETMANTPSZ256rri */ +/* Table18271 */ + 0x1bb8, /* VINSERTI32x4Z256rm */ + 0x1bbb, /* VINSERTI32x4Z256rr */ +/* Table18273 */ + 0x12e4, /* VEXTRACTI32x4Z256mr */ + 0x12e6, /* VEXTRACTI32x4Z256rr */ +/* Table18275 */ + 0x2477, /* VPCMPUBZ256rmi */ + 0x247b, /* VPCMPUBZ256rri */ +/* Table18277 */ + 0x2377, /* VPCMPBZ256rmi */ + 0x237b, /* VPCMPBZ256rri */ +/* Table18279 */ + 0x120e, /* VDBPSADBWZ256rmi */ + 0x1211, /* VDBPSADBWZ256rri */ +/* Table18281 */ + 0x3954, /* VSHUFI32X4Z256rmi */ + 0x3957, /* VSHUFI32X4Z256rri */ +/* Table18283 */ + 0x2361, /* VPCLMULQDQZ256rm */ + 0x2362, /* VPCLMULQDQZ256rr */ +/* Table18285 */ + 0x370f, /* VRANGEPSZ256rmi */ + 0x3712, /* VRANGEPSZ256rri */ +/* Table18287 */ + 0x1330, /* VFIXUPIMMPSZ256rmi */ + 0x1333, /* VFIXUPIMMPSZ256rri */ +/* Table18289 */ + 0x37d1, /* VREDUCEPSZ256rmi */ + 0x37d4, /* VREDUCEPSZ256rri */ +/* Table18291 */ + 0x1a54, /* VFPCLASSPSZ256rm */ + 0x1a58, /* VFPCLASSPSZ256rr */ +/* Table18293 */ + 0x3024, /* VPSHLDDZ256rmi */ + 0x3027, /* VPSHLDDZ256rri */ +/* Table18295 */ + 0x30c0, /* VPSHRDDZ256rmi */ + 0x30c3, /* VPSHRDDZ256rri */ +/* Table18297 */ + 0x2782, /* VPERMQZ256mi */ + 0x2785, /* VPERMQZ256ri */ +/* Table18299 */ + 0x2748, /* VPERMPDZ256mi */ + 0x274b, /* VPERMPDZ256ri */ +/* Table18301 */ + 0xc15, /* VALIGNQZ256rmi */ + 0xc18, /* VALIGNQZ256rri */ +/* Table18303 */ + 0x26e0, /* VPERMILPDZ256mi */ + 0x26e3, /* VPERMILPDZ256ri */ +/* Table18305 */ + 0x3801, /* VRNDSCALEPDZ256rmi */ + 0x3804, /* VRNDSCALEPDZ256rri */ +/* Table18307 */ + 0x1ba4, /* VINSERTF64x2Z256rm */ + 0x1ba7, /* VINSERTF64x2Z256rr */ +/* Table18309 */ + 0x12d3, /* VEXTRACTF64x2Z256mr */ + 0x12d5, /* VEXTRACTF64x2Z256rr */ +/* Table18311 */ + 0x24b7, /* VPCMPUQZ256rmi */ + 0x24bf, /* VPCMPUQZ256rri */ +/* Table18313 */ + 0x2457, /* VPCMPQZ256rmi */ + 0x245f, /* VPCMPQZ256rri */ +/* Table18315 */ + 0x3942, /* VSHUFF64X2Z256rmi */ + 0x3945, /* VSHUFF64X2Z256rri */ +/* Table18317 */ + 0x354c, /* VPTERNLOGQZ256rmi */ + 0x354f, /* VPTERNLOGQZ256rri */ +/* Table18319 */ + 0x1aea, /* VGETMANTPDZ256rmi */ + 0x1aed, /* VGETMANTPDZ256rri */ +/* Table18321 */ + 0x1bca, /* VINSERTI64x2Z256rm */ + 0x1bcd, /* VINSERTI64x2Z256rr */ +/* Table18323 */ + 0x12f3, /* VEXTRACTI64x2Z256mr */ + 0x12f5, /* VEXTRACTI64x2Z256rr */ +/* Table18325 */ + 0x24d7, /* VPCMPUWZ256rmi */ + 0x24db, /* VPCMPUWZ256rri */ +/* Table18327 */ + 0x24ef, /* VPCMPWZ256rmi */ + 0x24f3, /* VPCMPWZ256rri */ +/* Table18329 */ + 0x3966, /* VSHUFI64X2Z256rmi */ + 0x3969, /* VSHUFI64X2Z256rri */ +/* Table18331 */ + 0x36f1, /* VRANGEPDZ256rmi */ + 0x36f4, /* VRANGEPDZ256rri */ +/* Table18333 */ + 0x1312, /* VFIXUPIMMPDZ256rmi */ + 0x1315, /* VFIXUPIMMPDZ256rri */ +/* Table18335 */ + 0x37b3, /* VREDUCEPDZ256rmi */ + 0x37b6, /* VREDUCEPDZ256rri */ +/* Table18337 */ + 0x1a42, /* VFPCLASSPDZ256rm */ + 0x1a46, /* VFPCLASSPDZ256rr */ +/* Table18339 */ + 0x309c, /* VPSHLDWZ256rmi */ + 0x309f, /* VPSHLDWZ256rri */ +/* Table18341 */ + 0x303f, /* VPSHLDQZ256rmi */ + 0x3042, /* VPSHLDQZ256rri */ +/* Table18343 */ + 0x3138, /* VPSHRDWZ256rmi */ + 0x313b, /* VPSHRDWZ256rri */ +/* Table18345 */ + 0x30db, /* VPSHRDQZ256rmi */ + 0x30de, /* VPSHRDQZ256rri */ +/* Table18347 */ + 0x1b59, /* VGF2P8AFFINEQBZ256rmi */ + 0x1b5c, /* VGF2P8AFFINEQBZ256rri */ +/* Table18349 */ + 0x1b3a, /* VGF2P8AFFINEINVQBZ256rmi */ + 0x1b3d, /* VGF2P8AFFINEINVQBZ256rri */ +/* Table18351 */ + 0xc03, /* VALIGNDZrmi */ + 0xc06, /* VALIGNDZrri */ +/* Table18353 */ + 0x2730, /* VPERMILPSZmi */ + 0x2733, /* VPERMILPSZri */ +/* Table18355 */ + 0x3828, /* VRNDSCALEPSZrmi */ + 0x382b, /* VRNDSCALEPSZrri */ +/* Table18357 */ + 0x21cd, /* VPALIGNRZrmi */ + 0x21d0, /* VPALIGNRZrri */ +/* Table18359 */ + 0x1b98, /* VINSERTF32x4Zrm */ + 0x1b9b, /* VINSERTF32x4Zrr */ +/* Table18361 */ + 0x12c9, /* VEXTRACTF32x4Zmr */ + 0x12cb, /* VEXTRACTF32x4Zrr */ +/* Table18363 */ + 0x1b9e, /* VINSERTF32x8Zrm */ + 0x1ba1, /* VINSERTF32x8Zrr */ +/* Table18365 */ + 0x12ce, /* VEXTRACTF32x8Zmr */ + 0x12d0, /* VEXTRACTF32x8Zrr */ +/* Table18367 */ + 0xf4e, /* VCVTPS2PHZmr */ + 0xf50, /* VCVTPS2PHZrr */ +/* Table18369 */ + 0x249f, /* VPCMPUDZrmi */ + 0x24a7, /* VPCMPUDZrri */ +/* Table18371 */ + 0x239f, /* VPCMPDZrmi */ + 0x23a7, /* VPCMPDZrri */ +/* Table18373 */ + 0x3939, /* VSHUFF32X4Zrmi */ + 0x393c, /* VSHUFF32X4Zrri */ +/* Table18375 */ + 0x353a, /* VPTERNLOGDZrmi */ + 0x353d, /* VPTERNLOGDZrri */ +/* Table18377 */ + 0x1b11, /* VGETMANTPSZrmi */ + 0x1b14, /* VGETMANTPSZrri */ +/* Table18379 */ + 0x1bbe, /* VINSERTI32x4Zrm */ + 0x1bc1, /* VINSERTI32x4Zrr */ +/* Table18381 */ + 0x12e9, /* VEXTRACTI32x4Zmr */ + 0x12eb, /* VEXTRACTI32x4Zrr */ +/* Table18383 */ + 0x1bc4, /* VINSERTI32x8Zrm */ + 0x1bc7, /* VINSERTI32x8Zrr */ +/* Table18385 */ + 0x12ee, /* VEXTRACTI32x8Zmr */ + 0x12f0, /* VEXTRACTI32x8Zrr */ +/* Table18387 */ + 0x247f, /* VPCMPUBZrmi */ + 0x2483, /* VPCMPUBZrri */ +/* Table18389 */ + 0x237f, /* VPCMPBZrmi */ + 0x2383, /* VPCMPBZrri */ +/* Table18391 */ + 0x1214, /* VDBPSADBWZrmi */ + 0x1217, /* VDBPSADBWZrri */ +/* Table18393 */ + 0x395d, /* VSHUFI32X4Zrmi */ + 0x3960, /* VSHUFI32X4Zrri */ +/* Table18395 */ + 0x2363, /* VPCLMULQDQZrm */ + 0x2364, /* VPCLMULQDQZrr */ +/* Table18397 */ + 0x3718, /* VRANGEPSZrmi */ + 0x371b, /* VRANGEPSZrri */ +/* Table18399 */ + 0x1339, /* VFIXUPIMMPSZrmi */ + 0x133c, /* VFIXUPIMMPSZrri */ +/* Table18401 */ + 0x37da, /* VREDUCEPSZrmi */ + 0x37dd, /* VREDUCEPSZrri */ +/* Table18403 */ + 0x1a5a, /* VFPCLASSPSZrm */ + 0x1a5e, /* VFPCLASSPSZrr */ +/* Table18405 */ + 0x302d, /* VPSHLDDZrmi */ + 0x3030, /* VPSHLDDZrri */ +/* Table18407 */ + 0x30c9, /* VPSHRDDZrmi */ + 0x30cc, /* VPSHRDDZrri */ +/* Table18409 */ + 0x2794, /* VPERMQZmi */ + 0x2797, /* VPERMQZri */ +/* Table18411 */ + 0x275a, /* VPERMPDZmi */ + 0x275d, /* VPERMPDZri */ +/* Table18413 */ + 0xc1e, /* VALIGNQZrmi */ + 0xc21, /* VALIGNQZrri */ +/* Table18415 */ + 0x26f2, /* VPERMILPDZmi */ + 0x26f5, /* VPERMILPDZri */ +/* Table18417 */ + 0x380a, /* VRNDSCALEPDZrmi */ + 0x380d, /* VRNDSCALEPDZrri */ +/* Table18419 */ + 0x1baa, /* VINSERTF64x2Zrm */ + 0x1bad, /* VINSERTF64x2Zrr */ +/* Table18421 */ + 0x12d8, /* VEXTRACTF64x2Zmr */ + 0x12da, /* VEXTRACTF64x2Zrr */ +/* Table18423 */ + 0x1bb0, /* VINSERTF64x4Zrm */ + 0x1bb3, /* VINSERTF64x4Zrr */ +/* Table18425 */ + 0x12dd, /* VEXTRACTF64x4Zmr */ + 0x12df, /* VEXTRACTF64x4Zrr */ +/* Table18427 */ + 0x24c3, /* VPCMPUQZrmi */ + 0x24cb, /* VPCMPUQZrri */ +/* Table18429 */ + 0x2463, /* VPCMPQZrmi */ + 0x246b, /* VPCMPQZrri */ +/* Table18431 */ + 0x394b, /* VSHUFF64X2Zrmi */ + 0x394e, /* VSHUFF64X2Zrri */ +/* Table18433 */ + 0x3555, /* VPTERNLOGQZrmi */ + 0x3558, /* VPTERNLOGQZrri */ +/* Table18435 */ + 0x1af3, /* VGETMANTPDZrmi */ + 0x1af6, /* VGETMANTPDZrri */ +/* Table18437 */ + 0x1bd0, /* VINSERTI64x2Zrm */ + 0x1bd3, /* VINSERTI64x2Zrr */ +/* Table18439 */ + 0x12f8, /* VEXTRACTI64x2Zmr */ + 0x12fa, /* VEXTRACTI64x2Zrr */ +/* Table18441 */ + 0x1bd6, /* VINSERTI64x4Zrm */ + 0x1bd9, /* VINSERTI64x4Zrr */ +/* Table18443 */ + 0x12fd, /* VEXTRACTI64x4Zmr */ + 0x12ff, /* VEXTRACTI64x4Zrr */ +/* Table18445 */ + 0x24df, /* VPCMPUWZrmi */ + 0x24e3, /* VPCMPUWZrri */ +/* Table18447 */ + 0x24f7, /* VPCMPWZrmi */ + 0x24fb, /* VPCMPWZrri */ +/* Table18449 */ + 0x396f, /* VSHUFI64X2Zrmi */ + 0x3972, /* VSHUFI64X2Zrri */ +/* Table18451 */ + 0x36fa, /* VRANGEPDZrmi */ + 0x36fd, /* VRANGEPDZrri */ +/* Table18453 */ + 0x131b, /* VFIXUPIMMPDZrmi */ + 0x131e, /* VFIXUPIMMPDZrri */ +/* Table18455 */ + 0x37bc, /* VREDUCEPDZrmi */ + 0x37bf, /* VREDUCEPDZrri */ +/* Table18457 */ + 0x1a48, /* VFPCLASSPDZrm */ + 0x1a4c, /* VFPCLASSPDZrr */ +/* Table18459 */ + 0x30a2, /* VPSHLDWZrmi */ + 0x30a5, /* VPSHLDWZrri */ +/* Table18461 */ + 0x3048, /* VPSHLDQZrmi */ + 0x304b, /* VPSHLDQZrri */ +/* Table18463 */ + 0x313e, /* VPSHRDWZrmi */ + 0x3141, /* VPSHRDWZrri */ +/* Table18465 */ + 0x30e4, /* VPSHRDQZrmi */ + 0x30e7, /* VPSHRDQZrri */ +/* Table18467 */ + 0x1b62, /* VGF2P8AFFINEQBZrmi */ + 0x1b65, /* VGF2P8AFFINEQBZrri */ +/* Table18469 */ + 0x1b43, /* VGF2P8AFFINEINVQBZrmi */ + 0x1b46, /* VGF2P8AFFINEINVQBZrri */ +/* Table18471 */ + 0xbf2, /* VALIGNDZ128rmik */ + 0xbf5, /* VALIGNDZ128rrik */ +/* Table18473 */ + 0x270d, /* VPERMILPSZ128mik */ + 0x2710, /* VPERMILPSZ128rik */ +/* Table18475 */ + 0x3817, /* VRNDSCALEPSZ128rmik */ + 0x381a, /* VRNDSCALEPSZ128rrik */ +/* Table18477 */ + 0x383e, /* VRNDSCALESSZm_Intk */ + 0x3842, /* VRNDSCALESSZr_Intk */ +/* Table18479 */ + 0x21c2, /* VPALIGNRZ128rmik */ + 0x21c5, /* VPALIGNRZ128rrik */ +/* Table18481 */ + 0xf45, /* VCVTPS2PHZ128mrk */ + 0xf47, /* VCVTPS2PHZ128rrk */ +/* Table18483 */ + 0x248d, /* VPCMPUDZ128rmik */ + 0x2491, /* VPCMPUDZ128rrik */ +/* Table18485 */ + 0x238d, /* VPCMPDZ128rmik */ + 0x2391, /* VPCMPDZ128rrik */ +/* Table18487 */ + 0x3529, /* VPTERNLOGDZ128rmik */ + 0x352c, /* VPTERNLOGDZ128rrik */ +/* Table18489 */ + 0x1b00, /* VGETMANTPSZ128rmik */ + 0x1b03, /* VGETMANTPSZ128rrik */ +/* Table18491 */ + 0x1b24, /* VGETMANTSSZrmik */ + 0x1b2a, /* VGETMANTSSZrrik */ +/* Table18493 */ + 0x2471, /* VPCMPUBZ128rmik */ + 0x2475, /* VPCMPUBZ128rrik */ +/* Table18495 */ + 0x2371, /* VPCMPBZ128rmik */ + 0x2375, /* VPCMPBZ128rrik */ +/* Table18497 */ + 0x1209, /* VDBPSADBWZ128rmik */ + 0x120c, /* VDBPSADBWZ128rrik */ +/* Table18499 */ + 0x3707, /* VRANGEPSZ128rmik */ + 0x370a, /* VRANGEPSZ128rrik */ +/* Table18501 */ + 0x372b, /* VRANGESSZrmik */ + 0x3731, /* VRANGESSZrrik */ +/* Table18503 */ + 0x1328, /* VFIXUPIMMPSZ128rmik */ + 0x132b, /* VFIXUPIMMPSZ128rrik */ +/* Table18505 */ + 0x134c, /* VFIXUPIMMSSZrmik */ + 0x1352, /* VFIXUPIMMSSZrrik */ +/* Table18507 */ + 0x37c9, /* VREDUCEPSZ128rmik */ + 0x37cc, /* VREDUCEPSZ128rrik */ +/* Table18509 */ + 0x37ed, /* VREDUCESSZrmik */ + 0x37f3, /* VREDUCESSZrrik */ +/* Table18511 */ + 0x1a51, /* VFPCLASSPSZ128rmk */ + 0x1a53, /* VFPCLASSPSZ128rrk */ +/* Table18513 */ + 0x1a65, /* VFPCLASSSSZrmk */ + 0x1a67, /* VFPCLASSSSZrrk */ +/* Table18515 */ + 0x301c, /* VPSHLDDZ128rmik */ + 0x301f, /* VPSHLDDZ128rrik */ +/* Table18517 */ + 0x30b8, /* VPSHRDDZ128rmik */ + 0x30bb, /* VPSHRDDZ128rrik */ +/* Table18519 */ + 0xc0d, /* VALIGNQZ128rmik */ + 0xc10, /* VALIGNQZ128rrik */ +/* Table18521 */ + 0x26cf, /* VPERMILPDZ128mik */ + 0x26d2, /* VPERMILPDZ128rik */ +/* Table18523 */ + 0x37f9, /* VRNDSCALEPDZ128rmik */ + 0x37fc, /* VRNDSCALEPDZ128rrik */ +/* Table18525 */ + 0x3833, /* VRNDSCALESDZm_Intk */ + 0x3837, /* VRNDSCALESDZr_Intk */ +/* Table18527 */ + 0x24b1, /* VPCMPUQZ128rmik */ + 0x24b5, /* VPCMPUQZ128rrik */ +/* Table18529 */ + 0x2451, /* VPCMPQZ128rmik */ + 0x2455, /* VPCMPQZ128rrik */ +/* Table18531 */ + 0x3544, /* VPTERNLOGQZ128rmik */ + 0x3547, /* VPTERNLOGQZ128rrik */ +/* Table18533 */ + 0x1ae2, /* VGETMANTPDZ128rmik */ + 0x1ae5, /* VGETMANTPDZ128rrik */ +/* Table18535 */ + 0x1b1b, /* VGETMANTSDZrmik */ + 0x1b21, /* VGETMANTSDZrrik */ +/* Table18537 */ + 0x24d1, /* VPCMPUWZ128rmik */ + 0x24d5, /* VPCMPUWZ128rrik */ +/* Table18539 */ + 0x24e9, /* VPCMPWZ128rmik */ + 0x24ed, /* VPCMPWZ128rrik */ +/* Table18541 */ + 0x36e9, /* VRANGEPDZ128rmik */ + 0x36ec, /* VRANGEPDZ128rrik */ +/* Table18543 */ + 0x3722, /* VRANGESDZrmik */ + 0x3728, /* VRANGESDZrrik */ +/* Table18545 */ + 0x130a, /* VFIXUPIMMPDZ128rmik */ + 0x130d, /* VFIXUPIMMPDZ128rrik */ +/* Table18547 */ + 0x1343, /* VFIXUPIMMSDZrmik */ + 0x1349, /* VFIXUPIMMSDZrrik */ +/* Table18549 */ + 0x37ab, /* VREDUCEPDZ128rmik */ + 0x37ae, /* VREDUCEPDZ128rrik */ +/* Table18551 */ + 0x37e4, /* VREDUCESDZrmik */ + 0x37ea, /* VREDUCESDZrrik */ +/* Table18553 */ + 0x1a3f, /* VFPCLASSPDZ128rmk */ + 0x1a41, /* VFPCLASSPDZ128rrk */ +/* Table18555 */ + 0x1a61, /* VFPCLASSSDZrmk */ + 0x1a63, /* VFPCLASSSDZrrk */ +/* Table18557 */ + 0x3097, /* VPSHLDWZ128rmik */ + 0x309a, /* VPSHLDWZ128rrik */ +/* Table18559 */ + 0x3037, /* VPSHLDQZ128rmik */ + 0x303a, /* VPSHLDQZ128rrik */ +/* Table18561 */ + 0x3133, /* VPSHRDWZ128rmik */ + 0x3136, /* VPSHRDWZ128rrik */ +/* Table18563 */ + 0x30d3, /* VPSHRDQZ128rmik */ + 0x30d6, /* VPSHRDQZ128rrik */ +/* Table18565 */ + 0x1b51, /* VGF2P8AFFINEQBZ128rmik */ + 0x1b54, /* VGF2P8AFFINEQBZ128rrik */ +/* Table18567 */ + 0x1b32, /* VGF2P8AFFINEINVQBZ128rmik */ + 0x1b35, /* VGF2P8AFFINEINVQBZ128rrik */ +/* Table18569 */ + 0xbfb, /* VALIGNDZ256rmik */ + 0xbfe, /* VALIGNDZ256rrik */ +/* Table18571 */ + 0x271f, /* VPERMILPSZ256mik */ + 0x2722, /* VPERMILPSZ256rik */ +/* Table18573 */ + 0x3820, /* VRNDSCALEPSZ256rmik */ + 0x3823, /* VRNDSCALEPSZ256rrik */ +/* Table18575 */ + 0x21c8, /* VPALIGNRZ256rmik */ + 0x21cb, /* VPALIGNRZ256rrik */ +/* Table18577 */ + 0x1b93, /* VINSERTF32x4Z256rmk */ + 0x1b96, /* VINSERTF32x4Z256rrk */ +/* Table18579 */ + 0x12c5, /* VEXTRACTF32x4Z256mrk */ + 0x12c7, /* VEXTRACTF32x4Z256rrk */ +/* Table18581 */ + 0xf4a, /* VCVTPS2PHZ256mrk */ + 0xf4c, /* VCVTPS2PHZ256rrk */ +/* Table18583 */ + 0x2499, /* VPCMPUDZ256rmik */ + 0x249d, /* VPCMPUDZ256rrik */ +/* Table18585 */ + 0x2399, /* VPCMPDZ256rmik */ + 0x239d, /* VPCMPDZ256rrik */ +/* Table18587 */ + 0x3931, /* VSHUFF32X4Z256rmik */ + 0x3934, /* VSHUFF32X4Z256rrik */ +/* Table18589 */ + 0x3532, /* VPTERNLOGDZ256rmik */ + 0x3535, /* VPTERNLOGDZ256rrik */ +/* Table18591 */ + 0x1b09, /* VGETMANTPSZ256rmik */ + 0x1b0c, /* VGETMANTPSZ256rrik */ +/* Table18593 */ + 0x1bb9, /* VINSERTI32x4Z256rmk */ + 0x1bbc, /* VINSERTI32x4Z256rrk */ +/* Table18595 */ + 0x12e5, /* VEXTRACTI32x4Z256mrk */ + 0x12e7, /* VEXTRACTI32x4Z256rrk */ +/* Table18597 */ + 0x2479, /* VPCMPUBZ256rmik */ + 0x247d, /* VPCMPUBZ256rrik */ +/* Table18599 */ + 0x2379, /* VPCMPBZ256rmik */ + 0x237d, /* VPCMPBZ256rrik */ +/* Table18601 */ + 0x120f, /* VDBPSADBWZ256rmik */ + 0x1212, /* VDBPSADBWZ256rrik */ +/* Table18603 */ + 0x3955, /* VSHUFI32X4Z256rmik */ + 0x3958, /* VSHUFI32X4Z256rrik */ +/* Table18605 */ + 0x3710, /* VRANGEPSZ256rmik */ + 0x3713, /* VRANGEPSZ256rrik */ +/* Table18607 */ + 0x1331, /* VFIXUPIMMPSZ256rmik */ + 0x1334, /* VFIXUPIMMPSZ256rrik */ +/* Table18609 */ + 0x37d2, /* VREDUCEPSZ256rmik */ + 0x37d5, /* VREDUCEPSZ256rrik */ +/* Table18611 */ + 0x1a57, /* VFPCLASSPSZ256rmk */ + 0x1a59, /* VFPCLASSPSZ256rrk */ +/* Table18613 */ + 0x3025, /* VPSHLDDZ256rmik */ + 0x3028, /* VPSHLDDZ256rrik */ +/* Table18615 */ + 0x30c1, /* VPSHRDDZ256rmik */ + 0x30c4, /* VPSHRDDZ256rrik */ +/* Table18617 */ + 0x2783, /* VPERMQZ256mik */ + 0x2786, /* VPERMQZ256rik */ +/* Table18619 */ + 0x2749, /* VPERMPDZ256mik */ + 0x274c, /* VPERMPDZ256rik */ +/* Table18621 */ + 0xc16, /* VALIGNQZ256rmik */ + 0xc19, /* VALIGNQZ256rrik */ +/* Table18623 */ + 0x26e1, /* VPERMILPDZ256mik */ + 0x26e4, /* VPERMILPDZ256rik */ +/* Table18625 */ + 0x3802, /* VRNDSCALEPDZ256rmik */ + 0x3805, /* VRNDSCALEPDZ256rrik */ +/* Table18627 */ + 0x1ba5, /* VINSERTF64x2Z256rmk */ + 0x1ba8, /* VINSERTF64x2Z256rrk */ +/* Table18629 */ + 0x12d4, /* VEXTRACTF64x2Z256mrk */ + 0x12d6, /* VEXTRACTF64x2Z256rrk */ +/* Table18631 */ + 0x24bd, /* VPCMPUQZ256rmik */ + 0x24c1, /* VPCMPUQZ256rrik */ +/* Table18633 */ + 0x245d, /* VPCMPQZ256rmik */ + 0x2461, /* VPCMPQZ256rrik */ +/* Table18635 */ + 0x3943, /* VSHUFF64X2Z256rmik */ + 0x3946, /* VSHUFF64X2Z256rrik */ +/* Table18637 */ + 0x354d, /* VPTERNLOGQZ256rmik */ + 0x3550, /* VPTERNLOGQZ256rrik */ +/* Table18639 */ + 0x1aeb, /* VGETMANTPDZ256rmik */ + 0x1aee, /* VGETMANTPDZ256rrik */ +/* Table18641 */ + 0x1bcb, /* VINSERTI64x2Z256rmk */ + 0x1bce, /* VINSERTI64x2Z256rrk */ +/* Table18643 */ + 0x12f4, /* VEXTRACTI64x2Z256mrk */ + 0x12f6, /* VEXTRACTI64x2Z256rrk */ +/* Table18645 */ + 0x24d9, /* VPCMPUWZ256rmik */ + 0x24dd, /* VPCMPUWZ256rrik */ +/* Table18647 */ + 0x24f1, /* VPCMPWZ256rmik */ + 0x24f5, /* VPCMPWZ256rrik */ +/* Table18649 */ + 0x3967, /* VSHUFI64X2Z256rmik */ + 0x396a, /* VSHUFI64X2Z256rrik */ +/* Table18651 */ + 0x36f2, /* VRANGEPDZ256rmik */ + 0x36f5, /* VRANGEPDZ256rrik */ +/* Table18653 */ + 0x1313, /* VFIXUPIMMPDZ256rmik */ + 0x1316, /* VFIXUPIMMPDZ256rrik */ +/* Table18655 */ + 0x37b4, /* VREDUCEPDZ256rmik */ + 0x37b7, /* VREDUCEPDZ256rrik */ +/* Table18657 */ + 0x1a45, /* VFPCLASSPDZ256rmk */ + 0x1a47, /* VFPCLASSPDZ256rrk */ +/* Table18659 */ + 0x309d, /* VPSHLDWZ256rmik */ + 0x30a0, /* VPSHLDWZ256rrik */ +/* Table18661 */ + 0x3040, /* VPSHLDQZ256rmik */ + 0x3043, /* VPSHLDQZ256rrik */ +/* Table18663 */ + 0x3139, /* VPSHRDWZ256rmik */ + 0x313c, /* VPSHRDWZ256rrik */ +/* Table18665 */ + 0x30dc, /* VPSHRDQZ256rmik */ + 0x30df, /* VPSHRDQZ256rrik */ +/* Table18667 */ + 0x1b5a, /* VGF2P8AFFINEQBZ256rmik */ + 0x1b5d, /* VGF2P8AFFINEQBZ256rrik */ +/* Table18669 */ + 0x1b3b, /* VGF2P8AFFINEINVQBZ256rmik */ + 0x1b3e, /* VGF2P8AFFINEINVQBZ256rrik */ +/* Table18671 */ + 0xc04, /* VALIGNDZrmik */ + 0xc07, /* VALIGNDZrrik */ +/* Table18673 */ + 0x2731, /* VPERMILPSZmik */ + 0x2734, /* VPERMILPSZrik */ +/* Table18675 */ + 0x3829, /* VRNDSCALEPSZrmik */ + 0x382f, /* VRNDSCALEPSZrrik */ +/* Table18677 */ + 0x21ce, /* VPALIGNRZrmik */ + 0x21d1, /* VPALIGNRZrrik */ +/* Table18679 */ + 0x1b99, /* VINSERTF32x4Zrmk */ + 0x1b9c, /* VINSERTF32x4Zrrk */ +/* Table18681 */ + 0x12ca, /* VEXTRACTF32x4Zmrk */ + 0x12cc, /* VEXTRACTF32x4Zrrk */ +/* Table18683 */ + 0x1b9f, /* VINSERTF32x8Zrmk */ + 0x1ba2, /* VINSERTF32x8Zrrk */ +/* Table18685 */ + 0x12cf, /* VEXTRACTF32x8Zmrk */ + 0x12d1, /* VEXTRACTF32x8Zrrk */ +/* Table18687 */ + 0xf4f, /* VCVTPS2PHZmrk */ + 0xf54, /* VCVTPS2PHZrrk */ +/* Table18689 */ + 0x24a5, /* VPCMPUDZrmik */ + 0x24a9, /* VPCMPUDZrrik */ +/* Table18691 */ + 0x23a5, /* VPCMPDZrmik */ + 0x23a9, /* VPCMPDZrrik */ +/* Table18693 */ + 0x393a, /* VSHUFF32X4Zrmik */ + 0x393d, /* VSHUFF32X4Zrrik */ +/* Table18695 */ + 0x353b, /* VPTERNLOGDZrmik */ + 0x353e, /* VPTERNLOGDZrrik */ +/* Table18697 */ + 0x1b12, /* VGETMANTPSZrmik */ + 0x1b18, /* VGETMANTPSZrrik */ +/* Table18699 */ + 0x1bbf, /* VINSERTI32x4Zrmk */ + 0x1bc2, /* VINSERTI32x4Zrrk */ +/* Table18701 */ + 0x12ea, /* VEXTRACTI32x4Zmrk */ + 0x12ec, /* VEXTRACTI32x4Zrrk */ +/* Table18703 */ + 0x1bc5, /* VINSERTI32x8Zrmk */ + 0x1bc8, /* VINSERTI32x8Zrrk */ +/* Table18705 */ + 0x12ef, /* VEXTRACTI32x8Zmrk */ + 0x12f1, /* VEXTRACTI32x8Zrrk */ +/* Table18707 */ + 0x2481, /* VPCMPUBZrmik */ + 0x2485, /* VPCMPUBZrrik */ +/* Table18709 */ + 0x2381, /* VPCMPBZrmik */ + 0x2385, /* VPCMPBZrrik */ +/* Table18711 */ + 0x1215, /* VDBPSADBWZrmik */ + 0x1218, /* VDBPSADBWZrrik */ +/* Table18713 */ + 0x395e, /* VSHUFI32X4Zrmik */ + 0x3961, /* VSHUFI32X4Zrrik */ +/* Table18715 */ + 0x3719, /* VRANGEPSZrmik */ + 0x371f, /* VRANGEPSZrrik */ +/* Table18717 */ + 0x133a, /* VFIXUPIMMPSZrmik */ + 0x1340, /* VFIXUPIMMPSZrrik */ +/* Table18719 */ + 0x37db, /* VREDUCEPSZrmik */ + 0x37e1, /* VREDUCEPSZrrik */ +/* Table18721 */ + 0x1a5d, /* VFPCLASSPSZrmk */ + 0x1a5f, /* VFPCLASSPSZrrk */ +/* Table18723 */ + 0x302e, /* VPSHLDDZrmik */ + 0x3031, /* VPSHLDDZrrik */ +/* Table18725 */ + 0x30ca, /* VPSHRDDZrmik */ + 0x30cd, /* VPSHRDDZrrik */ +/* Table18727 */ + 0x2795, /* VPERMQZmik */ + 0x2798, /* VPERMQZrik */ +/* Table18729 */ + 0x275b, /* VPERMPDZmik */ + 0x275e, /* VPERMPDZrik */ +/* Table18731 */ + 0xc1f, /* VALIGNQZrmik */ + 0xc22, /* VALIGNQZrrik */ +/* Table18733 */ + 0x26f3, /* VPERMILPDZmik */ + 0x26f6, /* VPERMILPDZrik */ +/* Table18735 */ + 0x380b, /* VRNDSCALEPDZrmik */ + 0x3811, /* VRNDSCALEPDZrrik */ +/* Table18737 */ + 0x1bab, /* VINSERTF64x2Zrmk */ + 0x1bae, /* VINSERTF64x2Zrrk */ +/* Table18739 */ + 0x12d9, /* VEXTRACTF64x2Zmrk */ + 0x12db, /* VEXTRACTF64x2Zrrk */ +/* Table18741 */ + 0x1bb1, /* VINSERTF64x4Zrmk */ + 0x1bb4, /* VINSERTF64x4Zrrk */ +/* Table18743 */ + 0x12de, /* VEXTRACTF64x4Zmrk */ + 0x12e0, /* VEXTRACTF64x4Zrrk */ +/* Table18745 */ + 0x24c9, /* VPCMPUQZrmik */ + 0x24cd, /* VPCMPUQZrrik */ +/* Table18747 */ + 0x2469, /* VPCMPQZrmik */ + 0x246d, /* VPCMPQZrrik */ +/* Table18749 */ + 0x394c, /* VSHUFF64X2Zrmik */ + 0x394f, /* VSHUFF64X2Zrrik */ +/* Table18751 */ + 0x3556, /* VPTERNLOGQZrmik */ + 0x3559, /* VPTERNLOGQZrrik */ +/* Table18753 */ + 0x1af4, /* VGETMANTPDZrmik */ + 0x1afa, /* VGETMANTPDZrrik */ +/* Table18755 */ + 0x1bd1, /* VINSERTI64x2Zrmk */ + 0x1bd4, /* VINSERTI64x2Zrrk */ +/* Table18757 */ + 0x12f9, /* VEXTRACTI64x2Zmrk */ + 0x12fb, /* VEXTRACTI64x2Zrrk */ +/* Table18759 */ + 0x1bd7, /* VINSERTI64x4Zrmk */ + 0x1bda, /* VINSERTI64x4Zrrk */ +/* Table18761 */ + 0x12fe, /* VEXTRACTI64x4Zmrk */ + 0x1300, /* VEXTRACTI64x4Zrrk */ +/* Table18763 */ + 0x24e1, /* VPCMPUWZrmik */ + 0x24e5, /* VPCMPUWZrrik */ +/* Table18765 */ + 0x24f9, /* VPCMPWZrmik */ + 0x24fd, /* VPCMPWZrrik */ +/* Table18767 */ + 0x3970, /* VSHUFI64X2Zrmik */ + 0x3973, /* VSHUFI64X2Zrrik */ +/* Table18769 */ + 0x36fb, /* VRANGEPDZrmik */ + 0x3701, /* VRANGEPDZrrik */ +/* Table18771 */ + 0x131c, /* VFIXUPIMMPDZrmik */ + 0x1322, /* VFIXUPIMMPDZrrik */ +/* Table18773 */ + 0x37bd, /* VREDUCEPDZrmik */ + 0x37c3, /* VREDUCEPDZrrik */ +/* Table18775 */ + 0x1a4b, /* VFPCLASSPDZrmk */ + 0x1a4d, /* VFPCLASSPDZrrk */ +/* Table18777 */ + 0x30a3, /* VPSHLDWZrmik */ + 0x30a6, /* VPSHLDWZrrik */ +/* Table18779 */ + 0x3049, /* VPSHLDQZrmik */ + 0x304c, /* VPSHLDQZrrik */ +/* Table18781 */ + 0x313f, /* VPSHRDWZrmik */ + 0x3142, /* VPSHRDWZrrik */ +/* Table18783 */ + 0x30e5, /* VPSHRDQZrmik */ + 0x30e8, /* VPSHRDQZrrik */ +/* Table18785 */ + 0x1b63, /* VGF2P8AFFINEQBZrmik */ + 0x1b66, /* VGF2P8AFFINEQBZrrik */ +/* Table18787 */ + 0x1b44, /* VGF2P8AFFINEINVQBZrmik */ + 0x1b47, /* VGF2P8AFFINEINVQBZrrik */ +/* Table18789 */ + 0xbee, /* VALIGNDZ128rmbi */ + 0x0, /* */ +/* Table18791 */ + 0x2709, /* VPERMILPSZ128mbi */ + 0x0, /* */ +/* Table18793 */ + 0x3813, /* VRNDSCALEPSZ128rmbi */ + 0x382c, /* VRNDSCALEPSZrrib */ +/* Table18795 */ + 0x0, /* */ + 0x3844, /* VRNDSCALESSZrb_Int */ +/* Table18797 */ + 0x0, /* */ + 0xf51, /* VCVTPS2PHZrrb */ +/* Table18799 */ + 0x2489, /* VPCMPUDZ128rmib */ + 0x0, /* */ +/* Table18801 */ + 0x2389, /* VPCMPDZ128rmib */ + 0x0, /* */ +/* Table18803 */ + 0x3525, /* VPTERNLOGDZ128rmbi */ + 0x0, /* */ +/* Table18805 */ + 0x1afc, /* VGETMANTPSZ128rmbi */ + 0x1b15, /* VGETMANTPSZrrib */ +/* Table18807 */ + 0x0, /* */ + 0x1b27, /* VGETMANTSSZrrib */ +/* Table18809 */ + 0x3703, /* VRANGEPSZ128rmbi */ + 0x371c, /* VRANGEPSZrrib */ +/* Table18811 */ + 0x0, /* */ + 0x372e, /* VRANGESSZrrib */ +/* Table18813 */ + 0x1324, /* VFIXUPIMMPSZ128rmbi */ + 0x133d, /* VFIXUPIMMPSZrrib */ +/* Table18815 */ + 0x0, /* */ + 0x134f, /* VFIXUPIMMSSZrrib */ +/* Table18817 */ + 0x37c5, /* VREDUCEPSZ128rmbi */ + 0x37de, /* VREDUCEPSZrrib */ +/* Table18819 */ + 0x0, /* */ + 0x37f0, /* VREDUCESSZrrib */ +/* Table18821 */ + 0x1a4f, /* VFPCLASSPSZ128rmb */ + 0x0, /* */ +/* Table18823 */ + 0x3018, /* VPSHLDDZ128rmbi */ + 0x0, /* */ +/* Table18825 */ + 0x30b4, /* VPSHRDDZ128rmbi */ + 0x0, /* */ +/* Table18827 */ + 0xc09, /* VALIGNQZ128rmbi */ + 0x0, /* */ +/* Table18829 */ + 0x26cb, /* VPERMILPDZ128mbi */ + 0x0, /* */ +/* Table18831 */ + 0x37f5, /* VRNDSCALEPDZ128rmbi */ + 0x380e, /* VRNDSCALEPDZrrib */ +/* Table18833 */ + 0x0, /* */ + 0x3839, /* VRNDSCALESDZrb_Int */ +/* Table18835 */ + 0x24ad, /* VPCMPUQZ128rmib */ + 0x0, /* */ +/* Table18837 */ + 0x244d, /* VPCMPQZ128rmib */ + 0x0, /* */ +/* Table18839 */ + 0x3540, /* VPTERNLOGQZ128rmbi */ + 0x0, /* */ +/* Table18841 */ + 0x1ade, /* VGETMANTPDZ128rmbi */ + 0x1af7, /* VGETMANTPDZrrib */ +/* Table18843 */ + 0x0, /* */ + 0x1b1e, /* VGETMANTSDZrrib */ +/* Table18845 */ + 0x36e5, /* VRANGEPDZ128rmbi */ + 0x36fe, /* VRANGEPDZrrib */ +/* Table18847 */ + 0x0, /* */ + 0x3725, /* VRANGESDZrrib */ +/* Table18849 */ + 0x1306, /* VFIXUPIMMPDZ128rmbi */ + 0x131f, /* VFIXUPIMMPDZrrib */ +/* Table18851 */ + 0x0, /* */ + 0x1346, /* VFIXUPIMMSDZrrib */ +/* Table18853 */ + 0x37a7, /* VREDUCEPDZ128rmbi */ + 0x37c0, /* VREDUCEPDZrrib */ +/* Table18855 */ + 0x0, /* */ + 0x37e7, /* VREDUCESDZrrib */ +/* Table18857 */ + 0x1a3d, /* VFPCLASSPDZ128rmb */ + 0x0, /* */ +/* Table18859 */ + 0x3033, /* VPSHLDQZ128rmbi */ + 0x0, /* */ +/* Table18861 */ + 0x30cf, /* VPSHRDQZ128rmbi */ + 0x0, /* */ +/* Table18863 */ + 0x1b4d, /* VGF2P8AFFINEQBZ128rmbi */ + 0x0, /* */ +/* Table18865 */ + 0x1b2e, /* VGF2P8AFFINEINVQBZ128rmbi */ + 0x0, /* */ +/* Table18867 */ + 0xbf7, /* VALIGNDZ256rmbi */ + 0x0, /* */ +/* Table18869 */ + 0x271b, /* VPERMILPSZ256mbi */ + 0x0, /* */ +/* Table18871 */ + 0x381c, /* VRNDSCALEPSZ256rmbi */ + 0x382c, /* VRNDSCALEPSZrrib */ +/* Table18873 */ + 0x2495, /* VPCMPUDZ256rmib */ + 0x0, /* */ +/* Table18875 */ + 0x2395, /* VPCMPDZ256rmib */ + 0x0, /* */ +/* Table18877 */ + 0x392d, /* VSHUFF32X4Z256rmbi */ + 0x0, /* */ +/* Table18879 */ + 0x352e, /* VPTERNLOGDZ256rmbi */ + 0x0, /* */ +/* Table18881 */ + 0x1b05, /* VGETMANTPSZ256rmbi */ + 0x1b15, /* VGETMANTPSZrrib */ +/* Table18883 */ + 0x3951, /* VSHUFI32X4Z256rmbi */ + 0x0, /* */ +/* Table18885 */ + 0x370c, /* VRANGEPSZ256rmbi */ + 0x371c, /* VRANGEPSZrrib */ +/* Table18887 */ + 0x132d, /* VFIXUPIMMPSZ256rmbi */ + 0x133d, /* VFIXUPIMMPSZrrib */ +/* Table18889 */ + 0x37ce, /* VREDUCEPSZ256rmbi */ + 0x37de, /* VREDUCEPSZrrib */ +/* Table18891 */ + 0x1a55, /* VFPCLASSPSZ256rmb */ + 0x0, /* */ +/* Table18893 */ + 0x3021, /* VPSHLDDZ256rmbi */ + 0x0, /* */ +/* Table18895 */ + 0x30bd, /* VPSHRDDZ256rmbi */ + 0x0, /* */ +/* Table18897 */ + 0x277f, /* VPERMQZ256mbi */ + 0x0, /* */ +/* Table18899 */ + 0x2745, /* VPERMPDZ256mbi */ + 0x0, /* */ +/* Table18901 */ + 0xc12, /* VALIGNQZ256rmbi */ + 0x0, /* */ +/* Table18903 */ + 0x26dd, /* VPERMILPDZ256mbi */ + 0x0, /* */ +/* Table18905 */ + 0x37fe, /* VRNDSCALEPDZ256rmbi */ + 0x380e, /* VRNDSCALEPDZrrib */ +/* Table18907 */ + 0x24b9, /* VPCMPUQZ256rmib */ + 0x0, /* */ +/* Table18909 */ + 0x2459, /* VPCMPQZ256rmib */ + 0x0, /* */ +/* Table18911 */ + 0x393f, /* VSHUFF64X2Z256rmbi */ + 0x0, /* */ +/* Table18913 */ + 0x3549, /* VPTERNLOGQZ256rmbi */ + 0x0, /* */ +/* Table18915 */ + 0x1ae7, /* VGETMANTPDZ256rmbi */ + 0x1af7, /* VGETMANTPDZrrib */ +/* Table18917 */ + 0x3963, /* VSHUFI64X2Z256rmbi */ + 0x0, /* */ +/* Table18919 */ + 0x36ee, /* VRANGEPDZ256rmbi */ + 0x36fe, /* VRANGEPDZrrib */ +/* Table18921 */ + 0x130f, /* VFIXUPIMMPDZ256rmbi */ + 0x131f, /* VFIXUPIMMPDZrrib */ +/* Table18923 */ + 0x37b0, /* VREDUCEPDZ256rmbi */ + 0x37c0, /* VREDUCEPDZrrib */ +/* Table18925 */ + 0x1a43, /* VFPCLASSPDZ256rmb */ + 0x0, /* */ +/* Table18927 */ + 0x303c, /* VPSHLDQZ256rmbi */ + 0x0, /* */ +/* Table18929 */ + 0x30d8, /* VPSHRDQZ256rmbi */ + 0x0, /* */ +/* Table18931 */ + 0x1b56, /* VGF2P8AFFINEQBZ256rmbi */ + 0x0, /* */ +/* Table18933 */ + 0x1b37, /* VGF2P8AFFINEINVQBZ256rmbi */ + 0x0, /* */ +/* Table18935 */ + 0xc00, /* VALIGNDZrmbi */ + 0x0, /* */ +/* Table18937 */ + 0x272d, /* VPERMILPSZmbi */ + 0x0, /* */ +/* Table18939 */ + 0x3825, /* VRNDSCALEPSZrmbi */ + 0x382c, /* VRNDSCALEPSZrrib */ +/* Table18941 */ + 0x24a1, /* VPCMPUDZrmib */ + 0x0, /* */ +/* Table18943 */ + 0x23a1, /* VPCMPDZrmib */ + 0x0, /* */ +/* Table18945 */ + 0x3936, /* VSHUFF32X4Zrmbi */ + 0x0, /* */ +/* Table18947 */ + 0x3537, /* VPTERNLOGDZrmbi */ + 0x0, /* */ +/* Table18949 */ + 0x1b0e, /* VGETMANTPSZrmbi */ + 0x1b15, /* VGETMANTPSZrrib */ +/* Table18951 */ + 0x395a, /* VSHUFI32X4Zrmbi */ + 0x0, /* */ +/* Table18953 */ + 0x3715, /* VRANGEPSZrmbi */ + 0x371c, /* VRANGEPSZrrib */ +/* Table18955 */ + 0x1336, /* VFIXUPIMMPSZrmbi */ + 0x133d, /* VFIXUPIMMPSZrrib */ +/* Table18957 */ + 0x37d7, /* VREDUCEPSZrmbi */ + 0x37de, /* VREDUCEPSZrrib */ +/* Table18959 */ + 0x1a5b, /* VFPCLASSPSZrmb */ + 0x0, /* */ +/* Table18961 */ + 0x302a, /* VPSHLDDZrmbi */ + 0x0, /* */ +/* Table18963 */ + 0x30c6, /* VPSHRDDZrmbi */ + 0x0, /* */ +/* Table18965 */ + 0x2791, /* VPERMQZmbi */ + 0x0, /* */ +/* Table18967 */ + 0x2757, /* VPERMPDZmbi */ + 0x0, /* */ +/* Table18969 */ + 0xc1b, /* VALIGNQZrmbi */ + 0x0, /* */ +/* Table18971 */ + 0x26ef, /* VPERMILPDZmbi */ + 0x0, /* */ +/* Table18973 */ + 0x3807, /* VRNDSCALEPDZrmbi */ + 0x380e, /* VRNDSCALEPDZrrib */ +/* Table18975 */ + 0x24c5, /* VPCMPUQZrmib */ + 0x0, /* */ +/* Table18977 */ + 0x2465, /* VPCMPQZrmib */ + 0x0, /* */ +/* Table18979 */ + 0x3948, /* VSHUFF64X2Zrmbi */ + 0x0, /* */ +/* Table18981 */ + 0x3552, /* VPTERNLOGQZrmbi */ + 0x0, /* */ +/* Table18983 */ + 0x1af0, /* VGETMANTPDZrmbi */ + 0x1af7, /* VGETMANTPDZrrib */ +/* Table18985 */ + 0x396c, /* VSHUFI64X2Zrmbi */ + 0x0, /* */ +/* Table18987 */ + 0x36f7, /* VRANGEPDZrmbi */ + 0x36fe, /* VRANGEPDZrrib */ +/* Table18989 */ + 0x1318, /* VFIXUPIMMPDZrmbi */ + 0x131f, /* VFIXUPIMMPDZrrib */ +/* Table18991 */ + 0x37b9, /* VREDUCEPDZrmbi */ + 0x37c0, /* VREDUCEPDZrrib */ +/* Table18993 */ + 0x1a49, /* VFPCLASSPDZrmb */ + 0x0, /* */ +/* Table18995 */ + 0x3045, /* VPSHLDQZrmbi */ + 0x0, /* */ +/* Table18997 */ + 0x30e1, /* VPSHRDQZrmbi */ + 0x0, /* */ +/* Table18999 */ + 0x1b5f, /* VGF2P8AFFINEQBZrmbi */ + 0x0, /* */ +/* Table19001 */ + 0x1b40, /* VGF2P8AFFINEINVQBZrmbi */ + 0x0, /* */ +/* Table19003 */ + 0xbef, /* VALIGNDZ128rmbik */ + 0x0, /* */ +/* Table19005 */ + 0x270a, /* VPERMILPSZ128mbik */ + 0x0, /* */ +/* Table19007 */ + 0x3814, /* VRNDSCALEPSZ128rmbik */ + 0x382d, /* VRNDSCALEPSZrribk */ +/* Table19009 */ + 0x0, /* */ + 0x3845, /* VRNDSCALESSZrb_Intk */ +/* Table19011 */ + 0x0, /* */ + 0xf52, /* VCVTPS2PHZrrbk */ +/* Table19013 */ + 0x248b, /* VPCMPUDZ128rmibk */ + 0x0, /* */ +/* Table19015 */ + 0x238b, /* VPCMPDZ128rmibk */ + 0x0, /* */ +/* Table19017 */ + 0x3526, /* VPTERNLOGDZ128rmbik */ + 0x0, /* */ +/* Table19019 */ + 0x1afd, /* VGETMANTPSZ128rmbik */ + 0x1b16, /* VGETMANTPSZrribk */ +/* Table19021 */ + 0x0, /* */ + 0x1b28, /* VGETMANTSSZrribk */ +/* Table19023 */ + 0x3704, /* VRANGEPSZ128rmbik */ + 0x371d, /* VRANGEPSZrribk */ +/* Table19025 */ + 0x0, /* */ + 0x372f, /* VRANGESSZrribk */ +/* Table19027 */ + 0x1325, /* VFIXUPIMMPSZ128rmbik */ + 0x133e, /* VFIXUPIMMPSZrribk */ +/* Table19029 */ + 0x0, /* */ + 0x1350, /* VFIXUPIMMSSZrribk */ +/* Table19031 */ + 0x37c6, /* VREDUCEPSZ128rmbik */ + 0x37df, /* VREDUCEPSZrribk */ +/* Table19033 */ + 0x0, /* */ + 0x37f1, /* VREDUCESSZrribk */ +/* Table19035 */ + 0x1a50, /* VFPCLASSPSZ128rmbk */ + 0x0, /* */ +/* Table19037 */ + 0x3019, /* VPSHLDDZ128rmbik */ + 0x0, /* */ +/* Table19039 */ + 0x30b5, /* VPSHRDDZ128rmbik */ + 0x0, /* */ +/* Table19041 */ + 0xc0a, /* VALIGNQZ128rmbik */ + 0x0, /* */ +/* Table19043 */ + 0x26cc, /* VPERMILPDZ128mbik */ + 0x0, /* */ +/* Table19045 */ + 0x37f6, /* VRNDSCALEPDZ128rmbik */ + 0x380f, /* VRNDSCALEPDZrribk */ +/* Table19047 */ + 0x0, /* */ + 0x383a, /* VRNDSCALESDZrb_Intk */ +/* Table19049 */ + 0x24af, /* VPCMPUQZ128rmibk */ + 0x0, /* */ +/* Table19051 */ + 0x244f, /* VPCMPQZ128rmibk */ + 0x0, /* */ +/* Table19053 */ + 0x3541, /* VPTERNLOGQZ128rmbik */ + 0x0, /* */ +/* Table19055 */ + 0x1adf, /* VGETMANTPDZ128rmbik */ + 0x1af8, /* VGETMANTPDZrribk */ +/* Table19057 */ + 0x0, /* */ + 0x1b1f, /* VGETMANTSDZrribk */ +/* Table19059 */ + 0x36e6, /* VRANGEPDZ128rmbik */ + 0x36ff, /* VRANGEPDZrribk */ +/* Table19061 */ + 0x0, /* */ + 0x3726, /* VRANGESDZrribk */ +/* Table19063 */ + 0x1307, /* VFIXUPIMMPDZ128rmbik */ + 0x1320, /* VFIXUPIMMPDZrribk */ +/* Table19065 */ + 0x0, /* */ + 0x1347, /* VFIXUPIMMSDZrribk */ +/* Table19067 */ + 0x37a8, /* VREDUCEPDZ128rmbik */ + 0x37c1, /* VREDUCEPDZrribk */ +/* Table19069 */ + 0x0, /* */ + 0x37e8, /* VREDUCESDZrribk */ +/* Table19071 */ + 0x1a3e, /* VFPCLASSPDZ128rmbk */ + 0x0, /* */ +/* Table19073 */ + 0x3034, /* VPSHLDQZ128rmbik */ + 0x0, /* */ +/* Table19075 */ + 0x30d0, /* VPSHRDQZ128rmbik */ + 0x0, /* */ +/* Table19077 */ + 0x1b4e, /* VGF2P8AFFINEQBZ128rmbik */ + 0x0, /* */ +/* Table19079 */ + 0x1b2f, /* VGF2P8AFFINEINVQBZ128rmbik */ + 0x0, /* */ +/* Table19081 */ + 0xbf8, /* VALIGNDZ256rmbik */ + 0x0, /* */ +/* Table19083 */ + 0x271c, /* VPERMILPSZ256mbik */ + 0x0, /* */ +/* Table19085 */ + 0x381d, /* VRNDSCALEPSZ256rmbik */ + 0x382d, /* VRNDSCALEPSZrribk */ +/* Table19087 */ + 0x2497, /* VPCMPUDZ256rmibk */ + 0x0, /* */ +/* Table19089 */ + 0x2397, /* VPCMPDZ256rmibk */ + 0x0, /* */ +/* Table19091 */ + 0x392e, /* VSHUFF32X4Z256rmbik */ + 0x0, /* */ +/* Table19093 */ + 0x352f, /* VPTERNLOGDZ256rmbik */ + 0x0, /* */ +/* Table19095 */ + 0x1b06, /* VGETMANTPSZ256rmbik */ + 0x1b16, /* VGETMANTPSZrribk */ +/* Table19097 */ + 0x3952, /* VSHUFI32X4Z256rmbik */ + 0x0, /* */ +/* Table19099 */ + 0x370d, /* VRANGEPSZ256rmbik */ + 0x371d, /* VRANGEPSZrribk */ +/* Table19101 */ + 0x132e, /* VFIXUPIMMPSZ256rmbik */ + 0x133e, /* VFIXUPIMMPSZrribk */ +/* Table19103 */ + 0x37cf, /* VREDUCEPSZ256rmbik */ + 0x37df, /* VREDUCEPSZrribk */ +/* Table19105 */ + 0x1a56, /* VFPCLASSPSZ256rmbk */ + 0x0, /* */ +/* Table19107 */ + 0x3022, /* VPSHLDDZ256rmbik */ + 0x0, /* */ +/* Table19109 */ + 0x30be, /* VPSHRDDZ256rmbik */ + 0x0, /* */ +/* Table19111 */ + 0x2780, /* VPERMQZ256mbik */ + 0x0, /* */ +/* Table19113 */ + 0x2746, /* VPERMPDZ256mbik */ + 0x0, /* */ +/* Table19115 */ + 0xc13, /* VALIGNQZ256rmbik */ + 0x0, /* */ +/* Table19117 */ + 0x26de, /* VPERMILPDZ256mbik */ + 0x0, /* */ +/* Table19119 */ + 0x37ff, /* VRNDSCALEPDZ256rmbik */ + 0x380f, /* VRNDSCALEPDZrribk */ +/* Table19121 */ + 0x24bb, /* VPCMPUQZ256rmibk */ + 0x0, /* */ +/* Table19123 */ + 0x245b, /* VPCMPQZ256rmibk */ + 0x0, /* */ +/* Table19125 */ + 0x3940, /* VSHUFF64X2Z256rmbik */ + 0x0, /* */ +/* Table19127 */ + 0x354a, /* VPTERNLOGQZ256rmbik */ + 0x0, /* */ +/* Table19129 */ + 0x1ae8, /* VGETMANTPDZ256rmbik */ + 0x1af8, /* VGETMANTPDZrribk */ +/* Table19131 */ + 0x3964, /* VSHUFI64X2Z256rmbik */ + 0x0, /* */ +/* Table19133 */ + 0x36ef, /* VRANGEPDZ256rmbik */ + 0x36ff, /* VRANGEPDZrribk */ +/* Table19135 */ + 0x1310, /* VFIXUPIMMPDZ256rmbik */ + 0x1320, /* VFIXUPIMMPDZrribk */ +/* Table19137 */ + 0x37b1, /* VREDUCEPDZ256rmbik */ + 0x37c1, /* VREDUCEPDZrribk */ +/* Table19139 */ + 0x1a44, /* VFPCLASSPDZ256rmbk */ + 0x0, /* */ +/* Table19141 */ + 0x303d, /* VPSHLDQZ256rmbik */ + 0x0, /* */ +/* Table19143 */ + 0x30d9, /* VPSHRDQZ256rmbik */ + 0x0, /* */ +/* Table19145 */ + 0x1b57, /* VGF2P8AFFINEQBZ256rmbik */ + 0x0, /* */ +/* Table19147 */ + 0x1b38, /* VGF2P8AFFINEINVQBZ256rmbik */ + 0x0, /* */ +/* Table19149 */ + 0xc01, /* VALIGNDZrmbik */ + 0x0, /* */ +/* Table19151 */ + 0x272e, /* VPERMILPSZmbik */ + 0x0, /* */ +/* Table19153 */ + 0x3826, /* VRNDSCALEPSZrmbik */ + 0x382d, /* VRNDSCALEPSZrribk */ +/* Table19155 */ + 0x24a3, /* VPCMPUDZrmibk */ + 0x0, /* */ +/* Table19157 */ + 0x23a3, /* VPCMPDZrmibk */ + 0x0, /* */ +/* Table19159 */ + 0x3937, /* VSHUFF32X4Zrmbik */ + 0x0, /* */ +/* Table19161 */ + 0x3538, /* VPTERNLOGDZrmbik */ + 0x0, /* */ +/* Table19163 */ + 0x1b0f, /* VGETMANTPSZrmbik */ + 0x1b16, /* VGETMANTPSZrribk */ +/* Table19165 */ + 0x395b, /* VSHUFI32X4Zrmbik */ + 0x0, /* */ +/* Table19167 */ + 0x3716, /* VRANGEPSZrmbik */ + 0x371d, /* VRANGEPSZrribk */ +/* Table19169 */ + 0x1337, /* VFIXUPIMMPSZrmbik */ + 0x133e, /* VFIXUPIMMPSZrribk */ +/* Table19171 */ + 0x37d8, /* VREDUCEPSZrmbik */ + 0x37df, /* VREDUCEPSZrribk */ +/* Table19173 */ + 0x1a5c, /* VFPCLASSPSZrmbk */ + 0x0, /* */ +/* Table19175 */ + 0x302b, /* VPSHLDDZrmbik */ + 0x0, /* */ +/* Table19177 */ + 0x30c7, /* VPSHRDDZrmbik */ + 0x0, /* */ +/* Table19179 */ + 0x2792, /* VPERMQZmbik */ + 0x0, /* */ +/* Table19181 */ + 0x2758, /* VPERMPDZmbik */ + 0x0, /* */ +/* Table19183 */ + 0xc1c, /* VALIGNQZrmbik */ + 0x0, /* */ +/* Table19185 */ + 0x26f0, /* VPERMILPDZmbik */ + 0x0, /* */ +/* Table19187 */ + 0x3808, /* VRNDSCALEPDZrmbik */ + 0x380f, /* VRNDSCALEPDZrribk */ +/* Table19189 */ + 0x24c7, /* VPCMPUQZrmibk */ + 0x0, /* */ +/* Table19191 */ + 0x2467, /* VPCMPQZrmibk */ + 0x0, /* */ +/* Table19193 */ + 0x3949, /* VSHUFF64X2Zrmbik */ + 0x0, /* */ +/* Table19195 */ + 0x3553, /* VPTERNLOGQZrmbik */ + 0x0, /* */ +/* Table19197 */ + 0x1af1, /* VGETMANTPDZrmbik */ + 0x1af8, /* VGETMANTPDZrribk */ +/* Table19199 */ + 0x396d, /* VSHUFI64X2Zrmbik */ + 0x0, /* */ +/* Table19201 */ + 0x36f8, /* VRANGEPDZrmbik */ + 0x36ff, /* VRANGEPDZrribk */ +/* Table19203 */ + 0x1319, /* VFIXUPIMMPDZrmbik */ + 0x1320, /* VFIXUPIMMPDZrribk */ +/* Table19205 */ + 0x37ba, /* VREDUCEPDZrmbik */ + 0x37c1, /* VREDUCEPDZrribk */ +/* Table19207 */ + 0x1a4a, /* VFPCLASSPDZrmbk */ + 0x0, /* */ +/* Table19209 */ + 0x3046, /* VPSHLDQZrmbik */ + 0x0, /* */ +/* Table19211 */ + 0x30e2, /* VPSHRDQZrmbik */ + 0x0, /* */ +/* Table19213 */ + 0x1b60, /* VGF2P8AFFINEQBZrmbik */ + 0x0, /* */ +/* Table19215 */ + 0x1b41, /* VGF2P8AFFINEINVQBZrmbik */ + 0x0, /* */ +/* Table19217 */ + 0xbf0, /* VALIGNDZ128rmbikz */ + 0x0, /* */ +/* Table19219 */ + 0x270b, /* VPERMILPSZ128mbikz */ + 0x0, /* */ +/* Table19221 */ + 0x3815, /* VRNDSCALEPSZ128rmbikz */ + 0x382e, /* VRNDSCALEPSZrribkz */ +/* Table19223 */ + 0x0, /* */ + 0x3846, /* VRNDSCALESSZrb_Intkz */ +/* Table19225 */ + 0x0, /* */ + 0xf53, /* VCVTPS2PHZrrbkz */ +/* Table19227 */ + 0x3527, /* VPTERNLOGDZ128rmbikz */ + 0x0, /* */ +/* Table19229 */ + 0x1afe, /* VGETMANTPSZ128rmbikz */ + 0x1b17, /* VGETMANTPSZrribkz */ +/* Table19231 */ + 0x0, /* */ + 0x1b29, /* VGETMANTSSZrribkz */ +/* Table19233 */ + 0x3705, /* VRANGEPSZ128rmbikz */ + 0x371e, /* VRANGEPSZrribkz */ +/* Table19235 */ + 0x0, /* */ + 0x3730, /* VRANGESSZrribkz */ +/* Table19237 */ + 0x1326, /* VFIXUPIMMPSZ128rmbikz */ + 0x133f, /* VFIXUPIMMPSZrribkz */ +/* Table19239 */ + 0x0, /* */ + 0x1351, /* VFIXUPIMMSSZrribkz */ +/* Table19241 */ + 0x37c7, /* VREDUCEPSZ128rmbikz */ + 0x37e0, /* VREDUCEPSZrribkz */ +/* Table19243 */ + 0x0, /* */ + 0x37f2, /* VREDUCESSZrribkz */ +/* Table19245 */ + 0x301a, /* VPSHLDDZ128rmbikz */ + 0x0, /* */ +/* Table19247 */ + 0x30b6, /* VPSHRDDZ128rmbikz */ + 0x0, /* */ +/* Table19249 */ + 0xc0b, /* VALIGNQZ128rmbikz */ + 0x0, /* */ +/* Table19251 */ + 0x26cd, /* VPERMILPDZ128mbikz */ + 0x0, /* */ +/* Table19253 */ + 0x37f7, /* VRNDSCALEPDZ128rmbikz */ + 0x3810, /* VRNDSCALEPDZrribkz */ +/* Table19255 */ + 0x0, /* */ + 0x383b, /* VRNDSCALESDZrb_Intkz */ +/* Table19257 */ + 0x3542, /* VPTERNLOGQZ128rmbikz */ + 0x0, /* */ +/* Table19259 */ + 0x1ae0, /* VGETMANTPDZ128rmbikz */ + 0x1af9, /* VGETMANTPDZrribkz */ +/* Table19261 */ + 0x0, /* */ + 0x1b20, /* VGETMANTSDZrribkz */ +/* Table19263 */ + 0x36e7, /* VRANGEPDZ128rmbikz */ + 0x3700, /* VRANGEPDZrribkz */ +/* Table19265 */ + 0x0, /* */ + 0x3727, /* VRANGESDZrribkz */ +/* Table19267 */ + 0x1308, /* VFIXUPIMMPDZ128rmbikz */ + 0x1321, /* VFIXUPIMMPDZrribkz */ +/* Table19269 */ + 0x0, /* */ + 0x1348, /* VFIXUPIMMSDZrribkz */ +/* Table19271 */ + 0x37a9, /* VREDUCEPDZ128rmbikz */ + 0x37c2, /* VREDUCEPDZrribkz */ +/* Table19273 */ + 0x0, /* */ + 0x37e9, /* VREDUCESDZrribkz */ +/* Table19275 */ + 0x3035, /* VPSHLDQZ128rmbikz */ + 0x0, /* */ +/* Table19277 */ + 0x30d1, /* VPSHRDQZ128rmbikz */ + 0x0, /* */ +/* Table19279 */ + 0x1b4f, /* VGF2P8AFFINEQBZ128rmbikz */ + 0x0, /* */ +/* Table19281 */ + 0x1b30, /* VGF2P8AFFINEINVQBZ128rmbikz */ + 0x0, /* */ +/* Table19283 */ + 0xbf9, /* VALIGNDZ256rmbikz */ + 0x0, /* */ +/* Table19285 */ + 0x271d, /* VPERMILPSZ256mbikz */ + 0x0, /* */ +/* Table19287 */ + 0x381e, /* VRNDSCALEPSZ256rmbikz */ + 0x382e, /* VRNDSCALEPSZrribkz */ +/* Table19289 */ + 0x392f, /* VSHUFF32X4Z256rmbikz */ + 0x0, /* */ +/* Table19291 */ + 0x3530, /* VPTERNLOGDZ256rmbikz */ + 0x0, /* */ +/* Table19293 */ + 0x1b07, /* VGETMANTPSZ256rmbikz */ + 0x1b17, /* VGETMANTPSZrribkz */ +/* Table19295 */ + 0x3953, /* VSHUFI32X4Z256rmbikz */ + 0x0, /* */ +/* Table19297 */ + 0x370e, /* VRANGEPSZ256rmbikz */ + 0x371e, /* VRANGEPSZrribkz */ +/* Table19299 */ + 0x132f, /* VFIXUPIMMPSZ256rmbikz */ + 0x133f, /* VFIXUPIMMPSZrribkz */ +/* Table19301 */ + 0x37d0, /* VREDUCEPSZ256rmbikz */ + 0x37e0, /* VREDUCEPSZrribkz */ +/* Table19303 */ + 0x3023, /* VPSHLDDZ256rmbikz */ + 0x0, /* */ +/* Table19305 */ + 0x30bf, /* VPSHRDDZ256rmbikz */ + 0x0, /* */ +/* Table19307 */ + 0x2781, /* VPERMQZ256mbikz */ + 0x0, /* */ +/* Table19309 */ + 0x2747, /* VPERMPDZ256mbikz */ + 0x0, /* */ +/* Table19311 */ + 0xc14, /* VALIGNQZ256rmbikz */ + 0x0, /* */ +/* Table19313 */ + 0x26df, /* VPERMILPDZ256mbikz */ + 0x0, /* */ +/* Table19315 */ + 0x3800, /* VRNDSCALEPDZ256rmbikz */ + 0x3810, /* VRNDSCALEPDZrribkz */ +/* Table19317 */ + 0x3941, /* VSHUFF64X2Z256rmbikz */ + 0x0, /* */ +/* Table19319 */ + 0x354b, /* VPTERNLOGQZ256rmbikz */ + 0x0, /* */ +/* Table19321 */ + 0x1ae9, /* VGETMANTPDZ256rmbikz */ + 0x1af9, /* VGETMANTPDZrribkz */ +/* Table19323 */ + 0x3965, /* VSHUFI64X2Z256rmbikz */ + 0x0, /* */ +/* Table19325 */ + 0x36f0, /* VRANGEPDZ256rmbikz */ + 0x3700, /* VRANGEPDZrribkz */ +/* Table19327 */ + 0x1311, /* VFIXUPIMMPDZ256rmbikz */ + 0x1321, /* VFIXUPIMMPDZrribkz */ +/* Table19329 */ + 0x37b2, /* VREDUCEPDZ256rmbikz */ + 0x37c2, /* VREDUCEPDZrribkz */ +/* Table19331 */ + 0x303e, /* VPSHLDQZ256rmbikz */ + 0x0, /* */ +/* Table19333 */ + 0x30da, /* VPSHRDQZ256rmbikz */ + 0x0, /* */ +/* Table19335 */ + 0x1b58, /* VGF2P8AFFINEQBZ256rmbikz */ + 0x0, /* */ +/* Table19337 */ + 0x1b39, /* VGF2P8AFFINEINVQBZ256rmbikz */ + 0x0, /* */ +/* Table19339 */ + 0xc02, /* VALIGNDZrmbikz */ + 0x0, /* */ +/* Table19341 */ + 0x272f, /* VPERMILPSZmbikz */ + 0x0, /* */ +/* Table19343 */ + 0x3827, /* VRNDSCALEPSZrmbikz */ + 0x382e, /* VRNDSCALEPSZrribkz */ +/* Table19345 */ + 0x3938, /* VSHUFF32X4Zrmbikz */ + 0x0, /* */ +/* Table19347 */ + 0x3539, /* VPTERNLOGDZrmbikz */ + 0x0, /* */ +/* Table19349 */ + 0x1b10, /* VGETMANTPSZrmbikz */ + 0x1b17, /* VGETMANTPSZrribkz */ +/* Table19351 */ + 0x395c, /* VSHUFI32X4Zrmbikz */ + 0x0, /* */ +/* Table19353 */ + 0x3717, /* VRANGEPSZrmbikz */ + 0x371e, /* VRANGEPSZrribkz */ +/* Table19355 */ + 0x1338, /* VFIXUPIMMPSZrmbikz */ + 0x133f, /* VFIXUPIMMPSZrribkz */ +/* Table19357 */ + 0x37d9, /* VREDUCEPSZrmbikz */ + 0x37e0, /* VREDUCEPSZrribkz */ +/* Table19359 */ + 0x302c, /* VPSHLDDZrmbikz */ + 0x0, /* */ +/* Table19361 */ + 0x30c8, /* VPSHRDDZrmbikz */ + 0x0, /* */ +/* Table19363 */ + 0x2793, /* VPERMQZmbikz */ + 0x0, /* */ +/* Table19365 */ + 0x2759, /* VPERMPDZmbikz */ + 0x0, /* */ +/* Table19367 */ + 0xc1d, /* VALIGNQZrmbikz */ + 0x0, /* */ +/* Table19369 */ + 0x26f1, /* VPERMILPDZmbikz */ + 0x0, /* */ +/* Table19371 */ + 0x3809, /* VRNDSCALEPDZrmbikz */ + 0x3810, /* VRNDSCALEPDZrribkz */ +/* Table19373 */ + 0x394a, /* VSHUFF64X2Zrmbikz */ + 0x0, /* */ +/* Table19375 */ + 0x3554, /* VPTERNLOGQZrmbikz */ + 0x0, /* */ +/* Table19377 */ + 0x1af2, /* VGETMANTPDZrmbikz */ + 0x1af9, /* VGETMANTPDZrribkz */ +/* Table19379 */ + 0x396e, /* VSHUFI64X2Zrmbikz */ + 0x0, /* */ +/* Table19381 */ + 0x36f9, /* VRANGEPDZrmbikz */ + 0x3700, /* VRANGEPDZrribkz */ +/* Table19383 */ + 0x131a, /* VFIXUPIMMPDZrmbikz */ + 0x1321, /* VFIXUPIMMPDZrribkz */ +/* Table19385 */ + 0x37bb, /* VREDUCEPDZrmbikz */ + 0x37c2, /* VREDUCEPDZrribkz */ +/* Table19387 */ + 0x3047, /* VPSHLDQZrmbikz */ + 0x0, /* */ +/* Table19389 */ + 0x30e3, /* VPSHRDQZrmbikz */ + 0x0, /* */ +/* Table19391 */ + 0x1b61, /* VGF2P8AFFINEQBZrmbikz */ + 0x0, /* */ +/* Table19393 */ + 0x1b42, /* VGF2P8AFFINEINVQBZrmbikz */ + 0x0, /* */ +/* Table19395 */ + 0xbf3, /* VALIGNDZ128rmikz */ + 0xbf6, /* VALIGNDZ128rrikz */ +/* Table19397 */ + 0x270e, /* VPERMILPSZ128mikz */ + 0x2711, /* VPERMILPSZ128rikz */ +/* Table19399 */ + 0x3818, /* VRNDSCALEPSZ128rmikz */ + 0x381b, /* VRNDSCALEPSZ128rrikz */ +/* Table19401 */ + 0x383f, /* VRNDSCALESSZm_Intkz */ + 0x3843, /* VRNDSCALESSZr_Intkz */ +/* Table19403 */ + 0x21c3, /* VPALIGNRZ128rmikz */ + 0x21c6, /* VPALIGNRZ128rrikz */ +/* Table19405 */ + 0x0, /* */ + 0xf48, /* VCVTPS2PHZ128rrkz */ +/* Table19407 */ + 0x352a, /* VPTERNLOGDZ128rmikz */ + 0x352d, /* VPTERNLOGDZ128rrikz */ +/* Table19409 */ + 0x1b01, /* VGETMANTPSZ128rmikz */ + 0x1b04, /* VGETMANTPSZ128rrikz */ +/* Table19411 */ + 0x1b25, /* VGETMANTSSZrmikz */ + 0x1b2b, /* VGETMANTSSZrrikz */ +/* Table19413 */ + 0x120a, /* VDBPSADBWZ128rmikz */ + 0x120d, /* VDBPSADBWZ128rrikz */ +/* Table19415 */ + 0x3708, /* VRANGEPSZ128rmikz */ + 0x370b, /* VRANGEPSZ128rrikz */ +/* Table19417 */ + 0x372c, /* VRANGESSZrmikz */ + 0x3732, /* VRANGESSZrrikz */ +/* Table19419 */ + 0x1329, /* VFIXUPIMMPSZ128rmikz */ + 0x132c, /* VFIXUPIMMPSZ128rrikz */ +/* Table19421 */ + 0x134d, /* VFIXUPIMMSSZrmikz */ + 0x1353, /* VFIXUPIMMSSZrrikz */ +/* Table19423 */ + 0x37ca, /* VREDUCEPSZ128rmikz */ + 0x37cd, /* VREDUCEPSZ128rrikz */ +/* Table19425 */ + 0x37ee, /* VREDUCESSZrmikz */ + 0x37f4, /* VREDUCESSZrrikz */ +/* Table19427 */ + 0x301d, /* VPSHLDDZ128rmikz */ + 0x3020, /* VPSHLDDZ128rrikz */ +/* Table19429 */ + 0x30b9, /* VPSHRDDZ128rmikz */ + 0x30bc, /* VPSHRDDZ128rrikz */ +/* Table19431 */ + 0xc0e, /* VALIGNQZ128rmikz */ + 0xc11, /* VALIGNQZ128rrikz */ +/* Table19433 */ + 0x26d0, /* VPERMILPDZ128mikz */ + 0x26d3, /* VPERMILPDZ128rikz */ +/* Table19435 */ + 0x37fa, /* VRNDSCALEPDZ128rmikz */ + 0x37fd, /* VRNDSCALEPDZ128rrikz */ +/* Table19437 */ + 0x3834, /* VRNDSCALESDZm_Intkz */ + 0x3838, /* VRNDSCALESDZr_Intkz */ +/* Table19439 */ + 0x3545, /* VPTERNLOGQZ128rmikz */ + 0x3548, /* VPTERNLOGQZ128rrikz */ +/* Table19441 */ + 0x1ae3, /* VGETMANTPDZ128rmikz */ + 0x1ae6, /* VGETMANTPDZ128rrikz */ +/* Table19443 */ + 0x1b1c, /* VGETMANTSDZrmikz */ + 0x1b22, /* VGETMANTSDZrrikz */ +/* Table19445 */ + 0x36ea, /* VRANGEPDZ128rmikz */ + 0x36ed, /* VRANGEPDZ128rrikz */ +/* Table19447 */ + 0x3723, /* VRANGESDZrmikz */ + 0x3729, /* VRANGESDZrrikz */ +/* Table19449 */ + 0x130b, /* VFIXUPIMMPDZ128rmikz */ + 0x130e, /* VFIXUPIMMPDZ128rrikz */ +/* Table19451 */ + 0x1344, /* VFIXUPIMMSDZrmikz */ + 0x134a, /* VFIXUPIMMSDZrrikz */ +/* Table19453 */ + 0x37ac, /* VREDUCEPDZ128rmikz */ + 0x37af, /* VREDUCEPDZ128rrikz */ +/* Table19455 */ + 0x37e5, /* VREDUCESDZrmikz */ + 0x37eb, /* VREDUCESDZrrikz */ +/* Table19457 */ + 0x3098, /* VPSHLDWZ128rmikz */ + 0x309b, /* VPSHLDWZ128rrikz */ +/* Table19459 */ + 0x3038, /* VPSHLDQZ128rmikz */ + 0x303b, /* VPSHLDQZ128rrikz */ +/* Table19461 */ + 0x3134, /* VPSHRDWZ128rmikz */ + 0x3137, /* VPSHRDWZ128rrikz */ +/* Table19463 */ + 0x30d4, /* VPSHRDQZ128rmikz */ + 0x30d7, /* VPSHRDQZ128rrikz */ +/* Table19465 */ + 0x1b52, /* VGF2P8AFFINEQBZ128rmikz */ + 0x1b55, /* VGF2P8AFFINEQBZ128rrikz */ +/* Table19467 */ + 0x1b33, /* VGF2P8AFFINEINVQBZ128rmikz */ + 0x1b36, /* VGF2P8AFFINEINVQBZ128rrikz */ +/* Table19469 */ + 0xbfc, /* VALIGNDZ256rmikz */ + 0xbff, /* VALIGNDZ256rrikz */ +/* Table19471 */ + 0x2720, /* VPERMILPSZ256mikz */ + 0x2723, /* VPERMILPSZ256rikz */ +/* Table19473 */ + 0x3821, /* VRNDSCALEPSZ256rmikz */ + 0x3824, /* VRNDSCALEPSZ256rrikz */ +/* Table19475 */ + 0x21c9, /* VPALIGNRZ256rmikz */ + 0x21cc, /* VPALIGNRZ256rrikz */ +/* Table19477 */ + 0x1b94, /* VINSERTF32x4Z256rmkz */ + 0x1b97, /* VINSERTF32x4Z256rrkz */ +/* Table19479 */ + 0x0, /* */ + 0x12c8, /* VEXTRACTF32x4Z256rrkz */ +/* Table19481 */ + 0x0, /* */ + 0xf4d, /* VCVTPS2PHZ256rrkz */ +/* Table19483 */ + 0x3932, /* VSHUFF32X4Z256rmikz */ + 0x3935, /* VSHUFF32X4Z256rrikz */ +/* Table19485 */ + 0x3533, /* VPTERNLOGDZ256rmikz */ + 0x3536, /* VPTERNLOGDZ256rrikz */ +/* Table19487 */ + 0x1b0a, /* VGETMANTPSZ256rmikz */ + 0x1b0d, /* VGETMANTPSZ256rrikz */ +/* Table19489 */ + 0x1bba, /* VINSERTI32x4Z256rmkz */ + 0x1bbd, /* VINSERTI32x4Z256rrkz */ +/* Table19491 */ + 0x0, /* */ + 0x12e8, /* VEXTRACTI32x4Z256rrkz */ +/* Table19493 */ + 0x1210, /* VDBPSADBWZ256rmikz */ + 0x1213, /* VDBPSADBWZ256rrikz */ +/* Table19495 */ + 0x3956, /* VSHUFI32X4Z256rmikz */ + 0x3959, /* VSHUFI32X4Z256rrikz */ +/* Table19497 */ + 0x3711, /* VRANGEPSZ256rmikz */ + 0x3714, /* VRANGEPSZ256rrikz */ +/* Table19499 */ + 0x1332, /* VFIXUPIMMPSZ256rmikz */ + 0x1335, /* VFIXUPIMMPSZ256rrikz */ +/* Table19501 */ + 0x37d3, /* VREDUCEPSZ256rmikz */ + 0x37d6, /* VREDUCEPSZ256rrikz */ +/* Table19503 */ + 0x3026, /* VPSHLDDZ256rmikz */ + 0x3029, /* VPSHLDDZ256rrikz */ +/* Table19505 */ + 0x30c2, /* VPSHRDDZ256rmikz */ + 0x30c5, /* VPSHRDDZ256rrikz */ +/* Table19507 */ + 0x2784, /* VPERMQZ256mikz */ + 0x2787, /* VPERMQZ256rikz */ +/* Table19509 */ + 0x274a, /* VPERMPDZ256mikz */ + 0x274d, /* VPERMPDZ256rikz */ +/* Table19511 */ + 0xc17, /* VALIGNQZ256rmikz */ + 0xc1a, /* VALIGNQZ256rrikz */ +/* Table19513 */ + 0x26e2, /* VPERMILPDZ256mikz */ + 0x26e5, /* VPERMILPDZ256rikz */ +/* Table19515 */ + 0x3803, /* VRNDSCALEPDZ256rmikz */ + 0x3806, /* VRNDSCALEPDZ256rrikz */ +/* Table19517 */ + 0x1ba6, /* VINSERTF64x2Z256rmkz */ + 0x1ba9, /* VINSERTF64x2Z256rrkz */ +/* Table19519 */ + 0x0, /* */ + 0x12d7, /* VEXTRACTF64x2Z256rrkz */ +/* Table19521 */ + 0x3944, /* VSHUFF64X2Z256rmikz */ + 0x3947, /* VSHUFF64X2Z256rrikz */ +/* Table19523 */ + 0x354e, /* VPTERNLOGQZ256rmikz */ + 0x3551, /* VPTERNLOGQZ256rrikz */ +/* Table19525 */ + 0x1aec, /* VGETMANTPDZ256rmikz */ + 0x1aef, /* VGETMANTPDZ256rrikz */ +/* Table19527 */ + 0x1bcc, /* VINSERTI64x2Z256rmkz */ + 0x1bcf, /* VINSERTI64x2Z256rrkz */ +/* Table19529 */ + 0x0, /* */ + 0x12f7, /* VEXTRACTI64x2Z256rrkz */ +/* Table19531 */ + 0x3968, /* VSHUFI64X2Z256rmikz */ + 0x396b, /* VSHUFI64X2Z256rrikz */ +/* Table19533 */ + 0x36f3, /* VRANGEPDZ256rmikz */ + 0x36f6, /* VRANGEPDZ256rrikz */ +/* Table19535 */ + 0x1314, /* VFIXUPIMMPDZ256rmikz */ + 0x1317, /* VFIXUPIMMPDZ256rrikz */ +/* Table19537 */ + 0x37b5, /* VREDUCEPDZ256rmikz */ + 0x37b8, /* VREDUCEPDZ256rrikz */ +/* Table19539 */ + 0x309e, /* VPSHLDWZ256rmikz */ + 0x30a1, /* VPSHLDWZ256rrikz */ +/* Table19541 */ + 0x3041, /* VPSHLDQZ256rmikz */ + 0x3044, /* VPSHLDQZ256rrikz */ +/* Table19543 */ + 0x313a, /* VPSHRDWZ256rmikz */ + 0x313d, /* VPSHRDWZ256rrikz */ +/* Table19545 */ + 0x30dd, /* VPSHRDQZ256rmikz */ + 0x30e0, /* VPSHRDQZ256rrikz */ +/* Table19547 */ + 0x1b5b, /* VGF2P8AFFINEQBZ256rmikz */ + 0x1b5e, /* VGF2P8AFFINEQBZ256rrikz */ +/* Table19549 */ + 0x1b3c, /* VGF2P8AFFINEINVQBZ256rmikz */ + 0x1b3f, /* VGF2P8AFFINEINVQBZ256rrikz */ +/* Table19551 */ + 0xc05, /* VALIGNDZrmikz */ + 0xc08, /* VALIGNDZrrikz */ +/* Table19553 */ + 0x2732, /* VPERMILPSZmikz */ + 0x2735, /* VPERMILPSZrikz */ +/* Table19555 */ + 0x382a, /* VRNDSCALEPSZrmikz */ + 0x3830, /* VRNDSCALEPSZrrikz */ +/* Table19557 */ + 0x21cf, /* VPALIGNRZrmikz */ + 0x21d2, /* VPALIGNRZrrikz */ +/* Table19559 */ + 0x1b9a, /* VINSERTF32x4Zrmkz */ + 0x1b9d, /* VINSERTF32x4Zrrkz */ +/* Table19561 */ + 0x0, /* */ + 0x12cd, /* VEXTRACTF32x4Zrrkz */ +/* Table19563 */ + 0x1ba0, /* VINSERTF32x8Zrmkz */ + 0x1ba3, /* VINSERTF32x8Zrrkz */ +/* Table19565 */ + 0x0, /* */ + 0x12d2, /* VEXTRACTF32x8Zrrkz */ +/* Table19567 */ + 0x0, /* */ + 0xf55, /* VCVTPS2PHZrrkz */ +/* Table19569 */ + 0x393b, /* VSHUFF32X4Zrmikz */ + 0x393e, /* VSHUFF32X4Zrrikz */ +/* Table19571 */ + 0x353c, /* VPTERNLOGDZrmikz */ + 0x353f, /* VPTERNLOGDZrrikz */ +/* Table19573 */ + 0x1b13, /* VGETMANTPSZrmikz */ + 0x1b19, /* VGETMANTPSZrrikz */ +/* Table19575 */ + 0x1bc0, /* VINSERTI32x4Zrmkz */ + 0x1bc3, /* VINSERTI32x4Zrrkz */ +/* Table19577 */ + 0x0, /* */ + 0x12ed, /* VEXTRACTI32x4Zrrkz */ +/* Table19579 */ + 0x1bc6, /* VINSERTI32x8Zrmkz */ + 0x1bc9, /* VINSERTI32x8Zrrkz */ +/* Table19581 */ + 0x0, /* */ + 0x12f2, /* VEXTRACTI32x8Zrrkz */ +/* Table19583 */ + 0x1216, /* VDBPSADBWZrmikz */ + 0x1219, /* VDBPSADBWZrrikz */ +/* Table19585 */ + 0x395f, /* VSHUFI32X4Zrmikz */ + 0x3962, /* VSHUFI32X4Zrrikz */ +/* Table19587 */ + 0x371a, /* VRANGEPSZrmikz */ + 0x3720, /* VRANGEPSZrrikz */ +/* Table19589 */ + 0x133b, /* VFIXUPIMMPSZrmikz */ + 0x1341, /* VFIXUPIMMPSZrrikz */ +/* Table19591 */ + 0x37dc, /* VREDUCEPSZrmikz */ + 0x37e2, /* VREDUCEPSZrrikz */ +/* Table19593 */ + 0x302f, /* VPSHLDDZrmikz */ + 0x3032, /* VPSHLDDZrrikz */ +/* Table19595 */ + 0x30cb, /* VPSHRDDZrmikz */ + 0x30ce, /* VPSHRDDZrrikz */ +/* Table19597 */ + 0x2796, /* VPERMQZmikz */ + 0x2799, /* VPERMQZrikz */ +/* Table19599 */ + 0x275c, /* VPERMPDZmikz */ + 0x275f, /* VPERMPDZrikz */ +/* Table19601 */ + 0xc20, /* VALIGNQZrmikz */ + 0xc23, /* VALIGNQZrrikz */ +/* Table19603 */ + 0x26f4, /* VPERMILPDZmikz */ + 0x26f7, /* VPERMILPDZrikz */ +/* Table19605 */ + 0x380c, /* VRNDSCALEPDZrmikz */ + 0x3812, /* VRNDSCALEPDZrrikz */ +/* Table19607 */ + 0x1bac, /* VINSERTF64x2Zrmkz */ + 0x1baf, /* VINSERTF64x2Zrrkz */ +/* Table19609 */ + 0x0, /* */ + 0x12dc, /* VEXTRACTF64x2Zrrkz */ +/* Table19611 */ + 0x1bb2, /* VINSERTF64x4Zrmkz */ + 0x1bb5, /* VINSERTF64x4Zrrkz */ +/* Table19613 */ + 0x0, /* */ + 0x12e1, /* VEXTRACTF64x4Zrrkz */ +/* Table19615 */ + 0x394d, /* VSHUFF64X2Zrmikz */ + 0x3950, /* VSHUFF64X2Zrrikz */ +/* Table19617 */ + 0x3557, /* VPTERNLOGQZrmikz */ + 0x355a, /* VPTERNLOGQZrrikz */ +/* Table19619 */ + 0x1af5, /* VGETMANTPDZrmikz */ + 0x1afb, /* VGETMANTPDZrrikz */ +/* Table19621 */ + 0x1bd2, /* VINSERTI64x2Zrmkz */ + 0x1bd5, /* VINSERTI64x2Zrrkz */ +/* Table19623 */ + 0x0, /* */ + 0x12fc, /* VEXTRACTI64x2Zrrkz */ +/* Table19625 */ + 0x1bd8, /* VINSERTI64x4Zrmkz */ + 0x1bdb, /* VINSERTI64x4Zrrkz */ +/* Table19627 */ + 0x0, /* */ + 0x1301, /* VEXTRACTI64x4Zrrkz */ +/* Table19629 */ + 0x3971, /* VSHUFI64X2Zrmikz */ + 0x3974, /* VSHUFI64X2Zrrikz */ +/* Table19631 */ + 0x36fc, /* VRANGEPDZrmikz */ + 0x3702, /* VRANGEPDZrrikz */ +/* Table19633 */ + 0x131d, /* VFIXUPIMMPDZrmikz */ + 0x1323, /* VFIXUPIMMPDZrrikz */ +/* Table19635 */ + 0x37be, /* VREDUCEPDZrmikz */ + 0x37c4, /* VREDUCEPDZrrikz */ +/* Table19637 */ + 0x30a4, /* VPSHLDWZrmikz */ + 0x30a7, /* VPSHLDWZrrikz */ +/* Table19639 */ + 0x304a, /* VPSHLDQZrmikz */ + 0x304d, /* VPSHLDQZrrikz */ +/* Table19641 */ + 0x3140, /* VPSHRDWZrmikz */ + 0x3143, /* VPSHRDWZrrikz */ +/* Table19643 */ + 0x30e6, /* VPSHRDQZrmikz */ + 0x30e9, /* VPSHRDQZrrikz */ +/* Table19645 */ + 0x1b64, /* VGF2P8AFFINEQBZrmikz */ + 0x1b67, /* VGF2P8AFFINEQBZrrikz */ +/* Table19647 */ + 0x1b45, /* VGF2P8AFFINEINVQBZrmikz */ + 0x1b48, /* VGF2P8AFFINEINVQBZrrikz */ +/* Table19649 */ + 0x293f, /* VPMACSSWWrm */ + 0x2940, /* VPMACSSWWrr */ +/* Table19651 */ + 0x293d, /* VPMACSSWDrm */ + 0x293e, /* VPMACSSWDrr */ +/* Table19653 */ + 0x293b, /* VPMACSSDQLrm */ + 0x293c, /* VPMACSSDQLrr */ +/* Table19655 */ + 0x2937, /* VPMACSSDDrm */ + 0x2938, /* VPMACSSDDrr */ +/* Table19657 */ + 0x2939, /* VPMACSSDQHrm */ + 0x293a, /* VPMACSSDQHrr */ +/* Table19659 */ + 0x2943, /* VPMACSWWrm */ + 0x2944, /* VPMACSWWrr */ +/* Table19661 */ + 0x2941, /* VPMACSWDrm */ + 0x2942, /* VPMACSWDrr */ +/* Table19663 */ + 0x2935, /* VPMACSDQLrm */ + 0x2936, /* VPMACSDQLrr */ +/* Table19665 */ + 0x2931, /* VPMACSDDrm */ + 0x2932, /* VPMACSDDrr */ +/* Table19667 */ + 0x2933, /* VPMACSDQHrm */ + 0x2934, /* VPMACSDQHrr */ +/* Table19669 */ + 0x236b, /* VPCMOVrmr */ + 0x236d, /* VPCMOVrrr */ +/* Table19671 */ + 0x2efa, /* VPPERMrmr */ + 0x2efc, /* VPPERMrrr */ +/* Table19673 */ + 0x2945, /* VPMADCSSWDrm */ + 0x2946, /* VPMADCSSWDrr */ +/* Table19675 */ + 0x2947, /* VPMADCSWDrm */ + 0x2948, /* VPMADCSWDrr */ +/* Table19677 */ + 0x2fd6, /* VPROTBmi */ + 0x2fd8, /* VPROTBri */ +/* Table19679 */ + 0x2fe8, /* VPROTWmi */ + 0x2fea, /* VPROTWri */ +/* Table19681 */ + 0x2fdc, /* VPROTDmi */ + 0x2fde, /* VPROTDri */ +/* Table19683 */ + 0x2fe2, /* VPROTQmi */ + 0x2fe4, /* VPROTQri */ +/* Table19685 */ + 0x24ff, /* VPCOMBmi */ + 0x2501, /* VPCOMBri */ +/* Table19687 */ + 0x2557, /* VPCOMWmi */ + 0x2559, /* VPCOMWri */ +/* Table19689 */ + 0x2503, /* VPCOMDmi */ + 0x2505, /* VPCOMDri */ +/* Table19691 */ + 0x2543, /* VPCOMQmi */ + 0x2545, /* VPCOMQri */ +/* Table19693 */ + 0x2547, /* VPCOMUBmi */ + 0x2549, /* VPCOMUBri */ +/* Table19695 */ + 0x2553, /* VPCOMUWmi */ + 0x2555, /* VPCOMUWri */ +/* Table19697 */ + 0x254b, /* VPCOMUDmi */ + 0x254d, /* VPCOMUDri */ +/* Table19699 */ + 0x254f, /* VPCOMUQmi */ + 0x2551, /* VPCOMUQri */ +/* Table19701 */ + 0x236c, /* VPCMOVrrm */ + 0x236e, /* VPCMOVrrr_REV */ +/* Table19703 */ + 0x2efb, /* VPPERMrrm */ + 0x2efd, /* VPPERMrrr_REV */ +/* Table19705 */ + 0x2367, /* VPCMOVYrmr */ + 0x2369, /* VPCMOVYrrr */ +/* Table19707 */ + 0x2368, /* VPCMOVYrrm */ + 0x236a, /* VPCMOVYrrr_REV */ +/* Table19709 */ + 0x0, /* */ + 0x155, /* BLCFILL32rm */ + 0x171, /* BLSFILL32rm */ + 0x165, /* BLCS32rm */ + 0xb26, /* TZMSK32rm */ + 0x15d, /* BLCIC32rm */ + 0x179, /* BLSIC32rm */ + 0xafb, /* T1MSKC32rm */ + 0x0, /* */ + 0x156, /* BLCFILL32rr */ + 0x172, /* BLSFILL32rr */ + 0x166, /* BLCS32rr */ + 0xb27, /* TZMSK32rr */ + 0x15e, /* BLCIC32rr */ + 0x17a, /* BLSIC32rr */ + 0xafc, /* T1MSKC32rr */ +/* Table19725 */ + 0x0, /* */ + 0x161, /* BLCMSK32rm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x159, /* BLCI32rm */ + 0x0, /* */ + 0x0, /* */ + 0x162, /* BLCMSK32rr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x15a, /* BLCI32rr */ + 0x0, /* */ +/* Table19741 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x4f6, /* LLWPCB */ + 0xa67, /* SLWPCB */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table19757 */ + 0x1a6e, /* VFRCZPSrm */ + 0x1a6f, /* VFRCZPSrr */ +/* Table19759 */ + 0x1a6a, /* VFRCZPDrm */ + 0x1a6b, /* VFRCZPDrr */ +/* Table19761 */ + 0x1a72, /* VFRCZSSrm */ + 0x1a73, /* VFRCZSSrr */ +/* Table19763 */ + 0x1a70, /* VFRCZSDrm */ + 0x1a71, /* VFRCZSDrr */ +/* Table19765 */ + 0x2fd7, /* VPROTBmr */ + 0x2fda, /* VPROTBrr */ +/* Table19767 */ + 0x2fe9, /* VPROTWmr */ + 0x2fec, /* VPROTWrr */ +/* Table19769 */ + 0x2fdd, /* VPROTDmr */ + 0x2fe0, /* VPROTDrr */ +/* Table19771 */ + 0x2fe3, /* VPROTQmr */ + 0x2fe6, /* VPROTQrr */ +/* Table19773 */ + 0x3014, /* VPSHLBmr */ + 0x3016, /* VPSHLBrr */ +/* Table19775 */ + 0x30b0, /* VPSHLWmr */ + 0x30b2, /* VPSHLWrr */ +/* Table19777 */ + 0x30a8, /* VPSHLDmr */ + 0x30aa, /* VPSHLDrr */ +/* Table19779 */ + 0x30ac, /* VPSHLQmr */ + 0x30ae, /* VPSHLQrr */ +/* Table19781 */ + 0x3004, /* VPSHABmr */ + 0x3006, /* VPSHABrr */ +/* Table19783 */ + 0x3010, /* VPSHAWmr */ + 0x3012, /* VPSHAWrr */ +/* Table19785 */ + 0x3008, /* VPSHADmr */ + 0x300a, /* VPSHADrr */ +/* Table19787 */ + 0x300c, /* VPSHAQmr */ + 0x300e, /* VPSHAQrr */ +/* Table19789 */ + 0x28b7, /* VPHADDBWrm */ + 0x28b8, /* VPHADDBWrr */ +/* Table19791 */ + 0x28b3, /* VPHADDBDrm */ + 0x28b4, /* VPHADDBDrr */ +/* Table19793 */ + 0x28b5, /* VPHADDBQrm */ + 0x28b6, /* VPHADDBQrr */ +/* Table19795 */ + 0x28cf, /* VPHADDWDrm */ + 0x28d0, /* VPHADDWDrr */ +/* Table19797 */ + 0x28d1, /* VPHADDWQrm */ + 0x28d2, /* VPHADDWQrr */ +/* Table19799 */ + 0x28b9, /* VPHADDDQrm */ + 0x28ba, /* VPHADDDQrr */ +/* Table19801 */ + 0x28c7, /* VPHADDUBWrm */ + 0x28c8, /* VPHADDUBWrr */ +/* Table19803 */ + 0x28c3, /* VPHADDUBDrm */ + 0x28c4, /* VPHADDUBDrr */ +/* Table19805 */ + 0x28c5, /* VPHADDUBQrm */ + 0x28c6, /* VPHADDUBQrr */ +/* Table19807 */ + 0x28cb, /* VPHADDUWDrm */ + 0x28cc, /* VPHADDUWDrr */ +/* Table19809 */ + 0x28cd, /* VPHADDUWQrm */ + 0x28ce, /* VPHADDUWQrr */ +/* Table19811 */ + 0x28c9, /* VPHADDUDQrm */ + 0x28ca, /* VPHADDUDQrr */ +/* Table19813 */ + 0x28d9, /* VPHSUBBWrm */ + 0x28da, /* VPHSUBBWrr */ +/* Table19815 */ + 0x28e5, /* VPHSUBWDrm */ + 0x28e6, /* VPHSUBWDrr */ +/* Table19817 */ + 0x28db, /* VPHSUBDQrm */ + 0x28dc, /* VPHSUBDQrr */ +/* Table19819 */ + 0x0, /* */ + 0x157, /* BLCFILL64rm */ + 0x173, /* BLSFILL64rm */ + 0x167, /* BLCS64rm */ + 0xb28, /* TZMSK64rm */ + 0x15f, /* BLCIC64rm */ + 0x17b, /* BLSIC64rm */ + 0xafd, /* T1MSKC64rm */ + 0x0, /* */ + 0x158, /* BLCFILL64rr */ + 0x174, /* BLSFILL64rr */ + 0x168, /* BLCS64rr */ + 0xb29, /* TZMSK64rr */ + 0x160, /* BLCIC64rr */ + 0x17c, /* BLSIC64rr */ + 0xafe, /* T1MSKC64rr */ +/* Table19835 */ + 0x0, /* */ + 0x163, /* BLCMSK64rm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x15b, /* BLCI64rm */ + 0x0, /* */ + 0x0, /* */ + 0x164, /* BLCMSK64rr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x15c, /* BLCI64rr */ + 0x0, /* */ +/* Table19851 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x4f7, /* LLWPCB64 */ + 0xa68, /* SLWPCB64 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table19867 */ + 0x2fd9, /* VPROTBrm */ + 0x2fdb, /* VPROTBrr_REV */ +/* Table19869 */ + 0x2feb, /* VPROTWrm */ + 0x2fed, /* VPROTWrr_REV */ +/* Table19871 */ + 0x2fdf, /* VPROTDrm */ + 0x2fe1, /* VPROTDrr_REV */ +/* Table19873 */ + 0x2fe5, /* VPROTQrm */ + 0x2fe7, /* VPROTQrr_REV */ +/* Table19875 */ + 0x3015, /* VPSHLBrm */ + 0x3017, /* VPSHLBrr_REV */ +/* Table19877 */ + 0x30b1, /* VPSHLWrm */ + 0x30b3, /* VPSHLWrr_REV */ +/* Table19879 */ + 0x30a9, /* VPSHLDrm */ + 0x30ab, /* VPSHLDrr_REV */ +/* Table19881 */ + 0x30ad, /* VPSHLQrm */ + 0x30af, /* VPSHLQrr_REV */ +/* Table19883 */ + 0x3005, /* VPSHABrm */ + 0x3007, /* VPSHABrr_REV */ +/* Table19885 */ + 0x3011, /* VPSHAWrm */ + 0x3013, /* VPSHAWrr_REV */ +/* Table19887 */ + 0x3009, /* VPSHADrm */ + 0x300b, /* VPSHADrr_REV */ +/* Table19889 */ + 0x300d, /* VPSHAQrm */ + 0x300f, /* VPSHAQrr_REV */ +/* Table19891 */ + 0x1a6c, /* VFRCZPSYrm */ + 0x1a6d, /* VFRCZPSYrr */ +/* Table19893 */ + 0x1a68, /* VFRCZPDYrm */ + 0x1a69, /* VFRCZPDYrr */ +/* Table19895 */ + 0x151, /* BEXTRI32mi */ + 0x152, /* BEXTRI32ri */ +/* Table19897 */ + 0x513, /* LWPINS32rmi */ + 0x517, /* LWPVAL32rmi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x514, /* LWPINS32rri */ + 0x518, /* LWPVAL32rri */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table19913 */ + 0x153, /* BEXTRI64mi */ + 0x154, /* BEXTRI64ri */ +/* Table19915 */ + 0x515, /* LWPINS64rmi */ + 0x519, /* LWPVAL64rmi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x516, /* LWPINS64rri */ + 0x51a, /* LWPVAL64rri */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table19931 */ + 0x7ed, /* PI2FWrm */ + 0x7ee, /* PI2FWrr */ +/* Table19933 */ + 0x7eb, /* PI2FDrm */ + 0x7ec, /* PI2FDrr */ +/* Table19935 */ + 0x7b9, /* PF2IWrm */ + 0x7ba, /* PF2IWrr */ +/* Table19937 */ + 0x7b7, /* PF2IDrm */ + 0x7b8, /* PF2IDrr */ +/* Table19939 */ + 0x7cb, /* PFNACCrm */ + 0x7cc, /* PFNACCrr */ +/* Table19941 */ + 0x7cd, /* PFPNACCrm */ + 0x7ce, /* PFPNACCrr */ +/* Table19943 */ + 0x7c1, /* PFCMPGErm */ + 0x7c2, /* PFCMPGErr */ +/* Table19945 */ + 0x7c7, /* PFMINrm */ + 0x7c8, /* PFMINrr */ +/* Table19947 */ + 0x7d3, /* PFRCPrm */ + 0x7d4, /* PFRCPrr */ +/* Table19949 */ + 0x7d7, /* PFRSQRTrm */ + 0x7d8, /* PFRSQRTrr */ +/* Table19951 */ + 0x7db, /* PFSUBrm */ + 0x7dc, /* PFSUBrr */ +/* Table19953 */ + 0x7bd, /* PFADDrm */ + 0x7be, /* PFADDrr */ +/* Table19955 */ + 0x7c3, /* PFCMPGTrm */ + 0x7c4, /* PFCMPGTrr */ +/* Table19957 */ + 0x7c5, /* PFMAXrm */ + 0x7c6, /* PFMAXrr */ +/* Table19959 */ + 0x7cf, /* PFRCPIT1rm */ + 0x7d0, /* PFRCPIT1rr */ +/* Table19961 */ + 0x7d5, /* PFRSQIT1rm */ + 0x7d6, /* PFRSQIT1rr */ +/* Table19963 */ + 0x7d9, /* PFSUBRrm */ + 0x7da, /* PFSUBRrr */ +/* Table19965 */ + 0x7bb, /* PFACCrm */ + 0x7bc, /* PFACCrr */ +/* Table19967 */ + 0x7bf, /* PFCMPEQrm */ + 0x7c0, /* PFCMPEQrr */ +/* Table19969 */ + 0x7c9, /* PFMULrm */ + 0x7ca, /* PFMULrr */ +/* Table19971 */ + 0x7d1, /* PFRCPIT2rm */ + 0x7d2, /* PFRCPIT2rr */ +/* Table19973 */ + 0x830, /* PMULHRWrm */ + 0x831, /* PMULHRWrr */ +/* Table19975 */ + 0x89f, /* PSWAPDrm */ + 0x8a0, /* PSWAPDrr */ +/* Table19977 */ + 0x783, /* PAVGUSBrm */ + 0x784, /* PAVGUSBrr */ + 0x0 +}; + diff --git a/thirdparty/capstone/arch/X86/X86GenDisassemblerTables2.inc b/thirdparty/capstone/arch/X86/X86GenDisassemblerTables2.inc new file mode 100644 index 0000000..9f47425 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenDisassemblerTables2.inc @@ -0,0 +1,102151 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +static const unsigned char index_x86DisassemblerOneByteOpcodes[] = { + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 0, + 0, + 0, + 0, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 0, + 0, + 15, + 16, + 17, + 18, + 19, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +static const struct OpcodeDecision x86DisassemblerOneByteOpcodes[] = { + { { + { MODRM_SPLITRM, 1 }, + { MODRM_SPLITRM, 3 }, + { MODRM_SPLITRM, 5 }, + { MODRM_SPLITRM, 7 }, + { MODRM_ONEENTRY, 9 }, + { MODRM_ONEENTRY, 10 }, + { MODRM_ONEENTRY, 11 }, + { MODRM_ONEENTRY, 12 }, + { MODRM_SPLITRM, 13 }, + { MODRM_SPLITRM, 15 }, + { MODRM_SPLITRM, 17 }, + { MODRM_SPLITRM, 19 }, + { MODRM_ONEENTRY, 21 }, + { MODRM_ONEENTRY, 22 }, + { MODRM_ONEENTRY, 23 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 24 }, + { MODRM_SPLITRM, 26 }, + { MODRM_SPLITRM, 28 }, + { MODRM_SPLITRM, 30 }, + { MODRM_ONEENTRY, 32 }, + { MODRM_ONEENTRY, 33 }, + { MODRM_ONEENTRY, 34 }, + { MODRM_ONEENTRY, 35 }, + { MODRM_SPLITRM, 36 }, + { MODRM_SPLITRM, 38 }, + { MODRM_SPLITRM, 40 }, + { MODRM_SPLITRM, 42 }, + { MODRM_ONEENTRY, 44 }, + { MODRM_ONEENTRY, 45 }, + { MODRM_ONEENTRY, 46 }, + { MODRM_ONEENTRY, 47 }, + { MODRM_SPLITRM, 48 }, + { MODRM_SPLITRM, 50 }, + { MODRM_SPLITRM, 52 }, + { MODRM_SPLITRM, 54 }, + { MODRM_ONEENTRY, 56 }, + { MODRM_ONEENTRY, 57 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 58 }, + { MODRM_SPLITRM, 59 }, + { MODRM_SPLITRM, 61 }, + { MODRM_SPLITRM, 63 }, + { MODRM_SPLITRM, 65 }, + { MODRM_ONEENTRY, 67 }, + { MODRM_ONEENTRY, 68 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 69 }, + { MODRM_SPLITRM, 70 }, + { MODRM_SPLITRM, 72 }, + { MODRM_SPLITRM, 74 }, + { MODRM_SPLITRM, 76 }, + { MODRM_ONEENTRY, 78 }, + { MODRM_ONEENTRY, 79 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 80 }, + { MODRM_SPLITRM, 81 }, + { MODRM_SPLITRM, 83 }, + { MODRM_SPLITRM, 85 }, + { MODRM_SPLITRM, 87 }, + { MODRM_ONEENTRY, 89 }, + { MODRM_ONEENTRY, 90 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 91 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 96 }, + { MODRM_ONEENTRY, 97 }, + { MODRM_SPLITRM, 98 }, + { MODRM_SPLITRM, 100 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 102 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 103 }, + { MODRM_SPLITRM, 104 }, + { MODRM_ONEENTRY, 106 }, + { MODRM_SPLITRM, 107 }, + { MODRM_ONEENTRY, 109 }, + { MODRM_ONEENTRY, 110 }, + { MODRM_ONEENTRY, 111 }, + { MODRM_ONEENTRY, 112 }, + { MODRM_ONEENTRY, 113 }, + { MODRM_ONEENTRY, 114 }, + { MODRM_ONEENTRY, 115 }, + { MODRM_ONEENTRY, 116 }, + { MODRM_ONEENTRY, 117 }, + { MODRM_ONEENTRY, 118 }, + { MODRM_ONEENTRY, 119 }, + { MODRM_ONEENTRY, 120 }, + { MODRM_ONEENTRY, 121 }, + { MODRM_ONEENTRY, 122 }, + { MODRM_ONEENTRY, 123 }, + { MODRM_ONEENTRY, 124 }, + { MODRM_ONEENTRY, 125 }, + { MODRM_ONEENTRY, 126 }, + { MODRM_ONEENTRY, 127 }, + { MODRM_ONEENTRY, 128 }, + { MODRM_SPLITREG, 129 }, + { MODRM_SPLITREG, 145 }, + { MODRM_SPLITREG, 161 }, + { MODRM_SPLITREG, 177 }, + { MODRM_SPLITRM, 193 }, + { MODRM_SPLITRM, 195 }, + { MODRM_SPLITRM, 197 }, + { MODRM_SPLITRM, 199 }, + { MODRM_SPLITRM, 201 }, + { MODRM_SPLITRM, 203 }, + { MODRM_SPLITRM, 205 }, + { MODRM_SPLITRM, 207 }, + { MODRM_SPLITRM, 209 }, + { MODRM_SPLITRM, 211 }, + { MODRM_SPLITRM, 213 }, + { MODRM_SPLITREG, 215 }, + { MODRM_ONEENTRY, 231 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 233 }, + { MODRM_ONEENTRY, 234 }, + { MODRM_ONEENTRY, 235 }, + { MODRM_ONEENTRY, 236 }, + { MODRM_ONEENTRY, 237 }, + { MODRM_ONEENTRY, 238 }, + { MODRM_ONEENTRY, 239 }, + { MODRM_ONEENTRY, 240 }, + { MODRM_ONEENTRY, 241 }, + { MODRM_ONEENTRY, 242 }, + { MODRM_ONEENTRY, 243 }, + { MODRM_ONEENTRY, 244 }, + { MODRM_ONEENTRY, 245 }, + { MODRM_ONEENTRY, 246 }, + { MODRM_ONEENTRY, 247 }, + { MODRM_ONEENTRY, 248 }, + { MODRM_ONEENTRY, 249 }, + { MODRM_ONEENTRY, 250 }, + { MODRM_ONEENTRY, 251 }, + { MODRM_ONEENTRY, 252 }, + { MODRM_ONEENTRY, 253 }, + { MODRM_ONEENTRY, 254 }, + { MODRM_ONEENTRY, 255 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 258 }, + { MODRM_ONEENTRY, 258 }, + { MODRM_ONEENTRY, 258 }, + { MODRM_ONEENTRY, 258 }, + { MODRM_ONEENTRY, 258 }, + { MODRM_ONEENTRY, 258 }, + { MODRM_ONEENTRY, 258 }, + { MODRM_ONEENTRY, 258 }, + { MODRM_SPLITREG, 259 }, + { MODRM_SPLITREG, 275 }, + { MODRM_ONEENTRY, 291 }, + { MODRM_ONEENTRY, 292 }, + { MODRM_SPLITRM, 293 }, + { MODRM_SPLITRM, 295 }, + { MODRM_SPLITMISC, 297 }, + { MODRM_SPLITMISC, 369 }, + { MODRM_ONEENTRY, 441 }, + { MODRM_ONEENTRY, 442 }, + { MODRM_ONEENTRY, 443 }, + { MODRM_ONEENTRY, 444 }, + { MODRM_ONEENTRY, 445 }, + { MODRM_ONEENTRY, 446 }, + { MODRM_ONEENTRY, 447 }, + { MODRM_ONEENTRY, 448 }, + { MODRM_SPLITREG, 449 }, + { MODRM_SPLITREG, 465 }, + { MODRM_SPLITREG, 481 }, + { MODRM_SPLITREG, 497 }, + { MODRM_ONEENTRY, 513 }, + { MODRM_ONEENTRY, 514 }, + { MODRM_ONEENTRY, 515 }, + { MODRM_ONEENTRY, 516 }, + { MODRM_SPLITREG, 517 }, + { MODRM_SPLITMISC, 533 }, + { MODRM_SPLITMISC, 605 }, + { MODRM_SPLITMISC, 677 }, + { MODRM_SPLITREG, 749 }, + { MODRM_SPLITREG, 765 }, + { MODRM_SPLITMISC, 781 }, + { MODRM_SPLITMISC, 853 }, + { MODRM_ONEENTRY, 925 }, + { MODRM_ONEENTRY, 926 }, + { MODRM_ONEENTRY, 927 }, + { MODRM_ONEENTRY, 928 }, + { MODRM_ONEENTRY, 929 }, + { MODRM_ONEENTRY, 930 }, + { MODRM_ONEENTRY, 931 }, + { MODRM_ONEENTRY, 932 }, + { MODRM_ONEENTRY, 933 }, + { MODRM_ONEENTRY, 934 }, + { MODRM_ONEENTRY, 935 }, + { MODRM_ONEENTRY, 936 }, + { MODRM_ONEENTRY, 937 }, + { MODRM_ONEENTRY, 938 }, + { MODRM_ONEENTRY, 939 }, + { MODRM_ONEENTRY, 940 }, + { MODRM_ONEENTRY, 941 }, + { MODRM_ONEENTRY, 942 }, + { MODRM_ONEENTRY, 943 }, + { MODRM_ONEENTRY, 944 }, + { MODRM_ONEENTRY, 945 }, + { MODRM_ONEENTRY, 946 }, + { MODRM_SPLITREG, 947 }, + { MODRM_SPLITREG, 963 }, + { MODRM_ONEENTRY, 979 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 981 }, + { MODRM_ONEENTRY, 982 }, + { MODRM_ONEENTRY, 983 }, + { MODRM_ONEENTRY, 984 }, + { MODRM_SPLITREG, 985 }, + { MODRM_SPLITREG, 1001 }, + } }, + { { + { MODRM_SPLITRM, 1 }, + { MODRM_SPLITRM, 3 }, + { MODRM_SPLITRM, 5 }, + { MODRM_SPLITRM, 7 }, + { MODRM_ONEENTRY, 9 }, + { MODRM_ONEENTRY, 10 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 13 }, + { MODRM_SPLITRM, 15 }, + { MODRM_SPLITRM, 17 }, + { MODRM_SPLITRM, 19 }, + { MODRM_ONEENTRY, 21 }, + { MODRM_ONEENTRY, 22 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 24 }, + { MODRM_SPLITRM, 26 }, + { MODRM_SPLITRM, 28 }, + { MODRM_SPLITRM, 30 }, + { MODRM_ONEENTRY, 32 }, + { MODRM_ONEENTRY, 33 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 36 }, + { MODRM_SPLITRM, 38 }, + { MODRM_SPLITRM, 40 }, + { MODRM_SPLITRM, 42 }, + { MODRM_ONEENTRY, 44 }, + { MODRM_ONEENTRY, 45 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 48 }, + { MODRM_SPLITRM, 50 }, + { MODRM_SPLITRM, 52 }, + { MODRM_SPLITRM, 54 }, + { MODRM_ONEENTRY, 56 }, + { MODRM_ONEENTRY, 57 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 59 }, + { MODRM_SPLITRM, 61 }, + { MODRM_SPLITRM, 63 }, + { MODRM_SPLITRM, 65 }, + { MODRM_ONEENTRY, 67 }, + { MODRM_ONEENTRY, 68 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 70 }, + { MODRM_SPLITRM, 72 }, + { MODRM_SPLITRM, 74 }, + { MODRM_SPLITRM, 76 }, + { MODRM_ONEENTRY, 78 }, + { MODRM_ONEENTRY, 79 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 81 }, + { MODRM_SPLITRM, 83 }, + { MODRM_SPLITRM, 85 }, + { MODRM_SPLITRM, 87 }, + { MODRM_ONEENTRY, 89 }, + { MODRM_ONEENTRY, 90 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1017 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1018 }, + { MODRM_ONEENTRY, 1018 }, + { MODRM_ONEENTRY, 1018 }, + { MODRM_ONEENTRY, 1018 }, + { MODRM_ONEENTRY, 1018 }, + { MODRM_ONEENTRY, 1018 }, + { MODRM_ONEENTRY, 1018 }, + { MODRM_ONEENTRY, 1018 }, + { MODRM_ONEENTRY, 1019 }, + { MODRM_ONEENTRY, 1019 }, + { MODRM_ONEENTRY, 1019 }, + { MODRM_ONEENTRY, 1019 }, + { MODRM_ONEENTRY, 1019 }, + { MODRM_ONEENTRY, 1019 }, + { MODRM_ONEENTRY, 1019 }, + { MODRM_ONEENTRY, 1019 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 102 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1020 }, + { MODRM_SPLITRM, 104 }, + { MODRM_ONEENTRY, 1021 }, + { MODRM_SPLITRM, 107 }, + { MODRM_ONEENTRY, 109 }, + { MODRM_ONEENTRY, 110 }, + { MODRM_ONEENTRY, 111 }, + { MODRM_ONEENTRY, 112 }, + { MODRM_ONEENTRY, 113 }, + { MODRM_ONEENTRY, 114 }, + { MODRM_ONEENTRY, 115 }, + { MODRM_ONEENTRY, 116 }, + { MODRM_ONEENTRY, 117 }, + { MODRM_ONEENTRY, 118 }, + { MODRM_ONEENTRY, 119 }, + { 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MODRM_ONEENTRY, 1483 }, + { MODRM_ONEENTRY, 253 }, + { MODRM_ONEENTRY, 1484 }, + { MODRM_ONEENTRY, 255 }, + { MODRM_ONEENTRY, 1485 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 1486 }, + { MODRM_ONEENTRY, 1486 }, + { MODRM_ONEENTRY, 1486 }, + { MODRM_ONEENTRY, 1486 }, + { MODRM_ONEENTRY, 1486 }, + { MODRM_ONEENTRY, 1486 }, + { MODRM_ONEENTRY, 1486 }, + { MODRM_ONEENTRY, 1486 }, + { MODRM_SPLITREG, 259 }, + { MODRM_SPLITREG, 1487 }, + { MODRM_ONEENTRY, 1223 }, + { MODRM_ONEENTRY, 1224 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITMISC, 297 }, + { MODRM_SPLITMISC, 1644 }, + { MODRM_ONEENTRY, 441 }, + { MODRM_ONEENTRY, 1048 }, + { MODRM_ONEENTRY, 1575 }, + { MODRM_ONEENTRY, 1576 }, + { MODRM_ONEENTRY, 445 }, + { MODRM_ONEENTRY, 446 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1577 }, + { MODRM_SPLITREG, 449 }, + { MODRM_SPLITREG, 1578 }, + { MODRM_SPLITREG, 481 }, + { MODRM_SPLITREG, 1594 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 516 }, + { MODRM_SPLITREG, 517 }, + { MODRM_SPLITMISC, 533 }, + { MODRM_SPLITMISC, 605 }, + { MODRM_SPLITMISC, 677 }, + { MODRM_SPLITREG, 749 }, + { MODRM_SPLITREG, 765 }, + { MODRM_SPLITMISC, 781 }, + { MODRM_SPLITMISC, 853 }, + { MODRM_ONEENTRY, 925 }, + { MODRM_ONEENTRY, 926 }, + { MODRM_ONEENTRY, 927 }, + { MODRM_ONEENTRY, 1049 }, + { MODRM_ONEENTRY, 929 }, + { MODRM_ONEENTRY, 1336 }, + { MODRM_ONEENTRY, 931 }, + { MODRM_ONEENTRY, 1337 }, + { MODRM_ONEENTRY, 1338 }, + { MODRM_ONEENTRY, 1339 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 936 }, + { MODRM_ONEENTRY, 937 }, + { MODRM_ONEENTRY, 1341 }, + { MODRM_ONEENTRY, 939 }, + { MODRM_ONEENTRY, 1342 }, + { MODRM_ONEENTRY, 941 }, + { MODRM_ONEENTRY, 942 }, + { MODRM_ONEENTRY, 943 }, + { MODRM_ONEENTRY, 944 }, + { MODRM_ONEENTRY, 945 }, + { MODRM_ONEENTRY, 946 }, + { MODRM_SPLITREG, 947 }, + { MODRM_SPLITREG, 1610 }, + { MODRM_ONEENTRY, 979 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 981 }, + { MODRM_ONEENTRY, 982 }, + { MODRM_ONEENTRY, 983 }, + { MODRM_ONEENTRY, 984 }, + { MODRM_SPLITREG, 985 }, + { MODRM_SPLITREG, 1716 }, + } }, +}; + +static const unsigned char index_x86DisassemblerTwoByteOpcodes[] = { + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 0, + 8, + 0, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 0, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63, + 64, + 65, + 66, + 67, + 68, + 69, + 70, + 71, + 72, + 73, + 74, + 75, + 76, + 77, + 78, + 79, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 88, + 89, + 90, + 91, + 92, + 93, + 94, + 95, + 96, + 97, + 98, + 99, + 100, + 101, + 102, + 103, + 104, + 105, + 106, + 107, + 108, + 109, + 110, + 111, + 112, + 113, + 114, + 115, + 116, + 117, + 118, + 119, + 120, + 121, + 122, + 123, + 124, + 125, + 126, + 127, + 128, + 129, + 130, + 131, + 132, + 133, + 134, + 135, + 136, + 137, + 138, + 139, + 140, + 141, + 142, + 143, + 144, + 145, + 146, + 147, + 148, + 149, + 150, + 151, + 152, + 153, + 154, + 155, + 156, + 157, + 158, + 159, + 160, + 161, + 162, + 163, + 164, + 165, + 166, + 167, + 168, + 169, + 170, + 171, + 172, + 173, + 174, + 175, + 176, + 177, + 178, + 179, + 180, + 181, + 182, +}; + +static const struct OpcodeDecision x86DisassemblerTwoByteOpcodes[] = { + { { + { MODRM_SPLITREG, 1750 }, + { MODRM_SPLITMISC, 1766 }, + { MODRM_SPLITRM, 1838 }, + { MODRM_SPLITRM, 1840 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1842 }, + { MODRM_ONEENTRY, 1843 }, + { MODRM_ONEENTRY, 1844 }, + { MODRM_ONEENTRY, 1845 }, + { MODRM_ONEENTRY, 1846 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1847 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 1848 }, + { MODRM_ONEENTRY, 1864 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1865 }, + { MODRM_SPLITRM, 1867 }, + { MODRM_SPLITRM, 1869 }, + { MODRM_SPLITRM, 1871 }, + { MODRM_SPLITRM, 1873 }, + { MODRM_SPLITRM, 1875 }, + { MODRM_SPLITRM, 1877 }, + { MODRM_SPLITRM, 1879 }, + { MODRM_SPLITREG, 1881 }, + { MODRM_SPLITRM, 1897 }, + { MODRM_SPLITRM, 1899 }, + { MODRM_SPLITRM, 1901 }, + { MODRM_SPLITREG, 1903 }, + { MODRM_SPLITRM, 1919 }, + { MODRM_SPLITRM, 1921 }, + { MODRM_SPLITRM, 1923 }, + { MODRM_SPLITRM, 1925 }, + { MODRM_SPLITRM, 1927 }, + { MODRM_SPLITRM, 1929 }, + { MODRM_SPLITRM, 1931 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1933 }, + { MODRM_SPLITRM, 1935 }, + { MODRM_SPLITRM, 1937 }, + { MODRM_SPLITRM, 1939 }, + { MODRM_SPLITRM, 1941 }, + { MODRM_SPLITRM, 1943 }, + { MODRM_SPLITRM, 1945 }, + { MODRM_SPLITRM, 1947 }, + { MODRM_ONEENTRY, 1949 }, + { MODRM_ONEENTRY, 1950 }, + { MODRM_ONEENTRY, 1951 }, + { MODRM_ONEENTRY, 1952 }, + { MODRM_ONEENTRY, 1953 }, + { MODRM_ONEENTRY, 1954 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1955 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1956 }, + { MODRM_SPLITRM, 1958 }, + { MODRM_SPLITRM, 1960 }, + { MODRM_SPLITRM, 1962 }, + { MODRM_SPLITRM, 1964 }, + { MODRM_SPLITRM, 1966 }, + { MODRM_SPLITRM, 1968 }, + { MODRM_SPLITRM, 1970 }, + { MODRM_SPLITRM, 1972 }, + { MODRM_SPLITRM, 1974 }, + { MODRM_SPLITRM, 1976 }, + { MODRM_SPLITRM, 1978 }, + { MODRM_SPLITRM, 1980 }, + { MODRM_SPLITRM, 1982 }, + { MODRM_SPLITRM, 1984 }, + { MODRM_SPLITRM, 1986 }, + { MODRM_SPLITRM, 1988 }, + { MODRM_SPLITRM, 1990 }, + { MODRM_SPLITRM, 1992 }, + { MODRM_SPLITRM, 1994 }, + { MODRM_SPLITRM, 1996 }, + { MODRM_SPLITRM, 1998 }, + { MODRM_SPLITRM, 2000 }, + { MODRM_SPLITRM, 2002 }, + { MODRM_SPLITRM, 2004 }, + { MODRM_SPLITRM, 2006 }, + { MODRM_SPLITRM, 2008 }, + { MODRM_SPLITRM, 2010 }, + { MODRM_SPLITRM, 2012 }, + { MODRM_SPLITRM, 2014 }, + { MODRM_SPLITRM, 2016 }, + { MODRM_SPLITRM, 2018 }, + { MODRM_SPLITRM, 2020 }, + { MODRM_SPLITRM, 2022 }, + { MODRM_SPLITRM, 2024 }, + { MODRM_SPLITRM, 2026 }, + { MODRM_SPLITRM, 2028 }, + { MODRM_SPLITRM, 2030 }, + { MODRM_SPLITRM, 2032 }, + { MODRM_SPLITRM, 2034 }, + { MODRM_SPLITRM, 2036 }, + { MODRM_SPLITRM, 2038 }, + { MODRM_SPLITRM, 2040 }, + { MODRM_SPLITRM, 2042 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2044 }, + { MODRM_SPLITRM, 2046 }, + { MODRM_SPLITRM, 2048 }, + { MODRM_SPLITREG, 2050 }, + { MODRM_SPLITREG, 2066 }, + { MODRM_SPLITREG, 2082 }, + { MODRM_SPLITRM, 2098 }, + { MODRM_SPLITRM, 2100 }, + { MODRM_SPLITRM, 2102 }, + { MODRM_ONEENTRY, 2104 }, + { MODRM_SPLITRM, 2105 }, + { MODRM_SPLITRM, 2107 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2109 }, + { MODRM_SPLITRM, 2111 }, + { MODRM_ONEENTRY, 2113 }, + { MODRM_ONEENTRY, 2114 }, + { MODRM_ONEENTRY, 2115 }, + { MODRM_ONEENTRY, 2116 }, + { MODRM_ONEENTRY, 2117 }, + { MODRM_ONEENTRY, 2118 }, + { MODRM_ONEENTRY, 2119 }, + { MODRM_ONEENTRY, 2120 }, + { MODRM_ONEENTRY, 2121 }, + { MODRM_ONEENTRY, 2122 }, + { MODRM_ONEENTRY, 2123 }, + { MODRM_ONEENTRY, 2124 }, + { MODRM_ONEENTRY, 2125 }, + { MODRM_ONEENTRY, 2126 }, + { MODRM_ONEENTRY, 2127 }, + { MODRM_ONEENTRY, 2128 }, + { MODRM_SPLITRM, 2129 }, + { MODRM_SPLITRM, 2131 }, + { MODRM_SPLITRM, 2133 }, + { MODRM_SPLITRM, 2135 }, + { MODRM_SPLITRM, 2137 }, + { MODRM_SPLITRM, 2139 }, + { MODRM_SPLITRM, 2141 }, + { MODRM_SPLITRM, 2143 }, + { MODRM_SPLITRM, 2145 }, + { MODRM_SPLITRM, 2147 }, + { MODRM_SPLITRM, 2149 }, + { MODRM_SPLITRM, 2151 }, + { MODRM_SPLITRM, 2153 }, + { MODRM_SPLITRM, 2155 }, + { MODRM_SPLITRM, 2157 }, + { MODRM_SPLITRM, 2159 }, + { MODRM_ONEENTRY, 2161 }, + { MODRM_ONEENTRY, 2162 }, + { MODRM_ONEENTRY, 2163 }, + { MODRM_SPLITRM, 2164 }, + { MODRM_SPLITRM, 2166 }, + { MODRM_SPLITRM, 2168 }, + { MODRM_SPLITMISC, 2170 }, + { MODRM_SPLITMISC, 2242 }, + { MODRM_ONEENTRY, 2314 }, + { MODRM_ONEENTRY, 2315 }, + { MODRM_ONEENTRY, 2316 }, + { MODRM_SPLITRM, 2317 }, + { MODRM_SPLITRM, 2319 }, + { MODRM_SPLITRM, 2321 }, + { MODRM_SPLITMISC, 2323 }, + { MODRM_SPLITRM, 2395 }, + { MODRM_SPLITRM, 2397 }, + { MODRM_SPLITRM, 2399 }, + { MODRM_SPLITRM, 2401 }, + { MODRM_SPLITRM, 2403 }, + { MODRM_SPLITRM, 2405 }, + { MODRM_SPLITRM, 2407 }, + { MODRM_SPLITRM, 2409 }, + { MODRM_SPLITRM, 2411 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 2413 }, + { MODRM_SPLITREG, 2414 }, + { MODRM_SPLITRM, 2430 }, + { MODRM_SPLITRM, 2432 }, + { MODRM_SPLITRM, 2434 }, + { MODRM_SPLITRM, 2436 }, + { MODRM_SPLITRM, 2438 }, + { MODRM_SPLITRM, 2440 }, + { MODRM_SPLITRM, 2442 }, + { MODRM_SPLITRM, 2444 }, + { MODRM_SPLITRM, 2446 }, + { MODRM_SPLITRM, 2448 }, + { MODRM_SPLITRM, 2450 }, + { MODRM_SPLITRM, 2452 }, + { MODRM_SPLITREG, 2454 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2471 }, + { MODRM_SPLITRM, 2473 }, + { MODRM_SPLITRM, 2475 }, + { MODRM_SPLITRM, 2477 }, + { MODRM_SPLITRM, 2479 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2481 }, + { MODRM_SPLITRM, 2483 }, + { MODRM_SPLITRM, 2485 }, + { MODRM_SPLITRM, 2487 }, + { MODRM_SPLITRM, 2489 }, + { MODRM_SPLITRM, 2491 }, + { MODRM_SPLITRM, 2493 }, + { MODRM_SPLITRM, 2495 }, + { MODRM_SPLITRM, 2497 }, + { MODRM_SPLITRM, 2499 }, + { MODRM_SPLITRM, 2501 }, + { MODRM_SPLITRM, 2503 }, + { MODRM_SPLITRM, 2505 }, + { MODRM_SPLITRM, 2507 }, + { MODRM_SPLITRM, 2509 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2511 }, + { MODRM_SPLITRM, 2513 }, + { MODRM_SPLITRM, 2515 }, + { MODRM_SPLITRM, 2517 }, + { MODRM_SPLITRM, 2519 }, + { MODRM_SPLITRM, 2521 }, + { MODRM_SPLITRM, 2523 }, + { MODRM_SPLITRM, 2525 }, + { MODRM_SPLITRM, 2527 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2529 }, + { MODRM_SPLITRM, 2531 }, + { MODRM_SPLITRM, 2533 }, + { MODRM_SPLITRM, 2535 }, + { MODRM_SPLITRM, 2537 }, + { MODRM_SPLITRM, 2539 }, + { MODRM_SPLITRM, 2541 }, + { MODRM_SPLITRM, 2543 }, + { MODRM_SPLITRM, 2545 }, + { MODRM_SPLITRM, 2547 }, + { MODRM_SPLITRM, 2549 }, + { MODRM_SPLITRM, 2551 }, + { MODRM_SPLITRM, 2553 }, + { MODRM_SPLITRM, 2555 }, + { MODRM_ONEENTRY, 2557 }, + } }, + { { + { MODRM_SPLITREG, 1750 }, + { MODRM_SPLITMISC, 2558 }, + { MODRM_SPLITRM, 1838 }, + { MODRM_SPLITRM, 1840 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1842 }, + { MODRM_ONEENTRY, 1843 }, + { MODRM_ONEENTRY, 1844 }, + { MODRM_ONEENTRY, 1845 }, + { MODRM_ONEENTRY, 1846 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1847 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 1848 }, + { MODRM_ONEENTRY, 1864 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1865 }, + { MODRM_SPLITRM, 1867 }, + { MODRM_SPLITRM, 1869 }, + { MODRM_SPLITRM, 1871 }, + { MODRM_SPLITRM, 1873 }, + { MODRM_SPLITRM, 1875 }, + { MODRM_SPLITRM, 1877 }, + { MODRM_SPLITRM, 1879 }, + { MODRM_SPLITREG, 1881 }, + { MODRM_SPLITRM, 1897 }, + { MODRM_SPLITRM, 1899 }, + { MODRM_SPLITRM, 1901 }, + { MODRM_SPLITREG, 1903 }, + { MODRM_SPLITRM, 1919 }, + { MODRM_SPLITRM, 1921 }, + { MODRM_SPLITRM, 1923 }, + { MODRM_SPLITRM, 2630 }, + { MODRM_SPLITRM, 2632 }, + { MODRM_SPLITRM, 2634 }, + { MODRM_SPLITRM, 2636 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1933 }, + { MODRM_SPLITRM, 1935 }, + { MODRM_SPLITRM, 1937 }, + { MODRM_SPLITRM, 1939 }, + { MODRM_SPLITRM, 1941 }, + { MODRM_SPLITRM, 1943 }, + { MODRM_SPLITRM, 1945 }, + { MODRM_SPLITRM, 1947 }, + { MODRM_ONEENTRY, 1949 }, + { MODRM_ONEENTRY, 1950 }, + { MODRM_ONEENTRY, 1951 }, + { MODRM_ONEENTRY, 1952 }, + { MODRM_ONEENTRY, 1953 }, + { MODRM_ONEENTRY, 1954 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1955 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1956 }, + { MODRM_SPLITRM, 1958 }, + { MODRM_SPLITRM, 1960 }, + { MODRM_SPLITRM, 1962 }, + { MODRM_SPLITRM, 1964 }, + { MODRM_SPLITRM, 1966 }, + { MODRM_SPLITRM, 1968 }, + { MODRM_SPLITRM, 1970 }, + { MODRM_SPLITRM, 1972 }, + { MODRM_SPLITRM, 1974 }, + { MODRM_SPLITRM, 1976 }, + { MODRM_SPLITRM, 1978 }, + { MODRM_SPLITRM, 1980 }, + { MODRM_SPLITRM, 1982 }, + { MODRM_SPLITRM, 1984 }, + { MODRM_SPLITRM, 1986 }, + { MODRM_SPLITRM, 1988 }, + { MODRM_SPLITRM, 1990 }, + { MODRM_SPLITRM, 1992 }, + { MODRM_SPLITRM, 1994 }, + { MODRM_SPLITRM, 1996 }, + { MODRM_SPLITRM, 1998 }, + { MODRM_SPLITRM, 2000 }, + { MODRM_SPLITRM, 2002 }, + { MODRM_SPLITRM, 2004 }, + { MODRM_SPLITRM, 2006 }, + { MODRM_SPLITRM, 2008 }, + { MODRM_SPLITRM, 2010 }, + { MODRM_SPLITRM, 2012 }, + { MODRM_SPLITRM, 2014 }, + { MODRM_SPLITRM, 2016 }, + { MODRM_SPLITRM, 2018 }, + { MODRM_SPLITRM, 2020 }, + { MODRM_SPLITRM, 2022 }, + { MODRM_SPLITRM, 2024 }, + { MODRM_SPLITRM, 2026 }, + { MODRM_SPLITRM, 2028 }, + { MODRM_SPLITRM, 2030 }, + { MODRM_SPLITRM, 2032 }, + { MODRM_SPLITRM, 2034 }, + { MODRM_SPLITRM, 2036 }, + { MODRM_SPLITRM, 2038 }, + { MODRM_SPLITRM, 2040 }, + { MODRM_SPLITRM, 2042 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2044 }, + { MODRM_SPLITRM, 2046 }, + { MODRM_SPLITRM, 2048 }, + { MODRM_SPLITREG, 2050 }, + { MODRM_SPLITREG, 2066 }, + { MODRM_SPLITREG, 2082 }, + { MODRM_SPLITRM, 2098 }, + { MODRM_SPLITRM, 2100 }, + { MODRM_SPLITRM, 2102 }, + { MODRM_ONEENTRY, 2104 }, + { MODRM_SPLITRM, 2638 }, + { MODRM_SPLITRM, 2640 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2109 }, + { MODRM_SPLITRM, 2111 }, + { MODRM_ONEENTRY, 2113 }, + { MODRM_ONEENTRY, 2114 }, + { MODRM_ONEENTRY, 2115 }, + { MODRM_ONEENTRY, 2116 }, + { MODRM_ONEENTRY, 2117 }, + { MODRM_ONEENTRY, 2118 }, + { MODRM_ONEENTRY, 2119 }, + { MODRM_ONEENTRY, 2120 }, + { MODRM_ONEENTRY, 2121 }, + { MODRM_ONEENTRY, 2122 }, + { MODRM_ONEENTRY, 2123 }, + { MODRM_ONEENTRY, 2124 }, + { MODRM_ONEENTRY, 2125 }, + { MODRM_ONEENTRY, 2126 }, + { MODRM_ONEENTRY, 2127 }, + { MODRM_ONEENTRY, 2128 }, + { MODRM_SPLITRM, 2129 }, + { MODRM_SPLITRM, 2131 }, + { MODRM_SPLITRM, 2133 }, + { MODRM_SPLITRM, 2135 }, + { MODRM_SPLITRM, 2137 }, + { MODRM_SPLITRM, 2139 }, + { MODRM_SPLITRM, 2141 }, + { MODRM_SPLITRM, 2143 }, + { MODRM_SPLITRM, 2145 }, + { MODRM_SPLITRM, 2147 }, + { MODRM_SPLITRM, 2149 }, + { MODRM_SPLITRM, 2151 }, + { MODRM_SPLITRM, 2153 }, + { MODRM_SPLITRM, 2155 }, + { MODRM_SPLITRM, 2157 }, + { MODRM_SPLITRM, 2159 }, + { MODRM_ONEENTRY, 2642 }, + { MODRM_ONEENTRY, 2643 }, + { MODRM_ONEENTRY, 2163 }, + { MODRM_SPLITRM, 2164 }, + { MODRM_SPLITRM, 2166 }, + { MODRM_SPLITRM, 2168 }, + { MODRM_SPLITMISC, 2170 }, + { MODRM_SPLITMISC, 2242 }, + { MODRM_ONEENTRY, 2644 }, + { MODRM_ONEENTRY, 2645 }, + { MODRM_ONEENTRY, 2316 }, + { MODRM_SPLITRM, 2317 }, + { MODRM_SPLITRM, 2319 }, + { MODRM_SPLITRM, 2321 }, + { MODRM_SPLITMISC, 2323 }, + { MODRM_SPLITRM, 2395 }, + { MODRM_SPLITRM, 2397 }, + { MODRM_SPLITRM, 2399 }, + { MODRM_SPLITRM, 2401 }, + { MODRM_SPLITRM, 2403 }, + { MODRM_SPLITRM, 2405 }, + { MODRM_SPLITRM, 2407 }, + { MODRM_SPLITRM, 2409 }, + { MODRM_SPLITRM, 2411 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 2413 }, + { MODRM_SPLITREG, 2414 }, + { MODRM_SPLITRM, 2430 }, + { MODRM_SPLITRM, 2432 }, + { MODRM_SPLITRM, 2434 }, + { MODRM_SPLITRM, 2436 }, + { MODRM_SPLITRM, 2438 }, + { MODRM_SPLITRM, 2440 }, + { MODRM_SPLITRM, 2442 }, + { MODRM_SPLITRM, 2444 }, + { MODRM_SPLITRM, 2446 }, + { MODRM_SPLITRM, 2448 }, + { MODRM_SPLITRM, 2450 }, + { MODRM_SPLITRM, 2452 }, + { MODRM_SPLITREG, 2454 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2471 }, + { MODRM_SPLITRM, 2473 }, + { MODRM_SPLITRM, 2475 }, + { MODRM_SPLITRM, 2477 }, + { MODRM_SPLITRM, 2479 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2481 }, + { MODRM_SPLITRM, 2483 }, + { MODRM_SPLITRM, 2485 }, + { MODRM_SPLITRM, 2487 }, + { MODRM_SPLITRM, 2489 }, + { MODRM_SPLITRM, 2491 }, + { MODRM_SPLITRM, 2493 }, + { MODRM_SPLITRM, 2495 }, + { MODRM_SPLITRM, 2497 }, + { MODRM_SPLITRM, 2499 }, + { MODRM_SPLITRM, 2501 }, + { MODRM_SPLITRM, 2503 }, + { MODRM_SPLITRM, 2505 }, + { MODRM_SPLITRM, 2507 }, + { MODRM_SPLITRM, 2509 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2511 }, + { MODRM_SPLITRM, 2513 }, + { MODRM_SPLITRM, 2515 }, + { MODRM_SPLITRM, 2517 }, + { MODRM_SPLITRM, 2519 }, + { MODRM_SPLITRM, 2521 }, + { MODRM_SPLITRM, 2523 }, + { MODRM_SPLITRM, 2525 }, + { MODRM_SPLITRM, 2527 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2529 }, + { MODRM_SPLITRM, 2531 }, + { MODRM_SPLITRM, 2533 }, + { MODRM_SPLITRM, 2535 }, + { MODRM_SPLITRM, 2537 }, + { MODRM_SPLITRM, 2539 }, + { MODRM_SPLITRM, 2646 }, + { MODRM_SPLITRM, 2543 }, + { MODRM_SPLITRM, 2545 }, + { MODRM_SPLITRM, 2547 }, + { MODRM_SPLITRM, 2549 }, + { MODRM_SPLITRM, 2551 }, + { MODRM_SPLITRM, 2553 }, + { MODRM_SPLITRM, 2555 }, + { MODRM_ONEENTRY, 2557 }, + } }, + { { + { MODRM_SPLITREG, 2648 }, + { MODRM_SPLITMISC, 2664 }, + { MODRM_SPLITRM, 2736 }, + { MODRM_SPLITRM, 2738 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1842 }, + { MODRM_ONEENTRY, 1843 }, + { MODRM_ONEENTRY, 1844 }, + { MODRM_ONEENTRY, 1845 }, + { MODRM_ONEENTRY, 1846 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1847 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 1848 }, + { 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MODRM_SPLITRM, 3133 }, + { MODRM_SPLITRM, 3135 }, + { MODRM_SPLITRM, 3137 }, + { MODRM_SPLITRM, 3139 }, + { MODRM_SPLITRM, 3141 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 3143 }, + { MODRM_SPLITRM, 3145 }, + { MODRM_SPLITRM, 3147 }, + { MODRM_SPLITRM, 3149 }, + { MODRM_SPLITRM, 3151 }, + { MODRM_SPLITRM, 3153 }, + { MODRM_SPLITRM, 3155 }, + { MODRM_SPLITRM, 3157 }, + { MODRM_SPLITRM, 3159 }, + { MODRM_SPLITRM, 3161 }, + { MODRM_SPLITRM, 3163 }, + { MODRM_SPLITRM, 3165 }, + { MODRM_SPLITRM, 3167 }, + { MODRM_SPLITRM, 3169 }, + { MODRM_ONEENTRY, 2557 }, + } }, + { { + { MODRM_SPLITREG, 1750 }, + { MODRM_SPLITMISC, 1766 }, + { MODRM_SPLITRM, 1838 }, + { MODRM_SPLITRM, 1840 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1842 }, + { MODRM_ONEENTRY, 1843 }, + { MODRM_ONEENTRY, 1844 }, + { MODRM_ONEENTRY, 1845 }, + { MODRM_ONEENTRY, 1846 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1847 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 1848 }, + { MODRM_ONEENTRY, 1864 }, + { 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MODRM_SPLITRM, 2742 }, + { MODRM_SPLITRM, 3171 }, + { MODRM_SPLITRM, 2746 }, + { MODRM_SPLITRM, 2748 }, + { MODRM_SPLITRM, 2750 }, + { MODRM_SPLITRM, 3173 }, + { MODRM_SPLITRM, 2754 }, + { MODRM_SPLITREG, 2756 }, + { MODRM_SPLITRM, 2772 }, + { MODRM_SPLITRM, 2774 }, + { MODRM_SPLITRM, 2776 }, + { MODRM_SPLITRM, 2778 }, + { MODRM_SPLITRM, 2780 }, + { MODRM_SPLITRM, 2782 }, + { MODRM_SPLITRM, 2784 }, + { MODRM_SPLITRM, 1925 }, + { MODRM_SPLITRM, 1927 }, + { MODRM_SPLITRM, 1929 }, + { MODRM_SPLITRM, 1931 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2786 }, + { MODRM_SPLITRM, 2788 }, + { MODRM_SPLITRM, 2790 }, + { MODRM_SPLITRM, 2792 }, + { MODRM_SPLITRM, 2794 }, + { MODRM_SPLITRM, 2796 }, + { MODRM_SPLITRM, 2798 }, + { MODRM_SPLITRM, 2800 }, + { MODRM_ONEENTRY, 1949 }, + { MODRM_ONEENTRY, 1950 }, + { MODRM_ONEENTRY, 1951 }, + { MODRM_ONEENTRY, 1952 }, + { MODRM_ONEENTRY, 1953 }, + { MODRM_ONEENTRY, 1954 }, + { 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2852 }, + { MODRM_SPLITRM, 2854 }, + { MODRM_SPLITRM, 2856 }, + { MODRM_SPLITRM, 2858 }, + { MODRM_SPLITRM, 2860 }, + { MODRM_SPLITRM, 2862 }, + { MODRM_SPLITRM, 2864 }, + { MODRM_SPLITRM, 2866 }, + { MODRM_SPLITRM, 2868 }, + { MODRM_SPLITRM, 2870 }, + { MODRM_SPLITRM, 2872 }, + { MODRM_SPLITRM, 2874 }, + { MODRM_SPLITRM, 2876 }, + { MODRM_SPLITRM, 2878 }, + { MODRM_SPLITRM, 2880 }, + { MODRM_SPLITRM, 2882 }, + { MODRM_SPLITRM, 2884 }, + { MODRM_SPLITRM, 2886 }, + { MODRM_SPLITRM, 2888 }, + { MODRM_SPLITRM, 2890 }, + { MODRM_SPLITRM, 2892 }, + { MODRM_SPLITRM, 2894 }, + { MODRM_SPLITREG, 2896 }, + { MODRM_SPLITREG, 2912 }, + { MODRM_SPLITREG, 2928 }, + { MODRM_SPLITRM, 2944 }, + { MODRM_SPLITRM, 2946 }, + { MODRM_SPLITRM, 2948 }, + { MODRM_ONEENTRY, 2104 }, + { MODRM_SPLITRM, 3175 }, + { MODRM_SPLITRM, 3177 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2954 }, + { MODRM_SPLITRM, 2956 }, + { MODRM_SPLITRM, 2958 }, + { MODRM_SPLITRM, 2960 }, + { MODRM_ONEENTRY, 2962 }, + { MODRM_ONEENTRY, 2963 }, + { MODRM_ONEENTRY, 2964 }, + { MODRM_ONEENTRY, 2965 }, + { MODRM_ONEENTRY, 2966 }, + { MODRM_ONEENTRY, 2967 }, + { MODRM_ONEENTRY, 2968 }, + { MODRM_ONEENTRY, 2969 }, + { MODRM_ONEENTRY, 2970 }, + { MODRM_ONEENTRY, 2971 }, + { MODRM_ONEENTRY, 2972 }, + { MODRM_ONEENTRY, 2973 }, + { MODRM_ONEENTRY, 2974 }, + { MODRM_ONEENTRY, 2975 }, + { MODRM_ONEENTRY, 2976 }, + { MODRM_ONEENTRY, 2977 }, + { MODRM_SPLITRM, 2129 }, + { MODRM_SPLITRM, 2131 }, + { MODRM_SPLITRM, 2133 }, + { MODRM_SPLITRM, 2135 }, + { MODRM_SPLITRM, 2137 }, + { MODRM_SPLITRM, 2139 }, + { MODRM_SPLITRM, 2141 }, + { MODRM_SPLITRM, 2143 }, + { MODRM_SPLITRM, 2145 }, + { MODRM_SPLITRM, 2147 }, + { MODRM_SPLITRM, 2149 }, + { MODRM_SPLITRM, 2151 }, + { MODRM_SPLITRM, 2153 }, + { MODRM_SPLITRM, 2155 }, + { MODRM_SPLITRM, 2157 }, + { MODRM_SPLITRM, 2159 }, + { MODRM_ONEENTRY, 2978 }, + { MODRM_ONEENTRY, 2979 }, + { MODRM_ONEENTRY, 2163 }, + { MODRM_SPLITRM, 2980 }, + { MODRM_SPLITRM, 2982 }, + { MODRM_SPLITRM, 2984 }, + { MODRM_SPLITMISC, 2170 }, + { MODRM_SPLITMISC, 2242 }, + { MODRM_ONEENTRY, 2986 }, + { MODRM_ONEENTRY, 2987 }, + { MODRM_ONEENTRY, 2316 }, + { MODRM_SPLITRM, 2988 }, + { MODRM_SPLITRM, 2990 }, + { MODRM_SPLITRM, 2992 }, + { MODRM_SPLITMISC, 3179 }, + { MODRM_SPLITRM, 3010 }, + { MODRM_SPLITRM, 2397 }, + { MODRM_SPLITRM, 3012 }, + { MODRM_SPLITRM, 3014 }, + { MODRM_SPLITRM, 3016 }, + { MODRM_SPLITRM, 3018 }, + { MODRM_SPLITRM, 3020 }, + { MODRM_SPLITRM, 3022 }, + { MODRM_SPLITRM, 3024 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 2413 }, + { MODRM_SPLITREG, 3026 }, + { MODRM_SPLITRM, 3042 }, + { MODRM_SPLITRM, 3044 }, + { MODRM_SPLITRM, 3046 }, + { MODRM_SPLITRM, 3048 }, + { MODRM_SPLITRM, 3050 }, + { MODRM_SPLITRM, 2440 }, + { MODRM_SPLITRM, 3052 }, + { MODRM_SPLITRM, 3054 }, + { MODRM_SPLITRM, 2446 }, + { MODRM_SPLITRM, 3056 }, + { MODRM_SPLITRM, 3058 }, + { MODRM_SPLITRM, 3060 }, + { MODRM_SPLITREG, 3251 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_SPLITRM, 3079 }, + { MODRM_SPLITRM, 3081 }, + { MODRM_SPLITRM, 3083 }, + { MODRM_SPLITRM, 3085 }, + { MODRM_SPLITRM, 3087 }, + { MODRM_SPLITRM, 3089 }, + { MODRM_SPLITRM, 3091 }, + { MODRM_SPLITRM, 3093 }, + { MODRM_SPLITRM, 3095 }, + { MODRM_SPLITRM, 3097 }, + { MODRM_SPLITRM, 3099 }, + { MODRM_SPLITRM, 3101 }, + { MODRM_SPLITRM, 3103 }, + { MODRM_SPLITRM, 3105 }, + { MODRM_SPLITRM, 3107 }, + { MODRM_SPLITRM, 3109 }, + { MODRM_SPLITRM, 3111 }, + { MODRM_SPLITRM, 3113 }, + { MODRM_SPLITRM, 3115 }, + { MODRM_SPLITRM, 3117 }, + { MODRM_SPLITRM, 3119 }, + { MODRM_SPLITRM, 3121 }, + { MODRM_SPLITRM, 3123 }, + { MODRM_SPLITRM, 3125 }, + { MODRM_SPLITRM, 3127 }, + { MODRM_SPLITRM, 3129 }, + { MODRM_SPLITRM, 3131 }, + { MODRM_SPLITRM, 3133 }, + { MODRM_SPLITRM, 3135 }, + { MODRM_SPLITRM, 3137 }, + { MODRM_SPLITRM, 3139 }, + { MODRM_SPLITRM, 3141 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 3143 }, + { MODRM_SPLITRM, 3145 }, + { MODRM_SPLITRM, 3147 }, + { MODRM_SPLITRM, 3149 }, + { MODRM_SPLITRM, 3151 }, + { MODRM_SPLITRM, 3153 }, + { MODRM_SPLITRM, 3155 }, + { MODRM_SPLITRM, 3157 }, + { MODRM_SPLITRM, 3159 }, + { MODRM_SPLITRM, 3161 }, + { MODRM_SPLITRM, 3163 }, + { MODRM_SPLITRM, 3165 }, + { MODRM_SPLITRM, 3167 }, + { MODRM_SPLITRM, 3169 }, + { MODRM_ONEENTRY, 2557 }, + } }, + { { + { MODRM_SPLITREG, 1750 }, + { MODRM_SPLITMISC, 1766 }, + { MODRM_SPLITRM, 1838 }, + { MODRM_SPLITRM, 1840 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1842 }, + { MODRM_ONEENTRY, 1843 }, + { MODRM_ONEENTRY, 1844 }, + { MODRM_ONEENTRY, 1845 }, + { MODRM_ONEENTRY, 1846 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1847 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 1848 }, + { MODRM_ONEENTRY, 1864 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 3267 }, + { MODRM_SPLITRM, 3269 }, + { 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MODRM_SPLITRM, 2141 }, + { MODRM_SPLITRM, 2143 }, + { MODRM_SPLITRM, 2145 }, + { MODRM_SPLITRM, 2147 }, + { MODRM_SPLITRM, 2149 }, + { MODRM_SPLITRM, 2151 }, + { MODRM_SPLITRM, 2153 }, + { MODRM_SPLITRM, 2155 }, + { MODRM_SPLITRM, 2157 }, + { MODRM_SPLITRM, 2159 }, + { MODRM_ONEENTRY, 2642 }, + { MODRM_ONEENTRY, 2643 }, + { MODRM_ONEENTRY, 2163 }, + { MODRM_SPLITRM, 3746 }, + { MODRM_SPLITRM, 3748 }, + { MODRM_SPLITRM, 3750 }, + { MODRM_SPLITMISC, 2170 }, + { MODRM_SPLITMISC, 2242 }, + { MODRM_ONEENTRY, 2644 }, + { MODRM_ONEENTRY, 2645 }, + { MODRM_ONEENTRY, 2316 }, + { MODRM_SPLITRM, 3752 }, + { MODRM_SPLITRM, 3754 }, + { MODRM_SPLITRM, 3756 }, + { MODRM_SPLITMISC, 3758 }, + { MODRM_SPLITRM, 3830 }, + { MODRM_SPLITRM, 2397 }, + { MODRM_SPLITRM, 3832 }, + { MODRM_SPLITRM, 3834 }, + { MODRM_SPLITRM, 3836 }, + { MODRM_SPLITRM, 3838 }, + { MODRM_SPLITRM, 3840 }, + { MODRM_SPLITRM, 3842 }, + { MODRM_SPLITRM, 3844 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 2413 }, + { MODRM_SPLITREG, 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MODRM_SPLITRM, 2497 }, + { MODRM_SPLITRM, 2499 }, + { MODRM_SPLITRM, 2501 }, + { MODRM_SPLITRM, 2503 }, + { MODRM_SPLITRM, 2505 }, + { MODRM_SPLITRM, 2507 }, + { MODRM_SPLITRM, 2509 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2511 }, + { MODRM_SPLITRM, 2513 }, + { MODRM_SPLITRM, 2515 }, + { MODRM_SPLITRM, 2517 }, + { MODRM_SPLITRM, 2519 }, + { MODRM_SPLITRM, 2521 }, + { MODRM_SPLITRM, 2523 }, + { MODRM_SPLITRM, 2525 }, + { MODRM_SPLITRM, 2527 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2529 }, + { MODRM_SPLITRM, 2531 }, + { MODRM_SPLITRM, 2533 }, + { MODRM_SPLITRM, 2535 }, + { MODRM_SPLITRM, 2537 }, + { MODRM_SPLITRM, 2539 }, + { MODRM_SPLITRM, 2646 }, + { MODRM_SPLITRM, 2543 }, + { MODRM_SPLITRM, 2545 }, + { MODRM_SPLITRM, 2547 }, + { MODRM_SPLITRM, 2549 }, + { MODRM_SPLITRM, 2551 }, + { MODRM_SPLITRM, 2553 }, + { MODRM_SPLITRM, 2555 }, + { MODRM_ONEENTRY, 2557 }, + } }, + { { + { MODRM_SPLITREG, 3614 }, + { MODRM_SPLITMISC, 3630 }, + { MODRM_SPLITRM, 3702 }, + { MODRM_SPLITRM, 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2145 }, + { MODRM_SPLITRM, 2147 }, + { MODRM_SPLITRM, 2149 }, + { MODRM_SPLITRM, 2151 }, + { MODRM_SPLITRM, 2153 }, + { MODRM_SPLITRM, 2155 }, + { MODRM_SPLITRM, 2157 }, + { MODRM_SPLITRM, 2159 }, + { MODRM_ONEENTRY, 2978 }, + { MODRM_ONEENTRY, 2979 }, + { MODRM_ONEENTRY, 2163 }, + { MODRM_SPLITRM, 2980 }, + { MODRM_SPLITRM, 2982 }, + { MODRM_SPLITRM, 2984 }, + { MODRM_SPLITMISC, 2170 }, + { MODRM_SPLITMISC, 2242 }, + { MODRM_ONEENTRY, 2986 }, + { MODRM_ONEENTRY, 2987 }, + { MODRM_ONEENTRY, 2316 }, + { MODRM_SPLITRM, 2988 }, + { MODRM_SPLITRM, 2990 }, + { MODRM_SPLITRM, 2992 }, + { MODRM_SPLITREG, 2994 }, + { MODRM_SPLITRM, 3010 }, + { MODRM_SPLITRM, 2397 }, + { MODRM_SPLITRM, 3012 }, + { MODRM_SPLITRM, 3014 }, + { MODRM_SPLITRM, 3016 }, + { MODRM_SPLITRM, 3018 }, + { MODRM_SPLITRM, 3020 }, + { MODRM_SPLITRM, 3022 }, + { MODRM_SPLITRM, 3024 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 2413 }, + { MODRM_SPLITREG, 3026 }, + { MODRM_SPLITRM, 3042 }, + { MODRM_SPLITRM, 3044 }, + { MODRM_SPLITRM, 3046 }, + { MODRM_SPLITRM, 3048 }, + { MODRM_SPLITRM, 3050 }, + { MODRM_SPLITRM, 2440 }, + { MODRM_SPLITRM, 3052 }, + { MODRM_SPLITRM, 3054 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 3056 }, + { MODRM_SPLITRM, 3058 }, + { MODRM_SPLITRM, 3060 }, + { MODRM_SPLITREG, 3062 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_ONEENTRY, 3078 }, + { MODRM_SPLITRM, 3079 }, + { MODRM_SPLITRM, 3081 }, + { MODRM_SPLITRM, 3083 }, + { MODRM_SPLITRM, 3085 }, + { MODRM_SPLITRM, 3087 }, + { MODRM_SPLITRM, 3089 }, + { MODRM_SPLITRM, 3091 }, + { MODRM_SPLITRM, 3093 }, + { MODRM_SPLITRM, 3095 }, + { MODRM_SPLITRM, 3097 }, + { MODRM_SPLITRM, 3099 }, + { MODRM_SPLITRM, 3101 }, + { MODRM_SPLITRM, 3103 }, + { MODRM_SPLITRM, 3105 }, + { MODRM_SPLITRM, 3107 }, + { MODRM_SPLITRM, 3109 }, + { MODRM_SPLITRM, 3111 }, + { MODRM_SPLITRM, 3113 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MODRM_ONEENTRY, 1843 }, + { MODRM_ONEENTRY, 1844 }, + { MODRM_ONEENTRY, 1845 }, + { MODRM_ONEENTRY, 1846 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1847 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 1848 }, + { MODRM_ONEENTRY, 1864 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1865 }, + { MODRM_SPLITRM, 1867 }, + { MODRM_SPLITRM, 1869 }, + { MODRM_SPLITRM, 1871 }, + { MODRM_SPLITRM, 1873 }, + { MODRM_SPLITRM, 1875 }, + { MODRM_SPLITRM, 1877 }, + { MODRM_SPLITRM, 1879 }, + { MODRM_SPLITREG, 1881 }, + { MODRM_SPLITRM, 1897 }, + { MODRM_SPLITRM, 1899 }, + { MODRM_SPLITRM, 1901 }, + { MODRM_SPLITREG, 1903 }, + { MODRM_SPLITRM, 1919 }, + { MODRM_SPLITRM, 1921 }, + { MODRM_SPLITRM, 1923 }, + { MODRM_SPLITRM, 2630 }, + { MODRM_SPLITRM, 2632 }, + { MODRM_SPLITRM, 2634 }, + { MODRM_SPLITRM, 2636 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1933 }, + { MODRM_SPLITRM, 1935 }, + { MODRM_SPLITRM, 1937 }, + { MODRM_SPLITRM, 1939 }, + { MODRM_SPLITRM, 1941 }, + { MODRM_SPLITRM, 1943 }, + { MODRM_SPLITRM, 1945 }, + { MODRM_SPLITRM, 1947 }, + { MODRM_ONEENTRY, 1949 }, + { MODRM_ONEENTRY, 1950 }, + { MODRM_ONEENTRY, 1951 }, + { MODRM_ONEENTRY, 1952 }, + { MODRM_ONEENTRY, 1953 }, + { MODRM_ONEENTRY, 1954 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1955 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1956 }, + { MODRM_SPLITRM, 1958 }, + { MODRM_SPLITRM, 1960 }, + { MODRM_SPLITRM, 1962 }, + { MODRM_SPLITRM, 1964 }, + { MODRM_SPLITRM, 1966 }, + { MODRM_SPLITRM, 1968 }, + { MODRM_SPLITRM, 1970 }, + { MODRM_SPLITRM, 1972 }, + { MODRM_SPLITRM, 1974 }, + { MODRM_SPLITRM, 1976 }, + { MODRM_SPLITRM, 1978 }, + { MODRM_SPLITRM, 1980 }, + { MODRM_SPLITRM, 1982 }, + { MODRM_SPLITRM, 1984 }, + { MODRM_SPLITRM, 1986 }, + { MODRM_SPLITRM, 1988 }, + { MODRM_SPLITRM, 1990 }, + { MODRM_SPLITRM, 1992 }, + { MODRM_SPLITRM, 1994 }, + { MODRM_SPLITRM, 1996 }, + { MODRM_SPLITRM, 1998 }, + { MODRM_SPLITRM, 2000 }, + { MODRM_SPLITRM, 2002 }, + { MODRM_SPLITRM, 2004 }, + { MODRM_SPLITRM, 2006 }, + { MODRM_SPLITRM, 2008 }, + { MODRM_SPLITRM, 2010 }, + { MODRM_SPLITRM, 2012 }, + { MODRM_SPLITRM, 2014 }, + { MODRM_SPLITRM, 2016 }, + { MODRM_SPLITRM, 2018 }, + { MODRM_SPLITRM, 2020 }, + { MODRM_SPLITRM, 2022 }, + { MODRM_SPLITRM, 2024 }, + { MODRM_SPLITRM, 2026 }, + { MODRM_SPLITRM, 2028 }, + { MODRM_SPLITRM, 2030 }, + { MODRM_SPLITRM, 2032 }, + { MODRM_SPLITRM, 2034 }, + { MODRM_SPLITRM, 2036 }, + { MODRM_SPLITRM, 2038 }, + { MODRM_SPLITRM, 2040 }, + { MODRM_SPLITRM, 2042 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2044 }, + { MODRM_SPLITRM, 2046 }, + { MODRM_SPLITRM, 2048 }, + { MODRM_SPLITREG, 2050 }, + { MODRM_SPLITREG, 2066 }, + { MODRM_SPLITREG, 2082 }, + { MODRM_SPLITRM, 2098 }, + { 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MODRM_SPLITRM, 2436 }, + { MODRM_SPLITRM, 2438 }, + { MODRM_SPLITRM, 2440 }, + { MODRM_SPLITRM, 2442 }, + { MODRM_SPLITRM, 2444 }, + { MODRM_SPLITRM, 2446 }, + { MODRM_SPLITRM, 2448 }, + { MODRM_SPLITRM, 2450 }, + { MODRM_SPLITRM, 2452 }, + { MODRM_SPLITREG, 2454 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 2470 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2471 }, + { MODRM_SPLITRM, 2473 }, + { MODRM_SPLITRM, 2475 }, + { MODRM_SPLITRM, 2477 }, + { MODRM_SPLITRM, 2479 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2481 }, + { MODRM_SPLITRM, 2483 }, + { MODRM_SPLITRM, 2485 }, + { MODRM_SPLITRM, 2487 }, + { MODRM_SPLITRM, 2489 }, + { MODRM_SPLITRM, 2491 }, + { MODRM_SPLITRM, 2493 }, + { MODRM_SPLITRM, 2495 }, + { MODRM_SPLITRM, 2497 }, + { MODRM_SPLITRM, 2499 }, + { MODRM_SPLITRM, 2501 }, + { MODRM_SPLITRM, 2503 }, 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MODRM_SPLITRM, 10659 }, + { MODRM_SPLITRM, 10661 }, + { MODRM_SPLITRM, 10663 }, + { MODRM_SPLITRM, 10809 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10811 }, + { MODRM_SPLITRM, 10813 }, + { MODRM_SPLITRM, 10671 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10673 }, + { MODRM_SPLITRM, 10675 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10815 }, + { MODRM_SPLITRM, 10679 }, + { MODRM_SPLITRM, 10681 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, +}; + +static const unsigned char index_x86DisassemblerThreeByte38Opcodes[] = { + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 0, + 0, + 0, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 0, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 0, + 0, + 0, + 30, + 0, + 0, + 0, + 31, + 0, + 32, + 33, + 34, + 0, + 35, + 0, + 36, + 0, + 37, + 0, + 38, + 0, + 39, + 0, + 40, + 0, + 41, + 42, + 43, + 0, + 44, + 0, + 45, + 0, + 46, + 47, + 48, + 0, + 49, + 0, + 50, + 0, + 51, + 0, + 52, + 0, + 53, + 0, + 54, + 0, + 55, + 56, + 57, + 0, + 58, + 0, + 59, + 0, + 60, + 0, + 61, + 0, + 62, + 0, + 63, + 0, + 64, + 0, + 65, + 0, + 66, + 0, + 67, + 0, + 68, + 0, + 69, + 0, + 70, + 0, + 71, + 0, + 72, + 0, + 73, + 0, + 74, + 0, + 75, + 0, + 76, + 0, + 77, + 0, + 78, + 0, + 79, + 0, + 80, + 0, + 81, + 0, + 82, + 0, + 83, + 0, + 0, + 0, + 84, + 0, + 0, + 0, + 85, + 0, + 0, + 0, + 86, + 0, + 0, + 0, + 87, + 0, + 0, + 0, + 88, + 0, + 0, + 0, + 89, + 0, + 90, + 91, + 92, + 0, + 0, + 0, + 93, + 0, + 94, + 0, + 95, + 0, + 0, + 0, + 96, + 0, + 97, + 98, + 99, + 0, + 0, + 0, + 100, +}; + +static const struct OpcodeDecision x86DisassemblerThreeByte38Opcodes[] = { + { { + { MODRM_SPLITRM, 10817 }, + { MODRM_SPLITRM, 10819 }, + { MODRM_SPLITRM, 10821 }, + { MODRM_SPLITRM, 10823 }, + { MODRM_SPLITRM, 10825 }, + { MODRM_SPLITRM, 10827 }, + { MODRM_SPLITRM, 10829 }, + { MODRM_SPLITRM, 10831 }, + { MODRM_SPLITRM, 10833 }, + { MODRM_SPLITRM, 10835 }, + { MODRM_SPLITRM, 10837 }, + { MODRM_SPLITRM, 10839 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10841 }, + { MODRM_SPLITRM, 10843 }, + { MODRM_SPLITRM, 10845 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10847 }, + { MODRM_SPLITRM, 10849 }, + { MODRM_SPLITRM, 10851 }, + { MODRM_SPLITRM, 10853 }, + { MODRM_SPLITRM, 10855 }, + { MODRM_SPLITRM, 10857 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10859 }, + { MODRM_SPLITRM, 10861 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10863 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10865 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, + { { + { MODRM_SPLITRM, 10817 }, + { MODRM_SPLITRM, 10819 }, + { MODRM_SPLITRM, 10821 }, + { MODRM_SPLITRM, 10823 }, + { MODRM_SPLITRM, 10825 }, + { MODRM_SPLITRM, 10827 }, + { MODRM_SPLITRM, 10829 }, + { MODRM_SPLITRM, 10831 }, + { MODRM_SPLITRM, 10833 }, + { MODRM_SPLITRM, 10835 }, + { MODRM_SPLITRM, 10837 }, + { MODRM_SPLITRM, 10839 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10841 }, + { MODRM_SPLITRM, 10843 }, + { MODRM_SPLITRM, 10845 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10847 }, + { MODRM_SPLITRM, 10849 }, + { MODRM_SPLITRM, 10851 }, + { MODRM_SPLITRM, 10853 }, + { MODRM_SPLITRM, 10855 }, + { MODRM_SPLITRM, 10857 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10859 }, + { MODRM_SPLITRM, 10861 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10863 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10865 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, + { { + { MODRM_SPLITRM, 10867 }, + { MODRM_SPLITRM, 10869 }, + { MODRM_SPLITRM, 10871 }, + { MODRM_SPLITRM, 10873 }, + { MODRM_SPLITRM, 10875 }, + { MODRM_SPLITRM, 10877 }, + { MODRM_SPLITRM, 10879 }, + { MODRM_SPLITRM, 10881 }, + { MODRM_SPLITRM, 10883 }, + { MODRM_SPLITRM, 10885 }, + { MODRM_SPLITRM, 10887 }, + { MODRM_SPLITRM, 10889 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10891 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10893 }, + { MODRM_SPLITRM, 10895 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10897 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10899 }, + { MODRM_SPLITRM, 10901 }, + { MODRM_SPLITRM, 10903 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10905 }, + { MODRM_SPLITRM, 10907 }, + { MODRM_SPLITRM, 10909 }, + { MODRM_SPLITRM, 10911 }, + { MODRM_SPLITRM, 10913 }, + { MODRM_SPLITRM, 10915 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10917 }, + { MODRM_SPLITRM, 10919 }, + { MODRM_SPLITRM, 10921 }, + { MODRM_SPLITRM, 10923 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10925 }, + { MODRM_SPLITRM, 10927 }, + { MODRM_SPLITRM, 10929 }, + { MODRM_SPLITRM, 10931 }, + { MODRM_SPLITRM, 10933 }, + { MODRM_SPLITRM, 10935 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 10937 }, + { MODRM_SPLITRM, 10939 }, + { MODRM_SPLITRM, 10941 }, + { MODRM_SPLITRM, 10943 }, + { MODRM_SPLITRM, 10945 }, + { MODRM_SPLITRM, 10947 }, + { MODRM_SPLITRM, 10949 }, + { MODRM_SPLITRM, 10951 }, + { MODRM_SPLITRM, 10953 }, + { MODRM_SPLITRM, 10955 }, + { MODRM_SPLITRM, 10957 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { 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MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17429 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17629 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17631 }, + { MODRM_SPLITRM, 17633 }, + { MODRM_SPLITRM, 17635 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17637 }, + { MODRM_SPLITRM, 17639 }, + { MODRM_SPLITRM, 17641 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17643 }, + { MODRM_SPLITRM, 17645 }, + { MODRM_SPLITRM, 17647 }, + { MODRM_SPLITRM, 17449 }, + { MODRM_SPLITRM, 17451 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17649 }, + { MODRM_SPLITRM, 17455 }, + { MODRM_SPLITRM, 17457 }, + { MODRM_SPLITRM, 17459 }, + { MODRM_SPLITRM, 17461 }, + { MODRM_SPLITRM, 17463 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17651 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17653 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17471 }, + { MODRM_SPLITRM, 17473 }, + { MODRM_SPLITRM, 17475 }, + { MODRM_SPLITRM, 17477 }, + { MODRM_SPLITRM, 17479 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17655 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17485 }, + { MODRM_SPLITRM, 17657 }, + { MODRM_SPLITRM, 17489 }, + { MODRM_SPLITRM, 17659 }, + { MODRM_SPLITRM, 17493 }, + { MODRM_SPLITRM, 17661 }, + { MODRM_SPLITRM, 17497 }, + { MODRM_SPLITRM, 17663 }, + { MODRM_SPLITRM, 17665 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17667 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17669 }, + { MODRM_SPLITRM, 17671 }, + { MODRM_SPLITRM, 17673 }, + { MODRM_SPLITRM, 17675 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17677 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17679 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17681 }, + { MODRM_SPLITRM, 17683 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17685 }, + { MODRM_SPLITRM, 17687 }, + { MODRM_SPLITRM, 17689 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17691 }, + { MODRM_SPLITRM, 17693 }, + { MODRM_SPLITRM, 17695 }, + { MODRM_SPLITRM, 17697 }, + { MODRM_SPLITRM, 17699 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17701 }, + { MODRM_SPLITRM, 17703 }, + { MODRM_SPLITRM, 17705 }, + { MODRM_SPLITRM, 17707 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17709 }, + { MODRM_SPLITRM, 17711 }, + { MODRM_SPLITRM, 17713 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17715 }, + { MODRM_SPLITRM, 17717 }, + { MODRM_SPLITRM, 17719 }, + { MODRM_SPLITRM, 17721 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17723 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17725 }, + { MODRM_SPLITRM, 17727 }, + { MODRM_SPLITRM, 17729 }, + { MODRM_SPLITRM, 17731 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17733 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17735 }, + { MODRM_SPLITRM, 17737 }, + { MODRM_SPLITRM, 17739 }, + { MODRM_SPLITRM, 16943 }, + { MODRM_SPLITRM, 17741 }, + { MODRM_SPLITRM, 16947 }, + { MODRM_SPLITRM, 17743 }, + { MODRM_SPLITRM, 16951 }, + { MODRM_SPLITRM, 17745 }, + { MODRM_SPLITRM, 16955 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17747 }, + { MODRM_SPLITRM, 17749 }, + { MODRM_SPLITRM, 17751 }, + { MODRM_SPLITRM, 16963 }, + { MODRM_SPLITRM, 17753 }, + { MODRM_SPLITRM, 16967 }, + { MODRM_SPLITRM, 17755 }, + { MODRM_SPLITRM, 16971 }, + { MODRM_SPLITRM, 17757 }, + { MODRM_SPLITRM, 16975 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17759 }, + { MODRM_SPLITRM, 17761 }, + { MODRM_SPLITRM, 17763 }, + { MODRM_SPLITRM, 17765 }, + { MODRM_SPLITRM, 17767 }, + { MODRM_SPLITRM, 16987 }, + { MODRM_SPLITRM, 17769 }, + { MODRM_SPLITRM, 16991 }, + { MODRM_SPLITRM, 17771 }, + { MODRM_SPLITRM, 16995 }, + { MODRM_SPLITRM, 17773 }, + { MODRM_SPLITRM, 16999 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17775 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17777 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17779 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17781 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, +}; + +static const unsigned char index_x86DisassemblerThreeByte3AOpcodes[] = { + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 0, + 0, + 0, + 0, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 0, + 0, + 15, + 16, + 17, + 18, + 19, + 0, + 0, + 20, + 21, + 0, + 0, + 22, + 23, + 0, + 0, + 0, + 24, + 0, + 0, + 0, + 25, + 0, + 0, + 0, + 26, + 0, + 0, + 0, + 27, + 0, + 0, + 0, + 28, + 0, + 0, + 0, + 29, + 0, + 0, + 0, + 30, + 0, + 0, + 0, + 31, + 0, + 0, + 0, + 32, + 0, + 0, + 0, + 33, + 0, + 0, + 0, + 34, + 0, + 0, + 0, + 35, + 0, + 0, + 0, + 36, + 0, + 0, + 0, + 37, + 0, + 0, + 0, + 38, + 0, + 0, + 0, + 39, + 0, + 0, + 0, + 40, + 0, + 0, + 0, + 41, + 0, + 0, + 0, + 42, + 0, + 0, + 0, + 43, + 0, + 0, + 0, + 44, + 0, + 0, + 0, + 45, + 0, + 0, + 0, + 46, + 0, + 0, + 0, + 47, + 0, + 0, + 0, + 48, + 0, + 0, + 0, + 49, + 0, + 0, + 0, + 50, + 0, + 0, + 0, + 51, + 0, + 0, + 0, + 52, + 0, + 0, + 0, + 53, + 0, + 0, + 0, + 54, + 0, + 0, + 0, + 55, + 0, + 0, + 0, + 56, + 0, + 0, + 0, + 57, + 0, + 0, + 0, + 58, + 0, + 0, + 0, + 59, + 0, + 0, + 0, + 60, + 0, + 0, + 0, + 61, +}; + +static const struct OpcodeDecision x86DisassemblerThreeByte3AOpcodes[] = { + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17783 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17785 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 17783 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { 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+ { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19557 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19559 }, + { MODRM_SPLITRM, 19561 }, + { MODRM_SPLITRM, 19563 }, + { MODRM_SPLITRM, 19565 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19567 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19569 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19571 }, + { MODRM_SPLITRM, 19573 }, + { MODRM_SPLITRM, 19411 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19575 }, + { MODRM_SPLITRM, 19577 }, + { MODRM_SPLITRM, 19579 }, + { MODRM_SPLITRM, 19581 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19583 }, + { MODRM_SPLITRM, 19585 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19587 }, + { MODRM_SPLITRM, 19417 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19589 }, + { MODRM_SPLITRM, 19421 }, + { MODRM_SPLITRM, 19591 }, + { MODRM_SPLITRM, 19425 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19593 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19595 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, + { { + { MODRM_SPLITRM, 19597 }, + { MODRM_SPLITRM, 19599 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19601 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19603 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19605 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19607 }, + { MODRM_SPLITRM, 19609 }, + { MODRM_SPLITRM, 19611 }, + { MODRM_SPLITRM, 19613 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19615 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19617 }, + { MODRM_SPLITRM, 19619 }, + { MODRM_SPLITRM, 19443 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19621 }, + { MODRM_SPLITRM, 19623 }, + { MODRM_SPLITRM, 19625 }, + { MODRM_SPLITRM, 19627 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19629 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19631 }, + { MODRM_SPLITRM, 19447 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19633 }, + { MODRM_SPLITRM, 19451 }, + { MODRM_SPLITRM, 19635 }, + { MODRM_SPLITRM, 19455 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19637 }, + { MODRM_SPLITRM, 19639 }, + { MODRM_SPLITRM, 19641 }, + { MODRM_SPLITRM, 19643 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19645 }, + { MODRM_SPLITRM, 19647 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, +}; + +static const unsigned char index_x86DisassemblerXOP8Opcodes[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 2, + 0, + 0, + 0, + 3, + 0, + 0, + 0, + 4, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +static const struct OpcodeDecision x86DisassemblerXOP8Opcodes[] = { + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { 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MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19707 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, +}; + +static const unsigned char index_x86DisassemblerXOP9Opcodes[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 2, + 0, + 0, + 0, + 3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +static const struct OpcodeDecision x86DisassemblerXOP9Opcodes[] = { + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 19709 }, + { MODRM_SPLITREG, 19725 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 19741 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19757 }, + { MODRM_SPLITRM, 19759 }, + { MODRM_SPLITRM, 19761 }, + { MODRM_SPLITRM, 19763 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19765 }, + { MODRM_SPLITRM, 19767 }, + { MODRM_SPLITRM, 19769 }, + { MODRM_SPLITRM, 19771 }, + { MODRM_SPLITRM, 19773 }, + { MODRM_SPLITRM, 19775 }, + { MODRM_SPLITRM, 19777 }, + { MODRM_SPLITRM, 19779 }, + { MODRM_SPLITRM, 19781 }, + { MODRM_SPLITRM, 19783 }, + { MODRM_SPLITRM, 19785 }, + { MODRM_SPLITRM, 19787 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19789 }, + { MODRM_SPLITRM, 19791 }, + { MODRM_SPLITRM, 19793 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19795 }, + { MODRM_SPLITRM, 19797 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19799 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19801 }, + { MODRM_SPLITRM, 19803 }, + { MODRM_SPLITRM, 19805 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19807 }, + { MODRM_SPLITRM, 19809 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19811 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19813 }, + { MODRM_SPLITRM, 19815 }, + { MODRM_SPLITRM, 19817 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 19819 }, + { MODRM_SPLITREG, 19835 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 19851 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19867 }, + { MODRM_SPLITRM, 19869 }, + { MODRM_SPLITRM, 19871 }, + { MODRM_SPLITRM, 19873 }, + { MODRM_SPLITRM, 19875 }, + { MODRM_SPLITRM, 19877 }, + { MODRM_SPLITRM, 19879 }, + { MODRM_SPLITRM, 19881 }, + { MODRM_SPLITRM, 19883 }, + { MODRM_SPLITRM, 19885 }, + { MODRM_SPLITRM, 19887 }, + { MODRM_SPLITRM, 19889 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19891 }, + { MODRM_SPLITRM, 19893 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, +}; + +static const unsigned char index_x86DisassemblerXOPAOpcodes[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +static const struct OpcodeDecision x86DisassemblerXOPAOpcodes[] = { + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19895 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 19897 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19913 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 19915 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, +}; + +static const unsigned char index_x86Disassembler3DNowOpcodes[] = { + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 0, + 0, + 0, + 0, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 0, + 0, + 15, + 16, + 17, + 18, + 19, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +static const struct OpcodeDecision x86Disassembler3DNowOpcodes[] = { + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19931 }, + { MODRM_SPLITRM, 19933 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19935 }, + { MODRM_SPLITRM, 19937 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19939 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19941 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19943 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19945 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19947 }, + { MODRM_SPLITRM, 19949 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19951 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19953 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19955 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19957 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19959 }, + { MODRM_SPLITRM, 19961 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19963 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19965 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19967 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19969 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19971 }, + { MODRM_SPLITRM, 19973 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19975 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19977 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19931 }, + { MODRM_SPLITRM, 19933 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19935 }, + { MODRM_SPLITRM, 19937 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 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MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19939 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19941 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19943 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19945 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19947 }, + { MODRM_SPLITRM, 19949 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19951 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19953 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19955 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19957 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19959 }, + { MODRM_SPLITRM, 19961 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19963 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19965 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19967 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19969 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19971 }, + { MODRM_SPLITRM, 19973 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19975 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 19977 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, +}; + diff --git a/thirdparty/capstone/arch/X86/X86GenDisassemblerTables_reduce.inc b/thirdparty/capstone/arch/X86/X86GenDisassemblerTables_reduce.inc new file mode 100644 index 0000000..4663fbe --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenDisassemblerTables_reduce.inc @@ -0,0 +1,28047 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* * X86 Disassembler *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +static const struct OperandSpecifier x86OperandSets[][6] = { + { /* 0 */ + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 1 */ + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 2 */ + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 3 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 4 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 5 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 6 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 7 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 8 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 9 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 10 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 11 */ + { ENCODING_ID, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 12 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_ID, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 13 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 14 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_ID, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 15 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 16 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 17 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 18 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 19 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 20 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 21 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 22 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 23 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 24 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 25 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 26 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 27 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 28 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 29 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 30 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_R16 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 31 */ + { ENCODING_RM, TYPE_R16 }, + { ENCODING_REG, TYPE_R16 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 32 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 33 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 34 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 35 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 36 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 37 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 38 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_ID, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 39 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_ID, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 40 */ + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 41 */ + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 42 */ + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 43 */ + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 44 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 45 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 46 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 47 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 48 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_Rv, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 49 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RO, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 50 */ + { ENCODING_RM, TYPE_Rv }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 51 */ + { ENCODING_RM, TYPE_Rv }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 52 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 53 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 54 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 55 */ + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 56 */ + { ENCODING_ID, TYPE_REL }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 57 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 58 */ + { ENCODING_IW, TYPE_REL }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 59 */ + { ENCODING_RM, TYPE_Rv }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 60 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_ID, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 61 */ + { ENCODING_RM, TYPE_R8 }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 62 */ + { ENCODING_REG, TYPE_R8 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 63 */ + { ENCODING_RM, TYPE_R8 }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 64 */ + { ENCODING_REG, TYPE_R8 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 65 */ + { ENCODING_DI, TYPE_DSTIDX }, + { ENCODING_SI, TYPE_SRCIDX }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 66 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 67 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 68 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 69 */ + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 70 */ + { ENCODING_IW, TYPE_IMM }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 71 */ + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 72 */ + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_IW, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 73 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_M }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 74 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 75 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 76 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 77 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 78 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 79 */ + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 80 */ + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 81 */ + { ENCODING_DI, TYPE_DSTIDX }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 82 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 83 */ + { ENCODING_IB, TYPE_REL }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 84 */ + { ENCODING_Iv, TYPE_REL }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 85 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 86 */ + { ENCODING_RM, TYPE_R16 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 87 */ + { ENCODING_SI, TYPE_SRCIDX }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 88 */ + { ENCODING_IW, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 89 */ + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 90 */ + { ENCODING_VVVV, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 91 */ + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 92 */ + { ENCODING_VVVV, TYPE_R64 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 93 */ + { ENCODING_Ia, TYPE_MOFFS }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 94 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_SEGMENTREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 95 */ + { ENCODING_Rv, TYPE_Rv }, + { ENCODING_Iv, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 96 */ + { ENCODING_RM, TYPE_Rv }, + { ENCODING_REG, TYPE_SEGMENTREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 97 */ + { ENCODING_REG, TYPE_SEGMENTREG }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 98 */ + { ENCODING_REG, TYPE_SEGMENTREG }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 99 */ + { ENCODING_REG, TYPE_CONTROLREG }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 100 */ + { ENCODING_REG, TYPE_DEBUGREG }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 101 */ + { ENCODING_RM, TYPE_R32 }, + { ENCODING_REG, TYPE_CONTROLREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 102 */ + { ENCODING_RM, TYPE_R32 }, + { ENCODING_REG, TYPE_DEBUGREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 103 */ + { ENCODING_REG, TYPE_CONTROLREG }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 104 */ + { ENCODING_REG, TYPE_DEBUGREG }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 105 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_CONTROLREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 106 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_DEBUGREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 107 */ + { ENCODING_RO, TYPE_R64 }, + { ENCODING_IO, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 108 */ + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_SEGMENTREG }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 109 */ + { ENCODING_REG, TYPE_SEGMENTREG }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 110 */ + { ENCODING_RB, TYPE_R8 }, + { ENCODING_IB, TYPE_IMM }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 111 */ + { ENCODING_REG, TYPE_R16 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 112 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 113 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 114 */ + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_R16 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 115 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R16 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 116 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 117 */ + { ENCODING_Rv, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 118 */ + { ENCODING_RO, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 119 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 120 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 121 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 122 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 123 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 124 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 125 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 126 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_M }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 127 */ + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 128 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 129 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 130 */ + { ENCODING_RM, TYPE_M }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 131 */ + { ENCODING_DUP, TYPE_DUP1 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_IB, TYPE_UIMM8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 132 */ + { ENCODING_RM, TYPE_R32 }, + { ENCODING_REG, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 133 */ + { ENCODING_REG, TYPE_R32 }, + { ENCODING_RM, TYPE_R32 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 134 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 135 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 136 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 137 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_Rv }, + { ENCODING_RM, TYPE_Rv }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 138 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_R64 }, + { ENCODING_RM, TYPE_R64 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, + { /* 139 */ + { ENCODING_DUP, TYPE_DUP2 }, + { ENCODING_DUP, TYPE_DUP3 }, + { ENCODING_REG, TYPE_R8 }, + { ENCODING_RM, TYPE_R8 }, + { ENCODING_NONE, TYPE_NONE }, + { ENCODING_NONE, TYPE_NONE }, + }, +}; + +static const struct InstructionSpecifier x86DisassemblerInstrSpecifiers[1671] = { + { /* 0 */ + 0, + /* */ + }, + { /* 1 */ + 0, + /* */ + }, + { /* 2 */ + 0, + /* */ + }, + { /* 3 */ + 0, + /* */ + }, + { /* 4 */ + 0, + /* */ + }, + { /* 5 */ + 0, + /* */ + }, + { /* 6 */ + 0, + /* */ + }, + { /* 7 */ + 0, + /* */ + }, + { /* 8 */ + 0, + /* */ + }, + { /* 9 */ + 0, + /* */ + }, + { /* 10 */ + 0, + /* */ + }, + { /* 11 */ + 0, + /* */ + }, + { /* 12 */ + 0, + /* */ + }, + { /* 13 */ + 0, + /* */ + }, + { /* 14 */ + 0, + /* */ + }, + { /* 15 */ + 0, + /* */ + }, + { /* 16 */ + 0, + /* */ + }, + { /* 17 */ + 0, + /* */ + }, + { /* 18 */ + 0, + /* */ + }, + { /* 19 */ + 0, + /* */ + }, + { /* 20 */ + 0, + /* */ + }, + { /* 21 */ + 0, + /* */ + }, + { /* 22 */ + 0, + /* */ + }, + { /* 23 */ + 0, + /* */ + }, + { /* 24 */ + 0, + /* */ + }, + { /* 25 */ + 0, + /* */ + }, + { /* 26 */ + 0, + /* */ + }, + { /* 27 */ + 0, + /* */ + }, + { /* 28 */ + 0, + /* */ + }, + { /* 29 */ + 0, + /* */ + }, + { /* 30 */ + 0, + /* */ + }, + { /* 31 */ + 0, + /* */ + }, + { /* 32 */ + 0, + /* */ + }, + { /* 33 */ + 0, + /* */ + }, + { /* 34 */ + 0, + /* */ + }, + { /* 35 */ + 0, + /* */ + }, + { /* 36 */ + 0, + /* */ + }, + { /* 37 */ + 0, + /* */ + }, + { /* 38 */ + 0, + /* */ + }, + { /* 39 */ + 0, + /* */ + }, + { /* 40 */ + 0, + /* */ + }, + { /* 41 */ + 0, + /* */ + }, + { /* 42 */ + 0, + /* */ + }, + { /* 43 */ + 0, + /* */ + }, + { /* 44 */ + 0, + /* */ + }, + { /* 45 */ + 0, + /* */ + }, + { /* 46 */ + 0, + /* */ + }, + { /* 47 */ + 0, + /* */ + }, + { /* 48 */ + 0, + /* */ + }, + { /* 49 */ + 0, + /* */ + }, + { /* 50 */ + 0, + /* */ + }, + { /* 51 */ + 0, + /* */ + }, + { /* 52 */ + 0, + /* */ + }, + { /* 53 */ + 0, + /* */ + }, + { /* 54 */ + 0, + /* */ + }, + { /* 55 */ + 0, + /* */ + }, + { /* 56 */ + 0, + /* */ + }, + { /* 57 */ + 0, + /* */ + }, + { /* 58 */ + 0, + /* */ + }, + { /* 59 */ + 0, + /* */ + }, + { /* 60 */ + 0, + /* */ + }, + { /* 61 */ + 0, + /* */ + }, + { /* 62 */ + 0, + /* */ + }, + { /* 63 */ + 0, + /* */ + }, + { /* 64 */ + 0, + /* */ + }, + { /* 65 */ + 0, + /* */ + }, + { /* 66 */ + 0, + /* */ + }, + { /* 67 */ + 0, + /* */ + }, + { /* 68 */ + 0, + /* */ + }, + { /* 69 */ + 0, + /* */ + }, + { /* 70 */ + 0, + /* */ + }, + { /* 71 */ + 0, + /* */ + }, + { /* 72 */ + 0, + /* */ + }, + { /* 73 */ + 0, + /* */ + }, + { /* 74 */ + 0, + /* */ + }, + { /* 75 */ + 0, + /* */ + }, + { /* 76 */ + 0, + /* */ + }, + { /* 77 */ + 0, + /* */ + }, + { /* 78 */ + 0, + /* */ + }, + { /* 79 */ + 0, + /* */ + }, + { /* 80 */ + 0, + /* */ + }, + { /* 81 */ + 0, + /* */ + }, + { /* 82 */ + 0, + /* */ + }, + { /* 83 */ + 0, + /* */ + }, + { /* 84 */ + 0, + /* */ + }, + { /* 85 */ + 0, + /* */ + }, + { /* 86 */ + 0, + /* */ + }, + { /* 87 */ + 0, + /* */ + }, + { /* 88 */ + 0, + /* */ + }, + { /* 89 */ + 0, + /* */ + }, + { /* 90 */ + 0, + /* */ + }, + { /* 91 */ + 0, + /* */ + }, + { /* 92 */ + 0, + /* */ + }, + { /* 93 */ + 0, + /* */ + }, + { /* 94 */ + 0, + /* */ + }, + { /* 95 */ + 0, + /* */ + }, + { /* 96 */ + 0, + /* */ + }, + { /* 97 */ + 0, + /* */ + }, + { /* 98 */ + 0, + /* */ + }, + { /* 99 */ + 0, + /* */ + }, + { /* 100 */ + 0, + /* */ + }, + { /* 101 */ + 0, + /* */ + }, + { /* 102 */ + 0, + /* */ + }, + { /* 103 */ + 0, + /* */ + }, + { /* 104 */ + 0, + /* */ + }, + { /* 105 */ + 0, + /* */ + }, + { /* 106 */ + 0, + /* */ + }, + { /* 107 */ + 0, + /* */ + }, + { /* 108 */ + 0, + /* */ + }, + { /* 109 */ + 0, + /* */ + }, + { /* 110 */ + 0, + /* */ + }, + { /* 111 */ + 0, + /* */ + }, + { /* 112 */ + 0, + /* */ + }, + { /* 113 */ + 0, + /* */ + }, + { /* 114 */ + 0, + /* */ + }, + { /* 115 */ + 0, + /* */ + }, + { /* 116 */ + 0, + /* */ + }, + { /* 117 */ + 0, + /* */ + }, + { /* 118 */ + 0, + /* */ + }, + { /* 119 */ + 0, + /* */ + }, + { /* 120 */ + 0, + /* */ + }, + { /* 121 */ + 0, + /* */ + }, + { /* 122 */ + 0, + /* */ + }, + { /* 123 */ + 0, + /* */ + }, + { /* 124 */ + 0, + /* */ + }, + { /* 125 */ + 0, + /* */ + }, + { /* 126 */ + 0, + /* AAA */ + }, + { /* 127 */ + 1, + /* AAD8i8 */ + }, + { /* 128 */ + 1, + /* AAM8i8 */ + }, + { /* 129 */ + 0, + /* AAS */ + }, + { /* 130 */ + 2, + /* ADC16i16 */ + }, + { /* 131 */ + 3, + /* ADC16mi */ + }, + { /* 132 */ + 4, + /* ADC16mi8 */ + }, + { /* 133 */ + 5, + /* ADC16mr */ + }, + { /* 134 */ + 6, + /* ADC16ri */ + }, + { /* 135 */ + 7, + /* ADC16ri8 */ + }, + { /* 136 */ + 8, + /* ADC16rm */ + }, + { /* 137 */ + 9, + /* ADC16rr */ + }, + { /* 138 */ + 10, + /* ADC16rr_REV */ + }, + { /* 139 */ + 2, + /* ADC32i32 */ + }, + { /* 140 */ + 3, + /* ADC32mi */ + }, + { /* 141 */ + 4, + /* ADC32mi8 */ + }, + { /* 142 */ + 5, + /* ADC32mr */ + }, + { /* 143 */ + 6, + /* ADC32ri */ + }, + { /* 144 */ + 7, + /* ADC32ri8 */ + }, + { /* 145 */ + 8, + /* ADC32rm */ + }, + { /* 146 */ + 9, + /* ADC32rr */ + }, + { /* 147 */ + 10, + /* ADC32rr_REV */ + }, + { /* 148 */ + 11, + /* ADC64i32 */ + }, + { /* 149 */ + 12, + /* ADC64mi32 */ + }, + { /* 150 */ + 4, + /* ADC64mi8 */ + }, + { /* 151 */ + 13, + /* ADC64mr */ + }, + { /* 152 */ + 14, + /* ADC64ri32 */ + }, + { /* 153 */ + 15, + /* ADC64ri8 */ + }, + { /* 154 */ + 16, + /* ADC64rm */ + }, + { /* 155 */ + 17, + /* ADC64rr */ + }, + { /* 156 */ + 18, + /* ADC64rr_REV */ + }, + { /* 157 */ + 1, + /* ADC8i8 */ + }, + { /* 158 */ + 4, + /* ADC8mi */ + }, + { /* 159 */ + 4, + /* ADC8mi8 */ + }, + { /* 160 */ + 19, + /* ADC8mr */ + }, + { /* 161 */ + 20, + /* ADC8ri */ + }, + { /* 162 */ + 20, + /* ADC8ri8 */ + }, + { /* 163 */ + 21, + /* ADC8rm */ + }, + { /* 164 */ + 22, + /* ADC8rr */ + }, + { /* 165 */ + 23, + /* ADC8rr_REV */ + }, + { /* 166 */ + 24, + /* ADCX32rm */ + }, + { /* 167 */ + 25, + /* ADCX32rr */ + }, + { /* 168 */ + 16, + /* ADCX64rm */ + }, + { /* 169 */ + 18, + /* ADCX64rr */ + }, + { /* 170 */ + 2, + /* ADD16i16 */ + }, + { /* 171 */ + 3, + /* ADD16mi */ + }, + { /* 172 */ + 4, + /* ADD16mi8 */ + }, + { /* 173 */ + 5, + /* ADD16mr */ + }, + { /* 174 */ + 6, + /* ADD16ri */ + }, + { /* 175 */ + 7, + /* ADD16ri8 */ + }, + { /* 176 */ + 8, + /* ADD16rm */ + }, + { /* 177 */ + 9, + /* ADD16rr */ + }, + { /* 178 */ + 10, + /* ADD16rr_REV */ + }, + { /* 179 */ + 2, + /* ADD32i32 */ + }, + { /* 180 */ + 3, + /* ADD32mi */ + }, + { /* 181 */ + 4, + /* ADD32mi8 */ + }, + { /* 182 */ + 5, + /* ADD32mr */ + }, + { /* 183 */ + 6, + /* ADD32ri */ + }, + { /* 184 */ + 7, + /* ADD32ri8 */ + }, + { /* 185 */ + 8, + /* ADD32rm */ + }, + { /* 186 */ + 9, + /* ADD32rr */ + }, + { /* 187 */ + 10, + /* ADD32rr_REV */ + }, + { /* 188 */ + 11, + /* ADD64i32 */ + }, + { /* 189 */ + 12, + /* ADD64mi32 */ + }, + { /* 190 */ + 4, + /* ADD64mi8 */ + }, + { /* 191 */ + 13, + /* ADD64mr */ + }, + { /* 192 */ + 14, + /* ADD64ri32 */ + }, + { /* 193 */ + 15, + /* ADD64ri8 */ + }, + { /* 194 */ + 16, + /* ADD64rm */ + }, + { /* 195 */ + 17, + /* ADD64rr */ + }, + { /* 196 */ + 18, + /* ADD64rr_REV */ + }, + { /* 197 */ + 1, + /* ADD8i8 */ + }, + { /* 198 */ + 4, + /* ADD8mi */ + }, + { /* 199 */ + 4, + /* ADD8mi8 */ + }, + { /* 200 */ + 19, + /* ADD8mr */ + }, + { /* 201 */ + 20, + /* ADD8ri */ + }, + { /* 202 */ + 20, + /* ADD8ri8 */ + }, + { /* 203 */ + 21, + /* ADD8rm */ + }, + { /* 204 */ + 22, + /* ADD8rr */ + }, + { /* 205 */ + 23, + /* ADD8rr_REV */ + }, + { /* 206 */ + 24, + /* ADOX32rm */ + }, + { /* 207 */ + 25, + /* ADOX32rr */ + }, + { /* 208 */ + 16, + /* ADOX64rm */ + }, + { /* 209 */ + 18, + /* ADOX64rr */ + }, + { /* 210 */ + 2, + /* AND16i16 */ + }, + { /* 211 */ + 3, + /* AND16mi */ + }, + { /* 212 */ + 4, + /* AND16mi8 */ + }, + { /* 213 */ + 5, + /* AND16mr */ + }, + { /* 214 */ + 6, + /* AND16ri */ + }, + { /* 215 */ + 7, + /* AND16ri8 */ + }, + { /* 216 */ + 8, + /* AND16rm */ + }, + { /* 217 */ + 9, + /* AND16rr */ + }, + { /* 218 */ + 10, + /* AND16rr_REV */ + }, + { /* 219 */ + 2, + /* AND32i32 */ + }, + { /* 220 */ + 3, + /* AND32mi */ + }, + { /* 221 */ + 4, + /* AND32mi8 */ + }, + { /* 222 */ + 5, + /* AND32mr */ + }, + { /* 223 */ + 6, + /* AND32ri */ + }, + { /* 224 */ + 7, + /* AND32ri8 */ + }, + { /* 225 */ + 8, + /* AND32rm */ + }, + { /* 226 */ + 9, + /* AND32rr */ + }, + { /* 227 */ + 10, + /* AND32rr_REV */ + }, + { /* 228 */ + 11, + /* AND64i32 */ + }, + { /* 229 */ + 12, + /* AND64mi32 */ + }, + { /* 230 */ + 4, + /* AND64mi8 */ + }, + { /* 231 */ + 13, + /* AND64mr */ + }, + { /* 232 */ + 14, + /* AND64ri32 */ + }, + { /* 233 */ + 15, + /* AND64ri8 */ + }, + { /* 234 */ + 16, + /* AND64rm */ + }, + { /* 235 */ + 17, + /* AND64rr */ + }, + { /* 236 */ + 18, + /* AND64rr_REV */ + }, + { /* 237 */ + 1, + /* AND8i8 */ + }, + { /* 238 */ + 4, + /* AND8mi */ + }, + { /* 239 */ + 4, + /* AND8mi8 */ + }, + { /* 240 */ + 19, + /* AND8mr */ + }, + { /* 241 */ + 20, + /* AND8ri */ + }, + { /* 242 */ + 20, + /* AND8ri8 */ + }, + { /* 243 */ + 21, + /* AND8rm */ + }, + { /* 244 */ + 22, + /* AND8rr */ + }, + { /* 245 */ + 23, + /* AND8rr_REV */ + }, + { /* 246 */ + 26, + /* ANDN32rm */ + }, + { /* 247 */ + 27, + /* ANDN32rr */ + }, + { /* 248 */ + 28, + /* ANDN64rm */ + }, + { /* 249 */ + 29, + /* ANDN64rr */ + }, + { /* 250 */ + 30, + /* ARPL16mr */ + }, + { /* 251 */ + 31, + /* ARPL16rr */ + }, + { /* 252 */ + 32, + /* BEXTR32rm */ + }, + { /* 253 */ + 33, + /* BEXTR32rr */ + }, + { /* 254 */ + 34, + /* BEXTR64rm */ + }, + { /* 255 */ + 35, + /* BEXTR64rr */ + }, + { /* 256 */ + 36, + /* BEXTRI32mi */ + }, + { /* 257 */ + 37, + /* BEXTRI32ri */ + }, + { /* 258 */ + 38, + /* BEXTRI64mi */ + }, + { /* 259 */ + 39, + /* BEXTRI64ri */ + }, + { /* 260 */ + 40, + /* BLCFILL32rm */ + }, + { /* 261 */ + 41, + /* BLCFILL32rr */ + }, + { /* 262 */ + 42, + /* BLCFILL64rm */ + }, + { /* 263 */ + 43, + /* BLCFILL64rr */ + }, + { /* 264 */ + 40, + /* BLCI32rm */ + }, + { /* 265 */ + 41, + /* BLCI32rr */ + }, + { /* 266 */ + 42, + /* BLCI64rm */ + }, + { /* 267 */ + 43, + /* BLCI64rr */ + }, + { /* 268 */ + 40, + /* BLCIC32rm */ + }, + { /* 269 */ + 41, + /* BLCIC32rr */ + }, + { /* 270 */ + 42, + /* BLCIC64rm */ + }, + { /* 271 */ + 43, + /* BLCIC64rr */ + }, + { /* 272 */ + 40, + /* BLCMSK32rm */ + }, + { /* 273 */ + 41, + /* BLCMSK32rr */ + }, + { /* 274 */ + 42, + /* BLCMSK64rm */ + }, + { /* 275 */ + 43, + /* BLCMSK64rr */ + }, + { /* 276 */ + 40, + /* BLCS32rm */ + }, + { /* 277 */ + 41, + /* BLCS32rr */ + }, + { /* 278 */ + 42, + /* BLCS64rm */ + }, + { /* 279 */ + 43, + /* BLCS64rr */ + }, + { /* 280 */ + 40, + /* BLSFILL32rm */ + }, + { /* 281 */ + 41, + /* BLSFILL32rr */ + }, + { /* 282 */ + 42, + /* BLSFILL64rm */ + }, + { /* 283 */ + 43, + /* BLSFILL64rr */ + }, + { /* 284 */ + 40, + /* BLSI32rm */ + }, + { /* 285 */ + 41, + /* BLSI32rr */ + }, + { /* 286 */ + 42, + /* BLSI64rm */ + }, + { /* 287 */ + 43, + /* BLSI64rr */ + }, + { /* 288 */ + 40, + /* BLSIC32rm */ + }, + { /* 289 */ + 41, + /* BLSIC32rr */ + }, + { /* 290 */ + 42, + /* BLSIC64rm */ + }, + { /* 291 */ + 43, + /* BLSIC64rr */ + }, + { /* 292 */ + 40, + /* BLSMSK32rm */ + }, + { /* 293 */ + 41, + /* BLSMSK32rr */ + }, + { /* 294 */ + 42, + /* BLSMSK64rm */ + }, + { /* 295 */ + 43, + /* BLSMSK64rr */ + }, + { /* 296 */ + 40, + /* BLSR32rm */ + }, + { /* 297 */ + 41, + /* BLSR32rr */ + }, + { /* 298 */ + 42, + /* BLSR64rm */ + }, + { /* 299 */ + 43, + /* BLSR64rr */ + }, + { /* 300 */ + 44, + /* BOUNDS16rm */ + }, + { /* 301 */ + 44, + /* BOUNDS32rm */ + }, + { /* 302 */ + 44, + /* BSF16rm */ + }, + { /* 303 */ + 45, + /* BSF16rr */ + }, + { /* 304 */ + 44, + /* BSF32rm */ + }, + { /* 305 */ + 45, + /* BSF32rr */ + }, + { /* 306 */ + 46, + /* BSF64rm */ + }, + { /* 307 */ + 47, + /* BSF64rr */ + }, + { /* 308 */ + 44, + /* BSR16rm */ + }, + { /* 309 */ + 45, + /* BSR16rr */ + }, + { /* 310 */ + 44, + /* BSR32rm */ + }, + { /* 311 */ + 45, + /* BSR32rr */ + }, + { /* 312 */ + 46, + /* BSR64rm */ + }, + { /* 313 */ + 47, + /* BSR64rr */ + }, + { /* 314 */ + 48, + /* BSWAP16r_BAD */ + }, + { /* 315 */ + 48, + /* BSWAP32r */ + }, + { /* 316 */ + 49, + /* BSWAP64r */ + }, + { /* 317 */ + 4, + /* BT16mi8 */ + }, + { /* 318 */ + 5, + /* BT16mr */ + }, + { /* 319 */ + 50, + /* BT16ri8 */ + }, + { /* 320 */ + 51, + /* BT16rr */ + }, + { /* 321 */ + 4, + /* BT32mi8 */ + }, + { /* 322 */ + 5, + /* BT32mr */ + }, + { /* 323 */ + 50, + /* BT32ri8 */ + }, + { /* 324 */ + 51, + /* BT32rr */ + }, + { /* 325 */ + 4, + /* BT64mi8 */ + }, + { /* 326 */ + 13, + /* BT64mr */ + }, + { /* 327 */ + 52, + /* BT64ri8 */ + }, + { /* 328 */ + 53, + /* BT64rr */ + }, + { /* 329 */ + 4, + /* BTC16mi8 */ + }, + { /* 330 */ + 5, + /* BTC16mr */ + }, + { /* 331 */ + 7, + /* BTC16ri8 */ + }, + { /* 332 */ + 9, + /* BTC16rr */ + }, + { /* 333 */ + 4, + /* BTC32mi8 */ + }, + { /* 334 */ + 5, + /* BTC32mr */ + }, + { /* 335 */ + 7, + /* BTC32ri8 */ + }, + { /* 336 */ + 9, + /* BTC32rr */ + }, + { /* 337 */ + 4, + /* BTC64mi8 */ + }, + { /* 338 */ + 13, + /* BTC64mr */ + }, + { /* 339 */ + 15, + /* BTC64ri8 */ + }, + { /* 340 */ + 17, + /* BTC64rr */ + }, + { /* 341 */ + 4, + /* BTR16mi8 */ + }, + { /* 342 */ + 5, + /* BTR16mr */ + }, + { /* 343 */ + 7, + /* BTR16ri8 */ + }, + { /* 344 */ + 9, + /* BTR16rr */ + }, + { /* 345 */ + 4, + /* BTR32mi8 */ + }, + { /* 346 */ + 5, + /* BTR32mr */ + }, + { /* 347 */ + 7, + /* BTR32ri8 */ + }, + { /* 348 */ + 9, + /* BTR32rr */ + }, + { /* 349 */ + 4, + /* BTR64mi8 */ + }, + { /* 350 */ + 13, + /* BTR64mr */ + }, + { /* 351 */ + 15, + /* BTR64ri8 */ + }, + { /* 352 */ + 17, + /* BTR64rr */ + }, + { /* 353 */ + 4, + /* BTS16mi8 */ + }, + { /* 354 */ + 5, + /* BTS16mr */ + }, + { /* 355 */ + 7, + /* BTS16ri8 */ + }, + { /* 356 */ + 9, + /* BTS16rr */ + }, + { /* 357 */ + 4, + /* BTS32mi8 */ + }, + { /* 358 */ + 5, + /* BTS32mr */ + }, + { /* 359 */ + 7, + /* BTS32ri8 */ + }, + { /* 360 */ + 9, + /* BTS32rr */ + }, + { /* 361 */ + 4, + /* BTS64mi8 */ + }, + { /* 362 */ + 13, + /* BTS64mr */ + }, + { /* 363 */ + 15, + /* BTS64ri8 */ + }, + { /* 364 */ + 17, + /* BTS64rr */ + }, + { /* 365 */ + 32, + /* BZHI32rm */ + }, + { /* 366 */ + 33, + /* BZHI32rr */ + }, + { /* 367 */ + 34, + /* BZHI64rm */ + }, + { /* 368 */ + 35, + /* BZHI64rr */ + }, + { /* 369 */ + 54, + /* CALL16m */ + }, + { /* 370 */ + 0, + /* */ + }, + { /* 371 */ + 55, + /* CALL16r */ + }, + { /* 372 */ + 0, + /* */ + }, + { /* 373 */ + 54, + /* CALL32m */ + }, + { /* 374 */ + 0, + /* */ + }, + { /* 375 */ + 55, + /* CALL32r */ + }, + { /* 376 */ + 0, + /* */ + }, + { /* 377 */ + 54, + /* CALL64m */ + }, + { /* 378 */ + 0, + /* */ + }, + { /* 379 */ + 56, + /* CALL64pcrel32 */ + }, + { /* 380 */ + 57, + /* CALL64r */ + }, + { /* 381 */ + 0, + /* */ + }, + { /* 382 */ + 58, + /* CALLpcrel16 */ + }, + { /* 383 */ + 56, + /* CALLpcrel32 */ + }, + { /* 384 */ + 0, + /* CBW */ + }, + { /* 385 */ + 0, + /* CDQ */ + }, + { /* 386 */ + 0, + /* CDQE */ + }, + { /* 387 */ + 0, + /* CLAC */ + }, + { /* 388 */ + 0, + /* CLC */ + }, + { /* 389 */ + 0, + /* CLD */ + }, + { /* 390 */ + 54, + /* CLDEMOTE */ + }, + { /* 391 */ + 54, + /* CLFLUSHOPT */ + }, + { /* 392 */ + 0, + /* CLGI */ + }, + { /* 393 */ + 0, + /* CLI */ + }, + { /* 394 */ + 54, + /* CLRSSBSY */ + }, + { /* 395 */ + 0, + /* CLTS */ + }, + { /* 396 */ + 54, + /* CLWB */ + }, + { /* 397 */ + 0, + /* CLZEROr */ + }, + { /* 398 */ + 0, + /* CMC */ + }, + { /* 399 */ + 8, + /* CMOVA16rm */ + }, + { /* 400 */ + 10, + /* CMOVA16rr */ + }, + { /* 401 */ + 8, + /* CMOVA32rm */ + }, + { /* 402 */ + 10, + /* CMOVA32rr */ + }, + { /* 403 */ + 16, + /* CMOVA64rm */ + }, + { /* 404 */ + 18, + /* CMOVA64rr */ + }, + { /* 405 */ + 8, + /* CMOVAE16rm */ + }, + { /* 406 */ + 10, + /* CMOVAE16rr */ + }, + { /* 407 */ + 8, + /* CMOVAE32rm */ + }, + { /* 408 */ + 10, + /* CMOVAE32rr */ + }, + { /* 409 */ + 16, + /* CMOVAE64rm */ + }, + { /* 410 */ + 18, + /* CMOVAE64rr */ + }, + { /* 411 */ + 8, + /* CMOVB16rm */ + }, + { /* 412 */ + 10, + /* CMOVB16rr */ + }, + { /* 413 */ + 8, + /* CMOVB32rm */ + }, + { /* 414 */ + 10, + /* CMOVB32rr */ + }, + { /* 415 */ + 16, + /* CMOVB64rm */ + }, + { /* 416 */ + 18, + /* CMOVB64rr */ + }, + { /* 417 */ + 8, + /* CMOVBE16rm */ + }, + { /* 418 */ + 10, + /* CMOVBE16rr */ + }, + { /* 419 */ + 8, + /* CMOVBE32rm */ + }, + { /* 420 */ + 10, + /* CMOVBE32rr */ + }, + { /* 421 */ + 16, + /* CMOVBE64rm */ + }, + { /* 422 */ + 18, + /* CMOVBE64rr */ + }, + { /* 423 */ + 8, + /* CMOVE16rm */ + }, + { /* 424 */ + 10, + /* CMOVE16rr */ + }, + { /* 425 */ + 8, + /* CMOVE32rm */ + }, + { /* 426 */ + 10, + /* CMOVE32rr */ + }, + { /* 427 */ + 16, + /* CMOVE64rm */ + }, + { /* 428 */ + 18, + /* CMOVE64rr */ + }, + { /* 429 */ + 8, + /* CMOVG16rm */ + }, + { /* 430 */ + 10, + /* CMOVG16rr */ + }, + { /* 431 */ + 8, + /* CMOVG32rm */ + }, + { /* 432 */ + 10, + /* CMOVG32rr */ + }, + { /* 433 */ + 16, + /* CMOVG64rm */ + }, + { /* 434 */ + 18, + /* CMOVG64rr */ + }, + { /* 435 */ + 8, + /* CMOVGE16rm */ + }, + { /* 436 */ + 10, + /* CMOVGE16rr */ + }, + { /* 437 */ + 8, + /* CMOVGE32rm */ + }, + { /* 438 */ + 10, + /* CMOVGE32rr */ + }, + { /* 439 */ + 16, + /* CMOVGE64rm */ + }, + { /* 440 */ + 18, + /* CMOVGE64rr */ + }, + { /* 441 */ + 8, + /* CMOVL16rm */ + }, + { /* 442 */ + 10, + /* CMOVL16rr */ + }, + { /* 443 */ + 8, + /* CMOVL32rm */ + }, + { /* 444 */ + 10, + /* CMOVL32rr */ + }, + { /* 445 */ + 16, + /* CMOVL64rm */ + }, + { /* 446 */ + 18, + /* CMOVL64rr */ + }, + { /* 447 */ + 8, + /* CMOVLE16rm */ + }, + { /* 448 */ + 10, + /* CMOVLE16rr */ + }, + { /* 449 */ + 8, + /* CMOVLE32rm */ + }, + { /* 450 */ + 10, + /* CMOVLE32rr */ + }, + { /* 451 */ + 16, + /* CMOVLE64rm */ + }, + { /* 452 */ + 18, + /* CMOVLE64rr */ + }, + { /* 453 */ + 8, + /* CMOVNE16rm */ + }, + { /* 454 */ + 10, + /* CMOVNE16rr */ + }, + { /* 455 */ + 8, + /* CMOVNE32rm */ + }, + { /* 456 */ + 10, + /* CMOVNE32rr */ + }, + { /* 457 */ + 16, + /* CMOVNE64rm */ + }, + { /* 458 */ + 18, + /* CMOVNE64rr */ + }, + { /* 459 */ + 8, + /* CMOVNO16rm */ + }, + { /* 460 */ + 10, + /* CMOVNO16rr */ + }, + { /* 461 */ + 8, + /* CMOVNO32rm */ + }, + { /* 462 */ + 10, + /* CMOVNO32rr */ + }, + { /* 463 */ + 16, + /* CMOVNO64rm */ + }, + { /* 464 */ + 18, + /* CMOVNO64rr */ + }, + { /* 465 */ + 8, + /* CMOVNP16rm */ + }, + { /* 466 */ + 10, + /* CMOVNP16rr */ + }, + { /* 467 */ + 8, + /* CMOVNP32rm */ + }, + { /* 468 */ + 10, + /* CMOVNP32rr */ + }, + { /* 469 */ + 16, + /* CMOVNP64rm */ + }, + { /* 470 */ + 18, + /* CMOVNP64rr */ + }, + { /* 471 */ + 8, + /* CMOVNS16rm */ + }, + { /* 472 */ + 10, + /* CMOVNS16rr */ + }, + { /* 473 */ + 8, + /* CMOVNS32rm */ + }, + { /* 474 */ + 10, + /* CMOVNS32rr */ + }, + { /* 475 */ + 16, + /* CMOVNS64rm */ + }, + { /* 476 */ + 18, + /* CMOVNS64rr */ + }, + { /* 477 */ + 8, + /* CMOVO16rm */ + }, + { /* 478 */ + 10, + /* CMOVO16rr */ + }, + { /* 479 */ + 8, + /* CMOVO32rm */ + }, + { /* 480 */ + 10, + /* CMOVO32rr */ + }, + { /* 481 */ + 16, + /* CMOVO64rm */ + }, + { /* 482 */ + 18, + /* CMOVO64rr */ + }, + { /* 483 */ + 8, + /* CMOVP16rm */ + }, + { /* 484 */ + 10, + /* CMOVP16rr */ + }, + { /* 485 */ + 8, + /* CMOVP32rm */ + }, + { /* 486 */ + 10, + /* CMOVP32rr */ + }, + { /* 487 */ + 16, + /* CMOVP64rm */ + }, + { /* 488 */ + 18, + /* CMOVP64rr */ + }, + { /* 489 */ + 8, + /* CMOVS16rm */ + }, + { /* 490 */ + 10, + /* CMOVS16rr */ + }, + { /* 491 */ + 8, + /* CMOVS32rm */ + }, + { /* 492 */ + 10, + /* CMOVS32rr */ + }, + { /* 493 */ + 16, + /* CMOVS64rm */ + }, + { /* 494 */ + 18, + /* CMOVS64rr */ + }, + { /* 495 */ + 2, + /* CMP16i16 */ + }, + { /* 496 */ + 3, + /* CMP16mi */ + }, + { /* 497 */ + 4, + /* CMP16mi8 */ + }, + { /* 498 */ + 5, + /* CMP16mr */ + }, + { /* 499 */ + 59, + /* CMP16ri */ + }, + { /* 500 */ + 50, + /* CMP16ri8 */ + }, + { /* 501 */ + 44, + /* CMP16rm */ + }, + { /* 502 */ + 51, + /* CMP16rr */ + }, + { /* 503 */ + 45, + /* CMP16rr_REV */ + }, + { /* 504 */ + 2, + /* CMP32i32 */ + }, + { /* 505 */ + 3, + /* CMP32mi */ + }, + { /* 506 */ + 4, + /* CMP32mi8 */ + }, + { /* 507 */ + 5, + /* CMP32mr */ + }, + { /* 508 */ + 59, + /* CMP32ri */ + }, + { /* 509 */ + 50, + /* CMP32ri8 */ + }, + { /* 510 */ + 44, + /* CMP32rm */ + }, + { /* 511 */ + 51, + /* CMP32rr */ + }, + { /* 512 */ + 45, + /* CMP32rr_REV */ + }, + { /* 513 */ + 11, + /* CMP64i32 */ + }, + { /* 514 */ + 12, + /* CMP64mi32 */ + }, + { /* 515 */ + 4, + /* CMP64mi8 */ + }, + { /* 516 */ + 13, + /* CMP64mr */ + }, + { /* 517 */ + 60, + /* CMP64ri32 */ + }, + { /* 518 */ + 52, + /* CMP64ri8 */ + }, + { /* 519 */ + 46, + /* CMP64rm */ + }, + { /* 520 */ + 53, + /* CMP64rr */ + }, + { /* 521 */ + 47, + /* CMP64rr_REV */ + }, + { /* 522 */ + 1, + /* CMP8i8 */ + }, + { /* 523 */ + 4, + /* CMP8mi */ + }, + { /* 524 */ + 4, + /* CMP8mi8 */ + }, + { /* 525 */ + 19, + /* CMP8mr */ + }, + { /* 526 */ + 61, + /* CMP8ri */ + }, + { /* 527 */ + 61, + /* CMP8ri8 */ + }, + { /* 528 */ + 62, + /* CMP8rm */ + }, + { /* 529 */ + 63, + /* CMP8rr */ + }, + { /* 530 */ + 64, + /* CMP8rr_REV */ + }, + { /* 531 */ + 65, + /* CMPSB */ + }, + { /* 532 */ + 65, + /* CMPSL */ + }, + { /* 533 */ + 65, + /* CMPSQ */ + }, + { /* 534 */ + 65, + /* CMPSW */ + }, + { /* 535 */ + 54, + /* CMPXCHG16B */ + }, + { /* 536 */ + 5, + /* CMPXCHG16rm */ + }, + { /* 537 */ + 51, + /* CMPXCHG16rr */ + }, + { /* 538 */ + 5, + /* CMPXCHG32rm */ + }, + { /* 539 */ + 51, + /* CMPXCHG32rr */ + }, + { /* 540 */ + 13, + /* CMPXCHG64rm */ + }, + { /* 541 */ + 53, + /* CMPXCHG64rr */ + }, + { /* 542 */ + 54, + /* CMPXCHG8B */ + }, + { /* 543 */ + 19, + /* CMPXCHG8rm */ + }, + { /* 544 */ + 63, + /* CMPXCHG8rr */ + }, + { /* 545 */ + 0, + /* CPUID */ + }, + { /* 546 */ + 0, + /* CQO */ + }, + { /* 547 */ + 0, + /* CWD */ + }, + { /* 548 */ + 0, + /* CWDE */ + }, + { /* 549 */ + 0, + /* DAA */ + }, + { /* 550 */ + 0, + /* DAS */ + }, + { /* 551 */ + 0, + /* DATA16_PREFIX */ + }, + { /* 552 */ + 54, + /* DEC16m */ + }, + { /* 553 */ + 66, + /* DEC16r */ + }, + { /* 554 */ + 48, + /* DEC16r_alt */ + }, + { /* 555 */ + 54, + /* DEC32m */ + }, + { /* 556 */ + 66, + /* DEC32r */ + }, + { /* 557 */ + 48, + /* DEC32r_alt */ + }, + { /* 558 */ + 54, + /* DEC64m */ + }, + { /* 559 */ + 67, + /* DEC64r */ + }, + { /* 560 */ + 54, + /* DEC8m */ + }, + { /* 561 */ + 68, + /* DEC8r */ + }, + { /* 562 */ + 54, + /* DIV16m */ + }, + { /* 563 */ + 55, + /* DIV16r */ + }, + { /* 564 */ + 54, + /* DIV32m */ + }, + { /* 565 */ + 55, + /* DIV32r */ + }, + { /* 566 */ + 54, + /* DIV64m */ + }, + { /* 567 */ + 57, + /* DIV64r */ + }, + { /* 568 */ + 54, + /* DIV8m */ + }, + { /* 569 */ + 69, + /* DIV8r */ + }, + { /* 570 */ + 0, + /* ENDBR32 */ + }, + { /* 571 */ + 0, + /* ENDBR64 */ + }, + { /* 572 */ + 70, + /* ENTER */ + }, + { /* 573 */ + 71, + /* FARCALL16i */ + }, + { /* 574 */ + 54, + /* FARCALL16m */ + }, + { /* 575 */ + 72, + /* FARCALL32i */ + }, + { /* 576 */ + 54, + /* FARCALL32m */ + }, + { /* 577 */ + 54, + /* FARCALL64 */ + }, + { /* 578 */ + 71, + /* FARJMP16i */ + }, + { /* 579 */ + 54, + /* FARJMP16m */ + }, + { /* 580 */ + 72, + /* FARJMP32i */ + }, + { /* 581 */ + 54, + /* FARJMP32m */ + }, + { /* 582 */ + 54, + /* FARJMP64 */ + }, + { /* 583 */ + 0, + /* FSETPM */ + }, + { /* 584 */ + 0, + /* GETSEC */ + }, + { /* 585 */ + 0, + /* HLT */ + }, + { /* 586 */ + 54, + /* IDIV16m */ + }, + { /* 587 */ + 55, + /* IDIV16r */ + }, + { /* 588 */ + 54, + /* IDIV32m */ + }, + { /* 589 */ + 55, + /* IDIV32r */ + }, + { /* 590 */ + 54, + /* IDIV64m */ + }, + { /* 591 */ + 57, + /* IDIV64r */ + }, + { /* 592 */ + 54, + /* IDIV8m */ + }, + { /* 593 */ + 69, + /* IDIV8r */ + }, + { /* 594 */ + 54, + /* IMUL16m */ + }, + { /* 595 */ + 55, + /* IMUL16r */ + }, + { /* 596 */ + 8, + /* IMUL16rm */ + }, + { /* 597 */ + 73, + /* IMUL16rmi */ + }, + { /* 598 */ + 74, + /* IMUL16rmi8 */ + }, + { /* 599 */ + 10, + /* IMUL16rr */ + }, + { /* 600 */ + 75, + /* IMUL16rri */ + }, + { /* 601 */ + 76, + /* IMUL16rri8 */ + }, + { /* 602 */ + 54, + /* IMUL32m */ + }, + { /* 603 */ + 55, + /* IMUL32r */ + }, + { /* 604 */ + 8, + /* IMUL32rm */ + }, + { /* 605 */ + 73, + /* IMUL32rmi */ + }, + { /* 606 */ + 74, + /* IMUL32rmi8 */ + }, + { /* 607 */ + 10, + /* IMUL32rr */ + }, + { /* 608 */ + 75, + /* IMUL32rri */ + }, + { /* 609 */ + 76, + /* IMUL32rri8 */ + }, + { /* 610 */ + 54, + /* IMUL64m */ + }, + { /* 611 */ + 57, + /* IMUL64r */ + }, + { /* 612 */ + 16, + /* IMUL64rm */ + }, + { /* 613 */ + 38, + /* IMUL64rmi32 */ + }, + { /* 614 */ + 77, + /* IMUL64rmi8 */ + }, + { /* 615 */ + 18, + /* IMUL64rr */ + }, + { /* 616 */ + 39, + /* IMUL64rri32 */ + }, + { /* 617 */ + 78, + /* IMUL64rri8 */ + }, + { /* 618 */ + 54, + /* IMUL8m */ + }, + { /* 619 */ + 69, + /* IMUL8r */ + }, + { /* 620 */ + 79, + /* IN16ri */ + }, + { /* 621 */ + 0, + /* IN16rr */ + }, + { /* 622 */ + 79, + /* IN32ri */ + }, + { /* 623 */ + 0, + /* IN32rr */ + }, + { /* 624 */ + 79, + /* IN8ri */ + }, + { /* 625 */ + 0, + /* IN8rr */ + }, + { /* 626 */ + 54, + /* INC16m */ + }, + { /* 627 */ + 66, + /* INC16r */ + }, + { /* 628 */ + 48, + /* INC16r_alt */ + }, + { /* 629 */ + 54, + /* INC32m */ + }, + { /* 630 */ + 66, + /* INC32r */ + }, + { /* 631 */ + 48, + /* INC32r_alt */ + }, + { /* 632 */ + 54, + /* INC64m */ + }, + { /* 633 */ + 67, + /* INC64r */ + }, + { /* 634 */ + 54, + /* INC8m */ + }, + { /* 635 */ + 68, + /* INC8r */ + }, + { /* 636 */ + 80, + /* INCSSPD */ + }, + { /* 637 */ + 57, + /* INCSSPQ */ + }, + { /* 638 */ + 81, + /* INSB */ + }, + { /* 639 */ + 81, + /* INSL */ + }, + { /* 640 */ + 81, + /* INSW */ + }, + { /* 641 */ + 79, + /* INT */ + }, + { /* 642 */ + 0, + /* INT1 */ + }, + { /* 643 */ + 0, + /* INT3 */ + }, + { /* 644 */ + 0, + /* INTO */ + }, + { /* 645 */ + 0, + /* INVD */ + }, + { /* 646 */ + 82, + /* INVEPT32 */ + }, + { /* 647 */ + 46, + /* INVEPT64 */ + }, + { /* 648 */ + 54, + /* INVLPG */ + }, + { /* 649 */ + 0, + /* INVLPGA32 */ + }, + { /* 650 */ + 0, + /* INVLPGA64 */ + }, + { /* 651 */ + 82, + /* INVPCID32 */ + }, + { /* 652 */ + 46, + /* INVPCID64 */ + }, + { /* 653 */ + 82, + /* INVVPID32 */ + }, + { /* 654 */ + 46, + /* INVVPID64 */ + }, + { /* 655 */ + 0, + /* IRET16 */ + }, + { /* 656 */ + 0, + /* IRET32 */ + }, + { /* 657 */ + 0, + /* IRET64 */ + }, + { /* 658 */ + 83, + /* JAE_1 */ + }, + { /* 659 */ + 84, + /* JAE_2 */ + }, + { /* 660 */ + 84, + /* JAE_4 */ + }, + { /* 661 */ + 83, + /* JA_1 */ + }, + { /* 662 */ + 84, + /* JA_2 */ + }, + { /* 663 */ + 84, + /* JA_4 */ + }, + { /* 664 */ + 83, + /* JBE_1 */ + }, + { /* 665 */ + 84, + /* JBE_2 */ + }, + { /* 666 */ + 84, + /* JBE_4 */ + }, + { /* 667 */ + 83, + /* JB_1 */ + }, + { /* 668 */ + 84, + /* JB_2 */ + }, + { /* 669 */ + 84, + /* JB_4 */ + }, + { /* 670 */ + 83, + /* JCXZ */ + }, + { /* 671 */ + 83, + /* JECXZ */ + }, + { /* 672 */ + 83, + /* JE_1 */ + }, + { /* 673 */ + 84, + /* JE_2 */ + }, + { /* 674 */ + 84, + /* JE_4 */ + }, + { /* 675 */ + 83, + /* JGE_1 */ + }, + { /* 676 */ + 84, + /* JGE_2 */ + }, + { /* 677 */ + 84, + /* JGE_4 */ + }, + { /* 678 */ + 83, + /* JG_1 */ + }, + { /* 679 */ + 84, + /* JG_2 */ + }, + { /* 680 */ + 84, + /* JG_4 */ + }, + { /* 681 */ + 83, + /* JLE_1 */ + }, + { /* 682 */ + 84, + /* JLE_2 */ + }, + { /* 683 */ + 84, + /* JLE_4 */ + }, + { /* 684 */ + 83, + /* JL_1 */ + }, + { /* 685 */ + 84, + /* JL_2 */ + }, + { /* 686 */ + 84, + /* JL_4 */ + }, + { /* 687 */ + 54, + /* JMP16m */ + }, + { /* 688 */ + 0, + /* */ + }, + { /* 689 */ + 55, + /* JMP16r */ + }, + { /* 690 */ + 0, + /* */ + }, + { /* 691 */ + 54, + /* JMP32m */ + }, + { /* 692 */ + 0, + /* */ + }, + { /* 693 */ + 55, + /* JMP32r */ + }, + { /* 694 */ + 0, + /* */ + }, + { /* 695 */ + 54, + /* JMP64m */ + }, + { /* 696 */ + 0, + /* */ + }, + { /* 697 */ + 57, + /* JMP64r */ + }, + { /* 698 */ + 0, + /* */ + }, + { /* 699 */ + 83, + /* JMP_1 */ + }, + { /* 700 */ + 84, + /* JMP_2 */ + }, + { /* 701 */ + 84, + /* JMP_4 */ + }, + { /* 702 */ + 83, + /* JNE_1 */ + }, + { /* 703 */ + 84, + /* JNE_2 */ + }, + { /* 704 */ + 84, + /* JNE_4 */ + }, + { /* 705 */ + 83, + /* JNO_1 */ + }, + { /* 706 */ + 84, + /* JNO_2 */ + }, + { /* 707 */ + 84, + /* JNO_4 */ + }, + { /* 708 */ + 83, + /* JNP_1 */ + }, + { /* 709 */ + 84, + /* JNP_2 */ + }, + { /* 710 */ + 84, + /* JNP_4 */ + }, + { /* 711 */ + 83, + /* JNS_1 */ + }, + { /* 712 */ + 84, + /* JNS_2 */ + }, + { /* 713 */ + 84, + /* JNS_4 */ + }, + { /* 714 */ + 83, + /* JO_1 */ + }, + { /* 715 */ + 84, + /* JO_2 */ + }, + { /* 716 */ + 84, + /* JO_4 */ + }, + { /* 717 */ + 83, + /* JP_1 */ + }, + { /* 718 */ + 84, + /* JP_2 */ + }, + { /* 719 */ + 84, + /* JP_4 */ + }, + { /* 720 */ + 83, + /* JRCXZ */ + }, + { /* 721 */ + 83, + /* JS_1 */ + }, + { /* 722 */ + 84, + /* JS_2 */ + }, + { /* 723 */ + 84, + /* JS_4 */ + }, + { /* 724 */ + 0, + /* LAHF */ + }, + { /* 725 */ + 44, + /* LAR16rm */ + }, + { /* 726 */ + 45, + /* LAR16rr */ + }, + { /* 727 */ + 44, + /* LAR32rm */ + }, + { /* 728 */ + 45, + /* LAR32rr */ + }, + { /* 729 */ + 46, + /* LAR64rm */ + }, + { /* 730 */ + 85, + /* LAR64rr */ + }, + { /* 731 */ + 44, + /* LDS16rm */ + }, + { /* 732 */ + 44, + /* LDS32rm */ + }, + { /* 733 */ + 44, + /* LEA16r */ + }, + { /* 734 */ + 44, + /* LEA32r */ + }, + { /* 735 */ + 44, + /* LEA64_32r */ + }, + { /* 736 */ + 46, + /* LEA64r */ + }, + { /* 737 */ + 0, + /* LEAVE */ + }, + { /* 738 */ + 0, + /* LEAVE64 */ + }, + { /* 739 */ + 44, + /* LES16rm */ + }, + { /* 740 */ + 44, + /* LES32rm */ + }, + { /* 741 */ + 44, + /* LFS16rm */ + }, + { /* 742 */ + 44, + /* LFS32rm */ + }, + { /* 743 */ + 46, + /* LFS64rm */ + }, + { /* 744 */ + 54, + /* LGDT16m */ + }, + { /* 745 */ + 54, + /* LGDT32m */ + }, + { /* 746 */ + 54, + /* LGDT64m */ + }, + { /* 747 */ + 44, + /* LGS16rm */ + }, + { /* 748 */ + 44, + /* LGS32rm */ + }, + { /* 749 */ + 46, + /* LGS64rm */ + }, + { /* 750 */ + 54, + /* LIDT16m */ + }, + { /* 751 */ + 54, + /* LIDT32m */ + }, + { /* 752 */ + 54, + /* LIDT64m */ + }, + { /* 753 */ + 54, + /* LLDT16m */ + }, + { /* 754 */ + 86, + /* LLDT16r */ + }, + { /* 755 */ + 80, + /* LLWPCB */ + }, + { /* 756 */ + 57, + /* LLWPCB64 */ + }, + { /* 757 */ + 54, + /* LMSW16m */ + }, + { /* 758 */ + 86, + /* LMSW16r */ + }, + { /* 759 */ + 0, + /* LOCK_PREFIX */ + }, + { /* 760 */ + 87, + /* LODSB */ + }, + { /* 761 */ + 87, + /* LODSL */ + }, + { /* 762 */ + 87, + /* LODSQ */ + }, + { /* 763 */ + 87, + /* LODSW */ + }, + { /* 764 */ + 83, + /* LOOP */ + }, + { /* 765 */ + 83, + /* LOOPE */ + }, + { /* 766 */ + 83, + /* LOOPNE */ + }, + { /* 767 */ + 88, + /* LRETIL */ + }, + { /* 768 */ + 88, + /* LRETIQ */ + }, + { /* 769 */ + 2, + /* LRETIW */ + }, + { /* 770 */ + 0, + /* LRETL */ + }, + { /* 771 */ + 0, + /* LRETQ */ + }, + { /* 772 */ + 0, + /* LRETW */ + }, + { /* 773 */ + 44, + /* LSL16rm */ + }, + { /* 774 */ + 45, + /* LSL16rr */ + }, + { /* 775 */ + 44, + /* LSL32rm */ + }, + { /* 776 */ + 45, + /* LSL32rr */ + }, + { /* 777 */ + 46, + /* LSL64rm */ + }, + { /* 778 */ + 85, + /* LSL64rr */ + }, + { /* 779 */ + 44, + /* LSS16rm */ + }, + { /* 780 */ + 44, + /* LSS32rm */ + }, + { /* 781 */ + 46, + /* LSS64rm */ + }, + { /* 782 */ + 54, + /* LTRm */ + }, + { /* 783 */ + 86, + /* LTRr */ + }, + { /* 784 */ + 89, + /* LWPINS32rmi */ + }, + { /* 785 */ + 90, + /* LWPINS32rri */ + }, + { /* 786 */ + 91, + /* LWPINS64rmi */ + }, + { /* 787 */ + 92, + /* LWPINS64rri */ + }, + { /* 788 */ + 89, + /* LWPVAL32rmi */ + }, + { /* 789 */ + 90, + /* LWPVAL32rri */ + }, + { /* 790 */ + 91, + /* LWPVAL64rmi */ + }, + { /* 791 */ + 92, + /* LWPVAL64rri */ + }, + { /* 792 */ + 44, + /* LZCNT16rm */ + }, + { /* 793 */ + 45, + /* LZCNT16rr */ + }, + { /* 794 */ + 44, + /* LZCNT32rm */ + }, + { /* 795 */ + 45, + /* LZCNT32rr */ + }, + { /* 796 */ + 46, + /* LZCNT64rm */ + }, + { /* 797 */ + 47, + /* LZCNT64rr */ + }, + { /* 798 */ + 0, + /* MONITORXrrr */ + }, + { /* 799 */ + 0, + /* MONTMUL */ + }, + { /* 800 */ + 93, + /* MOV16ao16 */ + }, + { /* 801 */ + 93, + /* MOV16ao32 */ + }, + { /* 802 */ + 93, + /* MOV16ao64 */ + }, + { /* 803 */ + 3, + /* MOV16mi */ + }, + { /* 804 */ + 5, + /* MOV16mr */ + }, + { /* 805 */ + 94, + /* MOV16ms */ + }, + { /* 806 */ + 93, + /* MOV16o16a */ + }, + { /* 807 */ + 93, + /* MOV16o32a */ + }, + { /* 808 */ + 93, + /* MOV16o64a */ + }, + { /* 809 */ + 95, + /* MOV16ri */ + }, + { /* 810 */ + 59, + /* MOV16ri_alt */ + }, + { /* 811 */ + 44, + /* MOV16rm */ + }, + { /* 812 */ + 51, + /* MOV16rr */ + }, + { /* 813 */ + 45, + /* MOV16rr_REV */ + }, + { /* 814 */ + 96, + /* MOV16rs */ + }, + { /* 815 */ + 97, + /* MOV16sm */ + }, + { /* 816 */ + 98, + /* MOV16sr */ + }, + { /* 817 */ + 93, + /* MOV32ao16 */ + }, + { /* 818 */ + 93, + /* MOV32ao32 */ + }, + { /* 819 */ + 93, + /* MOV32ao64 */ + }, + { /* 820 */ + 99, + /* MOV32cr */ + }, + { /* 821 */ + 100, + /* MOV32dr */ + }, + { /* 822 */ + 3, + /* MOV32mi */ + }, + { /* 823 */ + 5, + /* MOV32mr */ + }, + { /* 824 */ + 93, + /* MOV32o16a */ + }, + { /* 825 */ + 93, + /* MOV32o32a */ + }, + { /* 826 */ + 93, + /* MOV32o64a */ + }, + { /* 827 */ + 101, + /* MOV32rc */ + }, + { /* 828 */ + 102, + /* MOV32rd */ + }, + { /* 829 */ + 95, + /* MOV32ri */ + }, + { /* 830 */ + 59, + /* MOV32ri_alt */ + }, + { /* 831 */ + 44, + /* MOV32rm */ + }, + { /* 832 */ + 51, + /* MOV32rr */ + }, + { /* 833 */ + 45, + /* MOV32rr_REV */ + }, + { /* 834 */ + 96, + /* MOV32rs */ + }, + { /* 835 */ + 98, + /* MOV32sr */ + }, + { /* 836 */ + 93, + /* MOV64ao32 */ + }, + { /* 837 */ + 93, + /* MOV64ao64 */ + }, + { /* 838 */ + 103, + /* MOV64cr */ + }, + { /* 839 */ + 104, + /* MOV64dr */ + }, + { /* 840 */ + 12, + /* MOV64mi32 */ + }, + { /* 841 */ + 13, + /* MOV64mr */ + }, + { /* 842 */ + 93, + /* MOV64o32a */ + }, + { /* 843 */ + 93, + /* MOV64o64a */ + }, + { /* 844 */ + 105, + /* MOV64rc */ + }, + { /* 845 */ + 106, + /* MOV64rd */ + }, + { /* 846 */ + 107, + /* MOV64ri */ + }, + { /* 847 */ + 60, + /* MOV64ri32 */ + }, + { /* 848 */ + 46, + /* MOV64rm */ + }, + { /* 849 */ + 53, + /* MOV64rr */ + }, + { /* 850 */ + 47, + /* MOV64rr_REV */ + }, + { /* 851 */ + 108, + /* MOV64rs */ + }, + { /* 852 */ + 109, + /* MOV64sr */ + }, + { /* 853 */ + 93, + /* MOV8ao16 */ + }, + { /* 854 */ + 93, + /* MOV8ao32 */ + }, + { /* 855 */ + 93, + /* MOV8ao64 */ + }, + { /* 856 */ + 4, + /* MOV8mi */ + }, + { /* 857 */ + 19, + /* MOV8mr */ + }, + { /* 858 */ + 0, + /* */ + }, + { /* 859 */ + 93, + /* MOV8o16a */ + }, + { /* 860 */ + 93, + /* MOV8o32a */ + }, + { /* 861 */ + 93, + /* MOV8o64a */ + }, + { /* 862 */ + 110, + /* MOV8ri */ + }, + { /* 863 */ + 61, + /* MOV8ri_alt */ + }, + { /* 864 */ + 62, + /* MOV8rm */ + }, + { /* 865 */ + 0, + /* */ + }, + { /* 866 */ + 63, + /* MOV8rr */ + }, + { /* 867 */ + 0, + /* */ + }, + { /* 868 */ + 64, + /* MOV8rr_REV */ + }, + { /* 869 */ + 5, + /* MOVBE16mr */ + }, + { /* 870 */ + 44, + /* MOVBE16rm */ + }, + { /* 871 */ + 5, + /* MOVBE32mr */ + }, + { /* 872 */ + 44, + /* MOVBE32rm */ + }, + { /* 873 */ + 13, + /* MOVBE64mr */ + }, + { /* 874 */ + 46, + /* MOVBE64rm */ + }, + { /* 875 */ + 111, + /* MOVDIR64B16 */ + }, + { /* 876 */ + 82, + /* MOVDIR64B32 */ + }, + { /* 877 */ + 46, + /* MOVDIR64B64 */ + }, + { /* 878 */ + 112, + /* MOVDIRI32 */ + }, + { /* 879 */ + 13, + /* MOVDIRI64 */ + }, + { /* 880 */ + 65, + /* MOVSB */ + }, + { /* 881 */ + 65, + /* MOVSL */ + }, + { /* 882 */ + 65, + /* MOVSQ */ + }, + { /* 883 */ + 65, + /* MOVSW */ + }, + { /* 884 */ + 44, + /* MOVSX16rm16 */ + }, + { /* 885 */ + 44, + /* MOVSX16rm8 */ + }, + { /* 886 */ + 45, + /* MOVSX16rr16 */ + }, + { /* 887 */ + 113, + /* MOVSX16rr8 */ + }, + { /* 888 */ + 44, + /* MOVSX32rm16 */ + }, + { /* 889 */ + 44, + /* MOVSX32rm8 */ + }, + { /* 890 */ + 0, + /* */ + }, + { /* 891 */ + 114, + /* MOVSX32rr16 */ + }, + { /* 892 */ + 113, + /* MOVSX32rr8 */ + }, + { /* 893 */ + 0, + /* */ + }, + { /* 894 */ + 46, + /* MOVSX64rm16 */ + }, + { /* 895 */ + 46, + /* MOVSX64rm32 */ + }, + { /* 896 */ + 46, + /* MOVSX64rm8 */ + }, + { /* 897 */ + 115, + /* MOVSX64rr16 */ + }, + { /* 898 */ + 85, + /* MOVSX64rr32 */ + }, + { /* 899 */ + 116, + /* MOVSX64rr8 */ + }, + { /* 900 */ + 44, + /* MOVZX16rm16 */ + }, + { /* 901 */ + 44, + /* MOVZX16rm8 */ + }, + { /* 902 */ + 45, + /* MOVZX16rr16 */ + }, + { /* 903 */ + 113, + /* MOVZX16rr8 */ + }, + { /* 904 */ + 44, + /* MOVZX32rm16 */ + }, + { /* 905 */ + 44, + /* MOVZX32rm8 */ + }, + { /* 906 */ + 0, + /* */ + }, + { /* 907 */ + 114, + /* MOVZX32rr16 */ + }, + { /* 908 */ + 113, + /* MOVZX32rr8 */ + }, + { /* 909 */ + 0, + /* */ + }, + { /* 910 */ + 46, + /* MOVZX64rm16 */ + }, + { /* 911 */ + 46, + /* MOVZX64rm8 */ + }, + { /* 912 */ + 115, + /* MOVZX64rr16 */ + }, + { /* 913 */ + 116, + /* MOVZX64rr8 */ + }, + { /* 914 */ + 54, + /* MUL16m */ + }, + { /* 915 */ + 55, + /* MUL16r */ + }, + { /* 916 */ + 54, + /* MUL32m */ + }, + { /* 917 */ + 55, + /* MUL32r */ + }, + { /* 918 */ + 54, + /* MUL64m */ + }, + { /* 919 */ + 57, + /* MUL64r */ + }, + { /* 920 */ + 54, + /* MUL8m */ + }, + { /* 921 */ + 69, + /* MUL8r */ + }, + { /* 922 */ + 26, + /* MULX32rm */ + }, + { /* 923 */ + 27, + /* MULX32rr */ + }, + { /* 924 */ + 28, + /* MULX64rm */ + }, + { /* 925 */ + 29, + /* MULX64rr */ + }, + { /* 926 */ + 0, + /* MWAITXrrr */ + }, + { /* 927 */ + 54, + /* NEG16m */ + }, + { /* 928 */ + 66, + /* NEG16r */ + }, + { /* 929 */ + 54, + /* NEG32m */ + }, + { /* 930 */ + 66, + /* NEG32r */ + }, + { /* 931 */ + 54, + /* NEG64m */ + }, + { /* 932 */ + 67, + /* NEG64r */ + }, + { /* 933 */ + 54, + /* NEG8m */ + }, + { /* 934 */ + 68, + /* NEG8r */ + }, + { /* 935 */ + 0, + /* NOOP */ + }, + { /* 936 */ + 54, + /* NOOP18_16m4 */ + }, + { /* 937 */ + 54, + /* NOOP18_16m5 */ + }, + { /* 938 */ + 54, + /* NOOP18_16m6 */ + }, + { /* 939 */ + 54, + /* NOOP18_16m7 */ + }, + { /* 940 */ + 55, + /* NOOP18_16r4 */ + }, + { /* 941 */ + 55, + /* NOOP18_16r5 */ + }, + { /* 942 */ + 55, + /* NOOP18_16r6 */ + }, + { /* 943 */ + 55, + /* NOOP18_16r7 */ + }, + { /* 944 */ + 54, + /* NOOP18_m4 */ + }, + { /* 945 */ + 54, + /* NOOP18_m5 */ + }, + { /* 946 */ + 54, + /* NOOP18_m6 */ + }, + { /* 947 */ + 54, + /* NOOP18_m7 */ + }, + { /* 948 */ + 55, + /* NOOP18_r4 */ + }, + { /* 949 */ + 55, + /* NOOP18_r5 */ + }, + { /* 950 */ + 55, + /* NOOP18_r6 */ + }, + { /* 951 */ + 55, + /* NOOP18_r7 */ + }, + { /* 952 */ + 45, + /* NOOP19rr */ + }, + { /* 953 */ + 54, + /* NOOPL */ + }, + { /* 954 */ + 54, + /* NOOPL_19 */ + }, + { /* 955 */ + 54, + /* NOOPL_1d */ + }, + { /* 956 */ + 54, + /* NOOPL_1e */ + }, + { /* 957 */ + 55, + /* NOOPLr */ + }, + { /* 958 */ + 54, + /* NOOPQ */ + }, + { /* 959 */ + 57, + /* NOOPQr */ + }, + { /* 960 */ + 54, + /* NOOPW */ + }, + { /* 961 */ + 54, + /* NOOPW_19 */ + }, + { /* 962 */ + 54, + /* NOOPW_1c */ + }, + { /* 963 */ + 54, + /* NOOPW_1d */ + }, + { /* 964 */ + 54, + /* NOOPW_1e */ + }, + { /* 965 */ + 55, + /* NOOPWr */ + }, + { /* 966 */ + 54, + /* NOT16m */ + }, + { /* 967 */ + 66, + /* NOT16r */ + }, + { /* 968 */ + 54, + /* NOT32m */ + }, + { /* 969 */ + 66, + /* NOT32r */ + }, + { /* 970 */ + 54, + /* NOT64m */ + }, + { /* 971 */ + 67, + /* NOT64r */ + }, + { /* 972 */ + 54, + /* NOT8m */ + }, + { /* 973 */ + 68, + /* NOT8r */ + }, + { /* 974 */ + 2, + /* OR16i16 */ + }, + { /* 975 */ + 3, + /* OR16mi */ + }, + { /* 976 */ + 4, + /* OR16mi8 */ + }, + { /* 977 */ + 5, + /* OR16mr */ + }, + { /* 978 */ + 6, + /* OR16ri */ + }, + { /* 979 */ + 7, + /* OR16ri8 */ + }, + { /* 980 */ + 8, + /* OR16rm */ + }, + { /* 981 */ + 9, + /* OR16rr */ + }, + { /* 982 */ + 10, + /* OR16rr_REV */ + }, + { /* 983 */ + 2, + /* OR32i32 */ + }, + { /* 984 */ + 3, + /* OR32mi */ + }, + { /* 985 */ + 4, + /* OR32mi8 */ + }, + { /* 986 */ + 5, + /* OR32mr */ + }, + { /* 987 */ + 6, + /* OR32ri */ + }, + { /* 988 */ + 7, + /* OR32ri8 */ + }, + { /* 989 */ + 8, + /* OR32rm */ + }, + { /* 990 */ + 9, + /* OR32rr */ + }, + { /* 991 */ + 10, + /* OR32rr_REV */ + }, + { /* 992 */ + 11, + /* OR64i32 */ + }, + { /* 993 */ + 12, + /* OR64mi32 */ + }, + { /* 994 */ + 4, + /* OR64mi8 */ + }, + { /* 995 */ + 13, + /* OR64mr */ + }, + { /* 996 */ + 14, + /* OR64ri32 */ + }, + { /* 997 */ + 15, + /* OR64ri8 */ + }, + { /* 998 */ + 16, + /* OR64rm */ + }, + { /* 999 */ + 17, + /* OR64rr */ + }, + { /* 1000 */ + 18, + /* OR64rr_REV */ + }, + { /* 1001 */ + 1, + /* OR8i8 */ + }, + { /* 1002 */ + 4, + /* OR8mi */ + }, + { /* 1003 */ + 4, + /* OR8mi8 */ + }, + { /* 1004 */ + 19, + /* OR8mr */ + }, + { /* 1005 */ + 20, + /* OR8ri */ + }, + { /* 1006 */ + 20, + /* OR8ri8 */ + }, + { /* 1007 */ + 21, + /* OR8rm */ + }, + { /* 1008 */ + 22, + /* OR8rr */ + }, + { /* 1009 */ + 23, + /* OR8rr_REV */ + }, + { /* 1010 */ + 79, + /* OUT16ir */ + }, + { /* 1011 */ + 0, + /* OUT16rr */ + }, + { /* 1012 */ + 79, + /* OUT32ir */ + }, + { /* 1013 */ + 0, + /* OUT32rr */ + }, + { /* 1014 */ + 79, + /* OUT8ir */ + }, + { /* 1015 */ + 0, + /* OUT8rr */ + }, + { /* 1016 */ + 87, + /* OUTSB */ + }, + { /* 1017 */ + 87, + /* OUTSL */ + }, + { /* 1018 */ + 87, + /* OUTSW */ + }, + { /* 1019 */ + 0, + /* PCONFIG */ + }, + { /* 1020 */ + 26, + /* PDEP32rm */ + }, + { /* 1021 */ + 27, + /* PDEP32rr */ + }, + { /* 1022 */ + 28, + /* PDEP64rm */ + }, + { /* 1023 */ + 29, + /* PDEP64rr */ + }, + { /* 1024 */ + 26, + /* PEXT32rm */ + }, + { /* 1025 */ + 27, + /* PEXT32rr */ + }, + { /* 1026 */ + 28, + /* PEXT64rm */ + }, + { /* 1027 */ + 29, + /* PEXT64rr */ + }, + { /* 1028 */ + 117, + /* POP16r */ + }, + { /* 1029 */ + 54, + /* POP16rmm */ + }, + { /* 1030 */ + 55, + /* POP16rmr */ + }, + { /* 1031 */ + 117, + /* POP32r */ + }, + { /* 1032 */ + 54, + /* POP32rmm */ + }, + { /* 1033 */ + 55, + /* POP32rmr */ + }, + { /* 1034 */ + 118, + /* POP64r */ + }, + { /* 1035 */ + 54, + /* POP64rmm */ + }, + { /* 1036 */ + 57, + /* POP64rmr */ + }, + { /* 1037 */ + 0, + /* POPA16 */ + }, + { /* 1038 */ + 0, + /* POPA32 */ + }, + { /* 1039 */ + 0, + /* POPDS16 */ + }, + { /* 1040 */ + 0, + /* POPDS32 */ + }, + { /* 1041 */ + 0, + /* POPES16 */ + }, + { /* 1042 */ + 0, + /* POPES32 */ + }, + { /* 1043 */ + 0, + /* POPF16 */ + }, + { /* 1044 */ + 0, + /* POPF32 */ + }, + { /* 1045 */ + 0, + /* POPF64 */ + }, + { /* 1046 */ + 0, + /* POPFS16 */ + }, + { /* 1047 */ + 0, + /* POPFS32 */ + }, + { /* 1048 */ + 0, + /* POPFS64 */ + }, + { /* 1049 */ + 0, + /* POPGS16 */ + }, + { /* 1050 */ + 0, + /* POPGS32 */ + }, + { /* 1051 */ + 0, + /* POPGS64 */ + }, + { /* 1052 */ + 0, + /* POPSS16 */ + }, + { /* 1053 */ + 0, + /* POPSS32 */ + }, + { /* 1054 */ + 54, + /* PTWRITE64m */ + }, + { /* 1055 */ + 57, + /* PTWRITE64r */ + }, + { /* 1056 */ + 54, + /* PTWRITEm */ + }, + { /* 1057 */ + 80, + /* PTWRITEr */ + }, + { /* 1058 */ + 1, + /* PUSH16i8 */ + }, + { /* 1059 */ + 117, + /* PUSH16r */ + }, + { /* 1060 */ + 54, + /* PUSH16rmm */ + }, + { /* 1061 */ + 55, + /* PUSH16rmr */ + }, + { /* 1062 */ + 1, + /* PUSH32i8 */ + }, + { /* 1063 */ + 117, + /* PUSH32r */ + }, + { /* 1064 */ + 54, + /* PUSH32rmm */ + }, + { /* 1065 */ + 55, + /* PUSH32rmr */ + }, + { /* 1066 */ + 11, + /* PUSH64i32 */ + }, + { /* 1067 */ + 1, + /* PUSH64i8 */ + }, + { /* 1068 */ + 118, + /* PUSH64r */ + }, + { /* 1069 */ + 54, + /* PUSH64rmm */ + }, + { /* 1070 */ + 57, + /* PUSH64rmr */ + }, + { /* 1071 */ + 0, + /* PUSHA16 */ + }, + { /* 1072 */ + 0, + /* PUSHA32 */ + }, + { /* 1073 */ + 0, + /* PUSHCS16 */ + }, + { /* 1074 */ + 0, + /* PUSHCS32 */ + }, + { /* 1075 */ + 0, + /* PUSHDS16 */ + }, + { /* 1076 */ + 0, + /* PUSHDS32 */ + }, + { /* 1077 */ + 0, + /* PUSHES16 */ + }, + { /* 1078 */ + 0, + /* PUSHES32 */ + }, + { /* 1079 */ + 0, + /* PUSHF16 */ + }, + { /* 1080 */ + 0, + /* PUSHF32 */ + }, + { /* 1081 */ + 0, + /* PUSHF64 */ + }, + { /* 1082 */ + 0, + /* PUSHFS16 */ + }, + { /* 1083 */ + 0, + /* PUSHFS32 */ + }, + { /* 1084 */ + 0, + /* PUSHFS64 */ + }, + { /* 1085 */ + 0, + /* PUSHGS16 */ + }, + { /* 1086 */ + 0, + /* PUSHGS32 */ + }, + { /* 1087 */ + 0, + /* PUSHGS64 */ + }, + { /* 1088 */ + 0, + /* PUSHSS16 */ + }, + { /* 1089 */ + 0, + /* PUSHSS32 */ + }, + { /* 1090 */ + 2, + /* PUSHi16 */ + }, + { /* 1091 */ + 2, + /* PUSHi32 */ + }, + { /* 1092 */ + 54, + /* RCL16m1 */ + }, + { /* 1093 */ + 54, + /* RCL16mCL */ + }, + { /* 1094 */ + 119, + /* RCL16mi */ + }, + { /* 1095 */ + 66, + /* RCL16r1 */ + }, + { /* 1096 */ + 66, + /* RCL16rCL */ + }, + { /* 1097 */ + 120, + /* RCL16ri */ + }, + { /* 1098 */ + 54, + /* RCL32m1 */ + }, + { /* 1099 */ + 54, + /* RCL32mCL */ + }, + { /* 1100 */ + 119, + /* RCL32mi */ + }, + { /* 1101 */ + 66, + /* RCL32r1 */ + }, + { /* 1102 */ + 66, + /* RCL32rCL */ + }, + { /* 1103 */ + 120, + /* RCL32ri */ + }, + { /* 1104 */ + 54, + /* RCL64m1 */ + }, + { /* 1105 */ + 54, + /* RCL64mCL */ + }, + { /* 1106 */ + 119, + /* RCL64mi */ + }, + { /* 1107 */ + 67, + /* RCL64r1 */ + }, + { /* 1108 */ + 67, + /* RCL64rCL */ + }, + { /* 1109 */ + 121, + /* RCL64ri */ + }, + { /* 1110 */ + 54, + /* RCL8m1 */ + }, + { /* 1111 */ + 54, + /* RCL8mCL */ + }, + { /* 1112 */ + 119, + /* RCL8mi */ + }, + { /* 1113 */ + 68, + /* RCL8r1 */ + }, + { /* 1114 */ + 68, + /* RCL8rCL */ + }, + { /* 1115 */ + 122, + /* RCL8ri */ + }, + { /* 1116 */ + 54, + /* RCR16m1 */ + }, + { /* 1117 */ + 54, + /* RCR16mCL */ + }, + { /* 1118 */ + 119, + /* RCR16mi */ + }, + { /* 1119 */ + 66, + /* RCR16r1 */ + }, + { /* 1120 */ + 66, + /* RCR16rCL */ + }, + { /* 1121 */ + 120, + /* RCR16ri */ + }, + { /* 1122 */ + 54, + /* RCR32m1 */ + }, + { /* 1123 */ + 54, + /* RCR32mCL */ + }, + { /* 1124 */ + 119, + /* RCR32mi */ + }, + { /* 1125 */ + 66, + /* RCR32r1 */ + }, + { /* 1126 */ + 66, + /* RCR32rCL */ + }, + { /* 1127 */ + 120, + /* RCR32ri */ + }, + { /* 1128 */ + 54, + /* RCR64m1 */ + }, + { /* 1129 */ + 54, + /* RCR64mCL */ + }, + { /* 1130 */ + 119, + /* RCR64mi */ + }, + { /* 1131 */ + 67, + /* RCR64r1 */ + }, + { /* 1132 */ + 67, + /* RCR64rCL */ + }, + { /* 1133 */ + 121, + /* RCR64ri */ + }, + { /* 1134 */ + 54, + /* RCR8m1 */ + }, + { /* 1135 */ + 54, + /* RCR8mCL */ + }, + { /* 1136 */ + 119, + /* RCR8mi */ + }, + { /* 1137 */ + 68, + /* RCR8r1 */ + }, + { /* 1138 */ + 68, + /* RCR8rCL */ + }, + { /* 1139 */ + 122, + /* RCR8ri */ + }, + { /* 1140 */ + 80, + /* RDFSBASE */ + }, + { /* 1141 */ + 57, + /* RDFSBASE64 */ + }, + { /* 1142 */ + 80, + /* RDGSBASE */ + }, + { /* 1143 */ + 57, + /* RDGSBASE64 */ + }, + { /* 1144 */ + 0, + /* RDMSR */ + }, + { /* 1145 */ + 80, + /* RDPID32 */ + }, + { /* 1146 */ + 57, + /* RDPID64 */ + }, + { /* 1147 */ + 0, + /* RDPKRUr */ + }, + { /* 1148 */ + 0, + /* RDPMC */ + }, + { /* 1149 */ + 55, + /* RDRAND16r */ + }, + { /* 1150 */ + 55, + /* RDRAND32r */ + }, + { /* 1151 */ + 57, + /* RDRAND64r */ + }, + { /* 1152 */ + 55, + /* RDSEED16r */ + }, + { /* 1153 */ + 55, + /* RDSEED32r */ + }, + { /* 1154 */ + 57, + /* RDSEED64r */ + }, + { /* 1155 */ + 123, + /* RDSSPD */ + }, + { /* 1156 */ + 67, + /* RDSSPQ */ + }, + { /* 1157 */ + 0, + /* RDTSC */ + }, + { /* 1158 */ + 0, + /* RDTSCP */ + }, + { /* 1159 */ + 0, + /* REPNE_PREFIX */ + }, + { /* 1160 */ + 0, + /* REP_PREFIX */ + }, + { /* 1161 */ + 88, + /* RETIL */ + }, + { /* 1162 */ + 88, + /* RETIQ */ + }, + { /* 1163 */ + 2, + /* RETIW */ + }, + { /* 1164 */ + 0, + /* RETL */ + }, + { /* 1165 */ + 0, + /* RETQ */ + }, + { /* 1166 */ + 0, + /* RETW */ + }, + { /* 1167 */ + 0, + /* REX64_PREFIX */ + }, + { /* 1168 */ + 54, + /* ROL16m1 */ + }, + { /* 1169 */ + 54, + /* ROL16mCL */ + }, + { /* 1170 */ + 119, + /* ROL16mi */ + }, + { /* 1171 */ + 66, + /* ROL16r1 */ + }, + { /* 1172 */ + 66, + /* ROL16rCL */ + }, + { /* 1173 */ + 120, + /* ROL16ri */ + }, + { /* 1174 */ + 54, + /* ROL32m1 */ + }, + { /* 1175 */ + 54, + /* ROL32mCL */ + }, + { /* 1176 */ + 119, + /* ROL32mi */ + }, + { /* 1177 */ + 66, + /* ROL32r1 */ + }, + { /* 1178 */ + 66, + /* ROL32rCL */ + }, + { /* 1179 */ + 120, + /* ROL32ri */ + }, + { /* 1180 */ + 54, + /* ROL64m1 */ + }, + { /* 1181 */ + 54, + /* ROL64mCL */ + }, + { /* 1182 */ + 119, + /* ROL64mi */ + }, + { /* 1183 */ + 67, + /* ROL64r1 */ + }, + { /* 1184 */ + 67, + /* ROL64rCL */ + }, + { /* 1185 */ + 121, + /* ROL64ri */ + }, + { /* 1186 */ + 54, + /* ROL8m1 */ + }, + { /* 1187 */ + 54, + /* ROL8mCL */ + }, + { /* 1188 */ + 119, + /* ROL8mi */ + }, + { /* 1189 */ + 68, + /* ROL8r1 */ + }, + { /* 1190 */ + 68, + /* ROL8rCL */ + }, + { /* 1191 */ + 122, + /* ROL8ri */ + }, + { /* 1192 */ + 54, + /* ROR16m1 */ + }, + { /* 1193 */ + 54, + /* ROR16mCL */ + }, + { /* 1194 */ + 119, + /* ROR16mi */ + }, + { /* 1195 */ + 66, + /* ROR16r1 */ + }, + { /* 1196 */ + 66, + /* ROR16rCL */ + }, + { /* 1197 */ + 120, + /* ROR16ri */ + }, + { /* 1198 */ + 54, + /* ROR32m1 */ + }, + { /* 1199 */ + 54, + /* ROR32mCL */ + }, + { /* 1200 */ + 119, + /* ROR32mi */ + }, + { /* 1201 */ + 66, + /* ROR32r1 */ + }, + { /* 1202 */ + 66, + /* ROR32rCL */ + }, + { /* 1203 */ + 120, + /* ROR32ri */ + }, + { /* 1204 */ + 54, + /* ROR64m1 */ + }, + { /* 1205 */ + 54, + /* ROR64mCL */ + }, + { /* 1206 */ + 119, + /* ROR64mi */ + }, + { /* 1207 */ + 67, + /* ROR64r1 */ + }, + { /* 1208 */ + 67, + /* ROR64rCL */ + }, + { /* 1209 */ + 121, + /* ROR64ri */ + }, + { /* 1210 */ + 54, + /* ROR8m1 */ + }, + { /* 1211 */ + 54, + /* ROR8mCL */ + }, + { /* 1212 */ + 119, + /* ROR8mi */ + }, + { /* 1213 */ + 68, + /* ROR8r1 */ + }, + { /* 1214 */ + 68, + /* ROR8rCL */ + }, + { /* 1215 */ + 122, + /* ROR8ri */ + }, + { /* 1216 */ + 124, + /* RORX32mi */ + }, + { /* 1217 */ + 125, + /* RORX32ri */ + }, + { /* 1218 */ + 126, + /* RORX64mi */ + }, + { /* 1219 */ + 127, + /* RORX64ri */ + }, + { /* 1220 */ + 0, + /* RSM */ + }, + { /* 1221 */ + 54, + /* RSTORSSP */ + }, + { /* 1222 */ + 0, + /* SAHF */ + }, + { /* 1223 */ + 54, + /* SAL16m1 */ + }, + { /* 1224 */ + 54, + /* SAL16mCL */ + }, + { /* 1225 */ + 4, + /* SAL16mi */ + }, + { /* 1226 */ + 66, + /* SAL16r1 */ + }, + { /* 1227 */ + 66, + /* SAL16rCL */ + }, + { /* 1228 */ + 7, + /* SAL16ri */ + }, + { /* 1229 */ + 54, + /* SAL32m1 */ + }, + { /* 1230 */ + 54, + /* SAL32mCL */ + }, + { /* 1231 */ + 4, + /* SAL32mi */ + }, + { /* 1232 */ + 66, + /* SAL32r1 */ + }, + { /* 1233 */ + 66, + /* SAL32rCL */ + }, + { /* 1234 */ + 7, + /* SAL32ri */ + }, + { /* 1235 */ + 54, + /* SAL64m1 */ + }, + { /* 1236 */ + 54, + /* SAL64mCL */ + }, + { /* 1237 */ + 4, + /* SAL64mi */ + }, + { /* 1238 */ + 67, + /* SAL64r1 */ + }, + { /* 1239 */ + 67, + /* SAL64rCL */ + }, + { /* 1240 */ + 15, + /* SAL64ri */ + }, + { /* 1241 */ + 54, + /* SAL8m1 */ + }, + { /* 1242 */ + 54, + /* SAL8mCL */ + }, + { /* 1243 */ + 4, + /* SAL8mi */ + }, + { /* 1244 */ + 68, + /* SAL8r1 */ + }, + { /* 1245 */ + 68, + /* SAL8rCL */ + }, + { /* 1246 */ + 20, + /* SAL8ri */ + }, + { /* 1247 */ + 0, + /* SALC */ + }, + { /* 1248 */ + 54, + /* SAR16m1 */ + }, + { /* 1249 */ + 54, + /* SAR16mCL */ + }, + { /* 1250 */ + 119, + /* SAR16mi */ + }, + { /* 1251 */ + 66, + /* SAR16r1 */ + }, + { /* 1252 */ + 66, + /* SAR16rCL */ + }, + { /* 1253 */ + 120, + /* SAR16ri */ + }, + { /* 1254 */ + 54, + /* SAR32m1 */ + }, + { /* 1255 */ + 54, + /* SAR32mCL */ + }, + { /* 1256 */ + 119, + /* SAR32mi */ + }, + { /* 1257 */ + 66, + /* SAR32r1 */ + }, + { /* 1258 */ + 66, + /* SAR32rCL */ + }, + { /* 1259 */ + 120, + /* SAR32ri */ + }, + { /* 1260 */ + 54, + /* SAR64m1 */ + }, + { /* 1261 */ + 54, + /* SAR64mCL */ + }, + { /* 1262 */ + 119, + /* SAR64mi */ + }, + { /* 1263 */ + 67, + /* SAR64r1 */ + }, + { /* 1264 */ + 67, + /* SAR64rCL */ + }, + { /* 1265 */ + 121, + /* SAR64ri */ + }, + { /* 1266 */ + 54, + /* SAR8m1 */ + }, + { /* 1267 */ + 54, + /* SAR8mCL */ + }, + { /* 1268 */ + 119, + /* SAR8mi */ + }, + { /* 1269 */ + 68, + /* SAR8r1 */ + }, + { /* 1270 */ + 68, + /* SAR8rCL */ + }, + { /* 1271 */ + 122, + /* SAR8ri */ + }, + { /* 1272 */ + 32, + /* SARX32rm */ + }, + { /* 1273 */ + 33, + /* SARX32rr */ + }, + { /* 1274 */ + 34, + /* SARX64rm */ + }, + { /* 1275 */ + 35, + /* SARX64rr */ + }, + { /* 1276 */ + 0, + /* SAVEPREVSSP */ + }, + { /* 1277 */ + 2, + /* SBB16i16 */ + }, + { /* 1278 */ + 3, + /* SBB16mi */ + }, + { /* 1279 */ + 4, + /* SBB16mi8 */ + }, + { /* 1280 */ + 5, + /* SBB16mr */ + }, + { /* 1281 */ + 6, + /* SBB16ri */ + }, + { /* 1282 */ + 7, + /* SBB16ri8 */ + }, + { /* 1283 */ + 8, + /* SBB16rm */ + }, + { /* 1284 */ + 9, + /* SBB16rr */ + }, + { /* 1285 */ + 10, + /* SBB16rr_REV */ + }, + { /* 1286 */ + 2, + /* SBB32i32 */ + }, + { /* 1287 */ + 3, + /* SBB32mi */ + }, + { /* 1288 */ + 4, + /* SBB32mi8 */ + }, + { /* 1289 */ + 5, + /* SBB32mr */ + }, + { /* 1290 */ + 6, + /* SBB32ri */ + }, + { /* 1291 */ + 7, + /* SBB32ri8 */ + }, + { /* 1292 */ + 8, + /* SBB32rm */ + }, + { /* 1293 */ + 9, + /* SBB32rr */ + }, + { /* 1294 */ + 10, + /* SBB32rr_REV */ + }, + { /* 1295 */ + 11, + /* SBB64i32 */ + }, + { /* 1296 */ + 12, + /* SBB64mi32 */ + }, + { /* 1297 */ + 4, + /* SBB64mi8 */ + }, + { /* 1298 */ + 13, + /* SBB64mr */ + }, + { /* 1299 */ + 14, + /* SBB64ri32 */ + }, + { /* 1300 */ + 15, + /* SBB64ri8 */ + }, + { /* 1301 */ + 16, + /* SBB64rm */ + }, + { /* 1302 */ + 17, + /* SBB64rr */ + }, + { /* 1303 */ + 18, + /* SBB64rr_REV */ + }, + { /* 1304 */ + 1, + /* SBB8i8 */ + }, + { /* 1305 */ + 4, + /* SBB8mi */ + }, + { /* 1306 */ + 4, + /* SBB8mi8 */ + }, + { /* 1307 */ + 19, + /* SBB8mr */ + }, + { /* 1308 */ + 20, + /* SBB8ri */ + }, + { /* 1309 */ + 20, + /* SBB8ri8 */ + }, + { /* 1310 */ + 21, + /* SBB8rm */ + }, + { /* 1311 */ + 22, + /* SBB8rr */ + }, + { /* 1312 */ + 23, + /* SBB8rr_REV */ + }, + { /* 1313 */ + 81, + /* SCASB */ + }, + { /* 1314 */ + 81, + /* SCASL */ + }, + { /* 1315 */ + 81, + /* SCASQ */ + }, + { /* 1316 */ + 81, + /* SCASW */ + }, + { /* 1317 */ + 54, + /* SETAEm */ + }, + { /* 1318 */ + 69, + /* SETAEr */ + }, + { /* 1319 */ + 54, + /* SETAm */ + }, + { /* 1320 */ + 69, + /* SETAr */ + }, + { /* 1321 */ + 54, + /* SETBEm */ + }, + { /* 1322 */ + 69, + /* SETBEr */ + }, + { /* 1323 */ + 54, + /* SETBm */ + }, + { /* 1324 */ + 69, + /* SETBr */ + }, + { /* 1325 */ + 54, + /* SETEm */ + }, + { /* 1326 */ + 69, + /* SETEr */ + }, + { /* 1327 */ + 54, + /* SETGEm */ + }, + { /* 1328 */ + 69, + /* SETGEr */ + }, + { /* 1329 */ + 54, + /* SETGm */ + }, + { /* 1330 */ + 69, + /* SETGr */ + }, + { /* 1331 */ + 54, + /* SETLEm */ + }, + { /* 1332 */ + 69, + /* SETLEr */ + }, + { /* 1333 */ + 54, + /* SETLm */ + }, + { /* 1334 */ + 69, + /* SETLr */ + }, + { /* 1335 */ + 54, + /* SETNEm */ + }, + { /* 1336 */ + 69, + /* SETNEr */ + }, + { /* 1337 */ + 54, + /* SETNOm */ + }, + { /* 1338 */ + 69, + /* SETNOr */ + }, + { /* 1339 */ + 54, + /* SETNPm */ + }, + { /* 1340 */ + 69, + /* SETNPr */ + }, + { /* 1341 */ + 54, + /* SETNSm */ + }, + { /* 1342 */ + 69, + /* SETNSr */ + }, + { /* 1343 */ + 54, + /* SETOm */ + }, + { /* 1344 */ + 69, + /* SETOr */ + }, + { /* 1345 */ + 54, + /* SETPm */ + }, + { /* 1346 */ + 69, + /* SETPr */ + }, + { /* 1347 */ + 0, + /* SETSSBSY */ + }, + { /* 1348 */ + 54, + /* SETSm */ + }, + { /* 1349 */ + 69, + /* SETSr */ + }, + { /* 1350 */ + 54, + /* SGDT16m */ + }, + { /* 1351 */ + 54, + /* SGDT32m */ + }, + { /* 1352 */ + 54, + /* SGDT64m */ + }, + { /* 1353 */ + 54, + /* SHL16m1 */ + }, + { /* 1354 */ + 54, + /* SHL16mCL */ + }, + { /* 1355 */ + 119, + /* SHL16mi */ + }, + { /* 1356 */ + 66, + /* SHL16r1 */ + }, + { /* 1357 */ + 66, + /* SHL16rCL */ + }, + { /* 1358 */ + 120, + /* SHL16ri */ + }, + { /* 1359 */ + 54, + /* SHL32m1 */ + }, + { /* 1360 */ + 54, + /* SHL32mCL */ + }, + { /* 1361 */ + 119, + /* SHL32mi */ + }, + { /* 1362 */ + 66, + /* SHL32r1 */ + }, + { /* 1363 */ + 66, + /* SHL32rCL */ + }, + { /* 1364 */ + 120, + /* SHL32ri */ + }, + { /* 1365 */ + 54, + /* SHL64m1 */ + }, + { /* 1366 */ + 54, + /* SHL64mCL */ + }, + { /* 1367 */ + 119, + /* SHL64mi */ + }, + { /* 1368 */ + 67, + /* SHL64r1 */ + }, + { /* 1369 */ + 67, + /* SHL64rCL */ + }, + { /* 1370 */ + 121, + /* SHL64ri */ + }, + { /* 1371 */ + 54, + /* SHL8m1 */ + }, + { /* 1372 */ + 54, + /* SHL8mCL */ + }, + { /* 1373 */ + 119, + /* SHL8mi */ + }, + { /* 1374 */ + 68, + /* SHL8r1 */ + }, + { /* 1375 */ + 68, + /* SHL8rCL */ + }, + { /* 1376 */ + 122, + /* SHL8ri */ + }, + { /* 1377 */ + 5, + /* SHLD16mrCL */ + }, + { /* 1378 */ + 128, + /* SHLD16mri8 */ + }, + { /* 1379 */ + 9, + /* SHLD16rrCL */ + }, + { /* 1380 */ + 129, + /* SHLD16rri8 */ + }, + { /* 1381 */ + 5, + /* SHLD32mrCL */ + }, + { /* 1382 */ + 128, + /* SHLD32mri8 */ + }, + { /* 1383 */ + 9, + /* SHLD32rrCL */ + }, + { /* 1384 */ + 129, + /* SHLD32rri8 */ + }, + { /* 1385 */ + 13, + /* SHLD64mrCL */ + }, + { /* 1386 */ + 130, + /* SHLD64mri8 */ + }, + { /* 1387 */ + 17, + /* SHLD64rrCL */ + }, + { /* 1388 */ + 131, + /* SHLD64rri8 */ + }, + { /* 1389 */ + 32, + /* SHLX32rm */ + }, + { /* 1390 */ + 33, + /* SHLX32rr */ + }, + { /* 1391 */ + 34, + /* SHLX64rm */ + }, + { /* 1392 */ + 35, + /* SHLX64rr */ + }, + { /* 1393 */ + 54, + /* SHR16m1 */ + }, + { /* 1394 */ + 54, + /* SHR16mCL */ + }, + { /* 1395 */ + 119, + /* SHR16mi */ + }, + { /* 1396 */ + 66, + /* SHR16r1 */ + }, + { /* 1397 */ + 66, + /* SHR16rCL */ + }, + { /* 1398 */ + 120, + /* SHR16ri */ + }, + { /* 1399 */ + 54, + /* SHR32m1 */ + }, + { /* 1400 */ + 54, + /* SHR32mCL */ + }, + { /* 1401 */ + 119, + /* SHR32mi */ + }, + { /* 1402 */ + 66, + /* SHR32r1 */ + }, + { /* 1403 */ + 66, + /* SHR32rCL */ + }, + { /* 1404 */ + 120, + /* SHR32ri */ + }, + { /* 1405 */ + 54, + /* SHR64m1 */ + }, + { /* 1406 */ + 54, + /* SHR64mCL */ + }, + { /* 1407 */ + 119, + /* SHR64mi */ + }, + { /* 1408 */ + 67, + /* SHR64r1 */ + }, + { /* 1409 */ + 67, + /* SHR64rCL */ + }, + { /* 1410 */ + 121, + /* SHR64ri */ + }, + { /* 1411 */ + 54, + /* SHR8m1 */ + }, + { /* 1412 */ + 54, + /* SHR8mCL */ + }, + { /* 1413 */ + 119, + /* SHR8mi */ + }, + { /* 1414 */ + 68, + /* SHR8r1 */ + }, + { /* 1415 */ + 68, + /* SHR8rCL */ + }, + { /* 1416 */ + 122, + /* SHR8ri */ + }, + { /* 1417 */ + 5, + /* SHRD16mrCL */ + }, + { /* 1418 */ + 128, + /* SHRD16mri8 */ + }, + { /* 1419 */ + 9, + /* SHRD16rrCL */ + }, + { /* 1420 */ + 129, + /* SHRD16rri8 */ + }, + { /* 1421 */ + 5, + /* SHRD32mrCL */ + }, + { /* 1422 */ + 128, + /* SHRD32mri8 */ + }, + { /* 1423 */ + 9, + /* SHRD32rrCL */ + }, + { /* 1424 */ + 129, + /* SHRD32rri8 */ + }, + { /* 1425 */ + 13, + /* SHRD64mrCL */ + }, + { /* 1426 */ + 130, + /* SHRD64mri8 */ + }, + { /* 1427 */ + 17, + /* SHRD64rrCL */ + }, + { /* 1428 */ + 131, + /* SHRD64rri8 */ + }, + { /* 1429 */ + 32, + /* SHRX32rm */ + }, + { /* 1430 */ + 33, + /* SHRX32rr */ + }, + { /* 1431 */ + 34, + /* SHRX64rm */ + }, + { /* 1432 */ + 35, + /* SHRX64rr */ + }, + { /* 1433 */ + 54, + /* SIDT16m */ + }, + { /* 1434 */ + 54, + /* SIDT32m */ + }, + { /* 1435 */ + 54, + /* SIDT64m */ + }, + { /* 1436 */ + 0, + /* SKINIT */ + }, + { /* 1437 */ + 54, + /* SLDT16m */ + }, + { /* 1438 */ + 55, + /* SLDT16r */ + }, + { /* 1439 */ + 55, + /* SLDT32r */ + }, + { /* 1440 */ + 57, + /* SLDT64r */ + }, + { /* 1441 */ + 80, + /* SLWPCB */ + }, + { /* 1442 */ + 57, + /* SLWPCB64 */ + }, + { /* 1443 */ + 54, + /* SMSW16m */ + }, + { /* 1444 */ + 55, + /* SMSW16r */ + }, + { /* 1445 */ + 55, + /* SMSW32r */ + }, + { /* 1446 */ + 57, + /* SMSW64r */ + }, + { /* 1447 */ + 0, + /* STAC */ + }, + { /* 1448 */ + 0, + /* STC */ + }, + { /* 1449 */ + 0, + /* STD */ + }, + { /* 1450 */ + 0, + /* STGI */ + }, + { /* 1451 */ + 0, + /* STI */ + }, + { /* 1452 */ + 81, + /* STOSB */ + }, + { /* 1453 */ + 81, + /* STOSL */ + }, + { /* 1454 */ + 81, + /* STOSQ */ + }, + { /* 1455 */ + 81, + /* STOSW */ + }, + { /* 1456 */ + 55, + /* STR16r */ + }, + { /* 1457 */ + 55, + /* STR32r */ + }, + { /* 1458 */ + 57, + /* STR64r */ + }, + { /* 1459 */ + 54, + /* STRm */ + }, + { /* 1460 */ + 2, + /* SUB16i16 */ + }, + { /* 1461 */ + 3, + /* SUB16mi */ + }, + { /* 1462 */ + 4, + /* SUB16mi8 */ + }, + { /* 1463 */ + 5, + /* SUB16mr */ + }, + { /* 1464 */ + 6, + /* SUB16ri */ + }, + { /* 1465 */ + 7, + /* SUB16ri8 */ + }, + { /* 1466 */ + 8, + /* SUB16rm */ + }, + { /* 1467 */ + 9, + /* SUB16rr */ + }, + { /* 1468 */ + 10, + /* SUB16rr_REV */ + }, + { /* 1469 */ + 2, + /* SUB32i32 */ + }, + { /* 1470 */ + 3, + /* SUB32mi */ + }, + { /* 1471 */ + 4, + /* SUB32mi8 */ + }, + { /* 1472 */ + 5, + /* SUB32mr */ + }, + { /* 1473 */ + 6, + /* SUB32ri */ + }, + { /* 1474 */ + 7, + /* SUB32ri8 */ + }, + { /* 1475 */ + 8, + /* SUB32rm */ + }, + { /* 1476 */ + 9, + /* SUB32rr */ + }, + { /* 1477 */ + 10, + /* SUB32rr_REV */ + }, + { /* 1478 */ + 11, + /* SUB64i32 */ + }, + { /* 1479 */ + 12, + /* SUB64mi32 */ + }, + { /* 1480 */ + 4, + /* SUB64mi8 */ + }, + { /* 1481 */ + 13, + /* SUB64mr */ + }, + { /* 1482 */ + 14, + /* SUB64ri32 */ + }, + { /* 1483 */ + 15, + /* SUB64ri8 */ + }, + { /* 1484 */ + 16, + /* SUB64rm */ + }, + { /* 1485 */ + 17, + /* SUB64rr */ + }, + { /* 1486 */ + 18, + /* SUB64rr_REV */ + }, + { /* 1487 */ + 1, + /* SUB8i8 */ + }, + { /* 1488 */ + 4, + /* SUB8mi */ + }, + { /* 1489 */ + 4, + /* SUB8mi8 */ + }, + { /* 1490 */ + 19, + /* SUB8mr */ + }, + { /* 1491 */ + 20, + /* SUB8ri */ + }, + { /* 1492 */ + 20, + /* SUB8ri8 */ + }, + { /* 1493 */ + 21, + /* SUB8rm */ + }, + { /* 1494 */ + 22, + /* SUB8rr */ + }, + { /* 1495 */ + 23, + /* SUB8rr_REV */ + }, + { /* 1496 */ + 0, + /* SWAPGS */ + }, + { /* 1497 */ + 0, + /* SYSCALL */ + }, + { /* 1498 */ + 0, + /* SYSENTER */ + }, + { /* 1499 */ + 0, + /* SYSEXIT */ + }, + { /* 1500 */ + 0, + /* SYSEXIT64 */ + }, + { /* 1501 */ + 0, + /* SYSRET */ + }, + { /* 1502 */ + 0, + /* SYSRET64 */ + }, + { /* 1503 */ + 40, + /* T1MSKC32rm */ + }, + { /* 1504 */ + 41, + /* T1MSKC32rr */ + }, + { /* 1505 */ + 42, + /* T1MSKC64rm */ + }, + { /* 1506 */ + 43, + /* T1MSKC64rr */ + }, + { /* 1507 */ + 2, + /* TEST16i16 */ + }, + { /* 1508 */ + 3, + /* TEST16mi */ + }, + { /* 1509 */ + 3, + /* TEST16mi_alt */ + }, + { /* 1510 */ + 5, + /* TEST16mr */ + }, + { /* 1511 */ + 59, + /* TEST16ri */ + }, + { /* 1512 */ + 59, + /* TEST16ri_alt */ + }, + { /* 1513 */ + 51, + /* TEST16rr */ + }, + { /* 1514 */ + 2, + /* TEST32i32 */ + }, + { /* 1515 */ + 3, + /* TEST32mi */ + }, + { /* 1516 */ + 3, + /* TEST32mi_alt */ + }, + { /* 1517 */ + 5, + /* TEST32mr */ + }, + { /* 1518 */ + 59, + /* TEST32ri */ + }, + { /* 1519 */ + 59, + /* TEST32ri_alt */ + }, + { /* 1520 */ + 51, + /* TEST32rr */ + }, + { /* 1521 */ + 11, + /* TEST64i32 */ + }, + { /* 1522 */ + 12, + /* TEST64mi32 */ + }, + { /* 1523 */ + 12, + /* TEST64mi32_alt */ + }, + { /* 1524 */ + 13, + /* TEST64mr */ + }, + { /* 1525 */ + 60, + /* TEST64ri32 */ + }, + { /* 1526 */ + 60, + /* TEST64ri32_alt */ + }, + { /* 1527 */ + 53, + /* TEST64rr */ + }, + { /* 1528 */ + 1, + /* TEST8i8 */ + }, + { /* 1529 */ + 4, + /* TEST8mi */ + }, + { /* 1530 */ + 4, + /* TEST8mi_alt */ + }, + { /* 1531 */ + 19, + /* TEST8mr */ + }, + { /* 1532 */ + 61, + /* TEST8ri */ + }, + { /* 1533 */ + 61, + /* TEST8ri_alt */ + }, + { /* 1534 */ + 63, + /* TEST8rr */ + }, + { /* 1535 */ + 80, + /* TPAUSE */ + }, + { /* 1536 */ + 44, + /* TZCNT16rm */ + }, + { /* 1537 */ + 45, + /* TZCNT16rr */ + }, + { /* 1538 */ + 44, + /* TZCNT32rm */ + }, + { /* 1539 */ + 45, + /* TZCNT32rr */ + }, + { /* 1540 */ + 46, + /* TZCNT64rm */ + }, + { /* 1541 */ + 47, + /* TZCNT64rr */ + }, + { /* 1542 */ + 40, + /* TZMSK32rm */ + }, + { /* 1543 */ + 41, + /* TZMSK32rr */ + }, + { /* 1544 */ + 42, + /* TZMSK64rm */ + }, + { /* 1545 */ + 43, + /* TZMSK64rr */ + }, + { /* 1546 */ + 0, + /* UD0 */ + }, + { /* 1547 */ + 0, + /* UD1 */ + }, + { /* 1548 */ + 0, + /* UD2 */ + }, + { /* 1549 */ + 86, + /* UMONITOR16 */ + }, + { /* 1550 */ + 80, + /* UMONITOR32 */ + }, + { /* 1551 */ + 57, + /* UMONITOR64 */ + }, + { /* 1552 */ + 80, + /* UMWAIT */ + }, + { /* 1553 */ + 54, + /* VERRm */ + }, + { /* 1554 */ + 86, + /* VERRr */ + }, + { /* 1555 */ + 54, + /* VERWm */ + }, + { /* 1556 */ + 86, + /* VERWr */ + }, + { /* 1557 */ + 0, + /* VMCALL */ + }, + { /* 1558 */ + 54, + /* VMCLEARm */ + }, + { /* 1559 */ + 0, + /* VMFUNC */ + }, + { /* 1560 */ + 0, + /* VMLAUNCH */ + }, + { /* 1561 */ + 0, + /* VMLOAD32 */ + }, + { /* 1562 */ + 0, + /* VMLOAD64 */ + }, + { /* 1563 */ + 0, + /* VMMCALL */ + }, + { /* 1564 */ + 54, + /* VMPTRLDm */ + }, + { /* 1565 */ + 54, + /* VMPTRSTm */ + }, + { /* 1566 */ + 112, + /* VMREAD32mr */ + }, + { /* 1567 */ + 132, + /* VMREAD32rr */ + }, + { /* 1568 */ + 13, + /* VMREAD64mr */ + }, + { /* 1569 */ + 53, + /* VMREAD64rr */ + }, + { /* 1570 */ + 0, + /* VMRESUME */ + }, + { /* 1571 */ + 0, + /* VMRUN32 */ + }, + { /* 1572 */ + 0, + /* VMRUN64 */ + }, + { /* 1573 */ + 0, + /* VMSAVE32 */ + }, + { /* 1574 */ + 0, + /* VMSAVE64 */ + }, + { /* 1575 */ + 82, + /* VMWRITE32rm */ + }, + { /* 1576 */ + 133, + /* VMWRITE32rr */ + }, + { /* 1577 */ + 46, + /* VMWRITE64rm */ + }, + { /* 1578 */ + 47, + /* VMWRITE64rr */ + }, + { /* 1579 */ + 0, + /* VMXOFF */ + }, + { /* 1580 */ + 54, + /* VMXON */ + }, + { /* 1581 */ + 0, + /* WBINVD */ + }, + { /* 1582 */ + 0, + /* WBNOINVD */ + }, + { /* 1583 */ + 80, + /* WRFSBASE */ + }, + { /* 1584 */ + 57, + /* WRFSBASE64 */ + }, + { /* 1585 */ + 80, + /* WRGSBASE */ + }, + { /* 1586 */ + 57, + /* WRGSBASE64 */ + }, + { /* 1587 */ + 0, + /* WRMSR */ + }, + { /* 1588 */ + 0, + /* WRPKRUr */ + }, + { /* 1589 */ + 112, + /* WRSSD */ + }, + { /* 1590 */ + 13, + /* WRSSQ */ + }, + { /* 1591 */ + 112, + /* WRUSSD */ + }, + { /* 1592 */ + 13, + /* WRUSSQ */ + }, + { /* 1593 */ + 8, + /* XADD16rm */ + }, + { /* 1594 */ + 134, + /* XADD16rr */ + }, + { /* 1595 */ + 8, + /* XADD32rm */ + }, + { /* 1596 */ + 134, + /* XADD32rr */ + }, + { /* 1597 */ + 16, + /* XADD64rm */ + }, + { /* 1598 */ + 135, + /* XADD64rr */ + }, + { /* 1599 */ + 21, + /* XADD8rm */ + }, + { /* 1600 */ + 136, + /* XADD8rr */ + }, + { /* 1601 */ + 48, + /* XCHG16ar */ + }, + { /* 1602 */ + 8, + /* XCHG16rm */ + }, + { /* 1603 */ + 137, + /* XCHG16rr */ + }, + { /* 1604 */ + 48, + /* XCHG32ar */ + }, + { /* 1605 */ + 8, + /* XCHG32rm */ + }, + { /* 1606 */ + 137, + /* XCHG32rr */ + }, + { /* 1607 */ + 49, + /* XCHG64ar */ + }, + { /* 1608 */ + 16, + /* XCHG64rm */ + }, + { /* 1609 */ + 138, + /* XCHG64rr */ + }, + { /* 1610 */ + 21, + /* XCHG8rm */ + }, + { /* 1611 */ + 139, + /* XCHG8rr */ + }, + { /* 1612 */ + 0, + /* XCRYPTCBC */ + }, + { /* 1613 */ + 0, + /* XCRYPTCFB */ + }, + { /* 1614 */ + 0, + /* XCRYPTCTR */ + }, + { /* 1615 */ + 0, + /* XCRYPTECB */ + }, + { /* 1616 */ + 0, + /* XCRYPTOFB */ + }, + { /* 1617 */ + 0, + /* XGETBV */ + }, + { /* 1618 */ + 0, + /* XLAT */ + }, + { /* 1619 */ + 2, + /* XOR16i16 */ + }, + { /* 1620 */ + 3, + /* XOR16mi */ + }, + { /* 1621 */ + 4, + /* XOR16mi8 */ + }, + { /* 1622 */ + 5, + /* XOR16mr */ + }, + { /* 1623 */ + 6, + /* XOR16ri */ + }, + { /* 1624 */ + 7, + /* XOR16ri8 */ + }, + { /* 1625 */ + 8, + /* XOR16rm */ + }, + { /* 1626 */ + 9, + /* XOR16rr */ + }, + { /* 1627 */ + 10, + /* XOR16rr_REV */ + }, + { /* 1628 */ + 2, + /* XOR32i32 */ + }, + { /* 1629 */ + 3, + /* XOR32mi */ + }, + { /* 1630 */ + 4, + /* XOR32mi8 */ + }, + { /* 1631 */ + 5, + /* XOR32mr */ + }, + { /* 1632 */ + 6, + /* XOR32ri */ + }, + { /* 1633 */ + 7, + /* XOR32ri8 */ + }, + { /* 1634 */ + 8, + /* XOR32rm */ + }, + { /* 1635 */ + 9, + /* XOR32rr */ + }, + { /* 1636 */ + 10, + /* XOR32rr_REV */ + }, + { /* 1637 */ + 11, + /* XOR64i32 */ + }, + { /* 1638 */ + 12, + /* XOR64mi32 */ + }, + { /* 1639 */ + 4, + /* XOR64mi8 */ + }, + { /* 1640 */ + 13, + /* XOR64mr */ + }, + { /* 1641 */ + 14, + /* XOR64ri32 */ + }, + { /* 1642 */ + 15, + /* XOR64ri8 */ + }, + { /* 1643 */ + 16, + /* XOR64rm */ + }, + { /* 1644 */ + 17, + /* XOR64rr */ + }, + { /* 1645 */ + 18, + /* XOR64rr_REV */ + }, + { /* 1646 */ + 1, + /* XOR8i8 */ + }, + { /* 1647 */ + 4, + /* XOR8mi */ + }, + { /* 1648 */ + 4, + /* XOR8mi8 */ + }, + { /* 1649 */ + 19, + /* XOR8mr */ + }, + { /* 1650 */ + 20, + /* XOR8ri */ + }, + { /* 1651 */ + 20, + /* XOR8ri8 */ + }, + { /* 1652 */ + 21, + /* XOR8rm */ + }, + { /* 1653 */ + 22, + /* XOR8rr */ + }, + { /* 1654 */ + 23, + /* XOR8rr_REV */ + }, + { /* 1655 */ + 54, + /* XRSTOR */ + }, + { /* 1656 */ + 54, + /* XRSTOR64 */ + }, + { /* 1657 */ + 54, + /* XRSTORS */ + }, + { /* 1658 */ + 54, + /* XRSTORS64 */ + }, + { /* 1659 */ + 54, + /* XSAVE */ + }, + { /* 1660 */ + 54, + /* XSAVE64 */ + }, + { /* 1661 */ + 54, + /* XSAVEC */ + }, + { /* 1662 */ + 54, + /* XSAVEC64 */ + }, + { /* 1663 */ + 54, + /* XSAVEOPT */ + }, + { /* 1664 */ + 54, + /* XSAVEOPT64 */ + }, + { /* 1665 */ + 54, + /* XSAVES */ + }, + { /* 1666 */ + 54, + /* XSAVES64 */ + }, + { /* 1667 */ + 0, + /* XSETBV */ + }, + { /* 1668 */ + 0, + /* XSHA1 */ + }, + { /* 1669 */ + 0, + /* XSHA256 */ + }, + { /* 1670 */ + 0, + /* XSTORE */ + }, +}; + +static const uint8_t x86DisassemblerContexts[16384] = { + IC, /* 0 */ + IC_64BIT, /* 1 */ + IC_XS, /* 2 */ + IC_64BIT_XS, /* 3 */ + IC_XD, /* 4 */ + IC_64BIT_XD, /* 5 */ + IC_XS, /* 6 */ + IC_64BIT_XS, /* 7 */ + IC, /* 8 */ + IC_64BIT_REXW, /* 9 */ + IC_XS, /* 10 */ + IC_64BIT_REXW_XS, /* 11 */ + IC_XD, /* 12 */ + IC_64BIT_REXW_XD, /* 13 */ + IC_XS, /* 14 */ + IC_64BIT_REXW_XS, /* 15 */ + IC_OPSIZE, /* 16 */ + IC_64BIT_OPSIZE, /* 17 */ + IC_XS_OPSIZE, /* 18 */ + IC_64BIT_XS_OPSIZE, /* 19 */ + IC_XD_OPSIZE, /* 20 */ + IC_64BIT_XD_OPSIZE, /* 21 */ + IC_XS_OPSIZE, /* 22 */ + IC_64BIT_XD_OPSIZE, /* 23 */ + IC_OPSIZE, /* 24 */ + IC_64BIT_REXW_OPSIZE, /* 25 */ + IC_XS_OPSIZE, /* 26 */ + IC_64BIT_REXW_XS, /* 27 */ + IC_XD_OPSIZE, /* 28 */ + IC_64BIT_REXW_XD, /* 29 */ + IC_XS_OPSIZE, /* 30 */ + IC_64BIT_REXW_XS, /* 31 */ + IC_ADSIZE, /* 32 */ + IC_64BIT_ADSIZE, /* 33 */ + IC_XS_ADSIZE, /* 34 */ + IC_64BIT_XS_ADSIZE, /* 35 */ + IC_XD_ADSIZE, /* 36 */ + IC_64BIT_XD_ADSIZE, /* 37 */ + IC_XS_ADSIZE, /* 38 */ + IC_64BIT_XD_ADSIZE, /* 39 */ + IC_ADSIZE, /* 40 */ + IC_64BIT_REXW_ADSIZE, /* 41 */ + IC_XS_ADSIZE, /* 42 */ + IC_64BIT_REXW_XS, /* 43 */ + IC_XD_ADSIZE, /* 44 */ + IC_64BIT_REXW_XD, /* 45 */ + IC_XS_ADSIZE, /* 46 */ + IC_64BIT_REXW_XS, /* 47 */ + IC_OPSIZE_ADSIZE, /* 48 */ + IC_64BIT_OPSIZE_ADSIZE, /* 49 */ + IC_XS_OPSIZE, /* 50 */ + IC_64BIT_XS_OPSIZE, /* 51 */ + IC_XD_OPSIZE, /* 52 */ + IC_64BIT_XD_OPSIZE, /* 53 */ + IC_XS_OPSIZE, /* 54 */ + IC_64BIT_XD_OPSIZE, /* 55 */ + IC_OPSIZE_ADSIZE, /* 56 */ + IC_64BIT_REXW_OPSIZE, /* 57 */ + IC_XS_OPSIZE, /* 58 */ + IC_64BIT_REXW_XS, /* 59 */ + IC_XD_OPSIZE, /* 60 */ + IC_64BIT_REXW_XD, /* 61 */ + IC_XS_OPSIZE, /* 62 */ + IC_64BIT_REXW_XS, /* 63 */ + IC_VEX, /* 64 */ + IC_VEX, /* 65 */ + IC_VEX_XS, /* 66 */ + IC_VEX_XS, /* 67 */ + IC_VEX_XD, /* 68 */ + IC_VEX_XD, /* 69 */ + IC_VEX_XD, /* 70 */ + IC_VEX_XD, /* 71 */ + IC_VEX_W, /* 72 */ + IC_VEX_W, /* 73 */ + IC_VEX_W_XS, /* 74 */ + IC_VEX_W_XS, /* 75 */ + IC_VEX_W_XD, /* 76 */ + IC_VEX_W_XD, /* 77 */ + IC_VEX_W_XD, /* 78 */ + IC_VEX_W_XD, /* 79 */ + IC_VEX_OPSIZE, /* 80 */ + IC_VEX_OPSIZE, /* 81 */ + IC_VEX_OPSIZE, /* 82 */ + IC_VEX_OPSIZE, /* 83 */ + IC_VEX_OPSIZE, /* 84 */ + IC_VEX_OPSIZE, /* 85 */ + IC_VEX_OPSIZE, /* 86 */ + IC_VEX_OPSIZE, /* 87 */ + IC_VEX_W_OPSIZE, /* 88 */ + IC_VEX_W_OPSIZE, /* 89 */ + IC_VEX_W_OPSIZE, /* 90 */ + IC_VEX_W_OPSIZE, /* 91 */ + IC_VEX_W_OPSIZE, /* 92 */ + IC_VEX_W_OPSIZE, /* 93 */ + IC_VEX_W_OPSIZE, /* 94 */ + IC_VEX_W_OPSIZE, /* 95 */ + IC_VEX, /* 96 */ + IC_VEX, /* 97 */ + IC_VEX_XS, /* 98 */ + IC_VEX_XS, /* 99 */ + IC_VEX_XD, /* 100 */ + IC_VEX_XD, /* 101 */ + IC_VEX_XD, /* 102 */ + IC_VEX_XD, /* 103 */ + IC_VEX_W, /* 104 */ + IC_VEX_W, /* 105 */ + IC_VEX_W_XS, /* 106 */ + IC_VEX_W_XS, /* 107 */ + IC_VEX_W_XD, /* 108 */ + IC_VEX_W_XD, /* 109 */ + IC_VEX_W_XD, /* 110 */ + IC_VEX_W_XD, /* 111 */ + IC_VEX_OPSIZE, /* 112 */ + IC_VEX_OPSIZE, /* 113 */ + IC_VEX_OPSIZE, /* 114 */ + IC_VEX_OPSIZE, /* 115 */ + IC_VEX_OPSIZE, /* 116 */ + IC_VEX_OPSIZE, /* 117 */ + IC_VEX_OPSIZE, /* 118 */ + IC_VEX_OPSIZE, /* 119 */ + IC_VEX_W_OPSIZE, /* 120 */ + IC_VEX_W_OPSIZE, /* 121 */ + IC_VEX_W_OPSIZE, /* 122 */ + IC_VEX_W_OPSIZE, /* 123 */ + IC_VEX_W_OPSIZE, /* 124 */ + IC_VEX_W_OPSIZE, /* 125 */ + IC_VEX_W_OPSIZE, /* 126 */ + IC_VEX_W_OPSIZE, /* 127 */ + IC_VEX_L, /* 128 */ + IC_VEX_L, /* 129 */ + IC_VEX_L_XS, /* 130 */ + IC_VEX_L_XS, /* 131 */ + IC_VEX_L_XD, /* 132 */ + IC_VEX_L_XD, /* 133 */ + IC_VEX_L_XD, /* 134 */ + IC_VEX_L_XD, /* 135 */ + IC_VEX_L_W, /* 136 */ + IC_VEX_L_W, /* 137 */ + IC_VEX_L_W_XS, /* 138 */ + IC_VEX_L_W_XS, /* 139 */ + IC_VEX_L_W_XD, /* 140 */ + IC_VEX_L_W_XD, /* 141 */ + IC_VEX_L_W_XD, /* 142 */ + IC_VEX_L_W_XD, /* 143 */ + IC_VEX_L_OPSIZE, /* 144 */ + IC_VEX_L_OPSIZE, /* 145 */ + IC_VEX_L_OPSIZE, /* 146 */ + IC_VEX_L_OPSIZE, /* 147 */ + IC_VEX_L_OPSIZE, /* 148 */ + IC_VEX_L_OPSIZE, /* 149 */ + IC_VEX_L_OPSIZE, /* 150 */ + IC_VEX_L_OPSIZE, /* 151 */ + IC_VEX_L_W_OPSIZE, /* 152 */ + IC_VEX_L_W_OPSIZE, /* 153 */ + IC_VEX_L_W_OPSIZE, /* 154 */ + IC_VEX_L_W_OPSIZE, /* 155 */ + IC_VEX_L_W_OPSIZE, /* 156 */ + IC_VEX_L_W_OPSIZE, /* 157 */ + IC_VEX_L_W_OPSIZE, /* 158 */ + IC_VEX_L_W_OPSIZE, /* 159 */ + IC_VEX_L, /* 160 */ + IC_VEX_L, /* 161 */ + IC_VEX_L_XS, /* 162 */ + IC_VEX_L_XS, /* 163 */ + IC_VEX_L_XD, /* 164 */ + IC_VEX_L_XD, /* 165 */ + IC_VEX_L_XD, /* 166 */ + IC_VEX_L_XD, /* 167 */ + IC_VEX_L_W, /* 168 */ + IC_VEX_L_W, /* 169 */ + IC_VEX_L_W_XS, /* 170 */ + IC_VEX_L_W_XS, /* 171 */ + IC_VEX_L_W_XD, /* 172 */ + IC_VEX_L_W_XD, /* 173 */ + IC_VEX_L_W_XD, /* 174 */ + IC_VEX_L_W_XD, /* 175 */ + IC_VEX_L_OPSIZE, /* 176 */ + IC_VEX_L_OPSIZE, /* 177 */ + IC_VEX_L_OPSIZE, /* 178 */ + IC_VEX_L_OPSIZE, /* 179 */ + IC_VEX_L_OPSIZE, /* 180 */ + IC_VEX_L_OPSIZE, /* 181 */ + IC_VEX_L_OPSIZE, /* 182 */ + IC_VEX_L_OPSIZE, /* 183 */ + IC_VEX_L_W_OPSIZE, /* 184 */ + IC_VEX_L_W_OPSIZE, /* 185 */ + IC_VEX_L_W_OPSIZE, /* 186 */ + IC_VEX_L_W_OPSIZE, /* 187 */ + IC_VEX_L_W_OPSIZE, /* 188 */ + IC_VEX_L_W_OPSIZE, /* 189 */ + IC_VEX_L_W_OPSIZE, /* 190 */ + IC_VEX_L_W_OPSIZE, /* 191 */ + IC_VEX_L, /* 192 */ + IC_VEX_L, /* 193 */ + IC_VEX_L_XS, /* 194 */ + IC_VEX_L_XS, /* 195 */ + IC_VEX_L_XD, /* 196 */ + IC_VEX_L_XD, /* 197 */ + IC_VEX_L_XD, /* 198 */ + IC_VEX_L_XD, /* 199 */ + IC_VEX_L_W, /* 200 */ + IC_VEX_L_W, /* 201 */ + IC_VEX_L_W_XS, /* 202 */ + IC_VEX_L_W_XS, /* 203 */ + IC_VEX_L_W_XD, /* 204 */ + IC_VEX_L_W_XD, /* 205 */ + IC_VEX_L_W_XD, /* 206 */ + IC_VEX_L_W_XD, /* 207 */ + IC_VEX_L_OPSIZE, /* 208 */ + IC_VEX_L_OPSIZE, /* 209 */ + IC_VEX_L_OPSIZE, /* 210 */ + IC_VEX_L_OPSIZE, /* 211 */ + IC_VEX_L_OPSIZE, /* 212 */ + IC_VEX_L_OPSIZE, /* 213 */ + IC_VEX_L_OPSIZE, /* 214 */ + IC_VEX_L_OPSIZE, /* 215 */ + IC_VEX_L_W_OPSIZE, /* 216 */ + IC_VEX_L_W_OPSIZE, /* 217 */ + IC_VEX_L_W_OPSIZE, /* 218 */ + IC_VEX_L_W_OPSIZE, /* 219 */ + IC_VEX_L_W_OPSIZE, /* 220 */ + IC_VEX_L_W_OPSIZE, /* 221 */ + IC_VEX_L_W_OPSIZE, /* 222 */ + IC_VEX_L_W_OPSIZE, /* 223 */ + IC_VEX_L, /* 224 */ + IC_VEX_L, /* 225 */ + IC_VEX_L_XS, /* 226 */ + IC_VEX_L_XS, /* 227 */ + IC_VEX_L_XD, /* 228 */ + IC_VEX_L_XD, /* 229 */ + IC_VEX_L_XD, /* 230 */ + IC_VEX_L_XD, /* 231 */ + IC_VEX_L_W, /* 232 */ + IC_VEX_L_W, /* 233 */ + IC_VEX_L_W_XS, /* 234 */ + IC_VEX_L_W_XS, /* 235 */ + IC_VEX_L_W_XD, /* 236 */ + IC_VEX_L_W_XD, /* 237 */ + IC_VEX_L_W_XD, /* 238 */ + IC_VEX_L_W_XD, /* 239 */ + IC_VEX_L_OPSIZE, /* 240 */ + IC_VEX_L_OPSIZE, /* 241 */ + IC_VEX_L_OPSIZE, /* 242 */ + IC_VEX_L_OPSIZE, /* 243 */ + IC_VEX_L_OPSIZE, /* 244 */ + IC_VEX_L_OPSIZE, /* 245 */ + IC_VEX_L_OPSIZE, /* 246 */ + IC_VEX_L_OPSIZE, /* 247 */ + IC_VEX_L_W_OPSIZE, /* 248 */ + IC_VEX_L_W_OPSIZE, /* 249 */ + IC_VEX_L_W_OPSIZE, /* 250 */ + IC_VEX_L_W_OPSIZE, /* 251 */ + IC_VEX_L_W_OPSIZE, /* 252 */ + IC_VEX_L_W_OPSIZE, /* 253 */ + IC_VEX_L_W_OPSIZE, /* 254 */ + IC_VEX_L_W_OPSIZE, /* 255 */ + IC_EVEX, /* 256 */ + IC_EVEX, /* 257 */ + IC_EVEX_XS, /* 258 */ + IC_EVEX_XS, /* 259 */ + IC_EVEX_XD, /* 260 */ + IC_EVEX_XD, /* 261 */ + IC_EVEX_XD, /* 262 */ + IC_EVEX_XD, /* 263 */ + IC_EVEX_W, /* 264 */ + IC_EVEX_W, /* 265 */ + IC_EVEX_W_XS, /* 266 */ + IC_EVEX_W_XS, /* 267 */ + IC_EVEX_W_XD, /* 268 */ + IC_EVEX_W_XD, /* 269 */ + IC_EVEX_W_XD, /* 270 */ + IC_EVEX_W_XD, /* 271 */ + IC_EVEX_OPSIZE, /* 272 */ + IC_EVEX_OPSIZE, /* 273 */ + IC_EVEX_OPSIZE, /* 274 */ + IC_EVEX_OPSIZE, /* 275 */ + IC_EVEX_OPSIZE, /* 276 */ + IC_EVEX_OPSIZE, /* 277 */ + IC_EVEX_OPSIZE, /* 278 */ + IC_EVEX_OPSIZE, /* 279 */ + IC_EVEX_W_OPSIZE, /* 280 */ + IC_EVEX_W_OPSIZE, /* 281 */ + IC_EVEX_W_OPSIZE, /* 282 */ + IC_EVEX_W_OPSIZE, /* 283 */ + IC_EVEX_W_OPSIZE, /* 284 */ + IC_EVEX_W_OPSIZE, /* 285 */ + IC_EVEX_W_OPSIZE, /* 286 */ + IC_EVEX_W_OPSIZE, /* 287 */ + IC_EVEX, /* 288 */ + IC_EVEX, /* 289 */ + IC_EVEX_XS, /* 290 */ + IC_EVEX_XS, /* 291 */ + IC_EVEX_XD, /* 292 */ + IC_EVEX_XD, /* 293 */ + IC_EVEX_XD, /* 294 */ + IC_EVEX_XD, /* 295 */ + IC_EVEX_W, /* 296 */ + IC_EVEX_W, /* 297 */ + IC_EVEX_W_XS, /* 298 */ + IC_EVEX_W_XS, /* 299 */ + IC_EVEX_W_XD, /* 300 */ + IC_EVEX_W_XD, /* 301 */ + IC_EVEX_W_XD, /* 302 */ + IC_EVEX_W_XD, /* 303 */ + IC_EVEX_OPSIZE, /* 304 */ + IC_EVEX_OPSIZE, /* 305 */ + IC_EVEX_OPSIZE, /* 306 */ + IC_EVEX_OPSIZE, /* 307 */ + IC_EVEX_OPSIZE, /* 308 */ + IC_EVEX_OPSIZE, /* 309 */ + IC_EVEX_OPSIZE, /* 310 */ + IC_EVEX_OPSIZE, /* 311 */ + IC_EVEX_W_OPSIZE, /* 312 */ + IC_EVEX_W_OPSIZE, /* 313 */ + IC_EVEX_W_OPSIZE, /* 314 */ + IC_EVEX_W_OPSIZE, /* 315 */ + IC_EVEX_W_OPSIZE, /* 316 */ + IC_EVEX_W_OPSIZE, /* 317 */ + IC_EVEX_W_OPSIZE, /* 318 */ + IC_EVEX_W_OPSIZE, /* 319 */ + IC_EVEX, /* 320 */ + IC_EVEX, /* 321 */ + IC_EVEX_XS, /* 322 */ + IC_EVEX_XS, /* 323 */ + IC_EVEX_XD, /* 324 */ + IC_EVEX_XD, /* 325 */ + IC_EVEX_XD, /* 326 */ + IC_EVEX_XD, /* 327 */ + IC_EVEX_W, /* 328 */ + IC_EVEX_W, /* 329 */ + IC_EVEX_W_XS, /* 330 */ + IC_EVEX_W_XS, /* 331 */ + IC_EVEX_W_XD, /* 332 */ + IC_EVEX_W_XD, /* 333 */ + IC_EVEX_W_XD, /* 334 */ + IC_EVEX_W_XD, /* 335 */ + IC_EVEX_OPSIZE, /* 336 */ + IC_EVEX_OPSIZE, /* 337 */ + IC_EVEX_OPSIZE, /* 338 */ + IC_EVEX_OPSIZE, /* 339 */ + IC_EVEX_OPSIZE, /* 340 */ + IC_EVEX_OPSIZE, /* 341 */ + IC_EVEX_OPSIZE, /* 342 */ + IC_EVEX_OPSIZE, /* 343 */ + IC_EVEX_W_OPSIZE, /* 344 */ + IC_EVEX_W_OPSIZE, /* 345 */ + IC_EVEX_W_OPSIZE, /* 346 */ + IC_EVEX_W_OPSIZE, /* 347 */ + IC_EVEX_W_OPSIZE, /* 348 */ + IC_EVEX_W_OPSIZE, /* 349 */ + IC_EVEX_W_OPSIZE, /* 350 */ + IC_EVEX_W_OPSIZE, /* 351 */ + IC_EVEX, /* 352 */ + IC_EVEX, /* 353 */ + IC_EVEX_XS, /* 354 */ + IC_EVEX_XS, /* 355 */ + IC_EVEX_XD, /* 356 */ + IC_EVEX_XD, /* 357 */ + IC_EVEX_XD, /* 358 */ + IC_EVEX_XD, /* 359 */ + IC_EVEX_W, /* 360 */ + IC_EVEX_W, /* 361 */ + IC_EVEX_W_XS, /* 362 */ + IC_EVEX_W_XS, /* 363 */ + IC_EVEX_W_XD, /* 364 */ + IC_EVEX_W_XD, /* 365 */ + IC_EVEX_W_XD, /* 366 */ + IC_EVEX_W_XD, /* 367 */ + IC_EVEX_OPSIZE, /* 368 */ + IC_EVEX_OPSIZE, /* 369 */ + IC_EVEX_OPSIZE, /* 370 */ + IC_EVEX_OPSIZE, /* 371 */ + IC_EVEX_OPSIZE, /* 372 */ + IC_EVEX_OPSIZE, /* 373 */ + IC_EVEX_OPSIZE, /* 374 */ + IC_EVEX_OPSIZE, /* 375 */ + IC_EVEX_W_OPSIZE, /* 376 */ + IC_EVEX_W_OPSIZE, /* 377 */ + IC_EVEX_W_OPSIZE, /* 378 */ + IC_EVEX_W_OPSIZE, /* 379 */ + IC_EVEX_W_OPSIZE, /* 380 */ + IC_EVEX_W_OPSIZE, /* 381 */ + IC_EVEX_W_OPSIZE, /* 382 */ + IC_EVEX_W_OPSIZE, /* 383 */ + IC_EVEX, /* 384 */ + IC_EVEX, /* 385 */ + IC_EVEX_XS, /* 386 */ + IC_EVEX_XS, /* 387 */ + IC_EVEX_XD, /* 388 */ + IC_EVEX_XD, /* 389 */ + IC_EVEX_XD, /* 390 */ + IC_EVEX_XD, /* 391 */ + IC_EVEX_W, /* 392 */ + IC_EVEX_W, /* 393 */ + IC_EVEX_W_XS, /* 394 */ + IC_EVEX_W_XS, /* 395 */ + IC_EVEX_W_XD, /* 396 */ + IC_EVEX_W_XD, /* 397 */ + IC_EVEX_W_XD, /* 398 */ + IC_EVEX_W_XD, /* 399 */ + IC_EVEX_OPSIZE, /* 400 */ + IC_EVEX_OPSIZE, /* 401 */ + IC_EVEX_OPSIZE, /* 402 */ + IC_EVEX_OPSIZE, /* 403 */ + IC_EVEX_OPSIZE, /* 404 */ + IC_EVEX_OPSIZE, /* 405 */ + IC_EVEX_OPSIZE, /* 406 */ + IC_EVEX_OPSIZE, /* 407 */ + IC_EVEX_W_OPSIZE, /* 408 */ + IC_EVEX_W_OPSIZE, /* 409 */ + IC_EVEX_W_OPSIZE, /* 410 */ + IC_EVEX_W_OPSIZE, /* 411 */ + IC_EVEX_W_OPSIZE, /* 412 */ + IC_EVEX_W_OPSIZE, /* 413 */ + IC_EVEX_W_OPSIZE, /* 414 */ + IC_EVEX_W_OPSIZE, /* 415 */ + IC_EVEX, /* 416 */ + IC_EVEX, /* 417 */ + IC_EVEX_XS, /* 418 */ + IC_EVEX_XS, /* 419 */ + IC_EVEX_XD, /* 420 */ + IC_EVEX_XD, /* 421 */ + IC_EVEX_XD, /* 422 */ + IC_EVEX_XD, /* 423 */ + IC_EVEX_W, /* 424 */ + IC_EVEX_W, /* 425 */ + IC_EVEX_W_XS, /* 426 */ + IC_EVEX_W_XS, /* 427 */ + IC_EVEX_W_XD, /* 428 */ + IC_EVEX_W_XD, /* 429 */ + IC_EVEX_W_XD, /* 430 */ + IC_EVEX_W_XD, /* 431 */ + IC_EVEX_OPSIZE, /* 432 */ + IC_EVEX_OPSIZE, /* 433 */ + IC_EVEX_OPSIZE, /* 434 */ + IC_EVEX_OPSIZE, /* 435 */ + IC_EVEX_OPSIZE, /* 436 */ + IC_EVEX_OPSIZE, /* 437 */ + IC_EVEX_OPSIZE, /* 438 */ + IC_EVEX_OPSIZE, /* 439 */ + IC_EVEX_W_OPSIZE, /* 440 */ + IC_EVEX_W_OPSIZE, /* 441 */ + IC_EVEX_W_OPSIZE, /* 442 */ + IC_EVEX_W_OPSIZE, /* 443 */ + IC_EVEX_W_OPSIZE, /* 444 */ + IC_EVEX_W_OPSIZE, /* 445 */ + IC_EVEX_W_OPSIZE, /* 446 */ + IC_EVEX_W_OPSIZE, /* 447 */ + IC_EVEX, /* 448 */ + IC_EVEX, /* 449 */ + IC_EVEX_XS, /* 450 */ + IC_EVEX_XS, /* 451 */ + IC_EVEX_XD, /* 452 */ + IC_EVEX_XD, /* 453 */ + IC_EVEX_XD, /* 454 */ + IC_EVEX_XD, /* 455 */ + IC_EVEX_W, /* 456 */ + IC_EVEX_W, /* 457 */ + IC_EVEX_W_XS, /* 458 */ + IC_EVEX_W_XS, /* 459 */ + IC_EVEX_W_XD, /* 460 */ + IC_EVEX_W_XD, /* 461 */ + IC_EVEX_W_XD, /* 462 */ + IC_EVEX_W_XD, /* 463 */ + IC_EVEX_OPSIZE, /* 464 */ + IC_EVEX_OPSIZE, /* 465 */ + IC_EVEX_OPSIZE, /* 466 */ + IC_EVEX_OPSIZE, /* 467 */ + IC_EVEX_OPSIZE, /* 468 */ + IC_EVEX_OPSIZE, /* 469 */ + IC_EVEX_OPSIZE, /* 470 */ + IC_EVEX_OPSIZE, /* 471 */ + IC_EVEX_W_OPSIZE, /* 472 */ + IC_EVEX_W_OPSIZE, /* 473 */ + IC_EVEX_W_OPSIZE, /* 474 */ + IC_EVEX_W_OPSIZE, /* 475 */ + IC_EVEX_W_OPSIZE, /* 476 */ + IC_EVEX_W_OPSIZE, /* 477 */ + IC_EVEX_W_OPSIZE, /* 478 */ + IC_EVEX_W_OPSIZE, /* 479 */ + IC_EVEX, /* 480 */ + IC_EVEX, /* 481 */ + IC_EVEX_XS, /* 482 */ + IC_EVEX_XS, /* 483 */ + IC_EVEX_XD, /* 484 */ + IC_EVEX_XD, /* 485 */ + IC_EVEX_XD, /* 486 */ + IC_EVEX_XD, /* 487 */ + IC_EVEX_W, /* 488 */ + IC_EVEX_W, /* 489 */ + IC_EVEX_W_XS, /* 490 */ + IC_EVEX_W_XS, /* 491 */ + IC_EVEX_W_XD, /* 492 */ + IC_EVEX_W_XD, /* 493 */ + IC_EVEX_W_XD, /* 494 */ + IC_EVEX_W_XD, /* 495 */ + IC_EVEX_OPSIZE, /* 496 */ + IC_EVEX_OPSIZE, /* 497 */ + IC_EVEX_OPSIZE, /* 498 */ + IC_EVEX_OPSIZE, /* 499 */ + IC_EVEX_OPSIZE, /* 500 */ + IC_EVEX_OPSIZE, /* 501 */ + IC_EVEX_OPSIZE, /* 502 */ + IC_EVEX_OPSIZE, /* 503 */ + IC_EVEX_W_OPSIZE, /* 504 */ + IC_EVEX_W_OPSIZE, /* 505 */ + IC_EVEX_W_OPSIZE, /* 506 */ + IC_EVEX_W_OPSIZE, /* 507 */ + IC_EVEX_W_OPSIZE, /* 508 */ + IC_EVEX_W_OPSIZE, /* 509 */ + IC_EVEX_W_OPSIZE, /* 510 */ + IC_EVEX_W_OPSIZE, /* 511 */ + IC, /* 512 */ + IC_64BIT, /* 513 */ + IC_XS, /* 514 */ + IC_64BIT_XS, /* 515 */ + IC_XD, /* 516 */ + IC_64BIT_XD, /* 517 */ + IC_XS, /* 518 */ + IC_64BIT_XS, /* 519 */ + IC, /* 520 */ + IC_64BIT_REXW, /* 521 */ + IC_XS, /* 522 */ + IC_64BIT_REXW_XS, /* 523 */ + IC_XD, /* 524 */ + IC_64BIT_REXW_XD, /* 525 */ + IC_XS, /* 526 */ + IC_64BIT_REXW_XS, /* 527 */ + IC_OPSIZE, /* 528 */ + IC_64BIT_OPSIZE, /* 529 */ + IC_XS_OPSIZE, /* 530 */ + IC_64BIT_XS_OPSIZE, /* 531 */ + IC_XD_OPSIZE, /* 532 */ + IC_64BIT_XD_OPSIZE, /* 533 */ + IC_XS_OPSIZE, /* 534 */ + IC_64BIT_XD_OPSIZE, /* 535 */ + IC_OPSIZE, /* 536 */ + IC_64BIT_REXW_OPSIZE, /* 537 */ + IC_XS_OPSIZE, /* 538 */ + IC_64BIT_REXW_XS, /* 539 */ + IC_XD_OPSIZE, /* 540 */ + IC_64BIT_REXW_XD, /* 541 */ + IC_XS_OPSIZE, /* 542 */ + IC_64BIT_REXW_XS, /* 543 */ + IC_ADSIZE, /* 544 */ + IC_64BIT_ADSIZE, /* 545 */ + IC_XS_ADSIZE, /* 546 */ + IC_64BIT_XS_ADSIZE, /* 547 */ + IC_XD_ADSIZE, /* 548 */ + IC_64BIT_XD_ADSIZE, /* 549 */ + IC_XS_ADSIZE, /* 550 */ + IC_64BIT_XD_ADSIZE, /* 551 */ + IC_ADSIZE, /* 552 */ + IC_64BIT_REXW_ADSIZE, /* 553 */ + IC_XS_ADSIZE, /* 554 */ + IC_64BIT_REXW_XS, /* 555 */ + IC_XD_ADSIZE, /* 556 */ + IC_64BIT_REXW_XD, /* 557 */ + IC_XS_ADSIZE, /* 558 */ + IC_64BIT_REXW_XS, /* 559 */ + IC_OPSIZE_ADSIZE, /* 560 */ + IC_64BIT_OPSIZE_ADSIZE, /* 561 */ + IC_XS_OPSIZE, /* 562 */ + IC_64BIT_XS_OPSIZE, /* 563 */ + IC_XD_OPSIZE, /* 564 */ + IC_64BIT_XD_OPSIZE, /* 565 */ + IC_XS_OPSIZE, /* 566 */ + IC_64BIT_XD_OPSIZE, /* 567 */ + IC_OPSIZE_ADSIZE, /* 568 */ + IC_64BIT_REXW_OPSIZE, /* 569 */ + IC_XS_OPSIZE, /* 570 */ + IC_64BIT_REXW_XS, /* 571 */ + IC_XD_OPSIZE, /* 572 */ + IC_64BIT_REXW_XD, /* 573 */ + IC_XS_OPSIZE, /* 574 */ + IC_64BIT_REXW_XS, /* 575 */ + IC_VEX, /* 576 */ + IC_VEX, /* 577 */ + IC_VEX_XS, /* 578 */ + IC_VEX_XS, /* 579 */ + IC_VEX_XD, /* 580 */ + IC_VEX_XD, /* 581 */ + IC_VEX_XD, /* 582 */ + IC_VEX_XD, /* 583 */ + IC_VEX_W, /* 584 */ + IC_VEX_W, /* 585 */ + IC_VEX_W_XS, /* 586 */ + IC_VEX_W_XS, /* 587 */ + IC_VEX_W_XD, /* 588 */ + IC_VEX_W_XD, /* 589 */ + IC_VEX_W_XD, /* 590 */ + IC_VEX_W_XD, /* 591 */ + IC_VEX_OPSIZE, /* 592 */ + IC_VEX_OPSIZE, /* 593 */ + IC_VEX_OPSIZE, /* 594 */ + IC_VEX_OPSIZE, /* 595 */ + IC_VEX_OPSIZE, /* 596 */ + IC_VEX_OPSIZE, /* 597 */ + IC_VEX_OPSIZE, /* 598 */ + IC_VEX_OPSIZE, /* 599 */ + IC_VEX_W_OPSIZE, /* 600 */ + IC_VEX_W_OPSIZE, /* 601 */ + IC_VEX_W_OPSIZE, /* 602 */ + IC_VEX_W_OPSIZE, /* 603 */ + IC_VEX_W_OPSIZE, /* 604 */ + IC_VEX_W_OPSIZE, /* 605 */ + IC_VEX_W_OPSIZE, /* 606 */ + IC_VEX_W_OPSIZE, /* 607 */ + IC_VEX, /* 608 */ + IC_VEX, /* 609 */ + IC_VEX_XS, /* 610 */ + IC_VEX_XS, /* 611 */ + IC_VEX_XD, /* 612 */ + IC_VEX_XD, /* 613 */ + IC_VEX_XD, /* 614 */ + IC_VEX_XD, /* 615 */ + IC_VEX_W, /* 616 */ + IC_VEX_W, /* 617 */ + IC_VEX_W_XS, /* 618 */ + IC_VEX_W_XS, /* 619 */ + IC_VEX_W_XD, /* 620 */ + IC_VEX_W_XD, /* 621 */ + IC_VEX_W_XD, /* 622 */ + IC_VEX_W_XD, /* 623 */ + IC_VEX_OPSIZE, /* 624 */ + IC_VEX_OPSIZE, /* 625 */ + IC_VEX_OPSIZE, /* 626 */ + IC_VEX_OPSIZE, /* 627 */ + IC_VEX_OPSIZE, /* 628 */ + IC_VEX_OPSIZE, /* 629 */ + IC_VEX_OPSIZE, /* 630 */ + IC_VEX_OPSIZE, /* 631 */ + IC_VEX_W_OPSIZE, /* 632 */ + IC_VEX_W_OPSIZE, /* 633 */ + IC_VEX_W_OPSIZE, /* 634 */ + IC_VEX_W_OPSIZE, /* 635 */ + IC_VEX_W_OPSIZE, /* 636 */ + IC_VEX_W_OPSIZE, /* 637 */ + IC_VEX_W_OPSIZE, /* 638 */ + IC_VEX_W_OPSIZE, /* 639 */ + IC_VEX_L, /* 640 */ + IC_VEX_L, /* 641 */ + IC_VEX_L_XS, /* 642 */ + IC_VEX_L_XS, /* 643 */ + IC_VEX_L_XD, /* 644 */ + IC_VEX_L_XD, /* 645 */ + IC_VEX_L_XD, /* 646 */ + IC_VEX_L_XD, /* 647 */ + IC_VEX_L_W, /* 648 */ + IC_VEX_L_W, /* 649 */ + IC_VEX_L_W_XS, /* 650 */ + IC_VEX_L_W_XS, /* 651 */ + IC_VEX_L_W_XD, /* 652 */ + IC_VEX_L_W_XD, /* 653 */ + IC_VEX_L_W_XD, /* 654 */ + IC_VEX_L_W_XD, /* 655 */ + IC_VEX_L_OPSIZE, /* 656 */ + IC_VEX_L_OPSIZE, /* 657 */ + IC_VEX_L_OPSIZE, /* 658 */ + IC_VEX_L_OPSIZE, /* 659 */ + IC_VEX_L_OPSIZE, /* 660 */ + IC_VEX_L_OPSIZE, /* 661 */ + IC_VEX_L_OPSIZE, /* 662 */ + IC_VEX_L_OPSIZE, /* 663 */ + IC_VEX_L_W_OPSIZE, /* 664 */ + IC_VEX_L_W_OPSIZE, /* 665 */ + IC_VEX_L_W_OPSIZE, /* 666 */ + IC_VEX_L_W_OPSIZE, /* 667 */ + IC_VEX_L_W_OPSIZE, /* 668 */ + IC_VEX_L_W_OPSIZE, /* 669 */ + IC_VEX_L_W_OPSIZE, /* 670 */ + IC_VEX_L_W_OPSIZE, /* 671 */ + IC_VEX_L, /* 672 */ + IC_VEX_L, /* 673 */ + IC_VEX_L_XS, /* 674 */ + IC_VEX_L_XS, /* 675 */ + IC_VEX_L_XD, /* 676 */ + IC_VEX_L_XD, /* 677 */ + IC_VEX_L_XD, /* 678 */ + IC_VEX_L_XD, /* 679 */ + IC_VEX_L_W, /* 680 */ + IC_VEX_L_W, /* 681 */ + IC_VEX_L_W_XS, /* 682 */ + IC_VEX_L_W_XS, /* 683 */ + IC_VEX_L_W_XD, /* 684 */ + IC_VEX_L_W_XD, /* 685 */ + IC_VEX_L_W_XD, /* 686 */ + IC_VEX_L_W_XD, /* 687 */ + IC_VEX_L_OPSIZE, /* 688 */ + IC_VEX_L_OPSIZE, /* 689 */ + IC_VEX_L_OPSIZE, /* 690 */ + IC_VEX_L_OPSIZE, /* 691 */ + IC_VEX_L_OPSIZE, /* 692 */ + IC_VEX_L_OPSIZE, /* 693 */ + IC_VEX_L_OPSIZE, /* 694 */ + IC_VEX_L_OPSIZE, /* 695 */ + IC_VEX_L_W_OPSIZE, /* 696 */ + IC_VEX_L_W_OPSIZE, /* 697 */ + IC_VEX_L_W_OPSIZE, /* 698 */ + IC_VEX_L_W_OPSIZE, /* 699 */ + IC_VEX_L_W_OPSIZE, /* 700 */ + IC_VEX_L_W_OPSIZE, /* 701 */ + IC_VEX_L_W_OPSIZE, /* 702 */ + IC_VEX_L_W_OPSIZE, /* 703 */ + IC_VEX_L, /* 704 */ + IC_VEX_L, /* 705 */ + IC_VEX_L_XS, /* 706 */ + IC_VEX_L_XS, /* 707 */ + IC_VEX_L_XD, /* 708 */ + IC_VEX_L_XD, /* 709 */ + IC_VEX_L_XD, /* 710 */ + IC_VEX_L_XD, /* 711 */ + IC_VEX_L_W, /* 712 */ + IC_VEX_L_W, /* 713 */ + IC_VEX_L_W_XS, /* 714 */ + IC_VEX_L_W_XS, /* 715 */ + IC_VEX_L_W_XD, /* 716 */ + IC_VEX_L_W_XD, /* 717 */ + IC_VEX_L_W_XD, /* 718 */ + IC_VEX_L_W_XD, /* 719 */ + IC_VEX_L_OPSIZE, /* 720 */ + IC_VEX_L_OPSIZE, /* 721 */ + IC_VEX_L_OPSIZE, /* 722 */ + IC_VEX_L_OPSIZE, /* 723 */ + IC_VEX_L_OPSIZE, /* 724 */ + IC_VEX_L_OPSIZE, /* 725 */ + IC_VEX_L_OPSIZE, /* 726 */ + IC_VEX_L_OPSIZE, /* 727 */ + IC_VEX_L_W_OPSIZE, /* 728 */ + IC_VEX_L_W_OPSIZE, /* 729 */ + IC_VEX_L_W_OPSIZE, /* 730 */ + IC_VEX_L_W_OPSIZE, /* 731 */ + IC_VEX_L_W_OPSIZE, /* 732 */ + IC_VEX_L_W_OPSIZE, /* 733 */ + IC_VEX_L_W_OPSIZE, /* 734 */ + IC_VEX_L_W_OPSIZE, /* 735 */ + IC_VEX_L, /* 736 */ + IC_VEX_L, /* 737 */ + IC_VEX_L_XS, /* 738 */ + IC_VEX_L_XS, /* 739 */ + IC_VEX_L_XD, /* 740 */ + IC_VEX_L_XD, /* 741 */ + IC_VEX_L_XD, /* 742 */ + IC_VEX_L_XD, /* 743 */ + IC_VEX_L_W, /* 744 */ + IC_VEX_L_W, /* 745 */ + IC_VEX_L_W_XS, /* 746 */ + IC_VEX_L_W_XS, /* 747 */ + IC_VEX_L_W_XD, /* 748 */ + IC_VEX_L_W_XD, /* 749 */ + IC_VEX_L_W_XD, /* 750 */ + IC_VEX_L_W_XD, /* 751 */ + IC_VEX_L_OPSIZE, /* 752 */ + IC_VEX_L_OPSIZE, /* 753 */ + IC_VEX_L_OPSIZE, /* 754 */ + IC_VEX_L_OPSIZE, /* 755 */ + IC_VEX_L_OPSIZE, /* 756 */ + IC_VEX_L_OPSIZE, /* 757 */ + IC_VEX_L_OPSIZE, /* 758 */ + IC_VEX_L_OPSIZE, /* 759 */ + IC_VEX_L_W_OPSIZE, /* 760 */ + IC_VEX_L_W_OPSIZE, /* 761 */ + IC_VEX_L_W_OPSIZE, /* 762 */ + IC_VEX_L_W_OPSIZE, /* 763 */ + IC_VEX_L_W_OPSIZE, /* 764 */ + IC_VEX_L_W_OPSIZE, /* 765 */ + IC_VEX_L_W_OPSIZE, /* 766 */ + IC_VEX_L_W_OPSIZE, /* 767 */ + IC_EVEX_L, /* 768 */ + IC_EVEX_L, /* 769 */ + IC_EVEX_L_XS, /* 770 */ + IC_EVEX_L_XS, /* 771 */ + IC_EVEX_L_XD, /* 772 */ + IC_EVEX_L_XD, /* 773 */ + IC_EVEX_L_XD, /* 774 */ + IC_EVEX_L_XD, /* 775 */ + IC_EVEX_L_W, /* 776 */ + IC_EVEX_L_W, /* 777 */ + IC_EVEX_L_W_XS, /* 778 */ + IC_EVEX_L_W_XS, /* 779 */ + IC_EVEX_L_W_XD, /* 780 */ + IC_EVEX_L_W_XD, /* 781 */ + IC_EVEX_L_W_XD, /* 782 */ + IC_EVEX_L_W_XD, /* 783 */ + IC_EVEX_L_OPSIZE, /* 784 */ + IC_EVEX_L_OPSIZE, /* 785 */ + IC_EVEX_L_OPSIZE, /* 786 */ + IC_EVEX_L_OPSIZE, /* 787 */ + IC_EVEX_L_OPSIZE, /* 788 */ + IC_EVEX_L_OPSIZE, /* 789 */ + IC_EVEX_L_OPSIZE, /* 790 */ + IC_EVEX_L_OPSIZE, /* 791 */ + IC_EVEX_L_W_OPSIZE, /* 792 */ + IC_EVEX_L_W_OPSIZE, /* 793 */ + IC_EVEX_L_W_OPSIZE, /* 794 */ + IC_EVEX_L_W_OPSIZE, /* 795 */ + IC_EVEX_L_W_OPSIZE, /* 796 */ + IC_EVEX_L_W_OPSIZE, /* 797 */ + IC_EVEX_L_W_OPSIZE, /* 798 */ + IC_EVEX_L_W_OPSIZE, /* 799 */ + IC_EVEX_L, /* 800 */ + IC_EVEX_L, /* 801 */ + IC_EVEX_L_XS, /* 802 */ + IC_EVEX_L_XS, /* 803 */ + IC_EVEX_L_XD, /* 804 */ + IC_EVEX_L_XD, /* 805 */ + IC_EVEX_L_XD, /* 806 */ + IC_EVEX_L_XD, /* 807 */ + IC_EVEX_L_W, /* 808 */ + IC_EVEX_L_W, /* 809 */ + IC_EVEX_L_W_XS, /* 810 */ + IC_EVEX_L_W_XS, /* 811 */ + IC_EVEX_L_W_XD, /* 812 */ + IC_EVEX_L_W_XD, /* 813 */ + IC_EVEX_L_W_XD, /* 814 */ + IC_EVEX_L_W_XD, /* 815 */ + IC_EVEX_L_OPSIZE, /* 816 */ + IC_EVEX_L_OPSIZE, /* 817 */ + IC_EVEX_L_OPSIZE, /* 818 */ + IC_EVEX_L_OPSIZE, /* 819 */ + IC_EVEX_L_OPSIZE, /* 820 */ + IC_EVEX_L_OPSIZE, /* 821 */ + IC_EVEX_L_OPSIZE, /* 822 */ + IC_EVEX_L_OPSIZE, /* 823 */ + IC_EVEX_L_W_OPSIZE, /* 824 */ + IC_EVEX_L_W_OPSIZE, /* 825 */ + IC_EVEX_L_W_OPSIZE, /* 826 */ + IC_EVEX_L_W_OPSIZE, /* 827 */ + IC_EVEX_L_W_OPSIZE, /* 828 */ + IC_EVEX_L_W_OPSIZE, /* 829 */ + IC_EVEX_L_W_OPSIZE, /* 830 */ + IC_EVEX_L_W_OPSIZE, /* 831 */ + IC_EVEX_L, /* 832 */ + IC_EVEX_L, /* 833 */ + IC_EVEX_L_XS, /* 834 */ + IC_EVEX_L_XS, /* 835 */ + IC_EVEX_L_XD, /* 836 */ + IC_EVEX_L_XD, /* 837 */ + IC_EVEX_L_XD, /* 838 */ + IC_EVEX_L_XD, /* 839 */ + IC_EVEX_L_W, /* 840 */ + IC_EVEX_L_W, /* 841 */ + IC_EVEX_L_W_XS, /* 842 */ + IC_EVEX_L_W_XS, /* 843 */ + IC_EVEX_L_W_XD, /* 844 */ + IC_EVEX_L_W_XD, /* 845 */ + IC_EVEX_L_W_XD, /* 846 */ + IC_EVEX_L_W_XD, /* 847 */ + IC_EVEX_L_OPSIZE, /* 848 */ + IC_EVEX_L_OPSIZE, /* 849 */ + IC_EVEX_L_OPSIZE, /* 850 */ + IC_EVEX_L_OPSIZE, /* 851 */ + IC_EVEX_L_OPSIZE, /* 852 */ + IC_EVEX_L_OPSIZE, /* 853 */ + IC_EVEX_L_OPSIZE, /* 854 */ + IC_EVEX_L_OPSIZE, /* 855 */ + IC_EVEX_L_W_OPSIZE, /* 856 */ + IC_EVEX_L_W_OPSIZE, /* 857 */ + IC_EVEX_L_W_OPSIZE, /* 858 */ + IC_EVEX_L_W_OPSIZE, /* 859 */ + IC_EVEX_L_W_OPSIZE, /* 860 */ + IC_EVEX_L_W_OPSIZE, /* 861 */ + IC_EVEX_L_W_OPSIZE, /* 862 */ + IC_EVEX_L_W_OPSIZE, /* 863 */ + IC_EVEX_L, /* 864 */ + IC_EVEX_L, /* 865 */ + IC_EVEX_L_XS, /* 866 */ + IC_EVEX_L_XS, /* 867 */ + IC_EVEX_L_XD, /* 868 */ + IC_EVEX_L_XD, /* 869 */ + IC_EVEX_L_XD, /* 870 */ + IC_EVEX_L_XD, /* 871 */ + IC_EVEX_L_W, /* 872 */ + IC_EVEX_L_W, /* 873 */ + IC_EVEX_L_W_XS, /* 874 */ + IC_EVEX_L_W_XS, /* 875 */ + IC_EVEX_L_W_XD, /* 876 */ + IC_EVEX_L_W_XD, /* 877 */ + IC_EVEX_L_W_XD, /* 878 */ + IC_EVEX_L_W_XD, /* 879 */ + IC_EVEX_L_OPSIZE, /* 880 */ + IC_EVEX_L_OPSIZE, /* 881 */ + IC_EVEX_L_OPSIZE, /* 882 */ + IC_EVEX_L_OPSIZE, /* 883 */ + IC_EVEX_L_OPSIZE, /* 884 */ + IC_EVEX_L_OPSIZE, /* 885 */ + IC_EVEX_L_OPSIZE, /* 886 */ + IC_EVEX_L_OPSIZE, /* 887 */ + IC_EVEX_L_W_OPSIZE, /* 888 */ + IC_EVEX_L_W_OPSIZE, /* 889 */ + IC_EVEX_L_W_OPSIZE, /* 890 */ + IC_EVEX_L_W_OPSIZE, /* 891 */ + IC_EVEX_L_W_OPSIZE, /* 892 */ + IC_EVEX_L_W_OPSIZE, /* 893 */ + IC_EVEX_L_W_OPSIZE, /* 894 */ + IC_EVEX_L_W_OPSIZE, /* 895 */ + IC_EVEX_L, /* 896 */ + IC_EVEX_L, /* 897 */ + IC_EVEX_L_XS, /* 898 */ + IC_EVEX_L_XS, /* 899 */ + IC_EVEX_L_XD, /* 900 */ + IC_EVEX_L_XD, /* 901 */ + IC_EVEX_L_XD, /* 902 */ + IC_EVEX_L_XD, /* 903 */ + IC_EVEX_L_W, /* 904 */ + IC_EVEX_L_W, /* 905 */ + IC_EVEX_L_W_XS, /* 906 */ + IC_EVEX_L_W_XS, /* 907 */ + IC_EVEX_L_W_XD, /* 908 */ + IC_EVEX_L_W_XD, /* 909 */ + IC_EVEX_L_W_XD, /* 910 */ + IC_EVEX_L_W_XD, /* 911 */ + IC_EVEX_L_OPSIZE, /* 912 */ + IC_EVEX_L_OPSIZE, /* 913 */ + IC_EVEX_L_OPSIZE, /* 914 */ + IC_EVEX_L_OPSIZE, /* 915 */ + IC_EVEX_L_OPSIZE, /* 916 */ + IC_EVEX_L_OPSIZE, /* 917 */ + IC_EVEX_L_OPSIZE, /* 918 */ + IC_EVEX_L_OPSIZE, /* 919 */ + IC_EVEX_L_W_OPSIZE, /* 920 */ + IC_EVEX_L_W_OPSIZE, /* 921 */ + IC_EVEX_L_W_OPSIZE, /* 922 */ + IC_EVEX_L_W_OPSIZE, /* 923 */ + IC_EVEX_L_W_OPSIZE, /* 924 */ + IC_EVEX_L_W_OPSIZE, /* 925 */ + IC_EVEX_L_W_OPSIZE, /* 926 */ + IC_EVEX_L_W_OPSIZE, /* 927 */ + IC_EVEX_L, /* 928 */ + IC_EVEX_L, /* 929 */ + IC_EVEX_L_XS, /* 930 */ + IC_EVEX_L_XS, /* 931 */ + IC_EVEX_L_XD, /* 932 */ + IC_EVEX_L_XD, /* 933 */ + IC_EVEX_L_XD, /* 934 */ + IC_EVEX_L_XD, /* 935 */ + IC_EVEX_L_W, /* 936 */ + IC_EVEX_L_W, /* 937 */ + IC_EVEX_L_W_XS, /* 938 */ + IC_EVEX_L_W_XS, /* 939 */ + IC_EVEX_L_W_XD, /* 940 */ + IC_EVEX_L_W_XD, /* 941 */ + IC_EVEX_L_W_XD, /* 942 */ + IC_EVEX_L_W_XD, /* 943 */ + IC_EVEX_L_OPSIZE, /* 944 */ + IC_EVEX_L_OPSIZE, /* 945 */ + IC_EVEX_L_OPSIZE, /* 946 */ + IC_EVEX_L_OPSIZE, /* 947 */ + IC_EVEX_L_OPSIZE, /* 948 */ + IC_EVEX_L_OPSIZE, /* 949 */ + IC_EVEX_L_OPSIZE, /* 950 */ + IC_EVEX_L_OPSIZE, /* 951 */ + IC_EVEX_L_W_OPSIZE, /* 952 */ + IC_EVEX_L_W_OPSIZE, /* 953 */ + IC_EVEX_L_W_OPSIZE, /* 954 */ + IC_EVEX_L_W_OPSIZE, /* 955 */ + IC_EVEX_L_W_OPSIZE, /* 956 */ + IC_EVEX_L_W_OPSIZE, /* 957 */ + IC_EVEX_L_W_OPSIZE, /* 958 */ + IC_EVEX_L_W_OPSIZE, /* 959 */ + IC_EVEX_L, /* 960 */ + IC_EVEX_L, /* 961 */ + IC_EVEX_L_XS, /* 962 */ + IC_EVEX_L_XS, /* 963 */ + IC_EVEX_L_XD, /* 964 */ + IC_EVEX_L_XD, /* 965 */ + IC_EVEX_L_XD, /* 966 */ + IC_EVEX_L_XD, /* 967 */ + IC_EVEX_L_W, /* 968 */ + IC_EVEX_L_W, /* 969 */ + IC_EVEX_L_W_XS, /* 970 */ + IC_EVEX_L_W_XS, /* 971 */ + IC_EVEX_L_W_XD, /* 972 */ + IC_EVEX_L_W_XD, /* 973 */ + IC_EVEX_L_W_XD, /* 974 */ + IC_EVEX_L_W_XD, /* 975 */ + IC_EVEX_L_OPSIZE, /* 976 */ + IC_EVEX_L_OPSIZE, /* 977 */ + IC_EVEX_L_OPSIZE, /* 978 */ + IC_EVEX_L_OPSIZE, /* 979 */ + IC_EVEX_L_OPSIZE, /* 980 */ + IC_EVEX_L_OPSIZE, /* 981 */ + IC_EVEX_L_OPSIZE, /* 982 */ + IC_EVEX_L_OPSIZE, /* 983 */ + IC_EVEX_L_W_OPSIZE, /* 984 */ + IC_EVEX_L_W_OPSIZE, /* 985 */ + IC_EVEX_L_W_OPSIZE, /* 986 */ + IC_EVEX_L_W_OPSIZE, /* 987 */ + IC_EVEX_L_W_OPSIZE, /* 988 */ + IC_EVEX_L_W_OPSIZE, /* 989 */ + IC_EVEX_L_W_OPSIZE, /* 990 */ + IC_EVEX_L_W_OPSIZE, /* 991 */ + IC_EVEX_L, /* 992 */ + IC_EVEX_L, /* 993 */ + IC_EVEX_L_XS, /* 994 */ + IC_EVEX_L_XS, /* 995 */ + IC_EVEX_L_XD, /* 996 */ + IC_EVEX_L_XD, /* 997 */ + IC_EVEX_L_XD, /* 998 */ + IC_EVEX_L_XD, /* 999 */ + IC_EVEX_L_W, /* 1000 */ + IC_EVEX_L_W, /* 1001 */ + IC_EVEX_L_W_XS, /* 1002 */ + IC_EVEX_L_W_XS, /* 1003 */ + IC_EVEX_L_W_XD, /* 1004 */ + IC_EVEX_L_W_XD, /* 1005 */ + IC_EVEX_L_W_XD, /* 1006 */ + IC_EVEX_L_W_XD, /* 1007 */ + IC_EVEX_L_OPSIZE, /* 1008 */ + IC_EVEX_L_OPSIZE, /* 1009 */ + IC_EVEX_L_OPSIZE, /* 1010 */ + IC_EVEX_L_OPSIZE, /* 1011 */ + IC_EVEX_L_OPSIZE, /* 1012 */ + IC_EVEX_L_OPSIZE, /* 1013 */ + IC_EVEX_L_OPSIZE, /* 1014 */ + IC_EVEX_L_OPSIZE, /* 1015 */ + IC_EVEX_L_W_OPSIZE, /* 1016 */ + IC_EVEX_L_W_OPSIZE, /* 1017 */ + IC_EVEX_L_W_OPSIZE, /* 1018 */ + IC_EVEX_L_W_OPSIZE, /* 1019 */ + IC_EVEX_L_W_OPSIZE, /* 1020 */ + IC_EVEX_L_W_OPSIZE, /* 1021 */ + IC_EVEX_L_W_OPSIZE, /* 1022 */ + IC_EVEX_L_W_OPSIZE, /* 1023 */ + IC, /* 1024 */ + IC_64BIT, /* 1025 */ + IC_XS, /* 1026 */ + IC_64BIT_XS, /* 1027 */ + IC_XD, /* 1028 */ + IC_64BIT_XD, /* 1029 */ + IC_XS, /* 1030 */ + IC_64BIT_XS, /* 1031 */ + IC, /* 1032 */ + IC_64BIT_REXW, /* 1033 */ + IC_XS, /* 1034 */ + IC_64BIT_REXW_XS, /* 1035 */ + IC_XD, /* 1036 */ + IC_64BIT_REXW_XD, /* 1037 */ + IC_XS, /* 1038 */ + IC_64BIT_REXW_XS, /* 1039 */ + IC_OPSIZE, /* 1040 */ + IC_64BIT_OPSIZE, /* 1041 */ + IC_XS_OPSIZE, /* 1042 */ + IC_64BIT_XS_OPSIZE, /* 1043 */ + IC_XD_OPSIZE, /* 1044 */ + IC_64BIT_XD_OPSIZE, /* 1045 */ + IC_XS_OPSIZE, /* 1046 */ + IC_64BIT_XD_OPSIZE, /* 1047 */ + IC_OPSIZE, /* 1048 */ + IC_64BIT_REXW_OPSIZE, /* 1049 */ + IC_XS_OPSIZE, /* 1050 */ + IC_64BIT_REXW_XS, /* 1051 */ + IC_XD_OPSIZE, /* 1052 */ + IC_64BIT_REXW_XD, /* 1053 */ + IC_XS_OPSIZE, /* 1054 */ + IC_64BIT_REXW_XS, /* 1055 */ + IC_ADSIZE, /* 1056 */ + IC_64BIT_ADSIZE, /* 1057 */ + IC_XS_ADSIZE, /* 1058 */ + IC_64BIT_XS_ADSIZE, /* 1059 */ + IC_XD_ADSIZE, /* 1060 */ + IC_64BIT_XD_ADSIZE, /* 1061 */ + IC_XS_ADSIZE, /* 1062 */ + IC_64BIT_XD_ADSIZE, /* 1063 */ + IC_ADSIZE, /* 1064 */ + IC_64BIT_REXW_ADSIZE, /* 1065 */ + IC_XS_ADSIZE, /* 1066 */ + IC_64BIT_REXW_XS, /* 1067 */ + IC_XD_ADSIZE, /* 1068 */ + IC_64BIT_REXW_XD, /* 1069 */ + IC_XS_ADSIZE, /* 1070 */ + IC_64BIT_REXW_XS, /* 1071 */ + IC_OPSIZE_ADSIZE, /* 1072 */ + IC_64BIT_OPSIZE_ADSIZE, /* 1073 */ + IC_XS_OPSIZE, /* 1074 */ + IC_64BIT_XS_OPSIZE, /* 1075 */ + IC_XD_OPSIZE, /* 1076 */ + IC_64BIT_XD_OPSIZE, /* 1077 */ + IC_XS_OPSIZE, /* 1078 */ + IC_64BIT_XD_OPSIZE, /* 1079 */ + IC_OPSIZE_ADSIZE, /* 1080 */ + IC_64BIT_REXW_OPSIZE, /* 1081 */ + IC_XS_OPSIZE, /* 1082 */ + IC_64BIT_REXW_XS, /* 1083 */ + IC_XD_OPSIZE, /* 1084 */ + IC_64BIT_REXW_XD, /* 1085 */ + IC_XS_OPSIZE, /* 1086 */ + IC_64BIT_REXW_XS, /* 1087 */ + IC_VEX, /* 1088 */ + IC_VEX, /* 1089 */ + IC_VEX_XS, /* 1090 */ + IC_VEX_XS, /* 1091 */ + IC_VEX_XD, /* 1092 */ + IC_VEX_XD, /* 1093 */ + IC_VEX_XD, /* 1094 */ + IC_VEX_XD, /* 1095 */ + IC_VEX_W, /* 1096 */ + IC_VEX_W, /* 1097 */ + IC_VEX_W_XS, /* 1098 */ + IC_VEX_W_XS, /* 1099 */ + IC_VEX_W_XD, /* 1100 */ + IC_VEX_W_XD, /* 1101 */ + IC_VEX_W_XD, /* 1102 */ + IC_VEX_W_XD, /* 1103 */ + IC_VEX_OPSIZE, /* 1104 */ + IC_VEX_OPSIZE, /* 1105 */ + IC_VEX_OPSIZE, /* 1106 */ + IC_VEX_OPSIZE, /* 1107 */ + IC_VEX_OPSIZE, /* 1108 */ + IC_VEX_OPSIZE, /* 1109 */ + IC_VEX_OPSIZE, /* 1110 */ + IC_VEX_OPSIZE, /* 1111 */ + IC_VEX_W_OPSIZE, /* 1112 */ + IC_VEX_W_OPSIZE, /* 1113 */ + IC_VEX_W_OPSIZE, /* 1114 */ + IC_VEX_W_OPSIZE, /* 1115 */ + IC_VEX_W_OPSIZE, /* 1116 */ + IC_VEX_W_OPSIZE, /* 1117 */ + IC_VEX_W_OPSIZE, /* 1118 */ + IC_VEX_W_OPSIZE, /* 1119 */ + IC_VEX, /* 1120 */ + IC_VEX, /* 1121 */ + IC_VEX_XS, /* 1122 */ + IC_VEX_XS, /* 1123 */ + IC_VEX_XD, /* 1124 */ + IC_VEX_XD, /* 1125 */ + IC_VEX_XD, /* 1126 */ + IC_VEX_XD, /* 1127 */ + IC_VEX_W, /* 1128 */ + IC_VEX_W, /* 1129 */ + IC_VEX_W_XS, /* 1130 */ + IC_VEX_W_XS, /* 1131 */ + IC_VEX_W_XD, /* 1132 */ + IC_VEX_W_XD, /* 1133 */ + IC_VEX_W_XD, /* 1134 */ + IC_VEX_W_XD, /* 1135 */ + IC_VEX_OPSIZE, /* 1136 */ + IC_VEX_OPSIZE, /* 1137 */ + IC_VEX_OPSIZE, /* 1138 */ + IC_VEX_OPSIZE, /* 1139 */ + IC_VEX_OPSIZE, /* 1140 */ + IC_VEX_OPSIZE, /* 1141 */ + IC_VEX_OPSIZE, /* 1142 */ + IC_VEX_OPSIZE, /* 1143 */ + IC_VEX_W_OPSIZE, /* 1144 */ + IC_VEX_W_OPSIZE, /* 1145 */ + IC_VEX_W_OPSIZE, /* 1146 */ + IC_VEX_W_OPSIZE, /* 1147 */ + IC_VEX_W_OPSIZE, /* 1148 */ + IC_VEX_W_OPSIZE, /* 1149 */ + IC_VEX_W_OPSIZE, /* 1150 */ + IC_VEX_W_OPSIZE, /* 1151 */ + IC_VEX_L, /* 1152 */ + IC_VEX_L, /* 1153 */ + IC_VEX_L_XS, /* 1154 */ + IC_VEX_L_XS, /* 1155 */ + IC_VEX_L_XD, /* 1156 */ + IC_VEX_L_XD, /* 1157 */ + IC_VEX_L_XD, /* 1158 */ + IC_VEX_L_XD, /* 1159 */ + IC_VEX_L_W, /* 1160 */ + IC_VEX_L_W, /* 1161 */ + IC_VEX_L_W_XS, /* 1162 */ + IC_VEX_L_W_XS, /* 1163 */ + IC_VEX_L_W_XD, /* 1164 */ + IC_VEX_L_W_XD, /* 1165 */ + IC_VEX_L_W_XD, /* 1166 */ + IC_VEX_L_W_XD, /* 1167 */ + IC_VEX_L_OPSIZE, /* 1168 */ + IC_VEX_L_OPSIZE, /* 1169 */ + IC_VEX_L_OPSIZE, /* 1170 */ + IC_VEX_L_OPSIZE, /* 1171 */ + IC_VEX_L_OPSIZE, /* 1172 */ + IC_VEX_L_OPSIZE, /* 1173 */ + IC_VEX_L_OPSIZE, /* 1174 */ + IC_VEX_L_OPSIZE, /* 1175 */ + IC_VEX_L_W_OPSIZE, /* 1176 */ + IC_VEX_L_W_OPSIZE, /* 1177 */ + IC_VEX_L_W_OPSIZE, /* 1178 */ + IC_VEX_L_W_OPSIZE, /* 1179 */ + IC_VEX_L_W_OPSIZE, /* 1180 */ + IC_VEX_L_W_OPSIZE, /* 1181 */ + IC_VEX_L_W_OPSIZE, /* 1182 */ + IC_VEX_L_W_OPSIZE, /* 1183 */ + IC_VEX_L, /* 1184 */ + IC_VEX_L, /* 1185 */ + IC_VEX_L_XS, /* 1186 */ + IC_VEX_L_XS, /* 1187 */ + IC_VEX_L_XD, /* 1188 */ + IC_VEX_L_XD, /* 1189 */ + IC_VEX_L_XD, /* 1190 */ + IC_VEX_L_XD, /* 1191 */ + IC_VEX_L_W, /* 1192 */ + IC_VEX_L_W, /* 1193 */ + IC_VEX_L_W_XS, /* 1194 */ + IC_VEX_L_W_XS, /* 1195 */ + IC_VEX_L_W_XD, /* 1196 */ + IC_VEX_L_W_XD, /* 1197 */ + IC_VEX_L_W_XD, /* 1198 */ + IC_VEX_L_W_XD, /* 1199 */ + IC_VEX_L_OPSIZE, /* 1200 */ + IC_VEX_L_OPSIZE, /* 1201 */ + IC_VEX_L_OPSIZE, /* 1202 */ + IC_VEX_L_OPSIZE, /* 1203 */ + IC_VEX_L_OPSIZE, /* 1204 */ + IC_VEX_L_OPSIZE, /* 1205 */ + IC_VEX_L_OPSIZE, /* 1206 */ + IC_VEX_L_OPSIZE, /* 1207 */ + IC_VEX_L_W_OPSIZE, /* 1208 */ + IC_VEX_L_W_OPSIZE, /* 1209 */ + IC_VEX_L_W_OPSIZE, /* 1210 */ + IC_VEX_L_W_OPSIZE, /* 1211 */ + IC_VEX_L_W_OPSIZE, /* 1212 */ + IC_VEX_L_W_OPSIZE, /* 1213 */ + IC_VEX_L_W_OPSIZE, /* 1214 */ + IC_VEX_L_W_OPSIZE, /* 1215 */ + IC_VEX_L, /* 1216 */ + IC_VEX_L, /* 1217 */ + IC_VEX_L_XS, /* 1218 */ + IC_VEX_L_XS, /* 1219 */ + IC_VEX_L_XD, /* 1220 */ + IC_VEX_L_XD, /* 1221 */ + IC_VEX_L_XD, /* 1222 */ + IC_VEX_L_XD, /* 1223 */ + IC_VEX_L_W, /* 1224 */ + IC_VEX_L_W, /* 1225 */ + IC_VEX_L_W_XS, /* 1226 */ + IC_VEX_L_W_XS, /* 1227 */ + IC_VEX_L_W_XD, /* 1228 */ + IC_VEX_L_W_XD, /* 1229 */ + IC_VEX_L_W_XD, /* 1230 */ + IC_VEX_L_W_XD, /* 1231 */ + IC_VEX_L_OPSIZE, /* 1232 */ + IC_VEX_L_OPSIZE, /* 1233 */ + IC_VEX_L_OPSIZE, /* 1234 */ + IC_VEX_L_OPSIZE, /* 1235 */ + IC_VEX_L_OPSIZE, /* 1236 */ + IC_VEX_L_OPSIZE, /* 1237 */ + IC_VEX_L_OPSIZE, /* 1238 */ + IC_VEX_L_OPSIZE, /* 1239 */ + IC_VEX_L_W_OPSIZE, /* 1240 */ + IC_VEX_L_W_OPSIZE, /* 1241 */ + IC_VEX_L_W_OPSIZE, /* 1242 */ + IC_VEX_L_W_OPSIZE, /* 1243 */ + IC_VEX_L_W_OPSIZE, /* 1244 */ + IC_VEX_L_W_OPSIZE, /* 1245 */ + IC_VEX_L_W_OPSIZE, /* 1246 */ + IC_VEX_L_W_OPSIZE, /* 1247 */ + IC_VEX_L, /* 1248 */ + IC_VEX_L, /* 1249 */ + IC_VEX_L_XS, /* 1250 */ + IC_VEX_L_XS, /* 1251 */ + IC_VEX_L_XD, /* 1252 */ + IC_VEX_L_XD, /* 1253 */ + IC_VEX_L_XD, /* 1254 */ + IC_VEX_L_XD, /* 1255 */ + IC_VEX_L_W, /* 1256 */ + IC_VEX_L_W, /* 1257 */ + IC_VEX_L_W_XS, /* 1258 */ + IC_VEX_L_W_XS, /* 1259 */ + IC_VEX_L_W_XD, /* 1260 */ + IC_VEX_L_W_XD, /* 1261 */ + IC_VEX_L_W_XD, /* 1262 */ + IC_VEX_L_W_XD, /* 1263 */ + IC_VEX_L_OPSIZE, /* 1264 */ + IC_VEX_L_OPSIZE, /* 1265 */ + IC_VEX_L_OPSIZE, /* 1266 */ + IC_VEX_L_OPSIZE, /* 1267 */ + IC_VEX_L_OPSIZE, /* 1268 */ + IC_VEX_L_OPSIZE, /* 1269 */ + IC_VEX_L_OPSIZE, /* 1270 */ + IC_VEX_L_OPSIZE, /* 1271 */ + IC_VEX_L_W_OPSIZE, /* 1272 */ + IC_VEX_L_W_OPSIZE, /* 1273 */ + IC_VEX_L_W_OPSIZE, /* 1274 */ + IC_VEX_L_W_OPSIZE, /* 1275 */ + IC_VEX_L_W_OPSIZE, /* 1276 */ + IC_VEX_L_W_OPSIZE, /* 1277 */ + IC_VEX_L_W_OPSIZE, /* 1278 */ + IC_VEX_L_W_OPSIZE, /* 1279 */ + IC_EVEX_L2, /* 1280 */ + IC_EVEX_L2, /* 1281 */ + IC_EVEX_L2_XS, /* 1282 */ + IC_EVEX_L2_XS, /* 1283 */ + IC_EVEX_L2_XD, /* 1284 */ + IC_EVEX_L2_XD, /* 1285 */ + IC_EVEX_L2_XD, /* 1286 */ + IC_EVEX_L2_XD, /* 1287 */ + IC_EVEX_L2_W, /* 1288 */ + IC_EVEX_L2_W, /* 1289 */ + IC_EVEX_L2_W_XS, /* 1290 */ + IC_EVEX_L2_W_XS, /* 1291 */ + IC_EVEX_L2_W_XD, /* 1292 */ + IC_EVEX_L2_W_XD, /* 1293 */ + IC_EVEX_L2_W_XD, /* 1294 */ + IC_EVEX_L2_W_XD, /* 1295 */ + IC_EVEX_L2_OPSIZE, /* 1296 */ + IC_EVEX_L2_OPSIZE, /* 1297 */ + IC_EVEX_L2_OPSIZE, /* 1298 */ + IC_EVEX_L2_OPSIZE, /* 1299 */ + IC_EVEX_L2_OPSIZE, /* 1300 */ + IC_EVEX_L2_OPSIZE, /* 1301 */ + IC_EVEX_L2_OPSIZE, /* 1302 */ + IC_EVEX_L2_OPSIZE, /* 1303 */ + IC_EVEX_L2_W_OPSIZE, /* 1304 */ + IC_EVEX_L2_W_OPSIZE, /* 1305 */ + IC_EVEX_L2_W_OPSIZE, /* 1306 */ + IC_EVEX_L2_W_OPSIZE, /* 1307 */ + IC_EVEX_L2_W_OPSIZE, /* 1308 */ + IC_EVEX_L2_W_OPSIZE, /* 1309 */ + IC_EVEX_L2_W_OPSIZE, /* 1310 */ + IC_EVEX_L2_W_OPSIZE, /* 1311 */ + IC_EVEX_L2, /* 1312 */ + IC_EVEX_L2, /* 1313 */ + IC_EVEX_L2_XS, /* 1314 */ + IC_EVEX_L2_XS, /* 1315 */ + IC_EVEX_L2_XD, /* 1316 */ + IC_EVEX_L2_XD, /* 1317 */ + IC_EVEX_L2_XD, /* 1318 */ + IC_EVEX_L2_XD, /* 1319 */ + IC_EVEX_L2_W, /* 1320 */ + IC_EVEX_L2_W, /* 1321 */ + IC_EVEX_L2_W_XS, /* 1322 */ + IC_EVEX_L2_W_XS, /* 1323 */ + IC_EVEX_L2_W_XD, /* 1324 */ + IC_EVEX_L2_W_XD, /* 1325 */ + IC_EVEX_L2_W_XD, /* 1326 */ + IC_EVEX_L2_W_XD, /* 1327 */ + IC_EVEX_L2_OPSIZE, /* 1328 */ + IC_EVEX_L2_OPSIZE, /* 1329 */ + IC_EVEX_L2_OPSIZE, /* 1330 */ + IC_EVEX_L2_OPSIZE, /* 1331 */ + IC_EVEX_L2_OPSIZE, /* 1332 */ + IC_EVEX_L2_OPSIZE, /* 1333 */ + IC_EVEX_L2_OPSIZE, /* 1334 */ + IC_EVEX_L2_OPSIZE, /* 1335 */ + IC_EVEX_L2_W_OPSIZE, /* 1336 */ + IC_EVEX_L2_W_OPSIZE, /* 1337 */ + IC_EVEX_L2_W_OPSIZE, /* 1338 */ + IC_EVEX_L2_W_OPSIZE, /* 1339 */ + IC_EVEX_L2_W_OPSIZE, /* 1340 */ + IC_EVEX_L2_W_OPSIZE, /* 1341 */ + IC_EVEX_L2_W_OPSIZE, /* 1342 */ + IC_EVEX_L2_W_OPSIZE, /* 1343 */ + IC_EVEX_L2, /* 1344 */ + IC_EVEX_L2, /* 1345 */ + IC_EVEX_L2_XS, /* 1346 */ + IC_EVEX_L2_XS, /* 1347 */ + IC_EVEX_L2_XD, /* 1348 */ + IC_EVEX_L2_XD, /* 1349 */ + IC_EVEX_L2_XD, /* 1350 */ + IC_EVEX_L2_XD, /* 1351 */ + IC_EVEX_L2_W, /* 1352 */ + IC_EVEX_L2_W, /* 1353 */ + IC_EVEX_L2_W_XS, /* 1354 */ + IC_EVEX_L2_W_XS, /* 1355 */ + IC_EVEX_L2_W_XD, /* 1356 */ + IC_EVEX_L2_W_XD, /* 1357 */ + IC_EVEX_L2_W_XD, /* 1358 */ + IC_EVEX_L2_W_XD, /* 1359 */ + IC_EVEX_L2_OPSIZE, /* 1360 */ + IC_EVEX_L2_OPSIZE, /* 1361 */ + IC_EVEX_L2_OPSIZE, /* 1362 */ + IC_EVEX_L2_OPSIZE, /* 1363 */ + IC_EVEX_L2_OPSIZE, /* 1364 */ + IC_EVEX_L2_OPSIZE, /* 1365 */ + IC_EVEX_L2_OPSIZE, /* 1366 */ + IC_EVEX_L2_OPSIZE, /* 1367 */ + IC_EVEX_L2_W_OPSIZE, /* 1368 */ + IC_EVEX_L2_W_OPSIZE, /* 1369 */ + IC_EVEX_L2_W_OPSIZE, /* 1370 */ + IC_EVEX_L2_W_OPSIZE, /* 1371 */ + IC_EVEX_L2_W_OPSIZE, /* 1372 */ + IC_EVEX_L2_W_OPSIZE, /* 1373 */ + IC_EVEX_L2_W_OPSIZE, /* 1374 */ + IC_EVEX_L2_W_OPSIZE, /* 1375 */ + IC_EVEX_L2, /* 1376 */ + IC_EVEX_L2, /* 1377 */ + IC_EVEX_L2_XS, /* 1378 */ + IC_EVEX_L2_XS, /* 1379 */ + IC_EVEX_L2_XD, /* 1380 */ + IC_EVEX_L2_XD, /* 1381 */ + IC_EVEX_L2_XD, /* 1382 */ + IC_EVEX_L2_XD, /* 1383 */ + IC_EVEX_L2_W, /* 1384 */ + IC_EVEX_L2_W, /* 1385 */ + IC_EVEX_L2_W_XS, /* 1386 */ + IC_EVEX_L2_W_XS, /* 1387 */ + IC_EVEX_L2_W_XD, /* 1388 */ + IC_EVEX_L2_W_XD, /* 1389 */ + IC_EVEX_L2_W_XD, /* 1390 */ + IC_EVEX_L2_W_XD, /* 1391 */ + IC_EVEX_L2_OPSIZE, /* 1392 */ + IC_EVEX_L2_OPSIZE, /* 1393 */ + IC_EVEX_L2_OPSIZE, /* 1394 */ + IC_EVEX_L2_OPSIZE, /* 1395 */ + IC_EVEX_L2_OPSIZE, /* 1396 */ + IC_EVEX_L2_OPSIZE, /* 1397 */ + IC_EVEX_L2_OPSIZE, /* 1398 */ + IC_EVEX_L2_OPSIZE, /* 1399 */ + IC_EVEX_L2_W_OPSIZE, /* 1400 */ + IC_EVEX_L2_W_OPSIZE, /* 1401 */ + IC_EVEX_L2_W_OPSIZE, /* 1402 */ + IC_EVEX_L2_W_OPSIZE, /* 1403 */ + IC_EVEX_L2_W_OPSIZE, /* 1404 */ + IC_EVEX_L2_W_OPSIZE, /* 1405 */ + IC_EVEX_L2_W_OPSIZE, /* 1406 */ + IC_EVEX_L2_W_OPSIZE, /* 1407 */ + IC_EVEX_L2, /* 1408 */ + IC_EVEX_L2, /* 1409 */ + IC_EVEX_L2_XS, /* 1410 */ + IC_EVEX_L2_XS, /* 1411 */ + IC_EVEX_L2_XD, /* 1412 */ + IC_EVEX_L2_XD, /* 1413 */ + IC_EVEX_L2_XD, /* 1414 */ + IC_EVEX_L2_XD, /* 1415 */ + IC_EVEX_L2_W, /* 1416 */ + IC_EVEX_L2_W, /* 1417 */ + IC_EVEX_L2_W_XS, /* 1418 */ + IC_EVEX_L2_W_XS, /* 1419 */ + IC_EVEX_L2_W_XD, /* 1420 */ + IC_EVEX_L2_W_XD, /* 1421 */ + IC_EVEX_L2_W_XD, /* 1422 */ + IC_EVEX_L2_W_XD, /* 1423 */ + IC_EVEX_L2_OPSIZE, /* 1424 */ + IC_EVEX_L2_OPSIZE, /* 1425 */ + IC_EVEX_L2_OPSIZE, /* 1426 */ + IC_EVEX_L2_OPSIZE, /* 1427 */ + IC_EVEX_L2_OPSIZE, /* 1428 */ + IC_EVEX_L2_OPSIZE, /* 1429 */ + IC_EVEX_L2_OPSIZE, /* 1430 */ + IC_EVEX_L2_OPSIZE, /* 1431 */ + IC_EVEX_L2_W_OPSIZE, /* 1432 */ + IC_EVEX_L2_W_OPSIZE, /* 1433 */ + IC_EVEX_L2_W_OPSIZE, /* 1434 */ + IC_EVEX_L2_W_OPSIZE, /* 1435 */ + IC_EVEX_L2_W_OPSIZE, /* 1436 */ + IC_EVEX_L2_W_OPSIZE, /* 1437 */ + IC_EVEX_L2_W_OPSIZE, /* 1438 */ + IC_EVEX_L2_W_OPSIZE, /* 1439 */ + IC_EVEX_L2, /* 1440 */ + IC_EVEX_L2, /* 1441 */ + IC_EVEX_L2_XS, /* 1442 */ + IC_EVEX_L2_XS, /* 1443 */ + IC_EVEX_L2_XD, /* 1444 */ + IC_EVEX_L2_XD, /* 1445 */ + IC_EVEX_L2_XD, /* 1446 */ + IC_EVEX_L2_XD, /* 1447 */ + IC_EVEX_L2_W, /* 1448 */ + IC_EVEX_L2_W, /* 1449 */ + IC_EVEX_L2_W_XS, /* 1450 */ + IC_EVEX_L2_W_XS, /* 1451 */ + IC_EVEX_L2_W_XD, /* 1452 */ + IC_EVEX_L2_W_XD, /* 1453 */ + IC_EVEX_L2_W_XD, /* 1454 */ + IC_EVEX_L2_W_XD, /* 1455 */ + IC_EVEX_L2_OPSIZE, /* 1456 */ + IC_EVEX_L2_OPSIZE, /* 1457 */ + IC_EVEX_L2_OPSIZE, /* 1458 */ + IC_EVEX_L2_OPSIZE, /* 1459 */ + IC_EVEX_L2_OPSIZE, /* 1460 */ + IC_EVEX_L2_OPSIZE, /* 1461 */ + IC_EVEX_L2_OPSIZE, /* 1462 */ + IC_EVEX_L2_OPSIZE, /* 1463 */ + IC_EVEX_L2_W_OPSIZE, /* 1464 */ + IC_EVEX_L2_W_OPSIZE, /* 1465 */ + IC_EVEX_L2_W_OPSIZE, /* 1466 */ + IC_EVEX_L2_W_OPSIZE, /* 1467 */ + IC_EVEX_L2_W_OPSIZE, /* 1468 */ + IC_EVEX_L2_W_OPSIZE, /* 1469 */ + IC_EVEX_L2_W_OPSIZE, /* 1470 */ + IC_EVEX_L2_W_OPSIZE, /* 1471 */ + IC_EVEX_L2, /* 1472 */ + IC_EVEX_L2, /* 1473 */ + IC_EVEX_L2_XS, /* 1474 */ + IC_EVEX_L2_XS, /* 1475 */ + IC_EVEX_L2_XD, /* 1476 */ + IC_EVEX_L2_XD, /* 1477 */ + IC_EVEX_L2_XD, /* 1478 */ + IC_EVEX_L2_XD, /* 1479 */ + IC_EVEX_L2_W, /* 1480 */ + IC_EVEX_L2_W, /* 1481 */ + IC_EVEX_L2_W_XS, /* 1482 */ + IC_EVEX_L2_W_XS, /* 1483 */ + IC_EVEX_L2_W_XD, /* 1484 */ + IC_EVEX_L2_W_XD, /* 1485 */ + IC_EVEX_L2_W_XD, /* 1486 */ + IC_EVEX_L2_W_XD, /* 1487 */ + IC_EVEX_L2_OPSIZE, /* 1488 */ + IC_EVEX_L2_OPSIZE, /* 1489 */ + IC_EVEX_L2_OPSIZE, /* 1490 */ + IC_EVEX_L2_OPSIZE, /* 1491 */ + IC_EVEX_L2_OPSIZE, /* 1492 */ + IC_EVEX_L2_OPSIZE, /* 1493 */ + IC_EVEX_L2_OPSIZE, /* 1494 */ + IC_EVEX_L2_OPSIZE, /* 1495 */ + IC_EVEX_L2_W_OPSIZE, /* 1496 */ + IC_EVEX_L2_W_OPSIZE, /* 1497 */ + IC_EVEX_L2_W_OPSIZE, /* 1498 */ + IC_EVEX_L2_W_OPSIZE, /* 1499 */ + IC_EVEX_L2_W_OPSIZE, /* 1500 */ + IC_EVEX_L2_W_OPSIZE, /* 1501 */ + IC_EVEX_L2_W_OPSIZE, /* 1502 */ + IC_EVEX_L2_W_OPSIZE, /* 1503 */ + IC_EVEX_L2, /* 1504 */ + IC_EVEX_L2, /* 1505 */ + IC_EVEX_L2_XS, /* 1506 */ + IC_EVEX_L2_XS, /* 1507 */ + IC_EVEX_L2_XD, /* 1508 */ + IC_EVEX_L2_XD, /* 1509 */ + IC_EVEX_L2_XD, /* 1510 */ + IC_EVEX_L2_XD, /* 1511 */ + IC_EVEX_L2_W, /* 1512 */ + IC_EVEX_L2_W, /* 1513 */ + IC_EVEX_L2_W_XS, /* 1514 */ + IC_EVEX_L2_W_XS, /* 1515 */ + IC_EVEX_L2_W_XD, /* 1516 */ + IC_EVEX_L2_W_XD, /* 1517 */ + IC_EVEX_L2_W_XD, /* 1518 */ + IC_EVEX_L2_W_XD, /* 1519 */ + IC_EVEX_L2_OPSIZE, /* 1520 */ + IC_EVEX_L2_OPSIZE, /* 1521 */ + IC_EVEX_L2_OPSIZE, /* 1522 */ + IC_EVEX_L2_OPSIZE, /* 1523 */ + IC_EVEX_L2_OPSIZE, /* 1524 */ + IC_EVEX_L2_OPSIZE, /* 1525 */ + IC_EVEX_L2_OPSIZE, /* 1526 */ + IC_EVEX_L2_OPSIZE, /* 1527 */ + IC_EVEX_L2_W_OPSIZE, /* 1528 */ + IC_EVEX_L2_W_OPSIZE, /* 1529 */ + IC_EVEX_L2_W_OPSIZE, /* 1530 */ + IC_EVEX_L2_W_OPSIZE, /* 1531 */ + IC_EVEX_L2_W_OPSIZE, /* 1532 */ + IC_EVEX_L2_W_OPSIZE, /* 1533 */ + IC_EVEX_L2_W_OPSIZE, /* 1534 */ + IC_EVEX_L2_W_OPSIZE, /* 1535 */ + IC, /* 1536 */ + IC_64BIT, /* 1537 */ + IC_XS, /* 1538 */ + IC_64BIT_XS, /* 1539 */ + IC_XD, /* 1540 */ + IC_64BIT_XD, /* 1541 */ + IC_XS, /* 1542 */ + IC_64BIT_XS, /* 1543 */ + IC, /* 1544 */ + IC_64BIT_REXW, /* 1545 */ + IC_XS, /* 1546 */ + IC_64BIT_REXW_XS, /* 1547 */ + IC_XD, /* 1548 */ + IC_64BIT_REXW_XD, /* 1549 */ + IC_XS, /* 1550 */ + IC_64BIT_REXW_XS, /* 1551 */ + IC_OPSIZE, /* 1552 */ + IC_64BIT_OPSIZE, /* 1553 */ + IC_XS_OPSIZE, /* 1554 */ + IC_64BIT_XS_OPSIZE, /* 1555 */ + IC_XD_OPSIZE, /* 1556 */ + IC_64BIT_XD_OPSIZE, /* 1557 */ + IC_XS_OPSIZE, /* 1558 */ + IC_64BIT_XD_OPSIZE, /* 1559 */ + IC_OPSIZE, /* 1560 */ + IC_64BIT_REXW_OPSIZE, /* 1561 */ + IC_XS_OPSIZE, /* 1562 */ + IC_64BIT_REXW_XS, /* 1563 */ + IC_XD_OPSIZE, /* 1564 */ + IC_64BIT_REXW_XD, /* 1565 */ + IC_XS_OPSIZE, /* 1566 */ + IC_64BIT_REXW_XS, /* 1567 */ + IC_ADSIZE, /* 1568 */ + IC_64BIT_ADSIZE, /* 1569 */ + IC_XS_ADSIZE, /* 1570 */ + IC_64BIT_XS_ADSIZE, /* 1571 */ + IC_XD_ADSIZE, /* 1572 */ + IC_64BIT_XD_ADSIZE, /* 1573 */ + IC_XS_ADSIZE, /* 1574 */ + IC_64BIT_XD_ADSIZE, /* 1575 */ + IC_ADSIZE, /* 1576 */ + IC_64BIT_REXW_ADSIZE, /* 1577 */ + IC_XS_ADSIZE, /* 1578 */ + IC_64BIT_REXW_XS, /* 1579 */ + IC_XD_ADSIZE, /* 1580 */ + IC_64BIT_REXW_XD, /* 1581 */ + IC_XS_ADSIZE, /* 1582 */ + IC_64BIT_REXW_XS, /* 1583 */ + IC_OPSIZE_ADSIZE, /* 1584 */ + IC_64BIT_OPSIZE_ADSIZE, /* 1585 */ + IC_XS_OPSIZE, /* 1586 */ + IC_64BIT_XS_OPSIZE, /* 1587 */ + IC_XD_OPSIZE, /* 1588 */ + IC_64BIT_XD_OPSIZE, /* 1589 */ + IC_XS_OPSIZE, /* 1590 */ + IC_64BIT_XD_OPSIZE, /* 1591 */ + IC_OPSIZE_ADSIZE, /* 1592 */ + IC_64BIT_REXW_OPSIZE, /* 1593 */ + IC_XS_OPSIZE, /* 1594 */ + IC_64BIT_REXW_XS, /* 1595 */ + IC_XD_OPSIZE, /* 1596 */ + IC_64BIT_REXW_XD, /* 1597 */ + IC_XS_OPSIZE, /* 1598 */ + IC_64BIT_REXW_XS, /* 1599 */ + IC_VEX, /* 1600 */ + IC_VEX, /* 1601 */ + IC_VEX_XS, /* 1602 */ + IC_VEX_XS, /* 1603 */ + IC_VEX_XD, /* 1604 */ + IC_VEX_XD, /* 1605 */ + IC_VEX_XD, /* 1606 */ + IC_VEX_XD, /* 1607 */ + IC_VEX_W, /* 1608 */ + IC_VEX_W, /* 1609 */ + IC_VEX_W_XS, /* 1610 */ + IC_VEX_W_XS, /* 1611 */ + IC_VEX_W_XD, /* 1612 */ + IC_VEX_W_XD, /* 1613 */ + IC_VEX_W_XD, /* 1614 */ + IC_VEX_W_XD, /* 1615 */ + IC_VEX_OPSIZE, /* 1616 */ + IC_VEX_OPSIZE, /* 1617 */ + IC_VEX_OPSIZE, /* 1618 */ + IC_VEX_OPSIZE, /* 1619 */ + IC_VEX_OPSIZE, /* 1620 */ + IC_VEX_OPSIZE, /* 1621 */ + IC_VEX_OPSIZE, /* 1622 */ + IC_VEX_OPSIZE, /* 1623 */ + IC_VEX_W_OPSIZE, /* 1624 */ + IC_VEX_W_OPSIZE, /* 1625 */ + IC_VEX_W_OPSIZE, /* 1626 */ + IC_VEX_W_OPSIZE, /* 1627 */ + IC_VEX_W_OPSIZE, /* 1628 */ + IC_VEX_W_OPSIZE, /* 1629 */ + IC_VEX_W_OPSIZE, /* 1630 */ + IC_VEX_W_OPSIZE, /* 1631 */ + IC_VEX, /* 1632 */ + IC_VEX, /* 1633 */ + IC_VEX_XS, /* 1634 */ + IC_VEX_XS, /* 1635 */ + IC_VEX_XD, /* 1636 */ + IC_VEX_XD, /* 1637 */ + IC_VEX_XD, /* 1638 */ + IC_VEX_XD, /* 1639 */ + IC_VEX_W, /* 1640 */ + IC_VEX_W, /* 1641 */ + IC_VEX_W_XS, /* 1642 */ + IC_VEX_W_XS, /* 1643 */ + IC_VEX_W_XD, /* 1644 */ + IC_VEX_W_XD, /* 1645 */ + IC_VEX_W_XD, /* 1646 */ + IC_VEX_W_XD, /* 1647 */ + IC_VEX_OPSIZE, /* 1648 */ + IC_VEX_OPSIZE, /* 1649 */ + IC_VEX_OPSIZE, /* 1650 */ + IC_VEX_OPSIZE, /* 1651 */ + IC_VEX_OPSIZE, /* 1652 */ + IC_VEX_OPSIZE, /* 1653 */ + IC_VEX_OPSIZE, /* 1654 */ + IC_VEX_OPSIZE, /* 1655 */ + IC_VEX_W_OPSIZE, /* 1656 */ + IC_VEX_W_OPSIZE, /* 1657 */ + IC_VEX_W_OPSIZE, /* 1658 */ + IC_VEX_W_OPSIZE, /* 1659 */ + IC_VEX_W_OPSIZE, /* 1660 */ + IC_VEX_W_OPSIZE, /* 1661 */ + IC_VEX_W_OPSIZE, /* 1662 */ + IC_VEX_W_OPSIZE, /* 1663 */ + IC_VEX_L, /* 1664 */ + IC_VEX_L, /* 1665 */ + IC_VEX_L_XS, /* 1666 */ + IC_VEX_L_XS, /* 1667 */ + IC_VEX_L_XD, /* 1668 */ + IC_VEX_L_XD, /* 1669 */ + IC_VEX_L_XD, /* 1670 */ + IC_VEX_L_XD, /* 1671 */ + IC_VEX_L_W, /* 1672 */ + IC_VEX_L_W, /* 1673 */ + IC_VEX_L_W_XS, /* 1674 */ + IC_VEX_L_W_XS, /* 1675 */ + IC_VEX_L_W_XD, /* 1676 */ + IC_VEX_L_W_XD, /* 1677 */ + IC_VEX_L_W_XD, /* 1678 */ + IC_VEX_L_W_XD, /* 1679 */ + IC_VEX_L_OPSIZE, /* 1680 */ + IC_VEX_L_OPSIZE, /* 1681 */ + IC_VEX_L_OPSIZE, /* 1682 */ + IC_VEX_L_OPSIZE, /* 1683 */ + IC_VEX_L_OPSIZE, /* 1684 */ + IC_VEX_L_OPSIZE, /* 1685 */ + IC_VEX_L_OPSIZE, /* 1686 */ + IC_VEX_L_OPSIZE, /* 1687 */ + IC_VEX_L_W_OPSIZE, /* 1688 */ + IC_VEX_L_W_OPSIZE, /* 1689 */ + IC_VEX_L_W_OPSIZE, /* 1690 */ + IC_VEX_L_W_OPSIZE, /* 1691 */ + IC_VEX_L_W_OPSIZE, /* 1692 */ + IC_VEX_L_W_OPSIZE, /* 1693 */ + IC_VEX_L_W_OPSIZE, /* 1694 */ + IC_VEX_L_W_OPSIZE, /* 1695 */ + IC_VEX_L, /* 1696 */ + IC_VEX_L, /* 1697 */ + IC_VEX_L_XS, /* 1698 */ + IC_VEX_L_XS, /* 1699 */ + IC_VEX_L_XD, /* 1700 */ + IC_VEX_L_XD, /* 1701 */ + IC_VEX_L_XD, /* 1702 */ + IC_VEX_L_XD, /* 1703 */ + IC_VEX_L_W, /* 1704 */ + IC_VEX_L_W, /* 1705 */ + IC_VEX_L_W_XS, /* 1706 */ + IC_VEX_L_W_XS, /* 1707 */ + IC_VEX_L_W_XD, /* 1708 */ + IC_VEX_L_W_XD, /* 1709 */ + IC_VEX_L_W_XD, /* 1710 */ + IC_VEX_L_W_XD, /* 1711 */ + IC_VEX_L_OPSIZE, /* 1712 */ + IC_VEX_L_OPSIZE, /* 1713 */ + IC_VEX_L_OPSIZE, /* 1714 */ + IC_VEX_L_OPSIZE, /* 1715 */ + IC_VEX_L_OPSIZE, /* 1716 */ + IC_VEX_L_OPSIZE, /* 1717 */ + IC_VEX_L_OPSIZE, /* 1718 */ + IC_VEX_L_OPSIZE, /* 1719 */ + IC_VEX_L_W_OPSIZE, /* 1720 */ + IC_VEX_L_W_OPSIZE, /* 1721 */ + IC_VEX_L_W_OPSIZE, /* 1722 */ + IC_VEX_L_W_OPSIZE, /* 1723 */ + IC_VEX_L_W_OPSIZE, /* 1724 */ + IC_VEX_L_W_OPSIZE, /* 1725 */ + IC_VEX_L_W_OPSIZE, /* 1726 */ + IC_VEX_L_W_OPSIZE, /* 1727 */ + IC_VEX_L, /* 1728 */ + IC_VEX_L, /* 1729 */ + IC_VEX_L_XS, /* 1730 */ + IC_VEX_L_XS, /* 1731 */ + IC_VEX_L_XD, /* 1732 */ + IC_VEX_L_XD, /* 1733 */ + IC_VEX_L_XD, /* 1734 */ + IC_VEX_L_XD, /* 1735 */ + IC_VEX_L_W, /* 1736 */ + IC_VEX_L_W, /* 1737 */ + IC_VEX_L_W_XS, /* 1738 */ + IC_VEX_L_W_XS, /* 1739 */ + IC_VEX_L_W_XD, /* 1740 */ + IC_VEX_L_W_XD, /* 1741 */ + IC_VEX_L_W_XD, /* 1742 */ + IC_VEX_L_W_XD, /* 1743 */ + IC_VEX_L_OPSIZE, /* 1744 */ + IC_VEX_L_OPSIZE, /* 1745 */ + IC_VEX_L_OPSIZE, /* 1746 */ + IC_VEX_L_OPSIZE, /* 1747 */ + IC_VEX_L_OPSIZE, /* 1748 */ + IC_VEX_L_OPSIZE, /* 1749 */ + IC_VEX_L_OPSIZE, /* 1750 */ + IC_VEX_L_OPSIZE, /* 1751 */ + IC_VEX_L_W_OPSIZE, /* 1752 */ + IC_VEX_L_W_OPSIZE, /* 1753 */ + IC_VEX_L_W_OPSIZE, /* 1754 */ + IC_VEX_L_W_OPSIZE, /* 1755 */ + IC_VEX_L_W_OPSIZE, /* 1756 */ + IC_VEX_L_W_OPSIZE, /* 1757 */ + IC_VEX_L_W_OPSIZE, /* 1758 */ + IC_VEX_L_W_OPSIZE, /* 1759 */ + IC_VEX_L, /* 1760 */ + IC_VEX_L, /* 1761 */ + IC_VEX_L_XS, /* 1762 */ + IC_VEX_L_XS, /* 1763 */ + IC_VEX_L_XD, /* 1764 */ + IC_VEX_L_XD, /* 1765 */ + IC_VEX_L_XD, /* 1766 */ + IC_VEX_L_XD, /* 1767 */ + IC_VEX_L_W, /* 1768 */ + IC_VEX_L_W, /* 1769 */ + IC_VEX_L_W_XS, /* 1770 */ + IC_VEX_L_W_XS, /* 1771 */ + IC_VEX_L_W_XD, /* 1772 */ + IC_VEX_L_W_XD, /* 1773 */ + IC_VEX_L_W_XD, /* 1774 */ + IC_VEX_L_W_XD, /* 1775 */ + IC_VEX_L_OPSIZE, /* 1776 */ + IC_VEX_L_OPSIZE, /* 1777 */ + IC_VEX_L_OPSIZE, /* 1778 */ + IC_VEX_L_OPSIZE, /* 1779 */ + IC_VEX_L_OPSIZE, /* 1780 */ + IC_VEX_L_OPSIZE, /* 1781 */ + IC_VEX_L_OPSIZE, /* 1782 */ + IC_VEX_L_OPSIZE, /* 1783 */ + IC_VEX_L_W_OPSIZE, /* 1784 */ + IC_VEX_L_W_OPSIZE, /* 1785 */ + IC_VEX_L_W_OPSIZE, /* 1786 */ + IC_VEX_L_W_OPSIZE, /* 1787 */ + IC_VEX_L_W_OPSIZE, /* 1788 */ + IC_VEX_L_W_OPSIZE, /* 1789 */ + IC_VEX_L_W_OPSIZE, /* 1790 */ + IC_VEX_L_W_OPSIZE, /* 1791 */ + IC_EVEX_L2, /* 1792 */ + IC_EVEX_L2, /* 1793 */ + IC_EVEX_L2_XS, /* 1794 */ + IC_EVEX_L2_XS, /* 1795 */ + IC_EVEX_L2_XD, /* 1796 */ + IC_EVEX_L2_XD, /* 1797 */ + IC_EVEX_L2_XD, /* 1798 */ + IC_EVEX_L2_XD, /* 1799 */ + IC_EVEX_L2_W, /* 1800 */ + IC_EVEX_L2_W, /* 1801 */ + IC_EVEX_L2_W_XS, /* 1802 */ + IC_EVEX_L2_W_XS, /* 1803 */ + IC_EVEX_L2_W_XD, /* 1804 */ + IC_EVEX_L2_W_XD, /* 1805 */ + IC_EVEX_L2_W_XD, /* 1806 */ + IC_EVEX_L2_W_XD, /* 1807 */ + IC_EVEX_L2_OPSIZE, /* 1808 */ + IC_EVEX_L2_OPSIZE, /* 1809 */ + IC_EVEX_L2_OPSIZE, /* 1810 */ + IC_EVEX_L2_OPSIZE, /* 1811 */ + IC_EVEX_L2_OPSIZE, /* 1812 */ + IC_EVEX_L2_OPSIZE, /* 1813 */ + IC_EVEX_L2_OPSIZE, /* 1814 */ + IC_EVEX_L2_OPSIZE, /* 1815 */ + IC_EVEX_L2_W_OPSIZE, /* 1816 */ + IC_EVEX_L2_W_OPSIZE, /* 1817 */ + IC_EVEX_L2_W_OPSIZE, /* 1818 */ + IC_EVEX_L2_W_OPSIZE, /* 1819 */ + IC_EVEX_L2_W_OPSIZE, /* 1820 */ + IC_EVEX_L2_W_OPSIZE, /* 1821 */ + IC_EVEX_L2_W_OPSIZE, /* 1822 */ + IC_EVEX_L2_W_OPSIZE, /* 1823 */ + IC_EVEX_L2, /* 1824 */ + IC_EVEX_L2, /* 1825 */ + IC_EVEX_L2_XS, /* 1826 */ + IC_EVEX_L2_XS, /* 1827 */ + IC_EVEX_L2_XD, /* 1828 */ + IC_EVEX_L2_XD, /* 1829 */ + IC_EVEX_L2_XD, /* 1830 */ + IC_EVEX_L2_XD, /* 1831 */ + IC_EVEX_L2_W, /* 1832 */ + IC_EVEX_L2_W, /* 1833 */ + IC_EVEX_L2_W_XS, /* 1834 */ + IC_EVEX_L2_W_XS, /* 1835 */ + IC_EVEX_L2_W_XD, /* 1836 */ + IC_EVEX_L2_W_XD, /* 1837 */ + IC_EVEX_L2_W_XD, /* 1838 */ + IC_EVEX_L2_W_XD, /* 1839 */ + IC_EVEX_L2_OPSIZE, /* 1840 */ + IC_EVEX_L2_OPSIZE, /* 1841 */ + IC_EVEX_L2_OPSIZE, /* 1842 */ + IC_EVEX_L2_OPSIZE, /* 1843 */ + IC_EVEX_L2_OPSIZE, /* 1844 */ + IC_EVEX_L2_OPSIZE, /* 1845 */ + IC_EVEX_L2_OPSIZE, /* 1846 */ + IC_EVEX_L2_OPSIZE, /* 1847 */ + IC_EVEX_L2_W_OPSIZE, /* 1848 */ + IC_EVEX_L2_W_OPSIZE, /* 1849 */ + IC_EVEX_L2_W_OPSIZE, /* 1850 */ + IC_EVEX_L2_W_OPSIZE, /* 1851 */ + IC_EVEX_L2_W_OPSIZE, /* 1852 */ + IC_EVEX_L2_W_OPSIZE, /* 1853 */ + IC_EVEX_L2_W_OPSIZE, /* 1854 */ + IC_EVEX_L2_W_OPSIZE, /* 1855 */ + IC_EVEX_L2, /* 1856 */ + IC_EVEX_L2, /* 1857 */ + IC_EVEX_L2_XS, /* 1858 */ + IC_EVEX_L2_XS, /* 1859 */ + IC_EVEX_L2_XD, /* 1860 */ + IC_EVEX_L2_XD, /* 1861 */ + IC_EVEX_L2_XD, /* 1862 */ + IC_EVEX_L2_XD, /* 1863 */ + IC_EVEX_L2_W, /* 1864 */ + IC_EVEX_L2_W, /* 1865 */ + IC_EVEX_L2_W_XS, /* 1866 */ + IC_EVEX_L2_W_XS, /* 1867 */ + IC_EVEX_L2_W_XD, /* 1868 */ + IC_EVEX_L2_W_XD, /* 1869 */ + IC_EVEX_L2_W_XD, /* 1870 */ + IC_EVEX_L2_W_XD, /* 1871 */ + IC_EVEX_L2_OPSIZE, /* 1872 */ + IC_EVEX_L2_OPSIZE, /* 1873 */ + IC_EVEX_L2_OPSIZE, /* 1874 */ + IC_EVEX_L2_OPSIZE, /* 1875 */ + IC_EVEX_L2_OPSIZE, /* 1876 */ + IC_EVEX_L2_OPSIZE, /* 1877 */ + IC_EVEX_L2_OPSIZE, /* 1878 */ + IC_EVEX_L2_OPSIZE, /* 1879 */ + IC_EVEX_L2_W_OPSIZE, /* 1880 */ + IC_EVEX_L2_W_OPSIZE, /* 1881 */ + IC_EVEX_L2_W_OPSIZE, /* 1882 */ + IC_EVEX_L2_W_OPSIZE, /* 1883 */ + IC_EVEX_L2_W_OPSIZE, /* 1884 */ + IC_EVEX_L2_W_OPSIZE, /* 1885 */ + IC_EVEX_L2_W_OPSIZE, /* 1886 */ + IC_EVEX_L2_W_OPSIZE, /* 1887 */ + IC_EVEX_L2, /* 1888 */ + IC_EVEX_L2, /* 1889 */ + IC_EVEX_L2_XS, /* 1890 */ + IC_EVEX_L2_XS, /* 1891 */ + IC_EVEX_L2_XD, /* 1892 */ + IC_EVEX_L2_XD, /* 1893 */ + IC_EVEX_L2_XD, /* 1894 */ + IC_EVEX_L2_XD, /* 1895 */ + IC_EVEX_L2_W, /* 1896 */ + IC_EVEX_L2_W, /* 1897 */ + IC_EVEX_L2_W_XS, /* 1898 */ + IC_EVEX_L2_W_XS, /* 1899 */ + IC_EVEX_L2_W_XD, /* 1900 */ + IC_EVEX_L2_W_XD, /* 1901 */ + IC_EVEX_L2_W_XD, /* 1902 */ + IC_EVEX_L2_W_XD, /* 1903 */ + IC_EVEX_L2_OPSIZE, /* 1904 */ + IC_EVEX_L2_OPSIZE, /* 1905 */ + IC_EVEX_L2_OPSIZE, /* 1906 */ + IC_EVEX_L2_OPSIZE, /* 1907 */ + IC_EVEX_L2_OPSIZE, /* 1908 */ + IC_EVEX_L2_OPSIZE, /* 1909 */ + IC_EVEX_L2_OPSIZE, /* 1910 */ + IC_EVEX_L2_OPSIZE, /* 1911 */ + IC_EVEX_L2_W_OPSIZE, /* 1912 */ + IC_EVEX_L2_W_OPSIZE, /* 1913 */ + IC_EVEX_L2_W_OPSIZE, /* 1914 */ + IC_EVEX_L2_W_OPSIZE, /* 1915 */ + IC_EVEX_L2_W_OPSIZE, /* 1916 */ + IC_EVEX_L2_W_OPSIZE, /* 1917 */ + IC_EVEX_L2_W_OPSIZE, /* 1918 */ + IC_EVEX_L2_W_OPSIZE, /* 1919 */ + IC_EVEX_L2, /* 1920 */ + IC_EVEX_L2, /* 1921 */ + IC_EVEX_L2_XS, /* 1922 */ + IC_EVEX_L2_XS, /* 1923 */ + IC_EVEX_L2_XD, /* 1924 */ + IC_EVEX_L2_XD, /* 1925 */ + IC_EVEX_L2_XD, /* 1926 */ + IC_EVEX_L2_XD, /* 1927 */ + IC_EVEX_L2_W, /* 1928 */ + IC_EVEX_L2_W, /* 1929 */ + IC_EVEX_L2_W_XS, /* 1930 */ + IC_EVEX_L2_W_XS, /* 1931 */ + IC_EVEX_L2_W_XD, /* 1932 */ + IC_EVEX_L2_W_XD, /* 1933 */ + IC_EVEX_L2_W_XD, /* 1934 */ + IC_EVEX_L2_W_XD, /* 1935 */ + IC_EVEX_L2_OPSIZE, /* 1936 */ + IC_EVEX_L2_OPSIZE, /* 1937 */ + IC_EVEX_L2_OPSIZE, /* 1938 */ + IC_EVEX_L2_OPSIZE, /* 1939 */ + IC_EVEX_L2_OPSIZE, /* 1940 */ + IC_EVEX_L2_OPSIZE, /* 1941 */ + IC_EVEX_L2_OPSIZE, /* 1942 */ + IC_EVEX_L2_OPSIZE, /* 1943 */ + IC_EVEX_L2_W_OPSIZE, /* 1944 */ + IC_EVEX_L2_W_OPSIZE, /* 1945 */ + IC_EVEX_L2_W_OPSIZE, /* 1946 */ + IC_EVEX_L2_W_OPSIZE, /* 1947 */ + IC_EVEX_L2_W_OPSIZE, /* 1948 */ + IC_EVEX_L2_W_OPSIZE, /* 1949 */ + IC_EVEX_L2_W_OPSIZE, /* 1950 */ + IC_EVEX_L2_W_OPSIZE, /* 1951 */ + IC_EVEX_L2, /* 1952 */ + IC_EVEX_L2, /* 1953 */ + IC_EVEX_L2_XS, /* 1954 */ + IC_EVEX_L2_XS, /* 1955 */ + IC_EVEX_L2_XD, /* 1956 */ + IC_EVEX_L2_XD, /* 1957 */ + IC_EVEX_L2_XD, /* 1958 */ + IC_EVEX_L2_XD, /* 1959 */ + IC_EVEX_L2_W, /* 1960 */ + IC_EVEX_L2_W, /* 1961 */ + IC_EVEX_L2_W_XS, /* 1962 */ + IC_EVEX_L2_W_XS, /* 1963 */ + IC_EVEX_L2_W_XD, /* 1964 */ + IC_EVEX_L2_W_XD, /* 1965 */ + IC_EVEX_L2_W_XD, /* 1966 */ + IC_EVEX_L2_W_XD, /* 1967 */ + IC_EVEX_L2_OPSIZE, /* 1968 */ + IC_EVEX_L2_OPSIZE, /* 1969 */ + IC_EVEX_L2_OPSIZE, /* 1970 */ + IC_EVEX_L2_OPSIZE, /* 1971 */ + IC_EVEX_L2_OPSIZE, /* 1972 */ + IC_EVEX_L2_OPSIZE, /* 1973 */ + IC_EVEX_L2_OPSIZE, /* 1974 */ + IC_EVEX_L2_OPSIZE, /* 1975 */ + IC_EVEX_L2_W_OPSIZE, /* 1976 */ + IC_EVEX_L2_W_OPSIZE, /* 1977 */ + IC_EVEX_L2_W_OPSIZE, /* 1978 */ + IC_EVEX_L2_W_OPSIZE, /* 1979 */ + IC_EVEX_L2_W_OPSIZE, /* 1980 */ + IC_EVEX_L2_W_OPSIZE, /* 1981 */ + IC_EVEX_L2_W_OPSIZE, /* 1982 */ + IC_EVEX_L2_W_OPSIZE, /* 1983 */ + IC_EVEX_L2, /* 1984 */ + IC_EVEX_L2, /* 1985 */ + IC_EVEX_L2_XS, /* 1986 */ + IC_EVEX_L2_XS, /* 1987 */ + IC_EVEX_L2_XD, /* 1988 */ + IC_EVEX_L2_XD, /* 1989 */ + IC_EVEX_L2_XD, /* 1990 */ + IC_EVEX_L2_XD, /* 1991 */ + IC_EVEX_L2_W, /* 1992 */ + IC_EVEX_L2_W, /* 1993 */ + IC_EVEX_L2_W_XS, /* 1994 */ + IC_EVEX_L2_W_XS, /* 1995 */ + IC_EVEX_L2_W_XD, /* 1996 */ + IC_EVEX_L2_W_XD, /* 1997 */ + IC_EVEX_L2_W_XD, /* 1998 */ + IC_EVEX_L2_W_XD, /* 1999 */ + IC_EVEX_L2_OPSIZE, /* 2000 */ + IC_EVEX_L2_OPSIZE, /* 2001 */ + IC_EVEX_L2_OPSIZE, /* 2002 */ + IC_EVEX_L2_OPSIZE, /* 2003 */ + IC_EVEX_L2_OPSIZE, /* 2004 */ + IC_EVEX_L2_OPSIZE, /* 2005 */ + IC_EVEX_L2_OPSIZE, /* 2006 */ + IC_EVEX_L2_OPSIZE, /* 2007 */ + IC_EVEX_L2_W_OPSIZE, /* 2008 */ + IC_EVEX_L2_W_OPSIZE, /* 2009 */ + IC_EVEX_L2_W_OPSIZE, /* 2010 */ + IC_EVEX_L2_W_OPSIZE, /* 2011 */ + IC_EVEX_L2_W_OPSIZE, /* 2012 */ + IC_EVEX_L2_W_OPSIZE, /* 2013 */ + IC_EVEX_L2_W_OPSIZE, /* 2014 */ + IC_EVEX_L2_W_OPSIZE, /* 2015 */ + IC_EVEX_L2, /* 2016 */ + IC_EVEX_L2, /* 2017 */ + IC_EVEX_L2_XS, /* 2018 */ + IC_EVEX_L2_XS, /* 2019 */ + IC_EVEX_L2_XD, /* 2020 */ + IC_EVEX_L2_XD, /* 2021 */ + IC_EVEX_L2_XD, /* 2022 */ + IC_EVEX_L2_XD, /* 2023 */ + IC_EVEX_L2_W, /* 2024 */ + IC_EVEX_L2_W, /* 2025 */ + IC_EVEX_L2_W_XS, /* 2026 */ + IC_EVEX_L2_W_XS, /* 2027 */ + IC_EVEX_L2_W_XD, /* 2028 */ + IC_EVEX_L2_W_XD, /* 2029 */ + IC_EVEX_L2_W_XD, /* 2030 */ + IC_EVEX_L2_W_XD, /* 2031 */ + IC_EVEX_L2_OPSIZE, /* 2032 */ + IC_EVEX_L2_OPSIZE, /* 2033 */ + IC_EVEX_L2_OPSIZE, /* 2034 */ + IC_EVEX_L2_OPSIZE, /* 2035 */ + IC_EVEX_L2_OPSIZE, /* 2036 */ + IC_EVEX_L2_OPSIZE, /* 2037 */ + IC_EVEX_L2_OPSIZE, /* 2038 */ + IC_EVEX_L2_OPSIZE, /* 2039 */ + IC_EVEX_L2_W_OPSIZE, /* 2040 */ + IC_EVEX_L2_W_OPSIZE, /* 2041 */ + IC_EVEX_L2_W_OPSIZE, /* 2042 */ + IC_EVEX_L2_W_OPSIZE, /* 2043 */ + IC_EVEX_L2_W_OPSIZE, /* 2044 */ + IC_EVEX_L2_W_OPSIZE, /* 2045 */ + IC_EVEX_L2_W_OPSIZE, /* 2046 */ + IC_EVEX_L2_W_OPSIZE, /* 2047 */ + IC, /* 2048 */ + IC_64BIT, /* 2049 */ + IC_XS, /* 2050 */ + IC_64BIT_XS, /* 2051 */ + IC_XD, /* 2052 */ + IC_64BIT_XD, /* 2053 */ + IC_XS, /* 2054 */ + IC_64BIT_XS, /* 2055 */ + IC, /* 2056 */ + IC_64BIT_REXW, /* 2057 */ + IC_XS, /* 2058 */ + IC_64BIT_REXW_XS, /* 2059 */ + IC_XD, /* 2060 */ + IC_64BIT_REXW_XD, /* 2061 */ + IC_XS, /* 2062 */ + IC_64BIT_REXW_XS, /* 2063 */ + IC_OPSIZE, /* 2064 */ + IC_64BIT_OPSIZE, /* 2065 */ + IC_XS_OPSIZE, /* 2066 */ + IC_64BIT_XS_OPSIZE, /* 2067 */ + IC_XD_OPSIZE, /* 2068 */ + IC_64BIT_XD_OPSIZE, /* 2069 */ + IC_XS_OPSIZE, /* 2070 */ + IC_64BIT_XD_OPSIZE, /* 2071 */ + IC_OPSIZE, /* 2072 */ + IC_64BIT_REXW_OPSIZE, /* 2073 */ + IC_XS_OPSIZE, /* 2074 */ + IC_64BIT_REXW_XS, /* 2075 */ + IC_XD_OPSIZE, /* 2076 */ + IC_64BIT_REXW_XD, /* 2077 */ + IC_XS_OPSIZE, /* 2078 */ + IC_64BIT_REXW_XS, /* 2079 */ + IC_ADSIZE, /* 2080 */ + IC_64BIT_ADSIZE, /* 2081 */ + IC_XS_ADSIZE, /* 2082 */ + IC_64BIT_XS_ADSIZE, /* 2083 */ + IC_XD_ADSIZE, /* 2084 */ + IC_64BIT_XD_ADSIZE, /* 2085 */ + IC_XS_ADSIZE, /* 2086 */ + IC_64BIT_XD_ADSIZE, /* 2087 */ + IC_ADSIZE, /* 2088 */ + IC_64BIT_REXW_ADSIZE, /* 2089 */ + IC_XS_ADSIZE, /* 2090 */ + IC_64BIT_REXW_XS, /* 2091 */ + IC_XD_ADSIZE, /* 2092 */ + IC_64BIT_REXW_XD, /* 2093 */ + IC_XS_ADSIZE, /* 2094 */ + IC_64BIT_REXW_XS, /* 2095 */ + IC_OPSIZE_ADSIZE, /* 2096 */ + IC_64BIT_OPSIZE_ADSIZE, /* 2097 */ + IC_XS_OPSIZE, /* 2098 */ + IC_64BIT_XS_OPSIZE, /* 2099 */ + IC_XD_OPSIZE, /* 2100 */ + IC_64BIT_XD_OPSIZE, /* 2101 */ + IC_XS_OPSIZE, /* 2102 */ + IC_64BIT_XD_OPSIZE, /* 2103 */ + IC_OPSIZE_ADSIZE, /* 2104 */ + IC_64BIT_REXW_OPSIZE, /* 2105 */ + IC_XS_OPSIZE, /* 2106 */ + IC_64BIT_REXW_XS, /* 2107 */ + IC_XD_OPSIZE, /* 2108 */ + IC_64BIT_REXW_XD, /* 2109 */ + IC_XS_OPSIZE, /* 2110 */ + IC_64BIT_REXW_XS, /* 2111 */ + IC_VEX, /* 2112 */ + IC_VEX, /* 2113 */ + IC_VEX_XS, /* 2114 */ + IC_VEX_XS, /* 2115 */ + IC_VEX_XD, /* 2116 */ + IC_VEX_XD, /* 2117 */ + IC_VEX_XD, /* 2118 */ + IC_VEX_XD, /* 2119 */ + IC_VEX_W, /* 2120 */ + IC_VEX_W, /* 2121 */ + IC_VEX_W_XS, /* 2122 */ + IC_VEX_W_XS, /* 2123 */ + IC_VEX_W_XD, /* 2124 */ + IC_VEX_W_XD, /* 2125 */ + IC_VEX_W_XD, /* 2126 */ + IC_VEX_W_XD, /* 2127 */ + IC_VEX_OPSIZE, /* 2128 */ + IC_VEX_OPSIZE, /* 2129 */ + IC_VEX_OPSIZE, /* 2130 */ + IC_VEX_OPSIZE, /* 2131 */ + IC_VEX_OPSIZE, /* 2132 */ + IC_VEX_OPSIZE, /* 2133 */ + IC_VEX_OPSIZE, /* 2134 */ + IC_VEX_OPSIZE, /* 2135 */ + IC_VEX_W_OPSIZE, /* 2136 */ + IC_VEX_W_OPSIZE, /* 2137 */ + IC_VEX_W_OPSIZE, /* 2138 */ + IC_VEX_W_OPSIZE, /* 2139 */ + IC_VEX_W_OPSIZE, /* 2140 */ + IC_VEX_W_OPSIZE, /* 2141 */ + IC_VEX_W_OPSIZE, /* 2142 */ + IC_VEX_W_OPSIZE, /* 2143 */ + IC_VEX, /* 2144 */ + IC_VEX, /* 2145 */ + IC_VEX_XS, /* 2146 */ + IC_VEX_XS, /* 2147 */ + IC_VEX_XD, /* 2148 */ + IC_VEX_XD, /* 2149 */ + IC_VEX_XD, /* 2150 */ + IC_VEX_XD, /* 2151 */ + IC_VEX_W, /* 2152 */ + IC_VEX_W, /* 2153 */ + IC_VEX_W_XS, /* 2154 */ + IC_VEX_W_XS, /* 2155 */ + IC_VEX_W_XD, /* 2156 */ + IC_VEX_W_XD, /* 2157 */ + IC_VEX_W_XD, /* 2158 */ + IC_VEX_W_XD, /* 2159 */ + IC_VEX_OPSIZE, /* 2160 */ + IC_VEX_OPSIZE, /* 2161 */ + IC_VEX_OPSIZE, /* 2162 */ + IC_VEX_OPSIZE, /* 2163 */ + IC_VEX_OPSIZE, /* 2164 */ + IC_VEX_OPSIZE, /* 2165 */ + IC_VEX_OPSIZE, /* 2166 */ + IC_VEX_OPSIZE, /* 2167 */ + IC_VEX_W_OPSIZE, /* 2168 */ + IC_VEX_W_OPSIZE, /* 2169 */ + IC_VEX_W_OPSIZE, /* 2170 */ + IC_VEX_W_OPSIZE, /* 2171 */ + IC_VEX_W_OPSIZE, /* 2172 */ + IC_VEX_W_OPSIZE, /* 2173 */ + IC_VEX_W_OPSIZE, /* 2174 */ + IC_VEX_W_OPSIZE, /* 2175 */ + IC_VEX_L, /* 2176 */ + IC_VEX_L, /* 2177 */ + IC_VEX_L_XS, /* 2178 */ + IC_VEX_L_XS, /* 2179 */ + IC_VEX_L_XD, /* 2180 */ + IC_VEX_L_XD, /* 2181 */ + IC_VEX_L_XD, /* 2182 */ + IC_VEX_L_XD, /* 2183 */ + IC_VEX_L_W, /* 2184 */ + IC_VEX_L_W, /* 2185 */ + IC_VEX_L_W_XS, /* 2186 */ + IC_VEX_L_W_XS, /* 2187 */ + IC_VEX_L_W_XD, /* 2188 */ + IC_VEX_L_W_XD, /* 2189 */ + IC_VEX_L_W_XD, /* 2190 */ + IC_VEX_L_W_XD, /* 2191 */ + IC_VEX_L_OPSIZE, /* 2192 */ + IC_VEX_L_OPSIZE, /* 2193 */ + IC_VEX_L_OPSIZE, /* 2194 */ + IC_VEX_L_OPSIZE, /* 2195 */ + IC_VEX_L_OPSIZE, /* 2196 */ + IC_VEX_L_OPSIZE, /* 2197 */ + IC_VEX_L_OPSIZE, /* 2198 */ + IC_VEX_L_OPSIZE, /* 2199 */ + IC_VEX_L_W_OPSIZE, /* 2200 */ + IC_VEX_L_W_OPSIZE, /* 2201 */ + IC_VEX_L_W_OPSIZE, /* 2202 */ + IC_VEX_L_W_OPSIZE, /* 2203 */ + IC_VEX_L_W_OPSIZE, /* 2204 */ + IC_VEX_L_W_OPSIZE, /* 2205 */ + IC_VEX_L_W_OPSIZE, /* 2206 */ + IC_VEX_L_W_OPSIZE, /* 2207 */ + IC_VEX_L, /* 2208 */ + IC_VEX_L, /* 2209 */ + IC_VEX_L_XS, /* 2210 */ + IC_VEX_L_XS, /* 2211 */ + IC_VEX_L_XD, /* 2212 */ + IC_VEX_L_XD, /* 2213 */ + IC_VEX_L_XD, /* 2214 */ + IC_VEX_L_XD, /* 2215 */ + IC_VEX_L_W, /* 2216 */ + IC_VEX_L_W, /* 2217 */ + IC_VEX_L_W_XS, /* 2218 */ + IC_VEX_L_W_XS, /* 2219 */ + IC_VEX_L_W_XD, /* 2220 */ + IC_VEX_L_W_XD, /* 2221 */ + IC_VEX_L_W_XD, /* 2222 */ + IC_VEX_L_W_XD, /* 2223 */ + IC_VEX_L_OPSIZE, /* 2224 */ + IC_VEX_L_OPSIZE, /* 2225 */ + IC_VEX_L_OPSIZE, /* 2226 */ + IC_VEX_L_OPSIZE, /* 2227 */ + IC_VEX_L_OPSIZE, /* 2228 */ + IC_VEX_L_OPSIZE, /* 2229 */ + IC_VEX_L_OPSIZE, /* 2230 */ + IC_VEX_L_OPSIZE, /* 2231 */ + IC_VEX_L_W_OPSIZE, /* 2232 */ + IC_VEX_L_W_OPSIZE, /* 2233 */ + IC_VEX_L_W_OPSIZE, /* 2234 */ + IC_VEX_L_W_OPSIZE, /* 2235 */ + IC_VEX_L_W_OPSIZE, /* 2236 */ + IC_VEX_L_W_OPSIZE, /* 2237 */ + IC_VEX_L_W_OPSIZE, /* 2238 */ + IC_VEX_L_W_OPSIZE, /* 2239 */ + IC_VEX_L, /* 2240 */ + IC_VEX_L, /* 2241 */ + IC_VEX_L_XS, /* 2242 */ + IC_VEX_L_XS, /* 2243 */ + IC_VEX_L_XD, /* 2244 */ + IC_VEX_L_XD, /* 2245 */ + IC_VEX_L_XD, /* 2246 */ + IC_VEX_L_XD, /* 2247 */ + IC_VEX_L_W, /* 2248 */ + IC_VEX_L_W, /* 2249 */ + IC_VEX_L_W_XS, /* 2250 */ + IC_VEX_L_W_XS, /* 2251 */ + IC_VEX_L_W_XD, /* 2252 */ + IC_VEX_L_W_XD, /* 2253 */ + IC_VEX_L_W_XD, /* 2254 */ + IC_VEX_L_W_XD, /* 2255 */ + IC_VEX_L_OPSIZE, /* 2256 */ + IC_VEX_L_OPSIZE, /* 2257 */ + IC_VEX_L_OPSIZE, /* 2258 */ + IC_VEX_L_OPSIZE, /* 2259 */ + IC_VEX_L_OPSIZE, /* 2260 */ + IC_VEX_L_OPSIZE, /* 2261 */ + IC_VEX_L_OPSIZE, /* 2262 */ + IC_VEX_L_OPSIZE, /* 2263 */ + IC_VEX_L_W_OPSIZE, /* 2264 */ + IC_VEX_L_W_OPSIZE, /* 2265 */ + IC_VEX_L_W_OPSIZE, /* 2266 */ + IC_VEX_L_W_OPSIZE, /* 2267 */ + IC_VEX_L_W_OPSIZE, /* 2268 */ + IC_VEX_L_W_OPSIZE, /* 2269 */ + IC_VEX_L_W_OPSIZE, /* 2270 */ + IC_VEX_L_W_OPSIZE, /* 2271 */ + IC_VEX_L, /* 2272 */ + IC_VEX_L, /* 2273 */ + IC_VEX_L_XS, /* 2274 */ + IC_VEX_L_XS, /* 2275 */ + IC_VEX_L_XD, /* 2276 */ + IC_VEX_L_XD, /* 2277 */ + IC_VEX_L_XD, /* 2278 */ + IC_VEX_L_XD, /* 2279 */ + IC_VEX_L_W, /* 2280 */ + IC_VEX_L_W, /* 2281 */ + IC_VEX_L_W_XS, /* 2282 */ + IC_VEX_L_W_XS, /* 2283 */ + IC_VEX_L_W_XD, /* 2284 */ + IC_VEX_L_W_XD, /* 2285 */ + IC_VEX_L_W_XD, /* 2286 */ + IC_VEX_L_W_XD, /* 2287 */ + IC_VEX_L_OPSIZE, /* 2288 */ + IC_VEX_L_OPSIZE, /* 2289 */ + IC_VEX_L_OPSIZE, /* 2290 */ + IC_VEX_L_OPSIZE, /* 2291 */ + IC_VEX_L_OPSIZE, /* 2292 */ + IC_VEX_L_OPSIZE, /* 2293 */ + IC_VEX_L_OPSIZE, /* 2294 */ + IC_VEX_L_OPSIZE, /* 2295 */ + IC_VEX_L_W_OPSIZE, /* 2296 */ + IC_VEX_L_W_OPSIZE, /* 2297 */ + IC_VEX_L_W_OPSIZE, /* 2298 */ + IC_VEX_L_W_OPSIZE, /* 2299 */ + IC_VEX_L_W_OPSIZE, /* 2300 */ + IC_VEX_L_W_OPSIZE, /* 2301 */ + IC_VEX_L_W_OPSIZE, /* 2302 */ + IC_VEX_L_W_OPSIZE, /* 2303 */ + IC_EVEX_K, /* 2304 */ + IC_EVEX_K, /* 2305 */ + IC_EVEX_XS_K, /* 2306 */ + IC_EVEX_XS_K, /* 2307 */ + IC_EVEX_XD_K, /* 2308 */ + IC_EVEX_XD_K, /* 2309 */ + IC_EVEX_XD_K, /* 2310 */ + IC_EVEX_XD_K, /* 2311 */ + IC_EVEX_W_K, /* 2312 */ + IC_EVEX_W_K, /* 2313 */ + IC_EVEX_W_XS_K, /* 2314 */ + IC_EVEX_W_XS_K, /* 2315 */ + IC_EVEX_W_XD_K, /* 2316 */ + IC_EVEX_W_XD_K, /* 2317 */ + IC_EVEX_W_XD_K, /* 2318 */ + IC_EVEX_W_XD_K, /* 2319 */ + IC_EVEX_OPSIZE_K, /* 2320 */ + IC_EVEX_OPSIZE_K, /* 2321 */ + IC_EVEX_OPSIZE_K, /* 2322 */ + IC_EVEX_OPSIZE_K, /* 2323 */ + IC_EVEX_OPSIZE_K, /* 2324 */ + IC_EVEX_OPSIZE_K, /* 2325 */ + IC_EVEX_OPSIZE_K, /* 2326 */ + IC_EVEX_OPSIZE_K, /* 2327 */ + IC_EVEX_W_OPSIZE_K, /* 2328 */ + IC_EVEX_W_OPSIZE_K, /* 2329 */ + IC_EVEX_W_OPSIZE_K, /* 2330 */ + IC_EVEX_W_OPSIZE_K, /* 2331 */ + IC_EVEX_W_OPSIZE_K, /* 2332 */ + IC_EVEX_W_OPSIZE_K, /* 2333 */ + IC_EVEX_W_OPSIZE_K, /* 2334 */ + IC_EVEX_W_OPSIZE_K, /* 2335 */ + IC_EVEX_K, /* 2336 */ + IC_EVEX_K, /* 2337 */ + IC_EVEX_XS_K, /* 2338 */ + IC_EVEX_XS_K, /* 2339 */ + IC_EVEX_XD_K, /* 2340 */ + IC_EVEX_XD_K, /* 2341 */ + IC_EVEX_XD_K, /* 2342 */ + IC_EVEX_XD_K, /* 2343 */ + IC_EVEX_W_K, /* 2344 */ + IC_EVEX_W_K, /* 2345 */ + IC_EVEX_W_XS_K, /* 2346 */ + IC_EVEX_W_XS_K, /* 2347 */ + IC_EVEX_W_XD_K, /* 2348 */ + IC_EVEX_W_XD_K, /* 2349 */ + IC_EVEX_W_XD_K, /* 2350 */ + IC_EVEX_W_XD_K, /* 2351 */ + IC_EVEX_OPSIZE_K, /* 2352 */ + IC_EVEX_OPSIZE_K, /* 2353 */ + IC_EVEX_OPSIZE_K, /* 2354 */ + IC_EVEX_OPSIZE_K, /* 2355 */ + IC_EVEX_OPSIZE_K, /* 2356 */ + IC_EVEX_OPSIZE_K, /* 2357 */ + IC_EVEX_OPSIZE_K, /* 2358 */ + IC_EVEX_OPSIZE_K, /* 2359 */ + IC_EVEX_W_OPSIZE_K, /* 2360 */ + IC_EVEX_W_OPSIZE_K, /* 2361 */ + IC_EVEX_W_OPSIZE_K, /* 2362 */ + IC_EVEX_W_OPSIZE_K, /* 2363 */ + IC_EVEX_W_OPSIZE_K, /* 2364 */ + IC_EVEX_W_OPSIZE_K, /* 2365 */ + IC_EVEX_W_OPSIZE_K, /* 2366 */ + IC_EVEX_W_OPSIZE_K, /* 2367 */ + IC_EVEX_K, /* 2368 */ + IC_EVEX_K, /* 2369 */ + IC_EVEX_XS_K, /* 2370 */ + IC_EVEX_XS_K, /* 2371 */ + IC_EVEX_XD_K, /* 2372 */ + IC_EVEX_XD_K, /* 2373 */ + IC_EVEX_XD_K, /* 2374 */ + IC_EVEX_XD_K, /* 2375 */ + IC_EVEX_W_K, /* 2376 */ + IC_EVEX_W_K, /* 2377 */ + IC_EVEX_W_XS_K, /* 2378 */ + IC_EVEX_W_XS_K, /* 2379 */ + IC_EVEX_W_XD_K, /* 2380 */ + IC_EVEX_W_XD_K, /* 2381 */ + IC_EVEX_W_XD_K, /* 2382 */ + IC_EVEX_W_XD_K, /* 2383 */ + IC_EVEX_OPSIZE_K, /* 2384 */ + IC_EVEX_OPSIZE_K, /* 2385 */ + IC_EVEX_OPSIZE_K, /* 2386 */ + IC_EVEX_OPSIZE_K, /* 2387 */ + IC_EVEX_OPSIZE_K, /* 2388 */ + IC_EVEX_OPSIZE_K, /* 2389 */ + IC_EVEX_OPSIZE_K, /* 2390 */ + IC_EVEX_OPSIZE_K, /* 2391 */ + IC_EVEX_W_OPSIZE_K, /* 2392 */ + IC_EVEX_W_OPSIZE_K, /* 2393 */ + IC_EVEX_W_OPSIZE_K, /* 2394 */ + IC_EVEX_W_OPSIZE_K, /* 2395 */ + IC_EVEX_W_OPSIZE_K, /* 2396 */ + IC_EVEX_W_OPSIZE_K, /* 2397 */ + IC_EVEX_W_OPSIZE_K, /* 2398 */ + IC_EVEX_W_OPSIZE_K, /* 2399 */ + IC_EVEX_K, /* 2400 */ + IC_EVEX_K, /* 2401 */ + IC_EVEX_XS_K, /* 2402 */ + IC_EVEX_XS_K, /* 2403 */ + IC_EVEX_XD_K, /* 2404 */ + IC_EVEX_XD_K, /* 2405 */ + IC_EVEX_XD_K, /* 2406 */ + IC_EVEX_XD_K, /* 2407 */ + IC_EVEX_W_K, /* 2408 */ + IC_EVEX_W_K, /* 2409 */ + IC_EVEX_W_XS_K, /* 2410 */ + IC_EVEX_W_XS_K, /* 2411 */ + IC_EVEX_W_XD_K, /* 2412 */ + IC_EVEX_W_XD_K, /* 2413 */ + IC_EVEX_W_XD_K, /* 2414 */ + IC_EVEX_W_XD_K, /* 2415 */ + IC_EVEX_OPSIZE_K, /* 2416 */ + IC_EVEX_OPSIZE_K, /* 2417 */ + IC_EVEX_OPSIZE_K, /* 2418 */ + IC_EVEX_OPSIZE_K, /* 2419 */ + IC_EVEX_OPSIZE_K, /* 2420 */ + IC_EVEX_OPSIZE_K, /* 2421 */ + IC_EVEX_OPSIZE_K, /* 2422 */ + IC_EVEX_OPSIZE_K, /* 2423 */ + IC_EVEX_W_OPSIZE_K, /* 2424 */ + IC_EVEX_W_OPSIZE_K, /* 2425 */ + IC_EVEX_W_OPSIZE_K, /* 2426 */ + IC_EVEX_W_OPSIZE_K, /* 2427 */ + IC_EVEX_W_OPSIZE_K, /* 2428 */ + IC_EVEX_W_OPSIZE_K, /* 2429 */ + IC_EVEX_W_OPSIZE_K, /* 2430 */ + IC_EVEX_W_OPSIZE_K, /* 2431 */ + IC_EVEX_K, /* 2432 */ + IC_EVEX_K, /* 2433 */ + IC_EVEX_XS_K, /* 2434 */ + IC_EVEX_XS_K, /* 2435 */ + IC_EVEX_XD_K, /* 2436 */ + IC_EVEX_XD_K, /* 2437 */ + IC_EVEX_XD_K, /* 2438 */ + IC_EVEX_XD_K, /* 2439 */ + IC_EVEX_W_K, /* 2440 */ + IC_EVEX_W_K, /* 2441 */ + IC_EVEX_W_XS_K, /* 2442 */ + IC_EVEX_W_XS_K, /* 2443 */ + IC_EVEX_W_XD_K, /* 2444 */ + IC_EVEX_W_XD_K, /* 2445 */ + IC_EVEX_W_XD_K, /* 2446 */ + IC_EVEX_W_XD_K, /* 2447 */ + IC_EVEX_OPSIZE_K, /* 2448 */ + IC_EVEX_OPSIZE_K, /* 2449 */ + IC_EVEX_OPSIZE_K, /* 2450 */ + IC_EVEX_OPSIZE_K, /* 2451 */ + IC_EVEX_OPSIZE_K, /* 2452 */ + IC_EVEX_OPSIZE_K, /* 2453 */ + IC_EVEX_OPSIZE_K, /* 2454 */ + IC_EVEX_OPSIZE_K, /* 2455 */ + IC_EVEX_W_OPSIZE_K, /* 2456 */ + IC_EVEX_W_OPSIZE_K, /* 2457 */ + IC_EVEX_W_OPSIZE_K, /* 2458 */ + IC_EVEX_W_OPSIZE_K, /* 2459 */ + IC_EVEX_W_OPSIZE_K, /* 2460 */ + IC_EVEX_W_OPSIZE_K, /* 2461 */ + IC_EVEX_W_OPSIZE_K, /* 2462 */ + IC_EVEX_W_OPSIZE_K, /* 2463 */ + IC_EVEX_K, /* 2464 */ + IC_EVEX_K, /* 2465 */ + IC_EVEX_XS_K, /* 2466 */ + IC_EVEX_XS_K, /* 2467 */ + IC_EVEX_XD_K, /* 2468 */ + IC_EVEX_XD_K, /* 2469 */ + IC_EVEX_XD_K, /* 2470 */ + IC_EVEX_XD_K, /* 2471 */ + IC_EVEX_W_K, /* 2472 */ + IC_EVEX_W_K, /* 2473 */ + IC_EVEX_W_XS_K, /* 2474 */ + IC_EVEX_W_XS_K, /* 2475 */ + IC_EVEX_W_XD_K, /* 2476 */ + IC_EVEX_W_XD_K, /* 2477 */ + IC_EVEX_W_XD_K, /* 2478 */ + IC_EVEX_W_XD_K, /* 2479 */ + IC_EVEX_OPSIZE_K, /* 2480 */ + IC_EVEX_OPSIZE_K, /* 2481 */ + IC_EVEX_OPSIZE_K, /* 2482 */ + IC_EVEX_OPSIZE_K, /* 2483 */ + IC_EVEX_OPSIZE_K, /* 2484 */ + IC_EVEX_OPSIZE_K, /* 2485 */ + IC_EVEX_OPSIZE_K, /* 2486 */ + IC_EVEX_OPSIZE_K, /* 2487 */ + IC_EVEX_W_OPSIZE_K, /* 2488 */ + IC_EVEX_W_OPSIZE_K, /* 2489 */ + IC_EVEX_W_OPSIZE_K, /* 2490 */ + IC_EVEX_W_OPSIZE_K, /* 2491 */ + IC_EVEX_W_OPSIZE_K, /* 2492 */ + IC_EVEX_W_OPSIZE_K, /* 2493 */ + IC_EVEX_W_OPSIZE_K, /* 2494 */ + IC_EVEX_W_OPSIZE_K, /* 2495 */ + IC_EVEX_K, /* 2496 */ + IC_EVEX_K, /* 2497 */ + IC_EVEX_XS_K, /* 2498 */ + IC_EVEX_XS_K, /* 2499 */ + IC_EVEX_XD_K, /* 2500 */ + IC_EVEX_XD_K, /* 2501 */ + IC_EVEX_XD_K, /* 2502 */ + IC_EVEX_XD_K, /* 2503 */ + IC_EVEX_W_K, /* 2504 */ + IC_EVEX_W_K, /* 2505 */ + IC_EVEX_W_XS_K, /* 2506 */ + IC_EVEX_W_XS_K, /* 2507 */ + IC_EVEX_W_XD_K, /* 2508 */ + IC_EVEX_W_XD_K, /* 2509 */ + IC_EVEX_W_XD_K, /* 2510 */ + IC_EVEX_W_XD_K, /* 2511 */ + IC_EVEX_OPSIZE_K, /* 2512 */ + IC_EVEX_OPSIZE_K, /* 2513 */ + IC_EVEX_OPSIZE_K, /* 2514 */ + IC_EVEX_OPSIZE_K, /* 2515 */ + IC_EVEX_OPSIZE_K, /* 2516 */ + IC_EVEX_OPSIZE_K, /* 2517 */ + IC_EVEX_OPSIZE_K, /* 2518 */ + IC_EVEX_OPSIZE_K, /* 2519 */ + IC_EVEX_W_OPSIZE_K, /* 2520 */ + IC_EVEX_W_OPSIZE_K, /* 2521 */ + IC_EVEX_W_OPSIZE_K, /* 2522 */ + IC_EVEX_W_OPSIZE_K, /* 2523 */ + IC_EVEX_W_OPSIZE_K, /* 2524 */ + IC_EVEX_W_OPSIZE_K, /* 2525 */ + IC_EVEX_W_OPSIZE_K, /* 2526 */ + IC_EVEX_W_OPSIZE_K, /* 2527 */ + IC_EVEX_K, /* 2528 */ + IC_EVEX_K, /* 2529 */ + IC_EVEX_XS_K, /* 2530 */ + IC_EVEX_XS_K, /* 2531 */ + IC_EVEX_XD_K, /* 2532 */ + IC_EVEX_XD_K, /* 2533 */ + IC_EVEX_XD_K, /* 2534 */ + IC_EVEX_XD_K, /* 2535 */ + IC_EVEX_W_K, /* 2536 */ + IC_EVEX_W_K, /* 2537 */ + IC_EVEX_W_XS_K, /* 2538 */ + IC_EVEX_W_XS_K, /* 2539 */ + IC_EVEX_W_XD_K, /* 2540 */ + IC_EVEX_W_XD_K, /* 2541 */ + IC_EVEX_W_XD_K, /* 2542 */ + IC_EVEX_W_XD_K, /* 2543 */ + IC_EVEX_OPSIZE_K, /* 2544 */ + IC_EVEX_OPSIZE_K, /* 2545 */ + IC_EVEX_OPSIZE_K, /* 2546 */ + IC_EVEX_OPSIZE_K, /* 2547 */ + IC_EVEX_OPSIZE_K, /* 2548 */ + IC_EVEX_OPSIZE_K, /* 2549 */ + IC_EVEX_OPSIZE_K, /* 2550 */ + IC_EVEX_OPSIZE_K, /* 2551 */ + IC_EVEX_W_OPSIZE_K, /* 2552 */ + IC_EVEX_W_OPSIZE_K, /* 2553 */ + IC_EVEX_W_OPSIZE_K, /* 2554 */ + IC_EVEX_W_OPSIZE_K, /* 2555 */ + IC_EVEX_W_OPSIZE_K, /* 2556 */ + IC_EVEX_W_OPSIZE_K, /* 2557 */ + IC_EVEX_W_OPSIZE_K, /* 2558 */ + IC_EVEX_W_OPSIZE_K, /* 2559 */ + IC, /* 2560 */ + IC_64BIT, /* 2561 */ + IC_XS, /* 2562 */ + IC_64BIT_XS, /* 2563 */ + IC_XD, /* 2564 */ + IC_64BIT_XD, /* 2565 */ + IC_XS, /* 2566 */ + IC_64BIT_XS, /* 2567 */ + IC, /* 2568 */ + IC_64BIT_REXW, /* 2569 */ + IC_XS, /* 2570 */ + IC_64BIT_REXW_XS, /* 2571 */ + IC_XD, /* 2572 */ + IC_64BIT_REXW_XD, /* 2573 */ + IC_XS, /* 2574 */ + IC_64BIT_REXW_XS, /* 2575 */ + IC_OPSIZE, /* 2576 */ + IC_64BIT_OPSIZE, /* 2577 */ + IC_XS_OPSIZE, /* 2578 */ + IC_64BIT_XS_OPSIZE, /* 2579 */ + IC_XD_OPSIZE, /* 2580 */ + IC_64BIT_XD_OPSIZE, /* 2581 */ + IC_XS_OPSIZE, /* 2582 */ + IC_64BIT_XD_OPSIZE, /* 2583 */ + IC_OPSIZE, /* 2584 */ + IC_64BIT_REXW_OPSIZE, /* 2585 */ + IC_XS_OPSIZE, /* 2586 */ + IC_64BIT_REXW_XS, /* 2587 */ + IC_XD_OPSIZE, /* 2588 */ + IC_64BIT_REXW_XD, /* 2589 */ + IC_XS_OPSIZE, /* 2590 */ + IC_64BIT_REXW_XS, /* 2591 */ + IC_ADSIZE, /* 2592 */ + IC_64BIT_ADSIZE, /* 2593 */ + IC_XS_ADSIZE, /* 2594 */ + IC_64BIT_XS_ADSIZE, /* 2595 */ + IC_XD_ADSIZE, /* 2596 */ + IC_64BIT_XD_ADSIZE, /* 2597 */ + IC_XS_ADSIZE, /* 2598 */ + IC_64BIT_XD_ADSIZE, /* 2599 */ + IC_ADSIZE, /* 2600 */ + IC_64BIT_REXW_ADSIZE, /* 2601 */ + IC_XS_ADSIZE, /* 2602 */ + IC_64BIT_REXW_XS, /* 2603 */ + IC_XD_ADSIZE, /* 2604 */ + IC_64BIT_REXW_XD, /* 2605 */ + IC_XS_ADSIZE, /* 2606 */ + IC_64BIT_REXW_XS, /* 2607 */ + IC_OPSIZE_ADSIZE, /* 2608 */ + IC_64BIT_OPSIZE_ADSIZE, /* 2609 */ + IC_XS_OPSIZE, /* 2610 */ + IC_64BIT_XS_OPSIZE, /* 2611 */ + IC_XD_OPSIZE, /* 2612 */ + IC_64BIT_XD_OPSIZE, /* 2613 */ + IC_XS_OPSIZE, /* 2614 */ + IC_64BIT_XD_OPSIZE, /* 2615 */ + IC_OPSIZE_ADSIZE, /* 2616 */ + IC_64BIT_REXW_OPSIZE, /* 2617 */ + IC_XS_OPSIZE, /* 2618 */ + IC_64BIT_REXW_XS, /* 2619 */ + IC_XD_OPSIZE, /* 2620 */ + IC_64BIT_REXW_XD, /* 2621 */ + IC_XS_OPSIZE, /* 2622 */ + IC_64BIT_REXW_XS, /* 2623 */ + IC_VEX, /* 2624 */ + IC_VEX, /* 2625 */ + IC_VEX_XS, /* 2626 */ + IC_VEX_XS, /* 2627 */ + IC_VEX_XD, /* 2628 */ + IC_VEX_XD, /* 2629 */ + IC_VEX_XD, /* 2630 */ + IC_VEX_XD, /* 2631 */ + IC_VEX_W, /* 2632 */ + IC_VEX_W, /* 2633 */ + IC_VEX_W_XS, /* 2634 */ + IC_VEX_W_XS, /* 2635 */ + IC_VEX_W_XD, /* 2636 */ + IC_VEX_W_XD, /* 2637 */ + IC_VEX_W_XD, /* 2638 */ + IC_VEX_W_XD, /* 2639 */ + IC_VEX_OPSIZE, /* 2640 */ + IC_VEX_OPSIZE, /* 2641 */ + IC_VEX_OPSIZE, /* 2642 */ + IC_VEX_OPSIZE, /* 2643 */ + IC_VEX_OPSIZE, /* 2644 */ + IC_VEX_OPSIZE, /* 2645 */ + IC_VEX_OPSIZE, /* 2646 */ + IC_VEX_OPSIZE, /* 2647 */ + IC_VEX_W_OPSIZE, /* 2648 */ + IC_VEX_W_OPSIZE, /* 2649 */ + IC_VEX_W_OPSIZE, /* 2650 */ + IC_VEX_W_OPSIZE, /* 2651 */ + IC_VEX_W_OPSIZE, /* 2652 */ + IC_VEX_W_OPSIZE, /* 2653 */ + IC_VEX_W_OPSIZE, /* 2654 */ + IC_VEX_W_OPSIZE, /* 2655 */ + IC_VEX, /* 2656 */ + IC_VEX, /* 2657 */ + IC_VEX_XS, /* 2658 */ + IC_VEX_XS, /* 2659 */ + IC_VEX_XD, /* 2660 */ + IC_VEX_XD, /* 2661 */ + IC_VEX_XD, /* 2662 */ + IC_VEX_XD, /* 2663 */ + IC_VEX_W, /* 2664 */ + IC_VEX_W, /* 2665 */ + IC_VEX_W_XS, /* 2666 */ + IC_VEX_W_XS, /* 2667 */ + IC_VEX_W_XD, /* 2668 */ + IC_VEX_W_XD, /* 2669 */ + IC_VEX_W_XD, /* 2670 */ + IC_VEX_W_XD, /* 2671 */ + IC_VEX_OPSIZE, /* 2672 */ + IC_VEX_OPSIZE, /* 2673 */ + IC_VEX_OPSIZE, /* 2674 */ + IC_VEX_OPSIZE, /* 2675 */ + IC_VEX_OPSIZE, /* 2676 */ + IC_VEX_OPSIZE, /* 2677 */ + IC_VEX_OPSIZE, /* 2678 */ + IC_VEX_OPSIZE, /* 2679 */ + IC_VEX_W_OPSIZE, /* 2680 */ + IC_VEX_W_OPSIZE, /* 2681 */ + IC_VEX_W_OPSIZE, /* 2682 */ + IC_VEX_W_OPSIZE, /* 2683 */ + IC_VEX_W_OPSIZE, /* 2684 */ + IC_VEX_W_OPSIZE, /* 2685 */ + IC_VEX_W_OPSIZE, /* 2686 */ + IC_VEX_W_OPSIZE, /* 2687 */ + IC_VEX_L, /* 2688 */ + IC_VEX_L, /* 2689 */ + IC_VEX_L_XS, /* 2690 */ + IC_VEX_L_XS, /* 2691 */ + IC_VEX_L_XD, /* 2692 */ + IC_VEX_L_XD, /* 2693 */ + IC_VEX_L_XD, /* 2694 */ + IC_VEX_L_XD, /* 2695 */ + IC_VEX_L_W, /* 2696 */ + IC_VEX_L_W, /* 2697 */ + IC_VEX_L_W_XS, /* 2698 */ + IC_VEX_L_W_XS, /* 2699 */ + IC_VEX_L_W_XD, /* 2700 */ + IC_VEX_L_W_XD, /* 2701 */ + IC_VEX_L_W_XD, /* 2702 */ + IC_VEX_L_W_XD, /* 2703 */ + IC_VEX_L_OPSIZE, /* 2704 */ + IC_VEX_L_OPSIZE, /* 2705 */ + IC_VEX_L_OPSIZE, /* 2706 */ + IC_VEX_L_OPSIZE, /* 2707 */ + IC_VEX_L_OPSIZE, /* 2708 */ + IC_VEX_L_OPSIZE, /* 2709 */ + IC_VEX_L_OPSIZE, /* 2710 */ + IC_VEX_L_OPSIZE, /* 2711 */ + IC_VEX_L_W_OPSIZE, /* 2712 */ + IC_VEX_L_W_OPSIZE, /* 2713 */ + IC_VEX_L_W_OPSIZE, /* 2714 */ + IC_VEX_L_W_OPSIZE, /* 2715 */ + IC_VEX_L_W_OPSIZE, /* 2716 */ + IC_VEX_L_W_OPSIZE, /* 2717 */ + IC_VEX_L_W_OPSIZE, /* 2718 */ + IC_VEX_L_W_OPSIZE, /* 2719 */ + IC_VEX_L, /* 2720 */ + IC_VEX_L, /* 2721 */ + IC_VEX_L_XS, /* 2722 */ + IC_VEX_L_XS, /* 2723 */ + IC_VEX_L_XD, /* 2724 */ + IC_VEX_L_XD, /* 2725 */ + IC_VEX_L_XD, /* 2726 */ + IC_VEX_L_XD, /* 2727 */ + IC_VEX_L_W, /* 2728 */ + IC_VEX_L_W, /* 2729 */ + IC_VEX_L_W_XS, /* 2730 */ + IC_VEX_L_W_XS, /* 2731 */ + IC_VEX_L_W_XD, /* 2732 */ + IC_VEX_L_W_XD, /* 2733 */ + IC_VEX_L_W_XD, /* 2734 */ + IC_VEX_L_W_XD, /* 2735 */ + IC_VEX_L_OPSIZE, /* 2736 */ + IC_VEX_L_OPSIZE, /* 2737 */ + IC_VEX_L_OPSIZE, /* 2738 */ + IC_VEX_L_OPSIZE, /* 2739 */ + IC_VEX_L_OPSIZE, /* 2740 */ + IC_VEX_L_OPSIZE, /* 2741 */ + IC_VEX_L_OPSIZE, /* 2742 */ + IC_VEX_L_OPSIZE, /* 2743 */ + IC_VEX_L_W_OPSIZE, /* 2744 */ + IC_VEX_L_W_OPSIZE, /* 2745 */ + IC_VEX_L_W_OPSIZE, /* 2746 */ + IC_VEX_L_W_OPSIZE, /* 2747 */ + IC_VEX_L_W_OPSIZE, /* 2748 */ + IC_VEX_L_W_OPSIZE, /* 2749 */ + IC_VEX_L_W_OPSIZE, /* 2750 */ + IC_VEX_L_W_OPSIZE, /* 2751 */ + IC_VEX_L, /* 2752 */ + IC_VEX_L, /* 2753 */ + IC_VEX_L_XS, /* 2754 */ + IC_VEX_L_XS, /* 2755 */ + IC_VEX_L_XD, /* 2756 */ + IC_VEX_L_XD, /* 2757 */ + IC_VEX_L_XD, /* 2758 */ + IC_VEX_L_XD, /* 2759 */ + IC_VEX_L_W, /* 2760 */ + IC_VEX_L_W, /* 2761 */ + IC_VEX_L_W_XS, /* 2762 */ + IC_VEX_L_W_XS, /* 2763 */ + IC_VEX_L_W_XD, /* 2764 */ + IC_VEX_L_W_XD, /* 2765 */ + IC_VEX_L_W_XD, /* 2766 */ + IC_VEX_L_W_XD, /* 2767 */ + IC_VEX_L_OPSIZE, /* 2768 */ + IC_VEX_L_OPSIZE, /* 2769 */ + IC_VEX_L_OPSIZE, /* 2770 */ + IC_VEX_L_OPSIZE, /* 2771 */ + IC_VEX_L_OPSIZE, /* 2772 */ + IC_VEX_L_OPSIZE, /* 2773 */ + IC_VEX_L_OPSIZE, /* 2774 */ + IC_VEX_L_OPSIZE, /* 2775 */ + IC_VEX_L_W_OPSIZE, /* 2776 */ + IC_VEX_L_W_OPSIZE, /* 2777 */ + IC_VEX_L_W_OPSIZE, /* 2778 */ + IC_VEX_L_W_OPSIZE, /* 2779 */ + IC_VEX_L_W_OPSIZE, /* 2780 */ + IC_VEX_L_W_OPSIZE, /* 2781 */ + IC_VEX_L_W_OPSIZE, /* 2782 */ + IC_VEX_L_W_OPSIZE, /* 2783 */ + IC_VEX_L, /* 2784 */ + IC_VEX_L, /* 2785 */ + IC_VEX_L_XS, /* 2786 */ + IC_VEX_L_XS, /* 2787 */ + IC_VEX_L_XD, /* 2788 */ + IC_VEX_L_XD, /* 2789 */ + IC_VEX_L_XD, /* 2790 */ + IC_VEX_L_XD, /* 2791 */ + IC_VEX_L_W, /* 2792 */ + IC_VEX_L_W, /* 2793 */ + IC_VEX_L_W_XS, /* 2794 */ + IC_VEX_L_W_XS, /* 2795 */ + IC_VEX_L_W_XD, /* 2796 */ + IC_VEX_L_W_XD, /* 2797 */ + IC_VEX_L_W_XD, /* 2798 */ + IC_VEX_L_W_XD, /* 2799 */ + IC_VEX_L_OPSIZE, /* 2800 */ + IC_VEX_L_OPSIZE, /* 2801 */ + IC_VEX_L_OPSIZE, /* 2802 */ + IC_VEX_L_OPSIZE, /* 2803 */ + IC_VEX_L_OPSIZE, /* 2804 */ + IC_VEX_L_OPSIZE, /* 2805 */ + IC_VEX_L_OPSIZE, /* 2806 */ + IC_VEX_L_OPSIZE, /* 2807 */ + IC_VEX_L_W_OPSIZE, /* 2808 */ + IC_VEX_L_W_OPSIZE, /* 2809 */ + IC_VEX_L_W_OPSIZE, /* 2810 */ + IC_VEX_L_W_OPSIZE, /* 2811 */ + IC_VEX_L_W_OPSIZE, /* 2812 */ + IC_VEX_L_W_OPSIZE, /* 2813 */ + IC_VEX_L_W_OPSIZE, /* 2814 */ + IC_VEX_L_W_OPSIZE, /* 2815 */ + IC_EVEX_L_K, /* 2816 */ + IC_EVEX_L_K, /* 2817 */ + IC_EVEX_L_XS_K, /* 2818 */ + IC_EVEX_L_XS_K, /* 2819 */ + IC_EVEX_L_XD_K, /* 2820 */ + IC_EVEX_L_XD_K, /* 2821 */ + IC_EVEX_L_XD_K, /* 2822 */ + IC_EVEX_L_XD_K, /* 2823 */ + IC_EVEX_L_W_K, /* 2824 */ + IC_EVEX_L_W_K, /* 2825 */ + IC_EVEX_L_W_XS_K, /* 2826 */ + IC_EVEX_L_W_XS_K, /* 2827 */ + IC_EVEX_L_W_XD_K, /* 2828 */ + IC_EVEX_L_W_XD_K, /* 2829 */ + IC_EVEX_L_W_XD_K, /* 2830 */ + IC_EVEX_L_W_XD_K, /* 2831 */ + IC_EVEX_L_OPSIZE_K, /* 2832 */ + IC_EVEX_L_OPSIZE_K, /* 2833 */ + IC_EVEX_L_OPSIZE_K, /* 2834 */ + IC_EVEX_L_OPSIZE_K, /* 2835 */ + IC_EVEX_L_OPSIZE_K, /* 2836 */ + IC_EVEX_L_OPSIZE_K, /* 2837 */ + IC_EVEX_L_OPSIZE_K, /* 2838 */ + IC_EVEX_L_OPSIZE_K, /* 2839 */ + IC_EVEX_L_W_OPSIZE_K, /* 2840 */ + IC_EVEX_L_W_OPSIZE_K, /* 2841 */ + IC_EVEX_L_W_OPSIZE_K, /* 2842 */ + IC_EVEX_L_W_OPSIZE_K, /* 2843 */ + IC_EVEX_L_W_OPSIZE_K, /* 2844 */ + IC_EVEX_L_W_OPSIZE_K, /* 2845 */ + IC_EVEX_L_W_OPSIZE_K, /* 2846 */ + IC_EVEX_L_W_OPSIZE_K, /* 2847 */ + IC_EVEX_L_K, /* 2848 */ + IC_EVEX_L_K, /* 2849 */ + IC_EVEX_L_XS_K, /* 2850 */ + IC_EVEX_L_XS_K, /* 2851 */ + IC_EVEX_L_XD_K, /* 2852 */ + IC_EVEX_L_XD_K, /* 2853 */ + IC_EVEX_L_XD_K, /* 2854 */ + IC_EVEX_L_XD_K, /* 2855 */ + IC_EVEX_L_W_K, /* 2856 */ + IC_EVEX_L_W_K, /* 2857 */ + IC_EVEX_L_W_XS_K, /* 2858 */ + IC_EVEX_L_W_XS_K, /* 2859 */ + IC_EVEX_L_W_XD_K, /* 2860 */ + IC_EVEX_L_W_XD_K, /* 2861 */ + IC_EVEX_L_W_XD_K, /* 2862 */ + IC_EVEX_L_W_XD_K, /* 2863 */ + IC_EVEX_L_OPSIZE_K, /* 2864 */ + IC_EVEX_L_OPSIZE_K, /* 2865 */ + IC_EVEX_L_OPSIZE_K, /* 2866 */ + IC_EVEX_L_OPSIZE_K, /* 2867 */ + IC_EVEX_L_OPSIZE_K, /* 2868 */ + IC_EVEX_L_OPSIZE_K, /* 2869 */ + IC_EVEX_L_OPSIZE_K, /* 2870 */ + IC_EVEX_L_OPSIZE_K, /* 2871 */ + IC_EVEX_L_W_OPSIZE_K, /* 2872 */ + IC_EVEX_L_W_OPSIZE_K, /* 2873 */ + IC_EVEX_L_W_OPSIZE_K, /* 2874 */ + IC_EVEX_L_W_OPSIZE_K, /* 2875 */ + IC_EVEX_L_W_OPSIZE_K, /* 2876 */ + IC_EVEX_L_W_OPSIZE_K, /* 2877 */ + IC_EVEX_L_W_OPSIZE_K, /* 2878 */ + IC_EVEX_L_W_OPSIZE_K, /* 2879 */ + IC_EVEX_L_K, /* 2880 */ + IC_EVEX_L_K, /* 2881 */ + IC_EVEX_L_XS_K, /* 2882 */ + IC_EVEX_L_XS_K, /* 2883 */ + IC_EVEX_L_XD_K, /* 2884 */ + IC_EVEX_L_XD_K, /* 2885 */ + IC_EVEX_L_XD_K, /* 2886 */ + IC_EVEX_L_XD_K, /* 2887 */ + IC_EVEX_L_W_K, /* 2888 */ + IC_EVEX_L_W_K, /* 2889 */ + IC_EVEX_L_W_XS_K, /* 2890 */ + IC_EVEX_L_W_XS_K, /* 2891 */ + IC_EVEX_L_W_XD_K, /* 2892 */ + IC_EVEX_L_W_XD_K, /* 2893 */ + IC_EVEX_L_W_XD_K, /* 2894 */ + IC_EVEX_L_W_XD_K, /* 2895 */ + IC_EVEX_L_OPSIZE_K, /* 2896 */ + IC_EVEX_L_OPSIZE_K, /* 2897 */ + IC_EVEX_L_OPSIZE_K, /* 2898 */ + IC_EVEX_L_OPSIZE_K, /* 2899 */ + IC_EVEX_L_OPSIZE_K, /* 2900 */ + IC_EVEX_L_OPSIZE_K, /* 2901 */ + IC_EVEX_L_OPSIZE_K, /* 2902 */ + IC_EVEX_L_OPSIZE_K, /* 2903 */ + IC_EVEX_L_W_OPSIZE_K, /* 2904 */ + IC_EVEX_L_W_OPSIZE_K, /* 2905 */ + IC_EVEX_L_W_OPSIZE_K, /* 2906 */ + IC_EVEX_L_W_OPSIZE_K, /* 2907 */ + IC_EVEX_L_W_OPSIZE_K, /* 2908 */ + IC_EVEX_L_W_OPSIZE_K, /* 2909 */ + IC_EVEX_L_W_OPSIZE_K, /* 2910 */ + IC_EVEX_L_W_OPSIZE_K, /* 2911 */ + IC_EVEX_L_K, /* 2912 */ + IC_EVEX_L_K, /* 2913 */ + IC_EVEX_L_XS_K, /* 2914 */ + IC_EVEX_L_XS_K, /* 2915 */ + IC_EVEX_L_XD_K, /* 2916 */ + IC_EVEX_L_XD_K, /* 2917 */ + IC_EVEX_L_XD_K, /* 2918 */ + IC_EVEX_L_XD_K, /* 2919 */ + IC_EVEX_L_W_K, /* 2920 */ + IC_EVEX_L_W_K, /* 2921 */ + IC_EVEX_L_W_XS_K, /* 2922 */ + IC_EVEX_L_W_XS_K, /* 2923 */ + IC_EVEX_L_W_XD_K, /* 2924 */ + IC_EVEX_L_W_XD_K, /* 2925 */ + IC_EVEX_L_W_XD_K, /* 2926 */ + IC_EVEX_L_W_XD_K, /* 2927 */ + IC_EVEX_L_OPSIZE_K, /* 2928 */ + IC_EVEX_L_OPSIZE_K, /* 2929 */ + IC_EVEX_L_OPSIZE_K, /* 2930 */ + IC_EVEX_L_OPSIZE_K, /* 2931 */ + IC_EVEX_L_OPSIZE_K, /* 2932 */ + IC_EVEX_L_OPSIZE_K, /* 2933 */ + IC_EVEX_L_OPSIZE_K, /* 2934 */ + IC_EVEX_L_OPSIZE_K, /* 2935 */ + IC_EVEX_L_W_OPSIZE_K, /* 2936 */ + IC_EVEX_L_W_OPSIZE_K, /* 2937 */ + IC_EVEX_L_W_OPSIZE_K, /* 2938 */ + IC_EVEX_L_W_OPSIZE_K, /* 2939 */ + IC_EVEX_L_W_OPSIZE_K, /* 2940 */ + IC_EVEX_L_W_OPSIZE_K, /* 2941 */ + IC_EVEX_L_W_OPSIZE_K, /* 2942 */ + IC_EVEX_L_W_OPSIZE_K, /* 2943 */ + IC_EVEX_L_K, /* 2944 */ + IC_EVEX_L_K, /* 2945 */ + IC_EVEX_L_XS_K, /* 2946 */ + IC_EVEX_L_XS_K, /* 2947 */ + IC_EVEX_L_XD_K, /* 2948 */ + IC_EVEX_L_XD_K, /* 2949 */ + IC_EVEX_L_XD_K, /* 2950 */ + IC_EVEX_L_XD_K, /* 2951 */ + IC_EVEX_L_W_K, /* 2952 */ + IC_EVEX_L_W_K, /* 2953 */ + IC_EVEX_L_W_XS_K, /* 2954 */ + IC_EVEX_L_W_XS_K, /* 2955 */ + IC_EVEX_L_W_XD_K, /* 2956 */ + IC_EVEX_L_W_XD_K, /* 2957 */ + IC_EVEX_L_W_XD_K, /* 2958 */ + IC_EVEX_L_W_XD_K, /* 2959 */ + IC_EVEX_L_OPSIZE_K, /* 2960 */ + IC_EVEX_L_OPSIZE_K, /* 2961 */ + IC_EVEX_L_OPSIZE_K, /* 2962 */ + IC_EVEX_L_OPSIZE_K, /* 2963 */ + IC_EVEX_L_OPSIZE_K, /* 2964 */ + IC_EVEX_L_OPSIZE_K, /* 2965 */ + IC_EVEX_L_OPSIZE_K, /* 2966 */ + IC_EVEX_L_OPSIZE_K, /* 2967 */ + IC_EVEX_L_W_OPSIZE_K, /* 2968 */ + IC_EVEX_L_W_OPSIZE_K, /* 2969 */ + IC_EVEX_L_W_OPSIZE_K, /* 2970 */ + IC_EVEX_L_W_OPSIZE_K, /* 2971 */ + IC_EVEX_L_W_OPSIZE_K, /* 2972 */ + IC_EVEX_L_W_OPSIZE_K, /* 2973 */ + IC_EVEX_L_W_OPSIZE_K, /* 2974 */ + IC_EVEX_L_W_OPSIZE_K, /* 2975 */ + IC_EVEX_L_K, /* 2976 */ + IC_EVEX_L_K, /* 2977 */ + IC_EVEX_L_XS_K, /* 2978 */ + IC_EVEX_L_XS_K, /* 2979 */ + IC_EVEX_L_XD_K, /* 2980 */ + IC_EVEX_L_XD_K, /* 2981 */ + IC_EVEX_L_XD_K, /* 2982 */ + IC_EVEX_L_XD_K, /* 2983 */ + IC_EVEX_L_W_K, /* 2984 */ + IC_EVEX_L_W_K, /* 2985 */ + IC_EVEX_L_W_XS_K, /* 2986 */ + IC_EVEX_L_W_XS_K, /* 2987 */ + IC_EVEX_L_W_XD_K, /* 2988 */ + IC_EVEX_L_W_XD_K, /* 2989 */ + IC_EVEX_L_W_XD_K, /* 2990 */ + IC_EVEX_L_W_XD_K, /* 2991 */ + IC_EVEX_L_OPSIZE_K, /* 2992 */ + IC_EVEX_L_OPSIZE_K, /* 2993 */ + IC_EVEX_L_OPSIZE_K, /* 2994 */ + IC_EVEX_L_OPSIZE_K, /* 2995 */ + IC_EVEX_L_OPSIZE_K, /* 2996 */ + IC_EVEX_L_OPSIZE_K, /* 2997 */ + IC_EVEX_L_OPSIZE_K, /* 2998 */ + IC_EVEX_L_OPSIZE_K, /* 2999 */ + IC_EVEX_L_W_OPSIZE_K, /* 3000 */ + IC_EVEX_L_W_OPSIZE_K, /* 3001 */ + IC_EVEX_L_W_OPSIZE_K, /* 3002 */ + IC_EVEX_L_W_OPSIZE_K, /* 3003 */ + IC_EVEX_L_W_OPSIZE_K, /* 3004 */ + IC_EVEX_L_W_OPSIZE_K, /* 3005 */ + IC_EVEX_L_W_OPSIZE_K, /* 3006 */ + IC_EVEX_L_W_OPSIZE_K, /* 3007 */ + IC_EVEX_L_K, /* 3008 */ + IC_EVEX_L_K, /* 3009 */ + IC_EVEX_L_XS_K, /* 3010 */ + IC_EVEX_L_XS_K, /* 3011 */ + IC_EVEX_L_XD_K, /* 3012 */ + IC_EVEX_L_XD_K, /* 3013 */ + IC_EVEX_L_XD_K, /* 3014 */ + IC_EVEX_L_XD_K, /* 3015 */ + IC_EVEX_L_W_K, /* 3016 */ + IC_EVEX_L_W_K, /* 3017 */ + IC_EVEX_L_W_XS_K, /* 3018 */ + IC_EVEX_L_W_XS_K, /* 3019 */ + IC_EVEX_L_W_XD_K, /* 3020 */ + IC_EVEX_L_W_XD_K, /* 3021 */ + IC_EVEX_L_W_XD_K, /* 3022 */ + IC_EVEX_L_W_XD_K, /* 3023 */ + IC_EVEX_L_OPSIZE_K, /* 3024 */ + IC_EVEX_L_OPSIZE_K, /* 3025 */ + IC_EVEX_L_OPSIZE_K, /* 3026 */ + IC_EVEX_L_OPSIZE_K, /* 3027 */ + IC_EVEX_L_OPSIZE_K, /* 3028 */ + IC_EVEX_L_OPSIZE_K, /* 3029 */ + IC_EVEX_L_OPSIZE_K, /* 3030 */ + IC_EVEX_L_OPSIZE_K, /* 3031 */ + IC_EVEX_L_W_OPSIZE_K, /* 3032 */ + IC_EVEX_L_W_OPSIZE_K, /* 3033 */ + IC_EVEX_L_W_OPSIZE_K, /* 3034 */ + IC_EVEX_L_W_OPSIZE_K, /* 3035 */ + IC_EVEX_L_W_OPSIZE_K, /* 3036 */ + IC_EVEX_L_W_OPSIZE_K, /* 3037 */ + IC_EVEX_L_W_OPSIZE_K, /* 3038 */ + IC_EVEX_L_W_OPSIZE_K, /* 3039 */ + IC_EVEX_L_K, /* 3040 */ + IC_EVEX_L_K, /* 3041 */ + IC_EVEX_L_XS_K, /* 3042 */ + IC_EVEX_L_XS_K, /* 3043 */ + IC_EVEX_L_XD_K, /* 3044 */ + IC_EVEX_L_XD_K, /* 3045 */ + IC_EVEX_L_XD_K, /* 3046 */ + IC_EVEX_L_XD_K, /* 3047 */ + IC_EVEX_L_W_K, /* 3048 */ + IC_EVEX_L_W_K, /* 3049 */ + IC_EVEX_L_W_XS_K, /* 3050 */ + IC_EVEX_L_W_XS_K, /* 3051 */ + IC_EVEX_L_W_XD_K, /* 3052 */ + IC_EVEX_L_W_XD_K, /* 3053 */ + IC_EVEX_L_W_XD_K, /* 3054 */ + IC_EVEX_L_W_XD_K, /* 3055 */ + IC_EVEX_L_OPSIZE_K, /* 3056 */ + IC_EVEX_L_OPSIZE_K, /* 3057 */ + IC_EVEX_L_OPSIZE_K, /* 3058 */ + IC_EVEX_L_OPSIZE_K, /* 3059 */ + IC_EVEX_L_OPSIZE_K, /* 3060 */ + IC_EVEX_L_OPSIZE_K, /* 3061 */ + IC_EVEX_L_OPSIZE_K, /* 3062 */ + IC_EVEX_L_OPSIZE_K, /* 3063 */ + IC_EVEX_L_W_OPSIZE_K, /* 3064 */ + IC_EVEX_L_W_OPSIZE_K, /* 3065 */ + IC_EVEX_L_W_OPSIZE_K, /* 3066 */ + IC_EVEX_L_W_OPSIZE_K, /* 3067 */ + IC_EVEX_L_W_OPSIZE_K, /* 3068 */ + IC_EVEX_L_W_OPSIZE_K, /* 3069 */ + IC_EVEX_L_W_OPSIZE_K, /* 3070 */ + IC_EVEX_L_W_OPSIZE_K, /* 3071 */ + IC, /* 3072 */ + IC_64BIT, /* 3073 */ + IC_XS, /* 3074 */ + IC_64BIT_XS, /* 3075 */ + IC_XD, /* 3076 */ + IC_64BIT_XD, /* 3077 */ + IC_XS, /* 3078 */ + IC_64BIT_XS, /* 3079 */ + IC, /* 3080 */ + IC_64BIT_REXW, /* 3081 */ + IC_XS, /* 3082 */ + IC_64BIT_REXW_XS, /* 3083 */ + IC_XD, /* 3084 */ + IC_64BIT_REXW_XD, /* 3085 */ + IC_XS, /* 3086 */ + IC_64BIT_REXW_XS, /* 3087 */ + IC_OPSIZE, /* 3088 */ + IC_64BIT_OPSIZE, /* 3089 */ + IC_XS_OPSIZE, /* 3090 */ + IC_64BIT_XS_OPSIZE, /* 3091 */ + IC_XD_OPSIZE, /* 3092 */ + IC_64BIT_XD_OPSIZE, /* 3093 */ + IC_XS_OPSIZE, /* 3094 */ + IC_64BIT_XD_OPSIZE, /* 3095 */ + IC_OPSIZE, /* 3096 */ + IC_64BIT_REXW_OPSIZE, /* 3097 */ + IC_XS_OPSIZE, /* 3098 */ + IC_64BIT_REXW_XS, /* 3099 */ + IC_XD_OPSIZE, /* 3100 */ + IC_64BIT_REXW_XD, /* 3101 */ + IC_XS_OPSIZE, /* 3102 */ + IC_64BIT_REXW_XS, /* 3103 */ + IC_ADSIZE, /* 3104 */ + IC_64BIT_ADSIZE, /* 3105 */ + IC_XS_ADSIZE, /* 3106 */ + IC_64BIT_XS_ADSIZE, /* 3107 */ + IC_XD_ADSIZE, /* 3108 */ + IC_64BIT_XD_ADSIZE, /* 3109 */ + IC_XS_ADSIZE, /* 3110 */ + IC_64BIT_XD_ADSIZE, /* 3111 */ + IC_ADSIZE, /* 3112 */ + IC_64BIT_REXW_ADSIZE, /* 3113 */ + IC_XS_ADSIZE, /* 3114 */ + IC_64BIT_REXW_XS, /* 3115 */ + IC_XD_ADSIZE, /* 3116 */ + IC_64BIT_REXW_XD, /* 3117 */ + IC_XS_ADSIZE, /* 3118 */ + IC_64BIT_REXW_XS, /* 3119 */ + IC_OPSIZE_ADSIZE, /* 3120 */ + IC_64BIT_OPSIZE_ADSIZE, /* 3121 */ + IC_XS_OPSIZE, /* 3122 */ + IC_64BIT_XS_OPSIZE, /* 3123 */ + IC_XD_OPSIZE, /* 3124 */ + IC_64BIT_XD_OPSIZE, /* 3125 */ + IC_XS_OPSIZE, /* 3126 */ + IC_64BIT_XD_OPSIZE, /* 3127 */ + IC_OPSIZE_ADSIZE, /* 3128 */ + IC_64BIT_REXW_OPSIZE, /* 3129 */ + IC_XS_OPSIZE, /* 3130 */ + IC_64BIT_REXW_XS, /* 3131 */ + IC_XD_OPSIZE, /* 3132 */ + IC_64BIT_REXW_XD, /* 3133 */ + IC_XS_OPSIZE, /* 3134 */ + IC_64BIT_REXW_XS, /* 3135 */ + IC_VEX, /* 3136 */ + IC_VEX, /* 3137 */ + IC_VEX_XS, /* 3138 */ + IC_VEX_XS, /* 3139 */ + IC_VEX_XD, /* 3140 */ + IC_VEX_XD, /* 3141 */ + IC_VEX_XD, /* 3142 */ + IC_VEX_XD, /* 3143 */ + IC_VEX_W, /* 3144 */ + IC_VEX_W, /* 3145 */ + IC_VEX_W_XS, /* 3146 */ + IC_VEX_W_XS, /* 3147 */ + IC_VEX_W_XD, /* 3148 */ + IC_VEX_W_XD, /* 3149 */ + IC_VEX_W_XD, /* 3150 */ + IC_VEX_W_XD, /* 3151 */ + IC_VEX_OPSIZE, /* 3152 */ + IC_VEX_OPSIZE, /* 3153 */ + IC_VEX_OPSIZE, /* 3154 */ + IC_VEX_OPSIZE, /* 3155 */ + IC_VEX_OPSIZE, /* 3156 */ + IC_VEX_OPSIZE, /* 3157 */ + IC_VEX_OPSIZE, /* 3158 */ + IC_VEX_OPSIZE, /* 3159 */ + IC_VEX_W_OPSIZE, /* 3160 */ + IC_VEX_W_OPSIZE, /* 3161 */ + IC_VEX_W_OPSIZE, /* 3162 */ + IC_VEX_W_OPSIZE, /* 3163 */ + IC_VEX_W_OPSIZE, /* 3164 */ + IC_VEX_W_OPSIZE, /* 3165 */ + IC_VEX_W_OPSIZE, /* 3166 */ + IC_VEX_W_OPSIZE, /* 3167 */ + IC_VEX, /* 3168 */ + IC_VEX, /* 3169 */ + IC_VEX_XS, /* 3170 */ + IC_VEX_XS, /* 3171 */ + IC_VEX_XD, /* 3172 */ + IC_VEX_XD, /* 3173 */ + IC_VEX_XD, /* 3174 */ + IC_VEX_XD, /* 3175 */ + IC_VEX_W, /* 3176 */ + IC_VEX_W, /* 3177 */ + IC_VEX_W_XS, /* 3178 */ + IC_VEX_W_XS, /* 3179 */ + IC_VEX_W_XD, /* 3180 */ + IC_VEX_W_XD, /* 3181 */ + IC_VEX_W_XD, /* 3182 */ + IC_VEX_W_XD, /* 3183 */ + IC_VEX_OPSIZE, /* 3184 */ + IC_VEX_OPSIZE, /* 3185 */ + IC_VEX_OPSIZE, /* 3186 */ + IC_VEX_OPSIZE, /* 3187 */ + IC_VEX_OPSIZE, /* 3188 */ + IC_VEX_OPSIZE, /* 3189 */ + IC_VEX_OPSIZE, /* 3190 */ + IC_VEX_OPSIZE, /* 3191 */ + IC_VEX_W_OPSIZE, /* 3192 */ + IC_VEX_W_OPSIZE, /* 3193 */ + IC_VEX_W_OPSIZE, /* 3194 */ + IC_VEX_W_OPSIZE, /* 3195 */ + IC_VEX_W_OPSIZE, /* 3196 */ + IC_VEX_W_OPSIZE, /* 3197 */ + IC_VEX_W_OPSIZE, /* 3198 */ + IC_VEX_W_OPSIZE, /* 3199 */ + IC_VEX_L, /* 3200 */ + IC_VEX_L, /* 3201 */ + IC_VEX_L_XS, /* 3202 */ + IC_VEX_L_XS, /* 3203 */ + IC_VEX_L_XD, /* 3204 */ + IC_VEX_L_XD, /* 3205 */ + IC_VEX_L_XD, /* 3206 */ + IC_VEX_L_XD, /* 3207 */ + IC_VEX_L_W, /* 3208 */ + IC_VEX_L_W, /* 3209 */ + IC_VEX_L_W_XS, /* 3210 */ + IC_VEX_L_W_XS, /* 3211 */ + IC_VEX_L_W_XD, /* 3212 */ + IC_VEX_L_W_XD, /* 3213 */ + IC_VEX_L_W_XD, /* 3214 */ + IC_VEX_L_W_XD, /* 3215 */ + IC_VEX_L_OPSIZE, /* 3216 */ + IC_VEX_L_OPSIZE, /* 3217 */ + IC_VEX_L_OPSIZE, /* 3218 */ + IC_VEX_L_OPSIZE, /* 3219 */ + IC_VEX_L_OPSIZE, /* 3220 */ + IC_VEX_L_OPSIZE, /* 3221 */ + IC_VEX_L_OPSIZE, /* 3222 */ + IC_VEX_L_OPSIZE, /* 3223 */ + IC_VEX_L_W_OPSIZE, /* 3224 */ + IC_VEX_L_W_OPSIZE, /* 3225 */ + IC_VEX_L_W_OPSIZE, /* 3226 */ + IC_VEX_L_W_OPSIZE, /* 3227 */ + IC_VEX_L_W_OPSIZE, /* 3228 */ + IC_VEX_L_W_OPSIZE, /* 3229 */ + IC_VEX_L_W_OPSIZE, /* 3230 */ + IC_VEX_L_W_OPSIZE, /* 3231 */ + IC_VEX_L, /* 3232 */ + IC_VEX_L, /* 3233 */ + IC_VEX_L_XS, /* 3234 */ + IC_VEX_L_XS, /* 3235 */ + IC_VEX_L_XD, /* 3236 */ + IC_VEX_L_XD, /* 3237 */ + IC_VEX_L_XD, /* 3238 */ + IC_VEX_L_XD, /* 3239 */ + IC_VEX_L_W, /* 3240 */ + IC_VEX_L_W, /* 3241 */ + IC_VEX_L_W_XS, /* 3242 */ + IC_VEX_L_W_XS, /* 3243 */ + IC_VEX_L_W_XD, /* 3244 */ + IC_VEX_L_W_XD, /* 3245 */ + IC_VEX_L_W_XD, /* 3246 */ + IC_VEX_L_W_XD, /* 3247 */ + IC_VEX_L_OPSIZE, /* 3248 */ + IC_VEX_L_OPSIZE, /* 3249 */ + IC_VEX_L_OPSIZE, /* 3250 */ + IC_VEX_L_OPSIZE, /* 3251 */ + IC_VEX_L_OPSIZE, /* 3252 */ + IC_VEX_L_OPSIZE, /* 3253 */ + IC_VEX_L_OPSIZE, /* 3254 */ + IC_VEX_L_OPSIZE, /* 3255 */ + IC_VEX_L_W_OPSIZE, /* 3256 */ + IC_VEX_L_W_OPSIZE, /* 3257 */ + IC_VEX_L_W_OPSIZE, /* 3258 */ + IC_VEX_L_W_OPSIZE, /* 3259 */ + IC_VEX_L_W_OPSIZE, /* 3260 */ + IC_VEX_L_W_OPSIZE, /* 3261 */ + IC_VEX_L_W_OPSIZE, /* 3262 */ + IC_VEX_L_W_OPSIZE, /* 3263 */ + IC_VEX_L, /* 3264 */ + IC_VEX_L, /* 3265 */ + IC_VEX_L_XS, /* 3266 */ + IC_VEX_L_XS, /* 3267 */ + IC_VEX_L_XD, /* 3268 */ + IC_VEX_L_XD, /* 3269 */ + IC_VEX_L_XD, /* 3270 */ + IC_VEX_L_XD, /* 3271 */ + IC_VEX_L_W, /* 3272 */ + IC_VEX_L_W, /* 3273 */ + IC_VEX_L_W_XS, /* 3274 */ + IC_VEX_L_W_XS, /* 3275 */ + IC_VEX_L_W_XD, /* 3276 */ + IC_VEX_L_W_XD, /* 3277 */ + IC_VEX_L_W_XD, /* 3278 */ + IC_VEX_L_W_XD, /* 3279 */ + IC_VEX_L_OPSIZE, /* 3280 */ + IC_VEX_L_OPSIZE, /* 3281 */ + IC_VEX_L_OPSIZE, /* 3282 */ + IC_VEX_L_OPSIZE, /* 3283 */ + IC_VEX_L_OPSIZE, /* 3284 */ + IC_VEX_L_OPSIZE, /* 3285 */ + IC_VEX_L_OPSIZE, /* 3286 */ + IC_VEX_L_OPSIZE, /* 3287 */ + IC_VEX_L_W_OPSIZE, /* 3288 */ + IC_VEX_L_W_OPSIZE, /* 3289 */ + IC_VEX_L_W_OPSIZE, /* 3290 */ + IC_VEX_L_W_OPSIZE, /* 3291 */ + IC_VEX_L_W_OPSIZE, /* 3292 */ + IC_VEX_L_W_OPSIZE, /* 3293 */ + IC_VEX_L_W_OPSIZE, /* 3294 */ + IC_VEX_L_W_OPSIZE, /* 3295 */ + IC_VEX_L, /* 3296 */ + IC_VEX_L, /* 3297 */ + IC_VEX_L_XS, /* 3298 */ + IC_VEX_L_XS, /* 3299 */ + IC_VEX_L_XD, /* 3300 */ + IC_VEX_L_XD, /* 3301 */ + IC_VEX_L_XD, /* 3302 */ + IC_VEX_L_XD, /* 3303 */ + IC_VEX_L_W, /* 3304 */ + IC_VEX_L_W, /* 3305 */ + IC_VEX_L_W_XS, /* 3306 */ + IC_VEX_L_W_XS, /* 3307 */ + IC_VEX_L_W_XD, /* 3308 */ + IC_VEX_L_W_XD, /* 3309 */ + IC_VEX_L_W_XD, /* 3310 */ + IC_VEX_L_W_XD, /* 3311 */ + IC_VEX_L_OPSIZE, /* 3312 */ + IC_VEX_L_OPSIZE, /* 3313 */ + IC_VEX_L_OPSIZE, /* 3314 */ + IC_VEX_L_OPSIZE, /* 3315 */ + IC_VEX_L_OPSIZE, /* 3316 */ + IC_VEX_L_OPSIZE, /* 3317 */ + IC_VEX_L_OPSIZE, /* 3318 */ + IC_VEX_L_OPSIZE, /* 3319 */ + IC_VEX_L_W_OPSIZE, /* 3320 */ + IC_VEX_L_W_OPSIZE, /* 3321 */ + IC_VEX_L_W_OPSIZE, /* 3322 */ + IC_VEX_L_W_OPSIZE, /* 3323 */ + IC_VEX_L_W_OPSIZE, /* 3324 */ + IC_VEX_L_W_OPSIZE, /* 3325 */ + IC_VEX_L_W_OPSIZE, /* 3326 */ + IC_VEX_L_W_OPSIZE, /* 3327 */ + IC_EVEX_L2_K, /* 3328 */ + IC_EVEX_L2_K, /* 3329 */ + IC_EVEX_L2_XS_K, /* 3330 */ + IC_EVEX_L2_XS_K, /* 3331 */ + IC_EVEX_L2_XD_K, /* 3332 */ + IC_EVEX_L2_XD_K, /* 3333 */ + IC_EVEX_L2_XD_K, /* 3334 */ + IC_EVEX_L2_XD_K, /* 3335 */ + IC_EVEX_L2_W_K, /* 3336 */ + IC_EVEX_L2_W_K, /* 3337 */ + IC_EVEX_L2_W_XS_K, /* 3338 */ + IC_EVEX_L2_W_XS_K, /* 3339 */ + IC_EVEX_L2_W_XD_K, /* 3340 */ + IC_EVEX_L2_W_XD_K, /* 3341 */ + IC_EVEX_L2_W_XD_K, /* 3342 */ + IC_EVEX_L2_W_XD_K, /* 3343 */ + IC_EVEX_L2_OPSIZE_K, /* 3344 */ + IC_EVEX_L2_OPSIZE_K, /* 3345 */ + IC_EVEX_L2_OPSIZE_K, /* 3346 */ + IC_EVEX_L2_OPSIZE_K, /* 3347 */ + IC_EVEX_L2_OPSIZE_K, /* 3348 */ + IC_EVEX_L2_OPSIZE_K, /* 3349 */ + IC_EVEX_L2_OPSIZE_K, /* 3350 */ + IC_EVEX_L2_OPSIZE_K, /* 3351 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3352 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3353 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3354 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3355 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3356 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3357 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3358 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3359 */ + IC_EVEX_L2_K, /* 3360 */ + IC_EVEX_L2_K, /* 3361 */ + IC_EVEX_L2_XS_K, /* 3362 */ + IC_EVEX_L2_XS_K, /* 3363 */ + IC_EVEX_L2_XD_K, /* 3364 */ + IC_EVEX_L2_XD_K, /* 3365 */ + IC_EVEX_L2_XD_K, /* 3366 */ + IC_EVEX_L2_XD_K, /* 3367 */ + IC_EVEX_L2_W_K, /* 3368 */ + IC_EVEX_L2_W_K, /* 3369 */ + IC_EVEX_L2_W_XS_K, /* 3370 */ + IC_EVEX_L2_W_XS_K, /* 3371 */ + IC_EVEX_L2_W_XD_K, /* 3372 */ + IC_EVEX_L2_W_XD_K, /* 3373 */ + IC_EVEX_L2_W_XD_K, /* 3374 */ + IC_EVEX_L2_W_XD_K, /* 3375 */ + IC_EVEX_L2_OPSIZE_K, /* 3376 */ + IC_EVEX_L2_OPSIZE_K, /* 3377 */ + IC_EVEX_L2_OPSIZE_K, /* 3378 */ + IC_EVEX_L2_OPSIZE_K, /* 3379 */ + IC_EVEX_L2_OPSIZE_K, /* 3380 */ + IC_EVEX_L2_OPSIZE_K, /* 3381 */ + IC_EVEX_L2_OPSIZE_K, /* 3382 */ + IC_EVEX_L2_OPSIZE_K, /* 3383 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3384 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3385 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3386 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3387 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3388 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3389 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3390 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3391 */ + IC_EVEX_L2_K, /* 3392 */ + IC_EVEX_L2_K, /* 3393 */ + IC_EVEX_L2_XS_K, /* 3394 */ + IC_EVEX_L2_XS_K, /* 3395 */ + IC_EVEX_L2_XD_K, /* 3396 */ + IC_EVEX_L2_XD_K, /* 3397 */ + IC_EVEX_L2_XD_K, /* 3398 */ + IC_EVEX_L2_XD_K, /* 3399 */ + IC_EVEX_L2_W_K, /* 3400 */ + IC_EVEX_L2_W_K, /* 3401 */ + IC_EVEX_L2_W_XS_K, /* 3402 */ + IC_EVEX_L2_W_XS_K, /* 3403 */ + IC_EVEX_L2_W_XD_K, /* 3404 */ + IC_EVEX_L2_W_XD_K, /* 3405 */ + IC_EVEX_L2_W_XD_K, /* 3406 */ + IC_EVEX_L2_W_XD_K, /* 3407 */ + IC_EVEX_L2_OPSIZE_K, /* 3408 */ + IC_EVEX_L2_OPSIZE_K, /* 3409 */ + IC_EVEX_L2_OPSIZE_K, /* 3410 */ + IC_EVEX_L2_OPSIZE_K, /* 3411 */ + IC_EVEX_L2_OPSIZE_K, /* 3412 */ + IC_EVEX_L2_OPSIZE_K, /* 3413 */ + IC_EVEX_L2_OPSIZE_K, /* 3414 */ + IC_EVEX_L2_OPSIZE_K, /* 3415 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3416 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3417 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3418 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3419 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3420 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3421 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3422 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3423 */ + IC_EVEX_L2_K, /* 3424 */ + IC_EVEX_L2_K, /* 3425 */ + IC_EVEX_L2_XS_K, /* 3426 */ + IC_EVEX_L2_XS_K, /* 3427 */ + IC_EVEX_L2_XD_K, /* 3428 */ + IC_EVEX_L2_XD_K, /* 3429 */ + IC_EVEX_L2_XD_K, /* 3430 */ + IC_EVEX_L2_XD_K, /* 3431 */ + IC_EVEX_L2_W_K, /* 3432 */ + IC_EVEX_L2_W_K, /* 3433 */ + IC_EVEX_L2_W_XS_K, /* 3434 */ + IC_EVEX_L2_W_XS_K, /* 3435 */ + IC_EVEX_L2_W_XD_K, /* 3436 */ + IC_EVEX_L2_W_XD_K, /* 3437 */ + IC_EVEX_L2_W_XD_K, /* 3438 */ + IC_EVEX_L2_W_XD_K, /* 3439 */ + IC_EVEX_L2_OPSIZE_K, /* 3440 */ + IC_EVEX_L2_OPSIZE_K, /* 3441 */ + IC_EVEX_L2_OPSIZE_K, /* 3442 */ + IC_EVEX_L2_OPSIZE_K, /* 3443 */ + IC_EVEX_L2_OPSIZE_K, /* 3444 */ + IC_EVEX_L2_OPSIZE_K, /* 3445 */ + IC_EVEX_L2_OPSIZE_K, /* 3446 */ + IC_EVEX_L2_OPSIZE_K, /* 3447 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3448 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3449 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3450 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3451 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3452 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3453 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3454 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3455 */ + IC_EVEX_L2_K, /* 3456 */ + IC_EVEX_L2_K, /* 3457 */ + IC_EVEX_L2_XS_K, /* 3458 */ + IC_EVEX_L2_XS_K, /* 3459 */ + IC_EVEX_L2_XD_K, /* 3460 */ + IC_EVEX_L2_XD_K, /* 3461 */ + IC_EVEX_L2_XD_K, /* 3462 */ + IC_EVEX_L2_XD_K, /* 3463 */ + IC_EVEX_L2_W_K, /* 3464 */ + IC_EVEX_L2_W_K, /* 3465 */ + IC_EVEX_L2_W_XS_K, /* 3466 */ + IC_EVEX_L2_W_XS_K, /* 3467 */ + IC_EVEX_L2_W_XD_K, /* 3468 */ + IC_EVEX_L2_W_XD_K, /* 3469 */ + IC_EVEX_L2_W_XD_K, /* 3470 */ + IC_EVEX_L2_W_XD_K, /* 3471 */ + IC_EVEX_L2_OPSIZE_K, /* 3472 */ + IC_EVEX_L2_OPSIZE_K, /* 3473 */ + IC_EVEX_L2_OPSIZE_K, /* 3474 */ + IC_EVEX_L2_OPSIZE_K, /* 3475 */ + IC_EVEX_L2_OPSIZE_K, /* 3476 */ + IC_EVEX_L2_OPSIZE_K, /* 3477 */ + IC_EVEX_L2_OPSIZE_K, /* 3478 */ + IC_EVEX_L2_OPSIZE_K, /* 3479 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3480 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3481 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3482 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3483 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3484 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3485 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3486 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3487 */ + IC_EVEX_L2_K, /* 3488 */ + IC_EVEX_L2_K, /* 3489 */ + IC_EVEX_L2_XS_K, /* 3490 */ + IC_EVEX_L2_XS_K, /* 3491 */ + IC_EVEX_L2_XD_K, /* 3492 */ + IC_EVEX_L2_XD_K, /* 3493 */ + IC_EVEX_L2_XD_K, /* 3494 */ + IC_EVEX_L2_XD_K, /* 3495 */ + IC_EVEX_L2_W_K, /* 3496 */ + IC_EVEX_L2_W_K, /* 3497 */ + IC_EVEX_L2_W_XS_K, /* 3498 */ + IC_EVEX_L2_W_XS_K, /* 3499 */ + IC_EVEX_L2_W_XD_K, /* 3500 */ + IC_EVEX_L2_W_XD_K, /* 3501 */ + IC_EVEX_L2_W_XD_K, /* 3502 */ + IC_EVEX_L2_W_XD_K, /* 3503 */ + IC_EVEX_L2_OPSIZE_K, /* 3504 */ + IC_EVEX_L2_OPSIZE_K, /* 3505 */ + IC_EVEX_L2_OPSIZE_K, /* 3506 */ + IC_EVEX_L2_OPSIZE_K, /* 3507 */ + IC_EVEX_L2_OPSIZE_K, /* 3508 */ + IC_EVEX_L2_OPSIZE_K, /* 3509 */ + IC_EVEX_L2_OPSIZE_K, /* 3510 */ + IC_EVEX_L2_OPSIZE_K, /* 3511 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3512 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3513 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3514 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3515 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3516 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3517 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3518 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3519 */ + IC_EVEX_L2_K, /* 3520 */ + IC_EVEX_L2_K, /* 3521 */ + IC_EVEX_L2_XS_K, /* 3522 */ + IC_EVEX_L2_XS_K, /* 3523 */ + IC_EVEX_L2_XD_K, /* 3524 */ + IC_EVEX_L2_XD_K, /* 3525 */ + IC_EVEX_L2_XD_K, /* 3526 */ + IC_EVEX_L2_XD_K, /* 3527 */ + IC_EVEX_L2_W_K, /* 3528 */ + IC_EVEX_L2_W_K, /* 3529 */ + IC_EVEX_L2_W_XS_K, /* 3530 */ + IC_EVEX_L2_W_XS_K, /* 3531 */ + IC_EVEX_L2_W_XD_K, /* 3532 */ + IC_EVEX_L2_W_XD_K, /* 3533 */ + IC_EVEX_L2_W_XD_K, /* 3534 */ + IC_EVEX_L2_W_XD_K, /* 3535 */ + IC_EVEX_L2_OPSIZE_K, /* 3536 */ + IC_EVEX_L2_OPSIZE_K, /* 3537 */ + IC_EVEX_L2_OPSIZE_K, /* 3538 */ + IC_EVEX_L2_OPSIZE_K, /* 3539 */ + IC_EVEX_L2_OPSIZE_K, /* 3540 */ + IC_EVEX_L2_OPSIZE_K, /* 3541 */ + IC_EVEX_L2_OPSIZE_K, /* 3542 */ + IC_EVEX_L2_OPSIZE_K, /* 3543 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3544 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3545 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3546 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3547 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3548 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3549 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3550 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3551 */ + IC_EVEX_L2_K, /* 3552 */ + IC_EVEX_L2_K, /* 3553 */ + IC_EVEX_L2_XS_K, /* 3554 */ + IC_EVEX_L2_XS_K, /* 3555 */ + IC_EVEX_L2_XD_K, /* 3556 */ + IC_EVEX_L2_XD_K, /* 3557 */ + IC_EVEX_L2_XD_K, /* 3558 */ + IC_EVEX_L2_XD_K, /* 3559 */ + IC_EVEX_L2_W_K, /* 3560 */ + IC_EVEX_L2_W_K, /* 3561 */ + IC_EVEX_L2_W_XS_K, /* 3562 */ + IC_EVEX_L2_W_XS_K, /* 3563 */ + IC_EVEX_L2_W_XD_K, /* 3564 */ + IC_EVEX_L2_W_XD_K, /* 3565 */ + IC_EVEX_L2_W_XD_K, /* 3566 */ + IC_EVEX_L2_W_XD_K, /* 3567 */ + IC_EVEX_L2_OPSIZE_K, /* 3568 */ + IC_EVEX_L2_OPSIZE_K, /* 3569 */ + IC_EVEX_L2_OPSIZE_K, /* 3570 */ + IC_EVEX_L2_OPSIZE_K, /* 3571 */ + IC_EVEX_L2_OPSIZE_K, /* 3572 */ + IC_EVEX_L2_OPSIZE_K, /* 3573 */ + IC_EVEX_L2_OPSIZE_K, /* 3574 */ + IC_EVEX_L2_OPSIZE_K, /* 3575 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3576 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3577 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3578 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3579 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3580 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3581 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3582 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3583 */ + IC, /* 3584 */ + IC_64BIT, /* 3585 */ + IC_XS, /* 3586 */ + IC_64BIT_XS, /* 3587 */ + IC_XD, /* 3588 */ + IC_64BIT_XD, /* 3589 */ + IC_XS, /* 3590 */ + IC_64BIT_XS, /* 3591 */ + IC, /* 3592 */ + IC_64BIT_REXW, /* 3593 */ + IC_XS, /* 3594 */ + IC_64BIT_REXW_XS, /* 3595 */ + IC_XD, /* 3596 */ + IC_64BIT_REXW_XD, /* 3597 */ + IC_XS, /* 3598 */ + IC_64BIT_REXW_XS, /* 3599 */ + IC_OPSIZE, /* 3600 */ + IC_64BIT_OPSIZE, /* 3601 */ + IC_XS_OPSIZE, /* 3602 */ + IC_64BIT_XS_OPSIZE, /* 3603 */ + IC_XD_OPSIZE, /* 3604 */ + IC_64BIT_XD_OPSIZE, /* 3605 */ + IC_XS_OPSIZE, /* 3606 */ + IC_64BIT_XD_OPSIZE, /* 3607 */ + IC_OPSIZE, /* 3608 */ + IC_64BIT_REXW_OPSIZE, /* 3609 */ + IC_XS_OPSIZE, /* 3610 */ + IC_64BIT_REXW_XS, /* 3611 */ + IC_XD_OPSIZE, /* 3612 */ + IC_64BIT_REXW_XD, /* 3613 */ + IC_XS_OPSIZE, /* 3614 */ + IC_64BIT_REXW_XS, /* 3615 */ + IC_ADSIZE, /* 3616 */ + IC_64BIT_ADSIZE, /* 3617 */ + IC_XS_ADSIZE, /* 3618 */ + IC_64BIT_XS_ADSIZE, /* 3619 */ + IC_XD_ADSIZE, /* 3620 */ + IC_64BIT_XD_ADSIZE, /* 3621 */ + IC_XS_ADSIZE, /* 3622 */ + IC_64BIT_XD_ADSIZE, /* 3623 */ + IC_ADSIZE, /* 3624 */ + IC_64BIT_REXW_ADSIZE, /* 3625 */ + IC_XS_ADSIZE, /* 3626 */ + IC_64BIT_REXW_XS, /* 3627 */ + IC_XD_ADSIZE, /* 3628 */ + IC_64BIT_REXW_XD, /* 3629 */ + IC_XS_ADSIZE, /* 3630 */ + IC_64BIT_REXW_XS, /* 3631 */ + IC_OPSIZE_ADSIZE, /* 3632 */ + IC_64BIT_OPSIZE_ADSIZE, /* 3633 */ + IC_XS_OPSIZE, /* 3634 */ + IC_64BIT_XS_OPSIZE, /* 3635 */ + IC_XD_OPSIZE, /* 3636 */ + IC_64BIT_XD_OPSIZE, /* 3637 */ + IC_XS_OPSIZE, /* 3638 */ + IC_64BIT_XD_OPSIZE, /* 3639 */ + IC_OPSIZE_ADSIZE, /* 3640 */ + IC_64BIT_REXW_OPSIZE, /* 3641 */ + IC_XS_OPSIZE, /* 3642 */ + IC_64BIT_REXW_XS, /* 3643 */ + IC_XD_OPSIZE, /* 3644 */ + IC_64BIT_REXW_XD, /* 3645 */ + IC_XS_OPSIZE, /* 3646 */ + IC_64BIT_REXW_XS, /* 3647 */ + IC_VEX, /* 3648 */ + IC_VEX, /* 3649 */ + IC_VEX_XS, /* 3650 */ + IC_VEX_XS, /* 3651 */ + IC_VEX_XD, /* 3652 */ + IC_VEX_XD, /* 3653 */ + IC_VEX_XD, /* 3654 */ + IC_VEX_XD, /* 3655 */ + IC_VEX_W, /* 3656 */ + IC_VEX_W, /* 3657 */ + IC_VEX_W_XS, /* 3658 */ + IC_VEX_W_XS, /* 3659 */ + IC_VEX_W_XD, /* 3660 */ + IC_VEX_W_XD, /* 3661 */ + IC_VEX_W_XD, /* 3662 */ + IC_VEX_W_XD, /* 3663 */ + IC_VEX_OPSIZE, /* 3664 */ + IC_VEX_OPSIZE, /* 3665 */ + IC_VEX_OPSIZE, /* 3666 */ + IC_VEX_OPSIZE, /* 3667 */ + IC_VEX_OPSIZE, /* 3668 */ + IC_VEX_OPSIZE, /* 3669 */ + IC_VEX_OPSIZE, /* 3670 */ + IC_VEX_OPSIZE, /* 3671 */ + IC_VEX_W_OPSIZE, /* 3672 */ + IC_VEX_W_OPSIZE, /* 3673 */ + IC_VEX_W_OPSIZE, /* 3674 */ + IC_VEX_W_OPSIZE, /* 3675 */ + IC_VEX_W_OPSIZE, /* 3676 */ + IC_VEX_W_OPSIZE, /* 3677 */ + IC_VEX_W_OPSIZE, /* 3678 */ + IC_VEX_W_OPSIZE, /* 3679 */ + IC_VEX, /* 3680 */ + IC_VEX, /* 3681 */ + IC_VEX_XS, /* 3682 */ + IC_VEX_XS, /* 3683 */ + IC_VEX_XD, /* 3684 */ + IC_VEX_XD, /* 3685 */ + IC_VEX_XD, /* 3686 */ + IC_VEX_XD, /* 3687 */ + IC_VEX_W, /* 3688 */ + IC_VEX_W, /* 3689 */ + IC_VEX_W_XS, /* 3690 */ + IC_VEX_W_XS, /* 3691 */ + IC_VEX_W_XD, /* 3692 */ + IC_VEX_W_XD, /* 3693 */ + IC_VEX_W_XD, /* 3694 */ + IC_VEX_W_XD, /* 3695 */ + IC_VEX_OPSIZE, /* 3696 */ + IC_VEX_OPSIZE, /* 3697 */ + IC_VEX_OPSIZE, /* 3698 */ + IC_VEX_OPSIZE, /* 3699 */ + IC_VEX_OPSIZE, /* 3700 */ + IC_VEX_OPSIZE, /* 3701 */ + IC_VEX_OPSIZE, /* 3702 */ + IC_VEX_OPSIZE, /* 3703 */ + IC_VEX_W_OPSIZE, /* 3704 */ + IC_VEX_W_OPSIZE, /* 3705 */ + IC_VEX_W_OPSIZE, /* 3706 */ + IC_VEX_W_OPSIZE, /* 3707 */ + IC_VEX_W_OPSIZE, /* 3708 */ + IC_VEX_W_OPSIZE, /* 3709 */ + IC_VEX_W_OPSIZE, /* 3710 */ + IC_VEX_W_OPSIZE, /* 3711 */ + IC_VEX_L, /* 3712 */ + IC_VEX_L, /* 3713 */ + IC_VEX_L_XS, /* 3714 */ + IC_VEX_L_XS, /* 3715 */ + IC_VEX_L_XD, /* 3716 */ + IC_VEX_L_XD, /* 3717 */ + IC_VEX_L_XD, /* 3718 */ + IC_VEX_L_XD, /* 3719 */ + IC_VEX_L_W, /* 3720 */ + IC_VEX_L_W, /* 3721 */ + IC_VEX_L_W_XS, /* 3722 */ + IC_VEX_L_W_XS, /* 3723 */ + IC_VEX_L_W_XD, /* 3724 */ + IC_VEX_L_W_XD, /* 3725 */ + IC_VEX_L_W_XD, /* 3726 */ + IC_VEX_L_W_XD, /* 3727 */ + IC_VEX_L_OPSIZE, /* 3728 */ + IC_VEX_L_OPSIZE, /* 3729 */ + IC_VEX_L_OPSIZE, /* 3730 */ + IC_VEX_L_OPSIZE, /* 3731 */ + IC_VEX_L_OPSIZE, /* 3732 */ + IC_VEX_L_OPSIZE, /* 3733 */ + IC_VEX_L_OPSIZE, /* 3734 */ + IC_VEX_L_OPSIZE, /* 3735 */ + IC_VEX_L_W_OPSIZE, /* 3736 */ + IC_VEX_L_W_OPSIZE, /* 3737 */ + IC_VEX_L_W_OPSIZE, /* 3738 */ + IC_VEX_L_W_OPSIZE, /* 3739 */ + IC_VEX_L_W_OPSIZE, /* 3740 */ + IC_VEX_L_W_OPSIZE, /* 3741 */ + IC_VEX_L_W_OPSIZE, /* 3742 */ + IC_VEX_L_W_OPSIZE, /* 3743 */ + IC_VEX_L, /* 3744 */ + IC_VEX_L, /* 3745 */ + IC_VEX_L_XS, /* 3746 */ + IC_VEX_L_XS, /* 3747 */ + IC_VEX_L_XD, /* 3748 */ + IC_VEX_L_XD, /* 3749 */ + IC_VEX_L_XD, /* 3750 */ + IC_VEX_L_XD, /* 3751 */ + IC_VEX_L_W, /* 3752 */ + IC_VEX_L_W, /* 3753 */ + IC_VEX_L_W_XS, /* 3754 */ + IC_VEX_L_W_XS, /* 3755 */ + IC_VEX_L_W_XD, /* 3756 */ + IC_VEX_L_W_XD, /* 3757 */ + IC_VEX_L_W_XD, /* 3758 */ + IC_VEX_L_W_XD, /* 3759 */ + IC_VEX_L_OPSIZE, /* 3760 */ + IC_VEX_L_OPSIZE, /* 3761 */ + IC_VEX_L_OPSIZE, /* 3762 */ + IC_VEX_L_OPSIZE, /* 3763 */ + IC_VEX_L_OPSIZE, /* 3764 */ + IC_VEX_L_OPSIZE, /* 3765 */ + IC_VEX_L_OPSIZE, /* 3766 */ + IC_VEX_L_OPSIZE, /* 3767 */ + IC_VEX_L_W_OPSIZE, /* 3768 */ + IC_VEX_L_W_OPSIZE, /* 3769 */ + IC_VEX_L_W_OPSIZE, /* 3770 */ + IC_VEX_L_W_OPSIZE, /* 3771 */ + IC_VEX_L_W_OPSIZE, /* 3772 */ + IC_VEX_L_W_OPSIZE, /* 3773 */ + IC_VEX_L_W_OPSIZE, /* 3774 */ + IC_VEX_L_W_OPSIZE, /* 3775 */ + IC_VEX_L, /* 3776 */ + IC_VEX_L, /* 3777 */ + IC_VEX_L_XS, /* 3778 */ + IC_VEX_L_XS, /* 3779 */ + IC_VEX_L_XD, /* 3780 */ + IC_VEX_L_XD, /* 3781 */ + IC_VEX_L_XD, /* 3782 */ + IC_VEX_L_XD, /* 3783 */ + IC_VEX_L_W, /* 3784 */ + IC_VEX_L_W, /* 3785 */ + IC_VEX_L_W_XS, /* 3786 */ + IC_VEX_L_W_XS, /* 3787 */ + IC_VEX_L_W_XD, /* 3788 */ + IC_VEX_L_W_XD, /* 3789 */ + IC_VEX_L_W_XD, /* 3790 */ + IC_VEX_L_W_XD, /* 3791 */ + IC_VEX_L_OPSIZE, /* 3792 */ + IC_VEX_L_OPSIZE, /* 3793 */ + IC_VEX_L_OPSIZE, /* 3794 */ + IC_VEX_L_OPSIZE, /* 3795 */ + IC_VEX_L_OPSIZE, /* 3796 */ + IC_VEX_L_OPSIZE, /* 3797 */ + IC_VEX_L_OPSIZE, /* 3798 */ + IC_VEX_L_OPSIZE, /* 3799 */ + IC_VEX_L_W_OPSIZE, /* 3800 */ + IC_VEX_L_W_OPSIZE, /* 3801 */ + IC_VEX_L_W_OPSIZE, /* 3802 */ + IC_VEX_L_W_OPSIZE, /* 3803 */ + IC_VEX_L_W_OPSIZE, /* 3804 */ + IC_VEX_L_W_OPSIZE, /* 3805 */ + IC_VEX_L_W_OPSIZE, /* 3806 */ + IC_VEX_L_W_OPSIZE, /* 3807 */ + IC_VEX_L, /* 3808 */ + IC_VEX_L, /* 3809 */ + IC_VEX_L_XS, /* 3810 */ + IC_VEX_L_XS, /* 3811 */ + IC_VEX_L_XD, /* 3812 */ + IC_VEX_L_XD, /* 3813 */ + IC_VEX_L_XD, /* 3814 */ + IC_VEX_L_XD, /* 3815 */ + IC_VEX_L_W, /* 3816 */ + IC_VEX_L_W, /* 3817 */ + IC_VEX_L_W_XS, /* 3818 */ + IC_VEX_L_W_XS, /* 3819 */ + IC_VEX_L_W_XD, /* 3820 */ + IC_VEX_L_W_XD, /* 3821 */ + IC_VEX_L_W_XD, /* 3822 */ + IC_VEX_L_W_XD, /* 3823 */ + IC_VEX_L_OPSIZE, /* 3824 */ + IC_VEX_L_OPSIZE, /* 3825 */ + IC_VEX_L_OPSIZE, /* 3826 */ + IC_VEX_L_OPSIZE, /* 3827 */ + IC_VEX_L_OPSIZE, /* 3828 */ + IC_VEX_L_OPSIZE, /* 3829 */ + IC_VEX_L_OPSIZE, /* 3830 */ + IC_VEX_L_OPSIZE, /* 3831 */ + IC_VEX_L_W_OPSIZE, /* 3832 */ + IC_VEX_L_W_OPSIZE, /* 3833 */ + IC_VEX_L_W_OPSIZE, /* 3834 */ + IC_VEX_L_W_OPSIZE, /* 3835 */ + IC_VEX_L_W_OPSIZE, /* 3836 */ + IC_VEX_L_W_OPSIZE, /* 3837 */ + IC_VEX_L_W_OPSIZE, /* 3838 */ + IC_VEX_L_W_OPSIZE, /* 3839 */ + IC_EVEX_L2_K, /* 3840 */ + IC_EVEX_L2_K, /* 3841 */ + IC_EVEX_L2_XS_K, /* 3842 */ + IC_EVEX_L2_XS_K, /* 3843 */ + IC_EVEX_L2_XD_K, /* 3844 */ + IC_EVEX_L2_XD_K, /* 3845 */ + IC_EVEX_L2_XD_K, /* 3846 */ + IC_EVEX_L2_XD_K, /* 3847 */ + IC_EVEX_L2_W_K, /* 3848 */ + IC_EVEX_L2_W_K, /* 3849 */ + IC_EVEX_L2_W_XS_K, /* 3850 */ + IC_EVEX_L2_W_XS_K, /* 3851 */ + IC_EVEX_L2_W_XD_K, /* 3852 */ + IC_EVEX_L2_W_XD_K, /* 3853 */ + IC_EVEX_L2_W_XD_K, /* 3854 */ + IC_EVEX_L2_W_XD_K, /* 3855 */ + IC_EVEX_L2_OPSIZE_K, /* 3856 */ + IC_EVEX_L2_OPSIZE_K, /* 3857 */ + IC_EVEX_L2_OPSIZE_K, /* 3858 */ + IC_EVEX_L2_OPSIZE_K, /* 3859 */ + IC_EVEX_L2_OPSIZE_K, /* 3860 */ + IC_EVEX_L2_OPSIZE_K, /* 3861 */ + IC_EVEX_L2_OPSIZE_K, /* 3862 */ + IC_EVEX_L2_OPSIZE_K, /* 3863 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3864 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3865 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3866 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3867 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3868 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3869 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3870 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3871 */ + IC_EVEX_L2_K, /* 3872 */ + IC_EVEX_L2_K, /* 3873 */ + IC_EVEX_L2_XS_K, /* 3874 */ + IC_EVEX_L2_XS_K, /* 3875 */ + IC_EVEX_L2_XD_K, /* 3876 */ + IC_EVEX_L2_XD_K, /* 3877 */ + IC_EVEX_L2_XD_K, /* 3878 */ + IC_EVEX_L2_XD_K, /* 3879 */ + IC_EVEX_L2_W_K, /* 3880 */ + IC_EVEX_L2_W_K, /* 3881 */ + IC_EVEX_L2_W_XS_K, /* 3882 */ + IC_EVEX_L2_W_XS_K, /* 3883 */ + IC_EVEX_L2_W_XD_K, /* 3884 */ + IC_EVEX_L2_W_XD_K, /* 3885 */ + IC_EVEX_L2_W_XD_K, /* 3886 */ + IC_EVEX_L2_W_XD_K, /* 3887 */ + IC_EVEX_L2_OPSIZE_K, /* 3888 */ + IC_EVEX_L2_OPSIZE_K, /* 3889 */ + IC_EVEX_L2_OPSIZE_K, /* 3890 */ + IC_EVEX_L2_OPSIZE_K, /* 3891 */ + IC_EVEX_L2_OPSIZE_K, /* 3892 */ + IC_EVEX_L2_OPSIZE_K, /* 3893 */ + IC_EVEX_L2_OPSIZE_K, /* 3894 */ + IC_EVEX_L2_OPSIZE_K, /* 3895 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3896 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3897 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3898 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3899 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3900 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3901 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3902 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3903 */ + IC_EVEX_L2_K, /* 3904 */ + IC_EVEX_L2_K, /* 3905 */ + IC_EVEX_L2_XS_K, /* 3906 */ + IC_EVEX_L2_XS_K, /* 3907 */ + IC_EVEX_L2_XD_K, /* 3908 */ + IC_EVEX_L2_XD_K, /* 3909 */ + IC_EVEX_L2_XD_K, /* 3910 */ + IC_EVEX_L2_XD_K, /* 3911 */ + IC_EVEX_L2_W_K, /* 3912 */ + IC_EVEX_L2_W_K, /* 3913 */ + IC_EVEX_L2_W_XS_K, /* 3914 */ + IC_EVEX_L2_W_XS_K, /* 3915 */ + IC_EVEX_L2_W_XD_K, /* 3916 */ + IC_EVEX_L2_W_XD_K, /* 3917 */ + IC_EVEX_L2_W_XD_K, /* 3918 */ + IC_EVEX_L2_W_XD_K, /* 3919 */ + IC_EVEX_L2_OPSIZE_K, /* 3920 */ + IC_EVEX_L2_OPSIZE_K, /* 3921 */ + IC_EVEX_L2_OPSIZE_K, /* 3922 */ + IC_EVEX_L2_OPSIZE_K, /* 3923 */ + IC_EVEX_L2_OPSIZE_K, /* 3924 */ + IC_EVEX_L2_OPSIZE_K, /* 3925 */ + IC_EVEX_L2_OPSIZE_K, /* 3926 */ + IC_EVEX_L2_OPSIZE_K, /* 3927 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3928 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3929 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3930 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3931 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3932 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3933 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3934 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3935 */ + IC_EVEX_L2_K, /* 3936 */ + IC_EVEX_L2_K, /* 3937 */ + IC_EVEX_L2_XS_K, /* 3938 */ + IC_EVEX_L2_XS_K, /* 3939 */ + IC_EVEX_L2_XD_K, /* 3940 */ + IC_EVEX_L2_XD_K, /* 3941 */ + IC_EVEX_L2_XD_K, /* 3942 */ + IC_EVEX_L2_XD_K, /* 3943 */ + IC_EVEX_L2_W_K, /* 3944 */ + IC_EVEX_L2_W_K, /* 3945 */ + IC_EVEX_L2_W_XS_K, /* 3946 */ + IC_EVEX_L2_W_XS_K, /* 3947 */ + IC_EVEX_L2_W_XD_K, /* 3948 */ + IC_EVEX_L2_W_XD_K, /* 3949 */ + IC_EVEX_L2_W_XD_K, /* 3950 */ + IC_EVEX_L2_W_XD_K, /* 3951 */ + IC_EVEX_L2_OPSIZE_K, /* 3952 */ + IC_EVEX_L2_OPSIZE_K, /* 3953 */ + IC_EVEX_L2_OPSIZE_K, /* 3954 */ + IC_EVEX_L2_OPSIZE_K, /* 3955 */ + IC_EVEX_L2_OPSIZE_K, /* 3956 */ + IC_EVEX_L2_OPSIZE_K, /* 3957 */ + IC_EVEX_L2_OPSIZE_K, /* 3958 */ + IC_EVEX_L2_OPSIZE_K, /* 3959 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3960 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3961 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3962 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3963 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3964 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3965 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3966 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3967 */ + IC_EVEX_L2_K, /* 3968 */ + IC_EVEX_L2_K, /* 3969 */ + IC_EVEX_L2_XS_K, /* 3970 */ + IC_EVEX_L2_XS_K, /* 3971 */ + IC_EVEX_L2_XD_K, /* 3972 */ + IC_EVEX_L2_XD_K, /* 3973 */ + IC_EVEX_L2_XD_K, /* 3974 */ + IC_EVEX_L2_XD_K, /* 3975 */ + IC_EVEX_L2_W_K, /* 3976 */ + IC_EVEX_L2_W_K, /* 3977 */ + IC_EVEX_L2_W_XS_K, /* 3978 */ + IC_EVEX_L2_W_XS_K, /* 3979 */ + IC_EVEX_L2_W_XD_K, /* 3980 */ + IC_EVEX_L2_W_XD_K, /* 3981 */ + IC_EVEX_L2_W_XD_K, /* 3982 */ + IC_EVEX_L2_W_XD_K, /* 3983 */ + IC_EVEX_L2_OPSIZE_K, /* 3984 */ + IC_EVEX_L2_OPSIZE_K, /* 3985 */ + IC_EVEX_L2_OPSIZE_K, /* 3986 */ + IC_EVEX_L2_OPSIZE_K, /* 3987 */ + IC_EVEX_L2_OPSIZE_K, /* 3988 */ + IC_EVEX_L2_OPSIZE_K, /* 3989 */ + IC_EVEX_L2_OPSIZE_K, /* 3990 */ + IC_EVEX_L2_OPSIZE_K, /* 3991 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3992 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3993 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3994 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3995 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3996 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3997 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3998 */ + IC_EVEX_L2_W_OPSIZE_K, /* 3999 */ + IC_EVEX_L2_K, /* 4000 */ + IC_EVEX_L2_K, /* 4001 */ + IC_EVEX_L2_XS_K, /* 4002 */ + IC_EVEX_L2_XS_K, /* 4003 */ + IC_EVEX_L2_XD_K, /* 4004 */ + IC_EVEX_L2_XD_K, /* 4005 */ + IC_EVEX_L2_XD_K, /* 4006 */ + IC_EVEX_L2_XD_K, /* 4007 */ + IC_EVEX_L2_W_K, /* 4008 */ + IC_EVEX_L2_W_K, /* 4009 */ + IC_EVEX_L2_W_XS_K, /* 4010 */ + IC_EVEX_L2_W_XS_K, /* 4011 */ + IC_EVEX_L2_W_XD_K, /* 4012 */ + IC_EVEX_L2_W_XD_K, /* 4013 */ + IC_EVEX_L2_W_XD_K, /* 4014 */ + IC_EVEX_L2_W_XD_K, /* 4015 */ + IC_EVEX_L2_OPSIZE_K, /* 4016 */ + IC_EVEX_L2_OPSIZE_K, /* 4017 */ + IC_EVEX_L2_OPSIZE_K, /* 4018 */ + IC_EVEX_L2_OPSIZE_K, /* 4019 */ + IC_EVEX_L2_OPSIZE_K, /* 4020 */ + IC_EVEX_L2_OPSIZE_K, /* 4021 */ + IC_EVEX_L2_OPSIZE_K, /* 4022 */ + IC_EVEX_L2_OPSIZE_K, /* 4023 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4024 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4025 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4026 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4027 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4028 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4029 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4030 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4031 */ + IC_EVEX_L2_K, /* 4032 */ + IC_EVEX_L2_K, /* 4033 */ + IC_EVEX_L2_XS_K, /* 4034 */ + IC_EVEX_L2_XS_K, /* 4035 */ + IC_EVEX_L2_XD_K, /* 4036 */ + IC_EVEX_L2_XD_K, /* 4037 */ + IC_EVEX_L2_XD_K, /* 4038 */ + IC_EVEX_L2_XD_K, /* 4039 */ + IC_EVEX_L2_W_K, /* 4040 */ + IC_EVEX_L2_W_K, /* 4041 */ + IC_EVEX_L2_W_XS_K, /* 4042 */ + IC_EVEX_L2_W_XS_K, /* 4043 */ + IC_EVEX_L2_W_XD_K, /* 4044 */ + IC_EVEX_L2_W_XD_K, /* 4045 */ + IC_EVEX_L2_W_XD_K, /* 4046 */ + IC_EVEX_L2_W_XD_K, /* 4047 */ + IC_EVEX_L2_OPSIZE_K, /* 4048 */ + IC_EVEX_L2_OPSIZE_K, /* 4049 */ + IC_EVEX_L2_OPSIZE_K, /* 4050 */ + IC_EVEX_L2_OPSIZE_K, /* 4051 */ + IC_EVEX_L2_OPSIZE_K, /* 4052 */ + IC_EVEX_L2_OPSIZE_K, /* 4053 */ + IC_EVEX_L2_OPSIZE_K, /* 4054 */ + IC_EVEX_L2_OPSIZE_K, /* 4055 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4056 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4057 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4058 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4059 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4060 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4061 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4062 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4063 */ + IC_EVEX_L2_K, /* 4064 */ + IC_EVEX_L2_K, /* 4065 */ + IC_EVEX_L2_XS_K, /* 4066 */ + IC_EVEX_L2_XS_K, /* 4067 */ + IC_EVEX_L2_XD_K, /* 4068 */ + IC_EVEX_L2_XD_K, /* 4069 */ + IC_EVEX_L2_XD_K, /* 4070 */ + IC_EVEX_L2_XD_K, /* 4071 */ + IC_EVEX_L2_W_K, /* 4072 */ + IC_EVEX_L2_W_K, /* 4073 */ + IC_EVEX_L2_W_XS_K, /* 4074 */ + IC_EVEX_L2_W_XS_K, /* 4075 */ + IC_EVEX_L2_W_XD_K, /* 4076 */ + IC_EVEX_L2_W_XD_K, /* 4077 */ + IC_EVEX_L2_W_XD_K, /* 4078 */ + IC_EVEX_L2_W_XD_K, /* 4079 */ + IC_EVEX_L2_OPSIZE_K, /* 4080 */ + IC_EVEX_L2_OPSIZE_K, /* 4081 */ + IC_EVEX_L2_OPSIZE_K, /* 4082 */ + IC_EVEX_L2_OPSIZE_K, /* 4083 */ + IC_EVEX_L2_OPSIZE_K, /* 4084 */ + IC_EVEX_L2_OPSIZE_K, /* 4085 */ + IC_EVEX_L2_OPSIZE_K, /* 4086 */ + IC_EVEX_L2_OPSIZE_K, /* 4087 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4088 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4089 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4090 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4091 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4092 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4093 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4094 */ + IC_EVEX_L2_W_OPSIZE_K, /* 4095 */ + IC, /* 4096 */ + IC_64BIT, /* 4097 */ + IC_XS, /* 4098 */ + IC_64BIT_XS, /* 4099 */ + IC_XD, /* 4100 */ + IC_64BIT_XD, /* 4101 */ + IC_XS, /* 4102 */ + IC_64BIT_XS, /* 4103 */ + IC, /* 4104 */ + IC_64BIT_REXW, /* 4105 */ + IC_XS, /* 4106 */ + IC_64BIT_REXW_XS, /* 4107 */ + IC_XD, /* 4108 */ + IC_64BIT_REXW_XD, /* 4109 */ + IC_XS, /* 4110 */ + IC_64BIT_REXW_XS, /* 4111 */ + IC_OPSIZE, /* 4112 */ + IC_64BIT_OPSIZE, /* 4113 */ + IC_XS_OPSIZE, /* 4114 */ + IC_64BIT_XS_OPSIZE, /* 4115 */ + IC_XD_OPSIZE, /* 4116 */ + IC_64BIT_XD_OPSIZE, /* 4117 */ + IC_XS_OPSIZE, /* 4118 */ + IC_64BIT_XD_OPSIZE, /* 4119 */ + IC_OPSIZE, /* 4120 */ + IC_64BIT_REXW_OPSIZE, /* 4121 */ + IC_XS_OPSIZE, /* 4122 */ + IC_64BIT_REXW_XS, /* 4123 */ + IC_XD_OPSIZE, /* 4124 */ + IC_64BIT_REXW_XD, /* 4125 */ + IC_XS_OPSIZE, /* 4126 */ + IC_64BIT_REXW_XS, /* 4127 */ + IC_ADSIZE, /* 4128 */ + IC_64BIT_ADSIZE, /* 4129 */ + IC_XS_ADSIZE, /* 4130 */ + IC_64BIT_XS_ADSIZE, /* 4131 */ + IC_XD_ADSIZE, /* 4132 */ + IC_64BIT_XD_ADSIZE, /* 4133 */ + IC_XS_ADSIZE, /* 4134 */ + IC_64BIT_XD_ADSIZE, /* 4135 */ + IC_ADSIZE, /* 4136 */ + IC_64BIT_REXW_ADSIZE, /* 4137 */ + IC_XS_ADSIZE, /* 4138 */ + IC_64BIT_REXW_XS, /* 4139 */ + IC_XD_ADSIZE, /* 4140 */ + IC_64BIT_REXW_XD, /* 4141 */ + IC_XS_ADSIZE, /* 4142 */ + IC_64BIT_REXW_XS, /* 4143 */ + IC_OPSIZE_ADSIZE, /* 4144 */ + IC_64BIT_OPSIZE_ADSIZE, /* 4145 */ + IC_XS_OPSIZE, /* 4146 */ + IC_64BIT_XS_OPSIZE, /* 4147 */ + IC_XD_OPSIZE, /* 4148 */ + IC_64BIT_XD_OPSIZE, /* 4149 */ + IC_XS_OPSIZE, /* 4150 */ + IC_64BIT_XD_OPSIZE, /* 4151 */ + IC_OPSIZE_ADSIZE, /* 4152 */ + IC_64BIT_REXW_OPSIZE, /* 4153 */ + IC_XS_OPSIZE, /* 4154 */ + IC_64BIT_REXW_XS, /* 4155 */ + IC_XD_OPSIZE, /* 4156 */ + IC_64BIT_REXW_XD, /* 4157 */ + IC_XS_OPSIZE, /* 4158 */ + IC_64BIT_REXW_XS, /* 4159 */ + IC_VEX, /* 4160 */ + IC_VEX, /* 4161 */ + IC_VEX_XS, /* 4162 */ + IC_VEX_XS, /* 4163 */ + IC_VEX_XD, /* 4164 */ + IC_VEX_XD, /* 4165 */ + IC_VEX_XD, /* 4166 */ + IC_VEX_XD, /* 4167 */ + IC_VEX_W, /* 4168 */ + IC_VEX_W, /* 4169 */ + IC_VEX_W_XS, /* 4170 */ + IC_VEX_W_XS, /* 4171 */ + IC_VEX_W_XD, /* 4172 */ + IC_VEX_W_XD, /* 4173 */ + IC_VEX_W_XD, /* 4174 */ + IC_VEX_W_XD, /* 4175 */ + IC_VEX_OPSIZE, /* 4176 */ + IC_VEX_OPSIZE, /* 4177 */ + IC_VEX_OPSIZE, /* 4178 */ + IC_VEX_OPSIZE, /* 4179 */ + IC_VEX_OPSIZE, /* 4180 */ + IC_VEX_OPSIZE, /* 4181 */ + IC_VEX_OPSIZE, /* 4182 */ + IC_VEX_OPSIZE, /* 4183 */ + IC_VEX_W_OPSIZE, /* 4184 */ + IC_VEX_W_OPSIZE, /* 4185 */ + IC_VEX_W_OPSIZE, /* 4186 */ + IC_VEX_W_OPSIZE, /* 4187 */ + IC_VEX_W_OPSIZE, /* 4188 */ + IC_VEX_W_OPSIZE, /* 4189 */ + IC_VEX_W_OPSIZE, /* 4190 */ + IC_VEX_W_OPSIZE, /* 4191 */ + IC_VEX, /* 4192 */ + IC_VEX, /* 4193 */ + IC_VEX_XS, /* 4194 */ + IC_VEX_XS, /* 4195 */ + IC_VEX_XD, /* 4196 */ + IC_VEX_XD, /* 4197 */ + IC_VEX_XD, /* 4198 */ + IC_VEX_XD, /* 4199 */ + IC_VEX_W, /* 4200 */ + IC_VEX_W, /* 4201 */ + IC_VEX_W_XS, /* 4202 */ + IC_VEX_W_XS, /* 4203 */ + IC_VEX_W_XD, /* 4204 */ + IC_VEX_W_XD, /* 4205 */ + IC_VEX_W_XD, /* 4206 */ + IC_VEX_W_XD, /* 4207 */ + IC_VEX_OPSIZE, /* 4208 */ + IC_VEX_OPSIZE, /* 4209 */ + IC_VEX_OPSIZE, /* 4210 */ + IC_VEX_OPSIZE, /* 4211 */ + IC_VEX_OPSIZE, /* 4212 */ + IC_VEX_OPSIZE, /* 4213 */ + IC_VEX_OPSIZE, /* 4214 */ + IC_VEX_OPSIZE, /* 4215 */ + IC_VEX_W_OPSIZE, /* 4216 */ + IC_VEX_W_OPSIZE, /* 4217 */ + IC_VEX_W_OPSIZE, /* 4218 */ + IC_VEX_W_OPSIZE, /* 4219 */ + IC_VEX_W_OPSIZE, /* 4220 */ + IC_VEX_W_OPSIZE, /* 4221 */ + IC_VEX_W_OPSIZE, /* 4222 */ + IC_VEX_W_OPSIZE, /* 4223 */ + IC_VEX_L, /* 4224 */ + IC_VEX_L, /* 4225 */ + IC_VEX_L_XS, /* 4226 */ + IC_VEX_L_XS, /* 4227 */ + IC_VEX_L_XD, /* 4228 */ + IC_VEX_L_XD, /* 4229 */ + IC_VEX_L_XD, /* 4230 */ + IC_VEX_L_XD, /* 4231 */ + IC_VEX_L_W, /* 4232 */ + IC_VEX_L_W, /* 4233 */ + IC_VEX_L_W_XS, /* 4234 */ + IC_VEX_L_W_XS, /* 4235 */ + IC_VEX_L_W_XD, /* 4236 */ + IC_VEX_L_W_XD, /* 4237 */ + IC_VEX_L_W_XD, /* 4238 */ + IC_VEX_L_W_XD, /* 4239 */ + IC_VEX_L_OPSIZE, /* 4240 */ + IC_VEX_L_OPSIZE, /* 4241 */ + IC_VEX_L_OPSIZE, /* 4242 */ + IC_VEX_L_OPSIZE, /* 4243 */ + IC_VEX_L_OPSIZE, /* 4244 */ + IC_VEX_L_OPSIZE, /* 4245 */ + IC_VEX_L_OPSIZE, /* 4246 */ + IC_VEX_L_OPSIZE, /* 4247 */ + IC_VEX_L_W_OPSIZE, /* 4248 */ + IC_VEX_L_W_OPSIZE, /* 4249 */ + IC_VEX_L_W_OPSIZE, /* 4250 */ + IC_VEX_L_W_OPSIZE, /* 4251 */ + IC_VEX_L_W_OPSIZE, /* 4252 */ + IC_VEX_L_W_OPSIZE, /* 4253 */ + IC_VEX_L_W_OPSIZE, /* 4254 */ + IC_VEX_L_W_OPSIZE, /* 4255 */ + IC_VEX_L, /* 4256 */ + IC_VEX_L, /* 4257 */ + IC_VEX_L_XS, /* 4258 */ + IC_VEX_L_XS, /* 4259 */ + IC_VEX_L_XD, /* 4260 */ + IC_VEX_L_XD, /* 4261 */ + IC_VEX_L_XD, /* 4262 */ + IC_VEX_L_XD, /* 4263 */ + IC_VEX_L_W, /* 4264 */ + IC_VEX_L_W, /* 4265 */ + IC_VEX_L_W_XS, /* 4266 */ + IC_VEX_L_W_XS, /* 4267 */ + IC_VEX_L_W_XD, /* 4268 */ + IC_VEX_L_W_XD, /* 4269 */ + IC_VEX_L_W_XD, /* 4270 */ + IC_VEX_L_W_XD, /* 4271 */ + IC_VEX_L_OPSIZE, /* 4272 */ + IC_VEX_L_OPSIZE, /* 4273 */ + IC_VEX_L_OPSIZE, /* 4274 */ + IC_VEX_L_OPSIZE, /* 4275 */ + IC_VEX_L_OPSIZE, /* 4276 */ + IC_VEX_L_OPSIZE, /* 4277 */ + IC_VEX_L_OPSIZE, /* 4278 */ + IC_VEX_L_OPSIZE, /* 4279 */ + IC_VEX_L_W_OPSIZE, /* 4280 */ + IC_VEX_L_W_OPSIZE, /* 4281 */ + IC_VEX_L_W_OPSIZE, /* 4282 */ + IC_VEX_L_W_OPSIZE, /* 4283 */ + IC_VEX_L_W_OPSIZE, /* 4284 */ + IC_VEX_L_W_OPSIZE, /* 4285 */ + IC_VEX_L_W_OPSIZE, /* 4286 */ + IC_VEX_L_W_OPSIZE, /* 4287 */ + IC_VEX_L, /* 4288 */ + IC_VEX_L, /* 4289 */ + IC_VEX_L_XS, /* 4290 */ + IC_VEX_L_XS, /* 4291 */ + IC_VEX_L_XD, /* 4292 */ + IC_VEX_L_XD, /* 4293 */ + IC_VEX_L_XD, /* 4294 */ + IC_VEX_L_XD, /* 4295 */ + IC_VEX_L_W, /* 4296 */ + IC_VEX_L_W, /* 4297 */ + IC_VEX_L_W_XS, /* 4298 */ + IC_VEX_L_W_XS, /* 4299 */ + IC_VEX_L_W_XD, /* 4300 */ + IC_VEX_L_W_XD, /* 4301 */ + IC_VEX_L_W_XD, /* 4302 */ + IC_VEX_L_W_XD, /* 4303 */ + IC_VEX_L_OPSIZE, /* 4304 */ + IC_VEX_L_OPSIZE, /* 4305 */ + IC_VEX_L_OPSIZE, /* 4306 */ + IC_VEX_L_OPSIZE, /* 4307 */ + IC_VEX_L_OPSIZE, /* 4308 */ + IC_VEX_L_OPSIZE, /* 4309 */ + IC_VEX_L_OPSIZE, /* 4310 */ + IC_VEX_L_OPSIZE, /* 4311 */ + IC_VEX_L_W_OPSIZE, /* 4312 */ + IC_VEX_L_W_OPSIZE, /* 4313 */ + IC_VEX_L_W_OPSIZE, /* 4314 */ + IC_VEX_L_W_OPSIZE, /* 4315 */ + IC_VEX_L_W_OPSIZE, /* 4316 */ + IC_VEX_L_W_OPSIZE, /* 4317 */ + IC_VEX_L_W_OPSIZE, /* 4318 */ + IC_VEX_L_W_OPSIZE, /* 4319 */ + IC_VEX_L, /* 4320 */ + IC_VEX_L, /* 4321 */ + IC_VEX_L_XS, /* 4322 */ + IC_VEX_L_XS, /* 4323 */ + IC_VEX_L_XD, /* 4324 */ + IC_VEX_L_XD, /* 4325 */ + IC_VEX_L_XD, /* 4326 */ + IC_VEX_L_XD, /* 4327 */ + IC_VEX_L_W, /* 4328 */ + IC_VEX_L_W, /* 4329 */ + IC_VEX_L_W_XS, /* 4330 */ + IC_VEX_L_W_XS, /* 4331 */ + IC_VEX_L_W_XD, /* 4332 */ + IC_VEX_L_W_XD, /* 4333 */ + IC_VEX_L_W_XD, /* 4334 */ + IC_VEX_L_W_XD, /* 4335 */ + IC_VEX_L_OPSIZE, /* 4336 */ + IC_VEX_L_OPSIZE, /* 4337 */ + IC_VEX_L_OPSIZE, /* 4338 */ + IC_VEX_L_OPSIZE, /* 4339 */ + IC_VEX_L_OPSIZE, /* 4340 */ + IC_VEX_L_OPSIZE, /* 4341 */ + IC_VEX_L_OPSIZE, /* 4342 */ + IC_VEX_L_OPSIZE, /* 4343 */ + IC_VEX_L_W_OPSIZE, /* 4344 */ + IC_VEX_L_W_OPSIZE, /* 4345 */ + IC_VEX_L_W_OPSIZE, /* 4346 */ + IC_VEX_L_W_OPSIZE, /* 4347 */ + IC_VEX_L_W_OPSIZE, /* 4348 */ + IC_VEX_L_W_OPSIZE, /* 4349 */ + IC_VEX_L_W_OPSIZE, /* 4350 */ + IC_VEX_L_W_OPSIZE, /* 4351 */ + IC_EVEX_KZ, /* 4352 */ + IC_EVEX_KZ, /* 4353 */ + IC_EVEX_XS_KZ, /* 4354 */ + IC_EVEX_XS_KZ, /* 4355 */ + IC_EVEX_XD_KZ, /* 4356 */ + IC_EVEX_XD_KZ, /* 4357 */ + IC_EVEX_XD_KZ, /* 4358 */ + IC_EVEX_XD_KZ, /* 4359 */ + IC_EVEX_W_KZ, /* 4360 */ + IC_EVEX_W_KZ, /* 4361 */ + IC_EVEX_W_XS_KZ, /* 4362 */ + IC_EVEX_W_XS_KZ, /* 4363 */ + IC_EVEX_W_XD_KZ, /* 4364 */ + IC_EVEX_W_XD_KZ, /* 4365 */ + IC_EVEX_W_XD_KZ, /* 4366 */ + IC_EVEX_W_XD_KZ, /* 4367 */ + IC_EVEX_OPSIZE_KZ, /* 4368 */ + IC_EVEX_OPSIZE_KZ, /* 4369 */ + IC_EVEX_OPSIZE_KZ, /* 4370 */ + IC_EVEX_OPSIZE_KZ, /* 4371 */ + IC_EVEX_OPSIZE_KZ, /* 4372 */ + IC_EVEX_OPSIZE_KZ, /* 4373 */ + IC_EVEX_OPSIZE_KZ, /* 4374 */ + IC_EVEX_OPSIZE_KZ, /* 4375 */ + IC_EVEX_W_OPSIZE_KZ, /* 4376 */ + IC_EVEX_W_OPSIZE_KZ, /* 4377 */ + IC_EVEX_W_OPSIZE_KZ, /* 4378 */ + IC_EVEX_W_OPSIZE_KZ, /* 4379 */ + IC_EVEX_W_OPSIZE_KZ, /* 4380 */ + IC_EVEX_W_OPSIZE_KZ, /* 4381 */ + IC_EVEX_W_OPSIZE_KZ, /* 4382 */ + IC_EVEX_W_OPSIZE_KZ, /* 4383 */ + IC_EVEX_KZ, /* 4384 */ + IC_EVEX_KZ, /* 4385 */ + IC_EVEX_XS_KZ, /* 4386 */ + IC_EVEX_XS_KZ, /* 4387 */ + IC_EVEX_XD_KZ, /* 4388 */ + IC_EVEX_XD_KZ, /* 4389 */ + IC_EVEX_XD_KZ, /* 4390 */ + IC_EVEX_XD_KZ, /* 4391 */ + IC_EVEX_W_KZ, /* 4392 */ + IC_EVEX_W_KZ, /* 4393 */ + IC_EVEX_W_XS_KZ, /* 4394 */ + IC_EVEX_W_XS_KZ, /* 4395 */ + IC_EVEX_W_XD_KZ, /* 4396 */ + IC_EVEX_W_XD_KZ, /* 4397 */ + IC_EVEX_W_XD_KZ, /* 4398 */ + IC_EVEX_W_XD_KZ, /* 4399 */ + IC_EVEX_OPSIZE_KZ, /* 4400 */ + IC_EVEX_OPSIZE_KZ, /* 4401 */ + IC_EVEX_OPSIZE_KZ, /* 4402 */ + IC_EVEX_OPSIZE_KZ, /* 4403 */ + IC_EVEX_OPSIZE_KZ, /* 4404 */ + IC_EVEX_OPSIZE_KZ, /* 4405 */ + IC_EVEX_OPSIZE_KZ, /* 4406 */ + IC_EVEX_OPSIZE_KZ, /* 4407 */ + IC_EVEX_W_OPSIZE_KZ, /* 4408 */ + IC_EVEX_W_OPSIZE_KZ, /* 4409 */ + IC_EVEX_W_OPSIZE_KZ, /* 4410 */ + IC_EVEX_W_OPSIZE_KZ, /* 4411 */ + IC_EVEX_W_OPSIZE_KZ, /* 4412 */ + IC_EVEX_W_OPSIZE_KZ, /* 4413 */ + IC_EVEX_W_OPSIZE_KZ, /* 4414 */ + IC_EVEX_W_OPSIZE_KZ, /* 4415 */ + IC_EVEX_KZ, /* 4416 */ + IC_EVEX_KZ, /* 4417 */ + IC_EVEX_XS_KZ, /* 4418 */ + IC_EVEX_XS_KZ, /* 4419 */ + IC_EVEX_XD_KZ, /* 4420 */ + IC_EVEX_XD_KZ, /* 4421 */ + IC_EVEX_XD_KZ, /* 4422 */ + IC_EVEX_XD_KZ, /* 4423 */ + IC_EVEX_W_KZ, /* 4424 */ + IC_EVEX_W_KZ, /* 4425 */ + IC_EVEX_W_XS_KZ, /* 4426 */ + IC_EVEX_W_XS_KZ, /* 4427 */ + IC_EVEX_W_XD_KZ, /* 4428 */ + IC_EVEX_W_XD_KZ, /* 4429 */ + IC_EVEX_W_XD_KZ, /* 4430 */ + IC_EVEX_W_XD_KZ, /* 4431 */ + IC_EVEX_OPSIZE_KZ, /* 4432 */ + IC_EVEX_OPSIZE_KZ, /* 4433 */ + IC_EVEX_OPSIZE_KZ, /* 4434 */ + IC_EVEX_OPSIZE_KZ, /* 4435 */ + IC_EVEX_OPSIZE_KZ, /* 4436 */ + IC_EVEX_OPSIZE_KZ, /* 4437 */ + IC_EVEX_OPSIZE_KZ, /* 4438 */ + IC_EVEX_OPSIZE_KZ, /* 4439 */ + IC_EVEX_W_OPSIZE_KZ, /* 4440 */ + IC_EVEX_W_OPSIZE_KZ, /* 4441 */ + IC_EVEX_W_OPSIZE_KZ, /* 4442 */ + IC_EVEX_W_OPSIZE_KZ, /* 4443 */ + IC_EVEX_W_OPSIZE_KZ, /* 4444 */ + IC_EVEX_W_OPSIZE_KZ, /* 4445 */ + IC_EVEX_W_OPSIZE_KZ, /* 4446 */ + IC_EVEX_W_OPSIZE_KZ, /* 4447 */ + IC_EVEX_KZ, /* 4448 */ + IC_EVEX_KZ, /* 4449 */ + IC_EVEX_XS_KZ, /* 4450 */ + IC_EVEX_XS_KZ, /* 4451 */ + IC_EVEX_XD_KZ, /* 4452 */ + IC_EVEX_XD_KZ, /* 4453 */ + IC_EVEX_XD_KZ, /* 4454 */ + IC_EVEX_XD_KZ, /* 4455 */ + IC_EVEX_W_KZ, /* 4456 */ + IC_EVEX_W_KZ, /* 4457 */ + IC_EVEX_W_XS_KZ, /* 4458 */ + IC_EVEX_W_XS_KZ, /* 4459 */ + IC_EVEX_W_XD_KZ, /* 4460 */ + IC_EVEX_W_XD_KZ, /* 4461 */ + IC_EVEX_W_XD_KZ, /* 4462 */ + IC_EVEX_W_XD_KZ, /* 4463 */ + IC_EVEX_OPSIZE_KZ, /* 4464 */ + IC_EVEX_OPSIZE_KZ, /* 4465 */ + IC_EVEX_OPSIZE_KZ, /* 4466 */ + IC_EVEX_OPSIZE_KZ, /* 4467 */ + IC_EVEX_OPSIZE_KZ, /* 4468 */ + IC_EVEX_OPSIZE_KZ, /* 4469 */ + IC_EVEX_OPSIZE_KZ, /* 4470 */ + IC_EVEX_OPSIZE_KZ, /* 4471 */ + IC_EVEX_W_OPSIZE_KZ, /* 4472 */ + IC_EVEX_W_OPSIZE_KZ, /* 4473 */ + IC_EVEX_W_OPSIZE_KZ, /* 4474 */ + IC_EVEX_W_OPSIZE_KZ, /* 4475 */ + IC_EVEX_W_OPSIZE_KZ, /* 4476 */ + IC_EVEX_W_OPSIZE_KZ, /* 4477 */ + IC_EVEX_W_OPSIZE_KZ, /* 4478 */ + IC_EVEX_W_OPSIZE_KZ, /* 4479 */ + IC_EVEX_KZ, /* 4480 */ + IC_EVEX_KZ, /* 4481 */ + IC_EVEX_XS_KZ, /* 4482 */ + IC_EVEX_XS_KZ, /* 4483 */ + IC_EVEX_XD_KZ, /* 4484 */ + IC_EVEX_XD_KZ, /* 4485 */ + IC_EVEX_XD_KZ, /* 4486 */ + IC_EVEX_XD_KZ, /* 4487 */ + IC_EVEX_W_KZ, /* 4488 */ + IC_EVEX_W_KZ, /* 4489 */ + IC_EVEX_W_XS_KZ, /* 4490 */ + IC_EVEX_W_XS_KZ, /* 4491 */ + IC_EVEX_W_XD_KZ, /* 4492 */ + IC_EVEX_W_XD_KZ, /* 4493 */ + IC_EVEX_W_XD_KZ, /* 4494 */ + IC_EVEX_W_XD_KZ, /* 4495 */ + IC_EVEX_OPSIZE_KZ, /* 4496 */ + IC_EVEX_OPSIZE_KZ, /* 4497 */ + IC_EVEX_OPSIZE_KZ, /* 4498 */ + IC_EVEX_OPSIZE_KZ, /* 4499 */ + IC_EVEX_OPSIZE_KZ, /* 4500 */ + IC_EVEX_OPSIZE_KZ, /* 4501 */ + IC_EVEX_OPSIZE_KZ, /* 4502 */ + IC_EVEX_OPSIZE_KZ, /* 4503 */ + IC_EVEX_W_OPSIZE_KZ, /* 4504 */ + IC_EVEX_W_OPSIZE_KZ, /* 4505 */ + IC_EVEX_W_OPSIZE_KZ, /* 4506 */ + IC_EVEX_W_OPSIZE_KZ, /* 4507 */ + IC_EVEX_W_OPSIZE_KZ, /* 4508 */ + IC_EVEX_W_OPSIZE_KZ, /* 4509 */ + IC_EVEX_W_OPSIZE_KZ, /* 4510 */ + IC_EVEX_W_OPSIZE_KZ, /* 4511 */ + IC_EVEX_KZ, /* 4512 */ + IC_EVEX_KZ, /* 4513 */ + IC_EVEX_XS_KZ, /* 4514 */ + IC_EVEX_XS_KZ, /* 4515 */ + IC_EVEX_XD_KZ, /* 4516 */ + IC_EVEX_XD_KZ, /* 4517 */ + IC_EVEX_XD_KZ, /* 4518 */ + IC_EVEX_XD_KZ, /* 4519 */ + IC_EVEX_W_KZ, /* 4520 */ + IC_EVEX_W_KZ, /* 4521 */ + IC_EVEX_W_XS_KZ, /* 4522 */ + IC_EVEX_W_XS_KZ, /* 4523 */ + IC_EVEX_W_XD_KZ, /* 4524 */ + IC_EVEX_W_XD_KZ, /* 4525 */ + IC_EVEX_W_XD_KZ, /* 4526 */ + IC_EVEX_W_XD_KZ, /* 4527 */ + IC_EVEX_OPSIZE_KZ, /* 4528 */ + IC_EVEX_OPSIZE_KZ, /* 4529 */ + IC_EVEX_OPSIZE_KZ, /* 4530 */ + IC_EVEX_OPSIZE_KZ, /* 4531 */ + IC_EVEX_OPSIZE_KZ, /* 4532 */ + IC_EVEX_OPSIZE_KZ, /* 4533 */ + IC_EVEX_OPSIZE_KZ, /* 4534 */ + IC_EVEX_OPSIZE_KZ, /* 4535 */ + IC_EVEX_W_OPSIZE_KZ, /* 4536 */ + IC_EVEX_W_OPSIZE_KZ, /* 4537 */ + IC_EVEX_W_OPSIZE_KZ, /* 4538 */ + IC_EVEX_W_OPSIZE_KZ, /* 4539 */ + IC_EVEX_W_OPSIZE_KZ, /* 4540 */ + IC_EVEX_W_OPSIZE_KZ, /* 4541 */ + IC_EVEX_W_OPSIZE_KZ, /* 4542 */ + IC_EVEX_W_OPSIZE_KZ, /* 4543 */ + IC_EVEX_KZ, /* 4544 */ + IC_EVEX_KZ, /* 4545 */ + IC_EVEX_XS_KZ, /* 4546 */ + IC_EVEX_XS_KZ, /* 4547 */ + IC_EVEX_XD_KZ, /* 4548 */ + IC_EVEX_XD_KZ, /* 4549 */ + IC_EVEX_XD_KZ, /* 4550 */ + IC_EVEX_XD_KZ, /* 4551 */ + IC_EVEX_W_KZ, /* 4552 */ + IC_EVEX_W_KZ, /* 4553 */ + IC_EVEX_W_XS_KZ, /* 4554 */ + IC_EVEX_W_XS_KZ, /* 4555 */ + IC_EVEX_W_XD_KZ, /* 4556 */ + IC_EVEX_W_XD_KZ, /* 4557 */ + IC_EVEX_W_XD_KZ, /* 4558 */ + IC_EVEX_W_XD_KZ, /* 4559 */ + IC_EVEX_OPSIZE_KZ, /* 4560 */ + IC_EVEX_OPSIZE_KZ, /* 4561 */ + IC_EVEX_OPSIZE_KZ, /* 4562 */ + IC_EVEX_OPSIZE_KZ, /* 4563 */ + IC_EVEX_OPSIZE_KZ, /* 4564 */ + IC_EVEX_OPSIZE_KZ, /* 4565 */ + IC_EVEX_OPSIZE_KZ, /* 4566 */ + IC_EVEX_OPSIZE_KZ, /* 4567 */ + IC_EVEX_W_OPSIZE_KZ, /* 4568 */ + IC_EVEX_W_OPSIZE_KZ, /* 4569 */ + IC_EVEX_W_OPSIZE_KZ, /* 4570 */ + IC_EVEX_W_OPSIZE_KZ, /* 4571 */ + IC_EVEX_W_OPSIZE_KZ, /* 4572 */ + IC_EVEX_W_OPSIZE_KZ, /* 4573 */ + IC_EVEX_W_OPSIZE_KZ, /* 4574 */ + IC_EVEX_W_OPSIZE_KZ, /* 4575 */ + IC_EVEX_KZ, /* 4576 */ + IC_EVEX_KZ, /* 4577 */ + IC_EVEX_XS_KZ, /* 4578 */ + IC_EVEX_XS_KZ, /* 4579 */ + IC_EVEX_XD_KZ, /* 4580 */ + IC_EVEX_XD_KZ, /* 4581 */ + IC_EVEX_XD_KZ, /* 4582 */ + IC_EVEX_XD_KZ, /* 4583 */ + IC_EVEX_W_KZ, /* 4584 */ + IC_EVEX_W_KZ, /* 4585 */ + IC_EVEX_W_XS_KZ, /* 4586 */ + IC_EVEX_W_XS_KZ, /* 4587 */ + IC_EVEX_W_XD_KZ, /* 4588 */ + IC_EVEX_W_XD_KZ, /* 4589 */ + IC_EVEX_W_XD_KZ, /* 4590 */ + IC_EVEX_W_XD_KZ, /* 4591 */ + IC_EVEX_OPSIZE_KZ, /* 4592 */ + IC_EVEX_OPSIZE_KZ, /* 4593 */ + IC_EVEX_OPSIZE_KZ, /* 4594 */ + IC_EVEX_OPSIZE_KZ, /* 4595 */ + IC_EVEX_OPSIZE_KZ, /* 4596 */ + IC_EVEX_OPSIZE_KZ, /* 4597 */ + IC_EVEX_OPSIZE_KZ, /* 4598 */ + IC_EVEX_OPSIZE_KZ, /* 4599 */ + IC_EVEX_W_OPSIZE_KZ, /* 4600 */ + IC_EVEX_W_OPSIZE_KZ, /* 4601 */ + IC_EVEX_W_OPSIZE_KZ, /* 4602 */ + IC_EVEX_W_OPSIZE_KZ, /* 4603 */ + IC_EVEX_W_OPSIZE_KZ, /* 4604 */ + IC_EVEX_W_OPSIZE_KZ, /* 4605 */ + IC_EVEX_W_OPSIZE_KZ, /* 4606 */ + IC_EVEX_W_OPSIZE_KZ, /* 4607 */ + IC, /* 4608 */ + IC_64BIT, /* 4609 */ + IC_XS, /* 4610 */ + IC_64BIT_XS, /* 4611 */ + IC_XD, /* 4612 */ + IC_64BIT_XD, /* 4613 */ + IC_XS, /* 4614 */ + IC_64BIT_XS, /* 4615 */ + IC, /* 4616 */ + IC_64BIT_REXW, /* 4617 */ + IC_XS, /* 4618 */ + IC_64BIT_REXW_XS, /* 4619 */ + IC_XD, /* 4620 */ + IC_64BIT_REXW_XD, /* 4621 */ + IC_XS, /* 4622 */ + IC_64BIT_REXW_XS, /* 4623 */ + IC_OPSIZE, /* 4624 */ + IC_64BIT_OPSIZE, /* 4625 */ + IC_XS_OPSIZE, /* 4626 */ + IC_64BIT_XS_OPSIZE, /* 4627 */ + IC_XD_OPSIZE, /* 4628 */ + IC_64BIT_XD_OPSIZE, /* 4629 */ + IC_XS_OPSIZE, /* 4630 */ + IC_64BIT_XD_OPSIZE, /* 4631 */ + IC_OPSIZE, /* 4632 */ + IC_64BIT_REXW_OPSIZE, /* 4633 */ + IC_XS_OPSIZE, /* 4634 */ + IC_64BIT_REXW_XS, /* 4635 */ + IC_XD_OPSIZE, /* 4636 */ + IC_64BIT_REXW_XD, /* 4637 */ + IC_XS_OPSIZE, /* 4638 */ + IC_64BIT_REXW_XS, /* 4639 */ + IC_ADSIZE, /* 4640 */ + IC_64BIT_ADSIZE, /* 4641 */ + IC_XS_ADSIZE, /* 4642 */ + IC_64BIT_XS_ADSIZE, /* 4643 */ + IC_XD_ADSIZE, /* 4644 */ + IC_64BIT_XD_ADSIZE, /* 4645 */ + IC_XS_ADSIZE, /* 4646 */ + IC_64BIT_XD_ADSIZE, /* 4647 */ + IC_ADSIZE, /* 4648 */ + IC_64BIT_REXW_ADSIZE, /* 4649 */ + IC_XS_ADSIZE, /* 4650 */ + IC_64BIT_REXW_XS, /* 4651 */ + IC_XD_ADSIZE, /* 4652 */ + IC_64BIT_REXW_XD, /* 4653 */ + IC_XS_ADSIZE, /* 4654 */ + IC_64BIT_REXW_XS, /* 4655 */ + IC_OPSIZE_ADSIZE, /* 4656 */ + IC_64BIT_OPSIZE_ADSIZE, /* 4657 */ + IC_XS_OPSIZE, /* 4658 */ + IC_64BIT_XS_OPSIZE, /* 4659 */ + IC_XD_OPSIZE, /* 4660 */ + IC_64BIT_XD_OPSIZE, /* 4661 */ + IC_XS_OPSIZE, /* 4662 */ + IC_64BIT_XD_OPSIZE, /* 4663 */ + IC_OPSIZE_ADSIZE, /* 4664 */ + IC_64BIT_REXW_OPSIZE, /* 4665 */ + IC_XS_OPSIZE, /* 4666 */ + IC_64BIT_REXW_XS, /* 4667 */ + IC_XD_OPSIZE, /* 4668 */ + IC_64BIT_REXW_XD, /* 4669 */ + IC_XS_OPSIZE, /* 4670 */ + IC_64BIT_REXW_XS, /* 4671 */ + IC_VEX, /* 4672 */ + IC_VEX, /* 4673 */ + IC_VEX_XS, /* 4674 */ + IC_VEX_XS, /* 4675 */ + IC_VEX_XD, /* 4676 */ + IC_VEX_XD, /* 4677 */ + IC_VEX_XD, /* 4678 */ + IC_VEX_XD, /* 4679 */ + IC_VEX_W, /* 4680 */ + IC_VEX_W, /* 4681 */ + IC_VEX_W_XS, /* 4682 */ + IC_VEX_W_XS, /* 4683 */ + IC_VEX_W_XD, /* 4684 */ + IC_VEX_W_XD, /* 4685 */ + IC_VEX_W_XD, /* 4686 */ + IC_VEX_W_XD, /* 4687 */ + IC_VEX_OPSIZE, /* 4688 */ + IC_VEX_OPSIZE, /* 4689 */ + IC_VEX_OPSIZE, /* 4690 */ + IC_VEX_OPSIZE, /* 4691 */ + IC_VEX_OPSIZE, /* 4692 */ + IC_VEX_OPSIZE, /* 4693 */ + IC_VEX_OPSIZE, /* 4694 */ + IC_VEX_OPSIZE, /* 4695 */ + IC_VEX_W_OPSIZE, /* 4696 */ + IC_VEX_W_OPSIZE, /* 4697 */ + IC_VEX_W_OPSIZE, /* 4698 */ + IC_VEX_W_OPSIZE, /* 4699 */ + IC_VEX_W_OPSIZE, /* 4700 */ + IC_VEX_W_OPSIZE, /* 4701 */ + IC_VEX_W_OPSIZE, /* 4702 */ + IC_VEX_W_OPSIZE, /* 4703 */ + IC_VEX, /* 4704 */ + IC_VEX, /* 4705 */ + IC_VEX_XS, /* 4706 */ + IC_VEX_XS, /* 4707 */ + IC_VEX_XD, /* 4708 */ + IC_VEX_XD, /* 4709 */ + IC_VEX_XD, /* 4710 */ + IC_VEX_XD, /* 4711 */ + IC_VEX_W, /* 4712 */ + IC_VEX_W, /* 4713 */ + IC_VEX_W_XS, /* 4714 */ + IC_VEX_W_XS, /* 4715 */ + IC_VEX_W_XD, /* 4716 */ + IC_VEX_W_XD, /* 4717 */ + IC_VEX_W_XD, /* 4718 */ + IC_VEX_W_XD, /* 4719 */ + IC_VEX_OPSIZE, /* 4720 */ + IC_VEX_OPSIZE, /* 4721 */ + IC_VEX_OPSIZE, /* 4722 */ + IC_VEX_OPSIZE, /* 4723 */ + IC_VEX_OPSIZE, /* 4724 */ + IC_VEX_OPSIZE, /* 4725 */ + IC_VEX_OPSIZE, /* 4726 */ + IC_VEX_OPSIZE, /* 4727 */ + IC_VEX_W_OPSIZE, /* 4728 */ + IC_VEX_W_OPSIZE, /* 4729 */ + IC_VEX_W_OPSIZE, /* 4730 */ + IC_VEX_W_OPSIZE, /* 4731 */ + IC_VEX_W_OPSIZE, /* 4732 */ + IC_VEX_W_OPSIZE, /* 4733 */ + IC_VEX_W_OPSIZE, /* 4734 */ + IC_VEX_W_OPSIZE, /* 4735 */ + IC_VEX_L, /* 4736 */ + IC_VEX_L, /* 4737 */ + IC_VEX_L_XS, /* 4738 */ + IC_VEX_L_XS, /* 4739 */ + IC_VEX_L_XD, /* 4740 */ + IC_VEX_L_XD, /* 4741 */ + IC_VEX_L_XD, /* 4742 */ + IC_VEX_L_XD, /* 4743 */ + IC_VEX_L_W, /* 4744 */ + IC_VEX_L_W, /* 4745 */ + IC_VEX_L_W_XS, /* 4746 */ + IC_VEX_L_W_XS, /* 4747 */ + IC_VEX_L_W_XD, /* 4748 */ + IC_VEX_L_W_XD, /* 4749 */ + IC_VEX_L_W_XD, /* 4750 */ + IC_VEX_L_W_XD, /* 4751 */ + IC_VEX_L_OPSIZE, /* 4752 */ + IC_VEX_L_OPSIZE, /* 4753 */ + IC_VEX_L_OPSIZE, /* 4754 */ + IC_VEX_L_OPSIZE, /* 4755 */ + IC_VEX_L_OPSIZE, /* 4756 */ + IC_VEX_L_OPSIZE, /* 4757 */ + IC_VEX_L_OPSIZE, /* 4758 */ + IC_VEX_L_OPSIZE, /* 4759 */ + IC_VEX_L_W_OPSIZE, /* 4760 */ + IC_VEX_L_W_OPSIZE, /* 4761 */ + IC_VEX_L_W_OPSIZE, /* 4762 */ + IC_VEX_L_W_OPSIZE, /* 4763 */ + IC_VEX_L_W_OPSIZE, /* 4764 */ + IC_VEX_L_W_OPSIZE, /* 4765 */ + IC_VEX_L_W_OPSIZE, /* 4766 */ + IC_VEX_L_W_OPSIZE, /* 4767 */ + IC_VEX_L, /* 4768 */ + IC_VEX_L, /* 4769 */ + IC_VEX_L_XS, /* 4770 */ + IC_VEX_L_XS, /* 4771 */ + IC_VEX_L_XD, /* 4772 */ + IC_VEX_L_XD, /* 4773 */ + IC_VEX_L_XD, /* 4774 */ + IC_VEX_L_XD, /* 4775 */ + IC_VEX_L_W, /* 4776 */ + IC_VEX_L_W, /* 4777 */ + IC_VEX_L_W_XS, /* 4778 */ + IC_VEX_L_W_XS, /* 4779 */ + IC_VEX_L_W_XD, /* 4780 */ + IC_VEX_L_W_XD, /* 4781 */ + IC_VEX_L_W_XD, /* 4782 */ + IC_VEX_L_W_XD, /* 4783 */ + IC_VEX_L_OPSIZE, /* 4784 */ + IC_VEX_L_OPSIZE, /* 4785 */ + IC_VEX_L_OPSIZE, /* 4786 */ + IC_VEX_L_OPSIZE, /* 4787 */ + IC_VEX_L_OPSIZE, /* 4788 */ + IC_VEX_L_OPSIZE, /* 4789 */ + IC_VEX_L_OPSIZE, /* 4790 */ + IC_VEX_L_OPSIZE, /* 4791 */ + IC_VEX_L_W_OPSIZE, /* 4792 */ + IC_VEX_L_W_OPSIZE, /* 4793 */ + IC_VEX_L_W_OPSIZE, /* 4794 */ + IC_VEX_L_W_OPSIZE, /* 4795 */ + IC_VEX_L_W_OPSIZE, /* 4796 */ + IC_VEX_L_W_OPSIZE, /* 4797 */ + IC_VEX_L_W_OPSIZE, /* 4798 */ + IC_VEX_L_W_OPSIZE, /* 4799 */ + IC_VEX_L, /* 4800 */ + IC_VEX_L, /* 4801 */ + IC_VEX_L_XS, /* 4802 */ + IC_VEX_L_XS, /* 4803 */ + IC_VEX_L_XD, /* 4804 */ + IC_VEX_L_XD, /* 4805 */ + IC_VEX_L_XD, /* 4806 */ + IC_VEX_L_XD, /* 4807 */ + IC_VEX_L_W, /* 4808 */ + IC_VEX_L_W, /* 4809 */ + IC_VEX_L_W_XS, /* 4810 */ + IC_VEX_L_W_XS, /* 4811 */ + IC_VEX_L_W_XD, /* 4812 */ + IC_VEX_L_W_XD, /* 4813 */ + IC_VEX_L_W_XD, /* 4814 */ + IC_VEX_L_W_XD, /* 4815 */ + IC_VEX_L_OPSIZE, /* 4816 */ + IC_VEX_L_OPSIZE, /* 4817 */ + IC_VEX_L_OPSIZE, /* 4818 */ + IC_VEX_L_OPSIZE, /* 4819 */ + IC_VEX_L_OPSIZE, /* 4820 */ + IC_VEX_L_OPSIZE, /* 4821 */ + IC_VEX_L_OPSIZE, /* 4822 */ + IC_VEX_L_OPSIZE, /* 4823 */ + IC_VEX_L_W_OPSIZE, /* 4824 */ + IC_VEX_L_W_OPSIZE, /* 4825 */ + IC_VEX_L_W_OPSIZE, /* 4826 */ + IC_VEX_L_W_OPSIZE, /* 4827 */ + IC_VEX_L_W_OPSIZE, /* 4828 */ + IC_VEX_L_W_OPSIZE, /* 4829 */ + IC_VEX_L_W_OPSIZE, /* 4830 */ + IC_VEX_L_W_OPSIZE, /* 4831 */ + IC_VEX_L, /* 4832 */ + IC_VEX_L, /* 4833 */ + IC_VEX_L_XS, /* 4834 */ + IC_VEX_L_XS, /* 4835 */ + IC_VEX_L_XD, /* 4836 */ + IC_VEX_L_XD, /* 4837 */ + IC_VEX_L_XD, /* 4838 */ + IC_VEX_L_XD, /* 4839 */ + IC_VEX_L_W, /* 4840 */ + IC_VEX_L_W, /* 4841 */ + IC_VEX_L_W_XS, /* 4842 */ + IC_VEX_L_W_XS, /* 4843 */ + IC_VEX_L_W_XD, /* 4844 */ + IC_VEX_L_W_XD, /* 4845 */ + IC_VEX_L_W_XD, /* 4846 */ + IC_VEX_L_W_XD, /* 4847 */ + IC_VEX_L_OPSIZE, /* 4848 */ + IC_VEX_L_OPSIZE, /* 4849 */ + IC_VEX_L_OPSIZE, /* 4850 */ + IC_VEX_L_OPSIZE, /* 4851 */ + IC_VEX_L_OPSIZE, /* 4852 */ + IC_VEX_L_OPSIZE, /* 4853 */ + IC_VEX_L_OPSIZE, /* 4854 */ + IC_VEX_L_OPSIZE, /* 4855 */ + IC_VEX_L_W_OPSIZE, /* 4856 */ + IC_VEX_L_W_OPSIZE, /* 4857 */ + IC_VEX_L_W_OPSIZE, /* 4858 */ + IC_VEX_L_W_OPSIZE, /* 4859 */ + IC_VEX_L_W_OPSIZE, /* 4860 */ + IC_VEX_L_W_OPSIZE, /* 4861 */ + IC_VEX_L_W_OPSIZE, /* 4862 */ + IC_VEX_L_W_OPSIZE, /* 4863 */ + IC_EVEX_L_KZ, /* 4864 */ + IC_EVEX_L_KZ, /* 4865 */ + IC_EVEX_L_XS_KZ, /* 4866 */ + IC_EVEX_L_XS_KZ, /* 4867 */ + IC_EVEX_L_XD_KZ, /* 4868 */ + IC_EVEX_L_XD_KZ, /* 4869 */ + IC_EVEX_L_XD_KZ, /* 4870 */ + IC_EVEX_L_XD_KZ, /* 4871 */ + IC_EVEX_L_W_KZ, /* 4872 */ + IC_EVEX_L_W_KZ, /* 4873 */ + IC_EVEX_L_W_XS_KZ, /* 4874 */ + IC_EVEX_L_W_XS_KZ, /* 4875 */ + IC_EVEX_L_W_XD_KZ, /* 4876 */ + IC_EVEX_L_W_XD_KZ, /* 4877 */ + IC_EVEX_L_W_XD_KZ, /* 4878 */ + IC_EVEX_L_W_XD_KZ, /* 4879 */ + IC_EVEX_L_OPSIZE_KZ, /* 4880 */ + IC_EVEX_L_OPSIZE_KZ, /* 4881 */ + IC_EVEX_L_OPSIZE_KZ, /* 4882 */ + IC_EVEX_L_OPSIZE_KZ, /* 4883 */ + IC_EVEX_L_OPSIZE_KZ, /* 4884 */ + IC_EVEX_L_OPSIZE_KZ, /* 4885 */ + IC_EVEX_L_OPSIZE_KZ, /* 4886 */ + IC_EVEX_L_OPSIZE_KZ, /* 4887 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4888 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4889 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4890 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4891 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4892 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4893 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4894 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4895 */ + IC_EVEX_L_KZ, /* 4896 */ + IC_EVEX_L_KZ, /* 4897 */ + IC_EVEX_L_XS_KZ, /* 4898 */ + IC_EVEX_L_XS_KZ, /* 4899 */ + IC_EVEX_L_XD_KZ, /* 4900 */ + IC_EVEX_L_XD_KZ, /* 4901 */ + IC_EVEX_L_XD_KZ, /* 4902 */ + IC_EVEX_L_XD_KZ, /* 4903 */ + IC_EVEX_L_W_KZ, /* 4904 */ + IC_EVEX_L_W_KZ, /* 4905 */ + IC_EVEX_L_W_XS_KZ, /* 4906 */ + IC_EVEX_L_W_XS_KZ, /* 4907 */ + IC_EVEX_L_W_XD_KZ, /* 4908 */ + IC_EVEX_L_W_XD_KZ, /* 4909 */ + IC_EVEX_L_W_XD_KZ, /* 4910 */ + IC_EVEX_L_W_XD_KZ, /* 4911 */ + IC_EVEX_L_OPSIZE_KZ, /* 4912 */ + IC_EVEX_L_OPSIZE_KZ, /* 4913 */ + IC_EVEX_L_OPSIZE_KZ, /* 4914 */ + IC_EVEX_L_OPSIZE_KZ, /* 4915 */ + IC_EVEX_L_OPSIZE_KZ, /* 4916 */ + IC_EVEX_L_OPSIZE_KZ, /* 4917 */ + IC_EVEX_L_OPSIZE_KZ, /* 4918 */ + IC_EVEX_L_OPSIZE_KZ, /* 4919 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4920 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4921 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4922 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4923 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4924 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4925 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4926 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4927 */ + IC_EVEX_L_KZ, /* 4928 */ + IC_EVEX_L_KZ, /* 4929 */ + IC_EVEX_L_XS_KZ, /* 4930 */ + IC_EVEX_L_XS_KZ, /* 4931 */ + IC_EVEX_L_XD_KZ, /* 4932 */ + IC_EVEX_L_XD_KZ, /* 4933 */ + IC_EVEX_L_XD_KZ, /* 4934 */ + IC_EVEX_L_XD_KZ, /* 4935 */ + IC_EVEX_L_W_KZ, /* 4936 */ + IC_EVEX_L_W_KZ, /* 4937 */ + IC_EVEX_L_W_XS_KZ, /* 4938 */ + IC_EVEX_L_W_XS_KZ, /* 4939 */ + IC_EVEX_L_W_XD_KZ, /* 4940 */ + IC_EVEX_L_W_XD_KZ, /* 4941 */ + IC_EVEX_L_W_XD_KZ, /* 4942 */ + IC_EVEX_L_W_XD_KZ, /* 4943 */ + IC_EVEX_L_OPSIZE_KZ, /* 4944 */ + IC_EVEX_L_OPSIZE_KZ, /* 4945 */ + IC_EVEX_L_OPSIZE_KZ, /* 4946 */ + IC_EVEX_L_OPSIZE_KZ, /* 4947 */ + IC_EVEX_L_OPSIZE_KZ, /* 4948 */ + IC_EVEX_L_OPSIZE_KZ, /* 4949 */ + IC_EVEX_L_OPSIZE_KZ, /* 4950 */ + IC_EVEX_L_OPSIZE_KZ, /* 4951 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4952 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4953 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4954 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4955 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4956 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4957 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4958 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4959 */ + IC_EVEX_L_KZ, /* 4960 */ + IC_EVEX_L_KZ, /* 4961 */ + IC_EVEX_L_XS_KZ, /* 4962 */ + IC_EVEX_L_XS_KZ, /* 4963 */ + IC_EVEX_L_XD_KZ, /* 4964 */ + IC_EVEX_L_XD_KZ, /* 4965 */ + IC_EVEX_L_XD_KZ, /* 4966 */ + IC_EVEX_L_XD_KZ, /* 4967 */ + IC_EVEX_L_W_KZ, /* 4968 */ + IC_EVEX_L_W_KZ, /* 4969 */ + IC_EVEX_L_W_XS_KZ, /* 4970 */ + IC_EVEX_L_W_XS_KZ, /* 4971 */ + IC_EVEX_L_W_XD_KZ, /* 4972 */ + IC_EVEX_L_W_XD_KZ, /* 4973 */ + IC_EVEX_L_W_XD_KZ, /* 4974 */ + IC_EVEX_L_W_XD_KZ, /* 4975 */ + IC_EVEX_L_OPSIZE_KZ, /* 4976 */ + IC_EVEX_L_OPSIZE_KZ, /* 4977 */ + IC_EVEX_L_OPSIZE_KZ, /* 4978 */ + IC_EVEX_L_OPSIZE_KZ, /* 4979 */ + IC_EVEX_L_OPSIZE_KZ, /* 4980 */ + IC_EVEX_L_OPSIZE_KZ, /* 4981 */ + IC_EVEX_L_OPSIZE_KZ, /* 4982 */ + IC_EVEX_L_OPSIZE_KZ, /* 4983 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4984 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4985 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4986 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4987 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4988 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4989 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4990 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 4991 */ + IC_EVEX_L_KZ, /* 4992 */ + IC_EVEX_L_KZ, /* 4993 */ + IC_EVEX_L_XS_KZ, /* 4994 */ + IC_EVEX_L_XS_KZ, /* 4995 */ + IC_EVEX_L_XD_KZ, /* 4996 */ + IC_EVEX_L_XD_KZ, /* 4997 */ + IC_EVEX_L_XD_KZ, /* 4998 */ + IC_EVEX_L_XD_KZ, /* 4999 */ + IC_EVEX_L_W_KZ, /* 5000 */ + IC_EVEX_L_W_KZ, /* 5001 */ + IC_EVEX_L_W_XS_KZ, /* 5002 */ + IC_EVEX_L_W_XS_KZ, /* 5003 */ + IC_EVEX_L_W_XD_KZ, /* 5004 */ + IC_EVEX_L_W_XD_KZ, /* 5005 */ + IC_EVEX_L_W_XD_KZ, /* 5006 */ + IC_EVEX_L_W_XD_KZ, /* 5007 */ + IC_EVEX_L_OPSIZE_KZ, /* 5008 */ + IC_EVEX_L_OPSIZE_KZ, /* 5009 */ + IC_EVEX_L_OPSIZE_KZ, /* 5010 */ + IC_EVEX_L_OPSIZE_KZ, /* 5011 */ + IC_EVEX_L_OPSIZE_KZ, /* 5012 */ + IC_EVEX_L_OPSIZE_KZ, /* 5013 */ + IC_EVEX_L_OPSIZE_KZ, /* 5014 */ + IC_EVEX_L_OPSIZE_KZ, /* 5015 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5016 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5017 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5018 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5019 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5020 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5021 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5022 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5023 */ + IC_EVEX_L_KZ, /* 5024 */ + IC_EVEX_L_KZ, /* 5025 */ + IC_EVEX_L_XS_KZ, /* 5026 */ + IC_EVEX_L_XS_KZ, /* 5027 */ + IC_EVEX_L_XD_KZ, /* 5028 */ + IC_EVEX_L_XD_KZ, /* 5029 */ + IC_EVEX_L_XD_KZ, /* 5030 */ + IC_EVEX_L_XD_KZ, /* 5031 */ + IC_EVEX_L_W_KZ, /* 5032 */ + IC_EVEX_L_W_KZ, /* 5033 */ + IC_EVEX_L_W_XS_KZ, /* 5034 */ + IC_EVEX_L_W_XS_KZ, /* 5035 */ + IC_EVEX_L_W_XD_KZ, /* 5036 */ + IC_EVEX_L_W_XD_KZ, /* 5037 */ + IC_EVEX_L_W_XD_KZ, /* 5038 */ + IC_EVEX_L_W_XD_KZ, /* 5039 */ + IC_EVEX_L_OPSIZE_KZ, /* 5040 */ + IC_EVEX_L_OPSIZE_KZ, /* 5041 */ + IC_EVEX_L_OPSIZE_KZ, /* 5042 */ + IC_EVEX_L_OPSIZE_KZ, /* 5043 */ + IC_EVEX_L_OPSIZE_KZ, /* 5044 */ + IC_EVEX_L_OPSIZE_KZ, /* 5045 */ + IC_EVEX_L_OPSIZE_KZ, /* 5046 */ + IC_EVEX_L_OPSIZE_KZ, /* 5047 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5048 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5049 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5050 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5051 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5052 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5053 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5054 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5055 */ + IC_EVEX_L_KZ, /* 5056 */ + IC_EVEX_L_KZ, /* 5057 */ + IC_EVEX_L_XS_KZ, /* 5058 */ + IC_EVEX_L_XS_KZ, /* 5059 */ + IC_EVEX_L_XD_KZ, /* 5060 */ + IC_EVEX_L_XD_KZ, /* 5061 */ + IC_EVEX_L_XD_KZ, /* 5062 */ + IC_EVEX_L_XD_KZ, /* 5063 */ + IC_EVEX_L_W_KZ, /* 5064 */ + IC_EVEX_L_W_KZ, /* 5065 */ + IC_EVEX_L_W_XS_KZ, /* 5066 */ + IC_EVEX_L_W_XS_KZ, /* 5067 */ + IC_EVEX_L_W_XD_KZ, /* 5068 */ + IC_EVEX_L_W_XD_KZ, /* 5069 */ + IC_EVEX_L_W_XD_KZ, /* 5070 */ + IC_EVEX_L_W_XD_KZ, /* 5071 */ + IC_EVEX_L_OPSIZE_KZ, /* 5072 */ + IC_EVEX_L_OPSIZE_KZ, /* 5073 */ + IC_EVEX_L_OPSIZE_KZ, /* 5074 */ + IC_EVEX_L_OPSIZE_KZ, /* 5075 */ + IC_EVEX_L_OPSIZE_KZ, /* 5076 */ + IC_EVEX_L_OPSIZE_KZ, /* 5077 */ + IC_EVEX_L_OPSIZE_KZ, /* 5078 */ + IC_EVEX_L_OPSIZE_KZ, /* 5079 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5080 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5081 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5082 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5083 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5084 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5085 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5086 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5087 */ + IC_EVEX_L_KZ, /* 5088 */ + IC_EVEX_L_KZ, /* 5089 */ + IC_EVEX_L_XS_KZ, /* 5090 */ + IC_EVEX_L_XS_KZ, /* 5091 */ + IC_EVEX_L_XD_KZ, /* 5092 */ + IC_EVEX_L_XD_KZ, /* 5093 */ + IC_EVEX_L_XD_KZ, /* 5094 */ + IC_EVEX_L_XD_KZ, /* 5095 */ + IC_EVEX_L_W_KZ, /* 5096 */ + IC_EVEX_L_W_KZ, /* 5097 */ + IC_EVEX_L_W_XS_KZ, /* 5098 */ + IC_EVEX_L_W_XS_KZ, /* 5099 */ + IC_EVEX_L_W_XD_KZ, /* 5100 */ + IC_EVEX_L_W_XD_KZ, /* 5101 */ + IC_EVEX_L_W_XD_KZ, /* 5102 */ + IC_EVEX_L_W_XD_KZ, /* 5103 */ + IC_EVEX_L_OPSIZE_KZ, /* 5104 */ + IC_EVEX_L_OPSIZE_KZ, /* 5105 */ + IC_EVEX_L_OPSIZE_KZ, /* 5106 */ + IC_EVEX_L_OPSIZE_KZ, /* 5107 */ + IC_EVEX_L_OPSIZE_KZ, /* 5108 */ + IC_EVEX_L_OPSIZE_KZ, /* 5109 */ + IC_EVEX_L_OPSIZE_KZ, /* 5110 */ + IC_EVEX_L_OPSIZE_KZ, /* 5111 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5112 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5113 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5114 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5115 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5116 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5117 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5118 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 5119 */ + IC, /* 5120 */ + IC_64BIT, /* 5121 */ + IC_XS, /* 5122 */ + IC_64BIT_XS, /* 5123 */ + IC_XD, /* 5124 */ + IC_64BIT_XD, /* 5125 */ + IC_XS, /* 5126 */ + IC_64BIT_XS, /* 5127 */ + IC, /* 5128 */ + IC_64BIT_REXW, /* 5129 */ + IC_XS, /* 5130 */ + IC_64BIT_REXW_XS, /* 5131 */ + IC_XD, /* 5132 */ + IC_64BIT_REXW_XD, /* 5133 */ + IC_XS, /* 5134 */ + IC_64BIT_REXW_XS, /* 5135 */ + IC_OPSIZE, /* 5136 */ + IC_64BIT_OPSIZE, /* 5137 */ + IC_XS_OPSIZE, /* 5138 */ + IC_64BIT_XS_OPSIZE, /* 5139 */ + IC_XD_OPSIZE, /* 5140 */ + IC_64BIT_XD_OPSIZE, /* 5141 */ + IC_XS_OPSIZE, /* 5142 */ + IC_64BIT_XD_OPSIZE, /* 5143 */ + IC_OPSIZE, /* 5144 */ + IC_64BIT_REXW_OPSIZE, /* 5145 */ + IC_XS_OPSIZE, /* 5146 */ + IC_64BIT_REXW_XS, /* 5147 */ + IC_XD_OPSIZE, /* 5148 */ + IC_64BIT_REXW_XD, /* 5149 */ + IC_XS_OPSIZE, /* 5150 */ + IC_64BIT_REXW_XS, /* 5151 */ + IC_ADSIZE, /* 5152 */ + IC_64BIT_ADSIZE, /* 5153 */ + IC_XS_ADSIZE, /* 5154 */ + IC_64BIT_XS_ADSIZE, /* 5155 */ + IC_XD_ADSIZE, /* 5156 */ + IC_64BIT_XD_ADSIZE, /* 5157 */ + IC_XS_ADSIZE, /* 5158 */ + IC_64BIT_XD_ADSIZE, /* 5159 */ + IC_ADSIZE, /* 5160 */ + IC_64BIT_REXW_ADSIZE, /* 5161 */ + IC_XS_ADSIZE, /* 5162 */ + IC_64BIT_REXW_XS, /* 5163 */ + IC_XD_ADSIZE, /* 5164 */ + IC_64BIT_REXW_XD, /* 5165 */ + IC_XS_ADSIZE, /* 5166 */ + IC_64BIT_REXW_XS, /* 5167 */ + IC_OPSIZE_ADSIZE, /* 5168 */ + IC_64BIT_OPSIZE_ADSIZE, /* 5169 */ + IC_XS_OPSIZE, /* 5170 */ + IC_64BIT_XS_OPSIZE, /* 5171 */ + IC_XD_OPSIZE, /* 5172 */ + IC_64BIT_XD_OPSIZE, /* 5173 */ + IC_XS_OPSIZE, /* 5174 */ + IC_64BIT_XD_OPSIZE, /* 5175 */ + IC_OPSIZE_ADSIZE, /* 5176 */ + IC_64BIT_REXW_OPSIZE, /* 5177 */ + IC_XS_OPSIZE, /* 5178 */ + IC_64BIT_REXW_XS, /* 5179 */ + IC_XD_OPSIZE, /* 5180 */ + IC_64BIT_REXW_XD, /* 5181 */ + IC_XS_OPSIZE, /* 5182 */ + IC_64BIT_REXW_XS, /* 5183 */ + IC_VEX, /* 5184 */ + IC_VEX, /* 5185 */ + IC_VEX_XS, /* 5186 */ + IC_VEX_XS, /* 5187 */ + IC_VEX_XD, /* 5188 */ + IC_VEX_XD, /* 5189 */ + IC_VEX_XD, /* 5190 */ + IC_VEX_XD, /* 5191 */ + IC_VEX_W, /* 5192 */ + IC_VEX_W, /* 5193 */ + IC_VEX_W_XS, /* 5194 */ + IC_VEX_W_XS, /* 5195 */ + IC_VEX_W_XD, /* 5196 */ + IC_VEX_W_XD, /* 5197 */ + IC_VEX_W_XD, /* 5198 */ + IC_VEX_W_XD, /* 5199 */ + IC_VEX_OPSIZE, /* 5200 */ + IC_VEX_OPSIZE, /* 5201 */ + IC_VEX_OPSIZE, /* 5202 */ + IC_VEX_OPSIZE, /* 5203 */ + IC_VEX_OPSIZE, /* 5204 */ + IC_VEX_OPSIZE, /* 5205 */ + IC_VEX_OPSIZE, /* 5206 */ + IC_VEX_OPSIZE, /* 5207 */ + IC_VEX_W_OPSIZE, /* 5208 */ + IC_VEX_W_OPSIZE, /* 5209 */ + IC_VEX_W_OPSIZE, /* 5210 */ + IC_VEX_W_OPSIZE, /* 5211 */ + IC_VEX_W_OPSIZE, /* 5212 */ + IC_VEX_W_OPSIZE, /* 5213 */ + IC_VEX_W_OPSIZE, /* 5214 */ + IC_VEX_W_OPSIZE, /* 5215 */ + IC_VEX, /* 5216 */ + IC_VEX, /* 5217 */ + IC_VEX_XS, /* 5218 */ + IC_VEX_XS, /* 5219 */ + IC_VEX_XD, /* 5220 */ + IC_VEX_XD, /* 5221 */ + IC_VEX_XD, /* 5222 */ + IC_VEX_XD, /* 5223 */ + IC_VEX_W, /* 5224 */ + IC_VEX_W, /* 5225 */ + IC_VEX_W_XS, /* 5226 */ + IC_VEX_W_XS, /* 5227 */ + IC_VEX_W_XD, /* 5228 */ + IC_VEX_W_XD, /* 5229 */ + IC_VEX_W_XD, /* 5230 */ + IC_VEX_W_XD, /* 5231 */ + IC_VEX_OPSIZE, /* 5232 */ + IC_VEX_OPSIZE, /* 5233 */ + IC_VEX_OPSIZE, /* 5234 */ + IC_VEX_OPSIZE, /* 5235 */ + IC_VEX_OPSIZE, /* 5236 */ + IC_VEX_OPSIZE, /* 5237 */ + IC_VEX_OPSIZE, /* 5238 */ + IC_VEX_OPSIZE, /* 5239 */ + IC_VEX_W_OPSIZE, /* 5240 */ + IC_VEX_W_OPSIZE, /* 5241 */ + IC_VEX_W_OPSIZE, /* 5242 */ + IC_VEX_W_OPSIZE, /* 5243 */ + IC_VEX_W_OPSIZE, /* 5244 */ + IC_VEX_W_OPSIZE, /* 5245 */ + IC_VEX_W_OPSIZE, /* 5246 */ + IC_VEX_W_OPSIZE, /* 5247 */ + IC_VEX_L, /* 5248 */ + IC_VEX_L, /* 5249 */ + IC_VEX_L_XS, /* 5250 */ + IC_VEX_L_XS, /* 5251 */ + IC_VEX_L_XD, /* 5252 */ + IC_VEX_L_XD, /* 5253 */ + IC_VEX_L_XD, /* 5254 */ + IC_VEX_L_XD, /* 5255 */ + IC_VEX_L_W, /* 5256 */ + IC_VEX_L_W, /* 5257 */ + IC_VEX_L_W_XS, /* 5258 */ + IC_VEX_L_W_XS, /* 5259 */ + IC_VEX_L_W_XD, /* 5260 */ + IC_VEX_L_W_XD, /* 5261 */ + IC_VEX_L_W_XD, /* 5262 */ + IC_VEX_L_W_XD, /* 5263 */ + IC_VEX_L_OPSIZE, /* 5264 */ + IC_VEX_L_OPSIZE, /* 5265 */ + IC_VEX_L_OPSIZE, /* 5266 */ + IC_VEX_L_OPSIZE, /* 5267 */ + IC_VEX_L_OPSIZE, /* 5268 */ + IC_VEX_L_OPSIZE, /* 5269 */ + IC_VEX_L_OPSIZE, /* 5270 */ + IC_VEX_L_OPSIZE, /* 5271 */ + IC_VEX_L_W_OPSIZE, /* 5272 */ + IC_VEX_L_W_OPSIZE, /* 5273 */ + IC_VEX_L_W_OPSIZE, /* 5274 */ + IC_VEX_L_W_OPSIZE, /* 5275 */ + IC_VEX_L_W_OPSIZE, /* 5276 */ + IC_VEX_L_W_OPSIZE, /* 5277 */ + IC_VEX_L_W_OPSIZE, /* 5278 */ + IC_VEX_L_W_OPSIZE, /* 5279 */ + IC_VEX_L, /* 5280 */ + IC_VEX_L, /* 5281 */ + IC_VEX_L_XS, /* 5282 */ + IC_VEX_L_XS, /* 5283 */ + IC_VEX_L_XD, /* 5284 */ + IC_VEX_L_XD, /* 5285 */ + IC_VEX_L_XD, /* 5286 */ + IC_VEX_L_XD, /* 5287 */ + IC_VEX_L_W, /* 5288 */ + IC_VEX_L_W, /* 5289 */ + IC_VEX_L_W_XS, /* 5290 */ + IC_VEX_L_W_XS, /* 5291 */ + IC_VEX_L_W_XD, /* 5292 */ + IC_VEX_L_W_XD, /* 5293 */ + IC_VEX_L_W_XD, /* 5294 */ + IC_VEX_L_W_XD, /* 5295 */ + IC_VEX_L_OPSIZE, /* 5296 */ + IC_VEX_L_OPSIZE, /* 5297 */ + IC_VEX_L_OPSIZE, /* 5298 */ + IC_VEX_L_OPSIZE, /* 5299 */ + IC_VEX_L_OPSIZE, /* 5300 */ + IC_VEX_L_OPSIZE, /* 5301 */ + IC_VEX_L_OPSIZE, /* 5302 */ + IC_VEX_L_OPSIZE, /* 5303 */ + IC_VEX_L_W_OPSIZE, /* 5304 */ + IC_VEX_L_W_OPSIZE, /* 5305 */ + IC_VEX_L_W_OPSIZE, /* 5306 */ + IC_VEX_L_W_OPSIZE, /* 5307 */ + IC_VEX_L_W_OPSIZE, /* 5308 */ + IC_VEX_L_W_OPSIZE, /* 5309 */ + IC_VEX_L_W_OPSIZE, /* 5310 */ + IC_VEX_L_W_OPSIZE, /* 5311 */ + IC_VEX_L, /* 5312 */ + IC_VEX_L, /* 5313 */ + IC_VEX_L_XS, /* 5314 */ + IC_VEX_L_XS, /* 5315 */ + IC_VEX_L_XD, /* 5316 */ + IC_VEX_L_XD, /* 5317 */ + IC_VEX_L_XD, /* 5318 */ + IC_VEX_L_XD, /* 5319 */ + IC_VEX_L_W, /* 5320 */ + IC_VEX_L_W, /* 5321 */ + IC_VEX_L_W_XS, /* 5322 */ + IC_VEX_L_W_XS, /* 5323 */ + IC_VEX_L_W_XD, /* 5324 */ + IC_VEX_L_W_XD, /* 5325 */ + IC_VEX_L_W_XD, /* 5326 */ + IC_VEX_L_W_XD, /* 5327 */ + IC_VEX_L_OPSIZE, /* 5328 */ + IC_VEX_L_OPSIZE, /* 5329 */ + IC_VEX_L_OPSIZE, /* 5330 */ + IC_VEX_L_OPSIZE, /* 5331 */ + IC_VEX_L_OPSIZE, /* 5332 */ + IC_VEX_L_OPSIZE, /* 5333 */ + IC_VEX_L_OPSIZE, /* 5334 */ + IC_VEX_L_OPSIZE, /* 5335 */ + IC_VEX_L_W_OPSIZE, /* 5336 */ + IC_VEX_L_W_OPSIZE, /* 5337 */ + IC_VEX_L_W_OPSIZE, /* 5338 */ + IC_VEX_L_W_OPSIZE, /* 5339 */ + IC_VEX_L_W_OPSIZE, /* 5340 */ + IC_VEX_L_W_OPSIZE, /* 5341 */ + IC_VEX_L_W_OPSIZE, /* 5342 */ + IC_VEX_L_W_OPSIZE, /* 5343 */ + IC_VEX_L, /* 5344 */ + IC_VEX_L, /* 5345 */ + IC_VEX_L_XS, /* 5346 */ + IC_VEX_L_XS, /* 5347 */ + IC_VEX_L_XD, /* 5348 */ + IC_VEX_L_XD, /* 5349 */ + IC_VEX_L_XD, /* 5350 */ + IC_VEX_L_XD, /* 5351 */ + IC_VEX_L_W, /* 5352 */ + IC_VEX_L_W, /* 5353 */ + IC_VEX_L_W_XS, /* 5354 */ + IC_VEX_L_W_XS, /* 5355 */ + IC_VEX_L_W_XD, /* 5356 */ + IC_VEX_L_W_XD, /* 5357 */ + IC_VEX_L_W_XD, /* 5358 */ + IC_VEX_L_W_XD, /* 5359 */ + IC_VEX_L_OPSIZE, /* 5360 */ + IC_VEX_L_OPSIZE, /* 5361 */ + IC_VEX_L_OPSIZE, /* 5362 */ + IC_VEX_L_OPSIZE, /* 5363 */ + IC_VEX_L_OPSIZE, /* 5364 */ + IC_VEX_L_OPSIZE, /* 5365 */ + IC_VEX_L_OPSIZE, /* 5366 */ + IC_VEX_L_OPSIZE, /* 5367 */ + IC_VEX_L_W_OPSIZE, /* 5368 */ + IC_VEX_L_W_OPSIZE, /* 5369 */ + IC_VEX_L_W_OPSIZE, /* 5370 */ + IC_VEX_L_W_OPSIZE, /* 5371 */ + IC_VEX_L_W_OPSIZE, /* 5372 */ + IC_VEX_L_W_OPSIZE, /* 5373 */ + IC_VEX_L_W_OPSIZE, /* 5374 */ + IC_VEX_L_W_OPSIZE, /* 5375 */ + IC_EVEX_L2_KZ, /* 5376 */ + IC_EVEX_L2_KZ, /* 5377 */ + IC_EVEX_L2_XS_KZ, /* 5378 */ + IC_EVEX_L2_XS_KZ, /* 5379 */ + IC_EVEX_L2_XD_KZ, /* 5380 */ + IC_EVEX_L2_XD_KZ, /* 5381 */ + IC_EVEX_L2_XD_KZ, /* 5382 */ + IC_EVEX_L2_XD_KZ, /* 5383 */ + IC_EVEX_L2_W_KZ, /* 5384 */ + IC_EVEX_L2_W_KZ, /* 5385 */ + IC_EVEX_L2_W_XS_KZ, /* 5386 */ + IC_EVEX_L2_W_XS_KZ, /* 5387 */ + IC_EVEX_L2_W_XD_KZ, /* 5388 */ + IC_EVEX_L2_W_XD_KZ, /* 5389 */ + IC_EVEX_L2_W_XD_KZ, /* 5390 */ + IC_EVEX_L2_W_XD_KZ, /* 5391 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5392 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5393 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5394 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5395 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5396 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5397 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5398 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5399 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5400 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5401 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5402 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5403 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5404 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5405 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5406 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5407 */ + IC_EVEX_L2_KZ, /* 5408 */ + IC_EVEX_L2_KZ, /* 5409 */ + IC_EVEX_L2_XS_KZ, /* 5410 */ + IC_EVEX_L2_XS_KZ, /* 5411 */ + IC_EVEX_L2_XD_KZ, /* 5412 */ + IC_EVEX_L2_XD_KZ, /* 5413 */ + IC_EVEX_L2_XD_KZ, /* 5414 */ + IC_EVEX_L2_XD_KZ, /* 5415 */ + IC_EVEX_L2_W_KZ, /* 5416 */ + IC_EVEX_L2_W_KZ, /* 5417 */ + IC_EVEX_L2_W_XS_KZ, /* 5418 */ + IC_EVEX_L2_W_XS_KZ, /* 5419 */ + IC_EVEX_L2_W_XD_KZ, /* 5420 */ + IC_EVEX_L2_W_XD_KZ, /* 5421 */ + IC_EVEX_L2_W_XD_KZ, /* 5422 */ + IC_EVEX_L2_W_XD_KZ, /* 5423 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5424 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5425 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5426 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5427 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5428 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5429 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5430 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5431 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5432 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5433 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5434 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5435 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5436 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5437 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5438 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5439 */ + IC_EVEX_L2_KZ, /* 5440 */ + IC_EVEX_L2_KZ, /* 5441 */ + IC_EVEX_L2_XS_KZ, /* 5442 */ + IC_EVEX_L2_XS_KZ, /* 5443 */ + IC_EVEX_L2_XD_KZ, /* 5444 */ + IC_EVEX_L2_XD_KZ, /* 5445 */ + IC_EVEX_L2_XD_KZ, /* 5446 */ + IC_EVEX_L2_XD_KZ, /* 5447 */ + IC_EVEX_L2_W_KZ, /* 5448 */ + IC_EVEX_L2_W_KZ, /* 5449 */ + IC_EVEX_L2_W_XS_KZ, /* 5450 */ + IC_EVEX_L2_W_XS_KZ, /* 5451 */ + IC_EVEX_L2_W_XD_KZ, /* 5452 */ + IC_EVEX_L2_W_XD_KZ, /* 5453 */ + IC_EVEX_L2_W_XD_KZ, /* 5454 */ + IC_EVEX_L2_W_XD_KZ, /* 5455 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5456 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5457 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5458 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5459 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5460 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5461 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5462 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5463 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5464 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5465 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5466 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5467 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5468 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5469 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5470 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5471 */ + IC_EVEX_L2_KZ, /* 5472 */ + IC_EVEX_L2_KZ, /* 5473 */ + IC_EVEX_L2_XS_KZ, /* 5474 */ + IC_EVEX_L2_XS_KZ, /* 5475 */ + IC_EVEX_L2_XD_KZ, /* 5476 */ + IC_EVEX_L2_XD_KZ, /* 5477 */ + IC_EVEX_L2_XD_KZ, /* 5478 */ + IC_EVEX_L2_XD_KZ, /* 5479 */ + IC_EVEX_L2_W_KZ, /* 5480 */ + IC_EVEX_L2_W_KZ, /* 5481 */ + IC_EVEX_L2_W_XS_KZ, /* 5482 */ + IC_EVEX_L2_W_XS_KZ, /* 5483 */ + IC_EVEX_L2_W_XD_KZ, /* 5484 */ + IC_EVEX_L2_W_XD_KZ, /* 5485 */ + IC_EVEX_L2_W_XD_KZ, /* 5486 */ + IC_EVEX_L2_W_XD_KZ, /* 5487 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5488 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5489 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5490 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5491 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5492 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5493 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5494 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5495 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5496 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5497 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5498 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5499 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5500 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5501 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5502 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5503 */ + IC_EVEX_L2_KZ, /* 5504 */ + IC_EVEX_L2_KZ, /* 5505 */ + IC_EVEX_L2_XS_KZ, /* 5506 */ + IC_EVEX_L2_XS_KZ, /* 5507 */ + IC_EVEX_L2_XD_KZ, /* 5508 */ + IC_EVEX_L2_XD_KZ, /* 5509 */ + IC_EVEX_L2_XD_KZ, /* 5510 */ + IC_EVEX_L2_XD_KZ, /* 5511 */ + IC_EVEX_L2_W_KZ, /* 5512 */ + IC_EVEX_L2_W_KZ, /* 5513 */ + IC_EVEX_L2_W_XS_KZ, /* 5514 */ + IC_EVEX_L2_W_XS_KZ, /* 5515 */ + IC_EVEX_L2_W_XD_KZ, /* 5516 */ + IC_EVEX_L2_W_XD_KZ, /* 5517 */ + IC_EVEX_L2_W_XD_KZ, /* 5518 */ + IC_EVEX_L2_W_XD_KZ, /* 5519 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5520 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5521 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5522 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5523 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5524 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5525 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5526 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5527 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5528 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5529 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5530 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5531 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5532 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5533 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5534 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5535 */ + IC_EVEX_L2_KZ, /* 5536 */ + IC_EVEX_L2_KZ, /* 5537 */ + IC_EVEX_L2_XS_KZ, /* 5538 */ + IC_EVEX_L2_XS_KZ, /* 5539 */ + IC_EVEX_L2_XD_KZ, /* 5540 */ + IC_EVEX_L2_XD_KZ, /* 5541 */ + IC_EVEX_L2_XD_KZ, /* 5542 */ + IC_EVEX_L2_XD_KZ, /* 5543 */ + IC_EVEX_L2_W_KZ, /* 5544 */ + IC_EVEX_L2_W_KZ, /* 5545 */ + IC_EVEX_L2_W_XS_KZ, /* 5546 */ + IC_EVEX_L2_W_XS_KZ, /* 5547 */ + IC_EVEX_L2_W_XD_KZ, /* 5548 */ + IC_EVEX_L2_W_XD_KZ, /* 5549 */ + IC_EVEX_L2_W_XD_KZ, /* 5550 */ + IC_EVEX_L2_W_XD_KZ, /* 5551 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5552 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5553 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5554 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5555 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5556 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5557 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5558 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5559 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5560 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5561 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5562 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5563 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5564 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5565 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5566 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5567 */ + IC_EVEX_L2_KZ, /* 5568 */ + IC_EVEX_L2_KZ, /* 5569 */ + IC_EVEX_L2_XS_KZ, /* 5570 */ + IC_EVEX_L2_XS_KZ, /* 5571 */ + IC_EVEX_L2_XD_KZ, /* 5572 */ + IC_EVEX_L2_XD_KZ, /* 5573 */ + IC_EVEX_L2_XD_KZ, /* 5574 */ + IC_EVEX_L2_XD_KZ, /* 5575 */ + IC_EVEX_L2_W_KZ, /* 5576 */ + IC_EVEX_L2_W_KZ, /* 5577 */ + IC_EVEX_L2_W_XS_KZ, /* 5578 */ + IC_EVEX_L2_W_XS_KZ, /* 5579 */ + IC_EVEX_L2_W_XD_KZ, /* 5580 */ + IC_EVEX_L2_W_XD_KZ, /* 5581 */ + IC_EVEX_L2_W_XD_KZ, /* 5582 */ + IC_EVEX_L2_W_XD_KZ, /* 5583 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5584 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5585 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5586 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5587 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5588 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5589 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5590 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5591 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5592 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5593 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5594 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5595 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5596 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5597 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5598 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5599 */ + IC_EVEX_L2_KZ, /* 5600 */ + IC_EVEX_L2_KZ, /* 5601 */ + IC_EVEX_L2_XS_KZ, /* 5602 */ + IC_EVEX_L2_XS_KZ, /* 5603 */ + IC_EVEX_L2_XD_KZ, /* 5604 */ + IC_EVEX_L2_XD_KZ, /* 5605 */ + IC_EVEX_L2_XD_KZ, /* 5606 */ + IC_EVEX_L2_XD_KZ, /* 5607 */ + IC_EVEX_L2_W_KZ, /* 5608 */ + IC_EVEX_L2_W_KZ, /* 5609 */ + IC_EVEX_L2_W_XS_KZ, /* 5610 */ + IC_EVEX_L2_W_XS_KZ, /* 5611 */ + IC_EVEX_L2_W_XD_KZ, /* 5612 */ + IC_EVEX_L2_W_XD_KZ, /* 5613 */ + IC_EVEX_L2_W_XD_KZ, /* 5614 */ + IC_EVEX_L2_W_XD_KZ, /* 5615 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5616 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5617 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5618 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5619 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5620 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5621 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5622 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5623 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5624 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5625 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5626 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5627 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5628 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5629 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5630 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5631 */ + IC, /* 5632 */ + IC_64BIT, /* 5633 */ + IC_XS, /* 5634 */ + IC_64BIT_XS, /* 5635 */ + IC_XD, /* 5636 */ + IC_64BIT_XD, /* 5637 */ + IC_XS, /* 5638 */ + IC_64BIT_XS, /* 5639 */ + IC, /* 5640 */ + IC_64BIT_REXW, /* 5641 */ + IC_XS, /* 5642 */ + IC_64BIT_REXW_XS, /* 5643 */ + IC_XD, /* 5644 */ + IC_64BIT_REXW_XD, /* 5645 */ + IC_XS, /* 5646 */ + IC_64BIT_REXW_XS, /* 5647 */ + IC_OPSIZE, /* 5648 */ + IC_64BIT_OPSIZE, /* 5649 */ + IC_XS_OPSIZE, /* 5650 */ + IC_64BIT_XS_OPSIZE, /* 5651 */ + IC_XD_OPSIZE, /* 5652 */ + IC_64BIT_XD_OPSIZE, /* 5653 */ + IC_XS_OPSIZE, /* 5654 */ + IC_64BIT_XD_OPSIZE, /* 5655 */ + IC_OPSIZE, /* 5656 */ + IC_64BIT_REXW_OPSIZE, /* 5657 */ + IC_XS_OPSIZE, /* 5658 */ + IC_64BIT_REXW_XS, /* 5659 */ + IC_XD_OPSIZE, /* 5660 */ + IC_64BIT_REXW_XD, /* 5661 */ + IC_XS_OPSIZE, /* 5662 */ + IC_64BIT_REXW_XS, /* 5663 */ + IC_ADSIZE, /* 5664 */ + IC_64BIT_ADSIZE, /* 5665 */ + IC_XS_ADSIZE, /* 5666 */ + IC_64BIT_XS_ADSIZE, /* 5667 */ + IC_XD_ADSIZE, /* 5668 */ + IC_64BIT_XD_ADSIZE, /* 5669 */ + IC_XS_ADSIZE, /* 5670 */ + IC_64BIT_XD_ADSIZE, /* 5671 */ + IC_ADSIZE, /* 5672 */ + IC_64BIT_REXW_ADSIZE, /* 5673 */ + IC_XS_ADSIZE, /* 5674 */ + IC_64BIT_REXW_XS, /* 5675 */ + IC_XD_ADSIZE, /* 5676 */ + IC_64BIT_REXW_XD, /* 5677 */ + IC_XS_ADSIZE, /* 5678 */ + IC_64BIT_REXW_XS, /* 5679 */ + IC_OPSIZE_ADSIZE, /* 5680 */ + IC_64BIT_OPSIZE_ADSIZE, /* 5681 */ + IC_XS_OPSIZE, /* 5682 */ + IC_64BIT_XS_OPSIZE, /* 5683 */ + IC_XD_OPSIZE, /* 5684 */ + IC_64BIT_XD_OPSIZE, /* 5685 */ + IC_XS_OPSIZE, /* 5686 */ + IC_64BIT_XD_OPSIZE, /* 5687 */ + IC_OPSIZE_ADSIZE, /* 5688 */ + IC_64BIT_REXW_OPSIZE, /* 5689 */ + IC_XS_OPSIZE, /* 5690 */ + IC_64BIT_REXW_XS, /* 5691 */ + IC_XD_OPSIZE, /* 5692 */ + IC_64BIT_REXW_XD, /* 5693 */ + IC_XS_OPSIZE, /* 5694 */ + IC_64BIT_REXW_XS, /* 5695 */ + IC_VEX, /* 5696 */ + IC_VEX, /* 5697 */ + IC_VEX_XS, /* 5698 */ + IC_VEX_XS, /* 5699 */ + IC_VEX_XD, /* 5700 */ + IC_VEX_XD, /* 5701 */ + IC_VEX_XD, /* 5702 */ + IC_VEX_XD, /* 5703 */ + IC_VEX_W, /* 5704 */ + IC_VEX_W, /* 5705 */ + IC_VEX_W_XS, /* 5706 */ + IC_VEX_W_XS, /* 5707 */ + IC_VEX_W_XD, /* 5708 */ + IC_VEX_W_XD, /* 5709 */ + IC_VEX_W_XD, /* 5710 */ + IC_VEX_W_XD, /* 5711 */ + IC_VEX_OPSIZE, /* 5712 */ + IC_VEX_OPSIZE, /* 5713 */ + IC_VEX_OPSIZE, /* 5714 */ + IC_VEX_OPSIZE, /* 5715 */ + IC_VEX_OPSIZE, /* 5716 */ + IC_VEX_OPSIZE, /* 5717 */ + IC_VEX_OPSIZE, /* 5718 */ + IC_VEX_OPSIZE, /* 5719 */ + IC_VEX_W_OPSIZE, /* 5720 */ + IC_VEX_W_OPSIZE, /* 5721 */ + IC_VEX_W_OPSIZE, /* 5722 */ + IC_VEX_W_OPSIZE, /* 5723 */ + IC_VEX_W_OPSIZE, /* 5724 */ + IC_VEX_W_OPSIZE, /* 5725 */ + IC_VEX_W_OPSIZE, /* 5726 */ + IC_VEX_W_OPSIZE, /* 5727 */ + IC_VEX, /* 5728 */ + IC_VEX, /* 5729 */ + IC_VEX_XS, /* 5730 */ + IC_VEX_XS, /* 5731 */ + IC_VEX_XD, /* 5732 */ + IC_VEX_XD, /* 5733 */ + IC_VEX_XD, /* 5734 */ + IC_VEX_XD, /* 5735 */ + IC_VEX_W, /* 5736 */ + IC_VEX_W, /* 5737 */ + IC_VEX_W_XS, /* 5738 */ + IC_VEX_W_XS, /* 5739 */ + IC_VEX_W_XD, /* 5740 */ + IC_VEX_W_XD, /* 5741 */ + IC_VEX_W_XD, /* 5742 */ + IC_VEX_W_XD, /* 5743 */ + IC_VEX_OPSIZE, /* 5744 */ + IC_VEX_OPSIZE, /* 5745 */ + IC_VEX_OPSIZE, /* 5746 */ + IC_VEX_OPSIZE, /* 5747 */ + IC_VEX_OPSIZE, /* 5748 */ + IC_VEX_OPSIZE, /* 5749 */ + IC_VEX_OPSIZE, /* 5750 */ + IC_VEX_OPSIZE, /* 5751 */ + IC_VEX_W_OPSIZE, /* 5752 */ + IC_VEX_W_OPSIZE, /* 5753 */ + IC_VEX_W_OPSIZE, /* 5754 */ + IC_VEX_W_OPSIZE, /* 5755 */ + IC_VEX_W_OPSIZE, /* 5756 */ + IC_VEX_W_OPSIZE, /* 5757 */ + IC_VEX_W_OPSIZE, /* 5758 */ + IC_VEX_W_OPSIZE, /* 5759 */ + IC_VEX_L, /* 5760 */ + IC_VEX_L, /* 5761 */ + IC_VEX_L_XS, /* 5762 */ + IC_VEX_L_XS, /* 5763 */ + IC_VEX_L_XD, /* 5764 */ + IC_VEX_L_XD, /* 5765 */ + IC_VEX_L_XD, /* 5766 */ + IC_VEX_L_XD, /* 5767 */ + IC_VEX_L_W, /* 5768 */ + IC_VEX_L_W, /* 5769 */ + IC_VEX_L_W_XS, /* 5770 */ + IC_VEX_L_W_XS, /* 5771 */ + IC_VEX_L_W_XD, /* 5772 */ + IC_VEX_L_W_XD, /* 5773 */ + IC_VEX_L_W_XD, /* 5774 */ + IC_VEX_L_W_XD, /* 5775 */ + IC_VEX_L_OPSIZE, /* 5776 */ + IC_VEX_L_OPSIZE, /* 5777 */ + IC_VEX_L_OPSIZE, /* 5778 */ + IC_VEX_L_OPSIZE, /* 5779 */ + IC_VEX_L_OPSIZE, /* 5780 */ + IC_VEX_L_OPSIZE, /* 5781 */ + IC_VEX_L_OPSIZE, /* 5782 */ + IC_VEX_L_OPSIZE, /* 5783 */ + IC_VEX_L_W_OPSIZE, /* 5784 */ + IC_VEX_L_W_OPSIZE, /* 5785 */ + IC_VEX_L_W_OPSIZE, /* 5786 */ + IC_VEX_L_W_OPSIZE, /* 5787 */ + IC_VEX_L_W_OPSIZE, /* 5788 */ + IC_VEX_L_W_OPSIZE, /* 5789 */ + IC_VEX_L_W_OPSIZE, /* 5790 */ + IC_VEX_L_W_OPSIZE, /* 5791 */ + IC_VEX_L, /* 5792 */ + IC_VEX_L, /* 5793 */ + IC_VEX_L_XS, /* 5794 */ + IC_VEX_L_XS, /* 5795 */ + IC_VEX_L_XD, /* 5796 */ + IC_VEX_L_XD, /* 5797 */ + IC_VEX_L_XD, /* 5798 */ + IC_VEX_L_XD, /* 5799 */ + IC_VEX_L_W, /* 5800 */ + IC_VEX_L_W, /* 5801 */ + IC_VEX_L_W_XS, /* 5802 */ + IC_VEX_L_W_XS, /* 5803 */ + IC_VEX_L_W_XD, /* 5804 */ + IC_VEX_L_W_XD, /* 5805 */ + IC_VEX_L_W_XD, /* 5806 */ + IC_VEX_L_W_XD, /* 5807 */ + IC_VEX_L_OPSIZE, /* 5808 */ + IC_VEX_L_OPSIZE, /* 5809 */ + IC_VEX_L_OPSIZE, /* 5810 */ + IC_VEX_L_OPSIZE, /* 5811 */ + IC_VEX_L_OPSIZE, /* 5812 */ + IC_VEX_L_OPSIZE, /* 5813 */ + IC_VEX_L_OPSIZE, /* 5814 */ + IC_VEX_L_OPSIZE, /* 5815 */ + IC_VEX_L_W_OPSIZE, /* 5816 */ + IC_VEX_L_W_OPSIZE, /* 5817 */ + IC_VEX_L_W_OPSIZE, /* 5818 */ + IC_VEX_L_W_OPSIZE, /* 5819 */ + IC_VEX_L_W_OPSIZE, /* 5820 */ + IC_VEX_L_W_OPSIZE, /* 5821 */ + IC_VEX_L_W_OPSIZE, /* 5822 */ + IC_VEX_L_W_OPSIZE, /* 5823 */ + IC_VEX_L, /* 5824 */ + IC_VEX_L, /* 5825 */ + IC_VEX_L_XS, /* 5826 */ + IC_VEX_L_XS, /* 5827 */ + IC_VEX_L_XD, /* 5828 */ + IC_VEX_L_XD, /* 5829 */ + IC_VEX_L_XD, /* 5830 */ + IC_VEX_L_XD, /* 5831 */ + IC_VEX_L_W, /* 5832 */ + IC_VEX_L_W, /* 5833 */ + IC_VEX_L_W_XS, /* 5834 */ + IC_VEX_L_W_XS, /* 5835 */ + IC_VEX_L_W_XD, /* 5836 */ + IC_VEX_L_W_XD, /* 5837 */ + IC_VEX_L_W_XD, /* 5838 */ + IC_VEX_L_W_XD, /* 5839 */ + IC_VEX_L_OPSIZE, /* 5840 */ + IC_VEX_L_OPSIZE, /* 5841 */ + IC_VEX_L_OPSIZE, /* 5842 */ + IC_VEX_L_OPSIZE, /* 5843 */ + IC_VEX_L_OPSIZE, /* 5844 */ + IC_VEX_L_OPSIZE, /* 5845 */ + IC_VEX_L_OPSIZE, /* 5846 */ + IC_VEX_L_OPSIZE, /* 5847 */ + IC_VEX_L_W_OPSIZE, /* 5848 */ + IC_VEX_L_W_OPSIZE, /* 5849 */ + IC_VEX_L_W_OPSIZE, /* 5850 */ + IC_VEX_L_W_OPSIZE, /* 5851 */ + IC_VEX_L_W_OPSIZE, /* 5852 */ + IC_VEX_L_W_OPSIZE, /* 5853 */ + IC_VEX_L_W_OPSIZE, /* 5854 */ + IC_VEX_L_W_OPSIZE, /* 5855 */ + IC_VEX_L, /* 5856 */ + IC_VEX_L, /* 5857 */ + IC_VEX_L_XS, /* 5858 */ + IC_VEX_L_XS, /* 5859 */ + IC_VEX_L_XD, /* 5860 */ + IC_VEX_L_XD, /* 5861 */ + IC_VEX_L_XD, /* 5862 */ + IC_VEX_L_XD, /* 5863 */ + IC_VEX_L_W, /* 5864 */ + IC_VEX_L_W, /* 5865 */ + IC_VEX_L_W_XS, /* 5866 */ + IC_VEX_L_W_XS, /* 5867 */ + IC_VEX_L_W_XD, /* 5868 */ + IC_VEX_L_W_XD, /* 5869 */ + IC_VEX_L_W_XD, /* 5870 */ + IC_VEX_L_W_XD, /* 5871 */ + IC_VEX_L_OPSIZE, /* 5872 */ + IC_VEX_L_OPSIZE, /* 5873 */ + IC_VEX_L_OPSIZE, /* 5874 */ + IC_VEX_L_OPSIZE, /* 5875 */ + IC_VEX_L_OPSIZE, /* 5876 */ + IC_VEX_L_OPSIZE, /* 5877 */ + IC_VEX_L_OPSIZE, /* 5878 */ + IC_VEX_L_OPSIZE, /* 5879 */ + IC_VEX_L_W_OPSIZE, /* 5880 */ + IC_VEX_L_W_OPSIZE, /* 5881 */ + IC_VEX_L_W_OPSIZE, /* 5882 */ + IC_VEX_L_W_OPSIZE, /* 5883 */ + IC_VEX_L_W_OPSIZE, /* 5884 */ + IC_VEX_L_W_OPSIZE, /* 5885 */ + IC_VEX_L_W_OPSIZE, /* 5886 */ + IC_VEX_L_W_OPSIZE, /* 5887 */ + IC_EVEX_L2_KZ, /* 5888 */ + IC_EVEX_L2_KZ, /* 5889 */ + IC_EVEX_L2_XS_KZ, /* 5890 */ + IC_EVEX_L2_XS_KZ, /* 5891 */ + IC_EVEX_L2_XD_KZ, /* 5892 */ + IC_EVEX_L2_XD_KZ, /* 5893 */ + IC_EVEX_L2_XD_KZ, /* 5894 */ + IC_EVEX_L2_XD_KZ, /* 5895 */ + IC_EVEX_L2_W_KZ, /* 5896 */ + IC_EVEX_L2_W_KZ, /* 5897 */ + IC_EVEX_L2_W_XS_KZ, /* 5898 */ + IC_EVEX_L2_W_XS_KZ, /* 5899 */ + IC_EVEX_L2_W_XD_KZ, /* 5900 */ + IC_EVEX_L2_W_XD_KZ, /* 5901 */ + IC_EVEX_L2_W_XD_KZ, /* 5902 */ + IC_EVEX_L2_W_XD_KZ, /* 5903 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5904 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5905 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5906 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5907 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5908 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5909 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5910 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5911 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5912 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5913 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5914 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5915 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5916 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5917 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5918 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5919 */ + IC_EVEX_L2_KZ, /* 5920 */ + IC_EVEX_L2_KZ, /* 5921 */ + IC_EVEX_L2_XS_KZ, /* 5922 */ + IC_EVEX_L2_XS_KZ, /* 5923 */ + IC_EVEX_L2_XD_KZ, /* 5924 */ + IC_EVEX_L2_XD_KZ, /* 5925 */ + IC_EVEX_L2_XD_KZ, /* 5926 */ + IC_EVEX_L2_XD_KZ, /* 5927 */ + IC_EVEX_L2_W_KZ, /* 5928 */ + IC_EVEX_L2_W_KZ, /* 5929 */ + IC_EVEX_L2_W_XS_KZ, /* 5930 */ + IC_EVEX_L2_W_XS_KZ, /* 5931 */ + IC_EVEX_L2_W_XD_KZ, /* 5932 */ + IC_EVEX_L2_W_XD_KZ, /* 5933 */ + IC_EVEX_L2_W_XD_KZ, /* 5934 */ + IC_EVEX_L2_W_XD_KZ, /* 5935 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5936 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5937 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5938 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5939 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5940 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5941 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5942 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5943 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5944 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5945 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5946 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5947 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5948 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5949 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5950 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5951 */ + IC_EVEX_L2_KZ, /* 5952 */ + IC_EVEX_L2_KZ, /* 5953 */ + IC_EVEX_L2_XS_KZ, /* 5954 */ + IC_EVEX_L2_XS_KZ, /* 5955 */ + IC_EVEX_L2_XD_KZ, /* 5956 */ + IC_EVEX_L2_XD_KZ, /* 5957 */ + IC_EVEX_L2_XD_KZ, /* 5958 */ + IC_EVEX_L2_XD_KZ, /* 5959 */ + IC_EVEX_L2_W_KZ, /* 5960 */ + IC_EVEX_L2_W_KZ, /* 5961 */ + IC_EVEX_L2_W_XS_KZ, /* 5962 */ + IC_EVEX_L2_W_XS_KZ, /* 5963 */ + IC_EVEX_L2_W_XD_KZ, /* 5964 */ + IC_EVEX_L2_W_XD_KZ, /* 5965 */ + IC_EVEX_L2_W_XD_KZ, /* 5966 */ + IC_EVEX_L2_W_XD_KZ, /* 5967 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5968 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5969 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5970 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5971 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5972 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5973 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5974 */ + IC_EVEX_L2_OPSIZE_KZ, /* 5975 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5976 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5977 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5978 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5979 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5980 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5981 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5982 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 5983 */ + IC_EVEX_L2_KZ, /* 5984 */ + IC_EVEX_L2_KZ, /* 5985 */ + IC_EVEX_L2_XS_KZ, /* 5986 */ + IC_EVEX_L2_XS_KZ, /* 5987 */ + IC_EVEX_L2_XD_KZ, /* 5988 */ + IC_EVEX_L2_XD_KZ, /* 5989 */ + IC_EVEX_L2_XD_KZ, /* 5990 */ + IC_EVEX_L2_XD_KZ, /* 5991 */ + IC_EVEX_L2_W_KZ, /* 5992 */ + IC_EVEX_L2_W_KZ, /* 5993 */ + IC_EVEX_L2_W_XS_KZ, /* 5994 */ + IC_EVEX_L2_W_XS_KZ, /* 5995 */ + IC_EVEX_L2_W_XD_KZ, /* 5996 */ + IC_EVEX_L2_W_XD_KZ, /* 5997 */ + IC_EVEX_L2_W_XD_KZ, /* 5998 */ + IC_EVEX_L2_W_XD_KZ, /* 5999 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6000 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6001 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6002 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6003 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6004 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6005 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6006 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6007 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6008 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6009 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6010 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6011 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6012 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6013 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6014 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6015 */ + IC_EVEX_L2_KZ, /* 6016 */ + IC_EVEX_L2_KZ, /* 6017 */ + IC_EVEX_L2_XS_KZ, /* 6018 */ + IC_EVEX_L2_XS_KZ, /* 6019 */ + IC_EVEX_L2_XD_KZ, /* 6020 */ + IC_EVEX_L2_XD_KZ, /* 6021 */ + IC_EVEX_L2_XD_KZ, /* 6022 */ + IC_EVEX_L2_XD_KZ, /* 6023 */ + IC_EVEX_L2_W_KZ, /* 6024 */ + IC_EVEX_L2_W_KZ, /* 6025 */ + IC_EVEX_L2_W_XS_KZ, /* 6026 */ + IC_EVEX_L2_W_XS_KZ, /* 6027 */ + IC_EVEX_L2_W_XD_KZ, /* 6028 */ + IC_EVEX_L2_W_XD_KZ, /* 6029 */ + IC_EVEX_L2_W_XD_KZ, /* 6030 */ + IC_EVEX_L2_W_XD_KZ, /* 6031 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6032 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6033 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6034 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6035 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6036 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6037 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6038 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6039 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6040 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6041 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6042 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6043 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6044 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6045 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6046 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6047 */ + IC_EVEX_L2_KZ, /* 6048 */ + IC_EVEX_L2_KZ, /* 6049 */ + IC_EVEX_L2_XS_KZ, /* 6050 */ + IC_EVEX_L2_XS_KZ, /* 6051 */ + IC_EVEX_L2_XD_KZ, /* 6052 */ + IC_EVEX_L2_XD_KZ, /* 6053 */ + IC_EVEX_L2_XD_KZ, /* 6054 */ + IC_EVEX_L2_XD_KZ, /* 6055 */ + IC_EVEX_L2_W_KZ, /* 6056 */ + IC_EVEX_L2_W_KZ, /* 6057 */ + IC_EVEX_L2_W_XS_KZ, /* 6058 */ + IC_EVEX_L2_W_XS_KZ, /* 6059 */ + IC_EVEX_L2_W_XD_KZ, /* 6060 */ + IC_EVEX_L2_W_XD_KZ, /* 6061 */ + IC_EVEX_L2_W_XD_KZ, /* 6062 */ + IC_EVEX_L2_W_XD_KZ, /* 6063 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6064 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6065 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6066 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6067 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6068 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6069 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6070 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6071 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6072 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6073 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6074 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6075 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6076 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6077 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6078 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6079 */ + IC_EVEX_L2_KZ, /* 6080 */ + IC_EVEX_L2_KZ, /* 6081 */ + IC_EVEX_L2_XS_KZ, /* 6082 */ + IC_EVEX_L2_XS_KZ, /* 6083 */ + IC_EVEX_L2_XD_KZ, /* 6084 */ + IC_EVEX_L2_XD_KZ, /* 6085 */ + IC_EVEX_L2_XD_KZ, /* 6086 */ + IC_EVEX_L2_XD_KZ, /* 6087 */ + IC_EVEX_L2_W_KZ, /* 6088 */ + IC_EVEX_L2_W_KZ, /* 6089 */ + IC_EVEX_L2_W_XS_KZ, /* 6090 */ + IC_EVEX_L2_W_XS_KZ, /* 6091 */ + IC_EVEX_L2_W_XD_KZ, /* 6092 */ + IC_EVEX_L2_W_XD_KZ, /* 6093 */ + IC_EVEX_L2_W_XD_KZ, /* 6094 */ + IC_EVEX_L2_W_XD_KZ, /* 6095 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6096 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6097 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6098 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6099 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6100 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6101 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6102 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6103 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6104 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6105 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6106 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6107 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6108 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6109 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6110 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6111 */ + IC_EVEX_L2_KZ, /* 6112 */ + IC_EVEX_L2_KZ, /* 6113 */ + IC_EVEX_L2_XS_KZ, /* 6114 */ + IC_EVEX_L2_XS_KZ, /* 6115 */ + IC_EVEX_L2_XD_KZ, /* 6116 */ + IC_EVEX_L2_XD_KZ, /* 6117 */ + IC_EVEX_L2_XD_KZ, /* 6118 */ + IC_EVEX_L2_XD_KZ, /* 6119 */ + IC_EVEX_L2_W_KZ, /* 6120 */ + IC_EVEX_L2_W_KZ, /* 6121 */ + IC_EVEX_L2_W_XS_KZ, /* 6122 */ + IC_EVEX_L2_W_XS_KZ, /* 6123 */ + IC_EVEX_L2_W_XD_KZ, /* 6124 */ + IC_EVEX_L2_W_XD_KZ, /* 6125 */ + IC_EVEX_L2_W_XD_KZ, /* 6126 */ + IC_EVEX_L2_W_XD_KZ, /* 6127 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6128 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6129 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6130 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6131 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6132 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6133 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6134 */ + IC_EVEX_L2_OPSIZE_KZ, /* 6135 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6136 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6137 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6138 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6139 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6140 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6141 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6142 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 6143 */ + IC, /* 6144 */ + IC_64BIT, /* 6145 */ + IC_XS, /* 6146 */ + IC_64BIT_XS, /* 6147 */ + IC_XD, /* 6148 */ + IC_64BIT_XD, /* 6149 */ + IC_XS, /* 6150 */ + IC_64BIT_XS, /* 6151 */ + IC, /* 6152 */ + IC_64BIT_REXW, /* 6153 */ + IC_XS, /* 6154 */ + IC_64BIT_REXW_XS, /* 6155 */ + IC_XD, /* 6156 */ + IC_64BIT_REXW_XD, /* 6157 */ + IC_XS, /* 6158 */ + IC_64BIT_REXW_XS, /* 6159 */ + IC_OPSIZE, /* 6160 */ + IC_64BIT_OPSIZE, /* 6161 */ + IC_XS_OPSIZE, /* 6162 */ + IC_64BIT_XS_OPSIZE, /* 6163 */ + IC_XD_OPSIZE, /* 6164 */ + IC_64BIT_XD_OPSIZE, /* 6165 */ + IC_XS_OPSIZE, /* 6166 */ + IC_64BIT_XD_OPSIZE, /* 6167 */ + IC_OPSIZE, /* 6168 */ + IC_64BIT_REXW_OPSIZE, /* 6169 */ + IC_XS_OPSIZE, /* 6170 */ + IC_64BIT_REXW_XS, /* 6171 */ + IC_XD_OPSIZE, /* 6172 */ + IC_64BIT_REXW_XD, /* 6173 */ + IC_XS_OPSIZE, /* 6174 */ + IC_64BIT_REXW_XS, /* 6175 */ + IC_ADSIZE, /* 6176 */ + IC_64BIT_ADSIZE, /* 6177 */ + IC_XS_ADSIZE, /* 6178 */ + IC_64BIT_XS_ADSIZE, /* 6179 */ + IC_XD_ADSIZE, /* 6180 */ + IC_64BIT_XD_ADSIZE, /* 6181 */ + IC_XS_ADSIZE, /* 6182 */ + IC_64BIT_XD_ADSIZE, /* 6183 */ + IC_ADSIZE, /* 6184 */ + IC_64BIT_REXW_ADSIZE, /* 6185 */ + IC_XS_ADSIZE, /* 6186 */ + IC_64BIT_REXW_XS, /* 6187 */ + IC_XD_ADSIZE, /* 6188 */ + IC_64BIT_REXW_XD, /* 6189 */ + IC_XS_ADSIZE, /* 6190 */ + IC_64BIT_REXW_XS, /* 6191 */ + IC_OPSIZE_ADSIZE, /* 6192 */ + IC_64BIT_OPSIZE_ADSIZE, /* 6193 */ + IC_XS_OPSIZE, /* 6194 */ + IC_64BIT_XS_OPSIZE, /* 6195 */ + IC_XD_OPSIZE, /* 6196 */ + IC_64BIT_XD_OPSIZE, /* 6197 */ + IC_XS_OPSIZE, /* 6198 */ + IC_64BIT_XD_OPSIZE, /* 6199 */ + IC_OPSIZE_ADSIZE, /* 6200 */ + IC_64BIT_REXW_OPSIZE, /* 6201 */ + IC_XS_OPSIZE, /* 6202 */ + IC_64BIT_REXW_XS, /* 6203 */ + IC_XD_OPSIZE, /* 6204 */ + IC_64BIT_REXW_XD, /* 6205 */ + IC_XS_OPSIZE, /* 6206 */ + IC_64BIT_REXW_XS, /* 6207 */ + IC_VEX, /* 6208 */ + IC_VEX, /* 6209 */ + IC_VEX_XS, /* 6210 */ + IC_VEX_XS, /* 6211 */ + IC_VEX_XD, /* 6212 */ + IC_VEX_XD, /* 6213 */ + IC_VEX_XD, /* 6214 */ + IC_VEX_XD, /* 6215 */ + IC_VEX_W, /* 6216 */ + IC_VEX_W, /* 6217 */ + IC_VEX_W_XS, /* 6218 */ + IC_VEX_W_XS, /* 6219 */ + IC_VEX_W_XD, /* 6220 */ + IC_VEX_W_XD, /* 6221 */ + IC_VEX_W_XD, /* 6222 */ + IC_VEX_W_XD, /* 6223 */ + IC_VEX_OPSIZE, /* 6224 */ + IC_VEX_OPSIZE, /* 6225 */ + IC_VEX_OPSIZE, /* 6226 */ + IC_VEX_OPSIZE, /* 6227 */ + IC_VEX_OPSIZE, /* 6228 */ + IC_VEX_OPSIZE, /* 6229 */ + IC_VEX_OPSIZE, /* 6230 */ + IC_VEX_OPSIZE, /* 6231 */ + IC_VEX_W_OPSIZE, /* 6232 */ + IC_VEX_W_OPSIZE, /* 6233 */ + IC_VEX_W_OPSIZE, /* 6234 */ + IC_VEX_W_OPSIZE, /* 6235 */ + IC_VEX_W_OPSIZE, /* 6236 */ + IC_VEX_W_OPSIZE, /* 6237 */ + IC_VEX_W_OPSIZE, /* 6238 */ + IC_VEX_W_OPSIZE, /* 6239 */ + IC_VEX, /* 6240 */ + IC_VEX, /* 6241 */ + IC_VEX_XS, /* 6242 */ + IC_VEX_XS, /* 6243 */ + IC_VEX_XD, /* 6244 */ + IC_VEX_XD, /* 6245 */ + IC_VEX_XD, /* 6246 */ + IC_VEX_XD, /* 6247 */ + IC_VEX_W, /* 6248 */ + IC_VEX_W, /* 6249 */ + IC_VEX_W_XS, /* 6250 */ + IC_VEX_W_XS, /* 6251 */ + IC_VEX_W_XD, /* 6252 */ + IC_VEX_W_XD, /* 6253 */ + IC_VEX_W_XD, /* 6254 */ + IC_VEX_W_XD, /* 6255 */ + IC_VEX_OPSIZE, /* 6256 */ + IC_VEX_OPSIZE, /* 6257 */ + IC_VEX_OPSIZE, /* 6258 */ + IC_VEX_OPSIZE, /* 6259 */ + IC_VEX_OPSIZE, /* 6260 */ + IC_VEX_OPSIZE, /* 6261 */ + IC_VEX_OPSIZE, /* 6262 */ + IC_VEX_OPSIZE, /* 6263 */ + IC_VEX_W_OPSIZE, /* 6264 */ + IC_VEX_W_OPSIZE, /* 6265 */ + IC_VEX_W_OPSIZE, /* 6266 */ + IC_VEX_W_OPSIZE, /* 6267 */ + IC_VEX_W_OPSIZE, /* 6268 */ + IC_VEX_W_OPSIZE, /* 6269 */ + IC_VEX_W_OPSIZE, /* 6270 */ + IC_VEX_W_OPSIZE, /* 6271 */ + IC_VEX_L, /* 6272 */ + IC_VEX_L, /* 6273 */ + IC_VEX_L_XS, /* 6274 */ + IC_VEX_L_XS, /* 6275 */ + IC_VEX_L_XD, /* 6276 */ + IC_VEX_L_XD, /* 6277 */ + IC_VEX_L_XD, /* 6278 */ + IC_VEX_L_XD, /* 6279 */ + IC_VEX_L_W, /* 6280 */ + IC_VEX_L_W, /* 6281 */ + IC_VEX_L_W_XS, /* 6282 */ + IC_VEX_L_W_XS, /* 6283 */ + IC_VEX_L_W_XD, /* 6284 */ + IC_VEX_L_W_XD, /* 6285 */ + IC_VEX_L_W_XD, /* 6286 */ + IC_VEX_L_W_XD, /* 6287 */ + IC_VEX_L_OPSIZE, /* 6288 */ + IC_VEX_L_OPSIZE, /* 6289 */ + IC_VEX_L_OPSIZE, /* 6290 */ + IC_VEX_L_OPSIZE, /* 6291 */ + IC_VEX_L_OPSIZE, /* 6292 */ + IC_VEX_L_OPSIZE, /* 6293 */ + IC_VEX_L_OPSIZE, /* 6294 */ + IC_VEX_L_OPSIZE, /* 6295 */ + IC_VEX_L_W_OPSIZE, /* 6296 */ + IC_VEX_L_W_OPSIZE, /* 6297 */ + IC_VEX_L_W_OPSIZE, /* 6298 */ + IC_VEX_L_W_OPSIZE, /* 6299 */ + IC_VEX_L_W_OPSIZE, /* 6300 */ + IC_VEX_L_W_OPSIZE, /* 6301 */ + IC_VEX_L_W_OPSIZE, /* 6302 */ + IC_VEX_L_W_OPSIZE, /* 6303 */ + IC_VEX_L, /* 6304 */ + IC_VEX_L, /* 6305 */ + IC_VEX_L_XS, /* 6306 */ + IC_VEX_L_XS, /* 6307 */ + IC_VEX_L_XD, /* 6308 */ + IC_VEX_L_XD, /* 6309 */ + IC_VEX_L_XD, /* 6310 */ + IC_VEX_L_XD, /* 6311 */ + IC_VEX_L_W, /* 6312 */ + IC_VEX_L_W, /* 6313 */ + IC_VEX_L_W_XS, /* 6314 */ + IC_VEX_L_W_XS, /* 6315 */ + IC_VEX_L_W_XD, /* 6316 */ + IC_VEX_L_W_XD, /* 6317 */ + IC_VEX_L_W_XD, /* 6318 */ + IC_VEX_L_W_XD, /* 6319 */ + IC_VEX_L_OPSIZE, /* 6320 */ + IC_VEX_L_OPSIZE, /* 6321 */ + IC_VEX_L_OPSIZE, /* 6322 */ + IC_VEX_L_OPSIZE, /* 6323 */ + IC_VEX_L_OPSIZE, /* 6324 */ + IC_VEX_L_OPSIZE, /* 6325 */ + IC_VEX_L_OPSIZE, /* 6326 */ + IC_VEX_L_OPSIZE, /* 6327 */ + IC_VEX_L_W_OPSIZE, /* 6328 */ + IC_VEX_L_W_OPSIZE, /* 6329 */ + IC_VEX_L_W_OPSIZE, /* 6330 */ + IC_VEX_L_W_OPSIZE, /* 6331 */ + IC_VEX_L_W_OPSIZE, /* 6332 */ + IC_VEX_L_W_OPSIZE, /* 6333 */ + IC_VEX_L_W_OPSIZE, /* 6334 */ + IC_VEX_L_W_OPSIZE, /* 6335 */ + IC_VEX_L, /* 6336 */ + IC_VEX_L, /* 6337 */ + IC_VEX_L_XS, /* 6338 */ + IC_VEX_L_XS, /* 6339 */ + IC_VEX_L_XD, /* 6340 */ + IC_VEX_L_XD, /* 6341 */ + IC_VEX_L_XD, /* 6342 */ + IC_VEX_L_XD, /* 6343 */ + IC_VEX_L_W, /* 6344 */ + IC_VEX_L_W, /* 6345 */ + IC_VEX_L_W_XS, /* 6346 */ + IC_VEX_L_W_XS, /* 6347 */ + IC_VEX_L_W_XD, /* 6348 */ + IC_VEX_L_W_XD, /* 6349 */ + IC_VEX_L_W_XD, /* 6350 */ + IC_VEX_L_W_XD, /* 6351 */ + IC_VEX_L_OPSIZE, /* 6352 */ + IC_VEX_L_OPSIZE, /* 6353 */ + IC_VEX_L_OPSIZE, /* 6354 */ + IC_VEX_L_OPSIZE, /* 6355 */ + IC_VEX_L_OPSIZE, /* 6356 */ + IC_VEX_L_OPSIZE, /* 6357 */ + IC_VEX_L_OPSIZE, /* 6358 */ + IC_VEX_L_OPSIZE, /* 6359 */ + IC_VEX_L_W_OPSIZE, /* 6360 */ + IC_VEX_L_W_OPSIZE, /* 6361 */ + IC_VEX_L_W_OPSIZE, /* 6362 */ + IC_VEX_L_W_OPSIZE, /* 6363 */ + IC_VEX_L_W_OPSIZE, /* 6364 */ + IC_VEX_L_W_OPSIZE, /* 6365 */ + IC_VEX_L_W_OPSIZE, /* 6366 */ + IC_VEX_L_W_OPSIZE, /* 6367 */ + IC_VEX_L, /* 6368 */ + IC_VEX_L, /* 6369 */ + IC_VEX_L_XS, /* 6370 */ + IC_VEX_L_XS, /* 6371 */ + IC_VEX_L_XD, /* 6372 */ + IC_VEX_L_XD, /* 6373 */ + IC_VEX_L_XD, /* 6374 */ + IC_VEX_L_XD, /* 6375 */ + IC_VEX_L_W, /* 6376 */ + IC_VEX_L_W, /* 6377 */ + IC_VEX_L_W_XS, /* 6378 */ + IC_VEX_L_W_XS, /* 6379 */ + IC_VEX_L_W_XD, /* 6380 */ + IC_VEX_L_W_XD, /* 6381 */ + IC_VEX_L_W_XD, /* 6382 */ + IC_VEX_L_W_XD, /* 6383 */ + IC_VEX_L_OPSIZE, /* 6384 */ + IC_VEX_L_OPSIZE, /* 6385 */ + IC_VEX_L_OPSIZE, /* 6386 */ + IC_VEX_L_OPSIZE, /* 6387 */ + IC_VEX_L_OPSIZE, /* 6388 */ + IC_VEX_L_OPSIZE, /* 6389 */ + IC_VEX_L_OPSIZE, /* 6390 */ + IC_VEX_L_OPSIZE, /* 6391 */ + IC_VEX_L_W_OPSIZE, /* 6392 */ + IC_VEX_L_W_OPSIZE, /* 6393 */ + IC_VEX_L_W_OPSIZE, /* 6394 */ + IC_VEX_L_W_OPSIZE, /* 6395 */ + IC_VEX_L_W_OPSIZE, /* 6396 */ + IC_VEX_L_W_OPSIZE, /* 6397 */ + IC_VEX_L_W_OPSIZE, /* 6398 */ + IC_VEX_L_W_OPSIZE, /* 6399 */ + IC_EVEX_KZ, /* 6400 */ + IC_EVEX_KZ, /* 6401 */ + IC_EVEX_XS_KZ, /* 6402 */ + IC_EVEX_XS_KZ, /* 6403 */ + IC_EVEX_XD_KZ, /* 6404 */ + IC_EVEX_XD_KZ, /* 6405 */ + IC_EVEX_XD_KZ, /* 6406 */ + IC_EVEX_XD_KZ, /* 6407 */ + IC_EVEX_W_KZ, /* 6408 */ + IC_EVEX_W_KZ, /* 6409 */ + IC_EVEX_W_XS_KZ, /* 6410 */ + IC_EVEX_W_XS_KZ, /* 6411 */ + IC_EVEX_W_XD_KZ, /* 6412 */ + IC_EVEX_W_XD_KZ, /* 6413 */ + IC_EVEX_W_XD_KZ, /* 6414 */ + IC_EVEX_W_XD_KZ, /* 6415 */ + IC_EVEX_OPSIZE_KZ, /* 6416 */ + IC_EVEX_OPSIZE_KZ, /* 6417 */ + IC_EVEX_OPSIZE_KZ, /* 6418 */ + IC_EVEX_OPSIZE_KZ, /* 6419 */ + IC_EVEX_OPSIZE_KZ, /* 6420 */ + IC_EVEX_OPSIZE_KZ, /* 6421 */ + IC_EVEX_OPSIZE_KZ, /* 6422 */ + IC_EVEX_OPSIZE_KZ, /* 6423 */ + IC_EVEX_W_OPSIZE_KZ, /* 6424 */ + IC_EVEX_W_OPSIZE_KZ, /* 6425 */ + IC_EVEX_W_OPSIZE_KZ, /* 6426 */ + IC_EVEX_W_OPSIZE_KZ, /* 6427 */ + IC_EVEX_W_OPSIZE_KZ, /* 6428 */ + IC_EVEX_W_OPSIZE_KZ, /* 6429 */ + IC_EVEX_W_OPSIZE_KZ, /* 6430 */ + IC_EVEX_W_OPSIZE_KZ, /* 6431 */ + IC_EVEX_KZ, /* 6432 */ + IC_EVEX_KZ, /* 6433 */ + IC_EVEX_XS_KZ, /* 6434 */ + IC_EVEX_XS_KZ, /* 6435 */ + IC_EVEX_XD_KZ, /* 6436 */ + IC_EVEX_XD_KZ, /* 6437 */ + IC_EVEX_XD_KZ, /* 6438 */ + IC_EVEX_XD_KZ, /* 6439 */ + IC_EVEX_W_KZ, /* 6440 */ + IC_EVEX_W_KZ, /* 6441 */ + IC_EVEX_W_XS_KZ, /* 6442 */ + IC_EVEX_W_XS_KZ, /* 6443 */ + IC_EVEX_W_XD_KZ, /* 6444 */ + IC_EVEX_W_XD_KZ, /* 6445 */ + IC_EVEX_W_XD_KZ, /* 6446 */ + IC_EVEX_W_XD_KZ, /* 6447 */ + IC_EVEX_OPSIZE_KZ, /* 6448 */ + IC_EVEX_OPSIZE_KZ, /* 6449 */ + IC_EVEX_OPSIZE_KZ, /* 6450 */ + IC_EVEX_OPSIZE_KZ, /* 6451 */ + IC_EVEX_OPSIZE_KZ, /* 6452 */ + IC_EVEX_OPSIZE_KZ, /* 6453 */ + IC_EVEX_OPSIZE_KZ, /* 6454 */ + IC_EVEX_OPSIZE_KZ, /* 6455 */ + IC_EVEX_W_OPSIZE_KZ, /* 6456 */ + IC_EVEX_W_OPSIZE_KZ, /* 6457 */ + IC_EVEX_W_OPSIZE_KZ, /* 6458 */ + IC_EVEX_W_OPSIZE_KZ, /* 6459 */ + IC_EVEX_W_OPSIZE_KZ, /* 6460 */ + IC_EVEX_W_OPSIZE_KZ, /* 6461 */ + IC_EVEX_W_OPSIZE_KZ, /* 6462 */ + IC_EVEX_W_OPSIZE_KZ, /* 6463 */ + IC_EVEX_KZ, /* 6464 */ + IC_EVEX_KZ, /* 6465 */ + IC_EVEX_XS_KZ, /* 6466 */ + IC_EVEX_XS_KZ, /* 6467 */ + IC_EVEX_XD_KZ, /* 6468 */ + IC_EVEX_XD_KZ, /* 6469 */ + IC_EVEX_XD_KZ, /* 6470 */ + IC_EVEX_XD_KZ, /* 6471 */ + IC_EVEX_W_KZ, /* 6472 */ + IC_EVEX_W_KZ, /* 6473 */ + IC_EVEX_W_XS_KZ, /* 6474 */ + IC_EVEX_W_XS_KZ, /* 6475 */ + IC_EVEX_W_XD_KZ, /* 6476 */ + IC_EVEX_W_XD_KZ, /* 6477 */ + IC_EVEX_W_XD_KZ, /* 6478 */ + IC_EVEX_W_XD_KZ, /* 6479 */ + IC_EVEX_OPSIZE_KZ, /* 6480 */ + IC_EVEX_OPSIZE_KZ, /* 6481 */ + IC_EVEX_OPSIZE_KZ, /* 6482 */ + IC_EVEX_OPSIZE_KZ, /* 6483 */ + IC_EVEX_OPSIZE_KZ, /* 6484 */ + IC_EVEX_OPSIZE_KZ, /* 6485 */ + IC_EVEX_OPSIZE_KZ, /* 6486 */ + IC_EVEX_OPSIZE_KZ, /* 6487 */ + IC_EVEX_W_OPSIZE_KZ, /* 6488 */ + IC_EVEX_W_OPSIZE_KZ, /* 6489 */ + IC_EVEX_W_OPSIZE_KZ, /* 6490 */ + IC_EVEX_W_OPSIZE_KZ, /* 6491 */ + IC_EVEX_W_OPSIZE_KZ, /* 6492 */ + IC_EVEX_W_OPSIZE_KZ, /* 6493 */ + IC_EVEX_W_OPSIZE_KZ, /* 6494 */ + IC_EVEX_W_OPSIZE_KZ, /* 6495 */ + IC_EVEX_KZ, /* 6496 */ + IC_EVEX_KZ, /* 6497 */ + IC_EVEX_XS_KZ, /* 6498 */ + IC_EVEX_XS_KZ, /* 6499 */ + IC_EVEX_XD_KZ, /* 6500 */ + IC_EVEX_XD_KZ, /* 6501 */ + IC_EVEX_XD_KZ, /* 6502 */ + IC_EVEX_XD_KZ, /* 6503 */ + IC_EVEX_W_KZ, /* 6504 */ + IC_EVEX_W_KZ, /* 6505 */ + IC_EVEX_W_XS_KZ, /* 6506 */ + IC_EVEX_W_XS_KZ, /* 6507 */ + IC_EVEX_W_XD_KZ, /* 6508 */ + IC_EVEX_W_XD_KZ, /* 6509 */ + IC_EVEX_W_XD_KZ, /* 6510 */ + IC_EVEX_W_XD_KZ, /* 6511 */ + IC_EVEX_OPSIZE_KZ, /* 6512 */ + IC_EVEX_OPSIZE_KZ, /* 6513 */ + IC_EVEX_OPSIZE_KZ, /* 6514 */ + IC_EVEX_OPSIZE_KZ, /* 6515 */ + IC_EVEX_OPSIZE_KZ, /* 6516 */ + IC_EVEX_OPSIZE_KZ, /* 6517 */ + IC_EVEX_OPSIZE_KZ, /* 6518 */ + IC_EVEX_OPSIZE_KZ, /* 6519 */ + IC_EVEX_W_OPSIZE_KZ, /* 6520 */ + IC_EVEX_W_OPSIZE_KZ, /* 6521 */ + IC_EVEX_W_OPSIZE_KZ, /* 6522 */ + IC_EVEX_W_OPSIZE_KZ, /* 6523 */ + IC_EVEX_W_OPSIZE_KZ, /* 6524 */ + IC_EVEX_W_OPSIZE_KZ, /* 6525 */ + IC_EVEX_W_OPSIZE_KZ, /* 6526 */ + IC_EVEX_W_OPSIZE_KZ, /* 6527 */ + IC_EVEX_KZ, /* 6528 */ + IC_EVEX_KZ, /* 6529 */ + IC_EVEX_XS_KZ, /* 6530 */ + IC_EVEX_XS_KZ, /* 6531 */ + IC_EVEX_XD_KZ, /* 6532 */ + IC_EVEX_XD_KZ, /* 6533 */ + IC_EVEX_XD_KZ, /* 6534 */ + IC_EVEX_XD_KZ, /* 6535 */ + IC_EVEX_W_KZ, /* 6536 */ + IC_EVEX_W_KZ, /* 6537 */ + IC_EVEX_W_XS_KZ, /* 6538 */ + IC_EVEX_W_XS_KZ, /* 6539 */ + IC_EVEX_W_XD_KZ, /* 6540 */ + IC_EVEX_W_XD_KZ, /* 6541 */ + IC_EVEX_W_XD_KZ, /* 6542 */ + IC_EVEX_W_XD_KZ, /* 6543 */ + IC_EVEX_OPSIZE_KZ, /* 6544 */ + IC_EVEX_OPSIZE_KZ, /* 6545 */ + IC_EVEX_OPSIZE_KZ, /* 6546 */ + IC_EVEX_OPSIZE_KZ, /* 6547 */ + IC_EVEX_OPSIZE_KZ, /* 6548 */ + IC_EVEX_OPSIZE_KZ, /* 6549 */ + IC_EVEX_OPSIZE_KZ, /* 6550 */ + IC_EVEX_OPSIZE_KZ, /* 6551 */ + IC_EVEX_W_OPSIZE_KZ, /* 6552 */ + IC_EVEX_W_OPSIZE_KZ, /* 6553 */ + IC_EVEX_W_OPSIZE_KZ, /* 6554 */ + IC_EVEX_W_OPSIZE_KZ, /* 6555 */ + IC_EVEX_W_OPSIZE_KZ, /* 6556 */ + IC_EVEX_W_OPSIZE_KZ, /* 6557 */ + IC_EVEX_W_OPSIZE_KZ, /* 6558 */ + IC_EVEX_W_OPSIZE_KZ, /* 6559 */ + IC_EVEX_KZ, /* 6560 */ + IC_EVEX_KZ, /* 6561 */ + IC_EVEX_XS_KZ, /* 6562 */ + IC_EVEX_XS_KZ, /* 6563 */ + IC_EVEX_XD_KZ, /* 6564 */ + IC_EVEX_XD_KZ, /* 6565 */ + IC_EVEX_XD_KZ, /* 6566 */ + IC_EVEX_XD_KZ, /* 6567 */ + IC_EVEX_W_KZ, /* 6568 */ + IC_EVEX_W_KZ, /* 6569 */ + IC_EVEX_W_XS_KZ, /* 6570 */ + IC_EVEX_W_XS_KZ, /* 6571 */ + IC_EVEX_W_XD_KZ, /* 6572 */ + IC_EVEX_W_XD_KZ, /* 6573 */ + IC_EVEX_W_XD_KZ, /* 6574 */ + IC_EVEX_W_XD_KZ, /* 6575 */ + IC_EVEX_OPSIZE_KZ, /* 6576 */ + IC_EVEX_OPSIZE_KZ, /* 6577 */ + IC_EVEX_OPSIZE_KZ, /* 6578 */ + IC_EVEX_OPSIZE_KZ, /* 6579 */ + IC_EVEX_OPSIZE_KZ, /* 6580 */ + IC_EVEX_OPSIZE_KZ, /* 6581 */ + IC_EVEX_OPSIZE_KZ, /* 6582 */ + IC_EVEX_OPSIZE_KZ, /* 6583 */ + IC_EVEX_W_OPSIZE_KZ, /* 6584 */ + IC_EVEX_W_OPSIZE_KZ, /* 6585 */ + IC_EVEX_W_OPSIZE_KZ, /* 6586 */ + IC_EVEX_W_OPSIZE_KZ, /* 6587 */ + IC_EVEX_W_OPSIZE_KZ, /* 6588 */ + IC_EVEX_W_OPSIZE_KZ, /* 6589 */ + IC_EVEX_W_OPSIZE_KZ, /* 6590 */ + IC_EVEX_W_OPSIZE_KZ, /* 6591 */ + IC_EVEX_KZ, /* 6592 */ + IC_EVEX_KZ, /* 6593 */ + IC_EVEX_XS_KZ, /* 6594 */ + IC_EVEX_XS_KZ, /* 6595 */ + IC_EVEX_XD_KZ, /* 6596 */ + IC_EVEX_XD_KZ, /* 6597 */ + IC_EVEX_XD_KZ, /* 6598 */ + IC_EVEX_XD_KZ, /* 6599 */ + IC_EVEX_W_KZ, /* 6600 */ + IC_EVEX_W_KZ, /* 6601 */ + IC_EVEX_W_XS_KZ, /* 6602 */ + IC_EVEX_W_XS_KZ, /* 6603 */ + IC_EVEX_W_XD_KZ, /* 6604 */ + IC_EVEX_W_XD_KZ, /* 6605 */ + IC_EVEX_W_XD_KZ, /* 6606 */ + IC_EVEX_W_XD_KZ, /* 6607 */ + IC_EVEX_OPSIZE_KZ, /* 6608 */ + IC_EVEX_OPSIZE_KZ, /* 6609 */ + IC_EVEX_OPSIZE_KZ, /* 6610 */ + IC_EVEX_OPSIZE_KZ, /* 6611 */ + IC_EVEX_OPSIZE_KZ, /* 6612 */ + IC_EVEX_OPSIZE_KZ, /* 6613 */ + IC_EVEX_OPSIZE_KZ, /* 6614 */ + IC_EVEX_OPSIZE_KZ, /* 6615 */ + IC_EVEX_W_OPSIZE_KZ, /* 6616 */ + IC_EVEX_W_OPSIZE_KZ, /* 6617 */ + IC_EVEX_W_OPSIZE_KZ, /* 6618 */ + IC_EVEX_W_OPSIZE_KZ, /* 6619 */ + IC_EVEX_W_OPSIZE_KZ, /* 6620 */ + IC_EVEX_W_OPSIZE_KZ, /* 6621 */ + IC_EVEX_W_OPSIZE_KZ, /* 6622 */ + IC_EVEX_W_OPSIZE_KZ, /* 6623 */ + IC_EVEX_KZ, /* 6624 */ + IC_EVEX_KZ, /* 6625 */ + IC_EVEX_XS_KZ, /* 6626 */ + IC_EVEX_XS_KZ, /* 6627 */ + IC_EVEX_XD_KZ, /* 6628 */ + IC_EVEX_XD_KZ, /* 6629 */ + IC_EVEX_XD_KZ, /* 6630 */ + IC_EVEX_XD_KZ, /* 6631 */ + IC_EVEX_W_KZ, /* 6632 */ + IC_EVEX_W_KZ, /* 6633 */ + IC_EVEX_W_XS_KZ, /* 6634 */ + IC_EVEX_W_XS_KZ, /* 6635 */ + IC_EVEX_W_XD_KZ, /* 6636 */ + IC_EVEX_W_XD_KZ, /* 6637 */ + IC_EVEX_W_XD_KZ, /* 6638 */ + IC_EVEX_W_XD_KZ, /* 6639 */ + IC_EVEX_OPSIZE_KZ, /* 6640 */ + IC_EVEX_OPSIZE_KZ, /* 6641 */ + IC_EVEX_OPSIZE_KZ, /* 6642 */ + IC_EVEX_OPSIZE_KZ, /* 6643 */ + IC_EVEX_OPSIZE_KZ, /* 6644 */ + IC_EVEX_OPSIZE_KZ, /* 6645 */ + IC_EVEX_OPSIZE_KZ, /* 6646 */ + IC_EVEX_OPSIZE_KZ, /* 6647 */ + IC_EVEX_W_OPSIZE_KZ, /* 6648 */ + IC_EVEX_W_OPSIZE_KZ, /* 6649 */ + IC_EVEX_W_OPSIZE_KZ, /* 6650 */ + IC_EVEX_W_OPSIZE_KZ, /* 6651 */ + IC_EVEX_W_OPSIZE_KZ, /* 6652 */ + IC_EVEX_W_OPSIZE_KZ, /* 6653 */ + IC_EVEX_W_OPSIZE_KZ, /* 6654 */ + IC_EVEX_W_OPSIZE_KZ, /* 6655 */ + IC, /* 6656 */ + IC_64BIT, /* 6657 */ + IC_XS, /* 6658 */ + IC_64BIT_XS, /* 6659 */ + IC_XD, /* 6660 */ + IC_64BIT_XD, /* 6661 */ + IC_XS, /* 6662 */ + IC_64BIT_XS, /* 6663 */ + IC, /* 6664 */ + IC_64BIT_REXW, /* 6665 */ + IC_XS, /* 6666 */ + IC_64BIT_REXW_XS, /* 6667 */ + IC_XD, /* 6668 */ + IC_64BIT_REXW_XD, /* 6669 */ + IC_XS, /* 6670 */ + IC_64BIT_REXW_XS, /* 6671 */ + IC_OPSIZE, /* 6672 */ + IC_64BIT_OPSIZE, /* 6673 */ + IC_XS_OPSIZE, /* 6674 */ + IC_64BIT_XS_OPSIZE, /* 6675 */ + IC_XD_OPSIZE, /* 6676 */ + IC_64BIT_XD_OPSIZE, /* 6677 */ + IC_XS_OPSIZE, /* 6678 */ + IC_64BIT_XD_OPSIZE, /* 6679 */ + IC_OPSIZE, /* 6680 */ + IC_64BIT_REXW_OPSIZE, /* 6681 */ + IC_XS_OPSIZE, /* 6682 */ + IC_64BIT_REXW_XS, /* 6683 */ + IC_XD_OPSIZE, /* 6684 */ + IC_64BIT_REXW_XD, /* 6685 */ + IC_XS_OPSIZE, /* 6686 */ + IC_64BIT_REXW_XS, /* 6687 */ + IC_ADSIZE, /* 6688 */ + IC_64BIT_ADSIZE, /* 6689 */ + IC_XS_ADSIZE, /* 6690 */ + IC_64BIT_XS_ADSIZE, /* 6691 */ + IC_XD_ADSIZE, /* 6692 */ + IC_64BIT_XD_ADSIZE, /* 6693 */ + IC_XS_ADSIZE, /* 6694 */ + IC_64BIT_XD_ADSIZE, /* 6695 */ + IC_ADSIZE, /* 6696 */ + IC_64BIT_REXW_ADSIZE, /* 6697 */ + IC_XS_ADSIZE, /* 6698 */ + IC_64BIT_REXW_XS, /* 6699 */ + IC_XD_ADSIZE, /* 6700 */ + IC_64BIT_REXW_XD, /* 6701 */ + IC_XS_ADSIZE, /* 6702 */ + IC_64BIT_REXW_XS, /* 6703 */ + IC_OPSIZE_ADSIZE, /* 6704 */ + IC_64BIT_OPSIZE_ADSIZE, /* 6705 */ + IC_XS_OPSIZE, /* 6706 */ + IC_64BIT_XS_OPSIZE, /* 6707 */ + IC_XD_OPSIZE, /* 6708 */ + IC_64BIT_XD_OPSIZE, /* 6709 */ + IC_XS_OPSIZE, /* 6710 */ + IC_64BIT_XD_OPSIZE, /* 6711 */ + IC_OPSIZE_ADSIZE, /* 6712 */ + IC_64BIT_REXW_OPSIZE, /* 6713 */ + IC_XS_OPSIZE, /* 6714 */ + IC_64BIT_REXW_XS, /* 6715 */ + IC_XD_OPSIZE, /* 6716 */ + IC_64BIT_REXW_XD, /* 6717 */ + IC_XS_OPSIZE, /* 6718 */ + IC_64BIT_REXW_XS, /* 6719 */ + IC_VEX, /* 6720 */ + IC_VEX, /* 6721 */ + IC_VEX_XS, /* 6722 */ + IC_VEX_XS, /* 6723 */ + IC_VEX_XD, /* 6724 */ + IC_VEX_XD, /* 6725 */ + IC_VEX_XD, /* 6726 */ + IC_VEX_XD, /* 6727 */ + IC_VEX_W, /* 6728 */ + IC_VEX_W, /* 6729 */ + IC_VEX_W_XS, /* 6730 */ + IC_VEX_W_XS, /* 6731 */ + IC_VEX_W_XD, /* 6732 */ + IC_VEX_W_XD, /* 6733 */ + IC_VEX_W_XD, /* 6734 */ + IC_VEX_W_XD, /* 6735 */ + IC_VEX_OPSIZE, /* 6736 */ + IC_VEX_OPSIZE, /* 6737 */ + IC_VEX_OPSIZE, /* 6738 */ + IC_VEX_OPSIZE, /* 6739 */ + IC_VEX_OPSIZE, /* 6740 */ + IC_VEX_OPSIZE, /* 6741 */ + IC_VEX_OPSIZE, /* 6742 */ + IC_VEX_OPSIZE, /* 6743 */ + IC_VEX_W_OPSIZE, /* 6744 */ + IC_VEX_W_OPSIZE, /* 6745 */ + IC_VEX_W_OPSIZE, /* 6746 */ + IC_VEX_W_OPSIZE, /* 6747 */ + IC_VEX_W_OPSIZE, /* 6748 */ + IC_VEX_W_OPSIZE, /* 6749 */ + IC_VEX_W_OPSIZE, /* 6750 */ + IC_VEX_W_OPSIZE, /* 6751 */ + IC_VEX, /* 6752 */ + IC_VEX, /* 6753 */ + IC_VEX_XS, /* 6754 */ + IC_VEX_XS, /* 6755 */ + IC_VEX_XD, /* 6756 */ + IC_VEX_XD, /* 6757 */ + IC_VEX_XD, /* 6758 */ + IC_VEX_XD, /* 6759 */ + IC_VEX_W, /* 6760 */ + IC_VEX_W, /* 6761 */ + IC_VEX_W_XS, /* 6762 */ + IC_VEX_W_XS, /* 6763 */ + IC_VEX_W_XD, /* 6764 */ + IC_VEX_W_XD, /* 6765 */ + IC_VEX_W_XD, /* 6766 */ + IC_VEX_W_XD, /* 6767 */ + IC_VEX_OPSIZE, /* 6768 */ + IC_VEX_OPSIZE, /* 6769 */ + IC_VEX_OPSIZE, /* 6770 */ + IC_VEX_OPSIZE, /* 6771 */ + IC_VEX_OPSIZE, /* 6772 */ + IC_VEX_OPSIZE, /* 6773 */ + IC_VEX_OPSIZE, /* 6774 */ + IC_VEX_OPSIZE, /* 6775 */ + IC_VEX_W_OPSIZE, /* 6776 */ + IC_VEX_W_OPSIZE, /* 6777 */ + IC_VEX_W_OPSIZE, /* 6778 */ + IC_VEX_W_OPSIZE, /* 6779 */ + IC_VEX_W_OPSIZE, /* 6780 */ + IC_VEX_W_OPSIZE, /* 6781 */ + IC_VEX_W_OPSIZE, /* 6782 */ + IC_VEX_W_OPSIZE, /* 6783 */ + IC_VEX_L, /* 6784 */ + IC_VEX_L, /* 6785 */ + IC_VEX_L_XS, /* 6786 */ + IC_VEX_L_XS, /* 6787 */ + IC_VEX_L_XD, /* 6788 */ + IC_VEX_L_XD, /* 6789 */ + IC_VEX_L_XD, /* 6790 */ + IC_VEX_L_XD, /* 6791 */ + IC_VEX_L_W, /* 6792 */ + IC_VEX_L_W, /* 6793 */ + IC_VEX_L_W_XS, /* 6794 */ + IC_VEX_L_W_XS, /* 6795 */ + IC_VEX_L_W_XD, /* 6796 */ + IC_VEX_L_W_XD, /* 6797 */ + IC_VEX_L_W_XD, /* 6798 */ + IC_VEX_L_W_XD, /* 6799 */ + IC_VEX_L_OPSIZE, /* 6800 */ + IC_VEX_L_OPSIZE, /* 6801 */ + IC_VEX_L_OPSIZE, /* 6802 */ + IC_VEX_L_OPSIZE, /* 6803 */ + IC_VEX_L_OPSIZE, /* 6804 */ + IC_VEX_L_OPSIZE, /* 6805 */ + IC_VEX_L_OPSIZE, /* 6806 */ + IC_VEX_L_OPSIZE, /* 6807 */ + IC_VEX_L_W_OPSIZE, /* 6808 */ + IC_VEX_L_W_OPSIZE, /* 6809 */ + IC_VEX_L_W_OPSIZE, /* 6810 */ + IC_VEX_L_W_OPSIZE, /* 6811 */ + IC_VEX_L_W_OPSIZE, /* 6812 */ + IC_VEX_L_W_OPSIZE, /* 6813 */ + IC_VEX_L_W_OPSIZE, /* 6814 */ + IC_VEX_L_W_OPSIZE, /* 6815 */ + IC_VEX_L, /* 6816 */ + IC_VEX_L, /* 6817 */ + IC_VEX_L_XS, /* 6818 */ + IC_VEX_L_XS, /* 6819 */ + IC_VEX_L_XD, /* 6820 */ + IC_VEX_L_XD, /* 6821 */ + IC_VEX_L_XD, /* 6822 */ + IC_VEX_L_XD, /* 6823 */ + IC_VEX_L_W, /* 6824 */ + IC_VEX_L_W, /* 6825 */ + IC_VEX_L_W_XS, /* 6826 */ + IC_VEX_L_W_XS, /* 6827 */ + IC_VEX_L_W_XD, /* 6828 */ + IC_VEX_L_W_XD, /* 6829 */ + IC_VEX_L_W_XD, /* 6830 */ + IC_VEX_L_W_XD, /* 6831 */ + IC_VEX_L_OPSIZE, /* 6832 */ + IC_VEX_L_OPSIZE, /* 6833 */ + IC_VEX_L_OPSIZE, /* 6834 */ + IC_VEX_L_OPSIZE, /* 6835 */ + IC_VEX_L_OPSIZE, /* 6836 */ + IC_VEX_L_OPSIZE, /* 6837 */ + IC_VEX_L_OPSIZE, /* 6838 */ + IC_VEX_L_OPSIZE, /* 6839 */ + IC_VEX_L_W_OPSIZE, /* 6840 */ + IC_VEX_L_W_OPSIZE, /* 6841 */ + IC_VEX_L_W_OPSIZE, /* 6842 */ + IC_VEX_L_W_OPSIZE, /* 6843 */ + IC_VEX_L_W_OPSIZE, /* 6844 */ + IC_VEX_L_W_OPSIZE, /* 6845 */ + IC_VEX_L_W_OPSIZE, /* 6846 */ + IC_VEX_L_W_OPSIZE, /* 6847 */ + IC_VEX_L, /* 6848 */ + IC_VEX_L, /* 6849 */ + IC_VEX_L_XS, /* 6850 */ + IC_VEX_L_XS, /* 6851 */ + IC_VEX_L_XD, /* 6852 */ + IC_VEX_L_XD, /* 6853 */ + IC_VEX_L_XD, /* 6854 */ + IC_VEX_L_XD, /* 6855 */ + IC_VEX_L_W, /* 6856 */ + IC_VEX_L_W, /* 6857 */ + IC_VEX_L_W_XS, /* 6858 */ + IC_VEX_L_W_XS, /* 6859 */ + IC_VEX_L_W_XD, /* 6860 */ + IC_VEX_L_W_XD, /* 6861 */ + IC_VEX_L_W_XD, /* 6862 */ + IC_VEX_L_W_XD, /* 6863 */ + IC_VEX_L_OPSIZE, /* 6864 */ + IC_VEX_L_OPSIZE, /* 6865 */ + IC_VEX_L_OPSIZE, /* 6866 */ + IC_VEX_L_OPSIZE, /* 6867 */ + IC_VEX_L_OPSIZE, /* 6868 */ + IC_VEX_L_OPSIZE, /* 6869 */ + IC_VEX_L_OPSIZE, /* 6870 */ + IC_VEX_L_OPSIZE, /* 6871 */ + IC_VEX_L_W_OPSIZE, /* 6872 */ + IC_VEX_L_W_OPSIZE, /* 6873 */ + IC_VEX_L_W_OPSIZE, /* 6874 */ + IC_VEX_L_W_OPSIZE, /* 6875 */ + IC_VEX_L_W_OPSIZE, /* 6876 */ + IC_VEX_L_W_OPSIZE, /* 6877 */ + IC_VEX_L_W_OPSIZE, /* 6878 */ + IC_VEX_L_W_OPSIZE, /* 6879 */ + IC_VEX_L, /* 6880 */ + IC_VEX_L, /* 6881 */ + IC_VEX_L_XS, /* 6882 */ + IC_VEX_L_XS, /* 6883 */ + IC_VEX_L_XD, /* 6884 */ + IC_VEX_L_XD, /* 6885 */ + IC_VEX_L_XD, /* 6886 */ + IC_VEX_L_XD, /* 6887 */ + IC_VEX_L_W, /* 6888 */ + IC_VEX_L_W, /* 6889 */ + IC_VEX_L_W_XS, /* 6890 */ + IC_VEX_L_W_XS, /* 6891 */ + IC_VEX_L_W_XD, /* 6892 */ + IC_VEX_L_W_XD, /* 6893 */ + IC_VEX_L_W_XD, /* 6894 */ + IC_VEX_L_W_XD, /* 6895 */ + IC_VEX_L_OPSIZE, /* 6896 */ + IC_VEX_L_OPSIZE, /* 6897 */ + IC_VEX_L_OPSIZE, /* 6898 */ + IC_VEX_L_OPSIZE, /* 6899 */ + IC_VEX_L_OPSIZE, /* 6900 */ + IC_VEX_L_OPSIZE, /* 6901 */ + IC_VEX_L_OPSIZE, /* 6902 */ + IC_VEX_L_OPSIZE, /* 6903 */ + IC_VEX_L_W_OPSIZE, /* 6904 */ + IC_VEX_L_W_OPSIZE, /* 6905 */ + IC_VEX_L_W_OPSIZE, /* 6906 */ + IC_VEX_L_W_OPSIZE, /* 6907 */ + IC_VEX_L_W_OPSIZE, /* 6908 */ + IC_VEX_L_W_OPSIZE, /* 6909 */ + IC_VEX_L_W_OPSIZE, /* 6910 */ + IC_VEX_L_W_OPSIZE, /* 6911 */ + IC_EVEX_L_KZ, /* 6912 */ + IC_EVEX_L_KZ, /* 6913 */ + IC_EVEX_L_XS_KZ, /* 6914 */ + IC_EVEX_L_XS_KZ, /* 6915 */ + IC_EVEX_L_XD_KZ, /* 6916 */ + IC_EVEX_L_XD_KZ, /* 6917 */ + IC_EVEX_L_XD_KZ, /* 6918 */ + IC_EVEX_L_XD_KZ, /* 6919 */ + IC_EVEX_L_W_KZ, /* 6920 */ + IC_EVEX_L_W_KZ, /* 6921 */ + IC_EVEX_L_W_XS_KZ, /* 6922 */ + IC_EVEX_L_W_XS_KZ, /* 6923 */ + IC_EVEX_L_W_XD_KZ, /* 6924 */ + IC_EVEX_L_W_XD_KZ, /* 6925 */ + IC_EVEX_L_W_XD_KZ, /* 6926 */ + IC_EVEX_L_W_XD_KZ, /* 6927 */ + IC_EVEX_L_OPSIZE_KZ, /* 6928 */ + IC_EVEX_L_OPSIZE_KZ, /* 6929 */ + IC_EVEX_L_OPSIZE_KZ, /* 6930 */ + IC_EVEX_L_OPSIZE_KZ, /* 6931 */ + IC_EVEX_L_OPSIZE_KZ, /* 6932 */ + IC_EVEX_L_OPSIZE_KZ, /* 6933 */ + IC_EVEX_L_OPSIZE_KZ, /* 6934 */ + IC_EVEX_L_OPSIZE_KZ, /* 6935 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6936 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6937 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6938 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6939 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6940 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6941 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6942 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6943 */ + IC_EVEX_L_KZ, /* 6944 */ + IC_EVEX_L_KZ, /* 6945 */ + IC_EVEX_L_XS_KZ, /* 6946 */ + IC_EVEX_L_XS_KZ, /* 6947 */ + IC_EVEX_L_XD_KZ, /* 6948 */ + IC_EVEX_L_XD_KZ, /* 6949 */ + IC_EVEX_L_XD_KZ, /* 6950 */ + IC_EVEX_L_XD_KZ, /* 6951 */ + IC_EVEX_L_W_KZ, /* 6952 */ + IC_EVEX_L_W_KZ, /* 6953 */ + IC_EVEX_L_W_XS_KZ, /* 6954 */ + IC_EVEX_L_W_XS_KZ, /* 6955 */ + IC_EVEX_L_W_XD_KZ, /* 6956 */ + IC_EVEX_L_W_XD_KZ, /* 6957 */ + IC_EVEX_L_W_XD_KZ, /* 6958 */ + IC_EVEX_L_W_XD_KZ, /* 6959 */ + IC_EVEX_L_OPSIZE_KZ, /* 6960 */ + IC_EVEX_L_OPSIZE_KZ, /* 6961 */ + IC_EVEX_L_OPSIZE_KZ, /* 6962 */ + IC_EVEX_L_OPSIZE_KZ, /* 6963 */ + IC_EVEX_L_OPSIZE_KZ, /* 6964 */ + IC_EVEX_L_OPSIZE_KZ, /* 6965 */ + IC_EVEX_L_OPSIZE_KZ, /* 6966 */ + IC_EVEX_L_OPSIZE_KZ, /* 6967 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6968 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6969 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6970 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6971 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6972 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6973 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6974 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 6975 */ + IC_EVEX_L_KZ, /* 6976 */ + IC_EVEX_L_KZ, /* 6977 */ + IC_EVEX_L_XS_KZ, /* 6978 */ + IC_EVEX_L_XS_KZ, /* 6979 */ + IC_EVEX_L_XD_KZ, /* 6980 */ + IC_EVEX_L_XD_KZ, /* 6981 */ + IC_EVEX_L_XD_KZ, /* 6982 */ + IC_EVEX_L_XD_KZ, /* 6983 */ + IC_EVEX_L_W_KZ, /* 6984 */ + IC_EVEX_L_W_KZ, /* 6985 */ + IC_EVEX_L_W_XS_KZ, /* 6986 */ + IC_EVEX_L_W_XS_KZ, /* 6987 */ + IC_EVEX_L_W_XD_KZ, /* 6988 */ + IC_EVEX_L_W_XD_KZ, /* 6989 */ + IC_EVEX_L_W_XD_KZ, /* 6990 */ + IC_EVEX_L_W_XD_KZ, /* 6991 */ + IC_EVEX_L_OPSIZE_KZ, /* 6992 */ + IC_EVEX_L_OPSIZE_KZ, /* 6993 */ + IC_EVEX_L_OPSIZE_KZ, /* 6994 */ + IC_EVEX_L_OPSIZE_KZ, /* 6995 */ + IC_EVEX_L_OPSIZE_KZ, /* 6996 */ + IC_EVEX_L_OPSIZE_KZ, /* 6997 */ + IC_EVEX_L_OPSIZE_KZ, /* 6998 */ + IC_EVEX_L_OPSIZE_KZ, /* 6999 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7000 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7001 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7002 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7003 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7004 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7005 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7006 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7007 */ + IC_EVEX_L_KZ, /* 7008 */ + IC_EVEX_L_KZ, /* 7009 */ + IC_EVEX_L_XS_KZ, /* 7010 */ + IC_EVEX_L_XS_KZ, /* 7011 */ + IC_EVEX_L_XD_KZ, /* 7012 */ + IC_EVEX_L_XD_KZ, /* 7013 */ + IC_EVEX_L_XD_KZ, /* 7014 */ + IC_EVEX_L_XD_KZ, /* 7015 */ + IC_EVEX_L_W_KZ, /* 7016 */ + IC_EVEX_L_W_KZ, /* 7017 */ + IC_EVEX_L_W_XS_KZ, /* 7018 */ + IC_EVEX_L_W_XS_KZ, /* 7019 */ + IC_EVEX_L_W_XD_KZ, /* 7020 */ + IC_EVEX_L_W_XD_KZ, /* 7021 */ + IC_EVEX_L_W_XD_KZ, /* 7022 */ + IC_EVEX_L_W_XD_KZ, /* 7023 */ + IC_EVEX_L_OPSIZE_KZ, /* 7024 */ + IC_EVEX_L_OPSIZE_KZ, /* 7025 */ + IC_EVEX_L_OPSIZE_KZ, /* 7026 */ + IC_EVEX_L_OPSIZE_KZ, /* 7027 */ + IC_EVEX_L_OPSIZE_KZ, /* 7028 */ + IC_EVEX_L_OPSIZE_KZ, /* 7029 */ + IC_EVEX_L_OPSIZE_KZ, /* 7030 */ + IC_EVEX_L_OPSIZE_KZ, /* 7031 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7032 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7033 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7034 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7035 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7036 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7037 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7038 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7039 */ + IC_EVEX_L_KZ, /* 7040 */ + IC_EVEX_L_KZ, /* 7041 */ + IC_EVEX_L_XS_KZ, /* 7042 */ + IC_EVEX_L_XS_KZ, /* 7043 */ + IC_EVEX_L_XD_KZ, /* 7044 */ + IC_EVEX_L_XD_KZ, /* 7045 */ + IC_EVEX_L_XD_KZ, /* 7046 */ + IC_EVEX_L_XD_KZ, /* 7047 */ + IC_EVEX_L_W_KZ, /* 7048 */ + IC_EVEX_L_W_KZ, /* 7049 */ + IC_EVEX_L_W_XS_KZ, /* 7050 */ + IC_EVEX_L_W_XS_KZ, /* 7051 */ + IC_EVEX_L_W_XD_KZ, /* 7052 */ + IC_EVEX_L_W_XD_KZ, /* 7053 */ + IC_EVEX_L_W_XD_KZ, /* 7054 */ + IC_EVEX_L_W_XD_KZ, /* 7055 */ + IC_EVEX_L_OPSIZE_KZ, /* 7056 */ + IC_EVEX_L_OPSIZE_KZ, /* 7057 */ + IC_EVEX_L_OPSIZE_KZ, /* 7058 */ + IC_EVEX_L_OPSIZE_KZ, /* 7059 */ + IC_EVEX_L_OPSIZE_KZ, /* 7060 */ + IC_EVEX_L_OPSIZE_KZ, /* 7061 */ + IC_EVEX_L_OPSIZE_KZ, /* 7062 */ + IC_EVEX_L_OPSIZE_KZ, /* 7063 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7064 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7065 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7066 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7067 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7068 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7069 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7070 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7071 */ + IC_EVEX_L_KZ, /* 7072 */ + IC_EVEX_L_KZ, /* 7073 */ + IC_EVEX_L_XS_KZ, /* 7074 */ + IC_EVEX_L_XS_KZ, /* 7075 */ + IC_EVEX_L_XD_KZ, /* 7076 */ + IC_EVEX_L_XD_KZ, /* 7077 */ + IC_EVEX_L_XD_KZ, /* 7078 */ + IC_EVEX_L_XD_KZ, /* 7079 */ + IC_EVEX_L_W_KZ, /* 7080 */ + IC_EVEX_L_W_KZ, /* 7081 */ + IC_EVEX_L_W_XS_KZ, /* 7082 */ + IC_EVEX_L_W_XS_KZ, /* 7083 */ + IC_EVEX_L_W_XD_KZ, /* 7084 */ + IC_EVEX_L_W_XD_KZ, /* 7085 */ + IC_EVEX_L_W_XD_KZ, /* 7086 */ + IC_EVEX_L_W_XD_KZ, /* 7087 */ + IC_EVEX_L_OPSIZE_KZ, /* 7088 */ + IC_EVEX_L_OPSIZE_KZ, /* 7089 */ + IC_EVEX_L_OPSIZE_KZ, /* 7090 */ + IC_EVEX_L_OPSIZE_KZ, /* 7091 */ + IC_EVEX_L_OPSIZE_KZ, /* 7092 */ + IC_EVEX_L_OPSIZE_KZ, /* 7093 */ + IC_EVEX_L_OPSIZE_KZ, /* 7094 */ + IC_EVEX_L_OPSIZE_KZ, /* 7095 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7096 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7097 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7098 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7099 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7100 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7101 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7102 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7103 */ + IC_EVEX_L_KZ, /* 7104 */ + IC_EVEX_L_KZ, /* 7105 */ + IC_EVEX_L_XS_KZ, /* 7106 */ + IC_EVEX_L_XS_KZ, /* 7107 */ + IC_EVEX_L_XD_KZ, /* 7108 */ + IC_EVEX_L_XD_KZ, /* 7109 */ + IC_EVEX_L_XD_KZ, /* 7110 */ + IC_EVEX_L_XD_KZ, /* 7111 */ + IC_EVEX_L_W_KZ, /* 7112 */ + IC_EVEX_L_W_KZ, /* 7113 */ + IC_EVEX_L_W_XS_KZ, /* 7114 */ + IC_EVEX_L_W_XS_KZ, /* 7115 */ + IC_EVEX_L_W_XD_KZ, /* 7116 */ + IC_EVEX_L_W_XD_KZ, /* 7117 */ + IC_EVEX_L_W_XD_KZ, /* 7118 */ + IC_EVEX_L_W_XD_KZ, /* 7119 */ + IC_EVEX_L_OPSIZE_KZ, /* 7120 */ + IC_EVEX_L_OPSIZE_KZ, /* 7121 */ + IC_EVEX_L_OPSIZE_KZ, /* 7122 */ + IC_EVEX_L_OPSIZE_KZ, /* 7123 */ + IC_EVEX_L_OPSIZE_KZ, /* 7124 */ + IC_EVEX_L_OPSIZE_KZ, /* 7125 */ + IC_EVEX_L_OPSIZE_KZ, /* 7126 */ + IC_EVEX_L_OPSIZE_KZ, /* 7127 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7128 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7129 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7130 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7131 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7132 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7133 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7134 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7135 */ + IC_EVEX_L_KZ, /* 7136 */ + IC_EVEX_L_KZ, /* 7137 */ + IC_EVEX_L_XS_KZ, /* 7138 */ + IC_EVEX_L_XS_KZ, /* 7139 */ + IC_EVEX_L_XD_KZ, /* 7140 */ + IC_EVEX_L_XD_KZ, /* 7141 */ + IC_EVEX_L_XD_KZ, /* 7142 */ + IC_EVEX_L_XD_KZ, /* 7143 */ + IC_EVEX_L_W_KZ, /* 7144 */ + IC_EVEX_L_W_KZ, /* 7145 */ + IC_EVEX_L_W_XS_KZ, /* 7146 */ + IC_EVEX_L_W_XS_KZ, /* 7147 */ + IC_EVEX_L_W_XD_KZ, /* 7148 */ + IC_EVEX_L_W_XD_KZ, /* 7149 */ + IC_EVEX_L_W_XD_KZ, /* 7150 */ + IC_EVEX_L_W_XD_KZ, /* 7151 */ + IC_EVEX_L_OPSIZE_KZ, /* 7152 */ + IC_EVEX_L_OPSIZE_KZ, /* 7153 */ + IC_EVEX_L_OPSIZE_KZ, /* 7154 */ + IC_EVEX_L_OPSIZE_KZ, /* 7155 */ + IC_EVEX_L_OPSIZE_KZ, /* 7156 */ + IC_EVEX_L_OPSIZE_KZ, /* 7157 */ + IC_EVEX_L_OPSIZE_KZ, /* 7158 */ + IC_EVEX_L_OPSIZE_KZ, /* 7159 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7160 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7161 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7162 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7163 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7164 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7165 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7166 */ + IC_EVEX_L_W_OPSIZE_KZ, /* 7167 */ + IC, /* 7168 */ + IC_64BIT, /* 7169 */ + IC_XS, /* 7170 */ + IC_64BIT_XS, /* 7171 */ + IC_XD, /* 7172 */ + IC_64BIT_XD, /* 7173 */ + IC_XS, /* 7174 */ + IC_64BIT_XS, /* 7175 */ + IC, /* 7176 */ + IC_64BIT_REXW, /* 7177 */ + IC_XS, /* 7178 */ + IC_64BIT_REXW_XS, /* 7179 */ + IC_XD, /* 7180 */ + IC_64BIT_REXW_XD, /* 7181 */ + IC_XS, /* 7182 */ + IC_64BIT_REXW_XS, /* 7183 */ + IC_OPSIZE, /* 7184 */ + IC_64BIT_OPSIZE, /* 7185 */ + IC_XS_OPSIZE, /* 7186 */ + IC_64BIT_XS_OPSIZE, /* 7187 */ + IC_XD_OPSIZE, /* 7188 */ + IC_64BIT_XD_OPSIZE, /* 7189 */ + IC_XS_OPSIZE, /* 7190 */ + IC_64BIT_XD_OPSIZE, /* 7191 */ + IC_OPSIZE, /* 7192 */ + IC_64BIT_REXW_OPSIZE, /* 7193 */ + IC_XS_OPSIZE, /* 7194 */ + IC_64BIT_REXW_XS, /* 7195 */ + IC_XD_OPSIZE, /* 7196 */ + IC_64BIT_REXW_XD, /* 7197 */ + IC_XS_OPSIZE, /* 7198 */ + IC_64BIT_REXW_XS, /* 7199 */ + IC_ADSIZE, /* 7200 */ + IC_64BIT_ADSIZE, /* 7201 */ + IC_XS_ADSIZE, /* 7202 */ + IC_64BIT_XS_ADSIZE, /* 7203 */ + IC_XD_ADSIZE, /* 7204 */ + IC_64BIT_XD_ADSIZE, /* 7205 */ + IC_XS_ADSIZE, /* 7206 */ + IC_64BIT_XD_ADSIZE, /* 7207 */ + IC_ADSIZE, /* 7208 */ + IC_64BIT_REXW_ADSIZE, /* 7209 */ + IC_XS_ADSIZE, /* 7210 */ + IC_64BIT_REXW_XS, /* 7211 */ + IC_XD_ADSIZE, /* 7212 */ + IC_64BIT_REXW_XD, /* 7213 */ + IC_XS_ADSIZE, /* 7214 */ + IC_64BIT_REXW_XS, /* 7215 */ + IC_OPSIZE_ADSIZE, /* 7216 */ + IC_64BIT_OPSIZE_ADSIZE, /* 7217 */ + IC_XS_OPSIZE, /* 7218 */ + IC_64BIT_XS_OPSIZE, /* 7219 */ + IC_XD_OPSIZE, /* 7220 */ + IC_64BIT_XD_OPSIZE, /* 7221 */ + IC_XS_OPSIZE, /* 7222 */ + IC_64BIT_XD_OPSIZE, /* 7223 */ + IC_OPSIZE_ADSIZE, /* 7224 */ + IC_64BIT_REXW_OPSIZE, /* 7225 */ + IC_XS_OPSIZE, /* 7226 */ + IC_64BIT_REXW_XS, /* 7227 */ + IC_XD_OPSIZE, /* 7228 */ + IC_64BIT_REXW_XD, /* 7229 */ + IC_XS_OPSIZE, /* 7230 */ + IC_64BIT_REXW_XS, /* 7231 */ + IC_VEX, /* 7232 */ + IC_VEX, /* 7233 */ + IC_VEX_XS, /* 7234 */ + IC_VEX_XS, /* 7235 */ + IC_VEX_XD, /* 7236 */ + IC_VEX_XD, /* 7237 */ + IC_VEX_XD, /* 7238 */ + IC_VEX_XD, /* 7239 */ + IC_VEX_W, /* 7240 */ + IC_VEX_W, /* 7241 */ + IC_VEX_W_XS, /* 7242 */ + IC_VEX_W_XS, /* 7243 */ + IC_VEX_W_XD, /* 7244 */ + IC_VEX_W_XD, /* 7245 */ + IC_VEX_W_XD, /* 7246 */ + IC_VEX_W_XD, /* 7247 */ + IC_VEX_OPSIZE, /* 7248 */ + IC_VEX_OPSIZE, /* 7249 */ + IC_VEX_OPSIZE, /* 7250 */ + IC_VEX_OPSIZE, /* 7251 */ + IC_VEX_OPSIZE, /* 7252 */ + IC_VEX_OPSIZE, /* 7253 */ + IC_VEX_OPSIZE, /* 7254 */ + IC_VEX_OPSIZE, /* 7255 */ + IC_VEX_W_OPSIZE, /* 7256 */ + IC_VEX_W_OPSIZE, /* 7257 */ + IC_VEX_W_OPSIZE, /* 7258 */ + IC_VEX_W_OPSIZE, /* 7259 */ + IC_VEX_W_OPSIZE, /* 7260 */ + IC_VEX_W_OPSIZE, /* 7261 */ + IC_VEX_W_OPSIZE, /* 7262 */ + IC_VEX_W_OPSIZE, /* 7263 */ + IC_VEX, /* 7264 */ + IC_VEX, /* 7265 */ + IC_VEX_XS, /* 7266 */ + IC_VEX_XS, /* 7267 */ + IC_VEX_XD, /* 7268 */ + IC_VEX_XD, /* 7269 */ + IC_VEX_XD, /* 7270 */ + IC_VEX_XD, /* 7271 */ + IC_VEX_W, /* 7272 */ + IC_VEX_W, /* 7273 */ + IC_VEX_W_XS, /* 7274 */ + IC_VEX_W_XS, /* 7275 */ + IC_VEX_W_XD, /* 7276 */ + IC_VEX_W_XD, /* 7277 */ + IC_VEX_W_XD, /* 7278 */ + IC_VEX_W_XD, /* 7279 */ + IC_VEX_OPSIZE, /* 7280 */ + IC_VEX_OPSIZE, /* 7281 */ + IC_VEX_OPSIZE, /* 7282 */ + IC_VEX_OPSIZE, /* 7283 */ + IC_VEX_OPSIZE, /* 7284 */ + IC_VEX_OPSIZE, /* 7285 */ + IC_VEX_OPSIZE, /* 7286 */ + IC_VEX_OPSIZE, /* 7287 */ + IC_VEX_W_OPSIZE, /* 7288 */ + IC_VEX_W_OPSIZE, /* 7289 */ + IC_VEX_W_OPSIZE, /* 7290 */ + IC_VEX_W_OPSIZE, /* 7291 */ + IC_VEX_W_OPSIZE, /* 7292 */ + IC_VEX_W_OPSIZE, /* 7293 */ + IC_VEX_W_OPSIZE, /* 7294 */ + IC_VEX_W_OPSIZE, /* 7295 */ + IC_VEX_L, /* 7296 */ + IC_VEX_L, /* 7297 */ + IC_VEX_L_XS, /* 7298 */ + IC_VEX_L_XS, /* 7299 */ + IC_VEX_L_XD, /* 7300 */ + IC_VEX_L_XD, /* 7301 */ + IC_VEX_L_XD, /* 7302 */ + IC_VEX_L_XD, /* 7303 */ + IC_VEX_L_W, /* 7304 */ + IC_VEX_L_W, /* 7305 */ + IC_VEX_L_W_XS, /* 7306 */ + IC_VEX_L_W_XS, /* 7307 */ + IC_VEX_L_W_XD, /* 7308 */ + IC_VEX_L_W_XD, /* 7309 */ + IC_VEX_L_W_XD, /* 7310 */ + IC_VEX_L_W_XD, /* 7311 */ + IC_VEX_L_OPSIZE, /* 7312 */ + IC_VEX_L_OPSIZE, /* 7313 */ + IC_VEX_L_OPSIZE, /* 7314 */ + IC_VEX_L_OPSIZE, /* 7315 */ + IC_VEX_L_OPSIZE, /* 7316 */ + IC_VEX_L_OPSIZE, /* 7317 */ + IC_VEX_L_OPSIZE, /* 7318 */ + IC_VEX_L_OPSIZE, /* 7319 */ + IC_VEX_L_W_OPSIZE, /* 7320 */ + IC_VEX_L_W_OPSIZE, /* 7321 */ + IC_VEX_L_W_OPSIZE, /* 7322 */ + IC_VEX_L_W_OPSIZE, /* 7323 */ + IC_VEX_L_W_OPSIZE, /* 7324 */ + IC_VEX_L_W_OPSIZE, /* 7325 */ + IC_VEX_L_W_OPSIZE, /* 7326 */ + IC_VEX_L_W_OPSIZE, /* 7327 */ + IC_VEX_L, /* 7328 */ + IC_VEX_L, /* 7329 */ + IC_VEX_L_XS, /* 7330 */ + IC_VEX_L_XS, /* 7331 */ + IC_VEX_L_XD, /* 7332 */ + IC_VEX_L_XD, /* 7333 */ + IC_VEX_L_XD, /* 7334 */ + IC_VEX_L_XD, /* 7335 */ + IC_VEX_L_W, /* 7336 */ + IC_VEX_L_W, /* 7337 */ + IC_VEX_L_W_XS, /* 7338 */ + IC_VEX_L_W_XS, /* 7339 */ + IC_VEX_L_W_XD, /* 7340 */ + IC_VEX_L_W_XD, /* 7341 */ + IC_VEX_L_W_XD, /* 7342 */ + IC_VEX_L_W_XD, /* 7343 */ + IC_VEX_L_OPSIZE, /* 7344 */ + IC_VEX_L_OPSIZE, /* 7345 */ + IC_VEX_L_OPSIZE, /* 7346 */ + IC_VEX_L_OPSIZE, /* 7347 */ + IC_VEX_L_OPSIZE, /* 7348 */ + IC_VEX_L_OPSIZE, /* 7349 */ + IC_VEX_L_OPSIZE, /* 7350 */ + IC_VEX_L_OPSIZE, /* 7351 */ + IC_VEX_L_W_OPSIZE, /* 7352 */ + IC_VEX_L_W_OPSIZE, /* 7353 */ + IC_VEX_L_W_OPSIZE, /* 7354 */ + IC_VEX_L_W_OPSIZE, /* 7355 */ + IC_VEX_L_W_OPSIZE, /* 7356 */ + IC_VEX_L_W_OPSIZE, /* 7357 */ + IC_VEX_L_W_OPSIZE, /* 7358 */ + IC_VEX_L_W_OPSIZE, /* 7359 */ + IC_VEX_L, /* 7360 */ + IC_VEX_L, /* 7361 */ + IC_VEX_L_XS, /* 7362 */ + IC_VEX_L_XS, /* 7363 */ + IC_VEX_L_XD, /* 7364 */ + IC_VEX_L_XD, /* 7365 */ + IC_VEX_L_XD, /* 7366 */ + IC_VEX_L_XD, /* 7367 */ + IC_VEX_L_W, /* 7368 */ + IC_VEX_L_W, /* 7369 */ + IC_VEX_L_W_XS, /* 7370 */ + IC_VEX_L_W_XS, /* 7371 */ + IC_VEX_L_W_XD, /* 7372 */ + IC_VEX_L_W_XD, /* 7373 */ + IC_VEX_L_W_XD, /* 7374 */ + IC_VEX_L_W_XD, /* 7375 */ + IC_VEX_L_OPSIZE, /* 7376 */ + IC_VEX_L_OPSIZE, /* 7377 */ + IC_VEX_L_OPSIZE, /* 7378 */ + IC_VEX_L_OPSIZE, /* 7379 */ + IC_VEX_L_OPSIZE, /* 7380 */ + IC_VEX_L_OPSIZE, /* 7381 */ + IC_VEX_L_OPSIZE, /* 7382 */ + IC_VEX_L_OPSIZE, /* 7383 */ + IC_VEX_L_W_OPSIZE, /* 7384 */ + IC_VEX_L_W_OPSIZE, /* 7385 */ + IC_VEX_L_W_OPSIZE, /* 7386 */ + IC_VEX_L_W_OPSIZE, /* 7387 */ + IC_VEX_L_W_OPSIZE, /* 7388 */ + IC_VEX_L_W_OPSIZE, /* 7389 */ + IC_VEX_L_W_OPSIZE, /* 7390 */ + IC_VEX_L_W_OPSIZE, /* 7391 */ + IC_VEX_L, /* 7392 */ + IC_VEX_L, /* 7393 */ + IC_VEX_L_XS, /* 7394 */ + IC_VEX_L_XS, /* 7395 */ + IC_VEX_L_XD, /* 7396 */ + IC_VEX_L_XD, /* 7397 */ + IC_VEX_L_XD, /* 7398 */ + IC_VEX_L_XD, /* 7399 */ + IC_VEX_L_W, /* 7400 */ + IC_VEX_L_W, /* 7401 */ + IC_VEX_L_W_XS, /* 7402 */ + IC_VEX_L_W_XS, /* 7403 */ + IC_VEX_L_W_XD, /* 7404 */ + IC_VEX_L_W_XD, /* 7405 */ + IC_VEX_L_W_XD, /* 7406 */ + IC_VEX_L_W_XD, /* 7407 */ + IC_VEX_L_OPSIZE, /* 7408 */ + IC_VEX_L_OPSIZE, /* 7409 */ + IC_VEX_L_OPSIZE, /* 7410 */ + IC_VEX_L_OPSIZE, /* 7411 */ + IC_VEX_L_OPSIZE, /* 7412 */ + IC_VEX_L_OPSIZE, /* 7413 */ + IC_VEX_L_OPSIZE, /* 7414 */ + IC_VEX_L_OPSIZE, /* 7415 */ + IC_VEX_L_W_OPSIZE, /* 7416 */ + IC_VEX_L_W_OPSIZE, /* 7417 */ + IC_VEX_L_W_OPSIZE, /* 7418 */ + IC_VEX_L_W_OPSIZE, /* 7419 */ + IC_VEX_L_W_OPSIZE, /* 7420 */ + IC_VEX_L_W_OPSIZE, /* 7421 */ + IC_VEX_L_W_OPSIZE, /* 7422 */ + IC_VEX_L_W_OPSIZE, /* 7423 */ + IC_EVEX_L2_KZ, /* 7424 */ + IC_EVEX_L2_KZ, /* 7425 */ + IC_EVEX_L2_XS_KZ, /* 7426 */ + IC_EVEX_L2_XS_KZ, /* 7427 */ + IC_EVEX_L2_XD_KZ, /* 7428 */ + IC_EVEX_L2_XD_KZ, /* 7429 */ + IC_EVEX_L2_XD_KZ, /* 7430 */ + IC_EVEX_L2_XD_KZ, /* 7431 */ + IC_EVEX_L2_W_KZ, /* 7432 */ + IC_EVEX_L2_W_KZ, /* 7433 */ + IC_EVEX_L2_W_XS_KZ, /* 7434 */ + IC_EVEX_L2_W_XS_KZ, /* 7435 */ + IC_EVEX_L2_W_XD_KZ, /* 7436 */ + IC_EVEX_L2_W_XD_KZ, /* 7437 */ + IC_EVEX_L2_W_XD_KZ, /* 7438 */ + IC_EVEX_L2_W_XD_KZ, /* 7439 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7440 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7441 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7442 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7443 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7444 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7445 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7446 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7447 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7448 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7449 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7450 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7451 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7452 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7453 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7454 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7455 */ + IC_EVEX_L2_KZ, /* 7456 */ + IC_EVEX_L2_KZ, /* 7457 */ + IC_EVEX_L2_XS_KZ, /* 7458 */ + IC_EVEX_L2_XS_KZ, /* 7459 */ + IC_EVEX_L2_XD_KZ, /* 7460 */ + IC_EVEX_L2_XD_KZ, /* 7461 */ + IC_EVEX_L2_XD_KZ, /* 7462 */ + IC_EVEX_L2_XD_KZ, /* 7463 */ + IC_EVEX_L2_W_KZ, /* 7464 */ + IC_EVEX_L2_W_KZ, /* 7465 */ + IC_EVEX_L2_W_XS_KZ, /* 7466 */ + IC_EVEX_L2_W_XS_KZ, /* 7467 */ + IC_EVEX_L2_W_XD_KZ, /* 7468 */ + IC_EVEX_L2_W_XD_KZ, /* 7469 */ + IC_EVEX_L2_W_XD_KZ, /* 7470 */ + IC_EVEX_L2_W_XD_KZ, /* 7471 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7472 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7473 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7474 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7475 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7476 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7477 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7478 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7479 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7480 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7481 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7482 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7483 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7484 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7485 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7486 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7487 */ + IC_EVEX_L2_KZ, /* 7488 */ + IC_EVEX_L2_KZ, /* 7489 */ + IC_EVEX_L2_XS_KZ, /* 7490 */ + IC_EVEX_L2_XS_KZ, /* 7491 */ + IC_EVEX_L2_XD_KZ, /* 7492 */ + IC_EVEX_L2_XD_KZ, /* 7493 */ + IC_EVEX_L2_XD_KZ, /* 7494 */ + IC_EVEX_L2_XD_KZ, /* 7495 */ + IC_EVEX_L2_W_KZ, /* 7496 */ + IC_EVEX_L2_W_KZ, /* 7497 */ + IC_EVEX_L2_W_XS_KZ, /* 7498 */ + IC_EVEX_L2_W_XS_KZ, /* 7499 */ + IC_EVEX_L2_W_XD_KZ, /* 7500 */ + IC_EVEX_L2_W_XD_KZ, /* 7501 */ + IC_EVEX_L2_W_XD_KZ, /* 7502 */ + IC_EVEX_L2_W_XD_KZ, /* 7503 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7504 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7505 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7506 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7507 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7508 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7509 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7510 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7511 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7512 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7513 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7514 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7515 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7516 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7517 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7518 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7519 */ + IC_EVEX_L2_KZ, /* 7520 */ + IC_EVEX_L2_KZ, /* 7521 */ + IC_EVEX_L2_XS_KZ, /* 7522 */ + IC_EVEX_L2_XS_KZ, /* 7523 */ + IC_EVEX_L2_XD_KZ, /* 7524 */ + IC_EVEX_L2_XD_KZ, /* 7525 */ + IC_EVEX_L2_XD_KZ, /* 7526 */ + IC_EVEX_L2_XD_KZ, /* 7527 */ + IC_EVEX_L2_W_KZ, /* 7528 */ + IC_EVEX_L2_W_KZ, /* 7529 */ + IC_EVEX_L2_W_XS_KZ, /* 7530 */ + IC_EVEX_L2_W_XS_KZ, /* 7531 */ + IC_EVEX_L2_W_XD_KZ, /* 7532 */ + IC_EVEX_L2_W_XD_KZ, /* 7533 */ + IC_EVEX_L2_W_XD_KZ, /* 7534 */ + IC_EVEX_L2_W_XD_KZ, /* 7535 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7536 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7537 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7538 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7539 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7540 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7541 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7542 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7543 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7544 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7545 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7546 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7547 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7548 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7549 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7550 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7551 */ + IC_EVEX_L2_KZ, /* 7552 */ + IC_EVEX_L2_KZ, /* 7553 */ + IC_EVEX_L2_XS_KZ, /* 7554 */ + IC_EVEX_L2_XS_KZ, /* 7555 */ + IC_EVEX_L2_XD_KZ, /* 7556 */ + IC_EVEX_L2_XD_KZ, /* 7557 */ + IC_EVEX_L2_XD_KZ, /* 7558 */ + IC_EVEX_L2_XD_KZ, /* 7559 */ + IC_EVEX_L2_W_KZ, /* 7560 */ + IC_EVEX_L2_W_KZ, /* 7561 */ + IC_EVEX_L2_W_XS_KZ, /* 7562 */ + IC_EVEX_L2_W_XS_KZ, /* 7563 */ + IC_EVEX_L2_W_XD_KZ, /* 7564 */ + IC_EVEX_L2_W_XD_KZ, /* 7565 */ + IC_EVEX_L2_W_XD_KZ, /* 7566 */ + IC_EVEX_L2_W_XD_KZ, /* 7567 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7568 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7569 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7570 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7571 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7572 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7573 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7574 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7575 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7576 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7577 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7578 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7579 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7580 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7581 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7582 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7583 */ + IC_EVEX_L2_KZ, /* 7584 */ + IC_EVEX_L2_KZ, /* 7585 */ + IC_EVEX_L2_XS_KZ, /* 7586 */ + IC_EVEX_L2_XS_KZ, /* 7587 */ + IC_EVEX_L2_XD_KZ, /* 7588 */ + IC_EVEX_L2_XD_KZ, /* 7589 */ + IC_EVEX_L2_XD_KZ, /* 7590 */ + IC_EVEX_L2_XD_KZ, /* 7591 */ + IC_EVEX_L2_W_KZ, /* 7592 */ + IC_EVEX_L2_W_KZ, /* 7593 */ + IC_EVEX_L2_W_XS_KZ, /* 7594 */ + IC_EVEX_L2_W_XS_KZ, /* 7595 */ + IC_EVEX_L2_W_XD_KZ, /* 7596 */ + IC_EVEX_L2_W_XD_KZ, /* 7597 */ + IC_EVEX_L2_W_XD_KZ, /* 7598 */ + IC_EVEX_L2_W_XD_KZ, /* 7599 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7600 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7601 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7602 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7603 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7604 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7605 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7606 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7607 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7608 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7609 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7610 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7611 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7612 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7613 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7614 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7615 */ + IC_EVEX_L2_KZ, /* 7616 */ + IC_EVEX_L2_KZ, /* 7617 */ + IC_EVEX_L2_XS_KZ, /* 7618 */ + IC_EVEX_L2_XS_KZ, /* 7619 */ + IC_EVEX_L2_XD_KZ, /* 7620 */ + IC_EVEX_L2_XD_KZ, /* 7621 */ + IC_EVEX_L2_XD_KZ, /* 7622 */ + IC_EVEX_L2_XD_KZ, /* 7623 */ + IC_EVEX_L2_W_KZ, /* 7624 */ + IC_EVEX_L2_W_KZ, /* 7625 */ + IC_EVEX_L2_W_XS_KZ, /* 7626 */ + IC_EVEX_L2_W_XS_KZ, /* 7627 */ + IC_EVEX_L2_W_XD_KZ, /* 7628 */ + IC_EVEX_L2_W_XD_KZ, /* 7629 */ + IC_EVEX_L2_W_XD_KZ, /* 7630 */ + IC_EVEX_L2_W_XD_KZ, /* 7631 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7632 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7633 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7634 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7635 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7636 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7637 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7638 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7639 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7640 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7641 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7642 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7643 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7644 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7645 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7646 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7647 */ + IC_EVEX_L2_KZ, /* 7648 */ + IC_EVEX_L2_KZ, /* 7649 */ + IC_EVEX_L2_XS_KZ, /* 7650 */ + IC_EVEX_L2_XS_KZ, /* 7651 */ + IC_EVEX_L2_XD_KZ, /* 7652 */ + IC_EVEX_L2_XD_KZ, /* 7653 */ + IC_EVEX_L2_XD_KZ, /* 7654 */ + IC_EVEX_L2_XD_KZ, /* 7655 */ + IC_EVEX_L2_W_KZ, /* 7656 */ + IC_EVEX_L2_W_KZ, /* 7657 */ + IC_EVEX_L2_W_XS_KZ, /* 7658 */ + IC_EVEX_L2_W_XS_KZ, /* 7659 */ + IC_EVEX_L2_W_XD_KZ, /* 7660 */ + IC_EVEX_L2_W_XD_KZ, /* 7661 */ + IC_EVEX_L2_W_XD_KZ, /* 7662 */ + IC_EVEX_L2_W_XD_KZ, /* 7663 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7664 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7665 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7666 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7667 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7668 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7669 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7670 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7671 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7672 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7673 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7674 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7675 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7676 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7677 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7678 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7679 */ + IC, /* 7680 */ + IC_64BIT, /* 7681 */ + IC_XS, /* 7682 */ + IC_64BIT_XS, /* 7683 */ + IC_XD, /* 7684 */ + IC_64BIT_XD, /* 7685 */ + IC_XS, /* 7686 */ + IC_64BIT_XS, /* 7687 */ + IC, /* 7688 */ + IC_64BIT_REXW, /* 7689 */ + IC_XS, /* 7690 */ + IC_64BIT_REXW_XS, /* 7691 */ + IC_XD, /* 7692 */ + IC_64BIT_REXW_XD, /* 7693 */ + IC_XS, /* 7694 */ + IC_64BIT_REXW_XS, /* 7695 */ + IC_OPSIZE, /* 7696 */ + IC_64BIT_OPSIZE, /* 7697 */ + IC_XS_OPSIZE, /* 7698 */ + IC_64BIT_XS_OPSIZE, /* 7699 */ + IC_XD_OPSIZE, /* 7700 */ + IC_64BIT_XD_OPSIZE, /* 7701 */ + IC_XS_OPSIZE, /* 7702 */ + IC_64BIT_XD_OPSIZE, /* 7703 */ + IC_OPSIZE, /* 7704 */ + IC_64BIT_REXW_OPSIZE, /* 7705 */ + IC_XS_OPSIZE, /* 7706 */ + IC_64BIT_REXW_XS, /* 7707 */ + IC_XD_OPSIZE, /* 7708 */ + IC_64BIT_REXW_XD, /* 7709 */ + IC_XS_OPSIZE, /* 7710 */ + IC_64BIT_REXW_XS, /* 7711 */ + IC_ADSIZE, /* 7712 */ + IC_64BIT_ADSIZE, /* 7713 */ + IC_XS_ADSIZE, /* 7714 */ + IC_64BIT_XS_ADSIZE, /* 7715 */ + IC_XD_ADSIZE, /* 7716 */ + IC_64BIT_XD_ADSIZE, /* 7717 */ + IC_XS_ADSIZE, /* 7718 */ + IC_64BIT_XD_ADSIZE, /* 7719 */ + IC_ADSIZE, /* 7720 */ + IC_64BIT_REXW_ADSIZE, /* 7721 */ + IC_XS_ADSIZE, /* 7722 */ + IC_64BIT_REXW_XS, /* 7723 */ + IC_XD_ADSIZE, /* 7724 */ + IC_64BIT_REXW_XD, /* 7725 */ + IC_XS_ADSIZE, /* 7726 */ + IC_64BIT_REXW_XS, /* 7727 */ + IC_OPSIZE_ADSIZE, /* 7728 */ + IC_64BIT_OPSIZE_ADSIZE, /* 7729 */ + IC_XS_OPSIZE, /* 7730 */ + IC_64BIT_XS_OPSIZE, /* 7731 */ + IC_XD_OPSIZE, /* 7732 */ + IC_64BIT_XD_OPSIZE, /* 7733 */ + IC_XS_OPSIZE, /* 7734 */ + IC_64BIT_XD_OPSIZE, /* 7735 */ + IC_OPSIZE_ADSIZE, /* 7736 */ + IC_64BIT_REXW_OPSIZE, /* 7737 */ + IC_XS_OPSIZE, /* 7738 */ + IC_64BIT_REXW_XS, /* 7739 */ + IC_XD_OPSIZE, /* 7740 */ + IC_64BIT_REXW_XD, /* 7741 */ + IC_XS_OPSIZE, /* 7742 */ + IC_64BIT_REXW_XS, /* 7743 */ + IC_VEX, /* 7744 */ + IC_VEX, /* 7745 */ + IC_VEX_XS, /* 7746 */ + IC_VEX_XS, /* 7747 */ + IC_VEX_XD, /* 7748 */ + IC_VEX_XD, /* 7749 */ + IC_VEX_XD, /* 7750 */ + IC_VEX_XD, /* 7751 */ + IC_VEX_W, /* 7752 */ + IC_VEX_W, /* 7753 */ + IC_VEX_W_XS, /* 7754 */ + IC_VEX_W_XS, /* 7755 */ + IC_VEX_W_XD, /* 7756 */ + IC_VEX_W_XD, /* 7757 */ + IC_VEX_W_XD, /* 7758 */ + IC_VEX_W_XD, /* 7759 */ + IC_VEX_OPSIZE, /* 7760 */ + IC_VEX_OPSIZE, /* 7761 */ + IC_VEX_OPSIZE, /* 7762 */ + IC_VEX_OPSIZE, /* 7763 */ + IC_VEX_OPSIZE, /* 7764 */ + IC_VEX_OPSIZE, /* 7765 */ + IC_VEX_OPSIZE, /* 7766 */ + IC_VEX_OPSIZE, /* 7767 */ + IC_VEX_W_OPSIZE, /* 7768 */ + IC_VEX_W_OPSIZE, /* 7769 */ + IC_VEX_W_OPSIZE, /* 7770 */ + IC_VEX_W_OPSIZE, /* 7771 */ + IC_VEX_W_OPSIZE, /* 7772 */ + IC_VEX_W_OPSIZE, /* 7773 */ + IC_VEX_W_OPSIZE, /* 7774 */ + IC_VEX_W_OPSIZE, /* 7775 */ + IC_VEX, /* 7776 */ + IC_VEX, /* 7777 */ + IC_VEX_XS, /* 7778 */ + IC_VEX_XS, /* 7779 */ + IC_VEX_XD, /* 7780 */ + IC_VEX_XD, /* 7781 */ + IC_VEX_XD, /* 7782 */ + IC_VEX_XD, /* 7783 */ + IC_VEX_W, /* 7784 */ + IC_VEX_W, /* 7785 */ + IC_VEX_W_XS, /* 7786 */ + IC_VEX_W_XS, /* 7787 */ + IC_VEX_W_XD, /* 7788 */ + IC_VEX_W_XD, /* 7789 */ + IC_VEX_W_XD, /* 7790 */ + IC_VEX_W_XD, /* 7791 */ + IC_VEX_OPSIZE, /* 7792 */ + IC_VEX_OPSIZE, /* 7793 */ + IC_VEX_OPSIZE, /* 7794 */ + IC_VEX_OPSIZE, /* 7795 */ + IC_VEX_OPSIZE, /* 7796 */ + IC_VEX_OPSIZE, /* 7797 */ + IC_VEX_OPSIZE, /* 7798 */ + IC_VEX_OPSIZE, /* 7799 */ + IC_VEX_W_OPSIZE, /* 7800 */ + IC_VEX_W_OPSIZE, /* 7801 */ + IC_VEX_W_OPSIZE, /* 7802 */ + IC_VEX_W_OPSIZE, /* 7803 */ + IC_VEX_W_OPSIZE, /* 7804 */ + IC_VEX_W_OPSIZE, /* 7805 */ + IC_VEX_W_OPSIZE, /* 7806 */ + IC_VEX_W_OPSIZE, /* 7807 */ + IC_VEX_L, /* 7808 */ + IC_VEX_L, /* 7809 */ + IC_VEX_L_XS, /* 7810 */ + IC_VEX_L_XS, /* 7811 */ + IC_VEX_L_XD, /* 7812 */ + IC_VEX_L_XD, /* 7813 */ + IC_VEX_L_XD, /* 7814 */ + IC_VEX_L_XD, /* 7815 */ + IC_VEX_L_W, /* 7816 */ + IC_VEX_L_W, /* 7817 */ + IC_VEX_L_W_XS, /* 7818 */ + IC_VEX_L_W_XS, /* 7819 */ + IC_VEX_L_W_XD, /* 7820 */ + IC_VEX_L_W_XD, /* 7821 */ + IC_VEX_L_W_XD, /* 7822 */ + IC_VEX_L_W_XD, /* 7823 */ + IC_VEX_L_OPSIZE, /* 7824 */ + IC_VEX_L_OPSIZE, /* 7825 */ + IC_VEX_L_OPSIZE, /* 7826 */ + IC_VEX_L_OPSIZE, /* 7827 */ + IC_VEX_L_OPSIZE, /* 7828 */ + IC_VEX_L_OPSIZE, /* 7829 */ + IC_VEX_L_OPSIZE, /* 7830 */ + IC_VEX_L_OPSIZE, /* 7831 */ + IC_VEX_L_W_OPSIZE, /* 7832 */ + IC_VEX_L_W_OPSIZE, /* 7833 */ + IC_VEX_L_W_OPSIZE, /* 7834 */ + IC_VEX_L_W_OPSIZE, /* 7835 */ + IC_VEX_L_W_OPSIZE, /* 7836 */ + IC_VEX_L_W_OPSIZE, /* 7837 */ + IC_VEX_L_W_OPSIZE, /* 7838 */ + IC_VEX_L_W_OPSIZE, /* 7839 */ + IC_VEX_L, /* 7840 */ + IC_VEX_L, /* 7841 */ + IC_VEX_L_XS, /* 7842 */ + IC_VEX_L_XS, /* 7843 */ + IC_VEX_L_XD, /* 7844 */ + IC_VEX_L_XD, /* 7845 */ + IC_VEX_L_XD, /* 7846 */ + IC_VEX_L_XD, /* 7847 */ + IC_VEX_L_W, /* 7848 */ + IC_VEX_L_W, /* 7849 */ + IC_VEX_L_W_XS, /* 7850 */ + IC_VEX_L_W_XS, /* 7851 */ + IC_VEX_L_W_XD, /* 7852 */ + IC_VEX_L_W_XD, /* 7853 */ + IC_VEX_L_W_XD, /* 7854 */ + IC_VEX_L_W_XD, /* 7855 */ + IC_VEX_L_OPSIZE, /* 7856 */ + IC_VEX_L_OPSIZE, /* 7857 */ + IC_VEX_L_OPSIZE, /* 7858 */ + IC_VEX_L_OPSIZE, /* 7859 */ + IC_VEX_L_OPSIZE, /* 7860 */ + IC_VEX_L_OPSIZE, /* 7861 */ + IC_VEX_L_OPSIZE, /* 7862 */ + IC_VEX_L_OPSIZE, /* 7863 */ + IC_VEX_L_W_OPSIZE, /* 7864 */ + IC_VEX_L_W_OPSIZE, /* 7865 */ + IC_VEX_L_W_OPSIZE, /* 7866 */ + IC_VEX_L_W_OPSIZE, /* 7867 */ + IC_VEX_L_W_OPSIZE, /* 7868 */ + IC_VEX_L_W_OPSIZE, /* 7869 */ + IC_VEX_L_W_OPSIZE, /* 7870 */ + IC_VEX_L_W_OPSIZE, /* 7871 */ + IC_VEX_L, /* 7872 */ + IC_VEX_L, /* 7873 */ + IC_VEX_L_XS, /* 7874 */ + IC_VEX_L_XS, /* 7875 */ + IC_VEX_L_XD, /* 7876 */ + IC_VEX_L_XD, /* 7877 */ + IC_VEX_L_XD, /* 7878 */ + IC_VEX_L_XD, /* 7879 */ + IC_VEX_L_W, /* 7880 */ + IC_VEX_L_W, /* 7881 */ + IC_VEX_L_W_XS, /* 7882 */ + IC_VEX_L_W_XS, /* 7883 */ + IC_VEX_L_W_XD, /* 7884 */ + IC_VEX_L_W_XD, /* 7885 */ + IC_VEX_L_W_XD, /* 7886 */ + IC_VEX_L_W_XD, /* 7887 */ + IC_VEX_L_OPSIZE, /* 7888 */ + IC_VEX_L_OPSIZE, /* 7889 */ + IC_VEX_L_OPSIZE, /* 7890 */ + IC_VEX_L_OPSIZE, /* 7891 */ + IC_VEX_L_OPSIZE, /* 7892 */ + IC_VEX_L_OPSIZE, /* 7893 */ + IC_VEX_L_OPSIZE, /* 7894 */ + IC_VEX_L_OPSIZE, /* 7895 */ + IC_VEX_L_W_OPSIZE, /* 7896 */ + IC_VEX_L_W_OPSIZE, /* 7897 */ + IC_VEX_L_W_OPSIZE, /* 7898 */ + IC_VEX_L_W_OPSIZE, /* 7899 */ + IC_VEX_L_W_OPSIZE, /* 7900 */ + IC_VEX_L_W_OPSIZE, /* 7901 */ + IC_VEX_L_W_OPSIZE, /* 7902 */ + IC_VEX_L_W_OPSIZE, /* 7903 */ + IC_VEX_L, /* 7904 */ + IC_VEX_L, /* 7905 */ + IC_VEX_L_XS, /* 7906 */ + IC_VEX_L_XS, /* 7907 */ + IC_VEX_L_XD, /* 7908 */ + IC_VEX_L_XD, /* 7909 */ + IC_VEX_L_XD, /* 7910 */ + IC_VEX_L_XD, /* 7911 */ + IC_VEX_L_W, /* 7912 */ + IC_VEX_L_W, /* 7913 */ + IC_VEX_L_W_XS, /* 7914 */ + IC_VEX_L_W_XS, /* 7915 */ + IC_VEX_L_W_XD, /* 7916 */ + IC_VEX_L_W_XD, /* 7917 */ + IC_VEX_L_W_XD, /* 7918 */ + IC_VEX_L_W_XD, /* 7919 */ + IC_VEX_L_OPSIZE, /* 7920 */ + IC_VEX_L_OPSIZE, /* 7921 */ + IC_VEX_L_OPSIZE, /* 7922 */ + IC_VEX_L_OPSIZE, /* 7923 */ + IC_VEX_L_OPSIZE, /* 7924 */ + IC_VEX_L_OPSIZE, /* 7925 */ + IC_VEX_L_OPSIZE, /* 7926 */ + IC_VEX_L_OPSIZE, /* 7927 */ + IC_VEX_L_W_OPSIZE, /* 7928 */ + IC_VEX_L_W_OPSIZE, /* 7929 */ + IC_VEX_L_W_OPSIZE, /* 7930 */ + IC_VEX_L_W_OPSIZE, /* 7931 */ + IC_VEX_L_W_OPSIZE, /* 7932 */ + IC_VEX_L_W_OPSIZE, /* 7933 */ + IC_VEX_L_W_OPSIZE, /* 7934 */ + IC_VEX_L_W_OPSIZE, /* 7935 */ + IC_EVEX_L2_KZ, /* 7936 */ + IC_EVEX_L2_KZ, /* 7937 */ + IC_EVEX_L2_XS_KZ, /* 7938 */ + IC_EVEX_L2_XS_KZ, /* 7939 */ + IC_EVEX_L2_XD_KZ, /* 7940 */ + IC_EVEX_L2_XD_KZ, /* 7941 */ + IC_EVEX_L2_XD_KZ, /* 7942 */ + IC_EVEX_L2_XD_KZ, /* 7943 */ + IC_EVEX_L2_W_KZ, /* 7944 */ + IC_EVEX_L2_W_KZ, /* 7945 */ + IC_EVEX_L2_W_XS_KZ, /* 7946 */ + IC_EVEX_L2_W_XS_KZ, /* 7947 */ + IC_EVEX_L2_W_XD_KZ, /* 7948 */ + IC_EVEX_L2_W_XD_KZ, /* 7949 */ + IC_EVEX_L2_W_XD_KZ, /* 7950 */ + IC_EVEX_L2_W_XD_KZ, /* 7951 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7952 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7953 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7954 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7955 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7956 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7957 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7958 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7959 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7960 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7961 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7962 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7963 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7964 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7965 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7966 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7967 */ + IC_EVEX_L2_KZ, /* 7968 */ + IC_EVEX_L2_KZ, /* 7969 */ + IC_EVEX_L2_XS_KZ, /* 7970 */ + IC_EVEX_L2_XS_KZ, /* 7971 */ + IC_EVEX_L2_XD_KZ, /* 7972 */ + IC_EVEX_L2_XD_KZ, /* 7973 */ + IC_EVEX_L2_XD_KZ, /* 7974 */ + IC_EVEX_L2_XD_KZ, /* 7975 */ + IC_EVEX_L2_W_KZ, /* 7976 */ + IC_EVEX_L2_W_KZ, /* 7977 */ + IC_EVEX_L2_W_XS_KZ, /* 7978 */ + IC_EVEX_L2_W_XS_KZ, /* 7979 */ + IC_EVEX_L2_W_XD_KZ, /* 7980 */ + IC_EVEX_L2_W_XD_KZ, /* 7981 */ + IC_EVEX_L2_W_XD_KZ, /* 7982 */ + IC_EVEX_L2_W_XD_KZ, /* 7983 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7984 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7985 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7986 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7987 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7988 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7989 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7990 */ + IC_EVEX_L2_OPSIZE_KZ, /* 7991 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7992 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7993 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7994 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7995 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7996 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7997 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7998 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 7999 */ + IC_EVEX_L2_KZ, /* 8000 */ + IC_EVEX_L2_KZ, /* 8001 */ + IC_EVEX_L2_XS_KZ, /* 8002 */ + IC_EVEX_L2_XS_KZ, /* 8003 */ + IC_EVEX_L2_XD_KZ, /* 8004 */ + IC_EVEX_L2_XD_KZ, /* 8005 */ + IC_EVEX_L2_XD_KZ, /* 8006 */ + IC_EVEX_L2_XD_KZ, /* 8007 */ + IC_EVEX_L2_W_KZ, /* 8008 */ + IC_EVEX_L2_W_KZ, /* 8009 */ + IC_EVEX_L2_W_XS_KZ, /* 8010 */ + IC_EVEX_L2_W_XS_KZ, /* 8011 */ + IC_EVEX_L2_W_XD_KZ, /* 8012 */ + IC_EVEX_L2_W_XD_KZ, /* 8013 */ + IC_EVEX_L2_W_XD_KZ, /* 8014 */ + IC_EVEX_L2_W_XD_KZ, /* 8015 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8016 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8017 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8018 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8019 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8020 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8021 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8022 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8023 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8024 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8025 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8026 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8027 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8028 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8029 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8030 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8031 */ + IC_EVEX_L2_KZ, /* 8032 */ + IC_EVEX_L2_KZ, /* 8033 */ + IC_EVEX_L2_XS_KZ, /* 8034 */ + IC_EVEX_L2_XS_KZ, /* 8035 */ + IC_EVEX_L2_XD_KZ, /* 8036 */ + IC_EVEX_L2_XD_KZ, /* 8037 */ + IC_EVEX_L2_XD_KZ, /* 8038 */ + IC_EVEX_L2_XD_KZ, /* 8039 */ + IC_EVEX_L2_W_KZ, /* 8040 */ + IC_EVEX_L2_W_KZ, /* 8041 */ + IC_EVEX_L2_W_XS_KZ, /* 8042 */ + IC_EVEX_L2_W_XS_KZ, /* 8043 */ + IC_EVEX_L2_W_XD_KZ, /* 8044 */ + IC_EVEX_L2_W_XD_KZ, /* 8045 */ + IC_EVEX_L2_W_XD_KZ, /* 8046 */ + IC_EVEX_L2_W_XD_KZ, /* 8047 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8048 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8049 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8050 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8051 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8052 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8053 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8054 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8055 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8056 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8057 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8058 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8059 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8060 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8061 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8062 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8063 */ + IC_EVEX_L2_KZ, /* 8064 */ + IC_EVEX_L2_KZ, /* 8065 */ + IC_EVEX_L2_XS_KZ, /* 8066 */ + IC_EVEX_L2_XS_KZ, /* 8067 */ + IC_EVEX_L2_XD_KZ, /* 8068 */ + IC_EVEX_L2_XD_KZ, /* 8069 */ + IC_EVEX_L2_XD_KZ, /* 8070 */ + IC_EVEX_L2_XD_KZ, /* 8071 */ + IC_EVEX_L2_W_KZ, /* 8072 */ + IC_EVEX_L2_W_KZ, /* 8073 */ + IC_EVEX_L2_W_XS_KZ, /* 8074 */ + IC_EVEX_L2_W_XS_KZ, /* 8075 */ + IC_EVEX_L2_W_XD_KZ, /* 8076 */ + IC_EVEX_L2_W_XD_KZ, /* 8077 */ + IC_EVEX_L2_W_XD_KZ, /* 8078 */ + IC_EVEX_L2_W_XD_KZ, /* 8079 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8080 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8081 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8082 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8083 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8084 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8085 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8086 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8087 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8088 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8089 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8090 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8091 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8092 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8093 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8094 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8095 */ + IC_EVEX_L2_KZ, /* 8096 */ + IC_EVEX_L2_KZ, /* 8097 */ + IC_EVEX_L2_XS_KZ, /* 8098 */ + IC_EVEX_L2_XS_KZ, /* 8099 */ + IC_EVEX_L2_XD_KZ, /* 8100 */ + IC_EVEX_L2_XD_KZ, /* 8101 */ + IC_EVEX_L2_XD_KZ, /* 8102 */ + IC_EVEX_L2_XD_KZ, /* 8103 */ + IC_EVEX_L2_W_KZ, /* 8104 */ + IC_EVEX_L2_W_KZ, /* 8105 */ + IC_EVEX_L2_W_XS_KZ, /* 8106 */ + IC_EVEX_L2_W_XS_KZ, /* 8107 */ + IC_EVEX_L2_W_XD_KZ, /* 8108 */ + IC_EVEX_L2_W_XD_KZ, /* 8109 */ + IC_EVEX_L2_W_XD_KZ, /* 8110 */ + IC_EVEX_L2_W_XD_KZ, /* 8111 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8112 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8113 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8114 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8115 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8116 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8117 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8118 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8119 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8120 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8121 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8122 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8123 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8124 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8125 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8126 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8127 */ + IC_EVEX_L2_KZ, /* 8128 */ + IC_EVEX_L2_KZ, /* 8129 */ + IC_EVEX_L2_XS_KZ, /* 8130 */ + IC_EVEX_L2_XS_KZ, /* 8131 */ + IC_EVEX_L2_XD_KZ, /* 8132 */ + IC_EVEX_L2_XD_KZ, /* 8133 */ + IC_EVEX_L2_XD_KZ, /* 8134 */ + IC_EVEX_L2_XD_KZ, /* 8135 */ + IC_EVEX_L2_W_KZ, /* 8136 */ + IC_EVEX_L2_W_KZ, /* 8137 */ + IC_EVEX_L2_W_XS_KZ, /* 8138 */ + IC_EVEX_L2_W_XS_KZ, /* 8139 */ + IC_EVEX_L2_W_XD_KZ, /* 8140 */ + IC_EVEX_L2_W_XD_KZ, /* 8141 */ + IC_EVEX_L2_W_XD_KZ, /* 8142 */ + IC_EVEX_L2_W_XD_KZ, /* 8143 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8144 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8145 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8146 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8147 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8148 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8149 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8150 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8151 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8152 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8153 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8154 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8155 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8156 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8157 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8158 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8159 */ + IC_EVEX_L2_KZ, /* 8160 */ + IC_EVEX_L2_KZ, /* 8161 */ + IC_EVEX_L2_XS_KZ, /* 8162 */ + IC_EVEX_L2_XS_KZ, /* 8163 */ + IC_EVEX_L2_XD_KZ, /* 8164 */ + IC_EVEX_L2_XD_KZ, /* 8165 */ + IC_EVEX_L2_XD_KZ, /* 8166 */ + IC_EVEX_L2_XD_KZ, /* 8167 */ + IC_EVEX_L2_W_KZ, /* 8168 */ + IC_EVEX_L2_W_KZ, /* 8169 */ + IC_EVEX_L2_W_XS_KZ, /* 8170 */ + IC_EVEX_L2_W_XS_KZ, /* 8171 */ + IC_EVEX_L2_W_XD_KZ, /* 8172 */ + IC_EVEX_L2_W_XD_KZ, /* 8173 */ + IC_EVEX_L2_W_XD_KZ, /* 8174 */ + IC_EVEX_L2_W_XD_KZ, /* 8175 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8176 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8177 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8178 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8179 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8180 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8181 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8182 */ + IC_EVEX_L2_OPSIZE_KZ, /* 8183 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8184 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8185 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8186 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8187 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8188 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8189 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8190 */ + IC_EVEX_L2_W_OPSIZE_KZ, /* 8191 */ + IC, /* 8192 */ + IC_64BIT, /* 8193 */ + IC_XS, /* 8194 */ + IC_64BIT_XS, /* 8195 */ + IC_XD, /* 8196 */ + IC_64BIT_XD, /* 8197 */ + IC_XS, /* 8198 */ + IC_64BIT_XS, /* 8199 */ + IC, /* 8200 */ + IC_64BIT_REXW, /* 8201 */ + IC_XS, /* 8202 */ + IC_64BIT_REXW_XS, /* 8203 */ + IC_XD, /* 8204 */ + IC_64BIT_REXW_XD, /* 8205 */ + IC_XS, /* 8206 */ + IC_64BIT_REXW_XS, /* 8207 */ + IC_OPSIZE, /* 8208 */ + IC_64BIT_OPSIZE, /* 8209 */ + IC_XS_OPSIZE, /* 8210 */ + IC_64BIT_XS_OPSIZE, /* 8211 */ + IC_XD_OPSIZE, /* 8212 */ + IC_64BIT_XD_OPSIZE, /* 8213 */ + IC_XS_OPSIZE, /* 8214 */ + IC_64BIT_XD_OPSIZE, /* 8215 */ + IC_OPSIZE, /* 8216 */ + IC_64BIT_REXW_OPSIZE, /* 8217 */ + IC_XS_OPSIZE, /* 8218 */ + IC_64BIT_REXW_XS, /* 8219 */ + IC_XD_OPSIZE, /* 8220 */ + IC_64BIT_REXW_XD, /* 8221 */ + IC_XS_OPSIZE, /* 8222 */ + IC_64BIT_REXW_XS, /* 8223 */ + IC_ADSIZE, /* 8224 */ + IC_64BIT_ADSIZE, /* 8225 */ + IC_XS_ADSIZE, /* 8226 */ + IC_64BIT_XS_ADSIZE, /* 8227 */ + IC_XD_ADSIZE, /* 8228 */ + IC_64BIT_XD_ADSIZE, /* 8229 */ + IC_XS_ADSIZE, /* 8230 */ + IC_64BIT_XD_ADSIZE, /* 8231 */ + IC_ADSIZE, /* 8232 */ + IC_64BIT_REXW_ADSIZE, /* 8233 */ + IC_XS_ADSIZE, /* 8234 */ + IC_64BIT_REXW_XS, /* 8235 */ + IC_XD_ADSIZE, /* 8236 */ + IC_64BIT_REXW_XD, /* 8237 */ + IC_XS_ADSIZE, /* 8238 */ + IC_64BIT_REXW_XS, /* 8239 */ + IC_OPSIZE_ADSIZE, /* 8240 */ + IC_64BIT_OPSIZE_ADSIZE, /* 8241 */ + IC_XS_OPSIZE, /* 8242 */ + IC_64BIT_XS_OPSIZE, /* 8243 */ + IC_XD_OPSIZE, /* 8244 */ + IC_64BIT_XD_OPSIZE, /* 8245 */ + IC_XS_OPSIZE, /* 8246 */ + IC_64BIT_XD_OPSIZE, /* 8247 */ + IC_OPSIZE_ADSIZE, /* 8248 */ + IC_64BIT_REXW_OPSIZE, /* 8249 */ + IC_XS_OPSIZE, /* 8250 */ + IC_64BIT_REXW_XS, /* 8251 */ + IC_XD_OPSIZE, /* 8252 */ + IC_64BIT_REXW_XD, /* 8253 */ + IC_XS_OPSIZE, /* 8254 */ + IC_64BIT_REXW_XS, /* 8255 */ + IC_VEX, /* 8256 */ + IC_VEX, /* 8257 */ + IC_VEX_XS, /* 8258 */ + IC_VEX_XS, /* 8259 */ + IC_VEX_XD, /* 8260 */ + IC_VEX_XD, /* 8261 */ + IC_VEX_XD, /* 8262 */ + IC_VEX_XD, /* 8263 */ + IC_VEX_W, /* 8264 */ + IC_VEX_W, /* 8265 */ + IC_VEX_W_XS, /* 8266 */ + IC_VEX_W_XS, /* 8267 */ + IC_VEX_W_XD, /* 8268 */ + IC_VEX_W_XD, /* 8269 */ + IC_VEX_W_XD, /* 8270 */ + IC_VEX_W_XD, /* 8271 */ + IC_VEX_OPSIZE, /* 8272 */ + IC_VEX_OPSIZE, /* 8273 */ + IC_VEX_OPSIZE, /* 8274 */ + IC_VEX_OPSIZE, /* 8275 */ + IC_VEX_OPSIZE, /* 8276 */ + IC_VEX_OPSIZE, /* 8277 */ + IC_VEX_OPSIZE, /* 8278 */ + IC_VEX_OPSIZE, /* 8279 */ + IC_VEX_W_OPSIZE, /* 8280 */ + IC_VEX_W_OPSIZE, /* 8281 */ + IC_VEX_W_OPSIZE, /* 8282 */ + IC_VEX_W_OPSIZE, /* 8283 */ + IC_VEX_W_OPSIZE, /* 8284 */ + IC_VEX_W_OPSIZE, /* 8285 */ + IC_VEX_W_OPSIZE, /* 8286 */ + IC_VEX_W_OPSIZE, /* 8287 */ + IC_VEX, /* 8288 */ + IC_VEX, /* 8289 */ + IC_VEX_XS, /* 8290 */ + IC_VEX_XS, /* 8291 */ + IC_VEX_XD, /* 8292 */ + IC_VEX_XD, /* 8293 */ + IC_VEX_XD, /* 8294 */ + IC_VEX_XD, /* 8295 */ + IC_VEX_W, /* 8296 */ + IC_VEX_W, /* 8297 */ + IC_VEX_W_XS, /* 8298 */ + IC_VEX_W_XS, /* 8299 */ + IC_VEX_W_XD, /* 8300 */ + IC_VEX_W_XD, /* 8301 */ + IC_VEX_W_XD, /* 8302 */ + IC_VEX_W_XD, /* 8303 */ + IC_VEX_OPSIZE, /* 8304 */ + IC_VEX_OPSIZE, /* 8305 */ + IC_VEX_OPSIZE, /* 8306 */ + IC_VEX_OPSIZE, /* 8307 */ + IC_VEX_OPSIZE, /* 8308 */ + IC_VEX_OPSIZE, /* 8309 */ + IC_VEX_OPSIZE, /* 8310 */ + IC_VEX_OPSIZE, /* 8311 */ + IC_VEX_W_OPSIZE, /* 8312 */ + IC_VEX_W_OPSIZE, /* 8313 */ + IC_VEX_W_OPSIZE, /* 8314 */ + IC_VEX_W_OPSIZE, /* 8315 */ + IC_VEX_W_OPSIZE, /* 8316 */ + IC_VEX_W_OPSIZE, /* 8317 */ + IC_VEX_W_OPSIZE, /* 8318 */ + IC_VEX_W_OPSIZE, /* 8319 */ + IC_VEX_L, /* 8320 */ + IC_VEX_L, /* 8321 */ + IC_VEX_L_XS, /* 8322 */ + IC_VEX_L_XS, /* 8323 */ + IC_VEX_L_XD, /* 8324 */ + IC_VEX_L_XD, /* 8325 */ + IC_VEX_L_XD, /* 8326 */ + IC_VEX_L_XD, /* 8327 */ + IC_VEX_L_W, /* 8328 */ + IC_VEX_L_W, /* 8329 */ + IC_VEX_L_W_XS, /* 8330 */ + IC_VEX_L_W_XS, /* 8331 */ + IC_VEX_L_W_XD, /* 8332 */ + IC_VEX_L_W_XD, /* 8333 */ + IC_VEX_L_W_XD, /* 8334 */ + IC_VEX_L_W_XD, /* 8335 */ + IC_VEX_L_OPSIZE, /* 8336 */ + IC_VEX_L_OPSIZE, /* 8337 */ + IC_VEX_L_OPSIZE, /* 8338 */ + IC_VEX_L_OPSIZE, /* 8339 */ + IC_VEX_L_OPSIZE, /* 8340 */ + IC_VEX_L_OPSIZE, /* 8341 */ + IC_VEX_L_OPSIZE, /* 8342 */ + IC_VEX_L_OPSIZE, /* 8343 */ + IC_VEX_L_W_OPSIZE, /* 8344 */ + IC_VEX_L_W_OPSIZE, /* 8345 */ + IC_VEX_L_W_OPSIZE, /* 8346 */ + IC_VEX_L_W_OPSIZE, /* 8347 */ + IC_VEX_L_W_OPSIZE, /* 8348 */ + IC_VEX_L_W_OPSIZE, /* 8349 */ + IC_VEX_L_W_OPSIZE, /* 8350 */ + IC_VEX_L_W_OPSIZE, /* 8351 */ + IC_VEX_L, /* 8352 */ + IC_VEX_L, /* 8353 */ + IC_VEX_L_XS, /* 8354 */ + IC_VEX_L_XS, /* 8355 */ + IC_VEX_L_XD, /* 8356 */ + IC_VEX_L_XD, /* 8357 */ + IC_VEX_L_XD, /* 8358 */ + IC_VEX_L_XD, /* 8359 */ + IC_VEX_L_W, /* 8360 */ + IC_VEX_L_W, /* 8361 */ + IC_VEX_L_W_XS, /* 8362 */ + IC_VEX_L_W_XS, /* 8363 */ + IC_VEX_L_W_XD, /* 8364 */ + IC_VEX_L_W_XD, /* 8365 */ + IC_VEX_L_W_XD, /* 8366 */ + IC_VEX_L_W_XD, /* 8367 */ + IC_VEX_L_OPSIZE, /* 8368 */ + IC_VEX_L_OPSIZE, /* 8369 */ + IC_VEX_L_OPSIZE, /* 8370 */ + IC_VEX_L_OPSIZE, /* 8371 */ + IC_VEX_L_OPSIZE, /* 8372 */ + IC_VEX_L_OPSIZE, /* 8373 */ + IC_VEX_L_OPSIZE, /* 8374 */ + IC_VEX_L_OPSIZE, /* 8375 */ + IC_VEX_L_W_OPSIZE, /* 8376 */ + IC_VEX_L_W_OPSIZE, /* 8377 */ + IC_VEX_L_W_OPSIZE, /* 8378 */ + IC_VEX_L_W_OPSIZE, /* 8379 */ + IC_VEX_L_W_OPSIZE, /* 8380 */ + IC_VEX_L_W_OPSIZE, /* 8381 */ + IC_VEX_L_W_OPSIZE, /* 8382 */ + IC_VEX_L_W_OPSIZE, /* 8383 */ + IC_VEX_L, /* 8384 */ + IC_VEX_L, /* 8385 */ + IC_VEX_L_XS, /* 8386 */ + IC_VEX_L_XS, /* 8387 */ + IC_VEX_L_XD, /* 8388 */ + IC_VEX_L_XD, /* 8389 */ + IC_VEX_L_XD, /* 8390 */ + IC_VEX_L_XD, /* 8391 */ + IC_VEX_L_W, /* 8392 */ + IC_VEX_L_W, /* 8393 */ + IC_VEX_L_W_XS, /* 8394 */ + IC_VEX_L_W_XS, /* 8395 */ + IC_VEX_L_W_XD, /* 8396 */ + IC_VEX_L_W_XD, /* 8397 */ + IC_VEX_L_W_XD, /* 8398 */ + IC_VEX_L_W_XD, /* 8399 */ + IC_VEX_L_OPSIZE, /* 8400 */ + IC_VEX_L_OPSIZE, /* 8401 */ + IC_VEX_L_OPSIZE, /* 8402 */ + IC_VEX_L_OPSIZE, /* 8403 */ + IC_VEX_L_OPSIZE, /* 8404 */ + IC_VEX_L_OPSIZE, /* 8405 */ + IC_VEX_L_OPSIZE, /* 8406 */ + IC_VEX_L_OPSIZE, /* 8407 */ + IC_VEX_L_W_OPSIZE, /* 8408 */ + IC_VEX_L_W_OPSIZE, /* 8409 */ + IC_VEX_L_W_OPSIZE, /* 8410 */ + IC_VEX_L_W_OPSIZE, /* 8411 */ + IC_VEX_L_W_OPSIZE, /* 8412 */ + IC_VEX_L_W_OPSIZE, /* 8413 */ + IC_VEX_L_W_OPSIZE, /* 8414 */ + IC_VEX_L_W_OPSIZE, /* 8415 */ + IC_VEX_L, /* 8416 */ + IC_VEX_L, /* 8417 */ + IC_VEX_L_XS, /* 8418 */ + IC_VEX_L_XS, /* 8419 */ + IC_VEX_L_XD, /* 8420 */ + IC_VEX_L_XD, /* 8421 */ + IC_VEX_L_XD, /* 8422 */ + IC_VEX_L_XD, /* 8423 */ + IC_VEX_L_W, /* 8424 */ + IC_VEX_L_W, /* 8425 */ + IC_VEX_L_W_XS, /* 8426 */ + IC_VEX_L_W_XS, /* 8427 */ + IC_VEX_L_W_XD, /* 8428 */ + IC_VEX_L_W_XD, /* 8429 */ + IC_VEX_L_W_XD, /* 8430 */ + IC_VEX_L_W_XD, /* 8431 */ + IC_VEX_L_OPSIZE, /* 8432 */ + IC_VEX_L_OPSIZE, /* 8433 */ + IC_VEX_L_OPSIZE, /* 8434 */ + IC_VEX_L_OPSIZE, /* 8435 */ + IC_VEX_L_OPSIZE, /* 8436 */ + IC_VEX_L_OPSIZE, /* 8437 */ + IC_VEX_L_OPSIZE, /* 8438 */ + IC_VEX_L_OPSIZE, /* 8439 */ + IC_VEX_L_W_OPSIZE, /* 8440 */ + IC_VEX_L_W_OPSIZE, /* 8441 */ + IC_VEX_L_W_OPSIZE, /* 8442 */ + IC_VEX_L_W_OPSIZE, /* 8443 */ + IC_VEX_L_W_OPSIZE, /* 8444 */ + IC_VEX_L_W_OPSIZE, /* 8445 */ + IC_VEX_L_W_OPSIZE, /* 8446 */ + IC_VEX_L_W_OPSIZE, /* 8447 */ + IC_EVEX_B, /* 8448 */ + IC_EVEX_B, /* 8449 */ + IC_EVEX_XS_B, /* 8450 */ + IC_EVEX_XS_B, /* 8451 */ + IC_EVEX_XD_B, /* 8452 */ + IC_EVEX_XD_B, /* 8453 */ + IC_EVEX_XD_B, /* 8454 */ + IC_EVEX_XD_B, /* 8455 */ + IC_EVEX_W_B, /* 8456 */ + IC_EVEX_W_B, /* 8457 */ + IC_EVEX_W_XS_B, /* 8458 */ + IC_EVEX_W_XS_B, /* 8459 */ + IC_EVEX_W_XD_B, /* 8460 */ + IC_EVEX_W_XD_B, /* 8461 */ + IC_EVEX_W_XD_B, /* 8462 */ + IC_EVEX_W_XD_B, /* 8463 */ + IC_EVEX_OPSIZE_B, /* 8464 */ + IC_EVEX_OPSIZE_B, /* 8465 */ + IC_EVEX_OPSIZE_B, /* 8466 */ + IC_EVEX_OPSIZE_B, /* 8467 */ + IC_EVEX_OPSIZE_B, /* 8468 */ + IC_EVEX_OPSIZE_B, /* 8469 */ + IC_EVEX_OPSIZE_B, /* 8470 */ + IC_EVEX_OPSIZE_B, /* 8471 */ + IC_EVEX_W_OPSIZE_B, /* 8472 */ + IC_EVEX_W_OPSIZE_B, /* 8473 */ + IC_EVEX_W_OPSIZE_B, /* 8474 */ + IC_EVEX_W_OPSIZE_B, /* 8475 */ + IC_EVEX_W_OPSIZE_B, /* 8476 */ + IC_EVEX_W_OPSIZE_B, /* 8477 */ + IC_EVEX_W_OPSIZE_B, /* 8478 */ + IC_EVEX_W_OPSIZE_B, /* 8479 */ + IC_EVEX_B, /* 8480 */ + IC_EVEX_B, /* 8481 */ + IC_EVEX_XS_B, /* 8482 */ + IC_EVEX_XS_B, /* 8483 */ + IC_EVEX_XD_B, /* 8484 */ + IC_EVEX_XD_B, /* 8485 */ + IC_EVEX_XD_B, /* 8486 */ + IC_EVEX_XD_B, /* 8487 */ + IC_EVEX_W_B, /* 8488 */ + IC_EVEX_W_B, /* 8489 */ + IC_EVEX_W_XS_B, /* 8490 */ + IC_EVEX_W_XS_B, /* 8491 */ + IC_EVEX_W_XD_B, /* 8492 */ + IC_EVEX_W_XD_B, /* 8493 */ + IC_EVEX_W_XD_B, /* 8494 */ + IC_EVEX_W_XD_B, /* 8495 */ + IC_EVEX_OPSIZE_B, /* 8496 */ + IC_EVEX_OPSIZE_B, /* 8497 */ + IC_EVEX_OPSIZE_B, /* 8498 */ + IC_EVEX_OPSIZE_B, /* 8499 */ + IC_EVEX_OPSIZE_B, /* 8500 */ + IC_EVEX_OPSIZE_B, /* 8501 */ + IC_EVEX_OPSIZE_B, /* 8502 */ + IC_EVEX_OPSIZE_B, /* 8503 */ + IC_EVEX_W_OPSIZE_B, /* 8504 */ + IC_EVEX_W_OPSIZE_B, /* 8505 */ + IC_EVEX_W_OPSIZE_B, /* 8506 */ + IC_EVEX_W_OPSIZE_B, /* 8507 */ + IC_EVEX_W_OPSIZE_B, /* 8508 */ + IC_EVEX_W_OPSIZE_B, /* 8509 */ + IC_EVEX_W_OPSIZE_B, /* 8510 */ + IC_EVEX_W_OPSIZE_B, /* 8511 */ + IC_EVEX_B, /* 8512 */ + IC_EVEX_B, /* 8513 */ + IC_EVEX_XS_B, /* 8514 */ + IC_EVEX_XS_B, /* 8515 */ + IC_EVEX_XD_B, /* 8516 */ + IC_EVEX_XD_B, /* 8517 */ + IC_EVEX_XD_B, /* 8518 */ + IC_EVEX_XD_B, /* 8519 */ + IC_EVEX_W_B, /* 8520 */ + IC_EVEX_W_B, /* 8521 */ + IC_EVEX_W_XS_B, /* 8522 */ + IC_EVEX_W_XS_B, /* 8523 */ + IC_EVEX_W_XD_B, /* 8524 */ + IC_EVEX_W_XD_B, /* 8525 */ + IC_EVEX_W_XD_B, /* 8526 */ + IC_EVEX_W_XD_B, /* 8527 */ + IC_EVEX_OPSIZE_B, /* 8528 */ + IC_EVEX_OPSIZE_B, /* 8529 */ + IC_EVEX_OPSIZE_B, /* 8530 */ + IC_EVEX_OPSIZE_B, /* 8531 */ + IC_EVEX_OPSIZE_B, /* 8532 */ + IC_EVEX_OPSIZE_B, /* 8533 */ + IC_EVEX_OPSIZE_B, /* 8534 */ + IC_EVEX_OPSIZE_B, /* 8535 */ + IC_EVEX_W_OPSIZE_B, /* 8536 */ + IC_EVEX_W_OPSIZE_B, /* 8537 */ + IC_EVEX_W_OPSIZE_B, /* 8538 */ + IC_EVEX_W_OPSIZE_B, /* 8539 */ + IC_EVEX_W_OPSIZE_B, /* 8540 */ + IC_EVEX_W_OPSIZE_B, /* 8541 */ + IC_EVEX_W_OPSIZE_B, /* 8542 */ + IC_EVEX_W_OPSIZE_B, /* 8543 */ + IC_EVEX_B, /* 8544 */ + IC_EVEX_B, /* 8545 */ + IC_EVEX_XS_B, /* 8546 */ + IC_EVEX_XS_B, /* 8547 */ + IC_EVEX_XD_B, /* 8548 */ + IC_EVEX_XD_B, /* 8549 */ + IC_EVEX_XD_B, /* 8550 */ + IC_EVEX_XD_B, /* 8551 */ + IC_EVEX_W_B, /* 8552 */ + IC_EVEX_W_B, /* 8553 */ + IC_EVEX_W_XS_B, /* 8554 */ + IC_EVEX_W_XS_B, /* 8555 */ + IC_EVEX_W_XD_B, /* 8556 */ + IC_EVEX_W_XD_B, /* 8557 */ + IC_EVEX_W_XD_B, /* 8558 */ + IC_EVEX_W_XD_B, /* 8559 */ + IC_EVEX_OPSIZE_B, /* 8560 */ + IC_EVEX_OPSIZE_B, /* 8561 */ + IC_EVEX_OPSIZE_B, /* 8562 */ + IC_EVEX_OPSIZE_B, /* 8563 */ + IC_EVEX_OPSIZE_B, /* 8564 */ + IC_EVEX_OPSIZE_B, /* 8565 */ + IC_EVEX_OPSIZE_B, /* 8566 */ + IC_EVEX_OPSIZE_B, /* 8567 */ + IC_EVEX_W_OPSIZE_B, /* 8568 */ + IC_EVEX_W_OPSIZE_B, /* 8569 */ + IC_EVEX_W_OPSIZE_B, /* 8570 */ + IC_EVEX_W_OPSIZE_B, /* 8571 */ + IC_EVEX_W_OPSIZE_B, /* 8572 */ + IC_EVEX_W_OPSIZE_B, /* 8573 */ + IC_EVEX_W_OPSIZE_B, /* 8574 */ + IC_EVEX_W_OPSIZE_B, /* 8575 */ + IC_EVEX_B, /* 8576 */ + IC_EVEX_B, /* 8577 */ + IC_EVEX_XS_B, /* 8578 */ + IC_EVEX_XS_B, /* 8579 */ + IC_EVEX_XD_B, /* 8580 */ + IC_EVEX_XD_B, /* 8581 */ + IC_EVEX_XD_B, /* 8582 */ + IC_EVEX_XD_B, /* 8583 */ + IC_EVEX_W_B, /* 8584 */ + IC_EVEX_W_B, /* 8585 */ + IC_EVEX_W_XS_B, /* 8586 */ + IC_EVEX_W_XS_B, /* 8587 */ + IC_EVEX_W_XD_B, /* 8588 */ + IC_EVEX_W_XD_B, /* 8589 */ + IC_EVEX_W_XD_B, /* 8590 */ + IC_EVEX_W_XD_B, /* 8591 */ + IC_EVEX_OPSIZE_B, /* 8592 */ + IC_EVEX_OPSIZE_B, /* 8593 */ + IC_EVEX_OPSIZE_B, /* 8594 */ + IC_EVEX_OPSIZE_B, /* 8595 */ + IC_EVEX_OPSIZE_B, /* 8596 */ + IC_EVEX_OPSIZE_B, /* 8597 */ + IC_EVEX_OPSIZE_B, /* 8598 */ + IC_EVEX_OPSIZE_B, /* 8599 */ + IC_EVEX_W_OPSIZE_B, /* 8600 */ + IC_EVEX_W_OPSIZE_B, /* 8601 */ + IC_EVEX_W_OPSIZE_B, /* 8602 */ + IC_EVEX_W_OPSIZE_B, /* 8603 */ + IC_EVEX_W_OPSIZE_B, /* 8604 */ + IC_EVEX_W_OPSIZE_B, /* 8605 */ + IC_EVEX_W_OPSIZE_B, /* 8606 */ + IC_EVEX_W_OPSIZE_B, /* 8607 */ + IC_EVEX_B, /* 8608 */ + IC_EVEX_B, /* 8609 */ + IC_EVEX_XS_B, /* 8610 */ + IC_EVEX_XS_B, /* 8611 */ + IC_EVEX_XD_B, /* 8612 */ + IC_EVEX_XD_B, /* 8613 */ + IC_EVEX_XD_B, /* 8614 */ + IC_EVEX_XD_B, /* 8615 */ + IC_EVEX_W_B, /* 8616 */ + IC_EVEX_W_B, /* 8617 */ + IC_EVEX_W_XS_B, /* 8618 */ + IC_EVEX_W_XS_B, /* 8619 */ + IC_EVEX_W_XD_B, /* 8620 */ + IC_EVEX_W_XD_B, /* 8621 */ + IC_EVEX_W_XD_B, /* 8622 */ + IC_EVEX_W_XD_B, /* 8623 */ + IC_EVEX_OPSIZE_B, /* 8624 */ + IC_EVEX_OPSIZE_B, /* 8625 */ + IC_EVEX_OPSIZE_B, /* 8626 */ + IC_EVEX_OPSIZE_B, /* 8627 */ + IC_EVEX_OPSIZE_B, /* 8628 */ + IC_EVEX_OPSIZE_B, /* 8629 */ + IC_EVEX_OPSIZE_B, /* 8630 */ + IC_EVEX_OPSIZE_B, /* 8631 */ + IC_EVEX_W_OPSIZE_B, /* 8632 */ + IC_EVEX_W_OPSIZE_B, /* 8633 */ + IC_EVEX_W_OPSIZE_B, /* 8634 */ + IC_EVEX_W_OPSIZE_B, /* 8635 */ + IC_EVEX_W_OPSIZE_B, /* 8636 */ + IC_EVEX_W_OPSIZE_B, /* 8637 */ + IC_EVEX_W_OPSIZE_B, /* 8638 */ + IC_EVEX_W_OPSIZE_B, /* 8639 */ + IC_EVEX_B, /* 8640 */ + IC_EVEX_B, /* 8641 */ + IC_EVEX_XS_B, /* 8642 */ + IC_EVEX_XS_B, /* 8643 */ + IC_EVEX_XD_B, /* 8644 */ + IC_EVEX_XD_B, /* 8645 */ + IC_EVEX_XD_B, /* 8646 */ + IC_EVEX_XD_B, /* 8647 */ + IC_EVEX_W_B, /* 8648 */ + IC_EVEX_W_B, /* 8649 */ + IC_EVEX_W_XS_B, /* 8650 */ + IC_EVEX_W_XS_B, /* 8651 */ + IC_EVEX_W_XD_B, /* 8652 */ + IC_EVEX_W_XD_B, /* 8653 */ + IC_EVEX_W_XD_B, /* 8654 */ + IC_EVEX_W_XD_B, /* 8655 */ + IC_EVEX_OPSIZE_B, /* 8656 */ + IC_EVEX_OPSIZE_B, /* 8657 */ + IC_EVEX_OPSIZE_B, /* 8658 */ + IC_EVEX_OPSIZE_B, /* 8659 */ + IC_EVEX_OPSIZE_B, /* 8660 */ + IC_EVEX_OPSIZE_B, /* 8661 */ + IC_EVEX_OPSIZE_B, /* 8662 */ + IC_EVEX_OPSIZE_B, /* 8663 */ + IC_EVEX_W_OPSIZE_B, /* 8664 */ + IC_EVEX_W_OPSIZE_B, /* 8665 */ + IC_EVEX_W_OPSIZE_B, /* 8666 */ + IC_EVEX_W_OPSIZE_B, /* 8667 */ + IC_EVEX_W_OPSIZE_B, /* 8668 */ + IC_EVEX_W_OPSIZE_B, /* 8669 */ + IC_EVEX_W_OPSIZE_B, /* 8670 */ + IC_EVEX_W_OPSIZE_B, /* 8671 */ + IC_EVEX_B, /* 8672 */ + IC_EVEX_B, /* 8673 */ + IC_EVEX_XS_B, /* 8674 */ + IC_EVEX_XS_B, /* 8675 */ + IC_EVEX_XD_B, /* 8676 */ + IC_EVEX_XD_B, /* 8677 */ + IC_EVEX_XD_B, /* 8678 */ + IC_EVEX_XD_B, /* 8679 */ + IC_EVEX_W_B, /* 8680 */ + IC_EVEX_W_B, /* 8681 */ + IC_EVEX_W_XS_B, /* 8682 */ + IC_EVEX_W_XS_B, /* 8683 */ + IC_EVEX_W_XD_B, /* 8684 */ + IC_EVEX_W_XD_B, /* 8685 */ + IC_EVEX_W_XD_B, /* 8686 */ + IC_EVEX_W_XD_B, /* 8687 */ + IC_EVEX_OPSIZE_B, /* 8688 */ + IC_EVEX_OPSIZE_B, /* 8689 */ + IC_EVEX_OPSIZE_B, /* 8690 */ + IC_EVEX_OPSIZE_B, /* 8691 */ + IC_EVEX_OPSIZE_B, /* 8692 */ + IC_EVEX_OPSIZE_B, /* 8693 */ + IC_EVEX_OPSIZE_B, /* 8694 */ + IC_EVEX_OPSIZE_B, /* 8695 */ + IC_EVEX_W_OPSIZE_B, /* 8696 */ + IC_EVEX_W_OPSIZE_B, /* 8697 */ + IC_EVEX_W_OPSIZE_B, /* 8698 */ + IC_EVEX_W_OPSIZE_B, /* 8699 */ + IC_EVEX_W_OPSIZE_B, /* 8700 */ + IC_EVEX_W_OPSIZE_B, /* 8701 */ + IC_EVEX_W_OPSIZE_B, /* 8702 */ + IC_EVEX_W_OPSIZE_B, /* 8703 */ + IC, /* 8704 */ + IC_64BIT, /* 8705 */ + IC_XS, /* 8706 */ + IC_64BIT_XS, /* 8707 */ + IC_XD, /* 8708 */ + IC_64BIT_XD, /* 8709 */ + IC_XS, /* 8710 */ + IC_64BIT_XS, /* 8711 */ + IC, /* 8712 */ + IC_64BIT_REXW, /* 8713 */ + IC_XS, /* 8714 */ + IC_64BIT_REXW_XS, /* 8715 */ + IC_XD, /* 8716 */ + IC_64BIT_REXW_XD, /* 8717 */ + IC_XS, /* 8718 */ + IC_64BIT_REXW_XS, /* 8719 */ + IC_OPSIZE, /* 8720 */ + IC_64BIT_OPSIZE, /* 8721 */ + IC_XS_OPSIZE, /* 8722 */ + IC_64BIT_XS_OPSIZE, /* 8723 */ + IC_XD_OPSIZE, /* 8724 */ + IC_64BIT_XD_OPSIZE, /* 8725 */ + IC_XS_OPSIZE, /* 8726 */ + IC_64BIT_XD_OPSIZE, /* 8727 */ + IC_OPSIZE, /* 8728 */ + IC_64BIT_REXW_OPSIZE, /* 8729 */ + IC_XS_OPSIZE, /* 8730 */ + IC_64BIT_REXW_XS, /* 8731 */ + IC_XD_OPSIZE, /* 8732 */ + IC_64BIT_REXW_XD, /* 8733 */ + IC_XS_OPSIZE, /* 8734 */ + IC_64BIT_REXW_XS, /* 8735 */ + IC_ADSIZE, /* 8736 */ + IC_64BIT_ADSIZE, /* 8737 */ + IC_XS_ADSIZE, /* 8738 */ + IC_64BIT_XS_ADSIZE, /* 8739 */ + IC_XD_ADSIZE, /* 8740 */ + IC_64BIT_XD_ADSIZE, /* 8741 */ + IC_XS_ADSIZE, /* 8742 */ + IC_64BIT_XD_ADSIZE, /* 8743 */ + IC_ADSIZE, /* 8744 */ + IC_64BIT_REXW_ADSIZE, /* 8745 */ + IC_XS_ADSIZE, /* 8746 */ + IC_64BIT_REXW_XS, /* 8747 */ + IC_XD_ADSIZE, /* 8748 */ + IC_64BIT_REXW_XD, /* 8749 */ + IC_XS_ADSIZE, /* 8750 */ + IC_64BIT_REXW_XS, /* 8751 */ + IC_OPSIZE_ADSIZE, /* 8752 */ + IC_64BIT_OPSIZE_ADSIZE, /* 8753 */ + IC_XS_OPSIZE, /* 8754 */ + IC_64BIT_XS_OPSIZE, /* 8755 */ + IC_XD_OPSIZE, /* 8756 */ + IC_64BIT_XD_OPSIZE, /* 8757 */ + IC_XS_OPSIZE, /* 8758 */ + IC_64BIT_XD_OPSIZE, /* 8759 */ + IC_OPSIZE_ADSIZE, /* 8760 */ + IC_64BIT_REXW_OPSIZE, /* 8761 */ + IC_XS_OPSIZE, /* 8762 */ + IC_64BIT_REXW_XS, /* 8763 */ + IC_XD_OPSIZE, /* 8764 */ + IC_64BIT_REXW_XD, /* 8765 */ + IC_XS_OPSIZE, /* 8766 */ + IC_64BIT_REXW_XS, /* 8767 */ + IC_VEX, /* 8768 */ + IC_VEX, /* 8769 */ + IC_VEX_XS, /* 8770 */ + IC_VEX_XS, /* 8771 */ + IC_VEX_XD, /* 8772 */ + IC_VEX_XD, /* 8773 */ + IC_VEX_XD, /* 8774 */ + IC_VEX_XD, /* 8775 */ + IC_VEX_W, /* 8776 */ + IC_VEX_W, /* 8777 */ + IC_VEX_W_XS, /* 8778 */ + IC_VEX_W_XS, /* 8779 */ + IC_VEX_W_XD, /* 8780 */ + IC_VEX_W_XD, /* 8781 */ + IC_VEX_W_XD, /* 8782 */ + IC_VEX_W_XD, /* 8783 */ + IC_VEX_OPSIZE, /* 8784 */ + IC_VEX_OPSIZE, /* 8785 */ + IC_VEX_OPSIZE, /* 8786 */ + IC_VEX_OPSIZE, /* 8787 */ + IC_VEX_OPSIZE, /* 8788 */ + IC_VEX_OPSIZE, /* 8789 */ + IC_VEX_OPSIZE, /* 8790 */ + IC_VEX_OPSIZE, /* 8791 */ + IC_VEX_W_OPSIZE, /* 8792 */ + IC_VEX_W_OPSIZE, /* 8793 */ + IC_VEX_W_OPSIZE, /* 8794 */ + IC_VEX_W_OPSIZE, /* 8795 */ + IC_VEX_W_OPSIZE, /* 8796 */ + IC_VEX_W_OPSIZE, /* 8797 */ + IC_VEX_W_OPSIZE, /* 8798 */ + IC_VEX_W_OPSIZE, /* 8799 */ + IC_VEX, /* 8800 */ + IC_VEX, /* 8801 */ + IC_VEX_XS, /* 8802 */ + IC_VEX_XS, /* 8803 */ + IC_VEX_XD, /* 8804 */ + IC_VEX_XD, /* 8805 */ + IC_VEX_XD, /* 8806 */ + IC_VEX_XD, /* 8807 */ + IC_VEX_W, /* 8808 */ + IC_VEX_W, /* 8809 */ + IC_VEX_W_XS, /* 8810 */ + IC_VEX_W_XS, /* 8811 */ + IC_VEX_W_XD, /* 8812 */ + IC_VEX_W_XD, /* 8813 */ + IC_VEX_W_XD, /* 8814 */ + IC_VEX_W_XD, /* 8815 */ + IC_VEX_OPSIZE, /* 8816 */ + IC_VEX_OPSIZE, /* 8817 */ + IC_VEX_OPSIZE, /* 8818 */ + IC_VEX_OPSIZE, /* 8819 */ + IC_VEX_OPSIZE, /* 8820 */ + IC_VEX_OPSIZE, /* 8821 */ + IC_VEX_OPSIZE, /* 8822 */ + IC_VEX_OPSIZE, /* 8823 */ + IC_VEX_W_OPSIZE, /* 8824 */ + IC_VEX_W_OPSIZE, /* 8825 */ + IC_VEX_W_OPSIZE, /* 8826 */ + IC_VEX_W_OPSIZE, /* 8827 */ + IC_VEX_W_OPSIZE, /* 8828 */ + IC_VEX_W_OPSIZE, /* 8829 */ + IC_VEX_W_OPSIZE, /* 8830 */ + IC_VEX_W_OPSIZE, /* 8831 */ + IC_VEX_L, /* 8832 */ + IC_VEX_L, /* 8833 */ + IC_VEX_L_XS, /* 8834 */ + IC_VEX_L_XS, /* 8835 */ + IC_VEX_L_XD, /* 8836 */ + IC_VEX_L_XD, /* 8837 */ + IC_VEX_L_XD, /* 8838 */ + IC_VEX_L_XD, /* 8839 */ + IC_VEX_L_W, /* 8840 */ + IC_VEX_L_W, /* 8841 */ + IC_VEX_L_W_XS, /* 8842 */ + IC_VEX_L_W_XS, /* 8843 */ + IC_VEX_L_W_XD, /* 8844 */ + IC_VEX_L_W_XD, /* 8845 */ + IC_VEX_L_W_XD, /* 8846 */ + IC_VEX_L_W_XD, /* 8847 */ + IC_VEX_L_OPSIZE, /* 8848 */ + IC_VEX_L_OPSIZE, /* 8849 */ + IC_VEX_L_OPSIZE, /* 8850 */ + IC_VEX_L_OPSIZE, /* 8851 */ + IC_VEX_L_OPSIZE, /* 8852 */ + IC_VEX_L_OPSIZE, /* 8853 */ + IC_VEX_L_OPSIZE, /* 8854 */ + IC_VEX_L_OPSIZE, /* 8855 */ + IC_VEX_L_W_OPSIZE, /* 8856 */ + IC_VEX_L_W_OPSIZE, /* 8857 */ + IC_VEX_L_W_OPSIZE, /* 8858 */ + IC_VEX_L_W_OPSIZE, /* 8859 */ + IC_VEX_L_W_OPSIZE, /* 8860 */ + IC_VEX_L_W_OPSIZE, /* 8861 */ + IC_VEX_L_W_OPSIZE, /* 8862 */ + IC_VEX_L_W_OPSIZE, /* 8863 */ + IC_VEX_L, /* 8864 */ + IC_VEX_L, /* 8865 */ + IC_VEX_L_XS, /* 8866 */ + IC_VEX_L_XS, /* 8867 */ + IC_VEX_L_XD, /* 8868 */ + IC_VEX_L_XD, /* 8869 */ + IC_VEX_L_XD, /* 8870 */ + IC_VEX_L_XD, /* 8871 */ + IC_VEX_L_W, /* 8872 */ + IC_VEX_L_W, /* 8873 */ + IC_VEX_L_W_XS, /* 8874 */ + IC_VEX_L_W_XS, /* 8875 */ + IC_VEX_L_W_XD, /* 8876 */ + IC_VEX_L_W_XD, /* 8877 */ + IC_VEX_L_W_XD, /* 8878 */ + IC_VEX_L_W_XD, /* 8879 */ + IC_VEX_L_OPSIZE, /* 8880 */ + IC_VEX_L_OPSIZE, /* 8881 */ + IC_VEX_L_OPSIZE, /* 8882 */ + IC_VEX_L_OPSIZE, /* 8883 */ + IC_VEX_L_OPSIZE, /* 8884 */ + IC_VEX_L_OPSIZE, /* 8885 */ + IC_VEX_L_OPSIZE, /* 8886 */ + IC_VEX_L_OPSIZE, /* 8887 */ + IC_VEX_L_W_OPSIZE, /* 8888 */ + IC_VEX_L_W_OPSIZE, /* 8889 */ + IC_VEX_L_W_OPSIZE, /* 8890 */ + IC_VEX_L_W_OPSIZE, /* 8891 */ + IC_VEX_L_W_OPSIZE, /* 8892 */ + IC_VEX_L_W_OPSIZE, /* 8893 */ + IC_VEX_L_W_OPSIZE, /* 8894 */ + IC_VEX_L_W_OPSIZE, /* 8895 */ + IC_VEX_L, /* 8896 */ + IC_VEX_L, /* 8897 */ + IC_VEX_L_XS, /* 8898 */ + IC_VEX_L_XS, /* 8899 */ + IC_VEX_L_XD, /* 8900 */ + IC_VEX_L_XD, /* 8901 */ + IC_VEX_L_XD, /* 8902 */ + IC_VEX_L_XD, /* 8903 */ + IC_VEX_L_W, /* 8904 */ + IC_VEX_L_W, /* 8905 */ + IC_VEX_L_W_XS, /* 8906 */ + IC_VEX_L_W_XS, /* 8907 */ + IC_VEX_L_W_XD, /* 8908 */ + IC_VEX_L_W_XD, /* 8909 */ + IC_VEX_L_W_XD, /* 8910 */ + IC_VEX_L_W_XD, /* 8911 */ + IC_VEX_L_OPSIZE, /* 8912 */ + IC_VEX_L_OPSIZE, /* 8913 */ + IC_VEX_L_OPSIZE, /* 8914 */ + IC_VEX_L_OPSIZE, /* 8915 */ + IC_VEX_L_OPSIZE, /* 8916 */ + IC_VEX_L_OPSIZE, /* 8917 */ + IC_VEX_L_OPSIZE, /* 8918 */ + IC_VEX_L_OPSIZE, /* 8919 */ + IC_VEX_L_W_OPSIZE, /* 8920 */ + IC_VEX_L_W_OPSIZE, /* 8921 */ + IC_VEX_L_W_OPSIZE, /* 8922 */ + IC_VEX_L_W_OPSIZE, /* 8923 */ + IC_VEX_L_W_OPSIZE, /* 8924 */ + IC_VEX_L_W_OPSIZE, /* 8925 */ + IC_VEX_L_W_OPSIZE, /* 8926 */ + IC_VEX_L_W_OPSIZE, /* 8927 */ + IC_VEX_L, /* 8928 */ + IC_VEX_L, /* 8929 */ + IC_VEX_L_XS, /* 8930 */ + IC_VEX_L_XS, /* 8931 */ + IC_VEX_L_XD, /* 8932 */ + IC_VEX_L_XD, /* 8933 */ + IC_VEX_L_XD, /* 8934 */ + IC_VEX_L_XD, /* 8935 */ + IC_VEX_L_W, /* 8936 */ + IC_VEX_L_W, /* 8937 */ + IC_VEX_L_W_XS, /* 8938 */ + IC_VEX_L_W_XS, /* 8939 */ + IC_VEX_L_W_XD, /* 8940 */ + IC_VEX_L_W_XD, /* 8941 */ + IC_VEX_L_W_XD, /* 8942 */ + IC_VEX_L_W_XD, /* 8943 */ + IC_VEX_L_OPSIZE, /* 8944 */ + IC_VEX_L_OPSIZE, /* 8945 */ + IC_VEX_L_OPSIZE, /* 8946 */ + IC_VEX_L_OPSIZE, /* 8947 */ + IC_VEX_L_OPSIZE, /* 8948 */ + IC_VEX_L_OPSIZE, /* 8949 */ + IC_VEX_L_OPSIZE, /* 8950 */ + IC_VEX_L_OPSIZE, /* 8951 */ + IC_VEX_L_W_OPSIZE, /* 8952 */ + IC_VEX_L_W_OPSIZE, /* 8953 */ + IC_VEX_L_W_OPSIZE, /* 8954 */ + IC_VEX_L_W_OPSIZE, /* 8955 */ + IC_VEX_L_W_OPSIZE, /* 8956 */ + IC_VEX_L_W_OPSIZE, /* 8957 */ + IC_VEX_L_W_OPSIZE, /* 8958 */ + IC_VEX_L_W_OPSIZE, /* 8959 */ + IC_EVEX_L_B, /* 8960 */ + IC_EVEX_L_B, /* 8961 */ + IC_EVEX_L_XS_B, /* 8962 */ + IC_EVEX_L_XS_B, /* 8963 */ + IC_EVEX_L_XD_B, /* 8964 */ + IC_EVEX_L_XD_B, /* 8965 */ + IC_EVEX_L_XD_B, /* 8966 */ + IC_EVEX_L_XD_B, /* 8967 */ + IC_EVEX_L_W_B, /* 8968 */ + IC_EVEX_L_W_B, /* 8969 */ + IC_EVEX_L_W_XS_B, /* 8970 */ + IC_EVEX_L_W_XS_B, /* 8971 */ + IC_EVEX_L_W_XD_B, /* 8972 */ + IC_EVEX_L_W_XD_B, /* 8973 */ + IC_EVEX_L_W_XD_B, /* 8974 */ + IC_EVEX_L_W_XD_B, /* 8975 */ + IC_EVEX_L_OPSIZE_B, /* 8976 */ + IC_EVEX_L_OPSIZE_B, /* 8977 */ + IC_EVEX_L_OPSIZE_B, /* 8978 */ + IC_EVEX_L_OPSIZE_B, /* 8979 */ + IC_EVEX_L_OPSIZE_B, /* 8980 */ + IC_EVEX_L_OPSIZE_B, /* 8981 */ + IC_EVEX_L_OPSIZE_B, /* 8982 */ + IC_EVEX_L_OPSIZE_B, /* 8983 */ + IC_EVEX_L_W_OPSIZE_B, /* 8984 */ + IC_EVEX_L_W_OPSIZE_B, /* 8985 */ + IC_EVEX_L_W_OPSIZE_B, /* 8986 */ + IC_EVEX_L_W_OPSIZE_B, /* 8987 */ + IC_EVEX_L_W_OPSIZE_B, /* 8988 */ + IC_EVEX_L_W_OPSIZE_B, /* 8989 */ + IC_EVEX_L_W_OPSIZE_B, /* 8990 */ + IC_EVEX_L_W_OPSIZE_B, /* 8991 */ + IC_EVEX_L_B, /* 8992 */ + IC_EVEX_L_B, /* 8993 */ + IC_EVEX_L_XS_B, /* 8994 */ + IC_EVEX_L_XS_B, /* 8995 */ + IC_EVEX_L_XD_B, /* 8996 */ + IC_EVEX_L_XD_B, /* 8997 */ + IC_EVEX_L_XD_B, /* 8998 */ + IC_EVEX_L_XD_B, /* 8999 */ + IC_EVEX_L_W_B, /* 9000 */ + IC_EVEX_L_W_B, /* 9001 */ + IC_EVEX_L_W_XS_B, /* 9002 */ + IC_EVEX_L_W_XS_B, /* 9003 */ + IC_EVEX_L_W_XD_B, /* 9004 */ + IC_EVEX_L_W_XD_B, /* 9005 */ + IC_EVEX_L_W_XD_B, /* 9006 */ + IC_EVEX_L_W_XD_B, /* 9007 */ + IC_EVEX_L_OPSIZE_B, /* 9008 */ + IC_EVEX_L_OPSIZE_B, /* 9009 */ + IC_EVEX_L_OPSIZE_B, /* 9010 */ + IC_EVEX_L_OPSIZE_B, /* 9011 */ + IC_EVEX_L_OPSIZE_B, /* 9012 */ + IC_EVEX_L_OPSIZE_B, /* 9013 */ + IC_EVEX_L_OPSIZE_B, /* 9014 */ + IC_EVEX_L_OPSIZE_B, /* 9015 */ + IC_EVEX_L_W_OPSIZE_B, /* 9016 */ + IC_EVEX_L_W_OPSIZE_B, /* 9017 */ + IC_EVEX_L_W_OPSIZE_B, /* 9018 */ + IC_EVEX_L_W_OPSIZE_B, /* 9019 */ + IC_EVEX_L_W_OPSIZE_B, /* 9020 */ + IC_EVEX_L_W_OPSIZE_B, /* 9021 */ + IC_EVEX_L_W_OPSIZE_B, /* 9022 */ + IC_EVEX_L_W_OPSIZE_B, /* 9023 */ + IC_EVEX_L_B, /* 9024 */ + IC_EVEX_L_B, /* 9025 */ + IC_EVEX_L_XS_B, /* 9026 */ + IC_EVEX_L_XS_B, /* 9027 */ + IC_EVEX_L_XD_B, /* 9028 */ + IC_EVEX_L_XD_B, /* 9029 */ + IC_EVEX_L_XD_B, /* 9030 */ + IC_EVEX_L_XD_B, /* 9031 */ + IC_EVEX_L_W_B, /* 9032 */ + IC_EVEX_L_W_B, /* 9033 */ + IC_EVEX_L_W_XS_B, /* 9034 */ + IC_EVEX_L_W_XS_B, /* 9035 */ + IC_EVEX_L_W_XD_B, /* 9036 */ + IC_EVEX_L_W_XD_B, /* 9037 */ + IC_EVEX_L_W_XD_B, /* 9038 */ + IC_EVEX_L_W_XD_B, /* 9039 */ + IC_EVEX_L_OPSIZE_B, /* 9040 */ + IC_EVEX_L_OPSIZE_B, /* 9041 */ + IC_EVEX_L_OPSIZE_B, /* 9042 */ + IC_EVEX_L_OPSIZE_B, /* 9043 */ + IC_EVEX_L_OPSIZE_B, /* 9044 */ + IC_EVEX_L_OPSIZE_B, /* 9045 */ + IC_EVEX_L_OPSIZE_B, /* 9046 */ + IC_EVEX_L_OPSIZE_B, /* 9047 */ + IC_EVEX_L_W_OPSIZE_B, /* 9048 */ + IC_EVEX_L_W_OPSIZE_B, /* 9049 */ + IC_EVEX_L_W_OPSIZE_B, /* 9050 */ + IC_EVEX_L_W_OPSIZE_B, /* 9051 */ + IC_EVEX_L_W_OPSIZE_B, /* 9052 */ + IC_EVEX_L_W_OPSIZE_B, /* 9053 */ + IC_EVEX_L_W_OPSIZE_B, /* 9054 */ + IC_EVEX_L_W_OPSIZE_B, /* 9055 */ + IC_EVEX_L_B, /* 9056 */ + IC_EVEX_L_B, /* 9057 */ + IC_EVEX_L_XS_B, /* 9058 */ + IC_EVEX_L_XS_B, /* 9059 */ + IC_EVEX_L_XD_B, /* 9060 */ + IC_EVEX_L_XD_B, /* 9061 */ + IC_EVEX_L_XD_B, /* 9062 */ + IC_EVEX_L_XD_B, /* 9063 */ + IC_EVEX_L_W_B, /* 9064 */ + IC_EVEX_L_W_B, /* 9065 */ + IC_EVEX_L_W_XS_B, /* 9066 */ + IC_EVEX_L_W_XS_B, /* 9067 */ + IC_EVEX_L_W_XD_B, /* 9068 */ + IC_EVEX_L_W_XD_B, /* 9069 */ + IC_EVEX_L_W_XD_B, /* 9070 */ + IC_EVEX_L_W_XD_B, /* 9071 */ + IC_EVEX_L_OPSIZE_B, /* 9072 */ + IC_EVEX_L_OPSIZE_B, /* 9073 */ + IC_EVEX_L_OPSIZE_B, /* 9074 */ + IC_EVEX_L_OPSIZE_B, /* 9075 */ + IC_EVEX_L_OPSIZE_B, /* 9076 */ + IC_EVEX_L_OPSIZE_B, /* 9077 */ + IC_EVEX_L_OPSIZE_B, /* 9078 */ + IC_EVEX_L_OPSIZE_B, /* 9079 */ + IC_EVEX_L_W_OPSIZE_B, /* 9080 */ + IC_EVEX_L_W_OPSIZE_B, /* 9081 */ + IC_EVEX_L_W_OPSIZE_B, /* 9082 */ + IC_EVEX_L_W_OPSIZE_B, /* 9083 */ + IC_EVEX_L_W_OPSIZE_B, /* 9084 */ + IC_EVEX_L_W_OPSIZE_B, /* 9085 */ + IC_EVEX_L_W_OPSIZE_B, /* 9086 */ + IC_EVEX_L_W_OPSIZE_B, /* 9087 */ + IC_EVEX_L_B, /* 9088 */ + IC_EVEX_L_B, /* 9089 */ + IC_EVEX_L_XS_B, /* 9090 */ + IC_EVEX_L_XS_B, /* 9091 */ + IC_EVEX_L_XD_B, /* 9092 */ + IC_EVEX_L_XD_B, /* 9093 */ + IC_EVEX_L_XD_B, /* 9094 */ + IC_EVEX_L_XD_B, /* 9095 */ + IC_EVEX_L_W_B, /* 9096 */ + IC_EVEX_L_W_B, /* 9097 */ + IC_EVEX_L_W_XS_B, /* 9098 */ + IC_EVEX_L_W_XS_B, /* 9099 */ + IC_EVEX_L_W_XD_B, /* 9100 */ + IC_EVEX_L_W_XD_B, /* 9101 */ + IC_EVEX_L_W_XD_B, /* 9102 */ + IC_EVEX_L_W_XD_B, /* 9103 */ + IC_EVEX_L_OPSIZE_B, /* 9104 */ + IC_EVEX_L_OPSIZE_B, /* 9105 */ + IC_EVEX_L_OPSIZE_B, /* 9106 */ + IC_EVEX_L_OPSIZE_B, /* 9107 */ + IC_EVEX_L_OPSIZE_B, /* 9108 */ + IC_EVEX_L_OPSIZE_B, /* 9109 */ + IC_EVEX_L_OPSIZE_B, /* 9110 */ + IC_EVEX_L_OPSIZE_B, /* 9111 */ + IC_EVEX_L_W_OPSIZE_B, /* 9112 */ + IC_EVEX_L_W_OPSIZE_B, /* 9113 */ + IC_EVEX_L_W_OPSIZE_B, /* 9114 */ + IC_EVEX_L_W_OPSIZE_B, /* 9115 */ + IC_EVEX_L_W_OPSIZE_B, /* 9116 */ + IC_EVEX_L_W_OPSIZE_B, /* 9117 */ + IC_EVEX_L_W_OPSIZE_B, /* 9118 */ + IC_EVEX_L_W_OPSIZE_B, /* 9119 */ + IC_EVEX_L_B, /* 9120 */ + IC_EVEX_L_B, /* 9121 */ + IC_EVEX_L_XS_B, /* 9122 */ + IC_EVEX_L_XS_B, /* 9123 */ + IC_EVEX_L_XD_B, /* 9124 */ + IC_EVEX_L_XD_B, /* 9125 */ + IC_EVEX_L_XD_B, /* 9126 */ + IC_EVEX_L_XD_B, /* 9127 */ + IC_EVEX_L_W_B, /* 9128 */ + IC_EVEX_L_W_B, /* 9129 */ + IC_EVEX_L_W_XS_B, /* 9130 */ + IC_EVEX_L_W_XS_B, /* 9131 */ + IC_EVEX_L_W_XD_B, /* 9132 */ + IC_EVEX_L_W_XD_B, /* 9133 */ + IC_EVEX_L_W_XD_B, /* 9134 */ + IC_EVEX_L_W_XD_B, /* 9135 */ + IC_EVEX_L_OPSIZE_B, /* 9136 */ + IC_EVEX_L_OPSIZE_B, /* 9137 */ + IC_EVEX_L_OPSIZE_B, /* 9138 */ + IC_EVEX_L_OPSIZE_B, /* 9139 */ + IC_EVEX_L_OPSIZE_B, /* 9140 */ + IC_EVEX_L_OPSIZE_B, /* 9141 */ + IC_EVEX_L_OPSIZE_B, /* 9142 */ + IC_EVEX_L_OPSIZE_B, /* 9143 */ + IC_EVEX_L_W_OPSIZE_B, /* 9144 */ + IC_EVEX_L_W_OPSIZE_B, /* 9145 */ + IC_EVEX_L_W_OPSIZE_B, /* 9146 */ + IC_EVEX_L_W_OPSIZE_B, /* 9147 */ + IC_EVEX_L_W_OPSIZE_B, /* 9148 */ + IC_EVEX_L_W_OPSIZE_B, /* 9149 */ + IC_EVEX_L_W_OPSIZE_B, /* 9150 */ + IC_EVEX_L_W_OPSIZE_B, /* 9151 */ + IC_EVEX_L_B, /* 9152 */ + IC_EVEX_L_B, /* 9153 */ + IC_EVEX_L_XS_B, /* 9154 */ + IC_EVEX_L_XS_B, /* 9155 */ + IC_EVEX_L_XD_B, /* 9156 */ + IC_EVEX_L_XD_B, /* 9157 */ + IC_EVEX_L_XD_B, /* 9158 */ + IC_EVEX_L_XD_B, /* 9159 */ + IC_EVEX_L_W_B, /* 9160 */ + IC_EVEX_L_W_B, /* 9161 */ + IC_EVEX_L_W_XS_B, /* 9162 */ + IC_EVEX_L_W_XS_B, /* 9163 */ + IC_EVEX_L_W_XD_B, /* 9164 */ + IC_EVEX_L_W_XD_B, /* 9165 */ + IC_EVEX_L_W_XD_B, /* 9166 */ + IC_EVEX_L_W_XD_B, /* 9167 */ + IC_EVEX_L_OPSIZE_B, /* 9168 */ + IC_EVEX_L_OPSIZE_B, /* 9169 */ + IC_EVEX_L_OPSIZE_B, /* 9170 */ + IC_EVEX_L_OPSIZE_B, /* 9171 */ + IC_EVEX_L_OPSIZE_B, /* 9172 */ + IC_EVEX_L_OPSIZE_B, /* 9173 */ + IC_EVEX_L_OPSIZE_B, /* 9174 */ + IC_EVEX_L_OPSIZE_B, /* 9175 */ + IC_EVEX_L_W_OPSIZE_B, /* 9176 */ + IC_EVEX_L_W_OPSIZE_B, /* 9177 */ + IC_EVEX_L_W_OPSIZE_B, /* 9178 */ + IC_EVEX_L_W_OPSIZE_B, /* 9179 */ + IC_EVEX_L_W_OPSIZE_B, /* 9180 */ + IC_EVEX_L_W_OPSIZE_B, /* 9181 */ + IC_EVEX_L_W_OPSIZE_B, /* 9182 */ + IC_EVEX_L_W_OPSIZE_B, /* 9183 */ + IC_EVEX_L_B, /* 9184 */ + IC_EVEX_L_B, /* 9185 */ + IC_EVEX_L_XS_B, /* 9186 */ + IC_EVEX_L_XS_B, /* 9187 */ + IC_EVEX_L_XD_B, /* 9188 */ + IC_EVEX_L_XD_B, /* 9189 */ + IC_EVEX_L_XD_B, /* 9190 */ + IC_EVEX_L_XD_B, /* 9191 */ + IC_EVEX_L_W_B, /* 9192 */ + IC_EVEX_L_W_B, /* 9193 */ + IC_EVEX_L_W_XS_B, /* 9194 */ + IC_EVEX_L_W_XS_B, /* 9195 */ + IC_EVEX_L_W_XD_B, /* 9196 */ + IC_EVEX_L_W_XD_B, /* 9197 */ + IC_EVEX_L_W_XD_B, /* 9198 */ + IC_EVEX_L_W_XD_B, /* 9199 */ + IC_EVEX_L_OPSIZE_B, /* 9200 */ + IC_EVEX_L_OPSIZE_B, /* 9201 */ + IC_EVEX_L_OPSIZE_B, /* 9202 */ + IC_EVEX_L_OPSIZE_B, /* 9203 */ + IC_EVEX_L_OPSIZE_B, /* 9204 */ + IC_EVEX_L_OPSIZE_B, /* 9205 */ + IC_EVEX_L_OPSIZE_B, /* 9206 */ + IC_EVEX_L_OPSIZE_B, /* 9207 */ + IC_EVEX_L_W_OPSIZE_B, /* 9208 */ + IC_EVEX_L_W_OPSIZE_B, /* 9209 */ + IC_EVEX_L_W_OPSIZE_B, /* 9210 */ + IC_EVEX_L_W_OPSIZE_B, /* 9211 */ + IC_EVEX_L_W_OPSIZE_B, /* 9212 */ + IC_EVEX_L_W_OPSIZE_B, /* 9213 */ + IC_EVEX_L_W_OPSIZE_B, /* 9214 */ + IC_EVEX_L_W_OPSIZE_B, /* 9215 */ + IC, /* 9216 */ + IC_64BIT, /* 9217 */ + IC_XS, /* 9218 */ + IC_64BIT_XS, /* 9219 */ + IC_XD, /* 9220 */ + IC_64BIT_XD, /* 9221 */ + IC_XS, /* 9222 */ + IC_64BIT_XS, /* 9223 */ + IC, /* 9224 */ + IC_64BIT_REXW, /* 9225 */ + IC_XS, /* 9226 */ + IC_64BIT_REXW_XS, /* 9227 */ + IC_XD, /* 9228 */ + IC_64BIT_REXW_XD, /* 9229 */ + IC_XS, /* 9230 */ + IC_64BIT_REXW_XS, /* 9231 */ + IC_OPSIZE, /* 9232 */ + IC_64BIT_OPSIZE, /* 9233 */ + IC_XS_OPSIZE, /* 9234 */ + IC_64BIT_XS_OPSIZE, /* 9235 */ + IC_XD_OPSIZE, /* 9236 */ + IC_64BIT_XD_OPSIZE, /* 9237 */ + IC_XS_OPSIZE, /* 9238 */ + IC_64BIT_XD_OPSIZE, /* 9239 */ + IC_OPSIZE, /* 9240 */ + IC_64BIT_REXW_OPSIZE, /* 9241 */ + IC_XS_OPSIZE, /* 9242 */ + IC_64BIT_REXW_XS, /* 9243 */ + IC_XD_OPSIZE, /* 9244 */ + IC_64BIT_REXW_XD, /* 9245 */ + IC_XS_OPSIZE, /* 9246 */ + IC_64BIT_REXW_XS, /* 9247 */ + IC_ADSIZE, /* 9248 */ + IC_64BIT_ADSIZE, /* 9249 */ + IC_XS_ADSIZE, /* 9250 */ + IC_64BIT_XS_ADSIZE, /* 9251 */ + IC_XD_ADSIZE, /* 9252 */ + IC_64BIT_XD_ADSIZE, /* 9253 */ + IC_XS_ADSIZE, /* 9254 */ + IC_64BIT_XD_ADSIZE, /* 9255 */ + IC_ADSIZE, /* 9256 */ + IC_64BIT_REXW_ADSIZE, /* 9257 */ + IC_XS_ADSIZE, /* 9258 */ + IC_64BIT_REXW_XS, /* 9259 */ + IC_XD_ADSIZE, /* 9260 */ + IC_64BIT_REXW_XD, /* 9261 */ + IC_XS_ADSIZE, /* 9262 */ + IC_64BIT_REXW_XS, /* 9263 */ + IC_OPSIZE_ADSIZE, /* 9264 */ + IC_64BIT_OPSIZE_ADSIZE, /* 9265 */ + IC_XS_OPSIZE, /* 9266 */ + IC_64BIT_XS_OPSIZE, /* 9267 */ + IC_XD_OPSIZE, /* 9268 */ + IC_64BIT_XD_OPSIZE, /* 9269 */ + IC_XS_OPSIZE, /* 9270 */ + IC_64BIT_XD_OPSIZE, /* 9271 */ + IC_OPSIZE_ADSIZE, /* 9272 */ + IC_64BIT_REXW_OPSIZE, /* 9273 */ + IC_XS_OPSIZE, /* 9274 */ + IC_64BIT_REXW_XS, /* 9275 */ + IC_XD_OPSIZE, /* 9276 */ + IC_64BIT_REXW_XD, /* 9277 */ + IC_XS_OPSIZE, /* 9278 */ + IC_64BIT_REXW_XS, /* 9279 */ + IC_VEX, /* 9280 */ + IC_VEX, /* 9281 */ + IC_VEX_XS, /* 9282 */ + IC_VEX_XS, /* 9283 */ + IC_VEX_XD, /* 9284 */ + IC_VEX_XD, /* 9285 */ + IC_VEX_XD, /* 9286 */ + IC_VEX_XD, /* 9287 */ + IC_VEX_W, /* 9288 */ + IC_VEX_W, /* 9289 */ + IC_VEX_W_XS, /* 9290 */ + IC_VEX_W_XS, /* 9291 */ + IC_VEX_W_XD, /* 9292 */ + IC_VEX_W_XD, /* 9293 */ + IC_VEX_W_XD, /* 9294 */ + IC_VEX_W_XD, /* 9295 */ + IC_VEX_OPSIZE, /* 9296 */ + IC_VEX_OPSIZE, /* 9297 */ + IC_VEX_OPSIZE, /* 9298 */ + IC_VEX_OPSIZE, /* 9299 */ + IC_VEX_OPSIZE, /* 9300 */ + IC_VEX_OPSIZE, /* 9301 */ + IC_VEX_OPSIZE, /* 9302 */ + IC_VEX_OPSIZE, /* 9303 */ + IC_VEX_W_OPSIZE, /* 9304 */ + IC_VEX_W_OPSIZE, /* 9305 */ + IC_VEX_W_OPSIZE, /* 9306 */ + IC_VEX_W_OPSIZE, /* 9307 */ + IC_VEX_W_OPSIZE, /* 9308 */ + IC_VEX_W_OPSIZE, /* 9309 */ + IC_VEX_W_OPSIZE, /* 9310 */ + IC_VEX_W_OPSIZE, /* 9311 */ + IC_VEX, /* 9312 */ + IC_VEX, /* 9313 */ + IC_VEX_XS, /* 9314 */ + IC_VEX_XS, /* 9315 */ + IC_VEX_XD, /* 9316 */ + IC_VEX_XD, /* 9317 */ + IC_VEX_XD, /* 9318 */ + IC_VEX_XD, /* 9319 */ + IC_VEX_W, /* 9320 */ + IC_VEX_W, /* 9321 */ + IC_VEX_W_XS, /* 9322 */ + IC_VEX_W_XS, /* 9323 */ + IC_VEX_W_XD, /* 9324 */ + IC_VEX_W_XD, /* 9325 */ + IC_VEX_W_XD, /* 9326 */ + IC_VEX_W_XD, /* 9327 */ + IC_VEX_OPSIZE, /* 9328 */ + IC_VEX_OPSIZE, /* 9329 */ + IC_VEX_OPSIZE, /* 9330 */ + IC_VEX_OPSIZE, /* 9331 */ + IC_VEX_OPSIZE, /* 9332 */ + IC_VEX_OPSIZE, /* 9333 */ + IC_VEX_OPSIZE, /* 9334 */ + IC_VEX_OPSIZE, /* 9335 */ + IC_VEX_W_OPSIZE, /* 9336 */ + IC_VEX_W_OPSIZE, /* 9337 */ + IC_VEX_W_OPSIZE, /* 9338 */ + IC_VEX_W_OPSIZE, /* 9339 */ + IC_VEX_W_OPSIZE, /* 9340 */ + IC_VEX_W_OPSIZE, /* 9341 */ + IC_VEX_W_OPSIZE, /* 9342 */ + IC_VEX_W_OPSIZE, /* 9343 */ + IC_VEX_L, /* 9344 */ + IC_VEX_L, /* 9345 */ + IC_VEX_L_XS, /* 9346 */ + IC_VEX_L_XS, /* 9347 */ + IC_VEX_L_XD, /* 9348 */ + IC_VEX_L_XD, /* 9349 */ + IC_VEX_L_XD, /* 9350 */ + IC_VEX_L_XD, /* 9351 */ + IC_VEX_L_W, /* 9352 */ + IC_VEX_L_W, /* 9353 */ + IC_VEX_L_W_XS, /* 9354 */ + IC_VEX_L_W_XS, /* 9355 */ + IC_VEX_L_W_XD, /* 9356 */ + IC_VEX_L_W_XD, /* 9357 */ + IC_VEX_L_W_XD, /* 9358 */ + IC_VEX_L_W_XD, /* 9359 */ + IC_VEX_L_OPSIZE, /* 9360 */ + IC_VEX_L_OPSIZE, /* 9361 */ + IC_VEX_L_OPSIZE, /* 9362 */ + IC_VEX_L_OPSIZE, /* 9363 */ + IC_VEX_L_OPSIZE, /* 9364 */ + IC_VEX_L_OPSIZE, /* 9365 */ + IC_VEX_L_OPSIZE, /* 9366 */ + IC_VEX_L_OPSIZE, /* 9367 */ + IC_VEX_L_W_OPSIZE, /* 9368 */ + IC_VEX_L_W_OPSIZE, /* 9369 */ + IC_VEX_L_W_OPSIZE, /* 9370 */ + IC_VEX_L_W_OPSIZE, /* 9371 */ + IC_VEX_L_W_OPSIZE, /* 9372 */ + IC_VEX_L_W_OPSIZE, /* 9373 */ + IC_VEX_L_W_OPSIZE, /* 9374 */ + IC_VEX_L_W_OPSIZE, /* 9375 */ + IC_VEX_L, /* 9376 */ + IC_VEX_L, /* 9377 */ + IC_VEX_L_XS, /* 9378 */ + IC_VEX_L_XS, /* 9379 */ + IC_VEX_L_XD, /* 9380 */ + IC_VEX_L_XD, /* 9381 */ + IC_VEX_L_XD, /* 9382 */ + IC_VEX_L_XD, /* 9383 */ + IC_VEX_L_W, /* 9384 */ + IC_VEX_L_W, /* 9385 */ + IC_VEX_L_W_XS, /* 9386 */ + IC_VEX_L_W_XS, /* 9387 */ + IC_VEX_L_W_XD, /* 9388 */ + IC_VEX_L_W_XD, /* 9389 */ + IC_VEX_L_W_XD, /* 9390 */ + IC_VEX_L_W_XD, /* 9391 */ + IC_VEX_L_OPSIZE, /* 9392 */ + IC_VEX_L_OPSIZE, /* 9393 */ + IC_VEX_L_OPSIZE, /* 9394 */ + IC_VEX_L_OPSIZE, /* 9395 */ + IC_VEX_L_OPSIZE, /* 9396 */ + IC_VEX_L_OPSIZE, /* 9397 */ + IC_VEX_L_OPSIZE, /* 9398 */ + IC_VEX_L_OPSIZE, /* 9399 */ + IC_VEX_L_W_OPSIZE, /* 9400 */ + IC_VEX_L_W_OPSIZE, /* 9401 */ + IC_VEX_L_W_OPSIZE, /* 9402 */ + IC_VEX_L_W_OPSIZE, /* 9403 */ + IC_VEX_L_W_OPSIZE, /* 9404 */ + IC_VEX_L_W_OPSIZE, /* 9405 */ + IC_VEX_L_W_OPSIZE, /* 9406 */ + IC_VEX_L_W_OPSIZE, /* 9407 */ + IC_VEX_L, /* 9408 */ + IC_VEX_L, /* 9409 */ + IC_VEX_L_XS, /* 9410 */ + IC_VEX_L_XS, /* 9411 */ + IC_VEX_L_XD, /* 9412 */ + IC_VEX_L_XD, /* 9413 */ + IC_VEX_L_XD, /* 9414 */ + IC_VEX_L_XD, /* 9415 */ + IC_VEX_L_W, /* 9416 */ + IC_VEX_L_W, /* 9417 */ + IC_VEX_L_W_XS, /* 9418 */ + IC_VEX_L_W_XS, /* 9419 */ + IC_VEX_L_W_XD, /* 9420 */ + IC_VEX_L_W_XD, /* 9421 */ + IC_VEX_L_W_XD, /* 9422 */ + IC_VEX_L_W_XD, /* 9423 */ + IC_VEX_L_OPSIZE, /* 9424 */ + IC_VEX_L_OPSIZE, /* 9425 */ + IC_VEX_L_OPSIZE, /* 9426 */ + IC_VEX_L_OPSIZE, /* 9427 */ + IC_VEX_L_OPSIZE, /* 9428 */ + IC_VEX_L_OPSIZE, /* 9429 */ + IC_VEX_L_OPSIZE, /* 9430 */ + IC_VEX_L_OPSIZE, /* 9431 */ + IC_VEX_L_W_OPSIZE, /* 9432 */ + IC_VEX_L_W_OPSIZE, /* 9433 */ + IC_VEX_L_W_OPSIZE, /* 9434 */ + IC_VEX_L_W_OPSIZE, /* 9435 */ + IC_VEX_L_W_OPSIZE, /* 9436 */ + IC_VEX_L_W_OPSIZE, /* 9437 */ + IC_VEX_L_W_OPSIZE, /* 9438 */ + IC_VEX_L_W_OPSIZE, /* 9439 */ + IC_VEX_L, /* 9440 */ + IC_VEX_L, /* 9441 */ + IC_VEX_L_XS, /* 9442 */ + IC_VEX_L_XS, /* 9443 */ + IC_VEX_L_XD, /* 9444 */ + IC_VEX_L_XD, /* 9445 */ + IC_VEX_L_XD, /* 9446 */ + IC_VEX_L_XD, /* 9447 */ + IC_VEX_L_W, /* 9448 */ + IC_VEX_L_W, /* 9449 */ + IC_VEX_L_W_XS, /* 9450 */ + IC_VEX_L_W_XS, /* 9451 */ + IC_VEX_L_W_XD, /* 9452 */ + IC_VEX_L_W_XD, /* 9453 */ + IC_VEX_L_W_XD, /* 9454 */ + IC_VEX_L_W_XD, /* 9455 */ + IC_VEX_L_OPSIZE, /* 9456 */ + IC_VEX_L_OPSIZE, /* 9457 */ + IC_VEX_L_OPSIZE, /* 9458 */ + IC_VEX_L_OPSIZE, /* 9459 */ + IC_VEX_L_OPSIZE, /* 9460 */ + IC_VEX_L_OPSIZE, /* 9461 */ + IC_VEX_L_OPSIZE, /* 9462 */ + IC_VEX_L_OPSIZE, /* 9463 */ + IC_VEX_L_W_OPSIZE, /* 9464 */ + IC_VEX_L_W_OPSIZE, /* 9465 */ + IC_VEX_L_W_OPSIZE, /* 9466 */ + IC_VEX_L_W_OPSIZE, /* 9467 */ + IC_VEX_L_W_OPSIZE, /* 9468 */ + IC_VEX_L_W_OPSIZE, /* 9469 */ + IC_VEX_L_W_OPSIZE, /* 9470 */ + IC_VEX_L_W_OPSIZE, /* 9471 */ + IC_EVEX_L2_B, /* 9472 */ + IC_EVEX_L2_B, /* 9473 */ + IC_EVEX_L2_XS_B, /* 9474 */ + IC_EVEX_L2_XS_B, /* 9475 */ + IC_EVEX_L2_XD_B, /* 9476 */ + IC_EVEX_L2_XD_B, /* 9477 */ + IC_EVEX_L2_XD_B, /* 9478 */ + IC_EVEX_L2_XD_B, /* 9479 */ + IC_EVEX_L2_W_B, /* 9480 */ + IC_EVEX_L2_W_B, /* 9481 */ + IC_EVEX_L2_W_XS_B, /* 9482 */ + IC_EVEX_L2_W_XS_B, /* 9483 */ + IC_EVEX_L2_W_XD_B, /* 9484 */ + IC_EVEX_L2_W_XD_B, /* 9485 */ + IC_EVEX_L2_W_XD_B, /* 9486 */ + IC_EVEX_L2_W_XD_B, /* 9487 */ + IC_EVEX_L2_OPSIZE_B, /* 9488 */ + IC_EVEX_L2_OPSIZE_B, /* 9489 */ + IC_EVEX_L2_OPSIZE_B, /* 9490 */ + IC_EVEX_L2_OPSIZE_B, /* 9491 */ + IC_EVEX_L2_OPSIZE_B, /* 9492 */ + IC_EVEX_L2_OPSIZE_B, /* 9493 */ + IC_EVEX_L2_OPSIZE_B, /* 9494 */ + IC_EVEX_L2_OPSIZE_B, /* 9495 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9496 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9497 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9498 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9499 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9500 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9501 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9502 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9503 */ + IC_EVEX_L2_B, /* 9504 */ + IC_EVEX_L2_B, /* 9505 */ + IC_EVEX_L2_XS_B, /* 9506 */ + IC_EVEX_L2_XS_B, /* 9507 */ + IC_EVEX_L2_XD_B, /* 9508 */ + IC_EVEX_L2_XD_B, /* 9509 */ + IC_EVEX_L2_XD_B, /* 9510 */ + IC_EVEX_L2_XD_B, /* 9511 */ + IC_EVEX_L2_W_B, /* 9512 */ + IC_EVEX_L2_W_B, /* 9513 */ + IC_EVEX_L2_W_XS_B, /* 9514 */ + IC_EVEX_L2_W_XS_B, /* 9515 */ + IC_EVEX_L2_W_XD_B, /* 9516 */ + IC_EVEX_L2_W_XD_B, /* 9517 */ + IC_EVEX_L2_W_XD_B, /* 9518 */ + IC_EVEX_L2_W_XD_B, /* 9519 */ + IC_EVEX_L2_OPSIZE_B, /* 9520 */ + IC_EVEX_L2_OPSIZE_B, /* 9521 */ + IC_EVEX_L2_OPSIZE_B, /* 9522 */ + IC_EVEX_L2_OPSIZE_B, /* 9523 */ + IC_EVEX_L2_OPSIZE_B, /* 9524 */ + IC_EVEX_L2_OPSIZE_B, /* 9525 */ + IC_EVEX_L2_OPSIZE_B, /* 9526 */ + IC_EVEX_L2_OPSIZE_B, /* 9527 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9528 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9529 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9530 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9531 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9532 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9533 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9534 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9535 */ + IC_EVEX_L2_B, /* 9536 */ + IC_EVEX_L2_B, /* 9537 */ + IC_EVEX_L2_XS_B, /* 9538 */ + IC_EVEX_L2_XS_B, /* 9539 */ + IC_EVEX_L2_XD_B, /* 9540 */ + IC_EVEX_L2_XD_B, /* 9541 */ + IC_EVEX_L2_XD_B, /* 9542 */ + IC_EVEX_L2_XD_B, /* 9543 */ + IC_EVEX_L2_W_B, /* 9544 */ + IC_EVEX_L2_W_B, /* 9545 */ + IC_EVEX_L2_W_XS_B, /* 9546 */ + IC_EVEX_L2_W_XS_B, /* 9547 */ + IC_EVEX_L2_W_XD_B, /* 9548 */ + IC_EVEX_L2_W_XD_B, /* 9549 */ + IC_EVEX_L2_W_XD_B, /* 9550 */ + IC_EVEX_L2_W_XD_B, /* 9551 */ + IC_EVEX_L2_OPSIZE_B, /* 9552 */ + IC_EVEX_L2_OPSIZE_B, /* 9553 */ + IC_EVEX_L2_OPSIZE_B, /* 9554 */ + IC_EVEX_L2_OPSIZE_B, /* 9555 */ + IC_EVEX_L2_OPSIZE_B, /* 9556 */ + IC_EVEX_L2_OPSIZE_B, /* 9557 */ + IC_EVEX_L2_OPSIZE_B, /* 9558 */ + IC_EVEX_L2_OPSIZE_B, /* 9559 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9560 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9561 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9562 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9563 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9564 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9565 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9566 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9567 */ + IC_EVEX_L2_B, /* 9568 */ + IC_EVEX_L2_B, /* 9569 */ + IC_EVEX_L2_XS_B, /* 9570 */ + IC_EVEX_L2_XS_B, /* 9571 */ + IC_EVEX_L2_XD_B, /* 9572 */ + IC_EVEX_L2_XD_B, /* 9573 */ + IC_EVEX_L2_XD_B, /* 9574 */ + IC_EVEX_L2_XD_B, /* 9575 */ + IC_EVEX_L2_W_B, /* 9576 */ + IC_EVEX_L2_W_B, /* 9577 */ + IC_EVEX_L2_W_XS_B, /* 9578 */ + IC_EVEX_L2_W_XS_B, /* 9579 */ + IC_EVEX_L2_W_XD_B, /* 9580 */ + IC_EVEX_L2_W_XD_B, /* 9581 */ + IC_EVEX_L2_W_XD_B, /* 9582 */ + IC_EVEX_L2_W_XD_B, /* 9583 */ + IC_EVEX_L2_OPSIZE_B, /* 9584 */ + IC_EVEX_L2_OPSIZE_B, /* 9585 */ + IC_EVEX_L2_OPSIZE_B, /* 9586 */ + IC_EVEX_L2_OPSIZE_B, /* 9587 */ + IC_EVEX_L2_OPSIZE_B, /* 9588 */ + IC_EVEX_L2_OPSIZE_B, /* 9589 */ + IC_EVEX_L2_OPSIZE_B, /* 9590 */ + IC_EVEX_L2_OPSIZE_B, /* 9591 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9592 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9593 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9594 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9595 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9596 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9597 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9598 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9599 */ + IC_EVEX_L2_B, /* 9600 */ + IC_EVEX_L2_B, /* 9601 */ + IC_EVEX_L2_XS_B, /* 9602 */ + IC_EVEX_L2_XS_B, /* 9603 */ + IC_EVEX_L2_XD_B, /* 9604 */ + IC_EVEX_L2_XD_B, /* 9605 */ + IC_EVEX_L2_XD_B, /* 9606 */ + IC_EVEX_L2_XD_B, /* 9607 */ + IC_EVEX_L2_W_B, /* 9608 */ + IC_EVEX_L2_W_B, /* 9609 */ + IC_EVEX_L2_W_XS_B, /* 9610 */ + IC_EVEX_L2_W_XS_B, /* 9611 */ + IC_EVEX_L2_W_XD_B, /* 9612 */ + IC_EVEX_L2_W_XD_B, /* 9613 */ + IC_EVEX_L2_W_XD_B, /* 9614 */ + IC_EVEX_L2_W_XD_B, /* 9615 */ + IC_EVEX_L2_OPSIZE_B, /* 9616 */ + IC_EVEX_L2_OPSIZE_B, /* 9617 */ + IC_EVEX_L2_OPSIZE_B, /* 9618 */ + IC_EVEX_L2_OPSIZE_B, /* 9619 */ + IC_EVEX_L2_OPSIZE_B, /* 9620 */ + IC_EVEX_L2_OPSIZE_B, /* 9621 */ + IC_EVEX_L2_OPSIZE_B, /* 9622 */ + IC_EVEX_L2_OPSIZE_B, /* 9623 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9624 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9625 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9626 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9627 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9628 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9629 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9630 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9631 */ + IC_EVEX_L2_B, /* 9632 */ + IC_EVEX_L2_B, /* 9633 */ + IC_EVEX_L2_XS_B, /* 9634 */ + IC_EVEX_L2_XS_B, /* 9635 */ + IC_EVEX_L2_XD_B, /* 9636 */ + IC_EVEX_L2_XD_B, /* 9637 */ + IC_EVEX_L2_XD_B, /* 9638 */ + IC_EVEX_L2_XD_B, /* 9639 */ + IC_EVEX_L2_W_B, /* 9640 */ + IC_EVEX_L2_W_B, /* 9641 */ + IC_EVEX_L2_W_XS_B, /* 9642 */ + IC_EVEX_L2_W_XS_B, /* 9643 */ + IC_EVEX_L2_W_XD_B, /* 9644 */ + IC_EVEX_L2_W_XD_B, /* 9645 */ + IC_EVEX_L2_W_XD_B, /* 9646 */ + IC_EVEX_L2_W_XD_B, /* 9647 */ + IC_EVEX_L2_OPSIZE_B, /* 9648 */ + IC_EVEX_L2_OPSIZE_B, /* 9649 */ + IC_EVEX_L2_OPSIZE_B, /* 9650 */ + IC_EVEX_L2_OPSIZE_B, /* 9651 */ + IC_EVEX_L2_OPSIZE_B, /* 9652 */ + IC_EVEX_L2_OPSIZE_B, /* 9653 */ + IC_EVEX_L2_OPSIZE_B, /* 9654 */ + IC_EVEX_L2_OPSIZE_B, /* 9655 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9656 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9657 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9658 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9659 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9660 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9661 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9662 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9663 */ + IC_EVEX_L2_B, /* 9664 */ + IC_EVEX_L2_B, /* 9665 */ + IC_EVEX_L2_XS_B, /* 9666 */ + IC_EVEX_L2_XS_B, /* 9667 */ + IC_EVEX_L2_XD_B, /* 9668 */ + IC_EVEX_L2_XD_B, /* 9669 */ + IC_EVEX_L2_XD_B, /* 9670 */ + IC_EVEX_L2_XD_B, /* 9671 */ + IC_EVEX_L2_W_B, /* 9672 */ + IC_EVEX_L2_W_B, /* 9673 */ + IC_EVEX_L2_W_XS_B, /* 9674 */ + IC_EVEX_L2_W_XS_B, /* 9675 */ + IC_EVEX_L2_W_XD_B, /* 9676 */ + IC_EVEX_L2_W_XD_B, /* 9677 */ + IC_EVEX_L2_W_XD_B, /* 9678 */ + IC_EVEX_L2_W_XD_B, /* 9679 */ + IC_EVEX_L2_OPSIZE_B, /* 9680 */ + IC_EVEX_L2_OPSIZE_B, /* 9681 */ + IC_EVEX_L2_OPSIZE_B, /* 9682 */ + IC_EVEX_L2_OPSIZE_B, /* 9683 */ + IC_EVEX_L2_OPSIZE_B, /* 9684 */ + IC_EVEX_L2_OPSIZE_B, /* 9685 */ + IC_EVEX_L2_OPSIZE_B, /* 9686 */ + IC_EVEX_L2_OPSIZE_B, /* 9687 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9688 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9689 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9690 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9691 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9692 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9693 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9694 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9695 */ + IC_EVEX_L2_B, /* 9696 */ + IC_EVEX_L2_B, /* 9697 */ + IC_EVEX_L2_XS_B, /* 9698 */ + IC_EVEX_L2_XS_B, /* 9699 */ + IC_EVEX_L2_XD_B, /* 9700 */ + IC_EVEX_L2_XD_B, /* 9701 */ + IC_EVEX_L2_XD_B, /* 9702 */ + IC_EVEX_L2_XD_B, /* 9703 */ + IC_EVEX_L2_W_B, /* 9704 */ + IC_EVEX_L2_W_B, /* 9705 */ + IC_EVEX_L2_W_XS_B, /* 9706 */ + IC_EVEX_L2_W_XS_B, /* 9707 */ + IC_EVEX_L2_W_XD_B, /* 9708 */ + IC_EVEX_L2_W_XD_B, /* 9709 */ + IC_EVEX_L2_W_XD_B, /* 9710 */ + IC_EVEX_L2_W_XD_B, /* 9711 */ + IC_EVEX_L2_OPSIZE_B, /* 9712 */ + IC_EVEX_L2_OPSIZE_B, /* 9713 */ + IC_EVEX_L2_OPSIZE_B, /* 9714 */ + IC_EVEX_L2_OPSIZE_B, /* 9715 */ + IC_EVEX_L2_OPSIZE_B, /* 9716 */ + IC_EVEX_L2_OPSIZE_B, /* 9717 */ + IC_EVEX_L2_OPSIZE_B, /* 9718 */ + IC_EVEX_L2_OPSIZE_B, /* 9719 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9720 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9721 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9722 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9723 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9724 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9725 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9726 */ + IC_EVEX_L2_W_OPSIZE_B, /* 9727 */ + IC, /* 9728 */ + IC_64BIT, /* 9729 */ + IC_XS, /* 9730 */ + IC_64BIT_XS, /* 9731 */ + IC_XD, /* 9732 */ + IC_64BIT_XD, /* 9733 */ + IC_XS, /* 9734 */ + IC_64BIT_XS, /* 9735 */ + IC, /* 9736 */ + IC_64BIT_REXW, /* 9737 */ + IC_XS, /* 9738 */ + IC_64BIT_REXW_XS, /* 9739 */ + IC_XD, /* 9740 */ + IC_64BIT_REXW_XD, /* 9741 */ + IC_XS, /* 9742 */ + IC_64BIT_REXW_XS, /* 9743 */ + IC_OPSIZE, /* 9744 */ + IC_64BIT_OPSIZE, /* 9745 */ + IC_XS_OPSIZE, /* 9746 */ + IC_64BIT_XS_OPSIZE, /* 9747 */ + IC_XD_OPSIZE, /* 9748 */ + IC_64BIT_XD_OPSIZE, /* 9749 */ + IC_XS_OPSIZE, /* 9750 */ + IC_64BIT_XD_OPSIZE, /* 9751 */ + IC_OPSIZE, /* 9752 */ + IC_64BIT_REXW_OPSIZE, /* 9753 */ + IC_XS_OPSIZE, /* 9754 */ + IC_64BIT_REXW_XS, /* 9755 */ + IC_XD_OPSIZE, /* 9756 */ + IC_64BIT_REXW_XD, /* 9757 */ + IC_XS_OPSIZE, /* 9758 */ + IC_64BIT_REXW_XS, /* 9759 */ + IC_ADSIZE, /* 9760 */ + IC_64BIT_ADSIZE, /* 9761 */ + IC_XS_ADSIZE, /* 9762 */ + IC_64BIT_XS_ADSIZE, /* 9763 */ + IC_XD_ADSIZE, /* 9764 */ + IC_64BIT_XD_ADSIZE, /* 9765 */ + IC_XS_ADSIZE, /* 9766 */ + IC_64BIT_XD_ADSIZE, /* 9767 */ + IC_ADSIZE, /* 9768 */ + IC_64BIT_REXW_ADSIZE, /* 9769 */ + IC_XS_ADSIZE, /* 9770 */ + IC_64BIT_REXW_XS, /* 9771 */ + IC_XD_ADSIZE, /* 9772 */ + IC_64BIT_REXW_XD, /* 9773 */ + IC_XS_ADSIZE, /* 9774 */ + IC_64BIT_REXW_XS, /* 9775 */ + IC_OPSIZE_ADSIZE, /* 9776 */ + IC_64BIT_OPSIZE_ADSIZE, /* 9777 */ + IC_XS_OPSIZE, /* 9778 */ + IC_64BIT_XS_OPSIZE, /* 9779 */ + IC_XD_OPSIZE, /* 9780 */ + IC_64BIT_XD_OPSIZE, /* 9781 */ + IC_XS_OPSIZE, /* 9782 */ + IC_64BIT_XD_OPSIZE, /* 9783 */ + IC_OPSIZE_ADSIZE, /* 9784 */ + IC_64BIT_REXW_OPSIZE, /* 9785 */ + IC_XS_OPSIZE, /* 9786 */ + IC_64BIT_REXW_XS, /* 9787 */ + IC_XD_OPSIZE, /* 9788 */ + IC_64BIT_REXW_XD, /* 9789 */ + IC_XS_OPSIZE, /* 9790 */ + IC_64BIT_REXW_XS, /* 9791 */ + IC_VEX, /* 9792 */ + IC_VEX, /* 9793 */ + IC_VEX_XS, /* 9794 */ + IC_VEX_XS, /* 9795 */ + IC_VEX_XD, /* 9796 */ + IC_VEX_XD, /* 9797 */ + IC_VEX_XD, /* 9798 */ + IC_VEX_XD, /* 9799 */ + IC_VEX_W, /* 9800 */ + IC_VEX_W, /* 9801 */ + IC_VEX_W_XS, /* 9802 */ + IC_VEX_W_XS, /* 9803 */ + IC_VEX_W_XD, /* 9804 */ + IC_VEX_W_XD, /* 9805 */ + IC_VEX_W_XD, /* 9806 */ + IC_VEX_W_XD, /* 9807 */ + IC_VEX_OPSIZE, /* 9808 */ + IC_VEX_OPSIZE, /* 9809 */ + IC_VEX_OPSIZE, /* 9810 */ + IC_VEX_OPSIZE, /* 9811 */ + IC_VEX_OPSIZE, /* 9812 */ + IC_VEX_OPSIZE, /* 9813 */ + IC_VEX_OPSIZE, /* 9814 */ + IC_VEX_OPSIZE, /* 9815 */ + IC_VEX_W_OPSIZE, /* 9816 */ + IC_VEX_W_OPSIZE, /* 9817 */ + IC_VEX_W_OPSIZE, /* 9818 */ + IC_VEX_W_OPSIZE, /* 9819 */ + IC_VEX_W_OPSIZE, /* 9820 */ + IC_VEX_W_OPSIZE, /* 9821 */ + IC_VEX_W_OPSIZE, /* 9822 */ + IC_VEX_W_OPSIZE, /* 9823 */ + IC_VEX, /* 9824 */ + IC_VEX, /* 9825 */ + IC_VEX_XS, /* 9826 */ + IC_VEX_XS, /* 9827 */ + IC_VEX_XD, /* 9828 */ + IC_VEX_XD, /* 9829 */ + IC_VEX_XD, /* 9830 */ + IC_VEX_XD, /* 9831 */ + IC_VEX_W, /* 9832 */ + IC_VEX_W, /* 9833 */ + IC_VEX_W_XS, /* 9834 */ + IC_VEX_W_XS, /* 9835 */ + IC_VEX_W_XD, /* 9836 */ + IC_VEX_W_XD, /* 9837 */ + IC_VEX_W_XD, /* 9838 */ + IC_VEX_W_XD, /* 9839 */ + IC_VEX_OPSIZE, /* 9840 */ + IC_VEX_OPSIZE, /* 9841 */ + IC_VEX_OPSIZE, /* 9842 */ + IC_VEX_OPSIZE, /* 9843 */ + IC_VEX_OPSIZE, /* 9844 */ + IC_VEX_OPSIZE, /* 9845 */ + IC_VEX_OPSIZE, /* 9846 */ + IC_VEX_OPSIZE, /* 9847 */ + IC_VEX_W_OPSIZE, /* 9848 */ + IC_VEX_W_OPSIZE, /* 9849 */ + IC_VEX_W_OPSIZE, /* 9850 */ + IC_VEX_W_OPSIZE, /* 9851 */ + IC_VEX_W_OPSIZE, /* 9852 */ + IC_VEX_W_OPSIZE, /* 9853 */ + IC_VEX_W_OPSIZE, /* 9854 */ + IC_VEX_W_OPSIZE, /* 9855 */ + IC_VEX_L, /* 9856 */ + IC_VEX_L, /* 9857 */ + IC_VEX_L_XS, /* 9858 */ + IC_VEX_L_XS, /* 9859 */ + IC_VEX_L_XD, /* 9860 */ + IC_VEX_L_XD, /* 9861 */ + IC_VEX_L_XD, /* 9862 */ + IC_VEX_L_XD, /* 9863 */ + IC_VEX_L_W, /* 9864 */ + IC_VEX_L_W, /* 9865 */ + IC_VEX_L_W_XS, /* 9866 */ + IC_VEX_L_W_XS, /* 9867 */ + IC_VEX_L_W_XD, /* 9868 */ + IC_VEX_L_W_XD, /* 9869 */ + IC_VEX_L_W_XD, /* 9870 */ + IC_VEX_L_W_XD, /* 9871 */ + IC_VEX_L_OPSIZE, /* 9872 */ + IC_VEX_L_OPSIZE, /* 9873 */ + IC_VEX_L_OPSIZE, /* 9874 */ + IC_VEX_L_OPSIZE, /* 9875 */ + IC_VEX_L_OPSIZE, /* 9876 */ + IC_VEX_L_OPSIZE, /* 9877 */ + IC_VEX_L_OPSIZE, /* 9878 */ + IC_VEX_L_OPSIZE, /* 9879 */ + IC_VEX_L_W_OPSIZE, /* 9880 */ + IC_VEX_L_W_OPSIZE, /* 9881 */ + IC_VEX_L_W_OPSIZE, /* 9882 */ + IC_VEX_L_W_OPSIZE, /* 9883 */ + IC_VEX_L_W_OPSIZE, /* 9884 */ + IC_VEX_L_W_OPSIZE, /* 9885 */ + IC_VEX_L_W_OPSIZE, /* 9886 */ + IC_VEX_L_W_OPSIZE, /* 9887 */ + IC_VEX_L, /* 9888 */ + IC_VEX_L, /* 9889 */ + IC_VEX_L_XS, /* 9890 */ + IC_VEX_L_XS, /* 9891 */ + IC_VEX_L_XD, /* 9892 */ + IC_VEX_L_XD, /* 9893 */ + IC_VEX_L_XD, /* 9894 */ + IC_VEX_L_XD, /* 9895 */ + IC_VEX_L_W, /* 9896 */ + IC_VEX_L_W, /* 9897 */ + IC_VEX_L_W_XS, /* 9898 */ + IC_VEX_L_W_XS, /* 9899 */ + IC_VEX_L_W_XD, /* 9900 */ + IC_VEX_L_W_XD, /* 9901 */ + IC_VEX_L_W_XD, /* 9902 */ + IC_VEX_L_W_XD, /* 9903 */ + IC_VEX_L_OPSIZE, /* 9904 */ + IC_VEX_L_OPSIZE, /* 9905 */ + IC_VEX_L_OPSIZE, /* 9906 */ + IC_VEX_L_OPSIZE, /* 9907 */ + IC_VEX_L_OPSIZE, /* 9908 */ + IC_VEX_L_OPSIZE, /* 9909 */ + IC_VEX_L_OPSIZE, /* 9910 */ + IC_VEX_L_OPSIZE, /* 9911 */ + IC_VEX_L_W_OPSIZE, /* 9912 */ + IC_VEX_L_W_OPSIZE, /* 9913 */ + IC_VEX_L_W_OPSIZE, /* 9914 */ + IC_VEX_L_W_OPSIZE, /* 9915 */ + IC_VEX_L_W_OPSIZE, /* 9916 */ + IC_VEX_L_W_OPSIZE, /* 9917 */ + IC_VEX_L_W_OPSIZE, /* 9918 */ + IC_VEX_L_W_OPSIZE, /* 9919 */ + IC_VEX_L, /* 9920 */ + IC_VEX_L, /* 9921 */ + IC_VEX_L_XS, /* 9922 */ + IC_VEX_L_XS, /* 9923 */ + IC_VEX_L_XD, /* 9924 */ + IC_VEX_L_XD, /* 9925 */ + IC_VEX_L_XD, /* 9926 */ + IC_VEX_L_XD, /* 9927 */ + IC_VEX_L_W, /* 9928 */ + IC_VEX_L_W, /* 9929 */ + IC_VEX_L_W_XS, /* 9930 */ + IC_VEX_L_W_XS, /* 9931 */ + IC_VEX_L_W_XD, /* 9932 */ + IC_VEX_L_W_XD, /* 9933 */ + IC_VEX_L_W_XD, /* 9934 */ + IC_VEX_L_W_XD, /* 9935 */ + IC_VEX_L_OPSIZE, /* 9936 */ + IC_VEX_L_OPSIZE, /* 9937 */ + IC_VEX_L_OPSIZE, /* 9938 */ + IC_VEX_L_OPSIZE, /* 9939 */ + IC_VEX_L_OPSIZE, /* 9940 */ + IC_VEX_L_OPSIZE, /* 9941 */ + IC_VEX_L_OPSIZE, /* 9942 */ + IC_VEX_L_OPSIZE, /* 9943 */ + IC_VEX_L_W_OPSIZE, /* 9944 */ + IC_VEX_L_W_OPSIZE, /* 9945 */ + IC_VEX_L_W_OPSIZE, /* 9946 */ + IC_VEX_L_W_OPSIZE, /* 9947 */ + IC_VEX_L_W_OPSIZE, /* 9948 */ + IC_VEX_L_W_OPSIZE, /* 9949 */ + IC_VEX_L_W_OPSIZE, /* 9950 */ + IC_VEX_L_W_OPSIZE, /* 9951 */ + IC_VEX_L, /* 9952 */ + IC_VEX_L, /* 9953 */ + IC_VEX_L_XS, /* 9954 */ + IC_VEX_L_XS, /* 9955 */ + IC_VEX_L_XD, /* 9956 */ + IC_VEX_L_XD, /* 9957 */ + IC_VEX_L_XD, /* 9958 */ + IC_VEX_L_XD, /* 9959 */ + IC_VEX_L_W, /* 9960 */ + IC_VEX_L_W, /* 9961 */ + IC_VEX_L_W_XS, /* 9962 */ + IC_VEX_L_W_XS, /* 9963 */ + IC_VEX_L_W_XD, /* 9964 */ + IC_VEX_L_W_XD, /* 9965 */ + IC_VEX_L_W_XD, /* 9966 */ + IC_VEX_L_W_XD, /* 9967 */ + IC_VEX_L_OPSIZE, /* 9968 */ + IC_VEX_L_OPSIZE, /* 9969 */ + IC_VEX_L_OPSIZE, /* 9970 */ + IC_VEX_L_OPSIZE, /* 9971 */ + IC_VEX_L_OPSIZE, /* 9972 */ + IC_VEX_L_OPSIZE, /* 9973 */ + IC_VEX_L_OPSIZE, /* 9974 */ + IC_VEX_L_OPSIZE, /* 9975 */ + IC_VEX_L_W_OPSIZE, /* 9976 */ + IC_VEX_L_W_OPSIZE, /* 9977 */ + IC_VEX_L_W_OPSIZE, /* 9978 */ + IC_VEX_L_W_OPSIZE, /* 9979 */ + IC_VEX_L_W_OPSIZE, /* 9980 */ + IC_VEX_L_W_OPSIZE, /* 9981 */ + IC_VEX_L_W_OPSIZE, /* 9982 */ + IC_VEX_L_W_OPSIZE, /* 9983 */ + IC_EVEX_L2_B, /* 9984 */ + IC_EVEX_L2_B, /* 9985 */ + IC_EVEX_L2_XS_B, /* 9986 */ + IC_EVEX_L2_XS_B, /* 9987 */ + IC_EVEX_L2_XD_B, /* 9988 */ + IC_EVEX_L2_XD_B, /* 9989 */ + IC_EVEX_L2_XD_B, /* 9990 */ + IC_EVEX_L2_XD_B, /* 9991 */ + IC_EVEX_L2_W_B, /* 9992 */ + IC_EVEX_L2_W_B, /* 9993 */ + IC_EVEX_L2_W_XS_B, /* 9994 */ + IC_EVEX_L2_W_XS_B, /* 9995 */ + IC_EVEX_L2_W_XD_B, /* 9996 */ + IC_EVEX_L2_W_XD_B, /* 9997 */ + IC_EVEX_L2_W_XD_B, /* 9998 */ + IC_EVEX_L2_W_XD_B, /* 9999 */ + IC_EVEX_L2_OPSIZE_B, /* 10000 */ + IC_EVEX_L2_OPSIZE_B, /* 10001 */ + IC_EVEX_L2_OPSIZE_B, /* 10002 */ + IC_EVEX_L2_OPSIZE_B, /* 10003 */ + IC_EVEX_L2_OPSIZE_B, /* 10004 */ + IC_EVEX_L2_OPSIZE_B, /* 10005 */ + IC_EVEX_L2_OPSIZE_B, /* 10006 */ + IC_EVEX_L2_OPSIZE_B, /* 10007 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10008 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10009 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10010 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10011 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10012 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10013 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10014 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10015 */ + IC_EVEX_L2_B, /* 10016 */ + IC_EVEX_L2_B, /* 10017 */ + IC_EVEX_L2_XS_B, /* 10018 */ + IC_EVEX_L2_XS_B, /* 10019 */ + IC_EVEX_L2_XD_B, /* 10020 */ + IC_EVEX_L2_XD_B, /* 10021 */ + IC_EVEX_L2_XD_B, /* 10022 */ + IC_EVEX_L2_XD_B, /* 10023 */ + IC_EVEX_L2_W_B, /* 10024 */ + IC_EVEX_L2_W_B, /* 10025 */ + IC_EVEX_L2_W_XS_B, /* 10026 */ + IC_EVEX_L2_W_XS_B, /* 10027 */ + IC_EVEX_L2_W_XD_B, /* 10028 */ + IC_EVEX_L2_W_XD_B, /* 10029 */ + IC_EVEX_L2_W_XD_B, /* 10030 */ + IC_EVEX_L2_W_XD_B, /* 10031 */ + IC_EVEX_L2_OPSIZE_B, /* 10032 */ + IC_EVEX_L2_OPSIZE_B, /* 10033 */ + IC_EVEX_L2_OPSIZE_B, /* 10034 */ + IC_EVEX_L2_OPSIZE_B, /* 10035 */ + IC_EVEX_L2_OPSIZE_B, /* 10036 */ + IC_EVEX_L2_OPSIZE_B, /* 10037 */ + IC_EVEX_L2_OPSIZE_B, /* 10038 */ + IC_EVEX_L2_OPSIZE_B, /* 10039 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10040 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10041 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10042 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10043 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10044 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10045 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10046 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10047 */ + IC_EVEX_L2_B, /* 10048 */ + IC_EVEX_L2_B, /* 10049 */ + IC_EVEX_L2_XS_B, /* 10050 */ + IC_EVEX_L2_XS_B, /* 10051 */ + IC_EVEX_L2_XD_B, /* 10052 */ + IC_EVEX_L2_XD_B, /* 10053 */ + IC_EVEX_L2_XD_B, /* 10054 */ + IC_EVEX_L2_XD_B, /* 10055 */ + IC_EVEX_L2_W_B, /* 10056 */ + IC_EVEX_L2_W_B, /* 10057 */ + IC_EVEX_L2_W_XS_B, /* 10058 */ + IC_EVEX_L2_W_XS_B, /* 10059 */ + IC_EVEX_L2_W_XD_B, /* 10060 */ + IC_EVEX_L2_W_XD_B, /* 10061 */ + IC_EVEX_L2_W_XD_B, /* 10062 */ + IC_EVEX_L2_W_XD_B, /* 10063 */ + IC_EVEX_L2_OPSIZE_B, /* 10064 */ + IC_EVEX_L2_OPSIZE_B, /* 10065 */ + IC_EVEX_L2_OPSIZE_B, /* 10066 */ + IC_EVEX_L2_OPSIZE_B, /* 10067 */ + IC_EVEX_L2_OPSIZE_B, /* 10068 */ + IC_EVEX_L2_OPSIZE_B, /* 10069 */ + IC_EVEX_L2_OPSIZE_B, /* 10070 */ + IC_EVEX_L2_OPSIZE_B, /* 10071 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10072 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10073 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10074 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10075 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10076 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10077 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10078 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10079 */ + IC_EVEX_L2_B, /* 10080 */ + IC_EVEX_L2_B, /* 10081 */ + IC_EVEX_L2_XS_B, /* 10082 */ + IC_EVEX_L2_XS_B, /* 10083 */ + IC_EVEX_L2_XD_B, /* 10084 */ + IC_EVEX_L2_XD_B, /* 10085 */ + IC_EVEX_L2_XD_B, /* 10086 */ + IC_EVEX_L2_XD_B, /* 10087 */ + IC_EVEX_L2_W_B, /* 10088 */ + IC_EVEX_L2_W_B, /* 10089 */ + IC_EVEX_L2_W_XS_B, /* 10090 */ + IC_EVEX_L2_W_XS_B, /* 10091 */ + IC_EVEX_L2_W_XD_B, /* 10092 */ + IC_EVEX_L2_W_XD_B, /* 10093 */ + IC_EVEX_L2_W_XD_B, /* 10094 */ + IC_EVEX_L2_W_XD_B, /* 10095 */ + IC_EVEX_L2_OPSIZE_B, /* 10096 */ + IC_EVEX_L2_OPSIZE_B, /* 10097 */ + IC_EVEX_L2_OPSIZE_B, /* 10098 */ + IC_EVEX_L2_OPSIZE_B, /* 10099 */ + IC_EVEX_L2_OPSIZE_B, /* 10100 */ + IC_EVEX_L2_OPSIZE_B, /* 10101 */ + IC_EVEX_L2_OPSIZE_B, /* 10102 */ + IC_EVEX_L2_OPSIZE_B, /* 10103 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10104 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10105 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10106 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10107 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10108 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10109 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10110 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10111 */ + IC_EVEX_L2_B, /* 10112 */ + IC_EVEX_L2_B, /* 10113 */ + IC_EVEX_L2_XS_B, /* 10114 */ + IC_EVEX_L2_XS_B, /* 10115 */ + IC_EVEX_L2_XD_B, /* 10116 */ + IC_EVEX_L2_XD_B, /* 10117 */ + IC_EVEX_L2_XD_B, /* 10118 */ + IC_EVEX_L2_XD_B, /* 10119 */ + IC_EVEX_L2_W_B, /* 10120 */ + IC_EVEX_L2_W_B, /* 10121 */ + IC_EVEX_L2_W_XS_B, /* 10122 */ + IC_EVEX_L2_W_XS_B, /* 10123 */ + IC_EVEX_L2_W_XD_B, /* 10124 */ + IC_EVEX_L2_W_XD_B, /* 10125 */ + IC_EVEX_L2_W_XD_B, /* 10126 */ + IC_EVEX_L2_W_XD_B, /* 10127 */ + IC_EVEX_L2_OPSIZE_B, /* 10128 */ + IC_EVEX_L2_OPSIZE_B, /* 10129 */ + IC_EVEX_L2_OPSIZE_B, /* 10130 */ + IC_EVEX_L2_OPSIZE_B, /* 10131 */ + IC_EVEX_L2_OPSIZE_B, /* 10132 */ + IC_EVEX_L2_OPSIZE_B, /* 10133 */ + IC_EVEX_L2_OPSIZE_B, /* 10134 */ + IC_EVEX_L2_OPSIZE_B, /* 10135 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10136 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10137 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10138 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10139 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10140 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10141 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10142 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10143 */ + IC_EVEX_L2_B, /* 10144 */ + IC_EVEX_L2_B, /* 10145 */ + IC_EVEX_L2_XS_B, /* 10146 */ + IC_EVEX_L2_XS_B, /* 10147 */ + IC_EVEX_L2_XD_B, /* 10148 */ + IC_EVEX_L2_XD_B, /* 10149 */ + IC_EVEX_L2_XD_B, /* 10150 */ + IC_EVEX_L2_XD_B, /* 10151 */ + IC_EVEX_L2_W_B, /* 10152 */ + IC_EVEX_L2_W_B, /* 10153 */ + IC_EVEX_L2_W_XS_B, /* 10154 */ + IC_EVEX_L2_W_XS_B, /* 10155 */ + IC_EVEX_L2_W_XD_B, /* 10156 */ + IC_EVEX_L2_W_XD_B, /* 10157 */ + IC_EVEX_L2_W_XD_B, /* 10158 */ + IC_EVEX_L2_W_XD_B, /* 10159 */ + IC_EVEX_L2_OPSIZE_B, /* 10160 */ + IC_EVEX_L2_OPSIZE_B, /* 10161 */ + IC_EVEX_L2_OPSIZE_B, /* 10162 */ + IC_EVEX_L2_OPSIZE_B, /* 10163 */ + IC_EVEX_L2_OPSIZE_B, /* 10164 */ + IC_EVEX_L2_OPSIZE_B, /* 10165 */ + IC_EVEX_L2_OPSIZE_B, /* 10166 */ + IC_EVEX_L2_OPSIZE_B, /* 10167 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10168 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10169 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10170 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10171 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10172 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10173 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10174 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10175 */ + IC_EVEX_L2_B, /* 10176 */ + IC_EVEX_L2_B, /* 10177 */ + IC_EVEX_L2_XS_B, /* 10178 */ + IC_EVEX_L2_XS_B, /* 10179 */ + IC_EVEX_L2_XD_B, /* 10180 */ + IC_EVEX_L2_XD_B, /* 10181 */ + IC_EVEX_L2_XD_B, /* 10182 */ + IC_EVEX_L2_XD_B, /* 10183 */ + IC_EVEX_L2_W_B, /* 10184 */ + IC_EVEX_L2_W_B, /* 10185 */ + IC_EVEX_L2_W_XS_B, /* 10186 */ + IC_EVEX_L2_W_XS_B, /* 10187 */ + IC_EVEX_L2_W_XD_B, /* 10188 */ + IC_EVEX_L2_W_XD_B, /* 10189 */ + IC_EVEX_L2_W_XD_B, /* 10190 */ + IC_EVEX_L2_W_XD_B, /* 10191 */ + IC_EVEX_L2_OPSIZE_B, /* 10192 */ + IC_EVEX_L2_OPSIZE_B, /* 10193 */ + IC_EVEX_L2_OPSIZE_B, /* 10194 */ + IC_EVEX_L2_OPSIZE_B, /* 10195 */ + IC_EVEX_L2_OPSIZE_B, /* 10196 */ + IC_EVEX_L2_OPSIZE_B, /* 10197 */ + IC_EVEX_L2_OPSIZE_B, /* 10198 */ + IC_EVEX_L2_OPSIZE_B, /* 10199 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10200 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10201 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10202 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10203 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10204 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10205 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10206 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10207 */ + IC_EVEX_L2_B, /* 10208 */ + IC_EVEX_L2_B, /* 10209 */ + IC_EVEX_L2_XS_B, /* 10210 */ + IC_EVEX_L2_XS_B, /* 10211 */ + IC_EVEX_L2_XD_B, /* 10212 */ + IC_EVEX_L2_XD_B, /* 10213 */ + IC_EVEX_L2_XD_B, /* 10214 */ + IC_EVEX_L2_XD_B, /* 10215 */ + IC_EVEX_L2_W_B, /* 10216 */ + IC_EVEX_L2_W_B, /* 10217 */ + IC_EVEX_L2_W_XS_B, /* 10218 */ + IC_EVEX_L2_W_XS_B, /* 10219 */ + IC_EVEX_L2_W_XD_B, /* 10220 */ + IC_EVEX_L2_W_XD_B, /* 10221 */ + IC_EVEX_L2_W_XD_B, /* 10222 */ + IC_EVEX_L2_W_XD_B, /* 10223 */ + IC_EVEX_L2_OPSIZE_B, /* 10224 */ + IC_EVEX_L2_OPSIZE_B, /* 10225 */ + IC_EVEX_L2_OPSIZE_B, /* 10226 */ + IC_EVEX_L2_OPSIZE_B, /* 10227 */ + IC_EVEX_L2_OPSIZE_B, /* 10228 */ + IC_EVEX_L2_OPSIZE_B, /* 10229 */ + IC_EVEX_L2_OPSIZE_B, /* 10230 */ + IC_EVEX_L2_OPSIZE_B, /* 10231 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10232 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10233 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10234 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10235 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10236 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10237 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10238 */ + IC_EVEX_L2_W_OPSIZE_B, /* 10239 */ + IC, /* 10240 */ + IC_64BIT, /* 10241 */ + IC_XS, /* 10242 */ + IC_64BIT_XS, /* 10243 */ + IC_XD, /* 10244 */ + IC_64BIT_XD, /* 10245 */ + IC_XS, /* 10246 */ + IC_64BIT_XS, /* 10247 */ + IC, /* 10248 */ + IC_64BIT_REXW, /* 10249 */ + IC_XS, /* 10250 */ + IC_64BIT_REXW_XS, /* 10251 */ + IC_XD, /* 10252 */ + IC_64BIT_REXW_XD, /* 10253 */ + IC_XS, /* 10254 */ + IC_64BIT_REXW_XS, /* 10255 */ + IC_OPSIZE, /* 10256 */ + IC_64BIT_OPSIZE, /* 10257 */ + IC_XS_OPSIZE, /* 10258 */ + IC_64BIT_XS_OPSIZE, /* 10259 */ + IC_XD_OPSIZE, /* 10260 */ + IC_64BIT_XD_OPSIZE, /* 10261 */ + IC_XS_OPSIZE, /* 10262 */ + IC_64BIT_XD_OPSIZE, /* 10263 */ + IC_OPSIZE, /* 10264 */ + IC_64BIT_REXW_OPSIZE, /* 10265 */ + IC_XS_OPSIZE, /* 10266 */ + IC_64BIT_REXW_XS, /* 10267 */ + IC_XD_OPSIZE, /* 10268 */ + IC_64BIT_REXW_XD, /* 10269 */ + IC_XS_OPSIZE, /* 10270 */ + IC_64BIT_REXW_XS, /* 10271 */ + IC_ADSIZE, /* 10272 */ + IC_64BIT_ADSIZE, /* 10273 */ + IC_XS_ADSIZE, /* 10274 */ + IC_64BIT_XS_ADSIZE, /* 10275 */ + IC_XD_ADSIZE, /* 10276 */ + IC_64BIT_XD_ADSIZE, /* 10277 */ + IC_XS_ADSIZE, /* 10278 */ + IC_64BIT_XD_ADSIZE, /* 10279 */ + IC_ADSIZE, /* 10280 */ + IC_64BIT_REXW_ADSIZE, /* 10281 */ + IC_XS_ADSIZE, /* 10282 */ + IC_64BIT_REXW_XS, /* 10283 */ + IC_XD_ADSIZE, /* 10284 */ + IC_64BIT_REXW_XD, /* 10285 */ + IC_XS_ADSIZE, /* 10286 */ + IC_64BIT_REXW_XS, /* 10287 */ + IC_OPSIZE_ADSIZE, /* 10288 */ + IC_64BIT_OPSIZE_ADSIZE, /* 10289 */ + IC_XS_OPSIZE, /* 10290 */ + IC_64BIT_XS_OPSIZE, /* 10291 */ + IC_XD_OPSIZE, /* 10292 */ + IC_64BIT_XD_OPSIZE, /* 10293 */ + IC_XS_OPSIZE, /* 10294 */ + IC_64BIT_XD_OPSIZE, /* 10295 */ + IC_OPSIZE_ADSIZE, /* 10296 */ + IC_64BIT_REXW_OPSIZE, /* 10297 */ + IC_XS_OPSIZE, /* 10298 */ + IC_64BIT_REXW_XS, /* 10299 */ + IC_XD_OPSIZE, /* 10300 */ + IC_64BIT_REXW_XD, /* 10301 */ + IC_XS_OPSIZE, /* 10302 */ + IC_64BIT_REXW_XS, /* 10303 */ + IC_VEX, /* 10304 */ + IC_VEX, /* 10305 */ + IC_VEX_XS, /* 10306 */ + IC_VEX_XS, /* 10307 */ + IC_VEX_XD, /* 10308 */ + IC_VEX_XD, /* 10309 */ + IC_VEX_XD, /* 10310 */ + IC_VEX_XD, /* 10311 */ + IC_VEX_W, /* 10312 */ + IC_VEX_W, /* 10313 */ + IC_VEX_W_XS, /* 10314 */ + IC_VEX_W_XS, /* 10315 */ + IC_VEX_W_XD, /* 10316 */ + IC_VEX_W_XD, /* 10317 */ + IC_VEX_W_XD, /* 10318 */ + IC_VEX_W_XD, /* 10319 */ + IC_VEX_OPSIZE, /* 10320 */ + IC_VEX_OPSIZE, /* 10321 */ + IC_VEX_OPSIZE, /* 10322 */ + IC_VEX_OPSIZE, /* 10323 */ + IC_VEX_OPSIZE, /* 10324 */ + IC_VEX_OPSIZE, /* 10325 */ + IC_VEX_OPSIZE, /* 10326 */ + IC_VEX_OPSIZE, /* 10327 */ + IC_VEX_W_OPSIZE, /* 10328 */ + IC_VEX_W_OPSIZE, /* 10329 */ + IC_VEX_W_OPSIZE, /* 10330 */ + IC_VEX_W_OPSIZE, /* 10331 */ + IC_VEX_W_OPSIZE, /* 10332 */ + IC_VEX_W_OPSIZE, /* 10333 */ + IC_VEX_W_OPSIZE, /* 10334 */ + IC_VEX_W_OPSIZE, /* 10335 */ + IC_VEX, /* 10336 */ + IC_VEX, /* 10337 */ + IC_VEX_XS, /* 10338 */ + IC_VEX_XS, /* 10339 */ + IC_VEX_XD, /* 10340 */ + IC_VEX_XD, /* 10341 */ + IC_VEX_XD, /* 10342 */ + IC_VEX_XD, /* 10343 */ + IC_VEX_W, /* 10344 */ + IC_VEX_W, /* 10345 */ + IC_VEX_W_XS, /* 10346 */ + IC_VEX_W_XS, /* 10347 */ + IC_VEX_W_XD, /* 10348 */ + IC_VEX_W_XD, /* 10349 */ + IC_VEX_W_XD, /* 10350 */ + IC_VEX_W_XD, /* 10351 */ + IC_VEX_OPSIZE, /* 10352 */ + IC_VEX_OPSIZE, /* 10353 */ + IC_VEX_OPSIZE, /* 10354 */ + IC_VEX_OPSIZE, /* 10355 */ + IC_VEX_OPSIZE, /* 10356 */ + IC_VEX_OPSIZE, /* 10357 */ + IC_VEX_OPSIZE, /* 10358 */ + IC_VEX_OPSIZE, /* 10359 */ + IC_VEX_W_OPSIZE, /* 10360 */ + IC_VEX_W_OPSIZE, /* 10361 */ + IC_VEX_W_OPSIZE, /* 10362 */ + IC_VEX_W_OPSIZE, /* 10363 */ + IC_VEX_W_OPSIZE, /* 10364 */ + IC_VEX_W_OPSIZE, /* 10365 */ + IC_VEX_W_OPSIZE, /* 10366 */ + IC_VEX_W_OPSIZE, /* 10367 */ + IC_VEX_L, /* 10368 */ + IC_VEX_L, /* 10369 */ + IC_VEX_L_XS, /* 10370 */ + IC_VEX_L_XS, /* 10371 */ + IC_VEX_L_XD, /* 10372 */ + IC_VEX_L_XD, /* 10373 */ + IC_VEX_L_XD, /* 10374 */ + IC_VEX_L_XD, /* 10375 */ + IC_VEX_L_W, /* 10376 */ + IC_VEX_L_W, /* 10377 */ + IC_VEX_L_W_XS, /* 10378 */ + IC_VEX_L_W_XS, /* 10379 */ + IC_VEX_L_W_XD, /* 10380 */ + IC_VEX_L_W_XD, /* 10381 */ + IC_VEX_L_W_XD, /* 10382 */ + IC_VEX_L_W_XD, /* 10383 */ + IC_VEX_L_OPSIZE, /* 10384 */ + IC_VEX_L_OPSIZE, /* 10385 */ + IC_VEX_L_OPSIZE, /* 10386 */ + IC_VEX_L_OPSIZE, /* 10387 */ + IC_VEX_L_OPSIZE, /* 10388 */ + IC_VEX_L_OPSIZE, /* 10389 */ + IC_VEX_L_OPSIZE, /* 10390 */ + IC_VEX_L_OPSIZE, /* 10391 */ + IC_VEX_L_W_OPSIZE, /* 10392 */ + IC_VEX_L_W_OPSIZE, /* 10393 */ + IC_VEX_L_W_OPSIZE, /* 10394 */ + IC_VEX_L_W_OPSIZE, /* 10395 */ + IC_VEX_L_W_OPSIZE, /* 10396 */ + IC_VEX_L_W_OPSIZE, /* 10397 */ + IC_VEX_L_W_OPSIZE, /* 10398 */ + IC_VEX_L_W_OPSIZE, /* 10399 */ + IC_VEX_L, /* 10400 */ + IC_VEX_L, /* 10401 */ + IC_VEX_L_XS, /* 10402 */ + IC_VEX_L_XS, /* 10403 */ + IC_VEX_L_XD, /* 10404 */ + IC_VEX_L_XD, /* 10405 */ + IC_VEX_L_XD, /* 10406 */ + IC_VEX_L_XD, /* 10407 */ + IC_VEX_L_W, /* 10408 */ + IC_VEX_L_W, /* 10409 */ + IC_VEX_L_W_XS, /* 10410 */ + IC_VEX_L_W_XS, /* 10411 */ + IC_VEX_L_W_XD, /* 10412 */ + IC_VEX_L_W_XD, /* 10413 */ + IC_VEX_L_W_XD, /* 10414 */ + IC_VEX_L_W_XD, /* 10415 */ + IC_VEX_L_OPSIZE, /* 10416 */ + IC_VEX_L_OPSIZE, /* 10417 */ + IC_VEX_L_OPSIZE, /* 10418 */ + IC_VEX_L_OPSIZE, /* 10419 */ + IC_VEX_L_OPSIZE, /* 10420 */ + IC_VEX_L_OPSIZE, /* 10421 */ + IC_VEX_L_OPSIZE, /* 10422 */ + IC_VEX_L_OPSIZE, /* 10423 */ + IC_VEX_L_W_OPSIZE, /* 10424 */ + IC_VEX_L_W_OPSIZE, /* 10425 */ + IC_VEX_L_W_OPSIZE, /* 10426 */ + IC_VEX_L_W_OPSIZE, /* 10427 */ + IC_VEX_L_W_OPSIZE, /* 10428 */ + IC_VEX_L_W_OPSIZE, /* 10429 */ + IC_VEX_L_W_OPSIZE, /* 10430 */ + IC_VEX_L_W_OPSIZE, /* 10431 */ + IC_VEX_L, /* 10432 */ + IC_VEX_L, /* 10433 */ + IC_VEX_L_XS, /* 10434 */ + IC_VEX_L_XS, /* 10435 */ + IC_VEX_L_XD, /* 10436 */ + IC_VEX_L_XD, /* 10437 */ + IC_VEX_L_XD, /* 10438 */ + IC_VEX_L_XD, /* 10439 */ + IC_VEX_L_W, /* 10440 */ + IC_VEX_L_W, /* 10441 */ + IC_VEX_L_W_XS, /* 10442 */ + IC_VEX_L_W_XS, /* 10443 */ + IC_VEX_L_W_XD, /* 10444 */ + IC_VEX_L_W_XD, /* 10445 */ + IC_VEX_L_W_XD, /* 10446 */ + IC_VEX_L_W_XD, /* 10447 */ + IC_VEX_L_OPSIZE, /* 10448 */ + IC_VEX_L_OPSIZE, /* 10449 */ + IC_VEX_L_OPSIZE, /* 10450 */ + IC_VEX_L_OPSIZE, /* 10451 */ + IC_VEX_L_OPSIZE, /* 10452 */ + IC_VEX_L_OPSIZE, /* 10453 */ + IC_VEX_L_OPSIZE, /* 10454 */ + IC_VEX_L_OPSIZE, /* 10455 */ + IC_VEX_L_W_OPSIZE, /* 10456 */ + IC_VEX_L_W_OPSIZE, /* 10457 */ + IC_VEX_L_W_OPSIZE, /* 10458 */ + IC_VEX_L_W_OPSIZE, /* 10459 */ + IC_VEX_L_W_OPSIZE, /* 10460 */ + IC_VEX_L_W_OPSIZE, /* 10461 */ + IC_VEX_L_W_OPSIZE, /* 10462 */ + IC_VEX_L_W_OPSIZE, /* 10463 */ + IC_VEX_L, /* 10464 */ + IC_VEX_L, /* 10465 */ + IC_VEX_L_XS, /* 10466 */ + IC_VEX_L_XS, /* 10467 */ + IC_VEX_L_XD, /* 10468 */ + IC_VEX_L_XD, /* 10469 */ + IC_VEX_L_XD, /* 10470 */ + IC_VEX_L_XD, /* 10471 */ + IC_VEX_L_W, /* 10472 */ + IC_VEX_L_W, /* 10473 */ + IC_VEX_L_W_XS, /* 10474 */ + IC_VEX_L_W_XS, /* 10475 */ + IC_VEX_L_W_XD, /* 10476 */ + IC_VEX_L_W_XD, /* 10477 */ + IC_VEX_L_W_XD, /* 10478 */ + IC_VEX_L_W_XD, /* 10479 */ + IC_VEX_L_OPSIZE, /* 10480 */ + IC_VEX_L_OPSIZE, /* 10481 */ + IC_VEX_L_OPSIZE, /* 10482 */ + IC_VEX_L_OPSIZE, /* 10483 */ + IC_VEX_L_OPSIZE, /* 10484 */ + IC_VEX_L_OPSIZE, /* 10485 */ + IC_VEX_L_OPSIZE, /* 10486 */ + IC_VEX_L_OPSIZE, /* 10487 */ + IC_VEX_L_W_OPSIZE, /* 10488 */ + IC_VEX_L_W_OPSIZE, /* 10489 */ + IC_VEX_L_W_OPSIZE, /* 10490 */ + IC_VEX_L_W_OPSIZE, /* 10491 */ + IC_VEX_L_W_OPSIZE, /* 10492 */ + IC_VEX_L_W_OPSIZE, /* 10493 */ + IC_VEX_L_W_OPSIZE, /* 10494 */ + IC_VEX_L_W_OPSIZE, /* 10495 */ + IC_EVEX_K_B, /* 10496 */ + IC_EVEX_K_B, /* 10497 */ + IC_EVEX_XS_K_B, /* 10498 */ + IC_EVEX_XS_K_B, /* 10499 */ + IC_EVEX_XD_K_B, /* 10500 */ + IC_EVEX_XD_K_B, /* 10501 */ + IC_EVEX_XD_K_B, /* 10502 */ + IC_EVEX_XD_K_B, /* 10503 */ + IC_EVEX_W_K_B, /* 10504 */ + IC_EVEX_W_K_B, /* 10505 */ + IC_EVEX_W_XS_K_B, /* 10506 */ + IC_EVEX_W_XS_K_B, /* 10507 */ + IC_EVEX_W_XD_K_B, /* 10508 */ + IC_EVEX_W_XD_K_B, /* 10509 */ + IC_EVEX_W_XD_K_B, /* 10510 */ + IC_EVEX_W_XD_K_B, /* 10511 */ + IC_EVEX_OPSIZE_K_B, /* 10512 */ + IC_EVEX_OPSIZE_K_B, /* 10513 */ + IC_EVEX_OPSIZE_K_B, /* 10514 */ + IC_EVEX_OPSIZE_K_B, /* 10515 */ + IC_EVEX_OPSIZE_K_B, /* 10516 */ + IC_EVEX_OPSIZE_K_B, /* 10517 */ + IC_EVEX_OPSIZE_K_B, /* 10518 */ + IC_EVEX_OPSIZE_K_B, /* 10519 */ + IC_EVEX_W_OPSIZE_K_B, /* 10520 */ + IC_EVEX_W_OPSIZE_K_B, /* 10521 */ + IC_EVEX_W_OPSIZE_K_B, /* 10522 */ + IC_EVEX_W_OPSIZE_K_B, /* 10523 */ + IC_EVEX_W_OPSIZE_K_B, /* 10524 */ + IC_EVEX_W_OPSIZE_K_B, /* 10525 */ + IC_EVEX_W_OPSIZE_K_B, /* 10526 */ + IC_EVEX_W_OPSIZE_K_B, /* 10527 */ + IC_EVEX_K_B, /* 10528 */ + IC_EVEX_K_B, /* 10529 */ + IC_EVEX_XS_K_B, /* 10530 */ + IC_EVEX_XS_K_B, /* 10531 */ + IC_EVEX_XD_K_B, /* 10532 */ + IC_EVEX_XD_K_B, /* 10533 */ + IC_EVEX_XD_K_B, /* 10534 */ + IC_EVEX_XD_K_B, /* 10535 */ + IC_EVEX_W_K_B, /* 10536 */ + IC_EVEX_W_K_B, /* 10537 */ + IC_EVEX_W_XS_K_B, /* 10538 */ + IC_EVEX_W_XS_K_B, /* 10539 */ + IC_EVEX_W_XD_K_B, /* 10540 */ + IC_EVEX_W_XD_K_B, /* 10541 */ + IC_EVEX_W_XD_K_B, /* 10542 */ + IC_EVEX_W_XD_K_B, /* 10543 */ + IC_EVEX_OPSIZE_K_B, /* 10544 */ + IC_EVEX_OPSIZE_K_B, /* 10545 */ + IC_EVEX_OPSIZE_K_B, /* 10546 */ + IC_EVEX_OPSIZE_K_B, /* 10547 */ + IC_EVEX_OPSIZE_K_B, /* 10548 */ + IC_EVEX_OPSIZE_K_B, /* 10549 */ + IC_EVEX_OPSIZE_K_B, /* 10550 */ + IC_EVEX_OPSIZE_K_B, /* 10551 */ + IC_EVEX_W_OPSIZE_K_B, /* 10552 */ + IC_EVEX_W_OPSIZE_K_B, /* 10553 */ + IC_EVEX_W_OPSIZE_K_B, /* 10554 */ + IC_EVEX_W_OPSIZE_K_B, /* 10555 */ + IC_EVEX_W_OPSIZE_K_B, /* 10556 */ + IC_EVEX_W_OPSIZE_K_B, /* 10557 */ + IC_EVEX_W_OPSIZE_K_B, /* 10558 */ + IC_EVEX_W_OPSIZE_K_B, /* 10559 */ + IC_EVEX_K_B, /* 10560 */ + IC_EVEX_K_B, /* 10561 */ + IC_EVEX_XS_K_B, /* 10562 */ + IC_EVEX_XS_K_B, /* 10563 */ + IC_EVEX_XD_K_B, /* 10564 */ + IC_EVEX_XD_K_B, /* 10565 */ + IC_EVEX_XD_K_B, /* 10566 */ + IC_EVEX_XD_K_B, /* 10567 */ + IC_EVEX_W_K_B, /* 10568 */ + IC_EVEX_W_K_B, /* 10569 */ + IC_EVEX_W_XS_K_B, /* 10570 */ + IC_EVEX_W_XS_K_B, /* 10571 */ + IC_EVEX_W_XD_K_B, /* 10572 */ + IC_EVEX_W_XD_K_B, /* 10573 */ + IC_EVEX_W_XD_K_B, /* 10574 */ + IC_EVEX_W_XD_K_B, /* 10575 */ + IC_EVEX_OPSIZE_K_B, /* 10576 */ + IC_EVEX_OPSIZE_K_B, /* 10577 */ + IC_EVEX_OPSIZE_K_B, /* 10578 */ + IC_EVEX_OPSIZE_K_B, /* 10579 */ + IC_EVEX_OPSIZE_K_B, /* 10580 */ + IC_EVEX_OPSIZE_K_B, /* 10581 */ + IC_EVEX_OPSIZE_K_B, /* 10582 */ + IC_EVEX_OPSIZE_K_B, /* 10583 */ + IC_EVEX_W_OPSIZE_K_B, /* 10584 */ + IC_EVEX_W_OPSIZE_K_B, /* 10585 */ + IC_EVEX_W_OPSIZE_K_B, /* 10586 */ + IC_EVEX_W_OPSIZE_K_B, /* 10587 */ + IC_EVEX_W_OPSIZE_K_B, /* 10588 */ + IC_EVEX_W_OPSIZE_K_B, /* 10589 */ + IC_EVEX_W_OPSIZE_K_B, /* 10590 */ + IC_EVEX_W_OPSIZE_K_B, /* 10591 */ + IC_EVEX_K_B, /* 10592 */ + IC_EVEX_K_B, /* 10593 */ + IC_EVEX_XS_K_B, /* 10594 */ + IC_EVEX_XS_K_B, /* 10595 */ + IC_EVEX_XD_K_B, /* 10596 */ + IC_EVEX_XD_K_B, /* 10597 */ + IC_EVEX_XD_K_B, /* 10598 */ + IC_EVEX_XD_K_B, /* 10599 */ + IC_EVEX_W_K_B, /* 10600 */ + IC_EVEX_W_K_B, /* 10601 */ + IC_EVEX_W_XS_K_B, /* 10602 */ + IC_EVEX_W_XS_K_B, /* 10603 */ + IC_EVEX_W_XD_K_B, /* 10604 */ + IC_EVEX_W_XD_K_B, /* 10605 */ + IC_EVEX_W_XD_K_B, /* 10606 */ + IC_EVEX_W_XD_K_B, /* 10607 */ + IC_EVEX_OPSIZE_K_B, /* 10608 */ + IC_EVEX_OPSIZE_K_B, /* 10609 */ + IC_EVEX_OPSIZE_K_B, /* 10610 */ + IC_EVEX_OPSIZE_K_B, /* 10611 */ + IC_EVEX_OPSIZE_K_B, /* 10612 */ + IC_EVEX_OPSIZE_K_B, /* 10613 */ + IC_EVEX_OPSIZE_K_B, /* 10614 */ + IC_EVEX_OPSIZE_K_B, /* 10615 */ + IC_EVEX_W_OPSIZE_K_B, /* 10616 */ + IC_EVEX_W_OPSIZE_K_B, /* 10617 */ + IC_EVEX_W_OPSIZE_K_B, /* 10618 */ + IC_EVEX_W_OPSIZE_K_B, /* 10619 */ + IC_EVEX_W_OPSIZE_K_B, /* 10620 */ + IC_EVEX_W_OPSIZE_K_B, /* 10621 */ + IC_EVEX_W_OPSIZE_K_B, /* 10622 */ + IC_EVEX_W_OPSIZE_K_B, /* 10623 */ + IC_EVEX_K_B, /* 10624 */ + IC_EVEX_K_B, /* 10625 */ + IC_EVEX_XS_K_B, /* 10626 */ + IC_EVEX_XS_K_B, /* 10627 */ + IC_EVEX_XD_K_B, /* 10628 */ + IC_EVEX_XD_K_B, /* 10629 */ + IC_EVEX_XD_K_B, /* 10630 */ + IC_EVEX_XD_K_B, /* 10631 */ + IC_EVEX_W_K_B, /* 10632 */ + IC_EVEX_W_K_B, /* 10633 */ + IC_EVEX_W_XS_K_B, /* 10634 */ + IC_EVEX_W_XS_K_B, /* 10635 */ + IC_EVEX_W_XD_K_B, /* 10636 */ + IC_EVEX_W_XD_K_B, /* 10637 */ + IC_EVEX_W_XD_K_B, /* 10638 */ + IC_EVEX_W_XD_K_B, /* 10639 */ + IC_EVEX_OPSIZE_K_B, /* 10640 */ + IC_EVEX_OPSIZE_K_B, /* 10641 */ + IC_EVEX_OPSIZE_K_B, /* 10642 */ + IC_EVEX_OPSIZE_K_B, /* 10643 */ + IC_EVEX_OPSIZE_K_B, /* 10644 */ + IC_EVEX_OPSIZE_K_B, /* 10645 */ + IC_EVEX_OPSIZE_K_B, /* 10646 */ + IC_EVEX_OPSIZE_K_B, /* 10647 */ + IC_EVEX_W_OPSIZE_K_B, /* 10648 */ + IC_EVEX_W_OPSIZE_K_B, /* 10649 */ + IC_EVEX_W_OPSIZE_K_B, /* 10650 */ + IC_EVEX_W_OPSIZE_K_B, /* 10651 */ + IC_EVEX_W_OPSIZE_K_B, /* 10652 */ + IC_EVEX_W_OPSIZE_K_B, /* 10653 */ + IC_EVEX_W_OPSIZE_K_B, /* 10654 */ + IC_EVEX_W_OPSIZE_K_B, /* 10655 */ + IC_EVEX_K_B, /* 10656 */ + IC_EVEX_K_B, /* 10657 */ + IC_EVEX_XS_K_B, /* 10658 */ + IC_EVEX_XS_K_B, /* 10659 */ + IC_EVEX_XD_K_B, /* 10660 */ + IC_EVEX_XD_K_B, /* 10661 */ + IC_EVEX_XD_K_B, /* 10662 */ + IC_EVEX_XD_K_B, /* 10663 */ + IC_EVEX_W_K_B, /* 10664 */ + IC_EVEX_W_K_B, /* 10665 */ + IC_EVEX_W_XS_K_B, /* 10666 */ + IC_EVEX_W_XS_K_B, /* 10667 */ + IC_EVEX_W_XD_K_B, /* 10668 */ + IC_EVEX_W_XD_K_B, /* 10669 */ + IC_EVEX_W_XD_K_B, /* 10670 */ + IC_EVEX_W_XD_K_B, /* 10671 */ + IC_EVEX_OPSIZE_K_B, /* 10672 */ + IC_EVEX_OPSIZE_K_B, /* 10673 */ + IC_EVEX_OPSIZE_K_B, /* 10674 */ + IC_EVEX_OPSIZE_K_B, /* 10675 */ + IC_EVEX_OPSIZE_K_B, /* 10676 */ + IC_EVEX_OPSIZE_K_B, /* 10677 */ + IC_EVEX_OPSIZE_K_B, /* 10678 */ + IC_EVEX_OPSIZE_K_B, /* 10679 */ + IC_EVEX_W_OPSIZE_K_B, /* 10680 */ + IC_EVEX_W_OPSIZE_K_B, /* 10681 */ + IC_EVEX_W_OPSIZE_K_B, /* 10682 */ + IC_EVEX_W_OPSIZE_K_B, /* 10683 */ + IC_EVEX_W_OPSIZE_K_B, /* 10684 */ + IC_EVEX_W_OPSIZE_K_B, /* 10685 */ + IC_EVEX_W_OPSIZE_K_B, /* 10686 */ + IC_EVEX_W_OPSIZE_K_B, /* 10687 */ + IC_EVEX_K_B, /* 10688 */ + IC_EVEX_K_B, /* 10689 */ + IC_EVEX_XS_K_B, /* 10690 */ + IC_EVEX_XS_K_B, /* 10691 */ + IC_EVEX_XD_K_B, /* 10692 */ + IC_EVEX_XD_K_B, /* 10693 */ + IC_EVEX_XD_K_B, /* 10694 */ + IC_EVEX_XD_K_B, /* 10695 */ + IC_EVEX_W_K_B, /* 10696 */ + IC_EVEX_W_K_B, /* 10697 */ + IC_EVEX_W_XS_K_B, /* 10698 */ + IC_EVEX_W_XS_K_B, /* 10699 */ + IC_EVEX_W_XD_K_B, /* 10700 */ + IC_EVEX_W_XD_K_B, /* 10701 */ + IC_EVEX_W_XD_K_B, /* 10702 */ + IC_EVEX_W_XD_K_B, /* 10703 */ + IC_EVEX_OPSIZE_K_B, /* 10704 */ + IC_EVEX_OPSIZE_K_B, /* 10705 */ + IC_EVEX_OPSIZE_K_B, /* 10706 */ + IC_EVEX_OPSIZE_K_B, /* 10707 */ + IC_EVEX_OPSIZE_K_B, /* 10708 */ + IC_EVEX_OPSIZE_K_B, /* 10709 */ + IC_EVEX_OPSIZE_K_B, /* 10710 */ + IC_EVEX_OPSIZE_K_B, /* 10711 */ + IC_EVEX_W_OPSIZE_K_B, /* 10712 */ + IC_EVEX_W_OPSIZE_K_B, /* 10713 */ + IC_EVEX_W_OPSIZE_K_B, /* 10714 */ + IC_EVEX_W_OPSIZE_K_B, /* 10715 */ + IC_EVEX_W_OPSIZE_K_B, /* 10716 */ + IC_EVEX_W_OPSIZE_K_B, /* 10717 */ + IC_EVEX_W_OPSIZE_K_B, /* 10718 */ + IC_EVEX_W_OPSIZE_K_B, /* 10719 */ + IC_EVEX_K_B, /* 10720 */ + IC_EVEX_K_B, /* 10721 */ + IC_EVEX_XS_K_B, /* 10722 */ + IC_EVEX_XS_K_B, /* 10723 */ + IC_EVEX_XD_K_B, /* 10724 */ + IC_EVEX_XD_K_B, /* 10725 */ + IC_EVEX_XD_K_B, /* 10726 */ + IC_EVEX_XD_K_B, /* 10727 */ + IC_EVEX_W_K_B, /* 10728 */ + IC_EVEX_W_K_B, /* 10729 */ + IC_EVEX_W_XS_K_B, /* 10730 */ + IC_EVEX_W_XS_K_B, /* 10731 */ + IC_EVEX_W_XD_K_B, /* 10732 */ + IC_EVEX_W_XD_K_B, /* 10733 */ + IC_EVEX_W_XD_K_B, /* 10734 */ + IC_EVEX_W_XD_K_B, /* 10735 */ + IC_EVEX_OPSIZE_K_B, /* 10736 */ + IC_EVEX_OPSIZE_K_B, /* 10737 */ + IC_EVEX_OPSIZE_K_B, /* 10738 */ + IC_EVEX_OPSIZE_K_B, /* 10739 */ + IC_EVEX_OPSIZE_K_B, /* 10740 */ + IC_EVEX_OPSIZE_K_B, /* 10741 */ + IC_EVEX_OPSIZE_K_B, /* 10742 */ + IC_EVEX_OPSIZE_K_B, /* 10743 */ + IC_EVEX_W_OPSIZE_K_B, /* 10744 */ + IC_EVEX_W_OPSIZE_K_B, /* 10745 */ + IC_EVEX_W_OPSIZE_K_B, /* 10746 */ + IC_EVEX_W_OPSIZE_K_B, /* 10747 */ + IC_EVEX_W_OPSIZE_K_B, /* 10748 */ + IC_EVEX_W_OPSIZE_K_B, /* 10749 */ + IC_EVEX_W_OPSIZE_K_B, /* 10750 */ + IC_EVEX_W_OPSIZE_K_B, /* 10751 */ + IC, /* 10752 */ + IC_64BIT, /* 10753 */ + IC_XS, /* 10754 */ + IC_64BIT_XS, /* 10755 */ + IC_XD, /* 10756 */ + IC_64BIT_XD, /* 10757 */ + IC_XS, /* 10758 */ + IC_64BIT_XS, /* 10759 */ + IC, /* 10760 */ + IC_64BIT_REXW, /* 10761 */ + IC_XS, /* 10762 */ + IC_64BIT_REXW_XS, /* 10763 */ + IC_XD, /* 10764 */ + IC_64BIT_REXW_XD, /* 10765 */ + IC_XS, /* 10766 */ + IC_64BIT_REXW_XS, /* 10767 */ + IC_OPSIZE, /* 10768 */ + IC_64BIT_OPSIZE, /* 10769 */ + IC_XS_OPSIZE, /* 10770 */ + IC_64BIT_XS_OPSIZE, /* 10771 */ + IC_XD_OPSIZE, /* 10772 */ + IC_64BIT_XD_OPSIZE, /* 10773 */ + IC_XS_OPSIZE, /* 10774 */ + IC_64BIT_XD_OPSIZE, /* 10775 */ + IC_OPSIZE, /* 10776 */ + IC_64BIT_REXW_OPSIZE, /* 10777 */ + IC_XS_OPSIZE, /* 10778 */ + IC_64BIT_REXW_XS, /* 10779 */ + IC_XD_OPSIZE, /* 10780 */ + IC_64BIT_REXW_XD, /* 10781 */ + IC_XS_OPSIZE, /* 10782 */ + IC_64BIT_REXW_XS, /* 10783 */ + IC_ADSIZE, /* 10784 */ + IC_64BIT_ADSIZE, /* 10785 */ + IC_XS_ADSIZE, /* 10786 */ + IC_64BIT_XS_ADSIZE, /* 10787 */ + IC_XD_ADSIZE, /* 10788 */ + IC_64BIT_XD_ADSIZE, /* 10789 */ + IC_XS_ADSIZE, /* 10790 */ + IC_64BIT_XD_ADSIZE, /* 10791 */ + IC_ADSIZE, /* 10792 */ + IC_64BIT_REXW_ADSIZE, /* 10793 */ + IC_XS_ADSIZE, /* 10794 */ + IC_64BIT_REXW_XS, /* 10795 */ + IC_XD_ADSIZE, /* 10796 */ + IC_64BIT_REXW_XD, /* 10797 */ + IC_XS_ADSIZE, /* 10798 */ + IC_64BIT_REXW_XS, /* 10799 */ + IC_OPSIZE_ADSIZE, /* 10800 */ + IC_64BIT_OPSIZE_ADSIZE, /* 10801 */ + IC_XS_OPSIZE, /* 10802 */ + IC_64BIT_XS_OPSIZE, /* 10803 */ + IC_XD_OPSIZE, /* 10804 */ + IC_64BIT_XD_OPSIZE, /* 10805 */ + IC_XS_OPSIZE, /* 10806 */ + IC_64BIT_XD_OPSIZE, /* 10807 */ + IC_OPSIZE_ADSIZE, /* 10808 */ + IC_64BIT_REXW_OPSIZE, /* 10809 */ + IC_XS_OPSIZE, /* 10810 */ + IC_64BIT_REXW_XS, /* 10811 */ + IC_XD_OPSIZE, /* 10812 */ + IC_64BIT_REXW_XD, /* 10813 */ + IC_XS_OPSIZE, /* 10814 */ + IC_64BIT_REXW_XS, /* 10815 */ + IC_VEX, /* 10816 */ + IC_VEX, /* 10817 */ + IC_VEX_XS, /* 10818 */ + IC_VEX_XS, /* 10819 */ + IC_VEX_XD, /* 10820 */ + IC_VEX_XD, /* 10821 */ + IC_VEX_XD, /* 10822 */ + IC_VEX_XD, /* 10823 */ + IC_VEX_W, /* 10824 */ + IC_VEX_W, /* 10825 */ + IC_VEX_W_XS, /* 10826 */ + IC_VEX_W_XS, /* 10827 */ + IC_VEX_W_XD, /* 10828 */ + IC_VEX_W_XD, /* 10829 */ + IC_VEX_W_XD, /* 10830 */ + IC_VEX_W_XD, /* 10831 */ + IC_VEX_OPSIZE, /* 10832 */ + IC_VEX_OPSIZE, /* 10833 */ + IC_VEX_OPSIZE, /* 10834 */ + IC_VEX_OPSIZE, /* 10835 */ + IC_VEX_OPSIZE, /* 10836 */ + IC_VEX_OPSIZE, /* 10837 */ + IC_VEX_OPSIZE, /* 10838 */ + IC_VEX_OPSIZE, /* 10839 */ + IC_VEX_W_OPSIZE, /* 10840 */ + IC_VEX_W_OPSIZE, /* 10841 */ + IC_VEX_W_OPSIZE, /* 10842 */ + IC_VEX_W_OPSIZE, /* 10843 */ + IC_VEX_W_OPSIZE, /* 10844 */ + IC_VEX_W_OPSIZE, /* 10845 */ + IC_VEX_W_OPSIZE, /* 10846 */ + IC_VEX_W_OPSIZE, /* 10847 */ + IC_VEX, /* 10848 */ + IC_VEX, /* 10849 */ + IC_VEX_XS, /* 10850 */ + IC_VEX_XS, /* 10851 */ + IC_VEX_XD, /* 10852 */ + IC_VEX_XD, /* 10853 */ + IC_VEX_XD, /* 10854 */ + IC_VEX_XD, /* 10855 */ + IC_VEX_W, /* 10856 */ + IC_VEX_W, /* 10857 */ + IC_VEX_W_XS, /* 10858 */ + IC_VEX_W_XS, /* 10859 */ + IC_VEX_W_XD, /* 10860 */ + IC_VEX_W_XD, /* 10861 */ + IC_VEX_W_XD, /* 10862 */ + IC_VEX_W_XD, /* 10863 */ + IC_VEX_OPSIZE, /* 10864 */ + IC_VEX_OPSIZE, /* 10865 */ + IC_VEX_OPSIZE, /* 10866 */ + IC_VEX_OPSIZE, /* 10867 */ + IC_VEX_OPSIZE, /* 10868 */ + IC_VEX_OPSIZE, /* 10869 */ + IC_VEX_OPSIZE, /* 10870 */ + IC_VEX_OPSIZE, /* 10871 */ + IC_VEX_W_OPSIZE, /* 10872 */ + IC_VEX_W_OPSIZE, /* 10873 */ + IC_VEX_W_OPSIZE, /* 10874 */ + IC_VEX_W_OPSIZE, /* 10875 */ + IC_VEX_W_OPSIZE, /* 10876 */ + IC_VEX_W_OPSIZE, /* 10877 */ + IC_VEX_W_OPSIZE, /* 10878 */ + IC_VEX_W_OPSIZE, /* 10879 */ + IC_VEX_L, /* 10880 */ + IC_VEX_L, /* 10881 */ + IC_VEX_L_XS, /* 10882 */ + IC_VEX_L_XS, /* 10883 */ + IC_VEX_L_XD, /* 10884 */ + IC_VEX_L_XD, /* 10885 */ + IC_VEX_L_XD, /* 10886 */ + IC_VEX_L_XD, /* 10887 */ + IC_VEX_L_W, /* 10888 */ + IC_VEX_L_W, /* 10889 */ + IC_VEX_L_W_XS, /* 10890 */ + IC_VEX_L_W_XS, /* 10891 */ + IC_VEX_L_W_XD, /* 10892 */ + IC_VEX_L_W_XD, /* 10893 */ + IC_VEX_L_W_XD, /* 10894 */ + IC_VEX_L_W_XD, /* 10895 */ + IC_VEX_L_OPSIZE, /* 10896 */ + IC_VEX_L_OPSIZE, /* 10897 */ + IC_VEX_L_OPSIZE, /* 10898 */ + IC_VEX_L_OPSIZE, /* 10899 */ + IC_VEX_L_OPSIZE, /* 10900 */ + IC_VEX_L_OPSIZE, /* 10901 */ + IC_VEX_L_OPSIZE, /* 10902 */ + IC_VEX_L_OPSIZE, /* 10903 */ + IC_VEX_L_W_OPSIZE, /* 10904 */ + IC_VEX_L_W_OPSIZE, /* 10905 */ + IC_VEX_L_W_OPSIZE, /* 10906 */ + IC_VEX_L_W_OPSIZE, /* 10907 */ + IC_VEX_L_W_OPSIZE, /* 10908 */ + IC_VEX_L_W_OPSIZE, /* 10909 */ + IC_VEX_L_W_OPSIZE, /* 10910 */ + IC_VEX_L_W_OPSIZE, /* 10911 */ + IC_VEX_L, /* 10912 */ + IC_VEX_L, /* 10913 */ + IC_VEX_L_XS, /* 10914 */ + IC_VEX_L_XS, /* 10915 */ + IC_VEX_L_XD, /* 10916 */ + IC_VEX_L_XD, /* 10917 */ + IC_VEX_L_XD, /* 10918 */ + IC_VEX_L_XD, /* 10919 */ + IC_VEX_L_W, /* 10920 */ + IC_VEX_L_W, /* 10921 */ + IC_VEX_L_W_XS, /* 10922 */ + IC_VEX_L_W_XS, /* 10923 */ + IC_VEX_L_W_XD, /* 10924 */ + IC_VEX_L_W_XD, /* 10925 */ + IC_VEX_L_W_XD, /* 10926 */ + IC_VEX_L_W_XD, /* 10927 */ + IC_VEX_L_OPSIZE, /* 10928 */ + IC_VEX_L_OPSIZE, /* 10929 */ + IC_VEX_L_OPSIZE, /* 10930 */ + IC_VEX_L_OPSIZE, /* 10931 */ + IC_VEX_L_OPSIZE, /* 10932 */ + IC_VEX_L_OPSIZE, /* 10933 */ + IC_VEX_L_OPSIZE, /* 10934 */ + IC_VEX_L_OPSIZE, /* 10935 */ + IC_VEX_L_W_OPSIZE, /* 10936 */ + IC_VEX_L_W_OPSIZE, /* 10937 */ + IC_VEX_L_W_OPSIZE, /* 10938 */ + IC_VEX_L_W_OPSIZE, /* 10939 */ + IC_VEX_L_W_OPSIZE, /* 10940 */ + IC_VEX_L_W_OPSIZE, /* 10941 */ + IC_VEX_L_W_OPSIZE, /* 10942 */ + IC_VEX_L_W_OPSIZE, /* 10943 */ + IC_VEX_L, /* 10944 */ + IC_VEX_L, /* 10945 */ + IC_VEX_L_XS, /* 10946 */ + IC_VEX_L_XS, /* 10947 */ + IC_VEX_L_XD, /* 10948 */ + IC_VEX_L_XD, /* 10949 */ + IC_VEX_L_XD, /* 10950 */ + IC_VEX_L_XD, /* 10951 */ + IC_VEX_L_W, /* 10952 */ + IC_VEX_L_W, /* 10953 */ + IC_VEX_L_W_XS, /* 10954 */ + IC_VEX_L_W_XS, /* 10955 */ + IC_VEX_L_W_XD, /* 10956 */ + IC_VEX_L_W_XD, /* 10957 */ + IC_VEX_L_W_XD, /* 10958 */ + IC_VEX_L_W_XD, /* 10959 */ + IC_VEX_L_OPSIZE, /* 10960 */ + IC_VEX_L_OPSIZE, /* 10961 */ + IC_VEX_L_OPSIZE, /* 10962 */ + IC_VEX_L_OPSIZE, /* 10963 */ + IC_VEX_L_OPSIZE, /* 10964 */ + IC_VEX_L_OPSIZE, /* 10965 */ + IC_VEX_L_OPSIZE, /* 10966 */ + IC_VEX_L_OPSIZE, /* 10967 */ + IC_VEX_L_W_OPSIZE, /* 10968 */ + IC_VEX_L_W_OPSIZE, /* 10969 */ + IC_VEX_L_W_OPSIZE, /* 10970 */ + IC_VEX_L_W_OPSIZE, /* 10971 */ + IC_VEX_L_W_OPSIZE, /* 10972 */ + IC_VEX_L_W_OPSIZE, /* 10973 */ + IC_VEX_L_W_OPSIZE, /* 10974 */ + IC_VEX_L_W_OPSIZE, /* 10975 */ + IC_VEX_L, /* 10976 */ + IC_VEX_L, /* 10977 */ + IC_VEX_L_XS, /* 10978 */ + IC_VEX_L_XS, /* 10979 */ + IC_VEX_L_XD, /* 10980 */ + IC_VEX_L_XD, /* 10981 */ + IC_VEX_L_XD, /* 10982 */ + IC_VEX_L_XD, /* 10983 */ + IC_VEX_L_W, /* 10984 */ + IC_VEX_L_W, /* 10985 */ + IC_VEX_L_W_XS, /* 10986 */ + IC_VEX_L_W_XS, /* 10987 */ + IC_VEX_L_W_XD, /* 10988 */ + IC_VEX_L_W_XD, /* 10989 */ + IC_VEX_L_W_XD, /* 10990 */ + IC_VEX_L_W_XD, /* 10991 */ + IC_VEX_L_OPSIZE, /* 10992 */ + IC_VEX_L_OPSIZE, /* 10993 */ + IC_VEX_L_OPSIZE, /* 10994 */ + IC_VEX_L_OPSIZE, /* 10995 */ + IC_VEX_L_OPSIZE, /* 10996 */ + IC_VEX_L_OPSIZE, /* 10997 */ + IC_VEX_L_OPSIZE, /* 10998 */ + IC_VEX_L_OPSIZE, /* 10999 */ + IC_VEX_L_W_OPSIZE, /* 11000 */ + IC_VEX_L_W_OPSIZE, /* 11001 */ + IC_VEX_L_W_OPSIZE, /* 11002 */ + IC_VEX_L_W_OPSIZE, /* 11003 */ + IC_VEX_L_W_OPSIZE, /* 11004 */ + IC_VEX_L_W_OPSIZE, /* 11005 */ + IC_VEX_L_W_OPSIZE, /* 11006 */ + IC_VEX_L_W_OPSIZE, /* 11007 */ + IC_EVEX_L_K_B, /* 11008 */ + IC_EVEX_L_K_B, /* 11009 */ + IC_EVEX_L_XS_K_B, /* 11010 */ + IC_EVEX_L_XS_K_B, /* 11011 */ + IC_EVEX_L_XD_K_B, /* 11012 */ + IC_EVEX_L_XD_K_B, /* 11013 */ + IC_EVEX_L_XD_K_B, /* 11014 */ + IC_EVEX_L_XD_K_B, /* 11015 */ + IC_EVEX_L_W_K_B, /* 11016 */ + IC_EVEX_L_W_K_B, /* 11017 */ + IC_EVEX_L_W_XS_K_B, /* 11018 */ + IC_EVEX_L_W_XS_K_B, /* 11019 */ + IC_EVEX_L_W_XD_K_B, /* 11020 */ + IC_EVEX_L_W_XD_K_B, /* 11021 */ + IC_EVEX_L_W_XD_K_B, /* 11022 */ + IC_EVEX_L_W_XD_K_B, /* 11023 */ + IC_EVEX_L_OPSIZE_K_B, /* 11024 */ + IC_EVEX_L_OPSIZE_K_B, /* 11025 */ + IC_EVEX_L_OPSIZE_K_B, /* 11026 */ + IC_EVEX_L_OPSIZE_K_B, /* 11027 */ + IC_EVEX_L_OPSIZE_K_B, /* 11028 */ + IC_EVEX_L_OPSIZE_K_B, /* 11029 */ + IC_EVEX_L_OPSIZE_K_B, /* 11030 */ + IC_EVEX_L_OPSIZE_K_B, /* 11031 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11032 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11033 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11034 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11035 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11036 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11037 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11038 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11039 */ + IC_EVEX_L_K_B, /* 11040 */ + IC_EVEX_L_K_B, /* 11041 */ + IC_EVEX_L_XS_K_B, /* 11042 */ + IC_EVEX_L_XS_K_B, /* 11043 */ + IC_EVEX_L_XD_K_B, /* 11044 */ + IC_EVEX_L_XD_K_B, /* 11045 */ + IC_EVEX_L_XD_K_B, /* 11046 */ + IC_EVEX_L_XD_K_B, /* 11047 */ + IC_EVEX_L_W_K_B, /* 11048 */ + IC_EVEX_L_W_K_B, /* 11049 */ + IC_EVEX_L_W_XS_K_B, /* 11050 */ + IC_EVEX_L_W_XS_K_B, /* 11051 */ + IC_EVEX_L_W_XD_K_B, /* 11052 */ + IC_EVEX_L_W_XD_K_B, /* 11053 */ + IC_EVEX_L_W_XD_K_B, /* 11054 */ + IC_EVEX_L_W_XD_K_B, /* 11055 */ + IC_EVEX_L_OPSIZE_K_B, /* 11056 */ + IC_EVEX_L_OPSIZE_K_B, /* 11057 */ + IC_EVEX_L_OPSIZE_K_B, /* 11058 */ + IC_EVEX_L_OPSIZE_K_B, /* 11059 */ + IC_EVEX_L_OPSIZE_K_B, /* 11060 */ + IC_EVEX_L_OPSIZE_K_B, /* 11061 */ + IC_EVEX_L_OPSIZE_K_B, /* 11062 */ + IC_EVEX_L_OPSIZE_K_B, /* 11063 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11064 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11065 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11066 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11067 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11068 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11069 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11070 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11071 */ + IC_EVEX_L_K_B, /* 11072 */ + IC_EVEX_L_K_B, /* 11073 */ + IC_EVEX_L_XS_K_B, /* 11074 */ + IC_EVEX_L_XS_K_B, /* 11075 */ + IC_EVEX_L_XD_K_B, /* 11076 */ + IC_EVEX_L_XD_K_B, /* 11077 */ + IC_EVEX_L_XD_K_B, /* 11078 */ + IC_EVEX_L_XD_K_B, /* 11079 */ + IC_EVEX_L_W_K_B, /* 11080 */ + IC_EVEX_L_W_K_B, /* 11081 */ + IC_EVEX_L_W_XS_K_B, /* 11082 */ + IC_EVEX_L_W_XS_K_B, /* 11083 */ + IC_EVEX_L_W_XD_K_B, /* 11084 */ + IC_EVEX_L_W_XD_K_B, /* 11085 */ + IC_EVEX_L_W_XD_K_B, /* 11086 */ + IC_EVEX_L_W_XD_K_B, /* 11087 */ + IC_EVEX_L_OPSIZE_K_B, /* 11088 */ + IC_EVEX_L_OPSIZE_K_B, /* 11089 */ + IC_EVEX_L_OPSIZE_K_B, /* 11090 */ + IC_EVEX_L_OPSIZE_K_B, /* 11091 */ + IC_EVEX_L_OPSIZE_K_B, /* 11092 */ + IC_EVEX_L_OPSIZE_K_B, /* 11093 */ + IC_EVEX_L_OPSIZE_K_B, /* 11094 */ + IC_EVEX_L_OPSIZE_K_B, /* 11095 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11096 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11097 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11098 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11099 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11100 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11101 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11102 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11103 */ + IC_EVEX_L_K_B, /* 11104 */ + IC_EVEX_L_K_B, /* 11105 */ + IC_EVEX_L_XS_K_B, /* 11106 */ + IC_EVEX_L_XS_K_B, /* 11107 */ + IC_EVEX_L_XD_K_B, /* 11108 */ + IC_EVEX_L_XD_K_B, /* 11109 */ + IC_EVEX_L_XD_K_B, /* 11110 */ + IC_EVEX_L_XD_K_B, /* 11111 */ + IC_EVEX_L_W_K_B, /* 11112 */ + IC_EVEX_L_W_K_B, /* 11113 */ + IC_EVEX_L_W_XS_K_B, /* 11114 */ + IC_EVEX_L_W_XS_K_B, /* 11115 */ + IC_EVEX_L_W_XD_K_B, /* 11116 */ + IC_EVEX_L_W_XD_K_B, /* 11117 */ + IC_EVEX_L_W_XD_K_B, /* 11118 */ + IC_EVEX_L_W_XD_K_B, /* 11119 */ + IC_EVEX_L_OPSIZE_K_B, /* 11120 */ + IC_EVEX_L_OPSIZE_K_B, /* 11121 */ + IC_EVEX_L_OPSIZE_K_B, /* 11122 */ + IC_EVEX_L_OPSIZE_K_B, /* 11123 */ + IC_EVEX_L_OPSIZE_K_B, /* 11124 */ + IC_EVEX_L_OPSIZE_K_B, /* 11125 */ + IC_EVEX_L_OPSIZE_K_B, /* 11126 */ + IC_EVEX_L_OPSIZE_K_B, /* 11127 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11128 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11129 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11130 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11131 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11132 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11133 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11134 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11135 */ + IC_EVEX_L_K_B, /* 11136 */ + IC_EVEX_L_K_B, /* 11137 */ + IC_EVEX_L_XS_K_B, /* 11138 */ + IC_EVEX_L_XS_K_B, /* 11139 */ + IC_EVEX_L_XD_K_B, /* 11140 */ + IC_EVEX_L_XD_K_B, /* 11141 */ + IC_EVEX_L_XD_K_B, /* 11142 */ + IC_EVEX_L_XD_K_B, /* 11143 */ + IC_EVEX_L_W_K_B, /* 11144 */ + IC_EVEX_L_W_K_B, /* 11145 */ + IC_EVEX_L_W_XS_K_B, /* 11146 */ + IC_EVEX_L_W_XS_K_B, /* 11147 */ + IC_EVEX_L_W_XD_K_B, /* 11148 */ + IC_EVEX_L_W_XD_K_B, /* 11149 */ + IC_EVEX_L_W_XD_K_B, /* 11150 */ + IC_EVEX_L_W_XD_K_B, /* 11151 */ + IC_EVEX_L_OPSIZE_K_B, /* 11152 */ + IC_EVEX_L_OPSIZE_K_B, /* 11153 */ + IC_EVEX_L_OPSIZE_K_B, /* 11154 */ + IC_EVEX_L_OPSIZE_K_B, /* 11155 */ + IC_EVEX_L_OPSIZE_K_B, /* 11156 */ + IC_EVEX_L_OPSIZE_K_B, /* 11157 */ + IC_EVEX_L_OPSIZE_K_B, /* 11158 */ + IC_EVEX_L_OPSIZE_K_B, /* 11159 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11160 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11161 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11162 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11163 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11164 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11165 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11166 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11167 */ + IC_EVEX_L_K_B, /* 11168 */ + IC_EVEX_L_K_B, /* 11169 */ + IC_EVEX_L_XS_K_B, /* 11170 */ + IC_EVEX_L_XS_K_B, /* 11171 */ + IC_EVEX_L_XD_K_B, /* 11172 */ + IC_EVEX_L_XD_K_B, /* 11173 */ + IC_EVEX_L_XD_K_B, /* 11174 */ + IC_EVEX_L_XD_K_B, /* 11175 */ + IC_EVEX_L_W_K_B, /* 11176 */ + IC_EVEX_L_W_K_B, /* 11177 */ + IC_EVEX_L_W_XS_K_B, /* 11178 */ + IC_EVEX_L_W_XS_K_B, /* 11179 */ + IC_EVEX_L_W_XD_K_B, /* 11180 */ + IC_EVEX_L_W_XD_K_B, /* 11181 */ + IC_EVEX_L_W_XD_K_B, /* 11182 */ + IC_EVEX_L_W_XD_K_B, /* 11183 */ + IC_EVEX_L_OPSIZE_K_B, /* 11184 */ + IC_EVEX_L_OPSIZE_K_B, /* 11185 */ + IC_EVEX_L_OPSIZE_K_B, /* 11186 */ + IC_EVEX_L_OPSIZE_K_B, /* 11187 */ + IC_EVEX_L_OPSIZE_K_B, /* 11188 */ + IC_EVEX_L_OPSIZE_K_B, /* 11189 */ + IC_EVEX_L_OPSIZE_K_B, /* 11190 */ + IC_EVEX_L_OPSIZE_K_B, /* 11191 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11192 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11193 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11194 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11195 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11196 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11197 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11198 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11199 */ + IC_EVEX_L_K_B, /* 11200 */ + IC_EVEX_L_K_B, /* 11201 */ + IC_EVEX_L_XS_K_B, /* 11202 */ + IC_EVEX_L_XS_K_B, /* 11203 */ + IC_EVEX_L_XD_K_B, /* 11204 */ + IC_EVEX_L_XD_K_B, /* 11205 */ + IC_EVEX_L_XD_K_B, /* 11206 */ + IC_EVEX_L_XD_K_B, /* 11207 */ + IC_EVEX_L_W_K_B, /* 11208 */ + IC_EVEX_L_W_K_B, /* 11209 */ + IC_EVEX_L_W_XS_K_B, /* 11210 */ + IC_EVEX_L_W_XS_K_B, /* 11211 */ + IC_EVEX_L_W_XD_K_B, /* 11212 */ + IC_EVEX_L_W_XD_K_B, /* 11213 */ + IC_EVEX_L_W_XD_K_B, /* 11214 */ + IC_EVEX_L_W_XD_K_B, /* 11215 */ + IC_EVEX_L_OPSIZE_K_B, /* 11216 */ + IC_EVEX_L_OPSIZE_K_B, /* 11217 */ + IC_EVEX_L_OPSIZE_K_B, /* 11218 */ + IC_EVEX_L_OPSIZE_K_B, /* 11219 */ + IC_EVEX_L_OPSIZE_K_B, /* 11220 */ + IC_EVEX_L_OPSIZE_K_B, /* 11221 */ + IC_EVEX_L_OPSIZE_K_B, /* 11222 */ + IC_EVEX_L_OPSIZE_K_B, /* 11223 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11224 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11225 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11226 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11227 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11228 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11229 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11230 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11231 */ + IC_EVEX_L_K_B, /* 11232 */ + IC_EVEX_L_K_B, /* 11233 */ + IC_EVEX_L_XS_K_B, /* 11234 */ + IC_EVEX_L_XS_K_B, /* 11235 */ + IC_EVEX_L_XD_K_B, /* 11236 */ + IC_EVEX_L_XD_K_B, /* 11237 */ + IC_EVEX_L_XD_K_B, /* 11238 */ + IC_EVEX_L_XD_K_B, /* 11239 */ + IC_EVEX_L_W_K_B, /* 11240 */ + IC_EVEX_L_W_K_B, /* 11241 */ + IC_EVEX_L_W_XS_K_B, /* 11242 */ + IC_EVEX_L_W_XS_K_B, /* 11243 */ + IC_EVEX_L_W_XD_K_B, /* 11244 */ + IC_EVEX_L_W_XD_K_B, /* 11245 */ + IC_EVEX_L_W_XD_K_B, /* 11246 */ + IC_EVEX_L_W_XD_K_B, /* 11247 */ + IC_EVEX_L_OPSIZE_K_B, /* 11248 */ + IC_EVEX_L_OPSIZE_K_B, /* 11249 */ + IC_EVEX_L_OPSIZE_K_B, /* 11250 */ + IC_EVEX_L_OPSIZE_K_B, /* 11251 */ + IC_EVEX_L_OPSIZE_K_B, /* 11252 */ + IC_EVEX_L_OPSIZE_K_B, /* 11253 */ + IC_EVEX_L_OPSIZE_K_B, /* 11254 */ + IC_EVEX_L_OPSIZE_K_B, /* 11255 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11256 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11257 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11258 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11259 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11260 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11261 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11262 */ + IC_EVEX_L_W_OPSIZE_K_B, /* 11263 */ + IC, /* 11264 */ + IC_64BIT, /* 11265 */ + IC_XS, /* 11266 */ + IC_64BIT_XS, /* 11267 */ + IC_XD, /* 11268 */ + IC_64BIT_XD, /* 11269 */ + IC_XS, /* 11270 */ + IC_64BIT_XS, /* 11271 */ + IC, /* 11272 */ + IC_64BIT_REXW, /* 11273 */ + IC_XS, /* 11274 */ + IC_64BIT_REXW_XS, /* 11275 */ + IC_XD, /* 11276 */ + IC_64BIT_REXW_XD, /* 11277 */ + IC_XS, /* 11278 */ + IC_64BIT_REXW_XS, /* 11279 */ + IC_OPSIZE, /* 11280 */ + IC_64BIT_OPSIZE, /* 11281 */ + IC_XS_OPSIZE, /* 11282 */ + IC_64BIT_XS_OPSIZE, /* 11283 */ + IC_XD_OPSIZE, /* 11284 */ + IC_64BIT_XD_OPSIZE, /* 11285 */ + IC_XS_OPSIZE, /* 11286 */ + IC_64BIT_XD_OPSIZE, /* 11287 */ + IC_OPSIZE, /* 11288 */ + IC_64BIT_REXW_OPSIZE, /* 11289 */ + IC_XS_OPSIZE, /* 11290 */ + IC_64BIT_REXW_XS, /* 11291 */ + IC_XD_OPSIZE, /* 11292 */ + IC_64BIT_REXW_XD, /* 11293 */ + IC_XS_OPSIZE, /* 11294 */ + IC_64BIT_REXW_XS, /* 11295 */ + IC_ADSIZE, /* 11296 */ + IC_64BIT_ADSIZE, /* 11297 */ + IC_XS_ADSIZE, /* 11298 */ + IC_64BIT_XS_ADSIZE, /* 11299 */ + IC_XD_ADSIZE, /* 11300 */ + IC_64BIT_XD_ADSIZE, /* 11301 */ + IC_XS_ADSIZE, /* 11302 */ + IC_64BIT_XD_ADSIZE, /* 11303 */ + IC_ADSIZE, /* 11304 */ + IC_64BIT_REXW_ADSIZE, /* 11305 */ + IC_XS_ADSIZE, /* 11306 */ + IC_64BIT_REXW_XS, /* 11307 */ + IC_XD_ADSIZE, /* 11308 */ + IC_64BIT_REXW_XD, /* 11309 */ + IC_XS_ADSIZE, /* 11310 */ + IC_64BIT_REXW_XS, /* 11311 */ + IC_OPSIZE_ADSIZE, /* 11312 */ + IC_64BIT_OPSIZE_ADSIZE, /* 11313 */ + IC_XS_OPSIZE, /* 11314 */ + IC_64BIT_XS_OPSIZE, /* 11315 */ + IC_XD_OPSIZE, /* 11316 */ + IC_64BIT_XD_OPSIZE, /* 11317 */ + IC_XS_OPSIZE, /* 11318 */ + IC_64BIT_XD_OPSIZE, /* 11319 */ + IC_OPSIZE_ADSIZE, /* 11320 */ + IC_64BIT_REXW_OPSIZE, /* 11321 */ + IC_XS_OPSIZE, /* 11322 */ + IC_64BIT_REXW_XS, /* 11323 */ + IC_XD_OPSIZE, /* 11324 */ + IC_64BIT_REXW_XD, /* 11325 */ + IC_XS_OPSIZE, /* 11326 */ + IC_64BIT_REXW_XS, /* 11327 */ + IC_VEX, /* 11328 */ + IC_VEX, /* 11329 */ + IC_VEX_XS, /* 11330 */ + IC_VEX_XS, /* 11331 */ + IC_VEX_XD, /* 11332 */ + IC_VEX_XD, /* 11333 */ + IC_VEX_XD, /* 11334 */ + IC_VEX_XD, /* 11335 */ + IC_VEX_W, /* 11336 */ + IC_VEX_W, /* 11337 */ + IC_VEX_W_XS, /* 11338 */ + IC_VEX_W_XS, /* 11339 */ + IC_VEX_W_XD, /* 11340 */ + IC_VEX_W_XD, /* 11341 */ + IC_VEX_W_XD, /* 11342 */ + IC_VEX_W_XD, /* 11343 */ + IC_VEX_OPSIZE, /* 11344 */ + IC_VEX_OPSIZE, /* 11345 */ + IC_VEX_OPSIZE, /* 11346 */ + IC_VEX_OPSIZE, /* 11347 */ + IC_VEX_OPSIZE, /* 11348 */ + IC_VEX_OPSIZE, /* 11349 */ + IC_VEX_OPSIZE, /* 11350 */ + IC_VEX_OPSIZE, /* 11351 */ + IC_VEX_W_OPSIZE, /* 11352 */ + IC_VEX_W_OPSIZE, /* 11353 */ + IC_VEX_W_OPSIZE, /* 11354 */ + IC_VEX_W_OPSIZE, /* 11355 */ + IC_VEX_W_OPSIZE, /* 11356 */ + IC_VEX_W_OPSIZE, /* 11357 */ + IC_VEX_W_OPSIZE, /* 11358 */ + IC_VEX_W_OPSIZE, /* 11359 */ + IC_VEX, /* 11360 */ + IC_VEX, /* 11361 */ + IC_VEX_XS, /* 11362 */ + IC_VEX_XS, /* 11363 */ + IC_VEX_XD, /* 11364 */ + IC_VEX_XD, /* 11365 */ + IC_VEX_XD, /* 11366 */ + IC_VEX_XD, /* 11367 */ + IC_VEX_W, /* 11368 */ + IC_VEX_W, /* 11369 */ + IC_VEX_W_XS, /* 11370 */ + IC_VEX_W_XS, /* 11371 */ + IC_VEX_W_XD, /* 11372 */ + IC_VEX_W_XD, /* 11373 */ + IC_VEX_W_XD, /* 11374 */ + IC_VEX_W_XD, /* 11375 */ + IC_VEX_OPSIZE, /* 11376 */ + IC_VEX_OPSIZE, /* 11377 */ + IC_VEX_OPSIZE, /* 11378 */ + IC_VEX_OPSIZE, /* 11379 */ + IC_VEX_OPSIZE, /* 11380 */ + IC_VEX_OPSIZE, /* 11381 */ + IC_VEX_OPSIZE, /* 11382 */ + IC_VEX_OPSIZE, /* 11383 */ + IC_VEX_W_OPSIZE, /* 11384 */ + IC_VEX_W_OPSIZE, /* 11385 */ + IC_VEX_W_OPSIZE, /* 11386 */ + IC_VEX_W_OPSIZE, /* 11387 */ + IC_VEX_W_OPSIZE, /* 11388 */ + IC_VEX_W_OPSIZE, /* 11389 */ + IC_VEX_W_OPSIZE, /* 11390 */ + IC_VEX_W_OPSIZE, /* 11391 */ + IC_VEX_L, /* 11392 */ + IC_VEX_L, /* 11393 */ + IC_VEX_L_XS, /* 11394 */ + IC_VEX_L_XS, /* 11395 */ + IC_VEX_L_XD, /* 11396 */ + IC_VEX_L_XD, /* 11397 */ + IC_VEX_L_XD, /* 11398 */ + IC_VEX_L_XD, /* 11399 */ + IC_VEX_L_W, /* 11400 */ + IC_VEX_L_W, /* 11401 */ + IC_VEX_L_W_XS, /* 11402 */ + IC_VEX_L_W_XS, /* 11403 */ + IC_VEX_L_W_XD, /* 11404 */ + IC_VEX_L_W_XD, /* 11405 */ + IC_VEX_L_W_XD, /* 11406 */ + IC_VEX_L_W_XD, /* 11407 */ + IC_VEX_L_OPSIZE, /* 11408 */ + IC_VEX_L_OPSIZE, /* 11409 */ + IC_VEX_L_OPSIZE, /* 11410 */ + IC_VEX_L_OPSIZE, /* 11411 */ + IC_VEX_L_OPSIZE, /* 11412 */ + IC_VEX_L_OPSIZE, /* 11413 */ + IC_VEX_L_OPSIZE, /* 11414 */ + IC_VEX_L_OPSIZE, /* 11415 */ + IC_VEX_L_W_OPSIZE, /* 11416 */ + IC_VEX_L_W_OPSIZE, /* 11417 */ + IC_VEX_L_W_OPSIZE, /* 11418 */ + IC_VEX_L_W_OPSIZE, /* 11419 */ + IC_VEX_L_W_OPSIZE, /* 11420 */ + IC_VEX_L_W_OPSIZE, /* 11421 */ + IC_VEX_L_W_OPSIZE, /* 11422 */ + IC_VEX_L_W_OPSIZE, /* 11423 */ + IC_VEX_L, /* 11424 */ + IC_VEX_L, /* 11425 */ + IC_VEX_L_XS, /* 11426 */ + IC_VEX_L_XS, /* 11427 */ + IC_VEX_L_XD, /* 11428 */ + IC_VEX_L_XD, /* 11429 */ + IC_VEX_L_XD, /* 11430 */ + IC_VEX_L_XD, /* 11431 */ + IC_VEX_L_W, /* 11432 */ + IC_VEX_L_W, /* 11433 */ + IC_VEX_L_W_XS, /* 11434 */ + IC_VEX_L_W_XS, /* 11435 */ + IC_VEX_L_W_XD, /* 11436 */ + IC_VEX_L_W_XD, /* 11437 */ + IC_VEX_L_W_XD, /* 11438 */ + IC_VEX_L_W_XD, /* 11439 */ + IC_VEX_L_OPSIZE, /* 11440 */ + IC_VEX_L_OPSIZE, /* 11441 */ + IC_VEX_L_OPSIZE, /* 11442 */ + IC_VEX_L_OPSIZE, /* 11443 */ + IC_VEX_L_OPSIZE, /* 11444 */ + IC_VEX_L_OPSIZE, /* 11445 */ + IC_VEX_L_OPSIZE, /* 11446 */ + IC_VEX_L_OPSIZE, /* 11447 */ + IC_VEX_L_W_OPSIZE, /* 11448 */ + IC_VEX_L_W_OPSIZE, /* 11449 */ + IC_VEX_L_W_OPSIZE, /* 11450 */ + IC_VEX_L_W_OPSIZE, /* 11451 */ + IC_VEX_L_W_OPSIZE, /* 11452 */ + IC_VEX_L_W_OPSIZE, /* 11453 */ + IC_VEX_L_W_OPSIZE, /* 11454 */ + IC_VEX_L_W_OPSIZE, /* 11455 */ + IC_VEX_L, /* 11456 */ + IC_VEX_L, /* 11457 */ + IC_VEX_L_XS, /* 11458 */ + IC_VEX_L_XS, /* 11459 */ + IC_VEX_L_XD, /* 11460 */ + IC_VEX_L_XD, /* 11461 */ + IC_VEX_L_XD, /* 11462 */ + IC_VEX_L_XD, /* 11463 */ + IC_VEX_L_W, /* 11464 */ + IC_VEX_L_W, /* 11465 */ + IC_VEX_L_W_XS, /* 11466 */ + IC_VEX_L_W_XS, /* 11467 */ + IC_VEX_L_W_XD, /* 11468 */ + IC_VEX_L_W_XD, /* 11469 */ + IC_VEX_L_W_XD, /* 11470 */ + IC_VEX_L_W_XD, /* 11471 */ + IC_VEX_L_OPSIZE, /* 11472 */ + IC_VEX_L_OPSIZE, /* 11473 */ + IC_VEX_L_OPSIZE, /* 11474 */ + IC_VEX_L_OPSIZE, /* 11475 */ + IC_VEX_L_OPSIZE, /* 11476 */ + IC_VEX_L_OPSIZE, /* 11477 */ + IC_VEX_L_OPSIZE, /* 11478 */ + IC_VEX_L_OPSIZE, /* 11479 */ + IC_VEX_L_W_OPSIZE, /* 11480 */ + IC_VEX_L_W_OPSIZE, /* 11481 */ + IC_VEX_L_W_OPSIZE, /* 11482 */ + IC_VEX_L_W_OPSIZE, /* 11483 */ + IC_VEX_L_W_OPSIZE, /* 11484 */ + IC_VEX_L_W_OPSIZE, /* 11485 */ + IC_VEX_L_W_OPSIZE, /* 11486 */ + IC_VEX_L_W_OPSIZE, /* 11487 */ + IC_VEX_L, /* 11488 */ + IC_VEX_L, /* 11489 */ + IC_VEX_L_XS, /* 11490 */ + IC_VEX_L_XS, /* 11491 */ + IC_VEX_L_XD, /* 11492 */ + IC_VEX_L_XD, /* 11493 */ + IC_VEX_L_XD, /* 11494 */ + IC_VEX_L_XD, /* 11495 */ + IC_VEX_L_W, /* 11496 */ + IC_VEX_L_W, /* 11497 */ + IC_VEX_L_W_XS, /* 11498 */ + IC_VEX_L_W_XS, /* 11499 */ + IC_VEX_L_W_XD, /* 11500 */ + IC_VEX_L_W_XD, /* 11501 */ + IC_VEX_L_W_XD, /* 11502 */ + IC_VEX_L_W_XD, /* 11503 */ + IC_VEX_L_OPSIZE, /* 11504 */ + IC_VEX_L_OPSIZE, /* 11505 */ + IC_VEX_L_OPSIZE, /* 11506 */ + IC_VEX_L_OPSIZE, /* 11507 */ + IC_VEX_L_OPSIZE, /* 11508 */ + IC_VEX_L_OPSIZE, /* 11509 */ + IC_VEX_L_OPSIZE, /* 11510 */ + IC_VEX_L_OPSIZE, /* 11511 */ + IC_VEX_L_W_OPSIZE, /* 11512 */ + IC_VEX_L_W_OPSIZE, /* 11513 */ + IC_VEX_L_W_OPSIZE, /* 11514 */ + IC_VEX_L_W_OPSIZE, /* 11515 */ + IC_VEX_L_W_OPSIZE, /* 11516 */ + IC_VEX_L_W_OPSIZE, /* 11517 */ + IC_VEX_L_W_OPSIZE, /* 11518 */ + IC_VEX_L_W_OPSIZE, /* 11519 */ + IC_EVEX_L2_K_B, /* 11520 */ + IC_EVEX_L2_K_B, /* 11521 */ + IC_EVEX_L2_XS_K_B, /* 11522 */ + IC_EVEX_L2_XS_K_B, /* 11523 */ + IC_EVEX_L2_XD_K_B, /* 11524 */ + IC_EVEX_L2_XD_K_B, /* 11525 */ + IC_EVEX_L2_XD_K_B, /* 11526 */ + IC_EVEX_L2_XD_K_B, /* 11527 */ + IC_EVEX_L2_W_K_B, /* 11528 */ + IC_EVEX_L2_W_K_B, /* 11529 */ + IC_EVEX_L2_W_XS_K_B, /* 11530 */ + IC_EVEX_L2_W_XS_K_B, /* 11531 */ + IC_EVEX_L2_W_XD_K_B, /* 11532 */ + IC_EVEX_L2_W_XD_K_B, /* 11533 */ + IC_EVEX_L2_W_XD_K_B, /* 11534 */ + IC_EVEX_L2_W_XD_K_B, /* 11535 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11536 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11537 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11538 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11539 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11540 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11541 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11542 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11543 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11544 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11545 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11546 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11547 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11548 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11549 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11550 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11551 */ + IC_EVEX_L2_K_B, /* 11552 */ + IC_EVEX_L2_K_B, /* 11553 */ + IC_EVEX_L2_XS_K_B, /* 11554 */ + IC_EVEX_L2_XS_K_B, /* 11555 */ + IC_EVEX_L2_XD_K_B, /* 11556 */ + IC_EVEX_L2_XD_K_B, /* 11557 */ + IC_EVEX_L2_XD_K_B, /* 11558 */ + IC_EVEX_L2_XD_K_B, /* 11559 */ + IC_EVEX_L2_W_K_B, /* 11560 */ + IC_EVEX_L2_W_K_B, /* 11561 */ + IC_EVEX_L2_W_XS_K_B, /* 11562 */ + IC_EVEX_L2_W_XS_K_B, /* 11563 */ + IC_EVEX_L2_W_XD_K_B, /* 11564 */ + IC_EVEX_L2_W_XD_K_B, /* 11565 */ + IC_EVEX_L2_W_XD_K_B, /* 11566 */ + IC_EVEX_L2_W_XD_K_B, /* 11567 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11568 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11569 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11570 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11571 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11572 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11573 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11574 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11575 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11576 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11577 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11578 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11579 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11580 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11581 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11582 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11583 */ + IC_EVEX_L2_K_B, /* 11584 */ + IC_EVEX_L2_K_B, /* 11585 */ + IC_EVEX_L2_XS_K_B, /* 11586 */ + IC_EVEX_L2_XS_K_B, /* 11587 */ + IC_EVEX_L2_XD_K_B, /* 11588 */ + IC_EVEX_L2_XD_K_B, /* 11589 */ + IC_EVEX_L2_XD_K_B, /* 11590 */ + IC_EVEX_L2_XD_K_B, /* 11591 */ + IC_EVEX_L2_W_K_B, /* 11592 */ + IC_EVEX_L2_W_K_B, /* 11593 */ + IC_EVEX_L2_W_XS_K_B, /* 11594 */ + IC_EVEX_L2_W_XS_K_B, /* 11595 */ + IC_EVEX_L2_W_XD_K_B, /* 11596 */ + IC_EVEX_L2_W_XD_K_B, /* 11597 */ + IC_EVEX_L2_W_XD_K_B, /* 11598 */ + IC_EVEX_L2_W_XD_K_B, /* 11599 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11600 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11601 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11602 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11603 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11604 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11605 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11606 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11607 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11608 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11609 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11610 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11611 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11612 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11613 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11614 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11615 */ + IC_EVEX_L2_K_B, /* 11616 */ + IC_EVEX_L2_K_B, /* 11617 */ + IC_EVEX_L2_XS_K_B, /* 11618 */ + IC_EVEX_L2_XS_K_B, /* 11619 */ + IC_EVEX_L2_XD_K_B, /* 11620 */ + IC_EVEX_L2_XD_K_B, /* 11621 */ + IC_EVEX_L2_XD_K_B, /* 11622 */ + IC_EVEX_L2_XD_K_B, /* 11623 */ + IC_EVEX_L2_W_K_B, /* 11624 */ + IC_EVEX_L2_W_K_B, /* 11625 */ + IC_EVEX_L2_W_XS_K_B, /* 11626 */ + IC_EVEX_L2_W_XS_K_B, /* 11627 */ + IC_EVEX_L2_W_XD_K_B, /* 11628 */ + IC_EVEX_L2_W_XD_K_B, /* 11629 */ + IC_EVEX_L2_W_XD_K_B, /* 11630 */ + IC_EVEX_L2_W_XD_K_B, /* 11631 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11632 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11633 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11634 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11635 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11636 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11637 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11638 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11639 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11640 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11641 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11642 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11643 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11644 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11645 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11646 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11647 */ + IC_EVEX_L2_K_B, /* 11648 */ + IC_EVEX_L2_K_B, /* 11649 */ + IC_EVEX_L2_XS_K_B, /* 11650 */ + IC_EVEX_L2_XS_K_B, /* 11651 */ + IC_EVEX_L2_XD_K_B, /* 11652 */ + IC_EVEX_L2_XD_K_B, /* 11653 */ + IC_EVEX_L2_XD_K_B, /* 11654 */ + IC_EVEX_L2_XD_K_B, /* 11655 */ + IC_EVEX_L2_W_K_B, /* 11656 */ + IC_EVEX_L2_W_K_B, /* 11657 */ + IC_EVEX_L2_W_XS_K_B, /* 11658 */ + IC_EVEX_L2_W_XS_K_B, /* 11659 */ + IC_EVEX_L2_W_XD_K_B, /* 11660 */ + IC_EVEX_L2_W_XD_K_B, /* 11661 */ + IC_EVEX_L2_W_XD_K_B, /* 11662 */ + IC_EVEX_L2_W_XD_K_B, /* 11663 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11664 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11665 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11666 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11667 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11668 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11669 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11670 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11671 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11672 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11673 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11674 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11675 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11676 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11677 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11678 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11679 */ + IC_EVEX_L2_K_B, /* 11680 */ + IC_EVEX_L2_K_B, /* 11681 */ + IC_EVEX_L2_XS_K_B, /* 11682 */ + IC_EVEX_L2_XS_K_B, /* 11683 */ + IC_EVEX_L2_XD_K_B, /* 11684 */ + IC_EVEX_L2_XD_K_B, /* 11685 */ + IC_EVEX_L2_XD_K_B, /* 11686 */ + IC_EVEX_L2_XD_K_B, /* 11687 */ + IC_EVEX_L2_W_K_B, /* 11688 */ + IC_EVEX_L2_W_K_B, /* 11689 */ + IC_EVEX_L2_W_XS_K_B, /* 11690 */ + IC_EVEX_L2_W_XS_K_B, /* 11691 */ + IC_EVEX_L2_W_XD_K_B, /* 11692 */ + IC_EVEX_L2_W_XD_K_B, /* 11693 */ + IC_EVEX_L2_W_XD_K_B, /* 11694 */ + IC_EVEX_L2_W_XD_K_B, /* 11695 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11696 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11697 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11698 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11699 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11700 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11701 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11702 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11703 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11704 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11705 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11706 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11707 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11708 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11709 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11710 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11711 */ + IC_EVEX_L2_K_B, /* 11712 */ + IC_EVEX_L2_K_B, /* 11713 */ + IC_EVEX_L2_XS_K_B, /* 11714 */ + IC_EVEX_L2_XS_K_B, /* 11715 */ + IC_EVEX_L2_XD_K_B, /* 11716 */ + IC_EVEX_L2_XD_K_B, /* 11717 */ + IC_EVEX_L2_XD_K_B, /* 11718 */ + IC_EVEX_L2_XD_K_B, /* 11719 */ + IC_EVEX_L2_W_K_B, /* 11720 */ + IC_EVEX_L2_W_K_B, /* 11721 */ + IC_EVEX_L2_W_XS_K_B, /* 11722 */ + IC_EVEX_L2_W_XS_K_B, /* 11723 */ + IC_EVEX_L2_W_XD_K_B, /* 11724 */ + IC_EVEX_L2_W_XD_K_B, /* 11725 */ + IC_EVEX_L2_W_XD_K_B, /* 11726 */ + IC_EVEX_L2_W_XD_K_B, /* 11727 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11728 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11729 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11730 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11731 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11732 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11733 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11734 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11735 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11736 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11737 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11738 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11739 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11740 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11741 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11742 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11743 */ + IC_EVEX_L2_K_B, /* 11744 */ + IC_EVEX_L2_K_B, /* 11745 */ + IC_EVEX_L2_XS_K_B, /* 11746 */ + IC_EVEX_L2_XS_K_B, /* 11747 */ + IC_EVEX_L2_XD_K_B, /* 11748 */ + IC_EVEX_L2_XD_K_B, /* 11749 */ + IC_EVEX_L2_XD_K_B, /* 11750 */ + IC_EVEX_L2_XD_K_B, /* 11751 */ + IC_EVEX_L2_W_K_B, /* 11752 */ + IC_EVEX_L2_W_K_B, /* 11753 */ + IC_EVEX_L2_W_XS_K_B, /* 11754 */ + IC_EVEX_L2_W_XS_K_B, /* 11755 */ + IC_EVEX_L2_W_XD_K_B, /* 11756 */ + IC_EVEX_L2_W_XD_K_B, /* 11757 */ + IC_EVEX_L2_W_XD_K_B, /* 11758 */ + IC_EVEX_L2_W_XD_K_B, /* 11759 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11760 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11761 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11762 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11763 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11764 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11765 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11766 */ + IC_EVEX_L2_OPSIZE_K_B, /* 11767 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11768 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11769 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11770 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11771 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11772 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11773 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11774 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 11775 */ + IC, /* 11776 */ + IC_64BIT, /* 11777 */ + IC_XS, /* 11778 */ + IC_64BIT_XS, /* 11779 */ + IC_XD, /* 11780 */ + IC_64BIT_XD, /* 11781 */ + IC_XS, /* 11782 */ + IC_64BIT_XS, /* 11783 */ + IC, /* 11784 */ + IC_64BIT_REXW, /* 11785 */ + IC_XS, /* 11786 */ + IC_64BIT_REXW_XS, /* 11787 */ + IC_XD, /* 11788 */ + IC_64BIT_REXW_XD, /* 11789 */ + IC_XS, /* 11790 */ + IC_64BIT_REXW_XS, /* 11791 */ + IC_OPSIZE, /* 11792 */ + IC_64BIT_OPSIZE, /* 11793 */ + IC_XS_OPSIZE, /* 11794 */ + IC_64BIT_XS_OPSIZE, /* 11795 */ + IC_XD_OPSIZE, /* 11796 */ + IC_64BIT_XD_OPSIZE, /* 11797 */ + IC_XS_OPSIZE, /* 11798 */ + IC_64BIT_XD_OPSIZE, /* 11799 */ + IC_OPSIZE, /* 11800 */ + IC_64BIT_REXW_OPSIZE, /* 11801 */ + IC_XS_OPSIZE, /* 11802 */ + IC_64BIT_REXW_XS, /* 11803 */ + IC_XD_OPSIZE, /* 11804 */ + IC_64BIT_REXW_XD, /* 11805 */ + IC_XS_OPSIZE, /* 11806 */ + IC_64BIT_REXW_XS, /* 11807 */ + IC_ADSIZE, /* 11808 */ + IC_64BIT_ADSIZE, /* 11809 */ + IC_XS_ADSIZE, /* 11810 */ + IC_64BIT_XS_ADSIZE, /* 11811 */ + IC_XD_ADSIZE, /* 11812 */ + IC_64BIT_XD_ADSIZE, /* 11813 */ + IC_XS_ADSIZE, /* 11814 */ + IC_64BIT_XD_ADSIZE, /* 11815 */ + IC_ADSIZE, /* 11816 */ + IC_64BIT_REXW_ADSIZE, /* 11817 */ + IC_XS_ADSIZE, /* 11818 */ + IC_64BIT_REXW_XS, /* 11819 */ + IC_XD_ADSIZE, /* 11820 */ + IC_64BIT_REXW_XD, /* 11821 */ + IC_XS_ADSIZE, /* 11822 */ + IC_64BIT_REXW_XS, /* 11823 */ + IC_OPSIZE_ADSIZE, /* 11824 */ + IC_64BIT_OPSIZE_ADSIZE, /* 11825 */ + IC_XS_OPSIZE, /* 11826 */ + IC_64BIT_XS_OPSIZE, /* 11827 */ + IC_XD_OPSIZE, /* 11828 */ + IC_64BIT_XD_OPSIZE, /* 11829 */ + IC_XS_OPSIZE, /* 11830 */ + IC_64BIT_XD_OPSIZE, /* 11831 */ + IC_OPSIZE_ADSIZE, /* 11832 */ + IC_64BIT_REXW_OPSIZE, /* 11833 */ + IC_XS_OPSIZE, /* 11834 */ + IC_64BIT_REXW_XS, /* 11835 */ + IC_XD_OPSIZE, /* 11836 */ + IC_64BIT_REXW_XD, /* 11837 */ + IC_XS_OPSIZE, /* 11838 */ + IC_64BIT_REXW_XS, /* 11839 */ + IC_VEX, /* 11840 */ + IC_VEX, /* 11841 */ + IC_VEX_XS, /* 11842 */ + IC_VEX_XS, /* 11843 */ + IC_VEX_XD, /* 11844 */ + IC_VEX_XD, /* 11845 */ + IC_VEX_XD, /* 11846 */ + IC_VEX_XD, /* 11847 */ + IC_VEX_W, /* 11848 */ + IC_VEX_W, /* 11849 */ + IC_VEX_W_XS, /* 11850 */ + IC_VEX_W_XS, /* 11851 */ + IC_VEX_W_XD, /* 11852 */ + IC_VEX_W_XD, /* 11853 */ + IC_VEX_W_XD, /* 11854 */ + IC_VEX_W_XD, /* 11855 */ + IC_VEX_OPSIZE, /* 11856 */ + IC_VEX_OPSIZE, /* 11857 */ + IC_VEX_OPSIZE, /* 11858 */ + IC_VEX_OPSIZE, /* 11859 */ + IC_VEX_OPSIZE, /* 11860 */ + IC_VEX_OPSIZE, /* 11861 */ + IC_VEX_OPSIZE, /* 11862 */ + IC_VEX_OPSIZE, /* 11863 */ + IC_VEX_W_OPSIZE, /* 11864 */ + IC_VEX_W_OPSIZE, /* 11865 */ + IC_VEX_W_OPSIZE, /* 11866 */ + IC_VEX_W_OPSIZE, /* 11867 */ + IC_VEX_W_OPSIZE, /* 11868 */ + IC_VEX_W_OPSIZE, /* 11869 */ + IC_VEX_W_OPSIZE, /* 11870 */ + IC_VEX_W_OPSIZE, /* 11871 */ + IC_VEX, /* 11872 */ + IC_VEX, /* 11873 */ + IC_VEX_XS, /* 11874 */ + IC_VEX_XS, /* 11875 */ + IC_VEX_XD, /* 11876 */ + IC_VEX_XD, /* 11877 */ + IC_VEX_XD, /* 11878 */ + IC_VEX_XD, /* 11879 */ + IC_VEX_W, /* 11880 */ + IC_VEX_W, /* 11881 */ + IC_VEX_W_XS, /* 11882 */ + IC_VEX_W_XS, /* 11883 */ + IC_VEX_W_XD, /* 11884 */ + IC_VEX_W_XD, /* 11885 */ + IC_VEX_W_XD, /* 11886 */ + IC_VEX_W_XD, /* 11887 */ + IC_VEX_OPSIZE, /* 11888 */ + IC_VEX_OPSIZE, /* 11889 */ + IC_VEX_OPSIZE, /* 11890 */ + IC_VEX_OPSIZE, /* 11891 */ + IC_VEX_OPSIZE, /* 11892 */ + IC_VEX_OPSIZE, /* 11893 */ + IC_VEX_OPSIZE, /* 11894 */ + IC_VEX_OPSIZE, /* 11895 */ + IC_VEX_W_OPSIZE, /* 11896 */ + IC_VEX_W_OPSIZE, /* 11897 */ + IC_VEX_W_OPSIZE, /* 11898 */ + IC_VEX_W_OPSIZE, /* 11899 */ + IC_VEX_W_OPSIZE, /* 11900 */ + IC_VEX_W_OPSIZE, /* 11901 */ + IC_VEX_W_OPSIZE, /* 11902 */ + IC_VEX_W_OPSIZE, /* 11903 */ + IC_VEX_L, /* 11904 */ + IC_VEX_L, /* 11905 */ + IC_VEX_L_XS, /* 11906 */ + IC_VEX_L_XS, /* 11907 */ + IC_VEX_L_XD, /* 11908 */ + IC_VEX_L_XD, /* 11909 */ + IC_VEX_L_XD, /* 11910 */ + IC_VEX_L_XD, /* 11911 */ + IC_VEX_L_W, /* 11912 */ + IC_VEX_L_W, /* 11913 */ + IC_VEX_L_W_XS, /* 11914 */ + IC_VEX_L_W_XS, /* 11915 */ + IC_VEX_L_W_XD, /* 11916 */ + IC_VEX_L_W_XD, /* 11917 */ + IC_VEX_L_W_XD, /* 11918 */ + IC_VEX_L_W_XD, /* 11919 */ + IC_VEX_L_OPSIZE, /* 11920 */ + IC_VEX_L_OPSIZE, /* 11921 */ + IC_VEX_L_OPSIZE, /* 11922 */ + IC_VEX_L_OPSIZE, /* 11923 */ + IC_VEX_L_OPSIZE, /* 11924 */ + IC_VEX_L_OPSIZE, /* 11925 */ + IC_VEX_L_OPSIZE, /* 11926 */ + IC_VEX_L_OPSIZE, /* 11927 */ + IC_VEX_L_W_OPSIZE, /* 11928 */ + IC_VEX_L_W_OPSIZE, /* 11929 */ + IC_VEX_L_W_OPSIZE, /* 11930 */ + IC_VEX_L_W_OPSIZE, /* 11931 */ + IC_VEX_L_W_OPSIZE, /* 11932 */ + IC_VEX_L_W_OPSIZE, /* 11933 */ + IC_VEX_L_W_OPSIZE, /* 11934 */ + IC_VEX_L_W_OPSIZE, /* 11935 */ + IC_VEX_L, /* 11936 */ + IC_VEX_L, /* 11937 */ + IC_VEX_L_XS, /* 11938 */ + IC_VEX_L_XS, /* 11939 */ + IC_VEX_L_XD, /* 11940 */ + IC_VEX_L_XD, /* 11941 */ + IC_VEX_L_XD, /* 11942 */ + IC_VEX_L_XD, /* 11943 */ + IC_VEX_L_W, /* 11944 */ + IC_VEX_L_W, /* 11945 */ + IC_VEX_L_W_XS, /* 11946 */ + IC_VEX_L_W_XS, /* 11947 */ + IC_VEX_L_W_XD, /* 11948 */ + IC_VEX_L_W_XD, /* 11949 */ + IC_VEX_L_W_XD, /* 11950 */ + IC_VEX_L_W_XD, /* 11951 */ + IC_VEX_L_OPSIZE, /* 11952 */ + IC_VEX_L_OPSIZE, /* 11953 */ + IC_VEX_L_OPSIZE, /* 11954 */ + IC_VEX_L_OPSIZE, /* 11955 */ + IC_VEX_L_OPSIZE, /* 11956 */ + IC_VEX_L_OPSIZE, /* 11957 */ + IC_VEX_L_OPSIZE, /* 11958 */ + IC_VEX_L_OPSIZE, /* 11959 */ + IC_VEX_L_W_OPSIZE, /* 11960 */ + IC_VEX_L_W_OPSIZE, /* 11961 */ + IC_VEX_L_W_OPSIZE, /* 11962 */ + IC_VEX_L_W_OPSIZE, /* 11963 */ + IC_VEX_L_W_OPSIZE, /* 11964 */ + IC_VEX_L_W_OPSIZE, /* 11965 */ + IC_VEX_L_W_OPSIZE, /* 11966 */ + IC_VEX_L_W_OPSIZE, /* 11967 */ + IC_VEX_L, /* 11968 */ + IC_VEX_L, /* 11969 */ + IC_VEX_L_XS, /* 11970 */ + IC_VEX_L_XS, /* 11971 */ + IC_VEX_L_XD, /* 11972 */ + IC_VEX_L_XD, /* 11973 */ + IC_VEX_L_XD, /* 11974 */ + IC_VEX_L_XD, /* 11975 */ + IC_VEX_L_W, /* 11976 */ + IC_VEX_L_W, /* 11977 */ + IC_VEX_L_W_XS, /* 11978 */ + IC_VEX_L_W_XS, /* 11979 */ + IC_VEX_L_W_XD, /* 11980 */ + IC_VEX_L_W_XD, /* 11981 */ + IC_VEX_L_W_XD, /* 11982 */ + IC_VEX_L_W_XD, /* 11983 */ + IC_VEX_L_OPSIZE, /* 11984 */ + IC_VEX_L_OPSIZE, /* 11985 */ + IC_VEX_L_OPSIZE, /* 11986 */ + IC_VEX_L_OPSIZE, /* 11987 */ + IC_VEX_L_OPSIZE, /* 11988 */ + IC_VEX_L_OPSIZE, /* 11989 */ + IC_VEX_L_OPSIZE, /* 11990 */ + IC_VEX_L_OPSIZE, /* 11991 */ + IC_VEX_L_W_OPSIZE, /* 11992 */ + IC_VEX_L_W_OPSIZE, /* 11993 */ + IC_VEX_L_W_OPSIZE, /* 11994 */ + IC_VEX_L_W_OPSIZE, /* 11995 */ + IC_VEX_L_W_OPSIZE, /* 11996 */ + IC_VEX_L_W_OPSIZE, /* 11997 */ + IC_VEX_L_W_OPSIZE, /* 11998 */ + IC_VEX_L_W_OPSIZE, /* 11999 */ + IC_VEX_L, /* 12000 */ + IC_VEX_L, /* 12001 */ + IC_VEX_L_XS, /* 12002 */ + IC_VEX_L_XS, /* 12003 */ + IC_VEX_L_XD, /* 12004 */ + IC_VEX_L_XD, /* 12005 */ + IC_VEX_L_XD, /* 12006 */ + IC_VEX_L_XD, /* 12007 */ + IC_VEX_L_W, /* 12008 */ + IC_VEX_L_W, /* 12009 */ + IC_VEX_L_W_XS, /* 12010 */ + IC_VEX_L_W_XS, /* 12011 */ + IC_VEX_L_W_XD, /* 12012 */ + IC_VEX_L_W_XD, /* 12013 */ + IC_VEX_L_W_XD, /* 12014 */ + IC_VEX_L_W_XD, /* 12015 */ + IC_VEX_L_OPSIZE, /* 12016 */ + IC_VEX_L_OPSIZE, /* 12017 */ + IC_VEX_L_OPSIZE, /* 12018 */ + IC_VEX_L_OPSIZE, /* 12019 */ + IC_VEX_L_OPSIZE, /* 12020 */ + IC_VEX_L_OPSIZE, /* 12021 */ + IC_VEX_L_OPSIZE, /* 12022 */ + IC_VEX_L_OPSIZE, /* 12023 */ + IC_VEX_L_W_OPSIZE, /* 12024 */ + IC_VEX_L_W_OPSIZE, /* 12025 */ + IC_VEX_L_W_OPSIZE, /* 12026 */ + IC_VEX_L_W_OPSIZE, /* 12027 */ + IC_VEX_L_W_OPSIZE, /* 12028 */ + IC_VEX_L_W_OPSIZE, /* 12029 */ + IC_VEX_L_W_OPSIZE, /* 12030 */ + IC_VEX_L_W_OPSIZE, /* 12031 */ + IC_EVEX_L2_K_B, /* 12032 */ + IC_EVEX_L2_K_B, /* 12033 */ + IC_EVEX_L2_XS_K_B, /* 12034 */ + IC_EVEX_L2_XS_K_B, /* 12035 */ + IC_EVEX_L2_XD_K_B, /* 12036 */ + IC_EVEX_L2_XD_K_B, /* 12037 */ + IC_EVEX_L2_XD_K_B, /* 12038 */ + IC_EVEX_L2_XD_K_B, /* 12039 */ + IC_EVEX_L2_W_K_B, /* 12040 */ + IC_EVEX_L2_W_K_B, /* 12041 */ + IC_EVEX_L2_W_XS_K_B, /* 12042 */ + IC_EVEX_L2_W_XS_K_B, /* 12043 */ + IC_EVEX_L2_W_XD_K_B, /* 12044 */ + IC_EVEX_L2_W_XD_K_B, /* 12045 */ + IC_EVEX_L2_W_XD_K_B, /* 12046 */ + IC_EVEX_L2_W_XD_K_B, /* 12047 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12048 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12049 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12050 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12051 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12052 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12053 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12054 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12055 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12056 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12057 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12058 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12059 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12060 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12061 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12062 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12063 */ + IC_EVEX_L2_K_B, /* 12064 */ + IC_EVEX_L2_K_B, /* 12065 */ + IC_EVEX_L2_XS_K_B, /* 12066 */ + IC_EVEX_L2_XS_K_B, /* 12067 */ + IC_EVEX_L2_XD_K_B, /* 12068 */ + IC_EVEX_L2_XD_K_B, /* 12069 */ + IC_EVEX_L2_XD_K_B, /* 12070 */ + IC_EVEX_L2_XD_K_B, /* 12071 */ + IC_EVEX_L2_W_K_B, /* 12072 */ + IC_EVEX_L2_W_K_B, /* 12073 */ + IC_EVEX_L2_W_XS_K_B, /* 12074 */ + IC_EVEX_L2_W_XS_K_B, /* 12075 */ + IC_EVEX_L2_W_XD_K_B, /* 12076 */ + IC_EVEX_L2_W_XD_K_B, /* 12077 */ + IC_EVEX_L2_W_XD_K_B, /* 12078 */ + IC_EVEX_L2_W_XD_K_B, /* 12079 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12080 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12081 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12082 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12083 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12084 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12085 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12086 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12087 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12088 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12089 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12090 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12091 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12092 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12093 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12094 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12095 */ + IC_EVEX_L2_K_B, /* 12096 */ + IC_EVEX_L2_K_B, /* 12097 */ + IC_EVEX_L2_XS_K_B, /* 12098 */ + IC_EVEX_L2_XS_K_B, /* 12099 */ + IC_EVEX_L2_XD_K_B, /* 12100 */ + IC_EVEX_L2_XD_K_B, /* 12101 */ + IC_EVEX_L2_XD_K_B, /* 12102 */ + IC_EVEX_L2_XD_K_B, /* 12103 */ + IC_EVEX_L2_W_K_B, /* 12104 */ + IC_EVEX_L2_W_K_B, /* 12105 */ + IC_EVEX_L2_W_XS_K_B, /* 12106 */ + IC_EVEX_L2_W_XS_K_B, /* 12107 */ + IC_EVEX_L2_W_XD_K_B, /* 12108 */ + IC_EVEX_L2_W_XD_K_B, /* 12109 */ + IC_EVEX_L2_W_XD_K_B, /* 12110 */ + IC_EVEX_L2_W_XD_K_B, /* 12111 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12112 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12113 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12114 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12115 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12116 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12117 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12118 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12119 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12120 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12121 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12122 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12123 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12124 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12125 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12126 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12127 */ + IC_EVEX_L2_K_B, /* 12128 */ + IC_EVEX_L2_K_B, /* 12129 */ + IC_EVEX_L2_XS_K_B, /* 12130 */ + IC_EVEX_L2_XS_K_B, /* 12131 */ + IC_EVEX_L2_XD_K_B, /* 12132 */ + IC_EVEX_L2_XD_K_B, /* 12133 */ + IC_EVEX_L2_XD_K_B, /* 12134 */ + IC_EVEX_L2_XD_K_B, /* 12135 */ + IC_EVEX_L2_W_K_B, /* 12136 */ + IC_EVEX_L2_W_K_B, /* 12137 */ + IC_EVEX_L2_W_XS_K_B, /* 12138 */ + IC_EVEX_L2_W_XS_K_B, /* 12139 */ + IC_EVEX_L2_W_XD_K_B, /* 12140 */ + IC_EVEX_L2_W_XD_K_B, /* 12141 */ + IC_EVEX_L2_W_XD_K_B, /* 12142 */ + IC_EVEX_L2_W_XD_K_B, /* 12143 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12144 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12145 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12146 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12147 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12148 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12149 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12150 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12151 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12152 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12153 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12154 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12155 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12156 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12157 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12158 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12159 */ + IC_EVEX_L2_K_B, /* 12160 */ + IC_EVEX_L2_K_B, /* 12161 */ + IC_EVEX_L2_XS_K_B, /* 12162 */ + IC_EVEX_L2_XS_K_B, /* 12163 */ + IC_EVEX_L2_XD_K_B, /* 12164 */ + IC_EVEX_L2_XD_K_B, /* 12165 */ + IC_EVEX_L2_XD_K_B, /* 12166 */ + IC_EVEX_L2_XD_K_B, /* 12167 */ + IC_EVEX_L2_W_K_B, /* 12168 */ + IC_EVEX_L2_W_K_B, /* 12169 */ + IC_EVEX_L2_W_XS_K_B, /* 12170 */ + IC_EVEX_L2_W_XS_K_B, /* 12171 */ + IC_EVEX_L2_W_XD_K_B, /* 12172 */ + IC_EVEX_L2_W_XD_K_B, /* 12173 */ + IC_EVEX_L2_W_XD_K_B, /* 12174 */ + IC_EVEX_L2_W_XD_K_B, /* 12175 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12176 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12177 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12178 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12179 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12180 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12181 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12182 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12183 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12184 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12185 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12186 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12187 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12188 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12189 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12190 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12191 */ + IC_EVEX_L2_K_B, /* 12192 */ + IC_EVEX_L2_K_B, /* 12193 */ + IC_EVEX_L2_XS_K_B, /* 12194 */ + IC_EVEX_L2_XS_K_B, /* 12195 */ + IC_EVEX_L2_XD_K_B, /* 12196 */ + IC_EVEX_L2_XD_K_B, /* 12197 */ + IC_EVEX_L2_XD_K_B, /* 12198 */ + IC_EVEX_L2_XD_K_B, /* 12199 */ + IC_EVEX_L2_W_K_B, /* 12200 */ + IC_EVEX_L2_W_K_B, /* 12201 */ + IC_EVEX_L2_W_XS_K_B, /* 12202 */ + IC_EVEX_L2_W_XS_K_B, /* 12203 */ + IC_EVEX_L2_W_XD_K_B, /* 12204 */ + IC_EVEX_L2_W_XD_K_B, /* 12205 */ + IC_EVEX_L2_W_XD_K_B, /* 12206 */ + IC_EVEX_L2_W_XD_K_B, /* 12207 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12208 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12209 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12210 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12211 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12212 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12213 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12214 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12215 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12216 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12217 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12218 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12219 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12220 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12221 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12222 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12223 */ + IC_EVEX_L2_K_B, /* 12224 */ + IC_EVEX_L2_K_B, /* 12225 */ + IC_EVEX_L2_XS_K_B, /* 12226 */ + IC_EVEX_L2_XS_K_B, /* 12227 */ + IC_EVEX_L2_XD_K_B, /* 12228 */ + IC_EVEX_L2_XD_K_B, /* 12229 */ + IC_EVEX_L2_XD_K_B, /* 12230 */ + IC_EVEX_L2_XD_K_B, /* 12231 */ + IC_EVEX_L2_W_K_B, /* 12232 */ + IC_EVEX_L2_W_K_B, /* 12233 */ + IC_EVEX_L2_W_XS_K_B, /* 12234 */ + IC_EVEX_L2_W_XS_K_B, /* 12235 */ + IC_EVEX_L2_W_XD_K_B, /* 12236 */ + IC_EVEX_L2_W_XD_K_B, /* 12237 */ + IC_EVEX_L2_W_XD_K_B, /* 12238 */ + IC_EVEX_L2_W_XD_K_B, /* 12239 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12240 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12241 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12242 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12243 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12244 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12245 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12246 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12247 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12248 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12249 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12250 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12251 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12252 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12253 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12254 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12255 */ + IC_EVEX_L2_K_B, /* 12256 */ + IC_EVEX_L2_K_B, /* 12257 */ + IC_EVEX_L2_XS_K_B, /* 12258 */ + IC_EVEX_L2_XS_K_B, /* 12259 */ + IC_EVEX_L2_XD_K_B, /* 12260 */ + IC_EVEX_L2_XD_K_B, /* 12261 */ + IC_EVEX_L2_XD_K_B, /* 12262 */ + IC_EVEX_L2_XD_K_B, /* 12263 */ + IC_EVEX_L2_W_K_B, /* 12264 */ + IC_EVEX_L2_W_K_B, /* 12265 */ + IC_EVEX_L2_W_XS_K_B, /* 12266 */ + IC_EVEX_L2_W_XS_K_B, /* 12267 */ + IC_EVEX_L2_W_XD_K_B, /* 12268 */ + IC_EVEX_L2_W_XD_K_B, /* 12269 */ + IC_EVEX_L2_W_XD_K_B, /* 12270 */ + IC_EVEX_L2_W_XD_K_B, /* 12271 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12272 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12273 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12274 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12275 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12276 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12277 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12278 */ + IC_EVEX_L2_OPSIZE_K_B, /* 12279 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12280 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12281 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12282 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12283 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12284 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12285 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12286 */ + IC_EVEX_L2_W_OPSIZE_K_B, /* 12287 */ + IC, /* 12288 */ + IC_64BIT, /* 12289 */ + IC_XS, /* 12290 */ + IC_64BIT_XS, /* 12291 */ + IC_XD, /* 12292 */ + IC_64BIT_XD, /* 12293 */ + IC_XS, /* 12294 */ + IC_64BIT_XS, /* 12295 */ + IC, /* 12296 */ + IC_64BIT_REXW, /* 12297 */ + IC_XS, /* 12298 */ + IC_64BIT_REXW_XS, /* 12299 */ + IC_XD, /* 12300 */ + IC_64BIT_REXW_XD, /* 12301 */ + IC_XS, /* 12302 */ + IC_64BIT_REXW_XS, /* 12303 */ + IC_OPSIZE, /* 12304 */ + IC_64BIT_OPSIZE, /* 12305 */ + IC_XS_OPSIZE, /* 12306 */ + IC_64BIT_XS_OPSIZE, /* 12307 */ + IC_XD_OPSIZE, /* 12308 */ + IC_64BIT_XD_OPSIZE, /* 12309 */ + IC_XS_OPSIZE, /* 12310 */ + IC_64BIT_XD_OPSIZE, /* 12311 */ + IC_OPSIZE, /* 12312 */ + IC_64BIT_REXW_OPSIZE, /* 12313 */ + IC_XS_OPSIZE, /* 12314 */ + IC_64BIT_REXW_XS, /* 12315 */ + IC_XD_OPSIZE, /* 12316 */ + IC_64BIT_REXW_XD, /* 12317 */ + IC_XS_OPSIZE, /* 12318 */ + IC_64BIT_REXW_XS, /* 12319 */ + IC_ADSIZE, /* 12320 */ + IC_64BIT_ADSIZE, /* 12321 */ + IC_XS_ADSIZE, /* 12322 */ + IC_64BIT_XS_ADSIZE, /* 12323 */ + IC_XD_ADSIZE, /* 12324 */ + IC_64BIT_XD_ADSIZE, /* 12325 */ + IC_XS_ADSIZE, /* 12326 */ + IC_64BIT_XD_ADSIZE, /* 12327 */ + IC_ADSIZE, /* 12328 */ + IC_64BIT_REXW_ADSIZE, /* 12329 */ + IC_XS_ADSIZE, /* 12330 */ + IC_64BIT_REXW_XS, /* 12331 */ + IC_XD_ADSIZE, /* 12332 */ + IC_64BIT_REXW_XD, /* 12333 */ + IC_XS_ADSIZE, /* 12334 */ + IC_64BIT_REXW_XS, /* 12335 */ + IC_OPSIZE_ADSIZE, /* 12336 */ + IC_64BIT_OPSIZE_ADSIZE, /* 12337 */ + IC_XS_OPSIZE, /* 12338 */ + IC_64BIT_XS_OPSIZE, /* 12339 */ + IC_XD_OPSIZE, /* 12340 */ + IC_64BIT_XD_OPSIZE, /* 12341 */ + IC_XS_OPSIZE, /* 12342 */ + IC_64BIT_XD_OPSIZE, /* 12343 */ + IC_OPSIZE_ADSIZE, /* 12344 */ + IC_64BIT_REXW_OPSIZE, /* 12345 */ + IC_XS_OPSIZE, /* 12346 */ + IC_64BIT_REXW_XS, /* 12347 */ + IC_XD_OPSIZE, /* 12348 */ + IC_64BIT_REXW_XD, /* 12349 */ + IC_XS_OPSIZE, /* 12350 */ + IC_64BIT_REXW_XS, /* 12351 */ + IC_VEX, /* 12352 */ + IC_VEX, /* 12353 */ + IC_VEX_XS, /* 12354 */ + IC_VEX_XS, /* 12355 */ + IC_VEX_XD, /* 12356 */ + IC_VEX_XD, /* 12357 */ + IC_VEX_XD, /* 12358 */ + IC_VEX_XD, /* 12359 */ + IC_VEX_W, /* 12360 */ + IC_VEX_W, /* 12361 */ + IC_VEX_W_XS, /* 12362 */ + IC_VEX_W_XS, /* 12363 */ + IC_VEX_W_XD, /* 12364 */ + IC_VEX_W_XD, /* 12365 */ + IC_VEX_W_XD, /* 12366 */ + IC_VEX_W_XD, /* 12367 */ + IC_VEX_OPSIZE, /* 12368 */ + IC_VEX_OPSIZE, /* 12369 */ + IC_VEX_OPSIZE, /* 12370 */ + IC_VEX_OPSIZE, /* 12371 */ + IC_VEX_OPSIZE, /* 12372 */ + IC_VEX_OPSIZE, /* 12373 */ + IC_VEX_OPSIZE, /* 12374 */ + IC_VEX_OPSIZE, /* 12375 */ + IC_VEX_W_OPSIZE, /* 12376 */ + IC_VEX_W_OPSIZE, /* 12377 */ + IC_VEX_W_OPSIZE, /* 12378 */ + IC_VEX_W_OPSIZE, /* 12379 */ + IC_VEX_W_OPSIZE, /* 12380 */ + IC_VEX_W_OPSIZE, /* 12381 */ + IC_VEX_W_OPSIZE, /* 12382 */ + IC_VEX_W_OPSIZE, /* 12383 */ + IC_VEX, /* 12384 */ + IC_VEX, /* 12385 */ + IC_VEX_XS, /* 12386 */ + IC_VEX_XS, /* 12387 */ + IC_VEX_XD, /* 12388 */ + IC_VEX_XD, /* 12389 */ + IC_VEX_XD, /* 12390 */ + IC_VEX_XD, /* 12391 */ + IC_VEX_W, /* 12392 */ + IC_VEX_W, /* 12393 */ + IC_VEX_W_XS, /* 12394 */ + IC_VEX_W_XS, /* 12395 */ + IC_VEX_W_XD, /* 12396 */ + IC_VEX_W_XD, /* 12397 */ + IC_VEX_W_XD, /* 12398 */ + IC_VEX_W_XD, /* 12399 */ + IC_VEX_OPSIZE, /* 12400 */ + IC_VEX_OPSIZE, /* 12401 */ + IC_VEX_OPSIZE, /* 12402 */ + IC_VEX_OPSIZE, /* 12403 */ + IC_VEX_OPSIZE, /* 12404 */ + IC_VEX_OPSIZE, /* 12405 */ + IC_VEX_OPSIZE, /* 12406 */ + IC_VEX_OPSIZE, /* 12407 */ + IC_VEX_W_OPSIZE, /* 12408 */ + IC_VEX_W_OPSIZE, /* 12409 */ + IC_VEX_W_OPSIZE, /* 12410 */ + IC_VEX_W_OPSIZE, /* 12411 */ + IC_VEX_W_OPSIZE, /* 12412 */ + IC_VEX_W_OPSIZE, /* 12413 */ + IC_VEX_W_OPSIZE, /* 12414 */ + IC_VEX_W_OPSIZE, /* 12415 */ + IC_VEX_L, /* 12416 */ + IC_VEX_L, /* 12417 */ + IC_VEX_L_XS, /* 12418 */ + IC_VEX_L_XS, /* 12419 */ + IC_VEX_L_XD, /* 12420 */ + IC_VEX_L_XD, /* 12421 */ + IC_VEX_L_XD, /* 12422 */ + IC_VEX_L_XD, /* 12423 */ + IC_VEX_L_W, /* 12424 */ + IC_VEX_L_W, /* 12425 */ + IC_VEX_L_W_XS, /* 12426 */ + IC_VEX_L_W_XS, /* 12427 */ + IC_VEX_L_W_XD, /* 12428 */ + IC_VEX_L_W_XD, /* 12429 */ + IC_VEX_L_W_XD, /* 12430 */ + IC_VEX_L_W_XD, /* 12431 */ + IC_VEX_L_OPSIZE, /* 12432 */ + IC_VEX_L_OPSIZE, /* 12433 */ + IC_VEX_L_OPSIZE, /* 12434 */ + IC_VEX_L_OPSIZE, /* 12435 */ + IC_VEX_L_OPSIZE, /* 12436 */ + IC_VEX_L_OPSIZE, /* 12437 */ + IC_VEX_L_OPSIZE, /* 12438 */ + IC_VEX_L_OPSIZE, /* 12439 */ + IC_VEX_L_W_OPSIZE, /* 12440 */ + IC_VEX_L_W_OPSIZE, /* 12441 */ + IC_VEX_L_W_OPSIZE, /* 12442 */ + IC_VEX_L_W_OPSIZE, /* 12443 */ + IC_VEX_L_W_OPSIZE, /* 12444 */ + IC_VEX_L_W_OPSIZE, /* 12445 */ + IC_VEX_L_W_OPSIZE, /* 12446 */ + IC_VEX_L_W_OPSIZE, /* 12447 */ + IC_VEX_L, /* 12448 */ + IC_VEX_L, /* 12449 */ + IC_VEX_L_XS, /* 12450 */ + IC_VEX_L_XS, /* 12451 */ + IC_VEX_L_XD, /* 12452 */ + IC_VEX_L_XD, /* 12453 */ + IC_VEX_L_XD, /* 12454 */ + IC_VEX_L_XD, /* 12455 */ + IC_VEX_L_W, /* 12456 */ + IC_VEX_L_W, /* 12457 */ + IC_VEX_L_W_XS, /* 12458 */ + IC_VEX_L_W_XS, /* 12459 */ + IC_VEX_L_W_XD, /* 12460 */ + IC_VEX_L_W_XD, /* 12461 */ + IC_VEX_L_W_XD, /* 12462 */ + IC_VEX_L_W_XD, /* 12463 */ + IC_VEX_L_OPSIZE, /* 12464 */ + IC_VEX_L_OPSIZE, /* 12465 */ + IC_VEX_L_OPSIZE, /* 12466 */ + IC_VEX_L_OPSIZE, /* 12467 */ + IC_VEX_L_OPSIZE, /* 12468 */ + IC_VEX_L_OPSIZE, /* 12469 */ + IC_VEX_L_OPSIZE, /* 12470 */ + IC_VEX_L_OPSIZE, /* 12471 */ + IC_VEX_L_W_OPSIZE, /* 12472 */ + IC_VEX_L_W_OPSIZE, /* 12473 */ + IC_VEX_L_W_OPSIZE, /* 12474 */ + IC_VEX_L_W_OPSIZE, /* 12475 */ + IC_VEX_L_W_OPSIZE, /* 12476 */ + IC_VEX_L_W_OPSIZE, /* 12477 */ + IC_VEX_L_W_OPSIZE, /* 12478 */ + IC_VEX_L_W_OPSIZE, /* 12479 */ + IC_VEX_L, /* 12480 */ + IC_VEX_L, /* 12481 */ + IC_VEX_L_XS, /* 12482 */ + IC_VEX_L_XS, /* 12483 */ + IC_VEX_L_XD, /* 12484 */ + IC_VEX_L_XD, /* 12485 */ + IC_VEX_L_XD, /* 12486 */ + IC_VEX_L_XD, /* 12487 */ + IC_VEX_L_W, /* 12488 */ + IC_VEX_L_W, /* 12489 */ + IC_VEX_L_W_XS, /* 12490 */ + IC_VEX_L_W_XS, /* 12491 */ + IC_VEX_L_W_XD, /* 12492 */ + IC_VEX_L_W_XD, /* 12493 */ + IC_VEX_L_W_XD, /* 12494 */ + IC_VEX_L_W_XD, /* 12495 */ + IC_VEX_L_OPSIZE, /* 12496 */ + IC_VEX_L_OPSIZE, /* 12497 */ + IC_VEX_L_OPSIZE, /* 12498 */ + IC_VEX_L_OPSIZE, /* 12499 */ + IC_VEX_L_OPSIZE, /* 12500 */ + IC_VEX_L_OPSIZE, /* 12501 */ + IC_VEX_L_OPSIZE, /* 12502 */ + IC_VEX_L_OPSIZE, /* 12503 */ + IC_VEX_L_W_OPSIZE, /* 12504 */ + IC_VEX_L_W_OPSIZE, /* 12505 */ + IC_VEX_L_W_OPSIZE, /* 12506 */ + IC_VEX_L_W_OPSIZE, /* 12507 */ + IC_VEX_L_W_OPSIZE, /* 12508 */ + IC_VEX_L_W_OPSIZE, /* 12509 */ + IC_VEX_L_W_OPSIZE, /* 12510 */ + IC_VEX_L_W_OPSIZE, /* 12511 */ + IC_VEX_L, /* 12512 */ + IC_VEX_L, /* 12513 */ + IC_VEX_L_XS, /* 12514 */ + IC_VEX_L_XS, /* 12515 */ + IC_VEX_L_XD, /* 12516 */ + IC_VEX_L_XD, /* 12517 */ + IC_VEX_L_XD, /* 12518 */ + IC_VEX_L_XD, /* 12519 */ + IC_VEX_L_W, /* 12520 */ + IC_VEX_L_W, /* 12521 */ + IC_VEX_L_W_XS, /* 12522 */ + IC_VEX_L_W_XS, /* 12523 */ + IC_VEX_L_W_XD, /* 12524 */ + IC_VEX_L_W_XD, /* 12525 */ + IC_VEX_L_W_XD, /* 12526 */ + IC_VEX_L_W_XD, /* 12527 */ + IC_VEX_L_OPSIZE, /* 12528 */ + IC_VEX_L_OPSIZE, /* 12529 */ + IC_VEX_L_OPSIZE, /* 12530 */ + IC_VEX_L_OPSIZE, /* 12531 */ + IC_VEX_L_OPSIZE, /* 12532 */ + IC_VEX_L_OPSIZE, /* 12533 */ + IC_VEX_L_OPSIZE, /* 12534 */ + IC_VEX_L_OPSIZE, /* 12535 */ + IC_VEX_L_W_OPSIZE, /* 12536 */ + IC_VEX_L_W_OPSIZE, /* 12537 */ + IC_VEX_L_W_OPSIZE, /* 12538 */ + IC_VEX_L_W_OPSIZE, /* 12539 */ + IC_VEX_L_W_OPSIZE, /* 12540 */ + IC_VEX_L_W_OPSIZE, /* 12541 */ + IC_VEX_L_W_OPSIZE, /* 12542 */ + IC_VEX_L_W_OPSIZE, /* 12543 */ + IC_EVEX_KZ_B, /* 12544 */ + IC_EVEX_KZ_B, /* 12545 */ + IC_EVEX_XS_KZ_B, /* 12546 */ + IC_EVEX_XS_KZ_B, /* 12547 */ + IC_EVEX_XD_KZ_B, /* 12548 */ + IC_EVEX_XD_KZ_B, /* 12549 */ + IC_EVEX_XD_KZ_B, /* 12550 */ + IC_EVEX_XD_KZ_B, /* 12551 */ + IC_EVEX_W_KZ_B, /* 12552 */ + IC_EVEX_W_KZ_B, /* 12553 */ + IC_EVEX_W_XS_KZ_B, /* 12554 */ + IC_EVEX_W_XS_KZ_B, /* 12555 */ + IC_EVEX_W_XD_KZ_B, /* 12556 */ + IC_EVEX_W_XD_KZ_B, /* 12557 */ + IC_EVEX_W_XD_KZ_B, /* 12558 */ + IC_EVEX_W_XD_KZ_B, /* 12559 */ + IC_EVEX_OPSIZE_KZ_B, /* 12560 */ + IC_EVEX_OPSIZE_KZ_B, /* 12561 */ + IC_EVEX_OPSIZE_KZ_B, /* 12562 */ + IC_EVEX_OPSIZE_KZ_B, /* 12563 */ + IC_EVEX_OPSIZE_KZ_B, /* 12564 */ + IC_EVEX_OPSIZE_KZ_B, /* 12565 */ + IC_EVEX_OPSIZE_KZ_B, /* 12566 */ + IC_EVEX_OPSIZE_KZ_B, /* 12567 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12568 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12569 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12570 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12571 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12572 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12573 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12574 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12575 */ + IC_EVEX_KZ_B, /* 12576 */ + IC_EVEX_KZ_B, /* 12577 */ + IC_EVEX_XS_KZ_B, /* 12578 */ + IC_EVEX_XS_KZ_B, /* 12579 */ + IC_EVEX_XD_KZ_B, /* 12580 */ + IC_EVEX_XD_KZ_B, /* 12581 */ + IC_EVEX_XD_KZ_B, /* 12582 */ + IC_EVEX_XD_KZ_B, /* 12583 */ + IC_EVEX_W_KZ_B, /* 12584 */ + IC_EVEX_W_KZ_B, /* 12585 */ + IC_EVEX_W_XS_KZ_B, /* 12586 */ + IC_EVEX_W_XS_KZ_B, /* 12587 */ + IC_EVEX_W_XD_KZ_B, /* 12588 */ + IC_EVEX_W_XD_KZ_B, /* 12589 */ + IC_EVEX_W_XD_KZ_B, /* 12590 */ + IC_EVEX_W_XD_KZ_B, /* 12591 */ + IC_EVEX_OPSIZE_KZ_B, /* 12592 */ + IC_EVEX_OPSIZE_KZ_B, /* 12593 */ + IC_EVEX_OPSIZE_KZ_B, /* 12594 */ + IC_EVEX_OPSIZE_KZ_B, /* 12595 */ + IC_EVEX_OPSIZE_KZ_B, /* 12596 */ + IC_EVEX_OPSIZE_KZ_B, /* 12597 */ + IC_EVEX_OPSIZE_KZ_B, /* 12598 */ + IC_EVEX_OPSIZE_KZ_B, /* 12599 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12600 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12601 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12602 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12603 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12604 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12605 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12606 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12607 */ + IC_EVEX_KZ_B, /* 12608 */ + IC_EVEX_KZ_B, /* 12609 */ + IC_EVEX_XS_KZ_B, /* 12610 */ + IC_EVEX_XS_KZ_B, /* 12611 */ + IC_EVEX_XD_KZ_B, /* 12612 */ + IC_EVEX_XD_KZ_B, /* 12613 */ + IC_EVEX_XD_KZ_B, /* 12614 */ + IC_EVEX_XD_KZ_B, /* 12615 */ + IC_EVEX_W_KZ_B, /* 12616 */ + IC_EVEX_W_KZ_B, /* 12617 */ + IC_EVEX_W_XS_KZ_B, /* 12618 */ + IC_EVEX_W_XS_KZ_B, /* 12619 */ + IC_EVEX_W_XD_KZ_B, /* 12620 */ + IC_EVEX_W_XD_KZ_B, /* 12621 */ + IC_EVEX_W_XD_KZ_B, /* 12622 */ + IC_EVEX_W_XD_KZ_B, /* 12623 */ + IC_EVEX_OPSIZE_KZ_B, /* 12624 */ + IC_EVEX_OPSIZE_KZ_B, /* 12625 */ + IC_EVEX_OPSIZE_KZ_B, /* 12626 */ + IC_EVEX_OPSIZE_KZ_B, /* 12627 */ + IC_EVEX_OPSIZE_KZ_B, /* 12628 */ + IC_EVEX_OPSIZE_KZ_B, /* 12629 */ + IC_EVEX_OPSIZE_KZ_B, /* 12630 */ + IC_EVEX_OPSIZE_KZ_B, /* 12631 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12632 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12633 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12634 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12635 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12636 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12637 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12638 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12639 */ + IC_EVEX_KZ_B, /* 12640 */ + IC_EVEX_KZ_B, /* 12641 */ + IC_EVEX_XS_KZ_B, /* 12642 */ + IC_EVEX_XS_KZ_B, /* 12643 */ + IC_EVEX_XD_KZ_B, /* 12644 */ + IC_EVEX_XD_KZ_B, /* 12645 */ + IC_EVEX_XD_KZ_B, /* 12646 */ + IC_EVEX_XD_KZ_B, /* 12647 */ + IC_EVEX_W_KZ_B, /* 12648 */ + IC_EVEX_W_KZ_B, /* 12649 */ + IC_EVEX_W_XS_KZ_B, /* 12650 */ + IC_EVEX_W_XS_KZ_B, /* 12651 */ + IC_EVEX_W_XD_KZ_B, /* 12652 */ + IC_EVEX_W_XD_KZ_B, /* 12653 */ + IC_EVEX_W_XD_KZ_B, /* 12654 */ + IC_EVEX_W_XD_KZ_B, /* 12655 */ + IC_EVEX_OPSIZE_KZ_B, /* 12656 */ + IC_EVEX_OPSIZE_KZ_B, /* 12657 */ + IC_EVEX_OPSIZE_KZ_B, /* 12658 */ + IC_EVEX_OPSIZE_KZ_B, /* 12659 */ + IC_EVEX_OPSIZE_KZ_B, /* 12660 */ + IC_EVEX_OPSIZE_KZ_B, /* 12661 */ + IC_EVEX_OPSIZE_KZ_B, /* 12662 */ + IC_EVEX_OPSIZE_KZ_B, /* 12663 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12664 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12665 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12666 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12667 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12668 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12669 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12670 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12671 */ + IC_EVEX_KZ_B, /* 12672 */ + IC_EVEX_KZ_B, /* 12673 */ + IC_EVEX_XS_KZ_B, /* 12674 */ + IC_EVEX_XS_KZ_B, /* 12675 */ + IC_EVEX_XD_KZ_B, /* 12676 */ + IC_EVEX_XD_KZ_B, /* 12677 */ + IC_EVEX_XD_KZ_B, /* 12678 */ + IC_EVEX_XD_KZ_B, /* 12679 */ + IC_EVEX_W_KZ_B, /* 12680 */ + IC_EVEX_W_KZ_B, /* 12681 */ + IC_EVEX_W_XS_KZ_B, /* 12682 */ + IC_EVEX_W_XS_KZ_B, /* 12683 */ + IC_EVEX_W_XD_KZ_B, /* 12684 */ + IC_EVEX_W_XD_KZ_B, /* 12685 */ + IC_EVEX_W_XD_KZ_B, /* 12686 */ + IC_EVEX_W_XD_KZ_B, /* 12687 */ + IC_EVEX_OPSIZE_KZ_B, /* 12688 */ + IC_EVEX_OPSIZE_KZ_B, /* 12689 */ + IC_EVEX_OPSIZE_KZ_B, /* 12690 */ + IC_EVEX_OPSIZE_KZ_B, /* 12691 */ + IC_EVEX_OPSIZE_KZ_B, /* 12692 */ + IC_EVEX_OPSIZE_KZ_B, /* 12693 */ + IC_EVEX_OPSIZE_KZ_B, /* 12694 */ + IC_EVEX_OPSIZE_KZ_B, /* 12695 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12696 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12697 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12698 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12699 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12700 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12701 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12702 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12703 */ + IC_EVEX_KZ_B, /* 12704 */ + IC_EVEX_KZ_B, /* 12705 */ + IC_EVEX_XS_KZ_B, /* 12706 */ + IC_EVEX_XS_KZ_B, /* 12707 */ + IC_EVEX_XD_KZ_B, /* 12708 */ + IC_EVEX_XD_KZ_B, /* 12709 */ + IC_EVEX_XD_KZ_B, /* 12710 */ + IC_EVEX_XD_KZ_B, /* 12711 */ + IC_EVEX_W_KZ_B, /* 12712 */ + IC_EVEX_W_KZ_B, /* 12713 */ + IC_EVEX_W_XS_KZ_B, /* 12714 */ + IC_EVEX_W_XS_KZ_B, /* 12715 */ + IC_EVEX_W_XD_KZ_B, /* 12716 */ + IC_EVEX_W_XD_KZ_B, /* 12717 */ + IC_EVEX_W_XD_KZ_B, /* 12718 */ + IC_EVEX_W_XD_KZ_B, /* 12719 */ + IC_EVEX_OPSIZE_KZ_B, /* 12720 */ + IC_EVEX_OPSIZE_KZ_B, /* 12721 */ + IC_EVEX_OPSIZE_KZ_B, /* 12722 */ + IC_EVEX_OPSIZE_KZ_B, /* 12723 */ + IC_EVEX_OPSIZE_KZ_B, /* 12724 */ + IC_EVEX_OPSIZE_KZ_B, /* 12725 */ + IC_EVEX_OPSIZE_KZ_B, /* 12726 */ + IC_EVEX_OPSIZE_KZ_B, /* 12727 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12728 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12729 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12730 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12731 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12732 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12733 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12734 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12735 */ + IC_EVEX_KZ_B, /* 12736 */ + IC_EVEX_KZ_B, /* 12737 */ + IC_EVEX_XS_KZ_B, /* 12738 */ + IC_EVEX_XS_KZ_B, /* 12739 */ + IC_EVEX_XD_KZ_B, /* 12740 */ + IC_EVEX_XD_KZ_B, /* 12741 */ + IC_EVEX_XD_KZ_B, /* 12742 */ + IC_EVEX_XD_KZ_B, /* 12743 */ + IC_EVEX_W_KZ_B, /* 12744 */ + IC_EVEX_W_KZ_B, /* 12745 */ + IC_EVEX_W_XS_KZ_B, /* 12746 */ + IC_EVEX_W_XS_KZ_B, /* 12747 */ + IC_EVEX_W_XD_KZ_B, /* 12748 */ + IC_EVEX_W_XD_KZ_B, /* 12749 */ + IC_EVEX_W_XD_KZ_B, /* 12750 */ + IC_EVEX_W_XD_KZ_B, /* 12751 */ + IC_EVEX_OPSIZE_KZ_B, /* 12752 */ + IC_EVEX_OPSIZE_KZ_B, /* 12753 */ + IC_EVEX_OPSIZE_KZ_B, /* 12754 */ + IC_EVEX_OPSIZE_KZ_B, /* 12755 */ + IC_EVEX_OPSIZE_KZ_B, /* 12756 */ + IC_EVEX_OPSIZE_KZ_B, /* 12757 */ + IC_EVEX_OPSIZE_KZ_B, /* 12758 */ + IC_EVEX_OPSIZE_KZ_B, /* 12759 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12760 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12761 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12762 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12763 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12764 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12765 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12766 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12767 */ + IC_EVEX_KZ_B, /* 12768 */ + IC_EVEX_KZ_B, /* 12769 */ + IC_EVEX_XS_KZ_B, /* 12770 */ + IC_EVEX_XS_KZ_B, /* 12771 */ + IC_EVEX_XD_KZ_B, /* 12772 */ + IC_EVEX_XD_KZ_B, /* 12773 */ + IC_EVEX_XD_KZ_B, /* 12774 */ + IC_EVEX_XD_KZ_B, /* 12775 */ + IC_EVEX_W_KZ_B, /* 12776 */ + IC_EVEX_W_KZ_B, /* 12777 */ + IC_EVEX_W_XS_KZ_B, /* 12778 */ + IC_EVEX_W_XS_KZ_B, /* 12779 */ + IC_EVEX_W_XD_KZ_B, /* 12780 */ + IC_EVEX_W_XD_KZ_B, /* 12781 */ + IC_EVEX_W_XD_KZ_B, /* 12782 */ + IC_EVEX_W_XD_KZ_B, /* 12783 */ + IC_EVEX_OPSIZE_KZ_B, /* 12784 */ + IC_EVEX_OPSIZE_KZ_B, /* 12785 */ + IC_EVEX_OPSIZE_KZ_B, /* 12786 */ + IC_EVEX_OPSIZE_KZ_B, /* 12787 */ + IC_EVEX_OPSIZE_KZ_B, /* 12788 */ + IC_EVEX_OPSIZE_KZ_B, /* 12789 */ + IC_EVEX_OPSIZE_KZ_B, /* 12790 */ + IC_EVEX_OPSIZE_KZ_B, /* 12791 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12792 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12793 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12794 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12795 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12796 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12797 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12798 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 12799 */ + IC, /* 12800 */ + IC_64BIT, /* 12801 */ + IC_XS, /* 12802 */ + IC_64BIT_XS, /* 12803 */ + IC_XD, /* 12804 */ + IC_64BIT_XD, /* 12805 */ + IC_XS, /* 12806 */ + IC_64BIT_XS, /* 12807 */ + IC, /* 12808 */ + IC_64BIT_REXW, /* 12809 */ + IC_XS, /* 12810 */ + IC_64BIT_REXW_XS, /* 12811 */ + IC_XD, /* 12812 */ + IC_64BIT_REXW_XD, /* 12813 */ + IC_XS, /* 12814 */ + IC_64BIT_REXW_XS, /* 12815 */ + IC_OPSIZE, /* 12816 */ + IC_64BIT_OPSIZE, /* 12817 */ + IC_XS_OPSIZE, /* 12818 */ + IC_64BIT_XS_OPSIZE, /* 12819 */ + IC_XD_OPSIZE, /* 12820 */ + IC_64BIT_XD_OPSIZE, /* 12821 */ + IC_XS_OPSIZE, /* 12822 */ + IC_64BIT_XD_OPSIZE, /* 12823 */ + IC_OPSIZE, /* 12824 */ + IC_64BIT_REXW_OPSIZE, /* 12825 */ + IC_XS_OPSIZE, /* 12826 */ + IC_64BIT_REXW_XS, /* 12827 */ + IC_XD_OPSIZE, /* 12828 */ + IC_64BIT_REXW_XD, /* 12829 */ + IC_XS_OPSIZE, /* 12830 */ + IC_64BIT_REXW_XS, /* 12831 */ + IC_ADSIZE, /* 12832 */ + IC_64BIT_ADSIZE, /* 12833 */ + IC_XS_ADSIZE, /* 12834 */ + IC_64BIT_XS_ADSIZE, /* 12835 */ + IC_XD_ADSIZE, /* 12836 */ + IC_64BIT_XD_ADSIZE, /* 12837 */ + IC_XS_ADSIZE, /* 12838 */ + IC_64BIT_XD_ADSIZE, /* 12839 */ + IC_ADSIZE, /* 12840 */ + IC_64BIT_REXW_ADSIZE, /* 12841 */ + IC_XS_ADSIZE, /* 12842 */ + IC_64BIT_REXW_XS, /* 12843 */ + IC_XD_ADSIZE, /* 12844 */ + IC_64BIT_REXW_XD, /* 12845 */ + IC_XS_ADSIZE, /* 12846 */ + IC_64BIT_REXW_XS, /* 12847 */ + IC_OPSIZE_ADSIZE, /* 12848 */ + IC_64BIT_OPSIZE_ADSIZE, /* 12849 */ + IC_XS_OPSIZE, /* 12850 */ + IC_64BIT_XS_OPSIZE, /* 12851 */ + IC_XD_OPSIZE, /* 12852 */ + IC_64BIT_XD_OPSIZE, /* 12853 */ + IC_XS_OPSIZE, /* 12854 */ + IC_64BIT_XD_OPSIZE, /* 12855 */ + IC_OPSIZE_ADSIZE, /* 12856 */ + IC_64BIT_REXW_OPSIZE, /* 12857 */ + IC_XS_OPSIZE, /* 12858 */ + IC_64BIT_REXW_XS, /* 12859 */ + IC_XD_OPSIZE, /* 12860 */ + IC_64BIT_REXW_XD, /* 12861 */ + IC_XS_OPSIZE, /* 12862 */ + IC_64BIT_REXW_XS, /* 12863 */ + IC_VEX, /* 12864 */ + IC_VEX, /* 12865 */ + IC_VEX_XS, /* 12866 */ + IC_VEX_XS, /* 12867 */ + IC_VEX_XD, /* 12868 */ + IC_VEX_XD, /* 12869 */ + IC_VEX_XD, /* 12870 */ + IC_VEX_XD, /* 12871 */ + IC_VEX_W, /* 12872 */ + IC_VEX_W, /* 12873 */ + IC_VEX_W_XS, /* 12874 */ + IC_VEX_W_XS, /* 12875 */ + IC_VEX_W_XD, /* 12876 */ + IC_VEX_W_XD, /* 12877 */ + IC_VEX_W_XD, /* 12878 */ + IC_VEX_W_XD, /* 12879 */ + IC_VEX_OPSIZE, /* 12880 */ + IC_VEX_OPSIZE, /* 12881 */ + IC_VEX_OPSIZE, /* 12882 */ + IC_VEX_OPSIZE, /* 12883 */ + IC_VEX_OPSIZE, /* 12884 */ + IC_VEX_OPSIZE, /* 12885 */ + IC_VEX_OPSIZE, /* 12886 */ + IC_VEX_OPSIZE, /* 12887 */ + IC_VEX_W_OPSIZE, /* 12888 */ + IC_VEX_W_OPSIZE, /* 12889 */ + IC_VEX_W_OPSIZE, /* 12890 */ + IC_VEX_W_OPSIZE, /* 12891 */ + IC_VEX_W_OPSIZE, /* 12892 */ + IC_VEX_W_OPSIZE, /* 12893 */ + IC_VEX_W_OPSIZE, /* 12894 */ + IC_VEX_W_OPSIZE, /* 12895 */ + IC_VEX, /* 12896 */ + IC_VEX, /* 12897 */ + IC_VEX_XS, /* 12898 */ + IC_VEX_XS, /* 12899 */ + IC_VEX_XD, /* 12900 */ + IC_VEX_XD, /* 12901 */ + IC_VEX_XD, /* 12902 */ + IC_VEX_XD, /* 12903 */ + IC_VEX_W, /* 12904 */ + IC_VEX_W, /* 12905 */ + IC_VEX_W_XS, /* 12906 */ + IC_VEX_W_XS, /* 12907 */ + IC_VEX_W_XD, /* 12908 */ + IC_VEX_W_XD, /* 12909 */ + IC_VEX_W_XD, /* 12910 */ + IC_VEX_W_XD, /* 12911 */ + IC_VEX_OPSIZE, /* 12912 */ + IC_VEX_OPSIZE, /* 12913 */ + IC_VEX_OPSIZE, /* 12914 */ + IC_VEX_OPSIZE, /* 12915 */ + IC_VEX_OPSIZE, /* 12916 */ + IC_VEX_OPSIZE, /* 12917 */ + IC_VEX_OPSIZE, /* 12918 */ + IC_VEX_OPSIZE, /* 12919 */ + IC_VEX_W_OPSIZE, /* 12920 */ + IC_VEX_W_OPSIZE, /* 12921 */ + IC_VEX_W_OPSIZE, /* 12922 */ + IC_VEX_W_OPSIZE, /* 12923 */ + IC_VEX_W_OPSIZE, /* 12924 */ + IC_VEX_W_OPSIZE, /* 12925 */ + IC_VEX_W_OPSIZE, /* 12926 */ + IC_VEX_W_OPSIZE, /* 12927 */ + IC_VEX_L, /* 12928 */ + IC_VEX_L, /* 12929 */ + IC_VEX_L_XS, /* 12930 */ + IC_VEX_L_XS, /* 12931 */ + IC_VEX_L_XD, /* 12932 */ + IC_VEX_L_XD, /* 12933 */ + IC_VEX_L_XD, /* 12934 */ + IC_VEX_L_XD, /* 12935 */ + IC_VEX_L_W, /* 12936 */ + IC_VEX_L_W, /* 12937 */ + IC_VEX_L_W_XS, /* 12938 */ + IC_VEX_L_W_XS, /* 12939 */ + IC_VEX_L_W_XD, /* 12940 */ + IC_VEX_L_W_XD, /* 12941 */ + IC_VEX_L_W_XD, /* 12942 */ + IC_VEX_L_W_XD, /* 12943 */ + IC_VEX_L_OPSIZE, /* 12944 */ + IC_VEX_L_OPSIZE, /* 12945 */ + IC_VEX_L_OPSIZE, /* 12946 */ + IC_VEX_L_OPSIZE, /* 12947 */ + IC_VEX_L_OPSIZE, /* 12948 */ + IC_VEX_L_OPSIZE, /* 12949 */ + IC_VEX_L_OPSIZE, /* 12950 */ + IC_VEX_L_OPSIZE, /* 12951 */ + IC_VEX_L_W_OPSIZE, /* 12952 */ + IC_VEX_L_W_OPSIZE, /* 12953 */ + IC_VEX_L_W_OPSIZE, /* 12954 */ + IC_VEX_L_W_OPSIZE, /* 12955 */ + IC_VEX_L_W_OPSIZE, /* 12956 */ + IC_VEX_L_W_OPSIZE, /* 12957 */ + IC_VEX_L_W_OPSIZE, /* 12958 */ + IC_VEX_L_W_OPSIZE, /* 12959 */ + IC_VEX_L, /* 12960 */ + IC_VEX_L, /* 12961 */ + IC_VEX_L_XS, /* 12962 */ + IC_VEX_L_XS, /* 12963 */ + IC_VEX_L_XD, /* 12964 */ + IC_VEX_L_XD, /* 12965 */ + IC_VEX_L_XD, /* 12966 */ + IC_VEX_L_XD, /* 12967 */ + IC_VEX_L_W, /* 12968 */ + IC_VEX_L_W, /* 12969 */ + IC_VEX_L_W_XS, /* 12970 */ + IC_VEX_L_W_XS, /* 12971 */ + IC_VEX_L_W_XD, /* 12972 */ + IC_VEX_L_W_XD, /* 12973 */ + IC_VEX_L_W_XD, /* 12974 */ + IC_VEX_L_W_XD, /* 12975 */ + IC_VEX_L_OPSIZE, /* 12976 */ + IC_VEX_L_OPSIZE, /* 12977 */ + IC_VEX_L_OPSIZE, /* 12978 */ + IC_VEX_L_OPSIZE, /* 12979 */ + IC_VEX_L_OPSIZE, /* 12980 */ + IC_VEX_L_OPSIZE, /* 12981 */ + IC_VEX_L_OPSIZE, /* 12982 */ + IC_VEX_L_OPSIZE, /* 12983 */ + IC_VEX_L_W_OPSIZE, /* 12984 */ + IC_VEX_L_W_OPSIZE, /* 12985 */ + IC_VEX_L_W_OPSIZE, /* 12986 */ + IC_VEX_L_W_OPSIZE, /* 12987 */ + IC_VEX_L_W_OPSIZE, /* 12988 */ + IC_VEX_L_W_OPSIZE, /* 12989 */ + IC_VEX_L_W_OPSIZE, /* 12990 */ + IC_VEX_L_W_OPSIZE, /* 12991 */ + IC_VEX_L, /* 12992 */ + IC_VEX_L, /* 12993 */ + IC_VEX_L_XS, /* 12994 */ + IC_VEX_L_XS, /* 12995 */ + IC_VEX_L_XD, /* 12996 */ + IC_VEX_L_XD, /* 12997 */ + IC_VEX_L_XD, /* 12998 */ + IC_VEX_L_XD, /* 12999 */ + IC_VEX_L_W, /* 13000 */ + IC_VEX_L_W, /* 13001 */ + IC_VEX_L_W_XS, /* 13002 */ + IC_VEX_L_W_XS, /* 13003 */ + IC_VEX_L_W_XD, /* 13004 */ + IC_VEX_L_W_XD, /* 13005 */ + IC_VEX_L_W_XD, /* 13006 */ + IC_VEX_L_W_XD, /* 13007 */ + IC_VEX_L_OPSIZE, /* 13008 */ + IC_VEX_L_OPSIZE, /* 13009 */ + IC_VEX_L_OPSIZE, /* 13010 */ + IC_VEX_L_OPSIZE, /* 13011 */ + IC_VEX_L_OPSIZE, /* 13012 */ + IC_VEX_L_OPSIZE, /* 13013 */ + IC_VEX_L_OPSIZE, /* 13014 */ + IC_VEX_L_OPSIZE, /* 13015 */ + IC_VEX_L_W_OPSIZE, /* 13016 */ + IC_VEX_L_W_OPSIZE, /* 13017 */ + IC_VEX_L_W_OPSIZE, /* 13018 */ + IC_VEX_L_W_OPSIZE, /* 13019 */ + IC_VEX_L_W_OPSIZE, /* 13020 */ + IC_VEX_L_W_OPSIZE, /* 13021 */ + IC_VEX_L_W_OPSIZE, /* 13022 */ + IC_VEX_L_W_OPSIZE, /* 13023 */ + IC_VEX_L, /* 13024 */ + IC_VEX_L, /* 13025 */ + IC_VEX_L_XS, /* 13026 */ + IC_VEX_L_XS, /* 13027 */ + IC_VEX_L_XD, /* 13028 */ + IC_VEX_L_XD, /* 13029 */ + IC_VEX_L_XD, /* 13030 */ + IC_VEX_L_XD, /* 13031 */ + IC_VEX_L_W, /* 13032 */ + IC_VEX_L_W, /* 13033 */ + IC_VEX_L_W_XS, /* 13034 */ + IC_VEX_L_W_XS, /* 13035 */ + IC_VEX_L_W_XD, /* 13036 */ + IC_VEX_L_W_XD, /* 13037 */ + IC_VEX_L_W_XD, /* 13038 */ + IC_VEX_L_W_XD, /* 13039 */ + IC_VEX_L_OPSIZE, /* 13040 */ + IC_VEX_L_OPSIZE, /* 13041 */ + IC_VEX_L_OPSIZE, /* 13042 */ + IC_VEX_L_OPSIZE, /* 13043 */ + IC_VEX_L_OPSIZE, /* 13044 */ + IC_VEX_L_OPSIZE, /* 13045 */ + IC_VEX_L_OPSIZE, /* 13046 */ + IC_VEX_L_OPSIZE, /* 13047 */ + IC_VEX_L_W_OPSIZE, /* 13048 */ + IC_VEX_L_W_OPSIZE, /* 13049 */ + IC_VEX_L_W_OPSIZE, /* 13050 */ + IC_VEX_L_W_OPSIZE, /* 13051 */ + IC_VEX_L_W_OPSIZE, /* 13052 */ + IC_VEX_L_W_OPSIZE, /* 13053 */ + IC_VEX_L_W_OPSIZE, /* 13054 */ + IC_VEX_L_W_OPSIZE, /* 13055 */ + IC_EVEX_L_KZ_B, /* 13056 */ + IC_EVEX_L_KZ_B, /* 13057 */ + IC_EVEX_L_XS_KZ_B, /* 13058 */ + IC_EVEX_L_XS_KZ_B, /* 13059 */ + IC_EVEX_L_XD_KZ_B, /* 13060 */ + IC_EVEX_L_XD_KZ_B, /* 13061 */ + IC_EVEX_L_XD_KZ_B, /* 13062 */ + IC_EVEX_L_XD_KZ_B, /* 13063 */ + IC_EVEX_L_W_KZ_B, /* 13064 */ + IC_EVEX_L_W_KZ_B, /* 13065 */ + IC_EVEX_L_W_XS_KZ_B, /* 13066 */ + IC_EVEX_L_W_XS_KZ_B, /* 13067 */ + IC_EVEX_L_W_XD_KZ_B, /* 13068 */ + IC_EVEX_L_W_XD_KZ_B, /* 13069 */ + IC_EVEX_L_W_XD_KZ_B, /* 13070 */ + IC_EVEX_L_W_XD_KZ_B, /* 13071 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13072 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13073 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13074 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13075 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13076 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13077 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13078 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13079 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13080 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13081 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13082 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13083 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13084 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13085 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13086 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13087 */ + IC_EVEX_L_KZ_B, /* 13088 */ + IC_EVEX_L_KZ_B, /* 13089 */ + IC_EVEX_L_XS_KZ_B, /* 13090 */ + IC_EVEX_L_XS_KZ_B, /* 13091 */ + IC_EVEX_L_XD_KZ_B, /* 13092 */ + IC_EVEX_L_XD_KZ_B, /* 13093 */ + IC_EVEX_L_XD_KZ_B, /* 13094 */ + IC_EVEX_L_XD_KZ_B, /* 13095 */ + IC_EVEX_L_W_KZ_B, /* 13096 */ + IC_EVEX_L_W_KZ_B, /* 13097 */ + IC_EVEX_L_W_XS_KZ_B, /* 13098 */ + IC_EVEX_L_W_XS_KZ_B, /* 13099 */ + IC_EVEX_L_W_XD_KZ_B, /* 13100 */ + IC_EVEX_L_W_XD_KZ_B, /* 13101 */ + IC_EVEX_L_W_XD_KZ_B, /* 13102 */ + IC_EVEX_L_W_XD_KZ_B, /* 13103 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13104 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13105 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13106 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13107 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13108 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13109 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13110 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13111 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13112 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13113 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13114 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13115 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13116 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13117 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13118 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13119 */ + IC_EVEX_L_KZ_B, /* 13120 */ + IC_EVEX_L_KZ_B, /* 13121 */ + IC_EVEX_L_XS_KZ_B, /* 13122 */ + IC_EVEX_L_XS_KZ_B, /* 13123 */ + IC_EVEX_L_XD_KZ_B, /* 13124 */ + IC_EVEX_L_XD_KZ_B, /* 13125 */ + IC_EVEX_L_XD_KZ_B, /* 13126 */ + IC_EVEX_L_XD_KZ_B, /* 13127 */ + IC_EVEX_L_W_KZ_B, /* 13128 */ + IC_EVEX_L_W_KZ_B, /* 13129 */ + IC_EVEX_L_W_XS_KZ_B, /* 13130 */ + IC_EVEX_L_W_XS_KZ_B, /* 13131 */ + IC_EVEX_L_W_XD_KZ_B, /* 13132 */ + IC_EVEX_L_W_XD_KZ_B, /* 13133 */ + IC_EVEX_L_W_XD_KZ_B, /* 13134 */ + IC_EVEX_L_W_XD_KZ_B, /* 13135 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13136 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13137 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13138 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13139 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13140 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13141 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13142 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13143 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13144 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13145 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13146 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13147 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13148 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13149 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13150 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13151 */ + IC_EVEX_L_KZ_B, /* 13152 */ + IC_EVEX_L_KZ_B, /* 13153 */ + IC_EVEX_L_XS_KZ_B, /* 13154 */ + IC_EVEX_L_XS_KZ_B, /* 13155 */ + IC_EVEX_L_XD_KZ_B, /* 13156 */ + IC_EVEX_L_XD_KZ_B, /* 13157 */ + IC_EVEX_L_XD_KZ_B, /* 13158 */ + IC_EVEX_L_XD_KZ_B, /* 13159 */ + IC_EVEX_L_W_KZ_B, /* 13160 */ + IC_EVEX_L_W_KZ_B, /* 13161 */ + IC_EVEX_L_W_XS_KZ_B, /* 13162 */ + IC_EVEX_L_W_XS_KZ_B, /* 13163 */ + IC_EVEX_L_W_XD_KZ_B, /* 13164 */ + IC_EVEX_L_W_XD_KZ_B, /* 13165 */ + IC_EVEX_L_W_XD_KZ_B, /* 13166 */ + IC_EVEX_L_W_XD_KZ_B, /* 13167 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13168 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13169 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13170 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13171 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13172 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13173 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13174 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13175 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13176 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13177 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13178 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13179 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13180 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13181 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13182 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13183 */ + IC_EVEX_L_KZ_B, /* 13184 */ + IC_EVEX_L_KZ_B, /* 13185 */ + IC_EVEX_L_XS_KZ_B, /* 13186 */ + IC_EVEX_L_XS_KZ_B, /* 13187 */ + IC_EVEX_L_XD_KZ_B, /* 13188 */ + IC_EVEX_L_XD_KZ_B, /* 13189 */ + IC_EVEX_L_XD_KZ_B, /* 13190 */ + IC_EVEX_L_XD_KZ_B, /* 13191 */ + IC_EVEX_L_W_KZ_B, /* 13192 */ + IC_EVEX_L_W_KZ_B, /* 13193 */ + IC_EVEX_L_W_XS_KZ_B, /* 13194 */ + IC_EVEX_L_W_XS_KZ_B, /* 13195 */ + IC_EVEX_L_W_XD_KZ_B, /* 13196 */ + IC_EVEX_L_W_XD_KZ_B, /* 13197 */ + IC_EVEX_L_W_XD_KZ_B, /* 13198 */ + IC_EVEX_L_W_XD_KZ_B, /* 13199 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13200 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13201 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13202 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13203 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13204 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13205 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13206 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13207 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13208 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13209 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13210 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13211 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13212 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13213 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13214 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13215 */ + IC_EVEX_L_KZ_B, /* 13216 */ + IC_EVEX_L_KZ_B, /* 13217 */ + IC_EVEX_L_XS_KZ_B, /* 13218 */ + IC_EVEX_L_XS_KZ_B, /* 13219 */ + IC_EVEX_L_XD_KZ_B, /* 13220 */ + IC_EVEX_L_XD_KZ_B, /* 13221 */ + IC_EVEX_L_XD_KZ_B, /* 13222 */ + IC_EVEX_L_XD_KZ_B, /* 13223 */ + IC_EVEX_L_W_KZ_B, /* 13224 */ + IC_EVEX_L_W_KZ_B, /* 13225 */ + IC_EVEX_L_W_XS_KZ_B, /* 13226 */ + IC_EVEX_L_W_XS_KZ_B, /* 13227 */ + IC_EVEX_L_W_XD_KZ_B, /* 13228 */ + IC_EVEX_L_W_XD_KZ_B, /* 13229 */ + IC_EVEX_L_W_XD_KZ_B, /* 13230 */ + IC_EVEX_L_W_XD_KZ_B, /* 13231 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13232 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13233 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13234 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13235 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13236 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13237 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13238 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13239 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13240 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13241 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13242 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13243 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13244 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13245 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13246 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13247 */ + IC_EVEX_L_KZ_B, /* 13248 */ + IC_EVEX_L_KZ_B, /* 13249 */ + IC_EVEX_L_XS_KZ_B, /* 13250 */ + IC_EVEX_L_XS_KZ_B, /* 13251 */ + IC_EVEX_L_XD_KZ_B, /* 13252 */ + IC_EVEX_L_XD_KZ_B, /* 13253 */ + IC_EVEX_L_XD_KZ_B, /* 13254 */ + IC_EVEX_L_XD_KZ_B, /* 13255 */ + IC_EVEX_L_W_KZ_B, /* 13256 */ + IC_EVEX_L_W_KZ_B, /* 13257 */ + IC_EVEX_L_W_XS_KZ_B, /* 13258 */ + IC_EVEX_L_W_XS_KZ_B, /* 13259 */ + IC_EVEX_L_W_XD_KZ_B, /* 13260 */ + IC_EVEX_L_W_XD_KZ_B, /* 13261 */ + IC_EVEX_L_W_XD_KZ_B, /* 13262 */ + IC_EVEX_L_W_XD_KZ_B, /* 13263 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13264 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13265 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13266 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13267 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13268 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13269 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13270 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13271 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13272 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13273 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13274 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13275 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13276 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13277 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13278 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13279 */ + IC_EVEX_L_KZ_B, /* 13280 */ + IC_EVEX_L_KZ_B, /* 13281 */ + IC_EVEX_L_XS_KZ_B, /* 13282 */ + IC_EVEX_L_XS_KZ_B, /* 13283 */ + IC_EVEX_L_XD_KZ_B, /* 13284 */ + IC_EVEX_L_XD_KZ_B, /* 13285 */ + IC_EVEX_L_XD_KZ_B, /* 13286 */ + IC_EVEX_L_XD_KZ_B, /* 13287 */ + IC_EVEX_L_W_KZ_B, /* 13288 */ + IC_EVEX_L_W_KZ_B, /* 13289 */ + IC_EVEX_L_W_XS_KZ_B, /* 13290 */ + IC_EVEX_L_W_XS_KZ_B, /* 13291 */ + IC_EVEX_L_W_XD_KZ_B, /* 13292 */ + IC_EVEX_L_W_XD_KZ_B, /* 13293 */ + IC_EVEX_L_W_XD_KZ_B, /* 13294 */ + IC_EVEX_L_W_XD_KZ_B, /* 13295 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13296 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13297 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13298 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13299 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13300 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13301 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13302 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 13303 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13304 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13305 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13306 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13307 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13308 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13309 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13310 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 13311 */ + IC, /* 13312 */ + IC_64BIT, /* 13313 */ + IC_XS, /* 13314 */ + IC_64BIT_XS, /* 13315 */ + IC_XD, /* 13316 */ + IC_64BIT_XD, /* 13317 */ + IC_XS, /* 13318 */ + IC_64BIT_XS, /* 13319 */ + IC, /* 13320 */ + IC_64BIT_REXW, /* 13321 */ + IC_XS, /* 13322 */ + IC_64BIT_REXW_XS, /* 13323 */ + IC_XD, /* 13324 */ + IC_64BIT_REXW_XD, /* 13325 */ + IC_XS, /* 13326 */ + IC_64BIT_REXW_XS, /* 13327 */ + IC_OPSIZE, /* 13328 */ + IC_64BIT_OPSIZE, /* 13329 */ + IC_XS_OPSIZE, /* 13330 */ + IC_64BIT_XS_OPSIZE, /* 13331 */ + IC_XD_OPSIZE, /* 13332 */ + IC_64BIT_XD_OPSIZE, /* 13333 */ + IC_XS_OPSIZE, /* 13334 */ + IC_64BIT_XD_OPSIZE, /* 13335 */ + IC_OPSIZE, /* 13336 */ + IC_64BIT_REXW_OPSIZE, /* 13337 */ + IC_XS_OPSIZE, /* 13338 */ + IC_64BIT_REXW_XS, /* 13339 */ + IC_XD_OPSIZE, /* 13340 */ + IC_64BIT_REXW_XD, /* 13341 */ + IC_XS_OPSIZE, /* 13342 */ + IC_64BIT_REXW_XS, /* 13343 */ + IC_ADSIZE, /* 13344 */ + IC_64BIT_ADSIZE, /* 13345 */ + IC_XS_ADSIZE, /* 13346 */ + IC_64BIT_XS_ADSIZE, /* 13347 */ + IC_XD_ADSIZE, /* 13348 */ + IC_64BIT_XD_ADSIZE, /* 13349 */ + IC_XS_ADSIZE, /* 13350 */ + IC_64BIT_XD_ADSIZE, /* 13351 */ + IC_ADSIZE, /* 13352 */ + IC_64BIT_REXW_ADSIZE, /* 13353 */ + IC_XS_ADSIZE, /* 13354 */ + IC_64BIT_REXW_XS, /* 13355 */ + IC_XD_ADSIZE, /* 13356 */ + IC_64BIT_REXW_XD, /* 13357 */ + IC_XS_ADSIZE, /* 13358 */ + IC_64BIT_REXW_XS, /* 13359 */ + IC_OPSIZE_ADSIZE, /* 13360 */ + IC_64BIT_OPSIZE_ADSIZE, /* 13361 */ + IC_XS_OPSIZE, /* 13362 */ + IC_64BIT_XS_OPSIZE, /* 13363 */ + IC_XD_OPSIZE, /* 13364 */ + IC_64BIT_XD_OPSIZE, /* 13365 */ + IC_XS_OPSIZE, /* 13366 */ + IC_64BIT_XD_OPSIZE, /* 13367 */ + IC_OPSIZE_ADSIZE, /* 13368 */ + IC_64BIT_REXW_OPSIZE, /* 13369 */ + IC_XS_OPSIZE, /* 13370 */ + IC_64BIT_REXW_XS, /* 13371 */ + IC_XD_OPSIZE, /* 13372 */ + IC_64BIT_REXW_XD, /* 13373 */ + IC_XS_OPSIZE, /* 13374 */ + IC_64BIT_REXW_XS, /* 13375 */ + IC_VEX, /* 13376 */ + IC_VEX, /* 13377 */ + IC_VEX_XS, /* 13378 */ + IC_VEX_XS, /* 13379 */ + IC_VEX_XD, /* 13380 */ + IC_VEX_XD, /* 13381 */ + IC_VEX_XD, /* 13382 */ + IC_VEX_XD, /* 13383 */ + IC_VEX_W, /* 13384 */ + IC_VEX_W, /* 13385 */ + IC_VEX_W_XS, /* 13386 */ + IC_VEX_W_XS, /* 13387 */ + IC_VEX_W_XD, /* 13388 */ + IC_VEX_W_XD, /* 13389 */ + IC_VEX_W_XD, /* 13390 */ + IC_VEX_W_XD, /* 13391 */ + IC_VEX_OPSIZE, /* 13392 */ + IC_VEX_OPSIZE, /* 13393 */ + IC_VEX_OPSIZE, /* 13394 */ + IC_VEX_OPSIZE, /* 13395 */ + IC_VEX_OPSIZE, /* 13396 */ + IC_VEX_OPSIZE, /* 13397 */ + IC_VEX_OPSIZE, /* 13398 */ + IC_VEX_OPSIZE, /* 13399 */ + IC_VEX_W_OPSIZE, /* 13400 */ + IC_VEX_W_OPSIZE, /* 13401 */ + IC_VEX_W_OPSIZE, /* 13402 */ + IC_VEX_W_OPSIZE, /* 13403 */ + IC_VEX_W_OPSIZE, /* 13404 */ + IC_VEX_W_OPSIZE, /* 13405 */ + IC_VEX_W_OPSIZE, /* 13406 */ + IC_VEX_W_OPSIZE, /* 13407 */ + IC_VEX, /* 13408 */ + IC_VEX, /* 13409 */ + IC_VEX_XS, /* 13410 */ + IC_VEX_XS, /* 13411 */ + IC_VEX_XD, /* 13412 */ + IC_VEX_XD, /* 13413 */ + IC_VEX_XD, /* 13414 */ + IC_VEX_XD, /* 13415 */ + IC_VEX_W, /* 13416 */ + IC_VEX_W, /* 13417 */ + IC_VEX_W_XS, /* 13418 */ + IC_VEX_W_XS, /* 13419 */ + IC_VEX_W_XD, /* 13420 */ + IC_VEX_W_XD, /* 13421 */ + IC_VEX_W_XD, /* 13422 */ + IC_VEX_W_XD, /* 13423 */ + IC_VEX_OPSIZE, /* 13424 */ + IC_VEX_OPSIZE, /* 13425 */ + IC_VEX_OPSIZE, /* 13426 */ + IC_VEX_OPSIZE, /* 13427 */ + IC_VEX_OPSIZE, /* 13428 */ + IC_VEX_OPSIZE, /* 13429 */ + IC_VEX_OPSIZE, /* 13430 */ + IC_VEX_OPSIZE, /* 13431 */ + IC_VEX_W_OPSIZE, /* 13432 */ + IC_VEX_W_OPSIZE, /* 13433 */ + IC_VEX_W_OPSIZE, /* 13434 */ + IC_VEX_W_OPSIZE, /* 13435 */ + IC_VEX_W_OPSIZE, /* 13436 */ + IC_VEX_W_OPSIZE, /* 13437 */ + IC_VEX_W_OPSIZE, /* 13438 */ + IC_VEX_W_OPSIZE, /* 13439 */ + IC_VEX_L, /* 13440 */ + IC_VEX_L, /* 13441 */ + IC_VEX_L_XS, /* 13442 */ + IC_VEX_L_XS, /* 13443 */ + IC_VEX_L_XD, /* 13444 */ + IC_VEX_L_XD, /* 13445 */ + IC_VEX_L_XD, /* 13446 */ + IC_VEX_L_XD, /* 13447 */ + IC_VEX_L_W, /* 13448 */ + IC_VEX_L_W, /* 13449 */ + IC_VEX_L_W_XS, /* 13450 */ + IC_VEX_L_W_XS, /* 13451 */ + IC_VEX_L_W_XD, /* 13452 */ + IC_VEX_L_W_XD, /* 13453 */ + IC_VEX_L_W_XD, /* 13454 */ + IC_VEX_L_W_XD, /* 13455 */ + IC_VEX_L_OPSIZE, /* 13456 */ + IC_VEX_L_OPSIZE, /* 13457 */ + IC_VEX_L_OPSIZE, /* 13458 */ + IC_VEX_L_OPSIZE, /* 13459 */ + IC_VEX_L_OPSIZE, /* 13460 */ + IC_VEX_L_OPSIZE, /* 13461 */ + IC_VEX_L_OPSIZE, /* 13462 */ + IC_VEX_L_OPSIZE, /* 13463 */ + IC_VEX_L_W_OPSIZE, /* 13464 */ + IC_VEX_L_W_OPSIZE, /* 13465 */ + IC_VEX_L_W_OPSIZE, /* 13466 */ + IC_VEX_L_W_OPSIZE, /* 13467 */ + IC_VEX_L_W_OPSIZE, /* 13468 */ + IC_VEX_L_W_OPSIZE, /* 13469 */ + IC_VEX_L_W_OPSIZE, /* 13470 */ + IC_VEX_L_W_OPSIZE, /* 13471 */ + IC_VEX_L, /* 13472 */ + IC_VEX_L, /* 13473 */ + IC_VEX_L_XS, /* 13474 */ + IC_VEX_L_XS, /* 13475 */ + IC_VEX_L_XD, /* 13476 */ + IC_VEX_L_XD, /* 13477 */ + IC_VEX_L_XD, /* 13478 */ + IC_VEX_L_XD, /* 13479 */ + IC_VEX_L_W, /* 13480 */ + IC_VEX_L_W, /* 13481 */ + IC_VEX_L_W_XS, /* 13482 */ + IC_VEX_L_W_XS, /* 13483 */ + IC_VEX_L_W_XD, /* 13484 */ + IC_VEX_L_W_XD, /* 13485 */ + IC_VEX_L_W_XD, /* 13486 */ + IC_VEX_L_W_XD, /* 13487 */ + IC_VEX_L_OPSIZE, /* 13488 */ + IC_VEX_L_OPSIZE, /* 13489 */ + IC_VEX_L_OPSIZE, /* 13490 */ + IC_VEX_L_OPSIZE, /* 13491 */ + IC_VEX_L_OPSIZE, /* 13492 */ + IC_VEX_L_OPSIZE, /* 13493 */ + IC_VEX_L_OPSIZE, /* 13494 */ + IC_VEX_L_OPSIZE, /* 13495 */ + IC_VEX_L_W_OPSIZE, /* 13496 */ + IC_VEX_L_W_OPSIZE, /* 13497 */ + IC_VEX_L_W_OPSIZE, /* 13498 */ + IC_VEX_L_W_OPSIZE, /* 13499 */ + IC_VEX_L_W_OPSIZE, /* 13500 */ + IC_VEX_L_W_OPSIZE, /* 13501 */ + IC_VEX_L_W_OPSIZE, /* 13502 */ + IC_VEX_L_W_OPSIZE, /* 13503 */ + IC_VEX_L, /* 13504 */ + IC_VEX_L, /* 13505 */ + IC_VEX_L_XS, /* 13506 */ + IC_VEX_L_XS, /* 13507 */ + IC_VEX_L_XD, /* 13508 */ + IC_VEX_L_XD, /* 13509 */ + IC_VEX_L_XD, /* 13510 */ + IC_VEX_L_XD, /* 13511 */ + IC_VEX_L_W, /* 13512 */ + IC_VEX_L_W, /* 13513 */ + IC_VEX_L_W_XS, /* 13514 */ + IC_VEX_L_W_XS, /* 13515 */ + IC_VEX_L_W_XD, /* 13516 */ + IC_VEX_L_W_XD, /* 13517 */ + IC_VEX_L_W_XD, /* 13518 */ + IC_VEX_L_W_XD, /* 13519 */ + IC_VEX_L_OPSIZE, /* 13520 */ + IC_VEX_L_OPSIZE, /* 13521 */ + IC_VEX_L_OPSIZE, /* 13522 */ + IC_VEX_L_OPSIZE, /* 13523 */ + IC_VEX_L_OPSIZE, /* 13524 */ + IC_VEX_L_OPSIZE, /* 13525 */ + IC_VEX_L_OPSIZE, /* 13526 */ + IC_VEX_L_OPSIZE, /* 13527 */ + IC_VEX_L_W_OPSIZE, /* 13528 */ + IC_VEX_L_W_OPSIZE, /* 13529 */ + IC_VEX_L_W_OPSIZE, /* 13530 */ + IC_VEX_L_W_OPSIZE, /* 13531 */ + IC_VEX_L_W_OPSIZE, /* 13532 */ + IC_VEX_L_W_OPSIZE, /* 13533 */ + IC_VEX_L_W_OPSIZE, /* 13534 */ + IC_VEX_L_W_OPSIZE, /* 13535 */ + IC_VEX_L, /* 13536 */ + IC_VEX_L, /* 13537 */ + IC_VEX_L_XS, /* 13538 */ + IC_VEX_L_XS, /* 13539 */ + IC_VEX_L_XD, /* 13540 */ + IC_VEX_L_XD, /* 13541 */ + IC_VEX_L_XD, /* 13542 */ + IC_VEX_L_XD, /* 13543 */ + IC_VEX_L_W, /* 13544 */ + IC_VEX_L_W, /* 13545 */ + IC_VEX_L_W_XS, /* 13546 */ + IC_VEX_L_W_XS, /* 13547 */ + IC_VEX_L_W_XD, /* 13548 */ + IC_VEX_L_W_XD, /* 13549 */ + IC_VEX_L_W_XD, /* 13550 */ + IC_VEX_L_W_XD, /* 13551 */ + IC_VEX_L_OPSIZE, /* 13552 */ + IC_VEX_L_OPSIZE, /* 13553 */ + IC_VEX_L_OPSIZE, /* 13554 */ + IC_VEX_L_OPSIZE, /* 13555 */ + IC_VEX_L_OPSIZE, /* 13556 */ + IC_VEX_L_OPSIZE, /* 13557 */ + IC_VEX_L_OPSIZE, /* 13558 */ + IC_VEX_L_OPSIZE, /* 13559 */ + IC_VEX_L_W_OPSIZE, /* 13560 */ + IC_VEX_L_W_OPSIZE, /* 13561 */ + IC_VEX_L_W_OPSIZE, /* 13562 */ + IC_VEX_L_W_OPSIZE, /* 13563 */ + IC_VEX_L_W_OPSIZE, /* 13564 */ + IC_VEX_L_W_OPSIZE, /* 13565 */ + IC_VEX_L_W_OPSIZE, /* 13566 */ + IC_VEX_L_W_OPSIZE, /* 13567 */ + IC_EVEX_L2_KZ_B, /* 13568 */ + IC_EVEX_L2_KZ_B, /* 13569 */ + IC_EVEX_L2_XS_KZ_B, /* 13570 */ + IC_EVEX_L2_XS_KZ_B, /* 13571 */ + IC_EVEX_L2_XD_KZ_B, /* 13572 */ + IC_EVEX_L2_XD_KZ_B, /* 13573 */ + IC_EVEX_L2_XD_KZ_B, /* 13574 */ + IC_EVEX_L2_XD_KZ_B, /* 13575 */ + IC_EVEX_L2_W_KZ_B, /* 13576 */ + IC_EVEX_L2_W_KZ_B, /* 13577 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13578 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13579 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13580 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13581 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13582 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13583 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13584 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13585 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13586 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13587 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13588 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13589 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13590 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13591 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13592 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13593 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13594 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13595 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13596 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13597 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13598 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13599 */ + IC_EVEX_L2_KZ_B, /* 13600 */ + IC_EVEX_L2_KZ_B, /* 13601 */ + IC_EVEX_L2_XS_KZ_B, /* 13602 */ + IC_EVEX_L2_XS_KZ_B, /* 13603 */ + IC_EVEX_L2_XD_KZ_B, /* 13604 */ + IC_EVEX_L2_XD_KZ_B, /* 13605 */ + IC_EVEX_L2_XD_KZ_B, /* 13606 */ + IC_EVEX_L2_XD_KZ_B, /* 13607 */ + IC_EVEX_L2_W_KZ_B, /* 13608 */ + IC_EVEX_L2_W_KZ_B, /* 13609 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13610 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13611 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13612 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13613 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13614 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13615 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13616 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13617 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13618 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13619 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13620 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13621 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13622 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13623 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13624 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13625 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13626 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13627 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13628 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13629 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13630 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13631 */ + IC_EVEX_L2_KZ_B, /* 13632 */ + IC_EVEX_L2_KZ_B, /* 13633 */ + IC_EVEX_L2_XS_KZ_B, /* 13634 */ + IC_EVEX_L2_XS_KZ_B, /* 13635 */ + IC_EVEX_L2_XD_KZ_B, /* 13636 */ + IC_EVEX_L2_XD_KZ_B, /* 13637 */ + IC_EVEX_L2_XD_KZ_B, /* 13638 */ + IC_EVEX_L2_XD_KZ_B, /* 13639 */ + IC_EVEX_L2_W_KZ_B, /* 13640 */ + IC_EVEX_L2_W_KZ_B, /* 13641 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13642 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13643 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13644 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13645 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13646 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13647 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13648 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13649 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13650 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13651 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13652 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13653 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13654 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13655 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13656 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13657 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13658 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13659 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13660 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13661 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13662 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13663 */ + IC_EVEX_L2_KZ_B, /* 13664 */ + IC_EVEX_L2_KZ_B, /* 13665 */ + IC_EVEX_L2_XS_KZ_B, /* 13666 */ + IC_EVEX_L2_XS_KZ_B, /* 13667 */ + IC_EVEX_L2_XD_KZ_B, /* 13668 */ + IC_EVEX_L2_XD_KZ_B, /* 13669 */ + IC_EVEX_L2_XD_KZ_B, /* 13670 */ + IC_EVEX_L2_XD_KZ_B, /* 13671 */ + IC_EVEX_L2_W_KZ_B, /* 13672 */ + IC_EVEX_L2_W_KZ_B, /* 13673 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13674 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13675 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13676 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13677 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13678 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13679 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13680 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13681 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13682 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13683 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13684 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13685 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13686 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13687 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13688 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13689 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13690 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13691 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13692 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13693 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13694 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13695 */ + IC_EVEX_L2_KZ_B, /* 13696 */ + IC_EVEX_L2_KZ_B, /* 13697 */ + IC_EVEX_L2_XS_KZ_B, /* 13698 */ + IC_EVEX_L2_XS_KZ_B, /* 13699 */ + IC_EVEX_L2_XD_KZ_B, /* 13700 */ + IC_EVEX_L2_XD_KZ_B, /* 13701 */ + IC_EVEX_L2_XD_KZ_B, /* 13702 */ + IC_EVEX_L2_XD_KZ_B, /* 13703 */ + IC_EVEX_L2_W_KZ_B, /* 13704 */ + IC_EVEX_L2_W_KZ_B, /* 13705 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13706 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13707 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13708 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13709 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13710 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13711 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13712 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13713 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13714 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13715 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13716 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13717 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13718 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13719 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13720 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13721 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13722 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13723 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13724 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13725 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13726 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13727 */ + IC_EVEX_L2_KZ_B, /* 13728 */ + IC_EVEX_L2_KZ_B, /* 13729 */ + IC_EVEX_L2_XS_KZ_B, /* 13730 */ + IC_EVEX_L2_XS_KZ_B, /* 13731 */ + IC_EVEX_L2_XD_KZ_B, /* 13732 */ + IC_EVEX_L2_XD_KZ_B, /* 13733 */ + IC_EVEX_L2_XD_KZ_B, /* 13734 */ + IC_EVEX_L2_XD_KZ_B, /* 13735 */ + IC_EVEX_L2_W_KZ_B, /* 13736 */ + IC_EVEX_L2_W_KZ_B, /* 13737 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13738 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13739 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13740 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13741 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13742 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13743 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13744 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13745 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13746 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13747 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13748 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13749 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13750 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13751 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13752 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13753 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13754 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13755 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13756 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13757 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13758 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13759 */ + IC_EVEX_L2_KZ_B, /* 13760 */ + IC_EVEX_L2_KZ_B, /* 13761 */ + IC_EVEX_L2_XS_KZ_B, /* 13762 */ + IC_EVEX_L2_XS_KZ_B, /* 13763 */ + IC_EVEX_L2_XD_KZ_B, /* 13764 */ + IC_EVEX_L2_XD_KZ_B, /* 13765 */ + IC_EVEX_L2_XD_KZ_B, /* 13766 */ + IC_EVEX_L2_XD_KZ_B, /* 13767 */ + IC_EVEX_L2_W_KZ_B, /* 13768 */ + IC_EVEX_L2_W_KZ_B, /* 13769 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13770 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13771 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13772 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13773 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13774 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13775 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13776 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13777 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13778 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13779 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13780 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13781 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13782 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13783 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13784 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13785 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13786 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13787 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13788 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13789 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13790 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13791 */ + IC_EVEX_L2_KZ_B, /* 13792 */ + IC_EVEX_L2_KZ_B, /* 13793 */ + IC_EVEX_L2_XS_KZ_B, /* 13794 */ + IC_EVEX_L2_XS_KZ_B, /* 13795 */ + IC_EVEX_L2_XD_KZ_B, /* 13796 */ + IC_EVEX_L2_XD_KZ_B, /* 13797 */ + IC_EVEX_L2_XD_KZ_B, /* 13798 */ + IC_EVEX_L2_XD_KZ_B, /* 13799 */ + IC_EVEX_L2_W_KZ_B, /* 13800 */ + IC_EVEX_L2_W_KZ_B, /* 13801 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13802 */ + IC_EVEX_L2_W_XS_KZ_B, /* 13803 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13804 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13805 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13806 */ + IC_EVEX_L2_W_XD_KZ_B, /* 13807 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13808 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13809 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13810 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13811 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13812 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13813 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13814 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 13815 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13816 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13817 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13818 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13819 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13820 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13821 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13822 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13823 */ + IC, /* 13824 */ + IC_64BIT, /* 13825 */ + IC_XS, /* 13826 */ + IC_64BIT_XS, /* 13827 */ + IC_XD, /* 13828 */ + IC_64BIT_XD, /* 13829 */ + IC_XS, /* 13830 */ + IC_64BIT_XS, /* 13831 */ + IC, /* 13832 */ + IC_64BIT_REXW, /* 13833 */ + IC_XS, /* 13834 */ + IC_64BIT_REXW_XS, /* 13835 */ + IC_XD, /* 13836 */ + IC_64BIT_REXW_XD, /* 13837 */ + IC_XS, /* 13838 */ + IC_64BIT_REXW_XS, /* 13839 */ + IC_OPSIZE, /* 13840 */ + IC_64BIT_OPSIZE, /* 13841 */ + IC_XS_OPSIZE, /* 13842 */ + IC_64BIT_XS_OPSIZE, /* 13843 */ + IC_XD_OPSIZE, /* 13844 */ + IC_64BIT_XD_OPSIZE, /* 13845 */ + IC_XS_OPSIZE, /* 13846 */ + IC_64BIT_XD_OPSIZE, /* 13847 */ + IC_OPSIZE, /* 13848 */ + IC_64BIT_REXW_OPSIZE, /* 13849 */ + IC_XS_OPSIZE, /* 13850 */ + IC_64BIT_REXW_XS, /* 13851 */ + IC_XD_OPSIZE, /* 13852 */ + IC_64BIT_REXW_XD, /* 13853 */ + IC_XS_OPSIZE, /* 13854 */ + IC_64BIT_REXW_XS, /* 13855 */ + IC_ADSIZE, /* 13856 */ + IC_64BIT_ADSIZE, /* 13857 */ + IC_XS_ADSIZE, /* 13858 */ + IC_64BIT_XS_ADSIZE, /* 13859 */ + IC_XD_ADSIZE, /* 13860 */ + IC_64BIT_XD_ADSIZE, /* 13861 */ + IC_XS_ADSIZE, /* 13862 */ + IC_64BIT_XD_ADSIZE, /* 13863 */ + IC_ADSIZE, /* 13864 */ + IC_64BIT_REXW_ADSIZE, /* 13865 */ + IC_XS_ADSIZE, /* 13866 */ + IC_64BIT_REXW_XS, /* 13867 */ + IC_XD_ADSIZE, /* 13868 */ + IC_64BIT_REXW_XD, /* 13869 */ + IC_XS_ADSIZE, /* 13870 */ + IC_64BIT_REXW_XS, /* 13871 */ + IC_OPSIZE_ADSIZE, /* 13872 */ + IC_64BIT_OPSIZE_ADSIZE, /* 13873 */ + IC_XS_OPSIZE, /* 13874 */ + IC_64BIT_XS_OPSIZE, /* 13875 */ + IC_XD_OPSIZE, /* 13876 */ + IC_64BIT_XD_OPSIZE, /* 13877 */ + IC_XS_OPSIZE, /* 13878 */ + IC_64BIT_XD_OPSIZE, /* 13879 */ + IC_OPSIZE_ADSIZE, /* 13880 */ + IC_64BIT_REXW_OPSIZE, /* 13881 */ + IC_XS_OPSIZE, /* 13882 */ + IC_64BIT_REXW_XS, /* 13883 */ + IC_XD_OPSIZE, /* 13884 */ + IC_64BIT_REXW_XD, /* 13885 */ + IC_XS_OPSIZE, /* 13886 */ + IC_64BIT_REXW_XS, /* 13887 */ + IC_VEX, /* 13888 */ + IC_VEX, /* 13889 */ + IC_VEX_XS, /* 13890 */ + IC_VEX_XS, /* 13891 */ + IC_VEX_XD, /* 13892 */ + IC_VEX_XD, /* 13893 */ + IC_VEX_XD, /* 13894 */ + IC_VEX_XD, /* 13895 */ + IC_VEX_W, /* 13896 */ + IC_VEX_W, /* 13897 */ + IC_VEX_W_XS, /* 13898 */ + IC_VEX_W_XS, /* 13899 */ + IC_VEX_W_XD, /* 13900 */ + IC_VEX_W_XD, /* 13901 */ + IC_VEX_W_XD, /* 13902 */ + IC_VEX_W_XD, /* 13903 */ + IC_VEX_OPSIZE, /* 13904 */ + IC_VEX_OPSIZE, /* 13905 */ + IC_VEX_OPSIZE, /* 13906 */ + IC_VEX_OPSIZE, /* 13907 */ + IC_VEX_OPSIZE, /* 13908 */ + IC_VEX_OPSIZE, /* 13909 */ + IC_VEX_OPSIZE, /* 13910 */ + IC_VEX_OPSIZE, /* 13911 */ + IC_VEX_W_OPSIZE, /* 13912 */ + IC_VEX_W_OPSIZE, /* 13913 */ + IC_VEX_W_OPSIZE, /* 13914 */ + IC_VEX_W_OPSIZE, /* 13915 */ + IC_VEX_W_OPSIZE, /* 13916 */ + IC_VEX_W_OPSIZE, /* 13917 */ + IC_VEX_W_OPSIZE, /* 13918 */ + IC_VEX_W_OPSIZE, /* 13919 */ + IC_VEX, /* 13920 */ + IC_VEX, /* 13921 */ + IC_VEX_XS, /* 13922 */ + IC_VEX_XS, /* 13923 */ + IC_VEX_XD, /* 13924 */ + IC_VEX_XD, /* 13925 */ + IC_VEX_XD, /* 13926 */ + IC_VEX_XD, /* 13927 */ + IC_VEX_W, /* 13928 */ + IC_VEX_W, /* 13929 */ + IC_VEX_W_XS, /* 13930 */ + IC_VEX_W_XS, /* 13931 */ + IC_VEX_W_XD, /* 13932 */ + IC_VEX_W_XD, /* 13933 */ + IC_VEX_W_XD, /* 13934 */ + IC_VEX_W_XD, /* 13935 */ + IC_VEX_OPSIZE, /* 13936 */ + IC_VEX_OPSIZE, /* 13937 */ + IC_VEX_OPSIZE, /* 13938 */ + IC_VEX_OPSIZE, /* 13939 */ + IC_VEX_OPSIZE, /* 13940 */ + IC_VEX_OPSIZE, /* 13941 */ + IC_VEX_OPSIZE, /* 13942 */ + IC_VEX_OPSIZE, /* 13943 */ + IC_VEX_W_OPSIZE, /* 13944 */ + IC_VEX_W_OPSIZE, /* 13945 */ + IC_VEX_W_OPSIZE, /* 13946 */ + IC_VEX_W_OPSIZE, /* 13947 */ + IC_VEX_W_OPSIZE, /* 13948 */ + IC_VEX_W_OPSIZE, /* 13949 */ + IC_VEX_W_OPSIZE, /* 13950 */ + IC_VEX_W_OPSIZE, /* 13951 */ + IC_VEX_L, /* 13952 */ + IC_VEX_L, /* 13953 */ + IC_VEX_L_XS, /* 13954 */ + IC_VEX_L_XS, /* 13955 */ + IC_VEX_L_XD, /* 13956 */ + IC_VEX_L_XD, /* 13957 */ + IC_VEX_L_XD, /* 13958 */ + IC_VEX_L_XD, /* 13959 */ + IC_VEX_L_W, /* 13960 */ + IC_VEX_L_W, /* 13961 */ + IC_VEX_L_W_XS, /* 13962 */ + IC_VEX_L_W_XS, /* 13963 */ + IC_VEX_L_W_XD, /* 13964 */ + IC_VEX_L_W_XD, /* 13965 */ + IC_VEX_L_W_XD, /* 13966 */ + IC_VEX_L_W_XD, /* 13967 */ + IC_VEX_L_OPSIZE, /* 13968 */ + IC_VEX_L_OPSIZE, /* 13969 */ + IC_VEX_L_OPSIZE, /* 13970 */ + IC_VEX_L_OPSIZE, /* 13971 */ + IC_VEX_L_OPSIZE, /* 13972 */ + IC_VEX_L_OPSIZE, /* 13973 */ + IC_VEX_L_OPSIZE, /* 13974 */ + IC_VEX_L_OPSIZE, /* 13975 */ + IC_VEX_L_W_OPSIZE, /* 13976 */ + IC_VEX_L_W_OPSIZE, /* 13977 */ + IC_VEX_L_W_OPSIZE, /* 13978 */ + IC_VEX_L_W_OPSIZE, /* 13979 */ + IC_VEX_L_W_OPSIZE, /* 13980 */ + IC_VEX_L_W_OPSIZE, /* 13981 */ + IC_VEX_L_W_OPSIZE, /* 13982 */ + IC_VEX_L_W_OPSIZE, /* 13983 */ + IC_VEX_L, /* 13984 */ + IC_VEX_L, /* 13985 */ + IC_VEX_L_XS, /* 13986 */ + IC_VEX_L_XS, /* 13987 */ + IC_VEX_L_XD, /* 13988 */ + IC_VEX_L_XD, /* 13989 */ + IC_VEX_L_XD, /* 13990 */ + IC_VEX_L_XD, /* 13991 */ + IC_VEX_L_W, /* 13992 */ + IC_VEX_L_W, /* 13993 */ + IC_VEX_L_W_XS, /* 13994 */ + IC_VEX_L_W_XS, /* 13995 */ + IC_VEX_L_W_XD, /* 13996 */ + IC_VEX_L_W_XD, /* 13997 */ + IC_VEX_L_W_XD, /* 13998 */ + IC_VEX_L_W_XD, /* 13999 */ + IC_VEX_L_OPSIZE, /* 14000 */ + IC_VEX_L_OPSIZE, /* 14001 */ + IC_VEX_L_OPSIZE, /* 14002 */ + IC_VEX_L_OPSIZE, /* 14003 */ + IC_VEX_L_OPSIZE, /* 14004 */ + IC_VEX_L_OPSIZE, /* 14005 */ + IC_VEX_L_OPSIZE, /* 14006 */ + IC_VEX_L_OPSIZE, /* 14007 */ + IC_VEX_L_W_OPSIZE, /* 14008 */ + IC_VEX_L_W_OPSIZE, /* 14009 */ + IC_VEX_L_W_OPSIZE, /* 14010 */ + IC_VEX_L_W_OPSIZE, /* 14011 */ + IC_VEX_L_W_OPSIZE, /* 14012 */ + IC_VEX_L_W_OPSIZE, /* 14013 */ + IC_VEX_L_W_OPSIZE, /* 14014 */ + IC_VEX_L_W_OPSIZE, /* 14015 */ + IC_VEX_L, /* 14016 */ + IC_VEX_L, /* 14017 */ + IC_VEX_L_XS, /* 14018 */ + IC_VEX_L_XS, /* 14019 */ + IC_VEX_L_XD, /* 14020 */ + IC_VEX_L_XD, /* 14021 */ + IC_VEX_L_XD, /* 14022 */ + IC_VEX_L_XD, /* 14023 */ + IC_VEX_L_W, /* 14024 */ + IC_VEX_L_W, /* 14025 */ + IC_VEX_L_W_XS, /* 14026 */ + IC_VEX_L_W_XS, /* 14027 */ + IC_VEX_L_W_XD, /* 14028 */ + IC_VEX_L_W_XD, /* 14029 */ + IC_VEX_L_W_XD, /* 14030 */ + IC_VEX_L_W_XD, /* 14031 */ + IC_VEX_L_OPSIZE, /* 14032 */ + IC_VEX_L_OPSIZE, /* 14033 */ + IC_VEX_L_OPSIZE, /* 14034 */ + IC_VEX_L_OPSIZE, /* 14035 */ + IC_VEX_L_OPSIZE, /* 14036 */ + IC_VEX_L_OPSIZE, /* 14037 */ + IC_VEX_L_OPSIZE, /* 14038 */ + IC_VEX_L_OPSIZE, /* 14039 */ + IC_VEX_L_W_OPSIZE, /* 14040 */ + IC_VEX_L_W_OPSIZE, /* 14041 */ + IC_VEX_L_W_OPSIZE, /* 14042 */ + IC_VEX_L_W_OPSIZE, /* 14043 */ + IC_VEX_L_W_OPSIZE, /* 14044 */ + IC_VEX_L_W_OPSIZE, /* 14045 */ + IC_VEX_L_W_OPSIZE, /* 14046 */ + IC_VEX_L_W_OPSIZE, /* 14047 */ + IC_VEX_L, /* 14048 */ + IC_VEX_L, /* 14049 */ + IC_VEX_L_XS, /* 14050 */ + IC_VEX_L_XS, /* 14051 */ + IC_VEX_L_XD, /* 14052 */ + IC_VEX_L_XD, /* 14053 */ + IC_VEX_L_XD, /* 14054 */ + IC_VEX_L_XD, /* 14055 */ + IC_VEX_L_W, /* 14056 */ + IC_VEX_L_W, /* 14057 */ + IC_VEX_L_W_XS, /* 14058 */ + IC_VEX_L_W_XS, /* 14059 */ + IC_VEX_L_W_XD, /* 14060 */ + IC_VEX_L_W_XD, /* 14061 */ + IC_VEX_L_W_XD, /* 14062 */ + IC_VEX_L_W_XD, /* 14063 */ + IC_VEX_L_OPSIZE, /* 14064 */ + IC_VEX_L_OPSIZE, /* 14065 */ + IC_VEX_L_OPSIZE, /* 14066 */ + IC_VEX_L_OPSIZE, /* 14067 */ + IC_VEX_L_OPSIZE, /* 14068 */ + IC_VEX_L_OPSIZE, /* 14069 */ + IC_VEX_L_OPSIZE, /* 14070 */ + IC_VEX_L_OPSIZE, /* 14071 */ + IC_VEX_L_W_OPSIZE, /* 14072 */ + IC_VEX_L_W_OPSIZE, /* 14073 */ + IC_VEX_L_W_OPSIZE, /* 14074 */ + IC_VEX_L_W_OPSIZE, /* 14075 */ + IC_VEX_L_W_OPSIZE, /* 14076 */ + IC_VEX_L_W_OPSIZE, /* 14077 */ + IC_VEX_L_W_OPSIZE, /* 14078 */ + IC_VEX_L_W_OPSIZE, /* 14079 */ + IC_EVEX_L2_KZ_B, /* 14080 */ + IC_EVEX_L2_KZ_B, /* 14081 */ + IC_EVEX_L2_XS_KZ_B, /* 14082 */ + IC_EVEX_L2_XS_KZ_B, /* 14083 */ + IC_EVEX_L2_XD_KZ_B, /* 14084 */ + IC_EVEX_L2_XD_KZ_B, /* 14085 */ + IC_EVEX_L2_XD_KZ_B, /* 14086 */ + IC_EVEX_L2_XD_KZ_B, /* 14087 */ + IC_EVEX_L2_W_KZ_B, /* 14088 */ + IC_EVEX_L2_W_KZ_B, /* 14089 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14090 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14091 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14092 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14093 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14094 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14095 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14096 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14097 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14098 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14099 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14100 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14101 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14102 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14103 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14104 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14105 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14106 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14107 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14108 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14109 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14110 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14111 */ + IC_EVEX_L2_KZ_B, /* 14112 */ + IC_EVEX_L2_KZ_B, /* 14113 */ + IC_EVEX_L2_XS_KZ_B, /* 14114 */ + IC_EVEX_L2_XS_KZ_B, /* 14115 */ + IC_EVEX_L2_XD_KZ_B, /* 14116 */ + IC_EVEX_L2_XD_KZ_B, /* 14117 */ + IC_EVEX_L2_XD_KZ_B, /* 14118 */ + IC_EVEX_L2_XD_KZ_B, /* 14119 */ + IC_EVEX_L2_W_KZ_B, /* 14120 */ + IC_EVEX_L2_W_KZ_B, /* 14121 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14122 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14123 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14124 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14125 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14126 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14127 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14128 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14129 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14130 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14131 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14132 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14133 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14134 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14135 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14136 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14137 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14138 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14139 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14140 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14141 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14142 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14143 */ + IC_EVEX_L2_KZ_B, /* 14144 */ + IC_EVEX_L2_KZ_B, /* 14145 */ + IC_EVEX_L2_XS_KZ_B, /* 14146 */ + IC_EVEX_L2_XS_KZ_B, /* 14147 */ + IC_EVEX_L2_XD_KZ_B, /* 14148 */ + IC_EVEX_L2_XD_KZ_B, /* 14149 */ + IC_EVEX_L2_XD_KZ_B, /* 14150 */ + IC_EVEX_L2_XD_KZ_B, /* 14151 */ + IC_EVEX_L2_W_KZ_B, /* 14152 */ + IC_EVEX_L2_W_KZ_B, /* 14153 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14154 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14155 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14156 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14157 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14158 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14159 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14160 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14161 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14162 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14163 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14164 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14165 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14166 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14167 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14168 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14169 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14170 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14171 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14172 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14173 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14174 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14175 */ + IC_EVEX_L2_KZ_B, /* 14176 */ + IC_EVEX_L2_KZ_B, /* 14177 */ + IC_EVEX_L2_XS_KZ_B, /* 14178 */ + IC_EVEX_L2_XS_KZ_B, /* 14179 */ + IC_EVEX_L2_XD_KZ_B, /* 14180 */ + IC_EVEX_L2_XD_KZ_B, /* 14181 */ + IC_EVEX_L2_XD_KZ_B, /* 14182 */ + IC_EVEX_L2_XD_KZ_B, /* 14183 */ + IC_EVEX_L2_W_KZ_B, /* 14184 */ + IC_EVEX_L2_W_KZ_B, /* 14185 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14186 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14187 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14188 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14189 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14190 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14191 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14192 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14193 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14194 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14195 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14196 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14197 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14198 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14199 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14200 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14201 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14202 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14203 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14204 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14205 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14206 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14207 */ + IC_EVEX_L2_KZ_B, /* 14208 */ + IC_EVEX_L2_KZ_B, /* 14209 */ + IC_EVEX_L2_XS_KZ_B, /* 14210 */ + IC_EVEX_L2_XS_KZ_B, /* 14211 */ + IC_EVEX_L2_XD_KZ_B, /* 14212 */ + IC_EVEX_L2_XD_KZ_B, /* 14213 */ + IC_EVEX_L2_XD_KZ_B, /* 14214 */ + IC_EVEX_L2_XD_KZ_B, /* 14215 */ + IC_EVEX_L2_W_KZ_B, /* 14216 */ + IC_EVEX_L2_W_KZ_B, /* 14217 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14218 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14219 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14220 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14221 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14222 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14223 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14224 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14225 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14226 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14227 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14228 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14229 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14230 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14231 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14232 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14233 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14234 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14235 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14236 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14237 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14238 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14239 */ + IC_EVEX_L2_KZ_B, /* 14240 */ + IC_EVEX_L2_KZ_B, /* 14241 */ + IC_EVEX_L2_XS_KZ_B, /* 14242 */ + IC_EVEX_L2_XS_KZ_B, /* 14243 */ + IC_EVEX_L2_XD_KZ_B, /* 14244 */ + IC_EVEX_L2_XD_KZ_B, /* 14245 */ + IC_EVEX_L2_XD_KZ_B, /* 14246 */ + IC_EVEX_L2_XD_KZ_B, /* 14247 */ + IC_EVEX_L2_W_KZ_B, /* 14248 */ + IC_EVEX_L2_W_KZ_B, /* 14249 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14250 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14251 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14252 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14253 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14254 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14255 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14256 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14257 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14258 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14259 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14260 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14261 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14262 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14263 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14264 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14265 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14266 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14267 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14268 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14269 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14270 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14271 */ + IC_EVEX_L2_KZ_B, /* 14272 */ + IC_EVEX_L2_KZ_B, /* 14273 */ + IC_EVEX_L2_XS_KZ_B, /* 14274 */ + IC_EVEX_L2_XS_KZ_B, /* 14275 */ + IC_EVEX_L2_XD_KZ_B, /* 14276 */ + IC_EVEX_L2_XD_KZ_B, /* 14277 */ + IC_EVEX_L2_XD_KZ_B, /* 14278 */ + IC_EVEX_L2_XD_KZ_B, /* 14279 */ + IC_EVEX_L2_W_KZ_B, /* 14280 */ + IC_EVEX_L2_W_KZ_B, /* 14281 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14282 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14283 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14284 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14285 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14286 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14287 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14288 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14289 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14290 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14291 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14292 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14293 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14294 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14295 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14296 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14297 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14298 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14299 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14300 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14301 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14302 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14303 */ + IC_EVEX_L2_KZ_B, /* 14304 */ + IC_EVEX_L2_KZ_B, /* 14305 */ + IC_EVEX_L2_XS_KZ_B, /* 14306 */ + IC_EVEX_L2_XS_KZ_B, /* 14307 */ + IC_EVEX_L2_XD_KZ_B, /* 14308 */ + IC_EVEX_L2_XD_KZ_B, /* 14309 */ + IC_EVEX_L2_XD_KZ_B, /* 14310 */ + IC_EVEX_L2_XD_KZ_B, /* 14311 */ + IC_EVEX_L2_W_KZ_B, /* 14312 */ + IC_EVEX_L2_W_KZ_B, /* 14313 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14314 */ + IC_EVEX_L2_W_XS_KZ_B, /* 14315 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14316 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14317 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14318 */ + IC_EVEX_L2_W_XD_KZ_B, /* 14319 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14320 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14321 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14322 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14323 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14324 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14325 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14326 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 14327 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14328 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14329 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14330 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14331 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14332 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14333 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14334 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14335 */ + IC, /* 14336 */ + IC_64BIT, /* 14337 */ + IC_XS, /* 14338 */ + IC_64BIT_XS, /* 14339 */ + IC_XD, /* 14340 */ + IC_64BIT_XD, /* 14341 */ + IC_XS, /* 14342 */ + IC_64BIT_XS, /* 14343 */ + IC, /* 14344 */ + IC_64BIT_REXW, /* 14345 */ + IC_XS, /* 14346 */ + IC_64BIT_REXW_XS, /* 14347 */ + IC_XD, /* 14348 */ + IC_64BIT_REXW_XD, /* 14349 */ + IC_XS, /* 14350 */ + IC_64BIT_REXW_XS, /* 14351 */ + IC_OPSIZE, /* 14352 */ + IC_64BIT_OPSIZE, /* 14353 */ + IC_XS_OPSIZE, /* 14354 */ + IC_64BIT_XS_OPSIZE, /* 14355 */ + IC_XD_OPSIZE, /* 14356 */ + IC_64BIT_XD_OPSIZE, /* 14357 */ + IC_XS_OPSIZE, /* 14358 */ + IC_64BIT_XD_OPSIZE, /* 14359 */ + IC_OPSIZE, /* 14360 */ + IC_64BIT_REXW_OPSIZE, /* 14361 */ + IC_XS_OPSIZE, /* 14362 */ + IC_64BIT_REXW_XS, /* 14363 */ + IC_XD_OPSIZE, /* 14364 */ + IC_64BIT_REXW_XD, /* 14365 */ + IC_XS_OPSIZE, /* 14366 */ + IC_64BIT_REXW_XS, /* 14367 */ + IC_ADSIZE, /* 14368 */ + IC_64BIT_ADSIZE, /* 14369 */ + IC_XS_ADSIZE, /* 14370 */ + IC_64BIT_XS_ADSIZE, /* 14371 */ + IC_XD_ADSIZE, /* 14372 */ + IC_64BIT_XD_ADSIZE, /* 14373 */ + IC_XS_ADSIZE, /* 14374 */ + IC_64BIT_XD_ADSIZE, /* 14375 */ + IC_ADSIZE, /* 14376 */ + IC_64BIT_REXW_ADSIZE, /* 14377 */ + IC_XS_ADSIZE, /* 14378 */ + IC_64BIT_REXW_XS, /* 14379 */ + IC_XD_ADSIZE, /* 14380 */ + IC_64BIT_REXW_XD, /* 14381 */ + IC_XS_ADSIZE, /* 14382 */ + IC_64BIT_REXW_XS, /* 14383 */ + IC_OPSIZE_ADSIZE, /* 14384 */ + IC_64BIT_OPSIZE_ADSIZE, /* 14385 */ + IC_XS_OPSIZE, /* 14386 */ + IC_64BIT_XS_OPSIZE, /* 14387 */ + IC_XD_OPSIZE, /* 14388 */ + IC_64BIT_XD_OPSIZE, /* 14389 */ + IC_XS_OPSIZE, /* 14390 */ + IC_64BIT_XD_OPSIZE, /* 14391 */ + IC_OPSIZE_ADSIZE, /* 14392 */ + IC_64BIT_REXW_OPSIZE, /* 14393 */ + IC_XS_OPSIZE, /* 14394 */ + IC_64BIT_REXW_XS, /* 14395 */ + IC_XD_OPSIZE, /* 14396 */ + IC_64BIT_REXW_XD, /* 14397 */ + IC_XS_OPSIZE, /* 14398 */ + IC_64BIT_REXW_XS, /* 14399 */ + IC_VEX, /* 14400 */ + IC_VEX, /* 14401 */ + IC_VEX_XS, /* 14402 */ + IC_VEX_XS, /* 14403 */ + IC_VEX_XD, /* 14404 */ + IC_VEX_XD, /* 14405 */ + IC_VEX_XD, /* 14406 */ + IC_VEX_XD, /* 14407 */ + IC_VEX_W, /* 14408 */ + IC_VEX_W, /* 14409 */ + IC_VEX_W_XS, /* 14410 */ + IC_VEX_W_XS, /* 14411 */ + IC_VEX_W_XD, /* 14412 */ + IC_VEX_W_XD, /* 14413 */ + IC_VEX_W_XD, /* 14414 */ + IC_VEX_W_XD, /* 14415 */ + IC_VEX_OPSIZE, /* 14416 */ + IC_VEX_OPSIZE, /* 14417 */ + IC_VEX_OPSIZE, /* 14418 */ + IC_VEX_OPSIZE, /* 14419 */ + IC_VEX_OPSIZE, /* 14420 */ + IC_VEX_OPSIZE, /* 14421 */ + IC_VEX_OPSIZE, /* 14422 */ + IC_VEX_OPSIZE, /* 14423 */ + IC_VEX_W_OPSIZE, /* 14424 */ + IC_VEX_W_OPSIZE, /* 14425 */ + IC_VEX_W_OPSIZE, /* 14426 */ + IC_VEX_W_OPSIZE, /* 14427 */ + IC_VEX_W_OPSIZE, /* 14428 */ + IC_VEX_W_OPSIZE, /* 14429 */ + IC_VEX_W_OPSIZE, /* 14430 */ + IC_VEX_W_OPSIZE, /* 14431 */ + IC_VEX, /* 14432 */ + IC_VEX, /* 14433 */ + IC_VEX_XS, /* 14434 */ + IC_VEX_XS, /* 14435 */ + IC_VEX_XD, /* 14436 */ + IC_VEX_XD, /* 14437 */ + IC_VEX_XD, /* 14438 */ + IC_VEX_XD, /* 14439 */ + IC_VEX_W, /* 14440 */ + IC_VEX_W, /* 14441 */ + IC_VEX_W_XS, /* 14442 */ + IC_VEX_W_XS, /* 14443 */ + IC_VEX_W_XD, /* 14444 */ + IC_VEX_W_XD, /* 14445 */ + IC_VEX_W_XD, /* 14446 */ + IC_VEX_W_XD, /* 14447 */ + IC_VEX_OPSIZE, /* 14448 */ + IC_VEX_OPSIZE, /* 14449 */ + IC_VEX_OPSIZE, /* 14450 */ + IC_VEX_OPSIZE, /* 14451 */ + IC_VEX_OPSIZE, /* 14452 */ + IC_VEX_OPSIZE, /* 14453 */ + IC_VEX_OPSIZE, /* 14454 */ + IC_VEX_OPSIZE, /* 14455 */ + IC_VEX_W_OPSIZE, /* 14456 */ + IC_VEX_W_OPSIZE, /* 14457 */ + IC_VEX_W_OPSIZE, /* 14458 */ + IC_VEX_W_OPSIZE, /* 14459 */ + IC_VEX_W_OPSIZE, /* 14460 */ + IC_VEX_W_OPSIZE, /* 14461 */ + IC_VEX_W_OPSIZE, /* 14462 */ + IC_VEX_W_OPSIZE, /* 14463 */ + IC_VEX_L, /* 14464 */ + IC_VEX_L, /* 14465 */ + IC_VEX_L_XS, /* 14466 */ + IC_VEX_L_XS, /* 14467 */ + IC_VEX_L_XD, /* 14468 */ + IC_VEX_L_XD, /* 14469 */ + IC_VEX_L_XD, /* 14470 */ + IC_VEX_L_XD, /* 14471 */ + IC_VEX_L_W, /* 14472 */ + IC_VEX_L_W, /* 14473 */ + IC_VEX_L_W_XS, /* 14474 */ + IC_VEX_L_W_XS, /* 14475 */ + IC_VEX_L_W_XD, /* 14476 */ + IC_VEX_L_W_XD, /* 14477 */ + IC_VEX_L_W_XD, /* 14478 */ + IC_VEX_L_W_XD, /* 14479 */ + IC_VEX_L_OPSIZE, /* 14480 */ + IC_VEX_L_OPSIZE, /* 14481 */ + IC_VEX_L_OPSIZE, /* 14482 */ + IC_VEX_L_OPSIZE, /* 14483 */ + IC_VEX_L_OPSIZE, /* 14484 */ + IC_VEX_L_OPSIZE, /* 14485 */ + IC_VEX_L_OPSIZE, /* 14486 */ + IC_VEX_L_OPSIZE, /* 14487 */ + IC_VEX_L_W_OPSIZE, /* 14488 */ + IC_VEX_L_W_OPSIZE, /* 14489 */ + IC_VEX_L_W_OPSIZE, /* 14490 */ + IC_VEX_L_W_OPSIZE, /* 14491 */ + IC_VEX_L_W_OPSIZE, /* 14492 */ + IC_VEX_L_W_OPSIZE, /* 14493 */ + IC_VEX_L_W_OPSIZE, /* 14494 */ + IC_VEX_L_W_OPSIZE, /* 14495 */ + IC_VEX_L, /* 14496 */ + IC_VEX_L, /* 14497 */ + IC_VEX_L_XS, /* 14498 */ + IC_VEX_L_XS, /* 14499 */ + IC_VEX_L_XD, /* 14500 */ + IC_VEX_L_XD, /* 14501 */ + IC_VEX_L_XD, /* 14502 */ + IC_VEX_L_XD, /* 14503 */ + IC_VEX_L_W, /* 14504 */ + IC_VEX_L_W, /* 14505 */ + IC_VEX_L_W_XS, /* 14506 */ + IC_VEX_L_W_XS, /* 14507 */ + IC_VEX_L_W_XD, /* 14508 */ + IC_VEX_L_W_XD, /* 14509 */ + IC_VEX_L_W_XD, /* 14510 */ + IC_VEX_L_W_XD, /* 14511 */ + IC_VEX_L_OPSIZE, /* 14512 */ + IC_VEX_L_OPSIZE, /* 14513 */ + IC_VEX_L_OPSIZE, /* 14514 */ + IC_VEX_L_OPSIZE, /* 14515 */ + IC_VEX_L_OPSIZE, /* 14516 */ + IC_VEX_L_OPSIZE, /* 14517 */ + IC_VEX_L_OPSIZE, /* 14518 */ + IC_VEX_L_OPSIZE, /* 14519 */ + IC_VEX_L_W_OPSIZE, /* 14520 */ + IC_VEX_L_W_OPSIZE, /* 14521 */ + IC_VEX_L_W_OPSIZE, /* 14522 */ + IC_VEX_L_W_OPSIZE, /* 14523 */ + IC_VEX_L_W_OPSIZE, /* 14524 */ + IC_VEX_L_W_OPSIZE, /* 14525 */ + IC_VEX_L_W_OPSIZE, /* 14526 */ + IC_VEX_L_W_OPSIZE, /* 14527 */ + IC_VEX_L, /* 14528 */ + IC_VEX_L, /* 14529 */ + IC_VEX_L_XS, /* 14530 */ + IC_VEX_L_XS, /* 14531 */ + IC_VEX_L_XD, /* 14532 */ + IC_VEX_L_XD, /* 14533 */ + IC_VEX_L_XD, /* 14534 */ + IC_VEX_L_XD, /* 14535 */ + IC_VEX_L_W, /* 14536 */ + IC_VEX_L_W, /* 14537 */ + IC_VEX_L_W_XS, /* 14538 */ + IC_VEX_L_W_XS, /* 14539 */ + IC_VEX_L_W_XD, /* 14540 */ + IC_VEX_L_W_XD, /* 14541 */ + IC_VEX_L_W_XD, /* 14542 */ + IC_VEX_L_W_XD, /* 14543 */ + IC_VEX_L_OPSIZE, /* 14544 */ + IC_VEX_L_OPSIZE, /* 14545 */ + IC_VEX_L_OPSIZE, /* 14546 */ + IC_VEX_L_OPSIZE, /* 14547 */ + IC_VEX_L_OPSIZE, /* 14548 */ + IC_VEX_L_OPSIZE, /* 14549 */ + IC_VEX_L_OPSIZE, /* 14550 */ + IC_VEX_L_OPSIZE, /* 14551 */ + IC_VEX_L_W_OPSIZE, /* 14552 */ + IC_VEX_L_W_OPSIZE, /* 14553 */ + IC_VEX_L_W_OPSIZE, /* 14554 */ + IC_VEX_L_W_OPSIZE, /* 14555 */ + IC_VEX_L_W_OPSIZE, /* 14556 */ + IC_VEX_L_W_OPSIZE, /* 14557 */ + IC_VEX_L_W_OPSIZE, /* 14558 */ + IC_VEX_L_W_OPSIZE, /* 14559 */ + IC_VEX_L, /* 14560 */ + IC_VEX_L, /* 14561 */ + IC_VEX_L_XS, /* 14562 */ + IC_VEX_L_XS, /* 14563 */ + IC_VEX_L_XD, /* 14564 */ + IC_VEX_L_XD, /* 14565 */ + IC_VEX_L_XD, /* 14566 */ + IC_VEX_L_XD, /* 14567 */ + IC_VEX_L_W, /* 14568 */ + IC_VEX_L_W, /* 14569 */ + IC_VEX_L_W_XS, /* 14570 */ + IC_VEX_L_W_XS, /* 14571 */ + IC_VEX_L_W_XD, /* 14572 */ + IC_VEX_L_W_XD, /* 14573 */ + IC_VEX_L_W_XD, /* 14574 */ + IC_VEX_L_W_XD, /* 14575 */ + IC_VEX_L_OPSIZE, /* 14576 */ + IC_VEX_L_OPSIZE, /* 14577 */ + IC_VEX_L_OPSIZE, /* 14578 */ + IC_VEX_L_OPSIZE, /* 14579 */ + IC_VEX_L_OPSIZE, /* 14580 */ + IC_VEX_L_OPSIZE, /* 14581 */ + IC_VEX_L_OPSIZE, /* 14582 */ + IC_VEX_L_OPSIZE, /* 14583 */ + IC_VEX_L_W_OPSIZE, /* 14584 */ + IC_VEX_L_W_OPSIZE, /* 14585 */ + IC_VEX_L_W_OPSIZE, /* 14586 */ + IC_VEX_L_W_OPSIZE, /* 14587 */ + IC_VEX_L_W_OPSIZE, /* 14588 */ + IC_VEX_L_W_OPSIZE, /* 14589 */ + IC_VEX_L_W_OPSIZE, /* 14590 */ + IC_VEX_L_W_OPSIZE, /* 14591 */ + IC_EVEX_KZ_B, /* 14592 */ + IC_EVEX_KZ_B, /* 14593 */ + IC_EVEX_XS_KZ_B, /* 14594 */ + IC_EVEX_XS_KZ_B, /* 14595 */ + IC_EVEX_XD_KZ_B, /* 14596 */ + IC_EVEX_XD_KZ_B, /* 14597 */ + IC_EVEX_XD_KZ_B, /* 14598 */ + IC_EVEX_XD_KZ_B, /* 14599 */ + IC_EVEX_W_KZ_B, /* 14600 */ + IC_EVEX_W_KZ_B, /* 14601 */ + IC_EVEX_W_XS_KZ_B, /* 14602 */ + IC_EVEX_W_XS_KZ_B, /* 14603 */ + IC_EVEX_W_XD_KZ_B, /* 14604 */ + IC_EVEX_W_XD_KZ_B, /* 14605 */ + IC_EVEX_W_XD_KZ_B, /* 14606 */ + IC_EVEX_W_XD_KZ_B, /* 14607 */ + IC_EVEX_OPSIZE_KZ_B, /* 14608 */ + IC_EVEX_OPSIZE_KZ_B, /* 14609 */ + IC_EVEX_OPSIZE_KZ_B, /* 14610 */ + IC_EVEX_OPSIZE_KZ_B, /* 14611 */ + IC_EVEX_OPSIZE_KZ_B, /* 14612 */ + IC_EVEX_OPSIZE_KZ_B, /* 14613 */ + IC_EVEX_OPSIZE_KZ_B, /* 14614 */ + IC_EVEX_OPSIZE_KZ_B, /* 14615 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14616 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14617 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14618 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14619 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14620 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14621 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14622 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14623 */ + IC_EVEX_KZ_B, /* 14624 */ + IC_EVEX_KZ_B, /* 14625 */ + IC_EVEX_XS_KZ_B, /* 14626 */ + IC_EVEX_XS_KZ_B, /* 14627 */ + IC_EVEX_XD_KZ_B, /* 14628 */ + IC_EVEX_XD_KZ_B, /* 14629 */ + IC_EVEX_XD_KZ_B, /* 14630 */ + IC_EVEX_XD_KZ_B, /* 14631 */ + IC_EVEX_W_KZ_B, /* 14632 */ + IC_EVEX_W_KZ_B, /* 14633 */ + IC_EVEX_W_XS_KZ_B, /* 14634 */ + IC_EVEX_W_XS_KZ_B, /* 14635 */ + IC_EVEX_W_XD_KZ_B, /* 14636 */ + IC_EVEX_W_XD_KZ_B, /* 14637 */ + IC_EVEX_W_XD_KZ_B, /* 14638 */ + IC_EVEX_W_XD_KZ_B, /* 14639 */ + IC_EVEX_OPSIZE_KZ_B, /* 14640 */ + IC_EVEX_OPSIZE_KZ_B, /* 14641 */ + IC_EVEX_OPSIZE_KZ_B, /* 14642 */ + IC_EVEX_OPSIZE_KZ_B, /* 14643 */ + IC_EVEX_OPSIZE_KZ_B, /* 14644 */ + IC_EVEX_OPSIZE_KZ_B, /* 14645 */ + IC_EVEX_OPSIZE_KZ_B, /* 14646 */ + IC_EVEX_OPSIZE_KZ_B, /* 14647 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14648 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14649 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14650 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14651 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14652 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14653 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14654 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14655 */ + IC_EVEX_KZ_B, /* 14656 */ + IC_EVEX_KZ_B, /* 14657 */ + IC_EVEX_XS_KZ_B, /* 14658 */ + IC_EVEX_XS_KZ_B, /* 14659 */ + IC_EVEX_XD_KZ_B, /* 14660 */ + IC_EVEX_XD_KZ_B, /* 14661 */ + IC_EVEX_XD_KZ_B, /* 14662 */ + IC_EVEX_XD_KZ_B, /* 14663 */ + IC_EVEX_W_KZ_B, /* 14664 */ + IC_EVEX_W_KZ_B, /* 14665 */ + IC_EVEX_W_XS_KZ_B, /* 14666 */ + IC_EVEX_W_XS_KZ_B, /* 14667 */ + IC_EVEX_W_XD_KZ_B, /* 14668 */ + IC_EVEX_W_XD_KZ_B, /* 14669 */ + IC_EVEX_W_XD_KZ_B, /* 14670 */ + IC_EVEX_W_XD_KZ_B, /* 14671 */ + IC_EVEX_OPSIZE_KZ_B, /* 14672 */ + IC_EVEX_OPSIZE_KZ_B, /* 14673 */ + IC_EVEX_OPSIZE_KZ_B, /* 14674 */ + IC_EVEX_OPSIZE_KZ_B, /* 14675 */ + IC_EVEX_OPSIZE_KZ_B, /* 14676 */ + IC_EVEX_OPSIZE_KZ_B, /* 14677 */ + IC_EVEX_OPSIZE_KZ_B, /* 14678 */ + IC_EVEX_OPSIZE_KZ_B, /* 14679 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14680 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14681 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14682 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14683 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14684 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14685 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14686 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14687 */ + IC_EVEX_KZ_B, /* 14688 */ + IC_EVEX_KZ_B, /* 14689 */ + IC_EVEX_XS_KZ_B, /* 14690 */ + IC_EVEX_XS_KZ_B, /* 14691 */ + IC_EVEX_XD_KZ_B, /* 14692 */ + IC_EVEX_XD_KZ_B, /* 14693 */ + IC_EVEX_XD_KZ_B, /* 14694 */ + IC_EVEX_XD_KZ_B, /* 14695 */ + IC_EVEX_W_KZ_B, /* 14696 */ + IC_EVEX_W_KZ_B, /* 14697 */ + IC_EVEX_W_XS_KZ_B, /* 14698 */ + IC_EVEX_W_XS_KZ_B, /* 14699 */ + IC_EVEX_W_XD_KZ_B, /* 14700 */ + IC_EVEX_W_XD_KZ_B, /* 14701 */ + IC_EVEX_W_XD_KZ_B, /* 14702 */ + IC_EVEX_W_XD_KZ_B, /* 14703 */ + IC_EVEX_OPSIZE_KZ_B, /* 14704 */ + IC_EVEX_OPSIZE_KZ_B, /* 14705 */ + IC_EVEX_OPSIZE_KZ_B, /* 14706 */ + IC_EVEX_OPSIZE_KZ_B, /* 14707 */ + IC_EVEX_OPSIZE_KZ_B, /* 14708 */ + IC_EVEX_OPSIZE_KZ_B, /* 14709 */ + IC_EVEX_OPSIZE_KZ_B, /* 14710 */ + IC_EVEX_OPSIZE_KZ_B, /* 14711 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14712 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14713 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14714 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14715 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14716 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14717 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14718 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14719 */ + IC_EVEX_KZ_B, /* 14720 */ + IC_EVEX_KZ_B, /* 14721 */ + IC_EVEX_XS_KZ_B, /* 14722 */ + IC_EVEX_XS_KZ_B, /* 14723 */ + IC_EVEX_XD_KZ_B, /* 14724 */ + IC_EVEX_XD_KZ_B, /* 14725 */ + IC_EVEX_XD_KZ_B, /* 14726 */ + IC_EVEX_XD_KZ_B, /* 14727 */ + IC_EVEX_W_KZ_B, /* 14728 */ + IC_EVEX_W_KZ_B, /* 14729 */ + IC_EVEX_W_XS_KZ_B, /* 14730 */ + IC_EVEX_W_XS_KZ_B, /* 14731 */ + IC_EVEX_W_XD_KZ_B, /* 14732 */ + IC_EVEX_W_XD_KZ_B, /* 14733 */ + IC_EVEX_W_XD_KZ_B, /* 14734 */ + IC_EVEX_W_XD_KZ_B, /* 14735 */ + IC_EVEX_OPSIZE_KZ_B, /* 14736 */ + IC_EVEX_OPSIZE_KZ_B, /* 14737 */ + IC_EVEX_OPSIZE_KZ_B, /* 14738 */ + IC_EVEX_OPSIZE_KZ_B, /* 14739 */ + IC_EVEX_OPSIZE_KZ_B, /* 14740 */ + IC_EVEX_OPSIZE_KZ_B, /* 14741 */ + IC_EVEX_OPSIZE_KZ_B, /* 14742 */ + IC_EVEX_OPSIZE_KZ_B, /* 14743 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14744 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14745 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14746 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14747 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14748 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14749 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14750 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14751 */ + IC_EVEX_KZ_B, /* 14752 */ + IC_EVEX_KZ_B, /* 14753 */ + IC_EVEX_XS_KZ_B, /* 14754 */ + IC_EVEX_XS_KZ_B, /* 14755 */ + IC_EVEX_XD_KZ_B, /* 14756 */ + IC_EVEX_XD_KZ_B, /* 14757 */ + IC_EVEX_XD_KZ_B, /* 14758 */ + IC_EVEX_XD_KZ_B, /* 14759 */ + IC_EVEX_W_KZ_B, /* 14760 */ + IC_EVEX_W_KZ_B, /* 14761 */ + IC_EVEX_W_XS_KZ_B, /* 14762 */ + IC_EVEX_W_XS_KZ_B, /* 14763 */ + IC_EVEX_W_XD_KZ_B, /* 14764 */ + IC_EVEX_W_XD_KZ_B, /* 14765 */ + IC_EVEX_W_XD_KZ_B, /* 14766 */ + IC_EVEX_W_XD_KZ_B, /* 14767 */ + IC_EVEX_OPSIZE_KZ_B, /* 14768 */ + IC_EVEX_OPSIZE_KZ_B, /* 14769 */ + IC_EVEX_OPSIZE_KZ_B, /* 14770 */ + IC_EVEX_OPSIZE_KZ_B, /* 14771 */ + IC_EVEX_OPSIZE_KZ_B, /* 14772 */ + IC_EVEX_OPSIZE_KZ_B, /* 14773 */ + IC_EVEX_OPSIZE_KZ_B, /* 14774 */ + IC_EVEX_OPSIZE_KZ_B, /* 14775 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14776 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14777 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14778 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14779 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14780 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14781 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14782 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14783 */ + IC_EVEX_KZ_B, /* 14784 */ + IC_EVEX_KZ_B, /* 14785 */ + IC_EVEX_XS_KZ_B, /* 14786 */ + IC_EVEX_XS_KZ_B, /* 14787 */ + IC_EVEX_XD_KZ_B, /* 14788 */ + IC_EVEX_XD_KZ_B, /* 14789 */ + IC_EVEX_XD_KZ_B, /* 14790 */ + IC_EVEX_XD_KZ_B, /* 14791 */ + IC_EVEX_W_KZ_B, /* 14792 */ + IC_EVEX_W_KZ_B, /* 14793 */ + IC_EVEX_W_XS_KZ_B, /* 14794 */ + IC_EVEX_W_XS_KZ_B, /* 14795 */ + IC_EVEX_W_XD_KZ_B, /* 14796 */ + IC_EVEX_W_XD_KZ_B, /* 14797 */ + IC_EVEX_W_XD_KZ_B, /* 14798 */ + IC_EVEX_W_XD_KZ_B, /* 14799 */ + IC_EVEX_OPSIZE_KZ_B, /* 14800 */ + IC_EVEX_OPSIZE_KZ_B, /* 14801 */ + IC_EVEX_OPSIZE_KZ_B, /* 14802 */ + IC_EVEX_OPSIZE_KZ_B, /* 14803 */ + IC_EVEX_OPSIZE_KZ_B, /* 14804 */ + IC_EVEX_OPSIZE_KZ_B, /* 14805 */ + IC_EVEX_OPSIZE_KZ_B, /* 14806 */ + IC_EVEX_OPSIZE_KZ_B, /* 14807 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14808 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14809 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14810 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14811 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14812 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14813 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14814 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14815 */ + IC_EVEX_KZ_B, /* 14816 */ + IC_EVEX_KZ_B, /* 14817 */ + IC_EVEX_XS_KZ_B, /* 14818 */ + IC_EVEX_XS_KZ_B, /* 14819 */ + IC_EVEX_XD_KZ_B, /* 14820 */ + IC_EVEX_XD_KZ_B, /* 14821 */ + IC_EVEX_XD_KZ_B, /* 14822 */ + IC_EVEX_XD_KZ_B, /* 14823 */ + IC_EVEX_W_KZ_B, /* 14824 */ + IC_EVEX_W_KZ_B, /* 14825 */ + IC_EVEX_W_XS_KZ_B, /* 14826 */ + IC_EVEX_W_XS_KZ_B, /* 14827 */ + IC_EVEX_W_XD_KZ_B, /* 14828 */ + IC_EVEX_W_XD_KZ_B, /* 14829 */ + IC_EVEX_W_XD_KZ_B, /* 14830 */ + IC_EVEX_W_XD_KZ_B, /* 14831 */ + IC_EVEX_OPSIZE_KZ_B, /* 14832 */ + IC_EVEX_OPSIZE_KZ_B, /* 14833 */ + IC_EVEX_OPSIZE_KZ_B, /* 14834 */ + IC_EVEX_OPSIZE_KZ_B, /* 14835 */ + IC_EVEX_OPSIZE_KZ_B, /* 14836 */ + IC_EVEX_OPSIZE_KZ_B, /* 14837 */ + IC_EVEX_OPSIZE_KZ_B, /* 14838 */ + IC_EVEX_OPSIZE_KZ_B, /* 14839 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14840 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14841 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14842 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14843 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14844 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14845 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14846 */ + IC_EVEX_W_OPSIZE_KZ_B, /* 14847 */ + IC, /* 14848 */ + IC_64BIT, /* 14849 */ + IC_XS, /* 14850 */ + IC_64BIT_XS, /* 14851 */ + IC_XD, /* 14852 */ + IC_64BIT_XD, /* 14853 */ + IC_XS, /* 14854 */ + IC_64BIT_XS, /* 14855 */ + IC, /* 14856 */ + IC_64BIT_REXW, /* 14857 */ + IC_XS, /* 14858 */ + IC_64BIT_REXW_XS, /* 14859 */ + IC_XD, /* 14860 */ + IC_64BIT_REXW_XD, /* 14861 */ + IC_XS, /* 14862 */ + IC_64BIT_REXW_XS, /* 14863 */ + IC_OPSIZE, /* 14864 */ + IC_64BIT_OPSIZE, /* 14865 */ + IC_XS_OPSIZE, /* 14866 */ + IC_64BIT_XS_OPSIZE, /* 14867 */ + IC_XD_OPSIZE, /* 14868 */ + IC_64BIT_XD_OPSIZE, /* 14869 */ + IC_XS_OPSIZE, /* 14870 */ + IC_64BIT_XD_OPSIZE, /* 14871 */ + IC_OPSIZE, /* 14872 */ + IC_64BIT_REXW_OPSIZE, /* 14873 */ + IC_XS_OPSIZE, /* 14874 */ + IC_64BIT_REXW_XS, /* 14875 */ + IC_XD_OPSIZE, /* 14876 */ + IC_64BIT_REXW_XD, /* 14877 */ + IC_XS_OPSIZE, /* 14878 */ + IC_64BIT_REXW_XS, /* 14879 */ + IC_ADSIZE, /* 14880 */ + IC_64BIT_ADSIZE, /* 14881 */ + IC_XS_ADSIZE, /* 14882 */ + IC_64BIT_XS_ADSIZE, /* 14883 */ + IC_XD_ADSIZE, /* 14884 */ + IC_64BIT_XD_ADSIZE, /* 14885 */ + IC_XS_ADSIZE, /* 14886 */ + IC_64BIT_XD_ADSIZE, /* 14887 */ + IC_ADSIZE, /* 14888 */ + IC_64BIT_REXW_ADSIZE, /* 14889 */ + IC_XS_ADSIZE, /* 14890 */ + IC_64BIT_REXW_XS, /* 14891 */ + IC_XD_ADSIZE, /* 14892 */ + IC_64BIT_REXW_XD, /* 14893 */ + IC_XS_ADSIZE, /* 14894 */ + IC_64BIT_REXW_XS, /* 14895 */ + IC_OPSIZE_ADSIZE, /* 14896 */ + IC_64BIT_OPSIZE_ADSIZE, /* 14897 */ + IC_XS_OPSIZE, /* 14898 */ + IC_64BIT_XS_OPSIZE, /* 14899 */ + IC_XD_OPSIZE, /* 14900 */ + IC_64BIT_XD_OPSIZE, /* 14901 */ + IC_XS_OPSIZE, /* 14902 */ + IC_64BIT_XD_OPSIZE, /* 14903 */ + IC_OPSIZE_ADSIZE, /* 14904 */ + IC_64BIT_REXW_OPSIZE, /* 14905 */ + IC_XS_OPSIZE, /* 14906 */ + IC_64BIT_REXW_XS, /* 14907 */ + IC_XD_OPSIZE, /* 14908 */ + IC_64BIT_REXW_XD, /* 14909 */ + IC_XS_OPSIZE, /* 14910 */ + IC_64BIT_REXW_XS, /* 14911 */ + IC_VEX, /* 14912 */ + IC_VEX, /* 14913 */ + IC_VEX_XS, /* 14914 */ + IC_VEX_XS, /* 14915 */ + IC_VEX_XD, /* 14916 */ + IC_VEX_XD, /* 14917 */ + IC_VEX_XD, /* 14918 */ + IC_VEX_XD, /* 14919 */ + IC_VEX_W, /* 14920 */ + IC_VEX_W, /* 14921 */ + IC_VEX_W_XS, /* 14922 */ + IC_VEX_W_XS, /* 14923 */ + IC_VEX_W_XD, /* 14924 */ + IC_VEX_W_XD, /* 14925 */ + IC_VEX_W_XD, /* 14926 */ + IC_VEX_W_XD, /* 14927 */ + IC_VEX_OPSIZE, /* 14928 */ + IC_VEX_OPSIZE, /* 14929 */ + IC_VEX_OPSIZE, /* 14930 */ + IC_VEX_OPSIZE, /* 14931 */ + IC_VEX_OPSIZE, /* 14932 */ + IC_VEX_OPSIZE, /* 14933 */ + IC_VEX_OPSIZE, /* 14934 */ + IC_VEX_OPSIZE, /* 14935 */ + IC_VEX_W_OPSIZE, /* 14936 */ + IC_VEX_W_OPSIZE, /* 14937 */ + IC_VEX_W_OPSIZE, /* 14938 */ + IC_VEX_W_OPSIZE, /* 14939 */ + IC_VEX_W_OPSIZE, /* 14940 */ + IC_VEX_W_OPSIZE, /* 14941 */ + IC_VEX_W_OPSIZE, /* 14942 */ + IC_VEX_W_OPSIZE, /* 14943 */ + IC_VEX, /* 14944 */ + IC_VEX, /* 14945 */ + IC_VEX_XS, /* 14946 */ + IC_VEX_XS, /* 14947 */ + IC_VEX_XD, /* 14948 */ + IC_VEX_XD, /* 14949 */ + IC_VEX_XD, /* 14950 */ + IC_VEX_XD, /* 14951 */ + IC_VEX_W, /* 14952 */ + IC_VEX_W, /* 14953 */ + IC_VEX_W_XS, /* 14954 */ + IC_VEX_W_XS, /* 14955 */ + IC_VEX_W_XD, /* 14956 */ + IC_VEX_W_XD, /* 14957 */ + IC_VEX_W_XD, /* 14958 */ + IC_VEX_W_XD, /* 14959 */ + IC_VEX_OPSIZE, /* 14960 */ + IC_VEX_OPSIZE, /* 14961 */ + IC_VEX_OPSIZE, /* 14962 */ + IC_VEX_OPSIZE, /* 14963 */ + IC_VEX_OPSIZE, /* 14964 */ + IC_VEX_OPSIZE, /* 14965 */ + IC_VEX_OPSIZE, /* 14966 */ + IC_VEX_OPSIZE, /* 14967 */ + IC_VEX_W_OPSIZE, /* 14968 */ + IC_VEX_W_OPSIZE, /* 14969 */ + IC_VEX_W_OPSIZE, /* 14970 */ + IC_VEX_W_OPSIZE, /* 14971 */ + IC_VEX_W_OPSIZE, /* 14972 */ + IC_VEX_W_OPSIZE, /* 14973 */ + IC_VEX_W_OPSIZE, /* 14974 */ + IC_VEX_W_OPSIZE, /* 14975 */ + IC_VEX_L, /* 14976 */ + IC_VEX_L, /* 14977 */ + IC_VEX_L_XS, /* 14978 */ + IC_VEX_L_XS, /* 14979 */ + IC_VEX_L_XD, /* 14980 */ + IC_VEX_L_XD, /* 14981 */ + IC_VEX_L_XD, /* 14982 */ + IC_VEX_L_XD, /* 14983 */ + IC_VEX_L_W, /* 14984 */ + IC_VEX_L_W, /* 14985 */ + IC_VEX_L_W_XS, /* 14986 */ + IC_VEX_L_W_XS, /* 14987 */ + IC_VEX_L_W_XD, /* 14988 */ + IC_VEX_L_W_XD, /* 14989 */ + IC_VEX_L_W_XD, /* 14990 */ + IC_VEX_L_W_XD, /* 14991 */ + IC_VEX_L_OPSIZE, /* 14992 */ + IC_VEX_L_OPSIZE, /* 14993 */ + IC_VEX_L_OPSIZE, /* 14994 */ + IC_VEX_L_OPSIZE, /* 14995 */ + IC_VEX_L_OPSIZE, /* 14996 */ + IC_VEX_L_OPSIZE, /* 14997 */ + IC_VEX_L_OPSIZE, /* 14998 */ + IC_VEX_L_OPSIZE, /* 14999 */ + IC_VEX_L_W_OPSIZE, /* 15000 */ + IC_VEX_L_W_OPSIZE, /* 15001 */ + IC_VEX_L_W_OPSIZE, /* 15002 */ + IC_VEX_L_W_OPSIZE, /* 15003 */ + IC_VEX_L_W_OPSIZE, /* 15004 */ + IC_VEX_L_W_OPSIZE, /* 15005 */ + IC_VEX_L_W_OPSIZE, /* 15006 */ + IC_VEX_L_W_OPSIZE, /* 15007 */ + IC_VEX_L, /* 15008 */ + IC_VEX_L, /* 15009 */ + IC_VEX_L_XS, /* 15010 */ + IC_VEX_L_XS, /* 15011 */ + IC_VEX_L_XD, /* 15012 */ + IC_VEX_L_XD, /* 15013 */ + IC_VEX_L_XD, /* 15014 */ + IC_VEX_L_XD, /* 15015 */ + IC_VEX_L_W, /* 15016 */ + IC_VEX_L_W, /* 15017 */ + IC_VEX_L_W_XS, /* 15018 */ + IC_VEX_L_W_XS, /* 15019 */ + IC_VEX_L_W_XD, /* 15020 */ + IC_VEX_L_W_XD, /* 15021 */ + IC_VEX_L_W_XD, /* 15022 */ + IC_VEX_L_W_XD, /* 15023 */ + IC_VEX_L_OPSIZE, /* 15024 */ + IC_VEX_L_OPSIZE, /* 15025 */ + IC_VEX_L_OPSIZE, /* 15026 */ + IC_VEX_L_OPSIZE, /* 15027 */ + IC_VEX_L_OPSIZE, /* 15028 */ + IC_VEX_L_OPSIZE, /* 15029 */ + IC_VEX_L_OPSIZE, /* 15030 */ + IC_VEX_L_OPSIZE, /* 15031 */ + IC_VEX_L_W_OPSIZE, /* 15032 */ + IC_VEX_L_W_OPSIZE, /* 15033 */ + IC_VEX_L_W_OPSIZE, /* 15034 */ + IC_VEX_L_W_OPSIZE, /* 15035 */ + IC_VEX_L_W_OPSIZE, /* 15036 */ + IC_VEX_L_W_OPSIZE, /* 15037 */ + IC_VEX_L_W_OPSIZE, /* 15038 */ + IC_VEX_L_W_OPSIZE, /* 15039 */ + IC_VEX_L, /* 15040 */ + IC_VEX_L, /* 15041 */ + IC_VEX_L_XS, /* 15042 */ + IC_VEX_L_XS, /* 15043 */ + IC_VEX_L_XD, /* 15044 */ + IC_VEX_L_XD, /* 15045 */ + IC_VEX_L_XD, /* 15046 */ + IC_VEX_L_XD, /* 15047 */ + IC_VEX_L_W, /* 15048 */ + IC_VEX_L_W, /* 15049 */ + IC_VEX_L_W_XS, /* 15050 */ + IC_VEX_L_W_XS, /* 15051 */ + IC_VEX_L_W_XD, /* 15052 */ + IC_VEX_L_W_XD, /* 15053 */ + IC_VEX_L_W_XD, /* 15054 */ + IC_VEX_L_W_XD, /* 15055 */ + IC_VEX_L_OPSIZE, /* 15056 */ + IC_VEX_L_OPSIZE, /* 15057 */ + IC_VEX_L_OPSIZE, /* 15058 */ + IC_VEX_L_OPSIZE, /* 15059 */ + IC_VEX_L_OPSIZE, /* 15060 */ + IC_VEX_L_OPSIZE, /* 15061 */ + IC_VEX_L_OPSIZE, /* 15062 */ + IC_VEX_L_OPSIZE, /* 15063 */ + IC_VEX_L_W_OPSIZE, /* 15064 */ + IC_VEX_L_W_OPSIZE, /* 15065 */ + IC_VEX_L_W_OPSIZE, /* 15066 */ + IC_VEX_L_W_OPSIZE, /* 15067 */ + IC_VEX_L_W_OPSIZE, /* 15068 */ + IC_VEX_L_W_OPSIZE, /* 15069 */ + IC_VEX_L_W_OPSIZE, /* 15070 */ + IC_VEX_L_W_OPSIZE, /* 15071 */ + IC_VEX_L, /* 15072 */ + IC_VEX_L, /* 15073 */ + IC_VEX_L_XS, /* 15074 */ + IC_VEX_L_XS, /* 15075 */ + IC_VEX_L_XD, /* 15076 */ + IC_VEX_L_XD, /* 15077 */ + IC_VEX_L_XD, /* 15078 */ + IC_VEX_L_XD, /* 15079 */ + IC_VEX_L_W, /* 15080 */ + IC_VEX_L_W, /* 15081 */ + IC_VEX_L_W_XS, /* 15082 */ + IC_VEX_L_W_XS, /* 15083 */ + IC_VEX_L_W_XD, /* 15084 */ + IC_VEX_L_W_XD, /* 15085 */ + IC_VEX_L_W_XD, /* 15086 */ + IC_VEX_L_W_XD, /* 15087 */ + IC_VEX_L_OPSIZE, /* 15088 */ + IC_VEX_L_OPSIZE, /* 15089 */ + IC_VEX_L_OPSIZE, /* 15090 */ + IC_VEX_L_OPSIZE, /* 15091 */ + IC_VEX_L_OPSIZE, /* 15092 */ + IC_VEX_L_OPSIZE, /* 15093 */ + IC_VEX_L_OPSIZE, /* 15094 */ + IC_VEX_L_OPSIZE, /* 15095 */ + IC_VEX_L_W_OPSIZE, /* 15096 */ + IC_VEX_L_W_OPSIZE, /* 15097 */ + IC_VEX_L_W_OPSIZE, /* 15098 */ + IC_VEX_L_W_OPSIZE, /* 15099 */ + IC_VEX_L_W_OPSIZE, /* 15100 */ + IC_VEX_L_W_OPSIZE, /* 15101 */ + IC_VEX_L_W_OPSIZE, /* 15102 */ + IC_VEX_L_W_OPSIZE, /* 15103 */ + IC_EVEX_L_KZ_B, /* 15104 */ + IC_EVEX_L_KZ_B, /* 15105 */ + IC_EVEX_L_XS_KZ_B, /* 15106 */ + IC_EVEX_L_XS_KZ_B, /* 15107 */ + IC_EVEX_L_XD_KZ_B, /* 15108 */ + IC_EVEX_L_XD_KZ_B, /* 15109 */ + IC_EVEX_L_XD_KZ_B, /* 15110 */ + IC_EVEX_L_XD_KZ_B, /* 15111 */ + IC_EVEX_L_W_KZ_B, /* 15112 */ + IC_EVEX_L_W_KZ_B, /* 15113 */ + IC_EVEX_L_W_XS_KZ_B, /* 15114 */ + IC_EVEX_L_W_XS_KZ_B, /* 15115 */ + IC_EVEX_L_W_XD_KZ_B, /* 15116 */ + IC_EVEX_L_W_XD_KZ_B, /* 15117 */ + IC_EVEX_L_W_XD_KZ_B, /* 15118 */ + IC_EVEX_L_W_XD_KZ_B, /* 15119 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15120 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15121 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15122 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15123 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15124 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15125 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15126 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15127 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15128 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15129 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15130 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15131 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15132 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15133 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15134 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15135 */ + IC_EVEX_L_KZ_B, /* 15136 */ + IC_EVEX_L_KZ_B, /* 15137 */ + IC_EVEX_L_XS_KZ_B, /* 15138 */ + IC_EVEX_L_XS_KZ_B, /* 15139 */ + IC_EVEX_L_XD_KZ_B, /* 15140 */ + IC_EVEX_L_XD_KZ_B, /* 15141 */ + IC_EVEX_L_XD_KZ_B, /* 15142 */ + IC_EVEX_L_XD_KZ_B, /* 15143 */ + IC_EVEX_L_W_KZ_B, /* 15144 */ + IC_EVEX_L_W_KZ_B, /* 15145 */ + IC_EVEX_L_W_XS_KZ_B, /* 15146 */ + IC_EVEX_L_W_XS_KZ_B, /* 15147 */ + IC_EVEX_L_W_XD_KZ_B, /* 15148 */ + IC_EVEX_L_W_XD_KZ_B, /* 15149 */ + IC_EVEX_L_W_XD_KZ_B, /* 15150 */ + IC_EVEX_L_W_XD_KZ_B, /* 15151 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15152 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15153 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15154 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15155 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15156 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15157 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15158 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15159 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15160 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15161 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15162 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15163 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15164 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15165 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15166 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15167 */ + IC_EVEX_L_KZ_B, /* 15168 */ + IC_EVEX_L_KZ_B, /* 15169 */ + IC_EVEX_L_XS_KZ_B, /* 15170 */ + IC_EVEX_L_XS_KZ_B, /* 15171 */ + IC_EVEX_L_XD_KZ_B, /* 15172 */ + IC_EVEX_L_XD_KZ_B, /* 15173 */ + IC_EVEX_L_XD_KZ_B, /* 15174 */ + IC_EVEX_L_XD_KZ_B, /* 15175 */ + IC_EVEX_L_W_KZ_B, /* 15176 */ + IC_EVEX_L_W_KZ_B, /* 15177 */ + IC_EVEX_L_W_XS_KZ_B, /* 15178 */ + IC_EVEX_L_W_XS_KZ_B, /* 15179 */ + IC_EVEX_L_W_XD_KZ_B, /* 15180 */ + IC_EVEX_L_W_XD_KZ_B, /* 15181 */ + IC_EVEX_L_W_XD_KZ_B, /* 15182 */ + IC_EVEX_L_W_XD_KZ_B, /* 15183 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15184 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15185 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15186 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15187 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15188 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15189 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15190 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15191 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15192 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15193 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15194 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15195 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15196 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15197 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15198 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15199 */ + IC_EVEX_L_KZ_B, /* 15200 */ + IC_EVEX_L_KZ_B, /* 15201 */ + IC_EVEX_L_XS_KZ_B, /* 15202 */ + IC_EVEX_L_XS_KZ_B, /* 15203 */ + IC_EVEX_L_XD_KZ_B, /* 15204 */ + IC_EVEX_L_XD_KZ_B, /* 15205 */ + IC_EVEX_L_XD_KZ_B, /* 15206 */ + IC_EVEX_L_XD_KZ_B, /* 15207 */ + IC_EVEX_L_W_KZ_B, /* 15208 */ + IC_EVEX_L_W_KZ_B, /* 15209 */ + IC_EVEX_L_W_XS_KZ_B, /* 15210 */ + IC_EVEX_L_W_XS_KZ_B, /* 15211 */ + IC_EVEX_L_W_XD_KZ_B, /* 15212 */ + IC_EVEX_L_W_XD_KZ_B, /* 15213 */ + IC_EVEX_L_W_XD_KZ_B, /* 15214 */ + IC_EVEX_L_W_XD_KZ_B, /* 15215 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15216 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15217 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15218 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15219 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15220 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15221 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15222 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15223 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15224 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15225 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15226 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15227 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15228 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15229 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15230 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15231 */ + IC_EVEX_L_KZ_B, /* 15232 */ + IC_EVEX_L_KZ_B, /* 15233 */ + IC_EVEX_L_XS_KZ_B, /* 15234 */ + IC_EVEX_L_XS_KZ_B, /* 15235 */ + IC_EVEX_L_XD_KZ_B, /* 15236 */ + IC_EVEX_L_XD_KZ_B, /* 15237 */ + IC_EVEX_L_XD_KZ_B, /* 15238 */ + IC_EVEX_L_XD_KZ_B, /* 15239 */ + IC_EVEX_L_W_KZ_B, /* 15240 */ + IC_EVEX_L_W_KZ_B, /* 15241 */ + IC_EVEX_L_W_XS_KZ_B, /* 15242 */ + IC_EVEX_L_W_XS_KZ_B, /* 15243 */ + IC_EVEX_L_W_XD_KZ_B, /* 15244 */ + IC_EVEX_L_W_XD_KZ_B, /* 15245 */ + IC_EVEX_L_W_XD_KZ_B, /* 15246 */ + IC_EVEX_L_W_XD_KZ_B, /* 15247 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15248 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15249 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15250 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15251 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15252 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15253 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15254 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15255 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15256 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15257 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15258 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15259 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15260 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15261 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15262 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15263 */ + IC_EVEX_L_KZ_B, /* 15264 */ + IC_EVEX_L_KZ_B, /* 15265 */ + IC_EVEX_L_XS_KZ_B, /* 15266 */ + IC_EVEX_L_XS_KZ_B, /* 15267 */ + IC_EVEX_L_XD_KZ_B, /* 15268 */ + IC_EVEX_L_XD_KZ_B, /* 15269 */ + IC_EVEX_L_XD_KZ_B, /* 15270 */ + IC_EVEX_L_XD_KZ_B, /* 15271 */ + IC_EVEX_L_W_KZ_B, /* 15272 */ + IC_EVEX_L_W_KZ_B, /* 15273 */ + IC_EVEX_L_W_XS_KZ_B, /* 15274 */ + IC_EVEX_L_W_XS_KZ_B, /* 15275 */ + IC_EVEX_L_W_XD_KZ_B, /* 15276 */ + IC_EVEX_L_W_XD_KZ_B, /* 15277 */ + IC_EVEX_L_W_XD_KZ_B, /* 15278 */ + IC_EVEX_L_W_XD_KZ_B, /* 15279 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15280 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15281 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15282 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15283 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15284 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15285 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15286 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15287 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15288 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15289 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15290 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15291 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15292 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15293 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15294 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15295 */ + IC_EVEX_L_KZ_B, /* 15296 */ + IC_EVEX_L_KZ_B, /* 15297 */ + IC_EVEX_L_XS_KZ_B, /* 15298 */ + IC_EVEX_L_XS_KZ_B, /* 15299 */ + IC_EVEX_L_XD_KZ_B, /* 15300 */ + IC_EVEX_L_XD_KZ_B, /* 15301 */ + IC_EVEX_L_XD_KZ_B, /* 15302 */ + IC_EVEX_L_XD_KZ_B, /* 15303 */ + IC_EVEX_L_W_KZ_B, /* 15304 */ + IC_EVEX_L_W_KZ_B, /* 15305 */ + IC_EVEX_L_W_XS_KZ_B, /* 15306 */ + IC_EVEX_L_W_XS_KZ_B, /* 15307 */ + IC_EVEX_L_W_XD_KZ_B, /* 15308 */ + IC_EVEX_L_W_XD_KZ_B, /* 15309 */ + IC_EVEX_L_W_XD_KZ_B, /* 15310 */ + IC_EVEX_L_W_XD_KZ_B, /* 15311 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15312 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15313 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15314 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15315 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15316 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15317 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15318 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15319 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15320 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15321 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15322 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15323 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15324 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15325 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15326 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15327 */ + IC_EVEX_L_KZ_B, /* 15328 */ + IC_EVEX_L_KZ_B, /* 15329 */ + IC_EVEX_L_XS_KZ_B, /* 15330 */ + IC_EVEX_L_XS_KZ_B, /* 15331 */ + IC_EVEX_L_XD_KZ_B, /* 15332 */ + IC_EVEX_L_XD_KZ_B, /* 15333 */ + IC_EVEX_L_XD_KZ_B, /* 15334 */ + IC_EVEX_L_XD_KZ_B, /* 15335 */ + IC_EVEX_L_W_KZ_B, /* 15336 */ + IC_EVEX_L_W_KZ_B, /* 15337 */ + IC_EVEX_L_W_XS_KZ_B, /* 15338 */ + IC_EVEX_L_W_XS_KZ_B, /* 15339 */ + IC_EVEX_L_W_XD_KZ_B, /* 15340 */ + IC_EVEX_L_W_XD_KZ_B, /* 15341 */ + IC_EVEX_L_W_XD_KZ_B, /* 15342 */ + IC_EVEX_L_W_XD_KZ_B, /* 15343 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15344 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15345 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15346 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15347 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15348 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15349 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15350 */ + IC_EVEX_L_OPSIZE_KZ_B, /* 15351 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15352 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15353 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15354 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15355 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15356 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15357 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15358 */ + IC_EVEX_L_W_OPSIZE_KZ_B, /* 15359 */ + IC, /* 15360 */ + IC_64BIT, /* 15361 */ + IC_XS, /* 15362 */ + IC_64BIT_XS, /* 15363 */ + IC_XD, /* 15364 */ + IC_64BIT_XD, /* 15365 */ + IC_XS, /* 15366 */ + IC_64BIT_XS, /* 15367 */ + IC, /* 15368 */ + IC_64BIT_REXW, /* 15369 */ + IC_XS, /* 15370 */ + IC_64BIT_REXW_XS, /* 15371 */ + IC_XD, /* 15372 */ + IC_64BIT_REXW_XD, /* 15373 */ + IC_XS, /* 15374 */ + IC_64BIT_REXW_XS, /* 15375 */ + IC_OPSIZE, /* 15376 */ + IC_64BIT_OPSIZE, /* 15377 */ + IC_XS_OPSIZE, /* 15378 */ + IC_64BIT_XS_OPSIZE, /* 15379 */ + IC_XD_OPSIZE, /* 15380 */ + IC_64BIT_XD_OPSIZE, /* 15381 */ + IC_XS_OPSIZE, /* 15382 */ + IC_64BIT_XD_OPSIZE, /* 15383 */ + IC_OPSIZE, /* 15384 */ + IC_64BIT_REXW_OPSIZE, /* 15385 */ + IC_XS_OPSIZE, /* 15386 */ + IC_64BIT_REXW_XS, /* 15387 */ + IC_XD_OPSIZE, /* 15388 */ + IC_64BIT_REXW_XD, /* 15389 */ + IC_XS_OPSIZE, /* 15390 */ + IC_64BIT_REXW_XS, /* 15391 */ + IC_ADSIZE, /* 15392 */ + IC_64BIT_ADSIZE, /* 15393 */ + IC_XS_ADSIZE, /* 15394 */ + IC_64BIT_XS_ADSIZE, /* 15395 */ + IC_XD_ADSIZE, /* 15396 */ + IC_64BIT_XD_ADSIZE, /* 15397 */ + IC_XS_ADSIZE, /* 15398 */ + IC_64BIT_XD_ADSIZE, /* 15399 */ + IC_ADSIZE, /* 15400 */ + IC_64BIT_REXW_ADSIZE, /* 15401 */ + IC_XS_ADSIZE, /* 15402 */ + IC_64BIT_REXW_XS, /* 15403 */ + IC_XD_ADSIZE, /* 15404 */ + IC_64BIT_REXW_XD, /* 15405 */ + IC_XS_ADSIZE, /* 15406 */ + IC_64BIT_REXW_XS, /* 15407 */ + IC_OPSIZE_ADSIZE, /* 15408 */ + IC_64BIT_OPSIZE_ADSIZE, /* 15409 */ + IC_XS_OPSIZE, /* 15410 */ + IC_64BIT_XS_OPSIZE, /* 15411 */ + IC_XD_OPSIZE, /* 15412 */ + IC_64BIT_XD_OPSIZE, /* 15413 */ + IC_XS_OPSIZE, /* 15414 */ + IC_64BIT_XD_OPSIZE, /* 15415 */ + IC_OPSIZE_ADSIZE, /* 15416 */ + IC_64BIT_REXW_OPSIZE, /* 15417 */ + IC_XS_OPSIZE, /* 15418 */ + IC_64BIT_REXW_XS, /* 15419 */ + IC_XD_OPSIZE, /* 15420 */ + IC_64BIT_REXW_XD, /* 15421 */ + IC_XS_OPSIZE, /* 15422 */ + IC_64BIT_REXW_XS, /* 15423 */ + IC_VEX, /* 15424 */ + IC_VEX, /* 15425 */ + IC_VEX_XS, /* 15426 */ + IC_VEX_XS, /* 15427 */ + IC_VEX_XD, /* 15428 */ + IC_VEX_XD, /* 15429 */ + IC_VEX_XD, /* 15430 */ + IC_VEX_XD, /* 15431 */ + IC_VEX_W, /* 15432 */ + IC_VEX_W, /* 15433 */ + IC_VEX_W_XS, /* 15434 */ + IC_VEX_W_XS, /* 15435 */ + IC_VEX_W_XD, /* 15436 */ + IC_VEX_W_XD, /* 15437 */ + IC_VEX_W_XD, /* 15438 */ + IC_VEX_W_XD, /* 15439 */ + IC_VEX_OPSIZE, /* 15440 */ + IC_VEX_OPSIZE, /* 15441 */ + IC_VEX_OPSIZE, /* 15442 */ + IC_VEX_OPSIZE, /* 15443 */ + IC_VEX_OPSIZE, /* 15444 */ + IC_VEX_OPSIZE, /* 15445 */ + IC_VEX_OPSIZE, /* 15446 */ + IC_VEX_OPSIZE, /* 15447 */ + IC_VEX_W_OPSIZE, /* 15448 */ + IC_VEX_W_OPSIZE, /* 15449 */ + IC_VEX_W_OPSIZE, /* 15450 */ + IC_VEX_W_OPSIZE, /* 15451 */ + IC_VEX_W_OPSIZE, /* 15452 */ + IC_VEX_W_OPSIZE, /* 15453 */ + IC_VEX_W_OPSIZE, /* 15454 */ + IC_VEX_W_OPSIZE, /* 15455 */ + IC_VEX, /* 15456 */ + IC_VEX, /* 15457 */ + IC_VEX_XS, /* 15458 */ + IC_VEX_XS, /* 15459 */ + IC_VEX_XD, /* 15460 */ + IC_VEX_XD, /* 15461 */ + IC_VEX_XD, /* 15462 */ + IC_VEX_XD, /* 15463 */ + IC_VEX_W, /* 15464 */ + IC_VEX_W, /* 15465 */ + IC_VEX_W_XS, /* 15466 */ + IC_VEX_W_XS, /* 15467 */ + IC_VEX_W_XD, /* 15468 */ + IC_VEX_W_XD, /* 15469 */ + IC_VEX_W_XD, /* 15470 */ + IC_VEX_W_XD, /* 15471 */ + IC_VEX_OPSIZE, /* 15472 */ + IC_VEX_OPSIZE, /* 15473 */ + IC_VEX_OPSIZE, /* 15474 */ + IC_VEX_OPSIZE, /* 15475 */ + IC_VEX_OPSIZE, /* 15476 */ + IC_VEX_OPSIZE, /* 15477 */ + IC_VEX_OPSIZE, /* 15478 */ + IC_VEX_OPSIZE, /* 15479 */ + IC_VEX_W_OPSIZE, /* 15480 */ + IC_VEX_W_OPSIZE, /* 15481 */ + IC_VEX_W_OPSIZE, /* 15482 */ + IC_VEX_W_OPSIZE, /* 15483 */ + IC_VEX_W_OPSIZE, /* 15484 */ + IC_VEX_W_OPSIZE, /* 15485 */ + IC_VEX_W_OPSIZE, /* 15486 */ + IC_VEX_W_OPSIZE, /* 15487 */ + IC_VEX_L, /* 15488 */ + IC_VEX_L, /* 15489 */ + IC_VEX_L_XS, /* 15490 */ + IC_VEX_L_XS, /* 15491 */ + IC_VEX_L_XD, /* 15492 */ + IC_VEX_L_XD, /* 15493 */ + IC_VEX_L_XD, /* 15494 */ + IC_VEX_L_XD, /* 15495 */ + IC_VEX_L_W, /* 15496 */ + IC_VEX_L_W, /* 15497 */ + IC_VEX_L_W_XS, /* 15498 */ + IC_VEX_L_W_XS, /* 15499 */ + IC_VEX_L_W_XD, /* 15500 */ + IC_VEX_L_W_XD, /* 15501 */ + IC_VEX_L_W_XD, /* 15502 */ + IC_VEX_L_W_XD, /* 15503 */ + IC_VEX_L_OPSIZE, /* 15504 */ + IC_VEX_L_OPSIZE, /* 15505 */ + IC_VEX_L_OPSIZE, /* 15506 */ + IC_VEX_L_OPSIZE, /* 15507 */ + IC_VEX_L_OPSIZE, /* 15508 */ + IC_VEX_L_OPSIZE, /* 15509 */ + IC_VEX_L_OPSIZE, /* 15510 */ + IC_VEX_L_OPSIZE, /* 15511 */ + IC_VEX_L_W_OPSIZE, /* 15512 */ + IC_VEX_L_W_OPSIZE, /* 15513 */ + IC_VEX_L_W_OPSIZE, /* 15514 */ + IC_VEX_L_W_OPSIZE, /* 15515 */ + IC_VEX_L_W_OPSIZE, /* 15516 */ + IC_VEX_L_W_OPSIZE, /* 15517 */ + IC_VEX_L_W_OPSIZE, /* 15518 */ + IC_VEX_L_W_OPSIZE, /* 15519 */ + IC_VEX_L, /* 15520 */ + IC_VEX_L, /* 15521 */ + IC_VEX_L_XS, /* 15522 */ + IC_VEX_L_XS, /* 15523 */ + IC_VEX_L_XD, /* 15524 */ + IC_VEX_L_XD, /* 15525 */ + IC_VEX_L_XD, /* 15526 */ + IC_VEX_L_XD, /* 15527 */ + IC_VEX_L_W, /* 15528 */ + IC_VEX_L_W, /* 15529 */ + IC_VEX_L_W_XS, /* 15530 */ + IC_VEX_L_W_XS, /* 15531 */ + IC_VEX_L_W_XD, /* 15532 */ + IC_VEX_L_W_XD, /* 15533 */ + IC_VEX_L_W_XD, /* 15534 */ + IC_VEX_L_W_XD, /* 15535 */ + IC_VEX_L_OPSIZE, /* 15536 */ + IC_VEX_L_OPSIZE, /* 15537 */ + IC_VEX_L_OPSIZE, /* 15538 */ + IC_VEX_L_OPSIZE, /* 15539 */ + IC_VEX_L_OPSIZE, /* 15540 */ + IC_VEX_L_OPSIZE, /* 15541 */ + IC_VEX_L_OPSIZE, /* 15542 */ + IC_VEX_L_OPSIZE, /* 15543 */ + IC_VEX_L_W_OPSIZE, /* 15544 */ + IC_VEX_L_W_OPSIZE, /* 15545 */ + IC_VEX_L_W_OPSIZE, /* 15546 */ + IC_VEX_L_W_OPSIZE, /* 15547 */ + IC_VEX_L_W_OPSIZE, /* 15548 */ + IC_VEX_L_W_OPSIZE, /* 15549 */ + IC_VEX_L_W_OPSIZE, /* 15550 */ + IC_VEX_L_W_OPSIZE, /* 15551 */ + IC_VEX_L, /* 15552 */ + IC_VEX_L, /* 15553 */ + IC_VEX_L_XS, /* 15554 */ + IC_VEX_L_XS, /* 15555 */ + IC_VEX_L_XD, /* 15556 */ + IC_VEX_L_XD, /* 15557 */ + IC_VEX_L_XD, /* 15558 */ + IC_VEX_L_XD, /* 15559 */ + IC_VEX_L_W, /* 15560 */ + IC_VEX_L_W, /* 15561 */ + IC_VEX_L_W_XS, /* 15562 */ + IC_VEX_L_W_XS, /* 15563 */ + IC_VEX_L_W_XD, /* 15564 */ + IC_VEX_L_W_XD, /* 15565 */ + IC_VEX_L_W_XD, /* 15566 */ + IC_VEX_L_W_XD, /* 15567 */ + IC_VEX_L_OPSIZE, /* 15568 */ + IC_VEX_L_OPSIZE, /* 15569 */ + IC_VEX_L_OPSIZE, /* 15570 */ + IC_VEX_L_OPSIZE, /* 15571 */ + IC_VEX_L_OPSIZE, /* 15572 */ + IC_VEX_L_OPSIZE, /* 15573 */ + IC_VEX_L_OPSIZE, /* 15574 */ + IC_VEX_L_OPSIZE, /* 15575 */ + IC_VEX_L_W_OPSIZE, /* 15576 */ + IC_VEX_L_W_OPSIZE, /* 15577 */ + IC_VEX_L_W_OPSIZE, /* 15578 */ + IC_VEX_L_W_OPSIZE, /* 15579 */ + IC_VEX_L_W_OPSIZE, /* 15580 */ + IC_VEX_L_W_OPSIZE, /* 15581 */ + IC_VEX_L_W_OPSIZE, /* 15582 */ + IC_VEX_L_W_OPSIZE, /* 15583 */ + IC_VEX_L, /* 15584 */ + IC_VEX_L, /* 15585 */ + IC_VEX_L_XS, /* 15586 */ + IC_VEX_L_XS, /* 15587 */ + IC_VEX_L_XD, /* 15588 */ + IC_VEX_L_XD, /* 15589 */ + IC_VEX_L_XD, /* 15590 */ + IC_VEX_L_XD, /* 15591 */ + IC_VEX_L_W, /* 15592 */ + IC_VEX_L_W, /* 15593 */ + IC_VEX_L_W_XS, /* 15594 */ + IC_VEX_L_W_XS, /* 15595 */ + IC_VEX_L_W_XD, /* 15596 */ + IC_VEX_L_W_XD, /* 15597 */ + IC_VEX_L_W_XD, /* 15598 */ + IC_VEX_L_W_XD, /* 15599 */ + IC_VEX_L_OPSIZE, /* 15600 */ + IC_VEX_L_OPSIZE, /* 15601 */ + IC_VEX_L_OPSIZE, /* 15602 */ + IC_VEX_L_OPSIZE, /* 15603 */ + IC_VEX_L_OPSIZE, /* 15604 */ + IC_VEX_L_OPSIZE, /* 15605 */ + IC_VEX_L_OPSIZE, /* 15606 */ + IC_VEX_L_OPSIZE, /* 15607 */ + IC_VEX_L_W_OPSIZE, /* 15608 */ + IC_VEX_L_W_OPSIZE, /* 15609 */ + IC_VEX_L_W_OPSIZE, /* 15610 */ + IC_VEX_L_W_OPSIZE, /* 15611 */ + IC_VEX_L_W_OPSIZE, /* 15612 */ + IC_VEX_L_W_OPSIZE, /* 15613 */ + IC_VEX_L_W_OPSIZE, /* 15614 */ + IC_VEX_L_W_OPSIZE, /* 15615 */ + IC_EVEX_L2_KZ_B, /* 15616 */ + IC_EVEX_L2_KZ_B, /* 15617 */ + IC_EVEX_L2_XS_KZ_B, /* 15618 */ + IC_EVEX_L2_XS_KZ_B, /* 15619 */ + IC_EVEX_L2_XD_KZ_B, /* 15620 */ + IC_EVEX_L2_XD_KZ_B, /* 15621 */ + IC_EVEX_L2_XD_KZ_B, /* 15622 */ + IC_EVEX_L2_XD_KZ_B, /* 15623 */ + IC_EVEX_L2_W_KZ_B, /* 15624 */ + IC_EVEX_L2_W_KZ_B, /* 15625 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15626 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15627 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15628 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15629 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15630 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15631 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15632 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15633 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15634 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15635 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15636 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15637 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15638 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15639 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15640 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15641 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15642 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15643 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15644 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15645 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15646 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15647 */ + IC_EVEX_L2_KZ_B, /* 15648 */ + IC_EVEX_L2_KZ_B, /* 15649 */ + IC_EVEX_L2_XS_KZ_B, /* 15650 */ + IC_EVEX_L2_XS_KZ_B, /* 15651 */ + IC_EVEX_L2_XD_KZ_B, /* 15652 */ + IC_EVEX_L2_XD_KZ_B, /* 15653 */ + IC_EVEX_L2_XD_KZ_B, /* 15654 */ + IC_EVEX_L2_XD_KZ_B, /* 15655 */ + IC_EVEX_L2_W_KZ_B, /* 15656 */ + IC_EVEX_L2_W_KZ_B, /* 15657 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15658 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15659 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15660 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15661 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15662 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15663 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15664 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15665 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15666 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15667 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15668 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15669 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15670 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15671 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15672 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15673 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15674 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15675 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15676 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15677 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15678 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15679 */ + IC_EVEX_L2_KZ_B, /* 15680 */ + IC_EVEX_L2_KZ_B, /* 15681 */ + IC_EVEX_L2_XS_KZ_B, /* 15682 */ + IC_EVEX_L2_XS_KZ_B, /* 15683 */ + IC_EVEX_L2_XD_KZ_B, /* 15684 */ + IC_EVEX_L2_XD_KZ_B, /* 15685 */ + IC_EVEX_L2_XD_KZ_B, /* 15686 */ + IC_EVEX_L2_XD_KZ_B, /* 15687 */ + IC_EVEX_L2_W_KZ_B, /* 15688 */ + IC_EVEX_L2_W_KZ_B, /* 15689 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15690 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15691 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15692 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15693 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15694 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15695 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15696 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15697 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15698 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15699 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15700 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15701 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15702 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15703 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15704 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15705 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15706 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15707 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15708 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15709 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15710 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15711 */ + IC_EVEX_L2_KZ_B, /* 15712 */ + IC_EVEX_L2_KZ_B, /* 15713 */ + IC_EVEX_L2_XS_KZ_B, /* 15714 */ + IC_EVEX_L2_XS_KZ_B, /* 15715 */ + IC_EVEX_L2_XD_KZ_B, /* 15716 */ + IC_EVEX_L2_XD_KZ_B, /* 15717 */ + IC_EVEX_L2_XD_KZ_B, /* 15718 */ + IC_EVEX_L2_XD_KZ_B, /* 15719 */ + IC_EVEX_L2_W_KZ_B, /* 15720 */ + IC_EVEX_L2_W_KZ_B, /* 15721 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15722 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15723 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15724 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15725 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15726 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15727 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15728 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15729 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15730 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15731 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15732 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15733 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15734 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15735 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15736 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15737 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15738 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15739 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15740 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15741 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15742 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15743 */ + IC_EVEX_L2_KZ_B, /* 15744 */ + IC_EVEX_L2_KZ_B, /* 15745 */ + IC_EVEX_L2_XS_KZ_B, /* 15746 */ + IC_EVEX_L2_XS_KZ_B, /* 15747 */ + IC_EVEX_L2_XD_KZ_B, /* 15748 */ + IC_EVEX_L2_XD_KZ_B, /* 15749 */ + IC_EVEX_L2_XD_KZ_B, /* 15750 */ + IC_EVEX_L2_XD_KZ_B, /* 15751 */ + IC_EVEX_L2_W_KZ_B, /* 15752 */ + IC_EVEX_L2_W_KZ_B, /* 15753 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15754 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15755 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15756 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15757 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15758 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15759 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15760 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15761 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15762 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15763 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15764 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15765 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15766 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15767 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15768 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15769 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15770 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15771 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15772 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15773 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15774 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15775 */ + IC_EVEX_L2_KZ_B, /* 15776 */ + IC_EVEX_L2_KZ_B, /* 15777 */ + IC_EVEX_L2_XS_KZ_B, /* 15778 */ + IC_EVEX_L2_XS_KZ_B, /* 15779 */ + IC_EVEX_L2_XD_KZ_B, /* 15780 */ + IC_EVEX_L2_XD_KZ_B, /* 15781 */ + IC_EVEX_L2_XD_KZ_B, /* 15782 */ + IC_EVEX_L2_XD_KZ_B, /* 15783 */ + IC_EVEX_L2_W_KZ_B, /* 15784 */ + IC_EVEX_L2_W_KZ_B, /* 15785 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15786 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15787 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15788 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15789 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15790 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15791 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15792 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15793 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15794 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15795 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15796 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15797 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15798 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15799 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15800 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15801 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15802 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15803 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15804 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15805 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15806 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15807 */ + IC_EVEX_L2_KZ_B, /* 15808 */ + IC_EVEX_L2_KZ_B, /* 15809 */ + IC_EVEX_L2_XS_KZ_B, /* 15810 */ + IC_EVEX_L2_XS_KZ_B, /* 15811 */ + IC_EVEX_L2_XD_KZ_B, /* 15812 */ + IC_EVEX_L2_XD_KZ_B, /* 15813 */ + IC_EVEX_L2_XD_KZ_B, /* 15814 */ + IC_EVEX_L2_XD_KZ_B, /* 15815 */ + IC_EVEX_L2_W_KZ_B, /* 15816 */ + IC_EVEX_L2_W_KZ_B, /* 15817 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15818 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15819 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15820 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15821 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15822 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15823 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15824 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15825 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15826 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15827 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15828 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15829 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15830 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15831 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15832 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15833 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15834 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15835 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15836 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15837 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15838 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15839 */ + IC_EVEX_L2_KZ_B, /* 15840 */ + IC_EVEX_L2_KZ_B, /* 15841 */ + IC_EVEX_L2_XS_KZ_B, /* 15842 */ + IC_EVEX_L2_XS_KZ_B, /* 15843 */ + IC_EVEX_L2_XD_KZ_B, /* 15844 */ + IC_EVEX_L2_XD_KZ_B, /* 15845 */ + IC_EVEX_L2_XD_KZ_B, /* 15846 */ + IC_EVEX_L2_XD_KZ_B, /* 15847 */ + IC_EVEX_L2_W_KZ_B, /* 15848 */ + IC_EVEX_L2_W_KZ_B, /* 15849 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15850 */ + IC_EVEX_L2_W_XS_KZ_B, /* 15851 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15852 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15853 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15854 */ + IC_EVEX_L2_W_XD_KZ_B, /* 15855 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15856 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15857 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15858 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15859 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15860 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15861 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15862 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 15863 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15864 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15865 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15866 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15867 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15868 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15869 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15870 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15871 */ + IC, /* 15872 */ + IC_64BIT, /* 15873 */ + IC_XS, /* 15874 */ + IC_64BIT_XS, /* 15875 */ + IC_XD, /* 15876 */ + IC_64BIT_XD, /* 15877 */ + IC_XS, /* 15878 */ + IC_64BIT_XS, /* 15879 */ + IC, /* 15880 */ + IC_64BIT_REXW, /* 15881 */ + IC_XS, /* 15882 */ + IC_64BIT_REXW_XS, /* 15883 */ + IC_XD, /* 15884 */ + IC_64BIT_REXW_XD, /* 15885 */ + IC_XS, /* 15886 */ + IC_64BIT_REXW_XS, /* 15887 */ + IC_OPSIZE, /* 15888 */ + IC_64BIT_OPSIZE, /* 15889 */ + IC_XS_OPSIZE, /* 15890 */ + IC_64BIT_XS_OPSIZE, /* 15891 */ + IC_XD_OPSIZE, /* 15892 */ + IC_64BIT_XD_OPSIZE, /* 15893 */ + IC_XS_OPSIZE, /* 15894 */ + IC_64BIT_XD_OPSIZE, /* 15895 */ + IC_OPSIZE, /* 15896 */ + IC_64BIT_REXW_OPSIZE, /* 15897 */ + IC_XS_OPSIZE, /* 15898 */ + IC_64BIT_REXW_XS, /* 15899 */ + IC_XD_OPSIZE, /* 15900 */ + IC_64BIT_REXW_XD, /* 15901 */ + IC_XS_OPSIZE, /* 15902 */ + IC_64BIT_REXW_XS, /* 15903 */ + IC_ADSIZE, /* 15904 */ + IC_64BIT_ADSIZE, /* 15905 */ + IC_XS_ADSIZE, /* 15906 */ + IC_64BIT_XS_ADSIZE, /* 15907 */ + IC_XD_ADSIZE, /* 15908 */ + IC_64BIT_XD_ADSIZE, /* 15909 */ + IC_XS_ADSIZE, /* 15910 */ + IC_64BIT_XD_ADSIZE, /* 15911 */ + IC_ADSIZE, /* 15912 */ + IC_64BIT_REXW_ADSIZE, /* 15913 */ + IC_XS_ADSIZE, /* 15914 */ + IC_64BIT_REXW_XS, /* 15915 */ + IC_XD_ADSIZE, /* 15916 */ + IC_64BIT_REXW_XD, /* 15917 */ + IC_XS_ADSIZE, /* 15918 */ + IC_64BIT_REXW_XS, /* 15919 */ + IC_OPSIZE_ADSIZE, /* 15920 */ + IC_64BIT_OPSIZE_ADSIZE, /* 15921 */ + IC_XS_OPSIZE, /* 15922 */ + IC_64BIT_XS_OPSIZE, /* 15923 */ + IC_XD_OPSIZE, /* 15924 */ + IC_64BIT_XD_OPSIZE, /* 15925 */ + IC_XS_OPSIZE, /* 15926 */ + IC_64BIT_XD_OPSIZE, /* 15927 */ + IC_OPSIZE_ADSIZE, /* 15928 */ + IC_64BIT_REXW_OPSIZE, /* 15929 */ + IC_XS_OPSIZE, /* 15930 */ + IC_64BIT_REXW_XS, /* 15931 */ + IC_XD_OPSIZE, /* 15932 */ + IC_64BIT_REXW_XD, /* 15933 */ + IC_XS_OPSIZE, /* 15934 */ + IC_64BIT_REXW_XS, /* 15935 */ + IC_VEX, /* 15936 */ + IC_VEX, /* 15937 */ + IC_VEX_XS, /* 15938 */ + IC_VEX_XS, /* 15939 */ + IC_VEX_XD, /* 15940 */ + IC_VEX_XD, /* 15941 */ + IC_VEX_XD, /* 15942 */ + IC_VEX_XD, /* 15943 */ + IC_VEX_W, /* 15944 */ + IC_VEX_W, /* 15945 */ + IC_VEX_W_XS, /* 15946 */ + IC_VEX_W_XS, /* 15947 */ + IC_VEX_W_XD, /* 15948 */ + IC_VEX_W_XD, /* 15949 */ + IC_VEX_W_XD, /* 15950 */ + IC_VEX_W_XD, /* 15951 */ + IC_VEX_OPSIZE, /* 15952 */ + IC_VEX_OPSIZE, /* 15953 */ + IC_VEX_OPSIZE, /* 15954 */ + IC_VEX_OPSIZE, /* 15955 */ + IC_VEX_OPSIZE, /* 15956 */ + IC_VEX_OPSIZE, /* 15957 */ + IC_VEX_OPSIZE, /* 15958 */ + IC_VEX_OPSIZE, /* 15959 */ + IC_VEX_W_OPSIZE, /* 15960 */ + IC_VEX_W_OPSIZE, /* 15961 */ + IC_VEX_W_OPSIZE, /* 15962 */ + IC_VEX_W_OPSIZE, /* 15963 */ + IC_VEX_W_OPSIZE, /* 15964 */ + IC_VEX_W_OPSIZE, /* 15965 */ + IC_VEX_W_OPSIZE, /* 15966 */ + IC_VEX_W_OPSIZE, /* 15967 */ + IC_VEX, /* 15968 */ + IC_VEX, /* 15969 */ + IC_VEX_XS, /* 15970 */ + IC_VEX_XS, /* 15971 */ + IC_VEX_XD, /* 15972 */ + IC_VEX_XD, /* 15973 */ + IC_VEX_XD, /* 15974 */ + IC_VEX_XD, /* 15975 */ + IC_VEX_W, /* 15976 */ + IC_VEX_W, /* 15977 */ + IC_VEX_W_XS, /* 15978 */ + IC_VEX_W_XS, /* 15979 */ + IC_VEX_W_XD, /* 15980 */ + IC_VEX_W_XD, /* 15981 */ + IC_VEX_W_XD, /* 15982 */ + IC_VEX_W_XD, /* 15983 */ + IC_VEX_OPSIZE, /* 15984 */ + IC_VEX_OPSIZE, /* 15985 */ + IC_VEX_OPSIZE, /* 15986 */ + IC_VEX_OPSIZE, /* 15987 */ + IC_VEX_OPSIZE, /* 15988 */ + IC_VEX_OPSIZE, /* 15989 */ + IC_VEX_OPSIZE, /* 15990 */ + IC_VEX_OPSIZE, /* 15991 */ + IC_VEX_W_OPSIZE, /* 15992 */ + IC_VEX_W_OPSIZE, /* 15993 */ + IC_VEX_W_OPSIZE, /* 15994 */ + IC_VEX_W_OPSIZE, /* 15995 */ + IC_VEX_W_OPSIZE, /* 15996 */ + IC_VEX_W_OPSIZE, /* 15997 */ + IC_VEX_W_OPSIZE, /* 15998 */ + IC_VEX_W_OPSIZE, /* 15999 */ + IC_VEX_L, /* 16000 */ + IC_VEX_L, /* 16001 */ + IC_VEX_L_XS, /* 16002 */ + IC_VEX_L_XS, /* 16003 */ + IC_VEX_L_XD, /* 16004 */ + IC_VEX_L_XD, /* 16005 */ + IC_VEX_L_XD, /* 16006 */ + IC_VEX_L_XD, /* 16007 */ + IC_VEX_L_W, /* 16008 */ + IC_VEX_L_W, /* 16009 */ + IC_VEX_L_W_XS, /* 16010 */ + IC_VEX_L_W_XS, /* 16011 */ + IC_VEX_L_W_XD, /* 16012 */ + IC_VEX_L_W_XD, /* 16013 */ + IC_VEX_L_W_XD, /* 16014 */ + IC_VEX_L_W_XD, /* 16015 */ + IC_VEX_L_OPSIZE, /* 16016 */ + IC_VEX_L_OPSIZE, /* 16017 */ + IC_VEX_L_OPSIZE, /* 16018 */ + IC_VEX_L_OPSIZE, /* 16019 */ + IC_VEX_L_OPSIZE, /* 16020 */ + IC_VEX_L_OPSIZE, /* 16021 */ + IC_VEX_L_OPSIZE, /* 16022 */ + IC_VEX_L_OPSIZE, /* 16023 */ + IC_VEX_L_W_OPSIZE, /* 16024 */ + IC_VEX_L_W_OPSIZE, /* 16025 */ + IC_VEX_L_W_OPSIZE, /* 16026 */ + IC_VEX_L_W_OPSIZE, /* 16027 */ + IC_VEX_L_W_OPSIZE, /* 16028 */ + IC_VEX_L_W_OPSIZE, /* 16029 */ + IC_VEX_L_W_OPSIZE, /* 16030 */ + IC_VEX_L_W_OPSIZE, /* 16031 */ + IC_VEX_L, /* 16032 */ + IC_VEX_L, /* 16033 */ + IC_VEX_L_XS, /* 16034 */ + IC_VEX_L_XS, /* 16035 */ + IC_VEX_L_XD, /* 16036 */ + IC_VEX_L_XD, /* 16037 */ + IC_VEX_L_XD, /* 16038 */ + IC_VEX_L_XD, /* 16039 */ + IC_VEX_L_W, /* 16040 */ + IC_VEX_L_W, /* 16041 */ + IC_VEX_L_W_XS, /* 16042 */ + IC_VEX_L_W_XS, /* 16043 */ + IC_VEX_L_W_XD, /* 16044 */ + IC_VEX_L_W_XD, /* 16045 */ + IC_VEX_L_W_XD, /* 16046 */ + IC_VEX_L_W_XD, /* 16047 */ + IC_VEX_L_OPSIZE, /* 16048 */ + IC_VEX_L_OPSIZE, /* 16049 */ + IC_VEX_L_OPSIZE, /* 16050 */ + IC_VEX_L_OPSIZE, /* 16051 */ + IC_VEX_L_OPSIZE, /* 16052 */ + IC_VEX_L_OPSIZE, /* 16053 */ + IC_VEX_L_OPSIZE, /* 16054 */ + IC_VEX_L_OPSIZE, /* 16055 */ + IC_VEX_L_W_OPSIZE, /* 16056 */ + IC_VEX_L_W_OPSIZE, /* 16057 */ + IC_VEX_L_W_OPSIZE, /* 16058 */ + IC_VEX_L_W_OPSIZE, /* 16059 */ + IC_VEX_L_W_OPSIZE, /* 16060 */ + IC_VEX_L_W_OPSIZE, /* 16061 */ + IC_VEX_L_W_OPSIZE, /* 16062 */ + IC_VEX_L_W_OPSIZE, /* 16063 */ + IC_VEX_L, /* 16064 */ + IC_VEX_L, /* 16065 */ + IC_VEX_L_XS, /* 16066 */ + IC_VEX_L_XS, /* 16067 */ + IC_VEX_L_XD, /* 16068 */ + IC_VEX_L_XD, /* 16069 */ + IC_VEX_L_XD, /* 16070 */ + IC_VEX_L_XD, /* 16071 */ + IC_VEX_L_W, /* 16072 */ + IC_VEX_L_W, /* 16073 */ + IC_VEX_L_W_XS, /* 16074 */ + IC_VEX_L_W_XS, /* 16075 */ + IC_VEX_L_W_XD, /* 16076 */ + IC_VEX_L_W_XD, /* 16077 */ + IC_VEX_L_W_XD, /* 16078 */ + IC_VEX_L_W_XD, /* 16079 */ + IC_VEX_L_OPSIZE, /* 16080 */ + IC_VEX_L_OPSIZE, /* 16081 */ + IC_VEX_L_OPSIZE, /* 16082 */ + IC_VEX_L_OPSIZE, /* 16083 */ + IC_VEX_L_OPSIZE, /* 16084 */ + IC_VEX_L_OPSIZE, /* 16085 */ + IC_VEX_L_OPSIZE, /* 16086 */ + IC_VEX_L_OPSIZE, /* 16087 */ + IC_VEX_L_W_OPSIZE, /* 16088 */ + IC_VEX_L_W_OPSIZE, /* 16089 */ + IC_VEX_L_W_OPSIZE, /* 16090 */ + IC_VEX_L_W_OPSIZE, /* 16091 */ + IC_VEX_L_W_OPSIZE, /* 16092 */ + IC_VEX_L_W_OPSIZE, /* 16093 */ + IC_VEX_L_W_OPSIZE, /* 16094 */ + IC_VEX_L_W_OPSIZE, /* 16095 */ + IC_VEX_L, /* 16096 */ + IC_VEX_L, /* 16097 */ + IC_VEX_L_XS, /* 16098 */ + IC_VEX_L_XS, /* 16099 */ + IC_VEX_L_XD, /* 16100 */ + IC_VEX_L_XD, /* 16101 */ + IC_VEX_L_XD, /* 16102 */ + IC_VEX_L_XD, /* 16103 */ + IC_VEX_L_W, /* 16104 */ + IC_VEX_L_W, /* 16105 */ + IC_VEX_L_W_XS, /* 16106 */ + IC_VEX_L_W_XS, /* 16107 */ + IC_VEX_L_W_XD, /* 16108 */ + IC_VEX_L_W_XD, /* 16109 */ + IC_VEX_L_W_XD, /* 16110 */ + IC_VEX_L_W_XD, /* 16111 */ + IC_VEX_L_OPSIZE, /* 16112 */ + IC_VEX_L_OPSIZE, /* 16113 */ + IC_VEX_L_OPSIZE, /* 16114 */ + IC_VEX_L_OPSIZE, /* 16115 */ + IC_VEX_L_OPSIZE, /* 16116 */ + IC_VEX_L_OPSIZE, /* 16117 */ + IC_VEX_L_OPSIZE, /* 16118 */ + IC_VEX_L_OPSIZE, /* 16119 */ + IC_VEX_L_W_OPSIZE, /* 16120 */ + IC_VEX_L_W_OPSIZE, /* 16121 */ + IC_VEX_L_W_OPSIZE, /* 16122 */ + IC_VEX_L_W_OPSIZE, /* 16123 */ + IC_VEX_L_W_OPSIZE, /* 16124 */ + IC_VEX_L_W_OPSIZE, /* 16125 */ + IC_VEX_L_W_OPSIZE, /* 16126 */ + IC_VEX_L_W_OPSIZE, /* 16127 */ + IC_EVEX_L2_KZ_B, /* 16128 */ + IC_EVEX_L2_KZ_B, /* 16129 */ + IC_EVEX_L2_XS_KZ_B, /* 16130 */ + IC_EVEX_L2_XS_KZ_B, /* 16131 */ + IC_EVEX_L2_XD_KZ_B, /* 16132 */ + IC_EVEX_L2_XD_KZ_B, /* 16133 */ + IC_EVEX_L2_XD_KZ_B, /* 16134 */ + IC_EVEX_L2_XD_KZ_B, /* 16135 */ + IC_EVEX_L2_W_KZ_B, /* 16136 */ + IC_EVEX_L2_W_KZ_B, /* 16137 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16138 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16139 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16140 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16141 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16142 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16143 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16144 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16145 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16146 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16147 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16148 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16149 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16150 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16151 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16152 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16153 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16154 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16155 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16156 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16157 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16158 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16159 */ + IC_EVEX_L2_KZ_B, /* 16160 */ + IC_EVEX_L2_KZ_B, /* 16161 */ + IC_EVEX_L2_XS_KZ_B, /* 16162 */ + IC_EVEX_L2_XS_KZ_B, /* 16163 */ + IC_EVEX_L2_XD_KZ_B, /* 16164 */ + IC_EVEX_L2_XD_KZ_B, /* 16165 */ + IC_EVEX_L2_XD_KZ_B, /* 16166 */ + IC_EVEX_L2_XD_KZ_B, /* 16167 */ + IC_EVEX_L2_W_KZ_B, /* 16168 */ + IC_EVEX_L2_W_KZ_B, /* 16169 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16170 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16171 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16172 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16173 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16174 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16175 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16176 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16177 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16178 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16179 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16180 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16181 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16182 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16183 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16184 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16185 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16186 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16187 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16188 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16189 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16190 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16191 */ + IC_EVEX_L2_KZ_B, /* 16192 */ + IC_EVEX_L2_KZ_B, /* 16193 */ + IC_EVEX_L2_XS_KZ_B, /* 16194 */ + IC_EVEX_L2_XS_KZ_B, /* 16195 */ + IC_EVEX_L2_XD_KZ_B, /* 16196 */ + IC_EVEX_L2_XD_KZ_B, /* 16197 */ + IC_EVEX_L2_XD_KZ_B, /* 16198 */ + IC_EVEX_L2_XD_KZ_B, /* 16199 */ + IC_EVEX_L2_W_KZ_B, /* 16200 */ + IC_EVEX_L2_W_KZ_B, /* 16201 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16202 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16203 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16204 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16205 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16206 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16207 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16208 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16209 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16210 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16211 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16212 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16213 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16214 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16215 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16216 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16217 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16218 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16219 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16220 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16221 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16222 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16223 */ + IC_EVEX_L2_KZ_B, /* 16224 */ + IC_EVEX_L2_KZ_B, /* 16225 */ + IC_EVEX_L2_XS_KZ_B, /* 16226 */ + IC_EVEX_L2_XS_KZ_B, /* 16227 */ + IC_EVEX_L2_XD_KZ_B, /* 16228 */ + IC_EVEX_L2_XD_KZ_B, /* 16229 */ + IC_EVEX_L2_XD_KZ_B, /* 16230 */ + IC_EVEX_L2_XD_KZ_B, /* 16231 */ + IC_EVEX_L2_W_KZ_B, /* 16232 */ + IC_EVEX_L2_W_KZ_B, /* 16233 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16234 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16235 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16236 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16237 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16238 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16239 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16240 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16241 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16242 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16243 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16244 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16245 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16246 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16247 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16248 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16249 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16250 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16251 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16252 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16253 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16254 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16255 */ + IC_EVEX_L2_KZ_B, /* 16256 */ + IC_EVEX_L2_KZ_B, /* 16257 */ + IC_EVEX_L2_XS_KZ_B, /* 16258 */ + IC_EVEX_L2_XS_KZ_B, /* 16259 */ + IC_EVEX_L2_XD_KZ_B, /* 16260 */ + IC_EVEX_L2_XD_KZ_B, /* 16261 */ + IC_EVEX_L2_XD_KZ_B, /* 16262 */ + IC_EVEX_L2_XD_KZ_B, /* 16263 */ + IC_EVEX_L2_W_KZ_B, /* 16264 */ + IC_EVEX_L2_W_KZ_B, /* 16265 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16266 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16267 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16268 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16269 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16270 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16271 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16272 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16273 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16274 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16275 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16276 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16277 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16278 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16279 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16280 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16281 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16282 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16283 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16284 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16285 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16286 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16287 */ + IC_EVEX_L2_KZ_B, /* 16288 */ + IC_EVEX_L2_KZ_B, /* 16289 */ + IC_EVEX_L2_XS_KZ_B, /* 16290 */ + IC_EVEX_L2_XS_KZ_B, /* 16291 */ + IC_EVEX_L2_XD_KZ_B, /* 16292 */ + IC_EVEX_L2_XD_KZ_B, /* 16293 */ + IC_EVEX_L2_XD_KZ_B, /* 16294 */ + IC_EVEX_L2_XD_KZ_B, /* 16295 */ + IC_EVEX_L2_W_KZ_B, /* 16296 */ + IC_EVEX_L2_W_KZ_B, /* 16297 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16298 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16299 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16300 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16301 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16302 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16303 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16304 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16305 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16306 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16307 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16308 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16309 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16310 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16311 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16312 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16313 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16314 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16315 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16316 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16317 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16318 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16319 */ + IC_EVEX_L2_KZ_B, /* 16320 */ + IC_EVEX_L2_KZ_B, /* 16321 */ + IC_EVEX_L2_XS_KZ_B, /* 16322 */ + IC_EVEX_L2_XS_KZ_B, /* 16323 */ + IC_EVEX_L2_XD_KZ_B, /* 16324 */ + IC_EVEX_L2_XD_KZ_B, /* 16325 */ + IC_EVEX_L2_XD_KZ_B, /* 16326 */ + IC_EVEX_L2_XD_KZ_B, /* 16327 */ + IC_EVEX_L2_W_KZ_B, /* 16328 */ + IC_EVEX_L2_W_KZ_B, /* 16329 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16330 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16331 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16332 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16333 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16334 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16335 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16336 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16337 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16338 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16339 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16340 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16341 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16342 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16343 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16344 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16345 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16346 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16347 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16348 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16349 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16350 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16351 */ + IC_EVEX_L2_KZ_B, /* 16352 */ + IC_EVEX_L2_KZ_B, /* 16353 */ + IC_EVEX_L2_XS_KZ_B, /* 16354 */ + IC_EVEX_L2_XS_KZ_B, /* 16355 */ + IC_EVEX_L2_XD_KZ_B, /* 16356 */ + IC_EVEX_L2_XD_KZ_B, /* 16357 */ + IC_EVEX_L2_XD_KZ_B, /* 16358 */ + IC_EVEX_L2_XD_KZ_B, /* 16359 */ + IC_EVEX_L2_W_KZ_B, /* 16360 */ + IC_EVEX_L2_W_KZ_B, /* 16361 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16362 */ + IC_EVEX_L2_W_XS_KZ_B, /* 16363 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16364 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16365 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16366 */ + IC_EVEX_L2_W_XD_KZ_B, /* 16367 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16368 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16369 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16370 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16371 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16372 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16373 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16374 */ + IC_EVEX_L2_OPSIZE_KZ_B, /* 16375 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16376 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16377 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16378 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16379 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16380 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16381 */ + IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16382 */ + IC_EVEX_L2_W_OPSIZE_KZ_B /* 16383 */ +}; + +static const InstrUID modRMTable[] = { +/* EmptyTable */ + 0x0, +/* Table1 */ + 0xc8, /* ADD8mr */ + 0xcc, /* ADD8rr */ +/* Table3 */ + 0xb6, /* ADD32mr */ + 0xba, /* ADD32rr */ +/* Table5 */ + 0xcb, /* ADD8rm */ + 0xcd, /* ADD8rr_REV */ +/* Table7 */ + 0xb9, /* ADD32rm */ + 0xbb, /* ADD32rr_REV */ +/* Table9 */ + 0xc5, /* ADD8i8 */ +/* Table10 */ + 0xb3, /* ADD32i32 */ +/* Table11 */ + 0x436, /* PUSHES32 */ +/* Table12 */ + 0x412, /* POPES32 */ +/* Table13 */ + 0x3ec, /* OR8mr */ + 0x3f0, /* OR8rr */ +/* Table15 */ + 0x3da, /* OR32mr */ + 0x3de, /* OR32rr */ +/* Table17 */ + 0x3ef, /* OR8rm */ + 0x3f1, /* OR8rr_REV */ +/* Table19 */ + 0x3dd, /* OR32rm */ + 0x3df, /* OR32rr_REV */ +/* Table21 */ + 0x3e9, /* OR8i8 */ +/* Table22 */ + 0x3d7, /* OR32i32 */ +/* Table23 */ + 0x432, /* PUSHCS32 */ +/* Table24 */ + 0xa0, /* ADC8mr */ + 0xa4, /* ADC8rr */ +/* Table26 */ + 0x8e, /* ADC32mr */ + 0x92, /* ADC32rr */ +/* Table28 */ + 0xa3, /* ADC8rm */ + 0xa5, /* ADC8rr_REV */ +/* Table30 */ + 0x91, /* ADC32rm */ + 0x93, /* ADC32rr_REV */ +/* Table32 */ + 0x9d, /* ADC8i8 */ +/* Table33 */ + 0x8b, /* ADC32i32 */ +/* Table34 */ + 0x441, /* PUSHSS32 */ +/* Table35 */ + 0x41d, /* POPSS32 */ +/* Table36 */ + 0x51b, /* SBB8mr */ + 0x51f, /* SBB8rr */ +/* Table38 */ + 0x509, /* SBB32mr */ + 0x50d, /* SBB32rr */ +/* Table40 */ + 0x51e, /* SBB8rm */ + 0x520, /* SBB8rr_REV */ +/* Table42 */ + 0x50c, /* SBB32rm */ + 0x50e, /* SBB32rr_REV */ +/* Table44 */ + 0x518, /* SBB8i8 */ +/* Table45 */ + 0x506, /* SBB32i32 */ +/* Table46 */ + 0x434, /* PUSHDS32 */ +/* Table47 */ + 0x410, /* POPDS32 */ +/* Table48 */ + 0xf0, /* AND8mr */ + 0xf4, /* AND8rr */ +/* Table50 */ + 0xde, /* AND32mr */ + 0xe2, /* AND32rr */ +/* Table52 */ + 0xf3, /* AND8rm */ + 0xf5, /* AND8rr_REV */ +/* Table54 */ + 0xe1, /* AND32rm */ + 0xe3, /* AND32rr_REV */ +/* Table56 */ + 0xed, /* AND8i8 */ +/* Table57 */ + 0xdb, /* AND32i32 */ +/* Table58 */ + 0x225, /* DAA */ +/* Table59 */ + 0x5d2, /* SUB8mr */ + 0x5d6, /* SUB8rr */ +/* Table61 */ + 0x5c0, /* SUB32mr */ + 0x5c4, /* SUB32rr */ +/* Table63 */ + 0x5d5, /* SUB8rm */ + 0x5d7, /* SUB8rr_REV */ +/* Table65 */ + 0x5c3, /* SUB32rm */ + 0x5c5, /* SUB32rr_REV */ +/* Table67 */ + 0x5cf, /* SUB8i8 */ +/* Table68 */ + 0x5bd, /* SUB32i32 */ +/* Table69 */ + 0x226, /* DAS */ +/* Table70 */ + 0x671, /* XOR8mr */ + 0x675, /* XOR8rr */ +/* Table72 */ + 0x65f, /* XOR32mr */ + 0x663, /* XOR32rr */ +/* Table74 */ + 0x674, /* XOR8rm */ + 0x676, /* XOR8rr_REV */ +/* Table76 */ + 0x662, /* XOR32rm */ + 0x664, /* XOR32rr_REV */ +/* Table78 */ + 0x66e, /* XOR8i8 */ +/* Table79 */ + 0x65c, /* XOR32i32 */ +/* Table80 */ + 0x7e, /* AAA */ +/* Table81 */ + 0x20d, /* CMP8mr */ + 0x211, /* CMP8rr */ +/* Table83 */ + 0x1fb, /* CMP32mr */ + 0x1ff, /* CMP32rr */ +/* Table85 */ + 0x210, /* CMP8rm */ + 0x212, /* CMP8rr_REV */ +/* Table87 */ + 0x1fe, /* CMP32rm */ + 0x200, /* CMP32rr_REV */ +/* Table89 */ + 0x20a, /* CMP8i8 */ +/* Table90 */ + 0x1f8, /* CMP32i32 */ +/* Table91 */ + 0x81, /* AAS */ +/* Table92 */ + 0x277, /* INC32r_alt */ +/* Table93 */ + 0x22d, /* DEC32r_alt */ +/* Table94 */ + 0x427, /* PUSH32r */ +/* Table95 */ + 0x407, /* POP32r */ +/* Table96 */ + 0x430, /* PUSHA32 */ +/* Table97 */ + 0x40e, /* POPA32 */ +/* Table98 */ + 0x12d, /* BOUNDS32rm */ + 0x0, /* */ +/* Table100 */ + 0xfa, /* ARPL16mr */ + 0xfb, /* ARPL16rr */ +/* Table102 */ + 0x227, /* DATA16_PREFIX */ +/* Table103 */ + 0x443, /* PUSHi32 */ +/* Table104 */ + 0x25d, /* IMUL32rmi */ + 0x260, /* IMUL32rri */ +/* Table106 */ + 0x426, /* PUSH32i8 */ +/* Table107 */ + 0x25e, /* IMUL32rmi8 */ + 0x261, /* IMUL32rri8 */ +/* Table109 */ + 0x27e, /* INSB */ +/* Table110 */ + 0x27f, /* INSL */ +/* Table111 */ + 0x3f8, /* OUTSB */ +/* Table112 */ + 0x3f9, /* OUTSL */ +/* Table113 */ + 0x2ca, /* JO_1 */ +/* Table114 */ + 0x2c1, /* JNO_1 */ +/* Table115 */ + 0x29b, /* JB_1 */ +/* Table116 */ + 0x292, /* JAE_1 */ +/* Table117 */ + 0x2a0, /* JE_1 */ +/* Table118 */ + 0x2be, /* JNE_1 */ +/* Table119 */ + 0x298, /* JBE_1 */ +/* Table120 */ + 0x295, /* JA_1 */ +/* Table121 */ + 0x2d1, /* JS_1 */ +/* Table122 */ + 0x2c7, /* JNS_1 */ +/* Table123 */ + 0x2cd, /* JP_1 */ +/* Table124 */ + 0x2c4, /* JNP_1 */ +/* Table125 */ + 0x2ac, /* JL_1 */ +/* Table126 */ + 0x2a3, /* JGE_1 */ +/* Table127 */ + 0x2a9, /* JLE_1 */ +/* Table128 */ + 0x2a6, /* JG_1 */ +/* Table129 */ + 0xc6, /* ADD8mi */ + 0x3ea, /* OR8mi */ + 0x9e, /* ADC8mi */ + 0x519, /* SBB8mi */ + 0xee, /* AND8mi */ + 0x5d0, /* SUB8mi */ + 0x66f, /* XOR8mi */ + 0x20b, /* CMP8mi */ + 0xc9, /* ADD8ri */ + 0x3ed, /* OR8ri */ + 0xa1, /* ADC8ri */ + 0x51c, /* SBB8ri */ + 0xf1, /* AND8ri */ + 0x5d3, /* SUB8ri */ + 0x672, /* XOR8ri */ + 0x20e, /* CMP8ri */ +/* Table145 */ + 0xb4, /* ADD32mi */ + 0x3d8, /* OR32mi */ + 0x8c, /* ADC32mi */ + 0x507, /* SBB32mi */ + 0xdc, /* AND32mi */ + 0x5be, /* SUB32mi */ + 0x65d, /* XOR32mi */ + 0x1f9, /* CMP32mi */ + 0xb7, /* ADD32ri */ + 0x3db, /* OR32ri */ + 0x8f, /* ADC32ri */ + 0x50a, /* SBB32ri */ + 0xdf, /* AND32ri */ + 0x5c1, /* SUB32ri */ + 0x660, /* XOR32ri */ + 0x1fc, /* CMP32ri */ +/* Table161 */ + 0xc7, /* ADD8mi8 */ + 0x3eb, /* OR8mi8 */ + 0x9f, /* ADC8mi8 */ + 0x51a, /* SBB8mi8 */ + 0xef, /* AND8mi8 */ + 0x5d1, /* SUB8mi8 */ + 0x670, /* XOR8mi8 */ + 0x20c, /* CMP8mi8 */ + 0xca, /* ADD8ri8 */ + 0x3ee, /* OR8ri8 */ + 0xa2, /* ADC8ri8 */ + 0x51d, /* SBB8ri8 */ + 0xf2, /* AND8ri8 */ + 0x5d4, /* SUB8ri8 */ + 0x673, /* XOR8ri8 */ + 0x20f, /* CMP8ri8 */ +/* Table177 */ + 0xb5, /* ADD32mi8 */ + 0x3d9, /* OR32mi8 */ + 0x8d, /* ADC32mi8 */ + 0x508, /* SBB32mi8 */ + 0xdd, /* AND32mi8 */ + 0x5bf, /* SUB32mi8 */ + 0x65e, /* XOR32mi8 */ + 0x1fa, /* CMP32mi8 */ + 0xb8, /* ADD32ri8 */ + 0x3dc, /* OR32ri8 */ + 0x90, /* ADC32ri8 */ + 0x50b, /* SBB32ri8 */ + 0xe0, /* AND32ri8 */ + 0x5c2, /* SUB32ri8 */ + 0x661, /* XOR32ri8 */ + 0x1fd, /* CMP32ri8 */ +/* Table193 */ + 0x5fb, /* TEST8mr */ + 0x5fe, /* TEST8rr */ +/* Table195 */ + 0x5ed, /* TEST32mr */ + 0x5f0, /* TEST32rr */ +/* Table197 */ + 0x64a, /* XCHG8rm */ + 0x64b, /* XCHG8rr */ +/* Table199 */ + 0x645, /* XCHG32rm */ + 0x646, /* XCHG32rr */ +/* Table201 */ + 0x359, /* MOV8mr */ + 0x362, /* MOV8rr */ +/* Table203 */ + 0x337, /* MOV32mr */ + 0x340, /* MOV32rr */ +/* Table205 */ + 0x360, /* MOV8rm */ + 0x364, /* MOV8rr_REV */ +/* Table207 */ + 0x33f, /* MOV32rm */ + 0x341, /* MOV32rr_REV */ +/* Table209 */ + 0x325, /* MOV16ms */ + 0x342, /* MOV32rs */ +/* Table211 */ + 0x2de, /* LEA32r */ + 0x0, /* */ +/* Table213 */ + 0x32f, /* MOV16sm */ + 0x343, /* MOV32sr */ +/* Table215 */ + 0x408, /* POP32rmm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x409, /* POP32rmr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table231 */ + 0x3a7, /* NOOP */ +/* Table232 */ + 0x644, /* XCHG32ar */ +/* Table233 */ + 0x224, /* CWDE */ +/* Table234 */ + 0x181, /* CDQ */ +/* Table235 */ + 0x23f, /* FARCALL32i */ +/* Table236 */ + 0x438, /* PUSHF32 */ +/* Table237 */ + 0x414, /* POPF32 */ +/* Table238 */ + 0x4c6, /* SAHF */ +/* Table239 */ + 0x2d4, /* LAHF */ +/* Table240 */ + 0x356, /* MOV8ao32 */ +/* Table241 */ + 0x332, /* MOV32ao32 */ +/* Table242 */ + 0x35c, /* MOV8o32a */ +/* Table243 */ + 0x339, /* MOV32o32a */ +/* Table244 */ + 0x370, /* MOVSB */ +/* Table245 */ + 0x371, /* MOVSL */ +/* Table246 */ + 0x213, /* CMPSB */ +/* Table247 */ + 0x214, /* CMPSL */ +/* Table248 */ + 0x5f8, /* TEST8i8 */ +/* Table249 */ + 0x5ea, /* TEST32i32 */ +/* Table250 */ + 0x5ac, /* STOSB */ +/* Table251 */ + 0x5ad, /* STOSL */ +/* Table252 */ + 0x2f8, /* LODSB */ +/* Table253 */ + 0x2f9, /* LODSL */ +/* Table254 */ + 0x521, /* SCASB */ +/* Table255 */ + 0x522, /* SCASL */ +/* Table256 */ + 0x35e, /* MOV8ri */ +/* Table257 */ + 0x33d, /* MOV32ri */ +/* Table258 */ + 0x4a4, /* ROL8mi */ + 0x4bc, /* ROR8mi */ + 0x458, /* RCL8mi */ + 0x470, /* RCR8mi */ + 0x55d, /* SHL8mi */ + 0x585, /* SHR8mi */ + 0x4db, /* SAL8mi */ + 0x4f4, /* SAR8mi */ + 0x4a7, /* ROL8ri */ + 0x4bf, /* ROR8ri */ + 0x45b, /* RCL8ri */ + 0x473, /* RCR8ri */ + 0x560, /* SHL8ri */ + 0x588, /* SHR8ri */ + 0x4de, /* SAL8ri */ + 0x4f7, /* SAR8ri */ +/* Table274 */ + 0x498, /* ROL32mi */ + 0x4b0, /* ROR32mi */ + 0x44c, /* RCL32mi */ + 0x464, /* RCR32mi */ + 0x551, /* SHL32mi */ + 0x579, /* SHR32mi */ + 0x4cf, /* SAL32mi */ + 0x4e8, /* SAR32mi */ + 0x49b, /* ROL32ri */ + 0x4b3, /* ROR32ri */ + 0x44f, /* RCL32ri */ + 0x467, /* RCR32ri */ + 0x554, /* SHL32ri */ + 0x57c, /* SHR32ri */ + 0x4d2, /* SAL32ri */ + 0x4eb, /* SAR32ri */ +/* Table290 */ + 0x489, /* RETIL */ +/* Table291 */ + 0x48c, /* RETL */ +/* Table292 */ + 0x2e4, /* LES32rm */ + 0x0, /* */ +/* Table294 */ + 0x2dc, /* LDS32rm */ + 0x0, /* */ +/* Table296 */ + 0x358, /* MOV8mi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x35f, /* MOV8ri_alt */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table312 */ + 0x336, /* MOV32mi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x33e, /* MOV32ri_alt */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table328 */ + 0x23c, /* ENTER */ +/* Table329 */ + 0x2e1, /* LEAVE */ +/* Table330 */ + 0x2ff, /* LRETIL */ +/* Table331 */ + 0x302, /* LRETL */ +/* Table332 */ + 0x283, /* INT3 */ +/* Table333 */ + 0x281, /* INT */ +/* Table334 */ + 0x284, /* INTO */ +/* Table335 */ + 0x290, /* IRET32 */ +/* Table336 */ + 0x4a2, /* ROL8m1 */ + 0x4ba, /* ROR8m1 */ + 0x456, /* RCL8m1 */ + 0x46e, /* RCR8m1 */ + 0x55b, /* SHL8m1 */ + 0x583, /* SHR8m1 */ + 0x4d9, /* SAL8m1 */ + 0x4f2, /* SAR8m1 */ + 0x4a5, /* ROL8r1 */ + 0x4bd, /* ROR8r1 */ + 0x459, /* RCL8r1 */ + 0x471, /* RCR8r1 */ + 0x55e, /* SHL8r1 */ + 0x586, /* SHR8r1 */ + 0x4dc, /* SAL8r1 */ + 0x4f5, /* SAR8r1 */ +/* Table352 */ + 0x496, /* ROL32m1 */ + 0x4ae, /* ROR32m1 */ + 0x44a, /* RCL32m1 */ + 0x462, /* RCR32m1 */ + 0x54f, /* SHL32m1 */ + 0x577, /* SHR32m1 */ + 0x4cd, /* SAL32m1 */ + 0x4e6, /* SAR32m1 */ + 0x499, /* ROL32r1 */ + 0x4b1, /* ROR32r1 */ + 0x44d, /* RCL32r1 */ + 0x465, /* RCR32r1 */ + 0x552, /* SHL32r1 */ + 0x57a, /* SHR32r1 */ + 0x4d0, /* SAL32r1 */ + 0x4e9, /* SAR32r1 */ +/* Table368 */ + 0x4a3, /* ROL8mCL */ + 0x4bb, /* ROR8mCL */ + 0x457, /* RCL8mCL */ + 0x46f, /* RCR8mCL */ + 0x55c, /* SHL8mCL */ + 0x584, /* SHR8mCL */ + 0x4da, /* SAL8mCL */ + 0x4f3, /* SAR8mCL */ + 0x4a6, /* ROL8rCL */ + 0x4be, /* ROR8rCL */ + 0x45a, /* RCL8rCL */ + 0x472, /* RCR8rCL */ + 0x55f, /* SHL8rCL */ + 0x587, /* SHR8rCL */ + 0x4dd, /* SAL8rCL */ + 0x4f6, /* SAR8rCL */ +/* Table384 */ + 0x497, /* ROL32mCL */ + 0x4af, /* ROR32mCL */ + 0x44b, /* RCL32mCL */ + 0x463, /* RCR32mCL */ + 0x550, /* SHL32mCL */ + 0x578, /* SHR32mCL */ + 0x4ce, /* SAL32mCL */ + 0x4e7, /* SAR32mCL */ + 0x49a, /* ROL32rCL */ + 0x4b2, /* ROR32rCL */ + 0x44e, /* RCL32rCL */ + 0x466, /* RCR32rCL */ + 0x553, /* SHL32rCL */ + 0x57b, /* SHR32rCL */ + 0x4d1, /* SAL32rCL */ + 0x4ea, /* SAR32rCL */ +/* Table400 */ + 0x80, /* AAM8i8 */ +/* Table401 */ + 0x7f, /* AAD8i8 */ +/* Table402 */ + 0x4df, /* SALC */ +/* Table403 */ + 0x652, /* XLAT */ +/* Table404 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x247, /* FSETPM */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table476 */ + 0x2fe, /* LOOPNE */ +/* Table477 */ + 0x2fd, /* LOOPE */ +/* Table478 */ + 0x2fc, /* LOOP */ +/* Table479 */ + 0x29f, /* JECXZ */ +/* Table480 */ + 0x270, /* IN8ri */ +/* Table481 */ + 0x26e, /* IN32ri */ +/* Table482 */ + 0x3f6, /* OUT8ir */ +/* Table483 */ + 0x3f4, /* OUT32ir */ +/* Table484 */ + 0x17f, /* CALLpcrel32 */ +/* Table485 */ + 0x2bd, /* JMP_4 */ +/* Table486 */ + 0x244, /* FARJMP32i */ +/* Table487 */ + 0x2bb, /* JMP_1 */ +/* Table488 */ + 0x271, /* IN8rr */ +/* Table489 */ + 0x26f, /* IN32rr */ +/* Table490 */ + 0x3f7, /* OUT8rr */ +/* Table491 */ + 0x3f5, /* OUT32rr */ +/* Table492 */ + 0x2f7, /* LOCK_PREFIX */ +/* Table493 */ + 0x282, /* INT1 */ +/* Table494 */ + 0x487, /* REPNE_PREFIX */ +/* Table495 */ + 0x488, /* REP_PREFIX */ +/* Table496 */ + 0x249, /* HLT */ +/* Table497 */ + 0x18e, /* CMC */ +/* Table498 */ + 0x5f9, /* TEST8mi */ + 0x5fa, /* TEST8mi_alt */ + 0x3cc, /* NOT8m */ + 0x3a5, /* NEG8m */ + 0x398, /* MUL8m */ + 0x26a, /* IMUL8m */ + 0x238, /* DIV8m */ + 0x250, /* IDIV8m */ + 0x5fc, /* TEST8ri */ + 0x5fd, /* TEST8ri_alt */ + 0x3cd, /* NOT8r */ + 0x3a6, /* NEG8r */ + 0x399, /* MUL8r */ + 0x26b, /* IMUL8r */ + 0x239, /* DIV8r */ + 0x251, /* IDIV8r */ +/* Table514 */ + 0x5eb, /* TEST32mi */ + 0x5ec, /* TEST32mi_alt */ + 0x3c8, /* NOT32m */ + 0x3a1, /* NEG32m */ + 0x394, /* MUL32m */ + 0x25a, /* IMUL32m */ + 0x234, /* DIV32m */ + 0x24c, /* IDIV32m */ + 0x5ee, /* TEST32ri */ + 0x5ef, /* TEST32ri_alt */ + 0x3c9, /* NOT32r */ + 0x3a2, /* NEG32r */ + 0x395, /* MUL32r */ + 0x25b, /* IMUL32r */ + 0x235, /* DIV32r */ + 0x24d, /* IDIV32r */ +/* Table530 */ + 0x184, /* CLC */ +/* Table531 */ + 0x5a8, /* STC */ +/* Table532 */ + 0x189, /* CLI */ +/* Table533 */ + 0x5ab, /* STI */ +/* Table534 */ + 0x185, /* CLD */ +/* Table535 */ + 0x5a9, /* STD */ +/* Table536 */ + 0x27a, /* INC8m */ + 0x230, /* DEC8m */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x27b, /* INC8r */ + 0x231, /* DEC8r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table552 */ + 0x275, /* INC32m */ + 0x22b, /* DEC32m */ + 0x175, /* CALL32m */ + 0x240, /* FARCALL32m */ + 0x2b3, /* JMP32m */ + 0x245, /* FARJMP32m */ + 0x428, /* PUSH32rmm */ + 0x0, /* */ + 0x276, /* INC32r */ + 0x22c, /* DEC32r */ + 0x177, /* CALL32r */ + 0x0, /* */ + 0x2b5, /* JMP32r */ + 0x0, /* */ + 0x429, /* PUSH32rmr */ + 0x0, /* */ +/* Table568 */ + 0x48f, /* REX64_PREFIX */ +/* Table569 */ + 0x42c, /* PUSH64r */ +/* Table570 */ + 0x40a, /* POP64r */ +/* Table571 */ + 0x42a, /* PUSH64i32 */ +/* Table572 */ + 0x42b, /* PUSH64i8 */ +/* Table573 */ + 0x2df, /* LEA64_32r */ + 0x0, /* */ +/* Table575 */ + 0x40b, /* POP64rmm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x40c, /* POP64rmr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table591 */ + 0x439, /* PUSHF64 */ +/* Table592 */ + 0x415, /* POPF64 */ +/* Table593 */ + 0x357, /* MOV8ao64 */ +/* Table594 */ + 0x333, /* MOV32ao64 */ +/* Table595 */ + 0x35d, /* MOV8o64a */ +/* Table596 */ + 0x33a, /* MOV32o64a */ +/* Table597 */ + 0x48a, /* RETIQ */ +/* Table598 */ + 0x48d, /* RETQ */ +/* Table599 */ + 0x2e2, /* LEAVE64 */ +/* Table600 */ + 0x2d0, /* JRCXZ */ +/* Table601 */ + 0x17b, /* CALL64pcrel32 */ +/* Table602 */ + 0x275, /* INC32m */ + 0x22b, /* DEC32m */ + 0x179, /* CALL64m */ + 0x240, /* FARCALL32m */ + 0x2b7, /* JMP64m */ + 0x245, /* FARJMP32m */ + 0x42d, /* PUSH64rmm */ + 0x0, /* */ + 0x276, /* INC32r */ + 0x22c, /* DEC32r */ + 0x17c, /* CALL64r */ + 0x0, /* */ + 0x2b9, /* JMP64r */ + 0x0, /* */ + 0x42e, /* PUSH64rmr */ + 0x0, /* */ +/* Table618 */ + 0xad, /* ADD16mr */ + 0xb1, /* ADD16rr */ +/* Table620 */ + 0xb0, /* ADD16rm */ + 0xb2, /* ADD16rr_REV */ +/* Table622 */ + 0xaa, /* ADD16i16 */ +/* Table623 */ + 0x435, /* PUSHES16 */ +/* Table624 */ + 0x411, /* POPES16 */ +/* Table625 */ + 0x3d1, /* OR16mr */ + 0x3d5, /* OR16rr */ +/* Table627 */ + 0x3d4, /* OR16rm */ + 0x3d6, /* OR16rr_REV */ +/* Table629 */ + 0x3ce, /* OR16i16 */ +/* Table630 */ + 0x431, /* PUSHCS16 */ +/* Table631 */ + 0x85, /* ADC16mr */ + 0x89, /* ADC16rr */ +/* Table633 */ + 0x88, /* ADC16rm */ + 0x8a, /* ADC16rr_REV */ +/* Table635 */ + 0x82, /* ADC16i16 */ +/* Table636 */ + 0x440, /* PUSHSS16 */ +/* Table637 */ + 0x41c, /* POPSS16 */ +/* Table638 */ + 0x500, /* SBB16mr */ + 0x504, /* SBB16rr */ +/* Table640 */ + 0x503, /* SBB16rm */ + 0x505, /* SBB16rr_REV */ +/* Table642 */ + 0x4fd, /* SBB16i16 */ +/* Table643 */ + 0x433, /* PUSHDS16 */ +/* Table644 */ + 0x40f, /* POPDS16 */ +/* Table645 */ + 0xd5, /* AND16mr */ + 0xd9, /* AND16rr */ +/* Table647 */ + 0xd8, /* AND16rm */ + 0xda, /* AND16rr_REV */ +/* Table649 */ + 0xd2, /* AND16i16 */ +/* Table650 */ + 0x5b7, /* SUB16mr */ + 0x5bb, /* SUB16rr */ +/* Table652 */ + 0x5ba, /* SUB16rm */ + 0x5bc, /* SUB16rr_REV */ +/* Table654 */ + 0x5b4, /* SUB16i16 */ +/* Table655 */ + 0x656, /* XOR16mr */ + 0x65a, /* XOR16rr */ +/* Table657 */ + 0x659, /* XOR16rm */ + 0x65b, /* XOR16rr_REV */ +/* Table659 */ + 0x653, /* XOR16i16 */ +/* Table660 */ + 0x1f2, /* CMP16mr */ + 0x1f6, /* CMP16rr */ +/* Table662 */ + 0x1f5, /* CMP16rm */ + 0x1f7, /* CMP16rr_REV */ +/* Table664 */ + 0x1ef, /* CMP16i16 */ +/* Table665 */ + 0x274, /* INC16r_alt */ +/* Table666 */ + 0x22a, /* DEC16r_alt */ +/* Table667 */ + 0x423, /* PUSH16r */ +/* Table668 */ + 0x404, /* POP16r */ +/* Table669 */ + 0x42f, /* PUSHA16 */ +/* Table670 */ + 0x40d, /* POPA16 */ +/* Table671 */ + 0x12c, /* BOUNDS16rm */ + 0x0, /* */ +/* Table673 */ + 0x442, /* PUSHi16 */ +/* Table674 */ + 0x255, /* IMUL16rmi */ + 0x258, /* IMUL16rri */ +/* Table676 */ + 0x422, /* PUSH16i8 */ +/* Table677 */ + 0x256, /* IMUL16rmi8 */ + 0x259, /* IMUL16rri8 */ +/* Table679 */ + 0x280, /* INSW */ +/* Table680 */ + 0x3fa, /* OUTSW */ +/* Table681 */ + 0xab, /* ADD16mi */ + 0x3cf, /* OR16mi */ + 0x83, /* ADC16mi */ + 0x4fe, /* SBB16mi */ + 0xd3, /* AND16mi */ + 0x5b5, /* SUB16mi */ + 0x654, /* XOR16mi */ + 0x1f0, /* CMP16mi */ + 0xae, /* ADD16ri */ + 0x3d2, /* OR16ri */ + 0x86, /* ADC16ri */ + 0x501, /* SBB16ri */ + 0xd6, /* AND16ri */ + 0x5b8, /* SUB16ri */ + 0x657, /* XOR16ri */ + 0x1f3, /* CMP16ri */ +/* Table697 */ + 0xac, /* ADD16mi8 */ + 0x3d0, /* OR16mi8 */ + 0x84, /* ADC16mi8 */ + 0x4ff, /* SBB16mi8 */ + 0xd4, /* AND16mi8 */ + 0x5b6, /* SUB16mi8 */ + 0x655, /* XOR16mi8 */ + 0x1f1, /* CMP16mi8 */ + 0xaf, /* ADD16ri8 */ + 0x3d3, /* OR16ri8 */ + 0x87, /* ADC16ri8 */ + 0x502, /* SBB16ri8 */ + 0xd7, /* AND16ri8 */ + 0x5b9, /* SUB16ri8 */ + 0x658, /* XOR16ri8 */ + 0x1f4, /* CMP16ri8 */ +/* Table713 */ + 0x5e6, /* TEST16mr */ + 0x5e9, /* TEST16rr */ +/* Table715 */ + 0x642, /* XCHG16rm */ + 0x643, /* XCHG16rr */ +/* Table717 */ + 0x324, /* MOV16mr */ + 0x32c, /* MOV16rr */ +/* Table719 */ + 0x32b, /* MOV16rm */ + 0x32d, /* MOV16rr_REV */ +/* Table721 */ + 0x325, /* MOV16ms */ + 0x32e, /* MOV16rs */ +/* Table723 */ + 0x2dd, /* LEA16r */ + 0x0, /* */ +/* Table725 */ + 0x32f, /* MOV16sm */ + 0x330, /* MOV16sr */ +/* Table727 */ + 0x405, /* POP16rmm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x406, /* POP16rmr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table743 */ + 0x641, /* XCHG16ar */ +/* Table744 */ + 0x180, /* CBW */ +/* Table745 */ + 0x223, /* CWD */ +/* Table746 */ + 0x23d, /* FARCALL16i */ +/* Table747 */ + 0x437, /* PUSHF16 */ +/* Table748 */ + 0x413, /* POPF16 */ +/* Table749 */ + 0x321, /* MOV16ao32 */ +/* Table750 */ + 0x327, /* MOV16o32a */ +/* Table751 */ + 0x373, /* MOVSW */ +/* Table752 */ + 0x216, /* CMPSW */ +/* Table753 */ + 0x5e3, /* TEST16i16 */ +/* Table754 */ + 0x5af, /* STOSW */ +/* Table755 */ + 0x2fb, /* LODSW */ +/* Table756 */ + 0x524, /* SCASW */ +/* Table757 */ + 0x329, /* MOV16ri */ +/* Table758 */ + 0x492, /* ROL16mi */ + 0x4aa, /* ROR16mi */ + 0x446, /* RCL16mi */ + 0x45e, /* RCR16mi */ + 0x54b, /* SHL16mi */ + 0x573, /* SHR16mi */ + 0x4c9, /* SAL16mi */ + 0x4e2, /* SAR16mi */ + 0x495, /* ROL16ri */ + 0x4ad, /* ROR16ri */ + 0x449, /* RCL16ri */ + 0x461, /* RCR16ri */ + 0x54e, /* SHL16ri */ + 0x576, /* SHR16ri */ + 0x4cc, /* SAL16ri */ + 0x4e5, /* SAR16ri */ +/* Table774 */ + 0x48b, /* RETIW */ +/* Table775 */ + 0x48e, /* RETW */ +/* Table776 */ + 0x2e3, /* LES16rm */ + 0x0, /* */ +/* Table778 */ + 0x2db, /* LDS16rm */ + 0x0, /* */ +/* Table780 */ + 0x323, /* MOV16mi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x32a, /* MOV16ri_alt */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table796 */ + 0x301, /* LRETIW */ +/* Table797 */ + 0x304, /* LRETW */ +/* Table798 */ + 0x28f, /* IRET16 */ +/* Table799 */ + 0x490, /* ROL16m1 */ + 0x4a8, /* ROR16m1 */ + 0x444, /* RCL16m1 */ + 0x45c, /* RCR16m1 */ + 0x549, /* SHL16m1 */ + 0x571, /* SHR16m1 */ + 0x4c7, /* SAL16m1 */ + 0x4e0, /* SAR16m1 */ + 0x493, /* ROL16r1 */ + 0x4ab, /* ROR16r1 */ + 0x447, /* RCL16r1 */ + 0x45f, /* RCR16r1 */ + 0x54c, /* SHL16r1 */ + 0x574, /* SHR16r1 */ + 0x4ca, /* SAL16r1 */ + 0x4e3, /* SAR16r1 */ +/* Table815 */ + 0x491, /* ROL16mCL */ + 0x4a9, /* ROR16mCL */ + 0x445, /* RCL16mCL */ + 0x45d, /* RCR16mCL */ + 0x54a, /* SHL16mCL */ + 0x572, /* SHR16mCL */ + 0x4c8, /* SAL16mCL */ + 0x4e1, /* SAR16mCL */ + 0x494, /* ROL16rCL */ + 0x4ac, /* ROR16rCL */ + 0x448, /* RCL16rCL */ + 0x460, /* RCR16rCL */ + 0x54d, /* SHL16rCL */ + 0x575, /* SHR16rCL */ + 0x4cb, /* SAL16rCL */ + 0x4e4, /* SAR16rCL */ +/* Table831 */ + 0x26c, /* IN16ri */ +/* Table832 */ + 0x3f2, /* OUT16ir */ +/* Table833 */ + 0x17e, /* CALLpcrel16 */ +/* Table834 */ + 0x2bc, /* JMP_2 */ +/* Table835 */ + 0x242, /* FARJMP16i */ +/* Table836 */ + 0x26d, /* IN16rr */ +/* Table837 */ + 0x3f3, /* OUT16rr */ +/* Table838 */ + 0x5e4, /* TEST16mi */ + 0x5e5, /* TEST16mi_alt */ + 0x3c6, /* NOT16m */ + 0x39f, /* NEG16m */ + 0x392, /* MUL16m */ + 0x252, /* IMUL16m */ + 0x232, /* DIV16m */ + 0x24a, /* IDIV16m */ + 0x5e7, /* TEST16ri */ + 0x5e8, /* TEST16ri_alt */ + 0x3c7, /* NOT16r */ + 0x3a0, /* NEG16r */ + 0x393, /* MUL16r */ + 0x253, /* IMUL16r */ + 0x233, /* DIV16r */ + 0x24b, /* IDIV16r */ +/* Table854 */ + 0x272, /* INC16m */ + 0x228, /* DEC16m */ + 0x171, /* CALL16m */ + 0x23e, /* FARCALL16m */ + 0x2af, /* JMP16m */ + 0x243, /* FARJMP16m */ + 0x424, /* PUSH16rmm */ + 0x0, /* */ + 0x273, /* INC16r */ + 0x229, /* DEC16r */ + 0x173, /* CALL16r */ + 0x0, /* */ + 0x2b1, /* JMP16r */ + 0x0, /* */ + 0x425, /* PUSH16rmr */ + 0x0, /* */ +/* Table870 */ + 0x355, /* MOV8ao16 */ +/* Table871 */ + 0x331, /* MOV32ao16 */ +/* Table872 */ + 0x35b, /* MOV8o16a */ +/* Table873 */ + 0x338, /* MOV32o16a */ +/* Table874 */ + 0x29e, /* JCXZ */ +/* Table875 */ + 0x320, /* MOV16ao16 */ +/* Table876 */ + 0x326, /* MOV16o16a */ +/* Table877 */ + 0xbf, /* ADD64mr */ + 0xc3, /* ADD64rr */ +/* Table879 */ + 0xc2, /* ADD64rm */ + 0xc4, /* ADD64rr_REV */ +/* Table881 */ + 0xbc, /* ADD64i32 */ +/* Table882 */ + 0x3e3, /* OR64mr */ + 0x3e7, /* OR64rr */ +/* Table884 */ + 0x3e6, /* OR64rm */ + 0x3e8, /* OR64rr_REV */ +/* Table886 */ + 0x3e0, /* OR64i32 */ +/* Table887 */ + 0x97, /* ADC64mr */ + 0x9b, /* ADC64rr */ +/* Table889 */ + 0x9a, /* ADC64rm */ + 0x9c, /* ADC64rr_REV */ +/* Table891 */ + 0x94, /* ADC64i32 */ +/* Table892 */ + 0x512, /* SBB64mr */ + 0x516, /* SBB64rr */ +/* Table894 */ + 0x515, /* SBB64rm */ + 0x517, /* SBB64rr_REV */ +/* Table896 */ + 0x50f, /* SBB64i32 */ +/* Table897 */ + 0xe7, /* AND64mr */ + 0xeb, /* AND64rr */ +/* Table899 */ + 0xea, /* AND64rm */ + 0xec, /* AND64rr_REV */ +/* Table901 */ + 0xe4, /* AND64i32 */ +/* Table902 */ + 0x5c9, /* SUB64mr */ + 0x5cd, /* SUB64rr */ +/* Table904 */ + 0x5cc, /* SUB64rm */ + 0x5ce, /* SUB64rr_REV */ +/* Table906 */ + 0x5c6, /* SUB64i32 */ +/* Table907 */ + 0x668, /* XOR64mr */ + 0x66c, /* XOR64rr */ +/* Table909 */ + 0x66b, /* XOR64rm */ + 0x66d, /* XOR64rr_REV */ +/* Table911 */ + 0x665, /* XOR64i32 */ +/* Table912 */ + 0x204, /* CMP64mr */ + 0x208, /* CMP64rr */ +/* Table914 */ + 0x207, /* CMP64rm */ + 0x209, /* CMP64rr_REV */ +/* Table916 */ + 0x201, /* CMP64i32 */ +/* Table917 */ + 0x37f, /* MOVSX64rm32 */ + 0x382, /* MOVSX64rr32 */ +/* Table919 */ + 0x265, /* IMUL64rmi32 */ + 0x268, /* IMUL64rri32 */ +/* Table921 */ + 0x266, /* IMUL64rmi8 */ + 0x269, /* IMUL64rri8 */ +/* Table923 */ + 0xbd, /* ADD64mi32 */ + 0x3e1, /* OR64mi32 */ + 0x95, /* ADC64mi32 */ + 0x510, /* SBB64mi32 */ + 0xe5, /* AND64mi32 */ + 0x5c7, /* SUB64mi32 */ + 0x666, /* XOR64mi32 */ + 0x202, /* CMP64mi32 */ + 0xc0, /* ADD64ri32 */ + 0x3e4, /* OR64ri32 */ + 0x98, /* ADC64ri32 */ + 0x513, /* SBB64ri32 */ + 0xe8, /* AND64ri32 */ + 0x5ca, /* SUB64ri32 */ + 0x669, /* XOR64ri32 */ + 0x205, /* CMP64ri32 */ +/* Table939 */ + 0xbe, /* ADD64mi8 */ + 0x3e2, /* OR64mi8 */ + 0x96, /* ADC64mi8 */ + 0x511, /* SBB64mi8 */ + 0xe6, /* AND64mi8 */ + 0x5c8, /* SUB64mi8 */ + 0x667, /* XOR64mi8 */ + 0x203, /* CMP64mi8 */ + 0xc1, /* ADD64ri8 */ + 0x3e5, /* OR64ri8 */ + 0x99, /* ADC64ri8 */ + 0x514, /* SBB64ri8 */ + 0xe9, /* AND64ri8 */ + 0x5cb, /* SUB64ri8 */ + 0x66a, /* XOR64ri8 */ + 0x206, /* CMP64ri8 */ +/* Table955 */ + 0x5f4, /* TEST64mr */ + 0x5f7, /* TEST64rr */ +/* Table957 */ + 0x648, /* XCHG64rm */ + 0x649, /* XCHG64rr */ +/* Table959 */ + 0x349, /* MOV64mr */ + 0x351, /* MOV64rr */ +/* Table961 */ + 0x350, /* MOV64rm */ + 0x352, /* MOV64rr_REV */ +/* Table963 */ + 0x325, /* MOV16ms */ + 0x353, /* MOV64rs */ +/* Table965 */ + 0x2e0, /* LEA64r */ + 0x0, /* */ +/* Table967 */ + 0x32f, /* MOV16sm */ + 0x354, /* MOV64sr */ +/* Table969 */ + 0x647, /* XCHG64ar */ +/* Table970 */ + 0x182, /* CDQE */ +/* Table971 */ + 0x222, /* CQO */ +/* Table972 */ + 0x345, /* MOV64ao64 */ +/* Table973 */ + 0x34b, /* MOV64o64a */ +/* Table974 */ + 0x372, /* MOVSQ */ +/* Table975 */ + 0x215, /* CMPSQ */ +/* Table976 */ + 0x5f1, /* TEST64i32 */ +/* Table977 */ + 0x5ae, /* STOSQ */ +/* Table978 */ + 0x2fa, /* LODSQ */ +/* Table979 */ + 0x523, /* SCASQ */ +/* Table980 */ + 0x34e, /* MOV64ri */ +/* Table981 */ + 0x49e, /* ROL64mi */ + 0x4b6, /* ROR64mi */ + 0x452, /* RCL64mi */ + 0x46a, /* RCR64mi */ + 0x557, /* SHL64mi */ + 0x57f, /* SHR64mi */ + 0x4d5, /* SAL64mi */ + 0x4ee, /* SAR64mi */ + 0x4a1, /* ROL64ri */ + 0x4b9, /* ROR64ri */ + 0x455, /* RCL64ri */ + 0x46d, /* RCR64ri */ + 0x55a, /* SHL64ri */ + 0x582, /* SHR64ri */ + 0x4d8, /* SAL64ri */ + 0x4f1, /* SAR64ri */ +/* Table997 */ + 0x348, /* MOV64mi32 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x34f, /* MOV64ri32 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1013 */ + 0x300, /* LRETIQ */ +/* Table1014 */ + 0x303, /* LRETQ */ +/* Table1015 */ + 0x291, /* IRET64 */ +/* Table1016 */ + 0x49c, /* ROL64m1 */ + 0x4b4, /* ROR64m1 */ + 0x450, /* RCL64m1 */ + 0x468, /* RCR64m1 */ + 0x555, /* SHL64m1 */ + 0x57d, /* SHR64m1 */ + 0x4d3, /* SAL64m1 */ + 0x4ec, /* SAR64m1 */ + 0x49f, /* ROL64r1 */ + 0x4b7, /* ROR64r1 */ + 0x453, /* RCL64r1 */ + 0x46b, /* RCR64r1 */ + 0x558, /* SHL64r1 */ + 0x580, /* SHR64r1 */ + 0x4d6, /* SAL64r1 */ + 0x4ef, /* SAR64r1 */ +/* Table1032 */ + 0x49d, /* ROL64mCL */ + 0x4b5, /* ROR64mCL */ + 0x451, /* RCL64mCL */ + 0x469, /* RCR64mCL */ + 0x556, /* SHL64mCL */ + 0x57e, /* SHR64mCL */ + 0x4d4, /* SAL64mCL */ + 0x4ed, /* SAR64mCL */ + 0x4a0, /* ROL64rCL */ + 0x4b8, /* ROR64rCL */ + 0x454, /* RCL64rCL */ + 0x46c, /* RCR64rCL */ + 0x559, /* SHL64rCL */ + 0x581, /* SHR64rCL */ + 0x4d7, /* SAL64rCL */ + 0x4f0, /* SAR64rCL */ +/* Table1048 */ + 0x5f2, /* TEST64mi32 */ + 0x5f3, /* TEST64mi32_alt */ + 0x3ca, /* NOT64m */ + 0x3a3, /* NEG64m */ + 0x396, /* MUL64m */ + 0x262, /* IMUL64m */ + 0x236, /* DIV64m */ + 0x24e, /* IDIV64m */ + 0x5f5, /* TEST64ri32 */ + 0x5f6, /* TEST64ri32_alt */ + 0x3cb, /* NOT64r */ + 0x3a4, /* NEG64r */ + 0x397, /* MUL64r */ + 0x263, /* IMUL64r */ + 0x237, /* DIV64r */ + 0x24f, /* IDIV64r */ +/* Table1064 */ + 0x278, /* INC64m */ + 0x22e, /* DEC64m */ + 0x179, /* CALL64m */ + 0x241, /* FARCALL64 */ + 0x2b7, /* JMP64m */ + 0x246, /* FARJMP64 */ + 0x42d, /* PUSH64rmm */ + 0x0, /* */ + 0x279, /* INC64r */ + 0x22f, /* DEC64r */ + 0x17c, /* CALL64r */ + 0x0, /* */ + 0x2b9, /* JMP64r */ + 0x0, /* */ + 0x42e, /* PUSH64rmr */ + 0x0, /* */ +/* Table1080 */ + 0x344, /* MOV64ao32 */ +/* Table1081 */ + 0x34a, /* MOV64o32a */ +/* Table1082 */ + 0x278, /* INC64m */ + 0x22e, /* DEC64m */ + 0x179, /* CALL64m */ + 0x241, /* FARCALL64 */ + 0x2b7, /* JMP64m */ + 0x246, /* FARJMP64 */ + 0x424, /* PUSH16rmm */ + 0x0, /* */ + 0x279, /* INC64r */ + 0x22f, /* DEC64r */ + 0x17c, /* CALL64r */ + 0x0, /* */ + 0x2b9, /* JMP64r */ + 0x0, /* */ + 0x425, /* PUSH16rmr */ + 0x0, /* */ +/* Table1098 */ + 0x322, /* MOV16ao64 */ +/* Table1099 */ + 0x328, /* MOV16o64a */ +/* Table1100 */ + 0x272, /* INC16m */ + 0x228, /* DEC16m */ + 0x179, /* CALL64m */ + 0x23e, /* FARCALL16m */ + 0x2b7, /* JMP64m */ + 0x243, /* FARJMP16m */ + 0x424, /* PUSH16rmm */ + 0x0, /* */ + 0x273, /* INC16r */ + 0x229, /* DEC16r */ + 0x17c, /* CALL64r */ + 0x0, /* */ + 0x2b9, /* JMP64r */ + 0x0, /* */ + 0x425, /* PUSH16rmr */ + 0x0, /* */ +/* Table1116 */ + 0x59d, /* SLDT16m */ + 0x5b3, /* STRm */ + 0x2f1, /* LLDT16m */ + 0x30e, /* LTRm */ + 0x611, /* VERRm */ + 0x613, /* VERWm */ + 0x0, /* */ + 0x0, /* */ + 0x59f, /* SLDT32r */ + 0x5b1, /* STR32r */ + 0x2f2, /* LLDT16r */ + 0x30f, /* LTRr */ + 0x612, /* VERRr */ + 0x614, /* VERWr */ + 0x0, /* */ + 0x0, /* */ +/* Table1132 */ + 0x547, /* SGDT32m */ + 0x59a, /* SIDT32m */ + 0x2e9, /* LGDT32m */ + 0x2ef, /* LIDT32m */ + 0x5a3, /* SMSW16m */ + 0x0, /* */ + 0x2f5, /* LMSW16m */ + 0x288, /* INVLPG */ + 0x0, /* */ + 0x615, /* VMCALL */ + 0x618, /* VMLAUNCH */ + 0x622, /* VMRESUME */ + 0x62b, /* VMXOFF */ + 0x3fb, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x183, /* CLAC */ + 0x5a7, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x651, /* XGETBV */ + 0x683, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x617, /* VMFUNC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x623, /* VMRUN32 */ + 0x61b, /* VMMCALL */ + 0x619, /* VMLOAD32 */ + 0x625, /* VMSAVE32 */ + 0x5aa, /* STGI */ + 0x188, /* CLGI */ + 0x59c, /* SKINIT */ + 0x289, /* INVLPGA32 */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47b, /* RDPKRUr */ + 0x634, /* WRPKRUr */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x5d8, /* SWAPGS */ + 0x486, /* RDTSCP */ + 0x31e, /* MONITORXrrr */ + 0x39e, /* MWAITXrrr */ + 0x18d, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1204 */ + 0x2d7, /* LAR32rm */ + 0x2d8, /* LAR32rr */ +/* Table1206 */ + 0x307, /* LSL32rm */ + 0x308, /* LSL32rr */ +/* Table1208 */ + 0x5d9, /* SYSCALL */ +/* Table1209 */ + 0x18b, /* CLTS */ +/* Table1210 */ + 0x5dd, /* SYSRET */ +/* Table1211 */ + 0x285, /* INVD */ +/* Table1212 */ + 0x62d, /* WBINVD */ +/* Table1213 */ + 0x60c, /* UD2 */ +/* Table1214 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3b0, /* NOOP18_m4 */ + 0x3b1, /* NOOP18_m5 */ + 0x3b2, /* NOOP18_m6 */ + 0x3b3, /* NOOP18_m7 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3b4, /* NOOP18_r4 */ + 0x3b5, /* NOOP18_r5 */ + 0x3b6, /* NOOP18_r6 */ + 0x3b7, /* NOOP18_r7 */ +/* Table1230 */ + 0x3ba, /* NOOPL_19 */ + 0x3b8, /* NOOP19rr */ +/* Table1232 */ + 0x186, /* CLDEMOTE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1248 */ + 0x3bb, /* NOOPL_1d */ + 0x0, /* */ +/* Table1250 */ + 0x3bc, /* NOOPL_1e */ + 0x0, /* */ +/* Table1252 */ + 0x3b9, /* NOOPL */ + 0x3bd, /* NOOPLr */ +/* Table1254 */ + 0x0, /* */ + 0x33b, /* MOV32rc */ +/* Table1256 */ + 0x0, /* */ + 0x33c, /* MOV32rd */ +/* Table1258 */ + 0x0, /* */ + 0x334, /* MOV32cr */ +/* Table1260 */ + 0x0, /* */ + 0x335, /* MOV32dr */ +/* Table1262 */ + 0x633, /* WRMSR */ +/* Table1263 */ + 0x485, /* RDTSC */ +/* Table1264 */ + 0x478, /* RDMSR */ +/* Table1265 */ + 0x47c, /* RDPMC */ +/* Table1266 */ + 0x5da, /* SYSENTER */ +/* Table1267 */ + 0x5db, /* SYSEXIT */ +/* Table1268 */ + 0x248, /* GETSEC */ +/* Table1269 */ + 0x1df, /* CMOVO32rm */ + 0x1e0, /* CMOVO32rr */ +/* Table1271 */ + 0x1cd, /* CMOVNO32rm */ + 0x1ce, /* CMOVNO32rr */ +/* Table1273 */ + 0x19d, /* CMOVB32rm */ + 0x19e, /* CMOVB32rr */ +/* Table1275 */ + 0x197, /* CMOVAE32rm */ + 0x198, /* CMOVAE32rr */ +/* Table1277 */ + 0x1a9, /* CMOVE32rm */ + 0x1aa, /* CMOVE32rr */ +/* Table1279 */ + 0x1c7, /* CMOVNE32rm */ + 0x1c8, /* CMOVNE32rr */ +/* Table1281 */ + 0x1a3, /* CMOVBE32rm */ + 0x1a4, /* CMOVBE32rr */ +/* Table1283 */ + 0x191, /* CMOVA32rm */ + 0x192, /* CMOVA32rr */ +/* Table1285 */ + 0x1eb, /* CMOVS32rm */ + 0x1ec, /* CMOVS32rr */ +/* Table1287 */ + 0x1d9, /* CMOVNS32rm */ + 0x1da, /* CMOVNS32rr */ +/* Table1289 */ + 0x1e5, /* CMOVP32rm */ + 0x1e6, /* CMOVP32rr */ +/* Table1291 */ + 0x1d3, /* CMOVNP32rm */ + 0x1d4, /* CMOVNP32rr */ +/* Table1293 */ + 0x1bb, /* CMOVL32rm */ + 0x1bc, /* CMOVL32rr */ +/* Table1295 */ + 0x1b5, /* CMOVGE32rm */ + 0x1b6, /* CMOVGE32rr */ +/* Table1297 */ + 0x1c1, /* CMOVLE32rm */ + 0x1c2, /* CMOVLE32rr */ +/* Table1299 */ + 0x1af, /* CMOVG32rm */ + 0x1b0, /* CMOVG32rr */ +/* Table1301 */ + 0x61e, /* VMREAD32mr */ + 0x61f, /* VMREAD32rr */ +/* Table1303 */ + 0x627, /* VMWRITE32rm */ + 0x628, /* VMWRITE32rr */ +/* Table1305 */ + 0x2cc, /* JO_4 */ +/* Table1306 */ + 0x2c3, /* JNO_4 */ +/* Table1307 */ + 0x29d, /* JB_4 */ +/* Table1308 */ + 0x294, /* JAE_4 */ +/* Table1309 */ + 0x2a2, /* JE_4 */ +/* Table1310 */ + 0x2c0, /* JNE_4 */ +/* Table1311 */ + 0x29a, /* JBE_4 */ +/* Table1312 */ + 0x297, /* JA_4 */ +/* Table1313 */ + 0x2d3, /* JS_4 */ +/* Table1314 */ + 0x2c9, /* JNS_4 */ +/* Table1315 */ + 0x2cf, /* JP_4 */ +/* Table1316 */ + 0x2c6, /* JNP_4 */ +/* Table1317 */ + 0x2ae, /* JL_4 */ +/* Table1318 */ + 0x2a5, /* JGE_4 */ +/* Table1319 */ + 0x2ab, /* JLE_4 */ +/* Table1320 */ + 0x2a8, /* JG_4 */ +/* Table1321 */ + 0x53f, /* SETOm */ + 0x540, /* SETOr */ +/* Table1323 */ + 0x539, /* SETNOm */ + 0x53a, /* SETNOr */ +/* Table1325 */ + 0x52b, /* SETBm */ + 0x52c, /* SETBr */ +/* Table1327 */ + 0x525, /* SETAEm */ + 0x526, /* SETAEr */ +/* Table1329 */ + 0x52d, /* SETEm */ + 0x52e, /* SETEr */ +/* Table1331 */ + 0x537, /* SETNEm */ + 0x538, /* SETNEr */ +/* Table1333 */ + 0x529, /* SETBEm */ + 0x52a, /* SETBEr */ +/* Table1335 */ + 0x527, /* SETAm */ + 0x528, /* SETAr */ +/* Table1337 */ + 0x544, /* SETSm */ + 0x545, /* SETSr */ +/* Table1339 */ + 0x53d, /* SETNSm */ + 0x53e, /* SETNSr */ +/* Table1341 */ + 0x541, /* SETPm */ + 0x542, /* SETPr */ +/* Table1343 */ + 0x53b, /* SETNPm */ + 0x53c, /* SETNPr */ +/* Table1345 */ + 0x535, /* SETLm */ + 0x536, /* SETLr */ +/* Table1347 */ + 0x52f, /* SETGEm */ + 0x530, /* SETGEr */ +/* Table1349 */ + 0x533, /* SETLEm */ + 0x534, /* SETLEr */ +/* Table1351 */ + 0x531, /* SETGm */ + 0x532, /* SETGr */ +/* Table1353 */ + 0x43b, /* PUSHFS32 */ +/* Table1354 */ + 0x417, /* POPFS32 */ +/* Table1355 */ + 0x221, /* CPUID */ +/* Table1356 */ + 0x142, /* BT32mr */ + 0x144, /* BT32rr */ +/* Table1358 */ + 0x566, /* SHLD32mri8 */ + 0x568, /* SHLD32rri8 */ +/* Table1360 */ + 0x565, /* SHLD32mrCL */ + 0x567, /* SHLD32rrCL */ +/* Table1362 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x31f, /* MONTMUL */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x684, /* XSHA1 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x685, /* XSHA256 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1434 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x686, /* XSTORE */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x64f, /* XCRYPTECB */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x64c, /* XCRYPTCBC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x64e, /* XCRYPTCTR */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x64d, /* XCRYPTCFB */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x650, /* XCRYPTOFB */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1506 */ + 0x43e, /* PUSHGS32 */ +/* Table1507 */ + 0x41a, /* POPGS32 */ +/* Table1508 */ + 0x4c4, /* RSM */ +/* Table1509 */ + 0x166, /* BTS32mr */ + 0x168, /* BTS32rr */ +/* Table1511 */ + 0x58e, /* SHRD32mri8 */ + 0x590, /* SHRD32rri8 */ +/* Table1513 */ + 0x58d, /* SHRD32mrCL */ + 0x58f, /* SHRD32rrCL */ +/* Table1515 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x67b, /* XSAVE */ + 0x677, /* XRSTOR */ + 0x67f, /* XSAVEOPT */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1531 */ + 0x25c, /* IMUL32rm */ + 0x25f, /* IMUL32rr */ +/* Table1533 */ + 0x21f, /* CMPXCHG8rm */ + 0x220, /* CMPXCHG8rr */ +/* Table1535 */ + 0x21a, /* CMPXCHG32rm */ + 0x21b, /* CMPXCHG32rr */ +/* Table1537 */ + 0x30c, /* LSS32rm */ + 0x0, /* */ +/* Table1539 */ + 0x15a, /* BTR32mr */ + 0x15c, /* BTR32rr */ +/* Table1541 */ + 0x2e6, /* LFS32rm */ + 0x0, /* */ +/* Table1543 */ + 0x2ec, /* LGS32rm */ + 0x0, /* */ +/* Table1545 */ + 0x389, /* MOVZX32rm8 */ + 0x38c, /* MOVZX32rr8 */ +/* Table1547 */ + 0x388, /* MOVZX32rm16 */ + 0x38b, /* MOVZX32rr16 */ +/* Table1549 */ + 0x60b, /* UD1 */ +/* Table1550 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x141, /* BT32mi8 */ + 0x165, /* BTS32mi8 */ + 0x159, /* BTR32mi8 */ + 0x14d, /* BTC32mi8 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x143, /* BT32ri8 */ + 0x167, /* BTS32ri8 */ + 0x15b, /* BTR32ri8 */ + 0x14f, /* BTC32ri8 */ +/* Table1566 */ + 0x14e, /* BTC32mr */ + 0x150, /* BTC32rr */ +/* Table1568 */ + 0x130, /* BSF32rm */ + 0x131, /* BSF32rr */ +/* Table1570 */ + 0x136, /* BSR32rm */ + 0x137, /* BSR32rr */ +/* Table1572 */ + 0x379, /* MOVSX32rm8 */ + 0x37c, /* MOVSX32rr8 */ +/* Table1574 */ + 0x378, /* MOVSX32rm16 */ + 0x37b, /* MOVSX32rr16 */ +/* Table1576 */ + 0x63f, /* XADD8rm */ + 0x640, /* XADD8rr */ +/* Table1578 */ + 0x63b, /* XADD32rm */ + 0x63c, /* XADD32rr */ +/* Table1580 */ + 0x0, /* */ + 0x21e, /* CMPXCHG8B */ + 0x0, /* */ + 0x679, /* XRSTORS */ + 0x67d, /* XSAVEC */ + 0x681, /* XSAVES */ + 0x61c, /* VMPTRLDm */ + 0x61d, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47e, /* RDRAND32r */ + 0x481, /* RDSEED32r */ +/* Table1596 */ + 0x13b, /* BSWAP32r */ +/* Table1597 */ + 0x60a, /* UD0 */ +/* Table1598 */ + 0x548, /* SGDT64m */ + 0x59b, /* SIDT64m */ + 0x2ea, /* LGDT64m */ + 0x2f0, /* LIDT64m */ + 0x5a3, /* SMSW16m */ + 0x0, /* */ + 0x2f5, /* LMSW16m */ + 0x288, /* INVLPG */ + 0x0, /* */ + 0x615, /* VMCALL */ + 0x618, /* VMLAUNCH */ + 0x622, /* VMRESUME */ + 0x62b, /* VMXOFF */ + 0x3fb, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x183, /* CLAC */ + 0x5a7, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x651, /* XGETBV */ + 0x683, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x617, /* VMFUNC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x624, /* VMRUN64 */ + 0x61b, /* VMMCALL */ + 0x61a, /* VMLOAD64 */ + 0x626, /* VMSAVE64 */ + 0x5aa, /* STGI */ + 0x188, /* CLGI */ + 0x59c, /* SKINIT */ + 0x28a, /* INVLPGA64 */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47b, /* RDPKRUr */ + 0x634, /* WRPKRUr */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x5d8, /* SWAPGS */ + 0x486, /* RDTSCP */ + 0x31e, /* MONITORXrrr */ + 0x39e, /* MWAITXrrr */ + 0x18d, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1670 */ + 0x0, /* */ + 0x34c, /* MOV64rc */ +/* Table1672 */ + 0x0, /* */ + 0x34d, /* MOV64rd */ +/* Table1674 */ + 0x0, /* */ + 0x346, /* MOV64cr */ +/* Table1676 */ + 0x0, /* */ + 0x347, /* MOV64dr */ +/* Table1678 */ + 0x620, /* VMREAD64mr */ + 0x621, /* VMREAD64rr */ +/* Table1680 */ + 0x629, /* VMWRITE64rm */ + 0x62a, /* VMWRITE64rr */ +/* Table1682 */ + 0x43c, /* PUSHFS64 */ +/* Table1683 */ + 0x418, /* POPFS64 */ +/* Table1684 */ + 0x43f, /* PUSHGS64 */ +/* Table1685 */ + 0x41b, /* POPGS64 */ +/* Table1686 */ + 0x59d, /* SLDT16m */ + 0x5b3, /* STRm */ + 0x2f1, /* LLDT16m */ + 0x30e, /* LTRm */ + 0x611, /* VERRm */ + 0x613, /* VERWm */ + 0x0, /* */ + 0x0, /* */ + 0x59e, /* SLDT16r */ + 0x5b0, /* STR16r */ + 0x2f2, /* LLDT16r */ + 0x30f, /* LTRr */ + 0x612, /* VERRr */ + 0x614, /* VERWr */ + 0x0, /* */ + 0x0, /* */ +/* Table1702 */ + 0x546, /* SGDT16m */ + 0x599, /* SIDT16m */ + 0x2e8, /* LGDT16m */ + 0x2ee, /* LIDT16m */ + 0x5a3, /* SMSW16m */ + 0x0, /* */ + 0x2f5, /* LMSW16m */ + 0x288, /* INVLPG */ + 0x0, /* */ + 0x615, /* VMCALL */ + 0x618, /* VMLAUNCH */ + 0x622, /* VMRESUME */ + 0x62b, /* VMXOFF */ + 0x3fb, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x183, /* CLAC */ + 0x5a7, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x651, /* XGETBV */ + 0x683, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x617, /* VMFUNC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x623, /* VMRUN32 */ + 0x61b, /* VMMCALL */ + 0x619, /* VMLOAD32 */ + 0x625, /* VMSAVE32 */ + 0x5aa, /* STGI */ + 0x188, /* CLGI */ + 0x59c, /* SKINIT */ + 0x289, /* INVLPGA32 */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47b, /* RDPKRUr */ + 0x634, /* WRPKRUr */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x5d8, /* SWAPGS */ + 0x486, /* RDTSCP */ + 0x31e, /* MONITORXrrr */ + 0x39e, /* MWAITXrrr */ + 0x18d, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table1774 */ + 0x2d5, /* LAR16rm */ + 0x2d6, /* LAR16rr */ +/* Table1776 */ + 0x305, /* LSL16rm */ + 0x306, /* LSL16rr */ +/* Table1778 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3a8, /* NOOP18_16m4 */ + 0x3a9, /* NOOP18_16m5 */ + 0x3aa, /* NOOP18_16m6 */ + 0x3ab, /* NOOP18_16m7 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x3ac, /* NOOP18_16r4 */ + 0x3ad, /* NOOP18_16r5 */ + 0x3ae, /* NOOP18_16r6 */ + 0x3af, /* NOOP18_16r7 */ +/* Table1794 */ + 0x3c1, /* NOOPW_19 */ + 0x3b8, /* NOOP19rr */ +/* Table1796 */ + 0x3c2, /* NOOPW_1c */ + 0x0, /* */ +/* Table1798 */ + 0x3c3, /* NOOPW_1d */ + 0x0, /* */ +/* Table1800 */ + 0x3c4, /* NOOPW_1e */ + 0x0, /* */ +/* Table1802 */ + 0x3c0, /* NOOPW */ + 0x3c5, /* NOOPWr */ +/* Table1804 */ + 0x1dd, /* CMOVO16rm */ + 0x1de, /* CMOVO16rr */ +/* Table1806 */ + 0x1cb, /* CMOVNO16rm */ + 0x1cc, /* CMOVNO16rr */ +/* Table1808 */ + 0x19b, /* CMOVB16rm */ + 0x19c, /* CMOVB16rr */ +/* Table1810 */ + 0x195, /* CMOVAE16rm */ + 0x196, /* CMOVAE16rr */ +/* Table1812 */ + 0x1a7, /* CMOVE16rm */ + 0x1a8, /* CMOVE16rr */ +/* Table1814 */ + 0x1c5, /* CMOVNE16rm */ + 0x1c6, /* CMOVNE16rr */ +/* Table1816 */ + 0x1a1, /* CMOVBE16rm */ + 0x1a2, /* CMOVBE16rr */ +/* Table1818 */ + 0x18f, /* CMOVA16rm */ + 0x190, /* CMOVA16rr */ +/* Table1820 */ + 0x1e9, /* CMOVS16rm */ + 0x1ea, /* CMOVS16rr */ +/* Table1822 */ + 0x1d7, /* CMOVNS16rm */ + 0x1d8, /* CMOVNS16rr */ +/* Table1824 */ + 0x1e3, /* CMOVP16rm */ + 0x1e4, /* CMOVP16rr */ +/* Table1826 */ + 0x1d1, /* CMOVNP16rm */ + 0x1d2, /* CMOVNP16rr */ +/* Table1828 */ + 0x1b9, /* CMOVL16rm */ + 0x1ba, /* CMOVL16rr */ +/* Table1830 */ + 0x1b3, /* CMOVGE16rm */ + 0x1b4, /* CMOVGE16rr */ +/* Table1832 */ + 0x1bf, /* CMOVLE16rm */ + 0x1c0, /* CMOVLE16rr */ +/* Table1834 */ + 0x1ad, /* CMOVG16rm */ + 0x1ae, /* CMOVG16rr */ +/* Table1836 */ + 0x2cb, /* JO_2 */ +/* Table1837 */ + 0x2c2, /* JNO_2 */ +/* Table1838 */ + 0x29c, /* JB_2 */ +/* Table1839 */ + 0x293, /* JAE_2 */ +/* Table1840 */ + 0x2a1, /* JE_2 */ +/* Table1841 */ + 0x2bf, /* JNE_2 */ +/* Table1842 */ + 0x299, /* JBE_2 */ +/* Table1843 */ + 0x296, /* JA_2 */ +/* Table1844 */ + 0x2d2, /* JS_2 */ +/* Table1845 */ + 0x2c8, /* JNS_2 */ +/* Table1846 */ + 0x2ce, /* JP_2 */ +/* Table1847 */ + 0x2c5, /* JNP_2 */ +/* Table1848 */ + 0x2ad, /* JL_2 */ +/* Table1849 */ + 0x2a4, /* JGE_2 */ +/* Table1850 */ + 0x2aa, /* JLE_2 */ +/* Table1851 */ + 0x2a7, /* JG_2 */ +/* Table1852 */ + 0x43a, /* PUSHFS16 */ +/* Table1853 */ + 0x416, /* POPFS16 */ +/* Table1854 */ + 0x13e, /* BT16mr */ + 0x140, /* BT16rr */ +/* Table1856 */ + 0x562, /* SHLD16mri8 */ + 0x564, /* SHLD16rri8 */ +/* Table1858 */ + 0x561, /* SHLD16mrCL */ + 0x563, /* SHLD16rrCL */ +/* Table1860 */ + 0x43d, /* PUSHGS16 */ +/* Table1861 */ + 0x419, /* POPGS16 */ +/* Table1862 */ + 0x162, /* BTS16mr */ + 0x164, /* BTS16rr */ +/* Table1864 */ + 0x58a, /* SHRD16mri8 */ + 0x58c, /* SHRD16rri8 */ +/* Table1866 */ + 0x589, /* SHRD16mrCL */ + 0x58b, /* SHRD16rrCL */ +/* Table1868 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x18c, /* CLWB */ + 0x187, /* CLFLUSHOPT */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x5ff, /* TPAUSE */ + 0x0, /* */ +/* Table1884 */ + 0x254, /* IMUL16rm */ + 0x257, /* IMUL16rr */ +/* Table1886 */ + 0x218, /* CMPXCHG16rm */ + 0x219, /* CMPXCHG16rr */ +/* Table1888 */ + 0x30b, /* LSS16rm */ + 0x0, /* */ +/* Table1890 */ + 0x156, /* BTR16mr */ + 0x158, /* BTR16rr */ +/* Table1892 */ + 0x2e5, /* LFS16rm */ + 0x0, /* */ +/* Table1894 */ + 0x2eb, /* LGS16rm */ + 0x0, /* */ +/* Table1896 */ + 0x385, /* MOVZX16rm8 */ + 0x387, /* MOVZX16rr8 */ +/* Table1898 */ + 0x384, /* MOVZX16rm16 */ + 0x386, /* MOVZX16rr16 */ +/* Table1900 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x13d, /* BT16mi8 */ + 0x161, /* BTS16mi8 */ + 0x155, /* BTR16mi8 */ + 0x149, /* BTC16mi8 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x13f, /* BT16ri8 */ + 0x163, /* BTS16ri8 */ + 0x157, /* BTR16ri8 */ + 0x14b, /* BTC16ri8 */ +/* Table1916 */ + 0x14a, /* BTC16mr */ + 0x14c, /* BTC16rr */ +/* Table1918 */ + 0x12e, /* BSF16rm */ + 0x12f, /* BSF16rr */ +/* Table1920 */ + 0x134, /* BSR16rm */ + 0x135, /* BSR16rr */ +/* Table1922 */ + 0x375, /* MOVSX16rm8 */ + 0x377, /* MOVSX16rr8 */ +/* Table1924 */ + 0x374, /* MOVSX16rm16 */ + 0x376, /* MOVSX16rr16 */ +/* Table1926 */ + 0x639, /* XADD16rm */ + 0x63a, /* XADD16rr */ +/* Table1928 */ + 0x0, /* */ + 0x21e, /* CMPXCHG8B */ + 0x0, /* */ + 0x679, /* XRSTORS */ + 0x67d, /* XSAVEC */ + 0x681, /* XSAVES */ + 0x616, /* VMCLEARm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47d, /* RDRAND16r */ + 0x480, /* RDSEED16r */ +/* Table1944 */ + 0x13a, /* BSWAP16r_BAD */ +/* Table1945 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x67b, /* XSAVE */ + 0x677, /* XRSTOR */ + 0x18c, /* CLWB */ + 0x187, /* CLFLUSHOPT */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x5ff, /* TPAUSE */ + 0x0, /* */ +/* Table1961 */ + 0x0, /* */ + 0x21e, /* CMPXCHG8B */ + 0x0, /* */ + 0x679, /* XRSTORS */ + 0x67d, /* XSAVEC */ + 0x681, /* XSAVES */ + 0x616, /* VMCLEARm */ + 0x61d, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47d, /* RDRAND16r */ + 0x480, /* RDSEED16r */ +/* Table1977 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x610, /* UMWAIT */ + 0x0, /* */ +/* Table1993 */ + 0x0, /* */ + 0x21e, /* CMPXCHG8B */ + 0x0, /* */ + 0x679, /* XRSTORS */ + 0x67d, /* XSAVEC */ + 0x681, /* XSAVES */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2009 */ + 0x547, /* SGDT32m */ + 0x59a, /* SIDT32m */ + 0x2e9, /* LGDT32m */ + 0x2ef, /* LIDT32m */ + 0x5a3, /* SMSW16m */ + 0x4c5, /* RSTORSSP */ + 0x2f5, /* LMSW16m */ + 0x288, /* INVLPG */ + 0x0, /* */ + 0x615, /* VMCALL */ + 0x618, /* VMLAUNCH */ + 0x622, /* VMRESUME */ + 0x62b, /* VMXOFF */ + 0x3fb, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x183, /* CLAC */ + 0x5a7, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x651, /* XGETBV */ + 0x683, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x617, /* VMFUNC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x623, /* VMRUN32 */ + 0x61b, /* VMMCALL */ + 0x619, /* VMLOAD32 */ + 0x625, /* VMSAVE32 */ + 0x5aa, /* STGI */ + 0x188, /* CLGI */ + 0x59c, /* SKINIT */ + 0x289, /* INVLPGA32 */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x543, /* SETSSBSY */ + 0x0, /* */ + 0x4fc, /* SAVEPREVSSP */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47b, /* RDPKRUr */ + 0x634, /* WRPKRUr */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x5d8, /* SWAPGS */ + 0x486, /* RDTSCP */ + 0x31e, /* MONITORXrrr */ + 0x39e, /* MWAITXrrr */ + 0x18d, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2081 */ + 0x62e, /* WBNOINVD */ +/* Table2082 */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x483, /* RDSSPD */ + 0x483, /* RDSSPD */ + 0x483, /* RDSSPD */ + 0x483, /* RDSSPD */ + 0x483, /* RDSSPD */ + 0x483, /* RDSSPD */ + 0x483, /* RDSSPD */ + 0x483, /* RDSSPD */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x23b, /* ENDBR64 */ + 0x23a, /* ENDBR32 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2154 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x420, /* PTWRITEm */ + 0x0, /* */ + 0x18a, /* CLRSSBSY */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x421, /* PTWRITEr */ + 0x27c, /* INCSSPD */ + 0x60e, /* UMONITOR32 */ + 0x0, /* */ +/* Table2170 */ + 0x602, /* TZCNT32rm */ + 0x603, /* TZCNT32rr */ +/* Table2172 */ + 0x31a, /* LZCNT32rm */ + 0x31b, /* LZCNT32rr */ +/* Table2174 */ + 0x0, /* */ + 0x21e, /* CMPXCHG8B */ + 0x0, /* */ + 0x679, /* XRSTORS */ + 0x67d, /* XSAVEC */ + 0x681, /* XSAVES */ + 0x62c, /* VMXON */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x479, /* RDPID32 */ +/* Table2190 */ + 0x600, /* TZCNT16rm */ + 0x601, /* TZCNT16rr */ +/* Table2192 */ + 0x318, /* LZCNT16rm */ + 0x319, /* LZCNT16rr */ +/* Table2194 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x60d, /* UMONITOR16 */ + 0x0, /* */ +/* Table2210 */ + 0x59d, /* SLDT16m */ + 0x5b3, /* STRm */ + 0x2f1, /* LLDT16m */ + 0x30e, /* LTRm */ + 0x611, /* VERRm */ + 0x613, /* VERWm */ + 0x0, /* */ + 0x0, /* */ + 0x5a0, /* SLDT64r */ + 0x5b2, /* STR64r */ + 0x2f2, /* LLDT16r */ + 0x30f, /* LTRr */ + 0x612, /* VERRr */ + 0x614, /* VERWr */ + 0x0, /* */ + 0x0, /* */ +/* Table2226 */ + 0x548, /* SGDT64m */ + 0x59b, /* SIDT64m */ + 0x2ea, /* LGDT64m */ + 0x2f0, /* LIDT64m */ + 0x5a3, /* SMSW16m */ + 0x0, /* */ + 0x2f5, /* LMSW16m */ + 0x288, /* INVLPG */ + 0x0, /* */ + 0x615, /* VMCALL */ + 0x618, /* VMLAUNCH */ + 0x622, /* VMRESUME */ + 0x62b, /* VMXOFF */ + 0x3fb, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x183, /* CLAC */ + 0x5a7, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x651, /* XGETBV */ + 0x683, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x617, /* VMFUNC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x624, /* VMRUN64 */ + 0x61b, /* VMMCALL */ + 0x61a, /* VMLOAD64 */ + 0x626, /* VMSAVE64 */ + 0x5aa, /* STGI */ + 0x188, /* CLGI */ + 0x59c, /* SKINIT */ + 0x28a, /* INVLPGA64 */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47b, /* RDPKRUr */ + 0x634, /* WRPKRUr */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x5d8, /* SWAPGS */ + 0x486, /* RDTSCP */ + 0x31e, /* MONITORXrrr */ + 0x39e, /* MWAITXrrr */ + 0x18d, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2298 */ + 0x2d9, /* LAR64rm */ + 0x2da, /* LAR64rr */ +/* Table2300 */ + 0x309, /* LSL64rm */ + 0x30a, /* LSL64rr */ +/* Table2302 */ + 0x5de, /* SYSRET64 */ +/* Table2303 */ + 0x3be, /* NOOPQ */ + 0x3bf, /* NOOPQr */ +/* Table2305 */ + 0x5dc, /* SYSEXIT64 */ +/* Table2306 */ + 0x1e1, /* CMOVO64rm */ + 0x1e2, /* CMOVO64rr */ +/* Table2308 */ + 0x1cf, /* CMOVNO64rm */ + 0x1d0, /* CMOVNO64rr */ +/* Table2310 */ + 0x19f, /* CMOVB64rm */ + 0x1a0, /* CMOVB64rr */ +/* Table2312 */ + 0x199, /* CMOVAE64rm */ + 0x19a, /* CMOVAE64rr */ +/* Table2314 */ + 0x1ab, /* CMOVE64rm */ + 0x1ac, /* CMOVE64rr */ +/* Table2316 */ + 0x1c9, /* CMOVNE64rm */ + 0x1ca, /* CMOVNE64rr */ +/* Table2318 */ + 0x1a5, /* CMOVBE64rm */ + 0x1a6, /* CMOVBE64rr */ +/* Table2320 */ + 0x193, /* CMOVA64rm */ + 0x194, /* CMOVA64rr */ +/* Table2322 */ + 0x1ed, /* CMOVS64rm */ + 0x1ee, /* CMOVS64rr */ +/* Table2324 */ + 0x1db, /* CMOVNS64rm */ + 0x1dc, /* CMOVNS64rr */ +/* Table2326 */ + 0x1e7, /* CMOVP64rm */ + 0x1e8, /* CMOVP64rr */ +/* Table2328 */ + 0x1d5, /* CMOVNP64rm */ + 0x1d6, /* CMOVNP64rr */ +/* Table2330 */ + 0x1bd, /* CMOVL64rm */ + 0x1be, /* CMOVL64rr */ +/* Table2332 */ + 0x1b7, /* CMOVGE64rm */ + 0x1b8, /* CMOVGE64rr */ +/* Table2334 */ + 0x1c3, /* CMOVLE64rm */ + 0x1c4, /* CMOVLE64rr */ +/* Table2336 */ + 0x1b1, /* CMOVG64rm */ + 0x1b2, /* CMOVG64rr */ +/* Table2338 */ + 0x146, /* BT64mr */ + 0x148, /* BT64rr */ +/* Table2340 */ + 0x56a, /* SHLD64mri8 */ + 0x56c, /* SHLD64rri8 */ +/* Table2342 */ + 0x569, /* SHLD64mrCL */ + 0x56b, /* SHLD64rrCL */ +/* Table2344 */ + 0x16a, /* BTS64mr */ + 0x16c, /* BTS64rr */ +/* Table2346 */ + 0x592, /* SHRD64mri8 */ + 0x594, /* SHRD64rri8 */ +/* Table2348 */ + 0x591, /* SHRD64mrCL */ + 0x593, /* SHRD64rrCL */ +/* Table2350 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x67c, /* XSAVE64 */ + 0x678, /* XRSTOR64 */ + 0x680, /* XSAVEOPT64 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2366 */ + 0x264, /* IMUL64rm */ + 0x267, /* IMUL64rr */ +/* Table2368 */ + 0x21c, /* CMPXCHG64rm */ + 0x21d, /* CMPXCHG64rr */ +/* Table2370 */ + 0x30d, /* LSS64rm */ + 0x0, /* */ +/* Table2372 */ + 0x15e, /* BTR64mr */ + 0x160, /* BTR64rr */ +/* Table2374 */ + 0x2e7, /* LFS64rm */ + 0x0, /* */ +/* Table2376 */ + 0x2ed, /* LGS64rm */ + 0x0, /* */ +/* Table2378 */ + 0x38f, /* MOVZX64rm8 */ + 0x391, /* MOVZX64rr8 */ +/* Table2380 */ + 0x38e, /* MOVZX64rm16 */ + 0x390, /* MOVZX64rr16 */ +/* Table2382 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x145, /* BT64mi8 */ + 0x169, /* BTS64mi8 */ + 0x15d, /* BTR64mi8 */ + 0x151, /* BTC64mi8 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x147, /* BT64ri8 */ + 0x16b, /* BTS64ri8 */ + 0x15f, /* BTR64ri8 */ + 0x153, /* BTC64ri8 */ +/* Table2398 */ + 0x152, /* BTC64mr */ + 0x154, /* BTC64rr */ +/* Table2400 */ + 0x132, /* BSF64rm */ + 0x133, /* BSF64rr */ +/* Table2402 */ + 0x138, /* BSR64rm */ + 0x139, /* BSR64rr */ +/* Table2404 */ + 0x380, /* MOVSX64rm8 */ + 0x383, /* MOVSX64rr8 */ +/* Table2406 */ + 0x37e, /* MOVSX64rm16 */ + 0x381, /* MOVSX64rr16 */ +/* Table2408 */ + 0x63d, /* XADD64rm */ + 0x63e, /* XADD64rr */ +/* Table2410 */ + 0x0, /* */ + 0x217, /* CMPXCHG16B */ + 0x0, /* */ + 0x67a, /* XRSTORS64 */ + 0x67e, /* XSAVEC64 */ + 0x682, /* XSAVES64 */ + 0x61c, /* VMPTRLDm */ + 0x61d, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47f, /* RDRAND64r */ + 0x482, /* RDSEED64r */ +/* Table2426 */ + 0x13c, /* BSWAP64r */ +/* Table2427 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x67c, /* XSAVE64 */ + 0x678, /* XRSTOR64 */ + 0x680, /* XSAVEOPT64 */ + 0x187, /* CLFLUSHOPT */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x5ff, /* TPAUSE */ + 0x0, /* */ +/* Table2443 */ + 0x0, /* */ + 0x217, /* CMPXCHG16B */ + 0x0, /* */ + 0x67a, /* XRSTORS64 */ + 0x67e, /* XSAVEC64 */ + 0x682, /* XSAVES64 */ + 0x616, /* VMCLEARm */ + 0x61d, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47f, /* RDRAND64r */ + 0x482, /* RDSEED64r */ +/* Table2459 */ + 0x548, /* SGDT64m */ + 0x59b, /* SIDT64m */ + 0x2ea, /* LGDT64m */ + 0x2f0, /* LIDT64m */ + 0x5a3, /* SMSW16m */ + 0x0, /* */ + 0x2f5, /* LMSW16m */ + 0x288, /* INVLPG */ + 0x0, /* */ + 0x615, /* VMCALL */ + 0x618, /* VMLAUNCH */ + 0x622, /* VMRESUME */ + 0x62b, /* VMXOFF */ + 0x3fb, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x183, /* CLAC */ + 0x5a7, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x651, /* XGETBV */ + 0x683, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x617, /* VMFUNC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x624, /* VMRUN64 */ + 0x61b, /* VMMCALL */ + 0x61a, /* VMLOAD64 */ + 0x626, /* VMSAVE64 */ + 0x5aa, /* STGI */ + 0x188, /* CLGI */ + 0x59c, /* SKINIT */ + 0x28a, /* INVLPGA64 */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x5a4, /* SMSW16r */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47b, /* RDPKRUr */ + 0x634, /* WRPKRUr */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x5d8, /* SWAPGS */ + 0x486, /* RDTSCP */ + 0x31e, /* MONITORXrrr */ + 0x39e, /* MWAITXrrr */ + 0x18d, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2531 */ + 0x548, /* SGDT64m */ + 0x59b, /* SIDT64m */ + 0x2ea, /* LGDT64m */ + 0x2f0, /* LIDT64m */ + 0x5a3, /* SMSW16m */ + 0x4c5, /* RSTORSSP */ + 0x2f5, /* LMSW16m */ + 0x288, /* INVLPG */ + 0x0, /* */ + 0x615, /* VMCALL */ + 0x618, /* VMLAUNCH */ + 0x622, /* VMRESUME */ + 0x62b, /* VMXOFF */ + 0x3fb, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x183, /* CLAC */ + 0x5a7, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x651, /* XGETBV */ + 0x683, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x617, /* VMFUNC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x624, /* VMRUN64 */ + 0x61b, /* VMMCALL */ + 0x61a, /* VMLOAD64 */ + 0x626, /* VMSAVE64 */ + 0x5aa, /* STGI */ + 0x188, /* CLGI */ + 0x59c, /* SKINIT */ + 0x28a, /* INVLPGA64 */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x5a5, /* SMSW32r */ + 0x543, /* SETSSBSY */ + 0x0, /* */ + 0x4fc, /* SAVEPREVSSP */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47b, /* RDPKRUr */ + 0x634, /* WRPKRUr */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x5d8, /* SWAPGS */ + 0x486, /* RDTSCP */ + 0x31e, /* MONITORXrrr */ + 0x39e, /* MWAITXrrr */ + 0x18d, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2603 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x420, /* PTWRITEm */ + 0x0, /* */ + 0x18a, /* CLRSSBSY */ + 0x0, /* */ + 0x474, /* RDFSBASE */ + 0x476, /* RDGSBASE */ + 0x62f, /* WRFSBASE */ + 0x631, /* WRGSBASE */ + 0x421, /* PTWRITEr */ + 0x27c, /* INCSSPD */ + 0x60f, /* UMONITOR64 */ + 0x0, /* */ +/* Table2619 */ + 0x0, /* */ + 0x21e, /* CMPXCHG8B */ + 0x0, /* */ + 0x679, /* XRSTORS */ + 0x67d, /* XSAVEC */ + 0x681, /* XSAVES */ + 0x62c, /* VMXON */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47a, /* RDPID64 */ +/* Table2635 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x420, /* PTWRITEm */ + 0x0, /* */ + 0x18a, /* CLRSSBSY */ + 0x0, /* */ + 0x474, /* RDFSBASE */ + 0x476, /* RDGSBASE */ + 0x62f, /* WRFSBASE */ + 0x631, /* WRGSBASE */ + 0x421, /* PTWRITEr */ + 0x27c, /* INCSSPD */ + 0x60e, /* UMONITOR32 */ + 0x0, /* */ +/* Table2651 */ + 0x548, /* SGDT64m */ + 0x59b, /* SIDT64m */ + 0x2ea, /* LGDT64m */ + 0x2f0, /* LIDT64m */ + 0x5a3, /* SMSW16m */ + 0x4c5, /* RSTORSSP */ + 0x2f5, /* LMSW16m */ + 0x288, /* INVLPG */ + 0x0, /* */ + 0x615, /* VMCALL */ + 0x618, /* VMLAUNCH */ + 0x622, /* VMRESUME */ + 0x62b, /* VMXOFF */ + 0x3fb, /* PCONFIG */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x183, /* CLAC */ + 0x5a7, /* STAC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x651, /* XGETBV */ + 0x683, /* XSETBV */ + 0x0, /* */ + 0x0, /* */ + 0x617, /* VMFUNC */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x624, /* VMRUN64 */ + 0x61b, /* VMMCALL */ + 0x61a, /* VMLOAD64 */ + 0x626, /* VMSAVE64 */ + 0x5aa, /* STGI */ + 0x188, /* CLGI */ + 0x59c, /* SKINIT */ + 0x28a, /* INVLPGA64 */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x5a6, /* SMSW64r */ + 0x543, /* SETSSBSY */ + 0x0, /* */ + 0x4fc, /* SAVEPREVSSP */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47b, /* RDPKRUr */ + 0x634, /* WRPKRUr */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x2f6, /* LMSW16r */ + 0x5d8, /* SWAPGS */ + 0x486, /* RDTSCP */ + 0x31e, /* MONITORXrrr */ + 0x39e, /* MWAITXrrr */ + 0x18d, /* CLZEROr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2723 */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x3bc, /* NOOPL_1e */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x484, /* RDSSPQ */ + 0x484, /* RDSSPQ */ + 0x484, /* RDSSPQ */ + 0x484, /* RDSSPQ */ + 0x484, /* RDSSPQ */ + 0x484, /* RDSSPQ */ + 0x484, /* RDSSPQ */ + 0x484, /* RDSSPQ */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x23b, /* ENDBR64 */ + 0x23a, /* ENDBR32 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2795 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x41e, /* PTWRITE64m */ + 0x677, /* XRSTOR */ + 0x18a, /* CLRSSBSY */ + 0x0, /* */ + 0x475, /* RDFSBASE64 */ + 0x477, /* RDGSBASE64 */ + 0x630, /* WRFSBASE64 */ + 0x632, /* WRGSBASE64 */ + 0x41f, /* PTWRITE64r */ + 0x27d, /* INCSSPQ */ + 0x60f, /* UMONITOR64 */ + 0x0, /* */ +/* Table2811 */ + 0x604, /* TZCNT64rm */ + 0x605, /* TZCNT64rr */ +/* Table2813 */ + 0x31c, /* LZCNT64rm */ + 0x31d, /* LZCNT64rr */ +/* Table2815 */ + 0x0, /* */ + 0x217, /* CMPXCHG16B */ + 0x0, /* */ + 0x67a, /* XRSTORS64 */ + 0x67e, /* XSAVEC64 */ + 0x682, /* XSAVES64 */ + 0x62c, /* VMXON */ + 0x61d, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47e, /* RDRAND32r */ + 0x47a, /* RDPID64 */ +/* Table2831 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x67b, /* XSAVE */ + 0x677, /* XRSTOR */ + 0x67f, /* XSAVEOPT */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x610, /* UMWAIT */ + 0x0, /* */ +/* Table2847 */ + 0x0, /* */ + 0x217, /* CMPXCHG16B */ + 0x0, /* */ + 0x67a, /* XRSTORS64 */ + 0x67e, /* XSAVEC64 */ + 0x682, /* XSAVES64 */ + 0x61c, /* VMPTRLDm */ + 0x61d, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47e, /* RDRAND32r */ + 0x481, /* RDSEED32r */ +/* Table2863 */ + 0x0, /* */ + 0x217, /* CMPXCHG16B */ + 0x0, /* */ + 0x67a, /* XRSTORS64 */ + 0x67e, /* XSAVEC64 */ + 0x682, /* XSAVES64 */ + 0x616, /* VMCLEARm */ + 0x61d, /* VMPTRSTm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x47d, /* RDRAND16r */ + 0x480, /* RDSEED16r */ +/* Table2879 */ + 0x368, /* MOVBE32rm */ + 0x0, /* */ +/* Table2881 */ + 0x367, /* MOVBE32mr */ + 0x0, /* */ +/* Table2883 */ + 0x635, /* WRSSD */ + 0x0, /* */ +/* Table2885 */ + 0x36e, /* MOVDIRI32 */ + 0x0, /* */ +/* Table2887 */ + 0x286, /* INVEPT32 */ + 0x0, /* */ +/* Table2889 */ + 0x28d, /* INVVPID32 */ + 0x0, /* */ +/* Table2891 */ + 0x28b, /* INVPCID32 */ + 0x0, /* */ +/* Table2893 */ + 0x366, /* MOVBE16rm */ + 0x0, /* */ +/* Table2895 */ + 0x365, /* MOVBE16mr */ + 0x0, /* */ +/* Table2897 */ + 0x637, /* WRUSSD */ + 0x0, /* */ +/* Table2899 */ + 0xa6, /* ADCX32rm */ + 0xa7, /* ADCX32rr */ +/* Table2901 */ + 0x36c, /* MOVDIR64B32 */ + 0x0, /* */ +/* Table2903 */ + 0x36b, /* MOVDIR64B16 */ + 0x0, /* */ +/* Table2905 */ + 0xce, /* ADOX32rm */ + 0xcf, /* ADOX32rr */ +/* Table2907 */ + 0x36a, /* MOVBE64rm */ + 0x0, /* */ +/* Table2909 */ + 0x369, /* MOVBE64mr */ + 0x0, /* */ +/* Table2911 */ + 0x636, /* WRSSQ */ + 0x0, /* */ +/* Table2913 */ + 0x36f, /* MOVDIRI64 */ + 0x0, /* */ +/* Table2915 */ + 0x287, /* INVEPT64 */ + 0x0, /* */ +/* Table2917 */ + 0x28e, /* INVVPID64 */ + 0x0, /* */ +/* Table2919 */ + 0x28c, /* INVPCID64 */ + 0x0, /* */ +/* Table2921 */ + 0x636, /* WRSSQ */ + 0xa7, /* ADCX32rr */ +/* Table2923 */ + 0x36d, /* MOVDIR64B64 */ + 0x0, /* */ +/* Table2925 */ + 0xd0, /* ADOX64rm */ + 0xd1, /* ADOX64rr */ +/* Table2927 */ + 0x638, /* WRUSSQ */ + 0x0, /* */ +/* Table2929 */ + 0xa8, /* ADCX64rm */ + 0xa9, /* ADCX64rr */ +/* Table2931 */ + 0xf6, /* ANDN32rm */ + 0xf7, /* ANDN32rr */ +/* Table2933 */ + 0x0, /* */ + 0x128, /* BLSR32rm */ + 0x124, /* BLSMSK32rm */ + 0x11c, /* BLSI32rm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x129, /* BLSR32rr */ + 0x125, /* BLSMSK32rr */ + 0x11d, /* BLSI32rr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2949 */ + 0x16d, /* BZHI32rm */ + 0x16e, /* BZHI32rr */ +/* Table2951 */ + 0xfc, /* BEXTR32rm */ + 0xfd, /* BEXTR32rr */ +/* Table2953 */ + 0x400, /* PEXT32rm */ + 0x401, /* PEXT32rr */ +/* Table2955 */ + 0x4f8, /* SARX32rm */ + 0x4f9, /* SARX32rr */ +/* Table2957 */ + 0x3fc, /* PDEP32rm */ + 0x3fd, /* PDEP32rr */ +/* Table2959 */ + 0x39a, /* MULX32rm */ + 0x39b, /* MULX32rr */ +/* Table2961 */ + 0x595, /* SHRX32rm */ + 0x596, /* SHRX32rr */ +/* Table2963 */ + 0x56d, /* SHLX32rm */ + 0x56e, /* SHLX32rr */ +/* Table2965 */ + 0xf8, /* ANDN64rm */ + 0xf9, /* ANDN64rr */ +/* Table2967 */ + 0x0, /* */ + 0x12a, /* BLSR64rm */ + 0x126, /* BLSMSK64rm */ + 0x11e, /* BLSI64rm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x12b, /* BLSR64rr */ + 0x127, /* BLSMSK64rr */ + 0x11f, /* BLSI64rr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table2983 */ + 0x16f, /* BZHI64rm */ + 0x170, /* BZHI64rr */ +/* Table2985 */ + 0xfe, /* BEXTR64rm */ + 0xff, /* BEXTR64rr */ +/* Table2987 */ + 0x402, /* PEXT64rm */ + 0x403, /* PEXT64rr */ +/* Table2989 */ + 0x4fa, /* SARX64rm */ + 0x4fb, /* SARX64rr */ +/* Table2991 */ + 0x3fe, /* PDEP64rm */ + 0x3ff, /* PDEP64rr */ +/* Table2993 */ + 0x39c, /* MULX64rm */ + 0x39d, /* MULX64rr */ +/* Table2995 */ + 0x597, /* SHRX64rm */ + 0x598, /* SHRX64rr */ +/* Table2997 */ + 0x56f, /* SHLX64rm */ + 0x570, /* SHLX64rr */ +/* Table2999 */ + 0x4c0, /* RORX32mi */ + 0x4c1, /* RORX32ri */ +/* Table3001 */ + 0x4c2, /* RORX64mi */ + 0x4c3, /* RORX64ri */ +/* Table3003 */ + 0x0, /* */ + 0x104, /* BLCFILL32rm */ + 0x118, /* BLSFILL32rm */ + 0x114, /* BLCS32rm */ + 0x606, /* TZMSK32rm */ + 0x10c, /* BLCIC32rm */ + 0x120, /* BLSIC32rm */ + 0x5df, /* T1MSKC32rm */ + 0x0, /* */ + 0x105, /* BLCFILL32rr */ + 0x119, /* BLSFILL32rr */ + 0x115, /* BLCS32rr */ + 0x607, /* TZMSK32rr */ + 0x10d, /* BLCIC32rr */ + 0x121, /* BLSIC32rr */ + 0x5e0, /* T1MSKC32rr */ +/* Table3019 */ + 0x0, /* */ + 0x110, /* BLCMSK32rm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x108, /* BLCI32rm */ + 0x0, /* */ + 0x0, /* */ + 0x111, /* BLCMSK32rr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x109, /* BLCI32rr */ + 0x0, /* */ +/* Table3035 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x2f3, /* LLWPCB */ + 0x5a1, /* SLWPCB */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table3051 */ + 0x0, /* */ + 0x106, /* BLCFILL64rm */ + 0x11a, /* BLSFILL64rm */ + 0x116, /* BLCS64rm */ + 0x608, /* TZMSK64rm */ + 0x10e, /* BLCIC64rm */ + 0x122, /* BLSIC64rm */ + 0x5e1, /* T1MSKC64rm */ + 0x0, /* */ + 0x107, /* BLCFILL64rr */ + 0x11b, /* BLSFILL64rr */ + 0x117, /* BLCS64rr */ + 0x609, /* TZMSK64rr */ + 0x10f, /* BLCIC64rr */ + 0x123, /* BLSIC64rr */ + 0x5e2, /* T1MSKC64rr */ +/* Table3067 */ + 0x0, /* */ + 0x112, /* BLCMSK64rm */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x10a, /* BLCI64rm */ + 0x0, /* */ + 0x0, /* */ + 0x113, /* BLCMSK64rr */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x10b, /* BLCI64rr */ + 0x0, /* */ +/* Table3083 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x2f4, /* LLWPCB64 */ + 0x5a2, /* SLWPCB64 */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table3099 */ + 0x100, /* BEXTRI32mi */ + 0x101, /* BEXTRI32ri */ +/* Table3101 */ + 0x310, /* LWPINS32rmi */ + 0x314, /* LWPVAL32rmi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x311, /* LWPINS32rri */ + 0x315, /* LWPVAL32rri */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ +/* Table3117 */ + 0x102, /* BEXTRI64mi */ + 0x103, /* BEXTRI64ri */ +/* Table3119 */ + 0x312, /* LWPINS64rmi */ + 0x316, /* LWPVAL64rmi */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x313, /* LWPINS64rri */ + 0x317, /* LWPVAL64rri */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0, /* */ + 0x0 +}; + diff --git a/thirdparty/capstone/arch/X86/X86GenDisassemblerTables_reduce2.inc b/thirdparty/capstone/arch/X86/X86GenDisassemblerTables_reduce2.inc new file mode 100644 index 0000000..7bd8e1e --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenDisassemblerTables_reduce2.inc @@ -0,0 +1,18827 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +static const unsigned char index_x86DisassemblerOneByteOpcodes[] = { + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 0, + 0, + 0, + 0, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 0, + 0, + 15, + 16, + 17, + 18, + 19, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +static const struct OpcodeDecision x86DisassemblerOneByteOpcodes[] = { + { { + { MODRM_SPLITRM, 1 }, + { MODRM_SPLITRM, 3 }, + { MODRM_SPLITRM, 5 }, + { MODRM_SPLITRM, 7 }, + { MODRM_ONEENTRY, 9 }, + { MODRM_ONEENTRY, 10 }, + { MODRM_ONEENTRY, 11 }, + { MODRM_ONEENTRY, 12 }, + { MODRM_SPLITRM, 13 }, + { MODRM_SPLITRM, 15 }, + { MODRM_SPLITRM, 17 }, + { MODRM_SPLITRM, 19 }, + { MODRM_ONEENTRY, 21 }, + { MODRM_ONEENTRY, 22 }, + { MODRM_ONEENTRY, 23 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 24 }, + { MODRM_SPLITRM, 26 }, + { MODRM_SPLITRM, 28 }, + { MODRM_SPLITRM, 30 }, + { MODRM_ONEENTRY, 32 }, + { MODRM_ONEENTRY, 33 }, + { MODRM_ONEENTRY, 34 }, + { MODRM_ONEENTRY, 35 }, + { MODRM_SPLITRM, 36 }, + { MODRM_SPLITRM, 38 }, + { MODRM_SPLITRM, 40 }, + { MODRM_SPLITRM, 42 }, + { MODRM_ONEENTRY, 44 }, + { MODRM_ONEENTRY, 45 }, + { MODRM_ONEENTRY, 46 }, + { MODRM_ONEENTRY, 47 }, + { MODRM_SPLITRM, 48 }, + { MODRM_SPLITRM, 50 }, + { MODRM_SPLITRM, 52 }, + { MODRM_SPLITRM, 54 }, + { MODRM_ONEENTRY, 56 }, + { MODRM_ONEENTRY, 57 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 58 }, + { MODRM_SPLITRM, 59 }, + { MODRM_SPLITRM, 61 }, + { MODRM_SPLITRM, 63 }, + { MODRM_SPLITRM, 65 }, + { MODRM_ONEENTRY, 67 }, + { MODRM_ONEENTRY, 68 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 69 }, + { MODRM_SPLITRM, 70 }, + { MODRM_SPLITRM, 72 }, + { MODRM_SPLITRM, 74 }, + { MODRM_SPLITRM, 76 }, + { MODRM_ONEENTRY, 78 }, + { MODRM_ONEENTRY, 79 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 80 }, + { MODRM_SPLITRM, 81 }, + { MODRM_SPLITRM, 83 }, + { MODRM_SPLITRM, 85 }, + { MODRM_SPLITRM, 87 }, + { MODRM_ONEENTRY, 89 }, + { MODRM_ONEENTRY, 90 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 91 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 92 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 93 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 94 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 95 }, + { MODRM_ONEENTRY, 96 }, + { MODRM_ONEENTRY, 97 }, + { MODRM_SPLITRM, 98 }, + { MODRM_SPLITRM, 100 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 102 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 103 }, + { MODRM_SPLITRM, 104 }, + { MODRM_ONEENTRY, 106 }, + { MODRM_SPLITRM, 107 }, + { MODRM_ONEENTRY, 109 }, + { MODRM_ONEENTRY, 110 }, + { MODRM_ONEENTRY, 111 }, + { MODRM_ONEENTRY, 112 }, + { MODRM_ONEENTRY, 113 }, + { MODRM_ONEENTRY, 114 }, + { MODRM_ONEENTRY, 115 }, + { MODRM_ONEENTRY, 116 }, + { MODRM_ONEENTRY, 117 }, + { MODRM_ONEENTRY, 118 }, + { MODRM_ONEENTRY, 119 }, + { MODRM_ONEENTRY, 120 }, + { MODRM_ONEENTRY, 121 }, + { MODRM_ONEENTRY, 122 }, + { MODRM_ONEENTRY, 123 }, + { MODRM_ONEENTRY, 124 }, + { MODRM_ONEENTRY, 125 }, + { MODRM_ONEENTRY, 126 }, + { MODRM_ONEENTRY, 127 }, + { MODRM_ONEENTRY, 128 }, + { MODRM_SPLITREG, 129 }, + { MODRM_SPLITREG, 145 }, + { MODRM_SPLITREG, 161 }, + { MODRM_SPLITREG, 177 }, + { MODRM_SPLITRM, 193 }, + { MODRM_SPLITRM, 195 }, + { MODRM_SPLITRM, 197 }, + { MODRM_SPLITRM, 199 }, + { MODRM_SPLITRM, 201 }, + { MODRM_SPLITRM, 203 }, + { MODRM_SPLITRM, 205 }, + { MODRM_SPLITRM, 207 }, + { MODRM_SPLITRM, 209 }, + { MODRM_SPLITRM, 211 }, + { MODRM_SPLITRM, 213 }, + { MODRM_SPLITREG, 215 }, + { MODRM_ONEENTRY, 231 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 232 }, + { MODRM_ONEENTRY, 233 }, + { MODRM_ONEENTRY, 234 }, + { MODRM_ONEENTRY, 235 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 236 }, + { MODRM_ONEENTRY, 237 }, + { MODRM_ONEENTRY, 238 }, + { MODRM_ONEENTRY, 239 }, + { MODRM_ONEENTRY, 240 }, + { MODRM_ONEENTRY, 241 }, + { MODRM_ONEENTRY, 242 }, + { MODRM_ONEENTRY, 243 }, + { MODRM_ONEENTRY, 244 }, + { MODRM_ONEENTRY, 245 }, + { MODRM_ONEENTRY, 246 }, + { MODRM_ONEENTRY, 247 }, + { MODRM_ONEENTRY, 248 }, + { MODRM_ONEENTRY, 249 }, + { MODRM_ONEENTRY, 250 }, + { MODRM_ONEENTRY, 251 }, + { MODRM_ONEENTRY, 252 }, + { MODRM_ONEENTRY, 253 }, + { MODRM_ONEENTRY, 254 }, + { MODRM_ONEENTRY, 255 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_ONEENTRY, 257 }, + { MODRM_SPLITREG, 258 }, + { MODRM_SPLITREG, 274 }, + { MODRM_ONEENTRY, 290 }, + { MODRM_ONEENTRY, 291 }, + { MODRM_SPLITRM, 292 }, + { MODRM_SPLITRM, 294 }, + { MODRM_SPLITREG, 296 }, + { MODRM_SPLITREG, 312 }, + { MODRM_ONEENTRY, 328 }, + { MODRM_ONEENTRY, 329 }, + { MODRM_ONEENTRY, 330 }, + { MODRM_ONEENTRY, 331 }, + { MODRM_ONEENTRY, 332 }, + { MODRM_ONEENTRY, 333 }, + { MODRM_ONEENTRY, 334 }, + { MODRM_ONEENTRY, 335 }, + { MODRM_SPLITREG, 336 }, + { MODRM_SPLITREG, 352 }, + { MODRM_SPLITREG, 368 }, + { MODRM_SPLITREG, 384 }, + { MODRM_ONEENTRY, 400 }, + { MODRM_ONEENTRY, 401 }, + { MODRM_ONEENTRY, 402 }, + { MODRM_ONEENTRY, 403 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITMISC, 404 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 476 }, + { MODRM_ONEENTRY, 477 }, + { MODRM_ONEENTRY, 478 }, + { MODRM_ONEENTRY, 479 }, + { MODRM_ONEENTRY, 480 }, + { MODRM_ONEENTRY, 481 }, + { MODRM_ONEENTRY, 482 }, + { MODRM_ONEENTRY, 483 }, + { MODRM_ONEENTRY, 484 }, + { MODRM_ONEENTRY, 485 }, + { MODRM_ONEENTRY, 486 }, + { MODRM_ONEENTRY, 487 }, + { MODRM_ONEENTRY, 488 }, + { MODRM_ONEENTRY, 489 }, + { MODRM_ONEENTRY, 490 }, + { MODRM_ONEENTRY, 491 }, + { MODRM_ONEENTRY, 492 }, + { MODRM_ONEENTRY, 493 }, + { MODRM_ONEENTRY, 494 }, + { MODRM_ONEENTRY, 495 }, + { MODRM_ONEENTRY, 496 }, + { MODRM_ONEENTRY, 497 }, + { MODRM_SPLITREG, 498 }, + { MODRM_SPLITREG, 514 }, + { MODRM_ONEENTRY, 530 }, + { MODRM_ONEENTRY, 531 }, + { MODRM_ONEENTRY, 532 }, + { MODRM_ONEENTRY, 533 }, + { MODRM_ONEENTRY, 534 }, + { MODRM_ONEENTRY, 535 }, + { MODRM_SPLITREG, 536 }, + { MODRM_SPLITREG, 552 }, + } }, + { { + { MODRM_SPLITRM, 1 }, + { MODRM_SPLITRM, 3 }, + { MODRM_SPLITRM, 5 }, + { MODRM_SPLITRM, 7 }, + { MODRM_ONEENTRY, 9 }, + { MODRM_ONEENTRY, 10 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 13 }, + { MODRM_SPLITRM, 15 }, + { MODRM_SPLITRM, 17 }, + { MODRM_SPLITRM, 19 }, + { MODRM_ONEENTRY, 21 }, + { MODRM_ONEENTRY, 22 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 24 }, + { MODRM_SPLITRM, 26 }, + { MODRM_SPLITRM, 28 }, + { MODRM_SPLITRM, 30 }, + { MODRM_ONEENTRY, 32 }, + { MODRM_ONEENTRY, 33 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 36 }, + { MODRM_SPLITRM, 38 }, + { MODRM_SPLITRM, 40 }, + { MODRM_SPLITRM, 42 }, + { MODRM_ONEENTRY, 44 }, + { MODRM_ONEENTRY, 45 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 48 }, + { MODRM_SPLITRM, 50 }, + { MODRM_SPLITRM, 52 }, + { MODRM_SPLITRM, 54 }, + { MODRM_ONEENTRY, 56 }, + { MODRM_ONEENTRY, 57 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 59 }, + { MODRM_SPLITRM, 61 }, + { MODRM_SPLITRM, 63 }, + { MODRM_SPLITRM, 65 }, + { MODRM_ONEENTRY, 67 }, + { MODRM_ONEENTRY, 68 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 70 }, + { MODRM_SPLITRM, 72 }, + { MODRM_SPLITRM, 74 }, + { MODRM_SPLITRM, 76 }, + { MODRM_ONEENTRY, 78 }, + { MODRM_ONEENTRY, 79 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 81 }, + { MODRM_SPLITRM, 83 }, + { MODRM_SPLITRM, 85 }, + { MODRM_SPLITRM, 87 }, + { MODRM_ONEENTRY, 89 }, + { MODRM_ONEENTRY, 90 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 568 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { 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+ { MODRM_SPLITRM, 13 }, + { MODRM_SPLITRM, 882 }, + { MODRM_SPLITRM, 17 }, + { MODRM_SPLITRM, 884 }, + { MODRM_ONEENTRY, 21 }, + { MODRM_ONEENTRY, 886 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 24 }, + { MODRM_SPLITRM, 887 }, + { MODRM_SPLITRM, 28 }, + { MODRM_SPLITRM, 889 }, + { MODRM_ONEENTRY, 32 }, + { MODRM_ONEENTRY, 891 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 36 }, + { MODRM_SPLITRM, 892 }, + { MODRM_SPLITRM, 40 }, + { MODRM_SPLITRM, 894 }, + { MODRM_ONEENTRY, 44 }, + { MODRM_ONEENTRY, 896 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 48 }, + { MODRM_SPLITRM, 897 }, + { MODRM_SPLITRM, 52 }, + { MODRM_SPLITRM, 899 }, + { MODRM_ONEENTRY, 56 }, + { MODRM_ONEENTRY, 901 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 59 }, + { MODRM_SPLITRM, 902 }, + { MODRM_SPLITRM, 63 }, + { MODRM_SPLITRM, 904 }, + { MODRM_ONEENTRY, 67 }, + { MODRM_ONEENTRY, 906 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 70 }, + { MODRM_SPLITRM, 907 }, + { MODRM_SPLITRM, 74 }, + { MODRM_SPLITRM, 909 }, + { MODRM_ONEENTRY, 78 }, + { MODRM_ONEENTRY, 911 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 81 }, + { MODRM_SPLITRM, 912 }, + { MODRM_SPLITRM, 85 }, + { MODRM_SPLITRM, 914 }, + { MODRM_ONEENTRY, 89 }, + { MODRM_ONEENTRY, 916 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 568 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 569 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 570 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 917 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 102 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 571 }, + { MODRM_SPLITRM, 919 }, + { MODRM_ONEENTRY, 572 }, + { MODRM_SPLITRM, 921 }, + { MODRM_ONEENTRY, 109 }, + { MODRM_ONEENTRY, 110 }, + { MODRM_ONEENTRY, 111 }, + { MODRM_ONEENTRY, 112 }, + { MODRM_ONEENTRY, 113 }, + { MODRM_ONEENTRY, 114 }, + { MODRM_ONEENTRY, 115 }, + { MODRM_ONEENTRY, 116 }, + { MODRM_ONEENTRY, 117 }, + { MODRM_ONEENTRY, 118 }, + { MODRM_ONEENTRY, 119 }, + { MODRM_ONEENTRY, 120 }, + { MODRM_ONEENTRY, 121 }, + { MODRM_ONEENTRY, 122 }, + { MODRM_ONEENTRY, 123 }, + { MODRM_ONEENTRY, 124 }, + { MODRM_ONEENTRY, 125 }, + { MODRM_ONEENTRY, 126 }, + { MODRM_ONEENTRY, 127 }, + { MODRM_ONEENTRY, 128 }, + { MODRM_SPLITREG, 129 }, + { MODRM_SPLITREG, 923 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 939 }, + { MODRM_SPLITRM, 193 }, + { MODRM_SPLITRM, 955 }, + { MODRM_SPLITRM, 197 }, + { MODRM_SPLITRM, 957 }, + { MODRM_SPLITRM, 201 }, + { MODRM_SPLITRM, 959 }, + { MODRM_SPLITRM, 205 }, + { MODRM_SPLITRM, 961 }, + { MODRM_SPLITRM, 963 }, + { MODRM_SPLITRM, 965 }, + { MODRM_SPLITRM, 967 }, + { MODRM_SPLITREG, 575 }, + { MODRM_ONEENTRY, 231 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 970 }, + { MODRM_ONEENTRY, 971 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 591 }, + { MODRM_ONEENTRY, 592 }, + { MODRM_ONEENTRY, 238 }, + { MODRM_ONEENTRY, 239 }, + { MODRM_ONEENTRY, 593 }, + { MODRM_ONEENTRY, 972 }, + { MODRM_ONEENTRY, 595 }, + { MODRM_ONEENTRY, 973 }, + { MODRM_ONEENTRY, 244 }, + { MODRM_ONEENTRY, 974 }, + { MODRM_ONEENTRY, 246 }, + { MODRM_ONEENTRY, 975 }, + { MODRM_ONEENTRY, 248 }, + { MODRM_ONEENTRY, 976 }, + { MODRM_ONEENTRY, 250 }, + { MODRM_ONEENTRY, 977 }, + { MODRM_ONEENTRY, 252 }, + { MODRM_ONEENTRY, 978 }, + { MODRM_ONEENTRY, 254 }, + { MODRM_ONEENTRY, 979 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_SPLITREG, 258 }, + { MODRM_SPLITREG, 981 }, + { MODRM_ONEENTRY, 597 }, + { MODRM_ONEENTRY, 598 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 296 }, + { MODRM_SPLITREG, 997 }, + { MODRM_ONEENTRY, 328 }, + { MODRM_ONEENTRY, 599 }, + { MODRM_ONEENTRY, 1013 }, + { MODRM_ONEENTRY, 1014 }, + { MODRM_ONEENTRY, 332 }, + { MODRM_ONEENTRY, 333 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1015 }, + { MODRM_SPLITREG, 336 }, + { MODRM_SPLITREG, 1016 }, + { MODRM_SPLITREG, 368 }, + { MODRM_SPLITREG, 1032 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 403 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITMISC, 404 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 476 }, + { MODRM_ONEENTRY, 477 }, + { MODRM_ONEENTRY, 478 }, + { MODRM_ONEENTRY, 600 }, + { MODRM_ONEENTRY, 480 }, + { MODRM_ONEENTRY, 481 }, + { MODRM_ONEENTRY, 482 }, + { MODRM_ONEENTRY, 483 }, + { MODRM_ONEENTRY, 601 }, + { MODRM_ONEENTRY, 485 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 487 }, + { MODRM_ONEENTRY, 488 }, + { MODRM_ONEENTRY, 489 }, + { MODRM_ONEENTRY, 490 }, + { MODRM_ONEENTRY, 491 }, + { MODRM_ONEENTRY, 492 }, + { MODRM_ONEENTRY, 493 }, + { MODRM_ONEENTRY, 494 }, + { MODRM_ONEENTRY, 495 }, + { MODRM_ONEENTRY, 496 }, + { MODRM_ONEENTRY, 497 }, + { MODRM_SPLITREG, 498 }, + { MODRM_SPLITREG, 1048 }, + { MODRM_ONEENTRY, 530 }, + { MODRM_ONEENTRY, 531 }, + { MODRM_ONEENTRY, 532 }, + { MODRM_ONEENTRY, 533 }, + { MODRM_ONEENTRY, 534 }, + { MODRM_ONEENTRY, 535 }, + { MODRM_SPLITREG, 536 }, + { MODRM_SPLITREG, 1064 }, + } }, + { { + { MODRM_SPLITRM, 1 }, + { MODRM_SPLITRM, 877 }, + { MODRM_SPLITRM, 5 }, + { MODRM_SPLITRM, 879 }, + { MODRM_ONEENTRY, 9 }, + { MODRM_ONEENTRY, 881 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 13 }, + { MODRM_SPLITRM, 882 }, + { MODRM_SPLITRM, 17 }, + { MODRM_SPLITRM, 884 }, + { MODRM_ONEENTRY, 21 }, + { MODRM_ONEENTRY, 886 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 24 }, + { MODRM_SPLITRM, 887 }, + { MODRM_SPLITRM, 28 }, + { MODRM_SPLITRM, 889 }, + { MODRM_ONEENTRY, 32 }, + { MODRM_ONEENTRY, 891 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 36 }, + { MODRM_SPLITRM, 892 }, + { MODRM_SPLITRM, 40 }, + { MODRM_SPLITRM, 894 }, + { MODRM_ONEENTRY, 44 }, + { MODRM_ONEENTRY, 896 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 48 }, + { MODRM_SPLITRM, 897 }, + { MODRM_SPLITRM, 52 }, + { MODRM_SPLITRM, 899 }, + { MODRM_ONEENTRY, 56 }, + { MODRM_ONEENTRY, 901 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 59 }, + { MODRM_SPLITRM, 902 }, + { MODRM_SPLITRM, 63 }, + { MODRM_SPLITRM, 904 }, + { MODRM_ONEENTRY, 67 }, + { MODRM_ONEENTRY, 906 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 70 }, + { MODRM_SPLITRM, 907 }, + { MODRM_SPLITRM, 74 }, + { MODRM_SPLITRM, 909 }, + { MODRM_ONEENTRY, 78 }, + { MODRM_ONEENTRY, 911 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 81 }, + { MODRM_SPLITRM, 912 }, + { MODRM_SPLITRM, 85 }, + { MODRM_SPLITRM, 914 }, + { MODRM_ONEENTRY, 89 }, + { MODRM_ONEENTRY, 916 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 568 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 667 }, + { MODRM_ONEENTRY, 667 }, + { MODRM_ONEENTRY, 667 }, + { MODRM_ONEENTRY, 667 }, + { MODRM_ONEENTRY, 667 }, + { MODRM_ONEENTRY, 667 }, + { MODRM_ONEENTRY, 667 }, + { MODRM_ONEENTRY, 667 }, + { MODRM_ONEENTRY, 668 }, + { MODRM_ONEENTRY, 668 }, + { MODRM_ONEENTRY, 668 }, + { MODRM_ONEENTRY, 668 }, + { MODRM_ONEENTRY, 668 }, + { MODRM_ONEENTRY, 668 }, + { MODRM_ONEENTRY, 668 }, + { MODRM_ONEENTRY, 668 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 917 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 102 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 673 }, + { MODRM_SPLITRM, 919 }, + { MODRM_ONEENTRY, 676 }, + { MODRM_SPLITRM, 921 }, + { MODRM_ONEENTRY, 109 }, + { MODRM_ONEENTRY, 679 }, + { MODRM_ONEENTRY, 111 }, + { MODRM_ONEENTRY, 680 }, + { MODRM_ONEENTRY, 113 }, + { MODRM_ONEENTRY, 114 }, + { MODRM_ONEENTRY, 115 }, + { MODRM_ONEENTRY, 116 }, + { MODRM_ONEENTRY, 117 }, + { MODRM_ONEENTRY, 118 }, + { MODRM_ONEENTRY, 119 }, + { MODRM_ONEENTRY, 120 }, + { MODRM_ONEENTRY, 121 }, + { MODRM_ONEENTRY, 122 }, + { MODRM_ONEENTRY, 123 }, + { MODRM_ONEENTRY, 124 }, + { MODRM_ONEENTRY, 125 }, + { MODRM_ONEENTRY, 126 }, + { MODRM_ONEENTRY, 127 }, + { MODRM_ONEENTRY, 128 }, + { MODRM_SPLITREG, 129 }, + { MODRM_SPLITREG, 923 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 939 }, + { MODRM_SPLITRM, 193 }, + { MODRM_SPLITRM, 955 }, + { MODRM_SPLITRM, 197 }, + { MODRM_SPLITRM, 957 }, + { MODRM_SPLITRM, 201 }, + { MODRM_SPLITRM, 959 }, + { MODRM_SPLITRM, 205 }, + { MODRM_SPLITRM, 961 }, + { MODRM_SPLITRM, 963 }, + { MODRM_SPLITRM, 965 }, + { MODRM_SPLITRM, 967 }, + { MODRM_SPLITREG, 727 }, + { MODRM_ONEENTRY, 231 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 969 }, + { MODRM_ONEENTRY, 970 }, + { MODRM_ONEENTRY, 971 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 747 }, + { MODRM_ONEENTRY, 748 }, + { MODRM_ONEENTRY, 238 }, + { MODRM_ONEENTRY, 239 }, + { MODRM_ONEENTRY, 593 }, + { MODRM_ONEENTRY, 972 }, + { MODRM_ONEENTRY, 595 }, + { MODRM_ONEENTRY, 973 }, + { MODRM_ONEENTRY, 244 }, + { MODRM_ONEENTRY, 974 }, + { MODRM_ONEENTRY, 246 }, + { MODRM_ONEENTRY, 975 }, + { MODRM_ONEENTRY, 248 }, + { MODRM_ONEENTRY, 976 }, + { MODRM_ONEENTRY, 250 }, + { MODRM_ONEENTRY, 977 }, + { MODRM_ONEENTRY, 252 }, + { MODRM_ONEENTRY, 978 }, + { MODRM_ONEENTRY, 254 }, + { MODRM_ONEENTRY, 979 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 256 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_ONEENTRY, 980 }, + { MODRM_SPLITREG, 258 }, + { MODRM_SPLITREG, 981 }, + { MODRM_ONEENTRY, 774 }, + { MODRM_ONEENTRY, 775 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 296 }, + { MODRM_SPLITREG, 997 }, + { MODRM_ONEENTRY, 328 }, + { MODRM_ONEENTRY, 599 }, + { MODRM_ONEENTRY, 1013 }, + { MODRM_ONEENTRY, 1014 }, + { MODRM_ONEENTRY, 332 }, + { MODRM_ONEENTRY, 333 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1015 }, + { MODRM_SPLITREG, 336 }, + { MODRM_SPLITREG, 1016 }, + { MODRM_SPLITREG, 368 }, + { MODRM_SPLITREG, 1032 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 403 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITMISC, 404 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 476 }, + { MODRM_ONEENTRY, 477 }, + { MODRM_ONEENTRY, 478 }, + { MODRM_ONEENTRY, 600 }, + { MODRM_ONEENTRY, 480 }, + { MODRM_ONEENTRY, 831 }, + { MODRM_ONEENTRY, 482 }, + { MODRM_ONEENTRY, 832 }, + { MODRM_ONEENTRY, 833 }, + { MODRM_ONEENTRY, 834 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 487 }, + { MODRM_ONEENTRY, 488 }, + { MODRM_ONEENTRY, 836 }, + { MODRM_ONEENTRY, 490 }, + { MODRM_ONEENTRY, 837 }, + { MODRM_ONEENTRY, 492 }, + { MODRM_ONEENTRY, 493 }, + { MODRM_ONEENTRY, 494 }, + { MODRM_ONEENTRY, 495 }, + { MODRM_ONEENTRY, 496 }, + { MODRM_ONEENTRY, 497 }, + { MODRM_SPLITREG, 498 }, + { MODRM_SPLITREG, 1048 }, + { MODRM_ONEENTRY, 530 }, + { MODRM_ONEENTRY, 531 }, + { MODRM_ONEENTRY, 532 }, + { MODRM_ONEENTRY, 533 }, + { MODRM_ONEENTRY, 534 }, + { MODRM_ONEENTRY, 535 }, + { MODRM_SPLITREG, 536 }, + { MODRM_SPLITREG, 1082 }, + } }, +}; + +static const unsigned char index_x86DisassemblerTwoByteOpcodes[] = { + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 0, + 8, + 0, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 0, + 17, + 18, + 19, + 20, + 21, + 22, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +static const struct OpcodeDecision x86DisassemblerTwoByteOpcodes[] = { + { { + { MODRM_SPLITREG, 1116 }, + { MODRM_SPLITMISC, 1132 }, + { MODRM_SPLITRM, 1204 }, + { MODRM_SPLITRM, 1206 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1208 }, + { MODRM_ONEENTRY, 1209 }, + { MODRM_ONEENTRY, 1210 }, + { MODRM_ONEENTRY, 1211 }, + { MODRM_ONEENTRY, 1212 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1213 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 1214 }, + { MODRM_SPLITRM, 1230 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 1232 }, + { MODRM_SPLITRM, 1248 }, + { MODRM_SPLITRM, 1250 }, + { MODRM_SPLITRM, 1252 }, + { MODRM_SPLITRM, 1254 }, + { MODRM_SPLITRM, 1256 }, + { MODRM_SPLITRM, 1258 }, + { MODRM_SPLITRM, 1260 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1262 }, + { MODRM_ONEENTRY, 1263 }, + { MODRM_ONEENTRY, 1264 }, + { MODRM_ONEENTRY, 1265 }, + { MODRM_ONEENTRY, 1266 }, + { MODRM_ONEENTRY, 1267 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1268 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1269 }, + { MODRM_SPLITRM, 1271 }, + { MODRM_SPLITRM, 1273 }, + { MODRM_SPLITRM, 1275 }, + { MODRM_SPLITRM, 1277 }, + { MODRM_SPLITRM, 1279 }, + { MODRM_SPLITRM, 1281 }, + { MODRM_SPLITRM, 1283 }, + { MODRM_SPLITRM, 1285 }, + { MODRM_SPLITRM, 1287 }, + { MODRM_SPLITRM, 1289 }, + { MODRM_SPLITRM, 1291 }, + { MODRM_SPLITRM, 1293 }, + { MODRM_SPLITRM, 1295 }, + { MODRM_SPLITRM, 1297 }, + { MODRM_SPLITRM, 1299 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1301 }, + { MODRM_SPLITRM, 1303 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1305 }, + { MODRM_ONEENTRY, 1306 }, + { MODRM_ONEENTRY, 1307 }, + { MODRM_ONEENTRY, 1308 }, + { MODRM_ONEENTRY, 1309 }, + { MODRM_ONEENTRY, 1310 }, + { MODRM_ONEENTRY, 1311 }, + { MODRM_ONEENTRY, 1312 }, + { MODRM_ONEENTRY, 1313 }, + { MODRM_ONEENTRY, 1314 }, + { MODRM_ONEENTRY, 1315 }, + { MODRM_ONEENTRY, 1316 }, + { MODRM_ONEENTRY, 1317 }, + { MODRM_ONEENTRY, 1318 }, + { MODRM_ONEENTRY, 1319 }, + { MODRM_ONEENTRY, 1320 }, + { MODRM_SPLITRM, 1321 }, + { MODRM_SPLITRM, 1323 }, + { MODRM_SPLITRM, 1325 }, + { MODRM_SPLITRM, 1327 }, + { MODRM_SPLITRM, 1329 }, + { MODRM_SPLITRM, 1331 }, + { MODRM_SPLITRM, 1333 }, + { MODRM_SPLITRM, 1335 }, + { MODRM_SPLITRM, 1337 }, + { MODRM_SPLITRM, 1339 }, + { MODRM_SPLITRM, 1341 }, + { MODRM_SPLITRM, 1343 }, + { MODRM_SPLITRM, 1345 }, + { MODRM_SPLITRM, 1347 }, + { MODRM_SPLITRM, 1349 }, + { MODRM_SPLITRM, 1351 }, + { MODRM_ONEENTRY, 1353 }, + { MODRM_ONEENTRY, 1354 }, + { MODRM_ONEENTRY, 1355 }, + { MODRM_SPLITRM, 1356 }, + { MODRM_SPLITRM, 1358 }, + { MODRM_SPLITRM, 1360 }, + { MODRM_SPLITMISC, 1362 }, + { MODRM_SPLITMISC, 1434 }, + { MODRM_ONEENTRY, 1506 }, + { MODRM_ONEENTRY, 1507 }, + { MODRM_ONEENTRY, 1508 }, + { MODRM_SPLITRM, 1509 }, + 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{ MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1208 }, + { MODRM_ONEENTRY, 1209 }, + { MODRM_ONEENTRY, 2302 }, + { MODRM_ONEENTRY, 1211 }, + { MODRM_ONEENTRY, 1212 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1213 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 1778 }, + { MODRM_SPLITRM, 1794 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1796 }, + { MODRM_SPLITRM, 1798 }, + { MODRM_SPLITRM, 1800 }, + { MODRM_SPLITRM, 2303 }, + { MODRM_SPLITRM, 1670 }, + { MODRM_SPLITRM, 1672 }, + { MODRM_SPLITRM, 1674 }, + { MODRM_SPLITRM, 1676 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1262 }, + { MODRM_ONEENTRY, 1263 }, + { MODRM_ONEENTRY, 1264 }, + { MODRM_ONEENTRY, 1265 }, + { MODRM_ONEENTRY, 1266 }, + { MODRM_ONEENTRY, 2305 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1268 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2306 }, + { MODRM_SPLITRM, 2308 }, + { MODRM_SPLITRM, 2310 }, + { MODRM_SPLITRM, 2312 }, + { MODRM_SPLITRM, 2314 }, + { MODRM_SPLITRM, 2316 }, + { MODRM_SPLITRM, 2318 }, + { MODRM_SPLITRM, 2320 }, + { MODRM_SPLITRM, 2322 }, + { MODRM_SPLITRM, 2324 }, + { MODRM_SPLITRM, 2326 }, + { MODRM_SPLITRM, 2328 }, + { MODRM_SPLITRM, 2330 }, + { MODRM_SPLITRM, 2332 }, + { MODRM_SPLITRM, 2334 }, + { MODRM_SPLITRM, 2336 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 1678 }, + { MODRM_SPLITRM, 1680 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1836 }, + { MODRM_ONEENTRY, 1837 }, + { MODRM_ONEENTRY, 1838 }, + { MODRM_ONEENTRY, 1839 }, + { MODRM_ONEENTRY, 1840 }, + { MODRM_ONEENTRY, 1841 }, + { MODRM_ONEENTRY, 1842 }, + { MODRM_ONEENTRY, 1843 }, + { MODRM_ONEENTRY, 1844 }, + { MODRM_ONEENTRY, 1845 }, + { MODRM_ONEENTRY, 1846 }, + { MODRM_ONEENTRY, 1847 }, + { MODRM_ONEENTRY, 1848 }, + { MODRM_ONEENTRY, 1849 }, + { MODRM_ONEENTRY, 1850 }, + { MODRM_ONEENTRY, 1851 }, + { MODRM_SPLITRM, 1321 }, + { MODRM_SPLITRM, 1323 }, + { MODRM_SPLITRM, 1325 }, + { MODRM_SPLITRM, 1327 }, + { MODRM_SPLITRM, 1329 }, + { MODRM_SPLITRM, 1331 }, + { MODRM_SPLITRM, 1333 }, + { MODRM_SPLITRM, 1335 }, + { MODRM_SPLITRM, 1337 }, + { MODRM_SPLITRM, 1339 }, + { MODRM_SPLITRM, 1341 }, + { MODRM_SPLITRM, 1343 }, + { MODRM_SPLITRM, 1345 }, + { MODRM_SPLITRM, 1347 }, + { MODRM_SPLITRM, 1349 }, + { MODRM_SPLITRM, 1351 }, + { MODRM_ONEENTRY, 1852 }, + { MODRM_ONEENTRY, 1853 }, + { MODRM_ONEENTRY, 1355 }, + { MODRM_SPLITRM, 2338 }, + { MODRM_SPLITRM, 2340 }, + { MODRM_SPLITRM, 2342 }, + { MODRM_SPLITMISC, 1362 }, + { MODRM_SPLITMISC, 1434 }, + { MODRM_ONEENTRY, 1860 }, + { MODRM_ONEENTRY, 1861 }, + { MODRM_ONEENTRY, 1508 }, + { MODRM_SPLITRM, 2344 }, + { MODRM_SPLITRM, 2346 }, + { MODRM_SPLITRM, 2348 }, + { MODRM_SPLITREG, 1945 }, + { MODRM_SPLITRM, 2366 }, + { MODRM_SPLITRM, 1533 }, + { MODRM_SPLITRM, 2368 }, + { MODRM_SPLITRM, 2370 }, + { MODRM_SPLITRM, 2372 }, + { MODRM_SPLITRM, 2374 }, + { MODRM_SPLITRM, 2376 }, + { MODRM_SPLITRM, 2378 }, + { MODRM_SPLITRM, 2380 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1549 }, + { MODRM_SPLITREG, 2382 }, + { MODRM_SPLITRM, 2398 }, + { MODRM_SPLITRM, 1918 }, + { MODRM_SPLITRM, 1920 }, + { MODRM_SPLITRM, 2404 }, + { MODRM_SPLITRM, 2406 }, + { MODRM_SPLITRM, 1576 }, + { MODRM_SPLITRM, 2408 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITREG, 2863 }, + { MODRM_ONEENTRY, 2426 }, + { MODRM_ONEENTRY, 2426 }, + { MODRM_ONEENTRY, 2426 }, + { MODRM_ONEENTRY, 2426 }, + { MODRM_ONEENTRY, 2426 }, + { MODRM_ONEENTRY, 2426 }, + { MODRM_ONEENTRY, 2426 }, + { MODRM_ONEENTRY, 2426 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 1597 }, + } }, +}; + +static const unsigned char index_x86DisassemblerThreeByte38Opcodes[] = { + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 0, + 0, + 0, + 0, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 0, + 0, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +static const struct OpcodeDecision x86DisassemblerThreeByte38Opcodes[] = { + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2879 }, + { MODRM_SPLITRM, 2881 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2883 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2885 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { 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MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2997 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, +}; + +static const unsigned char index_x86DisassemblerThreeByte3AOpcodes[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +static const struct OpcodeDecision x86DisassemblerThreeByte3AOpcodes[] = { + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 2999 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, + { { + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { 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MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_SPLITRM, 3001 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + { MODRM_ONEENTRY, 0 }, + } }, +}; + diff --git a/thirdparty/capstone/arch/X86/X86GenInstrInfo.inc b/thirdparty/capstone/arch/X86/X86GenInstrInfo.inc new file mode 100644 index 0000000..16a51b7 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenInstrInfo.inc @@ -0,0 +1,15158 @@ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +|* Target Instruction Enum Values and Descriptors *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + +enum { + X86_AAA = 146, + X86_AAD8i8 = 147, + X86_AAM8i8 = 148, + X86_AAS = 149, + X86_ABS_F = 150, + X86_ABS_Fp32 = 151, + X86_ABS_Fp64 = 152, + X86_ABS_Fp80 = 153, + X86_ADC16i16 = 154, + X86_ADC16mi = 155, + X86_ADC16mi8 = 156, + X86_ADC16mr = 157, + X86_ADC16ri = 158, + X86_ADC16ri8 = 159, + X86_ADC16rm = 160, + X86_ADC16rr = 161, + X86_ADC16rr_REV = 162, + X86_ADC32i32 = 163, + X86_ADC32mi = 164, + X86_ADC32mi8 = 165, + X86_ADC32mr = 166, + X86_ADC32ri = 167, + X86_ADC32ri8 = 168, + X86_ADC32rm = 169, + X86_ADC32rr = 170, + X86_ADC32rr_REV = 171, + X86_ADC64i32 = 172, + X86_ADC64mi32 = 173, + X86_ADC64mi8 = 174, + X86_ADC64mr = 175, + X86_ADC64ri32 = 176, + X86_ADC64ri8 = 177, + X86_ADC64rm = 178, + X86_ADC64rr = 179, + X86_ADC64rr_REV = 180, + X86_ADC8i8 = 181, + X86_ADC8mi = 182, + X86_ADC8mi8 = 183, + X86_ADC8mr = 184, + X86_ADC8ri = 185, + X86_ADC8ri8 = 186, + X86_ADC8rm = 187, + X86_ADC8rr = 188, + X86_ADC8rr_REV = 189, + X86_ADCX32rm = 190, + X86_ADCX32rr = 191, + X86_ADCX64rm = 192, + X86_ADCX64rr = 193, + X86_ADD16i16 = 194, + X86_ADD16mi = 195, + X86_ADD16mi8 = 196, + X86_ADD16mr = 197, + X86_ADD16ri = 198, + X86_ADD16ri8 = 199, + X86_ADD16rm = 200, + X86_ADD16rr = 201, + X86_ADD16rr_REV = 202, + X86_ADD32i32 = 203, + X86_ADD32mi = 204, + X86_ADD32mi8 = 205, + X86_ADD32mr = 206, + X86_ADD32ri = 207, + X86_ADD32ri8 = 208, + X86_ADD32rm = 209, + X86_ADD32rr = 210, + X86_ADD32rr_REV = 211, + X86_ADD64i32 = 212, + X86_ADD64mi32 = 213, + X86_ADD64mi8 = 214, + X86_ADD64mr = 215, + X86_ADD64ri32 = 216, + X86_ADD64ri8 = 217, + X86_ADD64rm = 218, + X86_ADD64rr = 219, + X86_ADD64rr_REV = 220, + X86_ADD8i8 = 221, + X86_ADD8mi = 222, + X86_ADD8mi8 = 223, + X86_ADD8mr = 224, + X86_ADD8ri = 225, + X86_ADD8ri8 = 226, + X86_ADD8rm = 227, + X86_ADD8rr = 228, + X86_ADD8rr_REV = 229, + X86_ADDPDrm = 230, + X86_ADDPDrr = 231, + X86_ADDPSrm = 232, + X86_ADDPSrr = 233, + X86_ADDSDrm = 234, + X86_ADDSDrm_Int = 235, + X86_ADDSDrr = 236, + X86_ADDSDrr_Int = 237, + X86_ADDSSrm = 238, + X86_ADDSSrm_Int = 239, + X86_ADDSSrr = 240, + X86_ADDSSrr_Int = 241, + X86_ADDSUBPDrm = 242, + X86_ADDSUBPDrr = 243, + X86_ADDSUBPSrm = 244, + X86_ADDSUBPSrr = 245, + X86_ADD_F32m = 246, + X86_ADD_F64m = 247, + X86_ADD_FI16m = 248, + X86_ADD_FI32m = 249, + X86_ADD_FPrST0 = 250, + X86_ADD_FST0r = 251, + X86_ADD_Fp32 = 252, + X86_ADD_Fp32m = 253, + X86_ADD_Fp64 = 254, + X86_ADD_Fp64m = 255, + X86_ADD_Fp64m32 = 256, + X86_ADD_Fp80 = 257, + X86_ADD_Fp80m32 = 258, + X86_ADD_Fp80m64 = 259, + X86_ADD_FpI16m32 = 260, + X86_ADD_FpI16m64 = 261, + X86_ADD_FpI16m80 = 262, + X86_ADD_FpI32m32 = 263, + X86_ADD_FpI32m64 = 264, + X86_ADD_FpI32m80 = 265, + X86_ADD_FrST0 = 266, + X86_ADOX32rm = 267, + X86_ADOX32rr = 268, + X86_ADOX64rm = 269, + X86_ADOX64rr = 270, + X86_AESDECLASTrm = 271, + X86_AESDECLASTrr = 272, + X86_AESDECrm = 273, + X86_AESDECrr = 274, + X86_AESENCLASTrm = 275, + X86_AESENCLASTrr = 276, + X86_AESENCrm = 277, + X86_AESENCrr = 278, + X86_AESIMCrm = 279, + X86_AESIMCrr = 280, + X86_AESKEYGENASSIST128rm = 281, + X86_AESKEYGENASSIST128rr = 282, + X86_AND16i16 = 283, + X86_AND16mi = 284, + X86_AND16mi8 = 285, + X86_AND16mr = 286, + X86_AND16ri = 287, + X86_AND16ri8 = 288, + X86_AND16rm = 289, + X86_AND16rr = 290, + X86_AND16rr_REV = 291, + X86_AND32i32 = 292, + X86_AND32mi = 293, + X86_AND32mi8 = 294, + X86_AND32mr = 295, + X86_AND32ri = 296, + X86_AND32ri8 = 297, + X86_AND32rm = 298, + X86_AND32rr = 299, + X86_AND32rr_REV = 300, + X86_AND64i32 = 301, + X86_AND64mi32 = 302, + X86_AND64mi8 = 303, + X86_AND64mr = 304, + X86_AND64ri32 = 305, + X86_AND64ri8 = 306, + X86_AND64rm = 307, + X86_AND64rr = 308, + X86_AND64rr_REV = 309, + X86_AND8i8 = 310, + X86_AND8mi = 311, + X86_AND8mi8 = 312, + X86_AND8mr = 313, + X86_AND8ri = 314, + X86_AND8ri8 = 315, + X86_AND8rm = 316, + X86_AND8rr = 317, + X86_AND8rr_REV = 318, + X86_ANDN32rm = 319, + X86_ANDN32rr = 320, + X86_ANDN64rm = 321, + X86_ANDN64rr = 322, + X86_ANDNPDrm = 323, + X86_ANDNPDrr = 324, + X86_ANDNPSrm = 325, + X86_ANDNPSrr = 326, + X86_ANDPDrm = 327, + X86_ANDPDrr = 328, + X86_ANDPSrm = 329, + X86_ANDPSrr = 330, + X86_ARPL16mr = 331, + X86_ARPL16rr = 332, + X86_BEXTR32rm = 333, + X86_BEXTR32rr = 334, + X86_BEXTR64rm = 335, + X86_BEXTR64rr = 336, + X86_BEXTRI32mi = 337, + X86_BEXTRI32ri = 338, + X86_BEXTRI64mi = 339, + X86_BEXTRI64ri = 340, + X86_BLCFILL32rm = 341, + X86_BLCFILL32rr = 342, + X86_BLCFILL64rm = 343, + X86_BLCFILL64rr = 344, + X86_BLCI32rm = 345, + X86_BLCI32rr = 346, + X86_BLCI64rm = 347, + X86_BLCI64rr = 348, + X86_BLCIC32rm = 349, + X86_BLCIC32rr = 350, + X86_BLCIC64rm = 351, + X86_BLCIC64rr = 352, + X86_BLCMSK32rm = 353, + X86_BLCMSK32rr = 354, + X86_BLCMSK64rm = 355, + X86_BLCMSK64rr = 356, + X86_BLCS32rm = 357, + X86_BLCS32rr = 358, + X86_BLCS64rm = 359, + X86_BLCS64rr = 360, + X86_BLENDPDrmi = 361, + X86_BLENDPDrri = 362, + X86_BLENDPSrmi = 363, + X86_BLENDPSrri = 364, + X86_BLENDVPDrm0 = 365, + X86_BLENDVPDrr0 = 366, + X86_BLENDVPSrm0 = 367, + X86_BLENDVPSrr0 = 368, + X86_BLSFILL32rm = 369, + X86_BLSFILL32rr = 370, + X86_BLSFILL64rm = 371, + X86_BLSFILL64rr = 372, + X86_BLSI32rm = 373, + X86_BLSI32rr = 374, + X86_BLSI64rm = 375, + X86_BLSI64rr = 376, + X86_BLSIC32rm = 377, + X86_BLSIC32rr = 378, + X86_BLSIC64rm = 379, + X86_BLSIC64rr = 380, + X86_BLSMSK32rm = 381, + X86_BLSMSK32rr = 382, + X86_BLSMSK64rm = 383, + X86_BLSMSK64rr = 384, + X86_BLSR32rm = 385, + X86_BLSR32rr = 386, + X86_BLSR64rm = 387, + X86_BLSR64rr = 388, + X86_BNDCL32rm = 389, + X86_BNDCL32rr = 390, + X86_BNDCL64rm = 391, + X86_BNDCL64rr = 392, + X86_BNDCN32rm = 393, + X86_BNDCN32rr = 394, + X86_BNDCN64rm = 395, + X86_BNDCN64rr = 396, + X86_BNDCU32rm = 397, + X86_BNDCU32rr = 398, + X86_BNDCU64rm = 399, + X86_BNDCU64rr = 400, + X86_BNDLDXrm = 401, + X86_BNDMK32rm = 402, + X86_BNDMK64rm = 403, + X86_BNDMOV32mr = 404, + X86_BNDMOV32rm = 405, + X86_BNDMOV64mr = 406, + X86_BNDMOV64rm = 407, + X86_BNDMOVrr = 408, + X86_BNDMOVrr_REV = 409, + X86_BNDSTXmr = 410, + X86_BOUNDS16rm = 411, + X86_BOUNDS32rm = 412, + X86_BSF16rm = 413, + X86_BSF16rr = 414, + X86_BSF32rm = 415, + X86_BSF32rr = 416, + X86_BSF64rm = 417, + X86_BSF64rr = 418, + X86_BSR16rm = 419, + X86_BSR16rr = 420, + X86_BSR32rm = 421, + X86_BSR32rr = 422, + X86_BSR64rm = 423, + X86_BSR64rr = 424, + X86_BSWAP16r_BAD = 425, + X86_BSWAP32r = 426, + X86_BSWAP64r = 427, + X86_BT16mi8 = 428, + X86_BT16mr = 429, + X86_BT16ri8 = 430, + X86_BT16rr = 431, + X86_BT32mi8 = 432, + X86_BT32mr = 433, + X86_BT32ri8 = 434, + X86_BT32rr = 435, + X86_BT64mi8 = 436, + X86_BT64mr = 437, + X86_BT64ri8 = 438, + X86_BT64rr = 439, + X86_BTC16mi8 = 440, + X86_BTC16mr = 441, + X86_BTC16ri8 = 442, + X86_BTC16rr = 443, + X86_BTC32mi8 = 444, + X86_BTC32mr = 445, + X86_BTC32ri8 = 446, + X86_BTC32rr = 447, + X86_BTC64mi8 = 448, + X86_BTC64mr = 449, + X86_BTC64ri8 = 450, + X86_BTC64rr = 451, + X86_BTR16mi8 = 452, + X86_BTR16mr = 453, + X86_BTR16ri8 = 454, + X86_BTR16rr = 455, + X86_BTR32mi8 = 456, + X86_BTR32mr = 457, + X86_BTR32ri8 = 458, + X86_BTR32rr = 459, + X86_BTR64mi8 = 460, + X86_BTR64mr = 461, + X86_BTR64ri8 = 462, + X86_BTR64rr = 463, + X86_BTS16mi8 = 464, + X86_BTS16mr = 465, + X86_BTS16ri8 = 466, + X86_BTS16rr = 467, + X86_BTS32mi8 = 468, + X86_BTS32mr = 469, + X86_BTS32ri8 = 470, + X86_BTS32rr = 471, + X86_BTS64mi8 = 472, + X86_BTS64mr = 473, + X86_BTS64ri8 = 474, + X86_BTS64rr = 475, + X86_BZHI32rm = 476, + X86_BZHI32rr = 477, + X86_BZHI64rm = 478, + X86_BZHI64rr = 479, + X86_CALL16m = 480, + X86_CALL16m_NT = 481, + X86_CALL16r = 482, + X86_CALL16r_NT = 483, + X86_CALL32m = 484, + X86_CALL32m_NT = 485, + X86_CALL32r = 486, + X86_CALL32r_NT = 487, + X86_CALL64m = 488, + X86_CALL64m_NT = 489, + X86_CALL64pcrel32 = 490, + X86_CALL64r = 491, + X86_CALL64r_NT = 492, + X86_CALLpcrel16 = 493, + X86_CALLpcrel32 = 494, + X86_CBW = 495, + X86_CDQ = 496, + X86_CDQE = 497, + X86_CHS_F = 498, + X86_CHS_Fp32 = 499, + X86_CHS_Fp64 = 500, + X86_CHS_Fp80 = 501, + X86_CLAC = 502, + X86_CLC = 503, + X86_CLD = 504, + X86_CLDEMOTE = 505, + X86_CLFLUSH = 506, + X86_CLFLUSHOPT = 507, + X86_CLGI = 508, + X86_CLI = 509, + X86_CLRSSBSY = 510, + X86_CLTS = 511, + X86_CLWB = 512, + X86_CLZEROr = 513, + X86_CMC = 514, + X86_CMOVA16rm = 515, + X86_CMOVA16rr = 516, + X86_CMOVA32rm = 517, + X86_CMOVA32rr = 518, + X86_CMOVA64rm = 519, + X86_CMOVA64rr = 520, + X86_CMOVAE16rm = 521, + X86_CMOVAE16rr = 522, + X86_CMOVAE32rm = 523, + X86_CMOVAE32rr = 524, + X86_CMOVAE64rm = 525, + X86_CMOVAE64rr = 526, + X86_CMOVB16rm = 527, + X86_CMOVB16rr = 528, + X86_CMOVB32rm = 529, + X86_CMOVB32rr = 530, + X86_CMOVB64rm = 531, + X86_CMOVB64rr = 532, + X86_CMOVBE16rm = 533, + X86_CMOVBE16rr = 534, + X86_CMOVBE32rm = 535, + X86_CMOVBE32rr = 536, + X86_CMOVBE64rm = 537, + X86_CMOVBE64rr = 538, + X86_CMOVBE_F = 539, + X86_CMOVBE_Fp32 = 540, + X86_CMOVBE_Fp64 = 541, + X86_CMOVBE_Fp80 = 542, + X86_CMOVB_F = 543, + X86_CMOVB_Fp32 = 544, + X86_CMOVB_Fp64 = 545, + X86_CMOVB_Fp80 = 546, + X86_CMOVE16rm = 547, + X86_CMOVE16rr = 548, + X86_CMOVE32rm = 549, + X86_CMOVE32rr = 550, + X86_CMOVE64rm = 551, + X86_CMOVE64rr = 552, + X86_CMOVE_F = 553, + X86_CMOVE_Fp32 = 554, + X86_CMOVE_Fp64 = 555, + X86_CMOVE_Fp80 = 556, + X86_CMOVG16rm = 557, + X86_CMOVG16rr = 558, + X86_CMOVG32rm = 559, + X86_CMOVG32rr = 560, + X86_CMOVG64rm = 561, + X86_CMOVG64rr = 562, + X86_CMOVGE16rm = 563, + X86_CMOVGE16rr = 564, + X86_CMOVGE32rm = 565, + X86_CMOVGE32rr = 566, + X86_CMOVGE64rm = 567, + X86_CMOVGE64rr = 568, + X86_CMOVL16rm = 569, + X86_CMOVL16rr = 570, + X86_CMOVL32rm = 571, + X86_CMOVL32rr = 572, + X86_CMOVL64rm = 573, + X86_CMOVL64rr = 574, + X86_CMOVLE16rm = 575, + X86_CMOVLE16rr = 576, + X86_CMOVLE32rm = 577, + X86_CMOVLE32rr = 578, + X86_CMOVLE64rm = 579, + X86_CMOVLE64rr = 580, + X86_CMOVNBE_F = 581, + X86_CMOVNBE_Fp32 = 582, + X86_CMOVNBE_Fp64 = 583, + X86_CMOVNBE_Fp80 = 584, + X86_CMOVNB_F = 585, + X86_CMOVNB_Fp32 = 586, + X86_CMOVNB_Fp64 = 587, + X86_CMOVNB_Fp80 = 588, + X86_CMOVNE16rm = 589, + X86_CMOVNE16rr = 590, + X86_CMOVNE32rm = 591, + X86_CMOVNE32rr = 592, + X86_CMOVNE64rm = 593, + X86_CMOVNE64rr = 594, + X86_CMOVNE_F = 595, + X86_CMOVNE_Fp32 = 596, + X86_CMOVNE_Fp64 = 597, + X86_CMOVNE_Fp80 = 598, + X86_CMOVNO16rm = 599, + X86_CMOVNO16rr = 600, + X86_CMOVNO32rm = 601, + X86_CMOVNO32rr = 602, + X86_CMOVNO64rm = 603, + X86_CMOVNO64rr = 604, + X86_CMOVNP16rm = 605, + X86_CMOVNP16rr = 606, + X86_CMOVNP32rm = 607, + X86_CMOVNP32rr = 608, + X86_CMOVNP64rm = 609, + X86_CMOVNP64rr = 610, + X86_CMOVNP_F = 611, + X86_CMOVNP_Fp32 = 612, + X86_CMOVNP_Fp64 = 613, + X86_CMOVNP_Fp80 = 614, + X86_CMOVNS16rm = 615, + X86_CMOVNS16rr = 616, + X86_CMOVNS32rm = 617, + X86_CMOVNS32rr = 618, + X86_CMOVNS64rm = 619, + X86_CMOVNS64rr = 620, + X86_CMOVO16rm = 621, + X86_CMOVO16rr = 622, + X86_CMOVO32rm = 623, + X86_CMOVO32rr = 624, + X86_CMOVO64rm = 625, + X86_CMOVO64rr = 626, + X86_CMOVP16rm = 627, + X86_CMOVP16rr = 628, + X86_CMOVP32rm = 629, + X86_CMOVP32rr = 630, + X86_CMOVP64rm = 631, + X86_CMOVP64rr = 632, + X86_CMOVP_F = 633, + X86_CMOVP_Fp32 = 634, + X86_CMOVP_Fp64 = 635, + X86_CMOVP_Fp80 = 636, + X86_CMOVS16rm = 637, + X86_CMOVS16rr = 638, + X86_CMOVS32rm = 639, + X86_CMOVS32rr = 640, + X86_CMOVS64rm = 641, + X86_CMOVS64rr = 642, + X86_CMP16i16 = 643, + X86_CMP16mi = 644, + X86_CMP16mi8 = 645, + X86_CMP16mr = 646, + X86_CMP16ri = 647, + X86_CMP16ri8 = 648, + X86_CMP16rm = 649, + X86_CMP16rr = 650, + X86_CMP16rr_REV = 651, + X86_CMP32i32 = 652, + X86_CMP32mi = 653, + X86_CMP32mi8 = 654, + X86_CMP32mr = 655, + X86_CMP32ri = 656, + X86_CMP32ri8 = 657, + X86_CMP32rm = 658, + X86_CMP32rr = 659, + X86_CMP32rr_REV = 660, + X86_CMP64i32 = 661, + X86_CMP64mi32 = 662, + X86_CMP64mi8 = 663, + X86_CMP64mr = 664, + X86_CMP64ri32 = 665, + X86_CMP64ri8 = 666, + X86_CMP64rm = 667, + X86_CMP64rr = 668, + X86_CMP64rr_REV = 669, + X86_CMP8i8 = 670, + X86_CMP8mi = 671, + X86_CMP8mi8 = 672, + X86_CMP8mr = 673, + X86_CMP8ri = 674, + X86_CMP8ri8 = 675, + X86_CMP8rm = 676, + X86_CMP8rr = 677, + X86_CMP8rr_REV = 678, + X86_CMPPDrmi = 679, + X86_CMPPDrmi_alt = 680, + X86_CMPPDrri = 681, + X86_CMPPDrri_alt = 682, + X86_CMPPSrmi = 683, + X86_CMPPSrmi_alt = 684, + X86_CMPPSrri = 685, + X86_CMPPSrri_alt = 686, + X86_CMPSB = 687, + X86_CMPSDrm = 688, + X86_CMPSDrm_Int = 689, + X86_CMPSDrm_alt = 690, + X86_CMPSDrr = 691, + X86_CMPSDrr_Int = 692, + X86_CMPSDrr_alt = 693, + X86_CMPSL = 694, + X86_CMPSQ = 695, + X86_CMPSSrm = 696, + X86_CMPSSrm_Int = 697, + X86_CMPSSrm_alt = 698, + X86_CMPSSrr = 699, + X86_CMPSSrr_Int = 700, + X86_CMPSSrr_alt = 701, + X86_CMPSW = 702, + X86_CMPXCHG16B = 703, + X86_CMPXCHG16rm = 704, + X86_CMPXCHG16rr = 705, + X86_CMPXCHG32rm = 706, + X86_CMPXCHG32rr = 707, + X86_CMPXCHG64rm = 708, + X86_CMPXCHG64rr = 709, + X86_CMPXCHG8B = 710, + X86_CMPXCHG8rm = 711, + X86_CMPXCHG8rr = 712, + X86_COMISDrm = 713, + X86_COMISDrm_Int = 714, + X86_COMISDrr = 715, + X86_COMISDrr_Int = 716, + X86_COMISSrm = 717, + X86_COMISSrm_Int = 718, + X86_COMISSrr = 719, + X86_COMISSrr_Int = 720, + X86_COMP_FST0r = 721, + X86_COM_FIPr = 722, + X86_COM_FIr = 723, + X86_COM_FST0r = 724, + X86_COS_F = 725, + X86_COS_Fp32 = 726, + X86_COS_Fp64 = 727, + X86_COS_Fp80 = 728, + X86_CPUID = 729, + X86_CQO = 730, + X86_CRC32r32m16 = 731, + X86_CRC32r32m32 = 732, + X86_CRC32r32m8 = 733, + X86_CRC32r32r16 = 734, + X86_CRC32r32r32 = 735, + X86_CRC32r32r8 = 736, + X86_CRC32r64m64 = 737, + X86_CRC32r64m8 = 738, + X86_CRC32r64r64 = 739, + X86_CRC32r64r8 = 740, + X86_CVTDQ2PDrm = 741, + X86_CVTDQ2PDrr = 742, + X86_CVTDQ2PSrm = 743, + X86_CVTDQ2PSrr = 744, + X86_CVTPD2DQrm = 745, + X86_CVTPD2DQrr = 746, + X86_CVTPD2PSrm = 747, + X86_CVTPD2PSrr = 748, + X86_CVTPS2DQrm = 749, + X86_CVTPS2DQrr = 750, + X86_CVTPS2PDrm = 751, + X86_CVTPS2PDrr = 752, + X86_CVTSD2SI64rm_Int = 753, + X86_CVTSD2SI64rr_Int = 754, + X86_CVTSD2SIrm_Int = 755, + X86_CVTSD2SIrr_Int = 756, + X86_CVTSD2SSrm = 757, + X86_CVTSD2SSrm_Int = 758, + X86_CVTSD2SSrr = 759, + X86_CVTSD2SSrr_Int = 760, + X86_CVTSI2SDrm = 761, + X86_CVTSI2SDrm_Int = 762, + X86_CVTSI2SDrr = 763, + X86_CVTSI2SDrr_Int = 764, + X86_CVTSI2SSrm = 765, + X86_CVTSI2SSrm_Int = 766, + X86_CVTSI2SSrr = 767, + X86_CVTSI2SSrr_Int = 768, + X86_CVTSI642SDrm = 769, + X86_CVTSI642SDrm_Int = 770, + X86_CVTSI642SDrr = 771, + X86_CVTSI642SDrr_Int = 772, + X86_CVTSI642SSrm = 773, + X86_CVTSI642SSrm_Int = 774, + X86_CVTSI642SSrr = 775, + X86_CVTSI642SSrr_Int = 776, + X86_CVTSS2SDrm = 777, + X86_CVTSS2SDrm_Int = 778, + X86_CVTSS2SDrr = 779, + X86_CVTSS2SDrr_Int = 780, + X86_CVTSS2SI64rm_Int = 781, + X86_CVTSS2SI64rr_Int = 782, + X86_CVTSS2SIrm_Int = 783, + X86_CVTSS2SIrr_Int = 784, + X86_CVTTPD2DQrm = 785, + X86_CVTTPD2DQrr = 786, + X86_CVTTPS2DQrm = 787, + X86_CVTTPS2DQrr = 788, + X86_CVTTSD2SI64rm = 789, + X86_CVTTSD2SI64rm_Int = 790, + X86_CVTTSD2SI64rr = 791, + X86_CVTTSD2SI64rr_Int = 792, + X86_CVTTSD2SIrm = 793, + X86_CVTTSD2SIrm_Int = 794, + X86_CVTTSD2SIrr = 795, + X86_CVTTSD2SIrr_Int = 796, + X86_CVTTSS2SI64rm = 797, + X86_CVTTSS2SI64rm_Int = 798, + X86_CVTTSS2SI64rr = 799, + X86_CVTTSS2SI64rr_Int = 800, + X86_CVTTSS2SIrm = 801, + X86_CVTTSS2SIrm_Int = 802, + X86_CVTTSS2SIrr = 803, + X86_CVTTSS2SIrr_Int = 804, + X86_CWD = 805, + X86_CWDE = 806, + X86_DAA = 807, + X86_DAS = 808, + X86_DATA16_PREFIX = 809, + X86_DEC16m = 810, + X86_DEC16r = 811, + X86_DEC16r_alt = 812, + X86_DEC32m = 813, + X86_DEC32r = 814, + X86_DEC32r_alt = 815, + X86_DEC64m = 816, + X86_DEC64r = 817, + X86_DEC8m = 818, + X86_DEC8r = 819, + X86_DIV16m = 820, + X86_DIV16r = 821, + X86_DIV32m = 822, + X86_DIV32r = 823, + X86_DIV64m = 824, + X86_DIV64r = 825, + X86_DIV8m = 826, + X86_DIV8r = 827, + X86_DIVPDrm = 828, + X86_DIVPDrr = 829, + X86_DIVPSrm = 830, + X86_DIVPSrr = 831, + X86_DIVR_F32m = 832, + X86_DIVR_F64m = 833, + X86_DIVR_FI16m = 834, + X86_DIVR_FI32m = 835, + X86_DIVR_FPrST0 = 836, + X86_DIVR_FST0r = 837, + X86_DIVR_Fp32m = 838, + X86_DIVR_Fp64m = 839, + X86_DIVR_Fp64m32 = 840, + X86_DIVR_Fp80m32 = 841, + X86_DIVR_Fp80m64 = 842, + X86_DIVR_FpI16m32 = 843, + X86_DIVR_FpI16m64 = 844, + X86_DIVR_FpI16m80 = 845, + X86_DIVR_FpI32m32 = 846, + X86_DIVR_FpI32m64 = 847, + X86_DIVR_FpI32m80 = 848, + X86_DIVR_FrST0 = 849, + X86_DIVSDrm = 850, + X86_DIVSDrm_Int = 851, + X86_DIVSDrr = 852, + X86_DIVSDrr_Int = 853, + X86_DIVSSrm = 854, + X86_DIVSSrm_Int = 855, + X86_DIVSSrr = 856, + X86_DIVSSrr_Int = 857, + X86_DIV_F32m = 858, + X86_DIV_F64m = 859, + X86_DIV_FI16m = 860, + X86_DIV_FI32m = 861, + X86_DIV_FPrST0 = 862, + X86_DIV_FST0r = 863, + X86_DIV_Fp32 = 864, + X86_DIV_Fp32m = 865, + X86_DIV_Fp64 = 866, + X86_DIV_Fp64m = 867, + X86_DIV_Fp64m32 = 868, + X86_DIV_Fp80 = 869, + X86_DIV_Fp80m32 = 870, + X86_DIV_Fp80m64 = 871, + X86_DIV_FpI16m32 = 872, + X86_DIV_FpI16m64 = 873, + X86_DIV_FpI16m80 = 874, + X86_DIV_FpI32m32 = 875, + X86_DIV_FpI32m64 = 876, + X86_DIV_FpI32m80 = 877, + X86_DIV_FrST0 = 878, + X86_DPPDrmi = 879, + X86_DPPDrri = 880, + X86_DPPSrmi = 881, + X86_DPPSrri = 882, + X86_ENCLS = 883, + X86_ENCLU = 884, + X86_ENCLV = 885, + X86_ENDBR32 = 886, + X86_ENDBR64 = 887, + X86_ENTER = 888, + X86_EXTRACTPSmr = 889, + X86_EXTRACTPSrr = 890, + X86_EXTRQ = 891, + X86_EXTRQI = 892, + X86_F2XM1 = 893, + X86_FARCALL16i = 894, + X86_FARCALL16m = 895, + X86_FARCALL32i = 896, + X86_FARCALL32m = 897, + X86_FARCALL64 = 898, + X86_FARJMP16i = 899, + X86_FARJMP16m = 900, + X86_FARJMP32i = 901, + X86_FARJMP32m = 902, + X86_FARJMP64 = 903, + X86_FBLDm = 904, + X86_FBSTPm = 905, + X86_FCOM32m = 906, + X86_FCOM64m = 907, + X86_FCOMP32m = 908, + X86_FCOMP64m = 909, + X86_FCOMPP = 910, + X86_FDECSTP = 911, + X86_FDISI8087_NOP = 912, + X86_FEMMS = 913, + X86_FENI8087_NOP = 914, + X86_FFREE = 915, + X86_FFREEP = 916, + X86_FICOM16m = 917, + X86_FICOM32m = 918, + X86_FICOMP16m = 919, + X86_FICOMP32m = 920, + X86_FINCSTP = 921, + X86_FLDCW16m = 922, + X86_FLDENVm = 923, + X86_FLDL2E = 924, + X86_FLDL2T = 925, + X86_FLDLG2 = 926, + X86_FLDLN2 = 927, + X86_FLDPI = 928, + X86_FNCLEX = 929, + X86_FNINIT = 930, + X86_FNOP = 931, + X86_FNSTCW16m = 932, + X86_FNSTSW16r = 933, + X86_FNSTSWm = 934, + X86_FPATAN = 935, + X86_FPNCEST0r = 936, + X86_FPREM = 937, + X86_FPREM1 = 938, + X86_FPTAN = 939, + X86_FRNDINT = 940, + X86_FRSTORm = 941, + X86_FSAVEm = 942, + X86_FSCALE = 943, + X86_FSETPM = 944, + X86_FSINCOS = 945, + X86_FSTENVm = 946, + X86_FXAM = 947, + X86_FXRSTOR = 948, + X86_FXRSTOR64 = 949, + X86_FXSAVE = 950, + X86_FXSAVE64 = 951, + X86_FXTRACT = 952, + X86_FYL2X = 953, + X86_FYL2XP1 = 954, + X86_GETSEC = 955, + X86_GF2P8AFFINEINVQBrmi = 956, + X86_GF2P8AFFINEINVQBrri = 957, + X86_GF2P8AFFINEQBrmi = 958, + X86_GF2P8AFFINEQBrri = 959, + X86_GF2P8MULBrm = 960, + X86_GF2P8MULBrr = 961, + X86_HADDPDrm = 962, + X86_HADDPDrr = 963, + X86_HADDPSrm = 964, + X86_HADDPSrr = 965, + X86_HLT = 966, + X86_HSUBPDrm = 967, + X86_HSUBPDrr = 968, + X86_HSUBPSrm = 969, + X86_HSUBPSrr = 970, + X86_IDIV16m = 971, + X86_IDIV16r = 972, + X86_IDIV32m = 973, + X86_IDIV32r = 974, + X86_IDIV64m = 975, + X86_IDIV64r = 976, + X86_IDIV8m = 977, + X86_IDIV8r = 978, + X86_ILD_F16m = 979, + X86_ILD_F32m = 980, + X86_ILD_F64m = 981, + X86_ILD_Fp16m32 = 982, + X86_ILD_Fp16m64 = 983, + X86_ILD_Fp16m80 = 984, + X86_ILD_Fp32m32 = 985, + X86_ILD_Fp32m64 = 986, + X86_ILD_Fp32m80 = 987, + X86_ILD_Fp64m32 = 988, + X86_ILD_Fp64m64 = 989, + X86_ILD_Fp64m80 = 990, + X86_IMUL16m = 991, + X86_IMUL16r = 992, + X86_IMUL16rm = 993, + X86_IMUL16rmi = 994, + X86_IMUL16rmi8 = 995, + X86_IMUL16rr = 996, + X86_IMUL16rri = 997, + X86_IMUL16rri8 = 998, + X86_IMUL32m = 999, + X86_IMUL32r = 1000, + X86_IMUL32rm = 1001, + X86_IMUL32rmi = 1002, + X86_IMUL32rmi8 = 1003, + X86_IMUL32rr = 1004, + X86_IMUL32rri = 1005, + X86_IMUL32rri8 = 1006, + X86_IMUL64m = 1007, + X86_IMUL64r = 1008, + X86_IMUL64rm = 1009, + X86_IMUL64rmi32 = 1010, + X86_IMUL64rmi8 = 1011, + X86_IMUL64rr = 1012, + X86_IMUL64rri32 = 1013, + X86_IMUL64rri8 = 1014, + X86_IMUL8m = 1015, + X86_IMUL8r = 1016, + X86_IN16ri = 1017, + X86_IN16rr = 1018, + X86_IN32ri = 1019, + X86_IN32rr = 1020, + X86_IN8ri = 1021, + X86_IN8rr = 1022, + X86_INC16m = 1023, + X86_INC16r = 1024, + X86_INC16r_alt = 1025, + X86_INC32m = 1026, + X86_INC32r = 1027, + X86_INC32r_alt = 1028, + X86_INC64m = 1029, + X86_INC64r = 1030, + X86_INC8m = 1031, + X86_INC8r = 1032, + X86_INCSSPD = 1033, + X86_INCSSPQ = 1034, + X86_INSB = 1035, + X86_INSERTPSrm = 1036, + X86_INSERTPSrr = 1037, + X86_INSERTQ = 1038, + X86_INSERTQI = 1039, + X86_INSL = 1040, + X86_INSW = 1041, + X86_INT = 1042, + X86_INT1 = 1043, + X86_INT3 = 1044, + X86_INTO = 1045, + X86_INVD = 1046, + X86_INVEPT32 = 1047, + X86_INVEPT64 = 1048, + X86_INVLPG = 1049, + X86_INVLPGA32 = 1050, + X86_INVLPGA64 = 1051, + X86_INVPCID32 = 1052, + X86_INVPCID64 = 1053, + X86_INVVPID32 = 1054, + X86_INVVPID64 = 1055, + X86_IRET16 = 1056, + X86_IRET32 = 1057, + X86_IRET64 = 1058, + X86_ISTT_FP16m = 1059, + X86_ISTT_FP32m = 1060, + X86_ISTT_FP64m = 1061, + X86_ISTT_Fp16m32 = 1062, + X86_ISTT_Fp16m64 = 1063, + X86_ISTT_Fp16m80 = 1064, + X86_ISTT_Fp32m32 = 1065, + X86_ISTT_Fp32m64 = 1066, + X86_ISTT_Fp32m80 = 1067, + X86_ISTT_Fp64m32 = 1068, + X86_ISTT_Fp64m64 = 1069, + X86_ISTT_Fp64m80 = 1070, + X86_IST_F16m = 1071, + X86_IST_F32m = 1072, + X86_IST_FP16m = 1073, + X86_IST_FP32m = 1074, + X86_IST_FP64m = 1075, + X86_IST_Fp16m32 = 1076, + X86_IST_Fp16m64 = 1077, + X86_IST_Fp16m80 = 1078, + X86_IST_Fp32m32 = 1079, + X86_IST_Fp32m64 = 1080, + X86_IST_Fp32m80 = 1081, + X86_IST_Fp64m32 = 1082, + X86_IST_Fp64m64 = 1083, + X86_IST_Fp64m80 = 1084, + X86_JAE_1 = 1085, + X86_JAE_2 = 1086, + X86_JAE_4 = 1087, + X86_JA_1 = 1088, + X86_JA_2 = 1089, + X86_JA_4 = 1090, + X86_JBE_1 = 1091, + X86_JBE_2 = 1092, + X86_JBE_4 = 1093, + X86_JB_1 = 1094, + X86_JB_2 = 1095, + X86_JB_4 = 1096, + X86_JCXZ = 1097, + X86_JECXZ = 1098, + X86_JE_1 = 1099, + X86_JE_2 = 1100, + X86_JE_4 = 1101, + X86_JGE_1 = 1102, + X86_JGE_2 = 1103, + X86_JGE_4 = 1104, + X86_JG_1 = 1105, + X86_JG_2 = 1106, + X86_JG_4 = 1107, + X86_JLE_1 = 1108, + X86_JLE_2 = 1109, + X86_JLE_4 = 1110, + X86_JL_1 = 1111, + X86_JL_2 = 1112, + X86_JL_4 = 1113, + X86_JMP16m = 1114, + X86_JMP16m_NT = 1115, + X86_JMP16r = 1116, + X86_JMP16r_NT = 1117, + X86_JMP32m = 1118, + X86_JMP32m_NT = 1119, + X86_JMP32r = 1120, + X86_JMP32r_NT = 1121, + X86_JMP64m = 1122, + X86_JMP64m_NT = 1123, + X86_JMP64r = 1124, + X86_JMP64r_NT = 1125, + X86_JMP_1 = 1126, + X86_JMP_2 = 1127, + X86_JMP_4 = 1128, + X86_JNE_1 = 1129, + X86_JNE_2 = 1130, + X86_JNE_4 = 1131, + X86_JNO_1 = 1132, + X86_JNO_2 = 1133, + X86_JNO_4 = 1134, + X86_JNP_1 = 1135, + X86_JNP_2 = 1136, + X86_JNP_4 = 1137, + X86_JNS_1 = 1138, + X86_JNS_2 = 1139, + X86_JNS_4 = 1140, + X86_JO_1 = 1141, + X86_JO_2 = 1142, + X86_JO_4 = 1143, + X86_JP_1 = 1144, + X86_JP_2 = 1145, + X86_JP_4 = 1146, + X86_JRCXZ = 1147, + X86_JS_1 = 1148, + X86_JS_2 = 1149, + X86_JS_4 = 1150, + X86_KADDBrr = 1151, + X86_KADDDrr = 1152, + X86_KADDQrr = 1153, + X86_KADDWrr = 1154, + X86_KANDBrr = 1155, + X86_KANDDrr = 1156, + X86_KANDNBrr = 1157, + X86_KANDNDrr = 1158, + X86_KANDNQrr = 1159, + X86_KANDNWrr = 1160, + X86_KANDQrr = 1161, + X86_KANDWrr = 1162, + X86_KMOVBkk = 1163, + X86_KMOVBkm = 1164, + X86_KMOVBkr = 1165, + X86_KMOVBmk = 1166, + X86_KMOVBrk = 1167, + X86_KMOVDkk = 1168, + X86_KMOVDkm = 1169, + X86_KMOVDkr = 1170, + X86_KMOVDmk = 1171, + X86_KMOVDrk = 1172, + X86_KMOVQkk = 1173, + X86_KMOVQkm = 1174, + X86_KMOVQkr = 1175, + X86_KMOVQmk = 1176, + X86_KMOVQrk = 1177, + X86_KMOVWkk = 1178, + X86_KMOVWkm = 1179, + X86_KMOVWkr = 1180, + X86_KMOVWmk = 1181, + X86_KMOVWrk = 1182, + X86_KNOTBrr = 1183, + X86_KNOTDrr = 1184, + X86_KNOTQrr = 1185, + X86_KNOTWrr = 1186, + X86_KORBrr = 1187, + X86_KORDrr = 1188, + X86_KORQrr = 1189, + X86_KORTESTBrr = 1190, + X86_KORTESTDrr = 1191, + X86_KORTESTQrr = 1192, + X86_KORTESTWrr = 1193, + X86_KORWrr = 1194, + X86_KSHIFTLBri = 1195, + X86_KSHIFTLDri = 1196, + X86_KSHIFTLQri = 1197, + X86_KSHIFTLWri = 1198, + X86_KSHIFTRBri = 1199, + X86_KSHIFTRDri = 1200, + X86_KSHIFTRQri = 1201, + X86_KSHIFTRWri = 1202, + X86_KTESTBrr = 1203, + X86_KTESTDrr = 1204, + X86_KTESTQrr = 1205, + X86_KTESTWrr = 1206, + X86_KUNPCKBWrr = 1207, + X86_KUNPCKDQrr = 1208, + X86_KUNPCKWDrr = 1209, + X86_KXNORBrr = 1210, + X86_KXNORDrr = 1211, + X86_KXNORQrr = 1212, + X86_KXNORWrr = 1213, + X86_KXORBrr = 1214, + X86_KXORDrr = 1215, + X86_KXORQrr = 1216, + X86_KXORWrr = 1217, + X86_LAHF = 1218, + X86_LAR16rm = 1219, + X86_LAR16rr = 1220, + X86_LAR32rm = 1221, + X86_LAR32rr = 1222, + X86_LAR64rm = 1223, + X86_LAR64rr = 1224, + X86_LDDQUrm = 1225, + X86_LDMXCSR = 1226, + X86_LDS16rm = 1227, + X86_LDS32rm = 1228, + X86_LD_F0 = 1229, + X86_LD_F1 = 1230, + X86_LD_F32m = 1231, + X86_LD_F64m = 1232, + X86_LD_F80m = 1233, + X86_LD_Fp032 = 1234, + X86_LD_Fp064 = 1235, + X86_LD_Fp080 = 1236, + X86_LD_Fp132 = 1237, + X86_LD_Fp164 = 1238, + X86_LD_Fp180 = 1239, + X86_LD_Fp32m = 1240, + X86_LD_Fp32m64 = 1241, + X86_LD_Fp32m80 = 1242, + X86_LD_Fp64m = 1243, + X86_LD_Fp64m80 = 1244, + X86_LD_Fp80m = 1245, + X86_LD_Frr = 1246, + X86_LEA16r = 1247, + X86_LEA32r = 1248, + X86_LEA64_32r = 1249, + X86_LEA64r = 1250, + X86_LEAVE = 1251, + X86_LEAVE64 = 1252, + X86_LES16rm = 1253, + X86_LES32rm = 1254, + X86_LFENCE = 1255, + X86_LFS16rm = 1256, + X86_LFS32rm = 1257, + X86_LFS64rm = 1258, + X86_LGDT16m = 1259, + X86_LGDT32m = 1260, + X86_LGDT64m = 1261, + X86_LGS16rm = 1262, + X86_LGS32rm = 1263, + X86_LGS64rm = 1264, + X86_LIDT16m = 1265, + X86_LIDT32m = 1266, + X86_LIDT64m = 1267, + X86_LLDT16m = 1268, + X86_LLDT16r = 1269, + X86_LLWPCB = 1270, + X86_LLWPCB64 = 1271, + X86_LMSW16m = 1272, + X86_LMSW16r = 1273, + X86_LOCK_PREFIX = 1274, + X86_LODSB = 1275, + X86_LODSL = 1276, + X86_LODSQ = 1277, + X86_LODSW = 1278, + X86_LOOP = 1279, + X86_LOOPE = 1280, + X86_LOOPNE = 1281, + X86_LRETIL = 1282, + X86_LRETIQ = 1283, + X86_LRETIW = 1284, + X86_LRETL = 1285, + X86_LRETQ = 1286, + X86_LRETW = 1287, + X86_LSL16rm = 1288, + X86_LSL16rr = 1289, + X86_LSL32rm = 1290, + X86_LSL32rr = 1291, + X86_LSL64rm = 1292, + X86_LSL64rr = 1293, + X86_LSS16rm = 1294, + X86_LSS32rm = 1295, + X86_LSS64rm = 1296, + X86_LTRm = 1297, + X86_LTRr = 1298, + X86_LWPINS32rmi = 1299, + X86_LWPINS32rri = 1300, + X86_LWPINS64rmi = 1301, + X86_LWPINS64rri = 1302, + X86_LWPVAL32rmi = 1303, + X86_LWPVAL32rri = 1304, + X86_LWPVAL64rmi = 1305, + X86_LWPVAL64rri = 1306, + X86_LZCNT16rm = 1307, + X86_LZCNT16rr = 1308, + X86_LZCNT32rm = 1309, + X86_LZCNT32rr = 1310, + X86_LZCNT64rm = 1311, + X86_LZCNT64rr = 1312, + X86_MASKMOVDQU = 1313, + X86_MASKMOVDQU64 = 1314, + X86_MAXCPDrm = 1315, + X86_MAXCPDrr = 1316, + X86_MAXCPSrm = 1317, + X86_MAXCPSrr = 1318, + X86_MAXCSDrm = 1319, + X86_MAXCSDrr = 1320, + X86_MAXCSSrm = 1321, + X86_MAXCSSrr = 1322, + X86_MAXPDrm = 1323, + X86_MAXPDrr = 1324, + X86_MAXPSrm = 1325, + X86_MAXPSrr = 1326, + X86_MAXSDrm = 1327, + X86_MAXSDrm_Int = 1328, + X86_MAXSDrr = 1329, + X86_MAXSDrr_Int = 1330, + X86_MAXSSrm = 1331, + X86_MAXSSrm_Int = 1332, + X86_MAXSSrr = 1333, + X86_MAXSSrr_Int = 1334, + X86_MFENCE = 1335, + X86_MINCPDrm = 1336, + X86_MINCPDrr = 1337, + X86_MINCPSrm = 1338, + X86_MINCPSrr = 1339, + X86_MINCSDrm = 1340, + X86_MINCSDrr = 1341, + X86_MINCSSrm = 1342, + X86_MINCSSrr = 1343, + X86_MINPDrm = 1344, + X86_MINPDrr = 1345, + X86_MINPSrm = 1346, + X86_MINPSrr = 1347, + X86_MINSDrm = 1348, + X86_MINSDrm_Int = 1349, + X86_MINSDrr = 1350, + X86_MINSDrr_Int = 1351, + X86_MINSSrm = 1352, + X86_MINSSrm_Int = 1353, + X86_MINSSrr = 1354, + X86_MINSSrr_Int = 1355, + X86_MMX_CVTPD2PIirm = 1356, + X86_MMX_CVTPD2PIirr = 1357, + X86_MMX_CVTPI2PDirm = 1358, + X86_MMX_CVTPI2PDirr = 1359, + X86_MMX_CVTPI2PSirm = 1360, + X86_MMX_CVTPI2PSirr = 1361, + X86_MMX_CVTPS2PIirm = 1362, + X86_MMX_CVTPS2PIirr = 1363, + X86_MMX_CVTTPD2PIirm = 1364, + X86_MMX_CVTTPD2PIirr = 1365, + X86_MMX_CVTTPS2PIirm = 1366, + X86_MMX_CVTTPS2PIirr = 1367, + X86_MMX_EMMS = 1368, + X86_MMX_MASKMOVQ = 1369, + X86_MMX_MASKMOVQ64 = 1370, + X86_MMX_MOVD64from64rm = 1371, + X86_MMX_MOVD64from64rr = 1372, + X86_MMX_MOVD64grr = 1373, + X86_MMX_MOVD64mr = 1374, + X86_MMX_MOVD64rm = 1375, + X86_MMX_MOVD64rr = 1376, + X86_MMX_MOVD64to64rm = 1377, + X86_MMX_MOVD64to64rr = 1378, + X86_MMX_MOVDQ2Qrr = 1379, + X86_MMX_MOVFR642Qrr = 1380, + X86_MMX_MOVNTQmr = 1381, + X86_MMX_MOVQ2DQrr = 1382, + X86_MMX_MOVQ2FR64rr = 1383, + X86_MMX_MOVQ64mr = 1384, + X86_MMX_MOVQ64rm = 1385, + X86_MMX_MOVQ64rr = 1386, + X86_MMX_MOVQ64rr_REV = 1387, + X86_MMX_PABSBrm = 1388, + X86_MMX_PABSBrr = 1389, + X86_MMX_PABSDrm = 1390, + X86_MMX_PABSDrr = 1391, + X86_MMX_PABSWrm = 1392, + X86_MMX_PABSWrr = 1393, + X86_MMX_PACKSSDWirm = 1394, + X86_MMX_PACKSSDWirr = 1395, + X86_MMX_PACKSSWBirm = 1396, + X86_MMX_PACKSSWBirr = 1397, + X86_MMX_PACKUSWBirm = 1398, + X86_MMX_PACKUSWBirr = 1399, + X86_MMX_PADDBirm = 1400, + X86_MMX_PADDBirr = 1401, + X86_MMX_PADDDirm = 1402, + X86_MMX_PADDDirr = 1403, + X86_MMX_PADDQirm = 1404, + X86_MMX_PADDQirr = 1405, + X86_MMX_PADDSBirm = 1406, + X86_MMX_PADDSBirr = 1407, + X86_MMX_PADDSWirm = 1408, + X86_MMX_PADDSWirr = 1409, + X86_MMX_PADDUSBirm = 1410, + X86_MMX_PADDUSBirr = 1411, + X86_MMX_PADDUSWirm = 1412, + X86_MMX_PADDUSWirr = 1413, + X86_MMX_PADDWirm = 1414, + X86_MMX_PADDWirr = 1415, + X86_MMX_PALIGNRrmi = 1416, + X86_MMX_PALIGNRrri = 1417, + X86_MMX_PANDNirm = 1418, + X86_MMX_PANDNirr = 1419, + X86_MMX_PANDirm = 1420, + X86_MMX_PANDirr = 1421, + X86_MMX_PAVGBirm = 1422, + X86_MMX_PAVGBirr = 1423, + X86_MMX_PAVGWirm = 1424, + X86_MMX_PAVGWirr = 1425, + X86_MMX_PCMPEQBirm = 1426, + X86_MMX_PCMPEQBirr = 1427, + X86_MMX_PCMPEQDirm = 1428, + X86_MMX_PCMPEQDirr = 1429, + X86_MMX_PCMPEQWirm = 1430, + X86_MMX_PCMPEQWirr = 1431, + X86_MMX_PCMPGTBirm = 1432, + X86_MMX_PCMPGTBirr = 1433, + X86_MMX_PCMPGTDirm = 1434, + X86_MMX_PCMPGTDirr = 1435, + X86_MMX_PCMPGTWirm = 1436, + X86_MMX_PCMPGTWirr = 1437, + X86_MMX_PEXTRWrr = 1438, + X86_MMX_PHADDDrm = 1439, + X86_MMX_PHADDDrr = 1440, + X86_MMX_PHADDSWrm = 1441, + X86_MMX_PHADDSWrr = 1442, + X86_MMX_PHADDWrm = 1443, + X86_MMX_PHADDWrr = 1444, + X86_MMX_PHSUBDrm = 1445, + X86_MMX_PHSUBDrr = 1446, + X86_MMX_PHSUBSWrm = 1447, + X86_MMX_PHSUBSWrr = 1448, + X86_MMX_PHSUBWrm = 1449, + X86_MMX_PHSUBWrr = 1450, + X86_MMX_PINSRWrm = 1451, + X86_MMX_PINSRWrr = 1452, + X86_MMX_PMADDUBSWrm = 1453, + X86_MMX_PMADDUBSWrr = 1454, + X86_MMX_PMADDWDirm = 1455, + X86_MMX_PMADDWDirr = 1456, + X86_MMX_PMAXSWirm = 1457, + X86_MMX_PMAXSWirr = 1458, + X86_MMX_PMAXUBirm = 1459, + X86_MMX_PMAXUBirr = 1460, + X86_MMX_PMINSWirm = 1461, + X86_MMX_PMINSWirr = 1462, + X86_MMX_PMINUBirm = 1463, + X86_MMX_PMINUBirr = 1464, + X86_MMX_PMOVMSKBrr = 1465, + X86_MMX_PMULHRSWrm = 1466, + X86_MMX_PMULHRSWrr = 1467, + X86_MMX_PMULHUWirm = 1468, + X86_MMX_PMULHUWirr = 1469, + X86_MMX_PMULHWirm = 1470, + X86_MMX_PMULHWirr = 1471, + X86_MMX_PMULLWirm = 1472, + X86_MMX_PMULLWirr = 1473, + X86_MMX_PMULUDQirm = 1474, + X86_MMX_PMULUDQirr = 1475, + X86_MMX_PORirm = 1476, + X86_MMX_PORirr = 1477, + X86_MMX_PSADBWirm = 1478, + X86_MMX_PSADBWirr = 1479, + X86_MMX_PSHUFBrm = 1480, + X86_MMX_PSHUFBrr = 1481, + X86_MMX_PSHUFWmi = 1482, + X86_MMX_PSHUFWri = 1483, + X86_MMX_PSIGNBrm = 1484, + X86_MMX_PSIGNBrr = 1485, + X86_MMX_PSIGNDrm = 1486, + X86_MMX_PSIGNDrr = 1487, + X86_MMX_PSIGNWrm = 1488, + X86_MMX_PSIGNWrr = 1489, + X86_MMX_PSLLDri = 1490, + X86_MMX_PSLLDrm = 1491, + X86_MMX_PSLLDrr = 1492, + X86_MMX_PSLLQri = 1493, + X86_MMX_PSLLQrm = 1494, + X86_MMX_PSLLQrr = 1495, + X86_MMX_PSLLWri = 1496, + X86_MMX_PSLLWrm = 1497, + X86_MMX_PSLLWrr = 1498, + X86_MMX_PSRADri = 1499, + X86_MMX_PSRADrm = 1500, + X86_MMX_PSRADrr = 1501, + X86_MMX_PSRAWri = 1502, + X86_MMX_PSRAWrm = 1503, + X86_MMX_PSRAWrr = 1504, + X86_MMX_PSRLDri = 1505, + X86_MMX_PSRLDrm = 1506, + X86_MMX_PSRLDrr = 1507, + X86_MMX_PSRLQri = 1508, + X86_MMX_PSRLQrm = 1509, + X86_MMX_PSRLQrr = 1510, + X86_MMX_PSRLWri = 1511, + X86_MMX_PSRLWrm = 1512, + X86_MMX_PSRLWrr = 1513, + X86_MMX_PSUBBirm = 1514, + X86_MMX_PSUBBirr = 1515, + X86_MMX_PSUBDirm = 1516, + X86_MMX_PSUBDirr = 1517, + X86_MMX_PSUBQirm = 1518, + X86_MMX_PSUBQirr = 1519, + X86_MMX_PSUBSBirm = 1520, + X86_MMX_PSUBSBirr = 1521, + X86_MMX_PSUBSWirm = 1522, + X86_MMX_PSUBSWirr = 1523, + X86_MMX_PSUBUSBirm = 1524, + X86_MMX_PSUBUSBirr = 1525, + X86_MMX_PSUBUSWirm = 1526, + X86_MMX_PSUBUSWirr = 1527, + X86_MMX_PSUBWirm = 1528, + X86_MMX_PSUBWirr = 1529, + X86_MMX_PUNPCKHBWirm = 1530, + X86_MMX_PUNPCKHBWirr = 1531, + X86_MMX_PUNPCKHDQirm = 1532, + X86_MMX_PUNPCKHDQirr = 1533, + X86_MMX_PUNPCKHWDirm = 1534, + X86_MMX_PUNPCKHWDirr = 1535, + X86_MMX_PUNPCKLBWirm = 1536, + X86_MMX_PUNPCKLBWirr = 1537, + X86_MMX_PUNPCKLDQirm = 1538, + X86_MMX_PUNPCKLDQirr = 1539, + X86_MMX_PUNPCKLWDirm = 1540, + X86_MMX_PUNPCKLWDirr = 1541, + X86_MMX_PXORirm = 1542, + X86_MMX_PXORirr = 1543, + X86_MONITORXrrr = 1544, + X86_MONITORrrr = 1545, + X86_MONTMUL = 1546, + X86_MOV16ao16 = 1547, + X86_MOV16ao32 = 1548, + X86_MOV16ao64 = 1549, + X86_MOV16mi = 1550, + X86_MOV16mr = 1551, + X86_MOV16ms = 1552, + X86_MOV16o16a = 1553, + X86_MOV16o32a = 1554, + X86_MOV16o64a = 1555, + X86_MOV16ri = 1556, + X86_MOV16ri_alt = 1557, + X86_MOV16rm = 1558, + X86_MOV16rr = 1559, + X86_MOV16rr_REV = 1560, + X86_MOV16rs = 1561, + X86_MOV16sm = 1562, + X86_MOV16sr = 1563, + X86_MOV32ao16 = 1564, + X86_MOV32ao32 = 1565, + X86_MOV32ao64 = 1566, + X86_MOV32cr = 1567, + X86_MOV32dr = 1568, + X86_MOV32mi = 1569, + X86_MOV32mr = 1570, + X86_MOV32o16a = 1571, + X86_MOV32o32a = 1572, + X86_MOV32o64a = 1573, + X86_MOV32rc = 1574, + X86_MOV32rd = 1575, + X86_MOV32ri = 1576, + X86_MOV32ri_alt = 1577, + X86_MOV32rm = 1578, + X86_MOV32rr = 1579, + X86_MOV32rr_REV = 1580, + X86_MOV32rs = 1581, + X86_MOV32sr = 1582, + X86_MOV64ao32 = 1583, + X86_MOV64ao64 = 1584, + X86_MOV64cr = 1585, + X86_MOV64dr = 1586, + X86_MOV64mi32 = 1587, + X86_MOV64mr = 1588, + X86_MOV64o32a = 1589, + X86_MOV64o64a = 1590, + X86_MOV64rc = 1591, + X86_MOV64rd = 1592, + X86_MOV64ri = 1593, + X86_MOV64ri32 = 1594, + X86_MOV64rm = 1595, + X86_MOV64rr = 1596, + X86_MOV64rr_REV = 1597, + X86_MOV64rs = 1598, + X86_MOV64sr = 1599, + X86_MOV64toPQIrm = 1600, + X86_MOV64toPQIrr = 1601, + X86_MOV64toSDrm = 1602, + X86_MOV64toSDrr = 1603, + X86_MOV8ao16 = 1604, + X86_MOV8ao32 = 1605, + X86_MOV8ao64 = 1606, + X86_MOV8mi = 1607, + X86_MOV8mr = 1608, + X86_MOV8mr_NOREX = 1609, + X86_MOV8o16a = 1610, + X86_MOV8o32a = 1611, + X86_MOV8o64a = 1612, + X86_MOV8ri = 1613, + X86_MOV8ri_alt = 1614, + X86_MOV8rm = 1615, + X86_MOV8rm_NOREX = 1616, + X86_MOV8rr = 1617, + X86_MOV8rr_NOREX = 1618, + X86_MOV8rr_REV = 1619, + X86_MOVAPDmr = 1620, + X86_MOVAPDrm = 1621, + X86_MOVAPDrr = 1622, + X86_MOVAPDrr_REV = 1623, + X86_MOVAPSmr = 1624, + X86_MOVAPSrm = 1625, + X86_MOVAPSrr = 1626, + X86_MOVAPSrr_REV = 1627, + X86_MOVBE16mr = 1628, + X86_MOVBE16rm = 1629, + X86_MOVBE32mr = 1630, + X86_MOVBE32rm = 1631, + X86_MOVBE64mr = 1632, + X86_MOVBE64rm = 1633, + X86_MOVDDUPrm = 1634, + X86_MOVDDUPrr = 1635, + X86_MOVDI2PDIrm = 1636, + X86_MOVDI2PDIrr = 1637, + X86_MOVDI2SSrm = 1638, + X86_MOVDI2SSrr = 1639, + X86_MOVDIR64B16 = 1640, + X86_MOVDIR64B32 = 1641, + X86_MOVDIR64B64 = 1642, + X86_MOVDIRI32 = 1643, + X86_MOVDIRI64 = 1644, + X86_MOVDQAmr = 1645, + X86_MOVDQArm = 1646, + X86_MOVDQArr = 1647, + X86_MOVDQArr_REV = 1648, + X86_MOVDQUmr = 1649, + X86_MOVDQUrm = 1650, + X86_MOVDQUrr = 1651, + X86_MOVDQUrr_REV = 1652, + X86_MOVHLPSrr = 1653, + X86_MOVHPDmr = 1654, + X86_MOVHPDrm = 1655, + X86_MOVHPSmr = 1656, + X86_MOVHPSrm = 1657, + X86_MOVLHPSrr = 1658, + X86_MOVLPDmr = 1659, + X86_MOVLPDrm = 1660, + X86_MOVLPSmr = 1661, + X86_MOVLPSrm = 1662, + X86_MOVMSKPDrr = 1663, + X86_MOVMSKPSrr = 1664, + X86_MOVNTDQArm = 1665, + X86_MOVNTDQmr = 1666, + X86_MOVNTI_64mr = 1667, + X86_MOVNTImr = 1668, + X86_MOVNTPDmr = 1669, + X86_MOVNTPSmr = 1670, + X86_MOVNTSD = 1671, + X86_MOVNTSS = 1672, + X86_MOVPDI2DImr = 1673, + X86_MOVPDI2DIrr = 1674, + X86_MOVPQI2QImr = 1675, + X86_MOVPQI2QIrr = 1676, + X86_MOVPQIto64mr = 1677, + X86_MOVPQIto64rr = 1678, + X86_MOVQI2PQIrm = 1679, + X86_MOVSB = 1680, + X86_MOVSDmr = 1681, + X86_MOVSDrm = 1682, + X86_MOVSDrr = 1683, + X86_MOVSDrr_REV = 1684, + X86_MOVSDto64mr = 1685, + X86_MOVSDto64rr = 1686, + X86_MOVSHDUPrm = 1687, + X86_MOVSHDUPrr = 1688, + X86_MOVSL = 1689, + X86_MOVSLDUPrm = 1690, + X86_MOVSLDUPrr = 1691, + X86_MOVSQ = 1692, + X86_MOVSS2DImr = 1693, + X86_MOVSS2DIrr = 1694, + X86_MOVSSmr = 1695, + X86_MOVSSrm = 1696, + X86_MOVSSrr = 1697, + X86_MOVSSrr_REV = 1698, + X86_MOVSW = 1699, + X86_MOVSX16rm16 = 1700, + X86_MOVSX16rm8 = 1701, + X86_MOVSX16rr16 = 1702, + X86_MOVSX16rr8 = 1703, + X86_MOVSX32rm16 = 1704, + X86_MOVSX32rm8 = 1705, + X86_MOVSX32rm8_NOREX = 1706, + X86_MOVSX32rr16 = 1707, + X86_MOVSX32rr8 = 1708, + X86_MOVSX32rr8_NOREX = 1709, + X86_MOVSX64rm16 = 1710, + X86_MOVSX64rm32 = 1711, + X86_MOVSX64rm8 = 1712, + X86_MOVSX64rr16 = 1713, + X86_MOVSX64rr32 = 1714, + X86_MOVSX64rr8 = 1715, + X86_MOVUPDmr = 1716, + X86_MOVUPDrm = 1717, + X86_MOVUPDrr = 1718, + X86_MOVUPDrr_REV = 1719, + X86_MOVUPSmr = 1720, + X86_MOVUPSrm = 1721, + X86_MOVUPSrr = 1722, + X86_MOVUPSrr_REV = 1723, + X86_MOVZPQILo2PQIrr = 1724, + X86_MOVZX16rm16 = 1725, + X86_MOVZX16rm8 = 1726, + X86_MOVZX16rr16 = 1727, + X86_MOVZX16rr8 = 1728, + X86_MOVZX32rm16 = 1729, + X86_MOVZX32rm8 = 1730, + X86_MOVZX32rm8_NOREX = 1731, + X86_MOVZX32rr16 = 1732, + X86_MOVZX32rr8 = 1733, + X86_MOVZX32rr8_NOREX = 1734, + X86_MOVZX64rm16 = 1735, + X86_MOVZX64rm8 = 1736, + X86_MOVZX64rr16 = 1737, + X86_MOVZX64rr8 = 1738, + X86_MPSADBWrmi = 1739, + X86_MPSADBWrri = 1740, + X86_MUL16m = 1741, + X86_MUL16r = 1742, + X86_MUL32m = 1743, + X86_MUL32r = 1744, + X86_MUL64m = 1745, + X86_MUL64r = 1746, + X86_MUL8m = 1747, + X86_MUL8r = 1748, + X86_MULPDrm = 1749, + X86_MULPDrr = 1750, + X86_MULPSrm = 1751, + X86_MULPSrr = 1752, + X86_MULSDrm = 1753, + X86_MULSDrm_Int = 1754, + X86_MULSDrr = 1755, + X86_MULSDrr_Int = 1756, + X86_MULSSrm = 1757, + X86_MULSSrm_Int = 1758, + X86_MULSSrr = 1759, + X86_MULSSrr_Int = 1760, + X86_MULX32rm = 1761, + X86_MULX32rr = 1762, + X86_MULX64rm = 1763, + X86_MULX64rr = 1764, + X86_MUL_F32m = 1765, + X86_MUL_F64m = 1766, + X86_MUL_FI16m = 1767, + X86_MUL_FI32m = 1768, + X86_MUL_FPrST0 = 1769, + X86_MUL_FST0r = 1770, + X86_MUL_Fp32 = 1771, + X86_MUL_Fp32m = 1772, + X86_MUL_Fp64 = 1773, + X86_MUL_Fp64m = 1774, + X86_MUL_Fp64m32 = 1775, + X86_MUL_Fp80 = 1776, + X86_MUL_Fp80m32 = 1777, + X86_MUL_Fp80m64 = 1778, + X86_MUL_FpI16m32 = 1779, + X86_MUL_FpI16m64 = 1780, + X86_MUL_FpI16m80 = 1781, + X86_MUL_FpI32m32 = 1782, + X86_MUL_FpI32m64 = 1783, + X86_MUL_FpI32m80 = 1784, + X86_MUL_FrST0 = 1785, + X86_MWAITXrrr = 1786, + X86_MWAITrr = 1787, + X86_NEG16m = 1788, + X86_NEG16r = 1789, + X86_NEG32m = 1790, + X86_NEG32r = 1791, + X86_NEG64m = 1792, + X86_NEG64r = 1793, + X86_NEG8m = 1794, + X86_NEG8r = 1795, + X86_NOOP = 1796, + X86_NOOP18_16m4 = 1797, + X86_NOOP18_16m5 = 1798, + X86_NOOP18_16m6 = 1799, + X86_NOOP18_16m7 = 1800, + X86_NOOP18_16r4 = 1801, + X86_NOOP18_16r5 = 1802, + X86_NOOP18_16r6 = 1803, + X86_NOOP18_16r7 = 1804, + X86_NOOP18_m4 = 1805, + X86_NOOP18_m5 = 1806, + X86_NOOP18_m6 = 1807, + X86_NOOP18_m7 = 1808, + X86_NOOP18_r4 = 1809, + X86_NOOP18_r5 = 1810, + X86_NOOP18_r6 = 1811, + X86_NOOP18_r7 = 1812, + X86_NOOP19rr = 1813, + X86_NOOPL = 1814, + X86_NOOPL_19 = 1815, + X86_NOOPL_1d = 1816, + X86_NOOPL_1e = 1817, + X86_NOOPLr = 1818, + X86_NOOPQ = 1819, + X86_NOOPQr = 1820, + X86_NOOPW = 1821, + X86_NOOPW_19 = 1822, + X86_NOOPW_1c = 1823, + X86_NOOPW_1d = 1824, + X86_NOOPW_1e = 1825, + X86_NOOPWr = 1826, + X86_NOT16m = 1827, + X86_NOT16r = 1828, + X86_NOT32m = 1829, + X86_NOT32r = 1830, + X86_NOT64m = 1831, + X86_NOT64r = 1832, + X86_NOT8m = 1833, + X86_NOT8r = 1834, + X86_OR16i16 = 1835, + X86_OR16mi = 1836, + X86_OR16mi8 = 1837, + X86_OR16mr = 1838, + X86_OR16ri = 1839, + X86_OR16ri8 = 1840, + X86_OR16rm = 1841, + X86_OR16rr = 1842, + X86_OR16rr_REV = 1843, + X86_OR32i32 = 1844, + X86_OR32mi = 1845, + X86_OR32mi8 = 1846, + X86_OR32mr = 1847, + X86_OR32ri = 1848, + X86_OR32ri8 = 1849, + X86_OR32rm = 1850, + X86_OR32rr = 1851, + X86_OR32rr_REV = 1852, + X86_OR64i32 = 1853, + X86_OR64mi32 = 1854, + X86_OR64mi8 = 1855, + X86_OR64mr = 1856, + X86_OR64ri32 = 1857, + X86_OR64ri8 = 1858, + X86_OR64rm = 1859, + X86_OR64rr = 1860, + X86_OR64rr_REV = 1861, + X86_OR8i8 = 1862, + X86_OR8mi = 1863, + X86_OR8mi8 = 1864, + X86_OR8mr = 1865, + X86_OR8ri = 1866, + X86_OR8ri8 = 1867, + X86_OR8rm = 1868, + X86_OR8rr = 1869, + X86_OR8rr_REV = 1870, + X86_ORPDrm = 1871, + X86_ORPDrr = 1872, + X86_ORPSrm = 1873, + X86_ORPSrr = 1874, + X86_OUT16ir = 1875, + X86_OUT16rr = 1876, + X86_OUT32ir = 1877, + X86_OUT32rr = 1878, + X86_OUT8ir = 1879, + X86_OUT8rr = 1880, + X86_OUTSB = 1881, + X86_OUTSL = 1882, + X86_OUTSW = 1883, + X86_PABSBrm = 1884, + X86_PABSBrr = 1885, + X86_PABSDrm = 1886, + X86_PABSDrr = 1887, + X86_PABSWrm = 1888, + X86_PABSWrr = 1889, + X86_PACKSSDWrm = 1890, + X86_PACKSSDWrr = 1891, + X86_PACKSSWBrm = 1892, + X86_PACKSSWBrr = 1893, + X86_PACKUSDWrm = 1894, + X86_PACKUSDWrr = 1895, + X86_PACKUSWBrm = 1896, + X86_PACKUSWBrr = 1897, + X86_PADDBrm = 1898, + X86_PADDBrr = 1899, + X86_PADDDrm = 1900, + X86_PADDDrr = 1901, + X86_PADDQrm = 1902, + X86_PADDQrr = 1903, + X86_PADDSBrm = 1904, + X86_PADDSBrr = 1905, + X86_PADDSWrm = 1906, + X86_PADDSWrr = 1907, + X86_PADDUSBrm = 1908, + X86_PADDUSBrr = 1909, + X86_PADDUSWrm = 1910, + X86_PADDUSWrr = 1911, + X86_PADDWrm = 1912, + X86_PADDWrr = 1913, + X86_PALIGNRrmi = 1914, + X86_PALIGNRrri = 1915, + X86_PANDNrm = 1916, + X86_PANDNrr = 1917, + X86_PANDrm = 1918, + X86_PANDrr = 1919, + X86_PAUSE = 1920, + X86_PAVGBrm = 1921, + X86_PAVGBrr = 1922, + X86_PAVGUSBrm = 1923, + X86_PAVGUSBrr = 1924, + X86_PAVGWrm = 1925, + X86_PAVGWrr = 1926, + X86_PBLENDVBrm0 = 1927, + X86_PBLENDVBrr0 = 1928, + X86_PBLENDWrmi = 1929, + X86_PBLENDWrri = 1930, + X86_PCLMULQDQrm = 1931, + X86_PCLMULQDQrr = 1932, + X86_PCMPEQBrm = 1933, + X86_PCMPEQBrr = 1934, + X86_PCMPEQDrm = 1935, + X86_PCMPEQDrr = 1936, + X86_PCMPEQQrm = 1937, + X86_PCMPEQQrr = 1938, + X86_PCMPEQWrm = 1939, + X86_PCMPEQWrr = 1940, + X86_PCMPESTRIrm = 1941, + X86_PCMPESTRIrr = 1942, + X86_PCMPESTRMrm = 1943, + X86_PCMPESTRMrr = 1944, + X86_PCMPGTBrm = 1945, + X86_PCMPGTBrr = 1946, + X86_PCMPGTDrm = 1947, + X86_PCMPGTDrr = 1948, + X86_PCMPGTQrm = 1949, + X86_PCMPGTQrr = 1950, + X86_PCMPGTWrm = 1951, + X86_PCMPGTWrr = 1952, + X86_PCMPISTRIrm = 1953, + X86_PCMPISTRIrr = 1954, + X86_PCMPISTRMrm = 1955, + X86_PCMPISTRMrr = 1956, + X86_PCONFIG = 1957, + X86_PDEP32rm = 1958, + X86_PDEP32rr = 1959, + X86_PDEP64rm = 1960, + X86_PDEP64rr = 1961, + X86_PEXT32rm = 1962, + X86_PEXT32rr = 1963, + X86_PEXT64rm = 1964, + X86_PEXT64rr = 1965, + X86_PEXTRBmr = 1966, + X86_PEXTRBrr = 1967, + X86_PEXTRDmr = 1968, + X86_PEXTRDrr = 1969, + X86_PEXTRQmr = 1970, + X86_PEXTRQrr = 1971, + X86_PEXTRWmr = 1972, + X86_PEXTRWrr = 1973, + X86_PEXTRWrr_REV = 1974, + X86_PF2IDrm = 1975, + X86_PF2IDrr = 1976, + X86_PF2IWrm = 1977, + X86_PF2IWrr = 1978, + X86_PFACCrm = 1979, + X86_PFACCrr = 1980, + X86_PFADDrm = 1981, + X86_PFADDrr = 1982, + X86_PFCMPEQrm = 1983, + X86_PFCMPEQrr = 1984, + X86_PFCMPGErm = 1985, + X86_PFCMPGErr = 1986, + X86_PFCMPGTrm = 1987, + X86_PFCMPGTrr = 1988, + X86_PFMAXrm = 1989, + X86_PFMAXrr = 1990, + X86_PFMINrm = 1991, + X86_PFMINrr = 1992, + X86_PFMULrm = 1993, + X86_PFMULrr = 1994, + X86_PFNACCrm = 1995, + X86_PFNACCrr = 1996, + X86_PFPNACCrm = 1997, + X86_PFPNACCrr = 1998, + X86_PFRCPIT1rm = 1999, + X86_PFRCPIT1rr = 2000, + X86_PFRCPIT2rm = 2001, + X86_PFRCPIT2rr = 2002, + X86_PFRCPrm = 2003, + X86_PFRCPrr = 2004, + X86_PFRSQIT1rm = 2005, + X86_PFRSQIT1rr = 2006, + X86_PFRSQRTrm = 2007, + X86_PFRSQRTrr = 2008, + X86_PFSUBRrm = 2009, + X86_PFSUBRrr = 2010, + X86_PFSUBrm = 2011, + X86_PFSUBrr = 2012, + X86_PHADDDrm = 2013, + X86_PHADDDrr = 2014, + X86_PHADDSWrm = 2015, + X86_PHADDSWrr = 2016, + X86_PHADDWrm = 2017, + X86_PHADDWrr = 2018, + X86_PHMINPOSUWrm = 2019, + X86_PHMINPOSUWrr = 2020, + X86_PHSUBDrm = 2021, + X86_PHSUBDrr = 2022, + X86_PHSUBSWrm = 2023, + X86_PHSUBSWrr = 2024, + X86_PHSUBWrm = 2025, + X86_PHSUBWrr = 2026, + X86_PI2FDrm = 2027, + X86_PI2FDrr = 2028, + X86_PI2FWrm = 2029, + X86_PI2FWrr = 2030, + X86_PINSRBrm = 2031, + X86_PINSRBrr = 2032, + X86_PINSRDrm = 2033, + X86_PINSRDrr = 2034, + X86_PINSRQrm = 2035, + X86_PINSRQrr = 2036, + X86_PINSRWrm = 2037, + X86_PINSRWrr = 2038, + X86_PMADDUBSWrm = 2039, + X86_PMADDUBSWrr = 2040, + X86_PMADDWDrm = 2041, + X86_PMADDWDrr = 2042, + X86_PMAXSBrm = 2043, + X86_PMAXSBrr = 2044, + X86_PMAXSDrm = 2045, + X86_PMAXSDrr = 2046, + X86_PMAXSWrm = 2047, + X86_PMAXSWrr = 2048, + X86_PMAXUBrm = 2049, + X86_PMAXUBrr = 2050, + X86_PMAXUDrm = 2051, + X86_PMAXUDrr = 2052, + X86_PMAXUWrm = 2053, + X86_PMAXUWrr = 2054, + X86_PMINSBrm = 2055, + X86_PMINSBrr = 2056, + X86_PMINSDrm = 2057, + X86_PMINSDrr = 2058, + X86_PMINSWrm = 2059, + X86_PMINSWrr = 2060, + X86_PMINUBrm = 2061, + X86_PMINUBrr = 2062, + X86_PMINUDrm = 2063, + X86_PMINUDrr = 2064, + X86_PMINUWrm = 2065, + X86_PMINUWrr = 2066, + X86_PMOVMSKBrr = 2067, + X86_PMOVSXBDrm = 2068, + X86_PMOVSXBDrr = 2069, + X86_PMOVSXBQrm = 2070, + X86_PMOVSXBQrr = 2071, + X86_PMOVSXBWrm = 2072, + X86_PMOVSXBWrr = 2073, + X86_PMOVSXDQrm = 2074, + X86_PMOVSXDQrr = 2075, + X86_PMOVSXWDrm = 2076, + X86_PMOVSXWDrr = 2077, + X86_PMOVSXWQrm = 2078, + X86_PMOVSXWQrr = 2079, + X86_PMOVZXBDrm = 2080, + X86_PMOVZXBDrr = 2081, + X86_PMOVZXBQrm = 2082, + X86_PMOVZXBQrr = 2083, + X86_PMOVZXBWrm = 2084, + X86_PMOVZXBWrr = 2085, + X86_PMOVZXDQrm = 2086, + X86_PMOVZXDQrr = 2087, + X86_PMOVZXWDrm = 2088, + X86_PMOVZXWDrr = 2089, + X86_PMOVZXWQrm = 2090, + X86_PMOVZXWQrr = 2091, + X86_PMULDQrm = 2092, + X86_PMULDQrr = 2093, + X86_PMULHRSWrm = 2094, + X86_PMULHRSWrr = 2095, + X86_PMULHRWrm = 2096, + X86_PMULHRWrr = 2097, + X86_PMULHUWrm = 2098, + X86_PMULHUWrr = 2099, + X86_PMULHWrm = 2100, + X86_PMULHWrr = 2101, + X86_PMULLDrm = 2102, + X86_PMULLDrr = 2103, + X86_PMULLWrm = 2104, + X86_PMULLWrr = 2105, + X86_PMULUDQrm = 2106, + X86_PMULUDQrr = 2107, + X86_POP16r = 2108, + X86_POP16rmm = 2109, + X86_POP16rmr = 2110, + X86_POP32r = 2111, + X86_POP32rmm = 2112, + X86_POP32rmr = 2113, + X86_POP64r = 2114, + X86_POP64rmm = 2115, + X86_POP64rmr = 2116, + X86_POPA16 = 2117, + X86_POPA32 = 2118, + X86_POPCNT16rm = 2119, + X86_POPCNT16rr = 2120, + X86_POPCNT32rm = 2121, + X86_POPCNT32rr = 2122, + X86_POPCNT64rm = 2123, + X86_POPCNT64rr = 2124, + X86_POPDS16 = 2125, + X86_POPDS32 = 2126, + X86_POPES16 = 2127, + X86_POPES32 = 2128, + X86_POPF16 = 2129, + X86_POPF32 = 2130, + X86_POPF64 = 2131, + X86_POPFS16 = 2132, + X86_POPFS32 = 2133, + X86_POPFS64 = 2134, + X86_POPGS16 = 2135, + X86_POPGS32 = 2136, + X86_POPGS64 = 2137, + X86_POPSS16 = 2138, + X86_POPSS32 = 2139, + X86_PORrm = 2140, + X86_PORrr = 2141, + X86_PREFETCH = 2142, + X86_PREFETCHNTA = 2143, + X86_PREFETCHT0 = 2144, + X86_PREFETCHT1 = 2145, + X86_PREFETCHT2 = 2146, + X86_PREFETCHW = 2147, + X86_PREFETCHWT1 = 2148, + X86_PSADBWrm = 2149, + X86_PSADBWrr = 2150, + X86_PSHUFBrm = 2151, + X86_PSHUFBrr = 2152, + X86_PSHUFDmi = 2153, + X86_PSHUFDri = 2154, + X86_PSHUFHWmi = 2155, + X86_PSHUFHWri = 2156, + X86_PSHUFLWmi = 2157, + X86_PSHUFLWri = 2158, + X86_PSIGNBrm = 2159, + X86_PSIGNBrr = 2160, + X86_PSIGNDrm = 2161, + X86_PSIGNDrr = 2162, + X86_PSIGNWrm = 2163, + X86_PSIGNWrr = 2164, + X86_PSLLDQri = 2165, + X86_PSLLDri = 2166, + X86_PSLLDrm = 2167, + X86_PSLLDrr = 2168, + X86_PSLLQri = 2169, + X86_PSLLQrm = 2170, + X86_PSLLQrr = 2171, + X86_PSLLWri = 2172, + X86_PSLLWrm = 2173, + X86_PSLLWrr = 2174, + X86_PSRADri = 2175, + X86_PSRADrm = 2176, + X86_PSRADrr = 2177, + X86_PSRAWri = 2178, + X86_PSRAWrm = 2179, + X86_PSRAWrr = 2180, + X86_PSRLDQri = 2181, + X86_PSRLDri = 2182, + X86_PSRLDrm = 2183, + X86_PSRLDrr = 2184, + X86_PSRLQri = 2185, + X86_PSRLQrm = 2186, + X86_PSRLQrr = 2187, + X86_PSRLWri = 2188, + X86_PSRLWrm = 2189, + X86_PSRLWrr = 2190, + X86_PSUBBrm = 2191, + X86_PSUBBrr = 2192, + X86_PSUBDrm = 2193, + X86_PSUBDrr = 2194, + X86_PSUBQrm = 2195, + X86_PSUBQrr = 2196, + X86_PSUBSBrm = 2197, + X86_PSUBSBrr = 2198, + X86_PSUBSWrm = 2199, + X86_PSUBSWrr = 2200, + X86_PSUBUSBrm = 2201, + X86_PSUBUSBrr = 2202, + X86_PSUBUSWrm = 2203, + X86_PSUBUSWrr = 2204, + X86_PSUBWrm = 2205, + X86_PSUBWrr = 2206, + X86_PSWAPDrm = 2207, + X86_PSWAPDrr = 2208, + X86_PTESTrm = 2209, + X86_PTESTrr = 2210, + X86_PTWRITE64m = 2211, + X86_PTWRITE64r = 2212, + X86_PTWRITEm = 2213, + X86_PTWRITEr = 2214, + X86_PUNPCKHBWrm = 2215, + X86_PUNPCKHBWrr = 2216, + X86_PUNPCKHDQrm = 2217, + X86_PUNPCKHDQrr = 2218, + X86_PUNPCKHQDQrm = 2219, + X86_PUNPCKHQDQrr = 2220, + X86_PUNPCKHWDrm = 2221, + X86_PUNPCKHWDrr = 2222, + X86_PUNPCKLBWrm = 2223, + X86_PUNPCKLBWrr = 2224, + X86_PUNPCKLDQrm = 2225, + X86_PUNPCKLDQrr = 2226, + X86_PUNPCKLQDQrm = 2227, + X86_PUNPCKLQDQrr = 2228, + X86_PUNPCKLWDrm = 2229, + X86_PUNPCKLWDrr = 2230, + X86_PUSH16i8 = 2231, + X86_PUSH16r = 2232, + X86_PUSH16rmm = 2233, + X86_PUSH16rmr = 2234, + X86_PUSH32i8 = 2235, + X86_PUSH32r = 2236, + X86_PUSH32rmm = 2237, + X86_PUSH32rmr = 2238, + X86_PUSH64i32 = 2239, + X86_PUSH64i8 = 2240, + X86_PUSH64r = 2241, + X86_PUSH64rmm = 2242, + X86_PUSH64rmr = 2243, + X86_PUSHA16 = 2244, + X86_PUSHA32 = 2245, + X86_PUSHCS16 = 2246, + X86_PUSHCS32 = 2247, + X86_PUSHDS16 = 2248, + X86_PUSHDS32 = 2249, + X86_PUSHES16 = 2250, + X86_PUSHES32 = 2251, + X86_PUSHF16 = 2252, + X86_PUSHF32 = 2253, + X86_PUSHF64 = 2254, + X86_PUSHFS16 = 2255, + X86_PUSHFS32 = 2256, + X86_PUSHFS64 = 2257, + X86_PUSHGS16 = 2258, + X86_PUSHGS32 = 2259, + X86_PUSHGS64 = 2260, + X86_PUSHSS16 = 2261, + X86_PUSHSS32 = 2262, + X86_PUSHi16 = 2263, + X86_PUSHi32 = 2264, + X86_PXORrm = 2265, + X86_PXORrr = 2266, + X86_RCL16m1 = 2267, + X86_RCL16mCL = 2268, + X86_RCL16mi = 2269, + X86_RCL16r1 = 2270, + X86_RCL16rCL = 2271, + X86_RCL16ri = 2272, + X86_RCL32m1 = 2273, + X86_RCL32mCL = 2274, + X86_RCL32mi = 2275, + X86_RCL32r1 = 2276, + X86_RCL32rCL = 2277, + X86_RCL32ri = 2278, + X86_RCL64m1 = 2279, + X86_RCL64mCL = 2280, + X86_RCL64mi = 2281, + X86_RCL64r1 = 2282, + X86_RCL64rCL = 2283, + X86_RCL64ri = 2284, + X86_RCL8m1 = 2285, + X86_RCL8mCL = 2286, + X86_RCL8mi = 2287, + X86_RCL8r1 = 2288, + X86_RCL8rCL = 2289, + X86_RCL8ri = 2290, + X86_RCPPSm = 2291, + X86_RCPPSr = 2292, + X86_RCPSSm = 2293, + X86_RCPSSm_Int = 2294, + X86_RCPSSr = 2295, + X86_RCPSSr_Int = 2296, + X86_RCR16m1 = 2297, + X86_RCR16mCL = 2298, + X86_RCR16mi = 2299, + X86_RCR16r1 = 2300, + X86_RCR16rCL = 2301, + X86_RCR16ri = 2302, + X86_RCR32m1 = 2303, + X86_RCR32mCL = 2304, + X86_RCR32mi = 2305, + X86_RCR32r1 = 2306, + X86_RCR32rCL = 2307, + X86_RCR32ri = 2308, + X86_RCR64m1 = 2309, + X86_RCR64mCL = 2310, + X86_RCR64mi = 2311, + X86_RCR64r1 = 2312, + X86_RCR64rCL = 2313, + X86_RCR64ri = 2314, + X86_RCR8m1 = 2315, + X86_RCR8mCL = 2316, + X86_RCR8mi = 2317, + X86_RCR8r1 = 2318, + X86_RCR8rCL = 2319, + X86_RCR8ri = 2320, + X86_RDFSBASE = 2321, + X86_RDFSBASE64 = 2322, + X86_RDGSBASE = 2323, + X86_RDGSBASE64 = 2324, + X86_RDMSR = 2325, + X86_RDPID32 = 2326, + X86_RDPID64 = 2327, + X86_RDPKRUr = 2328, + X86_RDPMC = 2329, + X86_RDRAND16r = 2330, + X86_RDRAND32r = 2331, + X86_RDRAND64r = 2332, + X86_RDSEED16r = 2333, + X86_RDSEED32r = 2334, + X86_RDSEED64r = 2335, + X86_RDSSPD = 2336, + X86_RDSSPQ = 2337, + X86_RDTSC = 2338, + X86_RDTSCP = 2339, + X86_REPNE_PREFIX = 2340, + X86_REP_PREFIX = 2341, + X86_RETIL = 2342, + X86_RETIQ = 2343, + X86_RETIW = 2344, + X86_RETL = 2345, + X86_RETQ = 2346, + X86_RETW = 2347, + X86_REX64_PREFIX = 2348, + X86_ROL16m1 = 2349, + X86_ROL16mCL = 2350, + X86_ROL16mi = 2351, + X86_ROL16r1 = 2352, + X86_ROL16rCL = 2353, + X86_ROL16ri = 2354, + X86_ROL32m1 = 2355, + X86_ROL32mCL = 2356, + X86_ROL32mi = 2357, + X86_ROL32r1 = 2358, + X86_ROL32rCL = 2359, + X86_ROL32ri = 2360, + X86_ROL64m1 = 2361, + X86_ROL64mCL = 2362, + X86_ROL64mi = 2363, + X86_ROL64r1 = 2364, + X86_ROL64rCL = 2365, + X86_ROL64ri = 2366, + X86_ROL8m1 = 2367, + X86_ROL8mCL = 2368, + X86_ROL8mi = 2369, + X86_ROL8r1 = 2370, + X86_ROL8rCL = 2371, + X86_ROL8ri = 2372, + X86_ROR16m1 = 2373, + X86_ROR16mCL = 2374, + X86_ROR16mi = 2375, + X86_ROR16r1 = 2376, + X86_ROR16rCL = 2377, + X86_ROR16ri = 2378, + X86_ROR32m1 = 2379, + X86_ROR32mCL = 2380, + X86_ROR32mi = 2381, + X86_ROR32r1 = 2382, + X86_ROR32rCL = 2383, + X86_ROR32ri = 2384, + X86_ROR64m1 = 2385, + X86_ROR64mCL = 2386, + X86_ROR64mi = 2387, + X86_ROR64r1 = 2388, + X86_ROR64rCL = 2389, + X86_ROR64ri = 2390, + X86_ROR8m1 = 2391, + X86_ROR8mCL = 2392, + X86_ROR8mi = 2393, + X86_ROR8r1 = 2394, + X86_ROR8rCL = 2395, + X86_ROR8ri = 2396, + X86_RORX32mi = 2397, + X86_RORX32ri = 2398, + X86_RORX64mi = 2399, + X86_RORX64ri = 2400, + X86_ROUNDPDm = 2401, + X86_ROUNDPDr = 2402, + X86_ROUNDPSm = 2403, + X86_ROUNDPSr = 2404, + X86_ROUNDSDm = 2405, + X86_ROUNDSDm_Int = 2406, + X86_ROUNDSDr = 2407, + X86_ROUNDSDr_Int = 2408, + X86_ROUNDSSm = 2409, + X86_ROUNDSSm_Int = 2410, + X86_ROUNDSSr = 2411, + X86_ROUNDSSr_Int = 2412, + X86_RSM = 2413, + X86_RSQRTPSm = 2414, + X86_RSQRTPSr = 2415, + X86_RSQRTSSm = 2416, + X86_RSQRTSSm_Int = 2417, + X86_RSQRTSSr = 2418, + X86_RSQRTSSr_Int = 2419, + X86_RSTORSSP = 2420, + X86_SAHF = 2421, + X86_SAL16m1 = 2422, + X86_SAL16mCL = 2423, + X86_SAL16mi = 2424, + X86_SAL16r1 = 2425, + X86_SAL16rCL = 2426, + X86_SAL16ri = 2427, + X86_SAL32m1 = 2428, + X86_SAL32mCL = 2429, + X86_SAL32mi = 2430, + X86_SAL32r1 = 2431, + X86_SAL32rCL = 2432, + X86_SAL32ri = 2433, + X86_SAL64m1 = 2434, + X86_SAL64mCL = 2435, + X86_SAL64mi = 2436, + X86_SAL64r1 = 2437, + X86_SAL64rCL = 2438, + X86_SAL64ri = 2439, + X86_SAL8m1 = 2440, + X86_SAL8mCL = 2441, + X86_SAL8mi = 2442, + X86_SAL8r1 = 2443, + X86_SAL8rCL = 2444, + X86_SAL8ri = 2445, + X86_SALC = 2446, + X86_SAR16m1 = 2447, + X86_SAR16mCL = 2448, + X86_SAR16mi = 2449, + X86_SAR16r1 = 2450, + X86_SAR16rCL = 2451, + X86_SAR16ri = 2452, + X86_SAR32m1 = 2453, + X86_SAR32mCL = 2454, + X86_SAR32mi = 2455, + X86_SAR32r1 = 2456, + X86_SAR32rCL = 2457, + X86_SAR32ri = 2458, + X86_SAR64m1 = 2459, + X86_SAR64mCL = 2460, + X86_SAR64mi = 2461, + X86_SAR64r1 = 2462, + X86_SAR64rCL = 2463, + X86_SAR64ri = 2464, + X86_SAR8m1 = 2465, + X86_SAR8mCL = 2466, + X86_SAR8mi = 2467, + X86_SAR8r1 = 2468, + X86_SAR8rCL = 2469, + X86_SAR8ri = 2470, + X86_SARX32rm = 2471, + X86_SARX32rr = 2472, + X86_SARX64rm = 2473, + X86_SARX64rr = 2474, + X86_SAVEPREVSSP = 2475, + X86_SBB16i16 = 2476, + X86_SBB16mi = 2477, + X86_SBB16mi8 = 2478, + X86_SBB16mr = 2479, + X86_SBB16ri = 2480, + X86_SBB16ri8 = 2481, + X86_SBB16rm = 2482, + X86_SBB16rr = 2483, + X86_SBB16rr_REV = 2484, + X86_SBB32i32 = 2485, + X86_SBB32mi = 2486, + X86_SBB32mi8 = 2487, + X86_SBB32mr = 2488, + X86_SBB32ri = 2489, + X86_SBB32ri8 = 2490, + X86_SBB32rm = 2491, + X86_SBB32rr = 2492, + X86_SBB32rr_REV = 2493, + X86_SBB64i32 = 2494, + X86_SBB64mi32 = 2495, + X86_SBB64mi8 = 2496, + X86_SBB64mr = 2497, + X86_SBB64ri32 = 2498, + X86_SBB64ri8 = 2499, + X86_SBB64rm = 2500, + X86_SBB64rr = 2501, + X86_SBB64rr_REV = 2502, + X86_SBB8i8 = 2503, + X86_SBB8mi = 2504, + X86_SBB8mi8 = 2505, + X86_SBB8mr = 2506, + X86_SBB8ri = 2507, + X86_SBB8ri8 = 2508, + X86_SBB8rm = 2509, + X86_SBB8rr = 2510, + X86_SBB8rr_REV = 2511, + X86_SCASB = 2512, + X86_SCASL = 2513, + X86_SCASQ = 2514, + X86_SCASW = 2515, + X86_SETAEm = 2516, + X86_SETAEr = 2517, + X86_SETAm = 2518, + X86_SETAr = 2519, + X86_SETBEm = 2520, + X86_SETBEr = 2521, + X86_SETBm = 2522, + X86_SETBr = 2523, + X86_SETEm = 2524, + X86_SETEr = 2525, + X86_SETGEm = 2526, + X86_SETGEr = 2527, + X86_SETGm = 2528, + X86_SETGr = 2529, + X86_SETLEm = 2530, + X86_SETLEr = 2531, + X86_SETLm = 2532, + X86_SETLr = 2533, + X86_SETNEm = 2534, + X86_SETNEr = 2535, + X86_SETNOm = 2536, + X86_SETNOr = 2537, + X86_SETNPm = 2538, + X86_SETNPr = 2539, + X86_SETNSm = 2540, + X86_SETNSr = 2541, + X86_SETOm = 2542, + X86_SETOr = 2543, + X86_SETPm = 2544, + X86_SETPr = 2545, + X86_SETSSBSY = 2546, + X86_SETSm = 2547, + X86_SETSr = 2548, + X86_SFENCE = 2549, + X86_SGDT16m = 2550, + X86_SGDT32m = 2551, + X86_SGDT64m = 2552, + X86_SHA1MSG1rm = 2553, + X86_SHA1MSG1rr = 2554, + X86_SHA1MSG2rm = 2555, + X86_SHA1MSG2rr = 2556, + X86_SHA1NEXTErm = 2557, + X86_SHA1NEXTErr = 2558, + X86_SHA1RNDS4rmi = 2559, + X86_SHA1RNDS4rri = 2560, + X86_SHA256MSG1rm = 2561, + X86_SHA256MSG1rr = 2562, + X86_SHA256MSG2rm = 2563, + X86_SHA256MSG2rr = 2564, + X86_SHA256RNDS2rm = 2565, + X86_SHA256RNDS2rr = 2566, + X86_SHL16m1 = 2567, + X86_SHL16mCL = 2568, + X86_SHL16mi = 2569, + X86_SHL16r1 = 2570, + X86_SHL16rCL = 2571, + X86_SHL16ri = 2572, + X86_SHL32m1 = 2573, + X86_SHL32mCL = 2574, + X86_SHL32mi = 2575, + X86_SHL32r1 = 2576, + X86_SHL32rCL = 2577, + X86_SHL32ri = 2578, + X86_SHL64m1 = 2579, + X86_SHL64mCL = 2580, + X86_SHL64mi = 2581, + X86_SHL64r1 = 2582, + X86_SHL64rCL = 2583, + X86_SHL64ri = 2584, + X86_SHL8m1 = 2585, + X86_SHL8mCL = 2586, + X86_SHL8mi = 2587, + X86_SHL8r1 = 2588, + X86_SHL8rCL = 2589, + X86_SHL8ri = 2590, + X86_SHLD16mrCL = 2591, + X86_SHLD16mri8 = 2592, + X86_SHLD16rrCL = 2593, + X86_SHLD16rri8 = 2594, + X86_SHLD32mrCL = 2595, + X86_SHLD32mri8 = 2596, + X86_SHLD32rrCL = 2597, + X86_SHLD32rri8 = 2598, + X86_SHLD64mrCL = 2599, + X86_SHLD64mri8 = 2600, + X86_SHLD64rrCL = 2601, + X86_SHLD64rri8 = 2602, + X86_SHLX32rm = 2603, + X86_SHLX32rr = 2604, + X86_SHLX64rm = 2605, + X86_SHLX64rr = 2606, + X86_SHR16m1 = 2607, + X86_SHR16mCL = 2608, + X86_SHR16mi = 2609, + X86_SHR16r1 = 2610, + X86_SHR16rCL = 2611, + X86_SHR16ri = 2612, + X86_SHR32m1 = 2613, + X86_SHR32mCL = 2614, + X86_SHR32mi = 2615, + X86_SHR32r1 = 2616, + X86_SHR32rCL = 2617, + X86_SHR32ri = 2618, + X86_SHR64m1 = 2619, + X86_SHR64mCL = 2620, + X86_SHR64mi = 2621, + X86_SHR64r1 = 2622, + X86_SHR64rCL = 2623, + X86_SHR64ri = 2624, + X86_SHR8m1 = 2625, + X86_SHR8mCL = 2626, + X86_SHR8mi = 2627, + X86_SHR8r1 = 2628, + X86_SHR8rCL = 2629, + X86_SHR8ri = 2630, + X86_SHRD16mrCL = 2631, + X86_SHRD16mri8 = 2632, + X86_SHRD16rrCL = 2633, + X86_SHRD16rri8 = 2634, + X86_SHRD32mrCL = 2635, + X86_SHRD32mri8 = 2636, + X86_SHRD32rrCL = 2637, + X86_SHRD32rri8 = 2638, + X86_SHRD64mrCL = 2639, + X86_SHRD64mri8 = 2640, + X86_SHRD64rrCL = 2641, + X86_SHRD64rri8 = 2642, + X86_SHRX32rm = 2643, + X86_SHRX32rr = 2644, + X86_SHRX64rm = 2645, + X86_SHRX64rr = 2646, + X86_SHUFPDrmi = 2647, + X86_SHUFPDrri = 2648, + X86_SHUFPSrmi = 2649, + X86_SHUFPSrri = 2650, + X86_SIDT16m = 2651, + X86_SIDT32m = 2652, + X86_SIDT64m = 2653, + X86_SIN_F = 2654, + X86_SIN_Fp32 = 2655, + X86_SIN_Fp64 = 2656, + X86_SIN_Fp80 = 2657, + X86_SKINIT = 2658, + X86_SLDT16m = 2659, + X86_SLDT16r = 2660, + X86_SLDT32r = 2661, + X86_SLDT64r = 2662, + X86_SLWPCB = 2663, + X86_SLWPCB64 = 2664, + X86_SMSW16m = 2665, + X86_SMSW16r = 2666, + X86_SMSW32r = 2667, + X86_SMSW64r = 2668, + X86_SQRTPDm = 2669, + X86_SQRTPDr = 2670, + X86_SQRTPSm = 2671, + X86_SQRTPSr = 2672, + X86_SQRTSDm = 2673, + X86_SQRTSDm_Int = 2674, + X86_SQRTSDr = 2675, + X86_SQRTSDr_Int = 2676, + X86_SQRTSSm = 2677, + X86_SQRTSSm_Int = 2678, + X86_SQRTSSr = 2679, + X86_SQRTSSr_Int = 2680, + X86_SQRT_F = 2681, + X86_SQRT_Fp32 = 2682, + X86_SQRT_Fp64 = 2683, + X86_SQRT_Fp80 = 2684, + X86_STAC = 2685, + X86_STC = 2686, + X86_STD = 2687, + X86_STGI = 2688, + X86_STI = 2689, + X86_STMXCSR = 2690, + X86_STOSB = 2691, + X86_STOSL = 2692, + X86_STOSQ = 2693, + X86_STOSW = 2694, + X86_STR16r = 2695, + X86_STR32r = 2696, + X86_STR64r = 2697, + X86_STRm = 2698, + X86_ST_F32m = 2699, + X86_ST_F64m = 2700, + X86_ST_FP32m = 2701, + X86_ST_FP64m = 2702, + X86_ST_FP80m = 2703, + X86_ST_FPrr = 2704, + X86_ST_Fp32m = 2705, + X86_ST_Fp64m = 2706, + X86_ST_Fp64m32 = 2707, + X86_ST_Fp80m32 = 2708, + X86_ST_Fp80m64 = 2709, + X86_ST_FpP32m = 2710, + X86_ST_FpP64m = 2711, + X86_ST_FpP64m32 = 2712, + X86_ST_FpP80m = 2713, + X86_ST_FpP80m32 = 2714, + X86_ST_FpP80m64 = 2715, + X86_ST_Frr = 2716, + X86_SUB16i16 = 2717, + X86_SUB16mi = 2718, + X86_SUB16mi8 = 2719, + X86_SUB16mr = 2720, + X86_SUB16ri = 2721, + X86_SUB16ri8 = 2722, + X86_SUB16rm = 2723, + X86_SUB16rr = 2724, + X86_SUB16rr_REV = 2725, + X86_SUB32i32 = 2726, + X86_SUB32mi = 2727, + X86_SUB32mi8 = 2728, + X86_SUB32mr = 2729, + X86_SUB32ri = 2730, + X86_SUB32ri8 = 2731, + X86_SUB32rm = 2732, + X86_SUB32rr = 2733, + X86_SUB32rr_REV = 2734, + X86_SUB64i32 = 2735, + X86_SUB64mi32 = 2736, + X86_SUB64mi8 = 2737, + X86_SUB64mr = 2738, + X86_SUB64ri32 = 2739, + X86_SUB64ri8 = 2740, + X86_SUB64rm = 2741, + X86_SUB64rr = 2742, + X86_SUB64rr_REV = 2743, + X86_SUB8i8 = 2744, + X86_SUB8mi = 2745, + X86_SUB8mi8 = 2746, + X86_SUB8mr = 2747, + X86_SUB8ri = 2748, + X86_SUB8ri8 = 2749, + X86_SUB8rm = 2750, + X86_SUB8rr = 2751, + X86_SUB8rr_REV = 2752, + X86_SUBPDrm = 2753, + X86_SUBPDrr = 2754, + X86_SUBPSrm = 2755, + X86_SUBPSrr = 2756, + X86_SUBR_F32m = 2757, + X86_SUBR_F64m = 2758, + X86_SUBR_FI16m = 2759, + X86_SUBR_FI32m = 2760, + X86_SUBR_FPrST0 = 2761, + X86_SUBR_FST0r = 2762, + X86_SUBR_Fp32m = 2763, + X86_SUBR_Fp64m = 2764, + X86_SUBR_Fp64m32 = 2765, + X86_SUBR_Fp80m32 = 2766, + X86_SUBR_Fp80m64 = 2767, + X86_SUBR_FpI16m32 = 2768, + X86_SUBR_FpI16m64 = 2769, + X86_SUBR_FpI16m80 = 2770, + X86_SUBR_FpI32m32 = 2771, + X86_SUBR_FpI32m64 = 2772, + X86_SUBR_FpI32m80 = 2773, + X86_SUBR_FrST0 = 2774, + X86_SUBSDrm = 2775, + X86_SUBSDrm_Int = 2776, + X86_SUBSDrr = 2777, + X86_SUBSDrr_Int = 2778, + X86_SUBSSrm = 2779, + X86_SUBSSrm_Int = 2780, + X86_SUBSSrr = 2781, + X86_SUBSSrr_Int = 2782, + X86_SUB_F32m = 2783, + X86_SUB_F64m = 2784, + X86_SUB_FI16m = 2785, + X86_SUB_FI32m = 2786, + X86_SUB_FPrST0 = 2787, + X86_SUB_FST0r = 2788, + X86_SUB_Fp32 = 2789, + X86_SUB_Fp32m = 2790, + X86_SUB_Fp64 = 2791, + X86_SUB_Fp64m = 2792, + X86_SUB_Fp64m32 = 2793, + X86_SUB_Fp80 = 2794, + X86_SUB_Fp80m32 = 2795, + X86_SUB_Fp80m64 = 2796, + X86_SUB_FpI16m32 = 2797, + X86_SUB_FpI16m64 = 2798, + X86_SUB_FpI16m80 = 2799, + X86_SUB_FpI32m32 = 2800, + X86_SUB_FpI32m64 = 2801, + X86_SUB_FpI32m80 = 2802, + X86_SUB_FrST0 = 2803, + X86_SWAPGS = 2804, + X86_SYSCALL = 2805, + X86_SYSENTER = 2806, + X86_SYSEXIT = 2807, + X86_SYSEXIT64 = 2808, + X86_SYSRET = 2809, + X86_SYSRET64 = 2810, + X86_T1MSKC32rm = 2811, + X86_T1MSKC32rr = 2812, + X86_T1MSKC64rm = 2813, + X86_T1MSKC64rr = 2814, + X86_TEST16i16 = 2815, + X86_TEST16mi = 2816, + X86_TEST16mi_alt = 2817, + X86_TEST16mr = 2818, + X86_TEST16ri = 2819, + X86_TEST16ri_alt = 2820, + X86_TEST16rr = 2821, + X86_TEST32i32 = 2822, + X86_TEST32mi = 2823, + X86_TEST32mi_alt = 2824, + X86_TEST32mr = 2825, + X86_TEST32ri = 2826, + X86_TEST32ri_alt = 2827, + X86_TEST32rr = 2828, + X86_TEST64i32 = 2829, + X86_TEST64mi32 = 2830, + X86_TEST64mi32_alt = 2831, + X86_TEST64mr = 2832, + X86_TEST64ri32 = 2833, + X86_TEST64ri32_alt = 2834, + X86_TEST64rr = 2835, + X86_TEST8i8 = 2836, + X86_TEST8mi = 2837, + X86_TEST8mi_alt = 2838, + X86_TEST8mr = 2839, + X86_TEST8ri = 2840, + X86_TEST8ri_alt = 2841, + X86_TEST8rr = 2842, + X86_TPAUSE = 2843, + X86_TST_F = 2844, + X86_TST_Fp32 = 2845, + X86_TST_Fp64 = 2846, + X86_TST_Fp80 = 2847, + X86_TZCNT16rm = 2848, + X86_TZCNT16rr = 2849, + X86_TZCNT32rm = 2850, + X86_TZCNT32rr = 2851, + X86_TZCNT64rm = 2852, + X86_TZCNT64rr = 2853, + X86_TZMSK32rm = 2854, + X86_TZMSK32rr = 2855, + X86_TZMSK64rm = 2856, + X86_TZMSK64rr = 2857, + X86_UCOMISDrm = 2858, + X86_UCOMISDrm_Int = 2859, + X86_UCOMISDrr = 2860, + X86_UCOMISDrr_Int = 2861, + X86_UCOMISSrm = 2862, + X86_UCOMISSrm_Int = 2863, + X86_UCOMISSrr = 2864, + X86_UCOMISSrr_Int = 2865, + X86_UCOM_FIPr = 2866, + X86_UCOM_FIr = 2867, + X86_UCOM_FPPr = 2868, + X86_UCOM_FPr = 2869, + X86_UCOM_FpIr32 = 2870, + X86_UCOM_FpIr64 = 2871, + X86_UCOM_FpIr80 = 2872, + X86_UCOM_Fpr32 = 2873, + X86_UCOM_Fpr64 = 2874, + X86_UCOM_Fpr80 = 2875, + X86_UCOM_Fr = 2876, + X86_UD0 = 2877, + X86_UD1 = 2878, + X86_UD2 = 2879, + X86_UMONITOR16 = 2880, + X86_UMONITOR32 = 2881, + X86_UMONITOR64 = 2882, + X86_UMWAIT = 2883, + X86_UNPCKHPDrm = 2884, + X86_UNPCKHPDrr = 2885, + X86_UNPCKHPSrm = 2886, + X86_UNPCKHPSrr = 2887, + X86_UNPCKLPDrm = 2888, + X86_UNPCKLPDrr = 2889, + X86_UNPCKLPSrm = 2890, + X86_UNPCKLPSrr = 2891, + X86_V4FMADDPSrm = 2892, + X86_V4FMADDPSrmk = 2893, + X86_V4FMADDPSrmkz = 2894, + X86_V4FMADDSSrm = 2895, + X86_V4FMADDSSrmk = 2896, + X86_V4FMADDSSrmkz = 2897, + X86_V4FNMADDPSrm = 2898, + X86_V4FNMADDPSrmk = 2899, + X86_V4FNMADDPSrmkz = 2900, + X86_V4FNMADDSSrm = 2901, + X86_V4FNMADDSSrmk = 2902, + X86_V4FNMADDSSrmkz = 2903, + X86_VADDPDYrm = 2904, + X86_VADDPDYrr = 2905, + X86_VADDPDZ128rm = 2906, + X86_VADDPDZ128rmb = 2907, + X86_VADDPDZ128rmbk = 2908, + X86_VADDPDZ128rmbkz = 2909, + X86_VADDPDZ128rmk = 2910, + X86_VADDPDZ128rmkz = 2911, + X86_VADDPDZ128rr = 2912, + X86_VADDPDZ128rrk = 2913, + X86_VADDPDZ128rrkz = 2914, + X86_VADDPDZ256rm = 2915, + X86_VADDPDZ256rmb = 2916, + X86_VADDPDZ256rmbk = 2917, + X86_VADDPDZ256rmbkz = 2918, + X86_VADDPDZ256rmk = 2919, + X86_VADDPDZ256rmkz = 2920, + X86_VADDPDZ256rr = 2921, + X86_VADDPDZ256rrk = 2922, + X86_VADDPDZ256rrkz = 2923, + X86_VADDPDZrm = 2924, + X86_VADDPDZrmb = 2925, + X86_VADDPDZrmbk = 2926, + X86_VADDPDZrmbkz = 2927, + X86_VADDPDZrmk = 2928, + X86_VADDPDZrmkz = 2929, + X86_VADDPDZrr = 2930, + X86_VADDPDZrrb = 2931, + X86_VADDPDZrrbk = 2932, + X86_VADDPDZrrbkz = 2933, + X86_VADDPDZrrk = 2934, + X86_VADDPDZrrkz = 2935, + X86_VADDPDrm = 2936, + X86_VADDPDrr = 2937, + X86_VADDPSYrm = 2938, + X86_VADDPSYrr = 2939, + X86_VADDPSZ128rm = 2940, + X86_VADDPSZ128rmb = 2941, + X86_VADDPSZ128rmbk = 2942, + X86_VADDPSZ128rmbkz = 2943, + X86_VADDPSZ128rmk = 2944, + X86_VADDPSZ128rmkz = 2945, + X86_VADDPSZ128rr = 2946, + X86_VADDPSZ128rrk = 2947, + X86_VADDPSZ128rrkz = 2948, + X86_VADDPSZ256rm = 2949, + X86_VADDPSZ256rmb = 2950, + X86_VADDPSZ256rmbk = 2951, + X86_VADDPSZ256rmbkz = 2952, + X86_VADDPSZ256rmk = 2953, + X86_VADDPSZ256rmkz = 2954, + X86_VADDPSZ256rr = 2955, + X86_VADDPSZ256rrk = 2956, + X86_VADDPSZ256rrkz = 2957, + X86_VADDPSZrm = 2958, + X86_VADDPSZrmb = 2959, + X86_VADDPSZrmbk = 2960, + X86_VADDPSZrmbkz = 2961, + X86_VADDPSZrmk = 2962, + X86_VADDPSZrmkz = 2963, + X86_VADDPSZrr = 2964, + X86_VADDPSZrrb = 2965, + X86_VADDPSZrrbk = 2966, + X86_VADDPSZrrbkz = 2967, + X86_VADDPSZrrk = 2968, + X86_VADDPSZrrkz = 2969, + X86_VADDPSrm = 2970, + X86_VADDPSrr = 2971, + X86_VADDSDZrm = 2972, + X86_VADDSDZrm_Int = 2973, + X86_VADDSDZrm_Intk = 2974, + X86_VADDSDZrm_Intkz = 2975, + X86_VADDSDZrr = 2976, + X86_VADDSDZrr_Int = 2977, + X86_VADDSDZrr_Intk = 2978, + X86_VADDSDZrr_Intkz = 2979, + X86_VADDSDZrrb_Int = 2980, + X86_VADDSDZrrb_Intk = 2981, + X86_VADDSDZrrb_Intkz = 2982, + X86_VADDSDrm = 2983, + X86_VADDSDrm_Int = 2984, + X86_VADDSDrr = 2985, + X86_VADDSDrr_Int = 2986, + X86_VADDSSZrm = 2987, + X86_VADDSSZrm_Int = 2988, + X86_VADDSSZrm_Intk = 2989, + X86_VADDSSZrm_Intkz = 2990, + X86_VADDSSZrr = 2991, + X86_VADDSSZrr_Int = 2992, + X86_VADDSSZrr_Intk = 2993, + X86_VADDSSZrr_Intkz = 2994, + X86_VADDSSZrrb_Int = 2995, + X86_VADDSSZrrb_Intk = 2996, + X86_VADDSSZrrb_Intkz = 2997, + X86_VADDSSrm = 2998, + X86_VADDSSrm_Int = 2999, + X86_VADDSSrr = 3000, + X86_VADDSSrr_Int = 3001, + X86_VADDSUBPDYrm = 3002, + X86_VADDSUBPDYrr = 3003, + X86_VADDSUBPDrm = 3004, + X86_VADDSUBPDrr = 3005, + X86_VADDSUBPSYrm = 3006, + X86_VADDSUBPSYrr = 3007, + X86_VADDSUBPSrm = 3008, + X86_VADDSUBPSrr = 3009, + X86_VAESDECLASTYrm = 3010, + X86_VAESDECLASTYrr = 3011, + X86_VAESDECLASTZ128rm = 3012, + X86_VAESDECLASTZ128rr = 3013, + X86_VAESDECLASTZ256rm = 3014, + X86_VAESDECLASTZ256rr = 3015, + X86_VAESDECLASTZrm = 3016, + X86_VAESDECLASTZrr = 3017, + X86_VAESDECLASTrm = 3018, + X86_VAESDECLASTrr = 3019, + X86_VAESDECYrm = 3020, + X86_VAESDECYrr = 3021, + X86_VAESDECZ128rm = 3022, + X86_VAESDECZ128rr = 3023, + X86_VAESDECZ256rm = 3024, + X86_VAESDECZ256rr = 3025, + X86_VAESDECZrm = 3026, + X86_VAESDECZrr = 3027, + X86_VAESDECrm = 3028, + X86_VAESDECrr = 3029, + X86_VAESENCLASTYrm = 3030, + X86_VAESENCLASTYrr = 3031, + X86_VAESENCLASTZ128rm = 3032, + X86_VAESENCLASTZ128rr = 3033, + X86_VAESENCLASTZ256rm = 3034, + X86_VAESENCLASTZ256rr = 3035, + X86_VAESENCLASTZrm = 3036, + X86_VAESENCLASTZrr = 3037, + X86_VAESENCLASTrm = 3038, + X86_VAESENCLASTrr = 3039, + X86_VAESENCYrm = 3040, + X86_VAESENCYrr = 3041, + X86_VAESENCZ128rm = 3042, + X86_VAESENCZ128rr = 3043, + X86_VAESENCZ256rm = 3044, + X86_VAESENCZ256rr = 3045, + X86_VAESENCZrm = 3046, + X86_VAESENCZrr = 3047, + X86_VAESENCrm = 3048, + X86_VAESENCrr = 3049, + X86_VAESIMCrm = 3050, + X86_VAESIMCrr = 3051, + X86_VAESKEYGENASSIST128rm = 3052, + X86_VAESKEYGENASSIST128rr = 3053, + X86_VALIGNDZ128rmbi = 3054, + X86_VALIGNDZ128rmbik = 3055, + X86_VALIGNDZ128rmbikz = 3056, + X86_VALIGNDZ128rmi = 3057, + X86_VALIGNDZ128rmik = 3058, + X86_VALIGNDZ128rmikz = 3059, + X86_VALIGNDZ128rri = 3060, + X86_VALIGNDZ128rrik = 3061, + X86_VALIGNDZ128rrikz = 3062, + X86_VALIGNDZ256rmbi = 3063, + X86_VALIGNDZ256rmbik = 3064, + X86_VALIGNDZ256rmbikz = 3065, + X86_VALIGNDZ256rmi = 3066, + X86_VALIGNDZ256rmik = 3067, + X86_VALIGNDZ256rmikz = 3068, + X86_VALIGNDZ256rri = 3069, + X86_VALIGNDZ256rrik = 3070, + X86_VALIGNDZ256rrikz = 3071, + X86_VALIGNDZrmbi = 3072, + X86_VALIGNDZrmbik = 3073, + X86_VALIGNDZrmbikz = 3074, + X86_VALIGNDZrmi = 3075, + X86_VALIGNDZrmik = 3076, + X86_VALIGNDZrmikz = 3077, + X86_VALIGNDZrri = 3078, + X86_VALIGNDZrrik = 3079, + X86_VALIGNDZrrikz = 3080, + X86_VALIGNQZ128rmbi = 3081, + X86_VALIGNQZ128rmbik = 3082, + X86_VALIGNQZ128rmbikz = 3083, + X86_VALIGNQZ128rmi = 3084, + X86_VALIGNQZ128rmik = 3085, + X86_VALIGNQZ128rmikz = 3086, + X86_VALIGNQZ128rri = 3087, + X86_VALIGNQZ128rrik = 3088, + X86_VALIGNQZ128rrikz = 3089, + X86_VALIGNQZ256rmbi = 3090, + X86_VALIGNQZ256rmbik = 3091, + X86_VALIGNQZ256rmbikz = 3092, + X86_VALIGNQZ256rmi = 3093, + X86_VALIGNQZ256rmik = 3094, + X86_VALIGNQZ256rmikz = 3095, + X86_VALIGNQZ256rri = 3096, + X86_VALIGNQZ256rrik = 3097, + X86_VALIGNQZ256rrikz = 3098, + X86_VALIGNQZrmbi = 3099, + X86_VALIGNQZrmbik = 3100, + X86_VALIGNQZrmbikz = 3101, + X86_VALIGNQZrmi = 3102, + X86_VALIGNQZrmik = 3103, + X86_VALIGNQZrmikz = 3104, + X86_VALIGNQZrri = 3105, + X86_VALIGNQZrrik = 3106, + X86_VALIGNQZrrikz = 3107, + X86_VANDNPDYrm = 3108, + X86_VANDNPDYrr = 3109, + X86_VANDNPDZ128rm = 3110, + X86_VANDNPDZ128rmb = 3111, + X86_VANDNPDZ128rmbk = 3112, + X86_VANDNPDZ128rmbkz = 3113, + X86_VANDNPDZ128rmk = 3114, + X86_VANDNPDZ128rmkz = 3115, + X86_VANDNPDZ128rr = 3116, + X86_VANDNPDZ128rrk = 3117, + X86_VANDNPDZ128rrkz = 3118, + X86_VANDNPDZ256rm = 3119, + X86_VANDNPDZ256rmb = 3120, + X86_VANDNPDZ256rmbk = 3121, + X86_VANDNPDZ256rmbkz = 3122, + X86_VANDNPDZ256rmk = 3123, + X86_VANDNPDZ256rmkz = 3124, + X86_VANDNPDZ256rr = 3125, + X86_VANDNPDZ256rrk = 3126, + X86_VANDNPDZ256rrkz = 3127, + X86_VANDNPDZrm = 3128, + X86_VANDNPDZrmb = 3129, + X86_VANDNPDZrmbk = 3130, + X86_VANDNPDZrmbkz = 3131, + X86_VANDNPDZrmk = 3132, + X86_VANDNPDZrmkz = 3133, + X86_VANDNPDZrr = 3134, + X86_VANDNPDZrrk = 3135, + X86_VANDNPDZrrkz = 3136, + X86_VANDNPDrm = 3137, + X86_VANDNPDrr = 3138, + X86_VANDNPSYrm = 3139, + X86_VANDNPSYrr = 3140, + X86_VANDNPSZ128rm = 3141, + X86_VANDNPSZ128rmb = 3142, + X86_VANDNPSZ128rmbk = 3143, + X86_VANDNPSZ128rmbkz = 3144, + X86_VANDNPSZ128rmk = 3145, + X86_VANDNPSZ128rmkz = 3146, + X86_VANDNPSZ128rr = 3147, + X86_VANDNPSZ128rrk = 3148, + X86_VANDNPSZ128rrkz = 3149, + X86_VANDNPSZ256rm = 3150, + X86_VANDNPSZ256rmb = 3151, + X86_VANDNPSZ256rmbk = 3152, + X86_VANDNPSZ256rmbkz = 3153, + X86_VANDNPSZ256rmk = 3154, + X86_VANDNPSZ256rmkz = 3155, + X86_VANDNPSZ256rr = 3156, + X86_VANDNPSZ256rrk = 3157, + X86_VANDNPSZ256rrkz = 3158, + X86_VANDNPSZrm = 3159, + X86_VANDNPSZrmb = 3160, + X86_VANDNPSZrmbk = 3161, + X86_VANDNPSZrmbkz = 3162, + X86_VANDNPSZrmk = 3163, + X86_VANDNPSZrmkz = 3164, + X86_VANDNPSZrr = 3165, + X86_VANDNPSZrrk = 3166, + X86_VANDNPSZrrkz = 3167, + X86_VANDNPSrm = 3168, + X86_VANDNPSrr = 3169, + X86_VANDPDYrm = 3170, + X86_VANDPDYrr = 3171, + X86_VANDPDZ128rm = 3172, + X86_VANDPDZ128rmb = 3173, + X86_VANDPDZ128rmbk = 3174, + X86_VANDPDZ128rmbkz = 3175, + X86_VANDPDZ128rmk = 3176, + X86_VANDPDZ128rmkz = 3177, + X86_VANDPDZ128rr = 3178, + X86_VANDPDZ128rrk = 3179, + X86_VANDPDZ128rrkz = 3180, + X86_VANDPDZ256rm = 3181, + X86_VANDPDZ256rmb = 3182, + X86_VANDPDZ256rmbk = 3183, + X86_VANDPDZ256rmbkz = 3184, + X86_VANDPDZ256rmk = 3185, + X86_VANDPDZ256rmkz = 3186, + X86_VANDPDZ256rr = 3187, + X86_VANDPDZ256rrk = 3188, + X86_VANDPDZ256rrkz = 3189, + X86_VANDPDZrm = 3190, + X86_VANDPDZrmb = 3191, + X86_VANDPDZrmbk = 3192, + X86_VANDPDZrmbkz = 3193, + X86_VANDPDZrmk = 3194, + X86_VANDPDZrmkz = 3195, + X86_VANDPDZrr = 3196, + X86_VANDPDZrrk = 3197, + X86_VANDPDZrrkz = 3198, + X86_VANDPDrm = 3199, + X86_VANDPDrr = 3200, + X86_VANDPSYrm = 3201, + X86_VANDPSYrr = 3202, + X86_VANDPSZ128rm = 3203, + X86_VANDPSZ128rmb = 3204, + X86_VANDPSZ128rmbk = 3205, + X86_VANDPSZ128rmbkz = 3206, + X86_VANDPSZ128rmk = 3207, + X86_VANDPSZ128rmkz = 3208, + X86_VANDPSZ128rr = 3209, + X86_VANDPSZ128rrk = 3210, + X86_VANDPSZ128rrkz = 3211, + X86_VANDPSZ256rm = 3212, + X86_VANDPSZ256rmb = 3213, + X86_VANDPSZ256rmbk = 3214, + X86_VANDPSZ256rmbkz = 3215, + X86_VANDPSZ256rmk = 3216, + X86_VANDPSZ256rmkz = 3217, + X86_VANDPSZ256rr = 3218, + X86_VANDPSZ256rrk = 3219, + X86_VANDPSZ256rrkz = 3220, + X86_VANDPSZrm = 3221, + X86_VANDPSZrmb = 3222, + X86_VANDPSZrmbk = 3223, + X86_VANDPSZrmbkz = 3224, + X86_VANDPSZrmk = 3225, + X86_VANDPSZrmkz = 3226, + X86_VANDPSZrr = 3227, + X86_VANDPSZrrk = 3228, + X86_VANDPSZrrkz = 3229, + X86_VANDPSrm = 3230, + X86_VANDPSrr = 3231, + X86_VBLENDMPDZ128rm = 3232, + X86_VBLENDMPDZ128rmb = 3233, + X86_VBLENDMPDZ128rmbk = 3234, + X86_VBLENDMPDZ128rmbkz = 3235, + X86_VBLENDMPDZ128rmk = 3236, + X86_VBLENDMPDZ128rmkz = 3237, + X86_VBLENDMPDZ128rr = 3238, + X86_VBLENDMPDZ128rrk = 3239, + X86_VBLENDMPDZ128rrkz = 3240, + X86_VBLENDMPDZ256rm = 3241, + X86_VBLENDMPDZ256rmb = 3242, + X86_VBLENDMPDZ256rmbk = 3243, + X86_VBLENDMPDZ256rmbkz = 3244, + X86_VBLENDMPDZ256rmk = 3245, + X86_VBLENDMPDZ256rmkz = 3246, + X86_VBLENDMPDZ256rr = 3247, + X86_VBLENDMPDZ256rrk = 3248, + X86_VBLENDMPDZ256rrkz = 3249, + X86_VBLENDMPDZrm = 3250, + X86_VBLENDMPDZrmb = 3251, + X86_VBLENDMPDZrmbk = 3252, + X86_VBLENDMPDZrmbkz = 3253, + X86_VBLENDMPDZrmk = 3254, + X86_VBLENDMPDZrmkz = 3255, + X86_VBLENDMPDZrr = 3256, + X86_VBLENDMPDZrrk = 3257, + X86_VBLENDMPDZrrkz = 3258, + X86_VBLENDMPSZ128rm = 3259, + X86_VBLENDMPSZ128rmb = 3260, + X86_VBLENDMPSZ128rmbk = 3261, + X86_VBLENDMPSZ128rmbkz = 3262, + X86_VBLENDMPSZ128rmk = 3263, + X86_VBLENDMPSZ128rmkz = 3264, + X86_VBLENDMPSZ128rr = 3265, + X86_VBLENDMPSZ128rrk = 3266, + X86_VBLENDMPSZ128rrkz = 3267, + X86_VBLENDMPSZ256rm = 3268, + X86_VBLENDMPSZ256rmb = 3269, + X86_VBLENDMPSZ256rmbk = 3270, + X86_VBLENDMPSZ256rmbkz = 3271, + X86_VBLENDMPSZ256rmk = 3272, + X86_VBLENDMPSZ256rmkz = 3273, + X86_VBLENDMPSZ256rr = 3274, + X86_VBLENDMPSZ256rrk = 3275, + X86_VBLENDMPSZ256rrkz = 3276, + X86_VBLENDMPSZrm = 3277, + X86_VBLENDMPSZrmb = 3278, + X86_VBLENDMPSZrmbk = 3279, + X86_VBLENDMPSZrmbkz = 3280, + X86_VBLENDMPSZrmk = 3281, + X86_VBLENDMPSZrmkz = 3282, + X86_VBLENDMPSZrr = 3283, + X86_VBLENDMPSZrrk = 3284, + X86_VBLENDMPSZrrkz = 3285, + X86_VBLENDPDYrmi = 3286, + X86_VBLENDPDYrri = 3287, + X86_VBLENDPDrmi = 3288, + X86_VBLENDPDrri = 3289, + X86_VBLENDPSYrmi = 3290, + X86_VBLENDPSYrri = 3291, + X86_VBLENDPSrmi = 3292, + X86_VBLENDPSrri = 3293, + X86_VBLENDVPDYrm = 3294, + X86_VBLENDVPDYrr = 3295, + X86_VBLENDVPDrm = 3296, + X86_VBLENDVPDrr = 3297, + X86_VBLENDVPSYrm = 3298, + X86_VBLENDVPSYrr = 3299, + X86_VBLENDVPSrm = 3300, + X86_VBLENDVPSrr = 3301, + X86_VBROADCASTF128 = 3302, + X86_VBROADCASTF32X2Z256m = 3303, + X86_VBROADCASTF32X2Z256mk = 3304, + X86_VBROADCASTF32X2Z256mkz = 3305, + X86_VBROADCASTF32X2Z256r = 3306, + X86_VBROADCASTF32X2Z256rk = 3307, + X86_VBROADCASTF32X2Z256rkz = 3308, + X86_VBROADCASTF32X2Zm = 3309, + X86_VBROADCASTF32X2Zmk = 3310, + X86_VBROADCASTF32X2Zmkz = 3311, + X86_VBROADCASTF32X2Zr = 3312, + X86_VBROADCASTF32X2Zrk = 3313, + X86_VBROADCASTF32X2Zrkz = 3314, + X86_VBROADCASTF32X4Z256rm = 3315, + X86_VBROADCASTF32X4Z256rmk = 3316, + X86_VBROADCASTF32X4Z256rmkz = 3317, + X86_VBROADCASTF32X4rm = 3318, + X86_VBROADCASTF32X4rmk = 3319, + X86_VBROADCASTF32X4rmkz = 3320, + X86_VBROADCASTF32X8rm = 3321, + X86_VBROADCASTF32X8rmk = 3322, + X86_VBROADCASTF32X8rmkz = 3323, + X86_VBROADCASTF64X2Z128rm = 3324, + X86_VBROADCASTF64X2Z128rmk = 3325, + X86_VBROADCASTF64X2Z128rmkz = 3326, + X86_VBROADCASTF64X2rm = 3327, + X86_VBROADCASTF64X2rmk = 3328, + X86_VBROADCASTF64X2rmkz = 3329, + X86_VBROADCASTF64X4rm = 3330, + X86_VBROADCASTF64X4rmk = 3331, + X86_VBROADCASTF64X4rmkz = 3332, + X86_VBROADCASTI128 = 3333, + X86_VBROADCASTI32X2Z128m = 3334, + X86_VBROADCASTI32X2Z128mk = 3335, + X86_VBROADCASTI32X2Z128mkz = 3336, + X86_VBROADCASTI32X2Z128r = 3337, + X86_VBROADCASTI32X2Z128rk = 3338, + X86_VBROADCASTI32X2Z128rkz = 3339, + X86_VBROADCASTI32X2Z256m = 3340, + X86_VBROADCASTI32X2Z256mk = 3341, + X86_VBROADCASTI32X2Z256mkz = 3342, + X86_VBROADCASTI32X2Z256r = 3343, + X86_VBROADCASTI32X2Z256rk = 3344, + X86_VBROADCASTI32X2Z256rkz = 3345, + X86_VBROADCASTI32X2Zm = 3346, + X86_VBROADCASTI32X2Zmk = 3347, + X86_VBROADCASTI32X2Zmkz = 3348, + X86_VBROADCASTI32X2Zr = 3349, + X86_VBROADCASTI32X2Zrk = 3350, + X86_VBROADCASTI32X2Zrkz = 3351, + X86_VBROADCASTI32X4Z256rm = 3352, + X86_VBROADCASTI32X4Z256rmk = 3353, + X86_VBROADCASTI32X4Z256rmkz = 3354, + X86_VBROADCASTI32X4rm = 3355, + X86_VBROADCASTI32X4rmk = 3356, + X86_VBROADCASTI32X4rmkz = 3357, + X86_VBROADCASTI32X8rm = 3358, + X86_VBROADCASTI32X8rmk = 3359, + X86_VBROADCASTI32X8rmkz = 3360, + X86_VBROADCASTI64X2Z128rm = 3361, + X86_VBROADCASTI64X2Z128rmk = 3362, + X86_VBROADCASTI64X2Z128rmkz = 3363, + X86_VBROADCASTI64X2rm = 3364, + X86_VBROADCASTI64X2rmk = 3365, + X86_VBROADCASTI64X2rmkz = 3366, + X86_VBROADCASTI64X4rm = 3367, + X86_VBROADCASTI64X4rmk = 3368, + X86_VBROADCASTI64X4rmkz = 3369, + X86_VBROADCASTSDYrm = 3370, + X86_VBROADCASTSDYrr = 3371, + X86_VBROADCASTSDZ256m = 3372, + X86_VBROADCASTSDZ256mk = 3373, + X86_VBROADCASTSDZ256mkz = 3374, + X86_VBROADCASTSDZ256r = 3375, + X86_VBROADCASTSDZ256rk = 3376, + X86_VBROADCASTSDZ256rkz = 3377, + X86_VBROADCASTSDZm = 3378, + X86_VBROADCASTSDZmk = 3379, + X86_VBROADCASTSDZmkz = 3380, + X86_VBROADCASTSDZr = 3381, + X86_VBROADCASTSDZrk = 3382, + X86_VBROADCASTSDZrkz = 3383, + X86_VBROADCASTSSYrm = 3384, + X86_VBROADCASTSSYrr = 3385, + X86_VBROADCASTSSZ128m = 3386, + X86_VBROADCASTSSZ128mk = 3387, + X86_VBROADCASTSSZ128mkz = 3388, + X86_VBROADCASTSSZ128r = 3389, + X86_VBROADCASTSSZ128rk = 3390, + X86_VBROADCASTSSZ128rkz = 3391, + X86_VBROADCASTSSZ256m = 3392, + X86_VBROADCASTSSZ256mk = 3393, + X86_VBROADCASTSSZ256mkz = 3394, + X86_VBROADCASTSSZ256r = 3395, + X86_VBROADCASTSSZ256rk = 3396, + X86_VBROADCASTSSZ256rkz = 3397, + X86_VBROADCASTSSZm = 3398, + X86_VBROADCASTSSZmk = 3399, + X86_VBROADCASTSSZmkz = 3400, + X86_VBROADCASTSSZr = 3401, + X86_VBROADCASTSSZrk = 3402, + X86_VBROADCASTSSZrkz = 3403, + X86_VBROADCASTSSrm = 3404, + X86_VBROADCASTSSrr = 3405, + X86_VCMPPDYrmi = 3406, + X86_VCMPPDYrmi_alt = 3407, + X86_VCMPPDYrri = 3408, + X86_VCMPPDYrri_alt = 3409, + X86_VCMPPDZ128rmbi = 3410, + X86_VCMPPDZ128rmbi_alt = 3411, + X86_VCMPPDZ128rmbi_altk = 3412, + X86_VCMPPDZ128rmbik = 3413, + X86_VCMPPDZ128rmi = 3414, + X86_VCMPPDZ128rmi_alt = 3415, + X86_VCMPPDZ128rmi_altk = 3416, + X86_VCMPPDZ128rmik = 3417, + X86_VCMPPDZ128rri = 3418, + X86_VCMPPDZ128rri_alt = 3419, + X86_VCMPPDZ128rri_altk = 3420, + X86_VCMPPDZ128rrik = 3421, + X86_VCMPPDZ256rmbi = 3422, + X86_VCMPPDZ256rmbi_alt = 3423, + X86_VCMPPDZ256rmbi_altk = 3424, + X86_VCMPPDZ256rmbik = 3425, + X86_VCMPPDZ256rmi = 3426, + X86_VCMPPDZ256rmi_alt = 3427, + X86_VCMPPDZ256rmi_altk = 3428, + X86_VCMPPDZ256rmik = 3429, + X86_VCMPPDZ256rri = 3430, + X86_VCMPPDZ256rri_alt = 3431, + X86_VCMPPDZ256rri_altk = 3432, + X86_VCMPPDZ256rrik = 3433, + X86_VCMPPDZrmbi = 3434, + X86_VCMPPDZrmbi_alt = 3435, + X86_VCMPPDZrmbi_altk = 3436, + X86_VCMPPDZrmbik = 3437, + X86_VCMPPDZrmi = 3438, + X86_VCMPPDZrmi_alt = 3439, + X86_VCMPPDZrmi_altk = 3440, + X86_VCMPPDZrmik = 3441, + X86_VCMPPDZrri = 3442, + X86_VCMPPDZrri_alt = 3443, + X86_VCMPPDZrri_altk = 3444, + X86_VCMPPDZrrib = 3445, + X86_VCMPPDZrrib_alt = 3446, + X86_VCMPPDZrrib_altk = 3447, + X86_VCMPPDZrribk = 3448, + X86_VCMPPDZrrik = 3449, + X86_VCMPPDrmi = 3450, + X86_VCMPPDrmi_alt = 3451, + X86_VCMPPDrri = 3452, + X86_VCMPPDrri_alt = 3453, + X86_VCMPPSYrmi = 3454, + X86_VCMPPSYrmi_alt = 3455, + X86_VCMPPSYrri = 3456, + X86_VCMPPSYrri_alt = 3457, + X86_VCMPPSZ128rmbi = 3458, + X86_VCMPPSZ128rmbi_alt = 3459, + X86_VCMPPSZ128rmbi_altk = 3460, + X86_VCMPPSZ128rmbik = 3461, + X86_VCMPPSZ128rmi = 3462, + X86_VCMPPSZ128rmi_alt = 3463, + X86_VCMPPSZ128rmi_altk = 3464, + X86_VCMPPSZ128rmik = 3465, + X86_VCMPPSZ128rri = 3466, + X86_VCMPPSZ128rri_alt = 3467, + X86_VCMPPSZ128rri_altk = 3468, + X86_VCMPPSZ128rrik = 3469, + X86_VCMPPSZ256rmbi = 3470, + X86_VCMPPSZ256rmbi_alt = 3471, + X86_VCMPPSZ256rmbi_altk = 3472, + X86_VCMPPSZ256rmbik = 3473, + X86_VCMPPSZ256rmi = 3474, + X86_VCMPPSZ256rmi_alt = 3475, + X86_VCMPPSZ256rmi_altk = 3476, + X86_VCMPPSZ256rmik = 3477, + X86_VCMPPSZ256rri = 3478, + X86_VCMPPSZ256rri_alt = 3479, + X86_VCMPPSZ256rri_altk = 3480, + X86_VCMPPSZ256rrik = 3481, + X86_VCMPPSZrmbi = 3482, + X86_VCMPPSZrmbi_alt = 3483, + X86_VCMPPSZrmbi_altk = 3484, + X86_VCMPPSZrmbik = 3485, + X86_VCMPPSZrmi = 3486, + X86_VCMPPSZrmi_alt = 3487, + X86_VCMPPSZrmi_altk = 3488, + X86_VCMPPSZrmik = 3489, + X86_VCMPPSZrri = 3490, + X86_VCMPPSZrri_alt = 3491, + X86_VCMPPSZrri_altk = 3492, + X86_VCMPPSZrrib = 3493, + X86_VCMPPSZrrib_alt = 3494, + X86_VCMPPSZrrib_altk = 3495, + X86_VCMPPSZrribk = 3496, + X86_VCMPPSZrrik = 3497, + X86_VCMPPSrmi = 3498, + X86_VCMPPSrmi_alt = 3499, + X86_VCMPPSrri = 3500, + X86_VCMPPSrri_alt = 3501, + X86_VCMPSDZrm = 3502, + X86_VCMPSDZrm_Int = 3503, + X86_VCMPSDZrm_Intk = 3504, + X86_VCMPSDZrmi_alt = 3505, + X86_VCMPSDZrmi_altk = 3506, + X86_VCMPSDZrr = 3507, + X86_VCMPSDZrr_Int = 3508, + X86_VCMPSDZrr_Intk = 3509, + X86_VCMPSDZrrb_Int = 3510, + X86_VCMPSDZrrb_Intk = 3511, + X86_VCMPSDZrrb_alt = 3512, + X86_VCMPSDZrrb_altk = 3513, + X86_VCMPSDZrri_alt = 3514, + X86_VCMPSDZrri_altk = 3515, + X86_VCMPSDrm = 3516, + X86_VCMPSDrm_Int = 3517, + X86_VCMPSDrm_alt = 3518, + X86_VCMPSDrr = 3519, + X86_VCMPSDrr_Int = 3520, + X86_VCMPSDrr_alt = 3521, + X86_VCMPSSZrm = 3522, + X86_VCMPSSZrm_Int = 3523, + X86_VCMPSSZrm_Intk = 3524, + X86_VCMPSSZrmi_alt = 3525, + X86_VCMPSSZrmi_altk = 3526, + X86_VCMPSSZrr = 3527, + X86_VCMPSSZrr_Int = 3528, + X86_VCMPSSZrr_Intk = 3529, + X86_VCMPSSZrrb_Int = 3530, + X86_VCMPSSZrrb_Intk = 3531, + X86_VCMPSSZrrb_alt = 3532, + X86_VCMPSSZrrb_altk = 3533, + X86_VCMPSSZrri_alt = 3534, + X86_VCMPSSZrri_altk = 3535, + X86_VCMPSSrm = 3536, + X86_VCMPSSrm_Int = 3537, + X86_VCMPSSrm_alt = 3538, + X86_VCMPSSrr = 3539, + X86_VCMPSSrr_Int = 3540, + X86_VCMPSSrr_alt = 3541, + X86_VCOMISDZrm = 3542, + X86_VCOMISDZrm_Int = 3543, + X86_VCOMISDZrr = 3544, + X86_VCOMISDZrr_Int = 3545, + X86_VCOMISDZrrb = 3546, + X86_VCOMISDrm = 3547, + X86_VCOMISDrm_Int = 3548, + X86_VCOMISDrr = 3549, + X86_VCOMISDrr_Int = 3550, + X86_VCOMISSZrm = 3551, + X86_VCOMISSZrm_Int = 3552, + X86_VCOMISSZrr = 3553, + X86_VCOMISSZrr_Int = 3554, + X86_VCOMISSZrrb = 3555, + X86_VCOMISSrm = 3556, + X86_VCOMISSrm_Int = 3557, + X86_VCOMISSrr = 3558, + X86_VCOMISSrr_Int = 3559, + X86_VCOMPRESSPDZ128mr = 3560, + X86_VCOMPRESSPDZ128mrk = 3561, + X86_VCOMPRESSPDZ128rr = 3562, + X86_VCOMPRESSPDZ128rrk = 3563, + X86_VCOMPRESSPDZ128rrkz = 3564, + X86_VCOMPRESSPDZ256mr = 3565, + X86_VCOMPRESSPDZ256mrk = 3566, + X86_VCOMPRESSPDZ256rr = 3567, + X86_VCOMPRESSPDZ256rrk = 3568, + X86_VCOMPRESSPDZ256rrkz = 3569, + X86_VCOMPRESSPDZmr = 3570, + X86_VCOMPRESSPDZmrk = 3571, + X86_VCOMPRESSPDZrr = 3572, + X86_VCOMPRESSPDZrrk = 3573, + X86_VCOMPRESSPDZrrkz = 3574, + X86_VCOMPRESSPSZ128mr = 3575, + X86_VCOMPRESSPSZ128mrk = 3576, + X86_VCOMPRESSPSZ128rr = 3577, + X86_VCOMPRESSPSZ128rrk = 3578, + X86_VCOMPRESSPSZ128rrkz = 3579, + X86_VCOMPRESSPSZ256mr = 3580, + X86_VCOMPRESSPSZ256mrk = 3581, + X86_VCOMPRESSPSZ256rr = 3582, + X86_VCOMPRESSPSZ256rrk = 3583, + X86_VCOMPRESSPSZ256rrkz = 3584, + X86_VCOMPRESSPSZmr = 3585, + X86_VCOMPRESSPSZmrk = 3586, + X86_VCOMPRESSPSZrr = 3587, + X86_VCOMPRESSPSZrrk = 3588, + X86_VCOMPRESSPSZrrkz = 3589, + X86_VCVTDQ2PDYrm = 3590, + X86_VCVTDQ2PDYrr = 3591, + X86_VCVTDQ2PDZ128rm = 3592, + X86_VCVTDQ2PDZ128rmb = 3593, + X86_VCVTDQ2PDZ128rmbk = 3594, + X86_VCVTDQ2PDZ128rmbkz = 3595, + X86_VCVTDQ2PDZ128rmk = 3596, + X86_VCVTDQ2PDZ128rmkz = 3597, + X86_VCVTDQ2PDZ128rr = 3598, + X86_VCVTDQ2PDZ128rrk = 3599, + X86_VCVTDQ2PDZ128rrkz = 3600, + X86_VCVTDQ2PDZ256rm = 3601, + X86_VCVTDQ2PDZ256rmb = 3602, + X86_VCVTDQ2PDZ256rmbk = 3603, + X86_VCVTDQ2PDZ256rmbkz = 3604, + X86_VCVTDQ2PDZ256rmk = 3605, + X86_VCVTDQ2PDZ256rmkz = 3606, + X86_VCVTDQ2PDZ256rr = 3607, + X86_VCVTDQ2PDZ256rrk = 3608, + X86_VCVTDQ2PDZ256rrkz = 3609, + X86_VCVTDQ2PDZrm = 3610, + X86_VCVTDQ2PDZrmb = 3611, + X86_VCVTDQ2PDZrmbk = 3612, + X86_VCVTDQ2PDZrmbkz = 3613, + X86_VCVTDQ2PDZrmk = 3614, + X86_VCVTDQ2PDZrmkz = 3615, + X86_VCVTDQ2PDZrr = 3616, + X86_VCVTDQ2PDZrrk = 3617, + X86_VCVTDQ2PDZrrkz = 3618, + X86_VCVTDQ2PDrm = 3619, + X86_VCVTDQ2PDrr = 3620, + X86_VCVTDQ2PSYrm = 3621, + X86_VCVTDQ2PSYrr = 3622, + X86_VCVTDQ2PSZ128rm = 3623, + X86_VCVTDQ2PSZ128rmb = 3624, + X86_VCVTDQ2PSZ128rmbk = 3625, + X86_VCVTDQ2PSZ128rmbkz = 3626, + X86_VCVTDQ2PSZ128rmk = 3627, + X86_VCVTDQ2PSZ128rmkz = 3628, + X86_VCVTDQ2PSZ128rr = 3629, + X86_VCVTDQ2PSZ128rrk = 3630, + X86_VCVTDQ2PSZ128rrkz = 3631, + X86_VCVTDQ2PSZ256rm = 3632, + X86_VCVTDQ2PSZ256rmb = 3633, + X86_VCVTDQ2PSZ256rmbk = 3634, + X86_VCVTDQ2PSZ256rmbkz = 3635, + X86_VCVTDQ2PSZ256rmk = 3636, + X86_VCVTDQ2PSZ256rmkz = 3637, + X86_VCVTDQ2PSZ256rr = 3638, + X86_VCVTDQ2PSZ256rrk = 3639, + X86_VCVTDQ2PSZ256rrkz = 3640, + X86_VCVTDQ2PSZrm = 3641, + X86_VCVTDQ2PSZrmb = 3642, + X86_VCVTDQ2PSZrmbk = 3643, + X86_VCVTDQ2PSZrmbkz = 3644, + X86_VCVTDQ2PSZrmk = 3645, + X86_VCVTDQ2PSZrmkz = 3646, + X86_VCVTDQ2PSZrr = 3647, + X86_VCVTDQ2PSZrrb = 3648, + X86_VCVTDQ2PSZrrbk = 3649, + X86_VCVTDQ2PSZrrbkz = 3650, + X86_VCVTDQ2PSZrrk = 3651, + X86_VCVTDQ2PSZrrkz = 3652, + X86_VCVTDQ2PSrm = 3653, + X86_VCVTDQ2PSrr = 3654, + X86_VCVTPD2DQYrm = 3655, + X86_VCVTPD2DQYrr = 3656, + X86_VCVTPD2DQZ128rm = 3657, + X86_VCVTPD2DQZ128rmb = 3658, + X86_VCVTPD2DQZ128rmbk = 3659, + X86_VCVTPD2DQZ128rmbkz = 3660, + X86_VCVTPD2DQZ128rmk = 3661, + X86_VCVTPD2DQZ128rmkz = 3662, + X86_VCVTPD2DQZ128rr = 3663, + X86_VCVTPD2DQZ128rrk = 3664, + X86_VCVTPD2DQZ128rrkz = 3665, + X86_VCVTPD2DQZ256rm = 3666, + X86_VCVTPD2DQZ256rmb = 3667, + X86_VCVTPD2DQZ256rmbk = 3668, + X86_VCVTPD2DQZ256rmbkz = 3669, + X86_VCVTPD2DQZ256rmk = 3670, + X86_VCVTPD2DQZ256rmkz = 3671, + X86_VCVTPD2DQZ256rr = 3672, + X86_VCVTPD2DQZ256rrk = 3673, + X86_VCVTPD2DQZ256rrkz = 3674, + X86_VCVTPD2DQZrm = 3675, + X86_VCVTPD2DQZrmb = 3676, + X86_VCVTPD2DQZrmbk = 3677, + X86_VCVTPD2DQZrmbkz = 3678, + X86_VCVTPD2DQZrmk = 3679, + X86_VCVTPD2DQZrmkz = 3680, + X86_VCVTPD2DQZrr = 3681, + X86_VCVTPD2DQZrrb = 3682, + X86_VCVTPD2DQZrrbk = 3683, + X86_VCVTPD2DQZrrbkz = 3684, + X86_VCVTPD2DQZrrk = 3685, + X86_VCVTPD2DQZrrkz = 3686, + X86_VCVTPD2DQrm = 3687, + X86_VCVTPD2DQrr = 3688, + X86_VCVTPD2PSYrm = 3689, + X86_VCVTPD2PSYrr = 3690, + X86_VCVTPD2PSZ128rm = 3691, + X86_VCVTPD2PSZ128rmb = 3692, + X86_VCVTPD2PSZ128rmbk = 3693, + X86_VCVTPD2PSZ128rmbkz = 3694, + X86_VCVTPD2PSZ128rmk = 3695, + X86_VCVTPD2PSZ128rmkz = 3696, + X86_VCVTPD2PSZ128rr = 3697, + X86_VCVTPD2PSZ128rrk = 3698, + X86_VCVTPD2PSZ128rrkz = 3699, + X86_VCVTPD2PSZ256rm = 3700, + X86_VCVTPD2PSZ256rmb = 3701, + X86_VCVTPD2PSZ256rmbk = 3702, + X86_VCVTPD2PSZ256rmbkz = 3703, + X86_VCVTPD2PSZ256rmk = 3704, + X86_VCVTPD2PSZ256rmkz = 3705, + X86_VCVTPD2PSZ256rr = 3706, + X86_VCVTPD2PSZ256rrk = 3707, + X86_VCVTPD2PSZ256rrkz = 3708, + X86_VCVTPD2PSZrm = 3709, + X86_VCVTPD2PSZrmb = 3710, + X86_VCVTPD2PSZrmbk = 3711, + X86_VCVTPD2PSZrmbkz = 3712, + X86_VCVTPD2PSZrmk = 3713, + X86_VCVTPD2PSZrmkz = 3714, + X86_VCVTPD2PSZrr = 3715, + X86_VCVTPD2PSZrrb = 3716, + X86_VCVTPD2PSZrrbk = 3717, + X86_VCVTPD2PSZrrbkz = 3718, + X86_VCVTPD2PSZrrk = 3719, + X86_VCVTPD2PSZrrkz = 3720, + X86_VCVTPD2PSrm = 3721, + X86_VCVTPD2PSrr = 3722, + X86_VCVTPD2QQZ128rm = 3723, + X86_VCVTPD2QQZ128rmb = 3724, + X86_VCVTPD2QQZ128rmbk = 3725, + X86_VCVTPD2QQZ128rmbkz = 3726, + X86_VCVTPD2QQZ128rmk = 3727, + X86_VCVTPD2QQZ128rmkz = 3728, + X86_VCVTPD2QQZ128rr = 3729, + X86_VCVTPD2QQZ128rrk = 3730, + X86_VCVTPD2QQZ128rrkz = 3731, + X86_VCVTPD2QQZ256rm = 3732, + X86_VCVTPD2QQZ256rmb = 3733, + X86_VCVTPD2QQZ256rmbk = 3734, + X86_VCVTPD2QQZ256rmbkz = 3735, + X86_VCVTPD2QQZ256rmk = 3736, + X86_VCVTPD2QQZ256rmkz = 3737, + X86_VCVTPD2QQZ256rr = 3738, + X86_VCVTPD2QQZ256rrk = 3739, + X86_VCVTPD2QQZ256rrkz = 3740, + X86_VCVTPD2QQZrm = 3741, + X86_VCVTPD2QQZrmb = 3742, + X86_VCVTPD2QQZrmbk = 3743, + X86_VCVTPD2QQZrmbkz = 3744, + X86_VCVTPD2QQZrmk = 3745, + X86_VCVTPD2QQZrmkz = 3746, + X86_VCVTPD2QQZrr = 3747, + X86_VCVTPD2QQZrrb = 3748, + X86_VCVTPD2QQZrrbk = 3749, + X86_VCVTPD2QQZrrbkz = 3750, + X86_VCVTPD2QQZrrk = 3751, + X86_VCVTPD2QQZrrkz = 3752, + X86_VCVTPD2UDQZ128rm = 3753, + X86_VCVTPD2UDQZ128rmb = 3754, + X86_VCVTPD2UDQZ128rmbk = 3755, + X86_VCVTPD2UDQZ128rmbkz = 3756, + X86_VCVTPD2UDQZ128rmk = 3757, + X86_VCVTPD2UDQZ128rmkz = 3758, + X86_VCVTPD2UDQZ128rr = 3759, + X86_VCVTPD2UDQZ128rrk = 3760, + X86_VCVTPD2UDQZ128rrkz = 3761, + X86_VCVTPD2UDQZ256rm = 3762, + X86_VCVTPD2UDQZ256rmb = 3763, + X86_VCVTPD2UDQZ256rmbk = 3764, + X86_VCVTPD2UDQZ256rmbkz = 3765, + X86_VCVTPD2UDQZ256rmk = 3766, + X86_VCVTPD2UDQZ256rmkz = 3767, + X86_VCVTPD2UDQZ256rr = 3768, + X86_VCVTPD2UDQZ256rrk = 3769, + X86_VCVTPD2UDQZ256rrkz = 3770, + X86_VCVTPD2UDQZrm = 3771, + X86_VCVTPD2UDQZrmb = 3772, + X86_VCVTPD2UDQZrmbk = 3773, + X86_VCVTPD2UDQZrmbkz = 3774, + X86_VCVTPD2UDQZrmk = 3775, + X86_VCVTPD2UDQZrmkz = 3776, + X86_VCVTPD2UDQZrr = 3777, + X86_VCVTPD2UDQZrrb = 3778, + X86_VCVTPD2UDQZrrbk = 3779, + X86_VCVTPD2UDQZrrbkz = 3780, + X86_VCVTPD2UDQZrrk = 3781, + X86_VCVTPD2UDQZrrkz = 3782, + X86_VCVTPD2UQQZ128rm = 3783, + X86_VCVTPD2UQQZ128rmb = 3784, + X86_VCVTPD2UQQZ128rmbk = 3785, + X86_VCVTPD2UQQZ128rmbkz = 3786, + X86_VCVTPD2UQQZ128rmk = 3787, + X86_VCVTPD2UQQZ128rmkz = 3788, + X86_VCVTPD2UQQZ128rr = 3789, + X86_VCVTPD2UQQZ128rrk = 3790, + X86_VCVTPD2UQQZ128rrkz = 3791, + X86_VCVTPD2UQQZ256rm = 3792, + X86_VCVTPD2UQQZ256rmb = 3793, + X86_VCVTPD2UQQZ256rmbk = 3794, + X86_VCVTPD2UQQZ256rmbkz = 3795, + X86_VCVTPD2UQQZ256rmk = 3796, + X86_VCVTPD2UQQZ256rmkz = 3797, + X86_VCVTPD2UQQZ256rr = 3798, + X86_VCVTPD2UQQZ256rrk = 3799, + X86_VCVTPD2UQQZ256rrkz = 3800, + X86_VCVTPD2UQQZrm = 3801, + X86_VCVTPD2UQQZrmb = 3802, + X86_VCVTPD2UQQZrmbk = 3803, + X86_VCVTPD2UQQZrmbkz = 3804, + X86_VCVTPD2UQQZrmk = 3805, + X86_VCVTPD2UQQZrmkz = 3806, + X86_VCVTPD2UQQZrr = 3807, + X86_VCVTPD2UQQZrrb = 3808, + X86_VCVTPD2UQQZrrbk = 3809, + X86_VCVTPD2UQQZrrbkz = 3810, + X86_VCVTPD2UQQZrrk = 3811, + X86_VCVTPD2UQQZrrkz = 3812, + X86_VCVTPH2PSYrm = 3813, + X86_VCVTPH2PSYrr = 3814, + X86_VCVTPH2PSZ128rm = 3815, + X86_VCVTPH2PSZ128rmk = 3816, + X86_VCVTPH2PSZ128rmkz = 3817, + X86_VCVTPH2PSZ128rr = 3818, + X86_VCVTPH2PSZ128rrk = 3819, + X86_VCVTPH2PSZ128rrkz = 3820, + X86_VCVTPH2PSZ256rm = 3821, + X86_VCVTPH2PSZ256rmk = 3822, + X86_VCVTPH2PSZ256rmkz = 3823, + X86_VCVTPH2PSZ256rr = 3824, + X86_VCVTPH2PSZ256rrk = 3825, + X86_VCVTPH2PSZ256rrkz = 3826, + X86_VCVTPH2PSZrm = 3827, + X86_VCVTPH2PSZrmk = 3828, + X86_VCVTPH2PSZrmkz = 3829, + X86_VCVTPH2PSZrr = 3830, + X86_VCVTPH2PSZrrb = 3831, + X86_VCVTPH2PSZrrbk = 3832, + X86_VCVTPH2PSZrrbkz = 3833, + X86_VCVTPH2PSZrrk = 3834, + X86_VCVTPH2PSZrrkz = 3835, + X86_VCVTPH2PSrm = 3836, + X86_VCVTPH2PSrr = 3837, + X86_VCVTPS2DQYrm = 3838, + X86_VCVTPS2DQYrr = 3839, + X86_VCVTPS2DQZ128rm = 3840, + X86_VCVTPS2DQZ128rmb = 3841, + X86_VCVTPS2DQZ128rmbk = 3842, + X86_VCVTPS2DQZ128rmbkz = 3843, + X86_VCVTPS2DQZ128rmk = 3844, + X86_VCVTPS2DQZ128rmkz = 3845, + X86_VCVTPS2DQZ128rr = 3846, + X86_VCVTPS2DQZ128rrk = 3847, + X86_VCVTPS2DQZ128rrkz = 3848, + X86_VCVTPS2DQZ256rm = 3849, + X86_VCVTPS2DQZ256rmb = 3850, + X86_VCVTPS2DQZ256rmbk = 3851, + X86_VCVTPS2DQZ256rmbkz = 3852, + X86_VCVTPS2DQZ256rmk = 3853, + X86_VCVTPS2DQZ256rmkz = 3854, + X86_VCVTPS2DQZ256rr = 3855, + X86_VCVTPS2DQZ256rrk = 3856, + X86_VCVTPS2DQZ256rrkz = 3857, + X86_VCVTPS2DQZrm = 3858, + X86_VCVTPS2DQZrmb = 3859, + X86_VCVTPS2DQZrmbk = 3860, + X86_VCVTPS2DQZrmbkz = 3861, + X86_VCVTPS2DQZrmk = 3862, + X86_VCVTPS2DQZrmkz = 3863, + X86_VCVTPS2DQZrr = 3864, + X86_VCVTPS2DQZrrb = 3865, + X86_VCVTPS2DQZrrbk = 3866, + X86_VCVTPS2DQZrrbkz = 3867, + X86_VCVTPS2DQZrrk = 3868, + X86_VCVTPS2DQZrrkz = 3869, + X86_VCVTPS2DQrm = 3870, + X86_VCVTPS2DQrr = 3871, + X86_VCVTPS2PDYrm = 3872, + X86_VCVTPS2PDYrr = 3873, + X86_VCVTPS2PDZ128rm = 3874, + X86_VCVTPS2PDZ128rmb = 3875, + X86_VCVTPS2PDZ128rmbk = 3876, + X86_VCVTPS2PDZ128rmbkz = 3877, + X86_VCVTPS2PDZ128rmk = 3878, + X86_VCVTPS2PDZ128rmkz = 3879, + X86_VCVTPS2PDZ128rr = 3880, + X86_VCVTPS2PDZ128rrk = 3881, + X86_VCVTPS2PDZ128rrkz = 3882, + X86_VCVTPS2PDZ256rm = 3883, + X86_VCVTPS2PDZ256rmb = 3884, + X86_VCVTPS2PDZ256rmbk = 3885, + X86_VCVTPS2PDZ256rmbkz = 3886, + X86_VCVTPS2PDZ256rmk = 3887, + X86_VCVTPS2PDZ256rmkz = 3888, + X86_VCVTPS2PDZ256rr = 3889, + X86_VCVTPS2PDZ256rrk = 3890, + X86_VCVTPS2PDZ256rrkz = 3891, + X86_VCVTPS2PDZrm = 3892, + X86_VCVTPS2PDZrmb = 3893, + X86_VCVTPS2PDZrmbk = 3894, + X86_VCVTPS2PDZrmbkz = 3895, + X86_VCVTPS2PDZrmk = 3896, + X86_VCVTPS2PDZrmkz = 3897, + X86_VCVTPS2PDZrr = 3898, + X86_VCVTPS2PDZrrb = 3899, + X86_VCVTPS2PDZrrbk = 3900, + X86_VCVTPS2PDZrrbkz = 3901, + X86_VCVTPS2PDZrrk = 3902, + X86_VCVTPS2PDZrrkz = 3903, + X86_VCVTPS2PDrm = 3904, + X86_VCVTPS2PDrr = 3905, + X86_VCVTPS2PHYmr = 3906, + X86_VCVTPS2PHYrr = 3907, + X86_VCVTPS2PHZ128mr = 3908, + X86_VCVTPS2PHZ128mrk = 3909, + X86_VCVTPS2PHZ128rr = 3910, + X86_VCVTPS2PHZ128rrk = 3911, + X86_VCVTPS2PHZ128rrkz = 3912, + X86_VCVTPS2PHZ256mr = 3913, + X86_VCVTPS2PHZ256mrk = 3914, + X86_VCVTPS2PHZ256rr = 3915, + X86_VCVTPS2PHZ256rrk = 3916, + X86_VCVTPS2PHZ256rrkz = 3917, + X86_VCVTPS2PHZmr = 3918, + X86_VCVTPS2PHZmrk = 3919, + X86_VCVTPS2PHZrr = 3920, + X86_VCVTPS2PHZrrb = 3921, + X86_VCVTPS2PHZrrbk = 3922, + X86_VCVTPS2PHZrrbkz = 3923, + X86_VCVTPS2PHZrrk = 3924, + X86_VCVTPS2PHZrrkz = 3925, + X86_VCVTPS2PHmr = 3926, + X86_VCVTPS2PHrr = 3927, + X86_VCVTPS2QQZ128rm = 3928, + X86_VCVTPS2QQZ128rmb = 3929, + X86_VCVTPS2QQZ128rmbk = 3930, + X86_VCVTPS2QQZ128rmbkz = 3931, + X86_VCVTPS2QQZ128rmk = 3932, + X86_VCVTPS2QQZ128rmkz = 3933, + X86_VCVTPS2QQZ128rr = 3934, + X86_VCVTPS2QQZ128rrk = 3935, + X86_VCVTPS2QQZ128rrkz = 3936, + X86_VCVTPS2QQZ256rm = 3937, + X86_VCVTPS2QQZ256rmb = 3938, + X86_VCVTPS2QQZ256rmbk = 3939, + X86_VCVTPS2QQZ256rmbkz = 3940, + X86_VCVTPS2QQZ256rmk = 3941, + X86_VCVTPS2QQZ256rmkz = 3942, + X86_VCVTPS2QQZ256rr = 3943, + X86_VCVTPS2QQZ256rrk = 3944, + X86_VCVTPS2QQZ256rrkz = 3945, + X86_VCVTPS2QQZrm = 3946, + X86_VCVTPS2QQZrmb = 3947, + X86_VCVTPS2QQZrmbk = 3948, + X86_VCVTPS2QQZrmbkz = 3949, + X86_VCVTPS2QQZrmk = 3950, + X86_VCVTPS2QQZrmkz = 3951, + X86_VCVTPS2QQZrr = 3952, + X86_VCVTPS2QQZrrb = 3953, + X86_VCVTPS2QQZrrbk = 3954, + X86_VCVTPS2QQZrrbkz = 3955, + X86_VCVTPS2QQZrrk = 3956, + X86_VCVTPS2QQZrrkz = 3957, + X86_VCVTPS2UDQZ128rm = 3958, + X86_VCVTPS2UDQZ128rmb = 3959, + X86_VCVTPS2UDQZ128rmbk = 3960, + X86_VCVTPS2UDQZ128rmbkz = 3961, + X86_VCVTPS2UDQZ128rmk = 3962, + X86_VCVTPS2UDQZ128rmkz = 3963, + X86_VCVTPS2UDQZ128rr = 3964, + X86_VCVTPS2UDQZ128rrk = 3965, + X86_VCVTPS2UDQZ128rrkz = 3966, + X86_VCVTPS2UDQZ256rm = 3967, + X86_VCVTPS2UDQZ256rmb = 3968, + X86_VCVTPS2UDQZ256rmbk = 3969, + X86_VCVTPS2UDQZ256rmbkz = 3970, + X86_VCVTPS2UDQZ256rmk = 3971, + X86_VCVTPS2UDQZ256rmkz = 3972, + X86_VCVTPS2UDQZ256rr = 3973, + X86_VCVTPS2UDQZ256rrk = 3974, + X86_VCVTPS2UDQZ256rrkz = 3975, + X86_VCVTPS2UDQZrm = 3976, + X86_VCVTPS2UDQZrmb = 3977, + X86_VCVTPS2UDQZrmbk = 3978, + X86_VCVTPS2UDQZrmbkz = 3979, + X86_VCVTPS2UDQZrmk = 3980, + X86_VCVTPS2UDQZrmkz = 3981, + X86_VCVTPS2UDQZrr = 3982, + X86_VCVTPS2UDQZrrb = 3983, + X86_VCVTPS2UDQZrrbk = 3984, + X86_VCVTPS2UDQZrrbkz = 3985, + X86_VCVTPS2UDQZrrk = 3986, + X86_VCVTPS2UDQZrrkz = 3987, + X86_VCVTPS2UQQZ128rm = 3988, + X86_VCVTPS2UQQZ128rmb = 3989, + X86_VCVTPS2UQQZ128rmbk = 3990, + X86_VCVTPS2UQQZ128rmbkz = 3991, + X86_VCVTPS2UQQZ128rmk = 3992, + X86_VCVTPS2UQQZ128rmkz = 3993, + X86_VCVTPS2UQQZ128rr = 3994, + X86_VCVTPS2UQQZ128rrk = 3995, + X86_VCVTPS2UQQZ128rrkz = 3996, + X86_VCVTPS2UQQZ256rm = 3997, + X86_VCVTPS2UQQZ256rmb = 3998, + X86_VCVTPS2UQQZ256rmbk = 3999, + X86_VCVTPS2UQQZ256rmbkz = 4000, + X86_VCVTPS2UQQZ256rmk = 4001, + X86_VCVTPS2UQQZ256rmkz = 4002, + X86_VCVTPS2UQQZ256rr = 4003, + X86_VCVTPS2UQQZ256rrk = 4004, + X86_VCVTPS2UQQZ256rrkz = 4005, + X86_VCVTPS2UQQZrm = 4006, + X86_VCVTPS2UQQZrmb = 4007, + X86_VCVTPS2UQQZrmbk = 4008, + X86_VCVTPS2UQQZrmbkz = 4009, + X86_VCVTPS2UQQZrmk = 4010, + X86_VCVTPS2UQQZrmkz = 4011, + X86_VCVTPS2UQQZrr = 4012, + X86_VCVTPS2UQQZrrb = 4013, + X86_VCVTPS2UQQZrrbk = 4014, + X86_VCVTPS2UQQZrrbkz = 4015, + X86_VCVTPS2UQQZrrk = 4016, + X86_VCVTPS2UQQZrrkz = 4017, + X86_VCVTQQ2PDZ128rm = 4018, + X86_VCVTQQ2PDZ128rmb = 4019, + X86_VCVTQQ2PDZ128rmbk = 4020, + X86_VCVTQQ2PDZ128rmbkz = 4021, + X86_VCVTQQ2PDZ128rmk = 4022, + X86_VCVTQQ2PDZ128rmkz = 4023, + X86_VCVTQQ2PDZ128rr = 4024, + X86_VCVTQQ2PDZ128rrk = 4025, + X86_VCVTQQ2PDZ128rrkz = 4026, + X86_VCVTQQ2PDZ256rm = 4027, + X86_VCVTQQ2PDZ256rmb = 4028, + X86_VCVTQQ2PDZ256rmbk = 4029, + X86_VCVTQQ2PDZ256rmbkz = 4030, + X86_VCVTQQ2PDZ256rmk = 4031, + X86_VCVTQQ2PDZ256rmkz = 4032, + X86_VCVTQQ2PDZ256rr = 4033, + X86_VCVTQQ2PDZ256rrk = 4034, + X86_VCVTQQ2PDZ256rrkz = 4035, + X86_VCVTQQ2PDZrm = 4036, + X86_VCVTQQ2PDZrmb = 4037, + X86_VCVTQQ2PDZrmbk = 4038, + X86_VCVTQQ2PDZrmbkz = 4039, + X86_VCVTQQ2PDZrmk = 4040, + X86_VCVTQQ2PDZrmkz = 4041, + X86_VCVTQQ2PDZrr = 4042, + X86_VCVTQQ2PDZrrb = 4043, + X86_VCVTQQ2PDZrrbk = 4044, + X86_VCVTQQ2PDZrrbkz = 4045, + X86_VCVTQQ2PDZrrk = 4046, + X86_VCVTQQ2PDZrrkz = 4047, + X86_VCVTQQ2PSZ128rm = 4048, + X86_VCVTQQ2PSZ128rmb = 4049, + X86_VCVTQQ2PSZ128rmbk = 4050, + X86_VCVTQQ2PSZ128rmbkz = 4051, + X86_VCVTQQ2PSZ128rmk = 4052, + X86_VCVTQQ2PSZ128rmkz = 4053, + X86_VCVTQQ2PSZ128rr = 4054, + X86_VCVTQQ2PSZ128rrk = 4055, + X86_VCVTQQ2PSZ128rrkz = 4056, + X86_VCVTQQ2PSZ256rm = 4057, + X86_VCVTQQ2PSZ256rmb = 4058, + X86_VCVTQQ2PSZ256rmbk = 4059, + X86_VCVTQQ2PSZ256rmbkz = 4060, + X86_VCVTQQ2PSZ256rmk = 4061, + X86_VCVTQQ2PSZ256rmkz = 4062, + X86_VCVTQQ2PSZ256rr = 4063, + X86_VCVTQQ2PSZ256rrk = 4064, + X86_VCVTQQ2PSZ256rrkz = 4065, + X86_VCVTQQ2PSZrm = 4066, + X86_VCVTQQ2PSZrmb = 4067, + X86_VCVTQQ2PSZrmbk = 4068, + X86_VCVTQQ2PSZrmbkz = 4069, + X86_VCVTQQ2PSZrmk = 4070, + X86_VCVTQQ2PSZrmkz = 4071, + X86_VCVTQQ2PSZrr = 4072, + X86_VCVTQQ2PSZrrb = 4073, + X86_VCVTQQ2PSZrrbk = 4074, + X86_VCVTQQ2PSZrrbkz = 4075, + X86_VCVTQQ2PSZrrk = 4076, + X86_VCVTQQ2PSZrrkz = 4077, + X86_VCVTSD2SI64Zrm_Int = 4078, + X86_VCVTSD2SI64Zrr_Int = 4079, + X86_VCVTSD2SI64Zrrb_Int = 4080, + X86_VCVTSD2SI64rm_Int = 4081, + X86_VCVTSD2SI64rr_Int = 4082, + X86_VCVTSD2SIZrm_Int = 4083, + X86_VCVTSD2SIZrr_Int = 4084, + X86_VCVTSD2SIZrrb_Int = 4085, + X86_VCVTSD2SIrm_Int = 4086, + X86_VCVTSD2SIrr_Int = 4087, + X86_VCVTSD2SSZrm = 4088, + X86_VCVTSD2SSZrm_Int = 4089, + X86_VCVTSD2SSZrm_Intk = 4090, + X86_VCVTSD2SSZrm_Intkz = 4091, + X86_VCVTSD2SSZrr = 4092, + X86_VCVTSD2SSZrr_Int = 4093, + X86_VCVTSD2SSZrr_Intk = 4094, + X86_VCVTSD2SSZrr_Intkz = 4095, + X86_VCVTSD2SSZrrb_Int = 4096, + X86_VCVTSD2SSZrrb_Intk = 4097, + X86_VCVTSD2SSZrrb_Intkz = 4098, + X86_VCVTSD2SSrm = 4099, + X86_VCVTSD2SSrm_Int = 4100, + X86_VCVTSD2SSrr = 4101, + X86_VCVTSD2SSrr_Int = 4102, + X86_VCVTSD2USI64Zrm_Int = 4103, + X86_VCVTSD2USI64Zrr_Int = 4104, + X86_VCVTSD2USI64Zrrb_Int = 4105, + X86_VCVTSD2USIZrm_Int = 4106, + X86_VCVTSD2USIZrr_Int = 4107, + X86_VCVTSD2USIZrrb_Int = 4108, + X86_VCVTSI2SDZrm = 4109, + X86_VCVTSI2SDZrm_Int = 4110, + X86_VCVTSI2SDZrr = 4111, + X86_VCVTSI2SDZrr_Int = 4112, + X86_VCVTSI2SDZrrb_Int = 4113, + X86_VCVTSI2SDrm = 4114, + X86_VCVTSI2SDrm_Int = 4115, + X86_VCVTSI2SDrr = 4116, + X86_VCVTSI2SDrr_Int = 4117, + X86_VCVTSI2SSZrm = 4118, + X86_VCVTSI2SSZrm_Int = 4119, + X86_VCVTSI2SSZrr = 4120, + X86_VCVTSI2SSZrr_Int = 4121, + X86_VCVTSI2SSZrrb_Int = 4122, + X86_VCVTSI2SSrm = 4123, + X86_VCVTSI2SSrm_Int = 4124, + X86_VCVTSI2SSrr = 4125, + X86_VCVTSI2SSrr_Int = 4126, + X86_VCVTSI642SDZrm = 4127, + X86_VCVTSI642SDZrm_Int = 4128, + X86_VCVTSI642SDZrr = 4129, + X86_VCVTSI642SDZrr_Int = 4130, + X86_VCVTSI642SDZrrb_Int = 4131, + X86_VCVTSI642SDrm = 4132, + X86_VCVTSI642SDrm_Int = 4133, + X86_VCVTSI642SDrr = 4134, + X86_VCVTSI642SDrr_Int = 4135, + X86_VCVTSI642SSZrm = 4136, + X86_VCVTSI642SSZrm_Int = 4137, + X86_VCVTSI642SSZrr = 4138, + X86_VCVTSI642SSZrr_Int = 4139, + X86_VCVTSI642SSZrrb_Int = 4140, + X86_VCVTSI642SSrm = 4141, + X86_VCVTSI642SSrm_Int = 4142, + X86_VCVTSI642SSrr = 4143, + X86_VCVTSI642SSrr_Int = 4144, + X86_VCVTSS2SDZrm = 4145, + X86_VCVTSS2SDZrm_Int = 4146, + X86_VCVTSS2SDZrm_Intk = 4147, + X86_VCVTSS2SDZrm_Intkz = 4148, + X86_VCVTSS2SDZrr = 4149, + X86_VCVTSS2SDZrr_Int = 4150, + X86_VCVTSS2SDZrr_Intk = 4151, + X86_VCVTSS2SDZrr_Intkz = 4152, + X86_VCVTSS2SDZrrb_Int = 4153, + X86_VCVTSS2SDZrrb_Intk = 4154, + X86_VCVTSS2SDZrrb_Intkz = 4155, + X86_VCVTSS2SDrm = 4156, + X86_VCVTSS2SDrm_Int = 4157, + X86_VCVTSS2SDrr = 4158, + X86_VCVTSS2SDrr_Int = 4159, + X86_VCVTSS2SI64Zrm_Int = 4160, + X86_VCVTSS2SI64Zrr_Int = 4161, + X86_VCVTSS2SI64Zrrb_Int = 4162, + X86_VCVTSS2SI64rm_Int = 4163, + X86_VCVTSS2SI64rr_Int = 4164, + X86_VCVTSS2SIZrm_Int = 4165, + X86_VCVTSS2SIZrr_Int = 4166, + X86_VCVTSS2SIZrrb_Int = 4167, + X86_VCVTSS2SIrm_Int = 4168, + X86_VCVTSS2SIrr_Int = 4169, + X86_VCVTSS2USI64Zrm_Int = 4170, + X86_VCVTSS2USI64Zrr_Int = 4171, + X86_VCVTSS2USI64Zrrb_Int = 4172, + X86_VCVTSS2USIZrm_Int = 4173, + X86_VCVTSS2USIZrr_Int = 4174, + X86_VCVTSS2USIZrrb_Int = 4175, + X86_VCVTTPD2DQYrm = 4176, + X86_VCVTTPD2DQYrr = 4177, + X86_VCVTTPD2DQZ128rm = 4178, + X86_VCVTTPD2DQZ128rmb = 4179, + X86_VCVTTPD2DQZ128rmbk = 4180, + X86_VCVTTPD2DQZ128rmbkz = 4181, + X86_VCVTTPD2DQZ128rmk = 4182, + X86_VCVTTPD2DQZ128rmkz = 4183, + X86_VCVTTPD2DQZ128rr = 4184, + X86_VCVTTPD2DQZ128rrk = 4185, + X86_VCVTTPD2DQZ128rrkz = 4186, + X86_VCVTTPD2DQZ256rm = 4187, + X86_VCVTTPD2DQZ256rmb = 4188, + X86_VCVTTPD2DQZ256rmbk = 4189, + X86_VCVTTPD2DQZ256rmbkz = 4190, + X86_VCVTTPD2DQZ256rmk = 4191, + X86_VCVTTPD2DQZ256rmkz = 4192, + X86_VCVTTPD2DQZ256rr = 4193, + X86_VCVTTPD2DQZ256rrk = 4194, + X86_VCVTTPD2DQZ256rrkz = 4195, + X86_VCVTTPD2DQZrm = 4196, + X86_VCVTTPD2DQZrmb = 4197, + X86_VCVTTPD2DQZrmbk = 4198, + X86_VCVTTPD2DQZrmbkz = 4199, + X86_VCVTTPD2DQZrmk = 4200, + X86_VCVTTPD2DQZrmkz = 4201, + X86_VCVTTPD2DQZrr = 4202, + X86_VCVTTPD2DQZrrb = 4203, + X86_VCVTTPD2DQZrrbk = 4204, + X86_VCVTTPD2DQZrrbkz = 4205, + X86_VCVTTPD2DQZrrk = 4206, + X86_VCVTTPD2DQZrrkz = 4207, + X86_VCVTTPD2DQrm = 4208, + X86_VCVTTPD2DQrr = 4209, + X86_VCVTTPD2QQZ128rm = 4210, + X86_VCVTTPD2QQZ128rmb = 4211, + X86_VCVTTPD2QQZ128rmbk = 4212, + X86_VCVTTPD2QQZ128rmbkz = 4213, + X86_VCVTTPD2QQZ128rmk = 4214, + X86_VCVTTPD2QQZ128rmkz = 4215, + X86_VCVTTPD2QQZ128rr = 4216, + X86_VCVTTPD2QQZ128rrk = 4217, + X86_VCVTTPD2QQZ128rrkz = 4218, + X86_VCVTTPD2QQZ256rm = 4219, + X86_VCVTTPD2QQZ256rmb = 4220, + X86_VCVTTPD2QQZ256rmbk = 4221, + X86_VCVTTPD2QQZ256rmbkz = 4222, + X86_VCVTTPD2QQZ256rmk = 4223, + X86_VCVTTPD2QQZ256rmkz = 4224, + X86_VCVTTPD2QQZ256rr = 4225, + X86_VCVTTPD2QQZ256rrk = 4226, + X86_VCVTTPD2QQZ256rrkz = 4227, + X86_VCVTTPD2QQZrm = 4228, + X86_VCVTTPD2QQZrmb = 4229, + X86_VCVTTPD2QQZrmbk = 4230, + X86_VCVTTPD2QQZrmbkz = 4231, + X86_VCVTTPD2QQZrmk = 4232, + X86_VCVTTPD2QQZrmkz = 4233, + X86_VCVTTPD2QQZrr = 4234, + X86_VCVTTPD2QQZrrb = 4235, + X86_VCVTTPD2QQZrrbk = 4236, + X86_VCVTTPD2QQZrrbkz = 4237, + X86_VCVTTPD2QQZrrk = 4238, + X86_VCVTTPD2QQZrrkz = 4239, + X86_VCVTTPD2UDQZ128rm = 4240, + X86_VCVTTPD2UDQZ128rmb = 4241, + X86_VCVTTPD2UDQZ128rmbk = 4242, + X86_VCVTTPD2UDQZ128rmbkz = 4243, + X86_VCVTTPD2UDQZ128rmk = 4244, + X86_VCVTTPD2UDQZ128rmkz = 4245, + X86_VCVTTPD2UDQZ128rr = 4246, + X86_VCVTTPD2UDQZ128rrk = 4247, + X86_VCVTTPD2UDQZ128rrkz = 4248, + X86_VCVTTPD2UDQZ256rm = 4249, + X86_VCVTTPD2UDQZ256rmb = 4250, + X86_VCVTTPD2UDQZ256rmbk = 4251, + X86_VCVTTPD2UDQZ256rmbkz = 4252, + X86_VCVTTPD2UDQZ256rmk = 4253, + X86_VCVTTPD2UDQZ256rmkz = 4254, + X86_VCVTTPD2UDQZ256rr = 4255, + X86_VCVTTPD2UDQZ256rrk = 4256, + X86_VCVTTPD2UDQZ256rrkz = 4257, + X86_VCVTTPD2UDQZrm = 4258, + X86_VCVTTPD2UDQZrmb = 4259, + X86_VCVTTPD2UDQZrmbk = 4260, + X86_VCVTTPD2UDQZrmbkz = 4261, + X86_VCVTTPD2UDQZrmk = 4262, + X86_VCVTTPD2UDQZrmkz = 4263, + X86_VCVTTPD2UDQZrr = 4264, + X86_VCVTTPD2UDQZrrb = 4265, + X86_VCVTTPD2UDQZrrbk = 4266, + X86_VCVTTPD2UDQZrrbkz = 4267, + X86_VCVTTPD2UDQZrrk = 4268, + X86_VCVTTPD2UDQZrrkz = 4269, + X86_VCVTTPD2UQQZ128rm = 4270, + X86_VCVTTPD2UQQZ128rmb = 4271, + X86_VCVTTPD2UQQZ128rmbk = 4272, + X86_VCVTTPD2UQQZ128rmbkz = 4273, + X86_VCVTTPD2UQQZ128rmk = 4274, + X86_VCVTTPD2UQQZ128rmkz = 4275, + X86_VCVTTPD2UQQZ128rr = 4276, + X86_VCVTTPD2UQQZ128rrk = 4277, + X86_VCVTTPD2UQQZ128rrkz = 4278, + X86_VCVTTPD2UQQZ256rm = 4279, + X86_VCVTTPD2UQQZ256rmb = 4280, + X86_VCVTTPD2UQQZ256rmbk = 4281, + X86_VCVTTPD2UQQZ256rmbkz = 4282, + X86_VCVTTPD2UQQZ256rmk = 4283, + X86_VCVTTPD2UQQZ256rmkz = 4284, + X86_VCVTTPD2UQQZ256rr = 4285, + X86_VCVTTPD2UQQZ256rrk = 4286, + X86_VCVTTPD2UQQZ256rrkz = 4287, + X86_VCVTTPD2UQQZrm = 4288, + X86_VCVTTPD2UQQZrmb = 4289, + X86_VCVTTPD2UQQZrmbk = 4290, + X86_VCVTTPD2UQQZrmbkz = 4291, + X86_VCVTTPD2UQQZrmk = 4292, + X86_VCVTTPD2UQQZrmkz = 4293, + X86_VCVTTPD2UQQZrr = 4294, + X86_VCVTTPD2UQQZrrb = 4295, + X86_VCVTTPD2UQQZrrbk = 4296, + X86_VCVTTPD2UQQZrrbkz = 4297, + X86_VCVTTPD2UQQZrrk = 4298, + X86_VCVTTPD2UQQZrrkz = 4299, + X86_VCVTTPS2DQYrm = 4300, + X86_VCVTTPS2DQYrr = 4301, + X86_VCVTTPS2DQZ128rm = 4302, + X86_VCVTTPS2DQZ128rmb = 4303, + X86_VCVTTPS2DQZ128rmbk = 4304, + X86_VCVTTPS2DQZ128rmbkz = 4305, + X86_VCVTTPS2DQZ128rmk = 4306, + X86_VCVTTPS2DQZ128rmkz = 4307, + X86_VCVTTPS2DQZ128rr = 4308, + X86_VCVTTPS2DQZ128rrk = 4309, + X86_VCVTTPS2DQZ128rrkz = 4310, + X86_VCVTTPS2DQZ256rm = 4311, + X86_VCVTTPS2DQZ256rmb = 4312, + X86_VCVTTPS2DQZ256rmbk = 4313, + X86_VCVTTPS2DQZ256rmbkz = 4314, + X86_VCVTTPS2DQZ256rmk = 4315, + X86_VCVTTPS2DQZ256rmkz = 4316, + X86_VCVTTPS2DQZ256rr = 4317, + X86_VCVTTPS2DQZ256rrk = 4318, + X86_VCVTTPS2DQZ256rrkz = 4319, + X86_VCVTTPS2DQZrm = 4320, + X86_VCVTTPS2DQZrmb = 4321, + X86_VCVTTPS2DQZrmbk = 4322, + X86_VCVTTPS2DQZrmbkz = 4323, + X86_VCVTTPS2DQZrmk = 4324, + X86_VCVTTPS2DQZrmkz = 4325, + X86_VCVTTPS2DQZrr = 4326, + X86_VCVTTPS2DQZrrb = 4327, + X86_VCVTTPS2DQZrrbk = 4328, + X86_VCVTTPS2DQZrrbkz = 4329, + X86_VCVTTPS2DQZrrk = 4330, + X86_VCVTTPS2DQZrrkz = 4331, + X86_VCVTTPS2DQrm = 4332, + X86_VCVTTPS2DQrr = 4333, + X86_VCVTTPS2QQZ128rm = 4334, + X86_VCVTTPS2QQZ128rmb = 4335, + X86_VCVTTPS2QQZ128rmbk = 4336, + X86_VCVTTPS2QQZ128rmbkz = 4337, + X86_VCVTTPS2QQZ128rmk = 4338, + X86_VCVTTPS2QQZ128rmkz = 4339, + X86_VCVTTPS2QQZ128rr = 4340, + X86_VCVTTPS2QQZ128rrk = 4341, + X86_VCVTTPS2QQZ128rrkz = 4342, + X86_VCVTTPS2QQZ256rm = 4343, + X86_VCVTTPS2QQZ256rmb = 4344, + X86_VCVTTPS2QQZ256rmbk = 4345, + X86_VCVTTPS2QQZ256rmbkz = 4346, + X86_VCVTTPS2QQZ256rmk = 4347, + X86_VCVTTPS2QQZ256rmkz = 4348, + X86_VCVTTPS2QQZ256rr = 4349, + X86_VCVTTPS2QQZ256rrk = 4350, + X86_VCVTTPS2QQZ256rrkz = 4351, + X86_VCVTTPS2QQZrm = 4352, + X86_VCVTTPS2QQZrmb = 4353, + X86_VCVTTPS2QQZrmbk = 4354, + X86_VCVTTPS2QQZrmbkz = 4355, + X86_VCVTTPS2QQZrmk = 4356, + X86_VCVTTPS2QQZrmkz = 4357, + X86_VCVTTPS2QQZrr = 4358, + X86_VCVTTPS2QQZrrb = 4359, + X86_VCVTTPS2QQZrrbk = 4360, + X86_VCVTTPS2QQZrrbkz = 4361, + X86_VCVTTPS2QQZrrk = 4362, + X86_VCVTTPS2QQZrrkz = 4363, + X86_VCVTTPS2UDQZ128rm = 4364, + X86_VCVTTPS2UDQZ128rmb = 4365, + X86_VCVTTPS2UDQZ128rmbk = 4366, + X86_VCVTTPS2UDQZ128rmbkz = 4367, + X86_VCVTTPS2UDQZ128rmk = 4368, + X86_VCVTTPS2UDQZ128rmkz = 4369, + X86_VCVTTPS2UDQZ128rr = 4370, + X86_VCVTTPS2UDQZ128rrk = 4371, + X86_VCVTTPS2UDQZ128rrkz = 4372, + X86_VCVTTPS2UDQZ256rm = 4373, + X86_VCVTTPS2UDQZ256rmb = 4374, + X86_VCVTTPS2UDQZ256rmbk = 4375, + X86_VCVTTPS2UDQZ256rmbkz = 4376, + X86_VCVTTPS2UDQZ256rmk = 4377, + X86_VCVTTPS2UDQZ256rmkz = 4378, + X86_VCVTTPS2UDQZ256rr = 4379, + X86_VCVTTPS2UDQZ256rrk = 4380, + X86_VCVTTPS2UDQZ256rrkz = 4381, + X86_VCVTTPS2UDQZrm = 4382, + X86_VCVTTPS2UDQZrmb = 4383, + X86_VCVTTPS2UDQZrmbk = 4384, + X86_VCVTTPS2UDQZrmbkz = 4385, + X86_VCVTTPS2UDQZrmk = 4386, + X86_VCVTTPS2UDQZrmkz = 4387, + X86_VCVTTPS2UDQZrr = 4388, + X86_VCVTTPS2UDQZrrb = 4389, + X86_VCVTTPS2UDQZrrbk = 4390, + X86_VCVTTPS2UDQZrrbkz = 4391, + X86_VCVTTPS2UDQZrrk = 4392, + X86_VCVTTPS2UDQZrrkz = 4393, + X86_VCVTTPS2UQQZ128rm = 4394, + X86_VCVTTPS2UQQZ128rmb = 4395, + X86_VCVTTPS2UQQZ128rmbk = 4396, + X86_VCVTTPS2UQQZ128rmbkz = 4397, + X86_VCVTTPS2UQQZ128rmk = 4398, + X86_VCVTTPS2UQQZ128rmkz = 4399, + X86_VCVTTPS2UQQZ128rr = 4400, + X86_VCVTTPS2UQQZ128rrk = 4401, + X86_VCVTTPS2UQQZ128rrkz = 4402, + X86_VCVTTPS2UQQZ256rm = 4403, + X86_VCVTTPS2UQQZ256rmb = 4404, + X86_VCVTTPS2UQQZ256rmbk = 4405, + X86_VCVTTPS2UQQZ256rmbkz = 4406, + X86_VCVTTPS2UQQZ256rmk = 4407, + X86_VCVTTPS2UQQZ256rmkz = 4408, + X86_VCVTTPS2UQQZ256rr = 4409, + X86_VCVTTPS2UQQZ256rrk = 4410, + X86_VCVTTPS2UQQZ256rrkz = 4411, + X86_VCVTTPS2UQQZrm = 4412, + X86_VCVTTPS2UQQZrmb = 4413, + X86_VCVTTPS2UQQZrmbk = 4414, + X86_VCVTTPS2UQQZrmbkz = 4415, + X86_VCVTTPS2UQQZrmk = 4416, + X86_VCVTTPS2UQQZrmkz = 4417, + X86_VCVTTPS2UQQZrr = 4418, + X86_VCVTTPS2UQQZrrb = 4419, + X86_VCVTTPS2UQQZrrbk = 4420, + X86_VCVTTPS2UQQZrrbkz = 4421, + X86_VCVTTPS2UQQZrrk = 4422, + X86_VCVTTPS2UQQZrrkz = 4423, + X86_VCVTTSD2SI64Zrm = 4424, + X86_VCVTTSD2SI64Zrm_Int = 4425, + X86_VCVTTSD2SI64Zrr = 4426, + X86_VCVTTSD2SI64Zrr_Int = 4427, + X86_VCVTTSD2SI64Zrrb_Int = 4428, + X86_VCVTTSD2SI64rm = 4429, + X86_VCVTTSD2SI64rm_Int = 4430, + X86_VCVTTSD2SI64rr = 4431, + X86_VCVTTSD2SI64rr_Int = 4432, + X86_VCVTTSD2SIZrm = 4433, + X86_VCVTTSD2SIZrm_Int = 4434, + X86_VCVTTSD2SIZrr = 4435, + X86_VCVTTSD2SIZrr_Int = 4436, + X86_VCVTTSD2SIZrrb_Int = 4437, + X86_VCVTTSD2SIrm = 4438, + X86_VCVTTSD2SIrm_Int = 4439, + X86_VCVTTSD2SIrr = 4440, + X86_VCVTTSD2SIrr_Int = 4441, + X86_VCVTTSD2USI64Zrm = 4442, + X86_VCVTTSD2USI64Zrm_Int = 4443, + X86_VCVTTSD2USI64Zrr = 4444, + X86_VCVTTSD2USI64Zrr_Int = 4445, + X86_VCVTTSD2USI64Zrrb_Int = 4446, + X86_VCVTTSD2USIZrm = 4447, + X86_VCVTTSD2USIZrm_Int = 4448, + X86_VCVTTSD2USIZrr = 4449, + X86_VCVTTSD2USIZrr_Int = 4450, + X86_VCVTTSD2USIZrrb_Int = 4451, + X86_VCVTTSS2SI64Zrm = 4452, + X86_VCVTTSS2SI64Zrm_Int = 4453, + X86_VCVTTSS2SI64Zrr = 4454, + X86_VCVTTSS2SI64Zrr_Int = 4455, + X86_VCVTTSS2SI64Zrrb_Int = 4456, + X86_VCVTTSS2SI64rm = 4457, + X86_VCVTTSS2SI64rm_Int = 4458, + X86_VCVTTSS2SI64rr = 4459, + X86_VCVTTSS2SI64rr_Int = 4460, + X86_VCVTTSS2SIZrm = 4461, + X86_VCVTTSS2SIZrm_Int = 4462, + X86_VCVTTSS2SIZrr = 4463, + X86_VCVTTSS2SIZrr_Int = 4464, + X86_VCVTTSS2SIZrrb_Int = 4465, + X86_VCVTTSS2SIrm = 4466, + X86_VCVTTSS2SIrm_Int = 4467, + X86_VCVTTSS2SIrr = 4468, + X86_VCVTTSS2SIrr_Int = 4469, + X86_VCVTTSS2USI64Zrm = 4470, + X86_VCVTTSS2USI64Zrm_Int = 4471, + X86_VCVTTSS2USI64Zrr = 4472, + X86_VCVTTSS2USI64Zrr_Int = 4473, + X86_VCVTTSS2USI64Zrrb_Int = 4474, + X86_VCVTTSS2USIZrm = 4475, + X86_VCVTTSS2USIZrm_Int = 4476, + X86_VCVTTSS2USIZrr = 4477, + X86_VCVTTSS2USIZrr_Int = 4478, + X86_VCVTTSS2USIZrrb_Int = 4479, + X86_VCVTUDQ2PDZ128rm = 4480, + X86_VCVTUDQ2PDZ128rmb = 4481, + X86_VCVTUDQ2PDZ128rmbk = 4482, + X86_VCVTUDQ2PDZ128rmbkz = 4483, + X86_VCVTUDQ2PDZ128rmk = 4484, + X86_VCVTUDQ2PDZ128rmkz = 4485, + X86_VCVTUDQ2PDZ128rr = 4486, + X86_VCVTUDQ2PDZ128rrk = 4487, + X86_VCVTUDQ2PDZ128rrkz = 4488, + X86_VCVTUDQ2PDZ256rm = 4489, + X86_VCVTUDQ2PDZ256rmb = 4490, + X86_VCVTUDQ2PDZ256rmbk = 4491, + X86_VCVTUDQ2PDZ256rmbkz = 4492, + X86_VCVTUDQ2PDZ256rmk = 4493, + X86_VCVTUDQ2PDZ256rmkz = 4494, + X86_VCVTUDQ2PDZ256rr = 4495, + X86_VCVTUDQ2PDZ256rrk = 4496, + X86_VCVTUDQ2PDZ256rrkz = 4497, + X86_VCVTUDQ2PDZrm = 4498, + X86_VCVTUDQ2PDZrmb = 4499, + X86_VCVTUDQ2PDZrmbk = 4500, + X86_VCVTUDQ2PDZrmbkz = 4501, + X86_VCVTUDQ2PDZrmk = 4502, + X86_VCVTUDQ2PDZrmkz = 4503, + X86_VCVTUDQ2PDZrr = 4504, + X86_VCVTUDQ2PDZrrk = 4505, + X86_VCVTUDQ2PDZrrkz = 4506, + X86_VCVTUDQ2PSZ128rm = 4507, + X86_VCVTUDQ2PSZ128rmb = 4508, + X86_VCVTUDQ2PSZ128rmbk = 4509, + X86_VCVTUDQ2PSZ128rmbkz = 4510, + X86_VCVTUDQ2PSZ128rmk = 4511, + X86_VCVTUDQ2PSZ128rmkz = 4512, + X86_VCVTUDQ2PSZ128rr = 4513, + X86_VCVTUDQ2PSZ128rrk = 4514, + X86_VCVTUDQ2PSZ128rrkz = 4515, + X86_VCVTUDQ2PSZ256rm = 4516, + X86_VCVTUDQ2PSZ256rmb = 4517, + X86_VCVTUDQ2PSZ256rmbk = 4518, + X86_VCVTUDQ2PSZ256rmbkz = 4519, + X86_VCVTUDQ2PSZ256rmk = 4520, + X86_VCVTUDQ2PSZ256rmkz = 4521, + X86_VCVTUDQ2PSZ256rr = 4522, + X86_VCVTUDQ2PSZ256rrk = 4523, + X86_VCVTUDQ2PSZ256rrkz = 4524, + X86_VCVTUDQ2PSZrm = 4525, + X86_VCVTUDQ2PSZrmb = 4526, + X86_VCVTUDQ2PSZrmbk = 4527, + X86_VCVTUDQ2PSZrmbkz = 4528, + X86_VCVTUDQ2PSZrmk = 4529, + X86_VCVTUDQ2PSZrmkz = 4530, + X86_VCVTUDQ2PSZrr = 4531, + X86_VCVTUDQ2PSZrrb = 4532, + X86_VCVTUDQ2PSZrrbk = 4533, + X86_VCVTUDQ2PSZrrbkz = 4534, + X86_VCVTUDQ2PSZrrk = 4535, + X86_VCVTUDQ2PSZrrkz = 4536, + X86_VCVTUQQ2PDZ128rm = 4537, + X86_VCVTUQQ2PDZ128rmb = 4538, + X86_VCVTUQQ2PDZ128rmbk = 4539, + X86_VCVTUQQ2PDZ128rmbkz = 4540, + X86_VCVTUQQ2PDZ128rmk = 4541, + X86_VCVTUQQ2PDZ128rmkz = 4542, + X86_VCVTUQQ2PDZ128rr = 4543, + X86_VCVTUQQ2PDZ128rrk = 4544, + X86_VCVTUQQ2PDZ128rrkz = 4545, + X86_VCVTUQQ2PDZ256rm = 4546, + X86_VCVTUQQ2PDZ256rmb = 4547, + X86_VCVTUQQ2PDZ256rmbk = 4548, + X86_VCVTUQQ2PDZ256rmbkz = 4549, + X86_VCVTUQQ2PDZ256rmk = 4550, + X86_VCVTUQQ2PDZ256rmkz = 4551, + X86_VCVTUQQ2PDZ256rr = 4552, + X86_VCVTUQQ2PDZ256rrk = 4553, + X86_VCVTUQQ2PDZ256rrkz = 4554, + X86_VCVTUQQ2PDZrm = 4555, + X86_VCVTUQQ2PDZrmb = 4556, + X86_VCVTUQQ2PDZrmbk = 4557, + X86_VCVTUQQ2PDZrmbkz = 4558, + X86_VCVTUQQ2PDZrmk = 4559, + X86_VCVTUQQ2PDZrmkz = 4560, + X86_VCVTUQQ2PDZrr = 4561, + X86_VCVTUQQ2PDZrrb = 4562, + X86_VCVTUQQ2PDZrrbk = 4563, + X86_VCVTUQQ2PDZrrbkz = 4564, + X86_VCVTUQQ2PDZrrk = 4565, + X86_VCVTUQQ2PDZrrkz = 4566, + X86_VCVTUQQ2PSZ128rm = 4567, + X86_VCVTUQQ2PSZ128rmb = 4568, + X86_VCVTUQQ2PSZ128rmbk = 4569, + X86_VCVTUQQ2PSZ128rmbkz = 4570, + X86_VCVTUQQ2PSZ128rmk = 4571, + X86_VCVTUQQ2PSZ128rmkz = 4572, + X86_VCVTUQQ2PSZ128rr = 4573, + X86_VCVTUQQ2PSZ128rrk = 4574, + X86_VCVTUQQ2PSZ128rrkz = 4575, + X86_VCVTUQQ2PSZ256rm = 4576, + X86_VCVTUQQ2PSZ256rmb = 4577, + X86_VCVTUQQ2PSZ256rmbk = 4578, + X86_VCVTUQQ2PSZ256rmbkz = 4579, + X86_VCVTUQQ2PSZ256rmk = 4580, + X86_VCVTUQQ2PSZ256rmkz = 4581, + X86_VCVTUQQ2PSZ256rr = 4582, + X86_VCVTUQQ2PSZ256rrk = 4583, + X86_VCVTUQQ2PSZ256rrkz = 4584, + X86_VCVTUQQ2PSZrm = 4585, + X86_VCVTUQQ2PSZrmb = 4586, + X86_VCVTUQQ2PSZrmbk = 4587, + X86_VCVTUQQ2PSZrmbkz = 4588, + X86_VCVTUQQ2PSZrmk = 4589, + X86_VCVTUQQ2PSZrmkz = 4590, + X86_VCVTUQQ2PSZrr = 4591, + X86_VCVTUQQ2PSZrrb = 4592, + X86_VCVTUQQ2PSZrrbk = 4593, + X86_VCVTUQQ2PSZrrbkz = 4594, + X86_VCVTUQQ2PSZrrk = 4595, + X86_VCVTUQQ2PSZrrkz = 4596, + X86_VCVTUSI2SDZrm = 4597, + X86_VCVTUSI2SDZrm_Int = 4598, + X86_VCVTUSI2SDZrr = 4599, + X86_VCVTUSI2SDZrr_Int = 4600, + X86_VCVTUSI2SSZrm = 4601, + X86_VCVTUSI2SSZrm_Int = 4602, + X86_VCVTUSI2SSZrr = 4603, + X86_VCVTUSI2SSZrr_Int = 4604, + X86_VCVTUSI2SSZrrb_Int = 4605, + X86_VCVTUSI642SDZrm = 4606, + X86_VCVTUSI642SDZrm_Int = 4607, + X86_VCVTUSI642SDZrr = 4608, + X86_VCVTUSI642SDZrr_Int = 4609, + X86_VCVTUSI642SDZrrb_Int = 4610, + X86_VCVTUSI642SSZrm = 4611, + X86_VCVTUSI642SSZrm_Int = 4612, + X86_VCVTUSI642SSZrr = 4613, + X86_VCVTUSI642SSZrr_Int = 4614, + X86_VCVTUSI642SSZrrb_Int = 4615, + X86_VDBPSADBWZ128rmi = 4616, + X86_VDBPSADBWZ128rmik = 4617, + X86_VDBPSADBWZ128rmikz = 4618, + X86_VDBPSADBWZ128rri = 4619, + X86_VDBPSADBWZ128rrik = 4620, + X86_VDBPSADBWZ128rrikz = 4621, + X86_VDBPSADBWZ256rmi = 4622, + X86_VDBPSADBWZ256rmik = 4623, + X86_VDBPSADBWZ256rmikz = 4624, + X86_VDBPSADBWZ256rri = 4625, + X86_VDBPSADBWZ256rrik = 4626, + X86_VDBPSADBWZ256rrikz = 4627, + X86_VDBPSADBWZrmi = 4628, + X86_VDBPSADBWZrmik = 4629, + X86_VDBPSADBWZrmikz = 4630, + X86_VDBPSADBWZrri = 4631, + X86_VDBPSADBWZrrik = 4632, + X86_VDBPSADBWZrrikz = 4633, + X86_VDIVPDYrm = 4634, + X86_VDIVPDYrr = 4635, + X86_VDIVPDZ128rm = 4636, + X86_VDIVPDZ128rmb = 4637, + X86_VDIVPDZ128rmbk = 4638, + X86_VDIVPDZ128rmbkz = 4639, + X86_VDIVPDZ128rmk = 4640, + X86_VDIVPDZ128rmkz = 4641, + X86_VDIVPDZ128rr = 4642, + X86_VDIVPDZ128rrk = 4643, + X86_VDIVPDZ128rrkz = 4644, + X86_VDIVPDZ256rm = 4645, + X86_VDIVPDZ256rmb = 4646, + X86_VDIVPDZ256rmbk = 4647, + X86_VDIVPDZ256rmbkz = 4648, + X86_VDIVPDZ256rmk = 4649, + X86_VDIVPDZ256rmkz = 4650, + X86_VDIVPDZ256rr = 4651, + X86_VDIVPDZ256rrk = 4652, + X86_VDIVPDZ256rrkz = 4653, + X86_VDIVPDZrm = 4654, + X86_VDIVPDZrmb = 4655, + X86_VDIVPDZrmbk = 4656, + X86_VDIVPDZrmbkz = 4657, + X86_VDIVPDZrmk = 4658, + X86_VDIVPDZrmkz = 4659, + X86_VDIVPDZrr = 4660, + X86_VDIVPDZrrb = 4661, + X86_VDIVPDZrrbk = 4662, + X86_VDIVPDZrrbkz = 4663, + X86_VDIVPDZrrk = 4664, + X86_VDIVPDZrrkz = 4665, + X86_VDIVPDrm = 4666, + X86_VDIVPDrr = 4667, + X86_VDIVPSYrm = 4668, + X86_VDIVPSYrr = 4669, + X86_VDIVPSZ128rm = 4670, + X86_VDIVPSZ128rmb = 4671, + X86_VDIVPSZ128rmbk = 4672, + X86_VDIVPSZ128rmbkz = 4673, + X86_VDIVPSZ128rmk = 4674, + X86_VDIVPSZ128rmkz = 4675, + X86_VDIVPSZ128rr = 4676, + X86_VDIVPSZ128rrk = 4677, + X86_VDIVPSZ128rrkz = 4678, + X86_VDIVPSZ256rm = 4679, + X86_VDIVPSZ256rmb = 4680, + X86_VDIVPSZ256rmbk = 4681, + X86_VDIVPSZ256rmbkz = 4682, + X86_VDIVPSZ256rmk = 4683, + X86_VDIVPSZ256rmkz = 4684, + X86_VDIVPSZ256rr = 4685, + X86_VDIVPSZ256rrk = 4686, + X86_VDIVPSZ256rrkz = 4687, + X86_VDIVPSZrm = 4688, + X86_VDIVPSZrmb = 4689, + X86_VDIVPSZrmbk = 4690, + X86_VDIVPSZrmbkz = 4691, + X86_VDIVPSZrmk = 4692, + X86_VDIVPSZrmkz = 4693, + X86_VDIVPSZrr = 4694, + X86_VDIVPSZrrb = 4695, + X86_VDIVPSZrrbk = 4696, + X86_VDIVPSZrrbkz = 4697, + X86_VDIVPSZrrk = 4698, + X86_VDIVPSZrrkz = 4699, + X86_VDIVPSrm = 4700, + X86_VDIVPSrr = 4701, + X86_VDIVSDZrm = 4702, + X86_VDIVSDZrm_Int = 4703, + X86_VDIVSDZrm_Intk = 4704, + X86_VDIVSDZrm_Intkz = 4705, + X86_VDIVSDZrr = 4706, + X86_VDIVSDZrr_Int = 4707, + X86_VDIVSDZrr_Intk = 4708, + X86_VDIVSDZrr_Intkz = 4709, + X86_VDIVSDZrrb_Int = 4710, + X86_VDIVSDZrrb_Intk = 4711, + X86_VDIVSDZrrb_Intkz = 4712, + X86_VDIVSDrm = 4713, + X86_VDIVSDrm_Int = 4714, + X86_VDIVSDrr = 4715, + X86_VDIVSDrr_Int = 4716, + X86_VDIVSSZrm = 4717, + X86_VDIVSSZrm_Int = 4718, + X86_VDIVSSZrm_Intk = 4719, + X86_VDIVSSZrm_Intkz = 4720, + X86_VDIVSSZrr = 4721, + X86_VDIVSSZrr_Int = 4722, + X86_VDIVSSZrr_Intk = 4723, + X86_VDIVSSZrr_Intkz = 4724, + X86_VDIVSSZrrb_Int = 4725, + X86_VDIVSSZrrb_Intk = 4726, + X86_VDIVSSZrrb_Intkz = 4727, + X86_VDIVSSrm = 4728, + X86_VDIVSSrm_Int = 4729, + X86_VDIVSSrr = 4730, + X86_VDIVSSrr_Int = 4731, + X86_VDPPDrmi = 4732, + X86_VDPPDrri = 4733, + X86_VDPPSYrmi = 4734, + X86_VDPPSYrri = 4735, + X86_VDPPSrmi = 4736, + X86_VDPPSrri = 4737, + X86_VERRm = 4738, + X86_VERRr = 4739, + X86_VERWm = 4740, + X86_VERWr = 4741, + X86_VEXP2PDZm = 4742, + X86_VEXP2PDZmb = 4743, + X86_VEXP2PDZmbk = 4744, + X86_VEXP2PDZmbkz = 4745, + X86_VEXP2PDZmk = 4746, + X86_VEXP2PDZmkz = 4747, + X86_VEXP2PDZr = 4748, + X86_VEXP2PDZrb = 4749, + X86_VEXP2PDZrbk = 4750, + X86_VEXP2PDZrbkz = 4751, + X86_VEXP2PDZrk = 4752, + X86_VEXP2PDZrkz = 4753, + X86_VEXP2PSZm = 4754, + X86_VEXP2PSZmb = 4755, + X86_VEXP2PSZmbk = 4756, + X86_VEXP2PSZmbkz = 4757, + X86_VEXP2PSZmk = 4758, + X86_VEXP2PSZmkz = 4759, + X86_VEXP2PSZr = 4760, + X86_VEXP2PSZrb = 4761, + X86_VEXP2PSZrbk = 4762, + X86_VEXP2PSZrbkz = 4763, + X86_VEXP2PSZrk = 4764, + X86_VEXP2PSZrkz = 4765, + X86_VEXPANDPDZ128rm = 4766, + X86_VEXPANDPDZ128rmk = 4767, + X86_VEXPANDPDZ128rmkz = 4768, + X86_VEXPANDPDZ128rr = 4769, + X86_VEXPANDPDZ128rrk = 4770, + X86_VEXPANDPDZ128rrkz = 4771, + X86_VEXPANDPDZ256rm = 4772, + X86_VEXPANDPDZ256rmk = 4773, + X86_VEXPANDPDZ256rmkz = 4774, + X86_VEXPANDPDZ256rr = 4775, + X86_VEXPANDPDZ256rrk = 4776, + X86_VEXPANDPDZ256rrkz = 4777, + X86_VEXPANDPDZrm = 4778, + X86_VEXPANDPDZrmk = 4779, + X86_VEXPANDPDZrmkz = 4780, + X86_VEXPANDPDZrr = 4781, + X86_VEXPANDPDZrrk = 4782, + X86_VEXPANDPDZrrkz = 4783, + X86_VEXPANDPSZ128rm = 4784, + X86_VEXPANDPSZ128rmk = 4785, + X86_VEXPANDPSZ128rmkz = 4786, + X86_VEXPANDPSZ128rr = 4787, + X86_VEXPANDPSZ128rrk = 4788, + X86_VEXPANDPSZ128rrkz = 4789, + X86_VEXPANDPSZ256rm = 4790, + X86_VEXPANDPSZ256rmk = 4791, + X86_VEXPANDPSZ256rmkz = 4792, + X86_VEXPANDPSZ256rr = 4793, + X86_VEXPANDPSZ256rrk = 4794, + X86_VEXPANDPSZ256rrkz = 4795, + X86_VEXPANDPSZrm = 4796, + X86_VEXPANDPSZrmk = 4797, + X86_VEXPANDPSZrmkz = 4798, + X86_VEXPANDPSZrr = 4799, + X86_VEXPANDPSZrrk = 4800, + X86_VEXPANDPSZrrkz = 4801, + X86_VEXTRACTF128mr = 4802, + X86_VEXTRACTF128rr = 4803, + X86_VEXTRACTF32x4Z256mr = 4804, + X86_VEXTRACTF32x4Z256mrk = 4805, + X86_VEXTRACTF32x4Z256rr = 4806, + X86_VEXTRACTF32x4Z256rrk = 4807, + X86_VEXTRACTF32x4Z256rrkz = 4808, + X86_VEXTRACTF32x4Zmr = 4809, + X86_VEXTRACTF32x4Zmrk = 4810, + X86_VEXTRACTF32x4Zrr = 4811, + X86_VEXTRACTF32x4Zrrk = 4812, + X86_VEXTRACTF32x4Zrrkz = 4813, + X86_VEXTRACTF32x8Zmr = 4814, + X86_VEXTRACTF32x8Zmrk = 4815, + X86_VEXTRACTF32x8Zrr = 4816, + X86_VEXTRACTF32x8Zrrk = 4817, + X86_VEXTRACTF32x8Zrrkz = 4818, + X86_VEXTRACTF64x2Z256mr = 4819, + X86_VEXTRACTF64x2Z256mrk = 4820, + X86_VEXTRACTF64x2Z256rr = 4821, + X86_VEXTRACTF64x2Z256rrk = 4822, + X86_VEXTRACTF64x2Z256rrkz = 4823, + X86_VEXTRACTF64x2Zmr = 4824, + X86_VEXTRACTF64x2Zmrk = 4825, + X86_VEXTRACTF64x2Zrr = 4826, + X86_VEXTRACTF64x2Zrrk = 4827, + X86_VEXTRACTF64x2Zrrkz = 4828, + X86_VEXTRACTF64x4Zmr = 4829, + X86_VEXTRACTF64x4Zmrk = 4830, + X86_VEXTRACTF64x4Zrr = 4831, + X86_VEXTRACTF64x4Zrrk = 4832, + X86_VEXTRACTF64x4Zrrkz = 4833, + X86_VEXTRACTI128mr = 4834, + X86_VEXTRACTI128rr = 4835, + X86_VEXTRACTI32x4Z256mr = 4836, + X86_VEXTRACTI32x4Z256mrk = 4837, + X86_VEXTRACTI32x4Z256rr = 4838, + X86_VEXTRACTI32x4Z256rrk = 4839, + X86_VEXTRACTI32x4Z256rrkz = 4840, + X86_VEXTRACTI32x4Zmr = 4841, + X86_VEXTRACTI32x4Zmrk = 4842, + X86_VEXTRACTI32x4Zrr = 4843, + X86_VEXTRACTI32x4Zrrk = 4844, + X86_VEXTRACTI32x4Zrrkz = 4845, + X86_VEXTRACTI32x8Zmr = 4846, + X86_VEXTRACTI32x8Zmrk = 4847, + X86_VEXTRACTI32x8Zrr = 4848, + X86_VEXTRACTI32x8Zrrk = 4849, + X86_VEXTRACTI32x8Zrrkz = 4850, + X86_VEXTRACTI64x2Z256mr = 4851, + X86_VEXTRACTI64x2Z256mrk = 4852, + X86_VEXTRACTI64x2Z256rr = 4853, + X86_VEXTRACTI64x2Z256rrk = 4854, + X86_VEXTRACTI64x2Z256rrkz = 4855, + X86_VEXTRACTI64x2Zmr = 4856, + X86_VEXTRACTI64x2Zmrk = 4857, + X86_VEXTRACTI64x2Zrr = 4858, + X86_VEXTRACTI64x2Zrrk = 4859, + X86_VEXTRACTI64x2Zrrkz = 4860, + X86_VEXTRACTI64x4Zmr = 4861, + X86_VEXTRACTI64x4Zmrk = 4862, + X86_VEXTRACTI64x4Zrr = 4863, + X86_VEXTRACTI64x4Zrrk = 4864, + X86_VEXTRACTI64x4Zrrkz = 4865, + X86_VEXTRACTPSZmr = 4866, + X86_VEXTRACTPSZrr = 4867, + X86_VEXTRACTPSmr = 4868, + X86_VEXTRACTPSrr = 4869, + X86_VFIXUPIMMPDZ128rmbi = 4870, + X86_VFIXUPIMMPDZ128rmbik = 4871, + X86_VFIXUPIMMPDZ128rmbikz = 4872, + X86_VFIXUPIMMPDZ128rmi = 4873, + X86_VFIXUPIMMPDZ128rmik = 4874, + X86_VFIXUPIMMPDZ128rmikz = 4875, + X86_VFIXUPIMMPDZ128rri = 4876, + X86_VFIXUPIMMPDZ128rrik = 4877, + X86_VFIXUPIMMPDZ128rrikz = 4878, + X86_VFIXUPIMMPDZ256rmbi = 4879, + X86_VFIXUPIMMPDZ256rmbik = 4880, + X86_VFIXUPIMMPDZ256rmbikz = 4881, + X86_VFIXUPIMMPDZ256rmi = 4882, + X86_VFIXUPIMMPDZ256rmik = 4883, + X86_VFIXUPIMMPDZ256rmikz = 4884, + X86_VFIXUPIMMPDZ256rri = 4885, + X86_VFIXUPIMMPDZ256rrik = 4886, + X86_VFIXUPIMMPDZ256rrikz = 4887, + X86_VFIXUPIMMPDZrmbi = 4888, + X86_VFIXUPIMMPDZrmbik = 4889, + X86_VFIXUPIMMPDZrmbikz = 4890, + X86_VFIXUPIMMPDZrmi = 4891, + X86_VFIXUPIMMPDZrmik = 4892, + X86_VFIXUPIMMPDZrmikz = 4893, + X86_VFIXUPIMMPDZrri = 4894, + X86_VFIXUPIMMPDZrrib = 4895, + X86_VFIXUPIMMPDZrribk = 4896, + X86_VFIXUPIMMPDZrribkz = 4897, + X86_VFIXUPIMMPDZrrik = 4898, + X86_VFIXUPIMMPDZrrikz = 4899, + X86_VFIXUPIMMPSZ128rmbi = 4900, + X86_VFIXUPIMMPSZ128rmbik = 4901, + X86_VFIXUPIMMPSZ128rmbikz = 4902, + X86_VFIXUPIMMPSZ128rmi = 4903, + X86_VFIXUPIMMPSZ128rmik = 4904, + X86_VFIXUPIMMPSZ128rmikz = 4905, + X86_VFIXUPIMMPSZ128rri = 4906, + X86_VFIXUPIMMPSZ128rrik = 4907, + X86_VFIXUPIMMPSZ128rrikz = 4908, + X86_VFIXUPIMMPSZ256rmbi = 4909, + X86_VFIXUPIMMPSZ256rmbik = 4910, + X86_VFIXUPIMMPSZ256rmbikz = 4911, + X86_VFIXUPIMMPSZ256rmi = 4912, + X86_VFIXUPIMMPSZ256rmik = 4913, + X86_VFIXUPIMMPSZ256rmikz = 4914, + X86_VFIXUPIMMPSZ256rri = 4915, + X86_VFIXUPIMMPSZ256rrik = 4916, + X86_VFIXUPIMMPSZ256rrikz = 4917, + X86_VFIXUPIMMPSZrmbi = 4918, + X86_VFIXUPIMMPSZrmbik = 4919, + X86_VFIXUPIMMPSZrmbikz = 4920, + X86_VFIXUPIMMPSZrmi = 4921, + X86_VFIXUPIMMPSZrmik = 4922, + X86_VFIXUPIMMPSZrmikz = 4923, + X86_VFIXUPIMMPSZrri = 4924, + X86_VFIXUPIMMPSZrrib = 4925, + X86_VFIXUPIMMPSZrribk = 4926, + X86_VFIXUPIMMPSZrribkz = 4927, + X86_VFIXUPIMMPSZrrik = 4928, + X86_VFIXUPIMMPSZrrikz = 4929, + X86_VFIXUPIMMSDZrmi = 4930, + X86_VFIXUPIMMSDZrmik = 4931, + X86_VFIXUPIMMSDZrmikz = 4932, + X86_VFIXUPIMMSDZrri = 4933, + X86_VFIXUPIMMSDZrrib = 4934, + X86_VFIXUPIMMSDZrribk = 4935, + X86_VFIXUPIMMSDZrribkz = 4936, + X86_VFIXUPIMMSDZrrik = 4937, + X86_VFIXUPIMMSDZrrikz = 4938, + X86_VFIXUPIMMSSZrmi = 4939, + X86_VFIXUPIMMSSZrmik = 4940, + X86_VFIXUPIMMSSZrmikz = 4941, + X86_VFIXUPIMMSSZrri = 4942, + X86_VFIXUPIMMSSZrrib = 4943, + X86_VFIXUPIMMSSZrribk = 4944, + X86_VFIXUPIMMSSZrribkz = 4945, + X86_VFIXUPIMMSSZrrik = 4946, + X86_VFIXUPIMMSSZrrikz = 4947, + X86_VFMADD132PDYm = 4948, + X86_VFMADD132PDYr = 4949, + X86_VFMADD132PDZ128m = 4950, + X86_VFMADD132PDZ128mb = 4951, + X86_VFMADD132PDZ128mbk = 4952, + X86_VFMADD132PDZ128mbkz = 4953, + X86_VFMADD132PDZ128mk = 4954, + X86_VFMADD132PDZ128mkz = 4955, + X86_VFMADD132PDZ128r = 4956, + X86_VFMADD132PDZ128rk = 4957, + X86_VFMADD132PDZ128rkz = 4958, + X86_VFMADD132PDZ256m = 4959, + X86_VFMADD132PDZ256mb = 4960, + X86_VFMADD132PDZ256mbk = 4961, + X86_VFMADD132PDZ256mbkz = 4962, + X86_VFMADD132PDZ256mk = 4963, + X86_VFMADD132PDZ256mkz = 4964, + X86_VFMADD132PDZ256r = 4965, + X86_VFMADD132PDZ256rk = 4966, + X86_VFMADD132PDZ256rkz = 4967, + X86_VFMADD132PDZm = 4968, + X86_VFMADD132PDZmb = 4969, + X86_VFMADD132PDZmbk = 4970, + X86_VFMADD132PDZmbkz = 4971, + X86_VFMADD132PDZmk = 4972, + X86_VFMADD132PDZmkz = 4973, + X86_VFMADD132PDZr = 4974, + X86_VFMADD132PDZrb = 4975, + X86_VFMADD132PDZrbk = 4976, + X86_VFMADD132PDZrbkz = 4977, + X86_VFMADD132PDZrk = 4978, + X86_VFMADD132PDZrkz = 4979, + X86_VFMADD132PDm = 4980, + X86_VFMADD132PDr = 4981, + X86_VFMADD132PSYm = 4982, + X86_VFMADD132PSYr = 4983, + X86_VFMADD132PSZ128m = 4984, + X86_VFMADD132PSZ128mb = 4985, + X86_VFMADD132PSZ128mbk = 4986, + X86_VFMADD132PSZ128mbkz = 4987, + X86_VFMADD132PSZ128mk = 4988, + X86_VFMADD132PSZ128mkz = 4989, + X86_VFMADD132PSZ128r = 4990, + X86_VFMADD132PSZ128rk = 4991, + X86_VFMADD132PSZ128rkz = 4992, + X86_VFMADD132PSZ256m = 4993, + X86_VFMADD132PSZ256mb = 4994, + X86_VFMADD132PSZ256mbk = 4995, + X86_VFMADD132PSZ256mbkz = 4996, + X86_VFMADD132PSZ256mk = 4997, + X86_VFMADD132PSZ256mkz = 4998, + X86_VFMADD132PSZ256r = 4999, + X86_VFMADD132PSZ256rk = 5000, + X86_VFMADD132PSZ256rkz = 5001, + X86_VFMADD132PSZm = 5002, + X86_VFMADD132PSZmb = 5003, + X86_VFMADD132PSZmbk = 5004, + X86_VFMADD132PSZmbkz = 5005, + X86_VFMADD132PSZmk = 5006, + X86_VFMADD132PSZmkz = 5007, + X86_VFMADD132PSZr = 5008, + X86_VFMADD132PSZrb = 5009, + X86_VFMADD132PSZrbk = 5010, + X86_VFMADD132PSZrbkz = 5011, + X86_VFMADD132PSZrk = 5012, + X86_VFMADD132PSZrkz = 5013, + X86_VFMADD132PSm = 5014, + X86_VFMADD132PSr = 5015, + X86_VFMADD132SDZm = 5016, + X86_VFMADD132SDZm_Int = 5017, + X86_VFMADD132SDZm_Intk = 5018, + X86_VFMADD132SDZm_Intkz = 5019, + X86_VFMADD132SDZr = 5020, + X86_VFMADD132SDZr_Int = 5021, + X86_VFMADD132SDZr_Intk = 5022, + X86_VFMADD132SDZr_Intkz = 5023, + X86_VFMADD132SDZrb = 5024, + X86_VFMADD132SDZrb_Int = 5025, + X86_VFMADD132SDZrb_Intk = 5026, + X86_VFMADD132SDZrb_Intkz = 5027, + X86_VFMADD132SDm = 5028, + X86_VFMADD132SDm_Int = 5029, + X86_VFMADD132SDr = 5030, + X86_VFMADD132SDr_Int = 5031, + X86_VFMADD132SSZm = 5032, + X86_VFMADD132SSZm_Int = 5033, + X86_VFMADD132SSZm_Intk = 5034, + X86_VFMADD132SSZm_Intkz = 5035, + X86_VFMADD132SSZr = 5036, + X86_VFMADD132SSZr_Int = 5037, + X86_VFMADD132SSZr_Intk = 5038, + X86_VFMADD132SSZr_Intkz = 5039, + X86_VFMADD132SSZrb = 5040, + X86_VFMADD132SSZrb_Int = 5041, + X86_VFMADD132SSZrb_Intk = 5042, + X86_VFMADD132SSZrb_Intkz = 5043, + X86_VFMADD132SSm = 5044, + X86_VFMADD132SSm_Int = 5045, + X86_VFMADD132SSr = 5046, + X86_VFMADD132SSr_Int = 5047, + X86_VFMADD213PDYm = 5048, + X86_VFMADD213PDYr = 5049, + X86_VFMADD213PDZ128m = 5050, + X86_VFMADD213PDZ128mb = 5051, + X86_VFMADD213PDZ128mbk = 5052, + X86_VFMADD213PDZ128mbkz = 5053, + X86_VFMADD213PDZ128mk = 5054, + X86_VFMADD213PDZ128mkz = 5055, + X86_VFMADD213PDZ128r = 5056, + X86_VFMADD213PDZ128rk = 5057, + X86_VFMADD213PDZ128rkz = 5058, + X86_VFMADD213PDZ256m = 5059, + X86_VFMADD213PDZ256mb = 5060, + X86_VFMADD213PDZ256mbk = 5061, + X86_VFMADD213PDZ256mbkz = 5062, + X86_VFMADD213PDZ256mk = 5063, + X86_VFMADD213PDZ256mkz = 5064, + X86_VFMADD213PDZ256r = 5065, + X86_VFMADD213PDZ256rk = 5066, + X86_VFMADD213PDZ256rkz = 5067, + X86_VFMADD213PDZm = 5068, + X86_VFMADD213PDZmb = 5069, + X86_VFMADD213PDZmbk = 5070, + X86_VFMADD213PDZmbkz = 5071, + X86_VFMADD213PDZmk = 5072, + X86_VFMADD213PDZmkz = 5073, + X86_VFMADD213PDZr = 5074, + X86_VFMADD213PDZrb = 5075, + X86_VFMADD213PDZrbk = 5076, + X86_VFMADD213PDZrbkz = 5077, + X86_VFMADD213PDZrk = 5078, + X86_VFMADD213PDZrkz = 5079, + X86_VFMADD213PDm = 5080, + X86_VFMADD213PDr = 5081, + X86_VFMADD213PSYm = 5082, + X86_VFMADD213PSYr = 5083, + X86_VFMADD213PSZ128m = 5084, + X86_VFMADD213PSZ128mb = 5085, + X86_VFMADD213PSZ128mbk = 5086, + X86_VFMADD213PSZ128mbkz = 5087, + X86_VFMADD213PSZ128mk = 5088, + X86_VFMADD213PSZ128mkz = 5089, + X86_VFMADD213PSZ128r = 5090, + X86_VFMADD213PSZ128rk = 5091, + X86_VFMADD213PSZ128rkz = 5092, + X86_VFMADD213PSZ256m = 5093, + X86_VFMADD213PSZ256mb = 5094, + X86_VFMADD213PSZ256mbk = 5095, + X86_VFMADD213PSZ256mbkz = 5096, + X86_VFMADD213PSZ256mk = 5097, + X86_VFMADD213PSZ256mkz = 5098, + X86_VFMADD213PSZ256r = 5099, + X86_VFMADD213PSZ256rk = 5100, + X86_VFMADD213PSZ256rkz = 5101, + X86_VFMADD213PSZm = 5102, + X86_VFMADD213PSZmb = 5103, + X86_VFMADD213PSZmbk = 5104, + X86_VFMADD213PSZmbkz = 5105, + X86_VFMADD213PSZmk = 5106, + X86_VFMADD213PSZmkz = 5107, + X86_VFMADD213PSZr = 5108, + X86_VFMADD213PSZrb = 5109, + X86_VFMADD213PSZrbk = 5110, + X86_VFMADD213PSZrbkz = 5111, + X86_VFMADD213PSZrk = 5112, + X86_VFMADD213PSZrkz = 5113, + X86_VFMADD213PSm = 5114, + X86_VFMADD213PSr = 5115, + X86_VFMADD213SDZm = 5116, + X86_VFMADD213SDZm_Int = 5117, + X86_VFMADD213SDZm_Intk = 5118, + X86_VFMADD213SDZm_Intkz = 5119, + X86_VFMADD213SDZr = 5120, + X86_VFMADD213SDZr_Int = 5121, + X86_VFMADD213SDZr_Intk = 5122, + X86_VFMADD213SDZr_Intkz = 5123, + X86_VFMADD213SDZrb = 5124, + X86_VFMADD213SDZrb_Int = 5125, + X86_VFMADD213SDZrb_Intk = 5126, + X86_VFMADD213SDZrb_Intkz = 5127, + X86_VFMADD213SDm = 5128, + X86_VFMADD213SDm_Int = 5129, + X86_VFMADD213SDr = 5130, + X86_VFMADD213SDr_Int = 5131, + X86_VFMADD213SSZm = 5132, + X86_VFMADD213SSZm_Int = 5133, + X86_VFMADD213SSZm_Intk = 5134, + X86_VFMADD213SSZm_Intkz = 5135, + X86_VFMADD213SSZr = 5136, + X86_VFMADD213SSZr_Int = 5137, + X86_VFMADD213SSZr_Intk = 5138, + X86_VFMADD213SSZr_Intkz = 5139, + X86_VFMADD213SSZrb = 5140, + X86_VFMADD213SSZrb_Int = 5141, + X86_VFMADD213SSZrb_Intk = 5142, + X86_VFMADD213SSZrb_Intkz = 5143, + X86_VFMADD213SSm = 5144, + X86_VFMADD213SSm_Int = 5145, + X86_VFMADD213SSr = 5146, + X86_VFMADD213SSr_Int = 5147, + X86_VFMADD231PDYm = 5148, + X86_VFMADD231PDYr = 5149, + X86_VFMADD231PDZ128m = 5150, + X86_VFMADD231PDZ128mb = 5151, + X86_VFMADD231PDZ128mbk = 5152, + X86_VFMADD231PDZ128mbkz = 5153, + X86_VFMADD231PDZ128mk = 5154, + X86_VFMADD231PDZ128mkz = 5155, + X86_VFMADD231PDZ128r = 5156, + X86_VFMADD231PDZ128rk = 5157, + X86_VFMADD231PDZ128rkz = 5158, + X86_VFMADD231PDZ256m = 5159, + X86_VFMADD231PDZ256mb = 5160, + X86_VFMADD231PDZ256mbk = 5161, + X86_VFMADD231PDZ256mbkz = 5162, + X86_VFMADD231PDZ256mk = 5163, + X86_VFMADD231PDZ256mkz = 5164, + X86_VFMADD231PDZ256r = 5165, + X86_VFMADD231PDZ256rk = 5166, + X86_VFMADD231PDZ256rkz = 5167, + X86_VFMADD231PDZm = 5168, + X86_VFMADD231PDZmb = 5169, + X86_VFMADD231PDZmbk = 5170, + X86_VFMADD231PDZmbkz = 5171, + X86_VFMADD231PDZmk = 5172, + X86_VFMADD231PDZmkz = 5173, + X86_VFMADD231PDZr = 5174, + X86_VFMADD231PDZrb = 5175, + X86_VFMADD231PDZrbk = 5176, + X86_VFMADD231PDZrbkz = 5177, + X86_VFMADD231PDZrk = 5178, + X86_VFMADD231PDZrkz = 5179, + X86_VFMADD231PDm = 5180, + X86_VFMADD231PDr = 5181, + X86_VFMADD231PSYm = 5182, + X86_VFMADD231PSYr = 5183, + X86_VFMADD231PSZ128m = 5184, + X86_VFMADD231PSZ128mb = 5185, + X86_VFMADD231PSZ128mbk = 5186, + X86_VFMADD231PSZ128mbkz = 5187, + X86_VFMADD231PSZ128mk = 5188, + X86_VFMADD231PSZ128mkz = 5189, + X86_VFMADD231PSZ128r = 5190, + X86_VFMADD231PSZ128rk = 5191, + X86_VFMADD231PSZ128rkz = 5192, + X86_VFMADD231PSZ256m = 5193, + X86_VFMADD231PSZ256mb = 5194, + X86_VFMADD231PSZ256mbk = 5195, + X86_VFMADD231PSZ256mbkz = 5196, + X86_VFMADD231PSZ256mk = 5197, + X86_VFMADD231PSZ256mkz = 5198, + X86_VFMADD231PSZ256r = 5199, + X86_VFMADD231PSZ256rk = 5200, + X86_VFMADD231PSZ256rkz = 5201, + X86_VFMADD231PSZm = 5202, + X86_VFMADD231PSZmb = 5203, + X86_VFMADD231PSZmbk = 5204, + X86_VFMADD231PSZmbkz = 5205, + X86_VFMADD231PSZmk = 5206, + X86_VFMADD231PSZmkz = 5207, + X86_VFMADD231PSZr = 5208, + X86_VFMADD231PSZrb = 5209, + X86_VFMADD231PSZrbk = 5210, + X86_VFMADD231PSZrbkz = 5211, + X86_VFMADD231PSZrk = 5212, + X86_VFMADD231PSZrkz = 5213, + X86_VFMADD231PSm = 5214, + X86_VFMADD231PSr = 5215, + X86_VFMADD231SDZm = 5216, + X86_VFMADD231SDZm_Int = 5217, + X86_VFMADD231SDZm_Intk = 5218, + X86_VFMADD231SDZm_Intkz = 5219, + X86_VFMADD231SDZr = 5220, + X86_VFMADD231SDZr_Int = 5221, + X86_VFMADD231SDZr_Intk = 5222, + X86_VFMADD231SDZr_Intkz = 5223, + X86_VFMADD231SDZrb = 5224, + X86_VFMADD231SDZrb_Int = 5225, + X86_VFMADD231SDZrb_Intk = 5226, + X86_VFMADD231SDZrb_Intkz = 5227, + X86_VFMADD231SDm = 5228, + X86_VFMADD231SDm_Int = 5229, + X86_VFMADD231SDr = 5230, + X86_VFMADD231SDr_Int = 5231, + X86_VFMADD231SSZm = 5232, + X86_VFMADD231SSZm_Int = 5233, + X86_VFMADD231SSZm_Intk = 5234, + X86_VFMADD231SSZm_Intkz = 5235, + X86_VFMADD231SSZr = 5236, + X86_VFMADD231SSZr_Int = 5237, + X86_VFMADD231SSZr_Intk = 5238, + X86_VFMADD231SSZr_Intkz = 5239, + X86_VFMADD231SSZrb = 5240, + X86_VFMADD231SSZrb_Int = 5241, + X86_VFMADD231SSZrb_Intk = 5242, + X86_VFMADD231SSZrb_Intkz = 5243, + X86_VFMADD231SSm = 5244, + X86_VFMADD231SSm_Int = 5245, + X86_VFMADD231SSr = 5246, + X86_VFMADD231SSr_Int = 5247, + X86_VFMADDPD4Ymr = 5248, + X86_VFMADDPD4Yrm = 5249, + X86_VFMADDPD4Yrr = 5250, + X86_VFMADDPD4Yrr_REV = 5251, + X86_VFMADDPD4mr = 5252, + X86_VFMADDPD4rm = 5253, + X86_VFMADDPD4rr = 5254, + X86_VFMADDPD4rr_REV = 5255, + X86_VFMADDPS4Ymr = 5256, + X86_VFMADDPS4Yrm = 5257, + X86_VFMADDPS4Yrr = 5258, + X86_VFMADDPS4Yrr_REV = 5259, + X86_VFMADDPS4mr = 5260, + X86_VFMADDPS4rm = 5261, + X86_VFMADDPS4rr = 5262, + X86_VFMADDPS4rr_REV = 5263, + X86_VFMADDSD4mr = 5264, + X86_VFMADDSD4mr_Int = 5265, + X86_VFMADDSD4rm = 5266, + X86_VFMADDSD4rm_Int = 5267, + X86_VFMADDSD4rr = 5268, + X86_VFMADDSD4rr_Int = 5269, + X86_VFMADDSD4rr_Int_REV = 5270, + X86_VFMADDSD4rr_REV = 5271, + X86_VFMADDSS4mr = 5272, + X86_VFMADDSS4mr_Int = 5273, + X86_VFMADDSS4rm = 5274, + X86_VFMADDSS4rm_Int = 5275, + X86_VFMADDSS4rr = 5276, + X86_VFMADDSS4rr_Int = 5277, + X86_VFMADDSS4rr_Int_REV = 5278, + X86_VFMADDSS4rr_REV = 5279, + X86_VFMADDSUB132PDYm = 5280, + X86_VFMADDSUB132PDYr = 5281, + X86_VFMADDSUB132PDZ128m = 5282, + X86_VFMADDSUB132PDZ128mb = 5283, + X86_VFMADDSUB132PDZ128mbk = 5284, + X86_VFMADDSUB132PDZ128mbkz = 5285, + X86_VFMADDSUB132PDZ128mk = 5286, + X86_VFMADDSUB132PDZ128mkz = 5287, + X86_VFMADDSUB132PDZ128r = 5288, + X86_VFMADDSUB132PDZ128rk = 5289, + X86_VFMADDSUB132PDZ128rkz = 5290, + X86_VFMADDSUB132PDZ256m = 5291, + X86_VFMADDSUB132PDZ256mb = 5292, + X86_VFMADDSUB132PDZ256mbk = 5293, + X86_VFMADDSUB132PDZ256mbkz = 5294, + X86_VFMADDSUB132PDZ256mk = 5295, + X86_VFMADDSUB132PDZ256mkz = 5296, + X86_VFMADDSUB132PDZ256r = 5297, + X86_VFMADDSUB132PDZ256rk = 5298, + X86_VFMADDSUB132PDZ256rkz = 5299, + X86_VFMADDSUB132PDZm = 5300, + X86_VFMADDSUB132PDZmb = 5301, + X86_VFMADDSUB132PDZmbk = 5302, + X86_VFMADDSUB132PDZmbkz = 5303, + X86_VFMADDSUB132PDZmk = 5304, + X86_VFMADDSUB132PDZmkz = 5305, + X86_VFMADDSUB132PDZr = 5306, + X86_VFMADDSUB132PDZrb = 5307, + X86_VFMADDSUB132PDZrbk = 5308, + X86_VFMADDSUB132PDZrbkz = 5309, + X86_VFMADDSUB132PDZrk = 5310, + X86_VFMADDSUB132PDZrkz = 5311, + X86_VFMADDSUB132PDm = 5312, + X86_VFMADDSUB132PDr = 5313, + X86_VFMADDSUB132PSYm = 5314, + X86_VFMADDSUB132PSYr = 5315, + X86_VFMADDSUB132PSZ128m = 5316, + X86_VFMADDSUB132PSZ128mb = 5317, + X86_VFMADDSUB132PSZ128mbk = 5318, + X86_VFMADDSUB132PSZ128mbkz = 5319, + X86_VFMADDSUB132PSZ128mk = 5320, + X86_VFMADDSUB132PSZ128mkz = 5321, + X86_VFMADDSUB132PSZ128r = 5322, + X86_VFMADDSUB132PSZ128rk = 5323, + X86_VFMADDSUB132PSZ128rkz = 5324, + X86_VFMADDSUB132PSZ256m = 5325, + X86_VFMADDSUB132PSZ256mb = 5326, + X86_VFMADDSUB132PSZ256mbk = 5327, + X86_VFMADDSUB132PSZ256mbkz = 5328, + X86_VFMADDSUB132PSZ256mk = 5329, + X86_VFMADDSUB132PSZ256mkz = 5330, + X86_VFMADDSUB132PSZ256r = 5331, + X86_VFMADDSUB132PSZ256rk = 5332, + X86_VFMADDSUB132PSZ256rkz = 5333, + X86_VFMADDSUB132PSZm = 5334, + X86_VFMADDSUB132PSZmb = 5335, + X86_VFMADDSUB132PSZmbk = 5336, + X86_VFMADDSUB132PSZmbkz = 5337, + X86_VFMADDSUB132PSZmk = 5338, + X86_VFMADDSUB132PSZmkz = 5339, + X86_VFMADDSUB132PSZr = 5340, + X86_VFMADDSUB132PSZrb = 5341, + X86_VFMADDSUB132PSZrbk = 5342, + X86_VFMADDSUB132PSZrbkz = 5343, + X86_VFMADDSUB132PSZrk = 5344, + X86_VFMADDSUB132PSZrkz = 5345, + X86_VFMADDSUB132PSm = 5346, + X86_VFMADDSUB132PSr = 5347, + X86_VFMADDSUB213PDYm = 5348, + X86_VFMADDSUB213PDYr = 5349, + X86_VFMADDSUB213PDZ128m = 5350, + X86_VFMADDSUB213PDZ128mb = 5351, + X86_VFMADDSUB213PDZ128mbk = 5352, + X86_VFMADDSUB213PDZ128mbkz = 5353, + X86_VFMADDSUB213PDZ128mk = 5354, + X86_VFMADDSUB213PDZ128mkz = 5355, + X86_VFMADDSUB213PDZ128r = 5356, + X86_VFMADDSUB213PDZ128rk = 5357, + X86_VFMADDSUB213PDZ128rkz = 5358, + X86_VFMADDSUB213PDZ256m = 5359, + X86_VFMADDSUB213PDZ256mb = 5360, + X86_VFMADDSUB213PDZ256mbk = 5361, + X86_VFMADDSUB213PDZ256mbkz = 5362, + X86_VFMADDSUB213PDZ256mk = 5363, + X86_VFMADDSUB213PDZ256mkz = 5364, + X86_VFMADDSUB213PDZ256r = 5365, + X86_VFMADDSUB213PDZ256rk = 5366, + X86_VFMADDSUB213PDZ256rkz = 5367, + X86_VFMADDSUB213PDZm = 5368, + X86_VFMADDSUB213PDZmb = 5369, + X86_VFMADDSUB213PDZmbk = 5370, + X86_VFMADDSUB213PDZmbkz = 5371, + X86_VFMADDSUB213PDZmk = 5372, + X86_VFMADDSUB213PDZmkz = 5373, + X86_VFMADDSUB213PDZr = 5374, + X86_VFMADDSUB213PDZrb = 5375, + X86_VFMADDSUB213PDZrbk = 5376, + X86_VFMADDSUB213PDZrbkz = 5377, + X86_VFMADDSUB213PDZrk = 5378, + X86_VFMADDSUB213PDZrkz = 5379, + X86_VFMADDSUB213PDm = 5380, + X86_VFMADDSUB213PDr = 5381, + X86_VFMADDSUB213PSYm = 5382, + X86_VFMADDSUB213PSYr = 5383, + X86_VFMADDSUB213PSZ128m = 5384, + X86_VFMADDSUB213PSZ128mb = 5385, + X86_VFMADDSUB213PSZ128mbk = 5386, + X86_VFMADDSUB213PSZ128mbkz = 5387, + X86_VFMADDSUB213PSZ128mk = 5388, + X86_VFMADDSUB213PSZ128mkz = 5389, + X86_VFMADDSUB213PSZ128r = 5390, + X86_VFMADDSUB213PSZ128rk = 5391, + X86_VFMADDSUB213PSZ128rkz = 5392, + X86_VFMADDSUB213PSZ256m = 5393, + X86_VFMADDSUB213PSZ256mb = 5394, + X86_VFMADDSUB213PSZ256mbk = 5395, + X86_VFMADDSUB213PSZ256mbkz = 5396, + X86_VFMADDSUB213PSZ256mk = 5397, + X86_VFMADDSUB213PSZ256mkz = 5398, + X86_VFMADDSUB213PSZ256r = 5399, + X86_VFMADDSUB213PSZ256rk = 5400, + X86_VFMADDSUB213PSZ256rkz = 5401, + X86_VFMADDSUB213PSZm = 5402, + X86_VFMADDSUB213PSZmb = 5403, + X86_VFMADDSUB213PSZmbk = 5404, + X86_VFMADDSUB213PSZmbkz = 5405, + X86_VFMADDSUB213PSZmk = 5406, + X86_VFMADDSUB213PSZmkz = 5407, + X86_VFMADDSUB213PSZr = 5408, + X86_VFMADDSUB213PSZrb = 5409, + X86_VFMADDSUB213PSZrbk = 5410, + X86_VFMADDSUB213PSZrbkz = 5411, + X86_VFMADDSUB213PSZrk = 5412, + X86_VFMADDSUB213PSZrkz = 5413, + X86_VFMADDSUB213PSm = 5414, + X86_VFMADDSUB213PSr = 5415, + X86_VFMADDSUB231PDYm = 5416, + X86_VFMADDSUB231PDYr = 5417, + X86_VFMADDSUB231PDZ128m = 5418, + X86_VFMADDSUB231PDZ128mb = 5419, + X86_VFMADDSUB231PDZ128mbk = 5420, + X86_VFMADDSUB231PDZ128mbkz = 5421, + X86_VFMADDSUB231PDZ128mk = 5422, + X86_VFMADDSUB231PDZ128mkz = 5423, + X86_VFMADDSUB231PDZ128r = 5424, + X86_VFMADDSUB231PDZ128rk = 5425, + X86_VFMADDSUB231PDZ128rkz = 5426, + X86_VFMADDSUB231PDZ256m = 5427, + X86_VFMADDSUB231PDZ256mb = 5428, + X86_VFMADDSUB231PDZ256mbk = 5429, + X86_VFMADDSUB231PDZ256mbkz = 5430, + X86_VFMADDSUB231PDZ256mk = 5431, + X86_VFMADDSUB231PDZ256mkz = 5432, + X86_VFMADDSUB231PDZ256r = 5433, + X86_VFMADDSUB231PDZ256rk = 5434, + X86_VFMADDSUB231PDZ256rkz = 5435, + X86_VFMADDSUB231PDZm = 5436, + X86_VFMADDSUB231PDZmb = 5437, + X86_VFMADDSUB231PDZmbk = 5438, + X86_VFMADDSUB231PDZmbkz = 5439, + X86_VFMADDSUB231PDZmk = 5440, + X86_VFMADDSUB231PDZmkz = 5441, + X86_VFMADDSUB231PDZr = 5442, + X86_VFMADDSUB231PDZrb = 5443, + X86_VFMADDSUB231PDZrbk = 5444, + X86_VFMADDSUB231PDZrbkz = 5445, + X86_VFMADDSUB231PDZrk = 5446, + X86_VFMADDSUB231PDZrkz = 5447, + X86_VFMADDSUB231PDm = 5448, + X86_VFMADDSUB231PDr = 5449, + X86_VFMADDSUB231PSYm = 5450, + X86_VFMADDSUB231PSYr = 5451, + X86_VFMADDSUB231PSZ128m = 5452, + X86_VFMADDSUB231PSZ128mb = 5453, + X86_VFMADDSUB231PSZ128mbk = 5454, + X86_VFMADDSUB231PSZ128mbkz = 5455, + X86_VFMADDSUB231PSZ128mk = 5456, + X86_VFMADDSUB231PSZ128mkz = 5457, + X86_VFMADDSUB231PSZ128r = 5458, + X86_VFMADDSUB231PSZ128rk = 5459, + X86_VFMADDSUB231PSZ128rkz = 5460, + X86_VFMADDSUB231PSZ256m = 5461, + X86_VFMADDSUB231PSZ256mb = 5462, + X86_VFMADDSUB231PSZ256mbk = 5463, + X86_VFMADDSUB231PSZ256mbkz = 5464, + X86_VFMADDSUB231PSZ256mk = 5465, + X86_VFMADDSUB231PSZ256mkz = 5466, + X86_VFMADDSUB231PSZ256r = 5467, + X86_VFMADDSUB231PSZ256rk = 5468, + X86_VFMADDSUB231PSZ256rkz = 5469, + X86_VFMADDSUB231PSZm = 5470, + X86_VFMADDSUB231PSZmb = 5471, + X86_VFMADDSUB231PSZmbk = 5472, + X86_VFMADDSUB231PSZmbkz = 5473, + X86_VFMADDSUB231PSZmk = 5474, + X86_VFMADDSUB231PSZmkz = 5475, + X86_VFMADDSUB231PSZr = 5476, + X86_VFMADDSUB231PSZrb = 5477, + X86_VFMADDSUB231PSZrbk = 5478, + X86_VFMADDSUB231PSZrbkz = 5479, + X86_VFMADDSUB231PSZrk = 5480, + X86_VFMADDSUB231PSZrkz = 5481, + X86_VFMADDSUB231PSm = 5482, + X86_VFMADDSUB231PSr = 5483, + X86_VFMADDSUBPD4Ymr = 5484, + X86_VFMADDSUBPD4Yrm = 5485, + X86_VFMADDSUBPD4Yrr = 5486, + X86_VFMADDSUBPD4Yrr_REV = 5487, + X86_VFMADDSUBPD4mr = 5488, + X86_VFMADDSUBPD4rm = 5489, + X86_VFMADDSUBPD4rr = 5490, + X86_VFMADDSUBPD4rr_REV = 5491, + X86_VFMADDSUBPS4Ymr = 5492, + X86_VFMADDSUBPS4Yrm = 5493, + X86_VFMADDSUBPS4Yrr = 5494, + X86_VFMADDSUBPS4Yrr_REV = 5495, + X86_VFMADDSUBPS4mr = 5496, + X86_VFMADDSUBPS4rm = 5497, + X86_VFMADDSUBPS4rr = 5498, + X86_VFMADDSUBPS4rr_REV = 5499, + X86_VFMSUB132PDYm = 5500, + X86_VFMSUB132PDYr = 5501, + X86_VFMSUB132PDZ128m = 5502, + X86_VFMSUB132PDZ128mb = 5503, + X86_VFMSUB132PDZ128mbk = 5504, + X86_VFMSUB132PDZ128mbkz = 5505, + X86_VFMSUB132PDZ128mk = 5506, + X86_VFMSUB132PDZ128mkz = 5507, + X86_VFMSUB132PDZ128r = 5508, + X86_VFMSUB132PDZ128rk = 5509, + X86_VFMSUB132PDZ128rkz = 5510, + X86_VFMSUB132PDZ256m = 5511, + X86_VFMSUB132PDZ256mb = 5512, + X86_VFMSUB132PDZ256mbk = 5513, + X86_VFMSUB132PDZ256mbkz = 5514, + X86_VFMSUB132PDZ256mk = 5515, + X86_VFMSUB132PDZ256mkz = 5516, + X86_VFMSUB132PDZ256r = 5517, + X86_VFMSUB132PDZ256rk = 5518, + X86_VFMSUB132PDZ256rkz = 5519, + X86_VFMSUB132PDZm = 5520, + X86_VFMSUB132PDZmb = 5521, + X86_VFMSUB132PDZmbk = 5522, + X86_VFMSUB132PDZmbkz = 5523, + X86_VFMSUB132PDZmk = 5524, + X86_VFMSUB132PDZmkz = 5525, + X86_VFMSUB132PDZr = 5526, + X86_VFMSUB132PDZrb = 5527, + X86_VFMSUB132PDZrbk = 5528, + X86_VFMSUB132PDZrbkz = 5529, + X86_VFMSUB132PDZrk = 5530, + X86_VFMSUB132PDZrkz = 5531, + X86_VFMSUB132PDm = 5532, + X86_VFMSUB132PDr = 5533, + X86_VFMSUB132PSYm = 5534, + X86_VFMSUB132PSYr = 5535, + X86_VFMSUB132PSZ128m = 5536, + X86_VFMSUB132PSZ128mb = 5537, + X86_VFMSUB132PSZ128mbk = 5538, + X86_VFMSUB132PSZ128mbkz = 5539, + X86_VFMSUB132PSZ128mk = 5540, + X86_VFMSUB132PSZ128mkz = 5541, + X86_VFMSUB132PSZ128r = 5542, + X86_VFMSUB132PSZ128rk = 5543, + X86_VFMSUB132PSZ128rkz = 5544, + X86_VFMSUB132PSZ256m = 5545, + X86_VFMSUB132PSZ256mb = 5546, + X86_VFMSUB132PSZ256mbk = 5547, + X86_VFMSUB132PSZ256mbkz = 5548, + X86_VFMSUB132PSZ256mk = 5549, + X86_VFMSUB132PSZ256mkz = 5550, + X86_VFMSUB132PSZ256r = 5551, + X86_VFMSUB132PSZ256rk = 5552, + X86_VFMSUB132PSZ256rkz = 5553, + X86_VFMSUB132PSZm = 5554, + X86_VFMSUB132PSZmb = 5555, + X86_VFMSUB132PSZmbk = 5556, + X86_VFMSUB132PSZmbkz = 5557, + X86_VFMSUB132PSZmk = 5558, + X86_VFMSUB132PSZmkz = 5559, + X86_VFMSUB132PSZr = 5560, + X86_VFMSUB132PSZrb = 5561, + X86_VFMSUB132PSZrbk = 5562, + X86_VFMSUB132PSZrbkz = 5563, + X86_VFMSUB132PSZrk = 5564, + X86_VFMSUB132PSZrkz = 5565, + X86_VFMSUB132PSm = 5566, + X86_VFMSUB132PSr = 5567, + X86_VFMSUB132SDZm = 5568, + X86_VFMSUB132SDZm_Int = 5569, + X86_VFMSUB132SDZm_Intk = 5570, + X86_VFMSUB132SDZm_Intkz = 5571, + X86_VFMSUB132SDZr = 5572, + X86_VFMSUB132SDZr_Int = 5573, + X86_VFMSUB132SDZr_Intk = 5574, + X86_VFMSUB132SDZr_Intkz = 5575, + X86_VFMSUB132SDZrb = 5576, + X86_VFMSUB132SDZrb_Int = 5577, + X86_VFMSUB132SDZrb_Intk = 5578, + X86_VFMSUB132SDZrb_Intkz = 5579, + X86_VFMSUB132SDm = 5580, + X86_VFMSUB132SDm_Int = 5581, + X86_VFMSUB132SDr = 5582, + X86_VFMSUB132SDr_Int = 5583, + X86_VFMSUB132SSZm = 5584, + X86_VFMSUB132SSZm_Int = 5585, + X86_VFMSUB132SSZm_Intk = 5586, + X86_VFMSUB132SSZm_Intkz = 5587, + X86_VFMSUB132SSZr = 5588, + X86_VFMSUB132SSZr_Int = 5589, + X86_VFMSUB132SSZr_Intk = 5590, + X86_VFMSUB132SSZr_Intkz = 5591, + X86_VFMSUB132SSZrb = 5592, + X86_VFMSUB132SSZrb_Int = 5593, + X86_VFMSUB132SSZrb_Intk = 5594, + X86_VFMSUB132SSZrb_Intkz = 5595, + X86_VFMSUB132SSm = 5596, + X86_VFMSUB132SSm_Int = 5597, + X86_VFMSUB132SSr = 5598, + X86_VFMSUB132SSr_Int = 5599, + X86_VFMSUB213PDYm = 5600, + X86_VFMSUB213PDYr = 5601, + X86_VFMSUB213PDZ128m = 5602, + X86_VFMSUB213PDZ128mb = 5603, + X86_VFMSUB213PDZ128mbk = 5604, + X86_VFMSUB213PDZ128mbkz = 5605, + X86_VFMSUB213PDZ128mk = 5606, + X86_VFMSUB213PDZ128mkz = 5607, + X86_VFMSUB213PDZ128r = 5608, + X86_VFMSUB213PDZ128rk = 5609, + X86_VFMSUB213PDZ128rkz = 5610, + X86_VFMSUB213PDZ256m = 5611, + X86_VFMSUB213PDZ256mb = 5612, + X86_VFMSUB213PDZ256mbk = 5613, + X86_VFMSUB213PDZ256mbkz = 5614, + X86_VFMSUB213PDZ256mk = 5615, + X86_VFMSUB213PDZ256mkz = 5616, + X86_VFMSUB213PDZ256r = 5617, + X86_VFMSUB213PDZ256rk = 5618, + X86_VFMSUB213PDZ256rkz = 5619, + X86_VFMSUB213PDZm = 5620, + X86_VFMSUB213PDZmb = 5621, + X86_VFMSUB213PDZmbk = 5622, + X86_VFMSUB213PDZmbkz = 5623, + X86_VFMSUB213PDZmk = 5624, + X86_VFMSUB213PDZmkz = 5625, + X86_VFMSUB213PDZr = 5626, + X86_VFMSUB213PDZrb = 5627, + X86_VFMSUB213PDZrbk = 5628, + X86_VFMSUB213PDZrbkz = 5629, + X86_VFMSUB213PDZrk = 5630, + X86_VFMSUB213PDZrkz = 5631, + X86_VFMSUB213PDm = 5632, + X86_VFMSUB213PDr = 5633, + X86_VFMSUB213PSYm = 5634, + X86_VFMSUB213PSYr = 5635, + X86_VFMSUB213PSZ128m = 5636, + X86_VFMSUB213PSZ128mb = 5637, + X86_VFMSUB213PSZ128mbk = 5638, + X86_VFMSUB213PSZ128mbkz = 5639, + X86_VFMSUB213PSZ128mk = 5640, + X86_VFMSUB213PSZ128mkz = 5641, + X86_VFMSUB213PSZ128r = 5642, + X86_VFMSUB213PSZ128rk = 5643, + X86_VFMSUB213PSZ128rkz = 5644, + X86_VFMSUB213PSZ256m = 5645, + X86_VFMSUB213PSZ256mb = 5646, + X86_VFMSUB213PSZ256mbk = 5647, + X86_VFMSUB213PSZ256mbkz = 5648, + X86_VFMSUB213PSZ256mk = 5649, + X86_VFMSUB213PSZ256mkz = 5650, + X86_VFMSUB213PSZ256r = 5651, + X86_VFMSUB213PSZ256rk = 5652, + X86_VFMSUB213PSZ256rkz = 5653, + X86_VFMSUB213PSZm = 5654, + X86_VFMSUB213PSZmb = 5655, + X86_VFMSUB213PSZmbk = 5656, + X86_VFMSUB213PSZmbkz = 5657, + X86_VFMSUB213PSZmk = 5658, + X86_VFMSUB213PSZmkz = 5659, + X86_VFMSUB213PSZr = 5660, + X86_VFMSUB213PSZrb = 5661, + X86_VFMSUB213PSZrbk = 5662, + X86_VFMSUB213PSZrbkz = 5663, + X86_VFMSUB213PSZrk = 5664, + X86_VFMSUB213PSZrkz = 5665, + X86_VFMSUB213PSm = 5666, + X86_VFMSUB213PSr = 5667, + X86_VFMSUB213SDZm = 5668, + X86_VFMSUB213SDZm_Int = 5669, + X86_VFMSUB213SDZm_Intk = 5670, + X86_VFMSUB213SDZm_Intkz = 5671, + X86_VFMSUB213SDZr = 5672, + X86_VFMSUB213SDZr_Int = 5673, + X86_VFMSUB213SDZr_Intk = 5674, + X86_VFMSUB213SDZr_Intkz = 5675, + X86_VFMSUB213SDZrb = 5676, + X86_VFMSUB213SDZrb_Int = 5677, + X86_VFMSUB213SDZrb_Intk = 5678, + X86_VFMSUB213SDZrb_Intkz = 5679, + X86_VFMSUB213SDm = 5680, + X86_VFMSUB213SDm_Int = 5681, + X86_VFMSUB213SDr = 5682, + X86_VFMSUB213SDr_Int = 5683, + X86_VFMSUB213SSZm = 5684, + X86_VFMSUB213SSZm_Int = 5685, + X86_VFMSUB213SSZm_Intk = 5686, + X86_VFMSUB213SSZm_Intkz = 5687, + X86_VFMSUB213SSZr = 5688, + X86_VFMSUB213SSZr_Int = 5689, + X86_VFMSUB213SSZr_Intk = 5690, + X86_VFMSUB213SSZr_Intkz = 5691, + X86_VFMSUB213SSZrb = 5692, + X86_VFMSUB213SSZrb_Int = 5693, + X86_VFMSUB213SSZrb_Intk = 5694, + X86_VFMSUB213SSZrb_Intkz = 5695, + X86_VFMSUB213SSm = 5696, + X86_VFMSUB213SSm_Int = 5697, + X86_VFMSUB213SSr = 5698, + X86_VFMSUB213SSr_Int = 5699, + X86_VFMSUB231PDYm = 5700, + X86_VFMSUB231PDYr = 5701, + X86_VFMSUB231PDZ128m = 5702, + X86_VFMSUB231PDZ128mb = 5703, + X86_VFMSUB231PDZ128mbk = 5704, + X86_VFMSUB231PDZ128mbkz = 5705, + X86_VFMSUB231PDZ128mk = 5706, + X86_VFMSUB231PDZ128mkz = 5707, + X86_VFMSUB231PDZ128r = 5708, + X86_VFMSUB231PDZ128rk = 5709, + X86_VFMSUB231PDZ128rkz = 5710, + X86_VFMSUB231PDZ256m = 5711, + X86_VFMSUB231PDZ256mb = 5712, + X86_VFMSUB231PDZ256mbk = 5713, + X86_VFMSUB231PDZ256mbkz = 5714, + X86_VFMSUB231PDZ256mk = 5715, + X86_VFMSUB231PDZ256mkz = 5716, + X86_VFMSUB231PDZ256r = 5717, + X86_VFMSUB231PDZ256rk = 5718, + X86_VFMSUB231PDZ256rkz = 5719, + X86_VFMSUB231PDZm = 5720, + X86_VFMSUB231PDZmb = 5721, + X86_VFMSUB231PDZmbk = 5722, + X86_VFMSUB231PDZmbkz = 5723, + X86_VFMSUB231PDZmk = 5724, + X86_VFMSUB231PDZmkz = 5725, + X86_VFMSUB231PDZr = 5726, + X86_VFMSUB231PDZrb = 5727, + X86_VFMSUB231PDZrbk = 5728, + X86_VFMSUB231PDZrbkz = 5729, + X86_VFMSUB231PDZrk = 5730, + X86_VFMSUB231PDZrkz = 5731, + X86_VFMSUB231PDm = 5732, + X86_VFMSUB231PDr = 5733, + X86_VFMSUB231PSYm = 5734, + X86_VFMSUB231PSYr = 5735, + X86_VFMSUB231PSZ128m = 5736, + X86_VFMSUB231PSZ128mb = 5737, + X86_VFMSUB231PSZ128mbk = 5738, + X86_VFMSUB231PSZ128mbkz = 5739, + X86_VFMSUB231PSZ128mk = 5740, + X86_VFMSUB231PSZ128mkz = 5741, + X86_VFMSUB231PSZ128r = 5742, + X86_VFMSUB231PSZ128rk = 5743, + X86_VFMSUB231PSZ128rkz = 5744, + X86_VFMSUB231PSZ256m = 5745, + X86_VFMSUB231PSZ256mb = 5746, + X86_VFMSUB231PSZ256mbk = 5747, + X86_VFMSUB231PSZ256mbkz = 5748, + X86_VFMSUB231PSZ256mk = 5749, + X86_VFMSUB231PSZ256mkz = 5750, + X86_VFMSUB231PSZ256r = 5751, + X86_VFMSUB231PSZ256rk = 5752, + X86_VFMSUB231PSZ256rkz = 5753, + X86_VFMSUB231PSZm = 5754, + X86_VFMSUB231PSZmb = 5755, + X86_VFMSUB231PSZmbk = 5756, + X86_VFMSUB231PSZmbkz = 5757, + X86_VFMSUB231PSZmk = 5758, + X86_VFMSUB231PSZmkz = 5759, + X86_VFMSUB231PSZr = 5760, + X86_VFMSUB231PSZrb = 5761, + X86_VFMSUB231PSZrbk = 5762, + X86_VFMSUB231PSZrbkz = 5763, + X86_VFMSUB231PSZrk = 5764, + X86_VFMSUB231PSZrkz = 5765, + X86_VFMSUB231PSm = 5766, + X86_VFMSUB231PSr = 5767, + X86_VFMSUB231SDZm = 5768, + X86_VFMSUB231SDZm_Int = 5769, + X86_VFMSUB231SDZm_Intk = 5770, + X86_VFMSUB231SDZm_Intkz = 5771, + X86_VFMSUB231SDZr = 5772, + X86_VFMSUB231SDZr_Int = 5773, + X86_VFMSUB231SDZr_Intk = 5774, + X86_VFMSUB231SDZr_Intkz = 5775, + X86_VFMSUB231SDZrb = 5776, + X86_VFMSUB231SDZrb_Int = 5777, + X86_VFMSUB231SDZrb_Intk = 5778, + X86_VFMSUB231SDZrb_Intkz = 5779, + X86_VFMSUB231SDm = 5780, + X86_VFMSUB231SDm_Int = 5781, + X86_VFMSUB231SDr = 5782, + X86_VFMSUB231SDr_Int = 5783, + X86_VFMSUB231SSZm = 5784, + X86_VFMSUB231SSZm_Int = 5785, + X86_VFMSUB231SSZm_Intk = 5786, + X86_VFMSUB231SSZm_Intkz = 5787, + X86_VFMSUB231SSZr = 5788, + X86_VFMSUB231SSZr_Int = 5789, + X86_VFMSUB231SSZr_Intk = 5790, + X86_VFMSUB231SSZr_Intkz = 5791, + X86_VFMSUB231SSZrb = 5792, + X86_VFMSUB231SSZrb_Int = 5793, + X86_VFMSUB231SSZrb_Intk = 5794, + X86_VFMSUB231SSZrb_Intkz = 5795, + X86_VFMSUB231SSm = 5796, + X86_VFMSUB231SSm_Int = 5797, + X86_VFMSUB231SSr = 5798, + X86_VFMSUB231SSr_Int = 5799, + X86_VFMSUBADD132PDYm = 5800, + X86_VFMSUBADD132PDYr = 5801, + X86_VFMSUBADD132PDZ128m = 5802, + X86_VFMSUBADD132PDZ128mb = 5803, + X86_VFMSUBADD132PDZ128mbk = 5804, + X86_VFMSUBADD132PDZ128mbkz = 5805, + X86_VFMSUBADD132PDZ128mk = 5806, + X86_VFMSUBADD132PDZ128mkz = 5807, + X86_VFMSUBADD132PDZ128r = 5808, + X86_VFMSUBADD132PDZ128rk = 5809, + X86_VFMSUBADD132PDZ128rkz = 5810, + X86_VFMSUBADD132PDZ256m = 5811, + X86_VFMSUBADD132PDZ256mb = 5812, + X86_VFMSUBADD132PDZ256mbk = 5813, + X86_VFMSUBADD132PDZ256mbkz = 5814, + X86_VFMSUBADD132PDZ256mk = 5815, + X86_VFMSUBADD132PDZ256mkz = 5816, + X86_VFMSUBADD132PDZ256r = 5817, + X86_VFMSUBADD132PDZ256rk = 5818, + X86_VFMSUBADD132PDZ256rkz = 5819, + X86_VFMSUBADD132PDZm = 5820, + X86_VFMSUBADD132PDZmb = 5821, + X86_VFMSUBADD132PDZmbk = 5822, + X86_VFMSUBADD132PDZmbkz = 5823, + X86_VFMSUBADD132PDZmk = 5824, + X86_VFMSUBADD132PDZmkz = 5825, + X86_VFMSUBADD132PDZr = 5826, + X86_VFMSUBADD132PDZrb = 5827, + X86_VFMSUBADD132PDZrbk = 5828, + X86_VFMSUBADD132PDZrbkz = 5829, + X86_VFMSUBADD132PDZrk = 5830, + X86_VFMSUBADD132PDZrkz = 5831, + X86_VFMSUBADD132PDm = 5832, + X86_VFMSUBADD132PDr = 5833, + X86_VFMSUBADD132PSYm = 5834, + X86_VFMSUBADD132PSYr = 5835, + X86_VFMSUBADD132PSZ128m = 5836, + X86_VFMSUBADD132PSZ128mb = 5837, + X86_VFMSUBADD132PSZ128mbk = 5838, + X86_VFMSUBADD132PSZ128mbkz = 5839, + X86_VFMSUBADD132PSZ128mk = 5840, + X86_VFMSUBADD132PSZ128mkz = 5841, + X86_VFMSUBADD132PSZ128r = 5842, + X86_VFMSUBADD132PSZ128rk = 5843, + X86_VFMSUBADD132PSZ128rkz = 5844, + X86_VFMSUBADD132PSZ256m = 5845, + X86_VFMSUBADD132PSZ256mb = 5846, + X86_VFMSUBADD132PSZ256mbk = 5847, + X86_VFMSUBADD132PSZ256mbkz = 5848, + X86_VFMSUBADD132PSZ256mk = 5849, + X86_VFMSUBADD132PSZ256mkz = 5850, + X86_VFMSUBADD132PSZ256r = 5851, + X86_VFMSUBADD132PSZ256rk = 5852, + X86_VFMSUBADD132PSZ256rkz = 5853, + X86_VFMSUBADD132PSZm = 5854, + X86_VFMSUBADD132PSZmb = 5855, + X86_VFMSUBADD132PSZmbk = 5856, + X86_VFMSUBADD132PSZmbkz = 5857, + X86_VFMSUBADD132PSZmk = 5858, + X86_VFMSUBADD132PSZmkz = 5859, + X86_VFMSUBADD132PSZr = 5860, + X86_VFMSUBADD132PSZrb = 5861, + X86_VFMSUBADD132PSZrbk = 5862, + X86_VFMSUBADD132PSZrbkz = 5863, + X86_VFMSUBADD132PSZrk = 5864, + X86_VFMSUBADD132PSZrkz = 5865, + X86_VFMSUBADD132PSm = 5866, + X86_VFMSUBADD132PSr = 5867, + X86_VFMSUBADD213PDYm = 5868, + X86_VFMSUBADD213PDYr = 5869, + X86_VFMSUBADD213PDZ128m = 5870, + X86_VFMSUBADD213PDZ128mb = 5871, + X86_VFMSUBADD213PDZ128mbk = 5872, + X86_VFMSUBADD213PDZ128mbkz = 5873, + X86_VFMSUBADD213PDZ128mk = 5874, + X86_VFMSUBADD213PDZ128mkz = 5875, + X86_VFMSUBADD213PDZ128r = 5876, + X86_VFMSUBADD213PDZ128rk = 5877, + X86_VFMSUBADD213PDZ128rkz = 5878, + X86_VFMSUBADD213PDZ256m = 5879, + X86_VFMSUBADD213PDZ256mb = 5880, + X86_VFMSUBADD213PDZ256mbk = 5881, + X86_VFMSUBADD213PDZ256mbkz = 5882, + X86_VFMSUBADD213PDZ256mk = 5883, + X86_VFMSUBADD213PDZ256mkz = 5884, + X86_VFMSUBADD213PDZ256r = 5885, + X86_VFMSUBADD213PDZ256rk = 5886, + X86_VFMSUBADD213PDZ256rkz = 5887, + X86_VFMSUBADD213PDZm = 5888, + X86_VFMSUBADD213PDZmb = 5889, + X86_VFMSUBADD213PDZmbk = 5890, + X86_VFMSUBADD213PDZmbkz = 5891, + X86_VFMSUBADD213PDZmk = 5892, + X86_VFMSUBADD213PDZmkz = 5893, + X86_VFMSUBADD213PDZr = 5894, + X86_VFMSUBADD213PDZrb = 5895, + X86_VFMSUBADD213PDZrbk = 5896, + X86_VFMSUBADD213PDZrbkz = 5897, + X86_VFMSUBADD213PDZrk = 5898, + X86_VFMSUBADD213PDZrkz = 5899, + X86_VFMSUBADD213PDm = 5900, + X86_VFMSUBADD213PDr = 5901, + X86_VFMSUBADD213PSYm = 5902, + X86_VFMSUBADD213PSYr = 5903, + X86_VFMSUBADD213PSZ128m = 5904, + X86_VFMSUBADD213PSZ128mb = 5905, + X86_VFMSUBADD213PSZ128mbk = 5906, + X86_VFMSUBADD213PSZ128mbkz = 5907, + X86_VFMSUBADD213PSZ128mk = 5908, + X86_VFMSUBADD213PSZ128mkz = 5909, + X86_VFMSUBADD213PSZ128r = 5910, + X86_VFMSUBADD213PSZ128rk = 5911, + X86_VFMSUBADD213PSZ128rkz = 5912, + X86_VFMSUBADD213PSZ256m = 5913, + X86_VFMSUBADD213PSZ256mb = 5914, + X86_VFMSUBADD213PSZ256mbk = 5915, + X86_VFMSUBADD213PSZ256mbkz = 5916, + X86_VFMSUBADD213PSZ256mk = 5917, + X86_VFMSUBADD213PSZ256mkz = 5918, + X86_VFMSUBADD213PSZ256r = 5919, + X86_VFMSUBADD213PSZ256rk = 5920, + X86_VFMSUBADD213PSZ256rkz = 5921, + X86_VFMSUBADD213PSZm = 5922, + X86_VFMSUBADD213PSZmb = 5923, + X86_VFMSUBADD213PSZmbk = 5924, + X86_VFMSUBADD213PSZmbkz = 5925, + X86_VFMSUBADD213PSZmk = 5926, + X86_VFMSUBADD213PSZmkz = 5927, + X86_VFMSUBADD213PSZr = 5928, + X86_VFMSUBADD213PSZrb = 5929, + X86_VFMSUBADD213PSZrbk = 5930, + X86_VFMSUBADD213PSZrbkz = 5931, + X86_VFMSUBADD213PSZrk = 5932, + X86_VFMSUBADD213PSZrkz = 5933, + X86_VFMSUBADD213PSm = 5934, + X86_VFMSUBADD213PSr = 5935, + X86_VFMSUBADD231PDYm = 5936, + X86_VFMSUBADD231PDYr = 5937, + X86_VFMSUBADD231PDZ128m = 5938, + X86_VFMSUBADD231PDZ128mb = 5939, + X86_VFMSUBADD231PDZ128mbk = 5940, + X86_VFMSUBADD231PDZ128mbkz = 5941, + X86_VFMSUBADD231PDZ128mk = 5942, + X86_VFMSUBADD231PDZ128mkz = 5943, + X86_VFMSUBADD231PDZ128r = 5944, + X86_VFMSUBADD231PDZ128rk = 5945, + X86_VFMSUBADD231PDZ128rkz = 5946, + X86_VFMSUBADD231PDZ256m = 5947, + X86_VFMSUBADD231PDZ256mb = 5948, + X86_VFMSUBADD231PDZ256mbk = 5949, + X86_VFMSUBADD231PDZ256mbkz = 5950, + X86_VFMSUBADD231PDZ256mk = 5951, + X86_VFMSUBADD231PDZ256mkz = 5952, + X86_VFMSUBADD231PDZ256r = 5953, + X86_VFMSUBADD231PDZ256rk = 5954, + X86_VFMSUBADD231PDZ256rkz = 5955, + X86_VFMSUBADD231PDZm = 5956, + X86_VFMSUBADD231PDZmb = 5957, + X86_VFMSUBADD231PDZmbk = 5958, + X86_VFMSUBADD231PDZmbkz = 5959, + X86_VFMSUBADD231PDZmk = 5960, + X86_VFMSUBADD231PDZmkz = 5961, + X86_VFMSUBADD231PDZr = 5962, + X86_VFMSUBADD231PDZrb = 5963, + X86_VFMSUBADD231PDZrbk = 5964, + X86_VFMSUBADD231PDZrbkz = 5965, + X86_VFMSUBADD231PDZrk = 5966, + X86_VFMSUBADD231PDZrkz = 5967, + X86_VFMSUBADD231PDm = 5968, + X86_VFMSUBADD231PDr = 5969, + X86_VFMSUBADD231PSYm = 5970, + X86_VFMSUBADD231PSYr = 5971, + X86_VFMSUBADD231PSZ128m = 5972, + X86_VFMSUBADD231PSZ128mb = 5973, + X86_VFMSUBADD231PSZ128mbk = 5974, + X86_VFMSUBADD231PSZ128mbkz = 5975, + X86_VFMSUBADD231PSZ128mk = 5976, + X86_VFMSUBADD231PSZ128mkz = 5977, + X86_VFMSUBADD231PSZ128r = 5978, + X86_VFMSUBADD231PSZ128rk = 5979, + X86_VFMSUBADD231PSZ128rkz = 5980, + X86_VFMSUBADD231PSZ256m = 5981, + X86_VFMSUBADD231PSZ256mb = 5982, + X86_VFMSUBADD231PSZ256mbk = 5983, + X86_VFMSUBADD231PSZ256mbkz = 5984, + X86_VFMSUBADD231PSZ256mk = 5985, + X86_VFMSUBADD231PSZ256mkz = 5986, + X86_VFMSUBADD231PSZ256r = 5987, + X86_VFMSUBADD231PSZ256rk = 5988, + X86_VFMSUBADD231PSZ256rkz = 5989, + X86_VFMSUBADD231PSZm = 5990, + X86_VFMSUBADD231PSZmb = 5991, + X86_VFMSUBADD231PSZmbk = 5992, + X86_VFMSUBADD231PSZmbkz = 5993, + X86_VFMSUBADD231PSZmk = 5994, + X86_VFMSUBADD231PSZmkz = 5995, + X86_VFMSUBADD231PSZr = 5996, + X86_VFMSUBADD231PSZrb = 5997, + X86_VFMSUBADD231PSZrbk = 5998, + X86_VFMSUBADD231PSZrbkz = 5999, + X86_VFMSUBADD231PSZrk = 6000, + X86_VFMSUBADD231PSZrkz = 6001, + X86_VFMSUBADD231PSm = 6002, + X86_VFMSUBADD231PSr = 6003, + X86_VFMSUBADDPD4Ymr = 6004, + X86_VFMSUBADDPD4Yrm = 6005, + X86_VFMSUBADDPD4Yrr = 6006, + X86_VFMSUBADDPD4Yrr_REV = 6007, + X86_VFMSUBADDPD4mr = 6008, + X86_VFMSUBADDPD4rm = 6009, + X86_VFMSUBADDPD4rr = 6010, + X86_VFMSUBADDPD4rr_REV = 6011, + X86_VFMSUBADDPS4Ymr = 6012, + X86_VFMSUBADDPS4Yrm = 6013, + X86_VFMSUBADDPS4Yrr = 6014, + X86_VFMSUBADDPS4Yrr_REV = 6015, + X86_VFMSUBADDPS4mr = 6016, + X86_VFMSUBADDPS4rm = 6017, + X86_VFMSUBADDPS4rr = 6018, + X86_VFMSUBADDPS4rr_REV = 6019, + X86_VFMSUBPD4Ymr = 6020, + X86_VFMSUBPD4Yrm = 6021, + X86_VFMSUBPD4Yrr = 6022, + X86_VFMSUBPD4Yrr_REV = 6023, + X86_VFMSUBPD4mr = 6024, + X86_VFMSUBPD4rm = 6025, + X86_VFMSUBPD4rr = 6026, + X86_VFMSUBPD4rr_REV = 6027, + X86_VFMSUBPS4Ymr = 6028, + X86_VFMSUBPS4Yrm = 6029, + X86_VFMSUBPS4Yrr = 6030, + X86_VFMSUBPS4Yrr_REV = 6031, + X86_VFMSUBPS4mr = 6032, + X86_VFMSUBPS4rm = 6033, + X86_VFMSUBPS4rr = 6034, + X86_VFMSUBPS4rr_REV = 6035, + X86_VFMSUBSD4mr = 6036, + X86_VFMSUBSD4mr_Int = 6037, + X86_VFMSUBSD4rm = 6038, + X86_VFMSUBSD4rm_Int = 6039, + X86_VFMSUBSD4rr = 6040, + X86_VFMSUBSD4rr_Int = 6041, + X86_VFMSUBSD4rr_Int_REV = 6042, + X86_VFMSUBSD4rr_REV = 6043, + X86_VFMSUBSS4mr = 6044, + X86_VFMSUBSS4mr_Int = 6045, + X86_VFMSUBSS4rm = 6046, + X86_VFMSUBSS4rm_Int = 6047, + X86_VFMSUBSS4rr = 6048, + X86_VFMSUBSS4rr_Int = 6049, + X86_VFMSUBSS4rr_Int_REV = 6050, + X86_VFMSUBSS4rr_REV = 6051, + X86_VFNMADD132PDYm = 6052, + X86_VFNMADD132PDYr = 6053, + X86_VFNMADD132PDZ128m = 6054, + X86_VFNMADD132PDZ128mb = 6055, + X86_VFNMADD132PDZ128mbk = 6056, + X86_VFNMADD132PDZ128mbkz = 6057, + X86_VFNMADD132PDZ128mk = 6058, + X86_VFNMADD132PDZ128mkz = 6059, + X86_VFNMADD132PDZ128r = 6060, + X86_VFNMADD132PDZ128rk = 6061, + X86_VFNMADD132PDZ128rkz = 6062, + X86_VFNMADD132PDZ256m = 6063, + X86_VFNMADD132PDZ256mb = 6064, + X86_VFNMADD132PDZ256mbk = 6065, + X86_VFNMADD132PDZ256mbkz = 6066, + X86_VFNMADD132PDZ256mk = 6067, + X86_VFNMADD132PDZ256mkz = 6068, + X86_VFNMADD132PDZ256r = 6069, + X86_VFNMADD132PDZ256rk = 6070, + X86_VFNMADD132PDZ256rkz = 6071, + X86_VFNMADD132PDZm = 6072, + X86_VFNMADD132PDZmb = 6073, + X86_VFNMADD132PDZmbk = 6074, + X86_VFNMADD132PDZmbkz = 6075, + X86_VFNMADD132PDZmk = 6076, + X86_VFNMADD132PDZmkz = 6077, + X86_VFNMADD132PDZr = 6078, + X86_VFNMADD132PDZrb = 6079, + X86_VFNMADD132PDZrbk = 6080, + X86_VFNMADD132PDZrbkz = 6081, + X86_VFNMADD132PDZrk = 6082, + X86_VFNMADD132PDZrkz = 6083, + X86_VFNMADD132PDm = 6084, + X86_VFNMADD132PDr = 6085, + X86_VFNMADD132PSYm = 6086, + X86_VFNMADD132PSYr = 6087, + X86_VFNMADD132PSZ128m = 6088, + X86_VFNMADD132PSZ128mb = 6089, + X86_VFNMADD132PSZ128mbk = 6090, + X86_VFNMADD132PSZ128mbkz = 6091, + X86_VFNMADD132PSZ128mk = 6092, + X86_VFNMADD132PSZ128mkz = 6093, + X86_VFNMADD132PSZ128r = 6094, + X86_VFNMADD132PSZ128rk = 6095, + X86_VFNMADD132PSZ128rkz = 6096, + X86_VFNMADD132PSZ256m = 6097, + X86_VFNMADD132PSZ256mb = 6098, + X86_VFNMADD132PSZ256mbk = 6099, + X86_VFNMADD132PSZ256mbkz = 6100, + X86_VFNMADD132PSZ256mk = 6101, + X86_VFNMADD132PSZ256mkz = 6102, + X86_VFNMADD132PSZ256r = 6103, + X86_VFNMADD132PSZ256rk = 6104, + X86_VFNMADD132PSZ256rkz = 6105, + X86_VFNMADD132PSZm = 6106, + X86_VFNMADD132PSZmb = 6107, + X86_VFNMADD132PSZmbk = 6108, + X86_VFNMADD132PSZmbkz = 6109, + X86_VFNMADD132PSZmk = 6110, + X86_VFNMADD132PSZmkz = 6111, + X86_VFNMADD132PSZr = 6112, + X86_VFNMADD132PSZrb = 6113, + X86_VFNMADD132PSZrbk = 6114, + X86_VFNMADD132PSZrbkz = 6115, + X86_VFNMADD132PSZrk = 6116, + X86_VFNMADD132PSZrkz = 6117, + X86_VFNMADD132PSm = 6118, + X86_VFNMADD132PSr = 6119, + X86_VFNMADD132SDZm = 6120, + X86_VFNMADD132SDZm_Int = 6121, + X86_VFNMADD132SDZm_Intk = 6122, + X86_VFNMADD132SDZm_Intkz = 6123, + X86_VFNMADD132SDZr = 6124, + X86_VFNMADD132SDZr_Int = 6125, + X86_VFNMADD132SDZr_Intk = 6126, + X86_VFNMADD132SDZr_Intkz = 6127, + X86_VFNMADD132SDZrb = 6128, + X86_VFNMADD132SDZrb_Int = 6129, + X86_VFNMADD132SDZrb_Intk = 6130, + X86_VFNMADD132SDZrb_Intkz = 6131, + X86_VFNMADD132SDm = 6132, + X86_VFNMADD132SDm_Int = 6133, + X86_VFNMADD132SDr = 6134, + X86_VFNMADD132SDr_Int = 6135, + X86_VFNMADD132SSZm = 6136, + X86_VFNMADD132SSZm_Int = 6137, + X86_VFNMADD132SSZm_Intk = 6138, + X86_VFNMADD132SSZm_Intkz = 6139, + X86_VFNMADD132SSZr = 6140, + X86_VFNMADD132SSZr_Int = 6141, + X86_VFNMADD132SSZr_Intk = 6142, + X86_VFNMADD132SSZr_Intkz = 6143, + X86_VFNMADD132SSZrb = 6144, + X86_VFNMADD132SSZrb_Int = 6145, + X86_VFNMADD132SSZrb_Intk = 6146, + X86_VFNMADD132SSZrb_Intkz = 6147, + X86_VFNMADD132SSm = 6148, + X86_VFNMADD132SSm_Int = 6149, + X86_VFNMADD132SSr = 6150, + X86_VFNMADD132SSr_Int = 6151, + X86_VFNMADD213PDYm = 6152, + X86_VFNMADD213PDYr = 6153, + X86_VFNMADD213PDZ128m = 6154, + X86_VFNMADD213PDZ128mb = 6155, + X86_VFNMADD213PDZ128mbk = 6156, + X86_VFNMADD213PDZ128mbkz = 6157, + X86_VFNMADD213PDZ128mk = 6158, + X86_VFNMADD213PDZ128mkz = 6159, + X86_VFNMADD213PDZ128r = 6160, + X86_VFNMADD213PDZ128rk = 6161, + X86_VFNMADD213PDZ128rkz = 6162, + X86_VFNMADD213PDZ256m = 6163, + X86_VFNMADD213PDZ256mb = 6164, + X86_VFNMADD213PDZ256mbk = 6165, + X86_VFNMADD213PDZ256mbkz = 6166, + X86_VFNMADD213PDZ256mk = 6167, + X86_VFNMADD213PDZ256mkz = 6168, + X86_VFNMADD213PDZ256r = 6169, + X86_VFNMADD213PDZ256rk = 6170, + X86_VFNMADD213PDZ256rkz = 6171, + X86_VFNMADD213PDZm = 6172, + X86_VFNMADD213PDZmb = 6173, + X86_VFNMADD213PDZmbk = 6174, + X86_VFNMADD213PDZmbkz = 6175, + X86_VFNMADD213PDZmk = 6176, + X86_VFNMADD213PDZmkz = 6177, + X86_VFNMADD213PDZr = 6178, + X86_VFNMADD213PDZrb = 6179, + X86_VFNMADD213PDZrbk = 6180, + X86_VFNMADD213PDZrbkz = 6181, + X86_VFNMADD213PDZrk = 6182, + X86_VFNMADD213PDZrkz = 6183, + X86_VFNMADD213PDm = 6184, + X86_VFNMADD213PDr = 6185, + X86_VFNMADD213PSYm = 6186, + X86_VFNMADD213PSYr = 6187, + X86_VFNMADD213PSZ128m = 6188, + X86_VFNMADD213PSZ128mb = 6189, + X86_VFNMADD213PSZ128mbk = 6190, + X86_VFNMADD213PSZ128mbkz = 6191, + X86_VFNMADD213PSZ128mk = 6192, + X86_VFNMADD213PSZ128mkz = 6193, + X86_VFNMADD213PSZ128r = 6194, + X86_VFNMADD213PSZ128rk = 6195, + X86_VFNMADD213PSZ128rkz = 6196, + X86_VFNMADD213PSZ256m = 6197, + X86_VFNMADD213PSZ256mb = 6198, + X86_VFNMADD213PSZ256mbk = 6199, + X86_VFNMADD213PSZ256mbkz = 6200, + X86_VFNMADD213PSZ256mk = 6201, + X86_VFNMADD213PSZ256mkz = 6202, + X86_VFNMADD213PSZ256r = 6203, + X86_VFNMADD213PSZ256rk = 6204, + X86_VFNMADD213PSZ256rkz = 6205, + X86_VFNMADD213PSZm = 6206, + X86_VFNMADD213PSZmb = 6207, + X86_VFNMADD213PSZmbk = 6208, + X86_VFNMADD213PSZmbkz = 6209, + X86_VFNMADD213PSZmk = 6210, + X86_VFNMADD213PSZmkz = 6211, + X86_VFNMADD213PSZr = 6212, + X86_VFNMADD213PSZrb = 6213, + X86_VFNMADD213PSZrbk = 6214, + X86_VFNMADD213PSZrbkz = 6215, + X86_VFNMADD213PSZrk = 6216, + X86_VFNMADD213PSZrkz = 6217, + X86_VFNMADD213PSm = 6218, + X86_VFNMADD213PSr = 6219, + X86_VFNMADD213SDZm = 6220, + X86_VFNMADD213SDZm_Int = 6221, + X86_VFNMADD213SDZm_Intk = 6222, + X86_VFNMADD213SDZm_Intkz = 6223, + X86_VFNMADD213SDZr = 6224, + X86_VFNMADD213SDZr_Int = 6225, + X86_VFNMADD213SDZr_Intk = 6226, + X86_VFNMADD213SDZr_Intkz = 6227, + X86_VFNMADD213SDZrb = 6228, + X86_VFNMADD213SDZrb_Int = 6229, + X86_VFNMADD213SDZrb_Intk = 6230, + X86_VFNMADD213SDZrb_Intkz = 6231, + X86_VFNMADD213SDm = 6232, + X86_VFNMADD213SDm_Int = 6233, + X86_VFNMADD213SDr = 6234, + X86_VFNMADD213SDr_Int = 6235, + X86_VFNMADD213SSZm = 6236, + X86_VFNMADD213SSZm_Int = 6237, + X86_VFNMADD213SSZm_Intk = 6238, + X86_VFNMADD213SSZm_Intkz = 6239, + X86_VFNMADD213SSZr = 6240, + X86_VFNMADD213SSZr_Int = 6241, + X86_VFNMADD213SSZr_Intk = 6242, + X86_VFNMADD213SSZr_Intkz = 6243, + X86_VFNMADD213SSZrb = 6244, + X86_VFNMADD213SSZrb_Int = 6245, + X86_VFNMADD213SSZrb_Intk = 6246, + X86_VFNMADD213SSZrb_Intkz = 6247, + X86_VFNMADD213SSm = 6248, + X86_VFNMADD213SSm_Int = 6249, + X86_VFNMADD213SSr = 6250, + X86_VFNMADD213SSr_Int = 6251, + X86_VFNMADD231PDYm = 6252, + X86_VFNMADD231PDYr = 6253, + X86_VFNMADD231PDZ128m = 6254, + X86_VFNMADD231PDZ128mb = 6255, + X86_VFNMADD231PDZ128mbk = 6256, + X86_VFNMADD231PDZ128mbkz = 6257, + X86_VFNMADD231PDZ128mk = 6258, + X86_VFNMADD231PDZ128mkz = 6259, + X86_VFNMADD231PDZ128r = 6260, + X86_VFNMADD231PDZ128rk = 6261, + X86_VFNMADD231PDZ128rkz = 6262, + X86_VFNMADD231PDZ256m = 6263, + X86_VFNMADD231PDZ256mb = 6264, + X86_VFNMADD231PDZ256mbk = 6265, + X86_VFNMADD231PDZ256mbkz = 6266, + X86_VFNMADD231PDZ256mk = 6267, + X86_VFNMADD231PDZ256mkz = 6268, + X86_VFNMADD231PDZ256r = 6269, + X86_VFNMADD231PDZ256rk = 6270, + X86_VFNMADD231PDZ256rkz = 6271, + X86_VFNMADD231PDZm = 6272, + X86_VFNMADD231PDZmb = 6273, + X86_VFNMADD231PDZmbk = 6274, + X86_VFNMADD231PDZmbkz = 6275, + X86_VFNMADD231PDZmk = 6276, + X86_VFNMADD231PDZmkz = 6277, + X86_VFNMADD231PDZr = 6278, + X86_VFNMADD231PDZrb = 6279, + X86_VFNMADD231PDZrbk = 6280, + X86_VFNMADD231PDZrbkz = 6281, + X86_VFNMADD231PDZrk = 6282, + X86_VFNMADD231PDZrkz = 6283, + X86_VFNMADD231PDm = 6284, + X86_VFNMADD231PDr = 6285, + X86_VFNMADD231PSYm = 6286, + X86_VFNMADD231PSYr = 6287, + X86_VFNMADD231PSZ128m = 6288, + X86_VFNMADD231PSZ128mb = 6289, + X86_VFNMADD231PSZ128mbk = 6290, + X86_VFNMADD231PSZ128mbkz = 6291, + X86_VFNMADD231PSZ128mk = 6292, + X86_VFNMADD231PSZ128mkz = 6293, + X86_VFNMADD231PSZ128r = 6294, + X86_VFNMADD231PSZ128rk = 6295, + X86_VFNMADD231PSZ128rkz = 6296, + X86_VFNMADD231PSZ256m = 6297, + X86_VFNMADD231PSZ256mb = 6298, + X86_VFNMADD231PSZ256mbk = 6299, + X86_VFNMADD231PSZ256mbkz = 6300, + X86_VFNMADD231PSZ256mk = 6301, + X86_VFNMADD231PSZ256mkz = 6302, + X86_VFNMADD231PSZ256r = 6303, + X86_VFNMADD231PSZ256rk = 6304, + X86_VFNMADD231PSZ256rkz = 6305, + X86_VFNMADD231PSZm = 6306, + X86_VFNMADD231PSZmb = 6307, + X86_VFNMADD231PSZmbk = 6308, + X86_VFNMADD231PSZmbkz = 6309, + X86_VFNMADD231PSZmk = 6310, + X86_VFNMADD231PSZmkz = 6311, + X86_VFNMADD231PSZr = 6312, + X86_VFNMADD231PSZrb = 6313, + X86_VFNMADD231PSZrbk = 6314, + X86_VFNMADD231PSZrbkz = 6315, + X86_VFNMADD231PSZrk = 6316, + X86_VFNMADD231PSZrkz = 6317, + X86_VFNMADD231PSm = 6318, + X86_VFNMADD231PSr = 6319, + X86_VFNMADD231SDZm = 6320, + X86_VFNMADD231SDZm_Int = 6321, + X86_VFNMADD231SDZm_Intk = 6322, + X86_VFNMADD231SDZm_Intkz = 6323, + X86_VFNMADD231SDZr = 6324, + X86_VFNMADD231SDZr_Int = 6325, + X86_VFNMADD231SDZr_Intk = 6326, + X86_VFNMADD231SDZr_Intkz = 6327, + X86_VFNMADD231SDZrb = 6328, + X86_VFNMADD231SDZrb_Int = 6329, + X86_VFNMADD231SDZrb_Intk = 6330, + X86_VFNMADD231SDZrb_Intkz = 6331, + X86_VFNMADD231SDm = 6332, + X86_VFNMADD231SDm_Int = 6333, + X86_VFNMADD231SDr = 6334, + X86_VFNMADD231SDr_Int = 6335, + X86_VFNMADD231SSZm = 6336, + X86_VFNMADD231SSZm_Int = 6337, + X86_VFNMADD231SSZm_Intk = 6338, + X86_VFNMADD231SSZm_Intkz = 6339, + X86_VFNMADD231SSZr = 6340, + X86_VFNMADD231SSZr_Int = 6341, + X86_VFNMADD231SSZr_Intk = 6342, + X86_VFNMADD231SSZr_Intkz = 6343, + X86_VFNMADD231SSZrb = 6344, + X86_VFNMADD231SSZrb_Int = 6345, + X86_VFNMADD231SSZrb_Intk = 6346, + X86_VFNMADD231SSZrb_Intkz = 6347, + X86_VFNMADD231SSm = 6348, + X86_VFNMADD231SSm_Int = 6349, + X86_VFNMADD231SSr = 6350, + X86_VFNMADD231SSr_Int = 6351, + X86_VFNMADDPD4Ymr = 6352, + X86_VFNMADDPD4Yrm = 6353, + X86_VFNMADDPD4Yrr = 6354, + X86_VFNMADDPD4Yrr_REV = 6355, + X86_VFNMADDPD4mr = 6356, + X86_VFNMADDPD4rm = 6357, + X86_VFNMADDPD4rr = 6358, + X86_VFNMADDPD4rr_REV = 6359, + X86_VFNMADDPS4Ymr = 6360, + X86_VFNMADDPS4Yrm = 6361, + X86_VFNMADDPS4Yrr = 6362, + X86_VFNMADDPS4Yrr_REV = 6363, + X86_VFNMADDPS4mr = 6364, + X86_VFNMADDPS4rm = 6365, + X86_VFNMADDPS4rr = 6366, + X86_VFNMADDPS4rr_REV = 6367, + X86_VFNMADDSD4mr = 6368, + X86_VFNMADDSD4mr_Int = 6369, + X86_VFNMADDSD4rm = 6370, + X86_VFNMADDSD4rm_Int = 6371, + X86_VFNMADDSD4rr = 6372, + X86_VFNMADDSD4rr_Int = 6373, + X86_VFNMADDSD4rr_Int_REV = 6374, + X86_VFNMADDSD4rr_REV = 6375, + X86_VFNMADDSS4mr = 6376, + X86_VFNMADDSS4mr_Int = 6377, + X86_VFNMADDSS4rm = 6378, + X86_VFNMADDSS4rm_Int = 6379, + X86_VFNMADDSS4rr = 6380, + X86_VFNMADDSS4rr_Int = 6381, + X86_VFNMADDSS4rr_Int_REV = 6382, + X86_VFNMADDSS4rr_REV = 6383, + X86_VFNMSUB132PDYm = 6384, + X86_VFNMSUB132PDYr = 6385, + X86_VFNMSUB132PDZ128m = 6386, + X86_VFNMSUB132PDZ128mb = 6387, + X86_VFNMSUB132PDZ128mbk = 6388, + X86_VFNMSUB132PDZ128mbkz = 6389, + X86_VFNMSUB132PDZ128mk = 6390, + X86_VFNMSUB132PDZ128mkz = 6391, + X86_VFNMSUB132PDZ128r = 6392, + X86_VFNMSUB132PDZ128rk = 6393, + X86_VFNMSUB132PDZ128rkz = 6394, + X86_VFNMSUB132PDZ256m = 6395, + X86_VFNMSUB132PDZ256mb = 6396, + X86_VFNMSUB132PDZ256mbk = 6397, + X86_VFNMSUB132PDZ256mbkz = 6398, + X86_VFNMSUB132PDZ256mk = 6399, + X86_VFNMSUB132PDZ256mkz = 6400, + X86_VFNMSUB132PDZ256r = 6401, + X86_VFNMSUB132PDZ256rk = 6402, + X86_VFNMSUB132PDZ256rkz = 6403, + X86_VFNMSUB132PDZm = 6404, + X86_VFNMSUB132PDZmb = 6405, + X86_VFNMSUB132PDZmbk = 6406, + X86_VFNMSUB132PDZmbkz = 6407, + X86_VFNMSUB132PDZmk = 6408, + X86_VFNMSUB132PDZmkz = 6409, + X86_VFNMSUB132PDZr = 6410, + X86_VFNMSUB132PDZrb = 6411, + X86_VFNMSUB132PDZrbk = 6412, + X86_VFNMSUB132PDZrbkz = 6413, + X86_VFNMSUB132PDZrk = 6414, + X86_VFNMSUB132PDZrkz = 6415, + X86_VFNMSUB132PDm = 6416, + X86_VFNMSUB132PDr = 6417, + X86_VFNMSUB132PSYm = 6418, + X86_VFNMSUB132PSYr = 6419, + X86_VFNMSUB132PSZ128m = 6420, + X86_VFNMSUB132PSZ128mb = 6421, + X86_VFNMSUB132PSZ128mbk = 6422, + X86_VFNMSUB132PSZ128mbkz = 6423, + X86_VFNMSUB132PSZ128mk = 6424, + X86_VFNMSUB132PSZ128mkz = 6425, + X86_VFNMSUB132PSZ128r = 6426, + X86_VFNMSUB132PSZ128rk = 6427, + X86_VFNMSUB132PSZ128rkz = 6428, + X86_VFNMSUB132PSZ256m = 6429, + X86_VFNMSUB132PSZ256mb = 6430, + X86_VFNMSUB132PSZ256mbk = 6431, + X86_VFNMSUB132PSZ256mbkz = 6432, + X86_VFNMSUB132PSZ256mk = 6433, + X86_VFNMSUB132PSZ256mkz = 6434, + X86_VFNMSUB132PSZ256r = 6435, + X86_VFNMSUB132PSZ256rk = 6436, + X86_VFNMSUB132PSZ256rkz = 6437, + X86_VFNMSUB132PSZm = 6438, + X86_VFNMSUB132PSZmb = 6439, + X86_VFNMSUB132PSZmbk = 6440, + X86_VFNMSUB132PSZmbkz = 6441, + X86_VFNMSUB132PSZmk = 6442, + X86_VFNMSUB132PSZmkz = 6443, + X86_VFNMSUB132PSZr = 6444, + X86_VFNMSUB132PSZrb = 6445, + X86_VFNMSUB132PSZrbk = 6446, + X86_VFNMSUB132PSZrbkz = 6447, + X86_VFNMSUB132PSZrk = 6448, + X86_VFNMSUB132PSZrkz = 6449, + X86_VFNMSUB132PSm = 6450, + X86_VFNMSUB132PSr = 6451, + X86_VFNMSUB132SDZm = 6452, + X86_VFNMSUB132SDZm_Int = 6453, + X86_VFNMSUB132SDZm_Intk = 6454, + X86_VFNMSUB132SDZm_Intkz = 6455, + X86_VFNMSUB132SDZr = 6456, + X86_VFNMSUB132SDZr_Int = 6457, + X86_VFNMSUB132SDZr_Intk = 6458, + X86_VFNMSUB132SDZr_Intkz = 6459, + X86_VFNMSUB132SDZrb = 6460, + X86_VFNMSUB132SDZrb_Int = 6461, + X86_VFNMSUB132SDZrb_Intk = 6462, + X86_VFNMSUB132SDZrb_Intkz = 6463, + X86_VFNMSUB132SDm = 6464, + X86_VFNMSUB132SDm_Int = 6465, + X86_VFNMSUB132SDr = 6466, + X86_VFNMSUB132SDr_Int = 6467, + X86_VFNMSUB132SSZm = 6468, + X86_VFNMSUB132SSZm_Int = 6469, + X86_VFNMSUB132SSZm_Intk = 6470, + X86_VFNMSUB132SSZm_Intkz = 6471, + X86_VFNMSUB132SSZr = 6472, + X86_VFNMSUB132SSZr_Int = 6473, + X86_VFNMSUB132SSZr_Intk = 6474, + X86_VFNMSUB132SSZr_Intkz = 6475, + X86_VFNMSUB132SSZrb = 6476, + X86_VFNMSUB132SSZrb_Int = 6477, + X86_VFNMSUB132SSZrb_Intk = 6478, + X86_VFNMSUB132SSZrb_Intkz = 6479, + X86_VFNMSUB132SSm = 6480, + X86_VFNMSUB132SSm_Int = 6481, + X86_VFNMSUB132SSr = 6482, + X86_VFNMSUB132SSr_Int = 6483, + X86_VFNMSUB213PDYm = 6484, + X86_VFNMSUB213PDYr = 6485, + X86_VFNMSUB213PDZ128m = 6486, + X86_VFNMSUB213PDZ128mb = 6487, + X86_VFNMSUB213PDZ128mbk = 6488, + X86_VFNMSUB213PDZ128mbkz = 6489, + X86_VFNMSUB213PDZ128mk = 6490, + X86_VFNMSUB213PDZ128mkz = 6491, + X86_VFNMSUB213PDZ128r = 6492, + X86_VFNMSUB213PDZ128rk = 6493, + X86_VFNMSUB213PDZ128rkz = 6494, + X86_VFNMSUB213PDZ256m = 6495, + X86_VFNMSUB213PDZ256mb = 6496, + X86_VFNMSUB213PDZ256mbk = 6497, + X86_VFNMSUB213PDZ256mbkz = 6498, + X86_VFNMSUB213PDZ256mk = 6499, + X86_VFNMSUB213PDZ256mkz = 6500, + X86_VFNMSUB213PDZ256r = 6501, + X86_VFNMSUB213PDZ256rk = 6502, + X86_VFNMSUB213PDZ256rkz = 6503, + X86_VFNMSUB213PDZm = 6504, + X86_VFNMSUB213PDZmb = 6505, + X86_VFNMSUB213PDZmbk = 6506, + X86_VFNMSUB213PDZmbkz = 6507, + X86_VFNMSUB213PDZmk = 6508, + X86_VFNMSUB213PDZmkz = 6509, + X86_VFNMSUB213PDZr = 6510, + X86_VFNMSUB213PDZrb = 6511, + X86_VFNMSUB213PDZrbk = 6512, + X86_VFNMSUB213PDZrbkz = 6513, + X86_VFNMSUB213PDZrk = 6514, + X86_VFNMSUB213PDZrkz = 6515, + X86_VFNMSUB213PDm = 6516, + X86_VFNMSUB213PDr = 6517, + X86_VFNMSUB213PSYm = 6518, + X86_VFNMSUB213PSYr = 6519, + X86_VFNMSUB213PSZ128m = 6520, + X86_VFNMSUB213PSZ128mb = 6521, + X86_VFNMSUB213PSZ128mbk = 6522, + X86_VFNMSUB213PSZ128mbkz = 6523, + X86_VFNMSUB213PSZ128mk = 6524, + X86_VFNMSUB213PSZ128mkz = 6525, + X86_VFNMSUB213PSZ128r = 6526, + X86_VFNMSUB213PSZ128rk = 6527, + X86_VFNMSUB213PSZ128rkz = 6528, + X86_VFNMSUB213PSZ256m = 6529, + X86_VFNMSUB213PSZ256mb = 6530, + X86_VFNMSUB213PSZ256mbk = 6531, + X86_VFNMSUB213PSZ256mbkz = 6532, + X86_VFNMSUB213PSZ256mk = 6533, + X86_VFNMSUB213PSZ256mkz = 6534, + X86_VFNMSUB213PSZ256r = 6535, + X86_VFNMSUB213PSZ256rk = 6536, + X86_VFNMSUB213PSZ256rkz = 6537, + X86_VFNMSUB213PSZm = 6538, + X86_VFNMSUB213PSZmb = 6539, + X86_VFNMSUB213PSZmbk = 6540, + X86_VFNMSUB213PSZmbkz = 6541, + X86_VFNMSUB213PSZmk = 6542, + X86_VFNMSUB213PSZmkz = 6543, + X86_VFNMSUB213PSZr = 6544, + X86_VFNMSUB213PSZrb = 6545, + X86_VFNMSUB213PSZrbk = 6546, + X86_VFNMSUB213PSZrbkz = 6547, + X86_VFNMSUB213PSZrk = 6548, + X86_VFNMSUB213PSZrkz = 6549, + X86_VFNMSUB213PSm = 6550, + X86_VFNMSUB213PSr = 6551, + X86_VFNMSUB213SDZm = 6552, + X86_VFNMSUB213SDZm_Int = 6553, + X86_VFNMSUB213SDZm_Intk = 6554, + X86_VFNMSUB213SDZm_Intkz = 6555, + X86_VFNMSUB213SDZr = 6556, + X86_VFNMSUB213SDZr_Int = 6557, + X86_VFNMSUB213SDZr_Intk = 6558, + X86_VFNMSUB213SDZr_Intkz = 6559, + X86_VFNMSUB213SDZrb = 6560, + X86_VFNMSUB213SDZrb_Int = 6561, + X86_VFNMSUB213SDZrb_Intk = 6562, + X86_VFNMSUB213SDZrb_Intkz = 6563, + X86_VFNMSUB213SDm = 6564, + X86_VFNMSUB213SDm_Int = 6565, + X86_VFNMSUB213SDr = 6566, + X86_VFNMSUB213SDr_Int = 6567, + X86_VFNMSUB213SSZm = 6568, + X86_VFNMSUB213SSZm_Int = 6569, + X86_VFNMSUB213SSZm_Intk = 6570, + X86_VFNMSUB213SSZm_Intkz = 6571, + X86_VFNMSUB213SSZr = 6572, + X86_VFNMSUB213SSZr_Int = 6573, + X86_VFNMSUB213SSZr_Intk = 6574, + X86_VFNMSUB213SSZr_Intkz = 6575, + X86_VFNMSUB213SSZrb = 6576, + X86_VFNMSUB213SSZrb_Int = 6577, + X86_VFNMSUB213SSZrb_Intk = 6578, + X86_VFNMSUB213SSZrb_Intkz = 6579, + X86_VFNMSUB213SSm = 6580, + X86_VFNMSUB213SSm_Int = 6581, + X86_VFNMSUB213SSr = 6582, + X86_VFNMSUB213SSr_Int = 6583, + X86_VFNMSUB231PDYm = 6584, + X86_VFNMSUB231PDYr = 6585, + X86_VFNMSUB231PDZ128m = 6586, + X86_VFNMSUB231PDZ128mb = 6587, + X86_VFNMSUB231PDZ128mbk = 6588, + X86_VFNMSUB231PDZ128mbkz = 6589, + X86_VFNMSUB231PDZ128mk = 6590, + X86_VFNMSUB231PDZ128mkz = 6591, + X86_VFNMSUB231PDZ128r = 6592, + X86_VFNMSUB231PDZ128rk = 6593, + X86_VFNMSUB231PDZ128rkz = 6594, + X86_VFNMSUB231PDZ256m = 6595, + X86_VFNMSUB231PDZ256mb = 6596, + X86_VFNMSUB231PDZ256mbk = 6597, + X86_VFNMSUB231PDZ256mbkz = 6598, + X86_VFNMSUB231PDZ256mk = 6599, + X86_VFNMSUB231PDZ256mkz = 6600, + X86_VFNMSUB231PDZ256r = 6601, + X86_VFNMSUB231PDZ256rk = 6602, + X86_VFNMSUB231PDZ256rkz = 6603, + X86_VFNMSUB231PDZm = 6604, + X86_VFNMSUB231PDZmb = 6605, + X86_VFNMSUB231PDZmbk = 6606, + X86_VFNMSUB231PDZmbkz = 6607, + X86_VFNMSUB231PDZmk = 6608, + X86_VFNMSUB231PDZmkz = 6609, + X86_VFNMSUB231PDZr = 6610, + X86_VFNMSUB231PDZrb = 6611, + X86_VFNMSUB231PDZrbk = 6612, + X86_VFNMSUB231PDZrbkz = 6613, + X86_VFNMSUB231PDZrk = 6614, + X86_VFNMSUB231PDZrkz = 6615, + X86_VFNMSUB231PDm = 6616, + X86_VFNMSUB231PDr = 6617, + X86_VFNMSUB231PSYm = 6618, + X86_VFNMSUB231PSYr = 6619, + X86_VFNMSUB231PSZ128m = 6620, + X86_VFNMSUB231PSZ128mb = 6621, + X86_VFNMSUB231PSZ128mbk = 6622, + X86_VFNMSUB231PSZ128mbkz = 6623, + X86_VFNMSUB231PSZ128mk = 6624, + X86_VFNMSUB231PSZ128mkz = 6625, + X86_VFNMSUB231PSZ128r = 6626, + X86_VFNMSUB231PSZ128rk = 6627, + X86_VFNMSUB231PSZ128rkz = 6628, + X86_VFNMSUB231PSZ256m = 6629, + X86_VFNMSUB231PSZ256mb = 6630, + X86_VFNMSUB231PSZ256mbk = 6631, + X86_VFNMSUB231PSZ256mbkz = 6632, + X86_VFNMSUB231PSZ256mk = 6633, + X86_VFNMSUB231PSZ256mkz = 6634, + X86_VFNMSUB231PSZ256r = 6635, + X86_VFNMSUB231PSZ256rk = 6636, + X86_VFNMSUB231PSZ256rkz = 6637, + X86_VFNMSUB231PSZm = 6638, + X86_VFNMSUB231PSZmb = 6639, + X86_VFNMSUB231PSZmbk = 6640, + X86_VFNMSUB231PSZmbkz = 6641, + X86_VFNMSUB231PSZmk = 6642, + X86_VFNMSUB231PSZmkz = 6643, + X86_VFNMSUB231PSZr = 6644, + X86_VFNMSUB231PSZrb = 6645, + X86_VFNMSUB231PSZrbk = 6646, + X86_VFNMSUB231PSZrbkz = 6647, + X86_VFNMSUB231PSZrk = 6648, + X86_VFNMSUB231PSZrkz = 6649, + X86_VFNMSUB231PSm = 6650, + X86_VFNMSUB231PSr = 6651, + X86_VFNMSUB231SDZm = 6652, + X86_VFNMSUB231SDZm_Int = 6653, + X86_VFNMSUB231SDZm_Intk = 6654, + X86_VFNMSUB231SDZm_Intkz = 6655, + X86_VFNMSUB231SDZr = 6656, + X86_VFNMSUB231SDZr_Int = 6657, + X86_VFNMSUB231SDZr_Intk = 6658, + X86_VFNMSUB231SDZr_Intkz = 6659, + X86_VFNMSUB231SDZrb = 6660, + X86_VFNMSUB231SDZrb_Int = 6661, + X86_VFNMSUB231SDZrb_Intk = 6662, + X86_VFNMSUB231SDZrb_Intkz = 6663, + X86_VFNMSUB231SDm = 6664, + X86_VFNMSUB231SDm_Int = 6665, + X86_VFNMSUB231SDr = 6666, + X86_VFNMSUB231SDr_Int = 6667, + X86_VFNMSUB231SSZm = 6668, + X86_VFNMSUB231SSZm_Int = 6669, + X86_VFNMSUB231SSZm_Intk = 6670, + X86_VFNMSUB231SSZm_Intkz = 6671, + X86_VFNMSUB231SSZr = 6672, + X86_VFNMSUB231SSZr_Int = 6673, + X86_VFNMSUB231SSZr_Intk = 6674, + X86_VFNMSUB231SSZr_Intkz = 6675, + X86_VFNMSUB231SSZrb = 6676, + X86_VFNMSUB231SSZrb_Int = 6677, + X86_VFNMSUB231SSZrb_Intk = 6678, + X86_VFNMSUB231SSZrb_Intkz = 6679, + X86_VFNMSUB231SSm = 6680, + X86_VFNMSUB231SSm_Int = 6681, + X86_VFNMSUB231SSr = 6682, + X86_VFNMSUB231SSr_Int = 6683, + X86_VFNMSUBPD4Ymr = 6684, + X86_VFNMSUBPD4Yrm = 6685, + X86_VFNMSUBPD4Yrr = 6686, + X86_VFNMSUBPD4Yrr_REV = 6687, + X86_VFNMSUBPD4mr = 6688, + X86_VFNMSUBPD4rm = 6689, + X86_VFNMSUBPD4rr = 6690, + X86_VFNMSUBPD4rr_REV = 6691, + X86_VFNMSUBPS4Ymr = 6692, + X86_VFNMSUBPS4Yrm = 6693, + X86_VFNMSUBPS4Yrr = 6694, + X86_VFNMSUBPS4Yrr_REV = 6695, + X86_VFNMSUBPS4mr = 6696, + X86_VFNMSUBPS4rm = 6697, + X86_VFNMSUBPS4rr = 6698, + X86_VFNMSUBPS4rr_REV = 6699, + X86_VFNMSUBSD4mr = 6700, + X86_VFNMSUBSD4mr_Int = 6701, + X86_VFNMSUBSD4rm = 6702, + X86_VFNMSUBSD4rm_Int = 6703, + X86_VFNMSUBSD4rr = 6704, + X86_VFNMSUBSD4rr_Int = 6705, + X86_VFNMSUBSD4rr_Int_REV = 6706, + X86_VFNMSUBSD4rr_REV = 6707, + X86_VFNMSUBSS4mr = 6708, + X86_VFNMSUBSS4mr_Int = 6709, + X86_VFNMSUBSS4rm = 6710, + X86_VFNMSUBSS4rm_Int = 6711, + X86_VFNMSUBSS4rr = 6712, + X86_VFNMSUBSS4rr_Int = 6713, + X86_VFNMSUBSS4rr_Int_REV = 6714, + X86_VFNMSUBSS4rr_REV = 6715, + X86_VFPCLASSPDZ128rm = 6716, + X86_VFPCLASSPDZ128rmb = 6717, + X86_VFPCLASSPDZ128rmbk = 6718, + X86_VFPCLASSPDZ128rmk = 6719, + X86_VFPCLASSPDZ128rr = 6720, + X86_VFPCLASSPDZ128rrk = 6721, + X86_VFPCLASSPDZ256rm = 6722, + X86_VFPCLASSPDZ256rmb = 6723, + X86_VFPCLASSPDZ256rmbk = 6724, + X86_VFPCLASSPDZ256rmk = 6725, + X86_VFPCLASSPDZ256rr = 6726, + X86_VFPCLASSPDZ256rrk = 6727, + X86_VFPCLASSPDZrm = 6728, + X86_VFPCLASSPDZrmb = 6729, + X86_VFPCLASSPDZrmbk = 6730, + X86_VFPCLASSPDZrmk = 6731, + X86_VFPCLASSPDZrr = 6732, + X86_VFPCLASSPDZrrk = 6733, + X86_VFPCLASSPSZ128rm = 6734, + X86_VFPCLASSPSZ128rmb = 6735, + X86_VFPCLASSPSZ128rmbk = 6736, + X86_VFPCLASSPSZ128rmk = 6737, + X86_VFPCLASSPSZ128rr = 6738, + X86_VFPCLASSPSZ128rrk = 6739, + X86_VFPCLASSPSZ256rm = 6740, + X86_VFPCLASSPSZ256rmb = 6741, + X86_VFPCLASSPSZ256rmbk = 6742, + X86_VFPCLASSPSZ256rmk = 6743, + X86_VFPCLASSPSZ256rr = 6744, + X86_VFPCLASSPSZ256rrk = 6745, + X86_VFPCLASSPSZrm = 6746, + X86_VFPCLASSPSZrmb = 6747, + X86_VFPCLASSPSZrmbk = 6748, + X86_VFPCLASSPSZrmk = 6749, + X86_VFPCLASSPSZrr = 6750, + X86_VFPCLASSPSZrrk = 6751, + X86_VFPCLASSSDZrm = 6752, + X86_VFPCLASSSDZrmk = 6753, + X86_VFPCLASSSDZrr = 6754, + X86_VFPCLASSSDZrrk = 6755, + X86_VFPCLASSSSZrm = 6756, + X86_VFPCLASSSSZrmk = 6757, + X86_VFPCLASSSSZrr = 6758, + X86_VFPCLASSSSZrrk = 6759, + X86_VFRCZPDYrm = 6760, + X86_VFRCZPDYrr = 6761, + X86_VFRCZPDrm = 6762, + X86_VFRCZPDrr = 6763, + X86_VFRCZPSYrm = 6764, + X86_VFRCZPSYrr = 6765, + X86_VFRCZPSrm = 6766, + X86_VFRCZPSrr = 6767, + X86_VFRCZSDrm = 6768, + X86_VFRCZSDrr = 6769, + X86_VFRCZSSrm = 6770, + X86_VFRCZSSrr = 6771, + X86_VGATHERDPDYrm = 6772, + X86_VGATHERDPDZ128rm = 6773, + X86_VGATHERDPDZ256rm = 6774, + X86_VGATHERDPDZrm = 6775, + X86_VGATHERDPDrm = 6776, + X86_VGATHERDPSYrm = 6777, + X86_VGATHERDPSZ128rm = 6778, + X86_VGATHERDPSZ256rm = 6779, + X86_VGATHERDPSZrm = 6780, + X86_VGATHERDPSrm = 6781, + X86_VGATHERPF0DPDm = 6782, + X86_VGATHERPF0DPSm = 6783, + X86_VGATHERPF0QPDm = 6784, + X86_VGATHERPF0QPSm = 6785, + X86_VGATHERPF1DPDm = 6786, + X86_VGATHERPF1DPSm = 6787, + X86_VGATHERPF1QPDm = 6788, + X86_VGATHERPF1QPSm = 6789, + X86_VGATHERQPDYrm = 6790, + X86_VGATHERQPDZ128rm = 6791, + X86_VGATHERQPDZ256rm = 6792, + X86_VGATHERQPDZrm = 6793, + X86_VGATHERQPDrm = 6794, + X86_VGATHERQPSYrm = 6795, + X86_VGATHERQPSZ128rm = 6796, + X86_VGATHERQPSZ256rm = 6797, + X86_VGATHERQPSZrm = 6798, + X86_VGATHERQPSrm = 6799, + X86_VGETEXPPDZ128m = 6800, + X86_VGETEXPPDZ128mb = 6801, + X86_VGETEXPPDZ128mbk = 6802, + X86_VGETEXPPDZ128mbkz = 6803, + X86_VGETEXPPDZ128mk = 6804, + X86_VGETEXPPDZ128mkz = 6805, + X86_VGETEXPPDZ128r = 6806, + X86_VGETEXPPDZ128rk = 6807, + X86_VGETEXPPDZ128rkz = 6808, + X86_VGETEXPPDZ256m = 6809, + X86_VGETEXPPDZ256mb = 6810, + X86_VGETEXPPDZ256mbk = 6811, + X86_VGETEXPPDZ256mbkz = 6812, + X86_VGETEXPPDZ256mk = 6813, + X86_VGETEXPPDZ256mkz = 6814, + X86_VGETEXPPDZ256r = 6815, + X86_VGETEXPPDZ256rk = 6816, + X86_VGETEXPPDZ256rkz = 6817, + X86_VGETEXPPDZm = 6818, + X86_VGETEXPPDZmb = 6819, + X86_VGETEXPPDZmbk = 6820, + X86_VGETEXPPDZmbkz = 6821, + X86_VGETEXPPDZmk = 6822, + X86_VGETEXPPDZmkz = 6823, + X86_VGETEXPPDZr = 6824, + X86_VGETEXPPDZrb = 6825, + X86_VGETEXPPDZrbk = 6826, + X86_VGETEXPPDZrbkz = 6827, + X86_VGETEXPPDZrk = 6828, + X86_VGETEXPPDZrkz = 6829, + X86_VGETEXPPSZ128m = 6830, + X86_VGETEXPPSZ128mb = 6831, + X86_VGETEXPPSZ128mbk = 6832, + X86_VGETEXPPSZ128mbkz = 6833, + X86_VGETEXPPSZ128mk = 6834, + X86_VGETEXPPSZ128mkz = 6835, + X86_VGETEXPPSZ128r = 6836, + X86_VGETEXPPSZ128rk = 6837, + X86_VGETEXPPSZ128rkz = 6838, + X86_VGETEXPPSZ256m = 6839, + X86_VGETEXPPSZ256mb = 6840, + X86_VGETEXPPSZ256mbk = 6841, + X86_VGETEXPPSZ256mbkz = 6842, + X86_VGETEXPPSZ256mk = 6843, + X86_VGETEXPPSZ256mkz = 6844, + X86_VGETEXPPSZ256r = 6845, + X86_VGETEXPPSZ256rk = 6846, + X86_VGETEXPPSZ256rkz = 6847, + X86_VGETEXPPSZm = 6848, + X86_VGETEXPPSZmb = 6849, + X86_VGETEXPPSZmbk = 6850, + X86_VGETEXPPSZmbkz = 6851, + X86_VGETEXPPSZmk = 6852, + X86_VGETEXPPSZmkz = 6853, + X86_VGETEXPPSZr = 6854, + X86_VGETEXPPSZrb = 6855, + X86_VGETEXPPSZrbk = 6856, + X86_VGETEXPPSZrbkz = 6857, + X86_VGETEXPPSZrk = 6858, + X86_VGETEXPPSZrkz = 6859, + X86_VGETEXPSDZm = 6860, + X86_VGETEXPSDZmk = 6861, + X86_VGETEXPSDZmkz = 6862, + X86_VGETEXPSDZr = 6863, + X86_VGETEXPSDZrb = 6864, + X86_VGETEXPSDZrbk = 6865, + X86_VGETEXPSDZrbkz = 6866, + X86_VGETEXPSDZrk = 6867, + X86_VGETEXPSDZrkz = 6868, + X86_VGETEXPSSZm = 6869, + X86_VGETEXPSSZmk = 6870, + X86_VGETEXPSSZmkz = 6871, + X86_VGETEXPSSZr = 6872, + X86_VGETEXPSSZrb = 6873, + X86_VGETEXPSSZrbk = 6874, + X86_VGETEXPSSZrbkz = 6875, + X86_VGETEXPSSZrk = 6876, + X86_VGETEXPSSZrkz = 6877, + X86_VGETMANTPDZ128rmbi = 6878, + X86_VGETMANTPDZ128rmbik = 6879, + X86_VGETMANTPDZ128rmbikz = 6880, + X86_VGETMANTPDZ128rmi = 6881, + X86_VGETMANTPDZ128rmik = 6882, + X86_VGETMANTPDZ128rmikz = 6883, + X86_VGETMANTPDZ128rri = 6884, + X86_VGETMANTPDZ128rrik = 6885, + X86_VGETMANTPDZ128rrikz = 6886, + X86_VGETMANTPDZ256rmbi = 6887, + X86_VGETMANTPDZ256rmbik = 6888, + X86_VGETMANTPDZ256rmbikz = 6889, + X86_VGETMANTPDZ256rmi = 6890, + X86_VGETMANTPDZ256rmik = 6891, + X86_VGETMANTPDZ256rmikz = 6892, + X86_VGETMANTPDZ256rri = 6893, + X86_VGETMANTPDZ256rrik = 6894, + X86_VGETMANTPDZ256rrikz = 6895, + X86_VGETMANTPDZrmbi = 6896, + X86_VGETMANTPDZrmbik = 6897, + X86_VGETMANTPDZrmbikz = 6898, + X86_VGETMANTPDZrmi = 6899, + X86_VGETMANTPDZrmik = 6900, + X86_VGETMANTPDZrmikz = 6901, + X86_VGETMANTPDZrri = 6902, + X86_VGETMANTPDZrrib = 6903, + X86_VGETMANTPDZrribk = 6904, + X86_VGETMANTPDZrribkz = 6905, + X86_VGETMANTPDZrrik = 6906, + X86_VGETMANTPDZrrikz = 6907, + X86_VGETMANTPSZ128rmbi = 6908, + X86_VGETMANTPSZ128rmbik = 6909, + X86_VGETMANTPSZ128rmbikz = 6910, + X86_VGETMANTPSZ128rmi = 6911, + X86_VGETMANTPSZ128rmik = 6912, + X86_VGETMANTPSZ128rmikz = 6913, + X86_VGETMANTPSZ128rri = 6914, + X86_VGETMANTPSZ128rrik = 6915, + X86_VGETMANTPSZ128rrikz = 6916, + X86_VGETMANTPSZ256rmbi = 6917, + X86_VGETMANTPSZ256rmbik = 6918, + X86_VGETMANTPSZ256rmbikz = 6919, + X86_VGETMANTPSZ256rmi = 6920, + X86_VGETMANTPSZ256rmik = 6921, + X86_VGETMANTPSZ256rmikz = 6922, + X86_VGETMANTPSZ256rri = 6923, + X86_VGETMANTPSZ256rrik = 6924, + X86_VGETMANTPSZ256rrikz = 6925, + X86_VGETMANTPSZrmbi = 6926, + X86_VGETMANTPSZrmbik = 6927, + X86_VGETMANTPSZrmbikz = 6928, + X86_VGETMANTPSZrmi = 6929, + X86_VGETMANTPSZrmik = 6930, + X86_VGETMANTPSZrmikz = 6931, + X86_VGETMANTPSZrri = 6932, + X86_VGETMANTPSZrrib = 6933, + X86_VGETMANTPSZrribk = 6934, + X86_VGETMANTPSZrribkz = 6935, + X86_VGETMANTPSZrrik = 6936, + X86_VGETMANTPSZrrikz = 6937, + X86_VGETMANTSDZrmi = 6938, + X86_VGETMANTSDZrmik = 6939, + X86_VGETMANTSDZrmikz = 6940, + X86_VGETMANTSDZrri = 6941, + X86_VGETMANTSDZrrib = 6942, + X86_VGETMANTSDZrribk = 6943, + X86_VGETMANTSDZrribkz = 6944, + X86_VGETMANTSDZrrik = 6945, + X86_VGETMANTSDZrrikz = 6946, + X86_VGETMANTSSZrmi = 6947, + X86_VGETMANTSSZrmik = 6948, + X86_VGETMANTSSZrmikz = 6949, + X86_VGETMANTSSZrri = 6950, + X86_VGETMANTSSZrrib = 6951, + X86_VGETMANTSSZrribk = 6952, + X86_VGETMANTSSZrribkz = 6953, + X86_VGETMANTSSZrrik = 6954, + X86_VGETMANTSSZrrikz = 6955, + X86_VGF2P8AFFINEINVQBYrmi = 6956, + X86_VGF2P8AFFINEINVQBYrri = 6957, + X86_VGF2P8AFFINEINVQBZ128rmbi = 6958, + X86_VGF2P8AFFINEINVQBZ128rmbik = 6959, + X86_VGF2P8AFFINEINVQBZ128rmbikz = 6960, + X86_VGF2P8AFFINEINVQBZ128rmi = 6961, + X86_VGF2P8AFFINEINVQBZ128rmik = 6962, + X86_VGF2P8AFFINEINVQBZ128rmikz = 6963, + X86_VGF2P8AFFINEINVQBZ128rri = 6964, + X86_VGF2P8AFFINEINVQBZ128rrik = 6965, + X86_VGF2P8AFFINEINVQBZ128rrikz = 6966, + X86_VGF2P8AFFINEINVQBZ256rmbi = 6967, + X86_VGF2P8AFFINEINVQBZ256rmbik = 6968, + X86_VGF2P8AFFINEINVQBZ256rmbikz = 6969, + X86_VGF2P8AFFINEINVQBZ256rmi = 6970, + X86_VGF2P8AFFINEINVQBZ256rmik = 6971, + X86_VGF2P8AFFINEINVQBZ256rmikz = 6972, + X86_VGF2P8AFFINEINVQBZ256rri = 6973, + X86_VGF2P8AFFINEINVQBZ256rrik = 6974, + X86_VGF2P8AFFINEINVQBZ256rrikz = 6975, + X86_VGF2P8AFFINEINVQBZrmbi = 6976, + X86_VGF2P8AFFINEINVQBZrmbik = 6977, + X86_VGF2P8AFFINEINVQBZrmbikz = 6978, + X86_VGF2P8AFFINEINVQBZrmi = 6979, + X86_VGF2P8AFFINEINVQBZrmik = 6980, + X86_VGF2P8AFFINEINVQBZrmikz = 6981, + X86_VGF2P8AFFINEINVQBZrri = 6982, + X86_VGF2P8AFFINEINVQBZrrik = 6983, + X86_VGF2P8AFFINEINVQBZrrikz = 6984, + X86_VGF2P8AFFINEINVQBrmi = 6985, + X86_VGF2P8AFFINEINVQBrri = 6986, + X86_VGF2P8AFFINEQBYrmi = 6987, + X86_VGF2P8AFFINEQBYrri = 6988, + X86_VGF2P8AFFINEQBZ128rmbi = 6989, + X86_VGF2P8AFFINEQBZ128rmbik = 6990, + X86_VGF2P8AFFINEQBZ128rmbikz = 6991, + X86_VGF2P8AFFINEQBZ128rmi = 6992, + X86_VGF2P8AFFINEQBZ128rmik = 6993, + X86_VGF2P8AFFINEQBZ128rmikz = 6994, + X86_VGF2P8AFFINEQBZ128rri = 6995, + X86_VGF2P8AFFINEQBZ128rrik = 6996, + X86_VGF2P8AFFINEQBZ128rrikz = 6997, + X86_VGF2P8AFFINEQBZ256rmbi = 6998, + X86_VGF2P8AFFINEQBZ256rmbik = 6999, + X86_VGF2P8AFFINEQBZ256rmbikz = 7000, + X86_VGF2P8AFFINEQBZ256rmi = 7001, + X86_VGF2P8AFFINEQBZ256rmik = 7002, + X86_VGF2P8AFFINEQBZ256rmikz = 7003, + X86_VGF2P8AFFINEQBZ256rri = 7004, + X86_VGF2P8AFFINEQBZ256rrik = 7005, + X86_VGF2P8AFFINEQBZ256rrikz = 7006, + X86_VGF2P8AFFINEQBZrmbi = 7007, + X86_VGF2P8AFFINEQBZrmbik = 7008, + X86_VGF2P8AFFINEQBZrmbikz = 7009, + X86_VGF2P8AFFINEQBZrmi = 7010, + X86_VGF2P8AFFINEQBZrmik = 7011, + X86_VGF2P8AFFINEQBZrmikz = 7012, + X86_VGF2P8AFFINEQBZrri = 7013, + X86_VGF2P8AFFINEQBZrrik = 7014, + X86_VGF2P8AFFINEQBZrrikz = 7015, + X86_VGF2P8AFFINEQBrmi = 7016, + X86_VGF2P8AFFINEQBrri = 7017, + X86_VGF2P8MULBYrm = 7018, + X86_VGF2P8MULBYrr = 7019, + X86_VGF2P8MULBZ128rm = 7020, + X86_VGF2P8MULBZ128rmk = 7021, + X86_VGF2P8MULBZ128rmkz = 7022, + X86_VGF2P8MULBZ128rr = 7023, + X86_VGF2P8MULBZ128rrk = 7024, + X86_VGF2P8MULBZ128rrkz = 7025, + X86_VGF2P8MULBZ256rm = 7026, + X86_VGF2P8MULBZ256rmk = 7027, + X86_VGF2P8MULBZ256rmkz = 7028, + X86_VGF2P8MULBZ256rr = 7029, + X86_VGF2P8MULBZ256rrk = 7030, + X86_VGF2P8MULBZ256rrkz = 7031, + X86_VGF2P8MULBZrm = 7032, + X86_VGF2P8MULBZrmk = 7033, + X86_VGF2P8MULBZrmkz = 7034, + X86_VGF2P8MULBZrr = 7035, + X86_VGF2P8MULBZrrk = 7036, + X86_VGF2P8MULBZrrkz = 7037, + X86_VGF2P8MULBrm = 7038, + X86_VGF2P8MULBrr = 7039, + X86_VHADDPDYrm = 7040, + X86_VHADDPDYrr = 7041, + X86_VHADDPDrm = 7042, + X86_VHADDPDrr = 7043, + X86_VHADDPSYrm = 7044, + X86_VHADDPSYrr = 7045, + X86_VHADDPSrm = 7046, + X86_VHADDPSrr = 7047, + X86_VHSUBPDYrm = 7048, + X86_VHSUBPDYrr = 7049, + X86_VHSUBPDrm = 7050, + X86_VHSUBPDrr = 7051, + X86_VHSUBPSYrm = 7052, + X86_VHSUBPSYrr = 7053, + X86_VHSUBPSrm = 7054, + X86_VHSUBPSrr = 7055, + X86_VINSERTF128rm = 7056, + X86_VINSERTF128rr = 7057, + X86_VINSERTF32x4Z256rm = 7058, + X86_VINSERTF32x4Z256rmk = 7059, + X86_VINSERTF32x4Z256rmkz = 7060, + X86_VINSERTF32x4Z256rr = 7061, + X86_VINSERTF32x4Z256rrk = 7062, + X86_VINSERTF32x4Z256rrkz = 7063, + X86_VINSERTF32x4Zrm = 7064, + X86_VINSERTF32x4Zrmk = 7065, + X86_VINSERTF32x4Zrmkz = 7066, + X86_VINSERTF32x4Zrr = 7067, + X86_VINSERTF32x4Zrrk = 7068, + X86_VINSERTF32x4Zrrkz = 7069, + X86_VINSERTF32x8Zrm = 7070, + X86_VINSERTF32x8Zrmk = 7071, + X86_VINSERTF32x8Zrmkz = 7072, + X86_VINSERTF32x8Zrr = 7073, + X86_VINSERTF32x8Zrrk = 7074, + X86_VINSERTF32x8Zrrkz = 7075, + X86_VINSERTF64x2Z256rm = 7076, + X86_VINSERTF64x2Z256rmk = 7077, + X86_VINSERTF64x2Z256rmkz = 7078, + X86_VINSERTF64x2Z256rr = 7079, + X86_VINSERTF64x2Z256rrk = 7080, + X86_VINSERTF64x2Z256rrkz = 7081, + X86_VINSERTF64x2Zrm = 7082, + X86_VINSERTF64x2Zrmk = 7083, + X86_VINSERTF64x2Zrmkz = 7084, + X86_VINSERTF64x2Zrr = 7085, + X86_VINSERTF64x2Zrrk = 7086, + X86_VINSERTF64x2Zrrkz = 7087, + X86_VINSERTF64x4Zrm = 7088, + X86_VINSERTF64x4Zrmk = 7089, + X86_VINSERTF64x4Zrmkz = 7090, + X86_VINSERTF64x4Zrr = 7091, + X86_VINSERTF64x4Zrrk = 7092, + X86_VINSERTF64x4Zrrkz = 7093, + X86_VINSERTI128rm = 7094, + X86_VINSERTI128rr = 7095, + X86_VINSERTI32x4Z256rm = 7096, + X86_VINSERTI32x4Z256rmk = 7097, + X86_VINSERTI32x4Z256rmkz = 7098, + X86_VINSERTI32x4Z256rr = 7099, + X86_VINSERTI32x4Z256rrk = 7100, + X86_VINSERTI32x4Z256rrkz = 7101, + X86_VINSERTI32x4Zrm = 7102, + X86_VINSERTI32x4Zrmk = 7103, + X86_VINSERTI32x4Zrmkz = 7104, + X86_VINSERTI32x4Zrr = 7105, + X86_VINSERTI32x4Zrrk = 7106, + X86_VINSERTI32x4Zrrkz = 7107, + X86_VINSERTI32x8Zrm = 7108, + X86_VINSERTI32x8Zrmk = 7109, + X86_VINSERTI32x8Zrmkz = 7110, + X86_VINSERTI32x8Zrr = 7111, + X86_VINSERTI32x8Zrrk = 7112, + X86_VINSERTI32x8Zrrkz = 7113, + X86_VINSERTI64x2Z256rm = 7114, + X86_VINSERTI64x2Z256rmk = 7115, + X86_VINSERTI64x2Z256rmkz = 7116, + X86_VINSERTI64x2Z256rr = 7117, + X86_VINSERTI64x2Z256rrk = 7118, + X86_VINSERTI64x2Z256rrkz = 7119, + X86_VINSERTI64x2Zrm = 7120, + X86_VINSERTI64x2Zrmk = 7121, + X86_VINSERTI64x2Zrmkz = 7122, + X86_VINSERTI64x2Zrr = 7123, + X86_VINSERTI64x2Zrrk = 7124, + X86_VINSERTI64x2Zrrkz = 7125, + X86_VINSERTI64x4Zrm = 7126, + X86_VINSERTI64x4Zrmk = 7127, + X86_VINSERTI64x4Zrmkz = 7128, + X86_VINSERTI64x4Zrr = 7129, + X86_VINSERTI64x4Zrrk = 7130, + X86_VINSERTI64x4Zrrkz = 7131, + X86_VINSERTPSZrm = 7132, + X86_VINSERTPSZrr = 7133, + X86_VINSERTPSrm = 7134, + X86_VINSERTPSrr = 7135, + X86_VLDDQUYrm = 7136, + X86_VLDDQUrm = 7137, + X86_VLDMXCSR = 7138, + X86_VMASKMOVDQU = 7139, + X86_VMASKMOVDQU64 = 7140, + X86_VMASKMOVPDYmr = 7141, + X86_VMASKMOVPDYrm = 7142, + X86_VMASKMOVPDmr = 7143, + X86_VMASKMOVPDrm = 7144, + X86_VMASKMOVPSYmr = 7145, + X86_VMASKMOVPSYrm = 7146, + X86_VMASKMOVPSmr = 7147, + X86_VMASKMOVPSrm = 7148, + X86_VMAXCPDYrm = 7149, + X86_VMAXCPDYrr = 7150, + X86_VMAXCPDZ128rm = 7151, + X86_VMAXCPDZ128rmb = 7152, + X86_VMAXCPDZ128rmbk = 7153, + X86_VMAXCPDZ128rmbkz = 7154, + X86_VMAXCPDZ128rmk = 7155, + X86_VMAXCPDZ128rmkz = 7156, + X86_VMAXCPDZ128rr = 7157, + X86_VMAXCPDZ128rrk = 7158, + X86_VMAXCPDZ128rrkz = 7159, + X86_VMAXCPDZ256rm = 7160, + X86_VMAXCPDZ256rmb = 7161, + X86_VMAXCPDZ256rmbk = 7162, + X86_VMAXCPDZ256rmbkz = 7163, + X86_VMAXCPDZ256rmk = 7164, + X86_VMAXCPDZ256rmkz = 7165, + X86_VMAXCPDZ256rr = 7166, + X86_VMAXCPDZ256rrk = 7167, + X86_VMAXCPDZ256rrkz = 7168, + X86_VMAXCPDZrm = 7169, + X86_VMAXCPDZrmb = 7170, + X86_VMAXCPDZrmbk = 7171, + X86_VMAXCPDZrmbkz = 7172, + X86_VMAXCPDZrmk = 7173, + X86_VMAXCPDZrmkz = 7174, + X86_VMAXCPDZrr = 7175, + X86_VMAXCPDZrrk = 7176, + X86_VMAXCPDZrrkz = 7177, + X86_VMAXCPDrm = 7178, + X86_VMAXCPDrr = 7179, + X86_VMAXCPSYrm = 7180, + X86_VMAXCPSYrr = 7181, + X86_VMAXCPSZ128rm = 7182, + X86_VMAXCPSZ128rmb = 7183, + X86_VMAXCPSZ128rmbk = 7184, + X86_VMAXCPSZ128rmbkz = 7185, + X86_VMAXCPSZ128rmk = 7186, + X86_VMAXCPSZ128rmkz = 7187, + X86_VMAXCPSZ128rr = 7188, + X86_VMAXCPSZ128rrk = 7189, + X86_VMAXCPSZ128rrkz = 7190, + X86_VMAXCPSZ256rm = 7191, + X86_VMAXCPSZ256rmb = 7192, + X86_VMAXCPSZ256rmbk = 7193, + X86_VMAXCPSZ256rmbkz = 7194, + X86_VMAXCPSZ256rmk = 7195, + X86_VMAXCPSZ256rmkz = 7196, + X86_VMAXCPSZ256rr = 7197, + X86_VMAXCPSZ256rrk = 7198, + X86_VMAXCPSZ256rrkz = 7199, + X86_VMAXCPSZrm = 7200, + X86_VMAXCPSZrmb = 7201, + X86_VMAXCPSZrmbk = 7202, + X86_VMAXCPSZrmbkz = 7203, + X86_VMAXCPSZrmk = 7204, + X86_VMAXCPSZrmkz = 7205, + X86_VMAXCPSZrr = 7206, + X86_VMAXCPSZrrk = 7207, + X86_VMAXCPSZrrkz = 7208, + X86_VMAXCPSrm = 7209, + X86_VMAXCPSrr = 7210, + X86_VMAXCSDZrm = 7211, + X86_VMAXCSDZrr = 7212, + X86_VMAXCSDrm = 7213, + X86_VMAXCSDrr = 7214, + X86_VMAXCSSZrm = 7215, + X86_VMAXCSSZrr = 7216, + X86_VMAXCSSrm = 7217, + X86_VMAXCSSrr = 7218, + X86_VMAXPDYrm = 7219, + X86_VMAXPDYrr = 7220, + X86_VMAXPDZ128rm = 7221, + X86_VMAXPDZ128rmb = 7222, + X86_VMAXPDZ128rmbk = 7223, + X86_VMAXPDZ128rmbkz = 7224, + X86_VMAXPDZ128rmk = 7225, + X86_VMAXPDZ128rmkz = 7226, + X86_VMAXPDZ128rr = 7227, + X86_VMAXPDZ128rrk = 7228, + X86_VMAXPDZ128rrkz = 7229, + X86_VMAXPDZ256rm = 7230, + X86_VMAXPDZ256rmb = 7231, + X86_VMAXPDZ256rmbk = 7232, + X86_VMAXPDZ256rmbkz = 7233, + X86_VMAXPDZ256rmk = 7234, + X86_VMAXPDZ256rmkz = 7235, + X86_VMAXPDZ256rr = 7236, + X86_VMAXPDZ256rrk = 7237, + X86_VMAXPDZ256rrkz = 7238, + X86_VMAXPDZrm = 7239, + X86_VMAXPDZrmb = 7240, + X86_VMAXPDZrmbk = 7241, + X86_VMAXPDZrmbkz = 7242, + X86_VMAXPDZrmk = 7243, + X86_VMAXPDZrmkz = 7244, + X86_VMAXPDZrr = 7245, + X86_VMAXPDZrrb = 7246, + X86_VMAXPDZrrbk = 7247, + X86_VMAXPDZrrbkz = 7248, + X86_VMAXPDZrrk = 7249, + X86_VMAXPDZrrkz = 7250, + X86_VMAXPDrm = 7251, + X86_VMAXPDrr = 7252, + X86_VMAXPSYrm = 7253, + X86_VMAXPSYrr = 7254, + X86_VMAXPSZ128rm = 7255, + X86_VMAXPSZ128rmb = 7256, + X86_VMAXPSZ128rmbk = 7257, + X86_VMAXPSZ128rmbkz = 7258, + X86_VMAXPSZ128rmk = 7259, + X86_VMAXPSZ128rmkz = 7260, + X86_VMAXPSZ128rr = 7261, + X86_VMAXPSZ128rrk = 7262, + X86_VMAXPSZ128rrkz = 7263, + X86_VMAXPSZ256rm = 7264, + X86_VMAXPSZ256rmb = 7265, + X86_VMAXPSZ256rmbk = 7266, + X86_VMAXPSZ256rmbkz = 7267, + X86_VMAXPSZ256rmk = 7268, + X86_VMAXPSZ256rmkz = 7269, + X86_VMAXPSZ256rr = 7270, + X86_VMAXPSZ256rrk = 7271, + X86_VMAXPSZ256rrkz = 7272, + X86_VMAXPSZrm = 7273, + X86_VMAXPSZrmb = 7274, + X86_VMAXPSZrmbk = 7275, + X86_VMAXPSZrmbkz = 7276, + X86_VMAXPSZrmk = 7277, + X86_VMAXPSZrmkz = 7278, + X86_VMAXPSZrr = 7279, + X86_VMAXPSZrrb = 7280, + X86_VMAXPSZrrbk = 7281, + X86_VMAXPSZrrbkz = 7282, + X86_VMAXPSZrrk = 7283, + X86_VMAXPSZrrkz = 7284, + X86_VMAXPSrm = 7285, + X86_VMAXPSrr = 7286, + X86_VMAXSDZrm = 7287, + X86_VMAXSDZrm_Int = 7288, + X86_VMAXSDZrm_Intk = 7289, + X86_VMAXSDZrm_Intkz = 7290, + X86_VMAXSDZrr = 7291, + X86_VMAXSDZrr_Int = 7292, + X86_VMAXSDZrr_Intk = 7293, + X86_VMAXSDZrr_Intkz = 7294, + X86_VMAXSDZrrb_Int = 7295, + X86_VMAXSDZrrb_Intk = 7296, + X86_VMAXSDZrrb_Intkz = 7297, + X86_VMAXSDrm = 7298, + X86_VMAXSDrm_Int = 7299, + X86_VMAXSDrr = 7300, + X86_VMAXSDrr_Int = 7301, + X86_VMAXSSZrm = 7302, + X86_VMAXSSZrm_Int = 7303, + X86_VMAXSSZrm_Intk = 7304, + X86_VMAXSSZrm_Intkz = 7305, + X86_VMAXSSZrr = 7306, + X86_VMAXSSZrr_Int = 7307, + X86_VMAXSSZrr_Intk = 7308, + X86_VMAXSSZrr_Intkz = 7309, + X86_VMAXSSZrrb_Int = 7310, + X86_VMAXSSZrrb_Intk = 7311, + X86_VMAXSSZrrb_Intkz = 7312, + X86_VMAXSSrm = 7313, + X86_VMAXSSrm_Int = 7314, + X86_VMAXSSrr = 7315, + X86_VMAXSSrr_Int = 7316, + X86_VMCALL = 7317, + X86_VMCLEARm = 7318, + X86_VMFUNC = 7319, + X86_VMINCPDYrm = 7320, + X86_VMINCPDYrr = 7321, + X86_VMINCPDZ128rm = 7322, + X86_VMINCPDZ128rmb = 7323, + X86_VMINCPDZ128rmbk = 7324, + X86_VMINCPDZ128rmbkz = 7325, + X86_VMINCPDZ128rmk = 7326, + X86_VMINCPDZ128rmkz = 7327, + X86_VMINCPDZ128rr = 7328, + X86_VMINCPDZ128rrk = 7329, + X86_VMINCPDZ128rrkz = 7330, + X86_VMINCPDZ256rm = 7331, + X86_VMINCPDZ256rmb = 7332, + X86_VMINCPDZ256rmbk = 7333, + X86_VMINCPDZ256rmbkz = 7334, + X86_VMINCPDZ256rmk = 7335, + X86_VMINCPDZ256rmkz = 7336, + X86_VMINCPDZ256rr = 7337, + X86_VMINCPDZ256rrk = 7338, + X86_VMINCPDZ256rrkz = 7339, + X86_VMINCPDZrm = 7340, + X86_VMINCPDZrmb = 7341, + X86_VMINCPDZrmbk = 7342, + X86_VMINCPDZrmbkz = 7343, + X86_VMINCPDZrmk = 7344, + X86_VMINCPDZrmkz = 7345, + X86_VMINCPDZrr = 7346, + X86_VMINCPDZrrk = 7347, + X86_VMINCPDZrrkz = 7348, + X86_VMINCPDrm = 7349, + X86_VMINCPDrr = 7350, + X86_VMINCPSYrm = 7351, + X86_VMINCPSYrr = 7352, + X86_VMINCPSZ128rm = 7353, + X86_VMINCPSZ128rmb = 7354, + X86_VMINCPSZ128rmbk = 7355, + X86_VMINCPSZ128rmbkz = 7356, + X86_VMINCPSZ128rmk = 7357, + X86_VMINCPSZ128rmkz = 7358, + X86_VMINCPSZ128rr = 7359, + X86_VMINCPSZ128rrk = 7360, + X86_VMINCPSZ128rrkz = 7361, + X86_VMINCPSZ256rm = 7362, + X86_VMINCPSZ256rmb = 7363, + X86_VMINCPSZ256rmbk = 7364, + X86_VMINCPSZ256rmbkz = 7365, + X86_VMINCPSZ256rmk = 7366, + X86_VMINCPSZ256rmkz = 7367, + X86_VMINCPSZ256rr = 7368, + X86_VMINCPSZ256rrk = 7369, + X86_VMINCPSZ256rrkz = 7370, + X86_VMINCPSZrm = 7371, + X86_VMINCPSZrmb = 7372, + X86_VMINCPSZrmbk = 7373, + X86_VMINCPSZrmbkz = 7374, + X86_VMINCPSZrmk = 7375, + X86_VMINCPSZrmkz = 7376, + X86_VMINCPSZrr = 7377, + X86_VMINCPSZrrk = 7378, + X86_VMINCPSZrrkz = 7379, + X86_VMINCPSrm = 7380, + X86_VMINCPSrr = 7381, + X86_VMINCSDZrm = 7382, + X86_VMINCSDZrr = 7383, + X86_VMINCSDrm = 7384, + X86_VMINCSDrr = 7385, + X86_VMINCSSZrm = 7386, + X86_VMINCSSZrr = 7387, + X86_VMINCSSrm = 7388, + X86_VMINCSSrr = 7389, + X86_VMINPDYrm = 7390, + X86_VMINPDYrr = 7391, + X86_VMINPDZ128rm = 7392, + X86_VMINPDZ128rmb = 7393, + X86_VMINPDZ128rmbk = 7394, + X86_VMINPDZ128rmbkz = 7395, + X86_VMINPDZ128rmk = 7396, + X86_VMINPDZ128rmkz = 7397, + X86_VMINPDZ128rr = 7398, + X86_VMINPDZ128rrk = 7399, + X86_VMINPDZ128rrkz = 7400, + X86_VMINPDZ256rm = 7401, + X86_VMINPDZ256rmb = 7402, + X86_VMINPDZ256rmbk = 7403, + X86_VMINPDZ256rmbkz = 7404, + X86_VMINPDZ256rmk = 7405, + X86_VMINPDZ256rmkz = 7406, + X86_VMINPDZ256rr = 7407, + X86_VMINPDZ256rrk = 7408, + X86_VMINPDZ256rrkz = 7409, + X86_VMINPDZrm = 7410, + X86_VMINPDZrmb = 7411, + X86_VMINPDZrmbk = 7412, + X86_VMINPDZrmbkz = 7413, + X86_VMINPDZrmk = 7414, + X86_VMINPDZrmkz = 7415, + X86_VMINPDZrr = 7416, + X86_VMINPDZrrb = 7417, + X86_VMINPDZrrbk = 7418, + X86_VMINPDZrrbkz = 7419, + X86_VMINPDZrrk = 7420, + X86_VMINPDZrrkz = 7421, + X86_VMINPDrm = 7422, + X86_VMINPDrr = 7423, + X86_VMINPSYrm = 7424, + X86_VMINPSYrr = 7425, + X86_VMINPSZ128rm = 7426, + X86_VMINPSZ128rmb = 7427, + X86_VMINPSZ128rmbk = 7428, + X86_VMINPSZ128rmbkz = 7429, + X86_VMINPSZ128rmk = 7430, + X86_VMINPSZ128rmkz = 7431, + X86_VMINPSZ128rr = 7432, + X86_VMINPSZ128rrk = 7433, + X86_VMINPSZ128rrkz = 7434, + X86_VMINPSZ256rm = 7435, + X86_VMINPSZ256rmb = 7436, + X86_VMINPSZ256rmbk = 7437, + X86_VMINPSZ256rmbkz = 7438, + X86_VMINPSZ256rmk = 7439, + X86_VMINPSZ256rmkz = 7440, + X86_VMINPSZ256rr = 7441, + X86_VMINPSZ256rrk = 7442, + X86_VMINPSZ256rrkz = 7443, + X86_VMINPSZrm = 7444, + X86_VMINPSZrmb = 7445, + X86_VMINPSZrmbk = 7446, + X86_VMINPSZrmbkz = 7447, + X86_VMINPSZrmk = 7448, + X86_VMINPSZrmkz = 7449, + X86_VMINPSZrr = 7450, + X86_VMINPSZrrb = 7451, + X86_VMINPSZrrbk = 7452, + X86_VMINPSZrrbkz = 7453, + X86_VMINPSZrrk = 7454, + X86_VMINPSZrrkz = 7455, + X86_VMINPSrm = 7456, + X86_VMINPSrr = 7457, + X86_VMINSDZrm = 7458, + X86_VMINSDZrm_Int = 7459, + X86_VMINSDZrm_Intk = 7460, + X86_VMINSDZrm_Intkz = 7461, + X86_VMINSDZrr = 7462, + X86_VMINSDZrr_Int = 7463, + X86_VMINSDZrr_Intk = 7464, + X86_VMINSDZrr_Intkz = 7465, + X86_VMINSDZrrb_Int = 7466, + X86_VMINSDZrrb_Intk = 7467, + X86_VMINSDZrrb_Intkz = 7468, + X86_VMINSDrm = 7469, + X86_VMINSDrm_Int = 7470, + X86_VMINSDrr = 7471, + X86_VMINSDrr_Int = 7472, + X86_VMINSSZrm = 7473, + X86_VMINSSZrm_Int = 7474, + X86_VMINSSZrm_Intk = 7475, + X86_VMINSSZrm_Intkz = 7476, + X86_VMINSSZrr = 7477, + X86_VMINSSZrr_Int = 7478, + X86_VMINSSZrr_Intk = 7479, + X86_VMINSSZrr_Intkz = 7480, + X86_VMINSSZrrb_Int = 7481, + X86_VMINSSZrrb_Intk = 7482, + X86_VMINSSZrrb_Intkz = 7483, + X86_VMINSSrm = 7484, + X86_VMINSSrm_Int = 7485, + X86_VMINSSrr = 7486, + X86_VMINSSrr_Int = 7487, + X86_VMLAUNCH = 7488, + X86_VMLOAD32 = 7489, + X86_VMLOAD64 = 7490, + X86_VMMCALL = 7491, + X86_VMOV64toPQIZrm = 7492, + X86_VMOV64toPQIZrr = 7493, + X86_VMOV64toPQIrm = 7494, + X86_VMOV64toPQIrr = 7495, + X86_VMOV64toSDZrm = 7496, + X86_VMOV64toSDZrr = 7497, + X86_VMOV64toSDrm = 7498, + X86_VMOV64toSDrr = 7499, + X86_VMOVAPDYmr = 7500, + X86_VMOVAPDYrm = 7501, + X86_VMOVAPDYrr = 7502, + X86_VMOVAPDYrr_REV = 7503, + X86_VMOVAPDZ128mr = 7504, + X86_VMOVAPDZ128mrk = 7505, + X86_VMOVAPDZ128rm = 7506, + X86_VMOVAPDZ128rmk = 7507, + X86_VMOVAPDZ128rmkz = 7508, + X86_VMOVAPDZ128rr = 7509, + X86_VMOVAPDZ128rr_REV = 7510, + X86_VMOVAPDZ128rrk = 7511, + X86_VMOVAPDZ128rrk_REV = 7512, + X86_VMOVAPDZ128rrkz = 7513, + X86_VMOVAPDZ128rrkz_REV = 7514, + X86_VMOVAPDZ256mr = 7515, + X86_VMOVAPDZ256mrk = 7516, + X86_VMOVAPDZ256rm = 7517, + X86_VMOVAPDZ256rmk = 7518, + X86_VMOVAPDZ256rmkz = 7519, + X86_VMOVAPDZ256rr = 7520, + X86_VMOVAPDZ256rr_REV = 7521, + X86_VMOVAPDZ256rrk = 7522, + X86_VMOVAPDZ256rrk_REV = 7523, + X86_VMOVAPDZ256rrkz = 7524, + X86_VMOVAPDZ256rrkz_REV = 7525, + X86_VMOVAPDZmr = 7526, + X86_VMOVAPDZmrk = 7527, + X86_VMOVAPDZrm = 7528, + X86_VMOVAPDZrmk = 7529, + X86_VMOVAPDZrmkz = 7530, + X86_VMOVAPDZrr = 7531, + X86_VMOVAPDZrr_REV = 7532, + X86_VMOVAPDZrrk = 7533, + X86_VMOVAPDZrrk_REV = 7534, + X86_VMOVAPDZrrkz = 7535, + X86_VMOVAPDZrrkz_REV = 7536, + X86_VMOVAPDmr = 7537, + X86_VMOVAPDrm = 7538, + X86_VMOVAPDrr = 7539, + X86_VMOVAPDrr_REV = 7540, + X86_VMOVAPSYmr = 7541, + X86_VMOVAPSYrm = 7542, + X86_VMOVAPSYrr = 7543, + X86_VMOVAPSYrr_REV = 7544, + X86_VMOVAPSZ128mr = 7545, + X86_VMOVAPSZ128mrk = 7546, + X86_VMOVAPSZ128rm = 7547, + X86_VMOVAPSZ128rmk = 7548, + X86_VMOVAPSZ128rmkz = 7549, + X86_VMOVAPSZ128rr = 7550, + X86_VMOVAPSZ128rr_REV = 7551, + X86_VMOVAPSZ128rrk = 7552, + X86_VMOVAPSZ128rrk_REV = 7553, + X86_VMOVAPSZ128rrkz = 7554, + X86_VMOVAPSZ128rrkz_REV = 7555, + X86_VMOVAPSZ256mr = 7556, + X86_VMOVAPSZ256mrk = 7557, + X86_VMOVAPSZ256rm = 7558, + X86_VMOVAPSZ256rmk = 7559, + X86_VMOVAPSZ256rmkz = 7560, + X86_VMOVAPSZ256rr = 7561, + X86_VMOVAPSZ256rr_REV = 7562, + X86_VMOVAPSZ256rrk = 7563, + X86_VMOVAPSZ256rrk_REV = 7564, + X86_VMOVAPSZ256rrkz = 7565, + X86_VMOVAPSZ256rrkz_REV = 7566, + X86_VMOVAPSZmr = 7567, + X86_VMOVAPSZmrk = 7568, + X86_VMOVAPSZrm = 7569, + X86_VMOVAPSZrmk = 7570, + X86_VMOVAPSZrmkz = 7571, + X86_VMOVAPSZrr = 7572, + X86_VMOVAPSZrr_REV = 7573, + X86_VMOVAPSZrrk = 7574, + X86_VMOVAPSZrrk_REV = 7575, + X86_VMOVAPSZrrkz = 7576, + X86_VMOVAPSZrrkz_REV = 7577, + X86_VMOVAPSmr = 7578, + X86_VMOVAPSrm = 7579, + X86_VMOVAPSrr = 7580, + X86_VMOVAPSrr_REV = 7581, + X86_VMOVDDUPYrm = 7582, + X86_VMOVDDUPYrr = 7583, + X86_VMOVDDUPZ128rm = 7584, + X86_VMOVDDUPZ128rmk = 7585, + X86_VMOVDDUPZ128rmkz = 7586, + X86_VMOVDDUPZ128rr = 7587, + X86_VMOVDDUPZ128rrk = 7588, + X86_VMOVDDUPZ128rrkz = 7589, + X86_VMOVDDUPZ256rm = 7590, + X86_VMOVDDUPZ256rmk = 7591, + X86_VMOVDDUPZ256rmkz = 7592, + X86_VMOVDDUPZ256rr = 7593, + X86_VMOVDDUPZ256rrk = 7594, + X86_VMOVDDUPZ256rrkz = 7595, + X86_VMOVDDUPZrm = 7596, + X86_VMOVDDUPZrmk = 7597, + X86_VMOVDDUPZrmkz = 7598, + X86_VMOVDDUPZrr = 7599, + X86_VMOVDDUPZrrk = 7600, + X86_VMOVDDUPZrrkz = 7601, + X86_VMOVDDUPrm = 7602, + X86_VMOVDDUPrr = 7603, + X86_VMOVDI2PDIZrm = 7604, + X86_VMOVDI2PDIZrr = 7605, + X86_VMOVDI2PDIrm = 7606, + X86_VMOVDI2PDIrr = 7607, + X86_VMOVDI2SSZrm = 7608, + X86_VMOVDI2SSZrr = 7609, + X86_VMOVDI2SSrm = 7610, + X86_VMOVDI2SSrr = 7611, + X86_VMOVDQA32Z128mr = 7612, + X86_VMOVDQA32Z128mrk = 7613, + X86_VMOVDQA32Z128rm = 7614, + X86_VMOVDQA32Z128rmk = 7615, + X86_VMOVDQA32Z128rmkz = 7616, + X86_VMOVDQA32Z128rr = 7617, + X86_VMOVDQA32Z128rr_REV = 7618, + X86_VMOVDQA32Z128rrk = 7619, + X86_VMOVDQA32Z128rrk_REV = 7620, + X86_VMOVDQA32Z128rrkz = 7621, + X86_VMOVDQA32Z128rrkz_REV = 7622, + X86_VMOVDQA32Z256mr = 7623, + X86_VMOVDQA32Z256mrk = 7624, + X86_VMOVDQA32Z256rm = 7625, + X86_VMOVDQA32Z256rmk = 7626, + X86_VMOVDQA32Z256rmkz = 7627, + X86_VMOVDQA32Z256rr = 7628, + X86_VMOVDQA32Z256rr_REV = 7629, + X86_VMOVDQA32Z256rrk = 7630, + X86_VMOVDQA32Z256rrk_REV = 7631, + X86_VMOVDQA32Z256rrkz = 7632, + X86_VMOVDQA32Z256rrkz_REV = 7633, + X86_VMOVDQA32Zmr = 7634, + X86_VMOVDQA32Zmrk = 7635, + X86_VMOVDQA32Zrm = 7636, + X86_VMOVDQA32Zrmk = 7637, + X86_VMOVDQA32Zrmkz = 7638, + X86_VMOVDQA32Zrr = 7639, + X86_VMOVDQA32Zrr_REV = 7640, + X86_VMOVDQA32Zrrk = 7641, + X86_VMOVDQA32Zrrk_REV = 7642, + X86_VMOVDQA32Zrrkz = 7643, + X86_VMOVDQA32Zrrkz_REV = 7644, + X86_VMOVDQA64Z128mr = 7645, + X86_VMOVDQA64Z128mrk = 7646, + X86_VMOVDQA64Z128rm = 7647, + X86_VMOVDQA64Z128rmk = 7648, + X86_VMOVDQA64Z128rmkz = 7649, + X86_VMOVDQA64Z128rr = 7650, + X86_VMOVDQA64Z128rr_REV = 7651, + X86_VMOVDQA64Z128rrk = 7652, + X86_VMOVDQA64Z128rrk_REV = 7653, + X86_VMOVDQA64Z128rrkz = 7654, + X86_VMOVDQA64Z128rrkz_REV = 7655, + X86_VMOVDQA64Z256mr = 7656, + X86_VMOVDQA64Z256mrk = 7657, + X86_VMOVDQA64Z256rm = 7658, + X86_VMOVDQA64Z256rmk = 7659, + X86_VMOVDQA64Z256rmkz = 7660, + X86_VMOVDQA64Z256rr = 7661, + X86_VMOVDQA64Z256rr_REV = 7662, + X86_VMOVDQA64Z256rrk = 7663, + X86_VMOVDQA64Z256rrk_REV = 7664, + X86_VMOVDQA64Z256rrkz = 7665, + X86_VMOVDQA64Z256rrkz_REV = 7666, + X86_VMOVDQA64Zmr = 7667, + X86_VMOVDQA64Zmrk = 7668, + X86_VMOVDQA64Zrm = 7669, + X86_VMOVDQA64Zrmk = 7670, + X86_VMOVDQA64Zrmkz = 7671, + X86_VMOVDQA64Zrr = 7672, + X86_VMOVDQA64Zrr_REV = 7673, + X86_VMOVDQA64Zrrk = 7674, + X86_VMOVDQA64Zrrk_REV = 7675, + X86_VMOVDQA64Zrrkz = 7676, + X86_VMOVDQA64Zrrkz_REV = 7677, + X86_VMOVDQAYmr = 7678, + X86_VMOVDQAYrm = 7679, + X86_VMOVDQAYrr = 7680, + X86_VMOVDQAYrr_REV = 7681, + X86_VMOVDQAmr = 7682, + X86_VMOVDQArm = 7683, + X86_VMOVDQArr = 7684, + X86_VMOVDQArr_REV = 7685, + X86_VMOVDQU16Z128mr = 7686, + X86_VMOVDQU16Z128mrk = 7687, + X86_VMOVDQU16Z128rm = 7688, + X86_VMOVDQU16Z128rmk = 7689, + X86_VMOVDQU16Z128rmkz = 7690, + X86_VMOVDQU16Z128rr = 7691, + X86_VMOVDQU16Z128rr_REV = 7692, + X86_VMOVDQU16Z128rrk = 7693, + X86_VMOVDQU16Z128rrk_REV = 7694, + X86_VMOVDQU16Z128rrkz = 7695, + X86_VMOVDQU16Z128rrkz_REV = 7696, + X86_VMOVDQU16Z256mr = 7697, + X86_VMOVDQU16Z256mrk = 7698, + X86_VMOVDQU16Z256rm = 7699, + X86_VMOVDQU16Z256rmk = 7700, + X86_VMOVDQU16Z256rmkz = 7701, + X86_VMOVDQU16Z256rr = 7702, + X86_VMOVDQU16Z256rr_REV = 7703, + X86_VMOVDQU16Z256rrk = 7704, + X86_VMOVDQU16Z256rrk_REV = 7705, + X86_VMOVDQU16Z256rrkz = 7706, + X86_VMOVDQU16Z256rrkz_REV = 7707, + X86_VMOVDQU16Zmr = 7708, + X86_VMOVDQU16Zmrk = 7709, + X86_VMOVDQU16Zrm = 7710, + X86_VMOVDQU16Zrmk = 7711, + X86_VMOVDQU16Zrmkz = 7712, + X86_VMOVDQU16Zrr = 7713, + X86_VMOVDQU16Zrr_REV = 7714, + X86_VMOVDQU16Zrrk = 7715, + X86_VMOVDQU16Zrrk_REV = 7716, + X86_VMOVDQU16Zrrkz = 7717, + X86_VMOVDQU16Zrrkz_REV = 7718, + X86_VMOVDQU32Z128mr = 7719, + X86_VMOVDQU32Z128mrk = 7720, + X86_VMOVDQU32Z128rm = 7721, + X86_VMOVDQU32Z128rmk = 7722, + X86_VMOVDQU32Z128rmkz = 7723, + X86_VMOVDQU32Z128rr = 7724, + X86_VMOVDQU32Z128rr_REV = 7725, + X86_VMOVDQU32Z128rrk = 7726, + X86_VMOVDQU32Z128rrk_REV = 7727, + X86_VMOVDQU32Z128rrkz = 7728, + X86_VMOVDQU32Z128rrkz_REV = 7729, + X86_VMOVDQU32Z256mr = 7730, + X86_VMOVDQU32Z256mrk = 7731, + X86_VMOVDQU32Z256rm = 7732, + X86_VMOVDQU32Z256rmk = 7733, + X86_VMOVDQU32Z256rmkz = 7734, + X86_VMOVDQU32Z256rr = 7735, + X86_VMOVDQU32Z256rr_REV = 7736, + X86_VMOVDQU32Z256rrk = 7737, + X86_VMOVDQU32Z256rrk_REV = 7738, + X86_VMOVDQU32Z256rrkz = 7739, + X86_VMOVDQU32Z256rrkz_REV = 7740, + X86_VMOVDQU32Zmr = 7741, + X86_VMOVDQU32Zmrk = 7742, + X86_VMOVDQU32Zrm = 7743, + X86_VMOVDQU32Zrmk = 7744, + X86_VMOVDQU32Zrmkz = 7745, + X86_VMOVDQU32Zrr = 7746, + X86_VMOVDQU32Zrr_REV = 7747, + X86_VMOVDQU32Zrrk = 7748, + X86_VMOVDQU32Zrrk_REV = 7749, + X86_VMOVDQU32Zrrkz = 7750, + X86_VMOVDQU32Zrrkz_REV = 7751, + X86_VMOVDQU64Z128mr = 7752, + X86_VMOVDQU64Z128mrk = 7753, + X86_VMOVDQU64Z128rm = 7754, + X86_VMOVDQU64Z128rmk = 7755, + X86_VMOVDQU64Z128rmkz = 7756, + X86_VMOVDQU64Z128rr = 7757, + X86_VMOVDQU64Z128rr_REV = 7758, + X86_VMOVDQU64Z128rrk = 7759, + X86_VMOVDQU64Z128rrk_REV = 7760, + X86_VMOVDQU64Z128rrkz = 7761, + X86_VMOVDQU64Z128rrkz_REV = 7762, + X86_VMOVDQU64Z256mr = 7763, + X86_VMOVDQU64Z256mrk = 7764, + X86_VMOVDQU64Z256rm = 7765, + X86_VMOVDQU64Z256rmk = 7766, + X86_VMOVDQU64Z256rmkz = 7767, + X86_VMOVDQU64Z256rr = 7768, + X86_VMOVDQU64Z256rr_REV = 7769, + X86_VMOVDQU64Z256rrk = 7770, + X86_VMOVDQU64Z256rrk_REV = 7771, + X86_VMOVDQU64Z256rrkz = 7772, + X86_VMOVDQU64Z256rrkz_REV = 7773, + X86_VMOVDQU64Zmr = 7774, + X86_VMOVDQU64Zmrk = 7775, + X86_VMOVDQU64Zrm = 7776, + X86_VMOVDQU64Zrmk = 7777, + X86_VMOVDQU64Zrmkz = 7778, + X86_VMOVDQU64Zrr = 7779, + X86_VMOVDQU64Zrr_REV = 7780, + X86_VMOVDQU64Zrrk = 7781, + X86_VMOVDQU64Zrrk_REV = 7782, + X86_VMOVDQU64Zrrkz = 7783, + X86_VMOVDQU64Zrrkz_REV = 7784, + X86_VMOVDQU8Z128mr = 7785, + X86_VMOVDQU8Z128mrk = 7786, + X86_VMOVDQU8Z128rm = 7787, + X86_VMOVDQU8Z128rmk = 7788, + X86_VMOVDQU8Z128rmkz = 7789, + X86_VMOVDQU8Z128rr = 7790, + X86_VMOVDQU8Z128rr_REV = 7791, + X86_VMOVDQU8Z128rrk = 7792, + X86_VMOVDQU8Z128rrk_REV = 7793, + X86_VMOVDQU8Z128rrkz = 7794, + X86_VMOVDQU8Z128rrkz_REV = 7795, + X86_VMOVDQU8Z256mr = 7796, + X86_VMOVDQU8Z256mrk = 7797, + X86_VMOVDQU8Z256rm = 7798, + X86_VMOVDQU8Z256rmk = 7799, + X86_VMOVDQU8Z256rmkz = 7800, + X86_VMOVDQU8Z256rr = 7801, + X86_VMOVDQU8Z256rr_REV = 7802, + X86_VMOVDQU8Z256rrk = 7803, + X86_VMOVDQU8Z256rrk_REV = 7804, + X86_VMOVDQU8Z256rrkz = 7805, + X86_VMOVDQU8Z256rrkz_REV = 7806, + X86_VMOVDQU8Zmr = 7807, + X86_VMOVDQU8Zmrk = 7808, + X86_VMOVDQU8Zrm = 7809, + X86_VMOVDQU8Zrmk = 7810, + X86_VMOVDQU8Zrmkz = 7811, + X86_VMOVDQU8Zrr = 7812, + X86_VMOVDQU8Zrr_REV = 7813, + X86_VMOVDQU8Zrrk = 7814, + X86_VMOVDQU8Zrrk_REV = 7815, + X86_VMOVDQU8Zrrkz = 7816, + X86_VMOVDQU8Zrrkz_REV = 7817, + X86_VMOVDQUYmr = 7818, + X86_VMOVDQUYrm = 7819, + X86_VMOVDQUYrr = 7820, + X86_VMOVDQUYrr_REV = 7821, + X86_VMOVDQUmr = 7822, + X86_VMOVDQUrm = 7823, + X86_VMOVDQUrr = 7824, + X86_VMOVDQUrr_REV = 7825, + X86_VMOVHLPSZrr = 7826, + X86_VMOVHLPSrr = 7827, + X86_VMOVHPDZ128mr = 7828, + X86_VMOVHPDZ128rm = 7829, + X86_VMOVHPDmr = 7830, + X86_VMOVHPDrm = 7831, + X86_VMOVHPSZ128mr = 7832, + X86_VMOVHPSZ128rm = 7833, + X86_VMOVHPSmr = 7834, + X86_VMOVHPSrm = 7835, + X86_VMOVLHPSZrr = 7836, + X86_VMOVLHPSrr = 7837, + X86_VMOVLPDZ128mr = 7838, + X86_VMOVLPDZ128rm = 7839, + X86_VMOVLPDmr = 7840, + X86_VMOVLPDrm = 7841, + X86_VMOVLPSZ128mr = 7842, + X86_VMOVLPSZ128rm = 7843, + X86_VMOVLPSmr = 7844, + X86_VMOVLPSrm = 7845, + X86_VMOVMSKPDYrr = 7846, + X86_VMOVMSKPDrr = 7847, + X86_VMOVMSKPSYrr = 7848, + X86_VMOVMSKPSrr = 7849, + X86_VMOVNTDQAYrm = 7850, + X86_VMOVNTDQAZ128rm = 7851, + X86_VMOVNTDQAZ256rm = 7852, + X86_VMOVNTDQAZrm = 7853, + X86_VMOVNTDQArm = 7854, + X86_VMOVNTDQYmr = 7855, + X86_VMOVNTDQZ128mr = 7856, + X86_VMOVNTDQZ256mr = 7857, + X86_VMOVNTDQZmr = 7858, + X86_VMOVNTDQmr = 7859, + X86_VMOVNTPDYmr = 7860, + X86_VMOVNTPDZ128mr = 7861, + X86_VMOVNTPDZ256mr = 7862, + X86_VMOVNTPDZmr = 7863, + X86_VMOVNTPDmr = 7864, + X86_VMOVNTPSYmr = 7865, + X86_VMOVNTPSZ128mr = 7866, + X86_VMOVNTPSZ256mr = 7867, + X86_VMOVNTPSZmr = 7868, + X86_VMOVNTPSmr = 7869, + X86_VMOVPDI2DIZmr = 7870, + X86_VMOVPDI2DIZrr = 7871, + X86_VMOVPDI2DImr = 7872, + X86_VMOVPDI2DIrr = 7873, + X86_VMOVPQI2QIZmr = 7874, + X86_VMOVPQI2QIZrr = 7875, + X86_VMOVPQI2QImr = 7876, + X86_VMOVPQI2QIrr = 7877, + X86_VMOVPQIto64Zmr = 7878, + X86_VMOVPQIto64Zrr = 7879, + X86_VMOVPQIto64mr = 7880, + X86_VMOVPQIto64rr = 7881, + X86_VMOVQI2PQIZrm = 7882, + X86_VMOVQI2PQIrm = 7883, + X86_VMOVSDZmr = 7884, + X86_VMOVSDZmrk = 7885, + X86_VMOVSDZrm = 7886, + X86_VMOVSDZrmk = 7887, + X86_VMOVSDZrmkz = 7888, + X86_VMOVSDZrr = 7889, + X86_VMOVSDZrr_REV = 7890, + X86_VMOVSDZrrk = 7891, + X86_VMOVSDZrrk_REV = 7892, + X86_VMOVSDZrrkz = 7893, + X86_VMOVSDZrrkz_REV = 7894, + X86_VMOVSDmr = 7895, + X86_VMOVSDrm = 7896, + X86_VMOVSDrr = 7897, + X86_VMOVSDrr_REV = 7898, + X86_VMOVSDto64Zmr = 7899, + X86_VMOVSDto64Zrr = 7900, + X86_VMOVSDto64mr = 7901, + X86_VMOVSDto64rr = 7902, + X86_VMOVSHDUPYrm = 7903, + X86_VMOVSHDUPYrr = 7904, + X86_VMOVSHDUPZ128rm = 7905, + X86_VMOVSHDUPZ128rmk = 7906, + X86_VMOVSHDUPZ128rmkz = 7907, + X86_VMOVSHDUPZ128rr = 7908, + X86_VMOVSHDUPZ128rrk = 7909, + X86_VMOVSHDUPZ128rrkz = 7910, + X86_VMOVSHDUPZ256rm = 7911, + X86_VMOVSHDUPZ256rmk = 7912, + X86_VMOVSHDUPZ256rmkz = 7913, + X86_VMOVSHDUPZ256rr = 7914, + X86_VMOVSHDUPZ256rrk = 7915, + X86_VMOVSHDUPZ256rrkz = 7916, + X86_VMOVSHDUPZrm = 7917, + X86_VMOVSHDUPZrmk = 7918, + X86_VMOVSHDUPZrmkz = 7919, + X86_VMOVSHDUPZrr = 7920, + X86_VMOVSHDUPZrrk = 7921, + X86_VMOVSHDUPZrrkz = 7922, + X86_VMOVSHDUPrm = 7923, + X86_VMOVSHDUPrr = 7924, + X86_VMOVSLDUPYrm = 7925, + X86_VMOVSLDUPYrr = 7926, + X86_VMOVSLDUPZ128rm = 7927, + X86_VMOVSLDUPZ128rmk = 7928, + X86_VMOVSLDUPZ128rmkz = 7929, + X86_VMOVSLDUPZ128rr = 7930, + X86_VMOVSLDUPZ128rrk = 7931, + X86_VMOVSLDUPZ128rrkz = 7932, + X86_VMOVSLDUPZ256rm = 7933, + X86_VMOVSLDUPZ256rmk = 7934, + X86_VMOVSLDUPZ256rmkz = 7935, + X86_VMOVSLDUPZ256rr = 7936, + X86_VMOVSLDUPZ256rrk = 7937, + X86_VMOVSLDUPZ256rrkz = 7938, + X86_VMOVSLDUPZrm = 7939, + X86_VMOVSLDUPZrmk = 7940, + X86_VMOVSLDUPZrmkz = 7941, + X86_VMOVSLDUPZrr = 7942, + X86_VMOVSLDUPZrrk = 7943, + X86_VMOVSLDUPZrrkz = 7944, + X86_VMOVSLDUPrm = 7945, + X86_VMOVSLDUPrr = 7946, + X86_VMOVSS2DIZmr = 7947, + X86_VMOVSS2DIZrr = 7948, + X86_VMOVSS2DImr = 7949, + X86_VMOVSS2DIrr = 7950, + X86_VMOVSSZmr = 7951, + X86_VMOVSSZmrk = 7952, + X86_VMOVSSZrm = 7953, + X86_VMOVSSZrmk = 7954, + X86_VMOVSSZrmkz = 7955, + X86_VMOVSSZrr = 7956, + X86_VMOVSSZrr_REV = 7957, + X86_VMOVSSZrrk = 7958, + X86_VMOVSSZrrk_REV = 7959, + X86_VMOVSSZrrkz = 7960, + X86_VMOVSSZrrkz_REV = 7961, + X86_VMOVSSmr = 7962, + X86_VMOVSSrm = 7963, + X86_VMOVSSrr = 7964, + X86_VMOVSSrr_REV = 7965, + X86_VMOVUPDYmr = 7966, + X86_VMOVUPDYrm = 7967, + X86_VMOVUPDYrr = 7968, + X86_VMOVUPDYrr_REV = 7969, + X86_VMOVUPDZ128mr = 7970, + X86_VMOVUPDZ128mrk = 7971, + X86_VMOVUPDZ128rm = 7972, + X86_VMOVUPDZ128rmk = 7973, + X86_VMOVUPDZ128rmkz = 7974, + X86_VMOVUPDZ128rr = 7975, + X86_VMOVUPDZ128rr_REV = 7976, + X86_VMOVUPDZ128rrk = 7977, + X86_VMOVUPDZ128rrk_REV = 7978, + X86_VMOVUPDZ128rrkz = 7979, + X86_VMOVUPDZ128rrkz_REV = 7980, + X86_VMOVUPDZ256mr = 7981, + X86_VMOVUPDZ256mrk = 7982, + X86_VMOVUPDZ256rm = 7983, + X86_VMOVUPDZ256rmk = 7984, + X86_VMOVUPDZ256rmkz = 7985, + X86_VMOVUPDZ256rr = 7986, + X86_VMOVUPDZ256rr_REV = 7987, + X86_VMOVUPDZ256rrk = 7988, + X86_VMOVUPDZ256rrk_REV = 7989, + X86_VMOVUPDZ256rrkz = 7990, + X86_VMOVUPDZ256rrkz_REV = 7991, + X86_VMOVUPDZmr = 7992, + X86_VMOVUPDZmrk = 7993, + X86_VMOVUPDZrm = 7994, + X86_VMOVUPDZrmk = 7995, + X86_VMOVUPDZrmkz = 7996, + X86_VMOVUPDZrr = 7997, + X86_VMOVUPDZrr_REV = 7998, + X86_VMOVUPDZrrk = 7999, + X86_VMOVUPDZrrk_REV = 8000, + X86_VMOVUPDZrrkz = 8001, + X86_VMOVUPDZrrkz_REV = 8002, + X86_VMOVUPDmr = 8003, + X86_VMOVUPDrm = 8004, + X86_VMOVUPDrr = 8005, + X86_VMOVUPDrr_REV = 8006, + X86_VMOVUPSYmr = 8007, + X86_VMOVUPSYrm = 8008, + X86_VMOVUPSYrr = 8009, + X86_VMOVUPSYrr_REV = 8010, + X86_VMOVUPSZ128mr = 8011, + X86_VMOVUPSZ128mrk = 8012, + X86_VMOVUPSZ128rm = 8013, + X86_VMOVUPSZ128rmk = 8014, + X86_VMOVUPSZ128rmkz = 8015, + X86_VMOVUPSZ128rr = 8016, + X86_VMOVUPSZ128rr_REV = 8017, + X86_VMOVUPSZ128rrk = 8018, + X86_VMOVUPSZ128rrk_REV = 8019, + X86_VMOVUPSZ128rrkz = 8020, + X86_VMOVUPSZ128rrkz_REV = 8021, + X86_VMOVUPSZ256mr = 8022, + X86_VMOVUPSZ256mrk = 8023, + X86_VMOVUPSZ256rm = 8024, + X86_VMOVUPSZ256rmk = 8025, + X86_VMOVUPSZ256rmkz = 8026, + X86_VMOVUPSZ256rr = 8027, + X86_VMOVUPSZ256rr_REV = 8028, + X86_VMOVUPSZ256rrk = 8029, + X86_VMOVUPSZ256rrk_REV = 8030, + X86_VMOVUPSZ256rrkz = 8031, + X86_VMOVUPSZ256rrkz_REV = 8032, + X86_VMOVUPSZmr = 8033, + X86_VMOVUPSZmrk = 8034, + X86_VMOVUPSZrm = 8035, + X86_VMOVUPSZrmk = 8036, + X86_VMOVUPSZrmkz = 8037, + X86_VMOVUPSZrr = 8038, + X86_VMOVUPSZrr_REV = 8039, + X86_VMOVUPSZrrk = 8040, + X86_VMOVUPSZrrk_REV = 8041, + X86_VMOVUPSZrrkz = 8042, + X86_VMOVUPSZrrkz_REV = 8043, + X86_VMOVUPSmr = 8044, + X86_VMOVUPSrm = 8045, + X86_VMOVUPSrr = 8046, + X86_VMOVUPSrr_REV = 8047, + X86_VMOVZPQILo2PQIZrr = 8048, + X86_VMOVZPQILo2PQIrr = 8049, + X86_VMPSADBWYrmi = 8050, + X86_VMPSADBWYrri = 8051, + X86_VMPSADBWrmi = 8052, + X86_VMPSADBWrri = 8053, + X86_VMPTRLDm = 8054, + X86_VMPTRSTm = 8055, + X86_VMREAD32mr = 8056, + X86_VMREAD32rr = 8057, + X86_VMREAD64mr = 8058, + X86_VMREAD64rr = 8059, + X86_VMRESUME = 8060, + X86_VMRUN32 = 8061, + X86_VMRUN64 = 8062, + X86_VMSAVE32 = 8063, + X86_VMSAVE64 = 8064, + X86_VMULPDYrm = 8065, + X86_VMULPDYrr = 8066, + X86_VMULPDZ128rm = 8067, + X86_VMULPDZ128rmb = 8068, + X86_VMULPDZ128rmbk = 8069, + X86_VMULPDZ128rmbkz = 8070, + X86_VMULPDZ128rmk = 8071, + X86_VMULPDZ128rmkz = 8072, + X86_VMULPDZ128rr = 8073, + X86_VMULPDZ128rrk = 8074, + X86_VMULPDZ128rrkz = 8075, + X86_VMULPDZ256rm = 8076, + X86_VMULPDZ256rmb = 8077, + X86_VMULPDZ256rmbk = 8078, + X86_VMULPDZ256rmbkz = 8079, + X86_VMULPDZ256rmk = 8080, + X86_VMULPDZ256rmkz = 8081, + X86_VMULPDZ256rr = 8082, + X86_VMULPDZ256rrk = 8083, + X86_VMULPDZ256rrkz = 8084, + X86_VMULPDZrm = 8085, + X86_VMULPDZrmb = 8086, + X86_VMULPDZrmbk = 8087, + X86_VMULPDZrmbkz = 8088, + X86_VMULPDZrmk = 8089, + X86_VMULPDZrmkz = 8090, + X86_VMULPDZrr = 8091, + X86_VMULPDZrrb = 8092, + X86_VMULPDZrrbk = 8093, + X86_VMULPDZrrbkz = 8094, + X86_VMULPDZrrk = 8095, + X86_VMULPDZrrkz = 8096, + X86_VMULPDrm = 8097, + X86_VMULPDrr = 8098, + X86_VMULPSYrm = 8099, + X86_VMULPSYrr = 8100, + X86_VMULPSZ128rm = 8101, + X86_VMULPSZ128rmb = 8102, + X86_VMULPSZ128rmbk = 8103, + X86_VMULPSZ128rmbkz = 8104, + X86_VMULPSZ128rmk = 8105, + X86_VMULPSZ128rmkz = 8106, + X86_VMULPSZ128rr = 8107, + X86_VMULPSZ128rrk = 8108, + X86_VMULPSZ128rrkz = 8109, + X86_VMULPSZ256rm = 8110, + X86_VMULPSZ256rmb = 8111, + X86_VMULPSZ256rmbk = 8112, + X86_VMULPSZ256rmbkz = 8113, + X86_VMULPSZ256rmk = 8114, + X86_VMULPSZ256rmkz = 8115, + X86_VMULPSZ256rr = 8116, + X86_VMULPSZ256rrk = 8117, + X86_VMULPSZ256rrkz = 8118, + X86_VMULPSZrm = 8119, + X86_VMULPSZrmb = 8120, + X86_VMULPSZrmbk = 8121, + X86_VMULPSZrmbkz = 8122, + X86_VMULPSZrmk = 8123, + X86_VMULPSZrmkz = 8124, + X86_VMULPSZrr = 8125, + X86_VMULPSZrrb = 8126, + X86_VMULPSZrrbk = 8127, + X86_VMULPSZrrbkz = 8128, + X86_VMULPSZrrk = 8129, + X86_VMULPSZrrkz = 8130, + X86_VMULPSrm = 8131, + X86_VMULPSrr = 8132, + X86_VMULSDZrm = 8133, + X86_VMULSDZrm_Int = 8134, + X86_VMULSDZrm_Intk = 8135, + X86_VMULSDZrm_Intkz = 8136, + X86_VMULSDZrr = 8137, + X86_VMULSDZrr_Int = 8138, + X86_VMULSDZrr_Intk = 8139, + X86_VMULSDZrr_Intkz = 8140, + X86_VMULSDZrrb_Int = 8141, + X86_VMULSDZrrb_Intk = 8142, + X86_VMULSDZrrb_Intkz = 8143, + X86_VMULSDrm = 8144, + X86_VMULSDrm_Int = 8145, + X86_VMULSDrr = 8146, + X86_VMULSDrr_Int = 8147, + X86_VMULSSZrm = 8148, + X86_VMULSSZrm_Int = 8149, + X86_VMULSSZrm_Intk = 8150, + X86_VMULSSZrm_Intkz = 8151, + X86_VMULSSZrr = 8152, + X86_VMULSSZrr_Int = 8153, + X86_VMULSSZrr_Intk = 8154, + X86_VMULSSZrr_Intkz = 8155, + X86_VMULSSZrrb_Int = 8156, + X86_VMULSSZrrb_Intk = 8157, + X86_VMULSSZrrb_Intkz = 8158, + X86_VMULSSrm = 8159, + X86_VMULSSrm_Int = 8160, + X86_VMULSSrr = 8161, + X86_VMULSSrr_Int = 8162, + X86_VMWRITE32rm = 8163, + X86_VMWRITE32rr = 8164, + X86_VMWRITE64rm = 8165, + X86_VMWRITE64rr = 8166, + X86_VMXOFF = 8167, + X86_VMXON = 8168, + X86_VORPDYrm = 8169, + X86_VORPDYrr = 8170, + X86_VORPDZ128rm = 8171, + X86_VORPDZ128rmb = 8172, + X86_VORPDZ128rmbk = 8173, + X86_VORPDZ128rmbkz = 8174, + X86_VORPDZ128rmk = 8175, + X86_VORPDZ128rmkz = 8176, + X86_VORPDZ128rr = 8177, + X86_VORPDZ128rrk = 8178, + X86_VORPDZ128rrkz = 8179, + X86_VORPDZ256rm = 8180, + X86_VORPDZ256rmb = 8181, + X86_VORPDZ256rmbk = 8182, + X86_VORPDZ256rmbkz = 8183, + X86_VORPDZ256rmk = 8184, + X86_VORPDZ256rmkz = 8185, + X86_VORPDZ256rr = 8186, + X86_VORPDZ256rrk = 8187, + X86_VORPDZ256rrkz = 8188, + X86_VORPDZrm = 8189, + X86_VORPDZrmb = 8190, + X86_VORPDZrmbk = 8191, + X86_VORPDZrmbkz = 8192, + X86_VORPDZrmk = 8193, + X86_VORPDZrmkz = 8194, + X86_VORPDZrr = 8195, + X86_VORPDZrrk = 8196, + X86_VORPDZrrkz = 8197, + X86_VORPDrm = 8198, + X86_VORPDrr = 8199, + X86_VORPSYrm = 8200, + X86_VORPSYrr = 8201, + X86_VORPSZ128rm = 8202, + X86_VORPSZ128rmb = 8203, + X86_VORPSZ128rmbk = 8204, + X86_VORPSZ128rmbkz = 8205, + X86_VORPSZ128rmk = 8206, + X86_VORPSZ128rmkz = 8207, + X86_VORPSZ128rr = 8208, + X86_VORPSZ128rrk = 8209, + X86_VORPSZ128rrkz = 8210, + X86_VORPSZ256rm = 8211, + X86_VORPSZ256rmb = 8212, + X86_VORPSZ256rmbk = 8213, + X86_VORPSZ256rmbkz = 8214, + X86_VORPSZ256rmk = 8215, + X86_VORPSZ256rmkz = 8216, + X86_VORPSZ256rr = 8217, + X86_VORPSZ256rrk = 8218, + X86_VORPSZ256rrkz = 8219, + X86_VORPSZrm = 8220, + X86_VORPSZrmb = 8221, + X86_VORPSZrmbk = 8222, + X86_VORPSZrmbkz = 8223, + X86_VORPSZrmk = 8224, + X86_VORPSZrmkz = 8225, + X86_VORPSZrr = 8226, + X86_VORPSZrrk = 8227, + X86_VORPSZrrkz = 8228, + X86_VORPSrm = 8229, + X86_VORPSrr = 8230, + X86_VP4DPWSSDSrm = 8231, + X86_VP4DPWSSDSrmk = 8232, + X86_VP4DPWSSDSrmkz = 8233, + X86_VP4DPWSSDrm = 8234, + X86_VP4DPWSSDrmk = 8235, + X86_VP4DPWSSDrmkz = 8236, + X86_VPABSBYrm = 8237, + X86_VPABSBYrr = 8238, + X86_VPABSBZ128rm = 8239, + X86_VPABSBZ128rmk = 8240, + X86_VPABSBZ128rmkz = 8241, + X86_VPABSBZ128rr = 8242, + X86_VPABSBZ128rrk = 8243, + X86_VPABSBZ128rrkz = 8244, + X86_VPABSBZ256rm = 8245, + X86_VPABSBZ256rmk = 8246, + X86_VPABSBZ256rmkz = 8247, + X86_VPABSBZ256rr = 8248, + X86_VPABSBZ256rrk = 8249, + X86_VPABSBZ256rrkz = 8250, + X86_VPABSBZrm = 8251, + X86_VPABSBZrmk = 8252, + X86_VPABSBZrmkz = 8253, + X86_VPABSBZrr = 8254, + X86_VPABSBZrrk = 8255, + X86_VPABSBZrrkz = 8256, + X86_VPABSBrm = 8257, + X86_VPABSBrr = 8258, + X86_VPABSDYrm = 8259, + X86_VPABSDYrr = 8260, + X86_VPABSDZ128rm = 8261, + X86_VPABSDZ128rmb = 8262, + X86_VPABSDZ128rmbk = 8263, + X86_VPABSDZ128rmbkz = 8264, + X86_VPABSDZ128rmk = 8265, + X86_VPABSDZ128rmkz = 8266, + X86_VPABSDZ128rr = 8267, + X86_VPABSDZ128rrk = 8268, + X86_VPABSDZ128rrkz = 8269, + X86_VPABSDZ256rm = 8270, + X86_VPABSDZ256rmb = 8271, + X86_VPABSDZ256rmbk = 8272, + X86_VPABSDZ256rmbkz = 8273, + X86_VPABSDZ256rmk = 8274, + X86_VPABSDZ256rmkz = 8275, + X86_VPABSDZ256rr = 8276, + X86_VPABSDZ256rrk = 8277, + X86_VPABSDZ256rrkz = 8278, + X86_VPABSDZrm = 8279, + X86_VPABSDZrmb = 8280, + X86_VPABSDZrmbk = 8281, + X86_VPABSDZrmbkz = 8282, + X86_VPABSDZrmk = 8283, + X86_VPABSDZrmkz = 8284, + X86_VPABSDZrr = 8285, + X86_VPABSDZrrk = 8286, + X86_VPABSDZrrkz = 8287, + X86_VPABSDrm = 8288, + X86_VPABSDrr = 8289, + X86_VPABSQZ128rm = 8290, + X86_VPABSQZ128rmb = 8291, + X86_VPABSQZ128rmbk = 8292, + X86_VPABSQZ128rmbkz = 8293, + X86_VPABSQZ128rmk = 8294, + X86_VPABSQZ128rmkz = 8295, + X86_VPABSQZ128rr = 8296, + X86_VPABSQZ128rrk = 8297, + X86_VPABSQZ128rrkz = 8298, + X86_VPABSQZ256rm = 8299, + X86_VPABSQZ256rmb = 8300, + X86_VPABSQZ256rmbk = 8301, + X86_VPABSQZ256rmbkz = 8302, + X86_VPABSQZ256rmk = 8303, + X86_VPABSQZ256rmkz = 8304, + X86_VPABSQZ256rr = 8305, + X86_VPABSQZ256rrk = 8306, + X86_VPABSQZ256rrkz = 8307, + X86_VPABSQZrm = 8308, + X86_VPABSQZrmb = 8309, + X86_VPABSQZrmbk = 8310, + X86_VPABSQZrmbkz = 8311, + X86_VPABSQZrmk = 8312, + X86_VPABSQZrmkz = 8313, + X86_VPABSQZrr = 8314, + X86_VPABSQZrrk = 8315, + X86_VPABSQZrrkz = 8316, + X86_VPABSWYrm = 8317, + X86_VPABSWYrr = 8318, + X86_VPABSWZ128rm = 8319, + X86_VPABSWZ128rmk = 8320, + X86_VPABSWZ128rmkz = 8321, + X86_VPABSWZ128rr = 8322, + X86_VPABSWZ128rrk = 8323, + X86_VPABSWZ128rrkz = 8324, + X86_VPABSWZ256rm = 8325, + X86_VPABSWZ256rmk = 8326, + X86_VPABSWZ256rmkz = 8327, + X86_VPABSWZ256rr = 8328, + X86_VPABSWZ256rrk = 8329, + X86_VPABSWZ256rrkz = 8330, + X86_VPABSWZrm = 8331, + X86_VPABSWZrmk = 8332, + X86_VPABSWZrmkz = 8333, + X86_VPABSWZrr = 8334, + X86_VPABSWZrrk = 8335, + X86_VPABSWZrrkz = 8336, + X86_VPABSWrm = 8337, + X86_VPABSWrr = 8338, + X86_VPACKSSDWYrm = 8339, + X86_VPACKSSDWYrr = 8340, + X86_VPACKSSDWZ128rm = 8341, + X86_VPACKSSDWZ128rmb = 8342, + X86_VPACKSSDWZ128rmbk = 8343, + X86_VPACKSSDWZ128rmbkz = 8344, + X86_VPACKSSDWZ128rmk = 8345, + X86_VPACKSSDWZ128rmkz = 8346, + X86_VPACKSSDWZ128rr = 8347, + X86_VPACKSSDWZ128rrk = 8348, + X86_VPACKSSDWZ128rrkz = 8349, + X86_VPACKSSDWZ256rm = 8350, + X86_VPACKSSDWZ256rmb = 8351, + X86_VPACKSSDWZ256rmbk = 8352, + X86_VPACKSSDWZ256rmbkz = 8353, + X86_VPACKSSDWZ256rmk = 8354, + X86_VPACKSSDWZ256rmkz = 8355, + X86_VPACKSSDWZ256rr = 8356, + X86_VPACKSSDWZ256rrk = 8357, + X86_VPACKSSDWZ256rrkz = 8358, + X86_VPACKSSDWZrm = 8359, + X86_VPACKSSDWZrmb = 8360, + X86_VPACKSSDWZrmbk = 8361, + X86_VPACKSSDWZrmbkz = 8362, + X86_VPACKSSDWZrmk = 8363, + X86_VPACKSSDWZrmkz = 8364, + X86_VPACKSSDWZrr = 8365, + X86_VPACKSSDWZrrk = 8366, + X86_VPACKSSDWZrrkz = 8367, + X86_VPACKSSDWrm = 8368, + X86_VPACKSSDWrr = 8369, + X86_VPACKSSWBYrm = 8370, + X86_VPACKSSWBYrr = 8371, + X86_VPACKSSWBZ128rm = 8372, + X86_VPACKSSWBZ128rmk = 8373, + X86_VPACKSSWBZ128rmkz = 8374, + X86_VPACKSSWBZ128rr = 8375, + X86_VPACKSSWBZ128rrk = 8376, + X86_VPACKSSWBZ128rrkz = 8377, + X86_VPACKSSWBZ256rm = 8378, + X86_VPACKSSWBZ256rmk = 8379, + X86_VPACKSSWBZ256rmkz = 8380, + X86_VPACKSSWBZ256rr = 8381, + X86_VPACKSSWBZ256rrk = 8382, + X86_VPACKSSWBZ256rrkz = 8383, + X86_VPACKSSWBZrm = 8384, + X86_VPACKSSWBZrmk = 8385, + X86_VPACKSSWBZrmkz = 8386, + X86_VPACKSSWBZrr = 8387, + X86_VPACKSSWBZrrk = 8388, + X86_VPACKSSWBZrrkz = 8389, + X86_VPACKSSWBrm = 8390, + X86_VPACKSSWBrr = 8391, + X86_VPACKUSDWYrm = 8392, + X86_VPACKUSDWYrr = 8393, + X86_VPACKUSDWZ128rm = 8394, + X86_VPACKUSDWZ128rmb = 8395, + X86_VPACKUSDWZ128rmbk = 8396, + X86_VPACKUSDWZ128rmbkz = 8397, + X86_VPACKUSDWZ128rmk = 8398, + X86_VPACKUSDWZ128rmkz = 8399, + X86_VPACKUSDWZ128rr = 8400, + X86_VPACKUSDWZ128rrk = 8401, + X86_VPACKUSDWZ128rrkz = 8402, + X86_VPACKUSDWZ256rm = 8403, + X86_VPACKUSDWZ256rmb = 8404, + X86_VPACKUSDWZ256rmbk = 8405, + X86_VPACKUSDWZ256rmbkz = 8406, + X86_VPACKUSDWZ256rmk = 8407, + X86_VPACKUSDWZ256rmkz = 8408, + X86_VPACKUSDWZ256rr = 8409, + X86_VPACKUSDWZ256rrk = 8410, + X86_VPACKUSDWZ256rrkz = 8411, + X86_VPACKUSDWZrm = 8412, + X86_VPACKUSDWZrmb = 8413, + X86_VPACKUSDWZrmbk = 8414, + X86_VPACKUSDWZrmbkz = 8415, + X86_VPACKUSDWZrmk = 8416, + X86_VPACKUSDWZrmkz = 8417, + X86_VPACKUSDWZrr = 8418, + X86_VPACKUSDWZrrk = 8419, + X86_VPACKUSDWZrrkz = 8420, + X86_VPACKUSDWrm = 8421, + X86_VPACKUSDWrr = 8422, + X86_VPACKUSWBYrm = 8423, + X86_VPACKUSWBYrr = 8424, + X86_VPACKUSWBZ128rm = 8425, + X86_VPACKUSWBZ128rmk = 8426, + X86_VPACKUSWBZ128rmkz = 8427, + X86_VPACKUSWBZ128rr = 8428, + X86_VPACKUSWBZ128rrk = 8429, + X86_VPACKUSWBZ128rrkz = 8430, + X86_VPACKUSWBZ256rm = 8431, + X86_VPACKUSWBZ256rmk = 8432, + X86_VPACKUSWBZ256rmkz = 8433, + X86_VPACKUSWBZ256rr = 8434, + X86_VPACKUSWBZ256rrk = 8435, + X86_VPACKUSWBZ256rrkz = 8436, + X86_VPACKUSWBZrm = 8437, + X86_VPACKUSWBZrmk = 8438, + X86_VPACKUSWBZrmkz = 8439, + X86_VPACKUSWBZrr = 8440, + X86_VPACKUSWBZrrk = 8441, + X86_VPACKUSWBZrrkz = 8442, + X86_VPACKUSWBrm = 8443, + X86_VPACKUSWBrr = 8444, + X86_VPADDBYrm = 8445, + X86_VPADDBYrr = 8446, + X86_VPADDBZ128rm = 8447, + X86_VPADDBZ128rmk = 8448, + X86_VPADDBZ128rmkz = 8449, + X86_VPADDBZ128rr = 8450, + X86_VPADDBZ128rrk = 8451, + X86_VPADDBZ128rrkz = 8452, + X86_VPADDBZ256rm = 8453, + X86_VPADDBZ256rmk = 8454, + X86_VPADDBZ256rmkz = 8455, + X86_VPADDBZ256rr = 8456, + X86_VPADDBZ256rrk = 8457, + X86_VPADDBZ256rrkz = 8458, + X86_VPADDBZrm = 8459, + X86_VPADDBZrmk = 8460, + X86_VPADDBZrmkz = 8461, + X86_VPADDBZrr = 8462, + X86_VPADDBZrrk = 8463, + X86_VPADDBZrrkz = 8464, + X86_VPADDBrm = 8465, + X86_VPADDBrr = 8466, + X86_VPADDDYrm = 8467, + X86_VPADDDYrr = 8468, + X86_VPADDDZ128rm = 8469, + X86_VPADDDZ128rmb = 8470, + X86_VPADDDZ128rmbk = 8471, + X86_VPADDDZ128rmbkz = 8472, + X86_VPADDDZ128rmk = 8473, + X86_VPADDDZ128rmkz = 8474, + X86_VPADDDZ128rr = 8475, + X86_VPADDDZ128rrk = 8476, + X86_VPADDDZ128rrkz = 8477, + X86_VPADDDZ256rm = 8478, + X86_VPADDDZ256rmb = 8479, + X86_VPADDDZ256rmbk = 8480, + X86_VPADDDZ256rmbkz = 8481, + X86_VPADDDZ256rmk = 8482, + X86_VPADDDZ256rmkz = 8483, + X86_VPADDDZ256rr = 8484, + X86_VPADDDZ256rrk = 8485, + X86_VPADDDZ256rrkz = 8486, + X86_VPADDDZrm = 8487, + X86_VPADDDZrmb = 8488, + X86_VPADDDZrmbk = 8489, + X86_VPADDDZrmbkz = 8490, + X86_VPADDDZrmk = 8491, + X86_VPADDDZrmkz = 8492, + X86_VPADDDZrr = 8493, + X86_VPADDDZrrk = 8494, + X86_VPADDDZrrkz = 8495, + X86_VPADDDrm = 8496, + X86_VPADDDrr = 8497, + X86_VPADDQYrm = 8498, + X86_VPADDQYrr = 8499, + X86_VPADDQZ128rm = 8500, + X86_VPADDQZ128rmb = 8501, + X86_VPADDQZ128rmbk = 8502, + X86_VPADDQZ128rmbkz = 8503, + X86_VPADDQZ128rmk = 8504, + X86_VPADDQZ128rmkz = 8505, + X86_VPADDQZ128rr = 8506, + X86_VPADDQZ128rrk = 8507, + X86_VPADDQZ128rrkz = 8508, + X86_VPADDQZ256rm = 8509, + X86_VPADDQZ256rmb = 8510, + X86_VPADDQZ256rmbk = 8511, + X86_VPADDQZ256rmbkz = 8512, + X86_VPADDQZ256rmk = 8513, + X86_VPADDQZ256rmkz = 8514, + X86_VPADDQZ256rr = 8515, + X86_VPADDQZ256rrk = 8516, + X86_VPADDQZ256rrkz = 8517, + X86_VPADDQZrm = 8518, + X86_VPADDQZrmb = 8519, + X86_VPADDQZrmbk = 8520, + X86_VPADDQZrmbkz = 8521, + X86_VPADDQZrmk = 8522, + X86_VPADDQZrmkz = 8523, + X86_VPADDQZrr = 8524, + X86_VPADDQZrrk = 8525, + X86_VPADDQZrrkz = 8526, + X86_VPADDQrm = 8527, + X86_VPADDQrr = 8528, + X86_VPADDSBYrm = 8529, + X86_VPADDSBYrr = 8530, + X86_VPADDSBZ128rm = 8531, + X86_VPADDSBZ128rmk = 8532, + X86_VPADDSBZ128rmkz = 8533, + X86_VPADDSBZ128rr = 8534, + X86_VPADDSBZ128rrk = 8535, + X86_VPADDSBZ128rrkz = 8536, + X86_VPADDSBZ256rm = 8537, + X86_VPADDSBZ256rmk = 8538, + X86_VPADDSBZ256rmkz = 8539, + X86_VPADDSBZ256rr = 8540, + X86_VPADDSBZ256rrk = 8541, + X86_VPADDSBZ256rrkz = 8542, + X86_VPADDSBZrm = 8543, + X86_VPADDSBZrmk = 8544, + X86_VPADDSBZrmkz = 8545, + X86_VPADDSBZrr = 8546, + X86_VPADDSBZrrk = 8547, + X86_VPADDSBZrrkz = 8548, + X86_VPADDSBrm = 8549, + X86_VPADDSBrr = 8550, + X86_VPADDSWYrm = 8551, + X86_VPADDSWYrr = 8552, + X86_VPADDSWZ128rm = 8553, + X86_VPADDSWZ128rmk = 8554, + X86_VPADDSWZ128rmkz = 8555, + X86_VPADDSWZ128rr = 8556, + X86_VPADDSWZ128rrk = 8557, + X86_VPADDSWZ128rrkz = 8558, + X86_VPADDSWZ256rm = 8559, + X86_VPADDSWZ256rmk = 8560, + X86_VPADDSWZ256rmkz = 8561, + X86_VPADDSWZ256rr = 8562, + X86_VPADDSWZ256rrk = 8563, + X86_VPADDSWZ256rrkz = 8564, + X86_VPADDSWZrm = 8565, + X86_VPADDSWZrmk = 8566, + X86_VPADDSWZrmkz = 8567, + X86_VPADDSWZrr = 8568, + X86_VPADDSWZrrk = 8569, + X86_VPADDSWZrrkz = 8570, + X86_VPADDSWrm = 8571, + X86_VPADDSWrr = 8572, + X86_VPADDUSBYrm = 8573, + X86_VPADDUSBYrr = 8574, + X86_VPADDUSBZ128rm = 8575, + X86_VPADDUSBZ128rmk = 8576, + X86_VPADDUSBZ128rmkz = 8577, + X86_VPADDUSBZ128rr = 8578, + X86_VPADDUSBZ128rrk = 8579, + X86_VPADDUSBZ128rrkz = 8580, + X86_VPADDUSBZ256rm = 8581, + X86_VPADDUSBZ256rmk = 8582, + X86_VPADDUSBZ256rmkz = 8583, + X86_VPADDUSBZ256rr = 8584, + X86_VPADDUSBZ256rrk = 8585, + X86_VPADDUSBZ256rrkz = 8586, + X86_VPADDUSBZrm = 8587, + X86_VPADDUSBZrmk = 8588, + X86_VPADDUSBZrmkz = 8589, + X86_VPADDUSBZrr = 8590, + X86_VPADDUSBZrrk = 8591, + X86_VPADDUSBZrrkz = 8592, + X86_VPADDUSBrm = 8593, + X86_VPADDUSBrr = 8594, + X86_VPADDUSWYrm = 8595, + X86_VPADDUSWYrr = 8596, + X86_VPADDUSWZ128rm = 8597, + X86_VPADDUSWZ128rmk = 8598, + X86_VPADDUSWZ128rmkz = 8599, + X86_VPADDUSWZ128rr = 8600, + X86_VPADDUSWZ128rrk = 8601, + X86_VPADDUSWZ128rrkz = 8602, + X86_VPADDUSWZ256rm = 8603, + X86_VPADDUSWZ256rmk = 8604, + X86_VPADDUSWZ256rmkz = 8605, + X86_VPADDUSWZ256rr = 8606, + X86_VPADDUSWZ256rrk = 8607, + X86_VPADDUSWZ256rrkz = 8608, + X86_VPADDUSWZrm = 8609, + X86_VPADDUSWZrmk = 8610, + X86_VPADDUSWZrmkz = 8611, + X86_VPADDUSWZrr = 8612, + X86_VPADDUSWZrrk = 8613, + X86_VPADDUSWZrrkz = 8614, + X86_VPADDUSWrm = 8615, + X86_VPADDUSWrr = 8616, + X86_VPADDWYrm = 8617, + X86_VPADDWYrr = 8618, + X86_VPADDWZ128rm = 8619, + X86_VPADDWZ128rmk = 8620, + X86_VPADDWZ128rmkz = 8621, + X86_VPADDWZ128rr = 8622, + X86_VPADDWZ128rrk = 8623, + X86_VPADDWZ128rrkz = 8624, + X86_VPADDWZ256rm = 8625, + X86_VPADDWZ256rmk = 8626, + X86_VPADDWZ256rmkz = 8627, + X86_VPADDWZ256rr = 8628, + X86_VPADDWZ256rrk = 8629, + X86_VPADDWZ256rrkz = 8630, + X86_VPADDWZrm = 8631, + X86_VPADDWZrmk = 8632, + X86_VPADDWZrmkz = 8633, + X86_VPADDWZrr = 8634, + X86_VPADDWZrrk = 8635, + X86_VPADDWZrrkz = 8636, + X86_VPADDWrm = 8637, + X86_VPADDWrr = 8638, + X86_VPALIGNRYrmi = 8639, + X86_VPALIGNRYrri = 8640, + X86_VPALIGNRZ128rmi = 8641, + X86_VPALIGNRZ128rmik = 8642, + X86_VPALIGNRZ128rmikz = 8643, + X86_VPALIGNRZ128rri = 8644, + X86_VPALIGNRZ128rrik = 8645, + X86_VPALIGNRZ128rrikz = 8646, + X86_VPALIGNRZ256rmi = 8647, + X86_VPALIGNRZ256rmik = 8648, + X86_VPALIGNRZ256rmikz = 8649, + X86_VPALIGNRZ256rri = 8650, + X86_VPALIGNRZ256rrik = 8651, + X86_VPALIGNRZ256rrikz = 8652, + X86_VPALIGNRZrmi = 8653, + X86_VPALIGNRZrmik = 8654, + X86_VPALIGNRZrmikz = 8655, + X86_VPALIGNRZrri = 8656, + X86_VPALIGNRZrrik = 8657, + X86_VPALIGNRZrrikz = 8658, + X86_VPALIGNRrmi = 8659, + X86_VPALIGNRrri = 8660, + X86_VPANDDZ128rm = 8661, + X86_VPANDDZ128rmb = 8662, + X86_VPANDDZ128rmbk = 8663, + X86_VPANDDZ128rmbkz = 8664, + X86_VPANDDZ128rmk = 8665, + X86_VPANDDZ128rmkz = 8666, + X86_VPANDDZ128rr = 8667, + X86_VPANDDZ128rrk = 8668, + X86_VPANDDZ128rrkz = 8669, + X86_VPANDDZ256rm = 8670, + X86_VPANDDZ256rmb = 8671, + X86_VPANDDZ256rmbk = 8672, + X86_VPANDDZ256rmbkz = 8673, + X86_VPANDDZ256rmk = 8674, + X86_VPANDDZ256rmkz = 8675, + X86_VPANDDZ256rr = 8676, + X86_VPANDDZ256rrk = 8677, + X86_VPANDDZ256rrkz = 8678, + X86_VPANDDZrm = 8679, + X86_VPANDDZrmb = 8680, + X86_VPANDDZrmbk = 8681, + X86_VPANDDZrmbkz = 8682, + X86_VPANDDZrmk = 8683, + X86_VPANDDZrmkz = 8684, + X86_VPANDDZrr = 8685, + X86_VPANDDZrrk = 8686, + X86_VPANDDZrrkz = 8687, + X86_VPANDNDZ128rm = 8688, + X86_VPANDNDZ128rmb = 8689, + X86_VPANDNDZ128rmbk = 8690, + X86_VPANDNDZ128rmbkz = 8691, + X86_VPANDNDZ128rmk = 8692, + X86_VPANDNDZ128rmkz = 8693, + X86_VPANDNDZ128rr = 8694, + X86_VPANDNDZ128rrk = 8695, + X86_VPANDNDZ128rrkz = 8696, + X86_VPANDNDZ256rm = 8697, + X86_VPANDNDZ256rmb = 8698, + X86_VPANDNDZ256rmbk = 8699, + X86_VPANDNDZ256rmbkz = 8700, + X86_VPANDNDZ256rmk = 8701, + X86_VPANDNDZ256rmkz = 8702, + X86_VPANDNDZ256rr = 8703, + X86_VPANDNDZ256rrk = 8704, + X86_VPANDNDZ256rrkz = 8705, + X86_VPANDNDZrm = 8706, + X86_VPANDNDZrmb = 8707, + X86_VPANDNDZrmbk = 8708, + X86_VPANDNDZrmbkz = 8709, + X86_VPANDNDZrmk = 8710, + X86_VPANDNDZrmkz = 8711, + X86_VPANDNDZrr = 8712, + X86_VPANDNDZrrk = 8713, + X86_VPANDNDZrrkz = 8714, + X86_VPANDNQZ128rm = 8715, + X86_VPANDNQZ128rmb = 8716, + X86_VPANDNQZ128rmbk = 8717, + X86_VPANDNQZ128rmbkz = 8718, + X86_VPANDNQZ128rmk = 8719, + X86_VPANDNQZ128rmkz = 8720, + X86_VPANDNQZ128rr = 8721, + X86_VPANDNQZ128rrk = 8722, + X86_VPANDNQZ128rrkz = 8723, + X86_VPANDNQZ256rm = 8724, + X86_VPANDNQZ256rmb = 8725, + X86_VPANDNQZ256rmbk = 8726, + X86_VPANDNQZ256rmbkz = 8727, + X86_VPANDNQZ256rmk = 8728, + X86_VPANDNQZ256rmkz = 8729, + X86_VPANDNQZ256rr = 8730, + X86_VPANDNQZ256rrk = 8731, + X86_VPANDNQZ256rrkz = 8732, + X86_VPANDNQZrm = 8733, + X86_VPANDNQZrmb = 8734, + X86_VPANDNQZrmbk = 8735, + X86_VPANDNQZrmbkz = 8736, + X86_VPANDNQZrmk = 8737, + X86_VPANDNQZrmkz = 8738, + X86_VPANDNQZrr = 8739, + X86_VPANDNQZrrk = 8740, + X86_VPANDNQZrrkz = 8741, + X86_VPANDNYrm = 8742, + X86_VPANDNYrr = 8743, + X86_VPANDNrm = 8744, + X86_VPANDNrr = 8745, + X86_VPANDQZ128rm = 8746, + X86_VPANDQZ128rmb = 8747, + X86_VPANDQZ128rmbk = 8748, + X86_VPANDQZ128rmbkz = 8749, + X86_VPANDQZ128rmk = 8750, + X86_VPANDQZ128rmkz = 8751, + X86_VPANDQZ128rr = 8752, + X86_VPANDQZ128rrk = 8753, + X86_VPANDQZ128rrkz = 8754, + X86_VPANDQZ256rm = 8755, + X86_VPANDQZ256rmb = 8756, + X86_VPANDQZ256rmbk = 8757, + X86_VPANDQZ256rmbkz = 8758, + X86_VPANDQZ256rmk = 8759, + X86_VPANDQZ256rmkz = 8760, + X86_VPANDQZ256rr = 8761, + X86_VPANDQZ256rrk = 8762, + X86_VPANDQZ256rrkz = 8763, + X86_VPANDQZrm = 8764, + X86_VPANDQZrmb = 8765, + X86_VPANDQZrmbk = 8766, + X86_VPANDQZrmbkz = 8767, + X86_VPANDQZrmk = 8768, + X86_VPANDQZrmkz = 8769, + X86_VPANDQZrr = 8770, + X86_VPANDQZrrk = 8771, + X86_VPANDQZrrkz = 8772, + X86_VPANDYrm = 8773, + X86_VPANDYrr = 8774, + X86_VPANDrm = 8775, + X86_VPANDrr = 8776, + X86_VPAVGBYrm = 8777, + X86_VPAVGBYrr = 8778, + X86_VPAVGBZ128rm = 8779, + X86_VPAVGBZ128rmk = 8780, + X86_VPAVGBZ128rmkz = 8781, + X86_VPAVGBZ128rr = 8782, + X86_VPAVGBZ128rrk = 8783, + X86_VPAVGBZ128rrkz = 8784, + X86_VPAVGBZ256rm = 8785, + X86_VPAVGBZ256rmk = 8786, + X86_VPAVGBZ256rmkz = 8787, + X86_VPAVGBZ256rr = 8788, + X86_VPAVGBZ256rrk = 8789, + X86_VPAVGBZ256rrkz = 8790, + X86_VPAVGBZrm = 8791, + X86_VPAVGBZrmk = 8792, + X86_VPAVGBZrmkz = 8793, + X86_VPAVGBZrr = 8794, + X86_VPAVGBZrrk = 8795, + X86_VPAVGBZrrkz = 8796, + X86_VPAVGBrm = 8797, + X86_VPAVGBrr = 8798, + X86_VPAVGWYrm = 8799, + X86_VPAVGWYrr = 8800, + X86_VPAVGWZ128rm = 8801, + X86_VPAVGWZ128rmk = 8802, + X86_VPAVGWZ128rmkz = 8803, + X86_VPAVGWZ128rr = 8804, + X86_VPAVGWZ128rrk = 8805, + X86_VPAVGWZ128rrkz = 8806, + X86_VPAVGWZ256rm = 8807, + X86_VPAVGWZ256rmk = 8808, + X86_VPAVGWZ256rmkz = 8809, + X86_VPAVGWZ256rr = 8810, + X86_VPAVGWZ256rrk = 8811, + X86_VPAVGWZ256rrkz = 8812, + X86_VPAVGWZrm = 8813, + X86_VPAVGWZrmk = 8814, + X86_VPAVGWZrmkz = 8815, + X86_VPAVGWZrr = 8816, + X86_VPAVGWZrrk = 8817, + X86_VPAVGWZrrkz = 8818, + X86_VPAVGWrm = 8819, + X86_VPAVGWrr = 8820, + X86_VPBLENDDYrmi = 8821, + X86_VPBLENDDYrri = 8822, + X86_VPBLENDDrmi = 8823, + X86_VPBLENDDrri = 8824, + X86_VPBLENDMBZ128rm = 8825, + X86_VPBLENDMBZ128rmk = 8826, + X86_VPBLENDMBZ128rmkz = 8827, + X86_VPBLENDMBZ128rr = 8828, + X86_VPBLENDMBZ128rrk = 8829, + X86_VPBLENDMBZ128rrkz = 8830, + X86_VPBLENDMBZ256rm = 8831, + X86_VPBLENDMBZ256rmk = 8832, + X86_VPBLENDMBZ256rmkz = 8833, + X86_VPBLENDMBZ256rr = 8834, + X86_VPBLENDMBZ256rrk = 8835, + X86_VPBLENDMBZ256rrkz = 8836, + X86_VPBLENDMBZrm = 8837, + X86_VPBLENDMBZrmk = 8838, + X86_VPBLENDMBZrmkz = 8839, + X86_VPBLENDMBZrr = 8840, + X86_VPBLENDMBZrrk = 8841, + X86_VPBLENDMBZrrkz = 8842, + X86_VPBLENDMDZ128rm = 8843, + X86_VPBLENDMDZ128rmb = 8844, + X86_VPBLENDMDZ128rmbk = 8845, + X86_VPBLENDMDZ128rmbkz = 8846, + X86_VPBLENDMDZ128rmk = 8847, + X86_VPBLENDMDZ128rmkz = 8848, + X86_VPBLENDMDZ128rr = 8849, + X86_VPBLENDMDZ128rrk = 8850, + X86_VPBLENDMDZ128rrkz = 8851, + X86_VPBLENDMDZ256rm = 8852, + X86_VPBLENDMDZ256rmb = 8853, + X86_VPBLENDMDZ256rmbk = 8854, + X86_VPBLENDMDZ256rmbkz = 8855, + X86_VPBLENDMDZ256rmk = 8856, + X86_VPBLENDMDZ256rmkz = 8857, + X86_VPBLENDMDZ256rr = 8858, + X86_VPBLENDMDZ256rrk = 8859, + X86_VPBLENDMDZ256rrkz = 8860, + X86_VPBLENDMDZrm = 8861, + X86_VPBLENDMDZrmb = 8862, + X86_VPBLENDMDZrmbk = 8863, + X86_VPBLENDMDZrmbkz = 8864, + X86_VPBLENDMDZrmk = 8865, + X86_VPBLENDMDZrmkz = 8866, + X86_VPBLENDMDZrr = 8867, + X86_VPBLENDMDZrrk = 8868, + X86_VPBLENDMDZrrkz = 8869, + X86_VPBLENDMQZ128rm = 8870, + X86_VPBLENDMQZ128rmb = 8871, + X86_VPBLENDMQZ128rmbk = 8872, + X86_VPBLENDMQZ128rmbkz = 8873, + X86_VPBLENDMQZ128rmk = 8874, + X86_VPBLENDMQZ128rmkz = 8875, + X86_VPBLENDMQZ128rr = 8876, + X86_VPBLENDMQZ128rrk = 8877, + X86_VPBLENDMQZ128rrkz = 8878, + X86_VPBLENDMQZ256rm = 8879, + X86_VPBLENDMQZ256rmb = 8880, + X86_VPBLENDMQZ256rmbk = 8881, + X86_VPBLENDMQZ256rmbkz = 8882, + X86_VPBLENDMQZ256rmk = 8883, + X86_VPBLENDMQZ256rmkz = 8884, + X86_VPBLENDMQZ256rr = 8885, + X86_VPBLENDMQZ256rrk = 8886, + X86_VPBLENDMQZ256rrkz = 8887, + X86_VPBLENDMQZrm = 8888, + X86_VPBLENDMQZrmb = 8889, + X86_VPBLENDMQZrmbk = 8890, + X86_VPBLENDMQZrmbkz = 8891, + X86_VPBLENDMQZrmk = 8892, + X86_VPBLENDMQZrmkz = 8893, + X86_VPBLENDMQZrr = 8894, + X86_VPBLENDMQZrrk = 8895, + X86_VPBLENDMQZrrkz = 8896, + X86_VPBLENDMWZ128rm = 8897, + X86_VPBLENDMWZ128rmk = 8898, + X86_VPBLENDMWZ128rmkz = 8899, + X86_VPBLENDMWZ128rr = 8900, + X86_VPBLENDMWZ128rrk = 8901, + X86_VPBLENDMWZ128rrkz = 8902, + X86_VPBLENDMWZ256rm = 8903, + X86_VPBLENDMWZ256rmk = 8904, + X86_VPBLENDMWZ256rmkz = 8905, + X86_VPBLENDMWZ256rr = 8906, + X86_VPBLENDMWZ256rrk = 8907, + X86_VPBLENDMWZ256rrkz = 8908, + X86_VPBLENDMWZrm = 8909, + X86_VPBLENDMWZrmk = 8910, + X86_VPBLENDMWZrmkz = 8911, + X86_VPBLENDMWZrr = 8912, + X86_VPBLENDMWZrrk = 8913, + X86_VPBLENDMWZrrkz = 8914, + X86_VPBLENDVBYrm = 8915, + X86_VPBLENDVBYrr = 8916, + X86_VPBLENDVBrm = 8917, + X86_VPBLENDVBrr = 8918, + X86_VPBLENDWYrmi = 8919, + X86_VPBLENDWYrri = 8920, + X86_VPBLENDWrmi = 8921, + X86_VPBLENDWrri = 8922, + X86_VPBROADCASTBYrm = 8923, + X86_VPBROADCASTBYrr = 8924, + X86_VPBROADCASTBZ128m = 8925, + X86_VPBROADCASTBZ128mk = 8926, + X86_VPBROADCASTBZ128mkz = 8927, + X86_VPBROADCASTBZ128r = 8928, + X86_VPBROADCASTBZ128rk = 8929, + X86_VPBROADCASTBZ128rkz = 8930, + X86_VPBROADCASTBZ256m = 8931, + X86_VPBROADCASTBZ256mk = 8932, + X86_VPBROADCASTBZ256mkz = 8933, + X86_VPBROADCASTBZ256r = 8934, + X86_VPBROADCASTBZ256rk = 8935, + X86_VPBROADCASTBZ256rkz = 8936, + X86_VPBROADCASTBZm = 8937, + X86_VPBROADCASTBZmk = 8938, + X86_VPBROADCASTBZmkz = 8939, + X86_VPBROADCASTBZr = 8940, + X86_VPBROADCASTBZrk = 8941, + X86_VPBROADCASTBZrkz = 8942, + X86_VPBROADCASTBrZ128r = 8943, + X86_VPBROADCASTBrZ128rk = 8944, + X86_VPBROADCASTBrZ128rkz = 8945, + X86_VPBROADCASTBrZ256r = 8946, + X86_VPBROADCASTBrZ256rk = 8947, + X86_VPBROADCASTBrZ256rkz = 8948, + X86_VPBROADCASTBrZr = 8949, + X86_VPBROADCASTBrZrk = 8950, + X86_VPBROADCASTBrZrkz = 8951, + X86_VPBROADCASTBrm = 8952, + X86_VPBROADCASTBrr = 8953, + X86_VPBROADCASTDYrm = 8954, + X86_VPBROADCASTDYrr = 8955, + X86_VPBROADCASTDZ128m = 8956, + X86_VPBROADCASTDZ128mk = 8957, + X86_VPBROADCASTDZ128mkz = 8958, + X86_VPBROADCASTDZ128r = 8959, + X86_VPBROADCASTDZ128rk = 8960, + X86_VPBROADCASTDZ128rkz = 8961, + X86_VPBROADCASTDZ256m = 8962, + X86_VPBROADCASTDZ256mk = 8963, + X86_VPBROADCASTDZ256mkz = 8964, + X86_VPBROADCASTDZ256r = 8965, + X86_VPBROADCASTDZ256rk = 8966, + X86_VPBROADCASTDZ256rkz = 8967, + X86_VPBROADCASTDZm = 8968, + X86_VPBROADCASTDZmk = 8969, + X86_VPBROADCASTDZmkz = 8970, + X86_VPBROADCASTDZr = 8971, + X86_VPBROADCASTDZrk = 8972, + X86_VPBROADCASTDZrkz = 8973, + X86_VPBROADCASTDrZ128r = 8974, + X86_VPBROADCASTDrZ128rk = 8975, + X86_VPBROADCASTDrZ128rkz = 8976, + X86_VPBROADCASTDrZ256r = 8977, + X86_VPBROADCASTDrZ256rk = 8978, + X86_VPBROADCASTDrZ256rkz = 8979, + X86_VPBROADCASTDrZr = 8980, + X86_VPBROADCASTDrZrk = 8981, + X86_VPBROADCASTDrZrkz = 8982, + X86_VPBROADCASTDrm = 8983, + X86_VPBROADCASTDrr = 8984, + X86_VPBROADCASTMB2QZ128rr = 8985, + X86_VPBROADCASTMB2QZ256rr = 8986, + X86_VPBROADCASTMB2QZrr = 8987, + X86_VPBROADCASTMW2DZ128rr = 8988, + X86_VPBROADCASTMW2DZ256rr = 8989, + X86_VPBROADCASTMW2DZrr = 8990, + X86_VPBROADCASTQYrm = 8991, + X86_VPBROADCASTQYrr = 8992, + X86_VPBROADCASTQZ128m = 8993, + X86_VPBROADCASTQZ128mk = 8994, + X86_VPBROADCASTQZ128mkz = 8995, + X86_VPBROADCASTQZ128r = 8996, + X86_VPBROADCASTQZ128rk = 8997, + X86_VPBROADCASTQZ128rkz = 8998, + X86_VPBROADCASTQZ256m = 8999, + X86_VPBROADCASTQZ256mk = 9000, + X86_VPBROADCASTQZ256mkz = 9001, + X86_VPBROADCASTQZ256r = 9002, + X86_VPBROADCASTQZ256rk = 9003, + X86_VPBROADCASTQZ256rkz = 9004, + X86_VPBROADCASTQZm = 9005, + X86_VPBROADCASTQZmk = 9006, + X86_VPBROADCASTQZmkz = 9007, + X86_VPBROADCASTQZr = 9008, + X86_VPBROADCASTQZrk = 9009, + X86_VPBROADCASTQZrkz = 9010, + X86_VPBROADCASTQrZ128r = 9011, + X86_VPBROADCASTQrZ128rk = 9012, + X86_VPBROADCASTQrZ128rkz = 9013, + X86_VPBROADCASTQrZ256r = 9014, + X86_VPBROADCASTQrZ256rk = 9015, + X86_VPBROADCASTQrZ256rkz = 9016, + X86_VPBROADCASTQrZr = 9017, + X86_VPBROADCASTQrZrk = 9018, + X86_VPBROADCASTQrZrkz = 9019, + X86_VPBROADCASTQrm = 9020, + X86_VPBROADCASTQrr = 9021, + X86_VPBROADCASTWYrm = 9022, + X86_VPBROADCASTWYrr = 9023, + X86_VPBROADCASTWZ128m = 9024, + X86_VPBROADCASTWZ128mk = 9025, + X86_VPBROADCASTWZ128mkz = 9026, + X86_VPBROADCASTWZ128r = 9027, + X86_VPBROADCASTWZ128rk = 9028, + X86_VPBROADCASTWZ128rkz = 9029, + X86_VPBROADCASTWZ256m = 9030, + X86_VPBROADCASTWZ256mk = 9031, + X86_VPBROADCASTWZ256mkz = 9032, + X86_VPBROADCASTWZ256r = 9033, + X86_VPBROADCASTWZ256rk = 9034, + X86_VPBROADCASTWZ256rkz = 9035, + X86_VPBROADCASTWZm = 9036, + X86_VPBROADCASTWZmk = 9037, + X86_VPBROADCASTWZmkz = 9038, + X86_VPBROADCASTWZr = 9039, + X86_VPBROADCASTWZrk = 9040, + X86_VPBROADCASTWZrkz = 9041, + X86_VPBROADCASTWrZ128r = 9042, + X86_VPBROADCASTWrZ128rk = 9043, + X86_VPBROADCASTWrZ128rkz = 9044, + X86_VPBROADCASTWrZ256r = 9045, + X86_VPBROADCASTWrZ256rk = 9046, + X86_VPBROADCASTWrZ256rkz = 9047, + X86_VPBROADCASTWrZr = 9048, + X86_VPBROADCASTWrZrk = 9049, + X86_VPBROADCASTWrZrkz = 9050, + X86_VPBROADCASTWrm = 9051, + X86_VPBROADCASTWrr = 9052, + X86_VPCLMULQDQYrm = 9053, + X86_VPCLMULQDQYrr = 9054, + X86_VPCLMULQDQZ128rm = 9055, + X86_VPCLMULQDQZ128rr = 9056, + X86_VPCLMULQDQZ256rm = 9057, + X86_VPCLMULQDQZ256rr = 9058, + X86_VPCLMULQDQZrm = 9059, + X86_VPCLMULQDQZrr = 9060, + X86_VPCLMULQDQrm = 9061, + X86_VPCLMULQDQrr = 9062, + X86_VPCMOVYrmr = 9063, + X86_VPCMOVYrrm = 9064, + X86_VPCMOVYrrr = 9065, + X86_VPCMOVYrrr_REV = 9066, + X86_VPCMOVrmr = 9067, + X86_VPCMOVrrm = 9068, + X86_VPCMOVrrr = 9069, + X86_VPCMOVrrr_REV = 9070, + X86_VPCMPBZ128rmi = 9071, + X86_VPCMPBZ128rmi_alt = 9072, + X86_VPCMPBZ128rmik = 9073, + X86_VPCMPBZ128rmik_alt = 9074, + X86_VPCMPBZ128rri = 9075, + X86_VPCMPBZ128rri_alt = 9076, + X86_VPCMPBZ128rrik = 9077, + X86_VPCMPBZ128rrik_alt = 9078, + X86_VPCMPBZ256rmi = 9079, + X86_VPCMPBZ256rmi_alt = 9080, + X86_VPCMPBZ256rmik = 9081, + X86_VPCMPBZ256rmik_alt = 9082, + X86_VPCMPBZ256rri = 9083, + X86_VPCMPBZ256rri_alt = 9084, + X86_VPCMPBZ256rrik = 9085, + X86_VPCMPBZ256rrik_alt = 9086, + X86_VPCMPBZrmi = 9087, + X86_VPCMPBZrmi_alt = 9088, + X86_VPCMPBZrmik = 9089, + X86_VPCMPBZrmik_alt = 9090, + X86_VPCMPBZrri = 9091, + X86_VPCMPBZrri_alt = 9092, + X86_VPCMPBZrrik = 9093, + X86_VPCMPBZrrik_alt = 9094, + X86_VPCMPDZ128rmi = 9095, + X86_VPCMPDZ128rmi_alt = 9096, + X86_VPCMPDZ128rmib = 9097, + X86_VPCMPDZ128rmib_alt = 9098, + X86_VPCMPDZ128rmibk = 9099, + X86_VPCMPDZ128rmibk_alt = 9100, + X86_VPCMPDZ128rmik = 9101, + X86_VPCMPDZ128rmik_alt = 9102, + X86_VPCMPDZ128rri = 9103, + X86_VPCMPDZ128rri_alt = 9104, + X86_VPCMPDZ128rrik = 9105, + X86_VPCMPDZ128rrik_alt = 9106, + X86_VPCMPDZ256rmi = 9107, + X86_VPCMPDZ256rmi_alt = 9108, + X86_VPCMPDZ256rmib = 9109, + X86_VPCMPDZ256rmib_alt = 9110, + X86_VPCMPDZ256rmibk = 9111, + X86_VPCMPDZ256rmibk_alt = 9112, + X86_VPCMPDZ256rmik = 9113, + X86_VPCMPDZ256rmik_alt = 9114, + X86_VPCMPDZ256rri = 9115, + X86_VPCMPDZ256rri_alt = 9116, + X86_VPCMPDZ256rrik = 9117, + X86_VPCMPDZ256rrik_alt = 9118, + X86_VPCMPDZrmi = 9119, + X86_VPCMPDZrmi_alt = 9120, + X86_VPCMPDZrmib = 9121, + X86_VPCMPDZrmib_alt = 9122, + X86_VPCMPDZrmibk = 9123, + X86_VPCMPDZrmibk_alt = 9124, + X86_VPCMPDZrmik = 9125, + X86_VPCMPDZrmik_alt = 9126, + X86_VPCMPDZrri = 9127, + X86_VPCMPDZrri_alt = 9128, + X86_VPCMPDZrrik = 9129, + X86_VPCMPDZrrik_alt = 9130, + X86_VPCMPEQBYrm = 9131, + X86_VPCMPEQBYrr = 9132, + X86_VPCMPEQBZ128rm = 9133, + X86_VPCMPEQBZ128rmk = 9134, + X86_VPCMPEQBZ128rr = 9135, + X86_VPCMPEQBZ128rrk = 9136, + X86_VPCMPEQBZ256rm = 9137, + X86_VPCMPEQBZ256rmk = 9138, + X86_VPCMPEQBZ256rr = 9139, + X86_VPCMPEQBZ256rrk = 9140, + X86_VPCMPEQBZrm = 9141, + X86_VPCMPEQBZrmk = 9142, + X86_VPCMPEQBZrr = 9143, + X86_VPCMPEQBZrrk = 9144, + X86_VPCMPEQBrm = 9145, + X86_VPCMPEQBrr = 9146, + X86_VPCMPEQDYrm = 9147, + X86_VPCMPEQDYrr = 9148, + X86_VPCMPEQDZ128rm = 9149, + X86_VPCMPEQDZ128rmb = 9150, + X86_VPCMPEQDZ128rmbk = 9151, + X86_VPCMPEQDZ128rmk = 9152, + X86_VPCMPEQDZ128rr = 9153, + X86_VPCMPEQDZ128rrk = 9154, + X86_VPCMPEQDZ256rm = 9155, + X86_VPCMPEQDZ256rmb = 9156, + X86_VPCMPEQDZ256rmbk = 9157, + X86_VPCMPEQDZ256rmk = 9158, + X86_VPCMPEQDZ256rr = 9159, + X86_VPCMPEQDZ256rrk = 9160, + X86_VPCMPEQDZrm = 9161, + X86_VPCMPEQDZrmb = 9162, + X86_VPCMPEQDZrmbk = 9163, + X86_VPCMPEQDZrmk = 9164, + X86_VPCMPEQDZrr = 9165, + X86_VPCMPEQDZrrk = 9166, + X86_VPCMPEQDrm = 9167, + X86_VPCMPEQDrr = 9168, + X86_VPCMPEQQYrm = 9169, + X86_VPCMPEQQYrr = 9170, + X86_VPCMPEQQZ128rm = 9171, + X86_VPCMPEQQZ128rmb = 9172, + X86_VPCMPEQQZ128rmbk = 9173, + X86_VPCMPEQQZ128rmk = 9174, + X86_VPCMPEQQZ128rr = 9175, + X86_VPCMPEQQZ128rrk = 9176, + X86_VPCMPEQQZ256rm = 9177, + X86_VPCMPEQQZ256rmb = 9178, + X86_VPCMPEQQZ256rmbk = 9179, + X86_VPCMPEQQZ256rmk = 9180, + X86_VPCMPEQQZ256rr = 9181, + X86_VPCMPEQQZ256rrk = 9182, + X86_VPCMPEQQZrm = 9183, + X86_VPCMPEQQZrmb = 9184, + X86_VPCMPEQQZrmbk = 9185, + X86_VPCMPEQQZrmk = 9186, + X86_VPCMPEQQZrr = 9187, + X86_VPCMPEQQZrrk = 9188, + X86_VPCMPEQQrm = 9189, + X86_VPCMPEQQrr = 9190, + X86_VPCMPEQWYrm = 9191, + X86_VPCMPEQWYrr = 9192, + X86_VPCMPEQWZ128rm = 9193, + X86_VPCMPEQWZ128rmk = 9194, + X86_VPCMPEQWZ128rr = 9195, + X86_VPCMPEQWZ128rrk = 9196, + X86_VPCMPEQWZ256rm = 9197, + X86_VPCMPEQWZ256rmk = 9198, + X86_VPCMPEQWZ256rr = 9199, + X86_VPCMPEQWZ256rrk = 9200, + X86_VPCMPEQWZrm = 9201, + X86_VPCMPEQWZrmk = 9202, + X86_VPCMPEQWZrr = 9203, + X86_VPCMPEQWZrrk = 9204, + X86_VPCMPEQWrm = 9205, + X86_VPCMPEQWrr = 9206, + X86_VPCMPESTRIrm = 9207, + X86_VPCMPESTRIrr = 9208, + X86_VPCMPESTRMrm = 9209, + X86_VPCMPESTRMrr = 9210, + X86_VPCMPGTBYrm = 9211, + X86_VPCMPGTBYrr = 9212, + X86_VPCMPGTBZ128rm = 9213, + X86_VPCMPGTBZ128rmk = 9214, + X86_VPCMPGTBZ128rr = 9215, + X86_VPCMPGTBZ128rrk = 9216, + X86_VPCMPGTBZ256rm = 9217, + X86_VPCMPGTBZ256rmk = 9218, + X86_VPCMPGTBZ256rr = 9219, + X86_VPCMPGTBZ256rrk = 9220, + X86_VPCMPGTBZrm = 9221, + X86_VPCMPGTBZrmk = 9222, + X86_VPCMPGTBZrr = 9223, + X86_VPCMPGTBZrrk = 9224, + X86_VPCMPGTBrm = 9225, + X86_VPCMPGTBrr = 9226, + X86_VPCMPGTDYrm = 9227, + X86_VPCMPGTDYrr = 9228, + X86_VPCMPGTDZ128rm = 9229, + X86_VPCMPGTDZ128rmb = 9230, + X86_VPCMPGTDZ128rmbk = 9231, + X86_VPCMPGTDZ128rmk = 9232, + X86_VPCMPGTDZ128rr = 9233, + X86_VPCMPGTDZ128rrk = 9234, + X86_VPCMPGTDZ256rm = 9235, + X86_VPCMPGTDZ256rmb = 9236, + X86_VPCMPGTDZ256rmbk = 9237, + X86_VPCMPGTDZ256rmk = 9238, + X86_VPCMPGTDZ256rr = 9239, + X86_VPCMPGTDZ256rrk = 9240, + X86_VPCMPGTDZrm = 9241, + X86_VPCMPGTDZrmb = 9242, + X86_VPCMPGTDZrmbk = 9243, + X86_VPCMPGTDZrmk = 9244, + X86_VPCMPGTDZrr = 9245, + X86_VPCMPGTDZrrk = 9246, + X86_VPCMPGTDrm = 9247, + X86_VPCMPGTDrr = 9248, + X86_VPCMPGTQYrm = 9249, + X86_VPCMPGTQYrr = 9250, + X86_VPCMPGTQZ128rm = 9251, + X86_VPCMPGTQZ128rmb = 9252, + X86_VPCMPGTQZ128rmbk = 9253, + X86_VPCMPGTQZ128rmk = 9254, + X86_VPCMPGTQZ128rr = 9255, + X86_VPCMPGTQZ128rrk = 9256, + X86_VPCMPGTQZ256rm = 9257, + X86_VPCMPGTQZ256rmb = 9258, + X86_VPCMPGTQZ256rmbk = 9259, + X86_VPCMPGTQZ256rmk = 9260, + X86_VPCMPGTQZ256rr = 9261, + X86_VPCMPGTQZ256rrk = 9262, + X86_VPCMPGTQZrm = 9263, + X86_VPCMPGTQZrmb = 9264, + X86_VPCMPGTQZrmbk = 9265, + X86_VPCMPGTQZrmk = 9266, + X86_VPCMPGTQZrr = 9267, + X86_VPCMPGTQZrrk = 9268, + X86_VPCMPGTQrm = 9269, + X86_VPCMPGTQrr = 9270, + X86_VPCMPGTWYrm = 9271, + X86_VPCMPGTWYrr = 9272, + X86_VPCMPGTWZ128rm = 9273, + X86_VPCMPGTWZ128rmk = 9274, + X86_VPCMPGTWZ128rr = 9275, + X86_VPCMPGTWZ128rrk = 9276, + X86_VPCMPGTWZ256rm = 9277, + X86_VPCMPGTWZ256rmk = 9278, + X86_VPCMPGTWZ256rr = 9279, + X86_VPCMPGTWZ256rrk = 9280, + X86_VPCMPGTWZrm = 9281, + X86_VPCMPGTWZrmk = 9282, + X86_VPCMPGTWZrr = 9283, + X86_VPCMPGTWZrrk = 9284, + X86_VPCMPGTWrm = 9285, + X86_VPCMPGTWrr = 9286, + X86_VPCMPISTRIrm = 9287, + X86_VPCMPISTRIrr = 9288, + X86_VPCMPISTRMrm = 9289, + X86_VPCMPISTRMrr = 9290, + X86_VPCMPQZ128rmi = 9291, + X86_VPCMPQZ128rmi_alt = 9292, + X86_VPCMPQZ128rmib = 9293, + X86_VPCMPQZ128rmib_alt = 9294, + X86_VPCMPQZ128rmibk = 9295, + X86_VPCMPQZ128rmibk_alt = 9296, + X86_VPCMPQZ128rmik = 9297, + X86_VPCMPQZ128rmik_alt = 9298, + X86_VPCMPQZ128rri = 9299, + X86_VPCMPQZ128rri_alt = 9300, + X86_VPCMPQZ128rrik = 9301, + X86_VPCMPQZ128rrik_alt = 9302, + X86_VPCMPQZ256rmi = 9303, + X86_VPCMPQZ256rmi_alt = 9304, + X86_VPCMPQZ256rmib = 9305, + X86_VPCMPQZ256rmib_alt = 9306, + X86_VPCMPQZ256rmibk = 9307, + X86_VPCMPQZ256rmibk_alt = 9308, + X86_VPCMPQZ256rmik = 9309, + X86_VPCMPQZ256rmik_alt = 9310, + X86_VPCMPQZ256rri = 9311, + X86_VPCMPQZ256rri_alt = 9312, + X86_VPCMPQZ256rrik = 9313, + X86_VPCMPQZ256rrik_alt = 9314, + X86_VPCMPQZrmi = 9315, + X86_VPCMPQZrmi_alt = 9316, + X86_VPCMPQZrmib = 9317, + X86_VPCMPQZrmib_alt = 9318, + X86_VPCMPQZrmibk = 9319, + X86_VPCMPQZrmibk_alt = 9320, + X86_VPCMPQZrmik = 9321, + X86_VPCMPQZrmik_alt = 9322, + X86_VPCMPQZrri = 9323, + X86_VPCMPQZrri_alt = 9324, + X86_VPCMPQZrrik = 9325, + X86_VPCMPQZrrik_alt = 9326, + X86_VPCMPUBZ128rmi = 9327, + X86_VPCMPUBZ128rmi_alt = 9328, + X86_VPCMPUBZ128rmik = 9329, + X86_VPCMPUBZ128rmik_alt = 9330, + X86_VPCMPUBZ128rri = 9331, + X86_VPCMPUBZ128rri_alt = 9332, + X86_VPCMPUBZ128rrik = 9333, + X86_VPCMPUBZ128rrik_alt = 9334, + X86_VPCMPUBZ256rmi = 9335, + X86_VPCMPUBZ256rmi_alt = 9336, + X86_VPCMPUBZ256rmik = 9337, + X86_VPCMPUBZ256rmik_alt = 9338, + X86_VPCMPUBZ256rri = 9339, + X86_VPCMPUBZ256rri_alt = 9340, + X86_VPCMPUBZ256rrik = 9341, + X86_VPCMPUBZ256rrik_alt = 9342, + X86_VPCMPUBZrmi = 9343, + X86_VPCMPUBZrmi_alt = 9344, + X86_VPCMPUBZrmik = 9345, + X86_VPCMPUBZrmik_alt = 9346, + X86_VPCMPUBZrri = 9347, + X86_VPCMPUBZrri_alt = 9348, + X86_VPCMPUBZrrik = 9349, + X86_VPCMPUBZrrik_alt = 9350, + X86_VPCMPUDZ128rmi = 9351, + X86_VPCMPUDZ128rmi_alt = 9352, + X86_VPCMPUDZ128rmib = 9353, + X86_VPCMPUDZ128rmib_alt = 9354, + X86_VPCMPUDZ128rmibk = 9355, + X86_VPCMPUDZ128rmibk_alt = 9356, + X86_VPCMPUDZ128rmik = 9357, + X86_VPCMPUDZ128rmik_alt = 9358, + X86_VPCMPUDZ128rri = 9359, + X86_VPCMPUDZ128rri_alt = 9360, + X86_VPCMPUDZ128rrik = 9361, + X86_VPCMPUDZ128rrik_alt = 9362, + X86_VPCMPUDZ256rmi = 9363, + X86_VPCMPUDZ256rmi_alt = 9364, + X86_VPCMPUDZ256rmib = 9365, + X86_VPCMPUDZ256rmib_alt = 9366, + X86_VPCMPUDZ256rmibk = 9367, + X86_VPCMPUDZ256rmibk_alt = 9368, + X86_VPCMPUDZ256rmik = 9369, + X86_VPCMPUDZ256rmik_alt = 9370, + X86_VPCMPUDZ256rri = 9371, + X86_VPCMPUDZ256rri_alt = 9372, + X86_VPCMPUDZ256rrik = 9373, + X86_VPCMPUDZ256rrik_alt = 9374, + X86_VPCMPUDZrmi = 9375, + X86_VPCMPUDZrmi_alt = 9376, + X86_VPCMPUDZrmib = 9377, + X86_VPCMPUDZrmib_alt = 9378, + X86_VPCMPUDZrmibk = 9379, + X86_VPCMPUDZrmibk_alt = 9380, + X86_VPCMPUDZrmik = 9381, + X86_VPCMPUDZrmik_alt = 9382, + X86_VPCMPUDZrri = 9383, + X86_VPCMPUDZrri_alt = 9384, + X86_VPCMPUDZrrik = 9385, + X86_VPCMPUDZrrik_alt = 9386, + X86_VPCMPUQZ128rmi = 9387, + X86_VPCMPUQZ128rmi_alt = 9388, + X86_VPCMPUQZ128rmib = 9389, + X86_VPCMPUQZ128rmib_alt = 9390, + X86_VPCMPUQZ128rmibk = 9391, + X86_VPCMPUQZ128rmibk_alt = 9392, + X86_VPCMPUQZ128rmik = 9393, + X86_VPCMPUQZ128rmik_alt = 9394, + X86_VPCMPUQZ128rri = 9395, + X86_VPCMPUQZ128rri_alt = 9396, + X86_VPCMPUQZ128rrik = 9397, + X86_VPCMPUQZ128rrik_alt = 9398, + X86_VPCMPUQZ256rmi = 9399, + X86_VPCMPUQZ256rmi_alt = 9400, + X86_VPCMPUQZ256rmib = 9401, + X86_VPCMPUQZ256rmib_alt = 9402, + X86_VPCMPUQZ256rmibk = 9403, + X86_VPCMPUQZ256rmibk_alt = 9404, + X86_VPCMPUQZ256rmik = 9405, + X86_VPCMPUQZ256rmik_alt = 9406, + X86_VPCMPUQZ256rri = 9407, + X86_VPCMPUQZ256rri_alt = 9408, + X86_VPCMPUQZ256rrik = 9409, + X86_VPCMPUQZ256rrik_alt = 9410, + X86_VPCMPUQZrmi = 9411, + X86_VPCMPUQZrmi_alt = 9412, + X86_VPCMPUQZrmib = 9413, + X86_VPCMPUQZrmib_alt = 9414, + X86_VPCMPUQZrmibk = 9415, + X86_VPCMPUQZrmibk_alt = 9416, + X86_VPCMPUQZrmik = 9417, + X86_VPCMPUQZrmik_alt = 9418, + X86_VPCMPUQZrri = 9419, + X86_VPCMPUQZrri_alt = 9420, + X86_VPCMPUQZrrik = 9421, + X86_VPCMPUQZrrik_alt = 9422, + X86_VPCMPUWZ128rmi = 9423, + X86_VPCMPUWZ128rmi_alt = 9424, + X86_VPCMPUWZ128rmik = 9425, + X86_VPCMPUWZ128rmik_alt = 9426, + X86_VPCMPUWZ128rri = 9427, + X86_VPCMPUWZ128rri_alt = 9428, + X86_VPCMPUWZ128rrik = 9429, + X86_VPCMPUWZ128rrik_alt = 9430, + X86_VPCMPUWZ256rmi = 9431, + X86_VPCMPUWZ256rmi_alt = 9432, + X86_VPCMPUWZ256rmik = 9433, + X86_VPCMPUWZ256rmik_alt = 9434, + X86_VPCMPUWZ256rri = 9435, + X86_VPCMPUWZ256rri_alt = 9436, + X86_VPCMPUWZ256rrik = 9437, + X86_VPCMPUWZ256rrik_alt = 9438, + X86_VPCMPUWZrmi = 9439, + X86_VPCMPUWZrmi_alt = 9440, + X86_VPCMPUWZrmik = 9441, + X86_VPCMPUWZrmik_alt = 9442, + X86_VPCMPUWZrri = 9443, + X86_VPCMPUWZrri_alt = 9444, + X86_VPCMPUWZrrik = 9445, + X86_VPCMPUWZrrik_alt = 9446, + X86_VPCMPWZ128rmi = 9447, + X86_VPCMPWZ128rmi_alt = 9448, + X86_VPCMPWZ128rmik = 9449, + X86_VPCMPWZ128rmik_alt = 9450, + X86_VPCMPWZ128rri = 9451, + X86_VPCMPWZ128rri_alt = 9452, + X86_VPCMPWZ128rrik = 9453, + X86_VPCMPWZ128rrik_alt = 9454, + X86_VPCMPWZ256rmi = 9455, + X86_VPCMPWZ256rmi_alt = 9456, + X86_VPCMPWZ256rmik = 9457, + X86_VPCMPWZ256rmik_alt = 9458, + X86_VPCMPWZ256rri = 9459, + X86_VPCMPWZ256rri_alt = 9460, + X86_VPCMPWZ256rrik = 9461, + X86_VPCMPWZ256rrik_alt = 9462, + X86_VPCMPWZrmi = 9463, + X86_VPCMPWZrmi_alt = 9464, + X86_VPCMPWZrmik = 9465, + X86_VPCMPWZrmik_alt = 9466, + X86_VPCMPWZrri = 9467, + X86_VPCMPWZrri_alt = 9468, + X86_VPCMPWZrrik = 9469, + X86_VPCMPWZrrik_alt = 9470, + X86_VPCOMBmi = 9471, + X86_VPCOMBmi_alt = 9472, + X86_VPCOMBri = 9473, + X86_VPCOMBri_alt = 9474, + X86_VPCOMDmi = 9475, + X86_VPCOMDmi_alt = 9476, + X86_VPCOMDri = 9477, + X86_VPCOMDri_alt = 9478, + X86_VPCOMPRESSBZ128mr = 9479, + X86_VPCOMPRESSBZ128mrk = 9480, + X86_VPCOMPRESSBZ128rr = 9481, + X86_VPCOMPRESSBZ128rrk = 9482, + X86_VPCOMPRESSBZ128rrkz = 9483, + X86_VPCOMPRESSBZ256mr = 9484, + X86_VPCOMPRESSBZ256mrk = 9485, + X86_VPCOMPRESSBZ256rr = 9486, + X86_VPCOMPRESSBZ256rrk = 9487, + X86_VPCOMPRESSBZ256rrkz = 9488, + X86_VPCOMPRESSBZmr = 9489, + X86_VPCOMPRESSBZmrk = 9490, + X86_VPCOMPRESSBZrr = 9491, + X86_VPCOMPRESSBZrrk = 9492, + X86_VPCOMPRESSBZrrkz = 9493, + X86_VPCOMPRESSDZ128mr = 9494, + X86_VPCOMPRESSDZ128mrk = 9495, + X86_VPCOMPRESSDZ128rr = 9496, + X86_VPCOMPRESSDZ128rrk = 9497, + X86_VPCOMPRESSDZ128rrkz = 9498, + X86_VPCOMPRESSDZ256mr = 9499, + X86_VPCOMPRESSDZ256mrk = 9500, + X86_VPCOMPRESSDZ256rr = 9501, + X86_VPCOMPRESSDZ256rrk = 9502, + X86_VPCOMPRESSDZ256rrkz = 9503, + X86_VPCOMPRESSDZmr = 9504, + X86_VPCOMPRESSDZmrk = 9505, + X86_VPCOMPRESSDZrr = 9506, + X86_VPCOMPRESSDZrrk = 9507, + X86_VPCOMPRESSDZrrkz = 9508, + X86_VPCOMPRESSQZ128mr = 9509, + X86_VPCOMPRESSQZ128mrk = 9510, + X86_VPCOMPRESSQZ128rr = 9511, + X86_VPCOMPRESSQZ128rrk = 9512, + X86_VPCOMPRESSQZ128rrkz = 9513, + X86_VPCOMPRESSQZ256mr = 9514, + X86_VPCOMPRESSQZ256mrk = 9515, + X86_VPCOMPRESSQZ256rr = 9516, + X86_VPCOMPRESSQZ256rrk = 9517, + X86_VPCOMPRESSQZ256rrkz = 9518, + X86_VPCOMPRESSQZmr = 9519, + X86_VPCOMPRESSQZmrk = 9520, + X86_VPCOMPRESSQZrr = 9521, + X86_VPCOMPRESSQZrrk = 9522, + X86_VPCOMPRESSQZrrkz = 9523, + X86_VPCOMPRESSWZ128mr = 9524, + X86_VPCOMPRESSWZ128mrk = 9525, + X86_VPCOMPRESSWZ128rr = 9526, + X86_VPCOMPRESSWZ128rrk = 9527, + X86_VPCOMPRESSWZ128rrkz = 9528, + X86_VPCOMPRESSWZ256mr = 9529, + X86_VPCOMPRESSWZ256mrk = 9530, + X86_VPCOMPRESSWZ256rr = 9531, + X86_VPCOMPRESSWZ256rrk = 9532, + X86_VPCOMPRESSWZ256rrkz = 9533, + X86_VPCOMPRESSWZmr = 9534, + X86_VPCOMPRESSWZmrk = 9535, + X86_VPCOMPRESSWZrr = 9536, + X86_VPCOMPRESSWZrrk = 9537, + X86_VPCOMPRESSWZrrkz = 9538, + X86_VPCOMQmi = 9539, + X86_VPCOMQmi_alt = 9540, + X86_VPCOMQri = 9541, + X86_VPCOMQri_alt = 9542, + X86_VPCOMUBmi = 9543, + X86_VPCOMUBmi_alt = 9544, + X86_VPCOMUBri = 9545, + X86_VPCOMUBri_alt = 9546, + X86_VPCOMUDmi = 9547, + X86_VPCOMUDmi_alt = 9548, + X86_VPCOMUDri = 9549, + X86_VPCOMUDri_alt = 9550, + X86_VPCOMUQmi = 9551, + X86_VPCOMUQmi_alt = 9552, + X86_VPCOMUQri = 9553, + X86_VPCOMUQri_alt = 9554, + X86_VPCOMUWmi = 9555, + X86_VPCOMUWmi_alt = 9556, + X86_VPCOMUWri = 9557, + X86_VPCOMUWri_alt = 9558, + X86_VPCOMWmi = 9559, + X86_VPCOMWmi_alt = 9560, + X86_VPCOMWri = 9561, + X86_VPCOMWri_alt = 9562, + X86_VPCONFLICTDZ128rm = 9563, + X86_VPCONFLICTDZ128rmb = 9564, + X86_VPCONFLICTDZ128rmbk = 9565, + X86_VPCONFLICTDZ128rmbkz = 9566, + X86_VPCONFLICTDZ128rmk = 9567, + X86_VPCONFLICTDZ128rmkz = 9568, + X86_VPCONFLICTDZ128rr = 9569, + X86_VPCONFLICTDZ128rrk = 9570, + X86_VPCONFLICTDZ128rrkz = 9571, + X86_VPCONFLICTDZ256rm = 9572, + X86_VPCONFLICTDZ256rmb = 9573, + X86_VPCONFLICTDZ256rmbk = 9574, + X86_VPCONFLICTDZ256rmbkz = 9575, + X86_VPCONFLICTDZ256rmk = 9576, + X86_VPCONFLICTDZ256rmkz = 9577, + X86_VPCONFLICTDZ256rr = 9578, + X86_VPCONFLICTDZ256rrk = 9579, + X86_VPCONFLICTDZ256rrkz = 9580, + X86_VPCONFLICTDZrm = 9581, + X86_VPCONFLICTDZrmb = 9582, + X86_VPCONFLICTDZrmbk = 9583, + X86_VPCONFLICTDZrmbkz = 9584, + X86_VPCONFLICTDZrmk = 9585, + X86_VPCONFLICTDZrmkz = 9586, + X86_VPCONFLICTDZrr = 9587, + X86_VPCONFLICTDZrrk = 9588, + X86_VPCONFLICTDZrrkz = 9589, + X86_VPCONFLICTQZ128rm = 9590, + X86_VPCONFLICTQZ128rmb = 9591, + X86_VPCONFLICTQZ128rmbk = 9592, + X86_VPCONFLICTQZ128rmbkz = 9593, + X86_VPCONFLICTQZ128rmk = 9594, + X86_VPCONFLICTQZ128rmkz = 9595, + X86_VPCONFLICTQZ128rr = 9596, + X86_VPCONFLICTQZ128rrk = 9597, + X86_VPCONFLICTQZ128rrkz = 9598, + X86_VPCONFLICTQZ256rm = 9599, + X86_VPCONFLICTQZ256rmb = 9600, + X86_VPCONFLICTQZ256rmbk = 9601, + X86_VPCONFLICTQZ256rmbkz = 9602, + X86_VPCONFLICTQZ256rmk = 9603, + X86_VPCONFLICTQZ256rmkz = 9604, + X86_VPCONFLICTQZ256rr = 9605, + X86_VPCONFLICTQZ256rrk = 9606, + X86_VPCONFLICTQZ256rrkz = 9607, + X86_VPCONFLICTQZrm = 9608, + X86_VPCONFLICTQZrmb = 9609, + X86_VPCONFLICTQZrmbk = 9610, + X86_VPCONFLICTQZrmbkz = 9611, + X86_VPCONFLICTQZrmk = 9612, + X86_VPCONFLICTQZrmkz = 9613, + X86_VPCONFLICTQZrr = 9614, + X86_VPCONFLICTQZrrk = 9615, + X86_VPCONFLICTQZrrkz = 9616, + X86_VPDPBUSDSZ128m = 9617, + X86_VPDPBUSDSZ128mb = 9618, + X86_VPDPBUSDSZ128mbk = 9619, + X86_VPDPBUSDSZ128mbkz = 9620, + X86_VPDPBUSDSZ128mk = 9621, + X86_VPDPBUSDSZ128mkz = 9622, + X86_VPDPBUSDSZ128r = 9623, + X86_VPDPBUSDSZ128rk = 9624, + X86_VPDPBUSDSZ128rkz = 9625, + X86_VPDPBUSDSZ256m = 9626, + X86_VPDPBUSDSZ256mb = 9627, + X86_VPDPBUSDSZ256mbk = 9628, + X86_VPDPBUSDSZ256mbkz = 9629, + X86_VPDPBUSDSZ256mk = 9630, + X86_VPDPBUSDSZ256mkz = 9631, + X86_VPDPBUSDSZ256r = 9632, + X86_VPDPBUSDSZ256rk = 9633, + X86_VPDPBUSDSZ256rkz = 9634, + X86_VPDPBUSDSZm = 9635, + X86_VPDPBUSDSZmb = 9636, + X86_VPDPBUSDSZmbk = 9637, + X86_VPDPBUSDSZmbkz = 9638, + X86_VPDPBUSDSZmk = 9639, + X86_VPDPBUSDSZmkz = 9640, + X86_VPDPBUSDSZr = 9641, + X86_VPDPBUSDSZrk = 9642, + X86_VPDPBUSDSZrkz = 9643, + X86_VPDPBUSDZ128m = 9644, + X86_VPDPBUSDZ128mb = 9645, + X86_VPDPBUSDZ128mbk = 9646, + X86_VPDPBUSDZ128mbkz = 9647, + X86_VPDPBUSDZ128mk = 9648, + X86_VPDPBUSDZ128mkz = 9649, + X86_VPDPBUSDZ128r = 9650, + X86_VPDPBUSDZ128rk = 9651, + X86_VPDPBUSDZ128rkz = 9652, + X86_VPDPBUSDZ256m = 9653, + X86_VPDPBUSDZ256mb = 9654, + X86_VPDPBUSDZ256mbk = 9655, + X86_VPDPBUSDZ256mbkz = 9656, + X86_VPDPBUSDZ256mk = 9657, + X86_VPDPBUSDZ256mkz = 9658, + X86_VPDPBUSDZ256r = 9659, + X86_VPDPBUSDZ256rk = 9660, + X86_VPDPBUSDZ256rkz = 9661, + X86_VPDPBUSDZm = 9662, + X86_VPDPBUSDZmb = 9663, + X86_VPDPBUSDZmbk = 9664, + X86_VPDPBUSDZmbkz = 9665, + X86_VPDPBUSDZmk = 9666, + X86_VPDPBUSDZmkz = 9667, + X86_VPDPBUSDZr = 9668, + X86_VPDPBUSDZrk = 9669, + X86_VPDPBUSDZrkz = 9670, + X86_VPDPWSSDSZ128m = 9671, + X86_VPDPWSSDSZ128mb = 9672, + X86_VPDPWSSDSZ128mbk = 9673, + X86_VPDPWSSDSZ128mbkz = 9674, + X86_VPDPWSSDSZ128mk = 9675, + X86_VPDPWSSDSZ128mkz = 9676, + X86_VPDPWSSDSZ128r = 9677, + X86_VPDPWSSDSZ128rk = 9678, + X86_VPDPWSSDSZ128rkz = 9679, + X86_VPDPWSSDSZ256m = 9680, + X86_VPDPWSSDSZ256mb = 9681, + X86_VPDPWSSDSZ256mbk = 9682, + X86_VPDPWSSDSZ256mbkz = 9683, + X86_VPDPWSSDSZ256mk = 9684, + X86_VPDPWSSDSZ256mkz = 9685, + X86_VPDPWSSDSZ256r = 9686, + X86_VPDPWSSDSZ256rk = 9687, + X86_VPDPWSSDSZ256rkz = 9688, + X86_VPDPWSSDSZm = 9689, + X86_VPDPWSSDSZmb = 9690, + X86_VPDPWSSDSZmbk = 9691, + X86_VPDPWSSDSZmbkz = 9692, + X86_VPDPWSSDSZmk = 9693, + X86_VPDPWSSDSZmkz = 9694, + X86_VPDPWSSDSZr = 9695, + X86_VPDPWSSDSZrk = 9696, + X86_VPDPWSSDSZrkz = 9697, + X86_VPDPWSSDZ128m = 9698, + X86_VPDPWSSDZ128mb = 9699, + X86_VPDPWSSDZ128mbk = 9700, + X86_VPDPWSSDZ128mbkz = 9701, + X86_VPDPWSSDZ128mk = 9702, + X86_VPDPWSSDZ128mkz = 9703, + X86_VPDPWSSDZ128r = 9704, + X86_VPDPWSSDZ128rk = 9705, + X86_VPDPWSSDZ128rkz = 9706, + X86_VPDPWSSDZ256m = 9707, + X86_VPDPWSSDZ256mb = 9708, + X86_VPDPWSSDZ256mbk = 9709, + X86_VPDPWSSDZ256mbkz = 9710, + X86_VPDPWSSDZ256mk = 9711, + X86_VPDPWSSDZ256mkz = 9712, + X86_VPDPWSSDZ256r = 9713, + X86_VPDPWSSDZ256rk = 9714, + X86_VPDPWSSDZ256rkz = 9715, + X86_VPDPWSSDZm = 9716, + X86_VPDPWSSDZmb = 9717, + X86_VPDPWSSDZmbk = 9718, + X86_VPDPWSSDZmbkz = 9719, + X86_VPDPWSSDZmk = 9720, + X86_VPDPWSSDZmkz = 9721, + X86_VPDPWSSDZr = 9722, + X86_VPDPWSSDZrk = 9723, + X86_VPDPWSSDZrkz = 9724, + X86_VPERM2F128rm = 9725, + X86_VPERM2F128rr = 9726, + X86_VPERM2I128rm = 9727, + X86_VPERM2I128rr = 9728, + X86_VPERMBZ128rm = 9729, + X86_VPERMBZ128rmk = 9730, + X86_VPERMBZ128rmkz = 9731, + X86_VPERMBZ128rr = 9732, + X86_VPERMBZ128rrk = 9733, + X86_VPERMBZ128rrkz = 9734, + X86_VPERMBZ256rm = 9735, + X86_VPERMBZ256rmk = 9736, + X86_VPERMBZ256rmkz = 9737, + X86_VPERMBZ256rr = 9738, + X86_VPERMBZ256rrk = 9739, + X86_VPERMBZ256rrkz = 9740, + X86_VPERMBZrm = 9741, + X86_VPERMBZrmk = 9742, + X86_VPERMBZrmkz = 9743, + X86_VPERMBZrr = 9744, + X86_VPERMBZrrk = 9745, + X86_VPERMBZrrkz = 9746, + X86_VPERMDYrm = 9747, + X86_VPERMDYrr = 9748, + X86_VPERMDZ256rm = 9749, + X86_VPERMDZ256rmb = 9750, + X86_VPERMDZ256rmbk = 9751, + X86_VPERMDZ256rmbkz = 9752, + X86_VPERMDZ256rmk = 9753, + X86_VPERMDZ256rmkz = 9754, + X86_VPERMDZ256rr = 9755, + X86_VPERMDZ256rrk = 9756, + X86_VPERMDZ256rrkz = 9757, + X86_VPERMDZrm = 9758, + X86_VPERMDZrmb = 9759, + X86_VPERMDZrmbk = 9760, + X86_VPERMDZrmbkz = 9761, + X86_VPERMDZrmk = 9762, + X86_VPERMDZrmkz = 9763, + X86_VPERMDZrr = 9764, + X86_VPERMDZrrk = 9765, + X86_VPERMDZrrkz = 9766, + X86_VPERMI2B128rm = 9767, + X86_VPERMI2B128rmk = 9768, + X86_VPERMI2B128rmkz = 9769, + X86_VPERMI2B128rr = 9770, + X86_VPERMI2B128rrk = 9771, + X86_VPERMI2B128rrkz = 9772, + X86_VPERMI2B256rm = 9773, + X86_VPERMI2B256rmk = 9774, + X86_VPERMI2B256rmkz = 9775, + X86_VPERMI2B256rr = 9776, + X86_VPERMI2B256rrk = 9777, + X86_VPERMI2B256rrkz = 9778, + X86_VPERMI2Brm = 9779, + X86_VPERMI2Brmk = 9780, + X86_VPERMI2Brmkz = 9781, + X86_VPERMI2Brr = 9782, + X86_VPERMI2Brrk = 9783, + X86_VPERMI2Brrkz = 9784, + X86_VPERMI2D128rm = 9785, + X86_VPERMI2D128rmb = 9786, + X86_VPERMI2D128rmbk = 9787, + X86_VPERMI2D128rmbkz = 9788, + X86_VPERMI2D128rmk = 9789, + X86_VPERMI2D128rmkz = 9790, + X86_VPERMI2D128rr = 9791, + X86_VPERMI2D128rrk = 9792, + X86_VPERMI2D128rrkz = 9793, + X86_VPERMI2D256rm = 9794, + X86_VPERMI2D256rmb = 9795, + X86_VPERMI2D256rmbk = 9796, + X86_VPERMI2D256rmbkz = 9797, + X86_VPERMI2D256rmk = 9798, + X86_VPERMI2D256rmkz = 9799, + X86_VPERMI2D256rr = 9800, + X86_VPERMI2D256rrk = 9801, + X86_VPERMI2D256rrkz = 9802, + X86_VPERMI2Drm = 9803, + X86_VPERMI2Drmb = 9804, + X86_VPERMI2Drmbk = 9805, + X86_VPERMI2Drmbkz = 9806, + X86_VPERMI2Drmk = 9807, + X86_VPERMI2Drmkz = 9808, + X86_VPERMI2Drr = 9809, + X86_VPERMI2Drrk = 9810, + X86_VPERMI2Drrkz = 9811, + X86_VPERMI2PD128rm = 9812, + X86_VPERMI2PD128rmb = 9813, + X86_VPERMI2PD128rmbk = 9814, + X86_VPERMI2PD128rmbkz = 9815, + X86_VPERMI2PD128rmk = 9816, + X86_VPERMI2PD128rmkz = 9817, + X86_VPERMI2PD128rr = 9818, + X86_VPERMI2PD128rrk = 9819, + X86_VPERMI2PD128rrkz = 9820, + X86_VPERMI2PD256rm = 9821, + X86_VPERMI2PD256rmb = 9822, + X86_VPERMI2PD256rmbk = 9823, + X86_VPERMI2PD256rmbkz = 9824, + X86_VPERMI2PD256rmk = 9825, + X86_VPERMI2PD256rmkz = 9826, + X86_VPERMI2PD256rr = 9827, + X86_VPERMI2PD256rrk = 9828, + X86_VPERMI2PD256rrkz = 9829, + X86_VPERMI2PDrm = 9830, + X86_VPERMI2PDrmb = 9831, + X86_VPERMI2PDrmbk = 9832, + X86_VPERMI2PDrmbkz = 9833, + X86_VPERMI2PDrmk = 9834, + X86_VPERMI2PDrmkz = 9835, + X86_VPERMI2PDrr = 9836, + X86_VPERMI2PDrrk = 9837, + X86_VPERMI2PDrrkz = 9838, + X86_VPERMI2PS128rm = 9839, + X86_VPERMI2PS128rmb = 9840, + X86_VPERMI2PS128rmbk = 9841, + X86_VPERMI2PS128rmbkz = 9842, + X86_VPERMI2PS128rmk = 9843, + X86_VPERMI2PS128rmkz = 9844, + X86_VPERMI2PS128rr = 9845, + X86_VPERMI2PS128rrk = 9846, + X86_VPERMI2PS128rrkz = 9847, + X86_VPERMI2PS256rm = 9848, + X86_VPERMI2PS256rmb = 9849, + X86_VPERMI2PS256rmbk = 9850, + X86_VPERMI2PS256rmbkz = 9851, + X86_VPERMI2PS256rmk = 9852, + X86_VPERMI2PS256rmkz = 9853, + X86_VPERMI2PS256rr = 9854, + X86_VPERMI2PS256rrk = 9855, + X86_VPERMI2PS256rrkz = 9856, + X86_VPERMI2PSrm = 9857, + X86_VPERMI2PSrmb = 9858, + X86_VPERMI2PSrmbk = 9859, + X86_VPERMI2PSrmbkz = 9860, + X86_VPERMI2PSrmk = 9861, + X86_VPERMI2PSrmkz = 9862, + X86_VPERMI2PSrr = 9863, + X86_VPERMI2PSrrk = 9864, + X86_VPERMI2PSrrkz = 9865, + X86_VPERMI2Q128rm = 9866, + X86_VPERMI2Q128rmb = 9867, + X86_VPERMI2Q128rmbk = 9868, + X86_VPERMI2Q128rmbkz = 9869, + X86_VPERMI2Q128rmk = 9870, + X86_VPERMI2Q128rmkz = 9871, + X86_VPERMI2Q128rr = 9872, + X86_VPERMI2Q128rrk = 9873, + X86_VPERMI2Q128rrkz = 9874, + X86_VPERMI2Q256rm = 9875, + X86_VPERMI2Q256rmb = 9876, + X86_VPERMI2Q256rmbk = 9877, + X86_VPERMI2Q256rmbkz = 9878, + X86_VPERMI2Q256rmk = 9879, + X86_VPERMI2Q256rmkz = 9880, + X86_VPERMI2Q256rr = 9881, + X86_VPERMI2Q256rrk = 9882, + X86_VPERMI2Q256rrkz = 9883, + X86_VPERMI2Qrm = 9884, + X86_VPERMI2Qrmb = 9885, + X86_VPERMI2Qrmbk = 9886, + X86_VPERMI2Qrmbkz = 9887, + X86_VPERMI2Qrmk = 9888, + X86_VPERMI2Qrmkz = 9889, + X86_VPERMI2Qrr = 9890, + X86_VPERMI2Qrrk = 9891, + X86_VPERMI2Qrrkz = 9892, + X86_VPERMI2W128rm = 9893, + X86_VPERMI2W128rmk = 9894, + X86_VPERMI2W128rmkz = 9895, + X86_VPERMI2W128rr = 9896, + X86_VPERMI2W128rrk = 9897, + X86_VPERMI2W128rrkz = 9898, + X86_VPERMI2W256rm = 9899, + X86_VPERMI2W256rmk = 9900, + X86_VPERMI2W256rmkz = 9901, + X86_VPERMI2W256rr = 9902, + X86_VPERMI2W256rrk = 9903, + X86_VPERMI2W256rrkz = 9904, + X86_VPERMI2Wrm = 9905, + X86_VPERMI2Wrmk = 9906, + X86_VPERMI2Wrmkz = 9907, + X86_VPERMI2Wrr = 9908, + X86_VPERMI2Wrrk = 9909, + X86_VPERMI2Wrrkz = 9910, + X86_VPERMIL2PDYmr = 9911, + X86_VPERMIL2PDYrm = 9912, + X86_VPERMIL2PDYrr = 9913, + X86_VPERMIL2PDYrr_REV = 9914, + X86_VPERMIL2PDmr = 9915, + X86_VPERMIL2PDrm = 9916, + X86_VPERMIL2PDrr = 9917, + X86_VPERMIL2PDrr_REV = 9918, + X86_VPERMIL2PSYmr = 9919, + X86_VPERMIL2PSYrm = 9920, + X86_VPERMIL2PSYrr = 9921, + X86_VPERMIL2PSYrr_REV = 9922, + X86_VPERMIL2PSmr = 9923, + X86_VPERMIL2PSrm = 9924, + X86_VPERMIL2PSrr = 9925, + X86_VPERMIL2PSrr_REV = 9926, + X86_VPERMILPDYmi = 9927, + X86_VPERMILPDYri = 9928, + X86_VPERMILPDYrm = 9929, + X86_VPERMILPDYrr = 9930, + X86_VPERMILPDZ128mbi = 9931, + X86_VPERMILPDZ128mbik = 9932, + X86_VPERMILPDZ128mbikz = 9933, + X86_VPERMILPDZ128mi = 9934, + X86_VPERMILPDZ128mik = 9935, + X86_VPERMILPDZ128mikz = 9936, + X86_VPERMILPDZ128ri = 9937, + X86_VPERMILPDZ128rik = 9938, + X86_VPERMILPDZ128rikz = 9939, + X86_VPERMILPDZ128rm = 9940, + X86_VPERMILPDZ128rmb = 9941, + X86_VPERMILPDZ128rmbk = 9942, + X86_VPERMILPDZ128rmbkz = 9943, + X86_VPERMILPDZ128rmk = 9944, + X86_VPERMILPDZ128rmkz = 9945, + X86_VPERMILPDZ128rr = 9946, + X86_VPERMILPDZ128rrk = 9947, + X86_VPERMILPDZ128rrkz = 9948, + X86_VPERMILPDZ256mbi = 9949, + X86_VPERMILPDZ256mbik = 9950, + X86_VPERMILPDZ256mbikz = 9951, + X86_VPERMILPDZ256mi = 9952, + X86_VPERMILPDZ256mik = 9953, + X86_VPERMILPDZ256mikz = 9954, + X86_VPERMILPDZ256ri = 9955, + X86_VPERMILPDZ256rik = 9956, + X86_VPERMILPDZ256rikz = 9957, + X86_VPERMILPDZ256rm = 9958, + X86_VPERMILPDZ256rmb = 9959, + X86_VPERMILPDZ256rmbk = 9960, + X86_VPERMILPDZ256rmbkz = 9961, + X86_VPERMILPDZ256rmk = 9962, + X86_VPERMILPDZ256rmkz = 9963, + X86_VPERMILPDZ256rr = 9964, + X86_VPERMILPDZ256rrk = 9965, + X86_VPERMILPDZ256rrkz = 9966, + X86_VPERMILPDZmbi = 9967, + X86_VPERMILPDZmbik = 9968, + X86_VPERMILPDZmbikz = 9969, + X86_VPERMILPDZmi = 9970, + X86_VPERMILPDZmik = 9971, + X86_VPERMILPDZmikz = 9972, + X86_VPERMILPDZri = 9973, + X86_VPERMILPDZrik = 9974, + X86_VPERMILPDZrikz = 9975, + X86_VPERMILPDZrm = 9976, + X86_VPERMILPDZrmb = 9977, + X86_VPERMILPDZrmbk = 9978, + X86_VPERMILPDZrmbkz = 9979, + X86_VPERMILPDZrmk = 9980, + X86_VPERMILPDZrmkz = 9981, + X86_VPERMILPDZrr = 9982, + X86_VPERMILPDZrrk = 9983, + X86_VPERMILPDZrrkz = 9984, + X86_VPERMILPDmi = 9985, + X86_VPERMILPDri = 9986, + X86_VPERMILPDrm = 9987, + X86_VPERMILPDrr = 9988, + X86_VPERMILPSYmi = 9989, + X86_VPERMILPSYri = 9990, + X86_VPERMILPSYrm = 9991, + X86_VPERMILPSYrr = 9992, + X86_VPERMILPSZ128mbi = 9993, + X86_VPERMILPSZ128mbik = 9994, + X86_VPERMILPSZ128mbikz = 9995, + X86_VPERMILPSZ128mi = 9996, + X86_VPERMILPSZ128mik = 9997, + X86_VPERMILPSZ128mikz = 9998, + X86_VPERMILPSZ128ri = 9999, + X86_VPERMILPSZ128rik = 10000, + X86_VPERMILPSZ128rikz = 10001, + X86_VPERMILPSZ128rm = 10002, + X86_VPERMILPSZ128rmb = 10003, + X86_VPERMILPSZ128rmbk = 10004, + X86_VPERMILPSZ128rmbkz = 10005, + X86_VPERMILPSZ128rmk = 10006, + X86_VPERMILPSZ128rmkz = 10007, + X86_VPERMILPSZ128rr = 10008, + X86_VPERMILPSZ128rrk = 10009, + X86_VPERMILPSZ128rrkz = 10010, + X86_VPERMILPSZ256mbi = 10011, + X86_VPERMILPSZ256mbik = 10012, + X86_VPERMILPSZ256mbikz = 10013, + X86_VPERMILPSZ256mi = 10014, + X86_VPERMILPSZ256mik = 10015, + X86_VPERMILPSZ256mikz = 10016, + X86_VPERMILPSZ256ri = 10017, + X86_VPERMILPSZ256rik = 10018, + X86_VPERMILPSZ256rikz = 10019, + X86_VPERMILPSZ256rm = 10020, + X86_VPERMILPSZ256rmb = 10021, + X86_VPERMILPSZ256rmbk = 10022, + X86_VPERMILPSZ256rmbkz = 10023, + X86_VPERMILPSZ256rmk = 10024, + X86_VPERMILPSZ256rmkz = 10025, + X86_VPERMILPSZ256rr = 10026, + X86_VPERMILPSZ256rrk = 10027, + X86_VPERMILPSZ256rrkz = 10028, + X86_VPERMILPSZmbi = 10029, + X86_VPERMILPSZmbik = 10030, + X86_VPERMILPSZmbikz = 10031, + X86_VPERMILPSZmi = 10032, + X86_VPERMILPSZmik = 10033, + X86_VPERMILPSZmikz = 10034, + X86_VPERMILPSZri = 10035, + X86_VPERMILPSZrik = 10036, + X86_VPERMILPSZrikz = 10037, + X86_VPERMILPSZrm = 10038, + X86_VPERMILPSZrmb = 10039, + X86_VPERMILPSZrmbk = 10040, + X86_VPERMILPSZrmbkz = 10041, + X86_VPERMILPSZrmk = 10042, + X86_VPERMILPSZrmkz = 10043, + X86_VPERMILPSZrr = 10044, + X86_VPERMILPSZrrk = 10045, + X86_VPERMILPSZrrkz = 10046, + X86_VPERMILPSmi = 10047, + X86_VPERMILPSri = 10048, + X86_VPERMILPSrm = 10049, + X86_VPERMILPSrr = 10050, + X86_VPERMPDYmi = 10051, + X86_VPERMPDYri = 10052, + X86_VPERMPDZ256mbi = 10053, + X86_VPERMPDZ256mbik = 10054, + X86_VPERMPDZ256mbikz = 10055, + X86_VPERMPDZ256mi = 10056, + X86_VPERMPDZ256mik = 10057, + X86_VPERMPDZ256mikz = 10058, + X86_VPERMPDZ256ri = 10059, + X86_VPERMPDZ256rik = 10060, + X86_VPERMPDZ256rikz = 10061, + X86_VPERMPDZ256rm = 10062, + X86_VPERMPDZ256rmb = 10063, + X86_VPERMPDZ256rmbk = 10064, + X86_VPERMPDZ256rmbkz = 10065, + X86_VPERMPDZ256rmk = 10066, + X86_VPERMPDZ256rmkz = 10067, + X86_VPERMPDZ256rr = 10068, + X86_VPERMPDZ256rrk = 10069, + X86_VPERMPDZ256rrkz = 10070, + X86_VPERMPDZmbi = 10071, + X86_VPERMPDZmbik = 10072, + X86_VPERMPDZmbikz = 10073, + X86_VPERMPDZmi = 10074, + X86_VPERMPDZmik = 10075, + X86_VPERMPDZmikz = 10076, + X86_VPERMPDZri = 10077, + X86_VPERMPDZrik = 10078, + X86_VPERMPDZrikz = 10079, + X86_VPERMPDZrm = 10080, + X86_VPERMPDZrmb = 10081, + X86_VPERMPDZrmbk = 10082, + X86_VPERMPDZrmbkz = 10083, + X86_VPERMPDZrmk = 10084, + X86_VPERMPDZrmkz = 10085, + X86_VPERMPDZrr = 10086, + X86_VPERMPDZrrk = 10087, + X86_VPERMPDZrrkz = 10088, + X86_VPERMPSYrm = 10089, + X86_VPERMPSYrr = 10090, + X86_VPERMPSZ256rm = 10091, + X86_VPERMPSZ256rmb = 10092, + X86_VPERMPSZ256rmbk = 10093, + X86_VPERMPSZ256rmbkz = 10094, + X86_VPERMPSZ256rmk = 10095, + X86_VPERMPSZ256rmkz = 10096, + X86_VPERMPSZ256rr = 10097, + X86_VPERMPSZ256rrk = 10098, + X86_VPERMPSZ256rrkz = 10099, + X86_VPERMPSZrm = 10100, + X86_VPERMPSZrmb = 10101, + X86_VPERMPSZrmbk = 10102, + X86_VPERMPSZrmbkz = 10103, + X86_VPERMPSZrmk = 10104, + X86_VPERMPSZrmkz = 10105, + X86_VPERMPSZrr = 10106, + X86_VPERMPSZrrk = 10107, + X86_VPERMPSZrrkz = 10108, + X86_VPERMQYmi = 10109, + X86_VPERMQYri = 10110, + X86_VPERMQZ256mbi = 10111, + X86_VPERMQZ256mbik = 10112, + X86_VPERMQZ256mbikz = 10113, + X86_VPERMQZ256mi = 10114, + X86_VPERMQZ256mik = 10115, + X86_VPERMQZ256mikz = 10116, + X86_VPERMQZ256ri = 10117, + X86_VPERMQZ256rik = 10118, + X86_VPERMQZ256rikz = 10119, + X86_VPERMQZ256rm = 10120, + X86_VPERMQZ256rmb = 10121, + X86_VPERMQZ256rmbk = 10122, + X86_VPERMQZ256rmbkz = 10123, + X86_VPERMQZ256rmk = 10124, + X86_VPERMQZ256rmkz = 10125, + X86_VPERMQZ256rr = 10126, + X86_VPERMQZ256rrk = 10127, + X86_VPERMQZ256rrkz = 10128, + X86_VPERMQZmbi = 10129, + X86_VPERMQZmbik = 10130, + X86_VPERMQZmbikz = 10131, + X86_VPERMQZmi = 10132, + X86_VPERMQZmik = 10133, + X86_VPERMQZmikz = 10134, + X86_VPERMQZri = 10135, + X86_VPERMQZrik = 10136, + X86_VPERMQZrikz = 10137, + X86_VPERMQZrm = 10138, + X86_VPERMQZrmb = 10139, + X86_VPERMQZrmbk = 10140, + X86_VPERMQZrmbkz = 10141, + X86_VPERMQZrmk = 10142, + X86_VPERMQZrmkz = 10143, + X86_VPERMQZrr = 10144, + X86_VPERMQZrrk = 10145, + X86_VPERMQZrrkz = 10146, + X86_VPERMT2B128rm = 10147, + X86_VPERMT2B128rmk = 10148, + X86_VPERMT2B128rmkz = 10149, + X86_VPERMT2B128rr = 10150, + X86_VPERMT2B128rrk = 10151, + X86_VPERMT2B128rrkz = 10152, + X86_VPERMT2B256rm = 10153, + X86_VPERMT2B256rmk = 10154, + X86_VPERMT2B256rmkz = 10155, + X86_VPERMT2B256rr = 10156, + X86_VPERMT2B256rrk = 10157, + X86_VPERMT2B256rrkz = 10158, + X86_VPERMT2Brm = 10159, + X86_VPERMT2Brmk = 10160, + X86_VPERMT2Brmkz = 10161, + X86_VPERMT2Brr = 10162, + X86_VPERMT2Brrk = 10163, + X86_VPERMT2Brrkz = 10164, + X86_VPERMT2D128rm = 10165, + X86_VPERMT2D128rmb = 10166, + X86_VPERMT2D128rmbk = 10167, + X86_VPERMT2D128rmbkz = 10168, + X86_VPERMT2D128rmk = 10169, + X86_VPERMT2D128rmkz = 10170, + X86_VPERMT2D128rr = 10171, + X86_VPERMT2D128rrk = 10172, + X86_VPERMT2D128rrkz = 10173, + X86_VPERMT2D256rm = 10174, + X86_VPERMT2D256rmb = 10175, + X86_VPERMT2D256rmbk = 10176, + X86_VPERMT2D256rmbkz = 10177, + X86_VPERMT2D256rmk = 10178, + X86_VPERMT2D256rmkz = 10179, + X86_VPERMT2D256rr = 10180, + X86_VPERMT2D256rrk = 10181, + X86_VPERMT2D256rrkz = 10182, + X86_VPERMT2Drm = 10183, + X86_VPERMT2Drmb = 10184, + X86_VPERMT2Drmbk = 10185, + X86_VPERMT2Drmbkz = 10186, + X86_VPERMT2Drmk = 10187, + X86_VPERMT2Drmkz = 10188, + X86_VPERMT2Drr = 10189, + X86_VPERMT2Drrk = 10190, + X86_VPERMT2Drrkz = 10191, + X86_VPERMT2PD128rm = 10192, + X86_VPERMT2PD128rmb = 10193, + X86_VPERMT2PD128rmbk = 10194, + X86_VPERMT2PD128rmbkz = 10195, + X86_VPERMT2PD128rmk = 10196, + X86_VPERMT2PD128rmkz = 10197, + X86_VPERMT2PD128rr = 10198, + X86_VPERMT2PD128rrk = 10199, + X86_VPERMT2PD128rrkz = 10200, + X86_VPERMT2PD256rm = 10201, + X86_VPERMT2PD256rmb = 10202, + X86_VPERMT2PD256rmbk = 10203, + X86_VPERMT2PD256rmbkz = 10204, + X86_VPERMT2PD256rmk = 10205, + X86_VPERMT2PD256rmkz = 10206, + X86_VPERMT2PD256rr = 10207, + X86_VPERMT2PD256rrk = 10208, + X86_VPERMT2PD256rrkz = 10209, + X86_VPERMT2PDrm = 10210, + X86_VPERMT2PDrmb = 10211, + X86_VPERMT2PDrmbk = 10212, + X86_VPERMT2PDrmbkz = 10213, + X86_VPERMT2PDrmk = 10214, + X86_VPERMT2PDrmkz = 10215, + X86_VPERMT2PDrr = 10216, + X86_VPERMT2PDrrk = 10217, + X86_VPERMT2PDrrkz = 10218, + X86_VPERMT2PS128rm = 10219, + X86_VPERMT2PS128rmb = 10220, + X86_VPERMT2PS128rmbk = 10221, + X86_VPERMT2PS128rmbkz = 10222, + X86_VPERMT2PS128rmk = 10223, + X86_VPERMT2PS128rmkz = 10224, + X86_VPERMT2PS128rr = 10225, + X86_VPERMT2PS128rrk = 10226, + X86_VPERMT2PS128rrkz = 10227, + X86_VPERMT2PS256rm = 10228, + X86_VPERMT2PS256rmb = 10229, + X86_VPERMT2PS256rmbk = 10230, + X86_VPERMT2PS256rmbkz = 10231, + X86_VPERMT2PS256rmk = 10232, + X86_VPERMT2PS256rmkz = 10233, + X86_VPERMT2PS256rr = 10234, + X86_VPERMT2PS256rrk = 10235, + X86_VPERMT2PS256rrkz = 10236, + X86_VPERMT2PSrm = 10237, + X86_VPERMT2PSrmb = 10238, + X86_VPERMT2PSrmbk = 10239, + X86_VPERMT2PSrmbkz = 10240, + X86_VPERMT2PSrmk = 10241, + X86_VPERMT2PSrmkz = 10242, + X86_VPERMT2PSrr = 10243, + X86_VPERMT2PSrrk = 10244, + X86_VPERMT2PSrrkz = 10245, + X86_VPERMT2Q128rm = 10246, + X86_VPERMT2Q128rmb = 10247, + X86_VPERMT2Q128rmbk = 10248, + X86_VPERMT2Q128rmbkz = 10249, + X86_VPERMT2Q128rmk = 10250, + X86_VPERMT2Q128rmkz = 10251, + X86_VPERMT2Q128rr = 10252, + X86_VPERMT2Q128rrk = 10253, + X86_VPERMT2Q128rrkz = 10254, + X86_VPERMT2Q256rm = 10255, + X86_VPERMT2Q256rmb = 10256, + X86_VPERMT2Q256rmbk = 10257, + X86_VPERMT2Q256rmbkz = 10258, + X86_VPERMT2Q256rmk = 10259, + X86_VPERMT2Q256rmkz = 10260, + X86_VPERMT2Q256rr = 10261, + X86_VPERMT2Q256rrk = 10262, + X86_VPERMT2Q256rrkz = 10263, + X86_VPERMT2Qrm = 10264, + X86_VPERMT2Qrmb = 10265, + X86_VPERMT2Qrmbk = 10266, + X86_VPERMT2Qrmbkz = 10267, + X86_VPERMT2Qrmk = 10268, + X86_VPERMT2Qrmkz = 10269, + X86_VPERMT2Qrr = 10270, + X86_VPERMT2Qrrk = 10271, + X86_VPERMT2Qrrkz = 10272, + X86_VPERMT2W128rm = 10273, + X86_VPERMT2W128rmk = 10274, + X86_VPERMT2W128rmkz = 10275, + X86_VPERMT2W128rr = 10276, + X86_VPERMT2W128rrk = 10277, + X86_VPERMT2W128rrkz = 10278, + X86_VPERMT2W256rm = 10279, + X86_VPERMT2W256rmk = 10280, + X86_VPERMT2W256rmkz = 10281, + X86_VPERMT2W256rr = 10282, + X86_VPERMT2W256rrk = 10283, + X86_VPERMT2W256rrkz = 10284, + X86_VPERMT2Wrm = 10285, + X86_VPERMT2Wrmk = 10286, + X86_VPERMT2Wrmkz = 10287, + X86_VPERMT2Wrr = 10288, + X86_VPERMT2Wrrk = 10289, + X86_VPERMT2Wrrkz = 10290, + X86_VPERMWZ128rm = 10291, + X86_VPERMWZ128rmk = 10292, + X86_VPERMWZ128rmkz = 10293, + X86_VPERMWZ128rr = 10294, + X86_VPERMWZ128rrk = 10295, + X86_VPERMWZ128rrkz = 10296, + X86_VPERMWZ256rm = 10297, + X86_VPERMWZ256rmk = 10298, + X86_VPERMWZ256rmkz = 10299, + X86_VPERMWZ256rr = 10300, + X86_VPERMWZ256rrk = 10301, + X86_VPERMWZ256rrkz = 10302, + X86_VPERMWZrm = 10303, + X86_VPERMWZrmk = 10304, + X86_VPERMWZrmkz = 10305, + X86_VPERMWZrr = 10306, + X86_VPERMWZrrk = 10307, + X86_VPERMWZrrkz = 10308, + X86_VPEXPANDBZ128rm = 10309, + X86_VPEXPANDBZ128rmk = 10310, + X86_VPEXPANDBZ128rmkz = 10311, + X86_VPEXPANDBZ128rr = 10312, + X86_VPEXPANDBZ128rrk = 10313, + X86_VPEXPANDBZ128rrkz = 10314, + X86_VPEXPANDBZ256rm = 10315, + X86_VPEXPANDBZ256rmk = 10316, + X86_VPEXPANDBZ256rmkz = 10317, + X86_VPEXPANDBZ256rr = 10318, + X86_VPEXPANDBZ256rrk = 10319, + X86_VPEXPANDBZ256rrkz = 10320, + X86_VPEXPANDBZrm = 10321, + X86_VPEXPANDBZrmk = 10322, + X86_VPEXPANDBZrmkz = 10323, + X86_VPEXPANDBZrr = 10324, + X86_VPEXPANDBZrrk = 10325, + X86_VPEXPANDBZrrkz = 10326, + X86_VPEXPANDDZ128rm = 10327, + X86_VPEXPANDDZ128rmk = 10328, + X86_VPEXPANDDZ128rmkz = 10329, + X86_VPEXPANDDZ128rr = 10330, + X86_VPEXPANDDZ128rrk = 10331, + X86_VPEXPANDDZ128rrkz = 10332, + X86_VPEXPANDDZ256rm = 10333, + X86_VPEXPANDDZ256rmk = 10334, + X86_VPEXPANDDZ256rmkz = 10335, + X86_VPEXPANDDZ256rr = 10336, + X86_VPEXPANDDZ256rrk = 10337, + X86_VPEXPANDDZ256rrkz = 10338, + X86_VPEXPANDDZrm = 10339, + X86_VPEXPANDDZrmk = 10340, + X86_VPEXPANDDZrmkz = 10341, + X86_VPEXPANDDZrr = 10342, + X86_VPEXPANDDZrrk = 10343, + X86_VPEXPANDDZrrkz = 10344, + X86_VPEXPANDQZ128rm = 10345, + X86_VPEXPANDQZ128rmk = 10346, + X86_VPEXPANDQZ128rmkz = 10347, + X86_VPEXPANDQZ128rr = 10348, + X86_VPEXPANDQZ128rrk = 10349, + X86_VPEXPANDQZ128rrkz = 10350, + X86_VPEXPANDQZ256rm = 10351, + X86_VPEXPANDQZ256rmk = 10352, + X86_VPEXPANDQZ256rmkz = 10353, + X86_VPEXPANDQZ256rr = 10354, + X86_VPEXPANDQZ256rrk = 10355, + X86_VPEXPANDQZ256rrkz = 10356, + X86_VPEXPANDQZrm = 10357, + X86_VPEXPANDQZrmk = 10358, + X86_VPEXPANDQZrmkz = 10359, + X86_VPEXPANDQZrr = 10360, + X86_VPEXPANDQZrrk = 10361, + X86_VPEXPANDQZrrkz = 10362, + X86_VPEXPANDWZ128rm = 10363, + X86_VPEXPANDWZ128rmk = 10364, + X86_VPEXPANDWZ128rmkz = 10365, + X86_VPEXPANDWZ128rr = 10366, + X86_VPEXPANDWZ128rrk = 10367, + X86_VPEXPANDWZ128rrkz = 10368, + X86_VPEXPANDWZ256rm = 10369, + X86_VPEXPANDWZ256rmk = 10370, + X86_VPEXPANDWZ256rmkz = 10371, + X86_VPEXPANDWZ256rr = 10372, + X86_VPEXPANDWZ256rrk = 10373, + X86_VPEXPANDWZ256rrkz = 10374, + X86_VPEXPANDWZrm = 10375, + X86_VPEXPANDWZrmk = 10376, + X86_VPEXPANDWZrmkz = 10377, + X86_VPEXPANDWZrr = 10378, + X86_VPEXPANDWZrrk = 10379, + X86_VPEXPANDWZrrkz = 10380, + X86_VPEXTRBZmr = 10381, + X86_VPEXTRBZrr = 10382, + X86_VPEXTRBmr = 10383, + X86_VPEXTRBrr = 10384, + X86_VPEXTRDZmr = 10385, + X86_VPEXTRDZrr = 10386, + X86_VPEXTRDmr = 10387, + X86_VPEXTRDrr = 10388, + X86_VPEXTRQZmr = 10389, + X86_VPEXTRQZrr = 10390, + X86_VPEXTRQmr = 10391, + X86_VPEXTRQrr = 10392, + X86_VPEXTRWZmr = 10393, + X86_VPEXTRWZrr = 10394, + X86_VPEXTRWZrr_REV = 10395, + X86_VPEXTRWmr = 10396, + X86_VPEXTRWrr = 10397, + X86_VPEXTRWrr_REV = 10398, + X86_VPGATHERDDYrm = 10399, + X86_VPGATHERDDZ128rm = 10400, + X86_VPGATHERDDZ256rm = 10401, + X86_VPGATHERDDZrm = 10402, + X86_VPGATHERDDrm = 10403, + X86_VPGATHERDQYrm = 10404, + X86_VPGATHERDQZ128rm = 10405, + X86_VPGATHERDQZ256rm = 10406, + X86_VPGATHERDQZrm = 10407, + X86_VPGATHERDQrm = 10408, + X86_VPGATHERQDYrm = 10409, + X86_VPGATHERQDZ128rm = 10410, + X86_VPGATHERQDZ256rm = 10411, + X86_VPGATHERQDZrm = 10412, + X86_VPGATHERQDrm = 10413, + X86_VPGATHERQQYrm = 10414, + X86_VPGATHERQQZ128rm = 10415, + X86_VPGATHERQQZ256rm = 10416, + X86_VPGATHERQQZrm = 10417, + X86_VPGATHERQQrm = 10418, + X86_VPHADDBDrm = 10419, + X86_VPHADDBDrr = 10420, + X86_VPHADDBQrm = 10421, + X86_VPHADDBQrr = 10422, + X86_VPHADDBWrm = 10423, + X86_VPHADDBWrr = 10424, + X86_VPHADDDQrm = 10425, + X86_VPHADDDQrr = 10426, + X86_VPHADDDYrm = 10427, + X86_VPHADDDYrr = 10428, + X86_VPHADDDrm = 10429, + X86_VPHADDDrr = 10430, + X86_VPHADDSWYrm = 10431, + X86_VPHADDSWYrr = 10432, + X86_VPHADDSWrm = 10433, + X86_VPHADDSWrr = 10434, + X86_VPHADDUBDrm = 10435, + X86_VPHADDUBDrr = 10436, + X86_VPHADDUBQrm = 10437, + X86_VPHADDUBQrr = 10438, + X86_VPHADDUBWrm = 10439, + X86_VPHADDUBWrr = 10440, + X86_VPHADDUDQrm = 10441, + X86_VPHADDUDQrr = 10442, + X86_VPHADDUWDrm = 10443, + X86_VPHADDUWDrr = 10444, + X86_VPHADDUWQrm = 10445, + X86_VPHADDUWQrr = 10446, + X86_VPHADDWDrm = 10447, + X86_VPHADDWDrr = 10448, + X86_VPHADDWQrm = 10449, + X86_VPHADDWQrr = 10450, + X86_VPHADDWYrm = 10451, + X86_VPHADDWYrr = 10452, + X86_VPHADDWrm = 10453, + X86_VPHADDWrr = 10454, + X86_VPHMINPOSUWrm = 10455, + X86_VPHMINPOSUWrr = 10456, + X86_VPHSUBBWrm = 10457, + X86_VPHSUBBWrr = 10458, + X86_VPHSUBDQrm = 10459, + X86_VPHSUBDQrr = 10460, + X86_VPHSUBDYrm = 10461, + X86_VPHSUBDYrr = 10462, + X86_VPHSUBDrm = 10463, + X86_VPHSUBDrr = 10464, + X86_VPHSUBSWYrm = 10465, + X86_VPHSUBSWYrr = 10466, + X86_VPHSUBSWrm = 10467, + X86_VPHSUBSWrr = 10468, + X86_VPHSUBWDrm = 10469, + X86_VPHSUBWDrr = 10470, + X86_VPHSUBWYrm = 10471, + X86_VPHSUBWYrr = 10472, + X86_VPHSUBWrm = 10473, + X86_VPHSUBWrr = 10474, + X86_VPINSRBZrm = 10475, + X86_VPINSRBZrr = 10476, + X86_VPINSRBrm = 10477, + X86_VPINSRBrr = 10478, + X86_VPINSRDZrm = 10479, + X86_VPINSRDZrr = 10480, + X86_VPINSRDrm = 10481, + X86_VPINSRDrr = 10482, + X86_VPINSRQZrm = 10483, + X86_VPINSRQZrr = 10484, + X86_VPINSRQrm = 10485, + X86_VPINSRQrr = 10486, + X86_VPINSRWZrm = 10487, + X86_VPINSRWZrr = 10488, + X86_VPINSRWrm = 10489, + X86_VPINSRWrr = 10490, + X86_VPLZCNTDZ128rm = 10491, + X86_VPLZCNTDZ128rmb = 10492, + X86_VPLZCNTDZ128rmbk = 10493, + X86_VPLZCNTDZ128rmbkz = 10494, + X86_VPLZCNTDZ128rmk = 10495, + X86_VPLZCNTDZ128rmkz = 10496, + X86_VPLZCNTDZ128rr = 10497, + X86_VPLZCNTDZ128rrk = 10498, + X86_VPLZCNTDZ128rrkz = 10499, + X86_VPLZCNTDZ256rm = 10500, + X86_VPLZCNTDZ256rmb = 10501, + X86_VPLZCNTDZ256rmbk = 10502, + X86_VPLZCNTDZ256rmbkz = 10503, + X86_VPLZCNTDZ256rmk = 10504, + X86_VPLZCNTDZ256rmkz = 10505, + X86_VPLZCNTDZ256rr = 10506, + X86_VPLZCNTDZ256rrk = 10507, + X86_VPLZCNTDZ256rrkz = 10508, + X86_VPLZCNTDZrm = 10509, + X86_VPLZCNTDZrmb = 10510, + X86_VPLZCNTDZrmbk = 10511, + X86_VPLZCNTDZrmbkz = 10512, + X86_VPLZCNTDZrmk = 10513, + X86_VPLZCNTDZrmkz = 10514, + X86_VPLZCNTDZrr = 10515, + X86_VPLZCNTDZrrk = 10516, + X86_VPLZCNTDZrrkz = 10517, + X86_VPLZCNTQZ128rm = 10518, + X86_VPLZCNTQZ128rmb = 10519, + X86_VPLZCNTQZ128rmbk = 10520, + X86_VPLZCNTQZ128rmbkz = 10521, + X86_VPLZCNTQZ128rmk = 10522, + X86_VPLZCNTQZ128rmkz = 10523, + X86_VPLZCNTQZ128rr = 10524, + X86_VPLZCNTQZ128rrk = 10525, + X86_VPLZCNTQZ128rrkz = 10526, + X86_VPLZCNTQZ256rm = 10527, + X86_VPLZCNTQZ256rmb = 10528, + X86_VPLZCNTQZ256rmbk = 10529, + X86_VPLZCNTQZ256rmbkz = 10530, + X86_VPLZCNTQZ256rmk = 10531, + X86_VPLZCNTQZ256rmkz = 10532, + X86_VPLZCNTQZ256rr = 10533, + X86_VPLZCNTQZ256rrk = 10534, + X86_VPLZCNTQZ256rrkz = 10535, + X86_VPLZCNTQZrm = 10536, + X86_VPLZCNTQZrmb = 10537, + X86_VPLZCNTQZrmbk = 10538, + X86_VPLZCNTQZrmbkz = 10539, + X86_VPLZCNTQZrmk = 10540, + X86_VPLZCNTQZrmkz = 10541, + X86_VPLZCNTQZrr = 10542, + X86_VPLZCNTQZrrk = 10543, + X86_VPLZCNTQZrrkz = 10544, + X86_VPMACSDDrm = 10545, + X86_VPMACSDDrr = 10546, + X86_VPMACSDQHrm = 10547, + X86_VPMACSDQHrr = 10548, + X86_VPMACSDQLrm = 10549, + X86_VPMACSDQLrr = 10550, + X86_VPMACSSDDrm = 10551, + X86_VPMACSSDDrr = 10552, + X86_VPMACSSDQHrm = 10553, + X86_VPMACSSDQHrr = 10554, + X86_VPMACSSDQLrm = 10555, + X86_VPMACSSDQLrr = 10556, + X86_VPMACSSWDrm = 10557, + X86_VPMACSSWDrr = 10558, + X86_VPMACSSWWrm = 10559, + X86_VPMACSSWWrr = 10560, + X86_VPMACSWDrm = 10561, + X86_VPMACSWDrr = 10562, + X86_VPMACSWWrm = 10563, + X86_VPMACSWWrr = 10564, + X86_VPMADCSSWDrm = 10565, + X86_VPMADCSSWDrr = 10566, + X86_VPMADCSWDrm = 10567, + X86_VPMADCSWDrr = 10568, + X86_VPMADD52HUQZ128m = 10569, + X86_VPMADD52HUQZ128mb = 10570, + X86_VPMADD52HUQZ128mbk = 10571, + X86_VPMADD52HUQZ128mbkz = 10572, + X86_VPMADD52HUQZ128mk = 10573, + X86_VPMADD52HUQZ128mkz = 10574, + X86_VPMADD52HUQZ128r = 10575, + X86_VPMADD52HUQZ128rk = 10576, + X86_VPMADD52HUQZ128rkz = 10577, + X86_VPMADD52HUQZ256m = 10578, + X86_VPMADD52HUQZ256mb = 10579, + X86_VPMADD52HUQZ256mbk = 10580, + X86_VPMADD52HUQZ256mbkz = 10581, + X86_VPMADD52HUQZ256mk = 10582, + X86_VPMADD52HUQZ256mkz = 10583, + X86_VPMADD52HUQZ256r = 10584, + X86_VPMADD52HUQZ256rk = 10585, + X86_VPMADD52HUQZ256rkz = 10586, + X86_VPMADD52HUQZm = 10587, + X86_VPMADD52HUQZmb = 10588, + X86_VPMADD52HUQZmbk = 10589, + X86_VPMADD52HUQZmbkz = 10590, + X86_VPMADD52HUQZmk = 10591, + X86_VPMADD52HUQZmkz = 10592, + X86_VPMADD52HUQZr = 10593, + X86_VPMADD52HUQZrk = 10594, + X86_VPMADD52HUQZrkz = 10595, + X86_VPMADD52LUQZ128m = 10596, + X86_VPMADD52LUQZ128mb = 10597, + X86_VPMADD52LUQZ128mbk = 10598, + X86_VPMADD52LUQZ128mbkz = 10599, + X86_VPMADD52LUQZ128mk = 10600, + X86_VPMADD52LUQZ128mkz = 10601, + X86_VPMADD52LUQZ128r = 10602, + X86_VPMADD52LUQZ128rk = 10603, + X86_VPMADD52LUQZ128rkz = 10604, + X86_VPMADD52LUQZ256m = 10605, + X86_VPMADD52LUQZ256mb = 10606, + X86_VPMADD52LUQZ256mbk = 10607, + X86_VPMADD52LUQZ256mbkz = 10608, + X86_VPMADD52LUQZ256mk = 10609, + X86_VPMADD52LUQZ256mkz = 10610, + X86_VPMADD52LUQZ256r = 10611, + X86_VPMADD52LUQZ256rk = 10612, + X86_VPMADD52LUQZ256rkz = 10613, + X86_VPMADD52LUQZm = 10614, + X86_VPMADD52LUQZmb = 10615, + X86_VPMADD52LUQZmbk = 10616, + X86_VPMADD52LUQZmbkz = 10617, + X86_VPMADD52LUQZmk = 10618, + X86_VPMADD52LUQZmkz = 10619, + X86_VPMADD52LUQZr = 10620, + X86_VPMADD52LUQZrk = 10621, + X86_VPMADD52LUQZrkz = 10622, + X86_VPMADDUBSWYrm = 10623, + X86_VPMADDUBSWYrr = 10624, + X86_VPMADDUBSWZ128rm = 10625, + X86_VPMADDUBSWZ128rmk = 10626, + X86_VPMADDUBSWZ128rmkz = 10627, + X86_VPMADDUBSWZ128rr = 10628, + X86_VPMADDUBSWZ128rrk = 10629, + X86_VPMADDUBSWZ128rrkz = 10630, + X86_VPMADDUBSWZ256rm = 10631, + X86_VPMADDUBSWZ256rmk = 10632, + X86_VPMADDUBSWZ256rmkz = 10633, + X86_VPMADDUBSWZ256rr = 10634, + X86_VPMADDUBSWZ256rrk = 10635, + X86_VPMADDUBSWZ256rrkz = 10636, + X86_VPMADDUBSWZrm = 10637, + X86_VPMADDUBSWZrmk = 10638, + X86_VPMADDUBSWZrmkz = 10639, + X86_VPMADDUBSWZrr = 10640, + X86_VPMADDUBSWZrrk = 10641, + X86_VPMADDUBSWZrrkz = 10642, + X86_VPMADDUBSWrm = 10643, + X86_VPMADDUBSWrr = 10644, + X86_VPMADDWDYrm = 10645, + X86_VPMADDWDYrr = 10646, + X86_VPMADDWDZ128rm = 10647, + X86_VPMADDWDZ128rmk = 10648, + X86_VPMADDWDZ128rmkz = 10649, + X86_VPMADDWDZ128rr = 10650, + X86_VPMADDWDZ128rrk = 10651, + X86_VPMADDWDZ128rrkz = 10652, + X86_VPMADDWDZ256rm = 10653, + X86_VPMADDWDZ256rmk = 10654, + X86_VPMADDWDZ256rmkz = 10655, + X86_VPMADDWDZ256rr = 10656, + X86_VPMADDWDZ256rrk = 10657, + X86_VPMADDWDZ256rrkz = 10658, + X86_VPMADDWDZrm = 10659, + X86_VPMADDWDZrmk = 10660, + X86_VPMADDWDZrmkz = 10661, + X86_VPMADDWDZrr = 10662, + X86_VPMADDWDZrrk = 10663, + X86_VPMADDWDZrrkz = 10664, + X86_VPMADDWDrm = 10665, + X86_VPMADDWDrr = 10666, + X86_VPMASKMOVDYmr = 10667, + X86_VPMASKMOVDYrm = 10668, + X86_VPMASKMOVDmr = 10669, + X86_VPMASKMOVDrm = 10670, + X86_VPMASKMOVQYmr = 10671, + X86_VPMASKMOVQYrm = 10672, + X86_VPMASKMOVQmr = 10673, + X86_VPMASKMOVQrm = 10674, + X86_VPMAXSBYrm = 10675, + X86_VPMAXSBYrr = 10676, + X86_VPMAXSBZ128rm = 10677, + X86_VPMAXSBZ128rmk = 10678, + X86_VPMAXSBZ128rmkz = 10679, + X86_VPMAXSBZ128rr = 10680, + X86_VPMAXSBZ128rrk = 10681, + X86_VPMAXSBZ128rrkz = 10682, + X86_VPMAXSBZ256rm = 10683, + X86_VPMAXSBZ256rmk = 10684, + X86_VPMAXSBZ256rmkz = 10685, + X86_VPMAXSBZ256rr = 10686, + X86_VPMAXSBZ256rrk = 10687, + X86_VPMAXSBZ256rrkz = 10688, + X86_VPMAXSBZrm = 10689, + X86_VPMAXSBZrmk = 10690, + X86_VPMAXSBZrmkz = 10691, + X86_VPMAXSBZrr = 10692, + X86_VPMAXSBZrrk = 10693, + X86_VPMAXSBZrrkz = 10694, + X86_VPMAXSBrm = 10695, + X86_VPMAXSBrr = 10696, + X86_VPMAXSDYrm = 10697, + X86_VPMAXSDYrr = 10698, + X86_VPMAXSDZ128rm = 10699, + X86_VPMAXSDZ128rmb = 10700, + X86_VPMAXSDZ128rmbk = 10701, + X86_VPMAXSDZ128rmbkz = 10702, + X86_VPMAXSDZ128rmk = 10703, + X86_VPMAXSDZ128rmkz = 10704, + X86_VPMAXSDZ128rr = 10705, + X86_VPMAXSDZ128rrk = 10706, + X86_VPMAXSDZ128rrkz = 10707, + X86_VPMAXSDZ256rm = 10708, + X86_VPMAXSDZ256rmb = 10709, + X86_VPMAXSDZ256rmbk = 10710, + X86_VPMAXSDZ256rmbkz = 10711, + X86_VPMAXSDZ256rmk = 10712, + X86_VPMAXSDZ256rmkz = 10713, + X86_VPMAXSDZ256rr = 10714, + X86_VPMAXSDZ256rrk = 10715, + X86_VPMAXSDZ256rrkz = 10716, + X86_VPMAXSDZrm = 10717, + X86_VPMAXSDZrmb = 10718, + X86_VPMAXSDZrmbk = 10719, + X86_VPMAXSDZrmbkz = 10720, + X86_VPMAXSDZrmk = 10721, + X86_VPMAXSDZrmkz = 10722, + X86_VPMAXSDZrr = 10723, + X86_VPMAXSDZrrk = 10724, + X86_VPMAXSDZrrkz = 10725, + X86_VPMAXSDrm = 10726, + X86_VPMAXSDrr = 10727, + X86_VPMAXSQZ128rm = 10728, + X86_VPMAXSQZ128rmb = 10729, + X86_VPMAXSQZ128rmbk = 10730, + X86_VPMAXSQZ128rmbkz = 10731, + X86_VPMAXSQZ128rmk = 10732, + X86_VPMAXSQZ128rmkz = 10733, + X86_VPMAXSQZ128rr = 10734, + X86_VPMAXSQZ128rrk = 10735, + X86_VPMAXSQZ128rrkz = 10736, + X86_VPMAXSQZ256rm = 10737, + X86_VPMAXSQZ256rmb = 10738, + X86_VPMAXSQZ256rmbk = 10739, + X86_VPMAXSQZ256rmbkz = 10740, + X86_VPMAXSQZ256rmk = 10741, + X86_VPMAXSQZ256rmkz = 10742, + X86_VPMAXSQZ256rr = 10743, + X86_VPMAXSQZ256rrk = 10744, + X86_VPMAXSQZ256rrkz = 10745, + X86_VPMAXSQZrm = 10746, + X86_VPMAXSQZrmb = 10747, + X86_VPMAXSQZrmbk = 10748, + X86_VPMAXSQZrmbkz = 10749, + X86_VPMAXSQZrmk = 10750, + X86_VPMAXSQZrmkz = 10751, + X86_VPMAXSQZrr = 10752, + X86_VPMAXSQZrrk = 10753, + X86_VPMAXSQZrrkz = 10754, + X86_VPMAXSWYrm = 10755, + X86_VPMAXSWYrr = 10756, + X86_VPMAXSWZ128rm = 10757, + X86_VPMAXSWZ128rmk = 10758, + X86_VPMAXSWZ128rmkz = 10759, + X86_VPMAXSWZ128rr = 10760, + X86_VPMAXSWZ128rrk = 10761, + X86_VPMAXSWZ128rrkz = 10762, + X86_VPMAXSWZ256rm = 10763, + X86_VPMAXSWZ256rmk = 10764, + X86_VPMAXSWZ256rmkz = 10765, + X86_VPMAXSWZ256rr = 10766, + X86_VPMAXSWZ256rrk = 10767, + X86_VPMAXSWZ256rrkz = 10768, + X86_VPMAXSWZrm = 10769, + X86_VPMAXSWZrmk = 10770, + X86_VPMAXSWZrmkz = 10771, + X86_VPMAXSWZrr = 10772, + X86_VPMAXSWZrrk = 10773, + X86_VPMAXSWZrrkz = 10774, + X86_VPMAXSWrm = 10775, + X86_VPMAXSWrr = 10776, + X86_VPMAXUBYrm = 10777, + X86_VPMAXUBYrr = 10778, + X86_VPMAXUBZ128rm = 10779, + X86_VPMAXUBZ128rmk = 10780, + X86_VPMAXUBZ128rmkz = 10781, + X86_VPMAXUBZ128rr = 10782, + X86_VPMAXUBZ128rrk = 10783, + X86_VPMAXUBZ128rrkz = 10784, + X86_VPMAXUBZ256rm = 10785, + X86_VPMAXUBZ256rmk = 10786, + X86_VPMAXUBZ256rmkz = 10787, + X86_VPMAXUBZ256rr = 10788, + X86_VPMAXUBZ256rrk = 10789, + X86_VPMAXUBZ256rrkz = 10790, + X86_VPMAXUBZrm = 10791, + X86_VPMAXUBZrmk = 10792, + X86_VPMAXUBZrmkz = 10793, + X86_VPMAXUBZrr = 10794, + X86_VPMAXUBZrrk = 10795, + X86_VPMAXUBZrrkz = 10796, + X86_VPMAXUBrm = 10797, + X86_VPMAXUBrr = 10798, + X86_VPMAXUDYrm = 10799, + X86_VPMAXUDYrr = 10800, + X86_VPMAXUDZ128rm = 10801, + X86_VPMAXUDZ128rmb = 10802, + X86_VPMAXUDZ128rmbk = 10803, + X86_VPMAXUDZ128rmbkz = 10804, + X86_VPMAXUDZ128rmk = 10805, + X86_VPMAXUDZ128rmkz = 10806, + X86_VPMAXUDZ128rr = 10807, + X86_VPMAXUDZ128rrk = 10808, + X86_VPMAXUDZ128rrkz = 10809, + X86_VPMAXUDZ256rm = 10810, + X86_VPMAXUDZ256rmb = 10811, + X86_VPMAXUDZ256rmbk = 10812, + X86_VPMAXUDZ256rmbkz = 10813, + X86_VPMAXUDZ256rmk = 10814, + X86_VPMAXUDZ256rmkz = 10815, + X86_VPMAXUDZ256rr = 10816, + X86_VPMAXUDZ256rrk = 10817, + X86_VPMAXUDZ256rrkz = 10818, + X86_VPMAXUDZrm = 10819, + X86_VPMAXUDZrmb = 10820, + X86_VPMAXUDZrmbk = 10821, + X86_VPMAXUDZrmbkz = 10822, + X86_VPMAXUDZrmk = 10823, + X86_VPMAXUDZrmkz = 10824, + X86_VPMAXUDZrr = 10825, + X86_VPMAXUDZrrk = 10826, + X86_VPMAXUDZrrkz = 10827, + X86_VPMAXUDrm = 10828, + X86_VPMAXUDrr = 10829, + X86_VPMAXUQZ128rm = 10830, + X86_VPMAXUQZ128rmb = 10831, + X86_VPMAXUQZ128rmbk = 10832, + X86_VPMAXUQZ128rmbkz = 10833, + X86_VPMAXUQZ128rmk = 10834, + X86_VPMAXUQZ128rmkz = 10835, + X86_VPMAXUQZ128rr = 10836, + X86_VPMAXUQZ128rrk = 10837, + X86_VPMAXUQZ128rrkz = 10838, + X86_VPMAXUQZ256rm = 10839, + X86_VPMAXUQZ256rmb = 10840, + X86_VPMAXUQZ256rmbk = 10841, + X86_VPMAXUQZ256rmbkz = 10842, + X86_VPMAXUQZ256rmk = 10843, + X86_VPMAXUQZ256rmkz = 10844, + X86_VPMAXUQZ256rr = 10845, + X86_VPMAXUQZ256rrk = 10846, + X86_VPMAXUQZ256rrkz = 10847, + X86_VPMAXUQZrm = 10848, + X86_VPMAXUQZrmb = 10849, + X86_VPMAXUQZrmbk = 10850, + X86_VPMAXUQZrmbkz = 10851, + X86_VPMAXUQZrmk = 10852, + X86_VPMAXUQZrmkz = 10853, + X86_VPMAXUQZrr = 10854, + X86_VPMAXUQZrrk = 10855, + X86_VPMAXUQZrrkz = 10856, + X86_VPMAXUWYrm = 10857, + X86_VPMAXUWYrr = 10858, + X86_VPMAXUWZ128rm = 10859, + X86_VPMAXUWZ128rmk = 10860, + X86_VPMAXUWZ128rmkz = 10861, + X86_VPMAXUWZ128rr = 10862, + X86_VPMAXUWZ128rrk = 10863, + X86_VPMAXUWZ128rrkz = 10864, + X86_VPMAXUWZ256rm = 10865, + X86_VPMAXUWZ256rmk = 10866, + X86_VPMAXUWZ256rmkz = 10867, + X86_VPMAXUWZ256rr = 10868, + X86_VPMAXUWZ256rrk = 10869, + X86_VPMAXUWZ256rrkz = 10870, + X86_VPMAXUWZrm = 10871, + X86_VPMAXUWZrmk = 10872, + X86_VPMAXUWZrmkz = 10873, + X86_VPMAXUWZrr = 10874, + X86_VPMAXUWZrrk = 10875, + X86_VPMAXUWZrrkz = 10876, + X86_VPMAXUWrm = 10877, + X86_VPMAXUWrr = 10878, + X86_VPMINSBYrm = 10879, + X86_VPMINSBYrr = 10880, + X86_VPMINSBZ128rm = 10881, + X86_VPMINSBZ128rmk = 10882, + X86_VPMINSBZ128rmkz = 10883, + X86_VPMINSBZ128rr = 10884, + X86_VPMINSBZ128rrk = 10885, + X86_VPMINSBZ128rrkz = 10886, + X86_VPMINSBZ256rm = 10887, + X86_VPMINSBZ256rmk = 10888, + X86_VPMINSBZ256rmkz = 10889, + X86_VPMINSBZ256rr = 10890, + X86_VPMINSBZ256rrk = 10891, + X86_VPMINSBZ256rrkz = 10892, + X86_VPMINSBZrm = 10893, + X86_VPMINSBZrmk = 10894, + X86_VPMINSBZrmkz = 10895, + X86_VPMINSBZrr = 10896, + X86_VPMINSBZrrk = 10897, + X86_VPMINSBZrrkz = 10898, + X86_VPMINSBrm = 10899, + X86_VPMINSBrr = 10900, + X86_VPMINSDYrm = 10901, + X86_VPMINSDYrr = 10902, + X86_VPMINSDZ128rm = 10903, + X86_VPMINSDZ128rmb = 10904, + X86_VPMINSDZ128rmbk = 10905, + X86_VPMINSDZ128rmbkz = 10906, + X86_VPMINSDZ128rmk = 10907, + X86_VPMINSDZ128rmkz = 10908, + X86_VPMINSDZ128rr = 10909, + X86_VPMINSDZ128rrk = 10910, + X86_VPMINSDZ128rrkz = 10911, + X86_VPMINSDZ256rm = 10912, + X86_VPMINSDZ256rmb = 10913, + X86_VPMINSDZ256rmbk = 10914, + X86_VPMINSDZ256rmbkz = 10915, + X86_VPMINSDZ256rmk = 10916, + X86_VPMINSDZ256rmkz = 10917, + X86_VPMINSDZ256rr = 10918, + X86_VPMINSDZ256rrk = 10919, + X86_VPMINSDZ256rrkz = 10920, + X86_VPMINSDZrm = 10921, + X86_VPMINSDZrmb = 10922, + X86_VPMINSDZrmbk = 10923, + X86_VPMINSDZrmbkz = 10924, + X86_VPMINSDZrmk = 10925, + X86_VPMINSDZrmkz = 10926, + X86_VPMINSDZrr = 10927, + X86_VPMINSDZrrk = 10928, + X86_VPMINSDZrrkz = 10929, + X86_VPMINSDrm = 10930, + X86_VPMINSDrr = 10931, + X86_VPMINSQZ128rm = 10932, + X86_VPMINSQZ128rmb = 10933, + X86_VPMINSQZ128rmbk = 10934, + X86_VPMINSQZ128rmbkz = 10935, + X86_VPMINSQZ128rmk = 10936, + X86_VPMINSQZ128rmkz = 10937, + X86_VPMINSQZ128rr = 10938, + X86_VPMINSQZ128rrk = 10939, + X86_VPMINSQZ128rrkz = 10940, + X86_VPMINSQZ256rm = 10941, + X86_VPMINSQZ256rmb = 10942, + X86_VPMINSQZ256rmbk = 10943, + X86_VPMINSQZ256rmbkz = 10944, + X86_VPMINSQZ256rmk = 10945, + X86_VPMINSQZ256rmkz = 10946, + X86_VPMINSQZ256rr = 10947, + X86_VPMINSQZ256rrk = 10948, + X86_VPMINSQZ256rrkz = 10949, + X86_VPMINSQZrm = 10950, + X86_VPMINSQZrmb = 10951, + X86_VPMINSQZrmbk = 10952, + X86_VPMINSQZrmbkz = 10953, + X86_VPMINSQZrmk = 10954, + X86_VPMINSQZrmkz = 10955, + X86_VPMINSQZrr = 10956, + X86_VPMINSQZrrk = 10957, + X86_VPMINSQZrrkz = 10958, + X86_VPMINSWYrm = 10959, + X86_VPMINSWYrr = 10960, + X86_VPMINSWZ128rm = 10961, + X86_VPMINSWZ128rmk = 10962, + X86_VPMINSWZ128rmkz = 10963, + X86_VPMINSWZ128rr = 10964, + X86_VPMINSWZ128rrk = 10965, + X86_VPMINSWZ128rrkz = 10966, + X86_VPMINSWZ256rm = 10967, + X86_VPMINSWZ256rmk = 10968, + X86_VPMINSWZ256rmkz = 10969, + X86_VPMINSWZ256rr = 10970, + X86_VPMINSWZ256rrk = 10971, + X86_VPMINSWZ256rrkz = 10972, + X86_VPMINSWZrm = 10973, + X86_VPMINSWZrmk = 10974, + X86_VPMINSWZrmkz = 10975, + X86_VPMINSWZrr = 10976, + X86_VPMINSWZrrk = 10977, + X86_VPMINSWZrrkz = 10978, + X86_VPMINSWrm = 10979, + X86_VPMINSWrr = 10980, + X86_VPMINUBYrm = 10981, + X86_VPMINUBYrr = 10982, + X86_VPMINUBZ128rm = 10983, + X86_VPMINUBZ128rmk = 10984, + X86_VPMINUBZ128rmkz = 10985, + X86_VPMINUBZ128rr = 10986, + X86_VPMINUBZ128rrk = 10987, + X86_VPMINUBZ128rrkz = 10988, + X86_VPMINUBZ256rm = 10989, + X86_VPMINUBZ256rmk = 10990, + X86_VPMINUBZ256rmkz = 10991, + X86_VPMINUBZ256rr = 10992, + X86_VPMINUBZ256rrk = 10993, + X86_VPMINUBZ256rrkz = 10994, + X86_VPMINUBZrm = 10995, + X86_VPMINUBZrmk = 10996, + X86_VPMINUBZrmkz = 10997, + X86_VPMINUBZrr = 10998, + X86_VPMINUBZrrk = 10999, + X86_VPMINUBZrrkz = 11000, + X86_VPMINUBrm = 11001, + X86_VPMINUBrr = 11002, + X86_VPMINUDYrm = 11003, + X86_VPMINUDYrr = 11004, + X86_VPMINUDZ128rm = 11005, + X86_VPMINUDZ128rmb = 11006, + X86_VPMINUDZ128rmbk = 11007, + X86_VPMINUDZ128rmbkz = 11008, + X86_VPMINUDZ128rmk = 11009, + X86_VPMINUDZ128rmkz = 11010, + X86_VPMINUDZ128rr = 11011, + X86_VPMINUDZ128rrk = 11012, + X86_VPMINUDZ128rrkz = 11013, + X86_VPMINUDZ256rm = 11014, + X86_VPMINUDZ256rmb = 11015, + X86_VPMINUDZ256rmbk = 11016, + X86_VPMINUDZ256rmbkz = 11017, + X86_VPMINUDZ256rmk = 11018, + X86_VPMINUDZ256rmkz = 11019, + X86_VPMINUDZ256rr = 11020, + X86_VPMINUDZ256rrk = 11021, + X86_VPMINUDZ256rrkz = 11022, + X86_VPMINUDZrm = 11023, + X86_VPMINUDZrmb = 11024, + X86_VPMINUDZrmbk = 11025, + X86_VPMINUDZrmbkz = 11026, + X86_VPMINUDZrmk = 11027, + X86_VPMINUDZrmkz = 11028, + X86_VPMINUDZrr = 11029, + X86_VPMINUDZrrk = 11030, + X86_VPMINUDZrrkz = 11031, + X86_VPMINUDrm = 11032, + X86_VPMINUDrr = 11033, + X86_VPMINUQZ128rm = 11034, + X86_VPMINUQZ128rmb = 11035, + X86_VPMINUQZ128rmbk = 11036, + X86_VPMINUQZ128rmbkz = 11037, + X86_VPMINUQZ128rmk = 11038, + X86_VPMINUQZ128rmkz = 11039, + X86_VPMINUQZ128rr = 11040, + X86_VPMINUQZ128rrk = 11041, + X86_VPMINUQZ128rrkz = 11042, + X86_VPMINUQZ256rm = 11043, + X86_VPMINUQZ256rmb = 11044, + X86_VPMINUQZ256rmbk = 11045, + X86_VPMINUQZ256rmbkz = 11046, + X86_VPMINUQZ256rmk = 11047, + X86_VPMINUQZ256rmkz = 11048, + X86_VPMINUQZ256rr = 11049, + X86_VPMINUQZ256rrk = 11050, + X86_VPMINUQZ256rrkz = 11051, + X86_VPMINUQZrm = 11052, + X86_VPMINUQZrmb = 11053, + X86_VPMINUQZrmbk = 11054, + X86_VPMINUQZrmbkz = 11055, + X86_VPMINUQZrmk = 11056, + X86_VPMINUQZrmkz = 11057, + X86_VPMINUQZrr = 11058, + X86_VPMINUQZrrk = 11059, + X86_VPMINUQZrrkz = 11060, + X86_VPMINUWYrm = 11061, + X86_VPMINUWYrr = 11062, + X86_VPMINUWZ128rm = 11063, + X86_VPMINUWZ128rmk = 11064, + X86_VPMINUWZ128rmkz = 11065, + X86_VPMINUWZ128rr = 11066, + X86_VPMINUWZ128rrk = 11067, + X86_VPMINUWZ128rrkz = 11068, + X86_VPMINUWZ256rm = 11069, + X86_VPMINUWZ256rmk = 11070, + X86_VPMINUWZ256rmkz = 11071, + X86_VPMINUWZ256rr = 11072, + X86_VPMINUWZ256rrk = 11073, + X86_VPMINUWZ256rrkz = 11074, + X86_VPMINUWZrm = 11075, + X86_VPMINUWZrmk = 11076, + X86_VPMINUWZrmkz = 11077, + X86_VPMINUWZrr = 11078, + X86_VPMINUWZrrk = 11079, + X86_VPMINUWZrrkz = 11080, + X86_VPMINUWrm = 11081, + X86_VPMINUWrr = 11082, + X86_VPMOVB2MZ128rr = 11083, + X86_VPMOVB2MZ256rr = 11084, + X86_VPMOVB2MZrr = 11085, + X86_VPMOVD2MZ128rr = 11086, + X86_VPMOVD2MZ256rr = 11087, + X86_VPMOVD2MZrr = 11088, + X86_VPMOVDBZ128mr = 11089, + X86_VPMOVDBZ128mrk = 11090, + X86_VPMOVDBZ128rr = 11091, + X86_VPMOVDBZ128rrk = 11092, + X86_VPMOVDBZ128rrkz = 11093, + X86_VPMOVDBZ256mr = 11094, + X86_VPMOVDBZ256mrk = 11095, + X86_VPMOVDBZ256rr = 11096, + X86_VPMOVDBZ256rrk = 11097, + X86_VPMOVDBZ256rrkz = 11098, + X86_VPMOVDBZmr = 11099, + X86_VPMOVDBZmrk = 11100, + X86_VPMOVDBZrr = 11101, + X86_VPMOVDBZrrk = 11102, + X86_VPMOVDBZrrkz = 11103, + X86_VPMOVDWZ128mr = 11104, + X86_VPMOVDWZ128mrk = 11105, + X86_VPMOVDWZ128rr = 11106, + X86_VPMOVDWZ128rrk = 11107, + X86_VPMOVDWZ128rrkz = 11108, + X86_VPMOVDWZ256mr = 11109, + X86_VPMOVDWZ256mrk = 11110, + X86_VPMOVDWZ256rr = 11111, + X86_VPMOVDWZ256rrk = 11112, + X86_VPMOVDWZ256rrkz = 11113, + X86_VPMOVDWZmr = 11114, + X86_VPMOVDWZmrk = 11115, + X86_VPMOVDWZrr = 11116, + X86_VPMOVDWZrrk = 11117, + X86_VPMOVDWZrrkz = 11118, + X86_VPMOVM2BZ128rr = 11119, + X86_VPMOVM2BZ256rr = 11120, + X86_VPMOVM2BZrr = 11121, + X86_VPMOVM2DZ128rr = 11122, + X86_VPMOVM2DZ256rr = 11123, + X86_VPMOVM2DZrr = 11124, + X86_VPMOVM2QZ128rr = 11125, + X86_VPMOVM2QZ256rr = 11126, + X86_VPMOVM2QZrr = 11127, + X86_VPMOVM2WZ128rr = 11128, + X86_VPMOVM2WZ256rr = 11129, + X86_VPMOVM2WZrr = 11130, + X86_VPMOVMSKBYrr = 11131, + X86_VPMOVMSKBrr = 11132, + X86_VPMOVQ2MZ128rr = 11133, + X86_VPMOVQ2MZ256rr = 11134, + X86_VPMOVQ2MZrr = 11135, + X86_VPMOVQBZ128mr = 11136, + X86_VPMOVQBZ128mrk = 11137, + X86_VPMOVQBZ128rr = 11138, + X86_VPMOVQBZ128rrk = 11139, + X86_VPMOVQBZ128rrkz = 11140, + X86_VPMOVQBZ256mr = 11141, + X86_VPMOVQBZ256mrk = 11142, + X86_VPMOVQBZ256rr = 11143, + X86_VPMOVQBZ256rrk = 11144, + X86_VPMOVQBZ256rrkz = 11145, + X86_VPMOVQBZmr = 11146, + X86_VPMOVQBZmrk = 11147, + X86_VPMOVQBZrr = 11148, + X86_VPMOVQBZrrk = 11149, + X86_VPMOVQBZrrkz = 11150, + X86_VPMOVQDZ128mr = 11151, + X86_VPMOVQDZ128mrk = 11152, + X86_VPMOVQDZ128rr = 11153, + X86_VPMOVQDZ128rrk = 11154, + X86_VPMOVQDZ128rrkz = 11155, + X86_VPMOVQDZ256mr = 11156, + X86_VPMOVQDZ256mrk = 11157, + X86_VPMOVQDZ256rr = 11158, + X86_VPMOVQDZ256rrk = 11159, + X86_VPMOVQDZ256rrkz = 11160, + X86_VPMOVQDZmr = 11161, + X86_VPMOVQDZmrk = 11162, + X86_VPMOVQDZrr = 11163, + X86_VPMOVQDZrrk = 11164, + X86_VPMOVQDZrrkz = 11165, + X86_VPMOVQWZ128mr = 11166, + X86_VPMOVQWZ128mrk = 11167, + X86_VPMOVQWZ128rr = 11168, + X86_VPMOVQWZ128rrk = 11169, + X86_VPMOVQWZ128rrkz = 11170, + X86_VPMOVQWZ256mr = 11171, + X86_VPMOVQWZ256mrk = 11172, + X86_VPMOVQWZ256rr = 11173, + X86_VPMOVQWZ256rrk = 11174, + X86_VPMOVQWZ256rrkz = 11175, + X86_VPMOVQWZmr = 11176, + X86_VPMOVQWZmrk = 11177, + X86_VPMOVQWZrr = 11178, + X86_VPMOVQWZrrk = 11179, + X86_VPMOVQWZrrkz = 11180, + X86_VPMOVSDBZ128mr = 11181, + X86_VPMOVSDBZ128mrk = 11182, + X86_VPMOVSDBZ128rr = 11183, + X86_VPMOVSDBZ128rrk = 11184, + X86_VPMOVSDBZ128rrkz = 11185, + X86_VPMOVSDBZ256mr = 11186, + X86_VPMOVSDBZ256mrk = 11187, + X86_VPMOVSDBZ256rr = 11188, + X86_VPMOVSDBZ256rrk = 11189, + X86_VPMOVSDBZ256rrkz = 11190, + X86_VPMOVSDBZmr = 11191, + X86_VPMOVSDBZmrk = 11192, + X86_VPMOVSDBZrr = 11193, + X86_VPMOVSDBZrrk = 11194, + X86_VPMOVSDBZrrkz = 11195, + X86_VPMOVSDWZ128mr = 11196, + X86_VPMOVSDWZ128mrk = 11197, + X86_VPMOVSDWZ128rr = 11198, + X86_VPMOVSDWZ128rrk = 11199, + X86_VPMOVSDWZ128rrkz = 11200, + X86_VPMOVSDWZ256mr = 11201, + X86_VPMOVSDWZ256mrk = 11202, + X86_VPMOVSDWZ256rr = 11203, + X86_VPMOVSDWZ256rrk = 11204, + X86_VPMOVSDWZ256rrkz = 11205, + X86_VPMOVSDWZmr = 11206, + X86_VPMOVSDWZmrk = 11207, + X86_VPMOVSDWZrr = 11208, + X86_VPMOVSDWZrrk = 11209, + X86_VPMOVSDWZrrkz = 11210, + X86_VPMOVSQBZ128mr = 11211, + X86_VPMOVSQBZ128mrk = 11212, + X86_VPMOVSQBZ128rr = 11213, + X86_VPMOVSQBZ128rrk = 11214, + X86_VPMOVSQBZ128rrkz = 11215, + X86_VPMOVSQBZ256mr = 11216, + X86_VPMOVSQBZ256mrk = 11217, + X86_VPMOVSQBZ256rr = 11218, + X86_VPMOVSQBZ256rrk = 11219, + X86_VPMOVSQBZ256rrkz = 11220, + X86_VPMOVSQBZmr = 11221, + X86_VPMOVSQBZmrk = 11222, + X86_VPMOVSQBZrr = 11223, + X86_VPMOVSQBZrrk = 11224, + X86_VPMOVSQBZrrkz = 11225, + X86_VPMOVSQDZ128mr = 11226, + X86_VPMOVSQDZ128mrk = 11227, + X86_VPMOVSQDZ128rr = 11228, + X86_VPMOVSQDZ128rrk = 11229, + X86_VPMOVSQDZ128rrkz = 11230, + X86_VPMOVSQDZ256mr = 11231, + X86_VPMOVSQDZ256mrk = 11232, + X86_VPMOVSQDZ256rr = 11233, + X86_VPMOVSQDZ256rrk = 11234, + X86_VPMOVSQDZ256rrkz = 11235, + X86_VPMOVSQDZmr = 11236, + X86_VPMOVSQDZmrk = 11237, + X86_VPMOVSQDZrr = 11238, + X86_VPMOVSQDZrrk = 11239, + X86_VPMOVSQDZrrkz = 11240, + X86_VPMOVSQWZ128mr = 11241, + X86_VPMOVSQWZ128mrk = 11242, + X86_VPMOVSQWZ128rr = 11243, + X86_VPMOVSQWZ128rrk = 11244, + X86_VPMOVSQWZ128rrkz = 11245, + X86_VPMOVSQWZ256mr = 11246, + X86_VPMOVSQWZ256mrk = 11247, + X86_VPMOVSQWZ256rr = 11248, + X86_VPMOVSQWZ256rrk = 11249, + X86_VPMOVSQWZ256rrkz = 11250, + X86_VPMOVSQWZmr = 11251, + X86_VPMOVSQWZmrk = 11252, + X86_VPMOVSQWZrr = 11253, + X86_VPMOVSQWZrrk = 11254, + X86_VPMOVSQWZrrkz = 11255, + X86_VPMOVSWBZ128mr = 11256, + X86_VPMOVSWBZ128mrk = 11257, + X86_VPMOVSWBZ128rr = 11258, + X86_VPMOVSWBZ128rrk = 11259, + X86_VPMOVSWBZ128rrkz = 11260, + X86_VPMOVSWBZ256mr = 11261, + X86_VPMOVSWBZ256mrk = 11262, + X86_VPMOVSWBZ256rr = 11263, + X86_VPMOVSWBZ256rrk = 11264, + X86_VPMOVSWBZ256rrkz = 11265, + X86_VPMOVSWBZmr = 11266, + X86_VPMOVSWBZmrk = 11267, + X86_VPMOVSWBZrr = 11268, + X86_VPMOVSWBZrrk = 11269, + X86_VPMOVSWBZrrkz = 11270, + X86_VPMOVSXBDYrm = 11271, + X86_VPMOVSXBDYrr = 11272, + X86_VPMOVSXBDZ128rm = 11273, + X86_VPMOVSXBDZ128rmk = 11274, + X86_VPMOVSXBDZ128rmkz = 11275, + X86_VPMOVSXBDZ128rr = 11276, + X86_VPMOVSXBDZ128rrk = 11277, + X86_VPMOVSXBDZ128rrkz = 11278, + X86_VPMOVSXBDZ256rm = 11279, + X86_VPMOVSXBDZ256rmk = 11280, + X86_VPMOVSXBDZ256rmkz = 11281, + X86_VPMOVSXBDZ256rr = 11282, + X86_VPMOVSXBDZ256rrk = 11283, + X86_VPMOVSXBDZ256rrkz = 11284, + X86_VPMOVSXBDZrm = 11285, + X86_VPMOVSXBDZrmk = 11286, + X86_VPMOVSXBDZrmkz = 11287, + X86_VPMOVSXBDZrr = 11288, + X86_VPMOVSXBDZrrk = 11289, + X86_VPMOVSXBDZrrkz = 11290, + X86_VPMOVSXBDrm = 11291, + X86_VPMOVSXBDrr = 11292, + X86_VPMOVSXBQYrm = 11293, + X86_VPMOVSXBQYrr = 11294, + X86_VPMOVSXBQZ128rm = 11295, + X86_VPMOVSXBQZ128rmk = 11296, + X86_VPMOVSXBQZ128rmkz = 11297, + X86_VPMOVSXBQZ128rr = 11298, + X86_VPMOVSXBQZ128rrk = 11299, + X86_VPMOVSXBQZ128rrkz = 11300, + X86_VPMOVSXBQZ256rm = 11301, + X86_VPMOVSXBQZ256rmk = 11302, + X86_VPMOVSXBQZ256rmkz = 11303, + X86_VPMOVSXBQZ256rr = 11304, + X86_VPMOVSXBQZ256rrk = 11305, + X86_VPMOVSXBQZ256rrkz = 11306, + X86_VPMOVSXBQZrm = 11307, + X86_VPMOVSXBQZrmk = 11308, + X86_VPMOVSXBQZrmkz = 11309, + X86_VPMOVSXBQZrr = 11310, + X86_VPMOVSXBQZrrk = 11311, + X86_VPMOVSXBQZrrkz = 11312, + X86_VPMOVSXBQrm = 11313, + X86_VPMOVSXBQrr = 11314, + X86_VPMOVSXBWYrm = 11315, + X86_VPMOVSXBWYrr = 11316, + X86_VPMOVSXBWZ128rm = 11317, + X86_VPMOVSXBWZ128rmk = 11318, + X86_VPMOVSXBWZ128rmkz = 11319, + X86_VPMOVSXBWZ128rr = 11320, + X86_VPMOVSXBWZ128rrk = 11321, + X86_VPMOVSXBWZ128rrkz = 11322, + X86_VPMOVSXBWZ256rm = 11323, + X86_VPMOVSXBWZ256rmk = 11324, + X86_VPMOVSXBWZ256rmkz = 11325, + X86_VPMOVSXBWZ256rr = 11326, + X86_VPMOVSXBWZ256rrk = 11327, + X86_VPMOVSXBWZ256rrkz = 11328, + X86_VPMOVSXBWZrm = 11329, + X86_VPMOVSXBWZrmk = 11330, + X86_VPMOVSXBWZrmkz = 11331, + X86_VPMOVSXBWZrr = 11332, + X86_VPMOVSXBWZrrk = 11333, + X86_VPMOVSXBWZrrkz = 11334, + X86_VPMOVSXBWrm = 11335, + X86_VPMOVSXBWrr = 11336, + X86_VPMOVSXDQYrm = 11337, + X86_VPMOVSXDQYrr = 11338, + X86_VPMOVSXDQZ128rm = 11339, + X86_VPMOVSXDQZ128rmk = 11340, + X86_VPMOVSXDQZ128rmkz = 11341, + X86_VPMOVSXDQZ128rr = 11342, + X86_VPMOVSXDQZ128rrk = 11343, + X86_VPMOVSXDQZ128rrkz = 11344, + X86_VPMOVSXDQZ256rm = 11345, + X86_VPMOVSXDQZ256rmk = 11346, + X86_VPMOVSXDQZ256rmkz = 11347, + X86_VPMOVSXDQZ256rr = 11348, + X86_VPMOVSXDQZ256rrk = 11349, + X86_VPMOVSXDQZ256rrkz = 11350, + X86_VPMOVSXDQZrm = 11351, + X86_VPMOVSXDQZrmk = 11352, + X86_VPMOVSXDQZrmkz = 11353, + X86_VPMOVSXDQZrr = 11354, + X86_VPMOVSXDQZrrk = 11355, + X86_VPMOVSXDQZrrkz = 11356, + X86_VPMOVSXDQrm = 11357, + X86_VPMOVSXDQrr = 11358, + X86_VPMOVSXWDYrm = 11359, + X86_VPMOVSXWDYrr = 11360, + X86_VPMOVSXWDZ128rm = 11361, + X86_VPMOVSXWDZ128rmk = 11362, + X86_VPMOVSXWDZ128rmkz = 11363, + X86_VPMOVSXWDZ128rr = 11364, + X86_VPMOVSXWDZ128rrk = 11365, + X86_VPMOVSXWDZ128rrkz = 11366, + X86_VPMOVSXWDZ256rm = 11367, + X86_VPMOVSXWDZ256rmk = 11368, + X86_VPMOVSXWDZ256rmkz = 11369, + X86_VPMOVSXWDZ256rr = 11370, + X86_VPMOVSXWDZ256rrk = 11371, + X86_VPMOVSXWDZ256rrkz = 11372, + X86_VPMOVSXWDZrm = 11373, + X86_VPMOVSXWDZrmk = 11374, + X86_VPMOVSXWDZrmkz = 11375, + X86_VPMOVSXWDZrr = 11376, + X86_VPMOVSXWDZrrk = 11377, + X86_VPMOVSXWDZrrkz = 11378, + X86_VPMOVSXWDrm = 11379, + X86_VPMOVSXWDrr = 11380, + X86_VPMOVSXWQYrm = 11381, + X86_VPMOVSXWQYrr = 11382, + X86_VPMOVSXWQZ128rm = 11383, + X86_VPMOVSXWQZ128rmk = 11384, + X86_VPMOVSXWQZ128rmkz = 11385, + X86_VPMOVSXWQZ128rr = 11386, + X86_VPMOVSXWQZ128rrk = 11387, + X86_VPMOVSXWQZ128rrkz = 11388, + X86_VPMOVSXWQZ256rm = 11389, + X86_VPMOVSXWQZ256rmk = 11390, + X86_VPMOVSXWQZ256rmkz = 11391, + X86_VPMOVSXWQZ256rr = 11392, + X86_VPMOVSXWQZ256rrk = 11393, + X86_VPMOVSXWQZ256rrkz = 11394, + X86_VPMOVSXWQZrm = 11395, + X86_VPMOVSXWQZrmk = 11396, + X86_VPMOVSXWQZrmkz = 11397, + X86_VPMOVSXWQZrr = 11398, + X86_VPMOVSXWQZrrk = 11399, + X86_VPMOVSXWQZrrkz = 11400, + X86_VPMOVSXWQrm = 11401, + X86_VPMOVSXWQrr = 11402, + X86_VPMOVUSDBZ128mr = 11403, + X86_VPMOVUSDBZ128mrk = 11404, + X86_VPMOVUSDBZ128rr = 11405, + X86_VPMOVUSDBZ128rrk = 11406, + X86_VPMOVUSDBZ128rrkz = 11407, + X86_VPMOVUSDBZ256mr = 11408, + X86_VPMOVUSDBZ256mrk = 11409, + X86_VPMOVUSDBZ256rr = 11410, + X86_VPMOVUSDBZ256rrk = 11411, + X86_VPMOVUSDBZ256rrkz = 11412, + X86_VPMOVUSDBZmr = 11413, + X86_VPMOVUSDBZmrk = 11414, + X86_VPMOVUSDBZrr = 11415, + X86_VPMOVUSDBZrrk = 11416, + X86_VPMOVUSDBZrrkz = 11417, + X86_VPMOVUSDWZ128mr = 11418, + X86_VPMOVUSDWZ128mrk = 11419, + X86_VPMOVUSDWZ128rr = 11420, + X86_VPMOVUSDWZ128rrk = 11421, + X86_VPMOVUSDWZ128rrkz = 11422, + X86_VPMOVUSDWZ256mr = 11423, + X86_VPMOVUSDWZ256mrk = 11424, + X86_VPMOVUSDWZ256rr = 11425, + X86_VPMOVUSDWZ256rrk = 11426, + X86_VPMOVUSDWZ256rrkz = 11427, + X86_VPMOVUSDWZmr = 11428, + X86_VPMOVUSDWZmrk = 11429, + X86_VPMOVUSDWZrr = 11430, + X86_VPMOVUSDWZrrk = 11431, + X86_VPMOVUSDWZrrkz = 11432, + X86_VPMOVUSQBZ128mr = 11433, + X86_VPMOVUSQBZ128mrk = 11434, + X86_VPMOVUSQBZ128rr = 11435, + X86_VPMOVUSQBZ128rrk = 11436, + X86_VPMOVUSQBZ128rrkz = 11437, + X86_VPMOVUSQBZ256mr = 11438, + X86_VPMOVUSQBZ256mrk = 11439, + X86_VPMOVUSQBZ256rr = 11440, + X86_VPMOVUSQBZ256rrk = 11441, + X86_VPMOVUSQBZ256rrkz = 11442, + X86_VPMOVUSQBZmr = 11443, + X86_VPMOVUSQBZmrk = 11444, + X86_VPMOVUSQBZrr = 11445, + X86_VPMOVUSQBZrrk = 11446, + X86_VPMOVUSQBZrrkz = 11447, + X86_VPMOVUSQDZ128mr = 11448, + X86_VPMOVUSQDZ128mrk = 11449, + X86_VPMOVUSQDZ128rr = 11450, + X86_VPMOVUSQDZ128rrk = 11451, + X86_VPMOVUSQDZ128rrkz = 11452, + X86_VPMOVUSQDZ256mr = 11453, + X86_VPMOVUSQDZ256mrk = 11454, + X86_VPMOVUSQDZ256rr = 11455, + X86_VPMOVUSQDZ256rrk = 11456, + X86_VPMOVUSQDZ256rrkz = 11457, + X86_VPMOVUSQDZmr = 11458, + X86_VPMOVUSQDZmrk = 11459, + X86_VPMOVUSQDZrr = 11460, + X86_VPMOVUSQDZrrk = 11461, + X86_VPMOVUSQDZrrkz = 11462, + X86_VPMOVUSQWZ128mr = 11463, + X86_VPMOVUSQWZ128mrk = 11464, + X86_VPMOVUSQWZ128rr = 11465, + X86_VPMOVUSQWZ128rrk = 11466, + X86_VPMOVUSQWZ128rrkz = 11467, + X86_VPMOVUSQWZ256mr = 11468, + X86_VPMOVUSQWZ256mrk = 11469, + X86_VPMOVUSQWZ256rr = 11470, + X86_VPMOVUSQWZ256rrk = 11471, + X86_VPMOVUSQWZ256rrkz = 11472, + X86_VPMOVUSQWZmr = 11473, + X86_VPMOVUSQWZmrk = 11474, + X86_VPMOVUSQWZrr = 11475, + X86_VPMOVUSQWZrrk = 11476, + X86_VPMOVUSQWZrrkz = 11477, + X86_VPMOVUSWBZ128mr = 11478, + X86_VPMOVUSWBZ128mrk = 11479, + X86_VPMOVUSWBZ128rr = 11480, + X86_VPMOVUSWBZ128rrk = 11481, + X86_VPMOVUSWBZ128rrkz = 11482, + X86_VPMOVUSWBZ256mr = 11483, + X86_VPMOVUSWBZ256mrk = 11484, + X86_VPMOVUSWBZ256rr = 11485, + X86_VPMOVUSWBZ256rrk = 11486, + X86_VPMOVUSWBZ256rrkz = 11487, + X86_VPMOVUSWBZmr = 11488, + X86_VPMOVUSWBZmrk = 11489, + X86_VPMOVUSWBZrr = 11490, + X86_VPMOVUSWBZrrk = 11491, + X86_VPMOVUSWBZrrkz = 11492, + X86_VPMOVW2MZ128rr = 11493, + X86_VPMOVW2MZ256rr = 11494, + X86_VPMOVW2MZrr = 11495, + X86_VPMOVWBZ128mr = 11496, + X86_VPMOVWBZ128mrk = 11497, + X86_VPMOVWBZ128rr = 11498, + X86_VPMOVWBZ128rrk = 11499, + X86_VPMOVWBZ128rrkz = 11500, + X86_VPMOVWBZ256mr = 11501, + X86_VPMOVWBZ256mrk = 11502, + X86_VPMOVWBZ256rr = 11503, + X86_VPMOVWBZ256rrk = 11504, + X86_VPMOVWBZ256rrkz = 11505, + X86_VPMOVWBZmr = 11506, + X86_VPMOVWBZmrk = 11507, + X86_VPMOVWBZrr = 11508, + X86_VPMOVWBZrrk = 11509, + X86_VPMOVWBZrrkz = 11510, + X86_VPMOVZXBDYrm = 11511, + X86_VPMOVZXBDYrr = 11512, + X86_VPMOVZXBDZ128rm = 11513, + X86_VPMOVZXBDZ128rmk = 11514, + X86_VPMOVZXBDZ128rmkz = 11515, + X86_VPMOVZXBDZ128rr = 11516, + X86_VPMOVZXBDZ128rrk = 11517, + X86_VPMOVZXBDZ128rrkz = 11518, + X86_VPMOVZXBDZ256rm = 11519, + X86_VPMOVZXBDZ256rmk = 11520, + X86_VPMOVZXBDZ256rmkz = 11521, + X86_VPMOVZXBDZ256rr = 11522, + X86_VPMOVZXBDZ256rrk = 11523, + X86_VPMOVZXBDZ256rrkz = 11524, + X86_VPMOVZXBDZrm = 11525, + X86_VPMOVZXBDZrmk = 11526, + X86_VPMOVZXBDZrmkz = 11527, + X86_VPMOVZXBDZrr = 11528, + X86_VPMOVZXBDZrrk = 11529, + X86_VPMOVZXBDZrrkz = 11530, + X86_VPMOVZXBDrm = 11531, + X86_VPMOVZXBDrr = 11532, + X86_VPMOVZXBQYrm = 11533, + X86_VPMOVZXBQYrr = 11534, + X86_VPMOVZXBQZ128rm = 11535, + X86_VPMOVZXBQZ128rmk = 11536, + X86_VPMOVZXBQZ128rmkz = 11537, + X86_VPMOVZXBQZ128rr = 11538, + X86_VPMOVZXBQZ128rrk = 11539, + X86_VPMOVZXBQZ128rrkz = 11540, + X86_VPMOVZXBQZ256rm = 11541, + X86_VPMOVZXBQZ256rmk = 11542, + X86_VPMOVZXBQZ256rmkz = 11543, + X86_VPMOVZXBQZ256rr = 11544, + X86_VPMOVZXBQZ256rrk = 11545, + X86_VPMOVZXBQZ256rrkz = 11546, + X86_VPMOVZXBQZrm = 11547, + X86_VPMOVZXBQZrmk = 11548, + X86_VPMOVZXBQZrmkz = 11549, + X86_VPMOVZXBQZrr = 11550, + X86_VPMOVZXBQZrrk = 11551, + X86_VPMOVZXBQZrrkz = 11552, + X86_VPMOVZXBQrm = 11553, + X86_VPMOVZXBQrr = 11554, + X86_VPMOVZXBWYrm = 11555, + X86_VPMOVZXBWYrr = 11556, + X86_VPMOVZXBWZ128rm = 11557, + X86_VPMOVZXBWZ128rmk = 11558, + X86_VPMOVZXBWZ128rmkz = 11559, + X86_VPMOVZXBWZ128rr = 11560, + X86_VPMOVZXBWZ128rrk = 11561, + X86_VPMOVZXBWZ128rrkz = 11562, + X86_VPMOVZXBWZ256rm = 11563, + X86_VPMOVZXBWZ256rmk = 11564, + X86_VPMOVZXBWZ256rmkz = 11565, + X86_VPMOVZXBWZ256rr = 11566, + X86_VPMOVZXBWZ256rrk = 11567, + X86_VPMOVZXBWZ256rrkz = 11568, + X86_VPMOVZXBWZrm = 11569, + X86_VPMOVZXBWZrmk = 11570, + X86_VPMOVZXBWZrmkz = 11571, + X86_VPMOVZXBWZrr = 11572, + X86_VPMOVZXBWZrrk = 11573, + X86_VPMOVZXBWZrrkz = 11574, + X86_VPMOVZXBWrm = 11575, + X86_VPMOVZXBWrr = 11576, + X86_VPMOVZXDQYrm = 11577, + X86_VPMOVZXDQYrr = 11578, + X86_VPMOVZXDQZ128rm = 11579, + X86_VPMOVZXDQZ128rmk = 11580, + X86_VPMOVZXDQZ128rmkz = 11581, + X86_VPMOVZXDQZ128rr = 11582, + X86_VPMOVZXDQZ128rrk = 11583, + X86_VPMOVZXDQZ128rrkz = 11584, + X86_VPMOVZXDQZ256rm = 11585, + X86_VPMOVZXDQZ256rmk = 11586, + X86_VPMOVZXDQZ256rmkz = 11587, + X86_VPMOVZXDQZ256rr = 11588, + X86_VPMOVZXDQZ256rrk = 11589, + X86_VPMOVZXDQZ256rrkz = 11590, + X86_VPMOVZXDQZrm = 11591, + X86_VPMOVZXDQZrmk = 11592, + X86_VPMOVZXDQZrmkz = 11593, + X86_VPMOVZXDQZrr = 11594, + X86_VPMOVZXDQZrrk = 11595, + X86_VPMOVZXDQZrrkz = 11596, + X86_VPMOVZXDQrm = 11597, + X86_VPMOVZXDQrr = 11598, + X86_VPMOVZXWDYrm = 11599, + X86_VPMOVZXWDYrr = 11600, + X86_VPMOVZXWDZ128rm = 11601, + X86_VPMOVZXWDZ128rmk = 11602, + X86_VPMOVZXWDZ128rmkz = 11603, + X86_VPMOVZXWDZ128rr = 11604, + X86_VPMOVZXWDZ128rrk = 11605, + X86_VPMOVZXWDZ128rrkz = 11606, + X86_VPMOVZXWDZ256rm = 11607, + X86_VPMOVZXWDZ256rmk = 11608, + X86_VPMOVZXWDZ256rmkz = 11609, + X86_VPMOVZXWDZ256rr = 11610, + X86_VPMOVZXWDZ256rrk = 11611, + X86_VPMOVZXWDZ256rrkz = 11612, + X86_VPMOVZXWDZrm = 11613, + X86_VPMOVZXWDZrmk = 11614, + X86_VPMOVZXWDZrmkz = 11615, + X86_VPMOVZXWDZrr = 11616, + X86_VPMOVZXWDZrrk = 11617, + X86_VPMOVZXWDZrrkz = 11618, + X86_VPMOVZXWDrm = 11619, + X86_VPMOVZXWDrr = 11620, + X86_VPMOVZXWQYrm = 11621, + X86_VPMOVZXWQYrr = 11622, + X86_VPMOVZXWQZ128rm = 11623, + X86_VPMOVZXWQZ128rmk = 11624, + X86_VPMOVZXWQZ128rmkz = 11625, + X86_VPMOVZXWQZ128rr = 11626, + X86_VPMOVZXWQZ128rrk = 11627, + X86_VPMOVZXWQZ128rrkz = 11628, + X86_VPMOVZXWQZ256rm = 11629, + X86_VPMOVZXWQZ256rmk = 11630, + X86_VPMOVZXWQZ256rmkz = 11631, + X86_VPMOVZXWQZ256rr = 11632, + X86_VPMOVZXWQZ256rrk = 11633, + X86_VPMOVZXWQZ256rrkz = 11634, + X86_VPMOVZXWQZrm = 11635, + X86_VPMOVZXWQZrmk = 11636, + X86_VPMOVZXWQZrmkz = 11637, + X86_VPMOVZXWQZrr = 11638, + X86_VPMOVZXWQZrrk = 11639, + X86_VPMOVZXWQZrrkz = 11640, + X86_VPMOVZXWQrm = 11641, + X86_VPMOVZXWQrr = 11642, + X86_VPMULDQYrm = 11643, + X86_VPMULDQYrr = 11644, + X86_VPMULDQZ128rm = 11645, + X86_VPMULDQZ128rmb = 11646, + X86_VPMULDQZ128rmbk = 11647, + X86_VPMULDQZ128rmbkz = 11648, + X86_VPMULDQZ128rmk = 11649, + X86_VPMULDQZ128rmkz = 11650, + X86_VPMULDQZ128rr = 11651, + X86_VPMULDQZ128rrk = 11652, + X86_VPMULDQZ128rrkz = 11653, + X86_VPMULDQZ256rm = 11654, + X86_VPMULDQZ256rmb = 11655, + X86_VPMULDQZ256rmbk = 11656, + X86_VPMULDQZ256rmbkz = 11657, + X86_VPMULDQZ256rmk = 11658, + X86_VPMULDQZ256rmkz = 11659, + X86_VPMULDQZ256rr = 11660, + X86_VPMULDQZ256rrk = 11661, + X86_VPMULDQZ256rrkz = 11662, + X86_VPMULDQZrm = 11663, + X86_VPMULDQZrmb = 11664, + X86_VPMULDQZrmbk = 11665, + X86_VPMULDQZrmbkz = 11666, + X86_VPMULDQZrmk = 11667, + X86_VPMULDQZrmkz = 11668, + X86_VPMULDQZrr = 11669, + X86_VPMULDQZrrk = 11670, + X86_VPMULDQZrrkz = 11671, + X86_VPMULDQrm = 11672, + X86_VPMULDQrr = 11673, + X86_VPMULHRSWYrm = 11674, + X86_VPMULHRSWYrr = 11675, + X86_VPMULHRSWZ128rm = 11676, + X86_VPMULHRSWZ128rmk = 11677, + X86_VPMULHRSWZ128rmkz = 11678, + X86_VPMULHRSWZ128rr = 11679, + X86_VPMULHRSWZ128rrk = 11680, + X86_VPMULHRSWZ128rrkz = 11681, + X86_VPMULHRSWZ256rm = 11682, + X86_VPMULHRSWZ256rmk = 11683, + X86_VPMULHRSWZ256rmkz = 11684, + X86_VPMULHRSWZ256rr = 11685, + X86_VPMULHRSWZ256rrk = 11686, + X86_VPMULHRSWZ256rrkz = 11687, + X86_VPMULHRSWZrm = 11688, + X86_VPMULHRSWZrmk = 11689, + X86_VPMULHRSWZrmkz = 11690, + X86_VPMULHRSWZrr = 11691, + X86_VPMULHRSWZrrk = 11692, + X86_VPMULHRSWZrrkz = 11693, + X86_VPMULHRSWrm = 11694, + X86_VPMULHRSWrr = 11695, + X86_VPMULHUWYrm = 11696, + X86_VPMULHUWYrr = 11697, + X86_VPMULHUWZ128rm = 11698, + X86_VPMULHUWZ128rmk = 11699, + X86_VPMULHUWZ128rmkz = 11700, + X86_VPMULHUWZ128rr = 11701, + X86_VPMULHUWZ128rrk = 11702, + X86_VPMULHUWZ128rrkz = 11703, + X86_VPMULHUWZ256rm = 11704, + X86_VPMULHUWZ256rmk = 11705, + X86_VPMULHUWZ256rmkz = 11706, + X86_VPMULHUWZ256rr = 11707, + X86_VPMULHUWZ256rrk = 11708, + X86_VPMULHUWZ256rrkz = 11709, + X86_VPMULHUWZrm = 11710, + X86_VPMULHUWZrmk = 11711, + X86_VPMULHUWZrmkz = 11712, + X86_VPMULHUWZrr = 11713, + X86_VPMULHUWZrrk = 11714, + X86_VPMULHUWZrrkz = 11715, + X86_VPMULHUWrm = 11716, + X86_VPMULHUWrr = 11717, + X86_VPMULHWYrm = 11718, + X86_VPMULHWYrr = 11719, + X86_VPMULHWZ128rm = 11720, + X86_VPMULHWZ128rmk = 11721, + X86_VPMULHWZ128rmkz = 11722, + X86_VPMULHWZ128rr = 11723, + X86_VPMULHWZ128rrk = 11724, + X86_VPMULHWZ128rrkz = 11725, + X86_VPMULHWZ256rm = 11726, + X86_VPMULHWZ256rmk = 11727, + X86_VPMULHWZ256rmkz = 11728, + X86_VPMULHWZ256rr = 11729, + X86_VPMULHWZ256rrk = 11730, + X86_VPMULHWZ256rrkz = 11731, + X86_VPMULHWZrm = 11732, + X86_VPMULHWZrmk = 11733, + X86_VPMULHWZrmkz = 11734, + X86_VPMULHWZrr = 11735, + X86_VPMULHWZrrk = 11736, + X86_VPMULHWZrrkz = 11737, + X86_VPMULHWrm = 11738, + X86_VPMULHWrr = 11739, + X86_VPMULLDYrm = 11740, + X86_VPMULLDYrr = 11741, + X86_VPMULLDZ128rm = 11742, + X86_VPMULLDZ128rmb = 11743, + X86_VPMULLDZ128rmbk = 11744, + X86_VPMULLDZ128rmbkz = 11745, + X86_VPMULLDZ128rmk = 11746, + X86_VPMULLDZ128rmkz = 11747, + X86_VPMULLDZ128rr = 11748, + X86_VPMULLDZ128rrk = 11749, + X86_VPMULLDZ128rrkz = 11750, + X86_VPMULLDZ256rm = 11751, + X86_VPMULLDZ256rmb = 11752, + X86_VPMULLDZ256rmbk = 11753, + X86_VPMULLDZ256rmbkz = 11754, + X86_VPMULLDZ256rmk = 11755, + X86_VPMULLDZ256rmkz = 11756, + X86_VPMULLDZ256rr = 11757, + X86_VPMULLDZ256rrk = 11758, + X86_VPMULLDZ256rrkz = 11759, + X86_VPMULLDZrm = 11760, + X86_VPMULLDZrmb = 11761, + X86_VPMULLDZrmbk = 11762, + X86_VPMULLDZrmbkz = 11763, + X86_VPMULLDZrmk = 11764, + X86_VPMULLDZrmkz = 11765, + X86_VPMULLDZrr = 11766, + X86_VPMULLDZrrk = 11767, + X86_VPMULLDZrrkz = 11768, + X86_VPMULLDrm = 11769, + X86_VPMULLDrr = 11770, + X86_VPMULLQZ128rm = 11771, + X86_VPMULLQZ128rmb = 11772, + X86_VPMULLQZ128rmbk = 11773, + X86_VPMULLQZ128rmbkz = 11774, + X86_VPMULLQZ128rmk = 11775, + X86_VPMULLQZ128rmkz = 11776, + X86_VPMULLQZ128rr = 11777, + X86_VPMULLQZ128rrk = 11778, + X86_VPMULLQZ128rrkz = 11779, + X86_VPMULLQZ256rm = 11780, + X86_VPMULLQZ256rmb = 11781, + X86_VPMULLQZ256rmbk = 11782, + X86_VPMULLQZ256rmbkz = 11783, + X86_VPMULLQZ256rmk = 11784, + X86_VPMULLQZ256rmkz = 11785, + X86_VPMULLQZ256rr = 11786, + X86_VPMULLQZ256rrk = 11787, + X86_VPMULLQZ256rrkz = 11788, + X86_VPMULLQZrm = 11789, + X86_VPMULLQZrmb = 11790, + X86_VPMULLQZrmbk = 11791, + X86_VPMULLQZrmbkz = 11792, + X86_VPMULLQZrmk = 11793, + X86_VPMULLQZrmkz = 11794, + X86_VPMULLQZrr = 11795, + X86_VPMULLQZrrk = 11796, + X86_VPMULLQZrrkz = 11797, + X86_VPMULLWYrm = 11798, + X86_VPMULLWYrr = 11799, + X86_VPMULLWZ128rm = 11800, + X86_VPMULLWZ128rmk = 11801, + X86_VPMULLWZ128rmkz = 11802, + X86_VPMULLWZ128rr = 11803, + X86_VPMULLWZ128rrk = 11804, + X86_VPMULLWZ128rrkz = 11805, + X86_VPMULLWZ256rm = 11806, + X86_VPMULLWZ256rmk = 11807, + X86_VPMULLWZ256rmkz = 11808, + X86_VPMULLWZ256rr = 11809, + X86_VPMULLWZ256rrk = 11810, + X86_VPMULLWZ256rrkz = 11811, + X86_VPMULLWZrm = 11812, + X86_VPMULLWZrmk = 11813, + X86_VPMULLWZrmkz = 11814, + X86_VPMULLWZrr = 11815, + X86_VPMULLWZrrk = 11816, + X86_VPMULLWZrrkz = 11817, + X86_VPMULLWrm = 11818, + X86_VPMULLWrr = 11819, + X86_VPMULTISHIFTQBZ128rm = 11820, + X86_VPMULTISHIFTQBZ128rmb = 11821, + X86_VPMULTISHIFTQBZ128rmbk = 11822, + X86_VPMULTISHIFTQBZ128rmbkz = 11823, + X86_VPMULTISHIFTQBZ128rmk = 11824, + X86_VPMULTISHIFTQBZ128rmkz = 11825, + X86_VPMULTISHIFTQBZ128rr = 11826, + X86_VPMULTISHIFTQBZ128rrk = 11827, + X86_VPMULTISHIFTQBZ128rrkz = 11828, + X86_VPMULTISHIFTQBZ256rm = 11829, + X86_VPMULTISHIFTQBZ256rmb = 11830, + X86_VPMULTISHIFTQBZ256rmbk = 11831, + X86_VPMULTISHIFTQBZ256rmbkz = 11832, + X86_VPMULTISHIFTQBZ256rmk = 11833, + X86_VPMULTISHIFTQBZ256rmkz = 11834, + X86_VPMULTISHIFTQBZ256rr = 11835, + X86_VPMULTISHIFTQBZ256rrk = 11836, + X86_VPMULTISHIFTQBZ256rrkz = 11837, + X86_VPMULTISHIFTQBZrm = 11838, + X86_VPMULTISHIFTQBZrmb = 11839, + X86_VPMULTISHIFTQBZrmbk = 11840, + X86_VPMULTISHIFTQBZrmbkz = 11841, + X86_VPMULTISHIFTQBZrmk = 11842, + X86_VPMULTISHIFTQBZrmkz = 11843, + X86_VPMULTISHIFTQBZrr = 11844, + X86_VPMULTISHIFTQBZrrk = 11845, + X86_VPMULTISHIFTQBZrrkz = 11846, + X86_VPMULUDQYrm = 11847, + X86_VPMULUDQYrr = 11848, + X86_VPMULUDQZ128rm = 11849, + X86_VPMULUDQZ128rmb = 11850, + X86_VPMULUDQZ128rmbk = 11851, + X86_VPMULUDQZ128rmbkz = 11852, + X86_VPMULUDQZ128rmk = 11853, + X86_VPMULUDQZ128rmkz = 11854, + X86_VPMULUDQZ128rr = 11855, + X86_VPMULUDQZ128rrk = 11856, + X86_VPMULUDQZ128rrkz = 11857, + X86_VPMULUDQZ256rm = 11858, + X86_VPMULUDQZ256rmb = 11859, + X86_VPMULUDQZ256rmbk = 11860, + X86_VPMULUDQZ256rmbkz = 11861, + X86_VPMULUDQZ256rmk = 11862, + X86_VPMULUDQZ256rmkz = 11863, + X86_VPMULUDQZ256rr = 11864, + X86_VPMULUDQZ256rrk = 11865, + X86_VPMULUDQZ256rrkz = 11866, + X86_VPMULUDQZrm = 11867, + X86_VPMULUDQZrmb = 11868, + X86_VPMULUDQZrmbk = 11869, + X86_VPMULUDQZrmbkz = 11870, + X86_VPMULUDQZrmk = 11871, + X86_VPMULUDQZrmkz = 11872, + X86_VPMULUDQZrr = 11873, + X86_VPMULUDQZrrk = 11874, + X86_VPMULUDQZrrkz = 11875, + X86_VPMULUDQrm = 11876, + X86_VPMULUDQrr = 11877, + X86_VPOPCNTBZ128rm = 11878, + X86_VPOPCNTBZ128rmk = 11879, + X86_VPOPCNTBZ128rmkz = 11880, + X86_VPOPCNTBZ128rr = 11881, + X86_VPOPCNTBZ128rrk = 11882, + X86_VPOPCNTBZ128rrkz = 11883, + X86_VPOPCNTBZ256rm = 11884, + X86_VPOPCNTBZ256rmk = 11885, + X86_VPOPCNTBZ256rmkz = 11886, + X86_VPOPCNTBZ256rr = 11887, + X86_VPOPCNTBZ256rrk = 11888, + X86_VPOPCNTBZ256rrkz = 11889, + X86_VPOPCNTBZrm = 11890, + X86_VPOPCNTBZrmk = 11891, + X86_VPOPCNTBZrmkz = 11892, + X86_VPOPCNTBZrr = 11893, + X86_VPOPCNTBZrrk = 11894, + X86_VPOPCNTBZrrkz = 11895, + X86_VPOPCNTDZ128rm = 11896, + X86_VPOPCNTDZ128rmb = 11897, + X86_VPOPCNTDZ128rmbk = 11898, + X86_VPOPCNTDZ128rmbkz = 11899, + X86_VPOPCNTDZ128rmk = 11900, + X86_VPOPCNTDZ128rmkz = 11901, + X86_VPOPCNTDZ128rr = 11902, + X86_VPOPCNTDZ128rrk = 11903, + X86_VPOPCNTDZ128rrkz = 11904, + X86_VPOPCNTDZ256rm = 11905, + X86_VPOPCNTDZ256rmb = 11906, + X86_VPOPCNTDZ256rmbk = 11907, + X86_VPOPCNTDZ256rmbkz = 11908, + X86_VPOPCNTDZ256rmk = 11909, + X86_VPOPCNTDZ256rmkz = 11910, + X86_VPOPCNTDZ256rr = 11911, + X86_VPOPCNTDZ256rrk = 11912, + X86_VPOPCNTDZ256rrkz = 11913, + X86_VPOPCNTDZrm = 11914, + X86_VPOPCNTDZrmb = 11915, + X86_VPOPCNTDZrmbk = 11916, + X86_VPOPCNTDZrmbkz = 11917, + X86_VPOPCNTDZrmk = 11918, + X86_VPOPCNTDZrmkz = 11919, + X86_VPOPCNTDZrr = 11920, + X86_VPOPCNTDZrrk = 11921, + X86_VPOPCNTDZrrkz = 11922, + X86_VPOPCNTQZ128rm = 11923, + X86_VPOPCNTQZ128rmb = 11924, + X86_VPOPCNTQZ128rmbk = 11925, + X86_VPOPCNTQZ128rmbkz = 11926, + X86_VPOPCNTQZ128rmk = 11927, + X86_VPOPCNTQZ128rmkz = 11928, + X86_VPOPCNTQZ128rr = 11929, + X86_VPOPCNTQZ128rrk = 11930, + X86_VPOPCNTQZ128rrkz = 11931, + X86_VPOPCNTQZ256rm = 11932, + X86_VPOPCNTQZ256rmb = 11933, + X86_VPOPCNTQZ256rmbk = 11934, + X86_VPOPCNTQZ256rmbkz = 11935, + X86_VPOPCNTQZ256rmk = 11936, + X86_VPOPCNTQZ256rmkz = 11937, + X86_VPOPCNTQZ256rr = 11938, + X86_VPOPCNTQZ256rrk = 11939, + X86_VPOPCNTQZ256rrkz = 11940, + X86_VPOPCNTQZrm = 11941, + X86_VPOPCNTQZrmb = 11942, + X86_VPOPCNTQZrmbk = 11943, + X86_VPOPCNTQZrmbkz = 11944, + X86_VPOPCNTQZrmk = 11945, + X86_VPOPCNTQZrmkz = 11946, + X86_VPOPCNTQZrr = 11947, + X86_VPOPCNTQZrrk = 11948, + X86_VPOPCNTQZrrkz = 11949, + X86_VPOPCNTWZ128rm = 11950, + X86_VPOPCNTWZ128rmk = 11951, + X86_VPOPCNTWZ128rmkz = 11952, + X86_VPOPCNTWZ128rr = 11953, + X86_VPOPCNTWZ128rrk = 11954, + X86_VPOPCNTWZ128rrkz = 11955, + X86_VPOPCNTWZ256rm = 11956, + X86_VPOPCNTWZ256rmk = 11957, + X86_VPOPCNTWZ256rmkz = 11958, + X86_VPOPCNTWZ256rr = 11959, + X86_VPOPCNTWZ256rrk = 11960, + X86_VPOPCNTWZ256rrkz = 11961, + X86_VPOPCNTWZrm = 11962, + X86_VPOPCNTWZrmk = 11963, + X86_VPOPCNTWZrmkz = 11964, + X86_VPOPCNTWZrr = 11965, + X86_VPOPCNTWZrrk = 11966, + X86_VPOPCNTWZrrkz = 11967, + X86_VPORDZ128rm = 11968, + X86_VPORDZ128rmb = 11969, + X86_VPORDZ128rmbk = 11970, + X86_VPORDZ128rmbkz = 11971, + X86_VPORDZ128rmk = 11972, + X86_VPORDZ128rmkz = 11973, + X86_VPORDZ128rr = 11974, + X86_VPORDZ128rrk = 11975, + X86_VPORDZ128rrkz = 11976, + X86_VPORDZ256rm = 11977, + X86_VPORDZ256rmb = 11978, + X86_VPORDZ256rmbk = 11979, + X86_VPORDZ256rmbkz = 11980, + X86_VPORDZ256rmk = 11981, + X86_VPORDZ256rmkz = 11982, + X86_VPORDZ256rr = 11983, + X86_VPORDZ256rrk = 11984, + X86_VPORDZ256rrkz = 11985, + X86_VPORDZrm = 11986, + X86_VPORDZrmb = 11987, + X86_VPORDZrmbk = 11988, + X86_VPORDZrmbkz = 11989, + X86_VPORDZrmk = 11990, + X86_VPORDZrmkz = 11991, + X86_VPORDZrr = 11992, + X86_VPORDZrrk = 11993, + X86_VPORDZrrkz = 11994, + X86_VPORQZ128rm = 11995, + X86_VPORQZ128rmb = 11996, + X86_VPORQZ128rmbk = 11997, + X86_VPORQZ128rmbkz = 11998, + X86_VPORQZ128rmk = 11999, + X86_VPORQZ128rmkz = 12000, + X86_VPORQZ128rr = 12001, + X86_VPORQZ128rrk = 12002, + X86_VPORQZ128rrkz = 12003, + X86_VPORQZ256rm = 12004, + X86_VPORQZ256rmb = 12005, + X86_VPORQZ256rmbk = 12006, + X86_VPORQZ256rmbkz = 12007, + X86_VPORQZ256rmk = 12008, + X86_VPORQZ256rmkz = 12009, + X86_VPORQZ256rr = 12010, + X86_VPORQZ256rrk = 12011, + X86_VPORQZ256rrkz = 12012, + X86_VPORQZrm = 12013, + X86_VPORQZrmb = 12014, + X86_VPORQZrmbk = 12015, + X86_VPORQZrmbkz = 12016, + X86_VPORQZrmk = 12017, + X86_VPORQZrmkz = 12018, + X86_VPORQZrr = 12019, + X86_VPORQZrrk = 12020, + X86_VPORQZrrkz = 12021, + X86_VPORYrm = 12022, + X86_VPORYrr = 12023, + X86_VPORrm = 12024, + X86_VPORrr = 12025, + X86_VPPERMrmr = 12026, + X86_VPPERMrrm = 12027, + X86_VPPERMrrr = 12028, + X86_VPPERMrrr_REV = 12029, + X86_VPROLDZ128mbi = 12030, + X86_VPROLDZ128mbik = 12031, + X86_VPROLDZ128mbikz = 12032, + X86_VPROLDZ128mi = 12033, + X86_VPROLDZ128mik = 12034, + X86_VPROLDZ128mikz = 12035, + X86_VPROLDZ128ri = 12036, + X86_VPROLDZ128rik = 12037, + X86_VPROLDZ128rikz = 12038, + X86_VPROLDZ256mbi = 12039, + X86_VPROLDZ256mbik = 12040, + X86_VPROLDZ256mbikz = 12041, + X86_VPROLDZ256mi = 12042, + X86_VPROLDZ256mik = 12043, + X86_VPROLDZ256mikz = 12044, + X86_VPROLDZ256ri = 12045, + X86_VPROLDZ256rik = 12046, + X86_VPROLDZ256rikz = 12047, + X86_VPROLDZmbi = 12048, + X86_VPROLDZmbik = 12049, + X86_VPROLDZmbikz = 12050, + X86_VPROLDZmi = 12051, + X86_VPROLDZmik = 12052, + X86_VPROLDZmikz = 12053, + X86_VPROLDZri = 12054, + X86_VPROLDZrik = 12055, + X86_VPROLDZrikz = 12056, + X86_VPROLQZ128mbi = 12057, + X86_VPROLQZ128mbik = 12058, + X86_VPROLQZ128mbikz = 12059, + X86_VPROLQZ128mi = 12060, + X86_VPROLQZ128mik = 12061, + X86_VPROLQZ128mikz = 12062, + X86_VPROLQZ128ri = 12063, + X86_VPROLQZ128rik = 12064, + X86_VPROLQZ128rikz = 12065, + X86_VPROLQZ256mbi = 12066, + X86_VPROLQZ256mbik = 12067, + X86_VPROLQZ256mbikz = 12068, + X86_VPROLQZ256mi = 12069, + X86_VPROLQZ256mik = 12070, + X86_VPROLQZ256mikz = 12071, + X86_VPROLQZ256ri = 12072, + X86_VPROLQZ256rik = 12073, + X86_VPROLQZ256rikz = 12074, + X86_VPROLQZmbi = 12075, + X86_VPROLQZmbik = 12076, + X86_VPROLQZmbikz = 12077, + X86_VPROLQZmi = 12078, + X86_VPROLQZmik = 12079, + X86_VPROLQZmikz = 12080, + X86_VPROLQZri = 12081, + X86_VPROLQZrik = 12082, + X86_VPROLQZrikz = 12083, + X86_VPROLVDZ128rm = 12084, + X86_VPROLVDZ128rmb = 12085, + X86_VPROLVDZ128rmbk = 12086, + X86_VPROLVDZ128rmbkz = 12087, + X86_VPROLVDZ128rmk = 12088, + X86_VPROLVDZ128rmkz = 12089, + X86_VPROLVDZ128rr = 12090, + X86_VPROLVDZ128rrk = 12091, + X86_VPROLVDZ128rrkz = 12092, + X86_VPROLVDZ256rm = 12093, + X86_VPROLVDZ256rmb = 12094, + X86_VPROLVDZ256rmbk = 12095, + X86_VPROLVDZ256rmbkz = 12096, + X86_VPROLVDZ256rmk = 12097, + X86_VPROLVDZ256rmkz = 12098, + X86_VPROLVDZ256rr = 12099, + X86_VPROLVDZ256rrk = 12100, + X86_VPROLVDZ256rrkz = 12101, + X86_VPROLVDZrm = 12102, + X86_VPROLVDZrmb = 12103, + X86_VPROLVDZrmbk = 12104, + X86_VPROLVDZrmbkz = 12105, + X86_VPROLVDZrmk = 12106, + X86_VPROLVDZrmkz = 12107, + X86_VPROLVDZrr = 12108, + X86_VPROLVDZrrk = 12109, + X86_VPROLVDZrrkz = 12110, + X86_VPROLVQZ128rm = 12111, + X86_VPROLVQZ128rmb = 12112, + X86_VPROLVQZ128rmbk = 12113, + X86_VPROLVQZ128rmbkz = 12114, + X86_VPROLVQZ128rmk = 12115, + X86_VPROLVQZ128rmkz = 12116, + X86_VPROLVQZ128rr = 12117, + X86_VPROLVQZ128rrk = 12118, + X86_VPROLVQZ128rrkz = 12119, + X86_VPROLVQZ256rm = 12120, + X86_VPROLVQZ256rmb = 12121, + X86_VPROLVQZ256rmbk = 12122, + X86_VPROLVQZ256rmbkz = 12123, + X86_VPROLVQZ256rmk = 12124, + X86_VPROLVQZ256rmkz = 12125, + X86_VPROLVQZ256rr = 12126, + X86_VPROLVQZ256rrk = 12127, + X86_VPROLVQZ256rrkz = 12128, + X86_VPROLVQZrm = 12129, + X86_VPROLVQZrmb = 12130, + X86_VPROLVQZrmbk = 12131, + X86_VPROLVQZrmbkz = 12132, + X86_VPROLVQZrmk = 12133, + X86_VPROLVQZrmkz = 12134, + X86_VPROLVQZrr = 12135, + X86_VPROLVQZrrk = 12136, + X86_VPROLVQZrrkz = 12137, + X86_VPRORDZ128mbi = 12138, + X86_VPRORDZ128mbik = 12139, + X86_VPRORDZ128mbikz = 12140, + X86_VPRORDZ128mi = 12141, + X86_VPRORDZ128mik = 12142, + X86_VPRORDZ128mikz = 12143, + X86_VPRORDZ128ri = 12144, + X86_VPRORDZ128rik = 12145, + X86_VPRORDZ128rikz = 12146, + X86_VPRORDZ256mbi = 12147, + X86_VPRORDZ256mbik = 12148, + X86_VPRORDZ256mbikz = 12149, + X86_VPRORDZ256mi = 12150, + X86_VPRORDZ256mik = 12151, + X86_VPRORDZ256mikz = 12152, + X86_VPRORDZ256ri = 12153, + X86_VPRORDZ256rik = 12154, + X86_VPRORDZ256rikz = 12155, + X86_VPRORDZmbi = 12156, + X86_VPRORDZmbik = 12157, + X86_VPRORDZmbikz = 12158, + X86_VPRORDZmi = 12159, + X86_VPRORDZmik = 12160, + X86_VPRORDZmikz = 12161, + X86_VPRORDZri = 12162, + X86_VPRORDZrik = 12163, + X86_VPRORDZrikz = 12164, + X86_VPRORQZ128mbi = 12165, + X86_VPRORQZ128mbik = 12166, + X86_VPRORQZ128mbikz = 12167, + X86_VPRORQZ128mi = 12168, + X86_VPRORQZ128mik = 12169, + X86_VPRORQZ128mikz = 12170, + X86_VPRORQZ128ri = 12171, + X86_VPRORQZ128rik = 12172, + X86_VPRORQZ128rikz = 12173, + X86_VPRORQZ256mbi = 12174, + X86_VPRORQZ256mbik = 12175, + X86_VPRORQZ256mbikz = 12176, + X86_VPRORQZ256mi = 12177, + X86_VPRORQZ256mik = 12178, + X86_VPRORQZ256mikz = 12179, + X86_VPRORQZ256ri = 12180, + X86_VPRORQZ256rik = 12181, + X86_VPRORQZ256rikz = 12182, + X86_VPRORQZmbi = 12183, + X86_VPRORQZmbik = 12184, + X86_VPRORQZmbikz = 12185, + X86_VPRORQZmi = 12186, + X86_VPRORQZmik = 12187, + X86_VPRORQZmikz = 12188, + X86_VPRORQZri = 12189, + X86_VPRORQZrik = 12190, + X86_VPRORQZrikz = 12191, + X86_VPRORVDZ128rm = 12192, + X86_VPRORVDZ128rmb = 12193, + X86_VPRORVDZ128rmbk = 12194, + X86_VPRORVDZ128rmbkz = 12195, + X86_VPRORVDZ128rmk = 12196, + X86_VPRORVDZ128rmkz = 12197, + X86_VPRORVDZ128rr = 12198, + X86_VPRORVDZ128rrk = 12199, + X86_VPRORVDZ128rrkz = 12200, + X86_VPRORVDZ256rm = 12201, + X86_VPRORVDZ256rmb = 12202, + X86_VPRORVDZ256rmbk = 12203, + X86_VPRORVDZ256rmbkz = 12204, + X86_VPRORVDZ256rmk = 12205, + X86_VPRORVDZ256rmkz = 12206, + X86_VPRORVDZ256rr = 12207, + X86_VPRORVDZ256rrk = 12208, + X86_VPRORVDZ256rrkz = 12209, + X86_VPRORVDZrm = 12210, + X86_VPRORVDZrmb = 12211, + X86_VPRORVDZrmbk = 12212, + X86_VPRORVDZrmbkz = 12213, + X86_VPRORVDZrmk = 12214, + X86_VPRORVDZrmkz = 12215, + X86_VPRORVDZrr = 12216, + X86_VPRORVDZrrk = 12217, + X86_VPRORVDZrrkz = 12218, + X86_VPRORVQZ128rm = 12219, + X86_VPRORVQZ128rmb = 12220, + X86_VPRORVQZ128rmbk = 12221, + X86_VPRORVQZ128rmbkz = 12222, + X86_VPRORVQZ128rmk = 12223, + X86_VPRORVQZ128rmkz = 12224, + X86_VPRORVQZ128rr = 12225, + X86_VPRORVQZ128rrk = 12226, + X86_VPRORVQZ128rrkz = 12227, + X86_VPRORVQZ256rm = 12228, + X86_VPRORVQZ256rmb = 12229, + X86_VPRORVQZ256rmbk = 12230, + X86_VPRORVQZ256rmbkz = 12231, + X86_VPRORVQZ256rmk = 12232, + X86_VPRORVQZ256rmkz = 12233, + X86_VPRORVQZ256rr = 12234, + X86_VPRORVQZ256rrk = 12235, + X86_VPRORVQZ256rrkz = 12236, + X86_VPRORVQZrm = 12237, + X86_VPRORVQZrmb = 12238, + X86_VPRORVQZrmbk = 12239, + X86_VPRORVQZrmbkz = 12240, + X86_VPRORVQZrmk = 12241, + X86_VPRORVQZrmkz = 12242, + X86_VPRORVQZrr = 12243, + X86_VPRORVQZrrk = 12244, + X86_VPRORVQZrrkz = 12245, + X86_VPROTBmi = 12246, + X86_VPROTBmr = 12247, + X86_VPROTBri = 12248, + X86_VPROTBrm = 12249, + X86_VPROTBrr = 12250, + X86_VPROTBrr_REV = 12251, + X86_VPROTDmi = 12252, + X86_VPROTDmr = 12253, + X86_VPROTDri = 12254, + X86_VPROTDrm = 12255, + X86_VPROTDrr = 12256, + X86_VPROTDrr_REV = 12257, + X86_VPROTQmi = 12258, + X86_VPROTQmr = 12259, + X86_VPROTQri = 12260, + X86_VPROTQrm = 12261, + X86_VPROTQrr = 12262, + X86_VPROTQrr_REV = 12263, + X86_VPROTWmi = 12264, + X86_VPROTWmr = 12265, + X86_VPROTWri = 12266, + X86_VPROTWrm = 12267, + X86_VPROTWrr = 12268, + X86_VPROTWrr_REV = 12269, + X86_VPSADBWYrm = 12270, + X86_VPSADBWYrr = 12271, + X86_VPSADBWZ128rm = 12272, + X86_VPSADBWZ128rr = 12273, + X86_VPSADBWZ256rm = 12274, + X86_VPSADBWZ256rr = 12275, + X86_VPSADBWZrm = 12276, + X86_VPSADBWZrr = 12277, + X86_VPSADBWrm = 12278, + X86_VPSADBWrr = 12279, + X86_VPSCATTERDDZ128mr = 12280, + X86_VPSCATTERDDZ256mr = 12281, + X86_VPSCATTERDDZmr = 12282, + X86_VPSCATTERDQZ128mr = 12283, + X86_VPSCATTERDQZ256mr = 12284, + X86_VPSCATTERDQZmr = 12285, + X86_VPSCATTERQDZ128mr = 12286, + X86_VPSCATTERQDZ256mr = 12287, + X86_VPSCATTERQDZmr = 12288, + X86_VPSCATTERQQZ128mr = 12289, + X86_VPSCATTERQQZ256mr = 12290, + X86_VPSCATTERQQZmr = 12291, + X86_VPSHABmr = 12292, + X86_VPSHABrm = 12293, + X86_VPSHABrr = 12294, + X86_VPSHABrr_REV = 12295, + X86_VPSHADmr = 12296, + X86_VPSHADrm = 12297, + X86_VPSHADrr = 12298, + X86_VPSHADrr_REV = 12299, + X86_VPSHAQmr = 12300, + X86_VPSHAQrm = 12301, + X86_VPSHAQrr = 12302, + X86_VPSHAQrr_REV = 12303, + X86_VPSHAWmr = 12304, + X86_VPSHAWrm = 12305, + X86_VPSHAWrr = 12306, + X86_VPSHAWrr_REV = 12307, + X86_VPSHLBmr = 12308, + X86_VPSHLBrm = 12309, + X86_VPSHLBrr = 12310, + X86_VPSHLBrr_REV = 12311, + X86_VPSHLDDZ128rmbi = 12312, + X86_VPSHLDDZ128rmbik = 12313, + X86_VPSHLDDZ128rmbikz = 12314, + X86_VPSHLDDZ128rmi = 12315, + X86_VPSHLDDZ128rmik = 12316, + X86_VPSHLDDZ128rmikz = 12317, + X86_VPSHLDDZ128rri = 12318, + X86_VPSHLDDZ128rrik = 12319, + X86_VPSHLDDZ128rrikz = 12320, + X86_VPSHLDDZ256rmbi = 12321, + X86_VPSHLDDZ256rmbik = 12322, + X86_VPSHLDDZ256rmbikz = 12323, + X86_VPSHLDDZ256rmi = 12324, + X86_VPSHLDDZ256rmik = 12325, + X86_VPSHLDDZ256rmikz = 12326, + X86_VPSHLDDZ256rri = 12327, + X86_VPSHLDDZ256rrik = 12328, + X86_VPSHLDDZ256rrikz = 12329, + X86_VPSHLDDZrmbi = 12330, + X86_VPSHLDDZrmbik = 12331, + X86_VPSHLDDZrmbikz = 12332, + X86_VPSHLDDZrmi = 12333, + X86_VPSHLDDZrmik = 12334, + X86_VPSHLDDZrmikz = 12335, + X86_VPSHLDDZrri = 12336, + X86_VPSHLDDZrrik = 12337, + X86_VPSHLDDZrrikz = 12338, + X86_VPSHLDQZ128rmbi = 12339, + X86_VPSHLDQZ128rmbik = 12340, + X86_VPSHLDQZ128rmbikz = 12341, + X86_VPSHLDQZ128rmi = 12342, + X86_VPSHLDQZ128rmik = 12343, + X86_VPSHLDQZ128rmikz = 12344, + X86_VPSHLDQZ128rri = 12345, + X86_VPSHLDQZ128rrik = 12346, + X86_VPSHLDQZ128rrikz = 12347, + X86_VPSHLDQZ256rmbi = 12348, + X86_VPSHLDQZ256rmbik = 12349, + X86_VPSHLDQZ256rmbikz = 12350, + X86_VPSHLDQZ256rmi = 12351, + X86_VPSHLDQZ256rmik = 12352, + X86_VPSHLDQZ256rmikz = 12353, + X86_VPSHLDQZ256rri = 12354, + X86_VPSHLDQZ256rrik = 12355, + X86_VPSHLDQZ256rrikz = 12356, + X86_VPSHLDQZrmbi = 12357, + X86_VPSHLDQZrmbik = 12358, + X86_VPSHLDQZrmbikz = 12359, + X86_VPSHLDQZrmi = 12360, + X86_VPSHLDQZrmik = 12361, + X86_VPSHLDQZrmikz = 12362, + X86_VPSHLDQZrri = 12363, + X86_VPSHLDQZrrik = 12364, + X86_VPSHLDQZrrikz = 12365, + X86_VPSHLDVDZ128m = 12366, + X86_VPSHLDVDZ128mb = 12367, + X86_VPSHLDVDZ128mbk = 12368, + X86_VPSHLDVDZ128mbkz = 12369, + X86_VPSHLDVDZ128mk = 12370, + X86_VPSHLDVDZ128mkz = 12371, + X86_VPSHLDVDZ128r = 12372, + X86_VPSHLDVDZ128rk = 12373, + X86_VPSHLDVDZ128rkz = 12374, + X86_VPSHLDVDZ256m = 12375, + X86_VPSHLDVDZ256mb = 12376, + X86_VPSHLDVDZ256mbk = 12377, + X86_VPSHLDVDZ256mbkz = 12378, + X86_VPSHLDVDZ256mk = 12379, + X86_VPSHLDVDZ256mkz = 12380, + X86_VPSHLDVDZ256r = 12381, + X86_VPSHLDVDZ256rk = 12382, + X86_VPSHLDVDZ256rkz = 12383, + X86_VPSHLDVDZm = 12384, + X86_VPSHLDVDZmb = 12385, + X86_VPSHLDVDZmbk = 12386, + X86_VPSHLDVDZmbkz = 12387, + X86_VPSHLDVDZmk = 12388, + X86_VPSHLDVDZmkz = 12389, + X86_VPSHLDVDZr = 12390, + X86_VPSHLDVDZrk = 12391, + X86_VPSHLDVDZrkz = 12392, + X86_VPSHLDVQZ128m = 12393, + X86_VPSHLDVQZ128mb = 12394, + X86_VPSHLDVQZ128mbk = 12395, + X86_VPSHLDVQZ128mbkz = 12396, + X86_VPSHLDVQZ128mk = 12397, + X86_VPSHLDVQZ128mkz = 12398, + X86_VPSHLDVQZ128r = 12399, + X86_VPSHLDVQZ128rk = 12400, + X86_VPSHLDVQZ128rkz = 12401, + X86_VPSHLDVQZ256m = 12402, + X86_VPSHLDVQZ256mb = 12403, + X86_VPSHLDVQZ256mbk = 12404, + X86_VPSHLDVQZ256mbkz = 12405, + X86_VPSHLDVQZ256mk = 12406, + X86_VPSHLDVQZ256mkz = 12407, + X86_VPSHLDVQZ256r = 12408, + X86_VPSHLDVQZ256rk = 12409, + X86_VPSHLDVQZ256rkz = 12410, + X86_VPSHLDVQZm = 12411, + X86_VPSHLDVQZmb = 12412, + X86_VPSHLDVQZmbk = 12413, + X86_VPSHLDVQZmbkz = 12414, + X86_VPSHLDVQZmk = 12415, + X86_VPSHLDVQZmkz = 12416, + X86_VPSHLDVQZr = 12417, + X86_VPSHLDVQZrk = 12418, + X86_VPSHLDVQZrkz = 12419, + X86_VPSHLDVWZ128m = 12420, + X86_VPSHLDVWZ128mk = 12421, + X86_VPSHLDVWZ128mkz = 12422, + X86_VPSHLDVWZ128r = 12423, + X86_VPSHLDVWZ128rk = 12424, + X86_VPSHLDVWZ128rkz = 12425, + X86_VPSHLDVWZ256m = 12426, + X86_VPSHLDVWZ256mk = 12427, + X86_VPSHLDVWZ256mkz = 12428, + X86_VPSHLDVWZ256r = 12429, + X86_VPSHLDVWZ256rk = 12430, + X86_VPSHLDVWZ256rkz = 12431, + X86_VPSHLDVWZm = 12432, + X86_VPSHLDVWZmk = 12433, + X86_VPSHLDVWZmkz = 12434, + X86_VPSHLDVWZr = 12435, + X86_VPSHLDVWZrk = 12436, + X86_VPSHLDVWZrkz = 12437, + X86_VPSHLDWZ128rmi = 12438, + X86_VPSHLDWZ128rmik = 12439, + X86_VPSHLDWZ128rmikz = 12440, + X86_VPSHLDWZ128rri = 12441, + X86_VPSHLDWZ128rrik = 12442, + X86_VPSHLDWZ128rrikz = 12443, + X86_VPSHLDWZ256rmi = 12444, + X86_VPSHLDWZ256rmik = 12445, + X86_VPSHLDWZ256rmikz = 12446, + X86_VPSHLDWZ256rri = 12447, + X86_VPSHLDWZ256rrik = 12448, + X86_VPSHLDWZ256rrikz = 12449, + X86_VPSHLDWZrmi = 12450, + X86_VPSHLDWZrmik = 12451, + X86_VPSHLDWZrmikz = 12452, + X86_VPSHLDWZrri = 12453, + X86_VPSHLDWZrrik = 12454, + X86_VPSHLDWZrrikz = 12455, + X86_VPSHLDmr = 12456, + X86_VPSHLDrm = 12457, + X86_VPSHLDrr = 12458, + X86_VPSHLDrr_REV = 12459, + X86_VPSHLQmr = 12460, + X86_VPSHLQrm = 12461, + X86_VPSHLQrr = 12462, + X86_VPSHLQrr_REV = 12463, + X86_VPSHLWmr = 12464, + X86_VPSHLWrm = 12465, + X86_VPSHLWrr = 12466, + X86_VPSHLWrr_REV = 12467, + X86_VPSHRDDZ128rmbi = 12468, + X86_VPSHRDDZ128rmbik = 12469, + X86_VPSHRDDZ128rmbikz = 12470, + X86_VPSHRDDZ128rmi = 12471, + X86_VPSHRDDZ128rmik = 12472, + X86_VPSHRDDZ128rmikz = 12473, + X86_VPSHRDDZ128rri = 12474, + X86_VPSHRDDZ128rrik = 12475, + X86_VPSHRDDZ128rrikz = 12476, + X86_VPSHRDDZ256rmbi = 12477, + X86_VPSHRDDZ256rmbik = 12478, + X86_VPSHRDDZ256rmbikz = 12479, + X86_VPSHRDDZ256rmi = 12480, + X86_VPSHRDDZ256rmik = 12481, + X86_VPSHRDDZ256rmikz = 12482, + X86_VPSHRDDZ256rri = 12483, + X86_VPSHRDDZ256rrik = 12484, + X86_VPSHRDDZ256rrikz = 12485, + X86_VPSHRDDZrmbi = 12486, + X86_VPSHRDDZrmbik = 12487, + X86_VPSHRDDZrmbikz = 12488, + X86_VPSHRDDZrmi = 12489, + X86_VPSHRDDZrmik = 12490, + X86_VPSHRDDZrmikz = 12491, + X86_VPSHRDDZrri = 12492, + X86_VPSHRDDZrrik = 12493, + X86_VPSHRDDZrrikz = 12494, + X86_VPSHRDQZ128rmbi = 12495, + X86_VPSHRDQZ128rmbik = 12496, + X86_VPSHRDQZ128rmbikz = 12497, + X86_VPSHRDQZ128rmi = 12498, + X86_VPSHRDQZ128rmik = 12499, + X86_VPSHRDQZ128rmikz = 12500, + X86_VPSHRDQZ128rri = 12501, + X86_VPSHRDQZ128rrik = 12502, + X86_VPSHRDQZ128rrikz = 12503, + X86_VPSHRDQZ256rmbi = 12504, + X86_VPSHRDQZ256rmbik = 12505, + X86_VPSHRDQZ256rmbikz = 12506, + X86_VPSHRDQZ256rmi = 12507, + X86_VPSHRDQZ256rmik = 12508, + X86_VPSHRDQZ256rmikz = 12509, + X86_VPSHRDQZ256rri = 12510, + X86_VPSHRDQZ256rrik = 12511, + X86_VPSHRDQZ256rrikz = 12512, + X86_VPSHRDQZrmbi = 12513, + X86_VPSHRDQZrmbik = 12514, + X86_VPSHRDQZrmbikz = 12515, + X86_VPSHRDQZrmi = 12516, + X86_VPSHRDQZrmik = 12517, + X86_VPSHRDQZrmikz = 12518, + X86_VPSHRDQZrri = 12519, + X86_VPSHRDQZrrik = 12520, + X86_VPSHRDQZrrikz = 12521, + X86_VPSHRDVDZ128m = 12522, + X86_VPSHRDVDZ128mb = 12523, + X86_VPSHRDVDZ128mbk = 12524, + X86_VPSHRDVDZ128mbkz = 12525, + X86_VPSHRDVDZ128mk = 12526, + X86_VPSHRDVDZ128mkz = 12527, + X86_VPSHRDVDZ128r = 12528, + X86_VPSHRDVDZ128rk = 12529, + X86_VPSHRDVDZ128rkz = 12530, + X86_VPSHRDVDZ256m = 12531, + X86_VPSHRDVDZ256mb = 12532, + X86_VPSHRDVDZ256mbk = 12533, + X86_VPSHRDVDZ256mbkz = 12534, + X86_VPSHRDVDZ256mk = 12535, + X86_VPSHRDVDZ256mkz = 12536, + X86_VPSHRDVDZ256r = 12537, + X86_VPSHRDVDZ256rk = 12538, + X86_VPSHRDVDZ256rkz = 12539, + X86_VPSHRDVDZm = 12540, + X86_VPSHRDVDZmb = 12541, + X86_VPSHRDVDZmbk = 12542, + X86_VPSHRDVDZmbkz = 12543, + X86_VPSHRDVDZmk = 12544, + X86_VPSHRDVDZmkz = 12545, + X86_VPSHRDVDZr = 12546, + X86_VPSHRDVDZrk = 12547, + X86_VPSHRDVDZrkz = 12548, + X86_VPSHRDVQZ128m = 12549, + X86_VPSHRDVQZ128mb = 12550, + X86_VPSHRDVQZ128mbk = 12551, + X86_VPSHRDVQZ128mbkz = 12552, + X86_VPSHRDVQZ128mk = 12553, + X86_VPSHRDVQZ128mkz = 12554, + X86_VPSHRDVQZ128r = 12555, + X86_VPSHRDVQZ128rk = 12556, + X86_VPSHRDVQZ128rkz = 12557, + X86_VPSHRDVQZ256m = 12558, + X86_VPSHRDVQZ256mb = 12559, + X86_VPSHRDVQZ256mbk = 12560, + X86_VPSHRDVQZ256mbkz = 12561, + X86_VPSHRDVQZ256mk = 12562, + X86_VPSHRDVQZ256mkz = 12563, + X86_VPSHRDVQZ256r = 12564, + X86_VPSHRDVQZ256rk = 12565, + X86_VPSHRDVQZ256rkz = 12566, + X86_VPSHRDVQZm = 12567, + X86_VPSHRDVQZmb = 12568, + X86_VPSHRDVQZmbk = 12569, + X86_VPSHRDVQZmbkz = 12570, + X86_VPSHRDVQZmk = 12571, + X86_VPSHRDVQZmkz = 12572, + X86_VPSHRDVQZr = 12573, + X86_VPSHRDVQZrk = 12574, + X86_VPSHRDVQZrkz = 12575, + X86_VPSHRDVWZ128m = 12576, + X86_VPSHRDVWZ128mk = 12577, + X86_VPSHRDVWZ128mkz = 12578, + X86_VPSHRDVWZ128r = 12579, + X86_VPSHRDVWZ128rk = 12580, + X86_VPSHRDVWZ128rkz = 12581, + X86_VPSHRDVWZ256m = 12582, + X86_VPSHRDVWZ256mk = 12583, + X86_VPSHRDVWZ256mkz = 12584, + X86_VPSHRDVWZ256r = 12585, + X86_VPSHRDVWZ256rk = 12586, + X86_VPSHRDVWZ256rkz = 12587, + X86_VPSHRDVWZm = 12588, + X86_VPSHRDVWZmk = 12589, + X86_VPSHRDVWZmkz = 12590, + X86_VPSHRDVWZr = 12591, + X86_VPSHRDVWZrk = 12592, + X86_VPSHRDVWZrkz = 12593, + X86_VPSHRDWZ128rmi = 12594, + X86_VPSHRDWZ128rmik = 12595, + X86_VPSHRDWZ128rmikz = 12596, + X86_VPSHRDWZ128rri = 12597, + X86_VPSHRDWZ128rrik = 12598, + X86_VPSHRDWZ128rrikz = 12599, + X86_VPSHRDWZ256rmi = 12600, + X86_VPSHRDWZ256rmik = 12601, + X86_VPSHRDWZ256rmikz = 12602, + X86_VPSHRDWZ256rri = 12603, + X86_VPSHRDWZ256rrik = 12604, + X86_VPSHRDWZ256rrikz = 12605, + X86_VPSHRDWZrmi = 12606, + X86_VPSHRDWZrmik = 12607, + X86_VPSHRDWZrmikz = 12608, + X86_VPSHRDWZrri = 12609, + X86_VPSHRDWZrrik = 12610, + X86_VPSHRDWZrrikz = 12611, + X86_VPSHUFBITQMBZ128rm = 12612, + X86_VPSHUFBITQMBZ128rmk = 12613, + X86_VPSHUFBITQMBZ128rr = 12614, + X86_VPSHUFBITQMBZ128rrk = 12615, + X86_VPSHUFBITQMBZ256rm = 12616, + X86_VPSHUFBITQMBZ256rmk = 12617, + X86_VPSHUFBITQMBZ256rr = 12618, + X86_VPSHUFBITQMBZ256rrk = 12619, + X86_VPSHUFBITQMBZrm = 12620, + X86_VPSHUFBITQMBZrmk = 12621, + X86_VPSHUFBITQMBZrr = 12622, + X86_VPSHUFBITQMBZrrk = 12623, + X86_VPSHUFBYrm = 12624, + X86_VPSHUFBYrr = 12625, + X86_VPSHUFBZ128rm = 12626, + X86_VPSHUFBZ128rmk = 12627, + X86_VPSHUFBZ128rmkz = 12628, + X86_VPSHUFBZ128rr = 12629, + X86_VPSHUFBZ128rrk = 12630, + X86_VPSHUFBZ128rrkz = 12631, + X86_VPSHUFBZ256rm = 12632, + X86_VPSHUFBZ256rmk = 12633, + X86_VPSHUFBZ256rmkz = 12634, + X86_VPSHUFBZ256rr = 12635, + X86_VPSHUFBZ256rrk = 12636, + X86_VPSHUFBZ256rrkz = 12637, + X86_VPSHUFBZrm = 12638, + X86_VPSHUFBZrmk = 12639, + X86_VPSHUFBZrmkz = 12640, + X86_VPSHUFBZrr = 12641, + X86_VPSHUFBZrrk = 12642, + X86_VPSHUFBZrrkz = 12643, + X86_VPSHUFBrm = 12644, + X86_VPSHUFBrr = 12645, + X86_VPSHUFDYmi = 12646, + X86_VPSHUFDYri = 12647, + X86_VPSHUFDZ128mbi = 12648, + X86_VPSHUFDZ128mbik = 12649, + X86_VPSHUFDZ128mbikz = 12650, + X86_VPSHUFDZ128mi = 12651, + X86_VPSHUFDZ128mik = 12652, + X86_VPSHUFDZ128mikz = 12653, + X86_VPSHUFDZ128ri = 12654, + X86_VPSHUFDZ128rik = 12655, + X86_VPSHUFDZ128rikz = 12656, + X86_VPSHUFDZ256mbi = 12657, + X86_VPSHUFDZ256mbik = 12658, + X86_VPSHUFDZ256mbikz = 12659, + X86_VPSHUFDZ256mi = 12660, + X86_VPSHUFDZ256mik = 12661, + X86_VPSHUFDZ256mikz = 12662, + X86_VPSHUFDZ256ri = 12663, + X86_VPSHUFDZ256rik = 12664, + X86_VPSHUFDZ256rikz = 12665, + X86_VPSHUFDZmbi = 12666, + X86_VPSHUFDZmbik = 12667, + X86_VPSHUFDZmbikz = 12668, + X86_VPSHUFDZmi = 12669, + X86_VPSHUFDZmik = 12670, + X86_VPSHUFDZmikz = 12671, + X86_VPSHUFDZri = 12672, + X86_VPSHUFDZrik = 12673, + X86_VPSHUFDZrikz = 12674, + X86_VPSHUFDmi = 12675, + X86_VPSHUFDri = 12676, + X86_VPSHUFHWYmi = 12677, + X86_VPSHUFHWYri = 12678, + X86_VPSHUFHWZ128mi = 12679, + X86_VPSHUFHWZ128mik = 12680, + X86_VPSHUFHWZ128mikz = 12681, + X86_VPSHUFHWZ128ri = 12682, + X86_VPSHUFHWZ128rik = 12683, + X86_VPSHUFHWZ128rikz = 12684, + X86_VPSHUFHWZ256mi = 12685, + X86_VPSHUFHWZ256mik = 12686, + X86_VPSHUFHWZ256mikz = 12687, + X86_VPSHUFHWZ256ri = 12688, + X86_VPSHUFHWZ256rik = 12689, + X86_VPSHUFHWZ256rikz = 12690, + X86_VPSHUFHWZmi = 12691, + X86_VPSHUFHWZmik = 12692, + X86_VPSHUFHWZmikz = 12693, + X86_VPSHUFHWZri = 12694, + X86_VPSHUFHWZrik = 12695, + X86_VPSHUFHWZrikz = 12696, + X86_VPSHUFHWmi = 12697, + X86_VPSHUFHWri = 12698, + X86_VPSHUFLWYmi = 12699, + X86_VPSHUFLWYri = 12700, + X86_VPSHUFLWZ128mi = 12701, + X86_VPSHUFLWZ128mik = 12702, + X86_VPSHUFLWZ128mikz = 12703, + X86_VPSHUFLWZ128ri = 12704, + X86_VPSHUFLWZ128rik = 12705, + X86_VPSHUFLWZ128rikz = 12706, + X86_VPSHUFLWZ256mi = 12707, + X86_VPSHUFLWZ256mik = 12708, + X86_VPSHUFLWZ256mikz = 12709, + X86_VPSHUFLWZ256ri = 12710, + X86_VPSHUFLWZ256rik = 12711, + X86_VPSHUFLWZ256rikz = 12712, + X86_VPSHUFLWZmi = 12713, + X86_VPSHUFLWZmik = 12714, + X86_VPSHUFLWZmikz = 12715, + X86_VPSHUFLWZri = 12716, + X86_VPSHUFLWZrik = 12717, + X86_VPSHUFLWZrikz = 12718, + X86_VPSHUFLWmi = 12719, + X86_VPSHUFLWri = 12720, + X86_VPSIGNBYrm = 12721, + X86_VPSIGNBYrr = 12722, + X86_VPSIGNBrm = 12723, + X86_VPSIGNBrr = 12724, + X86_VPSIGNDYrm = 12725, + X86_VPSIGNDYrr = 12726, + X86_VPSIGNDrm = 12727, + X86_VPSIGNDrr = 12728, + X86_VPSIGNWYrm = 12729, + X86_VPSIGNWYrr = 12730, + X86_VPSIGNWrm = 12731, + X86_VPSIGNWrr = 12732, + X86_VPSLLDQYri = 12733, + X86_VPSLLDQZ128rm = 12734, + X86_VPSLLDQZ128rr = 12735, + X86_VPSLLDQZ256rm = 12736, + X86_VPSLLDQZ256rr = 12737, + X86_VPSLLDQZrm = 12738, + X86_VPSLLDQZrr = 12739, + X86_VPSLLDQri = 12740, + X86_VPSLLDYri = 12741, + X86_VPSLLDYrm = 12742, + X86_VPSLLDYrr = 12743, + X86_VPSLLDZ128mbi = 12744, + X86_VPSLLDZ128mbik = 12745, + X86_VPSLLDZ128mbikz = 12746, + X86_VPSLLDZ128mi = 12747, + X86_VPSLLDZ128mik = 12748, + X86_VPSLLDZ128mikz = 12749, + X86_VPSLLDZ128ri = 12750, + X86_VPSLLDZ128rik = 12751, + X86_VPSLLDZ128rikz = 12752, + X86_VPSLLDZ128rm = 12753, + X86_VPSLLDZ128rmk = 12754, + X86_VPSLLDZ128rmkz = 12755, + X86_VPSLLDZ128rr = 12756, + X86_VPSLLDZ128rrk = 12757, + X86_VPSLLDZ128rrkz = 12758, + X86_VPSLLDZ256mbi = 12759, + X86_VPSLLDZ256mbik = 12760, + X86_VPSLLDZ256mbikz = 12761, + X86_VPSLLDZ256mi = 12762, + X86_VPSLLDZ256mik = 12763, + X86_VPSLLDZ256mikz = 12764, + X86_VPSLLDZ256ri = 12765, + X86_VPSLLDZ256rik = 12766, + X86_VPSLLDZ256rikz = 12767, + X86_VPSLLDZ256rm = 12768, + X86_VPSLLDZ256rmk = 12769, + X86_VPSLLDZ256rmkz = 12770, + X86_VPSLLDZ256rr = 12771, + X86_VPSLLDZ256rrk = 12772, + X86_VPSLLDZ256rrkz = 12773, + X86_VPSLLDZmbi = 12774, + X86_VPSLLDZmbik = 12775, + X86_VPSLLDZmbikz = 12776, + X86_VPSLLDZmi = 12777, + X86_VPSLLDZmik = 12778, + X86_VPSLLDZmikz = 12779, + X86_VPSLLDZri = 12780, + X86_VPSLLDZrik = 12781, + X86_VPSLLDZrikz = 12782, + X86_VPSLLDZrm = 12783, + X86_VPSLLDZrmk = 12784, + X86_VPSLLDZrmkz = 12785, + X86_VPSLLDZrr = 12786, + X86_VPSLLDZrrk = 12787, + X86_VPSLLDZrrkz = 12788, + X86_VPSLLDri = 12789, + X86_VPSLLDrm = 12790, + X86_VPSLLDrr = 12791, + X86_VPSLLQYri = 12792, + X86_VPSLLQYrm = 12793, + X86_VPSLLQYrr = 12794, + X86_VPSLLQZ128mbi = 12795, + X86_VPSLLQZ128mbik = 12796, + X86_VPSLLQZ128mbikz = 12797, + X86_VPSLLQZ128mi = 12798, + X86_VPSLLQZ128mik = 12799, + X86_VPSLLQZ128mikz = 12800, + X86_VPSLLQZ128ri = 12801, + X86_VPSLLQZ128rik = 12802, + X86_VPSLLQZ128rikz = 12803, + X86_VPSLLQZ128rm = 12804, + X86_VPSLLQZ128rmk = 12805, + X86_VPSLLQZ128rmkz = 12806, + X86_VPSLLQZ128rr = 12807, + X86_VPSLLQZ128rrk = 12808, + X86_VPSLLQZ128rrkz = 12809, + X86_VPSLLQZ256mbi = 12810, + X86_VPSLLQZ256mbik = 12811, + X86_VPSLLQZ256mbikz = 12812, + X86_VPSLLQZ256mi = 12813, + X86_VPSLLQZ256mik = 12814, + X86_VPSLLQZ256mikz = 12815, + X86_VPSLLQZ256ri = 12816, + X86_VPSLLQZ256rik = 12817, + X86_VPSLLQZ256rikz = 12818, + X86_VPSLLQZ256rm = 12819, + X86_VPSLLQZ256rmk = 12820, + X86_VPSLLQZ256rmkz = 12821, + X86_VPSLLQZ256rr = 12822, + X86_VPSLLQZ256rrk = 12823, + X86_VPSLLQZ256rrkz = 12824, + X86_VPSLLQZmbi = 12825, + X86_VPSLLQZmbik = 12826, + X86_VPSLLQZmbikz = 12827, + X86_VPSLLQZmi = 12828, + X86_VPSLLQZmik = 12829, + X86_VPSLLQZmikz = 12830, + X86_VPSLLQZri = 12831, + X86_VPSLLQZrik = 12832, + X86_VPSLLQZrikz = 12833, + X86_VPSLLQZrm = 12834, + X86_VPSLLQZrmk = 12835, + X86_VPSLLQZrmkz = 12836, + X86_VPSLLQZrr = 12837, + X86_VPSLLQZrrk = 12838, + X86_VPSLLQZrrkz = 12839, + X86_VPSLLQri = 12840, + X86_VPSLLQrm = 12841, + X86_VPSLLQrr = 12842, + X86_VPSLLVDYrm = 12843, + X86_VPSLLVDYrr = 12844, + X86_VPSLLVDZ128rm = 12845, + X86_VPSLLVDZ128rmb = 12846, + X86_VPSLLVDZ128rmbk = 12847, + X86_VPSLLVDZ128rmbkz = 12848, + X86_VPSLLVDZ128rmk = 12849, + X86_VPSLLVDZ128rmkz = 12850, + X86_VPSLLVDZ128rr = 12851, + X86_VPSLLVDZ128rrk = 12852, + X86_VPSLLVDZ128rrkz = 12853, + X86_VPSLLVDZ256rm = 12854, + X86_VPSLLVDZ256rmb = 12855, + X86_VPSLLVDZ256rmbk = 12856, + X86_VPSLLVDZ256rmbkz = 12857, + X86_VPSLLVDZ256rmk = 12858, + X86_VPSLLVDZ256rmkz = 12859, + X86_VPSLLVDZ256rr = 12860, + X86_VPSLLVDZ256rrk = 12861, + X86_VPSLLVDZ256rrkz = 12862, + X86_VPSLLVDZrm = 12863, + X86_VPSLLVDZrmb = 12864, + X86_VPSLLVDZrmbk = 12865, + X86_VPSLLVDZrmbkz = 12866, + X86_VPSLLVDZrmk = 12867, + X86_VPSLLVDZrmkz = 12868, + X86_VPSLLVDZrr = 12869, + X86_VPSLLVDZrrk = 12870, + X86_VPSLLVDZrrkz = 12871, + X86_VPSLLVDrm = 12872, + X86_VPSLLVDrr = 12873, + X86_VPSLLVQYrm = 12874, + X86_VPSLLVQYrr = 12875, + X86_VPSLLVQZ128rm = 12876, + X86_VPSLLVQZ128rmb = 12877, + X86_VPSLLVQZ128rmbk = 12878, + X86_VPSLLVQZ128rmbkz = 12879, + X86_VPSLLVQZ128rmk = 12880, + X86_VPSLLVQZ128rmkz = 12881, + X86_VPSLLVQZ128rr = 12882, + X86_VPSLLVQZ128rrk = 12883, + X86_VPSLLVQZ128rrkz = 12884, + X86_VPSLLVQZ256rm = 12885, + X86_VPSLLVQZ256rmb = 12886, + X86_VPSLLVQZ256rmbk = 12887, + X86_VPSLLVQZ256rmbkz = 12888, + X86_VPSLLVQZ256rmk = 12889, + X86_VPSLLVQZ256rmkz = 12890, + X86_VPSLLVQZ256rr = 12891, + X86_VPSLLVQZ256rrk = 12892, + X86_VPSLLVQZ256rrkz = 12893, + X86_VPSLLVQZrm = 12894, + X86_VPSLLVQZrmb = 12895, + X86_VPSLLVQZrmbk = 12896, + X86_VPSLLVQZrmbkz = 12897, + X86_VPSLLVQZrmk = 12898, + X86_VPSLLVQZrmkz = 12899, + X86_VPSLLVQZrr = 12900, + X86_VPSLLVQZrrk = 12901, + X86_VPSLLVQZrrkz = 12902, + X86_VPSLLVQrm = 12903, + X86_VPSLLVQrr = 12904, + X86_VPSLLVWZ128rm = 12905, + X86_VPSLLVWZ128rmk = 12906, + X86_VPSLLVWZ128rmkz = 12907, + X86_VPSLLVWZ128rr = 12908, + X86_VPSLLVWZ128rrk = 12909, + X86_VPSLLVWZ128rrkz = 12910, + X86_VPSLLVWZ256rm = 12911, + X86_VPSLLVWZ256rmk = 12912, + X86_VPSLLVWZ256rmkz = 12913, + X86_VPSLLVWZ256rr = 12914, + X86_VPSLLVWZ256rrk = 12915, + X86_VPSLLVWZ256rrkz = 12916, + X86_VPSLLVWZrm = 12917, + X86_VPSLLVWZrmk = 12918, + X86_VPSLLVWZrmkz = 12919, + X86_VPSLLVWZrr = 12920, + X86_VPSLLVWZrrk = 12921, + X86_VPSLLVWZrrkz = 12922, + X86_VPSLLWYri = 12923, + X86_VPSLLWYrm = 12924, + X86_VPSLLWYrr = 12925, + X86_VPSLLWZ128mi = 12926, + X86_VPSLLWZ128mik = 12927, + X86_VPSLLWZ128mikz = 12928, + X86_VPSLLWZ128ri = 12929, + X86_VPSLLWZ128rik = 12930, + X86_VPSLLWZ128rikz = 12931, + X86_VPSLLWZ128rm = 12932, + X86_VPSLLWZ128rmk = 12933, + X86_VPSLLWZ128rmkz = 12934, + X86_VPSLLWZ128rr = 12935, + X86_VPSLLWZ128rrk = 12936, + X86_VPSLLWZ128rrkz = 12937, + X86_VPSLLWZ256mi = 12938, + X86_VPSLLWZ256mik = 12939, + X86_VPSLLWZ256mikz = 12940, + X86_VPSLLWZ256ri = 12941, + X86_VPSLLWZ256rik = 12942, + X86_VPSLLWZ256rikz = 12943, + X86_VPSLLWZ256rm = 12944, + X86_VPSLLWZ256rmk = 12945, + X86_VPSLLWZ256rmkz = 12946, + X86_VPSLLWZ256rr = 12947, + X86_VPSLLWZ256rrk = 12948, + X86_VPSLLWZ256rrkz = 12949, + X86_VPSLLWZmi = 12950, + X86_VPSLLWZmik = 12951, + X86_VPSLLWZmikz = 12952, + X86_VPSLLWZri = 12953, + X86_VPSLLWZrik = 12954, + X86_VPSLLWZrikz = 12955, + X86_VPSLLWZrm = 12956, + X86_VPSLLWZrmk = 12957, + X86_VPSLLWZrmkz = 12958, + X86_VPSLLWZrr = 12959, + X86_VPSLLWZrrk = 12960, + X86_VPSLLWZrrkz = 12961, + X86_VPSLLWri = 12962, + X86_VPSLLWrm = 12963, + X86_VPSLLWrr = 12964, + X86_VPSRADYri = 12965, + X86_VPSRADYrm = 12966, + X86_VPSRADYrr = 12967, + X86_VPSRADZ128mbi = 12968, + X86_VPSRADZ128mbik = 12969, + X86_VPSRADZ128mbikz = 12970, + X86_VPSRADZ128mi = 12971, + X86_VPSRADZ128mik = 12972, + X86_VPSRADZ128mikz = 12973, + X86_VPSRADZ128ri = 12974, + X86_VPSRADZ128rik = 12975, + X86_VPSRADZ128rikz = 12976, + X86_VPSRADZ128rm = 12977, + X86_VPSRADZ128rmk = 12978, + X86_VPSRADZ128rmkz = 12979, + X86_VPSRADZ128rr = 12980, + X86_VPSRADZ128rrk = 12981, + X86_VPSRADZ128rrkz = 12982, + X86_VPSRADZ256mbi = 12983, + X86_VPSRADZ256mbik = 12984, + X86_VPSRADZ256mbikz = 12985, + X86_VPSRADZ256mi = 12986, + X86_VPSRADZ256mik = 12987, + X86_VPSRADZ256mikz = 12988, + X86_VPSRADZ256ri = 12989, + X86_VPSRADZ256rik = 12990, + X86_VPSRADZ256rikz = 12991, + X86_VPSRADZ256rm = 12992, + X86_VPSRADZ256rmk = 12993, + X86_VPSRADZ256rmkz = 12994, + X86_VPSRADZ256rr = 12995, + X86_VPSRADZ256rrk = 12996, + X86_VPSRADZ256rrkz = 12997, + X86_VPSRADZmbi = 12998, + X86_VPSRADZmbik = 12999, + X86_VPSRADZmbikz = 13000, + X86_VPSRADZmi = 13001, + X86_VPSRADZmik = 13002, + X86_VPSRADZmikz = 13003, + X86_VPSRADZri = 13004, + X86_VPSRADZrik = 13005, + X86_VPSRADZrikz = 13006, + X86_VPSRADZrm = 13007, + X86_VPSRADZrmk = 13008, + X86_VPSRADZrmkz = 13009, + X86_VPSRADZrr = 13010, + X86_VPSRADZrrk = 13011, + X86_VPSRADZrrkz = 13012, + X86_VPSRADri = 13013, + X86_VPSRADrm = 13014, + X86_VPSRADrr = 13015, + X86_VPSRAQZ128mbi = 13016, + X86_VPSRAQZ128mbik = 13017, + X86_VPSRAQZ128mbikz = 13018, + X86_VPSRAQZ128mi = 13019, + X86_VPSRAQZ128mik = 13020, + X86_VPSRAQZ128mikz = 13021, + X86_VPSRAQZ128ri = 13022, + X86_VPSRAQZ128rik = 13023, + X86_VPSRAQZ128rikz = 13024, + X86_VPSRAQZ128rm = 13025, + X86_VPSRAQZ128rmk = 13026, + X86_VPSRAQZ128rmkz = 13027, + X86_VPSRAQZ128rr = 13028, + X86_VPSRAQZ128rrk = 13029, + X86_VPSRAQZ128rrkz = 13030, + X86_VPSRAQZ256mbi = 13031, + X86_VPSRAQZ256mbik = 13032, + X86_VPSRAQZ256mbikz = 13033, + X86_VPSRAQZ256mi = 13034, + X86_VPSRAQZ256mik = 13035, + X86_VPSRAQZ256mikz = 13036, + X86_VPSRAQZ256ri = 13037, + X86_VPSRAQZ256rik = 13038, + X86_VPSRAQZ256rikz = 13039, + X86_VPSRAQZ256rm = 13040, + X86_VPSRAQZ256rmk = 13041, + X86_VPSRAQZ256rmkz = 13042, + X86_VPSRAQZ256rr = 13043, + X86_VPSRAQZ256rrk = 13044, + X86_VPSRAQZ256rrkz = 13045, + X86_VPSRAQZmbi = 13046, + X86_VPSRAQZmbik = 13047, + X86_VPSRAQZmbikz = 13048, + X86_VPSRAQZmi = 13049, + X86_VPSRAQZmik = 13050, + X86_VPSRAQZmikz = 13051, + X86_VPSRAQZri = 13052, + X86_VPSRAQZrik = 13053, + X86_VPSRAQZrikz = 13054, + X86_VPSRAQZrm = 13055, + X86_VPSRAQZrmk = 13056, + X86_VPSRAQZrmkz = 13057, + X86_VPSRAQZrr = 13058, + X86_VPSRAQZrrk = 13059, + X86_VPSRAQZrrkz = 13060, + X86_VPSRAVDYrm = 13061, + X86_VPSRAVDYrr = 13062, + X86_VPSRAVDZ128rm = 13063, + X86_VPSRAVDZ128rmb = 13064, + X86_VPSRAVDZ128rmbk = 13065, + X86_VPSRAVDZ128rmbkz = 13066, + X86_VPSRAVDZ128rmk = 13067, + X86_VPSRAVDZ128rmkz = 13068, + X86_VPSRAVDZ128rr = 13069, + X86_VPSRAVDZ128rrk = 13070, + X86_VPSRAVDZ128rrkz = 13071, + X86_VPSRAVDZ256rm = 13072, + X86_VPSRAVDZ256rmb = 13073, + X86_VPSRAVDZ256rmbk = 13074, + X86_VPSRAVDZ256rmbkz = 13075, + X86_VPSRAVDZ256rmk = 13076, + X86_VPSRAVDZ256rmkz = 13077, + X86_VPSRAVDZ256rr = 13078, + X86_VPSRAVDZ256rrk = 13079, + X86_VPSRAVDZ256rrkz = 13080, + X86_VPSRAVDZrm = 13081, + X86_VPSRAVDZrmb = 13082, + X86_VPSRAVDZrmbk = 13083, + X86_VPSRAVDZrmbkz = 13084, + X86_VPSRAVDZrmk = 13085, + X86_VPSRAVDZrmkz = 13086, + X86_VPSRAVDZrr = 13087, + X86_VPSRAVDZrrk = 13088, + X86_VPSRAVDZrrkz = 13089, + X86_VPSRAVDrm = 13090, + X86_VPSRAVDrr = 13091, + X86_VPSRAVQZ128rm = 13092, + X86_VPSRAVQZ128rmb = 13093, + X86_VPSRAVQZ128rmbk = 13094, + X86_VPSRAVQZ128rmbkz = 13095, + X86_VPSRAVQZ128rmk = 13096, + X86_VPSRAVQZ128rmkz = 13097, + X86_VPSRAVQZ128rr = 13098, + X86_VPSRAVQZ128rrk = 13099, + X86_VPSRAVQZ128rrkz = 13100, + X86_VPSRAVQZ256rm = 13101, + X86_VPSRAVQZ256rmb = 13102, + X86_VPSRAVQZ256rmbk = 13103, + X86_VPSRAVQZ256rmbkz = 13104, + X86_VPSRAVQZ256rmk = 13105, + X86_VPSRAVQZ256rmkz = 13106, + X86_VPSRAVQZ256rr = 13107, + X86_VPSRAVQZ256rrk = 13108, + X86_VPSRAVQZ256rrkz = 13109, + X86_VPSRAVQZrm = 13110, + X86_VPSRAVQZrmb = 13111, + X86_VPSRAVQZrmbk = 13112, + X86_VPSRAVQZrmbkz = 13113, + X86_VPSRAVQZrmk = 13114, + X86_VPSRAVQZrmkz = 13115, + X86_VPSRAVQZrr = 13116, + X86_VPSRAVQZrrk = 13117, + X86_VPSRAVQZrrkz = 13118, + X86_VPSRAVWZ128rm = 13119, + X86_VPSRAVWZ128rmk = 13120, + X86_VPSRAVWZ128rmkz = 13121, + X86_VPSRAVWZ128rr = 13122, + X86_VPSRAVWZ128rrk = 13123, + X86_VPSRAVWZ128rrkz = 13124, + X86_VPSRAVWZ256rm = 13125, + X86_VPSRAVWZ256rmk = 13126, + X86_VPSRAVWZ256rmkz = 13127, + X86_VPSRAVWZ256rr = 13128, + X86_VPSRAVWZ256rrk = 13129, + X86_VPSRAVWZ256rrkz = 13130, + X86_VPSRAVWZrm = 13131, + X86_VPSRAVWZrmk = 13132, + X86_VPSRAVWZrmkz = 13133, + X86_VPSRAVWZrr = 13134, + X86_VPSRAVWZrrk = 13135, + X86_VPSRAVWZrrkz = 13136, + X86_VPSRAWYri = 13137, + X86_VPSRAWYrm = 13138, + X86_VPSRAWYrr = 13139, + X86_VPSRAWZ128mi = 13140, + X86_VPSRAWZ128mik = 13141, + X86_VPSRAWZ128mikz = 13142, + X86_VPSRAWZ128ri = 13143, + X86_VPSRAWZ128rik = 13144, + X86_VPSRAWZ128rikz = 13145, + X86_VPSRAWZ128rm = 13146, + X86_VPSRAWZ128rmk = 13147, + X86_VPSRAWZ128rmkz = 13148, + X86_VPSRAWZ128rr = 13149, + X86_VPSRAWZ128rrk = 13150, + X86_VPSRAWZ128rrkz = 13151, + X86_VPSRAWZ256mi = 13152, + X86_VPSRAWZ256mik = 13153, + X86_VPSRAWZ256mikz = 13154, + X86_VPSRAWZ256ri = 13155, + X86_VPSRAWZ256rik = 13156, + X86_VPSRAWZ256rikz = 13157, + X86_VPSRAWZ256rm = 13158, + X86_VPSRAWZ256rmk = 13159, + X86_VPSRAWZ256rmkz = 13160, + X86_VPSRAWZ256rr = 13161, + X86_VPSRAWZ256rrk = 13162, + X86_VPSRAWZ256rrkz = 13163, + X86_VPSRAWZmi = 13164, + X86_VPSRAWZmik = 13165, + X86_VPSRAWZmikz = 13166, + X86_VPSRAWZri = 13167, + X86_VPSRAWZrik = 13168, + X86_VPSRAWZrikz = 13169, + X86_VPSRAWZrm = 13170, + X86_VPSRAWZrmk = 13171, + X86_VPSRAWZrmkz = 13172, + X86_VPSRAWZrr = 13173, + X86_VPSRAWZrrk = 13174, + X86_VPSRAWZrrkz = 13175, + X86_VPSRAWri = 13176, + X86_VPSRAWrm = 13177, + X86_VPSRAWrr = 13178, + X86_VPSRLDQYri = 13179, + X86_VPSRLDQZ128rm = 13180, + X86_VPSRLDQZ128rr = 13181, + X86_VPSRLDQZ256rm = 13182, + X86_VPSRLDQZ256rr = 13183, + X86_VPSRLDQZrm = 13184, + X86_VPSRLDQZrr = 13185, + X86_VPSRLDQri = 13186, + X86_VPSRLDYri = 13187, + X86_VPSRLDYrm = 13188, + X86_VPSRLDYrr = 13189, + X86_VPSRLDZ128mbi = 13190, + X86_VPSRLDZ128mbik = 13191, + X86_VPSRLDZ128mbikz = 13192, + X86_VPSRLDZ128mi = 13193, + X86_VPSRLDZ128mik = 13194, + X86_VPSRLDZ128mikz = 13195, + X86_VPSRLDZ128ri = 13196, + X86_VPSRLDZ128rik = 13197, + X86_VPSRLDZ128rikz = 13198, + X86_VPSRLDZ128rm = 13199, + X86_VPSRLDZ128rmk = 13200, + X86_VPSRLDZ128rmkz = 13201, + X86_VPSRLDZ128rr = 13202, + X86_VPSRLDZ128rrk = 13203, + X86_VPSRLDZ128rrkz = 13204, + X86_VPSRLDZ256mbi = 13205, + X86_VPSRLDZ256mbik = 13206, + X86_VPSRLDZ256mbikz = 13207, + X86_VPSRLDZ256mi = 13208, + X86_VPSRLDZ256mik = 13209, + X86_VPSRLDZ256mikz = 13210, + X86_VPSRLDZ256ri = 13211, + X86_VPSRLDZ256rik = 13212, + X86_VPSRLDZ256rikz = 13213, + X86_VPSRLDZ256rm = 13214, + X86_VPSRLDZ256rmk = 13215, + X86_VPSRLDZ256rmkz = 13216, + X86_VPSRLDZ256rr = 13217, + X86_VPSRLDZ256rrk = 13218, + X86_VPSRLDZ256rrkz = 13219, + X86_VPSRLDZmbi = 13220, + X86_VPSRLDZmbik = 13221, + X86_VPSRLDZmbikz = 13222, + X86_VPSRLDZmi = 13223, + X86_VPSRLDZmik = 13224, + X86_VPSRLDZmikz = 13225, + X86_VPSRLDZri = 13226, + X86_VPSRLDZrik = 13227, + X86_VPSRLDZrikz = 13228, + X86_VPSRLDZrm = 13229, + X86_VPSRLDZrmk = 13230, + X86_VPSRLDZrmkz = 13231, + X86_VPSRLDZrr = 13232, + X86_VPSRLDZrrk = 13233, + X86_VPSRLDZrrkz = 13234, + X86_VPSRLDri = 13235, + X86_VPSRLDrm = 13236, + X86_VPSRLDrr = 13237, + X86_VPSRLQYri = 13238, + X86_VPSRLQYrm = 13239, + X86_VPSRLQYrr = 13240, + X86_VPSRLQZ128mbi = 13241, + X86_VPSRLQZ128mbik = 13242, + X86_VPSRLQZ128mbikz = 13243, + X86_VPSRLQZ128mi = 13244, + X86_VPSRLQZ128mik = 13245, + X86_VPSRLQZ128mikz = 13246, + X86_VPSRLQZ128ri = 13247, + X86_VPSRLQZ128rik = 13248, + X86_VPSRLQZ128rikz = 13249, + X86_VPSRLQZ128rm = 13250, + X86_VPSRLQZ128rmk = 13251, + X86_VPSRLQZ128rmkz = 13252, + X86_VPSRLQZ128rr = 13253, + X86_VPSRLQZ128rrk = 13254, + X86_VPSRLQZ128rrkz = 13255, + X86_VPSRLQZ256mbi = 13256, + X86_VPSRLQZ256mbik = 13257, + X86_VPSRLQZ256mbikz = 13258, + X86_VPSRLQZ256mi = 13259, + X86_VPSRLQZ256mik = 13260, + X86_VPSRLQZ256mikz = 13261, + X86_VPSRLQZ256ri = 13262, + X86_VPSRLQZ256rik = 13263, + X86_VPSRLQZ256rikz = 13264, + X86_VPSRLQZ256rm = 13265, + X86_VPSRLQZ256rmk = 13266, + X86_VPSRLQZ256rmkz = 13267, + X86_VPSRLQZ256rr = 13268, + X86_VPSRLQZ256rrk = 13269, + X86_VPSRLQZ256rrkz = 13270, + X86_VPSRLQZmbi = 13271, + X86_VPSRLQZmbik = 13272, + X86_VPSRLQZmbikz = 13273, + X86_VPSRLQZmi = 13274, + X86_VPSRLQZmik = 13275, + X86_VPSRLQZmikz = 13276, + X86_VPSRLQZri = 13277, + X86_VPSRLQZrik = 13278, + X86_VPSRLQZrikz = 13279, + X86_VPSRLQZrm = 13280, + X86_VPSRLQZrmk = 13281, + X86_VPSRLQZrmkz = 13282, + X86_VPSRLQZrr = 13283, + X86_VPSRLQZrrk = 13284, + X86_VPSRLQZrrkz = 13285, + X86_VPSRLQri = 13286, + X86_VPSRLQrm = 13287, + X86_VPSRLQrr = 13288, + X86_VPSRLVDYrm = 13289, + X86_VPSRLVDYrr = 13290, + X86_VPSRLVDZ128rm = 13291, + X86_VPSRLVDZ128rmb = 13292, + X86_VPSRLVDZ128rmbk = 13293, + X86_VPSRLVDZ128rmbkz = 13294, + X86_VPSRLVDZ128rmk = 13295, + X86_VPSRLVDZ128rmkz = 13296, + X86_VPSRLVDZ128rr = 13297, + X86_VPSRLVDZ128rrk = 13298, + X86_VPSRLVDZ128rrkz = 13299, + X86_VPSRLVDZ256rm = 13300, + X86_VPSRLVDZ256rmb = 13301, + X86_VPSRLVDZ256rmbk = 13302, + X86_VPSRLVDZ256rmbkz = 13303, + X86_VPSRLVDZ256rmk = 13304, + X86_VPSRLVDZ256rmkz = 13305, + X86_VPSRLVDZ256rr = 13306, + X86_VPSRLVDZ256rrk = 13307, + X86_VPSRLVDZ256rrkz = 13308, + X86_VPSRLVDZrm = 13309, + X86_VPSRLVDZrmb = 13310, + X86_VPSRLVDZrmbk = 13311, + X86_VPSRLVDZrmbkz = 13312, + X86_VPSRLVDZrmk = 13313, + X86_VPSRLVDZrmkz = 13314, + X86_VPSRLVDZrr = 13315, + X86_VPSRLVDZrrk = 13316, + X86_VPSRLVDZrrkz = 13317, + X86_VPSRLVDrm = 13318, + X86_VPSRLVDrr = 13319, + X86_VPSRLVQYrm = 13320, + X86_VPSRLVQYrr = 13321, + X86_VPSRLVQZ128rm = 13322, + X86_VPSRLVQZ128rmb = 13323, + X86_VPSRLVQZ128rmbk = 13324, + X86_VPSRLVQZ128rmbkz = 13325, + X86_VPSRLVQZ128rmk = 13326, + X86_VPSRLVQZ128rmkz = 13327, + X86_VPSRLVQZ128rr = 13328, + X86_VPSRLVQZ128rrk = 13329, + X86_VPSRLVQZ128rrkz = 13330, + X86_VPSRLVQZ256rm = 13331, + X86_VPSRLVQZ256rmb = 13332, + X86_VPSRLVQZ256rmbk = 13333, + X86_VPSRLVQZ256rmbkz = 13334, + X86_VPSRLVQZ256rmk = 13335, + X86_VPSRLVQZ256rmkz = 13336, + X86_VPSRLVQZ256rr = 13337, + X86_VPSRLVQZ256rrk = 13338, + X86_VPSRLVQZ256rrkz = 13339, + X86_VPSRLVQZrm = 13340, + X86_VPSRLVQZrmb = 13341, + X86_VPSRLVQZrmbk = 13342, + X86_VPSRLVQZrmbkz = 13343, + X86_VPSRLVQZrmk = 13344, + X86_VPSRLVQZrmkz = 13345, + X86_VPSRLVQZrr = 13346, + X86_VPSRLVQZrrk = 13347, + X86_VPSRLVQZrrkz = 13348, + X86_VPSRLVQrm = 13349, + X86_VPSRLVQrr = 13350, + X86_VPSRLVWZ128rm = 13351, + X86_VPSRLVWZ128rmk = 13352, + X86_VPSRLVWZ128rmkz = 13353, + X86_VPSRLVWZ128rr = 13354, + X86_VPSRLVWZ128rrk = 13355, + X86_VPSRLVWZ128rrkz = 13356, + X86_VPSRLVWZ256rm = 13357, + X86_VPSRLVWZ256rmk = 13358, + X86_VPSRLVWZ256rmkz = 13359, + X86_VPSRLVWZ256rr = 13360, + X86_VPSRLVWZ256rrk = 13361, + X86_VPSRLVWZ256rrkz = 13362, + X86_VPSRLVWZrm = 13363, + X86_VPSRLVWZrmk = 13364, + X86_VPSRLVWZrmkz = 13365, + X86_VPSRLVWZrr = 13366, + X86_VPSRLVWZrrk = 13367, + X86_VPSRLVWZrrkz = 13368, + X86_VPSRLWYri = 13369, + X86_VPSRLWYrm = 13370, + X86_VPSRLWYrr = 13371, + X86_VPSRLWZ128mi = 13372, + X86_VPSRLWZ128mik = 13373, + X86_VPSRLWZ128mikz = 13374, + X86_VPSRLWZ128ri = 13375, + X86_VPSRLWZ128rik = 13376, + X86_VPSRLWZ128rikz = 13377, + X86_VPSRLWZ128rm = 13378, + X86_VPSRLWZ128rmk = 13379, + X86_VPSRLWZ128rmkz = 13380, + X86_VPSRLWZ128rr = 13381, + X86_VPSRLWZ128rrk = 13382, + X86_VPSRLWZ128rrkz = 13383, + X86_VPSRLWZ256mi = 13384, + X86_VPSRLWZ256mik = 13385, + X86_VPSRLWZ256mikz = 13386, + X86_VPSRLWZ256ri = 13387, + X86_VPSRLWZ256rik = 13388, + X86_VPSRLWZ256rikz = 13389, + X86_VPSRLWZ256rm = 13390, + X86_VPSRLWZ256rmk = 13391, + X86_VPSRLWZ256rmkz = 13392, + X86_VPSRLWZ256rr = 13393, + X86_VPSRLWZ256rrk = 13394, + X86_VPSRLWZ256rrkz = 13395, + X86_VPSRLWZmi = 13396, + X86_VPSRLWZmik = 13397, + X86_VPSRLWZmikz = 13398, + X86_VPSRLWZri = 13399, + X86_VPSRLWZrik = 13400, + X86_VPSRLWZrikz = 13401, + X86_VPSRLWZrm = 13402, + X86_VPSRLWZrmk = 13403, + X86_VPSRLWZrmkz = 13404, + X86_VPSRLWZrr = 13405, + X86_VPSRLWZrrk = 13406, + X86_VPSRLWZrrkz = 13407, + X86_VPSRLWri = 13408, + X86_VPSRLWrm = 13409, + X86_VPSRLWrr = 13410, + X86_VPSUBBYrm = 13411, + X86_VPSUBBYrr = 13412, + X86_VPSUBBZ128rm = 13413, + X86_VPSUBBZ128rmk = 13414, + X86_VPSUBBZ128rmkz = 13415, + X86_VPSUBBZ128rr = 13416, + X86_VPSUBBZ128rrk = 13417, + X86_VPSUBBZ128rrkz = 13418, + X86_VPSUBBZ256rm = 13419, + X86_VPSUBBZ256rmk = 13420, + X86_VPSUBBZ256rmkz = 13421, + X86_VPSUBBZ256rr = 13422, + X86_VPSUBBZ256rrk = 13423, + X86_VPSUBBZ256rrkz = 13424, + X86_VPSUBBZrm = 13425, + X86_VPSUBBZrmk = 13426, + X86_VPSUBBZrmkz = 13427, + X86_VPSUBBZrr = 13428, + X86_VPSUBBZrrk = 13429, + X86_VPSUBBZrrkz = 13430, + X86_VPSUBBrm = 13431, + X86_VPSUBBrr = 13432, + X86_VPSUBDYrm = 13433, + X86_VPSUBDYrr = 13434, + X86_VPSUBDZ128rm = 13435, + X86_VPSUBDZ128rmb = 13436, + X86_VPSUBDZ128rmbk = 13437, + X86_VPSUBDZ128rmbkz = 13438, + X86_VPSUBDZ128rmk = 13439, + X86_VPSUBDZ128rmkz = 13440, + X86_VPSUBDZ128rr = 13441, + X86_VPSUBDZ128rrk = 13442, + X86_VPSUBDZ128rrkz = 13443, + X86_VPSUBDZ256rm = 13444, + X86_VPSUBDZ256rmb = 13445, + X86_VPSUBDZ256rmbk = 13446, + X86_VPSUBDZ256rmbkz = 13447, + X86_VPSUBDZ256rmk = 13448, + X86_VPSUBDZ256rmkz = 13449, + X86_VPSUBDZ256rr = 13450, + X86_VPSUBDZ256rrk = 13451, + X86_VPSUBDZ256rrkz = 13452, + X86_VPSUBDZrm = 13453, + X86_VPSUBDZrmb = 13454, + X86_VPSUBDZrmbk = 13455, + X86_VPSUBDZrmbkz = 13456, + X86_VPSUBDZrmk = 13457, + X86_VPSUBDZrmkz = 13458, + X86_VPSUBDZrr = 13459, + X86_VPSUBDZrrk = 13460, + X86_VPSUBDZrrkz = 13461, + X86_VPSUBDrm = 13462, + X86_VPSUBDrr = 13463, + X86_VPSUBQYrm = 13464, + X86_VPSUBQYrr = 13465, + X86_VPSUBQZ128rm = 13466, + X86_VPSUBQZ128rmb = 13467, + X86_VPSUBQZ128rmbk = 13468, + X86_VPSUBQZ128rmbkz = 13469, + X86_VPSUBQZ128rmk = 13470, + X86_VPSUBQZ128rmkz = 13471, + X86_VPSUBQZ128rr = 13472, + X86_VPSUBQZ128rrk = 13473, + X86_VPSUBQZ128rrkz = 13474, + X86_VPSUBQZ256rm = 13475, + X86_VPSUBQZ256rmb = 13476, + X86_VPSUBQZ256rmbk = 13477, + X86_VPSUBQZ256rmbkz = 13478, + X86_VPSUBQZ256rmk = 13479, + X86_VPSUBQZ256rmkz = 13480, + X86_VPSUBQZ256rr = 13481, + X86_VPSUBQZ256rrk = 13482, + X86_VPSUBQZ256rrkz = 13483, + X86_VPSUBQZrm = 13484, + X86_VPSUBQZrmb = 13485, + X86_VPSUBQZrmbk = 13486, + X86_VPSUBQZrmbkz = 13487, + X86_VPSUBQZrmk = 13488, + X86_VPSUBQZrmkz = 13489, + X86_VPSUBQZrr = 13490, + X86_VPSUBQZrrk = 13491, + X86_VPSUBQZrrkz = 13492, + X86_VPSUBQrm = 13493, + X86_VPSUBQrr = 13494, + X86_VPSUBSBYrm = 13495, + X86_VPSUBSBYrr = 13496, + X86_VPSUBSBZ128rm = 13497, + X86_VPSUBSBZ128rmk = 13498, + X86_VPSUBSBZ128rmkz = 13499, + X86_VPSUBSBZ128rr = 13500, + X86_VPSUBSBZ128rrk = 13501, + X86_VPSUBSBZ128rrkz = 13502, + X86_VPSUBSBZ256rm = 13503, + X86_VPSUBSBZ256rmk = 13504, + X86_VPSUBSBZ256rmkz = 13505, + X86_VPSUBSBZ256rr = 13506, + X86_VPSUBSBZ256rrk = 13507, + X86_VPSUBSBZ256rrkz = 13508, + X86_VPSUBSBZrm = 13509, + X86_VPSUBSBZrmk = 13510, + X86_VPSUBSBZrmkz = 13511, + X86_VPSUBSBZrr = 13512, + X86_VPSUBSBZrrk = 13513, + X86_VPSUBSBZrrkz = 13514, + X86_VPSUBSBrm = 13515, + X86_VPSUBSBrr = 13516, + X86_VPSUBSWYrm = 13517, + X86_VPSUBSWYrr = 13518, + X86_VPSUBSWZ128rm = 13519, + X86_VPSUBSWZ128rmk = 13520, + X86_VPSUBSWZ128rmkz = 13521, + X86_VPSUBSWZ128rr = 13522, + X86_VPSUBSWZ128rrk = 13523, + X86_VPSUBSWZ128rrkz = 13524, + X86_VPSUBSWZ256rm = 13525, + X86_VPSUBSWZ256rmk = 13526, + X86_VPSUBSWZ256rmkz = 13527, + X86_VPSUBSWZ256rr = 13528, + X86_VPSUBSWZ256rrk = 13529, + X86_VPSUBSWZ256rrkz = 13530, + X86_VPSUBSWZrm = 13531, + X86_VPSUBSWZrmk = 13532, + X86_VPSUBSWZrmkz = 13533, + X86_VPSUBSWZrr = 13534, + X86_VPSUBSWZrrk = 13535, + X86_VPSUBSWZrrkz = 13536, + X86_VPSUBSWrm = 13537, + X86_VPSUBSWrr = 13538, + X86_VPSUBUSBYrm = 13539, + X86_VPSUBUSBYrr = 13540, + X86_VPSUBUSBZ128rm = 13541, + X86_VPSUBUSBZ128rmk = 13542, + X86_VPSUBUSBZ128rmkz = 13543, + X86_VPSUBUSBZ128rr = 13544, + X86_VPSUBUSBZ128rrk = 13545, + X86_VPSUBUSBZ128rrkz = 13546, + X86_VPSUBUSBZ256rm = 13547, + X86_VPSUBUSBZ256rmk = 13548, + X86_VPSUBUSBZ256rmkz = 13549, + X86_VPSUBUSBZ256rr = 13550, + X86_VPSUBUSBZ256rrk = 13551, + X86_VPSUBUSBZ256rrkz = 13552, + X86_VPSUBUSBZrm = 13553, + X86_VPSUBUSBZrmk = 13554, + X86_VPSUBUSBZrmkz = 13555, + X86_VPSUBUSBZrr = 13556, + X86_VPSUBUSBZrrk = 13557, + X86_VPSUBUSBZrrkz = 13558, + X86_VPSUBUSBrm = 13559, + X86_VPSUBUSBrr = 13560, + X86_VPSUBUSWYrm = 13561, + X86_VPSUBUSWYrr = 13562, + X86_VPSUBUSWZ128rm = 13563, + X86_VPSUBUSWZ128rmk = 13564, + X86_VPSUBUSWZ128rmkz = 13565, + X86_VPSUBUSWZ128rr = 13566, + X86_VPSUBUSWZ128rrk = 13567, + X86_VPSUBUSWZ128rrkz = 13568, + X86_VPSUBUSWZ256rm = 13569, + X86_VPSUBUSWZ256rmk = 13570, + X86_VPSUBUSWZ256rmkz = 13571, + X86_VPSUBUSWZ256rr = 13572, + X86_VPSUBUSWZ256rrk = 13573, + X86_VPSUBUSWZ256rrkz = 13574, + X86_VPSUBUSWZrm = 13575, + X86_VPSUBUSWZrmk = 13576, + X86_VPSUBUSWZrmkz = 13577, + X86_VPSUBUSWZrr = 13578, + X86_VPSUBUSWZrrk = 13579, + X86_VPSUBUSWZrrkz = 13580, + X86_VPSUBUSWrm = 13581, + X86_VPSUBUSWrr = 13582, + X86_VPSUBWYrm = 13583, + X86_VPSUBWYrr = 13584, + X86_VPSUBWZ128rm = 13585, + X86_VPSUBWZ128rmk = 13586, + X86_VPSUBWZ128rmkz = 13587, + X86_VPSUBWZ128rr = 13588, + X86_VPSUBWZ128rrk = 13589, + X86_VPSUBWZ128rrkz = 13590, + X86_VPSUBWZ256rm = 13591, + X86_VPSUBWZ256rmk = 13592, + X86_VPSUBWZ256rmkz = 13593, + X86_VPSUBWZ256rr = 13594, + X86_VPSUBWZ256rrk = 13595, + X86_VPSUBWZ256rrkz = 13596, + X86_VPSUBWZrm = 13597, + X86_VPSUBWZrmk = 13598, + X86_VPSUBWZrmkz = 13599, + X86_VPSUBWZrr = 13600, + X86_VPSUBWZrrk = 13601, + X86_VPSUBWZrrkz = 13602, + X86_VPSUBWrm = 13603, + X86_VPSUBWrr = 13604, + X86_VPTERNLOGDZ128rmbi = 13605, + X86_VPTERNLOGDZ128rmbik = 13606, + X86_VPTERNLOGDZ128rmbikz = 13607, + X86_VPTERNLOGDZ128rmi = 13608, + X86_VPTERNLOGDZ128rmik = 13609, + X86_VPTERNLOGDZ128rmikz = 13610, + X86_VPTERNLOGDZ128rri = 13611, + X86_VPTERNLOGDZ128rrik = 13612, + X86_VPTERNLOGDZ128rrikz = 13613, + X86_VPTERNLOGDZ256rmbi = 13614, + X86_VPTERNLOGDZ256rmbik = 13615, + X86_VPTERNLOGDZ256rmbikz = 13616, + X86_VPTERNLOGDZ256rmi = 13617, + X86_VPTERNLOGDZ256rmik = 13618, + X86_VPTERNLOGDZ256rmikz = 13619, + X86_VPTERNLOGDZ256rri = 13620, + X86_VPTERNLOGDZ256rrik = 13621, + X86_VPTERNLOGDZ256rrikz = 13622, + X86_VPTERNLOGDZrmbi = 13623, + X86_VPTERNLOGDZrmbik = 13624, + X86_VPTERNLOGDZrmbikz = 13625, + X86_VPTERNLOGDZrmi = 13626, + X86_VPTERNLOGDZrmik = 13627, + X86_VPTERNLOGDZrmikz = 13628, + X86_VPTERNLOGDZrri = 13629, + X86_VPTERNLOGDZrrik = 13630, + X86_VPTERNLOGDZrrikz = 13631, + X86_VPTERNLOGQZ128rmbi = 13632, + X86_VPTERNLOGQZ128rmbik = 13633, + X86_VPTERNLOGQZ128rmbikz = 13634, + X86_VPTERNLOGQZ128rmi = 13635, + X86_VPTERNLOGQZ128rmik = 13636, + X86_VPTERNLOGQZ128rmikz = 13637, + X86_VPTERNLOGQZ128rri = 13638, + X86_VPTERNLOGQZ128rrik = 13639, + X86_VPTERNLOGQZ128rrikz = 13640, + X86_VPTERNLOGQZ256rmbi = 13641, + X86_VPTERNLOGQZ256rmbik = 13642, + X86_VPTERNLOGQZ256rmbikz = 13643, + X86_VPTERNLOGQZ256rmi = 13644, + X86_VPTERNLOGQZ256rmik = 13645, + X86_VPTERNLOGQZ256rmikz = 13646, + X86_VPTERNLOGQZ256rri = 13647, + X86_VPTERNLOGQZ256rrik = 13648, + X86_VPTERNLOGQZ256rrikz = 13649, + X86_VPTERNLOGQZrmbi = 13650, + X86_VPTERNLOGQZrmbik = 13651, + X86_VPTERNLOGQZrmbikz = 13652, + X86_VPTERNLOGQZrmi = 13653, + X86_VPTERNLOGQZrmik = 13654, + X86_VPTERNLOGQZrmikz = 13655, + X86_VPTERNLOGQZrri = 13656, + X86_VPTERNLOGQZrrik = 13657, + X86_VPTERNLOGQZrrikz = 13658, + X86_VPTESTMBZ128rm = 13659, + X86_VPTESTMBZ128rmk = 13660, + X86_VPTESTMBZ128rr = 13661, + X86_VPTESTMBZ128rrk = 13662, + X86_VPTESTMBZ256rm = 13663, + X86_VPTESTMBZ256rmk = 13664, + X86_VPTESTMBZ256rr = 13665, + X86_VPTESTMBZ256rrk = 13666, + X86_VPTESTMBZrm = 13667, + X86_VPTESTMBZrmk = 13668, + X86_VPTESTMBZrr = 13669, + X86_VPTESTMBZrrk = 13670, + X86_VPTESTMDZ128rm = 13671, + X86_VPTESTMDZ128rmb = 13672, + X86_VPTESTMDZ128rmbk = 13673, + X86_VPTESTMDZ128rmk = 13674, + X86_VPTESTMDZ128rr = 13675, + X86_VPTESTMDZ128rrk = 13676, + X86_VPTESTMDZ256rm = 13677, + X86_VPTESTMDZ256rmb = 13678, + X86_VPTESTMDZ256rmbk = 13679, + X86_VPTESTMDZ256rmk = 13680, + X86_VPTESTMDZ256rr = 13681, + X86_VPTESTMDZ256rrk = 13682, + X86_VPTESTMDZrm = 13683, + X86_VPTESTMDZrmb = 13684, + X86_VPTESTMDZrmbk = 13685, + X86_VPTESTMDZrmk = 13686, + X86_VPTESTMDZrr = 13687, + X86_VPTESTMDZrrk = 13688, + X86_VPTESTMQZ128rm = 13689, + X86_VPTESTMQZ128rmb = 13690, + X86_VPTESTMQZ128rmbk = 13691, + X86_VPTESTMQZ128rmk = 13692, + X86_VPTESTMQZ128rr = 13693, + X86_VPTESTMQZ128rrk = 13694, + X86_VPTESTMQZ256rm = 13695, + X86_VPTESTMQZ256rmb = 13696, + X86_VPTESTMQZ256rmbk = 13697, + X86_VPTESTMQZ256rmk = 13698, + X86_VPTESTMQZ256rr = 13699, + X86_VPTESTMQZ256rrk = 13700, + X86_VPTESTMQZrm = 13701, + X86_VPTESTMQZrmb = 13702, + X86_VPTESTMQZrmbk = 13703, + X86_VPTESTMQZrmk = 13704, + X86_VPTESTMQZrr = 13705, + X86_VPTESTMQZrrk = 13706, + X86_VPTESTMWZ128rm = 13707, + X86_VPTESTMWZ128rmk = 13708, + X86_VPTESTMWZ128rr = 13709, + X86_VPTESTMWZ128rrk = 13710, + X86_VPTESTMWZ256rm = 13711, + X86_VPTESTMWZ256rmk = 13712, + X86_VPTESTMWZ256rr = 13713, + X86_VPTESTMWZ256rrk = 13714, + X86_VPTESTMWZrm = 13715, + X86_VPTESTMWZrmk = 13716, + X86_VPTESTMWZrr = 13717, + X86_VPTESTMWZrrk = 13718, + X86_VPTESTNMBZ128rm = 13719, + X86_VPTESTNMBZ128rmk = 13720, + X86_VPTESTNMBZ128rr = 13721, + X86_VPTESTNMBZ128rrk = 13722, + X86_VPTESTNMBZ256rm = 13723, + X86_VPTESTNMBZ256rmk = 13724, + X86_VPTESTNMBZ256rr = 13725, + X86_VPTESTNMBZ256rrk = 13726, + X86_VPTESTNMBZrm = 13727, + X86_VPTESTNMBZrmk = 13728, + X86_VPTESTNMBZrr = 13729, + X86_VPTESTNMBZrrk = 13730, + X86_VPTESTNMDZ128rm = 13731, + X86_VPTESTNMDZ128rmb = 13732, + X86_VPTESTNMDZ128rmbk = 13733, + X86_VPTESTNMDZ128rmk = 13734, + X86_VPTESTNMDZ128rr = 13735, + X86_VPTESTNMDZ128rrk = 13736, + X86_VPTESTNMDZ256rm = 13737, + X86_VPTESTNMDZ256rmb = 13738, + X86_VPTESTNMDZ256rmbk = 13739, + X86_VPTESTNMDZ256rmk = 13740, + X86_VPTESTNMDZ256rr = 13741, + X86_VPTESTNMDZ256rrk = 13742, + X86_VPTESTNMDZrm = 13743, + X86_VPTESTNMDZrmb = 13744, + X86_VPTESTNMDZrmbk = 13745, + X86_VPTESTNMDZrmk = 13746, + X86_VPTESTNMDZrr = 13747, + X86_VPTESTNMDZrrk = 13748, + X86_VPTESTNMQZ128rm = 13749, + X86_VPTESTNMQZ128rmb = 13750, + X86_VPTESTNMQZ128rmbk = 13751, + X86_VPTESTNMQZ128rmk = 13752, + X86_VPTESTNMQZ128rr = 13753, + X86_VPTESTNMQZ128rrk = 13754, + X86_VPTESTNMQZ256rm = 13755, + X86_VPTESTNMQZ256rmb = 13756, + X86_VPTESTNMQZ256rmbk = 13757, + X86_VPTESTNMQZ256rmk = 13758, + X86_VPTESTNMQZ256rr = 13759, + X86_VPTESTNMQZ256rrk = 13760, + X86_VPTESTNMQZrm = 13761, + X86_VPTESTNMQZrmb = 13762, + X86_VPTESTNMQZrmbk = 13763, + X86_VPTESTNMQZrmk = 13764, + X86_VPTESTNMQZrr = 13765, + X86_VPTESTNMQZrrk = 13766, + X86_VPTESTNMWZ128rm = 13767, + X86_VPTESTNMWZ128rmk = 13768, + X86_VPTESTNMWZ128rr = 13769, + X86_VPTESTNMWZ128rrk = 13770, + X86_VPTESTNMWZ256rm = 13771, + X86_VPTESTNMWZ256rmk = 13772, + X86_VPTESTNMWZ256rr = 13773, + X86_VPTESTNMWZ256rrk = 13774, + X86_VPTESTNMWZrm = 13775, + X86_VPTESTNMWZrmk = 13776, + X86_VPTESTNMWZrr = 13777, + X86_VPTESTNMWZrrk = 13778, + X86_VPTESTYrm = 13779, + X86_VPTESTYrr = 13780, + X86_VPTESTrm = 13781, + X86_VPTESTrr = 13782, + X86_VPUNPCKHBWYrm = 13783, + X86_VPUNPCKHBWYrr = 13784, + X86_VPUNPCKHBWZ128rm = 13785, + X86_VPUNPCKHBWZ128rmk = 13786, + X86_VPUNPCKHBWZ128rmkz = 13787, + X86_VPUNPCKHBWZ128rr = 13788, + X86_VPUNPCKHBWZ128rrk = 13789, + X86_VPUNPCKHBWZ128rrkz = 13790, + X86_VPUNPCKHBWZ256rm = 13791, + X86_VPUNPCKHBWZ256rmk = 13792, + X86_VPUNPCKHBWZ256rmkz = 13793, + X86_VPUNPCKHBWZ256rr = 13794, + X86_VPUNPCKHBWZ256rrk = 13795, + X86_VPUNPCKHBWZ256rrkz = 13796, + X86_VPUNPCKHBWZrm = 13797, + X86_VPUNPCKHBWZrmk = 13798, + X86_VPUNPCKHBWZrmkz = 13799, + X86_VPUNPCKHBWZrr = 13800, + X86_VPUNPCKHBWZrrk = 13801, + X86_VPUNPCKHBWZrrkz = 13802, + X86_VPUNPCKHBWrm = 13803, + X86_VPUNPCKHBWrr = 13804, + X86_VPUNPCKHDQYrm = 13805, + X86_VPUNPCKHDQYrr = 13806, + X86_VPUNPCKHDQZ128rm = 13807, + X86_VPUNPCKHDQZ128rmb = 13808, + X86_VPUNPCKHDQZ128rmbk = 13809, + X86_VPUNPCKHDQZ128rmbkz = 13810, + X86_VPUNPCKHDQZ128rmk = 13811, + X86_VPUNPCKHDQZ128rmkz = 13812, + X86_VPUNPCKHDQZ128rr = 13813, + X86_VPUNPCKHDQZ128rrk = 13814, + X86_VPUNPCKHDQZ128rrkz = 13815, + X86_VPUNPCKHDQZ256rm = 13816, + X86_VPUNPCKHDQZ256rmb = 13817, + X86_VPUNPCKHDQZ256rmbk = 13818, + X86_VPUNPCKHDQZ256rmbkz = 13819, + X86_VPUNPCKHDQZ256rmk = 13820, + X86_VPUNPCKHDQZ256rmkz = 13821, + X86_VPUNPCKHDQZ256rr = 13822, + X86_VPUNPCKHDQZ256rrk = 13823, + X86_VPUNPCKHDQZ256rrkz = 13824, + X86_VPUNPCKHDQZrm = 13825, + X86_VPUNPCKHDQZrmb = 13826, + X86_VPUNPCKHDQZrmbk = 13827, + X86_VPUNPCKHDQZrmbkz = 13828, + X86_VPUNPCKHDQZrmk = 13829, + X86_VPUNPCKHDQZrmkz = 13830, + X86_VPUNPCKHDQZrr = 13831, + X86_VPUNPCKHDQZrrk = 13832, + X86_VPUNPCKHDQZrrkz = 13833, + X86_VPUNPCKHDQrm = 13834, + X86_VPUNPCKHDQrr = 13835, + X86_VPUNPCKHQDQYrm = 13836, + X86_VPUNPCKHQDQYrr = 13837, + X86_VPUNPCKHQDQZ128rm = 13838, + X86_VPUNPCKHQDQZ128rmb = 13839, + X86_VPUNPCKHQDQZ128rmbk = 13840, + X86_VPUNPCKHQDQZ128rmbkz = 13841, + X86_VPUNPCKHQDQZ128rmk = 13842, + X86_VPUNPCKHQDQZ128rmkz = 13843, + X86_VPUNPCKHQDQZ128rr = 13844, + X86_VPUNPCKHQDQZ128rrk = 13845, + X86_VPUNPCKHQDQZ128rrkz = 13846, + X86_VPUNPCKHQDQZ256rm = 13847, + X86_VPUNPCKHQDQZ256rmb = 13848, + X86_VPUNPCKHQDQZ256rmbk = 13849, + X86_VPUNPCKHQDQZ256rmbkz = 13850, + X86_VPUNPCKHQDQZ256rmk = 13851, + X86_VPUNPCKHQDQZ256rmkz = 13852, + X86_VPUNPCKHQDQZ256rr = 13853, + X86_VPUNPCKHQDQZ256rrk = 13854, + X86_VPUNPCKHQDQZ256rrkz = 13855, + X86_VPUNPCKHQDQZrm = 13856, + X86_VPUNPCKHQDQZrmb = 13857, + X86_VPUNPCKHQDQZrmbk = 13858, + X86_VPUNPCKHQDQZrmbkz = 13859, + X86_VPUNPCKHQDQZrmk = 13860, + X86_VPUNPCKHQDQZrmkz = 13861, + X86_VPUNPCKHQDQZrr = 13862, + X86_VPUNPCKHQDQZrrk = 13863, + X86_VPUNPCKHQDQZrrkz = 13864, + X86_VPUNPCKHQDQrm = 13865, + X86_VPUNPCKHQDQrr = 13866, + X86_VPUNPCKHWDYrm = 13867, + X86_VPUNPCKHWDYrr = 13868, + X86_VPUNPCKHWDZ128rm = 13869, + X86_VPUNPCKHWDZ128rmk = 13870, + X86_VPUNPCKHWDZ128rmkz = 13871, + X86_VPUNPCKHWDZ128rr = 13872, + X86_VPUNPCKHWDZ128rrk = 13873, + X86_VPUNPCKHWDZ128rrkz = 13874, + X86_VPUNPCKHWDZ256rm = 13875, + X86_VPUNPCKHWDZ256rmk = 13876, + X86_VPUNPCKHWDZ256rmkz = 13877, + X86_VPUNPCKHWDZ256rr = 13878, + X86_VPUNPCKHWDZ256rrk = 13879, + X86_VPUNPCKHWDZ256rrkz = 13880, + X86_VPUNPCKHWDZrm = 13881, + X86_VPUNPCKHWDZrmk = 13882, + X86_VPUNPCKHWDZrmkz = 13883, + X86_VPUNPCKHWDZrr = 13884, + X86_VPUNPCKHWDZrrk = 13885, + X86_VPUNPCKHWDZrrkz = 13886, + X86_VPUNPCKHWDrm = 13887, + X86_VPUNPCKHWDrr = 13888, + X86_VPUNPCKLBWYrm = 13889, + X86_VPUNPCKLBWYrr = 13890, + X86_VPUNPCKLBWZ128rm = 13891, + X86_VPUNPCKLBWZ128rmk = 13892, + X86_VPUNPCKLBWZ128rmkz = 13893, + X86_VPUNPCKLBWZ128rr = 13894, + X86_VPUNPCKLBWZ128rrk = 13895, + X86_VPUNPCKLBWZ128rrkz = 13896, + X86_VPUNPCKLBWZ256rm = 13897, + X86_VPUNPCKLBWZ256rmk = 13898, + X86_VPUNPCKLBWZ256rmkz = 13899, + X86_VPUNPCKLBWZ256rr = 13900, + X86_VPUNPCKLBWZ256rrk = 13901, + X86_VPUNPCKLBWZ256rrkz = 13902, + X86_VPUNPCKLBWZrm = 13903, + X86_VPUNPCKLBWZrmk = 13904, + X86_VPUNPCKLBWZrmkz = 13905, + X86_VPUNPCKLBWZrr = 13906, + X86_VPUNPCKLBWZrrk = 13907, + X86_VPUNPCKLBWZrrkz = 13908, + X86_VPUNPCKLBWrm = 13909, + X86_VPUNPCKLBWrr = 13910, + X86_VPUNPCKLDQYrm = 13911, + X86_VPUNPCKLDQYrr = 13912, + X86_VPUNPCKLDQZ128rm = 13913, + X86_VPUNPCKLDQZ128rmb = 13914, + X86_VPUNPCKLDQZ128rmbk = 13915, + X86_VPUNPCKLDQZ128rmbkz = 13916, + X86_VPUNPCKLDQZ128rmk = 13917, + X86_VPUNPCKLDQZ128rmkz = 13918, + X86_VPUNPCKLDQZ128rr = 13919, + X86_VPUNPCKLDQZ128rrk = 13920, + X86_VPUNPCKLDQZ128rrkz = 13921, + X86_VPUNPCKLDQZ256rm = 13922, + X86_VPUNPCKLDQZ256rmb = 13923, + X86_VPUNPCKLDQZ256rmbk = 13924, + X86_VPUNPCKLDQZ256rmbkz = 13925, + X86_VPUNPCKLDQZ256rmk = 13926, + X86_VPUNPCKLDQZ256rmkz = 13927, + X86_VPUNPCKLDQZ256rr = 13928, + X86_VPUNPCKLDQZ256rrk = 13929, + X86_VPUNPCKLDQZ256rrkz = 13930, + X86_VPUNPCKLDQZrm = 13931, + X86_VPUNPCKLDQZrmb = 13932, + X86_VPUNPCKLDQZrmbk = 13933, + X86_VPUNPCKLDQZrmbkz = 13934, + X86_VPUNPCKLDQZrmk = 13935, + X86_VPUNPCKLDQZrmkz = 13936, + X86_VPUNPCKLDQZrr = 13937, + X86_VPUNPCKLDQZrrk = 13938, + X86_VPUNPCKLDQZrrkz = 13939, + X86_VPUNPCKLDQrm = 13940, + X86_VPUNPCKLDQrr = 13941, + X86_VPUNPCKLQDQYrm = 13942, + X86_VPUNPCKLQDQYrr = 13943, + X86_VPUNPCKLQDQZ128rm = 13944, + X86_VPUNPCKLQDQZ128rmb = 13945, + X86_VPUNPCKLQDQZ128rmbk = 13946, + X86_VPUNPCKLQDQZ128rmbkz = 13947, + X86_VPUNPCKLQDQZ128rmk = 13948, + X86_VPUNPCKLQDQZ128rmkz = 13949, + X86_VPUNPCKLQDQZ128rr = 13950, + X86_VPUNPCKLQDQZ128rrk = 13951, + X86_VPUNPCKLQDQZ128rrkz = 13952, + X86_VPUNPCKLQDQZ256rm = 13953, + X86_VPUNPCKLQDQZ256rmb = 13954, + X86_VPUNPCKLQDQZ256rmbk = 13955, + X86_VPUNPCKLQDQZ256rmbkz = 13956, + X86_VPUNPCKLQDQZ256rmk = 13957, + X86_VPUNPCKLQDQZ256rmkz = 13958, + X86_VPUNPCKLQDQZ256rr = 13959, + X86_VPUNPCKLQDQZ256rrk = 13960, + X86_VPUNPCKLQDQZ256rrkz = 13961, + X86_VPUNPCKLQDQZrm = 13962, + X86_VPUNPCKLQDQZrmb = 13963, + X86_VPUNPCKLQDQZrmbk = 13964, + X86_VPUNPCKLQDQZrmbkz = 13965, + X86_VPUNPCKLQDQZrmk = 13966, + X86_VPUNPCKLQDQZrmkz = 13967, + X86_VPUNPCKLQDQZrr = 13968, + X86_VPUNPCKLQDQZrrk = 13969, + X86_VPUNPCKLQDQZrrkz = 13970, + X86_VPUNPCKLQDQrm = 13971, + X86_VPUNPCKLQDQrr = 13972, + X86_VPUNPCKLWDYrm = 13973, + X86_VPUNPCKLWDYrr = 13974, + X86_VPUNPCKLWDZ128rm = 13975, + X86_VPUNPCKLWDZ128rmk = 13976, + X86_VPUNPCKLWDZ128rmkz = 13977, + X86_VPUNPCKLWDZ128rr = 13978, + X86_VPUNPCKLWDZ128rrk = 13979, + X86_VPUNPCKLWDZ128rrkz = 13980, + X86_VPUNPCKLWDZ256rm = 13981, + X86_VPUNPCKLWDZ256rmk = 13982, + X86_VPUNPCKLWDZ256rmkz = 13983, + X86_VPUNPCKLWDZ256rr = 13984, + X86_VPUNPCKLWDZ256rrk = 13985, + X86_VPUNPCKLWDZ256rrkz = 13986, + X86_VPUNPCKLWDZrm = 13987, + X86_VPUNPCKLWDZrmk = 13988, + X86_VPUNPCKLWDZrmkz = 13989, + X86_VPUNPCKLWDZrr = 13990, + X86_VPUNPCKLWDZrrk = 13991, + X86_VPUNPCKLWDZrrkz = 13992, + X86_VPUNPCKLWDrm = 13993, + X86_VPUNPCKLWDrr = 13994, + X86_VPXORDZ128rm = 13995, + X86_VPXORDZ128rmb = 13996, + X86_VPXORDZ128rmbk = 13997, + X86_VPXORDZ128rmbkz = 13998, + X86_VPXORDZ128rmk = 13999, + X86_VPXORDZ128rmkz = 14000, + X86_VPXORDZ128rr = 14001, + X86_VPXORDZ128rrk = 14002, + X86_VPXORDZ128rrkz = 14003, + X86_VPXORDZ256rm = 14004, + X86_VPXORDZ256rmb = 14005, + X86_VPXORDZ256rmbk = 14006, + X86_VPXORDZ256rmbkz = 14007, + X86_VPXORDZ256rmk = 14008, + X86_VPXORDZ256rmkz = 14009, + X86_VPXORDZ256rr = 14010, + X86_VPXORDZ256rrk = 14011, + X86_VPXORDZ256rrkz = 14012, + X86_VPXORDZrm = 14013, + X86_VPXORDZrmb = 14014, + X86_VPXORDZrmbk = 14015, + X86_VPXORDZrmbkz = 14016, + X86_VPXORDZrmk = 14017, + X86_VPXORDZrmkz = 14018, + X86_VPXORDZrr = 14019, + X86_VPXORDZrrk = 14020, + X86_VPXORDZrrkz = 14021, + X86_VPXORQZ128rm = 14022, + X86_VPXORQZ128rmb = 14023, + X86_VPXORQZ128rmbk = 14024, + X86_VPXORQZ128rmbkz = 14025, + X86_VPXORQZ128rmk = 14026, + X86_VPXORQZ128rmkz = 14027, + X86_VPXORQZ128rr = 14028, + X86_VPXORQZ128rrk = 14029, + X86_VPXORQZ128rrkz = 14030, + X86_VPXORQZ256rm = 14031, + X86_VPXORQZ256rmb = 14032, + X86_VPXORQZ256rmbk = 14033, + X86_VPXORQZ256rmbkz = 14034, + X86_VPXORQZ256rmk = 14035, + X86_VPXORQZ256rmkz = 14036, + X86_VPXORQZ256rr = 14037, + X86_VPXORQZ256rrk = 14038, + X86_VPXORQZ256rrkz = 14039, + X86_VPXORQZrm = 14040, + X86_VPXORQZrmb = 14041, + X86_VPXORQZrmbk = 14042, + X86_VPXORQZrmbkz = 14043, + X86_VPXORQZrmk = 14044, + X86_VPXORQZrmkz = 14045, + X86_VPXORQZrr = 14046, + X86_VPXORQZrrk = 14047, + X86_VPXORQZrrkz = 14048, + X86_VPXORYrm = 14049, + X86_VPXORYrr = 14050, + X86_VPXORrm = 14051, + X86_VPXORrr = 14052, + X86_VRANGEPDZ128rmbi = 14053, + X86_VRANGEPDZ128rmbik = 14054, + X86_VRANGEPDZ128rmbikz = 14055, + X86_VRANGEPDZ128rmi = 14056, + X86_VRANGEPDZ128rmik = 14057, + X86_VRANGEPDZ128rmikz = 14058, + X86_VRANGEPDZ128rri = 14059, + X86_VRANGEPDZ128rrik = 14060, + X86_VRANGEPDZ128rrikz = 14061, + X86_VRANGEPDZ256rmbi = 14062, + X86_VRANGEPDZ256rmbik = 14063, + X86_VRANGEPDZ256rmbikz = 14064, + X86_VRANGEPDZ256rmi = 14065, + X86_VRANGEPDZ256rmik = 14066, + X86_VRANGEPDZ256rmikz = 14067, + X86_VRANGEPDZ256rri = 14068, + X86_VRANGEPDZ256rrik = 14069, + X86_VRANGEPDZ256rrikz = 14070, + X86_VRANGEPDZrmbi = 14071, + X86_VRANGEPDZrmbik = 14072, + X86_VRANGEPDZrmbikz = 14073, + X86_VRANGEPDZrmi = 14074, + X86_VRANGEPDZrmik = 14075, + X86_VRANGEPDZrmikz = 14076, + X86_VRANGEPDZrri = 14077, + X86_VRANGEPDZrrib = 14078, + X86_VRANGEPDZrribk = 14079, + X86_VRANGEPDZrribkz = 14080, + X86_VRANGEPDZrrik = 14081, + X86_VRANGEPDZrrikz = 14082, + X86_VRANGEPSZ128rmbi = 14083, + X86_VRANGEPSZ128rmbik = 14084, + X86_VRANGEPSZ128rmbikz = 14085, + X86_VRANGEPSZ128rmi = 14086, + X86_VRANGEPSZ128rmik = 14087, + X86_VRANGEPSZ128rmikz = 14088, + X86_VRANGEPSZ128rri = 14089, + X86_VRANGEPSZ128rrik = 14090, + X86_VRANGEPSZ128rrikz = 14091, + X86_VRANGEPSZ256rmbi = 14092, + X86_VRANGEPSZ256rmbik = 14093, + X86_VRANGEPSZ256rmbikz = 14094, + X86_VRANGEPSZ256rmi = 14095, + X86_VRANGEPSZ256rmik = 14096, + X86_VRANGEPSZ256rmikz = 14097, + X86_VRANGEPSZ256rri = 14098, + X86_VRANGEPSZ256rrik = 14099, + X86_VRANGEPSZ256rrikz = 14100, + X86_VRANGEPSZrmbi = 14101, + X86_VRANGEPSZrmbik = 14102, + X86_VRANGEPSZrmbikz = 14103, + X86_VRANGEPSZrmi = 14104, + X86_VRANGEPSZrmik = 14105, + X86_VRANGEPSZrmikz = 14106, + X86_VRANGEPSZrri = 14107, + X86_VRANGEPSZrrib = 14108, + X86_VRANGEPSZrribk = 14109, + X86_VRANGEPSZrribkz = 14110, + X86_VRANGEPSZrrik = 14111, + X86_VRANGEPSZrrikz = 14112, + X86_VRANGESDZrmi = 14113, + X86_VRANGESDZrmik = 14114, + X86_VRANGESDZrmikz = 14115, + X86_VRANGESDZrri = 14116, + X86_VRANGESDZrrib = 14117, + X86_VRANGESDZrribk = 14118, + X86_VRANGESDZrribkz = 14119, + X86_VRANGESDZrrik = 14120, + X86_VRANGESDZrrikz = 14121, + X86_VRANGESSZrmi = 14122, + X86_VRANGESSZrmik = 14123, + X86_VRANGESSZrmikz = 14124, + X86_VRANGESSZrri = 14125, + X86_VRANGESSZrrib = 14126, + X86_VRANGESSZrribk = 14127, + X86_VRANGESSZrribkz = 14128, + X86_VRANGESSZrrik = 14129, + X86_VRANGESSZrrikz = 14130, + X86_VRCP14PDZ128m = 14131, + X86_VRCP14PDZ128mb = 14132, + X86_VRCP14PDZ128mbk = 14133, + X86_VRCP14PDZ128mbkz = 14134, + X86_VRCP14PDZ128mk = 14135, + X86_VRCP14PDZ128mkz = 14136, + X86_VRCP14PDZ128r = 14137, + X86_VRCP14PDZ128rk = 14138, + X86_VRCP14PDZ128rkz = 14139, + X86_VRCP14PDZ256m = 14140, + X86_VRCP14PDZ256mb = 14141, + X86_VRCP14PDZ256mbk = 14142, + X86_VRCP14PDZ256mbkz = 14143, + X86_VRCP14PDZ256mk = 14144, + X86_VRCP14PDZ256mkz = 14145, + X86_VRCP14PDZ256r = 14146, + X86_VRCP14PDZ256rk = 14147, + X86_VRCP14PDZ256rkz = 14148, + X86_VRCP14PDZm = 14149, + X86_VRCP14PDZmb = 14150, + X86_VRCP14PDZmbk = 14151, + X86_VRCP14PDZmbkz = 14152, + X86_VRCP14PDZmk = 14153, + X86_VRCP14PDZmkz = 14154, + X86_VRCP14PDZr = 14155, + X86_VRCP14PDZrk = 14156, + X86_VRCP14PDZrkz = 14157, + X86_VRCP14PSZ128m = 14158, + X86_VRCP14PSZ128mb = 14159, + X86_VRCP14PSZ128mbk = 14160, + X86_VRCP14PSZ128mbkz = 14161, + X86_VRCP14PSZ128mk = 14162, + X86_VRCP14PSZ128mkz = 14163, + X86_VRCP14PSZ128r = 14164, + X86_VRCP14PSZ128rk = 14165, + X86_VRCP14PSZ128rkz = 14166, + X86_VRCP14PSZ256m = 14167, + X86_VRCP14PSZ256mb = 14168, + X86_VRCP14PSZ256mbk = 14169, + X86_VRCP14PSZ256mbkz = 14170, + X86_VRCP14PSZ256mk = 14171, + X86_VRCP14PSZ256mkz = 14172, + X86_VRCP14PSZ256r = 14173, + X86_VRCP14PSZ256rk = 14174, + X86_VRCP14PSZ256rkz = 14175, + X86_VRCP14PSZm = 14176, + X86_VRCP14PSZmb = 14177, + X86_VRCP14PSZmbk = 14178, + X86_VRCP14PSZmbkz = 14179, + X86_VRCP14PSZmk = 14180, + X86_VRCP14PSZmkz = 14181, + X86_VRCP14PSZr = 14182, + X86_VRCP14PSZrk = 14183, + X86_VRCP14PSZrkz = 14184, + X86_VRCP14SDZrm = 14185, + X86_VRCP14SDZrmk = 14186, + X86_VRCP14SDZrmkz = 14187, + X86_VRCP14SDZrr = 14188, + X86_VRCP14SDZrrk = 14189, + X86_VRCP14SDZrrkz = 14190, + X86_VRCP14SSZrm = 14191, + X86_VRCP14SSZrmk = 14192, + X86_VRCP14SSZrmkz = 14193, + X86_VRCP14SSZrr = 14194, + X86_VRCP14SSZrrk = 14195, + X86_VRCP14SSZrrkz = 14196, + X86_VRCP28PDZm = 14197, + X86_VRCP28PDZmb = 14198, + X86_VRCP28PDZmbk = 14199, + X86_VRCP28PDZmbkz = 14200, + X86_VRCP28PDZmk = 14201, + X86_VRCP28PDZmkz = 14202, + X86_VRCP28PDZr = 14203, + X86_VRCP28PDZrb = 14204, + X86_VRCP28PDZrbk = 14205, + X86_VRCP28PDZrbkz = 14206, + X86_VRCP28PDZrk = 14207, + X86_VRCP28PDZrkz = 14208, + X86_VRCP28PSZm = 14209, + X86_VRCP28PSZmb = 14210, + X86_VRCP28PSZmbk = 14211, + X86_VRCP28PSZmbkz = 14212, + X86_VRCP28PSZmk = 14213, + X86_VRCP28PSZmkz = 14214, + X86_VRCP28PSZr = 14215, + X86_VRCP28PSZrb = 14216, + X86_VRCP28PSZrbk = 14217, + X86_VRCP28PSZrbkz = 14218, + X86_VRCP28PSZrk = 14219, + X86_VRCP28PSZrkz = 14220, + X86_VRCP28SDZm = 14221, + X86_VRCP28SDZmk = 14222, + X86_VRCP28SDZmkz = 14223, + X86_VRCP28SDZr = 14224, + X86_VRCP28SDZrb = 14225, + X86_VRCP28SDZrbk = 14226, + X86_VRCP28SDZrbkz = 14227, + X86_VRCP28SDZrk = 14228, + X86_VRCP28SDZrkz = 14229, + X86_VRCP28SSZm = 14230, + X86_VRCP28SSZmk = 14231, + X86_VRCP28SSZmkz = 14232, + X86_VRCP28SSZr = 14233, + X86_VRCP28SSZrb = 14234, + X86_VRCP28SSZrbk = 14235, + X86_VRCP28SSZrbkz = 14236, + X86_VRCP28SSZrk = 14237, + X86_VRCP28SSZrkz = 14238, + X86_VRCPPSYm = 14239, + X86_VRCPPSYr = 14240, + X86_VRCPPSm = 14241, + X86_VRCPPSr = 14242, + X86_VRCPSSm = 14243, + X86_VRCPSSm_Int = 14244, + X86_VRCPSSr = 14245, + X86_VRCPSSr_Int = 14246, + X86_VREDUCEPDZ128rmbi = 14247, + X86_VREDUCEPDZ128rmbik = 14248, + X86_VREDUCEPDZ128rmbikz = 14249, + X86_VREDUCEPDZ128rmi = 14250, + X86_VREDUCEPDZ128rmik = 14251, + X86_VREDUCEPDZ128rmikz = 14252, + X86_VREDUCEPDZ128rri = 14253, + X86_VREDUCEPDZ128rrik = 14254, + X86_VREDUCEPDZ128rrikz = 14255, + X86_VREDUCEPDZ256rmbi = 14256, + X86_VREDUCEPDZ256rmbik = 14257, + X86_VREDUCEPDZ256rmbikz = 14258, + X86_VREDUCEPDZ256rmi = 14259, + X86_VREDUCEPDZ256rmik = 14260, + X86_VREDUCEPDZ256rmikz = 14261, + X86_VREDUCEPDZ256rri = 14262, + X86_VREDUCEPDZ256rrik = 14263, + X86_VREDUCEPDZ256rrikz = 14264, + X86_VREDUCEPDZrmbi = 14265, + X86_VREDUCEPDZrmbik = 14266, + X86_VREDUCEPDZrmbikz = 14267, + X86_VREDUCEPDZrmi = 14268, + X86_VREDUCEPDZrmik = 14269, + X86_VREDUCEPDZrmikz = 14270, + X86_VREDUCEPDZrri = 14271, + X86_VREDUCEPDZrrib = 14272, + X86_VREDUCEPDZrribk = 14273, + X86_VREDUCEPDZrribkz = 14274, + X86_VREDUCEPDZrrik = 14275, + X86_VREDUCEPDZrrikz = 14276, + X86_VREDUCEPSZ128rmbi = 14277, + X86_VREDUCEPSZ128rmbik = 14278, + X86_VREDUCEPSZ128rmbikz = 14279, + X86_VREDUCEPSZ128rmi = 14280, + X86_VREDUCEPSZ128rmik = 14281, + X86_VREDUCEPSZ128rmikz = 14282, + X86_VREDUCEPSZ128rri = 14283, + X86_VREDUCEPSZ128rrik = 14284, + X86_VREDUCEPSZ128rrikz = 14285, + X86_VREDUCEPSZ256rmbi = 14286, + X86_VREDUCEPSZ256rmbik = 14287, + X86_VREDUCEPSZ256rmbikz = 14288, + X86_VREDUCEPSZ256rmi = 14289, + X86_VREDUCEPSZ256rmik = 14290, + X86_VREDUCEPSZ256rmikz = 14291, + X86_VREDUCEPSZ256rri = 14292, + X86_VREDUCEPSZ256rrik = 14293, + X86_VREDUCEPSZ256rrikz = 14294, + X86_VREDUCEPSZrmbi = 14295, + X86_VREDUCEPSZrmbik = 14296, + X86_VREDUCEPSZrmbikz = 14297, + X86_VREDUCEPSZrmi = 14298, + X86_VREDUCEPSZrmik = 14299, + X86_VREDUCEPSZrmikz = 14300, + X86_VREDUCEPSZrri = 14301, + X86_VREDUCEPSZrrib = 14302, + X86_VREDUCEPSZrribk = 14303, + X86_VREDUCEPSZrribkz = 14304, + X86_VREDUCEPSZrrik = 14305, + X86_VREDUCEPSZrrikz = 14306, + X86_VREDUCESDZrmi = 14307, + X86_VREDUCESDZrmik = 14308, + X86_VREDUCESDZrmikz = 14309, + X86_VREDUCESDZrri = 14310, + X86_VREDUCESDZrrib = 14311, + X86_VREDUCESDZrribk = 14312, + X86_VREDUCESDZrribkz = 14313, + X86_VREDUCESDZrrik = 14314, + X86_VREDUCESDZrrikz = 14315, + X86_VREDUCESSZrmi = 14316, + X86_VREDUCESSZrmik = 14317, + X86_VREDUCESSZrmikz = 14318, + X86_VREDUCESSZrri = 14319, + X86_VREDUCESSZrrib = 14320, + X86_VREDUCESSZrribk = 14321, + X86_VREDUCESSZrribkz = 14322, + X86_VREDUCESSZrrik = 14323, + X86_VREDUCESSZrrikz = 14324, + X86_VRNDSCALEPDZ128rmbi = 14325, + X86_VRNDSCALEPDZ128rmbik = 14326, + X86_VRNDSCALEPDZ128rmbikz = 14327, + X86_VRNDSCALEPDZ128rmi = 14328, + X86_VRNDSCALEPDZ128rmik = 14329, + X86_VRNDSCALEPDZ128rmikz = 14330, + X86_VRNDSCALEPDZ128rri = 14331, + X86_VRNDSCALEPDZ128rrik = 14332, + X86_VRNDSCALEPDZ128rrikz = 14333, + X86_VRNDSCALEPDZ256rmbi = 14334, + X86_VRNDSCALEPDZ256rmbik = 14335, + X86_VRNDSCALEPDZ256rmbikz = 14336, + X86_VRNDSCALEPDZ256rmi = 14337, + X86_VRNDSCALEPDZ256rmik = 14338, + X86_VRNDSCALEPDZ256rmikz = 14339, + X86_VRNDSCALEPDZ256rri = 14340, + X86_VRNDSCALEPDZ256rrik = 14341, + X86_VRNDSCALEPDZ256rrikz = 14342, + X86_VRNDSCALEPDZrmbi = 14343, + X86_VRNDSCALEPDZrmbik = 14344, + X86_VRNDSCALEPDZrmbikz = 14345, + X86_VRNDSCALEPDZrmi = 14346, + X86_VRNDSCALEPDZrmik = 14347, + X86_VRNDSCALEPDZrmikz = 14348, + X86_VRNDSCALEPDZrri = 14349, + X86_VRNDSCALEPDZrrib = 14350, + X86_VRNDSCALEPDZrribk = 14351, + X86_VRNDSCALEPDZrribkz = 14352, + X86_VRNDSCALEPDZrrik = 14353, + X86_VRNDSCALEPDZrrikz = 14354, + X86_VRNDSCALEPSZ128rmbi = 14355, + X86_VRNDSCALEPSZ128rmbik = 14356, + X86_VRNDSCALEPSZ128rmbikz = 14357, + X86_VRNDSCALEPSZ128rmi = 14358, + X86_VRNDSCALEPSZ128rmik = 14359, + X86_VRNDSCALEPSZ128rmikz = 14360, + X86_VRNDSCALEPSZ128rri = 14361, + X86_VRNDSCALEPSZ128rrik = 14362, + X86_VRNDSCALEPSZ128rrikz = 14363, + X86_VRNDSCALEPSZ256rmbi = 14364, + X86_VRNDSCALEPSZ256rmbik = 14365, + X86_VRNDSCALEPSZ256rmbikz = 14366, + X86_VRNDSCALEPSZ256rmi = 14367, + X86_VRNDSCALEPSZ256rmik = 14368, + X86_VRNDSCALEPSZ256rmikz = 14369, + X86_VRNDSCALEPSZ256rri = 14370, + X86_VRNDSCALEPSZ256rrik = 14371, + X86_VRNDSCALEPSZ256rrikz = 14372, + X86_VRNDSCALEPSZrmbi = 14373, + X86_VRNDSCALEPSZrmbik = 14374, + X86_VRNDSCALEPSZrmbikz = 14375, + X86_VRNDSCALEPSZrmi = 14376, + X86_VRNDSCALEPSZrmik = 14377, + X86_VRNDSCALEPSZrmikz = 14378, + X86_VRNDSCALEPSZrri = 14379, + X86_VRNDSCALEPSZrrib = 14380, + X86_VRNDSCALEPSZrribk = 14381, + X86_VRNDSCALEPSZrribkz = 14382, + X86_VRNDSCALEPSZrrik = 14383, + X86_VRNDSCALEPSZrrikz = 14384, + X86_VRNDSCALESDZm = 14385, + X86_VRNDSCALESDZm_Int = 14386, + X86_VRNDSCALESDZm_Intk = 14387, + X86_VRNDSCALESDZm_Intkz = 14388, + X86_VRNDSCALESDZr = 14389, + X86_VRNDSCALESDZr_Int = 14390, + X86_VRNDSCALESDZr_Intk = 14391, + X86_VRNDSCALESDZr_Intkz = 14392, + X86_VRNDSCALESDZrb_Int = 14393, + X86_VRNDSCALESDZrb_Intk = 14394, + X86_VRNDSCALESDZrb_Intkz = 14395, + X86_VRNDSCALESSZm = 14396, + X86_VRNDSCALESSZm_Int = 14397, + X86_VRNDSCALESSZm_Intk = 14398, + X86_VRNDSCALESSZm_Intkz = 14399, + X86_VRNDSCALESSZr = 14400, + X86_VRNDSCALESSZr_Int = 14401, + X86_VRNDSCALESSZr_Intk = 14402, + X86_VRNDSCALESSZr_Intkz = 14403, + X86_VRNDSCALESSZrb_Int = 14404, + X86_VRNDSCALESSZrb_Intk = 14405, + X86_VRNDSCALESSZrb_Intkz = 14406, + X86_VROUNDPDYm = 14407, + X86_VROUNDPDYr = 14408, + X86_VROUNDPDm = 14409, + X86_VROUNDPDr = 14410, + X86_VROUNDPSYm = 14411, + X86_VROUNDPSYr = 14412, + X86_VROUNDPSm = 14413, + X86_VROUNDPSr = 14414, + X86_VROUNDSDm = 14415, + X86_VROUNDSDm_Int = 14416, + X86_VROUNDSDr = 14417, + X86_VROUNDSDr_Int = 14418, + X86_VROUNDSSm = 14419, + X86_VROUNDSSm_Int = 14420, + X86_VROUNDSSr = 14421, + X86_VROUNDSSr_Int = 14422, + X86_VRSQRT14PDZ128m = 14423, + X86_VRSQRT14PDZ128mb = 14424, + X86_VRSQRT14PDZ128mbk = 14425, + X86_VRSQRT14PDZ128mbkz = 14426, + X86_VRSQRT14PDZ128mk = 14427, + X86_VRSQRT14PDZ128mkz = 14428, + X86_VRSQRT14PDZ128r = 14429, + X86_VRSQRT14PDZ128rk = 14430, + X86_VRSQRT14PDZ128rkz = 14431, + X86_VRSQRT14PDZ256m = 14432, + X86_VRSQRT14PDZ256mb = 14433, + X86_VRSQRT14PDZ256mbk = 14434, + X86_VRSQRT14PDZ256mbkz = 14435, + X86_VRSQRT14PDZ256mk = 14436, + X86_VRSQRT14PDZ256mkz = 14437, + X86_VRSQRT14PDZ256r = 14438, + X86_VRSQRT14PDZ256rk = 14439, + X86_VRSQRT14PDZ256rkz = 14440, + X86_VRSQRT14PDZm = 14441, + X86_VRSQRT14PDZmb = 14442, + X86_VRSQRT14PDZmbk = 14443, + X86_VRSQRT14PDZmbkz = 14444, + X86_VRSQRT14PDZmk = 14445, + X86_VRSQRT14PDZmkz = 14446, + X86_VRSQRT14PDZr = 14447, + X86_VRSQRT14PDZrk = 14448, + X86_VRSQRT14PDZrkz = 14449, + X86_VRSQRT14PSZ128m = 14450, + X86_VRSQRT14PSZ128mb = 14451, + X86_VRSQRT14PSZ128mbk = 14452, + X86_VRSQRT14PSZ128mbkz = 14453, + X86_VRSQRT14PSZ128mk = 14454, + X86_VRSQRT14PSZ128mkz = 14455, + X86_VRSQRT14PSZ128r = 14456, + X86_VRSQRT14PSZ128rk = 14457, + X86_VRSQRT14PSZ128rkz = 14458, + X86_VRSQRT14PSZ256m = 14459, + X86_VRSQRT14PSZ256mb = 14460, + X86_VRSQRT14PSZ256mbk = 14461, + X86_VRSQRT14PSZ256mbkz = 14462, + X86_VRSQRT14PSZ256mk = 14463, + X86_VRSQRT14PSZ256mkz = 14464, + X86_VRSQRT14PSZ256r = 14465, + X86_VRSQRT14PSZ256rk = 14466, + X86_VRSQRT14PSZ256rkz = 14467, + X86_VRSQRT14PSZm = 14468, + X86_VRSQRT14PSZmb = 14469, + X86_VRSQRT14PSZmbk = 14470, + X86_VRSQRT14PSZmbkz = 14471, + X86_VRSQRT14PSZmk = 14472, + X86_VRSQRT14PSZmkz = 14473, + X86_VRSQRT14PSZr = 14474, + X86_VRSQRT14PSZrk = 14475, + X86_VRSQRT14PSZrkz = 14476, + X86_VRSQRT14SDZrm = 14477, + X86_VRSQRT14SDZrmk = 14478, + X86_VRSQRT14SDZrmkz = 14479, + X86_VRSQRT14SDZrr = 14480, + X86_VRSQRT14SDZrrk = 14481, + X86_VRSQRT14SDZrrkz = 14482, + X86_VRSQRT14SSZrm = 14483, + X86_VRSQRT14SSZrmk = 14484, + X86_VRSQRT14SSZrmkz = 14485, + X86_VRSQRT14SSZrr = 14486, + X86_VRSQRT14SSZrrk = 14487, + X86_VRSQRT14SSZrrkz = 14488, + X86_VRSQRT28PDZm = 14489, + X86_VRSQRT28PDZmb = 14490, + X86_VRSQRT28PDZmbk = 14491, + X86_VRSQRT28PDZmbkz = 14492, + X86_VRSQRT28PDZmk = 14493, + X86_VRSQRT28PDZmkz = 14494, + X86_VRSQRT28PDZr = 14495, + X86_VRSQRT28PDZrb = 14496, + X86_VRSQRT28PDZrbk = 14497, + X86_VRSQRT28PDZrbkz = 14498, + X86_VRSQRT28PDZrk = 14499, + X86_VRSQRT28PDZrkz = 14500, + X86_VRSQRT28PSZm = 14501, + X86_VRSQRT28PSZmb = 14502, + X86_VRSQRT28PSZmbk = 14503, + X86_VRSQRT28PSZmbkz = 14504, + X86_VRSQRT28PSZmk = 14505, + X86_VRSQRT28PSZmkz = 14506, + X86_VRSQRT28PSZr = 14507, + X86_VRSQRT28PSZrb = 14508, + X86_VRSQRT28PSZrbk = 14509, + X86_VRSQRT28PSZrbkz = 14510, + X86_VRSQRT28PSZrk = 14511, + X86_VRSQRT28PSZrkz = 14512, + X86_VRSQRT28SDZm = 14513, + X86_VRSQRT28SDZmk = 14514, + X86_VRSQRT28SDZmkz = 14515, + X86_VRSQRT28SDZr = 14516, + X86_VRSQRT28SDZrb = 14517, + X86_VRSQRT28SDZrbk = 14518, + X86_VRSQRT28SDZrbkz = 14519, + X86_VRSQRT28SDZrk = 14520, + X86_VRSQRT28SDZrkz = 14521, + X86_VRSQRT28SSZm = 14522, + X86_VRSQRT28SSZmk = 14523, + X86_VRSQRT28SSZmkz = 14524, + X86_VRSQRT28SSZr = 14525, + X86_VRSQRT28SSZrb = 14526, + X86_VRSQRT28SSZrbk = 14527, + X86_VRSQRT28SSZrbkz = 14528, + X86_VRSQRT28SSZrk = 14529, + X86_VRSQRT28SSZrkz = 14530, + X86_VRSQRTPSYm = 14531, + X86_VRSQRTPSYr = 14532, + X86_VRSQRTPSm = 14533, + X86_VRSQRTPSr = 14534, + X86_VRSQRTSSm = 14535, + X86_VRSQRTSSm_Int = 14536, + X86_VRSQRTSSr = 14537, + X86_VRSQRTSSr_Int = 14538, + X86_VSCALEFPDZ128rm = 14539, + X86_VSCALEFPDZ128rmb = 14540, + X86_VSCALEFPDZ128rmbk = 14541, + X86_VSCALEFPDZ128rmbkz = 14542, + X86_VSCALEFPDZ128rmk = 14543, + X86_VSCALEFPDZ128rmkz = 14544, + X86_VSCALEFPDZ128rr = 14545, + X86_VSCALEFPDZ128rrk = 14546, + X86_VSCALEFPDZ128rrkz = 14547, + X86_VSCALEFPDZ256rm = 14548, + X86_VSCALEFPDZ256rmb = 14549, + X86_VSCALEFPDZ256rmbk = 14550, + X86_VSCALEFPDZ256rmbkz = 14551, + X86_VSCALEFPDZ256rmk = 14552, + X86_VSCALEFPDZ256rmkz = 14553, + X86_VSCALEFPDZ256rr = 14554, + X86_VSCALEFPDZ256rrk = 14555, + X86_VSCALEFPDZ256rrkz = 14556, + X86_VSCALEFPDZrm = 14557, + X86_VSCALEFPDZrmb = 14558, + X86_VSCALEFPDZrmbk = 14559, + X86_VSCALEFPDZrmbkz = 14560, + X86_VSCALEFPDZrmk = 14561, + X86_VSCALEFPDZrmkz = 14562, + X86_VSCALEFPDZrr = 14563, + X86_VSCALEFPDZrrb = 14564, + X86_VSCALEFPDZrrbk = 14565, + X86_VSCALEFPDZrrbkz = 14566, + X86_VSCALEFPDZrrk = 14567, + X86_VSCALEFPDZrrkz = 14568, + X86_VSCALEFPSZ128rm = 14569, + X86_VSCALEFPSZ128rmb = 14570, + X86_VSCALEFPSZ128rmbk = 14571, + X86_VSCALEFPSZ128rmbkz = 14572, + X86_VSCALEFPSZ128rmk = 14573, + X86_VSCALEFPSZ128rmkz = 14574, + X86_VSCALEFPSZ128rr = 14575, + X86_VSCALEFPSZ128rrk = 14576, + X86_VSCALEFPSZ128rrkz = 14577, + X86_VSCALEFPSZ256rm = 14578, + X86_VSCALEFPSZ256rmb = 14579, + X86_VSCALEFPSZ256rmbk = 14580, + X86_VSCALEFPSZ256rmbkz = 14581, + X86_VSCALEFPSZ256rmk = 14582, + X86_VSCALEFPSZ256rmkz = 14583, + X86_VSCALEFPSZ256rr = 14584, + X86_VSCALEFPSZ256rrk = 14585, + X86_VSCALEFPSZ256rrkz = 14586, + X86_VSCALEFPSZrm = 14587, + X86_VSCALEFPSZrmb = 14588, + X86_VSCALEFPSZrmbk = 14589, + X86_VSCALEFPSZrmbkz = 14590, + X86_VSCALEFPSZrmk = 14591, + X86_VSCALEFPSZrmkz = 14592, + X86_VSCALEFPSZrr = 14593, + X86_VSCALEFPSZrrb = 14594, + X86_VSCALEFPSZrrbk = 14595, + X86_VSCALEFPSZrrbkz = 14596, + X86_VSCALEFPSZrrk = 14597, + X86_VSCALEFPSZrrkz = 14598, + X86_VSCALEFSDZrm = 14599, + X86_VSCALEFSDZrmk = 14600, + X86_VSCALEFSDZrmkz = 14601, + X86_VSCALEFSDZrr = 14602, + X86_VSCALEFSDZrrb_Int = 14603, + X86_VSCALEFSDZrrb_Intk = 14604, + X86_VSCALEFSDZrrb_Intkz = 14605, + X86_VSCALEFSDZrrk = 14606, + X86_VSCALEFSDZrrkz = 14607, + X86_VSCALEFSSZrm = 14608, + X86_VSCALEFSSZrmk = 14609, + X86_VSCALEFSSZrmkz = 14610, + X86_VSCALEFSSZrr = 14611, + X86_VSCALEFSSZrrb_Int = 14612, + X86_VSCALEFSSZrrb_Intk = 14613, + X86_VSCALEFSSZrrb_Intkz = 14614, + X86_VSCALEFSSZrrk = 14615, + X86_VSCALEFSSZrrkz = 14616, + X86_VSCATTERDPDZ128mr = 14617, + X86_VSCATTERDPDZ256mr = 14618, + X86_VSCATTERDPDZmr = 14619, + X86_VSCATTERDPSZ128mr = 14620, + X86_VSCATTERDPSZ256mr = 14621, + X86_VSCATTERDPSZmr = 14622, + X86_VSCATTERPF0DPDm = 14623, + X86_VSCATTERPF0DPSm = 14624, + X86_VSCATTERPF0QPDm = 14625, + X86_VSCATTERPF0QPSm = 14626, + X86_VSCATTERPF1DPDm = 14627, + X86_VSCATTERPF1DPSm = 14628, + X86_VSCATTERPF1QPDm = 14629, + X86_VSCATTERPF1QPSm = 14630, + X86_VSCATTERQPDZ128mr = 14631, + X86_VSCATTERQPDZ256mr = 14632, + X86_VSCATTERQPDZmr = 14633, + X86_VSCATTERQPSZ128mr = 14634, + X86_VSCATTERQPSZ256mr = 14635, + X86_VSCATTERQPSZmr = 14636, + X86_VSHUFF32X4Z256rmbi = 14637, + X86_VSHUFF32X4Z256rmbik = 14638, + X86_VSHUFF32X4Z256rmbikz = 14639, + X86_VSHUFF32X4Z256rmi = 14640, + X86_VSHUFF32X4Z256rmik = 14641, + X86_VSHUFF32X4Z256rmikz = 14642, + X86_VSHUFF32X4Z256rri = 14643, + X86_VSHUFF32X4Z256rrik = 14644, + X86_VSHUFF32X4Z256rrikz = 14645, + X86_VSHUFF32X4Zrmbi = 14646, + X86_VSHUFF32X4Zrmbik = 14647, + X86_VSHUFF32X4Zrmbikz = 14648, + X86_VSHUFF32X4Zrmi = 14649, + X86_VSHUFF32X4Zrmik = 14650, + X86_VSHUFF32X4Zrmikz = 14651, + X86_VSHUFF32X4Zrri = 14652, + X86_VSHUFF32X4Zrrik = 14653, + X86_VSHUFF32X4Zrrikz = 14654, + X86_VSHUFF64X2Z256rmbi = 14655, + X86_VSHUFF64X2Z256rmbik = 14656, + X86_VSHUFF64X2Z256rmbikz = 14657, + X86_VSHUFF64X2Z256rmi = 14658, + X86_VSHUFF64X2Z256rmik = 14659, + X86_VSHUFF64X2Z256rmikz = 14660, + X86_VSHUFF64X2Z256rri = 14661, + X86_VSHUFF64X2Z256rrik = 14662, + X86_VSHUFF64X2Z256rrikz = 14663, + X86_VSHUFF64X2Zrmbi = 14664, + X86_VSHUFF64X2Zrmbik = 14665, + X86_VSHUFF64X2Zrmbikz = 14666, + X86_VSHUFF64X2Zrmi = 14667, + X86_VSHUFF64X2Zrmik = 14668, + X86_VSHUFF64X2Zrmikz = 14669, + X86_VSHUFF64X2Zrri = 14670, + X86_VSHUFF64X2Zrrik = 14671, + X86_VSHUFF64X2Zrrikz = 14672, + X86_VSHUFI32X4Z256rmbi = 14673, + X86_VSHUFI32X4Z256rmbik = 14674, + X86_VSHUFI32X4Z256rmbikz = 14675, + X86_VSHUFI32X4Z256rmi = 14676, + X86_VSHUFI32X4Z256rmik = 14677, + X86_VSHUFI32X4Z256rmikz = 14678, + X86_VSHUFI32X4Z256rri = 14679, + X86_VSHUFI32X4Z256rrik = 14680, + X86_VSHUFI32X4Z256rrikz = 14681, + X86_VSHUFI32X4Zrmbi = 14682, + X86_VSHUFI32X4Zrmbik = 14683, + X86_VSHUFI32X4Zrmbikz = 14684, + X86_VSHUFI32X4Zrmi = 14685, + X86_VSHUFI32X4Zrmik = 14686, + X86_VSHUFI32X4Zrmikz = 14687, + X86_VSHUFI32X4Zrri = 14688, + X86_VSHUFI32X4Zrrik = 14689, + X86_VSHUFI32X4Zrrikz = 14690, + X86_VSHUFI64X2Z256rmbi = 14691, + X86_VSHUFI64X2Z256rmbik = 14692, + X86_VSHUFI64X2Z256rmbikz = 14693, + X86_VSHUFI64X2Z256rmi = 14694, + X86_VSHUFI64X2Z256rmik = 14695, + X86_VSHUFI64X2Z256rmikz = 14696, + X86_VSHUFI64X2Z256rri = 14697, + X86_VSHUFI64X2Z256rrik = 14698, + X86_VSHUFI64X2Z256rrikz = 14699, + X86_VSHUFI64X2Zrmbi = 14700, + X86_VSHUFI64X2Zrmbik = 14701, + X86_VSHUFI64X2Zrmbikz = 14702, + X86_VSHUFI64X2Zrmi = 14703, + X86_VSHUFI64X2Zrmik = 14704, + X86_VSHUFI64X2Zrmikz = 14705, + X86_VSHUFI64X2Zrri = 14706, + X86_VSHUFI64X2Zrrik = 14707, + X86_VSHUFI64X2Zrrikz = 14708, + X86_VSHUFPDYrmi = 14709, + X86_VSHUFPDYrri = 14710, + X86_VSHUFPDZ128rmbi = 14711, + X86_VSHUFPDZ128rmbik = 14712, + X86_VSHUFPDZ128rmbikz = 14713, + X86_VSHUFPDZ128rmi = 14714, + X86_VSHUFPDZ128rmik = 14715, + X86_VSHUFPDZ128rmikz = 14716, + X86_VSHUFPDZ128rri = 14717, + X86_VSHUFPDZ128rrik = 14718, + X86_VSHUFPDZ128rrikz = 14719, + X86_VSHUFPDZ256rmbi = 14720, + X86_VSHUFPDZ256rmbik = 14721, + X86_VSHUFPDZ256rmbikz = 14722, + X86_VSHUFPDZ256rmi = 14723, + X86_VSHUFPDZ256rmik = 14724, + X86_VSHUFPDZ256rmikz = 14725, + X86_VSHUFPDZ256rri = 14726, + X86_VSHUFPDZ256rrik = 14727, + X86_VSHUFPDZ256rrikz = 14728, + X86_VSHUFPDZrmbi = 14729, + X86_VSHUFPDZrmbik = 14730, + X86_VSHUFPDZrmbikz = 14731, + X86_VSHUFPDZrmi = 14732, + X86_VSHUFPDZrmik = 14733, + X86_VSHUFPDZrmikz = 14734, + X86_VSHUFPDZrri = 14735, + X86_VSHUFPDZrrik = 14736, + X86_VSHUFPDZrrikz = 14737, + X86_VSHUFPDrmi = 14738, + X86_VSHUFPDrri = 14739, + X86_VSHUFPSYrmi = 14740, + X86_VSHUFPSYrri = 14741, + X86_VSHUFPSZ128rmbi = 14742, + X86_VSHUFPSZ128rmbik = 14743, + X86_VSHUFPSZ128rmbikz = 14744, + X86_VSHUFPSZ128rmi = 14745, + X86_VSHUFPSZ128rmik = 14746, + X86_VSHUFPSZ128rmikz = 14747, + X86_VSHUFPSZ128rri = 14748, + X86_VSHUFPSZ128rrik = 14749, + X86_VSHUFPSZ128rrikz = 14750, + X86_VSHUFPSZ256rmbi = 14751, + X86_VSHUFPSZ256rmbik = 14752, + X86_VSHUFPSZ256rmbikz = 14753, + X86_VSHUFPSZ256rmi = 14754, + X86_VSHUFPSZ256rmik = 14755, + X86_VSHUFPSZ256rmikz = 14756, + X86_VSHUFPSZ256rri = 14757, + X86_VSHUFPSZ256rrik = 14758, + X86_VSHUFPSZ256rrikz = 14759, + X86_VSHUFPSZrmbi = 14760, + X86_VSHUFPSZrmbik = 14761, + X86_VSHUFPSZrmbikz = 14762, + X86_VSHUFPSZrmi = 14763, + X86_VSHUFPSZrmik = 14764, + X86_VSHUFPSZrmikz = 14765, + X86_VSHUFPSZrri = 14766, + X86_VSHUFPSZrrik = 14767, + X86_VSHUFPSZrrikz = 14768, + X86_VSHUFPSrmi = 14769, + X86_VSHUFPSrri = 14770, + X86_VSQRTPDYm = 14771, + X86_VSQRTPDYr = 14772, + X86_VSQRTPDZ128m = 14773, + X86_VSQRTPDZ128mb = 14774, + X86_VSQRTPDZ128mbk = 14775, + X86_VSQRTPDZ128mbkz = 14776, + X86_VSQRTPDZ128mk = 14777, + X86_VSQRTPDZ128mkz = 14778, + X86_VSQRTPDZ128r = 14779, + X86_VSQRTPDZ128rk = 14780, + X86_VSQRTPDZ128rkz = 14781, + X86_VSQRTPDZ256m = 14782, + X86_VSQRTPDZ256mb = 14783, + X86_VSQRTPDZ256mbk = 14784, + X86_VSQRTPDZ256mbkz = 14785, + X86_VSQRTPDZ256mk = 14786, + X86_VSQRTPDZ256mkz = 14787, + X86_VSQRTPDZ256r = 14788, + X86_VSQRTPDZ256rk = 14789, + X86_VSQRTPDZ256rkz = 14790, + X86_VSQRTPDZm = 14791, + X86_VSQRTPDZmb = 14792, + X86_VSQRTPDZmbk = 14793, + X86_VSQRTPDZmbkz = 14794, + X86_VSQRTPDZmk = 14795, + X86_VSQRTPDZmkz = 14796, + X86_VSQRTPDZr = 14797, + X86_VSQRTPDZrb = 14798, + X86_VSQRTPDZrbk = 14799, + X86_VSQRTPDZrbkz = 14800, + X86_VSQRTPDZrk = 14801, + X86_VSQRTPDZrkz = 14802, + X86_VSQRTPDm = 14803, + X86_VSQRTPDr = 14804, + X86_VSQRTPSYm = 14805, + X86_VSQRTPSYr = 14806, + X86_VSQRTPSZ128m = 14807, + X86_VSQRTPSZ128mb = 14808, + X86_VSQRTPSZ128mbk = 14809, + X86_VSQRTPSZ128mbkz = 14810, + X86_VSQRTPSZ128mk = 14811, + X86_VSQRTPSZ128mkz = 14812, + X86_VSQRTPSZ128r = 14813, + X86_VSQRTPSZ128rk = 14814, + X86_VSQRTPSZ128rkz = 14815, + X86_VSQRTPSZ256m = 14816, + X86_VSQRTPSZ256mb = 14817, + X86_VSQRTPSZ256mbk = 14818, + X86_VSQRTPSZ256mbkz = 14819, + X86_VSQRTPSZ256mk = 14820, + X86_VSQRTPSZ256mkz = 14821, + X86_VSQRTPSZ256r = 14822, + X86_VSQRTPSZ256rk = 14823, + X86_VSQRTPSZ256rkz = 14824, + X86_VSQRTPSZm = 14825, + X86_VSQRTPSZmb = 14826, + X86_VSQRTPSZmbk = 14827, + X86_VSQRTPSZmbkz = 14828, + X86_VSQRTPSZmk = 14829, + X86_VSQRTPSZmkz = 14830, + X86_VSQRTPSZr = 14831, + X86_VSQRTPSZrb = 14832, + X86_VSQRTPSZrbk = 14833, + X86_VSQRTPSZrbkz = 14834, + X86_VSQRTPSZrk = 14835, + X86_VSQRTPSZrkz = 14836, + X86_VSQRTPSm = 14837, + X86_VSQRTPSr = 14838, + X86_VSQRTSDZm = 14839, + X86_VSQRTSDZm_Int = 14840, + X86_VSQRTSDZm_Intk = 14841, + X86_VSQRTSDZm_Intkz = 14842, + X86_VSQRTSDZr = 14843, + X86_VSQRTSDZr_Int = 14844, + X86_VSQRTSDZr_Intk = 14845, + X86_VSQRTSDZr_Intkz = 14846, + X86_VSQRTSDZrb_Int = 14847, + X86_VSQRTSDZrb_Intk = 14848, + X86_VSQRTSDZrb_Intkz = 14849, + X86_VSQRTSDm = 14850, + X86_VSQRTSDm_Int = 14851, + X86_VSQRTSDr = 14852, + X86_VSQRTSDr_Int = 14853, + X86_VSQRTSSZm = 14854, + X86_VSQRTSSZm_Int = 14855, + X86_VSQRTSSZm_Intk = 14856, + X86_VSQRTSSZm_Intkz = 14857, + X86_VSQRTSSZr = 14858, + X86_VSQRTSSZr_Int = 14859, + X86_VSQRTSSZr_Intk = 14860, + X86_VSQRTSSZr_Intkz = 14861, + X86_VSQRTSSZrb_Int = 14862, + X86_VSQRTSSZrb_Intk = 14863, + X86_VSQRTSSZrb_Intkz = 14864, + X86_VSQRTSSm = 14865, + X86_VSQRTSSm_Int = 14866, + X86_VSQRTSSr = 14867, + X86_VSQRTSSr_Int = 14868, + X86_VSTMXCSR = 14869, + X86_VSUBPDYrm = 14870, + X86_VSUBPDYrr = 14871, + X86_VSUBPDZ128rm = 14872, + X86_VSUBPDZ128rmb = 14873, + X86_VSUBPDZ128rmbk = 14874, + X86_VSUBPDZ128rmbkz = 14875, + X86_VSUBPDZ128rmk = 14876, + X86_VSUBPDZ128rmkz = 14877, + X86_VSUBPDZ128rr = 14878, + X86_VSUBPDZ128rrk = 14879, + X86_VSUBPDZ128rrkz = 14880, + X86_VSUBPDZ256rm = 14881, + X86_VSUBPDZ256rmb = 14882, + X86_VSUBPDZ256rmbk = 14883, + X86_VSUBPDZ256rmbkz = 14884, + X86_VSUBPDZ256rmk = 14885, + X86_VSUBPDZ256rmkz = 14886, + X86_VSUBPDZ256rr = 14887, + X86_VSUBPDZ256rrk = 14888, + X86_VSUBPDZ256rrkz = 14889, + X86_VSUBPDZrm = 14890, + X86_VSUBPDZrmb = 14891, + X86_VSUBPDZrmbk = 14892, + X86_VSUBPDZrmbkz = 14893, + X86_VSUBPDZrmk = 14894, + X86_VSUBPDZrmkz = 14895, + X86_VSUBPDZrr = 14896, + X86_VSUBPDZrrb = 14897, + X86_VSUBPDZrrbk = 14898, + X86_VSUBPDZrrbkz = 14899, + X86_VSUBPDZrrk = 14900, + X86_VSUBPDZrrkz = 14901, + X86_VSUBPDrm = 14902, + X86_VSUBPDrr = 14903, + X86_VSUBPSYrm = 14904, + X86_VSUBPSYrr = 14905, + X86_VSUBPSZ128rm = 14906, + X86_VSUBPSZ128rmb = 14907, + X86_VSUBPSZ128rmbk = 14908, + X86_VSUBPSZ128rmbkz = 14909, + X86_VSUBPSZ128rmk = 14910, + X86_VSUBPSZ128rmkz = 14911, + X86_VSUBPSZ128rr = 14912, + X86_VSUBPSZ128rrk = 14913, + X86_VSUBPSZ128rrkz = 14914, + X86_VSUBPSZ256rm = 14915, + X86_VSUBPSZ256rmb = 14916, + X86_VSUBPSZ256rmbk = 14917, + X86_VSUBPSZ256rmbkz = 14918, + X86_VSUBPSZ256rmk = 14919, + X86_VSUBPSZ256rmkz = 14920, + X86_VSUBPSZ256rr = 14921, + X86_VSUBPSZ256rrk = 14922, + X86_VSUBPSZ256rrkz = 14923, + X86_VSUBPSZrm = 14924, + X86_VSUBPSZrmb = 14925, + X86_VSUBPSZrmbk = 14926, + X86_VSUBPSZrmbkz = 14927, + X86_VSUBPSZrmk = 14928, + X86_VSUBPSZrmkz = 14929, + X86_VSUBPSZrr = 14930, + X86_VSUBPSZrrb = 14931, + X86_VSUBPSZrrbk = 14932, + X86_VSUBPSZrrbkz = 14933, + X86_VSUBPSZrrk = 14934, + X86_VSUBPSZrrkz = 14935, + X86_VSUBPSrm = 14936, + X86_VSUBPSrr = 14937, + X86_VSUBSDZrm = 14938, + X86_VSUBSDZrm_Int = 14939, + X86_VSUBSDZrm_Intk = 14940, + X86_VSUBSDZrm_Intkz = 14941, + X86_VSUBSDZrr = 14942, + X86_VSUBSDZrr_Int = 14943, + X86_VSUBSDZrr_Intk = 14944, + X86_VSUBSDZrr_Intkz = 14945, + X86_VSUBSDZrrb_Int = 14946, + X86_VSUBSDZrrb_Intk = 14947, + X86_VSUBSDZrrb_Intkz = 14948, + X86_VSUBSDrm = 14949, + X86_VSUBSDrm_Int = 14950, + X86_VSUBSDrr = 14951, + X86_VSUBSDrr_Int = 14952, + X86_VSUBSSZrm = 14953, + X86_VSUBSSZrm_Int = 14954, + X86_VSUBSSZrm_Intk = 14955, + X86_VSUBSSZrm_Intkz = 14956, + X86_VSUBSSZrr = 14957, + X86_VSUBSSZrr_Int = 14958, + X86_VSUBSSZrr_Intk = 14959, + X86_VSUBSSZrr_Intkz = 14960, + X86_VSUBSSZrrb_Int = 14961, + X86_VSUBSSZrrb_Intk = 14962, + X86_VSUBSSZrrb_Intkz = 14963, + X86_VSUBSSrm = 14964, + X86_VSUBSSrm_Int = 14965, + X86_VSUBSSrr = 14966, + X86_VSUBSSrr_Int = 14967, + X86_VTESTPDYrm = 14968, + X86_VTESTPDYrr = 14969, + X86_VTESTPDrm = 14970, + X86_VTESTPDrr = 14971, + X86_VTESTPSYrm = 14972, + X86_VTESTPSYrr = 14973, + X86_VTESTPSrm = 14974, + X86_VTESTPSrr = 14975, + X86_VUCOMISDZrm = 14976, + X86_VUCOMISDZrm_Int = 14977, + X86_VUCOMISDZrr = 14978, + X86_VUCOMISDZrr_Int = 14979, + X86_VUCOMISDZrrb = 14980, + X86_VUCOMISDrm = 14981, + X86_VUCOMISDrm_Int = 14982, + X86_VUCOMISDrr = 14983, + X86_VUCOMISDrr_Int = 14984, + X86_VUCOMISSZrm = 14985, + X86_VUCOMISSZrm_Int = 14986, + X86_VUCOMISSZrr = 14987, + X86_VUCOMISSZrr_Int = 14988, + X86_VUCOMISSZrrb = 14989, + X86_VUCOMISSrm = 14990, + X86_VUCOMISSrm_Int = 14991, + X86_VUCOMISSrr = 14992, + X86_VUCOMISSrr_Int = 14993, + X86_VUNPCKHPDYrm = 14994, + X86_VUNPCKHPDYrr = 14995, + X86_VUNPCKHPDZ128rm = 14996, + X86_VUNPCKHPDZ128rmb = 14997, + X86_VUNPCKHPDZ128rmbk = 14998, + X86_VUNPCKHPDZ128rmbkz = 14999, + X86_VUNPCKHPDZ128rmk = 15000, + X86_VUNPCKHPDZ128rmkz = 15001, + X86_VUNPCKHPDZ128rr = 15002, + X86_VUNPCKHPDZ128rrk = 15003, + X86_VUNPCKHPDZ128rrkz = 15004, + X86_VUNPCKHPDZ256rm = 15005, + X86_VUNPCKHPDZ256rmb = 15006, + X86_VUNPCKHPDZ256rmbk = 15007, + X86_VUNPCKHPDZ256rmbkz = 15008, + X86_VUNPCKHPDZ256rmk = 15009, + X86_VUNPCKHPDZ256rmkz = 15010, + X86_VUNPCKHPDZ256rr = 15011, + X86_VUNPCKHPDZ256rrk = 15012, + X86_VUNPCKHPDZ256rrkz = 15013, + X86_VUNPCKHPDZrm = 15014, + X86_VUNPCKHPDZrmb = 15015, + X86_VUNPCKHPDZrmbk = 15016, + X86_VUNPCKHPDZrmbkz = 15017, + X86_VUNPCKHPDZrmk = 15018, + X86_VUNPCKHPDZrmkz = 15019, + X86_VUNPCKHPDZrr = 15020, + X86_VUNPCKHPDZrrk = 15021, + X86_VUNPCKHPDZrrkz = 15022, + X86_VUNPCKHPDrm = 15023, + X86_VUNPCKHPDrr = 15024, + X86_VUNPCKHPSYrm = 15025, + X86_VUNPCKHPSYrr = 15026, + X86_VUNPCKHPSZ128rm = 15027, + X86_VUNPCKHPSZ128rmb = 15028, + X86_VUNPCKHPSZ128rmbk = 15029, + X86_VUNPCKHPSZ128rmbkz = 15030, + X86_VUNPCKHPSZ128rmk = 15031, + X86_VUNPCKHPSZ128rmkz = 15032, + X86_VUNPCKHPSZ128rr = 15033, + X86_VUNPCKHPSZ128rrk = 15034, + X86_VUNPCKHPSZ128rrkz = 15035, + X86_VUNPCKHPSZ256rm = 15036, + X86_VUNPCKHPSZ256rmb = 15037, + X86_VUNPCKHPSZ256rmbk = 15038, + X86_VUNPCKHPSZ256rmbkz = 15039, + X86_VUNPCKHPSZ256rmk = 15040, + X86_VUNPCKHPSZ256rmkz = 15041, + X86_VUNPCKHPSZ256rr = 15042, + X86_VUNPCKHPSZ256rrk = 15043, + X86_VUNPCKHPSZ256rrkz = 15044, + X86_VUNPCKHPSZrm = 15045, + X86_VUNPCKHPSZrmb = 15046, + X86_VUNPCKHPSZrmbk = 15047, + X86_VUNPCKHPSZrmbkz = 15048, + X86_VUNPCKHPSZrmk = 15049, + X86_VUNPCKHPSZrmkz = 15050, + X86_VUNPCKHPSZrr = 15051, + X86_VUNPCKHPSZrrk = 15052, + X86_VUNPCKHPSZrrkz = 15053, + X86_VUNPCKHPSrm = 15054, + X86_VUNPCKHPSrr = 15055, + X86_VUNPCKLPDYrm = 15056, + X86_VUNPCKLPDYrr = 15057, + X86_VUNPCKLPDZ128rm = 15058, + X86_VUNPCKLPDZ128rmb = 15059, + X86_VUNPCKLPDZ128rmbk = 15060, + X86_VUNPCKLPDZ128rmbkz = 15061, + X86_VUNPCKLPDZ128rmk = 15062, + X86_VUNPCKLPDZ128rmkz = 15063, + X86_VUNPCKLPDZ128rr = 15064, + X86_VUNPCKLPDZ128rrk = 15065, + X86_VUNPCKLPDZ128rrkz = 15066, + X86_VUNPCKLPDZ256rm = 15067, + X86_VUNPCKLPDZ256rmb = 15068, + X86_VUNPCKLPDZ256rmbk = 15069, + X86_VUNPCKLPDZ256rmbkz = 15070, + X86_VUNPCKLPDZ256rmk = 15071, + X86_VUNPCKLPDZ256rmkz = 15072, + X86_VUNPCKLPDZ256rr = 15073, + X86_VUNPCKLPDZ256rrk = 15074, + X86_VUNPCKLPDZ256rrkz = 15075, + X86_VUNPCKLPDZrm = 15076, + X86_VUNPCKLPDZrmb = 15077, + X86_VUNPCKLPDZrmbk = 15078, + X86_VUNPCKLPDZrmbkz = 15079, + X86_VUNPCKLPDZrmk = 15080, + X86_VUNPCKLPDZrmkz = 15081, + X86_VUNPCKLPDZrr = 15082, + X86_VUNPCKLPDZrrk = 15083, + X86_VUNPCKLPDZrrkz = 15084, + X86_VUNPCKLPDrm = 15085, + X86_VUNPCKLPDrr = 15086, + X86_VUNPCKLPSYrm = 15087, + X86_VUNPCKLPSYrr = 15088, + X86_VUNPCKLPSZ128rm = 15089, + X86_VUNPCKLPSZ128rmb = 15090, + X86_VUNPCKLPSZ128rmbk = 15091, + X86_VUNPCKLPSZ128rmbkz = 15092, + X86_VUNPCKLPSZ128rmk = 15093, + X86_VUNPCKLPSZ128rmkz = 15094, + X86_VUNPCKLPSZ128rr = 15095, + X86_VUNPCKLPSZ128rrk = 15096, + X86_VUNPCKLPSZ128rrkz = 15097, + X86_VUNPCKLPSZ256rm = 15098, + X86_VUNPCKLPSZ256rmb = 15099, + X86_VUNPCKLPSZ256rmbk = 15100, + X86_VUNPCKLPSZ256rmbkz = 15101, + X86_VUNPCKLPSZ256rmk = 15102, + X86_VUNPCKLPSZ256rmkz = 15103, + X86_VUNPCKLPSZ256rr = 15104, + X86_VUNPCKLPSZ256rrk = 15105, + X86_VUNPCKLPSZ256rrkz = 15106, + X86_VUNPCKLPSZrm = 15107, + X86_VUNPCKLPSZrmb = 15108, + X86_VUNPCKLPSZrmbk = 15109, + X86_VUNPCKLPSZrmbkz = 15110, + X86_VUNPCKLPSZrmk = 15111, + X86_VUNPCKLPSZrmkz = 15112, + X86_VUNPCKLPSZrr = 15113, + X86_VUNPCKLPSZrrk = 15114, + X86_VUNPCKLPSZrrkz = 15115, + X86_VUNPCKLPSrm = 15116, + X86_VUNPCKLPSrr = 15117, + X86_VXORPDYrm = 15118, + X86_VXORPDYrr = 15119, + X86_VXORPDZ128rm = 15120, + X86_VXORPDZ128rmb = 15121, + X86_VXORPDZ128rmbk = 15122, + X86_VXORPDZ128rmbkz = 15123, + X86_VXORPDZ128rmk = 15124, + X86_VXORPDZ128rmkz = 15125, + X86_VXORPDZ128rr = 15126, + X86_VXORPDZ128rrk = 15127, + X86_VXORPDZ128rrkz = 15128, + X86_VXORPDZ256rm = 15129, + X86_VXORPDZ256rmb = 15130, + X86_VXORPDZ256rmbk = 15131, + X86_VXORPDZ256rmbkz = 15132, + X86_VXORPDZ256rmk = 15133, + X86_VXORPDZ256rmkz = 15134, + X86_VXORPDZ256rr = 15135, + X86_VXORPDZ256rrk = 15136, + X86_VXORPDZ256rrkz = 15137, + X86_VXORPDZrm = 15138, + X86_VXORPDZrmb = 15139, + X86_VXORPDZrmbk = 15140, + X86_VXORPDZrmbkz = 15141, + X86_VXORPDZrmk = 15142, + X86_VXORPDZrmkz = 15143, + X86_VXORPDZrr = 15144, + X86_VXORPDZrrk = 15145, + X86_VXORPDZrrkz = 15146, + X86_VXORPDrm = 15147, + X86_VXORPDrr = 15148, + X86_VXORPSYrm = 15149, + X86_VXORPSYrr = 15150, + X86_VXORPSZ128rm = 15151, + X86_VXORPSZ128rmb = 15152, + X86_VXORPSZ128rmbk = 15153, + X86_VXORPSZ128rmbkz = 15154, + X86_VXORPSZ128rmk = 15155, + X86_VXORPSZ128rmkz = 15156, + X86_VXORPSZ128rr = 15157, + X86_VXORPSZ128rrk = 15158, + X86_VXORPSZ128rrkz = 15159, + X86_VXORPSZ256rm = 15160, + X86_VXORPSZ256rmb = 15161, + X86_VXORPSZ256rmbk = 15162, + X86_VXORPSZ256rmbkz = 15163, + X86_VXORPSZ256rmk = 15164, + X86_VXORPSZ256rmkz = 15165, + X86_VXORPSZ256rr = 15166, + X86_VXORPSZ256rrk = 15167, + X86_VXORPSZ256rrkz = 15168, + X86_VXORPSZrm = 15169, + X86_VXORPSZrmb = 15170, + X86_VXORPSZrmbk = 15171, + X86_VXORPSZrmbkz = 15172, + X86_VXORPSZrmk = 15173, + X86_VXORPSZrmkz = 15174, + X86_VXORPSZrr = 15175, + X86_VXORPSZrrk = 15176, + X86_VXORPSZrrkz = 15177, + X86_VXORPSrm = 15178, + X86_VXORPSrr = 15179, + X86_VZEROALL = 15180, + X86_VZEROUPPER = 15181, + X86_WAIT = 15182, + X86_WBINVD = 15183, + X86_WBNOINVD = 15184, + X86_WRFSBASE = 15185, + X86_WRFSBASE64 = 15186, + X86_WRGSBASE = 15187, + X86_WRGSBASE64 = 15188, + X86_WRMSR = 15189, + X86_WRPKRUr = 15190, + X86_WRSSD = 15191, + X86_WRSSQ = 15192, + X86_WRUSSD = 15193, + X86_WRUSSQ = 15194, + X86_XABORT = 15195, + X86_XACQUIRE_PREFIX = 15196, + X86_XADD16rm = 15197, + X86_XADD16rr = 15198, + X86_XADD32rm = 15199, + X86_XADD32rr = 15200, + X86_XADD64rm = 15201, + X86_XADD64rr = 15202, + X86_XADD8rm = 15203, + X86_XADD8rr = 15204, + X86_XBEGIN_2 = 15205, + X86_XBEGIN_4 = 15206, + X86_XCHG16ar = 15207, + X86_XCHG16rm = 15208, + X86_XCHG16rr = 15209, + X86_XCHG32ar = 15210, + X86_XCHG32rm = 15211, + X86_XCHG32rr = 15212, + X86_XCHG64ar = 15213, + X86_XCHG64rm = 15214, + X86_XCHG64rr = 15215, + X86_XCHG8rm = 15216, + X86_XCHG8rr = 15217, + X86_XCH_F = 15218, + X86_XCRYPTCBC = 15219, + X86_XCRYPTCFB = 15220, + X86_XCRYPTCTR = 15221, + X86_XCRYPTECB = 15222, + X86_XCRYPTOFB = 15223, + X86_XEND = 15224, + X86_XGETBV = 15225, + X86_XLAT = 15226, + X86_XOR16i16 = 15227, + X86_XOR16mi = 15228, + X86_XOR16mi8 = 15229, + X86_XOR16mr = 15230, + X86_XOR16ri = 15231, + X86_XOR16ri8 = 15232, + X86_XOR16rm = 15233, + X86_XOR16rr = 15234, + X86_XOR16rr_REV = 15235, + X86_XOR32i32 = 15236, + X86_XOR32mi = 15237, + X86_XOR32mi8 = 15238, + X86_XOR32mr = 15239, + X86_XOR32ri = 15240, + X86_XOR32ri8 = 15241, + X86_XOR32rm = 15242, + X86_XOR32rr = 15243, + X86_XOR32rr_REV = 15244, + X86_XOR64i32 = 15245, + X86_XOR64mi32 = 15246, + X86_XOR64mi8 = 15247, + X86_XOR64mr = 15248, + X86_XOR64ri32 = 15249, + X86_XOR64ri8 = 15250, + X86_XOR64rm = 15251, + X86_XOR64rr = 15252, + X86_XOR64rr_REV = 15253, + X86_XOR8i8 = 15254, + X86_XOR8mi = 15255, + X86_XOR8mi8 = 15256, + X86_XOR8mr = 15257, + X86_XOR8ri = 15258, + X86_XOR8ri8 = 15259, + X86_XOR8rm = 15260, + X86_XOR8rr = 15261, + X86_XOR8rr_REV = 15262, + X86_XORPDrm = 15263, + X86_XORPDrr = 15264, + X86_XORPSrm = 15265, + X86_XORPSrr = 15266, + X86_XRELEASE_PREFIX = 15267, + X86_XRSTOR = 15268, + X86_XRSTOR64 = 15269, + X86_XRSTORS = 15270, + X86_XRSTORS64 = 15271, + X86_XSAVE = 15272, + X86_XSAVE64 = 15273, + X86_XSAVEC = 15274, + X86_XSAVEC64 = 15275, + X86_XSAVEOPT = 15276, + X86_XSAVEOPT64 = 15277, + X86_XSAVES = 15278, + X86_XSAVES64 = 15279, + X86_XSETBV = 15280, + X86_XSHA1 = 15281, + X86_XSHA256 = 15282, + X86_XSTORE = 15283, + X86_XTEST = 15284, + X86_INSTRUCTION_LIST_END = 15285 +}; + +#endif // GET_INSTRINFO_ENUM diff --git a/thirdparty/capstone/arch/X86/X86GenInstrInfo_reduce.inc b/thirdparty/capstone/arch/X86/X86GenInstrInfo_reduce.inc new file mode 100644 index 0000000..81c0f6c --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenInstrInfo_reduce.inc @@ -0,0 +1,1564 @@ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +|* Target Instruction Enum Values and Descriptors *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + +enum { + X86_AAA = 126, + X86_AAD8i8 = 127, + X86_AAM8i8 = 128, + X86_AAS = 129, + X86_ADC16i16 = 130, + X86_ADC16mi = 131, + X86_ADC16mi8 = 132, + X86_ADC16mr = 133, + X86_ADC16ri = 134, + X86_ADC16ri8 = 135, + X86_ADC16rm = 136, + X86_ADC16rr = 137, + X86_ADC16rr_REV = 138, + X86_ADC32i32 = 139, + X86_ADC32mi = 140, + X86_ADC32mi8 = 141, + X86_ADC32mr = 142, + X86_ADC32ri = 143, + X86_ADC32ri8 = 144, + X86_ADC32rm = 145, + X86_ADC32rr = 146, + X86_ADC32rr_REV = 147, + X86_ADC64i32 = 148, + X86_ADC64mi32 = 149, + X86_ADC64mi8 = 150, + X86_ADC64mr = 151, + X86_ADC64ri32 = 152, + X86_ADC64ri8 = 153, + X86_ADC64rm = 154, + X86_ADC64rr = 155, + X86_ADC64rr_REV = 156, + X86_ADC8i8 = 157, + X86_ADC8mi = 158, + X86_ADC8mi8 = 159, + X86_ADC8mr = 160, + X86_ADC8ri = 161, + X86_ADC8ri8 = 162, + X86_ADC8rm = 163, + X86_ADC8rr = 164, + X86_ADC8rr_REV = 165, + X86_ADCX32rm = 166, + X86_ADCX32rr = 167, + X86_ADCX64rm = 168, + X86_ADCX64rr = 169, + X86_ADD16i16 = 170, + X86_ADD16mi = 171, + X86_ADD16mi8 = 172, + X86_ADD16mr = 173, + X86_ADD16ri = 174, + X86_ADD16ri8 = 175, + X86_ADD16rm = 176, + X86_ADD16rr = 177, + X86_ADD16rr_REV = 178, + X86_ADD32i32 = 179, + X86_ADD32mi = 180, + X86_ADD32mi8 = 181, + X86_ADD32mr = 182, + X86_ADD32ri = 183, + X86_ADD32ri8 = 184, + X86_ADD32rm = 185, + X86_ADD32rr = 186, + X86_ADD32rr_REV = 187, + X86_ADD64i32 = 188, + X86_ADD64mi32 = 189, + X86_ADD64mi8 = 190, + X86_ADD64mr = 191, + X86_ADD64ri32 = 192, + X86_ADD64ri8 = 193, + X86_ADD64rm = 194, + X86_ADD64rr = 195, + X86_ADD64rr_REV = 196, + X86_ADD8i8 = 197, + X86_ADD8mi = 198, + X86_ADD8mi8 = 199, + X86_ADD8mr = 200, + X86_ADD8ri = 201, + X86_ADD8ri8 = 202, + X86_ADD8rm = 203, + X86_ADD8rr = 204, + X86_ADD8rr_REV = 205, + X86_ADOX32rm = 206, + X86_ADOX32rr = 207, + X86_ADOX64rm = 208, + X86_ADOX64rr = 209, + X86_AND16i16 = 210, + X86_AND16mi = 211, + X86_AND16mi8 = 212, + X86_AND16mr = 213, + X86_AND16ri = 214, + X86_AND16ri8 = 215, + X86_AND16rm = 216, + X86_AND16rr = 217, + X86_AND16rr_REV = 218, + X86_AND32i32 = 219, + X86_AND32mi = 220, + X86_AND32mi8 = 221, + X86_AND32mr = 222, + X86_AND32ri = 223, + X86_AND32ri8 = 224, + X86_AND32rm = 225, + X86_AND32rr = 226, + X86_AND32rr_REV = 227, + X86_AND64i32 = 228, + X86_AND64mi32 = 229, + X86_AND64mi8 = 230, + X86_AND64mr = 231, + X86_AND64ri32 = 232, + X86_AND64ri8 = 233, + X86_AND64rm = 234, + X86_AND64rr = 235, + X86_AND64rr_REV = 236, + X86_AND8i8 = 237, + X86_AND8mi = 238, + X86_AND8mi8 = 239, + X86_AND8mr = 240, + X86_AND8ri = 241, + X86_AND8ri8 = 242, + X86_AND8rm = 243, + X86_AND8rr = 244, + X86_AND8rr_REV = 245, + X86_ANDN32rm = 246, + X86_ANDN32rr = 247, + X86_ANDN64rm = 248, + X86_ANDN64rr = 249, + X86_ARPL16mr = 250, + X86_ARPL16rr = 251, + X86_BEXTR32rm = 252, + X86_BEXTR32rr = 253, + X86_BEXTR64rm = 254, + X86_BEXTR64rr = 255, + X86_BEXTRI32mi = 256, + X86_BEXTRI32ri = 257, + X86_BEXTRI64mi = 258, + X86_BEXTRI64ri = 259, + X86_BLCFILL32rm = 260, + X86_BLCFILL32rr = 261, + X86_BLCFILL64rm = 262, + X86_BLCFILL64rr = 263, + X86_BLCI32rm = 264, + X86_BLCI32rr = 265, + X86_BLCI64rm = 266, + X86_BLCI64rr = 267, + X86_BLCIC32rm = 268, + X86_BLCIC32rr = 269, + X86_BLCIC64rm = 270, + X86_BLCIC64rr = 271, + X86_BLCMSK32rm = 272, + X86_BLCMSK32rr = 273, + X86_BLCMSK64rm = 274, + X86_BLCMSK64rr = 275, + X86_BLCS32rm = 276, + X86_BLCS32rr = 277, + X86_BLCS64rm = 278, + X86_BLCS64rr = 279, + X86_BLSFILL32rm = 280, + X86_BLSFILL32rr = 281, + X86_BLSFILL64rm = 282, + X86_BLSFILL64rr = 283, + X86_BLSI32rm = 284, + X86_BLSI32rr = 285, + X86_BLSI64rm = 286, + X86_BLSI64rr = 287, + X86_BLSIC32rm = 288, + X86_BLSIC32rr = 289, + X86_BLSIC64rm = 290, + X86_BLSIC64rr = 291, + X86_BLSMSK32rm = 292, + X86_BLSMSK32rr = 293, + X86_BLSMSK64rm = 294, + X86_BLSMSK64rr = 295, + X86_BLSR32rm = 296, + X86_BLSR32rr = 297, + X86_BLSR64rm = 298, + X86_BLSR64rr = 299, + X86_BOUNDS16rm = 300, + X86_BOUNDS32rm = 301, + X86_BSF16rm = 302, + X86_BSF16rr = 303, + X86_BSF32rm = 304, + X86_BSF32rr = 305, + X86_BSF64rm = 306, + X86_BSF64rr = 307, + X86_BSR16rm = 308, + X86_BSR16rr = 309, + X86_BSR32rm = 310, + X86_BSR32rr = 311, + X86_BSR64rm = 312, + X86_BSR64rr = 313, + X86_BSWAP16r_BAD = 314, + X86_BSWAP32r = 315, + X86_BSWAP64r = 316, + X86_BT16mi8 = 317, + X86_BT16mr = 318, + X86_BT16ri8 = 319, + X86_BT16rr = 320, + X86_BT32mi8 = 321, + X86_BT32mr = 322, + X86_BT32ri8 = 323, + X86_BT32rr = 324, + X86_BT64mi8 = 325, + X86_BT64mr = 326, + X86_BT64ri8 = 327, + X86_BT64rr = 328, + X86_BTC16mi8 = 329, + X86_BTC16mr = 330, + X86_BTC16ri8 = 331, + X86_BTC16rr = 332, + X86_BTC32mi8 = 333, + X86_BTC32mr = 334, + X86_BTC32ri8 = 335, + X86_BTC32rr = 336, + X86_BTC64mi8 = 337, + X86_BTC64mr = 338, + X86_BTC64ri8 = 339, + X86_BTC64rr = 340, + X86_BTR16mi8 = 341, + X86_BTR16mr = 342, + X86_BTR16ri8 = 343, + X86_BTR16rr = 344, + X86_BTR32mi8 = 345, + X86_BTR32mr = 346, + X86_BTR32ri8 = 347, + X86_BTR32rr = 348, + X86_BTR64mi8 = 349, + X86_BTR64mr = 350, + X86_BTR64ri8 = 351, + X86_BTR64rr = 352, + X86_BTS16mi8 = 353, + X86_BTS16mr = 354, + X86_BTS16ri8 = 355, + X86_BTS16rr = 356, + X86_BTS32mi8 = 357, + X86_BTS32mr = 358, + X86_BTS32ri8 = 359, + X86_BTS32rr = 360, + X86_BTS64mi8 = 361, + X86_BTS64mr = 362, + X86_BTS64ri8 = 363, + X86_BTS64rr = 364, + X86_BZHI32rm = 365, + X86_BZHI32rr = 366, + X86_BZHI64rm = 367, + X86_BZHI64rr = 368, + X86_CALL16m = 369, + X86_CALL16m_NT = 370, + X86_CALL16r = 371, + X86_CALL16r_NT = 372, + X86_CALL32m = 373, + X86_CALL32m_NT = 374, + X86_CALL32r = 375, + X86_CALL32r_NT = 376, + X86_CALL64m = 377, + X86_CALL64m_NT = 378, + X86_CALL64pcrel32 = 379, + X86_CALL64r = 380, + X86_CALL64r_NT = 381, + X86_CALLpcrel16 = 382, + X86_CALLpcrel32 = 383, + X86_CBW = 384, + X86_CDQ = 385, + X86_CDQE = 386, + X86_CLAC = 387, + X86_CLC = 388, + X86_CLD = 389, + X86_CLDEMOTE = 390, + X86_CLFLUSHOPT = 391, + X86_CLGI = 392, + X86_CLI = 393, + X86_CLRSSBSY = 394, + X86_CLTS = 395, + X86_CLWB = 396, + X86_CLZEROr = 397, + X86_CMC = 398, + X86_CMOVA16rm = 399, + X86_CMOVA16rr = 400, + X86_CMOVA32rm = 401, + X86_CMOVA32rr = 402, + X86_CMOVA64rm = 403, + X86_CMOVA64rr = 404, + X86_CMOVAE16rm = 405, + X86_CMOVAE16rr = 406, + X86_CMOVAE32rm = 407, + X86_CMOVAE32rr = 408, + X86_CMOVAE64rm = 409, + X86_CMOVAE64rr = 410, + X86_CMOVB16rm = 411, + X86_CMOVB16rr = 412, + X86_CMOVB32rm = 413, + X86_CMOVB32rr = 414, + X86_CMOVB64rm = 415, + X86_CMOVB64rr = 416, + X86_CMOVBE16rm = 417, + X86_CMOVBE16rr = 418, + X86_CMOVBE32rm = 419, + X86_CMOVBE32rr = 420, + X86_CMOVBE64rm = 421, + X86_CMOVBE64rr = 422, + X86_CMOVE16rm = 423, + X86_CMOVE16rr = 424, + X86_CMOVE32rm = 425, + X86_CMOVE32rr = 426, + X86_CMOVE64rm = 427, + X86_CMOVE64rr = 428, + X86_CMOVG16rm = 429, + X86_CMOVG16rr = 430, + X86_CMOVG32rm = 431, + X86_CMOVG32rr = 432, + X86_CMOVG64rm = 433, + X86_CMOVG64rr = 434, + X86_CMOVGE16rm = 435, + X86_CMOVGE16rr = 436, + X86_CMOVGE32rm = 437, + X86_CMOVGE32rr = 438, + X86_CMOVGE64rm = 439, + X86_CMOVGE64rr = 440, + X86_CMOVL16rm = 441, + X86_CMOVL16rr = 442, + X86_CMOVL32rm = 443, + X86_CMOVL32rr = 444, + X86_CMOVL64rm = 445, + X86_CMOVL64rr = 446, + X86_CMOVLE16rm = 447, + X86_CMOVLE16rr = 448, + X86_CMOVLE32rm = 449, + X86_CMOVLE32rr = 450, + X86_CMOVLE64rm = 451, + X86_CMOVLE64rr = 452, + X86_CMOVNE16rm = 453, + X86_CMOVNE16rr = 454, + X86_CMOVNE32rm = 455, + X86_CMOVNE32rr = 456, + X86_CMOVNE64rm = 457, + X86_CMOVNE64rr = 458, + X86_CMOVNO16rm = 459, + X86_CMOVNO16rr = 460, + X86_CMOVNO32rm = 461, + X86_CMOVNO32rr = 462, + X86_CMOVNO64rm = 463, + X86_CMOVNO64rr = 464, + X86_CMOVNP16rm = 465, + X86_CMOVNP16rr = 466, + X86_CMOVNP32rm = 467, + X86_CMOVNP32rr = 468, + X86_CMOVNP64rm = 469, + X86_CMOVNP64rr = 470, + X86_CMOVNS16rm = 471, + X86_CMOVNS16rr = 472, + X86_CMOVNS32rm = 473, + X86_CMOVNS32rr = 474, + X86_CMOVNS64rm = 475, + X86_CMOVNS64rr = 476, + X86_CMOVO16rm = 477, + X86_CMOVO16rr = 478, + X86_CMOVO32rm = 479, + X86_CMOVO32rr = 480, + X86_CMOVO64rm = 481, + X86_CMOVO64rr = 482, + X86_CMOVP16rm = 483, + X86_CMOVP16rr = 484, + X86_CMOVP32rm = 485, + X86_CMOVP32rr = 486, + X86_CMOVP64rm = 487, + X86_CMOVP64rr = 488, + X86_CMOVS16rm = 489, + X86_CMOVS16rr = 490, + X86_CMOVS32rm = 491, + X86_CMOVS32rr = 492, + X86_CMOVS64rm = 493, + X86_CMOVS64rr = 494, + X86_CMP16i16 = 495, + X86_CMP16mi = 496, + X86_CMP16mi8 = 497, + X86_CMP16mr = 498, + X86_CMP16ri = 499, + X86_CMP16ri8 = 500, + X86_CMP16rm = 501, + X86_CMP16rr = 502, + X86_CMP16rr_REV = 503, + X86_CMP32i32 = 504, + X86_CMP32mi = 505, + X86_CMP32mi8 = 506, + X86_CMP32mr = 507, + X86_CMP32ri = 508, + X86_CMP32ri8 = 509, + X86_CMP32rm = 510, + X86_CMP32rr = 511, + X86_CMP32rr_REV = 512, + X86_CMP64i32 = 513, + X86_CMP64mi32 = 514, + X86_CMP64mi8 = 515, + X86_CMP64mr = 516, + X86_CMP64ri32 = 517, + X86_CMP64ri8 = 518, + X86_CMP64rm = 519, + X86_CMP64rr = 520, + X86_CMP64rr_REV = 521, + X86_CMP8i8 = 522, + X86_CMP8mi = 523, + X86_CMP8mi8 = 524, + X86_CMP8mr = 525, + X86_CMP8ri = 526, + X86_CMP8ri8 = 527, + X86_CMP8rm = 528, + X86_CMP8rr = 529, + X86_CMP8rr_REV = 530, + X86_CMPSB = 531, + X86_CMPSL = 532, + X86_CMPSQ = 533, + X86_CMPSW = 534, + X86_CMPXCHG16B = 535, + X86_CMPXCHG16rm = 536, + X86_CMPXCHG16rr = 537, + X86_CMPXCHG32rm = 538, + X86_CMPXCHG32rr = 539, + X86_CMPXCHG64rm = 540, + X86_CMPXCHG64rr = 541, + X86_CMPXCHG8B = 542, + X86_CMPXCHG8rm = 543, + X86_CMPXCHG8rr = 544, + X86_CPUID = 545, + X86_CQO = 546, + X86_CWD = 547, + X86_CWDE = 548, + X86_DAA = 549, + X86_DAS = 550, + X86_DATA16_PREFIX = 551, + X86_DEC16m = 552, + X86_DEC16r = 553, + X86_DEC16r_alt = 554, + X86_DEC32m = 555, + X86_DEC32r = 556, + X86_DEC32r_alt = 557, + X86_DEC64m = 558, + X86_DEC64r = 559, + X86_DEC8m = 560, + X86_DEC8r = 561, + X86_DIV16m = 562, + X86_DIV16r = 563, + X86_DIV32m = 564, + X86_DIV32r = 565, + X86_DIV64m = 566, + X86_DIV64r = 567, + X86_DIV8m = 568, + X86_DIV8r = 569, + X86_ENDBR32 = 570, + X86_ENDBR64 = 571, + X86_ENTER = 572, + X86_FARCALL16i = 573, + X86_FARCALL16m = 574, + X86_FARCALL32i = 575, + X86_FARCALL32m = 576, + X86_FARCALL64 = 577, + X86_FARJMP16i = 578, + X86_FARJMP16m = 579, + X86_FARJMP32i = 580, + X86_FARJMP32m = 581, + X86_FARJMP64 = 582, + X86_FSETPM = 583, + X86_GETSEC = 584, + X86_HLT = 585, + X86_IDIV16m = 586, + X86_IDIV16r = 587, + X86_IDIV32m = 588, + X86_IDIV32r = 589, + X86_IDIV64m = 590, + X86_IDIV64r = 591, + X86_IDIV8m = 592, + X86_IDIV8r = 593, + X86_IMUL16m = 594, + X86_IMUL16r = 595, + X86_IMUL16rm = 596, + X86_IMUL16rmi = 597, + X86_IMUL16rmi8 = 598, + X86_IMUL16rr = 599, + X86_IMUL16rri = 600, + X86_IMUL16rri8 = 601, + X86_IMUL32m = 602, + X86_IMUL32r = 603, + X86_IMUL32rm = 604, + X86_IMUL32rmi = 605, + X86_IMUL32rmi8 = 606, + X86_IMUL32rr = 607, + X86_IMUL32rri = 608, + X86_IMUL32rri8 = 609, + X86_IMUL64m = 610, + X86_IMUL64r = 611, + X86_IMUL64rm = 612, + X86_IMUL64rmi32 = 613, + X86_IMUL64rmi8 = 614, + X86_IMUL64rr = 615, + X86_IMUL64rri32 = 616, + X86_IMUL64rri8 = 617, + X86_IMUL8m = 618, + X86_IMUL8r = 619, + X86_IN16ri = 620, + X86_IN16rr = 621, + X86_IN32ri = 622, + X86_IN32rr = 623, + X86_IN8ri = 624, + X86_IN8rr = 625, + X86_INC16m = 626, + X86_INC16r = 627, + X86_INC16r_alt = 628, + X86_INC32m = 629, + X86_INC32r = 630, + X86_INC32r_alt = 631, + X86_INC64m = 632, + X86_INC64r = 633, + X86_INC8m = 634, + X86_INC8r = 635, + X86_INCSSPD = 636, + X86_INCSSPQ = 637, + X86_INSB = 638, + X86_INSL = 639, + X86_INSW = 640, + X86_INT = 641, + X86_INT1 = 642, + X86_INT3 = 643, + X86_INTO = 644, + X86_INVD = 645, + X86_INVEPT32 = 646, + X86_INVEPT64 = 647, + X86_INVLPG = 648, + X86_INVLPGA32 = 649, + X86_INVLPGA64 = 650, + X86_INVPCID32 = 651, + X86_INVPCID64 = 652, + X86_INVVPID32 = 653, + X86_INVVPID64 = 654, + X86_IRET16 = 655, + X86_IRET32 = 656, + X86_IRET64 = 657, + X86_JAE_1 = 658, + X86_JAE_2 = 659, + X86_JAE_4 = 660, + X86_JA_1 = 661, + X86_JA_2 = 662, + X86_JA_4 = 663, + X86_JBE_1 = 664, + X86_JBE_2 = 665, + X86_JBE_4 = 666, + X86_JB_1 = 667, + X86_JB_2 = 668, + X86_JB_4 = 669, + X86_JCXZ = 670, + X86_JECXZ = 671, + X86_JE_1 = 672, + X86_JE_2 = 673, + X86_JE_4 = 674, + X86_JGE_1 = 675, + X86_JGE_2 = 676, + X86_JGE_4 = 677, + X86_JG_1 = 678, + X86_JG_2 = 679, + X86_JG_4 = 680, + X86_JLE_1 = 681, + X86_JLE_2 = 682, + X86_JLE_4 = 683, + X86_JL_1 = 684, + X86_JL_2 = 685, + X86_JL_4 = 686, + X86_JMP16m = 687, + X86_JMP16m_NT = 688, + X86_JMP16r = 689, + X86_JMP16r_NT = 690, + X86_JMP32m = 691, + X86_JMP32m_NT = 692, + X86_JMP32r = 693, + X86_JMP32r_NT = 694, + X86_JMP64m = 695, + X86_JMP64m_NT = 696, + X86_JMP64r = 697, + X86_JMP64r_NT = 698, + X86_JMP_1 = 699, + X86_JMP_2 = 700, + X86_JMP_4 = 701, + X86_JNE_1 = 702, + X86_JNE_2 = 703, + X86_JNE_4 = 704, + X86_JNO_1 = 705, + X86_JNO_2 = 706, + X86_JNO_4 = 707, + X86_JNP_1 = 708, + X86_JNP_2 = 709, + X86_JNP_4 = 710, + X86_JNS_1 = 711, + X86_JNS_2 = 712, + X86_JNS_4 = 713, + X86_JO_1 = 714, + X86_JO_2 = 715, + X86_JO_4 = 716, + X86_JP_1 = 717, + X86_JP_2 = 718, + X86_JP_4 = 719, + X86_JRCXZ = 720, + X86_JS_1 = 721, + X86_JS_2 = 722, + X86_JS_4 = 723, + X86_LAHF = 724, + X86_LAR16rm = 725, + X86_LAR16rr = 726, + X86_LAR32rm = 727, + X86_LAR32rr = 728, + X86_LAR64rm = 729, + X86_LAR64rr = 730, + X86_LDS16rm = 731, + X86_LDS32rm = 732, + X86_LEA16r = 733, + X86_LEA32r = 734, + X86_LEA64_32r = 735, + X86_LEA64r = 736, + X86_LEAVE = 737, + X86_LEAVE64 = 738, + X86_LES16rm = 739, + X86_LES32rm = 740, + X86_LFS16rm = 741, + X86_LFS32rm = 742, + X86_LFS64rm = 743, + X86_LGDT16m = 744, + X86_LGDT32m = 745, + X86_LGDT64m = 746, + X86_LGS16rm = 747, + X86_LGS32rm = 748, + X86_LGS64rm = 749, + X86_LIDT16m = 750, + X86_LIDT32m = 751, + X86_LIDT64m = 752, + X86_LLDT16m = 753, + X86_LLDT16r = 754, + X86_LLWPCB = 755, + X86_LLWPCB64 = 756, + X86_LMSW16m = 757, + X86_LMSW16r = 758, + X86_LOCK_PREFIX = 759, + X86_LODSB = 760, + X86_LODSL = 761, + X86_LODSQ = 762, + X86_LODSW = 763, + X86_LOOP = 764, + X86_LOOPE = 765, + X86_LOOPNE = 766, + X86_LRETIL = 767, + X86_LRETIQ = 768, + X86_LRETIW = 769, + X86_LRETL = 770, + X86_LRETQ = 771, + X86_LRETW = 772, + X86_LSL16rm = 773, + X86_LSL16rr = 774, + X86_LSL32rm = 775, + X86_LSL32rr = 776, + X86_LSL64rm = 777, + X86_LSL64rr = 778, + X86_LSS16rm = 779, + X86_LSS32rm = 780, + X86_LSS64rm = 781, + X86_LTRm = 782, + X86_LTRr = 783, + X86_LWPINS32rmi = 784, + X86_LWPINS32rri = 785, + X86_LWPINS64rmi = 786, + X86_LWPINS64rri = 787, + X86_LWPVAL32rmi = 788, + X86_LWPVAL32rri = 789, + X86_LWPVAL64rmi = 790, + X86_LWPVAL64rri = 791, + X86_LZCNT16rm = 792, + X86_LZCNT16rr = 793, + X86_LZCNT32rm = 794, + X86_LZCNT32rr = 795, + X86_LZCNT64rm = 796, + X86_LZCNT64rr = 797, + X86_MONITORXrrr = 798, + X86_MONTMUL = 799, + X86_MOV16ao16 = 800, + X86_MOV16ao32 = 801, + X86_MOV16ao64 = 802, + X86_MOV16mi = 803, + X86_MOV16mr = 804, + X86_MOV16ms = 805, + X86_MOV16o16a = 806, + X86_MOV16o32a = 807, + X86_MOV16o64a = 808, + X86_MOV16ri = 809, + X86_MOV16ri_alt = 810, + X86_MOV16rm = 811, + X86_MOV16rr = 812, + X86_MOV16rr_REV = 813, + X86_MOV16rs = 814, + X86_MOV16sm = 815, + X86_MOV16sr = 816, + X86_MOV32ao16 = 817, + X86_MOV32ao32 = 818, + X86_MOV32ao64 = 819, + X86_MOV32cr = 820, + X86_MOV32dr = 821, + X86_MOV32mi = 822, + X86_MOV32mr = 823, + X86_MOV32o16a = 824, + X86_MOV32o32a = 825, + X86_MOV32o64a = 826, + X86_MOV32rc = 827, + X86_MOV32rd = 828, + X86_MOV32ri = 829, + X86_MOV32ri_alt = 830, + X86_MOV32rm = 831, + X86_MOV32rr = 832, + X86_MOV32rr_REV = 833, + X86_MOV32rs = 834, + X86_MOV32sr = 835, + X86_MOV64ao32 = 836, + X86_MOV64ao64 = 837, + X86_MOV64cr = 838, + X86_MOV64dr = 839, + X86_MOV64mi32 = 840, + X86_MOV64mr = 841, + X86_MOV64o32a = 842, + X86_MOV64o64a = 843, + X86_MOV64rc = 844, + X86_MOV64rd = 845, + X86_MOV64ri = 846, + X86_MOV64ri32 = 847, + X86_MOV64rm = 848, + X86_MOV64rr = 849, + X86_MOV64rr_REV = 850, + X86_MOV64rs = 851, + X86_MOV64sr = 852, + X86_MOV8ao16 = 853, + X86_MOV8ao32 = 854, + X86_MOV8ao64 = 855, + X86_MOV8mi = 856, + X86_MOV8mr = 857, + X86_MOV8mr_NOREX = 858, + X86_MOV8o16a = 859, + X86_MOV8o32a = 860, + X86_MOV8o64a = 861, + X86_MOV8ri = 862, + X86_MOV8ri_alt = 863, + X86_MOV8rm = 864, + X86_MOV8rm_NOREX = 865, + X86_MOV8rr = 866, + X86_MOV8rr_NOREX = 867, + X86_MOV8rr_REV = 868, + X86_MOVBE16mr = 869, + X86_MOVBE16rm = 870, + X86_MOVBE32mr = 871, + X86_MOVBE32rm = 872, + X86_MOVBE64mr = 873, + X86_MOVBE64rm = 874, + X86_MOVDIR64B16 = 875, + X86_MOVDIR64B32 = 876, + X86_MOVDIR64B64 = 877, + X86_MOVDIRI32 = 878, + X86_MOVDIRI64 = 879, + X86_MOVSB = 880, + X86_MOVSL = 881, + X86_MOVSQ = 882, + X86_MOVSW = 883, + X86_MOVSX16rm16 = 884, + X86_MOVSX16rm8 = 885, + X86_MOVSX16rr16 = 886, + X86_MOVSX16rr8 = 887, + X86_MOVSX32rm16 = 888, + X86_MOVSX32rm8 = 889, + X86_MOVSX32rm8_NOREX = 890, + X86_MOVSX32rr16 = 891, + X86_MOVSX32rr8 = 892, + X86_MOVSX32rr8_NOREX = 893, + X86_MOVSX64rm16 = 894, + X86_MOVSX64rm32 = 895, + X86_MOVSX64rm8 = 896, + X86_MOVSX64rr16 = 897, + X86_MOVSX64rr32 = 898, + X86_MOVSX64rr8 = 899, + X86_MOVZX16rm16 = 900, + X86_MOVZX16rm8 = 901, + X86_MOVZX16rr16 = 902, + X86_MOVZX16rr8 = 903, + X86_MOVZX32rm16 = 904, + X86_MOVZX32rm8 = 905, + X86_MOVZX32rm8_NOREX = 906, + X86_MOVZX32rr16 = 907, + X86_MOVZX32rr8 = 908, + X86_MOVZX32rr8_NOREX = 909, + X86_MOVZX64rm16 = 910, + X86_MOVZX64rm8 = 911, + X86_MOVZX64rr16 = 912, + X86_MOVZX64rr8 = 913, + X86_MUL16m = 914, + X86_MUL16r = 915, + X86_MUL32m = 916, + X86_MUL32r = 917, + X86_MUL64m = 918, + X86_MUL64r = 919, + X86_MUL8m = 920, + X86_MUL8r = 921, + X86_MULX32rm = 922, + X86_MULX32rr = 923, + X86_MULX64rm = 924, + X86_MULX64rr = 925, + X86_MWAITXrrr = 926, + X86_NEG16m = 927, + X86_NEG16r = 928, + X86_NEG32m = 929, + X86_NEG32r = 930, + X86_NEG64m = 931, + X86_NEG64r = 932, + X86_NEG8m = 933, + X86_NEG8r = 934, + X86_NOOP = 935, + X86_NOOP18_16m4 = 936, + X86_NOOP18_16m5 = 937, + X86_NOOP18_16m6 = 938, + X86_NOOP18_16m7 = 939, + X86_NOOP18_16r4 = 940, + X86_NOOP18_16r5 = 941, + X86_NOOP18_16r6 = 942, + X86_NOOP18_16r7 = 943, + X86_NOOP18_m4 = 944, + X86_NOOP18_m5 = 945, + X86_NOOP18_m6 = 946, + X86_NOOP18_m7 = 947, + X86_NOOP18_r4 = 948, + X86_NOOP18_r5 = 949, + X86_NOOP18_r6 = 950, + X86_NOOP18_r7 = 951, + X86_NOOP19rr = 952, + X86_NOOPL = 953, + X86_NOOPL_19 = 954, + X86_NOOPL_1d = 955, + X86_NOOPL_1e = 956, + X86_NOOPLr = 957, + X86_NOOPQ = 958, + X86_NOOPQr = 959, + X86_NOOPW = 960, + X86_NOOPW_19 = 961, + X86_NOOPW_1c = 962, + X86_NOOPW_1d = 963, + X86_NOOPW_1e = 964, + X86_NOOPWr = 965, + X86_NOT16m = 966, + X86_NOT16r = 967, + X86_NOT32m = 968, + X86_NOT32r = 969, + X86_NOT64m = 970, + X86_NOT64r = 971, + X86_NOT8m = 972, + X86_NOT8r = 973, + X86_OR16i16 = 974, + X86_OR16mi = 975, + X86_OR16mi8 = 976, + X86_OR16mr = 977, + X86_OR16ri = 978, + X86_OR16ri8 = 979, + X86_OR16rm = 980, + X86_OR16rr = 981, + X86_OR16rr_REV = 982, + X86_OR32i32 = 983, + X86_OR32mi = 984, + X86_OR32mi8 = 985, + X86_OR32mr = 986, + X86_OR32ri = 987, + X86_OR32ri8 = 988, + X86_OR32rm = 989, + X86_OR32rr = 990, + X86_OR32rr_REV = 991, + X86_OR64i32 = 992, + X86_OR64mi32 = 993, + X86_OR64mi8 = 994, + X86_OR64mr = 995, + X86_OR64ri32 = 996, + X86_OR64ri8 = 997, + X86_OR64rm = 998, + X86_OR64rr = 999, + X86_OR64rr_REV = 1000, + X86_OR8i8 = 1001, + X86_OR8mi = 1002, + X86_OR8mi8 = 1003, + X86_OR8mr = 1004, + X86_OR8ri = 1005, + X86_OR8ri8 = 1006, + X86_OR8rm = 1007, + X86_OR8rr = 1008, + X86_OR8rr_REV = 1009, + X86_OUT16ir = 1010, + X86_OUT16rr = 1011, + X86_OUT32ir = 1012, + X86_OUT32rr = 1013, + X86_OUT8ir = 1014, + X86_OUT8rr = 1015, + X86_OUTSB = 1016, + X86_OUTSL = 1017, + X86_OUTSW = 1018, + X86_PCONFIG = 1019, + X86_PDEP32rm = 1020, + X86_PDEP32rr = 1021, + X86_PDEP64rm = 1022, + X86_PDEP64rr = 1023, + X86_PEXT32rm = 1024, + X86_PEXT32rr = 1025, + X86_PEXT64rm = 1026, + X86_PEXT64rr = 1027, + X86_POP16r = 1028, + X86_POP16rmm = 1029, + X86_POP16rmr = 1030, + X86_POP32r = 1031, + X86_POP32rmm = 1032, + X86_POP32rmr = 1033, + X86_POP64r = 1034, + X86_POP64rmm = 1035, + X86_POP64rmr = 1036, + X86_POPA16 = 1037, + X86_POPA32 = 1038, + X86_POPDS16 = 1039, + X86_POPDS32 = 1040, + X86_POPES16 = 1041, + X86_POPES32 = 1042, + X86_POPF16 = 1043, + X86_POPF32 = 1044, + X86_POPF64 = 1045, + X86_POPFS16 = 1046, + X86_POPFS32 = 1047, + X86_POPFS64 = 1048, + X86_POPGS16 = 1049, + X86_POPGS32 = 1050, + X86_POPGS64 = 1051, + X86_POPSS16 = 1052, + X86_POPSS32 = 1053, + X86_PTWRITE64m = 1054, + X86_PTWRITE64r = 1055, + X86_PTWRITEm = 1056, + X86_PTWRITEr = 1057, + X86_PUSH16i8 = 1058, + X86_PUSH16r = 1059, + X86_PUSH16rmm = 1060, + X86_PUSH16rmr = 1061, + X86_PUSH32i8 = 1062, + X86_PUSH32r = 1063, + X86_PUSH32rmm = 1064, + X86_PUSH32rmr = 1065, + X86_PUSH64i32 = 1066, + X86_PUSH64i8 = 1067, + X86_PUSH64r = 1068, + X86_PUSH64rmm = 1069, + X86_PUSH64rmr = 1070, + X86_PUSHA16 = 1071, + X86_PUSHA32 = 1072, + X86_PUSHCS16 = 1073, + X86_PUSHCS32 = 1074, + X86_PUSHDS16 = 1075, + X86_PUSHDS32 = 1076, + X86_PUSHES16 = 1077, + X86_PUSHES32 = 1078, + X86_PUSHF16 = 1079, + X86_PUSHF32 = 1080, + X86_PUSHF64 = 1081, + X86_PUSHFS16 = 1082, + X86_PUSHFS32 = 1083, + X86_PUSHFS64 = 1084, + X86_PUSHGS16 = 1085, + X86_PUSHGS32 = 1086, + X86_PUSHGS64 = 1087, + X86_PUSHSS16 = 1088, + X86_PUSHSS32 = 1089, + X86_PUSHi16 = 1090, + X86_PUSHi32 = 1091, + X86_RCL16m1 = 1092, + X86_RCL16mCL = 1093, + X86_RCL16mi = 1094, + X86_RCL16r1 = 1095, + X86_RCL16rCL = 1096, + X86_RCL16ri = 1097, + X86_RCL32m1 = 1098, + X86_RCL32mCL = 1099, + X86_RCL32mi = 1100, + X86_RCL32r1 = 1101, + X86_RCL32rCL = 1102, + X86_RCL32ri = 1103, + X86_RCL64m1 = 1104, + X86_RCL64mCL = 1105, + X86_RCL64mi = 1106, + X86_RCL64r1 = 1107, + X86_RCL64rCL = 1108, + X86_RCL64ri = 1109, + X86_RCL8m1 = 1110, + X86_RCL8mCL = 1111, + X86_RCL8mi = 1112, + X86_RCL8r1 = 1113, + X86_RCL8rCL = 1114, + X86_RCL8ri = 1115, + X86_RCR16m1 = 1116, + X86_RCR16mCL = 1117, + X86_RCR16mi = 1118, + X86_RCR16r1 = 1119, + X86_RCR16rCL = 1120, + X86_RCR16ri = 1121, + X86_RCR32m1 = 1122, + X86_RCR32mCL = 1123, + X86_RCR32mi = 1124, + X86_RCR32r1 = 1125, + X86_RCR32rCL = 1126, + X86_RCR32ri = 1127, + X86_RCR64m1 = 1128, + X86_RCR64mCL = 1129, + X86_RCR64mi = 1130, + X86_RCR64r1 = 1131, + X86_RCR64rCL = 1132, + X86_RCR64ri = 1133, + X86_RCR8m1 = 1134, + X86_RCR8mCL = 1135, + X86_RCR8mi = 1136, + X86_RCR8r1 = 1137, + X86_RCR8rCL = 1138, + X86_RCR8ri = 1139, + X86_RDFSBASE = 1140, + X86_RDFSBASE64 = 1141, + X86_RDGSBASE = 1142, + X86_RDGSBASE64 = 1143, + X86_RDMSR = 1144, + X86_RDPID32 = 1145, + X86_RDPID64 = 1146, + X86_RDPKRUr = 1147, + X86_RDPMC = 1148, + X86_RDRAND16r = 1149, + X86_RDRAND32r = 1150, + X86_RDRAND64r = 1151, + X86_RDSEED16r = 1152, + X86_RDSEED32r = 1153, + X86_RDSEED64r = 1154, + X86_RDSSPD = 1155, + X86_RDSSPQ = 1156, + X86_RDTSC = 1157, + X86_RDTSCP = 1158, + X86_REPNE_PREFIX = 1159, + X86_REP_PREFIX = 1160, + X86_RETIL = 1161, + X86_RETIQ = 1162, + X86_RETIW = 1163, + X86_RETL = 1164, + X86_RETQ = 1165, + X86_RETW = 1166, + X86_REX64_PREFIX = 1167, + X86_ROL16m1 = 1168, + X86_ROL16mCL = 1169, + X86_ROL16mi = 1170, + X86_ROL16r1 = 1171, + X86_ROL16rCL = 1172, + X86_ROL16ri = 1173, + X86_ROL32m1 = 1174, + X86_ROL32mCL = 1175, + X86_ROL32mi = 1176, + X86_ROL32r1 = 1177, + X86_ROL32rCL = 1178, + X86_ROL32ri = 1179, + X86_ROL64m1 = 1180, + X86_ROL64mCL = 1181, + X86_ROL64mi = 1182, + X86_ROL64r1 = 1183, + X86_ROL64rCL = 1184, + X86_ROL64ri = 1185, + X86_ROL8m1 = 1186, + X86_ROL8mCL = 1187, + X86_ROL8mi = 1188, + X86_ROL8r1 = 1189, + X86_ROL8rCL = 1190, + X86_ROL8ri = 1191, + X86_ROR16m1 = 1192, + X86_ROR16mCL = 1193, + X86_ROR16mi = 1194, + X86_ROR16r1 = 1195, + X86_ROR16rCL = 1196, + X86_ROR16ri = 1197, + X86_ROR32m1 = 1198, + X86_ROR32mCL = 1199, + X86_ROR32mi = 1200, + X86_ROR32r1 = 1201, + X86_ROR32rCL = 1202, + X86_ROR32ri = 1203, + X86_ROR64m1 = 1204, + X86_ROR64mCL = 1205, + X86_ROR64mi = 1206, + X86_ROR64r1 = 1207, + X86_ROR64rCL = 1208, + X86_ROR64ri = 1209, + X86_ROR8m1 = 1210, + X86_ROR8mCL = 1211, + X86_ROR8mi = 1212, + X86_ROR8r1 = 1213, + X86_ROR8rCL = 1214, + X86_ROR8ri = 1215, + X86_RORX32mi = 1216, + X86_RORX32ri = 1217, + X86_RORX64mi = 1218, + X86_RORX64ri = 1219, + X86_RSM = 1220, + X86_RSTORSSP = 1221, + X86_SAHF = 1222, + X86_SAL16m1 = 1223, + X86_SAL16mCL = 1224, + X86_SAL16mi = 1225, + X86_SAL16r1 = 1226, + X86_SAL16rCL = 1227, + X86_SAL16ri = 1228, + X86_SAL32m1 = 1229, + X86_SAL32mCL = 1230, + X86_SAL32mi = 1231, + X86_SAL32r1 = 1232, + X86_SAL32rCL = 1233, + X86_SAL32ri = 1234, + X86_SAL64m1 = 1235, + X86_SAL64mCL = 1236, + X86_SAL64mi = 1237, + X86_SAL64r1 = 1238, + X86_SAL64rCL = 1239, + X86_SAL64ri = 1240, + X86_SAL8m1 = 1241, + X86_SAL8mCL = 1242, + X86_SAL8mi = 1243, + X86_SAL8r1 = 1244, + X86_SAL8rCL = 1245, + X86_SAL8ri = 1246, + X86_SALC = 1247, + X86_SAR16m1 = 1248, + X86_SAR16mCL = 1249, + X86_SAR16mi = 1250, + X86_SAR16r1 = 1251, + X86_SAR16rCL = 1252, + X86_SAR16ri = 1253, + X86_SAR32m1 = 1254, + X86_SAR32mCL = 1255, + X86_SAR32mi = 1256, + X86_SAR32r1 = 1257, + X86_SAR32rCL = 1258, + X86_SAR32ri = 1259, + X86_SAR64m1 = 1260, + X86_SAR64mCL = 1261, + X86_SAR64mi = 1262, + X86_SAR64r1 = 1263, + X86_SAR64rCL = 1264, + X86_SAR64ri = 1265, + X86_SAR8m1 = 1266, + X86_SAR8mCL = 1267, + X86_SAR8mi = 1268, + X86_SAR8r1 = 1269, + X86_SAR8rCL = 1270, + X86_SAR8ri = 1271, + X86_SARX32rm = 1272, + X86_SARX32rr = 1273, + X86_SARX64rm = 1274, + X86_SARX64rr = 1275, + X86_SAVEPREVSSP = 1276, + X86_SBB16i16 = 1277, + X86_SBB16mi = 1278, + X86_SBB16mi8 = 1279, + X86_SBB16mr = 1280, + X86_SBB16ri = 1281, + X86_SBB16ri8 = 1282, + X86_SBB16rm = 1283, + X86_SBB16rr = 1284, + X86_SBB16rr_REV = 1285, + X86_SBB32i32 = 1286, + X86_SBB32mi = 1287, + X86_SBB32mi8 = 1288, + X86_SBB32mr = 1289, + X86_SBB32ri = 1290, + X86_SBB32ri8 = 1291, + X86_SBB32rm = 1292, + X86_SBB32rr = 1293, + X86_SBB32rr_REV = 1294, + X86_SBB64i32 = 1295, + X86_SBB64mi32 = 1296, + X86_SBB64mi8 = 1297, + X86_SBB64mr = 1298, + X86_SBB64ri32 = 1299, + X86_SBB64ri8 = 1300, + X86_SBB64rm = 1301, + X86_SBB64rr = 1302, + X86_SBB64rr_REV = 1303, + X86_SBB8i8 = 1304, + X86_SBB8mi = 1305, + X86_SBB8mi8 = 1306, + X86_SBB8mr = 1307, + X86_SBB8ri = 1308, + X86_SBB8ri8 = 1309, + X86_SBB8rm = 1310, + X86_SBB8rr = 1311, + X86_SBB8rr_REV = 1312, + X86_SCASB = 1313, + X86_SCASL = 1314, + X86_SCASQ = 1315, + X86_SCASW = 1316, + X86_SETAEm = 1317, + X86_SETAEr = 1318, + X86_SETAm = 1319, + X86_SETAr = 1320, + X86_SETBEm = 1321, + X86_SETBEr = 1322, + X86_SETBm = 1323, + X86_SETBr = 1324, + X86_SETEm = 1325, + X86_SETEr = 1326, + X86_SETGEm = 1327, + X86_SETGEr = 1328, + X86_SETGm = 1329, + X86_SETGr = 1330, + X86_SETLEm = 1331, + X86_SETLEr = 1332, + X86_SETLm = 1333, + X86_SETLr = 1334, + X86_SETNEm = 1335, + X86_SETNEr = 1336, + X86_SETNOm = 1337, + X86_SETNOr = 1338, + X86_SETNPm = 1339, + X86_SETNPr = 1340, + X86_SETNSm = 1341, + X86_SETNSr = 1342, + X86_SETOm = 1343, + X86_SETOr = 1344, + X86_SETPm = 1345, + X86_SETPr = 1346, + X86_SETSSBSY = 1347, + X86_SETSm = 1348, + X86_SETSr = 1349, + X86_SGDT16m = 1350, + X86_SGDT32m = 1351, + X86_SGDT64m = 1352, + X86_SHL16m1 = 1353, + X86_SHL16mCL = 1354, + X86_SHL16mi = 1355, + X86_SHL16r1 = 1356, + X86_SHL16rCL = 1357, + X86_SHL16ri = 1358, + X86_SHL32m1 = 1359, + X86_SHL32mCL = 1360, + X86_SHL32mi = 1361, + X86_SHL32r1 = 1362, + X86_SHL32rCL = 1363, + X86_SHL32ri = 1364, + X86_SHL64m1 = 1365, + X86_SHL64mCL = 1366, + X86_SHL64mi = 1367, + X86_SHL64r1 = 1368, + X86_SHL64rCL = 1369, + X86_SHL64ri = 1370, + X86_SHL8m1 = 1371, + X86_SHL8mCL = 1372, + X86_SHL8mi = 1373, + X86_SHL8r1 = 1374, + X86_SHL8rCL = 1375, + X86_SHL8ri = 1376, + X86_SHLD16mrCL = 1377, + X86_SHLD16mri8 = 1378, + X86_SHLD16rrCL = 1379, + X86_SHLD16rri8 = 1380, + X86_SHLD32mrCL = 1381, + X86_SHLD32mri8 = 1382, + X86_SHLD32rrCL = 1383, + X86_SHLD32rri8 = 1384, + X86_SHLD64mrCL = 1385, + X86_SHLD64mri8 = 1386, + X86_SHLD64rrCL = 1387, + X86_SHLD64rri8 = 1388, + X86_SHLX32rm = 1389, + X86_SHLX32rr = 1390, + X86_SHLX64rm = 1391, + X86_SHLX64rr = 1392, + X86_SHR16m1 = 1393, + X86_SHR16mCL = 1394, + X86_SHR16mi = 1395, + X86_SHR16r1 = 1396, + X86_SHR16rCL = 1397, + X86_SHR16ri = 1398, + X86_SHR32m1 = 1399, + X86_SHR32mCL = 1400, + X86_SHR32mi = 1401, + X86_SHR32r1 = 1402, + X86_SHR32rCL = 1403, + X86_SHR32ri = 1404, + X86_SHR64m1 = 1405, + X86_SHR64mCL = 1406, + X86_SHR64mi = 1407, + X86_SHR64r1 = 1408, + X86_SHR64rCL = 1409, + X86_SHR64ri = 1410, + X86_SHR8m1 = 1411, + X86_SHR8mCL = 1412, + X86_SHR8mi = 1413, + X86_SHR8r1 = 1414, + X86_SHR8rCL = 1415, + X86_SHR8ri = 1416, + X86_SHRD16mrCL = 1417, + X86_SHRD16mri8 = 1418, + X86_SHRD16rrCL = 1419, + X86_SHRD16rri8 = 1420, + X86_SHRD32mrCL = 1421, + X86_SHRD32mri8 = 1422, + X86_SHRD32rrCL = 1423, + X86_SHRD32rri8 = 1424, + X86_SHRD64mrCL = 1425, + X86_SHRD64mri8 = 1426, + X86_SHRD64rrCL = 1427, + X86_SHRD64rri8 = 1428, + X86_SHRX32rm = 1429, + X86_SHRX32rr = 1430, + X86_SHRX64rm = 1431, + X86_SHRX64rr = 1432, + X86_SIDT16m = 1433, + X86_SIDT32m = 1434, + X86_SIDT64m = 1435, + X86_SKINIT = 1436, + X86_SLDT16m = 1437, + X86_SLDT16r = 1438, + X86_SLDT32r = 1439, + X86_SLDT64r = 1440, + X86_SLWPCB = 1441, + X86_SLWPCB64 = 1442, + X86_SMSW16m = 1443, + X86_SMSW16r = 1444, + X86_SMSW32r = 1445, + X86_SMSW64r = 1446, + X86_STAC = 1447, + X86_STC = 1448, + X86_STD = 1449, + X86_STGI = 1450, + X86_STI = 1451, + X86_STOSB = 1452, + X86_STOSL = 1453, + X86_STOSQ = 1454, + X86_STOSW = 1455, + X86_STR16r = 1456, + X86_STR32r = 1457, + X86_STR64r = 1458, + X86_STRm = 1459, + X86_SUB16i16 = 1460, + X86_SUB16mi = 1461, + X86_SUB16mi8 = 1462, + X86_SUB16mr = 1463, + X86_SUB16ri = 1464, + X86_SUB16ri8 = 1465, + X86_SUB16rm = 1466, + X86_SUB16rr = 1467, + X86_SUB16rr_REV = 1468, + X86_SUB32i32 = 1469, + X86_SUB32mi = 1470, + X86_SUB32mi8 = 1471, + X86_SUB32mr = 1472, + X86_SUB32ri = 1473, + X86_SUB32ri8 = 1474, + X86_SUB32rm = 1475, + X86_SUB32rr = 1476, + X86_SUB32rr_REV = 1477, + X86_SUB64i32 = 1478, + X86_SUB64mi32 = 1479, + X86_SUB64mi8 = 1480, + X86_SUB64mr = 1481, + X86_SUB64ri32 = 1482, + X86_SUB64ri8 = 1483, + X86_SUB64rm = 1484, + X86_SUB64rr = 1485, + X86_SUB64rr_REV = 1486, + X86_SUB8i8 = 1487, + X86_SUB8mi = 1488, + X86_SUB8mi8 = 1489, + X86_SUB8mr = 1490, + X86_SUB8ri = 1491, + X86_SUB8ri8 = 1492, + X86_SUB8rm = 1493, + X86_SUB8rr = 1494, + X86_SUB8rr_REV = 1495, + X86_SWAPGS = 1496, + X86_SYSCALL = 1497, + X86_SYSENTER = 1498, + X86_SYSEXIT = 1499, + X86_SYSEXIT64 = 1500, + X86_SYSRET = 1501, + X86_SYSRET64 = 1502, + X86_T1MSKC32rm = 1503, + X86_T1MSKC32rr = 1504, + X86_T1MSKC64rm = 1505, + X86_T1MSKC64rr = 1506, + X86_TEST16i16 = 1507, + X86_TEST16mi = 1508, + X86_TEST16mi_alt = 1509, + X86_TEST16mr = 1510, + X86_TEST16ri = 1511, + X86_TEST16ri_alt = 1512, + X86_TEST16rr = 1513, + X86_TEST32i32 = 1514, + X86_TEST32mi = 1515, + X86_TEST32mi_alt = 1516, + X86_TEST32mr = 1517, + X86_TEST32ri = 1518, + X86_TEST32ri_alt = 1519, + X86_TEST32rr = 1520, + X86_TEST64i32 = 1521, + X86_TEST64mi32 = 1522, + X86_TEST64mi32_alt = 1523, + X86_TEST64mr = 1524, + X86_TEST64ri32 = 1525, + X86_TEST64ri32_alt = 1526, + X86_TEST64rr = 1527, + X86_TEST8i8 = 1528, + X86_TEST8mi = 1529, + X86_TEST8mi_alt = 1530, + X86_TEST8mr = 1531, + X86_TEST8ri = 1532, + X86_TEST8ri_alt = 1533, + X86_TEST8rr = 1534, + X86_TPAUSE = 1535, + X86_TZCNT16rm = 1536, + X86_TZCNT16rr = 1537, + X86_TZCNT32rm = 1538, + X86_TZCNT32rr = 1539, + X86_TZCNT64rm = 1540, + X86_TZCNT64rr = 1541, + X86_TZMSK32rm = 1542, + X86_TZMSK32rr = 1543, + X86_TZMSK64rm = 1544, + X86_TZMSK64rr = 1545, + X86_UD0 = 1546, + X86_UD1 = 1547, + X86_UD2 = 1548, + X86_UMONITOR16 = 1549, + X86_UMONITOR32 = 1550, + X86_UMONITOR64 = 1551, + X86_UMWAIT = 1552, + X86_VERRm = 1553, + X86_VERRr = 1554, + X86_VERWm = 1555, + X86_VERWr = 1556, + X86_VMCALL = 1557, + X86_VMCLEARm = 1558, + X86_VMFUNC = 1559, + X86_VMLAUNCH = 1560, + X86_VMLOAD32 = 1561, + X86_VMLOAD64 = 1562, + X86_VMMCALL = 1563, + X86_VMPTRLDm = 1564, + X86_VMPTRSTm = 1565, + X86_VMREAD32mr = 1566, + X86_VMREAD32rr = 1567, + X86_VMREAD64mr = 1568, + X86_VMREAD64rr = 1569, + X86_VMRESUME = 1570, + X86_VMRUN32 = 1571, + X86_VMRUN64 = 1572, + X86_VMSAVE32 = 1573, + X86_VMSAVE64 = 1574, + X86_VMWRITE32rm = 1575, + X86_VMWRITE32rr = 1576, + X86_VMWRITE64rm = 1577, + X86_VMWRITE64rr = 1578, + X86_VMXOFF = 1579, + X86_VMXON = 1580, + X86_WBINVD = 1581, + X86_WBNOINVD = 1582, + X86_WRFSBASE = 1583, + X86_WRFSBASE64 = 1584, + X86_WRGSBASE = 1585, + X86_WRGSBASE64 = 1586, + X86_WRMSR = 1587, + X86_WRPKRUr = 1588, + X86_WRSSD = 1589, + X86_WRSSQ = 1590, + X86_WRUSSD = 1591, + X86_WRUSSQ = 1592, + X86_XADD16rm = 1593, + X86_XADD16rr = 1594, + X86_XADD32rm = 1595, + X86_XADD32rr = 1596, + X86_XADD64rm = 1597, + X86_XADD64rr = 1598, + X86_XADD8rm = 1599, + X86_XADD8rr = 1600, + X86_XCHG16ar = 1601, + X86_XCHG16rm = 1602, + X86_XCHG16rr = 1603, + X86_XCHG32ar = 1604, + X86_XCHG32rm = 1605, + X86_XCHG32rr = 1606, + X86_XCHG64ar = 1607, + X86_XCHG64rm = 1608, + X86_XCHG64rr = 1609, + X86_XCHG8rm = 1610, + X86_XCHG8rr = 1611, + X86_XCRYPTCBC = 1612, + X86_XCRYPTCFB = 1613, + X86_XCRYPTCTR = 1614, + X86_XCRYPTECB = 1615, + X86_XCRYPTOFB = 1616, + X86_XGETBV = 1617, + X86_XLAT = 1618, + X86_XOR16i16 = 1619, + X86_XOR16mi = 1620, + X86_XOR16mi8 = 1621, + X86_XOR16mr = 1622, + X86_XOR16ri = 1623, + X86_XOR16ri8 = 1624, + X86_XOR16rm = 1625, + X86_XOR16rr = 1626, + X86_XOR16rr_REV = 1627, + X86_XOR32i32 = 1628, + X86_XOR32mi = 1629, + X86_XOR32mi8 = 1630, + X86_XOR32mr = 1631, + X86_XOR32ri = 1632, + X86_XOR32ri8 = 1633, + X86_XOR32rm = 1634, + X86_XOR32rr = 1635, + X86_XOR32rr_REV = 1636, + X86_XOR64i32 = 1637, + X86_XOR64mi32 = 1638, + X86_XOR64mi8 = 1639, + X86_XOR64mr = 1640, + X86_XOR64ri32 = 1641, + X86_XOR64ri8 = 1642, + X86_XOR64rm = 1643, + X86_XOR64rr = 1644, + X86_XOR64rr_REV = 1645, + X86_XOR8i8 = 1646, + X86_XOR8mi = 1647, + X86_XOR8mi8 = 1648, + X86_XOR8mr = 1649, + X86_XOR8ri = 1650, + X86_XOR8ri8 = 1651, + X86_XOR8rm = 1652, + X86_XOR8rr = 1653, + X86_XOR8rr_REV = 1654, + X86_XRSTOR = 1655, + X86_XRSTOR64 = 1656, + X86_XRSTORS = 1657, + X86_XRSTORS64 = 1658, + X86_XSAVE = 1659, + X86_XSAVE64 = 1660, + X86_XSAVEC = 1661, + X86_XSAVEC64 = 1662, + X86_XSAVEOPT = 1663, + X86_XSAVEOPT64 = 1664, + X86_XSAVES = 1665, + X86_XSAVES64 = 1666, + X86_XSETBV = 1667, + X86_XSHA1 = 1668, + X86_XSHA256 = 1669, + X86_XSTORE = 1670, + X86_INSTRUCTION_LIST_END = 1671 +}; + +#endif // GET_INSTRINFO_ENUM diff --git a/thirdparty/capstone/arch/X86/X86GenRegisterInfo.inc b/thirdparty/capstone/arch/X86/X86GenRegisterInfo.inc new file mode 100644 index 0000000..888da8e --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenRegisterInfo.inc @@ -0,0 +1,1549 @@ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +|* Target Register Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +enum { + X86_NoRegister, + X86_AH = 1, + X86_AL = 2, + X86_AX = 3, + X86_BH = 4, + X86_BL = 5, + X86_BP = 6, + X86_BPH = 7, + X86_BPL = 8, + X86_BX = 9, + X86_CH = 10, + X86_CL = 11, + X86_CS = 12, + X86_CX = 13, + X86_DF = 14, + X86_DH = 15, + X86_DI = 16, + X86_DIH = 17, + X86_DIL = 18, + X86_DL = 19, + X86_DS = 20, + X86_DX = 21, + X86_EAX = 22, + X86_EBP = 23, + X86_EBX = 24, + X86_ECX = 25, + X86_EDI = 26, + X86_EDX = 27, + X86_EFLAGS = 28, + X86_EIP = 29, + X86_EIZ = 30, + X86_ES = 31, + X86_ESI = 32, + X86_ESP = 33, + X86_FPSW = 34, + X86_FS = 35, + X86_GS = 36, + X86_HAX = 37, + X86_HBP = 38, + X86_HBX = 39, + X86_HCX = 40, + X86_HDI = 41, + X86_HDX = 42, + X86_HIP = 43, + X86_HSI = 44, + X86_HSP = 45, + X86_IP = 46, + X86_RAX = 47, + X86_RBP = 48, + X86_RBX = 49, + X86_RCX = 50, + X86_RDI = 51, + X86_RDX = 52, + X86_RIP = 53, + X86_RIZ = 54, + X86_RSI = 55, + X86_RSP = 56, + X86_SI = 57, + X86_SIH = 58, + X86_SIL = 59, + X86_SP = 60, + X86_SPH = 61, + X86_SPL = 62, + X86_SS = 63, + X86_SSP = 64, + X86_BND0 = 65, + X86_BND1 = 66, + X86_BND2 = 67, + X86_BND3 = 68, + X86_CR0 = 69, + X86_CR1 = 70, + X86_CR2 = 71, + X86_CR3 = 72, + X86_CR4 = 73, + X86_CR5 = 74, + X86_CR6 = 75, + X86_CR7 = 76, + X86_CR8 = 77, + X86_CR9 = 78, + X86_CR10 = 79, + X86_CR11 = 80, + X86_CR12 = 81, + X86_CR13 = 82, + X86_CR14 = 83, + X86_CR15 = 84, + X86_DR0 = 85, + X86_DR1 = 86, + X86_DR2 = 87, + X86_DR3 = 88, + X86_DR4 = 89, + X86_DR5 = 90, + X86_DR6 = 91, + X86_DR7 = 92, + X86_DR8 = 93, + X86_DR9 = 94, + X86_DR10 = 95, + X86_DR11 = 96, + X86_DR12 = 97, + X86_DR13 = 98, + X86_DR14 = 99, + X86_DR15 = 100, + X86_FP0 = 101, + X86_FP1 = 102, + X86_FP2 = 103, + X86_FP3 = 104, + X86_FP4 = 105, + X86_FP5 = 106, + X86_FP6 = 107, + X86_FP7 = 108, + X86_K0 = 109, + X86_K1 = 110, + X86_K2 = 111, + X86_K3 = 112, + X86_K4 = 113, + X86_K5 = 114, + X86_K6 = 115, + X86_K7 = 116, + X86_MM0 = 117, + X86_MM1 = 118, + X86_MM2 = 119, + X86_MM3 = 120, + X86_MM4 = 121, + X86_MM5 = 122, + X86_MM6 = 123, + X86_MM7 = 124, + X86_R8 = 125, + X86_R9 = 126, + X86_R10 = 127, + X86_R11 = 128, + X86_R12 = 129, + X86_R13 = 130, + X86_R14 = 131, + X86_R15 = 132, + X86_ST0 = 133, + X86_ST1 = 134, + X86_ST2 = 135, + X86_ST3 = 136, + X86_ST4 = 137, + X86_ST5 = 138, + X86_ST6 = 139, + X86_ST7 = 140, + X86_XMM0 = 141, + X86_XMM1 = 142, + X86_XMM2 = 143, + X86_XMM3 = 144, + X86_XMM4 = 145, + X86_XMM5 = 146, + X86_XMM6 = 147, + X86_XMM7 = 148, + X86_XMM8 = 149, + X86_XMM9 = 150, + X86_XMM10 = 151, + X86_XMM11 = 152, + X86_XMM12 = 153, + X86_XMM13 = 154, + X86_XMM14 = 155, + X86_XMM15 = 156, + X86_XMM16 = 157, + X86_XMM17 = 158, + X86_XMM18 = 159, + X86_XMM19 = 160, + X86_XMM20 = 161, + X86_XMM21 = 162, + X86_XMM22 = 163, + X86_XMM23 = 164, + X86_XMM24 = 165, + X86_XMM25 = 166, + X86_XMM26 = 167, + X86_XMM27 = 168, + X86_XMM28 = 169, + X86_XMM29 = 170, + X86_XMM30 = 171, + X86_XMM31 = 172, + X86_YMM0 = 173, + X86_YMM1 = 174, + X86_YMM2 = 175, + X86_YMM3 = 176, + X86_YMM4 = 177, + X86_YMM5 = 178, + X86_YMM6 = 179, + X86_YMM7 = 180, + X86_YMM8 = 181, + X86_YMM9 = 182, + X86_YMM10 = 183, + X86_YMM11 = 184, + X86_YMM12 = 185, + X86_YMM13 = 186, + X86_YMM14 = 187, + X86_YMM15 = 188, + X86_YMM16 = 189, + X86_YMM17 = 190, + X86_YMM18 = 191, + X86_YMM19 = 192, + X86_YMM20 = 193, + X86_YMM21 = 194, + X86_YMM22 = 195, + X86_YMM23 = 196, + X86_YMM24 = 197, + X86_YMM25 = 198, + X86_YMM26 = 199, + X86_YMM27 = 200, + X86_YMM28 = 201, + X86_YMM29 = 202, + X86_YMM30 = 203, + X86_YMM31 = 204, + X86_ZMM0 = 205, + X86_ZMM1 = 206, + X86_ZMM2 = 207, + X86_ZMM3 = 208, + X86_ZMM4 = 209, + X86_ZMM5 = 210, + X86_ZMM6 = 211, + X86_ZMM7 = 212, + X86_ZMM8 = 213, + X86_ZMM9 = 214, + X86_ZMM10 = 215, + X86_ZMM11 = 216, + X86_ZMM12 = 217, + X86_ZMM13 = 218, + X86_ZMM14 = 219, + X86_ZMM15 = 220, + X86_ZMM16 = 221, + X86_ZMM17 = 222, + X86_ZMM18 = 223, + X86_ZMM19 = 224, + X86_ZMM20 = 225, + X86_ZMM21 = 226, + X86_ZMM22 = 227, + X86_ZMM23 = 228, + X86_ZMM24 = 229, + X86_ZMM25 = 230, + X86_ZMM26 = 231, + X86_ZMM27 = 232, + X86_ZMM28 = 233, + X86_ZMM29 = 234, + X86_ZMM30 = 235, + X86_ZMM31 = 236, + X86_R8B = 237, + X86_R9B = 238, + X86_R10B = 239, + X86_R11B = 240, + X86_R12B = 241, + X86_R13B = 242, + X86_R14B = 243, + X86_R15B = 244, + X86_R8BH = 245, + X86_R9BH = 246, + X86_R10BH = 247, + X86_R11BH = 248, + X86_R12BH = 249, + X86_R13BH = 250, + X86_R14BH = 251, + X86_R15BH = 252, + X86_R8D = 253, + X86_R9D = 254, + X86_R10D = 255, + X86_R11D = 256, + X86_R12D = 257, + X86_R13D = 258, + X86_R14D = 259, + X86_R15D = 260, + X86_R8W = 261, + X86_R9W = 262, + X86_R10W = 263, + X86_R11W = 264, + X86_R12W = 265, + X86_R13W = 266, + X86_R14W = 267, + X86_R15W = 268, + X86_R8WH = 269, + X86_R9WH = 270, + X86_R10WH = 271, + X86_R11WH = 272, + X86_R12WH = 273, + X86_R13WH = 274, + X86_R14WH = 275, + X86_R15WH = 276, + X86_NUM_TARGET_REGS // 277 +}; + +// Register classes +enum { + X86_GR8RegClassID = 0, + X86_GRH8RegClassID = 1, + X86_GR8_NOREXRegClassID = 2, + X86_GR8_ABCD_HRegClassID = 3, + X86_GR8_ABCD_LRegClassID = 4, + X86_GRH16RegClassID = 5, + X86_GR16RegClassID = 6, + X86_GR16_NOREXRegClassID = 7, + X86_VK1RegClassID = 8, + X86_VK16RegClassID = 9, + X86_VK2RegClassID = 10, + X86_VK4RegClassID = 11, + X86_VK8RegClassID = 12, + X86_VK16WMRegClassID = 13, + X86_VK1WMRegClassID = 14, + X86_VK2WMRegClassID = 15, + X86_VK4WMRegClassID = 16, + X86_VK8WMRegClassID = 17, + X86_SEGMENT_REGRegClassID = 18, + X86_GR16_ABCDRegClassID = 19, + X86_FPCCRRegClassID = 20, + X86_FR32XRegClassID = 21, + X86_LOW32_ADDR_ACCESS_RBPRegClassID = 22, + X86_LOW32_ADDR_ACCESSRegClassID = 23, + X86_LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 24, + X86_DEBUG_REGRegClassID = 25, + X86_FR32RegClassID = 26, + X86_GR32RegClassID = 27, + X86_GR32_NOSPRegClassID = 28, + X86_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 29, + X86_GR32_NOREXRegClassID = 30, + X86_VK32RegClassID = 31, + X86_GR32_NOREX_NOSPRegClassID = 32, + X86_RFP32RegClassID = 33, + X86_VK32WMRegClassID = 34, + X86_GR32_ABCDRegClassID = 35, + X86_GR32_TCRegClassID = 36, + X86_GR32_ADRegClassID = 37, + X86_LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 38, + X86_CCRRegClassID = 39, + X86_DFCCRRegClassID = 40, + X86_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 41, + X86_LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 42, + X86_RFP64RegClassID = 43, + X86_FR64XRegClassID = 44, + X86_GR64RegClassID = 45, + X86_CONTROL_REGRegClassID = 46, + X86_FR64RegClassID = 47, + X86_GR64_with_sub_8bitRegClassID = 48, + X86_GR64_NOSPRegClassID = 49, + X86_GR64_NOREXRegClassID = 50, + X86_GR64_TCRegClassID = 51, + X86_GR64_NOSP_and_GR64_TCRegClassID = 52, + X86_GR64_TCW64RegClassID = 53, + X86_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 54, + X86_VK64RegClassID = 55, + X86_VR64RegClassID = 56, + X86_GR64_NOREX_NOSPRegClassID = 57, + X86_GR64_NOSP_and_GR64_TCW64RegClassID = 58, + X86_GR64_TC_and_GR64_TCW64RegClassID = 59, + X86_VK64WMRegClassID = 60, + X86_GR64_NOREX_and_GR64_TCRegClassID = 61, + X86_GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID = 62, + X86_GR64_NOREX_NOSP_and_GR64_TCRegClassID = 63, + X86_GR64_ABCDRegClassID = 64, + X86_GR64_NOREX_and_GR64_TCW64RegClassID = 65, + X86_GR64_with_sub_32bit_in_GR32_TCRegClassID = 66, + X86_GR64_ADRegClassID = 67, + X86_GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 68, + X86_GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPRegClassID = 69, + X86_GR64_and_LOW32_ADDR_ACCESSRegClassID = 70, + X86_RSTRegClassID = 71, + X86_RFP80RegClassID = 72, + X86_VR128XRegClassID = 73, + X86_VR128RegClassID = 74, + X86_VR128HRegClassID = 75, + X86_VR128LRegClassID = 76, + X86_BNDRRegClassID = 77, + X86_VR256XRegClassID = 78, + X86_VR256RegClassID = 79, + X86_VR256HRegClassID = 80, + X86_VR256LRegClassID = 81, + X86_VR512RegClassID = 82, + X86_VR512_with_sub_xmm_in_FR32RegClassID = 83, + X86_VR512_with_sub_xmm_in_VR128HRegClassID = 84, + X86_VR512_with_sub_xmm_in_VR128LRegClassID = 85, +}; +#endif // GET_REGINFO_ENUM + +#ifdef GET_REGINFO_MC_DESC +#define GET_REGINFO_MC_DESC + + +static const MCPhysReg X86RegDiffLists[] = { + /* 0 */ 0, 1, 0, + /* 3 */ -661, 1, 1, 0, + /* 7 */ -277, 1, 1, 0, + /* 11 */ -139, 1, 1, 0, + /* 15 */ -70, 1, 1, 0, + /* 19 */ 2, 1, 0, + /* 22 */ 4, 1, 0, + /* 25 */ 6, 1, 0, + /* 28 */ 11, 1, 0, + /* 31 */ 22, 1, 0, + /* 34 */ 26, 1, 0, + /* 37 */ 29, 1, 0, + /* 40 */ -685, 1, 0, + /* 43 */ 10, 3, 0, + /* 46 */ 4, 0, + /* 48 */ 5, 0, + /* 50 */ -244, 1, 7, 0, + /* 54 */ -119, 1, 7, 0, + /* 58 */ 10, 3, 7, 0, + /* 62 */ -24, 8, 0, + /* 65 */ -194, 1, 11, 0, + /* 69 */ -188, 1, 11, 0, + /* 73 */ -94, 1, 11, 0, + /* 77 */ -88, 1, 11, 0, + /* 81 */ 12, 0, + /* 83 */ -194, 1, 14, 0, + /* 87 */ -188, 1, 14, 0, + /* 91 */ -94, 1, 14, 0, + /* 95 */ -88, 1, 14, 0, + /* 99 */ 21, 0, + /* 101 */ 22, 0, + /* 103 */ -2, -27, 23, 0, + /* 107 */ -1, -27, 23, 0, + /* 111 */ -2, -25, 23, 0, + /* 115 */ -1, -25, 23, 0, + /* 119 */ -12, 23, 0, + /* 122 */ 128, 8, -24, 8, 24, 0, + /* 128 */ -17, 24, 0, + /* 131 */ -14, 24, 0, + /* 134 */ -25, -10, 2, -1, 24, 0, + /* 140 */ 2, 6, 25, 0, + /* 144 */ 6, 6, 25, 0, + /* 148 */ -2, 10, 25, 0, + /* 152 */ -1, 10, 25, 0, + /* 156 */ 2, 12, 25, 0, + /* 160 */ 3, 12, 25, 0, + /* 164 */ 4, 15, 25, 0, + /* 168 */ 5, 15, 25, 0, + /* 172 */ -2, 17, 25, 0, + /* 176 */ -1, 17, 25, 0, + /* 180 */ 1, 19, 25, 0, + /* 184 */ 2, 19, 25, 0, + /* 188 */ -15, 25, 0, + /* 191 */ 26, 0, + /* 193 */ -25, -6, -2, -4, 27, 0, + /* 199 */ -25, -12, -2, -1, 30, 0, + /* 205 */ -25, -17, 2, -1, 31, 0, + /* 211 */ 32, 32, 0, + /* 214 */ -25, -15, -4, -1, 35, 0, + /* 220 */ -25, -19, -1, -1, 36, 0, + /* 226 */ -707, 0, + /* 228 */ -636, 0, + /* 230 */ -613, 0, + /* 232 */ -405, 0, + /* 234 */ -16, -128, 0, + /* 237 */ 16, -8, -128, 0, + /* 241 */ 24, -8, -128, 0, + /* 245 */ -106, 0, + /* 247 */ -104, 0, + /* 249 */ -75, 0, + /* 251 */ -43, 0, + /* 253 */ -32, -32, 0, + /* 256 */ -27, 0, + /* 258 */ -25, 0, + /* 260 */ -22, 0, + /* 262 */ -23, 27, 2, -1, -16, 0, + /* 268 */ -23, 25, 2, -1, -14, 0, + /* 274 */ -11, 0, + /* 276 */ -6, 0, + /* 278 */ -5, 0, + /* 280 */ -2, -4, 0, + /* 283 */ -24, 17, -3, 0, + /* 287 */ -2, 0, + /* 289 */ 2, -1, 0, + /* 292 */ -4, -1, 0, + /* 295 */ -2, -1, 0, + /* 298 */ -1, -1, 0, +}; + +static const uint16_t X86SubRegIdxLists[] = { + /* 0 */ 1, 2, 0, + /* 3 */ 1, 3, 0, + /* 6 */ 6, 4, 1, 2, 5, 0, + /* 12 */ 6, 4, 1, 3, 5, 0, + /* 18 */ 6, 4, 5, 0, + /* 22 */ 8, 7, 0, +}; + +static const MCRegisterDesc X86RegDesc[] = { + { 5, 0, 0, 0, 0, 0 }, + { 873, 2, 184, 2, 4641, 0 }, + { 1014, 2, 180, 2, 4641, 0 }, + { 1148, 298, 181, 0, 0, 2 }, + { 879, 2, 168, 2, 4593, 0 }, + { 1017, 2, 164, 2, 4593, 0 }, + { 1043, 289, 173, 3, 352, 5 }, + { 936, 2, 176, 2, 768, 0 }, + { 1034, 2, 172, 2, 736, 0 }, + { 1160, 292, 165, 0, 304, 2 }, + { 922, 2, 160, 2, 4497, 0 }, + { 1020, 2, 156, 2, 4497, 0 }, + { 1082, 2, 2, 2, 4497, 0 }, + { 1172, 295, 157, 0, 400, 2 }, + { 870, 2, 2, 2, 4449, 0 }, + { 925, 2, 144, 2, 4449, 0 }, + { 991, 289, 149, 3, 448, 5 }, + { 928, 2, 152, 2, 1296, 0 }, + { 1026, 2, 148, 2, 4130, 0 }, + { 1023, 2, 140, 2, 4417, 0 }, + { 1085, 2, 2, 2, 4417, 0 }, + { 1184, 280, 141, 0, 688, 2 }, + { 1147, 221, 142, 7, 1524, 8 }, + { 1042, 206, 142, 13, 1236, 12 }, + { 1159, 215, 142, 7, 1460, 8 }, + { 1171, 200, 142, 7, 1172, 8 }, + { 990, 135, 142, 13, 869, 12 }, + { 1183, 194, 142, 7, 928, 8 }, + { 1094, 2, 2, 2, 1584, 0 }, + { 1054, 284, 126, 19, 496, 16 }, + { 1195, 2, 2, 2, 4417, 0 }, + { 1088, 2, 2, 2, 4417, 0 }, + { 1002, 269, 105, 13, 243, 12 }, + { 1066, 263, 105, 13, 243, 12 }, + { 1142, 2, 2, 2, 4593, 0 }, + { 1091, 2, 2, 2, 4593, 0 }, + { 1098, 2, 2, 2, 4593, 0 }, + { 1151, 2, 188, 2, 4161, 0 }, + { 1046, 2, 188, 2, 4161, 0 }, + { 1163, 2, 188, 2, 4161, 0 }, + { 1175, 2, 188, 2, 4161, 0 }, + { 994, 2, 188, 2, 4161, 0 }, + { 1187, 2, 188, 2, 4161, 0 }, + { 1058, 2, 131, 2, 3923, 0 }, + { 1006, 2, 119, 2, 3955, 0 }, + { 1070, 2, 119, 2, 3955, 0 }, + { 1055, 2, 128, 2, 1616, 0 }, + { 1155, 220, 2, 6, 1396, 8 }, + { 1050, 205, 2, 12, 1108, 12 }, + { 1167, 214, 2, 6, 1332, 8 }, + { 1179, 199, 2, 6, 1044, 8 }, + { 998, 134, 2, 12, 805, 12 }, + { 1191, 193, 2, 6, 928, 8 }, + { 1062, 283, 2, 18, 496, 16 }, + { 1199, 2, 2, 2, 3488, 0 }, + { 1010, 268, 2, 12, 179, 12 }, + { 1074, 262, 2, 12, 179, 12 }, + { 1003, 289, 112, 3, 544, 5 }, + { 932, 2, 115, 2, 3152, 0 }, + { 1030, 2, 111, 2, 3056, 0 }, + { 1067, 289, 104, 3, 592, 5 }, + { 940, 2, 107, 2, 3248, 0 }, + { 1038, 2, 103, 2, 3719, 0 }, + { 1101, 2, 2, 2, 4097, 0 }, + { 1078, 2, 2, 2, 4097, 0 }, + { 64, 2, 2, 2, 4097, 0 }, + { 167, 2, 2, 2, 4097, 0 }, + { 252, 2, 2, 2, 4097, 0 }, + { 337, 2, 2, 2, 4097, 0 }, + { 91, 2, 2, 2, 4097, 0 }, + { 194, 2, 2, 2, 4097, 0 }, + { 279, 2, 2, 2, 4097, 0 }, + { 364, 2, 2, 2, 4097, 0 }, + { 444, 2, 2, 2, 4097, 0 }, + { 524, 2, 2, 2, 4097, 0 }, + { 594, 2, 2, 2, 4097, 0 }, + { 664, 2, 2, 2, 4097, 0 }, + { 727, 2, 2, 2, 4097, 0 }, + { 786, 2, 2, 2, 4097, 0 }, + { 18, 2, 2, 2, 4097, 0 }, + { 121, 2, 2, 2, 4097, 0 }, + { 224, 2, 2, 2, 4097, 0 }, + { 309, 2, 2, 2, 4097, 0 }, + { 394, 2, 2, 2, 4097, 0 }, + { 474, 2, 2, 2, 4097, 0 }, + { 95, 2, 2, 2, 4097, 0 }, + { 198, 2, 2, 2, 4097, 0 }, + { 283, 2, 2, 2, 4097, 0 }, + { 368, 2, 2, 2, 4097, 0 }, + { 448, 2, 2, 2, 4097, 0 }, + { 528, 2, 2, 2, 4097, 0 }, + { 598, 2, 2, 2, 4097, 0 }, + { 668, 2, 2, 2, 4097, 0 }, + { 731, 2, 2, 2, 4097, 0 }, + { 790, 2, 2, 2, 4097, 0 }, + { 23, 2, 2, 2, 4097, 0 }, + { 126, 2, 2, 2, 4097, 0 }, + { 229, 2, 2, 2, 4097, 0 }, + { 314, 2, 2, 2, 4097, 0 }, + { 399, 2, 2, 2, 4097, 0 }, + { 479, 2, 2, 2, 4097, 0 }, + { 87, 2, 2, 2, 4097, 0 }, + { 190, 2, 2, 2, 4097, 0 }, + { 275, 2, 2, 2, 4097, 0 }, + { 360, 2, 2, 2, 4097, 0 }, + { 440, 2, 2, 2, 4097, 0 }, + { 520, 2, 2, 2, 4097, 0 }, + { 590, 2, 2, 2, 4097, 0 }, + { 660, 2, 2, 2, 4097, 0 }, + { 69, 2, 2, 2, 4097, 0 }, + { 172, 2, 2, 2, 4097, 0 }, + { 257, 2, 2, 2, 4097, 0 }, + { 342, 2, 2, 2, 4097, 0 }, + { 422, 2, 2, 2, 4097, 0 }, + { 502, 2, 2, 2, 4097, 0 }, + { 572, 2, 2, 2, 4097, 0 }, + { 642, 2, 2, 2, 4097, 0 }, + { 73, 2, 2, 2, 4097, 0 }, + { 176, 2, 2, 2, 4097, 0 }, + { 261, 2, 2, 2, 4097, 0 }, + { 346, 2, 2, 2, 4097, 0 }, + { 426, 2, 2, 2, 4097, 0 }, + { 506, 2, 2, 2, 4097, 0 }, + { 576, 2, 2, 2, 4097, 0 }, + { 646, 2, 2, 2, 4097, 0 }, + { 728, 122, 2, 12, 115, 12 }, + { 787, 122, 2, 12, 115, 12 }, + { 19, 122, 2, 12, 115, 12 }, + { 122, 122, 2, 12, 115, 12 }, + { 225, 122, 2, 12, 115, 12 }, + { 310, 122, 2, 12, 115, 12 }, + { 395, 122, 2, 12, 115, 12 }, + { 475, 122, 2, 12, 115, 12 }, + { 99, 2, 2, 2, 4385, 0 }, + { 202, 2, 2, 2, 4385, 0 }, + { 287, 2, 2, 2, 4385, 0 }, + { 372, 2, 2, 2, 4385, 0 }, + { 452, 2, 2, 2, 4385, 0 }, + { 532, 2, 2, 2, 4385, 0 }, + { 602, 2, 2, 2, 4385, 0 }, + { 672, 2, 2, 2, 4385, 0 }, + { 72, 2, 211, 2, 4385, 0 }, + { 175, 2, 211, 2, 4385, 0 }, + { 260, 2, 211, 2, 4385, 0 }, + { 345, 2, 211, 2, 4385, 0 }, + { 425, 2, 211, 2, 4385, 0 }, + { 505, 2, 211, 2, 4385, 0 }, + { 575, 2, 211, 2, 4385, 0 }, + { 645, 2, 211, 2, 4385, 0 }, + { 712, 2, 211, 2, 4385, 0 }, + { 771, 2, 211, 2, 4385, 0 }, + { 0, 2, 211, 2, 4385, 0 }, + { 103, 2, 211, 2, 4385, 0 }, + { 206, 2, 211, 2, 4385, 0 }, + { 291, 2, 211, 2, 4385, 0 }, + { 376, 2, 211, 2, 4385, 0 }, + { 456, 2, 211, 2, 4385, 0 }, + { 536, 2, 211, 2, 4385, 0 }, + { 606, 2, 211, 2, 4385, 0 }, + { 676, 2, 211, 2, 4385, 0 }, + { 735, 2, 211, 2, 4385, 0 }, + { 28, 2, 211, 2, 4385, 0 }, + { 131, 2, 211, 2, 4385, 0 }, + { 234, 2, 211, 2, 4385, 0 }, + { 319, 2, 211, 2, 4385, 0 }, + { 404, 2, 211, 2, 4385, 0 }, + { 484, 2, 211, 2, 4385, 0 }, + { 554, 2, 211, 2, 4385, 0 }, + { 624, 2, 211, 2, 4385, 0 }, + { 694, 2, 211, 2, 4385, 0 }, + { 753, 2, 211, 2, 4385, 0 }, + { 46, 2, 211, 2, 4385, 0 }, + { 149, 2, 211, 2, 4385, 0 }, + { 77, 254, 212, 23, 4017, 19 }, + { 180, 254, 212, 23, 4017, 19 }, + { 265, 254, 212, 23, 4017, 19 }, + { 350, 254, 212, 23, 4017, 19 }, + { 430, 254, 212, 23, 4017, 19 }, + { 510, 254, 212, 23, 4017, 19 }, + { 580, 254, 212, 23, 4017, 19 }, + { 650, 254, 212, 23, 4017, 19 }, + { 717, 254, 212, 23, 4017, 19 }, + { 776, 254, 212, 23, 4017, 19 }, + { 6, 254, 212, 23, 4017, 19 }, + { 109, 254, 212, 23, 4017, 19 }, + { 212, 254, 212, 23, 4017, 19 }, + { 297, 254, 212, 23, 4017, 19 }, + { 382, 254, 212, 23, 4017, 19 }, + { 462, 254, 212, 23, 4017, 19 }, + { 542, 254, 212, 23, 4017, 19 }, + { 612, 254, 212, 23, 4017, 19 }, + { 682, 254, 212, 23, 4017, 19 }, + { 741, 254, 212, 23, 4017, 19 }, + { 34, 254, 212, 23, 4017, 19 }, + { 137, 254, 212, 23, 4017, 19 }, + { 240, 254, 212, 23, 4017, 19 }, + { 325, 254, 212, 23, 4017, 19 }, + { 410, 254, 212, 23, 4017, 19 }, + { 490, 254, 212, 23, 4017, 19 }, + { 560, 254, 212, 23, 4017, 19 }, + { 630, 254, 212, 23, 4017, 19 }, + { 700, 254, 212, 23, 4017, 19 }, + { 759, 254, 212, 23, 4017, 19 }, + { 52, 254, 212, 23, 4017, 19 }, + { 155, 254, 212, 23, 4017, 19 }, + { 82, 253, 2, 22, 3985, 19 }, + { 185, 253, 2, 22, 3985, 19 }, + { 270, 253, 2, 22, 3985, 19 }, + { 355, 253, 2, 22, 3985, 19 }, + { 435, 253, 2, 22, 3985, 19 }, + { 515, 253, 2, 22, 3985, 19 }, + { 585, 253, 2, 22, 3985, 19 }, + { 655, 253, 2, 22, 3985, 19 }, + { 722, 253, 2, 22, 3985, 19 }, + { 781, 253, 2, 22, 3985, 19 }, + { 12, 253, 2, 22, 3985, 19 }, + { 115, 253, 2, 22, 3985, 19 }, + { 218, 253, 2, 22, 3985, 19 }, + { 303, 253, 2, 22, 3985, 19 }, + { 388, 253, 2, 22, 3985, 19 }, + { 468, 253, 2, 22, 3985, 19 }, + { 548, 253, 2, 22, 3985, 19 }, + { 618, 253, 2, 22, 3985, 19 }, + { 688, 253, 2, 22, 3985, 19 }, + { 747, 253, 2, 22, 3985, 19 }, + { 40, 253, 2, 22, 3985, 19 }, + { 143, 253, 2, 22, 3985, 19 }, + { 246, 253, 2, 22, 3985, 19 }, + { 331, 253, 2, 22, 3985, 19 }, + { 416, 253, 2, 22, 3985, 19 }, + { 496, 253, 2, 22, 3985, 19 }, + { 566, 253, 2, 22, 3985, 19 }, + { 636, 253, 2, 22, 3985, 19 }, + { 706, 253, 2, 22, 3985, 19 }, + { 765, 253, 2, 22, 3985, 19 }, + { 58, 253, 2, 22, 3985, 19 }, + { 161, 253, 2, 22, 3985, 19 }, + { 824, 2, 241, 2, 3683, 0 }, + { 828, 2, 241, 2, 3683, 0 }, + { 794, 2, 241, 2, 3683, 0 }, + { 799, 2, 241, 2, 3683, 0 }, + { 804, 2, 241, 2, 3683, 0 }, + { 809, 2, 241, 2, 3683, 0 }, + { 814, 2, 241, 2, 3683, 0 }, + { 819, 2, 241, 2, 3683, 0 }, + { 912, 2, 237, 2, 3651, 0 }, + { 917, 2, 237, 2, 3651, 0 }, + { 876, 2, 237, 2, 3651, 0 }, + { 882, 2, 237, 2, 3651, 0 }, + { 888, 2, 237, 2, 3651, 0 }, + { 894, 2, 237, 2, 3651, 0 }, + { 900, 2, 237, 2, 3651, 0 }, + { 906, 2, 237, 2, 3651, 0 }, + { 862, 123, 235, 13, 51, 12 }, + { 866, 123, 235, 13, 51, 12 }, + { 832, 123, 235, 13, 51, 12 }, + { 837, 123, 235, 13, 51, 12 }, + { 842, 123, 235, 13, 51, 12 }, + { 847, 123, 235, 13, 51, 12 }, + { 852, 123, 235, 13, 51, 12 }, + { 857, 123, 235, 13, 51, 12 }, + { 1134, 62, 238, 3, 643, 5 }, + { 1138, 62, 238, 3, 643, 5 }, + { 1104, 62, 238, 3, 643, 5 }, + { 1109, 62, 238, 3, 643, 5 }, + { 1114, 62, 238, 3, 643, 5 }, + { 1119, 62, 238, 3, 643, 5 }, + { 1124, 62, 238, 3, 643, 5 }, + { 1129, 62, 238, 3, 643, 5 }, + { 980, 2, 234, 2, 3619, 0 }, + { 985, 2, 234, 2, 3619, 0 }, + { 944, 2, 234, 2, 3619, 0 }, + { 950, 2, 234, 2, 3619, 0 }, + { 956, 2, 234, 2, 3619, 0 }, + { 962, 2, 234, 2, 3619, 0 }, + { 968, 2, 234, 2, 3619, 0 }, + { 974, 2, 234, 2, 3619, 0 }, +}; + + // GR8 Register Class... + static const MCPhysReg GR8[] = { + X86_AL, X86_CL, X86_DL, X86_AH, X86_CH, X86_DH, X86_BL, X86_BH, X86_SIL, X86_DIL, X86_BPL, X86_SPL, X86_R8B, X86_R9B, X86_R10B, X86_R11B, X86_R14B, X86_R15B, X86_R12B, X86_R13B, + }; + // GR8 Bit set. + static const uint8_t GR8Bits[] = { + 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // GRH8 Register Class... + static const MCPhysReg GRH8[] = { + X86_SIH, X86_DIH, X86_BPH, X86_SPH, X86_R8BH, X86_R9BH, X86_R10BH, X86_R11BH, X86_R12BH, X86_R13BH, X86_R14BH, X86_R15BH, + }; + // GRH8 Bit set. + static const uint8_t GRH8Bits[] = { + 0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // GR8_NOREX Register Class... + static const MCPhysReg GR8_NOREX[] = { + X86_AL, X86_CL, X86_DL, X86_AH, X86_CH, X86_DH, X86_BL, X86_BH, + }; + // GR8_NOREX Bit set. + static const uint8_t GR8_NOREXBits[] = { + 0x36, 0x8c, 0x08, + }; + // GR8_ABCD_H Register Class... + static const MCPhysReg GR8_ABCD_H[] = { + X86_AH, X86_CH, X86_DH, X86_BH, + }; + // GR8_ABCD_H Bit set. + static const uint8_t GR8_ABCD_HBits[] = { + 0x12, 0x84, + }; + // GR8_ABCD_L Register Class... + static const MCPhysReg GR8_ABCD_L[] = { + X86_AL, X86_CL, X86_DL, X86_BL, + }; + // GR8_ABCD_L Bit set. + static const uint8_t GR8_ABCD_LBits[] = { + 0x24, 0x08, 0x08, + }; + // GRH16 Register Class... + static const MCPhysReg GRH16[] = { + X86_HAX, X86_HCX, X86_HDX, X86_HSI, X86_HDI, X86_HBX, X86_HBP, X86_HSP, X86_HIP, X86_R8WH, X86_R9WH, X86_R10WH, X86_R11WH, X86_R12WH, X86_R13WH, X86_R14WH, X86_R15WH, + }; + // GRH16 Bit set. + static const uint8_t GRH16Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // GR16 Register Class... + static const MCPhysReg GR16[] = { + X86_AX, X86_CX, X86_DX, X86_SI, X86_DI, X86_BX, X86_BP, X86_SP, X86_R8W, X86_R9W, X86_R10W, X86_R11W, X86_R14W, X86_R15W, X86_R12W, X86_R13W, + }; + // GR16 Bit set. + static const uint8_t GR16Bits[] = { + 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // GR16_NOREX Register Class... + static const MCPhysReg GR16_NOREX[] = { + X86_AX, X86_CX, X86_DX, X86_SI, X86_DI, X86_BX, X86_BP, X86_SP, + }; + // GR16_NOREX Bit set. + static const uint8_t GR16_NOREXBits[] = { + 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x12, + }; + // VK1 Register Class... + static const MCPhysReg VK1[] = { + X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK1 Bit set. + static const uint8_t VK1Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // VK16 Register Class... + static const MCPhysReg VK16[] = { + X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK16 Bit set. + static const uint8_t VK16Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // VK2 Register Class... + static const MCPhysReg VK2[] = { + X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK2 Bit set. + static const uint8_t VK2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // VK4 Register Class... + static const MCPhysReg VK4[] = { + X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK4 Bit set. + static const uint8_t VK4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // VK8 Register Class... + static const MCPhysReg VK8[] = { + X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK8 Bit set. + static const uint8_t VK8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // VK16WM Register Class... + static const MCPhysReg VK16WM[] = { + X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK16WM Bit set. + static const uint8_t VK16WMBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, + }; + // VK1WM Register Class... + static const MCPhysReg VK1WM[] = { + X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK1WM Bit set. + static const uint8_t VK1WMBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, + }; + // VK2WM Register Class... + static const MCPhysReg VK2WM[] = { + X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK2WM Bit set. + static const uint8_t VK2WMBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, + }; + // VK4WM Register Class... + static const MCPhysReg VK4WM[] = { + X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK4WM Bit set. + static const uint8_t VK4WMBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, + }; + // VK8WM Register Class... + static const MCPhysReg VK8WM[] = { + X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK8WM Bit set. + static const uint8_t VK8WMBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, + }; + // SEGMENT_REG Register Class... + static const MCPhysReg SEGMENT_REG[] = { + X86_CS, X86_DS, X86_SS, X86_ES, X86_FS, X86_GS, + }; + // SEGMENT_REG Bit set. + static const uint8_t SEGMENT_REGBits[] = { + 0x00, 0x10, 0x10, 0x80, 0x18, 0x00, 0x00, 0x80, + }; + // GR16_ABCD Register Class... + static const MCPhysReg GR16_ABCD[] = { + X86_AX, X86_CX, X86_DX, X86_BX, + }; + // GR16_ABCD Bit set. + static const uint8_t GR16_ABCDBits[] = { + 0x08, 0x22, 0x20, + }; + // FPCCR Register Class... + static const MCPhysReg FPCCR[] = { + X86_FPSW, + }; + // FPCCR Bit set. + static const uint8_t FPCCRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x04, + }; + // FR32X Register Class... + static const MCPhysReg FR32X[] = { + X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31, + }; + // FR32X Bit set. + static const uint8_t FR32XBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + // LOW32_ADDR_ACCESS_RBP Register Class... + static const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = { + X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, X86_RIP, X86_RBP, + }; + // LOW32_ADDR_ACCESS_RBP Bit set. + static const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = { + 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // LOW32_ADDR_ACCESS Register Class... + static const MCPhysReg LOW32_ADDR_ACCESS[] = { + X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, X86_RIP, + }; + // LOW32_ADDR_ACCESS Bit set. + static const uint8_t LOW32_ADDR_ACCESSBits[] = { + 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class... + static const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = { + X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, X86_RBP, + }; + // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set. + static const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = { + 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // DEBUG_REG Register Class... + static const MCPhysReg DEBUG_REG[] = { + X86_DR0, X86_DR1, X86_DR2, X86_DR3, X86_DR4, X86_DR5, X86_DR6, X86_DR7, X86_DR8, X86_DR9, X86_DR10, X86_DR11, X86_DR12, X86_DR13, X86_DR14, X86_DR15, + }; + // DEBUG_REG Bit set. + static const uint8_t DEBUG_REGBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, + }; + // FR32 Register Class... + static const MCPhysReg FR32[] = { + X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, + }; + // FR32 Bit set. + static const uint8_t FR32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, + }; + // GR32 Register Class... + static const MCPhysReg GR32[] = { + X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, + }; + // GR32 Bit set. + static const uint8_t GR32Bits[] = { + 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // GR32_NOSP Register Class... + static const MCPhysReg GR32_NOSP[] = { + X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, + }; + // GR32_NOSP Bit set. + static const uint8_t GR32_NOSPBits[] = { + 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class... + static const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = { + X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_RBP, + }; + // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set. + static const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = { + 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x01, + }; + // GR32_NOREX Register Class... + static const MCPhysReg GR32_NOREX[] = { + X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, + }; + // GR32_NOREX Bit set. + static const uint8_t GR32_NOREXBits[] = { + 0x00, 0x00, 0xc0, 0x0f, 0x03, + }; + // VK32 Register Class... + static const MCPhysReg VK32[] = { + X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK32 Bit set. + static const uint8_t VK32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // GR32_NOREX_NOSP Register Class... + static const MCPhysReg GR32_NOREX_NOSP[] = { + X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, + }; + // GR32_NOREX_NOSP Bit set. + static const uint8_t GR32_NOREX_NOSPBits[] = { + 0x00, 0x00, 0xc0, 0x0f, 0x01, + }; + // RFP32 Register Class... + static const MCPhysReg RFP32[] = { + X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6, + }; + // RFP32 Bit set. + static const uint8_t RFP32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, + }; + // VK32WM Register Class... + static const MCPhysReg VK32WM[] = { + X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK32WM Bit set. + static const uint8_t VK32WMBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, + }; + // GR32_ABCD Register Class... + static const MCPhysReg GR32_ABCD[] = { + X86_EAX, X86_ECX, X86_EDX, X86_EBX, + }; + // GR32_ABCD Bit set. + static const uint8_t GR32_ABCDBits[] = { + 0x00, 0x00, 0x40, 0x0b, + }; + // GR32_TC Register Class... + static const MCPhysReg GR32_TC[] = { + X86_EAX, X86_ECX, X86_EDX, + }; + // GR32_TC Bit set. + static const uint8_t GR32_TCBits[] = { + 0x00, 0x00, 0x40, 0x0a, + }; + // GR32_AD Register Class... + static const MCPhysReg GR32_AD[] = { + X86_EAX, X86_EDX, + }; + // GR32_AD Bit set. + static const uint8_t GR32_ADBits[] = { + 0x00, 0x00, 0x40, 0x08, + }; + // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class... + static const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = { + X86_RIP, X86_RBP, + }; + // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set. + static const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, + }; + // CCR Register Class... + static const MCPhysReg CCR[] = { + X86_EFLAGS, + }; + // CCR Bit set. + static const uint8_t CCRBits[] = { + 0x00, 0x00, 0x00, 0x10, + }; + // DFCCR Register Class... + static const MCPhysReg DFCCR[] = { + X86_DF, + }; + // DFCCR Bit set. + static const uint8_t DFCCRBits[] = { + 0x00, 0x40, + }; + // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class... + static const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = { + X86_RBP, + }; + // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set. + static const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + }; + // LOW32_ADDR_ACCESS_with_sub_32bit Register Class... + static const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = { + X86_RIP, + }; + // LOW32_ADDR_ACCESS_with_sub_32bit Bit set. + static const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + }; + // RFP64 Register Class... + static const MCPhysReg RFP64[] = { + X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6, + }; + // RFP64 Bit set. + static const uint8_t RFP64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, + }; + // FR64X Register Class... + static const MCPhysReg FR64X[] = { + X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31, + }; + // FR64X Bit set. + static const uint8_t FR64XBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + // GR64 Register Class... + static const MCPhysReg GR64[] = { + X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, X86_RSP, X86_RIP, + }; + // GR64 Bit set. + static const uint8_t GR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // CONTROL_REG Register Class... + static const MCPhysReg CONTROL_REG[] = { + X86_CR0, X86_CR1, X86_CR2, X86_CR3, X86_CR4, X86_CR5, X86_CR6, X86_CR7, X86_CR8, X86_CR9, X86_CR10, X86_CR11, X86_CR12, X86_CR13, X86_CR14, X86_CR15, + }; + // CONTROL_REG Bit set. + static const uint8_t CONTROL_REGBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, + }; + // FR64 Register Class... + static const MCPhysReg FR64[] = { + X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, + }; + // FR64 Bit set. + static const uint8_t FR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, + }; + // GR64_with_sub_8bit Register Class... + static const MCPhysReg GR64_with_sub_8bit[] = { + X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, X86_RSP, + }; + // GR64_with_sub_8bit Bit set. + static const uint8_t GR64_with_sub_8bitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // GR64_NOSP Register Class... + static const MCPhysReg GR64_NOSP[] = { + X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, + }; + // GR64_NOSP Bit set. + static const uint8_t GR64_NOSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // GR64_NOREX Register Class... + static const MCPhysReg GR64_NOREX[] = { + X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, X86_RSP, X86_RIP, + }; + // GR64_NOREX Bit set. + static const uint8_t GR64_NOREXBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, + }; + // GR64_TC Register Class... + static const MCPhysReg GR64_TC[] = { + X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R11, X86_RIP, + }; + // GR64_TC Bit set. + static const uint8_t GR64_TCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, + }; + // GR64_NOSP_and_GR64_TC Register Class... + static const MCPhysReg GR64_NOSP_and_GR64_TC[] = { + X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R11, + }; + // GR64_NOSP_and_GR64_TC Bit set. + static const uint8_t GR64_NOSP_and_GR64_TCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, + }; + // GR64_TCW64 Register Class... + static const MCPhysReg GR64_TCW64[] = { + X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R10, X86_R11, X86_RIP, + }; + // GR64_TCW64 Bit set. + static const uint8_t GR64_TCW64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, + }; + // GR64_with_sub_16bit_in_GR16_NOREX Register Class... + static const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = { + X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, X86_RSP, + }; + // GR64_with_sub_16bit_in_GR16_NOREX Bit set. + static const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, + }; + // VK64 Register Class... + static const MCPhysReg VK64[] = { + X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK64 Bit set. + static const uint8_t VK64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // VR64 Register Class... + static const MCPhysReg VR64[] = { + X86_MM0, X86_MM1, X86_MM2, X86_MM3, X86_MM4, X86_MM5, X86_MM6, X86_MM7, + }; + // VR64 Bit set. + static const uint8_t VR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // GR64_NOREX_NOSP Register Class... + static const MCPhysReg GR64_NOREX_NOSP[] = { + X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, + }; + // GR64_NOREX_NOSP Bit set. + static const uint8_t GR64_NOREX_NOSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, + }; + // GR64_NOSP_and_GR64_TCW64 Register Class... + static const MCPhysReg GR64_NOSP_and_GR64_TCW64[] = { + X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R10, X86_R11, + }; + // GR64_NOSP_and_GR64_TCW64 Bit set. + static const uint8_t GR64_NOSP_and_GR64_TCW64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, + }; + // GR64_TC_and_GR64_TCW64 Register Class... + static const MCPhysReg GR64_TC_and_GR64_TCW64[] = { + X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R11, X86_RIP, + }; + // GR64_TC_and_GR64_TCW64 Bit set. + static const uint8_t GR64_TC_and_GR64_TCW64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, + }; + // VK64WM Register Class... + static const MCPhysReg VK64WM[] = { + X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, + }; + // VK64WM Bit set. + static const uint8_t VK64WMBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, + }; + // GR64_NOREX_and_GR64_TC Register Class... + static const MCPhysReg GR64_NOREX_and_GR64_TC[] = { + X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RIP, + }; + // GR64_NOREX_and_GR64_TC Bit set. + static const uint8_t GR64_NOREX_and_GR64_TCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbc, + }; + // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Register Class... + static const MCPhysReg GR64_TC_and_GR64_NOSP_and_GR64_TCW64[] = { + X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R11, + }; + // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Bit set. + static const uint8_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, + }; + // GR64_NOREX_NOSP_and_GR64_TC Register Class... + static const MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = { + X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, + }; + // GR64_NOREX_NOSP_and_GR64_TC Bit set. + static const uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, + }; + // GR64_ABCD Register Class... + static const MCPhysReg GR64_ABCD[] = { + X86_RAX, X86_RCX, X86_RDX, X86_RBX, + }; + // GR64_ABCD Bit set. + static const uint8_t GR64_ABCDBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x16, + }; + // GR64_NOREX_and_GR64_TCW64 Register Class... + static const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = { + X86_RAX, X86_RCX, X86_RDX, X86_RIP, + }; + // GR64_NOREX_and_GR64_TCW64 Bit set. + static const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, + }; + // GR64_with_sub_32bit_in_GR32_TC Register Class... + static const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = { + X86_RAX, X86_RCX, X86_RDX, + }; + // GR64_with_sub_32bit_in_GR32_TC Bit set. + static const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, + }; + // GR64_AD Register Class... + static const MCPhysReg GR64_AD[] = { + X86_RAX, X86_RDX, + }; + // GR64_AD Bit set. + static const uint8_t GR64_ADBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10, + }; + // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class... + static const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = { + X86_RBP, X86_RIP, + }; + // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set. + static const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, + }; + // GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP Register Class... + static const MCPhysReg GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP[] = { + X86_RBP, + }; + // GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP Bit set. + static const uint8_t GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + }; + // GR64_and_LOW32_ADDR_ACCESS Register Class... + static const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = { + X86_RIP, + }; + // GR64_and_LOW32_ADDR_ACCESS Bit set. + static const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + }; + // RST Register Class... + static const MCPhysReg RST[] = { + X86_ST0, X86_ST1, X86_ST2, X86_ST3, X86_ST4, X86_ST5, X86_ST6, X86_ST7, + }; + // RST Bit set. + static const uint8_t RSTBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // RFP80 Register Class... + static const MCPhysReg RFP80[] = { + X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6, + }; + // RFP80 Bit set. + static const uint8_t RFP80Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, + }; + // VR128X Register Class... + static const MCPhysReg VR128X[] = { + X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31, + }; + // VR128X Bit set. + static const uint8_t VR128XBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + // VR128 Register Class... + static const MCPhysReg VR128[] = { + X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, + }; + // VR128 Bit set. + static const uint8_t VR128Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, + }; + // VR128H Register Class... + static const MCPhysReg VR128H[] = { + X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, + }; + // VR128H Bit set. + static const uint8_t VR128HBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // VR128L Register Class... + static const MCPhysReg VR128L[] = { + X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, + }; + // VR128L Bit set. + static const uint8_t VR128LBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // BNDR Register Class... + static const MCPhysReg BNDR[] = { + X86_BND0, X86_BND1, X86_BND2, X86_BND3, + }; + // BNDR Bit set. + static const uint8_t BNDRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, + }; + // VR256X Register Class... + static const MCPhysReg VR256X[] = { + X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7, X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15, X86_YMM16, X86_YMM17, X86_YMM18, X86_YMM19, X86_YMM20, X86_YMM21, X86_YMM22, X86_YMM23, X86_YMM24, X86_YMM25, X86_YMM26, X86_YMM27, X86_YMM28, X86_YMM29, X86_YMM30, X86_YMM31, + }; + // VR256X Bit set. + static const uint8_t VR256XBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + // VR256 Register Class... + static const MCPhysReg VR256[] = { + X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7, X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15, + }; + // VR256 Bit set. + static const uint8_t VR256Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, + }; + // VR256H Register Class... + static const MCPhysReg VR256H[] = { + X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15, + }; + // VR256H Bit set. + static const uint8_t VR256HBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // VR256L Register Class... + static const MCPhysReg VR256L[] = { + X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7, + }; + // VR256L Bit set. + static const uint8_t VR256LBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // VR512 Register Class... + static const MCPhysReg VR512[] = { + X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7, X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15, X86_ZMM16, X86_ZMM17, X86_ZMM18, X86_ZMM19, X86_ZMM20, X86_ZMM21, X86_ZMM22, X86_ZMM23, X86_ZMM24, X86_ZMM25, X86_ZMM26, X86_ZMM27, X86_ZMM28, X86_ZMM29, X86_ZMM30, X86_ZMM31, + }; + // VR512 Bit set. + static const uint8_t VR512Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + // VR512_with_sub_xmm_in_FR32 Register Class... + static const MCPhysReg VR512_with_sub_xmm_in_FR32[] = { + X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7, X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15, + }; + // VR512_with_sub_xmm_in_FR32 Bit set. + static const uint8_t VR512_with_sub_xmm_in_FR32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, + }; + // VR512_with_sub_xmm_in_VR128H Register Class... + static const MCPhysReg VR512_with_sub_xmm_in_VR128H[] = { + X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15, + }; + // VR512_with_sub_xmm_in_VR128H Bit set. + static const uint8_t VR512_with_sub_xmm_in_VR128HBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // VR512_with_sub_xmm_in_VR128L Register Class... + static const MCPhysReg VR512_with_sub_xmm_in_VR128L[] = { + X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7, + }; + // VR512_with_sub_xmm_in_VR128L Bit set. + static const uint8_t VR512_with_sub_xmm_in_VR128LBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + + +static const MCRegisterClass X86MCRegisterClasses[] = { + { GR8, GR8Bits, sizeof(GR8Bits) }, + { GRH8, GRH8Bits, sizeof(GRH8Bits) }, + { GR8_NOREX, GR8_NOREXBits, sizeof(GR8_NOREXBits) }, + { GR8_ABCD_H, GR8_ABCD_HBits, sizeof(GR8_ABCD_HBits) }, + { GR8_ABCD_L, GR8_ABCD_LBits, sizeof(GR8_ABCD_LBits) }, + { GRH16, GRH16Bits, sizeof(GRH16Bits) }, + { GR16, GR16Bits, sizeof(GR16Bits) }, + { GR16_NOREX, GR16_NOREXBits, sizeof(GR16_NOREXBits) }, + { VK1, VK1Bits, sizeof(VK1Bits) }, + { VK16, VK16Bits, sizeof(VK16Bits) }, + { VK2, VK2Bits, sizeof(VK2Bits) }, + { VK4, VK4Bits, sizeof(VK4Bits) }, + { VK8, VK8Bits, sizeof(VK8Bits) }, + { VK16WM, VK16WMBits, sizeof(VK16WMBits) }, + { VK1WM, VK1WMBits, sizeof(VK1WMBits) }, + { VK2WM, VK2WMBits, sizeof(VK2WMBits) }, + { VK4WM, VK4WMBits, sizeof(VK4WMBits) }, + { VK8WM, VK8WMBits, sizeof(VK8WMBits) }, + { SEGMENT_REG, SEGMENT_REGBits, sizeof(SEGMENT_REGBits) }, + { GR16_ABCD, GR16_ABCDBits, sizeof(GR16_ABCDBits) }, + { FPCCR, FPCCRBits, sizeof(FPCCRBits) }, + { FR32X, FR32XBits, sizeof(FR32XBits) }, + { LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, sizeof(LOW32_ADDR_ACCESS_RBPBits) }, + { LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, sizeof(LOW32_ADDR_ACCESSBits) }, + { LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits) }, + { DEBUG_REG, DEBUG_REGBits, sizeof(DEBUG_REGBits) }, + { FR32, FR32Bits, sizeof(FR32Bits) }, + { GR32, GR32Bits, sizeof(GR32Bits) }, + { GR32_NOSP, GR32_NOSPBits, sizeof(GR32_NOSPBits) }, + { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits) }, + { GR32_NOREX, GR32_NOREXBits, sizeof(GR32_NOREXBits) }, + { VK32, VK32Bits, sizeof(VK32Bits) }, + { GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, sizeof(GR32_NOREX_NOSPBits) }, + { RFP32, RFP32Bits, sizeof(RFP32Bits) }, + { VK32WM, VK32WMBits, sizeof(VK32WMBits) }, + { GR32_ABCD, GR32_ABCDBits, sizeof(GR32_ABCDBits) }, + { GR32_TC, GR32_TCBits, sizeof(GR32_TCBits) }, + { GR32_AD, GR32_ADBits, sizeof(GR32_ADBits) }, + { LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits) }, + { CCR, CCRBits, sizeof(CCRBits) }, + { DFCCR, DFCCRBits, sizeof(DFCCRBits) }, + { LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits) }, + { LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits) }, + { RFP64, RFP64Bits, sizeof(RFP64Bits) }, + { FR64X, FR64XBits, sizeof(FR64XBits) }, + { GR64, GR64Bits, sizeof(GR64Bits) }, + { CONTROL_REG, CONTROL_REGBits, sizeof(CONTROL_REGBits) }, + { FR64, FR64Bits, sizeof(FR64Bits) }, + { GR64_with_sub_8bit, GR64_with_sub_8bitBits, sizeof(GR64_with_sub_8bitBits) }, + { GR64_NOSP, GR64_NOSPBits, sizeof(GR64_NOSPBits) }, + { GR64_NOREX, GR64_NOREXBits, sizeof(GR64_NOREXBits) }, + { GR64_TC, GR64_TCBits, sizeof(GR64_TCBits) }, + { GR64_NOSP_and_GR64_TC, GR64_NOSP_and_GR64_TCBits, sizeof(GR64_NOSP_and_GR64_TCBits) }, + { GR64_TCW64, GR64_TCW64Bits, sizeof(GR64_TCW64Bits) }, + { GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits) }, + { VK64, VK64Bits, sizeof(VK64Bits) }, + { VR64, VR64Bits, sizeof(VR64Bits) }, + { GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, sizeof(GR64_NOREX_NOSPBits) }, + { GR64_NOSP_and_GR64_TCW64, GR64_NOSP_and_GR64_TCW64Bits, sizeof(GR64_NOSP_and_GR64_TCW64Bits) }, + { GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, sizeof(GR64_TC_and_GR64_TCW64Bits) }, + { VK64WM, VK64WMBits, sizeof(VK64WMBits) }, + { GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, sizeof(GR64_NOREX_and_GR64_TCBits) }, + { GR64_TC_and_GR64_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits, sizeof(GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits) }, + { GR64_NOREX_NOSP_and_GR64_TC, GR64_NOREX_NOSP_and_GR64_TCBits, sizeof(GR64_NOREX_NOSP_and_GR64_TCBits) }, + { GR64_ABCD, GR64_ABCDBits, sizeof(GR64_ABCDBits) }, + { GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, sizeof(GR64_NOREX_and_GR64_TCW64Bits) }, + { GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, sizeof(GR64_with_sub_32bit_in_GR32_TCBits) }, + { GR64_AD, GR64_ADBits, sizeof(GR64_ADBits) }, + { GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits) }, + { GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP, GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPBits, sizeof(GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPBits) }, + { GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, sizeof(GR64_and_LOW32_ADDR_ACCESSBits) }, + { RST, RSTBits, sizeof(RSTBits) }, + { RFP80, RFP80Bits, sizeof(RFP80Bits) }, + { VR128X, VR128XBits, sizeof(VR128XBits) }, + { VR128, VR128Bits, sizeof(VR128Bits) }, + { VR128H, VR128HBits, sizeof(VR128HBits) }, + { VR128L, VR128LBits, sizeof(VR128LBits) }, + { BNDR, BNDRBits, sizeof(BNDRBits) }, + { VR256X, VR256XBits, sizeof(VR256XBits) }, + { VR256, VR256Bits, sizeof(VR256Bits) }, + { VR256H, VR256HBits, sizeof(VR256HBits) }, + { VR256L, VR256LBits, sizeof(VR256LBits) }, + { VR512, VR512Bits, sizeof(VR512Bits) }, + { VR512_with_sub_xmm_in_FR32, VR512_with_sub_xmm_in_FR32Bits, sizeof(VR512_with_sub_xmm_in_FR32Bits) }, + { VR512_with_sub_xmm_in_VR128H, VR512_with_sub_xmm_in_VR128HBits, sizeof(VR512_with_sub_xmm_in_VR128HBits) }, + { VR512_with_sub_xmm_in_VR128L, VR512_with_sub_xmm_in_VR128LBits, sizeof(VR512_with_sub_xmm_in_VR128LBits) }, +}; + +#endif // GET_REGINFO_MC_DESC \ No newline at end of file diff --git a/thirdparty/capstone/arch/X86/X86GenRegisterName.inc b/thirdparty/capstone/arch/X86/X86GenRegisterName.inc new file mode 100644 index 0000000..5de67c0 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenRegisterName.inc @@ -0,0 +1,292 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName(unsigned RegNo) +{ + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 's', 't', '(', '0', ')', 0, + /* 6 */ 's', 't', '(', '1', ')', 0, + /* 12 */ 's', 't', '(', '2', ')', 0, + /* 18 */ 's', 't', '(', '3', ')', 0, + /* 24 */ 's', 't', '(', '4', ')', 0, + /* 30 */ 's', 't', '(', '5', ')', 0, + /* 36 */ 's', 't', '(', '6', ')', 0, + /* 42 */ 's', 't', '(', '7', ')', 0, + /* 48 */ 'x', 'm', 'm', '1', '0', 0, + /* 54 */ 'y', 'm', 'm', '1', '0', 0, + /* 60 */ 'z', 'm', 'm', '1', '0', 0, + /* 66 */ 'c', 'r', '1', '0', 0, + /* 71 */ 'd', 'r', '1', '0', 0, + /* 76 */ 'x', 'm', 'm', '2', '0', 0, + /* 82 */ 'y', 'm', 'm', '2', '0', 0, + /* 88 */ 'z', 'm', 'm', '2', '0', 0, + /* 94 */ 'x', 'm', 'm', '3', '0', 0, + /* 100 */ 'y', 'm', 'm', '3', '0', 0, + /* 106 */ 'z', 'm', 'm', '3', '0', 0, + /* 112 */ 'b', 'n', 'd', '0', 0, + /* 117 */ 'k', '0', 0, + /* 120 */ 'x', 'm', 'm', '0', 0, + /* 125 */ 'y', 'm', 'm', '0', 0, + /* 130 */ 'z', 'm', 'm', '0', 0, + /* 135 */ 'f', 'p', '0', 0, + /* 139 */ 'c', 'r', '0', 0, + /* 143 */ 'd', 'r', '0', 0, + /* 147 */ 'x', 'm', 'm', '1', '1', 0, + /* 153 */ 'y', 'm', 'm', '1', '1', 0, + /* 159 */ 'z', 'm', 'm', '1', '1', 0, + /* 165 */ 'c', 'r', '1', '1', 0, + /* 170 */ 'd', 'r', '1', '1', 0, + /* 175 */ 'x', 'm', 'm', '2', '1', 0, + /* 181 */ 'y', 'm', 'm', '2', '1', 0, + /* 187 */ 'z', 'm', 'm', '2', '1', 0, + /* 193 */ 'x', 'm', 'm', '3', '1', 0, + /* 199 */ 'y', 'm', 'm', '3', '1', 0, + /* 205 */ 'z', 'm', 'm', '3', '1', 0, + /* 211 */ 'b', 'n', 'd', '1', 0, + /* 216 */ 'k', '1', 0, + /* 219 */ 'x', 'm', 'm', '1', 0, + /* 224 */ 'y', 'm', 'm', '1', 0, + /* 229 */ 'z', 'm', 'm', '1', 0, + /* 234 */ 'f', 'p', '1', 0, + /* 238 */ 'c', 'r', '1', 0, + /* 242 */ 'd', 'r', '1', 0, + /* 246 */ 'x', 'm', 'm', '1', '2', 0, + /* 252 */ 'y', 'm', 'm', '1', '2', 0, + /* 258 */ 'z', 'm', 'm', '1', '2', 0, + /* 264 */ 'c', 'r', '1', '2', 0, + /* 269 */ 'd', 'r', '1', '2', 0, + /* 274 */ 'x', 'm', 'm', '2', '2', 0, + /* 280 */ 'y', 'm', 'm', '2', '2', 0, + /* 286 */ 'z', 'm', 'm', '2', '2', 0, + /* 292 */ 'b', 'n', 'd', '2', 0, + /* 297 */ 'k', '2', 0, + /* 300 */ 'x', 'm', 'm', '2', 0, + /* 305 */ 'y', 'm', 'm', '2', 0, + /* 310 */ 'z', 'm', 'm', '2', 0, + /* 315 */ 'f', 'p', '2', 0, + /* 319 */ 'c', 'r', '2', 0, + /* 323 */ 'd', 'r', '2', 0, + /* 327 */ 'x', 'm', 'm', '1', '3', 0, + /* 333 */ 'y', 'm', 'm', '1', '3', 0, + /* 339 */ 'z', 'm', 'm', '1', '3', 0, + /* 345 */ 'c', 'r', '1', '3', 0, + /* 350 */ 'd', 'r', '1', '3', 0, + /* 355 */ 'x', 'm', 'm', '2', '3', 0, + /* 361 */ 'y', 'm', 'm', '2', '3', 0, + /* 367 */ 'z', 'm', 'm', '2', '3', 0, + /* 373 */ 'b', 'n', 'd', '3', 0, + /* 378 */ 'k', '3', 0, + /* 381 */ 'x', 'm', 'm', '3', 0, + /* 386 */ 'y', 'm', 'm', '3', 0, + /* 391 */ 'z', 'm', 'm', '3', 0, + /* 396 */ 'f', 'p', '3', 0, + /* 400 */ 'c', 'r', '3', 0, + /* 404 */ 'd', 'r', '3', 0, + /* 408 */ 'x', 'm', 'm', '1', '4', 0, + /* 414 */ 'y', 'm', 'm', '1', '4', 0, + /* 420 */ 'z', 'm', 'm', '1', '4', 0, + /* 426 */ 'c', 'r', '1', '4', 0, + /* 431 */ 'd', 'r', '1', '4', 0, + /* 436 */ 'x', 'm', 'm', '2', '4', 0, + /* 442 */ 'y', 'm', 'm', '2', '4', 0, + /* 448 */ 'z', 'm', 'm', '2', '4', 0, + /* 454 */ 'k', '4', 0, + /* 457 */ 'x', 'm', 'm', '4', 0, + /* 462 */ 'y', 'm', 'm', '4', 0, + /* 467 */ 'z', 'm', 'm', '4', 0, + /* 472 */ 'f', 'p', '4', 0, + /* 476 */ 'c', 'r', '4', 0, + /* 480 */ 'd', 'r', '4', 0, + /* 484 */ 'x', 'm', 'm', '1', '5', 0, + /* 490 */ 'y', 'm', 'm', '1', '5', 0, + /* 496 */ 'z', 'm', 'm', '1', '5', 0, + /* 502 */ 'c', 'r', '1', '5', 0, + /* 507 */ 'd', 'r', '1', '5', 0, + /* 512 */ 'x', 'm', 'm', '2', '5', 0, + /* 518 */ 'y', 'm', 'm', '2', '5', 0, + /* 524 */ 'z', 'm', 'm', '2', '5', 0, + /* 530 */ 'k', '5', 0, + /* 533 */ 'x', 'm', 'm', '5', 0, + /* 538 */ 'y', 'm', 'm', '5', 0, + /* 543 */ 'z', 'm', 'm', '5', 0, + /* 548 */ 'f', 'p', '5', 0, + /* 552 */ 'c', 'r', '5', 0, + /* 556 */ 'd', 'r', '5', 0, + /* 560 */ 'x', 'm', 'm', '1', '6', 0, + /* 566 */ 'y', 'm', 'm', '1', '6', 0, + /* 572 */ 'z', 'm', 'm', '1', '6', 0, + /* 578 */ 'x', 'm', 'm', '2', '6', 0, + /* 584 */ 'y', 'm', 'm', '2', '6', 0, + /* 590 */ 'z', 'm', 'm', '2', '6', 0, + /* 596 */ 'k', '6', 0, + /* 599 */ 'x', 'm', 'm', '6', 0, + /* 604 */ 'y', 'm', 'm', '6', 0, + /* 609 */ 'z', 'm', 'm', '6', 0, + /* 614 */ 'f', 'p', '6', 0, + /* 618 */ 'c', 'r', '6', 0, + /* 622 */ 'd', 'r', '6', 0, + /* 626 */ 'x', 'm', 'm', '1', '7', 0, + /* 632 */ 'y', 'm', 'm', '1', '7', 0, + /* 638 */ 'z', 'm', 'm', '1', '7', 0, + /* 644 */ 'x', 'm', 'm', '2', '7', 0, + /* 650 */ 'y', 'm', 'm', '2', '7', 0, + /* 656 */ 'z', 'm', 'm', '2', '7', 0, + /* 662 */ 'k', '7', 0, + /* 665 */ 'x', 'm', 'm', '7', 0, + /* 670 */ 'y', 'm', 'm', '7', 0, + /* 675 */ 'z', 'm', 'm', '7', 0, + /* 680 */ 'f', 'p', '7', 0, + /* 684 */ 'c', 'r', '7', 0, + /* 688 */ 'd', 'r', '7', 0, + /* 692 */ 'x', 'm', 'm', '1', '8', 0, + /* 698 */ 'y', 'm', 'm', '1', '8', 0, + /* 704 */ 'z', 'm', 'm', '1', '8', 0, + /* 710 */ 'x', 'm', 'm', '2', '8', 0, + /* 716 */ 'y', 'm', 'm', '2', '8', 0, + /* 722 */ 'z', 'm', 'm', '2', '8', 0, + /* 728 */ 'x', 'm', 'm', '8', 0, + /* 733 */ 'y', 'm', 'm', '8', 0, + /* 738 */ 'z', 'm', 'm', '8', 0, + /* 743 */ 'c', 'r', '8', 0, + /* 747 */ 'd', 'r', '8', 0, + /* 751 */ 'x', 'm', 'm', '1', '9', 0, + /* 757 */ 'y', 'm', 'm', '1', '9', 0, + /* 763 */ 'z', 'm', 'm', '1', '9', 0, + /* 769 */ 'x', 'm', 'm', '2', '9', 0, + /* 775 */ 'y', 'm', 'm', '2', '9', 0, + /* 781 */ 'z', 'm', 'm', '2', '9', 0, + /* 787 */ 'x', 'm', 'm', '9', 0, + /* 792 */ 'y', 'm', 'm', '9', 0, + /* 797 */ 'z', 'm', 'm', '9', 0, + /* 802 */ 'c', 'r', '9', 0, + /* 806 */ 'd', 'r', '9', 0, + /* 810 */ 'R', '1', '0', 'B', 'H', 0, + /* 816 */ 'R', '1', '1', 'B', 'H', 0, + /* 822 */ 'R', '1', '2', 'B', 'H', 0, + /* 828 */ 'R', '1', '3', 'B', 'H', 0, + /* 834 */ 'R', '1', '4', 'B', 'H', 0, + /* 840 */ 'R', '1', '5', 'B', 'H', 0, + /* 846 */ 'R', '8', 'B', 'H', 0, + /* 851 */ 'R', '9', 'B', 'H', 0, + /* 856 */ 'D', 'I', 'H', 0, + /* 860 */ 'S', 'I', 'H', 0, + /* 864 */ 'B', 'P', 'H', 0, + /* 868 */ 'S', 'P', 'H', 0, + /* 872 */ 'R', '1', '0', 'W', 'H', 0, + /* 878 */ 'R', '1', '1', 'W', 'H', 0, + /* 884 */ 'R', '1', '2', 'W', 'H', 0, + /* 890 */ 'R', '1', '3', 'W', 'H', 0, + /* 896 */ 'R', '1', '4', 'W', 'H', 0, + /* 902 */ 'R', '1', '5', 'W', 'H', 0, + /* 908 */ 'R', '8', 'W', 'H', 0, + /* 913 */ 'R', '9', 'W', 'H', 0, + /* 918 */ 'H', 'D', 'I', 0, + /* 922 */ 'H', 'S', 'I', 0, + /* 926 */ 'H', 'B', 'P', 0, + /* 930 */ 'H', 'I', 'P', 0, + /* 934 */ 'H', 'S', 'P', 0, + /* 938 */ 'H', 'A', 'X', 0, + /* 942 */ 'H', 'B', 'X', 0, + /* 946 */ 'H', 'C', 'X', 0, + /* 950 */ 'H', 'D', 'X', 0, + /* 954 */ 'r', '1', '0', 'b', 0, + /* 959 */ 'r', '1', '1', 'b', 0, + /* 964 */ 'r', '1', '2', 'b', 0, + /* 969 */ 'r', '1', '3', 'b', 0, + /* 974 */ 'r', '1', '4', 'b', 0, + /* 979 */ 'r', '1', '5', 'b', 0, + /* 984 */ 'r', '8', 'b', 0, + /* 988 */ 'r', '9', 'b', 0, + /* 992 */ 'r', '1', '0', 'd', 0, + /* 997 */ 'r', '1', '1', 'd', 0, + /* 1002 */ 'r', '1', '2', 'd', 0, + /* 1007 */ 'r', '1', '3', 'd', 0, + /* 1012 */ 'r', '1', '4', 'd', 0, + /* 1017 */ 'r', '1', '5', 'd', 0, + /* 1022 */ 'r', '8', 'd', 0, + /* 1026 */ 'r', '9', 'd', 0, + /* 1030 */ 'd', 'i', 'r', 'f', 'l', 'a', 'g', 0, + /* 1038 */ 'a', 'h', 0, + /* 1041 */ 'b', 'h', 0, + /* 1044 */ 'c', 'h', 0, + /* 1047 */ 'd', 'h', 0, + /* 1050 */ 'e', 'd', 'i', 0, + /* 1054 */ 'r', 'd', 'i', 0, + /* 1058 */ 'e', 's', 'i', 0, + /* 1062 */ 'r', 's', 'i', 0, + /* 1066 */ 'a', 'l', 0, + /* 1069 */ 'b', 'l', 0, + /* 1072 */ 'c', 'l', 0, + /* 1075 */ 'd', 'l', 0, + /* 1078 */ 'd', 'i', 'l', 0, + /* 1082 */ 's', 'i', 'l', 0, + /* 1086 */ 'b', 'p', 'l', 0, + /* 1090 */ 's', 'p', 'l', 0, + /* 1094 */ 'e', 'b', 'p', 0, + /* 1098 */ 'r', 'b', 'p', 0, + /* 1102 */ 'e', 'i', 'p', 0, + /* 1106 */ 'r', 'i', 'p', 0, + /* 1110 */ 'e', 's', 'p', 0, + /* 1114 */ 'r', 's', 'p', 0, + /* 1118 */ 's', 's', 'p', 0, + /* 1122 */ 'c', 's', 0, + /* 1125 */ 'd', 's', 0, + /* 1128 */ 'e', 's', 0, + /* 1131 */ 'f', 's', 0, + /* 1134 */ 'f', 'l', 'a', 'g', 's', 0, + /* 1140 */ 's', 's', 0, + /* 1143 */ 'r', '1', '0', 'w', 0, + /* 1148 */ 'r', '1', '1', 'w', 0, + /* 1153 */ 'r', '1', '2', 'w', 0, + /* 1158 */ 'r', '1', '3', 'w', 0, + /* 1163 */ 'r', '1', '4', 'w', 0, + /* 1168 */ 'r', '1', '5', 'w', 0, + /* 1173 */ 'r', '8', 'w', 0, + /* 1177 */ 'r', '9', 'w', 0, + /* 1181 */ 'f', 'p', 's', 'w', 0, + /* 1186 */ 'e', 'a', 'x', 0, + /* 1190 */ 'r', 'a', 'x', 0, + /* 1194 */ 'e', 'b', 'x', 0, + /* 1198 */ 'r', 'b', 'x', 0, + /* 1202 */ 'e', 'c', 'x', 0, + /* 1206 */ 'r', 'c', 'x', 0, + /* 1210 */ 'e', 'd', 'x', 0, + /* 1214 */ 'r', 'd', 'x', 0, + /* 1218 */ 'e', 'i', 'z', 0, + /* 1222 */ 'r', 'i', 'z', 0, + }; + + static const uint16_t RegAsmOffset[] = { + 1038, 1066, 1187, 1041, 1069, 1095, 864, 1086, 1195, 1044, 1072, 1122, 1203, 1030, + 1047, 1051, 856, 1078, 1075, 1125, 1211, 1186, 1094, 1194, 1202, 1050, 1210, 1134, + 1102, 1218, 1128, 1058, 1110, 1181, 1131, 1137, 938, 926, 942, 946, 918, 950, + 930, 922, 934, 1103, 1190, 1098, 1198, 1206, 1054, 1214, 1106, 1222, 1062, 1114, + 1059, 860, 1082, 1111, 868, 1090, 1140, 1118, 112, 211, 292, 373, 139, 238, + 319, 400, 476, 552, 618, 684, 743, 802, 66, 165, 264, 345, 426, 502, + 143, 242, 323, 404, 480, 556, 622, 688, 747, 806, 71, 170, 269, 350, + 431, 507, 135, 234, 315, 396, 472, 548, 614, 680, 117, 216, 297, 378, + 454, 530, 596, 662, 121, 220, 301, 382, 458, 534, 600, 666, 744, 803, + 67, 166, 265, 346, 427, 503, 0, 6, 12, 18, 24, 30, 36, 42, + 120, 219, 300, 381, 457, 533, 599, 665, 728, 787, 48, 147, 246, 327, + 408, 484, 560, 626, 692, 751, 76, 175, 274, 355, 436, 512, 578, 644, + 710, 769, 94, 193, 125, 224, 305, 386, 462, 538, 604, 670, 733, 792, + 54, 153, 252, 333, 414, 490, 566, 632, 698, 757, 82, 181, 280, 361, + 442, 518, 584, 650, 716, 775, 100, 199, 130, 229, 310, 391, 467, 543, + 609, 675, 738, 797, 60, 159, 258, 339, 420, 496, 572, 638, 704, 763, + 88, 187, 286, 367, 448, 524, 590, 656, 722, 781, 106, 205, 984, 988, + 954, 959, 964, 969, 974, 979, 846, 851, 810, 816, 822, 828, 834, 840, + 1022, 1026, 992, 997, 1002, 1007, 1012, 1017, 1173, 1177, 1143, 1148, 1153, 1158, + 1163, 1168, 908, 913, 872, 878, 884, 890, 896, 902, + }; + + return AsmStrs+RegAsmOffset[RegNo-1]; +#else + return NULL; +#endif +} + diff --git a/thirdparty/capstone/arch/X86/X86GenRegisterName1.inc b/thirdparty/capstone/arch/X86/X86GenRegisterName1.inc new file mode 100644 index 0000000..bf805d9 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86GenRegisterName1.inc @@ -0,0 +1,291 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName(unsigned RegNo) +{ + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 's', 't', '(', '0', ')', 0, + /* 6 */ 's', 't', '(', '1', ')', 0, + /* 12 */ 's', 't', '(', '2', ')', 0, + /* 18 */ 's', 't', '(', '3', ')', 0, + /* 24 */ 's', 't', '(', '4', ')', 0, + /* 30 */ 's', 't', '(', '5', ')', 0, + /* 36 */ 's', 't', '(', '6', ')', 0, + /* 42 */ 's', 't', '(', '7', ')', 0, + /* 48 */ 'x', 'm', 'm', '1', '0', 0, + /* 54 */ 'y', 'm', 'm', '1', '0', 0, + /* 60 */ 'z', 'm', 'm', '1', '0', 0, + /* 66 */ 'c', 'r', '1', '0', 0, + /* 71 */ 'd', 'r', '1', '0', 0, + /* 76 */ 'x', 'm', 'm', '2', '0', 0, + /* 82 */ 'y', 'm', 'm', '2', '0', 0, + /* 88 */ 'z', 'm', 'm', '2', '0', 0, + /* 94 */ 'x', 'm', 'm', '3', '0', 0, + /* 100 */ 'y', 'm', 'm', '3', '0', 0, + /* 106 */ 'z', 'm', 'm', '3', '0', 0, + /* 112 */ 'b', 'n', 'd', '0', 0, + /* 117 */ 'k', '0', 0, + /* 120 */ 'x', 'm', 'm', '0', 0, + /* 125 */ 'y', 'm', 'm', '0', 0, + /* 130 */ 'z', 'm', 'm', '0', 0, + /* 135 */ 'f', 'p', '0', 0, + /* 139 */ 'c', 'r', '0', 0, + /* 143 */ 'd', 'r', '0', 0, + /* 147 */ 'x', 'm', 'm', '1', '1', 0, + /* 153 */ 'y', 'm', 'm', '1', '1', 0, + /* 159 */ 'z', 'm', 'm', '1', '1', 0, + /* 165 */ 'c', 'r', '1', '1', 0, + /* 170 */ 'd', 'r', '1', '1', 0, + /* 175 */ 'x', 'm', 'm', '2', '1', 0, + /* 181 */ 'y', 'm', 'm', '2', '1', 0, + /* 187 */ 'z', 'm', 'm', '2', '1', 0, + /* 193 */ 'x', 'm', 'm', '3', '1', 0, + /* 199 */ 'y', 'm', 'm', '3', '1', 0, + /* 205 */ 'z', 'm', 'm', '3', '1', 0, + /* 211 */ 'b', 'n', 'd', '1', 0, + /* 216 */ 'k', '1', 0, + /* 219 */ 'x', 'm', 'm', '1', 0, + /* 224 */ 'y', 'm', 'm', '1', 0, + /* 229 */ 'z', 'm', 'm', '1', 0, + /* 234 */ 'f', 'p', '1', 0, + /* 238 */ 'c', 'r', '1', 0, + /* 242 */ 'd', 'r', '1', 0, + /* 246 */ 'x', 'm', 'm', '1', '2', 0, + /* 252 */ 'y', 'm', 'm', '1', '2', 0, + /* 258 */ 'z', 'm', 'm', '1', '2', 0, + /* 264 */ 'c', 'r', '1', '2', 0, + /* 269 */ 'd', 'r', '1', '2', 0, + /* 274 */ 'x', 'm', 'm', '2', '2', 0, + /* 280 */ 'y', 'm', 'm', '2', '2', 0, + /* 286 */ 'z', 'm', 'm', '2', '2', 0, + /* 292 */ 'b', 'n', 'd', '2', 0, + /* 297 */ 'k', '2', 0, + /* 300 */ 'x', 'm', 'm', '2', 0, + /* 305 */ 'y', 'm', 'm', '2', 0, + /* 310 */ 'z', 'm', 'm', '2', 0, + /* 315 */ 'f', 'p', '2', 0, + /* 319 */ 'c', 'r', '2', 0, + /* 323 */ 'd', 'r', '2', 0, + /* 327 */ 'x', 'm', 'm', '1', '3', 0, + /* 333 */ 'y', 'm', 'm', '1', '3', 0, + /* 339 */ 'z', 'm', 'm', '1', '3', 0, + /* 345 */ 'c', 'r', '1', '3', 0, + /* 350 */ 'd', 'r', '1', '3', 0, + /* 355 */ 'x', 'm', 'm', '2', '3', 0, + /* 361 */ 'y', 'm', 'm', '2', '3', 0, + /* 367 */ 'z', 'm', 'm', '2', '3', 0, + /* 373 */ 'b', 'n', 'd', '3', 0, + /* 378 */ 'k', '3', 0, + /* 381 */ 'x', 'm', 'm', '3', 0, + /* 386 */ 'y', 'm', 'm', '3', 0, + /* 391 */ 'z', 'm', 'm', '3', 0, + /* 396 */ 'f', 'p', '3', 0, + /* 400 */ 'c', 'r', '3', 0, + /* 404 */ 'd', 'r', '3', 0, + /* 408 */ 'x', 'm', 'm', '1', '4', 0, + /* 414 */ 'y', 'm', 'm', '1', '4', 0, + /* 420 */ 'z', 'm', 'm', '1', '4', 0, + /* 426 */ 'c', 'r', '1', '4', 0, + /* 431 */ 'd', 'r', '1', '4', 0, + /* 436 */ 'x', 'm', 'm', '2', '4', 0, + /* 442 */ 'y', 'm', 'm', '2', '4', 0, + /* 448 */ 'z', 'm', 'm', '2', '4', 0, + /* 454 */ 'k', '4', 0, + /* 457 */ 'x', 'm', 'm', '4', 0, + /* 462 */ 'y', 'm', 'm', '4', 0, + /* 467 */ 'z', 'm', 'm', '4', 0, + /* 472 */ 'f', 'p', '4', 0, + /* 476 */ 'c', 'r', '4', 0, + /* 480 */ 'd', 'r', '4', 0, + /* 484 */ 'x', 'm', 'm', '1', '5', 0, + /* 490 */ 'y', 'm', 'm', '1', '5', 0, + /* 496 */ 'z', 'm', 'm', '1', '5', 0, + /* 502 */ 'c', 'r', '1', '5', 0, + /* 507 */ 'd', 'r', '1', '5', 0, + /* 512 */ 'x', 'm', 'm', '2', '5', 0, + /* 518 */ 'y', 'm', 'm', '2', '5', 0, + /* 524 */ 'z', 'm', 'm', '2', '5', 0, + /* 530 */ 'k', '5', 0, + /* 533 */ 'x', 'm', 'm', '5', 0, + /* 538 */ 'y', 'm', 'm', '5', 0, + /* 543 */ 'z', 'm', 'm', '5', 0, + /* 548 */ 'f', 'p', '5', 0, + /* 552 */ 'c', 'r', '5', 0, + /* 556 */ 'd', 'r', '5', 0, + /* 560 */ 'x', 'm', 'm', '1', '6', 0, + /* 566 */ 'y', 'm', 'm', '1', '6', 0, + /* 572 */ 'z', 'm', 'm', '1', '6', 0, + /* 578 */ 'x', 'm', 'm', '2', '6', 0, + /* 584 */ 'y', 'm', 'm', '2', '6', 0, + /* 590 */ 'z', 'm', 'm', '2', '6', 0, + /* 596 */ 'k', '6', 0, + /* 599 */ 'x', 'm', 'm', '6', 0, + /* 604 */ 'y', 'm', 'm', '6', 0, + /* 609 */ 'z', 'm', 'm', '6', 0, + /* 614 */ 'f', 'p', '6', 0, + /* 618 */ 'c', 'r', '6', 0, + /* 622 */ 'd', 'r', '6', 0, + /* 626 */ 'x', 'm', 'm', '1', '7', 0, + /* 632 */ 'y', 'm', 'm', '1', '7', 0, + /* 638 */ 'z', 'm', 'm', '1', '7', 0, + /* 644 */ 'x', 'm', 'm', '2', '7', 0, + /* 650 */ 'y', 'm', 'm', '2', '7', 0, + /* 656 */ 'z', 'm', 'm', '2', '7', 0, + /* 662 */ 'k', '7', 0, + /* 665 */ 'x', 'm', 'm', '7', 0, + /* 670 */ 'y', 'm', 'm', '7', 0, + /* 675 */ 'z', 'm', 'm', '7', 0, + /* 680 */ 'f', 'p', '7', 0, + /* 684 */ 'c', 'r', '7', 0, + /* 688 */ 'd', 'r', '7', 0, + /* 692 */ 'x', 'm', 'm', '1', '8', 0, + /* 698 */ 'y', 'm', 'm', '1', '8', 0, + /* 704 */ 'z', 'm', 'm', '1', '8', 0, + /* 710 */ 'x', 'm', 'm', '2', '8', 0, + /* 716 */ 'y', 'm', 'm', '2', '8', 0, + /* 722 */ 'z', 'm', 'm', '2', '8', 0, + /* 728 */ 'x', 'm', 'm', '8', 0, + /* 733 */ 'y', 'm', 'm', '8', 0, + /* 738 */ 'z', 'm', 'm', '8', 0, + /* 743 */ 'c', 'r', '8', 0, + /* 747 */ 'd', 'r', '8', 0, + /* 751 */ 'x', 'm', 'm', '1', '9', 0, + /* 757 */ 'y', 'm', 'm', '1', '9', 0, + /* 763 */ 'z', 'm', 'm', '1', '9', 0, + /* 769 */ 'x', 'm', 'm', '2', '9', 0, + /* 775 */ 'y', 'm', 'm', '2', '9', 0, + /* 781 */ 'z', 'm', 'm', '2', '9', 0, + /* 787 */ 'x', 'm', 'm', '9', 0, + /* 792 */ 'y', 'm', 'm', '9', 0, + /* 797 */ 'z', 'm', 'm', '9', 0, + /* 802 */ 'c', 'r', '9', 0, + /* 806 */ 'd', 'r', '9', 0, + /* 810 */ 'R', '1', '0', 'B', 'H', 0, + /* 816 */ 'R', '1', '1', 'B', 'H', 0, + /* 822 */ 'R', '1', '2', 'B', 'H', 0, + /* 828 */ 'R', '1', '3', 'B', 'H', 0, + /* 834 */ 'R', '1', '4', 'B', 'H', 0, + /* 840 */ 'R', '1', '5', 'B', 'H', 0, + /* 846 */ 'R', '8', 'B', 'H', 0, + /* 851 */ 'R', '9', 'B', 'H', 0, + /* 856 */ 'D', 'I', 'H', 0, + /* 860 */ 'S', 'I', 'H', 0, + /* 864 */ 'B', 'P', 'H', 0, + /* 868 */ 'S', 'P', 'H', 0, + /* 872 */ 'R', '1', '0', 'W', 'H', 0, + /* 878 */ 'R', '1', '1', 'W', 'H', 0, + /* 884 */ 'R', '1', '2', 'W', 'H', 0, + /* 890 */ 'R', '1', '3', 'W', 'H', 0, + /* 896 */ 'R', '1', '4', 'W', 'H', 0, + /* 902 */ 'R', '1', '5', 'W', 'H', 0, + /* 908 */ 'R', '8', 'W', 'H', 0, + /* 913 */ 'R', '9', 'W', 'H', 0, + /* 918 */ 'H', 'D', 'I', 0, + /* 922 */ 'H', 'S', 'I', 0, + /* 926 */ 'H', 'B', 'P', 0, + /* 930 */ 'H', 'I', 'P', 0, + /* 934 */ 'H', 'S', 'P', 0, + /* 938 */ 'H', 'A', 'X', 0, + /* 942 */ 'H', 'B', 'X', 0, + /* 946 */ 'H', 'C', 'X', 0, + /* 950 */ 'H', 'D', 'X', 0, + /* 954 */ 'r', '1', '0', 'b', 0, + /* 959 */ 'r', '1', '1', 'b', 0, + /* 964 */ 'r', '1', '2', 'b', 0, + /* 969 */ 'r', '1', '3', 'b', 0, + /* 974 */ 'r', '1', '4', 'b', 0, + /* 979 */ 'r', '1', '5', 'b', 0, + /* 984 */ 'r', '8', 'b', 0, + /* 988 */ 'r', '9', 'b', 0, + /* 992 */ 'r', '1', '0', 'd', 0, + /* 997 */ 'r', '1', '1', 'd', 0, + /* 1002 */ 'r', '1', '2', 'd', 0, + /* 1007 */ 'r', '1', '3', 'd', 0, + /* 1012 */ 'r', '1', '4', 'd', 0, + /* 1017 */ 'r', '1', '5', 'd', 0, + /* 1022 */ 'r', '8', 'd', 0, + /* 1026 */ 'r', '9', 'd', 0, + /* 1030 */ 'd', 'i', 'r', 'f', 'l', 'a', 'g', 0, + /* 1038 */ 'a', 'h', 0, + /* 1041 */ 'b', 'h', 0, + /* 1044 */ 'c', 'h', 0, + /* 1047 */ 'd', 'h', 0, + /* 1050 */ 'e', 'd', 'i', 0, + /* 1054 */ 'r', 'd', 'i', 0, + /* 1058 */ 'e', 's', 'i', 0, + /* 1062 */ 'r', 's', 'i', 0, + /* 1066 */ 'a', 'l', 0, + /* 1069 */ 'b', 'l', 0, + /* 1072 */ 'c', 'l', 0, + /* 1075 */ 'd', 'l', 0, + /* 1078 */ 'd', 'i', 'l', 0, + /* 1082 */ 's', 'i', 'l', 0, + /* 1086 */ 'b', 'p', 'l', 0, + /* 1090 */ 's', 'p', 'l', 0, + /* 1094 */ 'e', 'b', 'p', 0, + /* 1098 */ 'r', 'b', 'p', 0, + /* 1102 */ 'e', 'i', 'p', 0, + /* 1106 */ 'r', 'i', 'p', 0, + /* 1110 */ 'e', 's', 'p', 0, + /* 1114 */ 'r', 's', 'p', 0, + /* 1118 */ 's', 's', 'p', 0, + /* 1122 */ 'c', 's', 0, + /* 1125 */ 'd', 's', 0, + /* 1128 */ 'e', 's', 0, + /* 1131 */ 'f', 's', 0, + /* 1134 */ 'f', 'l', 'a', 'g', 's', 0, + /* 1140 */ 's', 's', 0, + /* 1143 */ 'r', '1', '0', 'w', 0, + /* 1148 */ 'r', '1', '1', 'w', 0, + /* 1153 */ 'r', '1', '2', 'w', 0, + /* 1158 */ 'r', '1', '3', 'w', 0, + /* 1163 */ 'r', '1', '4', 'w', 0, + /* 1168 */ 'r', '1', '5', 'w', 0, + /* 1173 */ 'r', '8', 'w', 0, + /* 1177 */ 'r', '9', 'w', 0, + /* 1181 */ 'f', 'p', 's', 'w', 0, + /* 1186 */ 'e', 'a', 'x', 0, + /* 1190 */ 'r', 'a', 'x', 0, + /* 1194 */ 'e', 'b', 'x', 0, + /* 1198 */ 'r', 'b', 'x', 0, + /* 1202 */ 'e', 'c', 'x', 0, + /* 1206 */ 'r', 'c', 'x', 0, + /* 1210 */ 'e', 'd', 'x', 0, + /* 1214 */ 'r', 'd', 'x', 0, + /* 1218 */ 'e', 'i', 'z', 0, + /* 1222 */ 'r', 'i', 'z', 0, + }; + + static const uint16_t RegAsmOffset[] = { + 1038, 1066, 1187, 1041, 1069, 1095, 864, 1086, 1195, 1044, 1072, 1122, 1203, 1030, + 1047, 1051, 856, 1078, 1075, 1125, 1211, 1186, 1094, 1194, 1202, 1050, 1210, 1134, + 1102, 1218, 1128, 1058, 1110, 1181, 1131, 1137, 938, 926, 942, 946, 918, 950, + 930, 922, 934, 1103, 1190, 1098, 1198, 1206, 1054, 1214, 1106, 1222, 1062, 1114, + 1059, 860, 1082, 1111, 868, 1090, 1140, 1118, 112, 211, 292, 373, 139, 238, + 319, 400, 476, 552, 618, 684, 743, 802, 66, 165, 264, 345, 426, 502, + 143, 242, 323, 404, 480, 556, 622, 688, 747, 806, 71, 170, 269, 350, + 431, 507, 135, 234, 315, 396, 472, 548, 614, 680, 117, 216, 297, 378, + 454, 530, 596, 662, 121, 220, 301, 382, 458, 534, 600, 666, 744, 803, + 67, 166, 265, 346, 427, 503, 0, 6, 12, 18, 24, 30, 36, 42, + 120, 219, 300, 381, 457, 533, 599, 665, 728, 787, 48, 147, 246, 327, + 408, 484, 560, 626, 692, 751, 76, 175, 274, 355, 436, 512, 578, 644, + 710, 769, 94, 193, 125, 224, 305, 386, 462, 538, 604, 670, 733, 792, + 54, 153, 252, 333, 414, 490, 566, 632, 698, 757, 82, 181, 280, 361, + 442, 518, 584, 650, 716, 775, 100, 199, 130, 229, 310, 391, 467, 543, + 609, 675, 738, 797, 60, 159, 258, 339, 420, 496, 572, 638, 704, 763, + 88, 187, 286, 367, 448, 524, 590, 656, 722, 781, 106, 205, 984, 988, + 954, 959, 964, 969, 974, 979, 846, 851, 810, 816, 822, 828, 834, 840, + 1022, 1026, 992, 997, 1002, 1007, 1012, 1017, 1173, 1177, 1143, 1148, 1153, 1158, + 1163, 1168, 908, 913, 872, 878, 884, 890, 896, 902, + }; + + return AsmStrs+RegAsmOffset[RegNo-1]; +#else + return NULL; +#endif +} diff --git a/thirdparty/capstone/arch/X86/X86ImmSize.inc b/thirdparty/capstone/arch/X86/X86ImmSize.inc new file mode 100644 index 0000000..db8927d --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86ImmSize.inc @@ -0,0 +1,335 @@ +{1, 1, X86_AAD8i8}, +{1, 1, X86_AAM8i8}, +{2, 2, X86_ADC16i16}, +{2, 2, X86_ADC16mi}, +{1, 2, X86_ADC16mi8}, +{2, 2, X86_ADC16ri}, +{1, 2, X86_ADC16ri8}, +{4, 4, X86_ADC32i32}, +{4, 4, X86_ADC32mi}, +{1, 4, X86_ADC32mi8}, +{4, 4, X86_ADC32ri}, +{1, 4, X86_ADC32ri8}, +{4, 8, X86_ADC64i32}, +{4, 8, X86_ADC64mi32}, +{1, 8, X86_ADC64mi8}, +{4, 8, X86_ADC64ri32}, +{1, 8, X86_ADC64ri8}, +{1, 1, X86_ADC8i8}, +{1, 1, X86_ADC8mi}, +{1, 1, X86_ADC8mi8}, +{1, 1, X86_ADC8ri}, +{1, 1, X86_ADC8ri8}, +{2, 2, X86_ADD16i16}, +{2, 2, X86_ADD16mi}, +{1, 2, X86_ADD16mi8}, +{2, 2, X86_ADD16ri}, +{1, 2, X86_ADD16ri8}, +{4, 4, X86_ADD32i32}, +{4, 4, X86_ADD32mi}, +{1, 4, X86_ADD32mi8}, +{4, 4, X86_ADD32ri}, +{1, 4, X86_ADD32ri8}, +{4, 8, X86_ADD64i32}, +{4, 8, X86_ADD64mi32}, +{1, 8, X86_ADD64mi8}, +{4, 8, X86_ADD64ri32}, +{1, 8, X86_ADD64ri8}, +{1, 1, X86_ADD8i8}, +{1, 1, X86_ADD8mi}, +{1, 1, X86_ADD8mi8}, +{1, 1, X86_ADD8ri}, +{1, 1, X86_ADD8ri8}, +{2, 2, X86_AND16i16}, +{2, 2, X86_AND16mi}, +{1, 2, X86_AND16mi8}, +{2, 2, X86_AND16ri}, +{1, 2, X86_AND16ri8}, +{4, 4, X86_AND32i32}, +{4, 4, X86_AND32mi}, +{1, 4, X86_AND32mi8}, +{4, 4, X86_AND32ri}, +{1, 4, X86_AND32ri8}, +{4, 8, X86_AND64i32}, +{4, 8, X86_AND64mi32}, +{1, 8, X86_AND64mi8}, +{4, 8, X86_AND64ri32}, +{1, 8, X86_AND64ri8}, +{1, 1, X86_AND8i8}, +{1, 1, X86_AND8mi}, +{1, 1, X86_AND8mi8}, +{1, 1, X86_AND8ri}, +{1, 1, X86_AND8ri8}, +{1, 1, X86_BT16mi8}, +{1, 1, X86_BT16ri8}, +{1, 1, X86_BT32mi8}, +{1, 1, X86_BT32ri8}, +{1, 1, X86_BT64mi8}, +{1, 1, X86_BT64ri8}, +{1, 1, X86_BTC16mi8}, +{1, 1, X86_BTC16ri8}, +{1, 1, X86_BTC32mi8}, +{1, 1, X86_BTC32ri8}, +{1, 1, X86_BTC64mi8}, +{1, 1, X86_BTC64ri8}, +{1, 1, X86_BTR16mi8}, +{1, 1, X86_BTR16ri8}, +{1, 1, X86_BTR32mi8}, +{1, 1, X86_BTR32ri8}, +{1, 1, X86_BTR64mi8}, +{1, 1, X86_BTR64ri8}, +{1, 1, X86_BTS16mi8}, +{1, 1, X86_BTS16ri8}, +{1, 1, X86_BTS32mi8}, +{1, 1, X86_BTS32ri8}, +{1, 1, X86_BTS64mi8}, +{1, 1, X86_BTS64ri8}, +{2, 2, X86_CALLpcrel16}, +{2, 4, X86_CALLpcrel32}, +{2, 2, X86_CMP16i16}, +{2, 2, X86_CMP16mi}, +{1, 2, X86_CMP16mi8}, +{2, 2, X86_CMP16ri}, +{1, 2, X86_CMP16ri8}, +{4, 4, X86_CMP32i32}, +{4, 4, X86_CMP32mi}, +{1, 4, X86_CMP32mi8}, +{4, 4, X86_CMP32ri}, +{1, 4, X86_CMP32ri8}, +{4, 8, X86_CMP64i32}, +{4, 8, X86_CMP64mi32}, +{1, 8, X86_CMP64mi8}, +{4, 8, X86_CMP64ri32}, +{1, 8, X86_CMP64ri8}, +{1, 1, X86_CMP8i8}, +{1, 1, X86_CMP8mi}, +{1, 1, X86_CMP8mi8}, +{1, 1, X86_CMP8ri}, +{1, 1, X86_CMP8ri8}, +{1, 2, X86_IMUL16rmi8}, +{1, 2, X86_IMUL16rri8}, +{1, 4, X86_IMUL32rmi8}, +{1, 4, X86_IMUL32rri8}, +{4, 8, X86_IMUL64rmi32}, +{1, 8, X86_IMUL64rmi8}, +{4, 8, X86_IMUL64rri32}, +{1, 8, X86_IMUL64rri8}, +{2, 2, X86_IN16ri}, +{4, 4, X86_IN32ri}, +{1, 1, X86_IN8ri}, +{2, 2, X86_JMP_2}, +{2, 2, X86_MOV16mi}, +{2, 2, X86_MOV16ri}, +{2, 2, X86_MOV16ri_alt}, +{4, 4, X86_MOV32mi}, +{4, 4, X86_MOV32ri}, +{4, 4, X86_MOV32ri_alt}, +{4, 8, X86_MOV64mi32}, +{8, 8, X86_MOV64ri}, +{4, 8, X86_MOV64ri32}, +{1, 1, X86_MOV8mi}, +{1, 1, X86_MOV8ri}, +{1, 1, X86_MOV8ri_alt}, +{2, 2, X86_OR16i16}, +{2, 2, X86_OR16mi}, +{1, 2, X86_OR16mi8}, +{2, 2, X86_OR16ri}, +{1, 2, X86_OR16ri8}, +{4, 4, X86_OR32i32}, +{4, 4, X86_OR32mi}, +{1, 4, X86_OR32mi8}, +{4, 4, X86_OR32ri}, +{1, 4, X86_OR32ri8}, +{4, 8, X86_OR64i32}, +{4, 8, X86_OR64mi32}, +{1, 8, X86_OR64mi8}, +{4, 8, X86_OR64ri32}, +{1, 8, X86_OR64ri8}, +{1, 1, X86_OR8i8}, +{1, 1, X86_OR8mi}, +{1, 1, X86_OR8mi8}, +{1, 1, X86_OR8ri}, +{1, 1, X86_OR8ri8}, +{1, 2, X86_PUSH16i8}, +{1, 4, X86_PUSH32i8}, +{4, 8, X86_PUSH64i32}, +{1, 8, X86_PUSH64i8}, +{2, 2, X86_PUSHi16}, +{4, 4, X86_PUSHi32}, +{1, 1, X86_RCL16mi}, +{1, 1, X86_RCL16ri}, +{1, 1, X86_RCL32mi}, +{1, 1, X86_RCL32ri}, +{1, 1, X86_RCL64mi}, +{1, 1, X86_RCL64ri}, +{1, 1, X86_RCL8mi}, +{1, 1, X86_RCL8ri}, +{1, 1, X86_RCR16mi}, +{1, 1, X86_RCR16ri}, +{1, 1, X86_RCR32mi}, +{1, 1, X86_RCR32ri}, +{1, 1, X86_RCR64mi}, +{1, 1, X86_RCR64ri}, +{1, 1, X86_RCR8mi}, +{1, 1, X86_RCR8ri}, +//{4, 4, X86_RELEASE_ADD32mi}, +//{4, 8, X86_RELEASE_ADD64mi32}, +//{1, 1, X86_RELEASE_ADD8mi}, +//{4, 4, X86_RELEASE_AND32mi}, +//{4, 8, X86_RELEASE_AND64mi32}, +//{1, 1, X86_RELEASE_AND8mi}, +//{2, 2, X86_RELEASE_MOV16mi}, +//{4, 4, X86_RELEASE_MOV32mi}, +//{4, 8, X86_RELEASE_MOV64mi32}, +//{1, 1, X86_RELEASE_MOV8mi}, +//{4, 4, X86_RELEASE_OR32mi}, +//{4, 8, X86_RELEASE_OR64mi32}, +//{1, 1, X86_RELEASE_OR8mi}, +//{4, 4, X86_RELEASE_XOR32mi}, +//{4, 8, X86_RELEASE_XOR64mi32}, +//{1, 1, X86_RELEASE_XOR8mi}, +{1, 1, X86_ROL16mi}, +{1, 1, X86_ROL16ri}, +{1, 1, X86_ROL32mi}, +{1, 1, X86_ROL32ri}, +{1, 1, X86_ROL64mi}, +{1, 1, X86_ROL64ri}, +{1, 1, X86_ROL8mi}, +{1, 1, X86_ROL8ri}, +{1, 1, X86_ROR16mi}, +{1, 1, X86_ROR16ri}, +{1, 1, X86_ROR32mi}, +{1, 1, X86_ROR32ri}, +{1, 1, X86_ROR64mi}, +{1, 1, X86_ROR64ri}, +{1, 1, X86_ROR8mi}, +{1, 1, X86_ROR8ri}, +{4, 4, X86_RORX32mi}, +{4, 4, X86_RORX32ri}, +{8, 8, X86_RORX64mi}, +{8, 8, X86_RORX64ri}, +{1, 1, X86_SAL16mi}, +{1, 1, X86_SAL16ri}, +{1, 1, X86_SAL32mi}, +{1, 1, X86_SAL32ri}, +{1, 1, X86_SAL64mi}, +{1, 1, X86_SAL64ri}, +{1, 1, X86_SAL8mi}, +{1, 1, X86_SAL8ri}, +{1, 1, X86_SAR16mi}, +{1, 1, X86_SAR16ri}, +{1, 1, X86_SAR32mi}, +{1, 1, X86_SAR32ri}, +{1, 1, X86_SAR64mi}, +{1, 1, X86_SAR64ri}, +{1, 1, X86_SAR8mi}, +{1, 1, X86_SAR8ri}, +{2, 2, X86_SBB16i16}, +{2, 2, X86_SBB16mi}, +{1, 2, X86_SBB16mi8}, +{2, 2, X86_SBB16ri}, +{1, 2, X86_SBB16ri8}, +{4, 4, X86_SBB32i32}, +{4, 4, X86_SBB32mi}, +{1, 4, X86_SBB32mi8}, +{4, 4, X86_SBB32ri}, +{1, 4, X86_SBB32ri8}, +{4, 8, X86_SBB64i32}, +{4, 8, X86_SBB64mi32}, +{1, 8, X86_SBB64mi8}, +{4, 8, X86_SBB64ri32}, +{1, 8, X86_SBB64ri8}, +{1, 1, X86_SBB8i8}, +{1, 1, X86_SBB8mi}, +{1, 1, X86_SBB8mi8}, +{1, 1, X86_SBB8ri}, +{1, 1, X86_SBB8ri8}, +{1, 1, X86_SHL16mi}, +{1, 1, X86_SHL16ri}, +{1, 1, X86_SHL32mi}, +{1, 1, X86_SHL32ri}, +{1, 1, X86_SHL64mi}, +{1, 1, X86_SHL64ri}, +{1, 1, X86_SHL8mi}, +{1, 1, X86_SHL8ri}, +{1, 1, X86_SHLD16mri8}, +{1, 1, X86_SHLD16rri8}, +{1, 1, X86_SHLD32mri8}, +{1, 1, X86_SHLD32rri8}, +{1, 1, X86_SHLD64mri8}, +{1, 1, X86_SHLD64rri8}, +{1, 1, X86_SHR16mi}, +{1, 1, X86_SHR16ri}, +{1, 1, X86_SHR32mi}, +{1, 1, X86_SHR32ri}, +{1, 1, X86_SHR64mi}, +{1, 1, X86_SHR64ri}, +{1, 1, X86_SHR8mi}, +{1, 1, X86_SHR8ri}, +{1, 1, X86_SHRD16mri8}, +{1, 1, X86_SHRD16rri8}, +{1, 1, X86_SHRD32mri8}, +{1, 1, X86_SHRD32rri8}, +{1, 1, X86_SHRD64mri8}, +{1, 1, X86_SHRD64rri8}, +{2, 2, X86_SUB16i16}, +{2, 2, X86_SUB16mi}, +{1, 2, X86_SUB16mi8}, +{2, 2, X86_SUB16ri}, +{1, 2, X86_SUB16ri8}, +{4, 4, X86_SUB32i32}, +{4, 4, X86_SUB32mi}, +{1, 4, X86_SUB32mi8}, +{4, 4, X86_SUB32ri}, +{1, 4, X86_SUB32ri8}, +{4, 8, X86_SUB64i32}, +{4, 8, X86_SUB64mi32}, +{1, 8, X86_SUB64mi8}, +{4, 8, X86_SUB64ri32}, +{1, 8, X86_SUB64ri8}, +{1, 1, X86_SUB8i8}, +{1, 1, X86_SUB8mi}, +{1, 1, X86_SUB8mi8}, +{1, 1, X86_SUB8ri}, +{1, 1, X86_SUB8ri8}, +{2, 2, X86_TEST16i16}, +{2, 2, X86_TEST16mi}, +// {2, 2, X86_TEST16mi_alt}, +{2, 2, X86_TEST16ri}, +//{2, 2, X86_TEST16ri_alt}, +{4, 4, X86_TEST32i32}, +{4, 4, X86_TEST32mi}, +//{4, 4, X86_TEST32mi_alt}, +{4, 4, X86_TEST32ri}, +//{4, 4, X86_TEST32ri_alt}, +{4, 8, X86_TEST64i32}, +{4, 8, X86_TEST64mi32}, +//{4, 4, X86_TEST64mi32_alt}, +{4, 8, X86_TEST64ri32}, +//{4, 4, X86_TEST64ri32_alt}, +{1, 1, X86_TEST8i8}, +{1, 1, X86_TEST8mi}, +//{1, 1, X86_TEST8mi_alt}, +{1, 1, X86_TEST8ri}, +//{1, 1, X86_TEST8ri_NOREX}, +//{1, 1, X86_TEST8ri_alt}, +{2, 2, X86_XOR16i16}, +{2, 2, X86_XOR16mi}, +{1, 2, X86_XOR16mi8}, +{2, 2, X86_XOR16ri}, +{1, 2, X86_XOR16ri8}, +{4, 4, X86_XOR32i32}, +{4, 4, X86_XOR32mi}, +{1, 4, X86_XOR32mi8}, +{4, 4, X86_XOR32ri}, +{1, 4, X86_XOR32ri8}, +{4, 8, X86_XOR64i32}, +{4, 8, X86_XOR64mi32}, +{1, 8, X86_XOR64mi8}, +{4, 8, X86_XOR64ri32}, +{1, 8, X86_XOR64ri8}, +{1, 1, X86_XOR8i8}, +{1, 1, X86_XOR8mi}, +{1, 1, X86_XOR8mi8}, +{1, 1, X86_XOR8ri}, +{1, 1, X86_XOR8ri8}, diff --git a/thirdparty/capstone/arch/X86/X86InstPrinter.h b/thirdparty/capstone/arch/X86/X86InstPrinter.h new file mode 100644 index 0000000..a2f2860 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86InstPrinter.h @@ -0,0 +1,26 @@ +//= X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -*- C++ -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an X86 MCInst to Intel style .s file syntax. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +#ifndef CS_X86_INSTPRINTER_H +#define CS_X86_INSTPRINTER_H + +#include "../../MCInst.h" +#include "../../SStream.h" + +void X86_Intel_printInst(MCInst *MI, SStream *OS, void *Info); +void X86_ATT_printInst(MCInst *MI, SStream *OS, void *Info); + +#endif diff --git a/thirdparty/capstone/arch/X86/X86InstPrinterCommon.c b/thirdparty/capstone/arch/X86/X86InstPrinterCommon.c new file mode 100644 index 0000000..d8401c9 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86InstPrinterCommon.c @@ -0,0 +1,116 @@ +//===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file includes common code for rendering MCInst instances as Intel-style +// and Intel-style assembly. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +#ifdef _MSC_VER +#pragma warning(disable:4996) // disable MSVC's warning on strncpy() +#pragma warning(disable:28719) // disable MSVC's warning on strncpy() +#endif + +#if !defined(CAPSTONE_HAS_OSXKERNEL) +#include +#endif +#include + +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#include +#else +#include +#include +#endif + +#include + +#include "../../utils.h" +#include "../../MCInst.h" +#include "../../SStream.h" + +#include "X86InstPrinterCommon.h" +#include "X86Mapping.h" + +#ifndef CAPSTONE_X86_REDUCE +void printSSEAVXCC(MCInst *MI, unsigned Op, SStream *O) +{ + uint8_t Imm = (uint8_t)(MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f); + switch (Imm) { + default: break;//printf("Invalid avxcc argument!\n"); break; + case 0: SStream_concat0(O, "eq"); op_addAvxCC(MI, X86_AVX_CC_EQ); break; + case 1: SStream_concat0(O, "lt"); op_addAvxCC(MI, X86_AVX_CC_LT); break; + case 2: SStream_concat0(O, "le"); op_addAvxCC(MI, X86_AVX_CC_LE); break; + case 3: SStream_concat0(O, "unord"); op_addAvxCC(MI, X86_AVX_CC_UNORD); break; + case 4: SStream_concat0(O, "neq"); op_addAvxCC(MI, X86_AVX_CC_NEQ); break; + case 5: SStream_concat0(O, "nlt"); op_addAvxCC(MI, X86_AVX_CC_NLT); break; + case 6: SStream_concat0(O, "nle"); op_addAvxCC(MI, X86_AVX_CC_NLE); break; + case 7: SStream_concat0(O, "ord"); op_addAvxCC(MI, X86_AVX_CC_ORD); break; + case 8: SStream_concat0(O, "eq_uq"); op_addAvxCC(MI, X86_AVX_CC_EQ_UQ); break; + case 9: SStream_concat0(O, "nge"); op_addAvxCC(MI, X86_AVX_CC_NGE); break; + case 0xa: SStream_concat0(O, "ngt"); op_addAvxCC(MI, X86_AVX_CC_NGT); break; + case 0xb: SStream_concat0(O, "false"); op_addAvxCC(MI, X86_AVX_CC_FALSE); break; + case 0xc: SStream_concat0(O, "neq_oq"); op_addAvxCC(MI, X86_AVX_CC_NEQ_OQ); break; + case 0xd: SStream_concat0(O, "ge"); op_addAvxCC(MI, X86_AVX_CC_GE); break; + case 0xe: SStream_concat0(O, "gt"); op_addAvxCC(MI, X86_AVX_CC_GT); break; + case 0xf: SStream_concat0(O, "true"); op_addAvxCC(MI, X86_AVX_CC_TRUE); break; + case 0x10: SStream_concat0(O, "eq_os"); op_addAvxCC(MI, X86_AVX_CC_EQ_OS); break; + case 0x11: SStream_concat0(O, "lt_oq"); op_addAvxCC(MI, X86_AVX_CC_LT_OQ); break; + case 0x12: SStream_concat0(O, "le_oq"); op_addAvxCC(MI, X86_AVX_CC_LE_OQ); break; + case 0x13: SStream_concat0(O, "unord_s"); op_addAvxCC(MI, X86_AVX_CC_UNORD_S); break; + case 0x14: SStream_concat0(O, "neq_us"); op_addAvxCC(MI, X86_AVX_CC_NEQ_US); break; + case 0x15: SStream_concat0(O, "nlt_uq"); op_addAvxCC(MI, X86_AVX_CC_NLT_UQ); break; + case 0x16: SStream_concat0(O, "nle_uq"); op_addAvxCC(MI, X86_AVX_CC_NLE_UQ); break; + case 0x17: SStream_concat0(O, "ord_s"); op_addAvxCC(MI, X86_AVX_CC_ORD_S); break; + case 0x18: SStream_concat0(O, "eq_us"); op_addAvxCC(MI, X86_AVX_CC_EQ_US); break; + case 0x19: SStream_concat0(O, "nge_uq"); op_addAvxCC(MI, X86_AVX_CC_NGE_UQ); break; + case 0x1a: SStream_concat0(O, "ngt_uq"); op_addAvxCC(MI, X86_AVX_CC_NGT_UQ); break; + case 0x1b: SStream_concat0(O, "false_os"); op_addAvxCC(MI, X86_AVX_CC_FALSE_OS); break; + case 0x1c: SStream_concat0(O, "neq_os"); op_addAvxCC(MI, X86_AVX_CC_NEQ_OS); break; + case 0x1d: SStream_concat0(O, "ge_oq"); op_addAvxCC(MI, X86_AVX_CC_GE_OQ); break; + case 0x1e: SStream_concat0(O, "gt_oq"); op_addAvxCC(MI, X86_AVX_CC_GT_OQ); break; + case 0x1f: SStream_concat0(O, "true_us"); op_addAvxCC(MI, X86_AVX_CC_TRUE_US); break; + } + + MI->popcode_adjust = Imm + 1; +} + +void printXOPCC(MCInst *MI, unsigned Op, SStream *O) +{ + int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)); + + switch (Imm) { + default: // llvm_unreachable("Invalid xopcc argument!"); + case 0: SStream_concat0(O, "lt"); op_addXopCC(MI, X86_XOP_CC_LT); break; + case 1: SStream_concat0(O, "le"); op_addXopCC(MI, X86_XOP_CC_LE); break; + case 2: SStream_concat0(O, "gt"); op_addXopCC(MI, X86_XOP_CC_GT); break; + case 3: SStream_concat0(O, "ge"); op_addXopCC(MI, X86_XOP_CC_GE); break; + case 4: SStream_concat0(O, "eq"); op_addXopCC(MI, X86_XOP_CC_EQ); break; + case 5: SStream_concat0(O, "neq"); op_addXopCC(MI, X86_XOP_CC_NEQ); break; + case 6: SStream_concat0(O, "false"); op_addXopCC(MI, X86_XOP_CC_FALSE); break; + case 7: SStream_concat0(O, "true"); op_addXopCC(MI, X86_XOP_CC_TRUE); break; + } +} + +void printRoundingControl(MCInst *MI, unsigned Op, SStream *O) +{ + int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3; + switch (Imm) { + case 0: SStream_concat0(O, "{rn-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RN); break; + case 1: SStream_concat0(O, "{rd-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RD); break; + case 2: SStream_concat0(O, "{ru-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RU); break; + case 3: SStream_concat0(O, "{rz-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RZ); break; + default: break; // never reach + } +} +#endif diff --git a/thirdparty/capstone/arch/X86/X86InstPrinterCommon.h b/thirdparty/capstone/arch/X86/X86InstPrinterCommon.h new file mode 100644 index 0000000..29a9ec3 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86InstPrinterCommon.h @@ -0,0 +1,16 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +#ifndef CS_X86_INSTPRINTERCOMMON_H +#define CS_X86_INSTPRINTERCOMMON_H + +#include "../../MCInst.h" +#include "../../SStream.h" + +#define CS_X86_MAXIMUM_OPERAND_SIZE 6 + +void printSSEAVXCC(MCInst *MI, unsigned Op, SStream *O); +void printXOPCC(MCInst *MI, unsigned Op, SStream *O); +void printRoundingControl(MCInst *MI, unsigned Op, SStream *O); + +#endif diff --git a/thirdparty/capstone/arch/X86/X86IntelInstPrinter.c b/thirdparty/capstone/arch/X86/X86IntelInstPrinter.c new file mode 100644 index 0000000..7f83cdd --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86IntelInstPrinter.c @@ -0,0 +1,1066 @@ +//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file includes code for rendering MCInst instances as Intel-style +// assembly. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +#ifdef CAPSTONE_HAS_X86 + +#ifdef _MSC_VER +#pragma warning(disable:4996) // disable MSVC's warning on strncpy() +#pragma warning(disable:28719) // disable MSVC's warning on strncpy() +#endif + +#if !defined(CAPSTONE_HAS_OSXKERNEL) +#include +#endif +#include + +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#include +#else +#include +#include +#endif +#include + +#include "../../utils.h" +#include "../../MCInst.h" +#include "../../SStream.h" +#include "../../MCRegisterInfo.h" + +#include "X86InstPrinter.h" +#include "X86Mapping.h" +#include "X86InstPrinterCommon.h" + +#define GET_INSTRINFO_ENUM +#ifdef CAPSTONE_X86_REDUCE +#include "X86GenInstrInfo_reduce.inc" +#else +#include "X86GenInstrInfo.inc" +#endif + +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" + +#include "X86BaseInfo.h" + +static void printMemReference(MCInst *MI, unsigned Op, SStream *O); +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); + + +static void set_mem_access(MCInst *MI, bool status) +{ + if (MI->csh->detail_opt != CS_OPT_ON) + return; + + MI->csh->doing_mem = status; + if (!status) + // done, create the next operand slot + MI->flat_insn->detail->x86.op_count++; + +} + +static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) +{ + // FIXME: do this with autogen + // printf(">>> ID = %u\n", MI->flat_insn->id); + switch(MI->flat_insn->id) { + default: + SStream_concat0(O, "ptr "); + break; + case X86_INS_SGDT: + case X86_INS_SIDT: + case X86_INS_LGDT: + case X86_INS_LIDT: + case X86_INS_FXRSTOR: + case X86_INS_FXSAVE: + case X86_INS_LJMP: + case X86_INS_LCALL: + // do not print "ptr" + break; + } + + switch(MI->csh->mode) { + case CS_MODE_16: + switch(MI->flat_insn->id) { + default: + MI->x86opsize = 2; + break; + case X86_INS_LJMP: + case X86_INS_LCALL: + MI->x86opsize = 4; + break; + case X86_INS_SGDT: + case X86_INS_SIDT: + case X86_INS_LGDT: + case X86_INS_LIDT: + MI->x86opsize = 6; + break; + } + break; + case CS_MODE_32: + switch(MI->flat_insn->id) { + default: + MI->x86opsize = 4; + break; + case X86_INS_LJMP: + case X86_INS_JMP: + case X86_INS_LCALL: + case X86_INS_SGDT: + case X86_INS_SIDT: + case X86_INS_LGDT: + case X86_INS_LIDT: + MI->x86opsize = 6; + break; + } + break; + case CS_MODE_64: + switch(MI->flat_insn->id) { + default: + MI->x86opsize = 8; + break; + case X86_INS_LJMP: + case X86_INS_LCALL: + case X86_INS_SGDT: + case X86_INS_SIDT: + case X86_INS_LGDT: + case X86_INS_LIDT: + MI->x86opsize = 10; + break; + } + break; + default: // never reach + break; + } + + printMemReference(MI, OpNo, O); +} + +static void printi8mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "byte ptr "); + MI->x86opsize = 1; + printMemReference(MI, OpNo, O); +} + +static void printi16mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 2; + SStream_concat0(O, "word ptr "); + printMemReference(MI, OpNo, O); +} + +static void printi32mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + MI->x86opsize = 4; + SStream_concat0(O, "dword ptr "); + printMemReference(MI, OpNo, O); +} + +static void printi64mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "qword ptr "); + MI->x86opsize = 8; + printMemReference(MI, OpNo, O); +} + +static void printi128mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "xmmword ptr "); + MI->x86opsize = 16; + printMemReference(MI, OpNo, O); +} + +static void printi512mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "zmmword ptr "); + MI->x86opsize = 64; + printMemReference(MI, OpNo, O); +} + +#ifndef CAPSTONE_X86_REDUCE +static void printi256mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "ymmword ptr "); + MI->x86opsize = 32; + printMemReference(MI, OpNo, O); +} + +static void printf32mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + switch(MCInst_getOpcode(MI)) { + default: + SStream_concat0(O, "dword ptr "); + MI->x86opsize = 4; + break; + case X86_FSTENVm: + case X86_FLDENVm: + // TODO: fix this in tablegen instead + switch(MI->csh->mode) { + default: // never reach + break; + case CS_MODE_16: + MI->x86opsize = 14; + break; + case CS_MODE_32: + case CS_MODE_64: + MI->x86opsize = 28; + break; + } + break; + } + + printMemReference(MI, OpNo, O); +} + +static void printf64mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + // TODO: fix COMISD in Tablegen instead (#1456) + if (MI->op1_size == 16) { + // printf("printf64mem id = %u\n", MCInst_getOpcode(MI)); + switch(MCInst_getOpcode(MI)) { + default: + SStream_concat0(O, "qword ptr "); + MI->x86opsize = 8; + break; + case X86_MOVPQI2QImr: + case X86_COMISDrm: + SStream_concat0(O, "xmmword ptr "); + MI->x86opsize = 16; + break; + } + } else { + SStream_concat0(O, "qword ptr "); + MI->x86opsize = 8; + } + + printMemReference(MI, OpNo, O); +} + +static void printf80mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + switch(MCInst_getOpcode(MI)) { + default: + SStream_concat0(O, "xword ptr "); + break; + case X86_FBLDm: + case X86_FBSTPm: + break; + } + + MI->x86opsize = 10; + printMemReference(MI, OpNo, O); +} + +static void printf128mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "xmmword ptr "); + MI->x86opsize = 16; + printMemReference(MI, OpNo, O); +} + +static void printf256mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "ymmword ptr "); + MI->x86opsize = 32; + printMemReference(MI, OpNo, O); +} + +static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "zmmword ptr "); + MI->x86opsize = 64; + printMemReference(MI, OpNo, O); +} +#endif + +static const char *getRegisterName(unsigned RegNo); +static void printRegName(SStream *OS, unsigned RegNo) +{ + SStream_concat0(OS, getRegisterName(RegNo)); +} + +// for MASM syntax, 0x123 = 123h, 0xA123 = 0A123h +// this function tell us if we need to have prefix 0 in front of a number +static bool need_zero_prefix(uint64_t imm) +{ + // find the first hex letter representing imm + while(imm >= 0x10) + imm >>= 4; + + if (imm < 0xa) + return false; + else // this need 0 prefix + return true; +} + +static void printImm(MCInst *MI, SStream *O, int64_t imm, bool positive) +{ + if (positive) { + // always print this number in positive form + if (MI->csh->syntax == CS_OPT_SYNTAX_MASM) { + if (imm < 0) { + if (MI->op1_size) { + switch(MI->op1_size) { + default: + break; + case 1: + imm &= 0xff; + break; + case 2: + imm &= 0xffff; + break; + case 4: + imm &= 0xffffffff; + break; + } + } + + if (imm == 0x8000000000000000LL) // imm == -imm + SStream_concat0(O, "8000000000000000h"); + else if (need_zero_prefix(imm)) + SStream_concat(O, "0%"PRIx64"h", imm); + else + SStream_concat(O, "%"PRIx64"h", imm); + } else { + if (imm > HEX_THRESHOLD) { + if (need_zero_prefix(imm)) + SStream_concat(O, "0%"PRIx64"h", imm); + else + SStream_concat(O, "%"PRIx64"h", imm); + } else + SStream_concat(O, "%"PRIu64, imm); + } + } else { // Intel syntax + if (imm < 0) { + if (MI->op1_size) { + switch(MI->op1_size) { + default: + break; + case 1: + imm &= 0xff; + break; + case 2: + imm &= 0xffff; + break; + case 4: + imm &= 0xffffffff; + break; + } + } + + SStream_concat(O, "0x%"PRIx64, imm); + } else { + if (imm > HEX_THRESHOLD) + SStream_concat(O, "0x%"PRIx64, imm); + else + SStream_concat(O, "%"PRIu64, imm); + } + } + } else { + if (MI->csh->syntax == CS_OPT_SYNTAX_MASM) { + if (imm < 0) { + if (imm == 0x8000000000000000LL) // imm == -imm + SStream_concat0(O, "8000000000000000h"); + else if (imm < -HEX_THRESHOLD) { + if (need_zero_prefix(imm)) + SStream_concat(O, "-0%"PRIx64"h", -imm); + else + SStream_concat(O, "-%"PRIx64"h", -imm); + } else + SStream_concat(O, "-%"PRIu64, -imm); + } else { + if (imm > HEX_THRESHOLD) { + if (need_zero_prefix(imm)) + SStream_concat(O, "0%"PRIx64"h", imm); + else + SStream_concat(O, "%"PRIx64"h", imm); + } else + SStream_concat(O, "%"PRIu64, imm); + } + } else { // Intel syntax + if (imm < 0) { + if (imm == 0x8000000000000000LL) // imm == -imm + SStream_concat0(O, "0x8000000000000000"); + else if (imm < -HEX_THRESHOLD) + SStream_concat(O, "-0x%"PRIx64, -imm); + else + SStream_concat(O, "-%"PRIu64, -imm); + + } else { + if (imm > HEX_THRESHOLD) + SStream_concat(O, "0x%"PRIx64, imm); + else + SStream_concat(O, "%"PRIu64, imm); + } + } + } +} + +// local printOperand, without updating public operands +static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + if (MCOperand_isReg(Op)) { + printRegName(O, MCOperand_getReg(Op)); + } else if (MCOperand_isImm(Op)) { + int64_t imm = MCOperand_getImm(Op); + printImm(MI, O, imm, MI->csh->imm_unsigned); + } +} + +#ifndef CAPSTONE_DIET +// copy & normalize access info +static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags) +{ +#ifndef CAPSTONE_DIET + uint8_t i; + const uint8_t *arr = X86_get_op_access(h, id, eflags); + + // initialize access + memset(access, 0, CS_X86_MAXIMUM_OPERAND_SIZE * sizeof(access[0])); + + if (!arr) { + access[0] = 0; + return; + } + + // copy to access but zero out CS_AC_IGNORE + for(i = 0; arr[i]; i++) { + if (arr[i] != CS_AC_IGNORE) + access[i] = arr[i]; + else + access[i] = 0; + } + + // mark the end of array + access[i] = 0; +#endif +} +#endif + +static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O) +{ + MCOperand *SegReg; + int reg; + + if (MI->csh->detail_opt) { +#ifndef CAPSTONE_DIET + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; +#endif + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; + +#ifndef CAPSTONE_DIET + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; +#endif + } + + SegReg = MCInst_getOperand(MI, Op + 1); + reg = MCOperand_getReg(SegReg); + + // If this has a segment register, print it. + if (reg) { + _printOperand(MI, Op + 1, O); + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); + } + SStream_concat0(O, ":"); + } + + SStream_concat0(O, "["); + set_mem_access(MI, true); + printOperand(MI, Op, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printDstIdx(MCInst *MI, unsigned Op, SStream *O) +{ + if (MI->csh->detail_opt) { +#ifndef CAPSTONE_DIET + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; +#endif + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; + +#ifndef CAPSTONE_DIET + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; +#endif + } + + // DI accesses are always ES-based on non-64bit mode + if (MI->csh->mode != CS_MODE_64) { + SStream_concat0(O, "es:["); + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES; + } + } else + SStream_concat0(O, "["); + + set_mem_access(MI, true); + printOperand(MI, Op, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printSrcIdx8(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "byte ptr "); + MI->x86opsize = 1; + printSrcIdx(MI, OpNo, O); +} + +static void printSrcIdx16(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "word ptr "); + MI->x86opsize = 2; + printSrcIdx(MI, OpNo, O); +} + +static void printSrcIdx32(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "dword ptr "); + MI->x86opsize = 4; + printSrcIdx(MI, OpNo, O); +} + +static void printSrcIdx64(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "qword ptr "); + MI->x86opsize = 8; + printSrcIdx(MI, OpNo, O); +} + +static void printDstIdx8(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "byte ptr "); + MI->x86opsize = 1; + printDstIdx(MI, OpNo, O); +} + +static void printDstIdx16(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "word ptr "); + MI->x86opsize = 2; + printDstIdx(MI, OpNo, O); +} + +static void printDstIdx32(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "dword ptr "); + MI->x86opsize = 4; + printDstIdx(MI, OpNo, O); +} + +static void printDstIdx64(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "qword ptr "); + MI->x86opsize = 8; + printDstIdx(MI, OpNo, O); +} + +static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) +{ + MCOperand *DispSpec = MCInst_getOperand(MI, Op); + MCOperand *SegReg = MCInst_getOperand(MI, Op + 1); + int reg; + + if (MI->csh->detail_opt) { +#ifndef CAPSTONE_DIET + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; +#endif + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; + +#ifndef CAPSTONE_DIET + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; +#endif + } + + // If this has a segment register, print it. + reg = MCOperand_getReg(SegReg); + if (reg) { + _printOperand(MI, Op + 1, O); + SStream_concat0(O, ":"); + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); + } + } + + SStream_concat0(O, "["); + + if (MCOperand_isImm(DispSpec)) { + int64_t imm = MCOperand_getImm(DispSpec); + if (MI->csh->detail_opt) + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; + + if (imm < 0) + printImm(MI, O, arch_masks[MI->csh->mode] & imm, true); + else + printImm(MI, O, imm, true); + } + + SStream_concat0(O, "]"); + + if (MI->csh->detail_opt) + MI->flat_insn->detail->x86.op_count++; + + if (MI->op1_size == 0) + MI->op1_size = MI->x86opsize; +} + +static void printU8Imm(MCInst *MI, unsigned Op, SStream *O) +{ + uint8_t val = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0xff; + + printImm(MI, O, val, true); + + if (MI->csh->detail_opt) { +#ifndef CAPSTONE_DIET + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; +#endif + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = val; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = 1; + +#ifndef CAPSTONE_DIET + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; +#endif + + MI->flat_insn->detail->x86.op_count++; + } +} + +static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "byte ptr "); + MI->x86opsize = 1; + printMemOffset(MI, OpNo, O); +} + +static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "word ptr "); + MI->x86opsize = 2; + printMemOffset(MI, OpNo, O); +} + +static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "dword ptr "); + MI->x86opsize = 4; + printMemOffset(MI, OpNo, O); +} + +static void printMemOffs64(MCInst *MI, unsigned OpNo, SStream *O) +{ + SStream_concat0(O, "qword ptr "); + MI->x86opsize = 8; + printMemOffset(MI, OpNo, O); +} + +static void printInstruction(MCInst *MI, SStream *O); + +void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info) +{ + x86_reg reg, reg2; + enum cs_ac_type access1, access2; + + // printf("opcode = %u\n", MCInst_getOpcode(MI)); + + // perhaps this instruction does not need printer + if (MI->assembly[0]) { + strncpy(O->buffer, MI->assembly, sizeof(O->buffer)); + return; + } + + X86_lockrep(MI, O); + printInstruction(MI, O); + + reg = X86_insn_reg_intel(MCInst_getOpcode(MI), &access1); + if (MI->csh->detail_opt) { +#ifndef CAPSTONE_DIET + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE] = {0}; +#endif + + // first op can be embedded in the asm by llvm. + // so we have to add the missing register as the first operand + if (reg) { + // shift all the ops right to leave 1st slot for this new register op + memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), + sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); + MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; + MI->flat_insn->detail->x86.operands[0].reg = reg; + MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; + MI->flat_insn->detail->x86.operands[0].access = access1; + MI->flat_insn->detail->x86.op_count++; + } else { + if (X86_insn_reg_intel2(MCInst_getOpcode(MI), ®, &access1, ®2, &access2)) { + MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; + MI->flat_insn->detail->x86.operands[0].reg = reg; + MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; + MI->flat_insn->detail->x86.operands[0].access = access1; + MI->flat_insn->detail->x86.operands[1].type = X86_OP_REG; + MI->flat_insn->detail->x86.operands[1].reg = reg2; + MI->flat_insn->detail->x86.operands[1].size = MI->csh->regsize_map[reg2]; + MI->flat_insn->detail->x86.operands[1].access = access2; + MI->flat_insn->detail->x86.op_count = 2; + } + } + +#ifndef CAPSTONE_DIET + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[0].access = access[0]; + MI->flat_insn->detail->x86.operands[1].access = access[1]; +#endif + } + + if (MI->op1_size == 0 && reg) + MI->op1_size = MI->csh->regsize_map[reg]; +} + +/// printPCRelImm - This is used to print an immediate value that ends up +/// being encoded as a pc-relative value. +static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + if (MCOperand_isImm(Op)) { + int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; + uint8_t opsize = X86_immediate_size(MI->Opcode, NULL); + + // truncate imm for non-64bit + if (MI->csh->mode != CS_MODE_64) { + imm = imm & 0xffffffff; + } + + printImm(MI, O, imm, true); + + if (MI->csh->detail_opt) { +#ifndef CAPSTONE_DIET + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; +#endif + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; + // if op_count > 0, then this operand's size is taken from the destination op + if (MI->flat_insn->detail->x86.op_count > 0) + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size; + else if (opsize > 0) + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize; + else + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; + +#ifndef CAPSTONE_DIET + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; +#endif + + MI->flat_insn->detail->x86.op_count++; + } + + if (MI->op1_size == 0) + MI->op1_size = MI->imm_size; + } +} + +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + + if (MCOperand_isReg(Op)) { + unsigned int reg = MCOperand_getReg(Op); + + printRegName(O, reg); + if (MI->csh->detail_opt) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(reg); + } else { +#ifndef CAPSTONE_DIET + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; +#endif + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = X86_register_map(reg); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[X86_register_map(reg)]; + +#ifndef CAPSTONE_DIET + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; +#endif + + MI->flat_insn->detail->x86.op_count++; + } + } + + if (MI->op1_size == 0) + MI->op1_size = MI->csh->regsize_map[X86_register_map(reg)]; + } else if (MCOperand_isImm(Op)) { + uint8_t encsize; + int64_t imm = MCOperand_getImm(Op); + uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize); + + if (opsize == 1) // print 1 byte immediate in positive form + imm = imm & 0xff; + + // printf(">>> id = %u\n", MI->flat_insn->id); + switch(MI->flat_insn->id) { + default: + printImm(MI, O, imm, MI->csh->imm_unsigned); + break; + + case X86_INS_MOVABS: + case X86_INS_MOV: + // do not print number in negative form + printImm(MI, O, imm, true); + break; + + case X86_INS_IN: + case X86_INS_OUT: + case X86_INS_INT: + // do not print number in negative form + imm = imm & 0xff; + printImm(MI, O, imm, true); + break; + + case X86_INS_LCALL: + case X86_INS_LJMP: + case X86_INS_JMP: + // always print address in positive form + if (OpNo == 1) { // ptr16 part + imm = imm & 0xffff; + opsize = 2; + } else + opsize = 4; + printImm(MI, O, imm, true); + break; + + case X86_INS_AND: + case X86_INS_OR: + case X86_INS_XOR: + // do not print number in negative form + if (imm >= 0 && imm <= HEX_THRESHOLD) + printImm(MI, O, imm, true); + else { + imm = arch_masks[opsize? opsize : MI->imm_size] & imm; + printImm(MI, O, imm, true); + } + break; + + case X86_INS_RET: + case X86_INS_RETF: + // RET imm16 + if (imm >= 0 && imm <= HEX_THRESHOLD) + printImm(MI, O, imm, true); + else { + imm = 0xffff & imm; + printImm(MI, O, imm, true); + } + break; + } + + if (MI->csh->detail_opt) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; + } else { +#ifndef CAPSTONE_DIET + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; +#endif + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; + if (opsize > 0) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize; + MI->flat_insn->detail->x86.encoding.imm_size = encsize; + } else if (MI->flat_insn->detail->x86.op_count > 0) { + if (MI->flat_insn->id != X86_INS_LCALL && MI->flat_insn->id != X86_INS_LJMP) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = + MI->flat_insn->detail->x86.operands[0].size; + } else + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; + } else + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; + +#ifndef CAPSTONE_DIET + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; +#endif + + MI->flat_insn->detail->x86.op_count++; + } + } + } +} + +static void printMemReference(MCInst *MI, unsigned Op, SStream *O) +{ + bool NeedPlus = false; + MCOperand *BaseReg = MCInst_getOperand(MI, Op + X86_AddrBaseReg); + uint64_t ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op + X86_AddrScaleAmt)); + MCOperand *IndexReg = MCInst_getOperand(MI, Op + X86_AddrIndexReg); + MCOperand *DispSpec = MCInst_getOperand(MI, Op + X86_AddrDisp); + MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg); + int reg; + + if (MI->csh->detail_opt) { +#ifndef CAPSTONE_DIET + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; +#endif + + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(MCOperand_getReg(BaseReg)); + if (MCOperand_getReg(IndexReg) != X86_EIZ) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_register_map(MCOperand_getReg(IndexReg)); + } + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; + +#ifndef CAPSTONE_DIET + get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; +#endif + } + + // If this has a segment register, print it. + reg = MCOperand_getReg(SegReg); + if (reg) { + _printOperand(MI, Op + X86_AddrSegmentReg, O); + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); + } + SStream_concat0(O, ":"); + } + + SStream_concat0(O, "["); + + if (MCOperand_getReg(BaseReg)) { + _printOperand(MI, Op + X86_AddrBaseReg, O); + NeedPlus = true; + } + + if (MCOperand_getReg(IndexReg) && MCOperand_getReg(IndexReg) != X86_EIZ) { + if (NeedPlus) SStream_concat0(O, " + "); + _printOperand(MI, Op + X86_AddrIndexReg, O); + if (ScaleVal != 1) + SStream_concat(O, "*%u", ScaleVal); + NeedPlus = true; + } + + if (MCOperand_isImm(DispSpec)) { + int64_t DispVal = MCOperand_getImm(DispSpec); + if (MI->csh->detail_opt) + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal; + if (DispVal) { + if (NeedPlus) { + if (DispVal < 0) { + SStream_concat0(O, " - "); + printImm(MI, O, -DispVal, true); + } else { + SStream_concat0(O, " + "); + printImm(MI, O, DispVal, true); + } + } else { + // memory reference to an immediate address + if (MI->csh->mode == CS_MODE_64) + MI->op1_size = 8; + if (DispVal < 0) { + printImm(MI, O, arch_masks[MI->csh->mode] & DispVal, true); + } else { + printImm(MI, O, DispVal, true); + } + } + + } else { + // DispVal = 0 + if (!NeedPlus) // [0] + SStream_concat0(O, "0"); + } + } + + SStream_concat0(O, "]"); + + if (MI->csh->detail_opt) + MI->flat_insn->detail->x86.op_count++; + + if (MI->op1_size == 0) + MI->op1_size = MI->x86opsize; +} + +static void printanymem(MCInst *MI, unsigned OpNo, SStream *O) +{ + switch(MI->Opcode) { + default: break; + case X86_LEA16r: + MI->x86opsize = 2; + break; + case X86_LEA32r: + case X86_LEA64_32r: + MI->x86opsize = 4; + break; + case X86_LEA64r: + MI->x86opsize = 8; + break; +#ifndef CAPSTONE_X86_REDUCE + case X86_BNDCL32rm: + case X86_BNDCN32rm: + case X86_BNDCU32rm: + case X86_BNDSTXmr: + case X86_BNDLDXrm: + case X86_BNDCL64rm: + case X86_BNDCN64rm: + case X86_BNDCU64rm: + MI->x86opsize = 16; + break; +#endif + } + + printMemReference(MI, OpNo, O); +} + +#ifdef CAPSTONE_X86_REDUCE +#include "X86GenAsmWriter1_reduce.inc" +#else +#include "X86GenAsmWriter1.inc" +#endif + +#include "X86GenRegisterName1.inc" + +#endif diff --git a/thirdparty/capstone/arch/X86/X86Lookup16.inc b/thirdparty/capstone/arch/X86/X86Lookup16.inc new file mode 100644 index 0000000..2f0ba81 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86Lookup16.inc @@ -0,0 +1,16874 @@ +typedef struct x86_op_id_pair { + uint16_t first; + uint16_t second; +} x86_op_id_pair; + +static const x86_op_id_pair x86_16_bit_eq_tbl[] = { + { 138, 139 }, + { 141, 142 }, + { 163, 154 }, + { 164, 155 }, + { 165, 156 }, + { 166, 157 }, + { 167, 158 }, + { 168, 159 }, + { 169, 160 }, + { 170, 161 }, + { 171, 162 }, + { 172, 154 }, + { 174, 156 }, + { 175, 157 }, + { 177, 159 }, + { 178, 160 }, + { 179, 161 }, + { 180, 162 }, + { 203, 194 }, + { 204, 195 }, + { 205, 196 }, + { 206, 197 }, + { 207, 198 }, + { 208, 199 }, + { 209, 200 }, + { 210, 201 }, + { 211, 202 }, + { 212, 194 }, + { 214, 196 }, + { 215, 197 }, + { 217, 199 }, + { 218, 200 }, + { 219, 201 }, + { 220, 202 }, + { 249, 248 }, + { 263, 260 }, + { 264, 261 }, + { 265, 262 }, + { 292, 283 }, + { 293, 284 }, + { 294, 285 }, + { 295, 286 }, + { 296, 287 }, + { 297, 288 }, + { 298, 289 }, + { 299, 290 }, + { 300, 291 }, + { 301, 283 }, + { 303, 285 }, + { 304, 286 }, + { 306, 288 }, + { 307, 289 }, + { 308, 290 }, + { 309, 291 }, + { 412, 411 }, + { 415, 413 }, + { 416, 414 }, + { 417, 413 }, + { 418, 414 }, + { 421, 419 }, + { 422, 420 }, + { 423, 419 }, + { 424, 420 }, + { 432, 428 }, + { 433, 429 }, + { 434, 430 }, + { 435, 431 }, + { 436, 428 }, + { 437, 429 }, + { 438, 430 }, + { 439, 431 }, + { 444, 440 }, + { 445, 441 }, + { 446, 442 }, + { 447, 443 }, + { 448, 440 }, + { 449, 441 }, + { 450, 442 }, + { 451, 443 }, + { 456, 452 }, + { 457, 453 }, + { 458, 454 }, + { 459, 455 }, + { 460, 452 }, + { 461, 453 }, + { 462, 454 }, + { 463, 455 }, + { 468, 464 }, + { 469, 465 }, + { 470, 466 }, + { 471, 467 }, + { 472, 464 }, + { 473, 465 }, + { 474, 466 }, + { 475, 467 }, + { 484, 480 }, + { 485, 481 }, + { 486, 482 }, + { 487, 483 }, + { 488, 480 }, + { 489, 481 }, + { 491, 482 }, + { 492, 483 }, + { 494, 493 }, + { 504, 805 }, + { 517, 515 }, + { 518, 516 }, + { 519, 515 }, + { 520, 516 }, + { 523, 521 }, + { 524, 522 }, + { 525, 521 }, + { 526, 522 }, + { 529, 527 }, + { 530, 528 }, + { 531, 527 }, + { 532, 528 }, + { 535, 533 }, + { 536, 534 }, + { 537, 533 }, + { 538, 534 }, + { 549, 547 }, + { 550, 548 }, + { 551, 547 }, + { 552, 548 }, + { 559, 557 }, + { 560, 558 }, + { 561, 557 }, + { 562, 558 }, + { 565, 563 }, + { 566, 564 }, + { 567, 563 }, + { 568, 564 }, + { 571, 569 }, + { 572, 570 }, + { 573, 569 }, + { 574, 570 }, + { 577, 575 }, + { 578, 576 }, + { 579, 575 }, + { 580, 576 }, + { 591, 589 }, + { 592, 590 }, + { 593, 589 }, + { 594, 590 }, + { 601, 599 }, + { 602, 600 }, + { 603, 599 }, + { 604, 600 }, + { 607, 605 }, + { 608, 606 }, + { 609, 605 }, + { 610, 606 }, + { 617, 615 }, + { 618, 616 }, + { 619, 615 }, + { 620, 616 }, + { 623, 621 }, + { 624, 622 }, + { 625, 621 }, + { 626, 622 }, + { 629, 627 }, + { 630, 628 }, + { 631, 627 }, + { 632, 628 }, + { 639, 637 }, + { 640, 638 }, + { 641, 637 }, + { 642, 638 }, + { 652, 643 }, + { 653, 644 }, + { 654, 645 }, + { 655, 646 }, + { 656, 647 }, + { 657, 648 }, + { 658, 649 }, + { 659, 650 }, + { 660, 651 }, + { 661, 643 }, + { 663, 645 }, + { 664, 646 }, + { 666, 648 }, + { 667, 649 }, + { 668, 650 }, + { 669, 651 }, + { 694, 702 }, + { 695, 702 }, + { 706, 704 }, + { 707, 705 }, + { 708, 704 }, + { 709, 705 }, + { 732, 731 }, + { 735, 734 }, + { 813, 810 }, + { 814, 811 }, + { 815, 812 }, + { 816, 810 }, + { 817, 811 }, + { 822, 820 }, + { 823, 821 }, + { 824, 820 }, + { 825, 821 }, + { 835, 834 }, + { 846, 843 }, + { 847, 844 }, + { 848, 845 }, + { 861, 860 }, + { 875, 872 }, + { 876, 873 }, + { 877, 874 }, + { 896, 894 }, + { 897, 895 }, + { 901, 899 }, + { 902, 900 }, + { 918, 917 }, + { 920, 919 }, + { 973, 971 }, + { 974, 972 }, + { 975, 971 }, + { 976, 972 }, + { 980, 979 }, + { 981, 979 }, + { 985, 982 }, + { 986, 983 }, + { 987, 984 }, + { 988, 982 }, + { 989, 983 }, + { 990, 984 }, + { 999, 991 }, + { 1000, 992 }, + { 1001, 993 }, + { 1002, 994 }, + { 1003, 995 }, + { 1004, 996 }, + { 1005, 997 }, + { 1006, 998 }, + { 1007, 991 }, + { 1008, 992 }, + { 1009, 993 }, + { 1011, 995 }, + { 1012, 996 }, + { 1014, 998 }, + { 1019, 1017 }, + { 1020, 1018 }, + { 1026, 1023 }, + { 1027, 1024 }, + { 1028, 1025 }, + { 1029, 1023 }, + { 1030, 1024 }, + { 1040, 1041 }, + { 1044, 1043 }, + { 1057, 1056 }, + { 1058, 1056 }, + { 1060, 1059 }, + { 1061, 1059 }, + { 1065, 1062 }, + { 1066, 1063 }, + { 1067, 1064 }, + { 1068, 1062 }, + { 1069, 1063 }, + { 1070, 1064 }, + { 1072, 1071 }, + { 1074, 1073 }, + { 1075, 1073 }, + { 1079, 1076 }, + { 1080, 1077 }, + { 1081, 1078 }, + { 1082, 1076 }, + { 1083, 1077 }, + { 1084, 1078 }, + { 1118, 1114 }, + { 1119, 1115 }, + { 1120, 1116 }, + { 1121, 1117 }, + { 1122, 1114 }, + { 1123, 1115 }, + { 1124, 1116 }, + { 1125, 1117 }, + { 1153, 1154 }, + { 1159, 1160 }, + { 1161, 1162 }, + { 1173, 1178 }, + { 1174, 1179 }, + { 1175, 1180 }, + { 1176, 1181 }, + { 1177, 1182 }, + { 1185, 1186 }, + { 1189, 1194 }, + { 1192, 1193 }, + { 1197, 1198 }, + { 1201, 1202 }, + { 1205, 1206 }, + { 1212, 1213 }, + { 1216, 1217 }, + { 1221, 1219 }, + { 1222, 1220 }, + { 1223, 1219 }, + { 1224, 1220 }, + { 1228, 1227 }, + { 1248, 1247 }, + { 1250, 1247 }, + { 1254, 1253 }, + { 1257, 1256 }, + { 1258, 1256 }, + { 1260, 1259 }, + { 1261, 1259 }, + { 1263, 1262 }, + { 1264, 1262 }, + { 1266, 1265 }, + { 1267, 1265 }, + { 1276, 1278 }, + { 1277, 1278 }, + { 1282, 1284 }, + { 1283, 1284 }, + { 1285, 1287 }, + { 1286, 1287 }, + { 1290, 1288 }, + { 1291, 1289 }, + { 1292, 1288 }, + { 1293, 1289 }, + { 1295, 1294 }, + { 1296, 1294 }, + { 1309, 1307 }, + { 1310, 1308 }, + { 1311, 1307 }, + { 1312, 1308 }, + { 1404, 1414 }, + { 1405, 1415 }, + { 1493, 1496 }, + { 1494, 1497 }, + { 1495, 1498 }, + { 1508, 1511 }, + { 1509, 1512 }, + { 1510, 1513 }, + { 1518, 1528 }, + { 1519, 1529 }, + { 1548, 1547 }, + { 1549, 1547 }, + { 1554, 1553 }, + { 1555, 1553 }, + { 1564, 1547 }, + { 1565, 1547 }, + { 1565, 1548 }, + { 1565, 1564 }, + { 1566, 1547 }, + { 1566, 1549 }, + { 1566, 1564 }, + { 1569, 1550 }, + { 1570, 1551 }, + { 1571, 1553 }, + { 1572, 1553 }, + { 1572, 1554 }, + { 1572, 1571 }, + { 1573, 1553 }, + { 1573, 1555 }, + { 1573, 1571 }, + { 1576, 1556 }, + { 1577, 1557 }, + { 1578, 1558 }, + { 1579, 1559 }, + { 1580, 1560 }, + { 1581, 1561 }, + { 1582, 1563 }, + { 1583, 1547 }, + { 1583, 1548 }, + { 1584, 1547 }, + { 1584, 1549 }, + { 1588, 1551 }, + { 1589, 1553 }, + { 1589, 1554 }, + { 1590, 1553 }, + { 1590, 1555 }, + { 1593, 1556 }, + { 1595, 1558 }, + { 1596, 1559 }, + { 1597, 1560 }, + { 1598, 1561 }, + { 1599, 1563 }, + { 1605, 1604 }, + { 1606, 1604 }, + { 1611, 1610 }, + { 1612, 1610 }, + { 1630, 1628 }, + { 1631, 1629 }, + { 1632, 1628 }, + { 1633, 1629 }, + { 1641, 1640 }, + { 1642, 1640 }, + { 1689, 1699 }, + { 1692, 1699 }, + { 1704, 1700 }, + { 1705, 1701 }, + { 1707, 1702 }, + { 1708, 1703 }, + { 1710, 1700 }, + { 1711, 1700 }, + { 1711, 1710 }, + { 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11549, 11571 }, + { 11550, 11572 }, + { 11551, 11573 }, + { 11552, 11574 }, + { 11553, 11575 }, + { 11554, 11576 }, + { 11771, 11800 }, + { 11775, 11801 }, + { 11776, 11802 }, + { 11777, 11803 }, + { 11778, 11804 }, + { 11779, 11805 }, + { 11780, 11806 }, + { 11784, 11807 }, + { 11785, 11808 }, + { 11786, 11809 }, + { 11787, 11810 }, + { 11788, 11811 }, + { 11789, 11812 }, + { 11793, 11813 }, + { 11794, 11814 }, + { 11795, 11815 }, + { 11796, 11816 }, + { 11797, 11817 }, + { 11923, 11950 }, + { 11927, 11951 }, + { 11928, 11952 }, + { 11929, 11953 }, + { 11930, 11954 }, + { 11931, 11955 }, + { 11932, 11956 }, + { 11936, 11957 }, + { 11937, 11958 }, + { 11938, 11959 }, + { 11939, 11960 }, + { 11940, 11961 }, + { 11941, 11962 }, + { 11945, 11963 }, + { 11946, 11964 }, + { 11947, 11965 }, + { 11948, 11966 }, + { 11949, 11967 }, + { 12258, 12264 }, + { 12259, 12265 }, + { 12260, 12266 }, + { 12261, 12267 }, + { 12262, 12268 }, + { 12263, 12269 }, + { 12300, 12304 }, + { 12301, 12305 }, + { 12302, 12306 }, + { 12303, 12307 }, + { 12342, 12438 }, + { 12343, 12439 }, + { 12344, 12440 }, + { 12345, 12441 }, + { 12346, 12442 }, + { 12347, 12443 }, + { 12351, 12444 }, + { 12352, 12445 }, + { 12353, 12446 }, + { 12354, 12447 }, + { 12355, 12448 }, + { 12356, 12449 }, + { 12360, 12450 }, + { 12361, 12451 }, + { 12362, 12452 }, + { 12363, 12453 }, + { 12364, 12454 }, + { 12365, 12455 }, + { 12393, 12420 }, + { 12397, 12421 }, + { 12398, 12422 }, + { 12399, 12423 }, + { 12400, 12424 }, + { 12401, 12425 }, + { 12402, 12426 }, + { 12406, 12427 }, + { 12407, 12428 }, + { 12408, 12429 }, + { 12409, 12430 }, + { 12410, 12431 }, + { 12411, 12432 }, + { 12415, 12433 }, + { 12416, 12434 }, + { 12417, 12435 }, + { 12418, 12436 }, + { 12419, 12437 }, + { 12460, 12464 }, + { 12461, 12465 }, + { 12462, 12466 }, + { 12463, 12467 }, + { 12498, 12594 }, + { 12499, 12595 }, + { 12500, 12596 }, + { 12501, 12597 }, + { 12502, 12598 }, + { 12503, 12599 }, + { 12507, 12600 }, + { 12508, 12601 }, + { 12509, 12602 }, + { 12510, 12603 }, + { 12511, 12604 }, + { 12512, 12605 }, + { 12516, 12606 }, + { 12517, 12607 }, + { 12518, 12608 }, + { 12519, 12609 }, + { 12520, 12610 }, + { 12521, 12611 }, + { 12549, 12576 }, + { 12553, 12577 }, + { 12554, 12578 }, + { 12555, 12579 }, + { 12556, 12580 }, + { 12557, 12581 }, + { 12558, 12582 }, + { 12562, 12583 }, + { 12563, 12584 }, + { 12564, 12585 }, + { 12565, 12586 }, + { 12566, 12587 }, + { 12567, 12588 }, + { 12571, 12589 }, + { 12572, 12590 }, + { 12573, 12591 }, + { 12574, 12592 }, + { 12575, 12593 }, + { 12792, 12923 }, + { 12793, 12924 }, + { 12794, 12925 }, + { 12798, 12926 }, + { 12799, 12927 }, + { 12800, 12928 }, + { 12801, 12929 }, + { 12802, 12930 }, + { 12803, 12931 }, + { 12804, 12932 }, + { 12805, 12933 }, + { 12806, 12934 }, + { 12807, 12935 }, + { 12808, 12936 }, + { 12809, 12937 }, + { 12813, 12938 }, + { 12814, 12939 }, + { 12815, 12940 }, + { 12816, 12941 }, + { 12817, 12942 }, + { 12818, 12943 }, + { 12819, 12944 }, + { 12820, 12945 }, + { 12821, 12946 }, + { 12822, 12947 }, + { 12823, 12948 }, + { 12824, 12949 }, + { 12828, 12950 }, + { 12829, 12951 }, + { 12830, 12952 }, + { 12831, 12953 }, + { 12832, 12954 }, + { 12833, 12955 }, + { 12834, 12956 }, + { 12835, 12957 }, + { 12836, 12958 }, + { 12837, 12959 }, + { 12838, 12960 }, + { 12839, 12961 }, + { 12840, 12962 }, + { 12841, 12963 }, + { 12842, 12964 }, + { 12876, 12905 }, + { 12880, 12906 }, + { 12881, 12907 }, + { 12882, 12908 }, + { 12883, 12909 }, + { 12884, 12910 }, + { 12885, 12911 }, + { 12889, 12912 }, + { 12890, 12913 }, + { 12891, 12914 }, + { 12892, 12915 }, + { 12893, 12916 }, + { 12894, 12917 }, + { 12898, 12918 }, + { 12899, 12919 }, + { 12900, 12920 }, + { 12901, 12921 }, + { 12902, 12922 }, + { 13019, 13140 }, + { 13020, 13141 }, + { 13021, 13142 }, + { 13022, 13143 }, + { 13023, 13144 }, + { 13024, 13145 }, + { 13025, 13146 }, + { 13026, 13147 }, + { 13027, 13148 }, + { 13028, 13149 }, + { 13029, 13150 }, + { 13030, 13151 }, + { 13034, 13152 }, + { 13035, 13153 }, + { 13036, 13154 }, + { 13037, 13155 }, + { 13038, 13156 }, + { 13039, 13157 }, + { 13040, 13158 }, + { 13041, 13159 }, + { 13042, 13160 }, + { 13043, 13161 }, + { 13044, 13162 }, + { 13045, 13163 }, + { 13049, 13164 }, + { 13050, 13165 }, + { 13051, 13166 }, + { 13052, 13167 }, + { 13053, 13168 }, + { 13054, 13169 }, + { 13055, 13170 }, + { 13056, 13171 }, + { 13057, 13172 }, + { 13058, 13173 }, + { 13059, 13174 }, + { 13060, 13175 }, + { 13092, 13119 }, + { 13096, 13120 }, + { 13097, 13121 }, + { 13098, 13122 }, + { 13099, 13123 }, + { 13100, 13124 }, + { 13101, 13125 }, + { 13105, 13126 }, + { 13106, 13127 }, + { 13107, 13128 }, + { 13108, 13129 }, + { 13109, 13130 }, + { 13110, 13131 }, + { 13114, 13132 }, + { 13115, 13133 }, + { 13116, 13134 }, + { 13117, 13135 }, + { 13118, 13136 }, + { 13238, 13369 }, + { 13239, 13370 }, + { 13240, 13371 }, + { 13244, 13372 }, + { 13245, 13373 }, + { 13246, 13374 }, + { 13247, 13375 }, + { 13248, 13376 }, + { 13249, 13377 }, + { 13250, 13378 }, + { 13251, 13379 }, + { 13252, 13380 }, + { 13253, 13381 }, + { 13254, 13382 }, + { 13255, 13383 }, + { 13259, 13384 }, + { 13260, 13385 }, + { 13261, 13386 }, + { 13262, 13387 }, + { 13263, 13388 }, + { 13264, 13389 }, + { 13265, 13390 }, + { 13266, 13391 }, + { 13267, 13392 }, + { 13268, 13393 }, + { 13269, 13394 }, + { 13270, 13395 }, + { 13274, 13396 }, + { 13275, 13397 }, + { 13276, 13398 }, + { 13277, 13399 }, + { 13278, 13400 }, + { 13279, 13401 }, + { 13280, 13402 }, + { 13281, 13403 }, + { 13282, 13404 }, + { 13283, 13405 }, + { 13284, 13406 }, + { 13285, 13407 }, + { 13286, 13408 }, + { 13287, 13409 }, + { 13288, 13410 }, + { 13322, 13351 }, + { 13326, 13352 }, + { 13327, 13353 }, + { 13328, 13354 }, + { 13329, 13355 }, + { 13330, 13356 }, + { 13331, 13357 }, + { 13335, 13358 }, + { 13336, 13359 }, + { 13337, 13360 }, + { 13338, 13361 }, + { 13339, 13362 }, + { 13340, 13363 }, + { 13344, 13364 }, + { 13345, 13365 }, + { 13346, 13366 }, + { 13347, 13367 }, + { 13348, 13368 }, + { 13464, 13583 }, + { 13465, 13584 }, + { 13466, 13585 }, + { 13470, 13586 }, + { 13471, 13587 }, + { 13472, 13588 }, + { 13473, 13589 }, + { 13474, 13590 }, + { 13475, 13591 }, + { 13479, 13592 }, + { 13480, 13593 }, + { 13481, 13594 }, + { 13482, 13595 }, + { 13483, 13596 }, + { 13484, 13597 }, + { 13488, 13598 }, + { 13489, 13599 }, + { 13490, 13600 }, + { 13491, 13601 }, + { 13492, 13602 }, + { 13493, 13603 }, + { 13494, 13604 }, + { 13689, 13707 }, + { 13692, 13708 }, + { 13693, 13709 }, + { 13694, 13710 }, + { 13695, 13711 }, + { 13698, 13712 }, + { 13699, 13713 }, + { 13700, 13714 }, + { 13701, 13715 }, + { 13704, 13716 }, + { 13705, 13717 }, + { 13706, 13718 }, + { 13749, 13767 }, + { 13752, 13768 }, + { 13753, 13769 }, + { 13754, 13770 }, + { 13755, 13771 }, + { 13758, 13772 }, + { 13759, 13773 }, + { 13760, 13774 }, + { 13761, 13775 }, + { 13764, 13776 }, + { 13765, 13777 }, + { 13766, 13778 }, + { 15199, 15197 }, + { 15200, 15198 }, + { 15201, 15197 }, + { 15202, 15198 }, + { 15210, 15207 }, + { 15211, 15208 }, + { 15212, 15209 }, + { 15213, 15207 }, + { 15214, 15208 }, + { 15215, 15209 }, + { 15236, 15227 }, + { 15237, 15228 }, + { 15238, 15229 }, + { 15239, 15230 }, + { 15240, 15231 }, + { 15241, 15232 }, + { 15242, 15233 }, + { 15243, 15234 }, + { 15244, 15235 }, + { 15245, 15227 }, + { 15247, 15229 }, + { 15248, 15230 }, + { 15250, 15232 }, + { 15251, 15233 }, + { 15252, 15234 }, + { 15253, 15235 }, +}; + +static const uint16_t x86_16_bit_eq_lookup[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 0, + 13, + 14, + 0, + 15, + 16, + 17, + 18, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 0, + 29, + 30, + 0, + 31, + 32, + 33, + 34, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 35, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 36, + 37, + 38, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 0, + 49, + 50, + 0, + 51, + 52, + 53, + 54, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 55, + 0, + 0, + 56, + 57, + 58, + 59, + 0, + 0, + 60, + 61, + 62, + 63, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 64, + 65, + 66, + 67, + 68, + 69, + 70, + 71, + 0, + 0, + 0, + 0, + 72, + 73, + 74, + 75, + 76, + 77, + 78, + 79, + 0, + 0, + 0, + 0, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 0, + 0, + 0, + 0, + 88, + 89, + 90, + 91, + 92, + 93, + 94, + 95, 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0, + 0, + 0, + 0, + 0, + 170, + 171, + 172, + 173, + 174, + 175, + 176, + 177, + 178, + 179, + 0, + 180, + 181, + 0, + 182, + 183, + 184, + 185, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 186, + 187, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 188, + 189, + 190, + 191, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 192, + 0, + 0, + 193, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 194, + 195, + 196, + 197, + 198, + 0, + 0, + 0, + 0, + 199, + 200, + 201, + 202, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 243, + 244, + 0, + 0, + 0, + 0, + 0, + 245, + 246, + 247, + 248, + 249, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 250, + 0, + 0, + 0, + 251, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 252, + 253, + 0, + 254, + 255, + 0, + 0, + 0, + 256, + 257, + 258, + 259, + 260, + 261, + 0, + 262, + 0, + 263, + 264, + 0, + 0, + 0, + 265, + 266, + 267, + 268, + 269, + 270, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 271, + 272, + 273, + 274, + 275, + 276, + 277, + 278, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 279, + 0, + 0, + 0, + 0, + 0, + 280, + 0, + 281, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 282, + 283, + 284, + 285, + 286, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 287, + 0, + 0, + 0, + 288, + 0, + 0, + 289, + 0, + 0, + 0, + 0, + 290, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1554, + 1555, + 1556, + 1557, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1558, + 1559, + 1560, + 1561, + 1562, + 1563, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1564, + 1565, + 1566, + 1567, + 1568, + 1569, + 1570, + 1571, + 1572, + 1573, + 0, + 1574, + 1575, + 0, + 1576, + 1577, + 1578, + 1579, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; diff --git a/thirdparty/capstone/arch/X86/X86Lookup16_reduce.inc b/thirdparty/capstone/arch/X86/X86Lookup16_reduce.inc new file mode 100644 index 0000000..3b474cf --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86Lookup16_reduce.inc @@ -0,0 +1,2308 @@ +typedef struct x86_op_id_pair { + uint16_t first; + uint16_t second; +} x86_op_id_pair; + +static const x86_op_id_pair x86_16_bit_eq_tbl[] = { + { 139, 130 }, + { 140, 131 }, + { 141, 132 }, + { 142, 133 }, + { 143, 134 }, + { 144, 135 }, + { 145, 136 }, + { 146, 137 }, + { 147, 138 }, + { 148, 130 }, + { 150, 132 }, + { 151, 133 }, + { 153, 135 }, + { 154, 136 }, + { 155, 137 }, + { 156, 138 }, + { 179, 170 }, + { 180, 171 }, + { 181, 172 }, + { 182, 173 }, + { 183, 174 }, + { 184, 175 }, + { 185, 176 }, + { 186, 177 }, + { 187, 178 }, + { 188, 170 }, + { 190, 172 }, + { 191, 173 }, + { 193, 175 }, + { 194, 176 }, + { 195, 177 }, + { 196, 178 }, + { 219, 210 }, + { 220, 211 }, + { 221, 212 }, + { 222, 213 }, + { 223, 214 }, + { 224, 215 }, + { 225, 216 }, + { 226, 217 }, + { 227, 218 }, + { 228, 210 }, + { 230, 212 }, + { 231, 213 }, + { 233, 215 }, + { 234, 216 }, + { 235, 217 }, + { 236, 218 }, + { 301, 300 }, + { 304, 302 }, + { 305, 303 }, + { 306, 302 }, + { 307, 303 }, + { 310, 308 }, + { 311, 309 }, + { 312, 308 }, + { 313, 309 }, + { 321, 317 }, + { 322, 318 }, + { 323, 319 }, + { 324, 320 }, + { 325, 317 }, + { 326, 318 }, + { 327, 319 }, + { 328, 320 }, + { 333, 329 }, + { 334, 330 }, + { 335, 331 }, + { 336, 332 }, + { 337, 329 }, + { 338, 330 }, + { 339, 331 }, + { 340, 332 }, + { 345, 341 }, + { 346, 342 }, + { 347, 343 }, + { 348, 344 }, + { 349, 341 }, + { 350, 342 }, + { 351, 343 }, + { 352, 344 }, + { 357, 353 }, + { 358, 354 }, + { 359, 355 }, + { 360, 356 }, + { 361, 353 }, + { 362, 354 }, + { 363, 355 }, + { 364, 356 }, + { 373, 369 }, + { 374, 370 }, + { 375, 371 }, + { 376, 372 }, + { 377, 369 }, + { 378, 370 }, + { 380, 371 }, + { 381, 372 }, + { 383, 382 }, + { 389, 547 }, + { 401, 399 }, + { 402, 400 }, + { 403, 399 }, + { 404, 400 }, + { 407, 405 }, + { 408, 406 }, + { 409, 405 }, + { 410, 406 }, + { 413, 411 }, + { 414, 412 }, + { 415, 411 }, + { 416, 412 }, + { 419, 417 }, + { 420, 418 }, + { 421, 417 }, + { 422, 418 }, + { 425, 423 }, + { 426, 424 }, + { 427, 423 }, + { 428, 424 }, + { 431, 429 }, + { 432, 430 }, + { 433, 429 }, + { 434, 430 }, + { 437, 435 }, + { 438, 436 }, + { 439, 435 }, + { 440, 436 }, + { 443, 441 }, + { 444, 442 }, + { 445, 441 }, + { 446, 442 }, + { 449, 447 }, + { 450, 448 }, + { 451, 447 }, + { 452, 448 }, + { 455, 453 }, + { 456, 454 }, + { 457, 453 }, + { 458, 454 }, + { 461, 459 }, + { 462, 460 }, + { 463, 459 }, + { 464, 460 }, + { 467, 465 }, + { 468, 466 }, + { 469, 465 }, + { 470, 466 }, + { 473, 471 }, + { 474, 472 }, + { 475, 471 }, + { 476, 472 }, + { 479, 477 }, + { 480, 478 }, + { 481, 477 }, + { 482, 478 }, + { 485, 483 }, + { 486, 484 }, + { 487, 483 }, + { 488, 484 }, + { 491, 489 }, + { 492, 490 }, + { 493, 489 }, + { 494, 490 }, + { 504, 495 }, + { 505, 496 }, + { 506, 497 }, + { 507, 498 }, + { 508, 499 }, + { 509, 500 }, + { 510, 501 }, + { 511, 502 }, + { 512, 503 }, + { 513, 495 }, + { 515, 497 }, + { 516, 498 }, + { 518, 500 }, + { 519, 501 }, + { 520, 502 }, + { 521, 503 }, + { 532, 534 }, + { 533, 534 }, + { 538, 536 }, + { 539, 537 }, + { 540, 536 }, + { 541, 537 }, + { 555, 552 }, + { 556, 553 }, + { 557, 554 }, + { 558, 552 }, + { 559, 553 }, + { 564, 562 }, + { 565, 563 }, + { 566, 562 }, + { 567, 563 }, + { 575, 573 }, + { 576, 574 }, + { 580, 578 }, + { 581, 579 }, + { 588, 586 }, + { 589, 587 }, + { 590, 586 }, + { 591, 587 }, + { 602, 594 }, + { 603, 595 }, + { 604, 596 }, + { 605, 597 }, + { 606, 598 }, + { 607, 599 }, + { 608, 600 }, + { 609, 601 }, + { 610, 594 }, + { 611, 595 }, + { 612, 596 }, + { 614, 598 }, + { 615, 599 }, + { 617, 601 }, + { 622, 620 }, + { 623, 621 }, + { 629, 626 }, + { 630, 627 }, + { 631, 628 }, + { 632, 626 }, + { 633, 627 }, + { 639, 640 }, + { 643, 642 }, + { 656, 655 }, + { 657, 655 }, + { 691, 687 }, + { 692, 688 }, + { 693, 689 }, + { 694, 690 }, + { 695, 687 }, + { 696, 688 }, + { 697, 689 }, + { 698, 690 }, + { 727, 725 }, + { 728, 726 }, + { 729, 725 }, + { 730, 726 }, + { 732, 731 }, + { 734, 733 }, + { 736, 733 }, + { 740, 739 }, + { 742, 741 }, + { 743, 741 }, + { 745, 744 }, + { 746, 744 }, + { 748, 747 }, + { 749, 747 }, + { 751, 750 }, + { 752, 750 }, + { 761, 763 }, + { 762, 763 }, + { 767, 769 }, + { 768, 769 }, + { 770, 772 }, + { 771, 772 }, + { 775, 773 }, + { 776, 774 }, + { 777, 773 }, + { 778, 774 }, + { 780, 779 }, + { 781, 779 }, + { 794, 792 }, + { 795, 793 }, + { 796, 792 }, + { 797, 793 }, + { 801, 800 }, + { 802, 800 }, + { 807, 806 }, + { 808, 806 }, + { 817, 800 }, + { 818, 800 }, + { 818, 801 }, + { 818, 817 }, + { 819, 800 }, + { 819, 802 }, + { 819, 817 }, + { 822, 803 }, + { 823, 804 }, + { 824, 806 }, + { 825, 806 }, + { 825, 807 }, + { 825, 824 }, + { 826, 806 }, + { 826, 808 }, + { 826, 824 }, + { 829, 809 }, + { 830, 810 }, + { 831, 811 }, + { 832, 812 }, + { 833, 813 }, + { 834, 814 }, + { 835, 816 }, + { 836, 800 }, + { 836, 801 }, + { 837, 800 }, + { 837, 802 }, + { 841, 804 }, + { 842, 806 }, + { 842, 807 }, + { 843, 806 }, + { 843, 808 }, + { 846, 809 }, + { 848, 811 }, + { 849, 812 }, + { 850, 813 }, + { 851, 814 }, + { 852, 816 }, + { 854, 853 }, + { 855, 853 }, + { 860, 859 }, + { 861, 859 }, + { 871, 869 }, + { 872, 870 }, + { 873, 869 }, + { 874, 870 }, + { 876, 875 }, + { 877, 875 }, + { 881, 883 }, + { 882, 883 }, + { 888, 884 }, + { 889, 885 }, + { 891, 886 }, + { 892, 887 }, + { 894, 884 }, + { 895, 884 }, + { 895, 894 }, + { 896, 885 }, + { 897, 886 }, + { 898, 886 }, + { 898, 897 }, + { 899, 887 }, + { 904, 900 }, + { 905, 901 }, + { 907, 902 }, + { 908, 903 }, + { 910, 900 }, + { 911, 901 }, + { 912, 902 }, + { 913, 903 }, + { 916, 914 }, + { 917, 915 }, + { 918, 914 }, + { 919, 915 }, + { 929, 927 }, + { 930, 928 }, + { 931, 927 }, + { 932, 928 }, + { 936, 938 }, + { 940, 942 }, + { 944, 946 }, + { 948, 950 }, + { 953, 960 }, + { 954, 961 }, + { 955, 963 }, + { 956, 964 }, + { 957, 965 }, + { 958, 960 }, + { 959, 965 }, + { 968, 966 }, + { 969, 967 }, + { 970, 966 }, + { 971, 967 }, + { 983, 974 }, + { 984, 975 }, + { 985, 976 }, + { 986, 977 }, + { 987, 978 }, + { 988, 979 }, + { 989, 980 }, + { 990, 981 }, + { 991, 982 }, + { 992, 974 }, + { 994, 976 }, + { 995, 977 }, + { 997, 979 }, + { 998, 980 }, + { 999, 981 }, + { 1000, 982 }, + { 1012, 1010 }, + { 1013, 1011 }, + { 1017, 1018 }, + { 1031, 1028 }, + { 1032, 1029 }, + { 1033, 1030 }, + { 1034, 1028 }, + { 1035, 1029 }, + { 1036, 1030 }, + { 1038, 1037 }, + { 1040, 1039 }, + { 1042, 1041 }, + { 1044, 1043 }, + { 1045, 1043 }, + { 1047, 1046 }, + { 1048, 1046 }, + { 1050, 1049 }, + { 1051, 1049 }, + { 1053, 1052 }, + { 1062, 1058 }, + { 1063, 1059 }, + { 1064, 1060 }, + { 1065, 1061 }, + { 1067, 1058 }, + { 1068, 1059 }, + { 1069, 1060 }, + { 1070, 1061 }, + { 1072, 1071 }, + { 1074, 1073 }, + { 1076, 1075 }, + { 1078, 1077 }, + { 1080, 1079 }, + { 1081, 1079 }, + { 1083, 1082 }, + { 1084, 1082 }, + { 1086, 1085 }, + { 1087, 1085 }, + { 1089, 1088 }, + { 1091, 1090 }, + { 1098, 1092 }, + { 1099, 1093 }, + { 1100, 1094 }, + { 1101, 1095 }, + { 1102, 1096 }, + { 1103, 1097 }, + { 1104, 1092 }, + { 1105, 1093 }, + { 1106, 1094 }, + { 1107, 1095 }, + { 1108, 1096 }, + { 1109, 1097 }, + { 1122, 1116 }, + { 1123, 1117 }, + { 1124, 1118 }, + { 1125, 1119 }, + { 1126, 1120 }, + { 1127, 1121 }, + { 1128, 1116 }, + { 1129, 1117 }, + { 1130, 1118 }, + { 1131, 1119 }, + { 1132, 1120 }, + { 1133, 1121 }, + { 1150, 1149 }, + { 1151, 1149 }, + { 1153, 1152 }, + { 1154, 1152 }, + { 1161, 1163 }, + { 1162, 1163 }, + { 1164, 1166 }, + { 1165, 1166 }, + { 1174, 1168 }, + { 1175, 1169 }, + { 1176, 1170 }, + { 1177, 1171 }, + { 1178, 1172 }, + { 1179, 1173 }, + { 1180, 1168 }, + { 1181, 1169 }, + { 1182, 1170 }, + { 1183, 1171 }, + { 1184, 1172 }, + { 1185, 1173 }, + { 1198, 1192 }, + { 1199, 1193 }, + { 1200, 1194 }, + { 1201, 1195 }, + { 1202, 1196 }, + { 1203, 1197 }, + { 1204, 1192 }, + { 1205, 1193 }, + { 1206, 1194 }, + { 1207, 1195 }, + { 1208, 1196 }, + { 1209, 1197 }, + { 1229, 1223 }, + { 1230, 1224 }, + { 1231, 1225 }, + { 1232, 1226 }, + { 1233, 1227 }, + { 1234, 1228 }, + { 1235, 1223 }, + { 1236, 1224 }, + { 1237, 1225 }, + { 1238, 1226 }, + { 1239, 1227 }, + { 1240, 1228 }, + { 1254, 1248 }, + { 1255, 1249 }, + { 1256, 1250 }, + { 1257, 1251 }, + { 1258, 1252 }, + { 1259, 1253 }, + { 1260, 1248 }, + { 1261, 1249 }, + { 1262, 1250 }, + { 1263, 1251 }, + { 1264, 1252 }, + { 1265, 1253 }, + { 1286, 1277 }, + { 1287, 1278 }, + { 1288, 1279 }, + { 1289, 1280 }, + { 1290, 1281 }, + { 1291, 1282 }, + { 1292, 1283 }, + { 1293, 1284 }, + { 1294, 1285 }, + { 1295, 1277 }, + { 1297, 1279 }, + { 1298, 1280 }, + { 1300, 1282 }, + { 1301, 1283 }, + { 1302, 1284 }, + { 1303, 1285 }, + { 1314, 1316 }, + { 1315, 1316 }, + { 1351, 1350 }, + { 1352, 1350 }, + { 1359, 1353 }, + { 1360, 1354 }, + { 1361, 1355 }, + { 1362, 1356 }, + { 1363, 1357 }, + { 1364, 1358 }, + { 1365, 1353 }, + { 1366, 1354 }, + { 1367, 1355 }, + { 1368, 1356 }, + { 1369, 1357 }, + { 1370, 1358 }, + { 1381, 1377 }, + { 1382, 1378 }, + { 1383, 1379 }, + { 1384, 1380 }, + { 1385, 1377 }, + { 1386, 1378 }, + { 1387, 1379 }, + { 1388, 1380 }, + { 1399, 1393 }, + { 1400, 1394 }, + { 1401, 1395 }, + { 1402, 1396 }, + { 1403, 1397 }, + { 1404, 1398 }, + { 1405, 1393 }, + { 1406, 1394 }, + { 1407, 1395 }, + { 1408, 1396 }, + { 1409, 1397 }, + { 1410, 1398 }, + { 1421, 1417 }, + { 1422, 1418 }, + { 1423, 1419 }, + { 1424, 1420 }, + { 1425, 1417 }, + { 1426, 1418 }, + { 1427, 1419 }, + { 1428, 1420 }, + { 1434, 1433 }, + { 1435, 1433 }, + { 1439, 1438 }, + { 1440, 1438 }, + { 1445, 1444 }, + { 1446, 1444 }, + { 1453, 1455 }, + { 1454, 1455 }, + { 1457, 1456 }, + { 1458, 1456 }, + { 1469, 1460 }, + { 1470, 1461 }, + { 1471, 1462 }, + { 1472, 1463 }, + { 1473, 1464 }, + { 1474, 1465 }, + { 1475, 1466 }, + { 1476, 1467 }, + { 1477, 1468 }, + { 1478, 1460 }, + { 1480, 1462 }, + { 1481, 1463 }, + { 1483, 1465 }, + { 1484, 1466 }, + { 1485, 1467 }, + { 1486, 1468 }, + { 1514, 1507 }, + { 1515, 1508 }, + { 1516, 1509 }, + { 1517, 1510 }, + { 1518, 1511 }, + { 1519, 1512 }, + { 1520, 1513 }, + { 1521, 1507 }, + { 1524, 1510 }, + { 1527, 1513 }, + { 1538, 1536 }, + { 1539, 1537 }, + { 1540, 1536 }, + { 1541, 1537 }, + { 1550, 1549 }, + { 1551, 1549 }, + { 1595, 1593 }, + { 1596, 1594 }, + { 1597, 1593 }, + { 1598, 1594 }, + { 1604, 1601 }, + { 1605, 1602 }, + { 1606, 1603 }, + { 1607, 1601 }, + { 1608, 1602 }, + { 1609, 1603 }, + { 1628, 1619 }, + { 1629, 1620 }, + { 1630, 1621 }, + { 1631, 1622 }, + { 1632, 1623 }, + { 1633, 1624 }, + { 1634, 1625 }, + { 1635, 1626 }, + { 1636, 1627 }, + { 1637, 1619 }, + { 1639, 1621 }, + { 1640, 1622 }, + { 1642, 1624 }, + { 1643, 1625 }, + { 1644, 1626 }, + { 1645, 1627 }, +}; + +static const uint16_t x86_16_bit_eq_lookup[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 0, + 11, + 12, + 0, + 13, + 14, + 15, + 16, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 0, + 27, + 28, + 0, + 29, + 30, + 31, + 32, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 0, + 43, + 44, + 0, + 45, + 46, + 47, + 48, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 49, + 0, + 0, + 50, + 51, + 52, + 53, + 0, + 0, + 54, + 55, + 56, + 57, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 58, + 59, + 60, + 61, + 62, + 63, + 64, + 65, + 0, + 0, + 0, + 0, + 66, + 67, + 68, + 69, + 70, + 71, + 72, + 73, + 0, + 0, + 0, + 0, + 74, + 75, + 76, + 77, + 78, + 79, + 80, + 81, + 0, + 0, + 0, + 0, + 82, + 83, + 84, + 85, + 86, + 87, + 88, + 89, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 90, + 91, + 92, + 93, + 94, + 95, + 0, + 96, + 97, + 0, + 98, + 0, + 0, + 0, + 0, + 0, + 99, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 100, + 101, + 102, + 103, + 0, + 0, + 104, + 105, + 106, + 107, + 0, + 0, + 108, + 109, + 110, + 111, + 0, + 0, + 112, + 113, + 114, + 115, + 0, + 0, + 116, + 117, + 118, + 119, + 0, + 0, + 120, + 121, + 122, + 123, + 0, + 0, + 124, + 125, + 126, + 127, + 0, + 0, + 128, + 129, + 130, + 131, + 0, + 0, + 132, + 133, + 134, + 135, + 0, + 0, + 136, + 137, + 138, + 139, + 0, + 0, + 140, + 141, + 142, + 143, + 0, + 0, + 144, + 145, + 146, + 147, + 0, + 0, + 148, + 149, + 150, + 151, + 0, + 0, + 152, + 153, + 154, + 155, + 0, + 0, + 156, + 157, + 158, + 159, + 0, + 0, + 160, + 161, + 162, + 163, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 164, + 165, + 166, + 167, + 168, + 169, + 170, + 171, + 172, + 173, + 0, + 174, + 175, + 0, + 176, + 177, + 178, + 179, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 180, + 181, + 0, + 0, + 0, + 0, + 182, + 183, + 184, + 185, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 186, + 187, + 188, + 189, + 190, + 0, + 0, + 0, + 0, + 191, + 192, + 193, + 194, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 195, + 196, + 0, + 0, + 0, + 197, + 198, + 0, + 0, + 0, + 0, + 0, + 0, + 199, + 200, + 201, + 202, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 203, + 204, + 205, + 206, + 207, + 208, + 209, + 210, + 211, + 212, + 213, + 0, + 214, + 215, + 0, + 216, + 0, + 0, + 0, + 0, + 217, + 218, + 0, + 0, + 0, + 0, + 0, + 219, + 220, + 221, + 222, + 223, + 0, + 0, + 0, + 0, + 0, + 224, + 0, + 0, + 0, + 225, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 226, + 227, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 228, + 229, + 230, + 231, + 232, + 233, + 234, + 235, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 236, + 237, + 238, + 239, + 0, + 240, + 0, + 241, + 0, + 242, + 0, + 0, + 0, + 243, + 0, + 244, + 245, + 0, + 246, + 247, + 0, + 248, + 249, + 0, + 250, + 251, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 252, + 253, + 0, + 0, + 0, + 0, + 254, + 255, + 0, + 256, + 257, + 0, + 0, + 0, + 258, + 259, + 260, + 261, + 0, + 262, + 263, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 264, + 265, + 266, + 267, + 0, + 0, + 0, + 268, + 269, + 0, + 0, + 0, + 0, + 270, + 271, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 272, + 273, + 276, + 0, + 0, + 279, + 280, + 281, + 282, + 285, + 0, + 0, + 288, + 289, + 290, + 291, + 292, + 293, + 294, + 295, + 297, + 0, + 0, + 0, + 299, + 300, + 302, + 0, + 0, + 304, + 0, + 305, + 306, + 307, + 308, + 309, + 0, + 310, + 311, + 0, + 0, + 0, + 0, + 312, + 313, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 314, + 315, + 316, + 317, + 0, + 318, + 319, + 0, + 0, + 0, + 320, + 321, + 0, + 0, + 0, + 0, + 0, + 322, + 323, + 0, + 324, + 325, + 0, + 326, + 327, + 329, + 330, + 331, + 333, + 0, + 0, + 0, + 0, + 334, + 335, + 0, + 336, + 337, + 0, + 338, + 339, + 340, + 341, + 0, + 0, + 342, + 343, + 344, + 345, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 346, + 347, + 348, + 349, + 0, + 0, + 0, + 350, + 0, + 0, + 0, + 351, + 0, + 0, + 0, + 352, + 0, + 0, + 0, + 353, + 0, + 0, + 0, + 0, + 354, + 355, + 356, + 357, + 358, + 359, + 360, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 361, + 362, + 363, + 364, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 365, + 366, + 367, + 368, + 369, + 370, + 371, + 372, + 373, + 374, + 0, + 375, + 376, + 0, + 377, + 378, + 379, + 380, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 381, + 382, + 0, + 0, + 0, + 383, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 384, + 385, + 386, + 387, + 388, + 389, + 0, + 390, + 0, + 391, + 0, + 392, + 0, + 393, + 394, + 0, + 395, + 396, + 0, + 397, + 398, + 0, + 399, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 400, + 401, + 402, + 403, + 0, + 404, + 405, + 406, + 407, + 0, + 408, + 0, + 409, + 0, + 410, + 0, + 411, + 0, + 412, + 413, + 0, + 414, + 415, + 0, + 416, + 417, + 0, + 418, + 0, + 419, + 0, + 0, + 0, + 0, + 0, + 0, + 420, + 421, + 422, + 423, + 424, + 425, + 426, + 427, + 428, + 429, + 430, + 431, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 432, + 433, + 434, + 435, + 436, + 437, + 438, + 439, + 440, + 441, + 442, + 443, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 444, + 445, + 0, + 446, + 447, + 0, + 0, + 0, + 0, + 0, + 0, + 448, + 449, + 0, + 450, + 451, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 452, + 453, + 454, + 455, + 456, + 457, + 458, + 459, + 460, + 461, + 462, + 463, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 464, + 465, + 466, + 467, + 468, + 469, + 470, + 471, + 472, + 473, + 474, + 475, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 476, + 477, + 478, + 479, + 480, + 481, + 482, + 483, + 484, + 485, + 486, + 487, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 488, + 489, + 490, + 491, + 492, + 493, + 494, + 495, + 496, + 497, + 498, + 499, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 500, + 501, + 502, + 503, + 504, + 505, + 506, + 507, + 508, + 509, + 0, + 510, + 511, + 0, + 512, + 513, + 514, + 515, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 516, + 517, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 518, + 519, + 0, + 0, + 0, + 0, + 0, + 0, + 520, + 521, + 522, + 523, + 524, + 525, + 526, + 527, + 528, + 529, + 530, + 531, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 532, + 533, + 534, + 535, + 536, + 537, + 538, + 539, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 540, + 541, + 542, + 543, + 544, + 545, + 546, + 547, + 548, + 549, + 550, + 551, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 552, + 553, + 554, + 555, + 556, + 557, + 558, + 559, + 0, + 0, + 0, + 0, + 0, + 560, + 561, + 0, + 0, + 0, + 562, + 563, + 0, + 0, + 0, + 0, + 564, + 565, + 0, + 0, + 0, + 0, + 0, + 0, + 566, + 567, + 0, + 0, + 568, + 569, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 570, + 571, + 572, + 573, + 574, + 575, + 576, + 577, + 578, + 579, + 0, + 580, + 581, + 0, + 582, + 583, + 584, + 585, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 586, + 587, + 588, + 589, + 590, + 591, + 592, + 593, + 0, + 0, + 594, + 0, + 0, + 595, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 596, + 597, + 598, + 599, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 600, + 601, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 602, + 603, + 604, + 605, + 0, + 0, + 0, + 0, + 0, + 606, + 607, + 608, + 609, + 610, + 611, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 612, + 613, + 614, + 615, + 616, + 617, + 618, + 619, + 620, + 621, + 0, + 622, + 623, + 0, + 624, + 625, + 626, + 627, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; diff --git a/thirdparty/capstone/arch/X86/X86Mapping.c b/thirdparty/capstone/arch/X86/X86Mapping.c new file mode 100644 index 0000000..46ecfcb --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86Mapping.c @@ -0,0 +1,2270 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +#ifdef CAPSTONE_HAS_X86 + +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#endif + +#include +#ifndef CAPSTONE_HAS_OSXKERNEL +#include +#endif + +#include "../../Mapping.h" +#include "../../MCInstPrinter.h" +#include "X86Mapping.h" +#include "X86DisassemblerDecoder.h" + +#include "../../utils.h" + + +const uint64_t arch_masks[9] = { + 0, 0xff, + 0xffff, // 16bit + 0, + 0xffffffff, // 32bit + 0, 0, 0, + 0xffffffffffffffffLL // 64bit +}; + +static const x86_reg sib_base_map[] = { + X86_REG_INVALID, +#define ENTRY(x) X86_REG_##x, + ALL_SIB_BASES +#undef ENTRY +}; + +// Fill-ins to make the compiler happy. These constants are never actually +// assigned; they are just filler to make an automatically-generated switch +// statement work. +enum { + X86_REG_BX_SI = 500, + X86_REG_BX_DI = 501, + X86_REG_BP_SI = 502, + X86_REG_BP_DI = 503, + X86_REG_sib = 504, + X86_REG_sib64 = 505 +}; + +static const x86_reg sib_index_map[] = { + X86_REG_INVALID, +#define ENTRY(x) X86_REG_##x, + ALL_EA_BASES + REGS_XMM + REGS_YMM + REGS_ZMM +#undef ENTRY +}; + +static const x86_reg segment_map[] = { + X86_REG_INVALID, + X86_REG_CS, + X86_REG_SS, + X86_REG_DS, + X86_REG_ES, + X86_REG_FS, + X86_REG_GS, +}; + +x86_reg x86_map_sib_base(int r) +{ + return sib_base_map[r]; +} + +x86_reg x86_map_sib_index(int r) +{ + return sib_index_map[r]; +} + +x86_reg x86_map_segment(int r) +{ + return segment_map[r]; +} + +#ifndef CAPSTONE_DIET +static const name_map reg_name_maps[] = { + { X86_REG_INVALID, NULL }, + + { X86_REG_AH, "ah" }, + { X86_REG_AL, "al" }, + { X86_REG_AX, "ax" }, + { X86_REG_BH, "bh" }, + { X86_REG_BL, "bl" }, + { X86_REG_BP, "bp" }, + { X86_REG_BPL, "bpl" }, + { X86_REG_BX, "bx" }, + { X86_REG_CH, "ch" }, + { X86_REG_CL, "cl" }, + { X86_REG_CS, "cs" }, + { X86_REG_CX, "cx" }, + { X86_REG_DH, "dh" }, + { X86_REG_DI, "di" }, + { X86_REG_DIL, "dil" }, + { X86_REG_DL, "dl" }, + { X86_REG_DS, "ds" }, + { X86_REG_DX, "dx" }, + { X86_REG_EAX, "eax" }, + { X86_REG_EBP, "ebp" }, + { X86_REG_EBX, "ebx" }, + { X86_REG_ECX, "ecx" }, + { X86_REG_EDI, "edi" }, + { X86_REG_EDX, "edx" }, + { X86_REG_EFLAGS, "flags" }, + { X86_REG_EIP, "eip" }, + { X86_REG_EIZ, "eiz" }, + { X86_REG_ES, "es" }, + { X86_REG_ESI, "esi" }, + { X86_REG_ESP, "esp" }, + { X86_REG_FPSW, "fpsw" }, + { X86_REG_FS, "fs" }, + { X86_REG_GS, "gs" }, + { X86_REG_IP, "ip" }, + { X86_REG_RAX, "rax" }, + { X86_REG_RBP, "rbp" }, + { X86_REG_RBX, "rbx" }, + { X86_REG_RCX, "rcx" }, + { X86_REG_RDI, "rdi" }, + { X86_REG_RDX, "rdx" }, + { X86_REG_RIP, "rip" }, + { X86_REG_RIZ, "riz" }, + { X86_REG_RSI, "rsi" }, + { X86_REG_RSP, "rsp" }, + { X86_REG_SI, "si" }, + { X86_REG_SIL, "sil" }, + { X86_REG_SP, "sp" }, + { X86_REG_SPL, "spl" }, + { X86_REG_SS, "ss" }, + { X86_REG_CR0, "cr0" }, + { X86_REG_CR1, "cr1" }, + { X86_REG_CR2, "cr2" }, + { X86_REG_CR3, "cr3" }, + { X86_REG_CR4, "cr4" }, + { X86_REG_CR5, "cr5" }, + { X86_REG_CR6, "cr6" }, + { X86_REG_CR7, "cr7" }, + { X86_REG_CR8, "cr8" }, + { X86_REG_CR9, "cr9" }, + { X86_REG_CR10, "cr10" }, + { X86_REG_CR11, "cr11" }, + { X86_REG_CR12, "cr12" }, + { X86_REG_CR13, "cr13" }, + { X86_REG_CR14, "cr14" }, + { X86_REG_CR15, "cr15" }, + { X86_REG_DR0, "dr0" }, + { X86_REG_DR1, "dr1" }, + { X86_REG_DR2, "dr2" }, + { X86_REG_DR3, "dr3" }, + { X86_REG_DR4, "dr4" }, + { X86_REG_DR5, "dr5" }, + { X86_REG_DR6, "dr6" }, + { X86_REG_DR7, "dr7" }, + { X86_REG_DR8, "dr8" }, + { X86_REG_DR9, "dr9" }, + { X86_REG_DR10, "dr10" }, + { X86_REG_DR11, "dr11" }, + { X86_REG_DR12, "dr12" }, + { X86_REG_DR13, "dr13" }, + { X86_REG_DR14, "dr14" }, + { X86_REG_DR15, "dr15" }, + { X86_REG_FP0, "fp0" }, + { X86_REG_FP1, "fp1" }, + { X86_REG_FP2, "fp2" }, + { X86_REG_FP3, "fp3" }, + { X86_REG_FP4, "fp4" }, + { X86_REG_FP5, "fp5" }, + { X86_REG_FP6, "fp6" }, + { X86_REG_FP7, "fp7" }, + { X86_REG_K0, "k0" }, + { X86_REG_K1, "k1" }, + { X86_REG_K2, "k2" }, + { X86_REG_K3, "k3" }, + { X86_REG_K4, "k4" }, + { X86_REG_K5, "k5" }, + { X86_REG_K6, "k6" }, + { X86_REG_K7, "k7" }, + { X86_REG_MM0, "mm0" }, + { X86_REG_MM1, "mm1" }, + { X86_REG_MM2, "mm2" }, + { X86_REG_MM3, "mm3" }, + { X86_REG_MM4, "mm4" }, + { X86_REG_MM5, "mm5" }, + { X86_REG_MM6, "mm6" }, + { X86_REG_MM7, "mm7" }, + { X86_REG_R8, "r8" }, + { X86_REG_R9, "r9" }, + { X86_REG_R10, "r10" }, + { X86_REG_R11, "r11" }, + { X86_REG_R12, "r12" }, + { X86_REG_R13, "r13" }, + { X86_REG_R14, "r14" }, + { X86_REG_R15, "r15" }, + { X86_REG_ST0, "st(0)" }, + { X86_REG_ST1, "st(1)" }, + { X86_REG_ST2, "st(2)" }, + { X86_REG_ST3, "st(3)" }, + { X86_REG_ST4, "st(4)" }, + { X86_REG_ST5, "st(5)" }, + { X86_REG_ST6, "st(6)" }, + { X86_REG_ST7, "st(7)" }, + { X86_REG_XMM0, "xmm0" }, + { X86_REG_XMM1, "xmm1" }, + { X86_REG_XMM2, "xmm2" }, + { X86_REG_XMM3, "xmm3" }, + { X86_REG_XMM4, "xmm4" }, + { X86_REG_XMM5, "xmm5" }, + { X86_REG_XMM6, "xmm6" }, + { X86_REG_XMM7, "xmm7" }, + { X86_REG_XMM8, "xmm8" }, + { X86_REG_XMM9, "xmm9" }, + { X86_REG_XMM10, "xmm10" }, + { X86_REG_XMM11, "xmm11" }, + { X86_REG_XMM12, "xmm12" }, + { X86_REG_XMM13, "xmm13" }, + { X86_REG_XMM14, "xmm14" }, + { X86_REG_XMM15, "xmm15" }, + { X86_REG_XMM16, "xmm16" }, + { X86_REG_XMM17, "xmm17" }, + { X86_REG_XMM18, "xmm18" }, + { X86_REG_XMM19, "xmm19" }, + { X86_REG_XMM20, "xmm20" }, + { X86_REG_XMM21, "xmm21" }, + { X86_REG_XMM22, "xmm22" }, + { X86_REG_XMM23, "xmm23" }, + { X86_REG_XMM24, "xmm24" }, + { X86_REG_XMM25, "xmm25" }, + { X86_REG_XMM26, "xmm26" }, + { X86_REG_XMM27, "xmm27" }, + { X86_REG_XMM28, "xmm28" }, + { X86_REG_XMM29, "xmm29" }, + { X86_REG_XMM30, "xmm30" }, + { X86_REG_XMM31, "xmm31" }, + { X86_REG_YMM0, "ymm0" }, + { X86_REG_YMM1, "ymm1" }, + { X86_REG_YMM2, "ymm2" }, + { X86_REG_YMM3, "ymm3" }, + { X86_REG_YMM4, "ymm4" }, + { X86_REG_YMM5, "ymm5" }, + { X86_REG_YMM6, "ymm6" }, + { X86_REG_YMM7, "ymm7" }, + { X86_REG_YMM8, "ymm8" }, + { X86_REG_YMM9, "ymm9" }, + { X86_REG_YMM10, "ymm10" }, + { X86_REG_YMM11, "ymm11" }, + { X86_REG_YMM12, "ymm12" }, + { X86_REG_YMM13, "ymm13" }, + { X86_REG_YMM14, "ymm14" }, + { X86_REG_YMM15, "ymm15" }, + { X86_REG_YMM16, "ymm16" }, + { X86_REG_YMM17, "ymm17" }, + { X86_REG_YMM18, "ymm18" }, + { X86_REG_YMM19, "ymm19" }, + { X86_REG_YMM20, "ymm20" }, + { X86_REG_YMM21, "ymm21" }, + { X86_REG_YMM22, "ymm22" }, + { X86_REG_YMM23, "ymm23" }, + { X86_REG_YMM24, "ymm24" }, + { X86_REG_YMM25, "ymm25" }, + { X86_REG_YMM26, "ymm26" }, + { X86_REG_YMM27, "ymm27" }, + { X86_REG_YMM28, "ymm28" }, + { X86_REG_YMM29, "ymm29" }, + { X86_REG_YMM30, "ymm30" }, + { X86_REG_YMM31, "ymm31" }, + { X86_REG_ZMM0, "zmm0" }, + { X86_REG_ZMM1, "zmm1" }, + { X86_REG_ZMM2, "zmm2" }, + { X86_REG_ZMM3, "zmm3" }, + { X86_REG_ZMM4, "zmm4" }, + { X86_REG_ZMM5, "zmm5" }, + { X86_REG_ZMM6, "zmm6" }, + { X86_REG_ZMM7, "zmm7" }, + { X86_REG_ZMM8, "zmm8" }, + { X86_REG_ZMM9, "zmm9" }, + { X86_REG_ZMM10, "zmm10" }, + { X86_REG_ZMM11, "zmm11" }, + { X86_REG_ZMM12, "zmm12" }, + { X86_REG_ZMM13, "zmm13" }, + { X86_REG_ZMM14, "zmm14" }, + { X86_REG_ZMM15, "zmm15" }, + { X86_REG_ZMM16, "zmm16" }, + { X86_REG_ZMM17, "zmm17" }, + { X86_REG_ZMM18, "zmm18" }, + { X86_REG_ZMM19, "zmm19" }, + { X86_REG_ZMM20, "zmm20" }, + { X86_REG_ZMM21, "zmm21" }, + { X86_REG_ZMM22, "zmm22" }, + { X86_REG_ZMM23, "zmm23" }, + { X86_REG_ZMM24, "zmm24" }, + { X86_REG_ZMM25, "zmm25" }, + { X86_REG_ZMM26, "zmm26" }, + { X86_REG_ZMM27, "zmm27" }, + { X86_REG_ZMM28, "zmm28" }, + { X86_REG_ZMM29, "zmm29" }, + { X86_REG_ZMM30, "zmm30" }, + { X86_REG_ZMM31, "zmm31" }, + { X86_REG_R8B, "r8b" }, + { X86_REG_R9B, "r9b" }, + { X86_REG_R10B, "r10b" }, + { X86_REG_R11B, "r11b" }, + { X86_REG_R12B, "r12b" }, + { X86_REG_R13B, "r13b" }, + { X86_REG_R14B, "r14b" }, + { X86_REG_R15B, "r15b" }, + { X86_REG_R8D, "r8d" }, + { X86_REG_R9D, "r9d" }, + { X86_REG_R10D, "r10d" }, + { X86_REG_R11D, "r11d" }, + { X86_REG_R12D, "r12d" }, + { X86_REG_R13D, "r13d" }, + { X86_REG_R14D, "r14d" }, + { X86_REG_R15D, "r15d" }, + { X86_REG_R8W, "r8w" }, + { X86_REG_R9W, "r9w" }, + { X86_REG_R10W, "r10w" }, + { X86_REG_R11W, "r11w" }, + { X86_REG_R12W, "r12w" }, + { X86_REG_R13W, "r13w" }, + { X86_REG_R14W, "r14w" }, + { X86_REG_R15W, "r15w" }, + + { X86_REG_BND0, "bnd0" }, + { X86_REG_BND1, "bnd1" }, + { X86_REG_BND2, "bnd2" }, + { X86_REG_BND3, "bnd3" }, +}; +#endif + +// register size in non-64bit mode +const uint8_t regsize_map_32 [] = { + 0, // { X86_REG_INVALID, NULL }, + 1, // { X86_REG_AH, "ah" }, + 1, // { X86_REG_AL, "al" }, + 2, // { X86_REG_AX, "ax" }, + 1, // { X86_REG_BH, "bh" }, + 1, // { X86_REG_BL, "bl" }, + 2, // { X86_REG_BP, "bp" }, + 1, // { X86_REG_BPL, "bpl" }, + 2, // { X86_REG_BX, "bx" }, + 1, // { X86_REG_CH, "ch" }, + 1, // { X86_REG_CL, "cl" }, + 2, // { X86_REG_CS, "cs" }, + 2, // { X86_REG_CX, "cx" }, + 1, // { X86_REG_DH, "dh" }, + 2, // { X86_REG_DI, "di" }, + 1, // { X86_REG_DIL, "dil" }, + 1, // { X86_REG_DL, "dl" }, + 2, // { X86_REG_DS, "ds" }, + 2, // { X86_REG_DX, "dx" }, + 4, // { X86_REG_EAX, "eax" }, + 4, // { X86_REG_EBP, "ebp" }, + 4, // { X86_REG_EBX, "ebx" }, + 4, // { X86_REG_ECX, "ecx" }, + 4, // { X86_REG_EDI, "edi" }, + 4, // { X86_REG_EDX, "edx" }, + 4, // { X86_REG_EFLAGS, "flags" }, + 4, // { X86_REG_EIP, "eip" }, + 4, // { X86_REG_EIZ, "eiz" }, + 2, // { X86_REG_ES, "es" }, + 4, // { X86_REG_ESI, "esi" }, + 4, // { X86_REG_ESP, "esp" }, + 10, // { X86_REG_FPSW, "fpsw" }, + 2, // { X86_REG_FS, "fs" }, + 2, // { X86_REG_GS, "gs" }, + 2, // { X86_REG_IP, "ip" }, + 8, // { X86_REG_RAX, "rax" }, + 8, // { X86_REG_RBP, "rbp" }, + 8, // { X86_REG_RBX, "rbx" }, + 8, // { X86_REG_RCX, "rcx" }, + 8, // { X86_REG_RDI, "rdi" }, + 8, // { X86_REG_RDX, "rdx" }, + 8, // { X86_REG_RIP, "rip" }, + 8, // { X86_REG_RIZ, "riz" }, + 8, // { X86_REG_RSI, "rsi" }, + 8, // { X86_REG_RSP, "rsp" }, + 2, // { X86_REG_SI, "si" }, + 1, // { X86_REG_SIL, "sil" }, + 2, // { X86_REG_SP, "sp" }, + 1, // { X86_REG_SPL, "spl" }, + 2, // { X86_REG_SS, "ss" }, + 4, // { X86_REG_CR0, "cr0" }, + 4, // { X86_REG_CR1, "cr1" }, + 4, // { X86_REG_CR2, "cr2" }, + 4, // { X86_REG_CR3, "cr3" }, + 4, // { X86_REG_CR4, "cr4" }, + 8, // { X86_REG_CR5, "cr5" }, + 8, // { X86_REG_CR6, "cr6" }, + 8, // { X86_REG_CR7, "cr7" }, + 8, // { X86_REG_CR8, "cr8" }, + 8, // { X86_REG_CR9, "cr9" }, + 8, // { X86_REG_CR10, "cr10" }, + 8, // { X86_REG_CR11, "cr11" }, + 8, // { X86_REG_CR12, "cr12" }, + 8, // { X86_REG_CR13, "cr13" }, + 8, // { X86_REG_CR14, "cr14" }, + 8, // { X86_REG_CR15, "cr15" }, + 4, // { X86_REG_DR0, "dr0" }, + 4, // { X86_REG_DR1, "dr1" }, + 4, // { X86_REG_DR2, "dr2" }, + 4, // { X86_REG_DR3, "dr3" }, + 4, // { X86_REG_DR4, "dr4" }, + 4, // { X86_REG_DR5, "dr5" }, + 4, // { X86_REG_DR6, "dr6" }, + 4, // { X86_REG_DR7, "dr7" }, + 4, // { X86_REG_DR8, "dr8" }, + 4, // { X86_REG_DR9, "dr9" }, + 4, // { X86_REG_DR10, "dr10" }, + 4, // { X86_REG_DR11, "dr11" }, + 4, // { X86_REG_DR12, "dr12" }, + 4, // { X86_REG_DR13, "dr13" }, + 4, // { X86_REG_DR14, "dr14" }, + 4, // { X86_REG_DR15, "dr15" }, + 10, // { X86_REG_FP0, "fp0" }, + 10, // { X86_REG_FP1, "fp1" }, + 10, // { X86_REG_FP2, "fp2" }, + 10, // { X86_REG_FP3, "fp3" }, + 10, // { X86_REG_FP4, "fp4" }, + 10, // { X86_REG_FP5, "fp5" }, + 10, // { X86_REG_FP6, "fp6" }, + 10, // { X86_REG_FP7, "fp7" }, + 2, // { X86_REG_K0, "k0" }, + 2, // { X86_REG_K1, "k1" }, + 2, // { X86_REG_K2, "k2" }, + 2, // { X86_REG_K3, "k3" }, + 2, // { X86_REG_K4, "k4" }, + 2, // { X86_REG_K5, "k5" }, + 2, // { X86_REG_K6, "k6" }, + 2, // { X86_REG_K7, "k7" }, + 8, // { X86_REG_MM0, "mm0" }, + 8, // { X86_REG_MM1, "mm1" }, + 8, // { X86_REG_MM2, "mm2" }, + 8, // { X86_REG_MM3, "mm3" }, + 8, // { X86_REG_MM4, "mm4" }, + 8, // { X86_REG_MM5, "mm5" }, + 8, // { X86_REG_MM6, "mm6" }, + 8, // { X86_REG_MM7, "mm7" }, + 8, // { X86_REG_R8, "r8" }, + 8, // { X86_REG_R9, "r9" }, + 8, // { X86_REG_R10, "r10" }, + 8, // { X86_REG_R11, "r11" }, + 8, // { X86_REG_R12, "r12" }, + 8, // { X86_REG_R13, "r13" }, + 8, // { X86_REG_R14, "r14" }, + 8, // { X86_REG_R15, "r15" }, + 10, // { X86_REG_ST0, "st0" }, + 10, // { X86_REG_ST1, "st1" }, + 10, // { X86_REG_ST2, "st2" }, + 10, // { X86_REG_ST3, "st3" }, + 10, // { X86_REG_ST4, "st4" }, + 10, // { X86_REG_ST5, "st5" }, + 10, // { X86_REG_ST6, "st6" }, + 10, // { X86_REG_ST7, "st7" }, + 16, // { X86_REG_XMM0, "xmm0" }, + 16, // { X86_REG_XMM1, "xmm1" }, + 16, // { X86_REG_XMM2, "xmm2" }, + 16, // { X86_REG_XMM3, "xmm3" }, + 16, // { X86_REG_XMM4, "xmm4" }, + 16, // { X86_REG_XMM5, "xmm5" }, + 16, // { X86_REG_XMM6, "xmm6" }, + 16, // { X86_REG_XMM7, "xmm7" }, + 16, // { X86_REG_XMM8, "xmm8" }, + 16, // { X86_REG_XMM9, "xmm9" }, + 16, // { X86_REG_XMM10, "xmm10" }, + 16, // { X86_REG_XMM11, "xmm11" }, + 16, // { X86_REG_XMM12, "xmm12" }, + 16, // { X86_REG_XMM13, "xmm13" }, + 16, // { X86_REG_XMM14, "xmm14" }, + 16, // { X86_REG_XMM15, "xmm15" }, + 16, // { X86_REG_XMM16, "xmm16" }, + 16, // { X86_REG_XMM17, "xmm17" }, + 16, // { X86_REG_XMM18, "xmm18" }, + 16, // { X86_REG_XMM19, "xmm19" }, + 16, // { X86_REG_XMM20, "xmm20" }, + 16, // { X86_REG_XMM21, "xmm21" }, + 16, // { X86_REG_XMM22, "xmm22" }, + 16, // { X86_REG_XMM23, "xmm23" }, + 16, // { X86_REG_XMM24, "xmm24" }, + 16, // { X86_REG_XMM25, "xmm25" }, + 16, // { X86_REG_XMM26, "xmm26" }, + 16, // { X86_REG_XMM27, "xmm27" }, + 16, // { X86_REG_XMM28, "xmm28" }, + 16, // { X86_REG_XMM29, "xmm29" }, + 16, // { X86_REG_XMM30, "xmm30" }, + 16, // { X86_REG_XMM31, "xmm31" }, + 32, // { X86_REG_YMM0, "ymm0" }, + 32, // { X86_REG_YMM1, "ymm1" }, + 32, // { X86_REG_YMM2, "ymm2" }, + 32, // { X86_REG_YMM3, "ymm3" }, + 32, // { X86_REG_YMM4, "ymm4" }, + 32, // { X86_REG_YMM5, "ymm5" }, + 32, // { X86_REG_YMM6, "ymm6" }, + 32, // { X86_REG_YMM7, "ymm7" }, + 32, // { X86_REG_YMM8, "ymm8" }, + 32, // { X86_REG_YMM9, "ymm9" }, + 32, // { X86_REG_YMM10, "ymm10" }, + 32, // { X86_REG_YMM11, "ymm11" }, + 32, // { X86_REG_YMM12, "ymm12" }, + 32, // { X86_REG_YMM13, "ymm13" }, + 32, // { X86_REG_YMM14, "ymm14" }, + 32, // { X86_REG_YMM15, "ymm15" }, + 32, // { X86_REG_YMM16, "ymm16" }, + 32, // { X86_REG_YMM17, "ymm17" }, + 32, // { X86_REG_YMM18, "ymm18" }, + 32, // { X86_REG_YMM19, "ymm19" }, + 32, // { X86_REG_YMM20, "ymm20" }, + 32, // { X86_REG_YMM21, "ymm21" }, + 32, // { X86_REG_YMM22, "ymm22" }, + 32, // { X86_REG_YMM23, "ymm23" }, + 32, // { X86_REG_YMM24, "ymm24" }, + 32, // { X86_REG_YMM25, "ymm25" }, + 32, // { X86_REG_YMM26, "ymm26" }, + 32, // { X86_REG_YMM27, "ymm27" }, + 32, // { X86_REG_YMM28, "ymm28" }, + 32, // { X86_REG_YMM29, "ymm29" }, + 32, // { X86_REG_YMM30, "ymm30" }, + 32, // { X86_REG_YMM31, "ymm31" }, + 64, // { X86_REG_ZMM0, "zmm0" }, + 64, // { X86_REG_ZMM1, "zmm1" }, + 64, // { X86_REG_ZMM2, "zmm2" }, + 64, // { X86_REG_ZMM3, "zmm3" }, + 64, // { X86_REG_ZMM4, "zmm4" }, + 64, // { X86_REG_ZMM5, "zmm5" }, + 64, // { X86_REG_ZMM6, "zmm6" }, + 64, // { X86_REG_ZMM7, "zmm7" }, + 64, // { X86_REG_ZMM8, "zmm8" }, + 64, // { X86_REG_ZMM9, "zmm9" }, + 64, // { X86_REG_ZMM10, "zmm10" }, + 64, // { X86_REG_ZMM11, "zmm11" }, + 64, // { X86_REG_ZMM12, "zmm12" }, + 64, // { X86_REG_ZMM13, "zmm13" }, + 64, // { X86_REG_ZMM14, "zmm14" }, + 64, // { X86_REG_ZMM15, "zmm15" }, + 64, // { X86_REG_ZMM16, "zmm16" }, + 64, // { X86_REG_ZMM17, "zmm17" }, + 64, // { X86_REG_ZMM18, "zmm18" }, + 64, // { X86_REG_ZMM19, "zmm19" }, + 64, // { X86_REG_ZMM20, "zmm20" }, + 64, // { X86_REG_ZMM21, "zmm21" }, + 64, // { X86_REG_ZMM22, "zmm22" }, + 64, // { X86_REG_ZMM23, "zmm23" }, + 64, // { X86_REG_ZMM24, "zmm24" }, + 64, // { X86_REG_ZMM25, "zmm25" }, + 64, // { X86_REG_ZMM26, "zmm26" }, + 64, // { X86_REG_ZMM27, "zmm27" }, + 64, // { X86_REG_ZMM28, "zmm28" }, + 64, // { X86_REG_ZMM29, "zmm29" }, + 64, // { X86_REG_ZMM30, "zmm30" }, + 64, // { X86_REG_ZMM31, "zmm31" }, + 1, // { X86_REG_R8B, "r8b" }, + 1, // { X86_REG_R9B, "r9b" }, + 1, // { X86_REG_R10B, "r10b" }, + 1, // { X86_REG_R11B, "r11b" }, + 1, // { X86_REG_R12B, "r12b" }, + 1, // { X86_REG_R13B, "r13b" }, + 1, // { X86_REG_R14B, "r14b" }, + 1, // { X86_REG_R15B, "r15b" }, + 4, // { X86_REG_R8D, "r8d" }, + 4, // { X86_REG_R9D, "r9d" }, + 4, // { X86_REG_R10D, "r10d" }, + 4, // { X86_REG_R11D, "r11d" }, + 4, // { X86_REG_R12D, "r12d" }, + 4, // { X86_REG_R13D, "r13d" }, + 4, // { X86_REG_R14D, "r14d" }, + 4, // { X86_REG_R15D, "r15d" }, + 2, // { X86_REG_R8W, "r8w" }, + 2, // { X86_REG_R9W, "r9w" }, + 2, // { X86_REG_R10W, "r10w" }, + 2, // { X86_REG_R11W, "r11w" }, + 2, // { X86_REG_R12W, "r12w" }, + 2, // { X86_REG_R13W, "r13w" }, + 2, // { X86_REG_R14W, "r14w" }, + 2, // { X86_REG_R15W, "r15w" }, + 16, // { X86_REG_BND0, "bnd0" }, + 16, // { X86_REG_BND1, "bnd0" }, + 16, // { X86_REG_BND2, "bnd0" }, + 16, // { X86_REG_BND3, "bnd0" }, +}; + +// register size in 64bit mode +const uint8_t regsize_map_64 [] = { + 0, // { X86_REG_INVALID, NULL }, + 1, // { X86_REG_AH, "ah" }, + 1, // { X86_REG_AL, "al" }, + 2, // { X86_REG_AX, "ax" }, + 1, // { X86_REG_BH, "bh" }, + 1, // { X86_REG_BL, "bl" }, + 2, // { X86_REG_BP, "bp" }, + 1, // { X86_REG_BPL, "bpl" }, + 2, // { X86_REG_BX, "bx" }, + 1, // { X86_REG_CH, "ch" }, + 1, // { X86_REG_CL, "cl" }, + 2, // { X86_REG_CS, "cs" }, + 2, // { X86_REG_CX, "cx" }, + 1, // { X86_REG_DH, "dh" }, + 2, // { X86_REG_DI, "di" }, + 1, // { X86_REG_DIL, "dil" }, + 1, // { X86_REG_DL, "dl" }, + 2, // { X86_REG_DS, "ds" }, + 2, // { X86_REG_DX, "dx" }, + 4, // { X86_REG_EAX, "eax" }, + 4, // { X86_REG_EBP, "ebp" }, + 4, // { X86_REG_EBX, "ebx" }, + 4, // { X86_REG_ECX, "ecx" }, + 4, // { X86_REG_EDI, "edi" }, + 4, // { X86_REG_EDX, "edx" }, + 8, // { X86_REG_EFLAGS, "flags" }, + 4, // { X86_REG_EIP, "eip" }, + 4, // { X86_REG_EIZ, "eiz" }, + 2, // { X86_REG_ES, "es" }, + 4, // { X86_REG_ESI, "esi" }, + 4, // { X86_REG_ESP, "esp" }, + 10, // { X86_REG_FPSW, "fpsw" }, + 2, // { X86_REG_FS, "fs" }, + 2, // { X86_REG_GS, "gs" }, + 2, // { X86_REG_IP, "ip" }, + 8, // { X86_REG_RAX, "rax" }, + 8, // { X86_REG_RBP, "rbp" }, + 8, // { X86_REG_RBX, "rbx" }, + 8, // { X86_REG_RCX, "rcx" }, + 8, // { X86_REG_RDI, "rdi" }, + 8, // { X86_REG_RDX, "rdx" }, + 8, // { X86_REG_RIP, "rip" }, + 8, // { X86_REG_RIZ, "riz" }, + 8, // { X86_REG_RSI, "rsi" }, + 8, // { X86_REG_RSP, "rsp" }, + 2, // { X86_REG_SI, "si" }, + 1, // { X86_REG_SIL, "sil" }, + 2, // { X86_REG_SP, "sp" }, + 1, // { X86_REG_SPL, "spl" }, + 2, // { X86_REG_SS, "ss" }, + 8, // { X86_REG_CR0, "cr0" }, + 8, // { X86_REG_CR1, "cr1" }, + 8, // { X86_REG_CR2, "cr2" }, + 8, // { X86_REG_CR3, "cr3" }, + 8, // { X86_REG_CR4, "cr4" }, + 8, // { X86_REG_CR5, "cr5" }, + 8, // { X86_REG_CR6, "cr6" }, + 8, // { X86_REG_CR7, "cr7" }, + 8, // { X86_REG_CR8, "cr8" }, + 8, // { X86_REG_CR9, "cr9" }, + 8, // { X86_REG_CR10, "cr10" }, + 8, // { X86_REG_CR11, "cr11" }, + 8, // { X86_REG_CR12, "cr12" }, + 8, // { X86_REG_CR13, "cr13" }, + 8, // { X86_REG_CR14, "cr14" }, + 8, // { X86_REG_CR15, "cr15" }, + 8, // { X86_REG_DR0, "dr0" }, + 8, // { X86_REG_DR1, "dr1" }, + 8, // { X86_REG_DR2, "dr2" }, + 8, // { X86_REG_DR3, "dr3" }, + 8, // { X86_REG_DR4, "dr4" }, + 8, // { X86_REG_DR5, "dr5" }, + 8, // { X86_REG_DR6, "dr6" }, + 8, // { X86_REG_DR7, "dr7" }, + 8, // { X86_REG_DR8, "dr8" }, + 8, // { X86_REG_DR9, "dr9" }, + 8, // { X86_REG_DR10, "dr10" }, + 8, // { X86_REG_DR11, "dr11" }, + 8, // { X86_REG_DR12, "dr12" }, + 8, // { X86_REG_DR13, "dr13" }, + 8, // { X86_REG_DR14, "dr14" }, + 8, // { X86_REG_DR15, "dr15" }, + 10, // { X86_REG_FP0, "fp0" }, + 10, // { X86_REG_FP1, "fp1" }, + 10, // { X86_REG_FP2, "fp2" }, + 10, // { X86_REG_FP3, "fp3" }, + 10, // { X86_REG_FP4, "fp4" }, + 10, // { X86_REG_FP5, "fp5" }, + 10, // { X86_REG_FP6, "fp6" }, + 10, // { X86_REG_FP7, "fp7" }, + 2, // { X86_REG_K0, "k0" }, + 2, // { X86_REG_K1, "k1" }, + 2, // { X86_REG_K2, "k2" }, + 2, // { X86_REG_K3, "k3" }, + 2, // { X86_REG_K4, "k4" }, + 2, // { X86_REG_K5, "k5" }, + 2, // { X86_REG_K6, "k6" }, + 2, // { X86_REG_K7, "k7" }, + 8, // { X86_REG_MM0, "mm0" }, + 8, // { X86_REG_MM1, "mm1" }, + 8, // { X86_REG_MM2, "mm2" }, + 8, // { X86_REG_MM3, "mm3" }, + 8, // { X86_REG_MM4, "mm4" }, + 8, // { X86_REG_MM5, "mm5" }, + 8, // { X86_REG_MM6, "mm6" }, + 8, // { X86_REG_MM7, "mm7" }, + 8, // { X86_REG_R8, "r8" }, + 8, // { X86_REG_R9, "r9" }, + 8, // { X86_REG_R10, "r10" }, + 8, // { X86_REG_R11, "r11" }, + 8, // { X86_REG_R12, "r12" }, + 8, // { X86_REG_R13, "r13" }, + 8, // { X86_REG_R14, "r14" }, + 8, // { X86_REG_R15, "r15" }, + 10, // { X86_REG_ST0, "st0" }, + 10, // { X86_REG_ST1, "st1" }, + 10, // { X86_REG_ST2, "st2" }, + 10, // { X86_REG_ST3, "st3" }, + 10, // { X86_REG_ST4, "st4" }, + 10, // { X86_REG_ST5, "st5" }, + 10, // { X86_REG_ST6, "st6" }, + 10, // { X86_REG_ST7, "st7" }, + 16, // { X86_REG_XMM0, "xmm0" }, + 16, // { X86_REG_XMM1, "xmm1" }, + 16, // { X86_REG_XMM2, "xmm2" }, + 16, // { X86_REG_XMM3, "xmm3" }, + 16, // { X86_REG_XMM4, "xmm4" }, + 16, // { X86_REG_XMM5, "xmm5" }, + 16, // { X86_REG_XMM6, "xmm6" }, + 16, // { X86_REG_XMM7, "xmm7" }, + 16, // { X86_REG_XMM8, "xmm8" }, + 16, // { X86_REG_XMM9, "xmm9" }, + 16, // { X86_REG_XMM10, "xmm10" }, + 16, // { X86_REG_XMM11, "xmm11" }, + 16, // { X86_REG_XMM12, "xmm12" }, + 16, // { X86_REG_XMM13, "xmm13" }, + 16, // { X86_REG_XMM14, "xmm14" }, + 16, // { X86_REG_XMM15, "xmm15" }, + 16, // { X86_REG_XMM16, "xmm16" }, + 16, // { X86_REG_XMM17, "xmm17" }, + 16, // { X86_REG_XMM18, "xmm18" }, + 16, // { X86_REG_XMM19, "xmm19" }, + 16, // { X86_REG_XMM20, "xmm20" }, + 16, // { X86_REG_XMM21, "xmm21" }, + 16, // { X86_REG_XMM22, "xmm22" }, + 16, // { X86_REG_XMM23, "xmm23" }, + 16, // { X86_REG_XMM24, "xmm24" }, + 16, // { X86_REG_XMM25, "xmm25" }, + 16, // { X86_REG_XMM26, "xmm26" }, + 16, // { X86_REG_XMM27, "xmm27" }, + 16, // { X86_REG_XMM28, "xmm28" }, + 16, // { X86_REG_XMM29, "xmm29" }, + 16, // { X86_REG_XMM30, "xmm30" }, + 16, // { X86_REG_XMM31, "xmm31" }, + 32, // { X86_REG_YMM0, "ymm0" }, + 32, // { X86_REG_YMM1, "ymm1" }, + 32, // { X86_REG_YMM2, "ymm2" }, + 32, // { X86_REG_YMM3, "ymm3" }, + 32, // { X86_REG_YMM4, "ymm4" }, + 32, // { X86_REG_YMM5, "ymm5" }, + 32, // { X86_REG_YMM6, "ymm6" }, + 32, // { X86_REG_YMM7, "ymm7" }, + 32, // { X86_REG_YMM8, "ymm8" }, + 32, // { X86_REG_YMM9, "ymm9" }, + 32, // { X86_REG_YMM10, "ymm10" }, + 32, // { X86_REG_YMM11, "ymm11" }, + 32, // { X86_REG_YMM12, "ymm12" }, + 32, // { X86_REG_YMM13, "ymm13" }, + 32, // { X86_REG_YMM14, "ymm14" }, + 32, // { X86_REG_YMM15, "ymm15" }, + 32, // { X86_REG_YMM16, "ymm16" }, + 32, // { X86_REG_YMM17, "ymm17" }, + 32, // { X86_REG_YMM18, "ymm18" }, + 32, // { X86_REG_YMM19, "ymm19" }, + 32, // { X86_REG_YMM20, "ymm20" }, + 32, // { X86_REG_YMM21, "ymm21" }, + 32, // { X86_REG_YMM22, "ymm22" }, + 32, // { X86_REG_YMM23, "ymm23" }, + 32, // { X86_REG_YMM24, "ymm24" }, + 32, // { X86_REG_YMM25, "ymm25" }, + 32, // { X86_REG_YMM26, "ymm26" }, + 32, // { X86_REG_YMM27, "ymm27" }, + 32, // { X86_REG_YMM28, "ymm28" }, + 32, // { X86_REG_YMM29, "ymm29" }, + 32, // { X86_REG_YMM30, "ymm30" }, + 32, // { X86_REG_YMM31, "ymm31" }, + 64, // { X86_REG_ZMM0, "zmm0" }, + 64, // { X86_REG_ZMM1, "zmm1" }, + 64, // { X86_REG_ZMM2, "zmm2" }, + 64, // { X86_REG_ZMM3, "zmm3" }, + 64, // { X86_REG_ZMM4, "zmm4" }, + 64, // { X86_REG_ZMM5, "zmm5" }, + 64, // { X86_REG_ZMM6, "zmm6" }, + 64, // { X86_REG_ZMM7, "zmm7" }, + 64, // { X86_REG_ZMM8, "zmm8" }, + 64, // { X86_REG_ZMM9, "zmm9" }, + 64, // { X86_REG_ZMM10, "zmm10" }, + 64, // { X86_REG_ZMM11, "zmm11" }, + 64, // { X86_REG_ZMM12, "zmm12" }, + 64, // { X86_REG_ZMM13, "zmm13" }, + 64, // { X86_REG_ZMM14, "zmm14" }, + 64, // { X86_REG_ZMM15, "zmm15" }, + 64, // { X86_REG_ZMM16, "zmm16" }, + 64, // { X86_REG_ZMM17, "zmm17" }, + 64, // { X86_REG_ZMM18, "zmm18" }, + 64, // { X86_REG_ZMM19, "zmm19" }, + 64, // { X86_REG_ZMM20, "zmm20" }, + 64, // { X86_REG_ZMM21, "zmm21" }, + 64, // { X86_REG_ZMM22, "zmm22" }, + 64, // { X86_REG_ZMM23, "zmm23" }, + 64, // { X86_REG_ZMM24, "zmm24" }, + 64, // { X86_REG_ZMM25, "zmm25" }, + 64, // { X86_REG_ZMM26, "zmm26" }, + 64, // { X86_REG_ZMM27, "zmm27" }, + 64, // { X86_REG_ZMM28, "zmm28" }, + 64, // { X86_REG_ZMM29, "zmm29" }, + 64, // { X86_REG_ZMM30, "zmm30" }, + 64, // { X86_REG_ZMM31, "zmm31" }, + 1, // { X86_REG_R8B, "r8b" }, + 1, // { X86_REG_R9B, "r9b" }, + 1, // { X86_REG_R10B, "r10b" }, + 1, // { X86_REG_R11B, "r11b" }, + 1, // { X86_REG_R12B, "r12b" }, + 1, // { X86_REG_R13B, "r13b" }, + 1, // { X86_REG_R14B, "r14b" }, + 1, // { X86_REG_R15B, "r15b" }, + 4, // { X86_REG_R8D, "r8d" }, + 4, // { X86_REG_R9D, "r9d" }, + 4, // { X86_REG_R10D, "r10d" }, + 4, // { X86_REG_R11D, "r11d" }, + 4, // { X86_REG_R12D, "r12d" }, + 4, // { X86_REG_R13D, "r13d" }, + 4, // { X86_REG_R14D, "r14d" }, + 4, // { X86_REG_R15D, "r15d" }, + 2, // { X86_REG_R8W, "r8w" }, + 2, // { X86_REG_R9W, "r9w" }, + 2, // { X86_REG_R10W, "r10w" }, + 2, // { X86_REG_R11W, "r11w" }, + 2, // { X86_REG_R12W, "r12w" }, + 2, // { X86_REG_R13W, "r13w" }, + 2, // { X86_REG_R14W, "r14w" }, + 2, // { X86_REG_R15W, "r15w" }, + 16, // { X86_REG_BND0, "bnd0" }, + 16, // { X86_REG_BND1, "bnd0" }, + 16, // { X86_REG_BND2, "bnd0" }, + 16, // { X86_REG_BND3, "bnd0" }, +}; + +const char *X86_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + cs_struct *ud = (cs_struct *)handle; + + if (reg >= ARR_SIZE(reg_name_maps)) + return NULL; + + if (reg == X86_REG_EFLAGS) { + if (ud->mode & CS_MODE_32) + return "eflags"; + if (ud->mode & CS_MODE_64) + return "rflags"; + } + + return reg_name_maps[reg].name; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static const char * const insn_name_maps[] = { + NULL, // X86_INS_INVALID +#ifndef CAPSTONE_X86_REDUCE +#include "X86MappingInsnName.inc" +#else +#include "X86MappingInsnName_reduce.inc" +#endif +}; +#endif + +// NOTE: insn_name_maps[] is sorted in order +const char *X86_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + if (id >= ARR_SIZE(insn_name_maps)) + return NULL; + + return insn_name_maps[id]; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static const name_map group_name_maps[] = { + // generic groups + { X86_GRP_INVALID, NULL }, + { X86_GRP_JUMP, "jump" }, + { X86_GRP_CALL, "call" }, + { X86_GRP_RET, "ret" }, + { X86_GRP_INT, "int" }, + { X86_GRP_IRET, "iret" }, + { X86_GRP_PRIVILEGE, "privilege" }, + { X86_GRP_BRANCH_RELATIVE, "branch_relative" }, + + // architecture-specific groups + { X86_GRP_VM, "vm" }, + { X86_GRP_3DNOW, "3dnow" }, + { X86_GRP_AES, "aes" }, + { X86_GRP_ADX, "adx" }, + { X86_GRP_AVX, "avx" }, + { X86_GRP_AVX2, "avx2" }, + { X86_GRP_AVX512, "avx512" }, + { X86_GRP_BMI, "bmi" }, + { X86_GRP_BMI2, "bmi2" }, + { X86_GRP_CMOV, "cmov" }, + { X86_GRP_F16C, "fc16" }, + { X86_GRP_FMA, "fma" }, + { X86_GRP_FMA4, "fma4" }, + { X86_GRP_FSGSBASE, "fsgsbase" }, + { X86_GRP_HLE, "hle" }, + { X86_GRP_MMX, "mmx" }, + { X86_GRP_MODE32, "mode32" }, + { X86_GRP_MODE64, "mode64" }, + { X86_GRP_RTM, "rtm" }, + { X86_GRP_SHA, "sha" }, + { X86_GRP_SSE1, "sse1" }, + { X86_GRP_SSE2, "sse2" }, + { X86_GRP_SSE3, "sse3" }, + { X86_GRP_SSE41, "sse41" }, + { X86_GRP_SSE42, "sse42" }, + { X86_GRP_SSE4A, "sse4a" }, + { X86_GRP_SSSE3, "ssse3" }, + { X86_GRP_PCLMUL, "pclmul" }, + { X86_GRP_XOP, "xop" }, + { X86_GRP_CDI, "cdi" }, + { X86_GRP_ERI, "eri" }, + { X86_GRP_TBM, "tbm" }, + { X86_GRP_16BITMODE, "16bitmode" }, + { X86_GRP_NOT64BITMODE, "not64bitmode" }, + { X86_GRP_SGX, "sgx" }, + { X86_GRP_DQI, "dqi" }, + { X86_GRP_BWI, "bwi" }, + { X86_GRP_PFI, "pfi" }, + { X86_GRP_VLX, "vlx" }, + { X86_GRP_SMAP, "smap" }, + { X86_GRP_NOVLX, "novlx" }, + { X86_GRP_FPU, "fpu" }, +}; +#endif + +const char *X86_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + +#define GET_INSTRINFO_ENUM +#ifdef CAPSTONE_X86_REDUCE +#include "X86GenInstrInfo_reduce.inc" + +const insn_map_x86 insns[] = { // reduce x86 instructions +#include "X86MappingInsn_reduce.inc" +}; +#else +#include "X86GenInstrInfo.inc" + +const insn_map_x86 insns[] = { // full x86 instructions +#include "X86MappingInsn.inc" +}; +#endif + +#ifndef CAPSTONE_DIET +// in arr, replace r1 = r2 +static void arr_replace(uint16_t *arr, uint8_t max, x86_reg r1, x86_reg r2) +{ + uint8_t i; + + for(i = 0; i < max; i++) { + if (arr[i] == r1) { + arr[i] = r2; + break; + } + } +} +#endif + +// look for @id in @insns +// return -1 if not found +unsigned int find_insn(unsigned int id) +{ + // binary searching since the IDs are sorted in order + unsigned int left, right, m; + unsigned int max = ARR_SIZE(insns); + + right = max - 1; + + if (id < insns[0].id || id > insns[right].id) + // not found + return -1; + + left = 0; + + while(left <= right) { + m = (left + right) / 2; + if (id == insns[m].id) { + return m; + } + + if (id < insns[m].id) + right = m - 1; + else + left = m + 1; + } + + // not found + // printf("NOT FOUNDDDDDDDDDDDDDDD id = %u\n", id); + return -1; +} + +// given internal insn id, return public instruction info +void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + unsigned int i = find_insn(id); + if (i != -1) { + insn->id = insns[i].mapid; + + if (h->detail_opt) { +#ifndef CAPSTONE_DIET + memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + + // special cases when regs_write[] depends on arch + switch(id) { + default: + memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + break; + case X86_RDTSC: + if (h->mode == CS_MODE_64) { + memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + } else { + insn->detail->regs_write[0] = X86_REG_EAX; + insn->detail->regs_write[1] = X86_REG_EDX; + insn->detail->regs_write_count = 2; + } + break; + case X86_RDTSCP: + if (h->mode == CS_MODE_64) { + memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + } else { + insn->detail->regs_write[0] = X86_REG_EAX; + insn->detail->regs_write[1] = X86_REG_ECX; + insn->detail->regs_write[2] = X86_REG_EDX; + insn->detail->regs_write_count = 3; + } + break; + } + + switch(insn->id) { + default: + break; + + case X86_INS_LOOP: + case X86_INS_LOOPE: + case X86_INS_LOOPNE: + switch(h->mode) { + default: break; + case CS_MODE_16: + insn->detail->regs_read[0] = X86_REG_CX; + insn->detail->regs_read_count = 1; + insn->detail->regs_write[0] = X86_REG_CX; + insn->detail->regs_write_count = 1; + break; + case CS_MODE_32: + insn->detail->regs_read[0] = X86_REG_ECX; + insn->detail->regs_read_count = 1; + insn->detail->regs_write[0] = X86_REG_ECX; + insn->detail->regs_write_count = 1; + break; + case CS_MODE_64: + insn->detail->regs_read[0] = X86_REG_RCX; + insn->detail->regs_read_count = 1; + insn->detail->regs_write[0] = X86_REG_RCX; + insn->detail->regs_write_count = 1; + break; + } + + // LOOPE & LOOPNE also read EFLAGS + if (insn->id != X86_INS_LOOP) { + insn->detail->regs_read[1] = X86_REG_EFLAGS; + insn->detail->regs_read_count = 2; + } + + break; + + case X86_INS_LODSB: + case X86_INS_LODSD: + case X86_INS_LODSQ: + case X86_INS_LODSW: + switch(h->mode) { + default: + break; + case CS_MODE_16: + arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_SI); + arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_SI); + break; + case CS_MODE_64: + arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_RSI); + arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_RSI); + break; + } + break; + + case X86_INS_SCASB: + case X86_INS_SCASW: + case X86_INS_SCASQ: + case X86_INS_STOSB: + case X86_INS_STOSD: + case X86_INS_STOSQ: + case X86_INS_STOSW: + switch(h->mode) { + default: + break; + case CS_MODE_16: + arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_DI); + arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_DI); + break; + case CS_MODE_64: + arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_RDI); + arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_RDI); + break; + } + break; + + case X86_INS_CMPSB: + case X86_INS_CMPSD: + case X86_INS_CMPSQ: + case X86_INS_CMPSW: + case X86_INS_MOVSB: + case X86_INS_MOVSW: + case X86_INS_MOVSD: + case X86_INS_MOVSQ: + switch(h->mode) { + default: + break; + case CS_MODE_16: + arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_DI); + arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_DI); + arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_SI); + arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_SI); + break; + case CS_MODE_64: + arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_RDI); + arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_RDI); + arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_RSI); + arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_RSI); + break; + } + break; + + case X86_INS_RET: + switch(h->mode) { + case CS_MODE_16: + insn->detail->regs_write[0] = X86_REG_SP; + insn->detail->regs_read[0] = X86_REG_SP; + break; + case CS_MODE_32: + insn->detail->regs_write[0] = X86_REG_ESP; + insn->detail->regs_read[0] = X86_REG_ESP; + break; + default: // 64-bit + insn->detail->regs_write[0] = X86_REG_RSP; + insn->detail->regs_read[0] = X86_REG_RSP; + break; + } + insn->detail->regs_write_count = 1; + insn->detail->regs_read_count = 1; + break; + } + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = X86_GRP_JUMP; + insn->detail->groups_count++; + } + + switch (insns[i].id) { + case X86_OUT8ir: + case X86_OUT16ir: + case X86_OUT32ir: + if (insn->detail->x86.operands[0].imm == -78) { + // Writing to port 0xb2 causes an SMI on most platforms + // See: http://cs.gmu.edu/~tr-admin/papers/GMU-CS-TR-2011-8.pdf + insn->detail->groups[insn->detail->groups_count] = X86_GRP_INT; + insn->detail->groups_count++; + } + break; + + default: + break; + } +#endif + } + } +} + +// map special instructions with accumulate registers. +// this is needed because LLVM embeds these register names into AsmStrs[], +// but not separately in operands +struct insn_reg { + uint16_t insn; + x86_reg reg; + enum cs_ac_type access; +}; + +struct insn_reg2 { + uint16_t insn; + x86_reg reg1, reg2; + enum cs_ac_type access1, access2; +}; + +static const struct insn_reg insn_regs_att[] = { + { X86_INSB, X86_REG_DX, CS_AC_READ }, + { X86_INSL, X86_REG_DX, CS_AC_READ }, + { X86_INSW, X86_REG_DX, CS_AC_READ }, + { X86_MOV16o16a, X86_REG_AX, CS_AC_READ }, + { X86_MOV16o32a, X86_REG_AX, CS_AC_READ }, + { X86_MOV16o64a, X86_REG_AX, CS_AC_READ }, + { X86_MOV32o16a, X86_REG_EAX, CS_AC_READ }, + { X86_MOV32o32a, X86_REG_EAX, CS_AC_READ }, + { X86_MOV32o64a, X86_REG_EAX, CS_AC_READ }, + { X86_MOV64o32a, X86_REG_RAX, CS_AC_READ }, + { X86_MOV64o64a, X86_REG_RAX, CS_AC_READ }, + { X86_MOV8o16a, X86_REG_AL, CS_AC_READ }, + { X86_MOV8o32a, X86_REG_AL, CS_AC_READ }, + { X86_MOV8o64a, X86_REG_AL, CS_AC_READ }, + { X86_OUT16ir, X86_REG_AX, CS_AC_READ }, + { X86_OUT32ir, X86_REG_EAX, CS_AC_READ }, + { X86_OUT8ir, X86_REG_AL, CS_AC_READ }, + { X86_POPDS16, X86_REG_DS, CS_AC_WRITE }, + { X86_POPDS32, X86_REG_DS, CS_AC_WRITE }, + { X86_POPES16, X86_REG_ES, CS_AC_WRITE }, + { X86_POPES32, X86_REG_ES, CS_AC_WRITE }, + { X86_POPFS16, X86_REG_FS, CS_AC_WRITE }, + { X86_POPFS32, X86_REG_FS, CS_AC_WRITE }, + { X86_POPFS64, X86_REG_FS, CS_AC_WRITE }, + { X86_POPGS16, X86_REG_GS, CS_AC_WRITE }, + { X86_POPGS32, X86_REG_GS, CS_AC_WRITE }, + { X86_POPGS64, X86_REG_GS, CS_AC_WRITE }, + { X86_POPSS16, X86_REG_SS, CS_AC_WRITE }, + { X86_POPSS32, X86_REG_SS, CS_AC_WRITE }, + { X86_PUSHCS16, X86_REG_CS, CS_AC_READ }, + { X86_PUSHCS32, X86_REG_CS, CS_AC_READ }, + { X86_PUSHDS16, X86_REG_DS, CS_AC_READ }, + { X86_PUSHDS32, X86_REG_DS, CS_AC_READ }, + { X86_PUSHES16, X86_REG_ES, CS_AC_READ }, + { X86_PUSHES32, X86_REG_ES, CS_AC_READ }, + { X86_PUSHFS16, X86_REG_FS, CS_AC_READ }, + { X86_PUSHFS32, X86_REG_FS, CS_AC_READ }, + { X86_PUSHFS64, X86_REG_FS, CS_AC_READ }, + { X86_PUSHGS16, X86_REG_GS, CS_AC_READ }, + { X86_PUSHGS32, X86_REG_GS, CS_AC_READ }, + { X86_PUSHGS64, X86_REG_GS, CS_AC_READ }, + { X86_PUSHSS16, X86_REG_SS, CS_AC_READ }, + { X86_PUSHSS32, X86_REG_SS, CS_AC_READ }, + { X86_RCL16rCL, X86_REG_CL, CS_AC_READ }, + { X86_RCL32rCL, X86_REG_CL, CS_AC_READ }, + { X86_RCL64rCL, X86_REG_CL, CS_AC_READ }, + { X86_RCL8rCL, X86_REG_CL, CS_AC_READ }, + { X86_RCR16rCL, X86_REG_CL, CS_AC_READ }, + { X86_RCR32rCL, X86_REG_CL, CS_AC_READ }, + { X86_RCR64rCL, X86_REG_CL, CS_AC_READ }, + { X86_RCR8rCL, X86_REG_CL, CS_AC_READ }, + { X86_ROL16rCL, X86_REG_CL, CS_AC_READ }, + { X86_ROL32rCL, X86_REG_CL, CS_AC_READ }, + { X86_ROL64rCL, X86_REG_CL, CS_AC_READ }, + { X86_ROL8rCL, X86_REG_CL, CS_AC_READ }, + { X86_ROR16rCL, X86_REG_CL, CS_AC_READ }, + { X86_ROR32rCL, X86_REG_CL, CS_AC_READ }, + { X86_ROR64rCL, X86_REG_CL, CS_AC_READ }, + { X86_ROR8rCL, X86_REG_CL, CS_AC_READ }, + { X86_SAL16rCL, X86_REG_CL, CS_AC_READ }, + { X86_SAL32rCL, X86_REG_CL, CS_AC_READ }, + { X86_SAL64rCL, X86_REG_CL, CS_AC_READ }, + { X86_SAL8rCL, X86_REG_CL, CS_AC_READ }, + { X86_SAR16rCL, X86_REG_CL, CS_AC_READ }, + { X86_SAR32rCL, X86_REG_CL, CS_AC_READ }, + { X86_SAR64rCL, X86_REG_CL, CS_AC_READ }, + { X86_SAR8rCL, X86_REG_CL, CS_AC_READ }, + { X86_SHL16rCL, X86_REG_CL, CS_AC_READ }, + { X86_SHL32rCL, X86_REG_CL, CS_AC_READ }, + { X86_SHL64rCL, X86_REG_CL, CS_AC_READ }, + { X86_SHL8rCL, X86_REG_CL, CS_AC_READ }, + { X86_SHLD16mrCL, X86_REG_CL, CS_AC_READ }, + { X86_SHLD16rrCL, X86_REG_CL, CS_AC_READ }, + { X86_SHLD32mrCL, X86_REG_CL, CS_AC_READ }, + { X86_SHLD32rrCL, X86_REG_CL, CS_AC_READ }, + { X86_SHLD64mrCL, X86_REG_CL, CS_AC_READ }, + { X86_SHLD64rrCL, X86_REG_CL, CS_AC_READ }, + { X86_SHR16rCL, X86_REG_CL, CS_AC_READ }, + { X86_SHR32rCL, X86_REG_CL, CS_AC_READ }, + { X86_SHR64rCL, X86_REG_CL, CS_AC_READ }, + { X86_SHR8rCL, X86_REG_CL, CS_AC_READ }, + { X86_SHRD16mrCL, X86_REG_CL, CS_AC_READ }, + { X86_SHRD16rrCL, X86_REG_CL, CS_AC_READ }, + { X86_SHRD32mrCL, X86_REG_CL, CS_AC_READ }, + { X86_SHRD32rrCL, X86_REG_CL, CS_AC_READ }, + { X86_SHRD64mrCL, X86_REG_CL, CS_AC_READ }, + { X86_SHRD64rrCL, X86_REG_CL, CS_AC_READ }, + { X86_XCHG16ar, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, + { X86_XCHG32ar, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, + { X86_XCHG64ar, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, +}; + +static const struct insn_reg insn_regs_att_extra[] = { + // dummy entry, to avoid empty array + { 0, 0 }, +#ifndef CAPSTONE_X86_REDUCE + { X86_ADD_FrST0, X86_REG_ST0, CS_AC_READ }, + { X86_DIVR_FrST0, X86_REG_ST0, CS_AC_READ }, + { X86_DIV_FrST0, X86_REG_ST0, CS_AC_READ }, + { X86_FNSTSW16r, X86_REG_AX, CS_AC_READ }, + { X86_MUL_FrST0, X86_REG_ST0, CS_AC_READ }, + { X86_SKINIT, X86_REG_EAX, CS_AC_READ }, + { X86_SUBR_FrST0, X86_REG_ST0, CS_AC_READ }, + { X86_SUB_FrST0, X86_REG_ST0, CS_AC_READ }, + { X86_VMLOAD32, X86_REG_EAX, CS_AC_READ }, + { X86_VMLOAD64, X86_REG_RAX, CS_AC_READ }, + { X86_VMRUN32, X86_REG_EAX, CS_AC_READ }, + { X86_VMRUN64, X86_REG_RAX, CS_AC_READ }, + { X86_VMSAVE32, X86_REG_EAX, CS_AC_READ }, + { X86_VMSAVE64, X86_REG_RAX, CS_AC_READ }, +#endif +}; + +static const struct insn_reg insn_regs_intel[] = { + { X86_ADC16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, + { X86_ADC32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, + { X86_ADC64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, + { X86_ADC8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, + { X86_ADD16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, + { X86_ADD32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, + { X86_ADD64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, + { X86_ADD8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, + { X86_AND16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, + { X86_AND32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, + { X86_AND64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, + { X86_AND8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, + { X86_CMP16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, + { X86_CMP32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, + { X86_CMP64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, + { X86_CMP8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, + { X86_IN16ri, X86_REG_AX, CS_AC_WRITE }, + { X86_IN32ri, X86_REG_EAX, CS_AC_WRITE }, + { X86_IN8ri, X86_REG_AL, CS_AC_WRITE }, + { X86_LODSB, X86_REG_AL, CS_AC_WRITE }, + { X86_LODSL, X86_REG_EAX, CS_AC_WRITE }, + { X86_LODSQ, X86_REG_RAX, CS_AC_WRITE }, + { X86_LODSW, X86_REG_AX, CS_AC_WRITE }, + { X86_MOV16ao16, X86_REG_AX, CS_AC_WRITE }, // 16-bit A1 1020 // mov ax, word ptr [0x2010] + { X86_MOV16ao32, X86_REG_AX, CS_AC_WRITE }, // 32-bit A1 10203040 // mov ax, word ptr [0x40302010] + { X86_MOV16ao64, X86_REG_AX, CS_AC_WRITE }, // 64-bit 66 A1 1020304050607080 // movabs ax, word ptr [0x8070605040302010] + { X86_MOV32ao16, X86_REG_EAX, CS_AC_WRITE }, // 32-bit 67 A1 1020 // mov eax, dword ptr [0x2010] + { X86_MOV32ao32, X86_REG_EAX, CS_AC_WRITE }, // 32-bit A1 10203040 // mov eax, dword ptr [0x40302010] + { X86_MOV32ao64, X86_REG_EAX, CS_AC_WRITE }, // 64-bit A1 1020304050607080 // movabs eax, dword ptr [0x8070605040302010] + { X86_MOV64ao32, X86_REG_RAX, CS_AC_WRITE }, // 64-bit 48 8B04 10203040 // mov rax, qword ptr [0x40302010] + { X86_MOV64ao64, X86_REG_RAX, CS_AC_WRITE }, // 64-bit 48 A1 1020304050607080 // movabs rax, qword ptr [0x8070605040302010] + { X86_MOV8ao16, X86_REG_AL, CS_AC_WRITE }, // 16-bit A0 1020 // mov al, byte ptr [0x2010] + { X86_MOV8ao32, X86_REG_AL, CS_AC_WRITE }, // 32-bit A0 10203040 // mov al, byte ptr [0x40302010] + { X86_MOV8ao64, X86_REG_AL, CS_AC_WRITE }, // 64-bit 66 A0 1020304050607080 // movabs al, byte ptr [0x8070605040302010] + { X86_OR16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, + { X86_OR32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, + { X86_OR64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, + { X86_OR8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, + { X86_OUTSB, X86_REG_DX, CS_AC_WRITE }, + { X86_OUTSL, X86_REG_DX, CS_AC_WRITE }, + { X86_OUTSW, X86_REG_DX, CS_AC_WRITE }, + { X86_POPDS16, X86_REG_DS, CS_AC_WRITE }, + { X86_POPDS32, X86_REG_DS, CS_AC_WRITE }, + { X86_POPES16, X86_REG_ES, CS_AC_WRITE }, + { X86_POPES32, X86_REG_ES, CS_AC_WRITE }, + { X86_POPFS16, X86_REG_FS, CS_AC_WRITE }, + { X86_POPFS32, X86_REG_FS, CS_AC_WRITE }, + { X86_POPFS64, X86_REG_FS, CS_AC_WRITE }, + { X86_POPGS16, X86_REG_GS, CS_AC_WRITE }, + { X86_POPGS32, X86_REG_GS, CS_AC_WRITE }, + { X86_POPGS64, X86_REG_GS, CS_AC_WRITE }, + { X86_POPSS16, X86_REG_SS, CS_AC_WRITE }, + { X86_POPSS32, X86_REG_SS, CS_AC_WRITE }, + { X86_PUSHCS16, X86_REG_CS, CS_AC_READ }, + { X86_PUSHCS32, X86_REG_CS, CS_AC_READ }, + { X86_PUSHDS16, X86_REG_DS, CS_AC_READ }, + { X86_PUSHDS32, X86_REG_DS, CS_AC_READ }, + { X86_PUSHES16, X86_REG_ES, CS_AC_READ }, + { X86_PUSHES32, X86_REG_ES, CS_AC_READ }, + { X86_PUSHFS16, X86_REG_FS, CS_AC_READ }, + { X86_PUSHFS32, X86_REG_FS, CS_AC_READ }, + { X86_PUSHFS64, X86_REG_FS, CS_AC_READ }, + { X86_PUSHGS16, X86_REG_GS, CS_AC_READ }, + { X86_PUSHGS32, X86_REG_GS, CS_AC_READ }, + { X86_PUSHGS64, X86_REG_GS, CS_AC_READ }, + { X86_PUSHSS16, X86_REG_SS, CS_AC_READ }, + { X86_PUSHSS32, X86_REG_SS, CS_AC_READ }, + { X86_SBB16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, + { X86_SBB32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, + { X86_SBB64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, + { X86_SBB8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, + { X86_SCASB, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, + { X86_SCASL, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, + { X86_SCASQ, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, + { X86_SCASW, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, + { X86_SUB16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, + { X86_SUB32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, + { X86_SUB64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, + { X86_SUB8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, + { X86_TEST16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, + { X86_TEST32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, + { X86_TEST64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, + { X86_TEST8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, + { X86_XOR16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, + { X86_XOR32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, + { X86_XOR64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, + { X86_XOR8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, +}; + +static const struct insn_reg insn_regs_intel_extra[] = { + // dummy entry, to avoid empty array + { 0, 0, 0 }, +#ifndef CAPSTONE_X86_REDUCE + { X86_CMOVBE_F, X86_REG_ST0, CS_AC_WRITE }, + { X86_CMOVB_F, X86_REG_ST0, CS_AC_WRITE }, + { X86_CMOVE_F, X86_REG_ST0, CS_AC_WRITE }, + { X86_CMOVNBE_F, X86_REG_ST0, CS_AC_WRITE }, + { X86_CMOVNB_F, X86_REG_ST0, CS_AC_WRITE }, + { X86_CMOVNE_F, X86_REG_ST0, CS_AC_WRITE }, + { X86_CMOVNP_F, X86_REG_ST0, CS_AC_WRITE }, + { X86_CMOVP_F, X86_REG_ST0, CS_AC_WRITE }, + // { X86_COMP_FST0r, X86_REG_ST0, CS_AC_WRITE }, + // { X86_COM_FST0r, X86_REG_ST0, CS_AC_WRITE }, + { X86_FNSTSW16r, X86_REG_AX, CS_AC_WRITE }, + { X86_SKINIT, X86_REG_EAX, CS_AC_WRITE }, + { X86_VMLOAD32, X86_REG_EAX, CS_AC_WRITE }, + { X86_VMLOAD64, X86_REG_RAX, CS_AC_WRITE }, + { X86_VMRUN32, X86_REG_EAX, CS_AC_WRITE }, + { X86_VMRUN64, X86_REG_RAX, CS_AC_WRITE }, + { X86_VMSAVE32, X86_REG_EAX, CS_AC_READ }, + { X86_VMSAVE64, X86_REG_RAX, CS_AC_READ }, + { X86_XCH_F, X86_REG_ST0, CS_AC_WRITE }, +#endif +}; + +static const struct insn_reg2 insn_regs_intel2[] = { + { X86_IN16rr, X86_REG_AX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ }, + { X86_IN32rr, X86_REG_EAX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ }, + { X86_IN8rr, X86_REG_AL, X86_REG_DX, CS_AC_WRITE, CS_AC_READ }, + { X86_INVLPGA32, X86_REG_EAX, X86_REG_ECX, CS_AC_READ, CS_AC_READ }, + { X86_INVLPGA64, X86_REG_RAX, X86_REG_ECX, CS_AC_READ, CS_AC_READ }, + { X86_OUT16rr, X86_REG_DX, X86_REG_AX, CS_AC_READ, CS_AC_READ }, + { X86_OUT32rr, X86_REG_DX, X86_REG_EAX, CS_AC_READ, CS_AC_READ }, + { X86_OUT8rr, X86_REG_DX, X86_REG_AL, CS_AC_READ, CS_AC_READ }, +}; + +static int binary_search1(const struct insn_reg *insns, unsigned int max, unsigned int id) +{ + unsigned int first, last, mid; + + first = 0; + last = max -1; + + if (insns[0].insn > id || insns[last].insn < id) { + // not found + return -1; + } + + while (first <= last) { + mid = (first + last) / 2; + if (insns[mid].insn < id) { + first = mid + 1; + } else if (insns[mid].insn == id) { + return mid; + } else { + if (mid == 0) + break; + last = mid - 1; + } + } + + // not found + return -1; +} + +static int binary_search2(const struct insn_reg2 *insns, unsigned int max, unsigned int id) +{ + unsigned int first, last, mid; + + first = 0; + last = max -1; + + if (insns[0].insn > id || insns[last].insn < id) { + // not found + return -1; + } + + while (first <= last) { + mid = (first + last) / 2; + if (insns[mid].insn < id) { + first = mid + 1; + } else if (insns[mid].insn == id) { + return mid; + } else { + if (mid == 0) + break; + last = mid - 1; + } + } + + // not found + return -1; +} + +// return register of given instruction id +// return 0 if not found +// this is to handle instructions embedding accumulate registers into AsmStrs[] +x86_reg X86_insn_reg_intel(unsigned int id, enum cs_ac_type *access) +{ + int i; + + i = binary_search1(insn_regs_intel, ARR_SIZE(insn_regs_intel), id); + if (i != -1) { + if (access) { + *access = insn_regs_intel[i].access; + } + return insn_regs_intel[i].reg; + } + + i = binary_search1(insn_regs_intel_extra, ARR_SIZE(insn_regs_intel_extra), id); + if (i != -1) { + if (access) { + *access = insn_regs_intel_extra[i].access; + } + return insn_regs_intel_extra[i].reg; + } + + // not found + return 0; +} + +bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2) +{ + int i = binary_search2(insn_regs_intel2, ARR_SIZE(insn_regs_intel2), id); + if (i != -1) { + *reg1 = insn_regs_intel2[i].reg1; + *reg2 = insn_regs_intel2[i].reg2; + if (access1) + *access1 = insn_regs_intel2[i].access1; + if (access2) + *access2 = insn_regs_intel2[i].access2; + return true; + } + + // not found + return false; +} + +x86_reg X86_insn_reg_att(unsigned int id, enum cs_ac_type *access) +{ + int i; + + i = binary_search1(insn_regs_att, ARR_SIZE(insn_regs_att), id); + if (i != -1) { + if (access) + *access = insn_regs_att[i].access; + return insn_regs_att[i].reg; + } + + i = binary_search1(insn_regs_att_extra, ARR_SIZE(insn_regs_att_extra), id); + if (i != -1) { + if (access) + *access = insn_regs_att_extra[i].access; + return insn_regs_att_extra[i].reg; + } + + // not found + return 0; +} + +// ATT just reuses Intel data, but with the order of registers reversed +bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2) +{ + int i = binary_search2(insn_regs_intel2, ARR_SIZE(insn_regs_intel2), id); + if (i != -1) { + *reg1 = insn_regs_intel2[i].reg2; + *reg2 = insn_regs_intel2[i].reg1; + if (access1) + *access1 = insn_regs_intel2[i].access2; + if (access2) + *access2 = insn_regs_intel2[i].access1; + return true; + } + + // not found + return false; +} + +// given MCInst's id, find out if this insn is valid for REPNE prefix +static bool valid_repne(cs_struct *h, unsigned int opcode) +{ + unsigned int id; + unsigned int i = find_insn(opcode); + if (i != -1) { + id = insns[i].mapid; + switch(id) { + default: + return false; + + case X86_INS_CMPSB: + case X86_INS_CMPSS: + case X86_INS_CMPSW: + case X86_INS_CMPSQ: + + case X86_INS_SCASB: + case X86_INS_SCASW: + case X86_INS_SCASQ: + + case X86_INS_MOVSB: + case X86_INS_MOVSS: + case X86_INS_MOVSW: + case X86_INS_MOVSQ: + + case X86_INS_LODSB: + case X86_INS_LODSW: + case X86_INS_LODSD: + case X86_INS_LODSQ: + + case X86_INS_STOSB: + case X86_INS_STOSW: + case X86_INS_STOSD: + case X86_INS_STOSQ: + + case X86_INS_INSB: + case X86_INS_INSW: + case X86_INS_INSD: + + case X86_INS_OUTSB: + case X86_INS_OUTSW: + case X86_INS_OUTSD: + + return true; + + case X86_INS_MOVSD: + if (opcode == X86_MOVSW) // REP MOVSB + return true; + return false; + + case X86_INS_CMPSD: + if (opcode == X86_CMPSL) // REP CMPSD + return true; + return false; + + case X86_INS_SCASD: + if (opcode == X86_SCASL) // REP SCASD + return true; + return false; + } + } + + // not found + return false; +} + +// given MCInst's id, find out if this insn is valid for BND prefix +// BND prefix is valid for CALL/JMP/RET +#ifndef CAPSTONE_DIET +static bool valid_bnd(cs_struct *h, unsigned int opcode) +{ + unsigned int id; + unsigned int i = find_insn(opcode); + if (i != -1) { + id = insns[i].mapid; + switch(id) { + default: + return false; + + case X86_INS_JAE: + case X86_INS_JA: + case X86_INS_JBE: + case X86_INS_JB: + case X86_INS_JCXZ: + case X86_INS_JECXZ: + case X86_INS_JE: + case X86_INS_JGE: + case X86_INS_JG: + case X86_INS_JLE: + case X86_INS_JL: + case X86_INS_JMP: + case X86_INS_JNE: + case X86_INS_JNO: + case X86_INS_JNP: + case X86_INS_JNS: + case X86_INS_JO: + case X86_INS_JP: + case X86_INS_JRCXZ: + case X86_INS_JS: + + case X86_INS_CALL: + case X86_INS_RET: + case X86_INS_RETF: + case X86_INS_RETFQ: + return true; + } + } + + // not found + return false; +} + +// return true if the opcode is XCHG [mem] +static bool xchg_mem(unsigned int opcode) +{ + switch(opcode) { + default: + return false; + case X86_XCHG8rm: + case X86_XCHG16rm: + case X86_XCHG32rm: + case X86_XCHG64rm: + return true; + } +} +#endif + +// given MCInst's id, find out if this insn is valid for REP prefix +static bool valid_rep(cs_struct *h, unsigned int opcode) +{ + unsigned int id; + unsigned int i = find_insn(opcode); + if (i != -1) { + id = insns[i].mapid; + switch(id) { + default: + return false; + + case X86_INS_MOVSB: + case X86_INS_MOVSW: + case X86_INS_MOVSQ: + + case X86_INS_LODSB: + case X86_INS_LODSW: + case X86_INS_LODSQ: + + case X86_INS_STOSB: + case X86_INS_STOSW: + case X86_INS_STOSQ: + + case X86_INS_INSB: + case X86_INS_INSW: + case X86_INS_INSD: + + case X86_INS_OUTSB: + case X86_INS_OUTSW: + case X86_INS_OUTSD: + return true; + + // following are some confused instructions, which have the same + // mnemonics in 128bit media instructions. Intel is horribly crazy! + case X86_INS_MOVSD: + if (opcode == X86_MOVSL) // REP MOVSD + return true; + return false; + + case X86_INS_LODSD: + if (opcode == X86_LODSL) // REP LODSD + return true; + return false; + + case X86_INS_STOSD: + if (opcode == X86_STOSL) // REP STOSD + return true; + return false; + } + } + + // not found + return false; +} + +#ifndef CAPSTONE_DIET +// given MCInst's id, find if this is a "repz ret" instruction +// gcc generates "repz ret" (f3 c3) instructions in some cases as an +// optimization for AMD platforms, see: +// https://gcc.gnu.org/legacy-ml/gcc-patches/2003-05/msg02117.html +static bool valid_ret_repz(cs_struct *h, unsigned int opcode) +{ + unsigned int id; + unsigned int i = find_insn(opcode); + + if (i != -1) { + id = insns[i].mapid; + return id == X86_INS_RET; + } + + // not found + return false; +} +#endif + +// given MCInst's id, find out if this insn is valid for REPE prefix +static bool valid_repe(cs_struct *h, unsigned int opcode) +{ + unsigned int id; + unsigned int i = find_insn(opcode); + if (i != -1) { + id = insns[i].mapid; + switch(id) { + default: + return false; + + case X86_INS_CMPSB: + case X86_INS_CMPSW: + case X86_INS_CMPSQ: + + case X86_INS_SCASB: + case X86_INS_SCASW: + case X86_INS_SCASQ: + return true; + + // following are some confused instructions, which have the same + // mnemonics in 128bit media instructions. Intel is horribly crazy! + case X86_INS_CMPSD: + if (opcode == X86_CMPSL) // REP CMPSD + return true; + return false; + + case X86_INS_SCASD: + if (opcode == X86_SCASL) // REP SCASD + return true; + return false; + } + } + + // not found + return false; +} + +// Given MCInst's id, find out if this insn is valid for NOTRACK prefix. +// NOTRACK prefix is valid for CALL/JMP. +static bool valid_notrack(cs_struct *h, unsigned int opcode) +{ + unsigned int id; + unsigned int i = find_insn(opcode); + if (i != -1) { + id = insns[i].mapid; + switch(id) { + default: + return false; + case X86_INS_CALL: + case X86_INS_JMP: + return true; + } + } + + // not found + return false; +} + +#ifndef CAPSTONE_DIET +// add *CX register to regs_read[] & regs_write[] +static void add_cx(MCInst *MI) +{ + if (MI->csh->detail_opt) { + x86_reg cx; + + if (MI->csh->mode & CS_MODE_16) + cx = X86_REG_CX; + else if (MI->csh->mode & CS_MODE_32) + cx = X86_REG_ECX; + else // 64-bit + cx = X86_REG_RCX; + + MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = cx; + MI->flat_insn->detail->regs_read_count++; + + MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = cx; + MI->flat_insn->detail->regs_write_count++; + } +} +#endif + +// return true if we patch the mnemonic +bool X86_lockrep(MCInst *MI, SStream *O) +{ + unsigned int opcode; + bool res = false; + + switch(MI->x86_prefix[0]) { + default: + break; + case 0xf0: +#ifndef CAPSTONE_DIET + if (MI->xAcquireRelease == 0xf2) + SStream_concat(O, "xacquire|lock|"); + else if (MI->xAcquireRelease == 0xf3) + SStream_concat(O, "xrelease|lock|"); + else + SStream_concat(O, "lock|"); +#endif + break; + case 0xf2: // repne + opcode = MCInst_getOpcode(MI); + +#ifndef CAPSTONE_DIET // only care about memonic in standard (non-diet) mode + if (xchg_mem(opcode) && MI->xAcquireRelease) { + SStream_concat(O, "xacquire|"); + } else if (valid_repne(MI->csh, opcode)) { + SStream_concat(O, "repne|"); + add_cx(MI); + } else if (valid_bnd(MI->csh, opcode)) { + SStream_concat(O, "bnd|"); + } else { + // invalid prefix + MI->x86_prefix[0] = 0; + + // handle special cases +#ifndef CAPSTONE_X86_REDUCE +#if 0 + if (opcode == X86_MULPDrr) { + MCInst_setOpcode(MI, X86_MULSDrr); + SStream_concat0(O, "mulsd\t"); + res = true; + } +#endif +#endif + } +#else // diet mode -> only patch opcode in special cases + if (!valid_repne(MI->csh, opcode)) { + MI->x86_prefix[0] = 0; + } +#ifndef CAPSTONE_X86_REDUCE +#if 0 + // handle special cases + if (opcode == X86_MULPDrr) { + MCInst_setOpcode(MI, X86_MULSDrr); + } +#endif +#endif +#endif + break; + + case 0xf3: + opcode = MCInst_getOpcode(MI); + +#ifndef CAPSTONE_DIET // only care about memonic in standard (non-diet) mode + if (xchg_mem(opcode) && MI->xAcquireRelease) { + SStream_concat(O, "xrelease|"); + } else if (valid_rep(MI->csh, opcode)) { + SStream_concat(O, "rep|"); + add_cx(MI); + } else if (valid_repe(MI->csh, opcode)) { + SStream_concat(O, "repe|"); + add_cx(MI); + } else if (valid_ret_repz(MI->csh, opcode)) { + SStream_concat(O, "repz|"); + } else { + // invalid prefix + MI->x86_prefix[0] = 0; + + // handle special cases +#ifndef CAPSTONE_X86_REDUCE +#if 0 + // FIXME: remove this special case? + if (opcode == X86_MULPDrr) { + MCInst_setOpcode(MI, X86_MULSSrr); + SStream_concat0(O, "mulss\t"); + res = true; + } +#endif +#endif + } +#else // diet mode -> only patch opcode in special cases + if (!valid_rep(MI->csh, opcode) && !valid_repe(MI->csh, opcode)) { + MI->x86_prefix[0] = 0; + } +#ifndef CAPSTONE_X86_REDUCE +#if 0 + // handle special cases + // FIXME: remove this special case? + if (opcode == X86_MULPDrr) { + MCInst_setOpcode(MI, X86_MULSSrr); + } +#endif +#endif +#endif + break; + } + + switch(MI->x86_prefix[1]) { + default: + break; + case 0x3e: + opcode = MCInst_getOpcode(MI); + if (valid_notrack(MI->csh, opcode)) { + SStream_concat(O, "notrack|"); + } + break; + } + + // copy normalized prefix[] back to x86.prefix[] + if (MI->csh->detail_opt) + memcpy(MI->flat_insn->detail->x86.prefix, MI->x86_prefix, ARR_SIZE(MI->x86_prefix)); + + return res; +} + +void op_addReg(MCInst *MI, int reg) +{ + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg]; + MI->flat_insn->detail->x86.op_count++; + } + + if (MI->op1_size == 0) + MI->op1_size = MI->csh->regsize_map[reg]; +} + +void op_addImm(MCInst *MI, int v) +{ + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = v; + // if op_count > 0, then this operand's size is taken from the destination op + if (MI->csh->syntax != CS_OPT_SYNTAX_ATT) { + if (MI->flat_insn->detail->x86.op_count > 0) + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size; + else + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; + } else + MI->has_imm = true; + MI->flat_insn->detail->x86.op_count++; + } + + if (MI->op1_size == 0) + MI->op1_size = MI->imm_size; +} + +void op_addXopCC(MCInst *MI, int v) +{ + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.xop_cc = v; + } +} + +void op_addSseCC(MCInst *MI, int v) +{ + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.sse_cc = v; + } +} + +void op_addAvxCC(MCInst *MI, int v) +{ + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.avx_cc = v; + } +} + +void op_addAvxRoundingMode(MCInst *MI, int v) +{ + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.avx_rm = v; + } +} + +// below functions supply details to X86GenAsmWriter*.inc +void op_addAvxZeroOpmask(MCInst *MI) +{ + if (MI->csh->detail_opt) { + // link with the previous operand + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].avx_zero_opmask = true; + } +} + +void op_addAvxSae(MCInst *MI) +{ + if (MI->csh->detail_opt) { + MI->flat_insn->detail->x86.avx_sae = true; + } +} + +void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v) +{ + if (MI->csh->detail_opt) { + // link with the previous operand + MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].avx_bcast = v; + } +} + +#ifndef CAPSTONE_DIET +// map instruction to its characteristics +typedef struct insn_op { + uint64_t flags; // how this instruction update EFLAGS(arithmetic instructions) of FPU FLAGS(for FPU instructions) + uint8_t access[6]; +} insn_op; + +static const insn_op insn_ops[] = { +#ifdef CAPSTONE_X86_REDUCE +#include "X86MappingInsnOp_reduce.inc" +#else +#include "X86MappingInsnOp.inc" +#endif +}; + +// given internal insn id, return operand access info +const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags) +{ + unsigned int i = find_insn(id); + if (i != -1) { + *eflags = insn_ops[i].flags; + return insn_ops[i].access; + } + + return NULL; +} + +void X86_reg_access(const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count) +{ + uint8_t i; + uint8_t read_count, write_count; + cs_x86 *x86 = &(insn->detail->x86); + + read_count = insn->detail->regs_read_count; + write_count = insn->detail->regs_write_count; + + // implicit registers + memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0])); + memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0])); + + // explicit registers + for (i = 0; i < x86->op_count; i++) { + cs_x86_op *op = &(x86->operands[i]); + switch((int)op->type) { + case X86_OP_REG: + if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) { + regs_read[read_count] = op->reg; + read_count++; + } + if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) { + regs_write[write_count] = op->reg; + write_count++; + } + break; + case X86_OP_MEM: + // registers appeared in memory references always being read + if ((op->mem.segment != X86_REG_INVALID)) { + regs_read[read_count] = op->mem.segment; + read_count++; + } + if ((op->mem.base != X86_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) { + regs_read[read_count] = op->mem.base; + read_count++; + } + if ((op->mem.index != X86_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) { + regs_read[read_count] = op->mem.index; + read_count++; + } + default: + break; + } + } + + *regs_read_count = read_count; + *regs_write_count = write_count; +} +#endif + +// map immediate size to instruction id +// this array is sorted for binary searching +static const struct size_id { + uint8_t enc_size; + uint8_t size; + uint16_t id; +} x86_imm_size[] = { +#include "X86ImmSize.inc" +}; + +// given the instruction name, return the size of its immediate operand (or 0) +uint8_t X86_immediate_size(unsigned int id, uint8_t *enc_size) +{ + // binary searching since the IDs are sorted in order + unsigned int left, right, m; + + right = ARR_SIZE(x86_imm_size) - 1; + + if (id < x86_imm_size[0].id || id > x86_imm_size[right].id) + // not found + return 0; + + left = 0; + + while (left <= right) { + m = (left + right) / 2; + if (id == x86_imm_size[m].id) { + if (enc_size != NULL) + *enc_size = x86_imm_size[m].enc_size; + + return x86_imm_size[m].size; + } + + if (id > x86_imm_size[m].id) + left = m + 1; + else { + if (m == 0) + break; + right = m - 1; + } + } + + // not found + return 0; +} + +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" + +// map internal register id to public register id +static const struct register_map { + unsigned short id; + unsigned short pub_id; +} reg_map [] = { + // first dummy map + { 0, 0 }, +#include "X86MappingReg.inc" +}; + +// return 0 on invalid input, or public register ID otherwise +// NOTE: reg_map is sorted in order of internal register +unsigned short X86_register_map(unsigned short id) +{ + if (id < ARR_SIZE(reg_map)) + return reg_map[id].pub_id; + + return 0; +} + +/// The post-printer function. Used to fixup flaws in the disassembly information +/// of certain instructions. +void X86_postprinter(csh handle, cs_insn *insn, char *mnem, MCInst *mci) { + if (!insn || !insn->detail) { + return; + } + switch (insn->id) { + default: + break; + case X86_INS_RCL: + // Addmissing 1 immediate + if (insn->detail->x86.op_count > 1) { + return; + } + insn->detail->x86.operands[1].imm = 1; + insn->detail->x86.operands[1].type = X86_OP_IMM; + insn->detail->x86.operands[1].access = CS_AC_READ; + insn->detail->x86.op_count++; + break; + } +} + + +#endif diff --git a/thirdparty/capstone/arch/X86/X86Mapping.h b/thirdparty/capstone/arch/X86/X86Mapping.h new file mode 100644 index 0000000..933f208 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86Mapping.h @@ -0,0 +1,96 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +#ifndef CS_X86_MAP_H +#define CS_X86_MAP_H + +#include "capstone/capstone.h" +#include "../../cs_priv.h" + +// map instruction to its characteristics +typedef struct insn_map_x86 { + unsigned short id; + unsigned short mapid; + unsigned char is64bit; +#ifndef CAPSTONE_DIET + uint16_t regs_use[12]; // list of implicit registers used by this instruction + uint16_t regs_mod[20]; // list of implicit registers modified by this instruction + unsigned char groups[8]; // list of group this instruction belong to + bool branch; // branch instruction? + bool indirect_branch; // indirect branch instruction? +#endif +} insn_map_x86; + +extern const insn_map_x86 insns[]; + +// map sib_base to x86_reg +x86_reg x86_map_sib_base(int r); + +// map sib_index to x86_reg +x86_reg x86_map_sib_index(int r); + +// map seg_override to x86_reg +x86_reg x86_map_segment(int r); + +// return name of register in friendly string +const char *X86_reg_name(csh handle, unsigned int reg); + +// given internal insn id, return public instruction info +void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +// return insn name, given insn id +const char *X86_insn_name(csh handle, unsigned int id); + +// return group name, given group id +const char *X86_group_name(csh handle, unsigned int id); + +// return register of given instruction id +// return 0 if not found +// this is to handle instructions embedding accumulate registers into AsmStrs[] +x86_reg X86_insn_reg_intel(unsigned int id, enum cs_ac_type *access); +x86_reg X86_insn_reg_att(unsigned int id, enum cs_ac_type *access); +bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2); +bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2); + +extern const uint64_t arch_masks[9]; + +// handle LOCK/REP/REPNE prefixes +// return True if we patch mnemonic, like in MULPD case +bool X86_lockrep(MCInst *MI, SStream *O); + +// map registers to sizes +extern const uint8_t regsize_map_32[]; +extern const uint8_t regsize_map_64[]; + +void op_addReg(MCInst *MI, int reg); +void op_addImm(MCInst *MI, int v); + +void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v); + +void op_addXopCC(MCInst *MI, int v); +void op_addSseCC(MCInst *MI, int v); +void op_addAvxCC(MCInst *MI, int v); + +void op_addAvxZeroOpmask(MCInst *MI); + +void op_addAvxSae(MCInst *MI); + +void op_addAvxRoundingMode(MCInst *MI, int v); + +// given internal insn id, return operand access info +const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags); + +void X86_reg_access(const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count); + +// given the instruction id, return the size of its immediate operand (or 0) +uint8_t X86_immediate_size(unsigned int id, uint8_t *enc_size); + +unsigned short X86_register_map(unsigned short id); + +unsigned int find_insn(unsigned int id); + +void X86_postprinter(csh handle, cs_insn *insn, char *mnem, MCInst *mci); + +#endif diff --git a/thirdparty/capstone/arch/X86/X86MappingInsn.inc b/thirdparty/capstone/arch/X86/X86MappingInsn.inc new file mode 100644 index 0000000..0703eb8 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86MappingInsn.inc @@ -0,0 +1,105977 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + + +{ + X86_AAA, X86_INS_AAA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_AAD8i8, X86_INS_AAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_AAM8i8, X86_INS_AAM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_AAS, X86_INS_AAS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_ABS_F, X86_INS_FABS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ABS_Fp32, X86_INS_FABS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ABS_Fp64, X86_INS_FABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ABS_Fp80, X86_INS_FABS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16i16, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16mi, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16mi8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16mr, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16ri, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16ri8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16rm, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16rr, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16rr_REV, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32i32, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32mi, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32mi8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32mr, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32ri, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32ri8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32rm, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32rr, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32rr_REV, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64i32, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64mi32, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64mi8, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64mr, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64ri32, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64ri8, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64rm, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64rr, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64rr_REV, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8i8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8mi, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8mi8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8mr, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8ri, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8ri8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8rm, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8rr, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8rr_REV, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADCX32rm, X86_INS_ADCX, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADCX32rr, X86_INS_ADCX, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADCX64rm, X86_INS_ADCX, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADCX64rr, X86_INS_ADCX, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16i16, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16mi, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16mi8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16mr, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16ri, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16ri8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16rm, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16rr, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16rr_REV, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32i32, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32mi, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32mi8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32mr, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32ri, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32ri8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32rm, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32rr, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32rr_REV, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64i32, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64mi32, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64mi8, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64mr, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64ri32, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64ri8, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64rm, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64rr, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64rr_REV, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8i8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8mi, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8mi8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8mr, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8ri, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8ri8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8rm, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8rr, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8rr_REV, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADDPDrm, X86_INS_ADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDPDrr, X86_INS_ADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDPSrm, X86_INS_ADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDPSrr, X86_INS_ADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDSDrm, X86_INS_ADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDSDrm_Int, X86_INS_ADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDSDrr, X86_INS_ADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDSDrr_Int, X86_INS_ADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDSSrm, X86_INS_ADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDSSrm_Int, X86_INS_ADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDSSrr, X86_INS_ADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDSSrr_Int, X86_INS_ADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDSUBPDrm, X86_INS_ADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDSUBPDrr, X86_INS_ADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDSUBPSrm, X86_INS_ADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_ADDSUBPSrr, X86_INS_ADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_F32m, X86_INS_FADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_F64m, X86_INS_FADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_FI16m, X86_INS_FIADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_FI32m, X86_INS_FIADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_FPrST0, X86_INS_FADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_FST0r, X86_INS_FADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_Fp32, X86_INS_FADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_Fp32m, X86_INS_FADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_Fp64, X86_INS_FADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_Fp64m, X86_INS_FADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_Fp64m32, X86_INS_FADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_Fp80, X86_INS_FADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_Fp80m32, X86_INS_FADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_Fp80m64, X86_INS_FADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_FpI16m32, X86_INS_FADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_FpI16m64, X86_INS_FADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_FpI16m80, X86_INS_FADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_FpI32m32, X86_INS_FADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_FpI32m64, X86_INS_FADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_FpI32m80, X86_INS_FADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD_FrST0, X86_INS_FADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ADOX32rm, X86_INS_ADOX, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADOX32rr, X86_INS_ADOX, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADOX64rm, X86_INS_ADOX, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADOX64rr, X86_INS_ADOX, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_AESDECLASTrm, X86_INS_AESDECLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_AESDECLASTrr, X86_INS_AESDECLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_AESDECrm, X86_INS_AESDEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_AESDECrr, X86_INS_AESDEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_AESENCLASTrm, X86_INS_AESENCLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_AESENCLASTrr, X86_INS_AESENCLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_AESENCrm, X86_INS_AESENC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_AESENCrr, X86_INS_AESENC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_AESIMCrm, X86_INS_AESIMC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_AESIMCrr, X86_INS_AESIMC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_AESKEYGENASSIST128rm, X86_INS_AESKEYGENASSIST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_AESKEYGENASSIST128rr, X86_INS_AESKEYGENASSIST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_AND16i16, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16mi, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16mi8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16mr, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16ri, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16ri8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16rm, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16rr, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16rr_REV, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32i32, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32mi, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32mi8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32mr, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32ri, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32ri8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32rm, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32rr, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32rr_REV, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64i32, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64mi32, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64mi8, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64mr, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64ri32, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64ri8, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64rm, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64rr, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64rr_REV, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8i8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8mi, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8mi8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_AND8mr, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8ri, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8ri8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_AND8rm, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8rr, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8rr_REV, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ANDN32rm, X86_INS_ANDN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDN32rr, X86_INS_ANDN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDN64rm, X86_INS_ANDN, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDN64rr, X86_INS_ANDN, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDNPDrm, X86_INS_ANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDNPDrr, X86_INS_ANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDNPSrm, X86_INS_ANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDNPSrr, X86_INS_ANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDPDrm, X86_INS_ANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDPDrr, X86_INS_ANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDPSrm, X86_INS_ANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDPSrr, X86_INS_ANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_ARPL16mr, X86_INS_ARPL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_ARPL16rr, X86_INS_ARPL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTR32rm, X86_INS_BEXTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTR32rr, X86_INS_BEXTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTR64rm, X86_INS_BEXTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTR64rr, X86_INS_BEXTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTRI32mi, X86_INS_BEXTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTRI32ri, X86_INS_BEXTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTRI64mi, X86_INS_BEXTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTRI64ri, X86_INS_BEXTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCFILL32rm, X86_INS_BLCFILL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCFILL32rr, X86_INS_BLCFILL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCFILL64rm, X86_INS_BLCFILL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCFILL64rr, X86_INS_BLCFILL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCI32rm, X86_INS_BLCI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCI32rr, X86_INS_BLCI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCI64rm, X86_INS_BLCI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCI64rr, X86_INS_BLCI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCIC32rm, X86_INS_BLCIC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCIC32rr, X86_INS_BLCIC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCIC64rm, X86_INS_BLCIC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCIC64rr, X86_INS_BLCIC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCMSK32rm, X86_INS_BLCMSK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCMSK32rr, X86_INS_BLCMSK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCMSK64rm, X86_INS_BLCMSK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCMSK64rr, X86_INS_BLCMSK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCS32rm, X86_INS_BLCS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCS32rr, X86_INS_BLCS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCS64rm, X86_INS_BLCS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCS64rr, X86_INS_BLCS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLENDPDrmi, X86_INS_BLENDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_BLENDPDrri, X86_INS_BLENDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_BLENDPSrmi, X86_INS_BLENDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_BLENDPSrri, X86_INS_BLENDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_BLENDVPDrm0, X86_INS_BLENDVPD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_BLENDVPDrr0, X86_INS_BLENDVPD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_BLENDVPSrm0, X86_INS_BLENDVPS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_BLENDVPSrr0, X86_INS_BLENDVPS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSFILL32rm, X86_INS_BLSFILL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSFILL32rr, X86_INS_BLSFILL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSFILL64rm, X86_INS_BLSFILL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSFILL64rr, X86_INS_BLSFILL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSI32rm, X86_INS_BLSI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSI32rr, X86_INS_BLSI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSI64rm, X86_INS_BLSI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSI64rr, X86_INS_BLSI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSIC32rm, X86_INS_BLSIC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSIC32rr, X86_INS_BLSIC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSIC64rm, X86_INS_BLSIC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSIC64rr, X86_INS_BLSIC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSMSK32rm, X86_INS_BLSMSK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSMSK32rr, X86_INS_BLSMSK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSMSK64rm, X86_INS_BLSMSK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSMSK64rr, X86_INS_BLSMSK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSR32rm, X86_INS_BLSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSR32rr, X86_INS_BLSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSR64rm, X86_INS_BLSR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSR64rr, X86_INS_BLSR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BNDCL32rm, X86_INS_BNDCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDCL32rr, X86_INS_BNDCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDCL64rm, X86_INS_BNDCL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDCL64rr, X86_INS_BNDCL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDCN32rm, X86_INS_BNDCN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDCN32rr, X86_INS_BNDCN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDCN64rm, X86_INS_BNDCN, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDCN64rr, X86_INS_BNDCN, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDCU32rm, X86_INS_BNDCU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDCU32rr, X86_INS_BNDCU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDCU64rm, X86_INS_BNDCU, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDCU64rr, X86_INS_BNDCU, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDLDXrm, X86_INS_BNDLDX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDMK32rm, X86_INS_BNDMK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDMK64rm, X86_INS_BNDMK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDMOV32mr, X86_INS_BNDMOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDMOV32rm, X86_INS_BNDMOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDMOV64mr, X86_INS_BNDMOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDMOV64rm, X86_INS_BNDMOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDMOVrr, X86_INS_BNDMOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDMOVrr_REV, X86_INS_BNDMOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BNDSTXmr, X86_INS_BNDSTX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BOUNDS16rm, X86_INS_BOUND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_BOUNDS32rm, X86_INS_BOUND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_BSF16rm, X86_INS_BSF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSF16rr, X86_INS_BSF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSF32rm, X86_INS_BSF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSF32rr, X86_INS_BSF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSF64rm, X86_INS_BSF, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSF64rr, X86_INS_BSF, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSR16rm, X86_INS_BSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSR16rr, X86_INS_BSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSR32rm, X86_INS_BSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSR32rr, X86_INS_BSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSR64rm, X86_INS_BSR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSR64rr, X86_INS_BSR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSWAP16r_BAD, X86_INS_BSWAP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSWAP32r, X86_INS_BSWAP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSWAP64r, X86_INS_BSWAP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT16mi8, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT16mr, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT16ri8, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT16rr, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT32mi8, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT32mr, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT32ri8, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT32rr, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT64mi8, X86_INS_BT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT64mr, X86_INS_BT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT64ri8, X86_INS_BT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT64rr, X86_INS_BT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC16mi8, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC16mr, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC16ri8, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC16rr, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC32mi8, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC32mr, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC32ri8, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC32rr, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC64mi8, X86_INS_BTC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC64mr, X86_INS_BTC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC64ri8, X86_INS_BTC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC64rr, X86_INS_BTC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR16mi8, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR16mr, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR16ri8, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR16rr, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR32mi8, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR32mr, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR32ri8, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR32rr, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR64mi8, X86_INS_BTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR64mr, X86_INS_BTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR64ri8, X86_INS_BTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR64rr, X86_INS_BTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS16mi8, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS16mr, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS16ri8, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS16rr, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS32mi8, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS32mr, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS32ri8, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS32rr, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS64mi8, X86_INS_BTS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS64mr, X86_INS_BTS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS64ri8, X86_INS_BTS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS64rr, X86_INS_BTS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BZHI32rm, X86_INS_BZHI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_BZHI32rr, X86_INS_BZHI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_BZHI64rm, X86_INS_BZHI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_BZHI64rr, X86_INS_BZHI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL16m, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL16m_NT, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CALL16r, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL16r_NT, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CALL32m, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL32m_NT, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CALL32r, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL32r_NT, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CALL64m, X86_INS_CALL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL64m_NT, X86_INS_CALL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CALL64pcrel32, X86_INS_CALL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, X86_REG_RIP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_BRANCH_RELATIVE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL64r, X86_INS_CALL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL64r_NT, X86_INS_CALL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CALLpcrel16, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, X86_REG_EIP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_BRANCH_RELATIVE, 0 }, 0, 0 +#endif +}, + +{ + X86_CALLpcrel32, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, X86_REG_EIP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_BRANCH_RELATIVE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CBW, X86_INS_CBW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CDQ, X86_INS_CDQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CDQE, X86_INS_CDQE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { X86_REG_RAX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CHS_F, X86_INS_FCHS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_CHS_Fp32, X86_INS_FCHS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CHS_Fp64, X86_INS_FCHS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CHS_Fp80, X86_INS_FCHS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLAC, X86_INS_CLAC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_CLC, X86_INS_CLC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLD, X86_INS_CLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLDEMOTE, X86_INS_CLDEMOTE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLFLUSH, X86_INS_CLFLUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CLFLUSHOPT, X86_INS_CLFLUSHOPT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLGI, X86_INS_CLGI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_CLI, X86_INS_CLI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_CLRSSBSY, X86_INS_CLRSSBSY, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLTS, X86_INS_CLTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLWB, X86_INS_CLWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLZEROr, X86_INS_CLZERO, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMC, X86_INS_CMC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVA16rm, X86_INS_CMOVA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVA16rr, X86_INS_CMOVA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVA32rm, X86_INS_CMOVA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVA32rr, X86_INS_CMOVA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVA64rm, X86_INS_CMOVA, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVA64rr, X86_INS_CMOVA, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVAE16rm, X86_INS_CMOVAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVAE16rr, X86_INS_CMOVAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVAE32rm, X86_INS_CMOVAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVAE32rr, X86_INS_CMOVAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVAE64rm, X86_INS_CMOVAE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVAE64rr, X86_INS_CMOVAE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB16rm, X86_INS_CMOVB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB16rr, X86_INS_CMOVB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB32rm, X86_INS_CMOVB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB32rr, X86_INS_CMOVB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB64rm, X86_INS_CMOVB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB64rr, X86_INS_CMOVB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE16rm, X86_INS_CMOVBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE16rr, X86_INS_CMOVBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE32rm, X86_INS_CMOVBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE32rr, X86_INS_CMOVBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE64rm, X86_INS_CMOVBE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE64rr, X86_INS_CMOVBE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE_F, X86_INS_FCMOVBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE_Fp32, X86_INS_FCMOVBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE_Fp64, X86_INS_FCMOVBE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE_Fp80, X86_INS_FCMOVBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB_F, X86_INS_FCMOVB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB_Fp32, X86_INS_FCMOVB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB_Fp64, X86_INS_FCMOVB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB_Fp80, X86_INS_FCMOVB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE16rm, X86_INS_CMOVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE16rr, X86_INS_CMOVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE32rm, X86_INS_CMOVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE32rr, X86_INS_CMOVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE64rm, X86_INS_CMOVE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE64rr, X86_INS_CMOVE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE_F, X86_INS_FCMOVE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE_Fp32, X86_INS_FCMOVE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE_Fp64, X86_INS_FCMOVE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE_Fp80, X86_INS_FCMOVE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVG16rm, X86_INS_CMOVG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVG16rr, X86_INS_CMOVG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVG32rm, X86_INS_CMOVG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVG32rr, X86_INS_CMOVG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVG64rm, X86_INS_CMOVG, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVG64rr, X86_INS_CMOVG, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVGE16rm, X86_INS_CMOVGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVGE16rr, X86_INS_CMOVGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVGE32rm, X86_INS_CMOVGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVGE32rr, X86_INS_CMOVGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVGE64rm, X86_INS_CMOVGE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVGE64rr, X86_INS_CMOVGE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVL16rm, X86_INS_CMOVL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVL16rr, X86_INS_CMOVL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVL32rm, X86_INS_CMOVL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVL32rr, X86_INS_CMOVL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVL64rm, X86_INS_CMOVL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVL64rr, X86_INS_CMOVL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVLE16rm, X86_INS_CMOVLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVLE16rr, X86_INS_CMOVLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVLE32rm, X86_INS_CMOVLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVLE32rr, X86_INS_CMOVLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVLE64rm, X86_INS_CMOVLE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVLE64rr, X86_INS_CMOVLE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNBE_F, X86_INS_FCMOVNBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNBE_Fp32, X86_INS_FCMOVNBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNBE_Fp64, X86_INS_FCMOVNBE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNBE_Fp80, X86_INS_FCMOVNBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNB_F, X86_INS_FCMOVNB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNB_Fp32, X86_INS_FCMOVNB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNB_Fp64, X86_INS_FCMOVNB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNB_Fp80, X86_INS_FCMOVNB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE16rm, X86_INS_CMOVNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE16rr, X86_INS_CMOVNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE32rm, X86_INS_CMOVNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE32rr, X86_INS_CMOVNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE64rm, X86_INS_CMOVNE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE64rr, X86_INS_CMOVNE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE_F, X86_INS_FCMOVNE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE_Fp32, X86_INS_FCMOVNE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE_Fp64, X86_INS_FCMOVNE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE_Fp80, X86_INS_FCMOVNE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNO16rm, X86_INS_CMOVNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNO16rr, X86_INS_CMOVNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNO32rm, X86_INS_CMOVNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNO32rr, X86_INS_CMOVNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNO64rm, X86_INS_CMOVNO, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNO64rr, X86_INS_CMOVNO, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP16rm, X86_INS_CMOVNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP16rr, X86_INS_CMOVNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP32rm, X86_INS_CMOVNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP32rr, X86_INS_CMOVNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP64rm, X86_INS_CMOVNP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP64rr, X86_INS_CMOVNP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP_F, X86_INS_FCMOVNU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP_Fp32, X86_INS_FCMOVNP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP_Fp64, X86_INS_FCMOVNU, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP_Fp80, X86_INS_FCMOVNU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNS16rm, X86_INS_CMOVNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNS16rr, X86_INS_CMOVNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNS32rm, X86_INS_CMOVNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNS32rr, X86_INS_CMOVNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNS64rm, X86_INS_CMOVNS, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNS64rr, X86_INS_CMOVNS, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVO16rm, X86_INS_CMOVO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVO16rr, X86_INS_CMOVO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVO32rm, X86_INS_CMOVO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVO32rr, X86_INS_CMOVO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVO64rm, X86_INS_CMOVO, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVO64rr, X86_INS_CMOVO, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP16rm, X86_INS_CMOVP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP16rr, X86_INS_CMOVP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP32rm, X86_INS_CMOVP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP32rr, X86_INS_CMOVP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP64rm, X86_INS_CMOVP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP64rr, X86_INS_CMOVP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP_F, X86_INS_FCMOVU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP_Fp32, X86_INS_FCMOVU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP_Fp64, X86_INS_FCMOVU, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP_Fp80, X86_INS_FCMOVU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVS16rm, X86_INS_CMOVS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVS16rr, X86_INS_CMOVS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVS32rm, X86_INS_CMOVS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVS32rr, X86_INS_CMOVS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVS64rm, X86_INS_CMOVS, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVS64rr, X86_INS_CMOVS, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16i16, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16mi, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16mi8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16mr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16ri, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16ri8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16rm, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16rr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16rr_REV, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32i32, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32mi, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32mi8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32mr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32ri, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32ri8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32rm, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32rr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32rr_REV, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64i32, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64mi32, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64mi8, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64mr, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64ri32, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64ri8, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64rm, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64rr, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64rr_REV, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8i8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8mi, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8mi8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8mr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8ri, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8ri8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8rm, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8rr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8rr_REV, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPPDrmi, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPPDrmi_alt, X86_INS_CMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPPDrri, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPPDrri_alt, X86_INS_CMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPPSrmi, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPPSrmi_alt, X86_INS_CMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPPSrri, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPPSrri_alt, X86_INS_CMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSB, X86_INS_CMPSB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSDrm, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSDrm_Int, X86_INS_CMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSDrm_alt, X86_INS_CMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSDrr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSDrr_Int, X86_INS_CMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSDrr_alt, X86_INS_CMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSL, X86_INS_CMPSD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSQ, X86_INS_CMPSQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSSrm, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSSrm_Int, X86_INS_CMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSSrm_alt, X86_INS_CMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSSrr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSSrr_Int, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSSrr_alt, X86_INS_CMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSW, X86_INS_CMPSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG16B, X86_INS_CMPXCHG16B, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG16rm, X86_INS_CMPXCHG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG16rr, X86_INS_CMPXCHG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG32rm, X86_INS_CMPXCHG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG32rr, X86_INS_CMPXCHG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG64rm, X86_INS_CMPXCHG, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG64rr, X86_INS_CMPXCHG, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG8B, X86_INS_CMPXCHG8B, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG8rm, X86_INS_CMPXCHG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG8rr, X86_INS_CMPXCHG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_COMISDrm, X86_INS_COMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_COMISDrm_Int, X86_INS_COMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_COMISDrr, X86_INS_COMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_COMISDrr_Int, X86_INS_COMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_COMISSrm, X86_INS_COMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_COMISSrm_Int, X86_INS_COMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_COMISSrr, X86_INS_COMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_COMISSrr_Int, X86_INS_COMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_COMP_FST0r, X86_INS_FCOMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_COM_FIPr, X86_INS_FCOMPI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_COM_FIr, X86_INS_FCOMI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_COM_FST0r, X86_INS_FCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_COS_F, X86_INS_FCOS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_COS_Fp32, X86_INS_FCOS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_COS_Fp64, X86_INS_FCOS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_COS_Fp80, X86_INS_FCOS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CPUID, X86_INS_CPUID, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_ECX, 0 }, { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CQO, X86_INS_CQO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CRC32r32m16, X86_INS_CRC32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_CRC32r32m32, X86_INS_CRC32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_CRC32r32m8, X86_INS_CRC32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_CRC32r32r16, X86_INS_CRC32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_CRC32r32r32, X86_INS_CRC32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_CRC32r32r8, X86_INS_CRC32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_CRC32r64m64, X86_INS_CRC32, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_CRC32r64m8, X86_INS_CRC32, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_CRC32r64r64, X86_INS_CRC32, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_CRC32r64r8, X86_INS_CRC32, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTDQ2PDrm, X86_INS_CVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTDQ2PDrr, X86_INS_CVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTDQ2PSrm, X86_INS_CVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTDQ2PSrr, X86_INS_CVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTPD2DQrm, X86_INS_CVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTPD2DQrr, X86_INS_CVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTPD2PSrm, X86_INS_CVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTPD2PSrr, X86_INS_CVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTPS2DQrm, X86_INS_CVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTPS2DQrr, X86_INS_CVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTPS2PDrm, X86_INS_CVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTPS2PDrr, X86_INS_CVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSD2SI64rm_Int, X86_INS_CVTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSD2SI64rr_Int, X86_INS_CVTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSD2SIrm_Int, X86_INS_CVTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSD2SIrr_Int, X86_INS_CVTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSD2SSrm, X86_INS_CVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSD2SSrm_Int, X86_INS_CVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSD2SSrr, X86_INS_CVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSD2SSrr_Int, X86_INS_CVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI2SDrm, X86_INS_CVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI2SDrm_Int, X86_INS_CVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI2SDrr, X86_INS_CVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI2SDrr_Int, X86_INS_CVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI2SSrm, X86_INS_CVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI2SSrm_Int, X86_INS_CVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI2SSrr, X86_INS_CVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI2SSrr_Int, X86_INS_CVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI642SDrm, X86_INS_CVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI642SDrm_Int, X86_INS_CVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI642SDrr, X86_INS_CVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI642SDrr_Int, X86_INS_CVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI642SSrm, X86_INS_CVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI642SSrm_Int, X86_INS_CVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI642SSrr, X86_INS_CVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSI642SSrr_Int, X86_INS_CVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSS2SDrm, X86_INS_CVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSS2SDrm_Int, X86_INS_CVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSS2SDrr, X86_INS_CVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSS2SDrr_Int, X86_INS_CVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSS2SI64rm_Int, X86_INS_CVTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSS2SI64rr_Int, X86_INS_CVTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSS2SIrm_Int, X86_INS_CVTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTSS2SIrr_Int, X86_INS_CVTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTPD2DQrm, X86_INS_CVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTPD2DQrr, X86_INS_CVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTPS2DQrm, X86_INS_CVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTPS2DQrr, X86_INS_CVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSD2SI64rm, X86_INS_CVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSD2SI64rm_Int, X86_INS_CVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSD2SI64rr, X86_INS_CVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSD2SI64rr_Int, X86_INS_CVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSD2SIrm, X86_INS_CVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSD2SIrm_Int, X86_INS_CVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSD2SIrr, X86_INS_CVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSD2SIrr_Int, X86_INS_CVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSS2SI64rm, X86_INS_CVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSS2SI64rm_Int, X86_INS_CVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSS2SI64rr, X86_INS_CVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSS2SI64rr_Int, X86_INS_CVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSS2SIrm, X86_INS_CVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSS2SIrm_Int, X86_INS_CVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSS2SIrr, X86_INS_CVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_CVTTSS2SIrr_Int, X86_INS_CVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CWD, X86_INS_CWD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CWDE, X86_INS_CWDE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DAA, X86_INS_DAA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_DAS, X86_INS_DAS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_DATA16_PREFIX, X86_INS_DATA16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC16m, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC16r, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC16r_alt, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_DEC32m, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC32r, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC32r_alt, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_DEC64m, X86_INS_DEC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC64r, X86_INS_DEC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC8m, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC8r, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV16m, X86_INS_DIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV16r, X86_INS_DIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV32m, X86_INS_DIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV32r, X86_INS_DIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV64m, X86_INS_DIV, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV64r, X86_INS_DIV, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV8m, X86_INS_DIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV8r, X86_INS_DIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIVPDrm, X86_INS_DIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVPDrr, X86_INS_DIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVPSrm, X86_INS_DIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVPSrr, X86_INS_DIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_F32m, X86_INS_FDIVR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_F64m, X86_INS_FDIVR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_FI16m, X86_INS_FIDIVR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_FI32m, X86_INS_FIDIVR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_FPrST0, X86_INS_FDIVRP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_FST0r, X86_INS_FDIVR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_Fp32m, X86_INS_FDIVR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_Fp64m, X86_INS_FDIVR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_Fp64m32, X86_INS_FDIVR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_Fp80m32, X86_INS_FDIVR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_Fp80m64, X86_INS_FDIVR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_FpI16m32, X86_INS_FDIVR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_FpI16m64, X86_INS_FDIVR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_FpI16m80, X86_INS_FDIVR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_FpI32m32, X86_INS_FDIVR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_FpI32m64, X86_INS_FDIVR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_FpI32m80, X86_INS_FDIVR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIVR_FrST0, X86_INS_FDIVR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVSDrm, X86_INS_DIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVSDrm_Int, X86_INS_DIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVSDrr, X86_INS_DIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVSDrr_Int, X86_INS_DIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVSSrm, X86_INS_DIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVSSrm_Int, X86_INS_DIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVSSrr, X86_INS_DIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_DIVSSrr_Int, X86_INS_DIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_F32m, X86_INS_FDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_F64m, X86_INS_FDIV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_FI16m, X86_INS_FIDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_FI32m, X86_INS_FIDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_FPrST0, X86_INS_FDIVP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_FST0r, X86_INS_FDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_Fp32, X86_INS_FDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_Fp32m, X86_INS_FDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_Fp64, X86_INS_FDIV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_Fp64m, X86_INS_FDIV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_Fp64m32, X86_INS_FDIV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_Fp80, X86_INS_FDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_Fp80m32, X86_INS_FDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_Fp80m64, X86_INS_FDIV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_FpI16m32, X86_INS_FDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_FpI16m64, X86_INS_FDIV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_FpI16m80, X86_INS_FDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_FpI32m32, X86_INS_FDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_FpI32m64, X86_INS_FDIV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_FpI32m80, X86_INS_FDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV_FrST0, X86_INS_FDIV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_DPPDrmi, X86_INS_DPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_DPPDrri, X86_INS_DPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_DPPSrmi, X86_INS_DPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_DPPSrri, X86_INS_DPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_ENCLS, X86_INS_ENCLS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ENCLU, X86_INS_ENCLU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ENCLV, X86_INS_ENCLV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ENDBR32, X86_INS_ENDBR32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ENDBR64, X86_INS_ENDBR64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ENTER, X86_INS_ENTER, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_EXTRACTPSmr, X86_INS_EXTRACTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_EXTRACTPSrr, X86_INS_EXTRACTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_EXTRQ, X86_INS_EXTRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 +#endif +}, + +{ + X86_EXTRQI, X86_INS_EXTRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 +#endif +}, + +{ + X86_F2XM1, X86_INS_F2XM1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FARCALL16i, X86_INS_LCALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_FARCALL16m, X86_INS_LCALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, 0 }, 0, 0 +#endif +}, + +{ + X86_FARCALL32i, X86_INS_LCALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_FARCALL32m, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, 0 }, 0, 0 +#endif +}, + +{ + X86_FARCALL64, X86_INS_LCALL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { 0 }, { X86_GRP_CALL, 0 }, 0, 0 +#endif +}, + +{ + X86_FARJMP16i, X86_INS_LJMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 +#endif +}, + +{ + X86_FARJMP16m, X86_INS_LJMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, + +{ + X86_FARJMP32i, X86_INS_LJMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 +#endif +}, + +{ + X86_FARJMP32m, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, + +{ + X86_FARJMP64, X86_INS_LJMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, + +{ + X86_FBLDm, X86_INS_FBLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FBSTPm, X86_INS_FBSTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FCOM32m, X86_INS_FCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FCOM64m, X86_INS_FCOM, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FCOMP32m, X86_INS_FCOMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FCOMP64m, X86_INS_FCOMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FCOMPP, X86_INS_FCOMPP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FDECSTP, X86_INS_FDECSTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FDISI8087_NOP, X86_INS_FDISI8087_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FEMMS, X86_INS_FEMMS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_FENI8087_NOP, X86_INS_FENI8087_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FFREE, X86_INS_FFREE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FFREEP, X86_INS_FFREEP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FICOM16m, X86_INS_FICOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FICOM32m, X86_INS_FICOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FICOMP16m, X86_INS_FICOMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FICOMP32m, X86_INS_FICOMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FINCSTP, X86_INS_FINCSTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FLDCW16m, X86_INS_FLDCW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FLDENVm, X86_INS_FLDENV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FLDL2E, X86_INS_FLDL2E, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FLDL2T, X86_INS_FLDL2T, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FLDLG2, X86_INS_FLDLG2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FLDLN2, X86_INS_FLDLN2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FLDPI, X86_INS_FLDPI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FNCLEX, X86_INS_FNCLEX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FNINIT, X86_INS_FNINIT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FNOP, X86_INS_FNOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FNSTCW16m, X86_INS_FNSTCW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FNSTSW16r, X86_INS_FNSTSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_FPSW, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FNSTSWm, X86_INS_FNSTSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FPATAN, X86_INS_FPATAN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FPNCEST0r, X86_INS_FSTPNCE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FPREM, X86_INS_FPREM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FPREM1, X86_INS_FPREM1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FPTAN, X86_INS_FPTAN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FRNDINT, X86_INS_FRNDINT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FRSTORm, X86_INS_FRSTOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FSAVEm, X86_INS_FNSAVE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FSCALE, X86_INS_FSCALE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FSETPM, X86_INS_FSETPM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FSINCOS, X86_INS_FSINCOS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FSTENVm, X86_INS_FNSTENV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FXAM, X86_INS_FXAM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FXRSTOR, X86_INS_FXRSTOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FXRSTOR64, X86_INS_FXRSTOR64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_FXSAVE, X86_INS_FXSAVE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FXSAVE64, X86_INS_FXSAVE64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_FXTRACT, X86_INS_FXTRACT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FYL2X, X86_INS_FYL2X, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_FYL2XP1, X86_INS_FYL2XP1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_GETSEC, X86_INS_GETSEC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_GF2P8AFFINEINVQBrmi, X86_INS_GF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_GF2P8AFFINEINVQBrri, X86_INS_GF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_GF2P8AFFINEQBrmi, X86_INS_GF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_GF2P8AFFINEQBrri, X86_INS_GF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_GF2P8MULBrm, X86_INS_GF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_GF2P8MULBrr, X86_INS_GF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_HADDPDrm, X86_INS_HADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_HADDPDrr, X86_INS_HADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_HADDPSrm, X86_INS_HADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_HADDPSrr, X86_INS_HADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_HLT, X86_INS_HLT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_HSUBPDrm, X86_INS_HSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_HSUBPDrr, X86_INS_HSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_HSUBPSrm, X86_INS_HSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_HSUBPSrr, X86_INS_HSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV16m, X86_INS_IDIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV16r, X86_INS_IDIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV32m, X86_INS_IDIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV32r, X86_INS_IDIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV64m, X86_INS_IDIV, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV64r, X86_INS_IDIV, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV8m, X86_INS_IDIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV8r, X86_INS_IDIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ILD_F16m, X86_INS_FILD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ILD_F32m, X86_INS_FILD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ILD_F64m, X86_INS_FILD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ILD_Fp16m32, X86_INS_FILD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ILD_Fp16m64, X86_INS_FILD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ILD_Fp16m80, X86_INS_FILD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ILD_Fp32m32, X86_INS_FILD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ILD_Fp32m64, X86_INS_FILD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ILD_Fp32m80, X86_INS_FILD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ILD_Fp64m32, X86_INS_FILD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ILD_Fp64m64, X86_INS_FILD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ILD_Fp64m80, X86_INS_FILD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16m, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16r, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16rm, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16rmi, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16rmi8, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16rr, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16rri, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16rri8, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32m, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32r, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32rm, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32rmi, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32rmi8, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32rr, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32rri, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32rri8, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64m, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64r, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64rm, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64rmi32, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64rmi8, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64rr, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64rri32, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64rri8, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL8m, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL8r, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IN16ri, X86_INS_IN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IN16rr, X86_INS_IN, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IN32ri, X86_INS_IN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IN32rr, X86_INS_IN, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IN8ri, X86_INS_IN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IN8rr, X86_INS_IN, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC16m, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC16r, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC16r_alt, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INC32m, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC32r, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC32r_alt, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INC64m, X86_INS_INC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC64r, X86_INS_INC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC8m, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC8r, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INCSSPD, X86_INS_INCSSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INCSSPQ, X86_INS_INCSSPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INSB, X86_INS_INSB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INSERTPSrm, X86_INS_INSERTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_INSERTPSrr, X86_INS_INSERTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_INSERTQ, X86_INS_INSERTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 +#endif +}, + +{ + X86_INSERTQI, X86_INS_INSERTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 +#endif +}, + +{ + X86_INSL, X86_INS_INSD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INSW, X86_INS_INSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INT, X86_INS_INT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 +#endif +}, + +{ + X86_INT1, X86_INS_INT1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_INT, 0 }, 0, 0 +#endif +}, + +{ + X86_INT3, X86_INS_INT3, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 +#endif +}, + +{ + X86_INTO, X86_INS_INTO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_INT, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVD, X86_INS_INVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVEPT32, X86_INS_INVEPT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVEPT64, X86_INS_INVEPT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_INVLPG, X86_INS_INVLPG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVLPGA32, X86_INS_INVLPGA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVLPGA64, X86_INS_INVLPGA, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_INVPCID32, X86_INS_INVPCID, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVPCID64, X86_INS_INVPCID, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_INVVPID32, X86_INS_INVVPID, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVVPID64, X86_INS_INVVPID, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_IRET16, X86_INS_IRET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 +#endif +}, + +{ + X86_IRET32, X86_INS_IRETD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 +#endif +}, + +{ + X86_IRET64, X86_INS_IRETQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_ISTT_FP16m, X86_INS_FISTTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ISTT_FP32m, X86_INS_FISTTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ISTT_FP64m, X86_INS_FISTTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ISTT_Fp16m32, X86_INS_FISTTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ISTT_Fp16m64, X86_INS_FISTTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ISTT_Fp16m80, X86_INS_FISTTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ISTT_Fp32m32, X86_INS_FISTTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ISTT_Fp32m64, X86_INS_FISTTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ISTT_Fp32m80, X86_INS_FISTTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ISTT_Fp64m32, X86_INS_FISTTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ISTT_Fp64m64, X86_INS_FISTTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ISTT_Fp64m80, X86_INS_FISTTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IST_F16m, X86_INS_FIST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_IST_F32m, X86_INS_FIST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_IST_FP16m, X86_INS_FISTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_IST_FP32m, X86_INS_FISTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_IST_FP64m, X86_INS_FISTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_IST_Fp16m32, X86_INS_FISTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IST_Fp16m64, X86_INS_FISTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IST_Fp16m80, X86_INS_FISTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IST_Fp32m32, X86_INS_FISTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IST_Fp32m64, X86_INS_FISTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IST_Fp32m80, X86_INS_FISTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IST_Fp64m32, X86_INS_FISTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IST_Fp64m64, X86_INS_FISTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IST_Fp64m80, X86_INS_FISTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JAE_1, X86_INS_JAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JAE_2, X86_INS_JAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JAE_4, X86_INS_JAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JA_1, X86_INS_JA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JA_2, X86_INS_JA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JA_4, X86_INS_JA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JBE_1, X86_INS_JBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JBE_2, X86_INS_JBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JBE_4, X86_INS_JBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JB_1, X86_INS_JB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JB_2, X86_INS_JB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JB_4, X86_INS_JB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JCXZ, X86_INS_JCXZ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CX, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JECXZ, X86_INS_JECXZ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ECX, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JE_1, X86_INS_JE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JE_2, X86_INS_JE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JE_4, X86_INS_JE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JGE_1, X86_INS_JGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JGE_2, X86_INS_JGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JGE_4, X86_INS_JGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JG_1, X86_INS_JG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JG_2, X86_INS_JG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JG_4, X86_INS_JG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JLE_1, X86_INS_JLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JLE_2, X86_INS_JLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JLE_4, X86_INS_JLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JL_1, X86_INS_JL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JL_2, X86_INS_JL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JL_4, X86_INS_JL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JMP16m, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 +#endif +}, + +{ + X86_JMP16m_NT, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JMP16r, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 +#endif +}, + +{ + X86_JMP16r_NT, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JMP32m, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 +#endif +}, + +{ + X86_JMP32m_NT, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JMP32r, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 +#endif +}, + +{ + X86_JMP32r_NT, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JMP64m, X86_INS_JMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 1 +#endif +}, + +{ + X86_JMP64m_NT, X86_INS_JMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JMP64r, X86_INS_JMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 1 +#endif +}, + +{ + X86_JMP64r_NT, X86_INS_JMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JMP_1, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JMP_2, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JMP_4, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JNE_1, X86_INS_JNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JNE_2, X86_INS_JNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JNE_4, X86_INS_JNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JNO_1, X86_INS_JNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JNO_2, X86_INS_JNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JNO_4, X86_INS_JNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JNP_1, X86_INS_JNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JNP_2, X86_INS_JNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JNP_4, X86_INS_JNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JNS_1, X86_INS_JNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JNS_2, X86_INS_JNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JNS_4, X86_INS_JNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JO_1, X86_INS_JO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JO_2, X86_INS_JO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JO_4, X86_INS_JO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JP_1, X86_INS_JP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JP_2, X86_INS_JP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JP_4, X86_INS_JP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JRCXZ, X86_INS_JRCXZ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RCX, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JS_1, X86_INS_JS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JS_2, X86_INS_JS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_JS_4, X86_INS_JS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, + +{ + X86_KADDBrr, X86_INS_KADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_KADDDrr, X86_INS_KADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_KADDQrr, X86_INS_KADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_KADDWrr, X86_INS_KADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_KANDBrr, X86_INS_KANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KANDDrr, X86_INS_KANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KANDNBrr, X86_INS_KANDNB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KANDNDrr, X86_INS_KANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KANDNQrr, X86_INS_KANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KANDNWrr, X86_INS_KANDNW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KANDQrr, X86_INS_KANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KANDWrr, X86_INS_KANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVBkk, X86_INS_KMOVB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVBkm, X86_INS_KMOVB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVBkr, X86_INS_KMOVB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVBmk, X86_INS_KMOVB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVBrk, X86_INS_KMOVB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVDkk, X86_INS_KMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVDkm, X86_INS_KMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVDkr, X86_INS_KMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVDmk, X86_INS_KMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVDrk, X86_INS_KMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVQkk, X86_INS_KMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVQkm, X86_INS_KMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVQkr, X86_INS_KMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVQmk, X86_INS_KMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVQrk, X86_INS_KMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVWkk, X86_INS_KMOVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVWkm, X86_INS_KMOVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVWkr, X86_INS_KMOVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVWmk, X86_INS_KMOVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KMOVWrk, X86_INS_KMOVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KNOTBrr, X86_INS_KNOTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KNOTDrr, X86_INS_KNOTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KNOTQrr, X86_INS_KNOTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KNOTWrr, X86_INS_KNOTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KORBrr, X86_INS_KORB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KORDrr, X86_INS_KORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KORQrr, X86_INS_KORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KORTESTBrr, X86_INS_KORTESTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KORTESTDrr, X86_INS_KORTESTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KORTESTQrr, X86_INS_KORTESTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KORTESTWrr, X86_INS_KORTESTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KORWrr, X86_INS_KORW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KSHIFTLBri, X86_INS_KSHIFTLB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KSHIFTLDri, X86_INS_KSHIFTLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KSHIFTLQri, X86_INS_KSHIFTLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KSHIFTLWri, X86_INS_KSHIFTLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KSHIFTRBri, X86_INS_KSHIFTRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KSHIFTRDri, X86_INS_KSHIFTRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KSHIFTRQri, X86_INS_KSHIFTRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KSHIFTRWri, X86_INS_KSHIFTRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KTESTBrr, X86_INS_KTESTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_KTESTDrr, X86_INS_KTESTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_KTESTQrr, X86_INS_KTESTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_KTESTWrr, X86_INS_KTESTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_KUNPCKBWrr, X86_INS_KUNPCKBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KUNPCKDQrr, X86_INS_KUNPCKDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_KUNPCKWDrr, X86_INS_KUNPCKWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_KXNORBrr, X86_INS_KXNORB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KXNORDrr, X86_INS_KXNORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KXNORQrr, X86_INS_KXNORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KXNORWrr, X86_INS_KXNORW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_KXORBrr, X86_INS_KXORB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_KXORDrr, X86_INS_KXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KXORQrr, X86_INS_KXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_KXORWrr, X86_INS_KXORW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_LAHF, X86_INS_LAHF, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_AH, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LAR16rm, X86_INS_LAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LAR16rr, X86_INS_LAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LAR32rm, X86_INS_LAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LAR32rr, X86_INS_LAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LAR64rm, X86_INS_LAR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LAR64rr, X86_INS_LAR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LDDQUrm, X86_INS_LDDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_LDMXCSR, X86_INS_LDMXCSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_LDS16rm, X86_INS_LDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LDS32rm, X86_INS_LDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_F0, X86_INS_FLDZ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_LD_F1, X86_INS_FLD1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_LD_F32m, X86_INS_FLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_LD_F64m, X86_INS_FLD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_LD_F80m, X86_INS_FLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Fp032, X86_INS_FLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Fp064, X86_INS_FLD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Fp080, X86_INS_FLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Fp132, X86_INS_FLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Fp164, X86_INS_FLD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Fp180, X86_INS_FLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Fp32m, X86_INS_FLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Fp32m64, X86_INS_FLD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Fp32m80, X86_INS_FLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Fp64m, X86_INS_FLD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Fp64m80, X86_INS_FLD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Fp80m, X86_INS_FLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LD_Frr, X86_INS_FLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_LEA16r, X86_INS_LEA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LEA32r, X86_INS_LEA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_LEA64_32r, X86_INS_LEA, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_LEA64r, X86_INS_LEA, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LEAVE, X86_INS_LEAVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EBP, X86_REG_ESP, 0 }, { X86_REG_EBP, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_LEAVE64, X86_INS_LEAVE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RBP, X86_REG_RSP, 0 }, { X86_REG_RBP, X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_LES16rm, X86_INS_LES, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LES32rm, X86_INS_LES, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LFENCE, X86_INS_LFENCE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_LFS16rm, X86_INS_LFS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LFS32rm, X86_INS_LFS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LFS64rm, X86_INS_LFS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LGDT16m, X86_INS_LGDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_LGDT32m, X86_INS_LGDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_LGDT64m, X86_INS_LGDT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_LGS16rm, X86_INS_LGS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LGS32rm, X86_INS_LGS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LGS64rm, X86_INS_LGS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LIDT16m, X86_INS_LIDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_LIDT32m, X86_INS_LIDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_LIDT64m, X86_INS_LIDT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_LLDT16m, X86_INS_LLDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_LLDT16r, X86_INS_LLDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_LLWPCB, X86_INS_LLWPCB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LLWPCB64, X86_INS_LLWPCB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LMSW16m, X86_INS_LMSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_LMSW16r, X86_INS_LMSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_LOCK_PREFIX, X86_INS_LOCK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LODSB, X86_INS_LODSB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_AL, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LODSL, X86_INS_LODSD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EAX, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LODSQ, X86_INS_LODSQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_RAX, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LODSW, X86_INS_LODSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_AX, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LOOP, X86_INS_LOOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 0, 0 +#endif +}, + +{ + X86_LOOPE, X86_INS_LOOPE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 0, 0 +#endif +}, + +{ + X86_LOOPNE, X86_INS_LOOPNE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 0, 0 +#endif +}, + +{ + X86_LRETIL, X86_INS_RETF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 +#endif +}, + +{ + X86_LRETIQ, X86_INS_RETFQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_LRETIW, X86_INS_RETF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 +#endif +}, + +{ + X86_LRETL, X86_INS_RETF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 +#endif +}, + +{ + X86_LRETQ, X86_INS_RETFQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_LRETW, X86_INS_RETF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 +#endif +}, + +{ + X86_LSL16rm, X86_INS_LSL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSL16rr, X86_INS_LSL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSL32rm, X86_INS_LSL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSL32rr, X86_INS_LSL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSL64rm, X86_INS_LSL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSL64rr, X86_INS_LSL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSS16rm, X86_INS_LSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSS32rm, X86_INS_LSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSS64rm, X86_INS_LSS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LTRm, X86_INS_LTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_LTRr, X86_INS_LTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_LWPINS32rmi, X86_INS_LWPINS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPINS32rri, X86_INS_LWPINS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPINS64rmi, X86_INS_LWPINS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPINS64rri, X86_INS_LWPINS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPVAL32rmi, X86_INS_LWPVAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPVAL32rri, X86_INS_LWPVAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPVAL64rmi, X86_INS_LWPVAL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPVAL64rri, X86_INS_LWPVAL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LZCNT16rm, X86_INS_LZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LZCNT16rr, X86_INS_LZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LZCNT32rm, X86_INS_LZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LZCNT32rr, X86_INS_LZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LZCNT64rm, X86_INS_LZCNT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LZCNT64rr, X86_INS_LZCNT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MASKMOVDQU, X86_INS_MASKMOVDQU, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, 0 }, { 0 }, { X86_GRP_SSE2, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_MASKMOVDQU64, X86_INS_MASKMOVDQU, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDI, 0 }, { 0 }, { X86_GRP_SSE2, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXCPDrm, X86_INS_MAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXCPDrr, X86_INS_MAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXCPSrm, X86_INS_MAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXCPSrr, X86_INS_MAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXCSDrm, X86_INS_MAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXCSDrr, X86_INS_MAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXCSSrm, X86_INS_MAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXCSSrr, X86_INS_MAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXPDrm, X86_INS_MAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXPDrr, X86_INS_MAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXPSrm, X86_INS_MAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXPSrr, X86_INS_MAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXSDrm, X86_INS_MAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXSDrm_Int, X86_INS_MAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXSDrr, X86_INS_MAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXSDrr_Int, X86_INS_MAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXSSrm, X86_INS_MAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXSSrm_Int, X86_INS_MAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXSSrr, X86_INS_MAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MAXSSrr_Int, X86_INS_MAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MFENCE, X86_INS_MFENCE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MINCPDrm, X86_INS_MINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MINCPDrr, X86_INS_MINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MINCPSrm, X86_INS_MINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MINCPSrr, X86_INS_MINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MINCSDrm, X86_INS_MINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MINCSDrr, X86_INS_MINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MINCSSrm, X86_INS_MINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MINCSSrr, X86_INS_MINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MINPDrm, X86_INS_MINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MINPDrr, X86_INS_MINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MINPSrm, X86_INS_MINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MINPSrr, X86_INS_MINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MINSDrm, X86_INS_MINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MINSDrm_Int, X86_INS_MINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MINSDrr, X86_INS_MINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MINSDrr_Int, X86_INS_MINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MINSSrm, X86_INS_MINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MINSSrm_Int, X86_INS_MINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MINSSrr, X86_INS_MINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MINSSrr_Int, X86_INS_MINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_CVTPD2PIirm, X86_INS_CVTPD2PI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_CVTPD2PIirr, X86_INS_CVTPD2PI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_CVTPI2PDirm, X86_INS_CVTPI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_CVTPI2PDirr, X86_INS_CVTPI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_CVTPI2PSirm, X86_INS_CVTPI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_CVTPI2PSirr, X86_INS_CVTPI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_CVTPS2PIirm, X86_INS_CVTPS2PI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_CVTPS2PIirr, X86_INS_CVTPS2PI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_CVTTPD2PIirm, X86_INS_CVTTPD2PI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_CVTTPD2PIirr, X86_INS_CVTTPD2PI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_CVTTPS2PIirm, X86_INS_CVTTPS2PI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_CVTTPS2PIirr, X86_INS_CVTTPS2PI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_EMMS, X86_INS_EMMS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MASKMOVQ, X86_INS_MASKMOVQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, 0 }, { 0 }, { X86_GRP_MMX, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MASKMOVQ64, X86_INS_MASKMOVQ, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDI, 0 }, { 0 }, { X86_GRP_MMX, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVD64from64rm, X86_INS_MOVD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVD64from64rr, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVD64grr, X86_INS_MOVD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVD64mr, X86_INS_MOVD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVD64rm, X86_INS_MOVD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVD64rr, X86_INS_MOVD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVD64to64rm, X86_INS_MOVD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVD64to64rr, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVDQ2Qrr, X86_INS_MOVDQ2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVFR642Qrr, X86_INS_MOVDQ2Q, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVNTQmr, X86_INS_MOVNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVQ2DQrr, X86_INS_MOVQ2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVQ2FR64rr, X86_INS_MOVQ2DQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVQ64mr, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVQ64rm, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVQ64rr, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_MOVQ64rr_REV, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PABSBrm, X86_INS_PABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PABSBrr, X86_INS_PABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PABSDrm, X86_INS_PABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PABSDrr, X86_INS_PABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PABSWrm, X86_INS_PABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PABSWrr, X86_INS_PABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PACKSSDWirm, X86_INS_PACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PACKSSDWirr, X86_INS_PACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PACKSSWBirm, X86_INS_PACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PACKSSWBirr, X86_INS_PACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PACKUSWBirm, X86_INS_PACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PACKUSWBirr, X86_INS_PACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDBirm, X86_INS_PADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDBirr, X86_INS_PADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDDirm, X86_INS_PADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDDirr, X86_INS_PADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDQirm, X86_INS_PADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDQirr, X86_INS_PADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDSBirm, X86_INS_PADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDSBirr, X86_INS_PADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDSWirm, X86_INS_PADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDSWirr, X86_INS_PADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDUSBirm, X86_INS_PADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDUSBirr, X86_INS_PADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDUSWirm, X86_INS_PADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDUSWirr, X86_INS_PADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDWirm, X86_INS_PADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PADDWirr, X86_INS_PADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PALIGNRrmi, X86_INS_PALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PALIGNRrri, X86_INS_PALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PANDNirm, X86_INS_PANDN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PANDNirr, X86_INS_PANDN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PANDirm, X86_INS_PAND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PANDirr, X86_INS_PAND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PAVGBirm, X86_INS_PAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PAVGBirr, X86_INS_PAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PAVGWirm, X86_INS_PAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PAVGWirr, X86_INS_PAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PCMPEQBirm, X86_INS_PCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PCMPEQBirr, X86_INS_PCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PCMPEQDirm, X86_INS_PCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PCMPEQDirr, X86_INS_PCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PCMPEQWirm, X86_INS_PCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PCMPEQWirr, X86_INS_PCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PCMPGTBirm, X86_INS_PCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PCMPGTBirr, X86_INS_PCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PCMPGTDirm, X86_INS_PCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PCMPGTDirr, X86_INS_PCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PCMPGTWirm, X86_INS_PCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PCMPGTWirr, X86_INS_PCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PEXTRWrr, X86_INS_PEXTRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PHADDDrm, X86_INS_PHADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PHADDDrr, X86_INS_PHADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PHADDSWrm, X86_INS_PHADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PHADDSWrr, X86_INS_PHADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PHADDWrm, X86_INS_PHADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PHADDWrr, X86_INS_PHADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PHSUBDrm, X86_INS_PHSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PHSUBDrr, X86_INS_PHSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PHSUBSWrm, X86_INS_PHSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PHSUBSWrr, X86_INS_PHSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PHSUBWrm, X86_INS_PHSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PHSUBWrr, X86_INS_PHSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PINSRWrm, X86_INS_PINSRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PINSRWrr, X86_INS_PINSRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMADDUBSWrm, X86_INS_PMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMADDUBSWrr, X86_INS_PMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMADDWDirm, X86_INS_PMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMADDWDirr, X86_INS_PMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMAXSWirm, X86_INS_PMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMAXSWirr, X86_INS_PMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMAXUBirm, X86_INS_PMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMAXUBirr, X86_INS_PMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMINSWirm, X86_INS_PMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMINSWirr, X86_INS_PMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMINUBirm, X86_INS_PMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMINUBirr, X86_INS_PMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMOVMSKBrr, X86_INS_PMOVMSKB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMULHRSWrm, X86_INS_PMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMULHRSWrr, X86_INS_PMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMULHUWirm, X86_INS_PMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMULHUWirr, X86_INS_PMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMULHWirm, X86_INS_PMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMULHWirr, X86_INS_PMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMULLWirm, X86_INS_PMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMULLWirr, X86_INS_PMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMULUDQirm, X86_INS_PMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PMULUDQirr, X86_INS_PMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PORirm, X86_INS_POR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PORirr, X86_INS_POR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSADBWirm, X86_INS_PSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSADBWirr, X86_INS_PSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSHUFBrm, X86_INS_PSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSHUFBrr, X86_INS_PSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSHUFWmi, X86_INS_PSHUFW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSHUFWri, X86_INS_PSHUFW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSIGNBrm, X86_INS_PSIGNB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSIGNBrr, X86_INS_PSIGNB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSIGNDrm, X86_INS_PSIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSIGNDrr, X86_INS_PSIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSIGNWrm, X86_INS_PSIGNW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSIGNWrr, X86_INS_PSIGNW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSLLDri, X86_INS_PSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSLLDrm, X86_INS_PSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSLLDrr, X86_INS_PSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSLLQri, X86_INS_PSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSLLQrm, X86_INS_PSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSLLQrr, X86_INS_PSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSLLWri, X86_INS_PSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSLLWrm, X86_INS_PSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSLLWrr, X86_INS_PSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRADri, X86_INS_PSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRADrm, X86_INS_PSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRADrr, X86_INS_PSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRAWri, X86_INS_PSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRAWrm, X86_INS_PSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRAWrr, X86_INS_PSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRLDri, X86_INS_PSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRLDrm, X86_INS_PSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRLDrr, X86_INS_PSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRLQri, X86_INS_PSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRLQrm, X86_INS_PSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRLQrr, X86_INS_PSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRLWri, X86_INS_PSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRLWrm, X86_INS_PSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSRLWrr, X86_INS_PSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBBirm, X86_INS_PSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBBirr, X86_INS_PSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBDirm, X86_INS_PSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBDirr, X86_INS_PSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBQirm, X86_INS_PSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBQirr, X86_INS_PSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBSBirm, X86_INS_PSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBSBirr, X86_INS_PSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBSWirm, X86_INS_PSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBSWirr, X86_INS_PSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBUSBirm, X86_INS_PSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBUSBirr, X86_INS_PSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBUSWirm, X86_INS_PSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBUSWirr, X86_INS_PSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBWirm, X86_INS_PSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PSUBWirr, X86_INS_PSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PUNPCKHBWirm, X86_INS_PUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PUNPCKHBWirr, X86_INS_PUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PUNPCKHDQirm, X86_INS_PUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PUNPCKHDQirr, X86_INS_PUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PUNPCKHWDirm, X86_INS_PUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PUNPCKHWDirr, X86_INS_PUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PUNPCKLBWirm, X86_INS_PUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PUNPCKLBWirr, X86_INS_PUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PUNPCKLDQirm, X86_INS_PUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PUNPCKLDQirr, X86_INS_PUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PUNPCKLWDirm, X86_INS_PUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PUNPCKLWDirr, X86_INS_PUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PXORirm, X86_INS_PXOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MMX_PXORirr, X86_INS_PXOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 +#endif +}, + +{ + X86_MONITORXrrr, X86_INS_MONITORX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MONITORrrr, X86_INS_MONITOR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_MONTMUL, X86_INS_MONTMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RSI, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_RSI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16ao16, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16ao32, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16ao64, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16mi, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16mr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16ms, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16o16a, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16o32a, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16o64a, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16ri, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16ri_alt, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16rm, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16rr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16rr_REV, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16rs, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16sm, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16sr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32ao16, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32ao32, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32ao64, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32cr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32dr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32mi, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32mr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32o16a, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32o32a, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32o64a, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32rc, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32rd, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32ri, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32ri_alt, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32rm, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32rr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32rr_REV, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32rs, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32sr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64ao32, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64ao64, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64cr, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64dr, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64mi32, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64mr, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64o32a, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64o64a, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64rc, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64rd, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64ri, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64ri32, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64rm, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64rr, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64rr_REV, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64rs, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64sr, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64toPQIrm, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64toPQIrr, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64toSDrm, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64toSDrr, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8ao16, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8ao32, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8ao64, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8mi, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8mr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8mr_NOREX, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8o16a, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8o32a, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8o64a, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8ri, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8ri_alt, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8rm, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8rm_NOREX, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8rr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8rr_NOREX, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8rr_REV, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVAPDmr, X86_INS_MOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVAPDrm, X86_INS_MOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVAPDrr, X86_INS_MOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVAPDrr_REV, X86_INS_MOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVAPSmr, X86_INS_MOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVAPSrm, X86_INS_MOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVAPSrr, X86_INS_MOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVAPSrr_REV, X86_INS_MOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVBE16mr, X86_INS_MOVBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVBE16rm, X86_INS_MOVBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVBE32mr, X86_INS_MOVBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVBE32rm, X86_INS_MOVBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVBE64mr, X86_INS_MOVBE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVBE64rm, X86_INS_MOVBE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDDUPrm, X86_INS_MOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDDUPrr, X86_INS_MOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDI2PDIrm, X86_INS_MOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDI2PDIrr, X86_INS_MOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDI2SSrm, X86_INS_MOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDI2SSrr, X86_INS_MOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDIR64B16, X86_INS_MOVDIR64B, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDIR64B32, X86_INS_MOVDIR64B, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDIR64B64, X86_INS_MOVDIR64B, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDIRI32, X86_INS_MOVDIRI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDIRI64, X86_INS_MOVDIRI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDQAmr, X86_INS_MOVDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDQArm, X86_INS_MOVDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDQArr, X86_INS_MOVDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDQArr_REV, X86_INS_MOVDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDQUmr, X86_INS_MOVDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDQUrm, X86_INS_MOVDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDQUrr, X86_INS_MOVDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDQUrr_REV, X86_INS_MOVDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVHLPSrr, X86_INS_MOVHLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVHPDmr, X86_INS_MOVHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVHPDrm, X86_INS_MOVHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVHPSmr, X86_INS_MOVHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVHPSrm, X86_INS_MOVHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVLHPSrr, X86_INS_MOVLHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVLPDmr, X86_INS_MOVLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVLPDrm, X86_INS_MOVLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVLPSmr, X86_INS_MOVLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVLPSrm, X86_INS_MOVLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVMSKPDrr, X86_INS_MOVMSKPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVMSKPSrr, X86_INS_MOVMSKPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVNTDQArm, X86_INS_MOVNTDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVNTDQmr, X86_INS_MOVNTDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVNTI_64mr, X86_INS_MOVNTI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVNTImr, X86_INS_MOVNTI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVNTPDmr, X86_INS_MOVNTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVNTPSmr, X86_INS_MOVNTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVNTSD, X86_INS_MOVNTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVNTSS, X86_INS_MOVNTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVPDI2DImr, X86_INS_MOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVPDI2DIrr, X86_INS_MOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVPQI2QImr, X86_INS_MOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVPQI2QIrr, X86_INS_MOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVPQIto64mr, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVPQIto64rr, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVQI2PQIrm, X86_INS_MOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSB, X86_INS_MOVSB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSDmr, X86_INS_MOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSDrm, X86_INS_MOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSDrr, X86_INS_MOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSDrr_REV, X86_INS_MOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSDto64mr, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSDto64rr, X86_INS_MOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSHDUPrm, X86_INS_MOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSHDUPrr, X86_INS_MOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSL, X86_INS_MOVSD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSLDUPrm, X86_INS_MOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSLDUPrr, X86_INS_MOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSQ, X86_INS_MOVSQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSS2DImr, X86_INS_MOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSS2DIrr, X86_INS_MOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSSmr, X86_INS_MOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSSrm, X86_INS_MOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSSrr, X86_INS_MOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSSrr_REV, X86_INS_MOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSW, X86_INS_MOVSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX16rm16, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX16rm8, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX16rr16, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX16rr8, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX32rm16, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX32rm8, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX32rm8_NOREX, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX32rr16, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX32rr8, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX32rr8_NOREX, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX64rm16, X86_INS_MOVSX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX64rm32, X86_INS_MOVSXD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX64rm8, X86_INS_MOVSX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX64rr16, X86_INS_MOVSX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX64rr32, X86_INS_MOVSXD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX64rr8, X86_INS_MOVSX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVUPDmr, X86_INS_MOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVUPDrm, X86_INS_MOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVUPDrr, X86_INS_MOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVUPDrr_REV, X86_INS_MOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVUPSmr, X86_INS_MOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVUPSrm, X86_INS_MOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVUPSrr, X86_INS_MOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVUPSrr_REV, X86_INS_MOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZPQILo2PQIrr, X86_INS_MOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX16rm16, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX16rm8, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX16rr16, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX16rr8, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX32rm16, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX32rm8, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX32rm8_NOREX, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX32rr16, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX32rr8, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX32rr8_NOREX, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX64rm16, X86_INS_MOVZX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX64rm8, X86_INS_MOVZX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX64rr16, X86_INS_MOVZX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX64rr8, X86_INS_MOVZX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MPSADBWrmi, X86_INS_MPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_MPSADBWrri, X86_INS_MPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_MUL16m, X86_INS_MUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL16r, X86_INS_MUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL32m, X86_INS_MUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL32r, X86_INS_MUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL64m, X86_INS_MUL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL64r, X86_INS_MUL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL8m, X86_INS_MUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL8r, X86_INS_MUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MULPDrm, X86_INS_MULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MULPDrr, X86_INS_MULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MULPSrm, X86_INS_MULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MULPSrr, X86_INS_MULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MULSDrm, X86_INS_MULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MULSDrm_Int, X86_INS_MULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MULSDrr, X86_INS_MULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MULSDrr_Int, X86_INS_MULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_MULSSrm, X86_INS_MULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MULSSrm_Int, X86_INS_MULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MULSSrr, X86_INS_MULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MULSSrr_Int, X86_INS_MULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_MULX32rm, X86_INS_MULX, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_MULX32rr, X86_INS_MULX, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_MULX64rm, X86_INS_MULX, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_MULX64rr, X86_INS_MULX, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_F32m, X86_INS_FMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_F64m, X86_INS_FMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_FI16m, X86_INS_FIMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_FI32m, X86_INS_FIMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_FPrST0, X86_INS_FMULP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_FST0r, X86_INS_FMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_Fp32, X86_INS_FMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_Fp32m, X86_INS_FMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_Fp64, X86_INS_FMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_Fp64m, X86_INS_FMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_Fp64m32, X86_INS_FMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_Fp80, X86_INS_FMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_Fp80m32, X86_INS_FMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_Fp80m64, X86_INS_FMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_FpI16m32, X86_INS_FMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_FpI16m64, X86_INS_FMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_FpI16m80, X86_INS_FMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_FpI32m32, X86_INS_FMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_FpI32m64, X86_INS_FMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_FpI32m80, X86_INS_FMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL_FrST0, X86_INS_FMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_MWAITXrrr, X86_INS_MWAITX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MWAITrr, X86_INS_MWAIT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ECX, X86_REG_EAX, 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_NEG16m, X86_INS_NEG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG16r, X86_INS_NEG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG32m, X86_INS_NEG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG32r, X86_INS_NEG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG64m, X86_INS_NEG, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG64r, X86_INS_NEG, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG8m, X86_INS_NEG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG8r, X86_INS_NEG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16m4, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16m5, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16m6, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16m7, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16r4, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16r5, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16r6, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16r7, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_m4, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_m5, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_m6, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_m7, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_r4, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_r5, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_r6, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_r7, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP19rr, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPL, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPL_19, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPL_1d, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPL_1e, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPLr, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPQ, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPQr, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPW, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPW_19, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPW_1c, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPW_1d, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPW_1e, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPWr, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT16m, X86_INS_NOT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT16r, X86_INS_NOT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT32m, X86_INS_NOT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT32r, X86_INS_NOT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT64m, X86_INS_NOT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT64r, X86_INS_NOT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT8m, X86_INS_NOT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT8r, X86_INS_NOT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16i16, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16mi, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16mi8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16mr, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16ri, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16ri8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16rm, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16rr, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16rr_REV, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32i32, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32mi, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32mi8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32mr, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32ri, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32ri8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32rm, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32rr, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32rr_REV, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64i32, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64mi32, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64mi8, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64mr, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64ri32, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64ri8, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64rm, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64rr, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64rr_REV, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8i8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8mi, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8mi8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_OR8mr, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8ri, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8ri8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_OR8rm, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8rr, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8rr_REV, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ORPDrm, X86_INS_ORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_ORPDrr, X86_INS_ORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_ORPSrm, X86_INS_ORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_ORPSrr, X86_INS_ORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_OUT16ir, X86_INS_OUT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUT16rr, X86_INS_OUT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUT32ir, X86_INS_OUT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUT32rr, X86_INS_OUT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUT8ir, X86_INS_OUT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUT8rr, X86_INS_OUT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUTSB, X86_INS_OUTSB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUTSL, X86_INS_OUTSD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUTSW, X86_INS_OUTSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PABSBrm, X86_INS_PABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PABSBrr, X86_INS_PABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PABSDrm, X86_INS_PABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PABSDrr, X86_INS_PABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PABSWrm, X86_INS_PABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PABSWrr, X86_INS_PABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PACKSSDWrm, X86_INS_PACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PACKSSDWrr, X86_INS_PACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PACKSSWBrm, X86_INS_PACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PACKSSWBrr, X86_INS_PACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PACKUSDWrm, X86_INS_PACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PACKUSDWrr, X86_INS_PACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PACKUSWBrm, X86_INS_PACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PACKUSWBrr, X86_INS_PACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDBrm, X86_INS_PADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDBrr, X86_INS_PADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDDrm, X86_INS_PADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDDrr, X86_INS_PADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDQrm, X86_INS_PADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDQrr, X86_INS_PADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDSBrm, X86_INS_PADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDSBrr, X86_INS_PADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDSWrm, X86_INS_PADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDSWrr, X86_INS_PADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDUSBrm, X86_INS_PADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDUSBrr, X86_INS_PADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDUSWrm, X86_INS_PADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDUSWrr, X86_INS_PADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDWrm, X86_INS_PADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PADDWrr, X86_INS_PADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PALIGNRrmi, X86_INS_PALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PALIGNRrri, X86_INS_PALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PANDNrm, X86_INS_PANDN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PANDNrr, X86_INS_PANDN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PANDrm, X86_INS_PAND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PANDrr, X86_INS_PAND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PAUSE, X86_INS_PAUSE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PAVGBrm, X86_INS_PAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PAVGBrr, X86_INS_PAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PAVGUSBrm, X86_INS_PAVGUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PAVGUSBrr, X86_INS_PAVGUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PAVGWrm, X86_INS_PAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PAVGWrr, X86_INS_PAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PBLENDVBrm0, X86_INS_PBLENDVB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PBLENDVBrr0, X86_INS_PBLENDVB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PBLENDWrmi, X86_INS_PBLENDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PBLENDWrri, X86_INS_PBLENDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PCLMULQDQrm, X86_INS_PCLMULQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PCLMUL, 0 }, 0, 0 +#endif +}, + +{ + X86_PCLMULQDQrr, X86_INS_PCLMULQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PCLMUL, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPEQBrm, X86_INS_PCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPEQBrr, X86_INS_PCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPEQDrm, X86_INS_PCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPEQDrr, X86_INS_PCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPEQQrm, X86_INS_PCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPEQQrr, X86_INS_PCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPEQWrm, X86_INS_PCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPEQWrr, X86_INS_PCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPESTRIrm, X86_INS_PCMPESTRI, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPESTRIrr, X86_INS_PCMPESTRI, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPESTRMrm, X86_INS_PCMPESTRM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPESTRMrr, X86_INS_PCMPESTRM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPGTBrm, X86_INS_PCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPGTBrr, X86_INS_PCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPGTDrm, X86_INS_PCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPGTDrr, X86_INS_PCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPGTQrm, X86_INS_PCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPGTQrr, X86_INS_PCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPGTWrm, X86_INS_PCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPGTWrr, X86_INS_PCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPISTRIrm, X86_INS_PCMPISTRI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPISTRIrr, X86_INS_PCMPISTRI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPISTRMrm, X86_INS_PCMPISTRM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PCMPISTRMrr, X86_INS_PCMPISTRM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PCONFIG, X86_INS_PCONFIG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PDEP32rm, X86_INS_PDEP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PDEP32rr, X86_INS_PDEP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PDEP64rm, X86_INS_PDEP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PDEP64rr, X86_INS_PDEP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXT32rm, X86_INS_PEXT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXT32rr, X86_INS_PEXT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXT64rm, X86_INS_PEXT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXT64rr, X86_INS_PEXT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXTRBmr, X86_INS_PEXTRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXTRBrr, X86_INS_PEXTRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXTRDmr, X86_INS_PEXTRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXTRDrr, X86_INS_PEXTRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXTRQmr, X86_INS_PEXTRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXTRQrr, X86_INS_PEXTRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXTRWmr, X86_INS_PEXTRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXTRWrr, X86_INS_PEXTRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PEXTRWrr_REV, X86_INS_PEXTRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PF2IDrm, X86_INS_PF2ID, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PF2IDrr, X86_INS_PF2ID, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PF2IWrm, X86_INS_PF2IW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PF2IWrr, X86_INS_PF2IW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFACCrm, X86_INS_PFACC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFACCrr, X86_INS_PFACC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFADDrm, X86_INS_PFADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFADDrr, X86_INS_PFADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFCMPEQrm, X86_INS_PFCMPEQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFCMPEQrr, X86_INS_PFCMPEQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFCMPGErm, X86_INS_PFCMPGE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFCMPGErr, X86_INS_PFCMPGE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFCMPGTrm, X86_INS_PFCMPGT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFCMPGTrr, X86_INS_PFCMPGT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFMAXrm, X86_INS_PFMAX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFMAXrr, X86_INS_PFMAX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFMINrm, X86_INS_PFMIN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFMINrr, X86_INS_PFMIN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFMULrm, X86_INS_PFMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFMULrr, X86_INS_PFMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFNACCrm, X86_INS_PFNACC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFNACCrr, X86_INS_PFNACC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFPNACCrm, X86_INS_PFPNACC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFPNACCrr, X86_INS_PFPNACC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFRCPIT1rm, X86_INS_PFRCPIT1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFRCPIT1rr, X86_INS_PFRCPIT1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFRCPIT2rm, X86_INS_PFRCPIT2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFRCPIT2rr, X86_INS_PFRCPIT2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFRCPrm, X86_INS_PFRCP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFRCPrr, X86_INS_PFRCP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFRSQIT1rm, X86_INS_PFRSQIT1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFRSQIT1rr, X86_INS_PFRSQIT1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFRSQRTrm, X86_INS_PFRSQRT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFRSQRTrr, X86_INS_PFRSQRT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFSUBRrm, X86_INS_PFSUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFSUBRrr, X86_INS_PFSUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFSUBrm, X86_INS_PFSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PFSUBrr, X86_INS_PFSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PHADDDrm, X86_INS_PHADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PHADDDrr, X86_INS_PHADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PHADDSWrm, X86_INS_PHADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PHADDSWrr, X86_INS_PHADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PHADDWrm, X86_INS_PHADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PHADDWrr, X86_INS_PHADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PHMINPOSUWrm, X86_INS_PHMINPOSUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PHMINPOSUWrr, X86_INS_PHMINPOSUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PHSUBDrm, X86_INS_PHSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PHSUBDrr, X86_INS_PHSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PHSUBSWrm, X86_INS_PHSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PHSUBSWrr, X86_INS_PHSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PHSUBWrm, X86_INS_PHSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PHSUBWrr, X86_INS_PHSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PI2FDrm, X86_INS_PI2FD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PI2FDrr, X86_INS_PI2FD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PI2FWrm, X86_INS_PI2FW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PI2FWrr, X86_INS_PI2FW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PINSRBrm, X86_INS_PINSRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PINSRBrr, X86_INS_PINSRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PINSRDrm, X86_INS_PINSRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PINSRDrr, X86_INS_PINSRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PINSRQrm, X86_INS_PINSRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PINSRQrr, X86_INS_PINSRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PINSRWrm, X86_INS_PINSRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PINSRWrr, X86_INS_PINSRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PMADDUBSWrm, X86_INS_PMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PMADDUBSWrr, X86_INS_PMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PMADDWDrm, X86_INS_PMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMADDWDrr, X86_INS_PMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMAXSBrm, X86_INS_PMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMAXSBrr, X86_INS_PMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMAXSDrm, X86_INS_PMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMAXSDrr, X86_INS_PMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMAXSWrm, X86_INS_PMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMAXSWrr, X86_INS_PMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMAXUBrm, X86_INS_PMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMAXUBrr, X86_INS_PMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMAXUDrm, X86_INS_PMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMAXUDrr, X86_INS_PMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMAXUWrm, X86_INS_PMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMAXUWrr, X86_INS_PMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMINSBrm, X86_INS_PMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMINSBrr, X86_INS_PMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMINSDrm, X86_INS_PMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMINSDrr, X86_INS_PMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMINSWrm, X86_INS_PMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMINSWrr, X86_INS_PMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMINUBrm, X86_INS_PMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMINUBrr, X86_INS_PMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMINUDrm, X86_INS_PMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMINUDrr, X86_INS_PMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMINUWrm, X86_INS_PMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMINUWrr, X86_INS_PMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVMSKBrr, X86_INS_PMOVMSKB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVSXBDrm, X86_INS_PMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVSXBDrr, X86_INS_PMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVSXBQrm, X86_INS_PMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVSXBQrr, X86_INS_PMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVSXBWrm, X86_INS_PMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVSXBWrr, X86_INS_PMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVSXDQrm, X86_INS_PMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVSXDQrr, X86_INS_PMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVSXWDrm, X86_INS_PMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVSXWDrr, X86_INS_PMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVSXWQrm, X86_INS_PMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVSXWQrr, X86_INS_PMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVZXBDrm, X86_INS_PMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVZXBDrr, X86_INS_PMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVZXBQrm, X86_INS_PMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVZXBQrr, X86_INS_PMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVZXBWrm, X86_INS_PMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVZXBWrr, X86_INS_PMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVZXDQrm, X86_INS_PMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVZXDQrr, X86_INS_PMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVZXWDrm, X86_INS_PMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVZXWDrr, X86_INS_PMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVZXWQrm, X86_INS_PMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMOVZXWQrr, X86_INS_PMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULDQrm, X86_INS_PMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULDQrr, X86_INS_PMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULHRSWrm, X86_INS_PMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PMULHRSWrr, X86_INS_PMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PMULHRWrm, X86_INS_PMULHRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULHRWrr, X86_INS_PMULHRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULHUWrm, X86_INS_PMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULHUWrr, X86_INS_PMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULHWrm, X86_INS_PMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULHWrr, X86_INS_PMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULLDrm, X86_INS_PMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULLDrr, X86_INS_PMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULLWrm, X86_INS_PMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULLWrr, X86_INS_PMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULUDQrm, X86_INS_PMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PMULUDQrr, X86_INS_PMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_POP16r, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POP16rmm, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POP16rmr, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POP32r, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POP32rmm, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POP32rmr, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POP64r, X86_INS_POP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_POP64rmm, X86_INS_POP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_POP64rmr, X86_INS_POP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_POPA16, X86_INS_POPAW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPA32, X86_INS_POPAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPCNT16rm, X86_INS_POPCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POPCNT16rr, X86_INS_POPCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POPCNT32rm, X86_INS_POPCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POPCNT32rr, X86_INS_POPCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POPCNT64rm, X86_INS_POPCNT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POPCNT64rr, X86_INS_POPCNT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POPDS16, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPDS32, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPES16, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPES32, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPF16, X86_INS_POPF, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POPF32, X86_INS_POPFD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPF64, X86_INS_POPFQ, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_POPFS16, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPFS32, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPFS64, X86_INS_POP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_POPGS16, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPGS32, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPGS64, X86_INS_POP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_POPSS16, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPSS32, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PORrm, X86_INS_POR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PORrr, X86_INS_POR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PREFETCH, X86_INS_PREFETCH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PREFETCHNTA, X86_INS_PREFETCHNTA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_PREFETCHT0, X86_INS_PREFETCHT0, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_PREFETCHT1, X86_INS_PREFETCHT1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_PREFETCHT2, X86_INS_PREFETCHT2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_PREFETCHW, X86_INS_PREFETCHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PREFETCHWT1, X86_INS_PREFETCHWT1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PSADBWrm, X86_INS_PSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSADBWrr, X86_INS_PSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSHUFBrm, X86_INS_PSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PSHUFBrr, X86_INS_PSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PSHUFDmi, X86_INS_PSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSHUFDri, X86_INS_PSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSHUFHWmi, X86_INS_PSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSHUFHWri, X86_INS_PSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSHUFLWmi, X86_INS_PSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSHUFLWri, X86_INS_PSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSIGNBrm, X86_INS_PSIGNB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PSIGNBrr, X86_INS_PSIGNB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PSIGNDrm, X86_INS_PSIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PSIGNDrr, X86_INS_PSIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PSIGNWrm, X86_INS_PSIGNW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PSIGNWrr, X86_INS_PSIGNW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 +#endif +}, + +{ + X86_PSLLDQri, X86_INS_PSLLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSLLDri, X86_INS_PSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSLLDrm, X86_INS_PSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSLLDrr, X86_INS_PSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSLLQri, X86_INS_PSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSLLQrm, X86_INS_PSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSLLQrr, X86_INS_PSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSLLWri, X86_INS_PSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSLLWrm, X86_INS_PSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSLLWrr, X86_INS_PSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRADri, X86_INS_PSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRADrm, X86_INS_PSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRADrr, X86_INS_PSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRAWri, X86_INS_PSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRAWrm, X86_INS_PSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRAWrr, X86_INS_PSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRLDQri, X86_INS_PSRLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRLDri, X86_INS_PSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRLDrm, X86_INS_PSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRLDrr, X86_INS_PSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRLQri, X86_INS_PSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRLQrm, X86_INS_PSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRLQrr, X86_INS_PSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRLWri, X86_INS_PSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRLWrm, X86_INS_PSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSRLWrr, X86_INS_PSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBBrm, X86_INS_PSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBBrr, X86_INS_PSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBDrm, X86_INS_PSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBDrr, X86_INS_PSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBQrm, X86_INS_PSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBQrr, X86_INS_PSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBSBrm, X86_INS_PSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBSBrr, X86_INS_PSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBSWrm, X86_INS_PSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBSWrr, X86_INS_PSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBUSBrm, X86_INS_PSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBUSBrr, X86_INS_PSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBUSWrm, X86_INS_PSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBUSWrr, X86_INS_PSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBWrm, X86_INS_PSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSUBWrr, X86_INS_PSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PSWAPDrm, X86_INS_PSWAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PSWAPDrr, X86_INS_PSWAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 +#endif +}, + +{ + X86_PTESTrm, X86_INS_PTEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PTESTrr, X86_INS_PTEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_PTWRITE64m, X86_INS_PTWRITE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PTWRITE64r, X86_INS_PTWRITE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PTWRITEm, X86_INS_PTWRITE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PTWRITEr, X86_INS_PTWRITE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKHBWrm, X86_INS_PUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKHBWrr, X86_INS_PUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKHDQrm, X86_INS_PUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKHDQrr, X86_INS_PUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKHQDQrm, X86_INS_PUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKHQDQrr, X86_INS_PUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKHWDrm, X86_INS_PUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKHWDrr, X86_INS_PUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKLBWrm, X86_INS_PUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKLBWrr, X86_INS_PUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKLDQrm, X86_INS_PUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKLDQrr, X86_INS_PUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKLQDQrm, X86_INS_PUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKLQDQrr, X86_INS_PUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKLWDrm, X86_INS_PUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUNPCKLWDrr, X86_INS_PUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH16i8, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH16r, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH16rmm, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH16rmr, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH32i8, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH32r, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH32rmm, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH32rmr, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH64i32, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH64i8, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH64r, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH64rmm, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH64rmr, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHA16, X86_INS_PUSHAW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHA32, X86_INS_PUSHAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHCS16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHCS32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHDS16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHDS32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHES16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHES32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHF16, X86_INS_PUSHF, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHF32, X86_INS_PUSHFD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHF64, X86_INS_PUSHFQ, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, X86_REG_EFLAGS, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHFS16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHFS32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHFS64, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHGS16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHGS32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHGS64, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHSS16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHSS32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHi16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHi32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PXORrm, X86_INS_PXOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_PXORrr, X86_INS_PXOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_RCL16m1, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL16mCL, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL16mi, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL16r1, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL16rCL, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL16ri, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL32m1, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL32mCL, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL32mi, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL32r1, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL32rCL, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL32ri, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL64m1, X86_INS_RCL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL64mCL, X86_INS_RCL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL64mi, X86_INS_RCL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL64r1, X86_INS_RCL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL64rCL, X86_INS_RCL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL64ri, X86_INS_RCL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL8m1, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL8mCL, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL8mi, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL8r1, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL8rCL, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL8ri, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCPPSm, X86_INS_RCPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_RCPPSr, X86_INS_RCPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_RCPSSm, X86_INS_RCPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_RCPSSm_Int, X86_INS_RCPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCPSSr, X86_INS_RCPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_RCPSSr_Int, X86_INS_RCPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR16m1, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR16mCL, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR16mi, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR16r1, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR16rCL, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR16ri, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR32m1, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR32mCL, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR32mi, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR32r1, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR32rCL, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR32ri, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR64m1, X86_INS_RCR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR64mCL, X86_INS_RCR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR64mi, X86_INS_RCR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR64r1, X86_INS_RCR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR64rCL, X86_INS_RCR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR64ri, X86_INS_RCR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR8m1, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR8mCL, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR8mi, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR8r1, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR8rCL, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR8ri, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDFSBASE, X86_INS_RDFSBASE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_RDFSBASE64, X86_INS_RDFSBASE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_RDGSBASE, X86_INS_RDGSBASE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_RDGSBASE64, X86_INS_RDGSBASE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_RDMSR, X86_INS_RDMSR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ECX, 0 }, { X86_REG_EAX, X86_REG_EDX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDPID32, X86_INS_RDPID, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDPID64, X86_INS_RDPID, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDPKRUr, X86_INS_RDPKRU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDPMC, X86_INS_RDPMC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ECX, 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_RDRAND16r, X86_INS_RDRAND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDRAND32r, X86_INS_RDRAND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDRAND64r, X86_INS_RDRAND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDSEED16r, X86_INS_RDSEED, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDSEED32r, X86_INS_RDSEED, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDSEED64r, X86_INS_RDSEED, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDSSPD, X86_INS_RDSSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDSSPQ, X86_INS_RDSSPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDTSC, X86_INS_RDTSC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDTSCP, X86_INS_RDTSCP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_RAX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_REPNE_PREFIX, X86_INS_REPNE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_REP_PREFIX, X86_INS_REP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RETIL, X86_INS_RET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_RETIQ, X86_INS_RET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_RETIW, X86_INS_RET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 +#endif +}, + +{ + X86_RETL, X86_INS_RET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_RETQ, X86_INS_RET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_RETW, X86_INS_RET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 +#endif +}, + +{ + X86_REX64_PREFIX, X86_INS_REX64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL16m1, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL16mCL, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL16mi, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL16r1, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL16rCL, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL16ri, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL32m1, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL32mCL, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL32mi, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL32r1, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL32rCL, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL32ri, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL64m1, X86_INS_ROL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL64mCL, X86_INS_ROL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL64mi, X86_INS_ROL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL64r1, X86_INS_ROL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL64rCL, X86_INS_ROL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL64ri, X86_INS_ROL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL8m1, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL8mCL, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL8mi, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL8r1, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL8rCL, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL8ri, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR16m1, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR16mCL, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR16mi, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR16r1, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR16rCL, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR16ri, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR32m1, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR32mCL, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR32mi, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR32r1, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR32rCL, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR32ri, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR64m1, X86_INS_ROR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR64mCL, X86_INS_ROR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR64mi, X86_INS_ROR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR64r1, X86_INS_ROR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR64rCL, X86_INS_ROR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR64ri, X86_INS_ROR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR8m1, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR8mCL, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR8mi, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR8r1, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR8rCL, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR8ri, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RORX32mi, X86_INS_RORX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_RORX32ri, X86_INS_RORX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_RORX64mi, X86_INS_RORX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_RORX64ri, X86_INS_RORX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_ROUNDPDm, X86_INS_ROUNDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_ROUNDPDr, X86_INS_ROUNDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_ROUNDPSm, X86_INS_ROUNDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_ROUNDPSr, X86_INS_ROUNDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_ROUNDSDm, X86_INS_ROUNDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_ROUNDSDm_Int, X86_INS_ROUNDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROUNDSDr, X86_INS_ROUNDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_ROUNDSDr_Int, X86_INS_ROUNDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_ROUNDSSm, X86_INS_ROUNDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_ROUNDSSm_Int, X86_INS_ROUNDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROUNDSSr, X86_INS_ROUNDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_ROUNDSSr_Int, X86_INS_ROUNDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 +#endif +}, + +{ + X86_RSM, X86_INS_RSM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_RSQRTPSm, X86_INS_RSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_RSQRTPSr, X86_INS_RSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_RSQRTSSm, X86_INS_RSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_RSQRTSSm_Int, X86_INS_RSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RSQRTSSr, X86_INS_RSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_RSQRTSSr_Int, X86_INS_RSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RSTORSSP, X86_INS_RSTORSSP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAHF, X86_INS_SAHF, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AH, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL16m1, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL16mCL, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL16mi, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL16r1, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL16rCL, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL16ri, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL32m1, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL32mCL, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL32mi, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL32r1, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL32rCL, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL32ri, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL64m1, X86_INS_SAL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL64mCL, X86_INS_SAL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL64mi, X86_INS_SAL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL64r1, X86_INS_SAL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL64rCL, X86_INS_SAL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL64ri, X86_INS_SAL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL8m1, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL8mCL, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL8mi, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL8r1, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL8rCL, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL8ri, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SALC, X86_INS_SALC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_AL, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SAR16m1, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR16mCL, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR16mi, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR16r1, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR16rCL, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR16ri, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR32m1, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR32mCL, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR32mi, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR32r1, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR32rCL, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR32ri, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR64m1, X86_INS_SAR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR64mCL, X86_INS_SAR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR64mi, X86_INS_SAR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR64r1, X86_INS_SAR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR64rCL, X86_INS_SAR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR64ri, X86_INS_SAR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR8m1, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR8mCL, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR8mi, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR8r1, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR8rCL, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR8ri, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SARX32rm, X86_INS_SARX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SARX32rr, X86_INS_SARX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SARX64rm, X86_INS_SARX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SARX64rr, X86_INS_SARX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SAVEPREVSSP, X86_INS_SAVEPREVSSP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16i16, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16mi, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16mi8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16mr, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16ri, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16ri8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16rm, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16rr, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16rr_REV, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32i32, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32mi, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32mi8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32mr, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32ri, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32ri8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32rm, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32rr, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32rr_REV, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64i32, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64mi32, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64mi8, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64mr, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64ri32, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64ri8, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64rm, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64rr, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64rr_REV, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8i8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8mi, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8mi8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8mr, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8ri, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8ri8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8rm, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8rr, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8rr_REV, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SCASB, X86_INS_SCASB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SCASL, X86_INS_SCASD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SCASQ, X86_INS_SCASQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SCASW, X86_INS_SCASW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETAEm, X86_INS_SETAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETAEr, X86_INS_SETAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETAm, X86_INS_SETA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETAr, X86_INS_SETA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETBEm, X86_INS_SETBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETBEr, X86_INS_SETBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETBm, X86_INS_SETB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETBr, X86_INS_SETB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETEm, X86_INS_SETE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETEr, X86_INS_SETE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETGEm, X86_INS_SETGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETGEr, X86_INS_SETGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETGm, X86_INS_SETG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETGr, X86_INS_SETG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETLEm, X86_INS_SETLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETLEr, X86_INS_SETLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETLm, X86_INS_SETL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETLr, X86_INS_SETL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNEm, X86_INS_SETNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNEr, X86_INS_SETNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNOm, X86_INS_SETNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNOr, X86_INS_SETNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNPm, X86_INS_SETNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNPr, X86_INS_SETNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNSm, X86_INS_SETNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNSr, X86_INS_SETNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETOm, X86_INS_SETO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETOr, X86_INS_SETO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETPm, X86_INS_SETP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETPr, X86_INS_SETP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETSSBSY, X86_INS_SETSSBSY, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETSm, X86_INS_SETS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETSr, X86_INS_SETS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SFENCE, X86_INS_SFENCE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SGDT16m, X86_INS_SGDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SGDT32m, X86_INS_SGDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SGDT64m, X86_INS_SGDT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA1MSG1rm, X86_INS_SHA1MSG1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA1MSG1rr, X86_INS_SHA1MSG1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA1MSG2rm, X86_INS_SHA1MSG2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA1MSG2rr, X86_INS_SHA1MSG2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA1NEXTErm, X86_INS_SHA1NEXTE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA1NEXTErr, X86_INS_SHA1NEXTE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA1RNDS4rmi, X86_INS_SHA1RNDS4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA1RNDS4rri, X86_INS_SHA1RNDS4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA256MSG1rm, X86_INS_SHA256MSG1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA256MSG1rr, X86_INS_SHA256MSG1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA256MSG2rm, X86_INS_SHA256MSG2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA256MSG2rr, X86_INS_SHA256MSG2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA256RNDS2rm, X86_INS_SHA256RNDS2, 0, +#ifndef CAPSTONE_DIET + { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHA256RNDS2rr, X86_INS_SHA256RNDS2, 0, +#ifndef CAPSTONE_DIET + { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 +#endif +}, + +{ + X86_SHL16m1, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL16mCL, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL16mi, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL16r1, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL16rCL, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL16ri, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL32m1, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL32mCL, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL32mi, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL32r1, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL32rCL, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL32ri, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL64m1, X86_INS_SHL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL64mCL, X86_INS_SHL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL64mi, X86_INS_SHL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL64r1, X86_INS_SHL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL64rCL, X86_INS_SHL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL64ri, X86_INS_SHL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL8m1, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL8mCL, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL8mi, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL8r1, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL8rCL, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL8ri, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD16mrCL, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD16mri8, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD16rrCL, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD16rri8, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD32mrCL, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD32mri8, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD32rrCL, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD32rri8, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD64mrCL, X86_INS_SHLD, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD64mri8, X86_INS_SHLD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD64rrCL, X86_INS_SHLD, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD64rri8, X86_INS_SHLD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLX32rm, X86_INS_SHLX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHLX32rr, X86_INS_SHLX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHLX64rm, X86_INS_SHLX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHLX64rr, X86_INS_SHLX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHR16m1, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR16mCL, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR16mi, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR16r1, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR16rCL, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR16ri, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR32m1, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR32mCL, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR32mi, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR32r1, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR32rCL, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR32ri, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR64m1, X86_INS_SHR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR64mCL, X86_INS_SHR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR64mi, X86_INS_SHR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR64r1, X86_INS_SHR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR64rCL, X86_INS_SHR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR64ri, X86_INS_SHR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR8m1, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR8mCL, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR8mi, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR8r1, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR8rCL, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR8ri, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD16mrCL, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD16mri8, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD16rrCL, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD16rri8, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD32mrCL, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD32mri8, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD32rrCL, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD32rri8, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD64mrCL, X86_INS_SHRD, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD64mri8, X86_INS_SHRD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD64rrCL, X86_INS_SHRD, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD64rri8, X86_INS_SHRD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRX32rm, X86_INS_SHRX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHRX32rr, X86_INS_SHRX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHRX64rm, X86_INS_SHRX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHRX64rr, X86_INS_SHRX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHUFPDrmi, X86_INS_SHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHUFPDrri, X86_INS_SHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHUFPSrmi, X86_INS_SHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SHUFPSrri, X86_INS_SHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SIDT16m, X86_INS_SIDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SIDT32m, X86_INS_SIDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SIDT64m, X86_INS_SIDT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_SIN_F, X86_INS_FSIN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SIN_Fp32, X86_INS_FSIN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SIN_Fp64, X86_INS_FSIN, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SIN_Fp80, X86_INS_FSIN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SKINIT, X86_INS_SKINIT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_SLDT16m, X86_INS_SLDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SLDT16r, X86_INS_SLDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SLDT32r, X86_INS_SLDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SLDT64r, X86_INS_SLDT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SLWPCB, X86_INS_SLWPCB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SLWPCB64, X86_INS_SLWPCB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SMSW16m, X86_INS_SMSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SMSW16r, X86_INS_SMSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SMSW32r, X86_INS_SMSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SMSW64r, X86_INS_SMSW, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SQRTPDm, X86_INS_SQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_SQRTPDr, X86_INS_SQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_SQRTPSm, X86_INS_SQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SQRTPSr, X86_INS_SQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SQRTSDm, X86_INS_SQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_SQRTSDm_Int, X86_INS_SQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SQRTSDr, X86_INS_SQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_SQRTSDr_Int, X86_INS_SQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SQRTSSm, X86_INS_SQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SQRTSSm_Int, X86_INS_SQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SQRTSSr, X86_INS_SQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SQRTSSr_Int, X86_INS_SQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SQRT_F, X86_INS_FSQRT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SQRT_Fp32, X86_INS_FSQRT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SQRT_Fp64, X86_INS_FSQRT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SQRT_Fp80, X86_INS_FSQRT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STAC, X86_INS_STAC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_STC, X86_INS_STC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STD, X86_INS_STD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STGI, X86_INS_STGI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_STI, X86_INS_STI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_STMXCSR, X86_INS_STMXCSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_STOSB, X86_INS_STOSB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STOSL, X86_INS_STOSD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STOSQ, X86_INS_STOSQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RCX, X86_REG_RDI, X86_REG_EFLAGS, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STOSW, X86_INS_STOSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STR16r, X86_INS_STR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_STR32r, X86_INS_STR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_STR64r, X86_INS_STR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_STRm, X86_INS_STR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_ST_F32m, X86_INS_FST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ST_F64m, X86_INS_FST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ST_FP32m, X86_INS_FSTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ST_FP64m, X86_INS_FSTP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ST_FP80m, X86_INS_FSTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_ST_FPrr, X86_INS_FSTP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ST_Fp32m, X86_INS_FST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ST_Fp64m, X86_INS_FST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ST_Fp64m32, X86_INS_FST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ST_Fp80m32, X86_INS_FST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ST_Fp80m64, X86_INS_FST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ST_FpP32m, X86_INS_FST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ST_FpP64m, X86_INS_FST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ST_FpP64m32, X86_INS_FST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ST_FpP80m, X86_INS_FST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ST_FpP80m32, X86_INS_FST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ST_FpP80m64, X86_INS_FST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ST_Frr, X86_INS_FST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16i16, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16mi, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16mi8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16mr, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16ri, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16ri8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16rm, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16rr, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16rr_REV, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32i32, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32mi, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32mi8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32mr, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32ri, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32ri8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32rm, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32rr, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32rr_REV, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64i32, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64mi32, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64mi8, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64mr, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64ri32, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64ri8, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64rm, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64rr, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64rr_REV, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8i8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8mi, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8mi8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8mr, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8ri, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8ri8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8rm, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8rr, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8rr_REV, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUBPDrm, X86_INS_SUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBPDrr, X86_INS_SUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBPSrm, X86_INS_SUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBPSrr, X86_INS_SUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_F32m, X86_INS_FSUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_F64m, X86_INS_FSUBR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_FI16m, X86_INS_FISUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_FI32m, X86_INS_FISUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_FPrST0, X86_INS_FSUBRP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_FST0r, X86_INS_FSUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_Fp32m, X86_INS_FSUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_Fp64m, X86_INS_FSUBR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_Fp64m32, X86_INS_FSUBR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_Fp80m32, X86_INS_FSUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_Fp80m64, X86_INS_FSUBR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_FpI16m32, X86_INS_FSUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_FpI16m64, X86_INS_FSUBR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_FpI16m80, X86_INS_FSUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_FpI32m32, X86_INS_FSUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_FpI32m64, X86_INS_FSUBR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_FpI32m80, X86_INS_FSUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUBR_FrST0, X86_INS_FSUBR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBSDrm, X86_INS_SUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBSDrm_Int, X86_INS_SUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBSDrr, X86_INS_SUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBSDrr_Int, X86_INS_SUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBSSrm, X86_INS_SUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBSSrm_Int, X86_INS_SUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBSSrr, X86_INS_SUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SUBSSrr_Int, X86_INS_SUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_F32m, X86_INS_FSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_F64m, X86_INS_FSUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_FI16m, X86_INS_FISUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_FI32m, X86_INS_FISUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_FPrST0, X86_INS_FSUBP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_FST0r, X86_INS_FSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_Fp32, X86_INS_FSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_Fp32m, X86_INS_FSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_Fp64, X86_INS_FSUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_Fp64m, X86_INS_FSUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_Fp64m32, X86_INS_FSUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_Fp80, X86_INS_FSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_Fp80m32, X86_INS_FSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_Fp80m64, X86_INS_FSUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_FpI16m32, X86_INS_FSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_FpI16m64, X86_INS_FSUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_FpI16m80, X86_INS_FSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_FpI32m32, X86_INS_FSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_FpI32m64, X86_INS_FSUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_FpI32m80, X86_INS_FSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB_FrST0, X86_INS_FSUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_SWAPGS, X86_INS_SWAPGS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_SYSCALL, X86_INS_SYSCALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 +#endif +}, + +{ + X86_SYSENTER, X86_INS_SYSENTER, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 +#endif +}, + +{ + X86_SYSEXIT, X86_INS_SYSEXIT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 +#endif +}, + +{ + X86_SYSEXIT64, X86_INS_SYSEXITQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_SYSRET, X86_INS_SYSRET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 +#endif +}, + +{ + X86_SYSRET64, X86_INS_SYSRETQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_IRET, X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_T1MSKC32rm, X86_INS_T1MSKC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_T1MSKC32rr, X86_INS_T1MSKC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_T1MSKC64rm, X86_INS_T1MSKC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_T1MSKC64rr, X86_INS_T1MSKC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16i16, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16mi, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16mi_alt, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16mr, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16ri, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16ri_alt, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16rr, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32i32, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32mi, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32mi_alt, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32mr, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32ri, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32ri_alt, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32rr, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64i32, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64mi32, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64mi32_alt, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64mr, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64ri32, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64ri32_alt, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64rr, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8i8, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8mi, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8mi_alt, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8mr, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8ri, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8ri_alt, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8rr, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TPAUSE, X86_INS_TPAUSE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TST_F, X86_INS_FTST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_TST_Fp32, X86_INS_FTST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TST_Fp64, X86_INS_FTST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TST_Fp80, X86_INS_FTST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TZCNT16rm, X86_INS_TZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_TZCNT16rr, X86_INS_TZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_TZCNT32rm, X86_INS_TZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_TZCNT32rr, X86_INS_TZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_TZCNT64rm, X86_INS_TZCNT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_TZCNT64rr, X86_INS_TZCNT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_TZMSK32rm, X86_INS_TZMSK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_TZMSK32rr, X86_INS_TZMSK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_TZMSK64rm, X86_INS_TZMSK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_TZMSK64rr, X86_INS_TZMSK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_UCOMISDrm, X86_INS_UCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_UCOMISDrm_Int, X86_INS_UCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UCOMISDrr, X86_INS_UCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_UCOMISDrr_Int, X86_INS_UCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UCOMISSrm, X86_INS_UCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_UCOMISSrm_Int, X86_INS_UCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UCOMISSrr, X86_INS_UCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_UCOMISSrr_Int, X86_INS_UCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UCOM_FIPr, X86_INS_FUCOMPI, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ST0, 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_UCOM_FIr, X86_INS_FUCOMI, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ST0, 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_UCOM_FPPr, X86_INS_FUCOMPP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ST0, 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_UCOM_FPr, X86_INS_FUCOMP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ST0, 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_UCOM_FpIr32, X86_INS_FUCOMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UCOM_FpIr64, X86_INS_FUCOMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UCOM_FpIr80, X86_INS_FUCOMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UCOM_Fpr32, X86_INS_FUCOMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UCOM_Fpr64, X86_INS_FUCOMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UCOM_Fpr80, X86_INS_FUCOMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UCOM_Fr, X86_INS_FUCOM, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ST0, 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_UD0, X86_INS_UD0, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UD1, X86_INS_UD1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UD2, X86_INS_UD2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UMONITOR16, X86_INS_UMONITOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UMONITOR32, X86_INS_UMONITOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UMONITOR64, X86_INS_UMONITOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UMWAIT, X86_INS_UMWAIT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UNPCKHPDrm, X86_INS_UNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_UNPCKHPDrr, X86_INS_UNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_UNPCKHPSrm, X86_INS_UNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_UNPCKHPSrr, X86_INS_UNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_UNPCKLPDrm, X86_INS_UNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_UNPCKLPDrr, X86_INS_UNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_UNPCKLPSrm, X86_INS_UNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_UNPCKLPSrr, X86_INS_UNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_V4FMADDPSrm, X86_INS_V4FMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_V4FMADDPSrmk, X86_INS_V4FMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_V4FMADDPSrmkz, X86_INS_V4FMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_V4FMADDSSrm, X86_INS_V4FMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_V4FMADDSSrmk, X86_INS_V4FMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_V4FMADDSSrmkz, X86_INS_V4FMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_V4FNMADDPSrm, X86_INS_V4FNMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_V4FNMADDPSrmk, X86_INS_V4FNMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_V4FNMADDPSrmkz, X86_INS_V4FNMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_V4FNMADDSSrm, X86_INS_V4FNMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_V4FNMADDSSrmk, X86_INS_V4FNMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_V4FNMADDSSrmkz, X86_INS_V4FNMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDYrm, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDYrr, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ128rm, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ128rmb, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ128rmbk, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ128rmbkz, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ128rmk, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ128rmkz, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ128rr, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ128rrk, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ128rrkz, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ256rm, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ256rmb, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ256rmbk, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ256rmbkz, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ256rmk, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ256rmkz, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ256rr, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ256rrk, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZ256rrkz, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZrm, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZrmb, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZrmbk, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZrmbkz, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZrmk, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZrmkz, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZrr, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZrrb, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZrrbk, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZrrbkz, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZrrk, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDZrrkz, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDrm, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPDrr, X86_INS_VADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSYrm, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSYrr, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ128rm, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ128rmb, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ128rmbk, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ128rmbkz, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ128rmk, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ128rmkz, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ128rr, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ128rrk, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ128rrkz, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ256rm, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ256rmb, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ256rmbk, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ256rmbkz, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ256rmk, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ256rmkz, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ256rr, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ256rrk, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZ256rrkz, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZrm, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZrmb, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZrmbk, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZrmbkz, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZrmk, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZrmkz, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZrr, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZrrb, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZrrbk, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZrrbkz, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZrrk, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSZrrkz, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSrm, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDPSrr, X86_INS_VADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDZrm, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDZrm_Int, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDZrm_Intk, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDZrm_Intkz, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDZrr, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDZrr_Int, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDZrr_Intk, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDZrr_Intkz, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDZrrb_Int, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDZrrb_Intk, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDZrrb_Intkz, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDrm, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDrm_Int, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDrr, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSDrr_Int, X86_INS_VADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSZrm, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSZrm_Int, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSZrm_Intk, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSZrm_Intkz, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSZrr, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSZrr_Int, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSZrr_Intk, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSZrr_Intkz, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSZrrb_Int, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSZrrb_Intk, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSZrrb_Intkz, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSrm, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSrm_Int, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSrr, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSSrr_Int, X86_INS_VADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSUBPDYrm, X86_INS_VADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSUBPDYrr, X86_INS_VADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSUBPDrm, X86_INS_VADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSUBPDrr, X86_INS_VADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSUBPSYrm, X86_INS_VADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSUBPSYrr, X86_INS_VADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSUBPSrm, X86_INS_VADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VADDSUBPSrr, X86_INS_VADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECLASTYrm, X86_INS_VAESDECLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECLASTYrr, X86_INS_VAESDECLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECLASTZ128rm, X86_INS_VAESDECLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECLASTZ128rr, X86_INS_VAESDECLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECLASTZ256rm, X86_INS_VAESDECLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECLASTZ256rr, X86_INS_VAESDECLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECLASTZrm, X86_INS_VAESDECLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECLASTZrr, X86_INS_VAESDECLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECLASTrm, X86_INS_VAESDECLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECLASTrr, X86_INS_VAESDECLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECYrm, X86_INS_VAESDEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECYrr, X86_INS_VAESDEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECZ128rm, X86_INS_VAESDEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECZ128rr, X86_INS_VAESDEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECZ256rm, X86_INS_VAESDEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECZ256rr, X86_INS_VAESDEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECZrm, X86_INS_VAESDEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECZrr, X86_INS_VAESDEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECrm, X86_INS_VAESDEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_VAESDECrr, X86_INS_VAESDEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCLASTYrm, X86_INS_VAESENCLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCLASTYrr, X86_INS_VAESENCLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCLASTZ128rm, X86_INS_VAESENCLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCLASTZ128rr, X86_INS_VAESENCLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCLASTZ256rm, X86_INS_VAESENCLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCLASTZ256rr, X86_INS_VAESENCLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCLASTZrm, X86_INS_VAESENCLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCLASTZrr, X86_INS_VAESENCLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCLASTrm, X86_INS_VAESENCLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCLASTrr, X86_INS_VAESENCLAST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCYrm, X86_INS_VAESENC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCYrr, X86_INS_VAESENC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCZ128rm, X86_INS_VAESENC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCZ128rr, X86_INS_VAESENC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCZ256rm, X86_INS_VAESENC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCZ256rr, X86_INS_VAESENC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCZrm, X86_INS_VAESENC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCZrr, X86_INS_VAESENC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCrm, X86_INS_VAESENC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_VAESENCrr, X86_INS_VAESENC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_VAESIMCrm, X86_INS_VAESIMC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_VAESIMCrr, X86_INS_VAESIMC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_VAESKEYGENASSIST128rm, X86_INS_VAESKEYGENASSIST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_VAESKEYGENASSIST128rr, X86_INS_VAESKEYGENASSIST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ128rmbi, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ128rmbik, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ128rmbikz, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ128rmi, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ128rmik, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ128rmikz, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ128rri, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ128rrik, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ128rrikz, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ256rmbi, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ256rmbik, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ256rmbikz, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ256rmi, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ256rmik, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ256rmikz, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ256rri, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ256rrik, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZ256rrikz, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZrmbi, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZrmbik, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZrmbikz, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZrmi, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZrmik, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZrmikz, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZrri, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZrrik, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNDZrrikz, X86_INS_VALIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ128rmbi, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ128rmbik, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ128rmbikz, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ128rmi, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ128rmik, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ128rmikz, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ128rri, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ128rrik, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ128rrikz, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ256rmbi, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ256rmbik, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ256rmbikz, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ256rmi, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ256rmik, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ256rmikz, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ256rri, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ256rrik, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZ256rrikz, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZrmbi, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZrmbik, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZrmbikz, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZrmi, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZrmik, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZrmikz, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZrri, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZrrik, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VALIGNQZrrikz, X86_INS_VALIGNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDYrm, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDYrr, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ128rm, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ128rmb, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ128rmbk, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ128rmbkz, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ128rmk, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ128rmkz, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ128rr, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ128rrk, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ128rrkz, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ256rm, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ256rmb, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ256rmbk, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ256rmbkz, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ256rmk, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ256rmkz, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ256rr, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ256rrk, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZ256rrkz, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZrm, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZrmb, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZrmbk, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZrmbkz, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZrmk, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZrmkz, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZrr, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZrrk, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDZrrkz, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDrm, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPDrr, X86_INS_VANDNPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSYrm, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSYrr, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ128rm, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ128rmb, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ128rmbk, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ128rmbkz, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ128rmk, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ128rmkz, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ128rr, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ128rrk, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ128rrkz, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ256rm, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ256rmb, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ256rmbk, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ256rmbkz, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ256rmk, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ256rmkz, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ256rr, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ256rrk, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZ256rrkz, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZrm, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZrmb, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZrmbk, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZrmbkz, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZrmk, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZrmkz, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZrr, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZrrk, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSZrrkz, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSrm, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDNPSrr, X86_INS_VANDNPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDYrm, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDYrr, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ128rm, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ128rmb, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ128rmbk, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ128rmbkz, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ128rmk, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ128rmkz, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ128rr, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ128rrk, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ128rrkz, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ256rm, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ256rmb, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ256rmbk, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ256rmbkz, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ256rmk, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ256rmkz, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ256rr, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ256rrk, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZ256rrkz, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZrm, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZrmb, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZrmbk, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZrmbkz, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZrmk, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZrmkz, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZrr, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZrrk, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDZrrkz, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDrm, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPDrr, X86_INS_VANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSYrm, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSYrr, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ128rm, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ128rmb, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ128rmbk, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ128rmbkz, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ128rmk, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ128rmkz, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ128rr, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ128rrk, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ128rrkz, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ256rm, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ256rmb, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ256rmbk, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ256rmbkz, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ256rmk, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ256rmkz, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ256rr, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ256rrk, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZ256rrkz, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZrm, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZrmb, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZrmbk, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZrmbkz, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZrmk, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZrmkz, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZrr, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZrrk, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSZrrkz, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSrm, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VANDPSrr, X86_INS_VANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ128rm, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ128rmb, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ128rmbk, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ128rmbkz, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ128rmk, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ128rmkz, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ128rr, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ128rrk, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ128rrkz, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ256rm, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ256rmb, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ256rmbk, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ256rmbkz, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ256rmk, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ256rmkz, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ256rr, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ256rrk, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZ256rrkz, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZrm, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZrmb, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZrmbk, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZrmbkz, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZrmk, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZrmkz, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZrr, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZrrk, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPDZrrkz, X86_INS_VBLENDMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ128rm, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ128rmb, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ128rmbk, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ128rmbkz, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ128rmk, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ128rmkz, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ128rr, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ128rrk, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ128rrkz, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ256rm, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ256rmb, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ256rmbk, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ256rmbkz, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ256rmk, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ256rmkz, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ256rr, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ256rrk, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZ256rrkz, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZrm, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZrmb, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZrmbk, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZrmbkz, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZrmk, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZrmkz, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZrr, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZrrk, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDMPSZrrkz, X86_INS_VBLENDMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDPDYrmi, X86_INS_VBLENDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDPDYrri, X86_INS_VBLENDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDPDrmi, X86_INS_VBLENDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDPDrri, X86_INS_VBLENDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDPSYrmi, X86_INS_VBLENDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDPSYrri, X86_INS_VBLENDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDPSrmi, X86_INS_VBLENDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDPSrri, X86_INS_VBLENDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDVPDYrm, X86_INS_VBLENDVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDVPDYrr, X86_INS_VBLENDVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDVPDrm, X86_INS_VBLENDVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDVPDrr, X86_INS_VBLENDVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDVPSYrm, X86_INS_VBLENDVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDVPSYrr, X86_INS_VBLENDVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDVPSrm, X86_INS_VBLENDVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBLENDVPSrr, X86_INS_VBLENDVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF128, X86_INS_VBROADCASTF128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X2Z256m, X86_INS_VBROADCASTF32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X2Z256mk, X86_INS_VBROADCASTF32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X2Z256mkz, X86_INS_VBROADCASTF32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X2Z256r, X86_INS_VBROADCASTF32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X2Z256rk, X86_INS_VBROADCASTF32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X2Z256rkz, X86_INS_VBROADCASTF32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X2Zm, X86_INS_VBROADCASTF32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X2Zmk, X86_INS_VBROADCASTF32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X2Zmkz, X86_INS_VBROADCASTF32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X2Zr, X86_INS_VBROADCASTF32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X2Zrk, X86_INS_VBROADCASTF32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X2Zrkz, X86_INS_VBROADCASTF32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X4Z256rm, X86_INS_VBROADCASTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X4Z256rmk, X86_INS_VBROADCASTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X4Z256rmkz, X86_INS_VBROADCASTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X4rm, X86_INS_VBROADCASTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X4rmk, X86_INS_VBROADCASTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X4rmkz, X86_INS_VBROADCASTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X8rm, X86_INS_VBROADCASTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X8rmk, X86_INS_VBROADCASTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF32X8rmkz, X86_INS_VBROADCASTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF64X2Z128rm, X86_INS_VBROADCASTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF64X2Z128rmk, X86_INS_VBROADCASTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF64X2Z128rmkz, X86_INS_VBROADCASTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF64X2rm, X86_INS_VBROADCASTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF64X2rmk, X86_INS_VBROADCASTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF64X2rmkz, X86_INS_VBROADCASTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF64X4rm, X86_INS_VBROADCASTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF64X4rmk, X86_INS_VBROADCASTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTF64X4rmkz, X86_INS_VBROADCASTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI128, X86_INS_VBROADCASTI128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Z128m, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Z128mk, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Z128mkz, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Z128r, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Z128rk, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Z128rkz, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Z256m, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Z256mk, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Z256mkz, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Z256r, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Z256rk, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Z256rkz, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Zm, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Zmk, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Zmkz, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Zr, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Zrk, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X2Zrkz, X86_INS_VBROADCASTI32X2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X4Z256rm, X86_INS_VBROADCASTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X4Z256rmk, X86_INS_VBROADCASTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X4Z256rmkz, X86_INS_VBROADCASTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X4rm, X86_INS_VBROADCASTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X4rmk, X86_INS_VBROADCASTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X4rmkz, X86_INS_VBROADCASTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X8rm, X86_INS_VBROADCASTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X8rmk, X86_INS_VBROADCASTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI32X8rmkz, X86_INS_VBROADCASTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI64X2Z128rm, X86_INS_VBROADCASTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI64X2Z128rmk, X86_INS_VBROADCASTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI64X2Z128rmkz, X86_INS_VBROADCASTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI64X2rm, X86_INS_VBROADCASTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI64X2rmk, X86_INS_VBROADCASTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI64X2rmkz, X86_INS_VBROADCASTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI64X4rm, X86_INS_VBROADCASTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI64X4rmk, X86_INS_VBROADCASTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTI64X4rmkz, X86_INS_VBROADCASTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDYrm, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDYrr, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDZ256m, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDZ256mk, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDZ256mkz, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDZ256r, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDZ256rk, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDZ256rkz, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDZm, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDZmk, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDZmkz, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDZr, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDZrk, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSDZrkz, X86_INS_VBROADCASTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSYrm, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSYrr, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZ128m, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZ128mk, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZ128mkz, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZ128r, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZ128rk, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZ128rkz, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZ256m, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZ256mk, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZ256mkz, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZ256r, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZ256rk, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZ256rkz, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZm, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZmk, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZmkz, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZr, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZrk, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSZrkz, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSrm, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VBROADCASTSSrr, X86_INS_VBROADCASTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDYrmi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDYrmi_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDYrri, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDYrri_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ128rmbi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ128rmbi_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ128rmbi_altk, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ128rmbik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ128rmi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ128rmi_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ128rmi_altk, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ128rmik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ128rri, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ128rri_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ128rri_altk, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ128rrik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ256rmbi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ256rmbi_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ256rmbi_altk, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ256rmbik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ256rmi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ256rmi_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ256rmi_altk, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ256rmik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ256rri, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ256rri_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ256rri_altk, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZ256rrik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrmbi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrmbi_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrmbi_altk, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrmbik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrmi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrmi_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrmi_altk, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrmik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrri, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrri_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrri_altk, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrrib, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrrib_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrrib_altk, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrribk, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDZrrik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDrmi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDrmi_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDrri, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPDrri_alt, X86_INS_VCMPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSYrmi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSYrmi_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSYrri, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSYrri_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ128rmbi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ128rmbi_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ128rmbi_altk, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ128rmbik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ128rmi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ128rmi_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ128rmi_altk, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ128rmik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ128rri, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ128rri_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ128rri_altk, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ128rrik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ256rmbi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ256rmbi_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ256rmbi_altk, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ256rmbik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ256rmi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ256rmi_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ256rmi_altk, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ256rmik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ256rri, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ256rri_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ256rri_altk, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZ256rrik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrmbi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrmbi_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrmbi_altk, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrmbik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrmi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrmi_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrmi_altk, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrmik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrri, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrri_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrri_altk, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrrib, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrrib_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrrib_altk, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrribk, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSZrrik, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSrmi, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSrmi_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSrri, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPPSrri_alt, X86_INS_VCMPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrm, X86_INS_VCMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrm_Int, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrm_Intk, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrmi_alt, X86_INS_VCMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrmi_altk, X86_INS_VCMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrr, X86_INS_VCMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrr_Int, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrr_Intk, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrrb_Int, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrrb_Intk, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrrb_alt, X86_INS_VCMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrrb_altk, X86_INS_VCMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrri_alt, X86_INS_VCMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDZrri_altk, X86_INS_VCMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDrm, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDrm_Int, X86_INS_VCMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDrm_alt, X86_INS_VCMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDrr, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDrr_Int, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSDrr_alt, X86_INS_VCMPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrm, X86_INS_VCMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrm_Int, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrm_Intk, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrmi_alt, X86_INS_VCMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrmi_altk, X86_INS_VCMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrr, X86_INS_VCMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrr_Int, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrr_Intk, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrrb_Int, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrrb_Intk, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrrb_alt, X86_INS_VCMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrrb_altk, X86_INS_VCMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrri_alt, X86_INS_VCMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSZrri_altk, X86_INS_VCMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSrm, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSrm_Int, X86_INS_VCMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSrm_alt, X86_INS_VCMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSrr, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSrr_Int, X86_INS_VCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCMPSSrr_alt, X86_INS_VCMPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISDZrm, X86_INS_VCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISDZrm_Int, X86_INS_VCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISDZrr, X86_INS_VCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISDZrr_Int, X86_INS_VCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISDZrrb, X86_INS_VCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISDrm, X86_INS_VCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISDrm_Int, X86_INS_VCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISDrr, X86_INS_VCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISDrr_Int, X86_INS_VCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISSZrm, X86_INS_VCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISSZrm_Int, X86_INS_VCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISSZrr, X86_INS_VCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISSZrr_Int, X86_INS_VCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISSZrrb, X86_INS_VCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISSrm, X86_INS_VCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISSrm_Int, X86_INS_VCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISSrr, X86_INS_VCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMISSrr_Int, X86_INS_VCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZ128mr, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZ128mrk, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZ128rr, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZ128rrk, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZ128rrkz, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZ256mr, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZ256mrk, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZ256rr, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZ256rrk, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZ256rrkz, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZmr, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZmrk, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZrr, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZrrk, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPDZrrkz, X86_INS_VCOMPRESSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZ128mr, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZ128mrk, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZ128rr, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZ128rrk, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZ128rrkz, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZ256mr, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZ256mrk, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZ256rr, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZ256rrk, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZ256rrkz, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZmr, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZmrk, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZrr, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZrrk, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCOMPRESSPSZrrkz, X86_INS_VCOMPRESSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDYrm, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDYrr, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ128rm, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ128rmb, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ128rmbk, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ128rmbkz, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ128rmk, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ128rmkz, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ128rr, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ128rrk, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ128rrkz, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ256rm, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ256rmb, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ256rmbk, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ256rmbkz, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ256rmk, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ256rmkz, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ256rr, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ256rrk, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZ256rrkz, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZrm, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZrmb, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZrmbk, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZrmbkz, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZrmk, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZrmkz, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZrr, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZrrk, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDZrrkz, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDrm, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PDrr, X86_INS_VCVTDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSYrm, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSYrr, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ128rm, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ128rmb, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ128rmbk, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ128rmbkz, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ128rmk, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ128rmkz, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ128rr, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ128rrk, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ128rrkz, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ256rm, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ256rmb, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ256rmbk, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ256rmbkz, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ256rmk, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ256rmkz, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ256rr, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ256rrk, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZ256rrkz, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZrm, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZrmb, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZrmbk, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZrmbkz, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZrmk, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZrmkz, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZrr, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZrrb, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZrrbk, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZrrbkz, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZrrk, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSZrrkz, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSrm, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTDQ2PSrr, X86_INS_VCVTDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQYrm, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQYrr, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ128rm, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ128rmb, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ128rmbk, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ128rmbkz, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ128rmk, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ128rmkz, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ128rr, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ128rrk, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ128rrkz, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ256rm, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ256rmb, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ256rmbk, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ256rmbkz, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ256rmk, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ256rmkz, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ256rr, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ256rrk, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZ256rrkz, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZrm, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZrmb, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZrmbk, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZrmbkz, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZrmk, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZrmkz, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZrr, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZrrb, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZrrbk, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZrrbkz, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZrrk, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQZrrkz, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQrm, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2DQrr, X86_INS_VCVTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSYrm, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSYrr, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ128rm, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ128rmb, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ128rmbk, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ128rmbkz, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ128rmk, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ128rmkz, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ128rr, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ128rrk, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ128rrkz, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ256rm, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ256rmb, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ256rmbk, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ256rmbkz, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ256rmk, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ256rmkz, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ256rr, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ256rrk, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZ256rrkz, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZrm, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZrmb, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZrmbk, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZrmbkz, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZrmk, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZrmkz, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZrr, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZrrb, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZrrbk, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZrrbkz, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZrrk, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSZrrkz, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSrm, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2PSrr, X86_INS_VCVTPD2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ128rm, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ128rmb, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ128rmbk, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ128rmbkz, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ128rmk, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ128rmkz, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ128rr, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ128rrk, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ128rrkz, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ256rm, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ256rmb, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ256rmbk, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ256rmbkz, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ256rmk, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ256rmkz, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ256rr, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ256rrk, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZ256rrkz, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZrm, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZrmb, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZrmbk, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZrmbkz, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZrmk, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZrmkz, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZrr, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZrrb, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZrrbk, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZrrbkz, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZrrk, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2QQZrrkz, X86_INS_VCVTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ128rm, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ128rmb, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ128rmbk, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ128rmbkz, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ128rmk, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ128rmkz, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ128rr, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ128rrk, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ128rrkz, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ256rm, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ256rmb, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ256rmbk, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ256rmbkz, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ256rmk, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ256rmkz, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ256rr, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ256rrk, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZ256rrkz, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZrm, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZrmb, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZrmbk, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZrmbkz, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZrmk, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZrmkz, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZrr, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZrrb, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZrrbk, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZrrbkz, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZrrk, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UDQZrrkz, X86_INS_VCVTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ128rm, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ128rmb, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ128rmbk, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ128rmbkz, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ128rmk, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ128rmkz, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ128rr, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ128rrk, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ128rrkz, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ256rm, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ256rmb, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ256rmbk, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ256rmbkz, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ256rmk, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ256rmkz, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ256rr, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ256rrk, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZ256rrkz, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZrm, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZrmb, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZrmbk, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZrmbkz, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZrmk, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZrmkz, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZrr, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZrrb, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZrrbk, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZrrbkz, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZrrk, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPD2UQQZrrkz, X86_INS_VCVTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSYrm, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSYrr, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZ128rm, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZ128rmk, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZ128rmkz, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZ128rr, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZ128rrk, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZ128rrkz, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZ256rm, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZ256rmk, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZ256rmkz, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZ256rr, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZ256rrk, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZ256rrkz, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZrm, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZrmk, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZrmkz, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZrr, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZrrb, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZrrbk, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZrrbkz, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZrrk, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSZrrkz, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSrm, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPH2PSrr, X86_INS_VCVTPH2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQYrm, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQYrr, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ128rm, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ128rmb, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ128rmbk, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ128rmbkz, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ128rmk, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ128rmkz, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ128rr, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ128rrk, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ128rrkz, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ256rm, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ256rmb, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ256rmbk, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ256rmbkz, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ256rmk, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ256rmkz, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ256rr, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ256rrk, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZ256rrkz, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZrm, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZrmb, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZrmbk, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZrmbkz, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZrmk, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZrmkz, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZrr, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZrrb, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZrrbk, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZrrbkz, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZrrk, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQZrrkz, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQrm, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2DQrr, X86_INS_VCVTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDYrm, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDYrr, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ128rm, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ128rmb, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ128rmbk, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ128rmbkz, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ128rmk, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ128rmkz, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ128rr, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ128rrk, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ128rrkz, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ256rm, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ256rmb, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ256rmbk, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ256rmbkz, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ256rmk, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ256rmkz, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ256rr, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ256rrk, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZ256rrkz, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZrm, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZrmb, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZrmbk, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZrmbkz, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZrmk, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZrmkz, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZrr, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZrrb, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZrrbk, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZrrbkz, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZrrk, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDZrrkz, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDrm, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PDrr, X86_INS_VCVTPS2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHYmr, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHYrr, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZ128mr, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZ128mrk, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZ128rr, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZ128rrk, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZ128rrkz, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZ256mr, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZ256mrk, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZ256rr, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZ256rrk, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZ256rrkz, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZmr, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZmrk, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZrr, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZrrb, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZrrbk, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZrrbkz, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZrrk, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHZrrkz, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHmr, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2PHrr, X86_INS_VCVTPS2PH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ128rm, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ128rmb, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ128rmbk, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ128rmbkz, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ128rmk, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ128rmkz, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ128rr, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ128rrk, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ128rrkz, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ256rm, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ256rmb, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ256rmbk, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ256rmbkz, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ256rmk, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ256rmkz, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ256rr, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ256rrk, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZ256rrkz, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZrm, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZrmb, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZrmbk, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZrmbkz, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZrmk, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZrmkz, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZrr, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZrrb, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZrrbk, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZrrbkz, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZrrk, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2QQZrrkz, X86_INS_VCVTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ128rm, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ128rmb, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ128rmbk, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ128rmbkz, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ128rmk, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ128rmkz, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ128rr, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ128rrk, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ128rrkz, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ256rm, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ256rmb, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ256rmbk, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ256rmbkz, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ256rmk, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ256rmkz, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ256rr, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ256rrk, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZ256rrkz, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZrm, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZrmb, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZrmbk, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZrmbkz, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZrmk, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZrmkz, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZrr, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZrrb, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZrrbk, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZrrbkz, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZrrk, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UDQZrrkz, X86_INS_VCVTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ128rm, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ128rmb, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ128rmbk, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ128rmbkz, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ128rmk, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ128rmkz, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ128rr, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ128rrk, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ128rrkz, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ256rm, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ256rmb, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ256rmbk, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ256rmbkz, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ256rmk, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ256rmkz, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ256rr, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ256rrk, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZ256rrkz, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZrm, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZrmb, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZrmbk, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZrmbkz, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZrmk, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZrmkz, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZrr, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZrrb, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZrrbk, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZrrbkz, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZrrk, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTPS2UQQZrrkz, X86_INS_VCVTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ128rm, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ128rmb, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ128rmbk, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ128rmbkz, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ128rmk, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ128rmkz, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ128rr, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ128rrk, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ128rrkz, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ256rm, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ256rmb, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ256rmbk, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ256rmbkz, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ256rmk, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ256rmkz, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ256rr, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ256rrk, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZ256rrkz, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZrm, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZrmb, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZrmbk, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZrmbkz, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZrmk, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZrmkz, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZrr, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZrrb, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZrrbk, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZrrbkz, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZrrk, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PDZrrkz, X86_INS_VCVTQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ128rm, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ128rmb, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ128rmbk, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ128rmbkz, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ128rmk, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ128rmkz, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ128rr, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ128rrk, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ128rrkz, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ256rm, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ256rmb, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ256rmbk, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ256rmbkz, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ256rmk, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ256rmkz, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ256rr, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ256rrk, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZ256rrkz, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZrm, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZrmb, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZrmbk, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZrmbkz, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZrmk, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZrmkz, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZrr, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZrrb, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZrrbk, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZrrbkz, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZrrk, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTQQ2PSZrrkz, X86_INS_VCVTQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SI64Zrm_Int, X86_INS_VCVTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SI64Zrr_Int, X86_INS_VCVTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SI64Zrrb_Int, X86_INS_VCVTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SI64rm_Int, X86_INS_VCVTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SI64rr_Int, X86_INS_VCVTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SIZrm_Int, X86_INS_VCVTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SIZrr_Int, X86_INS_VCVTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SIZrrb_Int, X86_INS_VCVTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SIrm_Int, X86_INS_VCVTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SIrr_Int, X86_INS_VCVTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSZrm, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSZrm_Int, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSZrm_Intk, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSZrm_Intkz, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSZrr, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSZrr_Int, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSZrr_Intk, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSZrr_Intkz, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSZrrb_Int, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSZrrb_Intk, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSZrrb_Intkz, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSrm, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSrm_Int, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSrr, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2SSrr_Int, X86_INS_VCVTSD2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2USI64Zrm_Int, X86_INS_VCVTSD2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2USI64Zrr_Int, X86_INS_VCVTSD2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2USI64Zrrb_Int, X86_INS_VCVTSD2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2USIZrm_Int, X86_INS_VCVTSD2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2USIZrr_Int, X86_INS_VCVTSD2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSD2USIZrrb_Int, X86_INS_VCVTSD2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SDZrm, X86_INS_VCVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SDZrm_Int, X86_INS_VCVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SDZrr, X86_INS_VCVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SDZrr_Int, X86_INS_VCVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SDZrrb_Int, X86_INS_VCVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SDrm, X86_INS_VCVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SDrm_Int, X86_INS_VCVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SDrr, X86_INS_VCVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SDrr_Int, X86_INS_VCVTSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SSZrm, X86_INS_VCVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SSZrm_Int, X86_INS_VCVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SSZrr, X86_INS_VCVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SSZrr_Int, X86_INS_VCVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SSZrrb_Int, X86_INS_VCVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SSrm, X86_INS_VCVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SSrm_Int, X86_INS_VCVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SSrr, X86_INS_VCVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI2SSrr_Int, X86_INS_VCVTSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SDZrm, X86_INS_VCVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SDZrm_Int, X86_INS_VCVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SDZrr, X86_INS_VCVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SDZrr_Int, X86_INS_VCVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SDZrrb_Int, X86_INS_VCVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SDrm, X86_INS_VCVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SDrm_Int, X86_INS_VCVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SDrr, X86_INS_VCVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SDrr_Int, X86_INS_VCVTSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SSZrm, X86_INS_VCVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SSZrm_Int, X86_INS_VCVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SSZrr, X86_INS_VCVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SSZrr_Int, X86_INS_VCVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SSZrrb_Int, X86_INS_VCVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SSrm, X86_INS_VCVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SSrm_Int, X86_INS_VCVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SSrr, X86_INS_VCVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSI642SSrr_Int, X86_INS_VCVTSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDZrm, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDZrm_Int, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDZrm_Intk, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDZrm_Intkz, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDZrr, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDZrr_Int, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDZrr_Intk, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDZrr_Intkz, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDZrrb_Int, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDZrrb_Intk, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDZrrb_Intkz, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDrm, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDrm_Int, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDrr, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SDrr_Int, X86_INS_VCVTSS2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SI64Zrm_Int, X86_INS_VCVTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SI64Zrr_Int, X86_INS_VCVTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SI64Zrrb_Int, X86_INS_VCVTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SI64rm_Int, X86_INS_VCVTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SI64rr_Int, X86_INS_VCVTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SIZrm_Int, X86_INS_VCVTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SIZrr_Int, X86_INS_VCVTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SIZrrb_Int, X86_INS_VCVTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SIrm_Int, X86_INS_VCVTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2SIrr_Int, X86_INS_VCVTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2USI64Zrm_Int, X86_INS_VCVTSS2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2USI64Zrr_Int, X86_INS_VCVTSS2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2USI64Zrrb_Int, X86_INS_VCVTSS2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2USIZrm_Int, X86_INS_VCVTSS2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2USIZrr_Int, X86_INS_VCVTSS2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTSS2USIZrrb_Int, X86_INS_VCVTSS2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQYrm, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQYrr, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ128rm, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ128rmb, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ128rmbk, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ128rmbkz, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ128rmk, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ128rmkz, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ128rr, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ128rrk, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ128rrkz, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ256rm, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ256rmb, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ256rmbk, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ256rmbkz, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ256rmk, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ256rmkz, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ256rr, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ256rrk, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZ256rrkz, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZrm, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZrmb, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZrmbk, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZrmbkz, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZrmk, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZrmkz, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZrr, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZrrb, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZrrbk, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZrrbkz, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZrrk, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQZrrkz, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQrm, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2DQrr, X86_INS_VCVTTPD2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ128rm, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ128rmb, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ128rmbk, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ128rmbkz, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ128rmk, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ128rmkz, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ128rr, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ128rrk, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ128rrkz, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ256rm, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ256rmb, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ256rmbk, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ256rmbkz, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ256rmk, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ256rmkz, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ256rr, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ256rrk, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZ256rrkz, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZrm, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZrmb, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZrmbk, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZrmbkz, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZrmk, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZrmkz, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZrr, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZrrb, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZrrbk, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZrrbkz, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZrrk, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2QQZrrkz, X86_INS_VCVTTPD2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ128rm, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ128rmb, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ128rmbk, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ128rmbkz, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ128rmk, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ128rmkz, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ128rr, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ128rrk, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ128rrkz, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ256rm, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ256rmb, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ256rmbk, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ256rmbkz, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ256rmk, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ256rmkz, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ256rr, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ256rrk, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZ256rrkz, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZrm, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZrmb, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZrmbk, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZrmbkz, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZrmk, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZrmkz, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZrr, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZrrb, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZrrbk, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZrrbkz, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZrrk, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UDQZrrkz, X86_INS_VCVTTPD2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ128rm, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ128rmb, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ128rmbk, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ128rmbkz, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ128rmk, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ128rmkz, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ128rr, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ128rrk, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ128rrkz, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ256rm, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ256rmb, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ256rmbk, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ256rmbkz, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ256rmk, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ256rmkz, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ256rr, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ256rrk, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZ256rrkz, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZrm, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZrmb, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZrmbk, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZrmbkz, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZrmk, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZrmkz, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZrr, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZrrb, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZrrbk, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZrrbkz, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZrrk, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPD2UQQZrrkz, X86_INS_VCVTTPD2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQYrm, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQYrr, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ128rm, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ128rmb, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ128rmbk, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ128rmbkz, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ128rmk, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ128rmkz, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ128rr, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ128rrk, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ128rrkz, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ256rm, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ256rmb, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ256rmbk, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ256rmbkz, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ256rmk, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ256rmkz, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ256rr, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ256rrk, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZ256rrkz, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZrm, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZrmb, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZrmbk, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZrmbkz, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZrmk, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZrmkz, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZrr, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZrrb, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZrrbk, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZrrbkz, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZrrk, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQZrrkz, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQrm, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2DQrr, X86_INS_VCVTTPS2DQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ128rm, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ128rmb, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ128rmbk, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ128rmbkz, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ128rmk, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ128rmkz, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ128rr, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ128rrk, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ128rrkz, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ256rm, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ256rmb, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ256rmbk, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ256rmbkz, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ256rmk, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ256rmkz, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ256rr, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ256rrk, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZ256rrkz, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZrm, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZrmb, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZrmbk, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZrmbkz, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZrmk, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZrmkz, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZrr, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZrrb, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZrrbk, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZrrbkz, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZrrk, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2QQZrrkz, X86_INS_VCVTTPS2QQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ128rm, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ128rmb, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ128rmbk, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ128rmbkz, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ128rmk, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ128rmkz, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ128rr, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ128rrk, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ128rrkz, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ256rm, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ256rmb, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ256rmbk, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ256rmbkz, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ256rmk, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ256rmkz, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ256rr, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ256rrk, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZ256rrkz, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZrm, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZrmb, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZrmbk, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZrmbkz, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZrmk, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZrmkz, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZrr, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZrrb, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZrrbk, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZrrbkz, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZrrk, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UDQZrrkz, X86_INS_VCVTTPS2UDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ128rm, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ128rmb, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ128rmbk, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ128rmbkz, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ128rmk, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ128rmkz, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ128rr, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ128rrk, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ128rrkz, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ256rm, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ256rmb, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ256rmbk, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ256rmbkz, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ256rmk, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ256rmkz, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ256rr, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ256rrk, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZ256rrkz, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZrm, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZrmb, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZrmbk, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZrmbkz, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZrmk, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZrmkz, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZrr, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZrrb, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZrrbk, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZrrbkz, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZrrk, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTPS2UQQZrrkz, X86_INS_VCVTTPS2UQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SI64Zrm, X86_INS_VCVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SI64Zrm_Int, X86_INS_VCVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SI64Zrr, X86_INS_VCVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SI64Zrr_Int, X86_INS_VCVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SI64Zrrb_Int, X86_INS_VCVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SI64rm, X86_INS_VCVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SI64rm_Int, X86_INS_VCVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SI64rr, X86_INS_VCVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SI64rr_Int, X86_INS_VCVTTSD2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SIZrm, X86_INS_VCVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SIZrm_Int, X86_INS_VCVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SIZrr, X86_INS_VCVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SIZrr_Int, X86_INS_VCVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SIZrrb_Int, X86_INS_VCVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SIrm, X86_INS_VCVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SIrm_Int, X86_INS_VCVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SIrr, X86_INS_VCVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2SIrr_Int, X86_INS_VCVTTSD2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2USI64Zrm, X86_INS_VCVTTSD2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2USI64Zrm_Int, X86_INS_VCVTTSD2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2USI64Zrr, X86_INS_VCVTTSD2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2USI64Zrr_Int, X86_INS_VCVTTSD2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2USI64Zrrb_Int, X86_INS_VCVTTSD2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2USIZrm, X86_INS_VCVTTSD2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2USIZrm_Int, X86_INS_VCVTTSD2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2USIZrr, X86_INS_VCVTTSD2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2USIZrr_Int, X86_INS_VCVTTSD2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSD2USIZrrb_Int, X86_INS_VCVTTSD2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SI64Zrm, X86_INS_VCVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SI64Zrm_Int, X86_INS_VCVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SI64Zrr, X86_INS_VCVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SI64Zrr_Int, X86_INS_VCVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SI64Zrrb_Int, X86_INS_VCVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SI64rm, X86_INS_VCVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SI64rm_Int, X86_INS_VCVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SI64rr, X86_INS_VCVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SI64rr_Int, X86_INS_VCVTTSS2SI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SIZrm, X86_INS_VCVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SIZrm_Int, X86_INS_VCVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SIZrr, X86_INS_VCVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SIZrr_Int, X86_INS_VCVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SIZrrb_Int, X86_INS_VCVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SIrm, X86_INS_VCVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SIrm_Int, X86_INS_VCVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SIrr, X86_INS_VCVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2SIrr_Int, X86_INS_VCVTTSS2SI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2USI64Zrm, X86_INS_VCVTTSS2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2USI64Zrm_Int, X86_INS_VCVTTSS2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2USI64Zrr, X86_INS_VCVTTSS2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2USI64Zrr_Int, X86_INS_VCVTTSS2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2USI64Zrrb_Int, X86_INS_VCVTTSS2USI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2USIZrm, X86_INS_VCVTTSS2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2USIZrm_Int, X86_INS_VCVTTSS2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2USIZrr, X86_INS_VCVTTSS2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2USIZrr_Int, X86_INS_VCVTTSS2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTTSS2USIZrrb_Int, X86_INS_VCVTTSS2USI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ128rm, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ128rmb, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ128rmbk, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ128rmbkz, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ128rmk, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ128rmkz, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ128rr, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ128rrk, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ128rrkz, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ256rm, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ256rmb, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ256rmbk, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ256rmbkz, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ256rmk, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ256rmkz, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ256rr, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ256rrk, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZ256rrkz, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZrm, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZrmb, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZrmbk, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZrmbkz, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZrmk, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZrmkz, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZrr, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZrrk, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PDZrrkz, X86_INS_VCVTUDQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ128rm, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ128rmb, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ128rmbk, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ128rmbkz, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ128rmk, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ128rmkz, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ128rr, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ128rrk, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ128rrkz, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ256rm, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ256rmb, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ256rmbk, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ256rmbkz, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ256rmk, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ256rmkz, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ256rr, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ256rrk, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZ256rrkz, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZrm, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZrmb, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZrmbk, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZrmbkz, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZrmk, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZrmkz, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZrr, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZrrb, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZrrbk, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZrrbkz, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZrrk, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUDQ2PSZrrkz, X86_INS_VCVTUDQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ128rm, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ128rmb, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ128rmbk, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ128rmbkz, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ128rmk, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ128rmkz, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ128rr, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ128rrk, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ128rrkz, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ256rm, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ256rmb, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ256rmbk, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ256rmbkz, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ256rmk, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ256rmkz, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ256rr, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ256rrk, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZ256rrkz, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZrm, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZrmb, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZrmbk, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZrmbkz, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZrmk, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZrmkz, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZrr, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZrrb, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZrrbk, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZrrbkz, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZrrk, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PDZrrkz, X86_INS_VCVTUQQ2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ128rm, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ128rmb, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ128rmbk, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ128rmbkz, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ128rmk, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ128rmkz, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ128rr, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ128rrk, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ128rrkz, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ256rm, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ256rmb, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ256rmbk, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ256rmbkz, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ256rmk, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ256rmkz, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ256rr, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ256rrk, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZ256rrkz, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZrm, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZrmb, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZrmbk, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZrmbkz, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZrmk, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZrmkz, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZrr, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZrrb, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZrrbk, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZrrbkz, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZrrk, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUQQ2PSZrrkz, X86_INS_VCVTUQQ2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI2SDZrm, X86_INS_VCVTUSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI2SDZrm_Int, X86_INS_VCVTUSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI2SDZrr, X86_INS_VCVTUSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI2SDZrr_Int, X86_INS_VCVTUSI2SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI2SSZrm, X86_INS_VCVTUSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI2SSZrm_Int, X86_INS_VCVTUSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI2SSZrr, X86_INS_VCVTUSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI2SSZrr_Int, X86_INS_VCVTUSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI2SSZrrb_Int, X86_INS_VCVTUSI2SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI642SDZrm, X86_INS_VCVTUSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI642SDZrm_Int, X86_INS_VCVTUSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI642SDZrr, X86_INS_VCVTUSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI642SDZrr_Int, X86_INS_VCVTUSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI642SDZrrb_Int, X86_INS_VCVTUSI2SD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI642SSZrm, X86_INS_VCVTUSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI642SSZrm_Int, X86_INS_VCVTUSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI642SSZrr, X86_INS_VCVTUSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI642SSZrr_Int, X86_INS_VCVTUSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VCVTUSI642SSZrrb_Int, X86_INS_VCVTUSI2SS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZ128rmi, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZ128rmik, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZ128rmikz, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZ128rri, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZ128rrik, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZ128rrikz, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZ256rmi, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZ256rmik, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZ256rmikz, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZ256rri, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZ256rrik, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZ256rrikz, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZrmi, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZrmik, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZrmikz, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZrri, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZrrik, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDBPSADBWZrrikz, X86_INS_VDBPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDYrm, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDYrr, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ128rm, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ128rmb, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ128rmbk, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ128rmbkz, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ128rmk, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ128rmkz, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ128rr, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ128rrk, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ128rrkz, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ256rm, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ256rmb, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ256rmbk, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ256rmbkz, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ256rmk, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ256rmkz, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ256rr, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ256rrk, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZ256rrkz, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZrm, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZrmb, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZrmbk, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZrmbkz, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZrmk, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZrmkz, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZrr, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZrrb, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZrrbk, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZrrbkz, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZrrk, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDZrrkz, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDrm, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPDrr, X86_INS_VDIVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSYrm, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSYrr, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ128rm, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ128rmb, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ128rmbk, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ128rmbkz, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ128rmk, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ128rmkz, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ128rr, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ128rrk, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ128rrkz, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ256rm, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ256rmb, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ256rmbk, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ256rmbkz, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ256rmk, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ256rmkz, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ256rr, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ256rrk, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZ256rrkz, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZrm, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZrmb, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZrmbk, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZrmbkz, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZrmk, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZrmkz, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZrr, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZrrb, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZrrbk, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZrrbkz, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZrrk, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSZrrkz, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSrm, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVPSrr, X86_INS_VDIVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDZrm, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDZrm_Int, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDZrm_Intk, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDZrm_Intkz, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDZrr, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDZrr_Int, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDZrr_Intk, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDZrr_Intkz, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDZrrb_Int, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDZrrb_Intk, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDZrrb_Intkz, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDrm, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDrm_Int, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDrr, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSDrr_Int, X86_INS_VDIVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSZrm, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSZrm_Int, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSZrm_Intk, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSZrm_Intkz, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSZrr, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSZrr_Int, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSZrr_Intk, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSZrr_Intkz, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSZrrb_Int, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSZrrb_Intk, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSZrrb_Intkz, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSrm, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSrm_Int, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSrr, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDIVSSrr_Int, X86_INS_VDIVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDPPDrmi, X86_INS_VDPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDPPDrri, X86_INS_VDPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDPPSYrmi, X86_INS_VDPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDPPSYrri, X86_INS_VDPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDPPSrmi, X86_INS_VDPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VDPPSrri, X86_INS_VDPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VERRm, X86_INS_VERR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VERRr, X86_INS_VERR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VERWm, X86_INS_VERW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VERWr, X86_INS_VERW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PDZm, X86_INS_VEXP2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PDZmb, X86_INS_VEXP2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PDZmbk, X86_INS_VEXP2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PDZmbkz, X86_INS_VEXP2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PDZmk, X86_INS_VEXP2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PDZmkz, X86_INS_VEXP2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PDZr, X86_INS_VEXP2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PDZrb, X86_INS_VEXP2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PDZrbk, X86_INS_VEXP2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PDZrbkz, X86_INS_VEXP2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PDZrk, X86_INS_VEXP2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PDZrkz, X86_INS_VEXP2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PSZm, X86_INS_VEXP2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PSZmb, X86_INS_VEXP2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PSZmbk, X86_INS_VEXP2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PSZmbkz, X86_INS_VEXP2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PSZmk, X86_INS_VEXP2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PSZmkz, X86_INS_VEXP2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PSZr, X86_INS_VEXP2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PSZrb, X86_INS_VEXP2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PSZrbk, X86_INS_VEXP2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PSZrbkz, X86_INS_VEXP2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PSZrk, X86_INS_VEXP2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXP2PSZrkz, X86_INS_VEXP2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZ128rm, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZ128rmk, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZ128rmkz, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZ128rr, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZ128rrk, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZ128rrkz, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZ256rm, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZ256rmk, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZ256rmkz, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZ256rr, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZ256rrk, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZ256rrkz, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZrm, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZrmk, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZrmkz, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZrr, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZrrk, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPDZrrkz, X86_INS_VEXPANDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZ128rm, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZ128rmk, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZ128rmkz, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZ128rr, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZ128rrk, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZ128rrkz, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZ256rm, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZ256rmk, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZ256rmkz, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZ256rr, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZ256rrk, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZ256rrkz, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZrm, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZrmk, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZrmkz, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZrr, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZrrk, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXPANDPSZrrkz, X86_INS_VEXPANDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF128mr, X86_INS_VEXTRACTF128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF128rr, X86_INS_VEXTRACTF128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x4Z256mr, X86_INS_VEXTRACTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x4Z256mrk, X86_INS_VEXTRACTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x4Z256rr, X86_INS_VEXTRACTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x4Z256rrk, X86_INS_VEXTRACTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x4Z256rrkz, X86_INS_VEXTRACTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x4Zmr, X86_INS_VEXTRACTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x4Zmrk, X86_INS_VEXTRACTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x4Zrr, X86_INS_VEXTRACTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x4Zrrk, X86_INS_VEXTRACTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x4Zrrkz, X86_INS_VEXTRACTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x8Zmr, X86_INS_VEXTRACTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x8Zmrk, X86_INS_VEXTRACTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x8Zrr, X86_INS_VEXTRACTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x8Zrrk, X86_INS_VEXTRACTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF32x8Zrrkz, X86_INS_VEXTRACTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x2Z256mr, X86_INS_VEXTRACTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x2Z256mrk, X86_INS_VEXTRACTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x2Z256rr, X86_INS_VEXTRACTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x2Z256rrk, X86_INS_VEXTRACTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x2Z256rrkz, X86_INS_VEXTRACTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x2Zmr, X86_INS_VEXTRACTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x2Zmrk, X86_INS_VEXTRACTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x2Zrr, X86_INS_VEXTRACTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x2Zrrk, X86_INS_VEXTRACTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x2Zrrkz, X86_INS_VEXTRACTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x4Zmr, X86_INS_VEXTRACTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x4Zmrk, X86_INS_VEXTRACTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x4Zrr, X86_INS_VEXTRACTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x4Zrrk, X86_INS_VEXTRACTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTF64x4Zrrkz, X86_INS_VEXTRACTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI128mr, X86_INS_VEXTRACTI128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI128rr, X86_INS_VEXTRACTI128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x4Z256mr, X86_INS_VEXTRACTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x4Z256mrk, X86_INS_VEXTRACTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x4Z256rr, X86_INS_VEXTRACTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x4Z256rrk, X86_INS_VEXTRACTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x4Z256rrkz, X86_INS_VEXTRACTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x4Zmr, X86_INS_VEXTRACTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x4Zmrk, X86_INS_VEXTRACTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x4Zrr, X86_INS_VEXTRACTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x4Zrrk, X86_INS_VEXTRACTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x4Zrrkz, X86_INS_VEXTRACTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x8Zmr, X86_INS_VEXTRACTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x8Zmrk, X86_INS_VEXTRACTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x8Zrr, X86_INS_VEXTRACTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x8Zrrk, X86_INS_VEXTRACTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI32x8Zrrkz, X86_INS_VEXTRACTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x2Z256mr, X86_INS_VEXTRACTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x2Z256mrk, X86_INS_VEXTRACTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x2Z256rr, X86_INS_VEXTRACTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x2Z256rrk, X86_INS_VEXTRACTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x2Z256rrkz, X86_INS_VEXTRACTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x2Zmr, X86_INS_VEXTRACTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x2Zmrk, X86_INS_VEXTRACTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x2Zrr, X86_INS_VEXTRACTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x2Zrrk, X86_INS_VEXTRACTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x2Zrrkz, X86_INS_VEXTRACTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x4Zmr, X86_INS_VEXTRACTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x4Zmrk, X86_INS_VEXTRACTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x4Zrr, X86_INS_VEXTRACTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x4Zrrk, X86_INS_VEXTRACTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTI64x4Zrrkz, X86_INS_VEXTRACTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTPSZmr, X86_INS_VEXTRACTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTPSZrr, X86_INS_VEXTRACTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTPSmr, X86_INS_VEXTRACTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VEXTRACTPSrr, X86_INS_VEXTRACTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ128rmbi, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ128rmbik, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ128rmbikz, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ128rmi, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ128rmik, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ128rmikz, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ128rri, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ128rrik, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ128rrikz, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ256rmbi, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ256rmbik, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ256rmbikz, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ256rmi, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ256rmik, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ256rmikz, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ256rri, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ256rrik, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZ256rrikz, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZrmbi, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZrmbik, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZrmbikz, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZrmi, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZrmik, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZrmikz, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZrri, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZrrib, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZrribk, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZrribkz, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZrrik, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPDZrrikz, X86_INS_VFIXUPIMMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ128rmbi, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ128rmbik, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ128rmbikz, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ128rmi, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ128rmik, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ128rmikz, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ128rri, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ128rrik, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ128rrikz, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ256rmbi, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ256rmbik, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ256rmbikz, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ256rmi, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ256rmik, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ256rmikz, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ256rri, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ256rrik, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZ256rrikz, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZrmbi, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZrmbik, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZrmbikz, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZrmi, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZrmik, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZrmikz, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZrri, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZrrib, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZrribk, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZrribkz, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZrrik, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMPSZrrikz, X86_INS_VFIXUPIMMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSDZrmi, X86_INS_VFIXUPIMMSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSDZrmik, X86_INS_VFIXUPIMMSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSDZrmikz, X86_INS_VFIXUPIMMSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSDZrri, X86_INS_VFIXUPIMMSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSDZrrib, X86_INS_VFIXUPIMMSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSDZrribk, X86_INS_VFIXUPIMMSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSDZrribkz, X86_INS_VFIXUPIMMSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSDZrrik, X86_INS_VFIXUPIMMSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSDZrrikz, X86_INS_VFIXUPIMMSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSSZrmi, X86_INS_VFIXUPIMMSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSSZrmik, X86_INS_VFIXUPIMMSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSSZrmikz, X86_INS_VFIXUPIMMSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSSZrri, X86_INS_VFIXUPIMMSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSSZrrib, X86_INS_VFIXUPIMMSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSSZrribk, X86_INS_VFIXUPIMMSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSSZrribkz, X86_INS_VFIXUPIMMSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSSZrrik, X86_INS_VFIXUPIMMSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFIXUPIMMSSZrrikz, X86_INS_VFIXUPIMMSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDYm, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDYr, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ128m, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ128mb, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ128mbk, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ128mbkz, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ128mk, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ128mkz, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ128r, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ128rk, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ128rkz, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ256m, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ256mb, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ256mbk, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ256mbkz, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ256mk, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ256mkz, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ256r, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ256rk, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZ256rkz, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZm, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZmb, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZmbk, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZmbkz, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZmk, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZmkz, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZr, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZrb, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZrbk, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZrbkz, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZrk, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDZrkz, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDm, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PDr, X86_INS_VFMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSYm, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSYr, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ128m, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ128mb, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ128mbk, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ128mbkz, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ128mk, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ128mkz, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ128r, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ128rk, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ128rkz, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ256m, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ256mb, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ256mbk, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ256mbkz, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ256mk, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ256mkz, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ256r, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ256rk, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZ256rkz, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZm, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZmb, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZmbk, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZmbkz, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZmk, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZmkz, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZr, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZrb, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZrbk, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZrbkz, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZrk, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSZrkz, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSm, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132PSr, X86_INS_VFMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDZm, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDZm_Int, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDZm_Intk, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDZm_Intkz, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDZr, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDZr_Int, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDZr_Intk, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDZr_Intkz, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDZrb, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDZrb_Int, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDZrb_Intk, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDZrb_Intkz, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDm, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDm_Int, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDr, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SDr_Int, X86_INS_VFMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSZm, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSZm_Int, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSZm_Intk, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSZm_Intkz, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSZr, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSZr_Int, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSZr_Intk, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSZr_Intkz, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSZrb, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSZrb_Int, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSZrb_Intk, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSZrb_Intkz, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSm, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSm_Int, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSr, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD132SSr_Int, X86_INS_VFMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDYm, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDYr, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ128m, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ128mb, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ128mbk, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ128mbkz, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ128mk, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ128mkz, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ128r, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ128rk, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ128rkz, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ256m, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ256mb, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ256mbk, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ256mbkz, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ256mk, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ256mkz, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ256r, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ256rk, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZ256rkz, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZm, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZmb, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZmbk, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZmbkz, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZmk, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZmkz, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZr, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZrb, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZrbk, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZrbkz, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZrk, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDZrkz, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDm, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PDr, X86_INS_VFMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSYm, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSYr, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ128m, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ128mb, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ128mbk, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ128mbkz, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ128mk, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ128mkz, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ128r, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ128rk, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ128rkz, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ256m, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ256mb, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ256mbk, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ256mbkz, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ256mk, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ256mkz, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ256r, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ256rk, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZ256rkz, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZm, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZmb, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZmbk, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZmbkz, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZmk, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZmkz, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZr, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZrb, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZrbk, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZrbkz, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZrk, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSZrkz, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSm, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213PSr, X86_INS_VFMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDZm, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDZm_Int, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDZm_Intk, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDZm_Intkz, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDZr, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDZr_Int, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDZr_Intk, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDZr_Intkz, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDZrb, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDZrb_Int, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDZrb_Intk, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDZrb_Intkz, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDm, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDm_Int, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDr, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SDr_Int, X86_INS_VFMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSZm, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSZm_Int, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSZm_Intk, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSZm_Intkz, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSZr, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSZr_Int, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSZr_Intk, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSZr_Intkz, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSZrb, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSZrb_Int, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSZrb_Intk, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSZrb_Intkz, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSm, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSm_Int, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSr, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD213SSr_Int, X86_INS_VFMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDYm, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDYr, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ128m, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ128mb, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ128mbk, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ128mbkz, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ128mk, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ128mkz, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ128r, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ128rk, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ128rkz, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ256m, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ256mb, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ256mbk, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ256mbkz, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ256mk, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ256mkz, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ256r, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ256rk, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZ256rkz, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZm, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZmb, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZmbk, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZmbkz, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZmk, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZmkz, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZr, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZrb, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZrbk, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZrbkz, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZrk, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDZrkz, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDm, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PDr, X86_INS_VFMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSYm, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSYr, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ128m, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ128mb, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ128mbk, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ128mbkz, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ128mk, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ128mkz, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ128r, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ128rk, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ128rkz, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ256m, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ256mb, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ256mbk, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ256mbkz, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ256mk, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ256mkz, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ256r, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ256rk, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZ256rkz, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZm, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZmb, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZmbk, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZmbkz, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZmk, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZmkz, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZr, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZrb, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZrbk, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZrbkz, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZrk, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSZrkz, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSm, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231PSr, X86_INS_VFMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDZm, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDZm_Int, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDZm_Intk, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDZm_Intkz, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDZr, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDZr_Int, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDZr_Intk, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDZr_Intkz, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDZrb, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDZrb_Int, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDZrb_Intk, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDZrb_Intkz, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDm, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDm_Int, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDr, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SDr_Int, X86_INS_VFMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSZm, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSZm_Int, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSZm_Intk, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSZm_Intkz, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSZr, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSZr_Int, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSZr_Intk, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSZr_Intkz, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSZrb, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSZrb_Int, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSZrb_Intk, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSZrb_Intkz, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSm, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSm_Int, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSr, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADD231SSr_Int, X86_INS_VFMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPD4Ymr, X86_INS_VFMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPD4Yrm, X86_INS_VFMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPD4Yrr, X86_INS_VFMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPD4Yrr_REV, X86_INS_VFMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPD4mr, X86_INS_VFMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPD4rm, X86_INS_VFMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPD4rr, X86_INS_VFMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPD4rr_REV, X86_INS_VFMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPS4Ymr, X86_INS_VFMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPS4Yrm, X86_INS_VFMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPS4Yrr, X86_INS_VFMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPS4Yrr_REV, X86_INS_VFMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPS4mr, X86_INS_VFMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPS4rm, X86_INS_VFMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPS4rr, X86_INS_VFMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDPS4rr_REV, X86_INS_VFMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSD4mr, X86_INS_VFMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSD4mr_Int, X86_INS_VFMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSD4rm, X86_INS_VFMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSD4rm_Int, X86_INS_VFMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSD4rr, X86_INS_VFMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSD4rr_Int, X86_INS_VFMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSD4rr_Int_REV, X86_INS_VFMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSD4rr_REV, X86_INS_VFMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSS4mr, X86_INS_VFMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSS4mr_Int, X86_INS_VFMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSS4rm, X86_INS_VFMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSS4rm_Int, X86_INS_VFMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSS4rr, X86_INS_VFMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSS4rr_Int, X86_INS_VFMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSS4rr_Int_REV, X86_INS_VFMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSS4rr_REV, X86_INS_VFMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDYm, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDYr, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ128m, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ128mb, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ128mbk, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ128mbkz, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ128mk, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ128mkz, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ128r, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ128rk, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ128rkz, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ256m, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ256mb, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ256mbk, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ256mbkz, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ256mk, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ256mkz, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ256r, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ256rk, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZ256rkz, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZm, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZmb, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZmbk, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZmbkz, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZmk, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZmkz, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZr, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZrb, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZrbk, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZrbkz, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZrk, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDZrkz, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDm, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PDr, X86_INS_VFMADDSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSYm, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSYr, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ128m, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ128mb, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ128mbk, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ128mbkz, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ128mk, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ128mkz, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ128r, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ128rk, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ128rkz, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ256m, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ256mb, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ256mbk, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ256mbkz, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ256mk, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ256mkz, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ256r, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ256rk, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZ256rkz, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZm, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZmb, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZmbk, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZmbkz, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZmk, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZmkz, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZr, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZrb, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZrbk, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZrbkz, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZrk, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSZrkz, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSm, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB132PSr, X86_INS_VFMADDSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDYm, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDYr, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ128m, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ128mb, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ128mbk, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ128mbkz, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ128mk, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ128mkz, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ128r, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ128rk, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ128rkz, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ256m, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ256mb, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ256mbk, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ256mbkz, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ256mk, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ256mkz, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ256r, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ256rk, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZ256rkz, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZm, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZmb, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZmbk, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZmbkz, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZmk, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZmkz, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZr, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZrb, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZrbk, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZrbkz, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZrk, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDZrkz, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDm, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PDr, X86_INS_VFMADDSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSYm, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSYr, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ128m, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ128mb, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ128mbk, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ128mbkz, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ128mk, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ128mkz, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ128r, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ128rk, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ128rkz, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ256m, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ256mb, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ256mbk, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ256mbkz, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ256mk, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ256mkz, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ256r, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ256rk, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZ256rkz, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZm, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZmb, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZmbk, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZmbkz, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZmk, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZmkz, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZr, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZrb, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZrbk, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZrbkz, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZrk, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSZrkz, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSm, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB213PSr, X86_INS_VFMADDSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDYm, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDYr, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ128m, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ128mb, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ128mbk, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ128mbkz, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ128mk, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ128mkz, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ128r, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ128rk, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ128rkz, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ256m, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ256mb, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ256mbk, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ256mbkz, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ256mk, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ256mkz, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ256r, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ256rk, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZ256rkz, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZm, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZmb, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZmbk, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZmbkz, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZmk, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZmkz, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZr, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZrb, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZrbk, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZrbkz, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZrk, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDZrkz, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDm, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PDr, X86_INS_VFMADDSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSYm, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSYr, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ128m, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ128mb, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ128mbk, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ128mbkz, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ128mk, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ128mkz, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ128r, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ128rk, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ128rkz, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ256m, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ256mb, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ256mbk, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ256mbkz, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ256mk, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ256mkz, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ256r, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ256rk, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZ256rkz, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZm, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZmb, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZmbk, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZmbkz, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZmk, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZmkz, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZr, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZrb, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZrbk, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZrbkz, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZrk, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSZrkz, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSm, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUB231PSr, X86_INS_VFMADDSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPD4Ymr, X86_INS_VFMADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPD4Yrm, X86_INS_VFMADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPD4Yrr, X86_INS_VFMADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPD4Yrr_REV, X86_INS_VFMADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPD4mr, X86_INS_VFMADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPD4rm, X86_INS_VFMADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPD4rr, X86_INS_VFMADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPD4rr_REV, X86_INS_VFMADDSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPS4Ymr, X86_INS_VFMADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPS4Yrm, X86_INS_VFMADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPS4Yrr, X86_INS_VFMADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPS4Yrr_REV, X86_INS_VFMADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPS4mr, X86_INS_VFMADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPS4rm, X86_INS_VFMADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPS4rr, X86_INS_VFMADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMADDSUBPS4rr_REV, X86_INS_VFMADDSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDYm, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDYr, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ128m, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ128mb, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ128mbk, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ128mbkz, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ128mk, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ128mkz, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ128r, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ128rk, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ128rkz, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ256m, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ256mb, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ256mbk, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ256mbkz, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ256mk, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ256mkz, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ256r, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ256rk, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZ256rkz, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZm, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZmb, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZmbk, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZmbkz, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZmk, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZmkz, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZr, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZrb, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZrbk, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZrbkz, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZrk, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDZrkz, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDm, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PDr, X86_INS_VFMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSYm, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSYr, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ128m, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ128mb, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ128mbk, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ128mbkz, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ128mk, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ128mkz, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ128r, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ128rk, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ128rkz, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ256m, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ256mb, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ256mbk, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ256mbkz, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ256mk, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ256mkz, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ256r, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ256rk, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZ256rkz, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZm, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZmb, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZmbk, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZmbkz, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZmk, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZmkz, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZr, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZrb, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZrbk, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZrbkz, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZrk, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSZrkz, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSm, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132PSr, X86_INS_VFMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDZm, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDZm_Int, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDZm_Intk, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDZm_Intkz, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDZr, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDZr_Int, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDZr_Intk, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDZr_Intkz, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDZrb, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDZrb_Int, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDZrb_Intk, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDZrb_Intkz, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDm, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDm_Int, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDr, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SDr_Int, X86_INS_VFMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSZm, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSZm_Int, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSZm_Intk, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSZm_Intkz, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSZr, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSZr_Int, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSZr_Intk, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSZr_Intkz, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSZrb, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSZrb_Int, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSZrb_Intk, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSZrb_Intkz, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSm, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSm_Int, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSr, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB132SSr_Int, X86_INS_VFMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDYm, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDYr, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ128m, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ128mb, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ128mbk, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ128mbkz, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ128mk, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ128mkz, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ128r, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ128rk, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ128rkz, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ256m, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ256mb, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ256mbk, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ256mbkz, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ256mk, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ256mkz, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ256r, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ256rk, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZ256rkz, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZm, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZmb, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZmbk, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZmbkz, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZmk, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZmkz, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZr, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZrb, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZrbk, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZrbkz, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZrk, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDZrkz, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDm, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PDr, X86_INS_VFMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSYm, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSYr, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ128m, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ128mb, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ128mbk, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ128mbkz, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ128mk, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ128mkz, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ128r, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ128rk, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ128rkz, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ256m, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ256mb, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ256mbk, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ256mbkz, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ256mk, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ256mkz, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ256r, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ256rk, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZ256rkz, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZm, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZmb, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZmbk, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZmbkz, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZmk, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZmkz, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZr, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZrb, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZrbk, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZrbkz, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZrk, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSZrkz, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSm, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213PSr, X86_INS_VFMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDZm, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDZm_Int, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDZm_Intk, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDZm_Intkz, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDZr, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDZr_Int, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDZr_Intk, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDZr_Intkz, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDZrb, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDZrb_Int, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDZrb_Intk, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDZrb_Intkz, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDm, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDm_Int, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDr, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SDr_Int, X86_INS_VFMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSZm, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSZm_Int, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSZm_Intk, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSZm_Intkz, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSZr, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSZr_Int, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSZr_Intk, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSZr_Intkz, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSZrb, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSZrb_Int, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSZrb_Intk, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSZrb_Intkz, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSm, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSm_Int, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSr, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB213SSr_Int, X86_INS_VFMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDYm, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDYr, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ128m, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ128mb, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ128mbk, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ128mbkz, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ128mk, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ128mkz, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ128r, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ128rk, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ128rkz, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ256m, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ256mb, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ256mbk, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ256mbkz, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ256mk, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ256mkz, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ256r, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ256rk, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZ256rkz, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZm, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZmb, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZmbk, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZmbkz, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZmk, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZmkz, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZr, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZrb, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZrbk, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZrbkz, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZrk, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDZrkz, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDm, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PDr, X86_INS_VFMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSYm, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSYr, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ128m, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ128mb, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ128mbk, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ128mbkz, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ128mk, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ128mkz, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ128r, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ128rk, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ128rkz, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ256m, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ256mb, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ256mbk, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ256mbkz, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ256mk, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ256mkz, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ256r, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ256rk, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZ256rkz, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZm, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZmb, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZmbk, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZmbkz, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZmk, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZmkz, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZr, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZrb, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZrbk, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZrbkz, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZrk, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSZrkz, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSm, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231PSr, X86_INS_VFMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDZm, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDZm_Int, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDZm_Intk, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDZm_Intkz, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDZr, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDZr_Int, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDZr_Intk, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDZr_Intkz, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDZrb, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDZrb_Int, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDZrb_Intk, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDZrb_Intkz, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDm, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDm_Int, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDr, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SDr_Int, X86_INS_VFMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSZm, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSZm_Int, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSZm_Intk, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSZm_Intkz, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSZr, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSZr_Int, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSZr_Intk, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSZr_Intkz, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSZrb, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSZrb_Int, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSZrb_Intk, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSZrb_Intkz, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSm, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSm_Int, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSr, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUB231SSr_Int, X86_INS_VFMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDYm, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDYr, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ128m, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ128mb, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ128mbk, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ128mbkz, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ128mk, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ128mkz, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ128r, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ128rk, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ128rkz, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ256m, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ256mb, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ256mbk, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ256mbkz, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ256mk, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ256mkz, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ256r, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ256rk, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZ256rkz, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZm, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZmb, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZmbk, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZmbkz, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZmk, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZmkz, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZr, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZrb, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZrbk, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZrbkz, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZrk, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDZrkz, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDm, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PDr, X86_INS_VFMSUBADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSYm, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSYr, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ128m, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ128mb, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ128mbk, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ128mbkz, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ128mk, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ128mkz, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ128r, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ128rk, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ128rkz, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ256m, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ256mb, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ256mbk, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ256mbkz, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ256mk, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ256mkz, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ256r, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ256rk, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZ256rkz, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZm, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZmb, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZmbk, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZmbkz, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZmk, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZmkz, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZr, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZrb, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZrbk, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZrbkz, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZrk, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSZrkz, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSm, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD132PSr, X86_INS_VFMSUBADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDYm, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDYr, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ128m, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ128mb, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ128mbk, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ128mbkz, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ128mk, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ128mkz, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ128r, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ128rk, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ128rkz, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ256m, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ256mb, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ256mbk, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ256mbkz, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ256mk, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ256mkz, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ256r, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ256rk, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZ256rkz, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZm, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZmb, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZmbk, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZmbkz, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZmk, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZmkz, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZr, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZrb, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZrbk, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZrbkz, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZrk, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDZrkz, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDm, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PDr, X86_INS_VFMSUBADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSYm, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSYr, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ128m, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ128mb, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ128mbk, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ128mbkz, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ128mk, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ128mkz, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ128r, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ128rk, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ128rkz, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ256m, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ256mb, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ256mbk, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ256mbkz, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ256mk, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ256mkz, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ256r, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ256rk, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZ256rkz, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZm, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZmb, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZmbk, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZmbkz, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZmk, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZmkz, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZr, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZrb, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZrbk, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZrbkz, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZrk, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSZrkz, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSm, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD213PSr, X86_INS_VFMSUBADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDYm, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDYr, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ128m, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ128mb, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ128mbk, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ128mbkz, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ128mk, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ128mkz, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ128r, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ128rk, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ128rkz, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ256m, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ256mb, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ256mbk, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ256mbkz, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ256mk, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ256mkz, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ256r, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ256rk, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZ256rkz, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZm, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZmb, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZmbk, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZmbkz, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZmk, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZmkz, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZr, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZrb, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZrbk, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZrbkz, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZrk, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDZrkz, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDm, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PDr, X86_INS_VFMSUBADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSYm, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSYr, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ128m, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ128mb, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ128mbk, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ128mbkz, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ128mk, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ128mkz, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ128r, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ128rk, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ128rkz, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ256m, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ256mb, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ256mbk, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ256mbkz, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ256mk, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ256mkz, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ256r, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ256rk, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZ256rkz, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZm, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZmb, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZmbk, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZmbkz, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZmk, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZmkz, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZr, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZrb, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZrbk, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZrbkz, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZrk, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSZrkz, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSm, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADD231PSr, X86_INS_VFMSUBADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPD4Ymr, X86_INS_VFMSUBADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPD4Yrm, X86_INS_VFMSUBADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPD4Yrr, X86_INS_VFMSUBADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPD4Yrr_REV, X86_INS_VFMSUBADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPD4mr, X86_INS_VFMSUBADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPD4rm, X86_INS_VFMSUBADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPD4rr, X86_INS_VFMSUBADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPD4rr_REV, X86_INS_VFMSUBADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPS4Ymr, X86_INS_VFMSUBADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPS4Yrm, X86_INS_VFMSUBADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPS4Yrr, X86_INS_VFMSUBADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPS4Yrr_REV, X86_INS_VFMSUBADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPS4mr, X86_INS_VFMSUBADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPS4rm, X86_INS_VFMSUBADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPS4rr, X86_INS_VFMSUBADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBADDPS4rr_REV, X86_INS_VFMSUBADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPD4Ymr, X86_INS_VFMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPD4Yrm, X86_INS_VFMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPD4Yrr, X86_INS_VFMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPD4Yrr_REV, X86_INS_VFMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPD4mr, X86_INS_VFMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPD4rm, X86_INS_VFMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPD4rr, X86_INS_VFMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPD4rr_REV, X86_INS_VFMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPS4Ymr, X86_INS_VFMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPS4Yrm, X86_INS_VFMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPS4Yrr, X86_INS_VFMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPS4Yrr_REV, X86_INS_VFMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPS4mr, X86_INS_VFMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPS4rm, X86_INS_VFMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPS4rr, X86_INS_VFMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBPS4rr_REV, X86_INS_VFMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSD4mr, X86_INS_VFMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSD4mr_Int, X86_INS_VFMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSD4rm, X86_INS_VFMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSD4rm_Int, X86_INS_VFMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSD4rr, X86_INS_VFMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSD4rr_Int, X86_INS_VFMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSD4rr_Int_REV, X86_INS_VFMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSD4rr_REV, X86_INS_VFMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSS4mr, X86_INS_VFMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSS4mr_Int, X86_INS_VFMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSS4rm, X86_INS_VFMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSS4rm_Int, X86_INS_VFMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSS4rr, X86_INS_VFMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSS4rr_Int, X86_INS_VFMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSS4rr_Int_REV, X86_INS_VFMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFMSUBSS4rr_REV, X86_INS_VFMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDYm, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDYr, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ128m, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ128mb, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ128mbk, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ128mbkz, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ128mk, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ128mkz, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ128r, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ128rk, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ128rkz, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ256m, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ256mb, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ256mbk, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ256mbkz, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ256mk, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ256mkz, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ256r, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ256rk, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZ256rkz, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZm, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZmb, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZmbk, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZmbkz, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZmk, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZmkz, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZr, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZrb, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZrbk, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZrbkz, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZrk, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDZrkz, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDm, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PDr, X86_INS_VFNMADD132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSYm, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSYr, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ128m, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ128mb, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ128mbk, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ128mbkz, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ128mk, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ128mkz, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ128r, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ128rk, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ128rkz, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ256m, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ256mb, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ256mbk, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ256mbkz, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ256mk, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ256mkz, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ256r, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ256rk, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZ256rkz, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZm, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZmb, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZmbk, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZmbkz, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZmk, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZmkz, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZr, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZrb, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZrbk, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZrbkz, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZrk, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSZrkz, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSm, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132PSr, X86_INS_VFNMADD132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDZm, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDZm_Int, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDZm_Intk, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDZm_Intkz, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDZr, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDZr_Int, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDZr_Intk, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDZr_Intkz, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDZrb, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDZrb_Int, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDZrb_Intk, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDZrb_Intkz, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDm, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDm_Int, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDr, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SDr_Int, X86_INS_VFNMADD132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSZm, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSZm_Int, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSZm_Intk, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSZm_Intkz, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSZr, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSZr_Int, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSZr_Intk, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSZr_Intkz, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSZrb, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSZrb_Int, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSZrb_Intk, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSZrb_Intkz, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSm, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSm_Int, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSr, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD132SSr_Int, X86_INS_VFNMADD132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDYm, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDYr, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ128m, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ128mb, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ128mbk, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ128mbkz, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ128mk, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ128mkz, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ128r, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ128rk, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ128rkz, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ256m, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ256mb, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ256mbk, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ256mbkz, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ256mk, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ256mkz, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ256r, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ256rk, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZ256rkz, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZm, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZmb, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZmbk, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZmbkz, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZmk, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZmkz, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZr, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZrb, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZrbk, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZrbkz, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZrk, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDZrkz, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDm, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PDr, X86_INS_VFNMADD213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSYm, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSYr, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ128m, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ128mb, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ128mbk, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ128mbkz, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ128mk, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ128mkz, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ128r, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ128rk, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ128rkz, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ256m, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ256mb, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ256mbk, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ256mbkz, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ256mk, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ256mkz, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ256r, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ256rk, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZ256rkz, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZm, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZmb, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZmbk, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZmbkz, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZmk, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZmkz, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZr, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZrb, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZrbk, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZrbkz, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZrk, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSZrkz, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSm, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213PSr, X86_INS_VFNMADD213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDZm, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDZm_Int, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDZm_Intk, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDZm_Intkz, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDZr, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDZr_Int, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDZr_Intk, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDZr_Intkz, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDZrb, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDZrb_Int, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDZrb_Intk, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDZrb_Intkz, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDm, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDm_Int, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDr, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SDr_Int, X86_INS_VFNMADD213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSZm, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSZm_Int, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSZm_Intk, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSZm_Intkz, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSZr, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSZr_Int, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSZr_Intk, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSZr_Intkz, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSZrb, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSZrb_Int, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSZrb_Intk, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSZrb_Intkz, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSm, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSm_Int, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSr, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD213SSr_Int, X86_INS_VFNMADD213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDYm, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDYr, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ128m, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ128mb, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ128mbk, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ128mbkz, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ128mk, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ128mkz, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ128r, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ128rk, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ128rkz, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ256m, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ256mb, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ256mbk, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ256mbkz, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ256mk, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ256mkz, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ256r, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ256rk, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZ256rkz, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZm, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZmb, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZmbk, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZmbkz, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZmk, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZmkz, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZr, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZrb, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZrbk, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZrbkz, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZrk, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDZrkz, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDm, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PDr, X86_INS_VFNMADD231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSYm, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSYr, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ128m, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ128mb, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ128mbk, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ128mbkz, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ128mk, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ128mkz, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ128r, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ128rk, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ128rkz, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ256m, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ256mb, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ256mbk, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ256mbkz, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ256mk, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ256mkz, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ256r, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ256rk, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZ256rkz, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZm, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZmb, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZmbk, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZmbkz, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZmk, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZmkz, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZr, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZrb, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZrbk, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZrbkz, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZrk, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSZrkz, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSm, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231PSr, X86_INS_VFNMADD231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDZm, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDZm_Int, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDZm_Intk, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDZm_Intkz, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDZr, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDZr_Int, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDZr_Intk, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDZr_Intkz, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDZrb, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDZrb_Int, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDZrb_Intk, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDZrb_Intkz, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDm, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDm_Int, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDr, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SDr_Int, X86_INS_VFNMADD231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSZm, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSZm_Int, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSZm_Intk, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSZm_Intkz, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSZr, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSZr_Int, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSZr_Intk, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSZr_Intkz, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSZrb, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSZrb_Int, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSZrb_Intk, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSZrb_Intkz, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSm, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSm_Int, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSr, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADD231SSr_Int, X86_INS_VFNMADD231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPD4Ymr, X86_INS_VFNMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPD4Yrm, X86_INS_VFNMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPD4Yrr, X86_INS_VFNMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPD4Yrr_REV, X86_INS_VFNMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPD4mr, X86_INS_VFNMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPD4rm, X86_INS_VFNMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPD4rr, X86_INS_VFNMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPD4rr_REV, X86_INS_VFNMADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPS4Ymr, X86_INS_VFNMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPS4Yrm, X86_INS_VFNMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPS4Yrr, X86_INS_VFNMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPS4Yrr_REV, X86_INS_VFNMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPS4mr, X86_INS_VFNMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPS4rm, X86_INS_VFNMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPS4rr, X86_INS_VFNMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDPS4rr_REV, X86_INS_VFNMADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSD4mr, X86_INS_VFNMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSD4mr_Int, X86_INS_VFNMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSD4rm, X86_INS_VFNMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSD4rm_Int, X86_INS_VFNMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSD4rr, X86_INS_VFNMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSD4rr_Int, X86_INS_VFNMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSD4rr_Int_REV, X86_INS_VFNMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSD4rr_REV, X86_INS_VFNMADDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSS4mr, X86_INS_VFNMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSS4mr_Int, X86_INS_VFNMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSS4rm, X86_INS_VFNMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSS4rm_Int, X86_INS_VFNMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSS4rr, X86_INS_VFNMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSS4rr_Int, X86_INS_VFNMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSS4rr_Int_REV, X86_INS_VFNMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMADDSS4rr_REV, X86_INS_VFNMADDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDYm, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDYr, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ128m, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ128mb, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ128mbk, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ128mbkz, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ128mk, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ128mkz, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ128r, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ128rk, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ128rkz, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ256m, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ256mb, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ256mbk, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ256mbkz, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ256mk, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ256mkz, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ256r, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ256rk, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZ256rkz, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZm, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZmb, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZmbk, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZmbkz, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZmk, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZmkz, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZr, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZrb, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZrbk, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZrbkz, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZrk, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDZrkz, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDm, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PDr, X86_INS_VFNMSUB132PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSYm, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSYr, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ128m, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ128mb, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ128mbk, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ128mbkz, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ128mk, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ128mkz, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ128r, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ128rk, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ128rkz, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ256m, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ256mb, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ256mbk, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ256mbkz, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ256mk, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ256mkz, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ256r, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ256rk, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZ256rkz, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZm, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZmb, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZmbk, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZmbkz, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZmk, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZmkz, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZr, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZrb, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZrbk, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZrbkz, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZrk, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSZrkz, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSm, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132PSr, X86_INS_VFNMSUB132PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDZm, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDZm_Int, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDZm_Intk, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDZm_Intkz, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDZr, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDZr_Int, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDZr_Intk, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDZr_Intkz, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDZrb, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDZrb_Int, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDZrb_Intk, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDZrb_Intkz, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDm, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDm_Int, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDr, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SDr_Int, X86_INS_VFNMSUB132SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSZm, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSZm_Int, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSZm_Intk, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSZm_Intkz, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSZr, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSZr_Int, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSZr_Intk, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSZr_Intkz, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSZrb, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSZrb_Int, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSZrb_Intk, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSZrb_Intkz, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSm, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSm_Int, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSr, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB132SSr_Int, X86_INS_VFNMSUB132SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDYm, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDYr, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ128m, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ128mb, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ128mbk, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ128mbkz, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ128mk, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ128mkz, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ128r, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ128rk, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ128rkz, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ256m, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ256mb, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ256mbk, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ256mbkz, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ256mk, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ256mkz, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ256r, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ256rk, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZ256rkz, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZm, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZmb, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZmbk, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZmbkz, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZmk, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZmkz, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZr, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZrb, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZrbk, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZrbkz, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZrk, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDZrkz, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDm, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PDr, X86_INS_VFNMSUB213PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSYm, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSYr, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ128m, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ128mb, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ128mbk, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ128mbkz, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ128mk, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ128mkz, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ128r, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ128rk, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ128rkz, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ256m, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ256mb, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ256mbk, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ256mbkz, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ256mk, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ256mkz, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ256r, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ256rk, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZ256rkz, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZm, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZmb, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZmbk, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZmbkz, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZmk, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZmkz, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZr, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZrb, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZrbk, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZrbkz, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZrk, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSZrkz, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSm, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213PSr, X86_INS_VFNMSUB213PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDZm, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDZm_Int, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDZm_Intk, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDZm_Intkz, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDZr, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDZr_Int, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDZr_Intk, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDZr_Intkz, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDZrb, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDZrb_Int, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDZrb_Intk, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDZrb_Intkz, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDm, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDm_Int, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDr, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SDr_Int, X86_INS_VFNMSUB213SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSZm, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSZm_Int, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSZm_Intk, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSZm_Intkz, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSZr, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSZr_Int, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSZr_Intk, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSZr_Intkz, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSZrb, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSZrb_Int, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSZrb_Intk, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSZrb_Intkz, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSm, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSm_Int, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSr, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB213SSr_Int, X86_INS_VFNMSUB213SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDYm, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDYr, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ128m, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ128mb, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ128mbk, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ128mbkz, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ128mk, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ128mkz, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ128r, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ128rk, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ128rkz, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ256m, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ256mb, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ256mbk, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ256mbkz, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ256mk, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ256mkz, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ256r, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ256rk, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZ256rkz, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZm, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZmb, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZmbk, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZmbkz, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZmk, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZmkz, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZr, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZrb, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZrbk, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZrbkz, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZrk, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDZrkz, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDm, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PDr, X86_INS_VFNMSUB231PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSYm, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSYr, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ128m, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ128mb, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ128mbk, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ128mbkz, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ128mk, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ128mkz, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ128r, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ128rk, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ128rkz, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ256m, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ256mb, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ256mbk, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ256mbkz, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ256mk, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ256mkz, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ256r, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ256rk, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZ256rkz, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZm, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZmb, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZmbk, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZmbkz, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZmk, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZmkz, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZr, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZrb, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZrbk, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZrbkz, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZrk, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSZrkz, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSm, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231PSr, X86_INS_VFNMSUB231PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDZm, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDZm_Int, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDZm_Intk, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDZm_Intkz, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDZr, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDZr_Int, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDZr_Intk, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDZr_Intkz, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDZrb, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDZrb_Int, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDZrb_Intk, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDZrb_Intkz, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDm, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDm_Int, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDr, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SDr_Int, X86_INS_VFNMSUB231SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSZm, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSZm_Int, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSZm_Intk, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSZm_Intkz, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSZr, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSZr_Int, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSZr_Intk, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSZr_Intkz, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSZrb, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSZrb_Int, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSZrb_Intk, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSZrb_Intkz, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSm, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSm_Int, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSr, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUB231SSr_Int, X86_INS_VFNMSUB231SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPD4Ymr, X86_INS_VFNMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPD4Yrm, X86_INS_VFNMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPD4Yrr, X86_INS_VFNMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPD4Yrr_REV, X86_INS_VFNMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPD4mr, X86_INS_VFNMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPD4rm, X86_INS_VFNMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPD4rr, X86_INS_VFNMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPD4rr_REV, X86_INS_VFNMSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPS4Ymr, X86_INS_VFNMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPS4Yrm, X86_INS_VFNMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPS4Yrr, X86_INS_VFNMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPS4Yrr_REV, X86_INS_VFNMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPS4mr, X86_INS_VFNMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPS4rm, X86_INS_VFNMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPS4rr, X86_INS_VFNMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBPS4rr_REV, X86_INS_VFNMSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSD4mr, X86_INS_VFNMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSD4mr_Int, X86_INS_VFNMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSD4rm, X86_INS_VFNMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSD4rm_Int, X86_INS_VFNMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSD4rr, X86_INS_VFNMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSD4rr_Int, X86_INS_VFNMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSD4rr_Int_REV, X86_INS_VFNMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSD4rr_REV, X86_INS_VFNMSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSS4mr, X86_INS_VFNMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSS4mr_Int, X86_INS_VFNMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSS4rm, X86_INS_VFNMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSS4rm_Int, X86_INS_VFNMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSS4rr, X86_INS_VFNMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSS4rr_Int, X86_INS_VFNMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSS4rr_Int_REV, X86_INS_VFNMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFNMSUBSS4rr_REV, X86_INS_VFNMSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZ128rm, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZ128rmb, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZ128rmbk, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZ128rmk, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZ128rr, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZ128rrk, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZ256rm, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZ256rmb, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZ256rmbk, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZ256rmk, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZ256rr, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZ256rrk, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZrm, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZrmb, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZrmbk, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZrmk, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZrr, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPDZrrk, X86_INS_VFPCLASSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZ128rm, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZ128rmb, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZ128rmbk, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZ128rmk, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZ128rr, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZ128rrk, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZ256rm, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZ256rmb, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZ256rmbk, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZ256rmk, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZ256rr, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZ256rrk, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZrm, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZrmb, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZrmbk, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZrmk, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZrr, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSPSZrrk, X86_INS_VFPCLASSPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSSDZrm, X86_INS_VFPCLASSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSSDZrmk, X86_INS_VFPCLASSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSSDZrr, X86_INS_VFPCLASSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSSDZrrk, X86_INS_VFPCLASSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSSSZrm, X86_INS_VFPCLASSSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSSSZrmk, X86_INS_VFPCLASSSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSSSZrr, X86_INS_VFPCLASSSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFPCLASSSSZrrk, X86_INS_VFPCLASSSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFRCZPDYrm, X86_INS_VFRCZPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFRCZPDYrr, X86_INS_VFRCZPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFRCZPDrm, X86_INS_VFRCZPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VFRCZPDrr, X86_INS_VFRCZPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VFRCZPSYrm, X86_INS_VFRCZPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFRCZPSYrr, X86_INS_VFRCZPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VFRCZPSrm, X86_INS_VFRCZPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VFRCZPSrr, X86_INS_VFRCZPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VFRCZSDrm, X86_INS_VFRCZSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VFRCZSDrr, X86_INS_VFRCZSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VFRCZSSrm, X86_INS_VFRCZSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VFRCZSSrr, X86_INS_VFRCZSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERDPDYrm, X86_INS_VGATHERDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERDPDZ128rm, X86_INS_VGATHERDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERDPDZ256rm, X86_INS_VGATHERDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERDPDZrm, X86_INS_VGATHERDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERDPDrm, X86_INS_VGATHERDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERDPSYrm, X86_INS_VGATHERDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERDPSZ128rm, X86_INS_VGATHERDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERDPSZ256rm, X86_INS_VGATHERDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERDPSZrm, X86_INS_VGATHERDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERDPSrm, X86_INS_VGATHERDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERPF0DPDm, X86_INS_VGATHERPF0DPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERPF0DPSm, X86_INS_VGATHERPF0DPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERPF0QPDm, X86_INS_VGATHERPF0QPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERPF0QPSm, X86_INS_VGATHERPF0QPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERPF1DPDm, X86_INS_VGATHERPF1DPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERPF1DPSm, X86_INS_VGATHERPF1DPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERPF1QPDm, X86_INS_VGATHERPF1QPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERPF1QPSm, X86_INS_VGATHERPF1QPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERQPDYrm, X86_INS_VGATHERQPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERQPDZ128rm, X86_INS_VGATHERQPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERQPDZ256rm, X86_INS_VGATHERQPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERQPDZrm, X86_INS_VGATHERQPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERQPDrm, X86_INS_VGATHERQPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERQPSYrm, X86_INS_VGATHERQPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERQPSZ128rm, X86_INS_VGATHERQPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERQPSZ256rm, X86_INS_VGATHERQPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERQPSZrm, X86_INS_VGATHERQPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VGATHERQPSrm, X86_INS_VGATHERQPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ128m, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ128mb, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ128mbk, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ128mbkz, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ128mk, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ128mkz, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ128r, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ128rk, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ128rkz, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ256m, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ256mb, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ256mbk, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ256mbkz, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ256mk, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ256mkz, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ256r, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ256rk, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZ256rkz, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZm, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZmb, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZmbk, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZmbkz, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZmk, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZmkz, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZr, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZrb, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZrbk, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZrbkz, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZrk, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPDZrkz, X86_INS_VGETEXPPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ128m, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ128mb, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ128mbk, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ128mbkz, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ128mk, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ128mkz, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ128r, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ128rk, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ128rkz, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ256m, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ256mb, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ256mbk, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ256mbkz, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ256mk, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ256mkz, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ256r, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ256rk, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZ256rkz, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZm, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZmb, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZmbk, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZmbkz, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZmk, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZmkz, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZr, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZrb, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZrbk, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZrbkz, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZrk, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPPSZrkz, X86_INS_VGETEXPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSDZm, X86_INS_VGETEXPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSDZmk, X86_INS_VGETEXPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSDZmkz, X86_INS_VGETEXPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSDZr, X86_INS_VGETEXPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSDZrb, X86_INS_VGETEXPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSDZrbk, X86_INS_VGETEXPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSDZrbkz, X86_INS_VGETEXPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSDZrk, X86_INS_VGETEXPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSDZrkz, X86_INS_VGETEXPSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSSZm, X86_INS_VGETEXPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSSZmk, X86_INS_VGETEXPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSSZmkz, X86_INS_VGETEXPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSSZr, X86_INS_VGETEXPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSSZrb, X86_INS_VGETEXPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSSZrbk, X86_INS_VGETEXPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSSZrbkz, X86_INS_VGETEXPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSSZrk, X86_INS_VGETEXPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETEXPSSZrkz, X86_INS_VGETEXPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ128rmbi, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ128rmbik, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ128rmbikz, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ128rmi, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ128rmik, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ128rmikz, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ128rri, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ128rrik, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ128rrikz, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ256rmbi, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ256rmbik, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ256rmbikz, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ256rmi, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ256rmik, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ256rmikz, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ256rri, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ256rrik, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZ256rrikz, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZrmbi, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZrmbik, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZrmbikz, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZrmi, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZrmik, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZrmikz, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZrri, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZrrib, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZrribk, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZrribkz, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZrrik, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPDZrrikz, X86_INS_VGETMANTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ128rmbi, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ128rmbik, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ128rmbikz, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ128rmi, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ128rmik, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ128rmikz, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ128rri, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ128rrik, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ128rrikz, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ256rmbi, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ256rmbik, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ256rmbikz, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ256rmi, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ256rmik, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ256rmikz, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ256rri, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ256rrik, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZ256rrikz, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZrmbi, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZrmbik, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZrmbikz, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZrmi, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZrmik, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZrmikz, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZrri, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZrrib, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZrribk, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZrribkz, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZrrik, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTPSZrrikz, X86_INS_VGETMANTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSDZrmi, X86_INS_VGETMANTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSDZrmik, X86_INS_VGETMANTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSDZrmikz, X86_INS_VGETMANTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSDZrri, X86_INS_VGETMANTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSDZrrib, X86_INS_VGETMANTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSDZrribk, X86_INS_VGETMANTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSDZrribkz, X86_INS_VGETMANTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSDZrrik, X86_INS_VGETMANTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSDZrrikz, X86_INS_VGETMANTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSSZrmi, X86_INS_VGETMANTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSSZrmik, X86_INS_VGETMANTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSSZrmikz, X86_INS_VGETMANTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSSZrri, X86_INS_VGETMANTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSSZrrib, X86_INS_VGETMANTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSSZrribk, X86_INS_VGETMANTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSSZrribkz, X86_INS_VGETMANTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSSZrrik, X86_INS_VGETMANTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGETMANTSSZrrikz, X86_INS_VGETMANTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBYrmi, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBYrri, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ128rmbi, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ128rmbik, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ128rmbikz, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ128rmi, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ128rmik, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ128rmikz, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ128rri, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ128rrik, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ128rrikz, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ256rmbi, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ256rmbik, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ256rmbikz, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ256rmi, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ256rmik, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ256rmikz, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ256rri, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ256rrik, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZ256rrikz, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZrmbi, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZrmbik, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZrmbikz, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZrmi, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZrmik, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZrmikz, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZrri, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZrrik, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBZrrikz, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBrmi, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEINVQBrri, X86_INS_VGF2P8AFFINEINVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBYrmi, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBYrri, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ128rmbi, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ128rmbik, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ128rmbikz, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ128rmi, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ128rmik, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ128rmikz, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ128rri, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ128rrik, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ128rrikz, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ256rmbi, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ256rmbik, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ256rmbikz, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ256rmi, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ256rmik, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ256rmikz, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ256rri, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ256rrik, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZ256rrikz, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZrmbi, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZrmbik, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZrmbikz, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZrmi, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZrmik, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZrmikz, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZrri, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZrrik, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBZrrikz, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBrmi, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8AFFINEQBrri, X86_INS_VGF2P8AFFINEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBYrm, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBYrr, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZ128rm, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZ128rmk, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZ128rmkz, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZ128rr, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZ128rrk, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZ128rrkz, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZ256rm, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZ256rmk, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZ256rmkz, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZ256rr, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZ256rrk, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZ256rrkz, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZrm, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZrmk, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZrmkz, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZrr, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZrrk, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBZrrkz, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBrm, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VGF2P8MULBrr, X86_INS_VGF2P8MULB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VHADDPDYrm, X86_INS_VHADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHADDPDYrr, X86_INS_VHADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHADDPDrm, X86_INS_VHADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHADDPDrr, X86_INS_VHADDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHADDPSYrm, X86_INS_VHADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHADDPSYrr, X86_INS_VHADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHADDPSrm, X86_INS_VHADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHADDPSrr, X86_INS_VHADDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHSUBPDYrm, X86_INS_VHSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHSUBPDYrr, X86_INS_VHSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHSUBPDrm, X86_INS_VHSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHSUBPDrr, X86_INS_VHSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHSUBPSYrm, X86_INS_VHSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHSUBPSYrr, X86_INS_VHSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHSUBPSrm, X86_INS_VHSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VHSUBPSrr, X86_INS_VHSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF128rm, X86_INS_VINSERTF128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF128rr, X86_INS_VINSERTF128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x4Z256rm, X86_INS_VINSERTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x4Z256rmk, X86_INS_VINSERTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x4Z256rmkz, X86_INS_VINSERTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x4Z256rr, X86_INS_VINSERTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x4Z256rrk, X86_INS_VINSERTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x4Z256rrkz, X86_INS_VINSERTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x4Zrm, X86_INS_VINSERTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x4Zrmk, X86_INS_VINSERTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x4Zrmkz, X86_INS_VINSERTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x4Zrr, X86_INS_VINSERTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x4Zrrk, X86_INS_VINSERTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x4Zrrkz, X86_INS_VINSERTF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x8Zrm, X86_INS_VINSERTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x8Zrmk, X86_INS_VINSERTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x8Zrmkz, X86_INS_VINSERTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x8Zrr, X86_INS_VINSERTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x8Zrrk, X86_INS_VINSERTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF32x8Zrrkz, X86_INS_VINSERTF32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x2Z256rm, X86_INS_VINSERTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x2Z256rmk, X86_INS_VINSERTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x2Z256rmkz, X86_INS_VINSERTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x2Z256rr, X86_INS_VINSERTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x2Z256rrk, X86_INS_VINSERTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x2Z256rrkz, X86_INS_VINSERTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x2Zrm, X86_INS_VINSERTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x2Zrmk, X86_INS_VINSERTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x2Zrmkz, X86_INS_VINSERTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x2Zrr, X86_INS_VINSERTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x2Zrrk, X86_INS_VINSERTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x2Zrrkz, X86_INS_VINSERTF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x4Zrm, X86_INS_VINSERTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x4Zrmk, X86_INS_VINSERTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x4Zrmkz, X86_INS_VINSERTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x4Zrr, X86_INS_VINSERTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x4Zrrk, X86_INS_VINSERTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTF64x4Zrrkz, X86_INS_VINSERTF64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI128rm, X86_INS_VINSERTI128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI128rr, X86_INS_VINSERTI128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x4Z256rm, X86_INS_VINSERTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x4Z256rmk, X86_INS_VINSERTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x4Z256rmkz, X86_INS_VINSERTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x4Z256rr, X86_INS_VINSERTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x4Z256rrk, X86_INS_VINSERTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x4Z256rrkz, X86_INS_VINSERTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x4Zrm, X86_INS_VINSERTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x4Zrmk, X86_INS_VINSERTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x4Zrmkz, X86_INS_VINSERTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x4Zrr, X86_INS_VINSERTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x4Zrrk, X86_INS_VINSERTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x4Zrrkz, X86_INS_VINSERTI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x8Zrm, X86_INS_VINSERTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x8Zrmk, X86_INS_VINSERTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x8Zrmkz, X86_INS_VINSERTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x8Zrr, X86_INS_VINSERTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x8Zrrk, X86_INS_VINSERTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI32x8Zrrkz, X86_INS_VINSERTI32X8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x2Z256rm, X86_INS_VINSERTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x2Z256rmk, X86_INS_VINSERTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x2Z256rmkz, X86_INS_VINSERTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x2Z256rr, X86_INS_VINSERTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x2Z256rrk, X86_INS_VINSERTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x2Z256rrkz, X86_INS_VINSERTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x2Zrm, X86_INS_VINSERTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x2Zrmk, X86_INS_VINSERTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x2Zrmkz, X86_INS_VINSERTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x2Zrr, X86_INS_VINSERTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x2Zrrk, X86_INS_VINSERTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x2Zrrkz, X86_INS_VINSERTI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x4Zrm, X86_INS_VINSERTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x4Zrmk, X86_INS_VINSERTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x4Zrmkz, X86_INS_VINSERTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x4Zrr, X86_INS_VINSERTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x4Zrrk, X86_INS_VINSERTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTI64x4Zrrkz, X86_INS_VINSERTI64X4, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTPSZrm, X86_INS_VINSERTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTPSZrr, X86_INS_VINSERTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTPSrm, X86_INS_VINSERTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VINSERTPSrr, X86_INS_VINSERTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VLDDQUYrm, X86_INS_VLDDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VLDDQUrm, X86_INS_VLDDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VLDMXCSR, X86_INS_VLDMXCSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMASKMOVDQU, X86_INS_VMASKMOVDQU, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMASKMOVDQU64, X86_INS_VMASKMOVDQU, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDI, 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMASKMOVPDYmr, X86_INS_VMASKMOVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMASKMOVPDYrm, X86_INS_VMASKMOVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMASKMOVPDmr, X86_INS_VMASKMOVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMASKMOVPDrm, X86_INS_VMASKMOVPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMASKMOVPSYmr, X86_INS_VMASKMOVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMASKMOVPSYrm, X86_INS_VMASKMOVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMASKMOVPSmr, X86_INS_VMASKMOVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMASKMOVPSrm, X86_INS_VMASKMOVPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDYrm, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDYrr, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ128rm, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ128rmb, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ128rmbk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ128rmbkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ128rmk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ128rmkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ128rr, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ128rrk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ128rrkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ256rm, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ256rmb, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ256rmbk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ256rmbkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ256rmk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ256rmkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ256rr, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ256rrk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZ256rrkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZrm, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZrmb, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZrmbk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZrmbkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZrmk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZrmkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZrr, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZrrk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDZrrkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDrm, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPDrr, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSYrm, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSYrr, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ128rm, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ128rmb, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ128rmbk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ128rmbkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ128rmk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ128rmkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ128rr, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ128rrk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ128rrkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ256rm, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ256rmb, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ256rmbk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ256rmbkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ256rmk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ256rmkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ256rr, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ256rrk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZ256rrkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZrm, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZrmb, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZrmbk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZrmbkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZrmk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZrmkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZrr, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZrrk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSZrrkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSrm, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCPSrr, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCSDZrm, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCSDZrr, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCSDrm, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCSDrr, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCSSZrm, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCSSZrr, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCSSrm, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXCSSrr, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDYrm, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDYrr, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ128rm, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ128rmb, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ128rmbk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ128rmbkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ128rmk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ128rmkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ128rr, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ128rrk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ128rrkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ256rm, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ256rmb, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ256rmbk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ256rmbkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ256rmk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ256rmkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ256rr, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ256rrk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZ256rrkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZrm, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZrmb, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZrmbk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZrmbkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZrmk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZrmkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZrr, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZrrb, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZrrbk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZrrbkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZrrk, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDZrrkz, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDrm, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPDrr, X86_INS_VMAXPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSYrm, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSYrr, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ128rm, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ128rmb, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ128rmbk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ128rmbkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ128rmk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ128rmkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ128rr, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ128rrk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ128rrkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ256rm, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ256rmb, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ256rmbk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ256rmbkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ256rmk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ256rmkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ256rr, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ256rrk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZ256rrkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZrm, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZrmb, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZrmbk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZrmbkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZrmk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZrmkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZrr, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZrrb, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZrrbk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZrrbkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZrrk, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSZrrkz, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSrm, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXPSrr, X86_INS_VMAXPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDZrm, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDZrm_Int, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDZrm_Intk, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDZrm_Intkz, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDZrr, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDZrr_Int, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDZrr_Intk, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDZrr_Intkz, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDZrrb_Int, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDZrrb_Intk, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDZrrb_Intkz, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDrm, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDrm_Int, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDrr, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSDrr_Int, X86_INS_VMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSZrm, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSZrm_Int, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSZrm_Intk, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSZrm_Intkz, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSZrr, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSZrr_Int, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSZrr_Intk, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSZrr_Intkz, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSZrrb_Int, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSZrrb_Intk, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSZrrb_Intkz, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSrm, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSrm_Int, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSrr, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMAXSSrr_Int, X86_INS_VMAXSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMCALL, X86_INS_VMCALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMCLEARm, X86_INS_VMCLEAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMFUNC, X86_INS_VMFUNC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDYrm, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDYrr, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ128rm, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ128rmb, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ128rmbk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ128rmbkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ128rmk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ128rmkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ128rr, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ128rrk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ128rrkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ256rm, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ256rmb, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ256rmbk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ256rmbkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ256rmk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ256rmkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ256rr, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ256rrk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZ256rrkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZrm, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZrmb, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZrmbk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZrmbkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZrmk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZrmkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZrr, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZrrk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDZrrkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDrm, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPDrr, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSYrm, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSYrr, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ128rm, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ128rmb, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ128rmbk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ128rmbkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ128rmk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ128rmkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ128rr, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ128rrk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ128rrkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ256rm, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ256rmb, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ256rmbk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ256rmbkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ256rmk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ256rmkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ256rr, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ256rrk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZ256rrkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZrm, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZrmb, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZrmbk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZrmbkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZrmk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZrmkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZrr, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZrrk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSZrrkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSrm, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCPSrr, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCSDZrm, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCSDZrr, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCSDrm, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCSDrr, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCSSZrm, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCSSZrr, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCSSrm, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINCSSrr, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDYrm, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDYrr, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ128rm, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ128rmb, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ128rmbk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ128rmbkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ128rmk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ128rmkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ128rr, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ128rrk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ128rrkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ256rm, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ256rmb, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ256rmbk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ256rmbkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ256rmk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ256rmkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ256rr, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ256rrk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZ256rrkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZrm, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZrmb, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZrmbk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZrmbkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZrmk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZrmkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZrr, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZrrb, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZrrbk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZrrbkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZrrk, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDZrrkz, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDrm, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPDrr, X86_INS_VMINPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSYrm, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSYrr, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ128rm, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ128rmb, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ128rmbk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ128rmbkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ128rmk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ128rmkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ128rr, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ128rrk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ128rrkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ256rm, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ256rmb, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ256rmbk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ256rmbkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ256rmk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ256rmkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ256rr, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ256rrk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZ256rrkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZrm, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZrmb, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZrmbk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZrmbkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZrmk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZrmkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZrr, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZrrb, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZrrbk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZrrbkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZrrk, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSZrrkz, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSrm, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINPSrr, X86_INS_VMINPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDZrm, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDZrm_Int, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDZrm_Intk, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDZrm_Intkz, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDZrr, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDZrr_Int, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDZrr_Intk, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDZrr_Intkz, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDZrrb_Int, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDZrrb_Intk, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDZrrb_Intkz, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDrm, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDrm_Int, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDrr, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSDrr_Int, X86_INS_VMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSZrm, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSZrm_Int, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSZrm_Intk, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSZrm_Intkz, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSZrr, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSZrr_Int, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSZrr_Intk, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSZrr_Intkz, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSZrrb_Int, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSZrrb_Intk, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSZrrb_Intkz, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSrm, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSrm_Int, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSrr, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMINSSrr_Int, X86_INS_VMINSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMLAUNCH, X86_INS_VMLAUNCH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMLOAD32, X86_INS_VMLOAD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMLOAD64, X86_INS_VMLOAD, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMMCALL, X86_INS_VMMCALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOV64toPQIZrm, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOV64toPQIZrr, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOV64toPQIrm, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOV64toPQIrr, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOV64toSDZrm, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOV64toSDZrr, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOV64toSDrm, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOV64toSDrr, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDYmr, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDYrm, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDYrr, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDYrr_REV, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ128mr, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ128mrk, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ128rm, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ128rmk, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ128rmkz, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ128rr, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ128rr_REV, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ128rrk, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ128rrk_REV, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ128rrkz, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ128rrkz_REV, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ256mr, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ256mrk, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ256rm, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ256rmk, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ256rmkz, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ256rr, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ256rr_REV, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ256rrk, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ256rrk_REV, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ256rrkz, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZ256rrkz_REV, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZmr, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZmrk, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZrm, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZrmk, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZrmkz, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZrr, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZrr_REV, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZrrk, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZrrk_REV, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZrrkz, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDZrrkz_REV, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDmr, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDrm, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDrr, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPDrr_REV, X86_INS_VMOVAPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSYmr, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSYrm, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSYrr, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSYrr_REV, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ128mr, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ128mrk, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ128rm, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ128rmk, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ128rmkz, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ128rr, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ128rr_REV, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ128rrk, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ128rrk_REV, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ128rrkz, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ128rrkz_REV, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ256mr, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ256mrk, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ256rm, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ256rmk, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ256rmkz, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ256rr, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ256rr_REV, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ256rrk, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ256rrk_REV, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ256rrkz, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZ256rrkz_REV, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZmr, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZmrk, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZrm, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZrmk, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZrmkz, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZrr, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZrr_REV, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZrrk, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZrrk_REV, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZrrkz, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSZrrkz_REV, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSmr, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSrm, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSrr, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVAPSrr_REV, X86_INS_VMOVAPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPYrm, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPYrr, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZ128rm, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZ128rmk, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZ128rmkz, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZ128rr, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZ128rrk, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZ128rrkz, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZ256rm, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZ256rmk, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZ256rmkz, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZ256rr, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZ256rrk, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZ256rrkz, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZrm, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZrmk, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZrmkz, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZrr, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZrrk, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPZrrkz, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPrm, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDDUPrr, X86_INS_VMOVDDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDI2PDIZrm, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDI2PDIZrr, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDI2PDIrm, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDI2PDIrr, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDI2SSZrm, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDI2SSZrr, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDI2SSrm, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDI2SSrr, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z128mr, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z128mrk, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z128rm, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z128rmk, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z128rmkz, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z128rr, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z128rr_REV, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z128rrk, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z128rrk_REV, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z128rrkz, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z128rrkz_REV, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z256mr, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z256mrk, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z256rm, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z256rmk, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z256rmkz, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z256rr, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z256rr_REV, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z256rrk, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z256rrk_REV, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z256rrkz, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Z256rrkz_REV, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Zmr, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Zmrk, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Zrm, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Zrmk, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Zrmkz, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Zrr, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Zrr_REV, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Zrrk, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Zrrk_REV, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Zrrkz, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA32Zrrkz_REV, X86_INS_VMOVDQA32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z128mr, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z128mrk, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z128rm, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z128rmk, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z128rmkz, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z128rr, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z128rr_REV, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z128rrk, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z128rrk_REV, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z128rrkz, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z128rrkz_REV, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z256mr, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z256mrk, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z256rm, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z256rmk, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z256rmkz, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z256rr, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z256rr_REV, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z256rrk, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z256rrk_REV, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z256rrkz, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Z256rrkz_REV, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Zmr, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Zmrk, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Zrm, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Zrmk, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Zrmkz, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Zrr, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Zrr_REV, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Zrrk, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Zrrk_REV, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Zrrkz, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQA64Zrrkz_REV, X86_INS_VMOVDQA64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQAYmr, X86_INS_VMOVDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQAYrm, X86_INS_VMOVDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQAYrr, X86_INS_VMOVDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQAYrr_REV, X86_INS_VMOVDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQAmr, X86_INS_VMOVDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQArm, X86_INS_VMOVDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQArr, X86_INS_VMOVDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQArr_REV, X86_INS_VMOVDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z128mr, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z128mrk, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z128rm, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z128rmk, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z128rmkz, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z128rr, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z128rr_REV, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z128rrk, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z128rrk_REV, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z128rrkz, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z128rrkz_REV, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z256mr, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z256mrk, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z256rm, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z256rmk, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z256rmkz, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z256rr, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z256rr_REV, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z256rrk, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z256rrk_REV, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z256rrkz, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Z256rrkz_REV, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Zmr, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Zmrk, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Zrm, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Zrmk, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Zrmkz, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Zrr, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Zrr_REV, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Zrrk, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Zrrk_REV, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Zrrkz, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU16Zrrkz_REV, X86_INS_VMOVDQU16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z128mr, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z128mrk, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z128rm, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z128rmk, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z128rmkz, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z128rr, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z128rr_REV, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z128rrk, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z128rrk_REV, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z128rrkz, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z128rrkz_REV, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z256mr, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z256mrk, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z256rm, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z256rmk, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z256rmkz, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z256rr, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z256rr_REV, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z256rrk, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z256rrk_REV, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z256rrkz, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Z256rrkz_REV, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Zmr, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Zmrk, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Zrm, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Zrmk, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Zrmkz, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Zrr, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Zrr_REV, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Zrrk, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Zrrk_REV, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Zrrkz, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU32Zrrkz_REV, X86_INS_VMOVDQU32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z128mr, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z128mrk, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z128rm, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z128rmk, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z128rmkz, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z128rr, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z128rr_REV, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z128rrk, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z128rrk_REV, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z128rrkz, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z128rrkz_REV, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z256mr, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z256mrk, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z256rm, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z256rmk, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z256rmkz, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z256rr, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z256rr_REV, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z256rrk, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z256rrk_REV, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z256rrkz, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Z256rrkz_REV, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Zmr, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Zmrk, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Zrm, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Zrmk, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Zrmkz, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Zrr, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Zrr_REV, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Zrrk, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Zrrk_REV, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Zrrkz, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU64Zrrkz_REV, X86_INS_VMOVDQU64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z128mr, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z128mrk, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z128rm, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z128rmk, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z128rmkz, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z128rr, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z128rr_REV, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z128rrk, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z128rrk_REV, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z128rrkz, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z128rrkz_REV, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z256mr, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z256mrk, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z256rm, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z256rmk, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z256rmkz, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z256rr, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z256rr_REV, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z256rrk, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z256rrk_REV, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z256rrkz, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Z256rrkz_REV, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Zmr, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Zmrk, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Zrm, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Zrmk, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Zrmkz, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Zrr, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Zrr_REV, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Zrrk, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Zrrk_REV, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Zrrkz, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQU8Zrrkz_REV, X86_INS_VMOVDQU8, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQUYmr, X86_INS_VMOVDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQUYrm, X86_INS_VMOVDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQUYrr, X86_INS_VMOVDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQUYrr_REV, X86_INS_VMOVDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQUmr, X86_INS_VMOVDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQUrm, X86_INS_VMOVDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQUrr, X86_INS_VMOVDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVDQUrr_REV, X86_INS_VMOVDQU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVHLPSZrr, X86_INS_VMOVHLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVHLPSrr, X86_INS_VMOVHLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVHPDZ128mr, X86_INS_VMOVHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVHPDZ128rm, X86_INS_VMOVHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVHPDmr, X86_INS_VMOVHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVHPDrm, X86_INS_VMOVHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVHPSZ128mr, X86_INS_VMOVHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVHPSZ128rm, X86_INS_VMOVHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVHPSmr, X86_INS_VMOVHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVHPSrm, X86_INS_VMOVHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVLHPSZrr, X86_INS_VMOVLHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVLHPSrr, X86_INS_VMOVLHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVLPDZ128mr, X86_INS_VMOVLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVLPDZ128rm, X86_INS_VMOVLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVLPDmr, X86_INS_VMOVLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVLPDrm, X86_INS_VMOVLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVLPSZ128mr, X86_INS_VMOVLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVLPSZ128rm, X86_INS_VMOVLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVLPSmr, X86_INS_VMOVLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVLPSrm, X86_INS_VMOVLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVMSKPDYrr, X86_INS_VMOVMSKPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVMSKPDrr, X86_INS_VMOVMSKPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVMSKPSYrr, X86_INS_VMOVMSKPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVMSKPSrr, X86_INS_VMOVMSKPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTDQAYrm, X86_INS_VMOVNTDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTDQAZ128rm, X86_INS_VMOVNTDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTDQAZ256rm, X86_INS_VMOVNTDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTDQAZrm, X86_INS_VMOVNTDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTDQArm, X86_INS_VMOVNTDQA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTDQYmr, X86_INS_VMOVNTDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTDQZ128mr, X86_INS_VMOVNTDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTDQZ256mr, X86_INS_VMOVNTDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTDQZmr, X86_INS_VMOVNTDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTDQmr, X86_INS_VMOVNTDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTPDYmr, X86_INS_VMOVNTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTPDZ128mr, X86_INS_VMOVNTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTPDZ256mr, X86_INS_VMOVNTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTPDZmr, X86_INS_VMOVNTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTPDmr, X86_INS_VMOVNTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTPSYmr, X86_INS_VMOVNTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTPSZ128mr, X86_INS_VMOVNTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTPSZ256mr, X86_INS_VMOVNTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTPSZmr, X86_INS_VMOVNTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVNTPSmr, X86_INS_VMOVNTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVPDI2DIZmr, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVPDI2DIZrr, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVPDI2DImr, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVPDI2DIrr, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVPQI2QIZmr, X86_INS_VMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVPQI2QIZrr, X86_INS_VMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVPQI2QImr, X86_INS_VMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVPQI2QIrr, X86_INS_VMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVPQIto64Zmr, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVPQIto64Zrr, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVPQIto64mr, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVPQIto64rr, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVQI2PQIZrm, X86_INS_VMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVQI2PQIrm, X86_INS_VMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDZmr, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDZmrk, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDZrm, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDZrmk, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDZrmkz, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDZrr, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDZrr_REV, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDZrrk, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDZrrk_REV, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDZrrkz, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDZrrkz_REV, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDmr, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDrm, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDrr, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDrr_REV, X86_INS_VMOVSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDto64Zmr, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDto64Zrr, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDto64mr, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSDto64rr, X86_INS_VMOVQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPYrm, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPYrr, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZ128rm, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZ128rmk, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZ128rmkz, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZ128rr, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZ128rrk, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZ128rrkz, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZ256rm, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZ256rmk, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZ256rmkz, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZ256rr, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZ256rrk, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZ256rrkz, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZrm, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZrmk, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZrmkz, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZrr, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZrrk, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPZrrkz, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPrm, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSHDUPrr, X86_INS_VMOVSHDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPYrm, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPYrr, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZ128rm, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZ128rmk, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZ128rmkz, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZ128rr, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZ128rrk, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZ128rrkz, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZ256rm, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZ256rmk, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZ256rmkz, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZ256rr, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZ256rrk, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZ256rrkz, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZrm, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZrmk, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZrmkz, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZrr, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZrrk, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPZrrkz, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPrm, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSLDUPrr, X86_INS_VMOVSLDUP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSS2DIZmr, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSS2DIZrr, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSS2DImr, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSS2DIrr, X86_INS_VMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSZmr, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSZmrk, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSZrm, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSZrmk, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSZrmkz, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSZrr, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSZrr_REV, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSZrrk, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSZrrk_REV, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSZrrkz, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSZrrkz_REV, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSmr, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSrm, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSrr, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVSSrr_REV, X86_INS_VMOVSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDYmr, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDYrm, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDYrr, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDYrr_REV, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ128mr, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ128mrk, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ128rm, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ128rmk, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ128rmkz, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ128rr, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ128rr_REV, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ128rrk, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ128rrk_REV, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ128rrkz, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ128rrkz_REV, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ256mr, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ256mrk, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ256rm, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ256rmk, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ256rmkz, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ256rr, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ256rr_REV, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ256rrk, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ256rrk_REV, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ256rrkz, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZ256rrkz_REV, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZmr, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZmrk, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZrm, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZrmk, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZrmkz, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZrr, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZrr_REV, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZrrk, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZrrk_REV, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZrrkz, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDZrrkz_REV, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDmr, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDrm, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDrr, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPDrr_REV, X86_INS_VMOVUPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSYmr, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSYrm, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSYrr, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSYrr_REV, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ128mr, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ128mrk, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ128rm, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ128rmk, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ128rmkz, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ128rr, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ128rr_REV, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ128rrk, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ128rrk_REV, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ128rrkz, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ128rrkz_REV, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ256mr, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ256mrk, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ256rm, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ256rmk, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ256rmkz, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ256rr, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ256rr_REV, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ256rrk, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ256rrk_REV, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ256rrkz, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZ256rrkz_REV, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZmr, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZmrk, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZrm, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZrmk, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZrmkz, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZrr, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZrr_REV, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZrrk, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZrrk_REV, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZrrkz, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSZrrkz_REV, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSmr, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSrm, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSrr, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVUPSrr_REV, X86_INS_VMOVUPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVZPQILo2PQIZrr, X86_INS_VMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMOVZPQILo2PQIrr, X86_INS_VMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMPSADBWYrmi, X86_INS_VMPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VMPSADBWYrri, X86_INS_VMPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VMPSADBWrmi, X86_INS_VMPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMPSADBWrri, X86_INS_VMPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMPTRLDm, X86_INS_VMPTRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMPTRSTm, X86_INS_VMPTRST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMREAD32mr, X86_INS_VMREAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMREAD32rr, X86_INS_VMREAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMREAD64mr, X86_INS_VMREAD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMREAD64rr, X86_INS_VMREAD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMRESUME, X86_INS_VMRESUME, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMRUN32, X86_INS_VMRUN, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMRUN64, X86_INS_VMRUN, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMSAVE32, X86_INS_VMSAVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMSAVE64, X86_INS_VMSAVE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDYrm, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDYrr, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ128rm, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ128rmb, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ128rmbk, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ128rmbkz, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ128rmk, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ128rmkz, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ128rr, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ128rrk, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ128rrkz, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ256rm, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ256rmb, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ256rmbk, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ256rmbkz, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ256rmk, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ256rmkz, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ256rr, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ256rrk, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZ256rrkz, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZrm, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZrmb, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZrmbk, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZrmbkz, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZrmk, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZrmkz, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZrr, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZrrb, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZrrbk, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZrrbkz, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZrrk, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDZrrkz, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDrm, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPDrr, X86_INS_VMULPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSYrm, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSYrr, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ128rm, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ128rmb, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ128rmbk, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ128rmbkz, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ128rmk, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ128rmkz, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ128rr, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ128rrk, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ128rrkz, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ256rm, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ256rmb, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ256rmbk, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ256rmbkz, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ256rmk, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ256rmkz, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ256rr, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ256rrk, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZ256rrkz, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZrm, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZrmb, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZrmbk, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZrmbkz, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZrmk, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZrmkz, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZrr, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZrrb, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZrrbk, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZrrbkz, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZrrk, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSZrrkz, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSrm, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULPSrr, X86_INS_VMULPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDZrm, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDZrm_Int, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDZrm_Intk, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDZrm_Intkz, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDZrr, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDZrr_Int, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDZrr_Intk, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDZrr_Intkz, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDZrrb_Int, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDZrrb_Intk, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDZrrb_Intkz, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDrm, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDrm_Int, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDrr, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSDrr_Int, X86_INS_VMULSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSZrm, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSZrm_Int, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSZrm_Intk, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSZrm_Intkz, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSZrr, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSZrr_Int, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSZrr_Intk, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSZrr_Intkz, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSZrrb_Int, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSZrrb_Intk, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSZrrb_Intkz, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSrm, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSrm_Int, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSrr, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMULSSrr_Int, X86_INS_VMULSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VMWRITE32rm, X86_INS_VMWRITE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMWRITE32rr, X86_INS_VMWRITE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMWRITE64rm, X86_INS_VMWRITE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMWRITE64rr, X86_INS_VMWRITE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMXOFF, X86_INS_VMXOFF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMXON, X86_INS_VMXON, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDYrm, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDYrr, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ128rm, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ128rmb, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ128rmbk, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ128rmbkz, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ128rmk, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ128rmkz, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ128rr, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ128rrk, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ128rrkz, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ256rm, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ256rmb, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ256rmbk, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ256rmbkz, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ256rmk, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ256rmkz, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ256rr, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ256rrk, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZ256rrkz, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZrm, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZrmb, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZrmbk, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZrmbkz, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZrmk, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZrmkz, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZrr, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZrrk, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDZrrkz, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDrm, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VORPDrr, X86_INS_VORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSYrm, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSYrr, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ128rm, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ128rmb, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ128rmbk, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ128rmbkz, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ128rmk, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ128rmkz, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ128rr, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ128rrk, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ128rrkz, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ256rm, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ256rmb, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ256rmbk, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ256rmbkz, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ256rmk, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ256rmkz, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ256rr, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ256rrk, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZ256rrkz, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZrm, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZrmb, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZrmbk, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZrmbkz, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZrmk, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZrmkz, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZrr, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZrrk, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSZrrkz, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSrm, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VORPSrr, X86_INS_VORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VP4DPWSSDSrm, X86_INS_VP4DPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VP4DPWSSDSrmk, X86_INS_VP4DPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VP4DPWSSDSrmkz, X86_INS_VP4DPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VP4DPWSSDrm, X86_INS_VP4DPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VP4DPWSSDrmk, X86_INS_VP4DPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VP4DPWSSDrmkz, X86_INS_VP4DPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBYrm, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBYrr, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZ128rm, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZ128rmk, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZ128rmkz, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZ128rr, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZ128rrk, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZ128rrkz, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZ256rm, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZ256rmk, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZ256rmkz, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZ256rr, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZ256rrk, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZ256rrkz, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZrm, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZrmk, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZrmkz, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZrr, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZrrk, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBZrrkz, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBrm, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSBrr, X86_INS_VPABSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDYrm, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDYrr, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ128rm, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ128rmb, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ128rmbk, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ128rmbkz, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ128rmk, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ128rmkz, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ128rr, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ128rrk, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ128rrkz, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ256rm, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ256rmb, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ256rmbk, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ256rmbkz, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ256rmk, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ256rmkz, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ256rr, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ256rrk, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZ256rrkz, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZrm, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZrmb, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZrmbk, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZrmbkz, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZrmk, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZrmkz, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZrr, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZrrk, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDZrrkz, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDrm, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSDrr, X86_INS_VPABSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ128rm, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ128rmb, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ128rmbk, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ128rmbkz, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ128rmk, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ128rmkz, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ128rr, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ128rrk, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ128rrkz, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ256rm, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ256rmb, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ256rmbk, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ256rmbkz, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ256rmk, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ256rmkz, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ256rr, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ256rrk, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZ256rrkz, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZrm, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZrmb, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZrmbk, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZrmbkz, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZrmk, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZrmkz, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZrr, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZrrk, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSQZrrkz, X86_INS_VPABSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWYrm, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWYrr, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZ128rm, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZ128rmk, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZ128rmkz, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZ128rr, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZ128rrk, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZ128rrkz, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZ256rm, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZ256rmk, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZ256rmkz, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZ256rr, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZ256rrk, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZ256rrkz, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZrm, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZrmk, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZrmkz, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZrr, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZrrk, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWZrrkz, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWrm, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPABSWrr, X86_INS_VPABSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWYrm, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWYrr, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ128rm, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ128rmb, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ128rmbk, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ128rmbkz, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ128rmk, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ128rmkz, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ128rr, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ128rrk, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ128rrkz, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ256rm, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ256rmb, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ256rmbk, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ256rmbkz, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ256rmk, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ256rmkz, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ256rr, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ256rrk, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZ256rrkz, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZrm, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZrmb, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZrmbk, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZrmbkz, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZrmk, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZrmkz, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZrr, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZrrk, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWZrrkz, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWrm, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSDWrr, X86_INS_VPACKSSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBYrm, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBYrr, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZ128rm, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZ128rmk, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZ128rmkz, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZ128rr, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZ128rrk, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZ128rrkz, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZ256rm, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZ256rmk, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZ256rmkz, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZ256rr, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZ256rrk, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZ256rrkz, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZrm, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZrmk, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZrmkz, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZrr, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZrrk, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBZrrkz, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBrm, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKSSWBrr, X86_INS_VPACKSSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWYrm, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWYrr, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ128rm, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ128rmb, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ128rmbk, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ128rmbkz, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ128rmk, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ128rmkz, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ128rr, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ128rrk, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ128rrkz, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ256rm, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ256rmb, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ256rmbk, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ256rmbkz, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ256rmk, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ256rmkz, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ256rr, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ256rrk, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZ256rrkz, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZrm, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZrmb, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZrmbk, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZrmbkz, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZrmk, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZrmkz, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZrr, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZrrk, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWZrrkz, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWrm, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSDWrr, X86_INS_VPACKUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBYrm, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBYrr, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZ128rm, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZ128rmk, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZ128rmkz, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZ128rr, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZ128rrk, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZ128rrkz, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZ256rm, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZ256rmk, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZ256rmkz, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZ256rr, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZ256rrk, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZ256rrkz, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZrm, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZrmk, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZrmkz, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZrr, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZrrk, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBZrrkz, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBrm, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPACKUSWBrr, X86_INS_VPACKUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBYrm, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBYrr, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZ128rm, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZ128rmk, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZ128rmkz, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZ128rr, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZ128rrk, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZ128rrkz, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZ256rm, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZ256rmk, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZ256rmkz, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZ256rr, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZ256rrk, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZ256rrkz, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZrm, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZrmk, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZrmkz, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZrr, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZrrk, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBZrrkz, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBrm, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDBrr, X86_INS_VPADDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDYrm, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDYrr, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ128rm, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ128rmb, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ128rmbk, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ128rmbkz, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ128rmk, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ128rmkz, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ128rr, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ128rrk, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ128rrkz, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ256rm, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ256rmb, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ256rmbk, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ256rmbkz, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ256rmk, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ256rmkz, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ256rr, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ256rrk, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZ256rrkz, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZrm, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZrmb, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZrmbk, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZrmbkz, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZrmk, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZrmkz, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZrr, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZrrk, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDZrrkz, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDrm, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDDrr, X86_INS_VPADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQYrm, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQYrr, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ128rm, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ128rmb, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ128rmbk, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ128rmbkz, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ128rmk, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ128rmkz, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ128rr, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ128rrk, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ128rrkz, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ256rm, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ256rmb, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ256rmbk, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ256rmbkz, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ256rmk, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ256rmkz, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ256rr, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ256rrk, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZ256rrkz, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZrm, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZrmb, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZrmbk, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZrmbkz, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZrmk, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZrmkz, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZrr, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZrrk, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQZrrkz, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQrm, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDQrr, X86_INS_VPADDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBYrm, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBYrr, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZ128rm, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZ128rmk, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZ128rmkz, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZ128rr, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZ128rrk, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZ128rrkz, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZ256rm, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZ256rmk, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZ256rmkz, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZ256rr, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZ256rrk, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZ256rrkz, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZrm, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZrmk, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZrmkz, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZrr, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZrrk, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBZrrkz, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBrm, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSBrr, X86_INS_VPADDSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWYrm, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWYrr, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZ128rm, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZ128rmk, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZ128rmkz, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZ128rr, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZ128rrk, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZ128rrkz, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZ256rm, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZ256rmk, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZ256rmkz, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZ256rr, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZ256rrk, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZ256rrkz, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZrm, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZrmk, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZrmkz, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZrr, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZrrk, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWZrrkz, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWrm, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDSWrr, X86_INS_VPADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBYrm, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBYrr, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZ128rm, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZ128rmk, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZ128rmkz, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZ128rr, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZ128rrk, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZ128rrkz, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZ256rm, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZ256rmk, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZ256rmkz, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZ256rr, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZ256rrk, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZ256rrkz, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZrm, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZrmk, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZrmkz, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZrr, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZrrk, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBZrrkz, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBrm, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSBrr, X86_INS_VPADDUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWYrm, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWYrr, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZ128rm, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZ128rmk, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZ128rmkz, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZ128rr, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZ128rrk, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZ128rrkz, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZ256rm, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZ256rmk, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZ256rmkz, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZ256rr, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZ256rrk, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZ256rrkz, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZrm, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZrmk, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZrmkz, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZrr, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZrrk, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWZrrkz, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWrm, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDUSWrr, X86_INS_VPADDUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWYrm, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWYrr, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZ128rm, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZ128rmk, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZ128rmkz, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZ128rr, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZ128rrk, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZ128rrkz, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZ256rm, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZ256rmk, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZ256rmkz, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZ256rr, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZ256rrk, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZ256rrkz, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZrm, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZrmk, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZrmkz, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZrr, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZrrk, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWZrrkz, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWrm, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPADDWrr, X86_INS_VPADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRYrmi, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRYrri, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZ128rmi, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZ128rmik, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZ128rmikz, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZ128rri, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZ128rrik, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZ128rrikz, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZ256rmi, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZ256rmik, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZ256rmikz, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZ256rri, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZ256rrik, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZ256rrikz, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZrmi, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZrmik, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZrmikz, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZrri, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZrrik, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRZrrikz, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRrmi, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPALIGNRrri, X86_INS_VPALIGNR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ128rm, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ128rmb, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ128rmbk, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ128rmbkz, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ128rmk, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ128rmkz, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ128rr, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ128rrk, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ128rrkz, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ256rm, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ256rmb, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ256rmbk, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ256rmbkz, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ256rmk, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ256rmkz, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ256rr, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ256rrk, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZ256rrkz, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZrm, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZrmb, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZrmbk, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZrmbkz, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZrmk, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZrmkz, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZrr, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZrrk, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDDZrrkz, X86_INS_VPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ128rm, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ128rmb, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ128rmbk, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ128rmbkz, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ128rmk, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ128rmkz, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ128rr, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ128rrk, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ128rrkz, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ256rm, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ256rmb, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ256rmbk, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ256rmbkz, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ256rmk, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ256rmkz, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ256rr, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ256rrk, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZ256rrkz, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZrm, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZrmb, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZrmbk, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZrmbkz, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZrmk, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZrmkz, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZrr, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZrrk, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNDZrrkz, X86_INS_VPANDND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ128rm, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ128rmb, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ128rmbk, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ128rmbkz, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ128rmk, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ128rmkz, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ128rr, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ128rrk, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ128rrkz, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ256rm, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ256rmb, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ256rmbk, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ256rmbkz, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ256rmk, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ256rmkz, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ256rr, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ256rrk, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZ256rrkz, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZrm, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZrmb, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZrmbk, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZrmbkz, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZrmk, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZrmkz, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZrr, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZrrk, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNQZrrkz, X86_INS_VPANDNQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNYrm, X86_INS_VPANDN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNYrr, X86_INS_VPANDN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNrm, X86_INS_VPANDN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDNrr, X86_INS_VPANDN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ128rm, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ128rmb, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ128rmbk, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ128rmbkz, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ128rmk, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ128rmkz, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ128rr, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ128rrk, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ128rrkz, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ256rm, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ256rmb, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ256rmbk, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ256rmbkz, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ256rmk, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ256rmkz, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ256rr, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ256rrk, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZ256rrkz, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZrm, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZrmb, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZrmbk, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZrmbkz, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZrmk, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZrmkz, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZrr, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZrrk, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDQZrrkz, X86_INS_VPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDYrm, X86_INS_VPAND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDYrr, X86_INS_VPAND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDrm, X86_INS_VPAND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPANDrr, X86_INS_VPAND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBYrm, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBYrr, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZ128rm, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZ128rmk, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZ128rmkz, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZ128rr, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZ128rrk, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZ128rrkz, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZ256rm, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZ256rmk, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZ256rmkz, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZ256rr, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZ256rrk, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZ256rrkz, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZrm, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZrmk, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZrmkz, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZrr, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZrrk, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBZrrkz, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBrm, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGBrr, X86_INS_VPAVGB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWYrm, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWYrr, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZ128rm, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZ128rmk, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZ128rmkz, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZ128rr, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZ128rrk, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZ128rrkz, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZ256rm, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZ256rmk, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZ256rmkz, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZ256rr, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZ256rrk, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZ256rrkz, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZrm, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZrmk, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZrmkz, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZrr, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZrrk, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWZrrkz, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWrm, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPAVGWrr, X86_INS_VPAVGW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDDYrmi, X86_INS_VPBLENDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDDYrri, X86_INS_VPBLENDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDDrmi, X86_INS_VPBLENDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDDrri, X86_INS_VPBLENDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZ128rm, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZ128rmk, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZ128rmkz, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZ128rr, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZ128rrk, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZ128rrkz, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZ256rm, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZ256rmk, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZ256rmkz, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZ256rr, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZ256rrk, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZ256rrkz, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZrm, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZrmk, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZrmkz, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZrr, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZrrk, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMBZrrkz, X86_INS_VPBLENDMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ128rm, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ128rmb, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ128rmbk, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ128rmbkz, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ128rmk, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ128rmkz, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ128rr, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ128rrk, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ128rrkz, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ256rm, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ256rmb, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ256rmbk, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ256rmbkz, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ256rmk, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ256rmkz, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ256rr, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ256rrk, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZ256rrkz, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZrm, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZrmb, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZrmbk, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZrmbkz, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZrmk, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZrmkz, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZrr, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZrrk, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMDZrrkz, X86_INS_VPBLENDMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ128rm, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ128rmb, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ128rmbk, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ128rmbkz, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ128rmk, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ128rmkz, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ128rr, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ128rrk, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ128rrkz, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ256rm, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ256rmb, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ256rmbk, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ256rmbkz, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ256rmk, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ256rmkz, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ256rr, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ256rrk, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZ256rrkz, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZrm, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZrmb, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZrmbk, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZrmbkz, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZrmk, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZrmkz, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZrr, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZrrk, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMQZrrkz, X86_INS_VPBLENDMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZ128rm, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZ128rmk, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZ128rmkz, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZ128rr, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZ128rrk, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZ128rrkz, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZ256rm, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZ256rmk, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZ256rmkz, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZ256rr, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZ256rrk, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZ256rrkz, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZrm, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZrmk, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZrmkz, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZrr, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZrrk, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDMWZrrkz, X86_INS_VPBLENDMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDVBYrm, X86_INS_VPBLENDVB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDVBYrr, X86_INS_VPBLENDVB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDVBrm, X86_INS_VPBLENDVB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDVBrr, X86_INS_VPBLENDVB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDWYrmi, X86_INS_VPBLENDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDWYrri, X86_INS_VPBLENDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDWrmi, X86_INS_VPBLENDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBLENDWrri, X86_INS_VPBLENDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBYrm, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBYrr, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZ128m, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZ128mk, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZ128mkz, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZ128r, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZ128rk, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZ128rkz, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZ256m, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZ256mk, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZ256mkz, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZ256r, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZ256rk, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZ256rkz, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZm, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZmk, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZmkz, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZr, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZrk, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBZrkz, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBrZ128r, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBrZ128rk, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBrZ128rkz, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBrZ256r, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBrZ256rk, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBrZ256rkz, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBrZr, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBrZrk, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBrZrkz, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBrm, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTBrr, X86_INS_VPBROADCASTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDYrm, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDYrr, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZ128m, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZ128mk, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZ128mkz, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZ128r, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZ128rk, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZ128rkz, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZ256m, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZ256mk, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZ256mkz, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZ256r, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZ256rk, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZ256rkz, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZm, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZmk, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZmkz, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZr, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZrk, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDZrkz, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDrZ128r, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDrZ128rk, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDrZ128rkz, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDrZ256r, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDrZ256rk, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDrZ256rkz, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDrZr, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDrZrk, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDrZrkz, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDrm, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTDrr, X86_INS_VPBROADCASTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTMB2QZ128rr, X86_INS_VPBROADCASTMB2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTMB2QZ256rr, X86_INS_VPBROADCASTMB2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTMB2QZrr, X86_INS_VPBROADCASTMB2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTMW2DZ128rr, X86_INS_VPBROADCASTMW2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTMW2DZ256rr, X86_INS_VPBROADCASTMW2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTMW2DZrr, X86_INS_VPBROADCASTMW2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQYrm, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQYrr, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZ128m, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZ128mk, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZ128mkz, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZ128r, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZ128rk, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZ128rkz, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZ256m, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZ256mk, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZ256mkz, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZ256r, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZ256rk, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZ256rkz, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZm, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZmk, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZmkz, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZr, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZrk, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQZrkz, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQrZ128r, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQrZ128rk, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQrZ128rkz, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQrZ256r, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQrZ256rk, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQrZ256rkz, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQrZr, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQrZrk, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQrZrkz, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQrm, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTQrr, X86_INS_VPBROADCASTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWYrm, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWYrr, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZ128m, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZ128mk, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZ128mkz, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZ128r, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZ128rk, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZ128rkz, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZ256m, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZ256mk, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZ256mkz, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZ256r, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZ256rk, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZ256rkz, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZm, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZmk, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZmkz, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZr, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZrk, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWZrkz, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWrZ128r, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWrZ128rk, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWrZ128rkz, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWrZ256r, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWrZ256rk, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWrZ256rkz, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWrZr, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWrZrk, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWrZrkz, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWrm, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPBROADCASTWrr, X86_INS_VPBROADCASTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCLMULQDQYrm, X86_INS_VPCLMULQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCLMULQDQYrr, X86_INS_VPCLMULQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCLMULQDQZ128rm, X86_INS_VPCLMULQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCLMULQDQZ128rr, X86_INS_VPCLMULQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCLMULQDQZ256rm, X86_INS_VPCLMULQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCLMULQDQZ256rr, X86_INS_VPCLMULQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCLMULQDQZrm, X86_INS_VPCLMULQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCLMULQDQZrr, X86_INS_VPCLMULQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCLMULQDQrm, X86_INS_VPCLMULQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_PCLMUL, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCLMULQDQrr, X86_INS_VPCLMULQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_PCLMUL, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMOVYrmr, X86_INS_VPCMOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMOVYrrm, X86_INS_VPCMOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMOVYrrr, X86_INS_VPCMOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMOVYrrr_REV, X86_INS_VPCMOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMOVrmr, X86_INS_VPCMOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMOVrrm, X86_INS_VPCMOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMOVrrr, X86_INS_VPCMOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMOVrrr_REV, X86_INS_VPCMOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ128rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ128rmi_alt, X86_INS_VPCMPB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ128rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ128rmik_alt, X86_INS_VPCMPB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ128rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ128rri_alt, X86_INS_VPCMPB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ128rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ128rrik_alt, X86_INS_VPCMPB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ256rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ256rmi_alt, X86_INS_VPCMPB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ256rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ256rmik_alt, X86_INS_VPCMPB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ256rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ256rri_alt, X86_INS_VPCMPB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ256rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZ256rrik_alt, X86_INS_VPCMPB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZrmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZrmi_alt, X86_INS_VPCMPB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZrmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZrmik_alt, X86_INS_VPCMPB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZrri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZrri_alt, X86_INS_VPCMPB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZrrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPBZrrik_alt, X86_INS_VPCMPB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ128rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ128rmi_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ128rmib, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ128rmib_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ128rmibk, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ128rmibk_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ128rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ128rmik_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ128rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ128rri_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ128rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ128rrik_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ256rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ256rmi_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ256rmib, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ256rmib_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ256rmibk, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ256rmibk_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ256rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ256rmik_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ256rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ256rri_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ256rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZ256rrik_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZrmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZrmi_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZrmib, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZrmib_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZrmibk, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZrmibk_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZrmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZrmik_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZrri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZrri_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZrrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPDZrrik_alt, X86_INS_VPCMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBYrm, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBYrr, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBZ128rm, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBZ128rmk, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBZ128rr, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBZ128rrk, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBZ256rm, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBZ256rmk, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBZ256rr, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBZ256rrk, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBZrm, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBZrmk, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBZrr, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBZrrk, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBrm, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQBrr, X86_INS_VPCMPEQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDYrm, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDYrr, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZ128rm, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZ128rmb, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZ128rmbk, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZ128rmk, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZ128rr, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZ128rrk, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZ256rm, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZ256rmb, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZ256rmbk, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZ256rmk, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZ256rr, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZ256rrk, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZrm, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZrmb, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZrmbk, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZrmk, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZrr, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDZrrk, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDrm, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQDrr, X86_INS_VPCMPEQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQYrm, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQYrr, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZ128rm, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZ128rmb, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZ128rmbk, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZ128rmk, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZ128rr, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZ128rrk, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZ256rm, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZ256rmb, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZ256rmbk, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZ256rmk, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZ256rr, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZ256rrk, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZrm, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZrmb, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZrmbk, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZrmk, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZrr, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQZrrk, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQrm, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQQrr, X86_INS_VPCMPEQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWYrm, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWYrr, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWZ128rm, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWZ128rmk, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWZ128rr, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWZ128rrk, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWZ256rm, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWZ256rmk, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWZ256rr, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWZ256rrk, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWZrm, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWZrmk, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWZrr, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWZrrk, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWrm, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPEQWrr, X86_INS_VPCMPEQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPESTRIrm, X86_INS_VPCMPESTRI, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPESTRIrr, X86_INS_VPCMPESTRI, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPESTRMrm, X86_INS_VPCMPESTRM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPESTRMrr, X86_INS_VPCMPESTRM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBYrm, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBYrr, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBZ128rm, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBZ128rmk, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBZ128rr, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBZ128rrk, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBZ256rm, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBZ256rmk, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBZ256rr, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBZ256rrk, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBZrm, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBZrmk, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBZrr, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBZrrk, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBrm, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTBrr, X86_INS_VPCMPGTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDYrm, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDYrr, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZ128rm, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZ128rmb, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZ128rmbk, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZ128rmk, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZ128rr, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZ128rrk, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZ256rm, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZ256rmb, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZ256rmbk, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZ256rmk, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZ256rr, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZ256rrk, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZrm, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZrmb, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZrmbk, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZrmk, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZrr, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDZrrk, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDrm, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTDrr, X86_INS_VPCMPGTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQYrm, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQYrr, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZ128rm, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZ128rmb, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZ128rmbk, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZ128rmk, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZ128rr, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZ128rrk, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZ256rm, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZ256rmb, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZ256rmbk, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZ256rmk, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZ256rr, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZ256rrk, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZrm, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZrmb, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZrmbk, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZrmk, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZrr, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQZrrk, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQrm, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTQrr, X86_INS_VPCMPGTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWYrm, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWYrr, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWZ128rm, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWZ128rmk, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWZ128rr, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWZ128rrk, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWZ256rm, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWZ256rmk, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWZ256rr, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWZ256rrk, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWZrm, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWZrmk, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWZrr, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWZrrk, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWrm, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPGTWrr, X86_INS_VPCMPGTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPISTRIrm, X86_INS_VPCMPISTRI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPISTRIrr, X86_INS_VPCMPISTRI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPISTRMrm, X86_INS_VPCMPISTRM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPISTRMrr, X86_INS_VPCMPISTRM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ128rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ128rmi_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ128rmib, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ128rmib_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ128rmibk, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ128rmibk_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ128rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ128rmik_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ128rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ128rri_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ128rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ128rrik_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ256rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ256rmi_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ256rmib, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ256rmib_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ256rmibk, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ256rmibk_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ256rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ256rmik_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ256rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ256rri_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ256rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZ256rrik_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZrmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZrmi_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZrmib, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZrmib_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZrmibk, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZrmibk_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZrmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZrmik_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZrri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZrri_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZrrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPQZrrik_alt, X86_INS_VPCMPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ128rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ128rmi_alt, X86_INS_VPCMPUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ128rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ128rmik_alt, X86_INS_VPCMPUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ128rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ128rri_alt, X86_INS_VPCMPUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ128rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ128rrik_alt, X86_INS_VPCMPUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ256rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ256rmi_alt, X86_INS_VPCMPUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ256rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ256rmik_alt, X86_INS_VPCMPUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ256rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ256rri_alt, X86_INS_VPCMPUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ256rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZ256rrik_alt, X86_INS_VPCMPUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZrmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZrmi_alt, X86_INS_VPCMPUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZrmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZrmik_alt, X86_INS_VPCMPUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZrri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZrri_alt, X86_INS_VPCMPUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZrrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUBZrrik_alt, X86_INS_VPCMPUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ128rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ128rmi_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ128rmib, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ128rmib_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ128rmibk, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ128rmibk_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ128rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ128rmik_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ128rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ128rri_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ128rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ128rrik_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ256rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ256rmi_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ256rmib, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ256rmib_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ256rmibk, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ256rmibk_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ256rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ256rmik_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ256rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ256rri_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ256rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZ256rrik_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZrmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZrmi_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZrmib, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZrmib_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZrmibk, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZrmibk_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZrmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZrmik_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZrri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZrri_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZrrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUDZrrik_alt, X86_INS_VPCMPUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ128rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ128rmi_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ128rmib, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ128rmib_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ128rmibk, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ128rmibk_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ128rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ128rmik_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ128rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ128rri_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ128rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ128rrik_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ256rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ256rmi_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ256rmib, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ256rmib_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ256rmibk, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ256rmibk_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ256rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ256rmik_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ256rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ256rri_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ256rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZ256rrik_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZrmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZrmi_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZrmib, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZrmib_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZrmibk, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZrmibk_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZrmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZrmik_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZrri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZrri_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZrrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUQZrrik_alt, X86_INS_VPCMPUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ128rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ128rmi_alt, X86_INS_VPCMPUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ128rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ128rmik_alt, X86_INS_VPCMPUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ128rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ128rri_alt, X86_INS_VPCMPUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ128rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ128rrik_alt, X86_INS_VPCMPUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ256rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ256rmi_alt, X86_INS_VPCMPUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ256rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ256rmik_alt, X86_INS_VPCMPUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ256rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ256rri_alt, X86_INS_VPCMPUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ256rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZ256rrik_alt, X86_INS_VPCMPUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZrmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZrmi_alt, X86_INS_VPCMPUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZrmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZrmik_alt, X86_INS_VPCMPUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZrri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZrri_alt, X86_INS_VPCMPUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZrrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPUWZrrik_alt, X86_INS_VPCMPUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ128rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ128rmi_alt, X86_INS_VPCMPW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ128rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ128rmik_alt, X86_INS_VPCMPW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ128rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ128rri_alt, X86_INS_VPCMPW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ128rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ128rrik_alt, X86_INS_VPCMPW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ256rmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ256rmi_alt, X86_INS_VPCMPW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ256rmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ256rmik_alt, X86_INS_VPCMPW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ256rri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ256rri_alt, X86_INS_VPCMPW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ256rrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZ256rrik_alt, X86_INS_VPCMPW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZrmi, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZrmi_alt, X86_INS_VPCMPW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZrmik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZrmik_alt, X86_INS_VPCMPW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZrri, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZrri_alt, X86_INS_VPCMPW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZrrik, X86_INS_VPCMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCMPWZrrik_alt, X86_INS_VPCMPW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMBmi, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMBmi_alt, X86_INS_VPCOMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMBri, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMBri_alt, X86_INS_VPCOMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMDmi, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMDmi_alt, X86_INS_VPCOMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMDri, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMDri_alt, X86_INS_VPCOMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZ128mr, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZ128mrk, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZ128rr, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZ128rrk, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZ128rrkz, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZ256mr, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZ256mrk, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZ256rr, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZ256rrk, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZ256rrkz, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZmr, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZmrk, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZrr, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZrrk, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSBZrrkz, X86_INS_VPCOMPRESSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZ128mr, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZ128mrk, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZ128rr, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZ128rrk, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZ128rrkz, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZ256mr, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZ256mrk, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZ256rr, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZ256rrk, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZ256rrkz, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZmr, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZmrk, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZrr, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZrrk, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSDZrrkz, X86_INS_VPCOMPRESSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZ128mr, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZ128mrk, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZ128rr, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZ128rrk, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZ128rrkz, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZ256mr, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZ256mrk, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZ256rr, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZ256rrk, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZ256rrkz, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZmr, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZmrk, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZrr, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZrrk, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSQZrrkz, X86_INS_VPCOMPRESSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZ128mr, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZ128mrk, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZ128rr, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZ128rrk, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZ128rrkz, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZ256mr, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZ256mrk, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZ256rr, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZ256rrk, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZ256rrkz, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZmr, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZmrk, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZrr, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZrrk, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMPRESSWZrrkz, X86_INS_VPCOMPRESSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMQmi, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMQmi_alt, X86_INS_VPCOMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMQri, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMQri_alt, X86_INS_VPCOMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUBmi, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUBmi_alt, X86_INS_VPCOMUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUBri, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUBri_alt, X86_INS_VPCOMUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUDmi, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUDmi_alt, X86_INS_VPCOMUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUDri, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUDri_alt, X86_INS_VPCOMUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUQmi, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUQmi_alt, X86_INS_VPCOMUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUQri, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUQri_alt, X86_INS_VPCOMUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUWmi, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUWmi_alt, X86_INS_VPCOMUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUWri, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMUWri_alt, X86_INS_VPCOMUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMWmi, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMWmi_alt, X86_INS_VPCOMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMWri, X86_INS_VPCOM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCOMWri_alt, X86_INS_VPCOMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ128rm, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ128rmb, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ128rmbk, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ128rmbkz, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ128rmk, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ128rmkz, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ128rr, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ128rrk, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ128rrkz, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ256rm, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ256rmb, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ256rmbk, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ256rmbkz, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ256rmk, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ256rmkz, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ256rr, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ256rrk, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZ256rrkz, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZrm, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZrmb, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZrmbk, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZrmbkz, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZrmk, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZrmkz, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZrr, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZrrk, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTDZrrkz, X86_INS_VPCONFLICTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ128rm, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ128rmb, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ128rmbk, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ128rmbkz, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ128rmk, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ128rmkz, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ128rr, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ128rrk, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ128rrkz, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ256rm, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ256rmb, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ256rmbk, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ256rmbkz, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ256rmk, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ256rmkz, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ256rr, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ256rrk, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZ256rrkz, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZrm, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZrmb, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZrmbk, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZrmbkz, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZrmk, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZrmkz, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZrr, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZrrk, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPCONFLICTQZrrkz, X86_INS_VPCONFLICTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ128m, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ128mb, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ128mbk, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ128mbkz, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ128mk, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ128mkz, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ128r, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ128rk, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ128rkz, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ256m, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ256mb, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ256mbk, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ256mbkz, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ256mk, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ256mkz, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ256r, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ256rk, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZ256rkz, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZm, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZmb, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZmbk, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZmbkz, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZmk, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZmkz, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZr, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZrk, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDSZrkz, X86_INS_VPDPBUSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ128m, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ128mb, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ128mbk, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ128mbkz, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ128mk, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ128mkz, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ128r, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ128rk, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ128rkz, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ256m, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ256mb, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ256mbk, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ256mbkz, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ256mk, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ256mkz, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ256r, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ256rk, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZ256rkz, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZm, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZmb, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZmbk, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZmbkz, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZmk, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZmkz, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZr, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZrk, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPBUSDZrkz, X86_INS_VPDPBUSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ128m, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ128mb, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ128mbk, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ128mbkz, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ128mk, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ128mkz, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ128r, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ128rk, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ128rkz, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ256m, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ256mb, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ256mbk, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ256mbkz, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ256mk, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ256mkz, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ256r, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ256rk, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZ256rkz, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZm, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZmb, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZmbk, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZmbkz, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZmk, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZmkz, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZr, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZrk, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDSZrkz, X86_INS_VPDPWSSDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ128m, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ128mb, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ128mbk, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ128mbkz, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ128mk, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ128mkz, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ128r, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ128rk, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ128rkz, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ256m, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ256mb, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ256mbk, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ256mbkz, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ256mk, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ256mkz, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ256r, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ256rk, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZ256rkz, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZm, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZmb, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZmbk, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZmbkz, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZmk, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZmkz, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZr, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZrk, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPDPWSSDZrkz, X86_INS_VPDPWSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERM2F128rm, X86_INS_VPERM2F128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERM2F128rr, X86_INS_VPERM2F128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERM2I128rm, X86_INS_VPERM2I128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERM2I128rr, X86_INS_VPERM2I128, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZ128rm, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZ128rmk, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZ128rmkz, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZ128rr, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZ128rrk, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZ128rrkz, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZ256rm, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZ256rmk, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZ256rmkz, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZ256rr, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZ256rrk, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZ256rrkz, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZrm, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZrmk, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZrmkz, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZrr, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZrrk, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMBZrrkz, X86_INS_VPERMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDYrm, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDYrr, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZ256rm, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZ256rmb, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZ256rmbk, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZ256rmbkz, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZ256rmk, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZ256rmkz, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZ256rr, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZ256rrk, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZ256rrkz, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZrm, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZrmb, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZrmbk, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZrmbkz, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZrmk, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZrmkz, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZrr, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZrrk, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMDZrrkz, X86_INS_VPERMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2B128rm, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2B128rmk, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2B128rmkz, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2B128rr, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2B128rrk, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2B128rrkz, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2B256rm, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2B256rmk, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2B256rmkz, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2B256rr, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2B256rrk, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2B256rrkz, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Brm, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Brmk, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Brmkz, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Brr, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Brrk, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Brrkz, X86_INS_VPERMI2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D128rm, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D128rmb, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D128rmbk, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D128rmbkz, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D128rmk, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D128rmkz, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D128rr, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D128rrk, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D128rrkz, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D256rm, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D256rmb, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D256rmbk, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D256rmbkz, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D256rmk, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D256rmkz, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D256rr, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D256rrk, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2D256rrkz, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Drm, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Drmb, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Drmbk, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Drmbkz, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Drmk, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Drmkz, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Drr, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Drrk, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Drrkz, X86_INS_VPERMI2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD128rm, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD128rmb, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD128rmbk, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD128rmbkz, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD128rmk, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD128rmkz, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD128rr, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD128rrk, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD128rrkz, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD256rm, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD256rmb, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD256rmbk, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD256rmbkz, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD256rmk, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD256rmkz, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD256rr, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD256rrk, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PD256rrkz, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PDrm, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PDrmb, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PDrmbk, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PDrmbkz, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PDrmk, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PDrmkz, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PDrr, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PDrrk, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PDrrkz, X86_INS_VPERMI2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS128rm, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS128rmb, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS128rmbk, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS128rmbkz, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS128rmk, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS128rmkz, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS128rr, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS128rrk, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS128rrkz, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS256rm, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS256rmb, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS256rmbk, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS256rmbkz, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS256rmk, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS256rmkz, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS256rr, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS256rrk, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PS256rrkz, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PSrm, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PSrmb, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PSrmbk, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PSrmbkz, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PSrmk, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PSrmkz, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PSrr, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PSrrk, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2PSrrkz, X86_INS_VPERMI2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q128rm, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q128rmb, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q128rmbk, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q128rmbkz, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q128rmk, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q128rmkz, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q128rr, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q128rrk, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q128rrkz, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q256rm, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q256rmb, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q256rmbk, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q256rmbkz, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q256rmk, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q256rmkz, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q256rr, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q256rrk, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Q256rrkz, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Qrm, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Qrmb, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Qrmbk, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Qrmbkz, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Qrmk, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Qrmkz, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Qrr, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Qrrk, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Qrrkz, X86_INS_VPERMI2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2W128rm, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2W128rmk, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2W128rmkz, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2W128rr, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2W128rrk, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2W128rrkz, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2W256rm, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2W256rmk, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2W256rmkz, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2W256rr, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2W256rrk, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2W256rrkz, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Wrm, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Wrmk, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Wrmkz, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Wrr, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Wrrk, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMI2Wrrkz, X86_INS_VPERMI2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PDYmr, X86_INS_VPERMIL2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PDYrm, X86_INS_VPERMIL2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PDYrr, X86_INS_VPERMIL2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PDYrr_REV, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PDmr, X86_INS_VPERMIL2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PDrm, X86_INS_VPERMIL2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PDrr, X86_INS_VPERMIL2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PDrr_REV, X86_INS_VPERMIL2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PSYmr, X86_INS_VPERMIL2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PSYrm, X86_INS_VPERMIL2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PSYrr, X86_INS_VPERMIL2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PSYrr_REV, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PSmr, X86_INS_VPERMIL2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PSrm, X86_INS_VPERMIL2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PSrr, X86_INS_VPERMIL2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMIL2PSrr_REV, X86_INS_VPERMIL2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDYmi, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDYri, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDYrm, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDYrr, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128mbi, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128mbik, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128mbikz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128mi, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128mik, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128mikz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128ri, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128rik, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128rikz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128rm, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128rmb, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128rmbk, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128rmbkz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128rmk, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128rmkz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128rr, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128rrk, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ128rrkz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256mbi, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256mbik, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256mbikz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256mi, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256mik, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256mikz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256ri, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256rik, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256rikz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256rm, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256rmb, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256rmbk, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256rmbkz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256rmk, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256rmkz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256rr, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256rrk, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZ256rrkz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZmbi, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZmbik, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZmbikz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZmi, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZmik, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZmikz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZri, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZrik, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZrikz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZrm, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZrmb, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZrmbk, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZrmbkz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZrmk, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZrmkz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZrr, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZrrk, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDZrrkz, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDmi, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDri, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDrm, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPDrr, X86_INS_VPERMILPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSYmi, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSYri, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSYrm, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSYrr, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128mbi, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128mbik, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128mbikz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128mi, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128mik, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128mikz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128ri, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128rik, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128rikz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128rm, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128rmb, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128rmbk, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128rmbkz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128rmk, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128rmkz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128rr, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128rrk, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ128rrkz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256mbi, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256mbik, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256mbikz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256mi, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256mik, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256mikz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256ri, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256rik, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256rikz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256rm, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256rmb, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256rmbk, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256rmbkz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256rmk, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256rmkz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256rr, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256rrk, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZ256rrkz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZmbi, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZmbik, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZmbikz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZmi, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZmik, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZmikz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZri, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZrik, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZrikz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZrm, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZrmb, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZrmbk, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZrmbkz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZrmk, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZrmkz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZrr, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZrrk, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSZrrkz, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSmi, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSri, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSrm, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMILPSrr, X86_INS_VPERMILPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDYmi, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDYri, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256mbi, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256mbik, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256mbikz, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256mi, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256mik, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256mikz, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256ri, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256rik, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256rikz, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256rm, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256rmb, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256rmbk, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256rmbkz, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256rmk, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256rmkz, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256rr, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256rrk, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZ256rrkz, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZmbi, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZmbik, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZmbikz, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZmi, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZmik, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZmikz, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZri, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZrik, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZrikz, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZrm, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZrmb, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZrmbk, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZrmbkz, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZrmk, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZrmkz, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZrr, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZrrk, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPDZrrkz, X86_INS_VPERMPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSYrm, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSYrr, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZ256rm, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZ256rmb, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZ256rmbk, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZ256rmbkz, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZ256rmk, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZ256rmkz, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZ256rr, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZ256rrk, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZ256rrkz, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZrm, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZrmb, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZrmbk, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZrmbkz, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZrmk, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZrmkz, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZrr, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZrrk, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMPSZrrkz, X86_INS_VPERMPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQYmi, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQYri, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256mbi, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256mbik, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256mbikz, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256mi, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256mik, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256mikz, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256ri, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256rik, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256rikz, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256rm, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256rmb, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256rmbk, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256rmbkz, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256rmk, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256rmkz, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256rr, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256rrk, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZ256rrkz, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZmbi, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZmbik, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZmbikz, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZmi, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZmik, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZmikz, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZri, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZrik, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZrikz, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZrm, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZrmb, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZrmbk, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZrmbkz, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZrmk, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZrmkz, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZrr, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZrrk, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMQZrrkz, X86_INS_VPERMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2B128rm, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2B128rmk, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2B128rmkz, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2B128rr, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2B128rrk, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2B128rrkz, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2B256rm, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2B256rmk, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2B256rmkz, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2B256rr, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2B256rrk, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2B256rrkz, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Brm, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Brmk, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Brmkz, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Brr, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Brrk, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Brrkz, X86_INS_VPERMT2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D128rm, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D128rmb, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D128rmbk, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D128rmbkz, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D128rmk, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D128rmkz, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D128rr, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D128rrk, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D128rrkz, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D256rm, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D256rmb, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D256rmbk, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D256rmbkz, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D256rmk, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D256rmkz, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D256rr, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D256rrk, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2D256rrkz, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Drm, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Drmb, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Drmbk, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Drmbkz, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Drmk, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Drmkz, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Drr, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Drrk, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Drrkz, X86_INS_VPERMT2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD128rm, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD128rmb, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD128rmbk, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD128rmbkz, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD128rmk, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD128rmkz, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD128rr, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD128rrk, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD128rrkz, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD256rm, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD256rmb, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD256rmbk, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD256rmbkz, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD256rmk, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD256rmkz, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD256rr, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD256rrk, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PD256rrkz, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PDrm, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PDrmb, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PDrmbk, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PDrmbkz, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PDrmk, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PDrmkz, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PDrr, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PDrrk, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PDrrkz, X86_INS_VPERMT2PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS128rm, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS128rmb, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS128rmbk, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS128rmbkz, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS128rmk, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS128rmkz, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS128rr, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS128rrk, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS128rrkz, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS256rm, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS256rmb, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS256rmbk, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS256rmbkz, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS256rmk, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS256rmkz, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS256rr, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS256rrk, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PS256rrkz, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PSrm, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PSrmb, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PSrmbk, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PSrmbkz, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PSrmk, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PSrmkz, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PSrr, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PSrrk, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2PSrrkz, X86_INS_VPERMT2PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q128rm, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q128rmb, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q128rmbk, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q128rmbkz, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q128rmk, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q128rmkz, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q128rr, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q128rrk, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q128rrkz, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q256rm, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q256rmb, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q256rmbk, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q256rmbkz, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q256rmk, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q256rmkz, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q256rr, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q256rrk, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Q256rrkz, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Qrm, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Qrmb, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Qrmbk, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Qrmbkz, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Qrmk, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Qrmkz, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Qrr, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Qrrk, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Qrrkz, X86_INS_VPERMT2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2W128rm, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2W128rmk, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2W128rmkz, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2W128rr, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2W128rrk, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2W128rrkz, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2W256rm, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2W256rmk, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2W256rmkz, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2W256rr, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2W256rrk, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2W256rrkz, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Wrm, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Wrmk, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Wrmkz, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Wrr, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Wrrk, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMT2Wrrkz, X86_INS_VPERMT2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZ128rm, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZ128rmk, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZ128rmkz, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZ128rr, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZ128rrk, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZ128rrkz, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZ256rm, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZ256rmk, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZ256rmkz, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZ256rr, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZ256rrk, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZ256rrkz, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZrm, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZrmk, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZrmkz, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZrr, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZrrk, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPERMWZrrkz, X86_INS_VPERMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZ128rm, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZ128rmk, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZ128rmkz, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZ128rr, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZ128rrk, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZ128rrkz, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZ256rm, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZ256rmk, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZ256rmkz, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZ256rr, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZ256rrk, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZ256rrkz, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZrm, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZrmk, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZrmkz, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZrr, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZrrk, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDBZrrkz, X86_INS_VPEXPANDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZ128rm, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZ128rmk, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZ128rmkz, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZ128rr, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZ128rrk, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZ128rrkz, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZ256rm, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZ256rmk, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZ256rmkz, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZ256rr, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZ256rrk, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZ256rrkz, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZrm, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZrmk, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZrmkz, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZrr, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZrrk, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDDZrrkz, X86_INS_VPEXPANDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZ128rm, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZ128rmk, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZ128rmkz, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZ128rr, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZ128rrk, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZ128rrkz, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZ256rm, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZ256rmk, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZ256rmkz, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZ256rr, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZ256rrk, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZ256rrkz, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZrm, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZrmk, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZrmkz, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZrr, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZrrk, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDQZrrkz, X86_INS_VPEXPANDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZ128rm, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZ128rmk, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZ128rmkz, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZ128rr, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZ128rrk, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZ128rrkz, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZ256rm, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZ256rmk, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZ256rmkz, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZ256rr, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZ256rrk, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZ256rrkz, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZrm, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZrmk, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZrmkz, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZrr, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZrrk, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXPANDWZrrkz, X86_INS_VPEXPANDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRBZmr, X86_INS_VPEXTRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRBZrr, X86_INS_VPEXTRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRBmr, X86_INS_VPEXTRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRBrr, X86_INS_VPEXTRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRDZmr, X86_INS_VPEXTRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRDZrr, X86_INS_VPEXTRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRDmr, X86_INS_VPEXTRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRDrr, X86_INS_VPEXTRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRQZmr, X86_INS_VPEXTRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRQZrr, X86_INS_VPEXTRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRQmr, X86_INS_VPEXTRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRQrr, X86_INS_VPEXTRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRWZmr, X86_INS_VPEXTRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRWZrr, X86_INS_VPEXTRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRWZrr_REV, X86_INS_VPEXTRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRWmr, X86_INS_VPEXTRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRWrr, X86_INS_VPEXTRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPEXTRWrr_REV, X86_INS_VPEXTRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERDDYrm, X86_INS_VPGATHERDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERDDZ128rm, X86_INS_VPGATHERDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERDDZ256rm, X86_INS_VPGATHERDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERDDZrm, X86_INS_VPGATHERDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERDDrm, X86_INS_VPGATHERDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERDQYrm, X86_INS_VPGATHERDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERDQZ128rm, X86_INS_VPGATHERDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERDQZ256rm, X86_INS_VPGATHERDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERDQZrm, X86_INS_VPGATHERDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERDQrm, X86_INS_VPGATHERDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERQDYrm, X86_INS_VPGATHERQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERQDZ128rm, X86_INS_VPGATHERQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERQDZ256rm, X86_INS_VPGATHERQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERQDZrm, X86_INS_VPGATHERQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERQDrm, X86_INS_VPGATHERQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERQQYrm, X86_INS_VPGATHERQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERQQZ128rm, X86_INS_VPGATHERQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERQQZ256rm, X86_INS_VPGATHERQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERQQZrm, X86_INS_VPGATHERQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPGATHERQQrm, X86_INS_VPGATHERQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDBDrm, X86_INS_VPHADDBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDBDrr, X86_INS_VPHADDBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDBQrm, X86_INS_VPHADDBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDBQrr, X86_INS_VPHADDBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDBWrm, X86_INS_VPHADDBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDBWrr, X86_INS_VPHADDBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDDQrm, X86_INS_VPHADDDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDDQrr, X86_INS_VPHADDDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDDYrm, X86_INS_VPHADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDDYrr, X86_INS_VPHADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDDrm, X86_INS_VPHADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDDrr, X86_INS_VPHADDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDSWYrm, X86_INS_VPHADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDSWYrr, X86_INS_VPHADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDSWrm, X86_INS_VPHADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDSWrr, X86_INS_VPHADDSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDUBDrm, X86_INS_VPHADDUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDUBDrr, X86_INS_VPHADDUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDUBQrm, X86_INS_VPHADDUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDUBQrr, X86_INS_VPHADDUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDUBWrm, X86_INS_VPHADDUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDUBWrr, X86_INS_VPHADDUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDUDQrm, X86_INS_VPHADDUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDUDQrr, X86_INS_VPHADDUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDUWDrm, X86_INS_VPHADDUWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDUWDrr, X86_INS_VPHADDUWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDUWQrm, X86_INS_VPHADDUWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDUWQrr, X86_INS_VPHADDUWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDWDrm, X86_INS_VPHADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDWDrr, X86_INS_VPHADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDWQrm, X86_INS_VPHADDWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDWQrr, X86_INS_VPHADDWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDWYrm, X86_INS_VPHADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDWYrr, X86_INS_VPHADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDWrm, X86_INS_VPHADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHADDWrr, X86_INS_VPHADDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHMINPOSUWrm, X86_INS_VPHMINPOSUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPHMINPOSUWrr, X86_INS_VPHMINPOSUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBBWrm, X86_INS_VPHSUBBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBBWrr, X86_INS_VPHSUBBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBDQrm, X86_INS_VPHSUBDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBDQrr, X86_INS_VPHSUBDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBDYrm, X86_INS_VPHSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBDYrr, X86_INS_VPHSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBDrm, X86_INS_VPHSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBDrr, X86_INS_VPHSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBSWYrm, X86_INS_VPHSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBSWYrr, X86_INS_VPHSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBSWrm, X86_INS_VPHSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBSWrr, X86_INS_VPHSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBWDrm, X86_INS_VPHSUBWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBWDrr, X86_INS_VPHSUBWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBWYrm, X86_INS_VPHSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBWYrr, X86_INS_VPHSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBWrm, X86_INS_VPHSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPHSUBWrr, X86_INS_VPHSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRBZrm, X86_INS_VPINSRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRBZrr, X86_INS_VPINSRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRBrm, X86_INS_VPINSRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRBrr, X86_INS_VPINSRB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRDZrm, X86_INS_VPINSRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRDZrr, X86_INS_VPINSRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRDrm, X86_INS_VPINSRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRDrr, X86_INS_VPINSRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRQZrm, X86_INS_VPINSRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRQZrr, X86_INS_VPINSRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRQrm, X86_INS_VPINSRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRQrr, X86_INS_VPINSRQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRWZrm, X86_INS_VPINSRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRWZrr, X86_INS_VPINSRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRWrm, X86_INS_VPINSRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPINSRWrr, X86_INS_VPINSRW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ128rm, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ128rmb, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ128rmbk, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ128rmbkz, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ128rmk, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ128rmkz, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ128rr, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ128rrk, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ128rrkz, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ256rm, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ256rmb, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ256rmbk, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ256rmbkz, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ256rmk, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ256rmkz, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ256rr, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ256rrk, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZ256rrkz, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZrm, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZrmb, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZrmbk, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZrmbkz, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZrmk, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZrmkz, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZrr, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZrrk, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTDZrrkz, X86_INS_VPLZCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ128rm, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ128rmb, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ128rmbk, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ128rmbkz, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ128rmk, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ128rmkz, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ128rr, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ128rrk, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ128rrkz, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ256rm, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ256rmb, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ256rmbk, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ256rmbkz, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ256rmk, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ256rmkz, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ256rr, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ256rrk, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZ256rrkz, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZrm, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZrmb, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZrmbk, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZrmbkz, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZrmk, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZrmkz, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZrr, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZrrk, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPLZCNTQZrrkz, X86_INS_VPLZCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSDDrm, X86_INS_VPMACSDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSDDrr, X86_INS_VPMACSDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSDQHrm, X86_INS_VPMACSDQH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSDQHrr, X86_INS_VPMACSDQH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSDQLrm, X86_INS_VPMACSDQL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSDQLrr, X86_INS_VPMACSDQL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSSDDrm, X86_INS_VPMACSSDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSSDDrr, X86_INS_VPMACSSDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSSDQHrm, X86_INS_VPMACSSDQH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSSDQHrr, X86_INS_VPMACSSDQH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSSDQLrm, X86_INS_VPMACSSDQL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSSDQLrr, X86_INS_VPMACSSDQL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSSWDrm, X86_INS_VPMACSSWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSSWDrr, X86_INS_VPMACSSWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSSWWrm, X86_INS_VPMACSSWW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSSWWrr, X86_INS_VPMACSSWW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSWDrm, X86_INS_VPMACSWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSWDrr, X86_INS_VPMACSWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSWWrm, X86_INS_VPMACSWW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMACSWWrr, X86_INS_VPMACSWW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADCSSWDrm, X86_INS_VPMADCSSWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADCSSWDrr, X86_INS_VPMADCSSWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADCSWDrm, X86_INS_VPMADCSWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADCSWDrr, X86_INS_VPMADCSWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ128m, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ128mb, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ128mbk, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ128mbkz, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ128mk, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ128mkz, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ128r, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ128rk, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ128rkz, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ256m, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ256mb, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ256mbk, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ256mbkz, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ256mk, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ256mkz, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ256r, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ256rk, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZ256rkz, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZm, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZmb, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZmbk, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZmbkz, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZmk, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZmkz, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZr, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZrk, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52HUQZrkz, X86_INS_VPMADD52HUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ128m, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ128mb, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ128mbk, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ128mbkz, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ128mk, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ128mkz, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ128r, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ128rk, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ128rkz, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ256m, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ256mb, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ256mbk, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ256mbkz, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ256mk, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ256mkz, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ256r, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ256rk, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZ256rkz, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZm, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZmb, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZmbk, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZmbkz, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZmk, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZmkz, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZr, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZrk, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADD52LUQZrkz, X86_INS_VPMADD52LUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWYrm, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWYrr, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZ128rm, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZ128rmk, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZ128rmkz, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZ128rr, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZ128rrk, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZ128rrkz, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZ256rm, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZ256rmk, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZ256rmkz, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZ256rr, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZ256rrk, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZ256rrkz, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZrm, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZrmk, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZrmkz, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZrr, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZrrk, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWZrrkz, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWrm, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDUBSWrr, X86_INS_VPMADDUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDYrm, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDYrr, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZ128rm, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZ128rmk, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZ128rmkz, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZ128rr, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZ128rrk, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZ128rrkz, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZ256rm, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZ256rmk, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZ256rmkz, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZ256rr, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZ256rrk, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZ256rrkz, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZrm, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZrmk, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZrmkz, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZrr, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZrrk, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDZrrkz, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDrm, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMADDWDrr, X86_INS_VPMADDWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMASKMOVDYmr, X86_INS_VPMASKMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMASKMOVDYrm, X86_INS_VPMASKMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMASKMOVDmr, X86_INS_VPMASKMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMASKMOVDrm, X86_INS_VPMASKMOVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMASKMOVQYmr, X86_INS_VPMASKMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMASKMOVQYrm, X86_INS_VPMASKMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMASKMOVQmr, X86_INS_VPMASKMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMASKMOVQrm, X86_INS_VPMASKMOVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBYrm, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBYrr, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZ128rm, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZ128rmk, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZ128rmkz, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZ128rr, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZ128rrk, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZ128rrkz, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZ256rm, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZ256rmk, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZ256rmkz, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZ256rr, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZ256rrk, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZ256rrkz, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZrm, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZrmk, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZrmkz, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZrr, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZrrk, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBZrrkz, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBrm, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSBrr, X86_INS_VPMAXSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDYrm, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDYrr, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ128rm, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ128rmb, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ128rmbk, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ128rmbkz, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ128rmk, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ128rmkz, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ128rr, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ128rrk, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ128rrkz, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ256rm, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ256rmb, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ256rmbk, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ256rmbkz, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ256rmk, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ256rmkz, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ256rr, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ256rrk, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZ256rrkz, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZrm, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZrmb, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZrmbk, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZrmbkz, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZrmk, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZrmkz, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZrr, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZrrk, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDZrrkz, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDrm, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSDrr, X86_INS_VPMAXSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ128rm, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ128rmb, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ128rmbk, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ128rmbkz, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ128rmk, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ128rmkz, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ128rr, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ128rrk, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ128rrkz, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ256rm, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ256rmb, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ256rmbk, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ256rmbkz, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ256rmk, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ256rmkz, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ256rr, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ256rrk, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZ256rrkz, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZrm, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZrmb, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZrmbk, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZrmbkz, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZrmk, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZrmkz, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZrr, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZrrk, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSQZrrkz, X86_INS_VPMAXSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWYrm, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWYrr, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZ128rm, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZ128rmk, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZ128rmkz, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZ128rr, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZ128rrk, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZ128rrkz, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZ256rm, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZ256rmk, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZ256rmkz, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZ256rr, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZ256rrk, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZ256rrkz, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZrm, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZrmk, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZrmkz, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZrr, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZrrk, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWZrrkz, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWrm, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXSWrr, X86_INS_VPMAXSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBYrm, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBYrr, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZ128rm, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZ128rmk, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZ128rmkz, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZ128rr, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZ128rrk, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZ128rrkz, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZ256rm, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZ256rmk, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZ256rmkz, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZ256rr, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZ256rrk, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZ256rrkz, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZrm, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZrmk, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZrmkz, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZrr, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZrrk, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBZrrkz, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBrm, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUBrr, X86_INS_VPMAXUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDYrm, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDYrr, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ128rm, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ128rmb, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ128rmbk, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ128rmbkz, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ128rmk, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ128rmkz, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ128rr, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ128rrk, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ128rrkz, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ256rm, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ256rmb, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ256rmbk, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ256rmbkz, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ256rmk, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ256rmkz, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ256rr, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ256rrk, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZ256rrkz, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZrm, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZrmb, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZrmbk, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZrmbkz, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZrmk, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZrmkz, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZrr, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZrrk, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDZrrkz, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDrm, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUDrr, X86_INS_VPMAXUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ128rm, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ128rmb, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ128rmbk, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ128rmbkz, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ128rmk, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ128rmkz, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ128rr, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ128rrk, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ128rrkz, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ256rm, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ256rmb, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ256rmbk, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ256rmbkz, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ256rmk, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ256rmkz, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ256rr, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ256rrk, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZ256rrkz, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZrm, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZrmb, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZrmbk, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZrmbkz, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZrmk, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZrmkz, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZrr, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZrrk, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUQZrrkz, X86_INS_VPMAXUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWYrm, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWYrr, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZ128rm, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZ128rmk, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZ128rmkz, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZ128rr, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZ128rrk, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZ128rrkz, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZ256rm, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZ256rmk, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZ256rmkz, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZ256rr, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZ256rrk, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZ256rrkz, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZrm, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZrmk, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZrmkz, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZrr, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZrrk, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWZrrkz, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWrm, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMAXUWrr, X86_INS_VPMAXUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBYrm, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBYrr, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZ128rm, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZ128rmk, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZ128rmkz, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZ128rr, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZ128rrk, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZ128rrkz, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZ256rm, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZ256rmk, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZ256rmkz, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZ256rr, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZ256rrk, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZ256rrkz, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZrm, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZrmk, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZrmkz, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZrr, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZrrk, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBZrrkz, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBrm, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSBrr, X86_INS_VPMINSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDYrm, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDYrr, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ128rm, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ128rmb, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ128rmbk, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ128rmbkz, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ128rmk, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ128rmkz, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ128rr, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ128rrk, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ128rrkz, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ256rm, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ256rmb, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ256rmbk, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ256rmbkz, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ256rmk, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ256rmkz, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ256rr, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ256rrk, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZ256rrkz, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZrm, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZrmb, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZrmbk, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZrmbkz, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZrmk, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZrmkz, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZrr, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZrrk, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDZrrkz, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDrm, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSDrr, X86_INS_VPMINSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ128rm, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ128rmb, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ128rmbk, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ128rmbkz, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ128rmk, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ128rmkz, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ128rr, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ128rrk, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ128rrkz, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ256rm, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ256rmb, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ256rmbk, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ256rmbkz, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ256rmk, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ256rmkz, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ256rr, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ256rrk, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZ256rrkz, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZrm, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZrmb, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZrmbk, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZrmbkz, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZrmk, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZrmkz, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZrr, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZrrk, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSQZrrkz, X86_INS_VPMINSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWYrm, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWYrr, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZ128rm, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZ128rmk, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZ128rmkz, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZ128rr, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZ128rrk, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZ128rrkz, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZ256rm, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZ256rmk, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZ256rmkz, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZ256rr, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZ256rrk, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZ256rrkz, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZrm, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZrmk, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZrmkz, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZrr, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZrrk, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWZrrkz, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWrm, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINSWrr, X86_INS_VPMINSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBYrm, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBYrr, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZ128rm, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZ128rmk, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZ128rmkz, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZ128rr, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZ128rrk, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZ128rrkz, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZ256rm, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZ256rmk, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZ256rmkz, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZ256rr, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZ256rrk, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZ256rrkz, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZrm, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZrmk, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZrmkz, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZrr, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZrrk, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBZrrkz, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBrm, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUBrr, X86_INS_VPMINUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDYrm, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDYrr, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ128rm, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ128rmb, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ128rmbk, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ128rmbkz, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ128rmk, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ128rmkz, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ128rr, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ128rrk, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ128rrkz, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ256rm, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ256rmb, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ256rmbk, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ256rmbkz, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ256rmk, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ256rmkz, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ256rr, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ256rrk, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZ256rrkz, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZrm, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZrmb, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZrmbk, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZrmbkz, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZrmk, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZrmkz, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZrr, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZrrk, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDZrrkz, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDrm, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUDrr, X86_INS_VPMINUD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ128rm, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ128rmb, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ128rmbk, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ128rmbkz, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ128rmk, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ128rmkz, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ128rr, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ128rrk, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ128rrkz, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ256rm, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ256rmb, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ256rmbk, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ256rmbkz, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ256rmk, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ256rmkz, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ256rr, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ256rrk, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZ256rrkz, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZrm, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZrmb, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZrmbk, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZrmbkz, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZrmk, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZrmkz, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZrr, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZrrk, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUQZrrkz, X86_INS_VPMINUQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWYrm, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWYrr, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZ128rm, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZ128rmk, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZ128rmkz, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZ128rr, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZ128rrk, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZ128rrkz, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZ256rm, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZ256rmk, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZ256rmkz, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZ256rr, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZ256rrk, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZ256rrkz, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZrm, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZrmk, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZrmkz, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZrr, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZrrk, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWZrrkz, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWrm, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMINUWrr, X86_INS_VPMINUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVB2MZ128rr, X86_INS_VPMOVB2M, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVB2MZ256rr, X86_INS_VPMOVB2M, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVB2MZrr, X86_INS_VPMOVB2M, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVD2MZ128rr, X86_INS_VPMOVD2M, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVD2MZ256rr, X86_INS_VPMOVD2M, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVD2MZrr, X86_INS_VPMOVD2M, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZ128mr, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZ128mrk, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZ128rr, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZ128rrk, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZ128rrkz, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZ256mr, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZ256mrk, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZ256rr, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZ256rrk, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZ256rrkz, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZmr, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZmrk, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZrr, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZrrk, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDBZrrkz, X86_INS_VPMOVDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZ128mr, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZ128mrk, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZ128rr, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZ128rrk, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZ128rrkz, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZ256mr, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZ256mrk, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZ256rr, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZ256rrk, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZ256rrkz, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZmr, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZmrk, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZrr, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZrrk, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVDWZrrkz, X86_INS_VPMOVDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVM2BZ128rr, X86_INS_VPMOVM2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVM2BZ256rr, X86_INS_VPMOVM2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVM2BZrr, X86_INS_VPMOVM2B, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVM2DZ128rr, X86_INS_VPMOVM2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVM2DZ256rr, X86_INS_VPMOVM2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVM2DZrr, X86_INS_VPMOVM2D, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVM2QZ128rr, X86_INS_VPMOVM2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVM2QZ256rr, X86_INS_VPMOVM2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVM2QZrr, X86_INS_VPMOVM2Q, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVM2WZ128rr, X86_INS_VPMOVM2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVM2WZ256rr, X86_INS_VPMOVM2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVM2WZrr, X86_INS_VPMOVM2W, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVMSKBYrr, X86_INS_VPMOVMSKB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVMSKBrr, X86_INS_VPMOVMSKB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQ2MZ128rr, X86_INS_VPMOVQ2M, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQ2MZ256rr, X86_INS_VPMOVQ2M, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQ2MZrr, X86_INS_VPMOVQ2M, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZ128mr, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZ128mrk, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZ128rr, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZ128rrk, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZ128rrkz, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZ256mr, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZ256mrk, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZ256rr, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZ256rrk, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZ256rrkz, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZmr, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZmrk, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZrr, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZrrk, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQBZrrkz, X86_INS_VPMOVQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZ128mr, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZ128mrk, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZ128rr, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZ128rrk, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZ128rrkz, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZ256mr, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZ256mrk, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZ256rr, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZ256rrk, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZ256rrkz, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZmr, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZmrk, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZrr, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZrrk, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQDZrrkz, X86_INS_VPMOVQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZ128mr, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZ128mrk, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZ128rr, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZ128rrk, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZ128rrkz, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZ256mr, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZ256mrk, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZ256rr, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZ256rrk, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZ256rrkz, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZmr, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZmrk, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZrr, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZrrk, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVQWZrrkz, X86_INS_VPMOVQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZ128mr, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZ128mrk, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZ128rr, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZ128rrk, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZ128rrkz, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZ256mr, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZ256mrk, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZ256rr, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZ256rrk, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZ256rrkz, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZmr, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZmrk, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZrr, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZrrk, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDBZrrkz, X86_INS_VPMOVSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZ128mr, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZ128mrk, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZ128rr, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZ128rrk, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZ128rrkz, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZ256mr, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZ256mrk, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZ256rr, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZ256rrk, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZ256rrkz, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZmr, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZmrk, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZrr, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZrrk, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSDWZrrkz, X86_INS_VPMOVSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZ128mr, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZ128mrk, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZ128rr, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZ128rrk, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZ128rrkz, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZ256mr, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZ256mrk, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZ256rr, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZ256rrk, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZ256rrkz, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZmr, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZmrk, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZrr, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZrrk, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQBZrrkz, X86_INS_VPMOVSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZ128mr, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZ128mrk, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZ128rr, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZ128rrk, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZ128rrkz, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZ256mr, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZ256mrk, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZ256rr, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZ256rrk, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZ256rrkz, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZmr, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZmrk, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZrr, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZrrk, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQDZrrkz, X86_INS_VPMOVSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZ128mr, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZ128mrk, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZ128rr, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZ128rrk, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZ128rrkz, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZ256mr, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZ256mrk, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZ256rr, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZ256rrk, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZ256rrkz, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZmr, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZmrk, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZrr, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZrrk, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSQWZrrkz, X86_INS_VPMOVSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZ128mr, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZ128mrk, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZ128rr, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZ128rrk, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZ128rrkz, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZ256mr, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZ256mrk, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZ256rr, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZ256rrk, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZ256rrkz, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZmr, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZmrk, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZrr, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZrrk, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSWBZrrkz, X86_INS_VPMOVSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDYrm, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDYrr, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZ128rm, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZ128rmk, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZ128rmkz, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZ128rr, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZ128rrk, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZ128rrkz, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZ256rm, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZ256rmk, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZ256rmkz, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZ256rr, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZ256rrk, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZ256rrkz, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZrm, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZrmk, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZrmkz, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZrr, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZrrk, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDZrrkz, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDrm, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBDrr, X86_INS_VPMOVSXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQYrm, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQYrr, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZ128rm, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZ128rmk, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZ128rmkz, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZ128rr, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZ128rrk, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZ128rrkz, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZ256rm, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZ256rmk, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZ256rmkz, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZ256rr, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZ256rrk, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZ256rrkz, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZrm, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZrmk, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZrmkz, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZrr, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZrrk, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQZrrkz, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQrm, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBQrr, X86_INS_VPMOVSXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWYrm, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWYrr, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZ128rm, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZ128rmk, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZ128rmkz, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZ128rr, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZ128rrk, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZ128rrkz, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZ256rm, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZ256rmk, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZ256rmkz, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZ256rr, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZ256rrk, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZ256rrkz, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZrm, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZrmk, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZrmkz, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZrr, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZrrk, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWZrrkz, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWrm, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXBWrr, X86_INS_VPMOVSXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQYrm, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQYrr, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZ128rm, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZ128rmk, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZ128rmkz, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZ128rr, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZ128rrk, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZ128rrkz, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZ256rm, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZ256rmk, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZ256rmkz, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZ256rr, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZ256rrk, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZ256rrkz, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZrm, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZrmk, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZrmkz, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZrr, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZrrk, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQZrrkz, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQrm, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXDQrr, X86_INS_VPMOVSXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDYrm, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDYrr, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZ128rm, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZ128rmk, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZ128rmkz, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZ128rr, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZ128rrk, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZ128rrkz, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZ256rm, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZ256rmk, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZ256rmkz, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZ256rr, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZ256rrk, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZ256rrkz, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZrm, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZrmk, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZrmkz, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZrr, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZrrk, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDZrrkz, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDrm, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWDrr, X86_INS_VPMOVSXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQYrm, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQYrr, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZ128rm, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZ128rmk, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZ128rmkz, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZ128rr, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZ128rrk, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZ128rrkz, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZ256rm, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZ256rmk, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZ256rmkz, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZ256rr, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZ256rrk, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZ256rrkz, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZrm, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZrmk, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZrmkz, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZrr, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZrrk, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQZrrkz, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQrm, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVSXWQrr, X86_INS_VPMOVSXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZ128mr, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZ128mrk, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZ128rr, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZ128rrk, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZ128rrkz, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZ256mr, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZ256mrk, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZ256rr, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZ256rrk, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZ256rrkz, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZmr, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZmrk, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZrr, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZrrk, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDBZrrkz, X86_INS_VPMOVUSDB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZ128mr, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZ128mrk, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZ128rr, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZ128rrk, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZ128rrkz, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZ256mr, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZ256mrk, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZ256rr, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZ256rrk, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZ256rrkz, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZmr, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZmrk, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZrr, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZrrk, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSDWZrrkz, X86_INS_VPMOVUSDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZ128mr, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZ128mrk, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZ128rr, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZ128rrk, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZ128rrkz, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZ256mr, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZ256mrk, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZ256rr, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZ256rrk, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZ256rrkz, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZmr, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZmrk, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZrr, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZrrk, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQBZrrkz, X86_INS_VPMOVUSQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZ128mr, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZ128mrk, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZ128rr, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZ128rrk, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZ128rrkz, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZ256mr, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZ256mrk, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZ256rr, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZ256rrk, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZ256rrkz, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZmr, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZmrk, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZrr, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZrrk, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQDZrrkz, X86_INS_VPMOVUSQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZ128mr, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZ128mrk, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZ128rr, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZ128rrk, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZ128rrkz, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZ256mr, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZ256mrk, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZ256rr, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZ256rrk, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZ256rrkz, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZmr, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZmrk, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZrr, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZrrk, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSQWZrrkz, X86_INS_VPMOVUSQW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZ128mr, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZ128mrk, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZ128rr, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZ128rrk, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZ128rrkz, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZ256mr, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZ256mrk, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZ256rr, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZ256rrk, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZ256rrkz, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZmr, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZmrk, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZrr, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZrrk, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVUSWBZrrkz, X86_INS_VPMOVUSWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVW2MZ128rr, X86_INS_VPMOVW2M, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVW2MZ256rr, X86_INS_VPMOVW2M, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVW2MZrr, X86_INS_VPMOVW2M, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZ128mr, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZ128mrk, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZ128rr, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZ128rrk, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZ128rrkz, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZ256mr, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZ256mrk, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZ256rr, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZ256rrk, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZ256rrkz, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZmr, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZmrk, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZrr, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZrrk, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVWBZrrkz, X86_INS_VPMOVWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDYrm, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDYrr, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZ128rm, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZ128rmk, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZ128rmkz, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZ128rr, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZ128rrk, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZ128rrkz, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZ256rm, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZ256rmk, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZ256rmkz, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZ256rr, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZ256rrk, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZ256rrkz, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZrm, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZrmk, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZrmkz, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZrr, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZrrk, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDZrrkz, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDrm, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBDrr, X86_INS_VPMOVZXBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQYrm, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQYrr, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZ128rm, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZ128rmk, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZ128rmkz, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZ128rr, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZ128rrk, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZ128rrkz, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZ256rm, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZ256rmk, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZ256rmkz, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZ256rr, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZ256rrk, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZ256rrkz, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZrm, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZrmk, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZrmkz, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZrr, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZrrk, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQZrrkz, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQrm, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBQrr, X86_INS_VPMOVZXBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWYrm, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWYrr, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZ128rm, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZ128rmk, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZ128rmkz, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZ128rr, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZ128rrk, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZ128rrkz, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZ256rm, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZ256rmk, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZ256rmkz, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZ256rr, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZ256rrk, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZ256rrkz, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZrm, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZrmk, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZrmkz, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZrr, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZrrk, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWZrrkz, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWrm, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXBWrr, X86_INS_VPMOVZXBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQYrm, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQYrr, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZ128rm, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZ128rmk, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZ128rmkz, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZ128rr, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZ128rrk, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZ128rrkz, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZ256rm, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZ256rmk, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZ256rmkz, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZ256rr, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZ256rrk, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZ256rrkz, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZrm, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZrmk, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZrmkz, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZrr, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZrrk, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQZrrkz, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQrm, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXDQrr, X86_INS_VPMOVZXDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDYrm, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDYrr, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZ128rm, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZ128rmk, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZ128rmkz, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZ128rr, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZ128rrk, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZ128rrkz, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZ256rm, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZ256rmk, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZ256rmkz, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZ256rr, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZ256rrk, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZ256rrkz, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZrm, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZrmk, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZrmkz, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZrr, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZrrk, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDZrrkz, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDrm, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWDrr, X86_INS_VPMOVZXWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQYrm, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQYrr, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZ128rm, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZ128rmk, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZ128rmkz, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZ128rr, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZ128rrk, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZ128rrkz, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZ256rm, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZ256rmk, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZ256rmkz, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZ256rr, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZ256rrk, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZ256rrkz, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZrm, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZrmk, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZrmkz, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZrr, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZrrk, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQZrrkz, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQrm, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMOVZXWQrr, X86_INS_VPMOVZXWQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQYrm, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQYrr, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ128rm, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ128rmb, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ128rmbk, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ128rmbkz, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ128rmk, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ128rmkz, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ128rr, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ128rrk, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ128rrkz, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ256rm, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ256rmb, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ256rmbk, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ256rmbkz, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ256rmk, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ256rmkz, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ256rr, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ256rrk, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZ256rrkz, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZrm, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZrmb, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZrmbk, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZrmbkz, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZrmk, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZrmkz, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZrr, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZrrk, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQZrrkz, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQrm, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULDQrr, X86_INS_VPMULDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWYrm, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWYrr, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZ128rm, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZ128rmk, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZ128rmkz, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZ128rr, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZ128rrk, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZ128rrkz, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZ256rm, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZ256rmk, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZ256rmkz, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZ256rr, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZ256rrk, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZ256rrkz, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZrm, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZrmk, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZrmkz, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZrr, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZrrk, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWZrrkz, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWrm, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHRSWrr, X86_INS_VPMULHRSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWYrm, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWYrr, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZ128rm, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZ128rmk, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZ128rmkz, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZ128rr, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZ128rrk, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZ128rrkz, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZ256rm, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZ256rmk, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZ256rmkz, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZ256rr, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZ256rrk, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZ256rrkz, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZrm, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZrmk, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZrmkz, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZrr, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZrrk, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWZrrkz, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWrm, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHUWrr, X86_INS_VPMULHUW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWYrm, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWYrr, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZ128rm, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZ128rmk, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZ128rmkz, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZ128rr, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZ128rrk, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZ128rrkz, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZ256rm, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZ256rmk, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZ256rmkz, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZ256rr, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZ256rrk, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZ256rrkz, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZrm, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZrmk, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZrmkz, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZrr, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZrrk, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWZrrkz, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWrm, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULHWrr, X86_INS_VPMULHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDYrm, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDYrr, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ128rm, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ128rmb, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ128rmbk, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ128rmbkz, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ128rmk, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ128rmkz, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ128rr, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ128rrk, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ128rrkz, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ256rm, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ256rmb, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ256rmbk, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ256rmbkz, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ256rmk, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ256rmkz, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ256rr, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ256rrk, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZ256rrkz, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZrm, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZrmb, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZrmbk, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZrmbkz, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZrmk, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZrmkz, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZrr, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZrrk, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDZrrkz, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDrm, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLDrr, X86_INS_VPMULLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ128rm, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ128rmb, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ128rmbk, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ128rmbkz, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ128rmk, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ128rmkz, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ128rr, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ128rrk, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ128rrkz, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ256rm, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ256rmb, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ256rmbk, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ256rmbkz, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ256rmk, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ256rmkz, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ256rr, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ256rrk, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZ256rrkz, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZrm, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZrmb, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZrmbk, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZrmbkz, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZrmk, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZrmkz, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZrr, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZrrk, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLQZrrkz, X86_INS_VPMULLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWYrm, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWYrr, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZ128rm, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZ128rmk, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZ128rmkz, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZ128rr, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZ128rrk, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZ128rrkz, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZ256rm, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZ256rmk, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZ256rmkz, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZ256rr, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZ256rrk, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZ256rrkz, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZrm, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZrmk, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZrmkz, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZrr, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZrrk, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWZrrkz, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWrm, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULLWrr, X86_INS_VPMULLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ128rm, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ128rmb, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ128rmbk, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ128rmbkz, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ128rmk, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ128rmkz, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ128rr, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ128rrk, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ128rrkz, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ256rm, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ256rmb, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ256rmbk, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ256rmbkz, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ256rmk, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ256rmkz, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ256rr, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ256rrk, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZ256rrkz, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZrm, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZrmb, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZrmbk, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZrmbkz, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZrmk, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZrmkz, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZrr, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZrrk, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULTISHIFTQBZrrkz, X86_INS_VPMULTISHIFTQB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQYrm, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQYrr, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ128rm, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ128rmb, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ128rmbk, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ128rmbkz, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ128rmk, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ128rmkz, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ128rr, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ128rrk, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ128rrkz, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ256rm, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ256rmb, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ256rmbk, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ256rmbkz, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ256rmk, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ256rmkz, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ256rr, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ256rrk, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZ256rrkz, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZrm, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZrmb, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZrmbk, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZrmbkz, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZrmk, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZrmkz, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZrr, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZrrk, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQZrrkz, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQrm, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPMULUDQrr, X86_INS_VPMULUDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZ128rm, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZ128rmk, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZ128rmkz, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZ128rr, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZ128rrk, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZ128rrkz, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZ256rm, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZ256rmk, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZ256rmkz, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZ256rr, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZ256rrk, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZ256rrkz, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZrm, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZrmk, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZrmkz, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZrr, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZrrk, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTBZrrkz, X86_INS_VPOPCNTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ128rm, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ128rmb, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ128rmbk, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ128rmbkz, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ128rmk, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ128rmkz, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ128rr, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ128rrk, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ128rrkz, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ256rm, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ256rmb, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ256rmbk, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ256rmbkz, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ256rmk, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ256rmkz, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ256rr, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ256rrk, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZ256rrkz, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZrm, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZrmb, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZrmbk, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZrmbkz, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZrmk, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZrmkz, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZrr, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZrrk, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTDZrrkz, X86_INS_VPOPCNTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ128rm, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ128rmb, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ128rmbk, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ128rmbkz, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ128rmk, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ128rmkz, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ128rr, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ128rrk, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ128rrkz, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ256rm, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ256rmb, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ256rmbk, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ256rmbkz, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ256rmk, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ256rmkz, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ256rr, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ256rrk, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZ256rrkz, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZrm, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZrmb, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZrmbk, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZrmbkz, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZrmk, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZrmkz, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZrr, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZrrk, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTQZrrkz, X86_INS_VPOPCNTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZ128rm, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZ128rmk, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZ128rmkz, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZ128rr, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZ128rrk, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZ128rrkz, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZ256rm, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZ256rmk, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZ256rmkz, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZ256rr, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZ256rrk, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZ256rrkz, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZrm, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZrmk, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZrmkz, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZrr, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZrrk, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPOPCNTWZrrkz, X86_INS_VPOPCNTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ128rm, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ128rmb, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ128rmbk, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ128rmbkz, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ128rmk, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ128rmkz, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ128rr, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ128rrk, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ128rrkz, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ256rm, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ256rmb, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ256rmbk, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ256rmbkz, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ256rmk, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ256rmkz, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ256rr, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ256rrk, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZ256rrkz, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZrm, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZrmb, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZrmbk, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZrmbkz, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZrmk, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZrmkz, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZrr, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZrrk, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORDZrrkz, X86_INS_VPORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ128rm, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ128rmb, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ128rmbk, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ128rmbkz, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ128rmk, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ128rmkz, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ128rr, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ128rrk, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ128rrkz, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ256rm, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ256rmb, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ256rmbk, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ256rmbkz, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ256rmk, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ256rmkz, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ256rr, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ256rrk, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZ256rrkz, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZrm, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZrmb, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZrmbk, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZrmbkz, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZrmk, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZrmkz, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZrr, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZrrk, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORQZrrkz, X86_INS_VPORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORYrm, X86_INS_VPOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORYrr, X86_INS_VPOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORrm, X86_INS_VPOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPORrr, X86_INS_VPOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPPERMrmr, X86_INS_VPPERM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPPERMrrm, X86_INS_VPPERM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPPERMrrr, X86_INS_VPPERM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPPERMrrr_REV, X86_INS_VPPERM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ128mbi, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ128mbik, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ128mbikz, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ128mi, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ128mik, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ128mikz, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ128ri, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ128rik, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ128rikz, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ256mbi, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ256mbik, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ256mbikz, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ256mi, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ256mik, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ256mikz, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ256ri, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ256rik, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZ256rikz, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZmbi, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZmbik, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZmbikz, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZmi, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZmik, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZmikz, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZri, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZrik, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLDZrikz, X86_INS_VPROLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ128mbi, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ128mbik, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ128mbikz, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ128mi, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ128mik, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ128mikz, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ128ri, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ128rik, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ128rikz, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ256mbi, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ256mbik, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ256mbikz, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ256mi, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ256mik, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ256mikz, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ256ri, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ256rik, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZ256rikz, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZmbi, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZmbik, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZmbikz, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZmi, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZmik, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZmikz, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZri, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZrik, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLQZrikz, X86_INS_VPROLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ128rm, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ128rmb, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ128rmbk, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ128rmbkz, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ128rmk, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ128rmkz, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ128rr, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ128rrk, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ128rrkz, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ256rm, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ256rmb, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ256rmbk, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ256rmbkz, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ256rmk, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ256rmkz, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ256rr, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ256rrk, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZ256rrkz, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZrm, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZrmb, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZrmbk, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZrmbkz, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZrmk, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZrmkz, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZrr, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZrrk, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVDZrrkz, X86_INS_VPROLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ128rm, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ128rmb, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ128rmbk, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ128rmbkz, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ128rmk, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ128rmkz, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ128rr, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ128rrk, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ128rrkz, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ256rm, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ256rmb, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ256rmbk, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ256rmbkz, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ256rmk, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ256rmkz, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ256rr, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ256rrk, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZ256rrkz, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZrm, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZrmb, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZrmbk, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZrmbkz, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZrmk, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZrmkz, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZrr, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZrrk, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROLVQZrrkz, X86_INS_VPROLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ128mbi, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ128mbik, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ128mbikz, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ128mi, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ128mik, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ128mikz, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ128ri, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ128rik, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ128rikz, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ256mbi, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ256mbik, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ256mbikz, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ256mi, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ256mik, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ256mikz, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ256ri, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ256rik, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZ256rikz, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZmbi, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZmbik, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZmbikz, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZmi, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZmik, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZmikz, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZri, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZrik, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORDZrikz, X86_INS_VPRORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ128mbi, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ128mbik, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ128mbikz, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ128mi, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ128mik, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ128mikz, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ128ri, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ128rik, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ128rikz, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ256mbi, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ256mbik, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ256mbikz, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ256mi, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ256mik, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ256mikz, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ256ri, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ256rik, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZ256rikz, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZmbi, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZmbik, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZmbikz, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZmi, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZmik, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZmikz, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZri, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZrik, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORQZrikz, X86_INS_VPRORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ128rm, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ128rmb, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ128rmbk, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ128rmbkz, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ128rmk, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ128rmkz, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ128rr, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ128rrk, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ128rrkz, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ256rm, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ256rmb, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ256rmbk, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ256rmbkz, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ256rmk, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ256rmkz, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ256rr, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ256rrk, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZ256rrkz, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZrm, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZrmb, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZrmbk, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZrmbkz, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZrmk, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZrmkz, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZrr, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZrrk, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVDZrrkz, X86_INS_VPRORVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ128rm, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ128rmb, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ128rmbk, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ128rmbkz, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ128rmk, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ128rmkz, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ128rr, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ128rrk, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ128rrkz, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ256rm, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ256rmb, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ256rmbk, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ256rmbkz, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ256rmk, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ256rmkz, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ256rr, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ256rrk, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZ256rrkz, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZrm, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZrmb, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZrmbk, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZrmbkz, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZrmk, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZrmkz, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZrr, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZrrk, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPRORVQZrrkz, X86_INS_VPRORVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTBmi, X86_INS_VPROTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTBmr, X86_INS_VPROTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTBri, X86_INS_VPROTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTBrm, X86_INS_VPROTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTBrr, X86_INS_VPROTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTBrr_REV, X86_INS_VPROTB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTDmi, X86_INS_VPROTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTDmr, X86_INS_VPROTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTDri, X86_INS_VPROTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTDrm, X86_INS_VPROTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTDrr, X86_INS_VPROTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTDrr_REV, X86_INS_VPROTD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTQmi, X86_INS_VPROTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTQmr, X86_INS_VPROTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTQri, X86_INS_VPROTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTQrm, X86_INS_VPROTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTQrr, X86_INS_VPROTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTQrr_REV, X86_INS_VPROTQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTWmi, X86_INS_VPROTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTWmr, X86_INS_VPROTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTWri, X86_INS_VPROTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTWrm, X86_INS_VPROTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTWrr, X86_INS_VPROTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPROTWrr_REV, X86_INS_VPROTW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSADBWYrm, X86_INS_VPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSADBWYrr, X86_INS_VPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSADBWZ128rm, X86_INS_VPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSADBWZ128rr, X86_INS_VPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSADBWZ256rm, X86_INS_VPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSADBWZ256rr, X86_INS_VPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSADBWZrm, X86_INS_VPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSADBWZrr, X86_INS_VPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSADBWrm, X86_INS_VPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSADBWrr, X86_INS_VPSADBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSCATTERDDZ128mr, X86_INS_VPSCATTERDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSCATTERDDZ256mr, X86_INS_VPSCATTERDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSCATTERDDZmr, X86_INS_VPSCATTERDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSCATTERDQZ128mr, X86_INS_VPSCATTERDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSCATTERDQZ256mr, X86_INS_VPSCATTERDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSCATTERDQZmr, X86_INS_VPSCATTERDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSCATTERQDZ128mr, X86_INS_VPSCATTERQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSCATTERQDZ256mr, X86_INS_VPSCATTERQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSCATTERQDZmr, X86_INS_VPSCATTERQD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSCATTERQQZ128mr, X86_INS_VPSCATTERQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSCATTERQQZ256mr, X86_INS_VPSCATTERQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSCATTERQQZmr, X86_INS_VPSCATTERQQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHABmr, X86_INS_VPSHAB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHABrm, X86_INS_VPSHAB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHABrr, X86_INS_VPSHAB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHABrr_REV, X86_INS_VPSHAB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHADmr, X86_INS_VPSHAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHADrm, X86_INS_VPSHAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHADrr, X86_INS_VPSHAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHADrr_REV, X86_INS_VPSHAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHAQmr, X86_INS_VPSHAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHAQrm, X86_INS_VPSHAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHAQrr, X86_INS_VPSHAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHAQrr_REV, X86_INS_VPSHAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHAWmr, X86_INS_VPSHAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHAWrm, X86_INS_VPSHAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHAWrr, X86_INS_VPSHAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHAWrr_REV, X86_INS_VPSHAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLBmr, X86_INS_VPSHLB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLBrm, X86_INS_VPSHLB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLBrr, X86_INS_VPSHLB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLBrr_REV, X86_INS_VPSHLB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ128rmbi, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ128rmbik, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ128rmbikz, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ128rmi, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ128rmik, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ128rmikz, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ128rri, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ128rrik, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ128rrikz, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ256rmbi, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ256rmbik, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ256rmbikz, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ256rmi, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ256rmik, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ256rmikz, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ256rri, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ256rrik, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZ256rrikz, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZrmbi, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZrmbik, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZrmbikz, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZrmi, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZrmik, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZrmikz, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZrri, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZrrik, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDDZrrikz, X86_INS_VPSHLDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ128rmbi, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ128rmbik, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ128rmbikz, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ128rmi, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ128rmik, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ128rmikz, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ128rri, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ128rrik, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ128rrikz, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ256rmbi, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ256rmbik, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ256rmbikz, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ256rmi, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ256rmik, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ256rmikz, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ256rri, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ256rrik, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZ256rrikz, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZrmbi, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZrmbik, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZrmbikz, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZrmi, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZrmik, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZrmikz, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZrri, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZrrik, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDQZrrikz, X86_INS_VPSHLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ128m, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ128mb, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ128mbk, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ128mbkz, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ128mk, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ128mkz, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ128r, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ128rk, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ128rkz, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ256m, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ256mb, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ256mbk, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ256mbkz, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ256mk, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ256mkz, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ256r, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ256rk, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZ256rkz, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZm, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZmb, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZmbk, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZmbkz, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZmk, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZmkz, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZr, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZrk, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVDZrkz, X86_INS_VPSHLDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ128m, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ128mb, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ128mbk, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ128mbkz, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ128mk, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ128mkz, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ128r, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ128rk, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ128rkz, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ256m, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ256mb, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ256mbk, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ256mbkz, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ256mk, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ256mkz, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ256r, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ256rk, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZ256rkz, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZm, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZmb, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZmbk, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZmbkz, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZmk, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZmkz, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZr, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZrk, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVQZrkz, X86_INS_VPSHLDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZ128m, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZ128mk, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZ128mkz, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZ128r, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZ128rk, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZ128rkz, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZ256m, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZ256mk, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZ256mkz, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZ256r, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZ256rk, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZ256rkz, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZm, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZmk, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZmkz, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZr, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZrk, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDVWZrkz, X86_INS_VPSHLDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZ128rmi, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZ128rmik, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZ128rmikz, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZ128rri, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZ128rrik, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZ128rrikz, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZ256rmi, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZ256rmik, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZ256rmikz, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZ256rri, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZ256rrik, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZ256rrikz, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZrmi, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZrmik, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZrmikz, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZrri, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZrrik, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDWZrrikz, X86_INS_VPSHLDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDmr, X86_INS_VPSHLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDrm, X86_INS_VPSHLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDrr, X86_INS_VPSHLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLDrr_REV, X86_INS_VPSHLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLQmr, X86_INS_VPSHLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLQrm, X86_INS_VPSHLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLQrr, X86_INS_VPSHLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLQrr_REV, X86_INS_VPSHLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLWmr, X86_INS_VPSHLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLWrm, X86_INS_VPSHLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLWrr, X86_INS_VPSHLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHLWrr_REV, X86_INS_VPSHLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ128rmbi, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ128rmbik, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ128rmbikz, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ128rmi, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ128rmik, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ128rmikz, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ128rri, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ128rrik, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ128rrikz, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ256rmbi, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ256rmbik, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ256rmbikz, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ256rmi, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ256rmik, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ256rmikz, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ256rri, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ256rrik, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZ256rrikz, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZrmbi, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZrmbik, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZrmbikz, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZrmi, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZrmik, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZrmikz, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZrri, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZrrik, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDDZrrikz, X86_INS_VPSHRDD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ128rmbi, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ128rmbik, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ128rmbikz, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ128rmi, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ128rmik, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ128rmikz, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ128rri, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ128rrik, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ128rrikz, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ256rmbi, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ256rmbik, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ256rmbikz, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ256rmi, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ256rmik, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ256rmikz, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ256rri, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ256rrik, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZ256rrikz, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZrmbi, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZrmbik, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZrmbikz, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZrmi, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZrmik, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZrmikz, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZrri, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZrrik, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDQZrrikz, X86_INS_VPSHRDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ128m, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ128mb, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ128mbk, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ128mbkz, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ128mk, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ128mkz, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ128r, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ128rk, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ128rkz, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ256m, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ256mb, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ256mbk, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ256mbkz, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ256mk, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ256mkz, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ256r, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ256rk, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZ256rkz, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZm, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZmb, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZmbk, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZmbkz, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZmk, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZmkz, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZr, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZrk, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVDZrkz, X86_INS_VPSHRDVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ128m, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ128mb, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ128mbk, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ128mbkz, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ128mk, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ128mkz, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ128r, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ128rk, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ128rkz, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ256m, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ256mb, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ256mbk, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ256mbkz, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ256mk, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ256mkz, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ256r, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ256rk, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZ256rkz, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZm, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZmb, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZmbk, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZmbkz, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZmk, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZmkz, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZr, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZrk, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVQZrkz, X86_INS_VPSHRDVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZ128m, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZ128mk, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZ128mkz, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZ128r, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZ128rk, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZ128rkz, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZ256m, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZ256mk, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZ256mkz, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZ256r, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZ256rk, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZ256rkz, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZm, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZmk, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZmkz, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZr, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZrk, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDVWZrkz, X86_INS_VPSHRDVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZ128rmi, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZ128rmik, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZ128rmikz, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZ128rri, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZ128rrik, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZ128rrikz, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZ256rmi, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZ256rmik, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZ256rmikz, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZ256rri, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZ256rrik, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZ256rrikz, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZrmi, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZrmik, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZrmikz, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZrri, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZrrik, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHRDWZrrikz, X86_INS_VPSHRDW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBITQMBZ128rm, X86_INS_VPSHUFBITQMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBITQMBZ128rmk, X86_INS_VPSHUFBITQMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBITQMBZ128rr, X86_INS_VPSHUFBITQMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBITQMBZ128rrk, X86_INS_VPSHUFBITQMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBITQMBZ256rm, X86_INS_VPSHUFBITQMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBITQMBZ256rmk, X86_INS_VPSHUFBITQMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBITQMBZ256rr, X86_INS_VPSHUFBITQMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBITQMBZ256rrk, X86_INS_VPSHUFBITQMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBITQMBZrm, X86_INS_VPSHUFBITQMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBITQMBZrmk, X86_INS_VPSHUFBITQMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBITQMBZrr, X86_INS_VPSHUFBITQMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBITQMBZrrk, X86_INS_VPSHUFBITQMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBYrm, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBYrr, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZ128rm, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZ128rmk, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZ128rmkz, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZ128rr, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZ128rrk, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZ128rrkz, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZ256rm, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZ256rmk, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZ256rmkz, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZ256rr, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZ256rrk, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZ256rrkz, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZrm, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZrmk, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZrmkz, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZrr, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZrrk, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBZrrkz, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBrm, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFBrr, X86_INS_VPSHUFB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDYmi, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDYri, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ128mbi, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ128mbik, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ128mbikz, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ128mi, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ128mik, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ128mikz, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ128ri, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ128rik, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ128rikz, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ256mbi, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ256mbik, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ256mbikz, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ256mi, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ256mik, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ256mikz, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ256ri, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ256rik, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZ256rikz, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZmbi, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZmbik, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZmbikz, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZmi, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZmik, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZmikz, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZri, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZrik, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDZrikz, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDmi, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFDri, X86_INS_VPSHUFD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWYmi, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWYri, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZ128mi, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZ128mik, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZ128mikz, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZ128ri, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZ128rik, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZ128rikz, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZ256mi, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZ256mik, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZ256mikz, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZ256ri, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZ256rik, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZ256rikz, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZmi, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZmik, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZmikz, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZri, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZrik, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWZrikz, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWmi, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFHWri, X86_INS_VPSHUFHW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWYmi, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWYri, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZ128mi, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZ128mik, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZ128mikz, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZ128ri, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZ128rik, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZ128rikz, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZ256mi, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZ256mik, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZ256mikz, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZ256ri, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZ256rik, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZ256rikz, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZmi, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZmik, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZmikz, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZri, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZrik, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWZrikz, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWmi, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSHUFLWri, X86_INS_VPSHUFLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSIGNBYrm, X86_INS_VPSIGNB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSIGNBYrr, X86_INS_VPSIGNB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSIGNBrm, X86_INS_VPSIGNB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSIGNBrr, X86_INS_VPSIGNB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSIGNDYrm, X86_INS_VPSIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSIGNDYrr, X86_INS_VPSIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSIGNDrm, X86_INS_VPSIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSIGNDrr, X86_INS_VPSIGND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSIGNWYrm, X86_INS_VPSIGNW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSIGNWYrr, X86_INS_VPSIGNW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSIGNWrm, X86_INS_VPSIGNW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSIGNWrr, X86_INS_VPSIGNW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDQYri, X86_INS_VPSLLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDQZ128rm, X86_INS_VPSLLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDQZ128rr, X86_INS_VPSLLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDQZ256rm, X86_INS_VPSLLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDQZ256rr, X86_INS_VPSLLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDQZrm, X86_INS_VPSLLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDQZrr, X86_INS_VPSLLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDQri, X86_INS_VPSLLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDYri, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDYrm, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDYrr, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128mbi, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128mbik, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128mbikz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128mi, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128mik, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128mikz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128ri, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128rik, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128rikz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128rm, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128rmk, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128rmkz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128rr, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128rrk, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ128rrkz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256mbi, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256mbik, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256mbikz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256mi, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256mik, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256mikz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256ri, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256rik, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256rikz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256rm, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256rmk, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256rmkz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256rr, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256rrk, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZ256rrkz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZmbi, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZmbik, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZmbikz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZmi, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZmik, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZmikz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZri, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZrik, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZrikz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZrm, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZrmk, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZrmkz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZrr, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZrrk, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDZrrkz, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDri, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDrm, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLDrr, X86_INS_VPSLLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQYri, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQYrm, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQYrr, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128mbi, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128mbik, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128mbikz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128mi, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128mik, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128mikz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128ri, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128rik, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128rikz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128rm, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128rmk, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128rmkz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128rr, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128rrk, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ128rrkz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256mbi, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256mbik, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256mbikz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256mi, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256mik, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256mikz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256ri, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256rik, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256rikz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256rm, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256rmk, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256rmkz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256rr, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256rrk, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZ256rrkz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZmbi, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZmbik, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZmbikz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZmi, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZmik, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZmikz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZri, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZrik, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZrikz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZrm, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZrmk, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZrmkz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZrr, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZrrk, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQZrrkz, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQri, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQrm, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLQrr, X86_INS_VPSLLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDYrm, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDYrr, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ128rm, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ128rmb, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ128rmbk, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ128rmbkz, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ128rmk, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ128rmkz, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ128rr, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ128rrk, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ128rrkz, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ256rm, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ256rmb, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ256rmbk, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ256rmbkz, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ256rmk, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ256rmkz, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ256rr, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ256rrk, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZ256rrkz, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZrm, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZrmb, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZrmbk, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZrmbkz, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZrmk, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZrmkz, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZrr, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZrrk, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDZrrkz, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDrm, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVDrr, X86_INS_VPSLLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQYrm, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQYrr, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ128rm, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ128rmb, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ128rmbk, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ128rmbkz, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ128rmk, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ128rmkz, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ128rr, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ128rrk, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ128rrkz, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ256rm, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ256rmb, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ256rmbk, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ256rmbkz, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ256rmk, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ256rmkz, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ256rr, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ256rrk, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZ256rrkz, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZrm, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZrmb, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZrmbk, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZrmbkz, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZrmk, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZrmkz, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZrr, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZrrk, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQZrrkz, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQrm, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVQrr, X86_INS_VPSLLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZ128rm, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZ128rmk, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZ128rmkz, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZ128rr, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZ128rrk, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZ128rrkz, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZ256rm, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZ256rmk, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZ256rmkz, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZ256rr, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZ256rrk, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZ256rrkz, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZrm, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZrmk, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZrmkz, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZrr, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZrrk, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLVWZrrkz, X86_INS_VPSLLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWYri, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWYrm, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWYrr, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ128mi, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ128mik, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ128mikz, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ128ri, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ128rik, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ128rikz, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ128rm, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ128rmk, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ128rmkz, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ128rr, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ128rrk, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ128rrkz, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ256mi, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ256mik, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ256mikz, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ256ri, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ256rik, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ256rikz, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ256rm, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ256rmk, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ256rmkz, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ256rr, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ256rrk, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZ256rrkz, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZmi, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZmik, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZmikz, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZri, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZrik, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZrikz, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZrm, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZrmk, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZrmkz, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZrr, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZrrk, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWZrrkz, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWri, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWrm, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSLLWrr, X86_INS_VPSLLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADYri, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADYrm, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADYrr, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128mbi, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128mbik, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128mbikz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128mi, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128mik, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128mikz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128ri, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128rik, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128rikz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128rm, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128rmk, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128rmkz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128rr, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128rrk, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ128rrkz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256mbi, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256mbik, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256mbikz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256mi, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256mik, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256mikz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256ri, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256rik, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256rikz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256rm, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256rmk, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256rmkz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256rr, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256rrk, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZ256rrkz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZmbi, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZmbik, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZmbikz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZmi, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZmik, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZmikz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZri, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZrik, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZrikz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZrm, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZrmk, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZrmkz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZrr, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZrrk, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADZrrkz, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADri, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADrm, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRADrr, X86_INS_VPSRAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128mbi, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128mbik, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128mbikz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128mi, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128mik, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128mikz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128ri, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128rik, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128rikz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128rm, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128rmk, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128rmkz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128rr, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128rrk, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ128rrkz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256mbi, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256mbik, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256mbikz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256mi, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256mik, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256mikz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256ri, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256rik, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256rikz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256rm, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256rmk, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256rmkz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256rr, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256rrk, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZ256rrkz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZmbi, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZmbik, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZmbikz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZmi, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZmik, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZmikz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZri, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZrik, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZrikz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZrm, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZrmk, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZrmkz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZrr, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZrrk, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAQZrrkz, X86_INS_VPSRAQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDYrm, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDYrr, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ128rm, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ128rmb, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ128rmbk, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ128rmbkz, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ128rmk, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ128rmkz, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ128rr, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ128rrk, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ128rrkz, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ256rm, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ256rmb, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ256rmbk, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ256rmbkz, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ256rmk, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ256rmkz, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ256rr, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ256rrk, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZ256rrkz, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZrm, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZrmb, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZrmbk, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZrmbkz, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZrmk, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZrmkz, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZrr, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZrrk, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDZrrkz, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDrm, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVDrr, X86_INS_VPSRAVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ128rm, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ128rmb, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ128rmbk, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ128rmbkz, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ128rmk, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ128rmkz, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ128rr, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ128rrk, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ128rrkz, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ256rm, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ256rmb, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ256rmbk, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ256rmbkz, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ256rmk, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ256rmkz, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ256rr, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ256rrk, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZ256rrkz, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZrm, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZrmb, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZrmbk, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZrmbkz, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZrmk, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZrmkz, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZrr, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZrrk, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVQZrrkz, X86_INS_VPSRAVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZ128rm, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZ128rmk, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZ128rmkz, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZ128rr, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZ128rrk, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZ128rrkz, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZ256rm, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZ256rmk, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZ256rmkz, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZ256rr, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZ256rrk, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZ256rrkz, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZrm, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZrmk, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZrmkz, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZrr, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZrrk, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAVWZrrkz, X86_INS_VPSRAVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWYri, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWYrm, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWYrr, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ128mi, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ128mik, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ128mikz, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ128ri, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ128rik, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ128rikz, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ128rm, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ128rmk, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ128rmkz, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ128rr, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ128rrk, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ128rrkz, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ256mi, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ256mik, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ256mikz, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ256ri, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ256rik, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ256rikz, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ256rm, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ256rmk, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ256rmkz, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ256rr, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ256rrk, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZ256rrkz, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZmi, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZmik, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZmikz, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZri, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZrik, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZrikz, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZrm, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZrmk, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZrmkz, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZrr, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZrrk, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWZrrkz, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWri, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWrm, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRAWrr, X86_INS_VPSRAW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDQYri, X86_INS_VPSRLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDQZ128rm, X86_INS_VPSRLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDQZ128rr, X86_INS_VPSRLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDQZ256rm, X86_INS_VPSRLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDQZ256rr, X86_INS_VPSRLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDQZrm, X86_INS_VPSRLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDQZrr, X86_INS_VPSRLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDQri, X86_INS_VPSRLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDYri, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDYrm, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDYrr, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128mbi, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128mbik, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128mbikz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128mi, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128mik, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128mikz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128ri, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128rik, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128rikz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128rm, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128rmk, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128rmkz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128rr, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128rrk, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ128rrkz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256mbi, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256mbik, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256mbikz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256mi, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256mik, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256mikz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256ri, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256rik, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256rikz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256rm, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256rmk, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256rmkz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256rr, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256rrk, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZ256rrkz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZmbi, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZmbik, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZmbikz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZmi, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZmik, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZmikz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZri, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZrik, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZrikz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZrm, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZrmk, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZrmkz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZrr, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZrrk, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDZrrkz, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDri, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDrm, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLDrr, X86_INS_VPSRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQYri, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQYrm, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQYrr, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128mbi, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128mbik, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128mbikz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128mi, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128mik, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128mikz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128ri, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128rik, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128rikz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128rm, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128rmk, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128rmkz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128rr, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128rrk, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ128rrkz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256mbi, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256mbik, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256mbikz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256mi, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256mik, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256mikz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256ri, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256rik, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256rikz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256rm, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256rmk, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256rmkz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256rr, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256rrk, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZ256rrkz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZmbi, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZmbik, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZmbikz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZmi, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZmik, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZmikz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZri, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZrik, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZrikz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZrm, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZrmk, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZrmkz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZrr, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZrrk, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQZrrkz, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQri, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQrm, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLQrr, X86_INS_VPSRLQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDYrm, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDYrr, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ128rm, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ128rmb, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ128rmbk, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ128rmbkz, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ128rmk, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ128rmkz, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ128rr, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ128rrk, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ128rrkz, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ256rm, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ256rmb, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ256rmbk, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ256rmbkz, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ256rmk, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ256rmkz, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ256rr, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ256rrk, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZ256rrkz, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZrm, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZrmb, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZrmbk, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZrmbkz, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZrmk, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZrmkz, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZrr, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZrrk, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDZrrkz, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDrm, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVDrr, X86_INS_VPSRLVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQYrm, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQYrr, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ128rm, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ128rmb, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ128rmbk, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ128rmbkz, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ128rmk, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ128rmkz, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ128rr, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ128rrk, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ128rrkz, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ256rm, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ256rmb, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ256rmbk, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ256rmbkz, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ256rmk, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ256rmkz, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ256rr, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ256rrk, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZ256rrkz, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZrm, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZrmb, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZrmbk, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZrmbkz, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZrmk, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZrmkz, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZrr, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZrrk, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQZrrkz, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQrm, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVQrr, X86_INS_VPSRLVQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZ128rm, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZ128rmk, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZ128rmkz, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZ128rr, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZ128rrk, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZ128rrkz, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZ256rm, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZ256rmk, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZ256rmkz, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZ256rr, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZ256rrk, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZ256rrkz, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZrm, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZrmk, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZrmkz, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZrr, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZrrk, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLVWZrrkz, X86_INS_VPSRLVW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWYri, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWYrm, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWYrr, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ128mi, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ128mik, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ128mikz, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ128ri, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ128rik, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ128rikz, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ128rm, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ128rmk, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ128rmkz, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ128rr, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ128rrk, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ128rrkz, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ256mi, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ256mik, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ256mikz, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ256ri, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ256rik, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ256rikz, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ256rm, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ256rmk, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ256rmkz, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ256rr, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ256rrk, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZ256rrkz, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZmi, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZmik, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZmikz, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZri, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZrik, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZrikz, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZrm, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZrmk, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZrmkz, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZrr, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZrrk, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWZrrkz, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWri, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWrm, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSRLWrr, X86_INS_VPSRLW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBYrm, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBYrr, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZ128rm, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZ128rmk, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZ128rmkz, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZ128rr, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZ128rrk, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZ128rrkz, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZ256rm, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZ256rmk, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZ256rmkz, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZ256rr, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZ256rrk, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZ256rrkz, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZrm, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZrmk, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZrmkz, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZrr, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZrrk, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBZrrkz, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBrm, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBBrr, X86_INS_VPSUBB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDYrm, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDYrr, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ128rm, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ128rmb, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ128rmbk, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ128rmbkz, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ128rmk, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ128rmkz, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ128rr, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ128rrk, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ128rrkz, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ256rm, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ256rmb, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ256rmbk, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ256rmbkz, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ256rmk, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ256rmkz, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ256rr, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ256rrk, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZ256rrkz, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZrm, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZrmb, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZrmbk, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZrmbkz, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZrmk, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZrmkz, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZrr, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZrrk, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDZrrkz, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDrm, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBDrr, X86_INS_VPSUBD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQYrm, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQYrr, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ128rm, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ128rmb, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ128rmbk, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ128rmbkz, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ128rmk, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ128rmkz, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ128rr, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ128rrk, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ128rrkz, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ256rm, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ256rmb, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ256rmbk, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ256rmbkz, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ256rmk, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ256rmkz, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ256rr, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ256rrk, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZ256rrkz, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZrm, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZrmb, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZrmbk, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZrmbkz, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZrmk, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZrmkz, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZrr, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZrrk, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQZrrkz, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQrm, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBQrr, X86_INS_VPSUBQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBYrm, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBYrr, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZ128rm, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZ128rmk, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZ128rmkz, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZ128rr, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZ128rrk, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZ128rrkz, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZ256rm, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZ256rmk, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZ256rmkz, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZ256rr, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZ256rrk, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZ256rrkz, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZrm, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZrmk, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZrmkz, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZrr, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZrrk, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBZrrkz, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBrm, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSBrr, X86_INS_VPSUBSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWYrm, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWYrr, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZ128rm, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZ128rmk, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZ128rmkz, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZ128rr, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZ128rrk, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZ128rrkz, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZ256rm, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZ256rmk, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZ256rmkz, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZ256rr, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZ256rrk, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZ256rrkz, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZrm, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZrmk, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZrmkz, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZrr, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZrrk, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWZrrkz, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWrm, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBSWrr, X86_INS_VPSUBSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBYrm, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBYrr, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZ128rm, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZ128rmk, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZ128rmkz, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZ128rr, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZ128rrk, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZ128rrkz, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZ256rm, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZ256rmk, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZ256rmkz, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZ256rr, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZ256rrk, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZ256rrkz, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZrm, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZrmk, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZrmkz, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZrr, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZrrk, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBZrrkz, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBrm, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSBrr, X86_INS_VPSUBUSB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWYrm, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWYrr, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZ128rm, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZ128rmk, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZ128rmkz, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZ128rr, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZ128rrk, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZ128rrkz, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZ256rm, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZ256rmk, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZ256rmkz, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZ256rr, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZ256rrk, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZ256rrkz, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZrm, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZrmk, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZrmkz, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZrr, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZrrk, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWZrrkz, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWrm, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBUSWrr, X86_INS_VPSUBUSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWYrm, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWYrr, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZ128rm, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZ128rmk, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZ128rmkz, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZ128rr, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZ128rrk, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZ128rrkz, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZ256rm, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZ256rmk, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZ256rmkz, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZ256rr, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZ256rrk, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZ256rrkz, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZrm, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZrmk, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZrmkz, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZrr, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZrrk, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWZrrkz, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWrm, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPSUBWrr, X86_INS_VPSUBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ128rmbi, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ128rmbik, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ128rmbikz, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ128rmi, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ128rmik, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ128rmikz, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ128rri, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ128rrik, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ128rrikz, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ256rmbi, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ256rmbik, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ256rmbikz, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ256rmi, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ256rmik, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ256rmikz, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ256rri, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ256rrik, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZ256rrikz, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZrmbi, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZrmbik, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZrmbikz, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZrmi, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZrmik, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZrmikz, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZrri, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZrrik, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGDZrrikz, X86_INS_VPTERNLOGD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ128rmbi, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ128rmbik, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ128rmbikz, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ128rmi, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ128rmik, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ128rmikz, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ128rri, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ128rrik, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ128rrikz, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ256rmbi, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ256rmbik, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ256rmbikz, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ256rmi, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ256rmik, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ256rmikz, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ256rri, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ256rrik, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZ256rrikz, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZrmbi, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZrmbik, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZrmbikz, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZrmi, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZrmik, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZrmikz, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZrri, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZrrik, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTERNLOGQZrrikz, X86_INS_VPTERNLOGQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMBZ128rm, X86_INS_VPTESTMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMBZ128rmk, X86_INS_VPTESTMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMBZ128rr, X86_INS_VPTESTMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMBZ128rrk, X86_INS_VPTESTMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMBZ256rm, X86_INS_VPTESTMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMBZ256rmk, X86_INS_VPTESTMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMBZ256rr, X86_INS_VPTESTMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMBZ256rrk, X86_INS_VPTESTMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMBZrm, X86_INS_VPTESTMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMBZrmk, X86_INS_VPTESTMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMBZrr, X86_INS_VPTESTMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMBZrrk, X86_INS_VPTESTMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZ128rm, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZ128rmb, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZ128rmbk, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZ128rmk, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZ128rr, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZ128rrk, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZ256rm, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZ256rmb, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZ256rmbk, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZ256rmk, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZ256rr, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZ256rrk, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZrm, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZrmb, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZrmbk, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZrmk, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZrr, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMDZrrk, X86_INS_VPTESTMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZ128rm, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZ128rmb, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZ128rmbk, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZ128rmk, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZ128rr, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZ128rrk, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZ256rm, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZ256rmb, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZ256rmbk, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZ256rmk, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZ256rr, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZ256rrk, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZrm, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZrmb, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZrmbk, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZrmk, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZrr, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMQZrrk, X86_INS_VPTESTMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMWZ128rm, X86_INS_VPTESTMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMWZ128rmk, X86_INS_VPTESTMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMWZ128rr, X86_INS_VPTESTMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMWZ128rrk, X86_INS_VPTESTMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMWZ256rm, X86_INS_VPTESTMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMWZ256rmk, X86_INS_VPTESTMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMWZ256rr, X86_INS_VPTESTMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMWZ256rrk, X86_INS_VPTESTMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMWZrm, X86_INS_VPTESTMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMWZrmk, X86_INS_VPTESTMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMWZrr, X86_INS_VPTESTMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTMWZrrk, X86_INS_VPTESTMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMBZ128rm, X86_INS_VPTESTNMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMBZ128rmk, X86_INS_VPTESTNMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMBZ128rr, X86_INS_VPTESTNMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMBZ128rrk, X86_INS_VPTESTNMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMBZ256rm, X86_INS_VPTESTNMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMBZ256rmk, X86_INS_VPTESTNMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMBZ256rr, X86_INS_VPTESTNMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMBZ256rrk, X86_INS_VPTESTNMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMBZrm, X86_INS_VPTESTNMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMBZrmk, X86_INS_VPTESTNMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMBZrr, X86_INS_VPTESTNMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMBZrrk, X86_INS_VPTESTNMB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZ128rm, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZ128rmb, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZ128rmbk, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZ128rmk, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZ128rr, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZ128rrk, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZ256rm, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZ256rmb, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZ256rmbk, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZ256rmk, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZ256rr, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZ256rrk, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZrm, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZrmb, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZrmbk, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZrmk, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZrr, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMDZrrk, X86_INS_VPTESTNMD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZ128rm, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZ128rmb, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZ128rmbk, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZ128rmk, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZ128rr, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZ128rrk, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZ256rm, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZ256rmb, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZ256rmbk, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZ256rmk, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZ256rr, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZ256rrk, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZrm, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZrmb, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZrmbk, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZrmk, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZrr, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMQZrrk, X86_INS_VPTESTNMQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMWZ128rm, X86_INS_VPTESTNMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMWZ128rmk, X86_INS_VPTESTNMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMWZ128rr, X86_INS_VPTESTNMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMWZ128rrk, X86_INS_VPTESTNMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMWZ256rm, X86_INS_VPTESTNMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMWZ256rmk, X86_INS_VPTESTNMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMWZ256rr, X86_INS_VPTESTNMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMWZ256rrk, X86_INS_VPTESTNMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMWZrm, X86_INS_VPTESTNMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMWZrmk, X86_INS_VPTESTNMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMWZrr, X86_INS_VPTESTNMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTNMWZrrk, X86_INS_VPTESTNMW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTYrm, X86_INS_VPTEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTYrr, X86_INS_VPTEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTrm, X86_INS_VPTEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPTESTrr, X86_INS_VPTEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWYrm, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWYrr, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZ128rm, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZ128rmk, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZ128rmkz, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZ128rr, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZ128rrk, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZ128rrkz, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZ256rm, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZ256rmk, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZ256rmkz, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZ256rr, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZ256rrk, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZ256rrkz, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZrm, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZrmk, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZrmkz, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZrr, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZrrk, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWZrrkz, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWrm, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHBWrr, X86_INS_VPUNPCKHBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQYrm, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQYrr, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ128rm, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ128rmb, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ128rmbk, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ128rmbkz, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ128rmk, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ128rmkz, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ128rr, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ128rrk, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ128rrkz, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ256rm, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ256rmb, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ256rmbk, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ256rmbkz, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ256rmk, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ256rmkz, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ256rr, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ256rrk, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZ256rrkz, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZrm, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZrmb, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZrmbk, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZrmbkz, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZrmk, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZrmkz, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZrr, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZrrk, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQZrrkz, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQrm, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHDQrr, X86_INS_VPUNPCKHDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQYrm, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQYrr, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ128rm, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ128rmb, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ128rmbk, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ128rmbkz, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ128rmk, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ128rmkz, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ128rr, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ128rrk, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ128rrkz, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ256rm, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ256rmb, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ256rmbk, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ256rmbkz, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ256rmk, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ256rmkz, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ256rr, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ256rrk, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZ256rrkz, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZrm, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZrmb, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZrmbk, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZrmbkz, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZrmk, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZrmkz, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZrr, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZrrk, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQZrrkz, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQrm, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHQDQrr, X86_INS_VPUNPCKHQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDYrm, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDYrr, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZ128rm, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZ128rmk, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZ128rmkz, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZ128rr, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZ128rrk, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZ128rrkz, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZ256rm, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZ256rmk, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZ256rmkz, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZ256rr, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZ256rrk, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZ256rrkz, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZrm, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZrmk, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZrmkz, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZrr, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZrrk, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDZrrkz, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDrm, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKHWDrr, X86_INS_VPUNPCKHWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWYrm, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWYrr, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZ128rm, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZ128rmk, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZ128rmkz, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZ128rr, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZ128rrk, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZ128rrkz, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZ256rm, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZ256rmk, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZ256rmkz, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZ256rr, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZ256rrk, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZ256rrkz, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZrm, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZrmk, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZrmkz, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZrr, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZrrk, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWZrrkz, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWrm, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLBWrr, X86_INS_VPUNPCKLBW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQYrm, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQYrr, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ128rm, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ128rmb, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ128rmbk, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ128rmbkz, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ128rmk, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ128rmkz, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ128rr, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ128rrk, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ128rrkz, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ256rm, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ256rmb, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ256rmbk, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ256rmbkz, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ256rmk, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ256rmkz, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ256rr, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ256rrk, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZ256rrkz, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZrm, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZrmb, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZrmbk, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZrmbkz, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZrmk, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZrmkz, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZrr, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZrrk, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQZrrkz, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQrm, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLDQrr, X86_INS_VPUNPCKLDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQYrm, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQYrr, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ128rm, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ128rmb, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ128rmbk, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ128rmbkz, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ128rmk, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ128rmkz, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ128rr, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ128rrk, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ128rrkz, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ256rm, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ256rmb, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ256rmbk, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ256rmbkz, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ256rmk, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ256rmkz, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ256rr, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ256rrk, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZ256rrkz, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZrm, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZrmb, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZrmbk, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZrmbkz, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZrmk, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZrmkz, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZrr, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZrrk, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQZrrkz, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQrm, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLQDQrr, X86_INS_VPUNPCKLQDQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDYrm, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDYrr, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZ128rm, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZ128rmk, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZ128rmkz, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZ128rr, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZ128rrk, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZ128rrkz, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZ256rm, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZ256rmk, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZ256rmkz, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZ256rr, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZ256rrk, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZ256rrkz, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZrm, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZrmk, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZrmkz, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZrr, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZrrk, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDZrrkz, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDrm, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPUNPCKLWDrr, X86_INS_VPUNPCKLWD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ128rm, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ128rmb, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ128rmbk, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ128rmbkz, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ128rmk, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ128rmkz, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ128rr, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ128rrk, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ128rrkz, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ256rm, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ256rmb, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ256rmbk, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ256rmbkz, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ256rmk, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ256rmkz, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ256rr, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ256rrk, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZ256rrkz, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZrm, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZrmb, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZrmbk, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZrmbkz, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZrmk, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZrmkz, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZrr, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZrrk, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORDZrrkz, X86_INS_VPXORD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ128rm, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ128rmb, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ128rmbk, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ128rmbkz, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ128rmk, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ128rmkz, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ128rr, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ128rrk, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ128rrkz, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ256rm, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ256rmb, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ256rmbk, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ256rmbkz, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ256rmk, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ256rmkz, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ256rr, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ256rrk, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZ256rrkz, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZrm, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZrmb, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZrmbk, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZrmbkz, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZrmk, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZrmkz, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZrr, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZrrk, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORQZrrkz, X86_INS_VPXORQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORYrm, X86_INS_VPXOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORYrr, X86_INS_VPXOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORrm, X86_INS_VPXOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VPXORrr, X86_INS_VPXOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ128rmbi, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ128rmbik, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ128rmbikz, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ128rmi, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ128rmik, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ128rmikz, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ128rri, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ128rrik, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ128rrikz, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ256rmbi, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ256rmbik, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ256rmbikz, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ256rmi, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ256rmik, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ256rmikz, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ256rri, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ256rrik, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZ256rrikz, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZrmbi, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZrmbik, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZrmbikz, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZrmi, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZrmik, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZrmikz, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZrri, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZrrib, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZrribk, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZrribkz, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZrrik, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPDZrrikz, X86_INS_VRANGEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ128rmbi, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ128rmbik, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ128rmbikz, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ128rmi, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ128rmik, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ128rmikz, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ128rri, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ128rrik, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ128rrikz, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ256rmbi, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ256rmbik, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ256rmbikz, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ256rmi, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ256rmik, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ256rmikz, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ256rri, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ256rrik, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZ256rrikz, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZrmbi, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZrmbik, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZrmbikz, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZrmi, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZrmik, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZrmikz, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZrri, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZrrib, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZrribk, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZrribkz, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZrrik, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGEPSZrrikz, X86_INS_VRANGEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESDZrmi, X86_INS_VRANGESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESDZrmik, X86_INS_VRANGESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESDZrmikz, X86_INS_VRANGESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESDZrri, X86_INS_VRANGESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESDZrrib, X86_INS_VRANGESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESDZrribk, X86_INS_VRANGESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESDZrribkz, X86_INS_VRANGESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESDZrrik, X86_INS_VRANGESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESDZrrikz, X86_INS_VRANGESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESSZrmi, X86_INS_VRANGESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESSZrmik, X86_INS_VRANGESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESSZrmikz, X86_INS_VRANGESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESSZrri, X86_INS_VRANGESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESSZrrib, X86_INS_VRANGESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESSZrribk, X86_INS_VRANGESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESSZrribkz, X86_INS_VRANGESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESSZrrik, X86_INS_VRANGESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRANGESSZrrikz, X86_INS_VRANGESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ128m, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ128mb, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ128mbk, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ128mbkz, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ128mk, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ128mkz, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ128r, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ128rk, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ128rkz, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ256m, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ256mb, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ256mbk, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ256mbkz, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ256mk, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ256mkz, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ256r, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ256rk, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZ256rkz, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZm, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZmb, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZmbk, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZmbkz, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZmk, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZmkz, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZr, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZrk, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PDZrkz, X86_INS_VRCP14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ128m, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ128mb, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ128mbk, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ128mbkz, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ128mk, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ128mkz, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ128r, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ128rk, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ128rkz, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ256m, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ256mb, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ256mbk, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ256mbkz, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ256mk, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ256mkz, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ256r, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ256rk, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZ256rkz, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZm, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZmb, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZmbk, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZmbkz, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZmk, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZmkz, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZr, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZrk, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14PSZrkz, X86_INS_VRCP14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14SDZrm, X86_INS_VRCP14SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14SDZrmk, X86_INS_VRCP14SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14SDZrmkz, X86_INS_VRCP14SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14SDZrr, X86_INS_VRCP14SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14SDZrrk, X86_INS_VRCP14SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14SDZrrkz, X86_INS_VRCP14SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14SSZrm, X86_INS_VRCP14SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14SSZrmk, X86_INS_VRCP14SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14SSZrmkz, X86_INS_VRCP14SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14SSZrr, X86_INS_VRCP14SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14SSZrrk, X86_INS_VRCP14SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP14SSZrrkz, X86_INS_VRCP14SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PDZm, X86_INS_VRCP28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PDZmb, X86_INS_VRCP28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PDZmbk, X86_INS_VRCP28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PDZmbkz, X86_INS_VRCP28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PDZmk, X86_INS_VRCP28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PDZmkz, X86_INS_VRCP28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PDZr, X86_INS_VRCP28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PDZrb, X86_INS_VRCP28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PDZrbk, X86_INS_VRCP28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PDZrbkz, X86_INS_VRCP28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PDZrk, X86_INS_VRCP28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PDZrkz, X86_INS_VRCP28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PSZm, X86_INS_VRCP28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PSZmb, X86_INS_VRCP28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PSZmbk, X86_INS_VRCP28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PSZmbkz, X86_INS_VRCP28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PSZmk, X86_INS_VRCP28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PSZmkz, X86_INS_VRCP28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PSZr, X86_INS_VRCP28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PSZrb, X86_INS_VRCP28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PSZrbk, X86_INS_VRCP28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PSZrbkz, X86_INS_VRCP28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PSZrk, X86_INS_VRCP28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28PSZrkz, X86_INS_VRCP28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SDZm, X86_INS_VRCP28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SDZmk, X86_INS_VRCP28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SDZmkz, X86_INS_VRCP28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SDZr, X86_INS_VRCP28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SDZrb, X86_INS_VRCP28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SDZrbk, X86_INS_VRCP28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SDZrbkz, X86_INS_VRCP28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SDZrk, X86_INS_VRCP28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SDZrkz, X86_INS_VRCP28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SSZm, X86_INS_VRCP28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SSZmk, X86_INS_VRCP28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SSZmkz, X86_INS_VRCP28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SSZr, X86_INS_VRCP28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SSZrb, X86_INS_VRCP28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SSZrbk, X86_INS_VRCP28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SSZrbkz, X86_INS_VRCP28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SSZrk, X86_INS_VRCP28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCP28SSZrkz, X86_INS_VRCP28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCPPSYm, X86_INS_VRCPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCPPSYr, X86_INS_VRCPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCPPSm, X86_INS_VRCPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCPPSr, X86_INS_VRCPPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRCPSSm, X86_INS_VRCPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCPSSm_Int, X86_INS_VRCPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCPSSr, X86_INS_VRCPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRCPSSr_Int, X86_INS_VRCPSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ128rmbi, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ128rmbik, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ128rmbikz, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ128rmi, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ128rmik, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ128rmikz, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ128rri, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ128rrik, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ128rrikz, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ256rmbi, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ256rmbik, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ256rmbikz, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ256rmi, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ256rmik, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ256rmikz, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ256rri, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ256rrik, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZ256rrikz, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZrmbi, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZrmbik, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZrmbikz, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZrmi, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZrmik, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZrmikz, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZrri, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZrrib, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZrribk, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZrribkz, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZrrik, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPDZrrikz, X86_INS_VREDUCEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ128rmbi, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ128rmbik, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ128rmbikz, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ128rmi, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ128rmik, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ128rmikz, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ128rri, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ128rrik, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ128rrikz, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ256rmbi, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ256rmbik, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ256rmbikz, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ256rmi, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ256rmik, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ256rmikz, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ256rri, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ256rrik, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZ256rrikz, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZrmbi, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZrmbik, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZrmbikz, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZrmi, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZrmik, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZrmikz, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZrri, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZrrib, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZrribk, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZrribkz, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZrrik, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCEPSZrrikz, X86_INS_VREDUCEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESDZrmi, X86_INS_VREDUCESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESDZrmik, X86_INS_VREDUCESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESDZrmikz, X86_INS_VREDUCESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESDZrri, X86_INS_VREDUCESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESDZrrib, X86_INS_VREDUCESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESDZrribk, X86_INS_VREDUCESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESDZrribkz, X86_INS_VREDUCESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESDZrrik, X86_INS_VREDUCESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESDZrrikz, X86_INS_VREDUCESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESSZrmi, X86_INS_VREDUCESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESSZrmik, X86_INS_VREDUCESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESSZrmikz, X86_INS_VREDUCESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESSZrri, X86_INS_VREDUCESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESSZrrib, X86_INS_VREDUCESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESSZrribk, X86_INS_VREDUCESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESSZrribkz, X86_INS_VREDUCESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESSZrrik, X86_INS_VREDUCESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VREDUCESSZrrikz, X86_INS_VREDUCESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ128rmbi, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ128rmbik, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ128rmbikz, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ128rmi, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ128rmik, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ128rmikz, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ128rri, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ128rrik, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ128rrikz, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ256rmbi, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ256rmbik, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ256rmbikz, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ256rmi, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ256rmik, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ256rmikz, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ256rri, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ256rrik, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZ256rrikz, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZrmbi, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZrmbik, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZrmbikz, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZrmi, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZrmik, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZrmikz, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZrri, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZrrib, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZrribk, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZrribkz, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZrrik, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPDZrrikz, X86_INS_VRNDSCALEPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ128rmbi, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ128rmbik, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ128rmbikz, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ128rmi, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ128rmik, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ128rmikz, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ128rri, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ128rrik, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ128rrikz, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ256rmbi, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ256rmbik, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ256rmbikz, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ256rmi, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ256rmik, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ256rmikz, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ256rri, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ256rrik, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZ256rrikz, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZrmbi, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZrmbik, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZrmbikz, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZrmi, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZrmik, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZrmikz, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZrri, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZrrib, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZrribk, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZrribkz, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZrrik, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALEPSZrrikz, X86_INS_VRNDSCALEPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESDZm, X86_INS_VRNDSCALESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESDZm_Int, X86_INS_VRNDSCALESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESDZm_Intk, X86_INS_VRNDSCALESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESDZm_Intkz, X86_INS_VRNDSCALESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESDZr, X86_INS_VRNDSCALESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESDZr_Int, X86_INS_VRNDSCALESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESDZr_Intk, X86_INS_VRNDSCALESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESDZr_Intkz, X86_INS_VRNDSCALESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESDZrb_Int, X86_INS_VRNDSCALESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESDZrb_Intk, X86_INS_VRNDSCALESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESDZrb_Intkz, X86_INS_VRNDSCALESD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESSZm, X86_INS_VRNDSCALESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESSZm_Int, X86_INS_VRNDSCALESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESSZm_Intk, X86_INS_VRNDSCALESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESSZm_Intkz, X86_INS_VRNDSCALESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESSZr, X86_INS_VRNDSCALESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESSZr_Int, X86_INS_VRNDSCALESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESSZr_Intk, X86_INS_VRNDSCALESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESSZr_Intkz, X86_INS_VRNDSCALESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESSZrb_Int, X86_INS_VRNDSCALESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESSZrb_Intk, X86_INS_VRNDSCALESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRNDSCALESSZrb_Intkz, X86_INS_VRNDSCALESS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDPDYm, X86_INS_VROUNDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDPDYr, X86_INS_VROUNDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDPDm, X86_INS_VROUNDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDPDr, X86_INS_VROUNDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDPSYm, X86_INS_VROUNDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDPSYr, X86_INS_VROUNDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDPSm, X86_INS_VROUNDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDPSr, X86_INS_VROUNDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDSDm, X86_INS_VROUNDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDSDm_Int, X86_INS_VROUNDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDSDr, X86_INS_VROUNDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDSDr_Int, X86_INS_VROUNDSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDSSm, X86_INS_VROUNDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDSSm_Int, X86_INS_VROUNDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDSSr, X86_INS_VROUNDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VROUNDSSr_Int, X86_INS_VROUNDSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ128m, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ128mb, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ128mbk, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ128mbkz, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ128mk, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ128mkz, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ128r, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ128rk, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ128rkz, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ256m, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ256mb, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ256mbk, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ256mbkz, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ256mk, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ256mkz, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ256r, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ256rk, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZ256rkz, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZm, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZmb, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZmbk, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZmbkz, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZmk, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZmkz, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZr, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZrk, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PDZrkz, X86_INS_VRSQRT14PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ128m, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ128mb, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ128mbk, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ128mbkz, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ128mk, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ128mkz, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ128r, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ128rk, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ128rkz, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ256m, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ256mb, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ256mbk, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ256mbkz, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ256mk, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ256mkz, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ256r, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ256rk, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZ256rkz, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZm, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZmb, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZmbk, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZmbkz, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZmk, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZmkz, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZr, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZrk, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14PSZrkz, X86_INS_VRSQRT14PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14SDZrm, X86_INS_VRSQRT14SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14SDZrmk, X86_INS_VRSQRT14SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14SDZrmkz, X86_INS_VRSQRT14SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14SDZrr, X86_INS_VRSQRT14SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14SDZrrk, X86_INS_VRSQRT14SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14SDZrrkz, X86_INS_VRSQRT14SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14SSZrm, X86_INS_VRSQRT14SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14SSZrmk, X86_INS_VRSQRT14SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14SSZrmkz, X86_INS_VRSQRT14SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14SSZrr, X86_INS_VRSQRT14SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14SSZrrk, X86_INS_VRSQRT14SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT14SSZrrkz, X86_INS_VRSQRT14SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PDZm, X86_INS_VRSQRT28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PDZmb, X86_INS_VRSQRT28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PDZmbk, X86_INS_VRSQRT28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PDZmbkz, X86_INS_VRSQRT28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PDZmk, X86_INS_VRSQRT28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PDZmkz, X86_INS_VRSQRT28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PDZr, X86_INS_VRSQRT28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PDZrb, X86_INS_VRSQRT28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PDZrbk, X86_INS_VRSQRT28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PDZrbkz, X86_INS_VRSQRT28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PDZrk, X86_INS_VRSQRT28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PDZrkz, X86_INS_VRSQRT28PD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PSZm, X86_INS_VRSQRT28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PSZmb, X86_INS_VRSQRT28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PSZmbk, X86_INS_VRSQRT28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PSZmbkz, X86_INS_VRSQRT28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PSZmk, X86_INS_VRSQRT28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PSZmkz, X86_INS_VRSQRT28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PSZr, X86_INS_VRSQRT28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PSZrb, X86_INS_VRSQRT28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PSZrbk, X86_INS_VRSQRT28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PSZrbkz, X86_INS_VRSQRT28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PSZrk, X86_INS_VRSQRT28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28PSZrkz, X86_INS_VRSQRT28PS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SDZm, X86_INS_VRSQRT28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SDZmk, X86_INS_VRSQRT28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SDZmkz, X86_INS_VRSQRT28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SDZr, X86_INS_VRSQRT28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SDZrb, X86_INS_VRSQRT28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SDZrbk, X86_INS_VRSQRT28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SDZrbkz, X86_INS_VRSQRT28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SDZrk, X86_INS_VRSQRT28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SDZrkz, X86_INS_VRSQRT28SD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SSZm, X86_INS_VRSQRT28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SSZmk, X86_INS_VRSQRT28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SSZmkz, X86_INS_VRSQRT28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SSZr, X86_INS_VRSQRT28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SSZrb, X86_INS_VRSQRT28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SSZrbk, X86_INS_VRSQRT28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SSZrbkz, X86_INS_VRSQRT28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SSZrk, X86_INS_VRSQRT28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRT28SSZrkz, X86_INS_VRSQRT28SS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRTPSYm, X86_INS_VRSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRTPSYr, X86_INS_VRSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRTPSm, X86_INS_VRSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRTPSr, X86_INS_VRSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRTSSm, X86_INS_VRSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRTSSm_Int, X86_INS_VRSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRTSSr, X86_INS_VRSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VRSQRTSSr_Int, X86_INS_VRSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ128rm, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ128rmb, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ128rmbk, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ128rmbkz, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ128rmk, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ128rmkz, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ128rr, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ128rrk, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ128rrkz, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ256rm, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ256rmb, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ256rmbk, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ256rmbkz, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ256rmk, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ256rmkz, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ256rr, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ256rrk, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZ256rrkz, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZrm, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZrmb, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZrmbk, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZrmbkz, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZrmk, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZrmkz, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZrr, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZrrb, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZrrbk, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZrrbkz, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZrrk, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPDZrrkz, X86_INS_VSCALEFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ128rm, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ128rmb, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ128rmbk, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ128rmbkz, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ128rmk, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ128rmkz, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ128rr, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ128rrk, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ128rrkz, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ256rm, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ256rmb, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ256rmbk, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ256rmbkz, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ256rmk, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ256rmkz, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ256rr, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ256rrk, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZ256rrkz, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZrm, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZrmb, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZrmbk, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZrmbkz, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZrmk, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZrmkz, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZrr, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZrrb, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZrrbk, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZrrbkz, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZrrk, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFPSZrrkz, X86_INS_VSCALEFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSDZrm, X86_INS_VSCALEFSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSDZrmk, X86_INS_VSCALEFSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSDZrmkz, X86_INS_VSCALEFSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSDZrr, X86_INS_VSCALEFSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSDZrrb_Int, X86_INS_VSCALEFSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSDZrrb_Intk, X86_INS_VSCALEFSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSDZrrb_Intkz, X86_INS_VSCALEFSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSDZrrk, X86_INS_VSCALEFSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSDZrrkz, X86_INS_VSCALEFSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSSZrm, X86_INS_VSCALEFSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSSZrmk, X86_INS_VSCALEFSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSSZrmkz, X86_INS_VSCALEFSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSSZrr, X86_INS_VSCALEFSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSSZrrb_Int, X86_INS_VSCALEFSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSSZrrb_Intk, X86_INS_VSCALEFSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSSZrrb_Intkz, X86_INS_VSCALEFSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSSZrrk, X86_INS_VSCALEFSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCALEFSSZrrkz, X86_INS_VSCALEFSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERDPDZ128mr, X86_INS_VSCATTERDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERDPDZ256mr, X86_INS_VSCATTERDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERDPDZmr, X86_INS_VSCATTERDPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERDPSZ128mr, X86_INS_VSCATTERDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERDPSZ256mr, X86_INS_VSCATTERDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERDPSZmr, X86_INS_VSCATTERDPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERPF0DPDm, X86_INS_VSCATTERPF0DPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERPF0DPSm, X86_INS_VSCATTERPF0DPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERPF0QPDm, X86_INS_VSCATTERPF0QPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERPF0QPSm, X86_INS_VSCATTERPF0QPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERPF1DPDm, X86_INS_VSCATTERPF1DPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERPF1DPSm, X86_INS_VSCATTERPF1DPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERPF1QPDm, X86_INS_VSCATTERPF1QPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERPF1QPSm, X86_INS_VSCATTERPF1QPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERQPDZ128mr, X86_INS_VSCATTERQPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERQPDZ256mr, X86_INS_VSCATTERQPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERQPDZmr, X86_INS_VSCATTERQPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERQPSZ128mr, X86_INS_VSCATTERQPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERQPSZ256mr, X86_INS_VSCATTERQPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSCATTERQPSZmr, X86_INS_VSCATTERQPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Z256rmbi, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Z256rmbik, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Z256rmbikz, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Z256rmi, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Z256rmik, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Z256rmikz, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Z256rri, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Z256rrik, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Z256rrikz, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Zrmbi, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Zrmbik, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Zrmbikz, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Zrmi, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Zrmik, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Zrmikz, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Zrri, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Zrrik, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF32X4Zrrikz, X86_INS_VSHUFF32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Z256rmbi, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Z256rmbik, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Z256rmbikz, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Z256rmi, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Z256rmik, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Z256rmikz, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Z256rri, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Z256rrik, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Z256rrikz, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Zrmbi, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Zrmbik, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Zrmbikz, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Zrmi, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Zrmik, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Zrmikz, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Zrri, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Zrrik, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFF64X2Zrrikz, X86_INS_VSHUFF64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Z256rmbi, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Z256rmbik, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Z256rmbikz, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Z256rmi, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Z256rmik, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Z256rmikz, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Z256rri, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Z256rrik, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Z256rrikz, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Zrmbi, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Zrmbik, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Zrmbikz, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Zrmi, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Zrmik, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Zrmikz, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Zrri, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Zrrik, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI32X4Zrrikz, X86_INS_VSHUFI32X4, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Z256rmbi, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Z256rmbik, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Z256rmbikz, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Z256rmi, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Z256rmik, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Z256rmikz, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Z256rri, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Z256rrik, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Z256rrikz, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Zrmbi, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Zrmbik, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Zrmbikz, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Zrmi, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Zrmik, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Zrmikz, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Zrri, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Zrrik, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFI64X2Zrrikz, X86_INS_VSHUFI64X2, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDYrmi, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDYrri, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ128rmbi, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ128rmbik, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ128rmbikz, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ128rmi, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ128rmik, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ128rmikz, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ128rri, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ128rrik, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ128rrikz, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ256rmbi, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ256rmbik, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ256rmbikz, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ256rmi, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ256rmik, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ256rmikz, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ256rri, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ256rrik, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZ256rrikz, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZrmbi, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZrmbik, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZrmbikz, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZrmi, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZrmik, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZrmikz, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZrri, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZrrik, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDZrrikz, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDrmi, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPDrri, X86_INS_VSHUFPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSYrmi, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSYrri, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ128rmbi, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ128rmbik, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ128rmbikz, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ128rmi, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ128rmik, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ128rmikz, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ128rri, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ128rrik, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ128rrikz, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ256rmbi, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ256rmbik, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ256rmbikz, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ256rmi, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ256rmik, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ256rmikz, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ256rri, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ256rrik, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZ256rrikz, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZrmbi, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZrmbik, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZrmbikz, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZrmi, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZrmik, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZrmikz, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZrri, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZrrik, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSZrrikz, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSrmi, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSHUFPSrri, X86_INS_VSHUFPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDYm, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDYr, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ128m, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ128mb, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ128mbk, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ128mbkz, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ128mk, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ128mkz, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ128r, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ128rk, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ128rkz, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ256m, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ256mb, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ256mbk, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ256mbkz, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ256mk, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ256mkz, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ256r, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ256rk, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZ256rkz, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZm, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZmb, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZmbk, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZmbkz, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZmk, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZmkz, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZr, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZrb, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZrbk, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZrbkz, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZrk, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDZrkz, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDm, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPDr, X86_INS_VSQRTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSYm, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSYr, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ128m, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ128mb, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ128mbk, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ128mbkz, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ128mk, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ128mkz, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ128r, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ128rk, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ128rkz, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ256m, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ256mb, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ256mbk, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ256mbkz, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ256mk, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ256mkz, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ256r, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ256rk, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZ256rkz, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZm, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZmb, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZmbk, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZmbkz, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZmk, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZmkz, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZr, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZrb, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZrbk, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZrbkz, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZrk, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSZrkz, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSm, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTPSr, X86_INS_VSQRTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDZm, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDZm_Int, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDZm_Intk, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDZm_Intkz, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDZr, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDZr_Int, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDZr_Intk, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDZr_Intkz, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDZrb_Int, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDZrb_Intk, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDZrb_Intkz, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDm, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDm_Int, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDr, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSDr_Int, X86_INS_VSQRTSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSZm, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSZm_Int, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSZm_Intk, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSZm_Intkz, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSZr, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSZr_Int, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSZr_Intk, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSZr_Intkz, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSZrb_Int, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSZrb_Intk, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSZrb_Intkz, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSm, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSm_Int, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSr, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSQRTSSr_Int, X86_INS_VSQRTSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSTMXCSR, X86_INS_VSTMXCSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDYrm, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDYrr, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ128rm, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ128rmb, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ128rmbk, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ128rmbkz, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ128rmk, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ128rmkz, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ128rr, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ128rrk, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ128rrkz, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ256rm, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ256rmb, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ256rmbk, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ256rmbkz, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ256rmk, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ256rmkz, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ256rr, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ256rrk, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZ256rrkz, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZrm, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZrmb, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZrmbk, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZrmbkz, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZrmk, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZrmkz, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZrr, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZrrb, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZrrbk, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZrrbkz, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZrrk, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDZrrkz, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDrm, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPDrr, X86_INS_VSUBPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSYrm, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSYrr, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ128rm, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ128rmb, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ128rmbk, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ128rmbkz, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ128rmk, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ128rmkz, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ128rr, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ128rrk, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ128rrkz, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ256rm, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ256rmb, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ256rmbk, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ256rmbkz, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ256rmk, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ256rmkz, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ256rr, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ256rrk, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZ256rrkz, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZrm, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZrmb, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZrmbk, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZrmbkz, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZrmk, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZrmkz, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZrr, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZrrb, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZrrbk, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZrrbkz, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZrrk, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSZrrkz, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSrm, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBPSrr, X86_INS_VSUBPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDZrm, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDZrm_Int, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDZrm_Intk, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDZrm_Intkz, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDZrr, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDZrr_Int, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDZrr_Intk, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDZrr_Intkz, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDZrrb_Int, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDZrrb_Intk, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDZrrb_Intkz, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDrm, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDrm_Int, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDrr, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSDrr_Int, X86_INS_VSUBSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSZrm, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSZrm_Int, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSZrm_Intk, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSZrm_Intkz, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSZrr, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSZrr_Int, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSZrr_Intk, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSZrr_Intkz, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSZrrb_Int, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSZrrb_Intk, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSZrrb_Intkz, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSrm, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSrm_Int, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSrr, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VSUBSSrr_Int, X86_INS_VSUBSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VTESTPDYrm, X86_INS_VTESTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VTESTPDYrr, X86_INS_VTESTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VTESTPDrm, X86_INS_VTESTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VTESTPDrr, X86_INS_VTESTPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VTESTPSYrm, X86_INS_VTESTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VTESTPSYrr, X86_INS_VTESTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VTESTPSrm, X86_INS_VTESTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VTESTPSrr, X86_INS_VTESTPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISDZrm, X86_INS_VUCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISDZrm_Int, X86_INS_VUCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISDZrr, X86_INS_VUCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISDZrr_Int, X86_INS_VUCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISDZrrb, X86_INS_VUCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISDrm, X86_INS_VUCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISDrm_Int, X86_INS_VUCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISDrr, X86_INS_VUCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISDrr_Int, X86_INS_VUCOMISD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISSZrm, X86_INS_VUCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISSZrm_Int, X86_INS_VUCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISSZrr, X86_INS_VUCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISSZrr_Int, X86_INS_VUCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISSZrrb, X86_INS_VUCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISSrm, X86_INS_VUCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISSrm_Int, X86_INS_VUCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISSrr, X86_INS_VUCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUCOMISSrr_Int, X86_INS_VUCOMISS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDYrm, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDYrr, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ128rm, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ128rmb, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ128rmbk, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ128rmbkz, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ128rmk, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ128rmkz, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ128rr, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ128rrk, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ128rrkz, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ256rm, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ256rmb, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ256rmbk, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ256rmbkz, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ256rmk, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ256rmkz, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ256rr, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ256rrk, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZ256rrkz, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZrm, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZrmb, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZrmbk, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZrmbkz, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZrmk, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZrmkz, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZrr, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZrrk, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDZrrkz, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDrm, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPDrr, X86_INS_VUNPCKHPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSYrm, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSYrr, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ128rm, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ128rmb, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ128rmbk, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ128rmbkz, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ128rmk, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ128rmkz, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ128rr, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ128rrk, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ128rrkz, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ256rm, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ256rmb, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ256rmbk, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ256rmbkz, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ256rmk, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ256rmkz, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ256rr, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ256rrk, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZ256rrkz, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZrm, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZrmb, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZrmbk, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZrmbkz, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZrmk, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZrmkz, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZrr, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZrrk, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSZrrkz, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSrm, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKHPSrr, X86_INS_VUNPCKHPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDYrm, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDYrr, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ128rm, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ128rmb, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ128rmbk, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ128rmbkz, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ128rmk, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ128rmkz, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ128rr, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ128rrk, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ128rrkz, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ256rm, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ256rmb, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ256rmbk, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ256rmbkz, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ256rmk, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ256rmkz, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ256rr, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ256rrk, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZ256rrkz, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZrm, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZrmb, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZrmbk, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZrmbkz, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZrmk, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZrmkz, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZrr, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZrrk, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDZrrkz, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDrm, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPDrr, X86_INS_VUNPCKLPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSYrm, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSYrr, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ128rm, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ128rmb, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ128rmbk, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ128rmbkz, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ128rmk, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ128rmkz, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ128rr, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ128rrk, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ128rrkz, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ256rm, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ256rmb, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ256rmbk, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ256rmbkz, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ256rmk, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ256rmkz, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ256rr, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ256rrk, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZ256rrkz, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZrm, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZrmb, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZrmbk, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZrmbkz, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZrmk, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZrmkz, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZrr, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZrrk, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSZrrkz, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSrm, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VUNPCKLPSrr, X86_INS_VUNPCKLPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDYrm, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDYrr, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ128rm, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ128rmb, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ128rmbk, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ128rmbkz, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ128rmk, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ128rmkz, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ128rr, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ128rrk, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ128rrkz, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ256rm, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ256rmb, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ256rmbk, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ256rmbkz, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ256rmk, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ256rmkz, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ256rr, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ256rrk, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZ256rrkz, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZrm, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZrmb, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZrmbk, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZrmbkz, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZrmk, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZrmkz, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZrr, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZrrk, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDZrrkz, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDrm, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPDrr, X86_INS_VXORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSYrm, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSYrr, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ128rm, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ128rmb, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ128rmbk, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ128rmbkz, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ128rmk, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ128rmkz, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ128rr, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ128rrk, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ128rrkz, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ256rm, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ256rmb, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ256rmbk, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ256rmbkz, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ256rmk, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ256rmkz, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ256rr, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ256rrk, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZ256rrkz, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZrm, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZrmb, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZrmbk, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZrmbkz, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZrmk, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZrmkz, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZrr, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZrrk, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSZrrkz, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSrm, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VXORPSrr, X86_INS_VXORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 +#endif +}, + +{ + X86_VZEROALL, X86_INS_VZEROALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_VZEROUPPER, X86_INS_VZEROUPPER, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, 0 }, { X86_GRP_AVX, 0 }, 0, 0 +#endif +}, + +{ + X86_WAIT, X86_INS_WAIT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_WBINVD, X86_INS_WBINVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_WBNOINVD, X86_INS_WBNOINVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_WRFSBASE, X86_INS_WRFSBASE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_WRFSBASE64, X86_INS_WRFSBASE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_WRGSBASE, X86_INS_WRGSBASE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_WRGSBASE64, X86_INS_WRGSBASE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_WRMSR, X86_INS_WRMSR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_WRPKRUr, X86_INS_WRPKRU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_WRSSD, X86_INS_WRSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_WRSSQ, X86_INS_WRSSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_WRUSSD, X86_INS_WRUSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_WRUSSQ, X86_INS_WRUSSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XABORT, X86_INS_XABORT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RTM, 0 }, 0, 0 +#endif +}, + +{ + X86_XACQUIRE_PREFIX, X86_INS_XACQUIRE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_HLE, 0 }, 0, 0 +#endif +}, + +{ + X86_XADD16rm, X86_INS_XADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD16rr, X86_INS_XADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD32rm, X86_INS_XADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD32rr, X86_INS_XADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD64rm, X86_INS_XADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD64rr, X86_INS_XADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD8rm, X86_INS_XADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD8rr, X86_INS_XADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XBEGIN_2, X86_INS_XBEGIN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EAX, 0 }, { X86_GRP_BRANCH_RELATIVE, X86_GRP_RTM, 0 }, 1, 0 +#endif +}, + +{ + X86_XBEGIN_4, X86_INS_XBEGIN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EAX, 0 }, { X86_GRP_BRANCH_RELATIVE, X86_GRP_RTM, 0 }, 1, 0 +#endif +}, + +{ + X86_XCHG16ar, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG16rm, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG16rr, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG32ar, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG32rm, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG32rr, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG64ar, X86_INS_XCHG, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG64rm, X86_INS_XCHG, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG64rr, X86_INS_XCHG, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG8rm, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG8rr, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCH_F, X86_INS_FXCH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 +#endif +}, + +{ + X86_XCRYPTCBC, X86_INS_XCRYPTCBC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCRYPTCFB, X86_INS_XCRYPTCFB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCRYPTCTR, X86_INS_XCRYPTCTR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCRYPTECB, X86_INS_XCRYPTECB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCRYPTOFB, X86_INS_XCRYPTOFB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XEND, X86_INS_XEND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RTM, 0 }, 0, 0 +#endif +}, + +{ + X86_XGETBV, X86_INS_XGETBV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ECX, 0 }, { X86_REG_EDX, X86_REG_EAX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XLAT, X86_INS_XLATB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16i16, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16mi, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16mi8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16mr, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16ri, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16ri8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16rm, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16rr, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16rr_REV, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32i32, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32mi, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32mi8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32mr, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32ri, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32ri8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32rm, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32rr, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32rr_REV, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64i32, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64mi32, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64mi8, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64mr, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64ri32, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64ri8, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64rm, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64rr, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64rr_REV, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8i8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8mi, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8mi8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8mr, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8ri, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8ri8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8rm, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8rr, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8rr_REV, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XORPDrm, X86_INS_XORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_XORPDrr, X86_INS_XORPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 +#endif +}, + +{ + X86_XORPSrm, X86_INS_XORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_XORPSrr, X86_INS_XORPS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 +#endif +}, + +{ + X86_XRELEASE_PREFIX, X86_INS_XRELEASE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_HLE, 0 }, 0, 0 +#endif +}, + +{ + X86_XRSTOR, X86_INS_XRSTOR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XRSTOR64, X86_INS_XRSTOR64, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_XRSTORS, X86_INS_XRSTORS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_XRSTORS64, X86_INS_XRSTORS64, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVE, X86_INS_XSAVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVE64, X86_INS_XSAVE64, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVEC, X86_INS_XSAVEC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVEC64, X86_INS_XSAVEC64, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVEOPT, X86_INS_XSAVEOPT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVEOPT64, X86_INS_XSAVEOPT64, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVES, X86_INS_XSAVES, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVES64, X86_INS_XSAVES64, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_XSETBV, X86_INS_XSETBV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDX, X86_REG_EAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_XSHA1, X86_INS_XSHA1, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XSHA256, X86_INS_XSHA256, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XSTORE, X86_INS_XSTORE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XTEST, X86_INS_XTEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, diff --git a/thirdparty/capstone/arch/X86/X86MappingInsnName.inc b/thirdparty/capstone/arch/X86/X86MappingInsnName.inc new file mode 100644 index 0000000..81adb43 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86MappingInsnName.inc @@ -0,0 +1,1527 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + + "aaa", // X86_INS_AAA + "aad", // X86_INS_AAD + "aam", // X86_INS_AAM + "aas", // X86_INS_AAS + "fabs", // X86_INS_FABS + "adc", // X86_INS_ADC + "adcx", // X86_INS_ADCX + "add", // X86_INS_ADD + "addpd", // X86_INS_ADDPD + "addps", // X86_INS_ADDPS + "addsd", // X86_INS_ADDSD + "addss", // X86_INS_ADDSS + "addsubpd", // X86_INS_ADDSUBPD + "addsubps", // X86_INS_ADDSUBPS + "fadd", // X86_INS_FADD + "fiadd", // X86_INS_FIADD + "adox", // X86_INS_ADOX + "aesdeclast", // X86_INS_AESDECLAST + "aesdec", // X86_INS_AESDEC + "aesenclast", // X86_INS_AESENCLAST + "aesenc", // X86_INS_AESENC + "aesimc", // X86_INS_AESIMC + "aeskeygenassist", // X86_INS_AESKEYGENASSIST + "and", // X86_INS_AND + "andn", // X86_INS_ANDN + "andnpd", // X86_INS_ANDNPD + "andnps", // X86_INS_ANDNPS + "andpd", // X86_INS_ANDPD + "andps", // X86_INS_ANDPS + "arpl", // X86_INS_ARPL + "bextr", // X86_INS_BEXTR + "blcfill", // X86_INS_BLCFILL + "blci", // X86_INS_BLCI + "blcic", // X86_INS_BLCIC + "blcmsk", // X86_INS_BLCMSK + "blcs", // X86_INS_BLCS + "blendpd", // X86_INS_BLENDPD + "blendps", // X86_INS_BLENDPS + "blendvpd", // X86_INS_BLENDVPD + "blendvps", // X86_INS_BLENDVPS + "blsfill", // X86_INS_BLSFILL + "blsi", // X86_INS_BLSI + "blsic", // X86_INS_BLSIC + "blsmsk", // X86_INS_BLSMSK + "blsr", // X86_INS_BLSR + "bndcl", // X86_INS_BNDCL + "bndcn", // X86_INS_BNDCN + "bndcu", // X86_INS_BNDCU + "bndldx", // X86_INS_BNDLDX + "bndmk", // X86_INS_BNDMK + "bndmov", // X86_INS_BNDMOV + "bndstx", // X86_INS_BNDSTX + "bound", // X86_INS_BOUND + "bsf", // X86_INS_BSF + "bsr", // X86_INS_BSR + "bswap", // X86_INS_BSWAP + "bt", // X86_INS_BT + "btc", // X86_INS_BTC + "btr", // X86_INS_BTR + "bts", // X86_INS_BTS + "bzhi", // X86_INS_BZHI + "call", // X86_INS_CALL + "cbw", // X86_INS_CBW + "cdq", // X86_INS_CDQ + "cdqe", // X86_INS_CDQE + "fchs", // X86_INS_FCHS + "clac", // X86_INS_CLAC + "clc", // X86_INS_CLC + "cld", // X86_INS_CLD + "cldemote", // X86_INS_CLDEMOTE + "clflush", // X86_INS_CLFLUSH + "clflushopt", // X86_INS_CLFLUSHOPT + "clgi", // X86_INS_CLGI + "cli", // X86_INS_CLI + "clrssbsy", // X86_INS_CLRSSBSY + "clts", // X86_INS_CLTS + "clwb", // X86_INS_CLWB + "clzero", // X86_INS_CLZERO + "cmc", // X86_INS_CMC + "cmova", // X86_INS_CMOVA + "cmovae", // X86_INS_CMOVAE + "cmovb", // X86_INS_CMOVB + "cmovbe", // X86_INS_CMOVBE + "fcmovbe", // X86_INS_FCMOVBE + "fcmovb", // X86_INS_FCMOVB + "cmove", // X86_INS_CMOVE + "fcmove", // X86_INS_FCMOVE + "cmovg", // X86_INS_CMOVG + "cmovge", // X86_INS_CMOVGE + "cmovl", // X86_INS_CMOVL + "cmovle", // X86_INS_CMOVLE + "fcmovnbe", // X86_INS_FCMOVNBE + "fcmovnb", // X86_INS_FCMOVNB + "cmovne", // X86_INS_CMOVNE + "fcmovne", // X86_INS_FCMOVNE + "cmovno", // X86_INS_CMOVNO + "cmovnp", // X86_INS_CMOVNP + "fcmovnu", // X86_INS_FCMOVNU + "fcmovnp", // X86_INS_FCMOVNP + "cmovns", // X86_INS_CMOVNS + "cmovo", // X86_INS_CMOVO + "cmovp", // X86_INS_CMOVP + "fcmovu", // X86_INS_FCMOVU + "cmovs", // X86_INS_CMOVS + "cmp", // X86_INS_CMP + "cmppd", // X86_INS_CMPPD + "cmpps", // X86_INS_CMPPS + "cmpsb", // X86_INS_CMPSB + "cmpsd", // X86_INS_CMPSD + "cmpsq", // X86_INS_CMPSQ + "cmpss", // X86_INS_CMPSS + "cmpsw", // X86_INS_CMPSW + "cmpxchg16b", // X86_INS_CMPXCHG16B + "cmpxchg", // X86_INS_CMPXCHG + "cmpxchg8b", // X86_INS_CMPXCHG8B + "comisd", // X86_INS_COMISD + "comiss", // X86_INS_COMISS + "fcomp", // X86_INS_FCOMP + "fcompi", // X86_INS_FCOMPI + "fcomi", // X86_INS_FCOMI + "fcom", // X86_INS_FCOM + "fcos", // X86_INS_FCOS + "cpuid", // X86_INS_CPUID + "cqo", // X86_INS_CQO + "crc32", // X86_INS_CRC32 + "cvtdq2pd", // X86_INS_CVTDQ2PD + "cvtdq2ps", // X86_INS_CVTDQ2PS + "cvtpd2dq", // X86_INS_CVTPD2DQ + "cvtpd2ps", // X86_INS_CVTPD2PS + "cvtps2dq", // X86_INS_CVTPS2DQ + "cvtps2pd", // X86_INS_CVTPS2PD + "cvtsd2si", // X86_INS_CVTSD2SI + "cvtsd2ss", // X86_INS_CVTSD2SS + "cvtsi2sd", // X86_INS_CVTSI2SD + "cvtsi2ss", // X86_INS_CVTSI2SS + "cvtss2sd", // X86_INS_CVTSS2SD + "cvtss2si", // X86_INS_CVTSS2SI + "cvttpd2dq", // X86_INS_CVTTPD2DQ + "cvttps2dq", // X86_INS_CVTTPS2DQ + "cvttsd2si", // X86_INS_CVTTSD2SI + "cvttss2si", // X86_INS_CVTTSS2SI + "cwd", // X86_INS_CWD + "cwde", // X86_INS_CWDE + "daa", // X86_INS_DAA + "das", // X86_INS_DAS + "data16", // X86_INS_DATA16 + "dec", // X86_INS_DEC + "div", // X86_INS_DIV + "divpd", // X86_INS_DIVPD + "divps", // X86_INS_DIVPS + "fdivr", // X86_INS_FDIVR + "fidivr", // X86_INS_FIDIVR + "fdivrp", // X86_INS_FDIVRP + "divsd", // X86_INS_DIVSD + "divss", // X86_INS_DIVSS + "fdiv", // X86_INS_FDIV + "fidiv", // X86_INS_FIDIV + "fdivp", // X86_INS_FDIVP + "dppd", // X86_INS_DPPD + "dpps", // X86_INS_DPPS + "encls", // X86_INS_ENCLS + "enclu", // X86_INS_ENCLU + "enclv", // X86_INS_ENCLV + "endbr32", // X86_INS_ENDBR32 + "endbr64", // X86_INS_ENDBR64 + "enter", // X86_INS_ENTER + "extractps", // X86_INS_EXTRACTPS + "extrq", // X86_INS_EXTRQ + "f2xm1", // X86_INS_F2XM1 + "lcall", // X86_INS_LCALL + "ljmp", // X86_INS_LJMP + "jmp", // X86_INS_JMP + "fbld", // X86_INS_FBLD + "fbstp", // X86_INS_FBSTP + "fcompp", // X86_INS_FCOMPP + "fdecstp", // X86_INS_FDECSTP + "fdisi8087_nop", // X86_INS_FDISI8087_NOP + "femms", // X86_INS_FEMMS + "feni8087_nop", // X86_INS_FENI8087_NOP + "ffree", // X86_INS_FFREE + "ffreep", // X86_INS_FFREEP + "ficom", // X86_INS_FICOM + "ficomp", // X86_INS_FICOMP + "fincstp", // X86_INS_FINCSTP + "fldcw", // X86_INS_FLDCW + "fldenv", // X86_INS_FLDENV + "fldl2e", // X86_INS_FLDL2E + "fldl2t", // X86_INS_FLDL2T + "fldlg2", // X86_INS_FLDLG2 + "fldln2", // X86_INS_FLDLN2 + "fldpi", // X86_INS_FLDPI + "fnclex", // X86_INS_FNCLEX + "fninit", // X86_INS_FNINIT + "fnop", // X86_INS_FNOP + "fnstcw", // X86_INS_FNSTCW + "fnstsw", // X86_INS_FNSTSW + "fpatan", // X86_INS_FPATAN + "fstpnce", // X86_INS_FSTPNCE + "fprem", // X86_INS_FPREM + "fprem1", // X86_INS_FPREM1 + "fptan", // X86_INS_FPTAN + "frndint", // X86_INS_FRNDINT + "frstor", // X86_INS_FRSTOR + "fnsave", // X86_INS_FNSAVE + "fscale", // X86_INS_FSCALE + "fsetpm", // X86_INS_FSETPM + "fsincos", // X86_INS_FSINCOS + "fnstenv", // X86_INS_FNSTENV + "fxam", // X86_INS_FXAM + "fxrstor", // X86_INS_FXRSTOR + "fxrstor64", // X86_INS_FXRSTOR64 + "fxsave", // X86_INS_FXSAVE + "fxsave64", // X86_INS_FXSAVE64 + "fxtract", // X86_INS_FXTRACT + "fyl2x", // X86_INS_FYL2X + "fyl2xp1", // X86_INS_FYL2XP1 + "getsec", // X86_INS_GETSEC + "gf2p8affineinvqb", // X86_INS_GF2P8AFFINEINVQB + "gf2p8affineqb", // X86_INS_GF2P8AFFINEQB + "gf2p8mulb", // X86_INS_GF2P8MULB + "haddpd", // X86_INS_HADDPD + "haddps", // X86_INS_HADDPS + "hlt", // X86_INS_HLT + "hsubpd", // X86_INS_HSUBPD + "hsubps", // X86_INS_HSUBPS + "idiv", // X86_INS_IDIV + "fild", // X86_INS_FILD + "imul", // X86_INS_IMUL + "in", // X86_INS_IN + "inc", // X86_INS_INC + "incsspd", // X86_INS_INCSSPD + "incsspq", // X86_INS_INCSSPQ + "insb", // X86_INS_INSB + "insertps", // X86_INS_INSERTPS + "insertq", // X86_INS_INSERTQ + "insd", // X86_INS_INSD + "insw", // X86_INS_INSW + "int", // X86_INS_INT + "int1", // X86_INS_INT1 + "int3", // X86_INS_INT3 + "into", // X86_INS_INTO + "invd", // X86_INS_INVD + "invept", // X86_INS_INVEPT + "invlpg", // X86_INS_INVLPG + "invlpga", // X86_INS_INVLPGA + "invpcid", // X86_INS_INVPCID + "invvpid", // X86_INS_INVVPID + "iret", // X86_INS_IRET + "iretd", // X86_INS_IRETD + "iretq", // X86_INS_IRETQ + "fisttp", // X86_INS_FISTTP + "fist", // X86_INS_FIST + "fistp", // X86_INS_FISTP + "jae", // X86_INS_JAE + "ja", // X86_INS_JA + "jbe", // X86_INS_JBE + "jb", // X86_INS_JB + "jcxz", // X86_INS_JCXZ + "jecxz", // X86_INS_JECXZ + "je", // X86_INS_JE + "jge", // X86_INS_JGE + "jg", // X86_INS_JG + "jle", // X86_INS_JLE + "jl", // X86_INS_JL + "jne", // X86_INS_JNE + "jno", // X86_INS_JNO + "jnp", // X86_INS_JNP + "jns", // X86_INS_JNS + "jo", // X86_INS_JO + "jp", // X86_INS_JP + "jrcxz", // X86_INS_JRCXZ + "js", // X86_INS_JS + "kaddb", // X86_INS_KADDB + "kaddd", // X86_INS_KADDD + "kaddq", // X86_INS_KADDQ + "kaddw", // X86_INS_KADDW + "kandb", // X86_INS_KANDB + "kandd", // X86_INS_KANDD + "kandnb", // X86_INS_KANDNB + "kandnd", // X86_INS_KANDND + "kandnq", // X86_INS_KANDNQ + "kandnw", // X86_INS_KANDNW + "kandq", // X86_INS_KANDQ + "kandw", // X86_INS_KANDW + "kmovb", // X86_INS_KMOVB + "kmovd", // X86_INS_KMOVD + "kmovq", // X86_INS_KMOVQ + "kmovw", // X86_INS_KMOVW + "knotb", // X86_INS_KNOTB + "knotd", // X86_INS_KNOTD + "knotq", // X86_INS_KNOTQ + "knotw", // X86_INS_KNOTW + "korb", // X86_INS_KORB + "kord", // X86_INS_KORD + "korq", // X86_INS_KORQ + "kortestb", // X86_INS_KORTESTB + "kortestd", // X86_INS_KORTESTD + "kortestq", // X86_INS_KORTESTQ + "kortestw", // X86_INS_KORTESTW + "korw", // X86_INS_KORW + "kshiftlb", // X86_INS_KSHIFTLB + "kshiftld", // X86_INS_KSHIFTLD + "kshiftlq", // X86_INS_KSHIFTLQ + "kshiftlw", // X86_INS_KSHIFTLW + "kshiftrb", // X86_INS_KSHIFTRB + "kshiftrd", // X86_INS_KSHIFTRD + "kshiftrq", // X86_INS_KSHIFTRQ + "kshiftrw", // X86_INS_KSHIFTRW + "ktestb", // X86_INS_KTESTB + "ktestd", // X86_INS_KTESTD + "ktestq", // X86_INS_KTESTQ + "ktestw", // X86_INS_KTESTW + "kunpckbw", // X86_INS_KUNPCKBW + "kunpckdq", // X86_INS_KUNPCKDQ + "kunpckwd", // X86_INS_KUNPCKWD + "kxnorb", // X86_INS_KXNORB + "kxnord", // X86_INS_KXNORD + "kxnorq", // X86_INS_KXNORQ + "kxnorw", // X86_INS_KXNORW + "kxorb", // X86_INS_KXORB + "kxord", // X86_INS_KXORD + "kxorq", // X86_INS_KXORQ + "kxorw", // X86_INS_KXORW + "lahf", // X86_INS_LAHF + "lar", // X86_INS_LAR + "lddqu", // X86_INS_LDDQU + "ldmxcsr", // X86_INS_LDMXCSR + "lds", // X86_INS_LDS + "fldz", // X86_INS_FLDZ + "fld1", // X86_INS_FLD1 + "fld", // X86_INS_FLD + "lea", // X86_INS_LEA + "leave", // X86_INS_LEAVE + "les", // X86_INS_LES + "lfence", // X86_INS_LFENCE + "lfs", // X86_INS_LFS + "lgdt", // X86_INS_LGDT + "lgs", // X86_INS_LGS + "lidt", // X86_INS_LIDT + "lldt", // X86_INS_LLDT + "llwpcb", // X86_INS_LLWPCB + "lmsw", // X86_INS_LMSW + "lock", // X86_INS_LOCK + "lodsb", // X86_INS_LODSB + "lodsd", // X86_INS_LODSD + "lodsq", // X86_INS_LODSQ + "lodsw", // X86_INS_LODSW + "loop", // X86_INS_LOOP + "loope", // X86_INS_LOOPE + "loopne", // X86_INS_LOOPNE + "retf", // X86_INS_RETF + "retfq", // X86_INS_RETFQ + "lsl", // X86_INS_LSL + "lss", // X86_INS_LSS + "ltr", // X86_INS_LTR + "lwpins", // X86_INS_LWPINS + "lwpval", // X86_INS_LWPVAL + "lzcnt", // X86_INS_LZCNT + "maskmovdqu", // X86_INS_MASKMOVDQU + "maxpd", // X86_INS_MAXPD + "maxps", // X86_INS_MAXPS + "maxsd", // X86_INS_MAXSD + "maxss", // X86_INS_MAXSS + "mfence", // X86_INS_MFENCE + "minpd", // X86_INS_MINPD + "minps", // X86_INS_MINPS + "minsd", // X86_INS_MINSD + "minss", // X86_INS_MINSS + "cvtpd2pi", // X86_INS_CVTPD2PI + "cvtpi2pd", // X86_INS_CVTPI2PD + "cvtpi2ps", // X86_INS_CVTPI2PS + "cvtps2pi", // X86_INS_CVTPS2PI + "cvttpd2pi", // X86_INS_CVTTPD2PI + "cvttps2pi", // X86_INS_CVTTPS2PI + "emms", // X86_INS_EMMS + "maskmovq", // X86_INS_MASKMOVQ + "movd", // X86_INS_MOVD + "movq", // X86_INS_MOVQ + "movdq2q", // X86_INS_MOVDQ2Q + "movntq", // X86_INS_MOVNTQ + "movq2dq", // X86_INS_MOVQ2DQ + "pabsb", // X86_INS_PABSB + "pabsd", // X86_INS_PABSD + "pabsw", // X86_INS_PABSW + "packssdw", // X86_INS_PACKSSDW + "packsswb", // X86_INS_PACKSSWB + "packuswb", // X86_INS_PACKUSWB + "paddb", // X86_INS_PADDB + "paddd", // X86_INS_PADDD + "paddq", // X86_INS_PADDQ + "paddsb", // X86_INS_PADDSB + "paddsw", // X86_INS_PADDSW + "paddusb", // X86_INS_PADDUSB + "paddusw", // X86_INS_PADDUSW + "paddw", // X86_INS_PADDW + "palignr", // X86_INS_PALIGNR + "pandn", // X86_INS_PANDN + "pand", // X86_INS_PAND + "pavgb", // X86_INS_PAVGB + "pavgw", // X86_INS_PAVGW + "pcmpeqb", // X86_INS_PCMPEQB + "pcmpeqd", // X86_INS_PCMPEQD + "pcmpeqw", // X86_INS_PCMPEQW + "pcmpgtb", // X86_INS_PCMPGTB + "pcmpgtd", // X86_INS_PCMPGTD + "pcmpgtw", // X86_INS_PCMPGTW + "pextrw", // X86_INS_PEXTRW + "phaddd", // X86_INS_PHADDD + "phaddsw", // X86_INS_PHADDSW + "phaddw", // X86_INS_PHADDW + "phsubd", // X86_INS_PHSUBD + "phsubsw", // X86_INS_PHSUBSW + "phsubw", // X86_INS_PHSUBW + "pinsrw", // X86_INS_PINSRW + "pmaddubsw", // X86_INS_PMADDUBSW + "pmaddwd", // X86_INS_PMADDWD + "pmaxsw", // X86_INS_PMAXSW + "pmaxub", // X86_INS_PMAXUB + "pminsw", // X86_INS_PMINSW + "pminub", // X86_INS_PMINUB + "pmovmskb", // X86_INS_PMOVMSKB + "pmulhrsw", // X86_INS_PMULHRSW + "pmulhuw", // X86_INS_PMULHUW + "pmulhw", // X86_INS_PMULHW + "pmullw", // X86_INS_PMULLW + "pmuludq", // X86_INS_PMULUDQ + "por", // X86_INS_POR + "psadbw", // X86_INS_PSADBW + "pshufb", // X86_INS_PSHUFB + "pshufw", // X86_INS_PSHUFW + "psignb", // X86_INS_PSIGNB + "psignd", // X86_INS_PSIGND + "psignw", // X86_INS_PSIGNW + "pslld", // X86_INS_PSLLD + "psllq", // X86_INS_PSLLQ + "psllw", // X86_INS_PSLLW + "psrad", // X86_INS_PSRAD + "psraw", // X86_INS_PSRAW + "psrld", // X86_INS_PSRLD + "psrlq", // X86_INS_PSRLQ + "psrlw", // X86_INS_PSRLW + "psubb", // X86_INS_PSUBB + "psubd", // X86_INS_PSUBD + "psubq", // X86_INS_PSUBQ + "psubsb", // X86_INS_PSUBSB + "psubsw", // X86_INS_PSUBSW + "psubusb", // X86_INS_PSUBUSB + "psubusw", // X86_INS_PSUBUSW + "psubw", // X86_INS_PSUBW + "punpckhbw", // X86_INS_PUNPCKHBW + "punpckhdq", // X86_INS_PUNPCKHDQ + "punpckhwd", // X86_INS_PUNPCKHWD + "punpcklbw", // X86_INS_PUNPCKLBW + "punpckldq", // X86_INS_PUNPCKLDQ + "punpcklwd", // X86_INS_PUNPCKLWD + "pxor", // X86_INS_PXOR + "monitorx", // X86_INS_MONITORX + "monitor", // X86_INS_MONITOR + "montmul", // X86_INS_MONTMUL + "mov", // X86_INS_MOV + "movabs", // X86_INS_MOVABS + "movapd", // X86_INS_MOVAPD + "movaps", // X86_INS_MOVAPS + "movbe", // X86_INS_MOVBE + "movddup", // X86_INS_MOVDDUP + "movdir64b", // X86_INS_MOVDIR64B + "movdiri", // X86_INS_MOVDIRI + "movdqa", // X86_INS_MOVDQA + "movdqu", // X86_INS_MOVDQU + "movhlps", // X86_INS_MOVHLPS + "movhpd", // X86_INS_MOVHPD + "movhps", // X86_INS_MOVHPS + "movlhps", // X86_INS_MOVLHPS + "movlpd", // X86_INS_MOVLPD + "movlps", // X86_INS_MOVLPS + "movmskpd", // X86_INS_MOVMSKPD + "movmskps", // X86_INS_MOVMSKPS + "movntdqa", // X86_INS_MOVNTDQA + "movntdq", // X86_INS_MOVNTDQ + "movnti", // X86_INS_MOVNTI + "movntpd", // X86_INS_MOVNTPD + "movntps", // X86_INS_MOVNTPS + "movntsd", // X86_INS_MOVNTSD + "movntss", // X86_INS_MOVNTSS + "movsb", // X86_INS_MOVSB + "movsd", // X86_INS_MOVSD + "movshdup", // X86_INS_MOVSHDUP + "movsldup", // X86_INS_MOVSLDUP + "movsq", // X86_INS_MOVSQ + "movss", // X86_INS_MOVSS + "movsw", // X86_INS_MOVSW + "movsx", // X86_INS_MOVSX + "movsxd", // X86_INS_MOVSXD + "movupd", // X86_INS_MOVUPD + "movups", // X86_INS_MOVUPS + "movzx", // X86_INS_MOVZX + "mpsadbw", // X86_INS_MPSADBW + "mul", // X86_INS_MUL + "mulpd", // X86_INS_MULPD + "mulps", // X86_INS_MULPS + "mulsd", // X86_INS_MULSD + "mulss", // X86_INS_MULSS + "mulx", // X86_INS_MULX + "fmul", // X86_INS_FMUL + "fimul", // X86_INS_FIMUL + "fmulp", // X86_INS_FMULP + "mwaitx", // X86_INS_MWAITX + "mwait", // X86_INS_MWAIT + "neg", // X86_INS_NEG + "nop", // X86_INS_NOP + "not", // X86_INS_NOT + "or", // X86_INS_OR + "orpd", // X86_INS_ORPD + "orps", // X86_INS_ORPS + "out", // X86_INS_OUT + "outsb", // X86_INS_OUTSB + "outsd", // X86_INS_OUTSD + "outsw", // X86_INS_OUTSW + "packusdw", // X86_INS_PACKUSDW + "pause", // X86_INS_PAUSE + "pavgusb", // X86_INS_PAVGUSB + "pblendvb", // X86_INS_PBLENDVB + "pblendw", // X86_INS_PBLENDW + "pclmulqdq", // X86_INS_PCLMULQDQ + "pcmpeqq", // X86_INS_PCMPEQQ + "pcmpestri", // X86_INS_PCMPESTRI + "pcmpestrm", // X86_INS_PCMPESTRM + "pcmpgtq", // X86_INS_PCMPGTQ + "pcmpistri", // X86_INS_PCMPISTRI + "pcmpistrm", // X86_INS_PCMPISTRM + "pconfig", // X86_INS_PCONFIG + "pdep", // X86_INS_PDEP + "pext", // X86_INS_PEXT + "pextrb", // X86_INS_PEXTRB + "pextrd", // X86_INS_PEXTRD + "pextrq", // X86_INS_PEXTRQ + "pf2id", // X86_INS_PF2ID + "pf2iw", // X86_INS_PF2IW + "pfacc", // X86_INS_PFACC + "pfadd", // X86_INS_PFADD + "pfcmpeq", // X86_INS_PFCMPEQ + "pfcmpge", // X86_INS_PFCMPGE + "pfcmpgt", // X86_INS_PFCMPGT + "pfmax", // X86_INS_PFMAX + "pfmin", // X86_INS_PFMIN + "pfmul", // X86_INS_PFMUL + "pfnacc", // X86_INS_PFNACC + "pfpnacc", // X86_INS_PFPNACC + "pfrcpit1", // X86_INS_PFRCPIT1 + "pfrcpit2", // X86_INS_PFRCPIT2 + "pfrcp", // X86_INS_PFRCP + "pfrsqit1", // X86_INS_PFRSQIT1 + "pfrsqrt", // X86_INS_PFRSQRT + "pfsubr", // X86_INS_PFSUBR + "pfsub", // X86_INS_PFSUB + "phminposuw", // X86_INS_PHMINPOSUW + "pi2fd", // X86_INS_PI2FD + "pi2fw", // X86_INS_PI2FW + "pinsrb", // X86_INS_PINSRB + "pinsrd", // X86_INS_PINSRD + "pinsrq", // X86_INS_PINSRQ + "pmaxsb", // X86_INS_PMAXSB + "pmaxsd", // X86_INS_PMAXSD + "pmaxud", // X86_INS_PMAXUD + "pmaxuw", // X86_INS_PMAXUW + "pminsb", // X86_INS_PMINSB + "pminsd", // X86_INS_PMINSD + "pminud", // X86_INS_PMINUD + "pminuw", // X86_INS_PMINUW + "pmovsxbd", // X86_INS_PMOVSXBD + "pmovsxbq", // X86_INS_PMOVSXBQ + "pmovsxbw", // X86_INS_PMOVSXBW + "pmovsxdq", // X86_INS_PMOVSXDQ + "pmovsxwd", // X86_INS_PMOVSXWD + "pmovsxwq", // X86_INS_PMOVSXWQ + "pmovzxbd", // X86_INS_PMOVZXBD + "pmovzxbq", // X86_INS_PMOVZXBQ + "pmovzxbw", // X86_INS_PMOVZXBW + "pmovzxdq", // X86_INS_PMOVZXDQ + "pmovzxwd", // X86_INS_PMOVZXWD + "pmovzxwq", // X86_INS_PMOVZXWQ + "pmuldq", // X86_INS_PMULDQ + "pmulhrw", // X86_INS_PMULHRW + "pmulld", // X86_INS_PMULLD + "pop", // X86_INS_POP + "popaw", // X86_INS_POPAW + "popal", // X86_INS_POPAL + "popcnt", // X86_INS_POPCNT + "popf", // X86_INS_POPF + "popfd", // X86_INS_POPFD + "popfq", // X86_INS_POPFQ + "prefetch", // X86_INS_PREFETCH + "prefetchnta", // X86_INS_PREFETCHNTA + "prefetcht0", // X86_INS_PREFETCHT0 + "prefetcht1", // X86_INS_PREFETCHT1 + "prefetcht2", // X86_INS_PREFETCHT2 + "prefetchw", // X86_INS_PREFETCHW + "prefetchwt1", // X86_INS_PREFETCHWT1 + "pshufd", // X86_INS_PSHUFD + "pshufhw", // X86_INS_PSHUFHW + "pshuflw", // X86_INS_PSHUFLW + "pslldq", // X86_INS_PSLLDQ + "psrldq", // X86_INS_PSRLDQ + "pswapd", // X86_INS_PSWAPD + "ptest", // X86_INS_PTEST + "ptwrite", // X86_INS_PTWRITE + "punpckhqdq", // X86_INS_PUNPCKHQDQ + "punpcklqdq", // X86_INS_PUNPCKLQDQ + "push", // X86_INS_PUSH + "pushaw", // X86_INS_PUSHAW + "pushal", // X86_INS_PUSHAL + "pushf", // X86_INS_PUSHF + "pushfd", // X86_INS_PUSHFD + "pushfq", // X86_INS_PUSHFQ + "rcl", // X86_INS_RCL + "rcpps", // X86_INS_RCPPS + "rcpss", // X86_INS_RCPSS + "rcr", // X86_INS_RCR + "rdfsbase", // X86_INS_RDFSBASE + "rdgsbase", // X86_INS_RDGSBASE + "rdmsr", // X86_INS_RDMSR + "rdpid", // X86_INS_RDPID + "rdpkru", // X86_INS_RDPKRU + "rdpmc", // X86_INS_RDPMC + "rdrand", // X86_INS_RDRAND + "rdseed", // X86_INS_RDSEED + "rdsspd", // X86_INS_RDSSPD + "rdsspq", // X86_INS_RDSSPQ + "rdtsc", // X86_INS_RDTSC + "rdtscp", // X86_INS_RDTSCP + "repne", // X86_INS_REPNE + "rep", // X86_INS_REP + "ret", // X86_INS_RET + "rex64", // X86_INS_REX64 + "rol", // X86_INS_ROL + "ror", // X86_INS_ROR + "rorx", // X86_INS_RORX + "roundpd", // X86_INS_ROUNDPD + "roundps", // X86_INS_ROUNDPS + "roundsd", // X86_INS_ROUNDSD + "roundss", // X86_INS_ROUNDSS + "rsm", // X86_INS_RSM + "rsqrtps", // X86_INS_RSQRTPS + "rsqrtss", // X86_INS_RSQRTSS + "rstorssp", // X86_INS_RSTORSSP + "sahf", // X86_INS_SAHF + "sal", // X86_INS_SAL + "salc", // X86_INS_SALC + "sar", // X86_INS_SAR + "sarx", // X86_INS_SARX + "saveprevssp", // X86_INS_SAVEPREVSSP + "sbb", // X86_INS_SBB + "scasb", // X86_INS_SCASB + "scasd", // X86_INS_SCASD + "scasq", // X86_INS_SCASQ + "scasw", // X86_INS_SCASW + "setae", // X86_INS_SETAE + "seta", // X86_INS_SETA + "setbe", // X86_INS_SETBE + "setb", // X86_INS_SETB + "sete", // X86_INS_SETE + "setge", // X86_INS_SETGE + "setg", // X86_INS_SETG + "setle", // X86_INS_SETLE + "setl", // X86_INS_SETL + "setne", // X86_INS_SETNE + "setno", // X86_INS_SETNO + "setnp", // X86_INS_SETNP + "setns", // X86_INS_SETNS + "seto", // X86_INS_SETO + "setp", // X86_INS_SETP + "setssbsy", // X86_INS_SETSSBSY + "sets", // X86_INS_SETS + "sfence", // X86_INS_SFENCE + "sgdt", // X86_INS_SGDT + "sha1msg1", // X86_INS_SHA1MSG1 + "sha1msg2", // X86_INS_SHA1MSG2 + "sha1nexte", // X86_INS_SHA1NEXTE + "sha1rnds4", // X86_INS_SHA1RNDS4 + "sha256msg1", // X86_INS_SHA256MSG1 + "sha256msg2", // X86_INS_SHA256MSG2 + "sha256rnds2", // X86_INS_SHA256RNDS2 + "shl", // X86_INS_SHL + "shld", // X86_INS_SHLD + "shlx", // X86_INS_SHLX + "shr", // X86_INS_SHR + "shrd", // X86_INS_SHRD + "shrx", // X86_INS_SHRX + "shufpd", // X86_INS_SHUFPD + "shufps", // X86_INS_SHUFPS + "sidt", // X86_INS_SIDT + "fsin", // X86_INS_FSIN + "skinit", // X86_INS_SKINIT + "sldt", // X86_INS_SLDT + "slwpcb", // X86_INS_SLWPCB + "smsw", // X86_INS_SMSW + "sqrtpd", // X86_INS_SQRTPD + "sqrtps", // X86_INS_SQRTPS + "sqrtsd", // X86_INS_SQRTSD + "sqrtss", // X86_INS_SQRTSS + "fsqrt", // X86_INS_FSQRT + "stac", // X86_INS_STAC + "stc", // X86_INS_STC + "std", // X86_INS_STD + "stgi", // X86_INS_STGI + "sti", // X86_INS_STI + "stmxcsr", // X86_INS_STMXCSR + "stosb", // X86_INS_STOSB + "stosd", // X86_INS_STOSD + "stosq", // X86_INS_STOSQ + "stosw", // X86_INS_STOSW + "str", // X86_INS_STR + "fst", // X86_INS_FST + "fstp", // X86_INS_FSTP + "sub", // X86_INS_SUB + "subpd", // X86_INS_SUBPD + "subps", // X86_INS_SUBPS + "fsubr", // X86_INS_FSUBR + "fisubr", // X86_INS_FISUBR + "fsubrp", // X86_INS_FSUBRP + "subsd", // X86_INS_SUBSD + "subss", // X86_INS_SUBSS + "fsub", // X86_INS_FSUB + "fisub", // X86_INS_FISUB + "fsubp", // X86_INS_FSUBP + "swapgs", // X86_INS_SWAPGS + "syscall", // X86_INS_SYSCALL + "sysenter", // X86_INS_SYSENTER + "sysexit", // X86_INS_SYSEXIT + "sysexitq", // X86_INS_SYSEXITQ + "sysret", // X86_INS_SYSRET + "sysretq", // X86_INS_SYSRETQ + "t1mskc", // X86_INS_T1MSKC + "test", // X86_INS_TEST + "tpause", // X86_INS_TPAUSE + "ftst", // X86_INS_FTST + "tzcnt", // X86_INS_TZCNT + "tzmsk", // X86_INS_TZMSK + "ucomisd", // X86_INS_UCOMISD + "ucomiss", // X86_INS_UCOMISS + "fucompi", // X86_INS_FUCOMPI + "fucomi", // X86_INS_FUCOMI + "fucompp", // X86_INS_FUCOMPP + "fucomp", // X86_INS_FUCOMP + "fucom", // X86_INS_FUCOM + "ud0", // X86_INS_UD0 + "ud1", // X86_INS_UD1 + "ud2", // X86_INS_UD2 + "umonitor", // X86_INS_UMONITOR + "umwait", // X86_INS_UMWAIT + "unpckhpd", // X86_INS_UNPCKHPD + "unpckhps", // X86_INS_UNPCKHPS + "unpcklpd", // X86_INS_UNPCKLPD + "unpcklps", // X86_INS_UNPCKLPS + "v4fmaddps", // X86_INS_V4FMADDPS + "v4fmaddss", // X86_INS_V4FMADDSS + "v4fnmaddps", // X86_INS_V4FNMADDPS + "v4fnmaddss", // X86_INS_V4FNMADDSS + "vaddpd", // X86_INS_VADDPD + "vaddps", // X86_INS_VADDPS + "vaddsd", // X86_INS_VADDSD + "vaddss", // X86_INS_VADDSS + "vaddsubpd", // X86_INS_VADDSUBPD + "vaddsubps", // X86_INS_VADDSUBPS + "vaesdeclast", // X86_INS_VAESDECLAST + "vaesdec", // X86_INS_VAESDEC + "vaesenclast", // X86_INS_VAESENCLAST + "vaesenc", // X86_INS_VAESENC + "vaesimc", // X86_INS_VAESIMC + "vaeskeygenassist", // X86_INS_VAESKEYGENASSIST + "valignd", // X86_INS_VALIGND + "valignq", // X86_INS_VALIGNQ + "vandnpd", // X86_INS_VANDNPD + "vandnps", // X86_INS_VANDNPS + "vandpd", // X86_INS_VANDPD + "vandps", // X86_INS_VANDPS + "vblendmpd", // X86_INS_VBLENDMPD + "vblendmps", // X86_INS_VBLENDMPS + "vblendpd", // X86_INS_VBLENDPD + "vblendps", // X86_INS_VBLENDPS + "vblendvpd", // X86_INS_VBLENDVPD + "vblendvps", // X86_INS_VBLENDVPS + "vbroadcastf128", // X86_INS_VBROADCASTF128 + "vbroadcastf32x2", // X86_INS_VBROADCASTF32X2 + "vbroadcastf32x4", // X86_INS_VBROADCASTF32X4 + "vbroadcastf32x8", // X86_INS_VBROADCASTF32X8 + "vbroadcastf64x2", // X86_INS_VBROADCASTF64X2 + "vbroadcastf64x4", // X86_INS_VBROADCASTF64X4 + "vbroadcasti128", // X86_INS_VBROADCASTI128 + "vbroadcasti32x2", // X86_INS_VBROADCASTI32X2 + "vbroadcasti32x4", // X86_INS_VBROADCASTI32X4 + "vbroadcasti32x8", // X86_INS_VBROADCASTI32X8 + "vbroadcasti64x2", // X86_INS_VBROADCASTI64X2 + "vbroadcasti64x4", // X86_INS_VBROADCASTI64X4 + "vbroadcastsd", // X86_INS_VBROADCASTSD + "vbroadcastss", // X86_INS_VBROADCASTSS + "vcmp", // X86_INS_VCMP + "vcmppd", // X86_INS_VCMPPD + "vcmpps", // X86_INS_VCMPPS + "vcmpsd", // X86_INS_VCMPSD + "vcmpss", // X86_INS_VCMPSS + "vcomisd", // X86_INS_VCOMISD + "vcomiss", // X86_INS_VCOMISS + "vcompresspd", // X86_INS_VCOMPRESSPD + "vcompressps", // X86_INS_VCOMPRESSPS + "vcvtdq2pd", // X86_INS_VCVTDQ2PD + "vcvtdq2ps", // X86_INS_VCVTDQ2PS + "vcvtpd2dq", // X86_INS_VCVTPD2DQ + "vcvtpd2ps", // X86_INS_VCVTPD2PS + "vcvtpd2qq", // X86_INS_VCVTPD2QQ + "vcvtpd2udq", // X86_INS_VCVTPD2UDQ + "vcvtpd2uqq", // X86_INS_VCVTPD2UQQ + "vcvtph2ps", // X86_INS_VCVTPH2PS + "vcvtps2dq", // X86_INS_VCVTPS2DQ + "vcvtps2pd", // X86_INS_VCVTPS2PD + "vcvtps2ph", // X86_INS_VCVTPS2PH + "vcvtps2qq", // X86_INS_VCVTPS2QQ + "vcvtps2udq", // X86_INS_VCVTPS2UDQ + "vcvtps2uqq", // X86_INS_VCVTPS2UQQ + "vcvtqq2pd", // X86_INS_VCVTQQ2PD + "vcvtqq2ps", // X86_INS_VCVTQQ2PS + "vcvtsd2si", // X86_INS_VCVTSD2SI + "vcvtsd2ss", // X86_INS_VCVTSD2SS + "vcvtsd2usi", // X86_INS_VCVTSD2USI + "vcvtsi2sd", // X86_INS_VCVTSI2SD + "vcvtsi2ss", // X86_INS_VCVTSI2SS + "vcvtss2sd", // X86_INS_VCVTSS2SD + "vcvtss2si", // X86_INS_VCVTSS2SI + "vcvtss2usi", // X86_INS_VCVTSS2USI + "vcvttpd2dq", // X86_INS_VCVTTPD2DQ + "vcvttpd2qq", // X86_INS_VCVTTPD2QQ + "vcvttpd2udq", // X86_INS_VCVTTPD2UDQ + "vcvttpd2uqq", // X86_INS_VCVTTPD2UQQ + "vcvttps2dq", // X86_INS_VCVTTPS2DQ + "vcvttps2qq", // X86_INS_VCVTTPS2QQ + "vcvttps2udq", // X86_INS_VCVTTPS2UDQ + "vcvttps2uqq", // X86_INS_VCVTTPS2UQQ + "vcvttsd2si", // X86_INS_VCVTTSD2SI + "vcvttsd2usi", // X86_INS_VCVTTSD2USI + "vcvttss2si", // X86_INS_VCVTTSS2SI + "vcvttss2usi", // X86_INS_VCVTTSS2USI + "vcvtudq2pd", // X86_INS_VCVTUDQ2PD + "vcvtudq2ps", // X86_INS_VCVTUDQ2PS + "vcvtuqq2pd", // X86_INS_VCVTUQQ2PD + "vcvtuqq2ps", // X86_INS_VCVTUQQ2PS + "vcvtusi2sd", // X86_INS_VCVTUSI2SD + "vcvtusi2ss", // X86_INS_VCVTUSI2SS + "vdbpsadbw", // X86_INS_VDBPSADBW + "vdivpd", // X86_INS_VDIVPD + "vdivps", // X86_INS_VDIVPS + "vdivsd", // X86_INS_VDIVSD + "vdivss", // X86_INS_VDIVSS + "vdppd", // X86_INS_VDPPD + "vdpps", // X86_INS_VDPPS + "verr", // X86_INS_VERR + "verw", // X86_INS_VERW + "vexp2pd", // X86_INS_VEXP2PD + "vexp2ps", // X86_INS_VEXP2PS + "vexpandpd", // X86_INS_VEXPANDPD + "vexpandps", // X86_INS_VEXPANDPS + "vextractf128", // X86_INS_VEXTRACTF128 + "vextractf32x4", // X86_INS_VEXTRACTF32X4 + "vextractf32x8", // X86_INS_VEXTRACTF32X8 + "vextractf64x2", // X86_INS_VEXTRACTF64X2 + "vextractf64x4", // X86_INS_VEXTRACTF64X4 + "vextracti128", // X86_INS_VEXTRACTI128 + "vextracti32x4", // X86_INS_VEXTRACTI32X4 + "vextracti32x8", // X86_INS_VEXTRACTI32X8 + "vextracti64x2", // X86_INS_VEXTRACTI64X2 + "vextracti64x4", // X86_INS_VEXTRACTI64X4 + "vextractps", // X86_INS_VEXTRACTPS + "vfixupimmpd", // X86_INS_VFIXUPIMMPD + "vfixupimmps", // X86_INS_VFIXUPIMMPS + "vfixupimmsd", // X86_INS_VFIXUPIMMSD + "vfixupimmss", // X86_INS_VFIXUPIMMSS + "vfmadd132pd", // X86_INS_VFMADD132PD + "vfmadd132ps", // X86_INS_VFMADD132PS + "vfmadd132sd", // X86_INS_VFMADD132SD + "vfmadd132ss", // X86_INS_VFMADD132SS + "vfmadd213pd", // X86_INS_VFMADD213PD + "vfmadd213ps", // X86_INS_VFMADD213PS + "vfmadd213sd", // X86_INS_VFMADD213SD + "vfmadd213ss", // X86_INS_VFMADD213SS + "vfmadd231pd", // X86_INS_VFMADD231PD + "vfmadd231ps", // X86_INS_VFMADD231PS + "vfmadd231sd", // X86_INS_VFMADD231SD + "vfmadd231ss", // X86_INS_VFMADD231SS + "vfmaddpd", // X86_INS_VFMADDPD + "vfmaddps", // X86_INS_VFMADDPS + "vfmaddsd", // X86_INS_VFMADDSD + "vfmaddss", // X86_INS_VFMADDSS + "vfmaddsub132pd", // X86_INS_VFMADDSUB132PD + "vfmaddsub132ps", // X86_INS_VFMADDSUB132PS + "vfmaddsub213pd", // X86_INS_VFMADDSUB213PD + "vfmaddsub213ps", // X86_INS_VFMADDSUB213PS + "vfmaddsub231pd", // X86_INS_VFMADDSUB231PD + "vfmaddsub231ps", // X86_INS_VFMADDSUB231PS + "vfmaddsubpd", // X86_INS_VFMADDSUBPD + "vfmaddsubps", // X86_INS_VFMADDSUBPS + "vfmsub132pd", // X86_INS_VFMSUB132PD + "vfmsub132ps", // X86_INS_VFMSUB132PS + "vfmsub132sd", // X86_INS_VFMSUB132SD + "vfmsub132ss", // X86_INS_VFMSUB132SS + "vfmsub213pd", // X86_INS_VFMSUB213PD + "vfmsub213ps", // X86_INS_VFMSUB213PS + "vfmsub213sd", // X86_INS_VFMSUB213SD + "vfmsub213ss", // X86_INS_VFMSUB213SS + "vfmsub231pd", // X86_INS_VFMSUB231PD + "vfmsub231ps", // X86_INS_VFMSUB231PS + "vfmsub231sd", // X86_INS_VFMSUB231SD + "vfmsub231ss", // X86_INS_VFMSUB231SS + "vfmsubadd132pd", // X86_INS_VFMSUBADD132PD + "vfmsubadd132ps", // X86_INS_VFMSUBADD132PS + "vfmsubadd213pd", // X86_INS_VFMSUBADD213PD + "vfmsubadd213ps", // X86_INS_VFMSUBADD213PS + "vfmsubadd231pd", // X86_INS_VFMSUBADD231PD + "vfmsubadd231ps", // X86_INS_VFMSUBADD231PS + "vfmsubaddpd", // X86_INS_VFMSUBADDPD + "vfmsubaddps", // X86_INS_VFMSUBADDPS + "vfmsubpd", // X86_INS_VFMSUBPD + "vfmsubps", // X86_INS_VFMSUBPS + "vfmsubsd", // X86_INS_VFMSUBSD + "vfmsubss", // X86_INS_VFMSUBSS + "vfnmadd132pd", // X86_INS_VFNMADD132PD + "vfnmadd132ps", // X86_INS_VFNMADD132PS + "vfnmadd132sd", // X86_INS_VFNMADD132SD + "vfnmadd132ss", // X86_INS_VFNMADD132SS + "vfnmadd213pd", // X86_INS_VFNMADD213PD + "vfnmadd213ps", // X86_INS_VFNMADD213PS + "vfnmadd213sd", // X86_INS_VFNMADD213SD + "vfnmadd213ss", // X86_INS_VFNMADD213SS + "vfnmadd231pd", // X86_INS_VFNMADD231PD + "vfnmadd231ps", // X86_INS_VFNMADD231PS + "vfnmadd231sd", // X86_INS_VFNMADD231SD + "vfnmadd231ss", // X86_INS_VFNMADD231SS + "vfnmaddpd", // X86_INS_VFNMADDPD + "vfnmaddps", // X86_INS_VFNMADDPS + "vfnmaddsd", // X86_INS_VFNMADDSD + "vfnmaddss", // X86_INS_VFNMADDSS + "vfnmsub132pd", // X86_INS_VFNMSUB132PD + "vfnmsub132ps", // X86_INS_VFNMSUB132PS + "vfnmsub132sd", // X86_INS_VFNMSUB132SD + "vfnmsub132ss", // X86_INS_VFNMSUB132SS + "vfnmsub213pd", // X86_INS_VFNMSUB213PD + "vfnmsub213ps", // X86_INS_VFNMSUB213PS + "vfnmsub213sd", // X86_INS_VFNMSUB213SD + "vfnmsub213ss", // X86_INS_VFNMSUB213SS + "vfnmsub231pd", // X86_INS_VFNMSUB231PD + "vfnmsub231ps", // X86_INS_VFNMSUB231PS + "vfnmsub231sd", // X86_INS_VFNMSUB231SD + "vfnmsub231ss", // X86_INS_VFNMSUB231SS + "vfnmsubpd", // X86_INS_VFNMSUBPD + "vfnmsubps", // X86_INS_VFNMSUBPS + "vfnmsubsd", // X86_INS_VFNMSUBSD + "vfnmsubss", // X86_INS_VFNMSUBSS + "vfpclasspd", // X86_INS_VFPCLASSPD + "vfpclassps", // X86_INS_VFPCLASSPS + "vfpclasssd", // X86_INS_VFPCLASSSD + "vfpclassss", // X86_INS_VFPCLASSSS + "vfrczpd", // X86_INS_VFRCZPD + "vfrczps", // X86_INS_VFRCZPS + "vfrczsd", // X86_INS_VFRCZSD + "vfrczss", // X86_INS_VFRCZSS + "vgatherdpd", // X86_INS_VGATHERDPD + "vgatherdps", // X86_INS_VGATHERDPS + "vgatherpf0dpd", // X86_INS_VGATHERPF0DPD + "vgatherpf0dps", // X86_INS_VGATHERPF0DPS + "vgatherpf0qpd", // X86_INS_VGATHERPF0QPD + "vgatherpf0qps", // X86_INS_VGATHERPF0QPS + "vgatherpf1dpd", // X86_INS_VGATHERPF1DPD + "vgatherpf1dps", // X86_INS_VGATHERPF1DPS + "vgatherpf1qpd", // X86_INS_VGATHERPF1QPD + "vgatherpf1qps", // X86_INS_VGATHERPF1QPS + "vgatherqpd", // X86_INS_VGATHERQPD + "vgatherqps", // X86_INS_VGATHERQPS + "vgetexppd", // X86_INS_VGETEXPPD + "vgetexpps", // X86_INS_VGETEXPPS + "vgetexpsd", // X86_INS_VGETEXPSD + "vgetexpss", // X86_INS_VGETEXPSS + "vgetmantpd", // X86_INS_VGETMANTPD + "vgetmantps", // X86_INS_VGETMANTPS + "vgetmantsd", // X86_INS_VGETMANTSD + "vgetmantss", // X86_INS_VGETMANTSS + "vgf2p8affineinvqb", // X86_INS_VGF2P8AFFINEINVQB + "vgf2p8affineqb", // X86_INS_VGF2P8AFFINEQB + "vgf2p8mulb", // X86_INS_VGF2P8MULB + "vhaddpd", // X86_INS_VHADDPD + "vhaddps", // X86_INS_VHADDPS + "vhsubpd", // X86_INS_VHSUBPD + "vhsubps", // X86_INS_VHSUBPS + "vinsertf128", // X86_INS_VINSERTF128 + "vinsertf32x4", // X86_INS_VINSERTF32X4 + "vinsertf32x8", // X86_INS_VINSERTF32X8 + "vinsertf64x2", // X86_INS_VINSERTF64X2 + "vinsertf64x4", // X86_INS_VINSERTF64X4 + "vinserti128", // X86_INS_VINSERTI128 + "vinserti32x4", // X86_INS_VINSERTI32X4 + "vinserti32x8", // X86_INS_VINSERTI32X8 + "vinserti64x2", // X86_INS_VINSERTI64X2 + "vinserti64x4", // X86_INS_VINSERTI64X4 + "vinsertps", // X86_INS_VINSERTPS + "vlddqu", // X86_INS_VLDDQU + "vldmxcsr", // X86_INS_VLDMXCSR + "vmaskmovdqu", // X86_INS_VMASKMOVDQU + "vmaskmovpd", // X86_INS_VMASKMOVPD + "vmaskmovps", // X86_INS_VMASKMOVPS + "vmaxpd", // X86_INS_VMAXPD + "vmaxps", // X86_INS_VMAXPS + "vmaxsd", // X86_INS_VMAXSD + "vmaxss", // X86_INS_VMAXSS + "vmcall", // X86_INS_VMCALL + "vmclear", // X86_INS_VMCLEAR + "vmfunc", // X86_INS_VMFUNC + "vminpd", // X86_INS_VMINPD + "vminps", // X86_INS_VMINPS + "vminsd", // X86_INS_VMINSD + "vminss", // X86_INS_VMINSS + "vmlaunch", // X86_INS_VMLAUNCH + "vmload", // X86_INS_VMLOAD + "vmmcall", // X86_INS_VMMCALL + "vmovq", // X86_INS_VMOVQ + "vmovapd", // X86_INS_VMOVAPD + "vmovaps", // X86_INS_VMOVAPS + "vmovddup", // X86_INS_VMOVDDUP + "vmovd", // X86_INS_VMOVD + "vmovdqa32", // X86_INS_VMOVDQA32 + "vmovdqa64", // X86_INS_VMOVDQA64 + "vmovdqa", // X86_INS_VMOVDQA + "vmovdqu16", // X86_INS_VMOVDQU16 + "vmovdqu32", // X86_INS_VMOVDQU32 + "vmovdqu64", // X86_INS_VMOVDQU64 + "vmovdqu8", // X86_INS_VMOVDQU8 + "vmovdqu", // X86_INS_VMOVDQU + "vmovhlps", // X86_INS_VMOVHLPS + "vmovhpd", // X86_INS_VMOVHPD + "vmovhps", // X86_INS_VMOVHPS + "vmovlhps", // X86_INS_VMOVLHPS + "vmovlpd", // X86_INS_VMOVLPD + "vmovlps", // X86_INS_VMOVLPS + "vmovmskpd", // X86_INS_VMOVMSKPD + "vmovmskps", // X86_INS_VMOVMSKPS + "vmovntdqa", // X86_INS_VMOVNTDQA + "vmovntdq", // X86_INS_VMOVNTDQ + "vmovntpd", // X86_INS_VMOVNTPD + "vmovntps", // X86_INS_VMOVNTPS + "vmovsd", // X86_INS_VMOVSD + "vmovshdup", // X86_INS_VMOVSHDUP + "vmovsldup", // X86_INS_VMOVSLDUP + "vmovss", // X86_INS_VMOVSS + "vmovupd", // X86_INS_VMOVUPD + "vmovups", // X86_INS_VMOVUPS + "vmpsadbw", // X86_INS_VMPSADBW + "vmptrld", // X86_INS_VMPTRLD + "vmptrst", // X86_INS_VMPTRST + "vmread", // X86_INS_VMREAD + "vmresume", // X86_INS_VMRESUME + "vmrun", // X86_INS_VMRUN + "vmsave", // X86_INS_VMSAVE + "vmulpd", // X86_INS_VMULPD + "vmulps", // X86_INS_VMULPS + "vmulsd", // X86_INS_VMULSD + "vmulss", // X86_INS_VMULSS + "vmwrite", // X86_INS_VMWRITE + "vmxoff", // X86_INS_VMXOFF + "vmxon", // X86_INS_VMXON + "vorpd", // X86_INS_VORPD + "vorps", // X86_INS_VORPS + "vp4dpwssds", // X86_INS_VP4DPWSSDS + "vp4dpwssd", // X86_INS_VP4DPWSSD + "vpabsb", // X86_INS_VPABSB + "vpabsd", // X86_INS_VPABSD + "vpabsq", // X86_INS_VPABSQ + "vpabsw", // X86_INS_VPABSW + "vpackssdw", // X86_INS_VPACKSSDW + "vpacksswb", // X86_INS_VPACKSSWB + "vpackusdw", // X86_INS_VPACKUSDW + "vpackuswb", // X86_INS_VPACKUSWB + "vpaddb", // X86_INS_VPADDB + "vpaddd", // X86_INS_VPADDD + "vpaddq", // X86_INS_VPADDQ + "vpaddsb", // X86_INS_VPADDSB + "vpaddsw", // X86_INS_VPADDSW + "vpaddusb", // X86_INS_VPADDUSB + "vpaddusw", // X86_INS_VPADDUSW + "vpaddw", // X86_INS_VPADDW + "vpalignr", // X86_INS_VPALIGNR + "vpandd", // X86_INS_VPANDD + "vpandnd", // X86_INS_VPANDND + "vpandnq", // X86_INS_VPANDNQ + "vpandn", // X86_INS_VPANDN + "vpandq", // X86_INS_VPANDQ + "vpand", // X86_INS_VPAND + "vpavgb", // X86_INS_VPAVGB + "vpavgw", // X86_INS_VPAVGW + "vpblendd", // X86_INS_VPBLENDD + "vpblendmb", // X86_INS_VPBLENDMB + "vpblendmd", // X86_INS_VPBLENDMD + "vpblendmq", // X86_INS_VPBLENDMQ + "vpblendmw", // X86_INS_VPBLENDMW + "vpblendvb", // X86_INS_VPBLENDVB + "vpblendw", // X86_INS_VPBLENDW + "vpbroadcastb", // X86_INS_VPBROADCASTB + "vpbroadcastd", // X86_INS_VPBROADCASTD + "vpbroadcastmb2q", // X86_INS_VPBROADCASTMB2Q + "vpbroadcastmw2d", // X86_INS_VPBROADCASTMW2D + "vpbroadcastq", // X86_INS_VPBROADCASTQ + "vpbroadcastw", // X86_INS_VPBROADCASTW + "vpclmulqdq", // X86_INS_VPCLMULQDQ + "vpcmov", // X86_INS_VPCMOV + "vpcmp", // X86_INS_VPCMP + "vpcmpb", // X86_INS_VPCMPB + "vpcmpd", // X86_INS_VPCMPD + "vpcmpeqb", // X86_INS_VPCMPEQB + "vpcmpeqd", // X86_INS_VPCMPEQD + "vpcmpeqq", // X86_INS_VPCMPEQQ + "vpcmpeqw", // X86_INS_VPCMPEQW + "vpcmpestri", // X86_INS_VPCMPESTRI + "vpcmpestrm", // X86_INS_VPCMPESTRM + "vpcmpgtb", // X86_INS_VPCMPGTB + "vpcmpgtd", // X86_INS_VPCMPGTD + "vpcmpgtq", // X86_INS_VPCMPGTQ + "vpcmpgtw", // X86_INS_VPCMPGTW + "vpcmpistri", // X86_INS_VPCMPISTRI + "vpcmpistrm", // X86_INS_VPCMPISTRM + "vpcmpq", // X86_INS_VPCMPQ + "vpcmpub", // X86_INS_VPCMPUB + "vpcmpud", // X86_INS_VPCMPUD + "vpcmpuq", // X86_INS_VPCMPUQ + "vpcmpuw", // X86_INS_VPCMPUW + "vpcmpw", // X86_INS_VPCMPW + "vpcom", // X86_INS_VPCOM + "vpcomb", // X86_INS_VPCOMB + "vpcomd", // X86_INS_VPCOMD + "vpcompressb", // X86_INS_VPCOMPRESSB + "vpcompressd", // X86_INS_VPCOMPRESSD + "vpcompressq", // X86_INS_VPCOMPRESSQ + "vpcompressw", // X86_INS_VPCOMPRESSW + "vpcomq", // X86_INS_VPCOMQ + "vpcomub", // X86_INS_VPCOMUB + "vpcomud", // X86_INS_VPCOMUD + "vpcomuq", // X86_INS_VPCOMUQ + "vpcomuw", // X86_INS_VPCOMUW + "vpcomw", // X86_INS_VPCOMW + "vpconflictd", // X86_INS_VPCONFLICTD + "vpconflictq", // X86_INS_VPCONFLICTQ + "vpdpbusds", // X86_INS_VPDPBUSDS + "vpdpbusd", // X86_INS_VPDPBUSD + "vpdpwssds", // X86_INS_VPDPWSSDS + "vpdpwssd", // X86_INS_VPDPWSSD + "vperm2f128", // X86_INS_VPERM2F128 + "vperm2i128", // X86_INS_VPERM2I128 + "vpermb", // X86_INS_VPERMB + "vpermd", // X86_INS_VPERMD + "vpermi2b", // X86_INS_VPERMI2B + "vpermi2d", // X86_INS_VPERMI2D + "vpermi2pd", // X86_INS_VPERMI2PD + "vpermi2ps", // X86_INS_VPERMI2PS + "vpermi2q", // X86_INS_VPERMI2Q + "vpermi2w", // X86_INS_VPERMI2W + "vpermil2pd", // X86_INS_VPERMIL2PD + "vpermilpd", // X86_INS_VPERMILPD + "vpermil2ps", // X86_INS_VPERMIL2PS + "vpermilps", // X86_INS_VPERMILPS + "vpermpd", // X86_INS_VPERMPD + "vpermps", // X86_INS_VPERMPS + "vpermq", // X86_INS_VPERMQ + "vpermt2b", // X86_INS_VPERMT2B + "vpermt2d", // X86_INS_VPERMT2D + "vpermt2pd", // X86_INS_VPERMT2PD + "vpermt2ps", // X86_INS_VPERMT2PS + "vpermt2q", // X86_INS_VPERMT2Q + "vpermt2w", // X86_INS_VPERMT2W + "vpermw", // X86_INS_VPERMW + "vpexpandb", // X86_INS_VPEXPANDB + "vpexpandd", // X86_INS_VPEXPANDD + "vpexpandq", // X86_INS_VPEXPANDQ + "vpexpandw", // X86_INS_VPEXPANDW + "vpextrb", // X86_INS_VPEXTRB + "vpextrd", // X86_INS_VPEXTRD + "vpextrq", // X86_INS_VPEXTRQ + "vpextrw", // X86_INS_VPEXTRW + "vpgatherdd", // X86_INS_VPGATHERDD + "vpgatherdq", // X86_INS_VPGATHERDQ + "vpgatherqd", // X86_INS_VPGATHERQD + "vpgatherqq", // X86_INS_VPGATHERQQ + "vphaddbd", // X86_INS_VPHADDBD + "vphaddbq", // X86_INS_VPHADDBQ + "vphaddbw", // X86_INS_VPHADDBW + "vphadddq", // X86_INS_VPHADDDQ + "vphaddd", // X86_INS_VPHADDD + "vphaddsw", // X86_INS_VPHADDSW + "vphaddubd", // X86_INS_VPHADDUBD + "vphaddubq", // X86_INS_VPHADDUBQ + "vphaddubw", // X86_INS_VPHADDUBW + "vphaddudq", // X86_INS_VPHADDUDQ + "vphadduwd", // X86_INS_VPHADDUWD + "vphadduwq", // X86_INS_VPHADDUWQ + "vphaddwd", // X86_INS_VPHADDWD + "vphaddwq", // X86_INS_VPHADDWQ + "vphaddw", // X86_INS_VPHADDW + "vphminposuw", // X86_INS_VPHMINPOSUW + "vphsubbw", // X86_INS_VPHSUBBW + "vphsubdq", // X86_INS_VPHSUBDQ + "vphsubd", // X86_INS_VPHSUBD + "vphsubsw", // X86_INS_VPHSUBSW + "vphsubwd", // X86_INS_VPHSUBWD + "vphsubw", // X86_INS_VPHSUBW + "vpinsrb", // X86_INS_VPINSRB + "vpinsrd", // X86_INS_VPINSRD + "vpinsrq", // X86_INS_VPINSRQ + "vpinsrw", // X86_INS_VPINSRW + "vplzcntd", // X86_INS_VPLZCNTD + "vplzcntq", // X86_INS_VPLZCNTQ + "vpmacsdd", // X86_INS_VPMACSDD + "vpmacsdqh", // X86_INS_VPMACSDQH + "vpmacsdql", // X86_INS_VPMACSDQL + "vpmacssdd", // X86_INS_VPMACSSDD + "vpmacssdqh", // X86_INS_VPMACSSDQH + "vpmacssdql", // X86_INS_VPMACSSDQL + "vpmacsswd", // X86_INS_VPMACSSWD + "vpmacssww", // X86_INS_VPMACSSWW + "vpmacswd", // X86_INS_VPMACSWD + "vpmacsww", // X86_INS_VPMACSWW + "vpmadcsswd", // X86_INS_VPMADCSSWD + "vpmadcswd", // X86_INS_VPMADCSWD + "vpmadd52huq", // X86_INS_VPMADD52HUQ + "vpmadd52luq", // X86_INS_VPMADD52LUQ + "vpmaddubsw", // X86_INS_VPMADDUBSW + "vpmaddwd", // X86_INS_VPMADDWD + "vpmaskmovd", // X86_INS_VPMASKMOVD + "vpmaskmovq", // X86_INS_VPMASKMOVQ + "vpmaxsb", // X86_INS_VPMAXSB + "vpmaxsd", // X86_INS_VPMAXSD + "vpmaxsq", // X86_INS_VPMAXSQ + "vpmaxsw", // X86_INS_VPMAXSW + "vpmaxub", // X86_INS_VPMAXUB + "vpmaxud", // X86_INS_VPMAXUD + "vpmaxuq", // X86_INS_VPMAXUQ + "vpmaxuw", // X86_INS_VPMAXUW + "vpminsb", // X86_INS_VPMINSB + "vpminsd", // X86_INS_VPMINSD + "vpminsq", // X86_INS_VPMINSQ + "vpminsw", // X86_INS_VPMINSW + "vpminub", // X86_INS_VPMINUB + "vpminud", // X86_INS_VPMINUD + "vpminuq", // X86_INS_VPMINUQ + "vpminuw", // X86_INS_VPMINUW + "vpmovb2m", // X86_INS_VPMOVB2M + "vpmovd2m", // X86_INS_VPMOVD2M + "vpmovdb", // X86_INS_VPMOVDB + "vpmovdw", // X86_INS_VPMOVDW + "vpmovm2b", // X86_INS_VPMOVM2B + "vpmovm2d", // X86_INS_VPMOVM2D + "vpmovm2q", // X86_INS_VPMOVM2Q + "vpmovm2w", // X86_INS_VPMOVM2W + "vpmovmskb", // X86_INS_VPMOVMSKB + "vpmovq2m", // X86_INS_VPMOVQ2M + "vpmovqb", // X86_INS_VPMOVQB + "vpmovqd", // X86_INS_VPMOVQD + "vpmovqw", // X86_INS_VPMOVQW + "vpmovsdb", // X86_INS_VPMOVSDB + "vpmovsdw", // X86_INS_VPMOVSDW + "vpmovsqb", // X86_INS_VPMOVSQB + "vpmovsqd", // X86_INS_VPMOVSQD + "vpmovsqw", // X86_INS_VPMOVSQW + "vpmovswb", // X86_INS_VPMOVSWB + "vpmovsxbd", // X86_INS_VPMOVSXBD + "vpmovsxbq", // X86_INS_VPMOVSXBQ + "vpmovsxbw", // X86_INS_VPMOVSXBW + "vpmovsxdq", // X86_INS_VPMOVSXDQ + "vpmovsxwd", // X86_INS_VPMOVSXWD + "vpmovsxwq", // X86_INS_VPMOVSXWQ + "vpmovusdb", // X86_INS_VPMOVUSDB + "vpmovusdw", // X86_INS_VPMOVUSDW + "vpmovusqb", // X86_INS_VPMOVUSQB + "vpmovusqd", // X86_INS_VPMOVUSQD + "vpmovusqw", // X86_INS_VPMOVUSQW + "vpmovuswb", // X86_INS_VPMOVUSWB + "vpmovw2m", // X86_INS_VPMOVW2M + "vpmovwb", // X86_INS_VPMOVWB + "vpmovzxbd", // X86_INS_VPMOVZXBD + "vpmovzxbq", // X86_INS_VPMOVZXBQ + "vpmovzxbw", // X86_INS_VPMOVZXBW + "vpmovzxdq", // X86_INS_VPMOVZXDQ + "vpmovzxwd", // X86_INS_VPMOVZXWD + "vpmovzxwq", // X86_INS_VPMOVZXWQ + "vpmuldq", // X86_INS_VPMULDQ + "vpmulhrsw", // X86_INS_VPMULHRSW + "vpmulhuw", // X86_INS_VPMULHUW + "vpmulhw", // X86_INS_VPMULHW + "vpmulld", // X86_INS_VPMULLD + "vpmullq", // X86_INS_VPMULLQ + "vpmullw", // X86_INS_VPMULLW + "vpmultishiftqb", // X86_INS_VPMULTISHIFTQB + "vpmuludq", // X86_INS_VPMULUDQ + "vpopcntb", // X86_INS_VPOPCNTB + "vpopcntd", // X86_INS_VPOPCNTD + "vpopcntq", // X86_INS_VPOPCNTQ + "vpopcntw", // X86_INS_VPOPCNTW + "vpord", // X86_INS_VPORD + "vporq", // X86_INS_VPORQ + "vpor", // X86_INS_VPOR + "vpperm", // X86_INS_VPPERM + "vprold", // X86_INS_VPROLD + "vprolq", // X86_INS_VPROLQ + "vprolvd", // X86_INS_VPROLVD + "vprolvq", // X86_INS_VPROLVQ + "vprord", // X86_INS_VPRORD + "vprorq", // X86_INS_VPRORQ + "vprorvd", // X86_INS_VPRORVD + "vprorvq", // X86_INS_VPRORVQ + "vprotb", // X86_INS_VPROTB + "vprotd", // X86_INS_VPROTD + "vprotq", // X86_INS_VPROTQ + "vprotw", // X86_INS_VPROTW + "vpsadbw", // X86_INS_VPSADBW + "vpscatterdd", // X86_INS_VPSCATTERDD + "vpscatterdq", // X86_INS_VPSCATTERDQ + "vpscatterqd", // X86_INS_VPSCATTERQD + "vpscatterqq", // X86_INS_VPSCATTERQQ + "vpshab", // X86_INS_VPSHAB + "vpshad", // X86_INS_VPSHAD + "vpshaq", // X86_INS_VPSHAQ + "vpshaw", // X86_INS_VPSHAW + "vpshlb", // X86_INS_VPSHLB + "vpshldd", // X86_INS_VPSHLDD + "vpshldq", // X86_INS_VPSHLDQ + "vpshldvd", // X86_INS_VPSHLDVD + "vpshldvq", // X86_INS_VPSHLDVQ + "vpshldvw", // X86_INS_VPSHLDVW + "vpshldw", // X86_INS_VPSHLDW + "vpshld", // X86_INS_VPSHLD + "vpshlq", // X86_INS_VPSHLQ + "vpshlw", // X86_INS_VPSHLW + "vpshrdd", // X86_INS_VPSHRDD + "vpshrdq", // X86_INS_VPSHRDQ + "vpshrdvd", // X86_INS_VPSHRDVD + "vpshrdvq", // X86_INS_VPSHRDVQ + "vpshrdvw", // X86_INS_VPSHRDVW + "vpshrdw", // X86_INS_VPSHRDW + "vpshufbitqmb", // X86_INS_VPSHUFBITQMB + "vpshufb", // X86_INS_VPSHUFB + "vpshufd", // X86_INS_VPSHUFD + "vpshufhw", // X86_INS_VPSHUFHW + "vpshuflw", // X86_INS_VPSHUFLW + "vpsignb", // X86_INS_VPSIGNB + "vpsignd", // X86_INS_VPSIGND + "vpsignw", // X86_INS_VPSIGNW + "vpslldq", // X86_INS_VPSLLDQ + "vpslld", // X86_INS_VPSLLD + "vpsllq", // X86_INS_VPSLLQ + "vpsllvd", // X86_INS_VPSLLVD + "vpsllvq", // X86_INS_VPSLLVQ + "vpsllvw", // X86_INS_VPSLLVW + "vpsllw", // X86_INS_VPSLLW + "vpsrad", // X86_INS_VPSRAD + "vpsraq", // X86_INS_VPSRAQ + "vpsravd", // X86_INS_VPSRAVD + "vpsravq", // X86_INS_VPSRAVQ + "vpsravw", // X86_INS_VPSRAVW + "vpsraw", // X86_INS_VPSRAW + "vpsrldq", // X86_INS_VPSRLDQ + "vpsrld", // X86_INS_VPSRLD + "vpsrlq", // X86_INS_VPSRLQ + "vpsrlvd", // X86_INS_VPSRLVD + "vpsrlvq", // X86_INS_VPSRLVQ + "vpsrlvw", // X86_INS_VPSRLVW + "vpsrlw", // X86_INS_VPSRLW + "vpsubb", // X86_INS_VPSUBB + "vpsubd", // X86_INS_VPSUBD + "vpsubq", // X86_INS_VPSUBQ + "vpsubsb", // X86_INS_VPSUBSB + "vpsubsw", // X86_INS_VPSUBSW + "vpsubusb", // X86_INS_VPSUBUSB + "vpsubusw", // X86_INS_VPSUBUSW + "vpsubw", // X86_INS_VPSUBW + "vpternlogd", // X86_INS_VPTERNLOGD + "vpternlogq", // X86_INS_VPTERNLOGQ + "vptestmb", // X86_INS_VPTESTMB + "vptestmd", // X86_INS_VPTESTMD + "vptestmq", // X86_INS_VPTESTMQ + "vptestmw", // X86_INS_VPTESTMW + "vptestnmb", // X86_INS_VPTESTNMB + "vptestnmd", // X86_INS_VPTESTNMD + "vptestnmq", // X86_INS_VPTESTNMQ + "vptestnmw", // X86_INS_VPTESTNMW + "vptest", // X86_INS_VPTEST + "vpunpckhbw", // X86_INS_VPUNPCKHBW + "vpunpckhdq", // X86_INS_VPUNPCKHDQ + "vpunpckhqdq", // X86_INS_VPUNPCKHQDQ + "vpunpckhwd", // X86_INS_VPUNPCKHWD + "vpunpcklbw", // X86_INS_VPUNPCKLBW + "vpunpckldq", // X86_INS_VPUNPCKLDQ + "vpunpcklqdq", // X86_INS_VPUNPCKLQDQ + "vpunpcklwd", // X86_INS_VPUNPCKLWD + "vpxord", // X86_INS_VPXORD + "vpxorq", // X86_INS_VPXORQ + "vpxor", // X86_INS_VPXOR + "vrangepd", // X86_INS_VRANGEPD + "vrangeps", // X86_INS_VRANGEPS + "vrangesd", // X86_INS_VRANGESD + "vrangess", // X86_INS_VRANGESS + "vrcp14pd", // X86_INS_VRCP14PD + "vrcp14ps", // X86_INS_VRCP14PS + "vrcp14sd", // X86_INS_VRCP14SD + "vrcp14ss", // X86_INS_VRCP14SS + "vrcp28pd", // X86_INS_VRCP28PD + "vrcp28ps", // X86_INS_VRCP28PS + "vrcp28sd", // X86_INS_VRCP28SD + "vrcp28ss", // X86_INS_VRCP28SS + "vrcpps", // X86_INS_VRCPPS + "vrcpss", // X86_INS_VRCPSS + "vreducepd", // X86_INS_VREDUCEPD + "vreduceps", // X86_INS_VREDUCEPS + "vreducesd", // X86_INS_VREDUCESD + "vreducess", // X86_INS_VREDUCESS + "vrndscalepd", // X86_INS_VRNDSCALEPD + "vrndscaleps", // X86_INS_VRNDSCALEPS + "vrndscalesd", // X86_INS_VRNDSCALESD + "vrndscaless", // X86_INS_VRNDSCALESS + "vroundpd", // X86_INS_VROUNDPD + "vroundps", // X86_INS_VROUNDPS + "vroundsd", // X86_INS_VROUNDSD + "vroundss", // X86_INS_VROUNDSS + "vrsqrt14pd", // X86_INS_VRSQRT14PD + "vrsqrt14ps", // X86_INS_VRSQRT14PS + "vrsqrt14sd", // X86_INS_VRSQRT14SD + "vrsqrt14ss", // X86_INS_VRSQRT14SS + "vrsqrt28pd", // X86_INS_VRSQRT28PD + "vrsqrt28ps", // X86_INS_VRSQRT28PS + "vrsqrt28sd", // X86_INS_VRSQRT28SD + "vrsqrt28ss", // X86_INS_VRSQRT28SS + "vrsqrtps", // X86_INS_VRSQRTPS + "vrsqrtss", // X86_INS_VRSQRTSS + "vscalefpd", // X86_INS_VSCALEFPD + "vscalefps", // X86_INS_VSCALEFPS + "vscalefsd", // X86_INS_VSCALEFSD + "vscalefss", // X86_INS_VSCALEFSS + "vscatterdpd", // X86_INS_VSCATTERDPD + "vscatterdps", // X86_INS_VSCATTERDPS + "vscatterpf0dpd", // X86_INS_VSCATTERPF0DPD + "vscatterpf0dps", // X86_INS_VSCATTERPF0DPS + "vscatterpf0qpd", // X86_INS_VSCATTERPF0QPD + "vscatterpf0qps", // X86_INS_VSCATTERPF0QPS + "vscatterpf1dpd", // X86_INS_VSCATTERPF1DPD + "vscatterpf1dps", // X86_INS_VSCATTERPF1DPS + "vscatterpf1qpd", // X86_INS_VSCATTERPF1QPD + "vscatterpf1qps", // X86_INS_VSCATTERPF1QPS + "vscatterqpd", // X86_INS_VSCATTERQPD + "vscatterqps", // X86_INS_VSCATTERQPS + "vshuff32x4", // X86_INS_VSHUFF32X4 + "vshuff64x2", // X86_INS_VSHUFF64X2 + "vshufi32x4", // X86_INS_VSHUFI32X4 + "vshufi64x2", // X86_INS_VSHUFI64X2 + "vshufpd", // X86_INS_VSHUFPD + "vshufps", // X86_INS_VSHUFPS + "vsqrtpd", // X86_INS_VSQRTPD + "vsqrtps", // X86_INS_VSQRTPS + "vsqrtsd", // X86_INS_VSQRTSD + "vsqrtss", // X86_INS_VSQRTSS + "vstmxcsr", // X86_INS_VSTMXCSR + "vsubpd", // X86_INS_VSUBPD + "vsubps", // X86_INS_VSUBPS + "vsubsd", // X86_INS_VSUBSD + "vsubss", // X86_INS_VSUBSS + "vtestpd", // X86_INS_VTESTPD + "vtestps", // X86_INS_VTESTPS + "vucomisd", // X86_INS_VUCOMISD + "vucomiss", // X86_INS_VUCOMISS + "vunpckhpd", // X86_INS_VUNPCKHPD + "vunpckhps", // X86_INS_VUNPCKHPS + "vunpcklpd", // X86_INS_VUNPCKLPD + "vunpcklps", // X86_INS_VUNPCKLPS + "vxorpd", // X86_INS_VXORPD + "vxorps", // X86_INS_VXORPS + "vzeroall", // X86_INS_VZEROALL + "vzeroupper", // X86_INS_VZEROUPPER + "wait", // X86_INS_WAIT + "wbinvd", // X86_INS_WBINVD + "wbnoinvd", // X86_INS_WBNOINVD + "wrfsbase", // X86_INS_WRFSBASE + "wrgsbase", // X86_INS_WRGSBASE + "wrmsr", // X86_INS_WRMSR + "wrpkru", // X86_INS_WRPKRU + "wrssd", // X86_INS_WRSSD + "wrssq", // X86_INS_WRSSQ + "wrussd", // X86_INS_WRUSSD + "wrussq", // X86_INS_WRUSSQ + "xabort", // X86_INS_XABORT + "xacquire", // X86_INS_XACQUIRE + "xadd", // X86_INS_XADD + "xbegin", // X86_INS_XBEGIN + "xchg", // X86_INS_XCHG + "fxch", // X86_INS_FXCH + "xcryptcbc", // X86_INS_XCRYPTCBC + "xcryptcfb", // X86_INS_XCRYPTCFB + "xcryptctr", // X86_INS_XCRYPTCTR + "xcryptecb", // X86_INS_XCRYPTECB + "xcryptofb", // X86_INS_XCRYPTOFB + "xend", // X86_INS_XEND + "xgetbv", // X86_INS_XGETBV + "xlatb", // X86_INS_XLATB + "xor", // X86_INS_XOR + "xorpd", // X86_INS_XORPD + "xorps", // X86_INS_XORPS + "xrelease", // X86_INS_XRELEASE + "xrstor", // X86_INS_XRSTOR + "xrstor64", // X86_INS_XRSTOR64 + "xrstors", // X86_INS_XRSTORS + "xrstors64", // X86_INS_XRSTORS64 + "xsave", // X86_INS_XSAVE + "xsave64", // X86_INS_XSAVE64 + "xsavec", // X86_INS_XSAVEC + "xsavec64", // X86_INS_XSAVEC64 + "xsaveopt", // X86_INS_XSAVEOPT + "xsaveopt64", // X86_INS_XSAVEOPT64 + "xsaves", // X86_INS_XSAVES + "xsaves64", // X86_INS_XSAVES64 + "xsetbv", // X86_INS_XSETBV + "xsha1", // X86_INS_XSHA1 + "xsha256", // X86_INS_XSHA256 + "xstore", // X86_INS_XSTORE + "xtest", // X86_INS_XTEST diff --git a/thirdparty/capstone/arch/X86/X86MappingInsnName_reduce.inc b/thirdparty/capstone/arch/X86/X86MappingInsnName_reduce.inc new file mode 100644 index 0000000..932014f --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86MappingInsnName_reduce.inc @@ -0,0 +1,348 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + + "aaa", // X86_INS_AAA + "aad", // X86_INS_AAD + "aam", // X86_INS_AAM + "aas", // X86_INS_AAS + "adc", // X86_INS_ADC + "adcx", // X86_INS_ADCX + "add", // X86_INS_ADD + "adox", // X86_INS_ADOX + "and", // X86_INS_AND + "andn", // X86_INS_ANDN + "arpl", // X86_INS_ARPL + "bextr", // X86_INS_BEXTR + "blcfill", // X86_INS_BLCFILL + "blci", // X86_INS_BLCI + "blcic", // X86_INS_BLCIC + "blcmsk", // X86_INS_BLCMSK + "blcs", // X86_INS_BLCS + "blsfill", // X86_INS_BLSFILL + "blsi", // X86_INS_BLSI + "blsic", // X86_INS_BLSIC + "blsmsk", // X86_INS_BLSMSK + "blsr", // X86_INS_BLSR + "bound", // X86_INS_BOUND + "bsf", // X86_INS_BSF + "bsr", // X86_INS_BSR + "bswap", // X86_INS_BSWAP + "bt", // X86_INS_BT + "btc", // X86_INS_BTC + "btr", // X86_INS_BTR + "bts", // X86_INS_BTS + "bzhi", // X86_INS_BZHI + "call", // X86_INS_CALL + "cbw", // X86_INS_CBW + "cdq", // X86_INS_CDQ + "cdqe", // X86_INS_CDQE + "clac", // X86_INS_CLAC + "clc", // X86_INS_CLC + "cld", // X86_INS_CLD + "cldemote", // X86_INS_CLDEMOTE + "clflushopt", // X86_INS_CLFLUSHOPT + "clgi", // X86_INS_CLGI + "cli", // X86_INS_CLI + "clrssbsy", // X86_INS_CLRSSBSY + "clts", // X86_INS_CLTS + "clwb", // X86_INS_CLWB + "clzero", // X86_INS_CLZERO + "cmc", // X86_INS_CMC + "cmova", // X86_INS_CMOVA + "cmovae", // X86_INS_CMOVAE + "cmovb", // X86_INS_CMOVB + "cmovbe", // X86_INS_CMOVBE + "cmove", // X86_INS_CMOVE + "cmovg", // X86_INS_CMOVG + "cmovge", // X86_INS_CMOVGE + "cmovl", // X86_INS_CMOVL + "cmovle", // X86_INS_CMOVLE + "cmovne", // X86_INS_CMOVNE + "cmovno", // X86_INS_CMOVNO + "cmovnp", // X86_INS_CMOVNP + "cmovns", // X86_INS_CMOVNS + "cmovo", // X86_INS_CMOVO + "cmovp", // X86_INS_CMOVP + "cmovs", // X86_INS_CMOVS + "cmp", // X86_INS_CMP + "cmpsb", // X86_INS_CMPSB + "cmpsd", // X86_INS_CMPSD + "cmpsq", // X86_INS_CMPSQ + "cmpsw", // X86_INS_CMPSW + "cmpxchg16b", // X86_INS_CMPXCHG16B + "cmpxchg", // X86_INS_CMPXCHG + "cmpxchg8b", // X86_INS_CMPXCHG8B + "cpuid", // X86_INS_CPUID + "cqo", // X86_INS_CQO + "cwd", // X86_INS_CWD + "cwde", // X86_INS_CWDE + "daa", // X86_INS_DAA + "das", // X86_INS_DAS + "data16", // X86_INS_DATA16 + "dec", // X86_INS_DEC + "div", // X86_INS_DIV + "endbr32", // X86_INS_ENDBR32 + "endbr64", // X86_INS_ENDBR64 + "enter", // X86_INS_ENTER + "lcall", // X86_INS_LCALL + "ljmp", // X86_INS_LJMP + "jmp", // X86_INS_JMP + "fsetpm", // X86_INS_FSETPM + "getsec", // X86_INS_GETSEC + "hlt", // X86_INS_HLT + "idiv", // X86_INS_IDIV + "imul", // X86_INS_IMUL + "in", // X86_INS_IN + "inc", // X86_INS_INC + "incsspd", // X86_INS_INCSSPD + "incsspq", // X86_INS_INCSSPQ + "insb", // X86_INS_INSB + "insd", // X86_INS_INSD + "insw", // X86_INS_INSW + "int", // X86_INS_INT + "int1", // X86_INS_INT1 + "int3", // X86_INS_INT3 + "into", // X86_INS_INTO + "invd", // X86_INS_INVD + "invept", // X86_INS_INVEPT + "invlpg", // X86_INS_INVLPG + "invlpga", // X86_INS_INVLPGA + "invpcid", // X86_INS_INVPCID + "invvpid", // X86_INS_INVVPID + "iret", // X86_INS_IRET + "iretd", // X86_INS_IRETD + "iretq", // X86_INS_IRETQ + "jae", // X86_INS_JAE + "ja", // X86_INS_JA + "jbe", // X86_INS_JBE + "jb", // X86_INS_JB + "jcxz", // X86_INS_JCXZ + "jecxz", // X86_INS_JECXZ + "je", // X86_INS_JE + "jge", // X86_INS_JGE + "jg", // X86_INS_JG + "jle", // X86_INS_JLE + "jl", // X86_INS_JL + "jne", // X86_INS_JNE + "jno", // X86_INS_JNO + "jnp", // X86_INS_JNP + "jns", // X86_INS_JNS + "jo", // X86_INS_JO + "jp", // X86_INS_JP + "jrcxz", // X86_INS_JRCXZ + "js", // X86_INS_JS + "lahf", // X86_INS_LAHF + "lar", // X86_INS_LAR + "lds", // X86_INS_LDS + "lea", // X86_INS_LEA + "leave", // X86_INS_LEAVE + "les", // X86_INS_LES + "lfs", // X86_INS_LFS + "lgdt", // X86_INS_LGDT + "lgs", // X86_INS_LGS + "lidt", // X86_INS_LIDT + "lldt", // X86_INS_LLDT + "llwpcb", // X86_INS_LLWPCB + "lmsw", // X86_INS_LMSW + "lock", // X86_INS_LOCK + "lodsb", // X86_INS_LODSB + "lodsd", // X86_INS_LODSD + "lodsq", // X86_INS_LODSQ + "lodsw", // X86_INS_LODSW + "loop", // X86_INS_LOOP + "loope", // X86_INS_LOOPE + "loopne", // X86_INS_LOOPNE + "retf", // X86_INS_RETF + "retfq", // X86_INS_RETFQ + "lsl", // X86_INS_LSL + "lss", // X86_INS_LSS + "ltr", // X86_INS_LTR + "lwpins", // X86_INS_LWPINS + "lwpval", // X86_INS_LWPVAL + "lzcnt", // X86_INS_LZCNT + "monitorx", // X86_INS_MONITORX + "montmul", // X86_INS_MONTMUL + "mov", // X86_INS_MOV + "movabs", // X86_INS_MOVABS + "movbe", // X86_INS_MOVBE + "movdir64b", // X86_INS_MOVDIR64B + "movdiri", // X86_INS_MOVDIRI + "movsb", // X86_INS_MOVSB + "movsd", // X86_INS_MOVSD + "movsq", // X86_INS_MOVSQ + "movsw", // X86_INS_MOVSW + "movsx", // X86_INS_MOVSX + "movsxd", // X86_INS_MOVSXD + "movzx", // X86_INS_MOVZX + "mul", // X86_INS_MUL + "mulx", // X86_INS_MULX + "mwaitx", // X86_INS_MWAITX + "neg", // X86_INS_NEG + "nop", // X86_INS_NOP + "not", // X86_INS_NOT + "or", // X86_INS_OR + "out", // X86_INS_OUT + "outsb", // X86_INS_OUTSB + "outsd", // X86_INS_OUTSD + "outsw", // X86_INS_OUTSW + "pconfig", // X86_INS_PCONFIG + "pdep", // X86_INS_PDEP + "pext", // X86_INS_PEXT + "pop", // X86_INS_POP + "popaw", // X86_INS_POPAW + "popal", // X86_INS_POPAL + "popf", // X86_INS_POPF + "popfd", // X86_INS_POPFD + "popfq", // X86_INS_POPFQ + "ptwrite", // X86_INS_PTWRITE + "push", // X86_INS_PUSH + "pushaw", // X86_INS_PUSHAW + "pushal", // X86_INS_PUSHAL + "pushf", // X86_INS_PUSHF + "pushfd", // X86_INS_PUSHFD + "pushfq", // X86_INS_PUSHFQ + "rcl", // X86_INS_RCL + "rcr", // X86_INS_RCR + "rdfsbase", // X86_INS_RDFSBASE + "rdgsbase", // X86_INS_RDGSBASE + "rdmsr", // X86_INS_RDMSR + "rdpid", // X86_INS_RDPID + "rdpkru", // X86_INS_RDPKRU + "rdpmc", // X86_INS_RDPMC + "rdrand", // X86_INS_RDRAND + "rdseed", // X86_INS_RDSEED + "rdsspd", // X86_INS_RDSSPD + "rdsspq", // X86_INS_RDSSPQ + "rdtsc", // X86_INS_RDTSC + "rdtscp", // X86_INS_RDTSCP + "repne", // X86_INS_REPNE + "rep", // X86_INS_REP + "ret", // X86_INS_RET + "rex64", // X86_INS_REX64 + "rol", // X86_INS_ROL + "ror", // X86_INS_ROR + "rorx", // X86_INS_RORX + "rsm", // X86_INS_RSM + "rstorssp", // X86_INS_RSTORSSP + "sahf", // X86_INS_SAHF + "sal", // X86_INS_SAL + "salc", // X86_INS_SALC + "sar", // X86_INS_SAR + "sarx", // X86_INS_SARX + "saveprevssp", // X86_INS_SAVEPREVSSP + "sbb", // X86_INS_SBB + "scasb", // X86_INS_SCASB + "scasd", // X86_INS_SCASD + "scasq", // X86_INS_SCASQ + "scasw", // X86_INS_SCASW + "setae", // X86_INS_SETAE + "seta", // X86_INS_SETA + "setbe", // X86_INS_SETBE + "setb", // X86_INS_SETB + "sete", // X86_INS_SETE + "setge", // X86_INS_SETGE + "setg", // X86_INS_SETG + "setle", // X86_INS_SETLE + "setl", // X86_INS_SETL + "setne", // X86_INS_SETNE + "setno", // X86_INS_SETNO + "setnp", // X86_INS_SETNP + "setns", // X86_INS_SETNS + "seto", // X86_INS_SETO + "setp", // X86_INS_SETP + "setssbsy", // X86_INS_SETSSBSY + "sets", // X86_INS_SETS + "sgdt", // X86_INS_SGDT + "shl", // X86_INS_SHL + "shld", // X86_INS_SHLD + "shlx", // X86_INS_SHLX + "shr", // X86_INS_SHR + "shrd", // X86_INS_SHRD + "shrx", // X86_INS_SHRX + "sidt", // X86_INS_SIDT + "skinit", // X86_INS_SKINIT + "sldt", // X86_INS_SLDT + "slwpcb", // X86_INS_SLWPCB + "smsw", // X86_INS_SMSW + "stac", // X86_INS_STAC + "stc", // X86_INS_STC + "std", // X86_INS_STD + "stgi", // X86_INS_STGI + "sti", // X86_INS_STI + "stosb", // X86_INS_STOSB + "stosd", // X86_INS_STOSD + "stosq", // X86_INS_STOSQ + "stosw", // X86_INS_STOSW + "str", // X86_INS_STR + "sub", // X86_INS_SUB + "swapgs", // X86_INS_SWAPGS + "syscall", // X86_INS_SYSCALL + "sysenter", // X86_INS_SYSENTER + "sysexit", // X86_INS_SYSEXIT + "sysexitq", // X86_INS_SYSEXITQ + "sysret", // X86_INS_SYSRET + "sysretq", // X86_INS_SYSRETQ + "t1mskc", // X86_INS_T1MSKC + "test", // X86_INS_TEST + "tpause", // X86_INS_TPAUSE + "tzcnt", // X86_INS_TZCNT + "tzmsk", // X86_INS_TZMSK + "ud0", // X86_INS_UD0 + "ud1", // X86_INS_UD1 + "ud2", // X86_INS_UD2 + "umonitor", // X86_INS_UMONITOR + "umwait", // X86_INS_UMWAIT + "verr", // X86_INS_VERR + "verw", // X86_INS_VERW + "vmcall", // X86_INS_VMCALL + "vmclear", // X86_INS_VMCLEAR + "vmfunc", // X86_INS_VMFUNC + "vmlaunch", // X86_INS_VMLAUNCH + "vmload", // X86_INS_VMLOAD + "vmmcall", // X86_INS_VMMCALL + "vmptrld", // X86_INS_VMPTRLD + "vmptrst", // X86_INS_VMPTRST + "vmread", // X86_INS_VMREAD + "vmresume", // X86_INS_VMRESUME + "vmrun", // X86_INS_VMRUN + "vmsave", // X86_INS_VMSAVE + "vmwrite", // X86_INS_VMWRITE + "vmxoff", // X86_INS_VMXOFF + "vmxon", // X86_INS_VMXON + "wbinvd", // X86_INS_WBINVD + "wbnoinvd", // X86_INS_WBNOINVD + "wrfsbase", // X86_INS_WRFSBASE + "wrgsbase", // X86_INS_WRGSBASE + "wrmsr", // X86_INS_WRMSR + "wrpkru", // X86_INS_WRPKRU + "wrssd", // X86_INS_WRSSD + "wrssq", // X86_INS_WRSSQ + "wrussd", // X86_INS_WRUSSD + "wrussq", // X86_INS_WRUSSQ + "xadd", // X86_INS_XADD + "xchg", // X86_INS_XCHG + "xcryptcbc", // X86_INS_XCRYPTCBC + "xcryptcfb", // X86_INS_XCRYPTCFB + "xcryptctr", // X86_INS_XCRYPTCTR + "xcryptecb", // X86_INS_XCRYPTECB + "xcryptofb", // X86_INS_XCRYPTOFB + "xgetbv", // X86_INS_XGETBV + "xlatb", // X86_INS_XLATB + "xor", // X86_INS_XOR + "xrstor", // X86_INS_XRSTOR + "xrstor64", // X86_INS_XRSTOR64 + "xrstors", // X86_INS_XRSTORS + "xrstors64", // X86_INS_XRSTORS64 + "xsave", // X86_INS_XSAVE + "xsave64", // X86_INS_XSAVE64 + "xsavec", // X86_INS_XSAVEC + "xsavec64", // X86_INS_XSAVEC64 + "xsaveopt", // X86_INS_XSAVEOPT + "xsaveopt64", // X86_INS_XSAVEOPT64 + "xsaves", // X86_INS_XSAVES + "xsaves64", // X86_INS_XSAVES64 + "xsetbv", // X86_INS_XSETBV + "xsha1", // X86_INS_XSHA1 + "xsha256", // X86_INS_XSHA256 + "xstore", // X86_INS_XSTORE diff --git a/thirdparty/capstone/arch/X86/X86MappingInsnOp.inc b/thirdparty/capstone/arch/X86/X86MappingInsnOp.inc new file mode 100644 index 0000000..cb5cd43 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86MappingInsnOp.inc @@ -0,0 +1,75699 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + + +{ /* X86_AAA, X86_INS_AAA: aaa */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { 0 } +}, + +{ /* X86_AAD8i8, X86_INS_AAD: aad */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_AAM8i8, X86_INS_AAM: aam */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_AAS, X86_INS_AAS: aas */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { 0 } +}, + +{ /* X86_ABS_F, X86_INS_FABS: fabs */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_ABS_Fp32, X86_INS_FABS: fabs */ + 0, + { 0 } +}, + +{ /* X86_ABS_Fp64, X86_INS_FABS: fabs */ + 0, + { 0 } +}, + +{ /* X86_ABS_Fp80, X86_INS_FABS: fabs */ + 0, + { 0 } +}, + +{ /* X86_ADC16i16, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC16mi, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC16mi8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC16mr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC16ri, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC16ri8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC16rm, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC16rr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC16rr_REV, X86_INS_ADC: adc{w} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC32i32, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC32mi, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC32mi8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC32mr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC32ri, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC32ri8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC32rm, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC32rr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC32rr_REV, X86_INS_ADC: adc{l} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC64i32, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC64mi32, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC64mi8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC64mr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC64ri32, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC64ri8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC64rm, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC64rr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC64rr_REV, X86_INS_ADC: adc{q} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC8i8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC8mi, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC8mi8, X86_INS_ADC: adc{b} $dst $src */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC8mr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC8ri, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC8ri8, X86_INS_ADC: adc{b} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC8rm, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC8rr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC8rr_REV, X86_INS_ADC: adc{b} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADCX32rm, X86_INS_ADCX: adcx */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADCX32rr, X86_INS_ADCX: adcx */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADCX64rm, X86_INS_ADCX: adcx */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADCX64rr, X86_INS_ADCX: adcx */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD16i16, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD16mi, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD16mi8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD16mr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD16ri, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD16ri8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD16rm, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD16rr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD16rr_REV, X86_INS_ADD: add{w} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD32i32, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD32mi, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD32mi8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD32mr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD32ri, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD32ri8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD32rm, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD32rr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD32rr_REV, X86_INS_ADD: add{l} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD64i32, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD64mi32, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD64mi8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD64mr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD64ri32, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD64ri8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD64rm, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD64rr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD64rr_REV, X86_INS_ADD: add{q} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD8i8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD8mi, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD8mi8, X86_INS_ADD: add{b} $dst $src */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD8mr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD8ri, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD8ri8, X86_INS_ADD: add{b} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD8rm, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD8rr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD8rr_REV, X86_INS_ADD: add{b} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDPDrm, X86_INS_ADDPD: addpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDPDrr, X86_INS_ADDPD: addpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDPSrm, X86_INS_ADDPS: addps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDPSrr, X86_INS_ADDPS: addps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDSDrm, X86_INS_ADDSD: addsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDSDrm_Int, X86_INS_ADDSD: addsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADDSDrr, X86_INS_ADDSD: addsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDSDrr_Int, X86_INS_ADDSD: addsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDSSrm, X86_INS_ADDSS: addss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDSSrm_Int, X86_INS_ADDSS: addss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADDSSrr, X86_INS_ADDSS: addss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDSSrr_Int, X86_INS_ADDSS: addss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDSUBPDrm, X86_INS_ADDSUBPD: addsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDSUBPDrr, X86_INS_ADDSUBPD: addsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDSUBPSrm, X86_INS_ADDSUBPS: addsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADDSUBPSrr, X86_INS_ADDSUBPS: addsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD_F32m, X86_INS_FADD: fadd */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ADD_F64m, X86_INS_FADD: fadd */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ADD_FI16m, X86_INS_FIADD: fiadd */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ADD_FI32m, X86_INS_FIADD: fiadd */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ADD_FPrST0, X86_INS_FADD: faddp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ADD_FST0r, X86_INS_FADD: fadd */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ADD_Fp32, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_Fp32m, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_Fp64, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_Fp64m, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_Fp64m32, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_Fp80, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_Fp80m32, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_Fp80m64, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_FpI16m32, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_FpI16m64, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_FpI16m80, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_FpI32m32, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_FpI32m64, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_FpI32m80, X86_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* X86_ADD_FrST0, X86_INS_FADD: fadd */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ADOX32rm, X86_INS_ADOX: adox */ + X86_EFLAGS_MODIFY_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADOX32rr, X86_INS_ADOX: adox */ + X86_EFLAGS_MODIFY_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADOX64rm, X86_INS_ADOX: adox */ + X86_EFLAGS_MODIFY_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADOX64rr, X86_INS_ADOX: adox */ + X86_EFLAGS_MODIFY_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AESDECLASTrm, X86_INS_AESDECLAST: aesdeclast */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AESDECLASTrr, X86_INS_AESDECLAST: aesdeclast */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AESDECrm, X86_INS_AESDEC: aesdec */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AESDECrr, X86_INS_AESDEC: aesdec */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AESENCLASTrm, X86_INS_AESENCLAST: aesenclast */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AESENCLASTrr, X86_INS_AESENCLAST: aesenclast */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AESENCrm, X86_INS_AESENC: aesenc */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AESENCrr, X86_INS_AESENC: aesenc */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AESIMCrm, X86_INS_AESIMC: aesimc */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AESIMCrr, X86_INS_AESIMC: aesimc */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AESKEYGENASSIST128rm, X86_INS_AESKEYGENASSIST: aeskeygenassist */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AESKEYGENASSIST128rr, X86_INS_AESKEYGENASSIST: aeskeygenassist */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND16i16, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND16mi, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND16mi8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND16mr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND16ri, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND16ri8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND16rm, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND16rr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND16rr_REV, X86_INS_AND: and{w} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND32i32, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND32mi, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND32mi8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND32mr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND32ri, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND32ri8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND32rm, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND32rr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND32rr_REV, X86_INS_AND: and{l} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND64i32, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND64mi32, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND64mi8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND64mr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND64ri32, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND64ri8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND64rm, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND64rr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND64rr_REV, X86_INS_AND: and{q} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND8i8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND8mi, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND8mi8, X86_INS_AND: and{b} $dst $src */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND8mr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND8ri, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND8ri8, X86_INS_AND: and{b} $src1 $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND8rm, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND8rr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND8rr_REV, X86_INS_AND: and{b} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ANDN32rm, X86_INS_ANDN: andn */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ANDN32rr, X86_INS_ANDN: andn */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ANDN64rm, X86_INS_ANDN: andn */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ANDN64rr, X86_INS_ANDN: andn */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ANDNPDrm, X86_INS_ANDNPD: andnpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ANDNPDrr, X86_INS_ANDNPD: andnpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ANDNPSrm, X86_INS_ANDNPS: andnps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ANDNPSrr, X86_INS_ANDNPS: andnps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ANDPDrm, X86_INS_ANDPD: andpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ANDPDrr, X86_INS_ANDPD: andpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ANDPSrm, X86_INS_ANDPS: andps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ANDPSrr, X86_INS_ANDPS: andps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ARPL16mr, X86_INS_ARPL: arpl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ARPL16rr, X86_INS_ARPL: arpl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BEXTR32rm, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BEXTR32rr, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BEXTR64rm, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BEXTR64rr, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BEXTRI32mi, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BEXTRI32ri, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BEXTRI64mi, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BEXTRI64ri, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BLCFILL32rm, X86_INS_BLCFILL: blcfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCFILL32rr, X86_INS_BLCFILL: blcfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCFILL64rm, X86_INS_BLCFILL: blcfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCFILL64rr, X86_INS_BLCFILL: blcfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCI32rm, X86_INS_BLCI: blci */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCI32rr, X86_INS_BLCI: blci */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCI64rm, X86_INS_BLCI: blci */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCI64rr, X86_INS_BLCI: blci */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCIC32rm, X86_INS_BLCIC: blcic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCIC32rr, X86_INS_BLCIC: blcic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCIC64rm, X86_INS_BLCIC: blcic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCIC64rr, X86_INS_BLCIC: blcic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCMSK32rm, X86_INS_BLCMSK: blcmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCMSK32rr, X86_INS_BLCMSK: blcmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCMSK64rm, X86_INS_BLCMSK: blcmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCMSK64rr, X86_INS_BLCMSK: blcmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCS32rm, X86_INS_BLCS: blcs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCS32rr, X86_INS_BLCS: blcs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCS64rm, X86_INS_BLCS: blcs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCS64rr, X86_INS_BLCS: blcs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLENDPDrmi, X86_INS_BLENDPD: blendpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BLENDPDrri, X86_INS_BLENDPD: blendpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BLENDPSrmi, X86_INS_BLENDPS: blendps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BLENDPSrri, X86_INS_BLENDPS: blendps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BLENDVPDrm0, X86_INS_BLENDVPD: blendvpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLENDVPDrr0, X86_INS_BLENDVPD: blendvpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLENDVPSrm0, X86_INS_BLENDVPS: blendvps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLENDVPSrr0, X86_INS_BLENDVPS: blendvps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSFILL32rm, X86_INS_BLSFILL: blsfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSFILL32rr, X86_INS_BLSFILL: blsfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSFILL64rm, X86_INS_BLSFILL: blsfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSFILL64rr, X86_INS_BLSFILL: blsfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSI32rm, X86_INS_BLSI: blsi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSI32rr, X86_INS_BLSI: blsi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSI64rm, X86_INS_BLSI: blsi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSI64rr, X86_INS_BLSI: blsi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSIC32rm, X86_INS_BLSIC: blsic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSIC32rr, X86_INS_BLSIC: blsic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSIC64rm, X86_INS_BLSIC: blsic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSIC64rr, X86_INS_BLSIC: blsic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSMSK32rm, X86_INS_BLSMSK: blsmsk */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSMSK32rr, X86_INS_BLSMSK: blsmsk */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSMSK64rm, X86_INS_BLSMSK: blsmsk */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSMSK64rr, X86_INS_BLSMSK: blsmsk */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSR32rm, X86_INS_BLSR: blsr */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSR32rr, X86_INS_BLSR: blsr */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSR64rm, X86_INS_BLSR: blsr */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSR64rr, X86_INS_BLSR: blsr */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BNDCL32rm, X86_INS_BNDCL: bndcl */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BNDCL32rr, X86_INS_BNDCL: bndcl */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BNDCL64rm, X86_INS_BNDCL: bndcl */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BNDCL64rr, X86_INS_BNDCL: bndcl */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BNDCN32rm, X86_INS_BNDCN: bndcn */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BNDCN32rr, X86_INS_BNDCN: bndcn */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BNDCN64rm, X86_INS_BNDCN: bndcn */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BNDCN64rr, X86_INS_BNDCN: bndcn */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BNDCU32rm, X86_INS_BNDCU: bndcu */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BNDCU32rr, X86_INS_BNDCU: bndcu */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BNDCU64rm, X86_INS_BNDCU: bndcu */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BNDCU64rr, X86_INS_BNDCU: bndcu */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BNDLDXrm, X86_INS_BNDLDX: bndldx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BNDMK32rm, X86_INS_BNDMK: bndmk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BNDMK64rm, X86_INS_BNDMK: bndmk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BNDMOV32mr, X86_INS_BNDMOV: bndmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BNDMOV32rm, X86_INS_BNDMOV: bndmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BNDMOV64mr, X86_INS_BNDMOV: bndmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BNDMOV64rm, X86_INS_BNDMOV: bndmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BNDMOVrr, X86_INS_BNDMOV: bndmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BNDMOVrr_REV, X86_INS_BNDMOV: bndmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BNDSTXmr, X86_INS_BNDSTX: bndstx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BOUNDS16rm, X86_INS_BOUND: bound */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BOUNDS32rm, X86_INS_BOUND: bound */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSF16rm, X86_INS_BSF: bsf */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSF16rr, X86_INS_BSF: bsf */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSF32rm, X86_INS_BSF: bsf */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSF32rr, X86_INS_BSF: bsf */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSF64rm, X86_INS_BSF: bsf */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSF64rr, X86_INS_BSF: bsf */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSR16rm, X86_INS_BSR: bsr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSR16rr, X86_INS_BSR: bsr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSR32rm, X86_INS_BSR: bsr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSR32rr, X86_INS_BSR: bsr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSR64rm, X86_INS_BSR: bsr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSR64rr, X86_INS_BSR: bsr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSWAP16r_BAD, X86_INS_BSWAP: bswap */ + 0, + { 0 } +}, + +{ /* X86_BSWAP32r, X86_INS_BSWAP: bswap */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_BSWAP64r, X86_INS_BSWAP: bswap */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_BT16mi8, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BT16mr, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BT16ri8, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BT16rr, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BT32mi8, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BT32mr, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BT32ri8, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BT32rr, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BT64mi8, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BT64mr, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BT64ri8, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BT64rr, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BTC16mi8, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTC16mr, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTC16ri8, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTC16rr, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTC32mi8, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTC32mr, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTC32ri8, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTC32rr, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTC64mi8, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTC64mr, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTC64ri8, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTC64rr, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTR16mi8, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTR16mr, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTR16ri8, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTR16rr, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTR32mi8, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTR32mr, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTR32ri8, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTR32rr, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTR64mi8, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTR64mr, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTR64ri8, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTR64rr, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTS16mi8, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTS16mr, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTS16ri8, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTS16rr, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTS32mi8, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTS32mr, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTS32ri8, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTS32rr, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTS64mi8, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTS64mr, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTS64ri8, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTS64rr, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BZHI32rm, X86_INS_BZHI: bzhi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BZHI32rr, X86_INS_BZHI: bzhi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BZHI64rm, X86_INS_BZHI: bzhi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BZHI64rr, X86_INS_BZHI: bzhi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CALL16m, X86_INS_CALL: call */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CALL16m_NT, X86_INS_CALL: call */ + 0, + { 0 } +}, + +{ /* X86_CALL16r, X86_INS_CALL: call */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CALL16r_NT, X86_INS_CALL: call */ + 0, + { 0 } +}, + +{ /* X86_CALL32m, X86_INS_CALL: call */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CALL32m_NT, X86_INS_CALL: call */ + 0, + { 0 } +}, + +{ /* X86_CALL32r, X86_INS_CALL: call */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CALL32r_NT, X86_INS_CALL: call */ + 0, + { 0 } +}, + +{ /* X86_CALL64m, X86_INS_CALL: call */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CALL64m_NT, X86_INS_CALL: call */ + 0, + { 0 } +}, + +{ /* X86_CALL64pcrel32, X86_INS_CALL: call */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_CALL64r, X86_INS_CALL: call */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CALL64r_NT, X86_INS_CALL: call */ + 0, + { 0 } +}, + +{ /* X86_CALLpcrel16, X86_INS_CALL: call */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_CALLpcrel32, X86_INS_CALL: call */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_CBW, X86_INS_CBW: cbw */ + 0, + { 0 } +}, + +{ /* X86_CDQ, X86_INS_CDQ: cdq */ + 0, + { 0 } +}, + +{ /* X86_CDQE, X86_INS_CDQE: cdqe */ + 0, + { 0 } +}, + +{ /* X86_CHS_F, X86_INS_FCHS: fchs */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_CHS_Fp32, X86_INS_FCHS: fchs */ + 0, + { 0 } +}, + +{ /* X86_CHS_Fp64, X86_INS_FCHS: fchs */ + 0, + { 0 } +}, + +{ /* X86_CHS_Fp80, X86_INS_FCHS: fchs */ + 0, + { 0 } +}, + +{ /* X86_CLAC, X86_INS_CLAC: clac */ + X86_EFLAGS_RESET_AC, + { 0 } +}, + +{ /* X86_CLC, X86_INS_CLC: clc */ + X86_EFLAGS_RESET_CF, + { 0 } +}, + +{ /* X86_CLD, X86_INS_CLD: cld */ + X86_EFLAGS_RESET_DF, + { 0 } +}, + +{ /* X86_CLDEMOTE, X86_INS_CLDEMOTE: cldemote */ + 0, + { 0 } +}, + +{ /* X86_CLFLUSH, X86_INS_CLFLUSH: clflush */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CLFLUSHOPT, X86_INS_CLFLUSHOPT: clflushopt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CLGI, X86_INS_CLGI: clgi */ + 0, + { 0 } +}, + +{ /* X86_CLI, X86_INS_CLI: cli */ + X86_EFLAGS_RESET_IF, + { 0 } +}, + +{ /* X86_CLRSSBSY, X86_INS_CLRSSBSY: clrssbsy */ + 0, + { 0 } +}, + +{ /* X86_CLTS, X86_INS_CLTS: clts */ + 0, + { 0 } +}, + +{ /* X86_CLWB, X86_INS_CLWB: clwb */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CLZEROr, X86_INS_CLZERO: clzero */ + 0, + { 0 } +}, + +{ /* X86_CMC, X86_INS_CMC: cmc */ + X86_EFLAGS_MODIFY_CF, + { 0 } +}, + +{ /* X86_CMOVA16rm, X86_INS_CMOVA: cmova */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVA16rr, X86_INS_CMOVA: cmova */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVA32rm, X86_INS_CMOVA: cmova */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVA32rr, X86_INS_CMOVA: cmova */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVA64rm, X86_INS_CMOVA: cmova */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVA64rr, X86_INS_CMOVA: cmova */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVAE16rm, X86_INS_CMOVAE: cmovae */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVAE16rr, X86_INS_CMOVAE: cmovae */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVAE32rm, X86_INS_CMOVAE: cmovae */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVAE32rr, X86_INS_CMOVAE: cmovae */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVAE64rm, X86_INS_CMOVAE: cmovae */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVAE64rr, X86_INS_CMOVAE: cmovae */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVB16rm, X86_INS_CMOVB: cmovb */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVB16rr, X86_INS_CMOVB: cmovb */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVB32rm, X86_INS_CMOVB: cmovb */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVB32rr, X86_INS_CMOVB: cmovb */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVB64rm, X86_INS_CMOVB: cmovb */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVB64rr, X86_INS_CMOVB: cmovb */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE16rm, X86_INS_CMOVBE: cmovbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE16rr, X86_INS_CMOVBE: cmovbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE32rm, X86_INS_CMOVBE: cmovbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE32rr, X86_INS_CMOVBE: cmovbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE64rm, X86_INS_CMOVBE: cmovbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE64rr, X86_INS_CMOVBE: cmovbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE_F, X86_INS_FCMOVBE: fcmovbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* X86_CMOVBE_Fp32, X86_INS_FCMOVBE: fcmovbe */ + 0, + { 0 } +}, + +{ /* X86_CMOVBE_Fp64, X86_INS_FCMOVBE: fcmovbe */ + 0, + { 0 } +}, + +{ /* X86_CMOVBE_Fp80, X86_INS_FCMOVBE: fcmovbe */ + 0, + { 0 } +}, + +{ /* X86_CMOVB_F, X86_INS_FCMOVB: fcmovb */ + X86_EFLAGS_TEST_CF, + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* X86_CMOVB_Fp32, X86_INS_FCMOVB: fcmovb */ + 0, + { 0 } +}, + +{ /* X86_CMOVB_Fp64, X86_INS_FCMOVB: fcmovb */ + 0, + { 0 } +}, + +{ /* X86_CMOVB_Fp80, X86_INS_FCMOVB: fcmovb */ + 0, + { 0 } +}, + +{ /* X86_CMOVE16rm, X86_INS_CMOVE: cmove */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVE16rr, X86_INS_CMOVE: cmove */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVE32rm, X86_INS_CMOVE: cmove */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVE32rr, X86_INS_CMOVE: cmove */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVE64rm, X86_INS_CMOVE: cmove */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVE64rr, X86_INS_CMOVE: cmove */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVE_F, X86_INS_FCMOVE: fcmove */ + X86_EFLAGS_TEST_ZF, + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* X86_CMOVE_Fp32, X86_INS_FCMOVE: fcmove */ + 0, + { 0 } +}, + +{ /* X86_CMOVE_Fp64, X86_INS_FCMOVE: fcmove */ + 0, + { 0 } +}, + +{ /* X86_CMOVE_Fp80, X86_INS_FCMOVE: fcmove */ + 0, + { 0 } +}, + +{ /* X86_CMOVG16rm, X86_INS_CMOVG: cmovg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVG16rr, X86_INS_CMOVG: cmovg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVG32rm, X86_INS_CMOVG: cmovg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVG32rr, X86_INS_CMOVG: cmovg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVG64rm, X86_INS_CMOVG: cmovg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVG64rr, X86_INS_CMOVG: cmovg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVGE16rm, X86_INS_CMOVGE: cmovge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVGE16rr, X86_INS_CMOVGE: cmovge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVGE32rm, X86_INS_CMOVGE: cmovge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVGE32rr, X86_INS_CMOVGE: cmovge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVGE64rm, X86_INS_CMOVGE: cmovge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVGE64rr, X86_INS_CMOVGE: cmovge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVL16rm, X86_INS_CMOVL: cmovl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVL16rr, X86_INS_CMOVL: cmovl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVL32rm, X86_INS_CMOVL: cmovl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVL32rr, X86_INS_CMOVL: cmovl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVL64rm, X86_INS_CMOVL: cmovl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVL64rr, X86_INS_CMOVL: cmovl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVLE16rm, X86_INS_CMOVLE: cmovle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVLE16rr, X86_INS_CMOVLE: cmovle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVLE32rm, X86_INS_CMOVLE: cmovle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVLE32rr, X86_INS_CMOVLE: cmovle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVLE64rm, X86_INS_CMOVLE: cmovle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVLE64rr, X86_INS_CMOVLE: cmovle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNBE_F, X86_INS_FCMOVNBE: fcmovnbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* X86_CMOVNBE_Fp32, X86_INS_FCMOVNBE: fcmovnbe */ + 0, + { 0 } +}, + +{ /* X86_CMOVNBE_Fp64, X86_INS_FCMOVNBE: fcmovnbe */ + 0, + { 0 } +}, + +{ /* X86_CMOVNBE_Fp80, X86_INS_FCMOVNBE: fcmovnbe */ + 0, + { 0 } +}, + +{ /* X86_CMOVNB_F, X86_INS_FCMOVNB: fcmovnb */ + X86_EFLAGS_TEST_CF, + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* X86_CMOVNB_Fp32, X86_INS_FCMOVNB: fcmovnb */ + 0, + { 0 } +}, + +{ /* X86_CMOVNB_Fp64, X86_INS_FCMOVNB: fcmovnb */ + 0, + { 0 } +}, + +{ /* X86_CMOVNB_Fp80, X86_INS_FCMOVNB: fcmovnb */ + 0, + { 0 } +}, + +{ /* X86_CMOVNE16rm, X86_INS_CMOVNE: cmovne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNE16rr, X86_INS_CMOVNE: cmovne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNE32rm, X86_INS_CMOVNE: cmovne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNE32rr, X86_INS_CMOVNE: cmovne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNE64rm, X86_INS_CMOVNE: cmovne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNE64rr, X86_INS_CMOVNE: cmovne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNE_F, X86_INS_FCMOVNE: fcmovne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* X86_CMOVNE_Fp32, X86_INS_FCMOVNE: fcmovne */ + 0, + { 0 } +}, + +{ /* X86_CMOVNE_Fp64, X86_INS_FCMOVNE: fcmovne */ + 0, + { 0 } +}, + +{ /* X86_CMOVNE_Fp80, X86_INS_FCMOVNE: fcmovne */ + 0, + { 0 } +}, + +{ /* X86_CMOVNO16rm, X86_INS_CMOVNO: cmovno */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNO16rr, X86_INS_CMOVNO: cmovno */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNO32rm, X86_INS_CMOVNO: cmovno */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNO32rr, X86_INS_CMOVNO: cmovno */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNO64rm, X86_INS_CMOVNO: cmovno */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNO64rr, X86_INS_CMOVNO: cmovno */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP16rm, X86_INS_CMOVNP: cmovnp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP16rr, X86_INS_CMOVNP: cmovnp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP32rm, X86_INS_CMOVNP: cmovnp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP32rr, X86_INS_CMOVNP: cmovnp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP64rm, X86_INS_CMOVNP: cmovnp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP64rr, X86_INS_CMOVNP: cmovnp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP_F, X86_INS_FCMOVNU: fcmovnu */ + X86_EFLAGS_TEST_PF, + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* X86_CMOVNP_Fp32, X86_INS_FCMOVNP: fcmovnp */ + 0, + { 0 } +}, + +{ /* X86_CMOVNP_Fp64, X86_INS_FCMOVNU: fcmovnu */ + 0, + { 0 } +}, + +{ /* X86_CMOVNP_Fp80, X86_INS_FCMOVNU: fcmovnu */ + 0, + { 0 } +}, + +{ /* X86_CMOVNS16rm, X86_INS_CMOVNS: cmovns */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNS16rr, X86_INS_CMOVNS: cmovns */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNS32rm, X86_INS_CMOVNS: cmovns */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNS32rr, X86_INS_CMOVNS: cmovns */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNS64rm, X86_INS_CMOVNS: cmovns */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNS64rr, X86_INS_CMOVNS: cmovns */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVO16rm, X86_INS_CMOVO: cmovo */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVO16rr, X86_INS_CMOVO: cmovo */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVO32rm, X86_INS_CMOVO: cmovo */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVO32rr, X86_INS_CMOVO: cmovo */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVO64rm, X86_INS_CMOVO: cmovo */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVO64rr, X86_INS_CMOVO: cmovo */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP16rm, X86_INS_CMOVP: cmovp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP16rr, X86_INS_CMOVP: cmovp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP32rm, X86_INS_CMOVP: cmovp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP32rr, X86_INS_CMOVP: cmovp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP64rm, X86_INS_CMOVP: cmovp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP64rr, X86_INS_CMOVP: cmovp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP_F, X86_INS_FCMOVU: fcmovu */ + X86_EFLAGS_TEST_PF, + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* X86_CMOVP_Fp32, X86_INS_FCMOVU: fcmovu */ + 0, + { 0 } +}, + +{ /* X86_CMOVP_Fp64, X86_INS_FCMOVU: fcmovu */ + 0, + { 0 } +}, + +{ /* X86_CMOVP_Fp80, X86_INS_FCMOVU: fcmovu */ + 0, + { 0 } +}, + +{ /* X86_CMOVS16rm, X86_INS_CMOVS: cmovs */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVS16rr, X86_INS_CMOVS: cmovs */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVS32rm, X86_INS_CMOVS: cmovs */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVS32rr, X86_INS_CMOVS: cmovs */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVS64rm, X86_INS_CMOVS: cmovs */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVS64rr, X86_INS_CMOVS: cmovs */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMP16i16, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP16mi, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP16mi8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP16mr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP16ri, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP16ri8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP16rm, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP16rr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP16rr_REV, X86_INS_CMP: cmp{w} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP32i32, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP32mi, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP32mi8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP32mr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP32ri, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP32ri8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP32rm, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP32rr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP32rr_REV, X86_INS_CMP: cmp{l} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP64i32, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP64mi32, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP64mi8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP64mr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP64ri32, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP64ri8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP64rm, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP64rr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP64rr_REV, X86_INS_CMP: cmp{q} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP8i8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP8mi, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP8mi8, X86_INS_CMP: cmp{b} $dst $src */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP8mr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP8ri, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP8ri8, X86_INS_CMP: cmp{b} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP8rm, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP8rr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP8rr_REV, X86_INS_CMP: cmp{b} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPPDrmi, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPPDrmi_alt, X86_INS_CMPPD: cmppd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMPPDrri, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPPDrri_alt, X86_INS_CMPPD: cmppd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMPPSrmi, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPPSrmi_alt, X86_INS_CMPPS: cmpps */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMPPSrri, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPPSrri_alt, X86_INS_CMPPS: cmpps */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMPSB, X86_INS_CMPSB: cmpsb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPSDrm, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPSDrm_Int, X86_INS_CMPSD: cmpsd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPSDrm_alt, X86_INS_CMPSD: cmpsd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMPSDrr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPSDrr_Int, X86_INS_CMPSD: cmpsd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPSDrr_alt, X86_INS_CMPSD: cmpsd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMPSL, X86_INS_CMPSD: cmpsd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_IGNORE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMPSQ, X86_INS_CMPSQ: cmpsq */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPSSrm, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPSSrm_Int, X86_INS_CMPSS: cmpss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPSSrm_alt, X86_INS_CMPSS: cmpss */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMPSSrr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPSSrr_Int, X86_INS_CMP: cmp */ + 0, + { 0 } +}, + +{ /* X86_CMPSSrr_alt, X86_INS_CMPSS: cmpss */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMPSW, X86_INS_CMPSW: cmpsw */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG16B, X86_INS_CMPXCHG16B: cmpxchg16b */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG16rm, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG16rr, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG32rm, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG32rr, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG64rm, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG64rr, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG8B, X86_INS_CMPXCHG8B: cmpxchg8b */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG8rm, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG8rr, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_COMISDrm, X86_INS_COMISD: comisd */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_COMISDrm_Int, X86_INS_COMISD: comisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_COMISDrr, X86_INS_COMISD: comisd */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_COMISDrr_Int, X86_INS_COMISD: comisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_COMISSrm, X86_INS_COMISS: comiss */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_COMISSrm_Int, X86_INS_COMISS: comiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_COMISSrr, X86_INS_COMISS: comiss */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_COMISSrr_Int, X86_INS_COMISS: comiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_COMP_FST0r, X86_INS_FCOMP: fcomp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_COM_FIPr, X86_INS_FCOMPI: fcompi */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_COM_FIr, X86_INS_FCOMI: fcomi */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_COM_FST0r, X86_INS_FCOM: fcom */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_COS_F, X86_INS_FCOS: fcos */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_COS_Fp32, X86_INS_FCOS: fcos */ + 0, + { 0 } +}, + +{ /* X86_COS_Fp64, X86_INS_FCOS: fcos */ + 0, + { 0 } +}, + +{ /* X86_COS_Fp80, X86_INS_FCOS: fcos */ + 0, + { 0 } +}, + +{ /* X86_CPUID, X86_INS_CPUID: cpuid */ + 0, + { 0 } +}, + +{ /* X86_CQO, X86_INS_CQO: cqo */ + 0, + { 0 } +}, + +{ /* X86_CRC32r32m16, X86_INS_CRC32: crc32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CRC32r32m32, X86_INS_CRC32: crc32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CRC32r32m8, X86_INS_CRC32: crc32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CRC32r32r16, X86_INS_CRC32: crc32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CRC32r32r32, X86_INS_CRC32: crc32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CRC32r32r8, X86_INS_CRC32: crc32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CRC32r64m64, X86_INS_CRC32: crc32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CRC32r64m8, X86_INS_CRC32: crc32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CRC32r64r64, X86_INS_CRC32: crc32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CRC32r64r8, X86_INS_CRC32: crc32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTDQ2PDrm, X86_INS_CVTDQ2PD: cvtdq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTDQ2PDrr, X86_INS_CVTDQ2PD: cvtdq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTDQ2PSrm, X86_INS_CVTDQ2PS: cvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTDQ2PSrr, X86_INS_CVTDQ2PS: cvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTPD2DQrm, X86_INS_CVTPD2DQ: cvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTPD2DQrr, X86_INS_CVTPD2DQ: cvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTPD2PSrm, X86_INS_CVTPD2PS: cvtpd2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTPD2PSrr, X86_INS_CVTPD2PS: cvtpd2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTPS2DQrm, X86_INS_CVTPS2DQ: cvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTPS2DQrr, X86_INS_CVTPS2DQ: cvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTPS2PDrm, X86_INS_CVTPS2PD: cvtps2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTPS2PDrr, X86_INS_CVTPS2PD: cvtps2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSD2SI64rm_Int, X86_INS_CVTSD2SI: cvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSD2SI64rr_Int, X86_INS_CVTSD2SI: cvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSD2SIrm_Int, X86_INS_CVTSD2SI: cvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSD2SIrr_Int, X86_INS_CVTSD2SI: cvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSD2SSrm, X86_INS_CVTSD2SS: cvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSD2SSrm_Int, X86_INS_CVTSD2SS: cvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSD2SSrr, X86_INS_CVTSD2SS: cvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSD2SSrr_Int, X86_INS_CVTSD2SS: cvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI2SDrm, X86_INS_CVTSI2SD: cvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI2SDrm_Int, X86_INS_CVTSI2SD: cvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI2SDrr, X86_INS_CVTSI2SD: cvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI2SDrr_Int, X86_INS_CVTSI2SD: cvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI2SSrm, X86_INS_CVTSI2SS: cvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI2SSrm_Int, X86_INS_CVTSI2SS: cvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI2SSrr, X86_INS_CVTSI2SS: cvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI2SSrr_Int, X86_INS_CVTSI2SS: cvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI642SDrm, X86_INS_CVTSI2SD: cvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI642SDrm_Int, X86_INS_CVTSI2SD: cvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI642SDrr, X86_INS_CVTSI2SD: cvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI642SDrr_Int, X86_INS_CVTSI2SD: cvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI642SSrm, X86_INS_CVTSI2SS: cvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI642SSrm_Int, X86_INS_CVTSI2SS: cvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI642SSrr, X86_INS_CVTSI2SS: cvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSI642SSrr_Int, X86_INS_CVTSI2SS: cvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSS2SDrm, X86_INS_CVTSS2SD: cvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSS2SDrm_Int, X86_INS_CVTSS2SD: cvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSS2SDrr, X86_INS_CVTSS2SD: cvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSS2SDrr_Int, X86_INS_CVTSS2SD: cvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSS2SI64rm_Int, X86_INS_CVTSS2SI: cvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSS2SI64rr_Int, X86_INS_CVTSS2SI: cvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSS2SIrm_Int, X86_INS_CVTSS2SI: cvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTSS2SIrr_Int, X86_INS_CVTSS2SI: cvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTPD2DQrm, X86_INS_CVTTPD2DQ: cvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTPD2DQrr, X86_INS_CVTTPD2DQ: cvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTPS2DQrm, X86_INS_CVTTPS2DQ: cvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTPS2DQrr, X86_INS_CVTTPS2DQ: cvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSD2SI64rm, X86_INS_CVTTSD2SI: cvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSD2SI64rm_Int, X86_INS_CVTTSD2SI: cvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSD2SI64rr, X86_INS_CVTTSD2SI: cvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSD2SI64rr_Int, X86_INS_CVTTSD2SI: cvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSD2SIrm, X86_INS_CVTTSD2SI: cvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSD2SIrm_Int, X86_INS_CVTTSD2SI: cvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSD2SIrr, X86_INS_CVTTSD2SI: cvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSD2SIrr_Int, X86_INS_CVTTSD2SI: cvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSS2SI64rm, X86_INS_CVTTSS2SI: cvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSS2SI64rm_Int, X86_INS_CVTTSS2SI: cvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSS2SI64rr, X86_INS_CVTTSS2SI: cvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSS2SI64rr_Int, X86_INS_CVTTSS2SI: cvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSS2SIrm, X86_INS_CVTTSS2SI: cvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSS2SIrm_Int, X86_INS_CVTTSS2SI: cvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSS2SIrr, X86_INS_CVTTSS2SI: cvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CVTTSS2SIrr_Int, X86_INS_CVTTSS2SI: cvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CWD, X86_INS_CWD: cwd */ + 0, + { 0 } +}, + +{ /* X86_CWDE, X86_INS_CWDE: cwde */ + 0, + { 0 } +}, + +{ /* X86_DAA, X86_INS_DAA: daa */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { 0 } +}, + +{ /* X86_DAS, X86_INS_DAS: das */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { 0 } +}, + +{ /* X86_DATA16_PREFIX, X86_INS_DATA16: data16 */ + 0, + { 0 } +}, + +{ /* X86_DEC16m, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC16r, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC16r_alt, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC32m, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC32r, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC32r_alt, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC64m, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC64r, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC8m, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC8r, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DIV16m, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV16r, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV32m, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV32r, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV64m, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV64r, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV8m, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV8r, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIVPDrm, X86_INS_DIVPD: divpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_DIVPDrr, X86_INS_DIVPD: divpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_DIVPSrm, X86_INS_DIVPS: divps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_DIVPSrr, X86_INS_DIVPS: divps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_DIVR_F32m, X86_INS_FDIVR: fdivr */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIVR_F64m, X86_INS_FDIVR: fdivr */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIVR_FI16m, X86_INS_FIDIVR: fidivr */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIVR_FI32m, X86_INS_FIDIVR: fidivr */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIVR_FPrST0, X86_INS_FDIVRP: fdivrp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIVR_FST0r, X86_INS_FDIVR: fdivr */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIVR_Fp32m, X86_INS_FDIVR: fdivr */ + 0, + { 0 } +}, + +{ /* X86_DIVR_Fp64m, X86_INS_FDIVR: fdivr */ + 0, + { 0 } +}, + +{ /* X86_DIVR_Fp64m32, X86_INS_FDIVR: fdivr */ + 0, + { 0 } +}, + +{ /* X86_DIVR_Fp80m32, X86_INS_FDIVR: fdivr */ + 0, + { 0 } +}, + +{ /* X86_DIVR_Fp80m64, X86_INS_FDIVR: fdivr */ + 0, + { 0 } +}, + +{ /* X86_DIVR_FpI16m32, X86_INS_FDIVR: fdivr */ + 0, + { 0 } +}, + +{ /* X86_DIVR_FpI16m64, X86_INS_FDIVR: fdivr */ + 0, + { 0 } +}, + +{ /* X86_DIVR_FpI16m80, X86_INS_FDIVR: fdivr */ + 0, + { 0 } +}, + +{ /* X86_DIVR_FpI32m32, X86_INS_FDIVR: fdivr */ + 0, + { 0 } +}, + +{ /* X86_DIVR_FpI32m64, X86_INS_FDIVR: fdivr */ + 0, + { 0 } +}, + +{ /* X86_DIVR_FpI32m80, X86_INS_FDIVR: fdivr */ + 0, + { 0 } +}, + +{ /* X86_DIVR_FrST0, X86_INS_FDIVR: fdivr */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_DIVSDrm, X86_INS_DIVSD: divsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_DIVSDrm_Int, X86_INS_DIVSD: divsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_DIVSDrr, X86_INS_DIVSD: divsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_DIVSDrr_Int, X86_INS_DIVSD: divsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_DIVSSrm, X86_INS_DIVSS: divss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_DIVSSrm_Int, X86_INS_DIVSS: divss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_DIVSSrr, X86_INS_DIVSS: divss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_DIVSSrr_Int, X86_INS_DIVSS: divss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_DIV_F32m, X86_INS_FDIV: fdiv */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV_F64m, X86_INS_FDIV: fdiv */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV_FI16m, X86_INS_FIDIV: fidiv */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV_FI32m, X86_INS_FIDIV: fidiv */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV_FPrST0, X86_INS_FDIVP: fdivp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV_FST0r, X86_INS_FDIV: fdiv */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV_Fp32, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_Fp32m, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_Fp64, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_Fp64m, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_Fp64m32, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_Fp80, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_Fp80m32, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_Fp80m64, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_FpI16m32, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_FpI16m64, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_FpI16m80, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_FpI32m32, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_FpI32m64, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_FpI32m80, X86_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* X86_DIV_FrST0, X86_INS_FDIV: fdiv */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_DPPDrmi, X86_INS_DPPD: dppd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_DPPDrri, X86_INS_DPPD: dppd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_DPPSrmi, X86_INS_DPPS: dpps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_DPPSrri, X86_INS_DPPS: dpps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ENCLS, X86_INS_ENCLS: encls */ + 0, + { 0 } +}, + +{ /* X86_ENCLU, X86_INS_ENCLU: enclu */ + 0, + { 0 } +}, + +{ /* X86_ENCLV, X86_INS_ENCLV: enclv */ + 0, + { 0 } +}, + +{ /* X86_ENDBR32, X86_INS_ENDBR32: endbr32 */ + 0, + { 0 } +}, + +{ /* X86_ENDBR64, X86_INS_ENDBR64: endbr64 */ + 0, + { 0 } +}, + +{ /* X86_ENTER, X86_INS_ENTER: enter */ + 0, + { CS_AC_IGNORE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_EXTRACTPSmr, X86_INS_EXTRACTPS: extractps */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_EXTRACTPSrr, X86_INS_EXTRACTPS: extractps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_EXTRQ, X86_INS_EXTRQ: extrq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_EXTRQI, X86_INS_EXTRQ: extrq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_F2XM1, X86_INS_F2XM1: f2xm1 */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FARCALL16i, X86_INS_LCALL: lcall{w} $seg : $off */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_FARCALL16m, X86_INS_LCALL: lcall */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_FARCALL32i, X86_INS_LCALL: lcall{l} $seg : $off */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_FARCALL32m, X86_INS_CALL: call */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_FARCALL64, X86_INS_LCALL: lcall */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_FARJMP16i, X86_INS_LJMP: ljmp{w} $seg : $off */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_FARJMP16m, X86_INS_LJMP: ljmp{w} {*}$dst */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_FARJMP32i, X86_INS_LJMP: ljmp{l} $seg : $off */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_FARJMP32m, X86_INS_JMP: jmp */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_FARJMP64, X86_INS_LJMP: ljmp */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_FBLDm, X86_INS_FBLD: fbld */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_FBSTPm, X86_INS_FBSTP: fbstp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_FCOM32m, X86_INS_FCOM: fcom */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_FCOM64m, X86_INS_FCOM: fcom */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_FCOMP32m, X86_INS_FCOMP: fcomp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_FCOMP64m, X86_INS_FCOMP: fcomp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_FCOMPP, X86_INS_FCOMPP: fcompp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { 0 } +}, + +{ /* X86_FDECSTP, X86_INS_FDECSTP: fdecstp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FDISI8087_NOP, X86_INS_FDISI8087_NOP: fdisi8087_nop */ + 0, + { 0 } +}, + +{ /* X86_FEMMS, X86_INS_FEMMS: femms */ + 0, + { 0 } +}, + +{ /* X86_FENI8087_NOP, X86_INS_FENI8087_NOP: feni8087_nop */ + 0, + { 0 } +}, + +{ /* X86_FFREE, X86_INS_FFREE: ffree */ + X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_FFREEP, X86_INS_FFREEP: ffreep */ + 0, + { 0 } +}, + +{ /* X86_FICOM16m, X86_INS_FICOM: ficom */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_FICOM32m, X86_INS_FICOM: ficom */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_FICOMP16m, X86_INS_FICOMP: ficomp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_FICOMP32m, X86_INS_FICOMP: ficomp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_FINCSTP, X86_INS_FINCSTP: fincstp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FLDCW16m, X86_INS_FLDCW: fldcw */ + X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_FLDENVm, X86_INS_FLDENV: fldenv */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_FLDL2E, X86_INS_FLDL2E: fldl2e */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FLDL2T, X86_INS_FLDL2T: fldl2t */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FLDLG2, X86_INS_FLDLG2: fldlg2 */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FLDLN2, X86_INS_FLDLN2: fldln2 */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FLDPI, X86_INS_FLDPI: fldpi */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FNCLEX, X86_INS_FNCLEX: fnclex */ + X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FNINIT, X86_INS_FNINIT: fninit */ + X86_FPU_FLAGS_RESET_C0 | X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_RESET_C2 | X86_FPU_FLAGS_RESET_C3, + { 0 } +}, + +{ /* X86_FNOP, X86_INS_FNOP: fnop */ + X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FNSTCW16m, X86_INS_FNSTCW: fnstcw */ + X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_FNSTSW16r, X86_INS_FNSTSW: fnstsw */ + X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_FNSTSWm, X86_INS_FNSTSW: fnstsw */ + X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_FPATAN, X86_INS_FPATAN: fpatan */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FPNCEST0r, X86_INS_FSTPNCE: fstpnce */ + 0, + { 0 } +}, + +{ /* X86_FPREM, X86_INS_FPREM: fprem */ + X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { 0 } +}, + +{ /* X86_FPREM1, X86_INS_FPREM1: fprem1 */ + X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { 0 } +}, + +{ /* X86_FPTAN, X86_INS_FPTAN: fptan */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FRNDINT, X86_INS_FRNDINT: frndint */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FRSTORm, X86_INS_FRSTOR: frstor */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_FSAVEm, X86_INS_FNSAVE: fnsave */ + X86_FPU_FLAGS_RESET_C0 | X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_RESET_C2 | X86_FPU_FLAGS_RESET_C3, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_FSCALE, X86_INS_FSCALE: fscale */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FSETPM, X86_INS_FSETPM: fsetpm */ + 0, + { 0 } +}, + +{ /* X86_FSINCOS, X86_INS_FSINCOS: fsincos */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FSTENVm, X86_INS_FNSTENV: fnstenv */ + X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_FXAM, X86_INS_FXAM: fxam */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { 0 } +}, + +{ /* X86_FXRSTOR, X86_INS_FXRSTOR: fxrstor */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_FXRSTOR64, X86_INS_FXRSTOR64: fxrstor64 */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_FXSAVE, X86_INS_FXSAVE: fxsave */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_FXSAVE64, X86_INS_FXSAVE64: fxsave64 */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_FXTRACT, X86_INS_FXTRACT: fxtract */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FYL2X, X86_INS_FYL2X: fyl2x */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_FYL2XP1, X86_INS_FYL2XP1: fyl2xp1 */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_GETSEC, X86_INS_GETSEC: getsec */ + 0, + { 0 } +}, + +{ /* X86_GF2P8AFFINEINVQBrmi, X86_INS_GF2P8AFFINEINVQB: gf2p8affineinvqb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_GF2P8AFFINEINVQBrri, X86_INS_GF2P8AFFINEINVQB: gf2p8affineinvqb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_GF2P8AFFINEQBrmi, X86_INS_GF2P8AFFINEQB: gf2p8affineqb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_GF2P8AFFINEQBrri, X86_INS_GF2P8AFFINEQB: gf2p8affineqb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_GF2P8MULBrm, X86_INS_GF2P8MULB: gf2p8mulb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_GF2P8MULBrr, X86_INS_GF2P8MULB: gf2p8mulb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_HADDPDrm, X86_INS_HADDPD: haddpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_HADDPDrr, X86_INS_HADDPD: haddpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_HADDPSrm, X86_INS_HADDPS: haddps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_HADDPSrr, X86_INS_HADDPS: haddps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_HLT, X86_INS_HLT: hlt */ + 0, + { 0 } +}, + +{ /* X86_HSUBPDrm, X86_INS_HSUBPD: hsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_HSUBPDrr, X86_INS_HSUBPD: hsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_HSUBPSrm, X86_INS_HSUBPS: hsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_HSUBPSrr, X86_INS_HSUBPS: hsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IDIV16m, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV16r, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV32m, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV32r, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV64m, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV64r, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV8m, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV8r, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_ILD_F16m, X86_INS_FILD: fild */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ILD_F32m, X86_INS_FILD: fild */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ILD_F64m, X86_INS_FILD: fild */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ILD_Fp16m32, X86_INS_FILD: fild */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_ILD_Fp16m64, X86_INS_FILD: fild */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_ILD_Fp16m80, X86_INS_FILD: fild */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_ILD_Fp32m32, X86_INS_FILD: fild */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_ILD_Fp32m64, X86_INS_FILD: fild */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_ILD_Fp32m80, X86_INS_FILD: fild */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_ILD_Fp64m32, X86_INS_FILD: fild */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_ILD_Fp64m64, X86_INS_FILD: fild */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_ILD_Fp64m80, X86_INS_FILD: fild */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL16m, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL16r, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL16rm, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IMUL16rmi, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL16rmi8, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL16rr, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IMUL16rri, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL16rri8, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL32m, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL32r, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL32rm, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IMUL32rmi, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL32rmi8, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL32rr, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IMUL32rri, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL32rri8, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL64m, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL64r, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL64rm, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IMUL64rmi32, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL64rmi8, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL64rr, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IMUL64rri32, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL64rri8, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL8m, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL8r, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IN16ri, X86_INS_IN: in */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IN16rr, X86_INS_IN: in */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IN32ri, X86_INS_IN: in */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IN32rr, X86_INS_IN: in */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IN8ri, X86_INS_IN: in */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IN8rr, X86_INS_IN: in */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_INC16m, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC16r, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC16r_alt, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC32m, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC32r, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC32r_alt, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC64m, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC64r, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC8m, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC8r, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INCSSPD, X86_INS_INCSSPD: incsspd */ + 0, + { 0 } +}, + +{ /* X86_INCSSPQ, X86_INS_INCSSPQ: incsspq */ + 0, + { 0 } +}, + +{ /* X86_INSB, X86_INS_INSB: insb */ + 0, + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_INSERTPSrm, X86_INS_INSERTPS: insertps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_INSERTPSrr, X86_INS_INSERTPS: insertps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_INSERTQ, X86_INS_INSERTQ: insertq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_INSERTQI, X86_INS_INSERTQ: insertq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_INSL, X86_INS_INSD: insd */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_INSW, X86_INS_INSW: insw */ + 0, + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_INT, X86_INS_INT: int */ + X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_INT1, X86_INS_INT1: int1 */ + X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_INT3, X86_INS_INT3: int3 */ + X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_INTO, X86_INS_INTO: into */ + X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_INVD, X86_INS_INVD: invd */ + 0, + { 0 } +}, + +{ /* X86_INVEPT32, X86_INS_INVEPT: invept */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVEPT64, X86_INS_INVEPT: invept */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVLPG, X86_INS_INVLPG: invlpg */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_INVLPGA32, X86_INS_INVLPGA: invlpga */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVLPGA64, X86_INS_INVLPGA: invlpga */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVPCID32, X86_INS_INVPCID: invpcid */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVPCID64, X86_INS_INVPCID: invpcid */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVVPID32, X86_INS_INVVPID: invvpid */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVVPID64, X86_INS_INVVPID: invvpid */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_IRET16, X86_INS_IRET: iret */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_IRET32, X86_INS_IRETD: iretd */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_IRET64, X86_INS_IRETQ: iretq */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_ISTT_FP16m, X86_INS_FISTTP: fisttp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ISTT_FP32m, X86_INS_FISTTP: fisttp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ISTT_FP64m, X86_INS_FISTTP: fisttp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ISTT_Fp16m32, X86_INS_FISTTP: fisttp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ISTT_Fp16m64, X86_INS_FISTTP: fisttp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ISTT_Fp16m80, X86_INS_FISTTP: fisttp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ISTT_Fp32m32, X86_INS_FISTTP: fisttp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ISTT_Fp32m64, X86_INS_FISTTP: fisttp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ISTT_Fp32m80, X86_INS_FISTTP: fisttp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ISTT_Fp64m32, X86_INS_FISTTP: fisttp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ISTT_Fp64m64, X86_INS_FISTTP: fisttp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ISTT_Fp64m80, X86_INS_FISTTP: fisttp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_IST_F16m, X86_INS_FIST: fist */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_IST_F32m, X86_INS_FIST: fist */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_IST_FP16m, X86_INS_FISTP: fistp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_IST_FP32m, X86_INS_FISTP: fistp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_IST_FP64m, X86_INS_FISTP: fistp */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_IST_Fp16m32, X86_INS_FISTP: fistp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_IST_Fp16m64, X86_INS_FISTP: fistp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_IST_Fp16m80, X86_INS_FISTP: fistp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_IST_Fp32m32, X86_INS_FISTP: fistp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_IST_Fp32m64, X86_INS_FISTP: fistp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_IST_Fp32m80, X86_INS_FISTP: fistp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_IST_Fp64m32, X86_INS_FISTP: fistp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_IST_Fp64m64, X86_INS_FISTP: fistp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_IST_Fp64m80, X86_INS_FISTP: fistp */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_JAE_1, X86_INS_JAE: jae */ + X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JAE_2, X86_INS_JAE: jae $dst */ + X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JAE_4, X86_INS_JAE: jae $dst */ + X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JA_1, X86_INS_JA: ja */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JA_2, X86_INS_JA: ja $dst */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JA_4, X86_INS_JA: ja $dst */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JBE_1, X86_INS_JBE: jbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JBE_2, X86_INS_JBE: jbe $dst */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JBE_4, X86_INS_JBE: jbe $dst */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JB_1, X86_INS_JB: jb */ + X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JB_2, X86_INS_JB: jb $dst */ + X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JB_4, X86_INS_JB: jb $dst */ + X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JCXZ, X86_INS_JCXZ: jcxz */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JECXZ, X86_INS_JECXZ: jecxz */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JE_1, X86_INS_JE: je */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JE_2, X86_INS_JE: je $dst */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JE_4, X86_INS_JE: je $dst */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JGE_1, X86_INS_JGE: jge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JGE_2, X86_INS_JGE: jge $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JGE_4, X86_INS_JGE: jge $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JG_1, X86_INS_JG: jg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JG_2, X86_INS_JG: jg $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JG_4, X86_INS_JG: jg $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JLE_1, X86_INS_JLE: jle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JLE_2, X86_INS_JLE: jle $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JLE_4, X86_INS_JLE: jle $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JL_1, X86_INS_JL: jl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JL_2, X86_INS_JL: jl $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JL_4, X86_INS_JL: jl $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JMP16m, X86_INS_JMP: jmp */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_JMP16m_NT, X86_INS_JMP: jmp */ + 0, + { 0 } +}, + +{ /* X86_JMP16r, X86_INS_JMP: jmp */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_JMP16r_NT, X86_INS_JMP: jmp */ + 0, + { 0 } +}, + +{ /* X86_JMP32m, X86_INS_JMP: jmp */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_JMP32m_NT, X86_INS_JMP: jmp */ + 0, + { 0 } +}, + +{ /* X86_JMP32r, X86_INS_JMP: jmp */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_JMP32r_NT, X86_INS_JMP: jmp */ + 0, + { 0 } +}, + +{ /* X86_JMP64m, X86_INS_JMP: jmp */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_JMP64m_NT, X86_INS_JMP: jmp */ + 0, + { 0 } +}, + +{ /* X86_JMP64r, X86_INS_JMP: jmp */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_JMP64r_NT, X86_INS_JMP: jmp */ + 0, + { 0 } +}, + +{ /* X86_JMP_1, X86_INS_JMP: jmp */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JMP_2, X86_INS_JMP: jmp $dst */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JMP_4, X86_INS_JMP: jmp $dst */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNE_1, X86_INS_JNE: jne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNE_2, X86_INS_JNE: jne $dst */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNE_4, X86_INS_JNE: jne $dst */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNO_1, X86_INS_JNO: jno */ + X86_EFLAGS_TEST_OF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNO_2, X86_INS_JNO: jno $dst */ + X86_EFLAGS_TEST_OF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNO_4, X86_INS_JNO: jno $dst */ + X86_EFLAGS_TEST_OF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNP_1, X86_INS_JNP: jnp */ + X86_EFLAGS_TEST_PF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNP_2, X86_INS_JNP: jnp $dst */ + X86_EFLAGS_TEST_PF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNP_4, X86_INS_JNP: jnp $dst */ + X86_EFLAGS_TEST_PF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNS_1, X86_INS_JNS: jns */ + X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNS_2, X86_INS_JNS: jns $dst */ + X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNS_4, X86_INS_JNS: jns $dst */ + X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JO_1, X86_INS_JO: jo */ + X86_EFLAGS_TEST_OF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JO_2, X86_INS_JO: jo $dst */ + X86_EFLAGS_TEST_OF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JO_4, X86_INS_JO: jo $dst */ + X86_EFLAGS_TEST_OF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JP_1, X86_INS_JP: jp */ + X86_EFLAGS_TEST_PF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JP_2, X86_INS_JP: jp $dst */ + X86_EFLAGS_TEST_PF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JP_4, X86_INS_JP: jp $dst */ + X86_EFLAGS_TEST_PF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JRCXZ, X86_INS_JRCXZ: jrcxz */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JS_1, X86_INS_JS: js */ + X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JS_2, X86_INS_JS: js $dst */ + X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JS_4, X86_INS_JS: js $dst */ + X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_KADDBrr, X86_INS_KADDB: kaddb */ + 0, + { 0 } +}, + +{ /* X86_KADDDrr, X86_INS_KADDD: kaddd */ + 0, + { 0 } +}, + +{ /* X86_KADDQrr, X86_INS_KADDQ: kaddq */ + 0, + { 0 } +}, + +{ /* X86_KADDWrr, X86_INS_KADDW: kaddw */ + 0, + { 0 } +}, + +{ /* X86_KANDBrr, X86_INS_KANDB: kandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KANDDrr, X86_INS_KANDD: kandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KANDNBrr, X86_INS_KANDNB: kandnb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KANDNDrr, X86_INS_KANDND: kandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KANDNQrr, X86_INS_KANDNQ: kandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KANDNWrr, X86_INS_KANDNW: kandnw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KANDQrr, X86_INS_KANDQ: kandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KANDWrr, X86_INS_KANDW: kandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVBkk, X86_INS_KMOVB: kmovb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVBkm, X86_INS_KMOVB: kmovb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVBkr, X86_INS_KMOVB: kmovb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVBmk, X86_INS_KMOVB: kmovb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVBrk, X86_INS_KMOVB: kmovb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVDkk, X86_INS_KMOVD: kmovd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVDkm, X86_INS_KMOVD: kmovd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVDkr, X86_INS_KMOVD: kmovd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVDmk, X86_INS_KMOVD: kmovd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVDrk, X86_INS_KMOVD: kmovd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVQkk, X86_INS_KMOVQ: kmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVQkm, X86_INS_KMOVQ: kmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVQkr, X86_INS_KMOVQ: kmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVQmk, X86_INS_KMOVQ: kmovq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVQrk, X86_INS_KMOVQ: kmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVWkk, X86_INS_KMOVW: kmovw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVWkm, X86_INS_KMOVW: kmovw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVWkr, X86_INS_KMOVW: kmovw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVWmk, X86_INS_KMOVW: kmovw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KMOVWrk, X86_INS_KMOVW: kmovw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KNOTBrr, X86_INS_KNOTB: knotb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KNOTDrr, X86_INS_KNOTD: knotd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KNOTQrr, X86_INS_KNOTQ: knotq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KNOTWrr, X86_INS_KNOTW: knotw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_KORBrr, X86_INS_KORB: korb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KORDrr, X86_INS_KORD: kord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KORQrr, X86_INS_KORQ: korq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KORTESTBrr, X86_INS_KORTESTB: kortestb */ + X86_REG_EFLAGS, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KORTESTDrr, X86_INS_KORTESTD: kortestd */ + X86_REG_EFLAGS, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KORTESTQrr, X86_INS_KORTESTQ: kortestq */ + X86_REG_EFLAGS, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KORTESTWrr, X86_INS_KORTESTW: kortestw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KORWrr, X86_INS_KORW: korw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KSHIFTLBri, X86_INS_KSHIFTLB: kshiftlb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_KSHIFTLDri, X86_INS_KSHIFTLD: kshiftld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_KSHIFTLQri, X86_INS_KSHIFTLQ: kshiftlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_KSHIFTLWri, X86_INS_KSHIFTLW: kshiftlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_KSHIFTRBri, X86_INS_KSHIFTRB: kshiftrb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_KSHIFTRDri, X86_INS_KSHIFTRD: kshiftrd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_KSHIFTRQri, X86_INS_KSHIFTRQ: kshiftrq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_KSHIFTRWri, X86_INS_KSHIFTRW: kshiftrw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_KTESTBrr, X86_INS_KTESTB: ktestb */ + 0, + { 0 } +}, + +{ /* X86_KTESTDrr, X86_INS_KTESTD: ktestd */ + 0, + { 0 } +}, + +{ /* X86_KTESTQrr, X86_INS_KTESTQ: ktestq */ + 0, + { 0 } +}, + +{ /* X86_KTESTWrr, X86_INS_KTESTW: ktestw */ + 0, + { 0 } +}, + +{ /* X86_KUNPCKBWrr, X86_INS_KUNPCKBW: kunpckbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KUNPCKDQrr, X86_INS_KUNPCKDQ: kunpckdq */ + 0, + { 0 } +}, + +{ /* X86_KUNPCKWDrr, X86_INS_KUNPCKWD: kunpckwd */ + 0, + { 0 } +}, + +{ /* X86_KXNORBrr, X86_INS_KXNORB: kxnorb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KXNORDrr, X86_INS_KXNORD: kxnord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KXNORQrr, X86_INS_KXNORQ: kxnorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KXNORWrr, X86_INS_KXNORW: kxnorw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KXORBrr, X86_INS_KXORB: kxorb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KXORDrr, X86_INS_KXORD: kxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KXORQrr, X86_INS_KXORQ: kxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_KXORWrr, X86_INS_KXORW: kxorw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_LAHF, X86_INS_LAHF: lahf */ + 0, + { 0 } +}, + +{ /* X86_LAR16rm, X86_INS_LAR: lar */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LAR16rr, X86_INS_LAR: lar */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LAR32rm, X86_INS_LAR: lar */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LAR32rr, X86_INS_LAR: lar */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LAR64rm, X86_INS_LAR: lar */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LAR64rr, X86_INS_LAR: lar */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LDDQUrm, X86_INS_LDDQU: lddqu */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LDMXCSR, X86_INS_LDMXCSR: ldmxcsr */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LDS16rm, X86_INS_LDS: lds */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LDS32rm, X86_INS_LDS: lds */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LD_F0, X86_INS_FLDZ: fldz */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_LD_F1, X86_INS_FLD1: fld1 */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_LD_F32m, X86_INS_FLD: fld */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_F64m, X86_INS_FLD: fld */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_F80m, X86_INS_FLD: fld */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Fp032, X86_INS_FLD: fld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Fp064, X86_INS_FLD: fld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Fp080, X86_INS_FLD: fld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Fp132, X86_INS_FLD: fld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Fp164, X86_INS_FLD: fld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Fp180, X86_INS_FLD: fld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Fp32m, X86_INS_FLD: fld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Fp32m64, X86_INS_FLD: fld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Fp32m80, X86_INS_FLD: fld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Fp64m, X86_INS_FLD: fld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Fp64m80, X86_INS_FLD: fld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Fp80m, X86_INS_FLD: fld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LD_Frr, X86_INS_FLD: fld */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_LEA16r, X86_INS_LEA: lea */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LEA32r, X86_INS_LEA: lea */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LEA64_32r, X86_INS_LEA: lea */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LEA64r, X86_INS_LEA: lea */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LEAVE, X86_INS_LEAVE: leave */ + 0, + { 0 } +}, + +{ /* X86_LEAVE64, X86_INS_LEAVE: leave */ + 0, + { 0 } +}, + +{ /* X86_LES16rm, X86_INS_LES: les */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LES32rm, X86_INS_LES: les */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LFENCE, X86_INS_LFENCE: lfence */ + 0, + { 0 } +}, + +{ /* X86_LFS16rm, X86_INS_LFS: lfs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LFS32rm, X86_INS_LFS: lfs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LFS64rm, X86_INS_LFS: lfs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LGDT16m, X86_INS_LGDT: lgdt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LGDT32m, X86_INS_LGDT: lgdt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LGDT64m, X86_INS_LGDT: lgdt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LGS16rm, X86_INS_LGS: lgs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LGS32rm, X86_INS_LGS: lgs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LGS64rm, X86_INS_LGS: lgs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LIDT16m, X86_INS_LIDT: lidt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LIDT32m, X86_INS_LIDT: lidt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LIDT64m, X86_INS_LIDT: lidt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LLDT16m, X86_INS_LLDT: lldt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LLDT16r, X86_INS_LLDT: lldt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LLWPCB, X86_INS_LLWPCB: llwpcb */ + 0, + { 0 } +}, + +{ /* X86_LLWPCB64, X86_INS_LLWPCB: llwpcb */ + 0, + { 0 } +}, + +{ /* X86_LMSW16m, X86_INS_LMSW: lmsw */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LMSW16r, X86_INS_LMSW: lmsw */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LOCK_PREFIX, X86_INS_LOCK: lock */ + 0, + { 0 } +}, + +{ /* X86_LODSB, X86_INS_LODSB: lodsb */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LODSL, X86_INS_LODSD: lodsd */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LODSQ, X86_INS_LODSQ: lodsq */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LODSW, X86_INS_LODSW: lodsw */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LOOP, X86_INS_LOOP: loop */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LOOPE, X86_INS_LOOPE: loope */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LOOPNE, X86_INS_LOOPNE: loopne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LRETIL, X86_INS_RETF: retf */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LRETIQ, X86_INS_RETFQ: retfq */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LRETIW, X86_INS_RETF: retf */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LRETL, X86_INS_RETF: retf */ + 0, + { 0 } +}, + +{ /* X86_LRETQ, X86_INS_RETFQ: retfq */ + 0, + { 0 } +}, + +{ /* X86_LRETW, X86_INS_RETF: retf */ + 0, + { 0 } +}, + +{ /* X86_LSL16rm, X86_INS_LSL: lsl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSL16rr, X86_INS_LSL: lsl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSL32rm, X86_INS_LSL: lsl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSL32rr, X86_INS_LSL: lsl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSL64rm, X86_INS_LSL: lsl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSL64rr, X86_INS_LSL: lsl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSS16rm, X86_INS_LSS: lss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSS32rm, X86_INS_LSS: lss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSS64rm, X86_INS_LSS: lss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LTRm, X86_INS_LTR: ltr */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LTRr, X86_INS_LTR: ltr */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LWPINS32rmi, X86_INS_LWPINS: lwpins */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_LWPINS32rri, X86_INS_LWPINS: lwpins */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_LWPINS64rmi, X86_INS_LWPINS: lwpins */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_LWPINS64rri, X86_INS_LWPINS: lwpins */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_LWPVAL32rmi, X86_INS_LWPVAL: lwpval */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_LWPVAL32rri, X86_INS_LWPVAL: lwpval */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_LWPVAL64rmi, X86_INS_LWPVAL: lwpval */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_LWPVAL64rri, X86_INS_LWPVAL: lwpval */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_LZCNT16rm, X86_INS_LZCNT: lzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LZCNT16rr, X86_INS_LZCNT: lzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LZCNT32rm, X86_INS_LZCNT: lzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LZCNT32rr, X86_INS_LZCNT: lzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LZCNT64rm, X86_INS_LZCNT: lzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LZCNT64rr, X86_INS_LZCNT: lzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MASKMOVDQU, X86_INS_MASKMOVDQU: maskmovdqu */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MASKMOVDQU64, X86_INS_MASKMOVDQU: maskmovdqu */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MAXCPDrm, X86_INS_MAXPD: maxpd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXCPDrr, X86_INS_MAXPD: maxpd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXCPSrm, X86_INS_MAXPS: maxps $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXCPSrr, X86_INS_MAXPS: maxps $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXCSDrm, X86_INS_MAXSD: maxsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXCSDrr, X86_INS_MAXSD: maxsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXCSSrm, X86_INS_MAXSS: maxss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXCSSrr, X86_INS_MAXSS: maxss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXPDrm, X86_INS_MAXPD: maxpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXPDrr, X86_INS_MAXPD: maxpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXPSrm, X86_INS_MAXPS: maxps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXPSrr, X86_INS_MAXPS: maxps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXSDrm, X86_INS_MAXSD: maxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXSDrm_Int, X86_INS_MAXSD: maxsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MAXSDrr, X86_INS_MAXSD: maxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXSDrr_Int, X86_INS_MAXSD: maxsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXSSrm, X86_INS_MAXSS: maxss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXSSrm_Int, X86_INS_MAXSS: maxss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MAXSSrr, X86_INS_MAXSS: maxss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MAXSSrr_Int, X86_INS_MAXSS: maxss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MFENCE, X86_INS_MFENCE: mfence */ + 0, + { 0 } +}, + +{ /* X86_MINCPDrm, X86_INS_MINPD: minpd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINCPDrr, X86_INS_MINPD: minpd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINCPSrm, X86_INS_MINPS: minps $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINCPSrr, X86_INS_MINPS: minps $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINCSDrm, X86_INS_MINSD: minsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINCSDrr, X86_INS_MINSD: minsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINCSSrm, X86_INS_MINSS: minss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINCSSrr, X86_INS_MINSS: minss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINPDrm, X86_INS_MINPD: minpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINPDrr, X86_INS_MINPD: minpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINPSrm, X86_INS_MINPS: minps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINPSrr, X86_INS_MINPS: minps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINSDrm, X86_INS_MINSD: minsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINSDrm_Int, X86_INS_MINSD: minsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MINSDrr, X86_INS_MINSD: minsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINSDrr_Int, X86_INS_MINSD: minsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINSSrm, X86_INS_MINSS: minss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINSSrm_Int, X86_INS_MINSS: minss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MINSSrr, X86_INS_MINSS: minss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MINSSrr_Int, X86_INS_MINSS: minss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_CVTPD2PIirm, X86_INS_CVTPD2PI: cvtpd2pi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_CVTPD2PIirr, X86_INS_CVTPD2PI: cvtpd2pi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_CVTPI2PDirm, X86_INS_CVTPI2PD: cvtpi2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_CVTPI2PDirr, X86_INS_CVTPI2PD: cvtpi2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_CVTPI2PSirm, X86_INS_CVTPI2PS: cvtpi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_CVTPI2PSirr, X86_INS_CVTPI2PS: cvtpi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_CVTPS2PIirm, X86_INS_CVTPS2PI: cvtps2pi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_CVTPS2PIirr, X86_INS_CVTPS2PI: cvtps2pi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_CVTTPD2PIirm, X86_INS_CVTTPD2PI: cvttpd2pi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_CVTTPD2PIirr, X86_INS_CVTTPD2PI: cvttpd2pi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_CVTTPS2PIirm, X86_INS_CVTTPS2PI: cvttps2pi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_CVTTPS2PIirr, X86_INS_CVTTPS2PI: cvttps2pi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_EMMS, X86_INS_EMMS: emms */ + 0, + { 0 } +}, + +{ /* X86_MMX_MASKMOVQ, X86_INS_MASKMOVQ: maskmovq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MASKMOVQ64, X86_INS_MASKMOVQ: maskmovq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVD64from64rm, X86_INS_MOVD: movd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVD64from64rr, X86_INS_MOVQ: movq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVD64grr, X86_INS_MOVD: movd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVD64mr, X86_INS_MOVD: movd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVD64rm, X86_INS_MOVD: movd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVD64rr, X86_INS_MOVD: movd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVD64to64rm, X86_INS_MOVD: movd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVD64to64rr, X86_INS_MOVQ: movq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVDQ2Qrr, X86_INS_MOVDQ2Q: movdq2q */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVFR642Qrr, X86_INS_MOVDQ2Q: movdq2q $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVNTQmr, X86_INS_MOVNTQ: movntq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVQ2DQrr, X86_INS_MOVQ2DQ: movq2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVQ2FR64rr, X86_INS_MOVQ2DQ: movq2dq $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVQ64mr, X86_INS_MOVQ: movq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVQ64rm, X86_INS_MOVQ: movq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVQ64rr, X86_INS_MOVQ: movq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_MOVQ64rr_REV, X86_INS_MOVQ: movq $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PABSBrm, X86_INS_PABSB: pabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PABSBrr, X86_INS_PABSB: pabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PABSDrm, X86_INS_PABSD: pabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PABSDrr, X86_INS_PABSD: pabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PABSWrm, X86_INS_PABSW: pabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PABSWrr, X86_INS_PABSW: pabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PACKSSDWirm, X86_INS_PACKSSDW: packssdw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PACKSSDWirr, X86_INS_PACKSSDW: packssdw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PACKSSWBirm, X86_INS_PACKSSWB: packsswb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PACKSSWBirr, X86_INS_PACKSSWB: packsswb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PACKUSWBirm, X86_INS_PACKUSWB: packuswb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PACKUSWBirr, X86_INS_PACKUSWB: packuswb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDBirm, X86_INS_PADDB: paddb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDBirr, X86_INS_PADDB: paddb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDDirm, X86_INS_PADDD: paddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDDirr, X86_INS_PADDD: paddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDQirm, X86_INS_PADDQ: paddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDQirr, X86_INS_PADDQ: paddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDSBirm, X86_INS_PADDSB: paddsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDSBirr, X86_INS_PADDSB: paddsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDSWirm, X86_INS_PADDSW: paddsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDSWirr, X86_INS_PADDSW: paddsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDUSBirm, X86_INS_PADDUSB: paddusb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDUSBirr, X86_INS_PADDUSB: paddusb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDUSWirm, X86_INS_PADDUSW: paddusw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDUSWirr, X86_INS_PADDUSW: paddusw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDWirm, X86_INS_PADDW: paddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PADDWirr, X86_INS_PADDW: paddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PALIGNRrmi, X86_INS_PALIGNR: palignr */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MMX_PALIGNRrri, X86_INS_PALIGNR: palignr */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MMX_PANDNirm, X86_INS_PANDN: pandn */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PANDNirr, X86_INS_PANDN: pandn */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PANDirm, X86_INS_PAND: pand */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PANDirr, X86_INS_PAND: pand */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PAVGBirm, X86_INS_PAVGB: pavgb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PAVGBirr, X86_INS_PAVGB: pavgb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PAVGWirm, X86_INS_PAVGW: pavgw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PAVGWirr, X86_INS_PAVGW: pavgw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PCMPEQBirm, X86_INS_PCMPEQB: pcmpeqb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PCMPEQBirr, X86_INS_PCMPEQB: pcmpeqb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PCMPEQDirm, X86_INS_PCMPEQD: pcmpeqd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PCMPEQDirr, X86_INS_PCMPEQD: pcmpeqd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PCMPEQWirm, X86_INS_PCMPEQW: pcmpeqw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PCMPEQWirr, X86_INS_PCMPEQW: pcmpeqw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PCMPGTBirm, X86_INS_PCMPGTB: pcmpgtb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PCMPGTBirr, X86_INS_PCMPGTB: pcmpgtb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PCMPGTDirm, X86_INS_PCMPGTD: pcmpgtd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PCMPGTDirr, X86_INS_PCMPGTD: pcmpgtd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PCMPGTWirm, X86_INS_PCMPGTW: pcmpgtw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PCMPGTWirr, X86_INS_PCMPGTW: pcmpgtw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PEXTRWrr, X86_INS_PEXTRW: pextrw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PHADDDrm, X86_INS_PHADDD: phaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PHADDDrr, X86_INS_PHADDD: phaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PHADDSWrm, X86_INS_PHADDSW: phaddsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PHADDSWrr, X86_INS_PHADDSW: phaddsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PHADDWrm, X86_INS_PHADDW: phaddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PHADDWrr, X86_INS_PHADDW: phaddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PHSUBDrm, X86_INS_PHSUBD: phsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PHSUBDrr, X86_INS_PHSUBD: phsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PHSUBSWrm, X86_INS_PHSUBSW: phsubsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PHSUBSWrr, X86_INS_PHSUBSW: phsubsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PHSUBWrm, X86_INS_PHSUBW: phsubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PHSUBWrr, X86_INS_PHSUBW: phsubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PINSRWrm, X86_INS_PINSRW: pinsrw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PINSRWrr, X86_INS_PINSRW: pinsrw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMADDUBSWrm, X86_INS_PMADDUBSW: pmaddubsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMADDUBSWrr, X86_INS_PMADDUBSW: pmaddubsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMADDWDirm, X86_INS_PMADDWD: pmaddwd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMADDWDirr, X86_INS_PMADDWD: pmaddwd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMAXSWirm, X86_INS_PMAXSW: pmaxsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMAXSWirr, X86_INS_PMAXSW: pmaxsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMAXUBirm, X86_INS_PMAXUB: pmaxub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMAXUBirr, X86_INS_PMAXUB: pmaxub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMINSWirm, X86_INS_PMINSW: pminsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMINSWirr, X86_INS_PMINSW: pminsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMINUBirm, X86_INS_PMINUB: pminub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMINUBirr, X86_INS_PMINUB: pminub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMOVMSKBrr, X86_INS_PMOVMSKB: pmovmskb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMULHRSWrm, X86_INS_PMULHRSW: pmulhrsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMULHRSWrr, X86_INS_PMULHRSW: pmulhrsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMULHUWirm, X86_INS_PMULHUW: pmulhuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMULHUWirr, X86_INS_PMULHUW: pmulhuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMULHWirm, X86_INS_PMULHW: pmulhw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMULHWirr, X86_INS_PMULHW: pmulhw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMULLWirm, X86_INS_PMULLW: pmullw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMULLWirr, X86_INS_PMULLW: pmullw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMULUDQirm, X86_INS_PMULUDQ: pmuludq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PMULUDQirr, X86_INS_PMULUDQ: pmuludq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PORirm, X86_INS_POR: por */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PORirr, X86_INS_POR: por */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSADBWirm, X86_INS_PSADBW: psadbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSADBWirr, X86_INS_PSADBW: psadbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSHUFBrm, X86_INS_PSHUFB: pshufb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSHUFBrr, X86_INS_PSHUFB: pshufb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSHUFWmi, X86_INS_PSHUFW: pshufw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MMX_PSHUFWri, X86_INS_PSHUFW: pshufw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MMX_PSIGNBrm, X86_INS_PSIGNB: psignb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSIGNBrr, X86_INS_PSIGNB: psignb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSIGNDrm, X86_INS_PSIGND: psignd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSIGNDrr, X86_INS_PSIGND: psignd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSIGNWrm, X86_INS_PSIGNW: psignw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSIGNWrr, X86_INS_PSIGNW: psignw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSLLDri, X86_INS_PSLLD: pslld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MMX_PSLLDrm, X86_INS_PSLLD: pslld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSLLDrr, X86_INS_PSLLD: pslld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSLLQri, X86_INS_PSLLQ: psllq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MMX_PSLLQrm, X86_INS_PSLLQ: psllq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSLLQrr, X86_INS_PSLLQ: psllq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSLLWri, X86_INS_PSLLW: psllw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MMX_PSLLWrm, X86_INS_PSLLW: psllw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSLLWrr, X86_INS_PSLLW: psllw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSRADri, X86_INS_PSRAD: psrad */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MMX_PSRADrm, X86_INS_PSRAD: psrad */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSRADrr, X86_INS_PSRAD: psrad */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSRAWri, X86_INS_PSRAW: psraw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MMX_PSRAWrm, X86_INS_PSRAW: psraw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSRAWrr, X86_INS_PSRAW: psraw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSRLDri, X86_INS_PSRLD: psrld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MMX_PSRLDrm, X86_INS_PSRLD: psrld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSRLDrr, X86_INS_PSRLD: psrld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSRLQri, X86_INS_PSRLQ: psrlq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MMX_PSRLQrm, X86_INS_PSRLQ: psrlq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSRLQrr, X86_INS_PSRLQ: psrlq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSRLWri, X86_INS_PSRLW: psrlw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MMX_PSRLWrm, X86_INS_PSRLW: psrlw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSRLWrr, X86_INS_PSRLW: psrlw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBBirm, X86_INS_PSUBB: psubb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBBirr, X86_INS_PSUBB: psubb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBDirm, X86_INS_PSUBD: psubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBDirr, X86_INS_PSUBD: psubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBQirm, X86_INS_PSUBQ: psubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBQirr, X86_INS_PSUBQ: psubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBSBirm, X86_INS_PSUBSB: psubsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBSBirr, X86_INS_PSUBSB: psubsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBSWirm, X86_INS_PSUBSW: psubsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBSWirr, X86_INS_PSUBSW: psubsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBUSBirm, X86_INS_PSUBUSB: psubusb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBUSBirr, X86_INS_PSUBUSB: psubusb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBUSWirm, X86_INS_PSUBUSW: psubusw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBUSWirr, X86_INS_PSUBUSW: psubusw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBWirm, X86_INS_PSUBW: psubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PSUBWirr, X86_INS_PSUBW: psubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PUNPCKHBWirm, X86_INS_PUNPCKHBW: punpckhbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PUNPCKHBWirr, X86_INS_PUNPCKHBW: punpckhbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PUNPCKHDQirm, X86_INS_PUNPCKHDQ: punpckhdq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PUNPCKHDQirr, X86_INS_PUNPCKHDQ: punpckhdq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PUNPCKHWDirm, X86_INS_PUNPCKHWD: punpckhwd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PUNPCKHWDirr, X86_INS_PUNPCKHWD: punpckhwd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PUNPCKLBWirm, X86_INS_PUNPCKLBW: punpcklbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PUNPCKLBWirr, X86_INS_PUNPCKLBW: punpcklbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PUNPCKLDQirm, X86_INS_PUNPCKLDQ: punpckldq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PUNPCKLDQirr, X86_INS_PUNPCKLDQ: punpckldq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PUNPCKLWDirm, X86_INS_PUNPCKLWD: punpcklwd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PUNPCKLWDirr, X86_INS_PUNPCKLWD: punpcklwd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PXORirm, X86_INS_PXOR: pxor */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MMX_PXORirr, X86_INS_PXOR: pxor */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MONITORXrrr, X86_INS_MONITORX: monitorx */ + 0, + { 0 } +}, + +{ /* X86_MONITORrrr, X86_INS_MONITOR: monitor */ + 0, + { 0 } +}, + +{ /* X86_MONTMUL, X86_INS_MONTMUL: montmul */ + 0, + { 0 } +}, + +{ /* X86_MOV16ao16, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16ao32, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16ao64, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16mi, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV16mr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16ms, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16o16a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16o32a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16o64a, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16ri, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV16ri_alt, X86_INS_MOV: mov{w} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV16rm, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16rr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16rr_REV, X86_INS_MOV: mov{w} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16rs, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16sm, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16sr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32ao16, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32ao32, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32ao64, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32cr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32dr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32mi, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV32mr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32o16a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32o32a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32o64a, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32rc, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32rd, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32ri, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV32ri_alt, X86_INS_MOV: mov{l} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV32rm, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32rr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32rr_REV, X86_INS_MOV: mov{l} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32rs, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32sr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64ao32, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64ao64, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64cr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64dr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64mi32, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV64mr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64o32a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64o64a, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64rc, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64rd, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64ri, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV64ri32, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV64rm, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64rr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64rr_REV, X86_INS_MOV: mov{q} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64rs, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64sr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64toPQIrm, X86_INS_MOVQ: mov{d|q} {$src $dst|$dst $src} */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64toPQIrr, X86_INS_MOVQ: movq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64toSDrm, X86_INS_MOVQ: movq $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64toSDrr, X86_INS_MOVQ: mov{d|q} {$src $dst|$dst $src} */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8ao16, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8ao32, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8ao64, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8mi, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV8mr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8mr_NOREX, X86_INS_MOV: mov{b} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8o16a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8o32a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8o64a, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8ri, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV8ri_alt, X86_INS_MOV: mov{b} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV8rm, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8rm_NOREX, X86_INS_MOV: mov{b} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8rr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8rr_NOREX, X86_INS_MOV: mov{b} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8rr_REV, X86_INS_MOV: mov{b} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVAPDmr, X86_INS_MOVAPD: movapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVAPDrm, X86_INS_MOVAPD: movapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVAPDrr, X86_INS_MOVAPD: movapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVAPDrr_REV, X86_INS_MOVAPD: movapd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVAPSmr, X86_INS_MOVAPS: movaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVAPSrm, X86_INS_MOVAPS: movaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVAPSrr, X86_INS_MOVAPS: movaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVAPSrr_REV, X86_INS_MOVAPS: movaps $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVBE16mr, X86_INS_MOVBE: movbe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVBE16rm, X86_INS_MOVBE: movbe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVBE32mr, X86_INS_MOVBE: movbe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVBE32rm, X86_INS_MOVBE: movbe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVBE64mr, X86_INS_MOVBE: movbe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVBE64rm, X86_INS_MOVBE: movbe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDDUPrm, X86_INS_MOVDDUP: movddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDDUPrr, X86_INS_MOVDDUP: movddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDI2PDIrm, X86_INS_MOVD: movd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDI2PDIrr, X86_INS_MOVD: movd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDI2SSrm, X86_INS_MOVD: movd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDI2SSrr, X86_INS_MOVD: movd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDIR64B16, X86_INS_MOVDIR64B: movdir64b */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* X86_MOVDIR64B32, X86_INS_MOVDIR64B: movdir64b */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* X86_MOVDIR64B64, X86_INS_MOVDIR64B: movdir64b */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* X86_MOVDIRI32, X86_INS_MOVDIRI: movdiri */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDIRI64, X86_INS_MOVDIRI: movdiri */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDQAmr, X86_INS_MOVDQA: movdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDQArm, X86_INS_MOVDQA: movdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDQArr, X86_INS_MOVDQA: movdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDQArr_REV, X86_INS_MOVDQA: movdqa $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDQUmr, X86_INS_MOVDQU: movdqu */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDQUrm, X86_INS_MOVDQU: movdqu */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDQUrr, X86_INS_MOVDQU: movdqu */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDQUrr_REV, X86_INS_MOVDQU: movdqu $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVHLPSrr, X86_INS_MOVHLPS: movhlps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVHPDmr, X86_INS_MOVHPD: movhpd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVHPDrm, X86_INS_MOVHPD: movhpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVHPSmr, X86_INS_MOVHPS: movhps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVHPSrm, X86_INS_MOVHPS: movhps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVLHPSrr, X86_INS_MOVLHPS: movlhps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVLPDmr, X86_INS_MOVLPD: movlpd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVLPDrm, X86_INS_MOVLPD: movlpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVLPSmr, X86_INS_MOVLPS: movlps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVLPSrm, X86_INS_MOVLPS: movlps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVMSKPDrr, X86_INS_MOVMSKPD: movmskpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVMSKPSrr, X86_INS_MOVMSKPS: movmskps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVNTDQArm, X86_INS_MOVNTDQA: movntdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVNTDQmr, X86_INS_MOVNTDQ: movntdq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVNTI_64mr, X86_INS_MOVNTI: movnti */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVNTImr, X86_INS_MOVNTI: movnti */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVNTPDmr, X86_INS_MOVNTPD: movntpd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVNTPSmr, X86_INS_MOVNTPS: movntps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVNTSD, X86_INS_MOVNTSD: movntsd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVNTSS, X86_INS_MOVNTSS: movntss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVPDI2DImr, X86_INS_MOVD: movd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVPDI2DIrr, X86_INS_MOVD: movd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVPQI2QImr, X86_INS_MOVQ: movq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVPQI2QIrr, X86_INS_MOVQ: movq $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVPQIto64mr, X86_INS_MOVQ: movq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVPQIto64rr, X86_INS_MOVQ: movq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVQI2PQIrm, X86_INS_MOVQ: movq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSB, X86_INS_MOVSB: movsb */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSDmr, X86_INS_MOVSD: movsd */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSDrm, X86_INS_MOVSD: movsd */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSDrr, X86_INS_MOVSD: movsd */ + X86_EFLAGS_TEST_DF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSDrr_REV, X86_INS_MOVSD: movsd $dst $src2 */ + X86_EFLAGS_TEST_DF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSDto64mr, X86_INS_MOVQ: movq $dst $src */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSDto64rr, X86_INS_MOVQ: mov{d|q} {$src $dst|$dst $src} */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSHDUPrm, X86_INS_MOVSHDUP: movshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSHDUPrr, X86_INS_MOVSHDUP: movshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSL, X86_INS_MOVSD: movsd */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSLDUPrm, X86_INS_MOVSLDUP: movsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSLDUPrr, X86_INS_MOVSLDUP: movsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSQ, X86_INS_MOVSQ: movsq */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSS2DImr, X86_INS_MOVD: movd $dst $src */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSS2DIrr, X86_INS_MOVD: movd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSSmr, X86_INS_MOVSS: movss */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSSrm, X86_INS_MOVSS: movss */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSSrr, X86_INS_MOVSS: movss */ + X86_EFLAGS_TEST_DF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSSrr_REV, X86_INS_MOVSS: movss $dst $src2 */ + X86_EFLAGS_TEST_DF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSW, X86_INS_MOVSW: movsw */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX16rm16, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX16rm8, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX16rr16, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX16rr8, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX32rm16, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX32rm8, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX32rm8_NOREX, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX32rr16, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX32rr8, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX32rr8_NOREX, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX64rm16, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX64rm32, X86_INS_MOVSXD: movsxd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX64rm8, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX64rr16, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX64rr32, X86_INS_MOVSXD: movsxd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX64rr8, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVUPDmr, X86_INS_MOVUPD: movupd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVUPDrm, X86_INS_MOVUPD: movupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVUPDrr, X86_INS_MOVUPD: movupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVUPDrr_REV, X86_INS_MOVUPD: movupd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVUPSmr, X86_INS_MOVUPS: movups */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MOVUPSrm, X86_INS_MOVUPS: movups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVUPSrr, X86_INS_MOVUPS: movups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVUPSrr_REV, X86_INS_MOVUPS: movups $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZPQILo2PQIrr, X86_INS_MOVQ: movq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX16rm16, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX16rm8, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX16rr16, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX16rr8, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX32rm16, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX32rm8, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX32rm8_NOREX, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX32rr16, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX32rr8, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX32rr8_NOREX, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX64rm16, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX64rm8, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX64rr16, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX64rr8, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MPSADBWrmi, X86_INS_MPSADBW: mpsadbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MPSADBWrri, X86_INS_MPSADBW: mpsadbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MUL16m, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL16r, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL32m, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL32r, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL64m, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL64r, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL8m, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL8r, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MULPDrm, X86_INS_MULPD: mulpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULPDrr, X86_INS_MULPD: mulpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULPSrm, X86_INS_MULPS: mulps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULPSrr, X86_INS_MULPS: mulps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULSDrm, X86_INS_MULSD: mulsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULSDrm_Int, X86_INS_MULSD: mulsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MULSDrr, X86_INS_MULSD: mulsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULSDrr_Int, X86_INS_MULSD: mulsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULSSrm, X86_INS_MULSS: mulss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULSSrm_Int, X86_INS_MULSS: mulss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MULSSrr, X86_INS_MULSS: mulss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULSSrr_Int, X86_INS_MULSS: mulss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULX32rm, X86_INS_MULX: mulx */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULX32rr, X86_INS_MULX: mulx */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULX64rm, X86_INS_MULX: mulx */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULX64rr, X86_INS_MULX: mulx */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MUL_F32m, X86_INS_FMUL: fmul */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL_F64m, X86_INS_FMUL: fmul */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL_FI16m, X86_INS_FIMUL: fimul */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL_FI32m, X86_INS_FIMUL: fimul */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL_FPrST0, X86_INS_FMULP: fmulp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL_FST0r, X86_INS_FMUL: fmul */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL_Fp32, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_Fp32m, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_Fp64, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_Fp64m, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_Fp64m32, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_Fp80, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_Fp80m32, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_Fp80m64, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_FpI16m32, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_FpI16m64, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_FpI16m80, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_FpI32m32, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_FpI32m64, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_FpI32m80, X86_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* X86_MUL_FrST0, X86_INS_FMUL: fmul */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_MWAITXrrr, X86_INS_MWAITX: mwaitx */ + 0, + { 0 } +}, + +{ /* X86_MWAITrr, X86_INS_MWAIT: mwait */ + 0, + { 0 } +}, + +{ /* X86_NEG16m, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG16r, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG32m, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG32r, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG64m, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG64r, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG8m, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG8r, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOOP, X86_INS_NOP: nop */ + 0, + { 0 } +}, + +{ /* X86_NOOP18_16m4, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16m5, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16m6, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16m7, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16r4, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16r5, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16r6, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16r7, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_m4, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_m5, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_m6, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_m7, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_r4, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_r5, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_r6, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_r7, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP19rr, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_NOOPL, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPL_19, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPL_1d, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPL_1e, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPLr, X86_INS_NOP: nop */ + 0, + { 0 } +}, + +{ /* X86_NOOPQ, X86_INS_NOP: nop */ + 0, + { 0 } +}, + +{ /* X86_NOOPQr, X86_INS_NOP: nop */ + 0, + { 0 } +}, + +{ /* X86_NOOPW, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPW_19, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPW_1c, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPW_1d, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPW_1e, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPWr, X86_INS_NOP: nop */ + 0, + { 0 } +}, + +{ /* X86_NOT16m, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT16r, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT32m, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT32r, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT64m, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT64r, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT8m, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT8r, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_OR16i16, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR16mi, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR16mi8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR16mr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR16ri, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR16ri8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR16rm, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR16rr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR16rr_REV, X86_INS_OR: or{w} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR32i32, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR32mi, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR32mi8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR32mr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR32ri, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR32ri8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR32rm, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR32rr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR32rr_REV, X86_INS_OR: or{l} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR64i32, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR64mi32, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR64mi8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR64mr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR64ri32, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR64ri8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR64rm, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR64rr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR64rr_REV, X86_INS_OR: or{q} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR8i8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR8mi, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR8mi8, X86_INS_OR: or{b} $dst $src */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR8mr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR8ri, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR8ri8, X86_INS_OR: or{b} $src1 $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR8rm, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR8rr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR8rr_REV, X86_INS_OR: or{b} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ORPDrm, X86_INS_ORPD: orpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ORPDrr, X86_INS_ORPD: orpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ORPSrm, X86_INS_ORPS: orps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ORPSrr, X86_INS_ORPS: orps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OUT16ir, X86_INS_OUT: out */ + 0, + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_OUT16rr, X86_INS_OUT: out */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_OUT32ir, X86_INS_OUT: out */ + 0, + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_OUT32rr, X86_INS_OUT: out */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_OUT8ir, X86_INS_OUT: out */ + 0, + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_OUT8rr, X86_INS_OUT: out */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_OUTSB, X86_INS_OUTSB: outsb */ + X86_EFLAGS_TEST_DF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OUTSL, X86_INS_OUTSD: outsd */ + X86_EFLAGS_TEST_DF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_OUTSW, X86_INS_OUTSW: outsw */ + X86_EFLAGS_TEST_DF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PABSBrm, X86_INS_PABSB: pabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PABSBrr, X86_INS_PABSB: pabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PABSDrm, X86_INS_PABSD: pabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PABSDrr, X86_INS_PABSD: pabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PABSWrm, X86_INS_PABSW: pabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PABSWrr, X86_INS_PABSW: pabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PACKSSDWrm, X86_INS_PACKSSDW: packssdw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PACKSSDWrr, X86_INS_PACKSSDW: packssdw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PACKSSWBrm, X86_INS_PACKSSWB: packsswb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PACKSSWBrr, X86_INS_PACKSSWB: packsswb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PACKUSDWrm, X86_INS_PACKUSDW: packusdw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PACKUSDWrr, X86_INS_PACKUSDW: packusdw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PACKUSWBrm, X86_INS_PACKUSWB: packuswb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PACKUSWBrr, X86_INS_PACKUSWB: packuswb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDBrm, X86_INS_PADDB: paddb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDBrr, X86_INS_PADDB: paddb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDDrm, X86_INS_PADDD: paddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDDrr, X86_INS_PADDD: paddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDQrm, X86_INS_PADDQ: paddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDQrr, X86_INS_PADDQ: paddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDSBrm, X86_INS_PADDSB: paddsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDSBrr, X86_INS_PADDSB: paddsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDSWrm, X86_INS_PADDSW: paddsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDSWrr, X86_INS_PADDSW: paddsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDUSBrm, X86_INS_PADDUSB: paddusb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDUSBrr, X86_INS_PADDUSB: paddusb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDUSWrm, X86_INS_PADDUSW: paddusw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDUSWrr, X86_INS_PADDUSW: paddusw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDWrm, X86_INS_PADDW: paddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PADDWrr, X86_INS_PADDW: paddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PALIGNRrmi, X86_INS_PALIGNR: palignr */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PALIGNRrri, X86_INS_PALIGNR: palignr */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PANDNrm, X86_INS_PANDN: pandn */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PANDNrr, X86_INS_PANDN: pandn */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PANDrm, X86_INS_PAND: pand */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PANDrr, X86_INS_PAND: pand */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PAUSE, X86_INS_PAUSE: pause */ + 0, + { 0 } +}, + +{ /* X86_PAVGBrm, X86_INS_PAVGB: pavgb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PAVGBrr, X86_INS_PAVGB: pavgb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PAVGUSBrm, X86_INS_PAVGUSB: pavgusb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PAVGUSBrr, X86_INS_PAVGUSB: pavgusb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PAVGWrm, X86_INS_PAVGW: pavgw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PAVGWrr, X86_INS_PAVGW: pavgw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PBLENDVBrm0, X86_INS_PBLENDVB: pblendvb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PBLENDVBrr0, X86_INS_PBLENDVB: pblendvb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PBLENDWrmi, X86_INS_PBLENDW: pblendw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PBLENDWrri, X86_INS_PBLENDW: pblendw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PCLMULQDQrm, X86_INS_PCLMULQDQ: pclmulqdq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PCLMULQDQrr, X86_INS_PCLMULQDQ: pclmulqdq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PCMPEQBrm, X86_INS_PCMPEQB: pcmpeqb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPEQBrr, X86_INS_PCMPEQB: pcmpeqb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPEQDrm, X86_INS_PCMPEQD: pcmpeqd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPEQDrr, X86_INS_PCMPEQD: pcmpeqd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPEQQrm, X86_INS_PCMPEQQ: pcmpeqq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPEQQrr, X86_INS_PCMPEQQ: pcmpeqq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPEQWrm, X86_INS_PCMPEQW: pcmpeqw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPEQWrr, X86_INS_PCMPEQW: pcmpeqw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPESTRIrm, X86_INS_PCMPESTRI: pcmpestri */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PCMPESTRIrr, X86_INS_PCMPESTRI: pcmpestri */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PCMPESTRMrm, X86_INS_PCMPESTRM: pcmpestrm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPESTRMrr, X86_INS_PCMPESTRM: pcmpestrm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPGTBrm, X86_INS_PCMPGTB: pcmpgtb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPGTBrr, X86_INS_PCMPGTB: pcmpgtb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPGTDrm, X86_INS_PCMPGTD: pcmpgtd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPGTDrr, X86_INS_PCMPGTD: pcmpgtd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPGTQrm, X86_INS_PCMPGTQ: pcmpgtq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPGTQrr, X86_INS_PCMPGTQ: pcmpgtq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPGTWrm, X86_INS_PCMPGTW: pcmpgtw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPGTWrr, X86_INS_PCMPGTW: pcmpgtw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPISTRIrm, X86_INS_PCMPISTRI: pcmpistri */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PCMPISTRIrr, X86_INS_PCMPISTRI: pcmpistri */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PCMPISTRMrm, X86_INS_PCMPISTRM: pcmpistrm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PCMPISTRMrr, X86_INS_PCMPISTRM: pcmpistrm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PCONFIG, X86_INS_PCONFIG: pconfig */ + 0, + { 0 } +}, + +{ /* X86_PDEP32rm, X86_INS_PDEP: pdep */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PDEP32rr, X86_INS_PDEP: pdep */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PDEP64rm, X86_INS_PDEP: pdep */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PDEP64rr, X86_INS_PDEP: pdep */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PEXT32rm, X86_INS_PEXT: pext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PEXT32rr, X86_INS_PEXT: pext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PEXT64rm, X86_INS_PEXT: pext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PEXT64rr, X86_INS_PEXT: pext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PEXTRBmr, X86_INS_PEXTRB: pextrb */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PEXTRBrr, X86_INS_PEXTRB: pextrb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PEXTRDmr, X86_INS_PEXTRD: pextrd */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PEXTRDrr, X86_INS_PEXTRD: pextrd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PEXTRQmr, X86_INS_PEXTRQ: pextrq */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PEXTRQrr, X86_INS_PEXTRQ: pextrq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PEXTRWmr, X86_INS_PEXTRW: pextrw */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PEXTRWrr, X86_INS_PEXTRW: pextrw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PEXTRWrr_REV, X86_INS_PEXTRW: pextrw $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PF2IDrm, X86_INS_PF2ID: pf2id */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PF2IDrr, X86_INS_PF2ID: pf2id */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PF2IWrm, X86_INS_PF2IW: pf2iw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PF2IWrr, X86_INS_PF2IW: pf2iw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFACCrm, X86_INS_PFACC: pfacc */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFACCrr, X86_INS_PFACC: pfacc */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFADDrm, X86_INS_PFADD: pfadd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFADDrr, X86_INS_PFADD: pfadd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFCMPEQrm, X86_INS_PFCMPEQ: pfcmpeq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFCMPEQrr, X86_INS_PFCMPEQ: pfcmpeq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFCMPGErm, X86_INS_PFCMPGE: pfcmpge */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFCMPGErr, X86_INS_PFCMPGE: pfcmpge */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFCMPGTrm, X86_INS_PFCMPGT: pfcmpgt */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFCMPGTrr, X86_INS_PFCMPGT: pfcmpgt */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFMAXrm, X86_INS_PFMAX: pfmax */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFMAXrr, X86_INS_PFMAX: pfmax */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFMINrm, X86_INS_PFMIN: pfmin */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFMINrr, X86_INS_PFMIN: pfmin */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFMULrm, X86_INS_PFMUL: pfmul */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFMULrr, X86_INS_PFMUL: pfmul */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFNACCrm, X86_INS_PFNACC: pfnacc */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFNACCrr, X86_INS_PFNACC: pfnacc */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFPNACCrm, X86_INS_PFPNACC: pfpnacc */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFPNACCrr, X86_INS_PFPNACC: pfpnacc */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFRCPIT1rm, X86_INS_PFRCPIT1: pfrcpit1 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFRCPIT1rr, X86_INS_PFRCPIT1: pfrcpit1 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFRCPIT2rm, X86_INS_PFRCPIT2: pfrcpit2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFRCPIT2rr, X86_INS_PFRCPIT2: pfrcpit2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFRCPrm, X86_INS_PFRCP: pfrcp */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFRCPrr, X86_INS_PFRCP: pfrcp */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFRSQIT1rm, X86_INS_PFRSQIT1: pfrsqit1 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFRSQIT1rr, X86_INS_PFRSQIT1: pfrsqit1 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFRSQRTrm, X86_INS_PFRSQRT: pfrsqrt */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFRSQRTrr, X86_INS_PFRSQRT: pfrsqrt */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFSUBRrm, X86_INS_PFSUBR: pfsubr */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFSUBRrr, X86_INS_PFSUBR: pfsubr */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFSUBrm, X86_INS_PFSUB: pfsub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PFSUBrr, X86_INS_PFSUB: pfsub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHADDDrm, X86_INS_PHADDD: phaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHADDDrr, X86_INS_PHADDD: phaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHADDSWrm, X86_INS_PHADDSW: phaddsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHADDSWrr, X86_INS_PHADDSW: phaddsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHADDWrm, X86_INS_PHADDW: phaddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHADDWrr, X86_INS_PHADDW: phaddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHMINPOSUWrm, X86_INS_PHMINPOSUW: phminposuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHMINPOSUWrr, X86_INS_PHMINPOSUW: phminposuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHSUBDrm, X86_INS_PHSUBD: phsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHSUBDrr, X86_INS_PHSUBD: phsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHSUBSWrm, X86_INS_PHSUBSW: phsubsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHSUBSWrr, X86_INS_PHSUBSW: phsubsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHSUBWrm, X86_INS_PHSUBW: phsubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PHSUBWrr, X86_INS_PHSUBW: phsubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PI2FDrm, X86_INS_PI2FD: pi2fd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PI2FDrr, X86_INS_PI2FD: pi2fd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PI2FWrm, X86_INS_PI2FW: pi2fw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PI2FWrr, X86_INS_PI2FW: pi2fw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PINSRBrm, X86_INS_PINSRB: pinsrb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PINSRBrr, X86_INS_PINSRB: pinsrb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PINSRDrm, X86_INS_PINSRD: pinsrd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PINSRDrr, X86_INS_PINSRD: pinsrd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PINSRQrm, X86_INS_PINSRQ: pinsrq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PINSRQrr, X86_INS_PINSRQ: pinsrq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PINSRWrm, X86_INS_PINSRW: pinsrw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PINSRWrr, X86_INS_PINSRW: pinsrw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PMADDUBSWrm, X86_INS_PMADDUBSW: pmaddubsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMADDUBSWrr, X86_INS_PMADDUBSW: pmaddubsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMADDWDrm, X86_INS_PMADDWD: pmaddwd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMADDWDrr, X86_INS_PMADDWD: pmaddwd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMAXSBrm, X86_INS_PMAXSB: pmaxsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMAXSBrr, X86_INS_PMAXSB: pmaxsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMAXSDrm, X86_INS_PMAXSD: pmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMAXSDrr, X86_INS_PMAXSD: pmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMAXSWrm, X86_INS_PMAXSW: pmaxsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMAXSWrr, X86_INS_PMAXSW: pmaxsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMAXUBrm, X86_INS_PMAXUB: pmaxub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMAXUBrr, X86_INS_PMAXUB: pmaxub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMAXUDrm, X86_INS_PMAXUD: pmaxud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMAXUDrr, X86_INS_PMAXUD: pmaxud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMAXUWrm, X86_INS_PMAXUW: pmaxuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMAXUWrr, X86_INS_PMAXUW: pmaxuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMINSBrm, X86_INS_PMINSB: pminsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMINSBrr, X86_INS_PMINSB: pminsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMINSDrm, X86_INS_PMINSD: pminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMINSDrr, X86_INS_PMINSD: pminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMINSWrm, X86_INS_PMINSW: pminsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMINSWrr, X86_INS_PMINSW: pminsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMINUBrm, X86_INS_PMINUB: pminub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMINUBrr, X86_INS_PMINUB: pminub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMINUDrm, X86_INS_PMINUD: pminud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMINUDrr, X86_INS_PMINUD: pminud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMINUWrm, X86_INS_PMINUW: pminuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMINUWrr, X86_INS_PMINUW: pminuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVMSKBrr, X86_INS_PMOVMSKB: pmovmskb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVSXBDrm, X86_INS_PMOVSXBD: pmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVSXBDrr, X86_INS_PMOVSXBD: pmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVSXBQrm, X86_INS_PMOVSXBQ: pmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVSXBQrr, X86_INS_PMOVSXBQ: pmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVSXBWrm, X86_INS_PMOVSXBW: pmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVSXBWrr, X86_INS_PMOVSXBW: pmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVSXDQrm, X86_INS_PMOVSXDQ: pmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVSXDQrr, X86_INS_PMOVSXDQ: pmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVSXWDrm, X86_INS_PMOVSXWD: pmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVSXWDrr, X86_INS_PMOVSXWD: pmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVSXWQrm, X86_INS_PMOVSXWQ: pmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVSXWQrr, X86_INS_PMOVSXWQ: pmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVZXBDrm, X86_INS_PMOVZXBD: pmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVZXBDrr, X86_INS_PMOVZXBD: pmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVZXBQrm, X86_INS_PMOVZXBQ: pmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVZXBQrr, X86_INS_PMOVZXBQ: pmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVZXBWrm, X86_INS_PMOVZXBW: pmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVZXBWrr, X86_INS_PMOVZXBW: pmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVZXDQrm, X86_INS_PMOVZXDQ: pmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVZXDQrr, X86_INS_PMOVZXDQ: pmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVZXWDrm, X86_INS_PMOVZXWD: pmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVZXWDrr, X86_INS_PMOVZXWD: pmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVZXWQrm, X86_INS_PMOVZXWQ: pmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMOVZXWQrr, X86_INS_PMOVZXWQ: pmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULDQrm, X86_INS_PMULDQ: pmuldq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULDQrr, X86_INS_PMULDQ: pmuldq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULHRSWrm, X86_INS_PMULHRSW: pmulhrsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULHRSWrr, X86_INS_PMULHRSW: pmulhrsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULHRWrm, X86_INS_PMULHRW: pmulhrw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULHRWrr, X86_INS_PMULHRW: pmulhrw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULHUWrm, X86_INS_PMULHUW: pmulhuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULHUWrr, X86_INS_PMULHUW: pmulhuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULHWrm, X86_INS_PMULHW: pmulhw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULHWrr, X86_INS_PMULHW: pmulhw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULLDrm, X86_INS_PMULLD: pmulld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULLDrr, X86_INS_PMULLD: pmulld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULLWrm, X86_INS_PMULLW: pmullw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULLWrr, X86_INS_PMULLW: pmullw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULUDQrm, X86_INS_PMULUDQ: pmuludq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PMULUDQrr, X86_INS_PMULUDQ: pmuludq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_POP16r, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP16rmm, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP16rmr, X86_INS_POP: pop{w} $reg */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP32r, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP32rmm, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP32rmr, X86_INS_POP: pop{l} $reg */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP64r, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP64rmm, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP64rmr, X86_INS_POP: pop{q} $reg */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPA16, X86_INS_POPAW: popaw */ + 0, + { 0 } +}, + +{ /* X86_POPA32, X86_INS_POPAL: popal */ + 0, + { 0 } +}, + +{ /* X86_POPCNT16rm, X86_INS_POPCNT: popcnt */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_POPCNT16rr, X86_INS_POPCNT: popcnt */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_POPCNT32rm, X86_INS_POPCNT: popcnt */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_POPCNT32rr, X86_INS_POPCNT: popcnt */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_POPCNT64rm, X86_INS_POPCNT: popcnt */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_POPCNT64rr, X86_INS_POPCNT: popcnt */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_POPDS16, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPDS32, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPES16, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPES32, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPF16, X86_INS_POPF: popf */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_POPF32, X86_INS_POPFD: popfd */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_POPF64, X86_INS_POPFQ: popfq */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_POPFS16, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPFS32, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPFS64, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPGS16, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPGS32, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPGS64, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPSS16, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPSS32, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_PORrm, X86_INS_POR: por */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PORrr, X86_INS_POR: por */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PREFETCH, X86_INS_PREFETCH: prefetch */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PREFETCHNTA, X86_INS_PREFETCHNTA: prefetchnta */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PREFETCHT0, X86_INS_PREFETCHT0: prefetcht0 */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PREFETCHT1, X86_INS_PREFETCHT1: prefetcht1 */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PREFETCHT2, X86_INS_PREFETCHT2: prefetcht2 */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PREFETCHW, X86_INS_PREFETCHW: prefetchw */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { CS_AC_READ, 0 } +}, + +{ /* X86_PREFETCHWT1, X86_INS_PREFETCHWT1: prefetchwt1 */ + 0, + { 0 } +}, + +{ /* X86_PSADBWrm, X86_INS_PSADBW: psadbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSADBWrr, X86_INS_PSADBW: psadbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSHUFBrm, X86_INS_PSHUFB: pshufb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSHUFBrr, X86_INS_PSHUFB: pshufb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSHUFDmi, X86_INS_PSHUFD: pshufd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSHUFDri, X86_INS_PSHUFD: pshufd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSHUFHWmi, X86_INS_PSHUFHW: pshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSHUFHWri, X86_INS_PSHUFHW: pshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSHUFLWmi, X86_INS_PSHUFLW: pshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSHUFLWri, X86_INS_PSHUFLW: pshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSIGNBrm, X86_INS_PSIGNB: psignb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSIGNBrr, X86_INS_PSIGNB: psignb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSIGNDrm, X86_INS_PSIGND: psignd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSIGNDrr, X86_INS_PSIGND: psignd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSIGNWrm, X86_INS_PSIGNW: psignw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSIGNWrr, X86_INS_PSIGNW: psignw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSLLDQri, X86_INS_PSLLDQ: pslldq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSLLDri, X86_INS_PSLLD: pslld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSLLDrm, X86_INS_PSLLD: pslld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSLLDrr, X86_INS_PSLLD: pslld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSLLQri, X86_INS_PSLLQ: psllq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSLLQrm, X86_INS_PSLLQ: psllq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSLLQrr, X86_INS_PSLLQ: psllq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSLLWri, X86_INS_PSLLW: psllw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSLLWrm, X86_INS_PSLLW: psllw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSLLWrr, X86_INS_PSLLW: psllw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSRADri, X86_INS_PSRAD: psrad */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSRADrm, X86_INS_PSRAD: psrad */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSRADrr, X86_INS_PSRAD: psrad */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSRAWri, X86_INS_PSRAW: psraw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSRAWrm, X86_INS_PSRAW: psraw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSRAWrr, X86_INS_PSRAW: psraw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSRLDQri, X86_INS_PSRLDQ: psrldq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSRLDri, X86_INS_PSRLD: psrld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSRLDrm, X86_INS_PSRLD: psrld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSRLDrr, X86_INS_PSRLD: psrld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSRLQri, X86_INS_PSRLQ: psrlq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSRLQrm, X86_INS_PSRLQ: psrlq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSRLQrr, X86_INS_PSRLQ: psrlq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSRLWri, X86_INS_PSRLW: psrlw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PSRLWrm, X86_INS_PSRLW: psrlw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSRLWrr, X86_INS_PSRLW: psrlw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBBrm, X86_INS_PSUBB: psubb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBBrr, X86_INS_PSUBB: psubb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBDrm, X86_INS_PSUBD: psubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBDrr, X86_INS_PSUBD: psubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBQrm, X86_INS_PSUBQ: psubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBQrr, X86_INS_PSUBQ: psubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBSBrm, X86_INS_PSUBSB: psubsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBSBrr, X86_INS_PSUBSB: psubsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBSWrm, X86_INS_PSUBSW: psubsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBSWrr, X86_INS_PSUBSW: psubsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBUSBrm, X86_INS_PSUBUSB: psubusb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBUSBrr, X86_INS_PSUBUSB: psubusb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBUSWrm, X86_INS_PSUBUSW: psubusw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBUSWrr, X86_INS_PSUBUSW: psubusw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBWrm, X86_INS_PSUBW: psubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSUBWrr, X86_INS_PSUBW: psubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSWAPDrm, X86_INS_PSWAPD: pswapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PSWAPDrr, X86_INS_PSWAPD: pswapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PTESTrm, X86_INS_PTEST: ptest */ + X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PTESTrr, X86_INS_PTEST: ptest */ + X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PTWRITE64m, X86_INS_PTWRITE: ptwrite */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PTWRITE64r, X86_INS_PTWRITE: ptwrite */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PTWRITEm, X86_INS_PTWRITE: ptwrite */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PTWRITEr, X86_INS_PTWRITE: ptwrite */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKHBWrm, X86_INS_PUNPCKHBW: punpckhbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKHBWrr, X86_INS_PUNPCKHBW: punpckhbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKHDQrm, X86_INS_PUNPCKHDQ: punpckhdq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKHDQrr, X86_INS_PUNPCKHDQ: punpckhdq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKHQDQrm, X86_INS_PUNPCKHQDQ: punpckhqdq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKHQDQrr, X86_INS_PUNPCKHQDQ: punpckhqdq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKHWDrm, X86_INS_PUNPCKHWD: punpckhwd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKHWDrr, X86_INS_PUNPCKHWD: punpckhwd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKLBWrm, X86_INS_PUNPCKLBW: punpcklbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKLBWrr, X86_INS_PUNPCKLBW: punpcklbw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKLDQrm, X86_INS_PUNPCKLDQ: punpckldq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKLDQrr, X86_INS_PUNPCKLDQ: punpckldq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKLQDQrm, X86_INS_PUNPCKLQDQ: punpcklqdq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKLQDQrr, X86_INS_PUNPCKLQDQ: punpcklqdq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKLWDrm, X86_INS_PUNPCKLWD: punpcklwd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUNPCKLWDrr, X86_INS_PUNPCKLWD: punpcklwd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PUSH16i8, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSH16r, X86_INS_PUSH: push */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH16rmm, X86_INS_PUSH: push */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH16rmr, X86_INS_PUSH: push{w} $reg */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH32i8, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSH32r, X86_INS_PUSH: push */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH32rmm, X86_INS_PUSH: push */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH32rmr, X86_INS_PUSH: push{l} $reg */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH64i32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSH64i8, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSH64r, X86_INS_PUSH: push */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH64rmm, X86_INS_PUSH: push */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH64rmr, X86_INS_PUSH: push{q} $reg */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSHA16, X86_INS_PUSHAW: pushaw */ + 0, + { 0 } +}, + +{ /* X86_PUSHA32, X86_INS_PUSHAL: pushal */ + 0, + { 0 } +}, + +{ /* X86_PUSHCS16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHCS32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHDS16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHDS32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHES16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHES32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHF16, X86_INS_PUSHF: pushf */ + 0, + { 0 } +}, + +{ /* X86_PUSHF32, X86_INS_PUSHFD: pushfd */ + 0, + { 0 } +}, + +{ /* X86_PUSHF64, X86_INS_PUSHFQ: pushfq */ + 0, + { 0 } +}, + +{ /* X86_PUSHFS16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHFS32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHFS64, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHGS16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHGS32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHGS64, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHSS16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHSS32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHi16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHi32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PXORrm, X86_INS_PXOR: pxor */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_PXORrr, X86_INS_PXOR: pxor */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCL16m1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL16mCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCL16mi, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL16r1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL16rCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCL16ri, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL32m1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL32mCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCL32mi, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL32r1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL32rCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCL32ri, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL64m1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL64mCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCL64mi, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL64r1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL64rCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCL64ri, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL8m1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL8mCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCL8mi, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL8r1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL8rCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCL8ri, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCPPSm, X86_INS_RCPPS: rcpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCPPSr, X86_INS_RCPPS: rcpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCPSSm, X86_INS_RCPSS: rcpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCPSSm_Int, X86_INS_RCPSS: rcpss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCPSSr, X86_INS_RCPSS: rcpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCPSSr_Int, X86_INS_RCPSS: rcpss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCR16m1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR16mCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCR16mi, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR16r1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR16rCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCR16ri, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR32m1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR32mCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCR32mi, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR32r1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR32rCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCR32ri, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR64m1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR64mCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCR64mi, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR64r1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR64rCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCR64ri, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR8m1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR8mCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCR8mi, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR8r1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR8rCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCR8ri, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RDFSBASE, X86_INS_RDFSBASE: rdfsbase */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDFSBASE64, X86_INS_RDFSBASE: rdfsbase */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDGSBASE, X86_INS_RDGSBASE: rdgsbase */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDGSBASE64, X86_INS_RDGSBASE: rdgsbase */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDMSR, X86_INS_RDMSR: rdmsr */ + 0, + { 0 } +}, + +{ /* X86_RDPID32, X86_INS_RDPID: rdpid */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDPID64, X86_INS_RDPID: rdpid */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDPKRUr, X86_INS_RDPKRU: rdpkru */ + 0, + { 0 } +}, + +{ /* X86_RDPMC, X86_INS_RDPMC: rdpmc */ + 0, + { 0 } +}, + +{ /* X86_RDRAND16r, X86_INS_RDRAND: rdrand */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDRAND32r, X86_INS_RDRAND: rdrand */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDRAND64r, X86_INS_RDRAND: rdrand */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDSEED16r, X86_INS_RDSEED: rdseed */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDSEED32r, X86_INS_RDSEED: rdseed */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDSEED64r, X86_INS_RDSEED: rdseed */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDSSPD, X86_INS_RDSSPD: rdsspd */ + 0, + { 0 } +}, + +{ /* X86_RDSSPQ, X86_INS_RDSSPQ: rdsspq */ + 0, + { 0 } +}, + +{ /* X86_RDTSC, X86_INS_RDTSC: rdtsc */ + 0, + { 0 } +}, + +{ /* X86_RDTSCP, X86_INS_RDTSCP: rdtscp */ + 0, + { 0 } +}, + +{ /* X86_REPNE_PREFIX, X86_INS_REPNE: repne */ + 0, + { 0 } +}, + +{ /* X86_REP_PREFIX, X86_INS_REP: rep */ + 0, + { 0 } +}, + +{ /* X86_RETIL, X86_INS_RET: ret */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_RETIQ, X86_INS_RET: ret */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_RETIW, X86_INS_RET: ret */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_RETL, X86_INS_RET: ret */ + 0, + { 0 } +}, + +{ /* X86_RETQ, X86_INS_RET: ret */ + 0, + { 0 } +}, + +{ /* X86_RETW, X86_INS_RET: ret */ + 0, + { 0 } +}, + +{ /* X86_REX64_PREFIX, X86_INS_REX64: rex64 */ + 0, + { 0 } +}, + +{ /* X86_ROL16m1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL16mCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROL16mi, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL16r1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL16rCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROL16ri, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL32m1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL32mCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROL32mi, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL32r1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL32rCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROL32ri, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL64m1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL64mCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROL64mi, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL64r1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL64rCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROL64ri, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL8m1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL8mCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROL8mi, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL8r1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL8rCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROL8ri, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR16m1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR16mCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROR16mi, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR16r1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR16rCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROR16ri, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR32m1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR32mCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROR32mi, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR32r1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR32rCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROR32ri, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR64m1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR64mCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROR64mi, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR64r1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR64rCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROR64ri, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR8m1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR8mCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROR8mi, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR8r1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR8rCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROR8ri, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RORX32mi, X86_INS_RORX: rorx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RORX32ri, X86_INS_RORX: rorx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RORX64mi, X86_INS_RORX: rorx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RORX64ri, X86_INS_RORX: rorx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROUNDPDm, X86_INS_ROUNDPD: roundpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROUNDPDr, X86_INS_ROUNDPD: roundpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROUNDPSm, X86_INS_ROUNDPS: roundps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROUNDPSr, X86_INS_ROUNDPS: roundps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROUNDSDm, X86_INS_ROUNDSD: roundsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROUNDSDm_Int, X86_INS_ROUNDSD: roundsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROUNDSDr, X86_INS_ROUNDSD: roundsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROUNDSDr_Int, X86_INS_ROUNDSD: roundsd $dst $src2 $src3 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROUNDSSm, X86_INS_ROUNDSS: roundss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROUNDSSm_Int, X86_INS_ROUNDSS: roundss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROUNDSSr, X86_INS_ROUNDSS: roundss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROUNDSSr_Int, X86_INS_ROUNDSS: roundss $dst $src2 $src3 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RSM, X86_INS_RSM: rsm */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_RSQRTPSm, X86_INS_RSQRTPS: rsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RSQRTPSr, X86_INS_RSQRTPS: rsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RSQRTSSm, X86_INS_RSQRTSS: rsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RSQRTSSm_Int, X86_INS_RSQRTSS: rsqrtss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RSQRTSSr, X86_INS_RSQRTSS: rsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RSQRTSSr_Int, X86_INS_RSQRTSS: rsqrtss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RSTORSSP, X86_INS_RSTORSSP: rstorssp */ + 0, + { 0 } +}, + +{ /* X86_SAHF, X86_INS_SAHF: sahf */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { 0 } +}, + +{ /* X86_SAL16m1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL16mCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL16mi, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL16r1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL16rCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL16ri, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL32m1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL32mCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL32mi, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL32r1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL32rCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL32ri, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL64m1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL64mCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL64mi, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL64r1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL64rCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL64ri, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL8m1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL8mCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL8mi, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL8r1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL8rCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL8ri, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SALC, X86_INS_SALC: salc */ + 0, + { 0 } +}, + +{ /* X86_SAR16m1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR16mCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR16mi, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR16r1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR16rCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR16ri, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR32m1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR32mCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR32mi, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR32r1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR32rCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR32ri, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR64m1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR64mCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR64mi, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR64r1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR64rCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR64ri, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR8m1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR8mCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR8mi, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR8r1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR8rCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR8ri, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SARX32rm, X86_INS_SARX: sarx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SARX32rr, X86_INS_SARX: sarx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SARX64rm, X86_INS_SARX: sarx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SARX64rr, X86_INS_SARX: sarx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SAVEPREVSSP, X86_INS_SAVEPREVSSP: saveprevssp */ + 0, + { 0 } +}, + +{ /* X86_SBB16i16, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB16mi, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB16mi8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB16mr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB16ri, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB16ri8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB16rm, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB16rr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB16rr_REV, X86_INS_SBB: sbb{w} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB32i32, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB32mi, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB32mi8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB32mr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB32ri, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB32ri8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB32rm, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB32rr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB32rr_REV, X86_INS_SBB: sbb{l} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB64i32, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB64mi32, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB64mi8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB64mr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB64ri32, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB64ri8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB64rm, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB64rr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB64rr_REV, X86_INS_SBB: sbb{q} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB8i8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB8mi, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB8mi8, X86_INS_SBB: sbb{b} $dst $src */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB8mr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB8ri, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB8ri8, X86_INS_SBB: sbb{b} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB8rm, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB8rr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB8rr_REV, X86_INS_SBB: sbb{b} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SCASB, X86_INS_SCASB: scasb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SCASL, X86_INS_SCASD: scasd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SCASQ, X86_INS_SCASQ: scasq */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SCASW, X86_INS_SCASW: scasw */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SETAEm, X86_INS_SETAE: setae */ + X86_EFLAGS_TEST_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETAEr, X86_INS_SETAE: setae */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETAm, X86_INS_SETA: seta */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETAr, X86_INS_SETA: seta */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETBEm, X86_INS_SETBE: setbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETBEr, X86_INS_SETBE: setbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETBm, X86_INS_SETB: setb */ + X86_EFLAGS_TEST_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETBr, X86_INS_SETB: setb */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETEm, X86_INS_SETE: sete */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETEr, X86_INS_SETE: sete */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETGEm, X86_INS_SETGE: setge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETGEr, X86_INS_SETGE: setge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETGm, X86_INS_SETG: setg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETGr, X86_INS_SETG: setg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETLEm, X86_INS_SETLE: setle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETLEr, X86_INS_SETLE: setle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETLm, X86_INS_SETL: setl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETLr, X86_INS_SETL: setl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETNEm, X86_INS_SETNE: setne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETNEr, X86_INS_SETNE: setne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETNOm, X86_INS_SETNO: setno */ + X86_EFLAGS_TEST_OF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETNOr, X86_INS_SETNO: setno */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETNPm, X86_INS_SETNP: setnp */ + X86_EFLAGS_TEST_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETNPr, X86_INS_SETNP: setnp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETNSm, X86_INS_SETNS: setns */ + X86_EFLAGS_TEST_SF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETNSr, X86_INS_SETNS: setns */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETOm, X86_INS_SETO: seto */ + X86_EFLAGS_TEST_OF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETOr, X86_INS_SETO: seto */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETPm, X86_INS_SETP: setp */ + X86_EFLAGS_TEST_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETPr, X86_INS_SETP: setp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETSSBSY, X86_INS_SETSSBSY: setssbsy */ + 0, + { 0 } +}, + +{ /* X86_SETSm, X86_INS_SETS: sets */ + X86_EFLAGS_TEST_SF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETSr, X86_INS_SETS: sets */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SFENCE, X86_INS_SFENCE: sfence */ + 0, + { 0 } +}, + +{ /* X86_SGDT16m, X86_INS_SGDT: sgdt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SGDT32m, X86_INS_SGDT: sgdt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SGDT64m, X86_INS_SGDT: sgdt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SHA1MSG1rm, X86_INS_SHA1MSG1: sha1msg1 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHA1MSG1rr, X86_INS_SHA1MSG1: sha1msg1 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHA1MSG2rm, X86_INS_SHA1MSG2: sha1msg2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHA1MSG2rr, X86_INS_SHA1MSG2: sha1msg2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHA1NEXTErm, X86_INS_SHA1NEXTE: sha1nexte */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHA1NEXTErr, X86_INS_SHA1NEXTE: sha1nexte */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHA1RNDS4rmi, X86_INS_SHA1RNDS4: sha1rnds4 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHA1RNDS4rri, X86_INS_SHA1RNDS4: sha1rnds4 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHA256MSG1rm, X86_INS_SHA256MSG1: sha256msg1 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHA256MSG1rr, X86_INS_SHA256MSG1: sha256msg1 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHA256MSG2rm, X86_INS_SHA256MSG2: sha256msg2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHA256MSG2rr, X86_INS_SHA256MSG2: sha256msg2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHA256RNDS2rm, X86_INS_SHA256RNDS2: sha256rnds2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHA256RNDS2rr, X86_INS_SHA256RNDS2: sha256rnds2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL16m1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL16mCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL16mi, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL16r1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL16rCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL16ri, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL32m1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL32mCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL32mi, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL32r1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL32rCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL32ri, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL64m1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL64mCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL64mi, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL64r1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL64rCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL64ri, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL8m1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL8mCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL8mi, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL8r1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL8rCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL8ri, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLD16mrCL, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLD16mri8, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLD16rrCL, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLD16rri8, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLD32mrCL, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLD32mri8, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLD32rrCL, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLD32rri8, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLD64mrCL, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLD64mri8, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLD64rrCL, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLD64rri8, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLX32rm, X86_INS_SHLX: shlx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLX32rr, X86_INS_SHLX: shlx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLX64rm, X86_INS_SHLX: shlx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLX64rr, X86_INS_SHLX: shlx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHR16m1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR16mCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR16mi, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR16r1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR16rCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR16ri, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR32m1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR32mCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR32mi, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR32r1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR32rCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR32ri, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR64m1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR64mCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR64mi, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR64r1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR64rCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR64ri, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR8m1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR8mCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR8mi, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR8r1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR8rCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR8ri, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRD16mrCL, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRD16mri8, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRD16rrCL, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRD16rri8, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRD32mrCL, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRD32mri8, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRD32rrCL, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRD32rri8, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRD64mrCL, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRD64mri8, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRD64rrCL, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRD64rri8, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRX32rm, X86_INS_SHRX: shrx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRX32rr, X86_INS_SHRX: shrx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRX64rm, X86_INS_SHRX: shrx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRX64rr, X86_INS_SHRX: shrx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHUFPDrmi, X86_INS_SHUFPD: shufpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHUFPDrri, X86_INS_SHUFPD: shufpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHUFPSrmi, X86_INS_SHUFPS: shufps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHUFPSrri, X86_INS_SHUFPS: shufps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SIDT16m, X86_INS_SIDT: sidt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SIDT32m, X86_INS_SIDT: sidt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SIDT64m, X86_INS_SIDT: sidt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SIN_F, X86_INS_FSIN: fsin */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_SIN_Fp32, X86_INS_FSIN: fsin */ + 0, + { 0 } +}, + +{ /* X86_SIN_Fp64, X86_INS_FSIN: fsin */ + 0, + { 0 } +}, + +{ /* X86_SIN_Fp80, X86_INS_FSIN: fsin */ + 0, + { 0 } +}, + +{ /* X86_SKINIT, X86_INS_SKINIT: skinit */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_SLDT16m, X86_INS_SLDT: sldt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SLDT16r, X86_INS_SLDT: sldt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SLDT32r, X86_INS_SLDT: sldt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SLDT64r, X86_INS_SLDT: sldt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SLWPCB, X86_INS_SLWPCB: slwpcb */ + 0, + { 0 } +}, + +{ /* X86_SLWPCB64, X86_INS_SLWPCB: slwpcb */ + 0, + { 0 } +}, + +{ /* X86_SMSW16m, X86_INS_SMSW: smsw */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SMSW16r, X86_INS_SMSW: smsw */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SMSW32r, X86_INS_SMSW: smsw */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SMSW64r, X86_INS_SMSW: smsw */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SQRTPDm, X86_INS_SQRTPD: sqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SQRTPDr, X86_INS_SQRTPD: sqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SQRTPSm, X86_INS_SQRTPS: sqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SQRTPSr, X86_INS_SQRTPS: sqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SQRTSDm, X86_INS_SQRTSD: sqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SQRTSDm_Int, X86_INS_SQRTSD: sqrtsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SQRTSDr, X86_INS_SQRTSD: sqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SQRTSDr_Int, X86_INS_SQRTSD: sqrtsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SQRTSSm, X86_INS_SQRTSS: sqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SQRTSSm_Int, X86_INS_SQRTSS: sqrtss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SQRTSSr, X86_INS_SQRTSS: sqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SQRTSSr_Int, X86_INS_SQRTSS: sqrtss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SQRT_F, X86_INS_FSQRT: fsqrt */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_SQRT_Fp32, X86_INS_FSQRT: fsqrt */ + 0, + { 0 } +}, + +{ /* X86_SQRT_Fp64, X86_INS_FSQRT: fsqrt */ + 0, + { 0 } +}, + +{ /* X86_SQRT_Fp80, X86_INS_FSQRT: fsqrt */ + 0, + { 0 } +}, + +{ /* X86_STAC, X86_INS_STAC: stac */ + 0, + { 0 } +}, + +{ /* X86_STC, X86_INS_STC: stc */ + X86_EFLAGS_SET_CF, + { 0 } +}, + +{ /* X86_STD, X86_INS_STD: std */ + X86_EFLAGS_SET_DF, + { 0 } +}, + +{ /* X86_STGI, X86_INS_STGI: stgi */ + 0, + { 0 } +}, + +{ /* X86_STI, X86_INS_STI: sti */ + X86_EFLAGS_SET_IF, + { 0 } +}, + +{ /* X86_STMXCSR, X86_INS_STMXCSR: stmxcsr */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_STOSB, X86_INS_STOSB: stosb */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_STOSL, X86_INS_STOSD: stosd */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_STOSQ, X86_INS_STOSQ: stosq */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_STOSW, X86_INS_STOSW: stosw */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_STR16r, X86_INS_STR: str */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_STR32r, X86_INS_STR: str */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_STR64r, X86_INS_STR: str */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_STRm, X86_INS_STR: str */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_F32m, X86_INS_FST: fst */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ST_F64m, X86_INS_FST: fst */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ST_FP32m, X86_INS_FSTP: fstp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ST_FP64m, X86_INS_FSTP: fstp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_ST_FP80m, X86_INS_FSTP: fstp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_FPrr, X86_INS_FSTP: fstp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_Fp32m, X86_INS_FST: fst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_Fp64m, X86_INS_FST: fst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_Fp64m32, X86_INS_FST: fst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_Fp80m32, X86_INS_FST: fst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_Fp80m64, X86_INS_FST: fst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_FpP32m, X86_INS_FST: fst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_FpP64m, X86_INS_FST: fst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_FpP64m32, X86_INS_FST: fst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_FpP80m, X86_INS_FST: fst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_FpP80m32, X86_INS_FST: fst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_FpP80m64, X86_INS_FST: fst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_ST_Frr, X86_INS_FST: fst */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUB16i16, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB16mi, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB16mi8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB16mr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB16ri, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB16ri8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB16rm, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB16rr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB16rr_REV, X86_INS_SUB: sub{w} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB32i32, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB32mi, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB32mi8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB32mr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB32ri, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB32ri8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB32rm, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB32rr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB32rr_REV, X86_INS_SUB: sub{l} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB64i32, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB64mi32, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB64mi8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB64mr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB64ri32, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB64ri8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB64rm, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB64rr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB64rr_REV, X86_INS_SUB: sub{q} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB8i8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB8mi, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB8mi8, X86_INS_SUB: sub{b} $dst $src */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB8mr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB8ri, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB8ri8, X86_INS_SUB: sub{b} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB8rm, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB8rr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB8rr_REV, X86_INS_SUB: sub{b} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUBPDrm, X86_INS_SUBPD: subpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUBPDrr, X86_INS_SUBPD: subpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUBPSrm, X86_INS_SUBPS: subps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUBPSrr, X86_INS_SUBPS: subps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUBR_F32m, X86_INS_FSUBR: fsubr */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUBR_F64m, X86_INS_FSUBR: fsubr */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUBR_FI16m, X86_INS_FISUBR: fisubr */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUBR_FI32m, X86_INS_FISUBR: fisubr */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUBR_FPrST0, X86_INS_FSUBRP: fsubrp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUBR_FST0r, X86_INS_FSUBR: fsubr */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUBR_Fp32m, X86_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* X86_SUBR_Fp64m, X86_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* X86_SUBR_Fp64m32, X86_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* X86_SUBR_Fp80m32, X86_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* X86_SUBR_Fp80m64, X86_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* X86_SUBR_FpI16m32, X86_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* X86_SUBR_FpI16m64, X86_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* X86_SUBR_FpI16m80, X86_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* X86_SUBR_FpI32m32, X86_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* X86_SUBR_FpI32m64, X86_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* X86_SUBR_FpI32m80, X86_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* X86_SUBR_FrST0, X86_INS_FSUBR: fsubr */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SUBSDrm, X86_INS_SUBSD: subsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUBSDrm_Int, X86_INS_SUBSD: subsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUBSDrr, X86_INS_SUBSD: subsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUBSDrr_Int, X86_INS_SUBSD: subsd $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUBSSrm, X86_INS_SUBSS: subss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUBSSrm_Int, X86_INS_SUBSS: subss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUBSSrr, X86_INS_SUBSS: subss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUBSSrr_Int, X86_INS_SUBSS: subss $dst $src2 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB_F32m, X86_INS_FSUB: fsub */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUB_F64m, X86_INS_FSUB: fsub */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUB_FI16m, X86_INS_FISUB: fisub */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUB_FI32m, X86_INS_FISUB: fisub */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUB_FPrST0, X86_INS_FSUBP: fsubp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUB_FST0r, X86_INS_FSUB: fsub */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_SUB_Fp32, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_Fp32m, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_Fp64, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_Fp64m, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_Fp64m32, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_Fp80, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_Fp80m32, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_Fp80m64, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_FpI16m32, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_FpI16m64, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_FpI16m80, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_FpI32m32, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_FpI32m64, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_FpI32m80, X86_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* X86_SUB_FrST0, X86_INS_FSUB: fsub */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SWAPGS, X86_INS_SWAPGS: swapgs */ + 0, + { 0 } +}, + +{ /* X86_SYSCALL, X86_INS_SYSCALL: syscall */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_SYSENTER, X86_INS_SYSENTER: sysenter */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_SYSEXIT, X86_INS_SYSEXIT: sysexit */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_SYSEXIT64, X86_INS_SYSEXITQ: sysexitq */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_SYSRET, X86_INS_SYSRET: sysret */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_SYSRET64, X86_INS_SYSRETQ: sysretq */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_T1MSKC32rm, X86_INS_T1MSKC: t1mskc */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_T1MSKC32rr, X86_INS_T1MSKC: t1mskc */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_T1MSKC64rm, X86_INS_T1MSKC: t1mskc */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_T1MSKC64rr, X86_INS_T1MSKC: t1mskc */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TEST16i16, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST16mi, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST16mi_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST16mr, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST16ri, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST16ri_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST16rr, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_TEST32i32, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST32mi, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST32mi_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST32mr, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST32ri, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST32ri_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST32rr, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_TEST64i32, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST64mi32, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST64mi32_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST64mr, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_TEST64ri32, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST64ri32_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST64rr, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_TEST8i8, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST8mi, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST8mi_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST8mr, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST8ri, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST8ri_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST8rr, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_TPAUSE, X86_INS_TPAUSE: tpause */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_TST_F, X86_INS_FTST: ftst */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { 0 } +}, + +{ /* X86_TST_Fp32, X86_INS_FTST: ftst */ + 0, + { 0 } +}, + +{ /* X86_TST_Fp64, X86_INS_FTST: ftst */ + 0, + { 0 } +}, + +{ /* X86_TST_Fp80, X86_INS_FTST: ftst */ + 0, + { 0 } +}, + +{ /* X86_TZCNT16rm, X86_INS_TZCNT: tzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZCNT16rr, X86_INS_TZCNT: tzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZCNT32rm, X86_INS_TZCNT: tzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZCNT32rr, X86_INS_TZCNT: tzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZCNT64rm, X86_INS_TZCNT: tzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZCNT64rr, X86_INS_TZCNT: tzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZMSK32rm, X86_INS_TZMSK: tzmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZMSK32rr, X86_INS_TZMSK: tzmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZMSK64rm, X86_INS_TZMSK: tzmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZMSK64rr, X86_INS_TZMSK: tzmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_UCOMISDrm, X86_INS_UCOMISD: ucomisd */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_UCOMISDrm_Int, X86_INS_UCOMISD: ucomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_UCOMISDrr, X86_INS_UCOMISD: ucomisd */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_UCOMISDrr_Int, X86_INS_UCOMISD: ucomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_UCOMISSrm, X86_INS_UCOMISS: ucomiss */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_UCOMISSrm_Int, X86_INS_UCOMISS: ucomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_UCOMISSrr, X86_INS_UCOMISS: ucomiss */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_UCOMISSrr_Int, X86_INS_UCOMISS: ucomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_UCOM_FIPr, X86_INS_FUCOMPI: fucompi */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_UCOM_FIr, X86_INS_FUCOMI: fucomi */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_UCOM_FPPr, X86_INS_FUCOMPP: fucompp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { 0 } +}, + +{ /* X86_UCOM_FPr, X86_INS_FUCOMP: fucomp */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_UCOM_FpIr32, X86_INS_FUCOMP: fucomp */ + 0, + { 0 } +}, + +{ /* X86_UCOM_FpIr64, X86_INS_FUCOMP: fucomp */ + 0, + { 0 } +}, + +{ /* X86_UCOM_FpIr80, X86_INS_FUCOMP: fucomp */ + 0, + { 0 } +}, + +{ /* X86_UCOM_Fpr32, X86_INS_FUCOMP: fucomp */ + 0, + { 0 } +}, + +{ /* X86_UCOM_Fpr64, X86_INS_FUCOMP: fucomp */ + 0, + { 0 } +}, + +{ /* X86_UCOM_Fpr80, X86_INS_FUCOMP: fucomp */ + 0, + { 0 } +}, + +{ /* X86_UCOM_Fr, X86_INS_FUCOM: fucom */ + X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_UD0, X86_INS_UD0: ud0 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_UD1, X86_INS_UD1: ud1 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_UD2, X86_INS_UD2: ud2 */ + 0, + { 0 } +}, + +{ /* X86_UMONITOR16, X86_INS_UMONITOR: umonitor */ + 0, + { 0 } +}, + +{ /* X86_UMONITOR32, X86_INS_UMONITOR: umonitor */ + 0, + { 0 } +}, + +{ /* X86_UMONITOR64, X86_INS_UMONITOR: umonitor */ + 0, + { 0 } +}, + +{ /* X86_UMWAIT, X86_INS_UMWAIT: umwait */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_UNPCKHPDrm, X86_INS_UNPCKHPD: unpckhpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_UNPCKHPDrr, X86_INS_UNPCKHPD: unpckhpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_UNPCKHPSrm, X86_INS_UNPCKHPS: unpckhps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_UNPCKHPSrr, X86_INS_UNPCKHPS: unpckhps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_UNPCKLPDrm, X86_INS_UNPCKLPD: unpcklpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_UNPCKLPDrr, X86_INS_UNPCKLPD: unpcklpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_UNPCKLPSrm, X86_INS_UNPCKLPS: unpcklps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_UNPCKLPSrr, X86_INS_UNPCKLPS: unpcklps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_V4FMADDPSrm, X86_INS_V4FMADDPS: v4fmaddps */ + 0, + { 0 } +}, + +{ /* X86_V4FMADDPSrmk, X86_INS_V4FMADDPS: v4fmaddps */ + 0, + { 0 } +}, + +{ /* X86_V4FMADDPSrmkz, X86_INS_V4FMADDPS: v4fmaddps */ + 0, + { 0 } +}, + +{ /* X86_V4FMADDSSrm, X86_INS_V4FMADDSS: v4fmaddss */ + 0, + { 0 } +}, + +{ /* X86_V4FMADDSSrmk, X86_INS_V4FMADDSS: v4fmaddss */ + 0, + { 0 } +}, + +{ /* X86_V4FMADDSSrmkz, X86_INS_V4FMADDSS: v4fmaddss */ + 0, + { 0 } +}, + +{ /* X86_V4FNMADDPSrm, X86_INS_V4FNMADDPS: v4fnmaddps */ + 0, + { 0 } +}, + +{ /* X86_V4FNMADDPSrmk, X86_INS_V4FNMADDPS: v4fnmaddps */ + 0, + { 0 } +}, + +{ /* X86_V4FNMADDPSrmkz, X86_INS_V4FNMADDPS: v4fnmaddps */ + 0, + { 0 } +}, + +{ /* X86_V4FNMADDSSrm, X86_INS_V4FNMADDSS: v4fnmaddss */ + 0, + { 0 } +}, + +{ /* X86_V4FNMADDSSrmk, X86_INS_V4FNMADDSS: v4fnmaddss */ + 0, + { 0 } +}, + +{ /* X86_V4FNMADDSSrmkz, X86_INS_V4FNMADDSS: v4fnmaddss */ + 0, + { 0 } +}, + +{ /* X86_VADDPDYrm, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDYrr, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ128rm, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ128rmb, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ128rmbk, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ128rmbkz, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ128rmk, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ128rmkz, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ128rr, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ128rrk, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ128rrkz, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ256rm, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ256rmb, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ256rmbk, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ256rmbkz, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ256rmk, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ256rmkz, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ256rr, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ256rrk, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZ256rrkz, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZrm, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZrmb, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZrmbk, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZrmbkz, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZrmk, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZrmkz, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZrr, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZrrb, X86_INS_VADDPD: vaddpd */ + 0, + { 0 } +}, + +{ /* X86_VADDPDZrrbk, X86_INS_VADDPD: vaddpd */ + 0, + { 0 } +}, + +{ /* X86_VADDPDZrrbkz, X86_INS_VADDPD: vaddpd */ + 0, + { 0 } +}, + +{ /* X86_VADDPDZrrk, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDZrrkz, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDrm, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPDrr, X86_INS_VADDPD: vaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSYrm, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSYrr, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ128rm, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ128rmb, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ128rmbk, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ128rmbkz, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ128rmk, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ128rmkz, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ128rr, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ128rrk, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ128rrkz, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ256rm, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ256rmb, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ256rmbk, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ256rmbkz, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ256rmk, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ256rmkz, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ256rr, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ256rrk, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZ256rrkz, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZrm, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZrmb, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZrmbk, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZrmbkz, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZrmk, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZrmkz, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZrr, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZrrb, X86_INS_VADDPS: vaddps */ + 0, + { 0 } +}, + +{ /* X86_VADDPSZrrbk, X86_INS_VADDPS: vaddps */ + 0, + { 0 } +}, + +{ /* X86_VADDPSZrrbkz, X86_INS_VADDPS: vaddps */ + 0, + { 0 } +}, + +{ /* X86_VADDPSZrrk, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSZrrkz, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSrm, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDPSrr, X86_INS_VADDPS: vaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDZrm, X86_INS_VADDSD: vaddsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDZrm_Int, X86_INS_VADDSD: vaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDZrm_Intk, X86_INS_VADDSD: vaddsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDZrm_Intkz, X86_INS_VADDSD: vaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDZrr, X86_INS_VADDSD: vaddsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDZrr_Int, X86_INS_VADDSD: vaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDZrr_Intk, X86_INS_VADDSD: vaddsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDZrr_Intkz, X86_INS_VADDSD: vaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDZrrb_Int, X86_INS_VADDSD: vaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDZrrb_Intk, X86_INS_VADDSD: vaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDZrrb_Intkz, X86_INS_VADDSD: vaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDrm, X86_INS_VADDSD: vaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDrm_Int, X86_INS_VADDSD: vaddsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VADDSDrr, X86_INS_VADDSD: vaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSDrr_Int, X86_INS_VADDSD: vaddsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSZrm, X86_INS_VADDSS: vaddss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSZrm_Int, X86_INS_VADDSS: vaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSZrm_Intk, X86_INS_VADDSS: vaddss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSZrm_Intkz, X86_INS_VADDSS: vaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSZrr, X86_INS_VADDSS: vaddss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSZrr_Int, X86_INS_VADDSS: vaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSZrr_Intk, X86_INS_VADDSS: vaddss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSZrr_Intkz, X86_INS_VADDSS: vaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSZrrb_Int, X86_INS_VADDSS: vaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSZrrb_Intk, X86_INS_VADDSS: vaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSZrrb_Intkz, X86_INS_VADDSS: vaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSrm, X86_INS_VADDSS: vaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSrm_Int, X86_INS_VADDSS: vaddss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VADDSSrr, X86_INS_VADDSS: vaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSSrr_Int, X86_INS_VADDSS: vaddss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSUBPDYrm, X86_INS_VADDSUBPD: vaddsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSUBPDYrr, X86_INS_VADDSUBPD: vaddsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSUBPDrm, X86_INS_VADDSUBPD: vaddsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSUBPDrr, X86_INS_VADDSUBPD: vaddsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSUBPSYrm, X86_INS_VADDSUBPS: vaddsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSUBPSYrr, X86_INS_VADDSUBPS: vaddsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSUBPSrm, X86_INS_VADDSUBPS: vaddsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VADDSUBPSrr, X86_INS_VADDSUBPS: vaddsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECLASTYrm, X86_INS_VAESDECLAST: vaesdeclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECLASTYrr, X86_INS_VAESDECLAST: vaesdeclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECLASTZ128rm, X86_INS_VAESDECLAST: vaesdeclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECLASTZ128rr, X86_INS_VAESDECLAST: vaesdeclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECLASTZ256rm, X86_INS_VAESDECLAST: vaesdeclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECLASTZ256rr, X86_INS_VAESDECLAST: vaesdeclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECLASTZrm, X86_INS_VAESDECLAST: vaesdeclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECLASTZrr, X86_INS_VAESDECLAST: vaesdeclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECLASTrm, X86_INS_VAESDECLAST: vaesdeclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECLASTrr, X86_INS_VAESDECLAST: vaesdeclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECYrm, X86_INS_VAESDEC: vaesdec */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECYrr, X86_INS_VAESDEC: vaesdec */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECZ128rm, X86_INS_VAESDEC: vaesdec */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECZ128rr, X86_INS_VAESDEC: vaesdec */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECZ256rm, X86_INS_VAESDEC: vaesdec */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECZ256rr, X86_INS_VAESDEC: vaesdec */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECZrm, X86_INS_VAESDEC: vaesdec */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECZrr, X86_INS_VAESDEC: vaesdec */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECrm, X86_INS_VAESDEC: vaesdec */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESDECrr, X86_INS_VAESDEC: vaesdec */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCLASTYrm, X86_INS_VAESENCLAST: vaesenclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCLASTYrr, X86_INS_VAESENCLAST: vaesenclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCLASTZ128rm, X86_INS_VAESENCLAST: vaesenclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCLASTZ128rr, X86_INS_VAESENCLAST: vaesenclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCLASTZ256rm, X86_INS_VAESENCLAST: vaesenclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCLASTZ256rr, X86_INS_VAESENCLAST: vaesenclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCLASTZrm, X86_INS_VAESENCLAST: vaesenclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCLASTZrr, X86_INS_VAESENCLAST: vaesenclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCLASTrm, X86_INS_VAESENCLAST: vaesenclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCLASTrr, X86_INS_VAESENCLAST: vaesenclast */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCYrm, X86_INS_VAESENC: vaesenc */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCYrr, X86_INS_VAESENC: vaesenc */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCZ128rm, X86_INS_VAESENC: vaesenc */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCZ128rr, X86_INS_VAESENC: vaesenc */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCZ256rm, X86_INS_VAESENC: vaesenc */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCZ256rr, X86_INS_VAESENC: vaesenc */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCZrm, X86_INS_VAESENC: vaesenc */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCZrr, X86_INS_VAESENC: vaesenc */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCrm, X86_INS_VAESENC: vaesenc */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESENCrr, X86_INS_VAESENC: vaesenc */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VAESIMCrm, X86_INS_VAESIMC: vaesimc */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VAESIMCrr, X86_INS_VAESIMC: vaesimc */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VAESKEYGENASSIST128rm, X86_INS_VAESKEYGENASSIST: vaeskeygenassist */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VAESKEYGENASSIST128rr, X86_INS_VAESKEYGENASSIST: vaeskeygenassist */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNDZ128rmbi, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ128rmbik, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ128rmbikz, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ128rmi, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ128rmik, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ128rmikz, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ128rri, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ128rrik, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ128rrikz, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ256rmbi, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ256rmbik, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ256rmbikz, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ256rmi, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ256rmik, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ256rmikz, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ256rri, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ256rrik, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZ256rrikz, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZrmbi, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZrmbik, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZrmbikz, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZrmi, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZrmik, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZrmikz, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZrri, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZrrik, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNDZrrikz, X86_INS_VALIGND: valignd */ + 0, + { 0 } +}, + +{ /* X86_VALIGNQZ128rmbi, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ128rmbik, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ128rmbikz, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ128rmi, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ128rmik, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ128rmikz, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ128rri, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ128rrik, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ128rrikz, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ256rmbi, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ256rmbik, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ256rmbikz, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ256rmi, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ256rmik, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ256rmikz, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ256rri, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ256rrik, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZ256rrikz, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZrmbi, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZrmbik, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZrmbikz, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZrmi, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZrmik, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZrmikz, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZrri, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZrrik, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VALIGNQZrrikz, X86_INS_VALIGNQ: valignq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VANDNPDYrm, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDYrr, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ128rm, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ128rmb, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ128rmbk, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ128rmbkz, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ128rmk, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ128rmkz, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ128rr, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ128rrk, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ128rrkz, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ256rm, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ256rmb, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ256rmbk, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ256rmbkz, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ256rmk, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ256rmkz, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ256rr, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ256rrk, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZ256rrkz, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZrm, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZrmb, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZrmbk, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZrmbkz, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZrmk, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZrmkz, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZrr, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZrrk, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDZrrkz, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDrm, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPDrr, X86_INS_VANDNPD: vandnpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSYrm, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSYrr, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ128rm, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ128rmb, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ128rmbk, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ128rmbkz, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ128rmk, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ128rmkz, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ128rr, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ128rrk, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ128rrkz, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ256rm, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ256rmb, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ256rmbk, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ256rmbkz, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ256rmk, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ256rmkz, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ256rr, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ256rrk, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZ256rrkz, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZrm, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZrmb, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZrmbk, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZrmbkz, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZrmk, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZrmkz, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZrr, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZrrk, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSZrrkz, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSrm, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDNPSrr, X86_INS_VANDNPS: vandnps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDYrm, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDYrr, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ128rm, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ128rmb, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ128rmbk, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ128rmbkz, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ128rmk, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ128rmkz, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ128rr, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ128rrk, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ128rrkz, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ256rm, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ256rmb, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ256rmbk, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ256rmbkz, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ256rmk, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ256rmkz, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ256rr, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ256rrk, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZ256rrkz, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZrm, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZrmb, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZrmbk, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZrmbkz, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZrmk, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZrmkz, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZrr, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZrrk, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDZrrkz, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDrm, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPDrr, X86_INS_VANDPD: vandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSYrm, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSYrr, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ128rm, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ128rmb, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ128rmbk, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ128rmbkz, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ128rmk, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ128rmkz, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ128rr, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ128rrk, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ128rrkz, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ256rm, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ256rmb, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ256rmbk, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ256rmbkz, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ256rmk, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ256rmkz, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ256rr, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ256rrk, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZ256rrkz, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZrm, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZrmb, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZrmbk, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZrmbkz, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZrmk, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZrmkz, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZrr, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZrrk, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSZrrkz, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSrm, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VANDPSrr, X86_INS_VANDPS: vandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ128rm, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ128rmb, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ128rmbk, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ128rmbkz, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { 0 } +}, + +{ /* X86_VBLENDMPDZ128rmk, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ128rmkz, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ128rr, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ128rrk, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ128rrkz, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ256rm, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ256rmb, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ256rmbk, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ256rmbkz, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { 0 } +}, + +{ /* X86_VBLENDMPDZ256rmk, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ256rmkz, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ256rr, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ256rrk, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZ256rrkz, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZrm, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZrmb, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZrmbk, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZrmbkz, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { 0 } +}, + +{ /* X86_VBLENDMPDZrmk, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZrmkz, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZrr, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZrrk, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPDZrrkz, X86_INS_VBLENDMPD: vblendmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ128rm, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ128rmb, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ128rmbk, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ128rmbkz, X86_INS_VBLENDMPS: vblendmps */ + 0, + { 0 } +}, + +{ /* X86_VBLENDMPSZ128rmk, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ128rmkz, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ128rr, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ128rrk, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ128rrkz, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ256rm, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ256rmb, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ256rmbk, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ256rmbkz, X86_INS_VBLENDMPS: vblendmps */ + 0, + { 0 } +}, + +{ /* X86_VBLENDMPSZ256rmk, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ256rmkz, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ256rr, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ256rrk, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZ256rrkz, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZrm, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZrmb, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZrmbk, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZrmbkz, X86_INS_VBLENDMPS: vblendmps */ + 0, + { 0 } +}, + +{ /* X86_VBLENDMPSZrmk, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZrmkz, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZrr, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZrrk, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDMPSZrrkz, X86_INS_VBLENDMPS: vblendmps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDPDYrmi, X86_INS_VBLENDPD: vblendpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VBLENDPDYrri, X86_INS_VBLENDPD: vblendpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VBLENDPDrmi, X86_INS_VBLENDPD: vblendpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VBLENDPDrri, X86_INS_VBLENDPD: vblendpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VBLENDPSYrmi, X86_INS_VBLENDPS: vblendps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VBLENDPSYrri, X86_INS_VBLENDPS: vblendps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VBLENDPSrmi, X86_INS_VBLENDPS: vblendps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VBLENDPSrri, X86_INS_VBLENDPS: vblendps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VBLENDVPDYrm, X86_INS_VBLENDVPD: vblendvpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDVPDYrr, X86_INS_VBLENDVPD: vblendvpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDVPDrm, X86_INS_VBLENDVPD: vblendvpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDVPDrr, X86_INS_VBLENDVPD: vblendvpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDVPSYrm, X86_INS_VBLENDVPS: vblendvps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDVPSYrr, X86_INS_VBLENDVPS: vblendvps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDVPSrm, X86_INS_VBLENDVPS: vblendvps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBLENDVPSrr, X86_INS_VBLENDVPS: vblendvps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF128, X86_INS_VBROADCASTF128: vbroadcastf128 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X2Z256m, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X2Z256mk, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X2Z256mkz, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X2Z256r, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X2Z256rk, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X2Z256rkz, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X2Zm, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X2Zmk, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X2Zmkz, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X2Zr, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X2Zrk, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X2Zrkz, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF32X4Z256rm, X86_INS_VBROADCASTF32X4: vbroadcastf32x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTF32X4Z256rmk, X86_INS_VBROADCASTF32X4: vbroadcastf32x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTF32X4Z256rmkz, X86_INS_VBROADCASTF32X4: vbroadcastf32x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTF32X4rm, X86_INS_VBROADCASTF32X4: vbroadcastf32x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTF32X4rmk, X86_INS_VBROADCASTF32X4: vbroadcastf32x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTF32X4rmkz, X86_INS_VBROADCASTF32X4: vbroadcastf32x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTF32X8rm, X86_INS_VBROADCASTF32X8: vbroadcastf32x8 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTF32X8rmk, X86_INS_VBROADCASTF32X8: vbroadcastf32x8 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTF32X8rmkz, X86_INS_VBROADCASTF32X8: vbroadcastf32x8 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTF64X2Z128rm, X86_INS_VBROADCASTF64X2: vbroadcastf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF64X2Z128rmk, X86_INS_VBROADCASTF64X2: vbroadcastf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF64X2Z128rmkz, X86_INS_VBROADCASTF64X2: vbroadcastf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF64X2rm, X86_INS_VBROADCASTF64X2: vbroadcastf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF64X2rmk, X86_INS_VBROADCASTF64X2: vbroadcastf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF64X2rmkz, X86_INS_VBROADCASTF64X2: vbroadcastf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTF64X4rm, X86_INS_VBROADCASTF64X4: vbroadcastf64x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTF64X4rmk, X86_INS_VBROADCASTF64X4: vbroadcastf64x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTF64X4rmkz, X86_INS_VBROADCASTF64X4: vbroadcastf64x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTI128, X86_INS_VBROADCASTI128: vbroadcasti128 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTI32X2Z128m, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Z128mk, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Z128mkz, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Z128r, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Z128rk, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Z128rkz, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Z256m, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Z256mk, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Z256mkz, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Z256r, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Z256rk, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Z256rkz, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Zm, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Zmk, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Zmkz, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Zr, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Zrk, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X2Zrkz, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X4Z256rm, X86_INS_VBROADCASTI32X4: vbroadcasti32x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTI32X4Z256rmk, X86_INS_VBROADCASTI32X4: vbroadcasti32x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTI32X4Z256rmkz, X86_INS_VBROADCASTI32X4: vbroadcasti32x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTI32X4rm, X86_INS_VBROADCASTI32X4: vbroadcasti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI32X4rmk, X86_INS_VBROADCASTI32X4: vbroadcasti32x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTI32X4rmkz, X86_INS_VBROADCASTI32X4: vbroadcasti32x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTI32X8rm, X86_INS_VBROADCASTI32X8: vbroadcasti32x8 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTI32X8rmk, X86_INS_VBROADCASTI32X8: vbroadcasti32x8 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTI32X8rmkz, X86_INS_VBROADCASTI32X8: vbroadcasti32x8 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTI64X2Z128rm, X86_INS_VBROADCASTI64X2: vbroadcasti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI64X2Z128rmk, X86_INS_VBROADCASTI64X2: vbroadcasti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI64X2Z128rmkz, X86_INS_VBROADCASTI64X2: vbroadcasti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI64X2rm, X86_INS_VBROADCASTI64X2: vbroadcasti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI64X2rmk, X86_INS_VBROADCASTI64X2: vbroadcasti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI64X2rmkz, X86_INS_VBROADCASTI64X2: vbroadcasti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI64X4rm, X86_INS_VBROADCASTI64X4: vbroadcasti64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTI64X4rmk, X86_INS_VBROADCASTI64X4: vbroadcasti64x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTI64X4rmkz, X86_INS_VBROADCASTI64X4: vbroadcasti64x4 */ + 0, + { 0 } +}, + +{ /* X86_VBROADCASTSDYrm, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDYrr, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDZ256m, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDZ256mk, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDZ256mkz, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDZ256r, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDZ256rk, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDZ256rkz, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDZm, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDZmk, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDZmkz, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDZr, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDZrk, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSDZrkz, X86_INS_VBROADCASTSD: vbroadcastsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSYrm, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSYrr, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZ128m, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZ128mk, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZ128mkz, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZ128r, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZ128rk, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZ128rkz, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZ256m, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZ256mk, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZ256mkz, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZ256r, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZ256rk, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZ256rkz, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZm, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZmk, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZmkz, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZr, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZrk, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSZrkz, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSrm, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VBROADCASTSSrr, X86_INS_VBROADCASTSS: vbroadcastss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPDYrmi, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPDYrmi_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPDYrri, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPDYrri_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPDZ128rmbi, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ128rmbi_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ128rmbi_altk, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ128rmbik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ128rmi, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ128rmi_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ128rmi_altk, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ128rmik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ128rri, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ128rri_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ128rri_altk, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ128rrik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ256rmbi, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ256rmbi_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ256rmbi_altk, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ256rmbik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ256rmi, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ256rmi_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ256rmi_altk, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ256rmik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ256rri, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ256rri_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ256rri_altk, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZ256rrik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZrmbi, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZrmbi_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZrmbi_altk, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZrmbik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZrmi, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPDZrmi_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPDZrmi_altk, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZrmik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZrri, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPDZrri_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPDZrri_altk, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZrrib, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPDZrrib_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPDZrrib_altk, X86_INS_VCMPPD: vcmppd */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZrribk, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDZrrik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPDrmi, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPDrmi_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPDrri, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPDrri_alt, X86_INS_VCMPPD: vcmppd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPSYrmi, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPSYrmi_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPSYrri, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPSYrri_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPSZ128rmbi, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ128rmbi_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ128rmbi_altk, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ128rmbik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ128rmi, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ128rmi_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ128rmi_altk, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ128rmik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ128rri, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ128rri_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ128rri_altk, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ128rrik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ256rmbi, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ256rmbi_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ256rmbi_altk, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ256rmbik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ256rmi, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ256rmi_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ256rmi_altk, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ256rmik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ256rri, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ256rri_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ256rri_altk, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZ256rrik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZrmbi, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZrmbi_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZrmbi_altk, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZrmbik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZrmi, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPSZrmi_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPSZrmi_altk, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZrmik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZrri, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPSZrri_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPSZrri_altk, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZrrib, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPSZrrib_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPSZrrib_altk, X86_INS_VCMPPS: vcmpps */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZrribk, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSZrrik, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPPSrmi, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPSrmi_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPPSrri, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPPSrri_alt, X86_INS_VCMPPS: vcmpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPSDZrm, X86_INS_VCMPSD: vcmp${cc}sd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPSDZrm_Int, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSDZrm_Intk, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSDZrmi_alt, X86_INS_VCMPSD: vcmpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPSDZrmi_altk, X86_INS_VCMPSD: vcmpsd */ + 0, + { 0 } +}, + +{ /* X86_VCMPSDZrr, X86_INS_VCMPSD: vcmp${cc}sd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPSDZrr_Int, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSDZrr_Intk, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSDZrrb_Int, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSDZrrb_Intk, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSDZrrb_alt, X86_INS_VCMPSD: vcmpsd */ + 0, + { 0 } +}, + +{ /* X86_VCMPSDZrrb_altk, X86_INS_VCMPSD: vcmpsd */ + 0, + { 0 } +}, + +{ /* X86_VCMPSDZrri_alt, X86_INS_VCMPSD: vcmpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPSDZrri_altk, X86_INS_VCMPSD: vcmpsd */ + 0, + { 0 } +}, + +{ /* X86_VCMPSDrm, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPSDrm_Int, X86_INS_VCMPSD: vcmpsd */ + 0, + { 0 } +}, + +{ /* X86_VCMPSDrm_alt, X86_INS_VCMPSD: vcmpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPSDrr, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPSDrr_Int, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSDrr_alt, X86_INS_VCMPSD: vcmpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPSSZrm, X86_INS_VCMPSS: vcmp${cc}ss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPSSZrm_Int, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSSZrm_Intk, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSSZrmi_alt, X86_INS_VCMPSS: vcmpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPSSZrmi_altk, X86_INS_VCMPSS: vcmpss */ + 0, + { 0 } +}, + +{ /* X86_VCMPSSZrr, X86_INS_VCMPSS: vcmp${cc}ss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPSSZrr_Int, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPSSZrr_Intk, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSSZrrb_Int, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSSZrrb_Intk, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSSZrrb_alt, X86_INS_VCMPSS: vcmpss */ + 0, + { 0 } +}, + +{ /* X86_VCMPSSZrrb_altk, X86_INS_VCMPSS: vcmpss */ + 0, + { 0 } +}, + +{ /* X86_VCMPSSZrri_alt, X86_INS_VCMPSS: vcmpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPSSZrri_altk, X86_INS_VCMPSS: vcmpss */ + 0, + { 0 } +}, + +{ /* X86_VCMPSSrm, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPSSrm_Int, X86_INS_VCMPSS: vcmpss */ + 0, + { 0 } +}, + +{ /* X86_VCMPSSrm_alt, X86_INS_VCMPSS: vcmpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCMPSSrr, X86_INS_VCMP: vcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCMPSSrr_Int, X86_INS_VCMP: vcmp */ + 0, + { 0 } +}, + +{ /* X86_VCMPSSrr_alt, X86_INS_VCMPSS: vcmpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCOMISDZrm, X86_INS_VCOMISD: vcomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISDZrm_Int, X86_INS_VCOMISD: vcomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISDZrr, X86_INS_VCOMISD: vcomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISDZrr_Int, X86_INS_VCOMISD: vcomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISDZrrb, X86_INS_VCOMISD: vcomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISDrm, X86_INS_VCOMISD: vcomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISDrm_Int, X86_INS_VCOMISD: vcomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISDrr, X86_INS_VCOMISD: vcomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISDrr_Int, X86_INS_VCOMISD: vcomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISSZrm, X86_INS_VCOMISS: vcomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISSZrm_Int, X86_INS_VCOMISS: vcomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISSZrr, X86_INS_VCOMISS: vcomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISSZrr_Int, X86_INS_VCOMISS: vcomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISSZrrb, X86_INS_VCOMISS: vcomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISSrm, X86_INS_VCOMISS: vcomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISSrm_Int, X86_INS_VCOMISS: vcomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISSrr, X86_INS_VCOMISS: vcomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMISSrr_Int, X86_INS_VCOMISS: vcomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZ128mr, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZ128mrk, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZ128rr, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZ128rrk, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZ128rrkz, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZ256mr, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZ256mrk, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZ256rr, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZ256rrk, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZ256rrkz, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZmr, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZmrk, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZrr, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZrrk, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPDZrrkz, X86_INS_VCOMPRESSPD: vcompresspd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZ128mr, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZ128mrk, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZ128rr, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZ128rrk, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZ128rrkz, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZ256mr, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZ256mrk, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZ256rr, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZ256rrk, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZ256rrkz, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZmr, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZmrk, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZrr, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZrrk, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCOMPRESSPSZrrkz, X86_INS_VCOMPRESSPS: vcompressps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PDYrm, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PDYrr, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PDZ128rm, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ128rmb, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ128rmbk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ128rmbkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ128rmk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ128rmkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ128rr, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ128rrk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ128rrkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ256rm, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ256rmb, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ256rmbk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ256rmbkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ256rmk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ256rmkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ256rr, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ256rrk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZ256rrkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZrm, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PDZrmb, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZrmbk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZrmbkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZrmk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZrmkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZrr, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PDZrrk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDZrrkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTDQ2PDrm, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PDrr, X86_INS_VCVTDQ2PD: vcvtdq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSYrm, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSYrr, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ128rm, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ128rmb, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ128rmbk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ128rmbkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ128rmk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ128rmkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ128rr, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ128rrk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ128rrkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ256rm, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ256rmb, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ256rmbk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ256rmbkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ256rmk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ256rmkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ256rr, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ256rrk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZ256rrkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZrm, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZrmb, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZrmbk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZrmbkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZrmk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZrmkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZrr, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZrrb, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTDQ2PSZrrbk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZrrbkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZrrk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSZrrkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSrm, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTDQ2PSrr, X86_INS_VCVTDQ2PS: vcvtdq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQYrm, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQYrr, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ128rm, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ128rmb, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ128rmbk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ128rmbkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ128rmk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ128rmkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ128rr, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ128rrk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ128rrkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ256rm, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ256rmb, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ256rmbk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ256rmbkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ256rmk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ256rmkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ256rr, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ256rrk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZ256rrkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZrm, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZrmb, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZrmbk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZrmbkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZrmk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZrmkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZrr, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZrrb, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTPD2DQZrrbk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZrrbkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZrrk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQZrrkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQrm, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2DQrr, X86_INS_VCVTPD2DQ: vcvtpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2PSYrm, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2PSYrr, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2PSZ128rm, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ128rmb, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ128rmbk, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ128rmbkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ128rmk, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ128rmkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ128rr, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ128rrk, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ128rrkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ256rm, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ256rmb, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ256rmbk, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ256rmbkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ256rmk, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ256rmkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ256rr, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ256rrk, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZ256rrkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZrm, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2PSZrmb, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZrmbk, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZrmbkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZrmk, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZrmkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZrr, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2PSZrrb, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTPD2PSZrrbk, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZrrbkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZrrk, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSZrrkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSrm, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { 0 } +}, + +{ /* X86_VCVTPD2PSrr, X86_INS_VCVTPD2PS: vcvtpd2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ128rm, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ128rmb, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ128rmbk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ128rmbkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ128rmk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ128rmkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ128rr, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ128rrk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ128rrkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ256rm, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ256rmb, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ256rmbk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ256rmbkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ256rmk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ256rmkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ256rr, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ256rrk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZ256rrkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZrm, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZrmb, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZrmbk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZrmbkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZrmk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZrmkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZrr, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZrrb, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZrrbk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZrrbkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZrrk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2QQZrrkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ128rm, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ128rmb, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ128rmbk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ128rmbkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ128rmk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ128rmkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ128rr, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ128rrk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ128rrkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ256rm, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ256rmb, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ256rmbk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ256rmbkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ256rmk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ256rmkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ256rr, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ256rrk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZ256rrkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZrm, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZrmb, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZrmbk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZrmbkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZrmk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZrmkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZrr, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZrrb, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTPD2UDQZrrbk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZrrbkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZrrk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UDQZrrkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ128rm, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ128rmb, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ128rmbk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ128rmbkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ128rmk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ128rmkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ128rr, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ128rrk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ128rrkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ256rm, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ256rmb, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ256rmbk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ256rmbkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ256rmk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ256rmkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ256rr, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ256rrk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZ256rrkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZrm, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZrmb, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZrmbk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZrmbkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZrmk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZrmkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZrr, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZrrb, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZrrbk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZrrbkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZrrk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPD2UQQZrrkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSYrm, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSYrr, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZ128rm, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZ128rmk, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZ128rmkz, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZ128rr, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZ128rrk, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZ128rrkz, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZ256rm, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZ256rmk, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZ256rmkz, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZ256rr, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZ256rrk, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZ256rrkz, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZrm, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZrmk, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZrmkz, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZrr, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZrrb, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZrrbk, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZrrbkz, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZrrk, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSZrrkz, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSrm, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPH2PSrr, X86_INS_VCVTPH2PS: vcvtph2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQYrm, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQYrr, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ128rm, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ128rmb, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ128rmbk, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ128rmbkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ128rmk, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ128rmkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ128rr, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ128rrk, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ128rrkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ256rm, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ256rmb, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ256rmbk, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ256rmbkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ256rmk, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ256rmkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ256rr, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ256rrk, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZ256rrkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZrm, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZrmb, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZrmbk, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZrmbkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZrmk, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZrmkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZrr, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZrrb, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTPS2DQZrrbk, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZrrbkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZrrk, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQZrrkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQrm, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2DQrr, X86_INS_VCVTPS2DQ: vcvtps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PDYrm, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PDYrr, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PDZ128rm, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ128rmb, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ128rmbk, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ128rmbkz, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ128rmk, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ128rmkz, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ128rr, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ128rrk, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ128rrkz, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ256rm, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ256rmb, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ256rmbk, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ256rmbkz, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ256rmk, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ256rmkz, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ256rr, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ256rrk, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZ256rrkz, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZrm, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PDZrmb, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZrmbk, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZrmbkz, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZrmk, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZrmkz, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZrr, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PDZrrb, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZrrbk, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZrrbkz, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZrrk, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDZrrkz, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTPS2PDrm, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PDrr, X86_INS_VCVTPS2PD: vcvtps2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHYmr, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTPS2PHYrr, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTPS2PHZ128mr, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZ128mrk, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZ128rr, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZ128rrk, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZ128rrkz, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZ256mr, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZ256mrk, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZ256rr, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZ256rrk, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZ256rrkz, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZmr, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTPS2PHZmrk, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZrr, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTPS2PHZrrb, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZrrbk, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZrrbkz, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZrrk, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHZrrkz, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2PHmr, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTPS2PHrr, X86_INS_VCVTPS2PH: vcvtps2ph */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTPS2QQZ128rm, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ128rmb, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ128rmbk, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ128rmbkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ128rmk, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ128rmkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ128rr, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ128rrk, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ128rrkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ256rm, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ256rmb, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ256rmbk, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ256rmbkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ256rmk, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ256rmkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ256rr, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ256rrk, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZ256rrkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZrm, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZrmb, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZrmbk, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZrmbkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZrmk, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZrmkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZrr, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZrrb, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZrrbk, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZrrbkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZrrk, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2QQZrrkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ128rm, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ128rmb, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ128rmbk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ128rmbkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ128rmk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ128rmkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ128rr, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ128rrk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ128rrkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ256rm, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ256rmb, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ256rmbk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ256rmbkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ256rmk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ256rmkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ256rr, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ256rrk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZ256rrkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZrm, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZrmb, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZrmbk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZrmbkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZrmk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZrmkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZrr, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZrrb, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTPS2UDQZrrbk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZrrbkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZrrk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UDQZrrkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ128rm, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ128rmb, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ128rmbk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ128rmbkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ128rmk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ128rmkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ128rr, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ128rrk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ128rrkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ256rm, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ256rmb, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ256rmbk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ256rmbkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ256rmk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ256rmkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ256rr, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ256rrk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZ256rrkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZrm, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZrmb, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZrmbk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZrmbkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZrmk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZrmkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZrr, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZrrb, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZrrbk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZrrbkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZrrk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTPS2UQQZrrkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ128rm, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ128rmb, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ128rmbk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ128rmbkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ128rmk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ128rmkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ128rr, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ128rrk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ128rrkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ256rm, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ256rmb, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ256rmbk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ256rmbkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ256rmk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ256rmkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ256rr, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ256rrk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZ256rrkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZrm, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZrmb, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZrmbk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZrmbkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZrmk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZrmkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZrr, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZrrb, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZrrbk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZrrbkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZrrk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PDZrrkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ128rm, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ128rmb, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ128rmbk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ128rmbkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ128rmk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ128rmkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ128rr, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ128rrk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ128rrkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ256rm, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ256rmb, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ256rmbk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ256rmbkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ256rmk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ256rmkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ256rr, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ256rrk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZ256rrkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZrm, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZrmb, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZrmbk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZrmbkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZrmk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZrmkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZrr, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZrrb, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZrrbk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZrrbkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZrrk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTQQ2PSZrrkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SI64Zrm_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SI64Zrr_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SI64Zrrb_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SI64rm_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SI64rr_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SIZrm_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SIZrr_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SIZrrb_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SIrm_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SIrr_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSZrm, X86_INS_VCVTSD2SS: vcvtsd2ss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSZrm_Int, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSZrm_Intk, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSZrm_Intkz, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSZrr, X86_INS_VCVTSD2SS: vcvtsd2ss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSZrr_Int, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSZrr_Intk, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSZrr_Intkz, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSZrrb_Int, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSZrrb_Intk, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSZrrb_Intkz, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSrm, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSrm_Int, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSrr, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2SSrr_Int, X86_INS_VCVTSD2SS: vcvtsd2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2USI64Zrm_Int, X86_INS_VCVTSD2USI: vcvtsd2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2USI64Zrr_Int, X86_INS_VCVTSD2USI: vcvtsd2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2USI64Zrrb_Int, X86_INS_VCVTSD2USI: vcvtsd2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2USIZrm_Int, X86_INS_VCVTSD2USI: vcvtsd2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2USIZrr_Int, X86_INS_VCVTSD2USI: vcvtsd2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSD2USIZrrb_Int, X86_INS_VCVTSD2USI: vcvtsd2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SDZrm, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SDZrm_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SDZrr, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SDZrr_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SDZrrb_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SDrm, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SDrm_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SDrr, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SDrr_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SSZrm, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SSZrm_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SSZrr, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SSZrr_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SSZrrb_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SSrm, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SSrm_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SSrr, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI2SSrr_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SDZrm, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SDZrm_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SDZrr, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SDZrr_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SDZrrb_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SDrm, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SDrm_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SDrr, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SDrr_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SSZrm, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SSZrm_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SSZrr, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SSZrr_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SSZrrb_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SSrm, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SSrm_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SSrr, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSI642SSrr_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDZrm, X86_INS_VCVTSS2SD: vcvtss2sd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDZrm_Int, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDZrm_Intk, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDZrm_Intkz, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDZrr, X86_INS_VCVTSS2SD: vcvtss2sd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDZrr_Int, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDZrr_Intk, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDZrr_Intkz, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDZrrb_Int, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDZrrb_Intk, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDZrrb_Intkz, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDrm, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDrm_Int, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDrr, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SDrr_Int, X86_INS_VCVTSS2SD: vcvtss2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SI64Zrm_Int, X86_INS_VCVTSS2SI: vcvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SI64Zrr_Int, X86_INS_VCVTSS2SI: vcvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SI64Zrrb_Int, X86_INS_VCVTSS2SI: vcvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SI64rm_Int, X86_INS_VCVTSS2SI: vcvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SI64rr_Int, X86_INS_VCVTSS2SI: vcvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SIZrm_Int, X86_INS_VCVTSS2SI: vcvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SIZrr_Int, X86_INS_VCVTSS2SI: vcvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SIZrrb_Int, X86_INS_VCVTSS2SI: vcvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SIrm_Int, X86_INS_VCVTSS2SI: vcvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2SIrr_Int, X86_INS_VCVTSS2SI: vcvtss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2USI64Zrm_Int, X86_INS_VCVTSS2USI: vcvtss2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2USI64Zrr_Int, X86_INS_VCVTSS2USI: vcvtss2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2USI64Zrrb_Int, X86_INS_VCVTSS2USI: vcvtss2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2USIZrm_Int, X86_INS_VCVTSS2USI: vcvtss2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2USIZrr_Int, X86_INS_VCVTSS2USI: vcvtss2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTSS2USIZrrb_Int, X86_INS_VCVTSS2USI: vcvtss2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQYrm, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQYrr, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ128rm, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ128rmb, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ128rmbk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ128rmbkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ128rmk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ128rmkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ128rr, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ128rrk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ128rrkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ256rm, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ256rmb, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ256rmbk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ256rmbkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ256rmk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ256rmkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ256rr, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ256rrk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZ256rrkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZrm, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZrmb, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZrmbk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZrmbkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZrmk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZrmkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZrr, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZrrb, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZrrbk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZrrbkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZrrk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQZrrkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQrm, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2DQrr, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ128rm, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ128rmb, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ128rmbk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ128rmbkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ128rmk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ128rmkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ128rr, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ128rrk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ128rrkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ256rm, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ256rmb, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ256rmbk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ256rmbkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ256rmk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ256rmkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ256rr, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ256rrk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZ256rrkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZrm, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZrmb, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZrmbk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZrmbkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZrmk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZrmkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZrr, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZrrb, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZrrbk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZrrbkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZrrk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2QQZrrkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ128rm, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ128rmb, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ128rmbk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ128rmbkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ128rmk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ128rmkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ128rr, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ128rrk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ128rrkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ256rm, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ256rmb, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ256rmbk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ256rmbkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ256rmk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ256rmkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ256rr, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ256rrk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZ256rrkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZrm, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZrmb, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZrmbk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZrmbkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZrmk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZrmkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZrr, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZrrb, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZrrbk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZrrbkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZrrk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UDQZrrkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ128rm, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ128rmb, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ128rmbk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ128rmbkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ128rmk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ128rmkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ128rr, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ128rrk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ128rrkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ256rm, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ256rmb, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ256rmbk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ256rmbkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ256rmk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ256rmkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ256rr, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ256rrk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZ256rrkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZrm, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZrmb, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZrmbk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZrmbkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZrmk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZrmkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZrr, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZrrb, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZrrbk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZrrbkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZrrk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPD2UQQZrrkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQYrm, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQYrr, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ128rm, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ128rmb, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ128rmbk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ128rmbkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ128rmk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ128rmkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ128rr, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ128rrk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ128rrkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ256rm, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ256rmb, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ256rmbk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ256rmbkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ256rmk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ256rmkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ256rr, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ256rrk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZ256rrkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZrm, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZrmb, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZrmbk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZrmbkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZrmk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZrmkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZrr, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZrrb, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZrrbk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZrrbkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZrrk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQZrrkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQrm, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2DQrr, X86_INS_VCVTTPS2DQ: vcvttps2dq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ128rm, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ128rmb, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ128rmbk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ128rmbkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ128rmk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ128rmkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ128rr, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ128rrk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ128rrkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ256rm, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ256rmb, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ256rmbk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ256rmbkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ256rmk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ256rmkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ256rr, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ256rrk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZ256rrkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZrm, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZrmb, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZrmbk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZrmbkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZrmk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZrmkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZrr, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZrrb, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZrrbk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZrrbkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZrrk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2QQZrrkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ128rm, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ128rmb, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ128rmbk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ128rmbkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ128rmk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ128rmkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ128rr, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ128rrk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ128rrkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ256rm, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ256rmb, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ256rmbk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ256rmbkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ256rmk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ256rmkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ256rr, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ256rrk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZ256rrkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZrm, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZrmb, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZrmbk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZrmbkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZrmk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZrmkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZrr, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZrrb, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZrrbk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZrrbkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZrrk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UDQZrrkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ128rm, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ128rmb, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ128rmbk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ128rmbkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ128rmk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ128rmkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ128rr, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ128rrk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ128rrkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ256rm, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ256rmb, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ256rmbk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ256rmbkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ256rmk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ256rmkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ256rr, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ256rrk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZ256rrkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZrm, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZrmb, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZrmbk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZrmbkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZrmk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZrmkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZrr, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZrrb, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZrrbk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZrrbkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZrrk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTPS2UQQZrrkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SI64Zrm, X86_INS_VCVTTSD2SI: vcvttsd2si $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SI64Zrm_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SI64Zrr, X86_INS_VCVTTSD2SI: vcvttsd2si $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SI64Zrr_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SI64Zrrb_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SI64rm, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SI64rm_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SI64rr, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SI64rr_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SIZrm, X86_INS_VCVTTSD2SI: vcvttsd2si $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SIZrm_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SIZrr, X86_INS_VCVTTSD2SI: vcvttsd2si $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SIZrr_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SIZrrb_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SIrm, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SIrm_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SIrr, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2SIrr_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2USI64Zrm, X86_INS_VCVTTSD2USI: vcvttsd2usi $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2USI64Zrm_Int, X86_INS_VCVTTSD2USI: vcvttsd2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2USI64Zrr, X86_INS_VCVTTSD2USI: vcvttsd2usi $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2USI64Zrr_Int, X86_INS_VCVTTSD2USI: vcvttsd2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2USI64Zrrb_Int, X86_INS_VCVTTSD2USI: vcvttsd2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2USIZrm, X86_INS_VCVTTSD2USI: vcvttsd2usi $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2USIZrm_Int, X86_INS_VCVTTSD2USI: vcvttsd2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2USIZrr, X86_INS_VCVTTSD2USI: vcvttsd2usi $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2USIZrr_Int, X86_INS_VCVTTSD2USI: vcvttsd2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSD2USIZrrb_Int, X86_INS_VCVTTSD2USI: vcvttsd2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SI64Zrm, X86_INS_VCVTTSS2SI: vcvttss2si $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SI64Zrm_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SI64Zrr, X86_INS_VCVTTSS2SI: vcvttss2si $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SI64Zrr_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SI64Zrrb_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SI64rm, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SI64rm_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SI64rr, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SI64rr_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SIZrm, X86_INS_VCVTTSS2SI: vcvttss2si $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SIZrm_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SIZrr, X86_INS_VCVTTSS2SI: vcvttss2si $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SIZrr_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SIZrrb_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SIrm, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SIrm_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SIrr, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2SIrr_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2USI64Zrm, X86_INS_VCVTTSS2USI: vcvttss2usi $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2USI64Zrm_Int, X86_INS_VCVTTSS2USI: vcvttss2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2USI64Zrr, X86_INS_VCVTTSS2USI: vcvttss2usi $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2USI64Zrr_Int, X86_INS_VCVTTSS2USI: vcvttss2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2USI64Zrrb_Int, X86_INS_VCVTTSS2USI: vcvttss2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2USIZrm, X86_INS_VCVTTSS2USI: vcvttss2usi $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2USIZrm_Int, X86_INS_VCVTTSS2USI: vcvttss2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2USIZrr, X86_INS_VCVTTSS2USI: vcvttss2usi $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2USIZrr_Int, X86_INS_VCVTTSS2USI: vcvttss2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTTSS2USIZrrb_Int, X86_INS_VCVTTSS2USI: vcvttss2usi */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PDZ128rm, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ128rmb, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ128rmbk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ128rmbkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ128rmk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ128rmkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ128rr, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ128rrk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ128rrkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ256rm, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ256rmb, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ256rmbk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ256rmbkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ256rmk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ256rmkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ256rr, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ256rrk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZ256rrkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZrm, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PDZrmb, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZrmbk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZrmbkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZrmk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZrmkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZrr, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PDZrrk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PDZrrkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ + 0, + { 0 } +}, + +{ /* X86_VCVTUDQ2PSZ128rm, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ128rmb, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ128rmbk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ128rmbkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ128rmk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ128rmkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ128rr, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ128rrk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ128rrkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ256rm, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ256rmb, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ256rmbk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ256rmbkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ256rmk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ256rmkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ256rr, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ256rrk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZ256rrkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZrm, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZrmb, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZrmbk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZrmbkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZrmk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZrmkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZrr, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZrrb, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VCVTUDQ2PSZrrbk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZrrbkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZrrk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUDQ2PSZrrkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ128rm, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ128rmb, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ128rmbk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ128rmbkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ128rmk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ128rmkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ128rr, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ128rrk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ128rrkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ256rm, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ256rmb, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ256rmbk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ256rmbkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ256rmk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ256rmkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ256rr, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ256rrk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZ256rrkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZrm, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZrmb, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZrmbk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZrmbkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZrmk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZrmkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZrr, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZrrb, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZrrbk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZrrbkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZrrk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PDZrrkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ128rm, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ128rmb, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ128rmbk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ128rmbkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ128rmk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ128rmkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ128rr, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ128rrk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ128rrkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ256rm, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ256rmb, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ256rmbk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ256rmbkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ256rmk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ256rmkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ256rr, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ256rrk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZ256rrkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZrm, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZrmb, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZrmbk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZrmbkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZrmk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZrmkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZrr, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZrrb, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZrrbk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZrrbkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZrrk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUQQ2PSZrrkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI2SDZrm, X86_INS_VCVTUSI2SD: vcvtusi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI2SDZrm_Int, X86_INS_VCVTUSI2SD: vcvtusi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI2SDZrr, X86_INS_VCVTUSI2SD: vcvtusi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI2SDZrr_Int, X86_INS_VCVTUSI2SD: vcvtusi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI2SSZrm, X86_INS_VCVTUSI2SS: vcvtusi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI2SSZrm_Int, X86_INS_VCVTUSI2SS: vcvtusi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI2SSZrr, X86_INS_VCVTUSI2SS: vcvtusi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI2SSZrr_Int, X86_INS_VCVTUSI2SS: vcvtusi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI2SSZrrb_Int, X86_INS_VCVTUSI2SS: vcvtusi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI642SDZrm, X86_INS_VCVTUSI2SD: vcvtusi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI642SDZrm_Int, X86_INS_VCVTUSI2SD: vcvtusi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI642SDZrr, X86_INS_VCVTUSI2SD: vcvtusi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI642SDZrr_Int, X86_INS_VCVTUSI2SD: vcvtusi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI642SDZrrb_Int, X86_INS_VCVTUSI2SD: vcvtusi2sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI642SSZrm, X86_INS_VCVTUSI2SS: vcvtusi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI642SSZrm_Int, X86_INS_VCVTUSI2SS: vcvtusi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI642SSZrr, X86_INS_VCVTUSI2SS: vcvtusi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI642SSZrr_Int, X86_INS_VCVTUSI2SS: vcvtusi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VCVTUSI642SSZrrb_Int, X86_INS_VCVTUSI2SS: vcvtusi2ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDBPSADBWZ128rmi, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZ128rmik, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZ128rmikz, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZ128rri, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZ128rrik, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZ128rrikz, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZ256rmi, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZ256rmik, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZ256rmikz, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZ256rri, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZ256rrik, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZ256rrikz, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZrmi, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZrmik, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZrmikz, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZrri, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZrrik, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDBPSADBWZrrikz, X86_INS_VDBPSADBW: vdbpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDIVPDYrm, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDYrr, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ128rm, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ128rmb, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ128rmbk, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ128rmbkz, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ128rmk, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ128rmkz, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ128rr, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ128rrk, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ128rrkz, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ256rm, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ256rmb, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ256rmbk, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ256rmbkz, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ256rmk, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ256rmkz, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ256rr, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ256rrk, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZ256rrkz, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZrm, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZrmb, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZrmbk, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZrmbkz, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZrmk, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZrmkz, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZrr, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZrrb, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZrrbk, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZrrbkz, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZrrk, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDZrrkz, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDrm, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPDrr, X86_INS_VDIVPD: vdivpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSYrm, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSYrr, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ128rm, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ128rmb, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ128rmbk, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ128rmbkz, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ128rmk, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ128rmkz, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ128rr, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ128rrk, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ128rrkz, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ256rm, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ256rmb, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ256rmbk, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ256rmbkz, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ256rmk, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ256rmkz, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ256rr, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ256rrk, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZ256rrkz, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZrm, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZrmb, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZrmbk, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZrmbkz, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZrmk, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZrmkz, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZrr, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZrrb, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZrrbk, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZrrbkz, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZrrk, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSZrrkz, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSrm, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVPSrr, X86_INS_VDIVPS: vdivps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDZrm, X86_INS_VDIVSD: vdivsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDZrm_Int, X86_INS_VDIVSD: vdivsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDZrm_Intk, X86_INS_VDIVSD: vdivsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDZrm_Intkz, X86_INS_VDIVSD: vdivsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDZrr, X86_INS_VDIVSD: vdivsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDZrr_Int, X86_INS_VDIVSD: vdivsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDZrr_Intk, X86_INS_VDIVSD: vdivsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDZrr_Intkz, X86_INS_VDIVSD: vdivsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDZrrb_Int, X86_INS_VDIVSD: vdivsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDZrrb_Intk, X86_INS_VDIVSD: vdivsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDZrrb_Intkz, X86_INS_VDIVSD: vdivsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDrm, X86_INS_VDIVSD: vdivsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDrm_Int, X86_INS_VDIVSD: vdivsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDIVSDrr, X86_INS_VDIVSD: vdivsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSDrr_Int, X86_INS_VDIVSD: vdivsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSZrm, X86_INS_VDIVSS: vdivss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSZrm_Int, X86_INS_VDIVSS: vdivss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSZrm_Intk, X86_INS_VDIVSS: vdivss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSZrm_Intkz, X86_INS_VDIVSS: vdivss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSZrr, X86_INS_VDIVSS: vdivss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSZrr_Int, X86_INS_VDIVSS: vdivss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSZrr_Intk, X86_INS_VDIVSS: vdivss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSZrr_Intkz, X86_INS_VDIVSS: vdivss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSZrrb_Int, X86_INS_VDIVSS: vdivss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSZrrb_Intk, X86_INS_VDIVSS: vdivss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSZrrb_Intkz, X86_INS_VDIVSS: vdivss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSrm, X86_INS_VDIVSS: vdivss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSrm_Int, X86_INS_VDIVSS: vdivss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDIVSSrr, X86_INS_VDIVSS: vdivss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDIVSSrr_Int, X86_INS_VDIVSS: vdivss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VDPPDrmi, X86_INS_VDPPD: vdppd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDPPDrri, X86_INS_VDPPD: vdppd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDPPSYrmi, X86_INS_VDPPS: vdpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDPPSYrri, X86_INS_VDPPS: vdpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDPPSrmi, X86_INS_VDPPS: vdpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VDPPSrri, X86_INS_VDPPS: vdpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VERRm, X86_INS_VERR: verr */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_VERRr, X86_INS_VERR: verr */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_VERWm, X86_INS_VERW: verw */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_VERWr, X86_INS_VERW: verw */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PDZm, X86_INS_VEXP2PD: vexp2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PDZmb, X86_INS_VEXP2PD: vexp2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PDZmbk, X86_INS_VEXP2PD: vexp2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PDZmbkz, X86_INS_VEXP2PD: vexp2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PDZmk, X86_INS_VEXP2PD: vexp2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PDZmkz, X86_INS_VEXP2PD: vexp2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PDZr, X86_INS_VEXP2PD: vexp2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PDZrb, X86_INS_VEXP2PD: vexp2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PDZrbk, X86_INS_VEXP2PD: vexp2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PDZrbkz, X86_INS_VEXP2PD: vexp2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PDZrk, X86_INS_VEXP2PD: vexp2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PDZrkz, X86_INS_VEXP2PD: vexp2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PSZm, X86_INS_VEXP2PS: vexp2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PSZmb, X86_INS_VEXP2PS: vexp2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PSZmbk, X86_INS_VEXP2PS: vexp2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PSZmbkz, X86_INS_VEXP2PS: vexp2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PSZmk, X86_INS_VEXP2PS: vexp2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PSZmkz, X86_INS_VEXP2PS: vexp2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PSZr, X86_INS_VEXP2PS: vexp2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PSZrb, X86_INS_VEXP2PS: vexp2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PSZrbk, X86_INS_VEXP2PS: vexp2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PSZrbkz, X86_INS_VEXP2PS: vexp2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PSZrk, X86_INS_VEXP2PS: vexp2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXP2PSZrkz, X86_INS_VEXP2PS: vexp2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZ128rm, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZ128rmk, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZ128rmkz, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZ128rr, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZ128rrk, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZ128rrkz, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZ256rm, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZ256rmk, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZ256rmkz, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZ256rr, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZ256rrk, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZ256rrkz, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZrm, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZrmk, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZrmkz, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZrr, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZrrk, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPDZrrkz, X86_INS_VEXPANDPD: vexpandpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZ128rm, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZ128rmk, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZ128rmkz, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZ128rr, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZ128rrk, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZ128rrkz, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZ256rm, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZ256rmk, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZ256rmkz, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZ256rr, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZ256rrk, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZ256rrkz, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZrm, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZrmk, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZrmkz, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZrr, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZrrk, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXPANDPSZrrkz, X86_INS_VEXPANDPS: vexpandps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF128mr, X86_INS_VEXTRACTF128: vextractf128 */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VEXTRACTF128rr, X86_INS_VEXTRACTF128: vextractf128 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VEXTRACTF32x4Z256mr, X86_INS_VEXTRACTF32X4: vextractf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x4Z256mrk, X86_INS_VEXTRACTF32X4: vextractf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x4Z256rr, X86_INS_VEXTRACTF32X4: vextractf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x4Z256rrk, X86_INS_VEXTRACTF32X4: vextractf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x4Z256rrkz, X86_INS_VEXTRACTF32X4: vextractf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x4Zmr, X86_INS_VEXTRACTF32X4: vextractf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x4Zmrk, X86_INS_VEXTRACTF32X4: vextractf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x4Zrr, X86_INS_VEXTRACTF32X4: vextractf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x4Zrrk, X86_INS_VEXTRACTF32X4: vextractf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x4Zrrkz, X86_INS_VEXTRACTF32X4: vextractf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x8Zmr, X86_INS_VEXTRACTF32X8: vextractf32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x8Zmrk, X86_INS_VEXTRACTF32X8: vextractf32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x8Zrr, X86_INS_VEXTRACTF32X8: vextractf32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x8Zrrk, X86_INS_VEXTRACTF32X8: vextractf32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF32x8Zrrkz, X86_INS_VEXTRACTF32X8: vextractf32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x2Z256mr, X86_INS_VEXTRACTF64X2: vextractf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x2Z256mrk, X86_INS_VEXTRACTF64X2: vextractf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x2Z256rr, X86_INS_VEXTRACTF64X2: vextractf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x2Z256rrk, X86_INS_VEXTRACTF64X2: vextractf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x2Z256rrkz, X86_INS_VEXTRACTF64X2: vextractf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x2Zmr, X86_INS_VEXTRACTF64X2: vextractf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x2Zmrk, X86_INS_VEXTRACTF64X2: vextractf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x2Zrr, X86_INS_VEXTRACTF64X2: vextractf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x2Zrrk, X86_INS_VEXTRACTF64X2: vextractf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x2Zrrkz, X86_INS_VEXTRACTF64X2: vextractf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x4Zmr, X86_INS_VEXTRACTF64X4: vextractf64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x4Zmrk, X86_INS_VEXTRACTF64X4: vextractf64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x4Zrr, X86_INS_VEXTRACTF64X4: vextractf64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x4Zrrk, X86_INS_VEXTRACTF64X4: vextractf64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTF64x4Zrrkz, X86_INS_VEXTRACTF64X4: vextractf64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI128mr, X86_INS_VEXTRACTI128: vextracti128 */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VEXTRACTI128rr, X86_INS_VEXTRACTI128: vextracti128 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VEXTRACTI32x4Z256mr, X86_INS_VEXTRACTI32X4: vextracti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x4Z256mrk, X86_INS_VEXTRACTI32X4: vextracti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x4Z256rr, X86_INS_VEXTRACTI32X4: vextracti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x4Z256rrk, X86_INS_VEXTRACTI32X4: vextracti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x4Z256rrkz, X86_INS_VEXTRACTI32X4: vextracti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x4Zmr, X86_INS_VEXTRACTI32X4: vextracti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x4Zmrk, X86_INS_VEXTRACTI32X4: vextracti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x4Zrr, X86_INS_VEXTRACTI32X4: vextracti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x4Zrrk, X86_INS_VEXTRACTI32X4: vextracti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x4Zrrkz, X86_INS_VEXTRACTI32X4: vextracti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x8Zmr, X86_INS_VEXTRACTI32X8: vextracti32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x8Zmrk, X86_INS_VEXTRACTI32X8: vextracti32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x8Zrr, X86_INS_VEXTRACTI32X8: vextracti32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x8Zrrk, X86_INS_VEXTRACTI32X8: vextracti32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI32x8Zrrkz, X86_INS_VEXTRACTI32X8: vextracti32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x2Z256mr, X86_INS_VEXTRACTI64X2: vextracti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x2Z256mrk, X86_INS_VEXTRACTI64X2: vextracti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x2Z256rr, X86_INS_VEXTRACTI64X2: vextracti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x2Z256rrk, X86_INS_VEXTRACTI64X2: vextracti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x2Z256rrkz, X86_INS_VEXTRACTI64X2: vextracti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x2Zmr, X86_INS_VEXTRACTI64X2: vextracti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x2Zmrk, X86_INS_VEXTRACTI64X2: vextracti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x2Zrr, X86_INS_VEXTRACTI64X2: vextracti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x2Zrrk, X86_INS_VEXTRACTI64X2: vextracti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x2Zrrkz, X86_INS_VEXTRACTI64X2: vextracti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x4Zmr, X86_INS_VEXTRACTI64X4: vextracti64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x4Zmrk, X86_INS_VEXTRACTI64X4: vextracti64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x4Zrr, X86_INS_VEXTRACTI64X4: vextracti64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x4Zrrk, X86_INS_VEXTRACTI64X4: vextracti64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTI64x4Zrrkz, X86_INS_VEXTRACTI64X4: vextracti64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTPSZmr, X86_INS_VEXTRACTPS: vextractps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTPSZrr, X86_INS_VEXTRACTPS: vextractps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VEXTRACTPSmr, X86_INS_VEXTRACTPS: vextractps */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VEXTRACTPSrr, X86_INS_VEXTRACTPS: vextractps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ128rmbi, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ128rmbik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ128rmbikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ128rmi, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ128rmik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ128rmikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ128rri, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ128rrik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ128rrikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ256rmbi, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ256rmbik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ256rmbikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ256rmi, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ256rmik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ256rmikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ256rri, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ256rrik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZ256rrikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZrmbi, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZrmbik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZrmbikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZrmi, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZrmik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZrmikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZrri, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZrrib, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZrribk, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZrribkz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZrrik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPDZrrikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ128rmbi, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ128rmbik, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ128rmbikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ128rmi, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ128rmik, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ128rmikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ128rri, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ128rrik, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ128rrikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ256rmbi, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ256rmbik, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ256rmbikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ256rmi, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ256rmik, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ256rmikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ256rri, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ256rrik, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZ256rrikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZrmbi, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZrmbik, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZrmbikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZrmi, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZrmik, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZrmikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZrri, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZrrib, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZrribk, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZrribkz, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZrrik, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMPSZrrikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSDZrmi, X86_INS_VFIXUPIMMSD: vfixupimmsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSDZrmik, X86_INS_VFIXUPIMMSD: vfixupimmsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSDZrmikz, X86_INS_VFIXUPIMMSD: vfixupimmsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSDZrri, X86_INS_VFIXUPIMMSD: vfixupimmsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSDZrrib, X86_INS_VFIXUPIMMSD: vfixupimmsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSDZrribk, X86_INS_VFIXUPIMMSD: vfixupimmsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSDZrribkz, X86_INS_VFIXUPIMMSD: vfixupimmsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSDZrrik, X86_INS_VFIXUPIMMSD: vfixupimmsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSDZrrikz, X86_INS_VFIXUPIMMSD: vfixupimmsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSSZrmi, X86_INS_VFIXUPIMMSS: vfixupimmss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSSZrmik, X86_INS_VFIXUPIMMSS: vfixupimmss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSSZrmikz, X86_INS_VFIXUPIMMSS: vfixupimmss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSSZrri, X86_INS_VFIXUPIMMSS: vfixupimmss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSSZrrib, X86_INS_VFIXUPIMMSS: vfixupimmss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSSZrribk, X86_INS_VFIXUPIMMSS: vfixupimmss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSSZrribkz, X86_INS_VFIXUPIMMSS: vfixupimmss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSSZrrik, X86_INS_VFIXUPIMMSS: vfixupimmss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFIXUPIMMSSZrrikz, X86_INS_VFIXUPIMMSS: vfixupimmss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFMADD132PDYm, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDYr, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ128m, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ128mb, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ128mbk, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ128mbkz, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ128mk, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ128mkz, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ128r, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ128rk, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ128rkz, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ256m, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ256mb, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ256mbk, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ256mbkz, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ256mk, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ256mkz, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ256r, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ256rk, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZ256rkz, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZm, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZmb, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZmbk, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZmbkz, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZmk, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZmkz, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZr, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZrb, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZrbk, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZrbkz, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZrk, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDZrkz, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDm, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PDr, X86_INS_VFMADD132PD: vfmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSYm, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSYr, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ128m, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ128mb, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ128mbk, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ128mbkz, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ128mk, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ128mkz, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ128r, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ128rk, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ128rkz, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ256m, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ256mb, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ256mbk, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ256mbkz, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ256mk, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ256mkz, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ256r, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ256rk, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZ256rkz, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZm, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZmb, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZmbk, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZmbkz, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZmk, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZmkz, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZr, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZrb, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZrbk, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZrbkz, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZrk, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSZrkz, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSm, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132PSr, X86_INS_VFMADD132PS: vfmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDZm, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDZm_Int, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDZm_Intk, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDZm_Intkz, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDZr, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDZr_Int, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDZr_Intk, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDZr_Intkz, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDZrb, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDZrb_Int, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDZrb_Intk, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDZrb_Intkz, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDm, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDm_Int, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDr, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SDr_Int, X86_INS_VFMADD132SD: vfmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSZm, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSZm_Int, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSZm_Intk, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSZm_Intkz, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSZr, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSZr_Int, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSZr_Intk, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSZr_Intkz, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSZrb, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSZrb_Int, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSZrb_Intk, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSZrb_Intkz, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSm, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSm_Int, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSr, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD132SSr_Int, X86_INS_VFMADD132SS: vfmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDYm, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDYr, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ128m, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ128mb, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ128mbk, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ128mbkz, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ128mk, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ128mkz, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ128r, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ128rk, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ128rkz, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ256m, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ256mb, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ256mbk, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ256mbkz, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ256mk, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ256mkz, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ256r, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ256rk, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZ256rkz, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZm, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZmb, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZmbk, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZmbkz, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZmk, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZmkz, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZr, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZrb, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZrbk, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZrbkz, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZrk, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDZrkz, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDm, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PDr, X86_INS_VFMADD213PD: vfmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSYm, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSYr, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ128m, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ128mb, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ128mbk, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ128mbkz, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ128mk, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ128mkz, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ128r, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ128rk, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ128rkz, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ256m, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ256mb, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ256mbk, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ256mbkz, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ256mk, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ256mkz, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ256r, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ256rk, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZ256rkz, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZm, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZmb, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZmbk, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZmbkz, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZmk, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZmkz, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZr, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZrb, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZrbk, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZrbkz, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZrk, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSZrkz, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSm, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213PSr, X86_INS_VFMADD213PS: vfmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDZm, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDZm_Int, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDZm_Intk, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDZm_Intkz, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDZr, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDZr_Int, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDZr_Intk, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDZr_Intkz, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDZrb, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDZrb_Int, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDZrb_Intk, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDZrb_Intkz, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDm, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDm_Int, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDr, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SDr_Int, X86_INS_VFMADD213SD: vfmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSZm, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSZm_Int, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSZm_Intk, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSZm_Intkz, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSZr, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSZr_Int, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSZr_Intk, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSZr_Intkz, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSZrb, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSZrb_Int, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSZrb_Intk, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSZrb_Intkz, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSm, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSm_Int, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSr, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD213SSr_Int, X86_INS_VFMADD213SS: vfmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDYm, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDYr, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ128m, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ128mb, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ128mbk, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ128mbkz, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ128mk, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ128mkz, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ128r, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ128rk, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ128rkz, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ256m, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ256mb, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ256mbk, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ256mbkz, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ256mk, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ256mkz, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ256r, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ256rk, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZ256rkz, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZm, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZmb, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZmbk, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZmbkz, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZmk, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZmkz, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZr, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZrb, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZrbk, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZrbkz, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZrk, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDZrkz, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDm, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PDr, X86_INS_VFMADD231PD: vfmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSYm, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSYr, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ128m, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ128mb, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ128mbk, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ128mbkz, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ128mk, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ128mkz, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ128r, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ128rk, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ128rkz, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ256m, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ256mb, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ256mbk, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ256mbkz, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ256mk, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ256mkz, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ256r, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ256rk, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZ256rkz, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZm, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZmb, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZmbk, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZmbkz, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZmk, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZmkz, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZr, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZrb, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZrbk, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZrbkz, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZrk, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSZrkz, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSm, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231PSr, X86_INS_VFMADD231PS: vfmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDZm, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDZm_Int, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDZm_Intk, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDZm_Intkz, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDZr, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDZr_Int, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDZr_Intk, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDZr_Intkz, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDZrb, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDZrb_Int, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDZrb_Intk, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDZrb_Intkz, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDm, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDm_Int, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDr, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SDr_Int, X86_INS_VFMADD231SD: vfmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSZm, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSZm_Int, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSZm_Intk, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSZm_Intkz, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSZr, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSZr_Int, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSZr_Intk, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSZr_Intkz, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSZrb, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSZrb_Int, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSZrb_Intk, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSZrb_Intkz, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSm, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSm_Int, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSr, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADD231SSr_Int, X86_INS_VFMADD231SS: vfmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPD4Ymr, X86_INS_VFMADDPD: vfmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPD4Yrm, X86_INS_VFMADDPD: vfmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPD4Yrr, X86_INS_VFMADDPD: vfmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPD4Yrr_REV, X86_INS_VFMADDPD: vfmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPD4mr, X86_INS_VFMADDPD: vfmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPD4rm, X86_INS_VFMADDPD: vfmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPD4rr, X86_INS_VFMADDPD: vfmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPD4rr_REV, X86_INS_VFMADDPD: vfmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPS4Ymr, X86_INS_VFMADDPS: vfmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPS4Yrm, X86_INS_VFMADDPS: vfmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPS4Yrr, X86_INS_VFMADDPS: vfmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPS4Yrr_REV, X86_INS_VFMADDPS: vfmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPS4mr, X86_INS_VFMADDPS: vfmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPS4rm, X86_INS_VFMADDPS: vfmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPS4rr, X86_INS_VFMADDPS: vfmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDPS4rr_REV, X86_INS_VFMADDPS: vfmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSD4mr, X86_INS_VFMADDSD: vfmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSD4mr_Int, X86_INS_VFMADDSD: vfmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSD4rm, X86_INS_VFMADDSD: vfmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSD4rm_Int, X86_INS_VFMADDSD: vfmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFMADDSD4rr, X86_INS_VFMADDSD: vfmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSD4rr_Int, X86_INS_VFMADDSD: vfmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSD4rr_Int_REV, X86_INS_VFMADDSD: vfmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSD4rr_REV, X86_INS_VFMADDSD: vfmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSS4mr, X86_INS_VFMADDSS: vfmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSS4mr_Int, X86_INS_VFMADDSS: vfmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSS4rm, X86_INS_VFMADDSS: vfmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSS4rm_Int, X86_INS_VFMADDSS: vfmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFMADDSS4rr, X86_INS_VFMADDSS: vfmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSS4rr_Int, X86_INS_VFMADDSS: vfmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSS4rr_Int_REV, X86_INS_VFMADDSS: vfmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSS4rr_REV, X86_INS_VFMADDSS: vfmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDYm, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDYr, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ128m, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ128mb, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ128mbk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ128mbkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ128mk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ128mkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ128r, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ128rk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ128rkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ256m, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ256mb, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ256mbk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ256mbkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ256mk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ256mkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ256r, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ256rk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZ256rkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZm, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZmb, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZmbk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZmbkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZmk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZmkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZr, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZrb, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZrbk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZrbkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZrk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDZrkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDm, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PDr, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSYm, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSYr, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ128m, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ128mb, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ128mbk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ128mbkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ128mk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ128mkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ128r, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ128rk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ128rkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ256m, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ256mb, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ256mbk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ256mbkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ256mk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ256mkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ256r, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ256rk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZ256rkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZm, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZmb, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZmbk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZmbkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZmk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZmkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZr, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZrb, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZrbk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZrbkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZrk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSZrkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSm, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB132PSr, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDYm, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDYr, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ128m, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ128mb, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ128mbk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ128mbkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ128mk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ128mkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ128r, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ128rk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ128rkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ256m, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ256mb, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ256mbk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ256mbkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ256mk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ256mkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ256r, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ256rk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZ256rkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZm, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZmb, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZmbk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZmbkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZmk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZmkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZr, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZrb, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZrbk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZrbkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZrk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDZrkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDm, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PDr, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSYm, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSYr, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ128m, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ128mb, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ128mbk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ128mbkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ128mk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ128mkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ128r, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ128rk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ128rkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ256m, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ256mb, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ256mbk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ256mbkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ256mk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ256mkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ256r, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ256rk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZ256rkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZm, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZmb, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZmbk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZmbkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZmk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZmkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZr, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZrb, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZrbk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZrbkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZrk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSZrkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSm, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB213PSr, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDYm, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDYr, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ128m, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ128mb, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ128mbk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ128mbkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ128mk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ128mkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ128r, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ128rk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ128rkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ256m, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ256mb, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ256mbk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ256mbkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ256mk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ256mkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ256r, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ256rk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZ256rkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZm, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZmb, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZmbk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZmbkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZmk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZmkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZr, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZrb, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZrbk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZrbkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZrk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDZrkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDm, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PDr, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSYm, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSYr, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ128m, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ128mb, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ128mbk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ128mbkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ128mk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ128mkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ128r, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ128rk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ128rkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ256m, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ256mb, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ256mbk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ256mbkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ256mk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ256mkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ256r, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ256rk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZ256rkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZm, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZmb, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZmbk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZmbkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZmk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZmkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZr, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZrb, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZrbk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZrbkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZrk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSZrkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSm, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUB231PSr, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPD4Ymr, X86_INS_VFMADDSUBPD: vfmaddsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPD4Yrm, X86_INS_VFMADDSUBPD: vfmaddsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPD4Yrr, X86_INS_VFMADDSUBPD: vfmaddsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPD4Yrr_REV, X86_INS_VFMADDSUBPD: vfmaddsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPD4mr, X86_INS_VFMADDSUBPD: vfmaddsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPD4rm, X86_INS_VFMADDSUBPD: vfmaddsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPD4rr, X86_INS_VFMADDSUBPD: vfmaddsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPD4rr_REV, X86_INS_VFMADDSUBPD: vfmaddsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPS4Ymr, X86_INS_VFMADDSUBPS: vfmaddsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPS4Yrm, X86_INS_VFMADDSUBPS: vfmaddsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPS4Yrr, X86_INS_VFMADDSUBPS: vfmaddsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPS4Yrr_REV, X86_INS_VFMADDSUBPS: vfmaddsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPS4mr, X86_INS_VFMADDSUBPS: vfmaddsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPS4rm, X86_INS_VFMADDSUBPS: vfmaddsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPS4rr, X86_INS_VFMADDSUBPS: vfmaddsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMADDSUBPS4rr_REV, X86_INS_VFMADDSUBPS: vfmaddsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDYm, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDYr, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ128m, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ128mb, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ128mbk, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ128mbkz, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ128mk, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ128mkz, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ128r, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ128rk, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ128rkz, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ256m, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ256mb, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ256mbk, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ256mbkz, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ256mk, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ256mkz, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ256r, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ256rk, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZ256rkz, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZm, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZmb, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZmbk, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZmbkz, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZmk, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZmkz, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZr, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZrb, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZrbk, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZrbkz, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZrk, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDZrkz, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDm, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PDr, X86_INS_VFMSUB132PD: vfmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSYm, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSYr, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ128m, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ128mb, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ128mbk, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ128mbkz, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ128mk, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ128mkz, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ128r, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ128rk, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ128rkz, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ256m, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ256mb, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ256mbk, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ256mbkz, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ256mk, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ256mkz, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ256r, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ256rk, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZ256rkz, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZm, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZmb, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZmbk, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZmbkz, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZmk, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZmkz, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZr, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZrb, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZrbk, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZrbkz, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZrk, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSZrkz, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSm, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132PSr, X86_INS_VFMSUB132PS: vfmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDZm, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDZm_Int, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDZm_Intk, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDZm_Intkz, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDZr, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDZr_Int, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDZr_Intk, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDZr_Intkz, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDZrb, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDZrb_Int, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDZrb_Intk, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDZrb_Intkz, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDm, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDm_Int, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDr, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SDr_Int, X86_INS_VFMSUB132SD: vfmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSZm, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSZm_Int, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSZm_Intk, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSZm_Intkz, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSZr, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSZr_Int, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSZr_Intk, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSZr_Intkz, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSZrb, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSZrb_Int, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSZrb_Intk, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSZrb_Intkz, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSm, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSm_Int, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSr, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB132SSr_Int, X86_INS_VFMSUB132SS: vfmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDYm, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDYr, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ128m, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ128mb, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ128mbk, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ128mbkz, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ128mk, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ128mkz, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ128r, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ128rk, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ128rkz, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ256m, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ256mb, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ256mbk, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ256mbkz, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ256mk, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ256mkz, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ256r, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ256rk, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZ256rkz, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZm, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZmb, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZmbk, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZmbkz, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZmk, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZmkz, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZr, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZrb, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZrbk, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZrbkz, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZrk, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDZrkz, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDm, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PDr, X86_INS_VFMSUB213PD: vfmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSYm, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSYr, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ128m, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ128mb, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ128mbk, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ128mbkz, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ128mk, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ128mkz, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ128r, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ128rk, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ128rkz, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ256m, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ256mb, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ256mbk, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ256mbkz, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ256mk, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ256mkz, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ256r, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ256rk, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZ256rkz, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZm, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZmb, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZmbk, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZmbkz, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZmk, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZmkz, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZr, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZrb, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZrbk, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZrbkz, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZrk, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSZrkz, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSm, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213PSr, X86_INS_VFMSUB213PS: vfmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDZm, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDZm_Int, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDZm_Intk, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDZm_Intkz, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDZr, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDZr_Int, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDZr_Intk, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDZr_Intkz, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDZrb, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDZrb_Int, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDZrb_Intk, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDZrb_Intkz, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDm, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDm_Int, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDr, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SDr_Int, X86_INS_VFMSUB213SD: vfmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSZm, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSZm_Int, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSZm_Intk, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSZm_Intkz, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSZr, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSZr_Int, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSZr_Intk, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSZr_Intkz, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSZrb, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSZrb_Int, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSZrb_Intk, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSZrb_Intkz, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSm, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSm_Int, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSr, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB213SSr_Int, X86_INS_VFMSUB213SS: vfmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDYm, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDYr, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ128m, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ128mb, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ128mbk, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ128mbkz, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ128mk, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ128mkz, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ128r, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ128rk, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ128rkz, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ256m, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ256mb, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ256mbk, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ256mbkz, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ256mk, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ256mkz, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ256r, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ256rk, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZ256rkz, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZm, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZmb, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZmbk, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZmbkz, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZmk, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZmkz, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZr, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZrb, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZrbk, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZrbkz, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZrk, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDZrkz, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDm, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PDr, X86_INS_VFMSUB231PD: vfmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSYm, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSYr, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ128m, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ128mb, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ128mbk, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ128mbkz, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ128mk, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ128mkz, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ128r, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ128rk, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ128rkz, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ256m, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ256mb, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ256mbk, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ256mbkz, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ256mk, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ256mkz, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ256r, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ256rk, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZ256rkz, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZm, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZmb, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZmbk, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZmbkz, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZmk, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZmkz, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZr, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZrb, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZrbk, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZrbkz, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZrk, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSZrkz, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSm, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231PSr, X86_INS_VFMSUB231PS: vfmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDZm, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDZm_Int, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDZm_Intk, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDZm_Intkz, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDZr, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDZr_Int, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDZr_Intk, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDZr_Intkz, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDZrb, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDZrb_Int, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDZrb_Intk, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDZrb_Intkz, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDm, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDm_Int, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDr, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SDr_Int, X86_INS_VFMSUB231SD: vfmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSZm, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSZm_Int, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSZm_Intk, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSZm_Intkz, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSZr, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSZr_Int, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSZr_Intk, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSZr_Intkz, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSZrb, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSZrb_Int, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSZrb_Intk, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSZrb_Intkz, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSm, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSm_Int, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSr, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUB231SSr_Int, X86_INS_VFMSUB231SS: vfmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDYm, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDYr, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ128m, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ128mb, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ128mbk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ128mbkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ128mk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ128mkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ128r, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ128rk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ128rkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ256m, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ256mb, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ256mbk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ256mbkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ256mk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ256mkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ256r, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ256rk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZ256rkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZm, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZmb, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZmbk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZmbkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZmk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZmkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZr, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZrb, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZrbk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZrbkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZrk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDZrkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDm, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PDr, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSYm, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSYr, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ128m, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ128mb, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ128mbk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ128mbkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ128mk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ128mkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ128r, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ128rk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ128rkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ256m, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ256mb, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ256mbk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ256mbkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ256mk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ256mkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ256r, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ256rk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZ256rkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZm, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZmb, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZmbk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZmbkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZmk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZmkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZr, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZrb, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZrbk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZrbkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZrk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSZrkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSm, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD132PSr, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDYm, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDYr, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ128m, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ128mb, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ128mbk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ128mbkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ128mk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ128mkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ128r, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ128rk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ128rkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ256m, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ256mb, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ256mbk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ256mbkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ256mk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ256mkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ256r, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ256rk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZ256rkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZm, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZmb, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZmbk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZmbkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZmk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZmkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZr, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZrb, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZrbk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZrbkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZrk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDZrkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDm, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PDr, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSYm, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSYr, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ128m, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ128mb, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ128mbk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ128mbkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ128mk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ128mkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ128r, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ128rk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ128rkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ256m, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ256mb, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ256mbk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ256mbkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ256mk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ256mkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ256r, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ256rk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZ256rkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZm, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZmb, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZmbk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZmbkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZmk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZmkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZr, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZrb, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZrbk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZrbkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZrk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSZrkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSm, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD213PSr, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDYm, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDYr, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ128m, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ128mb, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ128mbk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ128mbkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ128mk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ128mkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ128r, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ128rk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ128rkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ256m, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ256mb, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ256mbk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ256mbkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ256mk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ256mkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ256r, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ256rk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZ256rkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZm, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZmb, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZmbk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZmbkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZmk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZmkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZr, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZrb, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZrbk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZrbkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZrk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDZrkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDm, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PDr, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSYm, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSYr, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ128m, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ128mb, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ128mbk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ128mbkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ128mk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ128mkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ128r, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ128rk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ128rkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ256m, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ256mb, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ256mbk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ256mbkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ256mk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ256mkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ256r, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ256rk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZ256rkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZm, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZmb, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZmbk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZmbkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZmk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZmkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZr, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZrb, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZrbk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZrbkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZrk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSZrkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSm, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADD231PSr, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPD4Ymr, X86_INS_VFMSUBADDPD: vfmsubaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPD4Yrm, X86_INS_VFMSUBADDPD: vfmsubaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPD4Yrr, X86_INS_VFMSUBADDPD: vfmsubaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPD4Yrr_REV, X86_INS_VFMSUBADDPD: vfmsubaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPD4mr, X86_INS_VFMSUBADDPD: vfmsubaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPD4rm, X86_INS_VFMSUBADDPD: vfmsubaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPD4rr, X86_INS_VFMSUBADDPD: vfmsubaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPD4rr_REV, X86_INS_VFMSUBADDPD: vfmsubaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPS4Ymr, X86_INS_VFMSUBADDPS: vfmsubaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPS4Yrm, X86_INS_VFMSUBADDPS: vfmsubaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPS4Yrr, X86_INS_VFMSUBADDPS: vfmsubaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPS4Yrr_REV, X86_INS_VFMSUBADDPS: vfmsubaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPS4mr, X86_INS_VFMSUBADDPS: vfmsubaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPS4rm, X86_INS_VFMSUBADDPS: vfmsubaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPS4rr, X86_INS_VFMSUBADDPS: vfmsubaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBADDPS4rr_REV, X86_INS_VFMSUBADDPS: vfmsubaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPD4Ymr, X86_INS_VFMSUBPD: vfmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPD4Yrm, X86_INS_VFMSUBPD: vfmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPD4Yrr, X86_INS_VFMSUBPD: vfmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPD4Yrr_REV, X86_INS_VFMSUBPD: vfmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPD4mr, X86_INS_VFMSUBPD: vfmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPD4rm, X86_INS_VFMSUBPD: vfmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPD4rr, X86_INS_VFMSUBPD: vfmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPD4rr_REV, X86_INS_VFMSUBPD: vfmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPS4Ymr, X86_INS_VFMSUBPS: vfmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPS4Yrm, X86_INS_VFMSUBPS: vfmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPS4Yrr, X86_INS_VFMSUBPS: vfmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPS4Yrr_REV, X86_INS_VFMSUBPS: vfmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPS4mr, X86_INS_VFMSUBPS: vfmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPS4rm, X86_INS_VFMSUBPS: vfmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPS4rr, X86_INS_VFMSUBPS: vfmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBPS4rr_REV, X86_INS_VFMSUBPS: vfmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSD4mr, X86_INS_VFMSUBSD: vfmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSD4mr_Int, X86_INS_VFMSUBSD: vfmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSD4rm, X86_INS_VFMSUBSD: vfmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSD4rm_Int, X86_INS_VFMSUBSD: vfmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFMSUBSD4rr, X86_INS_VFMSUBSD: vfmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSD4rr_Int, X86_INS_VFMSUBSD: vfmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSD4rr_Int_REV, X86_INS_VFMSUBSD: vfmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSD4rr_REV, X86_INS_VFMSUBSD: vfmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSS4mr, X86_INS_VFMSUBSS: vfmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSS4mr_Int, X86_INS_VFMSUBSS: vfmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSS4rm, X86_INS_VFMSUBSS: vfmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSS4rm_Int, X86_INS_VFMSUBSS: vfmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFMSUBSS4rr, X86_INS_VFMSUBSS: vfmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSS4rr_Int, X86_INS_VFMSUBSS: vfmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSS4rr_Int_REV, X86_INS_VFMSUBSS: vfmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFMSUBSS4rr_REV, X86_INS_VFMSUBSS: vfmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDYm, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDYr, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ128m, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ128mb, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ128mbk, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ128mbkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ128mk, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ128mkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ128r, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ128rk, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ128rkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ256m, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ256mb, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ256mbk, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ256mbkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ256mk, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ256mkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ256r, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ256rk, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZ256rkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZm, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZmb, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZmbk, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZmbkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZmk, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZmkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZr, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZrb, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZrbk, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZrbkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZrk, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDZrkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDm, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PDr, X86_INS_VFNMADD132PD: vfnmadd132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSYm, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSYr, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ128m, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ128mb, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ128mbk, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ128mbkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ128mk, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ128mkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ128r, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ128rk, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ128rkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ256m, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ256mb, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ256mbk, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ256mbkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ256mk, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ256mkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ256r, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ256rk, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZ256rkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZm, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZmb, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZmbk, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZmbkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZmk, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZmkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZr, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZrb, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZrbk, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZrbkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZrk, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSZrkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSm, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132PSr, X86_INS_VFNMADD132PS: vfnmadd132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDZm, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDZm_Int, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDZm_Intk, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDZm_Intkz, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDZr, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDZr_Int, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDZr_Intk, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDZr_Intkz, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDZrb, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDZrb_Int, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDZrb_Intk, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDZrb_Intkz, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDm, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDm_Int, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDr, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SDr_Int, X86_INS_VFNMADD132SD: vfnmadd132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSZm, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSZm_Int, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSZm_Intk, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSZm_Intkz, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSZr, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSZr_Int, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSZr_Intk, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSZr_Intkz, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSZrb, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSZrb_Int, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSZrb_Intk, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSZrb_Intkz, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSm, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSm_Int, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSr, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD132SSr_Int, X86_INS_VFNMADD132SS: vfnmadd132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDYm, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDYr, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ128m, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ128mb, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ128mbk, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ128mbkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ128mk, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ128mkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ128r, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ128rk, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ128rkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ256m, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ256mb, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ256mbk, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ256mbkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ256mk, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ256mkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ256r, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ256rk, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZ256rkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZm, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZmb, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZmbk, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZmbkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZmk, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZmkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZr, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZrb, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZrbk, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZrbkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZrk, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDZrkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDm, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PDr, X86_INS_VFNMADD213PD: vfnmadd213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSYm, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSYr, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ128m, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ128mb, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ128mbk, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ128mbkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ128mk, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ128mkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ128r, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ128rk, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ128rkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ256m, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ256mb, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ256mbk, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ256mbkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ256mk, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ256mkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ256r, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ256rk, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZ256rkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZm, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZmb, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZmbk, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZmbkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZmk, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZmkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZr, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZrb, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZrbk, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZrbkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZrk, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSZrkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSm, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213PSr, X86_INS_VFNMADD213PS: vfnmadd213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDZm, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDZm_Int, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDZm_Intk, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDZm_Intkz, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDZr, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDZr_Int, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDZr_Intk, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDZr_Intkz, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDZrb, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDZrb_Int, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDZrb_Intk, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDZrb_Intkz, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDm, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDm_Int, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDr, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SDr_Int, X86_INS_VFNMADD213SD: vfnmadd213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSZm, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSZm_Int, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSZm_Intk, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSZm_Intkz, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSZr, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSZr_Int, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSZr_Intk, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSZr_Intkz, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSZrb, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSZrb_Int, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSZrb_Intk, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSZrb_Intkz, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSm, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSm_Int, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSr, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD213SSr_Int, X86_INS_VFNMADD213SS: vfnmadd213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDYm, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDYr, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ128m, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ128mb, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ128mbk, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ128mbkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ128mk, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ128mkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ128r, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ128rk, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ128rkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ256m, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ256mb, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ256mbk, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ256mbkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ256mk, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ256mkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ256r, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ256rk, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZ256rkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZm, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZmb, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZmbk, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZmbkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZmk, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZmkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZr, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZrb, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZrbk, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZrbkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZrk, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDZrkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDm, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PDr, X86_INS_VFNMADD231PD: vfnmadd231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSYm, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSYr, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ128m, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ128mb, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ128mbk, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ128mbkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ128mk, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ128mkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ128r, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ128rk, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ128rkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ256m, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ256mb, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ256mbk, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ256mbkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ256mk, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ256mkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ256r, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ256rk, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZ256rkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZm, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZmb, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZmbk, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZmbkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZmk, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZmkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZr, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZrb, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZrbk, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZrbkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZrk, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSZrkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSm, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231PSr, X86_INS_VFNMADD231PS: vfnmadd231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDZm, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDZm_Int, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDZm_Intk, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDZm_Intkz, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDZr, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDZr_Int, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDZr_Intk, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDZr_Intkz, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDZrb, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDZrb_Int, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDZrb_Intk, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDZrb_Intkz, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDm, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDm_Int, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDr, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SDr_Int, X86_INS_VFNMADD231SD: vfnmadd231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSZm, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSZm_Int, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSZm_Intk, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSZm_Intkz, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSZr, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSZr_Int, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSZr_Intk, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSZr_Intkz, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSZrb, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSZrb_Int, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSZrb_Intk, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSZrb_Intkz, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSm, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSm_Int, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSr, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADD231SSr_Int, X86_INS_VFNMADD231SS: vfnmadd231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPD4Ymr, X86_INS_VFNMADDPD: vfnmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPD4Yrm, X86_INS_VFNMADDPD: vfnmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPD4Yrr, X86_INS_VFNMADDPD: vfnmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPD4Yrr_REV, X86_INS_VFNMADDPD: vfnmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPD4mr, X86_INS_VFNMADDPD: vfnmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPD4rm, X86_INS_VFNMADDPD: vfnmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPD4rr, X86_INS_VFNMADDPD: vfnmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPD4rr_REV, X86_INS_VFNMADDPD: vfnmaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPS4Ymr, X86_INS_VFNMADDPS: vfnmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPS4Yrm, X86_INS_VFNMADDPS: vfnmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPS4Yrr, X86_INS_VFNMADDPS: vfnmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPS4Yrr_REV, X86_INS_VFNMADDPS: vfnmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPS4mr, X86_INS_VFNMADDPS: vfnmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPS4rm, X86_INS_VFNMADDPS: vfnmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPS4rr, X86_INS_VFNMADDPS: vfnmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDPS4rr_REV, X86_INS_VFNMADDPS: vfnmaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSD4mr, X86_INS_VFNMADDSD: vfnmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSD4mr_Int, X86_INS_VFNMADDSD: vfnmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSD4rm, X86_INS_VFNMADDSD: vfnmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSD4rm_Int, X86_INS_VFNMADDSD: vfnmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFNMADDSD4rr, X86_INS_VFNMADDSD: vfnmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSD4rr_Int, X86_INS_VFNMADDSD: vfnmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSD4rr_Int_REV, X86_INS_VFNMADDSD: vfnmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSD4rr_REV, X86_INS_VFNMADDSD: vfnmaddsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSS4mr, X86_INS_VFNMADDSS: vfnmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSS4mr_Int, X86_INS_VFNMADDSS: vfnmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSS4rm, X86_INS_VFNMADDSS: vfnmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSS4rm_Int, X86_INS_VFNMADDSS: vfnmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFNMADDSS4rr, X86_INS_VFNMADDSS: vfnmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSS4rr_Int, X86_INS_VFNMADDSS: vfnmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSS4rr_Int_REV, X86_INS_VFNMADDSS: vfnmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMADDSS4rr_REV, X86_INS_VFNMADDSS: vfnmaddss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDYm, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDYr, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ128m, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ128mb, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ128mbk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ128mbkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ128mk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ128mkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ128r, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ128rk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ128rkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ256m, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ256mb, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ256mbk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ256mbkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ256mk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ256mkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ256r, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ256rk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZ256rkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZm, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZmb, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZmbk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZmbkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZmk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZmkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZr, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZrb, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZrbk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZrbkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZrk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDZrkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDm, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PDr, X86_INS_VFNMSUB132PD: vfnmsub132pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSYm, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSYr, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ128m, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ128mb, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ128mbk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ128mbkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ128mk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ128mkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ128r, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ128rk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ128rkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ256m, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ256mb, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ256mbk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ256mbkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ256mk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ256mkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ256r, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ256rk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZ256rkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZm, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZmb, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZmbk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZmbkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZmk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZmkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZr, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZrb, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZrbk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZrbkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZrk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSZrkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSm, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132PSr, X86_INS_VFNMSUB132PS: vfnmsub132ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDZm, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDZm_Int, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDZm_Intk, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDZm_Intkz, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDZr, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDZr_Int, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDZr_Intk, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDZr_Intkz, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDZrb, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDZrb_Int, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDZrb_Intk, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDZrb_Intkz, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDm, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDm_Int, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDr, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SDr_Int, X86_INS_VFNMSUB132SD: vfnmsub132sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSZm, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSZm_Int, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSZm_Intk, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSZm_Intkz, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSZr, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSZr_Int, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSZr_Intk, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSZr_Intkz, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSZrb, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSZrb_Int, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSZrb_Intk, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSZrb_Intkz, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSm, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSm_Int, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSr, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB132SSr_Int, X86_INS_VFNMSUB132SS: vfnmsub132ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDYm, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDYr, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ128m, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ128mb, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ128mbk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ128mbkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ128mk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ128mkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ128r, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ128rk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ128rkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ256m, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ256mb, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ256mbk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ256mbkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ256mk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ256mkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ256r, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ256rk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZ256rkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZm, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZmb, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZmbk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZmbkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZmk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZmkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZr, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZrb, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZrbk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZrbkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZrk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDZrkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDm, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PDr, X86_INS_VFNMSUB213PD: vfnmsub213pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSYm, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSYr, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ128m, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ128mb, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ128mbk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ128mbkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ128mk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ128mkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ128r, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ128rk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ128rkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ256m, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ256mb, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ256mbk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ256mbkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ256mk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ256mkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ256r, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ256rk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZ256rkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZm, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZmb, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZmbk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZmbkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZmk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZmkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZr, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZrb, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZrbk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZrbkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZrk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSZrkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSm, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213PSr, X86_INS_VFNMSUB213PS: vfnmsub213ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDZm, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDZm_Int, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDZm_Intk, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDZm_Intkz, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDZr, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDZr_Int, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDZr_Intk, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDZr_Intkz, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDZrb, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDZrb_Int, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDZrb_Intk, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDZrb_Intkz, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDm, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDm_Int, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDr, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SDr_Int, X86_INS_VFNMSUB213SD: vfnmsub213sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSZm, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSZm_Int, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSZm_Intk, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSZm_Intkz, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSZr, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSZr_Int, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSZr_Intk, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSZr_Intkz, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSZrb, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSZrb_Int, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSZrb_Intk, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSZrb_Intkz, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSm, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSm_Int, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSr, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB213SSr_Int, X86_INS_VFNMSUB213SS: vfnmsub213ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDYm, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDYr, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ128m, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ128mb, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ128mbk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ128mbkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ128mk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ128mkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ128r, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ128rk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ128rkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ256m, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ256mb, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ256mbk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ256mbkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ256mk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ256mkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ256r, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ256rk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZ256rkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZm, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZmb, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZmbk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZmbkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZmk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZmkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZr, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZrb, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZrbk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZrbkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZrk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDZrkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDm, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PDr, X86_INS_VFNMSUB231PD: vfnmsub231pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSYm, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSYr, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ128m, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ128mb, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ128mbk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ128mbkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ128mk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ128mkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ128r, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ128rk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ128rkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ256m, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ256mb, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ256mbk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ256mbkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ256mk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ256mkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ256r, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ256rk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZ256rkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZm, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZmb, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZmbk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZmbkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZmk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZmkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZr, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZrb, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZrbk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZrbkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZrk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSZrkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSm, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231PSr, X86_INS_VFNMSUB231PS: vfnmsub231ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDZm, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDZm_Int, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDZm_Intk, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDZm_Intkz, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDZr, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDZr_Int, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDZr_Intk, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDZr_Intkz, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDZrb, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDZrb_Int, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDZrb_Intk, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDZrb_Intkz, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDm, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDm_Int, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDr, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SDr_Int, X86_INS_VFNMSUB231SD: vfnmsub231sd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSZm, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSZm_Int, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSZm_Intk, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSZm_Intkz, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSZr, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSZr_Int, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSZr_Intk, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSZr_Intkz, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSZrb, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSZrb_Int, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSZrb_Intk, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSZrb_Intkz, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSm, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSm_Int, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSr, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUB231SSr_Int, X86_INS_VFNMSUB231SS: vfnmsub231ss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPD4Ymr, X86_INS_VFNMSUBPD: vfnmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPD4Yrm, X86_INS_VFNMSUBPD: vfnmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPD4Yrr, X86_INS_VFNMSUBPD: vfnmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPD4Yrr_REV, X86_INS_VFNMSUBPD: vfnmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPD4mr, X86_INS_VFNMSUBPD: vfnmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPD4rm, X86_INS_VFNMSUBPD: vfnmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPD4rr, X86_INS_VFNMSUBPD: vfnmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPD4rr_REV, X86_INS_VFNMSUBPD: vfnmsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPS4Ymr, X86_INS_VFNMSUBPS: vfnmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPS4Yrm, X86_INS_VFNMSUBPS: vfnmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPS4Yrr, X86_INS_VFNMSUBPS: vfnmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPS4Yrr_REV, X86_INS_VFNMSUBPS: vfnmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPS4mr, X86_INS_VFNMSUBPS: vfnmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPS4rm, X86_INS_VFNMSUBPS: vfnmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPS4rr, X86_INS_VFNMSUBPS: vfnmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBPS4rr_REV, X86_INS_VFNMSUBPS: vfnmsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSD4mr, X86_INS_VFNMSUBSD: vfnmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSD4mr_Int, X86_INS_VFNMSUBSD: vfnmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSD4rm, X86_INS_VFNMSUBSD: vfnmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSD4rm_Int, X86_INS_VFNMSUBSD: vfnmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFNMSUBSD4rr, X86_INS_VFNMSUBSD: vfnmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSD4rr_Int, X86_INS_VFNMSUBSD: vfnmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSD4rr_Int_REV, X86_INS_VFNMSUBSD: vfnmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSD4rr_REV, X86_INS_VFNMSUBSD: vfnmsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSS4mr, X86_INS_VFNMSUBSS: vfnmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSS4mr_Int, X86_INS_VFNMSUBSS: vfnmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSS4rm, X86_INS_VFNMSUBSS: vfnmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSS4rm_Int, X86_INS_VFNMSUBSS: vfnmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFNMSUBSS4rr, X86_INS_VFNMSUBSS: vfnmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSS4rr_Int, X86_INS_VFNMSUBSS: vfnmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSS4rr_Int_REV, X86_INS_VFNMSUBSS: vfnmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFNMSUBSS4rr_REV, X86_INS_VFNMSUBSS: vfnmsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZ128rm, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZ128rmb, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZ128rmbk, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZ128rmk, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZ128rr, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZ128rrk, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZ256rm, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZ256rmb, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZ256rmbk, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZ256rmk, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZ256rr, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZ256rrk, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZrm, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZrmb, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZrmbk, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZrmk, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZrr, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPDZrrk, X86_INS_VFPCLASSPD: vfpclasspd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZ128rm, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZ128rmb, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZ128rmbk, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZ128rmk, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZ128rr, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZ128rrk, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZ256rm, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZ256rmb, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZ256rmbk, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZ256rmk, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZ256rr, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZ256rrk, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZrm, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZrmb, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZrmbk, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZrmk, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZrr, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSPSZrrk, X86_INS_VFPCLASSPS: vfpclassps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSSDZrm, X86_INS_VFPCLASSSD: vfpclasssd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSSDZrmk, X86_INS_VFPCLASSSD: vfpclasssd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSSDZrr, X86_INS_VFPCLASSSD: vfpclasssd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSSDZrrk, X86_INS_VFPCLASSSD: vfpclasssd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSSSZrm, X86_INS_VFPCLASSSS: vfpclassss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSSSZrmk, X86_INS_VFPCLASSSS: vfpclassss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSSSZrr, X86_INS_VFPCLASSSS: vfpclassss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFPCLASSSSZrrk, X86_INS_VFPCLASSSS: vfpclassss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VFRCZPDYrm, X86_INS_VFRCZPD: vfrczpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VFRCZPDYrr, X86_INS_VFRCZPD: vfrczpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VFRCZPDrm, X86_INS_VFRCZPD: vfrczpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VFRCZPDrr, X86_INS_VFRCZPD: vfrczpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VFRCZPSYrm, X86_INS_VFRCZPS: vfrczps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VFRCZPSYrr, X86_INS_VFRCZPS: vfrczps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VFRCZPSrm, X86_INS_VFRCZPS: vfrczps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VFRCZPSrr, X86_INS_VFRCZPS: vfrczps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VFRCZSDrm, X86_INS_VFRCZSD: vfrczsd */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFRCZSDrr, X86_INS_VFRCZSD: vfrczsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VFRCZSSrm, X86_INS_VFRCZSS: vfrczss */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VFRCZSSrr, X86_INS_VFRCZSS: vfrczss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERDPDYrm, X86_INS_VGATHERDPD: vgatherdpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERDPDZ128rm, X86_INS_VGATHERDPD: vgatherdpd */ + 0, + { 0 } +}, + +{ /* X86_VGATHERDPDZ256rm, X86_INS_VGATHERDPD: vgatherdpd */ + 0, + { 0 } +}, + +{ /* X86_VGATHERDPDZrm, X86_INS_VGATHERDPD: vgatherdpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERDPDrm, X86_INS_VGATHERDPD: vgatherdpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERDPSYrm, X86_INS_VGATHERDPS: vgatherdps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERDPSZ128rm, X86_INS_VGATHERDPS: vgatherdps */ + 0, + { 0 } +}, + +{ /* X86_VGATHERDPSZ256rm, X86_INS_VGATHERDPS: vgatherdps */ + 0, + { 0 } +}, + +{ /* X86_VGATHERDPSZrm, X86_INS_VGATHERDPS: vgatherdps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERDPSrm, X86_INS_VGATHERDPS: vgatherdps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERPF0DPDm, X86_INS_VGATHERPF0DPD: vgatherpf0dpd */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERPF0DPSm, X86_INS_VGATHERPF0DPS: vgatherpf0dps */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERPF0QPDm, X86_INS_VGATHERPF0QPD: vgatherpf0qpd */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERPF0QPSm, X86_INS_VGATHERPF0QPS: vgatherpf0qps */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERPF1DPDm, X86_INS_VGATHERPF1DPD: vgatherpf1dpd */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERPF1DPSm, X86_INS_VGATHERPF1DPS: vgatherpf1dps */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERPF1QPDm, X86_INS_VGATHERPF1QPD: vgatherpf1qpd */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERPF1QPSm, X86_INS_VGATHERPF1QPS: vgatherpf1qps */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERQPDYrm, X86_INS_VGATHERQPD: vgatherqpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERQPDZ128rm, X86_INS_VGATHERQPD: vgatherqpd */ + 0, + { 0 } +}, + +{ /* X86_VGATHERQPDZ256rm, X86_INS_VGATHERQPD: vgatherqpd */ + 0, + { 0 } +}, + +{ /* X86_VGATHERQPDZrm, X86_INS_VGATHERQPD: vgatherqpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERQPDrm, X86_INS_VGATHERQPD: vgatherqpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERQPSYrm, X86_INS_VGATHERQPS: vgatherqps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERQPSZ128rm, X86_INS_VGATHERQPS: vgatherqps */ + 0, + { 0 } +}, + +{ /* X86_VGATHERQPSZ256rm, X86_INS_VGATHERQPS: vgatherqps */ + 0, + { 0 } +}, + +{ /* X86_VGATHERQPSZrm, X86_INS_VGATHERQPS: vgatherqps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VGATHERQPSrm, X86_INS_VGATHERQPS: vgatherqps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPPDZ128m, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ128mb, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ128mbk, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ128mbkz, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ128mk, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ128mkz, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ128r, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ128rk, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ128rkz, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ256m, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ256mb, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ256mbk, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ256mbkz, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ256mk, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ256mkz, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ256r, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ256rk, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZ256rkz, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZm, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZmb, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZmbk, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZmbkz, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZmk, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZmkz, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZr, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZrb, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZrbk, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZrbkz, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZrk, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPDZrkz, X86_INS_VGETEXPPD: vgetexppd */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ128m, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ128mb, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ128mbk, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ128mbkz, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ128mk, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ128mkz, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ128r, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ128rk, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ128rkz, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ256m, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ256mb, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ256mbk, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ256mbkz, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ256mk, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ256mkz, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ256r, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ256rk, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZ256rkz, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZm, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZmb, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZmbk, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZmbkz, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZmk, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZmkz, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZr, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZrb, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZrbk, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZrbkz, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZrk, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPPSZrkz, X86_INS_VGETEXPPS: vgetexpps */ + 0, + { 0 } +}, + +{ /* X86_VGETEXPSDZm, X86_INS_VGETEXPSD: vgetexpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSDZmk, X86_INS_VGETEXPSD: vgetexpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSDZmkz, X86_INS_VGETEXPSD: vgetexpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSDZr, X86_INS_VGETEXPSD: vgetexpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSDZrb, X86_INS_VGETEXPSD: vgetexpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSDZrbk, X86_INS_VGETEXPSD: vgetexpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSDZrbkz, X86_INS_VGETEXPSD: vgetexpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSDZrk, X86_INS_VGETEXPSD: vgetexpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSDZrkz, X86_INS_VGETEXPSD: vgetexpsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSSZm, X86_INS_VGETEXPSS: vgetexpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSSZmk, X86_INS_VGETEXPSS: vgetexpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSSZmkz, X86_INS_VGETEXPSS: vgetexpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSSZr, X86_INS_VGETEXPSS: vgetexpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSSZrb, X86_INS_VGETEXPSS: vgetexpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSSZrbk, X86_INS_VGETEXPSS: vgetexpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSSZrbkz, X86_INS_VGETEXPSS: vgetexpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSSZrk, X86_INS_VGETEXPSS: vgetexpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETEXPSSZrkz, X86_INS_VGETEXPSS: vgetexpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGETMANTPDZ128rmbi, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ128rmbik, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ128rmbikz, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ128rmi, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ128rmik, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ128rmikz, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ128rri, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ128rrik, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ128rrikz, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ256rmbi, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ256rmbik, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ256rmbikz, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ256rmi, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ256rmik, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ256rmikz, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ256rri, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ256rrik, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZ256rrikz, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZrmbi, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZrmbik, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZrmbikz, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZrmi, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZrmik, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZrmikz, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZrri, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZrrib, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZrribk, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZrribkz, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZrrik, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPDZrrikz, X86_INS_VGETMANTPD: vgetmantpd */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ128rmbi, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ128rmbik, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ128rmbikz, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ128rmi, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ128rmik, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ128rmikz, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ128rri, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ128rrik, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ128rrikz, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ256rmbi, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ256rmbik, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ256rmbikz, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ256rmi, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ256rmik, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ256rmikz, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ256rri, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ256rrik, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZ256rrikz, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZrmbi, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZrmbik, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZrmbikz, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZrmi, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZrmik, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZrmikz, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZrri, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZrrib, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZrribk, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZrribkz, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZrrik, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTPSZrrikz, X86_INS_VGETMANTPS: vgetmantps */ + 0, + { 0 } +}, + +{ /* X86_VGETMANTSDZrmi, X86_INS_VGETMANTSD: vgetmantsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSDZrmik, X86_INS_VGETMANTSD: vgetmantsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSDZrmikz, X86_INS_VGETMANTSD: vgetmantsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSDZrri, X86_INS_VGETMANTSD: vgetmantsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSDZrrib, X86_INS_VGETMANTSD: vgetmantsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSDZrribk, X86_INS_VGETMANTSD: vgetmantsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSDZrribkz, X86_INS_VGETMANTSD: vgetmantsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSDZrrik, X86_INS_VGETMANTSD: vgetmantsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSDZrrikz, X86_INS_VGETMANTSD: vgetmantsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSSZrmi, X86_INS_VGETMANTSS: vgetmantss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSSZrmik, X86_INS_VGETMANTSS: vgetmantss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSSZrmikz, X86_INS_VGETMANTSS: vgetmantss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSSZrri, X86_INS_VGETMANTSS: vgetmantss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSSZrrib, X86_INS_VGETMANTSS: vgetmantss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSSZrribk, X86_INS_VGETMANTSS: vgetmantss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSSZrribkz, X86_INS_VGETMANTSS: vgetmantss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSSZrrik, X86_INS_VGETMANTSS: vgetmantss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGETMANTSSZrrikz, X86_INS_VGETMANTSS: vgetmantss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBYrmi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBYrri, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ128rmbi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ128rmbik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ128rmbikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ128rmi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ128rmik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ128rmikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ128rri, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ128rrik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ128rrikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ256rmbi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ256rmbik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ256rmbikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ256rmi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ256rmik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ256rmikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ256rri, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ256rrik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZ256rrikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZrmbi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZrmbik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZrmbikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZrmi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZrmik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZrmikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZrri, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZrrik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBZrrikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBrmi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEINVQBrri, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBYrmi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBYrri, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ128rmbi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ128rmbik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ128rmbikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ128rmi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ128rmik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ128rmikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ128rri, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ128rrik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ128rrikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ256rmbi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ256rmbik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ256rmbikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ256rmi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ256rmik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ256rmikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ256rri, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ256rrik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZ256rrikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZrmbi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZrmbik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZrmbikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZrmi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZrmik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZrmikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZrri, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZrrik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBZrrikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBrmi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8AFFINEQBrri, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VGF2P8MULBYrm, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBYrr, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZ128rm, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZ128rmk, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZ128rmkz, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZ128rr, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZ128rrk, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZ128rrkz, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZ256rm, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZ256rmk, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZ256rmkz, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZ256rr, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZ256rrk, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZ256rrkz, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZrm, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZrmk, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZrmkz, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZrr, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZrrk, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBZrrkz, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBrm, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VGF2P8MULBrr, X86_INS_VGF2P8MULB: vgf2p8mulb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHADDPDYrm, X86_INS_VHADDPD: vhaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHADDPDYrr, X86_INS_VHADDPD: vhaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHADDPDrm, X86_INS_VHADDPD: vhaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHADDPDrr, X86_INS_VHADDPD: vhaddpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHADDPSYrm, X86_INS_VHADDPS: vhaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHADDPSYrr, X86_INS_VHADDPS: vhaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHADDPSrm, X86_INS_VHADDPS: vhaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHADDPSrr, X86_INS_VHADDPS: vhaddps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHSUBPDYrm, X86_INS_VHSUBPD: vhsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHSUBPDYrr, X86_INS_VHSUBPD: vhsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHSUBPDrm, X86_INS_VHSUBPD: vhsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHSUBPDrr, X86_INS_VHSUBPD: vhsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHSUBPSYrm, X86_INS_VHSUBPS: vhsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHSUBPSYrr, X86_INS_VHSUBPS: vhsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHSUBPSrm, X86_INS_VHSUBPS: vhsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VHSUBPSrr, X86_INS_VHSUBPS: vhsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF128rm, X86_INS_VINSERTF128: vinsertf128 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VINSERTF128rr, X86_INS_VINSERTF128: vinsertf128 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VINSERTF32x4Z256rm, X86_INS_VINSERTF32X4: vinsertf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x4Z256rmk, X86_INS_VINSERTF32X4: vinsertf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x4Z256rmkz, X86_INS_VINSERTF32X4: vinsertf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x4Z256rr, X86_INS_VINSERTF32X4: vinsertf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x4Z256rrk, X86_INS_VINSERTF32X4: vinsertf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x4Z256rrkz, X86_INS_VINSERTF32X4: vinsertf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x4Zrm, X86_INS_VINSERTF32X4: vinsertf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x4Zrmk, X86_INS_VINSERTF32X4: vinsertf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x4Zrmkz, X86_INS_VINSERTF32X4: vinsertf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x4Zrr, X86_INS_VINSERTF32X4: vinsertf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x4Zrrk, X86_INS_VINSERTF32X4: vinsertf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x4Zrrkz, X86_INS_VINSERTF32X4: vinsertf32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x8Zrm, X86_INS_VINSERTF32X8: vinsertf32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x8Zrmk, X86_INS_VINSERTF32X8: vinsertf32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x8Zrmkz, X86_INS_VINSERTF32X8: vinsertf32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x8Zrr, X86_INS_VINSERTF32X8: vinsertf32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x8Zrrk, X86_INS_VINSERTF32X8: vinsertf32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF32x8Zrrkz, X86_INS_VINSERTF32X8: vinsertf32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x2Z256rm, X86_INS_VINSERTF64X2: vinsertf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x2Z256rmk, X86_INS_VINSERTF64X2: vinsertf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x2Z256rmkz, X86_INS_VINSERTF64X2: vinsertf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x2Z256rr, X86_INS_VINSERTF64X2: vinsertf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x2Z256rrk, X86_INS_VINSERTF64X2: vinsertf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x2Z256rrkz, X86_INS_VINSERTF64X2: vinsertf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x2Zrm, X86_INS_VINSERTF64X2: vinsertf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x2Zrmk, X86_INS_VINSERTF64X2: vinsertf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x2Zrmkz, X86_INS_VINSERTF64X2: vinsertf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x2Zrr, X86_INS_VINSERTF64X2: vinsertf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x2Zrrk, X86_INS_VINSERTF64X2: vinsertf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x2Zrrkz, X86_INS_VINSERTF64X2: vinsertf64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x4Zrm, X86_INS_VINSERTF64X4: vinsertf64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x4Zrmk, X86_INS_VINSERTF64X4: vinsertf64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x4Zrmkz, X86_INS_VINSERTF64X4: vinsertf64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x4Zrr, X86_INS_VINSERTF64X4: vinsertf64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x4Zrrk, X86_INS_VINSERTF64X4: vinsertf64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTF64x4Zrrkz, X86_INS_VINSERTF64X4: vinsertf64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI128rm, X86_INS_VINSERTI128: vinserti128 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VINSERTI128rr, X86_INS_VINSERTI128: vinserti128 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VINSERTI32x4Z256rm, X86_INS_VINSERTI32X4: vinserti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x4Z256rmk, X86_INS_VINSERTI32X4: vinserti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x4Z256rmkz, X86_INS_VINSERTI32X4: vinserti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x4Z256rr, X86_INS_VINSERTI32X4: vinserti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x4Z256rrk, X86_INS_VINSERTI32X4: vinserti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x4Z256rrkz, X86_INS_VINSERTI32X4: vinserti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x4Zrm, X86_INS_VINSERTI32X4: vinserti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x4Zrmk, X86_INS_VINSERTI32X4: vinserti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x4Zrmkz, X86_INS_VINSERTI32X4: vinserti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x4Zrr, X86_INS_VINSERTI32X4: vinserti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x4Zrrk, X86_INS_VINSERTI32X4: vinserti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x4Zrrkz, X86_INS_VINSERTI32X4: vinserti32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x8Zrm, X86_INS_VINSERTI32X8: vinserti32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x8Zrmk, X86_INS_VINSERTI32X8: vinserti32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x8Zrmkz, X86_INS_VINSERTI32X8: vinserti32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x8Zrr, X86_INS_VINSERTI32X8: vinserti32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x8Zrrk, X86_INS_VINSERTI32X8: vinserti32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI32x8Zrrkz, X86_INS_VINSERTI32X8: vinserti32x8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x2Z256rm, X86_INS_VINSERTI64X2: vinserti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x2Z256rmk, X86_INS_VINSERTI64X2: vinserti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x2Z256rmkz, X86_INS_VINSERTI64X2: vinserti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x2Z256rr, X86_INS_VINSERTI64X2: vinserti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x2Z256rrk, X86_INS_VINSERTI64X2: vinserti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x2Z256rrkz, X86_INS_VINSERTI64X2: vinserti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x2Zrm, X86_INS_VINSERTI64X2: vinserti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x2Zrmk, X86_INS_VINSERTI64X2: vinserti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x2Zrmkz, X86_INS_VINSERTI64X2: vinserti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x2Zrr, X86_INS_VINSERTI64X2: vinserti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x2Zrrk, X86_INS_VINSERTI64X2: vinserti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x2Zrrkz, X86_INS_VINSERTI64X2: vinserti64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x4Zrm, X86_INS_VINSERTI64X4: vinserti64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x4Zrmk, X86_INS_VINSERTI64X4: vinserti64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x4Zrmkz, X86_INS_VINSERTI64X4: vinserti64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x4Zrr, X86_INS_VINSERTI64X4: vinserti64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x4Zrrk, X86_INS_VINSERTI64X4: vinserti64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTI64x4Zrrkz, X86_INS_VINSERTI64X4: vinserti64x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTPSZrm, X86_INS_VINSERTPS: vinsertps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTPSZrr, X86_INS_VINSERTPS: vinsertps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VINSERTPSrm, X86_INS_VINSERTPS: vinsertps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VINSERTPSrr, X86_INS_VINSERTPS: vinsertps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VLDDQUYrm, X86_INS_VLDDQU: vlddqu */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VLDDQUrm, X86_INS_VLDDQU: vlddqu */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VLDMXCSR, X86_INS_VLDMXCSR: vldmxcsr */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMASKMOVDQU, X86_INS_VMASKMOVDQU: vmaskmovdqu */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMASKMOVDQU64, X86_INS_VMASKMOVDQU: vmaskmovdqu */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMASKMOVPDYmr, X86_INS_VMASKMOVPD: vmaskmovpd */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMASKMOVPDYrm, X86_INS_VMASKMOVPD: vmaskmovpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMASKMOVPDmr, X86_INS_VMASKMOVPD: vmaskmovpd */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMASKMOVPDrm, X86_INS_VMASKMOVPD: vmaskmovpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMASKMOVPSYmr, X86_INS_VMASKMOVPS: vmaskmovps */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMASKMOVPSYrm, X86_INS_VMASKMOVPS: vmaskmovps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMASKMOVPSmr, X86_INS_VMASKMOVPS: vmaskmovps */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMASKMOVPSrm, X86_INS_VMASKMOVPS: vmaskmovps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDYrm, X86_INS_VMAXPD: vmaxpd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDYrr, X86_INS_VMAXPD: vmaxpd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ128rm, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ128rmb, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ128rmbk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ128rmbkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ128rmk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ128rmkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ128rr, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ128rrk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ128rrkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ256rm, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ256rmb, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ256rmbk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ256rmbkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ256rmk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ256rmkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ256rr, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ256rrk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZ256rrkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZrm, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZrmb, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZrmbk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZrmbkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZrmk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZrmkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZrr, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZrrk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDZrrkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDrm, X86_INS_VMAXPD: vmaxpd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPDrr, X86_INS_VMAXPD: vmaxpd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSYrm, X86_INS_VMAXPS: vmaxps $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSYrr, X86_INS_VMAXPS: vmaxps $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ128rm, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ128rmb, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ128rmbk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ128rmbkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ128rmk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ128rmkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ128rr, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ128rrk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ128rrkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ256rm, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ256rmb, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ256rmbk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ256rmbkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ256rmk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ256rmkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ256rr, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ256rrk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZ256rrkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZrm, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZrmb, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZrmbk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZrmbkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZrmk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZrmkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZrr, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZrrk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSZrrkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSrm, X86_INS_VMAXPS: vmaxps $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCPSrr, X86_INS_VMAXPS: vmaxps $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCSDZrm, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCSDZrr, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCSDrm, X86_INS_VMAXSD: vmaxsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCSDrr, X86_INS_VMAXSD: vmaxsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCSSZrm, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCSSZrr, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCSSrm, X86_INS_VMAXSS: vmaxss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXCSSrr, X86_INS_VMAXSS: vmaxss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDYrm, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDYrr, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ128rm, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ128rmb, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ128rmbk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ128rmbkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ128rmk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ128rmkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ128rr, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ128rrk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ128rrkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ256rm, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ256rmb, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ256rmbk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ256rmbkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ256rmk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ256rmkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ256rr, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ256rrk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZ256rrkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZrm, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZrmb, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZrmbk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZrmbkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZrmk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZrmkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZrr, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZrrb, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZrrbk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZrrbkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZrrk, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDZrrkz, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDrm, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPDrr, X86_INS_VMAXPD: vmaxpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSYrm, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSYrr, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ128rm, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ128rmb, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ128rmbk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ128rmbkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ128rmk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ128rmkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ128rr, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ128rrk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ128rrkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ256rm, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ256rmb, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ256rmbk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ256rmbkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ256rmk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ256rmkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ256rr, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ256rrk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZ256rrkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZrm, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZrmb, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZrmbk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZrmbkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZrmk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZrmkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZrr, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZrrb, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZrrbk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZrrbkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZrrk, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSZrrkz, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSrm, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXPSrr, X86_INS_VMAXPS: vmaxps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDZrm, X86_INS_VMAXSD: vmaxsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDZrm_Int, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDZrm_Intk, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDZrm_Intkz, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDZrr, X86_INS_VMAXSD: vmaxsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDZrr_Int, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDZrr_Intk, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDZrr_Intkz, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDZrrb_Int, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDZrrb_Intk, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDZrrb_Intkz, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDrm, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDrm_Int, X86_INS_VMAXSD: vmaxsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VMAXSDrr, X86_INS_VMAXSD: vmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSDrr_Int, X86_INS_VMAXSD: vmaxsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSZrm, X86_INS_VMAXSS: vmaxss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSZrm_Int, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSZrm_Intk, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSZrm_Intkz, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSZrr, X86_INS_VMAXSS: vmaxss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSZrr_Int, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSZrr_Intk, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSZrr_Intkz, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSZrrb_Int, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSZrrb_Intk, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSZrrb_Intkz, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSrm, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSrm_Int, X86_INS_VMAXSS: vmaxss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VMAXSSrr, X86_INS_VMAXSS: vmaxss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMAXSSrr_Int, X86_INS_VMAXSS: vmaxss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMCALL, X86_INS_VMCALL: vmcall */ + 0, + { 0 } +}, + +{ /* X86_VMCLEARm, X86_INS_VMCLEAR: vmclear */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMFUNC, X86_INS_VMFUNC: vmfunc */ + 0, + { 0 } +}, + +{ /* X86_VMINCPDYrm, X86_INS_VMINPD: vminpd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDYrr, X86_INS_VMINPD: vminpd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ128rm, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ128rmb, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ128rmbk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ128rmbkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ128rmk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ128rmkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ128rr, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ128rrk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ128rrkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ256rm, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ256rmb, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ256rmbk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ256rmbkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ256rmk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ256rmkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ256rr, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ256rrk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZ256rrkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZrm, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZrmb, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZrmbk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZrmbkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZrmk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZrmkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZrr, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZrrk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDZrrkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDrm, X86_INS_VMINPD: vminpd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPDrr, X86_INS_VMINPD: vminpd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSYrm, X86_INS_VMINPS: vminps $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSYrr, X86_INS_VMINPS: vminps $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ128rm, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ128rmb, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ128rmbk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ128rmbkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ128rmk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ128rmkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ128rr, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ128rrk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ128rrkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ256rm, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ256rmb, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ256rmbk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ256rmbkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ256rmk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ256rmkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ256rr, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ256rrk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZ256rrkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZrm, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZrmb, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZrmbk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZrmbkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZrmk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZrmkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZrr, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZrrk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSZrrkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSrm, X86_INS_VMINPS: vminps $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCPSrr, X86_INS_VMINPS: vminps $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCSDZrm, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCSDZrr, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCSDrm, X86_INS_VMINSD: vminsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCSDrr, X86_INS_VMINSD: vminsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCSSZrm, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCSSZrr, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCSSrm, X86_INS_VMINSS: vminss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINCSSrr, X86_INS_VMINSS: vminss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDYrm, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDYrr, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ128rm, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ128rmb, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ128rmbk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ128rmbkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ128rmk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ128rmkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ128rr, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ128rrk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ128rrkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ256rm, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ256rmb, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ256rmbk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ256rmbkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ256rmk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ256rmkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ256rr, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ256rrk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZ256rrkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZrm, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZrmb, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZrmbk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZrmbkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZrmk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZrmkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZrr, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZrrb, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZrrbk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZrrbkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZrrk, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDZrrkz, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDrm, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPDrr, X86_INS_VMINPD: vminpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSYrm, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSYrr, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ128rm, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ128rmb, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ128rmbk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ128rmbkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ128rmk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ128rmkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ128rr, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ128rrk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ128rrkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ256rm, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ256rmb, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ256rmbk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ256rmbkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ256rmk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ256rmkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ256rr, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ256rrk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZ256rrkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZrm, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZrmb, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZrmbk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZrmbkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZrmk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZrmkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZrr, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZrrb, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZrrbk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZrrbkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZrrk, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSZrrkz, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSrm, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINPSrr, X86_INS_VMINPS: vminps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDZrm, X86_INS_VMINSD: vminsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDZrm_Int, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDZrm_Intk, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDZrm_Intkz, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDZrr, X86_INS_VMINSD: vminsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDZrr_Int, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDZrr_Intk, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDZrr_Intkz, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDZrrb_Int, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDZrrb_Intk, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDZrrb_Intkz, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDrm, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDrm_Int, X86_INS_VMINSD: vminsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VMINSDrr, X86_INS_VMINSD: vminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSDrr_Int, X86_INS_VMINSD: vminsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSZrm, X86_INS_VMINSS: vminss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSZrm_Int, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSZrm_Intk, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSZrm_Intkz, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSZrr, X86_INS_VMINSS: vminss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSZrr_Int, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSZrr_Intk, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSZrr_Intkz, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSZrrb_Int, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSZrrb_Intk, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSZrrb_Intkz, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSrm, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSrm_Int, X86_INS_VMINSS: vminss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VMINSSrr, X86_INS_VMINSS: vminss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMINSSrr_Int, X86_INS_VMINSS: vminss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMLAUNCH, X86_INS_VMLAUNCH: vmlaunch */ + 0, + { 0 } +}, + +{ /* X86_VMLOAD32, X86_INS_VMLOAD: vmload */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMLOAD64, X86_INS_VMLOAD: vmload */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMMCALL, X86_INS_VMMCALL: vmmcall */ + 0, + { 0 } +}, + +{ /* X86_VMOV64toPQIZrm, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOV64toPQIZrr, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOV64toPQIrm, X86_INS_VMOVQ: vmovq $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOV64toPQIrr, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOV64toSDZrm, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOV64toSDZrr, X86_INS_VMOVQ: vmovq $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOV64toSDrm, X86_INS_VMOVQ: vmovq $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOV64toSDrr, X86_INS_VMOVQ: vmovq $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDYmr, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDYrm, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDYrr, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDYrr_REV, X86_INS_VMOVAPD: vmovapd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ128mr, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ128mrk, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ128rm, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ128rmk, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ128rmkz, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ128rr, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ128rr_REV, X86_INS_VMOVAPD: vmovapd */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPDZ128rrk, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ128rrk_REV, X86_INS_VMOVAPD: vmovapd */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPDZ128rrkz, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ128rrkz_REV, X86_INS_VMOVAPD: vmovapd */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPDZ256mr, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ256mrk, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ256rm, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ256rmk, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ256rmkz, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ256rr, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ256rr_REV, X86_INS_VMOVAPD: vmovapd */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPDZ256rrk, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ256rrk_REV, X86_INS_VMOVAPD: vmovapd */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPDZ256rrkz, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZ256rrkz_REV, X86_INS_VMOVAPD: vmovapd */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPDZmr, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZmrk, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZrm, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZrmk, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZrmkz, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZrr, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZrr_REV, X86_INS_VMOVAPD: vmovapd */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPDZrrk, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZrrk_REV, X86_INS_VMOVAPD: vmovapd */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPDZrrkz, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDZrrkz_REV, X86_INS_VMOVAPD: vmovapd */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPDmr, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDrm, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDrr, X86_INS_VMOVAPD: vmovapd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPDrr_REV, X86_INS_VMOVAPD: vmovapd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSYmr, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSYrm, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSYrr, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSYrr_REV, X86_INS_VMOVAPS: vmovaps $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ128mr, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ128mrk, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ128rm, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ128rmk, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ128rmkz, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ128rr, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ128rr_REV, X86_INS_VMOVAPS: vmovaps */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPSZ128rrk, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ128rrk_REV, X86_INS_VMOVAPS: vmovaps */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPSZ128rrkz, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ128rrkz_REV, X86_INS_VMOVAPS: vmovaps */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPSZ256mr, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ256mrk, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ256rm, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ256rmk, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ256rmkz, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ256rr, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ256rr_REV, X86_INS_VMOVAPS: vmovaps */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPSZ256rrk, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ256rrk_REV, X86_INS_VMOVAPS: vmovaps */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPSZ256rrkz, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZ256rrkz_REV, X86_INS_VMOVAPS: vmovaps */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPSZmr, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZmrk, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZrm, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZrmk, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZrmkz, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZrr, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZrr_REV, X86_INS_VMOVAPS: vmovaps */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPSZrrk, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZrrk_REV, X86_INS_VMOVAPS: vmovaps */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPSZrrkz, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSZrrkz_REV, X86_INS_VMOVAPS: vmovaps */ + 0, + { 0 } +}, + +{ /* X86_VMOVAPSmr, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSrm, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSrr, X86_INS_VMOVAPS: vmovaps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVAPSrr_REV, X86_INS_VMOVAPS: vmovaps $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPYrm, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPYrr, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZ128rm, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZ128rmk, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZ128rmkz, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZ128rr, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZ128rrk, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZ128rrkz, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZ256rm, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZ256rmk, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZ256rmkz, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZ256rr, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZ256rrk, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZ256rrkz, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZrm, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZrmk, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZrmkz, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZrr, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZrrk, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPZrrkz, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPrm, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDDUPrr, X86_INS_VMOVDDUP: vmovddup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDI2PDIZrm, X86_INS_VMOVD: vmovd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDI2PDIZrr, X86_INS_VMOVD: vmovd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDI2PDIrm, X86_INS_VMOVD: vmovd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDI2PDIrr, X86_INS_VMOVD: vmovd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDI2SSZrm, X86_INS_VMOVD: vmovd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDI2SSZrr, X86_INS_VMOVD: vmovd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDI2SSrm, X86_INS_VMOVD: vmovd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDI2SSrr, X86_INS_VMOVD: vmovd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z128mr, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z128mrk, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z128rm, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z128rmk, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z128rmkz, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z128rr, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z128rr_REV, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA32Z128rrk, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z128rrk_REV, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA32Z128rrkz, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z128rrkz_REV, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA32Z256mr, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z256mrk, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z256rm, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z256rmk, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z256rmkz, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z256rr, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z256rr_REV, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA32Z256rrk, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z256rrk_REV, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA32Z256rrkz, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Z256rrkz_REV, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA32Zmr, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Zmrk, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Zrm, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Zrmk, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Zrmkz, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Zrr, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Zrr_REV, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA32Zrrk, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Zrrk_REV, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA32Zrrkz, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA32Zrrkz_REV, X86_INS_VMOVDQA32: vmovdqa32 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA64Z128mr, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z128mrk, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z128rm, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z128rmk, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z128rmkz, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z128rr, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z128rr_REV, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA64Z128rrk, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z128rrk_REV, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA64Z128rrkz, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z128rrkz_REV, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA64Z256mr, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z256mrk, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z256rm, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z256rmk, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z256rmkz, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z256rr, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z256rr_REV, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA64Z256rrk, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z256rrk_REV, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA64Z256rrkz, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Z256rrkz_REV, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA64Zmr, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Zmrk, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Zrm, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Zrmk, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Zrmkz, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Zrr, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Zrr_REV, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA64Zrrk, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Zrrk_REV, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQA64Zrrkz, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQA64Zrrkz_REV, X86_INS_VMOVDQA64: vmovdqa64 */ + 0, + { 0 } +}, + +{ /* X86_VMOVDQAYmr, X86_INS_VMOVDQA: vmovdqa */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQAYrm, X86_INS_VMOVDQA: vmovdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQAYrr, X86_INS_VMOVDQA: vmovdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQAYrr_REV, X86_INS_VMOVDQA: vmovdqa $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQAmr, X86_INS_VMOVDQA: vmovdqa */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQArm, X86_INS_VMOVDQA: vmovdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQArr, X86_INS_VMOVDQA: vmovdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQArr_REV, X86_INS_VMOVDQA: vmovdqa $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z128mr, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z128mrk, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z128rm, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z128rmk, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z128rmkz, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z128rr, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z128rr_REV, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z128rrk, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z128rrk_REV, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z128rrkz, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z128rrkz_REV, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z256mr, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z256mrk, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z256rm, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z256rmk, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z256rmkz, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z256rr, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z256rr_REV, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z256rrk, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z256rrk_REV, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z256rrkz, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Z256rrkz_REV, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Zmr, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Zmrk, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Zrm, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Zrmk, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Zrmkz, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Zrr, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Zrr_REV, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Zrrk, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Zrrk_REV, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Zrrkz, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU16Zrrkz_REV, X86_INS_VMOVDQU16: vmovdqu16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z128mr, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z128mrk, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z128rm, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z128rmk, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z128rmkz, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z128rr, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z128rr_REV, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z128rrk, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z128rrk_REV, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z128rrkz, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z128rrkz_REV, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z256mr, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z256mrk, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z256rm, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z256rmk, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z256rmkz, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z256rr, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z256rr_REV, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z256rrk, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z256rrk_REV, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z256rrkz, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Z256rrkz_REV, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Zmr, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Zmrk, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Zrm, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Zrmk, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Zrmkz, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Zrr, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Zrr_REV, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Zrrk, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Zrrk_REV, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Zrrkz, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU32Zrrkz_REV, X86_INS_VMOVDQU32: vmovdqu32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z128mr, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z128mrk, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z128rm, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z128rmk, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z128rmkz, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z128rr, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z128rr_REV, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z128rrk, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z128rrk_REV, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z128rrkz, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z128rrkz_REV, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z256mr, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z256mrk, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z256rm, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z256rmk, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z256rmkz, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z256rr, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z256rr_REV, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z256rrk, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z256rrk_REV, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z256rrkz, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Z256rrkz_REV, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Zmr, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Zmrk, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Zrm, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Zrmk, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Zrmkz, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Zrr, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Zrr_REV, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Zrrk, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Zrrk_REV, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Zrrkz, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU64Zrrkz_REV, X86_INS_VMOVDQU64: vmovdqu64 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z128mr, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z128mrk, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z128rm, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z128rmk, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z128rmkz, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z128rr, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z128rr_REV, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z128rrk, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z128rrk_REV, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z128rrkz, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z128rrkz_REV, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z256mr, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z256mrk, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z256rm, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z256rmk, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z256rmkz, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z256rr, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z256rr_REV, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z256rrk, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z256rrk_REV, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z256rrkz, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Z256rrkz_REV, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Zmr, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Zmrk, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Zrm, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Zrmk, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Zrmkz, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Zrr, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Zrr_REV, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Zrrk, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Zrrk_REV, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Zrrkz, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQU8Zrrkz_REV, X86_INS_VMOVDQU8: vmovdqu8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQUYmr, X86_INS_VMOVDQU: vmovdqu */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQUYrm, X86_INS_VMOVDQU: vmovdqu */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQUYrr, X86_INS_VMOVDQU: vmovdqu */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQUYrr_REV, X86_INS_VMOVDQU: vmovdqu $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQUmr, X86_INS_VMOVDQU: vmovdqu */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQUrm, X86_INS_VMOVDQU: vmovdqu */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQUrr, X86_INS_VMOVDQU: vmovdqu */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVDQUrr_REV, X86_INS_VMOVDQU: vmovdqu $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVHLPSZrr, X86_INS_VMOVHLPS: vmovhlps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVHLPSrr, X86_INS_VMOVHLPS: vmovhlps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVHPDZ128mr, X86_INS_VMOVHPD: vmovhpd */ + 0, + { 0 } +}, + +{ /* X86_VMOVHPDZ128rm, X86_INS_VMOVHPD: vmovhpd */ + 0, + { 0 } +}, + +{ /* X86_VMOVHPDmr, X86_INS_VMOVHPD: vmovhpd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVHPDrm, X86_INS_VMOVHPD: vmovhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVHPSZ128mr, X86_INS_VMOVHPS: vmovhps */ + 0, + { 0 } +}, + +{ /* X86_VMOVHPSZ128rm, X86_INS_VMOVHPS: vmovhps */ + 0, + { 0 } +}, + +{ /* X86_VMOVHPSmr, X86_INS_VMOVHPS: vmovhps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVHPSrm, X86_INS_VMOVHPS: vmovhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVLHPSZrr, X86_INS_VMOVLHPS: vmovlhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVLHPSrr, X86_INS_VMOVLHPS: vmovlhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVLPDZ128mr, X86_INS_VMOVLPD: vmovlpd */ + 0, + { 0 } +}, + +{ /* X86_VMOVLPDZ128rm, X86_INS_VMOVLPD: vmovlpd */ + 0, + { 0 } +}, + +{ /* X86_VMOVLPDmr, X86_INS_VMOVLPD: vmovlpd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVLPDrm, X86_INS_VMOVLPD: vmovlpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVLPSZ128mr, X86_INS_VMOVLPS: vmovlps */ + 0, + { 0 } +}, + +{ /* X86_VMOVLPSZ128rm, X86_INS_VMOVLPS: vmovlps */ + 0, + { 0 } +}, + +{ /* X86_VMOVLPSmr, X86_INS_VMOVLPS: vmovlps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVLPSrm, X86_INS_VMOVLPS: vmovlps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVMSKPDYrr, X86_INS_VMOVMSKPD: vmovmskpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVMSKPDrr, X86_INS_VMOVMSKPD: vmovmskpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVMSKPSYrr, X86_INS_VMOVMSKPS: vmovmskps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVMSKPSrr, X86_INS_VMOVMSKPS: vmovmskps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTDQAYrm, X86_INS_VMOVNTDQA: vmovntdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTDQAZ128rm, X86_INS_VMOVNTDQA: vmovntdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTDQAZ256rm, X86_INS_VMOVNTDQA: vmovntdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTDQAZrm, X86_INS_VMOVNTDQA: vmovntdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTDQArm, X86_INS_VMOVNTDQA: vmovntdqa */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTDQYmr, X86_INS_VMOVNTDQ: vmovntdq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTDQZ128mr, X86_INS_VMOVNTDQ: vmovntdq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTDQZ256mr, X86_INS_VMOVNTDQ: vmovntdq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTDQZmr, X86_INS_VMOVNTDQ: vmovntdq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTDQmr, X86_INS_VMOVNTDQ: vmovntdq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTPDYmr, X86_INS_VMOVNTPD: vmovntpd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTPDZ128mr, X86_INS_VMOVNTPD: vmovntpd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTPDZ256mr, X86_INS_VMOVNTPD: vmovntpd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTPDZmr, X86_INS_VMOVNTPD: vmovntpd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTPDmr, X86_INS_VMOVNTPD: vmovntpd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTPSYmr, X86_INS_VMOVNTPS: vmovntps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTPSZ128mr, X86_INS_VMOVNTPS: vmovntps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTPSZ256mr, X86_INS_VMOVNTPS: vmovntps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTPSZmr, X86_INS_VMOVNTPS: vmovntps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVNTPSmr, X86_INS_VMOVNTPS: vmovntps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVPDI2DIZmr, X86_INS_VMOVD: vmovd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVPDI2DIZrr, X86_INS_VMOVD: vmovd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVPDI2DImr, X86_INS_VMOVD: vmovd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVPDI2DIrr, X86_INS_VMOVD: vmovd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVPQI2QIZmr, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVPQI2QIZrr, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVPQI2QImr, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVPQI2QIrr, X86_INS_VMOVQ: vmovq $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVPQIto64Zmr, X86_INS_VMOVQ: vmovq $dst $src */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVPQIto64Zrr, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVPQIto64mr, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVPQIto64rr, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVQI2PQIZrm, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVQI2PQIrm, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDZmr, X86_INS_VMOVSD: vmovsd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDZmrk, X86_INS_VMOVSD: vmovsd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDZrm, X86_INS_VMOVSD: vmovsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDZrmk, X86_INS_VMOVSD: vmovsd */ + 0, + { 0 } +}, + +{ /* X86_VMOVSDZrmkz, X86_INS_VMOVSD: vmovsd */ + 0, + { 0 } +}, + +{ /* X86_VMOVSDZrr, X86_INS_VMOVSD: vmovsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDZrr_REV, X86_INS_VMOVSD: vmovsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDZrrk, X86_INS_VMOVSD: vmovsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDZrrk_REV, X86_INS_VMOVSD: vmovsd */ + 0, + { 0 } +}, + +{ /* X86_VMOVSDZrrkz, X86_INS_VMOVSD: vmovsd */ + 0, + { 0 } +}, + +{ /* X86_VMOVSDZrrkz_REV, X86_INS_VMOVSD: vmovsd */ + 0, + { 0 } +}, + +{ /* X86_VMOVSDmr, X86_INS_VMOVSD: vmovsd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDrm, X86_INS_VMOVSD: vmovsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDrr, X86_INS_VMOVSD: vmovsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDrr_REV, X86_INS_VMOVSD: vmovsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDto64Zmr, X86_INS_VMOVQ: vmovq $dst $src */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDto64Zrr, X86_INS_VMOVQ: vmovq $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDto64mr, X86_INS_VMOVQ: vmovq $dst $src */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSDto64rr, X86_INS_VMOVQ: vmovq $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPYrm, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPYrr, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZ128rm, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZ128rmk, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZ128rmkz, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZ128rr, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZ128rrk, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZ128rrkz, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZ256rm, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZ256rmk, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZ256rmkz, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZ256rr, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZ256rrk, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZ256rrkz, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZrm, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZrmk, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZrmkz, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZrr, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZrrk, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPZrrkz, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPrm, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSHDUPrr, X86_INS_VMOVSHDUP: vmovshdup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPYrm, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPYrr, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZ128rm, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZ128rmk, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZ128rmkz, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZ128rr, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZ128rrk, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZ128rrkz, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZ256rm, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZ256rmk, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZ256rmkz, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZ256rr, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZ256rrk, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZ256rrkz, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZrm, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZrmk, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZrmkz, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZrr, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZrrk, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPZrrkz, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPrm, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSLDUPrr, X86_INS_VMOVSLDUP: vmovsldup */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSS2DIZmr, X86_INS_VMOVD: vmovd $dst $src */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSS2DIZrr, X86_INS_VMOVD: vmovd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSS2DImr, X86_INS_VMOVD: vmovd $dst $src */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSS2DIrr, X86_INS_VMOVD: vmovd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSSZmr, X86_INS_VMOVSS: vmovss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSSZmrk, X86_INS_VMOVSS: vmovss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSSZrm, X86_INS_VMOVSS: vmovss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSSZrmk, X86_INS_VMOVSS: vmovss */ + 0, + { 0 } +}, + +{ /* X86_VMOVSSZrmkz, X86_INS_VMOVSS: vmovss */ + 0, + { 0 } +}, + +{ /* X86_VMOVSSZrr, X86_INS_VMOVSS: vmovss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSSZrr_REV, X86_INS_VMOVSS: vmovss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSSZrrk, X86_INS_VMOVSS: vmovss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSSZrrk_REV, X86_INS_VMOVSS: vmovss */ + 0, + { 0 } +}, + +{ /* X86_VMOVSSZrrkz, X86_INS_VMOVSS: vmovss */ + 0, + { 0 } +}, + +{ /* X86_VMOVSSZrrkz_REV, X86_INS_VMOVSS: vmovss */ + 0, + { 0 } +}, + +{ /* X86_VMOVSSmr, X86_INS_VMOVSS: vmovss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSSrm, X86_INS_VMOVSS: vmovss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSSrr, X86_INS_VMOVSS: vmovss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVSSrr_REV, X86_INS_VMOVSS: vmovss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDYmr, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDYrm, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDYrr, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDYrr_REV, X86_INS_VMOVUPD: vmovupd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ128mr, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ128mrk, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ128rm, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ128rmk, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ128rmkz, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ128rr, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ128rr_REV, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ128rrk, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ128rrk_REV, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ128rrkz, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ128rrkz_REV, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ256mr, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ256mrk, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ256rm, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ256rmk, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ256rmkz, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ256rr, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ256rr_REV, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ256rrk, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ256rrk_REV, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ256rrkz, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZ256rrkz_REV, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZmr, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZmrk, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZrm, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZrmk, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZrmkz, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZrr, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZrr_REV, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZrrk, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZrrk_REV, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZrrkz, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDZrrkz_REV, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDmr, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDrm, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDrr, X86_INS_VMOVUPD: vmovupd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPDrr_REV, X86_INS_VMOVUPD: vmovupd $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSYmr, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSYrm, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSYrr, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSYrr_REV, X86_INS_VMOVUPS: vmovups $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ128mr, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ128mrk, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ128rm, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ128rmk, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ128rmkz, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ128rr, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ128rr_REV, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ128rrk, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ128rrk_REV, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ128rrkz, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ128rrkz_REV, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ256mr, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ256mrk, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ256rm, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ256rmk, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ256rmkz, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ256rr, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ256rr_REV, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ256rrk, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ256rrk_REV, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ256rrkz, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZ256rrkz_REV, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZmr, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZmrk, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZrm, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZrmk, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZrmkz, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZrr, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZrr_REV, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZrrk, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZrrk_REV, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZrrkz, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSZrrkz_REV, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSmr, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSrm, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSrr, X86_INS_VMOVUPS: vmovups */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVUPSrr_REV, X86_INS_VMOVUPS: vmovups $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVZPQILo2PQIZrr, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMOVZPQILo2PQIrr, X86_INS_VMOVQ: vmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMPSADBWYrmi, X86_INS_VMPSADBW: vmpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VMPSADBWYrri, X86_INS_VMPSADBW: vmpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VMPSADBWrmi, X86_INS_VMPSADBW: vmpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VMPSADBWrri, X86_INS_VMPSADBW: vmpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VMPTRLDm, X86_INS_VMPTRLD: vmptrld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMPTRSTm, X86_INS_VMPTRST: vmptrst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_VMREAD32mr, X86_INS_VMREAD: vmread */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMREAD32rr, X86_INS_VMREAD: vmread */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMREAD64mr, X86_INS_VMREAD: vmread */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMREAD64rr, X86_INS_VMREAD: vmread */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMRESUME, X86_INS_VMRESUME: vmresume */ + 0, + { 0 } +}, + +{ /* X86_VMRUN32, X86_INS_VMRUN: vmrun */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMRUN64, X86_INS_VMRUN: vmrun */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMSAVE32, X86_INS_VMSAVE: vmsave */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMSAVE64, X86_INS_VMSAVE: vmsave */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDYrm, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDYrr, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ128rm, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ128rmb, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ128rmbk, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ128rmbkz, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ128rmk, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ128rmkz, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ128rr, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ128rrk, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ128rrkz, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ256rm, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ256rmb, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ256rmbk, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ256rmbkz, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ256rmk, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ256rmkz, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ256rr, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ256rrk, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZ256rrkz, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZrm, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZrmb, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZrmbk, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZrmbkz, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZrmk, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZrmkz, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZrr, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZrrb, X86_INS_VMULPD: vmulpd */ + 0, + { 0 } +}, + +{ /* X86_VMULPDZrrbk, X86_INS_VMULPD: vmulpd */ + 0, + { 0 } +}, + +{ /* X86_VMULPDZrrbkz, X86_INS_VMULPD: vmulpd */ + 0, + { 0 } +}, + +{ /* X86_VMULPDZrrk, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDZrrkz, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDrm, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPDrr, X86_INS_VMULPD: vmulpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSYrm, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSYrr, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ128rm, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ128rmb, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ128rmbk, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ128rmbkz, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ128rmk, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ128rmkz, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ128rr, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ128rrk, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ128rrkz, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ256rm, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ256rmb, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ256rmbk, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ256rmbkz, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ256rmk, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ256rmkz, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ256rr, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ256rrk, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZ256rrkz, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZrm, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZrmb, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZrmbk, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZrmbkz, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZrmk, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZrmkz, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZrr, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZrrb, X86_INS_VMULPS: vmulps */ + 0, + { 0 } +}, + +{ /* X86_VMULPSZrrbk, X86_INS_VMULPS: vmulps */ + 0, + { 0 } +}, + +{ /* X86_VMULPSZrrbkz, X86_INS_VMULPS: vmulps */ + 0, + { 0 } +}, + +{ /* X86_VMULPSZrrk, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSZrrkz, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSrm, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULPSrr, X86_INS_VMULPS: vmulps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDZrm, X86_INS_VMULSD: vmulsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDZrm_Int, X86_INS_VMULSD: vmulsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDZrm_Intk, X86_INS_VMULSD: vmulsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDZrm_Intkz, X86_INS_VMULSD: vmulsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDZrr, X86_INS_VMULSD: vmulsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDZrr_Int, X86_INS_VMULSD: vmulsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDZrr_Intk, X86_INS_VMULSD: vmulsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDZrr_Intkz, X86_INS_VMULSD: vmulsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDZrrb_Int, X86_INS_VMULSD: vmulsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDZrrb_Intk, X86_INS_VMULSD: vmulsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDZrrb_Intkz, X86_INS_VMULSD: vmulsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDrm, X86_INS_VMULSD: vmulsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDrm_Int, X86_INS_VMULSD: vmulsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VMULSDrr, X86_INS_VMULSD: vmulsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSDrr_Int, X86_INS_VMULSD: vmulsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSZrm, X86_INS_VMULSS: vmulss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSZrm_Int, X86_INS_VMULSS: vmulss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSZrm_Intk, X86_INS_VMULSS: vmulss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSZrm_Intkz, X86_INS_VMULSS: vmulss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSZrr, X86_INS_VMULSS: vmulss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSZrr_Int, X86_INS_VMULSS: vmulss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSZrr_Intk, X86_INS_VMULSS: vmulss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSZrr_Intkz, X86_INS_VMULSS: vmulss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSZrrb_Int, X86_INS_VMULSS: vmulss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSZrrb_Intk, X86_INS_VMULSS: vmulss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSZrrb_Intkz, X86_INS_VMULSS: vmulss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSrm, X86_INS_VMULSS: vmulss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSrm_Int, X86_INS_VMULSS: vmulss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VMULSSrr, X86_INS_VMULSS: vmulss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMULSSrr_Int, X86_INS_VMULSS: vmulss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VMWRITE32rm, X86_INS_VMWRITE: vmwrite */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMWRITE32rr, X86_INS_VMWRITE: vmwrite */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMWRITE64rm, X86_INS_VMWRITE: vmwrite */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMWRITE64rr, X86_INS_VMWRITE: vmwrite */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMXOFF, X86_INS_VMXOFF: vmxoff */ + 0, + { 0 } +}, + +{ /* X86_VMXON, X86_INS_VMXON: vmxon */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VORPDYrm, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDYrr, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ128rm, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ128rmb, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ128rmbk, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ128rmbkz, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ128rmk, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ128rmkz, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ128rr, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ128rrk, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ128rrkz, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ256rm, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ256rmb, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ256rmbk, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ256rmbkz, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ256rmk, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ256rmkz, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ256rr, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ256rrk, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZ256rrkz, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZrm, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZrmb, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZrmbk, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZrmbkz, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZrmk, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZrmkz, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZrr, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZrrk, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDZrrkz, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDrm, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPDrr, X86_INS_VORPD: vorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSYrm, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSYrr, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ128rm, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ128rmb, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ128rmbk, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ128rmbkz, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ128rmk, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ128rmkz, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ128rr, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ128rrk, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ128rrkz, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ256rm, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ256rmb, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ256rmbk, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ256rmbkz, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ256rmk, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ256rmkz, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ256rr, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ256rrk, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZ256rrkz, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZrm, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZrmb, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZrmbk, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZrmbkz, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZrmk, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZrmkz, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZrr, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZrrk, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSZrrkz, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSrm, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VORPSrr, X86_INS_VORPS: vorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VP4DPWSSDSrm, X86_INS_VP4DPWSSDS: vp4dpwssds */ + 0, + { 0 } +}, + +{ /* X86_VP4DPWSSDSrmk, X86_INS_VP4DPWSSDS: vp4dpwssds */ + 0, + { 0 } +}, + +{ /* X86_VP4DPWSSDSrmkz, X86_INS_VP4DPWSSDS: vp4dpwssds */ + 0, + { 0 } +}, + +{ /* X86_VP4DPWSSDrm, X86_INS_VP4DPWSSD: vp4dpwssd */ + 0, + { 0 } +}, + +{ /* X86_VP4DPWSSDrmk, X86_INS_VP4DPWSSD: vp4dpwssd */ + 0, + { 0 } +}, + +{ /* X86_VP4DPWSSDrmkz, X86_INS_VP4DPWSSD: vp4dpwssd */ + 0, + { 0 } +}, + +{ /* X86_VPABSBYrm, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBYrr, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZ128rm, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZ128rmk, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZ128rmkz, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZ128rr, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZ128rrk, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZ128rrkz, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZ256rm, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZ256rmk, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZ256rmkz, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZ256rr, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZ256rrk, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZ256rrkz, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZrm, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZrmk, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZrmkz, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZrr, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZrrk, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBZrrkz, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBrm, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSBrr, X86_INS_VPABSB: vpabsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDYrm, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDYrr, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ128rm, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ128rmb, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ128rmbk, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ128rmbkz, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ128rmk, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ128rmkz, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ128rr, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ128rrk, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ128rrkz, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ256rm, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ256rmb, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ256rmbk, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ256rmbkz, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ256rmk, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ256rmkz, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ256rr, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ256rrk, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZ256rrkz, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZrm, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZrmb, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZrmbk, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZrmbkz, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZrmk, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZrmkz, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZrr, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZrrk, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDZrrkz, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDrm, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSDrr, X86_INS_VPABSD: vpabsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ128rm, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ128rmb, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ128rmbk, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ128rmbkz, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ128rmk, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ128rmkz, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ128rr, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ128rrk, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ128rrkz, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ256rm, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ256rmb, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ256rmbk, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ256rmbkz, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ256rmk, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ256rmkz, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ256rr, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ256rrk, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZ256rrkz, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZrm, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZrmb, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZrmbk, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZrmbkz, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZrmk, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZrmkz, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZrr, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZrrk, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSQZrrkz, X86_INS_VPABSQ: vpabsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWYrm, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWYrr, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZ128rm, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZ128rmk, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZ128rmkz, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZ128rr, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZ128rrk, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZ128rrkz, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZ256rm, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZ256rmk, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZ256rmkz, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZ256rr, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZ256rrk, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZ256rrkz, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZrm, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZrmk, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZrmkz, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZrr, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZrrk, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWZrrkz, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWrm, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPABSWrr, X86_INS_VPABSW: vpabsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWYrm, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWYrr, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ128rm, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ128rmb, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ128rmbk, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ128rmbkz, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ128rmk, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ128rmkz, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ128rr, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ128rrk, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ128rrkz, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ256rm, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ256rmb, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ256rmbk, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ256rmbkz, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ256rmk, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ256rmkz, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ256rr, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ256rrk, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZ256rrkz, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZrm, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZrmb, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZrmbk, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZrmbkz, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZrmk, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZrmkz, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZrr, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZrrk, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWZrrkz, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWrm, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSDWrr, X86_INS_VPACKSSDW: vpackssdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBYrm, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBYrr, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZ128rm, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZ128rmk, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZ128rmkz, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZ128rr, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZ128rrk, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZ128rrkz, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZ256rm, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZ256rmk, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZ256rmkz, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZ256rr, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZ256rrk, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZ256rrkz, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZrm, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZrmk, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZrmkz, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZrr, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZrrk, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBZrrkz, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBrm, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKSSWBrr, X86_INS_VPACKSSWB: vpacksswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWYrm, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWYrr, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ128rm, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ128rmb, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ128rmbk, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ128rmbkz, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ128rmk, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ128rmkz, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ128rr, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ128rrk, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ128rrkz, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ256rm, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ256rmb, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ256rmbk, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ256rmbkz, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ256rmk, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ256rmkz, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ256rr, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ256rrk, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZ256rrkz, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZrm, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZrmb, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZrmbk, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZrmbkz, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZrmk, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZrmkz, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZrr, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZrrk, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWZrrkz, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWrm, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSDWrr, X86_INS_VPACKUSDW: vpackusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBYrm, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBYrr, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZ128rm, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZ128rmk, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZ128rmkz, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZ128rr, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZ128rrk, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZ128rrkz, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZ256rm, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZ256rmk, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZ256rmkz, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZ256rr, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZ256rrk, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZ256rrkz, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZrm, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZrmk, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZrmkz, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZrr, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZrrk, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBZrrkz, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBrm, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPACKUSWBrr, X86_INS_VPACKUSWB: vpackuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBYrm, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBYrr, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZ128rm, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZ128rmk, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZ128rmkz, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZ128rr, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZ128rrk, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZ128rrkz, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZ256rm, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZ256rmk, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZ256rmkz, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZ256rr, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZ256rrk, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZ256rrkz, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZrm, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZrmk, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZrmkz, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZrr, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZrrk, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBZrrkz, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBrm, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDBrr, X86_INS_VPADDB: vpaddb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDYrm, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDYrr, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ128rm, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ128rmb, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ128rmbk, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ128rmbkz, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ128rmk, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ128rmkz, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ128rr, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ128rrk, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ128rrkz, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ256rm, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ256rmb, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ256rmbk, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ256rmbkz, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ256rmk, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ256rmkz, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ256rr, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ256rrk, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZ256rrkz, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZrm, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZrmb, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZrmbk, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZrmbkz, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZrmk, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZrmkz, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZrr, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZrrk, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDZrrkz, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDrm, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDDrr, X86_INS_VPADDD: vpaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQYrm, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQYrr, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ128rm, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ128rmb, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ128rmbk, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ128rmbkz, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ128rmk, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ128rmkz, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ128rr, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ128rrk, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ128rrkz, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ256rm, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ256rmb, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ256rmbk, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ256rmbkz, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ256rmk, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ256rmkz, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ256rr, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ256rrk, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZ256rrkz, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZrm, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZrmb, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZrmbk, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZrmbkz, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZrmk, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZrmkz, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZrr, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZrrk, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQZrrkz, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQrm, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDQrr, X86_INS_VPADDQ: vpaddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBYrm, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBYrr, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZ128rm, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZ128rmk, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZ128rmkz, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZ128rr, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZ128rrk, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZ128rrkz, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZ256rm, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZ256rmk, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZ256rmkz, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZ256rr, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZ256rrk, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZ256rrkz, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZrm, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZrmk, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZrmkz, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZrr, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZrrk, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBZrrkz, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBrm, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSBrr, X86_INS_VPADDSB: vpaddsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWYrm, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWYrr, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZ128rm, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZ128rmk, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZ128rmkz, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZ128rr, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZ128rrk, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZ128rrkz, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZ256rm, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZ256rmk, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZ256rmkz, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZ256rr, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZ256rrk, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZ256rrkz, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZrm, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZrmk, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZrmkz, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZrr, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZrrk, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWZrrkz, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWrm, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDSWrr, X86_INS_VPADDSW: vpaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBYrm, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBYrr, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZ128rm, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZ128rmk, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZ128rmkz, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZ128rr, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZ128rrk, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZ128rrkz, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZ256rm, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZ256rmk, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZ256rmkz, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZ256rr, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZ256rrk, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZ256rrkz, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZrm, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZrmk, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZrmkz, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZrr, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZrrk, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBZrrkz, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBrm, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSBrr, X86_INS_VPADDUSB: vpaddusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWYrm, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWYrr, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZ128rm, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZ128rmk, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZ128rmkz, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZ128rr, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZ128rrk, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZ128rrkz, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZ256rm, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZ256rmk, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZ256rmkz, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZ256rr, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZ256rrk, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZ256rrkz, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZrm, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZrmk, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZrmkz, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZrr, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZrrk, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWZrrkz, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWrm, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDUSWrr, X86_INS_VPADDUSW: vpaddusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWYrm, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWYrr, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZ128rm, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZ128rmk, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZ128rmkz, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZ128rr, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZ128rrk, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZ128rrkz, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZ256rm, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZ256rmk, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZ256rmkz, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZ256rr, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZ256rrk, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZ256rrkz, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZrm, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZrmk, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZrmkz, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZrr, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZrrk, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWZrrkz, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWrm, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPADDWrr, X86_INS_VPADDW: vpaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPALIGNRYrmi, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRYrri, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZ128rmi, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZ128rmik, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZ128rmikz, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZ128rri, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZ128rrik, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZ128rrikz, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZ256rmi, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZ256rmik, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZ256rmikz, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZ256rri, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZ256rrik, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZ256rrikz, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZrmi, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZrmik, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZrmikz, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZrri, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZrrik, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRZrrikz, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRrmi, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPALIGNRrri, X86_INS_VPALIGNR: vpalignr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPANDDZ128rm, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ128rmb, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ128rmbk, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ128rmbkz, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ128rmk, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ128rmkz, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ128rr, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ128rrk, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ128rrkz, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ256rm, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ256rmb, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ256rmbk, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ256rmbkz, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ256rmk, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ256rmkz, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ256rr, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ256rrk, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZ256rrkz, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZrm, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZrmb, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZrmbk, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZrmbkz, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZrmk, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZrmkz, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZrr, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZrrk, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDDZrrkz, X86_INS_VPANDD: vpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ128rm, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ128rmb, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ128rmbk, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ128rmbkz, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ128rmk, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ128rmkz, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ128rr, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ128rrk, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ128rrkz, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ256rm, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ256rmb, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ256rmbk, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ256rmbkz, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ256rmk, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ256rmkz, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ256rr, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ256rrk, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZ256rrkz, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZrm, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZrmb, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZrmbk, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZrmbkz, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZrmk, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZrmkz, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZrr, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZrrk, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNDZrrkz, X86_INS_VPANDND: vpandnd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ128rm, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ128rmb, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ128rmbk, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ128rmbkz, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ128rmk, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ128rmkz, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ128rr, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ128rrk, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ128rrkz, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ256rm, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ256rmb, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ256rmbk, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ256rmbkz, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ256rmk, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ256rmkz, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ256rr, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ256rrk, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZ256rrkz, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZrm, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZrmb, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZrmbk, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZrmbkz, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZrmk, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZrmkz, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZrr, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZrrk, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNQZrrkz, X86_INS_VPANDNQ: vpandnq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNYrm, X86_INS_VPANDN: vpandn */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNYrr, X86_INS_VPANDN: vpandn */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNrm, X86_INS_VPANDN: vpandn */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDNrr, X86_INS_VPANDN: vpandn */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ128rm, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ128rmb, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ128rmbk, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ128rmbkz, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ128rmk, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ128rmkz, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ128rr, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ128rrk, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ128rrkz, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ256rm, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ256rmb, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ256rmbk, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ256rmbkz, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ256rmk, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ256rmkz, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ256rr, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ256rrk, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZ256rrkz, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZrm, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZrmb, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZrmbk, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZrmbkz, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZrmk, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZrmkz, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZrr, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZrrk, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDQZrrkz, X86_INS_VPANDQ: vpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDYrm, X86_INS_VPAND: vpand */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDYrr, X86_INS_VPAND: vpand */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDrm, X86_INS_VPAND: vpand */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPANDrr, X86_INS_VPAND: vpand */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBYrm, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBYrr, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZ128rm, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZ128rmk, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZ128rmkz, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZ128rr, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZ128rrk, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZ128rrkz, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZ256rm, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZ256rmk, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZ256rmkz, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZ256rr, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZ256rrk, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZ256rrkz, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZrm, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZrmk, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZrmkz, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZrr, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZrrk, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBZrrkz, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBrm, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGBrr, X86_INS_VPAVGB: vpavgb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWYrm, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWYrr, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZ128rm, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZ128rmk, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZ128rmkz, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZ128rr, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZ128rrk, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZ128rrkz, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZ256rm, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZ256rmk, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZ256rmkz, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZ256rr, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZ256rrk, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZ256rrkz, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZrm, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZrmk, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZrmkz, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZrr, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZrrk, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWZrrkz, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWrm, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPAVGWrr, X86_INS_VPAVGW: vpavgw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDDYrmi, X86_INS_VPBLENDD: vpblendd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPBLENDDYrri, X86_INS_VPBLENDD: vpblendd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPBLENDDrmi, X86_INS_VPBLENDD: vpblendd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPBLENDDrri, X86_INS_VPBLENDD: vpblendd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPBLENDMBZ128rm, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZ128rmk, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZ128rmkz, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZ128rr, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZ128rrk, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZ128rrkz, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZ256rm, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZ256rmk, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZ256rmkz, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZ256rr, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZ256rrk, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZ256rrkz, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZrm, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZrmk, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZrmkz, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZrr, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZrrk, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMBZrrkz, X86_INS_VPBLENDMB: vpblendmb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ128rm, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ128rmb, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ128rmbk, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ128rmbkz, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { 0 } +}, + +{ /* X86_VPBLENDMDZ128rmk, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ128rmkz, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ128rr, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ128rrk, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ128rrkz, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ256rm, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ256rmb, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ256rmbk, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ256rmbkz, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { 0 } +}, + +{ /* X86_VPBLENDMDZ256rmk, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ256rmkz, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ256rr, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ256rrk, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZ256rrkz, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZrm, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZrmb, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZrmbk, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZrmbkz, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { 0 } +}, + +{ /* X86_VPBLENDMDZrmk, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZrmkz, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZrr, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZrrk, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMDZrrkz, X86_INS_VPBLENDMD: vpblendmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ128rm, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ128rmb, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ128rmbk, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ128rmbkz, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { 0 } +}, + +{ /* X86_VPBLENDMQZ128rmk, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ128rmkz, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ128rr, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ128rrk, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ128rrkz, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ256rm, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ256rmb, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ256rmbk, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ256rmbkz, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { 0 } +}, + +{ /* X86_VPBLENDMQZ256rmk, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ256rmkz, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ256rr, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ256rrk, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZ256rrkz, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZrm, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZrmb, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZrmbk, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZrmbkz, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { 0 } +}, + +{ /* X86_VPBLENDMQZrmk, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZrmkz, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZrr, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZrrk, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMQZrrkz, X86_INS_VPBLENDMQ: vpblendmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZ128rm, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZ128rmk, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZ128rmkz, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZ128rr, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZ128rrk, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZ128rrkz, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZ256rm, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZ256rmk, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZ256rmkz, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZ256rr, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZ256rrk, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZ256rrkz, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZrm, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZrmk, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZrmkz, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZrr, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZrrk, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDMWZrrkz, X86_INS_VPBLENDMW: vpblendmw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDVBYrm, X86_INS_VPBLENDVB: vpblendvb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDVBYrr, X86_INS_VPBLENDVB: vpblendvb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDVBrm, X86_INS_VPBLENDVB: vpblendvb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDVBrr, X86_INS_VPBLENDVB: vpblendvb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPBLENDWYrmi, X86_INS_VPBLENDW: vpblendw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPBLENDWYrri, X86_INS_VPBLENDW: vpblendw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPBLENDWrmi, X86_INS_VPBLENDW: vpblendw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPBLENDWrri, X86_INS_VPBLENDW: vpblendw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPBROADCASTBYrm, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBYrr, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZ128m, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZ128mk, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZ128mkz, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZ128r, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZ128rk, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZ128rkz, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZ256m, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZ256mk, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZ256mkz, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZ256r, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZ256rk, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZ256rkz, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZm, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZmk, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZmkz, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZr, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZrk, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBZrkz, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBrZ128r, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBrZ128rk, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBrZ128rkz, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBrZ256r, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBrZ256rk, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBrZ256rkz, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBrZr, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBrZrk, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBrZrkz, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBrm, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTBrr, X86_INS_VPBROADCASTB: vpbroadcastb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDYrm, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDYrr, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDZ128m, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZ128mk, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZ128mkz, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZ128r, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZ128rk, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZ128rkz, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZ256m, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZ256mk, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZ256mkz, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZ256r, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZ256rk, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZ256rkz, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZm, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZmk, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZmkz, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZr, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZrk, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDZrkz, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTDrZ128r, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDrZ128rk, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDrZ128rkz, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDrZ256r, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDrZ256rk, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDrZ256rkz, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDrZr, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDrZrk, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDrZrkz, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDrm, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTDrr, X86_INS_VPBROADCASTD: vpbroadcastd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTMB2QZ128rr, X86_INS_VPBROADCASTMB2Q: vpbroadcastmb2q */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTMB2QZ256rr, X86_INS_VPBROADCASTMB2Q: vpbroadcastmb2q */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTMB2QZrr, X86_INS_VPBROADCASTMB2Q: vpbroadcastmb2q */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTMW2DZ128rr, X86_INS_VPBROADCASTMW2D: vpbroadcastmw2d */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTMW2DZ256rr, X86_INS_VPBROADCASTMW2D: vpbroadcastmw2d */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTMW2DZrr, X86_INS_VPBROADCASTMW2D: vpbroadcastmw2d */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQYrm, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQYrr, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQZ128m, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZ128mk, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZ128mkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZ128r, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZ128rk, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZ128rkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZ256m, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZ256mk, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZ256mkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZ256r, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZ256rk, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZ256rkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZm, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZmk, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZmkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZr, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZrk, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQZrkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { 0 } +}, + +{ /* X86_VPBROADCASTQrZ128r, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQrZ128rk, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQrZ128rkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQrZ256r, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQrZ256rk, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQrZ256rkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQrZr, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQrZrk, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQrZrkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQrm, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTQrr, X86_INS_VPBROADCASTQ: vpbroadcastq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWYrm, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWYrr, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZ128m, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZ128mk, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZ128mkz, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZ128r, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZ128rk, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZ128rkz, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZ256m, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZ256mk, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZ256mkz, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZ256r, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZ256rk, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZ256rkz, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZm, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZmk, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZmkz, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZr, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZrk, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWZrkz, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWrZ128r, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWrZ128rk, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWrZ128rkz, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWrZ256r, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWrZ256rk, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWrZ256rkz, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWrZr, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWrZrk, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWrZrkz, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWrm, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPBROADCASTWrr, X86_INS_VPBROADCASTW: vpbroadcastw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCLMULQDQYrm, X86_INS_VPCLMULQDQ: vpclmulqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCLMULQDQYrr, X86_INS_VPCLMULQDQ: vpclmulqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCLMULQDQZ128rm, X86_INS_VPCLMULQDQ: vpclmulqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCLMULQDQZ128rr, X86_INS_VPCLMULQDQ: vpclmulqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCLMULQDQZ256rm, X86_INS_VPCLMULQDQ: vpclmulqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCLMULQDQZ256rr, X86_INS_VPCLMULQDQ: vpclmulqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCLMULQDQZrm, X86_INS_VPCLMULQDQ: vpclmulqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCLMULQDQZrr, X86_INS_VPCLMULQDQ: vpclmulqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCLMULQDQrm, X86_INS_VPCLMULQDQ: vpclmulqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCLMULQDQrr, X86_INS_VPCLMULQDQ: vpclmulqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMOVYrmr, X86_INS_VPCMOV: vpcmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMOVYrrm, X86_INS_VPCMOV: vpcmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMOVYrrr, X86_INS_VPCMOV: vpcmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMOVYrrr_REV, X86_INS_VPCMOV: vpcmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMOVrmr, X86_INS_VPCMOV: vpcmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMOVrrm, X86_INS_VPCMOV: vpcmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMOVrrr, X86_INS_VPCMOV: vpcmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMOVrrr_REV, X86_INS_VPCMOV: vpcmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZ128rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZ128rmi_alt, X86_INS_VPCMPB: vpcmpb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPBZ128rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZ128rmik_alt, X86_INS_VPCMPB: vpcmpb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPBZ128rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZ128rri_alt, X86_INS_VPCMPB: vpcmpb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPBZ128rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZ128rrik_alt, X86_INS_VPCMPB: vpcmpb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPBZ256rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZ256rmi_alt, X86_INS_VPCMPB: vpcmpb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPBZ256rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZ256rmik_alt, X86_INS_VPCMPB: vpcmpb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPBZ256rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZ256rri_alt, X86_INS_VPCMPB: vpcmpb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPBZ256rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZ256rrik_alt, X86_INS_VPCMPB: vpcmpb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPBZrmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZrmi_alt, X86_INS_VPCMPB: vpcmpb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPBZrmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZrmik_alt, X86_INS_VPCMPB: vpcmpb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPBZrri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZrri_alt, X86_INS_VPCMPB: vpcmpb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPBZrrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPBZrrik_alt, X86_INS_VPCMPB: vpcmpb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZ128rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZ128rmi_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZ128rmib, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZ128rmib_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZ128rmibk, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZ128rmibk_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZ128rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZ128rmik_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZ128rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZ128rri_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZ128rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZ128rrik_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZ256rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZ256rmi_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZ256rmib, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZ256rmib_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZ256rmibk, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZ256rmibk_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZ256rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZ256rmik_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZ256rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZ256rri_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZ256rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZ256rrik_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZrmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZrmi_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZrmib, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZrmib_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZrmibk, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZrmibk_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZrmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZrmik_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZrri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZrri_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPDZrrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPDZrrik_alt, X86_INS_VPCMPD: vpcmpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPEQBYrm, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBYrr, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBZ128rm, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBZ128rmk, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBZ128rr, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBZ128rrk, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBZ256rm, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBZ256rmk, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBZ256rr, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBZ256rrk, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBZrm, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBZrmk, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBZrr, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBZrrk, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBrm, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQBrr, X86_INS_VPCMPEQB: vpcmpeqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDYrm, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDYrr, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZ128rm, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZ128rmb, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZ128rmbk, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZ128rmk, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZ128rr, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZ128rrk, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZ256rm, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZ256rmb, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZ256rmbk, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZ256rmk, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZ256rr, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZ256rrk, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZrm, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZrmb, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZrmbk, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZrmk, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZrr, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDZrrk, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDrm, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQDrr, X86_INS_VPCMPEQD: vpcmpeqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQYrm, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQYrr, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZ128rm, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZ128rmb, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZ128rmbk, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZ128rmk, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZ128rr, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZ128rrk, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZ256rm, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZ256rmb, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZ256rmbk, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZ256rmk, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZ256rr, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZ256rrk, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZrm, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZrmb, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZrmbk, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZrmk, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZrr, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQZrrk, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQrm, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQQrr, X86_INS_VPCMPEQQ: vpcmpeqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWYrm, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWYrr, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWZ128rm, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWZ128rmk, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWZ128rr, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWZ128rrk, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWZ256rm, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWZ256rmk, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWZ256rr, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWZ256rrk, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWZrm, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWZrmk, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWZrr, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWZrrk, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWrm, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPEQWrr, X86_INS_VPCMPEQW: vpcmpeqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPESTRIrm, X86_INS_VPCMPESTRI: vpcmpestri */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPESTRIrr, X86_INS_VPCMPESTRI: vpcmpestri */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPESTRMrm, X86_INS_VPCMPESTRM: vpcmpestrm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPESTRMrr, X86_INS_VPCMPESTRM: vpcmpestrm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBYrm, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBYrr, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBZ128rm, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBZ128rmk, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBZ128rr, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBZ128rrk, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBZ256rm, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBZ256rmk, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBZ256rr, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBZ256rrk, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBZrm, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBZrmk, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBZrr, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBZrrk, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBrm, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTBrr, X86_INS_VPCMPGTB: vpcmpgtb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDYrm, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDYrr, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZ128rm, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZ128rmb, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZ128rmbk, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZ128rmk, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZ128rr, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZ128rrk, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZ256rm, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZ256rmb, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZ256rmbk, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZ256rmk, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZ256rr, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZ256rrk, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZrm, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZrmb, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZrmbk, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZrmk, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZrr, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDZrrk, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDrm, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTDrr, X86_INS_VPCMPGTD: vpcmpgtd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQYrm, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQYrr, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZ128rm, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZ128rmb, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZ128rmbk, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZ128rmk, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZ128rr, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZ128rrk, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZ256rm, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZ256rmb, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZ256rmbk, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZ256rmk, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZ256rr, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZ256rrk, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZrm, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZrmb, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZrmbk, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZrmk, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZrr, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQZrrk, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQrm, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTQrr, X86_INS_VPCMPGTQ: vpcmpgtq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWYrm, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWYrr, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWZ128rm, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWZ128rmk, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWZ128rr, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWZ128rrk, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWZ256rm, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWZ256rmk, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWZ256rr, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWZ256rrk, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWZrm, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWZrmk, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWZrr, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWZrrk, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWrm, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPGTWrr, X86_INS_VPCMPGTW: vpcmpgtw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPISTRIrm, X86_INS_VPCMPISTRI: vpcmpistri */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPISTRIrr, X86_INS_VPCMPISTRI: vpcmpistri */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPISTRMrm, X86_INS_VPCMPISTRM: vpcmpistrm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPISTRMrr, X86_INS_VPCMPISTRM: vpcmpistrm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ128rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ128rmi_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZ128rmib, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ128rmib_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZ128rmibk, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ128rmibk_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZ128rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ128rmik_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZ128rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ128rri_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZ128rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ128rrik_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZ256rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ256rmi_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZ256rmib, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ256rmib_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZ256rmibk, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ256rmibk_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZ256rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ256rmik_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZ256rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ256rri_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZ256rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZ256rrik_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZrmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZrmi_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZrmib, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZrmib_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZrmibk, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZrmibk_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZrmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZrmik_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZrri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZrri_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPQZrrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPQZrrik_alt, X86_INS_VPCMPQ: vpcmpq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUBZ128rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUBZ128rmi_alt, X86_INS_VPCMPUB: vpcmpub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUBZ128rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUBZ128rmik_alt, X86_INS_VPCMPUB: vpcmpub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUBZ128rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUBZ128rri_alt, X86_INS_VPCMPUB: vpcmpub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUBZ128rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUBZ128rrik_alt, X86_INS_VPCMPUB: vpcmpub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUBZ256rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUBZ256rmi_alt, X86_INS_VPCMPUB: vpcmpub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUBZ256rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUBZ256rmik_alt, X86_INS_VPCMPUB: vpcmpub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUBZ256rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUBZ256rri_alt, X86_INS_VPCMPUB: vpcmpub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUBZ256rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUBZ256rrik_alt, X86_INS_VPCMPUB: vpcmpub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUBZrmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUBZrmi_alt, X86_INS_VPCMPUB: vpcmpub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUBZrmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUBZrmik_alt, X86_INS_VPCMPUB: vpcmpub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUBZrri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUBZrri_alt, X86_INS_VPCMPUB: vpcmpub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUBZrrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUBZrrik_alt, X86_INS_VPCMPUB: vpcmpub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZ128rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZ128rmi_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZ128rmib, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZ128rmib_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZ128rmibk, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZ128rmibk_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZ128rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZ128rmik_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZ128rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZ128rri_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZ128rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZ128rrik_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZ256rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZ256rmi_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZ256rmib, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZ256rmib_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZ256rmibk, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZ256rmibk_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZ256rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZ256rmik_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZ256rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZ256rri_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZ256rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZ256rrik_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZrmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZrmi_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZrmib, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZrmib_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZrmibk, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZrmibk_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZrmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZrmik_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZrri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZrri_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUDZrrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUDZrrik_alt, X86_INS_VPCMPUD: vpcmpud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZ128rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZ128rmi_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZ128rmib, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZ128rmib_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZ128rmibk, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZ128rmibk_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZ128rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZ128rmik_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZ128rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZ128rri_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZ128rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZ128rrik_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZ256rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZ256rmi_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZ256rmib, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZ256rmib_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZ256rmibk, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZ256rmibk_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZ256rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZ256rmik_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZ256rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZ256rri_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZ256rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZ256rrik_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZrmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZrmi_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZrmib, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZrmib_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZrmibk, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZrmibk_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZrmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZrmik_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZrri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZrri_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUQZrrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUQZrrik_alt, X86_INS_VPCMPUQ: vpcmpuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUWZ128rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUWZ128rmi_alt, X86_INS_VPCMPUW: vpcmpuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUWZ128rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUWZ128rmik_alt, X86_INS_VPCMPUW: vpcmpuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUWZ128rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUWZ128rri_alt, X86_INS_VPCMPUW: vpcmpuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUWZ128rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUWZ128rrik_alt, X86_INS_VPCMPUW: vpcmpuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUWZ256rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUWZ256rmi_alt, X86_INS_VPCMPUW: vpcmpuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUWZ256rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUWZ256rmik_alt, X86_INS_VPCMPUW: vpcmpuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUWZ256rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUWZ256rri_alt, X86_INS_VPCMPUW: vpcmpuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUWZ256rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUWZ256rrik_alt, X86_INS_VPCMPUW: vpcmpuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUWZrmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUWZrmi_alt, X86_INS_VPCMPUW: vpcmpuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUWZrmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUWZrmik_alt, X86_INS_VPCMPUW: vpcmpuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUWZrri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUWZrri_alt, X86_INS_VPCMPUW: vpcmpuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPUWZrrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPUWZrrik_alt, X86_INS_VPCMPUW: vpcmpuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPWZ128rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPWZ128rmi_alt, X86_INS_VPCMPW: vpcmpw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPWZ128rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPWZ128rmik_alt, X86_INS_VPCMPW: vpcmpw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPWZ128rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPWZ128rri_alt, X86_INS_VPCMPW: vpcmpw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPWZ128rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPWZ128rrik_alt, X86_INS_VPCMPW: vpcmpw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPWZ256rmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPWZ256rmi_alt, X86_INS_VPCMPW: vpcmpw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPWZ256rmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPWZ256rmik_alt, X86_INS_VPCMPW: vpcmpw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPWZ256rri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPWZ256rri_alt, X86_INS_VPCMPW: vpcmpw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPWZ256rrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPWZ256rrik_alt, X86_INS_VPCMPW: vpcmpw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPWZrmi, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPWZrmi_alt, X86_INS_VPCMPW: vpcmpw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPWZrmik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPWZrmik_alt, X86_INS_VPCMPW: vpcmpw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPWZrri, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPWZrri_alt, X86_INS_VPCMPW: vpcmpw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCMPWZrrik, X86_INS_VPCMP: vpcmp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCMPWZrrik_alt, X86_INS_VPCMPW: vpcmpw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMBmi, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMBmi_alt, X86_INS_VPCOMB: vpcomb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMBri, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMBri_alt, X86_INS_VPCOMB: vpcomb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMDmi, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMDmi_alt, X86_INS_VPCOMD: vpcomd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMDri, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMDri_alt, X86_INS_VPCOMD: vpcomd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMPRESSBZ128mr, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZ128mrk, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZ128rr, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZ128rrk, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZ128rrkz, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZ256mr, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZ256mrk, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZ256rr, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZ256rrk, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZ256rrkz, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZmr, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZmrk, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZrr, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZrrk, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSBZrrkz, X86_INS_VPCOMPRESSB: vpcompressb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZ128mr, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZ128mrk, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZ128rr, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZ128rrk, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZ128rrkz, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZ256mr, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZ256mrk, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZ256rr, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZ256rrk, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZ256rrkz, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZmr, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZmrk, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZrr, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZrrk, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSDZrrkz, X86_INS_VPCOMPRESSD: vpcompressd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZ128mr, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZ128mrk, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZ128rr, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZ128rrk, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZ128rrkz, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZ256mr, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZ256mrk, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZ256rr, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZ256rrk, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZ256rrkz, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZmr, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZmrk, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZrr, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZrrk, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSQZrrkz, X86_INS_VPCOMPRESSQ: vpcompressq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZ128mr, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZ128mrk, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZ128rr, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZ128rrk, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZ128rrkz, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZ256mr, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZ256mrk, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZ256rr, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZ256rrk, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZ256rrkz, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZmr, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZmrk, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZrr, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZrrk, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMPRESSWZrrkz, X86_INS_VPCOMPRESSW: vpcompressw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMQmi, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMQmi_alt, X86_INS_VPCOMQ: vpcomq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMQri, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMQri_alt, X86_INS_VPCOMQ: vpcomq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMUBmi, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMUBmi_alt, X86_INS_VPCOMUB: vpcomub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMUBri, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMUBri_alt, X86_INS_VPCOMUB: vpcomub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMUDmi, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMUDmi_alt, X86_INS_VPCOMUD: vpcomud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMUDri, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMUDri_alt, X86_INS_VPCOMUD: vpcomud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMUQmi, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMUQmi_alt, X86_INS_VPCOMUQ: vpcomuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMUQri, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMUQri_alt, X86_INS_VPCOMUQ: vpcomuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMUWmi, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMUWmi_alt, X86_INS_VPCOMUW: vpcomuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMUWri, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMUWri_alt, X86_INS_VPCOMUW: vpcomuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMWmi, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMWmi_alt, X86_INS_VPCOMW: vpcomw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCOMWri, X86_INS_VPCOM: vpcom */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPCOMWri_alt, X86_INS_VPCOMW: vpcomw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPCONFLICTDZ128rm, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ128rmb, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ128rmbk, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ128rmbkz, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ128rmk, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ128rmkz, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ128rr, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ128rrk, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ128rrkz, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ256rm, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ256rmb, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ256rmbk, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ256rmbkz, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ256rmk, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ256rmkz, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ256rr, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ256rrk, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZ256rrkz, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZrm, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZrmb, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZrmbk, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZrmbkz, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZrmk, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZrmkz, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZrr, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZrrk, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTDZrrkz, X86_INS_VPCONFLICTD: vpconflictd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ128rm, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ128rmb, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ128rmbk, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ128rmbkz, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ128rmk, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ128rmkz, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ128rr, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ128rrk, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ128rrkz, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ256rm, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ256rmb, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ256rmbk, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ256rmbkz, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ256rmk, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ256rmkz, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ256rr, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ256rrk, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZ256rrkz, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZrm, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZrmb, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZrmbk, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZrmbkz, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZrmk, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZrmkz, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZrr, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZrrk, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPCONFLICTQZrrkz, X86_INS_VPCONFLICTQ: vpconflictq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ128m, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ128mb, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ128mbk, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ128mbkz, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ128mk, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ128mkz, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ128r, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ128rk, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ128rkz, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ256m, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ256mb, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ256mbk, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ256mbkz, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ256mk, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ256mkz, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ256r, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ256rk, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZ256rkz, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZm, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZmb, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZmbk, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZmbkz, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZmk, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZmkz, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZr, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZrk, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDSZrkz, X86_INS_VPDPBUSDS: vpdpbusds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ128m, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ128mb, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ128mbk, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ128mbkz, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ128mk, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ128mkz, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ128r, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ128rk, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ128rkz, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ256m, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ256mb, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ256mbk, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ256mbkz, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ256mk, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ256mkz, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ256r, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ256rk, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZ256rkz, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZm, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZmb, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZmbk, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZmbkz, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZmk, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZmkz, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZr, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZrk, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPBUSDZrkz, X86_INS_VPDPBUSD: vpdpbusd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ128m, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ128mb, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ128mbk, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ128mbkz, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ128mk, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ128mkz, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ128r, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ128rk, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ128rkz, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ256m, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ256mb, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ256mbk, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ256mbkz, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ256mk, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ256mkz, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ256r, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ256rk, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZ256rkz, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZm, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZmb, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZmbk, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZmbkz, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZmk, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZmkz, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZr, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZrk, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDSZrkz, X86_INS_VPDPWSSDS: vpdpwssds */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ128m, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ128mb, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ128mbk, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ128mbkz, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ128mk, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ128mkz, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ128r, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ128rk, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ128rkz, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ256m, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ256mb, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ256mbk, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ256mbkz, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ256mk, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ256mkz, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ256r, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ256rk, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZ256rkz, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZm, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZmb, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZmbk, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZmbkz, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZmk, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZmkz, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZr, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZrk, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPDPWSSDZrkz, X86_INS_VPDPWSSD: vpdpwssd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERM2F128rm, X86_INS_VPERM2F128: vperm2f128 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERM2F128rr, X86_INS_VPERM2F128: vperm2f128 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERM2I128rm, X86_INS_VPERM2I128: vperm2i128 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERM2I128rr, X86_INS_VPERM2I128: vperm2i128 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMBZ128rm, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZ128rmk, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZ128rmkz, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZ128rr, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZ128rrk, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZ128rrkz, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZ256rm, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZ256rmk, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZ256rmkz, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZ256rr, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZ256rrk, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZ256rrkz, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZrm, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZrmk, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZrmkz, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZrr, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZrrk, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMBZrrkz, X86_INS_VPERMB: vpermb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMDYrm, X86_INS_VPERMD: vpermd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMDYrr, X86_INS_VPERMD: vpermd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMDZ256rm, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZ256rmb, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZ256rmbk, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZ256rmbkz, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZ256rmk, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZ256rmkz, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZ256rr, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZ256rrk, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZ256rrkz, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZrm, X86_INS_VPERMD: vpermd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMDZrmb, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZrmbk, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZrmbkz, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZrmk, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZrmkz, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZrr, X86_INS_VPERMD: vpermd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMDZrrk, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMDZrrkz, X86_INS_VPERMD: vpermd */ + 0, + { 0 } +}, + +{ /* X86_VPERMI2B128rm, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2B128rmk, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2B128rmkz, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2B128rr, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2B128rrk, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2B128rrkz, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2B256rm, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2B256rmk, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2B256rmkz, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2B256rr, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2B256rrk, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2B256rrkz, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Brm, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Brmk, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Brmkz, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Brr, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Brrk, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Brrkz, X86_INS_VPERMI2B: vpermi2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D128rm, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D128rmb, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D128rmbk, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D128rmbkz, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D128rmk, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D128rmkz, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D128rr, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D128rrk, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D128rrkz, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D256rm, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D256rmb, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D256rmbk, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D256rmbkz, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D256rmk, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D256rmkz, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D256rr, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D256rrk, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2D256rrkz, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Drm, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Drmb, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Drmbk, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Drmbkz, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Drmk, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Drmkz, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Drr, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Drrk, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Drrkz, X86_INS_VPERMI2D: vpermi2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD128rm, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD128rmb, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD128rmbk, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD128rmbkz, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD128rmk, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD128rmkz, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD128rr, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD128rrk, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD128rrkz, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD256rm, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD256rmb, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD256rmbk, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD256rmbkz, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD256rmk, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD256rmkz, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD256rr, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD256rrk, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PD256rrkz, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PDrm, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PDrmb, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PDrmbk, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PDrmbkz, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PDrmk, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PDrmkz, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PDrr, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PDrrk, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PDrrkz, X86_INS_VPERMI2PD: vpermi2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS128rm, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS128rmb, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS128rmbk, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS128rmbkz, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS128rmk, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS128rmkz, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS128rr, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS128rrk, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS128rrkz, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS256rm, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS256rmb, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS256rmbk, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS256rmbkz, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS256rmk, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS256rmkz, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS256rr, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS256rrk, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PS256rrkz, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PSrm, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PSrmb, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PSrmbk, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PSrmbkz, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PSrmk, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PSrmkz, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PSrr, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PSrrk, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2PSrrkz, X86_INS_VPERMI2PS: vpermi2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q128rm, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q128rmb, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q128rmbk, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q128rmbkz, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q128rmk, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q128rmkz, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q128rr, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q128rrk, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q128rrkz, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q256rm, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q256rmb, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q256rmbk, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q256rmbkz, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q256rmk, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q256rmkz, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q256rr, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q256rrk, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Q256rrkz, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Qrm, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Qrmb, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Qrmbk, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Qrmbkz, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Qrmk, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Qrmkz, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Qrr, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Qrrk, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Qrrkz, X86_INS_VPERMI2Q: vpermi2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2W128rm, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2W128rmk, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2W128rmkz, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2W128rr, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2W128rrk, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2W128rrkz, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2W256rm, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2W256rmk, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2W256rmkz, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2W256rr, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2W256rrk, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2W256rrkz, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Wrm, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Wrmk, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Wrmkz, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Wrr, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Wrrk, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMI2Wrrkz, X86_INS_VPERMI2W: vpermi2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMIL2PDYmr, X86_INS_VPERMIL2PD: vpermil2pd */ + 0, + { 0 } +}, + +{ /* X86_VPERMIL2PDYrm, X86_INS_VPERMIL2PD: vpermil2pd */ + 0, + { 0 } +}, + +{ /* X86_VPERMIL2PDYrr, X86_INS_VPERMIL2PD: vpermil2pd */ + 0, + { 0 } +}, + +{ /* X86_VPERMIL2PDYrr_REV, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMIL2PDmr, X86_INS_VPERMIL2PD: vpermil2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMIL2PDrm, X86_INS_VPERMIL2PD: vpermil2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMIL2PDrr, X86_INS_VPERMIL2PD: vpermil2pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMIL2PDrr_REV, X86_INS_VPERMIL2PD: vpermil2pd */ + 0, + { 0 } +}, + +{ /* X86_VPERMIL2PSYmr, X86_INS_VPERMIL2PS: vpermil2ps */ + 0, + { 0 } +}, + +{ /* X86_VPERMIL2PSYrm, X86_INS_VPERMIL2PS: vpermil2ps */ + 0, + { 0 } +}, + +{ /* X86_VPERMIL2PSYrr, X86_INS_VPERMIL2PS: vpermil2ps */ + 0, + { 0 } +}, + +{ /* X86_VPERMIL2PSYrr_REV, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMIL2PSmr, X86_INS_VPERMIL2PS: vpermil2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMIL2PSrm, X86_INS_VPERMIL2PS: vpermil2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMIL2PSrr, X86_INS_VPERMIL2PS: vpermil2ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMIL2PSrr_REV, X86_INS_VPERMIL2PS: vpermil2ps */ + 0, + { 0 } +}, + +{ /* X86_VPERMILPDYmi, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDYri, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDYrm, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDYrr, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ128mbi, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ128mbik, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ128mbikz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ128mi, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ128mik, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ128mikz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ128ri, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ128rik, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ128rikz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ128rm, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ128rmb, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ128rmbk, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ128rmbkz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ128rmk, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ128rmkz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ128rr, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ128rrk, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ128rrkz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ256mbi, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ256mbik, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ256mbikz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ256mi, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ256mik, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ256mikz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ256ri, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ256rik, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ256rikz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZ256rm, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ256rmb, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ256rmbk, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ256rmbkz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ256rmk, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ256rmkz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ256rr, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ256rrk, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZ256rrkz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZmbi, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZmbik, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZmbikz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZmi, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZmik, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZmikz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZri, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZrik, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZrikz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDZrm, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZrmb, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZrmbk, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZrmbkz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZrmk, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZrmkz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZrr, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZrrk, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDZrrkz, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDmi, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDri, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPDrm, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPDrr, X86_INS_VPERMILPD: vpermilpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSYmi, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSYri, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSYrm, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSYrr, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ128mbi, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ128mbik, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ128mbikz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ128mi, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ128mik, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ128mikz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ128ri, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ128rik, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ128rikz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ128rm, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ128rmb, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ128rmbk, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ128rmbkz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ128rmk, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ128rmkz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ128rr, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ128rrk, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ128rrkz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ256mbi, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ256mbik, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ256mbikz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ256mi, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ256mik, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ256mikz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ256ri, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ256rik, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ256rikz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZ256rm, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ256rmb, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ256rmbk, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ256rmbkz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ256rmk, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ256rmkz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ256rr, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ256rrk, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZ256rrkz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZmbi, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZmbik, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZmbikz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZmi, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZmik, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZmikz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZri, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZrik, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZrikz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSZrm, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZrmb, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZrmbk, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZrmbkz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZrmk, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZrmkz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZrr, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZrrk, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSZrrkz, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSmi, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSri, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMILPSrm, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMILPSrr, X86_INS_VPERMILPS: vpermilps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDYmi, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDYri, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZ256mbi, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZ256mbik, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZ256mbikz, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZ256mi, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZ256mik, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZ256mikz, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZ256ri, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZ256rik, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZ256rikz, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZ256rm, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZ256rmb, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZ256rmbk, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZ256rmbkz, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZ256rmk, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZ256rmkz, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZ256rr, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZ256rrk, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZ256rrkz, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZmbi, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZmbik, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZmbikz, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZmi, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZmik, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZmikz, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZri, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZrik, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZrikz, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMPDZrm, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZrmb, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZrmbk, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZrmbkz, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZrmk, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZrmkz, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZrr, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZrrk, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPDZrrkz, X86_INS_VPERMPD: vpermpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSYrm, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSYrr, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZ256rm, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZ256rmb, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZ256rmbk, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZ256rmbkz, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZ256rmk, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZ256rmkz, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZ256rr, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZ256rrk, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZ256rrkz, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZrm, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZrmb, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZrmbk, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZrmbkz, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZrmk, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZrmkz, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZrr, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZrrk, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMPSZrrkz, X86_INS_VPERMPS: vpermps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQYmi, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQYri, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZ256mbi, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZ256mbik, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZ256mbikz, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZ256mi, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZ256mik, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZ256mikz, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZ256ri, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZ256rik, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZ256rikz, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZ256rm, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZ256rmb, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZ256rmbk, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZ256rmbkz, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZ256rmk, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZ256rmkz, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZ256rr, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZ256rrk, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZ256rrkz, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZmbi, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZmbik, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZmbikz, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZmi, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZmik, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZmikz, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZri, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZrik, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZrikz, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPERMQZrm, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZrmb, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZrmbk, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZrmbkz, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZrmk, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZrmkz, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZrr, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZrrk, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMQZrrkz, X86_INS_VPERMQ: vpermq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2B128rm, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2B128rmk, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2B128rmkz, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2B128rr, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2B128rrk, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2B128rrkz, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2B256rm, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2B256rmk, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2B256rmkz, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2B256rr, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2B256rrk, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2B256rrkz, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Brm, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Brmk, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Brmkz, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Brr, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Brrk, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Brrkz, X86_INS_VPERMT2B: vpermt2b */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D128rm, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D128rmb, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D128rmbk, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D128rmbkz, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D128rmk, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D128rmkz, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D128rr, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D128rrk, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D128rrkz, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D256rm, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D256rmb, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D256rmbk, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D256rmbkz, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D256rmk, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D256rmkz, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D256rr, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D256rrk, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2D256rrkz, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Drm, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Drmb, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Drmbk, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Drmbkz, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Drmk, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Drmkz, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Drr, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Drrk, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Drrkz, X86_INS_VPERMT2D: vpermt2d */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD128rm, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD128rmb, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD128rmbk, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD128rmbkz, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD128rmk, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD128rmkz, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD128rr, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD128rrk, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD128rrkz, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD256rm, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD256rmb, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD256rmbk, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD256rmbkz, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD256rmk, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD256rmkz, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD256rr, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD256rrk, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PD256rrkz, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PDrm, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PDrmb, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PDrmbk, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PDrmbkz, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PDrmk, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PDrmkz, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PDrr, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PDrrk, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PDrrkz, X86_INS_VPERMT2PD: vpermt2pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS128rm, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS128rmb, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS128rmbk, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS128rmbkz, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS128rmk, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS128rmkz, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS128rr, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS128rrk, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS128rrkz, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS256rm, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS256rmb, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS256rmbk, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS256rmbkz, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS256rmk, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS256rmkz, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS256rr, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS256rrk, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PS256rrkz, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PSrm, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PSrmb, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PSrmbk, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PSrmbkz, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PSrmk, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PSrmkz, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PSrr, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PSrrk, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2PSrrkz, X86_INS_VPERMT2PS: vpermt2ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q128rm, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q128rmb, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q128rmbk, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q128rmbkz, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q128rmk, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q128rmkz, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q128rr, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q128rrk, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q128rrkz, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q256rm, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q256rmb, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q256rmbk, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q256rmbkz, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q256rmk, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q256rmkz, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q256rr, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q256rrk, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Q256rrkz, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Qrm, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Qrmb, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Qrmbk, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Qrmbkz, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Qrmk, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Qrmkz, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Qrr, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Qrrk, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Qrrkz, X86_INS_VPERMT2Q: vpermt2q */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2W128rm, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2W128rmk, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2W128rmkz, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2W128rr, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2W128rrk, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2W128rrkz, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2W256rm, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2W256rmk, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2W256rmkz, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2W256rr, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2W256rrk, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2W256rrkz, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Wrm, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Wrmk, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Wrmkz, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Wrr, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Wrrk, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMT2Wrrkz, X86_INS_VPERMT2W: vpermt2w */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZ128rm, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZ128rmk, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZ128rmkz, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZ128rr, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZ128rrk, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZ128rrkz, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZ256rm, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZ256rmk, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZ256rmkz, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZ256rr, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZ256rrk, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZ256rrkz, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZrm, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZrmk, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZrmkz, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZrr, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZrrk, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPERMWZrrkz, X86_INS_VPERMW: vpermw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZ128rm, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZ128rmk, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZ128rmkz, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZ128rr, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZ128rrk, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZ128rrkz, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZ256rm, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZ256rmk, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZ256rmkz, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZ256rr, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZ256rrk, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZ256rrkz, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZrm, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZrmk, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZrmkz, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZrr, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZrrk, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDBZrrkz, X86_INS_VPEXPANDB: vpexpandb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZ128rm, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZ128rmk, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZ128rmkz, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZ128rr, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZ128rrk, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZ128rrkz, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZ256rm, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZ256rmk, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZ256rmkz, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZ256rr, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZ256rrk, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZ256rrkz, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZrm, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZrmk, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZrmkz, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZrr, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZrrk, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDDZrrkz, X86_INS_VPEXPANDD: vpexpandd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZ128rm, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZ128rmk, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZ128rmkz, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZ128rr, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZ128rrk, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZ128rrkz, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZ256rm, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZ256rmk, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZ256rmkz, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZ256rr, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZ256rrk, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZ256rrkz, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZrm, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZrmk, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZrmkz, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZrr, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZrrk, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDQZrrkz, X86_INS_VPEXPANDQ: vpexpandq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZ128rm, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZ128rmk, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZ128rmkz, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZ128rr, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZ128rrk, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZ128rrkz, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZ256rm, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZ256rmk, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZ256rmkz, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZ256rr, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZ256rrk, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZ256rrkz, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZrm, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZrmk, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZrmkz, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZrr, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZrrk, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXPANDWZrrkz, X86_INS_VPEXPANDW: vpexpandw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXTRBZmr, X86_INS_VPEXTRB: vpextrb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXTRBZrr, X86_INS_VPEXTRB: vpextrb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXTRBmr, X86_INS_VPEXTRB: vpextrb */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPEXTRBrr, X86_INS_VPEXTRB: vpextrb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPEXTRDZmr, X86_INS_VPEXTRD: vpextrd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXTRDZrr, X86_INS_VPEXTRD: vpextrd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXTRDmr, X86_INS_VPEXTRD: vpextrd */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPEXTRDrr, X86_INS_VPEXTRD: vpextrd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPEXTRQZmr, X86_INS_VPEXTRQ: vpextrq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXTRQZrr, X86_INS_VPEXTRQ: vpextrq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXTRQmr, X86_INS_VPEXTRQ: vpextrq */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPEXTRQrr, X86_INS_VPEXTRQ: vpextrq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPEXTRWZmr, X86_INS_VPEXTRW: vpextrw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXTRWZrr, X86_INS_VPEXTRW: vpextrw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXTRWZrr_REV, X86_INS_VPEXTRW: vpextrw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXTRWmr, X86_INS_VPEXTRW: vpextrw */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPEXTRWrr, X86_INS_VPEXTRW: vpextrw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPEXTRWrr_REV, X86_INS_VPEXTRW: vpextrw $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPGATHERDDYrm, X86_INS_VPGATHERDD: vpgatherdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPGATHERDDZ128rm, X86_INS_VPGATHERDD: vpgatherdd */ + 0, + { 0 } +}, + +{ /* X86_VPGATHERDDZ256rm, X86_INS_VPGATHERDD: vpgatherdd */ + 0, + { 0 } +}, + +{ /* X86_VPGATHERDDZrm, X86_INS_VPGATHERDD: vpgatherdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPGATHERDDrm, X86_INS_VPGATHERDD: vpgatherdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPGATHERDQYrm, X86_INS_VPGATHERDQ: vpgatherdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPGATHERDQZ128rm, X86_INS_VPGATHERDQ: vpgatherdq */ + 0, + { 0 } +}, + +{ /* X86_VPGATHERDQZ256rm, X86_INS_VPGATHERDQ: vpgatherdq */ + 0, + { 0 } +}, + +{ /* X86_VPGATHERDQZrm, X86_INS_VPGATHERDQ: vpgatherdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPGATHERDQrm, X86_INS_VPGATHERDQ: vpgatherdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPGATHERQDYrm, X86_INS_VPGATHERQD: vpgatherqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPGATHERQDZ128rm, X86_INS_VPGATHERQD: vpgatherqd */ + 0, + { 0 } +}, + +{ /* X86_VPGATHERQDZ256rm, X86_INS_VPGATHERQD: vpgatherqd */ + 0, + { 0 } +}, + +{ /* X86_VPGATHERQDZrm, X86_INS_VPGATHERQD: vpgatherqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPGATHERQDrm, X86_INS_VPGATHERQD: vpgatherqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPGATHERQQYrm, X86_INS_VPGATHERQQ: vpgatherqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPGATHERQQZ128rm, X86_INS_VPGATHERQQ: vpgatherqq */ + 0, + { 0 } +}, + +{ /* X86_VPGATHERQQZ256rm, X86_INS_VPGATHERQQ: vpgatherqq */ + 0, + { 0 } +}, + +{ /* X86_VPGATHERQQZrm, X86_INS_VPGATHERQQ: vpgatherqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPGATHERQQrm, X86_INS_VPGATHERQQ: vpgatherqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDBDrm, X86_INS_VPHADDBD: vphaddbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDBDrr, X86_INS_VPHADDBD: vphaddbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDBQrm, X86_INS_VPHADDBQ: vphaddbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDBQrr, X86_INS_VPHADDBQ: vphaddbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDBWrm, X86_INS_VPHADDBW: vphaddbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDBWrr, X86_INS_VPHADDBW: vphaddbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDDQrm, X86_INS_VPHADDDQ: vphadddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDDQrr, X86_INS_VPHADDDQ: vphadddq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDDYrm, X86_INS_VPHADDD: vphaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDDYrr, X86_INS_VPHADDD: vphaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDDrm, X86_INS_VPHADDD: vphaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDDrr, X86_INS_VPHADDD: vphaddd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDSWYrm, X86_INS_VPHADDSW: vphaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDSWYrr, X86_INS_VPHADDSW: vphaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDSWrm, X86_INS_VPHADDSW: vphaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDSWrr, X86_INS_VPHADDSW: vphaddsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDUBDrm, X86_INS_VPHADDUBD: vphaddubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDUBDrr, X86_INS_VPHADDUBD: vphaddubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDUBQrm, X86_INS_VPHADDUBQ: vphaddubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDUBQrr, X86_INS_VPHADDUBQ: vphaddubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDUBWrm, X86_INS_VPHADDUBW: vphaddubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDUBWrr, X86_INS_VPHADDUBW: vphaddubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDUDQrm, X86_INS_VPHADDUDQ: vphaddudq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDUDQrr, X86_INS_VPHADDUDQ: vphaddudq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDUWDrm, X86_INS_VPHADDUWD: vphadduwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDUWDrr, X86_INS_VPHADDUWD: vphadduwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDUWQrm, X86_INS_VPHADDUWQ: vphadduwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDUWQrr, X86_INS_VPHADDUWQ: vphadduwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDWDrm, X86_INS_VPHADDWD: vphaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDWDrr, X86_INS_VPHADDWD: vphaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDWQrm, X86_INS_VPHADDWQ: vphaddwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDWQrr, X86_INS_VPHADDWQ: vphaddwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDWYrm, X86_INS_VPHADDW: vphaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDWYrr, X86_INS_VPHADDW: vphaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDWrm, X86_INS_VPHADDW: vphaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHADDWrr, X86_INS_VPHADDW: vphaddw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHMINPOSUWrm, X86_INS_VPHMINPOSUW: vphminposuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHMINPOSUWrr, X86_INS_VPHMINPOSUW: vphminposuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBBWrm, X86_INS_VPHSUBBW: vphsubbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBBWrr, X86_INS_VPHSUBBW: vphsubbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBDQrm, X86_INS_VPHSUBDQ: vphsubdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBDQrr, X86_INS_VPHSUBDQ: vphsubdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBDYrm, X86_INS_VPHSUBD: vphsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBDYrr, X86_INS_VPHSUBD: vphsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBDrm, X86_INS_VPHSUBD: vphsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBDrr, X86_INS_VPHSUBD: vphsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBSWYrm, X86_INS_VPHSUBSW: vphsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBSWYrr, X86_INS_VPHSUBSW: vphsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBSWrm, X86_INS_VPHSUBSW: vphsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBSWrr, X86_INS_VPHSUBSW: vphsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBWDrm, X86_INS_VPHSUBWD: vphsubwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBWDrr, X86_INS_VPHSUBWD: vphsubwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBWYrm, X86_INS_VPHSUBW: vphsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBWYrr, X86_INS_VPHSUBW: vphsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBWrm, X86_INS_VPHSUBW: vphsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPHSUBWrr, X86_INS_VPHSUBW: vphsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPINSRBZrm, X86_INS_VPINSRB: vpinsrb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPINSRBZrr, X86_INS_VPINSRB: vpinsrb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPINSRBrm, X86_INS_VPINSRB: vpinsrb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPINSRBrr, X86_INS_VPINSRB: vpinsrb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPINSRDZrm, X86_INS_VPINSRD: vpinsrd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPINSRDZrr, X86_INS_VPINSRD: vpinsrd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPINSRDrm, X86_INS_VPINSRD: vpinsrd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPINSRDrr, X86_INS_VPINSRD: vpinsrd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPINSRQZrm, X86_INS_VPINSRQ: vpinsrq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPINSRQZrr, X86_INS_VPINSRQ: vpinsrq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPINSRQrm, X86_INS_VPINSRQ: vpinsrq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPINSRQrr, X86_INS_VPINSRQ: vpinsrq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPINSRWZrm, X86_INS_VPINSRW: vpinsrw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPINSRWZrr, X86_INS_VPINSRW: vpinsrw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPINSRWrm, X86_INS_VPINSRW: vpinsrw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPINSRWrr, X86_INS_VPINSRW: vpinsrw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ128rm, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ128rmb, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ128rmbk, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ128rmbkz, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ128rmk, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ128rmkz, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ128rr, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ128rrk, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ128rrkz, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ256rm, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ256rmb, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ256rmbk, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ256rmbkz, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ256rmk, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ256rmkz, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ256rr, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ256rrk, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZ256rrkz, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZrm, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZrmb, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZrmbk, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZrmbkz, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZrmk, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZrmkz, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZrr, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZrrk, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTDZrrkz, X86_INS_VPLZCNTD: vplzcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ128rm, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ128rmb, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ128rmbk, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ128rmbkz, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ128rmk, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ128rmkz, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ128rr, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ128rrk, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ128rrkz, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ256rm, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ256rmb, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ256rmbk, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ256rmbkz, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ256rmk, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ256rmkz, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ256rr, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ256rrk, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZ256rrkz, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZrm, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZrmb, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZrmbk, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZrmbkz, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZrmk, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZrmkz, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZrr, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZrrk, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPLZCNTQZrrkz, X86_INS_VPLZCNTQ: vplzcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSDDrm, X86_INS_VPMACSDD: vpmacsdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSDDrr, X86_INS_VPMACSDD: vpmacsdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSDQHrm, X86_INS_VPMACSDQH: vpmacsdqh */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSDQHrr, X86_INS_VPMACSDQH: vpmacsdqh */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSDQLrm, X86_INS_VPMACSDQL: vpmacsdql */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSDQLrr, X86_INS_VPMACSDQL: vpmacsdql */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSSDDrm, X86_INS_VPMACSSDD: vpmacssdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSSDDrr, X86_INS_VPMACSSDD: vpmacssdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSSDQHrm, X86_INS_VPMACSSDQH: vpmacssdqh */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSSDQHrr, X86_INS_VPMACSSDQH: vpmacssdqh */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSSDQLrm, X86_INS_VPMACSSDQL: vpmacssdql */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSSDQLrr, X86_INS_VPMACSSDQL: vpmacssdql */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSSWDrm, X86_INS_VPMACSSWD: vpmacsswd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSSWDrr, X86_INS_VPMACSSWD: vpmacsswd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSSWWrm, X86_INS_VPMACSSWW: vpmacssww */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSSWWrr, X86_INS_VPMACSSWW: vpmacssww */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSWDrm, X86_INS_VPMACSWD: vpmacswd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSWDrr, X86_INS_VPMACSWD: vpmacswd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSWWrm, X86_INS_VPMACSWW: vpmacsww */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMACSWWrr, X86_INS_VPMACSWW: vpmacsww */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADCSSWDrm, X86_INS_VPMADCSSWD: vpmadcsswd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADCSSWDrr, X86_INS_VPMADCSSWD: vpmadcsswd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADCSWDrm, X86_INS_VPMADCSWD: vpmadcswd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADCSWDrr, X86_INS_VPMADCSWD: vpmadcswd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ128m, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ128mb, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ128mbk, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ128mbkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ128mk, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ128mkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ128r, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ128rk, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ128rkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ256m, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ256mb, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ256mbk, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ256mbkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ256mk, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ256mkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ256r, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ256rk, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZ256rkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZm, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZmb, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZmbk, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZmbkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZmk, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZmkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZr, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZrk, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52HUQZrkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ128m, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ128mb, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ128mbk, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ128mbkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ128mk, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ128mkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ128r, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ128rk, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ128rkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ256m, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ256mb, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ256mbk, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ256mbkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ256mk, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ256mkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ256r, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ256rk, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZ256rkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZm, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZmb, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZmbk, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZmbkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZmk, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZmkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZr, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZrk, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADD52LUQZrkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWYrm, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWYrr, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZ128rm, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZ128rmk, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZ128rmkz, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZ128rr, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZ128rrk, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZ128rrkz, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZ256rm, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZ256rmk, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZ256rmkz, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZ256rr, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZ256rrk, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZ256rrkz, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZrm, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZrmk, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZrmkz, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZrr, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZrrk, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWZrrkz, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWrm, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDUBSWrr, X86_INS_VPMADDUBSW: vpmaddubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDYrm, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDYrr, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZ128rm, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZ128rmk, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZ128rmkz, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZ128rr, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZ128rrk, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZ128rrkz, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZ256rm, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZ256rmk, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZ256rmkz, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZ256rr, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZ256rrk, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZ256rrkz, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZrm, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZrmk, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZrmkz, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZrr, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZrrk, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDZrrkz, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDrm, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMADDWDrr, X86_INS_VPMADDWD: vpmaddwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMASKMOVDYmr, X86_INS_VPMASKMOVD: vpmaskmovd */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMASKMOVDYrm, X86_INS_VPMASKMOVD: vpmaskmovd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMASKMOVDmr, X86_INS_VPMASKMOVD: vpmaskmovd */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMASKMOVDrm, X86_INS_VPMASKMOVD: vpmaskmovd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMASKMOVQYmr, X86_INS_VPMASKMOVQ: vpmaskmovq */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMASKMOVQYrm, X86_INS_VPMASKMOVQ: vpmaskmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMASKMOVQmr, X86_INS_VPMASKMOVQ: vpmaskmovq */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMASKMOVQrm, X86_INS_VPMASKMOVQ: vpmaskmovq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBYrm, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBYrr, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZ128rm, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZ128rmk, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZ128rmkz, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZ128rr, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZ128rrk, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZ128rrkz, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZ256rm, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZ256rmk, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZ256rmkz, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZ256rr, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZ256rrk, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZ256rrkz, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZrm, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZrmk, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZrmkz, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZrr, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZrrk, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBZrrkz, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBrm, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSBrr, X86_INS_VPMAXSB: vpmaxsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDYrm, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDYrr, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ128rm, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ128rmb, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ128rmbk, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ128rmbkz, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ128rmk, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ128rmkz, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ128rr, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ128rrk, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ128rrkz, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ256rm, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ256rmb, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ256rmbk, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ256rmbkz, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ256rmk, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ256rmkz, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ256rr, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ256rrk, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZ256rrkz, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZrm, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZrmb, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZrmbk, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZrmbkz, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZrmk, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZrmkz, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZrr, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZrrk, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDZrrkz, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDrm, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSDrr, X86_INS_VPMAXSD: vpmaxsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ128rm, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ128rmb, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ128rmbk, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ128rmbkz, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ128rmk, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ128rmkz, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ128rr, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ128rrk, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ128rrkz, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ256rm, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ256rmb, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ256rmbk, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ256rmbkz, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ256rmk, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ256rmkz, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ256rr, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ256rrk, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZ256rrkz, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZrm, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZrmb, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZrmbk, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZrmbkz, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZrmk, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZrmkz, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZrr, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZrrk, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSQZrrkz, X86_INS_VPMAXSQ: vpmaxsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWYrm, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWYrr, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZ128rm, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZ128rmk, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZ128rmkz, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZ128rr, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZ128rrk, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZ128rrkz, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZ256rm, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZ256rmk, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZ256rmkz, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZ256rr, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZ256rrk, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZ256rrkz, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZrm, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZrmk, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZrmkz, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZrr, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZrrk, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWZrrkz, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWrm, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXSWrr, X86_INS_VPMAXSW: vpmaxsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBYrm, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBYrr, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZ128rm, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZ128rmk, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZ128rmkz, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZ128rr, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZ128rrk, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZ128rrkz, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZ256rm, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZ256rmk, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZ256rmkz, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZ256rr, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZ256rrk, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZ256rrkz, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZrm, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZrmk, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZrmkz, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZrr, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZrrk, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBZrrkz, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBrm, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUBrr, X86_INS_VPMAXUB: vpmaxub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDYrm, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDYrr, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ128rm, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ128rmb, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ128rmbk, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ128rmbkz, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ128rmk, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ128rmkz, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ128rr, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ128rrk, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ128rrkz, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ256rm, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ256rmb, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ256rmbk, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ256rmbkz, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ256rmk, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ256rmkz, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ256rr, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ256rrk, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZ256rrkz, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZrm, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZrmb, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZrmbk, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZrmbkz, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZrmk, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZrmkz, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZrr, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZrrk, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDZrrkz, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDrm, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUDrr, X86_INS_VPMAXUD: vpmaxud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ128rm, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ128rmb, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ128rmbk, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ128rmbkz, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ128rmk, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ128rmkz, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ128rr, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ128rrk, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ128rrkz, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ256rm, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ256rmb, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ256rmbk, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ256rmbkz, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ256rmk, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ256rmkz, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ256rr, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ256rrk, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZ256rrkz, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZrm, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZrmb, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZrmbk, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZrmbkz, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZrmk, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZrmkz, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZrr, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZrrk, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUQZrrkz, X86_INS_VPMAXUQ: vpmaxuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWYrm, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWYrr, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZ128rm, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZ128rmk, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZ128rmkz, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZ128rr, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZ128rrk, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZ128rrkz, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZ256rm, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZ256rmk, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZ256rmkz, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZ256rr, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZ256rrk, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZ256rrkz, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZrm, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZrmk, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZrmkz, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZrr, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZrrk, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWZrrkz, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWrm, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMAXUWrr, X86_INS_VPMAXUW: vpmaxuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBYrm, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBYrr, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZ128rm, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZ128rmk, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZ128rmkz, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZ128rr, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZ128rrk, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZ128rrkz, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZ256rm, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZ256rmk, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZ256rmkz, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZ256rr, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZ256rrk, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZ256rrkz, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZrm, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZrmk, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZrmkz, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZrr, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZrrk, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBZrrkz, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBrm, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSBrr, X86_INS_VPMINSB: vpminsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDYrm, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDYrr, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ128rm, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ128rmb, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ128rmbk, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ128rmbkz, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ128rmk, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ128rmkz, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ128rr, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ128rrk, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ128rrkz, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ256rm, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ256rmb, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ256rmbk, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ256rmbkz, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ256rmk, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ256rmkz, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ256rr, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ256rrk, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZ256rrkz, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZrm, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZrmb, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZrmbk, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZrmbkz, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZrmk, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZrmkz, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZrr, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZrrk, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDZrrkz, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDrm, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSDrr, X86_INS_VPMINSD: vpminsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ128rm, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ128rmb, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ128rmbk, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ128rmbkz, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ128rmk, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ128rmkz, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ128rr, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ128rrk, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ128rrkz, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ256rm, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ256rmb, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ256rmbk, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ256rmbkz, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ256rmk, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ256rmkz, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ256rr, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ256rrk, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZ256rrkz, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZrm, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZrmb, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZrmbk, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZrmbkz, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZrmk, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZrmkz, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZrr, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZrrk, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSQZrrkz, X86_INS_VPMINSQ: vpminsq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWYrm, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWYrr, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZ128rm, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZ128rmk, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZ128rmkz, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZ128rr, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZ128rrk, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZ128rrkz, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZ256rm, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZ256rmk, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZ256rmkz, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZ256rr, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZ256rrk, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZ256rrkz, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZrm, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZrmk, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZrmkz, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZrr, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZrrk, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWZrrkz, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWrm, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINSWrr, X86_INS_VPMINSW: vpminsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBYrm, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBYrr, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZ128rm, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZ128rmk, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZ128rmkz, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZ128rr, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZ128rrk, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZ128rrkz, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZ256rm, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZ256rmk, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZ256rmkz, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZ256rr, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZ256rrk, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZ256rrkz, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZrm, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZrmk, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZrmkz, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZrr, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZrrk, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBZrrkz, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBrm, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUBrr, X86_INS_VPMINUB: vpminub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDYrm, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDYrr, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ128rm, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ128rmb, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ128rmbk, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ128rmbkz, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ128rmk, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ128rmkz, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ128rr, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ128rrk, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ128rrkz, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ256rm, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ256rmb, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ256rmbk, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ256rmbkz, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ256rmk, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ256rmkz, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ256rr, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ256rrk, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZ256rrkz, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZrm, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZrmb, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZrmbk, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZrmbkz, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZrmk, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZrmkz, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZrr, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZrrk, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDZrrkz, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDrm, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUDrr, X86_INS_VPMINUD: vpminud */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ128rm, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ128rmb, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ128rmbk, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ128rmbkz, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ128rmk, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ128rmkz, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ128rr, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ128rrk, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ128rrkz, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ256rm, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ256rmb, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ256rmbk, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ256rmbkz, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ256rmk, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ256rmkz, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ256rr, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ256rrk, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZ256rrkz, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZrm, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZrmb, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZrmbk, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZrmbkz, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZrmk, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZrmkz, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZrr, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZrrk, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUQZrrkz, X86_INS_VPMINUQ: vpminuq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWYrm, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWYrr, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZ128rm, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZ128rmk, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZ128rmkz, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZ128rr, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZ128rrk, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZ128rrkz, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZ256rm, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZ256rmk, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZ256rmkz, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZ256rr, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZ256rrk, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZ256rrkz, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZrm, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZrmk, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZrmkz, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZrr, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZrrk, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWZrrkz, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWrm, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMINUWrr, X86_INS_VPMINUW: vpminuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVB2MZ128rr, X86_INS_VPMOVB2M: vpmovb2m */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVB2MZ256rr, X86_INS_VPMOVB2M: vpmovb2m */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVB2MZrr, X86_INS_VPMOVB2M: vpmovb2m */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVD2MZ128rr, X86_INS_VPMOVD2M: vpmovd2m */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVD2MZ256rr, X86_INS_VPMOVD2M: vpmovd2m */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVD2MZrr, X86_INS_VPMOVD2M: vpmovd2m */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZ128mr, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZ128mrk, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZ128rr, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZ128rrk, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZ128rrkz, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZ256mr, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZ256mrk, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZ256rr, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZ256rrk, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZ256rrkz, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZmr, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZmrk, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZrr, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZrrk, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDBZrrkz, X86_INS_VPMOVDB: vpmovdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZ128mr, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZ128mrk, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZ128rr, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZ128rrk, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZ128rrkz, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZ256mr, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZ256mrk, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZ256rr, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZ256rrk, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZ256rrkz, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZmr, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZmrk, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZrr, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZrrk, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVDWZrrkz, X86_INS_VPMOVDW: vpmovdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVM2BZ128rr, X86_INS_VPMOVM2B: vpmovm2b */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVM2BZ256rr, X86_INS_VPMOVM2B: vpmovm2b */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVM2BZrr, X86_INS_VPMOVM2B: vpmovm2b */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVM2DZ128rr, X86_INS_VPMOVM2D: vpmovm2d */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVM2DZ256rr, X86_INS_VPMOVM2D: vpmovm2d */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVM2DZrr, X86_INS_VPMOVM2D: vpmovm2d */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVM2QZ128rr, X86_INS_VPMOVM2Q: vpmovm2q */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVM2QZ256rr, X86_INS_VPMOVM2Q: vpmovm2q */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVM2QZrr, X86_INS_VPMOVM2Q: vpmovm2q */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVM2WZ128rr, X86_INS_VPMOVM2W: vpmovm2w */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVM2WZ256rr, X86_INS_VPMOVM2W: vpmovm2w */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVM2WZrr, X86_INS_VPMOVM2W: vpmovm2w */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVMSKBYrr, X86_INS_VPMOVMSKB: vpmovmskb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVMSKBrr, X86_INS_VPMOVMSKB: vpmovmskb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQ2MZ128rr, X86_INS_VPMOVQ2M: vpmovq2m */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQ2MZ256rr, X86_INS_VPMOVQ2M: vpmovq2m */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQ2MZrr, X86_INS_VPMOVQ2M: vpmovq2m */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZ128mr, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZ128mrk, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZ128rr, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZ128rrk, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZ128rrkz, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZ256mr, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZ256mrk, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZ256rr, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZ256rrk, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZ256rrkz, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZmr, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZmrk, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZrr, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZrrk, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQBZrrkz, X86_INS_VPMOVQB: vpmovqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZ128mr, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZ128mrk, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZ128rr, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZ128rrk, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZ128rrkz, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZ256mr, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZ256mrk, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZ256rr, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZ256rrk, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZ256rrkz, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZmr, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZmrk, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZrr, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZrrk, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQDZrrkz, X86_INS_VPMOVQD: vpmovqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZ128mr, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZ128mrk, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZ128rr, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZ128rrk, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZ128rrkz, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZ256mr, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZ256mrk, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZ256rr, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZ256rrk, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZ256rrkz, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZmr, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZmrk, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZrr, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZrrk, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVQWZrrkz, X86_INS_VPMOVQW: vpmovqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZ128mr, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZ128mrk, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZ128rr, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZ128rrk, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZ128rrkz, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZ256mr, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZ256mrk, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZ256rr, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZ256rrk, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZ256rrkz, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZmr, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZmrk, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZrr, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZrrk, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDBZrrkz, X86_INS_VPMOVSDB: vpmovsdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZ128mr, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZ128mrk, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZ128rr, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZ128rrk, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZ128rrkz, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZ256mr, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZ256mrk, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZ256rr, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZ256rrk, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZ256rrkz, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZmr, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZmrk, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZrr, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZrrk, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSDWZrrkz, X86_INS_VPMOVSDW: vpmovsdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZ128mr, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZ128mrk, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZ128rr, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZ128rrk, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZ128rrkz, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZ256mr, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZ256mrk, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZ256rr, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZ256rrk, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZ256rrkz, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZmr, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZmrk, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZrr, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZrrk, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQBZrrkz, X86_INS_VPMOVSQB: vpmovsqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZ128mr, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZ128mrk, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZ128rr, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZ128rrk, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZ128rrkz, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZ256mr, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZ256mrk, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZ256rr, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZ256rrk, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZ256rrkz, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZmr, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZmrk, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZrr, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZrrk, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQDZrrkz, X86_INS_VPMOVSQD: vpmovsqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZ128mr, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZ128mrk, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZ128rr, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZ128rrk, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZ128rrkz, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZ256mr, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZ256mrk, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZ256rr, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZ256rrk, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZ256rrkz, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZmr, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZmrk, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZrr, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZrrk, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSQWZrrkz, X86_INS_VPMOVSQW: vpmovsqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZ128mr, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZ128mrk, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZ128rr, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZ128rrk, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZ128rrkz, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZ256mr, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZ256mrk, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZ256rr, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZ256rrk, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZ256rrkz, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZmr, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZmrk, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZrr, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZrrk, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSWBZrrkz, X86_INS_VPMOVSWB: vpmovswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDYrm, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDYrr, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZ128rm, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZ128rmk, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZ128rmkz, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZ128rr, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZ128rrk, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZ128rrkz, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZ256rm, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZ256rmk, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZ256rmkz, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZ256rr, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZ256rrk, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZ256rrkz, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZrm, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZrmk, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZrmkz, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZrr, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZrrk, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDZrrkz, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDrm, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBDrr, X86_INS_VPMOVSXBD: vpmovsxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQYrm, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQYrr, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZ128rm, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZ128rmk, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZ128rmkz, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZ128rr, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZ128rrk, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZ128rrkz, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZ256rm, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZ256rmk, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZ256rmkz, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZ256rr, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZ256rrk, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZ256rrkz, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZrm, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZrmk, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZrmkz, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZrr, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZrrk, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQZrrkz, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQrm, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBQrr, X86_INS_VPMOVSXBQ: vpmovsxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWYrm, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWYrr, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZ128rm, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZ128rmk, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZ128rmkz, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZ128rr, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZ128rrk, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZ128rrkz, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZ256rm, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZ256rmk, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZ256rmkz, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZ256rr, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZ256rrk, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZ256rrkz, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZrm, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZrmk, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZrmkz, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZrr, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZrrk, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWZrrkz, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWrm, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXBWrr, X86_INS_VPMOVSXBW: vpmovsxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQYrm, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQYrr, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZ128rm, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZ128rmk, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZ128rmkz, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZ128rr, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZ128rrk, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZ128rrkz, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZ256rm, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZ256rmk, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZ256rmkz, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZ256rr, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZ256rrk, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZ256rrkz, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZrm, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZrmk, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZrmkz, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZrr, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZrrk, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQZrrkz, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQrm, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXDQrr, X86_INS_VPMOVSXDQ: vpmovsxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDYrm, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDYrr, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZ128rm, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZ128rmk, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZ128rmkz, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZ128rr, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZ128rrk, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZ128rrkz, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZ256rm, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZ256rmk, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZ256rmkz, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZ256rr, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZ256rrk, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZ256rrkz, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZrm, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZrmk, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZrmkz, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZrr, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZrrk, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDZrrkz, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDrm, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWDrr, X86_INS_VPMOVSXWD: vpmovsxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQYrm, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQYrr, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZ128rm, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZ128rmk, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZ128rmkz, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZ128rr, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZ128rrk, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZ128rrkz, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZ256rm, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZ256rmk, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZ256rmkz, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZ256rr, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZ256rrk, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZ256rrkz, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZrm, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZrmk, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZrmkz, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZrr, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZrrk, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQZrrkz, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQrm, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVSXWQrr, X86_INS_VPMOVSXWQ: vpmovsxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZ128mr, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZ128mrk, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZ128rr, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZ128rrk, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZ128rrkz, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZ256mr, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZ256mrk, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZ256rr, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZ256rrk, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZ256rrkz, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZmr, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZmrk, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZrr, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZrrk, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDBZrrkz, X86_INS_VPMOVUSDB: vpmovusdb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZ128mr, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZ128mrk, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZ128rr, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZ128rrk, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZ128rrkz, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZ256mr, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZ256mrk, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZ256rr, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZ256rrk, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZ256rrkz, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZmr, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZmrk, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZrr, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZrrk, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSDWZrrkz, X86_INS_VPMOVUSDW: vpmovusdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZ128mr, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZ128mrk, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZ128rr, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZ128rrk, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZ128rrkz, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZ256mr, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZ256mrk, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZ256rr, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZ256rrk, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZ256rrkz, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZmr, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZmrk, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZrr, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZrrk, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQBZrrkz, X86_INS_VPMOVUSQB: vpmovusqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZ128mr, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZ128mrk, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZ128rr, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZ128rrk, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZ128rrkz, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZ256mr, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZ256mrk, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZ256rr, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZ256rrk, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZ256rrkz, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZmr, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZmrk, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZrr, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZrrk, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQDZrrkz, X86_INS_VPMOVUSQD: vpmovusqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZ128mr, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZ128mrk, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZ128rr, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZ128rrk, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZ128rrkz, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZ256mr, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZ256mrk, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZ256rr, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZ256rrk, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZ256rrkz, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZmr, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZmrk, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZrr, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZrrk, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSQWZrrkz, X86_INS_VPMOVUSQW: vpmovusqw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZ128mr, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZ128mrk, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZ128rr, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZ128rrk, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZ128rrkz, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZ256mr, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZ256mrk, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZ256rr, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZ256rrk, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZ256rrkz, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZmr, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZmrk, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZrr, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZrrk, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVUSWBZrrkz, X86_INS_VPMOVUSWB: vpmovuswb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVW2MZ128rr, X86_INS_VPMOVW2M: vpmovw2m */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVW2MZ256rr, X86_INS_VPMOVW2M: vpmovw2m */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVW2MZrr, X86_INS_VPMOVW2M: vpmovw2m */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZ128mr, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZ128mrk, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZ128rr, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZ128rrk, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZ128rrkz, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZ256mr, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZ256mrk, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZ256rr, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZ256rrk, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZ256rrkz, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZmr, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZmrk, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZrr, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZrrk, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVWBZrrkz, X86_INS_VPMOVWB: vpmovwb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDYrm, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDYrr, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZ128rm, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZ128rmk, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZ128rmkz, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZ128rr, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZ128rrk, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZ128rrkz, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZ256rm, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZ256rmk, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZ256rmkz, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZ256rr, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZ256rrk, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZ256rrkz, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZrm, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZrmk, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZrmkz, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZrr, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZrrk, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDZrrkz, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDrm, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBDrr, X86_INS_VPMOVZXBD: vpmovzxbd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQYrm, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQYrr, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZ128rm, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZ128rmk, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZ128rmkz, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZ128rr, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZ128rrk, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZ128rrkz, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZ256rm, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZ256rmk, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZ256rmkz, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZ256rr, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZ256rrk, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZ256rrkz, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZrm, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZrmk, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZrmkz, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZrr, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZrrk, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQZrrkz, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQrm, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBQrr, X86_INS_VPMOVZXBQ: vpmovzxbq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWYrm, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWYrr, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZ128rm, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZ128rmk, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZ128rmkz, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZ128rr, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZ128rrk, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZ128rrkz, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZ256rm, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZ256rmk, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZ256rmkz, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZ256rr, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZ256rrk, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZ256rrkz, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZrm, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZrmk, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZrmkz, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZrr, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZrrk, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWZrrkz, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWrm, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXBWrr, X86_INS_VPMOVZXBW: vpmovzxbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQYrm, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQYrr, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZ128rm, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZ128rmk, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZ128rmkz, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZ128rr, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZ128rrk, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZ128rrkz, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZ256rm, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZ256rmk, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZ256rmkz, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZ256rr, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZ256rrk, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZ256rrkz, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZrm, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZrmk, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZrmkz, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZrr, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZrrk, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQZrrkz, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQrm, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXDQrr, X86_INS_VPMOVZXDQ: vpmovzxdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDYrm, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDYrr, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZ128rm, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZ128rmk, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZ128rmkz, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZ128rr, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZ128rrk, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZ128rrkz, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZ256rm, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZ256rmk, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZ256rmkz, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZ256rr, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZ256rrk, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZ256rrkz, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZrm, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZrmk, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZrmkz, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZrr, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZrrk, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDZrrkz, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDrm, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWDrr, X86_INS_VPMOVZXWD: vpmovzxwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQYrm, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQYrr, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZ128rm, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZ128rmk, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZ128rmkz, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZ128rr, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZ128rrk, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZ128rrkz, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZ256rm, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZ256rmk, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZ256rmkz, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZ256rr, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZ256rrk, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZ256rrkz, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZrm, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZrmk, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZrmkz, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZrr, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZrrk, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQZrrkz, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQrm, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMOVZXWQrr, X86_INS_VPMOVZXWQ: vpmovzxwq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQYrm, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQYrr, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ128rm, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ128rmb, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ128rmbk, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ128rmbkz, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ128rmk, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ128rmkz, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ128rr, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ128rrk, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ128rrkz, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ256rm, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ256rmb, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ256rmbk, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ256rmbkz, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ256rmk, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ256rmkz, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ256rr, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ256rrk, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZ256rrkz, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZrm, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZrmb, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZrmbk, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZrmbkz, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZrmk, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZrmkz, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZrr, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZrrk, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQZrrkz, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQrm, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULDQrr, X86_INS_VPMULDQ: vpmuldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWYrm, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWYrr, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZ128rm, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZ128rmk, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZ128rmkz, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZ128rr, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZ128rrk, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZ128rrkz, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZ256rm, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZ256rmk, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZ256rmkz, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZ256rr, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZ256rrk, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZ256rrkz, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZrm, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZrmk, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZrmkz, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZrr, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZrrk, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWZrrkz, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWrm, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHRSWrr, X86_INS_VPMULHRSW: vpmulhrsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWYrm, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWYrr, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZ128rm, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZ128rmk, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZ128rmkz, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZ128rr, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZ128rrk, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZ128rrkz, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZ256rm, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZ256rmk, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZ256rmkz, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZ256rr, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZ256rrk, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZ256rrkz, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZrm, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZrmk, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZrmkz, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZrr, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZrrk, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWZrrkz, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWrm, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHUWrr, X86_INS_VPMULHUW: vpmulhuw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWYrm, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWYrr, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZ128rm, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZ128rmk, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZ128rmkz, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZ128rr, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZ128rrk, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZ128rrkz, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZ256rm, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZ256rmk, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZ256rmkz, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZ256rr, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZ256rrk, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZ256rrkz, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZrm, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZrmk, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZrmkz, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZrr, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZrrk, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWZrrkz, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWrm, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULHWrr, X86_INS_VPMULHW: vpmulhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDYrm, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDYrr, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ128rm, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ128rmb, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ128rmbk, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ128rmbkz, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ128rmk, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ128rmkz, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ128rr, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ128rrk, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ128rrkz, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ256rm, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ256rmb, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ256rmbk, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ256rmbkz, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ256rmk, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ256rmkz, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ256rr, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ256rrk, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZ256rrkz, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZrm, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZrmb, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZrmbk, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZrmbkz, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZrmk, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZrmkz, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZrr, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZrrk, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDZrrkz, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDrm, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLDrr, X86_INS_VPMULLD: vpmulld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ128rm, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ128rmb, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ128rmbk, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ128rmbkz, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ128rmk, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ128rmkz, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ128rr, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ128rrk, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ128rrkz, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ256rm, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ256rmb, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ256rmbk, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ256rmbkz, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ256rmk, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ256rmkz, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ256rr, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ256rrk, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZ256rrkz, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZrm, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZrmb, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZrmbk, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZrmbkz, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZrmk, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZrmkz, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZrr, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZrrk, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLQZrrkz, X86_INS_VPMULLQ: vpmullq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWYrm, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWYrr, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZ128rm, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZ128rmk, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZ128rmkz, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZ128rr, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZ128rrk, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZ128rrkz, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZ256rm, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZ256rmk, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZ256rmkz, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZ256rr, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZ256rrk, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZ256rrkz, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZrm, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZrmk, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZrmkz, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZrr, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZrrk, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWZrrkz, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWrm, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULLWrr, X86_INS_VPMULLW: vpmullw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ128rm, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ128rmb, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ128rmbk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ128rmbkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ128rmk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ128rmkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ128rr, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ128rrk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ128rrkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ256rm, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ256rmb, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ256rmbk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ256rmbkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ256rmk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ256rmkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ256rr, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ256rrk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZ256rrkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZrm, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZrmb, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZrmbk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZrmbkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZrmk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZrmkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZrr, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZrrk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULTISHIFTQBZrrkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQYrm, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQYrr, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ128rm, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ128rmb, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ128rmbk, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ128rmbkz, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ128rmk, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ128rmkz, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ128rr, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ128rrk, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ128rrkz, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ256rm, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ256rmb, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ256rmbk, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ256rmbkz, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ256rmk, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ256rmkz, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ256rr, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ256rrk, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZ256rrkz, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZrm, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZrmb, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZrmbk, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZrmbkz, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZrmk, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZrmkz, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZrr, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZrrk, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQZrrkz, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQrm, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPMULUDQrr, X86_INS_VPMULUDQ: vpmuludq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZ128rm, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZ128rmk, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZ128rmkz, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZ128rr, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZ128rrk, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZ128rrkz, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZ256rm, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZ256rmk, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZ256rmkz, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZ256rr, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZ256rrk, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZ256rrkz, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZrm, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZrmk, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZrmkz, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZrr, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZrrk, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTBZrrkz, X86_INS_VPOPCNTB: vpopcntb */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ128rm, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ128rmb, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ128rmbk, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ128rmbkz, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ128rmk, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ128rmkz, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ128rr, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ128rrk, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ128rrkz, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ256rm, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ256rmb, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ256rmbk, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ256rmbkz, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ256rmk, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ256rmkz, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ256rr, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ256rrk, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZ256rrkz, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZrm, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZrmb, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZrmbk, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZrmbkz, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZrmk, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZrmkz, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZrr, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZrrk, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTDZrrkz, X86_INS_VPOPCNTD: vpopcntd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ128rm, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ128rmb, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ128rmbk, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ128rmbkz, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ128rmk, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ128rmkz, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ128rr, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ128rrk, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ128rrkz, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ256rm, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ256rmb, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ256rmbk, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ256rmbkz, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ256rmk, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ256rmkz, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ256rr, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ256rrk, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZ256rrkz, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZrm, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZrmb, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZrmbk, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZrmbkz, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZrmk, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZrmkz, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZrr, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZrrk, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTQZrrkz, X86_INS_VPOPCNTQ: vpopcntq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZ128rm, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZ128rmk, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZ128rmkz, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZ128rr, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZ128rrk, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZ128rrkz, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZ256rm, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZ256rmk, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZ256rmkz, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZ256rr, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZ256rrk, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZ256rrkz, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZrm, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZrmk, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZrmkz, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZrr, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZrrk, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPOPCNTWZrrkz, X86_INS_VPOPCNTW: vpopcntw */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ128rm, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ128rmb, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ128rmbk, X86_INS_VPORD: vpord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ128rmbkz, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ128rmk, X86_INS_VPORD: vpord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ128rmkz, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ128rr, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ128rrk, X86_INS_VPORD: vpord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ128rrkz, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ256rm, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ256rmb, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ256rmbk, X86_INS_VPORD: vpord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ256rmbkz, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ256rmk, X86_INS_VPORD: vpord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ256rmkz, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ256rr, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ256rrk, X86_INS_VPORD: vpord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZ256rrkz, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZrm, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZrmb, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZrmbk, X86_INS_VPORD: vpord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZrmbkz, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZrmk, X86_INS_VPORD: vpord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZrmkz, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZrr, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZrrk, X86_INS_VPORD: vpord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORDZrrkz, X86_INS_VPORD: vpord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ128rm, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ128rmb, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ128rmbk, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ128rmbkz, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ128rmk, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ128rmkz, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ128rr, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ128rrk, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ128rrkz, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ256rm, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ256rmb, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ256rmbk, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ256rmbkz, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ256rmk, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ256rmkz, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ256rr, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ256rrk, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZ256rrkz, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZrm, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZrmb, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZrmbk, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZrmbkz, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZrmk, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZrmkz, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZrr, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZrrk, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORQZrrkz, X86_INS_VPORQ: vporq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORYrm, X86_INS_VPOR: vpor */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORYrr, X86_INS_VPOR: vpor */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORrm, X86_INS_VPOR: vpor */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPORrr, X86_INS_VPOR: vpor */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPPERMrmr, X86_INS_VPPERM: vpperm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPPERMrrm, X86_INS_VPPERM: vpperm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPPERMrrr, X86_INS_VPPERM: vpperm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPPERMrrr_REV, X86_INS_VPPERM: vpperm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLDZ128mbi, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ128mbik, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ128mbikz, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ128mi, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ128mik, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ128mikz, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ128ri, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ128rik, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ128rikz, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ256mbi, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ256mbik, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ256mbikz, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ256mi, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ256mik, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ256mikz, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ256ri, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ256rik, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZ256rikz, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZmbi, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZmbik, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZmbikz, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZmi, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZmik, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZmikz, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZri, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZrik, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLDZrikz, X86_INS_VPROLD: vprold */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ128mbi, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ128mbik, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ128mbikz, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ128mi, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ128mik, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ128mikz, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ128ri, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ128rik, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ128rikz, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ256mbi, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ256mbik, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ256mbikz, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ256mi, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ256mik, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ256mikz, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ256ri, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ256rik, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZ256rikz, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZmbi, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZmbik, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZmbikz, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZmi, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZmik, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZmikz, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZri, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZrik, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLQZrikz, X86_INS_VPROLQ: vprolq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROLVDZ128rm, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ128rmb, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ128rmbk, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ128rmbkz, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ128rmk, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ128rmkz, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ128rr, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ128rrk, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ128rrkz, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ256rm, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ256rmb, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ256rmbk, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ256rmbkz, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ256rmk, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ256rmkz, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ256rr, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ256rrk, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZ256rrkz, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZrm, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZrmb, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZrmbk, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZrmbkz, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZrmk, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZrmkz, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZrr, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZrrk, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVDZrrkz, X86_INS_VPROLVD: vprolvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ128rm, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ128rmb, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ128rmbk, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ128rmbkz, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ128rmk, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ128rmkz, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ128rr, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ128rrk, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ128rrkz, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ256rm, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ256rmb, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ256rmbk, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ256rmbkz, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ256rmk, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ256rmkz, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ256rr, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ256rrk, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZ256rrkz, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZrm, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZrmb, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZrmbk, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZrmbkz, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZrmk, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZrmkz, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZrr, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZrrk, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROLVQZrrkz, X86_INS_VPROLVQ: vprolvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORDZ128mbi, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ128mbik, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ128mbikz, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ128mi, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ128mik, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ128mikz, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ128ri, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ128rik, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ128rikz, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ256mbi, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ256mbik, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ256mbikz, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ256mi, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ256mik, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ256mikz, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ256ri, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ256rik, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZ256rikz, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZmbi, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZmbik, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZmbikz, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZmi, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZmik, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZmikz, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZri, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZrik, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORDZrikz, X86_INS_VPRORD: vprord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ128mbi, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ128mbik, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ128mbikz, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ128mi, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ128mik, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ128mikz, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ128ri, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ128rik, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ128rikz, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ256mbi, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ256mbik, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ256mbikz, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ256mi, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ256mik, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ256mikz, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ256ri, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ256rik, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZ256rikz, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZmbi, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZmbik, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZmbikz, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZmi, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZmik, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZmikz, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZri, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZrik, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORQZrikz, X86_INS_VPRORQ: vprorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPRORVDZ128rm, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ128rmb, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ128rmbk, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ128rmbkz, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ128rmk, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ128rmkz, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ128rr, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ128rrk, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ128rrkz, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ256rm, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ256rmb, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ256rmbk, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ256rmbkz, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ256rmk, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ256rmkz, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ256rr, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ256rrk, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZ256rrkz, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZrm, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZrmb, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZrmbk, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZrmbkz, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZrmk, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZrmkz, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZrr, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZrrk, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVDZrrkz, X86_INS_VPRORVD: vprorvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ128rm, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ128rmb, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ128rmbk, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ128rmbkz, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ128rmk, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ128rmkz, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ128rr, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ128rrk, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ128rrkz, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ256rm, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ256rmb, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ256rmbk, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ256rmbkz, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ256rmk, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ256rmkz, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ256rr, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ256rrk, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZ256rrkz, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZrm, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZrmb, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZrmbk, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZrmbkz, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZrmk, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZrmkz, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZrr, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZrrk, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPRORVQZrrkz, X86_INS_VPRORVQ: vprorvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTBmi, X86_INS_VPROTB: vprotb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROTBmr, X86_INS_VPROTB: vprotb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTBri, X86_INS_VPROTB: vprotb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROTBrm, X86_INS_VPROTB: vprotb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTBrr, X86_INS_VPROTB: vprotb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTBrr_REV, X86_INS_VPROTB: vprotb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTDmi, X86_INS_VPROTD: vprotd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROTDmr, X86_INS_VPROTD: vprotd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTDri, X86_INS_VPROTD: vprotd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROTDrm, X86_INS_VPROTD: vprotd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTDrr, X86_INS_VPROTD: vprotd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTDrr_REV, X86_INS_VPROTD: vprotd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTQmi, X86_INS_VPROTQ: vprotq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROTQmr, X86_INS_VPROTQ: vprotq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTQri, X86_INS_VPROTQ: vprotq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROTQrm, X86_INS_VPROTQ: vprotq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTQrr, X86_INS_VPROTQ: vprotq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTQrr_REV, X86_INS_VPROTQ: vprotq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTWmi, X86_INS_VPROTW: vprotw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROTWmr, X86_INS_VPROTW: vprotw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTWri, X86_INS_VPROTW: vprotw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPROTWrm, X86_INS_VPROTW: vprotw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTWrr, X86_INS_VPROTW: vprotw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPROTWrr_REV, X86_INS_VPROTW: vprotw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSADBWYrm, X86_INS_VPSADBW: vpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSADBWYrr, X86_INS_VPSADBW: vpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSADBWZ128rm, X86_INS_VPSADBW: vpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSADBWZ128rr, X86_INS_VPSADBW: vpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSADBWZ256rm, X86_INS_VPSADBW: vpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSADBWZ256rr, X86_INS_VPSADBW: vpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSADBWZrm, X86_INS_VPSADBW: vpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSADBWZrr, X86_INS_VPSADBW: vpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSADBWrm, X86_INS_VPSADBW: vpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSADBWrr, X86_INS_VPSADBW: vpsadbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSCATTERDDZ128mr, X86_INS_VPSCATTERDD: vpscatterdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPSCATTERDDZ256mr, X86_INS_VPSCATTERDD: vpscatterdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPSCATTERDDZmr, X86_INS_VPSCATTERDD: vpscatterdd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSCATTERDQZ128mr, X86_INS_VPSCATTERDQ: vpscatterdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPSCATTERDQZ256mr, X86_INS_VPSCATTERDQ: vpscatterdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPSCATTERDQZmr, X86_INS_VPSCATTERDQ: vpscatterdq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSCATTERQDZ128mr, X86_INS_VPSCATTERQD: vpscatterqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPSCATTERQDZ256mr, X86_INS_VPSCATTERQD: vpscatterqd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPSCATTERQDZmr, X86_INS_VPSCATTERQD: vpscatterqd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSCATTERQQZ128mr, X86_INS_VPSCATTERQQ: vpscatterqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPSCATTERQQZ256mr, X86_INS_VPSCATTERQQ: vpscatterqq */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VPSCATTERQQZmr, X86_INS_VPSCATTERQQ: vpscatterqq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHABmr, X86_INS_VPSHAB: vpshab */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHABrm, X86_INS_VPSHAB: vpshab */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHABrr, X86_INS_VPSHAB: vpshab */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHABrr_REV, X86_INS_VPSHAB: vpshab */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHADmr, X86_INS_VPSHAD: vpshad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHADrm, X86_INS_VPSHAD: vpshad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHADrr, X86_INS_VPSHAD: vpshad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHADrr_REV, X86_INS_VPSHAD: vpshad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHAQmr, X86_INS_VPSHAQ: vpshaq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHAQrm, X86_INS_VPSHAQ: vpshaq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHAQrr, X86_INS_VPSHAQ: vpshaq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHAQrr_REV, X86_INS_VPSHAQ: vpshaq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHAWmr, X86_INS_VPSHAW: vpshaw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHAWrm, X86_INS_VPSHAW: vpshaw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHAWrr, X86_INS_VPSHAW: vpshaw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHAWrr_REV, X86_INS_VPSHAW: vpshaw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLBmr, X86_INS_VPSHLB: vpshlb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLBrm, X86_INS_VPSHLB: vpshlb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLBrr, X86_INS_VPSHLB: vpshlb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLBrr_REV, X86_INS_VPSHLB: vpshlb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDDZ128rmbi, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ128rmbik, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ128rmbikz, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ128rmi, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ128rmik, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ128rmikz, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ128rri, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ128rrik, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ128rrikz, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ256rmbi, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ256rmbik, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ256rmbikz, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ256rmi, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ256rmik, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ256rmikz, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ256rri, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ256rrik, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZ256rrikz, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZrmbi, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZrmbik, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZrmbikz, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZrmi, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZrmik, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZrmikz, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZrri, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZrrik, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDDZrrikz, X86_INS_VPSHLDD: vpshldd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ128rmbi, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ128rmbik, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ128rmbikz, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ128rmi, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ128rmik, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ128rmikz, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ128rri, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ128rrik, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ128rrikz, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ256rmbi, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ256rmbik, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ256rmbikz, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ256rmi, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ256rmik, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ256rmikz, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ256rri, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ256rrik, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZ256rrikz, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZrmbi, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZrmbik, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZrmbikz, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZrmi, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZrmik, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZrmikz, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZrri, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZrrik, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDQZrrikz, X86_INS_VPSHLDQ: vpshldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDVDZ128m, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ128mb, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ128mbk, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ128mbkz, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ128mk, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ128mkz, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ128r, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ128rk, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ128rkz, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ256m, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ256mb, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ256mbk, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ256mbkz, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ256mk, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ256mkz, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ256r, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ256rk, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZ256rkz, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZm, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZmb, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZmbk, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZmbkz, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZmk, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZmkz, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZr, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZrk, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVDZrkz, X86_INS_VPSHLDVD: vpshldvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ128m, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ128mb, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ128mbk, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ128mbkz, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ128mk, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ128mkz, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ128r, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ128rk, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ128rkz, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ256m, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ256mb, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ256mbk, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ256mbkz, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ256mk, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ256mkz, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ256r, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ256rk, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZ256rkz, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZm, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZmb, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZmbk, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZmbkz, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZmk, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZmkz, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZr, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZrk, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVQZrkz, X86_INS_VPSHLDVQ: vpshldvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZ128m, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZ128mk, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZ128mkz, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZ128r, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZ128rk, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZ128rkz, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZ256m, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZ256mk, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZ256mkz, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZ256r, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZ256rk, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZ256rkz, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZm, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZmk, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZmkz, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZr, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZrk, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDVWZrkz, X86_INS_VPSHLDVW: vpshldvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDWZ128rmi, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZ128rmik, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZ128rmikz, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZ128rri, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZ128rrik, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZ128rrikz, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZ256rmi, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZ256rmik, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZ256rmikz, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZ256rri, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZ256rrik, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZ256rrikz, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZrmi, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZrmik, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZrmikz, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZrri, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZrrik, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDWZrrikz, X86_INS_VPSHLDW: vpshldw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHLDmr, X86_INS_VPSHLD: vpshld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDrm, X86_INS_VPSHLD: vpshld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDrr, X86_INS_VPSHLD: vpshld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLDrr_REV, X86_INS_VPSHLD: vpshld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLQmr, X86_INS_VPSHLQ: vpshlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLQrm, X86_INS_VPSHLQ: vpshlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLQrr, X86_INS_VPSHLQ: vpshlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLQrr_REV, X86_INS_VPSHLQ: vpshlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLWmr, X86_INS_VPSHLW: vpshlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLWrm, X86_INS_VPSHLW: vpshlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLWrr, X86_INS_VPSHLW: vpshlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHLWrr_REV, X86_INS_VPSHLW: vpshlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDDZ128rmbi, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ128rmbik, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ128rmbikz, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ128rmi, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ128rmik, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ128rmikz, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ128rri, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ128rrik, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ128rrikz, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ256rmbi, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ256rmbik, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ256rmbikz, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ256rmi, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ256rmik, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ256rmikz, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ256rri, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ256rrik, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZ256rrikz, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZrmbi, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZrmbik, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZrmbikz, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZrmi, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZrmik, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZrmikz, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZrri, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZrrik, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDDZrrikz, X86_INS_VPSHRDD: vpshrdd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ128rmbi, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ128rmbik, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ128rmbikz, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ128rmi, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ128rmik, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ128rmikz, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ128rri, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ128rrik, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ128rrikz, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ256rmbi, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ256rmbik, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ256rmbikz, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ256rmi, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ256rmik, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ256rmikz, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ256rri, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ256rrik, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZ256rrikz, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZrmbi, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZrmbik, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZrmbikz, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZrmi, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZrmik, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZrmikz, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZrri, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZrrik, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDQZrrikz, X86_INS_VPSHRDQ: vpshrdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDVDZ128m, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ128mb, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ128mbk, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ128mbkz, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ128mk, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ128mkz, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ128r, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ128rk, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ128rkz, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ256m, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ256mb, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ256mbk, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ256mbkz, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ256mk, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ256mkz, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ256r, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ256rk, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZ256rkz, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZm, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZmb, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZmbk, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZmbkz, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZmk, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZmkz, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZr, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZrk, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVDZrkz, X86_INS_VPSHRDVD: vpshrdvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ128m, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ128mb, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ128mbk, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ128mbkz, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ128mk, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ128mkz, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ128r, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ128rk, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ128rkz, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ256m, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ256mb, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ256mbk, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ256mbkz, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ256mk, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ256mkz, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ256r, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ256rk, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZ256rkz, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZm, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZmb, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZmbk, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZmbkz, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZmk, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZmkz, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZr, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZrk, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVQZrkz, X86_INS_VPSHRDVQ: vpshrdvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZ128m, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZ128mk, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZ128mkz, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZ128r, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZ128rk, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZ128rkz, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZ256m, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZ256mk, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZ256mkz, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZ256r, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZ256rk, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZ256rkz, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZm, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZmk, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZmkz, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZr, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZrk, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDVWZrkz, X86_INS_VPSHRDVW: vpshrdvw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHRDWZ128rmi, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZ128rmik, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZ128rmikz, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZ128rri, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZ128rrik, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZ128rrikz, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZ256rmi, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZ256rmik, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZ256rmikz, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZ256rri, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZ256rrik, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZ256rrikz, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZrmi, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZrmik, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZrmikz, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZrri, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZrrik, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHRDWZrrikz, X86_INS_VPSHRDW: vpshrdw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFBITQMBZ128rm, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBITQMBZ128rmk, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBITQMBZ128rr, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBITQMBZ128rrk, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBITQMBZ256rm, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBITQMBZ256rmk, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBITQMBZ256rr, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBITQMBZ256rrk, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBITQMBZrm, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBITQMBZrmk, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBITQMBZrr, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBITQMBZrrk, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBYrm, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBYrr, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZ128rm, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZ128rmk, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZ128rmkz, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZ128rr, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZ128rrk, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZ128rrkz, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZ256rm, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZ256rmk, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZ256rmkz, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZ256rr, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZ256rrk, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZ256rrkz, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZrm, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZrmk, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZrmkz, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZrr, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZrrk, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBZrrkz, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBrm, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFBrr, X86_INS_VPSHUFB: vpshufb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSHUFDYmi, X86_INS_VPSHUFD: vpshufd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFDYri, X86_INS_VPSHUFD: vpshufd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFDZ128mbi, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ128mbik, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ128mbikz, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ128mi, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ128mik, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ128mikz, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ128ri, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ128rik, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ128rikz, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ256mbi, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ256mbik, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ256mbikz, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ256mi, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ256mik, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ256mikz, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ256ri, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ256rik, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZ256rikz, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZmbi, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZmbik, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZmbikz, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZmi, X86_INS_VPSHUFD: vpshufd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFDZmik, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZmikz, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZri, X86_INS_VPSHUFD: vpshufd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFDZrik, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDZrikz, X86_INS_VPSHUFD: vpshufd */ + 0, + { 0 } +}, + +{ /* X86_VPSHUFDmi, X86_INS_VPSHUFD: vpshufd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFDri, X86_INS_VPSHUFD: vpshufd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWYmi, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWYri, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZ128mi, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZ128mik, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZ128mikz, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZ128ri, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZ128rik, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZ128rikz, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZ256mi, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZ256mik, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZ256mikz, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZ256ri, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZ256rik, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZ256rikz, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZmi, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZmik, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZmikz, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZri, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZrik, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWZrikz, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWmi, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFHWri, X86_INS_VPSHUFHW: vpshufhw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWYmi, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWYri, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZ128mi, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZ128mik, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZ128mikz, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZ128ri, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZ128rik, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZ128rikz, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZ256mi, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZ256mik, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZ256mikz, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZ256ri, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZ256rik, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZ256rikz, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZmi, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZmik, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZmikz, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZri, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZrik, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWZrikz, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWmi, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSHUFLWri, X86_INS_VPSHUFLW: vpshuflw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSIGNBYrm, X86_INS_VPSIGNB: vpsignb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSIGNBYrr, X86_INS_VPSIGNB: vpsignb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSIGNBrm, X86_INS_VPSIGNB: vpsignb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSIGNBrr, X86_INS_VPSIGNB: vpsignb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSIGNDYrm, X86_INS_VPSIGND: vpsignd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSIGNDYrr, X86_INS_VPSIGND: vpsignd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSIGNDrm, X86_INS_VPSIGND: vpsignd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSIGNDrr, X86_INS_VPSIGND: vpsignd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSIGNWYrm, X86_INS_VPSIGNW: vpsignw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSIGNWYrr, X86_INS_VPSIGNW: vpsignw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSIGNWrm, X86_INS_VPSIGNW: vpsignw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSIGNWrr, X86_INS_VPSIGNW: vpsignw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDQYri, X86_INS_VPSLLDQ: vpslldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLDQZ128rm, X86_INS_VPSLLDQ: vpslldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDQZ128rr, X86_INS_VPSLLDQ: vpslldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDQZ256rm, X86_INS_VPSLLDQ: vpslldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDQZ256rr, X86_INS_VPSLLDQ: vpslldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDQZrm, X86_INS_VPSLLDQ: vpslldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDQZrr, X86_INS_VPSLLDQ: vpslldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDQri, X86_INS_VPSLLDQ: vpslldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLDYri, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLDYrm, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDYrr, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDZ128mbi, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128mbik, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128mbikz, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128mi, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128mik, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128mikz, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128ri, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128rik, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128rikz, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128rm, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128rmk, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128rmkz, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128rr, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128rrk, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ128rrkz, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256mbi, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256mbik, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256mbikz, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256mi, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256mik, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256mikz, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256ri, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256rik, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256rikz, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256rm, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256rmk, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256rmkz, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256rr, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256rrk, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZ256rrkz, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZmbi, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZmbik, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZmbikz, X86_INS_VPSLLD: vpslld */ + 0, + { 0 } +}, + +{ /* X86_VPSLLDZmi, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLDZmik, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLDZmikz, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLDZri, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLDZrik, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLDZrikz, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLDZrm, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDZrmk, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDZrmkz, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDZrr, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDZrrk, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDZrrkz, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDri, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLDrm, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLDrr, X86_INS_VPSLLD: vpslld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQYri, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQYrm, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQYrr, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZ128mbi, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ128mbik, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ128mbikz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ128mi, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ128mik, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ128mikz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ128ri, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ128rik, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ128rikz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ128rm, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZ128rmk, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZ128rmkz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZ128rr, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZ128rrk, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZ128rrkz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZ256mbi, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ256mbik, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ256mbikz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ256mi, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ256mik, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ256mikz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ256ri, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ256rik, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ256rikz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZ256rm, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZ256rmk, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZ256rmkz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZ256rr, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZ256rrk, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZ256rrkz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZmbi, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZmbik, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZmbikz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZmi, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZmik, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZmikz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZri, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZrik, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZrikz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQZrm, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZrmk, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZrmkz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZrr, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZrrk, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQZrrkz, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQri, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLQrm, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLQrr, X86_INS_VPSLLQ: vpsllq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVDYrm, X86_INS_VPSLLVD: vpsllvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVDYrr, X86_INS_VPSLLVD: vpsllvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVDZ128rm, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ128rmb, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ128rmbk, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ128rmbkz, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ128rmk, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ128rmkz, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ128rr, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ128rrk, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ128rrkz, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ256rm, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ256rmb, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ256rmbk, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ256rmbkz, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ256rmk, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ256rmkz, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ256rr, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ256rrk, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZ256rrkz, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZrm, X86_INS_VPSLLVD: vpsllvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVDZrmb, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZrmbk, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZrmbkz, X86_INS_VPSLLVD: vpsllvd */ + 0, + { 0 } +}, + +{ /* X86_VPSLLVDZrmk, X86_INS_VPSLLVD: vpsllvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVDZrmkz, X86_INS_VPSLLVD: vpsllvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVDZrr, X86_INS_VPSLLVD: vpsllvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVDZrrk, X86_INS_VPSLLVD: vpsllvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVDZrrkz, X86_INS_VPSLLVD: vpsllvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVDrm, X86_INS_VPSLLVD: vpsllvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVDrr, X86_INS_VPSLLVD: vpsllvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQYrm, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQYrr, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ128rm, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ128rmb, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ128rmbk, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ128rmbkz, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ128rmk, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ128rmkz, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ128rr, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ128rrk, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ128rrkz, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ256rm, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ256rmb, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ256rmbk, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ256rmbkz, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ256rmk, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ256rmkz, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ256rr, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ256rrk, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZ256rrkz, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZrm, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZrmb, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZrmbk, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZrmbkz, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZrmk, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZrmkz, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZrr, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZrrk, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQZrrkz, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQrm, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVQrr, X86_INS_VPSLLVQ: vpsllvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZ128rm, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZ128rmk, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZ128rmkz, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZ128rr, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZ128rrk, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZ128rrkz, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZ256rm, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZ256rmk, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZ256rmkz, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZ256rr, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZ256rrk, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZ256rrkz, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZrm, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZrmk, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZrmkz, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZrr, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZrrk, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLVWZrrkz, X86_INS_VPSLLVW: vpsllvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWYri, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWYrm, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWYrr, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZ128mi, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZ128mik, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZ128mikz, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZ128ri, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZ128rik, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZ128rikz, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZ128rm, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZ128rmk, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZ128rmkz, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZ128rr, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZ128rrk, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZ128rrkz, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZ256mi, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZ256mik, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZ256mikz, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZ256ri, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZ256rik, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZ256rikz, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZ256rm, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZ256rmk, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZ256rmkz, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZ256rr, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZ256rrk, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZ256rrkz, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZmi, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZmik, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZmikz, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZri, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZrik, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZrikz, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWZrm, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZrmk, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZrmkz, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZrr, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZrrk, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWZrrkz, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWri, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSLLWrm, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSLLWrr, X86_INS_VPSLLW: vpsllw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRADYri, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRADYrm, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRADYrr, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRADZ128mbi, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128mbik, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128mbikz, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128mi, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128mik, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128mikz, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128ri, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128rik, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128rikz, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128rm, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128rmk, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128rmkz, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128rr, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128rrk, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ128rrkz, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256mbi, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256mbik, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256mbikz, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256mi, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256mik, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256mikz, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256ri, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256rik, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256rikz, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256rm, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256rmk, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256rmkz, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256rr, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256rrk, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZ256rrkz, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZmbi, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZmbik, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZmbikz, X86_INS_VPSRAD: vpsrad */ + 0, + { 0 } +}, + +{ /* X86_VPSRADZmi, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRADZmik, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRADZmikz, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRADZri, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRADZrik, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRADZrikz, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRADZrm, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRADZrmk, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRADZrmkz, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRADZrr, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRADZrrk, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRADZrrkz, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRADri, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRADrm, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRADrr, X86_INS_VPSRAD: vpsrad */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZ128mbi, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ128mbik, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ128mbikz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ128mi, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ128mik, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ128mikz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ128ri, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ128rik, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ128rikz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ128rm, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZ128rmk, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZ128rmkz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZ128rr, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZ128rrk, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZ128rrkz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZ256mbi, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ256mbik, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ256mbikz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ256mi, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ256mik, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ256mikz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ256ri, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ256rik, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ256rikz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZ256rm, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZ256rmk, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZ256rmkz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZ256rr, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZ256rrk, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZ256rrkz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZmbi, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZmbik, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZmbikz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZmi, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZmik, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZmikz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZri, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZrik, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZrikz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAQZrm, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZrmk, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZrmkz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZrr, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZrrk, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAQZrrkz, X86_INS_VPSRAQ: vpsraq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVDYrm, X86_INS_VPSRAVD: vpsravd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVDYrr, X86_INS_VPSRAVD: vpsravd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVDZ128rm, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ128rmb, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ128rmbk, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ128rmbkz, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ128rmk, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ128rmkz, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ128rr, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ128rrk, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ128rrkz, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ256rm, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ256rmb, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ256rmbk, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ256rmbkz, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ256rmk, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ256rmkz, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ256rr, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ256rrk, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZ256rrkz, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZrm, X86_INS_VPSRAVD: vpsravd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVDZrmb, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZrmbk, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZrmbkz, X86_INS_VPSRAVD: vpsravd */ + 0, + { 0 } +}, + +{ /* X86_VPSRAVDZrmk, X86_INS_VPSRAVD: vpsravd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVDZrmkz, X86_INS_VPSRAVD: vpsravd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVDZrr, X86_INS_VPSRAVD: vpsravd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVDZrrk, X86_INS_VPSRAVD: vpsravd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVDZrrkz, X86_INS_VPSRAVD: vpsravd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVDrm, X86_INS_VPSRAVD: vpsravd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVDrr, X86_INS_VPSRAVD: vpsravd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ128rm, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ128rmb, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ128rmbk, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ128rmbkz, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ128rmk, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ128rmkz, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ128rr, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ128rrk, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ128rrkz, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ256rm, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ256rmb, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ256rmbk, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ256rmbkz, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ256rmk, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ256rmkz, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ256rr, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ256rrk, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZ256rrkz, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZrm, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZrmb, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZrmbk, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZrmbkz, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZrmk, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZrmkz, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZrr, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZrrk, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVQZrrkz, X86_INS_VPSRAVQ: vpsravq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZ128rm, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZ128rmk, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZ128rmkz, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZ128rr, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZ128rrk, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZ128rrkz, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZ256rm, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZ256rmk, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZ256rmkz, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZ256rr, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZ256rrk, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZ256rrkz, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZrm, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZrmk, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZrmkz, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZrr, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZrrk, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAVWZrrkz, X86_INS_VPSRAVW: vpsravw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWYri, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWYrm, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWYrr, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZ128mi, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZ128mik, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZ128mikz, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZ128ri, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZ128rik, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZ128rikz, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZ128rm, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZ128rmk, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZ128rmkz, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZ128rr, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZ128rrk, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZ128rrkz, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZ256mi, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZ256mik, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZ256mikz, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZ256ri, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZ256rik, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZ256rikz, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZ256rm, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZ256rmk, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZ256rmkz, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZ256rr, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZ256rrk, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZ256rrkz, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZmi, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZmik, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZmikz, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZri, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZrik, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZrikz, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWZrm, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZrmk, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZrmkz, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZrr, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZrrk, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWZrrkz, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWri, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRAWrm, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRAWrr, X86_INS_VPSRAW: vpsraw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDQYri, X86_INS_VPSRLDQ: vpsrldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLDQZ128rm, X86_INS_VPSRLDQ: vpsrldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDQZ128rr, X86_INS_VPSRLDQ: vpsrldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDQZ256rm, X86_INS_VPSRLDQ: vpsrldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDQZ256rr, X86_INS_VPSRLDQ: vpsrldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDQZrm, X86_INS_VPSRLDQ: vpsrldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDQZrr, X86_INS_VPSRLDQ: vpsrldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDQri, X86_INS_VPSRLDQ: vpsrldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLDYri, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLDYrm, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDYrr, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDZ128mbi, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128mbik, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128mbikz, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128mi, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128mik, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128mikz, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128ri, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128rik, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128rikz, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128rm, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128rmk, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128rmkz, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128rr, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128rrk, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ128rrkz, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256mbi, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256mbik, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256mbikz, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256mi, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256mik, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256mikz, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256ri, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256rik, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256rikz, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256rm, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256rmk, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256rmkz, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256rr, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256rrk, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZ256rrkz, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZmbi, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZmbik, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZmbikz, X86_INS_VPSRLD: vpsrld */ + 0, + { 0 } +}, + +{ /* X86_VPSRLDZmi, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLDZmik, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLDZmikz, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLDZri, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLDZrik, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLDZrikz, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLDZrm, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDZrmk, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDZrmkz, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDZrr, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDZrrk, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDZrrkz, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDri, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLDrm, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLDrr, X86_INS_VPSRLD: vpsrld */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQYri, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQYrm, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQYrr, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZ128mbi, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ128mbik, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ128mbikz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ128mi, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ128mik, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ128mikz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ128ri, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ128rik, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ128rikz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ128rm, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZ128rmk, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZ128rmkz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZ128rr, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZ128rrk, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZ128rrkz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZ256mbi, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ256mbik, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ256mbikz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ256mi, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ256mik, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ256mikz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ256ri, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ256rik, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ256rikz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZ256rm, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZ256rmk, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZ256rmkz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZ256rr, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZ256rrk, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZ256rrkz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZmbi, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZmbik, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZmbikz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZmi, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZmik, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZmikz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZri, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZrik, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZrikz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQZrm, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZrmk, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZrmkz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZrr, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZrrk, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQZrrkz, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQri, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLQrm, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLQrr, X86_INS_VPSRLQ: vpsrlq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVDYrm, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVDYrr, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVDZ128rm, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ128rmb, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ128rmbk, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ128rmbkz, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ128rmk, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ128rmkz, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ128rr, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ128rrk, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ128rrkz, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ256rm, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ256rmb, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ256rmbk, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ256rmbkz, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ256rmk, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ256rmkz, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ256rr, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ256rrk, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZ256rrkz, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZrm, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVDZrmb, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZrmbk, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZrmbkz, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { 0 } +}, + +{ /* X86_VPSRLVDZrmk, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVDZrmkz, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVDZrr, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVDZrrk, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVDZrrkz, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVDrm, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVDrr, X86_INS_VPSRLVD: vpsrlvd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQYrm, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQYrr, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ128rm, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ128rmb, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ128rmbk, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ128rmbkz, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ128rmk, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ128rmkz, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ128rr, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ128rrk, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ128rrkz, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ256rm, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ256rmb, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ256rmbk, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ256rmbkz, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ256rmk, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ256rmkz, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ256rr, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ256rrk, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZ256rrkz, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZrm, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZrmb, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZrmbk, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZrmbkz, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZrmk, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZrmkz, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZrr, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZrrk, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQZrrkz, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQrm, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVQrr, X86_INS_VPSRLVQ: vpsrlvq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZ128rm, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZ128rmk, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZ128rmkz, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZ128rr, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZ128rrk, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZ128rrkz, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZ256rm, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZ256rmk, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZ256rmkz, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZ256rr, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZ256rrk, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZ256rrkz, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZrm, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZrmk, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZrmkz, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZrr, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZrrk, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLVWZrrkz, X86_INS_VPSRLVW: vpsrlvw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWYri, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWYrm, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWYrr, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZ128mi, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZ128mik, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZ128mikz, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZ128ri, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZ128rik, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZ128rikz, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZ128rm, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZ128rmk, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZ128rmkz, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZ128rr, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZ128rrk, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZ128rrkz, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZ256mi, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZ256mik, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZ256mikz, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZ256ri, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZ256rik, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZ256rikz, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZ256rm, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZ256rmk, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZ256rmkz, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZ256rr, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZ256rrk, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZ256rrkz, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZmi, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZmik, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZmikz, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZri, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZrik, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZrikz, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWZrm, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZrmk, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZrmkz, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZrr, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZrrk, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWZrrkz, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWri, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPSRLWrm, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSRLWrr, X86_INS_VPSRLW: vpsrlw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBYrm, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBYrr, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZ128rm, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZ128rmk, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZ128rmkz, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZ128rr, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZ128rrk, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZ128rrkz, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZ256rm, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZ256rmk, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZ256rmkz, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZ256rr, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZ256rrk, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZ256rrkz, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZrm, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZrmk, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZrmkz, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZrr, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZrrk, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBZrrkz, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBrm, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBBrr, X86_INS_VPSUBB: vpsubb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDYrm, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDYrr, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ128rm, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ128rmb, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ128rmbk, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ128rmbkz, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ128rmk, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ128rmkz, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ128rr, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ128rrk, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ128rrkz, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ256rm, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ256rmb, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ256rmbk, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ256rmbkz, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ256rmk, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ256rmkz, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ256rr, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ256rrk, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZ256rrkz, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZrm, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZrmb, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZrmbk, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZrmbkz, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZrmk, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZrmkz, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZrr, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZrrk, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDZrrkz, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDrm, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBDrr, X86_INS_VPSUBD: vpsubd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQYrm, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQYrr, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ128rm, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ128rmb, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ128rmbk, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ128rmbkz, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ128rmk, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ128rmkz, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ128rr, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ128rrk, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ128rrkz, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ256rm, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ256rmb, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ256rmbk, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ256rmbkz, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ256rmk, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ256rmkz, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ256rr, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ256rrk, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZ256rrkz, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZrm, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZrmb, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZrmbk, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZrmbkz, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZrmk, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZrmkz, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZrr, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZrrk, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQZrrkz, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQrm, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBQrr, X86_INS_VPSUBQ: vpsubq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBYrm, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBYrr, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZ128rm, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZ128rmk, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZ128rmkz, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZ128rr, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZ128rrk, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZ128rrkz, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZ256rm, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZ256rmk, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZ256rmkz, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZ256rr, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZ256rrk, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZ256rrkz, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZrm, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZrmk, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZrmkz, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZrr, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZrrk, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBZrrkz, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBrm, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSBrr, X86_INS_VPSUBSB: vpsubsb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWYrm, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWYrr, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZ128rm, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZ128rmk, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZ128rmkz, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZ128rr, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZ128rrk, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZ128rrkz, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZ256rm, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZ256rmk, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZ256rmkz, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZ256rr, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZ256rrk, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZ256rrkz, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZrm, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZrmk, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZrmkz, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZrr, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZrrk, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWZrrkz, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWrm, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBSWrr, X86_INS_VPSUBSW: vpsubsw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBYrm, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBYrr, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZ128rm, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZ128rmk, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZ128rmkz, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZ128rr, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZ128rrk, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZ128rrkz, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZ256rm, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZ256rmk, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZ256rmkz, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZ256rr, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZ256rrk, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZ256rrkz, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZrm, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZrmk, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZrmkz, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZrr, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZrrk, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBZrrkz, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBrm, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSBrr, X86_INS_VPSUBUSB: vpsubusb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWYrm, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWYrr, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZ128rm, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZ128rmk, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZ128rmkz, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZ128rr, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZ128rrk, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZ128rrkz, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZ256rm, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZ256rmk, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZ256rmkz, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZ256rr, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZ256rrk, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZ256rrkz, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZrm, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZrmk, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZrmkz, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZrr, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZrrk, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWZrrkz, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWrm, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBUSWrr, X86_INS_VPSUBUSW: vpsubusw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWYrm, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWYrr, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZ128rm, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZ128rmk, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZ128rmkz, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZ128rr, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZ128rrk, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZ128rrkz, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZ256rm, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZ256rmk, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZ256rmkz, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZ256rr, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZ256rrk, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZ256rrkz, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZrm, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZrmk, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZrmkz, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZrr, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZrrk, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWZrrkz, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWrm, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPSUBWrr, X86_INS_VPSUBW: vpsubw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTERNLOGDZ128rmbi, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ128rmbik, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ128rmbikz, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ128rmi, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ128rmik, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ128rmikz, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ128rri, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ128rrik, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ128rrikz, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ256rmbi, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ256rmbik, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ256rmbikz, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ256rmi, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ256rmik, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ256rmikz, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ256rri, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ256rrik, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZ256rrikz, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZrmbi, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZrmbik, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZrmbikz, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZrmi, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZrmik, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZrmikz, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZrri, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZrrik, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGDZrrikz, X86_INS_VPTERNLOGD: vpternlogd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ128rmbi, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ128rmbik, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ128rmbikz, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ128rmi, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ128rmik, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ128rmikz, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ128rri, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ128rrik, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ128rrikz, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ256rmbi, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ256rmbik, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ256rmbikz, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ256rmi, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ256rmik, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ256rmikz, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ256rri, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ256rrik, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZ256rrikz, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZrmbi, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZrmbik, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZrmbikz, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZrmi, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZrmik, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZrmikz, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZrri, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZrrik, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTERNLOGQZrrikz, X86_INS_VPTERNLOGQ: vpternlogq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VPTESTMBZ128rm, X86_INS_VPTESTMB: vptestmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMBZ128rmk, X86_INS_VPTESTMB: vptestmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMBZ128rr, X86_INS_VPTESTMB: vptestmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMBZ128rrk, X86_INS_VPTESTMB: vptestmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMBZ256rm, X86_INS_VPTESTMB: vptestmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMBZ256rmk, X86_INS_VPTESTMB: vptestmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMBZ256rr, X86_INS_VPTESTMB: vptestmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMBZ256rrk, X86_INS_VPTESTMB: vptestmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMBZrm, X86_INS_VPTESTMB: vptestmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMBZrmk, X86_INS_VPTESTMB: vptestmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMBZrr, X86_INS_VPTESTMB: vptestmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMBZrrk, X86_INS_VPTESTMB: vptestmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZ128rm, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZ128rmb, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZ128rmbk, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZ128rmk, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZ128rr, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZ128rrk, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZ256rm, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZ256rmb, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZ256rmbk, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZ256rmk, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZ256rr, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZ256rrk, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZrm, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZrmb, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZrmbk, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZrmk, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZrr, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMDZrrk, X86_INS_VPTESTMD: vptestmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZ128rm, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZ128rmb, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZ128rmbk, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZ128rmk, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZ128rr, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZ128rrk, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZ256rm, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZ256rmb, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZ256rmbk, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZ256rmk, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZ256rr, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZ256rrk, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZrm, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZrmb, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZrmbk, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZrmk, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZrr, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMQZrrk, X86_INS_VPTESTMQ: vptestmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMWZ128rm, X86_INS_VPTESTMW: vptestmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMWZ128rmk, X86_INS_VPTESTMW: vptestmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMWZ128rr, X86_INS_VPTESTMW: vptestmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMWZ128rrk, X86_INS_VPTESTMW: vptestmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMWZ256rm, X86_INS_VPTESTMW: vptestmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMWZ256rmk, X86_INS_VPTESTMW: vptestmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMWZ256rr, X86_INS_VPTESTMW: vptestmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMWZ256rrk, X86_INS_VPTESTMW: vptestmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMWZrm, X86_INS_VPTESTMW: vptestmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMWZrmk, X86_INS_VPTESTMW: vptestmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMWZrr, X86_INS_VPTESTMW: vptestmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTMWZrrk, X86_INS_VPTESTMW: vptestmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMBZ128rm, X86_INS_VPTESTNMB: vptestnmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMBZ128rmk, X86_INS_VPTESTNMB: vptestnmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMBZ128rr, X86_INS_VPTESTNMB: vptestnmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMBZ128rrk, X86_INS_VPTESTNMB: vptestnmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMBZ256rm, X86_INS_VPTESTNMB: vptestnmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMBZ256rmk, X86_INS_VPTESTNMB: vptestnmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMBZ256rr, X86_INS_VPTESTNMB: vptestnmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMBZ256rrk, X86_INS_VPTESTNMB: vptestnmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMBZrm, X86_INS_VPTESTNMB: vptestnmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMBZrmk, X86_INS_VPTESTNMB: vptestnmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMBZrr, X86_INS_VPTESTNMB: vptestnmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMBZrrk, X86_INS_VPTESTNMB: vptestnmb */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZ128rm, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZ128rmb, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZ128rmbk, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZ128rmk, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZ128rr, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZ128rrk, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZ256rm, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZ256rmb, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZ256rmbk, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZ256rmk, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZ256rr, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZ256rrk, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZrm, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZrmb, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZrmbk, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZrmk, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZrr, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMDZrrk, X86_INS_VPTESTNMD: vptestnmd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZ128rm, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZ128rmb, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZ128rmbk, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZ128rmk, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZ128rr, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZ128rrk, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZ256rm, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZ256rmb, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZ256rmbk, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZ256rmk, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZ256rr, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZ256rrk, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZrm, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZrmb, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZrmbk, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZrmk, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZrr, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMQZrrk, X86_INS_VPTESTNMQ: vptestnmq */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMWZ128rm, X86_INS_VPTESTNMW: vptestnmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMWZ128rmk, X86_INS_VPTESTNMW: vptestnmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMWZ128rr, X86_INS_VPTESTNMW: vptestnmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMWZ128rrk, X86_INS_VPTESTNMW: vptestnmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMWZ256rm, X86_INS_VPTESTNMW: vptestnmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMWZ256rmk, X86_INS_VPTESTNMW: vptestnmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMWZ256rr, X86_INS_VPTESTNMW: vptestnmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMWZ256rrk, X86_INS_VPTESTNMW: vptestnmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMWZrm, X86_INS_VPTESTNMW: vptestnmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMWZrmk, X86_INS_VPTESTNMW: vptestnmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMWZrr, X86_INS_VPTESTNMW: vptestnmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTNMWZrrk, X86_INS_VPTESTNMW: vptestnmw */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTYrm, X86_INS_VPTEST: vptest */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTYrr, X86_INS_VPTEST: vptest */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTrm, X86_INS_VPTEST: vptest */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPTESTrr, X86_INS_VPTEST: vptest */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWYrm, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWYrr, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZ128rm, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZ128rmk, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZ128rmkz, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZ128rr, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZ128rrk, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZ128rrkz, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZ256rm, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZ256rmk, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZ256rmkz, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZ256rr, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZ256rrk, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZ256rrkz, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZrm, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZrmk, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZrmkz, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZrr, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZrrk, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWZrrkz, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWrm, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHBWrr, X86_INS_VPUNPCKHBW: vpunpckhbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQYrm, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQYrr, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ128rm, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ128rmb, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ128rmbk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ128rmbkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ128rmk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ128rmkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ128rr, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ128rrk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ128rrkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ256rm, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ256rmb, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ256rmbk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ256rmbkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ256rmk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ256rmkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ256rr, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ256rrk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZ256rrkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZrm, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZrmb, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZrmbk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZrmbkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZrmk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZrmkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZrr, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZrrk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQZrrkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQrm, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHDQrr, X86_INS_VPUNPCKHDQ: vpunpckhdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQYrm, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQYrr, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ128rm, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ128rmb, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ128rmbk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ128rmbkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ128rmk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ128rmkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ128rr, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ128rrk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ128rrkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ256rm, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ256rmb, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ256rmbk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ256rmbkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ256rmk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ256rmkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ256rr, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ256rrk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZ256rrkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZrm, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZrmb, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZrmbk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZrmbkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZrmk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZrmkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZrr, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZrrk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQZrrkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQrm, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHQDQrr, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDYrm, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDYrr, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZ128rm, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZ128rmk, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZ128rmkz, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZ128rr, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZ128rrk, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZ128rrkz, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZ256rm, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZ256rmk, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZ256rmkz, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZ256rr, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZ256rrk, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZ256rrkz, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZrm, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZrmk, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZrmkz, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZrr, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZrrk, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDZrrkz, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDrm, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKHWDrr, X86_INS_VPUNPCKHWD: vpunpckhwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWYrm, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWYrr, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZ128rm, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZ128rmk, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZ128rmkz, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZ128rr, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZ128rrk, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZ128rrkz, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZ256rm, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZ256rmk, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZ256rmkz, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZ256rr, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZ256rrk, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZ256rrkz, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZrm, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZrmk, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZrmkz, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZrr, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZrrk, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWZrrkz, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWrm, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLBWrr, X86_INS_VPUNPCKLBW: vpunpcklbw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQYrm, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQYrr, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ128rm, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ128rmb, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ128rmbk, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ128rmbkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ128rmk, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ128rmkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ128rr, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ128rrk, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ128rrkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ256rm, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ256rmb, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ256rmbk, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ256rmbkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ256rmk, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ256rmkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ256rr, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ256rrk, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZ256rrkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZrm, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZrmb, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZrmbk, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZrmbkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZrmk, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZrmkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZrr, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZrrk, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQZrrkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQrm, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLDQrr, X86_INS_VPUNPCKLDQ: vpunpckldq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQYrm, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQYrr, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ128rm, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ128rmb, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ128rmbk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ128rmbkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ128rmk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ128rmkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ128rr, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ128rrk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ128rrkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ256rm, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ256rmb, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ256rmbk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ256rmbkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ256rmk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ256rmkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ256rr, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ256rrk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZ256rrkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZrm, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZrmb, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZrmbk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZrmbkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZrmk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZrmkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZrr, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZrrk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQZrrkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQrm, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLQDQrr, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDYrm, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDYrr, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZ128rm, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZ128rmk, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZ128rmkz, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZ128rr, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZ128rrk, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZ128rrkz, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZ256rm, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZ256rmk, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZ256rmkz, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZ256rr, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZ256rrk, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZ256rrkz, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZrm, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZrmk, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZrmkz, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZrr, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZrrk, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDZrrkz, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDrm, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPUNPCKLWDrr, X86_INS_VPUNPCKLWD: vpunpcklwd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ128rm, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ128rmb, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ128rmbk, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ128rmbkz, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ128rmk, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ128rmkz, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ128rr, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ128rrk, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ128rrkz, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ256rm, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ256rmb, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ256rmbk, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ256rmbkz, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ256rmk, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ256rmkz, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ256rr, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ256rrk, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZ256rrkz, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZrm, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZrmb, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZrmbk, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZrmbkz, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZrmk, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZrmkz, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZrr, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZrrk, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORDZrrkz, X86_INS_VPXORD: vpxord */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ128rm, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ128rmb, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ128rmbk, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ128rmbkz, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ128rmk, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ128rmkz, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ128rr, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ128rrk, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ128rrkz, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ256rm, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ256rmb, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ256rmbk, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ256rmbkz, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ256rmk, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ256rmkz, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ256rr, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ256rrk, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZ256rrkz, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZrm, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZrmb, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZrmbk, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZrmbkz, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZrmk, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZrmkz, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZrr, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZrrk, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORQZrrkz, X86_INS_VPXORQ: vpxorq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORYrm, X86_INS_VPXOR: vpxor */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORYrr, X86_INS_VPXOR: vpxor */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORrm, X86_INS_VPXOR: vpxor */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VPXORrr, X86_INS_VPXOR: vpxor */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRANGEPDZ128rmbi, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ128rmbik, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ128rmbikz, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ128rmi, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ128rmik, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ128rmikz, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ128rri, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ128rrik, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ128rrikz, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ256rmbi, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ256rmbik, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ256rmbikz, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ256rmi, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ256rmik, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ256rmikz, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ256rri, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ256rrik, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZ256rrikz, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZrmbi, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZrmbik, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZrmbikz, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZrmi, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZrmik, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZrmikz, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZrri, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZrrib, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZrribk, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZrribkz, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZrrik, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPDZrrikz, X86_INS_VRANGEPD: vrangepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ128rmbi, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ128rmbik, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ128rmbikz, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ128rmi, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ128rmik, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ128rmikz, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ128rri, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ128rrik, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ128rrikz, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ256rmbi, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ256rmbik, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ256rmbikz, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ256rmi, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ256rmik, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ256rmikz, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ256rri, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ256rrik, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZ256rrikz, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZrmbi, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZrmbik, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZrmbikz, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZrmi, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZrmik, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZrmikz, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZrri, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZrrib, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZrribk, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZrribkz, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZrrik, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGEPSZrrikz, X86_INS_VRANGEPS: vrangeps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESDZrmi, X86_INS_VRANGESD: vrangesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESDZrmik, X86_INS_VRANGESD: vrangesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESDZrmikz, X86_INS_VRANGESD: vrangesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESDZrri, X86_INS_VRANGESD: vrangesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESDZrrib, X86_INS_VRANGESD: vrangesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESDZrribk, X86_INS_VRANGESD: vrangesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESDZrribkz, X86_INS_VRANGESD: vrangesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESDZrrik, X86_INS_VRANGESD: vrangesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESDZrrikz, X86_INS_VRANGESD: vrangesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESSZrmi, X86_INS_VRANGESS: vrangess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESSZrmik, X86_INS_VRANGESS: vrangess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESSZrmikz, X86_INS_VRANGESS: vrangess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESSZrri, X86_INS_VRANGESS: vrangess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESSZrrib, X86_INS_VRANGESS: vrangess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESSZrribk, X86_INS_VRANGESS: vrangess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESSZrribkz, X86_INS_VRANGESS: vrangess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESSZrrik, X86_INS_VRANGESS: vrangess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRANGESSZrrikz, X86_INS_VRANGESS: vrangess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRCP14PDZ128m, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ128mb, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ128mbk, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ128mbkz, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ128mk, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ128mkz, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ128r, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ128rk, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ128rkz, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ256m, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ256mb, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ256mbk, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ256mbkz, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ256mk, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ256mkz, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ256r, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ256rk, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZ256rkz, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZm, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZmb, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZmbk, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZmbkz, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZmk, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZmkz, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZr, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZrk, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PDZrkz, X86_INS_VRCP14PD: vrcp14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ128m, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ128mb, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ128mbk, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ128mbkz, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ128mk, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ128mkz, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ128r, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ128rk, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ128rkz, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ256m, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ256mb, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ256mbk, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ256mbkz, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ256mk, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ256mkz, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ256r, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ256rk, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZ256rkz, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZm, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZmb, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZmbk, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZmbkz, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZmk, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZmkz, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZr, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZrk, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14PSZrkz, X86_INS_VRCP14PS: vrcp14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14SDZrm, X86_INS_VRCP14SD: vrcp14sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14SDZrmk, X86_INS_VRCP14SD: vrcp14sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14SDZrmkz, X86_INS_VRCP14SD: vrcp14sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14SDZrr, X86_INS_VRCP14SD: vrcp14sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14SDZrrk, X86_INS_VRCP14SD: vrcp14sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14SDZrrkz, X86_INS_VRCP14SD: vrcp14sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14SSZrm, X86_INS_VRCP14SS: vrcp14ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14SSZrmk, X86_INS_VRCP14SS: vrcp14ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14SSZrmkz, X86_INS_VRCP14SS: vrcp14ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14SSZrr, X86_INS_VRCP14SS: vrcp14ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14SSZrrk, X86_INS_VRCP14SS: vrcp14ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP14SSZrrkz, X86_INS_VRCP14SS: vrcp14ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PDZm, X86_INS_VRCP28PD: vrcp28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PDZmb, X86_INS_VRCP28PD: vrcp28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PDZmbk, X86_INS_VRCP28PD: vrcp28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PDZmbkz, X86_INS_VRCP28PD: vrcp28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PDZmk, X86_INS_VRCP28PD: vrcp28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PDZmkz, X86_INS_VRCP28PD: vrcp28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PDZr, X86_INS_VRCP28PD: vrcp28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PDZrb, X86_INS_VRCP28PD: vrcp28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PDZrbk, X86_INS_VRCP28PD: vrcp28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PDZrbkz, X86_INS_VRCP28PD: vrcp28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PDZrk, X86_INS_VRCP28PD: vrcp28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PDZrkz, X86_INS_VRCP28PD: vrcp28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PSZm, X86_INS_VRCP28PS: vrcp28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PSZmb, X86_INS_VRCP28PS: vrcp28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PSZmbk, X86_INS_VRCP28PS: vrcp28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PSZmbkz, X86_INS_VRCP28PS: vrcp28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PSZmk, X86_INS_VRCP28PS: vrcp28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PSZmkz, X86_INS_VRCP28PS: vrcp28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PSZr, X86_INS_VRCP28PS: vrcp28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PSZrb, X86_INS_VRCP28PS: vrcp28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PSZrbk, X86_INS_VRCP28PS: vrcp28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PSZrbkz, X86_INS_VRCP28PS: vrcp28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PSZrk, X86_INS_VRCP28PS: vrcp28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28PSZrkz, X86_INS_VRCP28PS: vrcp28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SDZm, X86_INS_VRCP28SD: vrcp28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SDZmk, X86_INS_VRCP28SD: vrcp28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SDZmkz, X86_INS_VRCP28SD: vrcp28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SDZr, X86_INS_VRCP28SD: vrcp28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SDZrb, X86_INS_VRCP28SD: vrcp28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SDZrbk, X86_INS_VRCP28SD: vrcp28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SDZrbkz, X86_INS_VRCP28SD: vrcp28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SDZrk, X86_INS_VRCP28SD: vrcp28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SDZrkz, X86_INS_VRCP28SD: vrcp28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SSZm, X86_INS_VRCP28SS: vrcp28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SSZmk, X86_INS_VRCP28SS: vrcp28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SSZmkz, X86_INS_VRCP28SS: vrcp28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SSZr, X86_INS_VRCP28SS: vrcp28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SSZrb, X86_INS_VRCP28SS: vrcp28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SSZrbk, X86_INS_VRCP28SS: vrcp28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SSZrbkz, X86_INS_VRCP28SS: vrcp28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SSZrk, X86_INS_VRCP28SS: vrcp28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCP28SSZrkz, X86_INS_VRCP28SS: vrcp28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCPPSYm, X86_INS_VRCPPS: vrcpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCPPSYr, X86_INS_VRCPPS: vrcpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCPPSm, X86_INS_VRCPPS: vrcpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCPPSr, X86_INS_VRCPPS: vrcpps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRCPSSm, X86_INS_VRCPSS: vrcpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCPSSm_Int, X86_INS_VRCPSS: vrcpss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRCPSSr, X86_INS_VRCPSS: vrcpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRCPSSr_Int, X86_INS_VRCPSS: vrcpss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VREDUCEPDZ128rmbi, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ128rmbik, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ128rmbikz, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ128rmi, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ128rmik, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ128rmikz, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ128rri, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ128rrik, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ128rrikz, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ256rmbi, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ256rmbik, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ256rmbikz, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ256rmi, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ256rmik, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ256rmikz, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ256rri, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ256rrik, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZ256rrikz, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZrmbi, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZrmbik, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZrmbikz, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZrmi, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZrmik, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZrmikz, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZrri, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZrrib, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZrribk, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZrribkz, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZrrik, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPDZrrikz, X86_INS_VREDUCEPD: vreducepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ128rmbi, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ128rmbik, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ128rmbikz, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ128rmi, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ128rmik, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ128rmikz, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ128rri, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ128rrik, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ128rrikz, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ256rmbi, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ256rmbik, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ256rmbikz, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ256rmi, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ256rmik, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ256rmikz, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ256rri, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ256rrik, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZ256rrikz, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZrmbi, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZrmbik, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZrmbikz, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZrmi, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZrmik, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZrmikz, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZrri, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZrrib, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZrribk, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZrribkz, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZrrik, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCEPSZrrikz, X86_INS_VREDUCEPS: vreduceps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESDZrmi, X86_INS_VREDUCESD: vreducesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESDZrmik, X86_INS_VREDUCESD: vreducesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESDZrmikz, X86_INS_VREDUCESD: vreducesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESDZrri, X86_INS_VREDUCESD: vreducesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESDZrrib, X86_INS_VREDUCESD: vreducesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESDZrribk, X86_INS_VREDUCESD: vreducesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESDZrribkz, X86_INS_VREDUCESD: vreducesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESDZrrik, X86_INS_VREDUCESD: vreducesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESDZrrikz, X86_INS_VREDUCESD: vreducesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESSZrmi, X86_INS_VREDUCESS: vreducess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESSZrmik, X86_INS_VREDUCESS: vreducess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESSZrmikz, X86_INS_VREDUCESS: vreducess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESSZrri, X86_INS_VREDUCESS: vreducess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESSZrrib, X86_INS_VREDUCESS: vreducess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESSZrribk, X86_INS_VREDUCESS: vreducess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESSZrribkz, X86_INS_VREDUCESS: vreducess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESSZrrik, X86_INS_VREDUCESS: vreducess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VREDUCESSZrrikz, X86_INS_VREDUCESS: vreducess */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ128rmbi, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ128rmbik, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ128rmbikz, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ128rmi, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ128rmik, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ128rmikz, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ128rri, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ128rrik, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ128rrikz, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ256rmbi, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ256rmbik, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ256rmbikz, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ256rmi, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ256rmik, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ256rmikz, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ256rri, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ256rrik, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZ256rrikz, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZrmbi, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZrmbik, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZrmbikz, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZrmi, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZrmik, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZrmikz, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZrri, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZrrib, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZrribk, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZrribkz, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZrrik, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPDZrrikz, X86_INS_VRNDSCALEPD: vrndscalepd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ128rmbi, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ128rmbik, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ128rmbikz, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ128rmi, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ128rmik, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ128rmikz, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ128rri, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ128rrik, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ128rrikz, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ256rmbi, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ256rmbik, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ256rmbikz, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ256rmi, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ256rmik, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ256rmikz, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ256rri, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ256rrik, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZ256rrikz, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZrmbi, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZrmbik, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZrmbikz, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZrmi, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZrmik, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZrmikz, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZrri, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZrrib, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZrribk, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZrribkz, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZrrik, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALEPSZrrikz, X86_INS_VRNDSCALEPS: vrndscaleps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRNDSCALESDZm, X86_INS_VRNDSCALESD: vrndscalesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESDZm_Int, X86_INS_VRNDSCALESD: vrndscalesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESDZm_Intk, X86_INS_VRNDSCALESD: vrndscalesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESDZm_Intkz, X86_INS_VRNDSCALESD: vrndscalesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESDZr, X86_INS_VRNDSCALESD: vrndscalesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESDZr_Int, X86_INS_VRNDSCALESD: vrndscalesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESDZr_Intk, X86_INS_VRNDSCALESD: vrndscalesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESDZr_Intkz, X86_INS_VRNDSCALESD: vrndscalesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESDZrb_Int, X86_INS_VRNDSCALESD: vrndscalesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESDZrb_Intk, X86_INS_VRNDSCALESD: vrndscalesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESDZrb_Intkz, X86_INS_VRNDSCALESD: vrndscalesd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESSZm, X86_INS_VRNDSCALESS: vrndscaless */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESSZm_Int, X86_INS_VRNDSCALESS: vrndscaless */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESSZm_Intk, X86_INS_VRNDSCALESS: vrndscaless */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESSZm_Intkz, X86_INS_VRNDSCALESS: vrndscaless */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESSZr, X86_INS_VRNDSCALESS: vrndscaless */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESSZr_Int, X86_INS_VRNDSCALESS: vrndscaless */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESSZr_Intk, X86_INS_VRNDSCALESS: vrndscaless */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESSZr_Intkz, X86_INS_VRNDSCALESS: vrndscaless */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESSZrb_Int, X86_INS_VRNDSCALESS: vrndscaless */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESSZrb_Intk, X86_INS_VRNDSCALESS: vrndscaless */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRNDSCALESSZrb_Intkz, X86_INS_VRNDSCALESS: vrndscaless */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VROUNDPDYm, X86_INS_VROUNDPD: vroundpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VROUNDPDYr, X86_INS_VROUNDPD: vroundpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VROUNDPDm, X86_INS_VROUNDPD: vroundpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VROUNDPDr, X86_INS_VROUNDPD: vroundpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VROUNDPSYm, X86_INS_VROUNDPS: vroundps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VROUNDPSYr, X86_INS_VROUNDPS: vroundps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VROUNDPSm, X86_INS_VROUNDPS: vroundps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VROUNDPSr, X86_INS_VROUNDPS: vroundps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VROUNDSDm, X86_INS_VROUNDSD: vroundsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VROUNDSDm_Int, X86_INS_VROUNDSD: vroundsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VROUNDSDr, X86_INS_VROUNDSD: vroundsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VROUNDSDr_Int, X86_INS_VROUNDSD: vroundsd $dst $src1 $src2 $src3 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VROUNDSSm, X86_INS_VROUNDSS: vroundss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VROUNDSSm_Int, X86_INS_VROUNDSS: vroundss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VROUNDSSr, X86_INS_VROUNDSS: vroundss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VROUNDSSr_Int, X86_INS_VROUNDSS: vroundss $dst $src1 $src2 $src3 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRSQRT14PDZ128m, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ128mb, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ128mbk, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ128mbkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ128mk, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ128mkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ128r, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ128rk, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ128rkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ256m, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ256mb, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ256mbk, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ256mbkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ256mk, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ256mkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ256r, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ256rk, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZ256rkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZm, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZmb, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZmbk, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZmbkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZmk, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZmkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZr, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZrk, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PDZrkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ128m, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ128mb, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ128mbk, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ128mbkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ128mk, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ128mkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ128r, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ128rk, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ128rkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ256m, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ256mb, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ256mbk, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ256mbkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ256mk, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ256mkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ256r, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ256rk, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZ256rkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZm, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZmb, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZmbk, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZmbkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZmk, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZmkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZr, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZrk, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14PSZrkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14SDZrm, X86_INS_VRSQRT14SD: vrsqrt14sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14SDZrmk, X86_INS_VRSQRT14SD: vrsqrt14sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14SDZrmkz, X86_INS_VRSQRT14SD: vrsqrt14sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14SDZrr, X86_INS_VRSQRT14SD: vrsqrt14sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14SDZrrk, X86_INS_VRSQRT14SD: vrsqrt14sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14SDZrrkz, X86_INS_VRSQRT14SD: vrsqrt14sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14SSZrm, X86_INS_VRSQRT14SS: vrsqrt14ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14SSZrmk, X86_INS_VRSQRT14SS: vrsqrt14ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14SSZrmkz, X86_INS_VRSQRT14SS: vrsqrt14ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14SSZrr, X86_INS_VRSQRT14SS: vrsqrt14ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14SSZrrk, X86_INS_VRSQRT14SS: vrsqrt14ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT14SSZrrkz, X86_INS_VRSQRT14SS: vrsqrt14ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PDZm, X86_INS_VRSQRT28PD: vrsqrt28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PDZmb, X86_INS_VRSQRT28PD: vrsqrt28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PDZmbk, X86_INS_VRSQRT28PD: vrsqrt28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PDZmbkz, X86_INS_VRSQRT28PD: vrsqrt28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PDZmk, X86_INS_VRSQRT28PD: vrsqrt28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PDZmkz, X86_INS_VRSQRT28PD: vrsqrt28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PDZr, X86_INS_VRSQRT28PD: vrsqrt28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PDZrb, X86_INS_VRSQRT28PD: vrsqrt28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PDZrbk, X86_INS_VRSQRT28PD: vrsqrt28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PDZrbkz, X86_INS_VRSQRT28PD: vrsqrt28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PDZrk, X86_INS_VRSQRT28PD: vrsqrt28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PDZrkz, X86_INS_VRSQRT28PD: vrsqrt28pd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PSZm, X86_INS_VRSQRT28PS: vrsqrt28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PSZmb, X86_INS_VRSQRT28PS: vrsqrt28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PSZmbk, X86_INS_VRSQRT28PS: vrsqrt28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PSZmbkz, X86_INS_VRSQRT28PS: vrsqrt28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PSZmk, X86_INS_VRSQRT28PS: vrsqrt28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PSZmkz, X86_INS_VRSQRT28PS: vrsqrt28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PSZr, X86_INS_VRSQRT28PS: vrsqrt28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PSZrb, X86_INS_VRSQRT28PS: vrsqrt28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PSZrbk, X86_INS_VRSQRT28PS: vrsqrt28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PSZrbkz, X86_INS_VRSQRT28PS: vrsqrt28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PSZrk, X86_INS_VRSQRT28PS: vrsqrt28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28PSZrkz, X86_INS_VRSQRT28PS: vrsqrt28ps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SDZm, X86_INS_VRSQRT28SD: vrsqrt28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SDZmk, X86_INS_VRSQRT28SD: vrsqrt28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SDZmkz, X86_INS_VRSQRT28SD: vrsqrt28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SDZr, X86_INS_VRSQRT28SD: vrsqrt28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SDZrb, X86_INS_VRSQRT28SD: vrsqrt28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SDZrbk, X86_INS_VRSQRT28SD: vrsqrt28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SDZrbkz, X86_INS_VRSQRT28SD: vrsqrt28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SDZrk, X86_INS_VRSQRT28SD: vrsqrt28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SDZrkz, X86_INS_VRSQRT28SD: vrsqrt28sd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SSZm, X86_INS_VRSQRT28SS: vrsqrt28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SSZmk, X86_INS_VRSQRT28SS: vrsqrt28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SSZmkz, X86_INS_VRSQRT28SS: vrsqrt28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SSZr, X86_INS_VRSQRT28SS: vrsqrt28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SSZrb, X86_INS_VRSQRT28SS: vrsqrt28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SSZrbk, X86_INS_VRSQRT28SS: vrsqrt28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SSZrbkz, X86_INS_VRSQRT28SS: vrsqrt28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SSZrk, X86_INS_VRSQRT28SS: vrsqrt28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRT28SSZrkz, X86_INS_VRSQRT28SS: vrsqrt28ss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRTPSYm, X86_INS_VRSQRTPS: vrsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRTPSYr, X86_INS_VRSQRTPS: vrsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRTPSm, X86_INS_VRSQRTPS: vrsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRTPSr, X86_INS_VRSQRTPS: vrsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRTSSm, X86_INS_VRSQRTSS: vrsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRTSSm_Int, X86_INS_VRSQRTSS: vrsqrtss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VRSQRTSSr, X86_INS_VRSQRTSS: vrsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VRSQRTSSr_Int, X86_INS_VRSQRTSS: vrsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ128rm, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ128rmb, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ128rmbk, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ128rmbkz, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ128rmk, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ128rmkz, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ128rr, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ128rrk, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ128rrkz, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ256rm, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ256rmb, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ256rmbk, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ256rmbkz, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ256rmk, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ256rmkz, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ256rr, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ256rrk, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZ256rrkz, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZrm, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZrmb, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZrmbk, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZrmbkz, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZrmk, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZrmkz, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZrr, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZrrb, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZrrbk, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZrrbkz, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZrrk, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPDZrrkz, X86_INS_VSCALEFPD: vscalefpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ128rm, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ128rmb, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ128rmbk, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ128rmbkz, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ128rmk, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ128rmkz, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ128rr, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ128rrk, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ128rrkz, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ256rm, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ256rmb, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ256rmbk, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ256rmbkz, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ256rmk, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ256rmkz, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ256rr, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ256rrk, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZ256rrkz, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZrm, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZrmb, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZrmbk, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZrmbkz, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZrmk, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZrmkz, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZrr, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZrrb, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZrrbk, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZrrbkz, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZrrk, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFPSZrrkz, X86_INS_VSCALEFPS: vscalefps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSDZrm, X86_INS_VSCALEFSD: vscalefsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSDZrmk, X86_INS_VSCALEFSD: vscalefsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSDZrmkz, X86_INS_VSCALEFSD: vscalefsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSDZrr, X86_INS_VSCALEFSD: vscalefsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSDZrrb_Int, X86_INS_VSCALEFSD: vscalefsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSDZrrb_Intk, X86_INS_VSCALEFSD: vscalefsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSDZrrb_Intkz, X86_INS_VSCALEFSD: vscalefsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSDZrrk, X86_INS_VSCALEFSD: vscalefsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSDZrrkz, X86_INS_VSCALEFSD: vscalefsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSSZrm, X86_INS_VSCALEFSS: vscalefss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSSZrmk, X86_INS_VSCALEFSS: vscalefss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSSZrmkz, X86_INS_VSCALEFSS: vscalefss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSSZrr, X86_INS_VSCALEFSS: vscalefss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSSZrrb_Int, X86_INS_VSCALEFSS: vscalefss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSSZrrb_Intk, X86_INS_VSCALEFSS: vscalefss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSSZrrb_Intkz, X86_INS_VSCALEFSS: vscalefss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSSZrrk, X86_INS_VSCALEFSS: vscalefss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCALEFSSZrrkz, X86_INS_VSCALEFSS: vscalefss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERDPDZ128mr, X86_INS_VSCATTERDPD: vscatterdpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERDPDZ256mr, X86_INS_VSCATTERDPD: vscatterdpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERDPDZmr, X86_INS_VSCATTERDPD: vscatterdpd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERDPSZ128mr, X86_INS_VSCATTERDPS: vscatterdps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERDPSZ256mr, X86_INS_VSCATTERDPS: vscatterdps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERDPSZmr, X86_INS_VSCATTERDPS: vscatterdps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERPF0DPDm, X86_INS_VSCATTERPF0DPD: vscatterpf0dpd */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERPF0DPSm, X86_INS_VSCATTERPF0DPS: vscatterpf0dps */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERPF0QPDm, X86_INS_VSCATTERPF0QPD: vscatterpf0qpd */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERPF0QPSm, X86_INS_VSCATTERPF0QPS: vscatterpf0qps */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERPF1DPDm, X86_INS_VSCATTERPF1DPD: vscatterpf1dpd */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERPF1DPSm, X86_INS_VSCATTERPF1DPS: vscatterpf1dps */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERPF1QPDm, X86_INS_VSCATTERPF1QPD: vscatterpf1qpd */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERPF1QPSm, X86_INS_VSCATTERPF1QPS: vscatterpf1qps */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERQPDZ128mr, X86_INS_VSCATTERQPD: vscatterqpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERQPDZ256mr, X86_INS_VSCATTERQPD: vscatterqpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERQPDZmr, X86_INS_VSCATTERQPD: vscatterqpd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERQPSZ128mr, X86_INS_VSCATTERQPS: vscatterqps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERQPSZ256mr, X86_INS_VSCATTERQPS: vscatterqps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSCATTERQPSZmr, X86_INS_VSCATTERQPS: vscatterqps */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSHUFF32X4Z256rmbi, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Z256rmbik, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Z256rmbikz, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Z256rmi, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Z256rmik, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Z256rmikz, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Z256rri, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Z256rrik, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Z256rrikz, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Zrmbi, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Zrmbik, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Zrmbikz, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Zrmi, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Zrmik, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Zrmikz, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Zrri, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Zrrik, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF32X4Zrrikz, X86_INS_VSHUFF32X4: vshuff32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Z256rmbi, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Z256rmbik, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Z256rmbikz, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Z256rmi, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Z256rmik, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Z256rmikz, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Z256rri, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Z256rrik, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Z256rrikz, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Zrmbi, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Zrmbik, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Zrmbikz, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Zrmi, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Zrmik, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Zrmikz, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Zrri, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Zrrik, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFF64X2Zrrikz, X86_INS_VSHUFF64X2: vshuff64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Z256rmbi, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Z256rmbik, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Z256rmbikz, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Z256rmi, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Z256rmik, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Z256rmikz, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Z256rri, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Z256rrik, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Z256rrikz, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Zrmbi, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Zrmbik, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Zrmbikz, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Zrmi, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Zrmik, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Zrmikz, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Zrri, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Zrrik, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI32X4Zrrikz, X86_INS_VSHUFI32X4: vshufi32x4 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Z256rmbi, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Z256rmbik, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Z256rmbikz, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Z256rmi, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Z256rmik, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Z256rmikz, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Z256rri, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Z256rrik, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Z256rrikz, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Zrmbi, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Zrmbik, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Zrmbikz, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Zrmi, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Zrmik, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Zrmikz, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Zrri, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Zrrik, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFI64X2Zrrikz, X86_INS_VSHUFI64X2: vshufi64x2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDYrmi, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDYrri, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ128rmbi, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ128rmbik, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ128rmbikz, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ128rmi, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ128rmik, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ128rmikz, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ128rri, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ128rrik, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ128rrikz, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ256rmbi, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ256rmbik, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ256rmbikz, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ256rmi, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ256rmik, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ256rmikz, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ256rri, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ256rrik, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZ256rrikz, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZrmbi, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZrmbik, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZrmbikz, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZrmi, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZrmik, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZrmikz, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZrri, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZrrik, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDZrrikz, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDrmi, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPDrri, X86_INS_VSHUFPD: vshufpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSYrmi, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSYrri, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ128rmbi, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ128rmbik, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ128rmbikz, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ128rmi, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ128rmik, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ128rmikz, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ128rri, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ128rrik, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ128rrikz, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ256rmbi, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ256rmbik, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ256rmbikz, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ256rmi, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ256rmik, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ256rmikz, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ256rri, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ256rrik, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZ256rrikz, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZrmbi, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZrmbik, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZrmbikz, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZrmi, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZrmik, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZrmikz, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZrri, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZrrik, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSZrrikz, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSrmi, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSHUFPSrri, X86_INS_VSHUFPS: vshufps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSQRTPDYm, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDYr, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ128m, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ128mb, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ128mbk, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ128mbkz, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ128mk, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ128mkz, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ128r, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ128rk, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ128rkz, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ256m, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ256mb, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ256mbk, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ256mbkz, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ256mk, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ256mkz, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ256r, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ256rk, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZ256rkz, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZm, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZmb, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZmbk, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZmbkz, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZmk, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZmkz, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZr, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZrb, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZrbk, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZrbkz, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZrk, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDZrkz, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDm, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPDr, X86_INS_VSQRTPD: vsqrtpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSYm, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSYr, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ128m, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ128mb, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ128mbk, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ128mbkz, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ128mk, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ128mkz, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ128r, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ128rk, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ128rkz, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ256m, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ256mb, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ256mbk, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ256mbkz, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ256mk, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ256mkz, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ256r, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ256rk, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZ256rkz, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZm, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZmb, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZmbk, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZmbkz, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZmk, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZmkz, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZr, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZrb, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZrbk, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZrbkz, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZrk, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSZrkz, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSm, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTPSr, X86_INS_VSQRTPS: vsqrtps */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDZm, X86_INS_VSQRTSD: vsqrtsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDZm_Int, X86_INS_VSQRTSD: vsqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSQRTSDZm_Intk, X86_INS_VSQRTSD: vsqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDZm_Intkz, X86_INS_VSQRTSD: vsqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDZr, X86_INS_VSQRTSD: vsqrtsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDZr_Int, X86_INS_VSQRTSD: vsqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDZr_Intk, X86_INS_VSQRTSD: vsqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDZr_Intkz, X86_INS_VSQRTSD: vsqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDZrb_Int, X86_INS_VSQRTSD: vsqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDZrb_Intk, X86_INS_VSQRTSD: vsqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDZrb_Intkz, X86_INS_VSQRTSD: vsqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDm, X86_INS_VSQRTSD: vsqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDm_Int, X86_INS_VSQRTSD: vsqrtsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSQRTSDr, X86_INS_VSQRTSD: vsqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSDr_Int, X86_INS_VSQRTSD: vsqrtsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSZm, X86_INS_VSQRTSS: vsqrtss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSZm_Int, X86_INS_VSQRTSS: vsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSQRTSSZm_Intk, X86_INS_VSQRTSS: vsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSZm_Intkz, X86_INS_VSQRTSS: vsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSZr, X86_INS_VSQRTSS: vsqrtss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSZr_Int, X86_INS_VSQRTSS: vsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSZr_Intk, X86_INS_VSQRTSS: vsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSZr_Intkz, X86_INS_VSQRTSS: vsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSZrb_Int, X86_INS_VSQRTSS: vsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSZrb_Intk, X86_INS_VSQRTSS: vsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSZrb_Intkz, X86_INS_VSQRTSS: vsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSm, X86_INS_VSQRTSS: vsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSm_Int, X86_INS_VSQRTSS: vsqrtss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSQRTSSr, X86_INS_VSQRTSS: vsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSQRTSSr_Int, X86_INS_VSQRTSS: vsqrtss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSTMXCSR, X86_INS_VSTMXCSR: vstmxcsr */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDYrm, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDYrr, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ128rm, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ128rmb, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ128rmbk, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ128rmbkz, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ128rmk, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ128rmkz, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ128rr, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ128rrk, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ128rrkz, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ256rm, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ256rmb, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ256rmbk, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ256rmbkz, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ256rmk, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ256rmkz, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ256rr, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ256rrk, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZ256rrkz, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZrm, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZrmb, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZrmbk, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZrmbkz, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZrmk, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZrmkz, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZrr, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZrrb, X86_INS_VSUBPD: vsubpd */ + 0, + { 0 } +}, + +{ /* X86_VSUBPDZrrbk, X86_INS_VSUBPD: vsubpd */ + 0, + { 0 } +}, + +{ /* X86_VSUBPDZrrbkz, X86_INS_VSUBPD: vsubpd */ + 0, + { 0 } +}, + +{ /* X86_VSUBPDZrrk, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDZrrkz, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDrm, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPDrr, X86_INS_VSUBPD: vsubpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSYrm, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSYrr, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ128rm, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ128rmb, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ128rmbk, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ128rmbkz, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ128rmk, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ128rmkz, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ128rr, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ128rrk, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ128rrkz, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ256rm, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ256rmb, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ256rmbk, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ256rmbkz, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ256rmk, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ256rmkz, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ256rr, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ256rrk, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZ256rrkz, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZrm, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZrmb, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZrmbk, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZrmbkz, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZrmk, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZrmkz, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZrr, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZrrb, X86_INS_VSUBPS: vsubps */ + 0, + { 0 } +}, + +{ /* X86_VSUBPSZrrbk, X86_INS_VSUBPS: vsubps */ + 0, + { 0 } +}, + +{ /* X86_VSUBPSZrrbkz, X86_INS_VSUBPS: vsubps */ + 0, + { 0 } +}, + +{ /* X86_VSUBPSZrrk, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSZrrkz, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSrm, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBPSrr, X86_INS_VSUBPS: vsubps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDZrm, X86_INS_VSUBSD: vsubsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDZrm_Int, X86_INS_VSUBSD: vsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDZrm_Intk, X86_INS_VSUBSD: vsubsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDZrm_Intkz, X86_INS_VSUBSD: vsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDZrr, X86_INS_VSUBSD: vsubsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDZrr_Int, X86_INS_VSUBSD: vsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDZrr_Intk, X86_INS_VSUBSD: vsubsd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDZrr_Intkz, X86_INS_VSUBSD: vsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDZrrb_Int, X86_INS_VSUBSD: vsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDZrrb_Intk, X86_INS_VSUBSD: vsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDZrrb_Intkz, X86_INS_VSUBSD: vsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDrm, X86_INS_VSUBSD: vsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDrm_Int, X86_INS_VSUBSD: vsubsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSUBSDrr, X86_INS_VSUBSD: vsubsd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSDrr_Int, X86_INS_VSUBSD: vsubsd $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSZrm, X86_INS_VSUBSS: vsubss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSZrm_Int, X86_INS_VSUBSS: vsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSZrm_Intk, X86_INS_VSUBSS: vsubss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSZrm_Intkz, X86_INS_VSUBSS: vsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSZrr, X86_INS_VSUBSS: vsubss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSZrr_Int, X86_INS_VSUBSS: vsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSZrr_Intk, X86_INS_VSUBSS: vsubss */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSZrr_Intkz, X86_INS_VSUBSS: vsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSZrrb_Int, X86_INS_VSUBSS: vsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSZrrb_Intk, X86_INS_VSUBSS: vsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSZrrb_Intkz, X86_INS_VSUBSS: vsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSrm, X86_INS_VSUBSS: vsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSrm_Int, X86_INS_VSUBSS: vsubss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_VSUBSSrr, X86_INS_VSUBSS: vsubss */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VSUBSSrr_Int, X86_INS_VSUBSS: vsubss $dst $src1 $src2 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VTESTPDYrm, X86_INS_VTESTPD: vtestpd */ + X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VTESTPDYrr, X86_INS_VTESTPD: vtestpd */ + X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VTESTPDrm, X86_INS_VTESTPD: vtestpd */ + X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VTESTPDrr, X86_INS_VTESTPD: vtestpd */ + X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VTESTPSYrm, X86_INS_VTESTPS: vtestps */ + X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VTESTPSYrr, X86_INS_VTESTPS: vtestps */ + X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VTESTPSrm, X86_INS_VTESTPS: vtestps */ + X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VTESTPSrr, X86_INS_VTESTPS: vtestps */ + X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISDZrm, X86_INS_VUCOMISD: vucomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISDZrm_Int, X86_INS_VUCOMISD: vucomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISDZrr, X86_INS_VUCOMISD: vucomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISDZrr_Int, X86_INS_VUCOMISD: vucomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISDZrrb, X86_INS_VUCOMISD: vucomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISDrm, X86_INS_VUCOMISD: vucomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISDrm_Int, X86_INS_VUCOMISD: vucomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISDrr, X86_INS_VUCOMISD: vucomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISDrr_Int, X86_INS_VUCOMISD: vucomisd */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISSZrm, X86_INS_VUCOMISS: vucomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISSZrm_Int, X86_INS_VUCOMISS: vucomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISSZrr, X86_INS_VUCOMISS: vucomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISSZrr_Int, X86_INS_VUCOMISS: vucomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISSZrrb, X86_INS_VUCOMISS: vucomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISSrm, X86_INS_VUCOMISS: vucomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISSrm_Int, X86_INS_VUCOMISS: vucomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISSrr, X86_INS_VUCOMISS: vucomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUCOMISSrr_Int, X86_INS_VUCOMISS: vucomiss */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDYrm, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDYrr, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ128rm, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ128rmb, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ128rmbk, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ128rmbkz, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ128rmk, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ128rmkz, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ128rr, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ128rrk, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ128rrkz, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ256rm, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ256rmb, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ256rmbk, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ256rmbkz, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ256rmk, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ256rmkz, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ256rr, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ256rrk, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZ256rrkz, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZrm, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZrmb, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZrmbk, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZrmbkz, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZrmk, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZrmkz, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZrr, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZrrk, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDZrrkz, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDrm, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPDrr, X86_INS_VUNPCKHPD: vunpckhpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSYrm, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSYrr, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ128rm, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ128rmb, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ128rmbk, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ128rmbkz, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ128rmk, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ128rmkz, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ128rr, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ128rrk, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ128rrkz, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ256rm, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ256rmb, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ256rmbk, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ256rmbkz, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ256rmk, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ256rmkz, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ256rr, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ256rrk, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZ256rrkz, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZrm, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZrmb, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZrmbk, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZrmbkz, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZrmk, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZrmkz, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZrr, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZrrk, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSZrrkz, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSrm, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKHPSrr, X86_INS_VUNPCKHPS: vunpckhps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDYrm, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDYrr, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ128rm, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ128rmb, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ128rmbk, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ128rmbkz, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ128rmk, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ128rmkz, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ128rr, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ128rrk, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ128rrkz, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ256rm, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ256rmb, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ256rmbk, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ256rmbkz, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ256rmk, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ256rmkz, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ256rr, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ256rrk, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZ256rrkz, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZrm, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZrmb, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZrmbk, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZrmbkz, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZrmk, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZrmkz, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZrr, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZrrk, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDZrrkz, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDrm, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPDrr, X86_INS_VUNPCKLPD: vunpcklpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSYrm, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSYrr, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ128rm, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ128rmb, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ128rmbk, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ128rmbkz, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ128rmk, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ128rmkz, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ128rr, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ128rrk, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ128rrkz, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ256rm, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ256rmb, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ256rmbk, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ256rmbkz, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ256rmk, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ256rmkz, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ256rr, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ256rrk, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZ256rrkz, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZrm, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZrmb, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZrmbk, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZrmbkz, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZrmk, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZrmkz, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZrr, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZrrk, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSZrrkz, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSrm, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VUNPCKLPSrr, X86_INS_VUNPCKLPS: vunpcklps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDYrm, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDYrr, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ128rm, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ128rmb, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ128rmbk, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ128rmbkz, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ128rmk, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ128rmkz, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ128rr, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ128rrk, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ128rrkz, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ256rm, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ256rmb, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ256rmbk, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ256rmbkz, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ256rmk, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ256rmkz, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ256rr, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ256rrk, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZ256rrkz, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZrm, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZrmb, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZrmbk, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZrmbkz, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZrmk, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZrmkz, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZrr, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZrrk, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDZrrkz, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDrm, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPDrr, X86_INS_VXORPD: vxorpd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSYrm, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSYrr, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ128rm, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ128rmb, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ128rmbk, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ128rmbkz, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ128rmk, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ128rmkz, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ128rr, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ128rrk, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ128rrkz, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ256rm, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ256rmb, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ256rmbk, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ256rmbkz, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ256rmk, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ256rmkz, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ256rr, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ256rrk, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZ256rrkz, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZrm, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZrmb, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZrmbk, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZrmbkz, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZrmk, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZrmkz, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZrr, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZrrk, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSZrrkz, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSrm, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VXORPSrr, X86_INS_VXORPS: vxorps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_VZEROALL, X86_INS_VZEROALL: vzeroall */ + 0, + { 0 } +}, + +{ /* X86_VZEROUPPER, X86_INS_VZEROUPPER: vzeroupper */ + 0, + { 0 } +}, + +{ /* X86_WAIT, X86_INS_WAIT: wait */ + X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { 0 } +}, + +{ /* X86_WBINVD, X86_INS_WBINVD: wbinvd */ + 0, + { 0 } +}, + +{ /* X86_WBNOINVD, X86_INS_WBNOINVD: wbnoinvd */ + 0, + { 0 } +}, + +{ /* X86_WRFSBASE, X86_INS_WRFSBASE: wrfsbase */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_WRFSBASE64, X86_INS_WRFSBASE: wrfsbase */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_WRGSBASE, X86_INS_WRGSBASE: wrgsbase */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_WRGSBASE64, X86_INS_WRGSBASE: wrgsbase */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_WRMSR, X86_INS_WRMSR: wrmsr */ + 0, + { 0 } +}, + +{ /* X86_WRPKRUr, X86_INS_WRPKRU: wrpkru */ + 0, + { 0 } +}, + +{ /* X86_WRSSD, X86_INS_WRSSD: wrssd */ + 0, + { 0 } +}, + +{ /* X86_WRSSQ, X86_INS_WRSSQ: wrssq */ + 0, + { 0 } +}, + +{ /* X86_WRUSSD, X86_INS_WRUSSD: wrussd */ + 0, + { 0 } +}, + +{ /* X86_WRUSSQ, X86_INS_WRUSSQ: wrussq */ + 0, + { 0 } +}, + +{ /* X86_XABORT, X86_INS_XABORT: xabort */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_XACQUIRE_PREFIX, X86_INS_XACQUIRE: xacquire */ + 0, + { 0 } +}, + +{ /* X86_XADD16rm, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD16rr, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD32rm, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD32rr, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD64rm, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD64rr, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD8rm, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD8rr, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XBEGIN_2, X86_INS_XBEGIN: xbegin */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_XBEGIN_4, X86_INS_XBEGIN: xbegin */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_XCHG16ar, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG16rm, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG16rr, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG32ar, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG32rm, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG32rr, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG64ar, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG64rm, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG64rr, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG8rm, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG8rr, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCH_F, X86_INS_FXCH: fxch */ + X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, + { CS_AC_READ, 0 } +}, + +{ /* X86_XCRYPTCBC, X86_INS_XCRYPTCBC: xcryptcbc */ + 0, + { 0 } +}, + +{ /* X86_XCRYPTCFB, X86_INS_XCRYPTCFB: xcryptcfb */ + 0, + { 0 } +}, + +{ /* X86_XCRYPTCTR, X86_INS_XCRYPTCTR: xcryptctr */ + 0, + { 0 } +}, + +{ /* X86_XCRYPTECB, X86_INS_XCRYPTECB: xcryptecb */ + 0, + { 0 } +}, + +{ /* X86_XCRYPTOFB, X86_INS_XCRYPTOFB: xcryptofb */ + 0, + { 0 } +}, + +{ /* X86_XEND, X86_INS_XEND: xend */ + 0, + { 0 } +}, + +{ /* X86_XGETBV, X86_INS_XGETBV: xgetbv */ + 0, + { 0 } +}, + +{ /* X86_XLAT, X86_INS_XLATB: xlatb */ + 0, + { 0 } +}, + +{ /* X86_XOR16i16, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR16mi, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR16mi8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR16mr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR16ri, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR16ri8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR16rm, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR16rr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR16rr_REV, X86_INS_XOR: xor{w} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR32i32, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR32mi, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR32mi8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR32mr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR32ri, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR32ri8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR32rm, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR32rr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR32rr_REV, X86_INS_XOR: xor{l} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR64i32, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR64mi32, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR64mi8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR64mr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR64ri32, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR64ri8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR64rm, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR64rr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR64rr_REV, X86_INS_XOR: xor{q} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR8i8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR8mi, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR8mi8, X86_INS_XOR: xor{b} $dst $src */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR8mr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR8ri, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR8ri8, X86_INS_XOR: xor{b} $src1 $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR8rm, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR8rr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR8rr_REV, X86_INS_XOR: xor{b} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XORPDrm, X86_INS_XORPD: xorpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XORPDrr, X86_INS_XORPD: xorpd */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XORPSrm, X86_INS_XORPS: xorps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XORPSrr, X86_INS_XORPS: xorps */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XRELEASE_PREFIX, X86_INS_XRELEASE: xrelease */ + 0, + { 0 } +}, + +{ /* X86_XRSTOR, X86_INS_XRSTOR: xrstor */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_XRSTOR64, X86_INS_XRSTOR64: xrstor64 */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_XRSTORS, X86_INS_XRSTORS: xrstors */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_XRSTORS64, X86_INS_XRSTORS64: xrstors64 */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_XSAVE, X86_INS_XSAVE: xsave */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVE64, X86_INS_XSAVE64: xsave64 */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVEC, X86_INS_XSAVEC: xsavec */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVEC64, X86_INS_XSAVEC64: xsavec64 */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVEOPT, X86_INS_XSAVEOPT: xsaveopt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVEOPT64, X86_INS_XSAVEOPT64: xsaveopt64 */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVES, X86_INS_XSAVES: xsaves */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVES64, X86_INS_XSAVES64: xsaves64 */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSETBV, X86_INS_XSETBV: xsetbv */ + 0, + { 0 } +}, + +{ /* X86_XSHA1, X86_INS_XSHA1: xsha1 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XSHA256, X86_INS_XSHA256: xsha256 */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XSTORE, X86_INS_XSTORE: xstore */ + 0, + { 0 } +}, + +{ /* X86_XTEST, X86_INS_XTEST: xtest */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_AF, + { 0 } +}, diff --git a/thirdparty/capstone/arch/X86/X86MappingInsnOp_reduce.inc b/thirdparty/capstone/arch/X86/X86MappingInsnOp_reduce.inc new file mode 100644 index 0000000..3676d7e --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86MappingInsnOp_reduce.inc @@ -0,0 +1,7729 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + + +{ /* X86_AAA, X86_INS_AAA: aaa */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { 0 } +}, + +{ /* X86_AAD8i8, X86_INS_AAD: aad */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_AAM8i8, X86_INS_AAM: aam */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_AAS, X86_INS_AAS: aas */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { 0 } +}, + +{ /* X86_ADC16i16, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC16mi, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC16mi8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC16mr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC16ri, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC16ri8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC16rm, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC16rr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC16rr_REV, X86_INS_ADC: adc{w} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC32i32, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC32mi, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC32mi8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC32mr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC32ri, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC32ri8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC32rm, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC32rr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC32rr_REV, X86_INS_ADC: adc{l} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC64i32, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC64mi32, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC64mi8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC64mr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC64ri32, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC64ri8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC64rm, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC64rr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC64rr_REV, X86_INS_ADC: adc{q} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC8i8, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC8mi, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC8mi8, X86_INS_ADC: adc{b} $dst $src */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC8mr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC8ri, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC8ri8, X86_INS_ADC: adc{b} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADC8rm, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC8rr, X86_INS_ADC: adc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADC8rr_REV, X86_INS_ADC: adc{b} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADCX32rm, X86_INS_ADCX: adcx */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADCX32rr, X86_INS_ADCX: adcx */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADCX64rm, X86_INS_ADCX: adcx */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADCX64rr, X86_INS_ADCX: adcx */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD16i16, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD16mi, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD16mi8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD16mr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD16ri, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD16ri8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD16rm, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD16rr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD16rr_REV, X86_INS_ADD: add{w} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD32i32, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD32mi, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD32mi8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD32mr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD32ri, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD32ri8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD32rm, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD32rr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD32rr_REV, X86_INS_ADD: add{l} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD64i32, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD64mi32, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD64mi8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD64mr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD64ri32, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD64ri8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD64rm, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD64rr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD64rr_REV, X86_INS_ADD: add{q} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD8i8, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD8mi, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD8mi8, X86_INS_ADD: add{b} $dst $src */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD8mr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD8ri, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD8ri8, X86_INS_ADD: add{b} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ADD8rm, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD8rr, X86_INS_ADD: add */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADD8rr_REV, X86_INS_ADD: add{b} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADOX32rm, X86_INS_ADOX: adox */ + X86_EFLAGS_MODIFY_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADOX32rr, X86_INS_ADOX: adox */ + X86_EFLAGS_MODIFY_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADOX64rm, X86_INS_ADOX: adox */ + X86_EFLAGS_MODIFY_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ADOX64rr, X86_INS_ADOX: adox */ + X86_EFLAGS_MODIFY_OF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND16i16, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND16mi, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND16mi8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND16mr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND16ri, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND16ri8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND16rm, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND16rr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND16rr_REV, X86_INS_AND: and{w} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND32i32, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND32mi, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND32mi8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND32mr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND32ri, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND32ri8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND32rm, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND32rr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND32rr_REV, X86_INS_AND: and{l} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND64i32, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND64mi32, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND64mi8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND64mr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND64ri32, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND64ri8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND64rm, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND64rr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND64rr_REV, X86_INS_AND: and{q} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND8i8, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND8mi, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND8mi8, X86_INS_AND: and{b} $dst $src */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND8mr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND8ri, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND8ri8, X86_INS_AND: and{b} $src1 $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_AND8rm, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND8rr, X86_INS_AND: and */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_AND8rr_REV, X86_INS_AND: and{b} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ANDN32rm, X86_INS_ANDN: andn */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ANDN32rr, X86_INS_ANDN: andn */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ANDN64rm, X86_INS_ANDN: andn */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ANDN64rr, X86_INS_ANDN: andn */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ARPL16mr, X86_INS_ARPL: arpl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ARPL16rr, X86_INS_ARPL: arpl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BEXTR32rm, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BEXTR32rr, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BEXTR64rm, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BEXTR64rr, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BEXTRI32mi, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BEXTRI32ri, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BEXTRI64mi, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BEXTRI64ri, X86_INS_BEXTR: bextr */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, + { 0 }, +}, + +{ /* X86_BLCFILL32rm, X86_INS_BLCFILL: blcfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCFILL32rr, X86_INS_BLCFILL: blcfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCFILL64rm, X86_INS_BLCFILL: blcfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCFILL64rr, X86_INS_BLCFILL: blcfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCI32rm, X86_INS_BLCI: blci */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCI32rr, X86_INS_BLCI: blci */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCI64rm, X86_INS_BLCI: blci */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCI64rr, X86_INS_BLCI: blci */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCIC32rm, X86_INS_BLCIC: blcic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCIC32rr, X86_INS_BLCIC: blcic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCIC64rm, X86_INS_BLCIC: blcic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCIC64rr, X86_INS_BLCIC: blcic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCMSK32rm, X86_INS_BLCMSK: blcmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCMSK32rr, X86_INS_BLCMSK: blcmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCMSK64rm, X86_INS_BLCMSK: blcmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCMSK64rr, X86_INS_BLCMSK: blcmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCS32rm, X86_INS_BLCS: blcs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCS32rr, X86_INS_BLCS: blcs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCS64rm, X86_INS_BLCS: blcs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLCS64rr, X86_INS_BLCS: blcs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSFILL32rm, X86_INS_BLSFILL: blsfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSFILL32rr, X86_INS_BLSFILL: blsfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSFILL64rm, X86_INS_BLSFILL: blsfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSFILL64rr, X86_INS_BLSFILL: blsfill */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSI32rm, X86_INS_BLSI: blsi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSI32rr, X86_INS_BLSI: blsi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSI64rm, X86_INS_BLSI: blsi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSI64rr, X86_INS_BLSI: blsi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSIC32rm, X86_INS_BLSIC: blsic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSIC32rr, X86_INS_BLSIC: blsic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSIC64rm, X86_INS_BLSIC: blsic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSIC64rr, X86_INS_BLSIC: blsic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSMSK32rm, X86_INS_BLSMSK: blsmsk */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSMSK32rr, X86_INS_BLSMSK: blsmsk */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSMSK64rm, X86_INS_BLSMSK: blsmsk */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSMSK64rr, X86_INS_BLSMSK: blsmsk */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSR32rm, X86_INS_BLSR: blsr */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSR32rr, X86_INS_BLSR: blsr */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSR64rm, X86_INS_BLSR: blsr */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BLSR64rr, X86_INS_BLSR: blsr */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BOUNDS16rm, X86_INS_BOUND: bound */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BOUNDS32rm, X86_INS_BOUND: bound */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSF16rm, X86_INS_BSF: bsf */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSF16rr, X86_INS_BSF: bsf */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSF32rm, X86_INS_BSF: bsf */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSF32rr, X86_INS_BSF: bsf */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSF64rm, X86_INS_BSF: bsf */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSF64rr, X86_INS_BSF: bsf */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSR16rm, X86_INS_BSR: bsr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSR16rr, X86_INS_BSR: bsr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSR32rm, X86_INS_BSR: bsr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSR32rr, X86_INS_BSR: bsr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSR64rm, X86_INS_BSR: bsr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSR64rr, X86_INS_BSR: bsr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BSWAP16r_BAD, X86_INS_BSWAP: bswap */ + 0, + { 0 } +}, + +{ /* X86_BSWAP32r, X86_INS_BSWAP: bswap */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_BSWAP64r, X86_INS_BSWAP: bswap */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_BT16mi8, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BT16mr, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BT16ri8, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BT16rr, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BT32mi8, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BT32mr, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BT32ri8, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BT32rr, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BT64mi8, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BT64mr, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BT64ri8, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BT64rr, X86_INS_BT: bt */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BTC16mi8, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTC16mr, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTC16ri8, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTC16rr, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTC32mi8, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTC32mr, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTC32ri8, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTC32rr, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTC64mi8, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTC64mr, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTC64ri8, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTC64rr, X86_INS_BTC: btc */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTR16mi8, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTR16mr, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTR16ri8, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTR16rr, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTR32mi8, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTR32mr, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTR32ri8, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTR32rr, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTR64mi8, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTR64mr, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTR64ri8, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTR64rr, X86_INS_BTR: btr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTS16mi8, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTS16mr, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTS16ri8, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTS16rr, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTS32mi8, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTS32mr, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTS32ri8, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTS32rr, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTS64mi8, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTS64mr, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BTS64ri8, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_BTS64rr, X86_INS_BTS: bts */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_BZHI32rm, X86_INS_BZHI: bzhi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BZHI32rr, X86_INS_BZHI: bzhi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BZHI64rm, X86_INS_BZHI: bzhi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_BZHI64rr, X86_INS_BZHI: bzhi */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CALL16m, X86_INS_CALL: call */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CALL16m_NT, X86_INS_CALL: call */ + 0, + { 0 } +}, + +{ /* X86_CALL16r, X86_INS_CALL: call */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CALL16r_NT, X86_INS_CALL: call */ + 0, + { 0 } +}, + +{ /* X86_CALL32m, X86_INS_CALL: call */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CALL32m_NT, X86_INS_CALL: call */ + 0, + { 0 } +}, + +{ /* X86_CALL32r, X86_INS_CALL: call */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_CALL32r_NT, X86_INS_CALL: call */ + 0, + { 0 } +}, + +{ /* X86_CALL64m, X86_INS_CALL: call */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_CALL64m_NT, X86_INS_CALL: call */ + 0, + { 0 } +}, + +{ /* X86_CALL64pcrel32, X86_INS_CALL: call */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_CALL64r, X86_INS_CALL: call */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_CALL64r_NT, X86_INS_CALL: call */ + 0, + { 0 } +}, + +{ /* X86_CALLpcrel16, X86_INS_CALL: call */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_CALLpcrel32, X86_INS_CALL: call */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_CBW, X86_INS_CBW: cbw */ + 0, + { 0 } +}, + +{ /* X86_CDQ, X86_INS_CDQ: cdq */ + 0, + { 0 } +}, + +{ /* X86_CDQE, X86_INS_CDQE: cdqe */ + 0, + { 0 } +}, + +{ /* X86_CLAC, X86_INS_CLAC: clac */ + X86_EFLAGS_RESET_AC, + { 0 } +}, + +{ /* X86_CLC, X86_INS_CLC: clc */ + X86_EFLAGS_RESET_CF, + { 0 } +}, + +{ /* X86_CLD, X86_INS_CLD: cld */ + X86_EFLAGS_RESET_DF, + { 0 } +}, + +{ /* X86_CLDEMOTE, X86_INS_CLDEMOTE: cldemote */ + 0, + { 0 } +}, + +{ /* X86_CLFLUSHOPT, X86_INS_CLFLUSHOPT: clflushopt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CLGI, X86_INS_CLGI: clgi */ + 0, + { 0 } +}, + +{ /* X86_CLI, X86_INS_CLI: cli */ + X86_EFLAGS_RESET_IF, + { 0 } +}, + +{ /* X86_CLRSSBSY, X86_INS_CLRSSBSY: clrssbsy */ + 0, + { 0 } +}, + +{ /* X86_CLTS, X86_INS_CLTS: clts */ + 0, + { 0 } +}, + +{ /* X86_CLWB, X86_INS_CLWB: clwb */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_CLZEROr, X86_INS_CLZERO: clzero */ + 0, + { 0 } +}, + +{ /* X86_CMC, X86_INS_CMC: cmc */ + X86_EFLAGS_MODIFY_CF, + { 0 } +}, + +{ /* X86_CMOVA16rm, X86_INS_CMOVA: cmova */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVA16rr, X86_INS_CMOVA: cmova */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVA32rm, X86_INS_CMOVA: cmova */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVA32rr, X86_INS_CMOVA: cmova */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVA64rm, X86_INS_CMOVA: cmova */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVA64rr, X86_INS_CMOVA: cmova */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVAE16rm, X86_INS_CMOVAE: cmovae */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVAE16rr, X86_INS_CMOVAE: cmovae */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVAE32rm, X86_INS_CMOVAE: cmovae */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVAE32rr, X86_INS_CMOVAE: cmovae */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVAE64rm, X86_INS_CMOVAE: cmovae */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVAE64rr, X86_INS_CMOVAE: cmovae */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVB16rm, X86_INS_CMOVB: cmovb */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVB16rr, X86_INS_CMOVB: cmovb */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVB32rm, X86_INS_CMOVB: cmovb */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVB32rr, X86_INS_CMOVB: cmovb */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVB64rm, X86_INS_CMOVB: cmovb */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVB64rr, X86_INS_CMOVB: cmovb */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE16rm, X86_INS_CMOVBE: cmovbe */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE16rr, X86_INS_CMOVBE: cmovbe */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE32rm, X86_INS_CMOVBE: cmovbe */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE32rr, X86_INS_CMOVBE: cmovbe */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE64rm, X86_INS_CMOVBE: cmovbe */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVBE64rr, X86_INS_CMOVBE: cmovbe */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVE16rm, X86_INS_CMOVE: cmove */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVE16rr, X86_INS_CMOVE: cmove */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVE32rm, X86_INS_CMOVE: cmove */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVE32rr, X86_INS_CMOVE: cmove */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVE64rm, X86_INS_CMOVE: cmove */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVE64rr, X86_INS_CMOVE: cmove */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVG16rm, X86_INS_CMOVG: cmovg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVG16rr, X86_INS_CMOVG: cmovg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVG32rm, X86_INS_CMOVG: cmovg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVG32rr, X86_INS_CMOVG: cmovg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVG64rm, X86_INS_CMOVG: cmovg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVG64rr, X86_INS_CMOVG: cmovg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVGE16rm, X86_INS_CMOVGE: cmovge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVGE16rr, X86_INS_CMOVGE: cmovge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVGE32rm, X86_INS_CMOVGE: cmovge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVGE32rr, X86_INS_CMOVGE: cmovge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVGE64rm, X86_INS_CMOVGE: cmovge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVGE64rr, X86_INS_CMOVGE: cmovge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVL16rm, X86_INS_CMOVL: cmovl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVL16rr, X86_INS_CMOVL: cmovl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVL32rm, X86_INS_CMOVL: cmovl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVL32rr, X86_INS_CMOVL: cmovl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVL64rm, X86_INS_CMOVL: cmovl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVL64rr, X86_INS_CMOVL: cmovl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVLE16rm, X86_INS_CMOVLE: cmovle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVLE16rr, X86_INS_CMOVLE: cmovle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVLE32rm, X86_INS_CMOVLE: cmovle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVLE32rr, X86_INS_CMOVLE: cmovle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVLE64rm, X86_INS_CMOVLE: cmovle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVLE64rr, X86_INS_CMOVLE: cmovle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNE16rm, X86_INS_CMOVNE: cmovne */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNE16rr, X86_INS_CMOVNE: cmovne */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNE32rm, X86_INS_CMOVNE: cmovne */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNE32rr, X86_INS_CMOVNE: cmovne */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNE64rm, X86_INS_CMOVNE: cmovne */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNE64rr, X86_INS_CMOVNE: cmovne */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNO16rm, X86_INS_CMOVNO: cmovno */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNO16rr, X86_INS_CMOVNO: cmovno */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNO32rm, X86_INS_CMOVNO: cmovno */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNO32rr, X86_INS_CMOVNO: cmovno */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNO64rm, X86_INS_CMOVNO: cmovno */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNO64rr, X86_INS_CMOVNO: cmovno */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP16rm, X86_INS_CMOVNP: cmovnp */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP16rr, X86_INS_CMOVNP: cmovnp */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP32rm, X86_INS_CMOVNP: cmovnp */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP32rr, X86_INS_CMOVNP: cmovnp */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP64rm, X86_INS_CMOVNP: cmovnp */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNP64rr, X86_INS_CMOVNP: cmovnp */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNS16rm, X86_INS_CMOVNS: cmovns */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNS16rr, X86_INS_CMOVNS: cmovns */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNS32rm, X86_INS_CMOVNS: cmovns */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNS32rr, X86_INS_CMOVNS: cmovns */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNS64rm, X86_INS_CMOVNS: cmovns */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVNS64rr, X86_INS_CMOVNS: cmovns */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVO16rm, X86_INS_CMOVO: cmovo */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVO16rr, X86_INS_CMOVO: cmovo */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVO32rm, X86_INS_CMOVO: cmovo */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVO32rr, X86_INS_CMOVO: cmovo */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVO64rm, X86_INS_CMOVO: cmovo */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVO64rr, X86_INS_CMOVO: cmovo */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP16rm, X86_INS_CMOVP: cmovp */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP16rr, X86_INS_CMOVP: cmovp */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP32rm, X86_INS_CMOVP: cmovp */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP32rr, X86_INS_CMOVP: cmovp */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP64rm, X86_INS_CMOVP: cmovp */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVP64rr, X86_INS_CMOVP: cmovp */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVS16rm, X86_INS_CMOVS: cmovs */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVS16rr, X86_INS_CMOVS: cmovs */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVS32rm, X86_INS_CMOVS: cmovs */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVS32rr, X86_INS_CMOVS: cmovs */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVS64rm, X86_INS_CMOVS: cmovs */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMOVS64rr, X86_INS_CMOVS: cmovs */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMP16i16, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP16mi, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP16mi8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP16mr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP16ri, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP16ri8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP16rm, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP16rr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP16rr_REV, X86_INS_CMP: cmp{w} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP32i32, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP32mi, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP32mi8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP32mr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP32ri, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP32ri8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP32rm, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP32rr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP32rr_REV, X86_INS_CMP: cmp{l} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP64i32, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP64mi32, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP64mi8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP64mr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP64ri32, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP64ri8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP64rm, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP64rr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP64rr_REV, X86_INS_CMP: cmp{q} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP8i8, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP8mi, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP8mi8, X86_INS_CMP: cmp{b} $dst $src */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP8mr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP8ri, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP8ri8, X86_INS_CMP: cmp{b} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMP8rm, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP8rr, X86_INS_CMP: cmp */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMP8rr_REV, X86_INS_CMP: cmp{b} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPSB, X86_INS_CMPSB: cmpsb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPSL, X86_INS_CMPSD: cmpsd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_IGNORE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_CMPSQ, X86_INS_CMPSQ: cmpsq */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPSW, X86_INS_CMPSW: cmpsw */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG16B, X86_INS_CMPXCHG16B: cmpxchg16b */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG16rm, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG16rr, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG32rm, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG32rr, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG64rm, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG64rr, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG8B, X86_INS_CMPXCHG8B: cmpxchg8b */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG8rm, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_CMPXCHG8rr, X86_INS_CMPXCHG: cmpxchg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_CPUID, X86_INS_CPUID: cpuid */ + 0, + { 0 } +}, + +{ /* X86_CQO, X86_INS_CQO: cqo */ + 0, + { 0 } +}, + +{ /* X86_CWD, X86_INS_CWD: cwd */ + 0, + { 0 } +}, + +{ /* X86_CWDE, X86_INS_CWDE: cwde */ + 0, + { 0 } +}, + +{ /* X86_DAA, X86_INS_DAA: daa */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { 0 } +}, + +{ /* X86_DAS, X86_INS_DAS: das */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { 0 } +}, + +{ /* X86_DATA16_PREFIX, X86_INS_DATA16: data16 */ + 0, + { 0 } +}, + +{ /* X86_DEC16m, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC16r, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC16r_alt, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC32m, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC32r, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC32r_alt, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC64m, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC64r, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC8m, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DEC8r, X86_INS_DEC: dec */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_DIV16m, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV16r, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV32m, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV32r, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV64m, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV64r, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV8m, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_DIV8r, X86_INS_DIV: div */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_ENDBR32, X86_INS_ENDBR32: endbr32 */ + 0, + { 0 } +}, + +{ /* X86_ENDBR64, X86_INS_ENDBR64: endbr64 */ + 0, + { 0 } +}, + +{ /* X86_ENTER, X86_INS_ENTER: enter */ + 0, + { CS_AC_IGNORE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_FARCALL16i, X86_INS_LCALL: lcall{w} $seg : $off */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_FARCALL16m, X86_INS_LCALL: lcall */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_FARCALL32i, X86_INS_LCALL: lcall{l} $seg : $off */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_FARCALL32m, X86_INS_CALL: call */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_FARCALL64, X86_INS_LCALL: lcall */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_FARJMP16i, X86_INS_LJMP: ljmp{w} $seg : $off */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_FARJMP16m, X86_INS_LJMP: ljmp{w} {*}$dst */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_FARJMP32i, X86_INS_LJMP: ljmp{l} $seg : $off */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_FARJMP32m, X86_INS_JMP: jmp */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_FARJMP64, X86_INS_LJMP: ljmp */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_FSETPM, X86_INS_FSETPM: fsetpm */ + 0, + { 0 } +}, + +{ /* X86_GETSEC, X86_INS_GETSEC: getsec */ + 0, + { 0 } +}, + +{ /* X86_HLT, X86_INS_HLT: hlt */ + 0, + { 0 } +}, + +{ /* X86_IDIV16m, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV16r, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV32m, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV32r, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV64m, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV64r, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV8m, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IDIV8r, X86_INS_IDIV: idiv */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL16m, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL16r, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL16rm, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IMUL16rmi, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL16rmi8, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL16rr, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IMUL16rri, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL16rri8, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL32m, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL32r, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL32rm, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IMUL32rmi, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL32rmi8, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL32rr, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IMUL32rri, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL32rri8, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL64m, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL64r, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL64rm, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IMUL64rmi32, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL64rmi8, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL64rr, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IMUL64rri32, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL64rri8, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IMUL8m, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IMUL8r, X86_INS_IMUL: imul */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_IN16ri, X86_INS_IN: in */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IN16rr, X86_INS_IN: in */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IN32ri, X86_INS_IN: in */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IN32rr, X86_INS_IN: in */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_IN8ri, X86_INS_IN: in */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_IN8rr, X86_INS_IN: in */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_INC16m, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC16r, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC16r_alt, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC32m, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC32r, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC32r_alt, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC64m, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC64r, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC8m, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INC8r, X86_INS_INC: inc */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_INCSSPD, X86_INS_INCSSPD: incsspd */ + 0, + { 0 } +}, + +{ /* X86_INCSSPQ, X86_INS_INCSSPQ: incsspq */ + 0, + { 0 } +}, + +{ /* X86_INSB, X86_INS_INSB: insb */ + 0, + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_INSL, X86_INS_INSD: insd */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_INSW, X86_INS_INSW: insw */ + 0, + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_INT, X86_INS_INT: int */ + X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_INT1, X86_INS_INT1: int1 */ + X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_INT3, X86_INS_INT3: int3 */ + X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_INTO, X86_INS_INTO: into */ + X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_INVD, X86_INS_INVD: invd */ + 0, + { 0 } +}, + +{ /* X86_INVEPT32, X86_INS_INVEPT: invept */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVEPT64, X86_INS_INVEPT: invept */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVLPG, X86_INS_INVLPG: invlpg */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_INVLPGA32, X86_INS_INVLPGA: invlpga */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVLPGA64, X86_INS_INVLPGA: invlpga */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVPCID32, X86_INS_INVPCID: invpcid */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVPCID64, X86_INS_INVPCID: invpcid */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVVPID32, X86_INS_INVVPID: invvpid */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_INVVPID64, X86_INS_INVVPID: invvpid */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_IRET16, X86_INS_IRET: iret */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_IRET32, X86_INS_IRETD: iretd */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_IRET64, X86_INS_IRETQ: iretq */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_JAE_1, X86_INS_JAE: jae */ + X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JAE_2, X86_INS_JAE: jae $dst */ + X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JAE_4, X86_INS_JAE: jae $dst */ + X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JA_1, X86_INS_JA: ja */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JA_2, X86_INS_JA: ja $dst */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JA_4, X86_INS_JA: ja $dst */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JBE_1, X86_INS_JBE: jbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JBE_2, X86_INS_JBE: jbe $dst */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JBE_4, X86_INS_JBE: jbe $dst */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JB_1, X86_INS_JB: jb */ + X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JB_2, X86_INS_JB: jb $dst */ + X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JB_4, X86_INS_JB: jb $dst */ + X86_EFLAGS_TEST_CF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JCXZ, X86_INS_JCXZ: jcxz */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JECXZ, X86_INS_JECXZ: jecxz */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JE_1, X86_INS_JE: je */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JE_2, X86_INS_JE: je $dst */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JE_4, X86_INS_JE: je $dst */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JGE_1, X86_INS_JGE: jge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JGE_2, X86_INS_JGE: jge $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JGE_4, X86_INS_JGE: jge $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JG_1, X86_INS_JG: jg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JG_2, X86_INS_JG: jg $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JG_4, X86_INS_JG: jg $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JLE_1, X86_INS_JLE: jle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JLE_2, X86_INS_JLE: jle $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JLE_4, X86_INS_JLE: jle $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JL_1, X86_INS_JL: jl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JL_2, X86_INS_JL: jl $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JL_4, X86_INS_JL: jl $dst */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JMP16m, X86_INS_JMP: jmp */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_JMP16m_NT, X86_INS_JMP: jmp */ + 0, + { 0 } +}, + +{ /* X86_JMP16r, X86_INS_JMP: jmp */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JMP16r_NT, X86_INS_JMP: jmp */ + 0, + { 0 } +}, + +{ /* X86_JMP32m, X86_INS_JMP: jmp */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_JMP32m_NT, X86_INS_JMP: jmp */ + 0, + { 0 } +}, + +{ /* X86_JMP32r, X86_INS_JMP: jmp */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JMP32r_NT, X86_INS_JMP: jmp */ + 0, + { 0 } +}, + +{ /* X86_JMP64m, X86_INS_JMP: jmp */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_JMP64m_NT, X86_INS_JMP: jmp */ + 0, + { 0 } +}, + +{ /* X86_JMP64r, X86_INS_JMP: jmp */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JMP64r_NT, X86_INS_JMP: jmp */ + 0, + { 0 } +}, + +{ /* X86_JMP_1, X86_INS_JMP: jmp */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JMP_2, X86_INS_JMP: jmp $dst */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JMP_4, X86_INS_JMP: jmp $dst */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNE_1, X86_INS_JNE: jne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNE_2, X86_INS_JNE: jne $dst */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNE_4, X86_INS_JNE: jne $dst */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNO_1, X86_INS_JNO: jno */ + X86_EFLAGS_TEST_OF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNO_2, X86_INS_JNO: jno $dst */ + X86_EFLAGS_TEST_OF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNO_4, X86_INS_JNO: jno $dst */ + X86_EFLAGS_TEST_OF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNP_1, X86_INS_JNP: jnp */ + X86_EFLAGS_TEST_PF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNP_2, X86_INS_JNP: jnp $dst */ + X86_EFLAGS_TEST_PF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNP_4, X86_INS_JNP: jnp $dst */ + X86_EFLAGS_TEST_PF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNS_1, X86_INS_JNS: jns */ + X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNS_2, X86_INS_JNS: jns $dst */ + X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JNS_4, X86_INS_JNS: jns $dst */ + X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JO_1, X86_INS_JO: jo */ + X86_EFLAGS_TEST_OF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JO_2, X86_INS_JO: jo $dst */ + X86_EFLAGS_TEST_OF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JO_4, X86_INS_JO: jo $dst */ + X86_EFLAGS_TEST_OF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JP_1, X86_INS_JP: jp */ + X86_EFLAGS_TEST_PF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JP_2, X86_INS_JP: jp $dst */ + X86_EFLAGS_TEST_PF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JP_4, X86_INS_JP: jp $dst */ + X86_EFLAGS_TEST_PF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JRCXZ, X86_INS_JRCXZ: jrcxz */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JS_1, X86_INS_JS: js */ + X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JS_2, X86_INS_JS: js $dst */ + X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_JS_4, X86_INS_JS: js $dst */ + X86_EFLAGS_TEST_SF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LAHF, X86_INS_LAHF: lahf */ + 0, + { 0 } +}, + +{ /* X86_LAR16rm, X86_INS_LAR: lar */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LAR16rr, X86_INS_LAR: lar */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LAR32rm, X86_INS_LAR: lar */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LAR32rr, X86_INS_LAR: lar */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LAR64rm, X86_INS_LAR: lar */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LAR64rr, X86_INS_LAR: lar */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LDS16rm, X86_INS_LDS: lds */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LDS32rm, X86_INS_LDS: lds */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LEA16r, X86_INS_LEA: lea */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_LEA32r, X86_INS_LEA: lea */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_LEA64_32r, X86_INS_LEA: lea */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_LEA64r, X86_INS_LEA: lea */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_LEAVE, X86_INS_LEAVE: leave */ + 0, + { 0 } +}, + +{ /* X86_LEAVE64, X86_INS_LEAVE: leave */ + 0, + { 0 } +}, + +{ /* X86_LES16rm, X86_INS_LES: les */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LES32rm, X86_INS_LES: les */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LFS16rm, X86_INS_LFS: lfs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LFS32rm, X86_INS_LFS: lfs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LFS64rm, X86_INS_LFS: lfs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LGDT16m, X86_INS_LGDT: lgdt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LGDT32m, X86_INS_LGDT: lgdt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LGDT64m, X86_INS_LGDT: lgdt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LGS16rm, X86_INS_LGS: lgs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LGS32rm, X86_INS_LGS: lgs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LGS64rm, X86_INS_LGS: lgs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LIDT16m, X86_INS_LIDT: lidt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LIDT32m, X86_INS_LIDT: lidt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LIDT64m, X86_INS_LIDT: lidt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LLDT16m, X86_INS_LLDT: lldt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LLDT16r, X86_INS_LLDT: lldt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LLWPCB, X86_INS_LLWPCB: llwpcb */ + 0, + { 0 } +}, + +{ /* X86_LLWPCB64, X86_INS_LLWPCB: llwpcb */ + 0, + { 0 } +}, + +{ /* X86_LMSW16m, X86_INS_LMSW: lmsw */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LMSW16r, X86_INS_LMSW: lmsw */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LOCK_PREFIX, X86_INS_LOCK: lock */ + 0, + { 0 } +}, + +{ /* X86_LODSB, X86_INS_LODSB: lodsb */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LODSL, X86_INS_LODSD: lodsd */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LODSQ, X86_INS_LODSQ: lodsq */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LODSW, X86_INS_LODSW: lodsw */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LOOP, X86_INS_LOOP: loop */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LOOPE, X86_INS_LOOPE: loope */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LOOPNE, X86_INS_LOOPNE: loopne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LRETIL, X86_INS_RETF: retf */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LRETIQ, X86_INS_RETFQ: retfq */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LRETIW, X86_INS_RETF: retf */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_LRETL, X86_INS_RETF: retf */ + 0, + { 0 } +}, + +{ /* X86_LRETQ, X86_INS_RETFQ: retfq */ + 0, + { 0 } +}, + +{ /* X86_LRETW, X86_INS_RETF: retf */ + 0, + { 0 } +}, + +{ /* X86_LSL16rm, X86_INS_LSL: lsl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSL16rr, X86_INS_LSL: lsl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSL32rm, X86_INS_LSL: lsl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSL32rr, X86_INS_LSL: lsl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSL64rm, X86_INS_LSL: lsl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSL64rr, X86_INS_LSL: lsl */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSS16rm, X86_INS_LSS: lss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSS32rm, X86_INS_LSS: lss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LSS64rm, X86_INS_LSS: lss */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LTRm, X86_INS_LTR: ltr */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LTRr, X86_INS_LTR: ltr */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_LWPINS32rmi, X86_INS_LWPINS: lwpins */ + 0, + { 0 } +}, + +{ /* X86_LWPINS32rri, X86_INS_LWPINS: lwpins */ + 0, + { 0 } +}, + +{ /* X86_LWPINS64rmi, X86_INS_LWPINS: lwpins */ + 0, + { 0 } +}, + +{ /* X86_LWPINS64rri, X86_INS_LWPINS: lwpins */ + 0, + { 0 } +}, + +{ /* X86_LWPVAL32rmi, X86_INS_LWPVAL: lwpval */ + 0, + { 0 } +}, + +{ /* X86_LWPVAL32rri, X86_INS_LWPVAL: lwpval */ + 0, + { 0 } +}, + +{ /* X86_LWPVAL64rmi, X86_INS_LWPVAL: lwpval */ + 0, + { 0 } +}, + +{ /* X86_LWPVAL64rri, X86_INS_LWPVAL: lwpval */ + 0, + { 0 } +}, + +{ /* X86_LZCNT16rm, X86_INS_LZCNT: lzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LZCNT16rr, X86_INS_LZCNT: lzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LZCNT32rm, X86_INS_LZCNT: lzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LZCNT32rr, X86_INS_LZCNT: lzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LZCNT64rm, X86_INS_LZCNT: lzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_LZCNT64rr, X86_INS_LZCNT: lzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MONITORXrrr, X86_INS_MONITORX: monitorx */ + 0, + { 0 } +}, + +{ /* X86_MONTMUL, X86_INS_MONTMUL: montmul */ + 0, + { 0 } +}, + +{ /* X86_MOV16ao16, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16ao32, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16ao64, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16mi, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV16mr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16ms, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16o16a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16o32a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16o64a, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16ri, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV16ri_alt, X86_INS_MOV: mov{w} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV16rm, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16rr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16rr_REV, X86_INS_MOV: mov{w} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16rs, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16sm, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV16sr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32ao16, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32ao32, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32ao64, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32cr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32dr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32mi, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV32mr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32o16a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32o32a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32o64a, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32rc, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32rd, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32ri, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV32ri_alt, X86_INS_MOV: mov{l} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV32rm, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32rr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32rr_REV, X86_INS_MOV: mov{l} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32rs, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV32sr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64ao32, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64ao64, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64cr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64dr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64mi32, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV64mr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64o32a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64o64a, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64rc, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64rd, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64ri, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV64ri32, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV64rm, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64rr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64rr_REV, X86_INS_MOV: mov{q} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64rs, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV64sr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8ao16, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8ao32, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8ao64, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8mi, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV8mr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8mr_NOREX, X86_INS_MOV: mov{b} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8o16a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8o32a, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8o64a, X86_INS_MOVABS: movabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8ri, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV8ri_alt, X86_INS_MOV: mov{b} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_MOV8rm, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8rm_NOREX, X86_INS_MOV: mov{b} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8rr, X86_INS_MOV: mov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8rr_NOREX, X86_INS_MOV: mov{b} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOV8rr_REV, X86_INS_MOV: mov{b} $dst $src */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVBE16mr, X86_INS_MOVBE: movbe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVBE16rm, X86_INS_MOVBE: movbe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVBE32mr, X86_INS_MOVBE: movbe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVBE32rm, X86_INS_MOVBE: movbe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVBE64mr, X86_INS_MOVBE: movbe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVBE64rm, X86_INS_MOVBE: movbe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVDIR64B16, X86_INS_MOVDIR64B: movdir64b */ + 0, + { 0 } +}, + +{ /* X86_MOVDIR64B32, X86_INS_MOVDIR64B: movdir64b */ + 0, + { 0 } +}, + +{ /* X86_MOVDIR64B64, X86_INS_MOVDIR64B: movdir64b */ + 0, + { 0 } +}, + +{ /* X86_MOVDIRI32, X86_INS_MOVDIRI: movdiri */ + 0, + { 0 } +}, + +{ /* X86_MOVDIRI64, X86_INS_MOVDIRI: movdiri */ + 0, + { 0 } +}, + +{ /* X86_MOVSB, X86_INS_MOVSB: movsb */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSL, X86_INS_MOVSD: movsd */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSQ, X86_INS_MOVSQ: movsq */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSW, X86_INS_MOVSW: movsw */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX16rm16, X86_INS_MOVSX: movsx */ + 0, + { 0 } +}, + +{ /* X86_MOVSX16rm8, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX16rr16, X86_INS_MOVSX: movsx */ + 0, + { 0 } +}, + +{ /* X86_MOVSX16rr8, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX32rm16, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX32rm8, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX32rm8_NOREX, X86_INS_MOVSX: movsx */ + 0, + { 0 } +}, + +{ /* X86_MOVSX32rr16, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX32rr8, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX32rr8_NOREX, X86_INS_MOVSX: movsx */ + 0, + { 0 } +}, + +{ /* X86_MOVSX64rm16, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX64rm32, X86_INS_MOVSXD: movsxd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX64rm8, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX64rr16, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX64rr32, X86_INS_MOVSXD: movsxd */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVSX64rr8, X86_INS_MOVSX: movsx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX16rm16, X86_INS_MOVZX: movzx */ + 0, + { 0 } +}, + +{ /* X86_MOVZX16rm8, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX16rr16, X86_INS_MOVZX: movzx */ + 0, + { 0 } +}, + +{ /* X86_MOVZX16rr8, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX32rm16, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX32rm8, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX32rm8_NOREX, X86_INS_MOVZX: movzx */ + 0, + { 0 } +}, + +{ /* X86_MOVZX32rr16, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX32rr8, X86_INS_MOVZX: movzx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MOVZX32rr8_NOREX, X86_INS_MOVZX: movzx */ + 0, + { 0 } +}, + +{ /* X86_MOVZX64rm16, X86_INS_MOVZX: movzx */ + 0, + { 0 } +}, + +{ /* X86_MOVZX64rm8, X86_INS_MOVZX: movzx */ + 0, + { 0 } +}, + +{ /* X86_MOVZX64rr16, X86_INS_MOVZX: movzx */ + 0, + { 0 } +}, + +{ /* X86_MOVZX64rr8, X86_INS_MOVZX: movzx */ + 0, + { 0 } +}, + +{ /* X86_MUL16m, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL16r, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL32m, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL32r, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL64m, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL64r, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL8m, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MUL8r, X86_INS_MUL: mul */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_MULX32rm, X86_INS_MULX: mulx */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULX32rr, X86_INS_MULX: mulx */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULX64rm, X86_INS_MULX: mulx */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MULX64rr, X86_INS_MULX: mulx */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_MWAITXrrr, X86_INS_MWAITX: mwaitx */ + 0, + { 0 } +}, + +{ /* X86_NEG16m, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG16r, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG32m, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG32r, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG64m, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG64r, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG8m, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NEG8r, X86_INS_NEG: neg */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOOP, X86_INS_NOP: nop */ + 0, + { 0 } +}, + +{ /* X86_NOOP18_16m4, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16m5, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16m6, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16m7, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16r4, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16r5, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16r6, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_16r7, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_m4, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_m5, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_m6, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_m7, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_r4, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_r5, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_r6, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP18_r7, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOP19rr, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_NOOPL, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPL_19, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPL_1d, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPL_1e, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPLr, X86_INS_NOP: nop */ + 0, + { 0 } +}, + +{ /* X86_NOOPQ, X86_INS_NOP: nop */ + 0, + { 0 } +}, + +{ /* X86_NOOPQr, X86_INS_NOP: nop */ + 0, + { 0 } +}, + +{ /* X86_NOOPW, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPW_19, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPW_1c, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPW_1d, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPW_1e, X86_INS_NOP: nop */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_NOOPWr, X86_INS_NOP: nop */ + 0, + { 0 } +}, + +{ /* X86_NOT16m, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT16r, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT32m, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT32r, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT64m, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT64r, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT8m, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_NOT8r, X86_INS_NOT: not */ + 0, + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_OR16i16, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR16mi, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR16mi8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR16mr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR16ri, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR16ri8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR16rm, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR16rr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR16rr_REV, X86_INS_OR: or{w} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR32i32, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR32mi, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR32mi8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR32mr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR32ri, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR32ri8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR32rm, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR32rr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR32rr_REV, X86_INS_OR: or{l} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR64i32, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR64mi32, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR64mi8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR64mr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR64ri32, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR64ri8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR64rm, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR64rr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR64rr_REV, X86_INS_OR: or{q} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR8i8, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR8mi, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR8mi8, X86_INS_OR: or{b} $dst $src */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR8mr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR8ri, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR8ri8, X86_INS_OR: or{b} $src1 $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OR8rm, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR8rr, X86_INS_OR: or */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OR8rr_REV, X86_INS_OR: or{b} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_OUT16ir, X86_INS_OUT: out */ + 0, + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_OUT16rr, X86_INS_OUT: out */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_OUT32ir, X86_INS_OUT: out */ + 0, + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_OUT32rr, X86_INS_OUT: out */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_OUT8ir, X86_INS_OUT: out */ + 0, + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* X86_OUT8rr, X86_INS_OUT: out */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_OUTSB, X86_INS_OUTSB: outsb */ + X86_EFLAGS_TEST_DF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_OUTSL, X86_INS_OUTSD: outsd */ + X86_EFLAGS_TEST_DF, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_OUTSW, X86_INS_OUTSW: outsw */ + X86_EFLAGS_TEST_DF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_PCONFIG, X86_INS_PCONFIG: pconfig */ + 0, + { 0 } +}, + +{ /* X86_PDEP32rm, X86_INS_PDEP: pdep */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PDEP32rr, X86_INS_PDEP: pdep */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PDEP64rm, X86_INS_PDEP: pdep */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PDEP64rr, X86_INS_PDEP: pdep */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PEXT32rm, X86_INS_PEXT: pext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PEXT32rr, X86_INS_PEXT: pext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PEXT64rm, X86_INS_PEXT: pext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_PEXT64rr, X86_INS_PEXT: pext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_POP16r, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP16rmm, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP16rmr, X86_INS_POP: pop{w} $reg */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP32r, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP32rmm, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP32rmr, X86_INS_POP: pop{l} $reg */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP64r, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP64rmm, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POP64rmr, X86_INS_POP: pop{q} $reg */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPA16, X86_INS_POPAW: popaw */ + 0, + { 0 } +}, + +{ /* X86_POPA32, X86_INS_POPAL: popal */ + 0, + { 0 } +}, + +{ /* X86_POPDS16, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPDS32, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPES16, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPES32, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPF16, X86_INS_POPF: popf */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_POPF32, X86_INS_POPFD: popfd */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_POPF64, X86_INS_POPFQ: popfq */ + X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_POPFS16, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPFS32, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPFS64, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPGS16, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPGS32, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPGS64, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPSS16, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_POPSS32, X86_INS_POP: pop */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_PTWRITE64m, X86_INS_PTWRITE: ptwrite */ + 0, + { 0 } +}, + +{ /* X86_PTWRITE64r, X86_INS_PTWRITE: ptwrite */ + 0, + { 0 } +}, + +{ /* X86_PTWRITEm, X86_INS_PTWRITE: ptwrite */ + 0, + { 0 } +}, + +{ /* X86_PTWRITEr, X86_INS_PTWRITE: ptwrite */ + 0, + { 0 } +}, + +{ /* X86_PUSH16i8, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSH16r, X86_INS_PUSH: push */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH16rmm, X86_INS_PUSH: push */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH16rmr, X86_INS_PUSH: push{w} $reg */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH32i8, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSH32r, X86_INS_PUSH: push */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH32rmm, X86_INS_PUSH: push */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH32rmr, X86_INS_PUSH: push{l} $reg */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH64i32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSH64i8, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSH64r, X86_INS_PUSH: push */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH64rmm, X86_INS_PUSH: push */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSH64rmr, X86_INS_PUSH: push{q} $reg */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_PUSHA16, X86_INS_PUSHAW: pushaw */ + 0, + { 0 } +}, + +{ /* X86_PUSHA32, X86_INS_PUSHAL: pushal */ + 0, + { 0 } +}, + +{ /* X86_PUSHCS16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHCS32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHDS16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHDS32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHES16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHES32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHF16, X86_INS_PUSHF: pushf */ + 0, + { 0 } +}, + +{ /* X86_PUSHF32, X86_INS_PUSHFD: pushfd */ + 0, + { 0 } +}, + +{ /* X86_PUSHF64, X86_INS_PUSHFQ: pushfq */ + 0, + { 0 } +}, + +{ /* X86_PUSHFS16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHFS32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHFS64, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHGS16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHGS32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHGS64, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHSS16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHSS32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHi16, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_PUSHi32, X86_INS_PUSH: push */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL16m1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL16mCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCL16mi, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL16r1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL16rCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCL16ri, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL32m1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL32mCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCL32mi, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL32r1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL32rCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCL32ri, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL64m1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL64mCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCL64mi, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL64r1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL64rCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCL64ri, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL8m1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL8mCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCL8mi, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL8r1, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCL8rCL, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCL8ri, X86_INS_RCL: rcl */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR16m1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR16mCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCR16mi, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR16r1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR16rCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCR16ri, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR32m1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR32mCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCR32mi, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR32r1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR32rCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCR32ri, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR64m1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR64mCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCR64mi, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR64r1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR64rCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCR64ri, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR8m1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR8mCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_RCR8mi, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR8r1, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RCR8rCL, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_RCR8ri, X86_INS_RCR: rcr */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RDFSBASE, X86_INS_RDFSBASE: rdfsbase */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDFSBASE64, X86_INS_RDFSBASE: rdfsbase */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDGSBASE, X86_INS_RDGSBASE: rdgsbase */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDGSBASE64, X86_INS_RDGSBASE: rdgsbase */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDMSR, X86_INS_RDMSR: rdmsr */ + 0, + { 0 } +}, + +{ /* X86_RDPID32, X86_INS_RDPID: rdpid */ + 0, + { 0 } +}, + +{ /* X86_RDPID64, X86_INS_RDPID: rdpid */ + 0, + { 0 } +}, + +{ /* X86_RDPKRUr, X86_INS_RDPKRU: rdpkru */ + 0, + { 0 } +}, + +{ /* X86_RDPMC, X86_INS_RDPMC: rdpmc */ + 0, + { 0 } +}, + +{ /* X86_RDRAND16r, X86_INS_RDRAND: rdrand */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDRAND32r, X86_INS_RDRAND: rdrand */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDRAND64r, X86_INS_RDRAND: rdrand */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDSEED16r, X86_INS_RDSEED: rdseed */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDSEED32r, X86_INS_RDSEED: rdseed */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDSEED64r, X86_INS_RDSEED: rdseed */ + X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_RDSSPD, X86_INS_RDSSPD: rdsspd */ + 0, + { 0 } +}, + +{ /* X86_RDSSPQ, X86_INS_RDSSPQ: rdsspq */ + 0, + { 0 } +}, + +{ /* X86_RDTSC, X86_INS_RDTSC: rdtsc */ + 0, + { 0 } +}, + +{ /* X86_RDTSCP, X86_INS_RDTSCP: rdtscp */ + 0, + { 0 } +}, + +{ /* X86_REPNE_PREFIX, X86_INS_REPNE: repne */ + 0, + { 0 } +}, + +{ /* X86_REP_PREFIX, X86_INS_REP: rep */ + 0, + { 0 } +}, + +{ /* X86_RETIL, X86_INS_RET: ret */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_RETIQ, X86_INS_RET: ret */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_RETIW, X86_INS_RET: ret */ + 0, + { CS_AC_IGNORE, 0 } +}, + +{ /* X86_RETL, X86_INS_RET: ret */ + 0, + { 0 } +}, + +{ /* X86_RETQ, X86_INS_RET: ret */ + 0, + { 0 } +}, + +{ /* X86_RETW, X86_INS_RET: ret */ + 0, + { 0 } +}, + +{ /* X86_REX64_PREFIX, X86_INS_REX64: rex64 */ + 0, + { 0 } +}, + +{ /* X86_ROL16m1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL16mCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROL16mi, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL16r1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL16rCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROL16ri, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL32m1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL32mCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROL32mi, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL32r1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL32rCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROL32ri, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL64m1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL64mCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROL64mi, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL64r1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL64rCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROL64ri, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL8m1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL8mCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROL8mi, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL8r1, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROL8rCL, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROL8ri, X86_INS_ROL: rol */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR16m1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR16mCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROR16mi, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR16r1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR16rCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROR16ri, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR32m1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR32mCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROR32mi, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR32r1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR32rCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROR32ri, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR64m1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR64mCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROR64mi, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR64r1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR64rCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROR64ri, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR8m1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR8mCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_ROR8mi, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR8r1, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_ROR8rCL, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_ROR8ri, X86_INS_ROR: ror */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RORX32mi, X86_INS_RORX: rorx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RORX32ri, X86_INS_RORX: rorx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RORX64mi, X86_INS_RORX: rorx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RORX64ri, X86_INS_RORX: rorx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_RSM, X86_INS_RSM: rsm */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_RSTORSSP, X86_INS_RSTORSSP: rstorssp */ + 0, + { 0 } +}, + +{ /* X86_SAHF, X86_INS_SAHF: sahf */ + X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { 0 } +}, + +{ /* X86_SAL16m1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL16mCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL16mi, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL16r1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL16rCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL16ri, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL32m1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL32mCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL32mi, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL32r1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL32rCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL32ri, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL64m1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL64mCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL64mi, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL64r1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL64rCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL64ri, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL8m1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL8mCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL8mi, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL8r1, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAL8rCL, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAL8ri, X86_INS_SAL: sal */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SALC, X86_INS_SALC: salc */ + 0, + { 0 } +}, + +{ /* X86_SAR16m1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR16mCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR16mi, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR16r1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR16rCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR16ri, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR32m1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR32mCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR32mi, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR32r1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR32rCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR32ri, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR64m1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR64mCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR64mi, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR64r1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR64rCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR64ri, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR8m1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR8mCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR8mi, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR8r1, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SAR8rCL, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SAR8ri, X86_INS_SAR: sar */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SARX32rm, X86_INS_SARX: sarx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SARX32rr, X86_INS_SARX: sarx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SARX64rm, X86_INS_SARX: sarx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SARX64rr, X86_INS_SARX: sarx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SAVEPREVSSP, X86_INS_SAVEPREVSSP: saveprevssp */ + 0, + { 0 } +}, + +{ /* X86_SBB16i16, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB16mi, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB16mi8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB16mr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB16ri, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB16ri8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB16rm, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB16rr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB16rr_REV, X86_INS_SBB: sbb{w} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB32i32, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB32mi, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB32mi8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB32mr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB32ri, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB32ri8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB32rm, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB32rr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB32rr_REV, X86_INS_SBB: sbb{l} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB64i32, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB64mi32, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB64mi8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB64mr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB64ri32, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB64ri8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB64rm, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB64rr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB64rr_REV, X86_INS_SBB: sbb{q} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB8i8, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB8mi, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB8mi8, X86_INS_SBB: sbb{b} $dst $src */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB8mr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB8ri, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB8ri8, X86_INS_SBB: sbb{b} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SBB8rm, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB8rr, X86_INS_SBB: sbb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SBB8rr_REV, X86_INS_SBB: sbb{b} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_TEST_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SCASB, X86_INS_SCASB: scasb */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SCASL, X86_INS_SCASD: scasd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SCASQ, X86_INS_SCASQ: scasq */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SCASW, X86_INS_SCASW: scasw */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SETAEm, X86_INS_SETAE: setae */ + X86_EFLAGS_TEST_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETAEr, X86_INS_SETAE: setae */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETAm, X86_INS_SETA: seta */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETAr, X86_INS_SETA: seta */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETBEm, X86_INS_SETBE: setbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETBEr, X86_INS_SETBE: setbe */ + X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETBm, X86_INS_SETB: setb */ + X86_EFLAGS_TEST_CF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETBr, X86_INS_SETB: setb */ + X86_EFLAGS_TEST_CF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETEm, X86_INS_SETE: sete */ + X86_EFLAGS_TEST_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETEr, X86_INS_SETE: sete */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETGEm, X86_INS_SETGE: setge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETGEr, X86_INS_SETGE: setge */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETGm, X86_INS_SETG: setg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETGr, X86_INS_SETG: setg */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETLEm, X86_INS_SETLE: setle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETLEr, X86_INS_SETLE: setle */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETLm, X86_INS_SETL: setl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETLr, X86_INS_SETL: setl */ + X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETNEm, X86_INS_SETNE: setne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETNEr, X86_INS_SETNE: setne */ + X86_EFLAGS_TEST_ZF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETNOm, X86_INS_SETNO: setno */ + X86_EFLAGS_TEST_OF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETNOr, X86_INS_SETNO: setno */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETNPm, X86_INS_SETNP: setnp */ + X86_EFLAGS_TEST_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETNPr, X86_INS_SETNP: setnp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETNSm, X86_INS_SETNS: setns */ + X86_EFLAGS_TEST_SF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETNSr, X86_INS_SETNS: setns */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETOm, X86_INS_SETO: seto */ + X86_EFLAGS_TEST_OF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETOr, X86_INS_SETO: seto */ + X86_EFLAGS_TEST_OF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETPm, X86_INS_SETP: setp */ + X86_EFLAGS_TEST_PF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETPr, X86_INS_SETP: setp */ + X86_EFLAGS_TEST_PF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SETSSBSY, X86_INS_SETSSBSY: setssbsy */ + 0, + { 0 } +}, + +{ /* X86_SETSm, X86_INS_SETS: sets */ + X86_EFLAGS_TEST_SF, + { CS_AC_READ, 0 } +}, + +{ /* X86_SETSr, X86_INS_SETS: sets */ + X86_EFLAGS_TEST_SF, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SGDT16m, X86_INS_SGDT: sgdt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SGDT32m, X86_INS_SGDT: sgdt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SGDT64m, X86_INS_SGDT: sgdt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SHL16m1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL16mCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL16mi, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL16r1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL16rCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL16ri, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL32m1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL32mCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL32mi, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL32r1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL32rCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL32ri, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL64m1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL64mCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL64mi, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL64r1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL64rCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL64ri, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL8m1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL8mCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL8mi, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL8r1, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHL8rCL, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHL8ri, X86_INS_SHL: shl */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLD16mrCL, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLD16mri8, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLD16rrCL, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLD16rri8, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLD32mrCL, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLD32mri8, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLD32rrCL, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLD32rri8, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLD64mrCL, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLD64mri8, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLD64rrCL, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLD64rri8, X86_INS_SHLD: shld */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHLX32rm, X86_INS_SHLX: shlx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLX32rr, X86_INS_SHLX: shlx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLX64rm, X86_INS_SHLX: shlx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHLX64rr, X86_INS_SHLX: shlx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHR16m1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR16mCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR16mi, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR16r1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR16rCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR16ri, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR32m1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR32mCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR32mi, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR32r1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR32rCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR32ri, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR64m1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR64mCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR64mi, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR64r1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR64rCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR64ri, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR8m1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR8mCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR8mi, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR8r1, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHR8rCL, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SHR8ri, X86_INS_SHR: shr */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRD16mrCL, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRD16mri8, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRD16rrCL, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRD16rri8, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRD32mrCL, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRD32mri8, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRD32rrCL, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRD32rri8, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRD64mrCL, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRD64mri8, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRD64rrCL, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRD64rri8, X86_INS_SHRD: shrd */ + X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SHRX32rm, X86_INS_SHRX: shrx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRX32rr, X86_INS_SHRX: shrx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRX64rm, X86_INS_SHRX: shrx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SHRX64rr, X86_INS_SHRX: shrx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_SIDT16m, X86_INS_SIDT: sidt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SIDT32m, X86_INS_SIDT: sidt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SIDT64m, X86_INS_SIDT: sidt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SKINIT, X86_INS_SKINIT: skinit */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_SLDT16m, X86_INS_SLDT: sldt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SLDT16r, X86_INS_SLDT: sldt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SLDT32r, X86_INS_SLDT: sldt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SLDT64r, X86_INS_SLDT: sldt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SLWPCB, X86_INS_SLWPCB: slwpcb */ + 0, + { 0 } +}, + +{ /* X86_SLWPCB64, X86_INS_SLWPCB: slwpcb */ + 0, + { 0 } +}, + +{ /* X86_SMSW16m, X86_INS_SMSW: smsw */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SMSW16r, X86_INS_SMSW: smsw */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SMSW32r, X86_INS_SMSW: smsw */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SMSW64r, X86_INS_SMSW: smsw */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_STAC, X86_INS_STAC: stac */ + 0, + { 0 } +}, + +{ /* X86_STC, X86_INS_STC: stc */ + X86_EFLAGS_SET_CF, + { 0 } +}, + +{ /* X86_STD, X86_INS_STD: std */ + X86_EFLAGS_SET_DF, + { 0 } +}, + +{ /* X86_STGI, X86_INS_STGI: stgi */ + 0, + { 0 } +}, + +{ /* X86_STI, X86_INS_STI: sti */ + X86_EFLAGS_SET_IF, + { 0 } +}, + +{ /* X86_STOSB, X86_INS_STOSB: stosb */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_STOSL, X86_INS_STOSD: stosd */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_STOSQ, X86_INS_STOSQ: stosq */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_STOSW, X86_INS_STOSW: stosw */ + X86_EFLAGS_TEST_DF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_STR16r, X86_INS_STR: str */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_STR32r, X86_INS_STR: str */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_STR64r, X86_INS_STR: str */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_STRm, X86_INS_STR: str */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_SUB16i16, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB16mi, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB16mi8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB16mr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB16ri, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB16ri8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB16rm, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB16rr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB16rr_REV, X86_INS_SUB: sub{w} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB32i32, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB32mi, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB32mi8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB32mr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB32ri, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB32ri8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB32rm, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB32rr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB32rr_REV, X86_INS_SUB: sub{l} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB64i32, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB64mi32, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB64mi8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB64mr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB64ri32, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB64ri8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB64rm, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB64rr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB64rr_REV, X86_INS_SUB: sub{q} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB8i8, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB8mi, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB8mi8, X86_INS_SUB: sub{b} $dst $src */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB8mr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB8ri, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB8ri8, X86_INS_SUB: sub{b} $src1 $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_SUB8rm, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB8rr, X86_INS_SUB: sub */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SUB8rr_REV, X86_INS_SUB: sub{b} $dst $src2 */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_SWAPGS, X86_INS_SWAPGS: swapgs */ + 0, + { 0 } +}, + +{ /* X86_SYSCALL, X86_INS_SYSCALL: syscall */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_SYSENTER, X86_INS_SYSENTER: sysenter */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_SYSEXIT, X86_INS_SYSEXIT: sysexit */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_SYSEXIT64, X86_INS_SYSEXITQ: sysexitq */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_SYSRET, X86_INS_SYSRET: sysret */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_SYSRET64, X86_INS_SYSRETQ: sysretq */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, + { 0 } +}, + +{ /* X86_T1MSKC32rm, X86_INS_T1MSKC: t1mskc */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_T1MSKC32rr, X86_INS_T1MSKC: t1mskc */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_T1MSKC64rm, X86_INS_T1MSKC: t1mskc */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_T1MSKC64rr, X86_INS_T1MSKC: t1mskc */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TEST16i16, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST16mi, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST16mi_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST16mr, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST16ri, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST16ri_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST16rr, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_TEST32i32, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST32mi, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST32mi_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST32mr, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST32ri, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST32ri_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST32rr, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_TEST64i32, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST64mi32, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST64mi32_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST64mr, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST64ri32, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST64ri32_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST64rr, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_TEST8i8, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST8mi, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST8mi_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST8mr, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST8ri, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* X86_TEST8ri_alt, X86_INS_TEST: test */ + 0, + { 0 } +}, + +{ /* X86_TEST8rr, X86_INS_TEST: test */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* X86_TPAUSE, X86_INS_TPAUSE: tpause */ + 0, + { 0 } +}, + +{ /* X86_TZCNT16rm, X86_INS_TZCNT: tzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZCNT16rr, X86_INS_TZCNT: tzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZCNT32rm, X86_INS_TZCNT: tzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZCNT32rr, X86_INS_TZCNT: tzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZCNT64rm, X86_INS_TZCNT: tzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZCNT64rr, X86_INS_TZCNT: tzcnt */ + X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZMSK32rm, X86_INS_TZMSK: tzmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZMSK32rr, X86_INS_TZMSK: tzmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZMSK64rm, X86_INS_TZMSK: tzmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_TZMSK64rr, X86_INS_TZMSK: tzmsk */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_UD0, X86_INS_UD0: ud0 */ + 0, + { 0 } +}, + +{ /* X86_UD1, X86_INS_UD1: ud1 */ + 0, + { 0 } +}, + +{ /* X86_UD2, X86_INS_UD2: ud2 */ + 0, + { 0 } +}, + +{ /* X86_UMONITOR16, X86_INS_UMONITOR: umonitor */ + 0, + { 0 } +}, + +{ /* X86_UMONITOR32, X86_INS_UMONITOR: umonitor */ + 0, + { 0 } +}, + +{ /* X86_UMONITOR64, X86_INS_UMONITOR: umonitor */ + 0, + { 0 } +}, + +{ /* X86_UMWAIT, X86_INS_UMWAIT: umwait */ + 0, + { 0 } +}, + +{ /* X86_VERRm, X86_INS_VERR: verr */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_VERRr, X86_INS_VERR: verr */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_VERWm, X86_INS_VERW: verw */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_VERWr, X86_INS_VERW: verw */ + X86_EFLAGS_MODIFY_ZF, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMCALL, X86_INS_VMCALL: vmcall */ + 0, + { 0 } +}, + +{ /* X86_VMCLEARm, X86_INS_VMCLEAR: vmclear */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMFUNC, X86_INS_VMFUNC: vmfunc */ + 0, + { 0 } +}, + +{ /* X86_VMLAUNCH, X86_INS_VMLAUNCH: vmlaunch */ + 0, + { 0 } +}, + +{ /* X86_VMLOAD32, X86_INS_VMLOAD: vmload */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMLOAD64, X86_INS_VMLOAD: vmload */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMMCALL, X86_INS_VMMCALL: vmmcall */ + 0, + { 0 } +}, + +{ /* X86_VMPTRLDm, X86_INS_VMPTRLD: vmptrld */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMPTRSTm, X86_INS_VMPTRST: vmptrst */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_VMREAD32mr, X86_INS_VMREAD: vmread */ + 0, + { 0 } +}, + +{ /* X86_VMREAD32rr, X86_INS_VMREAD: vmread */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMREAD64mr, X86_INS_VMREAD: vmread */ + 0, + { 0 } +}, + +{ /* X86_VMREAD64rr, X86_INS_VMREAD: vmread */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMRESUME, X86_INS_VMRESUME: vmresume */ + 0, + { 0 } +}, + +{ /* X86_VMRUN32, X86_INS_VMRUN: vmrun */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMRUN64, X86_INS_VMRUN: vmrun */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMSAVE32, X86_INS_VMSAVE: vmsave */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMSAVE64, X86_INS_VMSAVE: vmsave */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_VMWRITE32rm, X86_INS_VMWRITE: vmwrite */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMWRITE32rr, X86_INS_VMWRITE: vmwrite */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMWRITE64rm, X86_INS_VMWRITE: vmwrite */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMWRITE64rr, X86_INS_VMWRITE: vmwrite */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_VMXOFF, X86_INS_VMXOFF: vmxoff */ + 0, + { 0 } +}, + +{ /* X86_VMXON, X86_INS_VMXON: vmxon */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_WBINVD, X86_INS_WBINVD: wbinvd */ + 0, + { 0 } +}, + +{ /* X86_WBNOINVD, X86_INS_WBNOINVD: wbnoinvd */ + 0, + { 0 } +}, + +{ /* X86_WRFSBASE, X86_INS_WRFSBASE: wrfsbase */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_WRFSBASE64, X86_INS_WRFSBASE: wrfsbase */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_WRGSBASE, X86_INS_WRGSBASE: wrgsbase */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_WRGSBASE64, X86_INS_WRGSBASE: wrgsbase */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_WRMSR, X86_INS_WRMSR: wrmsr */ + 0, + { 0 } +}, + +{ /* X86_WRPKRUr, X86_INS_WRPKRU: wrpkru */ + 0, + { 0 } +}, + +{ /* X86_WRSSD, X86_INS_WRSSD: wrssd */ + 0, + { 0 } +}, + +{ /* X86_WRSSQ, X86_INS_WRSSQ: wrssq */ + 0, + { 0 } +}, + +{ /* X86_WRUSSD, X86_INS_WRUSSD: wrussd */ + 0, + { 0 } +}, + +{ /* X86_WRUSSQ, X86_INS_WRUSSQ: wrussq */ + 0, + { 0 } +}, + +{ /* X86_XADD16rm, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD16rr, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD32rm, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD32rr, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD64rm, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD64rr, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD8rm, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XADD8rr, X86_INS_XADD: xadd */ + X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG16ar, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG16rm, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG16rr, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG32ar, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG32rm, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG32rr, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG64ar, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG64rm, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG64rr, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG8rm, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCHG8rr, X86_INS_XCHG: xchg */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* X86_XCRYPTCBC, X86_INS_XCRYPTCBC: xcryptcbc */ + 0, + { 0 } +}, + +{ /* X86_XCRYPTCFB, X86_INS_XCRYPTCFB: xcryptcfb */ + 0, + { 0 } +}, + +{ /* X86_XCRYPTCTR, X86_INS_XCRYPTCTR: xcryptctr */ + 0, + { 0 } +}, + +{ /* X86_XCRYPTECB, X86_INS_XCRYPTECB: xcryptecb */ + 0, + { 0 } +}, + +{ /* X86_XCRYPTOFB, X86_INS_XCRYPTOFB: xcryptofb */ + 0, + { 0 } +}, + +{ /* X86_XGETBV, X86_INS_XGETBV: xgetbv */ + 0, + { 0 } +}, + +{ /* X86_XLAT, X86_INS_XLATB: xlatb */ + 0, + { 0 } +}, + +{ /* X86_XOR16i16, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR16mi, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR16mi8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR16mr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR16ri, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR16ri8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR16rm, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR16rr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR16rr_REV, X86_INS_XOR: xor{w} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR32i32, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR32mi, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR32mi8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR32mr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR32ri, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR32ri8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR32rm, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR32rr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR32rr_REV, X86_INS_XOR: xor{l} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR64i32, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR64mi32, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR64mi8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR64mr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR64ri32, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR64ri8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR64rm, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR64rr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR64rr_REV, X86_INS_XOR: xor{q} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR8i8, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR8mi, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR8mi8, X86_INS_XOR: xor{b} $dst $src */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR8mr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR8ri, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR8ri8, X86_INS_XOR: xor{b} $src1 $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } +}, + +{ /* X86_XOR8rm, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR8rr, X86_INS_XOR: xor */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XOR8rr_REV, X86_INS_XOR: xor{b} $dst $src2 */ + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* X86_XRSTOR, X86_INS_XRSTOR: xrstor */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_XRSTOR64, X86_INS_XRSTOR64: xrstor64 */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_XRSTORS, X86_INS_XRSTORS: xrstors */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_XRSTORS64, X86_INS_XRSTORS64: xrstors64 */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* X86_XSAVE, X86_INS_XSAVE: xsave */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVE64, X86_INS_XSAVE64: xsave64 */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVEC, X86_INS_XSAVEC: xsavec */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVEC64, X86_INS_XSAVEC64: xsavec64 */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVEOPT, X86_INS_XSAVEOPT: xsaveopt */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVEOPT64, X86_INS_XSAVEOPT64: xsaveopt64 */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVES, X86_INS_XSAVES: xsaves */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSAVES64, X86_INS_XSAVES64: xsaves64 */ + 0, + { CS_AC_WRITE, 0 } +}, + +{ /* X86_XSETBV, X86_INS_XSETBV: xsetbv */ + 0, + { 0 } +}, + +{ /* X86_XSHA1, X86_INS_XSHA1: xsha1 */ + 0, + { 0 } +}, + +{ /* X86_XSHA256, X86_INS_XSHA256: xsha256 */ + 0, + { 0 } +}, + +{ /* X86_XSTORE, X86_INS_XSTORE: xstore */ + 0, + { 0 } +}, diff --git a/thirdparty/capstone/arch/X86/X86MappingInsn_reduce.inc b/thirdparty/capstone/arch/X86/X86MappingInsn_reduce.inc new file mode 100644 index 0000000..108fddc --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86MappingInsn_reduce.inc @@ -0,0 +1,10819 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + + +{ + X86_AAA, X86_INS_AAA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_AAD8i8, X86_INS_AAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_AAM8i8, X86_INS_AAM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_AAS, X86_INS_AAS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16i16, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16mi, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16mi8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16mr, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16ri, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16ri8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16rm, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16rr, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC16rr_REV, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32i32, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32mi, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32mi8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32mr, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32ri, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32ri8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32rm, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32rr, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC32rr_REV, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64i32, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64mi32, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64mi8, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64mr, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64ri32, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64ri8, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64rm, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64rr, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC64rr_REV, X86_INS_ADC, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8i8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8mi, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8mi8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8mr, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8ri, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8ri8, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8rm, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8rr, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADC8rr_REV, X86_INS_ADC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADCX32rm, X86_INS_ADCX, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADCX32rr, X86_INS_ADCX, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADCX64rm, X86_INS_ADCX, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADCX64rr, X86_INS_ADCX, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16i16, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16mi, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16mi8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16mr, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16ri, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16ri8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16rm, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16rr, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD16rr_REV, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32i32, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32mi, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32mi8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32mr, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32ri, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32ri8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32rm, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32rr, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD32rr_REV, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64i32, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64mi32, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64mi8, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64mr, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64ri32, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64ri8, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64rm, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64rr, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD64rr_REV, X86_INS_ADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8i8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8mi, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8mi8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8mr, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8ri, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8ri8, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8rm, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8rr, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADD8rr_REV, X86_INS_ADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ADOX32rm, X86_INS_ADOX, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADOX32rr, X86_INS_ADOX, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADOX64rm, X86_INS_ADOX, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_ADOX64rr, X86_INS_ADOX, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 +#endif +}, + +{ + X86_AND16i16, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16mi, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16mi8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16mr, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16ri, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16ri8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16rm, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16rr, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND16rr_REV, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32i32, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32mi, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32mi8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32mr, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32ri, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32ri8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32rm, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32rr, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND32rr_REV, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64i32, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64mi32, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64mi8, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64mr, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64ri32, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64ri8, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64rm, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64rr, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND64rr_REV, X86_INS_AND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8i8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8mi, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8mi8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_AND8mr, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8ri, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8ri8, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_AND8rm, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8rr, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_AND8rr_REV, X86_INS_AND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ANDN32rm, X86_INS_ANDN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDN32rr, X86_INS_ANDN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDN64rm, X86_INS_ANDN, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_ANDN64rr, X86_INS_ANDN, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_ARPL16mr, X86_INS_ARPL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_ARPL16rr, X86_INS_ARPL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTR32rm, X86_INS_BEXTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTR32rr, X86_INS_BEXTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTR64rm, X86_INS_BEXTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTR64rr, X86_INS_BEXTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTRI32mi, X86_INS_BEXTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTRI32ri, X86_INS_BEXTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTRI64mi, X86_INS_BEXTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BEXTRI64ri, X86_INS_BEXTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCFILL32rm, X86_INS_BLCFILL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCFILL32rr, X86_INS_BLCFILL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCFILL64rm, X86_INS_BLCFILL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCFILL64rr, X86_INS_BLCFILL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCI32rm, X86_INS_BLCI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCI32rr, X86_INS_BLCI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCI64rm, X86_INS_BLCI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCI64rr, X86_INS_BLCI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCIC32rm, X86_INS_BLCIC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCIC32rr, X86_INS_BLCIC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCIC64rm, X86_INS_BLCIC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCIC64rr, X86_INS_BLCIC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCMSK32rm, X86_INS_BLCMSK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCMSK32rr, X86_INS_BLCMSK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCMSK64rm, X86_INS_BLCMSK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCMSK64rr, X86_INS_BLCMSK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCS32rm, X86_INS_BLCS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCS32rr, X86_INS_BLCS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCS64rm, X86_INS_BLCS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLCS64rr, X86_INS_BLCS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSFILL32rm, X86_INS_BLSFILL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSFILL32rr, X86_INS_BLSFILL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSFILL64rm, X86_INS_BLSFILL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSFILL64rr, X86_INS_BLSFILL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSI32rm, X86_INS_BLSI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSI32rr, X86_INS_BLSI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSI64rm, X86_INS_BLSI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSI64rr, X86_INS_BLSI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSIC32rm, X86_INS_BLSIC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSIC32rr, X86_INS_BLSIC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSIC64rm, X86_INS_BLSIC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSIC64rr, X86_INS_BLSIC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSMSK32rm, X86_INS_BLSMSK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSMSK32rr, X86_INS_BLSMSK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSMSK64rm, X86_INS_BLSMSK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSMSK64rr, X86_INS_BLSMSK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSR32rm, X86_INS_BLSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSR32rr, X86_INS_BLSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSR64rm, X86_INS_BLSR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BLSR64rr, X86_INS_BLSR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_BOUNDS16rm, X86_INS_BOUND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_BOUNDS32rm, X86_INS_BOUND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_BSF16rm, X86_INS_BSF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSF16rr, X86_INS_BSF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSF32rm, X86_INS_BSF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSF32rr, X86_INS_BSF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSF64rm, X86_INS_BSF, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSF64rr, X86_INS_BSF, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSR16rm, X86_INS_BSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSR16rr, X86_INS_BSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSR32rm, X86_INS_BSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSR32rr, X86_INS_BSR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSR64rm, X86_INS_BSR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSR64rr, X86_INS_BSR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSWAP16r_BAD, X86_INS_BSWAP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSWAP32r, X86_INS_BSWAP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BSWAP64r, X86_INS_BSWAP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT16mi8, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT16mr, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT16ri8, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT16rr, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT32mi8, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT32mr, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT32ri8, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT32rr, X86_INS_BT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT64mi8, X86_INS_BT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT64mr, X86_INS_BT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT64ri8, X86_INS_BT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BT64rr, X86_INS_BT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC16mi8, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC16mr, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC16ri8, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC16rr, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC32mi8, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC32mr, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC32ri8, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC32rr, X86_INS_BTC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC64mi8, X86_INS_BTC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC64mr, X86_INS_BTC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC64ri8, X86_INS_BTC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTC64rr, X86_INS_BTC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR16mi8, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR16mr, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR16ri8, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR16rr, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR32mi8, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR32mr, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR32ri8, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR32rr, X86_INS_BTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR64mi8, X86_INS_BTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR64mr, X86_INS_BTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR64ri8, X86_INS_BTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTR64rr, X86_INS_BTR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS16mi8, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS16mr, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS16ri8, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS16rr, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS32mi8, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS32mr, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS32ri8, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS32rr, X86_INS_BTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS64mi8, X86_INS_BTS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS64mr, X86_INS_BTS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS64ri8, X86_INS_BTS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BTS64rr, X86_INS_BTS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_BZHI32rm, X86_INS_BZHI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_BZHI32rr, X86_INS_BZHI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_BZHI64rm, X86_INS_BZHI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_BZHI64rr, X86_INS_BZHI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL16m, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL16m_NT, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CALL16r, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL16r_NT, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CALL32m, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL32m_NT, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CALL32r, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL32r_NT, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CALL64m, X86_INS_CALL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL64m_NT, X86_INS_CALL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CALL64pcrel32, X86_INS_CALL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, X86_REG_RIP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL64r, X86_INS_CALL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_CALL64r_NT, X86_INS_CALL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CALLpcrel16, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, X86_REG_EIP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, 0 }, 0, 0 +#endif +}, + +{ + X86_CALLpcrel32, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, X86_REG_EIP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CBW, X86_INS_CBW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CDQ, X86_INS_CDQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CDQE, X86_INS_CDQE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { X86_REG_RAX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLAC, X86_INS_CLAC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_CLC, X86_INS_CLC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLD, X86_INS_CLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLDEMOTE, X86_INS_CLDEMOTE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLFLUSHOPT, X86_INS_CLFLUSHOPT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLGI, X86_INS_CLGI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_CLI, X86_INS_CLI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_CLRSSBSY, X86_INS_CLRSSBSY, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLTS, X86_INS_CLTS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLWB, X86_INS_CLWB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CLZEROr, X86_INS_CLZERO, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMC, X86_INS_CMC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVA16rm, X86_INS_CMOVA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVA16rr, X86_INS_CMOVA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVA32rm, X86_INS_CMOVA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVA32rr, X86_INS_CMOVA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVA64rm, X86_INS_CMOVA, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVA64rr, X86_INS_CMOVA, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVAE16rm, X86_INS_CMOVAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVAE16rr, X86_INS_CMOVAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVAE32rm, X86_INS_CMOVAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVAE32rr, X86_INS_CMOVAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVAE64rm, X86_INS_CMOVAE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVAE64rr, X86_INS_CMOVAE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB16rm, X86_INS_CMOVB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB16rr, X86_INS_CMOVB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB32rm, X86_INS_CMOVB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB32rr, X86_INS_CMOVB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB64rm, X86_INS_CMOVB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVB64rr, X86_INS_CMOVB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE16rm, X86_INS_CMOVBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE16rr, X86_INS_CMOVBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE32rm, X86_INS_CMOVBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE32rr, X86_INS_CMOVBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE64rm, X86_INS_CMOVBE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVBE64rr, X86_INS_CMOVBE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE16rm, X86_INS_CMOVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE16rr, X86_INS_CMOVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE32rm, X86_INS_CMOVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE32rr, X86_INS_CMOVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE64rm, X86_INS_CMOVE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVE64rr, X86_INS_CMOVE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVG16rm, X86_INS_CMOVG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVG16rr, X86_INS_CMOVG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVG32rm, X86_INS_CMOVG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVG32rr, X86_INS_CMOVG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVG64rm, X86_INS_CMOVG, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVG64rr, X86_INS_CMOVG, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVGE16rm, X86_INS_CMOVGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVGE16rr, X86_INS_CMOVGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVGE32rm, X86_INS_CMOVGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVGE32rr, X86_INS_CMOVGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVGE64rm, X86_INS_CMOVGE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVGE64rr, X86_INS_CMOVGE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVL16rm, X86_INS_CMOVL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVL16rr, X86_INS_CMOVL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVL32rm, X86_INS_CMOVL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVL32rr, X86_INS_CMOVL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVL64rm, X86_INS_CMOVL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVL64rr, X86_INS_CMOVL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVLE16rm, X86_INS_CMOVLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVLE16rr, X86_INS_CMOVLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVLE32rm, X86_INS_CMOVLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVLE32rr, X86_INS_CMOVLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVLE64rm, X86_INS_CMOVLE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVLE64rr, X86_INS_CMOVLE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE16rm, X86_INS_CMOVNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE16rr, X86_INS_CMOVNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE32rm, X86_INS_CMOVNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE32rr, X86_INS_CMOVNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE64rm, X86_INS_CMOVNE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNE64rr, X86_INS_CMOVNE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNO16rm, X86_INS_CMOVNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNO16rr, X86_INS_CMOVNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNO32rm, X86_INS_CMOVNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNO32rr, X86_INS_CMOVNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNO64rm, X86_INS_CMOVNO, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNO64rr, X86_INS_CMOVNO, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP16rm, X86_INS_CMOVNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP16rr, X86_INS_CMOVNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP32rm, X86_INS_CMOVNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP32rr, X86_INS_CMOVNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP64rm, X86_INS_CMOVNP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNP64rr, X86_INS_CMOVNP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNS16rm, X86_INS_CMOVNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNS16rr, X86_INS_CMOVNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNS32rm, X86_INS_CMOVNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNS32rr, X86_INS_CMOVNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNS64rm, X86_INS_CMOVNS, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVNS64rr, X86_INS_CMOVNS, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVO16rm, X86_INS_CMOVO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVO16rr, X86_INS_CMOVO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVO32rm, X86_INS_CMOVO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVO32rr, X86_INS_CMOVO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVO64rm, X86_INS_CMOVO, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVO64rr, X86_INS_CMOVO, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP16rm, X86_INS_CMOVP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP16rr, X86_INS_CMOVP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP32rm, X86_INS_CMOVP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP32rr, X86_INS_CMOVP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP64rm, X86_INS_CMOVP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVP64rr, X86_INS_CMOVP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVS16rm, X86_INS_CMOVS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVS16rr, X86_INS_CMOVS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVS32rm, X86_INS_CMOVS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVS32rr, X86_INS_CMOVS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVS64rm, X86_INS_CMOVS, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMOVS64rr, X86_INS_CMOVS, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16i16, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16mi, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16mi8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16mr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16ri, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16ri8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16rm, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16rr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP16rr_REV, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32i32, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32mi, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32mi8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32mr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32ri, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32ri8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32rm, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32rr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP32rr_REV, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64i32, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64mi32, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64mi8, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64mr, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64ri32, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64ri8, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64rm, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64rr, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP64rr_REV, X86_INS_CMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8i8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8mi, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8mi8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8mr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8ri, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8ri8, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8rm, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8rr, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMP8rr_REV, X86_INS_CMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSB, X86_INS_CMPSB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSL, X86_INS_CMPSD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSQ, X86_INS_CMPSQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPSW, X86_INS_CMPSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG16B, X86_INS_CMPXCHG16B, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG16rm, X86_INS_CMPXCHG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG16rr, X86_INS_CMPXCHG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG32rm, X86_INS_CMPXCHG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG32rr, X86_INS_CMPXCHG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG64rm, X86_INS_CMPXCHG, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG64rr, X86_INS_CMPXCHG, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG8B, X86_INS_CMPXCHG8B, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG8rm, X86_INS_CMPXCHG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CMPXCHG8rr, X86_INS_CMPXCHG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CPUID, X86_INS_CPUID, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_ECX, 0 }, { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CQO, X86_INS_CQO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CWD, X86_INS_CWD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_CWDE, X86_INS_CWDE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DAA, X86_INS_DAA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_DAS, X86_INS_DAS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_DATA16_PREFIX, X86_INS_DATA16, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC16m, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC16r, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC16r_alt, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_DEC32m, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC32r, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC32r_alt, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_DEC64m, X86_INS_DEC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC64r, X86_INS_DEC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC8m, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DEC8r, X86_INS_DEC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV16m, X86_INS_DIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV16r, X86_INS_DIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV32m, X86_INS_DIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV32r, X86_INS_DIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV64m, X86_INS_DIV, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV64r, X86_INS_DIV, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV8m, X86_INS_DIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_DIV8r, X86_INS_DIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ENDBR32, X86_INS_ENDBR32, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ENDBR64, X86_INS_ENDBR64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ENTER, X86_INS_ENTER, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_FARCALL16i, X86_INS_LCALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_FARCALL16m, X86_INS_LCALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, 0 }, 0, 0 +#endif +}, + +{ + X86_FARCALL32i, X86_INS_LCALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_FARCALL32m, X86_INS_CALL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, 0 }, 0, 0 +#endif +}, + +{ + X86_FARCALL64, X86_INS_LCALL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { 0 }, { X86_GRP_CALL, 0 }, 0, 0 +#endif +}, + +{ + X86_FARJMP16i, X86_INS_LJMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 +#endif +}, + +{ + X86_FARJMP16m, X86_INS_LJMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, + +{ + X86_FARJMP32i, X86_INS_LJMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 +#endif +}, + +{ + X86_FARJMP32m, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, + +{ + X86_FARJMP64, X86_INS_LJMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, + +{ + X86_FSETPM, X86_INS_FSETPM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_GETSEC, X86_INS_GETSEC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_HLT, X86_INS_HLT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV16m, X86_INS_IDIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV16r, X86_INS_IDIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV32m, X86_INS_IDIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV32r, X86_INS_IDIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV64m, X86_INS_IDIV, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV64r, X86_INS_IDIV, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV8m, X86_INS_IDIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IDIV8r, X86_INS_IDIV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16m, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16r, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16rm, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16rmi, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16rmi8, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16rr, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16rri, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL16rri8, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32m, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32r, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32rm, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32rmi, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32rmi8, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32rr, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32rri, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL32rri8, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64m, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64r, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64rm, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64rmi32, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64rmi8, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64rr, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64rri32, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL64rri8, X86_INS_IMUL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL8m, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IMUL8r, X86_INS_IMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IN16ri, X86_INS_IN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IN16rr, X86_INS_IN, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IN32ri, X86_INS_IN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IN32rr, X86_INS_IN, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IN8ri, X86_INS_IN, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_IN8rr, X86_INS_IN, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC16m, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC16r, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC16r_alt, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INC32m, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC32r, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC32r_alt, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INC64m, X86_INS_INC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC64r, X86_INS_INC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC8m, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INC8r, X86_INS_INC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INCSSPD, X86_INS_INCSSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INCSSPQ, X86_INS_INCSSPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INSB, X86_INS_INSB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INSL, X86_INS_INSD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INSW, X86_INS_INSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_INT, X86_INS_INT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 +#endif +}, + +{ + X86_INT1, X86_INS_INT1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_INT, 0 }, 0, 0 +#endif +}, + +{ + X86_INT3, X86_INS_INT3, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 +#endif +}, + +{ + X86_INTO, X86_INS_INTO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_INT, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVD, X86_INS_INVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVEPT32, X86_INS_INVEPT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVEPT64, X86_INS_INVEPT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_INVLPG, X86_INS_INVLPG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVLPGA32, X86_INS_INVLPGA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVLPGA64, X86_INS_INVLPGA, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_INVPCID32, X86_INS_INVPCID, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVPCID64, X86_INS_INVPCID, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_INVVPID32, X86_INS_INVVPID, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_INVVPID64, X86_INS_INVVPID, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_IRET16, X86_INS_IRET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 +#endif +}, + +{ + X86_IRET32, X86_INS_IRETD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 +#endif +}, + +{ + X86_IRET64, X86_INS_IRETQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_JAE_1, X86_INS_JAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JAE_2, X86_INS_JAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JAE_4, X86_INS_JAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JA_1, X86_INS_JA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JA_2, X86_INS_JA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JA_4, X86_INS_JA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JBE_1, X86_INS_JBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JBE_2, X86_INS_JBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JBE_4, X86_INS_JBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JB_1, X86_INS_JB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JB_2, X86_INS_JB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JB_4, X86_INS_JB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JCXZ, X86_INS_JCXZ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CX, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JECXZ, X86_INS_JECXZ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ECX, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JE_1, X86_INS_JE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JE_2, X86_INS_JE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JE_4, X86_INS_JE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JGE_1, X86_INS_JGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JGE_2, X86_INS_JGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JGE_4, X86_INS_JGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JG_1, X86_INS_JG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JG_2, X86_INS_JG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JG_4, X86_INS_JG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JLE_1, X86_INS_JLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JLE_2, X86_INS_JLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JLE_4, X86_INS_JLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JL_1, X86_INS_JL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JL_2, X86_INS_JL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JL_4, X86_INS_JL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JMP16m, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 +#endif +}, + +{ + X86_JMP16m_NT, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JMP16r, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 +#endif +}, + +{ + X86_JMP16r_NT, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JMP32m, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 +#endif +}, + +{ + X86_JMP32m_NT, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JMP32r, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 +#endif +}, + +{ + X86_JMP32r_NT, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JMP64m, X86_INS_JMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 1 +#endif +}, + +{ + X86_JMP64m_NT, X86_INS_JMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JMP64r, X86_INS_JMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 1 +#endif +}, + +{ + X86_JMP64r_NT, X86_INS_JMP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_JMP_1, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JMP_2, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JMP_4, X86_INS_JMP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JNE_1, X86_INS_JNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JNE_2, X86_INS_JNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JNE_4, X86_INS_JNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JNO_1, X86_INS_JNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JNO_2, X86_INS_JNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JNO_4, X86_INS_JNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JNP_1, X86_INS_JNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JNP_2, X86_INS_JNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JNP_4, X86_INS_JNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JNS_1, X86_INS_JNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JNS_2, X86_INS_JNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JNS_4, X86_INS_JNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JO_1, X86_INS_JO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JO_2, X86_INS_JO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JO_4, X86_INS_JO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JP_1, X86_INS_JP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JP_2, X86_INS_JP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JP_4, X86_INS_JP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JRCXZ, X86_INS_JRCXZ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RCX, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JS_1, X86_INS_JS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JS_2, X86_INS_JS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_JS_4, X86_INS_JS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, + +{ + X86_LAHF, X86_INS_LAHF, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_AH, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LAR16rm, X86_INS_LAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LAR16rr, X86_INS_LAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LAR32rm, X86_INS_LAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LAR32rr, X86_INS_LAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LAR64rm, X86_INS_LAR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LAR64rr, X86_INS_LAR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LDS16rm, X86_INS_LDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LDS32rm, X86_INS_LDS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LEA16r, X86_INS_LEA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LEA32r, X86_INS_LEA, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_LEA64_32r, X86_INS_LEA, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_LEA64r, X86_INS_LEA, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LEAVE, X86_INS_LEAVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EBP, X86_REG_ESP, 0 }, { X86_REG_EBP, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_LEAVE64, X86_INS_LEAVE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RBP, X86_REG_RSP, 0 }, { X86_REG_RBP, X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_LES16rm, X86_INS_LES, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LES32rm, X86_INS_LES, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LFS16rm, X86_INS_LFS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LFS32rm, X86_INS_LFS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LFS64rm, X86_INS_LFS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LGDT16m, X86_INS_LGDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_LGDT32m, X86_INS_LGDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_LGDT64m, X86_INS_LGDT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_LGS16rm, X86_INS_LGS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LGS32rm, X86_INS_LGS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LGS64rm, X86_INS_LGS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LIDT16m, X86_INS_LIDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_LIDT32m, X86_INS_LIDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_LIDT64m, X86_INS_LIDT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_LLDT16m, X86_INS_LLDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_LLDT16r, X86_INS_LLDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_LLWPCB, X86_INS_LLWPCB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LLWPCB64, X86_INS_LLWPCB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LMSW16m, X86_INS_LMSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_LMSW16r, X86_INS_LMSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_LOCK_PREFIX, X86_INS_LOCK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LODSB, X86_INS_LODSB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_AL, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LODSL, X86_INS_LODSD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EAX, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LODSQ, X86_INS_LODSQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_RAX, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LODSW, X86_INS_LODSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_AX, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LOOP, X86_INS_LOOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LOOPE, X86_INS_LOOPE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LOOPNE, X86_INS_LOOPNE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LRETIL, X86_INS_RETF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 +#endif +}, + +{ + X86_LRETIQ, X86_INS_RETFQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_LRETIW, X86_INS_RETF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 +#endif +}, + +{ + X86_LRETL, X86_INS_RETF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 +#endif +}, + +{ + X86_LRETQ, X86_INS_RETFQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_LRETW, X86_INS_RETF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 +#endif +}, + +{ + X86_LSL16rm, X86_INS_LSL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSL16rr, X86_INS_LSL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSL32rm, X86_INS_LSL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSL32rr, X86_INS_LSL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSL64rm, X86_INS_LSL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSL64rr, X86_INS_LSL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSS16rm, X86_INS_LSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSS32rm, X86_INS_LSS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LSS64rm, X86_INS_LSS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LTRm, X86_INS_LTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_LTRr, X86_INS_LTR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_LWPINS32rmi, X86_INS_LWPINS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPINS32rri, X86_INS_LWPINS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPINS64rmi, X86_INS_LWPINS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPINS64rri, X86_INS_LWPINS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPVAL32rmi, X86_INS_LWPVAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPVAL32rri, X86_INS_LWPVAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPVAL64rmi, X86_INS_LWPVAL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LWPVAL64rri, X86_INS_LWPVAL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LZCNT16rm, X86_INS_LZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LZCNT16rr, X86_INS_LZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LZCNT32rm, X86_INS_LZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LZCNT32rr, X86_INS_LZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LZCNT64rm, X86_INS_LZCNT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_LZCNT64rr, X86_INS_LZCNT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MONITORXrrr, X86_INS_MONITORX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MONTMUL, X86_INS_MONTMUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RSI, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_RSI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16ao16, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16ao32, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16ao64, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16mi, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16mr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16ms, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16o16a, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16o32a, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16o64a, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16ri, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16ri_alt, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16rm, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16rr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16rr_REV, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16rs, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16sm, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV16sr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32ao16, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32ao32, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32ao64, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32cr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32dr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32mi, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32mr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32o16a, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32o32a, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32o64a, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32rc, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32rd, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32ri, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32ri_alt, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32rm, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32rr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32rr_REV, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32rs, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV32sr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64ao32, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64ao64, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64cr, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64dr, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64mi32, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64mr, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64o32a, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64o64a, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64rc, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64rd, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64ri, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64ri32, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64rm, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64rr, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64rr_REV, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64rs, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV64sr, X86_INS_MOV, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8ao16, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8ao32, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8ao64, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8mi, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8mr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8mr_NOREX, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8o16a, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8o32a, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8o64a, X86_INS_MOVABS, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8ri, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8ri_alt, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8rm, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8rm_NOREX, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8rr, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8rr_NOREX, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOV8rr_REV, X86_INS_MOV, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVBE16mr, X86_INS_MOVBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVBE16rm, X86_INS_MOVBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVBE32mr, X86_INS_MOVBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVBE32rm, X86_INS_MOVBE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVBE64mr, X86_INS_MOVBE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVBE64rm, X86_INS_MOVBE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDIR64B16, X86_INS_MOVDIR64B, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDIR64B32, X86_INS_MOVDIR64B, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDIR64B64, X86_INS_MOVDIR64B, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDIRI32, X86_INS_MOVDIRI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVDIRI64, X86_INS_MOVDIRI, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSB, X86_INS_MOVSB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSL, X86_INS_MOVSD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSQ, X86_INS_MOVSQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSW, X86_INS_MOVSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX16rm16, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX16rm8, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX16rr16, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX16rr8, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX32rm16, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX32rm8, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX32rm8_NOREX, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX32rr16, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX32rr8, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX32rr8_NOREX, X86_INS_MOVSX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX64rm16, X86_INS_MOVSX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX64rm32, X86_INS_MOVSXD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX64rm8, X86_INS_MOVSX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX64rr16, X86_INS_MOVSX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX64rr32, X86_INS_MOVSXD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_MOVSX64rr8, X86_INS_MOVSX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX16rm16, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX16rm8, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX16rr16, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX16rr8, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX32rm16, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX32rm8, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX32rm8_NOREX, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX32rr16, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX32rr8, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX32rr8_NOREX, X86_INS_MOVZX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX64rm16, X86_INS_MOVZX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX64rm8, X86_INS_MOVZX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX64rr16, X86_INS_MOVZX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MOVZX64rr8, X86_INS_MOVZX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL16m, X86_INS_MUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL16r, X86_INS_MUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL32m, X86_INS_MUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL32r, X86_INS_MUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL64m, X86_INS_MUL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL64r, X86_INS_MUL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL8m, X86_INS_MUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MUL8r, X86_INS_MUL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_MULX32rm, X86_INS_MULX, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_MULX32rr, X86_INS_MULX, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_MULX64rm, X86_INS_MULX, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_MULX64rr, X86_INS_MULX, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_MWAITXrrr, X86_INS_MWAITX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG16m, X86_INS_NEG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG16r, X86_INS_NEG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG32m, X86_INS_NEG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG32r, X86_INS_NEG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG64m, X86_INS_NEG, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG64r, X86_INS_NEG, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG8m, X86_INS_NEG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NEG8r, X86_INS_NEG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16m4, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16m5, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16m6, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16m7, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16r4, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16r5, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16r6, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_16r7, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_m4, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_m5, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_m6, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_m7, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_r4, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_r5, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_r6, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP18_r7, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOP19rr, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPL, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPL_19, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPL_1d, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPL_1e, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPLr, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPQ, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPQr, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPW, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPW_19, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPW_1c, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPW_1d, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPW_1e, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOOPWr, X86_INS_NOP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT16m, X86_INS_NOT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT16r, X86_INS_NOT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT32m, X86_INS_NOT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT32r, X86_INS_NOT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT64m, X86_INS_NOT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT64r, X86_INS_NOT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT8m, X86_INS_NOT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_NOT8r, X86_INS_NOT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16i16, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16mi, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16mi8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16mr, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16ri, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16ri8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16rm, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16rr, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR16rr_REV, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32i32, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32mi, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32mi8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32mr, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32ri, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32ri8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32rm, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32rr, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR32rr_REV, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64i32, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64mi32, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64mi8, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64mr, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64ri32, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64ri8, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64rm, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64rr, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR64rr_REV, X86_INS_OR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8i8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8mi, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8mi8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_OR8mr, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8ri, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8ri8, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_OR8rm, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8rr, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OR8rr_REV, X86_INS_OR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUT16ir, X86_INS_OUT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUT16rr, X86_INS_OUT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUT32ir, X86_INS_OUT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUT32rr, X86_INS_OUT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUT8ir, X86_INS_OUT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUT8rr, X86_INS_OUT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUTSB, X86_INS_OUTSB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUTSL, X86_INS_OUTSD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_OUTSW, X86_INS_OUTSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_DX, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_ESI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PCONFIG, X86_INS_PCONFIG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PDEP32rm, X86_INS_PDEP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PDEP32rr, X86_INS_PDEP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PDEP64rm, X86_INS_PDEP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PDEP64rr, X86_INS_PDEP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXT32rm, X86_INS_PEXT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXT32rr, X86_INS_PEXT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXT64rm, X86_INS_PEXT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_PEXT64rr, X86_INS_PEXT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_POP16r, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POP16rmm, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POP16rmr, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POP32r, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POP32rmm, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POP32rmr, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POP64r, X86_INS_POP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_POP64rmm, X86_INS_POP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_POP64rmr, X86_INS_POP, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_POPA16, X86_INS_POPAW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPA32, X86_INS_POPAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPDS16, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPDS32, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPES16, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPES32, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPF16, X86_INS_POPF, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_POPF32, X86_INS_POPFD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPF64, X86_INS_POPFQ, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_POPFS16, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPFS32, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPFS64, X86_INS_POP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_POPGS16, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPGS32, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPGS64, X86_INS_POP, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_POPSS16, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_POPSS32, X86_INS_POP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PTWRITE64m, X86_INS_PTWRITE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PTWRITE64r, X86_INS_PTWRITE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PTWRITEm, X86_INS_PTWRITE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PTWRITEr, X86_INS_PTWRITE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH16i8, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH16r, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH16rmm, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH16rmr, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH32i8, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH32r, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH32rmm, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH32rmr, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH64i32, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH64i8, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH64r, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH64rmm, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSH64rmr, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHA16, X86_INS_PUSHAW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHA32, X86_INS_PUSHAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHCS16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHCS32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHDS16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHDS32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHES16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHES32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHF16, X86_INS_PUSHF, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHF32, X86_INS_PUSHFD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHF64, X86_INS_PUSHFQ, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RSP, X86_REG_EFLAGS, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHFS16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHFS32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHFS64, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHGS16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHGS32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHGS64, X86_INS_PUSH, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHSS16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHSS32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHi16, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_PUSHi32, X86_INS_PUSH, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_RCL16m1, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL16mCL, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL16mi, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL16r1, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL16rCL, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL16ri, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL32m1, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL32mCL, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL32mi, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL32r1, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL32rCL, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL32ri, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL64m1, X86_INS_RCL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL64mCL, X86_INS_RCL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL64mi, X86_INS_RCL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL64r1, X86_INS_RCL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL64rCL, X86_INS_RCL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL64ri, X86_INS_RCL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL8m1, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL8mCL, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL8mi, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL8r1, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL8rCL, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCL8ri, X86_INS_RCL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR16m1, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR16mCL, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR16mi, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR16r1, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR16rCL, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR16ri, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR32m1, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR32mCL, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR32mi, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR32r1, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR32rCL, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR32ri, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR64m1, X86_INS_RCR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR64mCL, X86_INS_RCR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR64mi, X86_INS_RCR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR64r1, X86_INS_RCR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR64rCL, X86_INS_RCR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR64ri, X86_INS_RCR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR8m1, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR8mCL, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR8mi, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR8r1, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR8rCL, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RCR8ri, X86_INS_RCR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDFSBASE, X86_INS_RDFSBASE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_RDFSBASE64, X86_INS_RDFSBASE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_RDGSBASE, X86_INS_RDGSBASE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_RDGSBASE64, X86_INS_RDGSBASE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_RDMSR, X86_INS_RDMSR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ECX, 0 }, { X86_REG_EAX, X86_REG_EDX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDPID32, X86_INS_RDPID, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDPID64, X86_INS_RDPID, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDPKRUr, X86_INS_RDPKRU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDPMC, X86_INS_RDPMC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ECX, 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_RDRAND16r, X86_INS_RDRAND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDRAND32r, X86_INS_RDRAND, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDRAND64r, X86_INS_RDRAND, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDSEED16r, X86_INS_RDSEED, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDSEED32r, X86_INS_RDSEED, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDSEED64r, X86_INS_RDSEED, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDSSPD, X86_INS_RDSSPD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDSSPQ, X86_INS_RDSSPQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDTSC, X86_INS_RDTSC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RDTSCP, X86_INS_RDTSCP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_RAX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_REPNE_PREFIX, X86_INS_REPNE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_REP_PREFIX, X86_INS_REP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RETIL, X86_INS_RET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_RETIQ, X86_INS_RET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_RETIW, X86_INS_RET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 +#endif +}, + +{ + X86_RETL, X86_INS_RET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_RETQ, X86_INS_RET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_RETW, X86_INS_RET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 +#endif +}, + +{ + X86_REX64_PREFIX, X86_INS_REX64, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL16m1, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL16mCL, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL16mi, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL16r1, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL16rCL, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL16ri, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL32m1, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL32mCL, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL32mi, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL32r1, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL32rCL, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL32ri, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL64m1, X86_INS_ROL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL64mCL, X86_INS_ROL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL64mi, X86_INS_ROL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL64r1, X86_INS_ROL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL64rCL, X86_INS_ROL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL64ri, X86_INS_ROL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL8m1, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL8mCL, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL8mi, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL8r1, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL8rCL, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROL8ri, X86_INS_ROL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR16m1, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR16mCL, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR16mi, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR16r1, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR16rCL, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR16ri, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR32m1, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR32mCL, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR32mi, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR32r1, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR32rCL, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR32ri, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR64m1, X86_INS_ROR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR64mCL, X86_INS_ROR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR64mi, X86_INS_ROR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR64r1, X86_INS_ROR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR64rCL, X86_INS_ROR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR64ri, X86_INS_ROR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR8m1, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR8mCL, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR8mi, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR8r1, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR8rCL, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_ROR8ri, X86_INS_ROR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_RORX32mi, X86_INS_RORX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_RORX32ri, X86_INS_RORX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_RORX64mi, X86_INS_RORX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_RORX64ri, X86_INS_RORX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_RSM, X86_INS_RSM, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_RSTORSSP, X86_INS_RSTORSSP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAHF, X86_INS_SAHF, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AH, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL16m1, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL16mCL, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL16mi, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL16r1, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL16rCL, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL16ri, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL32m1, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL32mCL, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL32mi, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL32r1, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL32rCL, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL32ri, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL64m1, X86_INS_SAL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL64mCL, X86_INS_SAL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL64mi, X86_INS_SAL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL64r1, X86_INS_SAL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL64rCL, X86_INS_SAL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL64ri, X86_INS_SAL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL8m1, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL8mCL, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL8mi, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL8r1, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL8rCL, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAL8ri, X86_INS_SAL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SALC, X86_INS_SALC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_AL, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SAR16m1, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR16mCL, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR16mi, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR16r1, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR16rCL, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR16ri, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR32m1, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR32mCL, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR32mi, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR32r1, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR32rCL, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR32ri, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR64m1, X86_INS_SAR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR64mCL, X86_INS_SAR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR64mi, X86_INS_SAR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR64r1, X86_INS_SAR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR64rCL, X86_INS_SAR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR64ri, X86_INS_SAR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR8m1, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR8mCL, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR8mi, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR8r1, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR8rCL, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SAR8ri, X86_INS_SAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SARX32rm, X86_INS_SARX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SARX32rr, X86_INS_SARX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SARX64rm, X86_INS_SARX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SARX64rr, X86_INS_SARX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SAVEPREVSSP, X86_INS_SAVEPREVSSP, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16i16, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16mi, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16mi8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16mr, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16ri, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16ri8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16rm, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16rr, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB16rr_REV, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32i32, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32mi, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32mi8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32mr, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32ri, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32ri8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32rm, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32rr, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB32rr_REV, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64i32, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64mi32, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64mi8, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64mr, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64ri32, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64ri8, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64rm, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64rr, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB64rr_REV, X86_INS_SBB, 1, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8i8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8mi, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8mi8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8mr, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8ri, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8ri8, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8rm, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8rr, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SBB8rr_REV, X86_INS_SBB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SCASB, X86_INS_SCASB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SCASL, X86_INS_SCASD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SCASQ, X86_INS_SCASQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SCASW, X86_INS_SCASW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETAEm, X86_INS_SETAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETAEr, X86_INS_SETAE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETAm, X86_INS_SETA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETAr, X86_INS_SETA, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETBEm, X86_INS_SETBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETBEr, X86_INS_SETBE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETBm, X86_INS_SETB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETBr, X86_INS_SETB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETEm, X86_INS_SETE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETEr, X86_INS_SETE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETGEm, X86_INS_SETGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETGEr, X86_INS_SETGE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETGm, X86_INS_SETG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETGr, X86_INS_SETG, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETLEm, X86_INS_SETLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETLEr, X86_INS_SETLE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETLm, X86_INS_SETL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETLr, X86_INS_SETL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNEm, X86_INS_SETNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNEr, X86_INS_SETNE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNOm, X86_INS_SETNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNOr, X86_INS_SETNO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNPm, X86_INS_SETNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNPr, X86_INS_SETNP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNSm, X86_INS_SETNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETNSr, X86_INS_SETNS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETOm, X86_INS_SETO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETOr, X86_INS_SETO, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETPm, X86_INS_SETP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETPr, X86_INS_SETP, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETSSBSY, X86_INS_SETSSBSY, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETSm, X86_INS_SETS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SETSr, X86_INS_SETS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SGDT16m, X86_INS_SGDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SGDT32m, X86_INS_SGDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SGDT64m, X86_INS_SGDT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_SHL16m1, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL16mCL, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL16mi, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL16r1, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL16rCL, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL16ri, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL32m1, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL32mCL, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL32mi, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL32r1, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL32rCL, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL32ri, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL64m1, X86_INS_SHL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL64mCL, X86_INS_SHL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL64mi, X86_INS_SHL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL64r1, X86_INS_SHL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL64rCL, X86_INS_SHL, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL64ri, X86_INS_SHL, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL8m1, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL8mCL, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL8mi, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL8r1, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL8rCL, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHL8ri, X86_INS_SHL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD16mrCL, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD16mri8, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD16rrCL, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD16rri8, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD32mrCL, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD32mri8, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD32rrCL, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD32rri8, X86_INS_SHLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD64mrCL, X86_INS_SHLD, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD64mri8, X86_INS_SHLD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD64rrCL, X86_INS_SHLD, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLD64rri8, X86_INS_SHLD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHLX32rm, X86_INS_SHLX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHLX32rr, X86_INS_SHLX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHLX64rm, X86_INS_SHLX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHLX64rr, X86_INS_SHLX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHR16m1, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR16mCL, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR16mi, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR16r1, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR16rCL, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR16ri, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR32m1, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR32mCL, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR32mi, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR32r1, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR32rCL, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR32ri, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR64m1, X86_INS_SHR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR64mCL, X86_INS_SHR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR64mi, X86_INS_SHR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR64r1, X86_INS_SHR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR64rCL, X86_INS_SHR, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR64ri, X86_INS_SHR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR8m1, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR8mCL, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR8mi, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR8r1, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR8rCL, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHR8ri, X86_INS_SHR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD16mrCL, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD16mri8, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD16rrCL, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD16rri8, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD32mrCL, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD32mri8, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD32rrCL, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD32rri8, X86_INS_SHRD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD64mrCL, X86_INS_SHRD, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD64mri8, X86_INS_SHRD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD64rrCL, X86_INS_SHRD, 1, +#ifndef CAPSTONE_DIET + { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRD64rri8, X86_INS_SHRD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SHRX32rm, X86_INS_SHRX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHRX32rr, X86_INS_SHRX, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHRX64rm, X86_INS_SHRX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SHRX64rr, X86_INS_SHRX, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 +#endif +}, + +{ + X86_SIDT16m, X86_INS_SIDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SIDT32m, X86_INS_SIDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SIDT64m, X86_INS_SIDT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_SKINIT, X86_INS_SKINIT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_SLDT16m, X86_INS_SLDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SLDT16r, X86_INS_SLDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SLDT32r, X86_INS_SLDT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SLDT64r, X86_INS_SLDT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SLWPCB, X86_INS_SLWPCB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SLWPCB64, X86_INS_SLWPCB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SMSW16m, X86_INS_SMSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SMSW16r, X86_INS_SMSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SMSW32r, X86_INS_SMSW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SMSW64r, X86_INS_SMSW, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STAC, X86_INS_STAC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_STC, X86_INS_STC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STD, X86_INS_STD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STGI, X86_INS_STGI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_STI, X86_INS_STI, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_STOSB, X86_INS_STOSB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AL, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STOSL, X86_INS_STOSD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STOSQ, X86_INS_STOSQ, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RCX, X86_REG_RDI, X86_REG_EFLAGS, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STOSW, X86_INS_STOSW, 0, +#ifndef CAPSTONE_DIET + { X86_REG_AX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_STR16r, X86_INS_STR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_STR32r, X86_INS_STR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_STR64r, X86_INS_STR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_STRm, X86_INS_STR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16i16, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16mi, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16mi8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16mr, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16ri, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16ri8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16rm, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16rr, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB16rr_REV, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32i32, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32mi, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32mi8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32mr, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32ri, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32ri8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32rm, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32rr, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB32rr_REV, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64i32, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64mi32, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64mi8, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64mr, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64ri32, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64ri8, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64rm, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64rr, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB64rr_REV, X86_INS_SUB, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8i8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8mi, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8mi8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8mr, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8ri, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8ri8, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8rm, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8rr, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SUB8rr_REV, X86_INS_SUB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_SWAPGS, X86_INS_SWAPGS, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_SYSCALL, X86_INS_SYSCALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 +#endif +}, + +{ + X86_SYSENTER, X86_INS_SYSENTER, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 +#endif +}, + +{ + X86_SYSEXIT, X86_INS_SYSEXIT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 +#endif +}, + +{ + X86_SYSEXIT64, X86_INS_SYSEXITQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_SYSRET, X86_INS_SYSRET, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 +#endif +}, + +{ + X86_SYSRET64, X86_INS_SYSRETQ, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_IRET, X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_T1MSKC32rm, X86_INS_T1MSKC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_T1MSKC32rr, X86_INS_T1MSKC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_T1MSKC64rm, X86_INS_T1MSKC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_T1MSKC64rr, X86_INS_T1MSKC, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16i16, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16mi, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16mi_alt, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16mr, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16ri, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16ri_alt, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST16rr, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32i32, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32mi, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32mi_alt, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32mr, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32ri, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32ri_alt, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST32rr, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64i32, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64mi32, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64mi32_alt, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64mr, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64ri32, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64ri32_alt, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST64rr, X86_INS_TEST, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8i8, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8mi, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8mi_alt, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8mr, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8ri, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8ri_alt, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TEST8rr, X86_INS_TEST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TPAUSE, X86_INS_TPAUSE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_TZCNT16rm, X86_INS_TZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_TZCNT16rr, X86_INS_TZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_TZCNT32rm, X86_INS_TZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_TZCNT32rr, X86_INS_TZCNT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_TZCNT64rm, X86_INS_TZCNT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_TZCNT64rr, X86_INS_TZCNT, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 +#endif +}, + +{ + X86_TZMSK32rm, X86_INS_TZMSK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_TZMSK32rr, X86_INS_TZMSK, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_TZMSK64rm, X86_INS_TZMSK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_TZMSK64rr, X86_INS_TZMSK, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 +#endif +}, + +{ + X86_UD0, X86_INS_UD0, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UD1, X86_INS_UD1, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UD2, X86_INS_UD2, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UMONITOR16, X86_INS_UMONITOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UMONITOR32, X86_INS_UMONITOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UMONITOR64, X86_INS_UMONITOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_UMWAIT, X86_INS_UMWAIT, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VERRm, X86_INS_VERR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VERRr, X86_INS_VERR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VERWm, X86_INS_VERW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VERWr, X86_INS_VERW, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMCALL, X86_INS_VMCALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMCLEARm, X86_INS_VMCLEAR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMFUNC, X86_INS_VMFUNC, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMLAUNCH, X86_INS_VMLAUNCH, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMLOAD32, X86_INS_VMLOAD, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMLOAD64, X86_INS_VMLOAD, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMMCALL, X86_INS_VMMCALL, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMPTRLDm, X86_INS_VMPTRLD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMPTRSTm, X86_INS_VMPTRST, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMREAD32mr, X86_INS_VMREAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMREAD32rr, X86_INS_VMREAD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMREAD64mr, X86_INS_VMREAD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_VMREAD64rr, X86_INS_VMREAD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMRESUME, X86_INS_VMRESUME, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMRUN32, X86_INS_VMRUN, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMRUN64, X86_INS_VMRUN, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMSAVE32, X86_INS_VMSAVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMSAVE64, X86_INS_VMSAVE, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMWRITE32rm, X86_INS_VMWRITE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMWRITE32rr, X86_INS_VMWRITE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_VMWRITE64rm, X86_INS_VMWRITE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMWRITE64rr, X86_INS_VMWRITE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_VMXOFF, X86_INS_VMXOFF, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_VMXON, X86_INS_VMXON, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 +#endif +}, + +{ + X86_WBINVD, X86_INS_WBINVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_WBNOINVD, X86_INS_WBNOINVD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_WRFSBASE, X86_INS_WRFSBASE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_WRFSBASE64, X86_INS_WRFSBASE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_WRGSBASE, X86_INS_WRGSBASE, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_WRGSBASE64, X86_INS_WRGSBASE, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_WRMSR, X86_INS_WRMSR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_WRPKRUr, X86_INS_WRPKRU, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_WRSSD, X86_INS_WRSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_WRSSQ, X86_INS_WRSSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_WRUSSD, X86_INS_WRUSSD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_WRUSSQ, X86_INS_WRUSSQ, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD16rm, X86_INS_XADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD16rr, X86_INS_XADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD32rm, X86_INS_XADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD32rr, X86_INS_XADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD64rm, X86_INS_XADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD64rr, X86_INS_XADD, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD8rm, X86_INS_XADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XADD8rr, X86_INS_XADD, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG16ar, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG16rm, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG16rr, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG32ar, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG32rm, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG32rr, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG64ar, X86_INS_XCHG, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG64rm, X86_INS_XCHG, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG64rr, X86_INS_XCHG, 1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG8rm, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCHG8rr, X86_INS_XCHG, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCRYPTCBC, X86_INS_XCRYPTCBC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCRYPTCFB, X86_INS_XCRYPTCFB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCRYPTCTR, X86_INS_XCRYPTCTR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCRYPTECB, X86_INS_XCRYPTECB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XCRYPTOFB, X86_INS_XCRYPTOFB, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XGETBV, X86_INS_XGETBV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_ECX, 0 }, { X86_REG_EDX, X86_REG_EAX, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XLAT, X86_INS_XLATB, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16i16, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16mi, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16mi8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16mr, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16ri, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16ri8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16rm, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16rr, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR16rr_REV, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32i32, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32mi, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32mi8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32mr, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32ri, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32ri8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32rm, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32rr, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR32rr_REV, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64i32, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64mi32, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64mi8, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64mr, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64ri32, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64ri8, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64rm, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64rr, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR64rr_REV, X86_INS_XOR, 1, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8i8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8mi, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8mi8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8mr, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8ri, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8ri8, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8rm, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8rr, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XOR8rr_REV, X86_INS_XOR, 0, +#ifndef CAPSTONE_DIET + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XRSTOR, X86_INS_XRSTOR, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XRSTOR64, X86_INS_XRSTOR64, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_XRSTORS, X86_INS_XRSTORS, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_XRSTORS64, X86_INS_XRSTORS64, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVE, X86_INS_XSAVE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVE64, X86_INS_XSAVE64, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVEC, X86_INS_XSAVEC, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVEC64, X86_INS_XSAVEC64, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVEOPT, X86_INS_XSAVEOPT, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVEOPT64, X86_INS_XSAVEOPT64, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVES, X86_INS_XSAVES, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XSAVES64, X86_INS_XSAVES64, 1, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 +#endif +}, + +{ + X86_XSETBV, X86_INS_XSETBV, 0, +#ifndef CAPSTONE_DIET + { X86_REG_EDX, X86_REG_EAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + X86_XSHA1, X86_INS_XSHA1, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XSHA256, X86_INS_XSHA256, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + X86_XSTORE, X86_INS_XSTORE, 0, +#ifndef CAPSTONE_DIET + { X86_REG_RDX, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RDI, 0 }, { 0 }, 0, 0 +#endif +}, diff --git a/thirdparty/capstone/arch/X86/X86MappingReg.inc b/thirdparty/capstone/arch/X86/X86MappingReg.inc new file mode 100644 index 0000000..8f5dde1 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86MappingReg.inc @@ -0,0 +1,280 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +{ X86_AH, X86_REG_AH }, +{ X86_AL, X86_REG_AL }, +{ X86_AX, X86_REG_AX }, +{ X86_BH, X86_REG_BH }, +{ X86_BL, X86_REG_BL }, +{ X86_BP, X86_REG_BP }, +{ X86_BPH, 0 }, +{ X86_BPL, X86_REG_BPL }, +{ X86_BX, X86_REG_BX }, +{ X86_CH, X86_REG_CH }, +{ X86_CL, X86_REG_CL }, +{ X86_CS, X86_REG_CS }, +{ X86_CX, X86_REG_CX }, +{ X86_DF, 0 }, +{ X86_DH, X86_REG_DH }, +{ X86_DI, X86_REG_DI }, +{ X86_DIH, 0 }, +{ X86_DIL, X86_REG_DIL }, +{ X86_DL, X86_REG_DL }, +{ X86_DS, X86_REG_DS }, +{ X86_DX, X86_REG_DX }, +{ X86_EAX, X86_REG_EAX }, +{ X86_EBP, X86_REG_EBP }, +{ X86_EBX, X86_REG_EBX }, +{ X86_ECX, X86_REG_ECX }, +{ X86_EDI, X86_REG_EDI }, +{ X86_EDX, X86_REG_EDX }, +{ X86_EFLAGS, X86_REG_EFLAGS }, +{ X86_EIP, X86_REG_EIP }, +{ X86_EIZ, X86_REG_EIZ }, +{ X86_ES, X86_REG_ES }, +{ X86_ESI, X86_REG_ESI }, +{ X86_ESP, X86_REG_ESP }, +{ X86_FPSW, X86_REG_FPSW }, +{ X86_FS, X86_REG_FS }, +{ X86_GS, X86_REG_GS }, +{ X86_HAX, 0 }, +{ X86_HBP, 0 }, +{ X86_HBX, 0 }, +{ X86_HCX, 0 }, +{ X86_HDI, 0 }, +{ X86_HDX, 0 }, +{ X86_HIP, 0 }, +{ X86_HSI, 0 }, +{ X86_HSP, 0 }, +{ X86_IP, X86_REG_IP }, +{ X86_RAX, X86_REG_RAX }, +{ X86_RBP, X86_REG_RBP }, +{ X86_RBX, X86_REG_RBX }, +{ X86_RCX, X86_REG_RCX }, +{ X86_RDI, X86_REG_RDI }, +{ X86_RDX, X86_REG_RDX }, +{ X86_RIP, X86_REG_RIP }, +{ X86_RIZ, X86_REG_RIZ }, +{ X86_RSI, X86_REG_RSI }, +{ X86_RSP, X86_REG_RSP }, +{ X86_SI, X86_REG_SI }, +{ X86_SIH, 0 }, +{ X86_SIL, X86_REG_SIL }, +{ X86_SP, X86_REG_SP }, +{ X86_SPH, 0 }, +{ X86_SPL, X86_REG_SPL }, +{ X86_SS, X86_REG_SS }, +{ X86_SSP, 0 }, +{ X86_BND0, X86_REG_BND0 }, +{ X86_BND1, X86_REG_BND1 }, +{ X86_BND2, X86_REG_BND2 }, +{ X86_BND3, X86_REG_BND3 }, +{ X86_CR0, X86_REG_CR0 }, +{ X86_CR1, X86_REG_CR1 }, +{ X86_CR2, X86_REG_CR2 }, +{ X86_CR3, X86_REG_CR3 }, +{ X86_CR4, X86_REG_CR4 }, +{ X86_CR5, X86_REG_CR5 }, +{ X86_CR6, X86_REG_CR6 }, +{ X86_CR7, X86_REG_CR7 }, +{ X86_CR8, X86_REG_CR8 }, +{ X86_CR9, X86_REG_CR9 }, +{ X86_CR10, X86_REG_CR10 }, +{ X86_CR11, X86_REG_CR11 }, +{ X86_CR12, X86_REG_CR12 }, +{ X86_CR13, X86_REG_CR13 }, +{ X86_CR14, X86_REG_CR14 }, +{ X86_CR15, X86_REG_CR15 }, +{ X86_DR0, X86_REG_DR0 }, +{ X86_DR1, X86_REG_DR1 }, +{ X86_DR2, X86_REG_DR2 }, +{ X86_DR3, X86_REG_DR3 }, +{ X86_DR4, X86_REG_DR4 }, +{ X86_DR5, X86_REG_DR5 }, +{ X86_DR6, X86_REG_DR6 }, +{ X86_DR7, X86_REG_DR7 }, +{ X86_DR8, X86_REG_DR8 }, +{ X86_DR9, X86_REG_DR9 }, +{ X86_DR10, X86_REG_DR10 }, +{ X86_DR11, X86_REG_DR11 }, +{ X86_DR12, X86_REG_DR12 }, +{ X86_DR13, X86_REG_DR13 }, +{ X86_DR14, X86_REG_DR14 }, +{ X86_DR15, X86_REG_DR15 }, +{ X86_FP0, X86_REG_FP0 }, +{ X86_FP1, X86_REG_FP1 }, +{ X86_FP2, X86_REG_FP2 }, +{ X86_FP3, X86_REG_FP3 }, +{ X86_FP4, X86_REG_FP4 }, +{ X86_FP5, X86_REG_FP5 }, +{ X86_FP6, X86_REG_FP6 }, +{ X86_FP7, X86_REG_FP7 }, +{ X86_K0, X86_REG_K0 }, +{ X86_K1, X86_REG_K1 }, +{ X86_K2, X86_REG_K2 }, +{ X86_K3, X86_REG_K3 }, +{ X86_K4, X86_REG_K4 }, +{ X86_K5, X86_REG_K5 }, +{ X86_K6, X86_REG_K6 }, +{ X86_K7, X86_REG_K7 }, +{ X86_MM0, X86_REG_MM0 }, +{ X86_MM1, X86_REG_MM1 }, +{ X86_MM2, X86_REG_MM2 }, +{ X86_MM3, X86_REG_MM3 }, +{ X86_MM4, X86_REG_MM4 }, +{ X86_MM5, X86_REG_MM5 }, +{ X86_MM6, X86_REG_MM6 }, +{ X86_MM7, X86_REG_MM7 }, +{ X86_R8, X86_REG_R8 }, +{ X86_R9, X86_REG_R9 }, +{ X86_R10, X86_REG_R10 }, +{ X86_R11, X86_REG_R11 }, +{ X86_R12, X86_REG_R12 }, +{ X86_R13, X86_REG_R13 }, +{ X86_R14, X86_REG_R14 }, +{ X86_R15, X86_REG_R15 }, +{ X86_ST0, X86_REG_ST0 }, +{ X86_ST1, X86_REG_ST1 }, +{ X86_ST2, X86_REG_ST2 }, +{ X86_ST3, X86_REG_ST3 }, +{ X86_ST4, X86_REG_ST4 }, +{ X86_ST5, X86_REG_ST5 }, +{ X86_ST6, X86_REG_ST6 }, +{ X86_ST7, X86_REG_ST7 }, +{ X86_XMM0, X86_REG_XMM0 }, +{ X86_XMM1, X86_REG_XMM1 }, +{ X86_XMM2, X86_REG_XMM2 }, +{ X86_XMM3, X86_REG_XMM3 }, +{ X86_XMM4, X86_REG_XMM4 }, +{ X86_XMM5, X86_REG_XMM5 }, +{ X86_XMM6, X86_REG_XMM6 }, +{ X86_XMM7, X86_REG_XMM7 }, +{ X86_XMM8, X86_REG_XMM8 }, +{ X86_XMM9, X86_REG_XMM9 }, +{ X86_XMM10, X86_REG_XMM10 }, +{ X86_XMM11, X86_REG_XMM11 }, +{ X86_XMM12, X86_REG_XMM12 }, +{ X86_XMM13, X86_REG_XMM13 }, +{ X86_XMM14, X86_REG_XMM14 }, +{ X86_XMM15, X86_REG_XMM15 }, +{ X86_XMM16, X86_REG_XMM16 }, +{ X86_XMM17, X86_REG_XMM17 }, +{ X86_XMM18, X86_REG_XMM18 }, +{ X86_XMM19, X86_REG_XMM19 }, +{ X86_XMM20, X86_REG_XMM20 }, +{ X86_XMM21, X86_REG_XMM21 }, +{ X86_XMM22, X86_REG_XMM22 }, +{ X86_XMM23, X86_REG_XMM23 }, +{ X86_XMM24, X86_REG_XMM24 }, +{ X86_XMM25, X86_REG_XMM25 }, +{ X86_XMM26, X86_REG_XMM26 }, +{ X86_XMM27, X86_REG_XMM27 }, +{ X86_XMM28, X86_REG_XMM28 }, +{ X86_XMM29, X86_REG_XMM29 }, +{ X86_XMM30, X86_REG_XMM30 }, +{ X86_XMM31, X86_REG_XMM31 }, +{ X86_YMM0, X86_REG_YMM0 }, +{ X86_YMM1, X86_REG_YMM1 }, +{ X86_YMM2, X86_REG_YMM2 }, +{ X86_YMM3, X86_REG_YMM3 }, +{ X86_YMM4, X86_REG_YMM4 }, +{ X86_YMM5, X86_REG_YMM5 }, +{ X86_YMM6, X86_REG_YMM6 }, +{ X86_YMM7, X86_REG_YMM7 }, +{ X86_YMM8, X86_REG_YMM8 }, +{ X86_YMM9, X86_REG_YMM9 }, +{ X86_YMM10, X86_REG_YMM10 }, +{ X86_YMM11, X86_REG_YMM11 }, +{ X86_YMM12, X86_REG_YMM12 }, +{ X86_YMM13, X86_REG_YMM13 }, +{ X86_YMM14, X86_REG_YMM14 }, +{ X86_YMM15, X86_REG_YMM15 }, +{ X86_YMM16, X86_REG_YMM16 }, +{ X86_YMM17, X86_REG_YMM17 }, +{ X86_YMM18, X86_REG_YMM18 }, +{ X86_YMM19, X86_REG_YMM19 }, +{ X86_YMM20, X86_REG_YMM20 }, +{ X86_YMM21, X86_REG_YMM21 }, +{ X86_YMM22, X86_REG_YMM22 }, +{ X86_YMM23, X86_REG_YMM23 }, +{ X86_YMM24, X86_REG_YMM24 }, +{ X86_YMM25, X86_REG_YMM25 }, +{ X86_YMM26, X86_REG_YMM26 }, +{ X86_YMM27, X86_REG_YMM27 }, +{ X86_YMM28, X86_REG_YMM28 }, +{ X86_YMM29, X86_REG_YMM29 }, +{ X86_YMM30, X86_REG_YMM30 }, +{ X86_YMM31, X86_REG_YMM31 }, +{ X86_ZMM0, X86_REG_ZMM0 }, +{ X86_ZMM1, X86_REG_ZMM1 }, +{ X86_ZMM2, X86_REG_ZMM2 }, +{ X86_ZMM3, X86_REG_ZMM3 }, +{ X86_ZMM4, X86_REG_ZMM4 }, +{ X86_ZMM5, X86_REG_ZMM5 }, +{ X86_ZMM6, X86_REG_ZMM6 }, +{ X86_ZMM7, X86_REG_ZMM7 }, +{ X86_ZMM8, X86_REG_ZMM8 }, +{ X86_ZMM9, X86_REG_ZMM9 }, +{ X86_ZMM10, X86_REG_ZMM10 }, +{ X86_ZMM11, X86_REG_ZMM11 }, +{ X86_ZMM12, X86_REG_ZMM12 }, +{ X86_ZMM13, X86_REG_ZMM13 }, +{ X86_ZMM14, X86_REG_ZMM14 }, +{ X86_ZMM15, X86_REG_ZMM15 }, +{ X86_ZMM16, X86_REG_ZMM16 }, +{ X86_ZMM17, X86_REG_ZMM17 }, +{ X86_ZMM18, X86_REG_ZMM18 }, +{ X86_ZMM19, X86_REG_ZMM19 }, +{ X86_ZMM20, X86_REG_ZMM20 }, +{ X86_ZMM21, X86_REG_ZMM21 }, +{ X86_ZMM22, X86_REG_ZMM22 }, +{ X86_ZMM23, X86_REG_ZMM23 }, +{ X86_ZMM24, X86_REG_ZMM24 }, +{ X86_ZMM25, X86_REG_ZMM25 }, +{ X86_ZMM26, X86_REG_ZMM26 }, +{ X86_ZMM27, X86_REG_ZMM27 }, +{ X86_ZMM28, X86_REG_ZMM28 }, +{ X86_ZMM29, X86_REG_ZMM29 }, +{ X86_ZMM30, X86_REG_ZMM30 }, +{ X86_ZMM31, X86_REG_ZMM31 }, +{ X86_R8B, X86_REG_R8B }, +{ X86_R9B, X86_REG_R9B }, +{ X86_R10B, X86_REG_R10B }, +{ X86_R11B, X86_REG_R11B }, +{ X86_R12B, X86_REG_R12B }, +{ X86_R13B, X86_REG_R13B }, +{ X86_R14B, X86_REG_R14B }, +{ X86_R15B, X86_REG_R15B }, +{ X86_R8BH, 0 }, +{ X86_R9BH, 0 }, +{ X86_R10BH, 0 }, +{ X86_R11BH, 0 }, +{ X86_R12BH, 0 }, +{ X86_R13BH, 0 }, +{ X86_R14BH, 0 }, +{ X86_R15BH, 0 }, +{ X86_R8D, X86_REG_R8D }, +{ X86_R9D, X86_REG_R9D }, +{ X86_R10D, X86_REG_R10D }, +{ X86_R11D, X86_REG_R11D }, +{ X86_R12D, X86_REG_R12D }, +{ X86_R13D, X86_REG_R13D }, +{ X86_R14D, X86_REG_R14D }, +{ X86_R15D, X86_REG_R15D }, +{ X86_R8W, X86_REG_R8W }, +{ X86_R9W, X86_REG_R9W }, +{ X86_R10W, X86_REG_R10W }, +{ X86_R11W, X86_REG_R11W }, +{ X86_R12W, X86_REG_R12W }, +{ X86_R13W, X86_REG_R13W }, +{ X86_R14W, X86_REG_R14W }, +{ X86_R15W, X86_REG_R15W }, +{ X86_R8WH, 0 }, +{ X86_R9WH, 0 }, +{ X86_R10WH, 0 }, +{ X86_R11WH, 0 }, +{ X86_R12WH, 0 }, +{ X86_R13WH, 0 }, +{ X86_R14WH, 0 }, +{ X86_R15WH, 0 }, diff --git a/thirdparty/capstone/arch/X86/X86Module.c b/thirdparty/capstone/arch/X86/X86Module.c new file mode 100644 index 0000000..ed080a7 --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86Module.c @@ -0,0 +1,94 @@ +/* Capstone Disassembly Engine */ +/* By Dang Hoang Vu 2013 */ + +#ifdef CAPSTONE_HAS_X86 + +#include "../../cs_priv.h" +#include "../../MCRegisterInfo.h" +#include "X86Disassembler.h" +#include "X86InstPrinter.h" +#include "X86Mapping.h" +#include "X86Module.h" + +cs_err X86_global_init(cs_struct *ud) +{ + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); + + X86_init(mri); + + // by default, we use Intel syntax + ud->printer = X86_Intel_printInst; + ud->syntax = CS_OPT_SYNTAX_INTEL; + ud->printer_info = mri; + ud->disasm = X86_getInstruction; + ud->reg_name = X86_reg_name; + ud->insn_id = X86_get_insn_id; + ud->insn_name = X86_insn_name; + ud->group_name = X86_group_name; + ud->post_printer = X86_postprinter; +#ifndef CAPSTONE_DIET + ud->reg_access = X86_reg_access; +#endif + + if (ud->mode == CS_MODE_64) + ud->regsize_map = regsize_map_64; + else + ud->regsize_map = regsize_map_32; + + return CS_ERR_OK; +} + +cs_err X86_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + switch(type) { + default: + break; + case CS_OPT_MODE: + if (value == CS_MODE_64) + handle->regsize_map = regsize_map_64; + else + handle->regsize_map = regsize_map_32; + + handle->mode = (cs_mode)value; + break; + case CS_OPT_SYNTAX: + switch(value) { + default: + // wrong syntax value + handle->errnum = CS_ERR_OPTION; + return CS_ERR_OPTION; + + case CS_OPT_SYNTAX_DEFAULT: + case CS_OPT_SYNTAX_INTEL: + handle->syntax = CS_OPT_SYNTAX_INTEL; + handle->printer = X86_Intel_printInst; + break; + + case CS_OPT_SYNTAX_MASM: + handle->printer = X86_Intel_printInst; + handle->syntax = (int)value; + break; + + case CS_OPT_SYNTAX_ATT: +#if !defined(CAPSTONE_DIET) && !defined(CAPSTONE_X86_ATT_DISABLE) + handle->printer = X86_ATT_printInst; + handle->syntax = CS_OPT_SYNTAX_ATT; + break; +#elif !defined(CAPSTONE_DIET) && defined(CAPSTONE_X86_ATT_DISABLE) + // ATT syntax is unsupported + handle->errnum = CS_ERR_X86_ATT; + return CS_ERR_X86_ATT; +#else // CAPSTONE_DIET + // this is irrelevant in CAPSTONE_DIET mode + handle->errnum = CS_ERR_DIET; + return CS_ERR_DIET; +#endif + } + break; + } + + return CS_ERR_OK; +} + +#endif diff --git a/thirdparty/capstone/arch/X86/X86Module.h b/thirdparty/capstone/arch/X86/X86Module.h new file mode 100644 index 0000000..53d13ed --- /dev/null +++ b/thirdparty/capstone/arch/X86/X86Module.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer , 2018 */ + +#ifndef CS_X86_MODULE_H +#define CS_X86_MODULE_H + +#include "../../utils.h" + +cs_err X86_global_init(cs_struct *ud); +cs_err X86_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/thirdparty/capstone/bindings/vb6/Project1.vbp b/thirdparty/capstone/bindings/vb6/Project1.vbp new file mode 100644 index 0000000..ccdcb77 --- /dev/null +++ b/thirdparty/capstone/bindings/vb6/Project1.vbp @@ -0,0 +1,46 @@ +Type=Exe +Reference=*\G{00020430-0000-0000-C000-000000000046}#2.0#0#C:\Windows\SysWOW64\stdole2.tlb#OLE Automation +Form=Form1.frm +Module=mCapStone; Module1.bas +Module=mx86; mx86.bas +Module=mMisc; mMisc.bas +Class=CInstruction; CInstruction.cls +Class=CInstDetails; CInstDetails.cls +Class=CDisassembler; CDisassembler.cls +Object={831FDD16-0C5C-11D2-A9FC-0000F8754DA1}#2.0#0; MSCOMCTL.OCX +Class=CX86Inst; CX86Inst.cls +Class=CX86Operand; CX86Operand.cls +Class=CX86OpMem; CX86OpMem.cls +Startup="Form1" +ExeName32="Project1.exe" +Command32="" +Name="Project1" +HelpContextID="0" +CompatibleMode="0" +MajorVer=1 +MinorVer=0 +RevisionVer=0 +AutoIncrementVer=0 +ServerSupportFiles=0 +VersionCompanyName="sandsprite" +CompilationType=0 +OptimizationType=0 +FavorPentiumPro(tm)=0 +CodeViewDebugInfo=0 +NoAliasing=0 +BoundsCheck=0 +OverflowCheck=0 +FlPointCheck=0 +FDIVCheck=0 +UnroundedFP=0 +StartMode=0 +Unattended=0 +Retained=0 +ThreadPerObject=0 +MaxNumberOfThreads=1 + +[MS Transaction Server] +AutoRefresh=1 + +[fastBuild] +fullPath=%ap%\bin\demo.exe diff --git a/thirdparty/capstone/bindings/vb6/Project1.vbw b/thirdparty/capstone/bindings/vb6/Project1.vbw new file mode 100644 index 0000000..e1f309d --- /dev/null +++ b/thirdparty/capstone/bindings/vb6/Project1.vbw @@ -0,0 +1,10 @@ +Form1 = 110, 110, 1233, 906, , 88, 88, 1116, 749, C +mCapStone = 22, 22, 1050, 683, +mx86 = 88, 88, 1040, 757, +mMisc = 66, 66, 1094, 727, +CInstruction = 182, 182, 1070, 558, +CInstDetails = 132, 132, 1084, 801, +CDisassembler = 44, 44, 1229, 809, +CX86Inst = 154, 154, 1106, 823, +CX86Operand = 176, 176, 1128, 845, +CX86OpMem = 198, 198, 1150, 867, diff --git a/thirdparty/capstone/suite/MC/ARM/arm-aliases.s.cs b/thirdparty/capstone/suite/MC/ARM/arm-aliases.s.cs new file mode 100644 index 0000000..8f3b66f --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/arm-aliases.s.cs @@ -0,0 +1,7 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x03,0x10,0x82,0xe0 = add r1, r2, r3 +0x03,0x10,0x42,0xe0 = sub r1, r2, r3 +0x03,0x10,0x22,0xe0 = eor r1, r2, r3 +0x03,0x10,0x82,0xe1 = orr r1, r2, r3 +0x03,0x10,0x02,0xe0 = and r1, r2, r3 +0x03,0x10,0xc2,0xe1 = bic r1, r2, r3 diff --git a/thirdparty/capstone/suite/MC/ARM/arm-arithmetic-aliases.s.cs b/thirdparty/capstone/suite/MC/ARM/arm-arithmetic-aliases.s.cs new file mode 100644 index 0000000..56a459f --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/arm-arithmetic-aliases.s.cs @@ -0,0 +1,50 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x06,0x20,0x42,0xe2 = sub r2, r2, #6 +0x06,0x20,0x42,0xe2 = sub r2, r2, #6 +0x03,0x20,0x42,0xe0 = sub r2, r2, r3 +0x03,0x20,0x42,0xe0 = sub r2, r2, r3 +0x06,0x20,0x82,0xe2 = add r2, r2, #6 +0x06,0x20,0x82,0xe2 = add r2, r2, #6 +0x03,0x20,0x82,0xe0 = add r2, r2, r3 +0x03,0x20,0x82,0xe0 = add r2, r2, r3 +0x06,0x20,0x02,0xe2 = and r2, r2, #6 +0x06,0x20,0x02,0xe2 = and r2, r2, #6 +0x03,0x20,0x02,0xe0 = and r2, r2, r3 +0x03,0x20,0x02,0xe0 = and r2, r2, r3 +0x06,0x20,0x82,0xe3 = orr r2, r2, #6 +0x06,0x20,0x82,0xe3 = orr r2, r2, #6 +0x03,0x20,0x82,0xe1 = orr r2, r2, r3 +0x03,0x20,0x82,0xe1 = orr r2, r2, r3 +0x06,0x20,0x22,0xe2 = eor r2, r2, #6 +0x06,0x20,0x22,0xe2 = eor r2, r2, #6 +0x03,0x20,0x22,0xe0 = eor r2, r2, r3 +0x03,0x20,0x22,0xe0 = eor r2, r2, r3 +0x06,0x20,0xc2,0xe3 = bic r2, r2, #6 +0x06,0x20,0xc2,0xe3 = bic r2, r2, #6 +0x03,0x20,0xc2,0xe1 = bic r2, r2, r3 +0x03,0x20,0xc2,0xe1 = bic r2, r2, r3 +0x06,0x20,0x52,0x02 = subseq r2, r2, #6 +0x06,0x20,0x52,0x02 = subseq r2, r2, #6 +0x03,0x20,0x52,0x00 = subseq r2, r2, r3 +0x03,0x20,0x52,0x00 = subseq r2, r2, r3 +0x06,0x20,0x92,0x02 = addseq r2, r2, #6 +0x06,0x20,0x92,0x02 = addseq r2, r2, #6 +0x03,0x20,0x92,0x00 = addseq r2, r2, r3 +0x03,0x20,0x92,0x00 = addseq r2, r2, r3 +0x06,0x20,0x12,0x02 = andseq r2, r2, #6 +0x06,0x20,0x12,0x02 = andseq r2, r2, #6 +0x03,0x20,0x12,0x00 = andseq r2, r2, r3 +0x03,0x20,0x12,0x00 = andseq r2, r2, r3 +0x06,0x20,0x92,0x03 = orrseq r2, r2, #6 +0x06,0x20,0x92,0x03 = orrseq r2, r2, #6 +0x03,0x20,0x92,0x01 = orrseq r2, r2, r3 +0x03,0x20,0x92,0x01 = orrseq r2, r2, r3 +0x06,0x20,0x32,0x02 = eorseq r2, r2, #6 +0x06,0x20,0x32,0x02 = eorseq r2, r2, #6 +0x03,0x20,0x32,0x00 = eorseq r2, r2, r3 +0x03,0x20,0x32,0x00 = eorseq r2, r2, r3 +0x06,0x20,0xd2,0x03 = bicseq r2, r2, #6 +0x06,0x20,0xd2,0x03 = bicseq r2, r2, #6 +0x03,0x20,0xd2,0x01 = bicseq r2, r2, r3 +0x03,0x20,0xd2,0x01 = bicseq r2, r2, r3 +0x7b,0x00,0x8f,0xe2 = add r0, pc, #0x7b diff --git a/thirdparty/capstone/suite/MC/ARM/arm-branches.s.cs b/thirdparty/capstone/suite/MC/ARM/arm-branches.s.cs new file mode 100644 index 0000000..0b12a6f --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/arm-branches.s.cs @@ -0,0 +1,6 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x01,0x00,0x00,0xea = b #4 +0x01,0x00,0x00,0xeb = bl #4 +0x01,0x00,0x00,0x0a = beq #4 +0x00,0x00,0x00,0xfb = blx #2 +0x01,0x00,0x00,0xea = b #4 diff --git a/thirdparty/capstone/suite/MC/ARM/arm-it-block.s.cs b/thirdparty/capstone/suite/MC/ARM/arm-it-block.s.cs new file mode 100644 index 0000000..caf1d57 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/arm-it-block.s.cs @@ -0,0 +1,2 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x03,0x20,0xa0,0x01 = moveq r2, r3 diff --git a/thirdparty/capstone/suite/MC/ARM/arm-memory-instructions.s.cs b/thirdparty/capstone/suite/MC/ARM/arm-memory-instructions.s.cs new file mode 100644 index 0000000..db0e870 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/arm-memory-instructions.s.cs @@ -0,0 +1,143 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x00,0x50,0x97,0xe5 = ldr r5, [r7] +0x3f,0x60,0x93,0xe5 = ldr r6, [r3, #0x3f] +0xff,0x2f,0xb4,0xe5 = ldr r2, [r4, #0xfff]! +0x1e,0x10,0x92,0xe4 = ldr r1, [r2], #0x1e +0x1e,0x30,0x11,0xe4 = ldr r3, [r1], #-0x1e +0x00,0x90,0x12,0xe4 = ldr r9, [r2], #-0 +0x01,0x30,0x98,0xe7 = ldr r3, [r8, r1] +0x03,0x20,0x15,0xe7 = ldr r2, [r5, -r3] +0x09,0x10,0xb5,0xe7 = ldr r1, [r5, r9]! +0x08,0x60,0x37,0xe7 = ldr r6, [r7, -r8]! +0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]! +0x02,0x50,0x99,0xe6 = ldr r5, [r9], r2 +0x06,0x40,0x13,0xe6 = ldr r4, [r3], -r6 +0x82,0x37,0x18,0xe7 = ldr r3, [r8, -r2, lsl #0xf] +0xc3,0x17,0x95,0xe6 = ldr r1, [r5], r3, asr #0xf +0x00,0x30,0xd8,0xe5 = ldrb r3, [r8] +0x3f,0x10,0xdd,0xe5 = ldrb r1, [sp, #0x3f] +0xff,0x9f,0xf3,0xe5 = ldrb r9, [r3, #0xfff]! +0x16,0x80,0xd1,0xe4 = ldrb r8, [r1], #0x16 +0x13,0x20,0x57,0xe4 = ldrb r2, [r7], #-0x13 +0x05,0x90,0xd8,0xe7 = ldrb r9, [r8, r5] +0x01,0x10,0x55,0xe7 = ldrb r1, [r5, -r1] +0x02,0x30,0xf5,0xe7 = ldrb r3, [r5, r2]! +0x03,0x60,0x79,0xe7 = ldrb r6, [r9, -r3]! +0x04,0x20,0xd1,0xe6 = ldrb r2, [r1], r4 +0x05,0x80,0x54,0xe6 = ldrb r8, [r4], -r5 +0x81,0x77,0x5c,0xe7 = ldrb r7, [r12, -r1, lsl #0xf] +0xc9,0x57,0xd2,0xe6 = ldrb r5, [r2], r9, asr #0xf +0x04,0x30,0xf1,0xe4 = ldrbt r3, [r1], #4 +0x08,0x20,0x78,0xe4 = ldrbt r2, [r8], #-8 +0x06,0x80,0xf7,0xe6 = ldrbt r8, [r7], r6 +0x06,0x16,0x72,0xe6 = ldrbt r1, [r2], -r6, lsl #0xc +0xd0,0x20,0xc5,0xe1 = ldrd r2, r3, [r5] +0xdf,0x60,0xc2,0xe1 = ldrd r6, r7, [r2, #0xf] +0xd0,0x02,0xe9,0xe1 = ldrd r0, r1, [r9, #0x20]! +0xd8,0x60,0xc1,0xe0 = ldrd r6, r7, [r1], #8 +0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0 +0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0 +0xd0,0x00,0x48,0xe0 = ldrd r0, r1, [r8], #-0 +0xd3,0x40,0x81,0xe1 = ldrd r4, r5, [r1, r3] +0xd2,0x40,0xa7,0xe1 = ldrd r4, r5, [r7, r2]! +0xdc,0x00,0x88,0xe0 = ldrd r0, r1, [r8], r12 +0xdc,0x00,0x08,0xe0 = ldrd r0, r1, [r8], -r12 +0xb0,0x30,0xd4,0xe1 = ldrh r3, [r4] +0xb4,0x20,0xd7,0xe1 = ldrh r2, [r7, #4] +0xb0,0x14,0xf8,0xe1 = ldrh r1, [r8, #0x40]! +0xb4,0xc0,0xdd,0xe0 = ldrh r12, [sp], #4 +0xb4,0x60,0x95,0xe1 = ldrh r6, [r5, r4] +0xbb,0x30,0xb8,0xe1 = ldrh r3, [r8, r11]! +0xb1,0x10,0x32,0xe1 = ldrh r1, [r2, -r1]! +0xb2,0x90,0x97,0xe0 = ldrh r9, [r7], r2 +0xb2,0x40,0x13,0xe0 = ldrh r4, [r3], -r2 +0xb0,0x98,0xf7,0xe0 = ldrht r9, [r7], #0x80 +0xbb,0x44,0x73,0xe0 = ldrht r4, [r3], #-0x4b +0xb0,0x40,0xf3,0xe0 = ldrht r4, [r3], #0 +0xb2,0x90,0xb7,0xe0 = ldrht r9, [r7], r2 +0xb2,0x40,0x33,0xe0 = ldrht r4, [r3], -r2 +0xd0,0x30,0xd4,0xe1 = ldrsb r3, [r4] +0xd1,0x21,0xd7,0xe1 = ldrsb r2, [r7, #0x11] +0xdf,0x1f,0xf8,0xe1 = ldrsb r1, [r8, #0xff]! +0xd9,0xc0,0xdd,0xe0 = ldrsb r12, [sp], #0x9 +0xd4,0x60,0x95,0xe1 = ldrsb r6, [r5, r4] +0xdb,0x30,0xb8,0xe1 = ldrsb r3, [r8, r11]! +0xd1,0x10,0x32,0xe1 = ldrsb r1, [r2, -r1]! +0xd2,0x90,0x97,0xe0 = ldrsb r9, [r7], r2 +0xd2,0x40,0x13,0xe0 = ldrsb r4, [r3], -r2 +0xd1,0x50,0xf6,0xe0 = ldrsbt r5, [r6], #1 +0xdc,0x30,0x78,0xe0 = ldrsbt r3, [r8], #-0xc +0xd0,0x50,0xf6,0xe0 = ldrsbt r5, [r6], #0 +0xd5,0x80,0xb9,0xe0 = ldrsbt r8, [r9], r5 +0xd4,0x20,0x31,0xe0 = ldrsbt r2, [r1], -r4 +0xf0,0x50,0xd9,0xe1 = ldrsh r5, [r9] +0xf7,0x40,0xd5,0xe1 = ldrsh r4, [r5, #7] +0xf7,0x33,0xf6,0xe1 = ldrsh r3, [r6, #0x37]! +0xf9,0x20,0x57,0xe0 = ldrsh r2, [r7], #-0x9 +0xf5,0x30,0x91,0xe1 = ldrsh r3, [r1, r5] +0xf1,0x40,0xb6,0xe1 = ldrsh r4, [r6, r1]! +0xf6,0x50,0x33,0xe1 = ldrsh r5, [r3, -r6]! +0xf8,0x60,0x99,0xe0 = ldrsh r6, [r9], r8 +0xf3,0x70,0x18,0xe0 = ldrsh r7, [r8], -r3 +0xf1,0x50,0xf6,0xe0 = ldrsht r5, [r6], #1 +0xfc,0x30,0x78,0xe0 = ldrsht r3, [r8], #-0xc +0xf0,0x50,0xf6,0xe0 = ldrsht r5, [r6], #0 +0xf5,0x80,0xb9,0xe0 = ldrsht r8, [r9], r5 +0xf4,0x20,0x31,0xe0 = ldrsht r2, [r1], -r4 +0x00,0x80,0x8c,0xe5 = str r8, [r12] +0x0c,0x70,0x81,0xe5 = str r7, [r1, #0xc] +0x28,0x30,0xa5,0xe5 = str r3, [r5, #0x28]! +0xff,0x9f,0x8d,0xe4 = str r9, [sp], #0xfff +0x80,0x10,0x07,0xe4 = str r1, [r7], #-0x80 +0x00,0x10,0x00,0xe4 = str r1, [r0], #-0 +0x03,0x90,0x86,0xe7 = str r9, [r6, r3] +0x02,0x80,0x00,0xe7 = str r8, [r0, -r2] +0x06,0x70,0xa1,0xe7 = str r7, [r1, r6]! +0x01,0x60,0x2d,0xe7 = str r6, [sp, -r1]! +0x09,0x50,0x83,0xe6 = str r5, [r3], r9 +0x05,0x40,0x02,0xe6 = str r4, [r2], -r5 +0x02,0x31,0x04,0xe7 = str r3, [r4, -r2, lsl #2] +0x43,0x2c,0x87,0xe6 = str r2, [r7], r3, asr #0x18 +0x00,0x90,0xc2,0xe5 = strb r9, [r2] +0x03,0x70,0xc1,0xe5 = strb r7, [r1, #3] +0x95,0x61,0xe4,0xe5 = strb r6, [r4, #0x195]! +0x48,0x50,0xc7,0xe4 = strb r5, [r7], #0x48 +0x01,0x10,0x4d,0xe4 = strb r1, [sp], #-1 +0x09,0x10,0xc2,0xe7 = strb r1, [r2, r9] +0x08,0x20,0x43,0xe7 = strb r2, [r3, -r8] +0x07,0x30,0xe4,0xe7 = strb r3, [r4, r7]! +0x06,0x40,0x65,0xe7 = strb r4, [r5, -r6]! +0x05,0x50,0xc6,0xe6 = strb r5, [r6], r5 +0x04,0x60,0x42,0xe6 = strb r6, [r2], -r4 +0x83,0x72,0x4c,0xe7 = strb r7, [r12, -r3, lsl #5] +0x42,0xd6,0xc7,0xe6 = strb sp, [r7], r2, asr #0xc +0x0c,0x60,0xe2,0xe4 = strbt r6, [r2], #0xc +0x0d,0x50,0x66,0xe4 = strbt r5, [r6], #-0xd +0x05,0x40,0xe9,0xe6 = strbt r4, [r9], r5 +0x82,0x31,0x68,0xe6 = strbt r3, [r8], -r2, lsl #3 +0xf0,0x20,0xc4,0xe1 = strd r2, r3, [r4] +0xf1,0x20,0xc6,0xe1 = strd r2, r3, [r6, #1] +0xf6,0x01,0xe7,0xe1 = strd r0, r1, [r7, #0x16]! +0xf7,0x40,0xc8,0xe0 = strd r4, r5, [r8], #7 +0xf0,0x40,0xcd,0xe0 = strd r4, r5, [sp], #0 +0xf0,0x60,0xce,0xe0 = strd r6, r7, [lr], #0 +0xf0,0xa0,0x49,0xe0 = strd r10, r11, [r9], #-0 +0xf1,0x80,0x84,0xe1 = strd r8, r9, [r4, r1] +0xf9,0x60,0xa3,0xe1 = strd r6, r7, [r3, r9]! +0xf8,0x60,0x85,0xe0 = strd r6, r7, [r5], r8 +0xfa,0x40,0x0c,0xe0 = strd r4, r5, [r12], -r10 +0xb0,0x30,0xc4,0xe1 = strh r3, [r4] +0xb4,0x20,0xc7,0xe1 = strh r2, [r7, #4] +0xb0,0x14,0xe8,0xe1 = strh r1, [r8, #0x40]! +0xb4,0xc0,0xcd,0xe0 = strh r12, [sp], #4 +0xb4,0x60,0x85,0xe1 = strh r6, [r5, r4] +0xbb,0x30,0xa8,0xe1 = strh r3, [r8, r11]! +0xb1,0x10,0x22,0xe1 = strh r1, [r2, -r1]! +0xb2,0x90,0x87,0xe0 = strh r9, [r7], r2 +0xb2,0x40,0x03,0xe0 = strh r4, [r3], -r2 +0xbc,0x24,0xe5,0xe0 = strht r2, [r5], #0x4c +0xb9,0x81,0x61,0xe0 = strht r8, [r1], #-0x19 +0xb4,0x50,0xa3,0xe0 = strht r5, [r3], r4 +0xb0,0x60,0x28,0xe0 = strht r6, [r8], -r0 +0xd0,0x00,0xcd,0xe1 = ldrd r0, r1, [sp] +0xf0,0x00,0xcd,0xe1 = strd r0, r1, [sp] diff --git a/thirdparty/capstone/suite/MC/ARM/arm-shift-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/arm-shift-encoding.s.cs new file mode 100644 index 0000000..13a7cc6 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/arm-shift-encoding.s.cs @@ -0,0 +1,50 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0] +0x20,0x00,0x90,0xe7 = ldr r0, [r0, r0, lsr #0x20] +0x20,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsr #0x10] +0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0] +0x00,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsl #0x10] +0x40,0x00,0x90,0xe7 = ldr r0, [r0, r0, asr #0x20] +0x40,0x08,0x90,0xe7 = ldr r0, [r0, r0, asr #0x10] +0x60,0x00,0x90,0xe7 = ldr r0, [r0, r0, rrx] +0x60,0x08,0x90,0xe7 = ldr r0, [r0, r0, ror #0x10] +0x00,0xf0,0xd0,0xf7 = pld [r0, r0] +0x20,0xf0,0xd0,0xf7 = pld [r0, r0, lsr #0x20] +0x20,0xf8,0xd0,0xf7 = pld [r0, r0, lsr #0x10] +0x00,0xf0,0xd0,0xf7 = pld [r0, r0] +0x00,0xf8,0xd0,0xf7 = pld [r0, r0, lsl #0x10] +0x40,0xf0,0xd0,0xf7 = pld [r0, r0, asr #0x20] +0x40,0xf8,0xd0,0xf7 = pld [r0, r0, asr #0x10] +0x60,0xf0,0xd0,0xf7 = pld [r0, r0, rrx] +0x60,0xf8,0xd0,0xf7 = pld [r0, r0, ror #0x10] +0x00,0x00,0x80,0xe7 = str r0, [r0, r0] +0x20,0x00,0x80,0xe7 = str r0, [r0, r0, lsr #0x20] +0x20,0x08,0x80,0xe7 = str r0, [r0, r0, lsr #0x10] +0x00,0x00,0x80,0xe7 = str r0, [r0, r0] +0x00,0x08,0x80,0xe7 = str r0, [r0, r0, lsl #0x10] +0x40,0x00,0x80,0xe7 = str r0, [r0, r0, asr #0x20] +0x40,0x08,0x80,0xe7 = str r0, [r0, r0, asr #0x10] +0x60,0x00,0x80,0xe7 = str r0, [r0, r0, rrx] +0x60,0x08,0x80,0xe7 = str r0, [r0, r0, ror #0x10] +0x62,0x00,0x91,0xe6 = ldr r0, [r1], r2, rrx +0x05,0x30,0x94,0xe6 = ldr r3, [r4], r5 +0x08,0x60,0x87,0xe6 = str r6, [r7], r8 +0x0b,0x90,0x8a,0xe6 = str r9, [r10], r11 +0x0f,0xd0,0xae,0xe0 = adc sp, lr, pc +0x29,0x10,0xa8,0xe0 = adc r1, r8, r9, lsr #0x20 +0x2f,0x28,0xa7,0xe0 = adc r2, r7, pc, lsr #0x10 +0x0a,0x30,0xa6,0xe0 = adc r3, r6, r10 +0x0e,0x48,0xa5,0xe0 = adc r4, r5, lr, lsl #0x10 +0x4b,0x50,0xa4,0xe0 = adc r5, r4, r11, asr #0x20 +0x4d,0x68,0xa3,0xe0 = adc r6, r3, sp, asr #0x10 +0x6c,0x70,0xa2,0xe0 = adc r7, r2, r12, rrx +0x60,0x88,0xa1,0xe0 = adc r8, r1, r0, ror #0x10 +0x0e,0x00,0x5d,0xe1 = cmp sp, lr +0x28,0x00,0x51,0xe1 = cmp r1, r8, lsr #0x20 +0x27,0x08,0x52,0xe1 = cmp r2, r7, lsr #0x10 +0x06,0x00,0x53,0xe1 = cmp r3, r6 +0x05,0x08,0x54,0xe1 = cmp r4, r5, lsl #0x10 +0x44,0x00,0x55,0xe1 = cmp r5, r4, asr #0x20 +0x43,0x08,0x56,0xe1 = cmp r6, r3, asr #0x10 +0x62,0x00,0x57,0xe1 = cmp r7, r2, rrx +0x61,0x08,0x58,0xe1 = cmp r8, r1, ror #0x10 diff --git a/thirdparty/capstone/suite/MC/ARM/arm-thumb-trustzone.s.cs b/thirdparty/capstone/suite/MC/ARM/arm-thumb-trustzone.s.cs new file mode 100644 index 0000000..a8428b5 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/arm-thumb-trustzone.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xff,0xf7,0x00,0x80 = smc #15 +0x0c,0xbf = ite eq diff --git a/thirdparty/capstone/suite/MC/ARM/arm-trustzone.s.cs b/thirdparty/capstone/suite/MC/ARM/arm-trustzone.s.cs new file mode 100644 index 0000000..163b06c --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/arm-trustzone.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x7f,0x00,0x60,0xe1 = smc #15 +0x70,0x00,0x60,0x01 = smceq #0 diff --git a/thirdparty/capstone/suite/MC/ARM/arm_addrmode2.s.cs b/thirdparty/capstone/suite/MC/ARM/arm_addrmode2.s.cs new file mode 100644 index 0000000..082f798 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/arm_addrmode2.s.cs @@ -0,0 +1,19 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x02,0x10,0xb0,0xe6 = ldrt r1, [r0], r2 +0xa2,0x11,0xb0,0xe6 = ldrt r1, [r0], r2, lsr #3 +0x04,0x10,0xb0,0xe4 = ldrt r1, [r0], #4 +0x00,0x10,0xb0,0xe4 = ldrt r1, [r0], #0 +0x02,0x10,0xf0,0xe6 = ldrbt r1, [r0], r2 +0xa2,0x11,0xf0,0xe6 = ldrbt r1, [r0], r2, lsr #3 +0x04,0x10,0xf0,0xe4 = ldrbt r1, [r0], #4 +0x00,0x10,0xf0,0xe4 = ldrbt r1, [r0], #0 +0x02,0x10,0xa0,0xe6 = strt r1, [r0], r2 +0xa2,0x11,0xa0,0xe6 = strt r1, [r0], r2, lsr #3 +0x04,0x10,0xa0,0xe4 = strt r1, [r0], #4 +0x00,0x10,0xa0,0xe4 = strt r1, [r0], #0 +0x02,0x10,0xe0,0xe6 = strbt r1, [r0], r2 +0xa2,0x11,0xe0,0xe6 = strbt r1, [r0], r2, lsr #3 +0x04,0x10,0xe0,0xe4 = strbt r1, [r0], #4 +0x00,0x10,0xe0,0xe4 = strbt r1, [r0], #0 +0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]! +0xa2,0x11,0xf0,0xe7 = ldrb r1, [r0, r2, lsr #3]! diff --git a/thirdparty/capstone/suite/MC/ARM/arm_addrmode3.s.cs b/thirdparty/capstone/suite/MC/ARM/arm_addrmode3.s.cs new file mode 100644 index 0000000..5dca005 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/arm_addrmode3.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xd2,0x10,0xb0,0xe0 = ldrsbt r1, [r0], r2 +0xd4,0x10,0xf0,0xe0 = ldrsbt r1, [r0], #4 +0xf2,0x10,0xb0,0xe0 = ldrsht r1, [r0], r2 +0xf4,0x10,0xf0,0xe0 = ldrsht r1, [r0], #4 +0xb2,0x10,0xb0,0xe0 = ldrht r1, [r0], r2 +0xb4,0x10,0xf0,0xe0 = ldrht r1, [r0], #4 +0xb2,0x10,0xa0,0xe0 = strht r1, [r0], r2 +0xb4,0x10,0xe0,0xe0 = strht r1, [r0], #4 diff --git a/thirdparty/capstone/suite/MC/ARM/arm_instructions.s.cs b/thirdparty/capstone/suite/MC/ARM/arm_instructions.s.cs new file mode 100644 index 0000000..5602e99 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/arm_instructions.s.cs @@ -0,0 +1,23 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x03,0x10,0x02,0xe0 = and r1, r2, r3 +0x03,0x10,0x12,0xe0 = ands r1, r2, r3 +0x03,0x10,0x22,0xe0 = eor r1, r2, r3 +0x03,0x10,0x32,0xe0 = eors r1, r2, r3 +0x03,0x10,0x42,0xe0 = sub r1, r2, r3 +0x03,0x10,0x52,0xe0 = subs r1, r2, r3 +0x03,0x10,0x82,0xe0 = add r1, r2, r3 +0x03,0x10,0x92,0xe0 = adds r1, r2, r3 +0x03,0x10,0xa2,0xe0 = adc r1, r2, r3 +0x03,0x10,0xc2,0xe1 = bic r1, r2, r3 +0x03,0x10,0xd2,0xe1 = bics r1, r2, r3 +0x02,0x10,0xa0,0xe1 = mov r1, r2 +0x02,0x10,0xe0,0xe1 = mvn r1, r2 +0x02,0x10,0xf0,0xe1 = mvns r1, r2 +0x90,0x02,0xcb,0xe7 = bfi r0, r0, #5, #7 +0x7a,0x00,0x20,0xe1 = bkpt #0xa +0x81,0x17,0x11,0xee = cdp p7, #1, c1, c1, c1, #4 +0x81,0x17,0x11,0xfe = cdp2 p7, #1, c1, c1, c1, #4 +0x13,0x14,0x82,0xe0 = add r1, r2, r3, lsl r4 +0x30,0x0f,0xa6,0xe6 = ssat16 r0, #7, r0 +0x00,0x00,0x0a,0xf1 = cpsie none, #0 +0xb0,0x30,0x42,0xe1 = strh r3, [r2, #-0] diff --git a/thirdparty/capstone/suite/MC/ARM/armv8.1m-pacbti.s.cs b/thirdparty/capstone/suite/MC/ARM/armv8.1m-pacbti.s.cs new file mode 100644 index 0000000..1bde361 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/armv8.1m-pacbti.s.cs @@ -0,0 +1,6 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xaf,0xf3,0x2d,0x80 = aut r12, lr, sp +0xaf,0xf3,0x0f,0x80 = bti +0xaf,0xf3,0x0f,0x80 = bti +0xaf,0xf3,0x1d,0x80 = pac r12, lr, sp +0xaf,0xf3,0x0d,0x80 = pacbti r12, lr, sp diff --git a/thirdparty/capstone/suite/MC/ARM/armv8.2a-dotprod-a32.s.cs b/thirdparty/capstone/suite/MC/ARM/armv8.2a-dotprod-a32.s.cs new file mode 100644 index 0000000..72eaecd --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/armv8.2a-dotprod-a32.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x12,0x0d,0x21,0xfc = vudot.u8 d0, d1, d2 +0x02,0x0d,0x21,0xfc = vsdot.s8 d0, d1, d2 +0x58,0x0d,0x22,0xfc = vudot.u8 q0, q1, q4 +0x48,0x0d,0x22,0xfc = vsdot.s8 q0, q1, q4 +0x12,0x0d,0x21,0xfe = vudot.u8 d0, d1, d2[0] +0x22,0x0d,0x21,0xfe = vsdot.s8 d0, d1, d2[1] +0x54,0x0d,0x22,0xfe = vudot.u8 q0, q1, d4[0] +0x64,0x0d,0x22,0xfe = vsdot.s8 q0, q1, d4[1] diff --git a/thirdparty/capstone/suite/MC/ARM/armv8.2a-dotprod-t32.s.cs b/thirdparty/capstone/suite/MC/ARM/armv8.2a-dotprod-t32.s.cs new file mode 100644 index 0000000..2a2879c --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/armv8.2a-dotprod-t32.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x21,0xfc,0x12,0x0d = vudot.u8 d0, d1, d2 +0x21,0xfc,0x02,0x0d = vsdot.s8 d0, d1, d2 +0x22,0xfc,0x58,0x0d = vudot.u8 q0, q1, q4 +0x22,0xfc,0x48,0x0d = vsdot.s8 q0, q1, q4 +0x21,0xfe,0x12,0x0d = vudot.u8 d0, d1, d2[0] +0x21,0xfe,0x22,0x0d = vsdot.s8 d0, d1, d2[1] +0x22,0xfe,0x54,0x0d = vudot.u8 q0, q1, d4[0] +0x22,0xfe,0x64,0x0d = vsdot.s8 q0, q1, d4[1] diff --git a/thirdparty/capstone/suite/MC/ARM/armv8.5a-sb.s.cs b/thirdparty/capstone/suite/MC/ARM/armv8.5a-sb.s.cs new file mode 100644 index 0000000..a6a3cee --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/armv8.5a-sb.s.cs @@ -0,0 +1,2 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x70,0xf0,0x7f,0xf5 = sb diff --git a/thirdparty/capstone/suite/MC/ARM/armv8a-fpmul.s.cs b/thirdparty/capstone/suite/MC/ARM/armv8a-fpmul.s.cs new file mode 100644 index 0000000..d212500 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/armv8a-fpmul.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x91,0x08,0x20,0xfc = vfmal.f16 d0, s1, s2 +0x91,0x08,0xa0,0xfc = vfmsl.f16 d0, s1, s2 +0x52,0x08,0x21,0xfc = vfmal.f16 q0, d1, d2 +0x52,0x08,0xa1,0xfc = vfmsl.f16 q0, d1, d2 +0x99,0x08,0x00,0xfe = vfmal.f16 d0, s1, s2[1] +0x99,0x08,0x10,0xfe = vfmsl.f16 d0, s1, s2[1] +0x7a,0x08,0x01,0xfe = vfmal.f16 q0, d1, d2[3] +0x7a,0x08,0x11,0xfe = vfmsl.f16 q0, d1, d2[3] diff --git a/thirdparty/capstone/suite/MC/ARM/basic-arm-instructions-v8.s.cs b/thirdparty/capstone/suite/MC/ARM/basic-arm-instructions-v8.s.cs new file mode 100644 index 0000000..387f845 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/basic-arm-instructions-v8.s.cs @@ -0,0 +1,10 @@ +# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None +0x59,0xf0,0x7f,0xf5 = dmb ishld +0x51,0xf0,0x7f,0xf5 = dmb oshld +0x55,0xf0,0x7f,0xf5 = dmb nshld +0x5d,0xf0,0x7f,0xf5 = dmb ld +0x49,0xf0,0x7f,0xf5 = dsb ishld +0x41,0xf0,0x7f,0xf5 = dsb oshld +0x45,0xf0,0x7f,0xf5 = dsb nshld +0x4d,0xf0,0x7f,0xf5 = dsb ld +0x05,0xf0,0x20,0xe3 = sevl diff --git a/thirdparty/capstone/suite/MC/ARM/basic-arm-instructions.s.cs b/thirdparty/capstone/suite/MC/ARM/basic-arm-instructions.s.cs new file mode 100644 index 0000000..bc82ec9 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/basic-arm-instructions.s.cs @@ -0,0 +1,1305 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x0f,0x10,0xa2,0xe2 = adc r1, r2, #0xf +0x0f,0x10,0xa2,0xe2 = adc r1, r2, #0xf +0x0f,0x10,0xa2,0xe2 = adc r1, r2, #0xf +0xff,0x78,0xa8,0xe2 = adc r7, r8, #0xff0000 +0x2a,0x71,0xa8,0xe2 = adc r7, r8, #-0x7ffffff6 +0x2a,0x71,0xa8,0xe2 = adc r7, r8, #-0x7ffffff6 +0x28,0x71,0xa8,0xe2 = adc r7, r8, #0x28, #2 +0x28,0x71,0xa8,0xe2 = adc r7, r8, #0x28, #2 +0x28,0x71,0xa8,0xe2 = adc r7, r8, #0x28, #2 +0x28,0x71,0xa8,0xe2 = adc r7, r8, #0x28, #2 +0xf0,0x10,0xa2,0xe2 = adc r1, r2, #0xf0 +0x0f,0x1c,0xa2,0xe2 = adc r1, r2, #0xf00 +0x0f,0x1a,0xa2,0xe2 = adc r1, r2, #0xf000 +0x0f,0x18,0xa2,0xe2 = adc r1, r2, #0xf0000 +0x0f,0x16,0xa2,0xe2 = adc r1, r2, #0xf00000 +0x0f,0x14,0xa2,0xe2 = adc r1, r2, #0xf000000 +0x0f,0x12,0xa2,0xe2 = adc r1, r2, #-0x10000000 +0xff,0x12,0xa2,0xe2 = adc r1, r2, #-0xffffff1 +0x0f,0x1c,0xb2,0xe2 = adcs r1, r2, #0xf00 +0x28,0x71,0xb8,0xe2 = adcs r7, r8, #0x28, #2 +0x0f,0x1c,0xb2,0x02 = adcseq r1, r2, #0xf00 +0x0f,0x1c,0xa2,0x02 = adceq r1, r2, #0xf00 +0x06,0x40,0xa5,0xe0 = adc r4, r5, r6 +0x86,0x40,0xa5,0xe0 = adc r4, r5, r6, lsl #1 +0x86,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsl #0x1f +0xa6,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #1 +0xa6,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsr #0x1f +0x26,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #0x20 +0xc6,0x40,0xa5,0xe0 = adc r4, r5, r6, asr #1 +0xc6,0x4f,0xa5,0xe0 = adc r4, r5, r6, asr #0x1f +0x46,0x40,0xa5,0xe0 = adc r4, r5, r6, asr #0x20 +0xe6,0x40,0xa5,0xe0 = adc r4, r5, r6, ror #1 +0xe6,0x4f,0xa5,0xe0 = adc r4, r5, r6, ror #0x1f +0x18,0x69,0xa7,0xe0 = adc r6, r7, r8, lsl r9 +0x38,0x69,0xa7,0xe0 = adc r6, r7, r8, lsr r9 +0x58,0x69,0xa7,0xe0 = adc r6, r7, r8, asr r9 +0x78,0x69,0xa7,0xe0 = adc r6, r7, r8, ror r9 +0x66,0x40,0xa5,0xe0 = adc r4, r5, r6, rrx +0x06,0x50,0xa5,0xe0 = adc r5, r5, r6 +0x85,0x40,0xa4,0xe0 = adc r4, r4, r5, lsl #1 +0x85,0x4f,0xa4,0xe0 = adc r4, r4, r5, lsl #0x1f +0xa5,0x40,0xa4,0xe0 = adc r4, r4, r5, lsr #1 +0xa5,0x4f,0xa4,0xe0 = adc r4, r4, r5, lsr #0x1f +0x25,0x40,0xa4,0xe0 = adc r4, r4, r5, lsr #0x20 +0xc5,0x40,0xa4,0xe0 = adc r4, r4, r5, asr #1 +0xc5,0x4f,0xa4,0xe0 = adc r4, r4, r5, asr #0x1f +0x45,0x40,0xa4,0xe0 = adc r4, r4, r5, asr #0x20 +0xe5,0x40,0xa4,0xe0 = adc r4, r4, r5, ror #1 +0xe5,0x4f,0xa4,0xe0 = adc r4, r4, r5, ror #0x1f +0x65,0x40,0xa4,0xe0 = adc r4, r4, r5, rrx +0x17,0x69,0xa6,0xe0 = adc r6, r6, r7, lsl r9 +0x37,0x69,0xa6,0xe0 = adc r6, r6, r7, lsr r9 +0x57,0x69,0xa6,0xe0 = adc r6, r6, r7, asr r9 +0x77,0x69,0xa6,0xe0 = adc r6, r6, r7, ror r9 +0x65,0x40,0xa4,0xe0 = adc r4, r4, r5, rrx +0x03,0x20,0x8f,0xe2 = add r2, pc, #3 +0x03,0x20,0x4f,0xe2 = sub r2, pc, #3 +0x00,0x10,0x4f,0xe2 = sub r1, pc, #0 +0x12,0x14,0x4f,0xe2 = sub r1, pc, #301989888 +0x06,0x11,0x4f,0xe2 = sub r1, pc, #-2147483647 +0x12,0x14,0x8f,0xe2 = add r1, pc, #301989888 +0x06,0x11,0x8f,0xe2 = add r1, pc, #-2147483647 +0x0f,0x4a,0x85,0xe2 = add r4, r5, #0xf000 +0x0f,0x4a,0x85,0xe2 = add r4, r5, #0xf000 +0x0f,0x4a,0x85,0xe2 = add r4, r5, #0xf000 +0x0f,0x4a,0x45,0xe2 = sub r4, r5, #0xf000 +0xff,0x78,0x88,0xe2 = add r7, r8, #0xff0000 +0x2a,0x71,0x88,0xe2 = add r7, r8, #-0x7ffffff6 +0x2a,0x71,0x88,0xe2 = add r7, r8, #-0x7ffffff6 +0x28,0x71,0x88,0xe2 = add r7, r8, #0x28, #2 +0x28,0x71,0x88,0xe2 = add r7, r8, #0x28, #2 +0x28,0x71,0x88,0xe2 = add r7, r8, #0x28, #2 +0x28,0x71,0x88,0xe2 = add r7, r8, #0x28, #2 +0x06,0x40,0x85,0xe0 = add r4, r5, r6 +0x86,0x42,0x85,0xe0 = add r4, r5, r6, lsl #5 +0xa6,0x42,0x85,0xe0 = add r4, r5, r6, lsr #5 +0xa6,0x42,0x85,0xe0 = add r4, r5, r6, lsr #5 +0xc6,0x42,0x85,0xe0 = add r4, r5, r6, asr #5 +0xe6,0x42,0x85,0xe0 = add r4, r5, r6, ror #5 +0x18,0x69,0x87,0xe0 = add r6, r7, r8, lsl r9 +0x13,0x49,0x84,0xe0 = add r4, r4, r3, lsl r9 +0x38,0x69,0x87,0xe0 = add r6, r7, r8, lsr r9 +0x58,0x69,0x87,0xe0 = add r6, r7, r8, asr r9 +0x78,0x69,0x87,0xe0 = add r6, r7, r8, ror r9 +0x66,0x40,0x85,0xe0 = add r4, r5, r6, rrx +0x0f,0x5a,0x85,0xe2 = add r5, r5, #0xf000 +0x0f,0x5a,0x85,0xe2 = add r5, r5, #0xf000 +0x0f,0x5a,0x85,0xe2 = add r5, r5, #0xf000 +0x0f,0x5a,0x45,0xe2 = sub r5, r5, #0xf000 +0xff,0x78,0x87,0xe2 = add r7, r7, #0xff0000 +0x2a,0x71,0x87,0xe2 = add r7, r7, #-0x7ffffff6 +0x2a,0x71,0x87,0xe2 = add r7, r7, #-0x7ffffff6 +0x28,0x71,0x87,0xe2 = add r7, r7, #0x28, #2 +0x28,0x71,0x87,0xe2 = add r7, r7, #0x28, #2 +0x28,0x71,0x87,0xe2 = add r7, r7, #0x28, #2 +0x28,0x71,0x87,0xe2 = add r7, r7, #0x28, #2 +0x05,0x40,0x84,0xe0 = add r4, r4, r5 +0x85,0x42,0x84,0xe0 = add r4, r4, r5, lsl #5 +0xa5,0x42,0x84,0xe0 = add r4, r4, r5, lsr #5 +0xa5,0x42,0x84,0xe0 = add r4, r4, r5, lsr #5 +0xc5,0x42,0x84,0xe0 = add r4, r4, r5, asr #5 +0xe5,0x42,0x84,0xe0 = add r4, r4, r5, ror #5 +0x17,0x69,0x86,0xe0 = add r6, r6, r7, lsl r9 +0x37,0x69,0x86,0xe0 = add r6, r6, r7, lsr r9 +0x57,0x69,0x86,0xe0 = add r6, r6, r7, asr r9 +0x77,0x69,0x86,0xe0 = add r6, r6, r7, ror r9 +0x65,0x40,0x84,0xe0 = add r4, r4, r5, rrx +0x04,0x00,0x40,0xe2 = sub r0, r0, #4 +0x15,0x40,0x45,0xe2 = sub r4, r5, #0x15 +0x03,0x01,0x8f,0xe2 = add r0, pc, #-1073741824 +0x03,0x01,0x9f,0x02 = addseq r0, pc, #-0x40000000 +0x22,0x30,0x81,0xe0 = add r3, r1, r2, lsr #0x20 +0x42,0x30,0x81,0xe0 = add r3, r1, r2, asr #0x20 +0xff,0x78,0x98,0xe2 = adds r7, r8, #0xff0000 +0xff,0x78,0x98,0xe2 = adds r7, r8, #0xff0000 +0xff,0x78,0x98,0xe2 = adds r7, r8, #0xff0000 +0xff,0x78,0x98,0xe2 = adds r7, r8, #0xff0000 +0x2a,0x71,0x98,0xe2 = adds r7, r8, #-0x7ffffff6 +0x2a,0x71,0x98,0xe2 = adds r7, r8, #-0x7ffffff6 +0x28,0x71,0x98,0xe2 = adds r7, r8, #0x28, #2 +0x28,0x71,0x98,0xe2 = adds r7, r8, #0x28, #2 +0x28,0x71,0x98,0xe2 = adds r7, r8, #0x28, #2 +0x28,0x71,0x98,0xe2 = adds r7, r8, #0x28, #2 +0x0f,0xa0,0x01,0xe2 = and r10, r1, #0xf +0x0f,0xa0,0x01,0xe2 = and r10, r1, #0xf +0x0f,0xa0,0x01,0xe2 = and r10, r1, #0xf +0x0e,0xa0,0xc1,0xe3 = bic r10, r1, #0xe +0xff,0x78,0x08,0xe2 = and r7, r8, #0xff0000 +0x2a,0x71,0x08,0xe2 = and r7, r8, #-0x7ffffff6 +0x2a,0x71,0x08,0xe2 = and r7, r8, #-0x7ffffff6 +0x28,0x71,0x08,0xe2 = and r7, r8, #0x28, #2 +0x28,0x71,0x08,0xe2 = and r7, r8, #0x28, #2 +0x28,0x71,0x08,0xe2 = and r7, r8, #0x28, #2 +0x28,0x71,0x08,0xe2 = and r7, r8, #0x28, #2 +0x06,0xa0,0x01,0xe0 = and r10, r1, r6 +0x06,0xa5,0x01,0xe0 = and r10, r1, r6, lsl #0xa +0x26,0xa5,0x01,0xe0 = and r10, r1, r6, lsr #0xa +0x26,0xa5,0x01,0xe0 = and r10, r1, r6, lsr #0xa +0x46,0xa5,0x01,0xe0 = and r10, r1, r6, asr #0xa +0x66,0xa5,0x01,0xe0 = and r10, r1, r6, ror #0xa +0x18,0x62,0x07,0xe0 = and r6, r7, r8, lsl r2 +0x38,0x62,0x07,0xe0 = and r6, r7, r8, lsr r2 +0x58,0x62,0x07,0xe0 = and r6, r7, r8, asr r2 +0x78,0x62,0x07,0xe0 = and r6, r7, r8, ror r2 +0x66,0xa0,0x01,0xe0 = and r10, r1, r6, rrx +0x02,0x21,0xc3,0xe3 = bic r2, r3, #-0x80000000 +0x02,0xd1,0xcd,0xe3 = bic sp, sp, #-0x80000000 +0x02,0xf1,0xcf,0xe3 = bic pc, pc, #-0x80000000 +0x0f,0x10,0x01,0xe2 = and r1, r1, #0xf +0x0f,0x10,0x01,0xe2 = and r1, r1, #0xf +0x0f,0x10,0x01,0xe2 = and r1, r1, #0xf +0x0e,0x10,0xc1,0xe3 = bic r1, r1, #0xe +0xff,0x78,0x07,0xe2 = and r7, r7, #0xff0000 +0x2a,0x71,0x07,0xe2 = and r7, r7, #-0x7ffffff6 +0x2a,0x71,0x07,0xe2 = and r7, r7, #-0x7ffffff6 +0x28,0x71,0x07,0xe2 = and r7, r7, #0x28, #2 +0x28,0x71,0x07,0xe2 = and r7, r7, #0x28, #2 +0x28,0x71,0x07,0xe2 = and r7, r7, #0x28, #2 +0x28,0x71,0x07,0xe2 = and r7, r7, #0x28, #2 +0x01,0xa0,0x0a,0xe0 = and r10, r10, r1 +0x01,0xa5,0x0a,0xe0 = and r10, r10, r1, lsl #0xa +0x21,0xa5,0x0a,0xe0 = and r10, r10, r1, lsr #0xa +0x21,0xa5,0x0a,0xe0 = and r10, r10, r1, lsr #0xa +0x41,0xa5,0x0a,0xe0 = and r10, r10, r1, asr #0xa +0x61,0xa5,0x0a,0xe0 = and r10, r10, r1, ror #0xa +0x17,0x62,0x06,0xe0 = and r6, r6, r7, lsl r2 +0x37,0x62,0x06,0xe0 = and r6, r6, r7, lsr r2 +0x57,0x62,0x06,0xe0 = and r6, r6, r7, asr r2 +0x77,0x62,0x06,0xe0 = and r6, r6, r7, ror r2 +0x61,0xa0,0x0a,0xe0 = and r10, r10, r1, rrx +0x22,0x30,0x01,0xe0 = and r3, r1, r2, lsr #0x20 +0x42,0x30,0x01,0xe0 = and r3, r1, r2, asr #0x20 +0x44,0x20,0xa0,0xe1 = asr r2, r4, #0x20 +0x44,0x21,0xa0,0xe1 = asr r2, r4, #2 +0x04,0x20,0xa0,0xe1 = mov r2, r4 +0x44,0x41,0xa0,0xe1 = asr r4, r4, #2 +0x9f,0x51,0xd3,0xe7 = bfc r5, #3, #0x11 +0x9f,0x51,0xd3,0x37 = bfclo r5, #3, #0x11 +0x92,0x51,0xd3,0xe7 = bfi r5, r2, #3, #0x11 +0x92,0x51,0xd3,0x17 = bfine r5, r2, #3, #0x11 +0x0f,0xa0,0xc1,0xe3 = bic r10, r1, #0xf +0x0f,0xa0,0xc1,0xe3 = bic r10, r1, #0xf +0x0f,0xa0,0xc1,0xe3 = bic r10, r1, #0xf +0x0e,0xa0,0x01,0xe2 = and r10, r1, #0xe +0xff,0x78,0xc8,0xe3 = bic r7, r8, #0xff0000 +0x2a,0x71,0xc8,0xe3 = bic r7, r8, #-0x7ffffff6 +0x2a,0x71,0xc8,0xe3 = bic r7, r8, #-0x7ffffff6 +0x28,0x71,0xc8,0xe3 = bic r7, r8, #0x28, #2 +0x28,0x71,0xc8,0xe3 = bic r7, r8, #0x28, #2 +0x28,0x71,0xc8,0xe3 = bic r7, r8, #0x28, #2 +0x06,0xa0,0xc1,0xe1 = bic r10, r1, r6 +0x06,0xa5,0xc1,0xe1 = bic r10, r1, r6, lsl #0xa +0x26,0xa5,0xc1,0xe1 = bic r10, r1, r6, lsr #0xa +0x26,0xa5,0xc1,0xe1 = bic r10, r1, r6, lsr #0xa +0x46,0xa5,0xc1,0xe1 = bic r10, r1, r6, asr #0xa +0x66,0xa5,0xc1,0xe1 = bic r10, r1, r6, ror #0xa +0x18,0x62,0xc7,0xe1 = bic r6, r7, r8, lsl r2 +0x38,0x62,0xc7,0xe1 = bic r6, r7, r8, lsr r2 +0x58,0x62,0xc7,0xe1 = bic r6, r7, r8, asr r2 +0x78,0x62,0xc7,0xe1 = bic r6, r7, r8, ror r2 +0x66,0xa0,0xc1,0xe1 = bic r10, r1, r6, rrx +0x02,0x21,0x03,0xe2 = and r2, r3, #-0x80000000 +0x02,0xd1,0x0d,0xe2 = and sp, sp, #-0x80000000 +0x02,0xf1,0x0f,0xe2 = and pc, pc, #-0x80000000 +0x0f,0x10,0xc1,0xe3 = bic r1, r1, #0xf +0x0f,0x10,0xc1,0xe3 = bic r1, r1, #0xf +0x0f,0x10,0xc1,0xe3 = bic r1, r1, #0xf +0x0e,0x10,0x01,0xe2 = and r1, r1, #0xe +0xff,0x78,0xc7,0xe3 = bic r7, r7, #0xff0000 +0x2a,0x71,0xc7,0xe3 = bic r7, r7, #-0x7ffffff6 +0x2a,0x71,0xc7,0xe3 = bic r7, r7, #-0x7ffffff6 +0x28,0x71,0xc7,0xe3 = bic r7, r7, #0x28, #2 +0x28,0x71,0xc7,0xe3 = bic r7, r7, #0x28, #2 +0x28,0x71,0xc7,0xe3 = bic r7, r7, #0x28, #2 +0x28,0x71,0xc7,0xe3 = bic r7, r7, #0x28, #2 +0x01,0xa0,0xca,0xe1 = bic r10, r10, r1 +0x01,0xa5,0xca,0xe1 = bic r10, r10, r1, lsl #0xa +0x21,0xa5,0xca,0xe1 = bic r10, r10, r1, lsr #0xa +0x21,0xa5,0xca,0xe1 = bic r10, r10, r1, lsr #0xa +0x41,0xa5,0xca,0xe1 = bic r10, r10, r1, asr #0xa +0x61,0xa5,0xca,0xe1 = bic r10, r10, r1, ror #0xa +0x17,0x62,0xc6,0xe1 = bic r6, r6, r7, lsl r2 +0x37,0x62,0xc6,0xe1 = bic r6, r6, r7, lsr r2 +0x57,0x62,0xc6,0xe1 = bic r6, r6, r7, asr r2 +0x77,0x62,0xc6,0xe1 = bic r6, r6, r7, ror r2 +0x61,0xa0,0xca,0xe1 = bic r10, r10, r1, rrx +0x22,0x30,0xc1,0xe1 = bic r3, r1, r2, lsr #0x20 +0x42,0x30,0xc1,0xe1 = bic r3, r1, r2, asr #0x20 +0x7a,0x00,0x20,0xe1 = bkpt #0xa +0x7f,0xff,0x2f,0xe1 = bkpt #0xffff +0x27,0x3b,0x6d,0x9b = blls #0x1b4ec9c +0xa0,0xb0,0x7b,0xfa = blx #0x1eec280 +0x50,0xd8,0x3d,0xfa = blx #0xf76140 +0x32,0xff,0x2f,0xe1 = blx r2 +0x32,0xff,0x2f,0x11 = blxne r2 +0x12,0xff,0x2f,0xe1 = bx r2 +0x12,0xff,0x2f,0x11 = bxne r2 +0x22,0xff,0x2f,0xe1 = bxj r2 +0x22,0xff,0x2f,0x11 = bxjne r2 +0x81,0x17,0x11,0xee = cdp p7, #1, c1, c1, c1, #4 +0x81,0x17,0x11,0xfe = cdp2 p7, #1, c1, c1, c1, #4 +0xe0,0x6c,0x0c,0xfe = cdp2 p12, #0, c6, c12, c0, #7 +0x81,0x17,0x11,0x1e = cdpne p7, #1, c1, c1, c1, #4 +0x1f,0xf0,0x7f,0xf5 = clrex +0x12,0x1f,0x6f,0xe1 = clz r1, r2 +0x12,0x1f,0x6f,0x01 = clzeq r1, r2 +0x0f,0x00,0x71,0xe3 = cmn r1, #0xf +0x0f,0x00,0x71,0xe3 = cmn r1, #0xf +0x0f,0x00,0x71,0xe3 = cmn r1, #0xf +0x0f,0x00,0x51,0xe3 = cmp r1, #0xf +0xff,0x08,0x77,0xe3 = cmn r7, #0xff0000 +0x2a,0x01,0x77,0xe3 = cmn r7, #-0x7ffffff6 +0x2a,0x01,0x77,0xe3 = cmn r7, #-0x7ffffff6 +0x28,0x01,0x77,0xe3 = cmn r7, #0x28, #2 +0x28,0x01,0x77,0xe3 = cmn r7, #0x28, #2 +0x28,0x01,0x77,0xe3 = cmn r7, #0x28, #2 +0x28,0x01,0x77,0xe3 = cmn r7, #0x28, #2 +0x06,0x00,0x71,0xe1 = cmn r1, r6 +0x06,0x05,0x71,0xe1 = cmn r1, r6, lsl #0xa +0x26,0x05,0x71,0xe1 = cmn r1, r6, lsr #0xa +0x26,0x05,0x7d,0xe1 = cmn sp, r6, lsr #0xa +0x46,0x05,0x71,0xe1 = cmn r1, r6, asr #0xa +0x66,0x05,0x71,0xe1 = cmn r1, r6, ror #0xa +0x18,0x02,0x77,0xe1 = cmn r7, r8, lsl r2 +0x38,0x02,0x7d,0xe1 = cmn sp, r8, lsr r2 +0x58,0x02,0x77,0xe1 = cmn r7, r8, asr r2 +0x78,0x02,0x77,0xe1 = cmn r7, r8, ror r2 +0x66,0x00,0x71,0xe1 = cmn r1, r6, rrx +0x0f,0x00,0x51,0xe3 = cmp r1, #0xf +0x0f,0x00,0x51,0xe3 = cmp r1, #0xf +0x0f,0x00,0x51,0xe3 = cmp r1, #0xf +0x0f,0x00,0x71,0xe3 = cmn r1, #0xf +0xff,0x08,0x57,0xe3 = cmp r7, #0xff0000 +0x2a,0x01,0x57,0xe3 = cmp r7, #-0x7ffffff6 +0x2a,0x01,0x57,0xe3 = cmp r7, #-0x7ffffff6 +0x28,0x01,0x57,0xe3 = cmp r7, #0x28, #2 +0x28,0x01,0x57,0xe3 = cmp r7, #0x28, #2 +0x28,0x01,0x57,0xe3 = cmp r7, #0x28, #2 +0x28,0x01,0x57,0xe3 = cmp r7, #0x28, #2 +0x06,0x00,0x51,0xe1 = cmp r1, r6 +0x06,0x05,0x51,0xe1 = cmp r1, r6, lsl #0xa +0x26,0x05,0x51,0xe1 = cmp r1, r6, lsr #0xa +0x26,0x05,0x5d,0xe1 = cmp sp, r6, lsr #0xa +0x46,0x05,0x51,0xe1 = cmp r1, r6, asr #0xa +0x66,0x05,0x51,0xe1 = cmp r1, r6, ror #0xa +0x18,0x02,0x57,0xe1 = cmp r7, r8, lsl r2 +0x38,0x02,0x5d,0xe1 = cmp sp, r8, lsr r2 +0x58,0x02,0x57,0xe1 = cmp r7, r8, asr r2 +0x78,0x02,0x57,0xe1 = cmp r7, r8, ror r2 +0x66,0x00,0x51,0xe1 = cmp r1, r6, rrx +0x02,0x00,0x70,0xe3 = cmn r0, #2 +0x00,0x00,0x5e,0xe3 = cmp lr, #0 +0xc0,0x01,0x08,0xf1 = cpsie aif +0xc0,0x01,0x08,0xf1 = cpsie aif +0x0f,0x00,0x02,0xf1 = cps #0xf +0xca,0x00,0x0e,0xf1 = cpsid if, #0xa +0xf0,0xf0,0x20,0xe3 = dbg #0 +0xf5,0xf0,0x20,0xe3 = dbg #5 +0xff,0xf0,0x20,0xe3 = dbg #0xf +0x5f,0xf0,0x7f,0xf5 = dmb sy +0x5e,0xf0,0x7f,0xf5 = dmb st +0x5d,0xf0,0x7f,0xf5 = dmb #0xd +0x5c,0xf0,0x7f,0xf5 = dmb #0xc +0x5b,0xf0,0x7f,0xf5 = dmb ish +0x5a,0xf0,0x7f,0xf5 = dmb ishst +0x59,0xf0,0x7f,0xf5 = dmb #0x9 +0x58,0xf0,0x7f,0xf5 = dmb #0x8 +0x57,0xf0,0x7f,0xf5 = dmb nsh +0x56,0xf0,0x7f,0xf5 = dmb nshst +0x55,0xf0,0x7f,0xf5 = dmb #0x5 +0x54,0xf0,0x7f,0xf5 = dmb #0x4 +0x53,0xf0,0x7f,0xf5 = dmb osh +0x52,0xf0,0x7f,0xf5 = dmb oshst +0x51,0xf0,0x7f,0xf5 = dmb #0x1 +0x50,0xf0,0x7f,0xf5 = dmb #0x0 +0x5f,0xf0,0x7f,0xf5 = dmb sy +0x5e,0xf0,0x7f,0xf5 = dmb st +0x5b,0xf0,0x7f,0xf5 = dmb ish +0x5b,0xf0,0x7f,0xf5 = dmb ish +0x5a,0xf0,0x7f,0xf5 = dmb ishst +0x5a,0xf0,0x7f,0xf5 = dmb ishst +0x57,0xf0,0x7f,0xf5 = dmb nsh +0x57,0xf0,0x7f,0xf5 = dmb nsh +0x56,0xf0,0x7f,0xf5 = dmb nshst +0x56,0xf0,0x7f,0xf5 = dmb nshst +0x53,0xf0,0x7f,0xf5 = dmb osh +0x52,0xf0,0x7f,0xf5 = dmb oshst +0x5f,0xf0,0x7f,0xf5 = dmb sy +0x4f,0xf0,0x7f,0xf5 = dsb sy +0x4e,0xf0,0x7f,0xf5 = dsb st +0x4d,0xf0,0x7f,0xf5 = dsb #0xd +0x4c,0xf0,0x7f,0xf5 = dsb #0xc +0x4b,0xf0,0x7f,0xf5 = dsb ish +0x4a,0xf0,0x7f,0xf5 = dsb ishst +0x49,0xf0,0x7f,0xf5 = dsb #0x9 +0x48,0xf0,0x7f,0xf5 = dsb #0x8 +0x47,0xf0,0x7f,0xf5 = dsb nsh +0x46,0xf0,0x7f,0xf5 = dsb nshst +0x45,0xf0,0x7f,0xf5 = dsb #0x5 +0x44,0xf0,0x7f,0xf5 = pssbb +0x43,0xf0,0x7f,0xf5 = dsb osh +0x42,0xf0,0x7f,0xf5 = dsb oshst +0x41,0xf0,0x7f,0xf5 = dsb #0x1 +0x40,0xf0,0x7f,0xf5 = ssbb +0x48,0xf0,0x7f,0xf5 = dsb #0x8 +0x47,0xf0,0x7f,0xf5 = dsb nsh +0x4f,0xf0,0x7f,0xf5 = dsb sy +0x4e,0xf0,0x7f,0xf5 = dsb st +0x4b,0xf0,0x7f,0xf5 = dsb ish +0x4b,0xf0,0x7f,0xf5 = dsb ish +0x4a,0xf0,0x7f,0xf5 = dsb ishst +0x4a,0xf0,0x7f,0xf5 = dsb ishst +0x47,0xf0,0x7f,0xf5 = dsb nsh +0x47,0xf0,0x7f,0xf5 = dsb nsh +0x46,0xf0,0x7f,0xf5 = dsb nshst +0x46,0xf0,0x7f,0xf5 = dsb nshst +0x43,0xf0,0x7f,0xf5 = dsb osh +0x42,0xf0,0x7f,0xf5 = dsb oshst +0x4f,0xf0,0x7f,0xf5 = dsb sy +0x4f,0xf0,0x7f,0xf5 = dsb sy +0x42,0xf0,0x7f,0xf5 = dsb oshst +0x0f,0x4a,0x25,0xe2 = eor r4, r5, #0xf000 +0x0f,0x4a,0x25,0xe2 = eor r4, r5, #0xf000 +0x0f,0x4a,0x25,0xe2 = eor r4, r5, #0xf000 +0xff,0x78,0x28,0xe2 = eor r7, r8, #0xff0000 +0x2a,0x71,0x28,0xe2 = eor r7, r8, #-0x7ffffff6 +0x2a,0x71,0x28,0xe2 = eor r7, r8, #-0x7ffffff6 +0x28,0x71,0x28,0xe2 = eor r7, r8, #0x28, #2 +0x28,0x71,0x28,0xe2 = eor r7, r8, #0x28, #2 +0x28,0x71,0x28,0xe2 = eor r7, r8, #0x28, #2 +0x28,0x71,0x28,0xe2 = eor r7, r8, #0x28, #2 +0x06,0x40,0x25,0xe0 = eor r4, r5, r6 +0x86,0x42,0x25,0xe0 = eor r4, r5, r6, lsl #5 +0xa6,0x42,0x25,0xe0 = eor r4, r5, r6, lsr #5 +0xa6,0x42,0x25,0xe0 = eor r4, r5, r6, lsr #5 +0xc6,0x42,0x25,0xe0 = eor r4, r5, r6, asr #5 +0xe6,0x42,0x25,0xe0 = eor r4, r5, r6, ror #5 +0x18,0x69,0x27,0xe0 = eor r6, r7, r8, lsl r9 +0x38,0x69,0x27,0xe0 = eor r6, r7, r8, lsr r9 +0x58,0x69,0x27,0xe0 = eor r6, r7, r8, asr r9 +0x78,0x69,0x27,0xe0 = eor r6, r7, r8, ror r9 +0x66,0x40,0x25,0xe0 = eor r4, r5, r6, rrx +0x0f,0x5a,0x25,0xe2 = eor r5, r5, #0xf000 +0x0f,0x5a,0x25,0xe2 = eor r5, r5, #0xf000 +0x0f,0x5a,0x25,0xe2 = eor r5, r5, #0xf000 +0xff,0x78,0x27,0xe2 = eor r7, r7, #0xff0000 +0x2a,0x71,0x27,0xe2 = eor r7, r7, #-0x7ffffff6 +0x2a,0x71,0x27,0xe2 = eor r7, r7, #-0x7ffffff6 +0x28,0x71,0x27,0xe2 = eor r7, r7, #0x28, #2 +0x28,0x71,0x27,0xe2 = eor r7, r7, #0x28, #2 +0x28,0x71,0x27,0xe2 = eor r7, r7, #0x28, #2 +0x28,0x71,0x27,0xe2 = eor r7, r7, #0x28, #2 +0x05,0x40,0x24,0xe0 = eor r4, r4, r5 +0x85,0x42,0x24,0xe0 = eor r4, r4, r5, lsl #5 +0xa5,0x42,0x24,0xe0 = eor r4, r4, r5, lsr #5 +0xa5,0x42,0x24,0xe0 = eor r4, r4, r5, lsr #5 +0xc5,0x42,0x24,0xe0 = eor r4, r4, r5, asr #5 +0xe5,0x42,0x24,0xe0 = eor r4, r4, r5, ror #5 +0x17,0x69,0x26,0xe0 = eor r6, r6, r7, lsl r9 +0x37,0x69,0x26,0xe0 = eor r6, r6, r7, lsr r9 +0x57,0x69,0x26,0xe0 = eor r6, r6, r7, asr r9 +0x77,0x69,0x26,0xe0 = eor r6, r6, r7, ror r9 +0x65,0x40,0x24,0xe0 = eor r4, r4, r5, rrx +0x22,0x30,0x21,0xe0 = eor r3, r1, r2, lsr #0x20 +0x42,0x30,0x21,0xe0 = eor r3, r1, r2, asr #0x20 +0x6f,0xf0,0x7f,0xf5 = isb sy +0x6f,0xf0,0x7f,0xf5 = isb sy +0x6f,0xf0,0x7f,0xf5 = isb sy +0x61,0xf0,0x7f,0xf5 = isb #0x1 +0x01,0x80,0x91,0xfd = ldc2 p0, c8, [r1, #4] +0x00,0x71,0x92,0xfd = ldc2 p1, c7, [r2] +0x38,0x62,0x13,0xfd = ldc2 p2, c6, [r3, #-0xe0] +0x1e,0x53,0x34,0xfd = ldc2 p3, c5, [r4, #-0x78]! +0x04,0x44,0xb5,0xfc = ldc2 p4, c4, [r5], #0x10 +0x12,0x35,0x36,0xfc = ldc2 p5, c3, [r6], #-0x48 +0x01,0x26,0xd7,0xfd = ldc2l p6, c2, [r7, #4] +0x00,0x17,0xd8,0xfd = ldc2l p7, c1, [r8] +0x38,0x08,0x59,0xfd = ldc2l p8, c0, [r9, #-0xe0] +0x1e,0x19,0x7a,0xfd = ldc2l p9, c1, [r10, #-0x78]! +0x04,0x20,0xfb,0xfc = ldc2l p0, c2, [r11], #0x10 +0x12,0x31,0x7c,0xfc = ldc2l p1, c3, [r12], #-0x48 +0x01,0x4c,0x90,0xed = ldc p12, c4, [r0, #4] +0x00,0x5d,0x91,0xed = ldc p13, c5, [r1] +0x38,0x6e,0x12,0xed = ldc p14, c6, [r2, #-0xe0] +0x1e,0x7f,0x33,0xed = ldc p15, c7, [r3, #-0x78]! +0x04,0x85,0xb4,0xec = ldc p5, c8, [r4], #0x10 +0x12,0x94,0x35,0xec = ldc p4, c9, [r5], #-0x48 +0x01,0xa3,0xd6,0xed = ldcl p3, c10, [r6, #4] +0x00,0xb2,0xd7,0xed = ldcl p2, c11, [r7] +0x38,0xc1,0x58,0xed = ldcl p1, c12, [r8, #-0xe0] +0x1e,0xd0,0x79,0xed = ldcl p0, c13, [r9, #-0x78]! +0x04,0xe6,0xfa,0xec = ldcl p6, c14, [r10], #0x10 +0x12,0xf7,0x7b,0xec = ldcl p7, c15, [r11], #-0x48 +0x01,0x4c,0x90,0x3d = ldclo p12, c4, [r0, #4] +0x00,0x5d,0x91,0x8d = ldchi p13, c5, [r1] +0x38,0x6e,0x12,0x2d = ldchs p14, c6, [r2, #-0xe0] +0x1e,0x7f,0x33,0x3d = ldclo p15, c7, [r3, #-0x78]! +0x04,0x85,0xb4,0x0c = ldceq p5, c8, [r4], #0x10 +0x12,0x94,0x35,0xcc = ldcgt p4, c9, [r5], #-0x48 +0x01,0xa3,0xd6,0xbd = ldcllt p3, c10, [r6, #4] +0x00,0xb2,0xd7,0xad = ldclge p2, c11, [r7] +0x38,0xc1,0x58,0xdd = ldclle p1, c12, [r8, #-0xe0] +0x1e,0xd0,0x79,0x1d = ldclne p0, c13, [r9, #-0x78]! +0x04,0xe6,0xfa,0x0c = ldcleq p6, c14, [r10], #0x10 +0x12,0xf7,0x7b,0x8c = ldclhi p7, c15, [r11], #-0x48 +0x19,0x82,0x91,0xfc = ldc2 p2, c8, [r1], {25} +0x7a,0x20,0x92,0xe8 = ldm r2, {r1, r3, r4, r5, r6, sp} +0x7a,0x20,0x92,0xe8 = ldm r2, {r1, r3, r4, r5, r6, sp} +0x7a,0x20,0x92,0xe9 = ldmib r2, {r1, r3, r4, r5, r6, sp} +0x7a,0x20,0x12,0xe8 = ldmda r2, {r1, r3, r4, r5, r6, sp} +0x7a,0x20,0x12,0xe9 = ldmdb r2, {r1, r3, r4, r5, r6, sp} +0x7a,0x20,0x92,0xe8 = ldm r2, {r1, r3, r4, r5, r6, sp} +0x7a,0x20,0xb2,0xe8 = ldm r2!, {r1, r3, r4, r5, r6, sp} +0x7a,0x20,0xb2,0xe9 = ldmib r2!, {r1, r3, r4, r5, r6, sp} +0x7a,0x20,0x32,0xe8 = ldmda r2!, {r1, r3, r4, r5, r6, sp} +0x7a,0x20,0x32,0xe9 = ldmdb r2!, {r1, r3, r4, r5, r6, sp} +0x05,0x40,0xd0,0xe8 = ldm r0, {r0, r2, lr} ^ +0x0f,0x80,0xfd,0xe8 = ldm sp!, {r0, r1, r2, r3, pc} ^ +0x9f,0x3f,0xd4,0xe1 = ldrexb r3, [r4] +0x9f,0x2f,0xf5,0xe1 = ldrexh r2, [r5] +0x9f,0x1f,0x97,0xe1 = ldrex r1, [r7] +0x9f,0x6f,0xb8,0xe1 = ldrexd r6, r7, [r8] +0xb0,0x80,0x7b,0x80 = ldrhthi r8, [r11], #-0 +0xb0,0x80,0xfb,0x80 = ldrhthi r8, [r11], #0 +0x84,0x2f,0xa0,0xe1 = lsl r2, r4, #0x1f +0x84,0x20,0xa0,0xe1 = lsl r2, r4, #1 +0x04,0x20,0xa0,0xe1 = mov r2, r4 +0x84,0x40,0xa0,0xe1 = lsl r4, r4, #1 +0x24,0x20,0xa0,0xe1 = lsr r2, r4, #0x20 +0x24,0x21,0xa0,0xe1 = lsr r2, r4, #2 +0x04,0x20,0xa0,0xe1 = mov r2, r4 +0x24,0x41,0xa0,0xe1 = lsr r4, r4, #2 +0x91,0x57,0x21,0xee = mcr p7, #1, r5, c1, c1, #4 +0x91,0x57,0x21,0xfe = mcr2 p7, #1, r5, c1, c1, #4 +0x91,0x57,0x21,0xee = mcr p7, #1, r5, c1, c1, #4 +0x91,0x57,0x21,0xfe = mcr2 p7, #1, r5, c1, c1, #4 +0x91,0x57,0x21,0x9e = mcrls p7, #1, r5, c1, c1, #4 +0x91,0x57,0x21,0x9e = mcrls p7, #1, r5, c1, c1, #4 +0xf1,0x57,0x44,0xec = mcrr p7, #0xf, r5, r4, c1 +0xf1,0x57,0x44,0xfc = mcrr2 p7, #0xf, r5, r4, c1 +0xf1,0x57,0x44,0xec = mcrr p7, #0xf, r5, r4, c1 +0xf1,0x57,0x44,0xfc = mcrr2 p7, #0xf, r5, r4, c1 +0xf1,0x57,0x44,0xcc = mcrrgt p7, #0xf, r5, r4, c1 +0xf1,0x57,0x44,0xcc = mcrrgt p7, #0xf, r5, r4, c1 +0x92,0x43,0x21,0xe0 = mla r1, r2, r3, r4 +0x92,0x43,0x31,0xe0 = mlas r1, r2, r3, r4 +0x92,0x43,0x21,0x10 = mlane r1, r2, r3, r4 +0x92,0x43,0x31,0x10 = mlasne r1, r2, r3, r4 +0x95,0x36,0x62,0xe0 = mls r2, r5, r6, r3 +0x95,0x36,0x62,0x10 = mlsne r2, r5, r6, r3 +0x07,0x30,0xa0,0xe3 = mov r3, #7 +0x07,0x30,0xa0,0xe3 = mov r3, #7 +0x07,0x30,0xa0,0xe3 = mov r3, #7 +0x06,0x30,0xe0,0xe3 = mvn r3, #6 +0xff,0x4e,0xa0,0xe3 = mov r4, #0xff0 +0xff,0x58,0xa0,0xe3 = mov r5, #0xff0000 +0x2a,0x70,0xa0,0xe3 = mov r7, #0x2a +0x2a,0x75,0xa0,0xe3 = mov r7, #0xa800000 +0xff,0x78,0xa0,0xe3 = mov r7, #0xff0000 +0x2a,0x71,0xa0,0xe3 = mov r7, #-0x7ffffff6 +0x2a,0x71,0xa0,0xe3 = mov r7, #-0x7ffffff6 +0x2a,0xf1,0xa0,0xe3 = mov pc, #0x8000000a +0x00,0x71,0xa0,0xe3 = mov r7, #0, #2 +0x28,0x71,0xa0,0xe3 = mov r7, #0x28, #2 +0x28,0x71,0xa0,0xe3 = mov r7, #0x28, #2 +0x28,0x71,0xa0,0xe3 = mov r7, #0x28, #2 +0x28,0x71,0xa0,0xe3 = mov r7, #0x28, #2 +0x2a,0x7f,0xa0,0xe3 = mov r7, #0x2a, #0x1e +0xff,0x6f,0x0f,0xe3 = movw r6, #0xffff +0xff,0x9f,0x0f,0xe3 = movw r9, #0xffff +0x07,0x30,0xb0,0xe3 = movs r3, #7 +0xff,0x4e,0xa0,0x03 = moveq r4, #0xff0 +0xff,0x58,0xb0,0x03 = movseq r5, #0xff0000 +0x03,0x20,0xa0,0xe1 = mov r2, r3 +0x03,0x20,0xb0,0xe1 = movs r2, r3 +0x03,0x20,0xa0,0x01 = moveq r2, r3 +0x03,0x20,0xb0,0x01 = movseq r2, r3 +0x08,0xc0,0xa0,0xe1 = mov r12, r8 +0x03,0x20,0xa0,0xe1 = mov r2, r3 +0x08,0xc0,0xa0,0xe1 = mov r12, r8 +0x03,0x20,0xa0,0xe1 = mov r2, r3 +0x08,0xc0,0xa0,0xe1 = mov r12, r8 +0x03,0x20,0xa0,0xe1 = mov r2, r3 +0x08,0xc0,0xa0,0xe1 = mov r12, r8 +0x03,0x20,0xa0,0xe1 = mov r2, r3 +0x07,0x30,0x40,0xe3 = movt r3, #7 +0xff,0x6f,0x4f,0xe3 = movt r6, #0xffff +0xf0,0x4f,0x40,0x03 = movteq r4, #0xff0 +0x92,0x1e,0x11,0xee = mrc p14, #0, r1, c1, c2, #4 +0xd6,0xff,0xff,0xee = mrc p15, #7, apsr_nzcv, c15, c6, #6 +0x92,0x1e,0x11,0xfe = mrc2 p14, #0, r1, c1, c2, #4 +0x30,0xf9,0xff,0xfe = mrc2 p9, #7, apsr_nzcv, c15, c0, #1 +0x92,0x1e,0x11,0xee = mrc p14, #0, r1, c1, c2, #4 +0xd6,0xff,0xff,0xee = mrc p15, #7, apsr_nzcv, c15, c6, #6 +0x92,0x1e,0x11,0xfe = mrc2 p14, #0, r1, c1, c2, #4 +0x30,0xf9,0xff,0xfe = mrc2 p9, #7, apsr_nzcv, c15, c0, #1 +0xd6,0xff,0xff,0x0e = mrceq p15, #7, apsr_nzcv, c15, c6, #6 +0xd6,0xff,0xff,0x0e = mrceq p15, #7, apsr_nzcv, c15, c6, #6 +0x11,0x57,0x54,0xec = mrrc p7, #1, r5, r4, c1 +0x11,0x57,0x54,0xfc = mrrc2 p7, #1, r5, r4, c1 +0x11,0x57,0x54,0xec = mrrc p7, #1, r5, r4, c1 +0x11,0x57,0x54,0xfc = mrrc2 p7, #1, r5, r4, c1 +0x11,0x57,0x54,0x3c = mrrclo p7, #1, r5, r4, c1 +0x11,0x57,0x54,0x3c = mrrclo p7, #1, r5, r4, c1 +0x00,0x80,0x0f,0xe1 = mrs r8, apsr +0x00,0x80,0x0f,0xe1 = mrs r8, apsr +0x00,0x80,0x4f,0xe1 = mrs r8, spsr +0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5 +0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5 +0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5 +0x05,0xf0,0x24,0xe3 = msr APSR_g, #5 +0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5 +0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5 +0x05,0xf0,0x2c,0xe3 = msr APSR_nzcvqg, #5 +0x05,0xf0,0x29,0xe3 = msr CPSR_fc, #5 +0x05,0xf0,0x21,0xe3 = msr CPSR_c, #5 +0x05,0xf0,0x22,0xe3 = msr CPSR_x, #5 +0x05,0xf0,0x29,0xe3 = msr CPSR_fc, #5 +0x05,0xf0,0x29,0xe3 = msr CPSR_fc, #5 +0x05,0xf0,0x2e,0xe3 = msr CPSR_fsx, #5 +0x05,0xf0,0x69,0xe3 = msr SPSR_fc, #5 +0x05,0xf0,0x6f,0xe3 = msr SPSR_fsxc, #5 +0x05,0xf0,0x2f,0xe3 = msr CPSR_fsxc, #5 +0xff,0xf8,0x2c,0xe3 = msr APSR_nzcvqg, #0xff0000 +0x2a,0xf1,0x28,0xe3 = msr APSR_nzcvq, #0x8000000a +0x2a,0xf1,0x2c,0xe3 = msr APSR_nzcvqg, #0x8000000a +0x28,0xf1,0x6f,0xe3 = msr SPSR_fsxc, #0x28, #2 +0x28,0xf1,0x6f,0xe3 = msr SPSR_fsxc, #0x28, #2 +0x28,0xf1,0x6f,0xe3 = msr SPSR_fsxc, #0x28, #2 +0x28,0xf1,0x6f,0xe3 = msr SPSR_fsxc, #0x28, #2 +0x00,0xf0,0x28,0xe1 = msr APSR_nzcvq, r0 +0x00,0xf0,0x24,0xe1 = msr APSR_g, r0 +0x00,0xf0,0x28,0xe1 = msr APSR_nzcvq, r0 +0x00,0xf0,0x28,0xe1 = msr APSR_nzcvq, r0 +0x00,0xf0,0x2c,0xe1 = msr APSR_nzcvqg, r0 +0x00,0xf0,0x29,0xe1 = msr CPSR_fc, r0 +0x00,0xf0,0x21,0xe1 = msr CPSR_c, r0 +0x00,0xf0,0x22,0xe1 = msr CPSR_x, r0 +0x00,0xf0,0x29,0xe1 = msr CPSR_fc, r0 +0x00,0xf0,0x29,0xe1 = msr CPSR_fc, r0 +0x00,0xf0,0x2e,0xe1 = msr CPSR_fsx, r0 +0x00,0xf0,0x69,0xe1 = msr SPSR_fc, r0 +0x00,0xf0,0x6f,0xe1 = msr SPSR_fsxc, r0 +0x00,0xf0,0x2f,0xe1 = msr CPSR_fsxc, r0 +0x96,0x07,0x05,0xe0 = mul r5, r6, r7 +0x96,0x07,0x15,0xe0 = muls r5, r6, r7 +0x96,0x07,0x05,0xc0 = mulgt r5, r6, r7 +0x96,0x07,0x15,0xd0 = mulsle r5, r6, r7 +0x07,0x30,0xe0,0xe3 = mvn r3, #7 +0x07,0x30,0xe0,0xe3 = mvn r3, #7 +0x07,0x30,0xe0,0xe3 = mvn r3, #7 +0x06,0x30,0xa0,0xe3 = mov r3, #6 +0xff,0x70,0xe0,0xe3 = mvn r7, #0xff +0xff,0x4e,0xe0,0xe3 = mvn r4, #0xff0 +0xff,0x58,0xe0,0xe3 = mvn r5, #0xff0000 +0xff,0x78,0xe0,0xe3 = mvn r7, #0xff0000 +0x2a,0x71,0xe0,0xe3 = mvn r7, #-0x7ffffff6 +0x2a,0x71,0xe0,0xe3 = mvn r7, #-0x7ffffff6 +0x28,0x71,0xe0,0xe3 = mvn r7, #0x28, #2 +0x28,0x71,0xe0,0xe3 = mvn r7, #0x28, #2 +0x28,0x71,0xe0,0xe3 = mvn r7, #0x28, #2 +0x28,0x71,0xe0,0xe3 = mvn r7, #0x28, #2 +0x07,0x30,0xf0,0xe3 = mvns r3, #7 +0xff,0x4e,0xe0,0x03 = mvneq r4, #0xff0 +0xff,0x58,0xf0,0x03 = mvnseq r5, #0xff0000 +0x03,0x20,0xe0,0xe1 = mvn r2, r3 +0x03,0x20,0xf0,0xe1 = mvns r2, r3 +0x86,0x59,0xe0,0xe1 = mvn r5, r6, lsl #0x13 +0xa6,0x54,0xe0,0xe1 = mvn r5, r6, lsr #0x9 +0x46,0x52,0xe0,0xe1 = mvn r5, r6, asr #4 +0x66,0x53,0xe0,0xe1 = mvn r5, r6, ror #6 +0x66,0x50,0xe0,0xe1 = mvn r5, r6, rrx +0x03,0x20,0xe0,0x01 = mvneq r2, r3 +0x03,0x25,0xf0,0x01 = mvnseq r2, r3, lsl #0xa +0x16,0x57,0xe0,0xe1 = mvn r5, r6, lsl r7 +0x36,0x57,0xf0,0xe1 = mvns r5, r6, lsr r7 +0x56,0x57,0xe0,0xc1 = mvngt r5, r6, asr r7 +0x76,0x57,0xf0,0xb1 = mvnslt r5, r6, ror r7 +0x00,0x50,0x68,0xe2 = rsb r5, r8, #0 +0x00,0xf0,0x20,0xe3 = nop +0x00,0xf0,0x20,0xe3 = nop +0x00,0xf0,0x20,0xc3 = nopgt +0x0f,0x4a,0x85,0xe3 = orr r4, r5, #0xf000 +0x0f,0x4a,0x85,0xe3 = orr r4, r5, #0xf000 +0x0f,0x4a,0x85,0xe3 = orr r4, r5, #0xf000 +0xff,0x78,0x88,0xe3 = orr r7, r8, #0xff0000 +0x2a,0x71,0x88,0xe3 = orr r7, r8, #-0x7ffffff6 +0x2a,0x71,0x88,0xe3 = orr r7, r8, #-0x7ffffff6 +0x28,0x71,0x88,0xe3 = orr r7, r8, #0x28, #2 +0x28,0x71,0x88,0xe3 = orr r7, r8, #0x28, #2 +0x28,0x71,0x88,0xe3 = orr r7, r8, #0x28, #2 +0x28,0x71,0x88,0xe3 = orr r7, r8, #0x28, #2 +0x06,0x40,0x85,0xe1 = orr r4, r5, r6 +0x86,0x42,0x85,0xe1 = orr r4, r5, r6, lsl #5 +0xa6,0x42,0x85,0xe1 = orr r4, r5, r6, lsr #5 +0xa6,0x42,0x85,0xe1 = orr r4, r5, r6, lsr #5 +0xc6,0x42,0x85,0xe1 = orr r4, r5, r6, asr #5 +0xe6,0x42,0x85,0xe1 = orr r4, r5, r6, ror #5 +0x18,0x69,0x87,0xe1 = orr r6, r7, r8, lsl r9 +0x38,0x69,0x87,0xe1 = orr r6, r7, r8, lsr r9 +0x58,0x69,0x87,0xe1 = orr r6, r7, r8, asr r9 +0x78,0x69,0x87,0xe1 = orr r6, r7, r8, ror r9 +0x66,0x40,0x85,0xe1 = orr r4, r5, r6, rrx +0x0f,0x5a,0x85,0xe3 = orr r5, r5, #0xf000 +0x0f,0x5a,0x85,0xe3 = orr r5, r5, #0xf000 +0x0f,0x5a,0x85,0xe3 = orr r5, r5, #0xf000 +0xff,0x78,0x87,0xe3 = orr r7, r7, #0xff0000 +0x2a,0x71,0x87,0xe3 = orr r7, r7, #-0x7ffffff6 +0x2a,0x71,0x87,0xe3 = orr r7, r7, #-0x7ffffff6 +0x28,0x71,0x87,0xe3 = orr r7, r7, #0x28, #2 +0x28,0x71,0x87,0xe3 = orr r7, r7, #0x28, #2 +0x28,0x71,0x87,0xe3 = orr r7, r7, #0x28, #2 +0x28,0x71,0x87,0xe3 = orr r7, r7, #0x28, #2 +0x05,0x40,0x84,0xe1 = orr r4, r4, r5 +0x85,0x42,0x84,0xe1 = orr r4, r4, r5, lsl #5 +0xa5,0x42,0x84,0xe1 = orr r4, r4, r5, lsr #5 +0xa5,0x42,0x84,0xe1 = orr r4, r4, r5, lsr #5 +0xc5,0x42,0x84,0xe1 = orr r4, r4, r5, asr #5 +0xe5,0x42,0x84,0xe1 = orr r4, r4, r5, ror #5 +0x17,0x69,0x86,0xe1 = orr r6, r6, r7, lsl r9 +0x37,0x69,0x86,0xe1 = orr r6, r6, r7, lsr r9 +0x57,0x69,0x86,0xe1 = orr r6, r6, r7, asr r9 +0x77,0x69,0x86,0xe1 = orr r6, r6, r7, ror r9 +0x65,0x40,0x84,0xe1 = orr r4, r4, r5, rrx +0x0f,0x4a,0x95,0x03 = orrseq r4, r5, #0xf000 +0x06,0x40,0x85,0x11 = orrne r4, r5, r6 +0x86,0x42,0x95,0x01 = orrseq r4, r5, r6, lsl #5 +0x78,0x69,0x87,0x31 = orrlo r6, r7, r8, ror r9 +0x66,0x40,0x95,0x81 = orrshi r4, r5, r6, rrx +0x0f,0x5a,0x85,0x23 = orrhs r5, r5, #0xf000 +0x05,0x40,0x94,0x01 = orrseq r4, r4, r5 +0x57,0x69,0x86,0x11 = orrne r6, r6, r7, asr r9 +0x77,0x69,0x96,0xb1 = orrslt r6, r6, r7, ror r9 +0x65,0x40,0x94,0xc1 = orrsgt r4, r4, r5, rrx +0x22,0x30,0x81,0xe1 = orr r3, r1, r2, lsr #0x20 +0x42,0x30,0x81,0xe1 = orr r3, r1, r2, asr #0x20 +0x13,0x20,0x82,0xe6 = pkhbt r2, r2, r3 +0x93,0x2f,0x82,0xe6 = pkhbt r2, r2, r3, lsl #0x1f +0x13,0x20,0x82,0xe6 = pkhbt r2, r2, r3 +0x93,0x27,0x82,0xe6 = pkhbt r2, r2, r3, lsl #0xf +0x12,0x20,0x83,0xe6 = pkhbt r2, r3, r2 +0xd3,0x2f,0x82,0xe6 = pkhtb r2, r2, r3, asr #0x1f +0xd3,0x27,0x82,0xe6 = pkhtb r2, r2, r3, asr #0xf +0x04,0x70,0x9d,0xe4 = pop {r7} +0x80,0x07,0xbd,0xe8 = pop {r7, r8, r9, r10} +0x04,0x70,0x2d,0xe5 = str r7, [sp, #-0x4]! +0x80,0x07,0x2d,0xe9 = push {r7, r8, r9, r10} +0x52,0x10,0x03,0xe1 = qadd r1, r2, r3 +0x52,0x10,0x03,0x11 = qaddne r1, r2, r3 +0x13,0x1f,0x22,0xe6 = qadd16 r1, r2, r3 +0x13,0x1f,0x22,0xc6 = qadd16gt r1, r2, r3 +0x93,0x1f,0x22,0xe6 = qadd8 r1, r2, r3 +0x93,0x1f,0x22,0xd6 = qadd8le r1, r2, r3 +0x57,0x60,0x48,0xe1 = qdadd r6, r7, r8 +0x57,0x60,0x48,0x81 = qdaddhi r6, r7, r8 +0x57,0x60,0x68,0xe1 = qdsub r6, r7, r8 +0x57,0x60,0x68,0x81 = qdsubhi r6, r7, r8 +0x50,0x9f,0x2c,0xe6 = qsax r9, r12, r0 +0x50,0x9f,0x2c,0x06 = qsaxeq r9, r12, r0 +0x52,0x10,0x23,0xe1 = qsub r1, r2, r3 +0x52,0x10,0x23,0x11 = qsubne r1, r2, r3 +0x73,0x1f,0x22,0xe6 = qsub16 r1, r2, r3 +0x73,0x1f,0x22,0xc6 = qsub16gt r1, r2, r3 +0xf3,0x1f,0x22,0xe6 = qsub8 r1, r2, r3 +0xf3,0x1f,0x22,0xd6 = qsub8le r1, r2, r3 +0x32,0x1f,0xff,0xe6 = rbit r1, r2 +0x32,0x1f,0xff,0x16 = rbitne r1, r2 +0x39,0x1f,0xbf,0xe6 = rev r1, r9 +0x35,0x1f,0xbf,0x16 = revne r1, r5 +0xb3,0x8f,0xbf,0xe6 = rev16 r8, r3 +0xb4,0xcf,0xbf,0x16 = rev16ne r12, r4 +0xb9,0x4f,0xff,0xe6 = revsh r4, r9 +0xb1,0x9f,0xff,0x16 = revshne r9, r1 +0x00,0x0a,0x12,0xf8 = rfeda r2 +0x00,0x0a,0x13,0xf9 = rfedb r3 +0x00,0x0a,0x95,0xf8 = rfeia r5 +0x00,0x0a,0x96,0xf9 = rfeib r6 +0x00,0x0a,0x34,0xf8 = rfeda r4! +0x00,0x0a,0x37,0xf9 = rfedb r7! +0x00,0x0a,0xb9,0xf8 = rfeia r9! +0x00,0x0a,0xb8,0xf9 = rfeib r8! +0x00,0x0a,0x12,0xf8 = rfeda r2 +0x00,0x0a,0x13,0xf9 = rfedb r3 +0x00,0x0a,0x95,0xf8 = rfeia r5 +0x00,0x0a,0x96,0xf9 = rfeib r6 +0x00,0x0a,0x34,0xf8 = rfeda r4! +0x00,0x0a,0x37,0xf9 = rfedb r7! +0x00,0x0a,0xb9,0xf8 = rfeia r9! +0x00,0x0a,0xb8,0xf9 = rfeib r8! +0x00,0x0a,0x91,0xf8 = rfeia r1 +0x00,0x0a,0xb1,0xf8 = rfeia r1! +0xe4,0x2f,0xa0,0xe1 = ror r2, r4, #0x1f +0xe4,0x20,0xa0,0xe1 = ror r2, r4, #1 +0x04,0x20,0xa0,0xe1 = mov r2, r4 +0xe4,0x40,0xa0,0xe1 = ror r4, r4, #1 +0x0f,0x4a,0x65,0xe2 = rsb r4, r5, #0xf000 +0x0f,0x4a,0x65,0xe2 = rsb r4, r5, #0xf000 +0x0f,0x4a,0x65,0xe2 = rsb r4, r5, #0xf000 +0xff,0x78,0x68,0xe2 = rsb r7, r8, #0xff0000 +0x2a,0x71,0x68,0xe2 = rsb r7, r8, #-0x7ffffff6 +0x2a,0x71,0x68,0xe2 = rsb r7, r8, #-0x7ffffff6 +0x28,0x71,0x68,0xe2 = rsb r7, r8, #0x28, #2 +0x28,0x71,0x68,0xe2 = rsb r7, r8, #0x28, #2 +0x28,0x71,0x68,0xe2 = rsb r7, r8, #0x28, #2 +0x28,0x71,0x68,0xe2 = rsb r7, r8, #0x28, #2 +0x06,0x40,0x65,0xe0 = rsb r4, r5, r6 +0x86,0x42,0x65,0xe0 = rsb r4, r5, r6, lsl #5 +0xa6,0x42,0x65,0x30 = rsblo r4, r5, r6, lsr #5 +0xa6,0x42,0x65,0xe0 = rsb r4, r5, r6, lsr #5 +0xc6,0x42,0x65,0xe0 = rsb r4, r5, r6, asr #5 +0xe6,0x42,0x65,0xe0 = rsb r4, r5, r6, ror #5 +0x18,0x69,0x67,0xe0 = rsb r6, r7, r8, lsl r9 +0x38,0x69,0x67,0xe0 = rsb r6, r7, r8, lsr r9 +0x58,0x69,0x67,0xe0 = rsb r6, r7, r8, asr r9 +0x78,0x69,0x67,0xd0 = rsble r6, r7, r8, ror r9 +0x66,0x40,0x65,0xe0 = rsb r4, r5, r6, rrx +0x0f,0x5a,0x65,0xe2 = rsb r5, r5, #0xf000 +0x0f,0x5a,0x65,0xe2 = rsb r5, r5, #0xf000 +0x0f,0x5a,0x65,0xe2 = rsb r5, r5, #0xf000 +0xff,0x78,0x67,0xe2 = rsb r7, r7, #0xff0000 +0x2a,0x71,0x67,0xe2 = rsb r7, r7, #-0x7ffffff6 +0x2a,0x71,0x67,0xe2 = rsb r7, r7, #-0x7ffffff6 +0x28,0x71,0x67,0xe2 = rsb r7, r7, #0x28, #2 +0x28,0x71,0x67,0xe2 = rsb r7, r7, #0x28, #2 +0x28,0x71,0x67,0xe2 = rsb r7, r7, #0x28, #2 +0x28,0x71,0x67,0xe2 = rsb r7, r7, #0x28, #2 +0x05,0x40,0x64,0xe0 = rsb r4, r4, r5 +0x85,0x42,0x64,0xe0 = rsb r4, r4, r5, lsl #5 +0xa5,0x42,0x64,0xe0 = rsb r4, r4, r5, lsr #5 +0xa5,0x42,0x64,0x10 = rsbne r4, r4, r5, lsr #5 +0xc5,0x42,0x64,0xe0 = rsb r4, r4, r5, asr #5 +0xe5,0x42,0x64,0xe0 = rsb r4, r4, r5, ror #5 +0x17,0x69,0x66,0xc0 = rsbgt r6, r6, r7, lsl r9 +0x37,0x69,0x66,0xe0 = rsb r6, r6, r7, lsr r9 +0x57,0x69,0x66,0xe0 = rsb r6, r6, r7, asr r9 +0x77,0x69,0x66,0xe0 = rsb r6, r6, r7, ror r9 +0x65,0x40,0x64,0xe0 = rsb r4, r4, r5, rrx +0xff,0x78,0x77,0xe2 = rsbs r7, r7, #0xff0000 +0xff,0x78,0x77,0xe2 = rsbs r7, r7, #0xff0000 +0xff,0x78,0x77,0xe2 = rsbs r7, r7, #0xff0000 +0xff,0x78,0x77,0xe2 = rsbs r7, r7, #0xff0000 +0x2a,0x71,0x78,0xe2 = rsbs r7, r8, #-0x7ffffff6 +0x2a,0x71,0x78,0xe2 = rsbs r7, r8, #-0x7ffffff6 +0x28,0x71,0x78,0xe2 = rsbs r7, r8, #0x28, #2 +0x28,0x71,0x78,0xe2 = rsbs r7, r8, #0x28, #2 +0x28,0x71,0x78,0xe2 = rsbs r7, r8, #0x28, #2 +0x28,0x71,0x78,0xe2 = rsbs r7, r8, #0x28, #2 +0x0f,0x4a,0xe5,0xe2 = rsc r4, r5, #0xf000 +0x0f,0x4a,0xe5,0xe2 = rsc r4, r5, #0xf000 +0x0f,0x4a,0xe5,0xe2 = rsc r4, r5, #0xf000 +0xff,0x78,0xe8,0xe2 = rsc r7, r8, #0xff0000 +0x2a,0x71,0xe8,0xe2 = rsc r7, r8, #-0x7ffffff6 +0x2a,0x71,0xe8,0xe2 = rsc r7, r8, #-0x7ffffff6 +0x28,0x71,0xe8,0xe2 = rsc r7, r8, #0x28, #2 +0x28,0x71,0xe8,0xe2 = rsc r7, r8, #0x28, #2 +0x28,0x71,0xe8,0xe2 = rsc r7, r8, #0x28, #2 +0x28,0x71,0xe8,0xe2 = rsc r7, r8, #0x28, #2 +0x06,0x40,0xe5,0xe0 = rsc r4, r5, r6 +0x86,0x42,0xe5,0xe0 = rsc r4, r5, r6, lsl #5 +0xa6,0x42,0xe5,0x30 = rsclo r4, r5, r6, lsr #5 +0xa6,0x42,0xe5,0xe0 = rsc r4, r5, r6, lsr #5 +0xc6,0x42,0xe5,0xe0 = rsc r4, r5, r6, asr #5 +0xe6,0x42,0xe5,0xe0 = rsc r4, r5, r6, ror #5 +0x18,0x69,0xe7,0xe0 = rsc r6, r7, r8, lsl r9 +0x38,0x69,0xe7,0xe0 = rsc r6, r7, r8, lsr r9 +0x58,0x69,0xe7,0xe0 = rsc r6, r7, r8, asr r9 +0x78,0x69,0xe7,0xd0 = rscle r6, r7, r8, ror r9 +0xfe,0x1e,0xf8,0xe2 = rscs r1, r8, #0xfe0 +0x0f,0x5a,0xe5,0xe2 = rsc r5, r5, #0xf000 +0x0f,0x5a,0xe5,0xe2 = rsc r5, r5, #0xf000 +0x0f,0x5a,0xe5,0xe2 = rsc r5, r5, #0xf000 +0xff,0x78,0xe7,0xe2 = rsc r7, r7, #0xff0000 +0x2a,0x71,0xe7,0xe2 = rsc r7, r7, #-0x7ffffff6 +0x2a,0x71,0xe7,0xe2 = rsc r7, r7, #-0x7ffffff6 +0x28,0x71,0xe7,0xe2 = rsc r7, r7, #0x28, #2 +0x28,0x71,0xe7,0xe2 = rsc r7, r7, #0x28, #2 +0x28,0x71,0xe7,0xe2 = rsc r7, r7, #0x28, #2 +0x28,0x71,0xe7,0xe2 = rsc r7, r7, #0x28, #2 +0x05,0x40,0xe4,0xe0 = rsc r4, r4, r5 +0x85,0x42,0xe4,0xe0 = rsc r4, r4, r5, lsl #5 +0xa5,0x42,0xe4,0xe0 = rsc r4, r4, r5, lsr #5 +0xa5,0x42,0xe4,0x10 = rscne r4, r4, r5, lsr #5 +0xc5,0x42,0xe4,0xe0 = rsc r4, r4, r5, asr #5 +0xe5,0x42,0xe4,0xe0 = rsc r4, r4, r5, ror #5 +0x17,0x69,0xe6,0xc0 = rscgt r6, r6, r7, lsl r9 +0x37,0x69,0xe6,0xe0 = rsc r6, r6, r7, lsr r9 +0x57,0x69,0xe6,0xe0 = rsc r6, r6, r7, asr r9 +0x77,0x69,0xe6,0xe0 = rsc r6, r6, r7, ror r9 +0x61,0x00,0xa0,0xe1 = rrx r0, r1 +0x6f,0xd0,0xa0,0xe1 = rrx sp, pc +0x6e,0xf0,0xa0,0xe1 = rrx pc, lr +0x6d,0xe0,0xa0,0xe1 = rrx lr, sp +0x61,0x00,0xb0,0xe1 = rrxs r0, r1 +0x6f,0xd0,0xb0,0xe1 = rrxs sp, pc +0x6e,0xf0,0xb0,0xe1 = rrxs pc, lr +0x6d,0xe0,0xb0,0xe1 = rrxs lr, sp +0x13,0x1f,0x12,0xe6 = sadd16 r1, r2, r3 +0x13,0x1f,0x12,0xc6 = sadd16gt r1, r2, r3 +0x93,0x1f,0x12,0xe6 = sadd8 r1, r2, r3 +0x93,0x1f,0x12,0xd6 = sadd8le r1, r2, r3 +0x30,0x9f,0x1c,0xe6 = sasx r9, r12, r0 +0x30,0x9f,0x1c,0x06 = sasxeq r9, r12, r0 +0x0f,0x4a,0xc5,0xe2 = sbc r4, r5, #0xf000 +0x0f,0x4a,0xc5,0xe2 = sbc r4, r5, #0xf000 +0x0f,0x4a,0xc5,0xe2 = sbc r4, r5, #0xf000 +0xff,0x78,0xc8,0xe2 = sbc r7, r8, #0xff0000 +0x2a,0x71,0xc8,0xe2 = sbc r7, r8, #-0x7ffffff6 +0x2a,0x71,0xc8,0xe2 = sbc r7, r8, #-0x7ffffff6 +0x28,0x71,0xc8,0xe2 = sbc r7, r8, #0x28, #2 +0x28,0x71,0xc8,0xe2 = sbc r7, r8, #0x28, #2 +0x28,0x71,0xc8,0xe2 = sbc r7, r8, #0x28, #2 +0x28,0x71,0xc8,0xe2 = sbc r7, r8, #0x28, #2 +0x06,0x40,0xc5,0xe0 = sbc r4, r5, r6 +0x86,0x42,0xc5,0xe0 = sbc r4, r5, r6, lsl #5 +0xa6,0x42,0xc5,0xe0 = sbc r4, r5, r6, lsr #5 +0xa6,0x42,0xc5,0xe0 = sbc r4, r5, r6, lsr #5 +0xc6,0x42,0xc5,0xe0 = sbc r4, r5, r6, asr #5 +0xe6,0x42,0xc5,0xe0 = sbc r4, r5, r6, ror #5 +0x18,0x69,0xc7,0xe0 = sbc r6, r7, r8, lsl r9 +0x38,0x69,0xc7,0xe0 = sbc r6, r7, r8, lsr r9 +0x58,0x69,0xc7,0xe0 = sbc r6, r7, r8, asr r9 +0x78,0x69,0xc7,0xe0 = sbc r6, r7, r8, ror r9 +0x0f,0x5a,0xc5,0xe2 = sbc r5, r5, #0xf000 +0x0f,0x5a,0xc5,0xe2 = sbc r5, r5, #0xf000 +0x0f,0x5a,0xc5,0xe2 = sbc r5, r5, #0xf000 +0xff,0x78,0xc7,0xe2 = sbc r7, r7, #0xff0000 +0x2a,0x71,0xc7,0xe2 = sbc r7, r7, #-0x7ffffff6 +0x2a,0x71,0xc7,0xe2 = sbc r7, r7, #-0x7ffffff6 +0x28,0x71,0xc7,0xe2 = sbc r7, r7, #0x28, #2 +0x28,0x71,0xc7,0xe2 = sbc r7, r7, #0x28, #2 +0x28,0x71,0xc7,0xe2 = sbc r7, r7, #0x28, #2 +0x28,0x71,0xc7,0xe2 = sbc r7, r7, #0x28, #2 +0x05,0x40,0xc4,0xe0 = sbc r4, r4, r5 +0x85,0x42,0xc4,0xe0 = sbc r4, r4, r5, lsl #5 +0xa5,0x42,0xc4,0xe0 = sbc r4, r4, r5, lsr #5 +0xa5,0x42,0xc4,0xe0 = sbc r4, r4, r5, lsr #5 +0xc5,0x42,0xc4,0xe0 = sbc r4, r4, r5, asr #5 +0xe5,0x42,0xc4,0xe0 = sbc r4, r4, r5, ror #5 +0x17,0x69,0xc6,0xe0 = sbc r6, r6, r7, lsl r9 +0x37,0x69,0xc6,0xe0 = sbc r6, r6, r7, lsr r9 +0x57,0x69,0xc6,0xe0 = sbc r6, r6, r7, asr r9 +0x77,0x69,0xc6,0xe0 = sbc r6, r6, r7, ror r9 +0x55,0x48,0xa0,0xe7 = sbfx r4, r5, #0x10, #1 +0x55,0x48,0xaf,0xc7 = sbfxgt r4, r5, #0x10, #0x10 +0xb1,0x9f,0x82,0xe6 = sel r9, r2, r1 +0xb1,0x9f,0x82,0x16 = selne r9, r2, r1 +0x00,0x02,0x01,0xf1 = setend be +0x00,0x02,0x01,0xf1 = setend be +0x00,0x00,0x01,0xf1 = setend le +0x00,0x00,0x01,0xf1 = setend le +0x04,0xf0,0x20,0xe3 = sev +0x04,0xf0,0x20,0x03 = seveq +0x12,0x4f,0x38,0xe6 = shadd16 r4, r8, r2 +0x12,0x4f,0x38,0xc6 = shadd16gt r4, r8, r2 +0x92,0x4f,0x38,0xe6 = shadd8 r4, r8, r2 +0x92,0x4f,0x38,0xc6 = shadd8gt r4, r8, r2 +0x32,0x4f,0x38,0xe6 = shasx r4, r8, r2 +0x32,0x4f,0x38,0xc6 = shasxgt r4, r8, r2 +0x72,0x4f,0x38,0xe6 = shsub16 r4, r8, r2 +0x72,0x4f,0x38,0xc6 = shsub16gt r4, r8, r2 +0xf2,0x4f,0x38,0xe6 = shsub8 r4, r8, r2 +0xf2,0x4f,0x38,0xc6 = shsub8gt r4, r8, r2 +0x81,0x09,0x03,0xe1 = smlabb r3, r1, r9, r0 +0xc6,0x14,0x05,0xe1 = smlabt r5, r6, r4, r1 +0xa2,0x23,0x04,0xe1 = smlatb r4, r2, r3, r2 +0xe3,0x48,0x08,0xe1 = smlatt r8, r3, r8, r4 +0x81,0x09,0x03,0xa1 = smlabbge r3, r1, r9, r0 +0xc6,0x14,0x05,0xd1 = smlabtle r5, r6, r4, r1 +0xa2,0x23,0x04,0x11 = smlatbne r4, r2, r3, r2 +0xe3,0x48,0x08,0x01 = smlatteq r8, r3, r8, r4 +0x13,0x85,0x02,0xe7 = smlad r2, r3, r5, r8 +0x33,0x85,0x02,0xe7 = smladx r2, r3, r5, r8 +0x13,0x85,0x02,0x07 = smladeq r2, r3, r5, r8 +0x33,0x85,0x02,0x87 = smladxhi r2, r3, r5, r8 +0x95,0x28,0xe3,0xe0 = smlal r2, r3, r5, r8 +0x95,0x28,0xf3,0xe0 = smlals r2, r3, r5, r8 +0x95,0x28,0xe3,0x00 = smlaleq r2, r3, r5, r8 +0x95,0x28,0xf3,0x80 = smlalshi r2, r3, r5, r8 +0x89,0x30,0x41,0xe1 = smlalbb r3, r1, r9, r0 +0xc4,0x51,0x46,0xe1 = smlalbt r5, r6, r4, r1 +0xa3,0x42,0x42,0xe1 = smlaltb r4, r2, r3, r2 +0xe8,0x84,0x43,0xe1 = smlaltt r8, r3, r8, r4 +0x89,0x30,0x41,0xa1 = smlalbbge r3, r1, r9, r0 +0xc4,0x51,0x46,0xd1 = smlalbtle r5, r6, r4, r1 +0xa3,0x42,0x42,0x11 = smlaltbne r4, r2, r3, r2 +0xe8,0x84,0x43,0x01 = smlaltteq r8, r3, r8, r4 +0x15,0x28,0x43,0xe7 = smlald r2, r3, r5, r8 +0x35,0x28,0x43,0xe7 = smlaldx r2, r3, r5, r8 +0x15,0x28,0x43,0x07 = smlaldeq r2, r3, r5, r8 +0x35,0x28,0x43,0x87 = smlaldxhi r2, r3, r5, r8 +0x83,0x8a,0x22,0xe1 = smlawb r2, r3, r10, r8 +0xc3,0x95,0x28,0xe1 = smlawt r8, r3, r5, r9 +0x87,0x85,0x22,0x01 = smlawbeq r2, r7, r5, r8 +0xc3,0x80,0x21,0x81 = smlawthi r1, r3, r0, r8 +0x53,0x85,0x02,0xe7 = smlsd r2, r3, r5, r8 +0x73,0x85,0x02,0xe7 = smlsdx r2, r3, r5, r8 +0x53,0x85,0x02,0x07 = smlsdeq r2, r3, r5, r8 +0x73,0x85,0x02,0x87 = smlsdxhi r2, r3, r5, r8 +0x55,0x21,0x49,0xe7 = smlsld r2, r9, r5, r1 +0x72,0x48,0x4b,0xe7 = smlsldx r4, r11, r2, r8 +0x55,0x86,0x42,0x07 = smlsldeq r8, r2, r5, r6 +0x73,0x18,0x40,0x87 = smlsldxhi r1, r0, r3, r8 +0x12,0x43,0x51,0xe7 = smmla r1, r2, r3, r4 +0x33,0x12,0x54,0xe7 = smmlar r4, r3, r2, r1 +0x12,0x43,0x51,0x37 = smmlalo r1, r2, r3, r4 +0x33,0x12,0x54,0x27 = smmlarhs r4, r3, r2, r1 +0xd2,0x43,0x51,0xe7 = smmls r1, r2, r3, r4 +0xf3,0x12,0x54,0xe7 = smmlsr r4, r3, r2, r1 +0xd2,0x43,0x51,0x37 = smmlslo r1, r2, r3, r4 +0xf3,0x12,0x54,0x27 = smmlsrhs r4, r3, r2, r1 +0x13,0xf4,0x52,0xe7 = smmul r2, r3, r4 +0x32,0xf1,0x53,0xe7 = smmulr r3, r2, r1 +0x13,0xf4,0x52,0x37 = smmullo r2, r3, r4 +0x32,0xf1,0x53,0x27 = smmulrhs r3, r2, r1 +0x13,0xf4,0x02,0xe7 = smuad r2, r3, r4 +0x32,0xf1,0x03,0xe7 = smuadx r3, r2, r1 +0x13,0xf4,0x02,0xb7 = smuadlt r2, r3, r4 +0x32,0xf1,0x03,0xa7 = smuadxge r3, r2, r1 +0x89,0x00,0x63,0xe1 = smulbb r3, r9, r0 +0xc4,0x01,0x65,0xe1 = smulbt r5, r4, r1 +0xa2,0x02,0x64,0xe1 = smultb r4, r2, r2 +0xe3,0x04,0x68,0xe1 = smultt r8, r3, r4 +0x89,0x00,0x61,0xa1 = smulbbge r1, r9, r0 +0xc6,0x04,0x65,0xd1 = smulbtle r5, r6, r4 +0xa3,0x02,0x62,0x11 = smultbne r2, r3, r2 +0xe3,0x04,0x68,0x01 = smultteq r8, r3, r4 +0x90,0x31,0xc9,0xe0 = smull r3, r9, r0, r1 +0x90,0x32,0xd9,0xe0 = smulls r3, r9, r0, r2 +0x94,0x85,0xc3,0x00 = smulleq r8, r3, r4, r5 +0x94,0x83,0xd3,0x00 = smullseq r8, r3, r4, r3 +0xa9,0x00,0x23,0xe1 = smulwb r3, r9, r0 +0xe9,0x02,0x23,0xe1 = smulwt r3, r9, r2 +0x50,0xf1,0x03,0xe7 = smusd r3, r0, r1 +0x79,0xf2,0x03,0xe7 = smusdx r3, r9, r2 +0x53,0xf2,0x08,0x07 = smusdeq r8, r3, r2 +0x74,0xf3,0x07,0x17 = smusdxne r7, r4, r3 +0x05,0x05,0x4d,0xf8 = srsda sp, #5 +0x01,0x05,0x4d,0xf9 = srsdb sp, #1 +0x00,0x05,0xcd,0xf8 = srsia sp, #0 +0x0f,0x05,0xcd,0xf9 = srsib sp, #0xf +0x1f,0x05,0x6d,0xf8 = srsda sp!, #0x1f +0x13,0x05,0x6d,0xf9 = srsdb sp!, #0x13 +0x02,0x05,0xed,0xf8 = srsia sp!, #2 +0x0e,0x05,0xed,0xf9 = srsib sp!, #0xe +0x0b,0x05,0xcd,0xf9 = srsib sp, #0xb +0x0a,0x05,0xcd,0xf8 = srsia sp, #0xa +0x09,0x05,0x4d,0xf9 = srsdb sp, #0x9 +0x05,0x05,0x4d,0xf8 = srsda sp, #5 +0x05,0x05,0xed,0xf9 = srsib sp!, #5 +0x05,0x05,0xed,0xf8 = srsia sp!, #5 +0x05,0x05,0x6d,0xf9 = srsdb sp!, #5 +0x05,0x05,0x6d,0xf8 = srsda sp!, #5 +0x05,0x05,0xcd,0xf8 = srsia sp, #5 +0x05,0x05,0xed,0xf8 = srsia sp!, #5 +0x05,0x05,0x4d,0xf8 = srsda sp, #5 +0x01,0x05,0x4d,0xf9 = srsdb sp, #1 +0x00,0x05,0xcd,0xf8 = srsia sp, #0 +0x0f,0x05,0xcd,0xf9 = srsib sp, #0xf +0x1f,0x05,0x6d,0xf8 = srsda sp!, #0x1f +0x13,0x05,0x6d,0xf9 = srsdb sp!, #0x13 +0x02,0x05,0xed,0xf8 = srsia sp!, #2 +0x0e,0x05,0xed,0xf9 = srsib sp!, #0xe +0x0b,0x05,0xcd,0xf9 = srsib sp, #0xb +0x0a,0x05,0xcd,0xf8 = srsia sp, #0xa +0x09,0x05,0x4d,0xf9 = srsdb sp, #0x9 +0x05,0x05,0x4d,0xf8 = srsda sp, #5 +0x05,0x05,0xed,0xf9 = srsib sp!, #5 +0x05,0x05,0xed,0xf8 = srsia sp!, #5 +0x05,0x05,0x6d,0xf9 = srsdb sp!, #5 +0x05,0x05,0x6d,0xf8 = srsda sp!, #5 +0x05,0x05,0xcd,0xf8 = srsia sp, #5 +0x05,0x05,0xed,0xf8 = srsia sp!, #5 +0x1a,0x80,0xa0,0xe6 = ssat r8, #1, r10 +0x1a,0x80,0xa0,0xe6 = ssat r8, #1, r10 +0x9a,0x8f,0xa0,0xe6 = ssat r8, #1, r10, lsl #0x1f +0x5a,0x80,0xa0,0xe6 = ssat r8, #1, r10, asr #0x20 +0xda,0x80,0xa0,0xe6 = ssat r8, #1, r10, asr #1 +0x37,0x2f,0xa0,0xe6 = ssat16 r2, #1, r7 +0x35,0x3f,0xaf,0xe6 = ssat16 r3, #0x10, r5 +0x54,0x2f,0x13,0xe6 = ssax r2, r3, r4 +0x54,0x2f,0x13,0xb6 = ssaxlt r2, r3, r4 +0x76,0x1f,0x10,0xe6 = ssub16 r1, r0, r6 +0x72,0x5f,0x13,0x16 = ssub16ne r5, r3, r2 +0xf4,0x9f,0x12,0xe6 = ssub8 r9, r2, r4 +0xf2,0x5f,0x11,0x06 = ssub8eq r5, r1, r2 +0x01,0x80,0x81,0xfd = stc2 p0, c8, [r1, #4] +0x00,0x71,0x82,0xfd = stc2 p1, c7, [r2] +0x38,0x62,0x03,0xfd = stc2 p2, c6, [r3, #-0xe0] +0x1e,0x53,0x24,0xfd = stc2 p3, c5, [r4, #-0x78]! +0x04,0x44,0xa5,0xfc = stc2 p4, c4, [r5], #0x10 +0x12,0x35,0x26,0xfc = stc2 p5, c3, [r6], #-0x48 +0x01,0x26,0xc7,0xfd = stc2l p6, c2, [r7, #4] +0x00,0x17,0xc8,0xfd = stc2l p7, c1, [r8] +0x38,0x08,0x49,0xfd = stc2l p8, c0, [r9, #-0xe0] +0x1e,0x19,0x6a,0xfd = stc2l p9, c1, [r10, #-0x78]! +0x04,0x20,0xeb,0xfc = stc2l p0, c2, [r11], #0x10 +0x12,0x31,0x6c,0xfc = stc2l p1, c3, [r12], #-0x48 +0x01,0x4c,0x80,0xed = stc p12, c4, [r0, #4] +0x00,0x5d,0x81,0xed = stc p13, c5, [r1] +0x38,0x6e,0x02,0xed = stc p14, c6, [r2, #-0xe0] +0x1e,0x7f,0x23,0xed = stc p15, c7, [r3, #-0x78]! +0x04,0x85,0xa4,0xec = stc p5, c8, [r4], #0x10 +0x12,0x94,0x25,0xec = stc p4, c9, [r5], #-0x48 +0x01,0xa3,0xc6,0xed = stcl p3, c10, [r6, #4] +0x00,0xb2,0xc7,0xed = stcl p2, c11, [r7] +0x38,0xc1,0x48,0xed = stcl p1, c12, [r8, #-0xe0] +0x1e,0xd0,0x69,0xed = stcl p0, c13, [r9, #-0x78]! +0x04,0xe6,0xea,0xec = stcl p6, c14, [r10], #0x10 +0x12,0xf7,0x6b,0xec = stcl p7, c15, [r11], #-0x48 +0x01,0x4c,0x80,0x3d = stclo p12, c4, [r0, #4] +0x00,0x5d,0x81,0x8d = stchi p13, c5, [r1] +0x38,0x6e,0x02,0x2d = stchs p14, c6, [r2, #-0xe0] +0x1e,0x7f,0x23,0x3d = stclo p15, c7, [r3, #-0x78]! +0x04,0x85,0xa4,0x0c = stceq p5, c8, [r4], #0x10 +0x12,0x94,0x25,0xcc = stcgt p4, c9, [r5], #-0x48 +0x01,0xa3,0xc6,0xbd = stcllt p3, c10, [r6, #4] +0x00,0xb2,0xc7,0xad = stclge p2, c11, [r7] +0x38,0xc1,0x48,0xdd = stclle p1, c12, [r8, #-0xe0] +0x1e,0xd0,0x69,0x1d = stclne p0, c13, [r9, #-0x78]! +0x04,0xe6,0xea,0x0c = stcleq p6, c14, [r10], #0x10 +0x12,0xf7,0x6b,0x8c = stclhi p7, c15, [r11], #-0x48 +0x19,0x82,0x81,0xfc = stc2 p2, c8, [r1], {25} +0x7a,0x20,0x82,0xe8 = stm r2, {r1, r3, r4, r5, r6, sp} +0x7a,0x40,0x83,0xe8 = stm r3, {r1, r3, r4, r5, r6, lr} +0x7a,0x20,0x84,0xe9 = stmib r4, {r1, r3, r4, r5, r6, sp} +0x7a,0x20,0x05,0xe8 = stmda r5, {r1, r3, r4, r5, r6, sp} +0x7a,0x01,0x06,0xe9 = stmdb r6, {r1, r3, r4, r5, r6, r8} +0x7a,0x20,0x0d,0xe9 = stmdb sp, {r1, r3, r4, r5, r6, sp} +0x7a,0x20,0xa8,0xe8 = stm r8!, {r1, r3, r4, r5, r6, sp} +0x7a,0x20,0xa9,0xe9 = stmib r9!, {r1, r3, r4, r5, r6, sp} +0x7a,0x00,0x2d,0xe8 = stmda sp!, {r1, r3, r4, r5, r6} +0xa2,0x20,0x20,0xe9 = stmdb r0!, {r1, r5, r7, sp} +0x93,0x1f,0xc4,0xe1 = strexb r1, r3, [r4] +0x92,0x4f,0xe5,0xe1 = strexh r4, r2, [r5] +0x91,0x2f,0x87,0xe1 = strex r2, r1, [r7] +0x92,0x6f,0xa8,0xe1 = strexd r6, r2, r3, [r8] +0x00,0x30,0x2a,0x55 = strpl r3, [r10, #-0]! +0x00,0x30,0xaa,0x55 = strpl r3, [r10, #0]! +0x0f,0x4a,0x45,0xe2 = sub r4, r5, #0xf000 +0x0f,0x4a,0x45,0xe2 = sub r4, r5, #0xf000 +0x0f,0x4a,0x45,0xe2 = sub r4, r5, #0xf000 +0xff,0x78,0x48,0xe2 = sub r7, r8, #0xff0000 +0x2a,0x71,0x48,0xe2 = sub r7, r8, #-0x7ffffff6 +0x2a,0x71,0x48,0xe2 = sub r7, r8, #-0x7ffffff6 +0x28,0x71,0x48,0xe2 = sub r7, r8, #0x28, #2 +0x28,0x71,0x48,0xe2 = sub r7, r8, #0x28, #2 +0x28,0x71,0x48,0xe2 = sub r7, r8, #0x28, #2 +0x28,0x71,0x48,0xe2 = sub r7, r8, #0x28, #2 +0x06,0x40,0x45,0xe0 = sub r4, r5, r6 +0x86,0x42,0x45,0xe0 = sub r4, r5, r6, lsl #5 +0xa6,0x42,0x45,0xe0 = sub r4, r5, r6, lsr #5 +0xa6,0x42,0x45,0xe0 = sub r4, r5, r6, lsr #5 +0xc6,0x42,0x45,0xe0 = sub r4, r5, r6, asr #5 +0xe6,0x42,0x45,0xe0 = sub r4, r5, r6, ror #5 +0x18,0x69,0x47,0xe0 = sub r6, r7, r8, lsl r9 +0x38,0x69,0x47,0xe0 = sub r6, r7, r8, lsr r9 +0x58,0x69,0x47,0xe0 = sub r6, r7, r8, asr r9 +0x78,0x69,0x47,0xe0 = sub r6, r7, r8, ror r9 +0x0f,0x5a,0x45,0xe2 = sub r5, r5, #0xf000 +0x0f,0x5a,0x45,0xe2 = sub r5, r5, #0xf000 +0x0f,0x5a,0x45,0xe2 = sub r5, r5, #0xf000 +0xff,0x78,0x47,0xe2 = sub r7, r7, #0xff0000 +0x2a,0x71,0x47,0xe2 = sub r7, r7, #-0x7ffffff6 +0x2a,0x71,0x47,0xe2 = sub r7, r7, #-0x7ffffff6 +0x28,0x71,0x47,0xe2 = sub r7, r7, #0x28, #2 +0x28,0x71,0x47,0xe2 = sub r7, r7, #0x28, #2 +0x28,0x71,0x47,0xe2 = sub r7, r7, #0x28, #2 +0x05,0x40,0x44,0xe0 = sub r4, r4, r5 +0x85,0x42,0x44,0xe0 = sub r4, r4, r5, lsl #5 +0xa5,0x42,0x44,0xe0 = sub r4, r4, r5, lsr #5 +0xa5,0x42,0x44,0xe0 = sub r4, r4, r5, lsr #5 +0xc5,0x42,0x44,0xe0 = sub r4, r4, r5, asr #5 +0xe5,0x42,0x44,0xe0 = sub r4, r4, r5, ror #5 +0x17,0x69,0x46,0xe0 = sub r6, r6, r7, lsl r9 +0x37,0x69,0x46,0xe0 = sub r6, r6, r7, lsr r9 +0x57,0x69,0x46,0xe0 = sub r6, r6, r7, asr r9 +0x77,0x69,0x46,0xe0 = sub r6, r6, r7, ror r9 +0x22,0x30,0x41,0xe0 = sub r3, r1, r2, lsr #0x20 +0x42,0x30,0x41,0xe0 = sub r3, r1, r2, asr #0x20 +0xff,0x78,0x58,0xe2 = subs r7, r8, #0xff0000 +0xff,0x78,0x58,0xe2 = subs r7, r8, #0xff0000 +0xff,0x78,0x58,0xe2 = subs r7, r8, #0xff0000 +0xff,0x78,0x58,0xe2 = subs r7, r8, #0xff0000 +0x2a,0x71,0x58,0xe2 = subs r7, r8, #-0x7ffffff6 +0x2a,0x71,0x58,0xe2 = subs r7, r8, #-0x7ffffff6 +0x28,0x71,0x58,0xe2 = subs r7, r8, #0x28, #2 +0x28,0x71,0x58,0xe2 = subs r7, r8, #0x28, #2 +0x28,0x71,0x58,0xe2 = subs r7, r8, #0x28, #2 +0x28,0x71,0x58,0xe2 = subs r7, r8, #0x28, #2 +0x10,0x00,0x00,0xef = svc #0x10 +0x00,0x00,0x00,0xef = svc #0 +0xff,0xff,0xff,0xef = svc #0xffffff +0x92,0x10,0x03,0xe1 = swp r1, r2, [r3] +0x94,0x40,0x06,0xe1 = swp r4, r4, [r6] +0x91,0x50,0x49,0xe1 = swpb r5, r1, [r9] +0x74,0x20,0xa3,0xe6 = sxtab r2, r3, r4 +0x76,0x40,0xa5,0xe6 = sxtab r4, r5, r6 +0x79,0x64,0xa2,0xb6 = sxtablt r6, r2, r9, ror #8 +0x74,0x58,0xa1,0xe6 = sxtab r5, r1, r4, ror #0x10 +0x73,0x7c,0xa8,0xe6 = sxtab r7, r8, r3, ror #0x18 +0x74,0x00,0x81,0xa6 = sxtab16ge r0, r1, r4 +0x77,0x60,0x82,0xe6 = sxtab16 r6, r2, r7 +0x78,0x34,0x85,0xe6 = sxtab16 r3, r5, r8, ror #8 +0x71,0x38,0x82,0xe6 = sxtab16 r3, r2, r1, ror #0x10 +0x73,0x1c,0x82,0x06 = sxtab16eq r1, r2, r3, ror #0x18 +0x79,0x10,0xb3,0xe6 = sxtah r1, r3, r9 +0x76,0x60,0xb1,0x86 = sxtahhi r6, r1, r6 +0x73,0x34,0xb8,0xe6 = sxtah r3, r8, r3, ror #8 +0x74,0x28,0xb2,0x36 = sxtahlo r2, r2, r4, ror #0x10 +0x73,0x9c,0xb3,0xe6 = sxtah r9, r3, r3, ror #0x18 +0x74,0x20,0xaf,0xa6 = sxtbge r2, r4 +0x76,0x50,0xaf,0xe6 = sxtb r5, r6 +0x79,0x64,0xaf,0xe6 = sxtb r6, r9, ror #8 +0x71,0x58,0xaf,0x36 = sxtblo r5, r1, ror #0x10 +0x73,0x8c,0xaf,0xe6 = sxtb r8, r3, ror #0x18 +0x74,0x10,0x8f,0xe6 = sxtb16 r1, r4 +0x77,0x60,0x8f,0xe6 = sxtb16 r6, r7 +0x75,0x34,0x8f,0x26 = sxtb16hs r3, r5, ror #8 +0x71,0x38,0x8f,0xe6 = sxtb16 r3, r1, ror #0x10 +0x73,0x2c,0x8f,0xa6 = sxtb16ge r2, r3, ror #0x18 +0x79,0x30,0xbf,0x16 = sxthne r3, r9 +0x76,0x10,0xbf,0xe6 = sxth r1, r6 +0x78,0x34,0xbf,0xe6 = sxth r3, r8, ror #8 +0x72,0x28,0xbf,0xd6 = sxthle r2, r2, ror #0x10 +0x73,0x9c,0xbf,0xe6 = sxth r9, r3, ror #0x18 +0x0f,0x0a,0x35,0xe3 = teq r5, #0xf000 +0x0f,0x0a,0x35,0xe3 = teq r5, #0xf000 +0x0f,0x0a,0x35,0xe3 = teq r5, #0xf000 +0xff,0x08,0x37,0xe3 = teq r7, #0xff0000 +0x2a,0x01,0x37,0xe3 = teq r7, #-0x7ffffff6 +0x2a,0x01,0x37,0xe3 = teq r7, #-0x7ffffff6 +0x28,0x01,0x37,0xe3 = teq r7, #0x28, #2 +0x28,0x01,0x37,0xe3 = teq r7, #0x28, #2 +0x28,0x01,0x37,0xe3 = teq r7, #0x28, #2 +0x28,0x01,0x37,0xe3 = teq r7, #0x28, #2 +0x05,0x00,0x34,0xe1 = teq r4, r5 +0x85,0x02,0x34,0xe1 = teq r4, r5, lsl #5 +0xa5,0x02,0x34,0xe1 = teq r4, r5, lsr #5 +0xa5,0x02,0x34,0xe1 = teq r4, r5, lsr #5 +0xc5,0x02,0x34,0xe1 = teq r4, r5, asr #5 +0xe5,0x02,0x34,0xe1 = teq r4, r5, ror #5 +0x17,0x09,0x36,0xe1 = teq r6, r7, lsl r9 +0x37,0x09,0x36,0xe1 = teq r6, r7, lsr r9 +0x57,0x09,0x36,0xe1 = teq r6, r7, asr r9 +0x77,0x09,0x36,0xe1 = teq r6, r7, ror r9 +0x0f,0x0a,0x15,0xe3 = tst r5, #0xf000 +0x0f,0x0a,0x15,0xe3 = tst r5, #0xf000 +0x0f,0x0a,0x15,0xe3 = tst r5, #0xf000 +0xff,0x08,0x17,0xe3 = tst r7, #0xff0000 +0x2a,0x01,0x17,0xe3 = tst r7, #-0x7ffffff6 +0x2a,0x01,0x17,0xe3 = tst r7, #-0x7ffffff6 +0x28,0x01,0x17,0xe3 = tst r7, #0x28, #2 +0x28,0x01,0x17,0xe3 = tst r7, #0x28, #2 +0x28,0x01,0x17,0xe3 = tst r7, #0x28, #2 +0x28,0x01,0x17,0xe3 = tst r7, #0x28, #2 +0x05,0x00,0x14,0xe1 = tst r4, r5 +0x85,0x02,0x14,0xe1 = tst r4, r5, lsl #5 +0xa5,0x02,0x14,0xe1 = tst r4, r5, lsr #5 +0xa5,0x02,0x14,0xe1 = tst r4, r5, lsr #5 +0xc5,0x02,0x14,0xe1 = tst r4, r5, asr #5 +0xe5,0x02,0x14,0xe1 = tst r4, r5, ror #5 +0x17,0x09,0x16,0xe1 = tst r6, r7, lsl r9 +0x37,0x09,0x16,0xe1 = tst r6, r7, lsr r9 +0x57,0x09,0x16,0xe1 = tst r6, r7, asr r9 +0x77,0x09,0x16,0xe1 = tst r6, r7, ror r9 +0x13,0x1f,0x52,0xe6 = uadd16 r1, r2, r3 +0x13,0x1f,0x52,0xc6 = uadd16gt r1, r2, r3 +0x93,0x1f,0x52,0xe6 = uadd8 r1, r2, r3 +0x93,0x1f,0x52,0xd6 = uadd8le r1, r2, r3 +0x30,0x9f,0x5c,0xe6 = uasx r9, r12, r0 +0x30,0x9f,0x5c,0x06 = uasxeq r9, r12, r0 +0x55,0x48,0xe0,0xe7 = ubfx r4, r5, #0x10, #1 +0x55,0x48,0xef,0xc7 = ubfxgt r4, r5, #0x10, #0x10 +0x12,0x4f,0x78,0xe6 = uhadd16 r4, r8, r2 +0x12,0x4f,0x78,0xc6 = uhadd16gt r4, r8, r2 +0x92,0x4f,0x78,0xe6 = uhadd8 r4, r8, r2 +0x92,0x4f,0x78,0xc6 = uhadd8gt r4, r8, r2 +0x32,0x4f,0x78,0xe6 = uhasx r4, r8, r2 +0x32,0x4f,0x78,0xc6 = uhasxgt r4, r8, r2 +0x72,0x4f,0x78,0xe6 = uhsub16 r4, r8, r2 +0x72,0x4f,0x78,0xc6 = uhsub16gt r4, r8, r2 +0xf2,0x4f,0x78,0xe6 = uhsub8 r4, r8, r2 +0xf2,0x4f,0x78,0xc6 = uhsub8gt r4, r8, r2 +0x95,0x36,0x44,0xe0 = umaal r3, r4, r5, r6 +0x95,0x36,0x44,0xb0 = umaallt r3, r4, r5, r6 +0x96,0x28,0xa4,0xe0 = umlal r2, r4, r6, r8 +0x92,0x66,0xa1,0xc0 = umlalgt r6, r1, r2, r6 +0x92,0x23,0xb9,0xe0 = umlals r2, r9, r2, r3 +0x91,0x32,0xb5,0x00 = umlalseq r3, r5, r1, r2 +0x96,0x28,0x84,0xe0 = umull r2, r4, r6, r8 +0x92,0x66,0x81,0xc0 = umullgt r6, r1, r2, r6 +0x92,0x23,0x99,0xe0 = umulls r2, r9, r2, r3 +0x91,0x32,0x95,0x00 = umullseq r3, r5, r1, r2 +0x13,0x1f,0x62,0xe6 = uqadd16 r1, r2, r3 +0x19,0x4f,0x67,0xc6 = uqadd16gt r4, r7, r9 +0x98,0x3f,0x64,0xe6 = uqadd8 r3, r4, r8 +0x92,0x8f,0x61,0xd6 = uqadd8le r8, r1, r2 +0x31,0x2f,0x64,0xe6 = uqasx r2, r4, r1 +0x39,0x5f,0x62,0x86 = uqasxhi r5, r2, r9 +0x57,0x1f,0x63,0xe6 = uqsax r1, r3, r7 +0x52,0x3f,0x66,0xe6 = uqsax r3, r6, r2 +0x73,0x1f,0x65,0xe6 = uqsub16 r1, r5, r3 +0x75,0x3f,0x62,0xc6 = uqsub16gt r3, r2, r5 +0xf4,0x2f,0x61,0xe6 = uqsub8 r2, r1, r4 +0xf9,0x4f,0x66,0xd6 = uqsub8le r4, r6, r9 +0x11,0xf4,0x82,0xe7 = usad8 r2, r1, r4 +0x16,0xf9,0x84,0xd7 = usad8le r4, r6, r9 +0x15,0x73,0x81,0xe7 = usada8 r1, r5, r3, r7 +0x12,0x15,0x83,0xc7 = usada8gt r3, r2, r5, r1 +0x1a,0x80,0xe1,0xe6 = usat r8, #1, r10 +0x1a,0x80,0xe4,0xe6 = usat r8, #4, r10 +0x9a,0x8f,0xe5,0xe6 = usat r8, #5, r10, lsl #0x1f +0x5a,0x80,0xff,0xe6 = usat r8, #0x1f, r10, asr #0x20 +0xda,0x80,0xf0,0xe6 = usat r8, #0x10, r10, asr #1 +0x37,0x2f,0xe2,0xe6 = usat16 r2, #2, r7 +0x35,0x3f,0xef,0xe6 = usat16 r3, #0xf, r5 +0x54,0x2f,0x53,0xe6 = usax r2, r3, r4 +0x54,0x2f,0x53,0x16 = usaxne r2, r3, r4 +0x77,0x4f,0x52,0xe6 = usub16 r4, r2, r7 +0x73,0x1f,0x51,0x86 = usub16hi r1, r1, r3 +0xf5,0x1f,0x58,0xe6 = usub8 r1, r8, r5 +0xf3,0x9f,0x52,0xd6 = usub8le r9, r2, r3 +0x74,0x20,0xe3,0xe6 = uxtab r2, r3, r4 +0x76,0x40,0xe5,0xe6 = uxtab r4, r5, r6 +0x79,0x64,0xe2,0xb6 = uxtablt r6, r2, r9, ror #8 +0x74,0x58,0xe1,0xe6 = uxtab r5, r1, r4, ror #0x10 +0x73,0x7c,0xe8,0xe6 = uxtab r7, r8, r3, ror #0x18 +0x74,0x00,0xc1,0xa6 = uxtab16ge r0, r1, r4 +0x77,0x60,0xc2,0xe6 = uxtab16 r6, r2, r7 +0x78,0x34,0xc5,0xe6 = uxtab16 r3, r5, r8, ror #8 +0x71,0x38,0xc2,0xe6 = uxtab16 r3, r2, r1, ror #0x10 +0x73,0x1c,0xc2,0x06 = uxtab16eq r1, r2, r3, ror #0x18 +0x79,0x10,0xf3,0xe6 = uxtah r1, r3, r9 +0x76,0x60,0xf1,0x86 = uxtahhi r6, r1, r6 +0x73,0x34,0xf8,0xe6 = uxtah r3, r8, r3, ror #8 +0x74,0x28,0xf2,0x36 = uxtahlo r2, r2, r4, ror #0x10 +0x73,0x9c,0xf3,0xe6 = uxtah r9, r3, r3, ror #0x18 +0x74,0x20,0xef,0xa6 = uxtbge r2, r4 +0x76,0x50,0xef,0xe6 = uxtb r5, r6 +0x79,0x64,0xef,0xe6 = uxtb r6, r9, ror #8 +0x71,0x58,0xef,0x36 = uxtblo r5, r1, ror #0x10 +0x73,0x8c,0xef,0xe6 = uxtb r8, r3, ror #0x18 +0x74,0x10,0xcf,0xe6 = uxtb16 r1, r4 +0x77,0x60,0xcf,0xe6 = uxtb16 r6, r7 +0x75,0x34,0xcf,0x26 = uxtb16hs r3, r5, ror #8 +0x71,0x38,0xcf,0xe6 = uxtb16 r3, r1, ror #0x10 +0x73,0x2c,0xcf,0xa6 = uxtb16ge r2, r3, ror #0x18 +0x79,0x30,0xff,0x16 = uxthne r3, r9 +0x76,0x10,0xff,0xe6 = uxth r1, r6 +0x78,0x34,0xff,0xe6 = uxth r3, r8, ror #8 +0x72,0x28,0xff,0xd6 = uxthle r2, r2, ror #0x10 +0x73,0x9c,0xff,0xe6 = uxth r9, r3, ror #0x18 +0x02,0xf0,0x20,0xe3 = wfe +0x02,0xf0,0x20,0x83 = wfehi +0x03,0xf0,0x20,0xe3 = wfi +0x03,0xf0,0x20,0xb3 = wfilt +0x01,0xf0,0x20,0xe3 = yield +0x01,0xf0,0x20,0x13 = yieldne +0x04,0xf0,0x20,0xe3 = sev +0x03,0xf0,0x20,0xe3 = wfi +0x02,0xf0,0x20,0xe3 = wfe +0x01,0xf0,0x20,0xe3 = yield +0x00,0xf0,0x20,0xe3 = nop +0xef,0xf0,0x20,0xc3 = hintgt #0xef diff --git a/thirdparty/capstone/suite/MC/ARM/basic-thumb-instructions.s.cs b/thirdparty/capstone/suite/MC/ARM/basic-thumb-instructions.s.cs new file mode 100644 index 0000000..bb3d8a8 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/basic-thumb-instructions.s.cs @@ -0,0 +1,130 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x74,0x41 = adcs r4, r6 +0xd1,0x1c = adds r1, r2, #3 +0x03,0x32 = adds r2, #3 +0x08,0x32 = adds r2, #8 +0xd1,0x18 = adds r1, r2, r3 +0x42,0x44 = add r2, r8 +0x01,0xb0 = add sp, #4 +0x7f,0xb0 = add sp, #0x1fc +0x01,0xb0 = add sp, #4 +0x02,0xaa = add r2, sp, #8 +0xff,0xaa = add r2, sp, #0x3fc +0x82,0xb0 = sub sp, #8 +0x82,0xb0 = sub sp, #8 +0x9d,0x44 = add sp, r3 +0x6a,0x44 = add r2, sp, r2 +0x00,0xa5 = adr r5, #0 +0x01,0xa2 = adr r2, #4 +0xff,0xa3 = adr r3, #0x3fc +0x1a,0x10 = asrs r2, r3, #0x20 +0x5a,0x11 = asrs r2, r3, #5 +0x5a,0x10 = asrs r2, r3, #1 +0x6d,0x15 = asrs r5, r5, #0x15 +0x6d,0x15 = asrs r5, r5, #0x15 +0x6b,0x15 = asrs r3, r5, #0x15 +0x15,0x41 = asrs r5, r2 +0x97,0xe3 = b #0x72e +0x2e,0xe7 = b #-0x1a4 +0x80,0xd0 = beq #-0x100 +0x50,0xd0 = beq #0xa0 +0xd8,0xf0,0x20,0xe8 = blx #0xd8040 +0xb0,0xf1,0x40,0xe8 = blx #0x1b0080 +0xb1,0x43 = bics r1, r6 +0x00,0xbe = bkpt #0 +0xff,0xbe = bkpt #0xff +0xa0,0x47 = blx r4 +0x10,0x47 = bx r2 +0xcd,0x42 = cmn r5, r1 +0x20,0x2e = cmp r6, #0x20 +0xa3,0x42 = cmp r3, r4 +0x88,0x45 = cmp r8, r1 +0x61,0xb6 = cpsie f +0x74,0xb6 = cpsid a +0x6c,0x40 = eors r4, r5 +0xff,0xcb = ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} +0xba,0xca = ldm r2!, {r1, r3, r4, r5, r7} +0x02,0xc9 = ldm r1, {r1} +0x29,0x68 = ldr r1, [r5] +0x32,0x6a = ldr r2, [r6, #0x20] +0xfb,0x6f = ldr r3, [r7, #0x7c] +0x00,0x99 = ldr r1, [sp] +0x06,0x9a = ldr r2, [sp, #0x18] +0xff,0x9b = ldr r3, [sp, #0x3fc] +0x97,0x4b = ldr r3, [pc, #0x25c] +0x5c,0x4b = ldr r3, [pc, #0x170] +0xd1,0x58 = ldr r1, [r2, r3] +0x1c,0x78 = ldrb r4, [r3] +0x35,0x78 = ldrb r5, [r6] +0xfe,0x7f = ldrb r6, [r7, #0x1f] +0x66,0x5d = ldrb r6, [r4, r5] +0x1b,0x88 = ldrh r3, [r3] +0x74,0x88 = ldrh r4, [r6, #2] +0xfd,0x8f = ldrh r5, [r7, #0x3e] +0x96,0x5b = ldrh r6, [r2, r6] +0x96,0x57 = ldrsb r6, [r2, r6] +0x7b,0x5e = ldrsh r3, [r7, r1] +0x2c,0x00 = movs r4, r5 +0x2c,0x01 = lsls r4, r5, #4 +0x1b,0x03 = lsls r3, r3, #0xc +0x1b,0x03 = lsls r3, r3, #0xc +0x19,0x03 = lsls r1, r3, #0xc +0xb2,0x40 = lsls r2, r6 +0x59,0x08 = lsrs r1, r3, #1 +0x19,0x08 = lsrs r1, r3, #0x20 +0x24,0x0d = lsrs r4, r4, #0x14 +0x24,0x0d = lsrs r4, r4, #0x14 +0x22,0x0d = lsrs r2, r4, #0x14 +0xf2,0x40 = lsrs r2, r6 +0x00,0x22 = movs r2, #0 +0xff,0x22 = movs r2, #0xff +0x17,0x22 = movs r2, #0x17 +0x23,0x46 = mov r3, r4 +0x19,0x00 = movs r1, r3 +0x51,0x43 = muls r1, r2, r1 +0x5a,0x43 = muls r2, r3, r2 +0x63,0x43 = muls r3, r4, r3 +0xde,0x43 = mvns r6, r3 +0x63,0x42 = rsbs r3, r4, #0 +0x4c,0xbc = pop {r2, r3, r6} +0x86,0xb4 = push {r1, r2, r7} +0x1e,0xba = rev r6, r3 +0x57,0xba = rev16 r7, r2 +0xcd,0xba = revsh r5, r1 +0xfa,0x41 = rors r2, r7 +0x59,0x42 = rsbs r1, r3, #0 +0x9c,0x41 = sbcs r4, r3 +0x58,0xb6 = setend be +0x50,0xb6 = setend le +0x44,0xc1 = stm r1!, {r2, r6} +0x8e,0xc1 = stm r1!, {r1, r2, r3, r7} +0x3a,0x60 = str r2, [r7] +0x3a,0x60 = str r2, [r7] +0x4d,0x60 = str r5, [r1, #4] +0xfb,0x67 = str r3, [r7, #0x7c] +0x00,0x92 = str r2, [sp] +0x00,0x93 = str r3, [sp] +0x05,0x94 = str r4, [sp, #0x14] +0xff,0x95 = str r5, [sp, #0x3fc] +0xfa,0x50 = str r2, [r7, r3] +0x1c,0x70 = strb r4, [r3] +0x35,0x70 = strb r5, [r6] +0xfe,0x77 = strb r6, [r7, #0x1f] +0x66,0x55 = strb r6, [r4, r5] +0x1b,0x80 = strh r3, [r3] +0x74,0x80 = strh r4, [r6, #2] +0xfd,0x87 = strh r5, [r7, #0x3e] +0x96,0x53 = strh r6, [r2, r6] +0xd1,0x1e = subs r1, r2, #3 +0x03,0x3a = subs r2, #3 +0x08,0x3a = subs r2, #8 +0x83,0xb0 = sub sp, #0xc +0xff,0xb0 = sub sp, #0x1fc +0xd1,0x1a = subs r1, r2, r3 +0x00,0xdf = svc #0 +0xff,0xdf = svc #0xff +0x6b,0xb2 = sxtb r3, r5 +0x2b,0xb2 = sxth r3, r5 +0x0e,0x42 = tst r6, r1 +0xd7,0xb2 = uxtb r7, r2 +0xa1,0xb2 = uxth r1, r4 diff --git a/thirdparty/capstone/suite/MC/ARM/basic-thumb2-instructions-v8.s.cs b/thirdparty/capstone/suite/MC/ARM/basic-thumb2-instructions-v8.s.cs new file mode 100644 index 0000000..a6d4d6f --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/basic-thumb2-instructions-v8.s.cs @@ -0,0 +1 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None diff --git a/thirdparty/capstone/suite/MC/ARM/basic-thumb2-instructions.s.cs b/thirdparty/capstone/suite/MC/ARM/basic-thumb2-instructions.s.cs new file mode 100644 index 0000000..923fbc0 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/basic-thumb2-instructions.s.cs @@ -0,0 +1,1341 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x41,0xf1,0x04,0x00 = adc r0, r1, #4 +0x51,0xf1,0x00,0x00 = adcs r0, r1, #0 +0x42,0xf1,0xff,0x01 = adc r1, r2, #0xff +0x47,0xf1,0x55,0x13 = adc r3, r7, #0x550055 +0x4c,0xf1,0xaa,0x28 = adc r8, r12, #0xaa00aa00 +0x47,0xf1,0xa5,0x39 = adc r9, r7, #0xa5a5a5a5 +0x43,0xf1,0x07,0x45 = adc r5, r3, #0x87000000 +0x42,0xf1,0xff,0x44 = adc r4, r2, #0x7f800000 +0x42,0xf5,0xd0,0x64 = adc r4, r2, #0x680 +0x45,0xeb,0x06,0x04 = adc.w r4, r5, r6 +0x55,0xeb,0x06,0x04 = adcs.w r4, r5, r6 +0x41,0xeb,0x03,0x09 = adc.w r9, r1, r3 +0x51,0xeb,0x03,0x09 = adcs.w r9, r1, r3 +0x41,0xeb,0x33,0x10 = adc.w r0, r1, r3, ror #4 +0x51,0xeb,0xc3,0x10 = adcs.w r0, r1, r3, lsl #7 +0x41,0xeb,0xd3,0x70 = adc.w r0, r1, r3, lsr #0x1f +0x51,0xeb,0x23,0x00 = adcs.w r0, r1, r3, asr #0x20 +0x0a,0xbf = itet eq +0x11,0x1d = addeq r1, r2, #4 +0x03,0xf2,0xff,0x35 = addwne r5, r3, #0x3ff +0x05,0xf2,0x25,0x14 = addweq r4, r5, #0x125 +0x0d,0xf5,0x80,0x62 = add.w r2, sp, #0x400 +0x08,0xf5,0x7f,0x42 = add.w r2, r8, #0xff00 +0x03,0xf2,0x01,0x12 = addw r2, r3, #0x101 +0x03,0xf2,0x01,0x12 = addw r2, r3, #0x101 +0x06,0xf5,0x80,0x7c = add.w r12, r6, #0x100 +0x06,0xf2,0x00,0x1c = addw r12, r6, #0x100 +0x12,0xf5,0xf8,0x71 = adds.w r1, r2, #0x1f0 +0x02,0xf1,0x01,0x02 = add.w r2, r2, #1 +0x00,0xf1,0x20,0x00 = add.w r0, r0, #0x20 +0x38,0x32 = adds r2, #0x38 +0x38,0x32 = adds r2, #0x38 +0x07,0xf1,0xcb,0x31 = add.w r1, r7, #0xcbcbcbcb +0xb2,0xf1,0x10,0x02 = subs.w r2, r2, #0x10 +0xb2,0xf1,0x10,0x02 = subs.w r2, r2, #0x10 +0xa2,0xf2,0x10,0x02 = subw r2, r2, #0x10 +0xa2,0xf2,0x10,0x02 = subw r2, r2, #0x10 +0xa2,0xf2,0x10,0x02 = subw r2, r2, #0x10 +0x02,0xeb,0x08,0x01 = add.w r1, r2, r8 +0x09,0xeb,0x22,0x05 = add.w r5, r9, r2, asr #0x20 +0x13,0xeb,0xc1,0x77 = adds.w r7, r3, r1, lsl #0x1f +0x13,0xeb,0x56,0x60 = adds.w r0, r3, r6, lsr #0x19 +0x08,0xeb,0x31,0x34 = add.w r4, r8, r1, ror #0xc +0xc9,0x19 = adds r1, r1, r7 +0x08,0xbf = it eq +0x59,0x19 = addeq r1, r3, r5 +0x08,0xbf = it eq +0x49,0x19 = addeq r1, r1, r5 +0x08,0xbf = it eq +0x13,0xeb,0x05,0x01 = addseq.w r1, r3, r5 +0x08,0xbf = it eq +0x11,0xeb,0x05,0x01 = addseq.w r1, r1, r5 +0xc2,0x44 = add r10, r8 +0xc2,0x44 = add r10, r8 +0x08,0xbf = it eq +0x51,0x44 = addeq r1, r10 +0x08,0xbf = it eq +0x11,0xeb,0x0a,0x01 = addseq.w r1, r1, r10 +0x08,0xbf = it eq +0xff,0xaf = addeq r7, sp, #0x3fc +0x08,0xbf = it eq +0x7f,0xb0 = addeq sp, #0x1fc +0x0d,0xf1,0x0f,0x07 = add.w r7, sp, #0xf +0x1d,0xf1,0x10,0x07 = adds.w r7, sp, #0x10 +0x0d,0xf1,0x10,0x08 = add.w r8, sp, #0x10 +0x0d,0xf2,0xfc,0x36 = addw r6, sp, #0x3fc +0x0d,0xf2,0xfb,0x36 = addw r6, sp, #0x3fb +0x08,0xbf = it eq +0xe8,0x44 = addeq r8, sp, r8 +0x08,0xbf = it eq +0xcd,0x44 = addeq sp, r9 +0x0d,0xeb,0x0c,0x02 = add.w r2, sp, r12 +0x08,0xbf = it eq +0x0d,0xeb,0x0c,0x02 = addeq.w r2, sp, r12 +0xaf,0xf6,0xc6,0x4b = adr.w r11, #4294964026 +0x0f,0xf2,0x03,0x02 = adr.w r2, #3 +0xaf,0xf2,0x3a,0x3b = adr.w r11, #-0x33a +0xaf,0xf2,0x00,0x01 = subw r1, pc, #0 +0x05,0xf4,0x7f,0x22 = and r2, r5, #0xff000 +0x1c,0xf0,0x0f,0x03 = ands r3, r12, #0xf +0x01,0xf0,0xff,0x01 = and r1, r1, #0xff +0x01,0xf0,0xff,0x01 = and r1, r1, #0xff +0x04,0xf0,0xff,0x35 = and r5, r4, #0xffffffff +0x19,0xf0,0xff,0x31 = ands r1, r9, #0xffffffff +0x09,0xea,0x08,0x04 = and.w r4, r9, r8 +0x04,0xea,0xe8,0x01 = and.w r1, r4, r8, asr #3 +0x11,0xea,0x47,0x02 = ands.w r2, r1, r7, lsl #1 +0x15,0xea,0x12,0x54 = ands.w r4, r5, r2, lsr #0x14 +0x0c,0xea,0x71,0x49 = and.w r9, r12, r1, ror #0x11 +0x4f,0xea,0x23,0x32 = asr.w r2, r3, #0xc +0x5f,0xea,0x23,0x08 = asrs.w r8, r3, #0x20 +0x5f,0xea,0x63,0x02 = asrs.w r2, r3, #1 +0x4f,0xea,0x23,0x12 = asr.w r2, r3, #4 +0x5f,0xea,0xec,0x32 = asrs.w r2, r12, #0xf +0x4f,0xea,0xe3,0x43 = asr.w r3, r3, #0x13 +0x5f,0xea,0xa8,0x08 = asrs.w r8, r8, #2 +0x5f,0xea,0x67,0x17 = asrs.w r7, r7, #5 +0x4f,0xea,0x6c,0x5c = asr.w r12, r12, #0x15 +0x51,0x10 = asrs r1, r2, #1 +0x04,0xbf = itt eq +0x5f,0xea,0x62,0x01 = asrseq.w r1, r2, #1 +0x51,0x10 = asreq r1, r2, #1 +0x44,0xfa,0x02,0xf3 = asr.w r3, r4, r2 +0x41,0xfa,0x02,0xf1 = asr.w r1, r1, r2 +0x54,0xfa,0x08,0xf3 = asrs.w r3, r4, r8 +0x08,0xbf = it eq +0x13,0xf5,0xce,0xa9 = beq.w #-0x2cc64 +0x6f,0xf3,0xd3,0x05 = bfc r5, #3, #0x11 +0x38,0xbf = it lo +0x6f,0xf3,0xd3,0x05 = bfclo r5, #3, #0x11 +0x62,0xf3,0xd3,0x05 = bfi r5, r2, #3, #0x11 +0x18,0xbf = it ne +0x62,0xf3,0xd3,0x05 = bfine r5, r2, #3, #0x11 +0x21,0xf0,0x0f,0x0a = bic r10, r1, #0xf +0x22,0xf0,0xff,0x35 = bic r5, r2, #0xffffffff +0x3a,0xf0,0xff,0x3b = bics r11, r10, #0xffffffff +0x23,0xea,0x06,0x0c = bic.w r12, r3, r6 +0x22,0xea,0x06,0x3b = bic.w r11, r2, r6, lsl #0xc +0x24,0xea,0xd1,0x28 = bic.w r8, r4, r1, lsr #0xb +0x25,0xea,0xd7,0x37 = bic.w r7, r5, r7, lsr #0xf +0x27,0xea,0x29,0x06 = bic.w r6, r7, r9, asr #0x20 +0x26,0xea,0x78,0x05 = bic.w r5, r6, r8, ror #1 +0x21,0xf0,0x0f,0x01 = bic r1, r1, #0xf +0x21,0xea,0x01,0x01 = bic.w r1, r1, r1 +0x24,0xea,0xc2,0x74 = bic.w r4, r4, r2, lsl #0x1f +0x26,0xea,0x13,0x36 = bic.w r6, r6, r3, lsr #0xc +0x27,0xea,0xd4,0x17 = bic.w r7, r7, r4, lsr #7 +0x28,0xea,0xe5,0x38 = bic.w r8, r8, r5, asr #0xf +0x2c,0xea,0x76,0x7c = bic.w r12, r12, r6, ror #0x1d +0x58,0xbf = it pl +0xea,0xbe = bkpt #0xea +0xc5,0xf3,0x00,0x8f = bxj r5 +0x18,0xbf = it ne +0xc7,0xf3,0x00,0x8f = bxjne r7 +0x1f,0xb9 = cbnz r7, #6 +0x37,0xb9 = cbnz r7, #0xc +0x11,0xee,0x81,0x17 = cdp p7, #1, c1, c1, c1, #4 +0x11,0xfe,0x81,0x17 = cdp2 p7, #1, c1, c1, c1, #4 +0xbf,0xf3,0x2f,0x8f = clrex +0x18,0xbf = it ne +0xbf,0xf3,0x2f,0x8f = clrexne +0xb2,0xfa,0x82,0xf1 = clz r1, r2 +0x08,0xbf = it eq +0xb2,0xfa,0x82,0xf1 = clzeq r1, r2 +0x11,0xf1,0x0f,0x0f = cmn.w r1, #0xf +0x18,0xeb,0x06,0x0f = cmn.w r8, r6 +0x11,0xeb,0x86,0x2f = cmn.w r1, r6, lsl #0xa +0x11,0xeb,0x96,0x2f = cmn.w r1, r6, lsr #0xa +0x1d,0xeb,0x96,0x2f = cmn.w sp, r6, lsr #0xa +0x11,0xeb,0xa6,0x2f = cmn.w r1, r6, asr #0xa +0x11,0xeb,0xb6,0x2f = cmn.w r1, r6, ror #0xa +0xb5,0xf5,0x7f,0x4f = cmp.w r5, #0xff00 +0xb4,0xeb,0x0c,0x0f = cmp.w r4, r12 +0xb9,0xeb,0x06,0x3f = cmp.w r9, r6, lsl #0xc +0xb3,0xeb,0xd7,0x7f = cmp.w r3, r7, lsr #0x1f +0xbd,0xeb,0x56,0x0f = cmp.w sp, r6, lsr #1 +0xb2,0xeb,0x25,0x6f = cmp.w r2, r5, asr #0x18 +0xb1,0xeb,0xf4,0x3f = cmp.w r1, r4, ror #0xf +0x12,0xf1,0x02,0x0f = cmn.w r2, #2 +0xb9,0xf1,0x01,0x0f = cmp.w r9, #1 +0x61,0xb6 = cpsie f +0x74,0xb6 = cpsid a +0xaf,0xf3,0x20,0x84 = cpsie.w f +0xaf,0xf3,0x80,0x86 = cpsid.w a +0xaf,0xf3,0x43,0x85 = cpsie i, #3 +0xaf,0xf3,0x43,0x85 = cpsie i, #3 +0xaf,0xf3,0x29,0x87 = cpsid f, #0x9 +0xaf,0xf3,0x29,0x87 = cpsid f, #0x9 +0xaf,0xf3,0x00,0x81 = cps #0 +0xaf,0xf3,0x00,0x81 = cps #0 +0xaf,0xf3,0xf5,0x80 = dbg #5 +0xaf,0xf3,0xf0,0x80 = dbg #0 +0xaf,0xf3,0xff,0x80 = dbg #0xf +0xaf,0xf3,0xf0,0x80 = dbg #0 +0x18,0xbf = it ne +0xaf,0xf3,0xf0,0x80 = dbgne #0 +0xbf,0xf3,0x5f,0x8f = dmb sy +0xbf,0xf3,0x5e,0x8f = dmb st +0xbf,0xf3,0x5d,0x8f = dmb #0xd +0xbf,0xf3,0x5c,0x8f = dmb #0xc +0xbf,0xf3,0x5b,0x8f = dmb ish +0xbf,0xf3,0x5a,0x8f = dmb ishst +0xbf,0xf3,0x59,0x8f = dmb #0x9 +0xbf,0xf3,0x58,0x8f = dmb #0x8 +0xbf,0xf3,0x57,0x8f = dmb nsh +0xbf,0xf3,0x56,0x8f = dmb nshst +0xbf,0xf3,0x55,0x8f = dmb #0x5 +0xbf,0xf3,0x54,0x8f = dmb #0x4 +0xbf,0xf3,0x53,0x8f = dmb osh +0xbf,0xf3,0x52,0x8f = dmb oshst +0xbf,0xf3,0x51,0x8f = dmb #0x1 +0xbf,0xf3,0x50,0x8f = dmb #0x0 +0xbf,0xf3,0x5f,0x8f = dmb sy +0xbf,0xf3,0x5f,0x8f = dmb sy +0xbf,0xf3,0x5e,0x8f = dmb st +0xbf,0xf3,0x5b,0x8f = dmb ish +0xbf,0xf3,0x5b,0x8f = dmb ish +0xbf,0xf3,0x5a,0x8f = dmb ishst +0xbf,0xf3,0x5a,0x8f = dmb ishst +0xbf,0xf3,0x57,0x8f = dmb nsh +0xbf,0xf3,0x57,0x8f = dmb nsh +0xbf,0xf3,0x56,0x8f = dmb nshst +0xbf,0xf3,0x56,0x8f = dmb nshst +0xbf,0xf3,0x53,0x8f = dmb osh +0xbf,0xf3,0x52,0x8f = dmb oshst +0xbf,0xf3,0x5f,0x8f = dmb sy +0xbf,0xf3,0x5f,0x8f = dmb sy +0xbf,0xf3,0x4f,0x8f = dsb sy +0xbf,0xf3,0x4e,0x8f = dsb st +0xbf,0xf3,0x4d,0x8f = dsb #0xd +0xbf,0xf3,0x4c,0x8f = dsb #0xc +0xbf,0xf3,0x4b,0x8f = dsb ish +0xbf,0xf3,0x4a,0x8f = dsb ishst +0xbf,0xf3,0x49,0x8f = dsb #0x9 +0xbf,0xf3,0x48,0x8f = dsb #0x8 +0xbf,0xf3,0x47,0x8f = dsb nsh +0xbf,0xf3,0x46,0x8f = dsb nshst +0xbf,0xf3,0x45,0x8f = dsb #0x5 +0xbf,0xf3,0x44,0x8f = pssbb +0xbf,0xf3,0x43,0x8f = dsb osh +0xbf,0xf3,0x42,0x8f = dsb oshst +0xbf,0xf3,0x41,0x8f = dsb #0x1 +0xbf,0xf3,0x40,0x8f = ssbb +0xbf,0xf3,0x4f,0x8f = dsb sy +0xbf,0xf3,0x4f,0x8f = dsb sy +0xbf,0xf3,0x4e,0x8f = dsb st +0xbf,0xf3,0x4b,0x8f = dsb ish +0xbf,0xf3,0x4b,0x8f = dsb ish +0xbf,0xf3,0x4a,0x8f = dsb ishst +0xbf,0xf3,0x4a,0x8f = dsb ishst +0xbf,0xf3,0x47,0x8f = dsb nsh +0xbf,0xf3,0x47,0x8f = dsb nsh +0xbf,0xf3,0x46,0x8f = dsb nshst +0xbf,0xf3,0x46,0x8f = dsb nshst +0xbf,0xf3,0x43,0x8f = dsb osh +0xbf,0xf3,0x42,0x8f = dsb oshst +0xbf,0xf3,0x4f,0x8f = dsb sy +0xbf,0xf3,0x4f,0x8f = dsb sy +0x85,0xf4,0x70,0x44 = eor r4, r5, #0xf000 +0x85,0xea,0x06,0x04 = eor.w r4, r5, r6 +0x85,0xea,0x46,0x14 = eor.w r4, r5, r6, lsl #5 +0x85,0xea,0x56,0x14 = eor.w r4, r5, r6, lsr #5 +0x85,0xea,0x56,0x14 = eor.w r4, r5, r6, lsr #5 +0x85,0xea,0x66,0x14 = eor.w r4, r5, r6, asr #5 +0x85,0xea,0x76,0x14 = eor.w r4, r5, r6, ror #5 +0xbf,0xf3,0x6f,0x8f = isb sy +0xbf,0xf3,0x6f,0x8f = isb sy +0xbf,0xf3,0x6f,0x8f = isb sy +0xbf,0xf3,0x6f,0x8f = isb sy +0xbf,0xf3,0x6f,0x8f = isb sy +0xbf,0xf3,0x61,0x8f = isb #0x1 +0x0d,0xbf = iteet eq +0x88,0x18 = addeq r0, r1, r2 +0x00,0xbf = nopne +0xf5,0x1b = subne r5, r6, r7 +0x11,0x1d = addeq r1, r2, #4 +0x0d,0xbf = iteet eq +0x88,0x18 = addeq r0, r1, r2 +0x00,0xbf = nopne +0xf5,0x1b = subne r5, r6, r7 +0x11,0x1d = addeq r1, r2, #4 +0x91,0xfd,0x01,0x80 = ldc2 p0, c8, [r1, #4] +0x92,0xfd,0x00,0x71 = ldc2 p1, c7, [r2] +0x13,0xfd,0x38,0x62 = ldc2 p2, c6, [r3, #-0xe0] +0x34,0xfd,0x1e,0x53 = ldc2 p3, c5, [r4, #-0x78]! +0xb5,0xfc,0x04,0x44 = ldc2 p4, c4, [r5], #0x10 +0x36,0xfc,0x12,0x35 = ldc2 p5, c3, [r6], #-0x48 +0xd7,0xfd,0x01,0x26 = ldc2l p6, c2, [r7, #4] +0xd8,0xfd,0x00,0x17 = ldc2l p7, c1, [r8] +0x59,0xfd,0x38,0x08 = ldc2l p8, c0, [r9, #-0xe0] +0x7a,0xfd,0x1e,0x19 = ldc2l p9, c1, [r10, #-0x78]! +0xfb,0xfc,0x04,0x20 = ldc2l p0, c2, [r11], #0x10 +0x7c,0xfc,0x12,0x31 = ldc2l p1, c3, [r12], #-0x48 +0x90,0xed,0x01,0x4c = ldc p12, c4, [r0, #4] +0x91,0xed,0x00,0x5d = ldc p13, c5, [r1] +0x12,0xed,0x38,0x6e = ldc p14, c6, [r2, #-0xe0] +0x33,0xed,0x1e,0x7f = ldc p15, c7, [r3, #-0x78]! +0xb4,0xec,0x04,0x85 = ldc p5, c8, [r4], #0x10 +0x35,0xec,0x12,0x94 = ldc p4, c9, [r5], #-0x48 +0xd6,0xed,0x01,0xa3 = ldcl p3, c10, [r6, #4] +0xd7,0xed,0x00,0xb2 = ldcl p2, c11, [r7] +0x58,0xed,0x38,0xc1 = ldcl p1, c12, [r8, #-0xe0] +0x79,0xed,0x1e,0xd0 = ldcl p0, c13, [r9, #-0x78]! +0xfa,0xec,0x04,0xe6 = ldcl p6, c14, [r10], #0x10 +0x7b,0xec,0x12,0xf7 = ldcl p7, c15, [r11], #-0x48 +0x91,0xfc,0x19,0x82 = ldc2 p2, c8, [r1], {25} +0x94,0xe8,0x30,0x03 = ldm.w r4, {r4, r5, r8, r9} +0x94,0xe8,0x60,0x00 = ldm.w r4, {r5, r6} +0xb5,0xe8,0x08,0x01 = ldm.w r5!, {r3, r8} +0x94,0xe8,0x30,0x03 = ldm.w r4, {r4, r5, r8, r9} +0x94,0xe8,0x60,0x00 = ldm.w r4, {r5, r6} +0xb5,0xe8,0x08,0x01 = ldm.w r5!, {r3, r8} +0xb5,0xe8,0x06,0x00 = ldm.w r5!, {r1, r2} +0x92,0xe8,0x06,0x00 = ldm.w r2, {r1, r2} +0x94,0xe8,0x30,0x03 = ldm.w r4, {r4, r5, r8, r9} +0x94,0xe8,0x60,0x00 = ldm.w r4, {r5, r6} +0xb5,0xe8,0x08,0x01 = ldm.w r5!, {r3, r8} +0x94,0xe8,0x30,0x03 = ldm.w r4, {r4, r5, r8, r9} +0x94,0xe8,0x60,0x00 = ldm.w r4, {r5, r6} +0xb5,0xe8,0x08,0x01 = ldm.w r5!, {r3, r8} +0xb5,0xe8,0x08,0x01 = ldm.w r5!, {r3, r8} +0xbd,0xe8,0xf0,0x8f = pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} +0x14,0xe9,0x30,0x03 = ldmdb r4, {r4, r5, r8, r9} +0x14,0xe9,0x60,0x00 = ldmdb r4, {r5, r6} +0x35,0xe9,0x08,0x01 = ldmdb r5!, {r3, r8} +0x35,0xe9,0x08,0x01 = ldmdb r5!, {r3, r8} +0x14,0xe9,0x60,0x00 = ldmdb r4, {r5, r6} +0x35,0xe9,0x08,0x01 = ldmdb r5!, {r3, r8} +0x55,0xf8,0x04,0x5c = ldr r5, [r5, #-4] +0x35,0x6a = ldr r5, [r6, #0x20] +0xd6,0xf8,0x21,0x50 = ldr.w r5, [r6, #0x21] +0xd6,0xf8,0x01,0x51 = ldr.w r5, [r6, #0x101] +0xd7,0xf8,0x01,0xf1 = ldr.w pc, [r7, #0x101] +0x54,0xf8,0xff,0x2f = ldr r2, [r4, #0xff]! +0x5d,0xf8,0x04,0x8f = ldr r8, [sp, #4]! +0x5d,0xf8,0x04,0xed = ldr lr, [sp, #-4]! +0x54,0xf8,0xff,0x2b = ldr r2, [r4], #0xff +0x5d,0xf8,0x04,0x8b = pop {r8} +0x5d,0xf8,0x04,0xe9 = ldr lr, [sp], #-4 +0x02,0x4f = ldr r7, [pc, #8] +0x02,0x4f = ldr r7, [pc, #8] +0xdf,0xf8,0x08,0x70 = ldr.w r7, [pc, #8] +0xff,0x4c = ldr r4, [pc, #0x3fc] +0x5f,0xf8,0xfc,0x33 = ldr.w r3, [pc, #-0x3fc] +0xdf,0xf8,0x00,0x64 = ldr.w r6, [pc, #0x400] +0x5f,0xf8,0x00,0x04 = ldr.w r0, [pc, #-0x400] +0xdf,0xf8,0xff,0x2f = ldr.w r2, [pc, #0xfff] +0x5f,0xf8,0xff,0x1f = ldr.w r1, [pc, #-0xfff] +0xdf,0xf8,0x84,0x80 = ldr.w r8, [pc, #0x84] +0xdf,0xf8,0x00,0xf1 = ldr.w pc, [pc, #0x100] +0x5f,0xf8,0x90,0xf1 = ldr.w pc, [pc, #-0x190] +0xdf,0xf8,0x04,0xd0 = ldr.w sp, [pc, #4] +0x1f,0xf8,0x00,0x90 = ldrb.w r9, [pc, #-0] +0x1f,0xf9,0x00,0xb0 = ldrsb.w r11, [pc, #-0] +0x3f,0xf8,0x00,0xa0 = ldrh.w r10, [pc, #-0] +0x3f,0xf9,0x00,0x10 = ldrsh.w r1, [pc, #-0] +0x5f,0xf8,0x00,0x50 = ldr.w r5, [pc, #-0] +0x58,0xf8,0x01,0x10 = ldr.w r1, [r8, r1] +0x55,0xf8,0x02,0x40 = ldr.w r4, [r5, r2] +0x50,0xf8,0x32,0x60 = ldr.w r6, [r0, r2, lsl #3] +0x58,0xf8,0x22,0x80 = ldr.w r8, [r8, r2, lsl #2] +0x5d,0xf8,0x12,0x70 = ldr.w r7, [sp, r2, lsl #1] +0x5d,0xf8,0x02,0x70 = ldr.w r7, [sp, r2] +0x15,0xf8,0x04,0x5c = ldrb r5, [r5, #-4] +0x96,0xf8,0x20,0x50 = ldrb.w r5, [r6, #0x20] +0x96,0xf8,0x21,0x50 = ldrb.w r5, [r6, #0x21] +0x96,0xf8,0x01,0x51 = ldrb.w r5, [r6, #0x101] +0x97,0xf8,0x01,0xe1 = ldrb.w lr, [r7, #0x101] +0x18,0xf8,0xff,0x5f = ldrb r5, [r8, #0xff]! +0x15,0xf8,0x04,0x2f = ldrb r2, [r5, #4]! +0x14,0xf8,0x04,0x1d = ldrb r1, [r4, #-4]! +0x13,0xf8,0xff,0xeb = ldrb lr, [r3], #0xff +0x12,0xf8,0x04,0x9b = ldrb r9, [r2], #4 +0x1d,0xf8,0x04,0x39 = ldrb r3, [sp], #-4 +0x18,0xf8,0x01,0x10 = ldrb.w r1, [r8, r1] +0x15,0xf8,0x02,0x40 = ldrb.w r4, [r5, r2] +0x10,0xf8,0x32,0x60 = ldrb.w r6, [r0, r2, lsl #3] +0x18,0xf8,0x22,0x80 = ldrb.w r8, [r8, r2, lsl #2] +0x1d,0xf8,0x12,0x70 = ldrb.w r7, [sp, r2, lsl #1] +0x1d,0xf8,0x02,0x70 = ldrb.w r7, [sp, r2] +0x12,0xf8,0x00,0x1e = ldrbt r1, [r2] +0x18,0xf8,0x00,0x1e = ldrbt r1, [r8] +0x18,0xf8,0x03,0x1e = ldrbt r1, [r8, #3] +0x18,0xf8,0xff,0x1e = ldrbt r1, [r8, #0xff] +0xd6,0xe9,0x06,0x35 = ldrd r3, r5, [r6, #0x18] +0xf6,0xe9,0x06,0x35 = ldrd r3, r5, [r6, #0x18]! +0xf6,0xe8,0x01,0x35 = ldrd r3, r5, [r6], #4 +0x76,0xe8,0x02,0x35 = ldrd r3, r5, [r6], #-8 +0xd6,0xe9,0x00,0x35 = ldrd r3, r5, [r6] +0xd3,0xe9,0x00,0x81 = ldrd r8, r1, [r3] +0x52,0xe9,0x00,0x01 = ldrd r0, r1, [r2, #-0] +0x72,0xe9,0x00,0x01 = ldrd r0, r1, [r2, #-0]! +0x72,0xe8,0x00,0x01 = ldrd r0, r1, [r2], #-0 +0x54,0xe8,0x00,0x1f = ldrex r1, [r4] +0x54,0xe8,0x00,0x8f = ldrex r8, [r4] +0x5d,0xe8,0x20,0x2f = ldrex r2, [sp, #0x80] +0xd7,0xe8,0x4f,0x5f = ldrexb r5, [r7] +0xdc,0xe8,0x5f,0x9f = ldrexh r9, [r12] +0xd4,0xe8,0x7f,0x93 = ldrexd r9, r3, [r4] +0x35,0xf8,0x04,0x5c = ldrh r5, [r5, #-4] +0x35,0x8c = ldrh r5, [r6, #0x20] +0xb6,0xf8,0x21,0x50 = ldrh.w r5, [r6, #0x21] +0xb6,0xf8,0x01,0x51 = ldrh.w r5, [r6, #0x101] +0xb7,0xf8,0x01,0xe1 = ldrh.w lr, [r7, #0x101] +0x38,0xf8,0xff,0x5f = ldrh r5, [r8, #0xff]! +0x35,0xf8,0x04,0x2f = ldrh r2, [r5, #4]! +0x34,0xf8,0x04,0x1d = ldrh r1, [r4, #-4]! +0x33,0xf8,0xff,0xeb = ldrh lr, [r3], #0xff +0x32,0xf8,0x04,0x9b = ldrh r9, [r2], #4 +0x3d,0xf8,0x04,0x39 = ldrh r3, [sp], #-4 +0x38,0xf8,0x01,0x10 = ldrh.w r1, [r8, r1] +0x35,0xf8,0x02,0x40 = ldrh.w r4, [r5, r2] +0x30,0xf8,0x32,0x60 = ldrh.w r6, [r0, r2, lsl #3] +0x38,0xf8,0x22,0x80 = ldrh.w r8, [r8, r2, lsl #2] +0x3d,0xf8,0x12,0x70 = ldrh.w r7, [sp, r2, lsl #1] +0x3d,0xf8,0x02,0x70 = ldrh.w r7, [sp, r2] +0x32,0xf8,0x00,0x1e = ldrht r1, [r2] +0x38,0xf8,0x00,0x1e = ldrht r1, [r8] +0x38,0xf8,0x03,0x1e = ldrht r1, [r8, #3] +0x38,0xf8,0xff,0x1e = ldrht r1, [r8, #0xff] +0x15,0xf9,0x04,0x5c = ldrsb r5, [r5, #-4] +0x96,0xf9,0x20,0x50 = ldrsb.w r5, [r6, #0x20] +0x96,0xf9,0x21,0x50 = ldrsb.w r5, [r6, #0x21] +0x96,0xf9,0x01,0x51 = ldrsb.w r5, [r6, #0x101] +0x97,0xf9,0x01,0xe1 = ldrsb.w lr, [r7, #0x101] +0x18,0xf9,0x01,0x10 = ldrsb.w r1, [r8, r1] +0x15,0xf9,0x02,0x40 = ldrsb.w r4, [r5, r2] +0x10,0xf9,0x32,0x60 = ldrsb.w r6, [r0, r2, lsl #3] +0x18,0xf9,0x22,0x80 = ldrsb.w r8, [r8, r2, lsl #2] +0x1d,0xf9,0x12,0x70 = ldrsb.w r7, [sp, r2, lsl #1] +0x1d,0xf9,0x02,0x70 = ldrsb.w r7, [sp, r2] +0x18,0xf9,0xff,0x5f = ldrsb r5, [r8, #0xff]! +0x15,0xf9,0x04,0x2f = ldrsb r2, [r5, #4]! +0x14,0xf9,0x04,0x1d = ldrsb r1, [r4, #-4]! +0x13,0xf9,0xff,0xeb = ldrsb lr, [r3], #0xff +0x12,0xf9,0x04,0x9b = ldrsb r9, [r2], #4 +0x1d,0xf9,0x04,0x39 = ldrsb r3, [sp], #-4 +0x12,0xf9,0x00,0x1e = ldrsbt r1, [r2] +0x18,0xf9,0x00,0x1e = ldrsbt r1, [r8] +0x18,0xf9,0x03,0x1e = ldrsbt r1, [r8, #3] +0x18,0xf9,0xff,0x1e = ldrsbt r1, [r8, #0xff] +0x35,0xf9,0x04,0x5c = ldrsh r5, [r5, #-4] +0xb6,0xf9,0x20,0x50 = ldrsh.w r5, [r6, #0x20] +0xb6,0xf9,0x21,0x50 = ldrsh.w r5, [r6, #0x21] +0xb6,0xf9,0x01,0x51 = ldrsh.w r5, [r6, #0x101] +0xb7,0xf9,0x01,0xe1 = ldrsh.w lr, [r7, #0x101] +0x38,0xf9,0x01,0x10 = ldrsh.w r1, [r8, r1] +0x35,0xf9,0x02,0x40 = ldrsh.w r4, [r5, r2] +0x30,0xf9,0x32,0x60 = ldrsh.w r6, [r0, r2, lsl #3] +0x38,0xf9,0x22,0x80 = ldrsh.w r8, [r8, r2, lsl #2] +0x3d,0xf9,0x12,0x70 = ldrsh.w r7, [sp, r2, lsl #1] +0x3d,0xf9,0x02,0x70 = ldrsh.w r7, [sp, r2] +0x38,0xf9,0xff,0x5f = ldrsh r5, [r8, #0xff]! +0x35,0xf9,0x04,0x2f = ldrsh r2, [r5, #4]! +0x34,0xf9,0x04,0x1d = ldrsh r1, [r4, #-4]! +0x33,0xf9,0xff,0xeb = ldrsh lr, [r3], #0xff +0x32,0xf9,0x04,0x9b = ldrsh r9, [r2], #4 +0x3d,0xf9,0x04,0x39 = ldrsh r3, [sp], #-4 +0x32,0xf9,0x00,0x1e = ldrsht r1, [r2] +0x38,0xf9,0x00,0x1e = ldrsht r1, [r8] +0x38,0xf9,0x03,0x1e = ldrsht r1, [r8, #3] +0x38,0xf9,0xff,0x1e = ldrsht r1, [r8, #0xff] +0x52,0xf8,0x00,0x1e = ldrt r1, [r2] +0x56,0xf8,0x00,0x2e = ldrt r2, [r6] +0x57,0xf8,0x03,0x3e = ldrt r3, [r7, #3] +0x59,0xf8,0xff,0x4e = ldrt r4, [r9, #0xff] +0x4f,0xea,0x03,0x32 = lsl.w r2, r3, #0xc +0x5f,0xea,0xc3,0x78 = lsls.w r8, r3, #0x1f +0x5f,0xea,0x43,0x02 = lsls.w r2, r3, #1 +0x4f,0xea,0x03,0x12 = lsl.w r2, r3, #4 +0x5f,0xea,0xcc,0x32 = lsls.w r2, r12, #0xf +0x4f,0xea,0xc3,0x43 = lsl.w r3, r3, #0x13 +0x5f,0xea,0x88,0x08 = lsls.w r8, r8, #2 +0x5f,0xea,0x47,0x17 = lsls.w r7, r7, #5 +0x4f,0xea,0x4c,0x5c = lsl.w r12, r12, #0x15 +0x51,0x00 = lsls r1, r2, #1 +0x04,0xbf = itt eq +0x5f,0xea,0x42,0x01 = lslseq.w r1, r2, #1 +0x51,0x00 = lsleq r1, r2, #1 +0x04,0xfa,0x02,0xf3 = lsl.w r3, r4, r2 +0x01,0xfa,0x02,0xf1 = lsl.w r1, r1, r2 +0x14,0xfa,0x08,0xf3 = lsls.w r3, r4, r8 +0x4f,0xea,0x13,0x32 = lsr.w r2, r3, #0xc +0x5f,0xea,0x13,0x08 = lsrs.w r8, r3, #0x20 +0x5f,0xea,0x53,0x02 = lsrs.w r2, r3, #1 +0x4f,0xea,0x13,0x12 = lsr.w r2, r3, #4 +0x5f,0xea,0xdc,0x32 = lsrs.w r2, r12, #0xf +0x4f,0xea,0xd3,0x43 = lsr.w r3, r3, #0x13 +0x5f,0xea,0x98,0x08 = lsrs.w r8, r8, #2 +0x5f,0xea,0x57,0x17 = lsrs.w r7, r7, #5 +0x4f,0xea,0x5c,0x5c = lsr.w r12, r12, #0x15 +0x51,0x08 = lsrs r1, r2, #1 +0x04,0xbf = itt eq +0x5f,0xea,0x52,0x01 = lsrseq.w r1, r2, #1 +0x51,0x08 = lsreq r1, r2, #1 +0x24,0xfa,0x02,0xf3 = lsr.w r3, r4, r2 +0x21,0xfa,0x02,0xf1 = lsr.w r1, r1, r2 +0x34,0xfa,0x08,0xf3 = lsrs.w r3, r4, r8 +0x21,0xee,0x91,0x57 = mcr p7, #1, r5, c1, c1, #4 +0x21,0xfe,0x91,0x57 = mcr2 p7, #1, r5, c1, c1, #4 +0x00,0xee,0x15,0x4e = mcr p14, #0, r4, c0, c5, #0 +0x41,0xfe,0x13,0x24 = mcr2 p4, #2, r2, c1, c3, #0 +0x21,0xee,0x91,0x57 = mcr p7, #1, r5, c1, c1, #4 +0x21,0xfe,0x91,0x57 = mcr2 p7, #1, r5, c1, c1, #4 +0x00,0xee,0x15,0x4e = mcr p14, #0, r4, c0, c5, #0 +0x41,0xfe,0x13,0x24 = mcr2 p4, #2, r2, c1, c3, #0 +0x44,0xec,0xf1,0x57 = mcrr p7, #0xf, r5, r4, c1 +0x44,0xfc,0xf1,0x57 = mcrr2 p7, #0xf, r5, r4, c1 +0x44,0xec,0xf1,0x57 = mcrr p7, #0xf, r5, r4, c1 +0x44,0xfc,0xf1,0x57 = mcrr2 p7, #0xf, r5, r4, c1 +0x02,0xfb,0x03,0x41 = mla r1, r2, r3, r4 +0x02,0xfb,0x13,0x41 = mls r1, r2, r3, r4 +0x15,0x21 = movs r1, #0x15 +0x5f,0xf0,0x15,0x01 = movs.w r1, #0x15 +0x5f,0xf0,0x15,0x08 = movs.w r8, #0x15 +0x4f,0xf6,0xff,0x70 = movw r0, #0xffff +0x4a,0xf6,0x01,0x31 = movw r1, #0xab01 +0x4a,0xf6,0x10,0x31 = movw r1, #0xab10 +0x4f,0xf0,0x7f,0x70 = mov.w r0, #0x3fc0000 +0x4f,0xf0,0x7f,0x70 = mov.w r0, #0x3fc0000 +0x5f,0xf0,0x7f,0x70 = movs.w r0, #0x3fc0000 +0x06,0xbf = itte eq +0x5f,0xf0,0x0c,0x01 = movseq.w r1, #0xc +0x0c,0x21 = moveq r1, #0xc +0x4f,0xf0,0x0c,0x01 = movne.w r1, #0xc +0x4f,0xf4,0xe1,0x76 = mov.w r6, #0x1c2 +0x38,0xbf = it lo +0x4f,0xf0,0xff,0x31 = movlo.w r1, #-1 +0x6f,0xf0,0x02,0x03 = mvn r3, #2 +0x4a,0xf6,0xcd,0x3b = movw r11, #0xabcd +0x01,0x20 = movs r0, #1 +0x18,0xbf = it ne +0x0f,0x23 = movne r3, #0xf +0x04,0xbf = itt eq +0xff,0x20 = moveq r0, #0xff +0x40,0xf2,0x00,0x11 = movweq r1, #0x100 +0x4f,0xea,0x02,0x46 = lsl.w r6, r2, #0x10 +0x4f,0xea,0x02,0x46 = lsl.w r6, r2, #0x10 +0x4f,0xea,0x12,0x46 = lsr.w r6, r2, #0x10 +0x4f,0xea,0x12,0x46 = lsr.w r6, r2, #0x10 +0x16,0x10 = asrs r6, r2, #0x20 +0x5f,0xea,0x22,0x06 = asrs.w r6, r2, #0x20 +0x5f,0xea,0x72,0x16 = rors.w r6, r2, #5 +0x5f,0xea,0x72,0x16 = rors.w r6, r2, #5 +0xac,0x40 = lsls r4, r5 +0x14,0xfa,0x05,0xf4 = lsls.w r4, r4, r5 +0xec,0x40 = lsrs r4, r5 +0x34,0xfa,0x05,0xf4 = lsrs.w r4, r4, r5 +0x2c,0x41 = asrs r4, r5 +0x54,0xfa,0x05,0xf4 = asrs.w r4, r4, r5 +0xec,0x41 = rors r4, r5 +0x74,0xfa,0x05,0xf4 = rors.w r4, r4, r5 +0x04,0xfa,0x05,0xf4 = lsl.w r4, r4, r5 +0x74,0xfa,0x08,0xf4 = rors.w r4, r4, r8 +0x35,0xfa,0x06,0xf4 = lsrs.w r4, r5, r6 +0x01,0xbf = itttt eq +0xac,0x40 = lsleq r4, r5 +0xec,0x40 = lsreq r4, r5 +0x2c,0x41 = asreq r4, r5 +0xec,0x41 = roreq r4, r5 +0x4f,0xea,0x34,0x04 = rrx r4, r4 +0xc0,0xf2,0x07,0x03 = movt r3, #7 +0xcf,0xf6,0xff,0x76 = movt r6, #0xffff +0x08,0xbf = it eq +0xc0,0xf6,0xf0,0x74 = movteq r4, #0xff0 +0x11,0xee,0x92,0x1e = mrc p14, #0, r1, c1, c2, #4 +0xff,0xee,0xd6,0xff = mrc p15, #7, apsr_nzcv, c15, c6, #6 +0x32,0xee,0x12,0x19 = mrc p9, #1, r1, c2, c2, #0 +0x73,0xfe,0x14,0x3c = mrc2 p12, #3, r3, c3, c4, #0 +0x11,0xfe,0x92,0x1e = mrc2 p14, #0, r1, c1, c2, #4 +0xff,0xfe,0x30,0xf8 = mrc2 p8, #7, apsr_nzcv, c15, c0, #1 +0x11,0xee,0x92,0x1e = mrc p14, #0, r1, c1, c2, #4 +0xff,0xee,0xd6,0xff = mrc p15, #7, apsr_nzcv, c15, c6, #6 +0x32,0xee,0x12,0x19 = mrc p9, #1, r1, c2, c2, #0 +0x73,0xfe,0x14,0x3c = mrc2 p12, #3, r3, c3, c4, #0 +0x11,0xfe,0x92,0x1e = mrc2 p14, #0, r1, c1, c2, #4 +0xff,0xfe,0x30,0xf8 = mrc2 p8, #7, apsr_nzcv, c15, c0, #1 +0x54,0xec,0x11,0x57 = mrrc p7, #1, r5, r4, c1 +0x54,0xfc,0x11,0x57 = mrrc2 p7, #1, r5, r4, c1 +0x54,0xec,0x11,0x57 = mrrc p7, #1, r5, r4, c1 +0x54,0xfc,0x11,0x57 = mrrc2 p7, #1, r5, r4, c1 +0xef,0xf3,0x00,0x88 = mrs r8, apsr +0xef,0xf3,0x00,0x88 = mrs r8, apsr +0xff,0xf3,0x00,0x88 = mrs r8, spsr +0x81,0xf3,0x00,0x88 = msr APSR_nzcvq, r1 +0x82,0xf3,0x00,0x84 = msr APSR_g, r2 +0x83,0xf3,0x00,0x88 = msr APSR_nzcvq, r3 +0x84,0xf3,0x00,0x88 = msr APSR_nzcvq, r4 +0x85,0xf3,0x00,0x8c = msr APSR_nzcvqg, r5 +0x86,0xf3,0x00,0x89 = msr CPSR_fc, r6 +0x87,0xf3,0x00,0x81 = msr CPSR_c, r7 +0x88,0xf3,0x00,0x82 = msr CPSR_x, r8 +0x89,0xf3,0x00,0x89 = msr CPSR_fc, r9 +0x8b,0xf3,0x00,0x89 = msr CPSR_fc, r11 +0x8c,0xf3,0x00,0x8e = msr CPSR_fsx, r12 +0x90,0xf3,0x00,0x89 = msr SPSR_fc, r0 +0x95,0xf3,0x00,0x8f = msr SPSR_fsxc, r5 +0x88,0xf3,0x00,0x8f = msr CPSR_fsxc, r8 +0x83,0xf3,0x00,0x89 = msr CPSR_fc, r3 +0x63,0x43 = muls r3, r4, r3 +0x04,0xfb,0x03,0xf3 = mul r3, r4, r3 +0x04,0xfb,0x06,0xf3 = mul r3, r4, r6 +0x08,0xbf = it eq +0x04,0xfb,0x05,0xf3 = muleq r3, r4, r5 +0xd8,0xbf = it le +0x04,0xfb,0x08,0xf4 = mulle r4, r4, r8 +0x06,0xfb,0x05,0xf5 = mul r5, r6, r5 +0x7f,0xf0,0x15,0x08 = mvns r8, #0x15 +0x6f,0xf0,0x7f,0x70 = mvn r0, #0x3fc0000 +0x7f,0xf0,0x7f,0x70 = mvns r0, #0x3fc0000 +0x06,0xbf = itte eq +0x7f,0xf0,0x0c,0x01 = mvnseq r1, #0xc +0x6f,0xf0,0x0c,0x01 = mvneq r1, #0xc +0x6f,0xf0,0x0c,0x01 = mvnne r1, #0xc +0x6f,0xea,0x03,0x02 = mvn.w r2, r3 +0xda,0x43 = mvns r2, r3 +0x6f,0xea,0xc6,0x45 = mvn.w r5, r6, lsl #0x13 +0x6f,0xea,0x56,0x25 = mvn.w r5, r6, lsr #0x9 +0x6f,0xea,0x26,0x15 = mvn.w r5, r6, asr #4 +0x6f,0xea,0xb6,0x15 = mvn.w r5, r6, ror #6 +0x6f,0xea,0x36,0x05 = mvn.w r5, r6, rrx +0x08,0xbf = it eq +0xda,0x43 = mvneq r2, r3 +0xc2,0xf1,0x00,0x05 = rsb.w r5, r2, #0 +0xc8,0xf1,0x00,0x05 = rsb.w r5, r8, #0 +0xaf,0xf3,0x00,0x80 = nop.w +0x65,0xf4,0x70,0x44 = orn r4, r5, #0xf000 +0x65,0xf4,0x70,0x44 = orn r4, r5, #0xf000 +0x65,0xea,0x06,0x04 = orn r4, r5, r6 +0x65,0xea,0x06,0x04 = orn r4, r5, r6 +0x75,0xea,0x06,0x04 = orns r4, r5, r6 +0x75,0xea,0x06,0x04 = orns r4, r5, r6 +0x65,0xea,0x46,0x14 = orn r4, r5, r6, lsl #5 +0x65,0xea,0x46,0x14 = orn r4, r5, r6, lsl #5 +0x75,0xea,0x56,0x14 = orns r4, r5, r6, lsr #5 +0x65,0xea,0x56,0x14 = orn r4, r5, r6, lsr #5 +0x75,0xea,0x66,0x14 = orns r4, r5, r6, asr #5 +0x65,0xea,0x76,0x14 = orn r4, r5, r6, ror #5 +0x45,0xf4,0x70,0x44 = orr r4, r5, #0xf000 +0x45,0xea,0x06,0x04 = orr.w r4, r5, r6 +0x45,0xea,0x46,0x14 = orr.w r4, r5, r6, lsl #5 +0x55,0xea,0x56,0x14 = orrs.w r4, r5, r6, lsr #5 +0x45,0xea,0x56,0x14 = orr.w r4, r5, r6, lsr #5 +0x55,0xea,0x66,0x14 = orrs.w r4, r5, r6, asr #5 +0x45,0xea,0x76,0x14 = orr.w r4, r5, r6, ror #5 +0xc2,0xea,0x03,0x02 = pkhbt r2, r2, r3 +0xc2,0xea,0xc3,0x72 = pkhbt r2, r2, r3, lsl #0x1f +0xc2,0xea,0x03,0x02 = pkhbt r2, r2, r3 +0xc2,0xea,0xc3,0x32 = pkhbt r2, r2, r3, lsl #0xf +0xc3,0xea,0x02,0x02 = pkhbt r2, r3, r2 +0xc2,0xea,0xe3,0x72 = pkhtb r2, r2, r3, asr #0x1f +0xc2,0xea,0xe3,0x32 = pkhtb r2, r2, r3, asr #0xf +0x15,0xf8,0x04,0xfc = pld [r5, #-4] +0x96,0xf8,0x20,0xf0 = pld [r6, #0x20] +0x96,0xf8,0x21,0xf0 = pld [r6, #0x21] +0x96,0xf8,0x01,0xf1 = pld [r6, #0x101] +0x97,0xf8,0x01,0xf1 = pld [r7, #0x101] +0x91,0xf8,0x00,0xf0 = pld [r1] +0x11,0xf8,0x00,0xfc = pld [r1, #-0] +0x11,0xf8,0x00,0xfc = pld [r1, #-0] +0x1f,0xf8,0xff,0xff = pld [pc, #-0xfff] +0x1f,0xf8,0xff,0xff = pld [pc, #-0xfff] +0x18,0xf8,0x01,0xf0 = pld [r8, r1] +0x15,0xf8,0x02,0xf0 = pld [r5, r2] +0x15,0xf8,0x02,0xf0 = pld [r5, r2] +0x10,0xf8,0x32,0xf0 = pld [r0, r2, lsl #3] +0x18,0xf8,0x22,0xf0 = pld [r8, r2, lsl #2] +0x1d,0xf8,0x12,0xf0 = pld [sp, r2, lsl #1] +0x1d,0xf8,0x02,0xf0 = pld [sp, r2] +0x1d,0xf8,0x12,0xf0 = pld [sp, r2, lsl #1] +0x15,0xf9,0x04,0xfc = pli [r5, #-4] +0x96,0xf9,0x20,0xf0 = pli [r6, #0x20] +0x96,0xf9,0x21,0xf0 = pli [r6, #0x21] +0x96,0xf9,0x01,0xf1 = pli [r6, #0x101] +0x97,0xf9,0x01,0xf1 = pli [r7, #0x101] +0x9f,0xf9,0xff,0xff = pli [pc, #0xfff] +0x1f,0xf9,0xff,0xff = pli [pc, #-0xfff] +0x1f,0xf9,0xff,0xff = pli [pc, #-0xfff] +0x18,0xf9,0x01,0xf0 = pli [r8, r1] +0x15,0xf9,0x02,0xf0 = pli [r5, r2] +0x15,0xf9,0x02,0xf0 = pli [r5, r2] +0x10,0xf9,0x32,0xf0 = pli [r0, r2, lsl #3] +0x18,0xf9,0x22,0xf0 = pli [r8, r2, lsl #2] +0x1d,0xf9,0x12,0xf0 = pli [sp, r2, lsl #1] +0x1d,0xf9,0x02,0xf0 = pli [sp, r2] +0x1d,0xf9,0x12,0xf0 = pli [sp, r2, lsl #1] +0xbd,0xe8,0x04,0x02 = pop.w {r2, r9} +0x2d,0xe9,0x04,0x02 = push.w {r2, r9} +0x83,0xfa,0x82,0xf1 = qadd r1, r2, r3 +0x92,0xfa,0x13,0xf1 = qadd16 r1, r2, r3 +0x82,0xfa,0x13,0xf1 = qadd8 r1, r2, r3 +0xc6,0xbf = itte gt +0x83,0xfa,0x82,0xf1 = qaddgt r1, r2, r3 +0x92,0xfa,0x13,0xf1 = qadd16gt r1, r2, r3 +0x82,0xfa,0x13,0xf1 = qadd8le r1, r2, r3 +0x88,0xfa,0x97,0xf6 = qdadd r6, r7, r8 +0x88,0xfa,0xb7,0xf6 = qdsub r6, r7, r8 +0x84,0xbf = itt hi +0x88,0xfa,0x97,0xf6 = qdaddhi r6, r7, r8 +0x88,0xfa,0xb7,0xf6 = qdsubhi r6, r7, r8 +0xec,0xfa,0x10,0xf9 = qsax r9, r12, r0 +0x08,0xbf = it eq +0xec,0xfa,0x10,0xf9 = qsaxeq r9, r12, r0 +0x83,0xfa,0xa2,0xf1 = qsub r1, r2, r3 +0xd2,0xfa,0x13,0xf1 = qsub16 r1, r2, r3 +0xc2,0xfa,0x13,0xf1 = qsub8 r1, r2, r3 +0xd6,0xbf = itet le +0x83,0xfa,0xa2,0xf1 = qsuble r1, r2, r3 +0xd2,0xfa,0x13,0xf1 = qsub16gt r1, r2, r3 +0xc2,0xfa,0x13,0xf1 = qsub8le r1, r2, r3 +0x92,0xfa,0xa2,0xf1 = rbit r1, r2 +0x18,0xbf = it ne +0x92,0xfa,0xa2,0xf1 = rbitne r1, r2 +0x92,0xfa,0x82,0xf1 = rev.w r1, r2 +0x98,0xfa,0x88,0xf2 = rev.w r2, r8 +0x1c,0xbf = itt ne +0x11,0xba = revne r1, r2 +0x98,0xfa,0x88,0xf1 = revne.w r1, r8 +0x92,0xfa,0x92,0xf1 = rev16.w r1, r2 +0x98,0xfa,0x98,0xf2 = rev16.w r2, r8 +0x1c,0xbf = itt ne +0x51,0xba = rev16ne r1, r2 +0x98,0xfa,0x98,0xf1 = rev16ne.w r1, r8 +0x92,0xfa,0xb2,0xf1 = revsh.w r1, r2 +0x98,0xfa,0xb8,0xf2 = revsh.w r2, r8 +0x1c,0xbf = itt ne +0xd1,0xba = revshne r1, r2 +0x98,0xfa,0xb8,0xf1 = revshne.w r1, r8 +0x4f,0xea,0x33,0x32 = ror.w r2, r3, #0xc +0x5f,0xea,0xf3,0x78 = rors.w r8, r3, #0x1f +0x5f,0xea,0x73,0x02 = rors.w r2, r3, #1 +0x4f,0xea,0x33,0x12 = ror.w r2, r3, #4 +0x5f,0xea,0xfc,0x32 = rors.w r2, r12, #0xf +0x4f,0xea,0xf3,0x43 = ror.w r3, r3, #0x13 +0x5f,0xea,0xb8,0x08 = rors.w r8, r8, #2 +0x5f,0xea,0x77,0x17 = rors.w r7, r7, #5 +0x4f,0xea,0x7c,0x5c = ror.w r12, r12, #0x15 +0x64,0xfa,0x02,0xf3 = ror.w r3, r4, r2 +0x61,0xfa,0x02,0xf1 = ror.w r1, r1, r2 +0x74,0xfa,0x08,0xf3 = rors.w r3, r4, r8 +0x4f,0xea,0x32,0x01 = rrx r1, r2 +0x5f,0xea,0x32,0x01 = rrxs r1, r2 +0xb4,0xbf = ite lt +0x4f,0xea,0x3c,0x09 = rrxlt r9, r12 +0x5f,0xea,0x33,0x08 = rrxsge r8, r3 +0xc5,0xf5,0x7f,0x22 = rsb.w r2, r5, #0xff000 +0xdc,0xf1,0x0f,0x03 = rsbs.w r3, r12, #0xf +0xc1,0xf1,0xff,0x01 = rsb.w r1, r1, #0xff +0xc1,0xf1,0xff,0x01 = rsb.w r1, r1, #0xff +0xcb,0xf1,0x00,0x0b = rsb.w r11, r11, #0 +0xc9,0xf1,0x00,0x09 = rsb.w r9, r9, #0 +0x4b,0x42 = rsbs r3, r1, #0 +0xc1,0xf1,0x00,0x03 = rsb.w r3, r1, #0 +0xc4,0xeb,0x08,0x04 = rsb r4, r4, r8 +0xc4,0xeb,0x08,0x04 = rsb r4, r4, r8 +0xc9,0xeb,0x08,0x04 = rsb r4, r9, r8 +0xc9,0xeb,0x08,0x04 = rsb r4, r9, r8 +0xc4,0xeb,0xe8,0x01 = rsb r1, r4, r8, asr #3 +0xc4,0xeb,0xe8,0x01 = rsb r1, r4, r8, asr #3 +0xd1,0xeb,0x47,0x02 = rsbs r2, r1, r7, lsl #1 +0xd1,0xeb,0x47,0x02 = rsbs r2, r1, r7, lsl #1 +0xd1,0xeb,0x02,0x00 = rsbs r0, r1, r2 +0xd1,0xeb,0x02,0x00 = rsbs r0, r1, r2 +0x94,0xfa,0x08,0xf3 = sadd16 r3, r4, r8 +0x18,0xbf = it ne +0x94,0xfa,0x08,0xf3 = sadd16ne r3, r4, r8 +0x84,0xfa,0x08,0xf3 = sadd8 r3, r4, r8 +0x18,0xbf = it ne +0x84,0xfa,0x08,0xf3 = sadd8ne r3, r4, r8 +0xa2,0xfa,0x07,0xf9 = sasx r9, r2, r7 +0x18,0xbf = it ne +0xa5,0xfa,0x06,0xf2 = sasxne r2, r5, r6 +0xa2,0xfa,0x07,0xf9 = sasx r9, r2, r7 +0x18,0xbf = it ne +0xa5,0xfa,0x06,0xf2 = sasxne r2, r5, r6 +0x61,0xf1,0x04,0x00 = sbc r0, r1, #4 +0x71,0xf1,0x00,0x00 = sbcs r0, r1, #0 +0x62,0xf1,0xff,0x01 = sbc r1, r2, #0xff +0x67,0xf1,0x55,0x13 = sbc r3, r7, #0x550055 +0x6c,0xf1,0xaa,0x28 = sbc r8, r12, #0xaa00aa00 +0x67,0xf1,0xa5,0x39 = sbc r9, r7, #0xa5a5a5a5 +0x63,0xf1,0x07,0x45 = sbc r5, r3, #0x87000000 +0x62,0xf1,0xff,0x44 = sbc r4, r2, #0x7f800000 +0x62,0xf5,0xd0,0x64 = sbc r4, r2, #0x680 +0x65,0xeb,0x06,0x04 = sbc.w r4, r5, r6 +0x75,0xeb,0x06,0x04 = sbcs.w r4, r5, r6 +0x61,0xeb,0x03,0x09 = sbc.w r9, r1, r3 +0x71,0xeb,0x03,0x09 = sbcs.w r9, r1, r3 +0x61,0xeb,0x33,0x10 = sbc.w r0, r1, r3, ror #4 +0x71,0xeb,0xc3,0x10 = sbcs.w r0, r1, r3, lsl #7 +0x61,0xeb,0xd3,0x70 = sbc.w r0, r1, r3, lsr #0x1f +0x71,0xeb,0x23,0x00 = sbcs.w r0, r1, r3, asr #0x20 +0x45,0xf3,0x00,0x44 = sbfx r4, r5, #0x10, #1 +0xc8,0xbf = it gt +0x45,0xf3,0x0f,0x44 = sbfxgt r4, r5, #0x10, #0x10 +0xa9,0xfa,0x82,0xf5 = sel r5, r9, r2 +0xd8,0xbf = it le +0xa9,0xfa,0x82,0xf5 = selle r5, r9, r2 +0xaf,0xf3,0x04,0x80 = sev.w +0x08,0xbf = it eq +0xaf,0xf3,0x04,0x80 = seveq.w +0x92,0xfa,0x03,0xf1 = sadd16 r1, r2, r3 +0x82,0xfa,0x03,0xf1 = sadd8 r1, r2, r3 +0xcc,0xbf = ite gt +0x92,0xfa,0x03,0xf1 = sadd16gt r1, r2, r3 +0x82,0xfa,0x03,0xf1 = sadd8le r1, r2, r3 +0xa8,0xfa,0x22,0xf4 = shasx r4, r8, r2 +0xc8,0xbf = it gt +0xa8,0xfa,0x22,0xf4 = shasxgt r4, r8, r2 +0xa8,0xfa,0x22,0xf4 = shasx r4, r8, r2 +0xc8,0xbf = it gt +0xa8,0xfa,0x22,0xf4 = shasxgt r4, r8, r2 +0xe8,0xfa,0x22,0xf4 = shsax r4, r8, r2 +0xc8,0xbf = it gt +0xe8,0xfa,0x22,0xf4 = shsaxgt r4, r8, r2 +0xe8,0xfa,0x22,0xf4 = shsax r4, r8, r2 +0xc8,0xbf = it gt +0xe8,0xfa,0x22,0xf4 = shsaxgt r4, r8, r2 +0xd8,0xfa,0x22,0xf4 = shsub16 r4, r8, r2 +0xc8,0xfa,0x22,0xf4 = shsub8 r4, r8, r2 +0xc4,0xbf = itt gt +0xd8,0xfa,0x22,0xf4 = shsub16gt r4, r8, r2 +0xc8,0xfa,0x22,0xf4 = shsub8gt r4, r8, r2 +0x11,0xfb,0x09,0x03 = smlabb r3, r1, r9, r0 +0x16,0xfb,0x14,0x15 = smlabt r5, r6, r4, r1 +0x12,0xfb,0x23,0x24 = smlatb r4, r2, r3, r2 +0x13,0xfb,0x38,0x48 = smlatt r8, r3, r8, r4 +0xcb,0xbf = itete gt +0x11,0xfb,0x09,0x03 = smlabbgt r3, r1, r9, r0 +0x16,0xfb,0x14,0x15 = smlabtle r5, r6, r4, r1 +0x12,0xfb,0x23,0x24 = smlatbgt r4, r2, r3, r2 +0x13,0xfb,0x38,0x48 = smlattle r8, r3, r8, r4 +0x23,0xfb,0x05,0x82 = smlad r2, r3, r5, r8 +0x23,0xfb,0x15,0x82 = smladx r2, r3, r5, r8 +0x84,0xbf = itt hi +0x23,0xfb,0x05,0x82 = smladhi r2, r3, r5, r8 +0x23,0xfb,0x15,0x82 = smladxhi r2, r3, r5, r8 +0xc5,0xfb,0x08,0x23 = smlal r2, r3, r5, r8 +0x08,0xbf = it eq +0xc5,0xfb,0x08,0x23 = smlaleq r2, r3, r5, r8 +0xc9,0xfb,0x80,0x31 = smlalbb r3, r1, r9, r0 +0xc4,0xfb,0x91,0x56 = smlalbt r5, r6, r4, r1 +0xc3,0xfb,0xa2,0x42 = smlaltb r4, r2, r3, r2 +0xc8,0xfb,0xb4,0x83 = smlaltt r8, r3, r8, r4 +0xad,0xbf = iteet ge +0xc9,0xfb,0x80,0x31 = smlalbbge r3, r1, r9, r0 +0xc4,0xfb,0x91,0x56 = smlalbtlt r5, r6, r4, r1 +0xc3,0xfb,0xa2,0x42 = smlaltblt r4, r2, r3, r2 +0xc8,0xfb,0xb4,0x83 = smlalttge r8, r3, r8, r4 +0xc5,0xfb,0xc8,0x23 = smlald r2, r3, r5, r8 +0xc5,0xfb,0xd8,0x23 = smlaldx r2, r3, r5, r8 +0x0c,0xbf = ite eq +0xc5,0xfb,0xc8,0x23 = smlaldeq r2, r3, r5, r8 +0xc5,0xfb,0xd8,0x23 = smlaldxne r2, r3, r5, r8 +0x33,0xfb,0x0a,0x82 = smlawb r2, r3, r10, r8 +0x33,0xfb,0x15,0x98 = smlawt r8, r3, r5, r9 +0x0c,0xbf = ite eq +0x37,0xfb,0x05,0x82 = smlawbeq r2, r7, r5, r8 +0x33,0xfb,0x10,0x81 = smlawtne r1, r3, r0, r8 +0x43,0xfb,0x05,0x82 = smlsd r2, r3, r5, r8 +0x43,0xfb,0x15,0x82 = smlsdx r2, r3, r5, r8 +0xd4,0xbf = ite le +0x43,0xfb,0x05,0x82 = smlsdle r2, r3, r5, r8 +0x43,0xfb,0x15,0x82 = smlsdxgt r2, r3, r5, r8 +0xd5,0xfb,0xc1,0x29 = smlsld r2, r9, r5, r1 +0xd2,0xfb,0xd8,0x4b = smlsldx r4, r11, r2, r8 +0xac,0xbf = ite ge +0xd5,0xfb,0xc6,0x82 = smlsldge r8, r2, r5, r6 +0xd3,0xfb,0xd8,0x10 = smlsldxlt r1, r0, r3, r8 +0x52,0xfb,0x03,0x41 = smmla r1, r2, r3, r4 +0x53,0xfb,0x12,0x14 = smmlar r4, r3, r2, r1 +0x34,0xbf = ite lo +0x52,0xfb,0x03,0x41 = smmlalo r1, r2, r3, r4 +0x53,0xfb,0x12,0x14 = smmlarhs r4, r3, r2, r1 +0x62,0xfb,0x03,0x41 = smmls r1, r2, r3, r4 +0x63,0xfb,0x12,0x14 = smmlsr r4, r3, r2, r1 +0x34,0xbf = ite lo +0x62,0xfb,0x03,0x41 = smmlslo r1, r2, r3, r4 +0x63,0xfb,0x12,0x14 = smmlsrhs r4, r3, r2, r1 +0x53,0xfb,0x04,0xf2 = smmul r2, r3, r4 +0x52,0xfb,0x11,0xf3 = smmulr r3, r2, r1 +0x34,0xbf = ite lo +0x53,0xfb,0x04,0xf2 = smmullo r2, r3, r4 +0x52,0xfb,0x11,0xf3 = smmulrhs r3, r2, r1 +0x23,0xfb,0x04,0xf2 = smuad r2, r3, r4 +0x22,0xfb,0x11,0xf3 = smuadx r3, r2, r1 +0xb4,0xbf = ite lt +0x23,0xfb,0x04,0xf2 = smuadlt r2, r3, r4 +0x22,0xfb,0x11,0xf3 = smuadxge r3, r2, r1 +0x19,0xfb,0x00,0xf3 = smulbb r3, r9, r0 +0x14,0xfb,0x11,0xf5 = smulbt r5, r4, r1 +0x12,0xfb,0x22,0xf4 = smultb r4, r2, r2 +0x13,0xfb,0x34,0xf8 = smultt r8, r3, r4 +0xab,0xbf = itete ge +0x19,0xfb,0x00,0xf1 = smulbbge r1, r9, r0 +0x16,0xfb,0x14,0xf5 = smulbtlt r5, r6, r4 +0x13,0xfb,0x22,0xf2 = smultbge r2, r3, r2 +0x13,0xfb,0x34,0xf8 = smulttlt r8, r3, r4 +0x80,0xfb,0x01,0x39 = smull r3, r9, r0, r1 +0x08,0xbf = it eq +0x84,0xfb,0x05,0x83 = smulleq r8, r3, r4, r5 +0x39,0xfb,0x00,0xf3 = smulwb r3, r9, r0 +0x39,0xfb,0x12,0xf3 = smulwt r3, r9, r2 +0xcc,0xbf = ite gt +0x39,0xfb,0x00,0xf3 = smulwbgt r3, r9, r0 +0x39,0xfb,0x12,0xf3 = smulwtle r3, r9, r2 +0x40,0xfb,0x01,0xf3 = smusd r3, r0, r1 +0x49,0xfb,0x12,0xf3 = smusdx r3, r9, r2 +0x0c,0xbf = ite eq +0x43,0xfb,0x02,0xf8 = smusdeq r8, r3, r2 +0x44,0xfb,0x13,0xf7 = smusdxne r7, r4, r3 +0x0d,0xe8,0x01,0xc0 = srsdb sp, #1 +0x8d,0xe9,0x00,0xc0 = srsia sp, #0 +0x2d,0xe8,0x13,0xc0 = srsdb sp!, #0x13 +0xad,0xe9,0x02,0xc0 = srsia sp!, #2 +0x8d,0xe9,0x0a,0xc0 = srsia sp, #0xa +0x0d,0xe8,0x09,0xc0 = srsdb sp, #0x9 +0xad,0xe9,0x05,0xc0 = srsia sp!, #5 +0x2d,0xe8,0x05,0xc0 = srsdb sp!, #5 +0x8d,0xe9,0x05,0xc0 = srsia sp, #5 +0xad,0xe9,0x05,0xc0 = srsia sp!, #5 +0x0d,0xe8,0x01,0xc0 = srsdb sp, #1 +0x8d,0xe9,0x00,0xc0 = srsia sp, #0 +0x2d,0xe8,0x13,0xc0 = srsdb sp!, #0x13 +0xad,0xe9,0x02,0xc0 = srsia sp!, #2 +0x8d,0xe9,0x0a,0xc0 = srsia sp, #0xa +0x0d,0xe8,0x09,0xc0 = srsdb sp, #0x9 +0xad,0xe9,0x05,0xc0 = srsia sp!, #5 +0x2d,0xe8,0x05,0xc0 = srsdb sp!, #5 +0x8d,0xe9,0x05,0xc0 = srsia sp, #5 +0xad,0xe9,0x05,0xc0 = srsia sp!, #5 +0x0a,0xf3,0x00,0x08 = ssat r8, #1, r10 +0x0a,0xf3,0x00,0x08 = ssat r8, #1, r10 +0x0a,0xf3,0xc0,0x78 = ssat r8, #1, r10, lsl #0x1f +0x2a,0xf3,0x40,0x08 = ssat r8, #1, r10, asr #1 +0x27,0xf3,0x00,0x02 = ssat16 r2, #1, r7 +0x25,0xf3,0x0f,0x03 = ssat16 r3, #0x10, r5 +0xe3,0xfa,0x04,0xf2 = ssax r2, r3, r4 +0xb8,0xbf = it lt +0xe3,0xfa,0x04,0xf2 = ssaxlt r2, r3, r4 +0xe3,0xfa,0x04,0xf2 = ssax r2, r3, r4 +0xb8,0xbf = it lt +0xe3,0xfa,0x04,0xf2 = ssaxlt r2, r3, r4 +0xd0,0xfa,0x06,0xf1 = ssub16 r1, r0, r6 +0xc2,0xfa,0x04,0xf9 = ssub8 r9, r2, r4 +0x14,0xbf = ite ne +0xd3,0xfa,0x02,0xf5 = ssub16ne r5, r3, r2 +0xc1,0xfa,0x02,0xf5 = ssub8eq r5, r1, r2 +0x81,0xfd,0x01,0x80 = stc2 p0, c8, [r1, #4] +0x82,0xfd,0x00,0x71 = stc2 p1, c7, [r2] +0x03,0xfd,0x38,0x62 = stc2 p2, c6, [r3, #-0xe0] +0x24,0xfd,0x1e,0x53 = stc2 p3, c5, [r4, #-0x78]! +0xa5,0xfc,0x04,0x44 = stc2 p4, c4, [r5], #0x10 +0x26,0xfc,0x12,0x35 = stc2 p5, c3, [r6], #-0x48 +0xc7,0xfd,0x01,0x26 = stc2l p6, c2, [r7, #4] +0xc8,0xfd,0x00,0x17 = stc2l p7, c1, [r8] +0x49,0xfd,0x38,0x08 = stc2l p8, c0, [r9, #-0xe0] +0x6a,0xfd,0x1e,0x19 = stc2l p9, c1, [r10, #-0x78]! +0xeb,0xfc,0x04,0x20 = stc2l p0, c2, [r11], #0x10 +0x6c,0xfc,0x12,0x31 = stc2l p1, c3, [r12], #-0x48 +0x80,0xed,0x01,0x4c = stc p12, c4, [r0, #4] +0x81,0xed,0x00,0x5d = stc p13, c5, [r1] +0x02,0xed,0x38,0x6e = stc p14, c6, [r2, #-0xe0] +0x23,0xed,0x1e,0x7f = stc p15, c7, [r3, #-0x78]! +0xa4,0xec,0x04,0x85 = stc p5, c8, [r4], #0x10 +0x25,0xec,0x12,0x94 = stc p4, c9, [r5], #-0x48 +0xc6,0xed,0x01,0xa3 = stcl p3, c10, [r6, #4] +0xc7,0xed,0x00,0xb2 = stcl p2, c11, [r7] +0x48,0xed,0x38,0xc1 = stcl p1, c12, [r8, #-0xe0] +0x69,0xed,0x1e,0xd0 = stcl p0, c13, [r9, #-0x78]! +0xea,0xec,0x04,0xe6 = stcl p6, c14, [r10], #0x10 +0x6b,0xec,0x12,0xf7 = stcl p7, c15, [r11], #-0x48 +0x81,0xfc,0x19,0x82 = stc2 p2, c8, [r1], {25} +0x84,0xe8,0x30,0x03 = stm.w r4, {r4, r5, r8, r9} +0x84,0xe8,0x60,0x00 = stm.w r4, {r5, r6} +0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8} +0x84,0xe8,0x30,0x03 = stm.w r4, {r4, r5, r8, r9} +0x84,0xe8,0x60,0x00 = stm.w r4, {r5, r6} +0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8} +0xa5,0xe8,0x06,0x00 = stm.w r5!, {r1, r2} +0x82,0xe8,0x06,0x00 = stm.w r2, {r1, r2} +0x84,0xe8,0x30,0x03 = stm.w r4, {r4, r5, r8, r9} +0x84,0xe8,0x60,0x00 = stm.w r4, {r5, r6} +0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8} +0x84,0xe8,0x30,0x03 = stm.w r4, {r4, r5, r8, r9} +0x84,0xe8,0x60,0x00 = stm.w r4, {r5, r6} +0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8} +0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8} +0x04,0xe9,0x30,0x03 = stmdb r4, {r4, r5, r8, r9} +0x04,0xe9,0x60,0x00 = stmdb r4, {r5, r6} +0x25,0xe9,0x08,0x01 = stmdb r5!, {r3, r8} +0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8} +0x05,0xe9,0x03,0x00 = stmdb r5, {r0, r1} +0x45,0xf8,0x04,0x5c = str r5, [r5, #-4] +0x35,0x62 = str r5, [r6, #0x20] +0xc6,0xf8,0x21,0x50 = str.w r5, [r6, #0x21] +0xc6,0xf8,0x01,0x51 = str.w r5, [r6, #0x101] +0xc7,0xf8,0x01,0xf1 = str.w pc, [r7, #0x101] +0x44,0xf8,0xff,0x2f = str r2, [r4, #0xff]! +0x4d,0xf8,0x04,0x8f = str r8, [sp, #4]! +0x4d,0xf8,0x04,0xed = str lr, [sp, #-4]! +0x44,0xf8,0xff,0x2b = str r2, [r4], #0xff +0x4d,0xf8,0x04,0x8b = str r8, [sp], #4 +0x4d,0xf8,0x04,0xe9 = str lr, [sp], #-4 +0x48,0xf8,0x01,0x10 = str.w r1, [r8, r1] +0x45,0xf8,0x02,0x40 = str.w r4, [r5, r2] +0x40,0xf8,0x32,0x60 = str.w r6, [r0, r2, lsl #3] +0x48,0xf8,0x22,0x80 = str.w r8, [r8, r2, lsl #2] +0x4d,0xf8,0x12,0x70 = str.w r7, [sp, r2, lsl #1] +0x4d,0xf8,0x02,0x70 = str.w r7, [sp, r2] +0x05,0xf8,0x04,0x5c = strb r5, [r5, #-4] +0x86,0xf8,0x20,0x50 = strb.w r5, [r6, #0x20] +0x86,0xf8,0x21,0x50 = strb.w r5, [r6, #0x21] +0x86,0xf8,0x01,0x51 = strb.w r5, [r6, #0x101] +0x87,0xf8,0x01,0xe1 = strb.w lr, [r7, #0x101] +0x08,0xf8,0xff,0x5f = strb r5, [r8, #0xff]! +0x05,0xf8,0x04,0x2f = strb r2, [r5, #4]! +0x04,0xf8,0x04,0x1d = strb r1, [r4, #-4]! +0x03,0xf8,0xff,0xeb = strb lr, [r3], #0xff +0x02,0xf8,0x04,0x9b = strb r9, [r2], #4 +0x0d,0xf8,0x04,0x39 = strb r3, [sp], #-4 +0x08,0xf8,0x00,0x4d = strb r4, [r8, #-0]! +0x00,0xf8,0x00,0x19 = strb r1, [r0], #-0 +0x08,0xf8,0x01,0x10 = strb.w r1, [r8, r1] +0x05,0xf8,0x02,0x40 = strb.w r4, [r5, r2] +0x00,0xf8,0x32,0x60 = strb.w r6, [r0, r2, lsl #3] +0x08,0xf8,0x22,0x80 = strb.w r8, [r8, r2, lsl #2] +0x0d,0xf8,0x12,0x70 = strb.w r7, [sp, r2, lsl #1] +0x0d,0xf8,0x02,0x70 = strb.w r7, [sp, r2] +0x02,0xf8,0x00,0x1e = strbt r1, [r2] +0x08,0xf8,0x00,0x1e = strbt r1, [r8] +0x08,0xf8,0x03,0x1e = strbt r1, [r8, #3] +0x08,0xf8,0xff,0x1e = strbt r1, [r8, #0xff] +0xc6,0xe9,0x06,0x35 = strd r3, r5, [r6, #0x18] +0xe6,0xe9,0x06,0x35 = strd r3, r5, [r6, #0x18]! +0xe6,0xe8,0x01,0x35 = strd r3, r5, [r6], #4 +0x66,0xe8,0x02,0x35 = strd r3, r5, [r6], #-8 +0xc6,0xe9,0x00,0x35 = strd r3, r5, [r6] +0xc3,0xe9,0x00,0x81 = strd r8, r1, [r3] +0x42,0xe9,0x00,0x01 = strd r0, r1, [r2, #-0] +0x62,0xe9,0x00,0x01 = strd r0, r1, [r2, #-0]! +0x62,0xe8,0x00,0x01 = strd r0, r1, [r2], #-0 +0xc2,0xe9,0x40,0x01 = strd r0, r1, [r2, #0x100] +0xe2,0xe9,0x40,0x01 = strd r0, r1, [r2, #0x100]! +0xe2,0xe8,0x40,0x01 = strd r0, r1, [r2], #0x100 +0x44,0xe8,0x00,0x81 = strex r1, r8, [r4] +0x44,0xe8,0x00,0x28 = strex r8, r2, [r4] +0x4d,0xe8,0x20,0xc2 = strex r2, r12, [sp, #0x80] +0xc7,0xe8,0x45,0x1f = strexb r5, r1, [r7] +0xcc,0xe8,0x59,0x7f = strexh r9, r7, [r12] +0xc4,0xe8,0x79,0x36 = strexd r9, r3, r6, [r4] +0x25,0xf8,0x04,0x5c = strh r5, [r5, #-4] +0x35,0x84 = strh r5, [r6, #0x20] +0xa6,0xf8,0x21,0x50 = strh.w r5, [r6, #0x21] +0xa6,0xf8,0x01,0x51 = strh.w r5, [r6, #0x101] +0xa7,0xf8,0x01,0xe1 = strh.w lr, [r7, #0x101] +0x28,0xf8,0xff,0x5f = strh r5, [r8, #0xff]! +0x25,0xf8,0x04,0x2f = strh r2, [r5, #4]! +0x24,0xf8,0x04,0x1d = strh r1, [r4, #-4]! +0x23,0xf8,0xff,0xeb = strh lr, [r3], #0xff +0x22,0xf8,0x04,0x9b = strh r9, [r2], #4 +0x2d,0xf8,0x04,0x39 = strh r3, [sp], #-4 +0x28,0xf8,0x01,0x10 = strh.w r1, [r8, r1] +0x25,0xf8,0x02,0x40 = strh.w r4, [r5, r2] +0x20,0xf8,0x32,0x60 = strh.w r6, [r0, r2, lsl #3] +0x28,0xf8,0x22,0x80 = strh.w r8, [r8, r2, lsl #2] +0x2d,0xf8,0x12,0x70 = strh.w r7, [sp, r2, lsl #1] +0x2d,0xf8,0x02,0x70 = strh.w r7, [sp, r2] +0x22,0xf8,0x00,0x1e = strht r1, [r2] +0x28,0xf8,0x00,0x1e = strht r1, [r8] +0x28,0xf8,0x03,0x1e = strht r1, [r8, #3] +0x28,0xf8,0xff,0x1e = strht r1, [r8, #0xff] +0x42,0xf8,0x00,0x1e = strt r1, [r2] +0x48,0xf8,0x00,0x1e = strt r1, [r8] +0x48,0xf8,0x03,0x1e = strt r1, [r8, #3] +0x48,0xf8,0xff,0x1e = strt r1, [r8, #0xff] +0x0a,0xbf = itet eq +0x11,0x1f = subeq r1, r2, #4 +0xa3,0xf2,0xff,0x35 = subwne r5, r3, #0x3ff +0xa5,0xf2,0x25,0x14 = subweq r4, r5, #0x125 +0xad,0xf5,0x80,0x62 = sub.w r2, sp, #0x400 +0xa8,0xf5,0x7f,0x42 = sub.w r2, r8, #0xff00 +0xa3,0xf2,0x01,0x12 = subw r2, r3, #0x101 +0xa3,0xf2,0x01,0x12 = subw r2, r3, #0x101 +0xa6,0xf5,0x80,0x7c = sub.w r12, r6, #0x100 +0xa6,0xf2,0x00,0x1c = subw r12, r6, #0x100 +0xb2,0xf5,0xf8,0x71 = subs.w r1, r2, #0x1f0 +0xa2,0xf1,0x01,0x02 = sub.w r2, r2, #1 +0xa0,0xf1,0x20,0x00 = sub.w r0, r0, #0x20 +0x38,0x3a = subs r2, #0x38 +0x38,0x3a = subs r2, #0x38 +0xa5,0xeb,0x06,0x04 = sub.w r4, r5, r6 +0xa5,0xeb,0x46,0x14 = sub.w r4, r5, r6, lsl #5 +0xa5,0xeb,0x56,0x14 = sub.w r4, r5, r6, lsr #5 +0xa5,0xeb,0x56,0x14 = sub.w r4, r5, r6, lsr #5 +0xa5,0xeb,0x66,0x14 = sub.w r4, r5, r6, asr #5 +0xa5,0xeb,0x76,0x14 = sub.w r4, r5, r6, ror #5 +0xa2,0xeb,0x3c,0x05 = sub.w r5, r2, r12, rrx +0xad,0xeb,0x0c,0x02 = sub.w r2, sp, r12 +0xad,0xeb,0x0c,0x0d = sub.w sp, sp, r12 +0xad,0xeb,0x0c,0x0d = sub.w sp, sp, r12 +0xad,0xeb,0x0c,0x02 = sub.w r2, sp, r12 +0xad,0xeb,0x0c,0x0d = sub.w sp, sp, r12 +0xad,0xeb,0x0c,0x0d = sub.w sp, sp, r12 +0x00,0xdf = svc #0 +0x08,0xbf = it eq +0xff,0xdf = svceq #0xff +0x18,0xbf = it ne +0x21,0xdf = svcne #0x21 +0x04,0xbf = itt eq +0x00,0xdf = svceq #0 +0x01,0xdf = svceq #1 +0x43,0xfa,0x84,0xf2 = sxtab r2, r3, r4 +0x45,0xfa,0x86,0xf4 = sxtab r4, r5, r6 +0xb8,0xbf = it lt +0x42,0xfa,0x99,0xf6 = sxtablt r6, r2, r9, ror #8 +0x41,0xfa,0xa4,0xf5 = sxtab r5, r1, r4, ror #0x10 +0x48,0xfa,0xb3,0xf7 = sxtab r7, r8, r3, ror #0x18 +0x22,0xfa,0x87,0xf6 = sxtab16 r6, r2, r7 +0x25,0xfa,0x98,0xf3 = sxtab16 r3, r5, r8, ror #8 +0x22,0xfa,0xa1,0xf3 = sxtab16 r3, r2, r1, ror #0x10 +0x14,0xbf = ite ne +0x21,0xfa,0x84,0xf0 = sxtab16ne r0, r1, r4 +0x22,0xfa,0xb3,0xf1 = sxtab16eq r1, r2, r3, ror #0x18 +0x03,0xfa,0x89,0xf1 = sxtah r1, r3, r9 +0x08,0xfa,0x93,0xf3 = sxtah r3, r8, r3, ror #8 +0x03,0xfa,0xb3,0xf9 = sxtah r9, r3, r3, ror #0x18 +0x8c,0xbf = ite hi +0x01,0xfa,0x86,0xf6 = sxtahhi r6, r1, r6 +0x02,0xfa,0xa4,0xf2 = sxtahls r2, r2, r4, ror #0x10 +0x75,0xb2 = sxtb r5, r6 +0x4f,0xfa,0x99,0xf6 = sxtb.w r6, r9, ror #8 +0x4f,0xfa,0xb3,0xf8 = sxtb.w r8, r3, ror #0x18 +0xac,0xbf = ite ge +0x62,0xb2 = sxtbge r2, r4 +0x4f,0xfa,0xa1,0xf5 = sxtblt.w r5, r1, ror #0x10 +0x4f,0xfa,0x88,0xf7 = sxtb.w r7, r8 +0x2f,0xfa,0x84,0xf1 = sxtb16 r1, r4 +0x2f,0xfa,0x87,0xf6 = sxtb16 r6, r7 +0x2f,0xfa,0xa1,0xf3 = sxtb16 r3, r1, ror #0x10 +0x2c,0xbf = ite hs +0x2f,0xfa,0x95,0xf3 = sxtb16hs r3, r5, ror #8 +0x2f,0xfa,0xb3,0xf2 = sxtb16lo r2, r3, ror #0x18 +0x31,0xb2 = sxth r1, r6 +0x0f,0xfa,0x98,0xf3 = sxth.w r3, r8, ror #8 +0x0f,0xfa,0xb3,0xf9 = sxth.w r9, r3, ror #0x18 +0x1c,0xbf = itt ne +0x0f,0xfa,0x89,0xf3 = sxthne.w r3, r9 +0x0f,0xfa,0xa2,0xf2 = sxthne.w r2, r2, ror #0x10 +0x0f,0xfa,0x88,0xf7 = sxth.w r7, r8 +0x75,0xb2 = sxtb r5, r6 +0x4f,0xfa,0x99,0xf6 = sxtb.w r6, r9, ror #8 +0x4f,0xfa,0xb3,0xf8 = sxtb.w r8, r3, ror #0x18 +0xac,0xbf = ite ge +0x62,0xb2 = sxtbge r2, r4 +0x4f,0xfa,0xa1,0xf5 = sxtblt.w r5, r1, ror #0x10 +0x2f,0xfa,0x84,0xf1 = sxtb16 r1, r4 +0x2f,0xfa,0x87,0xf6 = sxtb16 r6, r7 +0x2f,0xfa,0xa1,0xf3 = sxtb16 r3, r1, ror #0x10 +0x2c,0xbf = ite hs +0x2f,0xfa,0x95,0xf3 = sxtb16hs r3, r5, ror #8 +0x2f,0xfa,0xb3,0xf2 = sxtb16lo r2, r3, ror #0x18 +0x31,0xb2 = sxth r1, r6 +0x0f,0xfa,0x98,0xf3 = sxth.w r3, r8, ror #8 +0x0f,0xfa,0xb3,0xf9 = sxth.w r9, r3, ror #0x18 +0x1c,0xbf = itt ne +0x0f,0xfa,0x89,0xf3 = sxthne.w r3, r9 +0x0f,0xfa,0xa2,0xf2 = sxthne.w r2, r2, ror #0x10 +0xd3,0xe8,0x08,0xf0 = tbb [r3, r8] +0xd3,0xe8,0x18,0xf0 = tbh [r3, r8, lsl #1] +0x08,0xbf = it eq +0xd3,0xe8,0x08,0xf0 = tbbeq [r3, r8] +0x28,0xbf = it hs +0xd3,0xe8,0x18,0xf0 = tbhhs [r3, r8, lsl #1] +0x95,0xf4,0x70,0x4f = teq.w r5, #0xf000 +0x94,0xea,0x05,0x0f = teq.w r4, r5 +0x94,0xea,0x45,0x1f = teq.w r4, r5, lsl #5 +0x94,0xea,0x55,0x1f = teq.w r4, r5, lsr #5 +0x94,0xea,0x55,0x1f = teq.w r4, r5, lsr #5 +0x94,0xea,0x65,0x1f = teq.w r4, r5, asr #5 +0x94,0xea,0x75,0x1f = teq.w r4, r5, ror #5 +0x15,0xf4,0x70,0x4f = tst.w r5, #0xf000 +0x2a,0x42 = tst r2, r5 +0x13,0xea,0x4c,0x1f = tst.w r3, r12, lsl #5 +0x14,0xea,0x1b,0x1f = tst.w r4, r11, lsr #4 +0x15,0xea,0x1a,0x3f = tst.w r5, r10, lsr #0xc +0x16,0xea,0xa9,0x7f = tst.w r6, r9, asr #0x1e +0x17,0xea,0xb8,0x0f = tst.w r7, r8, ror #2 +0x92,0xfa,0x43,0xf1 = uadd16 r1, r2, r3 +0x82,0xfa,0x43,0xf1 = uadd8 r1, r2, r3 +0xcc,0xbf = ite gt +0x92,0xfa,0x43,0xf1 = uadd16gt r1, r2, r3 +0x82,0xfa,0x43,0xf1 = uadd8le r1, r2, r3 +0xac,0xfa,0x40,0xf9 = uasx r9, r12, r0 +0x08,0xbf = it eq +0xac,0xfa,0x40,0xf9 = uasxeq r9, r12, r0 +0xac,0xfa,0x40,0xf9 = uasx r9, r12, r0 +0x08,0xbf = it eq +0xac,0xfa,0x40,0xf9 = uasxeq r9, r12, r0 +0xc5,0xf3,0x00,0x44 = ubfx r4, r5, #0x10, #1 +0xc8,0xbf = it gt +0xc5,0xf3,0x0f,0x44 = ubfxgt r4, r5, #0x10, #0x10 +0x98,0xfa,0x62,0xf4 = uhadd16 r4, r8, r2 +0x88,0xfa,0x62,0xf4 = uhadd8 r4, r8, r2 +0xc4,0xbf = itt gt +0x98,0xfa,0x62,0xf4 = uhadd16gt r4, r8, r2 +0x88,0xfa,0x62,0xf4 = uhadd8gt r4, r8, r2 +0xa1,0xfa,0x65,0xf4 = uhasx r4, r1, r5 +0xe6,0xfa,0x66,0xf5 = uhsax r5, r6, r6 +0xc4,0xbf = itt gt +0xa9,0xfa,0x68,0xf6 = uhasxgt r6, r9, r8 +0xe8,0xfa,0x6c,0xf7 = uhsaxgt r7, r8, r12 +0xa1,0xfa,0x65,0xf4 = uhasx r4, r1, r5 +0xe6,0xfa,0x66,0xf5 = uhsax r5, r6, r6 +0xc4,0xbf = itt gt +0xa9,0xfa,0x68,0xf6 = uhasxgt r6, r9, r8 +0xe8,0xfa,0x6c,0xf7 = uhsaxgt r7, r8, r12 +0xd8,0xfa,0x63,0xf5 = uhsub16 r5, r8, r3 +0xc7,0xfa,0x66,0xf1 = uhsub8 r1, r7, r6 +0xbc,0xbf = itt lt +0xd9,0xfa,0x6c,0xf4 = uhsub16lt r4, r9, r12 +0xc1,0xfa,0x65,0xf3 = uhsub8lt r3, r1, r5 +0xe5,0xfb,0x66,0x34 = umaal r3, r4, r5, r6 +0xb8,0xbf = it lt +0xe5,0xfb,0x66,0x34 = umaallt r3, r4, r5, r6 +0xe6,0xfb,0x08,0x24 = umlal r2, r4, r6, r8 +0xc8,0xbf = it gt +0xe2,0xfb,0x06,0x61 = umlalgt r6, r1, r2, r6 +0xa6,0xfb,0x08,0x24 = umull r2, r4, r6, r8 +0xc8,0xbf = it gt +0xa2,0xfb,0x06,0x61 = umullgt r6, r1, r2, r6 +0x92,0xfa,0x53,0xf1 = uqadd16 r1, r2, r3 +0x84,0xfa,0x58,0xf3 = uqadd8 r3, r4, r8 +0xcc,0xbf = ite gt +0x97,0xfa,0x59,0xf4 = uqadd16gt r4, r7, r9 +0x81,0xfa,0x52,0xf8 = uqadd8le r8, r1, r2 +0xa2,0xfa,0x53,0xf1 = uqasx r1, r2, r3 +0xe4,0xfa,0x58,0xf3 = uqsax r3, r4, r8 +0xcc,0xbf = ite gt +0xa7,0xfa,0x59,0xf4 = uqasxgt r4, r7, r9 +0xe1,0xfa,0x52,0xf8 = uqsaxle r8, r1, r2 +0xa2,0xfa,0x53,0xf1 = uqasx r1, r2, r3 +0xe4,0xfa,0x58,0xf3 = uqsax r3, r4, r8 +0xcc,0xbf = ite gt +0xa7,0xfa,0x59,0xf4 = uqasxgt r4, r7, r9 +0xe1,0xfa,0x52,0xf8 = uqsaxle r8, r1, r2 +0xc2,0xfa,0x59,0xf8 = uqsub8 r8, r2, r9 +0xd9,0xfa,0x57,0xf1 = uqsub16 r1, r9, r7 +0xcc,0xbf = ite gt +0xc1,0xfa,0x56,0xf3 = uqsub8gt r3, r1, r6 +0xd6,0xfa,0x54,0xf4 = uqsub16le r4, r6, r4 +0x79,0xfb,0x07,0xf1 = usad8 r1, r9, r7 +0x72,0xfb,0x09,0xc8 = usada8 r8, r2, r9, r12 +0xcc,0xbf = ite gt +0x71,0xfb,0x06,0x93 = usada8gt r3, r1, r6, r9 +0x76,0xfb,0x04,0xf4 = usad8le r4, r6, r4 +0x8a,0xf3,0x01,0x08 = usat r8, #1, r10 +0x8a,0xf3,0x04,0x08 = usat r8, #4, r10 +0x8a,0xf3,0xc5,0x78 = usat r8, #5, r10, lsl #0x1f +0xaa,0xf3,0x50,0x08 = usat r8, #0x10, r10, asr #1 +0xa7,0xf3,0x02,0x02 = usat16 r2, #2, r7 +0xa5,0xf3,0x0f,0x03 = usat16 r3, #0xf, r5 +0xe3,0xfa,0x44,0xf2 = usax r2, r3, r4 +0x18,0xbf = it ne +0xe1,0xfa,0x49,0xf6 = usaxne r6, r1, r9 +0xe3,0xfa,0x44,0xf2 = usax r2, r3, r4 +0x18,0xbf = it ne +0xe1,0xfa,0x49,0xf6 = usaxne r6, r1, r9 +0xd2,0xfa,0x47,0xf4 = usub16 r4, r2, r7 +0xc8,0xfa,0x45,0xf1 = usub8 r1, r8, r5 +0x8c,0xbf = ite hi +0xd1,0xfa,0x43,0xf1 = usub16hi r1, r1, r3 +0xc2,0xfa,0x43,0xf9 = usub8ls r9, r2, r3 +0x53,0xfa,0x84,0xf2 = uxtab r2, r3, r4 +0x55,0xfa,0x86,0xf4 = uxtab r4, r5, r6 +0xb8,0xbf = it lt +0x52,0xfa,0x99,0xf6 = uxtablt r6, r2, r9, ror #8 +0x51,0xfa,0xa4,0xf5 = uxtab r5, r1, r4, ror #0x10 +0x58,0xfa,0xb3,0xf7 = uxtab r7, r8, r3, ror #0x18 +0xa8,0xbf = it ge +0x31,0xfa,0x84,0xf0 = uxtab16ge r0, r1, r4 +0x32,0xfa,0x87,0xf6 = uxtab16 r6, r2, r7 +0x35,0xfa,0x98,0xf3 = uxtab16 r3, r5, r8, ror #8 +0x32,0xfa,0xa1,0xf3 = uxtab16 r3, r2, r1, ror #0x10 +0x08,0xbf = it eq +0x32,0xfa,0xb3,0xf1 = uxtab16eq r1, r2, r3, ror #0x18 +0x13,0xfa,0x89,0xf1 = uxtah r1, r3, r9 +0x88,0xbf = it hi +0x11,0xfa,0x86,0xf6 = uxtahhi r6, r1, r6 +0x18,0xfa,0x93,0xf3 = uxtah r3, r8, r3, ror #8 +0x38,0xbf = it lo +0x12,0xfa,0xa4,0xf2 = uxtahlo r2, r2, r4, ror #0x10 +0x13,0xfa,0xb3,0xf9 = uxtah r9, r3, r3, ror #0x18 +0xa8,0xbf = it ge +0xe2,0xb2 = uxtbge r2, r4 +0xf5,0xb2 = uxtb r5, r6 +0x5f,0xfa,0x99,0xf6 = uxtb.w r6, r9, ror #8 +0x38,0xbf = it lo +0x5f,0xfa,0xa1,0xf5 = uxtblo.w r5, r1, ror #0x10 +0x5f,0xfa,0xb3,0xf8 = uxtb.w r8, r3, ror #0x18 +0x5f,0xfa,0x88,0xf7 = uxtb.w r7, r8 +0x3f,0xfa,0x84,0xf1 = uxtb16 r1, r4 +0x3f,0xfa,0x87,0xf6 = uxtb16 r6, r7 +0x28,0xbf = it hs +0x3f,0xfa,0x95,0xf3 = uxtb16hs r3, r5, ror #8 +0x3f,0xfa,0xa1,0xf3 = uxtb16 r3, r1, ror #0x10 +0xa8,0xbf = it ge +0x3f,0xfa,0xb3,0xf2 = uxtb16ge r2, r3, ror #0x18 +0x18,0xbf = it ne +0x1f,0xfa,0x89,0xf3 = uxthne.w r3, r9 +0xb1,0xb2 = uxth r1, r6 +0x1f,0xfa,0x98,0xf3 = uxth.w r3, r8, ror #8 +0xd8,0xbf = it le +0x1f,0xfa,0xa2,0xf2 = uxthle.w r2, r2, ror #0x10 +0x1f,0xfa,0xb3,0xf9 = uxth.w r9, r3, ror #0x18 +0x1f,0xfa,0x88,0xf7 = uxth.w r7, r8 +0x20,0xbf = wfe +0x30,0xbf = wfi +0x10,0xbf = yield +0xb6,0xbf = itet lt +0x20,0xbf = wfelt +0x30,0xbf = wfige +0x10,0xbf = yieldlt +0xaf,0xf3,0x04,0x80 = sev.w +0xaf,0xf3,0x03,0x80 = wfi.w +0xaf,0xf3,0x02,0x80 = wfe.w +0xaf,0xf3,0x01,0x80 = yield.w +0xaf,0xf3,0x00,0x80 = nop.w +0x40,0xbf = sev +0x30,0xbf = wfi +0x20,0xbf = wfe +0x10,0xbf = yield +0x00,0xbf = nop +0xb6,0xbf = itet lt +0xf0,0xbf = hintlt #0xf +0xaf,0xf3,0x10,0x80 = hintge.w #0x10 +0xaf,0xf3,0xef,0x80 = hintlt.w #0xef +0x70,0xbf = hint #7 +0xaf,0xf3,0x07,0x80 = hint.w #7 +0x9f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #0x16] +0xbf,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #0x16] +0x9f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #0x16] +0xbf,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #0x16] +0xdf,0xf8,0x16,0xb0 = ldr.w r11, [pc, #0x16] +0x9f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #0x16] +0xbf,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #0x16] +0x9f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #0x16] +0xbf,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #0x16] +0x5f,0xf8,0x16,0xb0 = ldr.w r11, [pc, #-0x16] +0x1f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #-0x16] +0x3f,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #-0x16] +0x1f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #-0x16] +0x3f,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #-0x16] +0x5f,0xf8,0x16,0xb0 = ldr.w r11, [pc, #-0x16] +0x1f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #-0x16] +0x3f,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #-0x16] +0x1f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #-0x16] +0x3f,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #-0x16] +0x03,0x49 = ldr r1, [pc, #0xc] +0xde,0xf3,0x04,0x8f = subs pc, lr, #4 diff --git a/thirdparty/capstone/suite/MC/ARM/bfloat16-a32.s.cs b/thirdparty/capstone/suite/MC/ARM/bfloat16-a32.s.cs new file mode 100644 index 0000000..75894d9 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/bfloat16-a32.s.cs @@ -0,0 +1,2 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x05,0x3d,0x04,0xfc = vdot.bf16 d3, d4, d5 diff --git a/thirdparty/capstone/suite/MC/ARM/bfloat16-t32.s.cs b/thirdparty/capstone/suite/MC/ARM/bfloat16-t32.s.cs new file mode 100644 index 0000000..21117a7 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/bfloat16-t32.s.cs @@ -0,0 +1,4 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xb6,0xff,0x46,0x16 = vcvt.bf16.f32 d1, q3 +0x18,0xbf = it ne +0xf3,0xee,0xe1,0x09 = vcvtt.bf16.f32 s1, s3 diff --git a/thirdparty/capstone/suite/MC/ARM/cde-integer.s.cs b/thirdparty/capstone/suite/MC/ARM/cde-integer.s.cs new file mode 100644 index 0000000..b8e16ad --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/cde-integer.s.cs @@ -0,0 +1,2 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x06,0xbf = itte eq diff --git a/thirdparty/capstone/suite/MC/ARM/cde-vec-pred.s.cs b/thirdparty/capstone/suite/MC/ARM/cde-vec-pred.s.cs new file mode 100644 index 0000000..12ce5fc --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/cde-vec-pred.s.cs @@ -0,0 +1,2 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x41,0xfe,0x00,0xef = vptete.i8 eq, q0, q0 diff --git a/thirdparty/capstone/suite/MC/ARM/clrm-asm.s.cs b/thirdparty/capstone/suite/MC/ARM/clrm-asm.s.cs new file mode 100644 index 0000000..75675da --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/clrm-asm.s.cs @@ -0,0 +1,7 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None +0x9f,0xe8,0x0f,0x00 = clrm {r0, r1, r2, r3} +0x9f,0xe8,0x1e,0x00 = clrm {r1, r2, r3, r4} +0x9f,0xe8,0xff,0xdf = clrm {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr, apsr} +0x9f,0xe8,0x00,0xc0 = clrm {lr, apsr} +0x9f,0xe8,0x03,0x80 = clrm {r0, r1, apsr} +0x9f,0xe8,0x1f,0xc0 = clrm {r0, r1, r2, r3, r4, lr, apsr} diff --git a/thirdparty/capstone/suite/MC/ARM/cps.s.cs b/thirdparty/capstone/suite/MC/ARM/cps.s.cs new file mode 100644 index 0000000..f1974c2 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/cps.s.cs @@ -0,0 +1,4 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x61,0xb6 = cpsie f +0xaf,0xf3,0x43,0x85 = cpsie i, #3 +0xaf,0xf3,0x00,0x81 = cps #0 diff --git a/thirdparty/capstone/suite/MC/ARM/crc32-thumb.s.cs b/thirdparty/capstone/suite/MC/ARM/crc32-thumb.s.cs new file mode 100644 index 0000000..c6541a5 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/crc32-thumb.s.cs @@ -0,0 +1,7 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None +0xc1,0xfa,0x82,0xf0 = crc32b r0, r1, r2 +0xc1,0xfa,0x92,0xf0 = crc32h r0, r1, r2 +0xc1,0xfa,0xa2,0xf0 = crc32w r0, r1, r2 +0xd1,0xfa,0x82,0xf0 = crc32cb r0, r1, r2 +0xd1,0xfa,0x92,0xf0 = crc32ch r0, r1, r2 +0xd1,0xfa,0xa2,0xf0 = crc32cw r0, r1, r2 diff --git a/thirdparty/capstone/suite/MC/ARM/crc32.s.cs b/thirdparty/capstone/suite/MC/ARM/crc32.s.cs new file mode 100644 index 0000000..a530ff7 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/crc32.s.cs @@ -0,0 +1,7 @@ +# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None +0x42,0x00,0x01,0xe1 = crc32b r0, r1, r2 +0x42,0x00,0x21,0xe1 = crc32h r0, r1, r2 +0x42,0x00,0x41,0xe1 = crc32w r0, r1, r2 +0x42,0x02,0x01,0xe1 = crc32cb r0, r1, r2 +0x42,0x02,0x21,0xe1 = crc32ch r0, r1, r2 +0x42,0x02,0x41,0xe1 = crc32cw r0, r1, r2 diff --git a/thirdparty/capstone/suite/MC/ARM/dot-req.s.cs b/thirdparty/capstone/suite/MC/ARM/dot-req.s.cs new file mode 100644 index 0000000..c54eab3 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/dot-req.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x05,0xb0,0xa0,0xe1 = mov r11, r5 +0x06,0x10,0xa0,0xe1 = mov r1, r6 diff --git a/thirdparty/capstone/suite/MC/ARM/fconst.s.cs b/thirdparty/capstone/suite/MC/ARM/fconst.s.cs new file mode 100644 index 0000000..7998f9c --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/fconst.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x00,0x2a,0xb0,0xee = vmov.f32 s4, #2.000000e+00 +0x00,0x2a,0xb7,0xee = vmov.f32 s4, #1.000000e+00 +0x00,0x3b,0xb0,0xee = vmov.f64 d3, #2.000000e+00 +0x00,0x3b,0xb7,0xee = vmov.f64 d3, #1.000000e+00 +0x01,0x2a,0xf0,0x1e = vmovne.f32 s5, #2.125000e+00 +0x00,0x2a,0xf2,0xce = vmovgt.f32 s5, #8.000000e+00 +0x03,0x2b,0xb0,0xbe = vmovlt.f64 d2, #2.375000e+00 +0x00,0x2b,0xb4,0xae = vmovge.f64 d2, #1.250000e-01 diff --git a/thirdparty/capstone/suite/MC/ARM/fp-armv8.s.cs b/thirdparty/capstone/suite/MC/ARM/fp-armv8.s.cs new file mode 100644 index 0000000..5e8299c --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/fp-armv8.s.cs @@ -0,0 +1,52 @@ +# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None +0xe0,0x3b,0xb2,0xee = vcvtt.f64.f16 d3, s1 +0xcc,0x2b,0xf3,0xee = vcvtt.f16.f64 s5, d12 +0x60,0x3b,0xb2,0xee = vcvtb.f64.f16 d3, s1 +0x41,0x2b,0xb3,0xee = vcvtb.f16.f64 s4, d1 +0xe0,0x3b,0xb2,0xae = vcvttge.f64.f16 d3, s1 +0xcc,0x2b,0xf3,0xce = vcvttgt.f16.f64 s5, d12 +0x60,0x3b,0xb2,0x0e = vcvtbeq.f64.f16 d3, s1 +0x41,0x2b,0xb3,0xbe = vcvtblt.f16.f64 s4, d1 +0xe1,0x1a,0xbc,0xfe = vcvta.s32.f32 s2, s3 +0xc3,0x1b,0xbc,0xfe = vcvta.s32.f64 s2, d3 +0xeb,0x3a,0xbd,0xfe = vcvtn.s32.f32 s6, s23 +0xe7,0x3b,0xbd,0xfe = vcvtn.s32.f64 s6, d23 +0xc2,0x0a,0xbe,0xfe = vcvtp.s32.f32 s0, s4 +0xc4,0x0b,0xbe,0xfe = vcvtp.s32.f64 s0, d4 +0xc4,0x8a,0xff,0xfe = vcvtm.s32.f32 s17, s8 +0xc8,0x8b,0xff,0xfe = vcvtm.s32.f64 s17, d8 +0x61,0x1a,0xbc,0xfe = vcvta.u32.f32 s2, s3 +0x43,0x1b,0xbc,0xfe = vcvta.u32.f64 s2, d3 +0x6b,0x3a,0xbd,0xfe = vcvtn.u32.f32 s6, s23 +0x67,0x3b,0xbd,0xfe = vcvtn.u32.f64 s6, d23 +0x42,0x0a,0xbe,0xfe = vcvtp.u32.f32 s0, s4 +0x44,0x0b,0xbe,0xfe = vcvtp.u32.f64 s0, d4 +0x44,0x8a,0xff,0xfe = vcvtm.u32.f32 s17, s8 +0x48,0x8b,0xff,0xfe = vcvtm.u32.f64 s17, d8 +0xab,0x2a,0x20,0xfe = vselge.f32 s4, s1, s23 +0xa7,0xeb,0x6f,0xfe = vselge.f64 d30, d31, d23 +0x80,0x0a,0x30,0xfe = vselgt.f32 s0, s1, s0 +0x24,0x5b,0x3a,0xfe = vselgt.f64 d5, d10, d20 +0x2b,0xfa,0x0e,0xfe = vseleq.f32 s30, s28, s23 +0x08,0x2b,0x04,0xfe = vseleq.f64 d2, d4, d8 +0x07,0xaa,0x58,0xfe = vselvs.f32 s21, s16, s14 +0x2f,0x0b,0x11,0xfe = vselvs.f64 d0, d1, d31 +0x00,0x2a,0xc6,0xfe = vmaxnm.f32 s5, s12, s0 +0xae,0x5b,0x86,0xfe = vmaxnm.f64 d5, d22, d30 +0x46,0x0a,0x80,0xfe = vminnm.f32 s0, s0, s12 +0x49,0x4b,0x86,0xfe = vminnm.f64 d4, d6, d9 +0xcc,0x3b,0xb6,0xae = vrintzge.f64 d3, d12 +0xcc,0x1a,0xf6,0xee = vrintz.f32 s3, s24 +0x40,0x5b,0xb6,0xbe = vrintrlt.f64 d5, d0 +0x64,0x0a,0xb6,0xee = vrintr.f32 s0, s9 +0x6e,0xcb,0xf7,0x0e = vrintxeq.f64 d28, d30 +0x47,0x5a,0xb7,0x6e = vrintxvs.f32 s10, s14 +0x44,0x3b,0xb8,0xfe = vrinta.f64 d3, d4 +0x60,0x6a,0xb8,0xfe = vrinta.f32 s12, s1 +0x44,0x3b,0xb9,0xfe = vrintn.f64 d3, d4 +0x60,0x6a,0xb9,0xfe = vrintn.f32 s12, s1 +0x44,0x3b,0xba,0xfe = vrintp.f64 d3, d4 +0x60,0x6a,0xba,0xfe = vrintp.f32 s12, s1 +0x44,0x3b,0xbb,0xfe = vrintm.f64 d3, d4 +0x60,0x6a,0xbb,0xfe = vrintm.f32 s12, s1 +0x10,0xda,0xf5,0xee = vmrs sp, mvfr2 diff --git a/thirdparty/capstone/suite/MC/ARM/fpv8.s.cs b/thirdparty/capstone/suite/MC/ARM/fpv8.s.cs new file mode 100644 index 0000000..bdd80e1 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/fpv8.s.cs @@ -0,0 +1,36 @@ +# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None +0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16 +0xe0,0x0b,0x71,0xee = vsub.f64 d16, d17, d16 +0xa0,0x0b,0xc1,0xee = vdiv.f64 d16, d17, d16 +0x07,0x5b,0x85,0xee = vdiv.f64 d5, d5, d7 +0xa0,0x0b,0x61,0xee = vmul.f64 d16, d17, d16 +0xa1,0x4b,0x64,0xee = vmul.f64 d20, d20, d17 +0xe0,0x0b,0x61,0xee = vnmul.f64 d16, d17, d16 +0xe0,0x1b,0xf4,0xee = vcmpe.f64 d17, d16 +0xc0,0x0b,0xf5,0xee = vcmpe.f64 d16, #0 +0xe0,0x0b,0xf0,0xee = vabs.f64 d16, d16 +0xe0,0x0b,0xb7,0xee = vcvt.f32.f64 s0, d16 +0xc0,0x0a,0xf7,0xee = vcvt.f64.f32 d16, s0 +0x60,0x0b,0xf1,0xee = vneg.f64 d16, d16 +0xe0,0x0b,0xf1,0xee = vsqrt.f64 d16, d16 +0xc0,0x0b,0xf8,0xee = vcvt.f64.s32 d16, s0 +0x40,0x0b,0xf8,0xee = vcvt.f64.u32 d16, s0 +0xe0,0x0b,0xbd,0xee = vcvt.s32.f64 s0, d16 +0xe0,0x0b,0xbc,0xee = vcvt.u32.f64 s0, d16 +0xa1,0x0b,0x42,0xee = vmla.f64 d16, d18, d17 +0xe1,0x0b,0x42,0xee = vmls.f64 d16, d18, d17 +0xe1,0x0b,0x52,0xee = vnmla.f64 d16, d18, d17 +0xa1,0x0b,0x52,0xee = vnmls.f64 d16, d18, d17 +0x60,0x0b,0xf1,0x1e = vnegne.f64 d16, d16 +0x08,0x0b,0xf0,0xee = vmov.f64 d16, #3.000000e+00 +0x08,0x0b,0xf8,0xee = vmov.f64 d16, #-3.000000e+00 +0x40,0x0b,0xbd,0xee = vcvtr.s32.f64 s0, d0 +0x40,0x0b,0xbc,0xee = vcvtr.u32.f64 s0, d0 +0xc0,0x0b,0xba,0xee = vcvt.f64.s32 d0, d0, #32 +0x40,0x0b,0xba,0xee = vcvt.f64.s16 d0, d0, #16 +0xc0,0x4b,0xfb,0xee = vcvt.f64.u32 d20, d20, #32 +0x40,0x7b,0xfb,0xee = vcvt.f64.u16 d23, d23, #16 +0xc0,0x2b,0xbe,0xee = vcvt.s32.f64 d2, d2, #32 +0x40,0xfb,0xbe,0xee = vcvt.s16.f64 d15, d15, #16 +0xc0,0x4b,0xff,0xee = vcvt.u32.f64 d20, d20, #32 +0x40,0x7b,0xff,0xee = vcvt.u16.f64 d23, d23, #16 diff --git a/thirdparty/capstone/suite/MC/ARM/gas-compl-copr-reg.s.cs b/thirdparty/capstone/suite/MC/ARM/gas-compl-copr-reg.s.cs new file mode 100644 index 0000000..517d804 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/gas-compl-copr-reg.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x01,0x4c,0x90,0xed = ldc p12, c4, [r0, #4] +0x38,0x6e,0x02,0xed = stc p14, c6, [r2, #-0xe0] +0x01,0x4c,0x90,0xed = ldc p12, c4, [r0, #4] +0x38,0x6e,0x02,0xed = stc p14, c6, [r2, #-0xe0] diff --git a/thirdparty/capstone/suite/MC/ARM/idiv-thumb.s.cs b/thirdparty/capstone/suite/MC/ARM/idiv-thumb.s.cs new file mode 100644 index 0000000..1196fe2 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/idiv-thumb.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x92,0xfb,0xf3,0xf1 = sdiv r1, r2, r3 +0xb4,0xfb,0xf5,0xf3 = udiv r3, r4, r5 diff --git a/thirdparty/capstone/suite/MC/ARM/idiv.s.cs b/thirdparty/capstone/suite/MC/ARM/idiv.s.cs new file mode 100644 index 0000000..557e619 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/idiv.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x12,0xf3,0x11,0xe7 = sdiv r1, r2, r3 +0x14,0xf5,0x33,0xe7 = udiv r3, r4, r5 diff --git a/thirdparty/capstone/suite/MC/ARM/implicit-it-generation.s.cs b/thirdparty/capstone/suite/MC/ARM/implicit-it-generation.s.cs new file mode 100644 index 0000000..36e63ee --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/implicit-it-generation.s.cs @@ -0,0 +1,12 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x01,0x30 = adds r0, #1 +0x10,0xf1,0x01,0x00 = adds.w r0, r0, #1 +0x80,0xe0 = b #0x100 +0x00,0xf0,0x00,0xbc = b.w #0x800 +0x02,0xd0 = beq #4 +0x00,0xf0,0x80,0x80 = beq.w #0x100 +0x02,0xe0 = b #4 +0x80,0xe0 = b #0x100 +0x00,0xf0,0x00,0xbc = b.w #0x800 +0x02,0xdc = bgt #4 +0x00,0xf3,0x80,0x80 = bgt.w #0x100 diff --git a/thirdparty/capstone/suite/MC/ARM/ldrd-strd-gnu-arm.s.cs b/thirdparty/capstone/suite/MC/ARM/ldrd-strd-gnu-arm.s.cs new file mode 100644 index 0000000..0f4c600 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/ldrd-strd-gnu-arm.s.cs @@ -0,0 +1,7 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xd0,0x02,0xea,0xe1 = ldrd r0, r1, [r10, #0x20]! +0xd0,0x02,0xca,0xe0 = ldrd r0, r1, [r10], #0x20 +0xd0,0x02,0xca,0xe1 = ldrd r0, r1, [r10, #0x20] +0xf0,0x02,0xea,0xe1 = strd r0, r1, [r10, #0x20]! +0xf0,0x02,0xca,0xe0 = strd r0, r1, [r10], #0x20 +0xf0,0x02,0xca,0xe1 = strd r0, r1, [r10, #0x20] diff --git a/thirdparty/capstone/suite/MC/ARM/ldrd-strd-gnu-thumb.s.cs b/thirdparty/capstone/suite/MC/ARM/ldrd-strd-gnu-thumb.s.cs new file mode 100644 index 0000000..081b432 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/ldrd-strd-gnu-thumb.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xfa,0xe9,0x80,0x01 = ldrd r0, r1, [r10, #0x200]! +0xfa,0xe8,0x80,0x01 = ldrd r0, r1, [r10], #0x200 +0xda,0xe9,0x80,0x01 = ldrd r0, r1, [r10, #0x200] +0xea,0xe9,0x80,0x01 = strd r0, r1, [r10, #0x200]! +0xea,0xe8,0x80,0x01 = strd r0, r1, [r10], #0x200 +0xca,0xe9,0x80,0x01 = strd r0, r1, [r10, #0x200] +0xfa,0xe9,0x80,0x12 = ldrd r1, r2, [r10, #0x200]! +0xfa,0xe8,0x80,0x12 = ldrd r1, r2, [r10], #0x200 +0xda,0xe9,0x80,0x12 = ldrd r1, r2, [r10, #0x200] +0xea,0xe9,0x80,0x12 = strd r1, r2, [r10, #0x200]! +0xea,0xe8,0x80,0x12 = strd r1, r2, [r10], #0x200 +0xca,0xe9,0x80,0x12 = strd r1, r2, [r10, #0x200] diff --git a/thirdparty/capstone/suite/MC/ARM/load-store-acquire-release-v8-thumb.s.cs b/thirdparty/capstone/suite/MC/ARM/load-store-acquire-release-v8-thumb.s.cs new file mode 100644 index 0000000..317369c --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/load-store-acquire-release-v8-thumb.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None +0xd4,0xe8,0xcf,0x3f = ldaexb r3, [r4] +0xd5,0xe8,0xdf,0x2f = ldaexh r2, [r5] +0xd7,0xe8,0xef,0x1f = ldaex r1, [r7] +0xd8,0xe8,0xff,0x67 = ldaexd r6, r7, [r8] +0xc4,0xe8,0xc1,0x3f = stlexb r1, r3, [r4] +0xc5,0xe8,0xd4,0x2f = stlexh r4, r2, [r5] +0xc7,0xe8,0xe2,0x1f = stlex r2, r1, [r7] +0xc8,0xe8,0xf6,0x23 = stlexd r6, r2, r3, [r8] +0xd6,0xe8,0xaf,0x5f = lda r5, [r6] +0xd6,0xe8,0x8f,0x5f = ldab r5, [r6] +0xd9,0xe8,0x9f,0xcf = ldah r12, [r9] +0xc0,0xe8,0xaf,0x3f = stl r3, [r0] +0xc1,0xe8,0x8f,0x2f = stlb r2, [r1] +0xc3,0xe8,0x9f,0x2f = stlh r2, [r3] diff --git a/thirdparty/capstone/suite/MC/ARM/load-store-acquire-release-v8.s.cs b/thirdparty/capstone/suite/MC/ARM/load-store-acquire-release-v8.s.cs new file mode 100644 index 0000000..dc86605 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/load-store-acquire-release-v8.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None +0x9f,0x3e,0xd4,0xe1 = ldaexb r3, [r4] +0x9f,0x2e,0xf5,0xe1 = ldaexh r2, [r5] +0x9f,0x1e,0x97,0xe1 = ldaex r1, [r7] +0x9f,0x6e,0xb8,0xe1 = ldaexd r6, r7, [r8] +0x93,0x1e,0xc4,0xe1 = stlexb r1, r3, [r4] +0x92,0x4e,0xe5,0xe1 = stlexh r4, r2, [r5] +0x91,0x2e,0x87,0xe1 = stlex r2, r1, [r7] +0x92,0x6e,0xa8,0xe1 = stlexd r6, r2, r3, [r8] +0x9f,0x5c,0x96,0xe1 = lda r5, [r6] +0x9f,0x5c,0xd6,0xe1 = ldab r5, [r6] +0x9f,0xcc,0xf9,0xe1 = ldah r12, [r9] +0x93,0xfc,0x80,0xe1 = stl r3, [r0] +0x92,0xfc,0xc1,0xe1 = stlb r2, [r1] +0x92,0xfc,0xe3,0xe1 = stlh r2, [r3] diff --git a/thirdparty/capstone/suite/MC/ARM/mve-bitops.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-bitops.s.cs new file mode 100644 index 0000000..e5cabb6 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-bitops.s.cs @@ -0,0 +1,96 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x81,0xef,0x52,0x09 = vorr.i16 q0, #0x12 +0x81,0xef,0x52,0x03 = vorr.i32 q0, #0x1200 +0x86,0xff,0x5d,0x09 = vorr.i16 q0, #0xed +0x86,0xff,0x5d,0x03 = vorr.i32 q0, #0xed00 +0x86,0xff,0x5d,0x05 = vorr.i32 q0, #0xed0000 +0x86,0xff,0x5d,0x07 = vorr.i32 q0, #0xed000000 +0x82,0xef,0x72,0x09 = vbic.i16 q0, #0x22 +0x81,0xef,0x71,0x03 = vbic.i32 q0, #0x1100 +0x85,0xff,0x7d,0x09 = vbic.i16 q0, #0xdd +0x85,0xff,0x7d,0x0b = vbic.i16 q0, #0xdd00 +0x86,0xff,0x7e,0x01 = vbic.i32 q0, #0xee +0x86,0xff,0x7e,0x03 = vbic.i32 q0, #0xee00 +0x86,0xff,0x7e,0x05 = vbic.i32 q0, #0xee0000 +0x86,0xff,0x7e,0x07 = vbic.i32 q0, #0xee000000 +0x12,0xef,0x5e,0x01 = vbic q0, q1, q7 +0x12,0xef,0x5e,0x01 = vbic q0, q1, q7 +0x12,0xef,0x5e,0x01 = vbic q0, q1, q7 +0x12,0xef,0x5e,0x01 = vbic q0, q1, q7 +0x12,0xef,0x5e,0x01 = vbic q0, q1, q7 +0x12,0xef,0x5e,0x01 = vbic q0, q1, q7 +0x12,0xef,0x5e,0x01 = vbic q0, q1, q7 +0x12,0xef,0x5e,0x01 = vbic q0, q1, q7 +0x12,0xef,0x5e,0x01 = vbic q0, q1, q7 +0x12,0xef,0x5e,0x01 = vbic q0, q1, q7 +0x12,0xef,0x5e,0x01 = vbic q0, q1, q7 +0x12,0xef,0x5e,0x01 = vbic q0, q1, q7 +0xb0,0xff,0x48,0x00 = vrev64.8 q0, q4 +0xb4,0xff,0x46,0x20 = vrev64.16 q1, q3 +0xb8,0xff,0x44,0x00 = vrev64.32 q0, q2 +0xb0,0xff,0xc2,0x00 = vrev32.8 q0, q1 +0xb4,0xff,0xca,0x00 = vrev32.16 q0, q5 +0xb0,0xff,0x44,0x01 = vrev16.8 q0, q2 +0xb0,0xff,0xc4,0x05 = vmvn q0, q2 +0x02,0xff,0x5e,0x41 = veor q2, q1, q7 +0x02,0xff,0x5e,0x41 = veor q2, q1, q7 +0x02,0xff,0x5e,0x41 = veor q2, q1, q7 +0x02,0xff,0x5e,0x41 = veor q2, q1, q7 +0x02,0xff,0x5e,0x41 = veor q2, q1, q7 +0x02,0xff,0x5e,0x41 = veor q2, q1, q7 +0x02,0xff,0x5e,0x41 = veor q2, q1, q7 +0x02,0xff,0x5e,0x41 = veor q2, q1, q7 +0x02,0xff,0x5e,0x41 = veor q2, q1, q7 +0x02,0xff,0x5e,0x41 = veor q2, q1, q7 +0x02,0xff,0x5e,0x41 = veor q2, q1, q7 +0x02,0xff,0x5e,0x41 = veor q2, q1, q7 +0x36,0xef,0x54,0x01 = vorn q0, q3, q2 +0x36,0xef,0x54,0x01 = vorn q0, q3, q2 +0x36,0xef,0x54,0x01 = vorn q0, q3, q2 +0x36,0xef,0x54,0x01 = vorn q0, q3, q2 +0x36,0xef,0x54,0x01 = vorn q0, q3, q2 +0x36,0xef,0x54,0x01 = vorn q0, q3, q2 +0x36,0xef,0x54,0x01 = vorn q0, q3, q2 +0x36,0xef,0x54,0x01 = vorn q0, q3, q2 +0x36,0xef,0x54,0x01 = vorn q0, q3, q2 +0x36,0xef,0x54,0x01 = vorn q0, q3, q2 +0x36,0xef,0x54,0x01 = vorn q0, q3, q2 +0x36,0xef,0x54,0x01 = vorn q0, q3, q2 +0x24,0xef,0x52,0x21 = vorr q1, q2, q1 +0x24,0xef,0x52,0x21 = vorr q1, q2, q1 +0x24,0xef,0x52,0x21 = vorr q1, q2, q1 +0x24,0xef,0x52,0x21 = vorr q1, q2, q1 +0x24,0xef,0x52,0x21 = vorr q1, q2, q1 +0x24,0xef,0x52,0x21 = vorr q1, q2, q1 +0x24,0xef,0x52,0x21 = vorr q1, q2, q1 +0x24,0xef,0x52,0x21 = vorr q1, q2, q1 +0x24,0xef,0x52,0x21 = vorr q1, q2, q1 +0x24,0xef,0x52,0x21 = vorr q1, q2, q1 +0x24,0xef,0x52,0x21 = vorr q1, q2, q1 +0x24,0xef,0x52,0x21 = vorr q1, q2, q1 +0x04,0xef,0x50,0x01 = vand q0, q2, q0 +0x04,0xef,0x50,0x01 = vand q0, q2, q0 +0x04,0xef,0x50,0x01 = vand q0, q2, q0 +0x04,0xef,0x50,0x01 = vand q0, q2, q0 +0x04,0xef,0x50,0x01 = vand q0, q2, q0 +0x04,0xef,0x50,0x01 = vand q0, q2, q0 +0x04,0xef,0x50,0x01 = vand q0, q2, q0 +0x04,0xef,0x50,0x01 = vand q0, q2, q0 +0x04,0xef,0x50,0x01 = vand q0, q2, q0 +0x04,0xef,0x50,0x01 = vand q0, q2, q0 +0x04,0xef,0x50,0x01 = vand q0, q2, q0 +0x04,0xef,0x50,0x01 = vand q0, q2, q0 +0x40,0xee,0x30,0x8b = vmov.8 q0[1], r8 +0x20,0xee,0x30,0x5b = vmov.16 q0[2], r5 +0x2d,0xee,0x10,0xbb = vmov.32 q6[3], r11 +0x12,0xee,0x10,0x0b = vmov.32 r0, q1[0] +0x35,0xee,0x70,0x1b = vmov.s16 r1, q2[7] +0x79,0xee,0x30,0x0b = vmov.s8 r0, q4[13] +0x93,0xee,0x30,0x0b = vmov.u16 r0, q1[4] +0xfa,0xee,0x70,0x0b = vmov.u8 r0, q5[7] +0x71,0xfe,0x4d,0x8f = vpste +0xb0,0xff,0xc2,0x05 = vmvnt q0, q1 +0xb0,0xff,0xc2,0x05 = vmvne q0, q1 +0x71,0xfe,0x4d,0x8f = vpste +0x32,0xef,0x54,0x01 = vornt q0, q1, q2 +0x32,0xef,0x54,0x01 = vorne q0, q1, q2 diff --git a/thirdparty/capstone/suite/MC/ARM/mve-float.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-float.s.cs new file mode 100644 index 0000000..16bd644 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-float.s.cs @@ -0,0 +1,103 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None +0xb6,0xff,0x40,0x24 = vrintn.f16 q1, q0 +0xba,0xff,0x48,0x04 = vrintn.f32 q0, q4 +0xb6,0xff,0x42,0x05 = vrinta.f16 q0, q1 +0xba,0xff,0x46,0x25 = vrinta.f32 q1, q3 +0xb6,0xff,0xca,0x06 = vrintm.f16 q0, q5 +0xba,0xff,0xc8,0x06 = vrintm.f32 q0, q4 +0xb6,0xff,0xc0,0x27 = vrintp.f16 q1, q0 +0xba,0xff,0xc2,0x07 = vrintp.f32 q0, q1 +0xb6,0xff,0xc4,0x24 = vrintx.f16 q1, q2 +0xba,0xff,0xc2,0x24 = vrintx.f32 q1, q1 +0xb6,0xff,0xcc,0x25 = vrintz.f16 q1, q6 +0xba,0xff,0xc0,0x25 = vrintz.f32 q1, q0 +0xb6,0xee,0x60,0x0a = vrintr.f32 s0, s1 +0xb6,0xee,0x41,0x0b = vrintr.f64 d0, d1 +0x12,0xff,0x56,0x4d = vmul.f16 q2, q1, q3 +0x00,0xff,0x5a,0x0d = vmul.f32 q0, q0, q5 +0x24,0xfc,0x42,0x68 = vcmla.f16 q3, q2, q1, #0 +0xa0,0xfc,0x4a,0x08 = vcmla.f16 q0, q0, q5, #0x5a +0x2e,0xfd,0x44,0x68 = vcmla.f16 q3, q7, q2, #0xb4 +0xae,0xfd,0x4c,0x48 = vcmla.f16 q2, q7, q6, #0x10e +0x3c,0xfc,0x4c,0x48 = vcmla.f32 q2, q6, q6, #0 +0xb2,0xfc,0x46,0xe8 = vcmla.f32 q7, q1, q3, #0x5a +0x3a,0xfd,0x46,0x88 = vcmla.f32 q4, q5, q3, #0xb4 +0xb4,0xfd,0x4e,0x68 = vcmla.f32 q3, q2, q7, #0x10e +0x14,0xef,0x56,0x0c = vfma.f16 q0, q2, q3 +0x06,0xef,0x5e,0x0c = vfma.f32 q0, q3, q7 +0x34,0xef,0x5a,0x0c = vfms.f16 q0, q2, q5 +0x22,0xef,0x54,0x2c = vfms.f32 q1, q1, q2 +0x10,0xef,0x4a,0x0d = vadd.f16 q0, q0, q5 +0x06,0xef,0x40,0x2d = vadd.f32 q1, q3, q0 +0x02,0xef,0x44,0x0d = vadd.f32 q0, q1, q2 +0x82,0xfc,0x4e,0x48 = vcadd.f16 q2, q1, q7, #0x5a +0x8a,0xfd,0x4e,0x48 = vcadd.f16 q2, q5, q7, #0x10e +0x98,0xfc,0x4e,0x08 = vcadd.f32 q0, q4, q7, #0x5a +0x94,0xfd,0x46,0x48 = vcadd.f32 q2, q2, q3, #0x10e +0x30,0xff,0x4c,0x0d = vabd.f16 q0, q0, q6 +0x22,0xff,0x48,0x0d = vabd.f32 q0, q1, q4 +0xbf,0xef,0x5e,0x2c = vcvt.f16.s16 q1, q7, #1 +0xb0,0xef,0x5e,0x2c = vcvt.f16.s16 q1, q7, #0x10 +0xb5,0xef,0x5e,0x2c = vcvt.f16.s16 q1, q7, #0xb +0xbd,0xef,0x52,0x2d = vcvt.s16.f16 q1, q1, #3 +0xb6,0xff,0x52,0x4c = vcvt.f16.u16 q2, q1, #0xa +0xbd,0xff,0x50,0x0d = vcvt.u16.f16 q0, q0, #3 +0xbf,0xef,0x5e,0x2e = vcvt.f32.s32 q1, q7, #1 +0xa0,0xef,0x5e,0x2e = vcvt.f32.s32 q1, q7, #0x20 +0xba,0xef,0x5e,0x2e = vcvt.f32.s32 q1, q7, #6 +0xab,0xef,0x50,0x2f = vcvt.s32.f32 q1, q0, #0x15 +0xbc,0xff,0x58,0x2e = vcvt.f32.u32 q1, q4, #4 +0xb8,0xff,0x5a,0x2f = vcvt.u32.f32 q1, q5, #8 +0xb7,0xff,0x42,0x06 = vcvt.f16.s16 q0, q1 +0xb7,0xff,0xc8,0x06 = vcvt.f16.u16 q0, q4 +0xb7,0xff,0x40,0x07 = vcvt.s16.f16 q0, q0 +0xb7,0xff,0xc0,0x07 = vcvt.u16.f16 q0, q0 +0xbb,0xff,0x40,0x06 = vcvt.f32.s32 q0, q0 +0xbb,0xff,0xc0,0x06 = vcvt.f32.u32 q0, q0 +0xbb,0xff,0x40,0x07 = vcvt.s32.f32 q0, q0 +0xbb,0xff,0xc4,0x07 = vcvt.u32.f32 q0, q2 +0xb7,0xff,0x4e,0x00 = vcvta.s16.f16 q0, q7 +0xbc,0xfe,0xe1,0x1a = vcvta.s32.f32 s2, s3 +0xb7,0xff,0x4e,0x00 = vcvta.s16.f16 q0, q7 +0xbb,0xff,0xcc,0xe1 = vcvtn.u32.f32 q7, q6 +0xbb,0xff,0x4e,0x02 = vcvtp.s32.f32 q0, q7 +0xbb,0xff,0xc8,0x23 = vcvtm.u32.f32 q1, q4 +0xb5,0xff,0xce,0x07 = vneg.f16 q0, q7 +0xb9,0xff,0xc4,0x07 = vneg.f32 q0, q2 +0xb5,0xff,0x44,0x07 = vabs.f16 q0, q2 +0xb9,0xff,0x40,0x07 = vabs.f32 q0, q0 +0x3f,0xfe,0x83,0x2e = vmaxnma.f16 q1, q1 +0x3f,0xee,0x8d,0x4e = vmaxnma.f32 q2, q6 +0x3f,0xfe,0x85,0x1e = vminnma.f16 q0, q2 +0x3f,0xee,0x83,0x1e = vminnma.f32 q0, q1 +0x08,0xbf = it eq +0x30,0xee,0x20,0x0a = vaddeq.f32 s0, s0, s1 +0x71,0xfe,0x4d,0x0f = vpst +0x12,0xef,0x44,0x0d = vaddt.f16 q0, q1, q2 +0x71,0xfe,0x4d,0x8f = vpste +0xbb,0xff,0xc2,0x03 = vcvtmt.u32.f32 q0, q1 +0xbb,0xff,0x42,0x01 = vcvtne.s32.f32 q0, q1 +0x18,0xbf = it ne +0xbd,0xee,0xe0,0x0a = vcvtne.s32.f32 s0, s1 +0xa8,0xbf = it ge +0xb2,0xee,0xe0,0x3b = vcvttge.f64.f16 d3, s1 +0x77,0xee,0xc1,0x9f = vpte.f32 lt, q3, r1 +0xbb,0xff,0xc0,0x47 = vcvtt.u32.f32 q2, q0 +0xbb,0xff,0xc0,0x27 = vcvte.u32.f32 q1, q0 +0x0c,0xbf = ite eq +0xbc,0xee,0xe0,0x0a = vcvteq.u32.f32 s0, s1 +0xb8,0xee,0x60,0x0a = vcvtne.f32.u32 s0, s1 +0x71,0xfe,0x4d,0x8f = vpste +0x12,0xff,0x54,0x0d = vmult.f16 q0, q1, q2 +0x12,0xff,0x54,0x0d = vmule.f16 q0, q1, q2 +0x0c,0xbf = ite eq +0x20,0xee,0x01,0x0b = vmuleq.f64 d0, d0, d1 +0x20,0xee,0x02,0x1b = vmulne.f64 d1, d0, d2 +0x08,0xbf = it eq +0xb1,0xee,0x60,0x0a = vnegeq.f32 s0, s1 +0x04,0xbf = itt eq +0x20,0xee,0xc1,0x0a = vnmuleq.f32 s0, s1, s2 +0x20,0xee,0x81,0x0a = vmuleq.f32 s0, s1, s2 +0x71,0xfe,0x4d,0x8f = vpste +0xb6,0xff,0x42,0x04 = vrintnt.f16 q0, q1 +0xba,0xff,0x42,0x04 = vrintne.f32 q0, q1 diff --git a/thirdparty/capstone/suite/MC/ARM/mve-integer.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-integer.s.cs new file mode 100644 index 0000000..7429d61 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-integer.s.cs @@ -0,0 +1,100 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x81,0xef,0x5b,0x0c = vmov.i32 q0, #0x1bff +0x85,0xef,0x5c,0x08 = vmov.i16 q0, #0x5c +0x84,0xef,0x5c,0x0e = vmov.i8 q0, #0x4c +0x80,0xff,0x5d,0x0f = vmov.f32 q0, #-3.625000e+00 +0x84,0xef,0x50,0x0f = vmov.f32 q0, #1.250000e-01 +0x84,0xef,0x51,0x0f = vmov.f32 q0, #1.328125e-01 +0x83,0xef,0x5f,0x0f = vmov.f32 q0, #3.100000e+01 +0xb0,0xee,0x60,0x8a = vmov.f32 s16, s1 +0xb0,0xee,0x41,0x0b = vmov.f64 d0, d1 +0x81,0xff,0x7f,0x0e = vmov.i64 q0, #0xff0000ffffffffff +0x00,0xef,0x56,0x09 = vmul.i8 q0, q0, q3 +0x10,0xef,0x56,0xc9 = vmul.i16 q6, q0, q3 +0x26,0xef,0x5c,0xe9 = vmul.i32 q7, q3, q6 +0x0a,0xff,0x4a,0x0b = vqrdmulh.s8 q0, q5, q5 +0x18,0xff,0x44,0x2b = vqrdmulh.s16 q1, q4, q2 +0x2a,0xff,0x40,0x0b = vqrdmulh.s32 q0, q5, q0 +0x08,0xef,0x4a,0x0b = vqdmulh.s8 q0, q4, q5 +0x18,0xef,0x40,0xcb = vqdmulh.s16 q6, q4, q0 +0x20,0xef,0x4c,0xab = vqdmulh.s32 q5, q0, q6 +0x04,0xff,0x4a,0x68 = vsub.i8 q3, q2, q5 +0x16,0xff,0x4c,0x08 = vsub.i16 q0, q3, q6 +0x20,0xff,0x4c,0x08 = vsub.i32 q0, q0, q6 +0x04,0xef,0x44,0x08 = vadd.i8 q0, q2, q2 +0x14,0xef,0x42,0x48 = vadd.i16 q2, q2, q1 +0x20,0xef,0x4c,0x08 = vadd.i32 q0, q0, q6 +0x0c,0xef,0x50,0x22 = vqsub.s8 q1, q6, q0 +0x1c,0xef,0x52,0x02 = vqsub.s16 q0, q6, q1 +0x20,0xef,0x5a,0x02 = vqsub.s32 q0, q0, q5 +0x04,0xff,0x5c,0x02 = vqsub.u8 q0, q2, q6 +0x1e,0xff,0x52,0x02 = vqsub.u16 q0, q7, q1 +0x28,0xff,0x5e,0x22 = vqsub.u32 q1, q4, q7 +0x02,0xef,0x54,0x00 = vqadd.s8 q0, q1, q2 +0x08,0xef,0x5c,0x00 = vqadd.s8 q0, q4, q6 +0x1a,0xef,0x5a,0x00 = vqadd.s16 q0, q5, q5 +0x20,0xef,0x58,0x00 = vqadd.s32 q0, q0, q4 +0x08,0xff,0x54,0x00 = vqadd.u8 q0, q4, q2 +0x1c,0xff,0x5c,0x80 = vqadd.u16 q4, q6, q6 +0x22,0xff,0x54,0x00 = vqadd.u32 q0, q1, q2 +0x00,0xef,0x44,0x07 = vabd.s8 q0, q0, q2 +0x1a,0xef,0x48,0x27 = vabd.s16 q1, q5, q4 +0x26,0xef,0x44,0x47 = vabd.s32 q2, q3, q2 +0x0c,0xff,0x48,0x27 = vabd.u8 q1, q6, q4 +0x1c,0xff,0x44,0x07 = vabd.u16 q0, q6, q2 +0x2e,0xff,0x48,0x07 = vabd.u32 q0, q7, q4 +0x02,0xef,0x42,0x01 = vrhadd.s8 q0, q1, q1 +0x12,0xef,0x40,0x01 = vrhadd.s16 q0, q1, q0 +0x28,0xef,0x42,0x01 = vrhadd.s32 q0, q4, q1 +0x00,0xff,0x4c,0x21 = vrhadd.u8 q1, q0, q6 +0x14,0xff,0x4a,0x41 = vrhadd.u16 q2, q2, q5 +0x26,0xff,0x40,0x41 = vrhadd.u32 q2, q3, q0 +0x00,0xef,0x44,0x02 = vhsub.s8 q0, q0, q2 +0x16,0xef,0x42,0x22 = vhsub.s16 q1, q3, q1 +0x24,0xef,0x4a,0x02 = vhsub.s32 q0, q2, q5 +0x08,0xff,0x44,0x02 = vhsub.u8 q0, q4, q2 +0x1e,0xff,0x4a,0x02 = vhsub.u16 q0, q7, q5 +0x2c,0xff,0x48,0x42 = vhsub.u32 q2, q6, q4 +0x0e,0xef,0x40,0x00 = vhadd.s8 q0, q7, q0 +0x10,0xef,0x44,0x80 = vhadd.s16 q4, q0, q2 +0x26,0xef,0x42,0x00 = vhadd.s32 q0, q3, q1 +0x00,0xff,0x46,0x60 = vhadd.u8 q3, q0, q3 +0x12,0xff,0x46,0x00 = vhadd.u16 q0, q1, q3 +0x22,0xff,0x46,0x00 = vhadd.u32 q0, q1, q3 +0xec,0xee,0x10,0x8b = vdup.8 q6, r8 +0xae,0xee,0x30,0xeb = vdup.16 q7, lr +0xa2,0xee,0x10,0x9b = vdup.32 q1, r9 +0xa0,0xee,0x30,0x1b = vdup.16 q0, r1 +0xa0,0xee,0x30,0x1b = vdup.16 q0, r1 +0xb0,0xff,0x42,0x44 = vcls.s8 q2, q1 +0xb4,0xff,0x48,0x04 = vcls.s16 q0, q4 +0xb8,0xff,0x40,0x04 = vcls.s32 q0, q0 +0xb0,0xff,0xce,0x04 = vclz.i8 q0, q7 +0xb4,0xff,0xce,0x84 = vclz.i16 q4, q7 +0xb8,0xff,0xca,0xe4 = vclz.i32 q7, q5 +0xb1,0xff,0xc0,0x23 = vneg.s8 q1, q0 +0xb5,0xff,0xc2,0x03 = vneg.s16 q0, q1 +0xb9,0xff,0xc4,0xe3 = vneg.s32 q7, q2 +0xb1,0xff,0x42,0x23 = vabs.s8 q1, q1 +0xb5,0xff,0x44,0x03 = vabs.s16 q0, q2 +0xb9,0xff,0x4e,0x03 = vabs.s32 q0, q7 +0xb0,0xff,0xc0,0x07 = vqneg.s8 q0, q0 +0xb4,0xff,0xc4,0xc7 = vqneg.s16 q6, q2 +0xb8,0xff,0xc4,0xe7 = vqneg.s32 q7, q2 +0xb0,0xff,0x48,0x47 = vqabs.s8 q2, q4 +0xb4,0xff,0x44,0x07 = vqabs.s16 q0, q2 +0xb8,0xff,0x4a,0x07 = vqabs.s32 q0, q5 +0x71,0xfe,0x4d,0x8f = vpste +0xb1,0xff,0xc2,0x03 = vnegt.s8 q0, q1 +0xb1,0xff,0xc2,0x03 = vnege.s8 q0, q1 +0x71,0xfe,0x4d,0x0f = vpst +0x12,0xef,0x54,0x00 = vqaddt.s16 q0, q1, q2 +0x71,0xfe,0x4d,0x8f = vpste +0xb0,0xff,0xc2,0x07 = vqnegt.s8 q0, q1 +0xb4,0xff,0xc2,0x07 = vqnege.s16 q0, q1 +0x33,0xee,0x8f,0x3e = vmina.s8 q1, q7 +0x37,0xee,0x89,0x3e = vmina.s16 q1, q4 +0x3b,0xee,0x8f,0x1e = vmina.s32 q0, q7 +0x33,0xee,0x8f,0x0e = vmaxa.s8 q0, q7 +0x37,0xee,0x81,0x2e = vmaxa.s16 q1, q0 +0x3b,0xee,0x81,0x2e = vmaxa.s32 q1, q0 diff --git a/thirdparty/capstone/suite/MC/ARM/mve-interleave.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-interleave.s.cs new file mode 100644 index 0000000..5383ad7 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-interleave.s.cs @@ -0,0 +1,68 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x9d,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [sp] +0x90,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [r0] +0xb0,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [r0]! +0x9b,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [r11] +0xb0,0xfc,0x00,0xbe = vld20.8 {q5, q6}, [r0]! +0x90,0xfc,0x20,0x1e = vld21.8 {q0, q1}, [r0] +0xb0,0xfc,0x20,0x7e = vld21.8 {q3, q4}, [r0]! +0x90,0xfc,0x80,0x1e = vld20.16 {q0, q1}, [r0] +0xb0,0xfc,0x80,0x1e = vld20.16 {q0, q1}, [r0]! +0x9b,0xfc,0x80,0x1e = vld20.16 {q0, q1}, [r11] +0xb0,0xfc,0x80,0xbe = vld20.16 {q5, q6}, [r0]! +0x90,0xfc,0xa0,0x1e = vld21.16 {q0, q1}, [r0] +0xb0,0xfc,0xa0,0x7e = vld21.16 {q3, q4}, [r0]! +0x90,0xfc,0x00,0x1f = vld20.32 {q0, q1}, [r0] +0xb0,0xfc,0x00,0x1f = vld20.32 {q0, q1}, [r0]! +0x9b,0xfc,0x00,0x1f = vld20.32 {q0, q1}, [r11] +0xb0,0xfc,0x00,0xbf = vld20.32 {q5, q6}, [r0]! +0x90,0xfc,0x20,0x1f = vld21.32 {q0, q1}, [r0] +0xb0,0xfc,0x20,0x7f = vld21.32 {q3, q4}, [r0]! +0x80,0xfc,0x00,0x1e = vst20.8 {q0, q1}, [r0] +0xa0,0xfc,0x00,0x1e = vst20.8 {q0, q1}, [r0]! +0x8b,0xfc,0x00,0x1e = vst20.8 {q0, q1}, [r11] +0xa0,0xfc,0x00,0xbe = vst20.8 {q5, q6}, [r0]! +0x80,0xfc,0x20,0x1e = vst21.8 {q0, q1}, [r0] +0xa0,0xfc,0x20,0x7e = vst21.8 {q3, q4}, [r0]! +0x80,0xfc,0x80,0x1e = vst20.16 {q0, q1}, [r0] +0xa0,0xfc,0x80,0x1e = vst20.16 {q0, q1}, [r0]! +0x8b,0xfc,0x80,0x1e = vst20.16 {q0, q1}, [r11] +0xa0,0xfc,0x80,0xbe = vst20.16 {q5, q6}, [r0]! +0x80,0xfc,0xa0,0x1e = vst21.16 {q0, q1}, [r0] +0xa0,0xfc,0xa0,0x7e = vst21.16 {q3, q4}, [r0]! +0x80,0xfc,0x00,0x1f = vst20.32 {q0, q1}, [r0] +0xa0,0xfc,0x00,0x1f = vst20.32 {q0, q1}, [r0]! +0x8b,0xfc,0x00,0x1f = vst20.32 {q0, q1}, [r11] +0xa0,0xfc,0x00,0xbf = vst20.32 {q5, q6}, [r0]! +0x80,0xfc,0x20,0x1f = vst21.32 {q0, q1}, [r0] +0xa0,0xfc,0x20,0x7f = vst21.32 {q3, q4}, [r0]! +0x90,0xfc,0x01,0x1e = vld40.8 {q0, q1, q2, q3}, [r0] +0xb0,0xfc,0x01,0x1e = vld40.8 {q0, q1, q2, q3}, [r0]! +0x9b,0xfc,0x01,0x1e = vld40.8 {q0, q1, q2, q3}, [r11] +0xb0,0xfc,0x01,0x7e = vld40.8 {q3, q4, q5, q6}, [r0]! +0x90,0xfc,0x21,0x1e = vld41.8 {q0, q1, q2, q3}, [r0] +0xb0,0xfc,0x21,0x9e = vld41.8 {q4, q5, q6, q7}, [r0]! +0x90,0xfc,0x41,0x1e = vld42.8 {q0, q1, q2, q3}, [r0] +0xb0,0xfc,0x41,0x1e = vld42.8 {q0, q1, q2, q3}, [r0]! +0x90,0xfc,0x61,0x1e = vld43.8 {q0, q1, q2, q3}, [r0] +0xb0,0xfc,0x61,0x9e = vld43.8 {q4, q5, q6, q7}, [r0]! +0x90,0xfc,0x81,0x1e = vld40.16 {q0, q1, q2, q3}, [r0] +0xb0,0xfc,0x81,0x1e = vld40.16 {q0, q1, q2, q3}, [r0]! +0x9b,0xfc,0x81,0x1e = vld40.16 {q0, q1, q2, q3}, [r11] +0xb0,0xfc,0x81,0x7e = vld40.16 {q3, q4, q5, q6}, [r0]! +0x90,0xfc,0xa1,0x1e = vld41.16 {q0, q1, q2, q3}, [r0] +0xb0,0xfc,0xa1,0x9e = vld41.16 {q4, q5, q6, q7}, [r0]! +0x90,0xfc,0xc1,0x1e = vld42.16 {q0, q1, q2, q3}, [r0] +0xb0,0xfc,0xc1,0x1e = vld42.16 {q0, q1, q2, q3}, [r0]! +0x90,0xfc,0xe1,0x1e = vld43.16 {q0, q1, q2, q3}, [r0] +0xb0,0xfc,0xe1,0x9e = vld43.16 {q4, q5, q6, q7}, [r0]! +0x90,0xfc,0x01,0x1f = vld40.32 {q0, q1, q2, q3}, [r0] +0xb0,0xfc,0x01,0x1f = vld40.32 {q0, q1, q2, q3}, [r0]! +0x9b,0xfc,0x01,0x1f = vld40.32 {q0, q1, q2, q3}, [r11] +0xb0,0xfc,0x01,0x7f = vld40.32 {q3, q4, q5, q6}, [r0]! +0x90,0xfc,0x21,0x1f = vld41.32 {q0, q1, q2, q3}, [r0] +0xb0,0xfc,0x21,0x9f = vld41.32 {q4, q5, q6, q7}, [r0]! +0x90,0xfc,0x41,0x1f = vld42.32 {q0, q1, q2, q3}, [r0] +0xb0,0xfc,0x41,0x1f = vld42.32 {q0, q1, q2, q3}, [r0]! +0x90,0xfc,0x61,0x1f = vld43.32 {q0, q1, q2, q3}, [r0] +0xb0,0xfc,0x61,0x9f = vld43.32 {q4, q5, q6, q7}, [r0]! diff --git a/thirdparty/capstone/suite/MC/ARM/mve-load-store.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-load-store.s.cs new file mode 100644 index 0000000..5ffe995 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-load-store.s.cs @@ -0,0 +1,443 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x90,0xed,0x00,0x1e = vldrb.u8 q0, [r0] +0x90,0xed,0x00,0x3e = vldrb.u8 q1, [r0] +0x9b,0xed,0x00,0x1e = vldrb.u8 q0, [r11] +0x9b,0xed,0x00,0x7e = vldrb.u8 q3, [r11] +0x94,0xed,0x38,0x1e = vldrb.u8 q0, [r4, #0x38] +0x94,0xed,0x38,0x9e = vldrb.u8 q4, [r4, #0x38] +0x98,0xed,0x38,0x1e = vldrb.u8 q0, [r8, #0x38] +0xb4,0xed,0x38,0xbe = vldrb.u8 q5, [r4, #0x38]! +0xb4,0xed,0x38,0xbe = vldrb.u8 q5, [r4, #0x38]! +0x34,0xec,0x19,0xbe = vldrb.u8 q5, [r4], #-0x19 +0x3a,0xec,0x19,0xbe = vldrb.u8 q5, [r10], #-0x19 +0x1d,0xed,0x19,0xbe = vldrb.u8 q5, [sp, #-0x19] +0x1d,0xed,0x7f,0xbe = vldrb.u8 q5, [sp, #-0x7f] +0x80,0xed,0x00,0x1e = vstrb.8 q0, [r0] +0x80,0xed,0x00,0x3e = vstrb.8 q1, [r0] +0x8b,0xed,0x00,0x1e = vstrb.8 q0, [r11] +0x8b,0xed,0x00,0x7e = vstrb.8 q3, [r11] +0x84,0xed,0x38,0x1e = vstrb.8 q0, [r4, #0x38] +0x84,0xed,0x38,0x9e = vstrb.8 q4, [r4, #0x38] +0x88,0xed,0x38,0x1e = vstrb.8 q0, [r8, #0x38] +0xa4,0xed,0x38,0xbe = vstrb.8 q5, [r4, #0x38]! +0xa4,0xed,0x38,0xbe = vstrb.8 q5, [r4, #0x38]! +0x24,0xec,0x19,0xbe = vstrb.8 q5, [r4], #-0x19 +0x2a,0xec,0x19,0xbe = vstrb.8 q5, [r10], #-0x19 +0x0d,0xed,0x19,0xbe = vstrb.8 q5, [sp, #-0x19] +0x8d,0xed,0x7f,0xbe = vstrb.8 q5, [sp, #0x7f] +0x90,0xfd,0x80,0x0e = vldrb.u16 q0, [r0] +0x90,0xfd,0x80,0x2e = vldrb.u16 q1, [r0] +0x97,0xfd,0x80,0x0e = vldrb.u16 q0, [r7] +0x97,0xfd,0x80,0x6e = vldrb.u16 q3, [r7] +0x94,0xfd,0xb8,0x0e = vldrb.u16 q0, [r4, #0x38] +0x94,0xfd,0xb8,0x8e = vldrb.u16 q4, [r4, #0x38] +0x92,0xfd,0xb8,0x0e = vldrb.u16 q0, [r2, #0x38] +0xb4,0xfd,0xb8,0xae = vldrb.u16 q5, [r4, #0x38]! +0xb4,0xfd,0xb8,0xae = vldrb.u16 q5, [r4, #0x38]! +0x34,0xfc,0x81,0xae = vldrb.u16 q5, [r4], #-1 +0x33,0xfc,0x99,0xae = vldrb.u16 q5, [r3], #-0x19 +0x16,0xfd,0x99,0xae = vldrb.u16 q5, [r6, #-0x19] +0x16,0xfd,0xc0,0xae = vldrb.u16 q5, [r6, #-0x40] +0x90,0xed,0x80,0x0e = vldrb.s16 q0, [r0] +0x90,0xed,0x80,0x2e = vldrb.s16 q1, [r0] +0x97,0xed,0x80,0x0e = vldrb.s16 q0, [r7] +0x97,0xed,0x80,0x6e = vldrb.s16 q3, [r7] +0x94,0xed,0xb8,0x0e = vldrb.s16 q0, [r4, #0x38] +0x94,0xed,0xb8,0x8e = vldrb.s16 q4, [r4, #0x38] +0x92,0xed,0xb8,0x0e = vldrb.s16 q0, [r2, #0x38] +0xb4,0xed,0xb8,0xae = vldrb.s16 q5, [r4, #0x38]! +0xb4,0xed,0xb8,0xae = vldrb.s16 q5, [r4, #0x38]! +0x34,0xec,0x99,0xae = vldrb.s16 q5, [r4], #-0x19 +0x33,0xec,0x99,0xae = vldrb.s16 q5, [r3], #-0x19 +0x16,0xed,0x99,0xae = vldrb.s16 q5, [r6, #-0x19] +0x16,0xed,0xc0,0xae = vldrb.s16 q5, [r6, #-0x40] +0x80,0xed,0x80,0x0e = vstrb.16 q0, [r0] +0x80,0xed,0x80,0x2e = vstrb.16 q1, [r0] +0x87,0xed,0x80,0x0e = vstrb.16 q0, [r7] +0x87,0xed,0x80,0x6e = vstrb.16 q3, [r7] +0x84,0xed,0xb8,0x0e = vstrb.16 q0, [r4, #0x38] +0x84,0xed,0xb8,0x8e = vstrb.16 q4, [r4, #0x38] +0x85,0xed,0xb8,0x0e = vstrb.16 q0, [r5, #0x38] +0xa4,0xed,0xb8,0xae = vstrb.16 q5, [r4, #0x38]! +0xa4,0xed,0xb8,0xae = vstrb.16 q5, [r4, #0x38]! +0x24,0xec,0x99,0xae = vstrb.16 q5, [r4], #-0x19 +0x23,0xec,0x99,0xae = vstrb.16 q5, [r3], #-0x19 +0x02,0xed,0x99,0xae = vstrb.16 q5, [r2, #-0x19] +0x02,0xed,0xc0,0xae = vstrb.16 q5, [r2, #-0x40] +0x90,0xfd,0x00,0x0f = vldrb.u32 q0, [r0] +0x90,0xfd,0x00,0x2f = vldrb.u32 q1, [r0] +0x97,0xfd,0x00,0x0f = vldrb.u32 q0, [r7] +0x97,0xfd,0x00,0x6f = vldrb.u32 q3, [r7] +0x94,0xfd,0x38,0x0f = vldrb.u32 q0, [r4, #0x38] +0x94,0xfd,0x38,0x8f = vldrb.u32 q4, [r4, #0x38] +0x92,0xfd,0x38,0x0f = vldrb.u32 q0, [r2, #0x38] +0xb4,0xfd,0x38,0xaf = vldrb.u32 q5, [r4, #0x38]! +0xb4,0xfd,0x38,0xaf = vldrb.u32 q5, [r4, #0x38]! +0x34,0xfc,0x19,0xaf = vldrb.u32 q5, [r4], #-0x19 +0x33,0xfc,0x19,0xaf = vldrb.u32 q5, [r3], #-0x19 +0x16,0xfd,0x19,0xaf = vldrb.u32 q5, [r6, #-0x19] +0x16,0xfd,0x40,0xaf = vldrb.u32 q5, [r6, #-0x40] +0x90,0xed,0x00,0x0f = vldrb.s32 q0, [r0] +0x90,0xed,0x00,0x2f = vldrb.s32 q1, [r0] +0x97,0xed,0x00,0x0f = vldrb.s32 q0, [r7] +0x97,0xed,0x00,0x6f = vldrb.s32 q3, [r7] +0x94,0xed,0x38,0x0f = vldrb.s32 q0, [r4, #0x38] +0x94,0xed,0x38,0x8f = vldrb.s32 q4, [r4, #0x38] +0x92,0xed,0x38,0x0f = vldrb.s32 q0, [r2, #0x38] +0xb4,0xed,0x38,0xaf = vldrb.s32 q5, [r4, #0x38]! +0xb4,0xed,0x38,0xaf = vldrb.s32 q5, [r4, #0x38]! +0x34,0xec,0x19,0xaf = vldrb.s32 q5, [r4], #-0x19 +0x33,0xec,0x19,0xaf = vldrb.s32 q5, [r3], #-0x19 +0x16,0xed,0x19,0xaf = vldrb.s32 q5, [r6, #-0x19] +0x16,0xed,0x40,0xaf = vldrb.s32 q5, [r6, #-0x40] +0x80,0xed,0x00,0x0f = vstrb.32 q0, [r0] +0x80,0xed,0x00,0x2f = vstrb.32 q1, [r0] +0x87,0xed,0x00,0x0f = vstrb.32 q0, [r7] +0x87,0xed,0x00,0x6f = vstrb.32 q3, [r7] +0x84,0xed,0x38,0x0f = vstrb.32 q0, [r4, #0x38] +0x84,0xed,0x38,0x8f = vstrb.32 q4, [r4, #0x38] +0x85,0xed,0x38,0x0f = vstrb.32 q0, [r5, #0x38] +0xa4,0xed,0x38,0xaf = vstrb.32 q5, [r4, #0x38]! +0xa4,0xed,0x38,0xaf = vstrb.32 q5, [r4, #0x38]! +0x24,0xec,0x19,0xaf = vstrb.32 q5, [r4], #-0x19 +0x23,0xec,0x19,0xaf = vstrb.32 q5, [r3], #-0x19 +0x02,0xed,0x19,0xaf = vstrb.32 q5, [r2, #-0x19] +0x02,0xed,0x40,0xaf = vstrb.32 q5, [r2, #-0x40] +0x90,0xed,0x80,0x1e = vldrh.u16 q0, [r0] +0x90,0xed,0x80,0x3e = vldrh.u16 q1, [r0] +0x9b,0xed,0x80,0x1e = vldrh.u16 q0, [r11] +0x9b,0xed,0x80,0x7e = vldrh.u16 q3, [r11] +0x94,0xed,0x9c,0x1e = vldrh.u16 q0, [r4, #0x38] +0x94,0xed,0x9c,0x9e = vldrh.u16 q4, [r4, #0x38] +0x98,0xed,0x9c,0x1e = vldrh.u16 q0, [r8, #0x38] +0xb4,0xed,0x9c,0xbe = vldrh.u16 q5, [r4, #0x38]! +0xb4,0xed,0x9c,0xbe = vldrh.u16 q5, [r4, #0x38]! +0x34,0xec,0x8d,0xbe = vldrh.u16 q5, [r4], #-0x1a +0x3a,0xec,0x8d,0xbe = vldrh.u16 q5, [r10], #-0x1a +0x1d,0xed,0x8d,0xbe = vldrh.u16 q5, [sp, #-0x1a] +0x1d,0xed,0xa0,0xbe = vldrh.u16 q5, [sp, #-0x40] +0x1d,0xed,0xff,0xbe = vldrh.u16 q5, [sp, #-0xfe] +0xba,0xec,0xff,0xbe = vldrh.u16 q5, [r10], #0xfe +0x80,0xed,0x80,0x1e = vstrh.16 q0, [r0] +0x80,0xed,0x80,0x3e = vstrh.16 q1, [r0] +0x8b,0xed,0x80,0x1e = vstrh.16 q0, [r11] +0x8b,0xed,0x80,0x7e = vstrh.16 q3, [r11] +0x84,0xed,0x9c,0x1e = vstrh.16 q0, [r4, #0x38] +0x84,0xed,0x9c,0x9e = vstrh.16 q4, [r4, #0x38] +0x88,0xed,0x9c,0x1e = vstrh.16 q0, [r8, #0x38] +0xa4,0xed,0x9c,0xbe = vstrh.16 q5, [r4, #0x38]! +0xa4,0xed,0x9c,0xbe = vstrh.16 q5, [r4, #0x38]! +0x24,0xec,0x8d,0xbe = vstrh.16 q5, [r4], #-0x1a +0x2a,0xec,0x8d,0xbe = vstrh.16 q5, [r10], #-0x1a +0x0d,0xed,0x8d,0xbe = vstrh.16 q5, [sp, #-0x1a] +0x0d,0xed,0xa0,0xbe = vstrh.16 q5, [sp, #-0x40] +0x0d,0xed,0xff,0xbe = vstrh.16 q5, [sp, #-0xfe] +0xaa,0xec,0xff,0xbe = vstrh.16 q5, [r10], #0xfe +0x98,0xfd,0x00,0x0f = vldrh.u32 q0, [r0] +0x98,0xfd,0x00,0x2f = vldrh.u32 q1, [r0] +0x9f,0xfd,0x00,0x0f = vldrh.u32 q0, [r7] +0x9f,0xfd,0x00,0x6f = vldrh.u32 q3, [r7] +0x9c,0xfd,0x1c,0x0f = vldrh.u32 q0, [r4, #0x38] +0x9c,0xfd,0x1c,0x8f = vldrh.u32 q4, [r4, #0x38] +0x9a,0xfd,0x1c,0x0f = vldrh.u32 q0, [r2, #0x38] +0xbc,0xfd,0x1c,0xaf = vldrh.u32 q5, [r4, #0x38]! +0xbc,0xfd,0x1c,0xaf = vldrh.u32 q5, [r4, #0x38]! +0x3c,0xfc,0x0d,0xaf = vldrh.u32 q5, [r4], #-0x1a +0x3b,0xfc,0x0d,0xaf = vldrh.u32 q5, [r3], #-0x1a +0x1e,0xfd,0x0d,0xaf = vldrh.u32 q5, [r6, #-0x1a] +0x1e,0xfd,0x20,0xaf = vldrh.u32 q5, [r6, #-0x40] +0x1e,0xfd,0x7f,0xaf = vldrh.u32 q5, [r6, #-0xfe] +0xbc,0xfd,0x7f,0xaf = vldrh.u32 q5, [r4, #0xfe]! +0x98,0xed,0x00,0x0f = vldrh.s32 q0, [r0] +0x98,0xed,0x00,0x2f = vldrh.s32 q1, [r0] +0x9f,0xed,0x00,0x0f = vldrh.s32 q0, [r7] +0x9f,0xed,0x00,0x6f = vldrh.s32 q3, [r7] +0x9c,0xed,0x1c,0x0f = vldrh.s32 q0, [r4, #0x38] +0x9c,0xed,0x1c,0x8f = vldrh.s32 q4, [r4, #0x38] +0x9a,0xed,0x1c,0x0f = vldrh.s32 q0, [r2, #0x38] +0xbc,0xed,0x1c,0xaf = vldrh.s32 q5, [r4, #0x38]! +0xbc,0xed,0x1c,0xaf = vldrh.s32 q5, [r4, #0x38]! +0x3c,0xec,0x0d,0xaf = vldrh.s32 q5, [r4], #-0x1a +0x3b,0xec,0x0d,0xaf = vldrh.s32 q5, [r3], #-0x1a +0x1e,0xed,0x0d,0xaf = vldrh.s32 q5, [r6, #-0x1a] +0x1e,0xed,0x20,0xaf = vldrh.s32 q5, [r6, #-0x40] +0x1e,0xed,0x7f,0xaf = vldrh.s32 q5, [r6, #-0xfe] +0xbc,0xed,0x7f,0xaf = vldrh.s32 q5, [r4, #0xfe]! +0x88,0xed,0x00,0x0f = vstrh.32 q0, [r0] +0x88,0xed,0x00,0x2f = vstrh.32 q1, [r0] +0x8f,0xed,0x00,0x0f = vstrh.32 q0, [r7] +0x8f,0xed,0x00,0x6f = vstrh.32 q3, [r7] +0x8c,0xed,0x1c,0x0f = vstrh.32 q0, [r4, #0x38] +0x8c,0xed,0x1c,0x8f = vstrh.32 q4, [r4, #0x38] +0x8d,0xed,0x1c,0x0f = vstrh.32 q0, [r5, #0x38] +0xac,0xed,0x1c,0xaf = vstrh.32 q5, [r4, #0x38]! +0xac,0xed,0x1c,0xaf = vstrh.32 q5, [r4, #0x38]! +0x2c,0xec,0x0d,0xaf = vstrh.32 q5, [r4], #-0x1a +0x2b,0xec,0x0d,0xaf = vstrh.32 q5, [r3], #-0x1a +0x0a,0xed,0x0d,0xaf = vstrh.32 q5, [r2, #-0x1a] +0x0a,0xed,0x20,0xaf = vstrh.32 q5, [r2, #-0x40] +0x0a,0xed,0x7f,0xaf = vstrh.32 q5, [r2, #-0xfe] +0xac,0xed,0x7f,0xaf = vstrh.32 q5, [r4, #0xfe]! +0x90,0xed,0x00,0x1f = vldrw.u32 q0, [r0] +0x90,0xed,0x00,0x3f = vldrw.u32 q1, [r0] +0x9b,0xed,0x00,0x1f = vldrw.u32 q0, [r11] +0x9b,0xed,0x00,0x7f = vldrw.u32 q3, [r11] +0x94,0xed,0x0e,0x1f = vldrw.u32 q0, [r4, #0x38] +0x94,0xed,0x0e,0x9f = vldrw.u32 q4, [r4, #0x38] +0x98,0xed,0x0e,0x1f = vldrw.u32 q0, [r8, #0x38] +0xb4,0xed,0x0e,0xbf = vldrw.u32 q5, [r4, #0x38]! +0xb4,0xed,0x0e,0xbf = vldrw.u32 q5, [r4, #0x38]! +0x34,0xec,0x07,0xbf = vldrw.u32 q5, [r4], #-0x1c +0x3a,0xec,0x07,0xbf = vldrw.u32 q5, [r10], #-0x1c +0x1d,0xed,0x07,0xbf = vldrw.u32 q5, [sp, #-0x1c] +0x1d,0xed,0x10,0xbf = vldrw.u32 q5, [sp, #-0x40] +0x1d,0xed,0x7f,0xbf = vldrw.u32 q5, [sp, #-0x1fc] +0xb4,0xed,0x7f,0xbf = vldrw.u32 q5, [r4, #0x1fc]! +0x80,0xed,0x00,0x1f = vstrw.32 q0, [r0] +0x80,0xed,0x00,0x3f = vstrw.32 q1, [r0] +0x8b,0xed,0x00,0x1f = vstrw.32 q0, [r11] +0x8b,0xed,0x00,0x7f = vstrw.32 q3, [r11] +0x84,0xed,0x0e,0x1f = vstrw.32 q0, [r4, #0x38] +0x84,0xed,0x0e,0x9f = vstrw.32 q4, [r4, #0x38] +0x88,0xed,0x0e,0x1f = vstrw.32 q0, [r8, #0x38] +0xa4,0xed,0x0e,0xbf = vstrw.32 q5, [r4, #0x38]! +0xa4,0xed,0x0e,0xbf = vstrw.32 q5, [r4, #0x38]! +0x24,0xec,0x07,0xbf = vstrw.32 q5, [r4], #-0x1c +0x2a,0xec,0x07,0xbf = vstrw.32 q5, [r10], #-0x1c +0x0d,0xed,0x07,0xbf = vstrw.32 q5, [sp, #-0x1c] +0x0d,0xed,0x10,0xbf = vstrw.32 q5, [sp, #-0x40] +0x0d,0xed,0x7f,0xbf = vstrw.32 q5, [sp, #-0x1fc] +0xa4,0xed,0x7f,0xbf = vstrw.32 q5, [r4, #0x1fc]! +0x90,0xfc,0x02,0x0e = vldrb.u8 q0, [r0, q1] +0x9a,0xfc,0x02,0x6e = vldrb.u8 q3, [r10, q1] +0x90,0xfc,0x82,0x0e = vldrb.u16 q0, [r0, q1] +0x99,0xfc,0x82,0x6e = vldrb.u16 q3, [r9, q1] +0x90,0xec,0x82,0x0e = vldrb.s16 q0, [r0, q1] +0x9d,0xec,0x82,0x6e = vldrb.s16 q3, [sp, q1] +0x90,0xfc,0x02,0x0f = vldrb.u32 q0, [r0, q1] +0x90,0xfc,0x02,0x6f = vldrb.u32 q3, [r0, q1] +0x90,0xec,0x02,0x0f = vldrb.s32 q0, [r0, q1] +0x90,0xec,0x02,0x6f = vldrb.s32 q3, [r0, q1] +0x90,0xfc,0x92,0x0e = vldrh.u16 q0, [r0, q1] +0x90,0xfc,0x92,0x6e = vldrh.u16 q3, [r0, q1] +0x90,0xfc,0x12,0x0f = vldrh.u32 q0, [r0, q1] +0x90,0xfc,0x12,0x6f = vldrh.u32 q3, [r0, q1] +0x90,0xec,0x12,0x0f = vldrh.s32 q0, [r0, q1] +0x90,0xec,0x12,0x6f = vldrh.s32 q3, [r0, q1] +0x90,0xfc,0x93,0x0e = vldrh.u16 q0, [r0, q1, uxtw #1] +0x90,0xfc,0x42,0x0f = vldrw.u32 q0, [r0, q1] +0x90,0xfc,0x42,0x6f = vldrw.u32 q3, [r0, q1] +0x90,0xfc,0x43,0x0f = vldrw.u32 q0, [r0, q1, uxtw #2] +0x9d,0xfc,0x43,0x0f = vldrw.u32 q0, [sp, q1, uxtw #2] +0x90,0xfc,0xd2,0x0f = vldrd.u64 q0, [r0, q1] +0x90,0xfc,0xd2,0x6f = vldrd.u64 q3, [r0, q1] +0x90,0xfc,0xd3,0x0f = vldrd.u64 q0, [r0, q1, uxtw #3] +0x9d,0xfc,0xd3,0x0f = vldrd.u64 q0, [sp, q1, uxtw #3] +0x80,0xec,0x02,0x0e = vstrb.8 q0, [r0, q1] +0x8a,0xec,0x02,0x6e = vstrb.8 q3, [r10, q1] +0x80,0xec,0x06,0x6e = vstrb.8 q3, [r0, q3] +0x80,0xec,0x82,0x0e = vstrb.16 q0, [r0, q1] +0x8d,0xec,0x82,0x6e = vstrb.16 q3, [sp, q1] +0x80,0xec,0x86,0x6e = vstrb.16 q3, [r0, q3] +0x80,0xec,0x02,0x0f = vstrb.32 q0, [r0, q1] +0x80,0xec,0x02,0x6f = vstrb.32 q3, [r0, q1] +0x80,0xec,0x06,0x6f = vstrb.32 q3, [r0, q3] +0x80,0xec,0x92,0x0e = vstrh.16 q0, [r0, q1] +0x80,0xec,0x92,0x6e = vstrh.16 q3, [r0, q1] +0x80,0xec,0x96,0x6e = vstrh.16 q3, [r0, q3] +0x80,0xec,0x12,0x0f = vstrh.32 q0, [r0, q1] +0x80,0xec,0x12,0x6f = vstrh.32 q3, [r0, q1] +0x80,0xec,0x16,0x6f = vstrh.32 q3, [r0, q3] +0x80,0xec,0x93,0x0e = vstrh.16 q0, [r0, q1, uxtw #1] +0x88,0xec,0x17,0x6f = vstrh.32 q3, [r8, q3, uxtw #1] +0x80,0xec,0x42,0x0f = vstrw.32 q0, [r0, q1] +0x80,0xec,0x42,0x6f = vstrw.32 q3, [r0, q1] +0x80,0xec,0x46,0x6f = vstrw.32 q3, [r0, q3] +0x80,0xec,0x43,0x0f = vstrw.32 q0, [r0, q1, uxtw #2] +0x8d,0xec,0x43,0x0f = vstrw.32 q0, [sp, q1, uxtw #2] +0x80,0xec,0xd2,0x0f = vstrd.64 q0, [r0, q1] +0x80,0xec,0xd2,0x6f = vstrd.64 q3, [r0, q1] +0x80,0xec,0xd6,0x6f = vstrd.64 q3, [r0, q3] +0x80,0xec,0xd3,0x0f = vstrd.64 q0, [r0, q1, uxtw #3] +0x8d,0xec,0xd3,0x0f = vstrd.64 q0, [sp, q1, uxtw #3] +0x92,0xfd,0x00,0x1e = vldrw.u32 q0, [q1] +0x92,0xfd,0x00,0xfe = vldrw.u32 q7, [q1] +0xb2,0xfd,0x00,0xfe = vldrw.u32 q7, [q1]! +0x92,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4] +0x12,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #-4] +0x92,0xfd,0x7f,0xfe = vldrw.u32 q7, [q1, #0x1fc] +0x12,0xfd,0x7f,0xfe = vldrw.u32 q7, [q1, #-0x1fc] +0x92,0xfd,0x42,0xfe = vldrw.u32 q7, [q1, #0x108] +0xb2,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4]! +0x82,0xfd,0x00,0x1e = vstrw.32 q0, [q1] +0x82,0xfd,0x00,0x3e = vstrw.32 q1, [q1] +0x82,0xfd,0x00,0xfe = vstrw.32 q7, [q1] +0xa2,0xfd,0x00,0xfe = vstrw.32 q7, [q1]! +0x8e,0xfd,0x00,0xfe = vstrw.32 q7, [q7] +0x82,0xfd,0x01,0xfe = vstrw.32 q7, [q1, #4] +0x02,0xfd,0x01,0xfe = vstrw.32 q7, [q1, #-4] +0x82,0xfd,0x7f,0xfe = vstrw.32 q7, [q1, #0x1fc] +0x02,0xfd,0x7f,0xfe = vstrw.32 q7, [q1, #-0x1fc] +0xa2,0xfd,0x42,0xfe = vstrw.32 q7, [q1, #0x108]! +0x92,0xfd,0x00,0x1f = vldrd.u64 q0, [q1] +0x92,0xfd,0x00,0xff = vldrd.u64 q7, [q1] +0xb2,0xfd,0x00,0xff = vldrd.u64 q7, [q1]! +0x92,0xfd,0x01,0xff = vldrd.u64 q7, [q1, #8] +0x12,0xfd,0x01,0xff = vldrd.u64 q7, [q1, #-8] +0x92,0xfd,0x7f,0xff = vldrd.u64 q7, [q1, #0x3f8] +0x12,0xfd,0x7f,0xff = vldrd.u64 q7, [q1, #-0x3f8] +0x92,0xfd,0x21,0xff = vldrd.u64 q7, [q1, #0x108] +0x92,0xfd,0x4e,0xff = vldrd.u64 q7, [q1, #0x270] +0x92,0xfd,0x21,0xff = vldrd.u64 q7, [q1, #0x108] +0x32,0xfd,0x7f,0xff = vldrd.u64 q7, [q1, #-0x3f8]! +0x82,0xfd,0x00,0x1f = vstrd.64 q0, [q1] +0x82,0xfd,0x00,0x3f = vstrd.64 q1, [q1] +0x82,0xfd,0x00,0xff = vstrd.64 q7, [q1] +0xa2,0xfd,0x00,0xff = vstrd.64 q7, [q1]! +0x8e,0xfd,0x00,0xff = vstrd.64 q7, [q7] +0x82,0xfd,0x01,0xff = vstrd.64 q7, [q1, #8] +0x22,0xfd,0x01,0xff = vstrd.64 q7, [q1, #-8]! +0x82,0xfd,0x7f,0xff = vstrd.64 q7, [q1, #0x3f8] +0x02,0xfd,0x7f,0xff = vstrd.64 q7, [q1, #-0x3f8] +0x82,0xfd,0x21,0xff = vstrd.64 q7, [q1, #0x108] +0x82,0xfd,0x4e,0xff = vstrd.64 q7, [q1, #0x270] +0x82,0xfd,0x21,0xff = vstrd.64 q7, [q1, #0x108] +0x90,0xed,0x00,0x1e = vldrb.u8 q0, [r0] +0x90,0xed,0x00,0x1e = vldrb.u8 q0, [r0] +0x98,0xed,0x38,0x1e = vldrb.u8 q0, [r8, #0x38] +0x98,0xed,0x38,0x1e = vldrb.u8 q0, [r8, #0x38] +0xb4,0xed,0x38,0xbe = vldrb.u8 q5, [r4, #0x38]! +0xb4,0xed,0x38,0xbe = vldrb.u8 q5, [r4, #0x38]! +0x80,0xed,0x00,0x1e = vstrb.8 q0, [r0] +0x80,0xed,0x00,0x1e = vstrb.8 q0, [r0] +0x84,0xed,0x38,0x9e = vstrb.8 q4, [r4, #0x38] +0x84,0xed,0x38,0x9e = vstrb.8 q4, [r4, #0x38] +0xa4,0xed,0x38,0xbe = vstrb.8 q5, [r4, #0x38]! +0xa4,0xed,0x38,0xbe = vstrb.8 q5, [r4, #0x38]! +0x90,0xed,0x80,0x1e = vldrh.u16 q0, [r0] +0x90,0xed,0x80,0x1e = vldrh.u16 q0, [r0] +0x90,0xed,0x80,0x1e = vldrh.u16 q0, [r0] +0x94,0xed,0x9c,0x1e = vldrh.u16 q0, [r4, #0x38] +0x94,0xed,0x9c,0x1e = vldrh.u16 q0, [r4, #0x38] +0x94,0xed,0x9c,0x1e = vldrh.u16 q0, [r4, #0x38] +0xb4,0xed,0x9c,0xbe = vldrh.u16 q5, [r4, #0x38]! +0xb4,0xed,0x9c,0xbe = vldrh.u16 q5, [r4, #0x38]! +0xb4,0xed,0x9c,0xbe = vldrh.u16 q5, [r4, #0x38]! +0x80,0xed,0x80,0x1e = vstrh.16 q0, [r0] +0x80,0xed,0x80,0x1e = vstrh.16 q0, [r0] +0x80,0xed,0x80,0x1e = vstrh.16 q0, [r0] +0x84,0xed,0x9c,0x1e = vstrh.16 q0, [r4, #0x38] +0x84,0xed,0x9c,0x1e = vstrh.16 q0, [r4, #0x38] +0x84,0xed,0x9c,0x1e = vstrh.16 q0, [r4, #0x38] +0xa4,0xed,0x9c,0xbe = vstrh.16 q5, [r4, #0x38]! +0xa4,0xed,0x9c,0xbe = vstrh.16 q5, [r4, #0x38]! +0xa4,0xed,0x9c,0xbe = vstrh.16 q5, [r4, #0x38]! +0x90,0xed,0x00,0x1f = vldrw.u32 q0, [r0] +0x90,0xed,0x00,0x1f = vldrw.u32 q0, [r0] +0x90,0xed,0x00,0x1f = vldrw.u32 q0, [r0] +0x94,0xed,0x0e,0x1f = vldrw.u32 q0, [r4, #0x38] +0x94,0xed,0x0e,0x1f = vldrw.u32 q0, [r4, #0x38] +0x94,0xed,0x0e,0x1f = vldrw.u32 q0, [r4, #0x38] +0xb4,0xed,0x0e,0xbf = vldrw.u32 q5, [r4, #0x38]! +0xb4,0xed,0x0e,0xbf = vldrw.u32 q5, [r4, #0x38]! +0xb4,0xed,0x0e,0xbf = vldrw.u32 q5, [r4, #0x38]! +0x80,0xed,0x00,0x1f = vstrw.32 q0, [r0] +0x80,0xed,0x00,0x1f = vstrw.32 q0, [r0] +0x80,0xed,0x00,0x1f = vstrw.32 q0, [r0] +0x84,0xed,0x0e,0x1f = vstrw.32 q0, [r4, #0x38] +0x84,0xed,0x0e,0x1f = vstrw.32 q0, [r4, #0x38] +0x84,0xed,0x0e,0x1f = vstrw.32 q0, [r4, #0x38] +0xa4,0xed,0x0e,0xbf = vstrw.32 q5, [r4, #0x38]! +0xa4,0xed,0x0e,0xbf = vstrw.32 q5, [r4, #0x38]! +0xa4,0xed,0x0e,0xbf = vstrw.32 q5, [r4, #0x38]! +0x90,0xfc,0x02,0x0e = vldrb.u8 q0, [r0, q1] +0x90,0xfc,0x02,0x0e = vldrb.u8 q0, [r0, q1] +0x90,0xfc,0x92,0x6e = vldrh.u16 q3, [r0, q1] +0x90,0xfc,0x92,0x6e = vldrh.u16 q3, [r0, q1] +0x90,0xfc,0x92,0x6e = vldrh.u16 q3, [r0, q1] +0x90,0xfc,0x93,0x0e = vldrh.u16 q0, [r0, q1, uxtw #1] +0x90,0xfc,0x93,0x0e = vldrh.u16 q0, [r0, q1, uxtw #1] +0x90,0xfc,0x93,0x0e = vldrh.u16 q0, [r0, q1, uxtw #1] +0x90,0xfc,0x42,0x0f = vldrw.u32 q0, [r0, q1] +0x90,0xfc,0x42,0x0f = vldrw.u32 q0, [r0, q1] +0x90,0xfc,0x42,0x0f = vldrw.u32 q0, [r0, q1] +0x90,0xfc,0x43,0x0f = vldrw.u32 q0, [r0, q1, uxtw #2] +0x90,0xfc,0x43,0x0f = vldrw.u32 q0, [r0, q1, uxtw #2] +0x90,0xfc,0x43,0x0f = vldrw.u32 q0, [r0, q1, uxtw #2] +0x90,0xfc,0xd2,0x0f = vldrd.u64 q0, [r0, q1] +0x90,0xfc,0xd2,0x0f = vldrd.u64 q0, [r0, q1] +0x90,0xfc,0xd2,0x0f = vldrd.u64 q0, [r0, q1] +0x90,0xfc,0xd3,0x0f = vldrd.u64 q0, [r0, q1, uxtw #3] +0x90,0xfc,0xd3,0x0f = vldrd.u64 q0, [r0, q1, uxtw #3] +0x90,0xfc,0xd3,0x0f = vldrd.u64 q0, [r0, q1, uxtw #3] +0x80,0xec,0x02,0x0e = vstrb.8 q0, [r0, q1] +0x80,0xec,0x02,0x0e = vstrb.8 q0, [r0, q1] +0x80,0xec,0x92,0x6e = vstrh.16 q3, [r0, q1] +0x80,0xec,0x92,0x6e = vstrh.16 q3, [r0, q1] +0x80,0xec,0x92,0x6e = vstrh.16 q3, [r0, q1] +0x80,0xec,0x93,0x0e = vstrh.16 q0, [r0, q1, uxtw #1] +0x80,0xec,0x93,0x0e = vstrh.16 q0, [r0, q1, uxtw #1] +0x80,0xec,0x93,0x0e = vstrh.16 q0, [r0, q1, uxtw #1] +0x80,0xec,0x42,0x0f = vstrw.32 q0, [r0, q1] +0x80,0xec,0x42,0x0f = vstrw.32 q0, [r0, q1] +0x80,0xec,0x42,0x0f = vstrw.32 q0, [r0, q1] +0x80,0xec,0x43,0x0f = vstrw.32 q0, [r0, q1, uxtw #2] +0x80,0xec,0x43,0x0f = vstrw.32 q0, [r0, q1, uxtw #2] +0x80,0xec,0x43,0x0f = vstrw.32 q0, [r0, q1, uxtw #2] +0x80,0xec,0xd2,0x6f = vstrd.64 q3, [r0, q1] +0x80,0xec,0xd2,0x6f = vstrd.64 q3, [r0, q1] +0x80,0xec,0xd2,0x6f = vstrd.64 q3, [r0, q1] +0x80,0xec,0xd3,0x0f = vstrd.64 q0, [r0, q1, uxtw #3] +0x80,0xec,0xd3,0x0f = vstrd.64 q0, [r0, q1, uxtw #3] +0x80,0xec,0xd3,0x0f = vstrd.64 q0, [r0, q1, uxtw #3] +0x92,0xfd,0x00,0x1e = vldrw.u32 q0, [q1] +0x92,0xfd,0x00,0x1e = vldrw.u32 q0, [q1] +0x92,0xfd,0x00,0x1e = vldrw.u32 q0, [q1] +0xb2,0xfd,0x00,0xfe = vldrw.u32 q7, [q1]! +0xb2,0xfd,0x00,0xfe = vldrw.u32 q7, [q1]! +0xb2,0xfd,0x00,0xfe = vldrw.u32 q7, [q1]! +0x92,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4] +0x92,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4] +0x92,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4] +0xb2,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4]! +0xb2,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4]! +0xb2,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4]! +0x82,0xfd,0x00,0x1e = vstrw.32 q0, [q1] +0x82,0xfd,0x00,0x1e = vstrw.32 q0, [q1] +0x82,0xfd,0x00,0x1e = vstrw.32 q0, [q1] +0xa2,0xfd,0x00,0xfe = vstrw.32 q7, [q1]! +0xa2,0xfd,0x00,0xfe = vstrw.32 q7, [q1]! +0xa2,0xfd,0x00,0xfe = vstrw.32 q7, [q1]! +0x82,0xfd,0x7f,0xfe = vstrw.32 q7, [q1, #0x1fc] +0x82,0xfd,0x7f,0xfe = vstrw.32 q7, [q1, #0x1fc] +0x82,0xfd,0x7f,0xfe = vstrw.32 q7, [q1, #0x1fc] +0xa2,0xfd,0x42,0xfe = vstrw.32 q7, [q1, #0x108]! +0xa2,0xfd,0x42,0xfe = vstrw.32 q7, [q1, #0x108]! +0xa2,0xfd,0x42,0xfe = vstrw.32 q7, [q1, #0x108]! +0x92,0xfd,0x00,0x1f = vldrd.u64 q0, [q1] +0x92,0xfd,0x00,0x1f = vldrd.u64 q0, [q1] +0x92,0xfd,0x00,0x1f = vldrd.u64 q0, [q1] +0xb2,0xfd,0x00,0xff = vldrd.u64 q7, [q1]! +0xb2,0xfd,0x00,0xff = vldrd.u64 q7, [q1]! +0xb2,0xfd,0x00,0xff = vldrd.u64 q7, [q1]! +0x92,0xfd,0x01,0xff = vldrd.u64 q7, [q1, #8] +0x92,0xfd,0x01,0xff = vldrd.u64 q7, [q1, #8] +0x92,0xfd,0x01,0xff = vldrd.u64 q7, [q1, #8] +0x32,0xfd,0x7f,0xff = vldrd.u64 q7, [q1, #-0x3f8]! +0x32,0xfd,0x7f,0xff = vldrd.u64 q7, [q1, #-0x3f8]! +0x32,0xfd,0x7f,0xff = vldrd.u64 q7, [q1, #-0x3f8]! +0x82,0xfd,0x00,0x1f = vstrd.64 q0, [q1] +0x82,0xfd,0x00,0x1f = vstrd.64 q0, [q1] +0x82,0xfd,0x00,0x1f = vstrd.64 q0, [q1] +0xa2,0xfd,0x00,0xff = vstrd.64 q7, [q1]! +0xa2,0xfd,0x00,0xff = vstrd.64 q7, [q1]! +0xa2,0xfd,0x00,0xff = vstrd.64 q7, [q1]! +0x82,0xfd,0x7f,0xff = vstrd.64 q7, [q1, #0x3f8] +0x82,0xfd,0x7f,0xff = vstrd.64 q7, [q1, #0x3f8] +0x82,0xfd,0x7f,0xff = vstrd.64 q7, [q1, #0x3f8] +0x22,0xfd,0x01,0xff = vstrd.64 q7, [q1, #-8]! +0x22,0xfd,0x01,0xff = vstrd.64 q7, [q1, #-8]! +0x22,0xfd,0x01,0xff = vstrd.64 q7, [q1, #-8]! +0x71,0xfe,0x4d,0x8f = vpste +0xa2,0xfd,0x42,0xfe = vstrwt.32 q7, [q1, #0x108]! +0x92,0xfd,0x01,0xff = vldrde.u64 q7, [q1, #8] diff --git a/thirdparty/capstone/suite/MC/ARM/mve-minmax.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-minmax.s.cs new file mode 100644 index 0000000..e094e36 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-minmax.s.cs @@ -0,0 +1,18 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x02,0xff,0x58,0x0f = vmaxnm.f32 q0, q1, q4 +0x30,0xff,0x52,0x6f = vminnm.f16 q3, q0, q1 +0x00,0xef,0x5e,0x66 = vmin.s8 q3, q0, q7 +0x12,0xef,0x54,0x06 = vmin.s16 q0, q1, q2 +0x22,0xef,0x54,0x06 = vmin.s32 q0, q1, q2 +0x02,0xff,0x54,0x06 = vmin.u8 q0, q1, q2 +0x12,0xff,0x54,0x06 = vmin.u16 q0, q1, q2 +0x22,0xff,0x54,0x06 = vmin.u32 q0, q1, q2 +0x00,0xef,0x4e,0x66 = vmax.s8 q3, q0, q7 +0x12,0xef,0x44,0x06 = vmax.s16 q0, q1, q2 +0x22,0xef,0x44,0x06 = vmax.s32 q0, q1, q2 +0x02,0xff,0x44,0x06 = vmax.u8 q0, q1, q2 +0x12,0xff,0x44,0x06 = vmax.u16 q0, q1, q2 +0x22,0xff,0x44,0x06 = vmax.u32 q0, q1, q2 +0x71,0xfe,0x4d,0x8f = vpste +0x02,0xef,0x54,0x06 = vmint.s8 q0, q1, q2 +0x12,0xef,0x54,0x06 = vmine.s16 q0, q1, q2 diff --git a/thirdparty/capstone/suite/MC/ARM/mve-misc.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-misc.s.cs new file mode 100644 index 0000000..b2f715a --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-misc.s.cs @@ -0,0 +1,30 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x3b,0xfe,0x05,0x0f = vpsel q0, q5, q2 +0x31,0xfe,0x4d,0x0f = vpnot +0x00,0xf0,0x43,0xc3 = wlstp.8 lr, r0, #0x684 +0x10,0xf0,0x43,0xc3 = wlstp.16 lr, r0, #0x684 +0x24,0xf0,0x49,0xcd = wlstp.32 lr, r4, #0xa92 +0x3e,0xf0,0xe9,0xcd = wlstp.64 lr, lr, #0xbd2 +0x05,0xf0,0xb7,0xc6 = wlstp.8 lr, r5, #0xd6c +0x11,0xf0,0x13,0xc2 = wlstp.16 lr, r1, #0x424 +0x27,0xf0,0xe3,0xc7 = wlstp.32 lr, r7, #0xfc4 +0x01,0xf0,0x0d,0xc9 = wlstp.8 lr, r1, #0x21a +0x0a,0xf0,0xbf,0xc2 = wlstp.8 lr, r10, #0x57c +0x0a,0xf0,0xc1,0xc2 = wlstp.8 lr, r10, #0x580 +0x0a,0xf0,0x9b,0xcc = wlstp.8 lr, r10, #0x936 +0x0a,0xf0,0xfb,0xcf = wlstp.8 lr, r10, #0xff6 +0x0b,0xf0,0xd1,0xca = wlstp.8 lr, r11, #0x5a2 +0x35,0xf0,0x01,0xc0 = wlstp.64 lr, r5, #0 +0x05,0xf0,0x01,0xe0 = dlstp.8 lr, r5 +0x15,0xf0,0x01,0xe0 = dlstp.16 lr, r5 +0x27,0xf0,0x01,0xe0 = dlstp.32 lr, r7 +0x32,0xf0,0x01,0xe0 = dlstp.64 lr, r2 +0x1f,0xf0,0x01,0xc8 = letp lr, #-2 +0x1f,0xf0,0x05,0xc0 = letp lr, #-8 +0x1f,0xf0,0xff,0xcf = letp lr, #-0xffe +0x0f,0xf0,0x01,0xe0 = lctp +0x08,0xbf = it eq +0x0f,0xf0,0x01,0xe0 = lctpeq +0x71,0xfe,0x4d,0x8f = vpste +0x33,0xfe,0x05,0x0f = vpselt q0, q1, q2 +0x33,0xfe,0x05,0x0f = vpsele q0, q1, q2 diff --git a/thirdparty/capstone/suite/MC/ARM/mve-qdest-qsrc.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-qdest-qsrc.s.cs new file mode 100644 index 0000000..1a847fb --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-qdest-qsrc.s.cs @@ -0,0 +1,135 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x3f,0xee,0x09,0x2e = vcvtb.f16.f32 q1, q4 +0x3f,0xfe,0x03,0x1e = vcvtt.f32.f16 q0, q1 +0xb2,0xee,0xc0,0x0b = vcvtt.f64.f16 d0, s0 +0xf3,0xee,0xc2,0x0b = vcvtt.f16.f64 s1, d2 +0x3f,0xee,0x09,0x3e = vcvtt.f16.f32 q1, q4 +0x0c,0xee,0x0c,0x3e = vqdmladhx.s8 q1, q6, q6 +0x12,0xee,0x08,0x1e = vqdmladhx.s16 q0, q1, q4 +0x26,0xee,0x0e,0x1e = vqdmladhx.s32 q0, q3, q7 +0x02,0xee,0x02,0x0e = vqdmladh.s8 q0, q1, q1 +0x14,0xee,0x04,0x0e = vqdmladh.s16 q0, q2, q2 +0x2a,0xee,0x0e,0x2e = vqdmladh.s32 q1, q5, q7 +0x0e,0xee,0x01,0x1e = vqrdmladhx.s8 q0, q7, q0 +0x10,0xee,0x03,0x1e = vqrdmladhx.s16 q0, q0, q1 +0x20,0xee,0x09,0x3e = vqrdmladhx.s32 q1, q0, q4 +0x22,0xee,0x01,0x3e = vqrdmladhx.s32 q1, q1, q0 +0x20,0xee,0x03,0x3e = vqrdmladhx.s32 q1, q0, q1 +0x0c,0xee,0x05,0x0e = vqrdmladh.s8 q0, q6, q2 +0x1a,0xee,0x09,0x2e = vqrdmladh.s16 q1, q5, q4 +0x24,0xee,0x05,0x0e = vqrdmladh.s32 q0, q2, q2 +0x08,0xfe,0x0e,0x3e = vqdmlsdhx.s8 q1, q4, q7 +0x14,0xfe,0x0a,0x1e = vqdmlsdhx.s16 q0, q2, q5 +0x28,0xfe,0x0c,0x7e = vqdmlsdhx.s32 q3, q4, q6 +0x06,0xfe,0x0c,0x0e = vqdmlsdh.s8 q0, q3, q6 +0x18,0xfe,0x02,0x0e = vqdmlsdh.s16 q0, q4, q1 +0x2a,0xfe,0x00,0x4e = vqdmlsdh.s32 q2, q5, q0 +0x06,0xfe,0x03,0x1e = vqrdmlsdhx.s8 q0, q3, q1 +0x12,0xfe,0x09,0x1e = vqrdmlsdhx.s16 q0, q1, q4 +0x2c,0xfe,0x07,0x3e = vqrdmlsdhx.s32 q1, q6, q3 +0x06,0xfe,0x01,0x6e = vqrdmlsdh.s8 q3, q3, q0 +0x1e,0xfe,0x09,0x0e = vqrdmlsdh.s16 q0, q7, q4 +0x2c,0xfe,0x0f,0x0e = vqrdmlsdh.s32 q0, q6, q7 +0x20,0xfe,0x0f,0x0e = vqrdmlsdh.s32 q0, q0, q7 +0x2c,0xfe,0x01,0x0e = vqrdmlsdh.s32 q0, q6, q0 +0x32,0xee,0x05,0x0e = vcmul.f16 q0, q1, q2, #0x5a +0x34,0xee,0x0a,0xce = vcmul.f16 q6, q2, q5, #0 +0x30,0xee,0x0b,0x2e = vcmul.f16 q1, q0, q5, #0x5a +0x30,0xee,0x0a,0x3e = vcmul.f16 q1, q0, q5, #0xb4 +0x30,0xee,0x0b,0x3e = vcmul.f16 q1, q0, q5, #0x10e +0x30,0xee,0x03,0x3e = vcmul.f16 q1, q0, q1, #0x10e +0x3e,0xfe,0x0a,0x2e = vcmul.f32 q1, q7, q5, #0 +0x38,0xfe,0x05,0x6e = vcmul.f32 q3, q4, q2, #0x5a +0x32,0xfe,0x06,0xbe = vcmul.f32 q5, q1, q3, #0xb4 +0x3e,0xfe,0x09,0x1e = vcmul.f32 q0, q7, q4, #0x10e +0x0d,0xee,0x00,0x4e = vmullb.s8 q2, q6, q0 +0x19,0xee,0x06,0x6e = vmullb.s16 q3, q4, q3 +0x2b,0xee,0x0c,0x6e = vmullb.s32 q3, q5, q6 +0x0d,0xee,0x04,0x1e = vmullt.s8 q0, q6, q2 +0x11,0xee,0x04,0x1e = vmullt.s16 q0, q0, q2 +0x29,0xee,0x08,0x5e = vmullt.s32 q2, q4, q4 +0x37,0xee,0x0e,0x4e = vmullb.p8 q2, q3, q7 +0x33,0xfe,0x06,0x0e = vmullb.p16 q0, q1, q3 +0x33,0xee,0x0e,0x3e = vmullt.p8 q1, q1, q7 +0x3f,0xfe,0x0e,0x1e = vmullt.p16 q0, q7, q7 +0x09,0xee,0x0b,0x0e = vmulh.s8 q0, q4, q5 +0x1f,0xee,0x09,0x0e = vmulh.s16 q0, q7, q4 +0x2f,0xee,0x09,0x0e = vmulh.s32 q0, q7, q4 +0x0b,0xfe,0x05,0x6e = vmulh.u8 q3, q5, q2 +0x1f,0xfe,0x09,0x4e = vmulh.u16 q2, q7, q4 +0x27,0xfe,0x05,0x2e = vmulh.u32 q1, q3, q2 +0x03,0xee,0x05,0x3e = vrmulh.s8 q1, q1, q2 +0x13,0xee,0x05,0x3e = vrmulh.s16 q1, q1, q2 +0x23,0xee,0x01,0x7e = vrmulh.s32 q3, q1, q0 +0x0d,0xfe,0x01,0x3e = vrmulh.u8 q1, q6, q0 +0x17,0xfe,0x0d,0x9e = vrmulh.u16 q4, q3, q6 +0x25,0xfe,0x05,0x3e = vrmulh.u32 q1, q2, q2 +0x33,0xee,0x03,0x0e = vqmovnb.s16 q0, q1 +0x33,0xee,0x01,0x5e = vqmovnt.s16 q2, q0 +0x37,0xee,0x0b,0x0e = vqmovnb.s32 q0, q5 +0x37,0xee,0x03,0x1e = vqmovnt.s32 q0, q1 +0x33,0xfe,0x09,0x0e = vqmovnb.u16 q0, q4 +0x33,0xfe,0x0f,0x1e = vqmovnt.u16 q0, q7 +0x37,0xfe,0x09,0x0e = vqmovnb.u32 q0, q4 +0x37,0xfe,0x05,0x1e = vqmovnt.u32 q0, q2 +0x3f,0xee,0x09,0x2e = vcvtb.f16.f32 q1, q4 +0x3f,0xee,0x09,0x3e = vcvtt.f16.f32 q1, q4 +0x3f,0xfe,0x07,0x0e = vcvtb.f32.f16 q0, q3 +0x3f,0xfe,0x03,0x1e = vcvtt.f32.f16 q0, q1 +0x31,0xee,0x87,0x0e = vqmovunb.s16 q0, q3 +0x31,0xee,0x83,0x9e = vqmovunt.s16 q4, q1 +0x35,0xee,0x8f,0x2e = vqmovunb.s32 q1, q7 +0x35,0xee,0x85,0x1e = vqmovunt.s32 q0, q2 +0x31,0xfe,0x8b,0x2e = vmovnb.i16 q1, q5 +0x31,0xfe,0x81,0x1e = vmovnt.i16 q0, q0 +0x35,0xfe,0x81,0x2e = vmovnb.i32 q1, q0 +0x35,0xfe,0x87,0x7e = vmovnt.i32 q3, q3 +0x0e,0xee,0x0a,0x6f = vhcadd.s8 q3, q7, q5, #0x5a +0x10,0xee,0x0c,0x0f = vhcadd.s16 q0, q0, q6, #0x5a +0x10,0xee,0x0c,0x0f = vhcadd.s16 q0, q0, q6, #0x5a +0x12,0xee,0x00,0x7f = vhcadd.s16 q3, q1, q0, #0x10e +0x28,0xee,0x0a,0x6f = vhcadd.s32 q3, q4, q5, #0x5a +0x2e,0xee,0x04,0xdf = vhcadd.s32 q6, q7, q2, #0x10e +0x30,0xee,0x04,0x2f = vadc.i32 q1, q0, q2 +0x32,0xee,0x02,0x1f = vadci.i32 q0, q1, q1 +0x00,0xfe,0x04,0x2f = vcadd.i8 q1, q0, q2, #0x5a +0x14,0xfe,0x06,0x0f = vcadd.i16 q0, q2, q3, #0x5a +0x1a,0xfe,0x0a,0x1f = vcadd.i16 q0, q5, q5, #0x10e +0x24,0xfe,0x0a,0x8f = vcadd.i32 q4, q2, q5, #0x5a +0x2a,0xfe,0x00,0xbf = vcadd.i32 q5, q5, q0, #0x10e +0x32,0xfe,0x02,0x6f = vsbc.i32 q3, q1, q1 +0x3c,0xfe,0x04,0x5f = vsbci.i32 q2, q6, q2 +0x38,0xee,0x0b,0x0f = vqdmullb.s16 q0, q4, q5 +0x3c,0xee,0x0b,0x1f = vqdmullt.s16 q0, q6, q5 +0x36,0xfe,0x0f,0x0f = vqdmullb.s32 q0, q3, q7 +0x3e,0xfe,0x0b,0x1f = vqdmullt.s32 q0, q7, q5 +0x32,0xee,0x01,0x0f = vqdmullb.s16 q0, q1, q0 +0x30,0xee,0x0b,0x1f = vqdmullt.s16 q0, q0, q5 +0x32,0xee,0x05,0x1f = vqdmullt.s16 q0, q1, q2 +0x30,0xee,0x60,0x0f = vqdmullb.s16 q0, q0, r0 +0x20,0xfe,0x02,0x1f = vcadd.i32 q0, q0, q1, #0x10e +0x90,0xfd,0x42,0x08 = vcadd.f32 q0, q0, q1, #0x10e +0x20,0xee,0x02,0x1f = vhcadd.s32 q0, q0, q1, #0x10e +0x10,0xee,0x02,0x1f = vhcadd.s16 q0, q0, q1, #0x10e +0xb0,0xff,0xc0,0x00 = vrev32.8 q0, q0 +0x71,0xfe,0x4d,0x8f = vpste +0x32,0xfe,0x05,0x1f = vqdmulltt.s32 q0, q1, q2 +0x32,0xee,0x05,0x0f = vqdmullbe.s16 q0, q1, q2 +0x71,0xfe,0x4d,0x8f = vpste +0x33,0xee,0x04,0x1e = vmulltt.p8 q0, q1, q2 +0x33,0xfe,0x04,0x0e = vmullbe.p16 q0, q1, q2 +0x71,0xfe,0x4d,0x8f = vpste +0x32,0xee,0x04,0x1e = vcmult.f16 q0, q1, q2, #0xb4 +0x32,0xee,0x04,0x1e = vcmule.f16 q0, q1, q2, #0xb4 +0x71,0xfe,0x4d,0xcf = vpstet +0x3f,0xee,0x03,0x0e = vcvtbt.f16.f32 q0, q1 +0xb7,0xff,0x42,0x01 = vcvtne.s16.f16 q0, q1 +0x77,0xee,0xc1,0x9f = vpte.f32 lt, q3, r1 +0x3f,0xee,0x01,0x5e = vcvttt.f16.f32 q2, q0 +0x3f,0xfe,0x01,0x3e = vcvtte.f32.f16 q1, q0 +0x77,0xee,0xc1,0x9f = vpte.f32 lt, q3, r1 +0x3f,0xee,0x01,0x4e = vcvtbt.f16.f32 q2, q0 +0x3f,0xfe,0x01,0x2e = vcvtbe.f32.f16 q1, q0 +0x0c,0xbf = ite eq +0xb3,0xee,0xe0,0x0a = vcvtteq.f16.f32 s0, s1 +0xb3,0xee,0xe0,0x0a = vcvttne.f16.f32 s0, s1 diff --git a/thirdparty/capstone/suite/MC/ARM/mve-qdest-rsrc.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-qdest-rsrc.s.cs new file mode 100644 index 0000000..301f924 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-qdest-rsrc.s.cs @@ -0,0 +1,143 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x07,0xee,0x43,0x1f = vsub.i8 q0, q3, r3 +0x1f,0xee,0x4e,0x1f = vsub.i16 q0, q7, lr +0x2b,0xee,0x4a,0x3f = vsub.i32 q1, q5, r10 +0x09,0xee,0x47,0x2f = vadd.i8 q1, q4, r7 +0x1d,0xee,0x4b,0x0f = vadd.i16 q0, q6, r11 +0x23,0xee,0x46,0x0f = vadd.i32 q0, q1, r6 +0x04,0xee,0x68,0x5f = vqsub.s8 q2, q2, r8 +0x18,0xee,0x60,0x3f = vqsub.s16 q1, q4, r0 +0x24,0xee,0x60,0x1f = vqsub.s32 q0, q2, r0 +0x02,0xfe,0x62,0x1f = vqsub.u8 q0, q1, r2 +0x14,0xfe,0x66,0x1f = vqsub.u16 q0, q2, r6 +0x24,0xfe,0x62,0x1f = vqsub.u32 q0, q2, r2 +0x0c,0xee,0x61,0x0f = vqadd.s8 q0, q6, r1 +0x18,0xee,0x62,0x6f = vqadd.s16 q3, q4, r2 +0x2a,0xee,0x6b,0x0f = vqadd.s32 q0, q5, r11 +0x02,0xfe,0x68,0x0f = vqadd.u8 q0, q1, r8 +0x1a,0xfe,0x69,0x0f = vqadd.u16 q0, q5, r9 +0x20,0xfe,0x67,0x0f = vqadd.u32 q0, q0, r7 +0x32,0xee,0x66,0x0f = vqdmullb.s16 q0, q1, r6 +0x36,0xfe,0x0f,0x0f = vqdmullb.s32 q0, q3, q7 +0x32,0xee,0x60,0x1f = vqdmullt.s16 q0, q1, r0 +0x38,0xfe,0x65,0x1f = vqdmullt.s32 q0, q4, r5 +0x36,0xfe,0x47,0x1f = vsub.f16 q0, q3, r7 +0x32,0xee,0x4a,0x3f = vsub.f32 q1, q1, r10 +0x32,0xfe,0x4e,0x0f = vadd.f16 q0, q1, lr +0x38,0xee,0x44,0x2f = vadd.f32 q1, q4, r4 +0x06,0xee,0x4e,0x1f = vhsub.s8 q0, q3, lr +0x10,0xee,0x46,0x1f = vhsub.s16 q0, q0, r6 +0x24,0xee,0x47,0x3f = vhsub.s32 q1, q2, r7 +0x0c,0xfe,0x45,0x3f = vhsub.u8 q1, q6, r5 +0x18,0xfe,0x4a,0x1f = vhsub.u16 q0, q4, r10 +0x28,0xfe,0x4c,0x1f = vhsub.u32 q0, q4, r12 +0x04,0xee,0x41,0x0f = vhadd.s8 q0, q2, r1 +0x14,0xee,0x41,0x0f = vhadd.s16 q0, q2, r1 +0x20,0xee,0x4a,0x0f = vhadd.s32 q0, q0, r10 +0x0a,0xfe,0x4e,0x0f = vhadd.u8 q0, q5, lr +0x14,0xfe,0x42,0x2f = vhadd.u16 q1, q2, r2 +0x24,0xfe,0x4b,0x0f = vhadd.u32 q0, q2, r11 +0x33,0xee,0xe0,0x1e = vqrshl.s8 q0, r0 +0x37,0xee,0xe3,0x1e = vqrshl.s16 q0, r3 +0x3b,0xee,0xee,0x1e = vqrshl.s32 q0, lr +0x33,0xfe,0xe0,0x1e = vqrshl.u8 q0, r0 +0x37,0xfe,0xe2,0x1e = vqrshl.u16 q0, r2 +0x3b,0xfe,0xe3,0x1e = vqrshl.u32 q0, r3 +0x31,0xee,0xe0,0x1e = vqshl.s8 q0, r0 +0x35,0xee,0xe1,0x3e = vqshl.s16 q1, r1 +0x39,0xee,0xe3,0x1e = vqshl.s32 q0, r3 +0x31,0xfe,0xe1,0x1e = vqshl.u8 q0, r1 +0x35,0xfe,0xeb,0x1e = vqshl.u16 q0, r11 +0x39,0xfe,0xee,0x1e = vqshl.u32 q0, lr +0x33,0xee,0x66,0x1e = vrshl.s8 q0, r6 +0x37,0xee,0x6e,0x1e = vrshl.s16 q0, lr +0x3b,0xee,0x64,0x1e = vrshl.s32 q0, r4 +0x33,0xfe,0x60,0x1e = vrshl.u8 q0, r0 +0x37,0xfe,0x6a,0x1e = vrshl.u16 q0, r10 +0x3b,0xfe,0x61,0x1e = vrshl.u32 q0, r1 +0x31,0xee,0x6e,0x1e = vshl.s8 q0, lr +0x35,0xee,0x6e,0x1e = vshl.s16 q0, lr +0x39,0xee,0x61,0x1e = vshl.s32 q0, r1 +0x31,0xfe,0x6a,0x1e = vshl.u8 q0, r10 +0x35,0xfe,0x6a,0x3e = vshl.u16 q1, r10 +0x39,0xfe,0x6c,0x1e = vshl.u32 q0, r12 +0x09,0xfe,0x68,0x1e = vbrsr.8 q0, q4, r8 +0x13,0xfe,0x61,0x1e = vbrsr.16 q0, q1, r1 +0x2d,0xfe,0x60,0x1e = vbrsr.32 q0, q6, r0 +0x01,0xee,0x6c,0x1e = vmul.i8 q0, q0, r12 +0x19,0xee,0x67,0x1e = vmul.i16 q0, q4, r7 +0x23,0xee,0x6b,0x1e = vmul.i32 q0, q1, r11 +0x31,0xfe,0x6a,0x0e = vmul.f16 q0, q0, r10 +0x33,0xee,0x67,0x0e = vmul.f32 q0, q1, r7 +0x03,0xee,0x66,0x0e = vqdmulh.s8 q0, q1, r6 +0x15,0xee,0x62,0x0e = vqdmulh.s16 q0, q2, r2 +0x27,0xee,0x68,0x2e = vqdmulh.s32 q1, q3, r8 +0x05,0xfe,0x66,0x0e = vqrdmulh.s8 q0, q2, r6 +0x11,0xfe,0x62,0x0e = vqrdmulh.s16 q0, q0, r2 +0x21,0xfe,0x62,0x0e = vqrdmulh.s32 q0, q0, r2 +0x31,0xfe,0x4c,0x1e = vfmas.f16 q0, q0, r12 +0x37,0xee,0x4e,0x1e = vfmas.f32 q0, q3, lr +0x01,0xee,0x46,0x1e = vmlas.i8 q0, q0, r6 +0x15,0xee,0x49,0x1e = vmlas.i16 q0, q2, r9 +0x2f,0xee,0x46,0x1e = vmlas.i32 q0, q7, r6 +0x01,0xee,0x46,0x1e = vmlas.i8 q0, q0, r6 +0x15,0xee,0x49,0x1e = vmlas.i16 q0, q2, r9 +0x2f,0xee,0x46,0x1e = vmlas.i32 q0, q7, r6 +0x0b,0xee,0x4e,0x1e = vmlas.i8 q0, q5, lr +0x17,0xee,0x4c,0x1e = vmlas.i16 q0, q3, r12 +0x23,0xee,0x4b,0x3e = vmlas.i32 q1, q1, r11 +0x33,0xfe,0x46,0x2e = vfma.f16 q1, q1, r6 +0x39,0xee,0x46,0xfe = vfmas.f32 q7, q4, r6 +0x07,0xee,0x48,0x0e = vmla.i8 q0, q3, r8 +0x17,0xee,0x4a,0x2e = vmla.i16 q1, q3, r10 +0x27,0xee,0x41,0x2e = vmla.i32 q1, q3, r1 +0x07,0xee,0x48,0x0e = vmla.i8 q0, q3, r8 +0x17,0xee,0x4a,0x2e = vmla.i16 q1, q3, r10 +0x27,0xee,0x41,0x2e = vmla.i32 q1, q3, r1 +0x0f,0xee,0x4a,0x0e = vmla.i8 q0, q7, r10 +0x11,0xee,0x47,0x0e = vmla.i16 q0, q0, r7 +0x2d,0xee,0x4a,0x2e = vmla.i32 q1, q6, r10 +0x00,0xee,0x65,0x1e = vqdmlash.s8 q0, q0, r5 +0x1a,0xee,0x6e,0x1e = vqdmlash.s16 q0, q5, lr +0x24,0xee,0x63,0x1e = vqdmlash.s32 q0, q2, r3 +0x06,0xee,0x63,0x0e = vqdmlah.s8 q0, q3, r3 +0x16,0xee,0x69,0xae = vqdmlah.s16 q5, q3, r9 +0x22,0xee,0x6b,0x0e = vqdmlah.s32 q0, q1, r11 +0x0a,0xee,0x4a,0x1e = vqrdmlash.s8 q0, q5, r10 +0x16,0xee,0x42,0x1e = vqrdmlash.s16 q0, q3, r2 +0x20,0xee,0x44,0x1e = vqrdmlash.s32 q0, q0, r4 +0x0a,0xee,0x4b,0x0e = vqrdmlah.s8 q0, q5, r11 +0x14,0xee,0x4a,0x0e = vqrdmlah.s16 q0, q2, r10 +0x28,0xee,0x4b,0x0e = vqrdmlah.s32 q0, q4, r11 +0x0f,0xee,0x60,0x0f = viwdup.u8 q0, lr, r1, #1 +0x1b,0xee,0xe1,0x2f = viwdup.u16 q1, r10, r1, #8 +0x2b,0xee,0xe4,0xcf = viwdup.u32 q6, r10, r5, #4 +0x0d,0xee,0xeb,0x1f = vdwdup.u8 q0, r12, r11, #8 +0x1d,0xee,0x61,0x1f = vdwdup.u16 q0, r12, r1, #2 +0x21,0xee,0xe7,0x1f = vdwdup.u32 q0, r0, r7, #8 +0x0f,0xee,0x6f,0x0f = vidup.u8 q0, lr, #2 +0x1f,0xee,0xee,0x0f = vidup.u16 q0, lr, #4 +0x2d,0xee,0x6e,0x0f = vidup.u32 q0, r12, #1 +0x05,0xee,0xee,0x1f = vddup.u8 q0, r4, #4 +0x1b,0xee,0xee,0x1f = vddup.u16 q0, r10, #4 +0x21,0xee,0xef,0x5f = vddup.u32 q2, r0, #8 +0x0e,0xf0,0x01,0xe8 = vctp.8 lr +0x10,0xf0,0x01,0xe8 = vctp.16 r0 +0x2a,0xf0,0x01,0xe8 = vctp.32 r10 +0x31,0xf0,0x01,0xe8 = vctp.64 r1 +0x71,0xfe,0x4d,0x8f = vpste +0x02,0xef,0x54,0x09 = vmult.i8 q0, q1, q2 +0x12,0xef,0x54,0x09 = vmule.i16 q0, q1, q2 +0x71,0xfe,0x4d,0x8f = vpste +0x12,0xef,0x54,0x09 = vmult.i16 q0, q1, q2 +0x14,0xef,0x56,0x29 = vmule.i16 q1, q2, q3 +0x3b,0xfe,0xe0,0x1e = vqrshl.u32 q0, r0 +0x71,0xfe,0x4d,0x8f = vpste +0x37,0xfe,0xe0,0x1e = vqrshlt.u16 q0, r0 +0x14,0xef,0x52,0x05 = vqrshle.s16 q0, q1, q2 +0x71,0xfe,0x4d,0x8f = vpste +0x14,0xff,0x42,0x05 = vrshlt.u16 q0, q1, q2 +0x3b,0xee,0x60,0x1e = vrshle.s32 q0, r0 +0x71,0xfe,0x4d,0x8f = vpste +0x31,0xee,0x60,0x1e = vshlt.s8 q0, r0 +0x39,0xfe,0x60,0x1e = vshle.u32 q0, r0 diff --git a/thirdparty/capstone/suite/MC/ARM/mve-reductions-fp.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-reductions-fp.s.cs new file mode 100644 index 0000000..c65225d --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-reductions-fp.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0xee,0xfe,0x86,0xef = vminnmv.f16 lr, q3 +0xee,0xee,0x82,0xef = vminnmv.f32 lr, q1 +0xec,0xfe,0x80,0xef = vminnmav.f16 lr, q0 +0xec,0xee,0x86,0xef = vminnmav.f32 lr, q3 +0xee,0xfe,0x02,0xef = vmaxnmv.f16 lr, q1 +0xee,0xee,0x02,0xaf = vmaxnmv.f32 r10, q1 +0xec,0xfe,0x0c,0x0f = vmaxnmav.f16 r0, q6 +0xec,0xee,0x0e,0xef = vmaxnmav.f32 lr, q7 diff --git a/thirdparty/capstone/suite/MC/ARM/mve-reductions.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-reductions.s.cs new file mode 100644 index 0000000..b1623ce --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-reductions.s.cs @@ -0,0 +1,56 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x82,0xee,0x07,0x0f = vabav.s8 r0, q1, q3 +0x92,0xee,0x07,0x0f = vabav.s16 r0, q1, q3 +0xa2,0xee,0x07,0x0f = vabav.s32 r0, q1, q3 +0x82,0xfe,0x07,0x0f = vabav.u8 r0, q1, q3 +0x92,0xfe,0x07,0x0f = vabav.u16 r0, q1, q3 +0xa2,0xfe,0x07,0x0f = vabav.u32 r0, q1, q3 +0xf5,0xee,0x00,0xef = vaddv.s16 lr, q0 +0xf5,0xee,0x0c,0x0f = vaddv.s16 r0, q6 +0xf5,0xee,0x20,0xef = vaddva.s16 lr, q0 +0xc9,0xee,0x04,0x0f = vaddlv.s32 r0, r9, q2 +0x89,0xfe,0x02,0x0f = vaddlv.u32 r0, r1, q1 +0xe2,0xee,0x80,0xef = vminv.s8 lr, q0 +0xe6,0xee,0x80,0xef = vminv.s16 lr, q0 +0xea,0xee,0x84,0xef = vminv.s32 lr, q2 +0xe2,0xfe,0x80,0x0f = vminv.u8 r0, q0 +0xea,0xfe,0x86,0xaf = vminv.u32 r10, q3 +0xe4,0xee,0x80,0x0f = vminav.s16 r0, q0 +0xe0,0xee,0x82,0x0f = vminav.s8 r0, q1 +0xe8,0xee,0x82,0xef = vminav.s32 lr, q1 +0xe2,0xee,0x08,0xef = vmaxv.s8 lr, q4 +0xe6,0xee,0x00,0xef = vmaxv.s16 lr, q0 +0xea,0xee,0x02,0x1f = vmaxv.s32 r1, q1 +0xe2,0xfe,0x08,0x0f = vmaxv.u8 r0, q4 +0xe6,0xfe,0x02,0x0f = vmaxv.u16 r0, q1 +0xea,0xfe,0x00,0x1f = vmaxv.u32 r1, q0 +0xe0,0xee,0x0c,0xef = vmaxav.s8 lr, q6 +0xe4,0xee,0x0c,0x0f = vmaxav.s16 r0, q6 +0xe8,0xee,0x0e,0xaf = vmaxav.s32 r10, q7 +0xf0,0xee,0x0e,0xee = vmlav.s16 lr, q0, q7 +0xf1,0xee,0x08,0xee = vmlav.s32 lr, q0, q4 +0xf0,0xfe,0x0e,0xee = vmlav.u16 lr, q0, q7 +0xf1,0xfe,0x00,0xee = vmlav.u32 lr, q0, q0 +0xf0,0xee,0x28,0xee = vmlava.s16 lr, q0, q4 +0xf0,0xee,0x0e,0x1e = vmladavx.s16 r0, q0, q7 +0xf0,0xee,0x2e,0xfe = vmladavax.s16 lr, q0, q7 +0xf6,0xee,0x00,0xef = vmlav.s8 lr, q3, q0 +0xf2,0xfe,0x0e,0xef = vmlav.u8 lr, q1, q7 +0x8c,0xee,0x04,0xef = vrmlalvh.s32 lr, r1, q6, q2 +0x8a,0xfe,0x04,0xef = vrmlalvh.u32 lr, r1, q5, q2 +0x8a,0xfe,0x04,0xef = vrmlalvh.u32 lr, r1, q5, q2 +0x86,0xee,0x20,0xff = vrmlaldavhax.s32 lr, r1, q3, q0 +0xdc,0xfe,0x0b,0xee = vrmlsldavh.s32 lr, r11, q6, q5 +0xf0,0xee,0x07,0xee = vmlsdav.s16 lr, q0, q3 +0x8c,0xee,0x04,0xef = vrmlalvh.s32 lr, r1, q6, q2 +0x8a,0xfe,0x04,0xef = vrmlalvh.u32 lr, r1, q5, q2 +0x86,0xee,0x2c,0xef = vrmlalvha.s32 lr, r1, q3, q6 +0x8e,0xfe,0x22,0xef = vrmlalvha.u32 lr, r1, q7, q1 +0xf0,0xee,0x07,0xee = vmlsdav.s16 lr, q0, q3 +0xf5,0xee,0x0d,0xee = vmlsdav.s32 lr, q2, q6 +0xf2,0xee,0x29,0xfe = vmlsdavax.s16 lr, q1, q4 +0xf0,0xee,0x0e,0xee = vmlav.s16 lr, q0, q7 +0x88,0xee,0x02,0xee = vmlalv.s16 lr, r1, q4, q1 +0xd9,0xee,0x02,0xee = vmlalv.s32 lr, r11, q4, q1 +0x8f,0xee,0x0c,0x0e = vmlalv.s32 r0, r1, q7, q6 +0xda,0xfe,0x08,0xee = vmlalv.u16 lr, r11, q5, q4 diff --git a/thirdparty/capstone/suite/MC/ARM/mve-scalar-shift.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-scalar-shift.s.cs new file mode 100644 index 0000000..2f7acff --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-scalar-shift.s.cs @@ -0,0 +1,31 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x50,0xea,0xef,0x51 = asrl r0, r1, #0x17 +0x5e,0xea,0xef,0x61 = asrl lr, r1, #0x1b +0x50,0xea,0x2d,0x41 = asrl r0, r1, r4 +0x52,0xea,0x22,0x9e = cinc lr, r2, lo +0x57,0xea,0x47,0x9e = cinc lr, r7, pl +0x5c,0xea,0x3c,0xae = cinv lr, r12, hs +0x5a,0xea,0x3a,0xbe = cneg lr, r10, hs +0x59,0xea,0x7b,0x89 = csel r9, r9, r11, vc +0x5f,0xea,0x1f,0x9e = cset lr, eq +0x5f,0xea,0x3f,0xae = csetm lr, hs +0x5a,0xea,0xd7,0x9e = csinc lr, r10, r7, le +0x55,0xea,0x2f,0xae = csinv lr, r5, zr, hs +0x52,0xea,0x42,0xae = cinv lr, r2, pl +0x51,0xea,0x7b,0xbe = csneg lr, r1, r11, vc +0x5e,0xea,0xcf,0x21 = lsll lr, r1, #0xb +0x5e,0xea,0x0d,0x41 = lsll lr, r1, r4 +0x5e,0xea,0x1f,0x31 = lsrl lr, r1, #0xc +0x5e,0xea,0x2d,0xcf = sqrshr lr, r12 +0x5b,0xea,0x2d,0xcf = sqrshr r11, r12 +0x5f,0xea,0x2d,0x83 = sqrshrl lr, r3, #0x40, r8 +0x5e,0xea,0x7f,0x4f = sqshl lr, #0x11 +0x5f,0xea,0x3f,0x7b = sqshll lr, r11, #0x1c +0x5e,0xea,0xef,0x2f = srshr lr, #0xb +0x5f,0xea,0xef,0x5b = srshrl lr, r11, #0x17 +0x5e,0xea,0x0d,0x1f = uqrshl lr, r1 +0x5f,0xea,0x8d,0x41 = uqrshll lr, r1, #0x30, r4 +0x50,0xea,0x4f,0x0f = uqshl r0, #1 +0x5f,0xea,0xcf,0x17 = uqshll lr, r7, #7 +0x50,0xea,0x9f,0x2f = urshr r0, #0xa +0x51,0xea,0x5f,0x79 = urshrl r0, r9, #0x1d diff --git a/thirdparty/capstone/suite/MC/ARM/mve-shifts.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-shifts.s.cs new file mode 100644 index 0000000..292a95a --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-shifts.s.cs @@ -0,0 +1,106 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None +0xa8,0xee,0xce,0x0f = vshlc q0, lr, #8 +0xa8,0xee,0x4c,0x0f = vmovlb.s8 q0, q6 +0xa8,0xee,0x48,0x1f = vmovlt.s8 q0, q4 +0x41,0xfe,0x00,0x0f = vpt.i8 eq, q0, q0 +0xa8,0xee,0x48,0x1f = vmovltt.s8 q0, q4 +0xa8,0xfe,0x40,0x0f = vmovlb.u8 q0, q0 +0xa8,0xfe,0x44,0x1f = vmovlt.u8 q0, q2 +0xb0,0xfe,0x40,0x2f = vmovlb.u16 q1, q0 +0xb0,0xfe,0x44,0x1f = vmovlt.u16 q0, q2 +0x31,0xee,0x05,0x0e = vshllb.s8 q0, q2, #8 +0x31,0xee,0x0b,0x3e = vshllt.s8 q1, q5, #8 +0xaf,0xee,0x40,0x0f = vshllb.s8 q0, q0, #7 +0x31,0xfe,0x03,0x2e = vshllb.u8 q1, q1, #8 +0x31,0xfe,0x01,0x1e = vshllt.u8 q0, q0, #8 +0xab,0xfe,0x40,0x0f = vshllb.u8 q0, q0, #3 +0x35,0xfe,0x0b,0x0e = vshllb.u16 q0, q5, #0x10 +0x35,0xfe,0x07,0x1e = vshllt.u16 q0, q3, #0x10 +0x35,0xee,0x01,0x1e = vshllt.s16 q0, q0, #0x10 +0xbe,0xee,0x40,0x1f = vshllt.s16 q0, q0, #0xe +0xbb,0xee,0x40,0x1f = vshllt.s16 q0, q0, #0xb +0xb4,0xfe,0x44,0x0f = vshllb.u16 q0, q2, #4 +0x8f,0xfe,0xc7,0x0f = vrshrnb.i16 q0, q3, #1 +0x8b,0xfe,0xc5,0x1f = vrshrnt.i16 q0, q2, #5 +0x98,0xfe,0xc9,0x0f = vrshrnb.i32 q0, q4, #8 +0x99,0xfe,0xc5,0x1f = vrshrnt.i32 q0, q2, #7 +0x8f,0xee,0xc5,0x2f = vshrnb.i16 q1, q2, #1 +0x8f,0xee,0xc3,0x1f = vshrnt.i16 q0, q1, #1 +0x94,0xee,0xc1,0x0f = vshrnb.i32 q0, q0, #0xc +0x9c,0xee,0xc5,0x1f = vshrnt.i32 q0, q2, #4 +0x88,0xfe,0xc4,0x0f = vqrshrunb.s16 q0, q2, #8 +0x8a,0xfe,0xc0,0x1f = vqrshrunt.s16 q0, q0, #6 +0x98,0xfe,0xc2,0x1f = vqrshrunt.s32 q0, q1, #8 +0x93,0xfe,0xce,0x0f = vqrshrunb.s32 q0, q7, #0xd +0x8b,0xee,0xce,0x0f = vqshrunb.s16 q0, q7, #5 +0x89,0xee,0xc2,0x1f = vqshrunt.s16 q0, q1, #7 +0x9c,0xee,0xcc,0x0f = vqshrunb.s32 q0, q6, #4 +0x96,0xee,0xc4,0x1f = vqshrunt.s32 q0, q2, #0xa +0x88,0xee,0x4f,0x0f = vqrshrnb.s16 q0, q7, #8 +0x8c,0xfe,0x47,0x3f = vqrshrnt.u16 q1, q3, #4 +0x99,0xfe,0x43,0x0f = vqrshrnb.u32 q0, q1, #7 +0x95,0xee,0x43,0x1f = vqrshrnt.s32 q0, q1, #0xb +0x8b,0xee,0x4c,0x0f = vqshrnb.s16 q0, q6, #5 +0x8c,0xee,0x42,0x1f = vqshrnt.s16 q0, q1, #4 +0x89,0xfe,0x46,0x0f = vqshrnb.u16 q0, q3, #7 +0x88,0xfe,0x44,0x1f = vqshrnt.u16 q0, q2, #8 +0x9d,0xee,0x48,0x3f = vqshrnt.s32 q1, q4, #3 +0x92,0xfe,0x44,0x0f = vqshrnb.u32 q0, q2, #0xe +0x0c,0xef,0x4c,0xc4 = vshl.s8 q6, q6, q6 +0x14,0xef,0x48,0x04 = vshl.s16 q0, q4, q2 +0x2a,0xef,0x42,0x24 = vshl.s32 q1, q1, q5 +0x04,0xff,0x4e,0x24 = vshl.u8 q1, q7, q2 +0x10,0xff,0x48,0x04 = vshl.u16 q0, q4, q0 +0x28,0xff,0x44,0x44 = vshl.u32 q2, q2, q4 +0x0c,0xef,0x52,0x04 = vqshl.s8 q0, q1, q6 +0x1e,0xef,0x56,0x84 = vqshl.s16 q4, q3, q7 +0x2a,0xef,0x5a,0x04 = vqshl.s32 q0, q5, q5 +0x0c,0xff,0x50,0x04 = vqshl.u8 q0, q0, q6 +0x18,0xff,0x5a,0x04 = vqshl.u16 q0, q5, q4 +0x28,0xff,0x50,0x24 = vqshl.u32 q1, q0, q4 +0x02,0xef,0x5c,0x25 = vqrshl.s8 q1, q6, q1 +0x1c,0xef,0x58,0x45 = vqrshl.s16 q2, q4, q6 +0x2a,0xef,0x50,0x05 = vqrshl.s32 q0, q0, q5 +0x02,0xff,0x54,0x05 = vqrshl.u8 q0, q2, q1 +0x10,0xff,0x5c,0x25 = vqrshl.u16 q1, q6, q0 +0x20,0xff,0x50,0x05 = vqrshl.u32 q0, q0, q0 +0x08,0xef,0x4c,0x05 = vrshl.s8 q0, q6, q4 +0x1e,0xef,0x48,0x25 = vrshl.s16 q1, q4, q7 +0x28,0xef,0x48,0x25 = vrshl.s32 q1, q4, q4 +0x0a,0xff,0x46,0x05 = vrshl.u8 q0, q3, q5 +0x1a,0xff,0x4c,0xa5 = vrshl.u16 q5, q6, q5 +0x26,0xff,0x4e,0x25 = vrshl.u32 q1, q7, q3 +0x8d,0xff,0x54,0x04 = vsri.8 q0, q2, #3 +0x9b,0xff,0x54,0x04 = vsri.16 q0, q2, #5 +0xb1,0xff,0x52,0x04 = vsri.32 q0, q1, #0xf +0x8b,0xff,0x56,0x05 = vsli.8 q0, q3, #3 +0x9c,0xff,0x52,0x05 = vsli.16 q0, q1, #0xc +0xa8,0xff,0x52,0x05 = vsli.32 q0, q1, #8 +0x8e,0xef,0x58,0x07 = vqshl.s8 q0, q4, #6 +0x8e,0xff,0x5c,0x07 = vqshl.u8 q0, q6, #6 +0x95,0xef,0x54,0x27 = vqshl.s16 q1, q2, #5 +0x93,0xff,0x5a,0x07 = vqshl.u16 q0, q5, #3 +0xbd,0xef,0x56,0x27 = vqshl.s32 q1, q3, #0x1d +0xb3,0xff,0x54,0x07 = vqshl.u32 q0, q2, #0x13 +0x88,0xff,0x52,0x06 = vqshlu.s8 q0, q1, #0 +0x9c,0xff,0x52,0x46 = vqshlu.s16 q2, q1, #0xc +0xba,0xff,0x58,0x06 = vqshlu.s32 q0, q4, #0x1a +0x89,0xef,0x56,0x22 = vrshr.s8 q1, q3, #7 +0x8e,0xff,0x56,0x22 = vrshr.u8 q1, q3, #2 +0x96,0xef,0x52,0x02 = vrshr.s16 q0, q1, #0xa +0x94,0xff,0x5a,0x02 = vrshr.u16 q0, q5, #0xc +0xa9,0xef,0x5a,0x02 = vrshr.s32 q0, q5, #0x17 +0xa2,0xff,0x52,0x02 = vrshr.u32 q0, q1, #0x1e +0x8c,0xef,0x5e,0x00 = vshr.s8 q0, q7, #4 +0x8b,0xff,0x54,0x00 = vshr.u8 q0, q2, #5 +0x90,0xef,0x56,0x00 = vshr.s16 q0, q3, #0x10 +0x98,0xff,0x5c,0xe0 = vshr.u16 q7, q6, #8 +0xa8,0xef,0x5c,0x00 = vshr.s32 q0, q6, #0x18 +0xa2,0xff,0x5a,0x40 = vshr.u32 q2, q5, #0x1e +0x8e,0xef,0x5c,0x05 = vshl.i8 q0, q6, #6 +0x9c,0xef,0x50,0x25 = vshl.i16 q1, q0, #0xc +0xba,0xef,0x54,0x45 = vshl.i32 q2, q2, #0x1a +0xa9,0xee,0x42,0x1f = vshllt.s8 q0, q1, #1 +0x71,0xfe,0x4d,0x8f = vpste +0xb4,0xee,0x42,0x1f = vshlltt.s16 q0, q1, #4 +0xb8,0xfe,0x42,0x0f = vshllbe.u16 q0, q1, #8 diff --git a/thirdparty/capstone/suite/MC/ARM/mve-vcmp.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-vcmp.s.cs new file mode 100644 index 0000000..4d9caa7 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-vcmp.s.cs @@ -0,0 +1,57 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x31,0xfe,0x08,0x0f = vcmp.f16 eq, q0, q4 +0x35,0xfe,0x8e,0x0f = vcmp.f16 ne, q2, q7 +0x31,0xfe,0x00,0x1f = vcmp.f16 ge, q0, q0 +0x31,0xfe,0x82,0x1f = vcmp.f16 lt, q0, q1 +0x33,0xfe,0x09,0x1f = vcmp.f16 gt, q1, q4 +0x35,0xfe,0x8d,0x1f = vcmp.f16 le, q2, q6 +0x35,0xee,0x0a,0x0f = vcmp.f32 eq, q2, q5 +0x37,0xee,0x88,0x0f = vcmp.f32 ne, q3, q4 +0x31,0xee,0x0e,0x1f = vcmp.f32 ge, q0, q7 +0x3b,0xee,0x84,0x1f = vcmp.f32 lt, q5, q2 +0x35,0xee,0x0f,0x1f = vcmp.f32 gt, q2, q7 +0x35,0xee,0x89,0x1f = vcmp.f32 le, q2, q4 +0x09,0xfe,0x0c,0x0f = vcmp.i8 eq, q4, q6 +0x05,0xfe,0x84,0x0f = vcmp.i8 ne, q2, q2 +0x09,0xfe,0x0c,0x0f = vcmp.i8 eq, q4, q6 +0x05,0xfe,0x84,0x0f = vcmp.i8 ne, q2, q2 +0x09,0xfe,0x0c,0x0f = vcmp.i8 eq, q4, q6 +0x05,0xfe,0x84,0x0f = vcmp.i8 ne, q2, q2 +0x01,0xfe,0x00,0x1f = vcmp.s8 ge, q0, q0 +0x05,0xfe,0x8e,0x1f = vcmp.s8 lt, q2, q7 +0x09,0xfe,0x07,0x1f = vcmp.s8 gt, q4, q3 +0x0f,0xfe,0x87,0x1f = vcmp.s8 le, q7, q3 +0x03,0xfe,0x89,0x0f = vcmp.u8 hi, q1, q4 +0x03,0xfe,0x09,0x0f = vcmp.u8 cs, q1, q4 +0x19,0xfe,0x0e,0x0f = vcmp.i16 eq, q4, q7 +0x15,0xfe,0x82,0x0f = vcmp.i16 ne, q2, q1 +0x13,0xfe,0x0e,0x1f = vcmp.s16 ge, q1, q7 +0x11,0xfe,0x82,0x1f = vcmp.s16 lt, q0, q1 +0x13,0xfe,0x0f,0x1f = vcmp.s16 gt, q1, q7 +0x15,0xfe,0x83,0x1f = vcmp.s16 le, q2, q1 +0x13,0xfe,0x89,0x0f = vcmp.u16 hi, q1, q4 +0x13,0xfe,0x09,0x0f = vcmp.u16 cs, q1, q4 +0x25,0xfe,0x0e,0x0f = vcmp.i32 eq, q2, q7 +0x25,0xfe,0x88,0x0f = vcmp.i32 ne, q2, q4 +0x2b,0xfe,0x0a,0x1f = vcmp.s32 ge, q5, q5 +0x25,0xfe,0x84,0x1f = vcmp.s32 lt, q2, q2 +0x21,0xfe,0x03,0x1f = vcmp.s32 gt, q0, q1 +0x2b,0xfe,0x89,0x1f = vcmp.s32 le, q5, q4 +0x23,0xfe,0x89,0x0f = vcmp.u32 hi, q1, q4 +0x23,0xfe,0x09,0x0f = vcmp.u32 cs, q1, q4 +0x39,0xfe,0x6f,0x1f = vcmp.f16 gt, q4, zr +0x39,0xfe,0x4c,0x0f = vcmp.f16 eq, q4, r12 +0x37,0xee,0xc0,0x0f = vcmp.f32 ne, q3, r0 +0x03,0xfe,0x40,0x0f = vcmp.i8 eq, q1, r0 +0x03,0xfe,0xe0,0x1f = vcmp.s8 le, q1, r0 +0x03,0xfe,0x60,0x0f = vcmp.u8 cs, q1, r0 +0x1b,0xfe,0x4a,0x0f = vcmp.i16 eq, q5, r10 +0x23,0xfe,0x44,0x0f = vcmp.i32 eq, q1, r4 +0x71,0xfe,0x4d,0x8f = vpste +0x01,0xfe,0x40,0x0f = vcmpt.i8 eq, q0, r0 +0x11,0xfe,0xc0,0x0f = vcmpe.i16 ne, q0, r0 +0xb4,0xee,0x60,0x09 = vcmp.f16 s0, s1 +0xb4,0xee,0xe0,0x09 = vcmpe.f16 s0, s1 +0x04,0xbf = itt eq +0xb4,0xee,0x60,0x0a = vcmpeq.f32 s0, s1 +0xb4,0xee,0xe0,0x0a = vcmpeeq.f32 s0, s1 diff --git a/thirdparty/capstone/suite/MC/ARM/mve-vmov-pair.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-vmov-pair.s.cs new file mode 100644 index 0000000..5486aee --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-vmov-pair.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x07,0xec,0x0e,0x8f = vmov lr, r7, q4[2], q4[0] +0x11,0xec,0x14,0x6f = vmov q3[3], q3[1], r4, r1 diff --git a/thirdparty/capstone/suite/MC/ARM/mve-vpt.s.cs b/thirdparty/capstone/suite/MC/ARM/mve-vpt.s.cs new file mode 100644 index 0000000..af44a45 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/mve-vpt.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x41,0xfe,0x02,0x2f = vpteee.i8 eq, q0, q1 +0x21,0xfe,0x03,0x3f = vptttt.s32 gt, q0, q1 +0x71,0xfe,0x82,0xef = vptete.f16 ne, q0, q1 +0x1c,0xff,0x54,0x2f = vmaxnmt.f16 q1, q6, q2 diff --git a/thirdparty/capstone/suite/MC/ARM/negative-immediates.s.cs b/thirdparty/capstone/suite/MC/ARM/negative-immediates.s.cs new file mode 100644 index 0000000..fa3abdd --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/negative-immediates.s.cs @@ -0,0 +1,10 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x61,0xf1,0x01,0x10 = sbc r0, r1, #0x10001 +0x61,0xf1,0x01,0x20 = sbc r0, r1, #0x1000100 +0xa0,0xf1,0xfe,0x10 = sub.w r0, r0, #0xfe00fe +0xa1,0xf2,0xff,0x00 = subw r0, r1, #0xff +0xa1,0xf1,0xff,0x00 = sub.w r0, r1, #0xff +0x21,0xf0,0x01,0x20 = bic r0, r1, #0x1000100 +0x01,0xf0,0x01,0x20 = and r0, r1, #0x1000100 +0x61,0xf0,0x01,0x20 = orn r0, r1, #0x1000100 +0x41,0xf0,0x01,0x20 = orr r0, r1, #0x1000100 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-abs-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-abs-encoding.s.cs new file mode 100644 index 0000000..73b2f5c --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-abs-encoding.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x20,0x03,0xf1,0xf3 = vabs.s8 d16, d16 +0x20,0x03,0xf5,0xf3 = vabs.s16 d16, d16 +0x20,0x03,0xf9,0xf3 = vabs.s32 d16, d16 +0x20,0x07,0xf9,0xf3 = vabs.f32 d16, d16 +0x60,0x03,0xf1,0xf3 = vabs.s8 q8, q8 +0x60,0x03,0xf5,0xf3 = vabs.s16 q8, q8 +0x60,0x03,0xf9,0xf3 = vabs.s32 q8, q8 +0x60,0x07,0xf9,0xf3 = vabs.f32 q8, q8 +0x20,0x07,0xf0,0xf3 = vqabs.s8 d16, d16 +0x20,0x07,0xf4,0xf3 = vqabs.s16 d16, d16 +0x20,0x07,0xf8,0xf3 = vqabs.s32 d16, d16 +0x60,0x07,0xf0,0xf3 = vqabs.s8 q8, q8 +0x60,0x07,0xf4,0xf3 = vqabs.s16 q8, q8 +0x60,0x07,0xf8,0xf3 = vqabs.s32 q8, q8 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-absdiff-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-absdiff-encoding.s.cs new file mode 100644 index 0000000..6f36a73 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-absdiff-encoding.s.cs @@ -0,0 +1,39 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xa1,0x07,0x40,0xf2 = vabd.s8 d16, d16, d17 +0xa1,0x07,0x50,0xf2 = vabd.s16 d16, d16, d17 +0xa1,0x07,0x60,0xf2 = vabd.s32 d16, d16, d17 +0xa1,0x07,0x40,0xf3 = vabd.u8 d16, d16, d17 +0xa1,0x07,0x50,0xf3 = vabd.u16 d16, d16, d17 +0xa1,0x07,0x60,0xf3 = vabd.u32 d16, d16, d17 +0xa1,0x0d,0x60,0xf3 = vabd.f32 d16, d16, d17 +0xe2,0x07,0x40,0xf2 = vabd.s8 q8, q8, q9 +0xe2,0x07,0x50,0xf2 = vabd.s16 q8, q8, q9 +0xe2,0x07,0x60,0xf2 = vabd.s32 q8, q8, q9 +0xe2,0x07,0x40,0xf3 = vabd.u8 q8, q8, q9 +0xe2,0x07,0x50,0xf3 = vabd.u16 q8, q8, q9 +0xe2,0x07,0x60,0xf3 = vabd.u32 q8, q8, q9 +0xe2,0x0d,0x60,0xf3 = vabd.f32 q8, q8, q9 +0xa1,0x07,0xc0,0xf2 = vabdl.s8 q8, d16, d17 +0xa1,0x07,0xd0,0xf2 = vabdl.s16 q8, d16, d17 +0xa1,0x07,0xe0,0xf2 = vabdl.s32 q8, d16, d17 +0xa1,0x07,0xc0,0xf3 = vabdl.u8 q8, d16, d17 +0xa1,0x07,0xd0,0xf3 = vabdl.u16 q8, d16, d17 +0xa1,0x07,0xe0,0xf3 = vabdl.u32 q8, d16, d17 +0xb1,0x07,0x42,0xf2 = vaba.s8 d16, d18, d17 +0xb1,0x07,0x52,0xf2 = vaba.s16 d16, d18, d17 +0xb1,0x07,0x62,0xf2 = vaba.s32 d16, d18, d17 +0xb1,0x07,0x42,0xf3 = vaba.u8 d16, d18, d17 +0xb1,0x07,0x52,0xf3 = vaba.u16 d16, d18, d17 +0xb1,0x07,0x62,0xf3 = vaba.u32 d16, d18, d17 +0xf4,0x27,0x40,0xf2 = vaba.s8 q9, q8, q10 +0xf4,0x27,0x50,0xf2 = vaba.s16 q9, q8, q10 +0xf4,0x27,0x60,0xf2 = vaba.s32 q9, q8, q10 +0xf4,0x27,0x40,0xf3 = vaba.u8 q9, q8, q10 +0xf4,0x27,0x50,0xf3 = vaba.u16 q9, q8, q10 +0xf4,0x27,0x60,0xf3 = vaba.u32 q9, q8, q10 +0xa2,0x05,0xc3,0xf2 = vabal.s8 q8, d19, d18 +0xa2,0x05,0xd3,0xf2 = vabal.s16 q8, d19, d18 +0xa2,0x05,0xe3,0xf2 = vabal.s32 q8, d19, d18 +0xa2,0x05,0xc3,0xf3 = vabal.u8 q8, d19, d18 +0xa2,0x05,0xd3,0xf3 = vabal.u16 q8, d19, d18 +0xa2,0x05,0xe3,0xf3 = vabal.u32 q8, d19, d18 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-add-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-add-encoding.s.cs new file mode 100644 index 0000000..bf8a5d9 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-add-encoding.s.cs @@ -0,0 +1,119 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xa0,0x08,0x41,0xf2 = vadd.i8 d16, d17, d16 +0xa0,0x08,0x51,0xf2 = vadd.i16 d16, d17, d16 +0xa0,0x08,0x71,0xf2 = vadd.i64 d16, d17, d16 +0xa0,0x08,0x61,0xf2 = vadd.i32 d16, d17, d16 +0xa1,0x0d,0x40,0xf2 = vadd.f32 d16, d16, d17 +0xe2,0x0d,0x40,0xf2 = vadd.f32 q8, q8, q9 +0xa0,0x00,0xc1,0xf2 = vaddl.s8 q8, d17, d16 +0xa0,0x00,0xd1,0xf2 = vaddl.s16 q8, d17, d16 +0xa0,0x00,0xe1,0xf2 = vaddl.s32 q8, d17, d16 +0xa0,0x00,0xc1,0xf3 = vaddl.u8 q8, d17, d16 +0xa0,0x00,0xd1,0xf3 = vaddl.u16 q8, d17, d16 +0xa0,0x00,0xe1,0xf3 = vaddl.u32 q8, d17, d16 +0xa2,0x01,0xc0,0xf2 = vaddw.s8 q8, q8, d18 +0xa2,0x01,0xd0,0xf2 = vaddw.s16 q8, q8, d18 +0xa2,0x01,0xe0,0xf2 = vaddw.s32 q8, q8, d18 +0xa2,0x01,0xc0,0xf3 = vaddw.u8 q8, q8, d18 +0xa2,0x01,0xd0,0xf3 = vaddw.u16 q8, q8, d18 +0xa2,0x01,0xe0,0xf3 = vaddw.u32 q8, q8, d18 +0xa1,0x00,0x40,0xf2 = vhadd.s8 d16, d16, d17 +0xa1,0x00,0x50,0xf2 = vhadd.s16 d16, d16, d17 +0xa1,0x00,0x60,0xf2 = vhadd.s32 d16, d16, d17 +0xa1,0x00,0x40,0xf3 = vhadd.u8 d16, d16, d17 +0xa1,0x00,0x50,0xf3 = vhadd.u16 d16, d16, d17 +0xa1,0x00,0x60,0xf3 = vhadd.u32 d16, d16, d17 +0xe2,0x00,0x40,0xf2 = vhadd.s8 q8, q8, q9 +0xe2,0x00,0x50,0xf2 = vhadd.s16 q8, q8, q9 +0xe2,0x00,0x60,0xf2 = vhadd.s32 q8, q8, q9 +0xe2,0x00,0x40,0xf3 = vhadd.u8 q8, q8, q9 +0xe2,0x00,0x50,0xf3 = vhadd.u16 q8, q8, q9 +0xe2,0x00,0x60,0xf3 = vhadd.u32 q8, q8, q9 +0x28,0xb0,0x0b,0xf2 = vhadd.s8 d11, d11, d24 +0x27,0xc0,0x1c,0xf2 = vhadd.s16 d12, d12, d23 +0x26,0xd0,0x2d,0xf2 = vhadd.s32 d13, d13, d22 +0x25,0xe0,0x0e,0xf3 = vhadd.u8 d14, d14, d21 +0x24,0xf0,0x1f,0xf3 = vhadd.u16 d15, d15, d20 +0xa3,0x00,0x60,0xf3 = vhadd.u32 d16, d16, d19 +0x68,0x20,0x02,0xf2 = vhadd.s8 q1, q1, q12 +0x66,0x40,0x14,0xf2 = vhadd.s16 q2, q2, q11 +0x64,0x60,0x26,0xf2 = vhadd.s32 q3, q3, q10 +0x62,0x80,0x08,0xf3 = vhadd.u8 q4, q4, q9 +0x60,0xa0,0x1a,0xf3 = vhadd.u16 q5, q5, q8 +0x4e,0xc0,0x2c,0xf3 = vhadd.u32 q6, q6, q7 +0xa1,0x01,0x40,0xf2 = vrhadd.s8 d16, d16, d17 +0xa1,0x01,0x50,0xf2 = vrhadd.s16 d16, d16, d17 +0xa1,0x01,0x60,0xf2 = vrhadd.s32 d16, d16, d17 +0xa1,0x01,0x40,0xf3 = vrhadd.u8 d16, d16, d17 +0xa1,0x01,0x50,0xf3 = vrhadd.u16 d16, d16, d17 +0xa1,0x01,0x60,0xf3 = vrhadd.u32 d16, d16, d17 +0xe2,0x01,0x40,0xf2 = vrhadd.s8 q8, q8, q9 +0xe2,0x01,0x50,0xf2 = vrhadd.s16 q8, q8, q9 +0xe2,0x01,0x60,0xf2 = vrhadd.s32 q8, q8, q9 +0xe2,0x01,0x40,0xf3 = vrhadd.u8 q8, q8, q9 +0xe2,0x01,0x50,0xf3 = vrhadd.u16 q8, q8, q9 +0xe2,0x01,0x60,0xf3 = vrhadd.u32 q8, q8, q9 +0xa1,0x01,0x40,0xf2 = vrhadd.s8 d16, d16, d17 +0xa1,0x01,0x50,0xf2 = vrhadd.s16 d16, d16, d17 +0xa1,0x01,0x60,0xf2 = vrhadd.s32 d16, d16, d17 +0xa1,0x01,0x40,0xf3 = vrhadd.u8 d16, d16, d17 +0xa1,0x01,0x50,0xf3 = vrhadd.u16 d16, d16, d17 +0xa1,0x01,0x60,0xf3 = vrhadd.u32 d16, d16, d17 +0xe2,0x01,0x40,0xf2 = vrhadd.s8 q8, q8, q9 +0xe2,0x01,0x50,0xf2 = vrhadd.s16 q8, q8, q9 +0xe2,0x01,0x60,0xf2 = vrhadd.s32 q8, q8, q9 +0xe2,0x01,0x40,0xf3 = vrhadd.u8 q8, q8, q9 +0xe2,0x01,0x50,0xf3 = vrhadd.u16 q8, q8, q9 +0xe2,0x01,0x60,0xf3 = vrhadd.u32 q8, q8, q9 +0xb1,0x00,0x40,0xf2 = vqadd.s8 d16, d16, d17 +0xb1,0x00,0x50,0xf2 = vqadd.s16 d16, d16, d17 +0xb1,0x00,0x60,0xf2 = vqadd.s32 d16, d16, d17 +0xb1,0x00,0x70,0xf2 = vqadd.s64 d16, d16, d17 +0xb1,0x00,0x40,0xf3 = vqadd.u8 d16, d16, d17 +0xb1,0x00,0x50,0xf3 = vqadd.u16 d16, d16, d17 +0xb1,0x00,0x60,0xf3 = vqadd.u32 d16, d16, d17 +0xb1,0x00,0x70,0xf3 = vqadd.u64 d16, d16, d17 +0xf2,0x00,0x40,0xf2 = vqadd.s8 q8, q8, q9 +0xf2,0x00,0x50,0xf2 = vqadd.s16 q8, q8, q9 +0xf2,0x00,0x60,0xf2 = vqadd.s32 q8, q8, q9 +0xf2,0x00,0x70,0xf2 = vqadd.s64 q8, q8, q9 +0xf2,0x00,0x40,0xf3 = vqadd.u8 q8, q8, q9 +0xf2,0x00,0x50,0xf3 = vqadd.u16 q8, q8, q9 +0xf2,0x00,0x60,0xf3 = vqadd.u32 q8, q8, q9 +0xf2,0x00,0x70,0xf3 = vqadd.u64 q8, q8, q9 +0xb1,0x00,0x40,0xf2 = vqadd.s8 d16, d16, d17 +0xb1,0x00,0x50,0xf2 = vqadd.s16 d16, d16, d17 +0xb1,0x00,0x60,0xf2 = vqadd.s32 d16, d16, d17 +0xb1,0x00,0x70,0xf2 = vqadd.s64 d16, d16, d17 +0xb1,0x00,0x40,0xf3 = vqadd.u8 d16, d16, d17 +0xb1,0x00,0x50,0xf3 = vqadd.u16 d16, d16, d17 +0xb1,0x00,0x60,0xf3 = vqadd.u32 d16, d16, d17 +0xb1,0x00,0x70,0xf3 = vqadd.u64 d16, d16, d17 +0xf2,0x00,0x40,0xf2 = vqadd.s8 q8, q8, q9 +0xf2,0x00,0x50,0xf2 = vqadd.s16 q8, q8, q9 +0xf2,0x00,0x60,0xf2 = vqadd.s32 q8, q8, q9 +0xf2,0x00,0x70,0xf2 = vqadd.s64 q8, q8, q9 +0xf2,0x00,0x40,0xf3 = vqadd.u8 q8, q8, q9 +0xf2,0x00,0x50,0xf3 = vqadd.u16 q8, q8, q9 +0xf2,0x00,0x60,0xf3 = vqadd.u32 q8, q8, q9 +0xf2,0x00,0x70,0xf3 = vqadd.u64 q8, q8, q9 +0xa2,0x04,0xc0,0xf2 = vaddhn.i16 d16, q8, q9 +0xa2,0x04,0xd0,0xf2 = vaddhn.i32 d16, q8, q9 +0xa2,0x04,0xe0,0xf2 = vaddhn.i64 d16, q8, q9 +0xa2,0x04,0xc0,0xf3 = vraddhn.i16 d16, q8, q9 +0xa2,0x04,0xd0,0xf3 = vraddhn.i32 d16, q8, q9 +0xa2,0x04,0xe0,0xf3 = vraddhn.i64 d16, q8, q9 +0x05,0x68,0x06,0xf2 = vadd.i8 d6, d6, d5 +0x01,0x78,0x17,0xf2 = vadd.i16 d7, d7, d1 +0x02,0x88,0x28,0xf2 = vadd.i32 d8, d8, d2 +0x03,0x98,0x39,0xf2 = vadd.i64 d9, d9, d3 +0x4a,0xc8,0x0c,0xf2 = vadd.i8 q6, q6, q5 +0x42,0xe8,0x1e,0xf2 = vadd.i16 q7, q7, q1 +0xc4,0x08,0x60,0xf2 = vadd.i32 q8, q8, q2 +0xc6,0x28,0x72,0xf2 = vadd.i64 q9, q9, q3 +0x05,0xc1,0x8c,0xf2 = vaddw.s8 q6, q6, d5 +0x01,0xe1,0x9e,0xf2 = vaddw.s16 q7, q7, d1 +0x82,0x01,0xe0,0xf2 = vaddw.s32 q8, q8, d2 +0x05,0xc1,0x8c,0xf3 = vaddw.u8 q6, q6, d5 +0x01,0xe1,0x9e,0xf3 = vaddw.u16 q7, q7, d1 +0x82,0x01,0xe0,0xf3 = vaddw.u32 q8, q8, d2 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-bitcount-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-bitcount-encoding.s.cs new file mode 100644 index 0000000..9c75cc1 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-bitcount-encoding.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x20,0x05,0xf0,0xf3 = vcnt.8 d16, d16 +0x60,0x05,0xf0,0xf3 = vcnt.8 q8, q8 +0xa0,0x04,0xf0,0xf3 = vclz.i8 d16, d16 +0xa0,0x04,0xf4,0xf3 = vclz.i16 d16, d16 +0xa0,0x04,0xf8,0xf3 = vclz.i32 d16, d16 +0xe0,0x04,0xf0,0xf3 = vclz.i8 q8, q8 +0xe0,0x04,0xf4,0xf3 = vclz.i16 q8, q8 +0xe0,0x04,0xf8,0xf3 = vclz.i32 q8, q8 +0x20,0x04,0xf0,0xf3 = vcls.s8 d16, d16 +0x20,0x04,0xf4,0xf3 = vcls.s16 d16, d16 +0x20,0x04,0xf8,0xf3 = vcls.s32 d16, d16 +0x60,0x04,0xf0,0xf3 = vcls.s8 q8, q8 +0x60,0x04,0xf4,0xf3 = vcls.s16 q8, q8 +0x60,0x04,0xf8,0xf3 = vcls.s32 q8, q8 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-bitwise-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-bitwise-encoding.s.cs new file mode 100644 index 0000000..1154b2e --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-bitwise-encoding.s.cs @@ -0,0 +1,152 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xb0,0x01,0x41,0xf2 = vand d16, d17, d16 +0xf2,0x01,0x40,0xf2 = vand q8, q8, q9 +0xb0,0x01,0x41,0xf3 = veor d16, d17, d16 +0xf2,0x01,0x40,0xf3 = veor q8, q8, q9 +0xb0,0x01,0x61,0xf2 = vorr d16, d17, d16 +0xf2,0x01,0x60,0xf2 = vorr q8, q8, q9 +0x11,0x07,0xc0,0xf2 = vorr.i32 d16, #0x1000000 +0x51,0x07,0xc0,0xf2 = vorr.i32 q8, #0x1000000 +0x50,0x01,0xc0,0xf2 = vorr.i32 q8, #0x0 +0xb0,0x01,0x51,0xf2 = vbic d16, d17, d16 +0xf2,0x01,0x50,0xf2 = vbic q8, q8, q9 +0xf6,0x41,0x54,0xf2 = vbic q10, q10, q11 +0x11,0x91,0x19,0xf2 = vbic d9, d9, d1 +0x3f,0x0b,0xc7,0xf3 = vbic.i16 d16, #0xff00 +0x7f,0x0b,0xc7,0xf3 = vbic.i16 q8, #0xff00 +0x3f,0x09,0xc7,0xf3 = vbic.i16 d16, #0xff +0x7f,0x09,0xc7,0xf3 = vbic.i16 q8, #0xff +0x3f,0x07,0xc7,0xf3 = vbic.i32 d16, #0xff000000 +0x7f,0x07,0xc7,0xf3 = vbic.i32 q8, #0xff000000 +0x3f,0x05,0xc7,0xf3 = vbic.i32 d16, #0xff0000 +0x7f,0x05,0xc7,0xf3 = vbic.i32 q8, #0xff0000 +0x3f,0x03,0xc7,0xf3 = vbic.i32 d16, #0xff00 +0x7f,0x03,0xc7,0xf3 = vbic.i32 q8, #0xff00 +0x3f,0x01,0xc7,0xf3 = vbic.i32 d16, #0xff +0x7f,0x01,0xc7,0xf3 = vbic.i32 q8, #0xff +0x3c,0xa9,0x87,0xf3 = vbic.i16 d10, #0xfc +0x7c,0x49,0xc7,0xf3 = vbic.i16 q10, #0xfc +0x3c,0xab,0x87,0xf3 = vbic.i16 d10, #0xfc00 +0x7c,0x4b,0xc7,0xf3 = vbic.i16 q10, #0xfc00 +0x3c,0xa7,0x87,0xf3 = vbic.i32 d10, #0xfc000000 +0x7c,0x47,0xc7,0xf3 = vbic.i32 q10, #0xfc000000 +0x3c,0xa5,0x87,0xf3 = vbic.i32 d10, #0xfc0000 +0x7c,0x45,0xc7,0xf3 = vbic.i32 q10, #0xfc0000 +0x3c,0xa3,0x87,0xf3 = vbic.i32 d10, #0xfc00 +0x7c,0x43,0xc7,0xf3 = vbic.i32 q10, #0xfc00 +0x3c,0xa1,0x87,0xf3 = vbic.i32 d10, #0xfc +0x7c,0x41,0xc7,0xf3 = vbic.i32 q10, #0xfc +0xb0,0x01,0x71,0xf2 = vorn d16, d17, d16 +0xf2,0x01,0x70,0xf2 = vorn q8, q8, q9 +0xa0,0x05,0xf0,0xf3 = vmvn d16, d16 +0xe0,0x05,0xf0,0xf3 = vmvn q8, q8 +0xb0,0x21,0x51,0xf3 = vbsl d18, d17, d16 +0xf2,0x01,0x54,0xf3 = vbsl q8, q10, q9 +0xb0,0x21,0x61,0xf3 = vbit d18, d17, d16 +0xf2,0x01,0x64,0xf3 = vbit q8, q10, q9 +0xb0,0x21,0x71,0xf3 = vbif d18, d17, d16 +0xf2,0x01,0x74,0xf3 = vbif q8, q10, q9 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x07,0xf2 = vand d4, d7, d3 +0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 +0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 +0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 +0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 +0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 +0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 +0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 +0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 +0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 +0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 +0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 +0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 +0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 +0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 +0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 +0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 +0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 +0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 +0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 +0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 +0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 +0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 +0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 +0x5a,0xc1,0x0c,0xf2 = vand q6, q6, q5 +0x5a,0xc1,0x0c,0xf2 = vand q6, q6, q5 +0x52,0xe1,0x0e,0xf2 = vand q7, q7, q1 +0xd4,0x01,0x40,0xf2 = vand q8, q8, q2 +0xd4,0x01,0x40,0xf2 = vand q8, q8, q2 +0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5 +0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5 +0x52,0xe1,0x0e,0xf3 = veor q7, q7, q1 +0xd4,0x01,0x40,0xf3 = veor q8, q8, q2 +0xd4,0x01,0x40,0xf3 = veor q8, q8, q2 +0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5 +0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5 +0x52,0xe1,0x0e,0xf3 = veor q7, q7, q1 +0xd4,0x01,0x40,0xf3 = veor q8, q8, q2 +0xd4,0x01,0x40,0xf3 = veor q8, q8, q2 +0x4a,0xa2,0xb5,0xf3 = vclt.s16 q5, q5, #0 +0x05,0x52,0xb5,0xf3 = vclt.s16 d5, d5, #0 +0x56,0xa8,0x1a,0xf3 = vceq.i16 q5, q5, q3 +0x13,0x58,0x15,0xf3 = vceq.i16 d5, d5, d3 +0x46,0xa3,0x1a,0xf2 = vcgt.s16 q5, q5, q3 +0x03,0x53,0x15,0xf2 = vcgt.s16 d5, d5, d3 +0x56,0xa3,0x1a,0xf2 = vcge.s16 q5, q5, q3 +0x13,0x53,0x15,0xf2 = vcge.s16 d5, d5, d3 +0x4a,0xa0,0xb5,0xf3 = vcgt.s16 q5, q5, #0 +0x05,0x50,0xb5,0xf3 = vcgt.s16 d5, d5, #0 +0xca,0xa0,0xb5,0xf3 = vcge.s16 q5, q5, #0 +0x85,0x50,0xb5,0xf3 = vcge.s16 d5, d5, #0 +0x4a,0xa1,0xb5,0xf3 = vceq.i16 q5, q5, #0 +0x05,0x51,0xb5,0xf3 = vceq.i16 d5, d5, #0 +0xca,0xa1,0xb5,0xf3 = vcle.s16 q5, q5, #0 +0x85,0x51,0xb5,0xf3 = vcle.s16 d5, d5, #0 +0x3e,0x5e,0x05,0xf3 = vacge.f32 d5, d5, d30 +0x56,0xae,0x0a,0xf3 = vacge.f32 q5, q5, q3 +0x3e,0x5e,0x25,0xf3 = vacgt.f32 d5, d5, d30 +0x56,0xae,0x2a,0xf3 = vacgt.f32 q5, q5, q3 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-cmp-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-cmp-encoding.s.cs new file mode 100644 index 0000000..dd397ba --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-cmp-encoding.s.cs @@ -0,0 +1,88 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xb1,0x08,0x40,0xf3 = vceq.i8 d16, d16, d17 +0xb1,0x08,0x50,0xf3 = vceq.i16 d16, d16, d17 +0xb1,0x08,0x60,0xf3 = vceq.i32 d16, d16, d17 +0xa1,0x0e,0x40,0xf2 = vceq.f32 d16, d16, d17 +0xf2,0x08,0x40,0xf3 = vceq.i8 q8, q8, q9 +0xf2,0x08,0x50,0xf3 = vceq.i16 q8, q8, q9 +0xf2,0x08,0x60,0xf3 = vceq.i32 q8, q8, q9 +0xe2,0x0e,0x40,0xf2 = vceq.f32 q8, q8, q9 +0xb1,0x03,0x40,0xf2 = vcge.s8 d16, d16, d17 +0xb1,0x03,0x50,0xf2 = vcge.s16 d16, d16, d17 +0xb1,0x03,0x60,0xf2 = vcge.s32 d16, d16, d17 +0xb1,0x03,0x40,0xf3 = vcge.u8 d16, d16, d17 +0xb1,0x03,0x50,0xf3 = vcge.u16 d16, d16, d17 +0xb1,0x03,0x60,0xf3 = vcge.u32 d16, d16, d17 +0xa1,0x0e,0x40,0xf3 = vcge.f32 d16, d16, d17 +0xf2,0x03,0x40,0xf2 = vcge.s8 q8, q8, q9 +0xf2,0x03,0x50,0xf2 = vcge.s16 q8, q8, q9 +0xf2,0x03,0x60,0xf2 = vcge.s32 q8, q8, q9 +0xf2,0x03,0x40,0xf3 = vcge.u8 q8, q8, q9 +0xf2,0x03,0x50,0xf3 = vcge.u16 q8, q8, q9 +0xf2,0x03,0x60,0xf3 = vcge.u32 q8, q8, q9 +0xe2,0x0e,0x40,0xf3 = vcge.f32 q8, q8, q9 +0xb1,0x0e,0x40,0xf3 = vacge.f32 d16, d16, d17 +0xf2,0x0e,0x40,0xf3 = vacge.f32 q8, q8, q9 +0xa1,0x03,0x40,0xf2 = vcgt.s8 d16, d16, d17 +0xa1,0x03,0x50,0xf2 = vcgt.s16 d16, d16, d17 +0xa1,0x03,0x60,0xf2 = vcgt.s32 d16, d16, d17 +0xa1,0x03,0x40,0xf3 = vcgt.u8 d16, d16, d17 +0xa1,0x03,0x50,0xf3 = vcgt.u16 d16, d16, d17 +0xa1,0x03,0x60,0xf3 = vcgt.u32 d16, d16, d17 +0xa1,0x0e,0x60,0xf3 = vcgt.f32 d16, d16, d17 +0xe2,0x03,0x40,0xf2 = vcgt.s8 q8, q8, q9 +0xe2,0x03,0x50,0xf2 = vcgt.s16 q8, q8, q9 +0xe2,0x03,0x60,0xf2 = vcgt.s32 q8, q8, q9 +0xe2,0x03,0x40,0xf3 = vcgt.u8 q8, q8, q9 +0xe2,0x03,0x50,0xf3 = vcgt.u16 q8, q8, q9 +0xe2,0x03,0x60,0xf3 = vcgt.u32 q8, q8, q9 +0xe2,0x0e,0x60,0xf3 = vcgt.f32 q8, q8, q9 +0xb1,0x0e,0x60,0xf3 = vacgt.f32 d16, d16, d17 +0xf2,0x0e,0x60,0xf3 = vacgt.f32 q8, q8, q9 +0xb1,0x08,0x40,0xf2 = vtst.8 d16, d16, d17 +0xb1,0x08,0x50,0xf2 = vtst.16 d16, d16, d17 +0xb1,0x08,0x60,0xf2 = vtst.32 d16, d16, d17 +0xf2,0x08,0x40,0xf2 = vtst.8 q8, q8, q9 +0xf2,0x08,0x50,0xf2 = vtst.16 q8, q8, q9 +0xf2,0x08,0x60,0xf2 = vtst.32 q8, q8, q9 +0x20,0x01,0xf1,0xf3 = vceq.i8 d16, d16, #0 +0xa0,0x00,0xf1,0xf3 = vcge.s8 d16, d16, #0 +0xa0,0x01,0xf1,0xf3 = vcle.s8 d16, d16, #0 +0x20,0x00,0xf1,0xf3 = vcgt.s8 d16, d16, #0 +0x20,0x02,0xf1,0xf3 = vclt.s8 d16, d16, #0 +0x6a,0x83,0x46,0xf2 = vcgt.s8 q12, q3, q13 +0x6a,0x83,0x56,0xf2 = vcgt.s16 q12, q3, q13 +0x6a,0x83,0x66,0xf2 = vcgt.s32 q12, q3, q13 +0x6a,0x83,0x46,0xf3 = vcgt.u8 q12, q3, q13 +0x6a,0x83,0x56,0xf3 = vcgt.u16 q12, q3, q13 +0x6a,0x83,0x66,0xf3 = vcgt.u32 q12, q3, q13 +0x6a,0x8e,0x66,0xf3 = vcgt.f32 q12, q3, q13 +0x0d,0xc3,0x03,0xf2 = vcgt.s8 d12, d3, d13 +0x0d,0xc3,0x13,0xf2 = vcgt.s16 d12, d3, d13 +0x0d,0xc3,0x23,0xf2 = vcgt.s32 d12, d3, d13 +0x0d,0xc3,0x03,0xf3 = vcgt.u8 d12, d3, d13 +0x0d,0xc3,0x13,0xf3 = vcgt.u16 d12, d3, d13 +0x0d,0xc3,0x23,0xf3 = vcgt.u32 d12, d3, d13 +0x0d,0xce,0x23,0xf3 = vcgt.f32 d12, d3, d13 +0xb0,0x03,0x41,0xf2 = vcge.s8 d16, d17, d16 +0xb0,0x03,0x51,0xf2 = vcge.s16 d16, d17, d16 +0xb0,0x03,0x61,0xf2 = vcge.s32 d16, d17, d16 +0xb0,0x03,0x41,0xf3 = vcge.u8 d16, d17, d16 +0xb0,0x03,0x51,0xf3 = vcge.u16 d16, d17, d16 +0xb0,0x03,0x61,0xf3 = vcge.u32 d16, d17, d16 +0xa0,0x0e,0x41,0xf3 = vcge.f32 d16, d17, d16 +0xf0,0x03,0x42,0xf2 = vcge.s8 q8, q9, q8 +0xf0,0x03,0x52,0xf2 = vcge.s16 q8, q9, q8 +0xf0,0x03,0x62,0xf2 = vcge.s32 q8, q9, q8 +0xf0,0x03,0x42,0xf3 = vcge.u8 q8, q9, q8 +0xf0,0x03,0x52,0xf3 = vcge.u16 q8, q9, q8 +0xf0,0x03,0x62,0xf3 = vcge.u32 q8, q9, q8 +0xe0,0x0e,0x42,0xf3 = vcge.f32 q8, q9, q8 +0xf6,0x2e,0x68,0xf3 = vacgt.f32 q9, q12, q11 +0x1b,0x9e,0x2c,0xf3 = vacgt.f32 d9, d12, d11 +0xf6,0x6e,0x68,0xf3 = vacgt.f32 q11, q12, q11 +0x1b,0xbe,0x2c,0xf3 = vacgt.f32 d11, d12, d11 +0xf6,0x2e,0x48,0xf3 = vacge.f32 q9, q12, q11 +0x1b,0x9e,0x0c,0xf3 = vacge.f32 d9, d12, d11 +0xf6,0x6e,0x48,0xf3 = vacge.f32 q11, q12, q11 +0x1b,0xbe,0x0c,0xf3 = vacge.f32 d11, d12, d11 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-convert-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-convert-encoding.s.cs new file mode 100644 index 0000000..0344353 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-convert-encoding.s.cs @@ -0,0 +1,27 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16 +0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16 +0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16 +0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16 +0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8 +0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8 +0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8 +0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8 +0x30,0x0f,0xff,0xf2 = vcvt.s32.f32 d16, d16, #1 +0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16 +0x30,0x0f,0xff,0xf3 = vcvt.u32.f32 d16, d16, #1 +0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16 +0x30,0x0e,0xff,0xf2 = vcvt.f32.s32 d16, d16, #1 +0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16 +0x30,0x0e,0xff,0xf3 = vcvt.f32.u32 d16, d16, #1 +0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16 +0x70,0x0f,0xff,0xf2 = vcvt.s32.f32 q8, q8, #1 +0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8 +0x70,0x0f,0xff,0xf3 = vcvt.u32.f32 q8, q8, #1 +0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8 +0x70,0x0e,0xff,0xf2 = vcvt.f32.s32 q8, q8, #1 +0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8 +0x70,0x0e,0xff,0xf3 = vcvt.f32.u32 q8, q8, #1 +0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8 +0x20,0x07,0xf6,0xf3 = vcvt.f32.f16 q8, d16 +0x20,0x06,0xf6,0xf3 = vcvt.f16.f32 d16, q8 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-crypto.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-crypto.s.cs new file mode 100644 index 0000000..3cb081a --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-crypto.s.cs @@ -0,0 +1,16 @@ +# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None +0x42,0x03,0xb0,0xf3 = aesd.8 q0, q1 +0x02,0x03,0xb0,0xf3 = aese.8 q0, q1 +0xc2,0x03,0xb0,0xf3 = aesimc.8 q0, q1 +0x82,0x03,0xb0,0xf3 = aesmc.8 q0, q1 +0xc2,0x02,0xb9,0xf3 = sha1h.32 q0, q1 +0x82,0x03,0xba,0xf3 = sha1su1.32 q0, q1 +0xc2,0x03,0xba,0xf3 = sha256su0.32 q0, q1 +0x44,0x0c,0x02,0xf2 = sha1c.32 q0, q1, q2 +0x44,0x0c,0x22,0xf2 = sha1m.32 q0, q1, q2 +0x44,0x0c,0x12,0xf2 = sha1p.32 q0, q1, q2 +0x44,0x0c,0x32,0xf2 = sha1su0.32 q0, q1, q2 +0x44,0x0c,0x02,0xf3 = sha256h.32 q0, q1, q2 +0x44,0x0c,0x12,0xf3 = sha256h2.32 q0, q1, q2 +0x44,0x0c,0x22,0xf3 = sha256su1.32 q0, q1, q2 +0xa1,0x0e,0xe0,0xf2 = vmull.p64 q8, d16, d17 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-dup-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-dup-encoding.s.cs new file mode 100644 index 0000000..8e57cd9 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-dup-encoding.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x90,0x0b,0xc0,0xee = vdup.8 d16, r0 +0xb0,0x0b,0x80,0xee = vdup.16 d16, r0 +0x90,0x0b,0x80,0xee = vdup.32 d16, r0 +0x90,0x0b,0xe0,0xee = vdup.8 q8, r0 +0xb0,0x0b,0xa0,0xee = vdup.16 q8, r0 +0x90,0x0b,0xa0,0xee = vdup.32 q8, r0 +0x20,0x0c,0xf3,0xf3 = vdup.8 d16, d16[1] +0x20,0x0c,0xf6,0xf3 = vdup.16 d16, d16[1] +0x20,0x0c,0xfc,0xf3 = vdup.32 d16, d16[1] +0x60,0x0c,0xf3,0xf3 = vdup.8 q8, d16[1] +0x60,0x0c,0xf6,0xf3 = vdup.16 q8, d16[1] +0x60,0x0c,0xfc,0xf3 = vdup.32 q8, d16[1] diff --git a/thirdparty/capstone/suite/MC/ARM/neon-minmax-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-minmax-encoding.s.cs new file mode 100644 index 0000000..9139764 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-minmax-encoding.s.cs @@ -0,0 +1,57 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x03,0x16,0x02,0xf2 = vmax.s8 d1, d2, d3 +0x06,0x46,0x15,0xf2 = vmax.s16 d4, d5, d6 +0x09,0x76,0x28,0xf2 = vmax.s32 d7, d8, d9 +0x0c,0xa6,0x0b,0xf3 = vmax.u8 d10, d11, d12 +0x0f,0xd6,0x1e,0xf3 = vmax.u16 d13, d14, d15 +0xa2,0x06,0x61,0xf3 = vmax.u32 d16, d17, d18 +0xa5,0x3f,0x44,0xf2 = vmax.f32 d19, d20, d21 +0x03,0x26,0x02,0xf2 = vmax.s8 d2, d2, d3 +0x06,0x56,0x15,0xf2 = vmax.s16 d5, d5, d6 +0x09,0x86,0x28,0xf2 = vmax.s32 d8, d8, d9 +0x0c,0xb6,0x0b,0xf3 = vmax.u8 d11, d11, d12 +0x0f,0xe6,0x1e,0xf3 = vmax.u16 d14, d14, d15 +0xa2,0x16,0x61,0xf3 = vmax.u32 d17, d17, d18 +0xa5,0x4f,0x44,0xf2 = vmax.f32 d20, d20, d21 +0x46,0x26,0x04,0xf2 = vmax.s8 q1, q2, q3 +0x4c,0x86,0x1a,0xf2 = vmax.s16 q4, q5, q6 +0xe2,0xe6,0x20,0xf2 = vmax.s32 q7, q8, q9 +0xe8,0x46,0x46,0xf3 = vmax.u8 q10, q11, q12 +0xee,0xa6,0x5c,0xf3 = vmax.u16 q13, q14, q15 +0x60,0xc6,0x2e,0xf3 = vmax.u32 q6, q7, q8 +0x42,0x2f,0x4a,0xf2 = vmax.f32 q9, q5, q1 +0x46,0x46,0x04,0xf2 = vmax.s8 q2, q2, q3 +0x4c,0xa6,0x1a,0xf2 = vmax.s16 q5, q5, q6 +0xe2,0x06,0x60,0xf2 = vmax.s32 q8, q8, q9 +0xc4,0x66,0x46,0xf3 = vmax.u8 q11, q11, q2 +0x4a,0x86,0x18,0xf3 = vmax.u16 q4, q4, q5 +0x60,0xe6,0x2e,0xf3 = vmax.u32 q7, q7, q8 +0x42,0x4f,0x04,0xf2 = vmax.f32 q2, q2, q1 +0x13,0x16,0x02,0xf2 = vmin.s8 d1, d2, d3 +0x16,0x46,0x15,0xf2 = vmin.s16 d4, d5, d6 +0x19,0x76,0x28,0xf2 = vmin.s32 d7, d8, d9 +0x1c,0xa6,0x0b,0xf3 = vmin.u8 d10, d11, d12 +0x1f,0xd6,0x1e,0xf3 = vmin.u16 d13, d14, d15 +0xb2,0x06,0x61,0xf3 = vmin.u32 d16, d17, d18 +0xa5,0x3f,0x64,0xf2 = vmin.f32 d19, d20, d21 +0x13,0x26,0x02,0xf2 = vmin.s8 d2, d2, d3 +0x16,0x56,0x15,0xf2 = vmin.s16 d5, d5, d6 +0x19,0x86,0x28,0xf2 = vmin.s32 d8, d8, d9 +0x1c,0xb6,0x0b,0xf3 = vmin.u8 d11, d11, d12 +0x1f,0xe6,0x1e,0xf3 = vmin.u16 d14, d14, d15 +0xb2,0x16,0x61,0xf3 = vmin.u32 d17, d17, d18 +0xa5,0x4f,0x64,0xf2 = vmin.f32 d20, d20, d21 +0x56,0x26,0x04,0xf2 = vmin.s8 q1, q2, q3 +0x5c,0x86,0x1a,0xf2 = vmin.s16 q4, q5, q6 +0xf2,0xe6,0x20,0xf2 = vmin.s32 q7, q8, q9 +0xf8,0x46,0x46,0xf3 = vmin.u8 q10, q11, q12 +0xfe,0xa6,0x5c,0xf3 = vmin.u16 q13, q14, q15 +0x70,0xc6,0x2e,0xf3 = vmin.u32 q6, q7, q8 +0x42,0x2f,0x6a,0xf2 = vmin.f32 q9, q5, q1 +0x56,0x46,0x04,0xf2 = vmin.s8 q2, q2, q3 +0x5c,0xa6,0x1a,0xf2 = vmin.s16 q5, q5, q6 +0xf2,0x06,0x60,0xf2 = vmin.s32 q8, q8, q9 +0xd4,0x66,0x46,0xf3 = vmin.u8 q11, q11, q2 +0x5a,0x86,0x18,0xf3 = vmin.u16 q4, q4, q5 +0x70,0xe6,0x2e,0xf3 = vmin.u32 q7, q7, q8 +0x42,0x4f,0x24,0xf2 = vmin.f32 q2, q2, q1 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-mov-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-mov-encoding.s.cs new file mode 100644 index 0000000..7a53d2b --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-mov-encoding.s.cs @@ -0,0 +1,76 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x18,0x0e,0xc0,0xf2 = vmov.i8 d16, #0x8 +0x10,0x08,0xc1,0xf2 = vmov.i16 d16, #0x10 +0x10,0x0a,0xc1,0xf2 = vmov.i16 d16, #0x1000 +0x10,0x00,0xc2,0xf2 = vmov.i32 d16, #0x20 +0x10,0x02,0xc2,0xf2 = vmov.i32 d16, #0x2000 +0x10,0x04,0xc2,0xf2 = vmov.i32 d16, #0x200000 +0x10,0x06,0xc2,0xf2 = vmov.i32 d16, #0x20000000 +0x10,0x0c,0xc2,0xf2 = vmov.i32 d16, #0x20ff +0x10,0x0d,0xc2,0xf2 = vmov.i32 d16, #0x20ffff +0x33,0x0e,0xc1,0xf3 = vmov.i64 d16, #0xff0000ff0000ffff +0x58,0x0e,0xc0,0xf2 = vmov.i8 q8, #0x8 +0x50,0x08,0xc1,0xf2 = vmov.i16 q8, #0x10 +0x50,0x0a,0xc1,0xf2 = vmov.i16 q8, #0x1000 +0x50,0x00,0xc2,0xf2 = vmov.i32 q8, #0x20 +0x50,0x02,0xc2,0xf2 = vmov.i32 q8, #0x2000 +0x50,0x04,0xc2,0xf2 = vmov.i32 q8, #0x200000 +0x50,0x06,0xc2,0xf2 = vmov.i32 q8, #0x20000000 +0x50,0x0c,0xc2,0xf2 = vmov.i32 q8, #0x20ff +0x50,0x0d,0xc2,0xf2 = vmov.i32 q8, #0x20ffff +0x73,0x0e,0xc1,0xf3 = vmov.i64 q8, #0xff0000ff0000ffff +0x30,0x08,0xc1,0xf2 = vmvn.i16 d16, #0x10 +0x30,0x0a,0xc1,0xf2 = vmvn.i16 d16, #0x1000 +0x30,0x00,0xc2,0xf2 = vmvn.i32 d16, #0x20 +0x30,0x02,0xc2,0xf2 = vmvn.i32 d16, #0x2000 +0x30,0x04,0xc2,0xf2 = vmvn.i32 d16, #0x200000 +0x30,0x06,0xc2,0xf2 = vmvn.i32 d16, #0x20000000 +0x30,0x0c,0xc2,0xf2 = vmvn.i32 d16, #0x20ff +0x30,0x0d,0xc2,0xf2 = vmvn.i32 d16, #0x20ffff +0x30,0x0a,0xc8,0xf2 = vmovl.s8 q8, d16 +0x30,0x0a,0xd0,0xf2 = vmovl.s16 q8, d16 +0x30,0x0a,0xe0,0xf2 = vmovl.s32 q8, d16 +0x30,0x0a,0xc8,0xf3 = vmovl.u8 q8, d16 +0x30,0x0a,0xd0,0xf3 = vmovl.u16 q8, d16 +0x30,0x0a,0xe0,0xf3 = vmovl.u32 q8, d16 +0x20,0x02,0xf2,0xf3 = vmovn.i16 d16, q8 +0x20,0x02,0xf6,0xf3 = vmovn.i32 d16, q8 +0x20,0x02,0xfa,0xf3 = vmovn.i64 d16, q8 +0xa0,0x02,0xf2,0xf3 = vqmovn.s16 d16, q8 +0xa0,0x02,0xf6,0xf3 = vqmovn.s32 d16, q8 +0xa0,0x02,0xfa,0xf3 = vqmovn.s64 d16, q8 +0xe0,0x02,0xf2,0xf3 = vqmovn.u16 d16, q8 +0xe0,0x02,0xf6,0xf3 = vqmovn.u32 d16, q8 +0xe0,0x02,0xfa,0xf3 = vqmovn.u64 d16, q8 +0x60,0x02,0xf2,0xf3 = vqmovun.s16 d16, q8 +0x60,0x02,0xf6,0xf3 = vqmovun.s32 d16, q8 +0x60,0x02,0xfa,0xf3 = vqmovun.s64 d16, q8 +0xb0,0x0b,0x50,0xee = vmov.s8 r0, d16[1] +0xf0,0x0b,0x10,0xee = vmov.s16 r0, d16[1] +0xb0,0x0b,0xd0,0xee = vmov.u8 r0, d16[1] +0xf0,0x0b,0x90,0xee = vmov.u16 r0, d16[1] +0x90,0x0b,0x30,0xee = vmov.32 r0, d16[1] +0xb0,0x1b,0x40,0xee = vmov.8 d16[1], r1 +0xf0,0x1b,0x00,0xee = vmov.16 d16[1], r1 +0x90,0x1b,0x20,0xee = vmov.32 d16[1], r1 +0xb0,0x1b,0x42,0xee = vmov.8 d18[1], r1 +0xf0,0x1b,0x02,0xee = vmov.16 d18[1], r1 +0x90,0x1b,0x22,0xee = vmov.32 d18[1], r1 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 +0x82,0x15,0xb0,0xf3 = vmvn d1, d2 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-mul-accum-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-mul-accum-encoding.s.cs new file mode 100644 index 0000000..bb1b176 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-mul-accum-encoding.s.cs @@ -0,0 +1,39 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xa1,0x09,0x42,0xf2 = vmla.i8 d16, d18, d17 +0xa1,0x09,0x52,0xf2 = vmla.i16 d16, d18, d17 +0xa1,0x09,0x62,0xf2 = vmla.i32 d16, d18, d17 +0xb1,0x0d,0x42,0xf2 = vmla.f32 d16, d18, d17 +0xe4,0x29,0x40,0xf2 = vmla.i8 q9, q8, q10 +0xe4,0x29,0x50,0xf2 = vmla.i16 q9, q8, q10 +0xe4,0x29,0x60,0xf2 = vmla.i32 q9, q8, q10 +0xf4,0x2d,0x40,0xf2 = vmla.f32 q9, q8, q10 +0xc3,0x80,0xe0,0xf3 = vmla.i32 q12, q8, d3[0] +0xa2,0x08,0xc3,0xf2 = vmlal.s8 q8, d19, d18 +0xa2,0x08,0xd3,0xf2 = vmlal.s16 q8, d19, d18 +0xa2,0x08,0xe3,0xf2 = vmlal.s32 q8, d19, d18 +0xa2,0x08,0xc3,0xf3 = vmlal.u8 q8, d19, d18 +0xa2,0x08,0xd3,0xf3 = vmlal.u16 q8, d19, d18 +0xa2,0x08,0xe3,0xf3 = vmlal.u32 q8, d19, d18 +0xa2,0x09,0xd3,0xf2 = vqdmlal.s16 q8, d19, d18 +0xa2,0x09,0xe3,0xf2 = vqdmlal.s32 q8, d19, d18 +0x47,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[0] +0x4f,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[1] +0x67,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[2] +0x6f,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[3] +0xa1,0x09,0x42,0xf3 = vmls.i8 d16, d18, d17 +0xa1,0x09,0x52,0xf3 = vmls.i16 d16, d18, d17 +0xa1,0x09,0x62,0xf3 = vmls.i32 d16, d18, d17 +0xb1,0x0d,0x62,0xf2 = vmls.f32 d16, d18, d17 +0xe4,0x29,0x40,0xf3 = vmls.i8 q9, q8, q10 +0xe4,0x29,0x50,0xf3 = vmls.i16 q9, q8, q10 +0xe4,0x29,0x60,0xf3 = vmls.i32 q9, q8, q10 +0xf4,0x2d,0x60,0xf2 = vmls.f32 q9, q8, q10 +0xe6,0x84,0x98,0xf3 = vmls.i16 q4, q12, d6[2] +0xa2,0x0a,0xc3,0xf2 = vmlsl.s8 q8, d19, d18 +0xa2,0x0a,0xd3,0xf2 = vmlsl.s16 q8, d19, d18 +0xa2,0x0a,0xe3,0xf2 = vmlsl.s32 q8, d19, d18 +0xa2,0x0a,0xc3,0xf3 = vmlsl.u8 q8, d19, d18 +0xa2,0x0a,0xd3,0xf3 = vmlsl.u16 q8, d19, d18 +0xa2,0x0a,0xe3,0xf3 = vmlsl.u32 q8, d19, d18 +0xa2,0x0b,0xd3,0xf2 = vqdmlsl.s16 q8, d19, d18 +0xa2,0x0b,0xe3,0xf2 = vqdmlsl.s32 q8, d19, d18 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-mul-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-mul-encoding.s.cs new file mode 100644 index 0000000..728888b --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-mul-encoding.s.cs @@ -0,0 +1,72 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xb1,0x09,0x40,0xf2 = vmul.i8 d16, d16, d17 +0xb1,0x09,0x50,0xf2 = vmul.i16 d16, d16, d17 +0xb1,0x09,0x60,0xf2 = vmul.i32 d16, d16, d17 +0xb1,0x0d,0x40,0xf3 = vmul.f32 d16, d16, d17 +0xf2,0x09,0x40,0xf2 = vmul.i8 q8, q8, q9 +0xf2,0x09,0x50,0xf2 = vmul.i16 q8, q8, q9 +0xf2,0x09,0x60,0xf2 = vmul.i32 q8, q8, q9 +0xf2,0x0d,0x40,0xf3 = vmul.f32 q8, q8, q9 +0xb1,0x09,0x40,0xf3 = vmul.p8 d16, d16, d17 +0xf2,0x09,0x40,0xf3 = vmul.p8 q8, q8, q9 +0x68,0x28,0xd8,0xf2 = vmul.i16 d18, d8, d0[3] +0xb1,0x09,0x40,0xf2 = vmul.i8 d16, d16, d17 +0xb1,0x09,0x50,0xf2 = vmul.i16 d16, d16, d17 +0xb1,0x09,0x60,0xf2 = vmul.i32 d16, d16, d17 +0xb1,0x0d,0x40,0xf3 = vmul.f32 d16, d16, d17 +0xf2,0x09,0x40,0xf2 = vmul.i8 q8, q8, q9 +0xf2,0x09,0x50,0xf2 = vmul.i16 q8, q8, q9 +0xf2,0x09,0x60,0xf2 = vmul.i32 q8, q8, q9 +0xf2,0x0d,0x40,0xf3 = vmul.f32 q8, q8, q9 +0xb1,0x09,0x40,0xf3 = vmul.p8 d16, d16, d17 +0xf2,0x09,0x40,0xf3 = vmul.p8 q8, q8, q9 +0xa1,0x0b,0x50,0xf2 = vqdmulh.s16 d16, d16, d17 +0xa1,0x0b,0x60,0xf2 = vqdmulh.s32 d16, d16, d17 +0xe2,0x0b,0x50,0xf2 = vqdmulh.s16 q8, q8, q9 +0xe2,0x0b,0x60,0xf2 = vqdmulh.s32 q8, q8, q9 +0xa1,0x0b,0x50,0xf2 = vqdmulh.s16 d16, d16, d17 +0xa1,0x0b,0x60,0xf2 = vqdmulh.s32 d16, d16, d17 +0xe2,0x0b,0x50,0xf2 = vqdmulh.s16 q8, q8, q9 +0xe2,0x0b,0x60,0xf2 = vqdmulh.s32 q8, q8, q9 +0x43,0xbc,0x92,0xf2 = vqdmulh.s16 d11, d2, d3[0] +0xa1,0x0b,0x50,0xf3 = vqrdmulh.s16 d16, d16, d17 +0xa1,0x0b,0x60,0xf3 = vqrdmulh.s32 d16, d16, d17 +0xe2,0x0b,0x50,0xf3 = vqrdmulh.s16 q8, q8, q9 +0xe2,0x0b,0x60,0xf3 = vqrdmulh.s32 q8, q8, q9 +0xa1,0x0c,0xc0,0xf2 = vmull.s8 q8, d16, d17 +0xa1,0x0c,0xd0,0xf2 = vmull.s16 q8, d16, d17 +0xa1,0x0c,0xe0,0xf2 = vmull.s32 q8, d16, d17 +0xa1,0x0c,0xc0,0xf3 = vmull.u8 q8, d16, d17 +0xa1,0x0c,0xd0,0xf3 = vmull.u16 q8, d16, d17 +0xa1,0x0c,0xe0,0xf3 = vmull.u32 q8, d16, d17 +0xa1,0x0e,0xc0,0xf2 = vmull.p8 q8, d16, d17 +0xa1,0x0d,0xd0,0xf2 = vqdmull.s16 q8, d16, d17 +0xa1,0x0d,0xe0,0xf2 = vqdmull.s32 q8, d16, d17 +0x64,0x08,0x90,0xf2 = vmul.i16 d0, d0, d4[2] +0x6f,0x18,0x91,0xf2 = vmul.i16 d1, d1, d7[3] +0x49,0x28,0x92,0xf2 = vmul.i16 d2, d2, d1[1] +0x42,0x38,0xa3,0xf2 = vmul.i32 d3, d3, d2[0] +0x63,0x48,0xa4,0xf2 = vmul.i32 d4, d4, d3[1] +0x44,0x58,0xa5,0xf2 = vmul.i32 d5, d5, d4[0] +0x65,0x69,0xa6,0xf2 = vmul.f32 d6, d6, d5[1] +0x64,0x08,0x90,0xf3 = vmul.i16 q0, q0, d4[2] +0x6f,0x28,0x92,0xf3 = vmul.i16 q1, q1, d7[3] +0x49,0x48,0x94,0xf3 = vmul.i16 q2, q2, d1[1] +0x42,0x68,0xa6,0xf3 = vmul.i32 q3, q3, d2[0] +0x63,0x88,0xa8,0xf3 = vmul.i32 q4, q4, d3[1] +0x44,0xa8,0xaa,0xf3 = vmul.i32 q5, q5, d4[0] +0x65,0xc9,0xac,0xf3 = vmul.f32 q6, q6, d5[1] +0x64,0x98,0x90,0xf2 = vmul.i16 d9, d0, d4[2] +0x6f,0x88,0x91,0xf2 = vmul.i16 d8, d1, d7[3] +0x49,0x78,0x92,0xf2 = vmul.i16 d7, d2, d1[1] +0x42,0x68,0xa3,0xf2 = vmul.i32 d6, d3, d2[0] +0x63,0x58,0xa4,0xf2 = vmul.i32 d5, d4, d3[1] +0x44,0x48,0xa5,0xf2 = vmul.i32 d4, d5, d4[0] +0x65,0x39,0xa6,0xf2 = vmul.f32 d3, d6, d5[1] +0x64,0x28,0xd0,0xf3 = vmul.i16 q9, q0, d4[2] +0x6f,0x08,0xd2,0xf3 = vmul.i16 q8, q1, d7[3] +0x49,0xe8,0x94,0xf3 = vmul.i16 q7, q2, d1[1] +0x42,0xc8,0xa6,0xf3 = vmul.i32 q6, q3, d2[0] +0x63,0xa8,0xa8,0xf3 = vmul.i32 q5, q4, d3[1] +0x44,0x88,0xaa,0xf3 = vmul.i32 q4, q5, d4[0] +0x65,0x69,0xac,0xf3 = vmul.f32 q3, q6, d5[1] diff --git a/thirdparty/capstone/suite/MC/ARM/neon-neg-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-neg-encoding.s.cs new file mode 100644 index 0000000..d87147a --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-neg-encoding.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xa0,0x03,0xf1,0xf3 = vneg.s8 d16, d16 +0xa0,0x03,0xf5,0xf3 = vneg.s16 d16, d16 +0xa0,0x03,0xf9,0xf3 = vneg.s32 d16, d16 +0xa0,0x07,0xf9,0xf3 = vneg.f32 d16, d16 +0xe0,0x03,0xf1,0xf3 = vneg.s8 q8, q8 +0xe0,0x03,0xf5,0xf3 = vneg.s16 q8, q8 +0xe0,0x03,0xf9,0xf3 = vneg.s32 q8, q8 +0xe0,0x07,0xf9,0xf3 = vneg.f32 q8, q8 +0xa0,0x07,0xf0,0xf3 = vqneg.s8 d16, d16 +0xa0,0x07,0xf4,0xf3 = vqneg.s16 d16, d16 +0xa0,0x07,0xf8,0xf3 = vqneg.s32 d16, d16 +0xe0,0x07,0xf0,0xf3 = vqneg.s8 q8, q8 +0xe0,0x07,0xf4,0xf3 = vqneg.s16 q8, q8 +0xe0,0x07,0xf8,0xf3 = vqneg.s32 q8, q8 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-pairwise-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-pairwise-encoding.s.cs new file mode 100644 index 0000000..3183a57 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-pairwise-encoding.s.cs @@ -0,0 +1,47 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xb0,0x0b,0x41,0xf2 = vpadd.i8 d16, d17, d16 +0xb0,0x0b,0x51,0xf2 = vpadd.i16 d16, d17, d16 +0xb0,0x0b,0x61,0xf2 = vpadd.i32 d16, d17, d16 +0xa1,0x0d,0x40,0xf3 = vpadd.f32 d16, d16, d17 +0xb0,0x1b,0x41,0xf2 = vpadd.i8 d17, d17, d16 +0xb0,0x1b,0x51,0xf2 = vpadd.i16 d17, d17, d16 +0xb0,0x1b,0x61,0xf2 = vpadd.i32 d17, d17, d16 +0xa1,0x0d,0x40,0xf3 = vpadd.f32 d16, d16, d17 +0x20,0x02,0xf0,0xf3 = vpaddl.s8 d16, d16 +0x20,0x02,0xf4,0xf3 = vpaddl.s16 d16, d16 +0x20,0x02,0xf8,0xf3 = vpaddl.s32 d16, d16 +0xa0,0x02,0xf0,0xf3 = vpaddl.u8 d16, d16 +0xa0,0x02,0xf4,0xf3 = vpaddl.u16 d16, d16 +0xa0,0x02,0xf8,0xf3 = vpaddl.u32 d16, d16 +0x60,0x02,0xf0,0xf3 = vpaddl.s8 q8, q8 +0x60,0x02,0xf4,0xf3 = vpaddl.s16 q8, q8 +0x60,0x02,0xf8,0xf3 = vpaddl.s32 q8, q8 +0xe0,0x02,0xf0,0xf3 = vpaddl.u8 q8, q8 +0xe0,0x02,0xf4,0xf3 = vpaddl.u16 q8, q8 +0xe0,0x02,0xf8,0xf3 = vpaddl.u32 q8, q8 +0x21,0x06,0xf0,0xf3 = vpadal.s8 d16, d17 +0x21,0x06,0xf4,0xf3 = vpadal.s16 d16, d17 +0x21,0x06,0xf8,0xf3 = vpadal.s32 d16, d17 +0xa1,0x06,0xf0,0xf3 = vpadal.u8 d16, d17 +0xa1,0x06,0xf4,0xf3 = vpadal.u16 d16, d17 +0xa1,0x06,0xf8,0xf3 = vpadal.u32 d16, d17 +0x60,0x26,0xf0,0xf3 = vpadal.s8 q9, q8 +0x60,0x26,0xf4,0xf3 = vpadal.s16 q9, q8 +0x60,0x26,0xf8,0xf3 = vpadal.s32 q9, q8 +0xe0,0x26,0xf0,0xf3 = vpadal.u8 q9, q8 +0xe0,0x26,0xf4,0xf3 = vpadal.u16 q9, q8 +0xe0,0x26,0xf8,0xf3 = vpadal.u32 q9, q8 +0xb1,0x0a,0x40,0xf2 = vpmin.s8 d16, d16, d17 +0xb1,0x0a,0x50,0xf2 = vpmin.s16 d16, d16, d17 +0xb1,0x0a,0x60,0xf2 = vpmin.s32 d16, d16, d17 +0xb1,0x0a,0x40,0xf3 = vpmin.u8 d16, d16, d17 +0xb1,0x0a,0x50,0xf3 = vpmin.u16 d16, d16, d17 +0xb1,0x0a,0x60,0xf3 = vpmin.u32 d16, d16, d17 +0xa1,0x0f,0x60,0xf3 = vpmin.f32 d16, d16, d17 +0xa1,0x0a,0x40,0xf2 = vpmax.s8 d16, d16, d17 +0xa1,0x0a,0x50,0xf2 = vpmax.s16 d16, d16, d17 +0xa1,0x0a,0x60,0xf2 = vpmax.s32 d16, d16, d17 +0xa1,0x0a,0x40,0xf3 = vpmax.u8 d16, d16, d17 +0xa1,0x0a,0x50,0xf3 = vpmax.u16 d16, d16, d17 +0xa1,0x0a,0x60,0xf3 = vpmax.u32 d16, d16, d17 +0xa1,0x0f,0x40,0xf3 = vpmax.f32 d16, d16, d17 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-reciprocal-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-reciprocal-encoding.s.cs new file mode 100644 index 0000000..d2d8fff --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-reciprocal-encoding.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x20,0x04,0xfb,0xf3 = vrecpe.u32 d16, d16 +0x60,0x04,0xfb,0xf3 = vrecpe.u32 q8, q8 +0x20,0x05,0xfb,0xf3 = vrecpe.f32 d16, d16 +0x60,0x05,0xfb,0xf3 = vrecpe.f32 q8, q8 +0xb1,0x0f,0x40,0xf2 = vrecps.f32 d16, d16, d17 +0xf2,0x0f,0x40,0xf2 = vrecps.f32 q8, q8, q9 +0xa0,0x04,0xfb,0xf3 = vrsqrte.u32 d16, d16 +0xe0,0x04,0xfb,0xf3 = vrsqrte.u32 q8, q8 +0xa0,0x05,0xfb,0xf3 = vrsqrte.f32 d16, d16 +0xe0,0x05,0xfb,0xf3 = vrsqrte.f32 q8, q8 +0xb1,0x0f,0x60,0xf2 = vrsqrts.f32 d16, d16, d17 +0xf2,0x0f,0x60,0xf2 = vrsqrts.f32 q8, q8, q9 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-reverse-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-reverse-encoding.s.cs new file mode 100644 index 0000000..b005473 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-reverse-encoding.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x20,0x00,0xf0,0xf3 = vrev64.8 d16, d16 +0x20,0x00,0xf4,0xf3 = vrev64.16 d16, d16 +0x20,0x00,0xf8,0xf3 = vrev64.32 d16, d16 +0x60,0x00,0xf0,0xf3 = vrev64.8 q8, q8 +0x60,0x00,0xf4,0xf3 = vrev64.16 q8, q8 +0x60,0x00,0xf8,0xf3 = vrev64.32 q8, q8 +0xa0,0x00,0xf0,0xf3 = vrev32.8 d16, d16 +0xa0,0x00,0xf4,0xf3 = vrev32.16 d16, d16 +0xe0,0x00,0xf0,0xf3 = vrev32.8 q8, q8 +0xe0,0x00,0xf4,0xf3 = vrev32.16 q8, q8 +0x20,0x01,0xf0,0xf3 = vrev16.8 d16, d16 +0x60,0x01,0xf0,0xf3 = vrev16.8 q8, q8 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-satshift-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-satshift-encoding.s.cs new file mode 100644 index 0000000..5066cd9 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-satshift-encoding.s.cs @@ -0,0 +1,75 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xb0,0x04,0x41,0xf2 = vqshl.s8 d16, d16, d17 +0xb0,0x04,0x51,0xf2 = vqshl.s16 d16, d16, d17 +0xb0,0x04,0x61,0xf2 = vqshl.s32 d16, d16, d17 +0xb0,0x04,0x71,0xf2 = vqshl.s64 d16, d16, d17 +0xb0,0x04,0x41,0xf3 = vqshl.u8 d16, d16, d17 +0xb0,0x04,0x51,0xf3 = vqshl.u16 d16, d16, d17 +0xb0,0x04,0x61,0xf3 = vqshl.u32 d16, d16, d17 +0xb0,0x04,0x71,0xf3 = vqshl.u64 d16, d16, d17 +0xf0,0x04,0x42,0xf2 = vqshl.s8 q8, q8, q9 +0xf0,0x04,0x52,0xf2 = vqshl.s16 q8, q8, q9 +0xf0,0x04,0x62,0xf2 = vqshl.s32 q8, q8, q9 +0xf0,0x04,0x72,0xf2 = vqshl.s64 q8, q8, q9 +0xf0,0x04,0x42,0xf3 = vqshl.u8 q8, q8, q9 +0xf0,0x04,0x52,0xf3 = vqshl.u16 q8, q8, q9 +0xf0,0x04,0x62,0xf3 = vqshl.u32 q8, q8, q9 +0xf0,0x04,0x72,0xf3 = vqshl.u64 q8, q8, q9 +0x30,0x07,0xcf,0xf2 = vqshl.s8 d16, d16, #7 +0x30,0x07,0xdf,0xf2 = vqshl.s16 d16, d16, #0xf +0x30,0x07,0xff,0xf2 = vqshl.s32 d16, d16, #0x1f +0xb0,0x07,0xff,0xf2 = vqshl.s64 d16, d16, #0x3f +0x30,0x07,0xcf,0xf3 = vqshl.u8 d16, d16, #7 +0x30,0x07,0xdf,0xf3 = vqshl.u16 d16, d16, #0xf +0x30,0x07,0xff,0xf3 = vqshl.u32 d16, d16, #0x1f +0xb0,0x07,0xff,0xf3 = vqshl.u64 d16, d16, #0x3f +0x30,0x06,0xcf,0xf3 = vqshlu.s8 d16, d16, #7 +0x30,0x06,0xdf,0xf3 = vqshlu.s16 d16, d16, #0xf +0x30,0x06,0xff,0xf3 = vqshlu.s32 d16, d16, #0x1f +0xb0,0x06,0xff,0xf3 = vqshlu.s64 d16, d16, #0x3f +0x70,0x07,0xcf,0xf2 = vqshl.s8 q8, q8, #7 +0x70,0x07,0xdf,0xf2 = vqshl.s16 q8, q8, #0xf +0x70,0x07,0xff,0xf2 = vqshl.s32 q8, q8, #0x1f +0xf0,0x07,0xff,0xf2 = vqshl.s64 q8, q8, #0x3f +0x70,0x07,0xcf,0xf3 = vqshl.u8 q8, q8, #7 +0x70,0x07,0xdf,0xf3 = vqshl.u16 q8, q8, #0xf +0x70,0x07,0xff,0xf3 = vqshl.u32 q8, q8, #0x1f +0xf0,0x07,0xff,0xf3 = vqshl.u64 q8, q8, #0x3f +0x70,0x06,0xcf,0xf3 = vqshlu.s8 q8, q8, #7 +0x70,0x06,0xdf,0xf3 = vqshlu.s16 q8, q8, #0xf +0x70,0x06,0xff,0xf3 = vqshlu.s32 q8, q8, #0x1f +0xf0,0x06,0xff,0xf3 = vqshlu.s64 q8, q8, #0x3f +0xb0,0x05,0x41,0xf2 = vqrshl.s8 d16, d16, d17 +0xb0,0x05,0x51,0xf2 = vqrshl.s16 d16, d16, d17 +0xb0,0x05,0x61,0xf2 = vqrshl.s32 d16, d16, d17 +0xb0,0x05,0x71,0xf2 = vqrshl.s64 d16, d16, d17 +0xb0,0x05,0x41,0xf3 = vqrshl.u8 d16, d16, d17 +0xb0,0x05,0x51,0xf3 = vqrshl.u16 d16, d16, d17 +0xb0,0x05,0x61,0xf3 = vqrshl.u32 d16, d16, d17 +0xb0,0x05,0x71,0xf3 = vqrshl.u64 d16, d16, d17 +0xf0,0x05,0x42,0xf2 = vqrshl.s8 q8, q8, q9 +0xf0,0x05,0x52,0xf2 = vqrshl.s16 q8, q8, q9 +0xf0,0x05,0x62,0xf2 = vqrshl.s32 q8, q8, q9 +0xf0,0x05,0x72,0xf2 = vqrshl.s64 q8, q8, q9 +0xf0,0x05,0x42,0xf3 = vqrshl.u8 q8, q8, q9 +0xf0,0x05,0x52,0xf3 = vqrshl.u16 q8, q8, q9 +0xf0,0x05,0x62,0xf3 = vqrshl.u32 q8, q8, q9 +0xf0,0x05,0x72,0xf3 = vqrshl.u64 q8, q8, q9 +0x30,0x09,0xc8,0xf2 = vqshrn.s16 d16, q8, #8 +0x30,0x09,0xd0,0xf2 = vqshrn.s32 d16, q8, #0x10 +0x30,0x09,0xe0,0xf2 = vqshrn.s64 d16, q8, #0x20 +0x30,0x09,0xc8,0xf3 = vqshrn.u16 d16, q8, #8 +0x30,0x09,0xd0,0xf3 = vqshrn.u32 d16, q8, #0x10 +0x30,0x09,0xe0,0xf3 = vqshrn.u64 d16, q8, #0x20 +0x30,0x08,0xc8,0xf3 = vqshrun.s16 d16, q8, #8 +0x30,0x08,0xd0,0xf3 = vqshrun.s32 d16, q8, #0x10 +0x30,0x08,0xe0,0xf3 = vqshrun.s64 d16, q8, #0x20 +0x70,0x09,0xc8,0xf2 = vqrshrn.s16 d16, q8, #8 +0x70,0x09,0xd0,0xf2 = vqrshrn.s32 d16, q8, #0x10 +0x70,0x09,0xe0,0xf2 = vqrshrn.s64 d16, q8, #0x20 +0x70,0x09,0xc8,0xf3 = vqrshrn.u16 d16, q8, #8 +0x70,0x09,0xd0,0xf3 = vqrshrn.u32 d16, q8, #0x10 +0x70,0x09,0xe0,0xf3 = vqrshrn.u64 d16, q8, #0x20 +0x70,0x08,0xc8,0xf3 = vqrshrun.s16 d16, q8, #8 +0x70,0x08,0xd0,0xf3 = vqrshrun.s32 d16, q8, #0x10 +0x70,0x08,0xe0,0xf3 = vqrshrun.s64 d16, q8, #0x20 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-shift-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-shift-encoding.s.cs new file mode 100644 index 0000000..92383bd --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-shift-encoding.s.cs @@ -0,0 +1,238 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xa1,0x04,0x40,0xf3 = vshl.u8 d16, d17, d16 +0xa1,0x04,0x50,0xf3 = vshl.u16 d16, d17, d16 +0xa1,0x04,0x60,0xf3 = vshl.u32 d16, d17, d16 +0xa1,0x04,0x70,0xf3 = vshl.u64 d16, d17, d16 +0x30,0x05,0xcf,0xf2 = vshl.i8 d16, d16, #7 +0x30,0x05,0xdf,0xf2 = vshl.i16 d16, d16, #0xf +0x30,0x05,0xff,0xf2 = vshl.i32 d16, d16, #0x1f +0xb0,0x05,0xff,0xf2 = vshl.i64 d16, d16, #0x3f +0xe2,0x04,0x40,0xf3 = vshl.u8 q8, q9, q8 +0xe2,0x04,0x50,0xf3 = vshl.u16 q8, q9, q8 +0xe2,0x04,0x60,0xf3 = vshl.u32 q8, q9, q8 +0xe2,0x04,0x70,0xf3 = vshl.u64 q8, q9, q8 +0x70,0x05,0xcf,0xf2 = vshl.i8 q8, q8, #7 +0x70,0x05,0xdf,0xf2 = vshl.i16 q8, q8, #0xf +0x70,0x05,0xff,0xf2 = vshl.i32 q8, q8, #0x1f +0xf0,0x05,0xff,0xf2 = vshl.i64 q8, q8, #0x3f +0x30,0x00,0xc9,0xf3 = vshr.u8 d16, d16, #7 +0x30,0x00,0xd1,0xf3 = vshr.u16 d16, d16, #0xf +0x30,0x00,0xe1,0xf3 = vshr.u32 d16, d16, #0x1f +0xb0,0x00,0xc1,0xf3 = vshr.u64 d16, d16, #0x3f +0x70,0x00,0xc9,0xf3 = vshr.u8 q8, q8, #7 +0x70,0x00,0xd1,0xf3 = vshr.u16 q8, q8, #0xf +0x70,0x00,0xe1,0xf3 = vshr.u32 q8, q8, #0x1f +0xf0,0x00,0xc1,0xf3 = vshr.u64 q8, q8, #0x3f +0x30,0x00,0xc9,0xf2 = vshr.s8 d16, d16, #7 +0x30,0x00,0xd1,0xf2 = vshr.s16 d16, d16, #0xf +0x30,0x00,0xe1,0xf2 = vshr.s32 d16, d16, #0x1f +0xb0,0x00,0xc1,0xf2 = vshr.s64 d16, d16, #0x3f +0x70,0x00,0xc9,0xf2 = vshr.s8 q8, q8, #7 +0x70,0x00,0xd1,0xf2 = vshr.s16 q8, q8, #0xf +0x70,0x00,0xe1,0xf2 = vshr.s32 q8, q8, #0x1f +0xf0,0x00,0xc1,0xf2 = vshr.s64 q8, q8, #0x3f +0x30,0x00,0xc9,0xf3 = vshr.u8 d16, d16, #7 +0x30,0x00,0xd1,0xf3 = vshr.u16 d16, d16, #0xf +0x30,0x00,0xe1,0xf3 = vshr.u32 d16, d16, #0x1f +0xb0,0x00,0xc1,0xf3 = vshr.u64 d16, d16, #0x3f +0x70,0x00,0xc9,0xf3 = vshr.u8 q8, q8, #7 +0x70,0x00,0xd1,0xf3 = vshr.u16 q8, q8, #0xf +0x70,0x00,0xe1,0xf3 = vshr.u32 q8, q8, #0x1f +0xf0,0x00,0xc1,0xf3 = vshr.u64 q8, q8, #0x3f +0x30,0x00,0xc9,0xf2 = vshr.s8 d16, d16, #7 +0x30,0x00,0xd1,0xf2 = vshr.s16 d16, d16, #0xf +0x30,0x00,0xe1,0xf2 = vshr.s32 d16, d16, #0x1f +0xb0,0x00,0xc1,0xf2 = vshr.s64 d16, d16, #0x3f +0x70,0x00,0xc9,0xf2 = vshr.s8 q8, q8, #7 +0x70,0x00,0xd1,0xf2 = vshr.s16 q8, q8, #0xf +0x70,0x00,0xe1,0xf2 = vshr.s32 q8, q8, #0x1f +0xf0,0x00,0xc1,0xf2 = vshr.s64 q8, q8, #0x3f +0x16,0x01,0xc9,0xf2 = vsra.s8 d16, d6, #7 +0x32,0xa1,0xd1,0xf2 = vsra.s16 d26, d18, #0xf +0x1a,0xb1,0xa1,0xf2 = vsra.s32 d11, d10, #0x1f +0xb3,0xc1,0x81,0xf2 = vsra.s64 d12, d19, #0x3f +0x70,0x21,0x89,0xf2 = vsra.s8 q1, q8, #7 +0x5e,0x41,0x91,0xf2 = vsra.s16 q2, q7, #0xf +0x5c,0x61,0xa1,0xf2 = vsra.s32 q3, q6, #0x1f +0xda,0x81,0x81,0xf2 = vsra.s64 q4, q5, #0x3f +0x30,0x01,0xc9,0xf2 = vsra.s8 d16, d16, #7 +0x1f,0xf1,0x91,0xf2 = vsra.s16 d15, d15, #0xf +0x1e,0xe1,0xa1,0xf2 = vsra.s32 d14, d14, #0x1f +0x9d,0xd1,0x81,0xf2 = vsra.s64 d13, d13, #0x3f +0x58,0x81,0x89,0xf2 = vsra.s8 q4, q4, #7 +0x5a,0xa1,0x91,0xf2 = vsra.s16 q5, q5, #0xf +0x5c,0xc1,0xa1,0xf2 = vsra.s32 q6, q6, #0x1f +0xde,0xe1,0x81,0xf2 = vsra.s64 q7, q7, #0x3f +0x16,0x01,0xc9,0xf3 = vsra.u8 d16, d6, #7 +0x32,0xa1,0xd1,0xf3 = vsra.u16 d26, d18, #0xf +0x1a,0xb1,0xa1,0xf3 = vsra.u32 d11, d10, #0x1f +0xb3,0xc1,0x81,0xf3 = vsra.u64 d12, d19, #0x3f +0x70,0x21,0x89,0xf3 = vsra.u8 q1, q8, #7 +0x5e,0x41,0x91,0xf3 = vsra.u16 q2, q7, #0xf +0x5c,0x61,0xa1,0xf3 = vsra.u32 q3, q6, #0x1f +0xda,0x81,0x81,0xf3 = vsra.u64 q4, q5, #0x3f +0x30,0x01,0xc9,0xf3 = vsra.u8 d16, d16, #7 +0x1f,0xf1,0x91,0xf3 = vsra.u16 d15, d15, #0xf +0x1e,0xe1,0xa1,0xf3 = vsra.u32 d14, d14, #0x1f +0x9d,0xd1,0x81,0xf3 = vsra.u64 d13, d13, #0x3f +0x58,0x81,0x89,0xf3 = vsra.u8 q4, q4, #7 +0x5a,0xa1,0x91,0xf3 = vsra.u16 q5, q5, #0xf +0x5c,0xc1,0xa1,0xf3 = vsra.u32 q6, q6, #0x1f +0xde,0xe1,0x81,0xf3 = vsra.u64 q7, q7, #0x3f +0x16,0x04,0xc9,0xf3 = vsri.8 d16, d6, #7 +0x32,0xa4,0xd1,0xf3 = vsri.16 d26, d18, #0xf +0x1a,0xb4,0xa1,0xf3 = vsri.32 d11, d10, #0x1f +0xb3,0xc4,0x81,0xf3 = vsri.64 d12, d19, #0x3f +0x70,0x24,0x89,0xf3 = vsri.8 q1, q8, #7 +0x5e,0x44,0x91,0xf3 = vsri.16 q2, q7, #0xf +0x5c,0x64,0xa1,0xf3 = vsri.32 q3, q6, #0x1f +0xda,0x84,0x81,0xf3 = vsri.64 q4, q5, #0x3f +0x30,0x04,0xc9,0xf3 = vsri.8 d16, d16, #7 +0x1f,0xf4,0x91,0xf3 = vsri.16 d15, d15, #0xf +0x1e,0xe4,0xa1,0xf3 = vsri.32 d14, d14, #0x1f +0x9d,0xd4,0x81,0xf3 = vsri.64 d13, d13, #0x3f +0x58,0x84,0x89,0xf3 = vsri.8 q4, q4, #7 +0x5a,0xa4,0x91,0xf3 = vsri.16 q5, q5, #0xf +0x5c,0xc4,0xa1,0xf3 = vsri.32 q6, q6, #0x1f +0xde,0xe4,0x81,0xf3 = vsri.64 q7, q7, #0x3f +0x16,0x05,0xcf,0xf3 = vsli.8 d16, d6, #7 +0x32,0xa5,0xdf,0xf3 = vsli.16 d26, d18, #0xf +0x1a,0xb5,0xbf,0xf3 = vsli.32 d11, d10, #0x1f +0xb3,0xc5,0xbf,0xf3 = vsli.64 d12, d19, #0x3f +0x70,0x25,0x8f,0xf3 = vsli.8 q1, q8, #7 +0x5e,0x45,0x9f,0xf3 = vsli.16 q2, q7, #0xf +0x5c,0x65,0xbf,0xf3 = vsli.32 q3, q6, #0x1f +0xda,0x85,0xbf,0xf3 = vsli.64 q4, q5, #0x3f +0x30,0x05,0xcf,0xf3 = vsli.8 d16, d16, #7 +0x1f,0xf5,0x9f,0xf3 = vsli.16 d15, d15, #0xf +0x1e,0xe5,0xbf,0xf3 = vsli.32 d14, d14, #0x1f +0x9d,0xd5,0xbf,0xf3 = vsli.64 d13, d13, #0x3f +0x58,0x85,0x8f,0xf3 = vsli.8 q4, q4, #7 +0x5a,0xa5,0x9f,0xf3 = vsli.16 q5, q5, #0xf +0x5c,0xc5,0xbf,0xf3 = vsli.32 q6, q6, #0x1f +0xde,0xe5,0xbf,0xf3 = vsli.64 q7, q7, #0x3f +0x30,0x0a,0xcf,0xf2 = vshll.s8 q8, d16, #7 +0x30,0x0a,0xdf,0xf2 = vshll.s16 q8, d16, #0xf +0x30,0x0a,0xff,0xf2 = vshll.s32 q8, d16, #0x1f +0x30,0x0a,0xcf,0xf3 = vshll.u8 q8, d16, #7 +0x30,0x0a,0xdf,0xf3 = vshll.u16 q8, d16, #0xf +0x30,0x0a,0xff,0xf3 = vshll.u32 q8, d16, #0x1f +0x20,0x03,0xf2,0xf3 = vshll.i8 q8, d16, #8 +0x20,0x03,0xf6,0xf3 = vshll.i16 q8, d16, #0x10 +0x20,0x03,0xfa,0xf3 = vshll.i32 q8, d16, #0x20 +0x30,0x08,0xc8,0xf2 = vshrn.i16 d16, q8, #8 +0x30,0x08,0xd0,0xf2 = vshrn.i32 d16, q8, #0x10 +0x30,0x08,0xe0,0xf2 = vshrn.i64 d16, q8, #0x20 +0xa1,0x05,0x40,0xf2 = vrshl.s8 d16, d17, d16 +0xa1,0x05,0x50,0xf2 = vrshl.s16 d16, d17, d16 +0xa1,0x05,0x60,0xf2 = vrshl.s32 d16, d17, d16 +0xa1,0x05,0x70,0xf2 = vrshl.s64 d16, d17, d16 +0xa1,0x05,0x40,0xf3 = vrshl.u8 d16, d17, d16 +0xa1,0x05,0x50,0xf3 = vrshl.u16 d16, d17, d16 +0xa1,0x05,0x60,0xf3 = vrshl.u32 d16, d17, d16 +0xa1,0x05,0x70,0xf3 = vrshl.u64 d16, d17, d16 +0xe2,0x05,0x40,0xf2 = vrshl.s8 q8, q9, q8 +0xe2,0x05,0x50,0xf2 = vrshl.s16 q8, q9, q8 +0xe2,0x05,0x60,0xf2 = vrshl.s32 q8, q9, q8 +0xe2,0x05,0x70,0xf2 = vrshl.s64 q8, q9, q8 +0xe2,0x05,0x40,0xf3 = vrshl.u8 q8, q9, q8 +0xe2,0x05,0x50,0xf3 = vrshl.u16 q8, q9, q8 +0xe2,0x05,0x60,0xf3 = vrshl.u32 q8, q9, q8 +0xe2,0x05,0x70,0xf3 = vrshl.u64 q8, q9, q8 +0x30,0x02,0xc8,0xf2 = vrshr.s8 d16, d16, #8 +0x30,0x02,0xd0,0xf2 = vrshr.s16 d16, d16, #0x10 +0x30,0x02,0xe0,0xf2 = vrshr.s32 d16, d16, #0x20 +0xb0,0x02,0xc0,0xf2 = vrshr.s64 d16, d16, #0x40 +0x30,0x02,0xc8,0xf3 = vrshr.u8 d16, d16, #8 +0x30,0x02,0xd0,0xf3 = vrshr.u16 d16, d16, #0x10 +0x30,0x02,0xe0,0xf3 = vrshr.u32 d16, d16, #0x20 +0xb0,0x02,0xc0,0xf3 = vrshr.u64 d16, d16, #0x40 +0x70,0x02,0xc8,0xf2 = vrshr.s8 q8, q8, #8 +0x70,0x02,0xd0,0xf2 = vrshr.s16 q8, q8, #0x10 +0x70,0x02,0xe0,0xf2 = vrshr.s32 q8, q8, #0x20 +0xf0,0x02,0xc0,0xf2 = vrshr.s64 q8, q8, #0x40 +0x70,0x02,0xc8,0xf3 = vrshr.u8 q8, q8, #8 +0x70,0x02,0xd0,0xf3 = vrshr.u16 q8, q8, #0x10 +0x70,0x02,0xe0,0xf3 = vrshr.u32 q8, q8, #0x20 +0xf0,0x02,0xc0,0xf3 = vrshr.u64 q8, q8, #0x40 +0x70,0x08,0xc8,0xf2 = vrshrn.i16 d16, q8, #8 +0x70,0x08,0xd0,0xf2 = vrshrn.i32 d16, q8, #0x10 +0x70,0x08,0xe0,0xf2 = vrshrn.i64 d16, q8, #0x20 +0x70,0x09,0xcc,0xf2 = vqrshrn.s16 d16, q8, #4 +0x70,0x09,0xd3,0xf2 = vqrshrn.s32 d16, q8, #0xd +0x70,0x09,0xf3,0xf2 = vqrshrn.s64 d16, q8, #0xd +0x70,0x09,0xcc,0xf3 = vqrshrn.u16 d16, q8, #4 +0x70,0x09,0xd3,0xf3 = vqrshrn.u32 d16, q8, #0xd +0x70,0x09,0xf3,0xf3 = vqrshrn.u64 d16, q8, #0xd +0x48,0x84,0x0a,0xf2 = vshl.s8 q4, q4, q5 +0x48,0x84,0x1a,0xf2 = vshl.s16 q4, q4, q5 +0x48,0x84,0x2a,0xf2 = vshl.s32 q4, q4, q5 +0x48,0x84,0x3a,0xf2 = vshl.s64 q4, q4, q5 +0x48,0x84,0x0a,0xf3 = vshl.u8 q4, q4, q5 +0x48,0x84,0x1a,0xf3 = vshl.u16 q4, q4, q5 +0x48,0x84,0x2a,0xf3 = vshl.u32 q4, q4, q5 +0x48,0x84,0x3a,0xf3 = vshl.u64 q4, q4, q5 +0x04,0x44,0x05,0xf2 = vshl.s8 d4, d4, d5 +0x04,0x44,0x15,0xf2 = vshl.s16 d4, d4, d5 +0x04,0x44,0x25,0xf2 = vshl.s32 d4, d4, d5 +0x04,0x44,0x35,0xf2 = vshl.s64 d4, d4, d5 +0x04,0x44,0x05,0xf3 = vshl.u8 d4, d4, d5 +0x04,0x44,0x15,0xf3 = vshl.u16 d4, d4, d5 +0x04,0x44,0x25,0xf3 = vshl.u32 d4, d4, d5 +0x04,0x44,0x35,0xf3 = vshl.u64 d4, d4, d5 +0x58,0x85,0x8a,0xf2 = vshl.i8 q4, q4, #2 +0x58,0x85,0x9e,0xf2 = vshl.i16 q4, q4, #0xe +0x58,0x85,0xbb,0xf2 = vshl.i32 q4, q4, #0x1b +0xd8,0x85,0xa3,0xf2 = vshl.i64 q4, q4, #0x23 +0x14,0x45,0x8e,0xf2 = vshl.i8 d4, d4, #6 +0x14,0x45,0x9a,0xf2 = vshl.i16 d4, d4, #0xa +0x14,0x45,0xb1,0xf2 = vshl.i32 d4, d4, #0x11 +0x94,0x45,0xab,0xf2 = vshl.i64 d4, d4, #0x2b +0x0b,0xb5,0x04,0xf2 = vrshl.s8 d11, d11, d4 +0x0c,0xc5,0x15,0xf2 = vrshl.s16 d12, d12, d5 +0x0d,0xd5,0x26,0xf2 = vrshl.s32 d13, d13, d6 +0x0e,0xe5,0x37,0xf2 = vrshl.s64 d14, d14, d7 +0x0f,0xf5,0x08,0xf3 = vrshl.u8 d15, d15, d8 +0x20,0x05,0x59,0xf3 = vrshl.u16 d16, d16, d9 +0x21,0x15,0x6a,0xf3 = vrshl.u32 d17, d17, d10 +0x22,0x25,0x7b,0xf3 = vrshl.u64 d18, d18, d11 +0xc2,0x25,0x00,0xf2 = vrshl.s8 q1, q1, q8 +0xc4,0x45,0x1e,0xf2 = vrshl.s16 q2, q2, q15 +0xc6,0x65,0x2c,0xf2 = vrshl.s32 q3, q3, q14 +0xc8,0x85,0x3a,0xf2 = vrshl.s64 q4, q4, q13 +0xca,0xa5,0x08,0xf3 = vrshl.u8 q5, q5, q12 +0xcc,0xc5,0x16,0xf3 = vrshl.u16 q6, q6, q11 +0xce,0xe5,0x24,0xf3 = vrshl.u32 q7, q7, q10 +0xe0,0x05,0x72,0xf3 = vrshl.u64 q8, q8, q9 +0x1f,0xf0,0x88,0xf2 = vshr.s8 d15, d15, #8 +0x1c,0xc0,0x90,0xf2 = vshr.s16 d12, d12, #0x10 +0x1d,0xd0,0xa0,0xf2 = vshr.s32 d13, d13, #0x20 +0x9e,0xe0,0x80,0xf2 = vshr.s64 d14, d14, #0x40 +0x30,0x00,0xc8,0xf3 = vshr.u8 d16, d16, #8 +0x31,0x10,0xd0,0xf3 = vshr.u16 d17, d17, #0x10 +0x16,0x60,0xa0,0xf3 = vshr.u32 d6, d6, #0x20 +0x9a,0xa0,0x80,0xf3 = vshr.u64 d10, d10, #0x40 +0x52,0x20,0x88,0xf2 = vshr.s8 q1, q1, #8 +0x54,0x40,0x90,0xf2 = vshr.s16 q2, q2, #0x10 +0x56,0x60,0xa0,0xf2 = vshr.s32 q3, q3, #0x20 +0xd8,0x80,0x80,0xf2 = vshr.s64 q4, q4, #0x40 +0x5a,0xa0,0x88,0xf3 = vshr.u8 q5, q5, #8 +0x5c,0xc0,0x90,0xf3 = vshr.u16 q6, q6, #0x10 +0x5e,0xe0,0xa0,0xf3 = vshr.u32 q7, q7, #0x20 +0xf0,0x00,0xc0,0xf3 = vshr.u64 q8, q8, #0x40 +0x1f,0xf2,0x88,0xf2 = vrshr.s8 d15, d15, #8 +0x1c,0xc2,0x90,0xf2 = vrshr.s16 d12, d12, #0x10 +0x1d,0xd2,0xa0,0xf2 = vrshr.s32 d13, d13, #0x20 +0x9e,0xe2,0x80,0xf2 = vrshr.s64 d14, d14, #0x40 +0x30,0x02,0xc8,0xf3 = vrshr.u8 d16, d16, #8 +0x31,0x12,0xd0,0xf3 = vrshr.u16 d17, d17, #0x10 +0x16,0x62,0xa0,0xf3 = vrshr.u32 d6, d6, #0x20 +0x9a,0xa2,0x80,0xf3 = vrshr.u64 d10, d10, #0x40 +0x52,0x22,0x88,0xf2 = vrshr.s8 q1, q1, #8 +0x54,0x42,0x90,0xf2 = vrshr.s16 q2, q2, #0x10 +0x56,0x62,0xa0,0xf2 = vrshr.s32 q3, q3, #0x20 +0xd8,0x82,0x80,0xf2 = vrshr.s64 q4, q4, #0x40 +0x5a,0xa2,0x88,0xf3 = vrshr.u8 q5, q5, #8 +0x5c,0xc2,0x90,0xf3 = vrshr.u16 q6, q6, #0x10 +0x5e,0xe2,0xa0,0xf3 = vrshr.u32 q7, q7, #0x20 +0xf0,0x02,0xc0,0xf3 = vrshr.u64 q8, q8, #0x40 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-shiftaccum-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-shiftaccum-encoding.s.cs new file mode 100644 index 0000000..e6d2007 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-shiftaccum-encoding.s.cs @@ -0,0 +1,97 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x30,0x11,0xc8,0xf2 = vsra.s8 d17, d16, #8 +0x1e,0xf1,0x90,0xf2 = vsra.s16 d15, d14, #0x10 +0x1c,0xd1,0xa0,0xf2 = vsra.s32 d13, d12, #0x20 +0x9a,0xb1,0x80,0xf2 = vsra.s64 d11, d10, #0x40 +0x54,0xe1,0x88,0xf2 = vsra.s8 q7, q2, #8 +0x5c,0x61,0x90,0xf2 = vsra.s16 q3, q6, #0x10 +0x5a,0x21,0xe0,0xf2 = vsra.s32 q9, q5, #0x20 +0xd8,0x01,0xc0,0xf2 = vsra.s64 q8, q4, #0x40 +0x30,0x11,0xc8,0xf3 = vsra.u8 d17, d16, #8 +0x1e,0xb1,0x95,0xf3 = vsra.u16 d11, d14, #0xb +0x1f,0xc1,0xaa,0xf3 = vsra.u32 d12, d15, #0x16 +0xb0,0xd1,0x8a,0xf3 = vsra.u64 d13, d16, #0x36 +0x5e,0x21,0x88,0xf3 = vsra.u8 q1, q7, #8 +0x5e,0x41,0x9a,0xf3 = vsra.u16 q2, q7, #6 +0x5c,0x61,0xab,0xf3 = vsra.u32 q3, q6, #0x15 +0xda,0x81,0xa7,0xf3 = vsra.u64 q4, q5, #0x19 +0x30,0x01,0xc8,0xf2 = vsra.s8 d16, d16, #8 +0x1e,0xe1,0x90,0xf2 = vsra.s16 d14, d14, #0x10 +0x1c,0xc1,0xa0,0xf2 = vsra.s32 d12, d12, #0x20 +0x9a,0xa1,0x80,0xf2 = vsra.s64 d10, d10, #0x40 +0x54,0x41,0x88,0xf2 = vsra.s8 q2, q2, #8 +0x5c,0xc1,0x90,0xf2 = vsra.s16 q6, q6, #0x10 +0x5a,0xa1,0xa0,0xf2 = vsra.s32 q5, q5, #0x20 +0xd8,0x81,0x80,0xf2 = vsra.s64 q4, q4, #0x40 +0x30,0x01,0xc8,0xf3 = vsra.u8 d16, d16, #8 +0x1e,0xe1,0x95,0xf3 = vsra.u16 d14, d14, #0xb +0x1f,0xf1,0xaa,0xf3 = vsra.u32 d15, d15, #0x16 +0xb0,0x01,0xca,0xf3 = vsra.u64 d16, d16, #0x36 +0x5e,0xe1,0x88,0xf3 = vsra.u8 q7, q7, #8 +0x5e,0xe1,0x9a,0xf3 = vsra.u16 q7, q7, #6 +0x5c,0xc1,0xab,0xf3 = vsra.u32 q6, q6, #0x15 +0xda,0xa1,0xa7,0xf3 = vsra.u64 q5, q5, #0x19 +0x3a,0x53,0x88,0xf2 = vrsra.s8 d5, d26, #8 +0x39,0x63,0x90,0xf2 = vrsra.s16 d6, d25, #0x10 +0x38,0x73,0xa0,0xf2 = vrsra.s32 d7, d24, #0x20 +0xb7,0xe3,0x80,0xf2 = vrsra.s64 d14, d23, #0x40 +0x36,0xf3,0x88,0xf3 = vrsra.u8 d15, d22, #8 +0x35,0x03,0xd0,0xf3 = vrsra.u16 d16, d21, #0x10 +0x34,0x13,0xe0,0xf3 = vrsra.u32 d17, d20, #0x20 +0xb3,0x23,0xc0,0xf3 = vrsra.u64 d18, d19, #0x40 +0x54,0x23,0x88,0xf2 = vrsra.s8 q1, q2, #8 +0x56,0x43,0x90,0xf2 = vrsra.s16 q2, q3, #0x10 +0x58,0x63,0xa0,0xf2 = vrsra.s32 q3, q4, #0x20 +0xda,0x83,0x80,0xf2 = vrsra.s64 q4, q5, #0x40 +0x5c,0xa3,0x88,0xf3 = vrsra.u8 q5, q6, #8 +0x5e,0xc3,0x90,0xf3 = vrsra.u16 q6, q7, #0x10 +0x70,0xe3,0xa0,0xf3 = vrsra.u32 q7, q8, #0x20 +0xf2,0x03,0xc0,0xf3 = vrsra.u64 q8, q9, #0x40 +0x3a,0xa3,0xc8,0xf2 = vrsra.s8 d26, d26, #8 +0x39,0x93,0xd0,0xf2 = vrsra.s16 d25, d25, #0x10 +0x38,0x83,0xe0,0xf2 = vrsra.s32 d24, d24, #0x20 +0xb7,0x73,0xc0,0xf2 = vrsra.s64 d23, d23, #0x40 +0x36,0x63,0xc8,0xf3 = vrsra.u8 d22, d22, #8 +0x35,0x53,0xd0,0xf3 = vrsra.u16 d21, d21, #0x10 +0x34,0x43,0xe0,0xf3 = vrsra.u32 d20, d20, #0x20 +0xb3,0x33,0xc0,0xf3 = vrsra.u64 d19, d19, #0x40 +0x54,0x43,0x88,0xf2 = vrsra.s8 q2, q2, #8 +0x56,0x63,0x90,0xf2 = vrsra.s16 q3, q3, #0x10 +0x58,0x83,0xa0,0xf2 = vrsra.s32 q4, q4, #0x20 +0xda,0xa3,0x80,0xf2 = vrsra.s64 q5, q5, #0x40 +0x5c,0xc3,0x88,0xf3 = vrsra.u8 q6, q6, #8 +0x5e,0xe3,0x90,0xf3 = vrsra.u16 q7, q7, #0x10 +0x70,0x03,0xe0,0xf3 = vrsra.u32 q8, q8, #0x20 +0xf2,0x23,0xc0,0xf3 = vrsra.u64 q9, q9, #0x40 +0x1c,0xb5,0x8f,0xf3 = vsli.8 d11, d12, #7 +0x1d,0xc5,0x9f,0xf3 = vsli.16 d12, d13, #0xf +0x1e,0xd5,0xbf,0xf3 = vsli.32 d13, d14, #0x1f +0x9f,0xe5,0xbf,0xf3 = vsli.64 d14, d15, #0x3f +0x70,0x25,0x8f,0xf3 = vsli.8 q1, q8, #7 +0x5e,0x45,0x9f,0xf3 = vsli.16 q2, q7, #0xf +0x58,0x65,0xbf,0xf3 = vsli.32 q3, q4, #0x1f +0xda,0x85,0xbf,0xf3 = vsli.64 q4, q5, #0x3f +0x1b,0xc4,0xc8,0xf3 = vsri.8 d28, d11, #8 +0x1c,0xa4,0xd0,0xf3 = vsri.16 d26, d12, #0x10 +0x1d,0x84,0xe0,0xf3 = vsri.32 d24, d13, #0x20 +0x9e,0x54,0xc0,0xf3 = vsri.64 d21, d14, #0x40 +0x70,0x24,0x88,0xf3 = vsri.8 q1, q8, #8 +0x54,0xa4,0x90,0xf3 = vsri.16 q5, q2, #0x10 +0x58,0xe4,0xa0,0xf3 = vsri.32 q7, q4, #0x20 +0xdc,0x24,0xc0,0xf3 = vsri.64 q9, q6, #0x40 +0x1c,0xc5,0x8f,0xf3 = vsli.8 d12, d12, #7 +0x1d,0xd5,0x9f,0xf3 = vsli.16 d13, d13, #0xf +0x1e,0xe5,0xbf,0xf3 = vsli.32 d14, d14, #0x1f +0x9f,0xf5,0xbf,0xf3 = vsli.64 d15, d15, #0x3f +0x70,0x05,0xcf,0xf3 = vsli.8 q8, q8, #7 +0x5e,0xe5,0x9f,0xf3 = vsli.16 q7, q7, #0xf +0x58,0x85,0xbf,0xf3 = vsli.32 q4, q4, #0x1f +0xda,0xa5,0xbf,0xf3 = vsli.64 q5, q5, #0x3f +0x1b,0xb4,0x88,0xf3 = vsri.8 d11, d11, #8 +0x1c,0xc4,0x90,0xf3 = vsri.16 d12, d12, #0x10 +0x1d,0xd4,0xa0,0xf3 = vsri.32 d13, d13, #0x20 +0x9e,0xe4,0x80,0xf3 = vsri.64 d14, d14, #0x40 +0x70,0x04,0xc8,0xf3 = vsri.8 q8, q8, #8 +0x54,0x44,0x90,0xf3 = vsri.16 q2, q2, #0x10 +0x58,0x84,0xa0,0xf3 = vsri.32 q4, q4, #0x20 +0xdc,0xc4,0x80,0xf3 = vsri.64 q6, q6, #0x40 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-shuffle-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-shuffle-encoding.s.cs new file mode 100644 index 0000000..b82d67d --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-shuffle-encoding.s.cs @@ -0,0 +1,59 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xa0,0x03,0xf1,0xf2 = vext.8 d16, d17, d16, #3 +0xa0,0x05,0xf1,0xf2 = vext.8 d16, d17, d16, #5 +0xe0,0x03,0xf2,0xf2 = vext.8 q8, q9, q8, #3 +0xe0,0x07,0xf2,0xf2 = vext.8 q8, q9, q8, #7 +0xa0,0x06,0xf1,0xf2 = vext.16 d16, d17, d16, #3 +0xe0,0x0c,0xf2,0xf2 = vext.32 q8, q9, q8, #3 +0xe0,0x08,0xf2,0xf2 = vext.64 q8, q9, q8, #1 +0xa0,0x13,0xf1,0xf2 = vext.8 d17, d17, d16, #3 +0x0b,0x75,0xb7,0xf2 = vext.8 d7, d7, d11, #5 +0x60,0x63,0xb6,0xf2 = vext.8 q3, q3, q8, #3 +0xc8,0x27,0xf2,0xf2 = vext.8 q9, q9, q4, #7 +0x2a,0x16,0xb1,0xf2 = vext.16 d1, d1, d26, #3 +0x60,0xac,0xba,0xf2 = vext.32 q5, q5, q8, #3 +0x60,0xa8,0xba,0xf2 = vext.64 q5, q5, q8, #1 +0xa0,0x10,0xf2,0xf3 = vtrn.8 d17, d16 +0xa0,0x10,0xf6,0xf3 = vtrn.16 d17, d16 +0xa0,0x10,0xfa,0xf3 = vtrn.32 d17, d16 +0xe0,0x20,0xf2,0xf3 = vtrn.8 q9, q8 +0xe0,0x20,0xf6,0xf3 = vtrn.16 q9, q8 +0xe0,0x20,0xfa,0xf3 = vtrn.32 q9, q8 +0x20,0x11,0xf2,0xf3 = vuzp.8 d17, d16 +0x20,0x11,0xf6,0xf3 = vuzp.16 d17, d16 +0x60,0x21,0xf2,0xf3 = vuzp.8 q9, q8 +0x60,0x21,0xf6,0xf3 = vuzp.16 q9, q8 +0x60,0x21,0xfa,0xf3 = vuzp.32 q9, q8 +0xa0,0x11,0xf2,0xf3 = vzip.8 d17, d16 +0xa0,0x11,0xf6,0xf3 = vzip.16 d17, d16 +0xe0,0x21,0xf2,0xf3 = vzip.8 q9, q8 +0xe0,0x21,0xf6,0xf3 = vzip.16 q9, q8 +0xe0,0x21,0xfa,0xf3 = vzip.32 q9, q8 +0x83,0x20,0xba,0xf3 = vtrn.32 d2, d3 +0x83,0x20,0xba,0xf3 = vtrn.32 d2, d3 +0x89,0x30,0xb2,0xf3 = vtrn.8 d3, d9 +0x89,0x30,0xb2,0xf3 = vtrn.8 d3, d9 +0x89,0x30,0xb2,0xf3 = vtrn.8 d3, d9 +0x89,0x30,0xb2,0xf3 = vtrn.8 d3, d9 +0x89,0x30,0xb6,0xf3 = vtrn.16 d3, d9 +0x89,0x30,0xb6,0xf3 = vtrn.16 d3, d9 +0x89,0x30,0xb6,0xf3 = vtrn.16 d3, d9 +0x89,0x30,0xb6,0xf3 = vtrn.16 d3, d9 +0x89,0x30,0xba,0xf3 = vtrn.32 d3, d9 +0x89,0x30,0xba,0xf3 = vtrn.32 d3, d9 +0x89,0x30,0xba,0xf3 = vtrn.32 d3, d9 +0x89,0x30,0xba,0xf3 = vtrn.32 d3, d9 +0x89,0x30,0xba,0xf3 = vtrn.32 d3, d9 +0xcc,0xc0,0xf2,0xf3 = vtrn.8 q14, q6 +0xcc,0xc0,0xf2,0xf3 = vtrn.8 q14, q6 +0xcc,0xc0,0xf2,0xf3 = vtrn.8 q14, q6 +0xcc,0xc0,0xf2,0xf3 = vtrn.8 q14, q6 +0xcc,0xc0,0xf6,0xf3 = vtrn.16 q14, q6 +0xcc,0xc0,0xf6,0xf3 = vtrn.16 q14, q6 +0xcc,0xc0,0xf6,0xf3 = vtrn.16 q14, q6 +0xcc,0xc0,0xf6,0xf3 = vtrn.16 q14, q6 +0xcc,0xc0,0xfa,0xf3 = vtrn.32 q14, q6 +0xcc,0xc0,0xfa,0xf3 = vtrn.32 q14, q6 +0xcc,0xc0,0xfa,0xf3 = vtrn.32 q14, q6 +0xcc,0xc0,0xfa,0xf3 = vtrn.32 q14, q6 +0xcc,0xc0,0xfa,0xf3 = vtrn.32 q14, q6 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-sub-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-sub-encoding.s.cs new file mode 100644 index 0000000..2d9a223 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-sub-encoding.s.cs @@ -0,0 +1,82 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xa0,0x08,0x41,0xf3 = vsub.i8 d16, d17, d16 +0xa0,0x08,0x51,0xf3 = vsub.i16 d16, d17, d16 +0xa0,0x08,0x61,0xf3 = vsub.i32 d16, d17, d16 +0xa0,0x08,0x71,0xf3 = vsub.i64 d16, d17, d16 +0xa1,0x0d,0x60,0xf2 = vsub.f32 d16, d16, d17 +0xe2,0x08,0x40,0xf3 = vsub.i8 q8, q8, q9 +0xe2,0x08,0x50,0xf3 = vsub.i16 q8, q8, q9 +0xe2,0x08,0x60,0xf3 = vsub.i32 q8, q8, q9 +0xe2,0x08,0x70,0xf3 = vsub.i64 q8, q8, q9 +0xe2,0x0d,0x60,0xf2 = vsub.f32 q8, q8, q9 +0x25,0xd8,0x0d,0xf3 = vsub.i8 d13, d13, d21 +0x26,0xe8,0x1e,0xf3 = vsub.i16 d14, d14, d22 +0x27,0xf8,0x2f,0xf3 = vsub.i32 d15, d15, d23 +0xa8,0x08,0x70,0xf3 = vsub.i64 d16, d16, d24 +0xa9,0x1d,0x61,0xf2 = vsub.f32 d17, d17, d25 +0x64,0x28,0x02,0xf3 = vsub.i8 q1, q1, q10 +0x62,0x48,0x14,0xf3 = vsub.i16 q2, q2, q9 +0x60,0x68,0x26,0xf3 = vsub.i32 q3, q3, q8 +0x4e,0x88,0x38,0xf3 = vsub.i64 q4, q4, q7 +0x4c,0xad,0x2a,0xf2 = vsub.f32 q5, q5, q6 +0xa0,0x02,0xc1,0xf2 = vsubl.s8 q8, d17, d16 +0xa0,0x02,0xd1,0xf2 = vsubl.s16 q8, d17, d16 +0xa0,0x02,0xe1,0xf2 = vsubl.s32 q8, d17, d16 +0xa0,0x02,0xc1,0xf3 = vsubl.u8 q8, d17, d16 +0xa0,0x02,0xd1,0xf3 = vsubl.u16 q8, d17, d16 +0xa0,0x02,0xe1,0xf3 = vsubl.u32 q8, d17, d16 +0xa2,0x03,0xc0,0xf2 = vsubw.s8 q8, q8, d18 +0xa2,0x03,0xd0,0xf2 = vsubw.s16 q8, q8, d18 +0xa2,0x03,0xe0,0xf2 = vsubw.s32 q8, q8, d18 +0xa2,0x03,0xc0,0xf3 = vsubw.u8 q8, q8, d18 +0xa2,0x03,0xd0,0xf3 = vsubw.u16 q8, q8, d18 +0xa2,0x03,0xe0,0xf3 = vsubw.u32 q8, q8, d18 +0xa1,0x02,0x40,0xf2 = vhsub.s8 d16, d16, d17 +0xa1,0x02,0x50,0xf2 = vhsub.s16 d16, d16, d17 +0xa1,0x02,0x60,0xf2 = vhsub.s32 d16, d16, d17 +0xa1,0x02,0x40,0xf3 = vhsub.u8 d16, d16, d17 +0xa1,0x02,0x50,0xf3 = vhsub.u16 d16, d16, d17 +0xa1,0x02,0x60,0xf3 = vhsub.u32 d16, d16, d17 +0xe2,0x02,0x40,0xf2 = vhsub.s8 q8, q8, q9 +0xe2,0x02,0x50,0xf2 = vhsub.s16 q8, q8, q9 +0xe2,0x02,0x60,0xf2 = vhsub.s32 q8, q8, q9 +0xb1,0x02,0x40,0xf2 = vqsub.s8 d16, d16, d17 +0xb1,0x02,0x50,0xf2 = vqsub.s16 d16, d16, d17 +0xb1,0x02,0x60,0xf2 = vqsub.s32 d16, d16, d17 +0xb1,0x02,0x70,0xf2 = vqsub.s64 d16, d16, d17 +0xb1,0x02,0x40,0xf3 = vqsub.u8 d16, d16, d17 +0xb1,0x02,0x50,0xf3 = vqsub.u16 d16, d16, d17 +0xb1,0x02,0x60,0xf3 = vqsub.u32 d16, d16, d17 +0xb1,0x02,0x70,0xf3 = vqsub.u64 d16, d16, d17 +0xf2,0x02,0x40,0xf2 = vqsub.s8 q8, q8, q9 +0xf2,0x02,0x50,0xf2 = vqsub.s16 q8, q8, q9 +0xf2,0x02,0x60,0xf2 = vqsub.s32 q8, q8, q9 +0xf2,0x02,0x70,0xf2 = vqsub.s64 q8, q8, q9 +0xf2,0x02,0x40,0xf3 = vqsub.u8 q8, q8, q9 +0xf2,0x02,0x50,0xf3 = vqsub.u16 q8, q8, q9 +0xf2,0x02,0x60,0xf3 = vqsub.u32 q8, q8, q9 +0xf2,0x02,0x70,0xf3 = vqsub.u64 q8, q8, q9 +0xa2,0x06,0xc0,0xf2 = vsubhn.i16 d16, q8, q9 +0xa2,0x06,0xd0,0xf2 = vsubhn.i32 d16, q8, q9 +0xa2,0x06,0xe0,0xf2 = vsubhn.i64 d16, q8, q9 +0xa2,0x06,0xc0,0xf3 = vrsubhn.i16 d16, q8, q9 +0xa2,0x06,0xd0,0xf3 = vrsubhn.i32 d16, q8, q9 +0xa2,0x06,0xe0,0xf3 = vrsubhn.i64 d16, q8, q9 +0x28,0xb2,0x0b,0xf2 = vhsub.s8 d11, d11, d24 +0x27,0xc2,0x1c,0xf2 = vhsub.s16 d12, d12, d23 +0x26,0xd2,0x2d,0xf2 = vhsub.s32 d13, d13, d22 +0x25,0xe2,0x0e,0xf3 = vhsub.u8 d14, d14, d21 +0x24,0xf2,0x1f,0xf3 = vhsub.u16 d15, d15, d20 +0xa3,0x02,0x60,0xf3 = vhsub.u32 d16, d16, d19 +0x68,0x22,0x02,0xf2 = vhsub.s8 q1, q1, q12 +0x66,0x42,0x14,0xf2 = vhsub.s16 q2, q2, q11 +0x64,0x62,0x26,0xf2 = vhsub.s32 q3, q3, q10 +0x62,0x82,0x08,0xf3 = vhsub.u8 q4, q4, q9 +0x60,0xa2,0x1a,0xf3 = vhsub.u16 q5, q5, q8 +0x4e,0xc2,0x2c,0xf3 = vhsub.u32 q6, q6, q7 +0x05,0xc3,0x8c,0xf2 = vsubw.s8 q6, q6, d5 +0x01,0xe3,0x9e,0xf2 = vsubw.s16 q7, q7, d1 +0x82,0x03,0xe0,0xf2 = vsubw.s32 q8, q8, d2 +0x05,0xc3,0x8c,0xf3 = vsubw.u8 q6, q6, d5 +0x01,0xe3,0x9e,0xf3 = vsubw.u16 q7, q7, d1 +0x82,0x03,0xe0,0xf3 = vsubw.u32 q8, q8, d2 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-table-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-table-encoding.s.cs new file mode 100644 index 0000000..4b7d73d --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-table-encoding.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xa0,0x08,0xf1,0xf3 = vtbl.8 d16, {d17}, d16 +0xa2,0x09,0xf0,0xf3 = vtbl.8 d16, {d16, d17}, d18 +0xa4,0x0a,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18}, d20 +0xa4,0x0b,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18, d19}, d20 +0xe1,0x28,0xf0,0xf3 = vtbx.8 d18, {d16}, d17 +0xe2,0x39,0xf0,0xf3 = vtbx.8 d19, {d16, d17}, d18 +0xe5,0x4a,0xf0,0xf3 = vtbx.8 d20, {d16, d17, d18}, d21 +0xe5,0x4b,0xf0,0xf3 = vtbx.8 d20, {d16, d17, d18, d19}, d21 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-v8.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-v8.s.cs new file mode 100644 index 0000000..a3447e0 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-v8.s.cs @@ -0,0 +1,38 @@ +# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None +0x11,0x4f,0x05,0xf3 = vmaxnm.f32 d4, d5, d1 +0x5c,0x4f,0x08,0xf3 = vmaxnm.f32 q2, q4, q6 +0x3e,0x5f,0x24,0xf3 = vminnm.f32 d5, d4, d30 +0xd4,0x0f,0x2a,0xf3 = vminnm.f32 q0, q13, q2 +0x06,0x40,0xbb,0xf3 = vcvta.s32.f32 d4, d6 +0x8a,0xc0,0xbb,0xf3 = vcvta.u32.f32 d12, d10 +0x4c,0x80,0xbb,0xf3 = vcvta.s32.f32 q4, q6 +0xe4,0x80,0xbb,0xf3 = vcvta.u32.f32 q4, q10 +0x2e,0x13,0xbb,0xf3 = vcvtm.s32.f32 d1, d30 +0x8a,0xc3,0xbb,0xf3 = vcvtm.u32.f32 d12, d10 +0x64,0x23,0xbb,0xf3 = vcvtm.s32.f32 q1, q10 +0xc2,0xa3,0xfb,0xf3 = vcvtm.u32.f32 q13, q1 +0x21,0xf1,0xbb,0xf3 = vcvtn.s32.f32 d15, d17 +0x83,0x51,0xbb,0xf3 = vcvtn.u32.f32 d5, d3 +0x60,0x61,0xbb,0xf3 = vcvtn.s32.f32 q3, q8 +0xc6,0xa1,0xbb,0xf3 = vcvtn.u32.f32 q5, q3 +0x25,0xb2,0xbb,0xf3 = vcvtp.s32.f32 d11, d21 +0xa7,0xe2,0xbb,0xf3 = vcvtp.u32.f32 d14, d23 +0x6e,0x82,0xbb,0xf3 = vcvtp.s32.f32 q4, q15 +0xe0,0x22,0xfb,0xf3 = vcvtp.u32.f32 q9, q8 +0x00,0x34,0xba,0xf3 = vrintn.f32 d3, d0 +0x48,0x24,0xba,0xf3 = vrintn.f32 q1, q4 +0x8c,0x54,0xba,0xf3 = vrintx.f32 d5, d12 +0xc6,0x04,0xba,0xf3 = vrintx.f32 q0, q3 +0x00,0x35,0xba,0xf3 = vrinta.f32 d3, d0 +0x44,0x05,0xfa,0xf3 = vrinta.f32 q8, q2 +0xa2,0xc5,0xba,0xf3 = vrintz.f32 d12, d18 +0xc8,0x25,0xfa,0xf3 = vrintz.f32 q9, q4 +0x80,0x36,0xba,0xf3 = vrintm.f32 d3, d0 +0xc8,0x26,0xba,0xf3 = vrintm.f32 q1, q4 +0x80,0x37,0xba,0xf3 = vrintp.f32 d3, d0 +0xc8,0x27,0xba,0xf3 = vrintp.f32 q1, q4 +0x00,0x34,0xba,0xf3 = vrintn.f32 d3, d0 +0xc6,0x04,0xba,0xf3 = vrintx.f32 q0, q3 +0x00,0x35,0xba,0xf3 = vrinta.f32 d3, d0 +0xc8,0x25,0xfa,0xf3 = vrintz.f32 q9, q4 +0xc8,0x27,0xba,0xf3 = vrintp.f32 q1, q4 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-vld-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-vld-encoding.s.cs new file mode 100644 index 0000000..38a9380 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-vld-encoding.s.cs @@ -0,0 +1,213 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x1f,0x07,0x60,0xf4 = vld1.8 {d16}, [r0:64] +0x4f,0x07,0x60,0xf4 = vld1.16 {d16}, [r0] +0x8f,0x07,0x60,0xf4 = vld1.32 {d16}, [r0] +0xcf,0x07,0x60,0xf4 = vld1.64 {d16}, [r0] +0x1f,0x0a,0x60,0xf4 = vld1.8 {d16, d17}, [r0:64] +0x6f,0x0a,0x60,0xf4 = vld1.16 {d16, d17}, [r0:128] +0x8f,0x0a,0x60,0xf4 = vld1.32 {d16, d17}, [r0] +0xcf,0x0a,0x60,0xf4 = vld1.64 {d16, d17}, [r0] +0x0f,0x16,0x23,0xf4 = vld1.8 {d1, d2, d3}, [r3] +0x5f,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64] +0x8f,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3] +0xdf,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64] +0x0f,0x12,0x23,0xf4 = vld1.8 {d1, d2, d3, d4}, [r3] +0x5f,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64] +0x8f,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3] +0xdf,0x62,0x23,0xf4 = vld1.64 {d6, d7, d8, d9}, [r3:64] +0x1d,0x07,0x60,0xf4 = vld1.8 {d16}, [r0:64]! +0x4d,0x07,0x60,0xf4 = vld1.16 {d16}, [r0]! +0x8d,0x07,0x60,0xf4 = vld1.32 {d16}, [r0]! +0xcd,0x07,0x60,0xf4 = vld1.64 {d16}, [r0]! +0x1d,0x0a,0x60,0xf4 = vld1.8 {d16, d17}, [r0:64]! +0x6d,0x0a,0x60,0xf4 = vld1.16 {d16, d17}, [r0:128]! +0x8d,0x0a,0x60,0xf4 = vld1.32 {d16, d17}, [r0]! +0xcd,0x0a,0x60,0xf4 = vld1.64 {d16, d17}, [r0]! +0x15,0x07,0x60,0xf4 = vld1.8 {d16}, [r0:64], r5 +0x45,0x07,0x60,0xf4 = vld1.16 {d16}, [r0], r5 +0x85,0x07,0x60,0xf4 = vld1.32 {d16}, [r0], r5 +0xc5,0x07,0x60,0xf4 = vld1.64 {d16}, [r0], r5 +0x15,0x0a,0x60,0xf4 = vld1.8 {d16, d17}, [r0:64], r5 +0x65,0x0a,0x60,0xf4 = vld1.16 {d16, d17}, [r0:128], r5 +0x85,0x0a,0x60,0xf4 = vld1.32 {d16, d17}, [r0], r5 +0xc5,0x0a,0x60,0xf4 = vld1.64 {d16, d17}, [r0], r5 +0x0d,0x16,0x23,0xf4 = vld1.8 {d1, d2, d3}, [r3]! +0x5d,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64]! +0x8d,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3]! +0xdd,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64]! +0x06,0x16,0x23,0xf4 = vld1.8 {d1, d2, d3}, [r3], r6 +0x56,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64], r6 +0x86,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3], r6 +0xd6,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64], r6 +0x0d,0x12,0x23,0xf4 = vld1.8 {d1, d2, d3, d4}, [r3]! +0x5d,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64]! +0x8d,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3]! +0xdd,0x62,0x23,0xf4 = vld1.64 {d6, d7, d8, d9}, [r3:64]! +0x08,0x12,0x23,0xf4 = vld1.8 {d1, d2, d3, d4}, [r3], r8 +0x58,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64], r8 +0x88,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3], r8 +0xd8,0x62,0x23,0xf4 = vld1.64 {d6, d7, d8, d9}, [r3:64], r8 +0x1f,0x08,0x60,0xf4 = vld2.8 {d16, d17}, [r0:64] +0x6f,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128] +0x8f,0x08,0x60,0xf4 = vld2.32 {d16, d17}, [r0] +0x1f,0x03,0x60,0xf4 = vld2.8 {d16, d17, d18, d19}, [r0:64] +0x6f,0x03,0x60,0xf4 = vld2.16 {d16, d17, d18, d19}, [r0:128] +0xbf,0x03,0x60,0xf4 = vld2.32 {d16, d17, d18, d19}, [r0:256] +0x1d,0x38,0x60,0xf4 = vld2.8 {d19, d20}, [r0:64]! +0x6d,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128]! +0x8d,0x48,0x60,0xf4 = vld2.32 {d20, d21}, [r0]! +0x1d,0x43,0x20,0xf4 = vld2.8 {d4, d5, d6, d7}, [r0:64]! +0x6d,0x13,0x20,0xf4 = vld2.16 {d1, d2, d3, d4}, [r0:128]! +0xbd,0xe3,0x20,0xf4 = vld2.32 {d14, d15, d16, d17}, [r0:256]! +0x16,0x38,0x60,0xf4 = vld2.8 {d19, d20}, [r0:64], r6 +0x66,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128], r6 +0x86,0x48,0x60,0xf4 = vld2.32 {d20, d21}, [r0], r6 +0x16,0x43,0x20,0xf4 = vld2.8 {d4, d5, d6, d7}, [r0:64], r6 +0x66,0x13,0x20,0xf4 = vld2.16 {d1, d2, d3, d4}, [r0:128], r6 +0xb6,0xe3,0x20,0xf4 = vld2.32 {d14, d15, d16, d17}, [r0:256], r6 +0x0f,0x04,0x61,0xf4 = vld3.8 {d16, d17, d18}, [r1] +0x4f,0x64,0x22,0xf4 = vld3.16 {d6, d7, d8}, [r2] +0x8f,0x14,0x23,0xf4 = vld3.32 {d1, d2, d3}, [r3] +0x1f,0x05,0x60,0xf4 = vld3.8 {d16, d18, d20}, [r0:64] +0x4f,0xb5,0x64,0xf4 = vld3.16 {d27, d29, d31}, [r4] +0x8f,0x65,0x25,0xf4 = vld3.32 {d6, d8, d10}, [r5] +0x01,0xc4,0x26,0xf4 = vld3.8 {d12, d13, d14}, [r6], r1 +0x42,0xb4,0x27,0xf4 = vld3.16 {d11, d12, d13}, [r7], r2 +0x83,0x24,0x28,0xf4 = vld3.32 {d2, d3, d4}, [r8], r3 +0x04,0x45,0x29,0xf4 = vld3.8 {d4, d6, d8}, [r9], r4 +0x44,0xe5,0x29,0xf4 = vld3.16 {d14, d16, d18}, [r9], r4 +0x85,0x05,0x6a,0xf4 = vld3.32 {d16, d18, d20}, [r10], r5 +0x0d,0x64,0x28,0xf4 = vld3.8 {d6, d7, d8}, [r8]! +0x4d,0x94,0x27,0xf4 = vld3.16 {d9, d10, d11}, [r7]! +0x8d,0x14,0x26,0xf4 = vld3.32 {d1, d2, d3}, [r6]! +0x1d,0x05,0x60,0xf4 = vld3.8 {d16, d18, d20}, [r0:64]! +0x4d,0x45,0x65,0xf4 = vld3.16 {d20, d22, d24}, [r5]! +0x8d,0x55,0x24,0xf4 = vld3.32 {d5, d7, d9}, [r4]! +0x1f,0x00,0x61,0xf4 = vld4.8 {d16, d17, d18, d19}, [r1:64] +0x6f,0x00,0x62,0xf4 = vld4.16 {d16, d17, d18, d19}, [r2:128] +0xbf,0x00,0x63,0xf4 = vld4.32 {d16, d17, d18, d19}, [r3:256] +0x3f,0x11,0x65,0xf4 = vld4.8 {d17, d19, d21, d23}, [r5:256] +0x4f,0x11,0x67,0xf4 = vld4.16 {d17, d19, d21, d23}, [r7] +0x8f,0x01,0x68,0xf4 = vld4.32 {d16, d18, d20, d22}, [r8] +0x1d,0x00,0x61,0xf4 = vld4.8 {d16, d17, d18, d19}, [r1:64]! +0x6d,0x00,0x62,0xf4 = vld4.16 {d16, d17, d18, d19}, [r2:128]! +0xbd,0x00,0x63,0xf4 = vld4.32 {d16, d17, d18, d19}, [r3:256]! +0x3d,0x11,0x65,0xf4 = vld4.8 {d17, d19, d21, d23}, [r5:256]! +0x4d,0x11,0x67,0xf4 = vld4.16 {d17, d19, d21, d23}, [r7]! +0x8d,0x01,0x68,0xf4 = vld4.32 {d16, d18, d20, d22}, [r8]! +0x18,0x00,0x61,0xf4 = vld4.8 {d16, d17, d18, d19}, [r1:64], r8 +0x47,0x00,0x62,0xf4 = vld4.16 {d16, d17, d18, d19}, [r2], r7 +0x95,0x00,0x63,0xf4 = vld4.32 {d16, d17, d18, d19}, [r3:64], r5 +0x32,0x01,0x64,0xf4 = vld4.8 {d16, d18, d20, d22}, [r4:256], r2 +0x43,0x01,0x66,0xf4 = vld4.16 {d16, d18, d20, d22}, [r6], r3 +0x84,0x11,0x69,0xf4 = vld4.32 {d17, d19, d21, d23}, [r9], r4 +0x0f,0x4c,0xa1,0xf4 = vld1.8 {d4[]}, [r1] +0x0d,0x4c,0xa1,0xf4 = vld1.8 {d4[]}, [r1]! +0x03,0x4c,0xa1,0xf4 = vld1.8 {d4[]}, [r1], r3 +0x2f,0x4c,0xa1,0xf4 = vld1.8 {d4[], d5[]}, [r1] +0x2d,0x4c,0xa1,0xf4 = vld1.8 {d4[], d5[]}, [r1]! +0x23,0x4c,0xa1,0xf4 = vld1.8 {d4[], d5[]}, [r1], r3 +0x6f,0x00,0xe0,0xf4 = vld1.8 {d16[3]}, [r0] +0x9f,0x04,0xe0,0xf4 = vld1.16 {d16[2]}, [r0:16] +0xbf,0x08,0xe0,0xf4 = vld1.32 {d16[1]}, [r0:32] +0xcd,0xc0,0xa2,0xf4 = vld1.8 {d12[6]}, [r2]! +0xc2,0xc0,0xa2,0xf4 = vld1.8 {d12[6]}, [r2], r2 +0xcd,0xc4,0xa2,0xf4 = vld1.16 {d12[3]}, [r2]! +0x82,0xc4,0xa2,0xf4 = vld1.16 {d12[2]}, [r2], r2 +0x3f,0x01,0xe0,0xf4 = vld2.8 {d16[1], d17[1]}, [r0:16] +0x5f,0x05,0xe0,0xf4 = vld2.16 {d16[1], d17[1]}, [r0:32] +0x8f,0x09,0xe0,0xf4 = vld2.32 {d16[1], d17[1]}, [r0] +0x6f,0x15,0xe0,0xf4 = vld2.16 {d17[1], d19[1]}, [r0] +0x5f,0x19,0xe0,0xf4 = vld2.32 {d17[0], d19[0]}, [r0:64] +0x5d,0x19,0xe0,0xf4 = vld2.32 {d17[0], d19[0]}, [r0:64]! +0x83,0x21,0xa2,0xf4 = vld2.8 {d2[4], d3[4]}, [r2], r3 +0x8d,0x21,0xa2,0xf4 = vld2.8 {d2[4], d3[4]}, [r2]! +0x8f,0x21,0xa2,0xf4 = vld2.8 {d2[4], d3[4]}, [r2] +0x8f,0x6d,0xe1,0xf4 = vld2.32 {d22[], d23[]}, [r1] +0xaf,0x6d,0xe1,0xf4 = vld2.32 {d22[], d24[]}, [r1] +0x8d,0xad,0xa3,0xf4 = vld2.32 {d10[], d11[]}, [r3]! +0xad,0xed,0xa4,0xf4 = vld2.32 {d14[], d16[]}, [r4]! +0x84,0x6d,0xe5,0xf4 = vld2.32 {d22[], d23[]}, [r5], r4 +0xa4,0x6d,0xe6,0xf4 = vld2.32 {d22[], d24[]}, [r6], r4 +0x2f,0x02,0xe1,0xf4 = vld3.8 {d16[1], d17[1], d18[1]}, [r1] +0x4f,0x66,0xa2,0xf4 = vld3.16 {d6[1], d7[1], d8[1]}, [r2] +0x8f,0x1a,0xa3,0xf4 = vld3.32 {d1[1], d2[1], d3[1]}, [r3] +0xaf,0xb6,0xe4,0xf4 = vld3.16 {d27[2], d29[2], d31[2]}, [r4] +0x4f,0x6a,0xa5,0xf4 = vld3.32 {d6[0], d8[0], d10[0]}, [r5] +0x61,0xc2,0xa6,0xf4 = vld3.8 {d12[3], d13[3], d14[3]}, [r6], r1 +0x82,0xb6,0xa7,0xf4 = vld3.16 {d11[2], d12[2], d13[2]}, [r7], r2 +0x83,0x2a,0xa8,0xf4 = vld3.32 {d2[1], d3[1], d4[1]}, [r8], r3 +0xa4,0xe6,0xa9,0xf4 = vld3.16 {d14[2], d16[2], d18[2]}, [r9], r4 +0x45,0x0a,0xea,0xf4 = vld3.32 {d16[0], d18[0], d20[0]}, [r10], r5 +0xcd,0x62,0xa8,0xf4 = vld3.8 {d6[6], d7[6], d8[6]}, [r8]! +0x8d,0x96,0xa7,0xf4 = vld3.16 {d9[2], d10[2], d11[2]}, [r7]! +0x8d,0x1a,0xa6,0xf4 = vld3.32 {d1[1], d2[1], d3[1]}, [r6]! +0xad,0x46,0xe5,0xf4 = vld3.16 {d20[2], d22[2], d24[2]}, [r5]! +0x4d,0x5a,0xa4,0xf4 = vld3.32 {d5[0], d7[0], d9[0]}, [r4]! +0x0f,0x0e,0xe1,0xf4 = vld3.8 {d16[], d17[], d18[]}, [r1] +0x4f,0x0e,0xe2,0xf4 = vld3.16 {d16[], d17[], d18[]}, [r2] +0x8f,0x0e,0xe3,0xf4 = vld3.32 {d16[], d17[], d18[]}, [r3] +0x2f,0x1e,0xe7,0xf4 = vld3.8 {d17[], d19[], d21[]}, [r7] +0x6f,0x1e,0xe7,0xf4 = vld3.16 {d17[], d19[], d21[]}, [r7] +0xaf,0x0e,0xe8,0xf4 = vld3.32 {d16[], d18[], d20[]}, [r8] +0x0d,0x0e,0xe1,0xf4 = vld3.8 {d16[], d17[], d18[]}, [r1]! +0x4d,0x0e,0xe2,0xf4 = vld3.16 {d16[], d17[], d18[]}, [r2]! +0x8d,0x0e,0xe3,0xf4 = vld3.32 {d16[], d17[], d18[]}, [r3]! +0x2d,0x1e,0xe7,0xf4 = vld3.8 {d17[], d19[], d21[]}, [r7]! +0x6d,0x1e,0xe7,0xf4 = vld3.16 {d17[], d19[], d21[]}, [r7]! +0xad,0x0e,0xe8,0xf4 = vld3.32 {d16[], d18[], d20[]}, [r8]! +0x08,0x0e,0xe1,0xf4 = vld3.8 {d16[], d17[], d18[]}, [r1], r8 +0x47,0x0e,0xe2,0xf4 = vld3.16 {d16[], d17[], d18[]}, [r2], r7 +0x85,0x0e,0xe3,0xf4 = vld3.32 {d16[], d17[], d18[]}, [r3], r5 +0x23,0x0e,0xe6,0xf4 = vld3.8 {d16[], d18[], d20[]}, [r6], r3 +0x63,0x0e,0xe6,0xf4 = vld3.16 {d16[], d18[], d20[]}, [r6], r3 +0xa4,0x1e,0xe9,0xf4 = vld3.32 {d17[], d19[], d21[]}, [r9], r4 +0x2f,0x03,0xe1,0xf4 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1] +0x4f,0x07,0xe2,0xf4 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2] +0x8f,0x0b,0xe3,0xf4 = vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] +0x6f,0x17,0xe7,0xf4 = vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] +0xcf,0x0b,0xe8,0xf4 = vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] +0x3d,0x03,0xe1,0xf4 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! +0x5d,0x07,0xe2,0xf4 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]! +0xad,0x0b,0xe3,0xf4 = vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]! +0x6d,0x17,0xe7,0xf4 = vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]! +0xcd,0x0b,0xe8,0xf4 = vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! +0x38,0x03,0xe1,0xf4 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8 +0x47,0x07,0xe2,0xf4 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 +0x95,0x0b,0xe3,0xf4 = vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5 +0x63,0x07,0xe6,0xf4 = vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 +0xc4,0x1b,0xe9,0xf4 = vld4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 +0x0f,0x0f,0xe1,0xf4 = vld4.8 {d16[], d17[], d18[], d19[]}, [r1] +0x4f,0x0f,0xe2,0xf4 = vld4.16 {d16[], d17[], d18[], d19[]}, [r2] +0x8f,0x0f,0xe3,0xf4 = vld4.32 {d16[], d17[], d18[], d19[]}, [r3] +0x2f,0x1f,0xe7,0xf4 = vld4.8 {d17[], d19[], d21[], d23[]}, [r7] +0x6f,0x1f,0xe7,0xf4 = vld4.16 {d17[], d19[], d21[], d23[]}, [r7] +0xaf,0x0f,0xe8,0xf4 = vld4.32 {d16[], d18[], d20[], d22[]}, [r8] +0x0d,0x0f,0xe1,0xf4 = vld4.8 {d16[], d17[], d18[], d19[]}, [r1]! +0x4d,0x0f,0xe2,0xf4 = vld4.16 {d16[], d17[], d18[], d19[]}, [r2]! +0x8d,0x0f,0xe3,0xf4 = vld4.32 {d16[], d17[], d18[], d19[]}, [r3]! +0x2d,0x1f,0xe7,0xf4 = vld4.8 {d17[], d19[], d21[], d23[]}, [r7]! +0x6d,0x1f,0xe7,0xf4 = vld4.16 {d17[], d19[], d21[], d23[]}, [r7]! +0xad,0x0f,0xe8,0xf4 = vld4.32 {d16[], d18[], d20[], d22[]}, [r8]! +0x08,0x0f,0xe1,0xf4 = vld4.8 {d16[], d17[], d18[], d19[]}, [r1], r8 +0x47,0x0f,0xe2,0xf4 = vld4.16 {d16[], d17[], d18[], d19[]}, [r2], r7 +0x85,0x0f,0xe3,0xf4 = vld4.32 {d16[], d17[], d18[], d19[]}, [r3], r5 +0x23,0x0f,0xe6,0xf4 = vld4.8 {d16[], d18[], d20[], d22[]}, [r6], r3 +0x63,0x0f,0xe6,0xf4 = vld4.16 {d16[], d18[], d20[], d22[]}, [r6], r3 +0xa4,0x1f,0xe9,0xf4 = vld4.32 {d17[], d19[], d21[], d23[]}, [r9], r4 +0x0f,0x6a,0x29,0xf4 = vld1.8 {d6, d7}, [r9] +0x0f,0x62,0x29,0xf4 = vld1.8 {d6, d7, d8, d9}, [r9] +0x0f,0x27,0x22,0xf4 = vld1.8 {d2}, [r2] +0x0f,0x27,0x22,0xf4 = vld1.8 {d2}, [r2] +0x0f,0x27,0x22,0xf4 = vld1.8 {d2}, [r2] +0x0f,0x4a,0x22,0xf4 = vld1.8 {d4, d5}, [r2] +0x0f,0x4a,0x22,0xf4 = vld1.8 {d4, d5}, [r2] +0x0f,0x4a,0x22,0xf4 = vld1.8 {d4, d5}, [r2] +0x8f,0x4a,0x22,0xf4 = vld1.32 {d4, d5}, [r2] +0x0f,0x26,0x22,0xf4 = vld1.8 {d2, d3, d4}, [r2] +0x8f,0x26,0x22,0xf4 = vld1.32 {d2, d3, d4}, [r2] +0xcf,0x26,0x22,0xf4 = vld1.64 {d2, d3, d4}, [r2] +0xed,0x22,0x22,0xf4 = vld1.64 {d2, d3, d4, d5}, [r2:128]! +0xed,0x22,0x22,0xf4 = vld1.64 {d2, d3, d4, d5}, [r2:128]! +0x1f,0x08,0x60,0xf4 = vld2.8 {d16, d17}, [r0:64] +0x6f,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128] diff --git a/thirdparty/capstone/suite/MC/ARM/neon-vld-vst-align.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-vld-vst-align.s.cs new file mode 100644 index 0000000..ad793b7 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-vld-vst-align.s.cs @@ -0,0 +1,958 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x24,0xf9,0x0f,0x07 = vld1.8 {d0}, [r4] +0x24,0xf9,0x1f,0x07 = vld1.8 {d0}, [r4:64] +0x24,0xf9,0x0d,0x07 = vld1.8 {d0}, [r4]! +0x24,0xf9,0x1d,0x07 = vld1.8 {d0}, [r4:64]! +0x24,0xf9,0x06,0x07 = vld1.8 {d0}, [r4], r6 +0x24,0xf9,0x16,0x07 = vld1.8 {d0}, [r4:64], r6 +0x24,0xf9,0x0f,0x0a = vld1.8 {d0, d1}, [r4] +0x24,0xf9,0x1f,0x0a = vld1.8 {d0, d1}, [r4:64] +0x24,0xf9,0x2f,0x0a = vld1.8 {d0, d1}, [r4:128] +0x24,0xf9,0x0d,0x0a = vld1.8 {d0, d1}, [r4]! +0x24,0xf9,0x1d,0x0a = vld1.8 {d0, d1}, [r4:64]! +0x24,0xf9,0x2d,0x0a = vld1.8 {d0, d1}, [r4:128]! +0x24,0xf9,0x06,0x0a = vld1.8 {d0, d1}, [r4], r6 +0x24,0xf9,0x16,0x0a = vld1.8 {d0, d1}, [r4:64], r6 +0x24,0xf9,0x26,0x0a = vld1.8 {d0, d1}, [r4:128], r6 +0x24,0xf9,0x0f,0x06 = vld1.8 {d0, d1, d2}, [r4] +0x24,0xf9,0x1f,0x06 = vld1.8 {d0, d1, d2}, [r4:64] +0x24,0xf9,0x0d,0x06 = vld1.8 {d0, d1, d2}, [r4]! +0x24,0xf9,0x1d,0x06 = vld1.8 {d0, d1, d2}, [r4:64]! +0x24,0xf9,0x06,0x06 = vld1.8 {d0, d1, d2}, [r4], r6 +0x24,0xf9,0x16,0x06 = vld1.8 {d0, d1, d2}, [r4:64], r6 +0x24,0xf9,0x0f,0x02 = vld1.8 {d0, d1, d2, d3}, [r4] +0x24,0xf9,0x1f,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:64] +0x24,0xf9,0x2f,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:128] +0x24,0xf9,0x3f,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:256] +0x24,0xf9,0x0d,0x02 = vld1.8 {d0, d1, d2, d3}, [r4]! +0x24,0xf9,0x1d,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:64]! +0x24,0xf9,0x2d,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:128]! +0x24,0xf9,0x3d,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:256]! +0x24,0xf9,0x06,0x02 = vld1.8 {d0, d1, d2, d3}, [r4], r6 +0x24,0xf9,0x16,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:64], r6 +0x24,0xf9,0x26,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:128], r6 +0x24,0xf9,0x36,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:256], r6 +0xa4,0xf9,0x4f,0x00 = vld1.8 {d0[2]}, [r4] +0xa4,0xf9,0x4d,0x00 = vld1.8 {d0[2]}, [r4]! +0xa4,0xf9,0x46,0x00 = vld1.8 {d0[2]}, [r4], r6 +0xa4,0xf9,0x0f,0x0c = vld1.8 {d0[]}, [r4] +0xa4,0xf9,0x0d,0x0c = vld1.8 {d0[]}, [r4]! +0xa4,0xf9,0x06,0x0c = vld1.8 {d0[]}, [r4], r6 +0xa4,0xf9,0x2f,0x0c = vld1.8 {d0[], d1[]}, [r4] +0xa4,0xf9,0x2d,0x0c = vld1.8 {d0[], d1[]}, [r4]! +0xa4,0xf9,0x26,0x0c = vld1.8 {d0[], d1[]}, [r4], r6 +0x24,0xf9,0x4f,0x07 = vld1.16 {d0}, [r4] +0x24,0xf9,0x5f,0x07 = vld1.16 {d0}, [r4:64] +0x24,0xf9,0x4d,0x07 = vld1.16 {d0}, [r4]! +0x24,0xf9,0x5d,0x07 = vld1.16 {d0}, [r4:64]! +0x24,0xf9,0x46,0x07 = vld1.16 {d0}, [r4], r6 +0x24,0xf9,0x56,0x07 = vld1.16 {d0}, [r4:64], r6 +0x24,0xf9,0x4f,0x0a = vld1.16 {d0, d1}, [r4] +0x24,0xf9,0x5f,0x0a = vld1.16 {d0, d1}, [r4:64] +0x24,0xf9,0x6f,0x0a = vld1.16 {d0, d1}, [r4:128] +0x24,0xf9,0x4d,0x0a = vld1.16 {d0, d1}, [r4]! +0x24,0xf9,0x5d,0x0a = vld1.16 {d0, d1}, [r4:64]! +0x24,0xf9,0x6d,0x0a = vld1.16 {d0, d1}, [r4:128]! +0x24,0xf9,0x46,0x0a = vld1.16 {d0, d1}, [r4], r6 +0x24,0xf9,0x56,0x0a = vld1.16 {d0, d1}, [r4:64], r6 +0x24,0xf9,0x66,0x0a = vld1.16 {d0, d1}, [r4:128], r6 +0x24,0xf9,0x4f,0x06 = vld1.16 {d0, d1, d2}, [r4] +0x24,0xf9,0x5f,0x06 = vld1.16 {d0, d1, d2}, [r4:64] +0x24,0xf9,0x4d,0x06 = vld1.16 {d0, d1, d2}, [r4]! +0x24,0xf9,0x5d,0x06 = vld1.16 {d0, d1, d2}, [r4:64]! +0x24,0xf9,0x46,0x06 = vld1.16 {d0, d1, d2}, [r4], r6 +0x24,0xf9,0x56,0x06 = vld1.16 {d0, d1, d2}, [r4:64], r6 +0x24,0xf9,0x4f,0x02 = vld1.16 {d0, d1, d2, d3}, [r4] +0x24,0xf9,0x5f,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:64] +0x24,0xf9,0x6f,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:128] +0x24,0xf9,0x7f,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:256] +0x24,0xf9,0x4d,0x02 = vld1.16 {d0, d1, d2, d3}, [r4]! +0x24,0xf9,0x5d,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:64]! +0x24,0xf9,0x6d,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:128]! +0x24,0xf9,0x7d,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:256]! +0x24,0xf9,0x46,0x02 = vld1.16 {d0, d1, d2, d3}, [r4], r6 +0x24,0xf9,0x56,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:64], r6 +0x24,0xf9,0x66,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:128], r6 +0x24,0xf9,0x76,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:256], r6 +0xa4,0xf9,0x8f,0x04 = vld1.16 {d0[2]}, [r4] +0xa4,0xf9,0x9f,0x04 = vld1.16 {d0[2]}, [r4:16] +0xa4,0xf9,0x8d,0x04 = vld1.16 {d0[2]}, [r4]! +0xa4,0xf9,0x9d,0x04 = vld1.16 {d0[2]}, [r4:16]! +0xa4,0xf9,0x86,0x04 = vld1.16 {d0[2]}, [r4], r6 +0xa4,0xf9,0x96,0x04 = vld1.16 {d0[2]}, [r4:16], r6 +0xa4,0xf9,0x4f,0x0c = vld1.16 {d0[]}, [r4] +0xa4,0xf9,0x5f,0x0c = vld1.16 {d0[]}, [r4:16] +0xa4,0xf9,0x4d,0x0c = vld1.16 {d0[]}, [r4]! +0xa4,0xf9,0x5d,0x0c = vld1.16 {d0[]}, [r4:16]! +0xa4,0xf9,0x46,0x0c = vld1.16 {d0[]}, [r4], r6 +0xa4,0xf9,0x56,0x0c = vld1.16 {d0[]}, [r4:16], r6 +0xa4,0xf9,0x6f,0x0c = vld1.16 {d0[], d1[]}, [r4] +0xa4,0xf9,0x7f,0x0c = vld1.16 {d0[], d1[]}, [r4:16] +0xa4,0xf9,0x6d,0x0c = vld1.16 {d0[], d1[]}, [r4]! +0xa4,0xf9,0x7d,0x0c = vld1.16 {d0[], d1[]}, [r4:16]! +0xa4,0xf9,0x66,0x0c = vld1.16 {d0[], d1[]}, [r4], r6 +0xa4,0xf9,0x76,0x0c = vld1.16 {d0[], d1[]}, [r4:16], r6 +0x24,0xf9,0x8f,0x07 = vld1.32 {d0}, [r4] +0x24,0xf9,0x9f,0x07 = vld1.32 {d0}, [r4:64] +0x24,0xf9,0x8d,0x07 = vld1.32 {d0}, [r4]! +0x24,0xf9,0x9d,0x07 = vld1.32 {d0}, [r4:64]! +0x24,0xf9,0x86,0x07 = vld1.32 {d0}, [r4], r6 +0x24,0xf9,0x96,0x07 = vld1.32 {d0}, [r4:64], r6 +0x24,0xf9,0x8f,0x0a = vld1.32 {d0, d1}, [r4] +0x24,0xf9,0x9f,0x0a = vld1.32 {d0, d1}, [r4:64] +0x24,0xf9,0xaf,0x0a = vld1.32 {d0, d1}, [r4:128] +0x24,0xf9,0x8d,0x0a = vld1.32 {d0, d1}, [r4]! +0x24,0xf9,0x9d,0x0a = vld1.32 {d0, d1}, [r4:64]! +0x24,0xf9,0xad,0x0a = vld1.32 {d0, d1}, [r4:128]! +0x24,0xf9,0x86,0x0a = vld1.32 {d0, d1}, [r4], r6 +0x24,0xf9,0x96,0x0a = vld1.32 {d0, d1}, [r4:64], r6 +0x24,0xf9,0xa6,0x0a = vld1.32 {d0, d1}, [r4:128], r6 +0x24,0xf9,0x8f,0x06 = vld1.32 {d0, d1, d2}, [r4] +0x24,0xf9,0x9f,0x06 = vld1.32 {d0, d1, d2}, [r4:64] +0x24,0xf9,0x8d,0x06 = vld1.32 {d0, d1, d2}, [r4]! +0x24,0xf9,0x9d,0x06 = vld1.32 {d0, d1, d2}, [r4:64]! +0x24,0xf9,0x86,0x06 = vld1.32 {d0, d1, d2}, [r4], r6 +0x24,0xf9,0x96,0x06 = vld1.32 {d0, d1, d2}, [r4:64], r6 +0x24,0xf9,0x8f,0x02 = vld1.32 {d0, d1, d2, d3}, [r4] +0x24,0xf9,0x9f,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:64] +0x24,0xf9,0xaf,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:128] +0x24,0xf9,0xbf,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:256] +0x24,0xf9,0x8d,0x02 = vld1.32 {d0, d1, d2, d3}, [r4]! +0x24,0xf9,0x9d,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:64]! +0x24,0xf9,0xad,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:128]! +0x24,0xf9,0xbd,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:256]! +0x24,0xf9,0x86,0x02 = vld1.32 {d0, d1, d2, d3}, [r4], r6 +0x24,0xf9,0x96,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:64], r6 +0x24,0xf9,0xa6,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:128], r6 +0x24,0xf9,0xb6,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:256], r6 +0xa4,0xf9,0x8f,0x08 = vld1.32 {d0[1]}, [r4] +0xa4,0xf9,0xbf,0x08 = vld1.32 {d0[1]}, [r4:32] +0xa4,0xf9,0x8d,0x08 = vld1.32 {d0[1]}, [r4]! +0xa4,0xf9,0xbd,0x08 = vld1.32 {d0[1]}, [r4:32]! +0xa4,0xf9,0x86,0x08 = vld1.32 {d0[1]}, [r4], r6 +0xa4,0xf9,0xb6,0x08 = vld1.32 {d0[1]}, [r4:32], r6 +0xa4,0xf9,0x8f,0x0c = vld1.32 {d0[]}, [r4] +0xa4,0xf9,0x9f,0x0c = vld1.32 {d0[]}, [r4:32] +0xa4,0xf9,0x8d,0x0c = vld1.32 {d0[]}, [r4]! +0xa4,0xf9,0x9d,0x0c = vld1.32 {d0[]}, [r4:32]! +0xa4,0xf9,0x86,0x0c = vld1.32 {d0[]}, [r4], r6 +0xa4,0xf9,0x96,0x0c = vld1.32 {d0[]}, [r4:32], r6 +0xa4,0xf9,0xaf,0x0c = vld1.32 {d0[], d1[]}, [r4] +0xa4,0xf9,0xbf,0x0c = vld1.32 {d0[], d1[]}, [r4:32] +0xa4,0xf9,0xad,0x0c = vld1.32 {d0[], d1[]}, [r4]! +0xa4,0xf9,0xbd,0x0c = vld1.32 {d0[], d1[]}, [r4:32]! +0xa4,0xf9,0xa6,0x0c = vld1.32 {d0[], d1[]}, [r4], r6 +0xa4,0xf9,0xb6,0x0c = vld1.32 {d0[], d1[]}, [r4:32], r6 +0xa4,0xf9,0x8f,0x08 = vld1.32 {d0[1]}, [r4] +0xa4,0xf9,0xbf,0x08 = vld1.32 {d0[1]}, [r4:32] +0xa4,0xf9,0x8d,0x08 = vld1.32 {d0[1]}, [r4]! +0xa4,0xf9,0xbd,0x08 = vld1.32 {d0[1]}, [r4:32]! +0xa4,0xf9,0x86,0x08 = vld1.32 {d0[1]}, [r4], r6 +0xa4,0xf9,0xb6,0x08 = vld1.32 {d0[1]}, [r4:32], r6 +0x24,0xf9,0xcf,0x07 = vld1.64 {d0}, [r4] +0x24,0xf9,0xdf,0x07 = vld1.64 {d0}, [r4:64] +0x24,0xf9,0xcd,0x07 = vld1.64 {d0}, [r4]! +0x24,0xf9,0xdd,0x07 = vld1.64 {d0}, [r4:64]! +0x24,0xf9,0xc6,0x07 = vld1.64 {d0}, [r4], r6 +0x24,0xf9,0xd6,0x07 = vld1.64 {d0}, [r4:64], r6 +0x24,0xf9,0xcf,0x0a = vld1.64 {d0, d1}, [r4] +0x24,0xf9,0xdf,0x0a = vld1.64 {d0, d1}, [r4:64] +0x24,0xf9,0xef,0x0a = vld1.64 {d0, d1}, [r4:128] +0x24,0xf9,0xcd,0x0a = vld1.64 {d0, d1}, [r4]! +0x24,0xf9,0xdd,0x0a = vld1.64 {d0, d1}, [r4:64]! +0x24,0xf9,0xed,0x0a = vld1.64 {d0, d1}, [r4:128]! +0x24,0xf9,0xc6,0x0a = vld1.64 {d0, d1}, [r4], r6 +0x24,0xf9,0xd6,0x0a = vld1.64 {d0, d1}, [r4:64], r6 +0x24,0xf9,0xe6,0x0a = vld1.64 {d0, d1}, [r4:128], r6 +0x24,0xf9,0xcf,0x06 = vld1.64 {d0, d1, d2}, [r4] +0x24,0xf9,0xdf,0x06 = vld1.64 {d0, d1, d2}, [r4:64] +0x24,0xf9,0xcd,0x06 = vld1.64 {d0, d1, d2}, [r4]! +0x24,0xf9,0xdd,0x06 = vld1.64 {d0, d1, d2}, [r4:64]! +0x24,0xf9,0xc6,0x06 = vld1.64 {d0, d1, d2}, [r4], r6 +0x24,0xf9,0xd6,0x06 = vld1.64 {d0, d1, d2}, [r4:64], r6 +0x24,0xf9,0xcf,0x02 = vld1.64 {d0, d1, d2, d3}, [r4] +0x24,0xf9,0xdf,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:64] +0x24,0xf9,0xef,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:128] +0x24,0xf9,0xff,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:256] +0x24,0xf9,0xcd,0x02 = vld1.64 {d0, d1, d2, d3}, [r4]! +0x24,0xf9,0xdd,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:64]! +0x24,0xf9,0xed,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:128]! +0x24,0xf9,0xfd,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:256]! +0x24,0xf9,0xc6,0x02 = vld1.64 {d0, d1, d2, d3}, [r4], r6 +0x24,0xf9,0xd6,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:64], r6 +0x24,0xf9,0xe6,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:128], r6 +0x24,0xf9,0xf6,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:256], r6 +0x24,0xf9,0x0f,0x08 = vld2.8 {d0, d1}, [r4] +0x24,0xf9,0x1f,0x08 = vld2.8 {d0, d1}, [r4:64] +0x24,0xf9,0x2f,0x08 = vld2.8 {d0, d1}, [r4:128] +0x24,0xf9,0x0d,0x08 = vld2.8 {d0, d1}, [r4]! +0x24,0xf9,0x1d,0x08 = vld2.8 {d0, d1}, [r4:64]! +0x24,0xf9,0x2d,0x08 = vld2.8 {d0, d1}, [r4:128]! +0x24,0xf9,0x06,0x08 = vld2.8 {d0, d1}, [r4], r6 +0x24,0xf9,0x16,0x08 = vld2.8 {d0, d1}, [r4:64], r6 +0x24,0xf9,0x26,0x08 = vld2.8 {d0, d1}, [r4:128], r6 +0x24,0xf9,0x0f,0x09 = vld2.8 {d0, d2}, [r4] +0x24,0xf9,0x1f,0x09 = vld2.8 {d0, d2}, [r4:64] +0x24,0xf9,0x2f,0x09 = vld2.8 {d0, d2}, [r4:128] +0x24,0xf9,0x0d,0x09 = vld2.8 {d0, d2}, [r4]! +0x24,0xf9,0x1d,0x09 = vld2.8 {d0, d2}, [r4:64]! +0x24,0xf9,0x2d,0x09 = vld2.8 {d0, d2}, [r4:128]! +0x24,0xf9,0x06,0x09 = vld2.8 {d0, d2}, [r4], r6 +0x24,0xf9,0x16,0x09 = vld2.8 {d0, d2}, [r4:64], r6 +0x24,0xf9,0x26,0x09 = vld2.8 {d0, d2}, [r4:128], r6 +0x24,0xf9,0x0f,0x03 = vld2.8 {d0, d1, d2, d3}, [r4] +0x24,0xf9,0x1f,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:64] +0x24,0xf9,0x2f,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:128] +0x24,0xf9,0x3f,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:256] +0x24,0xf9,0x0d,0x03 = vld2.8 {d0, d1, d2, d3}, [r4]! +0x24,0xf9,0x1d,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:64]! +0x24,0xf9,0x2d,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:128]! +0x24,0xf9,0x3d,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:256]! +0x24,0xf9,0x06,0x03 = vld2.8 {d0, d1, d2, d3}, [r4], r6 +0x24,0xf9,0x16,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:64], r6 +0x24,0xf9,0x26,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:128], r6 +0x24,0xf9,0x36,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:256], r6 +0xa4,0xf9,0x4f,0x01 = vld2.8 {d0[2], d1[2]}, [r4] +0xa4,0xf9,0x5f,0x01 = vld2.8 {d0[2], d1[2]}, [r4:16] +0xa4,0xf9,0x4d,0x01 = vld2.8 {d0[2], d1[2]}, [r4]! +0xa4,0xf9,0x5d,0x01 = vld2.8 {d0[2], d1[2]}, [r4:16]! +0xa4,0xf9,0x46,0x01 = vld2.8 {d0[2], d1[2]}, [r4], r6 +0xa4,0xf9,0x56,0x01 = vld2.8 {d0[2], d1[2]}, [r4:16], r6 +0xa4,0xf9,0x0f,0x0d = vld2.8 {d0[], d1[]}, [r4] +0xa4,0xf9,0x1f,0x0d = vld2.8 {d0[], d1[]}, [r4:16] +0xa4,0xf9,0x0d,0x0d = vld2.8 {d0[], d1[]}, [r4]! +0xa4,0xf9,0x1d,0x0d = vld2.8 {d0[], d1[]}, [r4:16]! +0xa4,0xf9,0x06,0x0d = vld2.8 {d0[], d1[]}, [r4], r6 +0xa4,0xf9,0x16,0x0d = vld2.8 {d0[], d1[]}, [r4:16], r6 +0xa4,0xf9,0x2f,0x0d = vld2.8 {d0[], d2[]}, [r4] +0xa4,0xf9,0x3f,0x0d = vld2.8 {d0[], d2[]}, [r4:16] +0xa4,0xf9,0x2d,0x0d = vld2.8 {d0[], d2[]}, [r4]! +0xa4,0xf9,0x3d,0x0d = vld2.8 {d0[], d2[]}, [r4:16]! +0xa4,0xf9,0x26,0x0d = vld2.8 {d0[], d2[]}, [r4], r6 +0xa4,0xf9,0x36,0x0d = vld2.8 {d0[], d2[]}, [r4:16], r6 +0x24,0xf9,0x4f,0x08 = vld2.16 {d0, d1}, [r4] +0x24,0xf9,0x5f,0x08 = vld2.16 {d0, d1}, [r4:64] +0x24,0xf9,0x6f,0x08 = vld2.16 {d0, d1}, [r4:128] +0x24,0xf9,0x4d,0x08 = vld2.16 {d0, d1}, [r4]! +0x24,0xf9,0x5d,0x08 = vld2.16 {d0, d1}, [r4:64]! +0x24,0xf9,0x6d,0x08 = vld2.16 {d0, d1}, [r4:128]! +0x24,0xf9,0x46,0x08 = vld2.16 {d0, d1}, [r4], r6 +0x24,0xf9,0x56,0x08 = vld2.16 {d0, d1}, [r4:64], r6 +0x24,0xf9,0x66,0x08 = vld2.16 {d0, d1}, [r4:128], r6 +0x24,0xf9,0x4f,0x09 = vld2.16 {d0, d2}, [r4] +0x24,0xf9,0x5f,0x09 = vld2.16 {d0, d2}, [r4:64] +0x24,0xf9,0x6f,0x09 = vld2.16 {d0, d2}, [r4:128] +0x24,0xf9,0x4d,0x09 = vld2.16 {d0, d2}, [r4]! +0x24,0xf9,0x5d,0x09 = vld2.16 {d0, d2}, [r4:64]! +0x24,0xf9,0x6d,0x09 = vld2.16 {d0, d2}, [r4:128]! +0x24,0xf9,0x46,0x09 = vld2.16 {d0, d2}, [r4], r6 +0x24,0xf9,0x56,0x09 = vld2.16 {d0, d2}, [r4:64], r6 +0x24,0xf9,0x66,0x09 = vld2.16 {d0, d2}, [r4:128], r6 +0x24,0xf9,0x4f,0x03 = vld2.16 {d0, d1, d2, d3}, [r4] +0x24,0xf9,0x5f,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:64] +0x24,0xf9,0x6f,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:128] +0x24,0xf9,0x7f,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:256] +0x24,0xf9,0x4d,0x03 = vld2.16 {d0, d1, d2, d3}, [r4]! +0x24,0xf9,0x5d,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:64]! +0x24,0xf9,0x6d,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:128]! +0x24,0xf9,0x7d,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:256]! +0x24,0xf9,0x46,0x03 = vld2.16 {d0, d1, d2, d3}, [r4], r6 +0x24,0xf9,0x56,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:64], r6 +0x24,0xf9,0x66,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:128], r6 +0x24,0xf9,0x76,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:256], r6 +0xa4,0xf9,0x8f,0x05 = vld2.16 {d0[2], d1[2]}, [r4] +0xa4,0xf9,0x9f,0x05 = vld2.16 {d0[2], d1[2]}, [r4:32] +0xa4,0xf9,0x8d,0x05 = vld2.16 {d0[2], d1[2]}, [r4]! +0xa4,0xf9,0x9d,0x05 = vld2.16 {d0[2], d1[2]}, [r4:32]! +0xa4,0xf9,0x86,0x05 = vld2.16 {d0[2], d1[2]}, [r4], r6 +0xa4,0xf9,0x96,0x05 = vld2.16 {d0[2], d1[2]}, [r4:32], r6 +0xa4,0xf9,0xaf,0x05 = vld2.16 {d0[2], d2[2]}, [r4] +0xa4,0xf9,0xbf,0x05 = vld2.16 {d0[2], d2[2]}, [r4:32] +0xa4,0xf9,0xad,0x05 = vld2.16 {d0[2], d2[2]}, [r4]! +0xa4,0xf9,0xbd,0x05 = vld2.16 {d0[2], d2[2]}, [r4:32]! +0xa4,0xf9,0xa6,0x05 = vld2.16 {d0[2], d2[2]}, [r4], r6 +0xa4,0xf9,0xb6,0x05 = vld2.16 {d0[2], d2[2]}, [r4:32], r6 +0xa4,0xf9,0x4f,0x0d = vld2.16 {d0[], d1[]}, [r4] +0xa4,0xf9,0x5f,0x0d = vld2.16 {d0[], d1[]}, [r4:32] +0xa4,0xf9,0x4d,0x0d = vld2.16 {d0[], d1[]}, [r4]! +0xa4,0xf9,0x5d,0x0d = vld2.16 {d0[], d1[]}, [r4:32]! +0xa4,0xf9,0x46,0x0d = vld2.16 {d0[], d1[]}, [r4], r6 +0xa4,0xf9,0x56,0x0d = vld2.16 {d0[], d1[]}, [r4:32], r6 +0xa4,0xf9,0x6f,0x0d = vld2.16 {d0[], d2[]}, [r4] +0xa4,0xf9,0x7f,0x0d = vld2.16 {d0[], d2[]}, [r4:32] +0xa4,0xf9,0x6d,0x0d = vld2.16 {d0[], d2[]}, [r4]! +0xa4,0xf9,0x7d,0x0d = vld2.16 {d0[], d2[]}, [r4:32]! +0xa4,0xf9,0x66,0x0d = vld2.16 {d0[], d2[]}, [r4], r6 +0xa4,0xf9,0x76,0x0d = vld2.16 {d0[], d2[]}, [r4:32], r6 +0x24,0xf9,0x8f,0x08 = vld2.32 {d0, d1}, [r4] +0x24,0xf9,0x9f,0x08 = vld2.32 {d0, d1}, [r4:64] +0x24,0xf9,0xaf,0x08 = vld2.32 {d0, d1}, [r4:128] +0x24,0xf9,0x8d,0x08 = vld2.32 {d0, d1}, [r4]! +0x24,0xf9,0x9d,0x08 = vld2.32 {d0, d1}, [r4:64]! +0x24,0xf9,0xad,0x08 = vld2.32 {d0, d1}, [r4:128]! +0x24,0xf9,0x86,0x08 = vld2.32 {d0, d1}, [r4], r6 +0x24,0xf9,0x96,0x08 = vld2.32 {d0, d1}, [r4:64], r6 +0x24,0xf9,0xa6,0x08 = vld2.32 {d0, d1}, [r4:128], r6 +0x24,0xf9,0x8f,0x09 = vld2.32 {d0, d2}, [r4] +0x24,0xf9,0x9f,0x09 = vld2.32 {d0, d2}, [r4:64] +0x24,0xf9,0xaf,0x09 = vld2.32 {d0, d2}, [r4:128] +0x24,0xf9,0x8d,0x09 = vld2.32 {d0, d2}, [r4]! +0x24,0xf9,0x9d,0x09 = vld2.32 {d0, d2}, [r4:64]! +0x24,0xf9,0xad,0x09 = vld2.32 {d0, d2}, [r4:128]! +0x24,0xf9,0x86,0x09 = vld2.32 {d0, d2}, [r4], r6 +0x24,0xf9,0x96,0x09 = vld2.32 {d0, d2}, [r4:64], r6 +0x24,0xf9,0xa6,0x09 = vld2.32 {d0, d2}, [r4:128], r6 +0x24,0xf9,0x8f,0x03 = vld2.32 {d0, d1, d2, d3}, [r4] +0x24,0xf9,0x9f,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:64] +0x24,0xf9,0xaf,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:128] +0x24,0xf9,0xbf,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:256] +0x24,0xf9,0x8d,0x03 = vld2.32 {d0, d1, d2, d3}, [r4]! +0x24,0xf9,0x9d,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:64]! +0x24,0xf9,0xad,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:128]! +0x24,0xf9,0xbd,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:256]! +0x24,0xf9,0x86,0x03 = vld2.32 {d0, d1, d2, d3}, [r4], r6 +0x24,0xf9,0x96,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:64], r6 +0x24,0xf9,0xa6,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:128], r6 +0x24,0xf9,0xb6,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:256], r6 +0xa4,0xf9,0x8f,0x09 = vld2.32 {d0[1], d1[1]}, [r4] +0xa4,0xf9,0x9f,0x09 = vld2.32 {d0[1], d1[1]}, [r4:64] +0xa4,0xf9,0x8d,0x09 = vld2.32 {d0[1], d1[1]}, [r4]! +0xa4,0xf9,0x9d,0x09 = vld2.32 {d0[1], d1[1]}, [r4:64]! +0xa4,0xf9,0x86,0x09 = vld2.32 {d0[1], d1[1]}, [r4], r6 +0xa4,0xf9,0x96,0x09 = vld2.32 {d0[1], d1[1]}, [r4:64], r6 +0xa4,0xf9,0xcf,0x09 = vld2.32 {d0[1], d2[1]}, [r4] +0xa4,0xf9,0xdf,0x09 = vld2.32 {d0[1], d2[1]}, [r4:64] +0xa4,0xf9,0xcd,0x09 = vld2.32 {d0[1], d2[1]}, [r4]! +0xa4,0xf9,0xdd,0x09 = vld2.32 {d0[1], d2[1]}, [r4:64]! +0xa4,0xf9,0xc6,0x09 = vld2.32 {d0[1], d2[1]}, [r4], r6 +0xa4,0xf9,0xd6,0x09 = vld2.32 {d0[1], d2[1]}, [r4:64], r6 +0xa4,0xf9,0x8f,0x0d = vld2.32 {d0[], d1[]}, [r4] +0xa4,0xf9,0x9f,0x0d = vld2.32 {d0[], d1[]}, [r4:64] +0xa4,0xf9,0x8d,0x0d = vld2.32 {d0[], d1[]}, [r4]! +0xa4,0xf9,0x9d,0x0d = vld2.32 {d0[], d1[]}, [r4:64]! +0xa4,0xf9,0x86,0x0d = vld2.32 {d0[], d1[]}, [r4], r6 +0xa4,0xf9,0x96,0x0d = vld2.32 {d0[], d1[]}, [r4:64], r6 +0xa4,0xf9,0xaf,0x0d = vld2.32 {d0[], d2[]}, [r4] +0xa4,0xf9,0xbf,0x0d = vld2.32 {d0[], d2[]}, [r4:64] +0xa4,0xf9,0xad,0x0d = vld2.32 {d0[], d2[]}, [r4]! +0xa4,0xf9,0xbd,0x0d = vld2.32 {d0[], d2[]}, [r4:64]! +0xa4,0xf9,0xa6,0x0d = vld2.32 {d0[], d2[]}, [r4], r6 +0xa4,0xf9,0xb6,0x0d = vld2.32 {d0[], d2[]}, [r4:64], r6 +0x24,0xf9,0x0f,0x04 = vld3.8 {d0, d1, d2}, [r4] +0x24,0xf9,0x1f,0x04 = vld3.8 {d0, d1, d2}, [r4:64] +0x24,0xf9,0x0d,0x04 = vld3.8 {d0, d1, d2}, [r4]! +0x24,0xf9,0x1d,0x04 = vld3.8 {d0, d1, d2}, [r4:64]! +0x24,0xf9,0x06,0x04 = vld3.8 {d0, d1, d2}, [r4], r6 +0x24,0xf9,0x16,0x04 = vld3.8 {d0, d1, d2}, [r4:64], r6 +0x24,0xf9,0x0f,0x05 = vld3.8 {d0, d2, d4}, [r4] +0x24,0xf9,0x1f,0x05 = vld3.8 {d0, d2, d4}, [r4:64] +0x24,0xf9,0x0d,0x05 = vld3.8 {d0, d2, d4}, [r4]! +0x24,0xf9,0x1d,0x05 = vld3.8 {d0, d2, d4}, [r4:64]! +0x24,0xf9,0x06,0x05 = vld3.8 {d0, d2, d4}, [r4], r6 +0x24,0xf9,0x16,0x05 = vld3.8 {d0, d2, d4}, [r4:64], r6 +0xa4,0xf9,0x2f,0x02 = vld3.8 {d0[1], d1[1], d2[1]}, [r4] +0xa4,0xf9,0x2d,0x02 = vld3.8 {d0[1], d1[1], d2[1]}, [r4]! +0xa4,0xf9,0x26,0x02 = vld3.8 {d0[1], d1[1], d2[1]}, [r4], r6 +0xa4,0xf9,0x0f,0x0e = vld3.8 {d0[], d1[], d2[]}, [r4] +0xa4,0xf9,0x0d,0x0e = vld3.8 {d0[], d1[], d2[]}, [r4]! +0xa4,0xf9,0x06,0x0e = vld3.8 {d0[], d1[], d2[]}, [r4], r6 +0xa4,0xf9,0x2f,0x0e = vld3.8 {d0[], d2[], d4[]}, [r4] +0xa4,0xf9,0x2d,0x0e = vld3.8 {d0[], d2[], d4[]}, [r4]! +0xa4,0xf9,0x26,0x0e = vld3.8 {d0[], d2[], d4[]}, [r4], r6 +0x24,0xf9,0x4f,0x04 = vld3.16 {d0, d1, d2}, [r4] +0x24,0xf9,0x5f,0x04 = vld3.16 {d0, d1, d2}, [r4:64] +0x24,0xf9,0x4d,0x04 = vld3.16 {d0, d1, d2}, [r4]! +0x24,0xf9,0x5d,0x04 = vld3.16 {d0, d1, d2}, [r4:64]! +0x24,0xf9,0x46,0x04 = vld3.16 {d0, d1, d2}, [r4], r6 +0x24,0xf9,0x56,0x04 = vld3.16 {d0, d1, d2}, [r4:64], r6 +0x24,0xf9,0x4f,0x05 = vld3.16 {d0, d2, d4}, [r4] +0x24,0xf9,0x5f,0x05 = vld3.16 {d0, d2, d4}, [r4:64] +0x24,0xf9,0x4d,0x05 = vld3.16 {d0, d2, d4}, [r4]! +0x24,0xf9,0x5d,0x05 = vld3.16 {d0, d2, d4}, [r4:64]! +0x24,0xf9,0x46,0x05 = vld3.16 {d0, d2, d4}, [r4], r6 +0x24,0xf9,0x56,0x05 = vld3.16 {d0, d2, d4}, [r4:64], r6 +0xa4,0xf9,0x4f,0x06 = vld3.16 {d0[1], d1[1], d2[1]}, [r4] +0xa4,0xf9,0x4d,0x06 = vld3.16 {d0[1], d1[1], d2[1]}, [r4]! +0xa4,0xf9,0x46,0x06 = vld3.16 {d0[1], d1[1], d2[1]}, [r4], r6 +0xa4,0xf9,0x6f,0x06 = vld3.16 {d0[1], d2[1], d4[1]}, [r4] +0xa4,0xf9,0x6d,0x06 = vld3.16 {d0[1], d2[1], d4[1]}, [r4]! +0xa4,0xf9,0x66,0x06 = vld3.16 {d0[1], d2[1], d4[1]}, [r4], r6 +0xa4,0xf9,0x4f,0x0e = vld3.16 {d0[], d1[], d2[]}, [r4] +0xa4,0xf9,0x4d,0x0e = vld3.16 {d0[], d1[], d2[]}, [r4]! +0xa4,0xf9,0x46,0x0e = vld3.16 {d0[], d1[], d2[]}, [r4], r6 +0xa4,0xf9,0x6f,0x0e = vld3.16 {d0[], d2[], d4[]}, [r4] +0xa4,0xf9,0x6d,0x0e = vld3.16 {d0[], d2[], d4[]}, [r4]! +0xa4,0xf9,0x66,0x0e = vld3.16 {d0[], d2[], d4[]}, [r4], r6 +0x24,0xf9,0x8f,0x04 = vld3.32 {d0, d1, d2}, [r4] +0x24,0xf9,0x9f,0x04 = vld3.32 {d0, d1, d2}, [r4:64] +0x24,0xf9,0x8d,0x04 = vld3.32 {d0, d1, d2}, [r4]! +0x24,0xf9,0x9d,0x04 = vld3.32 {d0, d1, d2}, [r4:64]! +0x24,0xf9,0x86,0x04 = vld3.32 {d0, d1, d2}, [r4], r6 +0x24,0xf9,0x96,0x04 = vld3.32 {d0, d1, d2}, [r4:64], r6 +0x24,0xf9,0x8f,0x05 = vld3.32 {d0, d2, d4}, [r4] +0x24,0xf9,0x9f,0x05 = vld3.32 {d0, d2, d4}, [r4:64] +0x24,0xf9,0x8d,0x05 = vld3.32 {d0, d2, d4}, [r4]! +0x24,0xf9,0x9d,0x05 = vld3.32 {d0, d2, d4}, [r4:64]! +0x24,0xf9,0x86,0x05 = vld3.32 {d0, d2, d4}, [r4], r6 +0x24,0xf9,0x96,0x05 = vld3.32 {d0, d2, d4}, [r4:64], r6 +0xa4,0xf9,0x8f,0x0a = vld3.32 {d0[1], d1[1], d2[1]}, [r4] +0xa4,0xf9,0x8d,0x0a = vld3.32 {d0[1], d1[1], d2[1]}, [r4]! +0xa4,0xf9,0x86,0x0a = vld3.32 {d0[1], d1[1], d2[1]}, [r4], r6 +0xa4,0xf9,0xcf,0x0a = vld3.32 {d0[1], d2[1], d4[1]}, [r4] +0xa4,0xf9,0xcd,0x0a = vld3.32 {d0[1], d2[1], d4[1]}, [r4]! +0xa4,0xf9,0xc6,0x0a = vld3.32 {d0[1], d2[1], d4[1]}, [r4], r6 +0xa4,0xf9,0x8f,0x0e = vld3.32 {d0[], d1[], d2[]}, [r4] +0xa4,0xf9,0x8d,0x0e = vld3.32 {d0[], d1[], d2[]}, [r4]! +0xa4,0xf9,0x86,0x0e = vld3.32 {d0[], d1[], d2[]}, [r4], r6 +0xa4,0xf9,0xaf,0x0e = vld3.32 {d0[], d2[], d4[]}, [r4] +0xa4,0xf9,0xad,0x0e = vld3.32 {d0[], d2[], d4[]}, [r4]! +0xa4,0xf9,0xa6,0x0e = vld3.32 {d0[], d2[], d4[]}, [r4], r6 +0x24,0xf9,0x0f,0x00 = vld4.8 {d0, d1, d2, d3}, [r4] +0x24,0xf9,0x1f,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:64] +0x24,0xf9,0x2f,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:128] +0x24,0xf9,0x3f,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:256] +0x24,0xf9,0x0d,0x00 = vld4.8 {d0, d1, d2, d3}, [r4]! +0x24,0xf9,0x1d,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:64]! +0x24,0xf9,0x2d,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:128]! +0x24,0xf9,0x3d,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:256]! +0x24,0xf9,0x06,0x00 = vld4.8 {d0, d1, d2, d3}, [r4], r6 +0x24,0xf9,0x16,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:64], r6 +0x24,0xf9,0x26,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:128], r6 +0x24,0xf9,0x36,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:256], r6 +0x24,0xf9,0x0f,0x01 = vld4.8 {d0, d2, d4, d6}, [r4] +0x24,0xf9,0x1f,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:64] +0x24,0xf9,0x2f,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:128] +0x24,0xf9,0x3f,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:256] +0x24,0xf9,0x0d,0x01 = vld4.8 {d0, d2, d4, d6}, [r4]! +0x24,0xf9,0x1d,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:64]! +0x24,0xf9,0x2d,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:128]! +0x24,0xf9,0x3d,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:256]! +0x24,0xf9,0x06,0x01 = vld4.8 {d0, d2, d4, d6}, [r4], r6 +0x24,0xf9,0x16,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:64], r6 +0x24,0xf9,0x26,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:128], r6 +0x24,0xf9,0x36,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:256], r6 +0xa4,0xf9,0x2f,0x03 = vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4] +0xa4,0xf9,0x3f,0x03 = vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] +0xa4,0xf9,0x2d,0x03 = vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]! +0xa4,0xf9,0x3d,0x03 = vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! +0xa4,0xf9,0x26,0x03 = vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 +0xa4,0xf9,0x36,0x03 = vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 +0xa4,0xf9,0x0f,0x0f = vld4.8 {d0[], d1[], d2[], d3[]}, [r4] +0xa4,0xf9,0x1f,0x0f = vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32] +0xa4,0xf9,0x0d,0x0f = vld4.8 {d0[], d1[], d2[], d3[]}, [r4]! +0xa4,0xf9,0x1d,0x0f = vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! +0xa4,0xf9,0x06,0x0f = vld4.8 {d0[], d1[], d2[], d3[]}, [r4], r6 +0xa4,0xf9,0x16,0x0f = vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32], r6 +0xa4,0xf9,0x2f,0x0f = vld4.8 {d0[], d2[], d4[], d6[]}, [r4] +0xa4,0xf9,0x3f,0x0f = vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32] +0xa4,0xf9,0x2d,0x0f = vld4.8 {d0[], d2[], d4[], d6[]}, [r4]! +0xa4,0xf9,0x3d,0x0f = vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]! +0xa4,0xf9,0x26,0x0f = vld4.8 {d0[], d2[], d4[], d6[]}, [r4], r6 +0xa4,0xf9,0x36,0x0f = vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r6 +0x24,0xf9,0x4f,0x00 = vld4.16 {d0, d1, d2, d3}, [r4] +0x24,0xf9,0x5f,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:64] +0x24,0xf9,0x6f,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:128] +0x24,0xf9,0x7f,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:256] +0x24,0xf9,0x4d,0x00 = vld4.16 {d0, d1, d2, d3}, [r4]! +0x24,0xf9,0x5d,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:64]! +0x24,0xf9,0x6d,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:128]! +0x24,0xf9,0x7d,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:256]! +0x24,0xf9,0x46,0x00 = vld4.16 {d0, d1, d2, d3}, [r4], r6 +0x24,0xf9,0x56,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:64], r6 +0x24,0xf9,0x66,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:128], r6 +0x24,0xf9,0x76,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:256], r6 +0x24,0xf9,0x4f,0x01 = vld4.16 {d0, d2, d4, d6}, [r4] +0x24,0xf9,0x5f,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:64] +0x24,0xf9,0x6f,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:128] +0x24,0xf9,0x7f,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:256] +0x24,0xf9,0x4d,0x01 = vld4.16 {d0, d2, d4, d6}, [r4]! +0x24,0xf9,0x5d,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:64]! +0x24,0xf9,0x6d,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:128]! +0x24,0xf9,0x7d,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:256]! +0x24,0xf9,0x46,0x01 = vld4.16 {d0, d2, d4, d6}, [r4], r6 +0x24,0xf9,0x56,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:64], r6 +0x24,0xf9,0x66,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:128], r6 +0x24,0xf9,0x76,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:256], r6 +0xa4,0xf9,0x4f,0x07 = vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4] +0xa4,0xf9,0x5f,0x07 = vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] +0xa4,0xf9,0x4d,0x07 = vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! +0xa4,0xf9,0x5d,0x07 = vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! +0xa4,0xf9,0x46,0x07 = vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 +0xa4,0xf9,0x56,0x07 = vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 +0xa4,0xf9,0x6f,0x07 = vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4] +0xa4,0xf9,0x7f,0x07 = vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] +0xa4,0xf9,0x6d,0x07 = vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]! +0xa4,0xf9,0x7d,0x07 = vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! +0xa4,0xf9,0x66,0x07 = vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 +0xa4,0xf9,0x76,0x07 = vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 +0xa4,0xf9,0x4f,0x0f = vld4.16 {d0[], d1[], d2[], d3[]}, [r4] +0xa4,0xf9,0x5f,0x0f = vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64] +0xa4,0xf9,0x4d,0x0f = vld4.16 {d0[], d1[], d2[], d3[]}, [r4]! +0xa4,0xf9,0x5d,0x0f = vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! +0xa4,0xf9,0x46,0x0f = vld4.16 {d0[], d1[], d2[], d3[]}, [r4], r6 +0xa4,0xf9,0x56,0x0f = vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64], r6 +0xa4,0xf9,0x6f,0x0f = vld4.16 {d0[], d2[], d4[], d6[]}, [r4] +0xa4,0xf9,0x7f,0x0f = vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64] +0xa4,0xf9,0x6d,0x0f = vld4.16 {d0[], d2[], d4[], d6[]}, [r4]! +0xa4,0xf9,0x7d,0x0f = vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]! +0xa4,0xf9,0x66,0x0f = vld4.16 {d0[], d2[], d4[], d6[]}, [r4], r6 +0xa4,0xf9,0x76,0x0f = vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r6 +0x24,0xf9,0x8f,0x00 = vld4.32 {d0, d1, d2, d3}, [r4] +0x24,0xf9,0x9f,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:64] +0x24,0xf9,0xaf,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:128] +0x24,0xf9,0xbf,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:256] +0x24,0xf9,0x8d,0x00 = vld4.32 {d0, d1, d2, d3}, [r4]! +0x24,0xf9,0x9d,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:64]! +0x24,0xf9,0xad,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:128]! +0x24,0xf9,0xbd,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:256]! +0x24,0xf9,0x86,0x00 = vld4.32 {d0, d1, d2, d3}, [r4], r6 +0x24,0xf9,0x96,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:64], r6 +0x24,0xf9,0xa6,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:128], r6 +0x24,0xf9,0xb6,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:256], r6 +0x24,0xf9,0x8f,0x01 = vld4.32 {d0, d2, d4, d6}, [r4] +0x24,0xf9,0x9f,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:64] +0x24,0xf9,0xaf,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:128] +0x24,0xf9,0xbf,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:256] +0x24,0xf9,0x8d,0x01 = vld4.32 {d0, d2, d4, d6}, [r4]! +0x24,0xf9,0x9d,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:64]! +0x24,0xf9,0xad,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:128]! +0x24,0xf9,0xbd,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:256]! +0x24,0xf9,0x86,0x01 = vld4.32 {d0, d2, d4, d6}, [r4], r6 +0x24,0xf9,0x96,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:64], r6 +0x24,0xf9,0xa6,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:128], r6 +0x24,0xf9,0xb6,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:256], r6 +0xa4,0xf9,0x8f,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4] +0xa4,0xf9,0x9f,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] +0xa4,0xf9,0xaf,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] +0xa4,0xf9,0x8d,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! +0xa4,0xf9,0x9d,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! +0xa4,0xf9,0xad,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! +0xa4,0xf9,0x86,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 +0xa4,0xf9,0x96,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 +0xa4,0xf9,0xa6,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 +0xa4,0xf9,0xcf,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] +0xa4,0xf9,0xdf,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] +0xa4,0xf9,0xef,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] +0xa4,0xf9,0xcd,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! +0xa4,0xf9,0xdd,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! +0xa4,0xf9,0xed,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! +0xa4,0xf9,0xc6,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 +0xa4,0xf9,0xd6,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 +0xa4,0xf9,0xe6,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 +0xa4,0xf9,0x8f,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4] +0xa4,0xf9,0x9f,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64] +0xa4,0xf9,0xdf,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128] +0xa4,0xf9,0x8d,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4]! +0xa4,0xf9,0x9d,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]! +0xa4,0xf9,0xdd,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]! +0xa4,0xf9,0x86,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4], r6 +0xa4,0xf9,0x96,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64], r6 +0xa4,0xf9,0xd6,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128], r6 +0xa4,0xf9,0xaf,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4] +0xa4,0xf9,0xbf,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64] +0xa4,0xf9,0xff,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128] +0xa4,0xf9,0xad,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4]! +0xa4,0xf9,0xbd,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]! +0xa4,0xf9,0xfd,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]! +0xa4,0xf9,0xa6,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4], r6 +0xa4,0xf9,0xb6,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64], r6 +0xa4,0xf9,0xf6,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r6 +0x04,0xf9,0x0f,0x07 = vst1.8 {d0}, [r4] +0x04,0xf9,0x1f,0x07 = vst1.8 {d0}, [r4:64] +0x04,0xf9,0x0d,0x07 = vst1.8 {d0}, [r4]! +0x04,0xf9,0x1d,0x07 = vst1.8 {d0}, [r4:64]! +0x04,0xf9,0x06,0x07 = vst1.8 {d0}, [r4], r6 +0x04,0xf9,0x16,0x07 = vst1.8 {d0}, [r4:64], r6 +0x04,0xf9,0x0f,0x0a = vst1.8 {d0, d1}, [r4] +0x04,0xf9,0x1f,0x0a = vst1.8 {d0, d1}, [r4:64] +0x04,0xf9,0x2f,0x0a = vst1.8 {d0, d1}, [r4:128] +0x04,0xf9,0x0d,0x0a = vst1.8 {d0, d1}, [r4]! +0x04,0xf9,0x1d,0x0a = vst1.8 {d0, d1}, [r4:64]! +0x04,0xf9,0x2d,0x0a = vst1.8 {d0, d1}, [r4:128]! +0x04,0xf9,0x06,0x0a = vst1.8 {d0, d1}, [r4], r6 +0x04,0xf9,0x16,0x0a = vst1.8 {d0, d1}, [r4:64], r6 +0x04,0xf9,0x26,0x0a = vst1.8 {d0, d1}, [r4:128], r6 +0x04,0xf9,0x0f,0x06 = vst1.8 {d0, d1, d2}, [r4] +0x04,0xf9,0x1f,0x06 = vst1.8 {d0, d1, d2}, [r4:64] +0x04,0xf9,0x0d,0x06 = vst1.8 {d0, d1, d2}, [r4]! +0x04,0xf9,0x1d,0x06 = vst1.8 {d0, d1, d2}, [r4:64]! +0x04,0xf9,0x06,0x06 = vst1.8 {d0, d1, d2}, [r4], r6 +0x04,0xf9,0x16,0x06 = vst1.8 {d0, d1, d2}, [r4:64], r6 +0x04,0xf9,0x0f,0x02 = vst1.8 {d0, d1, d2, d3}, [r4] +0x04,0xf9,0x1f,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:64] +0x04,0xf9,0x2f,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:128] +0x04,0xf9,0x3f,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:256] +0x04,0xf9,0x0d,0x02 = vst1.8 {d0, d1, d2, d3}, [r4]! +0x04,0xf9,0x1d,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:64]! +0x04,0xf9,0x2d,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:128]! +0x04,0xf9,0x3d,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:256]! +0x04,0xf9,0x06,0x02 = vst1.8 {d0, d1, d2, d3}, [r4], r6 +0x04,0xf9,0x16,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:64], r6 +0x04,0xf9,0x26,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:128], r6 +0x04,0xf9,0x36,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:256], r6 +0x84,0xf9,0x4f,0x00 = vst1.8 {d0[2]}, [r4] +0x84,0xf9,0x4d,0x00 = vst1.8 {d0[2]}, [r4]! +0x84,0xf9,0x46,0x00 = vst1.8 {d0[2]}, [r4], r6 +0x04,0xf9,0x4f,0x07 = vst1.16 {d0}, [r4] +0x04,0xf9,0x5f,0x07 = vst1.16 {d0}, [r4:64] +0x04,0xf9,0x4d,0x07 = vst1.16 {d0}, [r4]! +0x04,0xf9,0x5d,0x07 = vst1.16 {d0}, [r4:64]! +0x04,0xf9,0x46,0x07 = vst1.16 {d0}, [r4], r6 +0x04,0xf9,0x56,0x07 = vst1.16 {d0}, [r4:64], r6 +0x04,0xf9,0x4f,0x0a = vst1.16 {d0, d1}, [r4] +0x04,0xf9,0x5f,0x0a = vst1.16 {d0, d1}, [r4:64] +0x04,0xf9,0x6f,0x0a = vst1.16 {d0, d1}, [r4:128] +0x04,0xf9,0x4d,0x0a = vst1.16 {d0, d1}, [r4]! +0x04,0xf9,0x5d,0x0a = vst1.16 {d0, d1}, [r4:64]! +0x04,0xf9,0x6d,0x0a = vst1.16 {d0, d1}, [r4:128]! +0x04,0xf9,0x46,0x0a = vst1.16 {d0, d1}, [r4], r6 +0x04,0xf9,0x56,0x0a = vst1.16 {d0, d1}, [r4:64], r6 +0x04,0xf9,0x66,0x0a = vst1.16 {d0, d1}, [r4:128], r6 +0x04,0xf9,0x4f,0x06 = vst1.16 {d0, d1, d2}, [r4] +0x04,0xf9,0x5f,0x06 = vst1.16 {d0, d1, d2}, [r4:64] +0x04,0xf9,0x4d,0x06 = vst1.16 {d0, d1, d2}, [r4]! +0x04,0xf9,0x5d,0x06 = vst1.16 {d0, d1, d2}, [r4:64]! +0x04,0xf9,0x46,0x06 = vst1.16 {d0, d1, d2}, [r4], r6 +0x04,0xf9,0x56,0x06 = vst1.16 {d0, d1, d2}, [r4:64], r6 +0x04,0xf9,0x4f,0x02 = vst1.16 {d0, d1, d2, d3}, [r4] +0x04,0xf9,0x5f,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:64] +0x04,0xf9,0x6f,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:128] +0x04,0xf9,0x7f,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:256] +0x04,0xf9,0x4d,0x02 = vst1.16 {d0, d1, d2, d3}, [r4]! +0x04,0xf9,0x5d,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:64]! +0x04,0xf9,0x6d,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:128]! +0x04,0xf9,0x7d,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:256]! +0x04,0xf9,0x46,0x02 = vst1.16 {d0, d1, d2, d3}, [r4], r6 +0x04,0xf9,0x56,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:64], r6 +0x04,0xf9,0x66,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:128], r6 +0x04,0xf9,0x76,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:256], r6 +0x84,0xf9,0x8f,0x04 = vst1.16 {d0[2]}, [r4] +0x84,0xf9,0x9f,0x04 = vst1.16 {d0[2]}, [r4:16] +0x84,0xf9,0x8d,0x04 = vst1.16 {d0[2]}, [r4]! +0x84,0xf9,0x9d,0x04 = vst1.16 {d0[2]}, [r4:16]! +0x84,0xf9,0x86,0x04 = vst1.16 {d0[2]}, [r4], r6 +0x84,0xf9,0x96,0x04 = vst1.16 {d0[2]}, [r4:16], r6 +0x04,0xf9,0x8f,0x07 = vst1.32 {d0}, [r4] +0x04,0xf9,0x9f,0x07 = vst1.32 {d0}, [r4:64] +0x04,0xf9,0x8d,0x07 = vst1.32 {d0}, [r4]! +0x04,0xf9,0x9d,0x07 = vst1.32 {d0}, [r4:64]! +0x04,0xf9,0x86,0x07 = vst1.32 {d0}, [r4], r6 +0x04,0xf9,0x96,0x07 = vst1.32 {d0}, [r4:64], r6 +0x04,0xf9,0x8f,0x0a = vst1.32 {d0, d1}, [r4] +0x04,0xf9,0x9f,0x0a = vst1.32 {d0, d1}, [r4:64] +0x04,0xf9,0xaf,0x0a = vst1.32 {d0, d1}, [r4:128] +0x04,0xf9,0x8d,0x0a = vst1.32 {d0, d1}, [r4]! +0x04,0xf9,0x9d,0x0a = vst1.32 {d0, d1}, [r4:64]! +0x04,0xf9,0xad,0x0a = vst1.32 {d0, d1}, [r4:128]! +0x04,0xf9,0x86,0x0a = vst1.32 {d0, d1}, [r4], r6 +0x04,0xf9,0x96,0x0a = vst1.32 {d0, d1}, [r4:64], r6 +0x04,0xf9,0xa6,0x0a = vst1.32 {d0, d1}, [r4:128], r6 +0x04,0xf9,0x8f,0x06 = vst1.32 {d0, d1, d2}, [r4] +0x04,0xf9,0x9f,0x06 = vst1.32 {d0, d1, d2}, [r4:64] +0x04,0xf9,0x8d,0x06 = vst1.32 {d0, d1, d2}, [r4]! +0x04,0xf9,0x9d,0x06 = vst1.32 {d0, d1, d2}, [r4:64]! +0x04,0xf9,0x86,0x06 = vst1.32 {d0, d1, d2}, [r4], r6 +0x04,0xf9,0x96,0x06 = vst1.32 {d0, d1, d2}, [r4:64], r6 +0x04,0xf9,0x8f,0x02 = vst1.32 {d0, d1, d2, d3}, [r4] +0x04,0xf9,0x9f,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:64] +0x04,0xf9,0xaf,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:128] +0x04,0xf9,0xbf,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:256] +0x04,0xf9,0x8d,0x02 = vst1.32 {d0, d1, d2, d3}, [r4]! +0x04,0xf9,0x9d,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:64]! +0x04,0xf9,0xad,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:128]! +0x04,0xf9,0xbd,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:256]! +0x04,0xf9,0x86,0x02 = vst1.32 {d0, d1, d2, d3}, [r4], r6 +0x04,0xf9,0x96,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:64], r6 +0x04,0xf9,0xa6,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:128], r6 +0x04,0xf9,0xb6,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:256], r6 +0x84,0xf9,0x8f,0x08 = vst1.32 {d0[1]}, [r4] +0x84,0xf9,0xbf,0x08 = vst1.32 {d0[1]}, [r4:32] +0x84,0xf9,0x8d,0x08 = vst1.32 {d0[1]}, [r4]! +0x84,0xf9,0xbd,0x08 = vst1.32 {d0[1]}, [r4:32]! +0x84,0xf9,0x86,0x08 = vst1.32 {d0[1]}, [r4], r6 +0x84,0xf9,0xb6,0x08 = vst1.32 {d0[1]}, [r4:32], r6 +0x04,0xf9,0xcf,0x07 = vst1.64 {d0}, [r4] +0x04,0xf9,0xdf,0x07 = vst1.64 {d0}, [r4:64] +0x04,0xf9,0xcd,0x07 = vst1.64 {d0}, [r4]! +0x04,0xf9,0xdd,0x07 = vst1.64 {d0}, [r4:64]! +0x04,0xf9,0xc6,0x07 = vst1.64 {d0}, [r4], r6 +0x04,0xf9,0xd6,0x07 = vst1.64 {d0}, [r4:64], r6 +0x04,0xf9,0xcf,0x0a = vst1.64 {d0, d1}, [r4] +0x04,0xf9,0xdf,0x0a = vst1.64 {d0, d1}, [r4:64] +0x04,0xf9,0xef,0x0a = vst1.64 {d0, d1}, [r4:128] +0x04,0xf9,0xcd,0x0a = vst1.64 {d0, d1}, [r4]! +0x04,0xf9,0xdd,0x0a = vst1.64 {d0, d1}, [r4:64]! +0x04,0xf9,0xed,0x0a = vst1.64 {d0, d1}, [r4:128]! +0x04,0xf9,0xc6,0x0a = vst1.64 {d0, d1}, [r4], r6 +0x04,0xf9,0xd6,0x0a = vst1.64 {d0, d1}, [r4:64], r6 +0x04,0xf9,0xe6,0x0a = vst1.64 {d0, d1}, [r4:128], r6 +0x04,0xf9,0xcf,0x06 = vst1.64 {d0, d1, d2}, [r4] +0x04,0xf9,0xdf,0x06 = vst1.64 {d0, d1, d2}, [r4:64] +0x04,0xf9,0xcd,0x06 = vst1.64 {d0, d1, d2}, [r4]! +0x04,0xf9,0xdd,0x06 = vst1.64 {d0, d1, d2}, [r4:64]! +0x04,0xf9,0xc6,0x06 = vst1.64 {d0, d1, d2}, [r4], r6 +0x04,0xf9,0xd6,0x06 = vst1.64 {d0, d1, d2}, [r4:64], r6 +0x04,0xf9,0xcf,0x02 = vst1.64 {d0, d1, d2, d3}, [r4] +0x04,0xf9,0xdf,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:64] +0x04,0xf9,0xef,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:128] +0x04,0xf9,0xff,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:256] +0x04,0xf9,0xcd,0x02 = vst1.64 {d0, d1, d2, d3}, [r4]! +0x04,0xf9,0xdd,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:64]! +0x04,0xf9,0xed,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:128]! +0x04,0xf9,0xfd,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:256]! +0x04,0xf9,0xc6,0x02 = vst1.64 {d0, d1, d2, d3}, [r4], r6 +0x04,0xf9,0xd6,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:64], r6 +0x04,0xf9,0xe6,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:128], r6 +0x04,0xf9,0xf6,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:256], r6 +0x04,0xf9,0x0f,0x08 = vst2.8 {d0, d1}, [r4] +0x04,0xf9,0x1f,0x08 = vst2.8 {d0, d1}, [r4:64] +0x04,0xf9,0x2f,0x08 = vst2.8 {d0, d1}, [r4:128] +0x04,0xf9,0x0d,0x08 = vst2.8 {d0, d1}, [r4]! +0x04,0xf9,0x1d,0x08 = vst2.8 {d0, d1}, [r4:64]! +0x04,0xf9,0x2d,0x08 = vst2.8 {d0, d1}, [r4:128]! +0x04,0xf9,0x06,0x08 = vst2.8 {d0, d1}, [r4], r6 +0x04,0xf9,0x16,0x08 = vst2.8 {d0, d1}, [r4:64], r6 +0x04,0xf9,0x26,0x08 = vst2.8 {d0, d1}, [r4:128], r6 +0x04,0xf9,0x0f,0x09 = vst2.8 {d0, d2}, [r4] +0x04,0xf9,0x1f,0x09 = vst2.8 {d0, d2}, [r4:64] +0x04,0xf9,0x2f,0x09 = vst2.8 {d0, d2}, [r4:128] +0x04,0xf9,0x0d,0x09 = vst2.8 {d0, d2}, [r4]! +0x04,0xf9,0x1d,0x09 = vst2.8 {d0, d2}, [r4:64]! +0x04,0xf9,0x2d,0x09 = vst2.8 {d0, d2}, [r4:128]! +0x04,0xf9,0x06,0x09 = vst2.8 {d0, d2}, [r4], r6 +0x04,0xf9,0x16,0x09 = vst2.8 {d0, d2}, [r4:64], r6 +0x04,0xf9,0x26,0x09 = vst2.8 {d0, d2}, [r4:128], r6 +0x04,0xf9,0x0f,0x03 = vst2.8 {d0, d1, d2, d3}, [r4] +0x04,0xf9,0x1f,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:64] +0x04,0xf9,0x2f,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:128] +0x04,0xf9,0x3f,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:256] +0x04,0xf9,0x0d,0x03 = vst2.8 {d0, d1, d2, d3}, [r4]! +0x04,0xf9,0x1d,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:64]! +0x04,0xf9,0x2d,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:128]! +0x04,0xf9,0x3d,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:256]! +0x04,0xf9,0x06,0x03 = vst2.8 {d0, d1, d2, d3}, [r4], r6 +0x04,0xf9,0x16,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:64], r6 +0x04,0xf9,0x26,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:128], r6 +0x04,0xf9,0x36,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:256], r6 +0x84,0xf9,0x4f,0x01 = vst2.8 {d0[2], d1[2]}, [r4] +0x84,0xf9,0x5f,0x01 = vst2.8 {d0[2], d1[2]}, [r4:16] +0x84,0xf9,0x4d,0x01 = vst2.8 {d0[2], d1[2]}, [r4]! +0x84,0xf9,0x5d,0x01 = vst2.8 {d0[2], d1[2]}, [r4:16]! +0x84,0xf9,0x46,0x01 = vst2.8 {d0[2], d1[2]}, [r4], r6 +0x84,0xf9,0x56,0x01 = vst2.8 {d0[2], d1[2]}, [r4:16], r6 +0x04,0xf9,0x8f,0x08 = vst2.32 {d0, d1}, [r4] +0x04,0xf9,0x9f,0x08 = vst2.32 {d0, d1}, [r4:64] +0x04,0xf9,0xaf,0x08 = vst2.32 {d0, d1}, [r4:128] +0x04,0xf9,0x8d,0x08 = vst2.32 {d0, d1}, [r4]! +0x04,0xf9,0x9d,0x08 = vst2.32 {d0, d1}, [r4:64]! +0x04,0xf9,0xad,0x08 = vst2.32 {d0, d1}, [r4:128]! +0x04,0xf9,0x86,0x08 = vst2.32 {d0, d1}, [r4], r6 +0x04,0xf9,0x96,0x08 = vst2.32 {d0, d1}, [r4:64], r6 +0x04,0xf9,0xa6,0x08 = vst2.32 {d0, d1}, [r4:128], r6 +0x04,0xf9,0x8f,0x09 = vst2.32 {d0, d2}, [r4] +0x04,0xf9,0x9f,0x09 = vst2.32 {d0, d2}, [r4:64] +0x04,0xf9,0xaf,0x09 = vst2.32 {d0, d2}, [r4:128] +0x04,0xf9,0x8d,0x09 = vst2.32 {d0, d2}, [r4]! +0x04,0xf9,0x9d,0x09 = vst2.32 {d0, d2}, [r4:64]! +0x04,0xf9,0xad,0x09 = vst2.32 {d0, d2}, [r4:128]! +0x04,0xf9,0x86,0x09 = vst2.32 {d0, d2}, [r4], r6 +0x04,0xf9,0x96,0x09 = vst2.32 {d0, d2}, [r4:64], r6 +0x04,0xf9,0xa6,0x09 = vst2.32 {d0, d2}, [r4:128], r6 +0x04,0xf9,0x8f,0x03 = vst2.32 {d0, d1, d2, d3}, [r4] +0x04,0xf9,0x9f,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:64] +0x04,0xf9,0xaf,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:128] +0x04,0xf9,0xbf,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:256] +0x04,0xf9,0x8d,0x03 = vst2.32 {d0, d1, d2, d3}, [r4]! +0x04,0xf9,0x9d,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:64]! +0x04,0xf9,0xad,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:128]! +0x04,0xf9,0xbd,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:256]! +0x04,0xf9,0x86,0x03 = vst2.32 {d0, d1, d2, d3}, [r4], r6 +0x04,0xf9,0x96,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:64], r6 +0x04,0xf9,0xa6,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:128], r6 +0x04,0xf9,0xb6,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:256], r6 +0x84,0xf9,0x8f,0x09 = vst2.32 {d0[1], d1[1]}, [r4] +0x84,0xf9,0x9f,0x09 = vst2.32 {d0[1], d1[1]}, [r4:64] +0x84,0xf9,0x8d,0x09 = vst2.32 {d0[1], d1[1]}, [r4]! +0x84,0xf9,0x9d,0x09 = vst2.32 {d0[1], d1[1]}, [r4:64]! +0x84,0xf9,0x86,0x09 = vst2.32 {d0[1], d1[1]}, [r4], r6 +0x84,0xf9,0x96,0x09 = vst2.32 {d0[1], d1[1]}, [r4:64], r6 +0x84,0xf9,0xcf,0x09 = vst2.32 {d0[1], d2[1]}, [r4] +0x84,0xf9,0xdf,0x09 = vst2.32 {d0[1], d2[1]}, [r4:64] +0x84,0xf9,0xcd,0x09 = vst2.32 {d0[1], d2[1]}, [r4]! +0x84,0xf9,0xdd,0x09 = vst2.32 {d0[1], d2[1]}, [r4:64]! +0x84,0xf9,0xc6,0x09 = vst2.32 {d0[1], d2[1]}, [r4], r6 +0x84,0xf9,0xd6,0x09 = vst2.32 {d0[1], d2[1]}, [r4:64], r6 +0x04,0xf9,0x0f,0x04 = vst3.8 {d0, d1, d2}, [r4] +0x04,0xf9,0x1f,0x04 = vst3.8 {d0, d1, d2}, [r4:64] +0x04,0xf9,0x0d,0x04 = vst3.8 {d0, d1, d2}, [r4]! +0x04,0xf9,0x1d,0x04 = vst3.8 {d0, d1, d2}, [r4:64]! +0x04,0xf9,0x06,0x04 = vst3.8 {d0, d1, d2}, [r4], r6 +0x04,0xf9,0x16,0x04 = vst3.8 {d0, d1, d2}, [r4:64], r6 +0x04,0xf9,0x0f,0x05 = vst3.8 {d0, d2, d4}, [r4] +0x04,0xf9,0x1f,0x05 = vst3.8 {d0, d2, d4}, [r4:64] +0x04,0xf9,0x0d,0x05 = vst3.8 {d0, d2, d4}, [r4]! +0x04,0xf9,0x1d,0x05 = vst3.8 {d0, d2, d4}, [r4:64]! +0x04,0xf9,0x06,0x05 = vst3.8 {d0, d2, d4}, [r4], r6 +0x04,0xf9,0x16,0x05 = vst3.8 {d0, d2, d4}, [r4:64], r6 +0x84,0xf9,0x2f,0x02 = vst3.8 {d0[1], d1[1], d2[1]}, [r4] +0x84,0xf9,0x2d,0x02 = vst3.8 {d0[1], d1[1], d2[1]}, [r4]! +0x84,0xf9,0x26,0x02 = vst3.8 {d0[1], d1[1], d2[1]}, [r4], r6 +0x04,0xf9,0x4f,0x04 = vst3.16 {d0, d1, d2}, [r4] +0x04,0xf9,0x5f,0x04 = vst3.16 {d0, d1, d2}, [r4:64] +0x04,0xf9,0x4d,0x04 = vst3.16 {d0, d1, d2}, [r4]! +0x04,0xf9,0x5d,0x04 = vst3.16 {d0, d1, d2}, [r4:64]! +0x04,0xf9,0x46,0x04 = vst3.16 {d0, d1, d2}, [r4], r6 +0x04,0xf9,0x56,0x04 = vst3.16 {d0, d1, d2}, [r4:64], r6 +0x04,0xf9,0x4f,0x05 = vst3.16 {d0, d2, d4}, [r4] +0x04,0xf9,0x5f,0x05 = vst3.16 {d0, d2, d4}, [r4:64] +0x04,0xf9,0x4d,0x05 = vst3.16 {d0, d2, d4}, [r4]! +0x04,0xf9,0x5d,0x05 = vst3.16 {d0, d2, d4}, [r4:64]! +0x04,0xf9,0x46,0x05 = vst3.16 {d0, d2, d4}, [r4], r6 +0x04,0xf9,0x56,0x05 = vst3.16 {d0, d2, d4}, [r4:64], r6 +0x84,0xf9,0x4f,0x06 = vst3.16 {d0[1], d1[1], d2[1]}, [r4] +0x84,0xf9,0x4d,0x06 = vst3.16 {d0[1], d1[1], d2[1]}, [r4]! +0x84,0xf9,0x46,0x06 = vst3.16 {d0[1], d1[1], d2[1]}, [r4], r6 +0x84,0xf9,0x6f,0x06 = vst3.16 {d0[1], d2[1], d4[1]}, [r4] +0x84,0xf9,0x6d,0x06 = vst3.16 {d0[1], d2[1], d4[1]}, [r4]! +0x84,0xf9,0x66,0x06 = vst3.16 {d0[1], d2[1], d4[1]}, [r4], r6 +0x04,0xf9,0x8f,0x04 = vst3.32 {d0, d1, d2}, [r4] +0x04,0xf9,0x9f,0x04 = vst3.32 {d0, d1, d2}, [r4:64] +0x04,0xf9,0x8d,0x04 = vst3.32 {d0, d1, d2}, [r4]! +0x04,0xf9,0x9d,0x04 = vst3.32 {d0, d1, d2}, [r4:64]! +0x04,0xf9,0x86,0x04 = vst3.32 {d0, d1, d2}, [r4], r6 +0x04,0xf9,0x96,0x04 = vst3.32 {d0, d1, d2}, [r4:64], r6 +0x04,0xf9,0x8f,0x05 = vst3.32 {d0, d2, d4}, [r4] +0x04,0xf9,0x9f,0x05 = vst3.32 {d0, d2, d4}, [r4:64] +0x04,0xf9,0x8d,0x05 = vst3.32 {d0, d2, d4}, [r4]! +0x04,0xf9,0x9d,0x05 = vst3.32 {d0, d2, d4}, [r4:64]! +0x04,0xf9,0x86,0x05 = vst3.32 {d0, d2, d4}, [r4], r6 +0x04,0xf9,0x96,0x05 = vst3.32 {d0, d2, d4}, [r4:64], r6 +0x84,0xf9,0x8f,0x0a = vst3.32 {d0[1], d1[1], d2[1]}, [r4] +0x84,0xf9,0x8d,0x0a = vst3.32 {d0[1], d1[1], d2[1]}, [r4]! +0x84,0xf9,0x86,0x0a = vst3.32 {d0[1], d1[1], d2[1]}, [r4], r6 +0x84,0xf9,0xcf,0x0a = vst3.32 {d0[1], d2[1], d4[1]}, [r4] +0x84,0xf9,0xcd,0x0a = vst3.32 {d0[1], d2[1], d4[1]}, [r4]! +0x84,0xf9,0xc6,0x0a = vst3.32 {d0[1], d2[1], d4[1]}, [r4], r6 +0x04,0xf9,0x0f,0x00 = vst4.8 {d0, d1, d2, d3}, [r4] +0x04,0xf9,0x1f,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:64] +0x04,0xf9,0x2f,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:128] +0x04,0xf9,0x3f,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:256] +0x04,0xf9,0x0d,0x00 = vst4.8 {d0, d1, d2, d3}, [r4]! +0x04,0xf9,0x1d,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:64]! +0x04,0xf9,0x2d,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:128]! +0x04,0xf9,0x3d,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:256]! +0x04,0xf9,0x06,0x00 = vst4.8 {d0, d1, d2, d3}, [r4], r6 +0x04,0xf9,0x16,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:64], r6 +0x04,0xf9,0x26,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:128], r6 +0x04,0xf9,0x36,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:256], r6 +0x04,0xf9,0x0f,0x01 = vst4.8 {d0, d2, d4, d6}, [r4] +0x04,0xf9,0x1f,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:64] +0x04,0xf9,0x2f,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:128] +0x04,0xf9,0x3f,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:256] +0x04,0xf9,0x0d,0x01 = vst4.8 {d0, d2, d4, d6}, [r4]! +0x04,0xf9,0x1d,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:64]! +0x04,0xf9,0x2d,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:128]! +0x04,0xf9,0x3d,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:256]! +0x04,0xf9,0x06,0x01 = vst4.8 {d0, d2, d4, d6}, [r4], r6 +0x04,0xf9,0x16,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:64], r6 +0x04,0xf9,0x26,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:128], r6 +0x04,0xf9,0x36,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:256], r6 +0x84,0xf9,0x2f,0x03 = vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4] +0x84,0xf9,0x3f,0x03 = vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] +0x84,0xf9,0x2d,0x03 = vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]! +0x84,0xf9,0x3d,0x03 = vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! +0x84,0xf9,0x26,0x03 = vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 +0x84,0xf9,0x36,0x03 = vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 +0x04,0xf9,0x4f,0x00 = vst4.16 {d0, d1, d2, d3}, [r4] +0x04,0xf9,0x5f,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:64] +0x04,0xf9,0x6f,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:128] +0x04,0xf9,0x7f,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:256] +0x04,0xf9,0x4d,0x00 = vst4.16 {d0, d1, d2, d3}, [r4]! +0x04,0xf9,0x5d,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:64]! +0x04,0xf9,0x6d,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:128]! +0x04,0xf9,0x7d,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:256]! +0x04,0xf9,0x46,0x00 = vst4.16 {d0, d1, d2, d3}, [r4], r6 +0x04,0xf9,0x56,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:64], r6 +0x04,0xf9,0x66,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:128], r6 +0x04,0xf9,0x76,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:256], r6 +0x04,0xf9,0x4f,0x01 = vst4.16 {d0, d2, d4, d6}, [r4] +0x04,0xf9,0x5f,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:64] +0x04,0xf9,0x6f,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:128] +0x04,0xf9,0x7f,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:256] +0x04,0xf9,0x4d,0x01 = vst4.16 {d0, d2, d4, d6}, [r4]! +0x04,0xf9,0x5d,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:64]! +0x04,0xf9,0x6d,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:128]! +0x04,0xf9,0x7d,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:256]! +0x04,0xf9,0x46,0x01 = vst4.16 {d0, d2, d4, d6}, [r4], r6 +0x04,0xf9,0x56,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:64], r6 +0x04,0xf9,0x66,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:128], r6 +0x04,0xf9,0x76,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:256], r6 +0x84,0xf9,0x4f,0x07 = vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4] +0x84,0xf9,0x5f,0x07 = vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] +0x84,0xf9,0x4d,0x07 = vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! +0x84,0xf9,0x5d,0x07 = vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! +0x84,0xf9,0x46,0x07 = vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 +0x84,0xf9,0x56,0x07 = vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 +0x84,0xf9,0x6f,0x07 = vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4] +0x84,0xf9,0x7f,0x07 = vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] +0x84,0xf9,0x6d,0x07 = vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]! +0x84,0xf9,0x7d,0x07 = vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! +0x84,0xf9,0x66,0x07 = vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 +0x84,0xf9,0x76,0x07 = vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 +0x04,0xf9,0x8f,0x00 = vst4.32 {d0, d1, d2, d3}, [r4] +0x04,0xf9,0x9f,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:64] +0x04,0xf9,0xaf,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:128] +0x04,0xf9,0xbf,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:256] +0x04,0xf9,0x8d,0x00 = vst4.32 {d0, d1, d2, d3}, [r4]! +0x04,0xf9,0x9d,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:64]! +0x04,0xf9,0xad,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:128]! +0x04,0xf9,0xbd,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:256]! +0x04,0xf9,0x86,0x00 = vst4.32 {d0, d1, d2, d3}, [r4], r6 +0x04,0xf9,0x96,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:64], r6 +0x04,0xf9,0xa6,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:128], r6 +0x04,0xf9,0xb6,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:256], r6 +0x04,0xf9,0x8f,0x01 = vst4.32 {d0, d2, d4, d6}, [r4] +0x04,0xf9,0x9f,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:64] +0x04,0xf9,0xaf,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:128] +0x04,0xf9,0xbf,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:256] +0x04,0xf9,0x8d,0x01 = vst4.32 {d0, d2, d4, d6}, [r4]! +0x04,0xf9,0x9d,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:64]! +0x04,0xf9,0xad,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:128]! +0x04,0xf9,0xbd,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:256]! +0x04,0xf9,0x86,0x01 = vst4.32 {d0, d2, d4, d6}, [r4], r6 +0x04,0xf9,0x96,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:64], r6 +0x04,0xf9,0xa6,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:128], r6 +0x04,0xf9,0xb6,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:256], r6 +0x84,0xf9,0x8f,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4] +0x84,0xf9,0x9f,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] +0x84,0xf9,0xaf,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] +0x84,0xf9,0x8d,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! +0x84,0xf9,0x9d,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! +0x84,0xf9,0xad,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! +0x84,0xf9,0x86,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 +0x84,0xf9,0x96,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 +0x84,0xf9,0xa6,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 +0x84,0xf9,0xcf,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] +0x84,0xf9,0xdf,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] +0x84,0xf9,0xef,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] +0x84,0xf9,0xcd,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! +0x84,0xf9,0xdd,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! +0x84,0xf9,0xed,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! +0x84,0xf9,0xc6,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 +0x84,0xf9,0xd6,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 +0x84,0xf9,0xe6,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 +0x84,0xf9,0x8d,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! +0x84,0xf9,0x9d,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! +0x84,0xf9,0xad,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! +0x84,0xf9,0x86,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 +0x84,0xf9,0x96,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 +0x84,0xf9,0xa6,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 +0x84,0xf9,0xcf,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] +0x84,0xf9,0xdf,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] +0x84,0xf9,0xef,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] +0x84,0xf9,0xcd,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! +0x84,0xf9,0xdd,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! +0x84,0xf9,0xed,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! +0x84,0xf9,0xc6,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 +0x84,0xf9,0xd6,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 +0x84,0xf9,0xe6,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 diff --git a/thirdparty/capstone/suite/MC/ARM/neon-vst-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-vst-encoding.s.cs new file mode 100644 index 0000000..db04fa2 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-vst-encoding.s.cs @@ -0,0 +1,120 @@ +# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None +0x1f,0x07,0x40,0xf4 = vst1.8 {d16}, [r0:64] +0x4f,0x07,0x40,0xf4 = vst1.16 {d16}, [r0] +0x8f,0x07,0x40,0xf4 = vst1.32 {d16}, [r0] +0xcf,0x07,0x40,0xf4 = vst1.64 {d16}, [r0] +0x1f,0x0a,0x40,0xf4 = vst1.8 {d16, d17}, [r0:64] +0x6f,0x0a,0x40,0xf4 = vst1.16 {d16, d17}, [r0:128] +0x8f,0x0a,0x40,0xf4 = vst1.32 {d16, d17}, [r0] +0xcf,0x0a,0x40,0xf4 = vst1.64 {d16, d17}, [r0] +0x1f,0x06,0x40,0xf4 = vst1.8 {d16, d17, d18}, [r0:64] +0x1d,0x06,0x40,0xf4 = vst1.8 {d16, d17, d18}, [r0:64]! +0x03,0x06,0x40,0xf4 = vst1.8 {d16, d17, d18}, [r0], r3 +0x1f,0x02,0x40,0xf4 = vst1.8 {d16, d17, d18, d19}, [r0:64] +0x5d,0x02,0x41,0xf4 = vst1.16 {d16, d17, d18, d19}, [r1:64]! +0xc2,0x02,0x43,0xf4 = vst1.64 {d16, d17, d18, d19}, [r3], r2 +0x1f,0x08,0x40,0xf4 = vst2.8 {d16, d17}, [r0:64] +0x6f,0x08,0x40,0xf4 = vst2.16 {d16, d17}, [r0:128] +0x8f,0x08,0x40,0xf4 = vst2.32 {d16, d17}, [r0] +0x1f,0x03,0x40,0xf4 = vst2.8 {d16, d17, d18, d19}, [r0:64] +0x6f,0x03,0x40,0xf4 = vst2.16 {d16, d17, d18, d19}, [r0:128] +0xbf,0x03,0x40,0xf4 = vst2.32 {d16, d17, d18, d19}, [r0:256] +0x1d,0x08,0x40,0xf4 = vst2.8 {d16, d17}, [r0:64]! +0x6d,0xe8,0x40,0xf4 = vst2.16 {d30, d31}, [r0:128]! +0x8d,0xe8,0x00,0xf4 = vst2.32 {d14, d15}, [r0]! +0x1d,0x03,0x40,0xf4 = vst2.8 {d16, d17, d18, d19}, [r0:64]! +0x6d,0x23,0x40,0xf4 = vst2.16 {d18, d19, d20, d21}, [r0:128]! +0xbd,0x83,0x00,0xf4 = vst2.32 {d8, d9, d10, d11}, [r0:256]! +0x0f,0x04,0x41,0xf4 = vst3.8 {d16, d17, d18}, [r1] +0x4f,0x64,0x02,0xf4 = vst3.16 {d6, d7, d8}, [r2] +0x8f,0x14,0x03,0xf4 = vst3.32 {d1, d2, d3}, [r3] +0x1f,0x05,0x40,0xf4 = vst3.8 {d16, d18, d20}, [r0:64] +0x4f,0xb5,0x44,0xf4 = vst3.16 {d27, d29, d31}, [r4] +0x8f,0x65,0x05,0xf4 = vst3.32 {d6, d8, d10}, [r5] +0x01,0xc4,0x06,0xf4 = vst3.8 {d12, d13, d14}, [r6], r1 +0x42,0xb4,0x07,0xf4 = vst3.16 {d11, d12, d13}, [r7], r2 +0x83,0x24,0x08,0xf4 = vst3.32 {d2, d3, d4}, [r8], r3 +0x04,0x45,0x09,0xf4 = vst3.8 {d4, d6, d8}, [r9], r4 +0x44,0xe5,0x09,0xf4 = vst3.16 {d14, d16, d18}, [r9], r4 +0x85,0x05,0x4a,0xf4 = vst3.32 {d16, d18, d20}, [r10], r5 +0x0d,0x64,0x08,0xf4 = vst3.8 {d6, d7, d8}, [r8]! +0x4d,0x94,0x07,0xf4 = vst3.16 {d9, d10, d11}, [r7]! +0x8d,0x14,0x06,0xf4 = vst3.32 {d1, d2, d3}, [r6]! +0x1d,0x05,0x40,0xf4 = vst3.8 {d16, d18, d20}, [r0:64]! +0x4d,0x45,0x45,0xf4 = vst3.16 {d20, d22, d24}, [r5]! +0x8d,0x55,0x04,0xf4 = vst3.32 {d5, d7, d9}, [r4]! +0x1f,0x00,0x41,0xf4 = vst4.8 {d16, d17, d18, d19}, [r1:64] +0x6f,0x00,0x42,0xf4 = vst4.16 {d16, d17, d18, d19}, [r2:128] +0xbf,0x00,0x43,0xf4 = vst4.32 {d16, d17, d18, d19}, [r3:256] +0x3f,0x11,0x45,0xf4 = vst4.8 {d17, d19, d21, d23}, [r5:256] +0x4f,0x11,0x47,0xf4 = vst4.16 {d17, d19, d21, d23}, [r7] +0x8f,0x01,0x48,0xf4 = vst4.32 {d16, d18, d20, d22}, [r8] +0x1d,0x00,0x41,0xf4 = vst4.8 {d16, d17, d18, d19}, [r1:64]! +0x6d,0x00,0x42,0xf4 = vst4.16 {d16, d17, d18, d19}, [r2:128]! +0xbd,0x00,0x43,0xf4 = vst4.32 {d16, d17, d18, d19}, [r3:256]! +0x3d,0x11,0x45,0xf4 = vst4.8 {d17, d19, d21, d23}, [r5:256]! +0x4d,0x11,0x47,0xf4 = vst4.16 {d17, d19, d21, d23}, [r7]! +0x8d,0x01,0x48,0xf4 = vst4.32 {d16, d18, d20, d22}, [r8]! +0x18,0x00,0x41,0xf4 = vst4.8 {d16, d17, d18, d19}, [r1:64], r8 +0x47,0x00,0x42,0xf4 = vst4.16 {d16, d17, d18, d19}, [r2], r7 +0x95,0x00,0x43,0xf4 = vst4.32 {d16, d17, d18, d19}, [r3:64], r5 +0x32,0x01,0x44,0xf4 = vst4.8 {d16, d18, d20, d22}, [r4:256], r2 +0x43,0x01,0x46,0xf4 = vst4.16 {d16, d18, d20, d22}, [r6], r3 +0x84,0x11,0x49,0xf4 = vst4.32 {d17, d19, d21, d23}, [r9], r4 +0x3f,0x01,0xc0,0xf4 = vst2.8 {d16[1], d17[1]}, [r0:16] +0x5f,0x05,0xc0,0xf4 = vst2.16 {d16[1], d17[1]}, [r0:32] +0x8f,0x09,0xc0,0xf4 = vst2.32 {d16[1], d17[1]}, [r0] +0x6f,0x15,0xc0,0xf4 = vst2.16 {d17[1], d19[1]}, [r0] +0x5f,0x19,0xc0,0xf4 = vst2.32 {d17[0], d19[0]}, [r0:64] +0x83,0x21,0x82,0xf4 = vst2.8 {d2[4], d3[4]}, [r2], r3 +0x8d,0x21,0x82,0xf4 = vst2.8 {d2[4], d3[4]}, [r2]! +0x8f,0x21,0x82,0xf4 = vst2.8 {d2[4], d3[4]}, [r2] +0x6f,0x15,0xc0,0xf4 = vst2.16 {d17[1], d19[1]}, [r0] +0x5f,0x19,0xc0,0xf4 = vst2.32 {d17[0], d19[0]}, [r0:64] +0x6d,0x75,0x81,0xf4 = vst2.16 {d7[1], d9[1]}, [r1]! +0x5d,0x69,0x82,0xf4 = vst2.32 {d6[0], d8[0]}, [r2:64]! +0x65,0x25,0x83,0xf4 = vst2.16 {d2[1], d4[1]}, [r3], r5 +0x57,0x59,0x84,0xf4 = vst2.32 {d5[0], d7[0]}, [r4:64], r7 +0x2f,0x02,0xc1,0xf4 = vst3.8 {d16[1], d17[1], d18[1]}, [r1] +0x4f,0x66,0x82,0xf4 = vst3.16 {d6[1], d7[1], d8[1]}, [r2] +0x8f,0x1a,0x83,0xf4 = vst3.32 {d1[1], d2[1], d3[1]}, [r3] +0x6f,0xb6,0xc4,0xf4 = vst3.16 {d27[1], d29[1], d31[1]}, [r4] +0xcf,0x6a,0x85,0xf4 = vst3.32 {d6[1], d8[1], d10[1]}, [r5] +0x21,0xc2,0x86,0xf4 = vst3.8 {d12[1], d13[1], d14[1]}, [r6], r1 +0x42,0xb6,0x87,0xf4 = vst3.16 {d11[1], d12[1], d13[1]}, [r7], r2 +0x83,0x2a,0x88,0xf4 = vst3.32 {d2[1], d3[1], d4[1]}, [r8], r3 +0x64,0xe6,0x89,0xf4 = vst3.16 {d14[1], d16[1], d18[1]}, [r9], r4 +0xc5,0x0a,0xca,0xf4 = vst3.32 {d16[1], d18[1], d20[1]}, [r10], r5 +0x2d,0x62,0x88,0xf4 = vst3.8 {d6[1], d7[1], d8[1]}, [r8]! +0x4d,0x96,0x87,0xf4 = vst3.16 {d9[1], d10[1], d11[1]}, [r7]! +0x8d,0x1a,0x86,0xf4 = vst3.32 {d1[1], d2[1], d3[1]}, [r6]! +0x6d,0x46,0xc5,0xf4 = vst3.16 {d20[1], d22[1], d24[1]}, [r5]! +0xcd,0x5a,0x84,0xf4 = vst3.32 {d5[1], d7[1], d9[1]}, [r4]! +0x2f,0x03,0xc1,0xf4 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1] +0x4f,0x07,0xc2,0xf4 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2] +0x8f,0x0b,0xc3,0xf4 = vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] +0x6f,0x17,0xc7,0xf4 = vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] +0xcf,0x0b,0xc8,0xf4 = vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] +0x3d,0x03,0xc1,0xf4 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! +0x5d,0x07,0xc2,0xf4 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]! +0xad,0x0b,0xc3,0xf4 = vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]! +0x6d,0x17,0xc7,0xf4 = vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]! +0xcd,0x0b,0xc8,0xf4 = vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! +0x38,0x03,0xc1,0xf4 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8 +0x47,0x07,0xc2,0xf4 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 +0x95,0x0b,0xc3,0xf4 = vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5 +0x63,0x07,0xc6,0xf4 = vst4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 +0xc4,0x1b,0xc9,0xf4 = vst4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 +0x0f,0x27,0x02,0xf4 = vst1.8 {d2}, [r2] +0x0f,0x27,0x02,0xf4 = vst1.8 {d2}, [r2] +0x0f,0x27,0x02,0xf4 = vst1.8 {d2}, [r2] +0x0f,0x4a,0x02,0xf4 = vst1.8 {d4, d5}, [r2] +0x0f,0x4a,0x02,0xf4 = vst1.8 {d4, d5}, [r2] +0x0f,0x4a,0x02,0xf4 = vst1.8 {d4, d5}, [r2] +0x8f,0x4a,0x02,0xf4 = vst1.32 {d4, d5}, [r2] +0x0f,0x89,0x04,0xf4 = vst2.8 {d8, d10}, [r4] +0xbf,0x98,0x83,0xf4 = vst1.32 {d9[1]}, [r3:32] +0xbd,0xb8,0xc9,0xf4 = vst1.32 {d27[1]}, [r9:32]! +0xb5,0xb8,0xc3,0xf4 = vst1.32 {d27[1]}, [r3:32], r5 +0x1f,0x08,0x40,0xf4 = vst2.8 {d16, d17}, [r0:64] +0x6f,0x08,0x40,0xf4 = vst2.16 {d16, d17}, [r0:128] diff --git a/thirdparty/capstone/suite/MC/ARM/neon-vswp.s.cs b/thirdparty/capstone/suite/MC/ARM/neon-vswp.s.cs new file mode 100644 index 0000000..bf5ea6c --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neon-vswp.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x02,0x10,0xb2,0xf3 = vswp d1, d2 +0x44,0x20,0xb2,0xf3 = vswp q1, q2 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-abs-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-abs-encoding.s.cs new file mode 100644 index 0000000..fc2386a --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-abs-encoding.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xf1,0xff,0x20,0x03 = vabs.s8 d16, d16 +0xf5,0xff,0x20,0x03 = vabs.s16 d16, d16 +0xf9,0xff,0x20,0x03 = vabs.s32 d16, d16 +0xf9,0xff,0x20,0x07 = vabs.f32 d16, d16 +0xf1,0xff,0x60,0x03 = vabs.s8 q8, q8 +0xf5,0xff,0x60,0x03 = vabs.s16 q8, q8 +0xf9,0xff,0x60,0x03 = vabs.s32 q8, q8 +0xf9,0xff,0x60,0x07 = vabs.f32 q8, q8 +0xf0,0xff,0x20,0x07 = vqabs.s8 d16, d16 +0xf4,0xff,0x20,0x07 = vqabs.s16 d16, d16 +0xf8,0xff,0x20,0x07 = vqabs.s32 d16, d16 +0xf0,0xff,0x60,0x07 = vqabs.s8 q8, q8 +0xf4,0xff,0x60,0x07 = vqabs.s16 q8, q8 +0xf8,0xff,0x60,0x07 = vqabs.s32 q8, q8 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-absdiff-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-absdiff-encoding.s.cs new file mode 100644 index 0000000..e1efa77 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-absdiff-encoding.s.cs @@ -0,0 +1,39 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x40,0xef,0xa1,0x07 = vabd.s8 d16, d16, d17 +0x50,0xef,0xa1,0x07 = vabd.s16 d16, d16, d17 +0x60,0xef,0xa1,0x07 = vabd.s32 d16, d16, d17 +0x40,0xff,0xa1,0x07 = vabd.u8 d16, d16, d17 +0x50,0xff,0xa1,0x07 = vabd.u16 d16, d16, d17 +0x60,0xff,0xa1,0x07 = vabd.u32 d16, d16, d17 +0x60,0xff,0xa1,0x0d = vabd.f32 d16, d16, d17 +0x40,0xef,0xe2,0x07 = vabd.s8 q8, q8, q9 +0x50,0xef,0xe2,0x07 = vabd.s16 q8, q8, q9 +0x60,0xef,0xe2,0x07 = vabd.s32 q8, q8, q9 +0x40,0xff,0xe2,0x07 = vabd.u8 q8, q8, q9 +0x50,0xff,0xe2,0x07 = vabd.u16 q8, q8, q9 +0x60,0xff,0xe2,0x07 = vabd.u32 q8, q8, q9 +0x60,0xff,0xe2,0x0d = vabd.f32 q8, q8, q9 +0xc0,0xef,0xa1,0x07 = vabdl.s8 q8, d16, d17 +0xd0,0xef,0xa1,0x07 = vabdl.s16 q8, d16, d17 +0xe0,0xef,0xa1,0x07 = vabdl.s32 q8, d16, d17 +0xc0,0xff,0xa1,0x07 = vabdl.u8 q8, d16, d17 +0xd0,0xff,0xa1,0x07 = vabdl.u16 q8, d16, d17 +0xe0,0xff,0xa1,0x07 = vabdl.u32 q8, d16, d17 +0x42,0xef,0xb1,0x07 = vaba.s8 d16, d18, d17 +0x52,0xef,0xb1,0x07 = vaba.s16 d16, d18, d17 +0x62,0xef,0xb1,0x07 = vaba.s32 d16, d18, d17 +0x42,0xff,0xb1,0x07 = vaba.u8 d16, d18, d17 +0x52,0xff,0xb1,0x07 = vaba.u16 d16, d18, d17 +0x62,0xff,0xb1,0x07 = vaba.u32 d16, d18, d17 +0x40,0xef,0xf4,0x27 = vaba.s8 q9, q8, q10 +0x50,0xef,0xf4,0x27 = vaba.s16 q9, q8, q10 +0x60,0xef,0xf4,0x27 = vaba.s32 q9, q8, q10 +0x40,0xff,0xf4,0x27 = vaba.u8 q9, q8, q10 +0x50,0xff,0xf4,0x27 = vaba.u16 q9, q8, q10 +0x60,0xff,0xf4,0x27 = vaba.u32 q9, q8, q10 +0xc3,0xef,0xa2,0x05 = vabal.s8 q8, d19, d18 +0xd3,0xef,0xa2,0x05 = vabal.s16 q8, d19, d18 +0xe3,0xef,0xa2,0x05 = vabal.s32 q8, d19, d18 +0xc3,0xff,0xa2,0x05 = vabal.u8 q8, d19, d18 +0xd3,0xff,0xa2,0x05 = vabal.u16 q8, d19, d18 +0xe3,0xff,0xa2,0x05 = vabal.u32 q8, d19, d18 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-add-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-add-encoding.s.cs new file mode 100644 index 0000000..3a67385 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-add-encoding.s.cs @@ -0,0 +1,65 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x41,0xef,0xa0,0x08 = vadd.i8 d16, d17, d16 +0x51,0xef,0xa0,0x08 = vadd.i16 d16, d17, d16 +0x71,0xef,0xa0,0x08 = vadd.i64 d16, d17, d16 +0x61,0xef,0xa0,0x08 = vadd.i32 d16, d17, d16 +0x40,0xef,0xa1,0x0d = vadd.f32 d16, d16, d17 +0x40,0xef,0xe2,0x0d = vadd.f32 q8, q8, q9 +0xc1,0xef,0xa0,0x00 = vaddl.s8 q8, d17, d16 +0xd1,0xef,0xa0,0x00 = vaddl.s16 q8, d17, d16 +0xe1,0xef,0xa0,0x00 = vaddl.s32 q8, d17, d16 +0xc1,0xff,0xa0,0x00 = vaddl.u8 q8, d17, d16 +0xd1,0xff,0xa0,0x00 = vaddl.u16 q8, d17, d16 +0xe1,0xff,0xa0,0x00 = vaddl.u32 q8, d17, d16 +0xc0,0xef,0xa2,0x01 = vaddw.s8 q8, q8, d18 +0xd0,0xef,0xa2,0x01 = vaddw.s16 q8, q8, d18 +0xe0,0xef,0xa2,0x01 = vaddw.s32 q8, q8, d18 +0xc0,0xff,0xa2,0x01 = vaddw.u8 q8, q8, d18 +0xd0,0xff,0xa2,0x01 = vaddw.u16 q8, q8, d18 +0xe0,0xff,0xa2,0x01 = vaddw.u32 q8, q8, d18 +0x40,0xef,0xa1,0x00 = vhadd.s8 d16, d16, d17 +0x50,0xef,0xa1,0x00 = vhadd.s16 d16, d16, d17 +0x60,0xef,0xa1,0x00 = vhadd.s32 d16, d16, d17 +0x40,0xff,0xa1,0x00 = vhadd.u8 d16, d16, d17 +0x50,0xff,0xa1,0x00 = vhadd.u16 d16, d16, d17 +0x60,0xff,0xa1,0x00 = vhadd.u32 d16, d16, d17 +0x40,0xef,0xe2,0x00 = vhadd.s8 q8, q8, q9 +0x50,0xef,0xe2,0x00 = vhadd.s16 q8, q8, q9 +0x60,0xef,0xe2,0x00 = vhadd.s32 q8, q8, q9 +0x40,0xff,0xe2,0x00 = vhadd.u8 q8, q8, q9 +0x50,0xff,0xe2,0x00 = vhadd.u16 q8, q8, q9 +0x60,0xff,0xe2,0x00 = vhadd.u32 q8, q8, q9 +0x40,0xef,0xa1,0x01 = vrhadd.s8 d16, d16, d17 +0x50,0xef,0xa1,0x01 = vrhadd.s16 d16, d16, d17 +0x60,0xef,0xa1,0x01 = vrhadd.s32 d16, d16, d17 +0x40,0xff,0xa1,0x01 = vrhadd.u8 d16, d16, d17 +0x50,0xff,0xa1,0x01 = vrhadd.u16 d16, d16, d17 +0x60,0xff,0xa1,0x01 = vrhadd.u32 d16, d16, d17 +0x40,0xef,0xe2,0x01 = vrhadd.s8 q8, q8, q9 +0x50,0xef,0xe2,0x01 = vrhadd.s16 q8, q8, q9 +0x60,0xef,0xe2,0x01 = vrhadd.s32 q8, q8, q9 +0x40,0xff,0xe2,0x01 = vrhadd.u8 q8, q8, q9 +0x50,0xff,0xe2,0x01 = vrhadd.u16 q8, q8, q9 +0x60,0xff,0xe2,0x01 = vrhadd.u32 q8, q8, q9 +0x40,0xef,0xb1,0x00 = vqadd.s8 d16, d16, d17 +0x50,0xef,0xb1,0x00 = vqadd.s16 d16, d16, d17 +0x60,0xef,0xb1,0x00 = vqadd.s32 d16, d16, d17 +0x70,0xef,0xb1,0x00 = vqadd.s64 d16, d16, d17 +0x40,0xff,0xb1,0x00 = vqadd.u8 d16, d16, d17 +0x50,0xff,0xb1,0x00 = vqadd.u16 d16, d16, d17 +0x60,0xff,0xb1,0x00 = vqadd.u32 d16, d16, d17 +0x70,0xff,0xb1,0x00 = vqadd.u64 d16, d16, d17 +0x40,0xef,0xf2,0x00 = vqadd.s8 q8, q8, q9 +0x50,0xef,0xf2,0x00 = vqadd.s16 q8, q8, q9 +0x60,0xef,0xf2,0x00 = vqadd.s32 q8, q8, q9 +0x70,0xef,0xf2,0x00 = vqadd.s64 q8, q8, q9 +0x40,0xff,0xf2,0x00 = vqadd.u8 q8, q8, q9 +0x50,0xff,0xf2,0x00 = vqadd.u16 q8, q8, q9 +0x60,0xff,0xf2,0x00 = vqadd.u32 q8, q8, q9 +0x70,0xff,0xf2,0x00 = vqadd.u64 q8, q8, q9 +0xc0,0xef,0xa2,0x04 = vaddhn.i16 d16, q8, q9 +0xd0,0xef,0xa2,0x04 = vaddhn.i32 d16, q8, q9 +0xe0,0xef,0xa2,0x04 = vaddhn.i64 d16, q8, q9 +0xc0,0xff,0xa2,0x04 = vraddhn.i16 d16, q8, q9 +0xd0,0xff,0xa2,0x04 = vraddhn.i32 d16, q8, q9 +0xe0,0xff,0xa2,0x04 = vraddhn.i64 d16, q8, q9 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-bitcount-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-bitcount-encoding.s.cs new file mode 100644 index 0000000..6f6714d --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-bitcount-encoding.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xf0,0xff,0x20,0x05 = vcnt.8 d16, d16 +0xf0,0xff,0x60,0x05 = vcnt.8 q8, q8 +0xf0,0xff,0xa0,0x04 = vclz.i8 d16, d16 +0xf4,0xff,0xa0,0x04 = vclz.i16 d16, d16 +0xf8,0xff,0xa0,0x04 = vclz.i32 d16, d16 +0xf0,0xff,0xe0,0x04 = vclz.i8 q8, q8 +0xf4,0xff,0xe0,0x04 = vclz.i16 q8, q8 +0xf8,0xff,0xe0,0x04 = vclz.i32 q8, q8 +0xf0,0xff,0x20,0x04 = vcls.s8 d16, d16 +0xf4,0xff,0x20,0x04 = vcls.s16 d16, d16 +0xf8,0xff,0x20,0x04 = vcls.s32 d16, d16 +0xf0,0xff,0x60,0x04 = vcls.s8 q8, q8 +0xf4,0xff,0x60,0x04 = vcls.s16 q8, q8 +0xf8,0xff,0x60,0x04 = vcls.s32 q8, q8 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-bitwise-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-bitwise-encoding.s.cs new file mode 100644 index 0000000..30cd6c6 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-bitwise-encoding.s.cs @@ -0,0 +1,19 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x41,0xef,0xb0,0x01 = vand d16, d17, d16 +0x40,0xef,0xf2,0x01 = vand q8, q8, q9 +0x41,0xff,0xb0,0x01 = veor d16, d17, d16 +0x40,0xff,0xf2,0x01 = veor q8, q8, q9 +0x61,0xef,0xb0,0x01 = vorr d16, d17, d16 +0x60,0xef,0xf2,0x01 = vorr q8, q8, q9 +0x51,0xef,0xb0,0x01 = vbic d16, d17, d16 +0x50,0xef,0xf2,0x01 = vbic q8, q8, q9 +0x71,0xef,0xb0,0x01 = vorn d16, d17, d16 +0x70,0xef,0xf2,0x01 = vorn q8, q8, q9 +0xf0,0xff,0xa0,0x05 = vmvn d16, d16 +0xf0,0xff,0xe0,0x05 = vmvn q8, q8 +0x51,0xff,0xb0,0x21 = vbsl d18, d17, d16 +0x54,0xff,0xf2,0x01 = vbsl q8, q10, q9 +0x61,0xff,0xb0,0x21 = vbit d18, d17, d16 +0x64,0xff,0xf2,0x01 = vbit q8, q10, q9 +0x71,0xff,0xb0,0x21 = vbif d18, d17, d16 +0x74,0xff,0xf2,0x01 = vbif q8, q10, q9 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-cmp-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-cmp-encoding.s.cs new file mode 100644 index 0000000..6bd4971 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-cmp-encoding.s.cs @@ -0,0 +1,17 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xfb,0xff,0x20,0x07 = vcvt.s32.f32 d16, d16 +0xfb,0xff,0xa0,0x07 = vcvt.u32.f32 d16, d16 +0xfb,0xff,0x20,0x06 = vcvt.f32.s32 d16, d16 +0xfb,0xff,0xa0,0x06 = vcvt.f32.u32 d16, d16 +0xfb,0xff,0x60,0x07 = vcvt.s32.f32 q8, q8 +0xfb,0xff,0xe0,0x07 = vcvt.u32.f32 q8, q8 +0xfb,0xff,0x60,0x06 = vcvt.f32.s32 q8, q8 +0xfb,0xff,0xe0,0x06 = vcvt.f32.u32 q8, q8 +0xff,0xef,0x30,0x0f = vcvt.s32.f32 d16, d16, #1 +0xff,0xff,0x30,0x0f = vcvt.u32.f32 d16, d16, #1 +0xff,0xef,0x30,0x0e = vcvt.f32.s32 d16, d16, #1 +0xff,0xff,0x30,0x0e = vcvt.f32.u32 d16, d16, #1 +0xff,0xef,0x70,0x0f = vcvt.s32.f32 q8, q8, #1 +0xff,0xff,0x70,0x0f = vcvt.u32.f32 q8, q8, #1 +0xff,0xef,0x70,0x0e = vcvt.f32.s32 q8, q8, #1 +0xff,0xff,0x70,0x0e = vcvt.f32.u32 q8, q8, #1 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-convert-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-convert-encoding.s.cs new file mode 100644 index 0000000..b502580 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-convert-encoding.s.cs @@ -0,0 +1,19 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xfb,0xff,0x20,0x07 = vcvt.s32.f32 d16, d16 +0xfb,0xff,0xa0,0x07 = vcvt.u32.f32 d16, d16 +0xfb,0xff,0x20,0x06 = vcvt.f32.s32 d16, d16 +0xfb,0xff,0xa0,0x06 = vcvt.f32.u32 d16, d16 +0xfb,0xff,0x60,0x07 = vcvt.s32.f32 q8, q8 +0xfb,0xff,0xe0,0x07 = vcvt.u32.f32 q8, q8 +0xfb,0xff,0x60,0x06 = vcvt.f32.s32 q8, q8 +0xfb,0xff,0xe0,0x06 = vcvt.f32.u32 q8, q8 +0xff,0xef,0x30,0x0f = vcvt.s32.f32 d16, d16, #1 +0xff,0xff,0x30,0x0f = vcvt.u32.f32 d16, d16, #1 +0xff,0xef,0x30,0x0e = vcvt.f32.s32 d16, d16, #1 +0xff,0xff,0x30,0x0e = vcvt.f32.u32 d16, d16, #1 +0xff,0xef,0x70,0x0f = vcvt.s32.f32 q8, q8, #1 +0xff,0xff,0x70,0x0f = vcvt.u32.f32 q8, q8, #1 +0xff,0xef,0x70,0x0e = vcvt.f32.s32 q8, q8, #1 +0xff,0xff,0x70,0x0e = vcvt.f32.u32 q8, q8, #1 +0xf6,0xff,0x20,0x07 = vcvt.f32.f16 q8, d16 +0xf6,0xff,0x20,0x06 = vcvt.f16.f32 d16, q8 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-dup-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-dup-encoding.s.cs new file mode 100644 index 0000000..525cd7f --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-dup-encoding.s.cs @@ -0,0 +1,19 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xc0,0xee,0x90,0x1b = vdup.8 d16, r1 +0x8f,0xee,0x30,0x2b = vdup.16 d15, r2 +0x8e,0xee,0x10,0x3b = vdup.32 d14, r3 +0xe2,0xee,0x90,0x4b = vdup.8 q9, r4 +0xa0,0xee,0xb0,0x5b = vdup.16 q8, r5 +0xae,0xee,0x10,0x6b = vdup.32 q7, r6 +0xf1,0xff,0x0b,0x0c = vdup.8 d16, d11[0] +0xf2,0xff,0x0c,0x1c = vdup.16 d17, d12[0] +0xf4,0xff,0x0d,0x2c = vdup.32 d18, d13[0] +0xb1,0xff,0x4a,0x6c = vdup.8 q3, d10[0] +0xf2,0xff,0x49,0x2c = vdup.16 q9, d9[0] +0xf4,0xff,0x48,0x0c = vdup.32 q8, d8[0] +0xf3,0xff,0x0b,0x0c = vdup.8 d16, d11[1] +0xf6,0xff,0x0c,0x1c = vdup.16 d17, d12[1] +0xfc,0xff,0x0d,0x2c = vdup.32 d18, d13[1] +0xb3,0xff,0x4a,0x6c = vdup.8 q3, d10[1] +0xf6,0xff,0x49,0x2c = vdup.16 q9, d9[1] +0xfc,0xff,0x48,0x0c = vdup.32 q8, d8[1] diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-minmax-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-minmax-encoding.s.cs new file mode 100644 index 0000000..eb605f9 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-minmax-encoding.s.cs @@ -0,0 +1,57 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x02,0xef,0x03,0x16 = vmax.s8 d1, d2, d3 +0x15,0xef,0x06,0x46 = vmax.s16 d4, d5, d6 +0x28,0xef,0x09,0x76 = vmax.s32 d7, d8, d9 +0x0b,0xff,0x0c,0xa6 = vmax.u8 d10, d11, d12 +0x1e,0xff,0x0f,0xd6 = vmax.u16 d13, d14, d15 +0x61,0xff,0xa2,0x06 = vmax.u32 d16, d17, d18 +0x44,0xef,0xa5,0x3f = vmax.f32 d19, d20, d21 +0x02,0xef,0x03,0x26 = vmax.s8 d2, d2, d3 +0x15,0xef,0x06,0x56 = vmax.s16 d5, d5, d6 +0x28,0xef,0x09,0x86 = vmax.s32 d8, d8, d9 +0x0b,0xff,0x0c,0xb6 = vmax.u8 d11, d11, d12 +0x1e,0xff,0x0f,0xe6 = vmax.u16 d14, d14, d15 +0x61,0xff,0xa2,0x16 = vmax.u32 d17, d17, d18 +0x44,0xef,0xa5,0x4f = vmax.f32 d20, d20, d21 +0x04,0xef,0x46,0x26 = vmax.s8 q1, q2, q3 +0x1a,0xef,0x4c,0x86 = vmax.s16 q4, q5, q6 +0x20,0xef,0xe2,0xe6 = vmax.s32 q7, q8, q9 +0x46,0xff,0xe8,0x46 = vmax.u8 q10, q11, q12 +0x5c,0xff,0xee,0xa6 = vmax.u16 q13, q14, q15 +0x2e,0xff,0x60,0xc6 = vmax.u32 q6, q7, q8 +0x4a,0xef,0x42,0x2f = vmax.f32 q9, q5, q1 +0x04,0xef,0x46,0x46 = vmax.s8 q2, q2, q3 +0x1a,0xef,0x4c,0xa6 = vmax.s16 q5, q5, q6 +0x60,0xef,0xe2,0x06 = vmax.s32 q8, q8, q9 +0x46,0xff,0xc4,0x66 = vmax.u8 q11, q11, q2 +0x18,0xff,0x4a,0x86 = vmax.u16 q4, q4, q5 +0x2e,0xff,0x60,0xe6 = vmax.u32 q7, q7, q8 +0x04,0xef,0x42,0x4f = vmax.f32 q2, q2, q1 +0x02,0xef,0x13,0x16 = vmin.s8 d1, d2, d3 +0x15,0xef,0x16,0x46 = vmin.s16 d4, d5, d6 +0x28,0xef,0x19,0x76 = vmin.s32 d7, d8, d9 +0x0b,0xff,0x1c,0xa6 = vmin.u8 d10, d11, d12 +0x1e,0xff,0x1f,0xd6 = vmin.u16 d13, d14, d15 +0x61,0xff,0xb2,0x06 = vmin.u32 d16, d17, d18 +0x64,0xef,0xa5,0x3f = vmin.f32 d19, d20, d21 +0x02,0xef,0x13,0x26 = vmin.s8 d2, d2, d3 +0x15,0xef,0x16,0x56 = vmin.s16 d5, d5, d6 +0x28,0xef,0x19,0x86 = vmin.s32 d8, d8, d9 +0x0b,0xff,0x1c,0xb6 = vmin.u8 d11, d11, d12 +0x1e,0xff,0x1f,0xe6 = vmin.u16 d14, d14, d15 +0x61,0xff,0xb2,0x16 = vmin.u32 d17, d17, d18 +0x64,0xef,0xa5,0x4f = vmin.f32 d20, d20, d21 +0x04,0xef,0x56,0x26 = vmin.s8 q1, q2, q3 +0x1a,0xef,0x5c,0x86 = vmin.s16 q4, q5, q6 +0x20,0xef,0xf2,0xe6 = vmin.s32 q7, q8, q9 +0x46,0xff,0xf8,0x46 = vmin.u8 q10, q11, q12 +0x5c,0xff,0xfe,0xa6 = vmin.u16 q13, q14, q15 +0x2e,0xff,0x70,0xc6 = vmin.u32 q6, q7, q8 +0x6a,0xef,0x42,0x2f = vmin.f32 q9, q5, q1 +0x04,0xef,0x56,0x46 = vmin.s8 q2, q2, q3 +0x1a,0xef,0x5c,0xa6 = vmin.s16 q5, q5, q6 +0x60,0xef,0xf2,0x06 = vmin.s32 q8, q8, q9 +0x46,0xff,0xd4,0x66 = vmin.u8 q11, q11, q2 +0x18,0xff,0x5a,0x86 = vmin.u16 q4, q4, q5 +0x2e,0xff,0x70,0xe6 = vmin.u32 q7, q7, q8 +0x24,0xef,0x42,0x4f = vmin.f32 q2, q2, q1 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-mov-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-mov-encoding.s.cs new file mode 100644 index 0000000..b39c0c6 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-mov-encoding.s.cs @@ -0,0 +1,58 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xc0,0xef,0x18,0x0e = vmov.i8 d16, #0x8 +0xc1,0xef,0x10,0x08 = vmov.i16 d16, #0x10 +0xc1,0xef,0x10,0x0a = vmov.i16 d16, #0x1000 +0xc2,0xef,0x10,0x00 = vmov.i32 d16, #0x20 +0xc2,0xef,0x10,0x02 = vmov.i32 d16, #0x2000 +0xc2,0xef,0x10,0x04 = vmov.i32 d16, #0x200000 +0xc2,0xef,0x10,0x06 = vmov.i32 d16, #0x20000000 +0xc2,0xef,0x10,0x0c = vmov.i32 d16, #0x20ff +0xc2,0xef,0x10,0x0d = vmov.i32 d16, #0x20ffff +0xc1,0xff,0x33,0x0e = vmov.i64 d16, #0xff0000ff0000ffff +0xc0,0xef,0x58,0x0e = vmov.i8 q8, #0x8 +0xc1,0xef,0x50,0x08 = vmov.i16 q8, #0x10 +0xc1,0xef,0x50,0x0a = vmov.i16 q8, #0x1000 +0xc2,0xef,0x50,0x00 = vmov.i32 q8, #0x20 +0xc2,0xef,0x50,0x02 = vmov.i32 q8, #0x2000 +0xc2,0xef,0x50,0x04 = vmov.i32 q8, #0x200000 +0xc2,0xef,0x50,0x06 = vmov.i32 q8, #0x20000000 +0xc2,0xef,0x50,0x0c = vmov.i32 q8, #0x20ff +0xc2,0xef,0x50,0x0d = vmov.i32 q8, #0x20ffff +0xc1,0xff,0x73,0x0e = vmov.i64 q8, #0xff0000ff0000ffff +0xc1,0xef,0x30,0x08 = vmvn.i16 d16, #0x10 +0xc1,0xef,0x30,0x0a = vmvn.i16 d16, #0x1000 +0xc2,0xef,0x30,0x00 = vmvn.i32 d16, #0x20 +0xc2,0xef,0x30,0x02 = vmvn.i32 d16, #0x2000 +0xc2,0xef,0x30,0x04 = vmvn.i32 d16, #0x200000 +0xc2,0xef,0x30,0x06 = vmvn.i32 d16, #0x20000000 +0xc2,0xef,0x30,0x0c = vmvn.i32 d16, #0x20ff +0xc2,0xef,0x30,0x0d = vmvn.i32 d16, #0x20ffff +0xc8,0xef,0x30,0x0a = vmovl.s8 q8, d16 +0xd0,0xef,0x30,0x0a = vmovl.s16 q8, d16 +0xe0,0xef,0x30,0x0a = vmovl.s32 q8, d16 +0xc8,0xff,0x30,0x0a = vmovl.u8 q8, d16 +0xd0,0xff,0x30,0x0a = vmovl.u16 q8, d16 +0xe0,0xff,0x30,0x0a = vmovl.u32 q8, d16 +0xf2,0xff,0x20,0x02 = vmovn.i16 d16, q8 +0xf6,0xff,0x20,0x02 = vmovn.i32 d16, q8 +0xfa,0xff,0x20,0x02 = vmovn.i64 d16, q8 +0xf2,0xff,0xa0,0x02 = vqmovn.s16 d16, q8 +0xf6,0xff,0xa0,0x02 = vqmovn.s32 d16, q8 +0xfa,0xff,0xa0,0x02 = vqmovn.s64 d16, q8 +0xf2,0xff,0xe0,0x02 = vqmovn.u16 d16, q8 +0xf6,0xff,0xe0,0x02 = vqmovn.u32 d16, q8 +0xfa,0xff,0xe0,0x02 = vqmovn.u64 d16, q8 +0xf2,0xff,0x60,0x02 = vqmovun.s16 d16, q8 +0xf6,0xff,0x60,0x02 = vqmovun.s32 d16, q8 +0xfa,0xff,0x60,0x02 = vqmovun.s64 d16, q8 +0x50,0xee,0xb0,0x0b = vmov.s8 r0, d16[1] +0x10,0xee,0xf0,0x0b = vmov.s16 r0, d16[1] +0xd0,0xee,0xb0,0x0b = vmov.u8 r0, d16[1] +0x90,0xee,0xf0,0x0b = vmov.u16 r0, d16[1] +0x30,0xee,0x90,0x0b = vmov.32 r0, d16[1] +0x40,0xee,0xb0,0x1b = vmov.8 d16[1], r1 +0x00,0xee,0xf0,0x1b = vmov.16 d16[1], r1 +0x20,0xee,0x90,0x1b = vmov.32 d16[1], r1 +0x42,0xee,0xb0,0x1b = vmov.8 d18[1], r1 +0x02,0xee,0xf0,0x1b = vmov.16 d18[1], r1 +0x22,0xee,0x90,0x1b = vmov.32 d18[1], r1 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-mul-accum-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-mul-accum-encoding.s.cs new file mode 100644 index 0000000..385141d --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-mul-accum-encoding.s.cs @@ -0,0 +1,41 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x42,0xef,0xa1,0x09 = vmla.i8 d16, d18, d17 +0x52,0xef,0xa1,0x09 = vmla.i16 d16, d18, d17 +0x62,0xef,0xa1,0x09 = vmla.i32 d16, d18, d17 +0x42,0xef,0xb1,0x0d = vmla.f32 d16, d18, d17 +0x40,0xef,0xe4,0x29 = vmla.i8 q9, q8, q10 +0x50,0xef,0xe4,0x29 = vmla.i16 q9, q8, q10 +0x60,0xef,0xe4,0x29 = vmla.i32 q9, q8, q10 +0x40,0xef,0xf4,0x2d = vmla.f32 q9, q8, q10 +0xe0,0xff,0xc3,0x80 = vmla.i32 q12, q8, d3[0] +0xc3,0xef,0xa2,0x08 = vmlal.s8 q8, d19, d18 +0xd3,0xef,0xa2,0x08 = vmlal.s16 q8, d19, d18 +0xe3,0xef,0xa2,0x08 = vmlal.s32 q8, d19, d18 +0xc3,0xff,0xa2,0x08 = vmlal.u8 q8, d19, d18 +0xd3,0xff,0xa2,0x08 = vmlal.u16 q8, d19, d18 +0xe3,0xff,0xa2,0x08 = vmlal.u32 q8, d19, d18 +0xa5,0xef,0x4a,0x02 = vmlal.s32 q0, d5, d10[0] +0xd3,0xef,0xa2,0x09 = vqdmlal.s16 q8, d19, d18 +0xe3,0xef,0xa2,0x09 = vqdmlal.s32 q8, d19, d18 +0xdb,0xef,0x47,0x63 = vqdmlal.s16 q11, d11, d7[0] +0xdb,0xef,0x4f,0x63 = vqdmlal.s16 q11, d11, d7[1] +0xdb,0xef,0x67,0x63 = vqdmlal.s16 q11, d11, d7[2] +0xdb,0xef,0x6f,0x63 = vqdmlal.s16 q11, d11, d7[3] +0x42,0xff,0xa1,0x09 = vmls.i8 d16, d18, d17 +0x52,0xff,0xa1,0x09 = vmls.i16 d16, d18, d17 +0x62,0xff,0xa1,0x09 = vmls.i32 d16, d18, d17 +0x62,0xef,0xb1,0x0d = vmls.f32 d16, d18, d17 +0x40,0xff,0xe4,0x29 = vmls.i8 q9, q8, q10 +0x50,0xff,0xe4,0x29 = vmls.i16 q9, q8, q10 +0x60,0xff,0xe4,0x29 = vmls.i32 q9, q8, q10 +0x60,0xef,0xf4,0x2d = vmls.f32 q9, q8, q10 +0x98,0xff,0xe6,0x84 = vmls.i16 q4, q12, d6[2] +0xc3,0xef,0xa2,0x0a = vmlsl.s8 q8, d19, d18 +0xd3,0xef,0xa2,0x0a = vmlsl.s16 q8, d19, d18 +0xe3,0xef,0xa2,0x0a = vmlsl.s32 q8, d19, d18 +0xc3,0xff,0xa2,0x0a = vmlsl.u8 q8, d19, d18 +0xd3,0xff,0xa2,0x0a = vmlsl.u16 q8, d19, d18 +0xe3,0xff,0xa2,0x0a = vmlsl.u32 q8, d19, d18 +0xd9,0xff,0xe9,0x66 = vmlsl.u16 q11, d25, d1[3] +0xd3,0xef,0xa2,0x0b = vqdmlsl.s16 q8, d19, d18 +0xe3,0xef,0xa2,0x0b = vqdmlsl.s32 q8, d19, d18 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-mul-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-mul-encoding.s.cs new file mode 100644 index 0000000..0fa9106 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-mul-encoding.s.cs @@ -0,0 +1,31 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x40,0xef,0xb1,0x09 = vmul.i8 d16, d16, d17 +0x50,0xef,0xb1,0x09 = vmul.i16 d16, d16, d17 +0x60,0xef,0xb1,0x09 = vmul.i32 d16, d16, d17 +0x40,0xff,0xb1,0x0d = vmul.f32 d16, d16, d17 +0x40,0xef,0xf2,0x09 = vmul.i8 q8, q8, q9 +0x50,0xef,0xf2,0x09 = vmul.i16 q8, q8, q9 +0x60,0xef,0xf2,0x09 = vmul.i32 q8, q8, q9 +0x40,0xff,0xf2,0x0d = vmul.f32 q8, q8, q9 +0x40,0xff,0xb1,0x09 = vmul.p8 d16, d16, d17 +0x40,0xff,0xf2,0x09 = vmul.p8 q8, q8, q9 +0xd8,0xef,0x68,0x28 = vmul.i16 d18, d8, d0[3] +0x50,0xef,0xa1,0x0b = vqdmulh.s16 d16, d16, d17 +0x60,0xef,0xa1,0x0b = vqdmulh.s32 d16, d16, d17 +0x50,0xef,0xe2,0x0b = vqdmulh.s16 q8, q8, q9 +0x60,0xef,0xe2,0x0b = vqdmulh.s32 q8, q8, q9 +0x92,0xef,0x43,0xbc = vqdmulh.s16 d11, d2, d3[0] +0x50,0xff,0xa1,0x0b = vqrdmulh.s16 d16, d16, d17 +0x60,0xff,0xa1,0x0b = vqrdmulh.s32 d16, d16, d17 +0x50,0xff,0xe2,0x0b = vqrdmulh.s16 q8, q8, q9 +0x60,0xff,0xe2,0x0b = vqrdmulh.s32 q8, q8, q9 +0xc0,0xef,0xa1,0x0c = vmull.s8 q8, d16, d17 +0xd0,0xef,0xa1,0x0c = vmull.s16 q8, d16, d17 +0xe0,0xef,0xa1,0x0c = vmull.s32 q8, d16, d17 +0xc0,0xff,0xa1,0x0c = vmull.u8 q8, d16, d17 +0xd0,0xff,0xa1,0x0c = vmull.u16 q8, d16, d17 +0xe0,0xff,0xa1,0x0c = vmull.u32 q8, d16, d17 +0xc0,0xef,0xa1,0x0e = vmull.p8 q8, d16, d17 +0xd0,0xef,0xa1,0x0d = vqdmull.s16 q8, d16, d17 +0xe0,0xef,0xa1,0x0d = vqdmull.s32 q8, d16, d17 +0x97,0xef,0x49,0x2b = vqdmull.s16 q1, d7, d1[1] diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-neg-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-neg-encoding.s.cs new file mode 100644 index 0000000..a6eaa06 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-neg-encoding.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xf1,0xff,0xa0,0x03 = vneg.s8 d16, d16 +0xf5,0xff,0xa0,0x03 = vneg.s16 d16, d16 +0xf9,0xff,0xa0,0x03 = vneg.s32 d16, d16 +0xf9,0xff,0xa0,0x07 = vneg.f32 d16, d16 +0xf1,0xff,0xe0,0x03 = vneg.s8 q8, q8 +0xf5,0xff,0xe0,0x03 = vneg.s16 q8, q8 +0xf9,0xff,0xe0,0x03 = vneg.s32 q8, q8 +0xf9,0xff,0xe0,0x07 = vneg.f32 q8, q8 +0xf0,0xff,0xa0,0x07 = vqneg.s8 d16, d16 +0xf4,0xff,0xa0,0x07 = vqneg.s16 d16, d16 +0xf8,0xff,0xa0,0x07 = vqneg.s32 d16, d16 +0xf0,0xff,0xe0,0x07 = vqneg.s8 q8, q8 +0xf4,0xff,0xe0,0x07 = vqneg.s16 q8, q8 +0xf8,0xff,0xe0,0x07 = vqneg.s32 q8, q8 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-pairwise-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-pairwise-encoding.s.cs new file mode 100644 index 0000000..39bbe94 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-pairwise-encoding.s.cs @@ -0,0 +1,43 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x05,0xef,0x1b,0x1b = vpadd.i8 d1, d5, d11 +0x12,0xef,0x1c,0xdb = vpadd.i16 d13, d2, d12 +0x21,0xef,0x1d,0xeb = vpadd.i32 d14, d1, d13 +0x40,0xff,0x8e,0x3d = vpadd.f32 d19, d16, d14 +0xb0,0xff,0x0a,0x72 = vpaddl.s8 d7, d10 +0xb4,0xff,0x0b,0x82 = vpaddl.s16 d8, d11 +0xb8,0xff,0x0c,0x92 = vpaddl.s32 d9, d12 +0xb0,0xff,0x8d,0x02 = vpaddl.u8 d0, d13 +0xb4,0xff,0x8e,0x52 = vpaddl.u16 d5, d14 +0xb8,0xff,0x8f,0x62 = vpaddl.u32 d6, d15 +0xb0,0xff,0x4e,0x82 = vpaddl.s8 q4, q7 +0xb4,0xff,0x4c,0xa2 = vpaddl.s16 q5, q6 +0xb8,0xff,0x4a,0xc2 = vpaddl.s32 q6, q5 +0xb0,0xff,0xc8,0xe2 = vpaddl.u8 q7, q4 +0xf4,0xff,0xc6,0x02 = vpaddl.u16 q8, q3 +0xf8,0xff,0xc4,0x22 = vpaddl.u32 q9, q2 +0xf0,0xff,0x04,0x06 = vpadal.s8 d16, d4 +0xf4,0xff,0x09,0x46 = vpadal.s16 d20, d9 +0xf8,0xff,0x01,0x26 = vpadal.s32 d18, d1 +0xb0,0xff,0xa9,0xe6 = vpadal.u8 d14, d25 +0xb4,0xff,0x86,0xc6 = vpadal.u16 d12, d6 +0xb8,0xff,0x87,0xb6 = vpadal.u32 d11, d7 +0xb0,0xff,0x64,0x86 = vpadal.s8 q4, q10 +0xb4,0xff,0x66,0xa6 = vpadal.s16 q5, q11 +0xb8,0xff,0x68,0xc6 = vpadal.s32 q6, q12 +0xb0,0xff,0xea,0xe6 = vpadal.u8 q7, q13 +0xf4,0xff,0xec,0x06 = vpadal.u16 q8, q14 +0xf8,0xff,0xee,0x26 = vpadal.u32 q9, q15 +0x4d,0xef,0x9a,0x0a = vpmin.s8 d16, d29, d10 +0x5c,0xef,0x9b,0x1a = vpmin.s16 d17, d28, d11 +0x6b,0xef,0x9c,0x2a = vpmin.s32 d18, d27, d12 +0x4a,0xff,0x9d,0x3a = vpmin.u8 d19, d26, d13 +0x59,0xff,0x9e,0x4a = vpmin.u16 d20, d25, d14 +0x68,0xff,0x9f,0x5a = vpmin.u32 d21, d24, d15 +0x67,0xff,0xa0,0x6f = vpmin.f32 d22, d23, d16 +0x04,0xef,0xa1,0x3a = vpmax.s8 d3, d20, d17 +0x15,0xef,0xa0,0x4a = vpmax.s16 d4, d21, d16 +0x26,0xef,0x8f,0x5a = vpmax.s32 d5, d22, d15 +0x07,0xff,0x8e,0x6a = vpmax.u8 d6, d23, d14 +0x18,0xff,0x8d,0x7a = vpmax.u16 d7, d24, d13 +0x29,0xff,0x8c,0x8a = vpmax.u32 d8, d25, d12 +0x0a,0xff,0x8b,0x9f = vpmax.f32 d9, d26, d11 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-reciprocal-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-reciprocal-encoding.s.cs new file mode 100644 index 0000000..139b9ae --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-reciprocal-encoding.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xfb,0xff,0x20,0x04 = vrecpe.u32 d16, d16 +0xfb,0xff,0x60,0x04 = vrecpe.u32 q8, q8 +0xfb,0xff,0x20,0x05 = vrecpe.f32 d16, d16 +0xfb,0xff,0x60,0x05 = vrecpe.f32 q8, q8 +0x40,0xef,0xb1,0x0f = vrecps.f32 d16, d16, d17 +0x40,0xef,0xf2,0x0f = vrecps.f32 q8, q8, q9 +0xfb,0xff,0xa0,0x04 = vrsqrte.u32 d16, d16 +0xfb,0xff,0xe0,0x04 = vrsqrte.u32 q8, q8 +0xfb,0xff,0xa0,0x05 = vrsqrte.f32 d16, d16 +0xfb,0xff,0xe0,0x05 = vrsqrte.f32 q8, q8 +0x60,0xef,0xb1,0x0f = vrsqrts.f32 d16, d16, d17 +0x60,0xef,0xf2,0x0f = vrsqrts.f32 q8, q8, q9 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-reverse-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-reverse-encoding.s.cs new file mode 100644 index 0000000..119b1d1 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-reverse-encoding.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xf0,0xff,0x20,0x00 = vrev64.8 d16, d16 +0xf4,0xff,0x20,0x00 = vrev64.16 d16, d16 +0xf8,0xff,0x20,0x00 = vrev64.32 d16, d16 +0xf0,0xff,0x60,0x00 = vrev64.8 q8, q8 +0xf4,0xff,0x60,0x00 = vrev64.16 q8, q8 +0xf8,0xff,0x60,0x00 = vrev64.32 q8, q8 +0xf0,0xff,0xa0,0x00 = vrev32.8 d16, d16 +0xf4,0xff,0xa0,0x00 = vrev32.16 d16, d16 +0xf0,0xff,0xe0,0x00 = vrev32.8 q8, q8 +0xf4,0xff,0xe0,0x00 = vrev32.16 q8, q8 +0xf0,0xff,0x20,0x01 = vrev16.8 d16, d16 +0xf0,0xff,0x60,0x01 = vrev16.8 q8, q8 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-satshift-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-satshift-encoding.s.cs new file mode 100644 index 0000000..f971d11 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-satshift-encoding.s.cs @@ -0,0 +1,75 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x41,0xef,0xb0,0x04 = vqshl.s8 d16, d16, d17 +0x51,0xef,0xb0,0x04 = vqshl.s16 d16, d16, d17 +0x61,0xef,0xb0,0x04 = vqshl.s32 d16, d16, d17 +0x71,0xef,0xb0,0x04 = vqshl.s64 d16, d16, d17 +0x41,0xff,0xb0,0x04 = vqshl.u8 d16, d16, d17 +0x51,0xff,0xb0,0x04 = vqshl.u16 d16, d16, d17 +0x61,0xff,0xb0,0x04 = vqshl.u32 d16, d16, d17 +0x71,0xff,0xb0,0x04 = vqshl.u64 d16, d16, d17 +0x42,0xef,0xf0,0x04 = vqshl.s8 q8, q8, q9 +0x52,0xef,0xf0,0x04 = vqshl.s16 q8, q8, q9 +0x62,0xef,0xf0,0x04 = vqshl.s32 q8, q8, q9 +0x72,0xef,0xf0,0x04 = vqshl.s64 q8, q8, q9 +0x42,0xff,0xf0,0x04 = vqshl.u8 q8, q8, q9 +0x52,0xff,0xf0,0x04 = vqshl.u16 q8, q8, q9 +0x62,0xff,0xf0,0x04 = vqshl.u32 q8, q8, q9 +0x72,0xff,0xf0,0x04 = vqshl.u64 q8, q8, q9 +0xcf,0xef,0x30,0x07 = vqshl.s8 d16, d16, #7 +0xdf,0xef,0x30,0x07 = vqshl.s16 d16, d16, #0xf +0xff,0xef,0x30,0x07 = vqshl.s32 d16, d16, #0x1f +0xff,0xef,0xb0,0x07 = vqshl.s64 d16, d16, #0x3f +0xcf,0xff,0x30,0x07 = vqshl.u8 d16, d16, #7 +0xdf,0xff,0x30,0x07 = vqshl.u16 d16, d16, #0xf +0xff,0xff,0x30,0x07 = vqshl.u32 d16, d16, #0x1f +0xff,0xff,0xb0,0x07 = vqshl.u64 d16, d16, #0x3f +0xcf,0xff,0x30,0x06 = vqshlu.s8 d16, d16, #7 +0xdf,0xff,0x30,0x06 = vqshlu.s16 d16, d16, #0xf +0xff,0xff,0x30,0x06 = vqshlu.s32 d16, d16, #0x1f +0xff,0xff,0xb0,0x06 = vqshlu.s64 d16, d16, #0x3f +0xcf,0xef,0x70,0x07 = vqshl.s8 q8, q8, #7 +0xdf,0xef,0x70,0x07 = vqshl.s16 q8, q8, #0xf +0xff,0xef,0x70,0x07 = vqshl.s32 q8, q8, #0x1f +0xff,0xef,0xf0,0x07 = vqshl.s64 q8, q8, #0x3f +0xcf,0xff,0x70,0x07 = vqshl.u8 q8, q8, #7 +0xdf,0xff,0x70,0x07 = vqshl.u16 q8, q8, #0xf +0xff,0xff,0x70,0x07 = vqshl.u32 q8, q8, #0x1f +0xff,0xff,0xf0,0x07 = vqshl.u64 q8, q8, #0x3f +0xcf,0xff,0x70,0x06 = vqshlu.s8 q8, q8, #7 +0xdf,0xff,0x70,0x06 = vqshlu.s16 q8, q8, #0xf +0xff,0xff,0x70,0x06 = vqshlu.s32 q8, q8, #0x1f +0xff,0xff,0xf0,0x06 = vqshlu.s64 q8, q8, #0x3f +0x41,0xef,0xb0,0x05 = vqrshl.s8 d16, d16, d17 +0x51,0xef,0xb0,0x05 = vqrshl.s16 d16, d16, d17 +0x61,0xef,0xb0,0x05 = vqrshl.s32 d16, d16, d17 +0x71,0xef,0xb0,0x05 = vqrshl.s64 d16, d16, d17 +0x41,0xff,0xb0,0x05 = vqrshl.u8 d16, d16, d17 +0x51,0xff,0xb0,0x05 = vqrshl.u16 d16, d16, d17 +0x61,0xff,0xb0,0x05 = vqrshl.u32 d16, d16, d17 +0x71,0xff,0xb0,0x05 = vqrshl.u64 d16, d16, d17 +0x42,0xef,0xf0,0x05 = vqrshl.s8 q8, q8, q9 +0x52,0xef,0xf0,0x05 = vqrshl.s16 q8, q8, q9 +0x62,0xef,0xf0,0x05 = vqrshl.s32 q8, q8, q9 +0x72,0xef,0xf0,0x05 = vqrshl.s64 q8, q8, q9 +0x42,0xff,0xf0,0x05 = vqrshl.u8 q8, q8, q9 +0x52,0xff,0xf0,0x05 = vqrshl.u16 q8, q8, q9 +0x62,0xff,0xf0,0x05 = vqrshl.u32 q8, q8, q9 +0x72,0xff,0xf0,0x05 = vqrshl.u64 q8, q8, q9 +0xc8,0xef,0x30,0x09 = vqshrn.s16 d16, q8, #8 +0xd0,0xef,0x30,0x09 = vqshrn.s32 d16, q8, #0x10 +0xe0,0xef,0x30,0x09 = vqshrn.s64 d16, q8, #0x20 +0xc8,0xff,0x30,0x09 = vqshrn.u16 d16, q8, #8 +0xd0,0xff,0x30,0x09 = vqshrn.u32 d16, q8, #0x10 +0xe0,0xff,0x30,0x09 = vqshrn.u64 d16, q8, #0x20 +0xc8,0xff,0x30,0x08 = vqshrun.s16 d16, q8, #8 +0xd0,0xff,0x30,0x08 = vqshrun.s32 d16, q8, #0x10 +0xe0,0xff,0x30,0x08 = vqshrun.s64 d16, q8, #0x20 +0xc8,0xef,0x70,0x09 = vqrshrn.s16 d16, q8, #8 +0xd0,0xef,0x70,0x09 = vqrshrn.s32 d16, q8, #0x10 +0xe0,0xef,0x70,0x09 = vqrshrn.s64 d16, q8, #0x20 +0xc8,0xff,0x70,0x09 = vqrshrn.u16 d16, q8, #8 +0xd0,0xff,0x70,0x09 = vqrshrn.u32 d16, q8, #0x10 +0xe0,0xff,0x70,0x09 = vqrshrn.u64 d16, q8, #0x20 +0xc8,0xff,0x70,0x08 = vqrshrun.s16 d16, q8, #8 +0xd0,0xff,0x70,0x08 = vqrshrun.s32 d16, q8, #0x10 +0xe0,0xff,0x70,0x08 = vqrshrun.s64 d16, q8, #0x20 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-shift-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-shift-encoding.s.cs new file mode 100644 index 0000000..ca49ff3 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-shift-encoding.s.cs @@ -0,0 +1,80 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x40,0xff,0xa1,0x04 = vshl.u8 d16, d17, d16 +0x50,0xff,0xa1,0x04 = vshl.u16 d16, d17, d16 +0x60,0xff,0xa1,0x04 = vshl.u32 d16, d17, d16 +0x70,0xff,0xa1,0x04 = vshl.u64 d16, d17, d16 +0xcf,0xef,0x30,0x05 = vshl.i8 d16, d16, #7 +0xdf,0xef,0x30,0x05 = vshl.i16 d16, d16, #0xf +0xff,0xef,0x30,0x05 = vshl.i32 d16, d16, #0x1f +0xff,0xef,0xb0,0x05 = vshl.i64 d16, d16, #0x3f +0x40,0xff,0xe2,0x04 = vshl.u8 q8, q9, q8 +0x50,0xff,0xe2,0x04 = vshl.u16 q8, q9, q8 +0x60,0xff,0xe2,0x04 = vshl.u32 q8, q9, q8 +0x70,0xff,0xe2,0x04 = vshl.u64 q8, q9, q8 +0xcf,0xef,0x70,0x05 = vshl.i8 q8, q8, #7 +0xdf,0xef,0x70,0x05 = vshl.i16 q8, q8, #0xf +0xff,0xef,0x70,0x05 = vshl.i32 q8, q8, #0x1f +0xff,0xef,0xf0,0x05 = vshl.i64 q8, q8, #0x3f +0xc8,0xff,0x30,0x00 = vshr.u8 d16, d16, #8 +0xd0,0xff,0x30,0x00 = vshr.u16 d16, d16, #0x10 +0xe0,0xff,0x30,0x00 = vshr.u32 d16, d16, #0x20 +0xc0,0xff,0xb0,0x00 = vshr.u64 d16, d16, #0x40 +0xc8,0xff,0x70,0x00 = vshr.u8 q8, q8, #8 +0xd0,0xff,0x70,0x00 = vshr.u16 q8, q8, #0x10 +0xe0,0xff,0x70,0x00 = vshr.u32 q8, q8, #0x20 +0xc0,0xff,0xf0,0x00 = vshr.u64 q8, q8, #0x40 +0xc8,0xef,0x30,0x00 = vshr.s8 d16, d16, #8 +0xd0,0xef,0x30,0x00 = vshr.s16 d16, d16, #0x10 +0xe0,0xef,0x30,0x00 = vshr.s32 d16, d16, #0x20 +0xc0,0xef,0xb0,0x00 = vshr.s64 d16, d16, #0x40 +0xc8,0xef,0x70,0x00 = vshr.s8 q8, q8, #8 +0xd0,0xef,0x70,0x00 = vshr.s16 q8, q8, #0x10 +0xe0,0xef,0x70,0x00 = vshr.s32 q8, q8, #0x20 +0xc0,0xef,0xf0,0x00 = vshr.s64 q8, q8, #0x40 +0xcf,0xef,0x30,0x0a = vshll.s8 q8, d16, #7 +0xdf,0xef,0x30,0x0a = vshll.s16 q8, d16, #0xf +0xff,0xef,0x30,0x0a = vshll.s32 q8, d16, #0x1f +0xcf,0xff,0x30,0x0a = vshll.u8 q8, d16, #7 +0xdf,0xff,0x30,0x0a = vshll.u16 q8, d16, #0xf +0xff,0xff,0x30,0x0a = vshll.u32 q8, d16, #0x1f +0xf2,0xff,0x20,0x03 = vshll.i8 q8, d16, #8 +0xf6,0xff,0x20,0x03 = vshll.i16 q8, d16, #0x10 +0xfa,0xff,0x20,0x03 = vshll.i32 q8, d16, #0x20 +0xc8,0xef,0x30,0x08 = vshrn.i16 d16, q8, #8 +0xd0,0xef,0x30,0x08 = vshrn.i32 d16, q8, #0x10 +0xe0,0xef,0x30,0x08 = vshrn.i64 d16, q8, #0x20 +0x40,0xef,0xa1,0x05 = vrshl.s8 d16, d17, d16 +0x50,0xef,0xa1,0x05 = vrshl.s16 d16, d17, d16 +0x60,0xef,0xa1,0x05 = vrshl.s32 d16, d17, d16 +0x70,0xef,0xa1,0x05 = vrshl.s64 d16, d17, d16 +0x40,0xff,0xa1,0x05 = vrshl.u8 d16, d17, d16 +0x50,0xff,0xa1,0x05 = vrshl.u16 d16, d17, d16 +0x60,0xff,0xa1,0x05 = vrshl.u32 d16, d17, d16 +0x70,0xff,0xa1,0x05 = vrshl.u64 d16, d17, d16 +0x40,0xef,0xe2,0x05 = vrshl.s8 q8, q9, q8 +0x50,0xef,0xe2,0x05 = vrshl.s16 q8, q9, q8 +0x60,0xef,0xe2,0x05 = vrshl.s32 q8, q9, q8 +0x70,0xef,0xe2,0x05 = vrshl.s64 q8, q9, q8 +0x40,0xff,0xe2,0x05 = vrshl.u8 q8, q9, q8 +0x50,0xff,0xe2,0x05 = vrshl.u16 q8, q9, q8 +0x60,0xff,0xe2,0x05 = vrshl.u32 q8, q9, q8 +0x70,0xff,0xe2,0x05 = vrshl.u64 q8, q9, q8 +0xc8,0xef,0x30,0x02 = vrshr.s8 d16, d16, #8 +0xd0,0xef,0x30,0x02 = vrshr.s16 d16, d16, #0x10 +0xe0,0xef,0x30,0x02 = vrshr.s32 d16, d16, #0x20 +0xc0,0xef,0xb0,0x02 = vrshr.s64 d16, d16, #0x40 +0xc8,0xff,0x30,0x02 = vrshr.u8 d16, d16, #8 +0xd0,0xff,0x30,0x02 = vrshr.u16 d16, d16, #0x10 +0xe0,0xff,0x30,0x02 = vrshr.u32 d16, d16, #0x20 +0xc0,0xff,0xb0,0x02 = vrshr.u64 d16, d16, #0x40 +0xc8,0xef,0x70,0x02 = vrshr.s8 q8, q8, #8 +0xd0,0xef,0x70,0x02 = vrshr.s16 q8, q8, #0x10 +0xe0,0xef,0x70,0x02 = vrshr.s32 q8, q8, #0x20 +0xc0,0xef,0xf0,0x02 = vrshr.s64 q8, q8, #0x40 +0xc8,0xff,0x70,0x02 = vrshr.u8 q8, q8, #8 +0xd0,0xff,0x70,0x02 = vrshr.u16 q8, q8, #0x10 +0xe0,0xff,0x70,0x02 = vrshr.u32 q8, q8, #0x20 +0xc0,0xff,0xf0,0x02 = vrshr.u64 q8, q8, #0x40 +0xc8,0xef,0x70,0x08 = vrshrn.i16 d16, q8, #8 +0xd0,0xef,0x70,0x08 = vrshrn.i32 d16, q8, #0x10 +0xe0,0xef,0x70,0x08 = vrshrn.i64 d16, q8, #0x20 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-shiftaccum-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-shiftaccum-encoding.s.cs new file mode 100644 index 0000000..fb300d9 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-shiftaccum-encoding.s.cs @@ -0,0 +1,97 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xc8,0xef,0x30,0x11 = vsra.s8 d17, d16, #8 +0x90,0xef,0x1e,0xf1 = vsra.s16 d15, d14, #0x10 +0xa0,0xef,0x1c,0xd1 = vsra.s32 d13, d12, #0x20 +0x80,0xef,0x9a,0xb1 = vsra.s64 d11, d10, #0x40 +0x88,0xef,0x54,0xe1 = vsra.s8 q7, q2, #8 +0x90,0xef,0x5c,0x61 = vsra.s16 q3, q6, #0x10 +0xe0,0xef,0x5a,0x21 = vsra.s32 q9, q5, #0x20 +0xc0,0xef,0xd8,0x01 = vsra.s64 q8, q4, #0x40 +0xc8,0xff,0x30,0x11 = vsra.u8 d17, d16, #8 +0x95,0xff,0x1e,0xb1 = vsra.u16 d11, d14, #0xb +0xaa,0xff,0x1f,0xc1 = vsra.u32 d12, d15, #0x16 +0x8a,0xff,0xb0,0xd1 = vsra.u64 d13, d16, #0x36 +0x88,0xff,0x5e,0x21 = vsra.u8 q1, q7, #8 +0x9a,0xff,0x5e,0x41 = vsra.u16 q2, q7, #6 +0xab,0xff,0x5c,0x61 = vsra.u32 q3, q6, #0x15 +0xa7,0xff,0xda,0x81 = vsra.u64 q4, q5, #0x19 +0xc8,0xef,0x30,0x01 = vsra.s8 d16, d16, #8 +0x90,0xef,0x1e,0xe1 = vsra.s16 d14, d14, #0x10 +0xa0,0xef,0x1c,0xc1 = vsra.s32 d12, d12, #0x20 +0x80,0xef,0x9a,0xa1 = vsra.s64 d10, d10, #0x40 +0x88,0xef,0x54,0x41 = vsra.s8 q2, q2, #8 +0x90,0xef,0x5c,0xc1 = vsra.s16 q6, q6, #0x10 +0xa0,0xef,0x5a,0xa1 = vsra.s32 q5, q5, #0x20 +0x80,0xef,0xd8,0x81 = vsra.s64 q4, q4, #0x40 +0xc8,0xff,0x30,0x01 = vsra.u8 d16, d16, #8 +0x95,0xff,0x1e,0xe1 = vsra.u16 d14, d14, #0xb +0xaa,0xff,0x1f,0xf1 = vsra.u32 d15, d15, #0x16 +0xca,0xff,0xb0,0x01 = vsra.u64 d16, d16, #0x36 +0x88,0xff,0x5e,0xe1 = vsra.u8 q7, q7, #8 +0x9a,0xff,0x5e,0xe1 = vsra.u16 q7, q7, #6 +0xab,0xff,0x5c,0xc1 = vsra.u32 q6, q6, #0x15 +0xa7,0xff,0xda,0xa1 = vsra.u64 q5, q5, #0x19 +0x88,0xef,0x3a,0x53 = vrsra.s8 d5, d26, #8 +0x90,0xef,0x39,0x63 = vrsra.s16 d6, d25, #0x10 +0xa0,0xef,0x38,0x73 = vrsra.s32 d7, d24, #0x20 +0x80,0xef,0xb7,0xe3 = vrsra.s64 d14, d23, #0x40 +0x88,0xff,0x36,0xf3 = vrsra.u8 d15, d22, #8 +0xd0,0xff,0x35,0x03 = vrsra.u16 d16, d21, #0x10 +0xe0,0xff,0x34,0x13 = vrsra.u32 d17, d20, #0x20 +0xc0,0xff,0xb3,0x23 = vrsra.u64 d18, d19, #0x40 +0x88,0xef,0x54,0x23 = vrsra.s8 q1, q2, #8 +0x90,0xef,0x56,0x43 = vrsra.s16 q2, q3, #0x10 +0xa0,0xef,0x58,0x63 = vrsra.s32 q3, q4, #0x20 +0x80,0xef,0xda,0x83 = vrsra.s64 q4, q5, #0x40 +0x88,0xff,0x5c,0xa3 = vrsra.u8 q5, q6, #8 +0x90,0xff,0x5e,0xc3 = vrsra.u16 q6, q7, #0x10 +0xa0,0xff,0x70,0xe3 = vrsra.u32 q7, q8, #0x20 +0xc0,0xff,0xf2,0x03 = vrsra.u64 q8, q9, #0x40 +0xc8,0xef,0x3a,0xa3 = vrsra.s8 d26, d26, #8 +0xd0,0xef,0x39,0x93 = vrsra.s16 d25, d25, #0x10 +0xe0,0xef,0x38,0x83 = vrsra.s32 d24, d24, #0x20 +0xc0,0xef,0xb7,0x73 = vrsra.s64 d23, d23, #0x40 +0xc8,0xff,0x36,0x63 = vrsra.u8 d22, d22, #8 +0xd0,0xff,0x35,0x53 = vrsra.u16 d21, d21, #0x10 +0xe0,0xff,0x34,0x43 = vrsra.u32 d20, d20, #0x20 +0xc0,0xff,0xb3,0x33 = vrsra.u64 d19, d19, #0x40 +0x88,0xef,0x54,0x43 = vrsra.s8 q2, q2, #8 +0x90,0xef,0x56,0x63 = vrsra.s16 q3, q3, #0x10 +0xa0,0xef,0x58,0x83 = vrsra.s32 q4, q4, #0x20 +0x80,0xef,0xda,0xa3 = vrsra.s64 q5, q5, #0x40 +0x88,0xff,0x5c,0xc3 = vrsra.u8 q6, q6, #8 +0x90,0xff,0x5e,0xe3 = vrsra.u16 q7, q7, #0x10 +0xe0,0xff,0x70,0x03 = vrsra.u32 q8, q8, #0x20 +0xc0,0xff,0xf2,0x23 = vrsra.u64 q9, q9, #0x40 +0x8f,0xff,0x1c,0xb5 = vsli.8 d11, d12, #7 +0x9f,0xff,0x1d,0xc5 = vsli.16 d12, d13, #0xf +0xbf,0xff,0x1e,0xd5 = vsli.32 d13, d14, #0x1f +0xbf,0xff,0x9f,0xe5 = vsli.64 d14, d15, #0x3f +0x8f,0xff,0x70,0x25 = vsli.8 q1, q8, #7 +0x9f,0xff,0x5e,0x45 = vsli.16 q2, q7, #0xf +0xbf,0xff,0x58,0x65 = vsli.32 q3, q4, #0x1f +0xbf,0xff,0xda,0x85 = vsli.64 q4, q5, #0x3f +0xc8,0xff,0x1b,0xc4 = vsri.8 d28, d11, #8 +0xd0,0xff,0x1c,0xa4 = vsri.16 d26, d12, #0x10 +0xe0,0xff,0x1d,0x84 = vsri.32 d24, d13, #0x20 +0xc0,0xff,0x9e,0x54 = vsri.64 d21, d14, #0x40 +0x88,0xff,0x70,0x24 = vsri.8 q1, q8, #8 +0x90,0xff,0x54,0xa4 = vsri.16 q5, q2, #0x10 +0xa0,0xff,0x58,0xe4 = vsri.32 q7, q4, #0x20 +0xc0,0xff,0xdc,0x24 = vsri.64 q9, q6, #0x40 +0x8f,0xff,0x1c,0xc5 = vsli.8 d12, d12, #7 +0x9f,0xff,0x1d,0xd5 = vsli.16 d13, d13, #0xf +0xbf,0xff,0x1e,0xe5 = vsli.32 d14, d14, #0x1f +0xbf,0xff,0x9f,0xf5 = vsli.64 d15, d15, #0x3f +0xcf,0xff,0x70,0x05 = vsli.8 q8, q8, #7 +0x9f,0xff,0x5e,0xe5 = vsli.16 q7, q7, #0xf +0xbf,0xff,0x58,0x85 = vsli.32 q4, q4, #0x1f +0xbf,0xff,0xda,0xa5 = vsli.64 q5, q5, #0x3f +0x88,0xff,0x1b,0xb4 = vsri.8 d11, d11, #8 +0x90,0xff,0x1c,0xc4 = vsri.16 d12, d12, #0x10 +0xa0,0xff,0x1d,0xd4 = vsri.32 d13, d13, #0x20 +0x80,0xff,0x9e,0xe4 = vsri.64 d14, d14, #0x40 +0xc8,0xff,0x70,0x04 = vsri.8 q8, q8, #8 +0x90,0xff,0x54,0x44 = vsri.16 q2, q2, #0x10 +0xa0,0xff,0x58,0x84 = vsri.32 q4, q4, #0x20 +0x80,0xff,0xdc,0xc4 = vsri.64 q6, q6, #0x40 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-shuffle-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-shuffle-encoding.s.cs new file mode 100644 index 0000000..151d905 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-shuffle-encoding.s.cs @@ -0,0 +1,23 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xf1,0xef,0xa0,0x03 = vext.8 d16, d17, d16, #3 +0xf1,0xef,0xa0,0x05 = vext.8 d16, d17, d16, #5 +0xf2,0xef,0xe0,0x03 = vext.8 q8, q9, q8, #3 +0xf2,0xef,0xe0,0x07 = vext.8 q8, q9, q8, #7 +0xf1,0xef,0xa0,0x06 = vext.16 d16, d17, d16, #3 +0xf2,0xef,0xe0,0x0c = vext.32 q8, q9, q8, #3 +0xf2,0xff,0xa0,0x10 = vtrn.8 d17, d16 +0xf6,0xff,0xa0,0x10 = vtrn.16 d17, d16 +0xfa,0xff,0xa0,0x10 = vtrn.32 d17, d16 +0xf2,0xff,0xe0,0x20 = vtrn.8 q9, q8 +0xf6,0xff,0xe0,0x20 = vtrn.16 q9, q8 +0xfa,0xff,0xe0,0x20 = vtrn.32 q9, q8 +0xf2,0xff,0x20,0x11 = vuzp.8 d17, d16 +0xf6,0xff,0x20,0x11 = vuzp.16 d17, d16 +0xf2,0xff,0x60,0x21 = vuzp.8 q9, q8 +0xf6,0xff,0x60,0x21 = vuzp.16 q9, q8 +0xfa,0xff,0x60,0x21 = vuzp.32 q9, q8 +0xf2,0xff,0xa0,0x11 = vzip.8 d17, d16 +0xf6,0xff,0xa0,0x11 = vzip.16 d17, d16 +0xf2,0xff,0xe0,0x21 = vzip.8 q9, q8 +0xf6,0xff,0xe0,0x21 = vzip.16 q9, q8 +0xfa,0xff,0xe0,0x21 = vzip.32 q9, q8 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-sub-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-sub-encoding.s.cs new file mode 100644 index 0000000..151d905 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-sub-encoding.s.cs @@ -0,0 +1,23 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xf1,0xef,0xa0,0x03 = vext.8 d16, d17, d16, #3 +0xf1,0xef,0xa0,0x05 = vext.8 d16, d17, d16, #5 +0xf2,0xef,0xe0,0x03 = vext.8 q8, q9, q8, #3 +0xf2,0xef,0xe0,0x07 = vext.8 q8, q9, q8, #7 +0xf1,0xef,0xa0,0x06 = vext.16 d16, d17, d16, #3 +0xf2,0xef,0xe0,0x0c = vext.32 q8, q9, q8, #3 +0xf2,0xff,0xa0,0x10 = vtrn.8 d17, d16 +0xf6,0xff,0xa0,0x10 = vtrn.16 d17, d16 +0xfa,0xff,0xa0,0x10 = vtrn.32 d17, d16 +0xf2,0xff,0xe0,0x20 = vtrn.8 q9, q8 +0xf6,0xff,0xe0,0x20 = vtrn.16 q9, q8 +0xfa,0xff,0xe0,0x20 = vtrn.32 q9, q8 +0xf2,0xff,0x20,0x11 = vuzp.8 d17, d16 +0xf6,0xff,0x20,0x11 = vuzp.16 d17, d16 +0xf2,0xff,0x60,0x21 = vuzp.8 q9, q8 +0xf6,0xff,0x60,0x21 = vuzp.16 q9, q8 +0xfa,0xff,0x60,0x21 = vuzp.32 q9, q8 +0xf2,0xff,0xa0,0x11 = vzip.8 d17, d16 +0xf6,0xff,0xa0,0x11 = vzip.16 d17, d16 +0xf2,0xff,0xe0,0x21 = vzip.8 q9, q8 +0xf6,0xff,0xe0,0x21 = vzip.16 q9, q8 +0xfa,0xff,0xe0,0x21 = vzip.32 q9, q8 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-table-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-table-encoding.s.cs new file mode 100644 index 0000000..f2d43c1 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-table-encoding.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xf1,0xff,0xa0,0x08 = vtbl.8 d16, {d17}, d16 +0xf0,0xff,0xa2,0x09 = vtbl.8 d16, {d16, d17}, d18 +0xf0,0xff,0xa4,0x0a = vtbl.8 d16, {d16, d17, d18}, d20 +0xf0,0xff,0xa4,0x0b = vtbl.8 d16, {d16, d17, d18, d19}, d20 +0xf0,0xff,0xe1,0x28 = vtbx.8 d18, {d16}, d17 +0xf0,0xff,0xe2,0x39 = vtbx.8 d19, {d16, d17}, d18 +0xf0,0xff,0xe5,0x4a = vtbx.8 d20, {d16, d17, d18}, d21 +0xf0,0xff,0xe5,0x4b = vtbx.8 d20, {d16, d17, d18, d19}, d21 diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-vld-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-vld-encoding.s.cs new file mode 100644 index 0000000..85c3b70 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-vld-encoding.s.cs @@ -0,0 +1,51 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x60,0xf9,0x1f,0x07 = vld1.8 {d16}, [r0:64] +0x60,0xf9,0x4f,0x07 = vld1.16 {d16}, [r0] +0x60,0xf9,0x8f,0x07 = vld1.32 {d16}, [r0] +0x60,0xf9,0xcf,0x07 = vld1.64 {d16}, [r0] +0x60,0xf9,0x1f,0x0a = vld1.8 {d16, d17}, [r0:64] +0x60,0xf9,0x6f,0x0a = vld1.16 {d16, d17}, [r0:128] +0x60,0xf9,0x8f,0x0a = vld1.32 {d16, d17}, [r0] +0x60,0xf9,0xcf,0x0a = vld1.64 {d16, d17}, [r0] +0x60,0xf9,0x1f,0x08 = vld2.8 {d16, d17}, [r0:64] +0x60,0xf9,0x6f,0x08 = vld2.16 {d16, d17}, [r0:128] +0x60,0xf9,0x8f,0x08 = vld2.32 {d16, d17}, [r0] +0x60,0xf9,0x1f,0x03 = vld2.8 {d16, d17, d18, d19}, [r0:64] +0x60,0xf9,0x6f,0x03 = vld2.16 {d16, d17, d18, d19}, [r0:128] +0x60,0xf9,0xbf,0x03 = vld2.32 {d16, d17, d18, d19}, [r0:256] +0x60,0xf9,0x1f,0x04 = vld3.8 {d16, d17, d18}, [r0:64] +0x60,0xf9,0x4f,0x04 = vld3.16 {d16, d17, d18}, [r0] +0x60,0xf9,0x8f,0x04 = vld3.32 {d16, d17, d18}, [r0] +0x60,0xf9,0x1d,0x05 = vld3.8 {d16, d18, d20}, [r0:64]! +0x60,0xf9,0x1d,0x15 = vld3.8 {d17, d19, d21}, [r0:64]! +0x60,0xf9,0x4d,0x05 = vld3.16 {d16, d18, d20}, [r0]! +0x60,0xf9,0x4d,0x15 = vld3.16 {d17, d19, d21}, [r0]! +0x60,0xf9,0x8d,0x05 = vld3.32 {d16, d18, d20}, [r0]! +0x60,0xf9,0x8d,0x15 = vld3.32 {d17, d19, d21}, [r0]! +0x60,0xf9,0x1f,0x00 = vld4.8 {d16, d17, d18, d19}, [r0:64] +0x60,0xf9,0x6f,0x00 = vld4.16 {d16, d17, d18, d19}, [r0:128] +0x60,0xf9,0xbf,0x00 = vld4.32 {d16, d17, d18, d19}, [r0:256] +0x60,0xf9,0x3d,0x01 = vld4.8 {d16, d18, d20, d22}, [r0:256]! +0x60,0xf9,0x3d,0x11 = vld4.8 {d17, d19, d21, d23}, [r0:256]! +0x60,0xf9,0x4d,0x01 = vld4.16 {d16, d18, d20, d22}, [r0]! +0x60,0xf9,0x4d,0x11 = vld4.16 {d17, d19, d21, d23}, [r0]! +0x60,0xf9,0x8d,0x01 = vld4.32 {d16, d18, d20, d22}, [r0]! +0x60,0xf9,0x8d,0x11 = vld4.32 {d17, d19, d21, d23}, [r0]! +0xe0,0xf9,0x6f,0x00 = vld1.8 {d16[3]}, [r0] +0xe0,0xf9,0x9f,0x04 = vld1.16 {d16[2]}, [r0:16] +0xe0,0xf9,0xbf,0x08 = vld1.32 {d16[1]}, [r0:32] +0xe0,0xf9,0x3f,0x01 = vld2.8 {d16[1], d17[1]}, [r0:16] +0xe0,0xf9,0x5f,0x05 = vld2.16 {d16[1], d17[1]}, [r0:32] +0xe0,0xf9,0x8f,0x09 = vld2.32 {d16[1], d17[1]}, [r0] +0xe0,0xf9,0x6f,0x15 = vld2.16 {d17[1], d19[1]}, [r0] +0xe0,0xf9,0x5f,0x19 = vld2.32 {d17[0], d19[0]}, [r0:64] +0xe0,0xf9,0x2f,0x02 = vld3.8 {d16[1], d17[1], d18[1]}, [r0] +0xe0,0xf9,0x4f,0x06 = vld3.16 {d16[1], d17[1], d18[1]}, [r0] +0xe0,0xf9,0x8f,0x0a = vld3.32 {d16[1], d17[1], d18[1]}, [r0] +0xe0,0xf9,0x6f,0x06 = vld3.16 {d16[1], d18[1], d20[1]}, [r0] +0xe0,0xf9,0xcf,0x1a = vld3.32 {d17[1], d19[1], d21[1]}, [r0] +0xe0,0xf9,0x3f,0x03 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] +0xe0,0xf9,0x4f,0x07 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +0xe0,0xf9,0xaf,0x0b = vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] +0xe0,0xf9,0x7f,0x07 = vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64] +0xe0,0xf9,0x4f,0x1b = vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] diff --git a/thirdparty/capstone/suite/MC/ARM/neont2-vst-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/neont2-vst-encoding.s.cs new file mode 100644 index 0000000..a719925 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/neont2-vst-encoding.s.cs @@ -0,0 +1,48 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x40,0xf9,0x1f,0x07 = vst1.8 {d16}, [r0:64] +0x40,0xf9,0x4f,0x07 = vst1.16 {d16}, [r0] +0x40,0xf9,0x8f,0x07 = vst1.32 {d16}, [r0] +0x40,0xf9,0xcf,0x07 = vst1.64 {d16}, [r0] +0x40,0xf9,0x1f,0x0a = vst1.8 {d16, d17}, [r0:64] +0x40,0xf9,0x6f,0x0a = vst1.16 {d16, d17}, [r0:128] +0x40,0xf9,0x8f,0x0a = vst1.32 {d16, d17}, [r0] +0x40,0xf9,0xcf,0x0a = vst1.64 {d16, d17}, [r0] +0x40,0xf9,0x1f,0x08 = vst2.8 {d16, d17}, [r0:64] +0x40,0xf9,0x6f,0x08 = vst2.16 {d16, d17}, [r0:128] +0x40,0xf9,0x8f,0x08 = vst2.32 {d16, d17}, [r0] +0x40,0xf9,0x1f,0x03 = vst2.8 {d16, d17, d18, d19}, [r0:64] +0x40,0xf9,0x6f,0x03 = vst2.16 {d16, d17, d18, d19}, [r0:128] +0x40,0xf9,0xbf,0x03 = vst2.32 {d16, d17, d18, d19}, [r0:256] +0x40,0xf9,0x1f,0x04 = vst3.8 {d16, d17, d18}, [r0:64] +0x40,0xf9,0x4f,0x04 = vst3.16 {d16, d17, d18}, [r0] +0x40,0xf9,0x8f,0x04 = vst3.32 {d16, d17, d18}, [r0] +0x40,0xf9,0x1d,0x05 = vst3.8 {d16, d18, d20}, [r0:64]! +0x40,0xf9,0x1d,0x15 = vst3.8 {d17, d19, d21}, [r0:64]! +0x40,0xf9,0x4d,0x05 = vst3.16 {d16, d18, d20}, [r0]! +0x40,0xf9,0x4d,0x15 = vst3.16 {d17, d19, d21}, [r0]! +0x40,0xf9,0x8d,0x05 = vst3.32 {d16, d18, d20}, [r0]! +0x40,0xf9,0x8d,0x15 = vst3.32 {d17, d19, d21}, [r0]! +0x40,0xf9,0x1f,0x00 = vst4.8 {d16, d17, d18, d19}, [r0:64] +0x40,0xf9,0x6f,0x00 = vst4.16 {d16, d17, d18, d19}, [r0:128] +0x40,0xf9,0x3d,0x01 = vst4.8 {d16, d18, d20, d22}, [r0:256]! +0x40,0xf9,0x3d,0x11 = vst4.8 {d17, d19, d21, d23}, [r0:256]! +0x40,0xf9,0x4d,0x01 = vst4.16 {d16, d18, d20, d22}, [r0]! +0x40,0xf9,0x4d,0x11 = vst4.16 {d17, d19, d21, d23}, [r0]! +0x40,0xf9,0x8d,0x01 = vst4.32 {d16, d18, d20, d22}, [r0]! +0x40,0xf9,0x8d,0x11 = vst4.32 {d17, d19, d21, d23}, [r0]! +0xc0,0xf9,0x3f,0x01 = vst2.8 {d16[1], d17[1]}, [r0:16] +0xc0,0xf9,0x5f,0x05 = vst2.16 {d16[1], d17[1]}, [r0:32] +0xc0,0xf9,0x8f,0x09 = vst2.32 {d16[1], d17[1]}, [r0] +0xc0,0xf9,0x6f,0x15 = vst2.16 {d17[1], d19[1]}, [r0] +0xc0,0xf9,0x5f,0x19 = vst2.32 {d17[0], d19[0]}, [r0:64] +0xc0,0xf9,0x2f,0x02 = vst3.8 {d16[1], d17[1], d18[1]}, [r0] +0xc0,0xf9,0x4f,0x06 = vst3.16 {d16[1], d17[1], d18[1]}, [r0] +0xc0,0xf9,0x8f,0x0a = vst3.32 {d16[1], d17[1], d18[1]}, [r0] +0xc0,0xf9,0xaf,0x16 = vst3.16 {d17[2], d19[2], d21[2]}, [r0] +0xc0,0xf9,0x4f,0x0a = vst3.32 {d16[0], d18[0], d20[0]}, [r0] +0xc0,0xf9,0x3f,0x03 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] +0xc0,0xf9,0x4f,0x07 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +0xc0,0xf9,0xaf,0x0b = vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] +0xc0,0xf9,0xff,0x17 = vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] +0xc0,0xf9,0x4f,0x1b = vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] +0x04,0xf9,0x0f,0x89 = vst2.8 {d8, d10}, [r4] diff --git a/thirdparty/capstone/suite/MC/ARM/simple-fp-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/simple-fp-encoding.s.cs new file mode 100644 index 0000000..c8ec770 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/simple-fp-encoding.s.cs @@ -0,0 +1,177 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16 +0x80,0x0a,0x30,0xee = vadd.f32 s0, s1, s0 +0xe0,0x0b,0x71,0xee = vsub.f64 d16, d17, d16 +0xc0,0x0a,0x30,0xee = vsub.f32 s0, s1, s0 +0xa0,0x0b,0xc1,0xee = vdiv.f64 d16, d17, d16 +0x80,0x0a,0x80,0xee = vdiv.f32 s0, s1, s0 +0xa3,0x2a,0xc2,0xee = vdiv.f32 s5, s5, s7 +0x07,0x5b,0x85,0xee = vdiv.f64 d5, d5, d7 +0xa0,0x0b,0x61,0xee = vmul.f64 d16, d17, d16 +0xa1,0x4b,0x64,0xee = vmul.f64 d20, d20, d17 +0x80,0x0a,0x20,0xee = vmul.f32 s0, s1, s0 +0xaa,0x5a,0x65,0xee = vmul.f32 s11, s11, s21 +0xe0,0x0b,0x61,0xee = vnmul.f64 d16, d17, d16 +0xc0,0x0a,0x20,0xee = vnmul.f32 s0, s1, s0 +0x60,0x1b,0xf4,0xee = vcmp.f64 d17, d16 +0x40,0x0a,0xf4,0xee = vcmp.f32 s1, s0 +0x40,0x1b,0xf5,0xee = vcmp.f64 d17, #0 +0x40,0x0a,0xf5,0xee = vcmp.f32 s1, #0 +0xe0,0x1b,0xf4,0xee = vcmpe.f64 d17, d16 +0xc0,0x0a,0xf4,0xee = vcmpe.f32 s1, s0 +0xc0,0x0b,0xf5,0xee = vcmpe.f64 d16, #0 +0xc0,0x0a,0xb5,0xee = vcmpe.f32 s0, #0 +0xe0,0x0b,0xf0,0xee = vabs.f64 d16, d16 +0xc0,0x0a,0xb0,0xee = vabs.f32 s0, s0 +0xe0,0x0b,0xb7,0xee = vcvt.f32.f64 s0, d16 +0xc0,0x0a,0xf7,0xee = vcvt.f64.f32 d16, s0 +0x60,0x0b,0xf1,0xee = vneg.f64 d16, d16 +0x40,0x0a,0xb1,0xee = vneg.f32 s0, s0 +0xe0,0x0b,0xf1,0xee = vsqrt.f64 d16, d16 +0xc0,0x0a,0xb1,0xee = vsqrt.f32 s0, s0 +0xc0,0x0b,0xf8,0xee = vcvt.f64.s32 d16, s0 +0xc0,0x0a,0xb8,0xee = vcvt.f32.s32 s0, s0 +0x40,0x0b,0xf8,0xee = vcvt.f64.u32 d16, s0 +0x40,0x0a,0xb8,0xee = vcvt.f32.u32 s0, s0 +0xe0,0x0b,0xbd,0xee = vcvt.s32.f64 s0, d16 +0xc0,0x0a,0xbd,0xee = vcvt.s32.f32 s0, s0 +0xe0,0x0b,0xbc,0xee = vcvt.u32.f64 s0, d16 +0xc0,0x0a,0xbc,0xee = vcvt.u32.f32 s0, s0 +0xa1,0x0b,0x42,0xee = vmla.f64 d16, d18, d17 +0x00,0x0a,0x41,0xee = vmla.f32 s1, s2, s0 +0xe1,0x0b,0x42,0xee = vmls.f64 d16, d18, d17 +0x40,0x0a,0x41,0xee = vmls.f32 s1, s2, s0 +0xe1,0x0b,0x52,0xee = vnmla.f64 d16, d18, d17 +0x40,0x0a,0x51,0xee = vnmla.f32 s1, s2, s0 +0xa1,0x0b,0x52,0xee = vnmls.f64 d16, d18, d17 +0x00,0x0a,0x51,0xee = vnmls.f32 s1, s2, s0 +0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr +0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr +0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr +0x10,0x2a,0xf0,0xee = vmrs r2, fpsid +0x10,0x3a,0xf0,0xee = vmrs r3, fpsid +0x10,0x4a,0xf7,0xee = vmrs r4, mvfr0 +0x10,0x5a,0xf6,0xee = vmrs r5, mvfr1 +0x60,0x0b,0xf1,0x1e = vnegne.f64 d16, d16 +0x10,0x0a,0x00,0x1e = vmovne s0, r0 +0x10,0x1a,0x00,0x0e = vmoveq s0, r1 +0x10,0x1a,0x11,0xee = vmov r1, s2 +0x10,0x3a,0x02,0xee = vmov s4, r3 +0x12,0x1b,0x55,0xec = vmov r1, r5, d2 +0x14,0x3b,0x49,0xec = vmov d4, r3, r9 +0x10,0x0a,0xf1,0xee = vmrs r0, fpscr +0x10,0x0a,0xf8,0xee = vmrs r0, fpexc +0x10,0x0a,0xf0,0xee = vmrs r0, fpsid +0x10,0x1a,0xf9,0xee = vmrs r1, fpinst +0x10,0x8a,0xfa,0xee = vmrs r8, fpinst2 +0x10,0x0a,0xe1,0xee = vmsr fpscr, r0 +0x10,0x0a,0xe8,0xee = vmsr fpexc, r0 +0x10,0x0a,0xe0,0xee = vmsr fpsid, r0 +0x10,0x3a,0xe9,0xee = vmsr fpinst, r3 +0x10,0x4a,0xea,0xee = vmsr fpinst2, r4 +0x08,0x0b,0xf0,0xee = vmov.f64 d16, #3.000000e+00 +0x08,0x0a,0xb0,0xee = vmov.f32 s0, #3.000000e+00 +0x08,0x0b,0xf8,0xee = vmov.f64 d16, #-3.000000e+00 +0x08,0x0a,0xb8,0xee = vmov.f32 s0, #-3.000000e+00 +0x10,0x0a,0x00,0xee = vmov s0, r0 +0x90,0x1a,0x00,0xee = vmov s1, r1 +0x10,0x2a,0x01,0xee = vmov s2, r2 +0x90,0x3a,0x01,0xee = vmov s3, r3 +0x10,0x0a,0x10,0xee = vmov r0, s0 +0x90,0x1a,0x10,0xee = vmov r1, s1 +0x10,0x2a,0x11,0xee = vmov r2, s2 +0x90,0x3a,0x11,0xee = vmov r3, s3 +0x30,0x0b,0x51,0xec = vmov r0, r1, d16 +0x31,0x1a,0x42,0xec = vmov s3, s4, r1, r2 +0x11,0x1a,0x42,0xec = vmov s2, s3, r1, r2 +0x31,0x1a,0x52,0xec = vmov r1, r2, s3, s4 +0x11,0x1a,0x52,0xec = vmov r1, r2, s2, s3 +0x1f,0x1b,0x42,0xec = vmov d15, r1, r2 +0x30,0x1b,0x42,0xec = vmov d16, r1, r2 +0x1f,0x1b,0x52,0xec = vmov r1, r2, d15 +0x30,0x1b,0x52,0xec = vmov r1, r2, d16 +0x00,0x1b,0xd0,0xed = vldr d17, [r0] +0x00,0x0a,0x9e,0xed = vldr s0, [lr] +0x00,0x0b,0x9e,0xed = vldr d0, [lr] +0x08,0x1b,0x92,0xed = vldr d1, [r2, #0x20] +0x08,0x1b,0x12,0xed = vldr d1, [r2, #-0x20] +0x00,0x2b,0x93,0xed = vldr d2, [r3] +0x00,0x3b,0x9f,0xed = vldr d3, [pc] +0x00,0x3b,0x9f,0xed = vldr d3, [pc] +0x00,0x3b,0x1f,0xed = vldr d3, [pc, #-0] +0x00,0x6a,0xd0,0xed = vldr s13, [r0] +0x08,0x0a,0xd2,0xed = vldr s1, [r2, #0x20] +0x08,0x0a,0x52,0xed = vldr s1, [r2, #-0x20] +0x00,0x1a,0x93,0xed = vldr s2, [r3] +0x00,0x2a,0xdf,0xed = vldr s5, [pc] +0x00,0x2a,0xdf,0xed = vldr s5, [pc] +0x00,0x2a,0x5f,0xed = vldr s5, [pc, #-0] +0x00,0x4b,0x81,0xed = vstr d4, [r1] +0x06,0x4b,0x81,0xed = vstr d4, [r1, #0x18] +0x06,0x4b,0x01,0xed = vstr d4, [r1, #-0x18] +0x00,0x0a,0x8e,0xed = vstr s0, [lr] +0x00,0x0b,0x8e,0xed = vstr d0, [lr] +0x00,0x2a,0x81,0xed = vstr s4, [r1] +0x06,0x2a,0x81,0xed = vstr s4, [r1, #0x18] +0x06,0x2a,0x01,0xed = vstr s4, [r1, #-0x18] +0x0c,0x2b,0x91,0xec = vldmia r1, {d2, d3, d4, d5, d6, d7} +0x06,0x1a,0x91,0xec = vldmia r1, {s2, s3, s4, s5, s6, s7} +0x0c,0x2b,0x81,0xec = vstmia r1, {d2, d3, d4, d5, d6, d7} +0x06,0x1a,0x81,0xec = vstmia r1, {s2, s3, s4, s5, s6, s7} +0x10,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12, d13, d14, d15} +0x07,0x0b,0xb5,0xec = fldmiax r5!, {d0, d1, d2} +0x05,0x4b,0x90,0x0c = fldmiaxeq r0, {d4, d5} +0x07,0x4b,0x35,0x1d = fldmdbxne r5!, {d4, d5, d6} +0x11,0x0b,0xa5,0xec = fstmiax r5!, {d0, d1, d2, d3, d4, d5, d6, d7} +0x05,0x8b,0x84,0x0c = fstmiaxeq r4, {d8, d9} +0x07,0x2b,0x27,0x1d = fstmdbxne r7!, {d2, d3, d4} +0x40,0x0b,0xbd,0xee = vcvtr.s32.f64 s0, d0 +0x60,0x0a,0xbd,0xee = vcvtr.s32.f32 s0, s1 +0x40,0x0b,0xbc,0xee = vcvtr.u32.f64 s0, d0 +0x60,0x0a,0xbc,0xee = vcvtr.u32.f32 s0, s1 +0x90,0x8a,0x00,0xee = vmov s1, r8 +0x10,0x4a,0x01,0xee = vmov s2, r4 +0x90,0x6a,0x01,0xee = vmov s3, r6 +0x10,0x1a,0x02,0xee = vmov s4, r1 +0x90,0x2a,0x02,0xee = vmov s5, r2 +0x10,0x3a,0x03,0xee = vmov s6, r3 +0x10,0x1a,0x14,0xee = vmov r1, s8 +0x10,0x2a,0x12,0xee = vmov r2, s4 +0x10,0x3a,0x13,0xee = vmov r3, s6 +0x90,0x4a,0x10,0xee = vmov r4, s1 +0x10,0x5a,0x11,0xee = vmov r5, s2 +0x90,0x6a,0x11,0xee = vmov r6, s3 +0xc6,0x0a,0xbb,0xee = vcvt.f32.u32 s0, s0, #0x14 +0xc0,0x0b,0xba,0xee = vcvt.f64.s32 d0, d0, #0x20 +0x67,0x0a,0xbb,0xee = vcvt.f32.u16 s0, s0, #1 +0x40,0x0b,0xba,0xee = vcvt.f64.s16 d0, d0, #0x10 +0xc6,0x0a,0xfa,0xee = vcvt.f32.s32 s1, s1, #0x14 +0xc0,0x4b,0xfb,0xee = vcvt.f64.u32 d20, d20, #0x20 +0x67,0x8a,0xfa,0xee = vcvt.f32.s16 s17, s17, #1 +0x40,0x7b,0xfb,0xee = vcvt.f64.u16 d23, d23, #0x10 +0xc6,0x6a,0xbf,0xee = vcvt.u32.f32 s12, s12, #0x14 +0xc0,0x2b,0xbe,0xee = vcvt.s32.f64 d2, d2, #0x20 +0x67,0xea,0xbf,0xee = vcvt.u16.f32 s28, s28, #1 +0x40,0xfb,0xbe,0xee = vcvt.s16.f64 d15, d15, #0x10 +0xc6,0x0a,0xfe,0xee = vcvt.s32.f32 s1, s1, #0x14 +0xc0,0x4b,0xff,0xee = vcvt.u32.f64 d20, d20, #0x20 +0x67,0x8a,0xfe,0xee = vcvt.s16.f32 s17, s17, #1 +0x40,0x7b,0xff,0xee = vcvt.u16.f64 d23, d23, #0x10 +0x10,0x40,0x80,0xf2 = vmov.i32 d4, #0x0 +0x12,0x46,0x84,0xf2 = vmov.i32 d4, #0x42000000 +0x00,0x2a,0xf7,0xee = vmov.f32 s5, #1.000000e+00 +0x00,0x2a,0xf4,0xee = vmov.f32 s5, #1.250000e-01 +0x0e,0x2a,0xff,0xee = vmov.f32 s5, #-1.875000e+00 +0x03,0x2a,0xfe,0xee = vmov.f32 s5, #-5.937500e-01 +0x00,0x6b,0xb7,0xee = vmov.f64 d6, #1.000000e+00 +0x00,0x6b,0xb4,0xee = vmov.f64 d6, #1.250000e-01 +0x0e,0x6b,0xbf,0xee = vmov.f64 d6, #-1.875000e+00 +0x03,0x6b,0xbe,0xee = vmov.f64 d6, #-5.937500e-01 +0x10,0x7f,0x87,0xf2 = vmov.f32 d7, #1.000000e+00 +0x10,0x7f,0x84,0xf2 = vmov.f32 d7, #1.250000e-01 +0x1e,0x7f,0x87,0xf3 = vmov.f32 d7, #-1.875000e+00 +0x13,0x7f,0x86,0xf3 = vmov.f32 d7, #-5.937500e-01 +0x50,0x0f,0xc7,0xf2 = vmov.f32 q8, #1.000000e+00 +0x50,0x0f,0xc4,0xf2 = vmov.f32 q8, #1.250000e-01 +0x5e,0x0f,0xc7,0xf3 = vmov.f32 q8, #-1.875000e+00 +0x53,0x0f,0xc6,0xf3 = vmov.f32 q8, #-5.937500e-01 diff --git a/thirdparty/capstone/suite/MC/ARM/thumb-add-sub-width.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb-add-sub-width.s.cs new file mode 100644 index 0000000..e18f3f2 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb-add-sub-width.s.cs @@ -0,0 +1,25 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x08,0x44 = add r0, r1 +0x08,0x44 = add r0, r1 +0x40,0x18 = adds r0, r0, r1 +0x40,0x18 = adds r0, r0, r1 +0x08,0x44 = add r0, r1 +0x08,0x44 = add r0, r1 +0x40,0x18 = adds r0, r0, r1 +0x40,0x18 = adds r0, r0, r1 +0x01,0xbf = itttt eq +0x40,0x18 = addeq r0, r0, r1 +0x08,0x44 = addeq r0, r1 +0x10,0xeb,0x01,0x00 = addseq.w r0, r0, r1 +0x10,0xeb,0x01,0x00 = addseq.w r0, r0, r1 +0x40,0x1a = subs r0, r0, r1 +0x40,0x1a = subs r0, r0, r1 +0xa0,0xeb,0x01,0x00 = sub.w r0, r0, r1 +0xa0,0xeb,0x01,0x00 = sub.w r0, r0, r1 +0x40,0x1a = subs r0, r0, r1 +0x40,0x1a = subs r0, r0, r1 +0x01,0xbf = itttt eq +0x40,0x1a = subeq r0, r0, r1 +0x40,0x1a = subeq r0, r0, r1 +0xb0,0xeb,0x01,0x00 = subseq.w r0, r0, r1 +0xb0,0xeb,0x01,0x00 = subseq.w r0, r0, r1 diff --git a/thirdparty/capstone/suite/MC/ARM/thumb-fp-armv8.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb-fp-armv8.s.cs new file mode 100644 index 0000000..07cccfd --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb-fp-armv8.s.cs @@ -0,0 +1,43 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None +0xb2,0xee,0xe0,0x3b = vcvtt.f64.f16 d3, s1 +0xf3,0xee,0xcc,0x2b = vcvtt.f16.f64 s5, d12 +0xb2,0xee,0x60,0x3b = vcvtb.f64.f16 d3, s1 +0xb3,0xee,0x41,0x2b = vcvtb.f16.f64 s4, d1 +0xbc,0xfe,0xe1,0x1a = vcvta.s32.f32 s2, s3 +0xbc,0xfe,0xc3,0x1b = vcvta.s32.f64 s2, d3 +0xbd,0xfe,0xeb,0x3a = vcvtn.s32.f32 s6, s23 +0xbd,0xfe,0xe7,0x3b = vcvtn.s32.f64 s6, d23 +0xbe,0xfe,0xc2,0x0a = vcvtp.s32.f32 s0, s4 +0xbe,0xfe,0xc4,0x0b = vcvtp.s32.f64 s0, d4 +0xff,0xfe,0xc4,0x8a = vcvtm.s32.f32 s17, s8 +0xff,0xfe,0xc8,0x8b = vcvtm.s32.f64 s17, d8 +0xbc,0xfe,0x61,0x1a = vcvta.u32.f32 s2, s3 +0xbc,0xfe,0x43,0x1b = vcvta.u32.f64 s2, d3 +0xbd,0xfe,0x6b,0x3a = vcvtn.u32.f32 s6, s23 +0xbd,0xfe,0x67,0x3b = vcvtn.u32.f64 s6, d23 +0xbe,0xfe,0x42,0x0a = vcvtp.u32.f32 s0, s4 +0xbe,0xfe,0x44,0x0b = vcvtp.u32.f64 s0, d4 +0xff,0xfe,0x44,0x8a = vcvtm.u32.f32 s17, s8 +0xff,0xfe,0x48,0x8b = vcvtm.u32.f64 s17, d8 +0x20,0xfe,0xab,0x2a = vselge.f32 s4, s1, s23 +0x6f,0xfe,0xa7,0xeb = vselge.f64 d30, d31, d23 +0x30,0xfe,0x80,0x0a = vselgt.f32 s0, s1, s0 +0x3a,0xfe,0x24,0x5b = vselgt.f64 d5, d10, d20 +0x0e,0xfe,0x2b,0xfa = vseleq.f32 s30, s28, s23 +0x04,0xfe,0x08,0x2b = vseleq.f64 d2, d4, d8 +0x58,0xfe,0x07,0xaa = vselvs.f32 s21, s16, s14 +0x11,0xfe,0x2f,0x0b = vselvs.f64 d0, d1, d31 +0xc6,0xfe,0x00,0x2a = vmaxnm.f32 s5, s12, s0 +0x86,0xfe,0xae,0x5b = vmaxnm.f64 d5, d22, d30 +0x80,0xfe,0x46,0x0a = vminnm.f32 s0, s0, s12 +0x86,0xfe,0x49,0x4b = vminnm.f64 d4, d6, d9 +0xf6,0xee,0xcc,0x1a = vrintz.f32 s3, s24 +0xb6,0xee,0x64,0x0a = vrintr.f32 s0, s9 +0xb8,0xfe,0x44,0x3b = vrinta.f64 d3, d4 +0xb8,0xfe,0x60,0x6a = vrinta.f32 s12, s1 +0xb9,0xfe,0x44,0x3b = vrintn.f64 d3, d4 +0xb9,0xfe,0x60,0x6a = vrintn.f32 s12, s1 +0xba,0xfe,0x44,0x3b = vrintp.f64 d3, d4 +0xba,0xfe,0x60,0x6a = vrintp.f32 s12, s1 +0xbb,0xfe,0x44,0x3b = vrintm.f64 d3, d4 +0xbb,0xfe,0x60,0x6a = vrintm.f32 s12, s1 diff --git a/thirdparty/capstone/suite/MC/ARM/thumb-hints.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb-hints.s.cs new file mode 100644 index 0000000..1885ec7 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb-hints.s.cs @@ -0,0 +1,12 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x00,0xbf = nop +0x10,0xbf = yield +0x20,0xbf = wfe +0x30,0xbf = wfi +0x40,0xbf = sev +0xbf,0xf3,0x5f,0x8f = dmb sy +0xbf,0xf3,0x5f,0x8f = dmb sy +0xbf,0xf3,0x4f,0x8f = dsb sy +0xbf,0xf3,0x4f,0x8f = dsb sy +0xbf,0xf3,0x6f,0x8f = isb sy +0xbf,0xf3,0x6f,0x8f = isb sy diff --git a/thirdparty/capstone/suite/MC/ARM/thumb-mov.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb-mov.s.cs new file mode 100644 index 0000000..f4ccba5 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb-mov.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x85,0x46 = mov sp, r0 +0x68,0x46 = mov r0, sp +0xed,0x46 = mov sp, sp +0x87,0x46 = mov pc, r0 +0x78,0x46 = mov r0, pc +0xff,0x46 = mov pc, pc +0x4f,0xea,0x00,0x0d = mov.w sp, r0 +0x4f,0xea,0x0d,0x00 = mov.w r0, sp diff --git a/thirdparty/capstone/suite/MC/ARM/thumb-neon-crypto.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb-neon-crypto.s.cs new file mode 100644 index 0000000..55bfd2c --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb-neon-crypto.s.cs @@ -0,0 +1,16 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None +0xb0,0xff,0x42,0x03 = aesd.8 q0, q1 +0xb0,0xff,0x02,0x03 = aese.8 q0, q1 +0xb0,0xff,0xc2,0x03 = aesimc.8 q0, q1 +0xb0,0xff,0x82,0x03 = aesmc.8 q0, q1 +0xb9,0xff,0xc2,0x02 = sha1h.32 q0, q1 +0xba,0xff,0x82,0x03 = sha1su1.32 q0, q1 +0xba,0xff,0xc2,0x03 = sha256su0.32 q0, q1 +0x02,0xef,0x44,0x0c = sha1c.32 q0, q1, q2 +0x22,0xef,0x44,0x0c = sha1m.32 q0, q1, q2 +0x12,0xef,0x44,0x0c = sha1p.32 q0, q1, q2 +0x32,0xef,0x44,0x0c = sha1su0.32 q0, q1, q2 +0x02,0xff,0x44,0x0c = sha256h.32 q0, q1, q2 +0x12,0xff,0x44,0x0c = sha256h2.32 q0, q1, q2 +0x22,0xff,0x44,0x0c = sha256su1.32 q0, q1, q2 +0xe0,0xef,0xa1,0x0e = vmull.p64 q8, d16, d17 diff --git a/thirdparty/capstone/suite/MC/ARM/thumb-neon-v8.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb-neon-v8.s.cs new file mode 100644 index 0000000..51d892f --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb-neon-v8.s.cs @@ -0,0 +1,38 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None +0x05,0xff,0x11,0x4f = vmaxnm.f32 d4, d5, d1 +0x08,0xff,0x5c,0x4f = vmaxnm.f32 q2, q4, q6 +0x24,0xff,0x3e,0x5f = vminnm.f32 d5, d4, d30 +0x2a,0xff,0xd4,0x0f = vminnm.f32 q0, q13, q2 +0xbb,0xff,0x06,0x40 = vcvta.s32.f32 d4, d6 +0xbb,0xff,0x8a,0xc0 = vcvta.u32.f32 d12, d10 +0xbb,0xff,0x4c,0x80 = vcvta.s32.f32 q4, q6 +0xbb,0xff,0xe4,0x80 = vcvta.u32.f32 q4, q10 +0xbb,0xff,0x2e,0x13 = vcvtm.s32.f32 d1, d30 +0xbb,0xff,0x8a,0xc3 = vcvtm.u32.f32 d12, d10 +0xbb,0xff,0x64,0x23 = vcvtm.s32.f32 q1, q10 +0xfb,0xff,0xc2,0xa3 = vcvtm.u32.f32 q13, q1 +0xbb,0xff,0x21,0xf1 = vcvtn.s32.f32 d15, d17 +0xbb,0xff,0x83,0x51 = vcvtn.u32.f32 d5, d3 +0xbb,0xff,0x60,0x61 = vcvtn.s32.f32 q3, q8 +0xbb,0xff,0xc6,0xa1 = vcvtn.u32.f32 q5, q3 +0xbb,0xff,0x25,0xb2 = vcvtp.s32.f32 d11, d21 +0xbb,0xff,0xa7,0xe2 = vcvtp.u32.f32 d14, d23 +0xbb,0xff,0x6e,0x82 = vcvtp.s32.f32 q4, q15 +0xfb,0xff,0xe0,0x22 = vcvtp.u32.f32 q9, q8 +0xba,0xff,0x00,0x34 = vrintn.f32 d3, d0 +0xba,0xff,0x48,0x24 = vrintn.f32 q1, q4 +0xba,0xff,0x8c,0x54 = vrintx.f32 d5, d12 +0xba,0xff,0xc6,0x04 = vrintx.f32 q0, q3 +0xba,0xff,0x00,0x35 = vrinta.f32 d3, d0 +0xfa,0xff,0x44,0x05 = vrinta.f32 q8, q2 +0xba,0xff,0xa2,0xc5 = vrintz.f32 d12, d18 +0xfa,0xff,0xc8,0x25 = vrintz.f32 q9, q4 +0xba,0xff,0x80,0x36 = vrintm.f32 d3, d0 +0xba,0xff,0xc8,0x26 = vrintm.f32 q1, q4 +0xba,0xff,0x80,0x37 = vrintp.f32 d3, d0 +0xba,0xff,0xc8,0x27 = vrintp.f32 q1, q4 +0xba,0xff,0x00,0x34 = vrintn.f32 d3, d0 +0xba,0xff,0xc6,0x04 = vrintx.f32 q0, q3 +0xba,0xff,0x00,0x35 = vrinta.f32 d3, d0 +0xfa,0xff,0xc8,0x25 = vrintz.f32 q9, q4 +0xba,0xff,0xc8,0x27 = vrintp.f32 q1, q4 diff --git a/thirdparty/capstone/suite/MC/ARM/thumb-shift-encoding.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb-shift-encoding.s.cs new file mode 100644 index 0000000..a177c87 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb-shift-encoding.s.cs @@ -0,0 +1,19 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x6e,0xeb,0x00,0x0c = sbc.w r12, lr, r0 +0x68,0xeb,0x19,0x01 = sbc.w r1, r8, r9, lsr #0x20 +0x67,0xeb,0x1a,0x42 = sbc.w r2, r7, r10, lsr #0x10 +0x66,0xeb,0x0a,0x03 = sbc.w r3, r6, r10 +0x65,0xeb,0x0e,0x44 = sbc.w r4, r5, lr, lsl #0x10 +0x64,0xeb,0x2b,0x05 = sbc.w r5, r4, r11, asr #0x20 +0x63,0xeb,0x2c,0x46 = sbc.w r6, r3, r12, asr #0x10 +0x62,0xeb,0x3c,0x07 = sbc.w r7, r2, r12, rrx +0x61,0xeb,0x30,0x48 = sbc.w r8, r1, r0, ror #0x10 +0x0e,0xea,0x00,0x0c = and.w r12, lr, r0 +0x08,0xea,0x19,0x01 = and.w r1, r8, r9, lsr #0x20 +0x07,0xea,0x1a,0x42 = and.w r2, r7, r10, lsr #0x10 +0x06,0xea,0x0a,0x03 = and.w r3, r6, r10 +0x05,0xea,0x0e,0x44 = and.w r4, r5, lr, lsl #0x10 +0x04,0xea,0x2b,0x05 = and.w r5, r4, r11, asr #0x20 +0x03,0xea,0x2c,0x46 = and.w r6, r3, r12, asr #0x10 +0x02,0xea,0x3c,0x07 = and.w r7, r2, r12, rrx +0x01,0xea,0x30,0x48 = and.w r8, r1, r0, ror #0x10 diff --git a/thirdparty/capstone/suite/MC/ARM/thumb.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb.s.cs new file mode 100644 index 0000000..6a83a09 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb.s.cs @@ -0,0 +1,19 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x91,0x42 = cmp r1, r2 +0x16,0xbc = pop {r1, r2, r4} +0xfe,0xde = trap +0xc8,0x47 = blx r9 +0xd0,0x47 = blx r10 +0x1a,0xba = rev r2, r3 +0x63,0xba = rev16 r3, r4 +0xf5,0xba = revsh r5, r6 +0x5a,0xb2 = sxtb r2, r3 +0x1a,0xb2 = sxth r2, r3 +0x2c,0x42 = tst r4, r5 +0xf3,0xb2 = uxtb r3, r6 +0xb3,0xb2 = uxth r3, r6 +0x8b,0x58 = ldr r3, [r1, r2] +0x02,0xbe = bkpt #2 +0xc0,0x46 = mov r8, r8 +0x67,0xb6 = cpsie aif +0x78,0x46 = mov r0, pc diff --git a/thirdparty/capstone/suite/MC/ARM/thumb2-b.w-encodingT4.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb2-b.w-encodingT4.s.cs new file mode 100644 index 0000000..7e936f8 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb2-b.w-encodingT4.s.cs @@ -0,0 +1,2 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x36,0xf0,0x06,0xbc = b.w #0x3680c diff --git a/thirdparty/capstone/suite/MC/ARM/thumb2-branches.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb2-branches.s.cs new file mode 100644 index 0000000..dbdfb91 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb2-branches.s.cs @@ -0,0 +1,93 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x00,0xe4 = b #-0x800 +0xff,0xe3 = b #0x7fe +0xff,0xf7,0x00,0xbc = b.w #-0x800 +0x00,0xf0,0xff,0xbb = b.w #0x7fe +0x66,0xf6,0x30,0xbc = b.w #-0x1997a0 +0x99,0xf1,0xcf,0xbb = b.w #0x19979e +0x00,0xe4 = b #-0x800 +0xff,0xe3 = b #0x7fe +0xff,0xf7,0xff,0xbb = b.w #-0x802 +0x00,0xf0,0x00,0xbc = b.w #0x800 +0x66,0xf6,0x30,0xbc = b.w #-0x1997a0 +0x99,0xf1,0xcf,0xbb = b.w #0x19979e +0x08,0xbf = it eq +0x00,0xe4 = beq #-0x800 +0x18,0xbf = it ne +0x01,0xe4 = bne #-0x7fe +0xc8,0xbf = it gt +0xff,0xf7,0x00,0xbc = bgt.w #-0x800 +0xd8,0xbf = it le +0x00,0xf0,0xff,0xbb = ble.w #0x7fe +0xa8,0xbf = it ge +0x66,0xf6,0x30,0xbc = bge.w #-0x1997a0 +0xb8,0xbf = it lt +0x99,0xf1,0xcf,0xbb = blt.w #0x19979e +0x80,0xd0 = beq #-0x100 +0x7f,0xd1 = bne #0xfe +0x00,0xf0,0x80,0xf8 = bl #0x100 +0x18,0xbf = it ne +0x00,0xf0,0x80,0xf8 = blne #0x100 +0x3f,0xf5,0x80,0xaf = bmi.w #-0x100 +0x40,0xf0,0x7f,0x80 = bne.w #0xfe +0xc0,0xf6,0x00,0x80 = blt.w #-0x100000 +0xbf,0xf2,0xff,0xaf = bge.w #0xffffe +0x80,0xd1 = bne #-0x100 +0x7f,0xdc = bgt #0xfe +0x7f,0xf4,0x7f,0xaf = bne.w #-0x102 +0x00,0xf3,0x80,0x80 = bgt.w #0x100 +0x40,0xf4,0x00,0x80 = bne.w #-0x100000 +0x3f,0xf3,0xff,0xaf = bgt.w #0xffffe +0x08,0xbf = it eq +0x08,0x44 = addeq r0, r1 +0x40,0xd1 = bne #0x80 +0x0c,0xbf = ite eq +0x08,0x44 = addeq r0, r1 +0x40,0xe0 = bne #0x80 +0x00,0xe4 = b #-0x800 +0xff,0xe3 = b #0x7fe +0xff,0xf7,0x00,0xbc = b.w #-0x800 +0x00,0xf0,0xff,0xbb = b.w #0x7fe +0x66,0xf6,0x30,0xbc = b.w #-0x1997a0 +0x99,0xf1,0xcf,0xbb = b.w #0x19979e +0x00,0xe4 = b #-0x800 +0xff,0xe3 = b #0x7fe +0xff,0xf7,0xff,0xbb = b.w #-0x802 +0x00,0xf0,0x00,0xbc = b.w #0x800 +0x66,0xf6,0x30,0xbc = b.w #-0x1997a0 +0x99,0xf1,0xcf,0xbb = b.w #0x19979e +0x08,0xbf = it eq +0x00,0xe4 = beq #-0x800 +0x18,0xbf = it ne +0x01,0xe4 = bne #-0x7fe +0xc8,0xbf = it gt +0xff,0xf7,0x00,0xbc = bgt.w #-0x800 +0xd8,0xbf = it le +0x00,0xf0,0xff,0xbb = ble.w #0x7fe +0xa8,0xbf = it ge +0x66,0xf6,0x30,0xbc = bge.w #-0x1997a0 +0xb8,0xbf = it lt +0x99,0xf1,0xcf,0xbb = blt.w #0x19979e +0x80,0xd0 = beq #-0x100 +0x7f,0xd1 = bne #0xfe +0x3f,0xf5,0x80,0xaf = bmi.w #-0x100 +0x40,0xf0,0x7f,0x80 = bne.w #0xfe +0xc0,0xf6,0x00,0x80 = blt.w #-0x100000 +0xbf,0xf2,0xff,0xaf = bge.w #0xffffe +0x80,0xd1 = bne #-0x100 +0x7f,0xdc = bgt #0xfe +0x7f,0xf4,0x7f,0xaf = bne.w #-0x102 +0x00,0xf3,0x80,0x80 = bgt.w #0x100 +0x40,0xf4,0x00,0x80 = bne.w #-0x100000 +0x3f,0xf3,0xff,0xaf = bgt.w #0xffffe +0x08,0xbf = it eq +0x08,0x44 = addeq r0, r1 +0x40,0xd1 = bne #0x80 +0x0c,0xbf = ite eq +0x08,0x44 = addeq r0, r1 +0x40,0xe0 = bne #0x80 +0x01,0xe0 = b #2 +0x00,0xf0,0x01,0xf8 = bl #2 +0x01,0xd0 = beq #2 +0x08,0xb1 = cbz r0, #2 +0x00,0xf0,0x02,0xe8 = blx #4 diff --git a/thirdparty/capstone/suite/MC/ARM/thumb2-bxj-v8.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb2-bxj-v8.s.cs new file mode 100644 index 0000000..7a6aff3 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb2-bxj-v8.s.cs @@ -0,0 +1,2 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None +0xcd,0xf3,0x00,0x8f = bxj sp diff --git a/thirdparty/capstone/suite/MC/ARM/thumb2-bxj.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb2-bxj.s.cs new file mode 100644 index 0000000..3d821be --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb2-bxj.s.cs @@ -0,0 +1,2 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xc2,0xf3,0x00,0x8f = bxj r2 diff --git a/thirdparty/capstone/suite/MC/ARM/thumb2-ldr.w-str.w.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb2-ldr.w-str.w.s.cs new file mode 100644 index 0000000..34a2edd --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb2-ldr.w-str.w.s.cs @@ -0,0 +1,56 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x51,0xf8,0x04,0x3b = ldr r3, [r1], #4 +0x51,0xf8,0x04,0x3b = ldr r3, [r1], #4 +0x40,0xf8,0x04,0x3b = str r3, [r0], #4 +0x40,0xf8,0x04,0x3b = str r3, [r0], #4 +0x51,0xf8,0x04,0x3d = ldr r3, [r1, #-4]! +0x51,0xf8,0x04,0x3d = ldr r3, [r1, #-4]! +0x40,0xf8,0x04,0x3d = str r3, [r0, #-4]! +0x40,0xf8,0x04,0x3d = str r3, [r0, #-4]! +0x51,0xf8,0x04,0x0d = ldr r0, [r1, #-4]! +0x51,0xf8,0x04,0xdd = ldr sp, [r1, #-4]! +0x51,0xf8,0x04,0xfd = ldr pc, [r1, #-4]! +0x50,0xf8,0x04,0x1d = ldr r1, [r0, #-4]! +0x5d,0xf8,0x04,0x1d = ldr r1, [sp, #-4]! +0x50,0xf8,0xff,0x1f = ldr r1, [r0, #0xff]! +0x50,0xf8,0xff,0x1d = ldr r1, [r0, #-0xff]! +0x50,0xf8,0x00,0x1f = ldr r1, [r0, #0]! +0x08,0xbf = it eq +0x50,0xf8,0xff,0x1f = ldreq r1, [r0, #0xff]! +0xd8,0xbf = it le +0x50,0xf8,0xff,0x1f = ldrle r1, [r0, #0xff]! +0x51,0xf8,0x04,0x0b = ldr r0, [r1], #4 +0x51,0xf8,0x04,0xdb = ldr sp, [r1], #4 +0x51,0xf8,0x04,0xfb = ldr pc, [r1], #4 +0x51,0xf8,0x04,0x0b = ldr r0, [r1], #4 +0x5d,0xf8,0x04,0x0b = pop {r0} +0x5f,0xf8,0x04,0x0b = ldr.w r0, [pc, #-0xb04] +0x51,0xf8,0xff,0x0b = ldr r0, [r1], #0xff +0x51,0xf8,0x00,0x0b = ldr r0, [r1], #0 +0x51,0xf8,0xff,0x09 = ldr r0, [r1], #-0xff +0x08,0xbf = it eq +0x51,0xf8,0xff,0x0b = ldreq r0, [r1], #0xff +0xd8,0xbf = it le +0x51,0xf8,0xff,0x0b = ldrle r0, [r1], #0xff +0x40,0xf8,0x04,0x1d = str r1, [r0, #-4]! +0x40,0xf8,0x04,0xdd = str sp, [r0, #-4]! +0x42,0xf8,0x04,0x1d = str r1, [r2, #-4]! +0x4d,0xf8,0x04,0x1d = str r1, [sp, #-4]! +0x42,0xf8,0xff,0x1f = str r1, [r2, #0xff]! +0x42,0xf8,0x00,0x1f = str r1, [r2, #0]! +0x42,0xf8,0xff,0x1d = str r1, [r2, #-0xff]! +0x08,0xbf = it eq +0x42,0xf8,0xff,0x1f = streq r1, [r2, #0xff]! +0xd8,0xbf = it le +0x42,0xf8,0xff,0x1f = strle r1, [r2, #0xff]! +0x40,0xf8,0x04,0x1b = str r1, [r0], #4 +0x40,0xf8,0x04,0xdb = str sp, [r0], #4 +0x41,0xf8,0x04,0x0b = str r0, [r1], #4 +0x4d,0xf8,0x04,0x0b = str r0, [sp], #4 +0x40,0xf8,0xff,0x1b = str r1, [r0], #0xff +0x40,0xf8,0x00,0x1b = str r1, [r0], #0 +0x40,0xf8,0xff,0x19 = str r1, [r0], #-0xff +0x08,0xbf = it eq +0x40,0xf8,0xff,0x1b = streq r1, [r0], #0xff +0xd8,0xbf = it le +0x40,0xf8,0xff,0x1b = strle r1, [r0], #0xff diff --git a/thirdparty/capstone/suite/MC/ARM/thumb2-ldrexd-strexd.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb2-ldrexd-strexd.s.cs new file mode 100644 index 0000000..9e1715e --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb2-ldrexd-strexd.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xd2,0xe8,0x7f,0x01 = ldrexd r0, r1, [r2] +0xc6,0xe8,0x73,0x45 = strexd r3, r4, r5, [r6] diff --git a/thirdparty/capstone/suite/MC/ARM/thumb2-mclass.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb2-mclass.s.cs new file mode 100644 index 0000000..0a1c3e0 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb2-mclass.s.cs @@ -0,0 +1,19 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None +0xef,0xf3,0x00,0x80 = mrs r0, apsr +0xef,0xf3,0x01,0x80 = mrs r0, iapsr +0xef,0xf3,0x02,0x80 = mrs r0, eapsr +0xef,0xf3,0x03,0x80 = mrs r0, xpsr +0xef,0xf3,0x05,0x80 = mrs r0, ipsr +0xef,0xf3,0x06,0x80 = mrs r0, epsr +0xef,0xf3,0x07,0x80 = mrs r0, iepsr +0xef,0xf3,0x08,0x80 = mrs r0, msp +0xef,0xf3,0x09,0x80 = mrs r0, psp +0xef,0xf3,0x10,0x80 = mrs r0, primask +0xef,0xf3,0x14,0x80 = mrs r0, control +0x80,0xf3,0x05,0x88 = msr ipsr, r0 +0x80,0xf3,0x06,0x88 = msr epsr, r0 +0x80,0xf3,0x07,0x88 = msr iepsr, r0 +0x80,0xf3,0x08,0x88 = msr msp, r0 +0x80,0xf3,0x09,0x88 = msr psp, r0 +0x80,0xf3,0x10,0x88 = msr primask, r0 +0x80,0xf3,0x14,0x88 = msr control, r0 diff --git a/thirdparty/capstone/suite/MC/ARM/thumb2-narrow-dp.ll.cs b/thirdparty/capstone/suite/MC/ARM/thumb2-narrow-dp.ll.cs new file mode 100644 index 0000000..2ec7762 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb2-narrow-dp.ll.cs @@ -0,0 +1,415 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x40,0x1d = adds r0, r0, #5 +0x08,0x31 = adds r1, #8 +0x11,0xf1,0x08,0x01 = adds.w r1, r1, #8 +0x18,0xf1,0x08,0x08 = adds.w r8, r8, #8 +0x08,0xbf = it eq +0x40,0x1d = addeq r0, r0, #5 +0x08,0xbf = it eq +0x08,0x31 = addeq r1, #8 +0x08,0xbf = it eq +0x10,0xf1,0x05,0x00 = addseq.w r0, r0, #5 +0x08,0xbf = it eq +0x11,0xf1,0x08,0x01 = addseq.w r1, r1, #8 +0x50,0x18 = adds r0, r2, r1 +0x52,0x18 = adds r2, r2, r1 +0x0b,0x44 = add r3, r1 +0x08,0xbf = it eq +0x50,0x18 = addeq r0, r2, r1 +0x08,0xbf = it eq +0x52,0x18 = addeq r2, r2, r1 +0x08,0xbf = it eq +0x12,0xeb,0x01,0x00 = addseq.w r0, r2, r1 +0x08,0xbf = it eq +0x12,0xeb,0x01,0x02 = addseq.w r2, r2, r1 +0x0b,0x44 = add r3, r1 +0x7c,0x44 = add r4, pc +0x7c,0x44 = add r4, pc +0x97,0x44 = add pc, r2 +0x97,0x44 = add pc, r2 +0xef,0x44 = add pc, sp, pc +0x05,0xb0 = add sp, #0x14 +0x7f,0xb0 = add sp, #0x1fc +0x0d,0xf5,0x00,0x7d = add.w sp, sp, #0x200 +0xe9,0x44 = add r9, sp, r9 +0xd5,0x44 = add sp, r10 +0xd5,0x44 = add sp, r10 +0xfd,0x44 = add sp, pc +0x12,0xea,0x01,0x00 = ands.w r0, r2, r1 +0x0a,0x40 = ands r2, r1 +0x0a,0x40 = ands r2, r1 +0x10,0xea,0x01,0x00 = ands.w r0, r0, r1 +0x11,0xea,0x03,0x03 = ands.w r3, r1, r3 +0x01,0xea,0x00,0x00 = and.w r0, r1, r0 +0x0f,0x40 = ands r7, r1 +0x0f,0x40 = ands r7, r1 +0x11,0xea,0x08,0x08 = ands.w r8, r1, r8 +0x18,0xea,0x01,0x08 = ands.w r8, r8, r1 +0x18,0xea,0x00,0x00 = ands.w r0, r8, r0 +0x11,0xea,0x08,0x01 = ands.w r1, r1, r8 +0x12,0xea,0x41,0x02 = ands.w r2, r2, r1, lsl #1 +0x11,0xea,0x50,0x00 = ands.w r0, r1, r0, lsr #1 +0x08,0xbf = it eq +0x02,0xea,0x01,0x00 = andeq.w r0, r2, r1 +0x08,0xbf = it eq +0x0b,0x40 = andeq r3, r1 +0x08,0xbf = it eq +0x0b,0x40 = andeq r3, r1 +0x08,0xbf = it eq +0x00,0xea,0x01,0x00 = andeq.w r0, r0, r1 +0x08,0xbf = it eq +0x01,0xea,0x02,0x02 = andeq.w r2, r1, r2 +0x08,0xbf = it eq +0x11,0xea,0x00,0x00 = andseq.w r0, r1, r0 +0x08,0xbf = it eq +0x0f,0x40 = andeq r7, r1 +0x08,0xbf = it eq +0x0f,0x40 = andeq r7, r1 +0x08,0xbf = it eq +0x01,0xea,0x08,0x08 = andeq.w r8, r1, r8 +0x08,0xbf = it eq +0x08,0xea,0x01,0x08 = andeq.w r8, r8, r1 +0x08,0xbf = it eq +0x08,0xea,0x04,0x04 = andeq.w r4, r8, r4 +0x08,0xbf = it eq +0x04,0xea,0x08,0x04 = andeq.w r4, r4, r8 +0x08,0xbf = it eq +0x00,0xea,0x41,0x00 = andeq.w r0, r0, r1, lsl #1 +0x08,0xbf = it eq +0x01,0xea,0x55,0x05 = andeq.w r5, r1, r5, lsr #1 +0x92,0xea,0x01,0x00 = eors.w r0, r2, r1 +0x4d,0x40 = eors r5, r1 +0x4d,0x40 = eors r5, r1 +0x90,0xea,0x01,0x00 = eors.w r0, r0, r1 +0x91,0xea,0x02,0x02 = eors.w r2, r1, r2 +0x81,0xea,0x01,0x01 = eor.w r1, r1, r1 +0x4f,0x40 = eors r7, r1 +0x4f,0x40 = eors r7, r1 +0x91,0xea,0x08,0x08 = eors.w r8, r1, r8 +0x98,0xea,0x01,0x08 = eors.w r8, r8, r1 +0x98,0xea,0x06,0x06 = eors.w r6, r8, r6 +0x90,0xea,0x08,0x00 = eors.w r0, r0, r8 +0x92,0xea,0x41,0x02 = eors.w r2, r2, r1, lsl #1 +0x91,0xea,0x50,0x00 = eors.w r0, r1, r0, lsr #1 +0x08,0xbf = it eq +0x82,0xea,0x01,0x03 = eoreq.w r3, r2, r1 +0x08,0xbf = it eq +0x48,0x40 = eoreq r0, r1 +0x08,0xbf = it eq +0x4a,0x40 = eoreq r2, r1 +0x08,0xbf = it eq +0x83,0xea,0x01,0x03 = eoreq.w r3, r3, r1 +0x08,0xbf = it eq +0x81,0xea,0x00,0x00 = eoreq.w r0, r1, r0 +0x08,0xbf = it eq +0x91,0xea,0x01,0x01 = eorseq.w r1, r1, r1 +0x08,0xbf = it eq +0x4f,0x40 = eoreq r7, r1 +0x08,0xbf = it eq +0x4f,0x40 = eoreq r7, r1 +0x08,0xbf = it eq +0x81,0xea,0x08,0x08 = eoreq.w r8, r1, r8 +0x08,0xbf = it eq +0x88,0xea,0x01,0x08 = eoreq.w r8, r8, r1 +0x08,0xbf = it eq +0x88,0xea,0x00,0x00 = eoreq.w r0, r8, r0 +0x08,0xbf = it eq +0x83,0xea,0x08,0x03 = eoreq.w r3, r3, r8 +0x08,0xbf = it eq +0x84,0xea,0x41,0x04 = eoreq.w r4, r4, r1, lsl #1 +0x08,0xbf = it eq +0x81,0xea,0x50,0x00 = eoreq.w r0, r1, r0, lsr #1 +0x12,0xfa,0x01,0xf0 = lsls.w r0, r2, r1 +0x8a,0x40 = lsls r2, r1 +0x11,0xfa,0x02,0xf2 = lsls.w r2, r1, r2 +0x10,0xfa,0x01,0xf0 = lsls.w r0, r0, r1 +0x11,0xfa,0x04,0xf4 = lsls.w r4, r1, r4 +0x01,0xfa,0x04,0xf4 = lsl.w r4, r1, r4 +0x8f,0x40 = lsls r7, r1 +0x11,0xfa,0x08,0xf8 = lsls.w r8, r1, r8 +0x18,0xfa,0x01,0xf8 = lsls.w r8, r8, r1 +0x18,0xfa,0x03,0xf3 = lsls.w r3, r8, r3 +0x15,0xfa,0x08,0xf5 = lsls.w r5, r5, r8 +0x08,0xbf = it eq +0x02,0xfa,0x01,0xf0 = lsleq.w r0, r2, r1 +0x08,0xbf = it eq +0x8a,0x40 = lsleq r2, r1 +0x08,0xbf = it eq +0x01,0xfa,0x02,0xf2 = lsleq.w r2, r1, r2 +0x08,0xbf = it eq +0x00,0xfa,0x01,0xf0 = lsleq.w r0, r0, r1 +0x08,0xbf = it eq +0x01,0xfa,0x03,0xf3 = lsleq.w r3, r1, r3 +0x08,0xbf = it eq +0x11,0xfa,0x04,0xf4 = lslseq.w r4, r1, r4 +0x08,0xbf = it eq +0x8f,0x40 = lsleq r7, r1 +0x08,0xbf = it eq +0x01,0xfa,0x08,0xf8 = lsleq.w r8, r1, r8 +0x08,0xbf = it eq +0x08,0xfa,0x01,0xf8 = lsleq.w r8, r8, r1 +0x08,0xbf = it eq +0x08,0xfa,0x00,0xf0 = lsleq.w r0, r8, r0 +0x08,0xbf = it eq +0x03,0xfa,0x08,0xf3 = lsleq.w r3, r3, r8 +0x32,0xfa,0x01,0xf6 = lsrs.w r6, r2, r1 +0xca,0x40 = lsrs r2, r1 +0x31,0xfa,0x02,0xf2 = lsrs.w r2, r1, r2 +0x32,0xfa,0x01,0xf2 = lsrs.w r2, r2, r1 +0x31,0xfa,0x03,0xf3 = lsrs.w r3, r1, r3 +0x21,0xfa,0x04,0xf4 = lsr.w r4, r1, r4 +0xcf,0x40 = lsrs r7, r1 +0x31,0xfa,0x08,0xf8 = lsrs.w r8, r1, r8 +0x38,0xfa,0x01,0xf8 = lsrs.w r8, r8, r1 +0x38,0xfa,0x02,0xf2 = lsrs.w r2, r8, r2 +0x35,0xfa,0x08,0xf5 = lsrs.w r5, r5, r8 +0x08,0xbf = it eq +0x22,0xfa,0x01,0xf6 = lsreq.w r6, r2, r1 +0x08,0xbf = it eq +0xcf,0x40 = lsreq r7, r1 +0x08,0xbf = it eq +0x21,0xfa,0x07,0xf7 = lsreq.w r7, r1, r7 +0x08,0xbf = it eq +0x27,0xfa,0x01,0xf7 = lsreq.w r7, r7, r1 +0x08,0xbf = it eq +0x21,0xfa,0x02,0xf2 = lsreq.w r2, r1, r2 +0x08,0xbf = it eq +0x31,0xfa,0x00,0xf0 = lsrseq.w r0, r1, r0 +0x08,0xbf = it eq +0xcf,0x40 = lsreq r7, r1 +0x08,0xbf = it eq +0x21,0xfa,0x08,0xf8 = lsreq.w r8, r1, r8 +0x08,0xbf = it eq +0x28,0xfa,0x01,0xf8 = lsreq.w r8, r8, r1 +0x08,0xbf = it eq +0x28,0xfa,0x01,0xf1 = lsreq.w r1, r8, r1 +0x08,0xbf = it eq +0x24,0xfa,0x08,0xf4 = lsreq.w r4, r4, r8 +0x56,0xfa,0x05,0xf7 = asrs.w r7, r6, r5 +0x08,0x41 = asrs r0, r1 +0x51,0xfa,0x00,0xf0 = asrs.w r0, r1, r0 +0x53,0xfa,0x01,0xf3 = asrs.w r3, r3, r1 +0x51,0xfa,0x01,0xf1 = asrs.w r1, r1, r1 +0x41,0xfa,0x00,0xf0 = asr.w r0, r1, r0 +0x0f,0x41 = asrs r7, r1 +0x51,0xfa,0x08,0xf8 = asrs.w r8, r1, r8 +0x58,0xfa,0x01,0xf8 = asrs.w r8, r8, r1 +0x58,0xfa,0x05,0xf5 = asrs.w r5, r8, r5 +0x55,0xfa,0x08,0xf5 = asrs.w r5, r5, r8 +0x08,0xbf = it eq +0x42,0xfa,0x01,0xf0 = asreq.w r0, r2, r1 +0x08,0xbf = it eq +0x0a,0x41 = asreq r2, r1 +0x08,0xbf = it eq +0x42,0xfa,0x01,0xf1 = asreq.w r1, r2, r1 +0x08,0xbf = it eq +0x44,0xfa,0x01,0xf4 = asreq.w r4, r4, r1 +0x08,0xbf = it eq +0x41,0xfa,0x06,0xf6 = asreq.w r6, r1, r6 +0x08,0xbf = it eq +0x51,0xfa,0x03,0xf3 = asrseq.w r3, r1, r3 +0x08,0xbf = it eq +0x0f,0x41 = asreq r7, r1 +0x08,0xbf = it eq +0x41,0xfa,0x08,0xf8 = asreq.w r8, r1, r8 +0x08,0xbf = it eq +0x48,0xfa,0x01,0xf8 = asreq.w r8, r8, r1 +0x08,0xbf = it eq +0x48,0xfa,0x01,0xf1 = asreq.w r1, r8, r1 +0x08,0xbf = it eq +0x43,0xfa,0x08,0xf3 = asreq.w r3, r3, r8 +0x52,0xeb,0x01,0x05 = adcs.w r5, r2, r1 +0x4d,0x41 = adcs r5, r1 +0x4b,0x41 = adcs r3, r1 +0x52,0xeb,0x01,0x02 = adcs.w r2, r2, r1 +0x51,0xeb,0x03,0x03 = adcs.w r3, r1, r3 +0x41,0xeb,0x00,0x00 = adc.w r0, r1, r0 +0x4f,0x41 = adcs r7, r1 +0x4f,0x41 = adcs r7, r1 +0x51,0xeb,0x08,0x08 = adcs.w r8, r1, r8 +0x58,0xeb,0x01,0x08 = adcs.w r8, r8, r1 +0x58,0xeb,0x05,0x05 = adcs.w r5, r8, r5 +0x52,0xeb,0x08,0x02 = adcs.w r2, r2, r8 +0x53,0xeb,0x41,0x03 = adcs.w r3, r3, r1, lsl #1 +0x51,0xeb,0x54,0x04 = adcs.w r4, r1, r4, lsr #1 +0x08,0xbf = it eq +0x42,0xeb,0x03,0x01 = adceq.w r1, r2, r3 +0x08,0xbf = it eq +0x49,0x41 = adceq r1, r1 +0x08,0xbf = it eq +0x4b,0x41 = adceq r3, r1 +0x08,0xbf = it eq +0x43,0xeb,0x01,0x03 = adceq.w r3, r3, r1 +0x08,0xbf = it eq +0x41,0xeb,0x00,0x00 = adceq.w r0, r1, r0 +0x08,0xbf = it eq +0x51,0xeb,0x03,0x03 = adcseq.w r3, r1, r3 +0x08,0xbf = it eq +0x4f,0x41 = adceq r7, r1 +0x08,0xbf = it eq +0x4f,0x41 = adceq r7, r1 +0x08,0xbf = it eq +0x41,0xeb,0x08,0x08 = adceq.w r8, r1, r8 +0x08,0xbf = it eq +0x48,0xeb,0x01,0x08 = adceq.w r8, r8, r1 +0x08,0xbf = it eq +0x48,0xeb,0x03,0x03 = adceq.w r3, r8, r3 +0x08,0xbf = it eq +0x41,0xeb,0x08,0x01 = adceq.w r1, r1, r8 +0x08,0xbf = it eq +0x42,0xeb,0x41,0x02 = adceq.w r2, r2, r1, lsl #1 +0x08,0xbf = it eq +0x41,0xeb,0x51,0x01 = adceq.w r1, r1, r1, lsr #1 +0x72,0xeb,0x01,0x03 = sbcs.w r3, r2, r1 +0x8c,0x41 = sbcs r4, r1 +0x74,0xeb,0x01,0x01 = sbcs.w r1, r4, r1 +0x74,0xeb,0x01,0x04 = sbcs.w r4, r4, r1 +0x71,0xeb,0x02,0x02 = sbcs.w r2, r1, r2 +0x61,0xeb,0x00,0x00 = sbc.w r0, r1, r0 +0x8f,0x41 = sbcs r7, r1 +0x71,0xeb,0x08,0x08 = sbcs.w r8, r1, r8 +0x78,0xeb,0x01,0x08 = sbcs.w r8, r8, r1 +0x78,0xeb,0x04,0x04 = sbcs.w r4, r8, r4 +0x73,0xeb,0x08,0x03 = sbcs.w r3, r3, r8 +0x72,0xeb,0x41,0x02 = sbcs.w r2, r2, r1, lsl #1 +0x71,0xeb,0x55,0x05 = sbcs.w r5, r1, r5, lsr #1 +0x08,0xbf = it eq +0x62,0xeb,0x01,0x05 = sbceq.w r5, r2, r1 +0x08,0xbf = it eq +0x8d,0x41 = sbceq r5, r1 +0x08,0xbf = it eq +0x65,0xeb,0x01,0x01 = sbceq.w r1, r5, r1 +0x08,0xbf = it eq +0x65,0xeb,0x01,0x05 = sbceq.w r5, r5, r1 +0x08,0xbf = it eq +0x61,0xeb,0x00,0x00 = sbceq.w r0, r1, r0 +0x08,0xbf = it eq +0x71,0xeb,0x02,0x02 = sbcseq.w r2, r1, r2 +0x08,0xbf = it eq +0x8f,0x41 = sbceq r7, r1 +0x08,0xbf = it eq +0x61,0xeb,0x08,0x08 = sbceq.w r8, r1, r8 +0x08,0xbf = it eq +0x68,0xeb,0x01,0x08 = sbceq.w r8, r8, r1 +0x08,0xbf = it eq +0x68,0xeb,0x07,0x07 = sbceq.w r7, r8, r7 +0x08,0xbf = it eq +0x67,0xeb,0x08,0x07 = sbceq.w r7, r7, r8 +0x08,0xbf = it eq +0x62,0xeb,0x41,0x02 = sbceq.w r2, r2, r1, lsl #1 +0x08,0xbf = it eq +0x61,0xeb,0x55,0x05 = sbceq.w r5, r1, r5, lsr #1 +0x72,0xfa,0x01,0xf3 = rors.w r3, r2, r1 +0xc8,0x41 = rors r0, r1 +0x70,0xfa,0x01,0xf1 = rors.w r1, r0, r1 +0x72,0xfa,0x01,0xf2 = rors.w r2, r2, r1 +0x71,0xfa,0x02,0xf2 = rors.w r2, r1, r2 +0x61,0xfa,0x05,0xf5 = ror.w r5, r1, r5 +0xcf,0x41 = rors r7, r1 +0x71,0xfa,0x08,0xf8 = rors.w r8, r1, r8 +0x78,0xfa,0x01,0xf8 = rors.w r8, r8, r1 +0x78,0xfa,0x06,0xf6 = rors.w r6, r8, r6 +0x76,0xfa,0x08,0xf6 = rors.w r6, r6, r8 +0x08,0xbf = it eq +0x62,0xfa,0x01,0xf4 = roreq.w r4, r2, r1 +0x08,0xbf = it eq +0xcc,0x41 = roreq r4, r1 +0x08,0xbf = it eq +0x64,0xfa,0x01,0xf1 = roreq.w r1, r4, r1 +0x08,0xbf = it eq +0x64,0xfa,0x01,0xf4 = roreq.w r4, r4, r1 +0x08,0xbf = it eq +0x61,0xfa,0x00,0xf0 = roreq.w r0, r1, r0 +0x08,0xbf = it eq +0x71,0xfa,0x00,0xf0 = rorseq.w r0, r1, r0 +0x08,0xbf = it eq +0xcf,0x41 = roreq r7, r1 +0x08,0xbf = it eq +0x61,0xfa,0x08,0xf8 = roreq.w r8, r1, r8 +0x08,0xbf = it eq +0x68,0xfa,0x01,0xf8 = roreq.w r8, r8, r1 +0x08,0xbf = it eq +0x68,0xfa,0x03,0xf3 = roreq.w r3, r8, r3 +0x08,0xbf = it eq +0x61,0xfa,0x08,0xf1 = roreq.w r1, r1, r8 +0x52,0xea,0x01,0x07 = orrs.w r7, r2, r1 +0x0a,0x43 = orrs r2, r1 +0x0b,0x43 = orrs r3, r1 +0x54,0xea,0x01,0x04 = orrs.w r4, r4, r1 +0x51,0xea,0x05,0x05 = orrs.w r5, r1, r5 +0x41,0xea,0x02,0x02 = orr.w r2, r1, r2 +0x0f,0x43 = orrs r7, r1 +0x0f,0x43 = orrs r7, r1 +0x51,0xea,0x08,0x08 = orrs.w r8, r1, r8 +0x58,0xea,0x01,0x08 = orrs.w r8, r8, r1 +0x58,0xea,0x01,0x01 = orrs.w r1, r8, r1 +0x50,0xea,0x08,0x00 = orrs.w r0, r0, r8 +0x51,0xea,0x41,0x01 = orrs.w r1, r1, r1, lsl #1 +0x51,0xea,0x50,0x00 = orrs.w r0, r1, r0, lsr #1 +0x08,0xbf = it eq +0x42,0xea,0x01,0x00 = orreq.w r0, r2, r1 +0x08,0xbf = it eq +0x0d,0x43 = orreq r5, r1 +0x08,0xbf = it eq +0x0d,0x43 = orreq r5, r1 +0x08,0xbf = it eq +0x42,0xea,0x01,0x02 = orreq.w r2, r2, r1 +0x08,0xbf = it eq +0x41,0xea,0x03,0x03 = orreq.w r3, r1, r3 +0x08,0xbf = it eq +0x51,0xea,0x04,0x04 = orrseq.w r4, r1, r4 +0x08,0xbf = it eq +0x0f,0x43 = orreq r7, r1 +0x08,0xbf = it eq +0x0f,0x43 = orreq r7, r1 +0x08,0xbf = it eq +0x41,0xea,0x08,0x08 = orreq.w r8, r1, r8 +0x08,0xbf = it eq +0x48,0xea,0x01,0x08 = orreq.w r8, r8, r1 +0x08,0xbf = it eq +0x48,0xea,0x00,0x00 = orreq.w r0, r8, r0 +0x08,0xbf = it eq +0x40,0xea,0x08,0x00 = orreq.w r0, r0, r8 +0x08,0xbf = it eq +0x42,0xea,0x41,0x02 = orreq.w r2, r2, r1, lsl #1 +0x08,0xbf = it eq +0x41,0xea,0x52,0x02 = orreq.w r2, r1, r2, lsr #1 +0x32,0xea,0x01,0x03 = bics.w r3, r2, r1 +0x8a,0x43 = bics r2, r1 +0x32,0xea,0x01,0x01 = bics.w r1, r2, r1 +0x32,0xea,0x01,0x02 = bics.w r2, r2, r1 +0x31,0xea,0x00,0x00 = bics.w r0, r1, r0 +0x21,0xea,0x00,0x00 = bic.w r0, r1, r0 +0x8f,0x43 = bics r7, r1 +0x31,0xea,0x08,0x08 = bics.w r8, r1, r8 +0x38,0xea,0x01,0x08 = bics.w r8, r8, r1 +0x38,0xea,0x07,0x07 = bics.w r7, r8, r7 +0x35,0xea,0x08,0x05 = bics.w r5, r5, r8 +0x33,0xea,0x41,0x03 = bics.w r3, r3, r1, lsl #1 +0x31,0xea,0x54,0x04 = bics.w r4, r1, r4, lsr #1 +0x08,0xbf = it eq +0x22,0xea,0x01,0x00 = biceq.w r0, r2, r1 +0x08,0xbf = it eq +0x8d,0x43 = biceq r5, r1 +0x08,0xbf = it eq +0x25,0xea,0x01,0x01 = biceq.w r1, r5, r1 +0x08,0xbf = it eq +0x24,0xea,0x01,0x04 = biceq.w r4, r4, r1 +0x08,0xbf = it eq +0x21,0xea,0x02,0x02 = biceq.w r2, r1, r2 +0x08,0xbf = it eq +0x31,0xea,0x05,0x05 = bicseq.w r5, r1, r5 +0x08,0xbf = it eq +0x8f,0x43 = biceq r7, r1 +0x08,0xbf = it eq +0x21,0xea,0x08,0x08 = biceq.w r8, r1, r8 +0x08,0xbf = it eq +0x28,0xea,0x01,0x08 = biceq.w r8, r8, r1 +0x08,0xbf = it eq +0x28,0xea,0x00,0x00 = biceq.w r0, r8, r0 +0x08,0xbf = it eq +0x22,0xea,0x08,0x02 = biceq.w r2, r2, r8 +0x08,0xbf = it eq +0x24,0xea,0x41,0x04 = biceq.w r4, r4, r1, lsl #1 +0x08,0xbf = it eq +0x21,0xea,0x55,0x05 = biceq.w r5, r1, r5, lsr #1 diff --git a/thirdparty/capstone/suite/MC/ARM/thumb2-pldw.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb2-pldw.s.cs new file mode 100644 index 0000000..9bd5225 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb2-pldw.s.cs @@ -0,0 +1,2 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xb0,0xf8,0x01,0xf1 = pldw [r0, #0x101] diff --git a/thirdparty/capstone/suite/MC/ARM/thumb_rewrites.s.cs b/thirdparty/capstone/suite/MC/ARM/thumb_rewrites.s.cs new file mode 100644 index 0000000..377e967 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumb_rewrites.s.cs @@ -0,0 +1,32 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0xc9,0x1c = adds r1, r1, #3 +0x03,0x31 = adds r1, #3 +0x08,0x30 = adds r0, #8 +0x00,0x18 = adds r0, r0, r0 +0x40,0x44 = add r0, r8 +0x41,0x44 = add r1, r8 +0x85,0x44 = add sp, r0 +0x6c,0x44 = add r4, sp, r4 +0x08,0xb0 = add sp, #0x20 +0xfe,0xad = add r5, sp, #0x3f8 +0x08,0x44 = add r0, r1 +0x1a,0x44 = add r2, r3 +0x00,0x1a = subs r0, r0, r0 +0x5b,0x1f = subs r3, r3, #5 +0x05,0x3b = subs r3, #5 +0x08,0x3a = subs r2, #8 +0x84,0xb0 = sub sp, #0x10 +0x08,0x40 = ands r0, r1 +0x08,0x40 = ands r0, r1 +0x48,0x40 = eors r0, r1 +0x48,0x40 = eors r0, r1 +0x88,0x40 = lsls r0, r1 +0xc8,0x40 = lsrs r0, r1 +0x08,0x41 = asrs r0, r1 +0x48,0x41 = adcs r0, r1 +0x48,0x41 = adcs r0, r1 +0x88,0x41 = sbcs r0, r1 +0xc8,0x41 = rors r0, r1 +0x08,0x43 = orrs r0, r1 +0x08,0x43 = orrs r0, r1 +0x88,0x43 = bics r0, r1 diff --git a/thirdparty/capstone/suite/MC/ARM/thumbv7em.s.cs b/thirdparty/capstone/suite/MC/ARM/thumbv7em.s.cs new file mode 100644 index 0000000..6d915cb --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumbv7em.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None +0x80,0xf3,0x00,0x84 = msr apsr_g, r0 +0x80,0xf3,0x00,0x8c = msr apsr_nzcvqg, r0 +0x80,0xf3,0x01,0x84 = msr iapsr_g, r0 +0x80,0xf3,0x01,0x8c = msr iapsr_nzcvqg, r0 +0x80,0xf3,0x02,0x84 = msr eapsr_g, r0 +0x80,0xf3,0x02,0x8c = msr eapsr_nzcvqg, r0 +0x80,0xf3,0x03,0x84 = msr xpsr_g, r0 +0x80,0xf3,0x03,0x8c = msr xpsr_nzcvqg, r0 diff --git a/thirdparty/capstone/suite/MC/ARM/thumbv7m.s.cs b/thirdparty/capstone/suite/MC/ARM/thumbv7m.s.cs new file mode 100644 index 0000000..b18931c --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumbv7m.s.cs @@ -0,0 +1,7 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None +0xef,0xf3,0x11,0x80 = mrs r0, basepri +0xef,0xf3,0x12,0x80 = mrs r0, basepri_max +0xef,0xf3,0x13,0x80 = mrs r0, faultmask +0x80,0xf3,0x11,0x88 = msr basepri, r0 +0x80,0xf3,0x12,0x88 = msr basepri_max, r0 +0x80,0xf3,0x13,0x88 = msr faultmask, r0 diff --git a/thirdparty/capstone/suite/MC/ARM/thumbv8.1m-vmrs-vmsr.s.cs b/thirdparty/capstone/suite/MC/ARM/thumbv8.1m-vmrs-vmsr.s.cs new file mode 100644 index 0000000..677c777 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumbv8.1m-vmrs-vmsr.s.cs @@ -0,0 +1,12 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0xe2,0xee,0x10,0x0a = vmsr fpscr_nzcvqc, r0 +0xf2,0xee,0x10,0xaa = vmrs r10, fpscr_nzcvqc +0xfe,0xee,0x10,0x0a = vmrs r0, fpcxtns +0xee,0xee,0x10,0xaa = vmsr fpcxtns, r10 +0xef,0xee,0x10,0x5a = vmsr fpcxts, r5 +0xfe,0xee,0x10,0x3a = vmrs r3, fpcxtns +0xff,0xee,0x10,0x0a = vmrs r0, fpcxts +0xfc,0xee,0x10,0x0a = vmrs r0, vpr +0xfd,0xee,0x10,0x4a = vmrs r4, p0 +0xec,0xee,0x10,0x0a = vmsr vpr, r0 +0xed,0xee,0x10,0x4a = vmsr p0, r4 diff --git a/thirdparty/capstone/suite/MC/ARM/thumbv8.1m.s.cs b/thirdparty/capstone/suite/MC/ARM/thumbv8.1m.s.cs new file mode 100644 index 0000000..dd183b4 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumbv8.1m.s.cs @@ -0,0 +1,166 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None +0x42,0xf0,0x01,0xe0 = dls lr, r2 +0x4e,0xf0,0x01,0xe0 = dls lr, lr +0x40,0xf0,0x01,0xe0 = dls lr, r0 +0x41,0xf0,0x01,0xe0 = dls lr, r1 +0x4a,0xf0,0x01,0xe0 = dls lr, r10 +0x4b,0xf0,0x01,0xe0 = dls lr, r11 +0x4c,0xf0,0x01,0xe0 = dls lr, r12 +0x42,0xf0,0x01,0xe0 = dls lr, r2 +0x43,0xf0,0x01,0xe0 = dls lr, r3 +0x45,0xf0,0x01,0xe0 = dls lr, r5 +0x46,0xf0,0x01,0xe0 = dls lr, r6 +0x47,0xf0,0x01,0xe0 = dls lr, r7 +0x48,0xf0,0x01,0xe0 = dls lr, r8 +0x49,0xf0,0x01,0xe0 = dls lr, r9 +0x2f,0xf0,0x35,0xc8 = le #-0x6a +0x2f,0xf0,0x4b,0xc2 = le #-0x494 +0x2f,0xf0,0x5d,0xca = le #-0x4ba +0x2f,0xf0,0x77,0xc2 = le #-0x4ec +0x2f,0xf0,0x77,0xca = le #-0x4ee +0x2f,0xf0,0x83,0xc2 = le #-0x504 +0x2f,0xf0,0x83,0xca = le #-0x506 +0x2f,0xf0,0x0b,0xc3 = le #-0x614 +0x2f,0xf0,0x59,0xc8 = le #-0xb2 +0x2f,0xf0,0xad,0xcb = le #-0x75a +0x2f,0xf0,0xb7,0xc3 = le #-0x76c +0x2f,0xf0,0xbb,0xcb = le #-0x776 +0x2f,0xf0,0x0f,0xc4 = le #-0x81c +0x2f,0xf0,0x6d,0xcc = le #-0x8da +0x2f,0xf0,0x8b,0xc4 = le #-0x914 +0x2f,0xf0,0x8d,0xc4 = le #-0x918 +0x2f,0xf0,0xcd,0xc4 = le #-0x998 +0x2f,0xf0,0x7b,0xc8 = le #-0xf6 +0x2f,0xf0,0xd7,0xc4 = le #-0x9ac +0x2f,0xf0,0x09,0xcd = le #-0xa12 +0x2f,0xf0,0x83,0xc8 = le #-0x106 +0x2f,0xf0,0x33,0xc5 = le #-0xa64 +0x2f,0xf0,0x51,0xcd = le #-0xaa2 +0x2f,0xf0,0x9b,0xc5 = le #-0xb34 +0x2f,0xf0,0xa1,0xcd = le #-0xb42 +0x2f,0xf0,0x29,0xce = le #-0xc52 +0x2f,0xf0,0x65,0xce = le #-0xcca +0x2f,0xf0,0x8d,0xc6 = le #-0xd18 +0x2f,0xf0,0xa9,0xc8 = le #-0x152 +0x2f,0xf0,0xc1,0xce = le #-0xd82 +0x2f,0xf0,0xcd,0xc6 = le #-0xd98 +0x2f,0xf0,0xeb,0xce = le #-0xdd6 +0x2f,0xf0,0x1f,0xc7 = le #-0xe3c +0x2f,0xf0,0x2f,0xc7 = le #-0xe5c +0x2f,0xf0,0x37,0xc7 = le #-0xe6c +0x2f,0xf0,0x8b,0xc7 = le #-0xf14 +0x2f,0xf0,0xc9,0xcf = le #-0xf92 +0x2f,0xf0,0xd3,0xcf = le #-0xfa6 +0x2f,0xf0,0xe1,0xcf = le #-0xfc2 +0x2f,0xf0,0xef,0xc7 = le #-0xfdc +0x2f,0xf0,0xf3,0xc7 = le #-0xfe4 +0x2f,0xf0,0xef,0xc8 = le #-0x1de +0x2f,0xf0,0x11,0xc1 = le #-0x220 +0x2f,0xf0,0x25,0xc9 = le #-0x24a +0x2f,0xf0,0x2f,0xc9 = le #-0x25e +0x2f,0xf0,0x49,0xc1 = le #-0x290 +0x2f,0xf0,0x73,0xc1 = le #-0x2e4 +0x2f,0xf0,0x7d,0xc9 = le #-0x2fa +0x2f,0xf0,0xaf,0xc9 = le #-0x35e +0x2f,0xf0,0xb3,0xc9 = le #-0x366 +0x0f,0xf0,0x1d,0xc2 = le lr, #-0x438 +0x0f,0xf0,0x29,0xc2 = le lr, #-0x450 +0x0f,0xf0,0x41,0xc2 = le lr, #-0x480 +0x0f,0xf0,0xdb,0xca = le lr, #-0x5b6 +0x0f,0xf0,0xdf,0xca = le lr, #-0x5be +0x0f,0xf0,0x27,0xc3 = le lr, #-0x64c +0x0f,0xf0,0x31,0xc3 = le lr, #-0x660 +0x0f,0xf0,0x4f,0xcb = le lr, #-0x69e +0x0f,0xf0,0x59,0xcb = le lr, #-0x6b2 +0x0f,0xf0,0x9d,0xcb = le lr, #-0x73a +0x0f,0xf0,0xab,0xcb = le lr, #-0x756 +0x0f,0xf0,0xb5,0xc3 = le lr, #-0x768 +0x0f,0xf0,0xc1,0xcb = le lr, #-0x782 +0x0f,0xf0,0xc3,0xcb = le lr, #-0x786 +0x0f,0xf0,0x01,0xc8 = le lr, #-2 +0x0f,0xf0,0x1d,0xc4 = le lr, #-0x838 +0x0f,0xf0,0x23,0xc4 = le lr, #-0x844 +0x0f,0xf0,0x31,0xc4 = le lr, #-0x860 +0x0f,0xf0,0x47,0xc4 = le lr, #-0x88c +0x0f,0xf0,0x95,0xc4 = le lr, #-0x928 +0x0f,0xf0,0xcd,0xc4 = le lr, #-0x998 +0x0f,0xf0,0x19,0xc5 = le lr, #-0xa30 +0x0f,0xf0,0x1d,0xc5 = le lr, #-0xa38 +0x0f,0xf0,0x1f,0xcd = le lr, #-0xa3e +0x0f,0xf0,0x3d,0xc5 = le lr, #-0xa78 +0x0f,0xf0,0x43,0xcd = le lr, #-0xa86 +0x0f,0xf0,0x91,0xcd = le lr, #-0xb22 +0x0f,0xf0,0x97,0xc5 = le lr, #-0xb2c +0x0f,0xf0,0xdf,0xc5 = le lr, #-0xbbc +0x0f,0xf0,0xe5,0xcd = le lr, #-0xbca +0x0f,0xf0,0x99,0xc0 = le lr, #-0x130 +0x0f,0xf0,0x0d,0xce = le lr, #-0xc1a +0x0f,0xf0,0x4f,0xc6 = le lr, #-0xc9c +0x0f,0xf0,0x7b,0xc6 = le lr, #-0xcf4 +0x0f,0xf0,0x83,0xc6 = le lr, #-0xd04 +0x0f,0xf0,0x8d,0xce = le lr, #-0xd1a +0x0f,0xf0,0xbd,0xcf = le lr, #-0xf7a +0x0f,0xf0,0xe5,0xcf = le lr, #-0xfca +0x0f,0xf0,0xeb,0xc7 = le lr, #-0xfd4 +0x0f,0xf0,0xe5,0xc8 = le lr, #-0x1ca +0x0f,0xf0,0x1d,0xc0 = le lr, #-0x38 +0x0f,0xf0,0x23,0xc9 = le lr, #-0x246 +0x0f,0xf0,0x53,0xc1 = le lr, #-0x2a4 +0x0f,0xf0,0x79,0xc1 = le lr, #-0x2f0 +0x0f,0xf0,0x27,0xc0 = le lr, #-0x4c +0x0f,0xf0,0x91,0xc9 = le lr, #-0x322 +0x0f,0xf0,0xaf,0xc9 = le lr, #-0x35e +0x0f,0xf0,0xc3,0xc9 = le lr, #-0x386 +0x0f,0xf0,0xe5,0xc1 = le lr, #-0x3c8 +0x4e,0xf0,0x55,0xc2 = wls lr, lr, #0x4a8 +0x4e,0xf0,0x2b,0xcc = wls lr, lr, #0x856 +0x4e,0xf0,0xe1,0xc9 = wls lr, lr, #0x3c2 +0x40,0xf0,0x43,0xc3 = wls lr, r0, #0x684 +0x40,0xf0,0x49,0xcd = wls lr, r0, #0xa92 +0x40,0xf0,0xe9,0xcd = wls lr, r0, #0xbd2 +0x40,0xf0,0xb7,0xc6 = wls lr, r0, #0xd6c +0x41,0xf0,0x13,0xc2 = wls lr, r1, #0x424 +0x41,0xf0,0xe3,0xc7 = wls lr, r1, #0xfc4 +0x41,0xf0,0x0d,0xc9 = wls lr, r1, #0x21a +0x4a,0xf0,0xbf,0xc2 = wls lr, r10, #0x57c +0x4a,0xf0,0xc1,0xc2 = wls lr, r10, #0x580 +0x4a,0xf0,0x9b,0xcc = wls lr, r10, #0x936 +0x4a,0xf0,0xfb,0xcf = wls lr, r10, #0xff6 +0x4b,0xf0,0xd1,0xca = wls lr, r11, #0x5a2 +0x4b,0xf0,0x3b,0xcd = wls lr, r11, #0xa76 +0x4b,0xf0,0x0d,0xcf = wls lr, r11, #0xe1a +0x4c,0xf0,0x67,0xc8 = wls lr, r12, #0xce +0x4c,0xf0,0xa9,0xc5 = wls lr, r12, #0xb50 +0x4c,0xf0,0x5d,0xce = wls lr, r12, #0xcba +0x42,0xf0,0x55,0xce = wls lr, r2, #0xcaa +0x42,0xf0,0x7d,0xc7 = wls lr, r2, #0xef8 +0x42,0xf0,0xb5,0xc1 = wls lr, r2, #0x368 +0x43,0xf0,0xdd,0xce = wls lr, r3, #0xdba +0x43,0xf0,0x1b,0xc7 = wls lr, r3, #0xe34 +0x43,0xf0,0xb3,0xcf = wls lr, r3, #0xf66 +0x43,0xf0,0x65,0xc1 = wls lr, r3, #0x2c8 +0x44,0xf0,0x31,0xcc = wls lr, r4, #0x862 +0x44,0xf0,0xdb,0xcc = wls lr, r4, #0x9b6 +0x45,0xf0,0xb9,0xcb = wls lr, r5, #0x772 +0x45,0xf0,0xa3,0xc6 = wls lr, r5, #0xd44 +0x46,0xf0,0x7f,0xce = wls lr, r6, #0xcfe +0x46,0xf0,0xd1,0xc0 = wls lr, r6, #0x1a0 +0x46,0xf0,0xd3,0xc8 = wls lr, r6, #0x1a6 +0x47,0xf0,0xc9,0xce = wls lr, r7, #0xd92 +0x47,0xf0,0x1d,0xc7 = wls lr, r7, #0xe38 +0x48,0xf0,0x47,0xc5 = wls lr, r8, #0xa8c +0x49,0xf0,0x2d,0xca = wls lr, r9, #0x45a +0x49,0xf0,0xe1,0xc3 = wls lr, r9, #0x7c0 +0x49,0xf0,0x57,0xcf = wls lr, r9, #0xeae +0x49,0xf0,0x6b,0xc7 = wls lr, r9, #0xed4 +0x52,0xea,0x22,0x9e = cinc lr, r2, lo +0x57,0xea,0x47,0x9e = cinc lr, r7, pl +0x5c,0xea,0x3c,0xae = cinv lr, r12, hs +0x5a,0xea,0x3a,0xbe = cneg lr, r10, hs +0x59,0xea,0x7b,0x89 = csel r9, r9, r11, vc +0x5f,0xea,0x1f,0x9e = cset lr, eq +0x5f,0xea,0x3f,0xae = csetm lr, hs +0x5a,0xea,0xd7,0x9e = csinc lr, r10, r7, le +0x55,0xea,0x2f,0xae = csinv lr, r5, zr, hs +0x52,0xea,0x42,0xae = cinv lr, r2, pl +0x50,0xea,0x01,0x80 = csel r0, r0, r1, eq diff --git a/thirdparty/capstone/suite/MC/ARM/thumbv8m.s.cs b/thirdparty/capstone/suite/MC/ARM/thumbv8m.s.cs new file mode 100644 index 0000000..236be89 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/thumbv8m.s.cs @@ -0,0 +1,47 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0xbf,0xf3,0x6f,0x8f = isb sy +0x92,0xfb,0xf3,0xf1 = sdiv r1, r2, r3 +0xb2,0xfb,0xf3,0xf1 = udiv r1, r2, r3 +0xbf,0xf3,0x2f,0x8f = clrex +0x52,0xe8,0x01,0x1f = ldrex r1, [r2, #4] +0xd2,0xe8,0x4f,0x1f = ldrexb r1, [r2] +0xd2,0xe8,0x5f,0x1f = ldrexh r1, [r2] +0x43,0xe8,0x01,0x21 = strex r1, r2, [r3, #4] +0xc3,0xe8,0x41,0x2f = strexb r1, r2, [r3] +0xc3,0xe8,0x51,0x2f = strexh r1, r2, [r3] +0x4f,0xf6,0xff,0x71 = movw r1, #0xffff +0xcf,0xf6,0xff,0x71 = movt r1, #0xffff +0xd2,0xe8,0xaf,0x1f = lda r1, [r2] +0xd2,0xe8,0x8f,0x1f = ldab r1, [r2] +0xd2,0xe8,0x9f,0x1f = ldah r1, [r2] +0xc3,0xe8,0xaf,0x1f = stl r1, [r3] +0xc3,0xe8,0x8f,0x1f = stlb r1, [r3] +0xc3,0xe8,0x9f,0x1f = stlh r1, [r3] +0xd2,0xe8,0xef,0x1f = ldaex r1, [r2] +0xd2,0xe8,0xcf,0x1f = ldaexb r1, [r2] +0xd2,0xe8,0xdf,0x1f = ldaexh r1, [r2] +0xc3,0xe8,0xe1,0x2f = stlex r1, r2, [r3] +0xc3,0xe8,0xc1,0x2f = stlexb r1, r2, [r3] +0xc3,0xe8,0xd1,0x2f = stlexh r1, r2, [r3] +0x7f,0xe9,0x7f,0xe9 = sg +0x04,0x47 = bxns r0 +0x74,0x47 = bxns lr +0x84,0x47 = blxns r0 +0x41,0xe8,0x00,0xf0 = tt r0, r1 +0x4d,0xe8,0x00,0xf0 = tt r0, sp +0x41,0xe8,0x80,0xf0 = tta r0, r1 +0x41,0xe8,0x40,0xf0 = ttt r0, r1 +0x41,0xe8,0xc0,0xf0 = ttat r0, r1 +0xef,0xf3,0x88,0x81 = mrs r1, msp_ns +0x82,0xf3,0x89,0x88 = msr psp_ns, r2 +0xef,0xf3,0x90,0x83 = mrs r3, primask_ns +0x84,0xf3,0x94,0x88 = msr control_ns, r4 +0xef,0xf3,0x98,0x85 = mrs r5, sp_ns +0xef,0xf3,0x0a,0x86 = mrs r6, msplim +0xef,0xf3,0x0b,0x87 = mrs r7, psplim +0x88,0xf3,0x0a,0x88 = msr msplim, r8 +0x89,0xf3,0x0b,0x88 = msr psplim, r9 +0xef,0xf3,0x8a,0x8a = mrs r10, msplim_ns +0x8b,0xf3,0x8b,0x88 = msr psplim_ns, r11 +0xef,0xf3,0x92,0x88 = mrs r8, 0x92 +0x88,0xf3,0x92,0x80 = msr 0x92, r8 diff --git a/thirdparty/capstone/suite/MC/ARM/udf-arm.s.cs b/thirdparty/capstone/suite/MC/ARM/udf-arm.s.cs new file mode 100644 index 0000000..7ae8938 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/udf-arm.s.cs @@ -0,0 +1,2 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0xf0,0x00,0xf0,0xe7 = udf #0 diff --git a/thirdparty/capstone/suite/MC/ARM/udf-thumb-2.s.cs b/thirdparty/capstone/suite/MC/ARM/udf-thumb-2.s.cs new file mode 100644 index 0000000..b18fb6c --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/udf-thumb-2.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x00,0xde = udf #0 +0xf0,0xf7,0x00,0xa0 = udf.w #0 diff --git a/thirdparty/capstone/suite/MC/ARM/udf-thumb.s.cs b/thirdparty/capstone/suite/MC/ARM/udf-thumb.s.cs new file mode 100644 index 0000000..2920cdf --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/udf-thumb.s.cs @@ -0,0 +1,2 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x00,0xde = udf #0 diff --git a/thirdparty/capstone/suite/MC/ARM/vfp4-thumb.s.cs b/thirdparty/capstone/suite/MC/ARM/vfp4-thumb.s.cs new file mode 100644 index 0000000..65be67a --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/vfp4-thumb.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +// 0xe2,0xee,0xa1,0x0b = vfma.f64 d16, d18, d17 +0xa2,0xee,0x00,0x1a = vfma.f32 s2, s4, s0 +0x42,0xef,0xb1,0x0c = vfma.f32 d16, d18, d17 +0x08,0xef,0x50,0x4c = vfma.f32 q2, q4, q0 +// 0xd2,0xee,0xe1,0x0b = vfnma.f64 d16, d18, d17 +0x92,0xee,0x40,0x1a = vfnma.f32 s2, s4, s0 +// 0xe2,0xee,0xe1,0x0b = vfms.f64 d16, d18, d17 +0xa2,0xee,0x40,0x1a = vfms.f32 s2, s4, s0 +0x62,0xef,0xb1,0x0c = vfms.f32 d16, d18, d17 +0x28,0xef,0x50,0x4c = vfms.f32 q2, q4, q0 +// 0xd2,0xee,0xa1,0x0b = vfnms.f64 d16, d18, d17 +0x92,0xee,0x00,0x1a = vfnms.f32 s2, s4, s0 diff --git a/thirdparty/capstone/suite/MC/ARM/vfp4.s.cs b/thirdparty/capstone/suite/MC/ARM/vfp4.s.cs new file mode 100644 index 0000000..370b516 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/vfp4.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +// 0xa1,0x0b,0xe2,0xee = vfma.f64 d16, d18, d17 +0x00,0x1a,0xa2,0xee = vfma.f32 s2, s4, s0 +0xb1,0x0c,0x42,0xf2 = vfma.f32 d16, d18, d17 +0x50,0x4c,0x08,0xf2 = vfma.f32 q2, q4, q0 +// 0xe1,0x0b,0xd2,0xee = vfnma.f64 d16, d18, d17 +0x40,0x1a,0x92,0xee = vfnma.f32 s2, s4, s0 +// 0xe1,0x0b,0xe2,0xee = vfms.f64 d16, d18, d17 +0x40,0x1a,0xa2,0xee = vfms.f32 s2, s4, s0 +0xb1,0x0c,0x62,0xf2 = vfms.f32 d16, d18, d17 +0x50,0x4c,0x28,0xf2 = vfms.f32 q2, q4, q0 +// 0xa1,0x0b,0xd2,0xee = vfnms.f64 d16, d18, d17 +0x00,0x1a,0x92,0xee = vfnms.f32 s2, s4, s0 diff --git a/thirdparty/capstone/suite/MC/ARM/vmov-vmvn-replicate.s.cs b/thirdparty/capstone/suite/MC/ARM/vmov-vmvn-replicate.s.cs new file mode 100644 index 0000000..9e87f25 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/vmov-vmvn-replicate.s.cs @@ -0,0 +1,47 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x3f,0x2e,0x87,0xf3 = vmov.i64 d2, #0xffffffffffffffff +0x7f,0x4e,0x87,0xf3 = vmov.i64 q2, #0xffffffffffffffff +0x1f,0x2e,0x87,0xf3 = vmov.i8 d2, #0xff +0x5f,0x4e,0x87,0xf3 = vmov.i8 q2, #0xff +0x1b,0x2e,0x82,0xf3 = vmov.i8 d2, #0xab +0x5b,0x4e,0x82,0xf3 = vmov.i8 q2, #0xab +0x1b,0x2e,0x82,0xf3 = vmov.i8 d2, #0xab +0x5b,0x4e,0x82,0xf3 = vmov.i8 q2, #0xab +0x5b,0x4e,0x82,0xf3 = vmov.i8 q2, #0xab +0x5b,0x4e,0x82,0xf3 = vmov.i8 q2, #0xab +0x3a,0x2e,0x82,0xf3 = vmov.i64 d2, #0xff00ff00ff00ff00 +0x7a,0x4e,0x82,0xf3 = vmov.i64 q2, #0xff00ff00ff00ff00 +0x15,0x28,0x82,0xf3 = vmov.i16 d2, #0xa5 +0x55,0x48,0x82,0xf3 = vmov.i16 q2, #0xa5 +0x15,0x28,0x82,0xf3 = vmov.i16 d2, #0xa5 +0x55,0x48,0x82,0xf3 = vmov.i16 q2, #0xa5 +0x15,0x2a,0x82,0xf3 = vmov.i16 d2, #0xa500 +0x55,0x4a,0x82,0xf3 = vmov.i16 q2, #0xa500 +0x15,0x2a,0x82,0xf3 = vmov.i16 d2, #0xa500 +0x55,0x4a,0x82,0xf3 = vmov.i16 q2, #0xa500 +0x15,0x20,0x82,0xf3 = vmov.i32 d2, #0xa5 +0x55,0x40,0x82,0xf3 = vmov.i32 q2, #0xa5 +0x15,0x2d,0x82,0xf3 = vmov.i32 d2, #0xa5ffff +0x55,0x4d,0x82,0xf3 = vmov.i32 q2, #0xa5ffff +0x10,0x2e,0x80,0xf2 = vmov.i8 d2, #0x0 +0x50,0x4e,0x80,0xf2 = vmov.i8 q2, #0x0 +0x10,0x2e,0x80,0xf2 = vmov.i8 d2, #0x0 +0x50,0x4e,0x80,0xf2 = vmov.i8 q2, #0x0 +0x14,0x2e,0x85,0xf2 = vmov.i8 d2, #0x54 +0x54,0x4e,0x85,0xf2 = vmov.i8 q2, #0x54 +0x14,0x2e,0x85,0xf2 = vmov.i8 d2, #0x54 +0x54,0x4e,0x85,0xf2 = vmov.i8 q2, #0x54 +0x14,0x2e,0x85,0xf2 = vmov.i8 d2, #0x54 +0x54,0x4e,0x85,0xf2 = vmov.i8 q2, #0x54 +0x35,0x28,0x82,0xf3 = vmvn.i16 d2, #0xa5 +0x75,0x48,0x82,0xf3 = vmvn.i16 q2, #0xa5 +0x35,0x28,0x82,0xf3 = vmvn.i16 d2, #0xa5 +0x75,0x48,0x82,0xf3 = vmvn.i16 q2, #0xa5 +0x35,0x2a,0x82,0xf3 = vmvn.i16 d2, #0xa500 +0x75,0x4a,0x82,0xf3 = vmvn.i16 q2, #0xa500 +0x35,0x2a,0x82,0xf3 = vmvn.i16 d2, #0xa500 +0x75,0x4a,0x82,0xf3 = vmvn.i16 q2, #0xa500 +0x35,0x20,0x82,0xf3 = vmvn.i32 d2, #0xa5 +0x75,0x40,0x82,0xf3 = vmvn.i32 q2, #0xa5 +0x35,0x2d,0x82,0xf3 = vmvn.i32 d2, #0xa5ffff +0x75,0x4d,0x82,0xf3 = vmvn.i32 q2, #0xa5ffff diff --git a/thirdparty/capstone/suite/MC/ARM/vmovhr.s.cs b/thirdparty/capstone/suite/MC/ARM/vmovhr.s.cs new file mode 100644 index 0000000..56a516f --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/vmovhr.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None +0x16,0xee,0x90,0x09 = vmov.f16 r0, s13 +0x0a,0xee,0x90,0x19 = vmov.f16 s21, r1 +0x01,0xee,0x10,0xd9 = vmov.f16 s2, sp +0x12,0xee,0x90,0xd9 = vmov.f16 sp, s5 diff --git a/thirdparty/capstone/suite/MC/ARM/vpush-vpop-thumb.s.cs b/thirdparty/capstone/suite/MC/ARM/vpush-vpop-thumb.s.cs new file mode 100644 index 0000000..1526131 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/vpush-vpop-thumb.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM, CS_MODE_THUMB, None +0x2d,0xed,0x0a,0x8b = vpush {d8, d9, d10, d11, d12} +0x2d,0xed,0x05,0x4a = vpush {s8, s9, s10, s11, s12} +0xbd,0xec,0x0a,0x8b = vpop {d8, d9, d10, d11, d12} +0xbd,0xec,0x05,0x4a = vpop {s8, s9, s10, s11, s12} +0x2d,0xed,0x0a,0x8b = vpush {d8, d9, d10, d11, d12} +0x2d,0xed,0x05,0x4a = vpush {s8, s9, s10, s11, s12} +0xbd,0xec,0x0a,0x8b = vpop {d8, d9, d10, d11, d12} +0xbd,0xec,0x05,0x4a = vpop {s8, s9, s10, s11, s12} diff --git a/thirdparty/capstone/suite/MC/ARM/vpush-vpop.s.cs b/thirdparty/capstone/suite/MC/ARM/vpush-vpop.s.cs new file mode 100644 index 0000000..d369a54 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/vpush-vpop.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM, CS_MODE_ARM, None +0x0a,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12} +0x05,0x4a,0x2d,0xed = vpush {s8, s9, s10, s11, s12} +0x0a,0x8b,0xbd,0xec = vpop {d8, d9, d10, d11, d12} +0x05,0x4a,0xbd,0xec = vpop {s8, s9, s10, s11, s12} +0x0a,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12} +0x05,0x4a,0x2d,0xed = vpush {s8, s9, s10, s11, s12} +0x0a,0x8b,0xbd,0xec = vpop {d8, d9, d10, d11, d12} +0x05,0x4a,0xbd,0xec = vpop {s8, s9, s10, s11, s12} diff --git a/thirdparty/capstone/suite/MC/ARM/vscclrm-asm.s.cs b/thirdparty/capstone/suite/MC/ARM/vscclrm-asm.s.cs new file mode 100644 index 0000000..89a682c --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/vscclrm-asm.s.cs @@ -0,0 +1,10 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None +0x9f,0xec,0x04,0x0a = vscclrm {s0, s1, s2, s3, vpr} +0xdf,0xec,0x06,0x1a = vscclrm {s3, s4, s5, s6, s7, s8, vpr} +0x9f,0xec,0x0c,0x9a = vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr} +0xdf,0xec,0x01,0xfa = vscclrm {s31, vpr} +0x9f,0xec,0x04,0x0b = vscclrm {d0, d1, vpr} +0x9f,0xec,0x08,0x0b = vscclrm {d0, d1, d2, d3, vpr} +0x9f,0xec,0x06,0x5b = vscclrm {d5, d6, d7, vpr} +0x88,0xbf = it hi +0xdf,0xec,0x1d,0x1a = vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr} diff --git a/thirdparty/capstone/suite/MC/ARM/vstrldr_sys.s.cs b/thirdparty/capstone/suite/MC/ARM/vstrldr_sys.s.cs new file mode 100644 index 0000000..d8fcc88 --- /dev/null +++ b/thirdparty/capstone/suite/MC/ARM/vstrldr_sys.s.cs @@ -0,0 +1,48 @@ +# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None +0x80,0xed,0x80,0x2f = vstr fpscr, [r0] +0x09,0xed,0x86,0x4f = vstr fpscr_nzcvqc, [r9, #-0x18] +0x29,0xed,0x86,0x4f = vstr fpscr_nzcvqc, [r9, #-0x18]! +0x29,0xec,0x86,0x4f = vstr fpscr_nzcvqc, [r9], #-0x18 +0x88,0xbf = it hi +0x80,0xed,0x80,0x2f = vstrhi fpscr, [r0] +0x90,0xed,0x80,0x2f = vldr fpscr, [r0] +0x19,0xed,0x86,0x4f = vldr fpscr_nzcvqc, [r9, #-0x18] +0x39,0xed,0x86,0x4f = vldr fpscr_nzcvqc, [r9, #-0x18]! +0x39,0xec,0x86,0x4f = vldr fpscr_nzcvqc, [r9], #-0x18 +0x3d,0xec,0x8d,0x4f = vldr fpscr_nzcvqc, [sp], #-0x34 +0x88,0xbf = it hi +0x90,0xed,0x80,0x2f = vldrhi fpscr, [r0] +0xcc,0xed,0xff,0xef = vstr fpcxts, [r12, #0x1fc] +0xec,0xed,0xff,0xef = vstr fpcxts, [r12, #0x1fc]! +0xec,0xec,0xff,0xef = vstr fpcxts, [r12], #0x1fc +0x6d,0xec,0x86,0xef = vstr fpcxts, [sp], #-0x18 +0xdc,0xed,0xff,0xef = vldr fpcxts, [r12, #0x1fc] +0xfc,0xed,0xff,0xef = vldr fpcxts, [r12, #0x1fc]! +0xfc,0xec,0xff,0xef = vldr fpcxts, [r12], #0x1fc +0x7d,0xec,0x86,0xef = vldr fpcxts, [sp], #-0x18 +0xc0,0xed,0x80,0xcf = vstr fpcxtns, [r0] +0x49,0xed,0x86,0xcf = vstr fpcxtns, [r9, #-0x18] +0xc6,0xed,0xfd,0xcf = vstr fpcxtns, [r6, #0x1f4] +0x4e,0xed,0xff,0xcf = vstr fpcxtns, [lr, #-0x1fc] +0xcc,0xed,0xff,0xcf = vstr fpcxtns, [r12, #0x1fc] +0x6d,0xec,0x86,0xcf = vstr fpcxtns, [sp], #-0x18 +0xd0,0xed,0x80,0xcf = vldr fpcxtns, [r0] +0x59,0xed,0x86,0xcf = vldr fpcxtns, [r9, #-0x18] +0xd6,0xed,0xfd,0xcf = vldr fpcxtns, [r6, #0x1f4] +0x5e,0xed,0xff,0xcf = vldr fpcxtns, [lr, #-0x1fc] +0xdc,0xed,0xff,0xcf = vldr fpcxtns, [r12, #0x1fc] +0x7d,0xec,0x86,0xcf = vldr fpcxtns, [sp], #-0x18 +0xc6,0xed,0xfd,0x8f = vstr vpr, [r6, #0x1f4] +0x4e,0xed,0xff,0xaf = vstr p0, [lr, #-0x1fc] +0xe6,0xed,0xfd,0x8f = vstr vpr, [r6, #0x1f4]! +0x6e,0xed,0xff,0xaf = vstr p0, [lr, #-0x1fc]! +0xe6,0xec,0xfd,0x8f = vstr vpr, [r6], #0x1f4 +0x6e,0xec,0xff,0xaf = vstr p0, [lr], #-0x1fc +0x6d,0xec,0x86,0xaf = vstr p0, [sp], #-0x18 +0xd6,0xed,0xfd,0x8f = vldr vpr, [r6, #0x1f4] +0x5e,0xed,0xff,0xaf = vldr p0, [lr, #-0x1fc] +0xf6,0xed,0xfd,0x8f = vldr vpr, [r6, #0x1f4]! +0x7e,0xed,0xff,0xaf = vldr p0, [lr, #-0x1fc]! +0xf6,0xec,0xfd,0x8f = vldr vpr, [r6], #0x1f4 +0x7e,0xec,0xff,0xaf = vldr p0, [lr], #-0x1fc +0x7d,0xec,0x86,0xaf = vldr p0, [sp], #-0x18 diff --git a/thirdparty/capstone/suite/MC/X86/3DNow.s.cs b/thirdparty/capstone/suite/MC/X86/3DNow.s.cs new file mode 100644 index 0000000..495577a --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/3DNow.s.cs @@ -0,0 +1,29 @@ +# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT +0x0f,0x0f,0xca,0xbf = pavgusb %mm2, %mm1 +0x0f,0x0f,0x5c,0x16,0x09,0xbf = pavgusb 9(%esi, %edx), %mm3 +0x0f,0x0f,0xca,0x1d = pf2id %mm2, %mm1 +0x0f,0x0f,0x5c,0x16,0x09,0x1d = pf2id 9(%esi, %edx), %mm3 +0x0f,0x0f,0xca,0xae = pfacc %mm2, %mm1 +0x0f,0x0f,0xca,0x9e = pfadd %mm2, %mm1 +0x0f,0x0f,0xca,0xb0 = pfcmpeq %mm2, %mm1 +0x0f,0x0f,0xca,0x90 = pfcmpge %mm2, %mm1 +0x0f,0x0f,0xca,0xa0 = pfcmpgt %mm2, %mm1 +0x0f,0x0f,0xca,0xa4 = pfmax %mm2, %mm1 +0x0f,0x0f,0xca,0x94 = pfmin %mm2, %mm1 +0x0f,0x0f,0xca,0xb4 = pfmul %mm2, %mm1 +0x0f,0x0f,0xca,0x96 = pfrcp %mm2, %mm1 +0x0f,0x0f,0xca,0xa6 = pfrcpit1 %mm2, %mm1 +0x0f,0x0f,0xca,0xb6 = pfrcpit2 %mm2, %mm1 +0x0f,0x0f,0xca,0xa7 = pfrsqit1 %mm2, %mm1 +0x0f,0x0f,0xca,0x97 = pfrsqrt %mm2, %mm1 +0x0f,0x0f,0xca,0x9a = pfsub %mm2, %mm1 +0x0f,0x0f,0xca,0xaa = pfsubr %mm2, %mm1 +0x0f,0x0f,0xca,0x0d = pi2fd %mm2, %mm1 +0x0f,0x0f,0xca,0xb7 = pmulhrw %mm2, %mm1 +0x0f,0x0e = femms +0x0f,0x0d,0x00 = prefetch (%eax) +0x0f,0x0f,0xca,0x1c = pf2iw %mm2, %mm1 +0x0f,0x0f,0xca,0x0c = pi2fw %mm2, %mm1 +0x0f,0x0f,0xca,0x8a = pfnacc %mm2, %mm1 +0x0f,0x0f,0xca,0x8e = pfpnacc %mm2, %mm1 +0x0f,0x0f,0xca,0xbb = pswapd %mm2, %mm1 diff --git a/thirdparty/capstone/suite/MC/X86/address-size.s.cs b/thirdparty/capstone/suite/MC/X86/address-size.s.cs new file mode 100644 index 0000000..209e72b --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/address-size.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x67,0xc6,0x06,0x00 = movb $0x0, (%esi) +0xc6,0x06,0x00 = movb $0x0, (%rsi) +0x67,0xc6,0x06,0x00 = movb $0x0, (%esi) +0xc6,0x06,0x00 = movb $0x0, (%rsi) diff --git a/thirdparty/capstone/suite/MC/X86/avx512-encodings.s.cs b/thirdparty/capstone/suite/MC/X86/avx512-encodings.s.cs new file mode 100644 index 0000000..529431a --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/avx512-encodings.s.cs @@ -0,0 +1,12 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x62,0xa3,0x55,0x48,0x38,0xcd,0x01 = vinserti32x4 $1, %xmm21, %zmm5, %zmm17 +0x62,0xe3,0x1d,0x40,0x38,0x4f,0x10,0x01 = vinserti32x4 $1, 256(%rdi), %zmm28, %zmm17 +0x62,0x33,0x7d,0x48,0x39,0xc9,0x01 = vextracti32x4 $1, %zmm9, %xmm17 +0x62,0x33,0xfd,0x48,0x3b,0xc9,0x01 = vextracti64x4 $1, %zmm9, %ymm17 +0x62,0x73,0xfd,0x48,0x3b,0x4f,0x10,0x01 = vextracti64x4 $1, %zmm9, 512(%rdi) +0x62,0xb1,0x35,0x40,0x72,0xe1,0x02 = vpsrad $2, %zmm17, %zmm25 +0x62,0xf1,0x35,0x40,0x72,0x64,0xb7,0x08,0x02 = vpsrad $2, 512(%rdi, %rsi, 4), %zmm25 +0x62,0x21,0x1d,0x48,0xe2,0xc9 = vpsrad %xmm17, %zmm12, %zmm25 +0x62,0x61,0x1d,0x48,0xe2,0x4c,0xb7,0x20 = vpsrad 512(%rdi, %rsi, 4), %zmm12, %zmm25 +0x62,0xf2,0x7d,0xc9,0x58,0xc8 = vpbroadcastd %xmm0, %zmm1 {%k1} {z} +0x62,0xf1,0xfe,0x4b,0x6f,0xc8 = vmovdqu64 %zmm0, %zmm1 {%k3} diff --git a/thirdparty/capstone/suite/MC/X86/intel-syntax-encoding.s.cs b/thirdparty/capstone/suite/MC/X86/intel-syntax-encoding.s.cs new file mode 100644 index 0000000..452c2ed --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/intel-syntax-encoding.s.cs @@ -0,0 +1,30 @@ +# CS_ARCH_X86, CS_MODE_64, None +0x66,0x83,0xf0,0x0c = xor ax, 12 +0x83,0xf0,0x0c = xor eax, 12 +0x48,0x83,0xf0,0x0c = xor rax, 12 +0x66,0x83,0xc8,0x0c = or ax, 12 +0x83,0xc8,0x0c = or eax, 12 +0x48,0x83,0xc8,0x0c = or rax, 12 +0x66,0x83,0xf8,0x0c = cmp ax, 12 +0x83,0xf8,0x0c = cmp eax, 12 +0x48,0x83,0xf8,0x0c = cmp rax, 12 +0x48,0x89,0x44,0x24,0xf0 = mov QWORD PTR [RSP - 16], RAX +0x66,0x83,0xc0,0xf4 = add ax, -12 +0x83,0xc0,0xf4 = add eax, -12 +0x48,0x83,0xc0,0xf4 = add rax, -12 +0x66,0x83,0xd0,0xf4 = adc ax, -12 +0x83,0xd0,0xf4 = adc eax, -12 +0x48,0x83,0xd0,0xf4 = adc rax, -12 +0x66,0x83,0xd8,0xf4 = sbb ax, -12 +0x83,0xd8,0xf4 = sbb eax, -12 +0x48,0x83,0xd8,0xf4 = sbb rax, -12 +0x66,0x83,0xf8,0xf4 = cmp ax, -12 +0x83,0xf8,0xf4 = cmp eax, -12 +0x48,0x83,0xf8,0xf4 = cmp rax, -12 +0xf2,0x0f,0x10,0x2c,0x25,0xf8,0xff,0xff,0xff = movsd xmm5, qword ptr [0xfffffffffffffff8] +0xd1,0xe7 = shl EDI, 1 +0x0f,0xc2,0xd1,0x01 = cmpltps XMM2, XMM1 +0xc3 = ret +0xcb = retf +0xc2,0x08,0x00 = ret 8 +0xca,0x08,0x00 = retf 8 diff --git a/thirdparty/capstone/suite/MC/X86/x86-32-avx.s.cs b/thirdparty/capstone/suite/MC/X86/x86-32-avx.s.cs new file mode 100644 index 0000000..2239e1c --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86-32-avx.s.cs @@ -0,0 +1,826 @@ +# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT +0xc5,0xca,0x58,0xd4 = vaddss %xmm4, %xmm6, %xmm2 +0xc5,0xca,0x59,0xd4 = vmulss %xmm4, %xmm6, %xmm2 +0xc5,0xca,0x5c,0xd4 = vsubss %xmm4, %xmm6, %xmm2 +0xc5,0xca,0x5e,0xd4 = vdivss %xmm4, %xmm6, %xmm2 +0xc5,0xcb,0x58,0xd4 = vaddsd %xmm4, %xmm6, %xmm2 +0xc5,0xcb,0x59,0xd4 = vmulsd %xmm4, %xmm6, %xmm2 +0xc5,0xcb,0x5c,0xd4 = vsubsd %xmm4, %xmm6, %xmm2 +0xc5,0xcb,0x5e,0xd4 = vdivsd %xmm4, %xmm6, %xmm2 +0xc5,0xea,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde = vaddss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xea,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde = vsubss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xea,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde = vmulss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xea,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde = vdivss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xeb,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde = vaddsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xeb,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde = vsubsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xeb,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde = vmulsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xeb,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde = vdivsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xc8,0x58,0xd4 = vaddps %xmm4, %xmm6, %xmm2 +0xc5,0xc8,0x5c,0xd4 = vsubps %xmm4, %xmm6, %xmm2 +0xc5,0xc8,0x59,0xd4 = vmulps %xmm4, %xmm6, %xmm2 +0xc5,0xc8,0x5e,0xd4 = vdivps %xmm4, %xmm6, %xmm2 +0xc5,0xc9,0x58,0xd4 = vaddpd %xmm4, %xmm6, %xmm2 +0xc5,0xc9,0x5c,0xd4 = vsubpd %xmm4, %xmm6, %xmm2 +0xc5,0xc9,0x59,0xd4 = vmulpd %xmm4, %xmm6, %xmm2 +0xc5,0xc9,0x5e,0xd4 = vdivpd %xmm4, %xmm6, %xmm2 +0xc5,0xe8,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde = vaddps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe8,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde = vsubps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe8,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde = vmulps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe8,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde = vdivps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe9,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde = vaddpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe9,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde = vsubpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe9,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde = vmulpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe9,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde = vdivpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xda,0x5f,0xf2 = vmaxss %xmm2, %xmm4, %xmm6 +0xc5,0xdb,0x5f,0xf2 = vmaxsd %xmm2, %xmm4, %xmm6 +0xc5,0xda,0x5d,0xf2 = vminss %xmm2, %xmm4, %xmm6 +0xc5,0xdb,0x5d,0xf2 = vminsd %xmm2, %xmm4, %xmm6 +0xc5,0xea,0x5f,0x6c,0xcb,0xfc = vmaxss -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xeb,0x5f,0x6c,0xcb,0xfc = vmaxsd -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xea,0x5d,0x6c,0xcb,0xfc = vminss -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xeb,0x5d,0x6c,0xcb,0xfc = vminsd -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xd8,0x5f,0xf2 = vmaxps %xmm2, %xmm4, %xmm6 +0xc5,0xd9,0x5f,0xf2 = vmaxpd %xmm2, %xmm4, %xmm6 +0xc5,0xd8,0x5d,0xf2 = vminps %xmm2, %xmm4, %xmm6 +0xc5,0xd9,0x5d,0xf2 = vminpd %xmm2, %xmm4, %xmm6 +0xc5,0xe8,0x5f,0x6c,0xcb,0xfc = vmaxps -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe9,0x5f,0x6c,0xcb,0xfc = vmaxpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe8,0x5d,0x6c,0xcb,0xfc = vminps -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe9,0x5d,0x6c,0xcb,0xfc = vminpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xd8,0x54,0xf2 = vandps %xmm2, %xmm4, %xmm6 +0xc5,0xd9,0x54,0xf2 = vandpd %xmm2, %xmm4, %xmm6 +0xc5,0xe8,0x54,0x6c,0xcb,0xfc = vandps -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe9,0x54,0x6c,0xcb,0xfc = vandpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xd8,0x56,0xf2 = vorps %xmm2, %xmm4, %xmm6 +0xc5,0xd9,0x56,0xf2 = vorpd %xmm2, %xmm4, %xmm6 +0xc5,0xe8,0x56,0x6c,0xcb,0xfc = vorps -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe9,0x56,0x6c,0xcb,0xfc = vorpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xd8,0x57,0xf2 = vxorps %xmm2, %xmm4, %xmm6 +0xc5,0xd9,0x57,0xf2 = vxorpd %xmm2, %xmm4, %xmm6 +0xc5,0xe8,0x57,0x6c,0xcb,0xfc = vxorps -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe9,0x57,0x6c,0xcb,0xfc = vxorpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xd8,0x55,0xf2 = vandnps %xmm2, %xmm4, %xmm6 +0xc5,0xd9,0x55,0xf2 = vandnpd %xmm2, %xmm4, %xmm6 +0xc5,0xe8,0x55,0x6c,0xcb,0xfc = vandnps -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe9,0x55,0x6c,0xcb,0xfc = vandnpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xfa,0x10,0x6c,0xcb,0xfc = vmovss -4(%ebx, %ecx, 8), %xmm5 +0xc5,0xea,0x10,0xec = vmovss %xmm4, %xmm2, %xmm5 +0xc5,0xfb,0x10,0x6c,0xcb,0xfc = vmovsd -4(%ebx, %ecx, 8), %xmm5 +0xc5,0xeb,0x10,0xec = vmovsd %xmm4, %xmm2, %xmm5 +0xc5,0xe8,0x15,0xe1 = vunpckhps %xmm1, %xmm2, %xmm4 +0xc5,0xe9,0x15,0xe1 = vunpckhpd %xmm1, %xmm2, %xmm4 +0xc5,0xe8,0x14,0xe1 = vunpcklps %xmm1, %xmm2, %xmm4 +0xc5,0xe9,0x14,0xe1 = vunpcklpd %xmm1, %xmm2, %xmm4 +0xc5,0xe8,0x15,0x6c,0xcb,0xfc = vunpckhps -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe9,0x15,0x6c,0xcb,0xfc = vunpckhpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe8,0x14,0x6c,0xcb,0xfc = vunpcklps -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xe9,0x14,0x6c,0xcb,0xfc = vunpcklpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 +0xc5,0xc8,0xc2,0xc8,0x00 = vcmpeqps %xmm0, %xmm6, %xmm1 +0xc5,0xc8,0xc2,0x08,0x00 = vcmpeqps (%eax), %xmm6, %xmm1 +0xc5,0xc8,0xc2,0xc8,0x07 = vcmpordps %xmm0, %xmm6, %xmm1 +0xc5,0xc9,0xc2,0xc8,0x00 = vcmpeqpd %xmm0, %xmm6, %xmm1 +0xc5,0xc9,0xc2,0x08,0x00 = vcmpeqpd (%eax), %xmm6, %xmm1 +0xc5,0xc9,0xc2,0xc8,0x07 = vcmpordpd %xmm0, %xmm6, %xmm1 +0xc5,0xe8,0xc6,0xd9,0x08 = vshufps $8, %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc6,0x5c,0xcb,0xfc,0x08 = vshufps $8, -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe9,0xc6,0xd9,0x08 = vshufpd $8, %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xc6,0x5c,0xcb,0xfc,0x08 = vshufpd $8, -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x00 = vcmpeqps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x02 = vcmpleps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x01 = vcmpltps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x04 = vcmpneqps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x06 = vcmpnleps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x05 = vcmpnltps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x07 = vcmpordps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x03 = vcmpunordps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x00 = vcmpeqps -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x02 = vcmpleps -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x01 = vcmpltps -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x04 = vcmpneqps -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x06 = vcmpnleps -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x05 = vcmpnltps -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordps -4(%ebx, %ecx, 8), %xmm6, %xmm2 +0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x03 = vcmpunordps -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe9,0xc2,0xd9,0x00 = vcmpeqpd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xc2,0xd9,0x02 = vcmplepd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xc2,0xd9,0x01 = vcmpltpd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xc2,0xd9,0x04 = vcmpneqpd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xc2,0xd9,0x06 = vcmpnlepd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xc2,0xd9,0x05 = vcmpnltpd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xc2,0xd9,0x07 = vcmpordpd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xc2,0xd9,0x03 = vcmpunordpd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x00 = vcmpeqpd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x02 = vcmplepd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x01 = vcmpltpd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x04 = vcmpneqpd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x06 = vcmpnlepd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x05 = vcmpnltpd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordpd -4(%ebx, %ecx, 8), %xmm6, %xmm2 +0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x03 = vcmpunordpd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xf8,0x50,0xc2 = vmovmskps %xmm2, %eax +0xc5,0xf9,0x50,0xc2 = vmovmskpd %xmm2, %eax +0xc5,0xfc,0x50,0xc2 = vmovmskps %ymm2, %eax +0xc5,0xfd,0x50,0xc2 = vmovmskpd %ymm2, %eax +0xc5,0xea,0xc2,0xd9,0x00 = vcmpeqss %xmm1, %xmm2, %xmm3 +0xc5,0xea,0xc2,0xd9,0x02 = vcmpless %xmm1, %xmm2, %xmm3 +0xc5,0xea,0xc2,0xd9,0x01 = vcmpltss %xmm1, %xmm2, %xmm3 +0xc5,0xea,0xc2,0xd9,0x04 = vcmpneqss %xmm1, %xmm2, %xmm3 +0xc5,0xea,0xc2,0xd9,0x06 = vcmpnless %xmm1, %xmm2, %xmm3 +0xc5,0xea,0xc2,0xd9,0x05 = vcmpnltss %xmm1, %xmm2, %xmm3 +0xc5,0xea,0xc2,0xd9,0x07 = vcmpordss %xmm1, %xmm2, %xmm3 +0xc5,0xea,0xc2,0xd9,0x03 = vcmpunordss %xmm1, %xmm2, %xmm3 +0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x00 = vcmpeqss -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x02 = vcmpless -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x01 = vcmpltss -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x04 = vcmpneqss -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x06 = vcmpnless -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x05 = vcmpnltss -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordss -4(%ebx, %ecx, 8), %xmm6, %xmm2 +0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x03 = vcmpunordss -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xeb,0xc2,0xd9,0x00 = vcmpeqsd %xmm1, %xmm2, %xmm3 +0xc5,0xeb,0xc2,0xd9,0x02 = vcmplesd %xmm1, %xmm2, %xmm3 +0xc5,0xeb,0xc2,0xd9,0x01 = vcmpltsd %xmm1, %xmm2, %xmm3 +0xc5,0xeb,0xc2,0xd9,0x04 = vcmpneqsd %xmm1, %xmm2, %xmm3 +0xc5,0xeb,0xc2,0xd9,0x06 = vcmpnlesd %xmm1, %xmm2, %xmm3 +0xc5,0xeb,0xc2,0xd9,0x05 = vcmpnltsd %xmm1, %xmm2, %xmm3 +0xc5,0xeb,0xc2,0xd9,0x07 = vcmpordsd %xmm1, %xmm2, %xmm3 +0xc5,0xeb,0xc2,0xd9,0x03 = vcmpunordsd %xmm1, %xmm2, %xmm3 +0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x00 = vcmpeqsd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x02 = vcmplesd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x01 = vcmpltsd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x04 = vcmpneqsd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x06 = vcmpnlesd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x05 = vcmpnltsd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordsd -4(%ebx, %ecx, 8), %xmm6, %xmm2 +0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x03 = vcmpunordsd -4(%ebx, %ecx, 8), %xmm2, %xmm3 +0xc5,0xf8,0x2e,0xd1 = vucomiss %xmm1, %xmm2 +0xc5,0xf8,0x2e,0x10 = vucomiss (%eax), %xmm2 +0xc5,0xf8,0x2f,0xd1 = vcomiss %xmm1, %xmm2 +0xc5,0xf8,0x2f,0x10 = vcomiss (%eax), %xmm2 +0xc5,0xf9,0x2e,0xd1 = vucomisd %xmm1, %xmm2 +0xc5,0xf9,0x2e,0x10 = vucomisd (%eax), %xmm2 +0xc5,0xf9,0x2f,0xd1 = vcomisd %xmm1, %xmm2 +0xc5,0xf9,0x2f,0x10 = vcomisd (%eax), %xmm2 +0xc5,0xfa,0x2c,0xc1 = vcvttss2si %xmm1, %eax +0xc5,0xf2,0x2a,0x10 = vcvtsi2ssl (%eax), %xmm1, %xmm2 +0xc5,0xfb,0x2c,0xc1 = vcvttsd2si %xmm1, %eax +0xc5,0xfb,0x2c,0x01 = vcvttsd2si (%ecx), %eax +0xc5,0xf3,0x2a,0x10 = vcvtsi2sdl (%eax), %xmm1, %xmm2 +0xc5,0xf8,0x28,0x10 = vmovaps (%eax), %xmm2 +0xc5,0xf8,0x28,0xd1 = vmovaps %xmm1, %xmm2 +0xc5,0xf8,0x29,0x08 = vmovaps %xmm1, (%eax) +0xc5,0xf9,0x28,0x10 = vmovapd (%eax), %xmm2 +0xc5,0xf9,0x28,0xd1 = vmovapd %xmm1, %xmm2 +0xc5,0xf9,0x29,0x08 = vmovapd %xmm1, (%eax) +0xc5,0xf8,0x10,0x10 = vmovups (%eax), %xmm2 +0xc5,0xf8,0x10,0xd1 = vmovups %xmm1, %xmm2 +0xc5,0xf8,0x11,0x08 = vmovups %xmm1, (%eax) +0xc5,0xf9,0x10,0x10 = vmovupd (%eax), %xmm2 +0xc5,0xf9,0x10,0xd1 = vmovupd %xmm1, %xmm2 +0xc5,0xf9,0x11,0x08 = vmovupd %xmm1, (%eax) +0xc5,0xf8,0x13,0x08 = vmovlps %xmm1, (%eax) +0xc5,0xe8,0x12,0x18 = vmovlps (%eax), %xmm2, %xmm3 +0xc5,0xf9,0x13,0x08 = vmovlpd %xmm1, (%eax) +0xc5,0xe9,0x12,0x18 = vmovlpd (%eax), %xmm2, %xmm3 +0xc5,0xf8,0x17,0x08 = vmovhps %xmm1, (%eax) +0xc5,0xe8,0x16,0x18 = vmovhps (%eax), %xmm2, %xmm3 +0xc5,0xf9,0x17,0x08 = vmovhpd %xmm1, (%eax) +0xc5,0xe9,0x16,0x18 = vmovhpd (%eax), %xmm2, %xmm3 +0xc5,0xe8,0x16,0xd9 = vmovlhps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0x12,0xd9 = vmovhlps %xmm1, %xmm2, %xmm3 +0xc5,0xfa,0x2d,0xc1 = vcvtss2si %xmm1, %eax +0xc5,0xfa,0x2d,0x18 = vcvtss2si (%eax), %ebx +0xc5,0xfa,0x2d,0xc1 = vcvtss2si %xmm1, %eax +0xc5,0xfa,0x2d,0x18 = vcvtss2si (%eax), %ebx +0xc5,0xf8,0x5b,0xf5 = vcvtdq2ps %xmm5, %xmm6 +0xc5,0xf8,0x5b,0x30 = vcvtdq2ps (%eax), %xmm6 +0xc5,0xdb,0x5a,0xf2 = vcvtsd2ss %xmm2, %xmm4, %xmm6 +0xc5,0xdb,0x5a,0x30 = vcvtsd2ss (%eax), %xmm4, %xmm6 +0xc5,0xf9,0x5b,0xda = vcvtps2dq %xmm2, %xmm3 +0xc5,0xf9,0x5b,0x18 = vcvtps2dq (%eax), %xmm3 +0xc5,0xda,0x5a,0xf2 = vcvtss2sd %xmm2, %xmm4, %xmm6 +0xc5,0xda,0x5a,0x30 = vcvtss2sd (%eax), %xmm4, %xmm6 +0xc5,0xf8,0x5b,0xf4 = vcvtdq2ps %xmm4, %xmm6 +0xc5,0xf8,0x5b,0x21 = vcvtdq2ps (%ecx), %xmm4 +0xc5,0xfa,0x5b,0xda = vcvttps2dq %xmm2, %xmm3 +0xc5,0xfa,0x5b,0x18 = vcvttps2dq (%eax), %xmm3 +0xc5,0xf8,0x5a,0xda = vcvtps2pd %xmm2, %xmm3 +0xc5,0xf8,0x5a,0x18 = vcvtps2pd (%eax), %xmm3 +0xc5,0xf9,0x5a,0xda = vcvtpd2ps %xmm2, %xmm3 +0xc5,0xf9,0x51,0xd1 = vsqrtpd %xmm1, %xmm2 +0xc5,0xf9,0x51,0x10 = vsqrtpd (%eax), %xmm2 +0xc5,0xf8,0x51,0xd1 = vsqrtps %xmm1, %xmm2 +0xc5,0xf8,0x51,0x10 = vsqrtps (%eax), %xmm2 +0xc5,0xeb,0x51,0xd9 = vsqrtsd %xmm1, %xmm2, %xmm3 +0xc5,0xeb,0x51,0x18 = vsqrtsd (%eax), %xmm2, %xmm3 +0xc5,0xea,0x51,0xd9 = vsqrtss %xmm1, %xmm2, %xmm3 +0xc5,0xea,0x51,0x18 = vsqrtss (%eax), %xmm2, %xmm3 +0xc5,0xf8,0x52,0xd1 = vrsqrtps %xmm1, %xmm2 +0xc5,0xf8,0x52,0x10 = vrsqrtps (%eax), %xmm2 +0xc5,0xea,0x52,0xd9 = vrsqrtss %xmm1, %xmm2, %xmm3 +0xc5,0xea,0x52,0x18 = vrsqrtss (%eax), %xmm2, %xmm3 +0xc5,0xf8,0x53,0xd1 = vrcpps %xmm1, %xmm2 +0xc5,0xf8,0x53,0x10 = vrcpps (%eax), %xmm2 +0xc5,0xea,0x53,0xd9 = vrcpss %xmm1, %xmm2, %xmm3 +0xc5,0xea,0x53,0x18 = vrcpss (%eax), %xmm2, %xmm3 +0xc5,0xf9,0xe7,0x08 = vmovntdq %xmm1, (%eax) +0xc5,0xf9,0x2b,0x08 = vmovntpd %xmm1, (%eax) +0xc5,0xf8,0x2b,0x08 = vmovntps %xmm1, (%eax) +0xc5,0xf8,0xae,0x10 = vldmxcsr (%eax) +0xc5,0xf8,0xae,0x18 = vstmxcsr (%eax) +0xc5,0xf8,0xae,0x15,0xef,0xbe,0xad,0xde = vldmxcsr 0xdeadbeef +0xc5,0xf8,0xae,0x1d,0xef,0xbe,0xad,0xde = vstmxcsr 0xdeadbeef +0xc5,0xe9,0xf8,0xd9 = vpsubb %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xf8,0x18 = vpsubb (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xf9,0xd9 = vpsubw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xf9,0x18 = vpsubw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xfa,0xd9 = vpsubd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xfa,0x18 = vpsubd (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xfb,0xd9 = vpsubq %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xfb,0x18 = vpsubq (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xe8,0xd9 = vpsubsb %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xe8,0x18 = vpsubsb (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xe9,0xd9 = vpsubsw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xe9,0x18 = vpsubsw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xd8,0xd9 = vpsubusb %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xd8,0x18 = vpsubusb (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xd9,0xd9 = vpsubusw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xd9,0x18 = vpsubusw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xfc,0xd9 = vpaddb %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xfc,0x18 = vpaddb (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xfd,0xd9 = vpaddw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xfd,0x18 = vpaddw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xfe,0xd9 = vpaddd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xfe,0x18 = vpaddd (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xd4,0xd9 = vpaddq %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xd4,0x18 = vpaddq (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xec,0xd9 = vpaddsb %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xec,0x18 = vpaddsb (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xed,0xd9 = vpaddsw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xed,0x18 = vpaddsw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xdc,0xd9 = vpaddusb %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xdc,0x18 = vpaddusb (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xdd,0xd9 = vpaddusw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xdd,0x18 = vpaddusw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xe4,0xd9 = vpmulhuw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xe4,0x18 = vpmulhuw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xe5,0xd9 = vpmulhw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xe5,0x18 = vpmulhw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xd5,0xd9 = vpmullw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xd5,0x18 = vpmullw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xf4,0xd9 = vpmuludq %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xf4,0x18 = vpmuludq (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xe0,0xd9 = vpavgb %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xe0,0x18 = vpavgb (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xe3,0xd9 = vpavgw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xe3,0x18 = vpavgw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xea,0xd9 = vpminsw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xea,0x18 = vpminsw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xda,0xd9 = vpminub %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xda,0x18 = vpminub (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xee,0xd9 = vpmaxsw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xee,0x18 = vpmaxsw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xde,0xd9 = vpmaxub %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xde,0x18 = vpmaxub (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xf6,0xd9 = vpsadbw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xf6,0x18 = vpsadbw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xf1,0xd9 = vpsllw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xf1,0x18 = vpsllw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xf2,0xd9 = vpslld %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xf2,0x18 = vpslld (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xf3,0xd9 = vpsllq %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xf3,0x18 = vpsllq (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xe1,0xd9 = vpsraw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xe1,0x18 = vpsraw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xe2,0xd9 = vpsrad %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xe2,0x18 = vpsrad (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xd1,0xd9 = vpsrlw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xd1,0x18 = vpsrlw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xd2,0xd9 = vpsrld %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xd2,0x18 = vpsrld (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xd3,0xd9 = vpsrlq %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xd3,0x18 = vpsrlq (%eax), %xmm2, %xmm3 +0xc5,0xe1,0x72,0xf2,0x0a = vpslld $10, %xmm2, %xmm3 +0xc5,0xe1,0x73,0xfa,0x0a = vpslldq $10, %xmm2, %xmm3 +0xc5,0xe1,0x73,0xf2,0x0a = vpsllq $10, %xmm2, %xmm3 +0xc5,0xe1,0x71,0xf2,0x0a = vpsllw $10, %xmm2, %xmm3 +0xc5,0xe1,0x72,0xe2,0x0a = vpsrad $10, %xmm2, %xmm3 +0xc5,0xe1,0x71,0xe2,0x0a = vpsraw $10, %xmm2, %xmm3 +0xc5,0xe1,0x72,0xd2,0x0a = vpsrld $10, %xmm2, %xmm3 +0xc5,0xe1,0x73,0xda,0x0a = vpsrldq $10, %xmm2, %xmm3 +0xc5,0xe1,0x73,0xd2,0x0a = vpsrlq $10, %xmm2, %xmm3 +0xc5,0xe1,0x71,0xd2,0x0a = vpsrlw $10, %xmm2, %xmm3 +0xc5,0xe1,0x72,0xf2,0x0a = vpslld $10, %xmm2, %xmm3 +0xc5,0xe9,0xdb,0xd9 = vpand %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xdb,0x18 = vpand (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xeb,0xd9 = vpor %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xeb,0x18 = vpor (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xef,0xd9 = vpxor %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xef,0x18 = vpxor (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xdf,0xd9 = vpandn %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0xdf,0x18 = vpandn (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x74,0xd9 = vpcmpeqb %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x74,0x18 = vpcmpeqb (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x75,0xd9 = vpcmpeqw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x75,0x18 = vpcmpeqw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x76,0xd9 = vpcmpeqd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x76,0x18 = vpcmpeqd (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x64,0xd9 = vpcmpgtb %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x64,0x18 = vpcmpgtb (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x65,0xd9 = vpcmpgtw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x65,0x18 = vpcmpgtw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x66,0xd9 = vpcmpgtd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x66,0x18 = vpcmpgtd (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x63,0xd9 = vpacksswb %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x63,0x18 = vpacksswb (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x6b,0xd9 = vpackssdw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x6b,0x18 = vpackssdw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x67,0xd9 = vpackuswb %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x67,0x18 = vpackuswb (%eax), %xmm2, %xmm3 +0xc5,0xf9,0x70,0xda,0x04 = vpshufd $4, %xmm2, %xmm3 +0xc5,0xf9,0x70,0x18,0x04 = vpshufd $4, (%eax), %xmm3 +0xc5,0xfa,0x70,0xda,0x04 = vpshufhw $4, %xmm2, %xmm3 +0xc5,0xfa,0x70,0x18,0x04 = vpshufhw $4, (%eax), %xmm3 +0xc5,0xfb,0x70,0xda,0x04 = vpshuflw $4, %xmm2, %xmm3 +0xc5,0xfb,0x70,0x18,0x04 = vpshuflw $4, (%eax), %xmm3 +0xc5,0xe9,0x60,0xd9 = vpunpcklbw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x60,0x18 = vpunpcklbw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x61,0xd9 = vpunpcklwd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x61,0x18 = vpunpcklwd (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x62,0xd9 = vpunpckldq %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x62,0x18 = vpunpckldq (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x6c,0xd9 = vpunpcklqdq %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x6c,0x18 = vpunpcklqdq (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x68,0xd9 = vpunpckhbw %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x68,0x18 = vpunpckhbw (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x69,0xd9 = vpunpckhwd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x69,0x18 = vpunpckhwd (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x6a,0xd9 = vpunpckhdq %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x6a,0x18 = vpunpckhdq (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x6d,0xd9 = vpunpckhqdq %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x6d,0x18 = vpunpckhqdq (%eax), %xmm2, %xmm3 +0xc5,0xe9,0xc4,0xd8,0x07 = vpinsrw $7, %eax, %xmm2, %xmm3 +0xc5,0xe9,0xc4,0x18,0x07 = vpinsrw $7, (%eax), %xmm2, %xmm3 +0xc5,0xf9,0xc5,0xc2,0x07 = vpextrw $7, %xmm2, %eax +0xc5,0xf9,0xd7,0xc1 = vpmovmskb %xmm1, %eax +0xc5,0xf9,0xf7,0xd1 = vmaskmovdqu %xmm1, %xmm2 +0xc5,0xf9,0x7e,0xc8 = vmovd %xmm1, %eax +0xc5,0xf9,0x7e,0x08 = vmovd %xmm1, (%eax) +0xc5,0xf9,0x6e,0xc8 = vmovd %eax, %xmm1 +0xc5,0xf9,0x6e,0x08 = vmovd (%eax), %xmm1 +0xc5,0xf9,0xd6,0x08 = vmovq %xmm1, (%eax) +0xc5,0xfa,0x7e,0xd1 = vmovq %xmm1, %xmm2 +0xc5,0xfa,0x7e,0x08 = vmovq (%eax), %xmm1 +0xc5,0xfb,0xe6,0xd1 = vcvtpd2dq %xmm1, %xmm2 +0xc5,0xfa,0xe6,0xd1 = vcvtdq2pd %xmm1, %xmm2 +0xc5,0xfa,0xe6,0x10 = vcvtdq2pd (%eax), %xmm2 +0xc5,0xfa,0x16,0xd1 = vmovshdup %xmm1, %xmm2 +0xc5,0xfa,0x16,0x10 = vmovshdup (%eax), %xmm2 +0xc5,0xfa,0x12,0xd1 = vmovsldup %xmm1, %xmm2 +0xc5,0xfa,0x12,0x10 = vmovsldup (%eax), %xmm2 +0xc5,0xfb,0x12,0xd1 = vmovddup %xmm1, %xmm2 +0xc5,0xfb,0x12,0x10 = vmovddup (%eax), %xmm2 +0xc5,0xeb,0xd0,0xd9 = vaddsubps %xmm1, %xmm2, %xmm3 +0xc5,0xf3,0xd0,0x10 = vaddsubps (%eax), %xmm1, %xmm2 +0xc5,0xe9,0xd0,0xd9 = vaddsubpd %xmm1, %xmm2, %xmm3 +0xc5,0xf1,0xd0,0x10 = vaddsubpd (%eax), %xmm1, %xmm2 +0xc5,0xeb,0x7c,0xd9 = vhaddps %xmm1, %xmm2, %xmm3 +0xc5,0xeb,0x7c,0x18 = vhaddps (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x7c,0xd9 = vhaddpd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x7c,0x18 = vhaddpd (%eax), %xmm2, %xmm3 +0xc5,0xeb,0x7d,0xd9 = vhsubps %xmm1, %xmm2, %xmm3 +0xc5,0xeb,0x7d,0x18 = vhsubps (%eax), %xmm2, %xmm3 +0xc5,0xe9,0x7d,0xd9 = vhsubpd %xmm1, %xmm2, %xmm3 +0xc5,0xe9,0x7d,0x18 = vhsubpd (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x79,0x1c,0xd1 = vpabsb %xmm1, %xmm2 +0xc4,0xe2,0x79,0x1c,0x10 = vpabsb (%eax), %xmm2 +0xc4,0xe2,0x79,0x1d,0xd1 = vpabsw %xmm1, %xmm2 +0xc4,0xe2,0x79,0x1d,0x10 = vpabsw (%eax), %xmm2 +0xc4,0xe2,0x79,0x1e,0xd1 = vpabsd %xmm1, %xmm2 +0xc4,0xe2,0x79,0x1e,0x10 = vpabsd (%eax), %xmm2 +0xc4,0xe2,0x69,0x01,0xd9 = vphaddw %xmm1, %xmm2, %xmm3 +0xc4,0xe2,0x69,0x01,0x18 = vphaddw (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x69,0x02,0xd9 = vphaddd %xmm1, %xmm2, %xmm3 +0xc4,0xe2,0x69,0x02,0x18 = vphaddd (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x69,0x03,0xd9 = vphaddsw %xmm1, %xmm2, %xmm3 +0xc4,0xe2,0x69,0x03,0x18 = vphaddsw (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x69,0x05,0xd9 = vphsubw %xmm1, %xmm2, %xmm3 +0xc4,0xe2,0x69,0x05,0x18 = vphsubw (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x69,0x06,0xd9 = vphsubd %xmm1, %xmm2, %xmm3 +0xc4,0xe2,0x69,0x06,0x18 = vphsubd (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x69,0x07,0xd9 = vphsubsw %xmm1, %xmm2, %xmm3 +0xc4,0xe2,0x69,0x07,0x18 = vphsubsw (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x69,0x04,0xd9 = vpmaddubsw %xmm1, %xmm2, %xmm3 +0xc4,0xe2,0x69,0x04,0x18 = vpmaddubsw (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x69,0x00,0xd9 = vpshufb %xmm1, %xmm2, %xmm3 +0xc4,0xe2,0x69,0x00,0x18 = vpshufb (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x69,0x08,0xd9 = vpsignb %xmm1, %xmm2, %xmm3 +0xc4,0xe2,0x69,0x08,0x18 = vpsignb (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x69,0x09,0xd9 = vpsignw %xmm1, %xmm2, %xmm3 +0xc4,0xe2,0x69,0x09,0x18 = vpsignw (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x69,0x0a,0xd9 = vpsignd %xmm1, %xmm2, %xmm3 +0xc4,0xe2,0x69,0x0a,0x18 = vpsignd (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x69,0x0b,0xd9 = vpmulhrsw %xmm1, %xmm2, %xmm3 +0xc4,0xe2,0x69,0x0b,0x18 = vpmulhrsw (%eax), %xmm2, %xmm3 +0xc4,0xe3,0x69,0x0f,0xd9,0x07 = vpalignr $7, %xmm1, %xmm2, %xmm3 +0xc4,0xe3,0x69,0x0f,0x18,0x07 = vpalignr $7, (%eax), %xmm2, %xmm3 +0xc4,0xe3,0x69,0x0b,0xd9,0x07 = vroundsd $7, %xmm1, %xmm2, %xmm3 +0xc4,0xe3,0x69,0x0b,0x18,0x07 = vroundsd $7, (%eax), %xmm2, %xmm3 +0xc4,0xe3,0x69,0x0a,0xd9,0x07 = vroundss $7, %xmm1, %xmm2, %xmm3 +0xc4,0xe3,0x69,0x0a,0x18,0x07 = vroundss $7, (%eax), %xmm2, %xmm3 +0xc4,0xe3,0x79,0x09,0xda,0x07 = vroundpd $7, %xmm2, %xmm3 +0xc4,0xe3,0x79,0x09,0x18,0x07 = vroundpd $7, (%eax), %xmm3 +0xc4,0xe3,0x79,0x08,0xda,0x07 = vroundps $7, %xmm2, %xmm3 +0xc4,0xe3,0x79,0x08,0x18,0x07 = vroundps $7, (%eax), %xmm3 +0xc4,0xe2,0x79,0x41,0xda = vphminposuw %xmm2, %xmm3 +0xc4,0xe2,0x79,0x41,0x10 = vphminposuw (%eax), %xmm2 +0xc4,0xe2,0x61,0x2b,0xca = vpackusdw %xmm2, %xmm3, %xmm1 +0xc4,0xe2,0x69,0x2b,0x18 = vpackusdw (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x61,0x29,0xca = vpcmpeqq %xmm2, %xmm3, %xmm1 +0xc4,0xe2,0x69,0x29,0x18 = vpcmpeqq (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x61,0x38,0xca = vpminsb %xmm2, %xmm3, %xmm1 +0xc4,0xe2,0x69,0x38,0x18 = vpminsb (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x61,0x39,0xca = vpminsd %xmm2, %xmm3, %xmm1 +0xc4,0xe2,0x69,0x39,0x18 = vpminsd (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x61,0x3b,0xca = vpminud %xmm2, %xmm3, %xmm1 +0xc4,0xe2,0x69,0x3b,0x18 = vpminud (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x61,0x3a,0xca = vpminuw %xmm2, %xmm3, %xmm1 +0xc4,0xe2,0x69,0x3a,0x18 = vpminuw (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x61,0x3c,0xca = vpmaxsb %xmm2, %xmm3, %xmm1 +0xc4,0xe2,0x69,0x3c,0x18 = vpmaxsb (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x61,0x3d,0xca = vpmaxsd %xmm2, %xmm3, %xmm1 +0xc4,0xe2,0x69,0x3d,0x18 = vpmaxsd (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x61,0x3f,0xca = vpmaxud %xmm2, %xmm3, %xmm1 +0xc4,0xe2,0x69,0x3f,0x18 = vpmaxud (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x61,0x3e,0xca = vpmaxuw %xmm2, %xmm3, %xmm1 +0xc4,0xe2,0x69,0x3e,0x18 = vpmaxuw (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x61,0x28,0xca = vpmuldq %xmm2, %xmm3, %xmm1 +0xc4,0xe2,0x69,0x28,0x18 = vpmuldq (%eax), %xmm2, %xmm3 +0xc4,0xe2,0x51,0x40,0xca = vpmulld %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0x40,0x18 = vpmulld (%eax), %xmm5, %xmm3 +0xc4,0xe3,0x51,0x0c,0xca,0x03 = vblendps $3, %xmm2, %xmm5, %xmm1 +0xc4,0xe3,0x51,0x0c,0x08,0x03 = vblendps $3, (%eax), %xmm5, %xmm1 +0xc4,0xe3,0x51,0x0d,0xca,0x03 = vblendpd $3, %xmm2, %xmm5, %xmm1 +0xc4,0xe3,0x51,0x0d,0x08,0x03 = vblendpd $3, (%eax), %xmm5, %xmm1 +0xc4,0xe3,0x51,0x0e,0xca,0x03 = vpblendw $3, %xmm2, %xmm5, %xmm1 +0xc4,0xe3,0x51,0x0e,0x08,0x03 = vpblendw $3, (%eax), %xmm5, %xmm1 +0xc4,0xe3,0x51,0x42,0xca,0x03 = vmpsadbw $3, %xmm2, %xmm5, %xmm1 +0xc4,0xe3,0x51,0x42,0x08,0x03 = vmpsadbw $3, (%eax), %xmm5, %xmm1 +0xc4,0xe3,0x51,0x40,0xca,0x03 = vdpps $3, %xmm2, %xmm5, %xmm1 +0xc4,0xe3,0x51,0x40,0x08,0x03 = vdpps $3, (%eax), %xmm5, %xmm1 +0xc4,0xe3,0x51,0x41,0xca,0x03 = vdppd $3, %xmm2, %xmm5, %xmm1 +0xc4,0xe3,0x51,0x41,0x08,0x03 = vdppd $3, (%eax), %xmm5, %xmm1 +0xc4,0xe3,0x71,0x4b,0xdd,0x20 = vblendvpd %xmm2, %xmm5, %xmm1, %xmm3 +0xc4,0xe3,0x71,0x4b,0x18,0x20 = vblendvpd %xmm2, (%eax), %xmm1, %xmm3 +0xc4,0xe3,0x71,0x4a,0xdd,0x20 = vblendvps %xmm2, %xmm5, %xmm1, %xmm3 +0xc4,0xe3,0x71,0x4a,0x18,0x20 = vblendvps %xmm2, (%eax), %xmm1, %xmm3 +0xc4,0xe3,0x71,0x4c,0xdd,0x20 = vpblendvb %xmm2, %xmm5, %xmm1, %xmm3 +0xc4,0xe3,0x71,0x4c,0x18,0x20 = vpblendvb %xmm2, (%eax), %xmm1, %xmm3 +0xc4,0xe2,0x79,0x20,0xea = vpmovsxbw %xmm2, %xmm5 +0xc4,0xe2,0x79,0x20,0x10 = vpmovsxbw (%eax), %xmm2 +0xc4,0xe2,0x79,0x23,0xea = vpmovsxwd %xmm2, %xmm5 +0xc4,0xe2,0x79,0x23,0x10 = vpmovsxwd (%eax), %xmm2 +0xc4,0xe2,0x79,0x25,0xea = vpmovsxdq %xmm2, %xmm5 +0xc4,0xe2,0x79,0x25,0x10 = vpmovsxdq (%eax), %xmm2 +0xc4,0xe2,0x79,0x30,0xea = vpmovzxbw %xmm2, %xmm5 +0xc4,0xe2,0x79,0x30,0x10 = vpmovzxbw (%eax), %xmm2 +0xc4,0xe2,0x79,0x33,0xea = vpmovzxwd %xmm2, %xmm5 +0xc4,0xe2,0x79,0x33,0x10 = vpmovzxwd (%eax), %xmm2 +0xc4,0xe2,0x79,0x35,0xea = vpmovzxdq %xmm2, %xmm5 +0xc4,0xe2,0x79,0x35,0x10 = vpmovzxdq (%eax), %xmm2 +0xc4,0xe2,0x79,0x22,0xea = vpmovsxbq %xmm2, %xmm5 +0xc4,0xe2,0x79,0x22,0x10 = vpmovsxbq (%eax), %xmm2 +0xc4,0xe2,0x79,0x32,0xea = vpmovzxbq %xmm2, %xmm5 +0xc4,0xe2,0x79,0x32,0x10 = vpmovzxbq (%eax), %xmm2 +0xc4,0xe2,0x79,0x21,0xea = vpmovsxbd %xmm2, %xmm5 +0xc4,0xe2,0x79,0x21,0x10 = vpmovsxbd (%eax), %xmm2 +0xc4,0xe2,0x79,0x24,0xea = vpmovsxwq %xmm2, %xmm5 +0xc4,0xe2,0x79,0x24,0x10 = vpmovsxwq (%eax), %xmm2 +0xc4,0xe2,0x79,0x31,0xea = vpmovzxbd %xmm2, %xmm5 +0xc4,0xe2,0x79,0x31,0x10 = vpmovzxbd (%eax), %xmm2 +0xc4,0xe2,0x79,0x34,0xea = vpmovzxwq %xmm2, %xmm5 +0xc4,0xe2,0x79,0x34,0x10 = vpmovzxwq (%eax), %xmm2 +0xc5,0xf9,0xc5,0xc2,0x07 = vpextrw $7, %xmm2, %eax +0xc4,0xe3,0x79,0x15,0x10,0x07 = vpextrw $7, %xmm2, (%eax) +0xc4,0xe3,0x79,0x16,0xd0,0x07 = vpextrd $7, %xmm2, %eax +0xc4,0xe3,0x79,0x16,0x10,0x07 = vpextrd $7, %xmm2, (%eax) +0xc4,0xe3,0x79,0x14,0xd0,0x07 = vpextrb $7, %xmm2, %eax +0xc4,0xe3,0x79,0x14,0x10,0x07 = vpextrb $7, %xmm2, (%eax) +0xc4,0xe3,0x79,0x17,0x10,0x07 = vextractps $7, %xmm2, (%eax) +0xc4,0xe3,0x79,0x17,0xd0,0x07 = vextractps $7, %xmm2, %eax +0xc5,0xe9,0xc4,0xe8,0x07 = vpinsrw $7, %eax, %xmm2, %xmm5 +0xc5,0xe9,0xc4,0x28,0x07 = vpinsrw $7, (%eax), %xmm2, %xmm5 +0xc4,0xe3,0x69,0x20,0xe8,0x07 = vpinsrb $7, %eax, %xmm2, %xmm5 +0xc4,0xe3,0x69,0x20,0x28,0x07 = vpinsrb $7, (%eax), %xmm2, %xmm5 +0xc4,0xe3,0x69,0x22,0xe8,0x07 = vpinsrd $7, %eax, %xmm2, %xmm5 +0xc4,0xe3,0x69,0x22,0x28,0x07 = vpinsrd $7, (%eax), %xmm2, %xmm5 +0xc4,0xe3,0x51,0x21,0xca,0x07 = vinsertps $7, %xmm2, %xmm5, %xmm1 +0xc4,0xe3,0x51,0x21,0x08,0x07 = vinsertps $7, (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x79,0x17,0xea = vptest %xmm2, %xmm5 +0xc4,0xe2,0x79,0x17,0x10 = vptest (%eax), %xmm2 +0xc4,0xe2,0x79,0x2a,0x10 = vmovntdqa (%eax), %xmm2 +0xc4,0xe2,0x51,0x37,0xca = vpcmpgtq %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0x37,0x18 = vpcmpgtq (%eax), %xmm5, %xmm3 +0xc4,0xe3,0x79,0x62,0xea,0x07 = vpcmpistrm $7, %xmm2, %xmm5 +0xc4,0xe3,0x79,0x62,0x28,0x07 = vpcmpistrm $7, (%eax), %xmm5 +0xc4,0xe3,0x79,0x60,0xea,0x07 = vpcmpestrm $7, %xmm2, %xmm5 +0xc4,0xe3,0x79,0x60,0x28,0x07 = vpcmpestrm $7, (%eax), %xmm5 +0xc4,0xe3,0x79,0x63,0xea,0x07 = vpcmpistri $7, %xmm2, %xmm5 +0xc4,0xe3,0x79,0x63,0x28,0x07 = vpcmpistri $7, (%eax), %xmm5 +0xc4,0xe3,0x79,0x61,0xea,0x07 = vpcmpestri $7, %xmm2, %xmm5 +0xc4,0xe3,0x79,0x61,0x28,0x07 = vpcmpestri $7, (%eax), %xmm5 +0xc4,0xe2,0x79,0xdb,0xea = vaesimc %xmm2, %xmm5 +0xc4,0xe2,0x79,0xdb,0x10 = vaesimc (%eax), %xmm2 +0xc4,0xe2,0x51,0xdc,0xca = vaesenc %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xdc,0x18 = vaesenc (%eax), %xmm5, %xmm3 +0xc4,0xe2,0x51,0xdd,0xca = vaesenclast %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xdd,0x18 = vaesenclast (%eax), %xmm5, %xmm3 +0xc4,0xe2,0x51,0xde,0xca = vaesdec %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xde,0x18 = vaesdec (%eax), %xmm5, %xmm3 +0xc4,0xe2,0x51,0xdf,0xca = vaesdeclast %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xdf,0x18 = vaesdeclast (%eax), %xmm5, %xmm3 +0xc4,0xe3,0x79,0xdf,0xea,0x07 = vaeskeygenassist $7, %xmm2, %xmm5 +0xc4,0xe3,0x79,0xdf,0x28,0x07 = vaeskeygenassist $7, (%eax), %xmm5 +0xc5,0xe8,0xc2,0xd9,0x08 = vcmpeq_uqps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x09 = vcmpngeps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x0a = vcmpngtps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x0b = vcmpfalseps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x0c = vcmpneq_oqps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x0d = vcmpgeps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x0e = vcmpgtps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x0f = vcmptrueps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x10 = vcmpeq_osps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x11 = vcmplt_oqps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x12 = vcmple_oqps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x13 = vcmpunord_sps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x14 = vcmpneq_usps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x15 = vcmpnlt_uqps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x16 = vcmpnle_uqps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x17 = vcmpord_sps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x18 = vcmpeq_usps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x19 = vcmpnge_uqps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x1a = vcmpngt_uqps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x1b = vcmpfalse_osps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x1c = vcmpneq_osps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x1d = vcmpge_oqps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x1e = vcmpgt_oqps %xmm1, %xmm2, %xmm3 +0xc5,0xe8,0xc2,0xd9,0x1f = vcmptrue_usps %xmm1, %xmm2, %xmm3 +0xc5,0xfc,0x28,0x10 = vmovaps (%eax), %ymm2 +0xc5,0xfc,0x28,0xd1 = vmovaps %ymm1, %ymm2 +0xc5,0xfc,0x29,0x08 = vmovaps %ymm1, (%eax) +0xc5,0xfd,0x28,0x10 = vmovapd (%eax), %ymm2 +0xc5,0xfd,0x28,0xd1 = vmovapd %ymm1, %ymm2 +0xc5,0xfd,0x29,0x08 = vmovapd %ymm1, (%eax) +0xc5,0xfc,0x10,0x10 = vmovups (%eax), %ymm2 +0xc5,0xfc,0x10,0xd1 = vmovups %ymm1, %ymm2 +0xc5,0xfc,0x11,0x08 = vmovups %ymm1, (%eax) +0xc5,0xfd,0x10,0x10 = vmovupd (%eax), %ymm2 +0xc5,0xfd,0x10,0xd1 = vmovupd %ymm1, %ymm2 +0xc5,0xfd,0x11,0x08 = vmovupd %ymm1, (%eax) +0xc5,0xec,0x15,0xe1 = vunpckhps %ymm1, %ymm2, %ymm4 +0xc5,0xed,0x15,0xe1 = vunpckhpd %ymm1, %ymm2, %ymm4 +0xc5,0xec,0x14,0xe1 = vunpcklps %ymm1, %ymm2, %ymm4 +0xc5,0xed,0x14,0xe1 = vunpcklpd %ymm1, %ymm2, %ymm4 +0xc5,0xec,0x15,0x6c,0xcb,0xfc = vunpckhps -4(%ebx, %ecx, 8), %ymm2, %ymm5 +0xc5,0xed,0x15,0x6c,0xcb,0xfc = vunpckhpd -4(%ebx, %ecx, 8), %ymm2, %ymm5 +0xc5,0xec,0x14,0x6c,0xcb,0xfc = vunpcklps -4(%ebx, %ecx, 8), %ymm2, %ymm5 +0xc5,0xed,0x14,0x6c,0xcb,0xfc = vunpcklpd -4(%ebx, %ecx, 8), %ymm2, %ymm5 +0xc5,0xfd,0xe7,0x08 = vmovntdq %ymm1, (%eax) +0xc5,0xfd,0x2b,0x08 = vmovntpd %ymm1, (%eax) +0xc5,0xfc,0x2b,0x08 = vmovntps %ymm1, (%eax) +0xc5,0xf8,0x50,0xc2 = vmovmskps %xmm2, %eax +0xc5,0xf9,0x50,0xc2 = vmovmskpd %xmm2, %eax +0xc5,0xdc,0x5f,0xf2 = vmaxps %ymm2, %ymm4, %ymm6 +0xc5,0xdd,0x5f,0xf2 = vmaxpd %ymm2, %ymm4, %ymm6 +0xc5,0xdc,0x5d,0xf2 = vminps %ymm2, %ymm4, %ymm6 +0xc5,0xdd,0x5d,0xf2 = vminpd %ymm2, %ymm4, %ymm6 +0xc5,0xdc,0x5c,0xf2 = vsubps %ymm2, %ymm4, %ymm6 +0xc5,0xdd,0x5c,0xf2 = vsubpd %ymm2, %ymm4, %ymm6 +0xc5,0xdc,0x5e,0xf2 = vdivps %ymm2, %ymm4, %ymm6 +0xc5,0xdd,0x5e,0xf2 = vdivpd %ymm2, %ymm4, %ymm6 +0xc5,0xdc,0x58,0xf2 = vaddps %ymm2, %ymm4, %ymm6 +0xc5,0xdd,0x58,0xf2 = vaddpd %ymm2, %ymm4, %ymm6 +0xc5,0xdc,0x59,0xf2 = vmulps %ymm2, %ymm4, %ymm6 +0xc5,0xdd,0x59,0xf2 = vmulpd %ymm2, %ymm4, %ymm6 +0xc5,0xdc,0x5f,0x30 = vmaxps (%eax), %ymm4, %ymm6 +0xc5,0xdd,0x5f,0x30 = vmaxpd (%eax), %ymm4, %ymm6 +0xc5,0xdc,0x5d,0x30 = vminps (%eax), %ymm4, %ymm6 +0xc5,0xdd,0x5d,0x30 = vminpd (%eax), %ymm4, %ymm6 +0xc5,0xdc,0x5c,0x30 = vsubps (%eax), %ymm4, %ymm6 +0xc5,0xdd,0x5c,0x30 = vsubpd (%eax), %ymm4, %ymm6 +0xc5,0xdc,0x5e,0x30 = vdivps (%eax), %ymm4, %ymm6 +0xc5,0xdd,0x5e,0x30 = vdivpd (%eax), %ymm4, %ymm6 +0xc5,0xdc,0x58,0x30 = vaddps (%eax), %ymm4, %ymm6 +0xc5,0xdd,0x58,0x30 = vaddpd (%eax), %ymm4, %ymm6 +0xc5,0xdc,0x59,0x30 = vmulps (%eax), %ymm4, %ymm6 +0xc5,0xdd,0x59,0x30 = vmulpd (%eax), %ymm4, %ymm6 +0xc5,0xfd,0x51,0xd1 = vsqrtpd %ymm1, %ymm2 +0xc5,0xfd,0x51,0x10 = vsqrtpd (%eax), %ymm2 +0xc5,0xfc,0x51,0xd1 = vsqrtps %ymm1, %ymm2 +0xc5,0xfc,0x51,0x10 = vsqrtps (%eax), %ymm2 +0xc5,0xfc,0x52,0xd1 = vrsqrtps %ymm1, %ymm2 +0xc5,0xfc,0x52,0x10 = vrsqrtps (%eax), %ymm2 +0xc5,0xfc,0x53,0xd1 = vrcpps %ymm1, %ymm2 +0xc5,0xfc,0x53,0x10 = vrcpps (%eax), %ymm2 +0xc5,0xdc,0x54,0xf2 = vandps %ymm2, %ymm4, %ymm6 +0xc5,0xdd,0x54,0xf2 = vandpd %ymm2, %ymm4, %ymm6 +0xc5,0xec,0x54,0x6c,0xcb,0xfc = vandps -4(%ebx, %ecx, 8), %ymm2, %ymm5 +0xc5,0xed,0x54,0x6c,0xcb,0xfc = vandpd -4(%ebx, %ecx, 8), %ymm2, %ymm5 +0xc5,0xdc,0x56,0xf2 = vorps %ymm2, %ymm4, %ymm6 +0xc5,0xdd,0x56,0xf2 = vorpd %ymm2, %ymm4, %ymm6 +0xc5,0xec,0x56,0x6c,0xcb,0xfc = vorps -4(%ebx, %ecx, 8), %ymm2, %ymm5 +0xc5,0xed,0x56,0x6c,0xcb,0xfc = vorpd -4(%ebx, %ecx, 8), %ymm2, %ymm5 +0xc5,0xdc,0x57,0xf2 = vxorps %ymm2, %ymm4, %ymm6 +0xc5,0xdd,0x57,0xf2 = vxorpd %ymm2, %ymm4, %ymm6 +0xc5,0xec,0x57,0x6c,0xcb,0xfc = vxorps -4(%ebx, %ecx, 8), %ymm2, %ymm5 +0xc5,0xed,0x57,0x6c,0xcb,0xfc = vxorpd -4(%ebx, %ecx, 8), %ymm2, %ymm5 +0xc5,0xdc,0x55,0xf2 = vandnps %ymm2, %ymm4, %ymm6 +0xc5,0xdd,0x55,0xf2 = vandnpd %ymm2, %ymm4, %ymm6 +0xc5,0xec,0x55,0x6c,0xcb,0xfc = vandnps -4(%ebx, %ecx, 8), %ymm2, %ymm5 +0xc5,0xed,0x55,0x6c,0xcb,0xfc = vandnpd -4(%ebx, %ecx, 8), %ymm2, %ymm5 +0xc5,0xfc,0x5a,0xd3 = vcvtps2pd %xmm3, %ymm2 +0xc5,0xfc,0x5a,0x10 = vcvtps2pd (%eax), %ymm2 +0xc5,0xfe,0xe6,0xd3 = vcvtdq2pd %xmm3, %ymm2 +0xc5,0xfe,0xe6,0x10 = vcvtdq2pd (%eax), %ymm2 +0xc5,0xfc,0x5b,0xea = vcvtdq2ps %ymm2, %ymm5 +0xc5,0xfc,0x5b,0x10 = vcvtdq2ps (%eax), %ymm2 +0xc5,0xfd,0x5b,0xea = vcvtps2dq %ymm2, %ymm5 +0xc5,0xfd,0x5b,0x28 = vcvtps2dq (%eax), %ymm5 +0xc5,0xfe,0x5b,0xea = vcvttps2dq %ymm2, %ymm5 +0xc5,0xfe,0x5b,0x28 = vcvttps2dq (%eax), %ymm5 +0xc5,0xf9,0xe6,0xe9 = vcvttpd2dq %xmm1, %xmm5 +0xc5,0xfd,0xe6,0xea = vcvttpd2dq %ymm2, %xmm5 +0xc5,0xf9,0xe6,0xe9 = vcvttpd2dq %xmm1, %xmm5 +0xc5,0xf9,0xe6,0x08 = vcvttpd2dqx (%eax), %xmm1 +0xc5,0xfd,0xe6,0xca = vcvttpd2dq %ymm2, %xmm1 +0xc5,0xfd,0xe6,0x08 = vcvttpd2dqy (%eax), %xmm1 +0xc5,0xfd,0x5a,0xea = vcvtpd2ps %ymm2, %xmm5 +0xc5,0xf9,0x5a,0xe9 = vcvtpd2ps %xmm1, %xmm5 +0xc5,0xf9,0x5a,0x08 = vcvtpd2psx (%eax), %xmm1 +0xc5,0xfd,0x5a,0xca = vcvtpd2ps %ymm2, %xmm1 +0xc5,0xfd,0x5a,0x08 = vcvtpd2psy (%eax), %xmm1 +0xc5,0xff,0xe6,0xea = vcvtpd2dq %ymm2, %xmm5 +0xc5,0xff,0xe6,0xca = vcvtpd2dq %ymm2, %xmm1 +0xc5,0xff,0xe6,0x08 = vcvtpd2dqy (%eax), %xmm1 +0xc5,0xfb,0xe6,0xe9 = vcvtpd2dq %xmm1, %xmm5 +0xc5,0xfb,0xe6,0x08 = vcvtpd2dqx (%eax), %xmm1 +0xc5,0xec,0xc2,0xd9,0x00 = vcmpeqps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x02 = vcmpleps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x01 = vcmpltps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x04 = vcmpneqps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x06 = vcmpnleps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x05 = vcmpnltps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x07 = vcmpordps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x03 = vcmpunordps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x00 = vcmpeqps -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x02 = vcmpleps -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x01 = vcmpltps -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x04 = vcmpneqps -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x06 = vcmpnleps -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x05 = vcmpnltps -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xcc,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordps -4(%ebx, %ecx, 8), %ymm6, %ymm2 +0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x03 = vcmpunordps -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xed,0xc2,0xd9,0x00 = vcmpeqpd %ymm1, %ymm2, %ymm3 +0xc5,0xed,0xc2,0xd9,0x02 = vcmplepd %ymm1, %ymm2, %ymm3 +0xc5,0xed,0xc2,0xd9,0x01 = vcmpltpd %ymm1, %ymm2, %ymm3 +0xc5,0xed,0xc2,0xd9,0x04 = vcmpneqpd %ymm1, %ymm2, %ymm3 +0xc5,0xed,0xc2,0xd9,0x06 = vcmpnlepd %ymm1, %ymm2, %ymm3 +0xc5,0xed,0xc2,0xd9,0x05 = vcmpnltpd %ymm1, %ymm2, %ymm3 +0xc5,0xed,0xc2,0xd9,0x07 = vcmpordpd %ymm1, %ymm2, %ymm3 +0xc5,0xed,0xc2,0xd9,0x03 = vcmpunordpd %ymm1, %ymm2, %ymm3 +0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x00 = vcmpeqpd -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x02 = vcmplepd -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x01 = vcmpltpd -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x04 = vcmpneqpd -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x06 = vcmpnlepd -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x05 = vcmpnltpd -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xcd,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordpd -4(%ebx, %ecx, 8), %ymm6, %ymm2 +0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x03 = vcmpunordpd -4(%ebx, %ecx, 8), %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x08 = vcmpeq_uqps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x09 = vcmpngeps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x0a = vcmpngtps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x0b = vcmpfalseps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x0c = vcmpneq_oqps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x0d = vcmpgeps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x0e = vcmpgtps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x0f = vcmptrueps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x10 = vcmpeq_osps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x11 = vcmplt_oqps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x12 = vcmple_oqps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x13 = vcmpunord_sps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x14 = vcmpneq_usps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x15 = vcmpnlt_uqps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x16 = vcmpnle_uqps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x17 = vcmpord_sps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x18 = vcmpeq_usps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x19 = vcmpnge_uqps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x1a = vcmpngt_uqps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x1b = vcmpfalse_osps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x1c = vcmpneq_osps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x1d = vcmpge_oqps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x1e = vcmpgt_oqps %ymm1, %ymm2, %ymm3 +0xc5,0xec,0xc2,0xd9,0x1f = vcmptrue_usps %ymm1, %ymm2, %ymm3 +0xc5,0xef,0xd0,0xd9 = vaddsubps %ymm1, %ymm2, %ymm3 +0xc5,0xf7,0xd0,0x10 = vaddsubps (%eax), %ymm1, %ymm2 +0xc5,0xed,0xd0,0xd9 = vaddsubpd %ymm1, %ymm2, %ymm3 +0xc5,0xf5,0xd0,0x10 = vaddsubpd (%eax), %ymm1, %ymm2 +0xc5,0xef,0x7c,0xd9 = vhaddps %ymm1, %ymm2, %ymm3 +0xc5,0xef,0x7c,0x18 = vhaddps (%eax), %ymm2, %ymm3 +0xc5,0xed,0x7c,0xd9 = vhaddpd %ymm1, %ymm2, %ymm3 +0xc5,0xed,0x7c,0x18 = vhaddpd (%eax), %ymm2, %ymm3 +0xc5,0xef,0x7d,0xd9 = vhsubps %ymm1, %ymm2, %ymm3 +0xc5,0xef,0x7d,0x18 = vhsubps (%eax), %ymm2, %ymm3 +0xc5,0xed,0x7d,0xd9 = vhsubpd %ymm1, %ymm2, %ymm3 +0xc5,0xed,0x7d,0x18 = vhsubpd (%eax), %ymm2, %ymm3 +0xc4,0xe3,0x55,0x0c,0xca,0x03 = vblendps $3, %ymm2, %ymm5, %ymm1 +0xc4,0xe3,0x55,0x0c,0x08,0x03 = vblendps $3, (%eax), %ymm5, %ymm1 +0xc4,0xe3,0x55,0x0d,0xca,0x03 = vblendpd $3, %ymm2, %ymm5, %ymm1 +0xc4,0xe3,0x55,0x0d,0x08,0x03 = vblendpd $3, (%eax), %ymm5, %ymm1 +0xc4,0xe3,0x55,0x40,0xca,0x03 = vdpps $3, %ymm2, %ymm5, %ymm1 +0xc4,0xe3,0x55,0x40,0x08,0x03 = vdpps $3, (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x7d,0x1a,0x10 = vbroadcastf128 (%eax), %ymm2 +0xc4,0xe2,0x7d,0x19,0x10 = vbroadcastsd (%eax), %ymm2 +0xc4,0xe2,0x79,0x18,0x10 = vbroadcastss (%eax), %xmm2 +0xc4,0xe2,0x7d,0x18,0x10 = vbroadcastss (%eax), %ymm2 +0xc4,0xe3,0x6d,0x18,0xea,0x07 = vinsertf128 $7, %xmm2, %ymm2, %ymm5 +0xc4,0xe3,0x6d,0x18,0x28,0x07 = vinsertf128 $7, (%eax), %ymm2, %ymm5 +0xc4,0xe3,0x7d,0x19,0xd2,0x07 = vextractf128 $7, %ymm2, %xmm2 +0xc4,0xe3,0x7d,0x19,0x10,0x07 = vextractf128 $7, %ymm2, (%eax) +0xc4,0xe2,0x51,0x2f,0x10 = vmaskmovpd %xmm2, %xmm5, (%eax) +0xc4,0xe2,0x55,0x2f,0x10 = vmaskmovpd %ymm2, %ymm5, (%eax) +0xc4,0xe2,0x69,0x2d,0x28 = vmaskmovpd (%eax), %xmm2, %xmm5 +0xc4,0xe2,0x6d,0x2d,0x28 = vmaskmovpd (%eax), %ymm2, %ymm5 +0xc4,0xe2,0x51,0x2e,0x10 = vmaskmovps %xmm2, %xmm5, (%eax) +0xc4,0xe2,0x55,0x2e,0x10 = vmaskmovps %ymm2, %ymm5, (%eax) +0xc4,0xe2,0x69,0x2c,0x28 = vmaskmovps (%eax), %xmm2, %xmm5 +0xc4,0xe2,0x6d,0x2c,0x28 = vmaskmovps (%eax), %ymm2, %ymm5 +0xc4,0xe3,0x79,0x04,0xe9,0x07 = vpermilps $7, %xmm1, %xmm5 +0xc4,0xe3,0x7d,0x04,0xcd,0x07 = vpermilps $7, %ymm5, %ymm1 +0xc4,0xe3,0x79,0x04,0x28,0x07 = vpermilps $7, (%eax), %xmm5 +0xc4,0xe3,0x7d,0x04,0x28,0x07 = vpermilps $7, (%eax), %ymm5 +0xc4,0xe2,0x51,0x0c,0xc9 = vpermilps %xmm1, %xmm5, %xmm1 +0xc4,0xe2,0x55,0x0c,0xc9 = vpermilps %ymm1, %ymm5, %ymm1 +0xc4,0xe2,0x51,0x0c,0x18 = vpermilps (%eax), %xmm5, %xmm3 +0xc4,0xe2,0x55,0x0c,0x08 = vpermilps (%eax), %ymm5, %ymm1 +0xc4,0xe3,0x79,0x05,0xe9,0x07 = vpermilpd $7, %xmm1, %xmm5 +0xc4,0xe3,0x7d,0x05,0xcd,0x07 = vpermilpd $7, %ymm5, %ymm1 +0xc4,0xe3,0x79,0x05,0x28,0x07 = vpermilpd $7, (%eax), %xmm5 +0xc4,0xe3,0x7d,0x05,0x28,0x07 = vpermilpd $7, (%eax), %ymm5 +0xc4,0xe2,0x51,0x0d,0xc9 = vpermilpd %xmm1, %xmm5, %xmm1 +0xc4,0xe2,0x55,0x0d,0xc9 = vpermilpd %ymm1, %ymm5, %ymm1 +0xc4,0xe2,0x51,0x0d,0x18 = vpermilpd (%eax), %xmm5, %xmm3 +0xc4,0xe2,0x55,0x0d,0x08 = vpermilpd (%eax), %ymm5, %ymm1 +0xc4,0xe3,0x55,0x06,0xca,0x07 = vperm2f128 $7, %ymm2, %ymm5, %ymm1 +0xc4,0xe3,0x55,0x06,0x08,0x07 = vperm2f128 $7, (%eax), %ymm5, %ymm1 +0xc5,0xfc,0x77 = vzeroall +0xc5,0xf8,0x77 = vzeroupper +0xc5,0xfb,0x2d,0xcc = vcvtsd2si %xmm4, %ecx +0xc5,0xfb,0x2d,0x09 = vcvtsd2si (%ecx), %ecx +0xc5,0xfb,0x2d,0xcc = vcvtsd2si %xmm4, %ecx +0xc5,0xfb,0x2d,0x09 = vcvtsd2si (%ecx), %ecx +0xc5,0xfb,0x2a,0x7d,0x00 = vcvtsi2sdl (%ebp), %xmm0, %xmm7 +0xc5,0xfb,0x2a,0x3c,0x24 = vcvtsi2sdl (%esp), %xmm0, %xmm7 +0xc5,0xfb,0x2a,0x7d,0x00 = vcvtsi2sdl (%ebp), %xmm0, %xmm7 +0xc5,0xfb,0x2a,0x3c,0x24 = vcvtsi2sdl (%esp), %xmm0, %xmm7 +0xc5,0xff,0xf0,0x10 = vlddqu (%eax), %ymm2 +0xc5,0xff,0x12,0xea = vmovddup %ymm2, %ymm5 +0xc5,0xff,0x12,0x10 = vmovddup (%eax), %ymm2 +0xc5,0xfd,0x6f,0xea = vmovdqa %ymm2, %ymm5 +0xc5,0xfd,0x7f,0x10 = vmovdqa %ymm2, (%eax) +0xc5,0xfd,0x6f,0x10 = vmovdqa (%eax), %ymm2 +0xc5,0xfe,0x6f,0xea = vmovdqu %ymm2, %ymm5 +0xc5,0xfe,0x7f,0x10 = vmovdqu %ymm2, (%eax) +0xc5,0xfe,0x6f,0x10 = vmovdqu (%eax), %ymm2 +0xc5,0xfe,0x16,0xea = vmovshdup %ymm2, %ymm5 +0xc5,0xfe,0x16,0x10 = vmovshdup (%eax), %ymm2 +0xc5,0xfe,0x12,0xea = vmovsldup %ymm2, %ymm5 +0xc5,0xfe,0x12,0x10 = vmovsldup (%eax), %ymm2 +0xc4,0xe2,0x7d,0x17,0xea = vptest %ymm2, %ymm5 +0xc4,0xe2,0x7d,0x17,0x10 = vptest (%eax), %ymm2 +0xc4,0xe3,0x7d,0x09,0xcd,0x07 = vroundpd $7, %ymm5, %ymm1 +0xc4,0xe3,0x7d,0x09,0x28,0x07 = vroundpd $7, (%eax), %ymm5 +0xc4,0xe3,0x7d,0x08,0xcd,0x07 = vroundps $7, %ymm5, %ymm1 +0xc4,0xe3,0x7d,0x08,0x28,0x07 = vroundps $7, (%eax), %ymm5 +0xc5,0xd5,0xc6,0xca,0x07 = vshufpd $7, %ymm2, %ymm5, %ymm1 +0xc5,0xd5,0xc6,0x08,0x07 = vshufpd $7, (%eax), %ymm5, %ymm1 +0xc5,0xd4,0xc6,0xca,0x07 = vshufps $7, %ymm2, %ymm5, %ymm1 +0xc5,0xd4,0xc6,0x08,0x07 = vshufps $7, (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x79,0x0f,0xea = vtestpd %xmm2, %xmm5 +0xc4,0xe2,0x7d,0x0f,0xea = vtestpd %ymm2, %ymm5 +0xc4,0xe2,0x79,0x0f,0x10 = vtestpd (%eax), %xmm2 +0xc4,0xe2,0x7d,0x0f,0x10 = vtestpd (%eax), %ymm2 +0xc4,0xe2,0x79,0x0e,0xea = vtestps %xmm2, %xmm5 +0xc4,0xe2,0x7d,0x0e,0xea = vtestps %ymm2, %ymm5 +0xc4,0xe2,0x79,0x0e,0x10 = vtestps (%eax), %xmm2 +0xc4,0xe2,0x7d,0x0e,0x10 = vtestps (%eax), %ymm2 +0xc4,0xe3,0x75,0x4b,0x94,0x20,0xad,0xde,0x00,0x00,0x00 = vblendvpd %ymm0, 0xdead(%eax), %ymm1, %ymm2 +// 0xc4,0xe3,0x51,0x44,0xca,0x11 = vpclmulhqhqdq %xmm2, %xmm5, %xmm1 +// 0xc4,0xe3,0x51,0x44,0x18,0x11 = vpclmulhqhqdq (%eax), %xmm5, %xmm3 +// 0xc4,0xe3,0x51,0x44,0xca,0x01 = vpclmulhqlqdq %xmm2, %xmm5, %xmm1 +// 0xc4,0xe3,0x51,0x44,0x18,0x01 = vpclmulhqlqdq (%eax), %xmm5, %xmm3 +// 0xc4,0xe3,0x51,0x44,0xca,0x10 = vpclmullqhqdq %xmm2, %xmm5, %xmm1 +// 0xc4,0xe3,0x51,0x44,0x18,0x10 = vpclmullqhqdq (%eax), %xmm5, %xmm3 +// 0xc4,0xe3,0x51,0x44,0xca,0x00 = vpclmullqlqdq %xmm2, %xmm5, %xmm1 +// 0xc4,0xe3,0x51,0x44,0x18,0x00 = vpclmullqlqdq (%eax), %xmm5, %xmm3 +0xc4,0xe3,0x51,0x44,0xca,0x11 = vpclmulqdq $17, %xmm2, %xmm5, %xmm1 +0xc4,0xe3,0x51,0x44,0x18,0x11 = vpclmulqdq $17, (%eax), %xmm5, %xmm3 diff --git a/thirdparty/capstone/suite/MC/X86/x86-32-fma3.s.cs b/thirdparty/capstone/suite/MC/X86/x86-32-fma3.s.cs new file mode 100644 index 0000000..b1bc8db --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86-32-fma3.s.cs @@ -0,0 +1,169 @@ +# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT +0xc4,0xe2,0xd1,0x98,0xca = vfmadd132pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0x98,0x08 = vfmadd132pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0x98,0xca = vfmadd132ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0x98,0x08 = vfmadd132ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xa8,0xca = vfmadd213pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xa8,0x08 = vfmadd213pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xa8,0xca = vfmadd213ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xa8,0x08 = vfmadd213ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xb8,0xca = vfmadd231pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xb8,0x08 = vfmadd231pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xb8,0xca = vfmadd231ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xb8,0x08 = vfmadd231ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd5,0x98,0xca = vfmadd132pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0x98,0x08 = vfmadd132pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0x98,0xca = vfmadd132ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0x98,0x08 = vfmadd132ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xa8,0xca = vfmadd213pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xa8,0x08 = vfmadd213pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xa8,0xca = vfmadd213ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xa8,0x08 = vfmadd213ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xb8,0xca = vfmadd231pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xb8,0x08 = vfmadd231pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xb8,0xca = vfmadd231ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xb8,0x08 = vfmadd231ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd1,0x98,0xca = vfmadd132pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0x98,0x08 = vfmadd132pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0x98,0xca = vfmadd132ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0x98,0x08 = vfmadd132ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xa8,0xca = vfmadd213pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xa8,0x08 = vfmadd213pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xa8,0xca = vfmadd213ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xa8,0x08 = vfmadd213ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xb8,0xca = vfmadd231pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xb8,0x08 = vfmadd231pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xb8,0xca = vfmadd231ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xb8,0x08 = vfmadd231ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0x96,0xca = vfmaddsub132pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0x96,0x08 = vfmaddsub132pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0x96,0xca = vfmaddsub132ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0x96,0x08 = vfmaddsub132ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xa6,0xca = vfmaddsub213pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xa6,0x08 = vfmaddsub213pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xa6,0xca = vfmaddsub213ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xa6,0x08 = vfmaddsub213ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xb6,0xca = vfmaddsub231pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xb6,0x08 = vfmaddsub231pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xb6,0xca = vfmaddsub231ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xb6,0x08 = vfmaddsub231ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0x97,0xca = vfmsubadd132pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0x97,0x08 = vfmsubadd132pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0x97,0xca = vfmsubadd132ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0x97,0x08 = vfmsubadd132ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xa7,0xca = vfmsubadd213pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xa7,0x08 = vfmsubadd213pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xa7,0xca = vfmsubadd213ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xa7,0x08 = vfmsubadd213ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xb7,0xca = vfmsubadd231pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xb7,0x08 = vfmsubadd231pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xb7,0xca = vfmsubadd231ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xb7,0x08 = vfmsubadd231ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0x9a,0xca = vfmsub132pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0x9a,0x08 = vfmsub132pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0x9a,0xca = vfmsub132ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0x9a,0x08 = vfmsub132ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xaa,0xca = vfmsub213pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xaa,0x08 = vfmsub213pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xaa,0xca = vfmsub213ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xaa,0x08 = vfmsub213ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xba,0xca = vfmsub231pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xba,0x08 = vfmsub231pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xba,0xca = vfmsub231ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xba,0x08 = vfmsub231ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0x9c,0xca = vfnmadd132pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0x9c,0x08 = vfnmadd132pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0x9c,0xca = vfnmadd132ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0x9c,0x08 = vfnmadd132ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xac,0xca = vfnmadd213pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xac,0x08 = vfnmadd213pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xac,0xca = vfnmadd213ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xac,0x08 = vfnmadd213ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xbc,0xca = vfnmadd231pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xbc,0x08 = vfnmadd231pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xbc,0xca = vfnmadd231ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xbc,0x08 = vfnmadd231ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0x9e,0xca = vfnmsub132pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0x9e,0x08 = vfnmsub132pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0x9e,0xca = vfnmsub132ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0x9e,0x08 = vfnmsub132ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xae,0xca = vfnmsub213pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xae,0x08 = vfnmsub213pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xae,0xca = vfnmsub213ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xae,0x08 = vfnmsub213ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xbe,0xca = vfnmsub231pd %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0xd1,0xbe,0x08 = vfnmsub231pd (%eax), %xmm5, %xmm1 +0xc4,0xe2,0x51,0xbe,0xca = vfnmsub231ps %xmm2, %xmm5, %xmm1 +0xc4,0xe2,0x51,0xbe,0x08 = vfnmsub231ps (%eax), %xmm5, %xmm1 +0xc4,0xe2,0xd5,0x98,0xca = vfmadd132pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0x98,0x08 = vfmadd132pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0x98,0xca = vfmadd132ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0x98,0x08 = vfmadd132ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xa8,0xca = vfmadd213pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xa8,0x08 = vfmadd213pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xa8,0xca = vfmadd213ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xa8,0x08 = vfmadd213ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xb8,0xca = vfmadd231pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xb8,0x08 = vfmadd231pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xb8,0xca = vfmadd231ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xb8,0x08 = vfmadd231ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0x96,0xca = vfmaddsub132pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0x96,0x08 = vfmaddsub132pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0x96,0xca = vfmaddsub132ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0x96,0x08 = vfmaddsub132ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xa6,0xca = vfmaddsub213pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xa6,0x08 = vfmaddsub213pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xa6,0xca = vfmaddsub213ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xa6,0x08 = vfmaddsub213ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xb6,0xca = vfmaddsub231pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xb6,0x08 = vfmaddsub231pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xb6,0xca = vfmaddsub231ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xb6,0x08 = vfmaddsub231ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0x97,0xca = vfmsubadd132pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0x97,0x08 = vfmsubadd132pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0x97,0xca = vfmsubadd132ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0x97,0x08 = vfmsubadd132ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xa7,0xca = vfmsubadd213pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xa7,0x08 = vfmsubadd213pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xa7,0xca = vfmsubadd213ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xa7,0x08 = vfmsubadd213ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xb7,0xca = vfmsubadd231pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xb7,0x08 = vfmsubadd231pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xb7,0xca = vfmsubadd231ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xb7,0x08 = vfmsubadd231ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0x9a,0xca = vfmsub132pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0x9a,0x08 = vfmsub132pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0x9a,0xca = vfmsub132ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0x9a,0x08 = vfmsub132ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xaa,0xca = vfmsub213pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xaa,0x08 = vfmsub213pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xaa,0xca = vfmsub213ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xaa,0x08 = vfmsub213ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xba,0xca = vfmsub231pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xba,0x08 = vfmsub231pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xba,0xca = vfmsub231ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xba,0x08 = vfmsub231ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0x9c,0xca = vfnmadd132pd %ymm2, %ymm5, %ymm1 +// 0xc4,0xe2,0xd5,0x9c,0x08 = vfnmadd132pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0x9c,0xca = vfnmadd132ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0x9c,0x08 = vfnmadd132ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xac,0xca = vfnmadd213pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xac,0x08 = vfnmadd213pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xac,0xca = vfnmadd213ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xac,0x08 = vfnmadd213ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xbc,0xca = vfnmadd231pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xbc,0x08 = vfnmadd231pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xbc,0xca = vfnmadd231ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xbc,0x08 = vfnmadd231ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0x9e,0xca = vfnmsub132pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0x9e,0x08 = vfnmsub132pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0x9e,0xca = vfnmsub132ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0x9e,0x08 = vfnmsub132ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xae,0xca = vfnmsub213pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xae,0x08 = vfnmsub213pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xae,0xca = vfnmsub213ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xae,0x08 = vfnmsub213ps (%eax), %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xbe,0xca = vfnmsub231pd %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0xd5,0xbe,0x08 = vfnmsub231pd (%eax), %ymm5, %ymm1 +0xc4,0xe2,0x55,0xbe,0xca = vfnmsub231ps %ymm2, %ymm5, %ymm1 +0xc4,0xe2,0x55,0xbe,0x08 = vfnmsub231ps (%eax), %ymm5, %ymm1 diff --git a/thirdparty/capstone/suite/MC/X86/x86-32-ms-inline-asm.s.cs b/thirdparty/capstone/suite/MC/X86/x86-32-ms-inline-asm.s.cs new file mode 100644 index 0000000..6c201df --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86-32-ms-inline-asm.s.cs @@ -0,0 +1,27 @@ +# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT +0x8b,0x03 = movl (%ebx), %eax +0x89,0x4b,0x04 = movl %ecx, 4(%ebx) +0x8b,0x04,0x85,0x04,0x00,0x00,0x00 = movl 4(, %eax, 4), %eax +0x8b,0x04,0x85,0x04,0x00,0x00,0x00 = movl 4(, %eax, 4), %eax +0x8b,0x04,0x06 = movl (%esi, %eax), %eax +0x8b,0x04,0x06 = movl (%esi, %eax), %eax +0x8b,0x04,0x86 = movl (%esi, %eax, 4), %eax +0x8b,0x04,0x86 = movl (%esi, %eax, 4), %eax +0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax +0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax +0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax +0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax +0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax +0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax +0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax +0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax +0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax +0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax +0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax +0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax +0x8b,0x44,0x46,0x10 = movl 16(%esi, %eax, 2), %eax +0x0f,0x18,0x40,0x40 = prefetchnta 64(%eax) +0x60 = pushal +0x61 = popal +0x60 = pushal +0x61 = popal diff --git a/thirdparty/capstone/suite/MC/X86/x86_64-avx-clmul-encoding.s.cs b/thirdparty/capstone/suite/MC/X86/x86_64-avx-clmul-encoding.s.cs new file mode 100644 index 0000000..e5d631e --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86_64-avx-clmul-encoding.s.cs @@ -0,0 +1,11 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +// 0xc4,0x43,0x29,0x44,0xdc,0x11 = vpclmulhqhqdq %xmm12, %xmm10, %xmm11 +// 0xc4,0x63,0x29,0x44,0x28,0x11 = vpclmulhqhqdq (%rax), %xmm10, %xmm13 +// 0xc4,0x43,0x29,0x44,0xdc,0x01 = vpclmulhqlqdq %xmm12, %xmm10, %xmm11 +// 0xc4,0x63,0x29,0x44,0x28,0x01 = vpclmulhqlqdq (%rax), %xmm10, %xmm13 +// 0xc4,0x43,0x29,0x44,0xdc,0x10 = vpclmullqhqdq %xmm12, %xmm10, %xmm11 +// 0xc4,0x63,0x29,0x44,0x28,0x10 = vpclmullqhqdq (%rax), %xmm10, %xmm13 +// 0xc4,0x43,0x29,0x44,0xdc,0x00 = vpclmullqlqdq %xmm12, %xmm10, %xmm11 +// 0xc4,0x63,0x29,0x44,0x28,0x00 = vpclmullqlqdq (%rax), %xmm10, %xmm13 +0xc4,0x43,0x29,0x44,0xdc,0x11 = vpclmulqdq $17, %xmm12, %xmm10, %xmm11 +0xc4,0x63,0x29,0x44,0x28,0x11 = vpclmulqdq $17, (%rax), %xmm10, %xmm13 diff --git a/thirdparty/capstone/suite/MC/X86/x86_64-avx-encoding.s.cs b/thirdparty/capstone/suite/MC/X86/x86_64-avx-encoding.s.cs new file mode 100644 index 0000000..13d6884 --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86_64-avx-encoding.s.cs @@ -0,0 +1,1058 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0xc4,0x41,0x32,0x58,0xd0 = vaddss %xmm8, %xmm9, %xmm10 +0xc4,0x41,0x32,0x59,0xd0 = vmulss %xmm8, %xmm9, %xmm10 +0xc4,0x41,0x32,0x5c,0xd0 = vsubss %xmm8, %xmm9, %xmm10 +0xc4,0x41,0x32,0x5e,0xd0 = vdivss %xmm8, %xmm9, %xmm10 +0xc4,0x41,0x33,0x58,0xd0 = vaddsd %xmm8, %xmm9, %xmm10 +0xc4,0x41,0x33,0x59,0xd0 = vmulsd %xmm8, %xmm9, %xmm10 +0xc4,0x41,0x33,0x5c,0xd0 = vsubsd %xmm8, %xmm9, %xmm10 +0xc4,0x41,0x33,0x5e,0xd0 = vdivsd %xmm8, %xmm9, %xmm10 +0xc5,0x2a,0x58,0x5c,0xd9,0xfc = vaddss -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x2a,0x5c,0x5c,0xd9,0xfc = vsubss -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x2a,0x59,0x5c,0xd9,0xfc = vmulss -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x2a,0x5e,0x5c,0xd9,0xfc = vdivss -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x2b,0x58,0x5c,0xd9,0xfc = vaddsd -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x2b,0x5c,0x5c,0xd9,0xfc = vsubsd -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x2b,0x59,0x5c,0xd9,0xfc = vmulsd -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x2b,0x5e,0x5c,0xd9,0xfc = vdivsd -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc4,0x41,0x20,0x58,0xfa = vaddps %xmm10, %xmm11, %xmm15 +0xc4,0x41,0x20,0x5c,0xfa = vsubps %xmm10, %xmm11, %xmm15 +0xc4,0x41,0x20,0x59,0xfa = vmulps %xmm10, %xmm11, %xmm15 +0xc4,0x41,0x20,0x5e,0xfa = vdivps %xmm10, %xmm11, %xmm15 +0xc4,0x41,0x21,0x58,0xfa = vaddpd %xmm10, %xmm11, %xmm15 +0xc4,0x41,0x21,0x5c,0xfa = vsubpd %xmm10, %xmm11, %xmm15 +0xc4,0x41,0x21,0x59,0xfa = vmulpd %xmm10, %xmm11, %xmm15 +0xc4,0x41,0x21,0x5e,0xfa = vdivpd %xmm10, %xmm11, %xmm15 +0xc5,0x28,0x58,0x5c,0xd9,0xfc = vaddps -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x28,0x5c,0x5c,0xd9,0xfc = vsubps -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x28,0x59,0x5c,0xd9,0xfc = vmulps -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x28,0x5e,0x5c,0xd9,0xfc = vdivps -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x29,0x58,0x5c,0xd9,0xfc = vaddpd -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x29,0x5c,0x5c,0xd9,0xfc = vsubpd -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x29,0x59,0x5c,0xd9,0xfc = vmulpd -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc5,0x29,0x5e,0x5c,0xd9,0xfc = vdivpd -4(%rcx, %rbx, 8), %xmm10, %xmm11 +0xc4,0x41,0x0a,0x5f,0xe2 = vmaxss %xmm10, %xmm14, %xmm12 +0xc4,0x41,0x0b,0x5f,0xe2 = vmaxsd %xmm10, %xmm14, %xmm12 +0xc4,0x41,0x0a,0x5d,0xe2 = vminss %xmm10, %xmm14, %xmm12 +0xc4,0x41,0x0b,0x5d,0xe2 = vminsd %xmm10, %xmm14, %xmm12 +0xc5,0x1a,0x5f,0x54,0xcb,0xfc = vmaxss -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc5,0x1b,0x5f,0x54,0xcb,0xfc = vmaxsd -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc5,0x1a,0x5d,0x54,0xcb,0xfc = vminss -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc5,0x1b,0x5d,0x54,0xcb,0xfc = vminsd -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc4,0x41,0x08,0x5f,0xe2 = vmaxps %xmm10, %xmm14, %xmm12 +0xc4,0x41,0x09,0x5f,0xe2 = vmaxpd %xmm10, %xmm14, %xmm12 +0xc4,0x41,0x08,0x5d,0xe2 = vminps %xmm10, %xmm14, %xmm12 +0xc4,0x41,0x09,0x5d,0xe2 = vminpd %xmm10, %xmm14, %xmm12 +0xc5,0x18,0x5f,0x54,0xcb,0xfc = vmaxps -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc5,0x19,0x5f,0x54,0xcb,0xfc = vmaxpd -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc5,0x18,0x5d,0x54,0xcb,0xfc = vminps -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc5,0x19,0x5d,0x54,0xcb,0xfc = vminpd -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc4,0x41,0x08,0x54,0xe2 = vandps %xmm10, %xmm14, %xmm12 +0xc4,0x41,0x09,0x54,0xe2 = vandpd %xmm10, %xmm14, %xmm12 +0xc5,0x18,0x54,0x54,0xcb,0xfc = vandps -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc5,0x19,0x54,0x54,0xcb,0xfc = vandpd -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc4,0x41,0x08,0x56,0xe2 = vorps %xmm10, %xmm14, %xmm12 +0xc4,0x41,0x09,0x56,0xe2 = vorpd %xmm10, %xmm14, %xmm12 +0xc5,0x18,0x56,0x54,0xcb,0xfc = vorps -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc5,0x19,0x56,0x54,0xcb,0xfc = vorpd -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc4,0x41,0x08,0x57,0xe2 = vxorps %xmm10, %xmm14, %xmm12 +0xc4,0x41,0x09,0x57,0xe2 = vxorpd %xmm10, %xmm14, %xmm12 +0xc5,0x18,0x57,0x54,0xcb,0xfc = vxorps -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc5,0x19,0x57,0x54,0xcb,0xfc = vxorpd -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc4,0x41,0x08,0x55,0xe2 = vandnps %xmm10, %xmm14, %xmm12 +0xc4,0x41,0x09,0x55,0xe2 = vandnpd %xmm10, %xmm14, %xmm12 +0xc5,0x18,0x55,0x54,0xcb,0xfc = vandnps -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc5,0x19,0x55,0x54,0xcb,0xfc = vandnpd -4(%rbx, %rcx, 8), %xmm12, %xmm10 +0xc5,0x7a,0x10,0x54,0xcb,0xfc = vmovss -4(%rbx, %rcx, 8), %xmm10 +0xc4,0x41,0x2a,0x10,0xfe = vmovss %xmm14, %xmm10, %xmm15 +0xc5,0x7b,0x10,0x54,0xcb,0xfc = vmovsd -4(%rbx, %rcx, 8), %xmm10 +0xc4,0x41,0x2b,0x10,0xfe = vmovsd %xmm14, %xmm10, %xmm15 +0xc4,0x41,0x18,0x15,0xef = vunpckhps %xmm15, %xmm12, %xmm13 +0xc4,0x41,0x19,0x15,0xef = vunpckhpd %xmm15, %xmm12, %xmm13 +0xc4,0x41,0x18,0x14,0xef = vunpcklps %xmm15, %xmm12, %xmm13 +0xc4,0x41,0x19,0x14,0xef = vunpcklpd %xmm15, %xmm12, %xmm13 +0xc5,0x18,0x15,0x7c,0xcb,0xfc = vunpckhps -4(%rbx, %rcx, 8), %xmm12, %xmm15 +0xc5,0x19,0x15,0x7c,0xcb,0xfc = vunpckhpd -4(%rbx, %rcx, 8), %xmm12, %xmm15 +0xc5,0x18,0x14,0x7c,0xcb,0xfc = vunpcklps -4(%rbx, %rcx, 8), %xmm12, %xmm15 +0xc5,0x19,0x14,0x7c,0xcb,0xfc = vunpcklpd -4(%rbx, %rcx, 8), %xmm12, %xmm15 +0xc4,0x41,0x18,0xc2,0xfa,0x00 = vcmpeqps %xmm10, %xmm12, %xmm15 +0xc5,0x18,0xc2,0x38,0x00 = vcmpeqps (%rax), %xmm12, %xmm15 +0xc4,0x41,0x18,0xc2,0xfa,0x07 = vcmpordps %xmm10, %xmm12, %xmm15 +0xc4,0x41,0x19,0xc2,0xfa,0x00 = vcmpeqpd %xmm10, %xmm12, %xmm15 +0xc5,0x19,0xc2,0x38,0x00 = vcmpeqpd (%rax), %xmm12, %xmm15 +0xc4,0x41,0x19,0xc2,0xfa,0x07 = vcmpordpd %xmm10, %xmm12, %xmm15 +0xc4,0x41,0x18,0xc6,0xeb,0x08 = vshufps $8, %xmm11, %xmm12, %xmm13 +0xc5,0x18,0xc6,0x6c,0xcb,0xfc,0x08 = vshufps $8, -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc4,0x41,0x19,0xc6,0xeb,0x08 = vshufpd $8, %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xc6,0x6c,0xcb,0xfc,0x08 = vshufpd $8, -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x00 = vcmpeqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x02 = vcmpleps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x01 = vcmpltps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x04 = vcmpneqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x06 = vcmpnleps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x05 = vcmpnltps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x07 = vcmpordps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x03 = vcmpunordps %xmm11, %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x00 = vcmpeqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x02 = vcmpleps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x01 = vcmpltps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x04 = vcmpneqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x06 = vcmpnleps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x05 = vcmpnltps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordps -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x03 = vcmpunordps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x00 = vcmpeqpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x02 = vcmplepd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x01 = vcmpltpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x04 = vcmpneqpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x06 = vcmpnlepd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x05 = vcmpnltpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x07 = vcmpordpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x03 = vcmpunordpd %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x00 = vcmpeqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x02 = vcmplepd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x01 = vcmpltpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x04 = vcmpneqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x06 = vcmpnlepd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x05 = vcmpnltpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordpd -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x03 = vcmpunordpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x00 = vcmpeqss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x02 = vcmpless %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x01 = vcmpltss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x04 = vcmpneqss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x06 = vcmpnless %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x05 = vcmpnltss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x07 = vcmpordss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x03 = vcmpunordss %xmm11, %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x00 = vcmpeqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x02 = vcmpless -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x01 = vcmpltss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x04 = vcmpneqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x06 = vcmpnless -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x05 = vcmpnltss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordss -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x03 = vcmpunordss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x00 = vcmpeqsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x02 = vcmplesd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x01 = vcmpltsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x04 = vcmpneqsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x06 = vcmpnlesd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x05 = vcmpnltsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x07 = vcmpordsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x03 = vcmpunordsd %xmm11, %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x00 = vcmpeqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x02 = vcmplesd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x01 = vcmpltsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x04 = vcmpneqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x06 = vcmpnlesd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x05 = vcmpnltsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordsd -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x03 = vcmpunordsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x08 = vcmpeq_uqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x09 = vcmpngeps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x0a = vcmpngtps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x0b = vcmpfalseps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x0c = vcmpneq_oqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x0d = vcmpgeps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x0e = vcmpgtps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x0f = vcmptrueps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x10 = vcmpeq_osps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x11 = vcmplt_oqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x12 = vcmple_oqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x13 = vcmpunord_sps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x14 = vcmpneq_usps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x15 = vcmpnlt_uqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x16 = vcmpnle_uqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x17 = vcmpord_sps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x18 = vcmpeq_usps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x19 = vcmpnge_uqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x1a = vcmpngt_uqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x1b = vcmpfalse_osps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x1c = vcmpneq_osps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x1d = vcmpge_oqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x1e = vcmpgt_oqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x1f = vcmptrue_usps %xmm11, %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x08 = vcmpeq_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x09 = vcmpngeps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0a = vcmpngtps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0b = vcmpfalseps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0c = vcmpneq_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0d = vcmpgeps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x0e = vcmpgtps -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0f = vcmptrueps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x10 = vcmpeq_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x11 = vcmplt_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x12 = vcmple_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x13 = vcmpunord_sps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x14 = vcmpneq_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x15 = vcmpnlt_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x16 = vcmpnle_uqps -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x17 = vcmpord_sps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x18 = vcmpeq_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x19 = vcmpnge_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1a = vcmpngt_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1b = vcmpfalse_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1c = vcmpneq_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1d = vcmpge_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x1e = vcmpgt_oqps -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1f = vcmptrue_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x08 = vcmpeq_uqpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x09 = vcmpngepd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x0a = vcmpngtpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x0b = vcmpfalsepd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x0c = vcmpneq_oqpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x0d = vcmpgepd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x0e = vcmpgtpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x0f = vcmptruepd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x10 = vcmpeq_ospd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x11 = vcmplt_oqpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x12 = vcmple_oqpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x13 = vcmpunord_spd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x14 = vcmpneq_uspd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x15 = vcmpnlt_uqpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x16 = vcmpnle_uqpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x17 = vcmpord_spd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x18 = vcmpeq_uspd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x19 = vcmpnge_uqpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x1a = vcmpngt_uqpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x1b = vcmpfalse_ospd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x1c = vcmpneq_ospd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x1d = vcmpge_oqpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x1e = vcmpgt_oqpd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x19,0xc2,0xeb,0x1f = vcmptrue_uspd %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x08 = vcmpeq_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x09 = vcmpngepd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0a = vcmpngtpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0b = vcmpfalsepd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0c = vcmpneq_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0d = vcmpgepd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x0e = vcmpgtpd -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0f = vcmptruepd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x10 = vcmpeq_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x11 = vcmplt_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x12 = vcmple_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x13 = vcmpunord_spd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x14 = vcmpneq_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x15 = vcmpnlt_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x16 = vcmpnle_uqpd -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x17 = vcmpord_spd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x18 = vcmpeq_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x19 = vcmpnge_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1a = vcmpngt_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1b = vcmpfalse_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1c = vcmpneq_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1d = vcmpge_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x1e = vcmpgt_oqpd -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1f = vcmptrue_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x08 = vcmpeq_uqss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x09 = vcmpngess %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x0a = vcmpngtss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x0b = vcmpfalsess %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x0c = vcmpneq_oqss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x0d = vcmpgess %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x0e = vcmpgtss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x0f = vcmptruess %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x10 = vcmpeq_osss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x11 = vcmplt_oqss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x12 = vcmple_oqss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x13 = vcmpunord_sss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x14 = vcmpneq_usss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x15 = vcmpnlt_uqss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x16 = vcmpnle_uqss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x17 = vcmpord_sss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x18 = vcmpeq_usss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x19 = vcmpnge_uqss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x1a = vcmpngt_uqss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x1b = vcmpfalse_osss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x1c = vcmpneq_osss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x1d = vcmpge_oqss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x1e = vcmpgt_oqss %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1a,0xc2,0xeb,0x1f = vcmptrue_usss %xmm11, %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x08 = vcmpeq_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x09 = vcmpngess -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0a = vcmpngtss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0b = vcmpfalsess -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0c = vcmpneq_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0d = vcmpgess -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x0e = vcmpgtss -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0f = vcmptruess -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x10 = vcmpeq_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x11 = vcmplt_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x12 = vcmple_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x13 = vcmpunord_sss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x14 = vcmpneq_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x15 = vcmpnlt_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x16 = vcmpnle_uqss -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x17 = vcmpord_sss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x18 = vcmpeq_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x19 = vcmpnge_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1a = vcmpngt_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1b = vcmpfalse_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1c = vcmpneq_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1d = vcmpge_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x1e = vcmpgt_oqss -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1f = vcmptrue_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x08 = vcmpeq_uqsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x09 = vcmpngesd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x0a = vcmpngtsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x0b = vcmpfalsesd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x0c = vcmpneq_oqsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x0d = vcmpgesd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x0e = vcmpgtsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x0f = vcmptruesd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x10 = vcmpeq_ossd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x11 = vcmplt_oqsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x12 = vcmple_oqsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x13 = vcmpunord_ssd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x14 = vcmpneq_ussd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x15 = vcmpnlt_uqsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x16 = vcmpnle_uqsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x17 = vcmpord_ssd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x18 = vcmpeq_ussd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x19 = vcmpnge_uqsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x1a = vcmpngt_uqsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x1b = vcmpfalse_ossd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x1c = vcmpneq_ossd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x1d = vcmpge_oqsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x1e = vcmpgt_oqsd %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x1b,0xc2,0xeb,0x1f = vcmptrue_ussd %xmm11, %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x08 = vcmpeq_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x09 = vcmpngesd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0a = vcmpngtsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0b = vcmpfalsesd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0c = vcmpneq_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0d = vcmpgesd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x0e = vcmpgtsd -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0f = vcmptruesd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x10 = vcmpeq_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x11 = vcmplt_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x12 = vcmple_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x13 = vcmpunord_ssd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x14 = vcmpneq_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x15 = vcmpnlt_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x16 = vcmpnle_uqsd -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x17 = vcmpord_ssd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x18 = vcmpeq_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x19 = vcmpnge_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1a = vcmpngt_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1b = vcmpfalse_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1c = vcmpneq_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1d = vcmpge_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x1e = vcmpgt_oqsd -4(%rbx, %rcx, 8), %xmm6, %xmm2 +0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1f = vcmptrue_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13 +0xc4,0x41,0x78,0x2e,0xe3 = vucomiss %xmm11, %xmm12 +0xc5,0x78,0x2e,0x20 = vucomiss (%rax), %xmm12 +0xc4,0x41,0x78,0x2f,0xe3 = vcomiss %xmm11, %xmm12 +0xc5,0x78,0x2f,0x20 = vcomiss (%rax), %xmm12 +0xc4,0x41,0x79,0x2e,0xe3 = vucomisd %xmm11, %xmm12 +0xc5,0x79,0x2e,0x20 = vucomisd (%rax), %xmm12 +0xc4,0x41,0x79,0x2f,0xe3 = vcomisd %xmm11, %xmm12 +0xc5,0x79,0x2f,0x20 = vcomisd (%rax), %xmm12 +0xc5,0xfa,0x2c,0x01 = vcvttss2si (%rcx), %eax +0xc5,0x22,0x2a,0x20 = vcvtsi2ssl (%rax), %xmm11, %xmm12 +0xc5,0x22,0x2a,0x20 = vcvtsi2ssl (%rax), %xmm11, %xmm12 +0xc5,0xfb,0x2c,0x01 = vcvttsd2si (%rcx), %eax +0xc5,0x23,0x2a,0x20 = vcvtsi2sdl (%rax), %xmm11, %xmm12 +0xc5,0x23,0x2a,0x20 = vcvtsi2sdl (%rax), %xmm11, %xmm12 +0xc5,0x78,0x28,0x20 = vmovaps (%rax), %xmm12 +0xc4,0x41,0x78,0x28,0xe3 = vmovaps %xmm11, %xmm12 +0xc5,0x78,0x29,0x18 = vmovaps %xmm11, (%rax) +0xc5,0x79,0x28,0x20 = vmovapd (%rax), %xmm12 +0xc4,0x41,0x79,0x28,0xe3 = vmovapd %xmm11, %xmm12 +0xc5,0x79,0x29,0x18 = vmovapd %xmm11, (%rax) +0xc5,0x78,0x10,0x20 = vmovups (%rax), %xmm12 +0xc4,0x41,0x78,0x10,0xe3 = vmovups %xmm11, %xmm12 +0xc5,0x78,0x11,0x18 = vmovups %xmm11, (%rax) +0xc5,0x79,0x10,0x20 = vmovupd (%rax), %xmm12 +0xc4,0x41,0x79,0x10,0xe3 = vmovupd %xmm11, %xmm12 +0xc5,0x79,0x11,0x18 = vmovupd %xmm11, (%rax) +0xc5,0x78,0x13,0x18 = vmovlps %xmm11, (%rax) +0xc5,0x18,0x12,0x28 = vmovlps (%rax), %xmm12, %xmm13 +0xc5,0x79,0x13,0x18 = vmovlpd %xmm11, (%rax) +0xc5,0x19,0x12,0x28 = vmovlpd (%rax), %xmm12, %xmm13 +0xc5,0x78,0x17,0x18 = vmovhps %xmm11, (%rax) +0xc5,0x18,0x16,0x28 = vmovhps (%rax), %xmm12, %xmm13 +0xc5,0x79,0x17,0x18 = vmovhpd %xmm11, (%rax) +0xc5,0x19,0x16,0x28 = vmovhpd (%rax), %xmm12, %xmm13 +0xc4,0x41,0x18,0x16,0xeb = vmovlhps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0x12,0xeb = vmovhlps %xmm11, %xmm12, %xmm13 +0xc4,0xc1,0x7a,0x2d,0xc3 = vcvtss2si %xmm11, %eax +0xc5,0xfa,0x2d,0x18 = vcvtss2si (%rax), %ebx +0xc4,0x41,0x78,0x5b,0xe2 = vcvtdq2ps %xmm10, %xmm12 +0xc5,0x78,0x5b,0x20 = vcvtdq2ps (%rax), %xmm12 +0xc4,0x41,0x13,0x5a,0xd4 = vcvtsd2ss %xmm12, %xmm13, %xmm10 +0xc5,0x13,0x5a,0x10 = vcvtsd2ss (%rax), %xmm13, %xmm10 +0xc4,0x41,0x79,0x5b,0xdc = vcvtps2dq %xmm12, %xmm11 +0xc5,0x79,0x5b,0x18 = vcvtps2dq (%rax), %xmm11 +0xc4,0x41,0x12,0x5a,0xd4 = vcvtss2sd %xmm12, %xmm13, %xmm10 +0xc5,0x12,0x5a,0x10 = vcvtss2sd (%rax), %xmm13, %xmm10 +0xc4,0x41,0x78,0x5b,0xd5 = vcvtdq2ps %xmm13, %xmm10 +0xc5,0x78,0x5b,0x29 = vcvtdq2ps (%rcx), %xmm13 +0xc4,0x41,0x7a,0x5b,0xdc = vcvttps2dq %xmm12, %xmm11 +0xc5,0x7a,0x5b,0x18 = vcvttps2dq (%rax), %xmm11 +0xc4,0x41,0x78,0x5a,0xdc = vcvtps2pd %xmm12, %xmm11 +0xc5,0x78,0x5a,0x18 = vcvtps2pd (%rax), %xmm11 +0xc4,0x41,0x79,0x5a,0xdc = vcvtpd2ps %xmm12, %xmm11 +0xc4,0x41,0x79,0x51,0xe3 = vsqrtpd %xmm11, %xmm12 +0xc5,0x79,0x51,0x20 = vsqrtpd (%rax), %xmm12 +0xc4,0x41,0x78,0x51,0xe3 = vsqrtps %xmm11, %xmm12 +0xc5,0x78,0x51,0x20 = vsqrtps (%rax), %xmm12 +0xc4,0x41,0x1b,0x51,0xd3 = vsqrtsd %xmm11, %xmm12, %xmm10 +0xc5,0x1b,0x51,0x10 = vsqrtsd (%rax), %xmm12, %xmm10 +0xc4,0x41,0x1a,0x51,0xd3 = vsqrtss %xmm11, %xmm12, %xmm10 +0xc5,0x1a,0x51,0x10 = vsqrtss (%rax), %xmm12, %xmm10 +0xc4,0x41,0x78,0x52,0xe3 = vrsqrtps %xmm11, %xmm12 +0xc5,0x78,0x52,0x20 = vrsqrtps (%rax), %xmm12 +0xc4,0x41,0x1a,0x52,0xd3 = vrsqrtss %xmm11, %xmm12, %xmm10 +0xc5,0x1a,0x52,0x10 = vrsqrtss (%rax), %xmm12, %xmm10 +0xc4,0x41,0x78,0x53,0xe3 = vrcpps %xmm11, %xmm12 +0xc5,0x78,0x53,0x20 = vrcpps (%rax), %xmm12 +0xc4,0x41,0x1a,0x53,0xd3 = vrcpss %xmm11, %xmm12, %xmm10 +0xc5,0x1a,0x53,0x10 = vrcpss (%rax), %xmm12, %xmm10 +0xc5,0x79,0xe7,0x18 = vmovntdq %xmm11, (%rax) +0xc5,0x79,0x2b,0x18 = vmovntpd %xmm11, (%rax) +0xc5,0x78,0x2b,0x18 = vmovntps %xmm11, (%rax) +0xc5,0xf8,0xae,0x15,0xfc,0xff,0xff,0xff = vldmxcsr -4(%rip) +0xc5,0xf8,0xae,0x5c,0x24,0xfc = vstmxcsr -4(%rsp) +0xc4,0x41,0x19,0xf8,0xeb = vpsubb %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xf8,0x28 = vpsubb (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xf9,0xeb = vpsubw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xf9,0x28 = vpsubw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xfa,0xeb = vpsubd %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xfa,0x28 = vpsubd (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xfb,0xeb = vpsubq %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xfb,0x28 = vpsubq (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xe8,0xeb = vpsubsb %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xe8,0x28 = vpsubsb (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xe9,0xeb = vpsubsw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xe9,0x28 = vpsubsw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xd8,0xeb = vpsubusb %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xd8,0x28 = vpsubusb (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xd9,0xeb = vpsubusw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xd9,0x28 = vpsubusw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xfc,0xeb = vpaddb %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xfc,0x28 = vpaddb (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xfd,0xeb = vpaddw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xfd,0x28 = vpaddw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xfe,0xeb = vpaddd %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xfe,0x28 = vpaddd (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xd4,0xeb = vpaddq %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xd4,0x28 = vpaddq (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xec,0xeb = vpaddsb %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xec,0x28 = vpaddsb (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xed,0xeb = vpaddsw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xed,0x28 = vpaddsw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xdc,0xeb = vpaddusb %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xdc,0x28 = vpaddusb (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xdd,0xeb = vpaddusw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xdd,0x28 = vpaddusw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xe4,0xeb = vpmulhuw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xe4,0x28 = vpmulhuw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xe5,0xeb = vpmulhw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xe5,0x28 = vpmulhw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xd5,0xeb = vpmullw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xd5,0x28 = vpmullw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xf4,0xeb = vpmuludq %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xf4,0x28 = vpmuludq (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xe0,0xeb = vpavgb %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xe0,0x28 = vpavgb (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xe3,0xeb = vpavgw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xe3,0x28 = vpavgw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xea,0xeb = vpminsw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xea,0x28 = vpminsw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xda,0xeb = vpminub %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xda,0x28 = vpminub (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xee,0xeb = vpmaxsw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xee,0x28 = vpmaxsw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xde,0xeb = vpmaxub %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xde,0x28 = vpmaxub (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xf6,0xeb = vpsadbw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xf6,0x28 = vpsadbw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xf1,0xeb = vpsllw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xf1,0x28 = vpsllw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xf2,0xeb = vpslld %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xf2,0x28 = vpslld (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xf3,0xeb = vpsllq %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xf3,0x28 = vpsllq (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xe1,0xeb = vpsraw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xe1,0x28 = vpsraw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xe2,0xeb = vpsrad %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xe2,0x28 = vpsrad (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xd1,0xeb = vpsrlw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xd1,0x28 = vpsrlw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xd2,0xeb = vpsrld %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xd2,0x28 = vpsrld (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xd3,0xeb = vpsrlq %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xd3,0x28 = vpsrlq (%rax), %xmm12, %xmm13 +0xc4,0xc1,0x11,0x72,0xf4,0x0a = vpslld $10, %xmm12, %xmm13 +0xc4,0xc1,0x11,0x73,0xfc,0x0a = vpslldq $10, %xmm12, %xmm13 +0xc4,0xc1,0x11,0x73,0xf4,0x0a = vpsllq $10, %xmm12, %xmm13 +0xc4,0xc1,0x11,0x71,0xf4,0x0a = vpsllw $10, %xmm12, %xmm13 +0xc4,0xc1,0x11,0x72,0xe4,0x0a = vpsrad $10, %xmm12, %xmm13 +0xc4,0xc1,0x11,0x71,0xe4,0x0a = vpsraw $10, %xmm12, %xmm13 +0xc4,0xc1,0x11,0x72,0xd4,0x0a = vpsrld $10, %xmm12, %xmm13 +0xc4,0xc1,0x11,0x73,0xdc,0x0a = vpsrldq $10, %xmm12, %xmm13 +0xc4,0xc1,0x11,0x73,0xd4,0x0a = vpsrlq $10, %xmm12, %xmm13 +0xc4,0xc1,0x11,0x71,0xd4,0x0a = vpsrlw $10, %xmm12, %xmm13 +0xc4,0xc1,0x11,0x72,0xf4,0x0a = vpslld $10, %xmm12, %xmm13 +0xc4,0x41,0x19,0xdb,0xeb = vpand %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xdb,0x28 = vpand (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xeb,0xeb = vpor %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xeb,0x28 = vpor (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xef,0xeb = vpxor %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xef,0x28 = vpxor (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0xdf,0xeb = vpandn %xmm11, %xmm12, %xmm13 +0xc5,0x19,0xdf,0x28 = vpandn (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x74,0xeb = vpcmpeqb %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x74,0x28 = vpcmpeqb (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x75,0xeb = vpcmpeqw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x75,0x28 = vpcmpeqw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x76,0xeb = vpcmpeqd %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x76,0x28 = vpcmpeqd (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x64,0xeb = vpcmpgtb %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x64,0x28 = vpcmpgtb (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x65,0xeb = vpcmpgtw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x65,0x28 = vpcmpgtw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x66,0xeb = vpcmpgtd %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x66,0x28 = vpcmpgtd (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x63,0xeb = vpacksswb %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x63,0x28 = vpacksswb (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x6b,0xeb = vpackssdw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x6b,0x28 = vpackssdw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x67,0xeb = vpackuswb %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x67,0x28 = vpackuswb (%rax), %xmm12, %xmm13 +0xc4,0x41,0x79,0x70,0xec,0x04 = vpshufd $4, %xmm12, %xmm13 +0xc5,0x79,0x70,0x28,0x04 = vpshufd $4, (%rax), %xmm13 +0xc4,0x41,0x7a,0x70,0xec,0x04 = vpshufhw $4, %xmm12, %xmm13 +0xc5,0x7a,0x70,0x28,0x04 = vpshufhw $4, (%rax), %xmm13 +0xc4,0x41,0x7b,0x70,0xec,0x04 = vpshuflw $4, %xmm12, %xmm13 +0xc5,0x7b,0x70,0x28,0x04 = vpshuflw $4, (%rax), %xmm13 +0xc4,0x41,0x19,0x60,0xeb = vpunpcklbw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x60,0x28 = vpunpcklbw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x61,0xeb = vpunpcklwd %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x61,0x28 = vpunpcklwd (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x62,0xeb = vpunpckldq %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x62,0x28 = vpunpckldq (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x6c,0xeb = vpunpcklqdq %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x6c,0x28 = vpunpcklqdq (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x68,0xeb = vpunpckhbw %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x68,0x28 = vpunpckhbw (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x69,0xeb = vpunpckhwd %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x69,0x28 = vpunpckhwd (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x6a,0xeb = vpunpckhdq %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x6a,0x28 = vpunpckhdq (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x6d,0xeb = vpunpckhqdq %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x6d,0x28 = vpunpckhqdq (%rax), %xmm12, %xmm13 +0xc5,0x19,0xc4,0xe8,0x07 = vpinsrw $7, %eax, %xmm12, %xmm13 +0xc5,0x19,0xc4,0x28,0x07 = vpinsrw $7, (%rax), %xmm12, %xmm13 +0xc4,0xc1,0x79,0xc5,0xc4,0x07 = vpextrw $7, %xmm12, %eax +0xc4,0xc1,0x79,0xd7,0xc4 = vpmovmskb %xmm12, %eax +0xc4,0x41,0x79,0xf7,0xfe = vmaskmovdqu %xmm14, %xmm15 +0xc5,0x79,0x6e,0xf0 = vmovd %eax, %xmm14 +0xc5,0x79,0x6e,0x30 = vmovd (%rax), %xmm14 +0xc5,0x79,0x7e,0x30 = vmovd %xmm14, (%rax) +0xc4,0x61,0xf9,0x6e,0xf0 = vmovq %rax, %xmm14 +0xc4,0xe1,0xf9,0x7e,0xc0 = vmovq %xmm0, %rax +0xc5,0x79,0xd6,0x30 = vmovq %xmm14, (%rax) +0xc4,0x41,0x7a,0x7e,0xe6 = vmovq %xmm14, %xmm12 +0xc5,0x7a,0x7e,0x30 = vmovq (%rax), %xmm14 +0xc4,0x61,0xf9,0x6e,0xf0 = vmovq %rax, %xmm14 +0xc4,0x61,0xf9,0x7e,0xf0 = vmovq %xmm14, %rax +0xc4,0x41,0x7b,0xe6,0xe3 = vcvtpd2dq %xmm11, %xmm12 +0xc4,0x41,0x7a,0xe6,0xe3 = vcvtdq2pd %xmm11, %xmm12 +0xc5,0x7a,0xe6,0x20 = vcvtdq2pd (%rax), %xmm12 +0xc4,0x41,0x7a,0x16,0xe3 = vmovshdup %xmm11, %xmm12 +0xc5,0x7a,0x16,0x20 = vmovshdup (%rax), %xmm12 +0xc4,0x41,0x7a,0x12,0xe3 = vmovsldup %xmm11, %xmm12 +0xc5,0x7a,0x12,0x20 = vmovsldup (%rax), %xmm12 +0xc4,0x41,0x7b,0x12,0xe3 = vmovddup %xmm11, %xmm12 +0xc5,0x7b,0x12,0x20 = vmovddup (%rax), %xmm12 +0xc4,0x41,0x1b,0xd0,0xeb = vaddsubps %xmm11, %xmm12, %xmm13 +0xc5,0x23,0xd0,0x20 = vaddsubps (%rax), %xmm11, %xmm12 +0xc4,0x41,0x19,0xd0,0xeb = vaddsubpd %xmm11, %xmm12, %xmm13 +0xc5,0x21,0xd0,0x20 = vaddsubpd (%rax), %xmm11, %xmm12 +0xc4,0x41,0x1b,0x7c,0xeb = vhaddps %xmm11, %xmm12, %xmm13 +0xc5,0x1b,0x7c,0x28 = vhaddps (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x7c,0xeb = vhaddpd %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x7c,0x28 = vhaddpd (%rax), %xmm12, %xmm13 +0xc4,0x41,0x1b,0x7d,0xeb = vhsubps %xmm11, %xmm12, %xmm13 +0xc5,0x1b,0x7d,0x28 = vhsubps (%rax), %xmm12, %xmm13 +0xc4,0x41,0x19,0x7d,0xeb = vhsubpd %xmm11, %xmm12, %xmm13 +0xc5,0x19,0x7d,0x28 = vhsubpd (%rax), %xmm12, %xmm13 +0xc4,0x42,0x79,0x1c,0xe3 = vpabsb %xmm11, %xmm12 +0xc4,0x62,0x79,0x1c,0x20 = vpabsb (%rax), %xmm12 +0xc4,0x42,0x79,0x1d,0xe3 = vpabsw %xmm11, %xmm12 +0xc4,0x62,0x79,0x1d,0x20 = vpabsw (%rax), %xmm12 +0xc4,0x42,0x79,0x1e,0xe3 = vpabsd %xmm11, %xmm12 +0xc4,0x62,0x79,0x1e,0x20 = vpabsd (%rax), %xmm12 +0xc4,0x42,0x19,0x01,0xeb = vphaddw %xmm11, %xmm12, %xmm13 +0xc4,0x62,0x19,0x01,0x28 = vphaddw (%rax), %xmm12, %xmm13 +0xc4,0x42,0x19,0x02,0xeb = vphaddd %xmm11, %xmm12, %xmm13 +0xc4,0x62,0x19,0x02,0x28 = vphaddd (%rax), %xmm12, %xmm13 +0xc4,0x42,0x19,0x03,0xeb = vphaddsw %xmm11, %xmm12, %xmm13 +0xc4,0x62,0x19,0x03,0x28 = vphaddsw (%rax), %xmm12, %xmm13 +0xc4,0x42,0x19,0x05,0xeb = vphsubw %xmm11, %xmm12, %xmm13 +0xc4,0x62,0x19,0x05,0x28 = vphsubw (%rax), %xmm12, %xmm13 +0xc4,0x42,0x19,0x06,0xeb = vphsubd %xmm11, %xmm12, %xmm13 +0xc4,0x62,0x19,0x06,0x28 = vphsubd (%rax), %xmm12, %xmm13 +0xc4,0x42,0x19,0x07,0xeb = vphsubsw %xmm11, %xmm12, %xmm13 +0xc4,0x62,0x19,0x07,0x28 = vphsubsw (%rax), %xmm12, %xmm13 +0xc4,0x42,0x19,0x04,0xeb = vpmaddubsw %xmm11, %xmm12, %xmm13 +0xc4,0x62,0x19,0x04,0x28 = vpmaddubsw (%rax), %xmm12, %xmm13 +0xc4,0x42,0x19,0x00,0xeb = vpshufb %xmm11, %xmm12, %xmm13 +0xc4,0x62,0x19,0x00,0x28 = vpshufb (%rax), %xmm12, %xmm13 +0xc4,0x42,0x19,0x08,0xeb = vpsignb %xmm11, %xmm12, %xmm13 +0xc4,0x62,0x19,0x08,0x28 = vpsignb (%rax), %xmm12, %xmm13 +0xc4,0x42,0x19,0x09,0xeb = vpsignw %xmm11, %xmm12, %xmm13 +0xc4,0x62,0x19,0x09,0x28 = vpsignw (%rax), %xmm12, %xmm13 +0xc4,0x42,0x19,0x0a,0xeb = vpsignd %xmm11, %xmm12, %xmm13 +0xc4,0x62,0x19,0x0a,0x28 = vpsignd (%rax), %xmm12, %xmm13 +0xc4,0x42,0x19,0x0b,0xeb = vpmulhrsw %xmm11, %xmm12, %xmm13 +0xc4,0x62,0x19,0x0b,0x28 = vpmulhrsw (%rax), %xmm12, %xmm13 +0xc4,0x43,0x19,0x0f,0xeb,0x07 = vpalignr $7, %xmm11, %xmm12, %xmm13 +0xc4,0x63,0x19,0x0f,0x28,0x07 = vpalignr $7, (%rax), %xmm12, %xmm13 +0xc4,0x43,0x19,0x0b,0xeb,0x07 = vroundsd $7, %xmm11, %xmm12, %xmm13 +0xc4,0x63,0x19,0x0b,0x28,0x07 = vroundsd $7, (%rax), %xmm12, %xmm13 +0xc4,0x43,0x19,0x0a,0xeb,0x07 = vroundss $7, %xmm11, %xmm12, %xmm13 +0xc4,0x63,0x19,0x0a,0x28,0x07 = vroundss $7, (%rax), %xmm12, %xmm13 +0xc4,0x43,0x79,0x09,0xec,0x07 = vroundpd $7, %xmm12, %xmm13 +0xc4,0x63,0x79,0x09,0x28,0x07 = vroundpd $7, (%rax), %xmm13 +0xc4,0x43,0x79,0x08,0xec,0x07 = vroundps $7, %xmm12, %xmm13 +0xc4,0x63,0x79,0x08,0x28,0x07 = vroundps $7, (%rax), %xmm13 +0xc4,0x42,0x79,0x41,0xec = vphminposuw %xmm12, %xmm13 +0xc4,0x62,0x79,0x41,0x20 = vphminposuw (%rax), %xmm12 +0xc4,0x42,0x11,0x2b,0xdc = vpackusdw %xmm12, %xmm13, %xmm11 +0xc4,0x62,0x19,0x2b,0x28 = vpackusdw (%rax), %xmm12, %xmm13 +0xc4,0x42,0x11,0x29,0xdc = vpcmpeqq %xmm12, %xmm13, %xmm11 +0xc4,0x62,0x19,0x29,0x28 = vpcmpeqq (%rax), %xmm12, %xmm13 +0xc4,0x42,0x11,0x38,0xdc = vpminsb %xmm12, %xmm13, %xmm11 +0xc4,0x62,0x19,0x38,0x28 = vpminsb (%rax), %xmm12, %xmm13 +0xc4,0x42,0x11,0x39,0xdc = vpminsd %xmm12, %xmm13, %xmm11 +0xc4,0x62,0x19,0x39,0x28 = vpminsd (%rax), %xmm12, %xmm13 +0xc4,0x42,0x11,0x3b,0xdc = vpminud %xmm12, %xmm13, %xmm11 +0xc4,0x62,0x19,0x3b,0x28 = vpminud (%rax), %xmm12, %xmm13 +0xc4,0x42,0x11,0x3a,0xdc = vpminuw %xmm12, %xmm13, %xmm11 +0xc4,0x62,0x19,0x3a,0x28 = vpminuw (%rax), %xmm12, %xmm13 +0xc4,0x42,0x11,0x3c,0xdc = vpmaxsb %xmm12, %xmm13, %xmm11 +0xc4,0x62,0x19,0x3c,0x28 = vpmaxsb (%rax), %xmm12, %xmm13 +0xc4,0x42,0x11,0x3d,0xdc = vpmaxsd %xmm12, %xmm13, %xmm11 +0xc4,0x62,0x19,0x3d,0x28 = vpmaxsd (%rax), %xmm12, %xmm13 +0xc4,0x42,0x11,0x3f,0xdc = vpmaxud %xmm12, %xmm13, %xmm11 +0xc4,0x62,0x19,0x3f,0x28 = vpmaxud (%rax), %xmm12, %xmm13 +0xc4,0x42,0x11,0x3e,0xdc = vpmaxuw %xmm12, %xmm13, %xmm11 +0xc4,0x62,0x19,0x3e,0x28 = vpmaxuw (%rax), %xmm12, %xmm13 +0xc4,0x42,0x11,0x28,0xdc = vpmuldq %xmm12, %xmm13, %xmm11 +0xc4,0x62,0x19,0x28,0x28 = vpmuldq (%rax), %xmm12, %xmm13 +0xc4,0x42,0x51,0x40,0xdc = vpmulld %xmm12, %xmm5, %xmm11 +0xc4,0x62,0x51,0x40,0x28 = vpmulld (%rax), %xmm5, %xmm13 +0xc4,0x43,0x51,0x0c,0xdc,0x03 = vblendps $3, %xmm12, %xmm5, %xmm11 +0xc4,0x63,0x51,0x0c,0x18,0x03 = vblendps $3, (%rax), %xmm5, %xmm11 +0xc4,0x43,0x51,0x0d,0xdc,0x03 = vblendpd $3, %xmm12, %xmm5, %xmm11 +0xc4,0x63,0x51,0x0d,0x18,0x03 = vblendpd $3, (%rax), %xmm5, %xmm11 +0xc4,0x43,0x51,0x0e,0xdc,0x03 = vpblendw $3, %xmm12, %xmm5, %xmm11 +0xc4,0x63,0x51,0x0e,0x18,0x03 = vpblendw $3, (%rax), %xmm5, %xmm11 +0xc4,0x43,0x51,0x42,0xdc,0x03 = vmpsadbw $3, %xmm12, %xmm5, %xmm11 +0xc4,0x63,0x51,0x42,0x18,0x03 = vmpsadbw $3, (%rax), %xmm5, %xmm11 +0xc4,0x43,0x51,0x40,0xdc,0x03 = vdpps $3, %xmm12, %xmm5, %xmm11 +0xc4,0x63,0x51,0x40,0x18,0x03 = vdpps $3, (%rax), %xmm5, %xmm11 +0xc4,0x43,0x51,0x41,0xdc,0x03 = vdppd $3, %xmm12, %xmm5, %xmm11 +0xc4,0x63,0x51,0x41,0x18,0x03 = vdppd $3, (%rax), %xmm5, %xmm11 +0xc4,0x63,0x21,0x4b,0xed,0xc0 = vblendvpd %xmm12, %xmm5, %xmm11, %xmm13 +0xc4,0x63,0x21,0x4b,0x28,0xc0 = vblendvpd %xmm12, (%rax), %xmm11, %xmm13 +0xc4,0x63,0x21,0x4a,0xed,0xc0 = vblendvps %xmm12, %xmm5, %xmm11, %xmm13 +0xc4,0x63,0x21,0x4a,0x28,0xc0 = vblendvps %xmm12, (%rax), %xmm11, %xmm13 +0xc4,0x63,0x21,0x4c,0xed,0xc0 = vpblendvb %xmm12, %xmm5, %xmm11, %xmm13 +0xc4,0x63,0x21,0x4c,0x28,0xc0 = vpblendvb %xmm12, (%rax), %xmm11, %xmm13 +0xc4,0x42,0x79,0x20,0xd4 = vpmovsxbw %xmm12, %xmm10 +0xc4,0x62,0x79,0x20,0x20 = vpmovsxbw (%rax), %xmm12 +0xc4,0x42,0x79,0x23,0xd4 = vpmovsxwd %xmm12, %xmm10 +0xc4,0x62,0x79,0x23,0x20 = vpmovsxwd (%rax), %xmm12 +0xc4,0x42,0x79,0x25,0xd4 = vpmovsxdq %xmm12, %xmm10 +0xc4,0x62,0x79,0x25,0x20 = vpmovsxdq (%rax), %xmm12 +0xc4,0x42,0x79,0x30,0xd4 = vpmovzxbw %xmm12, %xmm10 +0xc4,0x62,0x79,0x30,0x20 = vpmovzxbw (%rax), %xmm12 +0xc4,0x42,0x79,0x33,0xd4 = vpmovzxwd %xmm12, %xmm10 +0xc4,0x62,0x79,0x33,0x20 = vpmovzxwd (%rax), %xmm12 +0xc4,0x42,0x79,0x35,0xd4 = vpmovzxdq %xmm12, %xmm10 +0xc4,0x62,0x79,0x35,0x20 = vpmovzxdq (%rax), %xmm12 +0xc4,0x42,0x79,0x22,0xd4 = vpmovsxbq %xmm12, %xmm10 +0xc4,0x62,0x79,0x22,0x20 = vpmovsxbq (%rax), %xmm12 +0xc4,0x42,0x79,0x32,0xd4 = vpmovzxbq %xmm12, %xmm10 +0xc4,0x62,0x79,0x32,0x20 = vpmovzxbq (%rax), %xmm12 +0xc4,0x42,0x79,0x21,0xd4 = vpmovsxbd %xmm12, %xmm10 +0xc4,0x62,0x79,0x21,0x20 = vpmovsxbd (%rax), %xmm12 +0xc4,0x42,0x79,0x24,0xd4 = vpmovsxwq %xmm12, %xmm10 +0xc4,0x62,0x79,0x24,0x20 = vpmovsxwq (%rax), %xmm12 +0xc4,0x42,0x79,0x31,0xd4 = vpmovzxbd %xmm12, %xmm10 +0xc4,0x62,0x79,0x31,0x20 = vpmovzxbd (%rax), %xmm12 +0xc4,0x42,0x79,0x34,0xd4 = vpmovzxwq %xmm12, %xmm10 +0xc4,0x62,0x79,0x34,0x20 = vpmovzxwq (%rax), %xmm12 +0xc4,0xc1,0x79,0xc5,0xc4,0x07 = vpextrw $7, %xmm12, %eax +0xc4,0x63,0x79,0x15,0x20,0x07 = vpextrw $7, %xmm12, (%rax) +0xc4,0x63,0x79,0x16,0xe0,0x07 = vpextrd $7, %xmm12, %eax +0xc4,0x63,0x79,0x16,0x20,0x07 = vpextrd $7, %xmm12, (%rax) +0xc4,0x63,0x79,0x14,0xe0,0x07 = vpextrb $7, %xmm12, %eax +0xc4,0x63,0x79,0x14,0x20,0x07 = vpextrb $7, %xmm12, (%rax) +0xc4,0x63,0xf9,0x16,0xe1,0x07 = vpextrq $7, %xmm12, %rcx +0xc4,0x63,0xf9,0x16,0x21,0x07 = vpextrq $7, %xmm12, (%rcx) +0xc4,0x63,0x79,0x17,0x20,0x07 = vextractps $7, %xmm12, (%rax) +0xc4,0x63,0x79,0x17,0xe0,0x07 = vextractps $7, %xmm12, %eax +0xc5,0x19,0xc4,0xd0,0x07 = vpinsrw $7, %eax, %xmm12, %xmm10 +0xc5,0x19,0xc4,0x10,0x07 = vpinsrw $7, (%rax), %xmm12, %xmm10 +0xc4,0x63,0x19,0x20,0xd0,0x07 = vpinsrb $7, %eax, %xmm12, %xmm10 +0xc4,0x63,0x19,0x20,0x10,0x07 = vpinsrb $7, (%rax), %xmm12, %xmm10 +0xc4,0x63,0x19,0x22,0xd0,0x07 = vpinsrd $7, %eax, %xmm12, %xmm10 +0xc4,0x63,0x19,0x22,0x10,0x07 = vpinsrd $7, (%rax), %xmm12, %xmm10 +0xc4,0x63,0x99,0x22,0xd0,0x07 = vpinsrq $7, %rax, %xmm12, %xmm10 +0xc4,0x63,0x99,0x22,0x10,0x07 = vpinsrq $7, (%rax), %xmm12, %xmm10 +0xc4,0x43,0x29,0x21,0xdc,0x07 = vinsertps $7, %xmm12, %xmm10, %xmm11 +0xc4,0x63,0x29,0x21,0x18,0x07 = vinsertps $7, (%rax), %xmm10, %xmm11 +0xc4,0x42,0x79,0x17,0xd4 = vptest %xmm12, %xmm10 +0xc4,0x62,0x79,0x17,0x20 = vptest (%rax), %xmm12 +0xc4,0x62,0x79,0x2a,0x20 = vmovntdqa (%rax), %xmm12 +0xc4,0x42,0x29,0x37,0xdc = vpcmpgtq %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0x37,0x28 = vpcmpgtq (%rax), %xmm10, %xmm13 +0xc4,0x43,0x79,0x62,0xd4,0x07 = vpcmpistrm $7, %xmm12, %xmm10 +0xc4,0x63,0x79,0x62,0x10,0x07 = vpcmpistrm $7, (%rax), %xmm10 +0xc4,0x43,0x79,0x60,0xd4,0x07 = vpcmpestrm $7, %xmm12, %xmm10 +0xc4,0x63,0x79,0x60,0x10,0x07 = vpcmpestrm $7, (%rax), %xmm10 +0xc4,0x43,0x79,0x63,0xd4,0x07 = vpcmpistri $7, %xmm12, %xmm10 +0xc4,0x63,0x79,0x63,0x10,0x07 = vpcmpistri $7, (%rax), %xmm10 +0xc4,0x43,0x79,0x61,0xd4,0x07 = vpcmpestri $7, %xmm12, %xmm10 +0xc4,0x63,0x79,0x61,0x10,0x07 = vpcmpestri $7, (%rax), %xmm10 +0xc4,0x42,0x79,0xdb,0xd4 = vaesimc %xmm12, %xmm10 +0xc4,0x62,0x79,0xdb,0x20 = vaesimc (%rax), %xmm12 +0xc4,0x42,0x29,0xdc,0xdc = vaesenc %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xdc,0x28 = vaesenc (%rax), %xmm10, %xmm13 +0xc4,0x42,0x29,0xdd,0xdc = vaesenclast %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xdd,0x28 = vaesenclast (%rax), %xmm10, %xmm13 +0xc4,0x42,0x29,0xde,0xdc = vaesdec %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xde,0x28 = vaesdec (%rax), %xmm10, %xmm13 +0xc4,0x42,0x29,0xdf,0xdc = vaesdeclast %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xdf,0x28 = vaesdeclast (%rax), %xmm10, %xmm13 +0xc4,0x43,0x79,0xdf,0xd4,0x07 = vaeskeygenassist $7, %xmm12, %xmm10 +0xc4,0x63,0x79,0xdf,0x10,0x07 = vaeskeygenassist $7, (%rax), %xmm10 +0xc4,0x41,0x18,0xc2,0xeb,0x08 = vcmpeq_uqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x09 = vcmpngeps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x0a = vcmpngtps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x0b = vcmpfalseps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x0c = vcmpneq_oqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x0d = vcmpgeps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x0e = vcmpgtps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x0f = vcmptrueps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x10 = vcmpeq_osps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x11 = vcmplt_oqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x12 = vcmple_oqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x13 = vcmpunord_sps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x14 = vcmpneq_usps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x15 = vcmpnlt_uqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x16 = vcmpnle_uqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x17 = vcmpord_sps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x18 = vcmpeq_usps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x19 = vcmpnge_uqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x1a = vcmpngt_uqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x1b = vcmpfalse_osps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x1c = vcmpneq_osps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x1d = vcmpge_oqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x1e = vcmpgt_oqps %xmm11, %xmm12, %xmm13 +0xc4,0x41,0x18,0xc2,0xeb,0x1f = vcmptrue_usps %xmm11, %xmm12, %xmm13 +0xc5,0x7c,0x28,0x20 = vmovaps (%rax), %ymm12 +0xc4,0x41,0x7c,0x28,0xe3 = vmovaps %ymm11, %ymm12 +0xc5,0x7c,0x29,0x18 = vmovaps %ymm11, (%rax) +0xc5,0x7d,0x28,0x20 = vmovapd (%rax), %ymm12 +0xc4,0x41,0x7d,0x28,0xe3 = vmovapd %ymm11, %ymm12 +0xc5,0x7d,0x29,0x18 = vmovapd %ymm11, (%rax) +0xc5,0x7c,0x10,0x20 = vmovups (%rax), %ymm12 +0xc4,0x41,0x7c,0x10,0xe3 = vmovups %ymm11, %ymm12 +0xc5,0x7c,0x11,0x18 = vmovups %ymm11, (%rax) +0xc5,0x7d,0x10,0x20 = vmovupd (%rax), %ymm12 +0xc4,0x41,0x7d,0x10,0xe3 = vmovupd %ymm11, %ymm12 +0xc5,0x7d,0x11,0x18 = vmovupd %ymm11, (%rax) +0xc4,0xc1,0x1c,0x15,0xe3 = vunpckhps %ymm11, %ymm12, %ymm4 +0xc4,0xc1,0x1d,0x15,0xe3 = vunpckhpd %ymm11, %ymm12, %ymm4 +0xc4,0xc1,0x1c,0x14,0xe3 = vunpcklps %ymm11, %ymm12, %ymm4 +0xc4,0xc1,0x1d,0x14,0xe3 = vunpcklpd %ymm11, %ymm12, %ymm4 +0xc5,0x1c,0x15,0x54,0xcb,0xfc = vunpckhps -4(%rbx, %rcx, 8), %ymm12, %ymm10 +0xc5,0x1d,0x15,0x54,0xcb,0xfc = vunpckhpd -4(%rbx, %rcx, 8), %ymm12, %ymm10 +0xc5,0x1c,0x14,0x54,0xcb,0xfc = vunpcklps -4(%rbx, %rcx, 8), %ymm12, %ymm10 +0xc5,0x1d,0x14,0x54,0xcb,0xfc = vunpcklpd -4(%rbx, %rcx, 8), %ymm12, %ymm10 +0xc5,0x7d,0xe7,0x18 = vmovntdq %ymm11, (%rax) +0xc5,0x7d,0x2b,0x18 = vmovntpd %ymm11, (%rax) +0xc5,0x7c,0x2b,0x18 = vmovntps %ymm11, (%rax) +0xc4,0xc1,0x78,0x50,0xc4 = vmovmskps %xmm12, %eax +0xc4,0xc1,0x79,0x50,0xc4 = vmovmskpd %xmm12, %eax +0xc4,0xc1,0x5c,0x5f,0xf4 = vmaxps %ymm12, %ymm4, %ymm6 +0xc4,0xc1,0x5d,0x5f,0xf4 = vmaxpd %ymm12, %ymm4, %ymm6 +0xc4,0xc1,0x5c,0x5d,0xf4 = vminps %ymm12, %ymm4, %ymm6 +0xc4,0xc1,0x5d,0x5d,0xf4 = vminpd %ymm12, %ymm4, %ymm6 +0xc4,0xc1,0x5c,0x5c,0xf4 = vsubps %ymm12, %ymm4, %ymm6 +0xc4,0xc1,0x5d,0x5c,0xf4 = vsubpd %ymm12, %ymm4, %ymm6 +0xc4,0xc1,0x5c,0x5e,0xf4 = vdivps %ymm12, %ymm4, %ymm6 +0xc4,0xc1,0x5d,0x5e,0xf4 = vdivpd %ymm12, %ymm4, %ymm6 +0xc4,0xc1,0x5c,0x58,0xf4 = vaddps %ymm12, %ymm4, %ymm6 +0xc4,0xc1,0x5d,0x58,0xf4 = vaddpd %ymm12, %ymm4, %ymm6 +0xc4,0xc1,0x5c,0x59,0xf4 = vmulps %ymm12, %ymm4, %ymm6 +0xc4,0xc1,0x5d,0x59,0xf4 = vmulpd %ymm12, %ymm4, %ymm6 +0xc5,0xdc,0x5f,0x30 = vmaxps (%rax), %ymm4, %ymm6 +0xc5,0xdd,0x5f,0x30 = vmaxpd (%rax), %ymm4, %ymm6 +0xc5,0xdc,0x5d,0x30 = vminps (%rax), %ymm4, %ymm6 +0xc5,0xdd,0x5d,0x30 = vminpd (%rax), %ymm4, %ymm6 +0xc5,0xdc,0x5c,0x30 = vsubps (%rax), %ymm4, %ymm6 +0xc5,0xdd,0x5c,0x30 = vsubpd (%rax), %ymm4, %ymm6 +0xc5,0xdc,0x5e,0x30 = vdivps (%rax), %ymm4, %ymm6 +0xc5,0xdd,0x5e,0x30 = vdivpd (%rax), %ymm4, %ymm6 +0xc5,0xdc,0x58,0x30 = vaddps (%rax), %ymm4, %ymm6 +0xc5,0xdd,0x58,0x30 = vaddpd (%rax), %ymm4, %ymm6 +0xc5,0xdc,0x59,0x30 = vmulps (%rax), %ymm4, %ymm6 +0xc5,0xdd,0x59,0x30 = vmulpd (%rax), %ymm4, %ymm6 +0xc4,0x41,0x7d,0x51,0xe3 = vsqrtpd %ymm11, %ymm12 +0xc5,0x7d,0x51,0x20 = vsqrtpd (%rax), %ymm12 +0xc4,0x41,0x7c,0x51,0xe3 = vsqrtps %ymm11, %ymm12 +0xc5,0x7c,0x51,0x20 = vsqrtps (%rax), %ymm12 +0xc4,0x41,0x7c,0x52,0xe3 = vrsqrtps %ymm11, %ymm12 +0xc5,0x7c,0x52,0x20 = vrsqrtps (%rax), %ymm12 +0xc4,0x41,0x7c,0x53,0xe3 = vrcpps %ymm11, %ymm12 +0xc5,0x7c,0x53,0x20 = vrcpps (%rax), %ymm12 +0xc4,0x41,0x0c,0x54,0xdc = vandps %ymm12, %ymm14, %ymm11 +0xc4,0x41,0x0d,0x54,0xdc = vandpd %ymm12, %ymm14, %ymm11 +0xc5,0x1c,0x54,0x54,0xcb,0xfc = vandps -4(%rbx, %rcx, 8), %ymm12, %ymm10 +0xc5,0x1d,0x54,0x54,0xcb,0xfc = vandpd -4(%rbx, %rcx, 8), %ymm12, %ymm10 +0xc4,0x41,0x0c,0x56,0xdc = vorps %ymm12, %ymm14, %ymm11 +0xc4,0x41,0x0d,0x56,0xdc = vorpd %ymm12, %ymm14, %ymm11 +0xc5,0x1c,0x56,0x54,0xcb,0xfc = vorps -4(%rbx, %rcx, 8), %ymm12, %ymm10 +0xc5,0x1d,0x56,0x54,0xcb,0xfc = vorpd -4(%rbx, %rcx, 8), %ymm12, %ymm10 +0xc4,0x41,0x0c,0x57,0xdc = vxorps %ymm12, %ymm14, %ymm11 +0xc4,0x41,0x0d,0x57,0xdc = vxorpd %ymm12, %ymm14, %ymm11 +0xc5,0x1c,0x57,0x54,0xcb,0xfc = vxorps -4(%rbx, %rcx, 8), %ymm12, %ymm10 +0xc5,0x1d,0x57,0x54,0xcb,0xfc = vxorpd -4(%rbx, %rcx, 8), %ymm12, %ymm10 +0xc4,0x41,0x0c,0x55,0xdc = vandnps %ymm12, %ymm14, %ymm11 +0xc4,0x41,0x0d,0x55,0xdc = vandnpd %ymm12, %ymm14, %ymm11 +0xc5,0x1c,0x55,0x54,0xcb,0xfc = vandnps -4(%rbx, %rcx, 8), %ymm12, %ymm10 +0xc5,0x1d,0x55,0x54,0xcb,0xfc = vandnpd -4(%rbx, %rcx, 8), %ymm12, %ymm10 +0xc4,0x41,0x7c,0x5a,0xe5 = vcvtps2pd %xmm13, %ymm12 +0xc5,0x7c,0x5a,0x20 = vcvtps2pd (%rax), %ymm12 +0xc4,0x41,0x7e,0xe6,0xe5 = vcvtdq2pd %xmm13, %ymm12 +0xc5,0x7e,0xe6,0x20 = vcvtdq2pd (%rax), %ymm12 +0xc4,0x41,0x7c,0x5b,0xd4 = vcvtdq2ps %ymm12, %ymm10 +0xc5,0x7c,0x5b,0x20 = vcvtdq2ps (%rax), %ymm12 +0xc4,0x41,0x7d,0x5b,0xd4 = vcvtps2dq %ymm12, %ymm10 +0xc5,0x7d,0x5b,0x10 = vcvtps2dq (%rax), %ymm10 +0xc4,0x41,0x7e,0x5b,0xd4 = vcvttps2dq %ymm12, %ymm10 +0xc5,0x7e,0x5b,0x10 = vcvttps2dq (%rax), %ymm10 +0xc4,0x41,0x79,0xe6,0xd3 = vcvttpd2dq %xmm11, %xmm10 +0xc4,0x41,0x7d,0xe6,0xd4 = vcvttpd2dq %ymm12, %xmm10 +0xc4,0x41,0x79,0xe6,0xd3 = vcvttpd2dq %xmm11, %xmm10 +0xc5,0x79,0xe6,0x18 = vcvttpd2dqx (%rax), %xmm11 +0xc4,0x41,0x7d,0xe6,0xdc = vcvttpd2dq %ymm12, %xmm11 +0xc5,0x7d,0xe6,0x18 = vcvttpd2dqy (%rax), %xmm11 +0xc4,0x41,0x7d,0x5a,0xd4 = vcvtpd2ps %ymm12, %xmm10 +0xc4,0x41,0x79,0x5a,0xd3 = vcvtpd2ps %xmm11, %xmm10 +0xc5,0x79,0x5a,0x18 = vcvtpd2psx (%rax), %xmm11 +0xc4,0x41,0x7d,0x5a,0xdc = vcvtpd2ps %ymm12, %xmm11 +0xc5,0x7d,0x5a,0x18 = vcvtpd2psy (%rax), %xmm11 +0xc4,0x41,0x7f,0xe6,0xd4 = vcvtpd2dq %ymm12, %xmm10 +0xc4,0x41,0x7f,0xe6,0xdc = vcvtpd2dq %ymm12, %xmm11 +0xc5,0x7f,0xe6,0x18 = vcvtpd2dqy (%rax), %xmm11 +0xc4,0x41,0x7b,0xe6,0xd3 = vcvtpd2dq %xmm11, %xmm10 +0xc5,0x7b,0xe6,0x18 = vcvtpd2dqx (%rax), %xmm11 +0xc4,0x41,0x1c,0xc2,0xeb,0x00 = vcmpeqps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x02 = vcmpleps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x01 = vcmpltps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x04 = vcmpneqps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x06 = vcmpnleps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x05 = vcmpnltps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x07 = vcmpordps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x03 = vcmpunordps %ymm11, %ymm12, %ymm13 +0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x00 = vcmpeqps -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x02 = vcmpleps -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x01 = vcmpltps -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x04 = vcmpneqps -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x06 = vcmpnleps -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x05 = vcmpnltps -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc5,0x4c,0xc2,0x64,0xcb,0xfc,0x07 = vcmpordps -4(%rbx, %rcx, 8), %ymm6, %ymm12 +0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x03 = vcmpunordps -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc4,0x41,0x1d,0xc2,0xeb,0x00 = vcmpeqpd %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1d,0xc2,0xeb,0x02 = vcmplepd %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1d,0xc2,0xeb,0x01 = vcmpltpd %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1d,0xc2,0xeb,0x04 = vcmpneqpd %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1d,0xc2,0xeb,0x06 = vcmpnlepd %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1d,0xc2,0xeb,0x05 = vcmpnltpd %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1d,0xc2,0xeb,0x07 = vcmpordpd %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1d,0xc2,0xeb,0x03 = vcmpunordpd %ymm11, %ymm12, %ymm13 +0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x00 = vcmpeqpd -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x02 = vcmplepd -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x01 = vcmpltpd -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x04 = vcmpneqpd -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x06 = vcmpnlepd -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x05 = vcmpnltpd -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc5,0x4d,0xc2,0x64,0xcb,0xfc,0x07 = vcmpordpd -4(%rbx, %rcx, 8), %ymm6, %ymm12 +0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x03 = vcmpunordpd -4(%rbx, %rcx, 8), %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x08 = vcmpeq_uqps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x09 = vcmpngeps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x0a = vcmpngtps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x0b = vcmpfalseps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x0c = vcmpneq_oqps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x0d = vcmpgeps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x0e = vcmpgtps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x0f = vcmptrueps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x10 = vcmpeq_osps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x11 = vcmplt_oqps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x12 = vcmple_oqps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x13 = vcmpunord_sps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x14 = vcmpneq_usps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x15 = vcmpnlt_uqps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x16 = vcmpnle_uqps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x17 = vcmpord_sps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x18 = vcmpeq_usps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x19 = vcmpnge_uqps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x1a = vcmpngt_uqps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x1b = vcmpfalse_osps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x1c = vcmpneq_osps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x1d = vcmpge_oqps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x1e = vcmpgt_oqps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1c,0xc2,0xeb,0x1f = vcmptrue_usps %ymm11, %ymm12, %ymm13 +0xc4,0x41,0x1f,0xd0,0xeb = vaddsubps %ymm11, %ymm12, %ymm13 +0xc5,0x27,0xd0,0x20 = vaddsubps (%rax), %ymm11, %ymm12 +0xc4,0x41,0x1d,0xd0,0xeb = vaddsubpd %ymm11, %ymm12, %ymm13 +0xc5,0x25,0xd0,0x20 = vaddsubpd (%rax), %ymm11, %ymm12 +0xc4,0x41,0x1f,0x7c,0xeb = vhaddps %ymm11, %ymm12, %ymm13 +0xc5,0x1f,0x7c,0x28 = vhaddps (%rax), %ymm12, %ymm13 +0xc4,0x41,0x1d,0x7c,0xeb = vhaddpd %ymm11, %ymm12, %ymm13 +0xc5,0x1d,0x7c,0x28 = vhaddpd (%rax), %ymm12, %ymm13 +0xc4,0x41,0x1f,0x7d,0xeb = vhsubps %ymm11, %ymm12, %ymm13 +0xc5,0x1f,0x7d,0x28 = vhsubps (%rax), %ymm12, %ymm13 +0xc4,0x41,0x1d,0x7d,0xeb = vhsubpd %ymm11, %ymm12, %ymm13 +0xc5,0x1d,0x7d,0x28 = vhsubpd (%rax), %ymm12, %ymm13 +0xc4,0x43,0x2d,0x0c,0xdc,0x03 = vblendps $3, %ymm12, %ymm10, %ymm11 +0xc4,0x63,0x2d,0x0c,0x18,0x03 = vblendps $3, (%rax), %ymm10, %ymm11 +0xc4,0x43,0x2d,0x0d,0xdc,0x03 = vblendpd $3, %ymm12, %ymm10, %ymm11 +0xc4,0x63,0x2d,0x0d,0x18,0x03 = vblendpd $3, (%rax), %ymm10, %ymm11 +0xc4,0x43,0x2d,0x40,0xdc,0x03 = vdpps $3, %ymm12, %ymm10, %ymm11 +0xc4,0x63,0x2d,0x40,0x18,0x03 = vdpps $3, (%rax), %ymm10, %ymm11 +0xc4,0x62,0x7d,0x1a,0x20 = vbroadcastf128 (%rax), %ymm12 +0xc4,0x62,0x7d,0x19,0x20 = vbroadcastsd (%rax), %ymm12 +0xc4,0x62,0x79,0x18,0x20 = vbroadcastss (%rax), %xmm12 +0xc4,0x62,0x7d,0x18,0x20 = vbroadcastss (%rax), %ymm12 +0xc4,0x43,0x1d,0x18,0xd4,0x07 = vinsertf128 $7, %xmm12, %ymm12, %ymm10 +0xc4,0x63,0x1d,0x18,0x10,0x07 = vinsertf128 $7, (%rax), %ymm12, %ymm10 +0xc4,0x43,0x7d,0x19,0xe4,0x07 = vextractf128 $7, %ymm12, %xmm12 +0xc4,0x63,0x7d,0x19,0x20,0x07 = vextractf128 $7, %ymm12, (%rax) +0xc4,0x62,0x29,0x2f,0x20 = vmaskmovpd %xmm12, %xmm10, (%rax) +0xc4,0x62,0x2d,0x2f,0x20 = vmaskmovpd %ymm12, %ymm10, (%rax) +0xc4,0x62,0x19,0x2d,0x10 = vmaskmovpd (%rax), %xmm12, %xmm10 +0xc4,0x62,0x1d,0x2d,0x10 = vmaskmovpd (%rax), %ymm12, %ymm10 +0xc4,0x62,0x29,0x2e,0x20 = vmaskmovps %xmm12, %xmm10, (%rax) +0xc4,0x62,0x2d,0x2e,0x20 = vmaskmovps %ymm12, %ymm10, (%rax) +0xc4,0x62,0x19,0x2c,0x10 = vmaskmovps (%rax), %xmm12, %xmm10 +0xc4,0x62,0x1d,0x2c,0x10 = vmaskmovps (%rax), %ymm12, %ymm10 +0xc4,0x43,0x79,0x04,0xd3,0x07 = vpermilps $7, %xmm11, %xmm10 +0xc4,0x43,0x7d,0x04,0xda,0x07 = vpermilps $7, %ymm10, %ymm11 +0xc4,0x63,0x79,0x04,0x10,0x07 = vpermilps $7, (%rax), %xmm10 +0xc4,0x63,0x7d,0x04,0x10,0x07 = vpermilps $7, (%rax), %ymm10 +0xc4,0x42,0x29,0x0c,0xdb = vpermilps %xmm11, %xmm10, %xmm11 +0xc4,0x42,0x2d,0x0c,0xdb = vpermilps %ymm11, %ymm10, %ymm11 +0xc4,0x62,0x29,0x0c,0x28 = vpermilps (%rax), %xmm10, %xmm13 +0xc4,0x62,0x2d,0x0c,0x18 = vpermilps (%rax), %ymm10, %ymm11 +0xc4,0x43,0x79,0x05,0xd3,0x07 = vpermilpd $7, %xmm11, %xmm10 +0xc4,0x43,0x7d,0x05,0xda,0x07 = vpermilpd $7, %ymm10, %ymm11 +0xc4,0x63,0x79,0x05,0x10,0x07 = vpermilpd $7, (%rax), %xmm10 +0xc4,0x63,0x7d,0x05,0x10,0x07 = vpermilpd $7, (%rax), %ymm10 +0xc4,0x42,0x29,0x0d,0xdb = vpermilpd %xmm11, %xmm10, %xmm11 +0xc4,0x42,0x2d,0x0d,0xdb = vpermilpd %ymm11, %ymm10, %ymm11 +0xc4,0x62,0x29,0x0d,0x28 = vpermilpd (%rax), %xmm10, %xmm13 +0xc4,0x62,0x2d,0x0d,0x18 = vpermilpd (%rax), %ymm10, %ymm11 +0xc4,0x43,0x2d,0x06,0xdc,0x07 = vperm2f128 $7, %ymm12, %ymm10, %ymm11 +0xc4,0x63,0x2d,0x06,0x18,0x07 = vperm2f128 $7, (%rax), %ymm10, %ymm11 +0xc4,0x41,0x7b,0x2d,0xc0 = vcvtsd2si %xmm8, %r8d +0xc5,0xfb,0x2d,0x09 = vcvtsd2si (%rcx), %ecx +0xc4,0xe1,0xfa,0x2d,0xcc = vcvtss2si %xmm4, %rcx +0xc4,0x61,0xfa,0x2d,0x01 = vcvtss2si (%rcx), %r8 +0xc4,0x41,0x3b,0x2a,0xf8 = vcvtsi2sdl %r8d, %xmm8, %xmm15 +0xc5,0x3b,0x2a,0x7d,0x00 = vcvtsi2sdl (%rbp), %xmm8, %xmm15 +0xc4,0xe1,0xdb,0x2a,0xf1 = vcvtsi2sdq %rcx, %xmm4, %xmm6 +0xc4,0xe1,0xdb,0x2a,0x31 = vcvtsi2sdq (%rcx), %xmm4, %xmm6 +0xc4,0xe1,0xda,0x2a,0xf1 = vcvtsi2ssq %rcx, %xmm4, %xmm6 +0xc4,0xe1,0xda,0x2a,0x31 = vcvtsi2ssq (%rcx), %xmm4, %xmm6 +0xc4,0xe1,0xfb,0x2c,0xcc = vcvttsd2si %xmm4, %rcx +0xc4,0xe1,0xfb,0x2c,0x09 = vcvttsd2si (%rcx), %rcx +0xc4,0xe1,0xfa,0x2c,0xcc = vcvttss2si %xmm4, %rcx +0xc4,0xe1,0xfa,0x2c,0x09 = vcvttss2si (%rcx), %rcx +0xc5,0x7f,0xf0,0x20 = vlddqu (%rax), %ymm12 +0xc4,0x41,0x7f,0x12,0xd4 = vmovddup %ymm12, %ymm10 +0xc5,0x7f,0x12,0x20 = vmovddup (%rax), %ymm12 +0xc4,0x41,0x7d,0x6f,0xd4 = vmovdqa %ymm12, %ymm10 +0xc5,0x7d,0x7f,0x20 = vmovdqa %ymm12, (%rax) +0xc5,0x7d,0x6f,0x20 = vmovdqa (%rax), %ymm12 +0xc4,0x41,0x7e,0x6f,0xd4 = vmovdqu %ymm12, %ymm10 +0xc5,0x7e,0x7f,0x20 = vmovdqu %ymm12, (%rax) +0xc5,0x7e,0x6f,0x20 = vmovdqu (%rax), %ymm12 +0xc4,0x41,0x7e,0x16,0xd4 = vmovshdup %ymm12, %ymm10 +0xc5,0x7e,0x16,0x20 = vmovshdup (%rax), %ymm12 +0xc4,0x41,0x7e,0x12,0xd4 = vmovsldup %ymm12, %ymm10 +0xc5,0x7e,0x12,0x20 = vmovsldup (%rax), %ymm12 +0xc4,0x42,0x7d,0x17,0xd4 = vptest %ymm12, %ymm10 +0xc4,0x62,0x7d,0x17,0x20 = vptest (%rax), %ymm12 +0xc4,0x43,0x7d,0x09,0xda,0x07 = vroundpd $7, %ymm10, %ymm11 +0xc4,0x63,0x7d,0x09,0x10,0x07 = vroundpd $7, (%rax), %ymm10 +0xc4,0x43,0x7d,0x08,0xda,0x07 = vroundps $7, %ymm10, %ymm11 +0xc4,0x63,0x7d,0x08,0x10,0x07 = vroundps $7, (%rax), %ymm10 +0xc4,0x41,0x2d,0xc6,0xdc,0x07 = vshufpd $7, %ymm12, %ymm10, %ymm11 +0xc5,0x2d,0xc6,0x18,0x07 = vshufpd $7, (%rax), %ymm10, %ymm11 +0xc4,0x41,0x2c,0xc6,0xdc,0x07 = vshufps $7, %ymm12, %ymm10, %ymm11 +0xc5,0x2c,0xc6,0x18,0x07 = vshufps $7, (%rax), %ymm10, %ymm11 +0xc4,0x42,0x79,0x0f,0xd4 = vtestpd %xmm12, %xmm10 +0xc4,0x42,0x7d,0x0f,0xd4 = vtestpd %ymm12, %ymm10 +0xc4,0x62,0x79,0x0f,0x20 = vtestpd (%rax), %xmm12 +0xc4,0x62,0x7d,0x0f,0x20 = vtestpd (%rax), %ymm12 +0xc4,0x42,0x79,0x0e,0xd4 = vtestps %xmm12, %xmm10 +0xc4,0x42,0x7d,0x0e,0xd4 = vtestps %ymm12, %ymm10 +0xc4,0x62,0x79,0x0e,0x20 = vtestps (%rax), %xmm12 +0xc4,0x62,0x7d,0x0e,0x20 = vtestps (%rax), %ymm12 +0xc4,0x43,0x79,0x17,0xc0,0x0a = vextractps $10, %xmm8, %r8d +0xc4,0xe3,0x79,0x17,0xe1,0x07 = vextractps $7, %xmm4, %ecx +0xc4,0xe1,0xf9,0x7e,0xe1 = vmovq %xmm4, %rcx +0xc5,0xf9,0x50,0xcc = vmovmskpd %xmm4, %ecx +0xc5,0xfd,0x50,0xcc = vmovmskpd %ymm4, %ecx +0xc5,0xf8,0x50,0xcc = vmovmskps %xmm4, %ecx +0xc5,0xfc,0x50,0xcc = vmovmskps %ymm4, %ecx +0xc4,0xe3,0x79,0x14,0xe1,0x07 = vpextrb $7, %xmm4, %ecx +0xc4,0x41,0x01,0xc4,0xc0,0x07 = vpinsrw $7, %r8d, %xmm15, %xmm8 +0xc5,0xd9,0xc4,0xf1,0x07 = vpinsrw $7, %ecx, %xmm4, %xmm6 +0xc5,0xf9,0xd7,0xcc = vpmovmskb %xmm4, %ecx +0xc4,0x63,0x1d,0x4b,0xac,0x20,0xad,0xde,0x00,0x00,0xb0 = vblendvpd %ymm11, 0xdead(%rax, %riz), %ymm12, %ymm13 +0xc4,0x81,0x78,0x29,0x1c,0x1e = vmovaps %xmm3, (%r14, %r11) +0xc4,0x81,0x78,0x28,0x1c,0x1e = vmovaps (%r14, %r11), %xmm3 +0xc4,0xc1,0x78,0x29,0x1c,0x1e = vmovaps %xmm3, (%r14, %rbx) +0xc4,0xc1,0x78,0x28,0x1c,0x1e = vmovaps (%r14, %rbx), %xmm3 +0xc4,0xa1,0x78,0x29,0x1c,0x18 = vmovaps %xmm3, (%rax, %r11) +0xc4,0xe2,0xf9,0x92,0x14,0x4f = vgatherdpd %xmm0, (%rdi, %xmm1, 2), %xmm2 +0xc4,0xe2,0xf9,0x93,0x14,0x4f = vgatherqpd %xmm0, (%rdi, %xmm1, 2), %xmm2 +0xc4,0xe2,0xfd,0x92,0x14,0x4f = vgatherdpd %ymm0, (%rdi, %xmm1, 2), %ymm2 +0xc4,0xe2,0xfd,0x93,0x14,0x4f = vgatherqpd %ymm0, (%rdi, %ymm1, 2), %ymm2 +0xc4,0x02,0x39,0x92,0x14,0x4f = vgatherdps %xmm8, (%r15, %xmm9, 2), %xmm10 +0xc4,0x02,0x39,0x93,0x14,0x4f = vgatherqps %xmm8, (%r15, %xmm9, 2), %xmm10 +0xc4,0x02,0x3d,0x92,0x14,0x4f = vgatherdps %ymm8, (%r15, %ymm9, 2), %ymm10 +0xc4,0x02,0x3d,0x93,0x14,0x4f = vgatherqps %xmm8, (%r15, %ymm9, 2), %xmm10 +0xc4,0xe2,0xf9,0x90,0x14,0x4f = vpgatherdq %xmm0, (%rdi, %xmm1, 2), %xmm2 +0xc4,0xe2,0xf9,0x91,0x14,0x4f = vpgatherqq %xmm0, (%rdi, %xmm1, 2), %xmm2 +0xc4,0xe2,0xfd,0x90,0x14,0x4f = vpgatherdq %ymm0, (%rdi, %xmm1, 2), %ymm2 +0xc4,0xe2,0xfd,0x91,0x14,0x4f = vpgatherqq %ymm0, (%rdi, %ymm1, 2), %ymm2 +0xc4,0x02,0x39,0x90,0x14,0x4f = vpgatherdd %xmm8, (%r15, %xmm9, 2), %xmm10 +0xc4,0x02,0x39,0x91,0x14,0x4f = vpgatherqd %xmm8, (%r15, %xmm9, 2), %xmm10 +0xc4,0x02,0x3d,0x90,0x14,0x4f = vpgatherdd %ymm8, (%r15, %ymm9, 2), %ymm10 +0xc4,0x02,0x3d,0x91,0x14,0x4f = vpgatherqd %xmm8, (%r15, %ymm9, 2), %xmm10 +0xc5,0x78,0x28,0xc0 = vmovaps %xmm0, %xmm8 +0xc5,0x78,0x29,0xc0 = vmovaps %xmm8, %xmm0 +0xc5,0x7c,0x28,0xc0 = vmovaps %ymm0, %ymm8 +0xc5,0x7c,0x29,0xc0 = vmovaps %ymm8, %ymm0 +0xc5,0x78,0x10,0xc0 = vmovups %xmm0, %xmm8 +0xc5,0x78,0x11,0xc0 = vmovups %xmm8, %xmm0 +0xc5,0x7c,0x10,0xc0 = vmovups %ymm0, %ymm8 +0xc5,0x7c,0x11,0xc0 = vmovups %ymm8, %ymm0 +0xc5,0x7a,0x10,0xc0 = vmovss %xmm0, %xmm0, %xmm8 +0xc5,0xba,0x10,0xc0 = vmovss %xmm0, %xmm8, %xmm0 +0xc5,0x7a,0x11,0xc0 = vmovss %xmm8, %xmm0, %xmm0 +0xc5,0x7b,0x10,0xc0 = vmovsd %xmm0, %xmm0, %xmm8 +0xc5,0xbb,0x10,0xc0 = vmovsd %xmm0, %xmm8, %xmm0 +0xc5,0x7b,0x11,0xc0 = vmovsd %xmm8, %xmm0, %xmm0 diff --git a/thirdparty/capstone/suite/MC/X86/x86_64-bmi-encoding.s.cs b/thirdparty/capstone/suite/MC/X86/x86_64-bmi-encoding.s.cs new file mode 100644 index 0000000..7151d2c --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86_64-bmi-encoding.s.cs @@ -0,0 +1,51 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0xc4,0xc2,0x28,0xf3,0xd3 = blsmskl %r11d, %r10d +0xc4,0xc2,0xa8,0xf3,0xd3 = blsmskq %r11, %r10 +0xc4,0xe2,0x28,0xf3,0x10 = blsmskl (%rax), %r10d +0xc4,0xe2,0xa8,0xf3,0x10 = blsmskq (%rax), %r10 +0xc4,0xc2,0x28,0xf3,0xdb = blsil %r11d, %r10d +0xc4,0xc2,0xa8,0xf3,0xdb = blsiq %r11, %r10 +0xc4,0xe2,0x28,0xf3,0x18 = blsil (%rax), %r10d +0xc4,0xe2,0xa8,0xf3,0x18 = blsiq (%rax), %r10 +0xc4,0xc2,0x28,0xf3,0xcb = blsrl %r11d, %r10d +0xc4,0xc2,0xa8,0xf3,0xcb = blsrq %r11, %r10 +0xc4,0xe2,0x28,0xf3,0x08 = blsrl (%rax), %r10d +0xc4,0xe2,0xa8,0xf3,0x08 = blsrq (%rax), %r10 +0xc4,0x62,0x20,0xf2,0x10 = andnl (%rax), %r11d, %r10d +0xc4,0x62,0xa0,0xf2,0x10 = andnq (%rax), %r11, %r10 +0xc4,0x62,0x18,0xf7,0x10 = bextrl %r12d, (%rax), %r10d +0xc4,0x42,0x18,0xf7,0xd3 = bextrl %r12d, %r11d, %r10d +0xc4,0x62,0x98,0xf7,0x10 = bextrq %r12, (%rax), %r10 +0xc4,0x42,0x98,0xf7,0xd3 = bextrq %r12, %r11, %r10 +0xc4,0x62,0x18,0xf5,0x10 = bzhil %r12d, (%rax), %r10d +0xc4,0x42,0x18,0xf5,0xd3 = bzhil %r12d, %r11d, %r10d +0xc4,0x62,0x98,0xf5,0x10 = bzhiq %r12, (%rax), %r10 +0xc4,0x42,0x98,0xf5,0xd3 = bzhiq %r12, %r11, %r10 +0xc4,0x42,0x22,0xf5,0xd4 = pextl %r12d, %r11d, %r10d +0xc4,0x62,0x22,0xf5,0x10 = pextl (%rax), %r11d, %r10d +0xc4,0x42,0xa2,0xf5,0xd4 = pextq %r12, %r11, %r10 +0xc4,0x62,0xa2,0xf5,0x10 = pextq (%rax), %r11, %r10 +0xc4,0x42,0x23,0xf5,0xd4 = pdepl %r12d, %r11d, %r10d +0xc4,0x62,0x23,0xf5,0x10 = pdepl (%rax), %r11d, %r10d +0xc4,0x42,0xa3,0xf5,0xd4 = pdepq %r12, %r11, %r10 +0xc4,0x62,0xa3,0xf5,0x10 = pdepq (%rax), %r11, %r10 +0xc4,0x42,0x23,0xf6,0xd4 = mulxl %r12d, %r11d, %r10d +0xc4,0x62,0x23,0xf6,0x10 = mulxl (%rax), %r11d, %r10d +0xc4,0x42,0xa3,0xf6,0xd4 = mulxq %r12, %r11, %r10 +0xc4,0x62,0xa3,0xf6,0x10 = mulxq (%rax), %r11, %r10 +0xc4,0x43,0x7b,0xf0,0xd4,0x0a = rorxl $10, %r12d, %r10d +0xc4,0x63,0x7b,0xf0,0x10,0x1f = rorxl $31, (%rax), %r10d +0xc4,0x43,0xfb,0xf0,0xd4,0x01 = rorxq $1, %r12, %r10 +0xc4,0x63,0xfb,0xf0,0x10,0x3f = rorxq $63, (%rax), %r10 +0xc4,0x62,0x19,0xf7,0x10 = shlxl %r12d, (%rax), %r10d +0xc4,0x42,0x19,0xf7,0xd3 = shlxl %r12d, %r11d, %r10d +0xc4,0x62,0x99,0xf7,0x10 = shlxq %r12, (%rax), %r10 +0xc4,0x42,0x99,0xf7,0xd3 = shlxq %r12, %r11, %r10 +0xc4,0x62,0x1a,0xf7,0x10 = sarxl %r12d, (%rax), %r10d +0xc4,0x42,0x1a,0xf7,0xd3 = sarxl %r12d, %r11d, %r10d +0xc4,0x62,0x9a,0xf7,0x10 = sarxq %r12, (%rax), %r10 +0xc4,0x42,0x9a,0xf7,0xd3 = sarxq %r12, %r11, %r10 +0xc4,0x62,0x1b,0xf7,0x10 = shrxl %r12d, (%rax), %r10d +0xc4,0x42,0x1b,0xf7,0xd3 = shrxl %r12d, %r11d, %r10d +0xc4,0x62,0x9b,0xf7,0x10 = shrxq %r12, (%rax), %r10 +0xc4,0x42,0x9b,0xf7,0xd3 = shrxq %r12, %r11, %r10 diff --git a/thirdparty/capstone/suite/MC/X86/x86_64-encoding.s.cs b/thirdparty/capstone/suite/MC/X86/x86_64-encoding.s.cs new file mode 100644 index 0000000..a8e04f8 --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86_64-encoding.s.cs @@ -0,0 +1,59 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x65,0x48,0x8b,0x07 = movq %gs:(%rdi), %rax +0xf2,0x0f,0x38,0xf0,0xc3 = crc32b %bl, %eax +0xf2,0x0f,0x38,0xf0,0x43,0x04 = crc32b 4(%rbx), %eax +0x66,0xf2,0x0f,0x38,0xf1,0xc3 = crc32w %bx, %eax +0x66,0xf2,0x0f,0x38,0xf1,0x43,0x04 = crc32w 4(%rbx), %eax +0xf2,0x0f,0x38,0xf1,0xc3 = crc32l %ebx, %eax +0xf2,0x0f,0x38,0xf1,0x43,0x04 = crc32l 4(%rbx), %eax +0xf2,0x0f,0x38,0xf1,0x8c,0xcb,0xef,0xbe,0xad,0xde = crc32l -0x21524111(%rbx, %rcx, 8), %ecx +0xf2,0x0f,0x38,0xf1,0x0c,0x25,0x45,0x00,0x00,0x00 = crc32l 0x45, %ecx +0xf2,0x0f,0x38,0xf1,0x0c,0x25,0xed,0x7e,0x00,0x00 = crc32l 0x7eed, %ecx +0xf2,0x0f,0x38,0xf1,0x0c,0x25,0xfe,0xca,0xbe,0xba = crc32l 0xffffffffbabecafe, %ecx +0xf2,0x0f,0x38,0xf1,0xc9 = crc32l %ecx, %ecx +0xf2,0x41,0x0f,0x38,0xf0,0xc3 = crc32b %r11b, %eax +0xf2,0x0f,0x38,0xf0,0x43,0x04 = crc32b 4(%rbx), %eax +0xf2,0x48,0x0f,0x38,0xf0,0xc7 = crc32b %dil, %rax +0xf2,0x49,0x0f,0x38,0xf0,0xc3 = crc32b %r11b, %rax +0xf2,0x48,0x0f,0x38,0xf0,0x43,0x04 = crc32b 4(%rbx), %rax +0xf2,0x48,0x0f,0x38,0xf1,0xc3 = crc32q %rbx, %rax +0xf2,0x48,0x0f,0x38,0xf1,0x43,0x04 = crc32q 4(%rbx), %rax +0x49,0x0f,0x6e,0xc8 = movq %r8, %mm1 +0x41,0x0f,0x6e,0xc8 = movd %r8d, %mm1 +0x48,0x0f,0x6e,0xca = movq %rdx, %mm1 +0x0f,0x6e,0xca = movd %edx, %mm1 +0x49,0x0f,0x7e,0xc8 = movq %mm1, %r8 +0x41,0x0f,0x7e,0xc8 = movd %mm1, %r8d +0x48,0x0f,0x7e,0xca = movq %mm1, %rdx +0x0f,0x7e,0xca = movd %mm1, %edx +0x0f,0x3a,0xcc,0xd1,0x01 = sha1rnds4 $1, %xmm1, %xmm2 +0x0f,0x3a,0xcc,0x10,0x01 = sha1rnds4 $1, (%rax), %xmm2 +0x0f,0x38,0xc8,0xd1 = sha1nexte %xmm1, %xmm2 +0x0f,0x38,0xc9,0xd1 = sha1msg1 %xmm1, %xmm2 +0x0f,0x38,0xc9,0x10 = sha1msg1 (%rax), %xmm2 +0x0f,0x38,0xca,0xd1 = sha1msg2 %xmm1, %xmm2 +0x0f,0x38,0xca,0x10 = sha1msg2 (%rax), %xmm2 +0x0f,0x38,0xcb,0x10 = sha256rnds2 %xmm0, (%rax), %xmm2 +0x0f,0x38,0xcb,0xd1 = sha256rnds2 %xmm0, %xmm1, %xmm2 +0x0f,0x38,0xcb,0x10 = sha256rnds2 %xmm0, (%rax), %xmm2 +0x0f,0x38,0xcb,0xd1 = sha256rnds2 %xmm0, %xmm1, %xmm2 +0x0f,0x38,0xcc,0xd1 = sha256msg1 %xmm1, %xmm2 +0x0f,0x38,0xcc,0x10 = sha256msg1 (%rax), %xmm2 +0x0f,0x38,0xcd,0xd1 = sha256msg2 %xmm1, %xmm2 +0x0f,0x38,0xcd,0x10 = sha256msg2 (%rax), %xmm2 +0x48,0x8b,0x1c,0x25,0xad,0xde,0x00,0x00 = movq 0xdead, %rbx +0x48,0x8b,0x04,0x25,0xef,0xbe,0x00,0x00 = movq 0xbeef, %rax +0x48,0x8b,0x04,0xe5,0xfc,0xff,0xff,0xff = movq -4(, %riz, 8), %rax +0x48,0x8b,0x04,0x21 = movq (%rcx, %riz), %rax +0x48,0x8b,0x04,0xe1 = movq (%rcx, %riz, 8), %rax +0x48,0x0f,0xae,0x00 = fxsave64 (%rax) +0x48,0x0f,0xae,0x08 = fxrstor64 (%rax) +0xc9 = leave +0xc9 = leave +0x67,0xd9,0x07 = flds (%edi) +0x67,0xdf,0x07 = filds (%edi) +0xd9,0x07 = flds (%rdi) +0xdf,0x07 = filds (%rdi) +0x66,0x0f,0xd7,0xcd = pmovmskb %xmm5, %ecx +0x66,0x0f,0xc4,0xe9,0x03 = pinsrw $3, %ecx, %xmm5 +0x66,0x0f,0xc4,0xe9,0x03 = pinsrw $3, %ecx, %xmm5 diff --git a/thirdparty/capstone/suite/MC/X86/x86_64-fma3-encoding.s.cs b/thirdparty/capstone/suite/MC/X86/x86_64-fma3-encoding.s.cs new file mode 100644 index 0000000..389e368 --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86_64-fma3-encoding.s.cs @@ -0,0 +1,169 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0xc4,0x42,0xa9,0x98,0xdc = vfmadd132pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0x98,0x18 = vfmadd132pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0x98,0xdc = vfmadd132ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0x98,0x18 = vfmadd132ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xa8,0xdc = vfmadd213pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xa8,0x18 = vfmadd213pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xa8,0xdc = vfmadd213ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xa8,0x18 = vfmadd213ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xb8,0xdc = vfmadd231pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xb8,0x18 = vfmadd231pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xb8,0xdc = vfmadd231ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xb8,0x18 = vfmadd231ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xad,0x98,0xdc = vfmadd132pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0x98,0x18 = vfmadd132pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0x98,0xdc = vfmadd132ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0x98,0x18 = vfmadd132ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xa8,0xdc = vfmadd213pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xa8,0x18 = vfmadd213pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xa8,0xdc = vfmadd213ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xa8,0x18 = vfmadd213ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xb8,0xdc = vfmadd231pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xb8,0x18 = vfmadd231pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xb8,0xdc = vfmadd231ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xb8,0x18 = vfmadd231ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xa9,0x98,0xdc = vfmadd132pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0x98,0x18 = vfmadd132pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0x98,0xdc = vfmadd132ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0x98,0x18 = vfmadd132ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xa8,0xdc = vfmadd213pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xa8,0x18 = vfmadd213pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xa8,0xdc = vfmadd213ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xa8,0x18 = vfmadd213ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xb8,0xdc = vfmadd231pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xb8,0x18 = vfmadd231pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xb8,0xdc = vfmadd231ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xb8,0x18 = vfmadd231ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0x96,0xdc = vfmaddsub132pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0x96,0x18 = vfmaddsub132pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0x96,0xdc = vfmaddsub132ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0x96,0x18 = vfmaddsub132ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xa6,0xdc = vfmaddsub213pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xa6,0x18 = vfmaddsub213pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xa6,0xdc = vfmaddsub213ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xa6,0x18 = vfmaddsub213ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xb6,0xdc = vfmaddsub231pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xb6,0x18 = vfmaddsub231pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xb6,0xdc = vfmaddsub231ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xb6,0x18 = vfmaddsub231ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0x97,0xdc = vfmsubadd132pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0x97,0x18 = vfmsubadd132pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0x97,0xdc = vfmsubadd132ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0x97,0x18 = vfmsubadd132ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xa7,0xdc = vfmsubadd213pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xa7,0x18 = vfmsubadd213pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xa7,0xdc = vfmsubadd213ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xa7,0x18 = vfmsubadd213ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xb7,0xdc = vfmsubadd231pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xb7,0x18 = vfmsubadd231pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xb7,0xdc = vfmsubadd231ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xb7,0x18 = vfmsubadd231ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0x9a,0xdc = vfmsub132pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0x9a,0x18 = vfmsub132pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0x9a,0xdc = vfmsub132ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0x9a,0x18 = vfmsub132ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xaa,0xdc = vfmsub213pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xaa,0x18 = vfmsub213pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xaa,0xdc = vfmsub213ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xaa,0x18 = vfmsub213ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xba,0xdc = vfmsub231pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xba,0x18 = vfmsub231pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xba,0xdc = vfmsub231ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xba,0x18 = vfmsub231ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0x9c,0xdc = vfnmadd132pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0x9c,0x18 = vfnmadd132pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0x9c,0xdc = vfnmadd132ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0x9c,0x18 = vfnmadd132ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xac,0xdc = vfnmadd213pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xac,0x18 = vfnmadd213pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xac,0xdc = vfnmadd213ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xac,0x18 = vfnmadd213ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xbc,0xdc = vfnmadd231pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xbc,0x18 = vfnmadd231pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xbc,0xdc = vfnmadd231ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xbc,0x18 = vfnmadd231ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0x9e,0xdc = vfnmsub132pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0x9e,0x18 = vfnmsub132pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0x9e,0xdc = vfnmsub132ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0x9e,0x18 = vfnmsub132ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xae,0xdc = vfnmsub213pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xae,0x18 = vfnmsub213pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xae,0xdc = vfnmsub213ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xae,0x18 = vfnmsub213ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xa9,0xbe,0xdc = vfnmsub231pd %xmm12, %xmm10, %xmm11 +0xc4,0x62,0xa9,0xbe,0x18 = vfnmsub231pd (%rax), %xmm10, %xmm11 +0xc4,0x42,0x29,0xbe,0xdc = vfnmsub231ps %xmm12, %xmm10, %xmm11 +0xc4,0x62,0x29,0xbe,0x18 = vfnmsub231ps (%rax), %xmm10, %xmm11 +0xc4,0x42,0xad,0x98,0xdc = vfmadd132pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0x98,0x18 = vfmadd132pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0x98,0xdc = vfmadd132ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0x98,0x18 = vfmadd132ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xa8,0xdc = vfmadd213pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xa8,0x18 = vfmadd213pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xa8,0xdc = vfmadd213ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xa8,0x18 = vfmadd213ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xb8,0xdc = vfmadd231pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xb8,0x18 = vfmadd231pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xb8,0xdc = vfmadd231ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xb8,0x18 = vfmadd231ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0x96,0xdc = vfmaddsub132pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0x96,0x18 = vfmaddsub132pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0x96,0xdc = vfmaddsub132ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0x96,0x18 = vfmaddsub132ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xa6,0xdc = vfmaddsub213pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xa6,0x18 = vfmaddsub213pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xa6,0xdc = vfmaddsub213ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xa6,0x18 = vfmaddsub213ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xb6,0xdc = vfmaddsub231pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xb6,0x18 = vfmaddsub231pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xb6,0xdc = vfmaddsub231ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xb6,0x18 = vfmaddsub231ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0x97,0xdc = vfmsubadd132pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0x97,0x18 = vfmsubadd132pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0x97,0xdc = vfmsubadd132ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0x97,0x18 = vfmsubadd132ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xa7,0xdc = vfmsubadd213pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xa7,0x18 = vfmsubadd213pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xa7,0xdc = vfmsubadd213ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xa7,0x18 = vfmsubadd213ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xb7,0xdc = vfmsubadd231pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xb7,0x18 = vfmsubadd231pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xb7,0xdc = vfmsubadd231ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xb7,0x18 = vfmsubadd231ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0x9a,0xdc = vfmsub132pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0x9a,0x18 = vfmsub132pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0x9a,0xdc = vfmsub132ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0x9a,0x18 = vfmsub132ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xaa,0xdc = vfmsub213pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xaa,0x18 = vfmsub213pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xaa,0xdc = vfmsub213ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xaa,0x18 = vfmsub213ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xba,0xdc = vfmsub231pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xba,0x18 = vfmsub231pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xba,0xdc = vfmsub231ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xba,0x18 = vfmsub231ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0x9c,0xdc = vfnmadd132pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0x9c,0x18 = vfnmadd132pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0x9c,0xdc = vfnmadd132ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0x9c,0x18 = vfnmadd132ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xac,0xdc = vfnmadd213pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xac,0x18 = vfnmadd213pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xac,0xdc = vfnmadd213ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xac,0x18 = vfnmadd213ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xbc,0xdc = vfnmadd231pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xbc,0x18 = vfnmadd231pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xbc,0xdc = vfnmadd231ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xbc,0x18 = vfnmadd231ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0x9e,0xdc = vfnmsub132pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0x9e,0x18 = vfnmsub132pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0x9e,0xdc = vfnmsub132ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0x9e,0x18 = vfnmsub132ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xae,0xdc = vfnmsub213pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xae,0x18 = vfnmsub213pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xae,0xdc = vfnmsub213ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xae,0x18 = vfnmsub213ps (%rax), %ymm10, %ymm11 +0xc4,0x42,0xad,0xbe,0xdc = vfnmsub231pd %ymm12, %ymm10, %ymm11 +0xc4,0x62,0xad,0xbe,0x18 = vfnmsub231pd (%rax), %ymm10, %ymm11 +0xc4,0x42,0x2d,0xbe,0xdc = vfnmsub231ps %ymm12, %ymm10, %ymm11 +0xc4,0x62,0x2d,0xbe,0x18 = vfnmsub231ps (%rax), %ymm10, %ymm11 diff --git a/thirdparty/capstone/suite/MC/X86/x86_64-fma4-encoding.s.cs b/thirdparty/capstone/suite/MC/X86/x86_64-fma4-encoding.s.cs new file mode 100644 index 0000000..c3eef0e --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86_64-fma4-encoding.s.cs @@ -0,0 +1,98 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0xc4,0xe3,0xf9,0x6a,0x01,0x10 = vfmaddss (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x6a,0x01,0x10 = vfmaddss %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x6a,0xc2,0x10 = vfmaddss %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x6b,0x01,0x10 = vfmaddsd (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x6b,0x01,0x10 = vfmaddsd %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x6b,0xc2,0x10 = vfmaddsd %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xc3,0xf9,0x6b,0xc2,0x10 = vfmaddsd %xmm10, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x68,0x01,0x10 = vfmaddps (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x68,0x01,0x10 = vfmaddps %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x68,0xc2,0x10 = vfmaddps %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x69,0x01,0x10 = vfmaddpd (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x69,0x01,0x10 = vfmaddpd %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x69,0xc2,0x10 = vfmaddpd %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xfd,0x68,0x01,0x10 = vfmaddps (%rcx), %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0x7d,0x68,0x01,0x10 = vfmaddps %ymm1, (%rcx), %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x68,0xc2,0x10 = vfmaddps %ymm2, %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x69,0x01,0x10 = vfmaddpd (%rcx), %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0x7d,0x69,0x01,0x10 = vfmaddpd %ymm1, (%rcx), %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x69,0xc2,0x10 = vfmaddpd %ymm2, %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0xf9,0x6e,0x01,0x10 = vfmsubss (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x6e,0x01,0x10 = vfmsubss %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x6e,0xc2,0x10 = vfmsubss %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x6f,0x01,0x10 = vfmsubsd (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x6f,0x01,0x10 = vfmsubsd %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x6f,0xc2,0x10 = vfmsubsd %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x6c,0x01,0x10 = vfmsubps (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x6c,0x01,0x10 = vfmsubps %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x6c,0xc2,0x10 = vfmsubps %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x6d,0x01,0x10 = vfmsubpd (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x6d,0x01,0x10 = vfmsubpd %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x6d,0xc2,0x10 = vfmsubpd %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xfd,0x6c,0x01,0x10 = vfmsubps (%rcx), %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0x7d,0x6c,0x01,0x10 = vfmsubps %ymm1, (%rcx), %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x6c,0xc2,0x10 = vfmsubps %ymm2, %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x6d,0x01,0x10 = vfmsubpd (%rcx), %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0x7d,0x6d,0x01,0x10 = vfmsubpd %ymm1, (%rcx), %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x6d,0xc2,0x10 = vfmsubpd %ymm2, %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0xf9,0x7a,0x01,0x10 = vfnmaddss (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x7a,0x01,0x10 = vfnmaddss %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x7a,0xc2,0x10 = vfnmaddss %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x7b,0x01,0x10 = vfnmaddsd (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x7b,0x01,0x10 = vfnmaddsd %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x7b,0xc2,0x10 = vfnmaddsd %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x78,0x01,0x10 = vfnmaddps (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x78,0x01,0x10 = vfnmaddps %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x78,0xc2,0x10 = vfnmaddps %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x79,0x01,0x10 = vfnmaddpd (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x79,0x01,0x10 = vfnmaddpd %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x79,0xc2,0x10 = vfnmaddpd %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xfd,0x78,0x01,0x10 = vfnmaddps (%rcx), %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0x7d,0x78,0x01,0x10 = vfnmaddps %ymm1, (%rcx), %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x78,0xc2,0x10 = vfnmaddps %ymm2, %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x79,0x01,0x10 = vfnmaddpd (%rcx), %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0x7d,0x79,0x01,0x10 = vfnmaddpd %ymm1, (%rcx), %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x79,0xc2,0x10 = vfnmaddpd %ymm2, %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0xf9,0x7e,0x01,0x10 = vfnmsubss (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x7e,0x01,0x10 = vfnmsubss %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x7e,0xc2,0x10 = vfnmsubss %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x7f,0x01,0x10 = vfnmsubsd (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x7f,0x01,0x10 = vfnmsubsd %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x7f,0xc2,0x10 = vfnmsubsd %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x7c,0x01,0x10 = vfnmsubps (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x7c,0x01,0x10 = vfnmsubps %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x7c,0xc2,0x10 = vfnmsubps %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x7d,0x01,0x10 = vfnmsubpd (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x7d,0x01,0x10 = vfnmsubpd %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x7d,0xc2,0x10 = vfnmsubpd %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xfd,0x7c,0x01,0x10 = vfnmsubps (%rcx), %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0x7d,0x7c,0x01,0x10 = vfnmsubps %ymm1, (%rcx), %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x7c,0xc2,0x10 = vfnmsubps %ymm2, %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x7d,0x01,0x10 = vfnmsubpd (%rcx), %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0x7d,0x7d,0x01,0x10 = vfnmsubpd %ymm1, (%rcx), %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x7d,0xc2,0x10 = vfnmsubpd %ymm2, %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0xf9,0x5c,0x01,0x10 = vfmaddsubps (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x5c,0x01,0x10 = vfmaddsubps %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x5c,0xc2,0x10 = vfmaddsubps %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x5d,0x01,0x10 = vfmaddsubpd (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x5d,0x01,0x10 = vfmaddsubpd %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x5d,0xc2,0x10 = vfmaddsubpd %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xfd,0x5c,0x01,0x10 = vfmaddsubps (%rcx), %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0x7d,0x5c,0x01,0x10 = vfmaddsubps %ymm1, (%rcx), %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x5c,0xc2,0x10 = vfmaddsubps %ymm2, %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x5d,0x01,0x10 = vfmaddsubpd (%rcx), %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0x7d,0x5d,0x01,0x10 = vfmaddsubpd %ymm1, (%rcx), %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x5d,0xc2,0x10 = vfmaddsubpd %ymm2, %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0xf9,0x5e,0x01,0x10 = vfmsubaddps (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x5e,0x01,0x10 = vfmsubaddps %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x5e,0xc2,0x10 = vfmsubaddps %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x5f,0x01,0x10 = vfmsubaddpd (%rcx), %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0x79,0x5f,0x01,0x10 = vfmsubaddpd %xmm1, (%rcx), %xmm0, %xmm0 +0xc4,0xe3,0xf9,0x5f,0xc2,0x10 = vfmsubaddpd %xmm2, %xmm1, %xmm0, %xmm0 +0xc4,0xe3,0xfd,0x5e,0x01,0x10 = vfmsubaddps (%rcx), %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0x7d,0x5e,0x01,0x10 = vfmsubaddps %ymm1, (%rcx), %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x5e,0xc2,0x10 = vfmsubaddps %ymm2, %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x5f,0x01,0x10 = vfmsubaddpd (%rcx), %ymm1, %ymm0, %ymm0 +0xc4,0xe3,0x7d,0x5f,0x01,0x10 = vfmsubaddpd %ymm1, (%rcx), %ymm0, %ymm0 +0xc4,0xe3,0xfd,0x5f,0xc2,0x10 = vfmsubaddpd %ymm2, %ymm1, %ymm0, %ymm0 diff --git a/thirdparty/capstone/suite/MC/X86/x86_64-imm-widths.s.cs b/thirdparty/capstone/suite/MC/X86/x86_64-imm-widths.s.cs new file mode 100644 index 0000000..4f2df32 --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86_64-imm-widths.s.cs @@ -0,0 +1,27 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x04,0x00 = addb $0x00, %al +0x04,0x7f = addb $0x7F, %al +0x04,0x80 = addb $0x80, %al +0x04,0xff = addb $0xFF, %al +0x66,0x83,0xc0,0x00 = addw $0x0000, %ax +0x66,0x83,0xc0,0x7f = addw $0x007F, %ax +0x66,0x83,0xc0,0x80 = addw $-0x80, %ax +0x66,0x83,0xc0,0xff = addw $-1, %ax +0x83,0xc0,0x00 = addl $0x00000000, %eax +0x83,0xc0,0x7f = addl $0x0000007F, %eax +0x05,0x80,0xff,0x00,0x00 = addl $0xFF80, %eax +0x05,0xff,0xff,0x00,0x00 = addl $0xFFFF, %eax +0x83,0xc0,0x80 = addl $-0x80, %eax +0x83,0xc0,0xff = addl $-1, %eax +0x48,0x83,0xc0,0x00 = addq $0x0000000000000000, %rax +0x48,0x83,0xc0,0x7f = addq $0x000000000000007F, %rax +0x48,0x83,0xc0,0x80 = addq $0xFFFFFFFFFFFFFF80, %rax +0x48,0x83,0xc0,0xff = addq $0xFFFFFFFFFFFFFFFF, %rax +0x48,0x83,0xc0,0x00 = addq $0x0000000000000000, %rax +0x48,0x05,0x80,0xff,0x00,0x00 = addq $0xFF80, %rax +0x48,0x05,0xff,0xff,0x00,0x00 = addq $0xFFFF, %rax +0x48,0xb8,0x80,0xff,0xff,0xff,0x00,0x00,0x00,0x00 = movabsq $0xFFFFFF80, %rax +0x48,0xb8,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00 = movabsq $0xFFFFFFFF, %rax +0x48,0x05,0xff,0xff,0xff,0x7f = addq $0x000000007FFFFFFF, %rax +0x48,0x05,0x00,0x00,0x00,0x80 = addq $0xFFFFFFFF80000000, %rax +0x48,0x05,0x00,0xff,0xff,0xff = addq $0xFFFFFFFFFFFFFF00, %rax diff --git a/thirdparty/capstone/suite/MC/X86/x86_64-rand-encoding.s.cs b/thirdparty/capstone/suite/MC/X86/x86_64-rand-encoding.s.cs new file mode 100644 index 0000000..23b1b22 --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86_64-rand-encoding.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x66,0x0f,0xc7,0xf0 = rdrandw %ax +0x0f,0xc7,0xf0 = rdrandl %eax +0x48,0x0f,0xc7,0xf0 = rdrandq %rax +0x66,0x41,0x0f,0xc7,0xf3 = rdrandw %r11w +0x41,0x0f,0xc7,0xf3 = rdrandl %r11d +0x49,0x0f,0xc7,0xf3 = rdrandq %r11 +0x66,0x0f,0xc7,0xf8 = rdseedw %ax +0x0f,0xc7,0xf8 = rdseedl %eax +0x48,0x0f,0xc7,0xf8 = rdseedq %rax +0x66,0x41,0x0f,0xc7,0xfb = rdseedw %r11w +0x41,0x0f,0xc7,0xfb = rdseedl %r11d +0x49,0x0f,0xc7,0xfb = rdseedq %r11 diff --git a/thirdparty/capstone/suite/MC/X86/x86_64-rtm-encoding.s.cs b/thirdparty/capstone/suite/MC/X86/x86_64-rtm-encoding.s.cs new file mode 100644 index 0000000..0695dc2 --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86_64-rtm-encoding.s.cs @@ -0,0 +1,4 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x0f,0x01,0xd5 = xend +0x0f,0x01,0xd6 = xtest +0xc6,0xf8,0x0d = xabort $13 diff --git a/thirdparty/capstone/suite/MC/X86/x86_64-sse4a.s.cs b/thirdparty/capstone/suite/MC/X86/x86_64-sse4a.s.cs new file mode 100644 index 0000000..6403f14 --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86_64-sse4a.s.cs @@ -0,0 +1 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT diff --git a/thirdparty/capstone/suite/MC/X86/x86_64-tbm-encoding.s.cs b/thirdparty/capstone/suite/MC/X86/x86_64-tbm-encoding.s.cs new file mode 100644 index 0000000..a8d6fcc --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86_64-tbm-encoding.s.cs @@ -0,0 +1,40 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x8f,0xea,0x78,0x10,0xc7,0xfe,0x0a,0x00,0x00 = bextrl $2814, %edi, %eax +0x8f,0xea,0x78,0x10,0x07,0xfe,0x0a,0x00,0x00 = bextrl $2814, (%rdi), %eax +0x8f,0xea,0xf8,0x10,0xc7,0xfe,0x0a,0x00,0x00 = bextrq $2814, %rdi, %rax +0x8f,0xea,0xf8,0x10,0x07,0xfe,0x0a,0x00,0x00 = bextrq $2814, (%rdi), %rax +0x8f,0xe9,0x78,0x01,0xcf = blcfilll %edi, %eax +0x8f,0xe9,0x78,0x01,0x0f = blcfilll (%rdi), %eax +0x8f,0xe9,0xf8,0x01,0xcf = blcfillq %rdi, %rax +0x8f,0xe9,0xf8,0x01,0x0f = blcfillq (%rdi), %rax +0x8f,0xe9,0x78,0x02,0xf7 = blcil %edi, %eax +0x8f,0xe9,0x78,0x02,0x37 = blcil (%rdi), %eax +0x8f,0xe9,0xf8,0x02,0xf7 = blciq %rdi, %rax +0x8f,0xe9,0xf8,0x02,0x37 = blciq (%rdi), %rax +0x8f,0xe9,0x78,0x01,0xef = blcicl %edi, %eax +0x8f,0xe9,0x78,0x01,0x2f = blcicl (%rdi), %eax +0x8f,0xe9,0xf8,0x01,0xef = blcicq %rdi, %rax +0x8f,0xe9,0xf8,0x01,0x2f = blcicq (%rdi), %rax +0x8f,0xe9,0x78,0x02,0xcf = blcmskl %edi, %eax +0x8f,0xe9,0x78,0x02,0x0f = blcmskl (%rdi), %eax +0x8f,0xe9,0xf8,0x02,0xcf = blcmskq %rdi, %rax +0x8f,0xe9,0xf8,0x02,0x0f = blcmskq (%rdi), %rax +0x8f,0xe9,0x78,0x01,0xdf = blcsl %edi, %eax +0x8f,0xe9,0x78,0x01,0x1f = blcsl (%rdi), %eax +0x8f,0xe9,0xf8,0x01,0xdf = blcsq %rdi, %rax +0x8f,0xe9,0xf8,0x01,0x1f = blcsq (%rdi), %rax +0x8f,0xe9,0x78,0x01,0xd7 = blsfilll %edi, %eax +0x8f,0xe9,0x78,0x01,0x17 = blsfilll (%rdi), %eax +0x8f,0xe9,0xf8,0x01,0xd7 = blsfillq %rdi, %rax +0x8f,0xe9,0xf8,0x01,0x17 = blsfillq (%rdi), %rax +0x8f,0xe9,0x78,0x01,0xf7 = blsicl %edi, %eax +0x8f,0xe9,0x78,0x01,0x37 = blsicl (%rdi), %eax +0x8f,0xe9,0xf8,0x01,0xf7 = blsicq %rdi, %rax +0x8f,0xe9,0x78,0x01,0xff = t1mskcl %edi, %eax +0x8f,0xe9,0x78,0x01,0x3f = t1mskcl (%rdi), %eax +0x8f,0xe9,0xf8,0x01,0xff = t1mskcq %rdi, %rax +0x8f,0xe9,0xf8,0x01,0x3f = t1mskcq (%rdi), %rax +0x8f,0xe9,0x78,0x01,0xe7 = tzmskl %edi, %eax +0x8f,0xe9,0x78,0x01,0x27 = tzmskl (%rdi), %eax +0x8f,0xe9,0xf8,0x01,0xe7 = tzmskq %rdi, %rax +0x8f,0xe9,0xf8,0x01,0x27 = tzmskq (%rdi), %rax diff --git a/thirdparty/capstone/suite/MC/X86/x86_64-xop-encoding.s.cs b/thirdparty/capstone/suite/MC/X86/x86_64-xop-encoding.s.cs new file mode 100644 index 0000000..4adebcb --- /dev/null +++ b/thirdparty/capstone/suite/MC/X86/x86_64-xop-encoding.s.cs @@ -0,0 +1,152 @@ +# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x8f,0xe9,0x78,0xe2,0x0c,0x01 = vphsubwd (%rcx, %rax), %xmm1 +0x8f,0xe9,0x78,0xe2,0xc8 = vphsubwd %xmm0, %xmm1 +0x8f,0xe9,0x78,0xe3,0x0c,0x01 = vphsubdq (%rcx, %rax), %xmm1 +0x8f,0xe9,0x78,0xe3,0xc8 = vphsubdq %xmm0, %xmm1 +0x8f,0xe9,0x78,0xe1,0x08 = vphsubbw (%rax), %xmm1 +0x8f,0xe9,0x78,0xe1,0xca = vphsubbw %xmm2, %xmm1 +0x8f,0xe9,0x78,0xc7,0x21 = vphaddwq (%rcx), %xmm4 +0x8f,0xe9,0x78,0xc7,0xd6 = vphaddwq %xmm6, %xmm2 +0x8f,0xe9,0x78,0xc6,0x3c,0x02 = vphaddwd (%rdx, %rax), %xmm7 +0x8f,0xe9,0x78,0xc6,0xe3 = vphaddwd %xmm3, %xmm4 +0x8f,0xe9,0x78,0xd7,0x34,0x01 = vphadduwq (%rcx, %rax), %xmm6 +0x8f,0xe9,0x78,0xd7,0xc7 = vphadduwq %xmm7, %xmm0 +0x8f,0xe9,0x78,0xd6,0x28 = vphadduwd (%rax), %xmm5 +0x8f,0xe9,0x78,0xd6,0xca = vphadduwd %xmm2, %xmm1 +0x8f,0xe9,0x78,0xdb,0x64,0x01,0x08 = vphaddudq 8(%rcx, %rax), %xmm4 +0x8f,0xe9,0x78,0xdb,0xd6 = vphaddudq %xmm6, %xmm2 +0x8f,0xe9,0x78,0xd1,0x19 = vphaddubw (%rcx), %xmm3 +0x8f,0xe9,0x78,0xd1,0xc5 = vphaddubw %xmm5, %xmm0 +0x8f,0xe9,0x78,0xd3,0x21 = vphaddubq (%rcx), %xmm4 +0x8f,0xe9,0x78,0xd3,0xd2 = vphaddubq %xmm2, %xmm2 +0x8f,0xe9,0x78,0xd2,0x28 = vphaddubd (%rax), %xmm5 +0x8f,0xe9,0x78,0xd2,0xfd = vphaddubd %xmm5, %xmm7 +0x8f,0xe9,0x78,0xcb,0x22 = vphadddq (%rdx), %xmm4 +0x8f,0xe9,0x78,0xcb,0xec = vphadddq %xmm4, %xmm5 +0x8f,0xe9,0x78,0xc1,0x0c,0x01 = vphaddbw (%rcx, %rax), %xmm1 +0x8f,0xe9,0x78,0xc1,0xf5 = vphaddbw %xmm5, %xmm6 +0x8f,0xe9,0x78,0xc3,0x0c,0x01 = vphaddbq (%rcx, %rax), %xmm1 +0x8f,0xe9,0x78,0xc3,0xc2 = vphaddbq %xmm2, %xmm0 +0x8f,0xe9,0x78,0xc2,0x0c,0x01 = vphaddbd (%rcx, %rax), %xmm1 +0x8f,0xe9,0x78,0xc2,0xd9 = vphaddbd %xmm1, %xmm3 +0x8f,0xe9,0x78,0x82,0x0c,0x01 = vfrczss (%rcx, %rax), %xmm1 +0x8f,0xe9,0x78,0x82,0xfd = vfrczss %xmm5, %xmm7 +0x8f,0xe9,0x78,0x83,0x0c,0x01 = vfrczsd (%rcx, %rax), %xmm1 +0x8f,0xe9,0x78,0x83,0xc7 = vfrczsd %xmm7, %xmm0 +0x8f,0xe9,0x78,0x80,0x58,0x04 = vfrczps 4(%rax), %xmm3 +0x8f,0xe9,0x78,0x80,0xee = vfrczps %xmm6, %xmm5 +0x8f,0xe9,0x78,0x80,0x09 = vfrczps (%rcx), %xmm1 +0x8f,0xe9,0x7c,0x80,0xe2 = vfrczps %ymm2, %ymm4 +0x8f,0xe9,0x78,0x81,0x0c,0x01 = vfrczpd (%rcx, %rax), %xmm1 +0x8f,0xe9,0x78,0x81,0xc7 = vfrczpd %xmm7, %xmm0 +0x8f,0xe9,0x7c,0x81,0x14,0x01 = vfrczpd (%rcx, %rax), %ymm2 +0x8f,0xe9,0x7c,0x81,0xdd = vfrczpd %ymm5, %ymm3 +0x8f,0xe9,0x78,0x95,0xd1 = vpshlw %xmm0, %xmm1, %xmm2 +0x8f,0xe9,0xf0,0x95,0x10 = vpshlw (%rax), %xmm1, %xmm2 +0x8f,0xe9,0x78,0x95,0x14,0x08 = vpshlw %xmm0, (%rax, %rcx), %xmm2 +0x8f,0xe9,0x68,0x97,0xf4 = vpshlq %xmm2, %xmm4, %xmm6 +0x8f,0xe9,0xe8,0x97,0x09 = vpshlq (%rcx), %xmm2, %xmm1 +0x8f,0xe9,0x50,0x97,0x34,0x0a = vpshlq %xmm5, (%rdx, %rcx), %xmm6 +0x8f,0xe9,0x40,0x96,0xdd = vpshld %xmm7, %xmm5, %xmm3 +0x8f,0xe9,0xe0,0x96,0x58,0x04 = vpshld 4(%rax), %xmm3, %xmm3 +0x8f,0xe9,0x70,0x96,0x2c,0x08 = vpshld %xmm1, (%rax, %rcx), %xmm5 +0x8f,0xe9,0x70,0x94,0xda = vpshlb %xmm1, %xmm2, %xmm3 +0x8f,0xe9,0xf8,0x94,0x39 = vpshlb (%rcx), %xmm0, %xmm7 +0x8f,0xe9,0x68,0x94,0x1c,0x10 = vpshlb %xmm2, (%rax, %rdx), %xmm3 +0x8f,0xe9,0x40,0x99,0xdd = vpshaw %xmm7, %xmm5, %xmm3 +0x8f,0xe9,0xe8,0x99,0x08 = vpshaw (%rax), %xmm2, %xmm1 +0x8f,0xe9,0x78,0x99,0x5c,0x08,0x08 = vpshaw %xmm0, 8(%rax, %rcx), %xmm3 +0x8f,0xe9,0x58,0x9b,0xe4 = vpshaq %xmm4, %xmm4, %xmm4 +0x8f,0xe9,0xe8,0x9b,0x01 = vpshaq (%rcx), %xmm2, %xmm0 +0x8f,0xe9,0x48,0x9b,0x2c,0x08 = vpshaq %xmm6, (%rax, %rcx), %xmm5 +0x8f,0xe9,0x50,0x9a,0xc4 = vpshad %xmm5, %xmm4, %xmm0 +0x8f,0xe9,0xe8,0x9a,0x28 = vpshad (%rax), %xmm2, %xmm5 +0x8f,0xe9,0x68,0x9a,0x28 = vpshad %xmm2, (%rax), %xmm5 +0x8f,0xe9,0x70,0x98,0xc1 = vpshab %xmm1, %xmm1, %xmm0 +0x8f,0xe9,0xd8,0x98,0x01 = vpshab (%rcx), %xmm4, %xmm0 +0x8f,0xe9,0x50,0x98,0x19 = vpshab %xmm5, (%rcx), %xmm3 +0x8f,0xe9,0xe0,0x91,0x30 = vprotw (%rax), %xmm3, %xmm6 +0x8f,0xe9,0x50,0x91,0x0c,0x08 = vprotw %xmm5, (%rax, %rcx), %xmm1 +0x8f,0xe9,0x78,0x91,0xd1 = vprotw %xmm0, %xmm1, %xmm2 +0x8f,0xe8,0x78,0xc1,0x09,0x2a = vprotw $42, (%rcx), %xmm1 +0x8f,0xe8,0x78,0xc1,0x20,0x29 = vprotw $41, (%rax), %xmm4 +0x8f,0xe8,0x78,0xc1,0xd9,0x28 = vprotw $40, %xmm1, %xmm3 +0x8f,0xe9,0xf0,0x93,0x10 = vprotq (%rax), %xmm1, %xmm2 +0x8f,0xe9,0xf0,0x93,0x14,0x08 = vprotq (%rax, %rcx), %xmm1, %xmm2 +0x8f,0xe9,0x78,0x93,0xd1 = vprotq %xmm0, %xmm1, %xmm2 +0x8f,0xe8,0x78,0xc3,0x10,0x2a = vprotq $42, (%rax), %xmm2 +0x8f,0xe8,0x78,0xc3,0x14,0x08,0x2a = vprotq $42, (%rax, %rcx), %xmm2 +0x8f,0xe8,0x78,0xc3,0xd1,0x2a = vprotq $42, %xmm1, %xmm2 +0x8f,0xe9,0xf8,0x92,0x18 = vprotd (%rax), %xmm0, %xmm3 +0x8f,0xe9,0x68,0x92,0x24,0x08 = vprotd %xmm2, (%rax, %rcx), %xmm4 +0x8f,0xe9,0x50,0x92,0xd3 = vprotd %xmm5, %xmm3, %xmm2 +0x8f,0xe8,0x78,0xc2,0x31,0x2b = vprotd $43, (%rcx), %xmm6 +0x8f,0xe8,0x78,0xc2,0x3c,0x08,0x2c = vprotd $44, (%rax, %rcx), %xmm7 +0x8f,0xe8,0x78,0xc2,0xe4,0x2d = vprotd $45, %xmm4, %xmm4 +0x8f,0xe9,0xe8,0x90,0x29 = vprotb (%rcx), %xmm2, %xmm5 +0x8f,0xe9,0x50,0x90,0x24,0x08 = vprotb %xmm5, (%rax, %rcx), %xmm4 +0x8f,0xe9,0x58,0x90,0xd3 = vprotb %xmm4, %xmm3, %xmm2 +0x8f,0xe8,0x78,0xc0,0x18,0x2e = vprotb $46, (%rax), %xmm3 +0x8f,0xe8,0x78,0xc0,0x3c,0x08,0x2f = vprotb $47, (%rax, %rcx), %xmm7 +0x8f,0xe8,0x78,0xc0,0xed,0x30 = vprotb $48, %xmm5, %xmm5 +0x8f,0xe8,0x60,0xb6,0xe2,0x10 = vpmadcswd %xmm1, %xmm2, %xmm3, %xmm4 +0x8f,0xe8,0x60,0xb6,0x20,0x10 = vpmadcswd %xmm1, (%rax), %xmm3, %xmm4 +0x8f,0xe8,0x48,0xa6,0xe4,0x10 = vpmadcsswd %xmm1, %xmm4, %xmm6, %xmm4 +0x8f,0xe8,0x60,0xa6,0x24,0x08,0x10 = vpmadcsswd %xmm1, (%rax, %rcx), %xmm3, %xmm4 +0x8f,0xe8,0x50,0x95,0xe2,0x00 = vpmacsww %xmm0, %xmm2, %xmm5, %xmm4 +0x8f,0xe8,0x48,0x95,0x20,0x10 = vpmacsww %xmm1, (%rax), %xmm6, %xmm4 +0x8f,0xe8,0x48,0x96,0xfd,0x40 = vpmacswd %xmm4, %xmm5, %xmm6, %xmm7 +0x8f,0xe8,0x70,0x96,0x10,0x00 = vpmacswd %xmm0, (%rax), %xmm1, %xmm2 +0x8f,0xe8,0x68,0x85,0xcb,0x40 = vpmacssww %xmm4, %xmm3, %xmm2, %xmm1 +0x8f,0xe8,0x40,0x85,0x39,0x60 = vpmacssww %xmm6, (%rcx), %xmm7, %xmm7 +0x8f,0xe8,0x58,0x86,0xd2,0x40 = vpmacsswd %xmm4, %xmm2, %xmm4, %xmm2 +0x8f,0xe8,0x70,0x86,0x44,0x08,0x08,0x00 = vpmacsswd %xmm0, 8(%rax, %rcx), %xmm1, %xmm0 +0x8f,0xe8,0x68,0x87,0xe1,0x10 = vpmacssdql %xmm1, %xmm1, %xmm2, %xmm4 +0x8f,0xe8,0x48,0x87,0x29,0x70 = vpmacssdql %xmm7, (%rcx), %xmm6, %xmm5 +0x8f,0xe8,0x78,0x8f,0xca,0x30 = vpmacssdqh %xmm3, %xmm2, %xmm0, %xmm1 +0x8f,0xe8,0x68,0x8f,0x1c,0x08,0x70 = vpmacssdqh %xmm7, (%rax, %rcx), %xmm2, %xmm3 +0x8f,0xe8,0x60,0x8e,0xea,0x20 = vpmacssdd %xmm2, %xmm2, %xmm3, %xmm5 +0x8f,0xe8,0x70,0x8e,0x10,0x40 = vpmacssdd %xmm4, (%rax), %xmm1, %xmm2 +0x8f,0xe8,0x48,0x97,0xf8,0x30 = vpmacsdql %xmm3, %xmm0, %xmm6, %xmm7 +0x8f,0xe8,0x60,0x97,0x69,0x08,0x50 = vpmacsdql %xmm5, 8(%rcx), %xmm3, %xmm5 +0x8f,0xe8,0x60,0x9f,0xd5,0x70 = vpmacsdqh %xmm7, %xmm5, %xmm3, %xmm2 +0x8f,0xe8,0x68,0x9f,0x40,0x04,0x50 = vpmacsdqh %xmm5, 4(%rax), %xmm2, %xmm0 +0x8f,0xe8,0x58,0x9e,0xd6,0x40 = vpmacsdd %xmm4, %xmm6, %xmm4, %xmm2 +0x8f,0xe8,0x58,0x9e,0x1c,0x08,0x40 = vpmacsdd %xmm4, (%rax, %rcx), %xmm4, %xmm3 +0x8f,0xe8,0x60,0xcd,0xe2,0x2a = vpcomw $42, %xmm2, %xmm3, %xmm4 +0x8f,0xe8,0x60,0xcd,0x20,0x2a = vpcomw $42, (%rax), %xmm3, %xmm4 +0x8f,0xe8,0x60,0xed,0xe9,0x2b = vpcomuw $43, %xmm1, %xmm3, %xmm5 +0x8f,0xe8,0x78,0xed,0x34,0x08,0x2c = vpcomuw $44, (%rax, %rcx), %xmm0, %xmm6 +0x8f,0xe8,0x60,0xef,0xfb,0x2d = vpcomuq $45, %xmm3, %xmm3, %xmm7 +0x8f,0xe8,0x60,0xef,0x08,0x2e = vpcomuq $46, (%rax), %xmm3, %xmm1 +0x8f,0xe8,0x70,0xee,0xd0,0x2f = vpcomud $47, %xmm0, %xmm1, %xmm2 +0x8f,0xe8,0x48,0xee,0x58,0x04,0x30 = vpcomud $48, 4(%rax), %xmm6, %xmm3 +0x8f,0xe8,0x58,0xec,0xeb,0x31 = vpcomub $49, %xmm3, %xmm4, %xmm5 +0x8f,0xe8,0x48,0xec,0x11,0x32 = vpcomub $50, (%rcx), %xmm6, %xmm2 +0x8f,0xe8,0x78,0xcf,0xeb,0x33 = vpcomq $51, %xmm3, %xmm0, %xmm5 +0x8f,0xe8,0x70,0xcf,0x38,0x34 = vpcomq $52, (%rax), %xmm1, %xmm7 +0x8f,0xe8,0x60,0xce,0xc3,0x35 = vpcomd $53, %xmm3, %xmm3, %xmm0 +0x8f,0xe8,0x68,0xce,0x11,0x36 = vpcomd $54, (%rcx), %xmm2, %xmm2 +0x8f,0xe8,0x58,0xcc,0xd6,0x37 = vpcomb $55, %xmm6, %xmm4, %xmm2 +0x8f,0xe8,0x60,0xcc,0x50,0x08,0x38 = vpcomb $56, 8(%rax), %xmm3, %xmm2 +0x8f,0xe8,0x60,0xa3,0xe2,0x10 = vpperm %xmm1, %xmm2, %xmm3, %xmm4 +0x8f,0xe8,0xe0,0xa3,0x20,0x20 = vpperm (%rax), %xmm2, %xmm3, %xmm4 +0x8f,0xe8,0x60,0xa3,0x20,0x10 = vpperm %xmm1, (%rax), %xmm3, %xmm4 +0x8f,0xe8,0x60,0xa2,0xe2,0x10 = vpcmov %xmm1, %xmm2, %xmm3, %xmm4 +0x8f,0xe8,0xe0,0xa2,0x20,0x20 = vpcmov (%rax), %xmm2, %xmm3, %xmm4 +0x8f,0xe8,0x60,0xa2,0x20,0x10 = vpcmov %xmm1, (%rax), %xmm3, %xmm4 +0x8f,0xe8,0x64,0xa2,0xe2,0x10 = vpcmov %ymm1, %ymm2, %ymm3, %ymm4 +0x8f,0xe8,0xe4,0xa2,0x20,0x20 = vpcmov (%rax), %ymm2, %ymm3, %ymm4 +0x8f,0xe8,0x64,0xa2,0x20,0x10 = vpcmov %ymm1, (%rax), %ymm3, %ymm4 +0xc4,0xe3,0x71,0x49,0xfa,0x51 = vpermil2pd $1, %xmm5, %xmm2, %xmm1, %xmm7 +0xc4,0xe3,0xe1,0x49,0x20,0x32 = vpermil2pd $2, (%rax), %xmm3, %xmm3, %xmm4 +0xc4,0xe3,0xdd,0x49,0x70,0x08,0x03 = vpermil2pd $3, 8(%rax), %ymm0, %ymm4, %ymm6 +0xc4,0xe3,0x71,0x49,0x04,0x08,0x30 = vpermil2pd $0, %xmm3, (%rax, %rcx), %xmm1, %xmm0 +0xc4,0xe3,0x65,0x49,0xe2,0x11 = vpermil2pd $1, %ymm1, %ymm2, %ymm3, %ymm4 +0xc4,0xe3,0x65,0x49,0x20,0x12 = vpermil2pd $2, %ymm1, (%rax), %ymm3, %ymm4 +0xc4,0xe3,0x69,0x48,0xcb,0x40 = vpermil2ps $0, %xmm4, %xmm3, %xmm2, %xmm1 +0xc4,0xe3,0xe1,0x48,0x40,0x04,0x21 = vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0 +0xc4,0xe3,0xd5,0x48,0x30,0x12 = vpermil2ps $2, (%rax), %ymm1, %ymm5, %ymm6 +0xc4,0xe3,0x61,0x48,0x20,0x13 = vpermil2ps $3, %xmm1, (%rax), %xmm3, %xmm4 +0xc4,0xe3,0x6d,0x48,0xd4,0x40 = vpermil2ps $0, %ymm4, %ymm4, %ymm2, %ymm2 +0xc4,0xe3,0x75,0x49,0x40,0x04,0x11 = vpermil2pd $1, %ymm1, 4(%rax), %ymm1, %ymm0 diff --git a/thirdparty/capstone/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch b/thirdparty/capstone/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch new file mode 100644 index 0000000..d59b2dc --- /dev/null +++ b/thirdparty/capstone/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch @@ -0,0 +1,250 @@ +# Sets the correct access attributes for register lists of LDM instructions. +# See issue: https://github.com/llvm/llvm-project/issues/62455 + +diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc +index fe71aa54f..a3b04d915 100644 +--- a/arch/ARM/ARMGenCSMappingInsnOp.inc ++++ b/arch/ARM/ARMGenCSMappingInsnOp.inc +@@ -9073,7 +9073,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -9092,7 +9092,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -9108,7 +9108,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -9127,7 +9127,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -9143,7 +9143,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -9162,7 +9162,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -9178,7 +9178,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -9197,7 +9197,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -55518,7 +55518,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -55534,7 +55534,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -55553,7 +55553,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -55574,7 +55574,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -55590,7 +55590,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -55609,7 +55609,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -80998,7 +80998,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -81017,7 +81017,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -81033,7 +81033,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -81052,7 +81052,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -81068,7 +81068,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -81087,7 +81087,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -81103,7 +81103,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -81122,7 +81122,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -82831,7 +82831,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -82850,7 +82850,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -82866,7 +82866,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -82885,7 +82885,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -88945,7 +88945,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } diff --git a/thirdparty/capstone/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch b/thirdparty/capstone/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch new file mode 100644 index 0000000..5c59b0d --- /dev/null +++ b/thirdparty/capstone/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch @@ -0,0 +1,25 @@ +# Sets the correct access attributes for register lists of VSCCLRM instructions. +# See issue: https://github.com/llvm/llvm-project/issues/62455 + +diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc +index a3b04d915..12c9a1f9c 100644 +--- a/arch/ARM/ARMGenCSMappingInsnOp.inc ++++ b/arch/ARM/ARMGenCSMappingInsnOp.inc +@@ -70562,7 +70562,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } +@@ -70575,7 +70575,7 @@ + CS_AC_READ, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ + { CS_OP_IMM, +- CS_AC_READ, ++ CS_AC_WRITE, + { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } } diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86.td new file mode 100644 index 0000000..63c2dc4 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86.td @@ -0,0 +1,1203 @@ +//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This is a target description file for the Intel i386 architecture, referred +// to here as the "X86" architecture. +// +//===----------------------------------------------------------------------===// + +// Get the target-independent interfaces which we are implementing... +// +include "llvm/Target/Target.td" + +//===----------------------------------------------------------------------===// +// X86 Subtarget state +// + +def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", + "64-bit mode (x86_64)">; +def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true", + "32-bit mode (80386)">; +def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true", + "16-bit mode (i8086)">; + +//===----------------------------------------------------------------------===// +// X86 Subtarget features +//===----------------------------------------------------------------------===// + +def FeatureX87 : SubtargetFeature<"x87","HasX87", "true", + "Enable X87 float instructions">; + +def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true", + "Enable NOPL instruction">; + +def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", + "Enable conditional move instructions">; + +def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", + "Support POPCNT instruction">; + +def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true", + "Support fxsave/fxrestore instructions">; + +def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true", + "Support xsave instructions">; + +def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true", + "Support xsaveopt instructions">; + +def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true", + "Support xsavec instructions">; + +def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true", + "Support xsaves instructions">; + +def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", + "Enable SSE instructions", + // SSE codegen depends on cmovs, and all + // SSE1+ processors support them. + [FeatureCMOV]>; +def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", + "Enable SSE2 instructions", + [FeatureSSE1]>; +def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", + "Enable SSE3 instructions", + [FeatureSSE2]>; +def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", + "Enable SSSE3 instructions", + [FeatureSSE3]>; +def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41", + "Enable SSE 4.1 instructions", + [FeatureSSSE3]>; +def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42", + "Enable SSE 4.2 instructions", + [FeatureSSE41]>; +// The MMX subtarget feature is separate from the rest of the SSE features +// because it's important (for odd compatibility reasons) to be able to +// turn it off explicitly while allowing SSE+ to be on. +def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX", + "Enable MMX instructions">; +def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", + "Enable 3DNow! instructions", + [FeatureMMX]>; +def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", + "Enable 3DNow! Athlon instructions", + [Feature3DNow]>; +// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied +// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) +// without disabling 64-bit mode. +def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", + "Support 64-bit instructions", + [FeatureCMOV]>; +def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true", + "64-bit with cmpxchg16b", + [Feature64Bit]>; +def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true", + "SHLD instruction is slow">; +def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true", + "PMULLD instruction is slow">; +// FIXME: This should not apply to CPUs that do not have SSE. +def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", + "IsUAMem16Slow", "true", + "Slow unaligned 16-byte memory access">; +def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32", + "IsUAMem32Slow", "true", + "Slow unaligned 32-byte memory access">; +def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", + "Support SSE 4a instructions", + [FeatureSSE3]>; + +def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", + "Enable AVX instructions", + [FeatureSSE42]>; +def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", + "Enable AVX2 instructions", + [FeatureAVX]>; +def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", + "Enable three-operand fused multiple-add", + [FeatureAVX]>; +def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", + "Support 16-bit floating point conversion instructions", + [FeatureAVX]>; +def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F", + "Enable AVX-512 instructions", + [FeatureAVX2, FeatureFMA, FeatureF16C]>; +def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true", + "Enable AVX-512 Exponential and Reciprocal Instructions", + [FeatureAVX512]>; +def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true", + "Enable AVX-512 Conflict Detection Instructions", + [FeatureAVX512]>; +def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ", + "true", "Enable AVX-512 Population Count Instructions", + [FeatureAVX512]>; +def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true", + "Enable AVX-512 PreFetch Instructions", + [FeatureAVX512]>; +def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1", + "true", + "Prefetch with Intent to Write and T1 Hint">; +def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true", + "Enable AVX-512 Doubleword and Quadword Instructions", + [FeatureAVX512]>; +def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true", + "Enable AVX-512 Byte and Word Instructions", + [FeatureAVX512]>; +def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true", + "Enable AVX-512 Vector Length eXtensions", + [FeatureAVX512]>; +def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true", + "Enable AVX-512 Vector Byte Manipulation Instructions", + [FeatureBWI]>; +def FeatureVBMI2 : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true", + "Enable AVX-512 further Vector Byte Manipulation Instructions", + [FeatureBWI]>; +def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true", + "Enable AVX-512 Integer Fused Multiple-Add", + [FeatureAVX512]>; +def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true", + "Enable protection keys">; +def FeatureVNNI : SubtargetFeature<"avx512vnni", "HasVNNI", "true", + "Enable AVX-512 Vector Neural Network Instructions", + [FeatureAVX512]>; +def FeatureBITALG : SubtargetFeature<"avx512bitalg", "HasBITALG", "true", + "Enable AVX-512 Bit Algorithms", + [FeatureBWI]>; +def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", + "Enable packed carry-less multiplication instructions", + [FeatureSSE2]>; +def FeatureGFNI : SubtargetFeature<"gfni", "HasGFNI", "true", + "Enable Galois Field Arithmetic Instructions", + [FeatureSSE2]>; +def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true", + "Enable vpclmulqdq instructions", + [FeatureAVX, FeaturePCLMUL]>; +def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", + "Enable four-operand fused multiple-add", + [FeatureAVX, FeatureSSE4A]>; +def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", + "Enable XOP instructions", + [FeatureFMA4]>; +def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem", + "HasSSEUnalignedMem", "true", + "Allow unaligned memory operands with SSE instructions">; +def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", + "Enable AES instructions", + [FeatureSSE2]>; +def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true", + "Promote selected AES instructions to AVX512/AVX registers", + [FeatureAVX, FeatureAES]>; +def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", + "Enable TBM instructions">; +def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true", + "Enable LWP instructions">; +def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", + "Support MOVBE instruction">; +def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", + "Support RDRAND instruction">; +def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true", + "Support FS/GS Base instructions">; +def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true", + "Support LZCNT instruction">; +def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true", + "Support BMI instructions">; +def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true", + "Support BMI2 instructions">; +def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true", + "Support RTM instructions">; +def FeatureADX : SubtargetFeature<"adx", "HasADX", "true", + "Support ADX instructions">; +def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true", + "Enable SHA instructions", + [FeatureSSE2]>; +def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true", + "Support CET Shadow-Stack instructions">; +def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", + "Support PRFCHW instructions">; +def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", + "Support RDSEED instruction">; +def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true", + "Support LAHF and SAHF instructions">; +def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true", + "Enable MONITORX/MWAITX timer functionality">; +def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true", + "Enable Cache Line Zero">; +def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true", + "Enable Cache Demote">; +def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true", + "Support ptwrite instruction">; +def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true", + "Support MPX instructions">; +def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", + "Use LEA for adjusting the stack pointer">; +def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb", + "HasSlowDivide32", "true", + "Use 8-bit divide for positive values less than 256">; +def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl", + "HasSlowDivide64", "true", + "Use 32-bit divide for positive values less than 2^32">; +def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", + "PadShortFunctions", "true", + "Pad short functions">; +def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", + "Invalidate Process-Context Identifier">; +def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", + "Enable Software Guard Extensions">; +def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", + "Flush A Cache Line Optimized">; +def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true", + "Cache Line Write Back">; +def FeatureWBNOINVD : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true", + "Write Back No Invalidate">; +def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true", + "Support RDPID instructions">; +def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true", + "Wait and pause enhancements">; +// On some processors, instructions that implicitly take two memory operands are +// slow. In practice, this means that CALL, PUSH, and POP with memory operands +// should be avoided in favor of a MOV + register CALL/PUSH/POP. +def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops", + "SlowTwoMemOps", "true", + "Two memory operand instructions are slow">; +def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", + "LEA instruction needs inputs at AG stage">; +def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", + "LEA instruction with certain arguments is slow">; +def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true", + "LEA instruction with 3 ops or certain registers is slow">; +def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true", + "INC and DEC instructions are slower than ADD and SUB">; +def FeatureSoftFloat + : SubtargetFeature<"soft-float", "UseSoftFloat", "true", + "Use software floating point features.">; +def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt", + "HasPOPCNTFalseDeps", "true", + "POPCNT has a false dependency on dest register">; +def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt", + "HasLZCNTFalseDeps", "true", + "LZCNT/TZCNT have a false dependency on dest register">; +def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true", + "platform configuration instruction">; +// On recent X86 (port bound) processors, its preferable to combine to a single shuffle +// using a variable mask over multiple fixed shuffles. +def FeatureFastVariableShuffle + : SubtargetFeature<"fast-variable-shuffle", + "HasFastVariableShuffle", + "true", "Shuffles with variable masks are fast">; +// On some X86 processors, there is no performance hazard to writing only the +// lower parts of a YMM or ZMM register without clearing the upper part. +def FeatureFastPartialYMMorZMMWrite + : SubtargetFeature<"fast-partial-ymm-or-zmm-write", + "HasFastPartialYMMorZMMWrite", + "true", "Partial writes to YMM/ZMM registers are fast">; +// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency +// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if +// vector FSQRT has higher throughput than the corresponding NR code. +// The idea is that throughput bound code is likely to be vectorized, so for +// vectorized code we should care about the throughput of SQRT operations. +// But if the code is scalar that probably means that the code has some kind of +// dependency and we should care more about reducing the latency. +def FeatureFastScalarFSQRT + : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT", + "true", "Scalar SQRT is fast (disable Newton-Raphson)">; +def FeatureFastVectorFSQRT + : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT", + "true", "Vector SQRT is fast (disable Newton-Raphson)">; +// If lzcnt has equivalent latency/throughput to most simple integer ops, it can +// be used to replace test/set sequences. +def FeatureFastLZCNT + : SubtargetFeature< + "fast-lzcnt", "HasFastLZCNT", "true", + "LZCNT instructions are as fast as most simple integer ops">; +// If the target can efficiently decode NOPs upto 11-bytes in length. +def FeatureFast11ByteNOP + : SubtargetFeature< + "fast-11bytenop", "HasFast11ByteNOP", "true", + "Target can quickly decode up to 11 byte NOPs">; +// If the target can efficiently decode NOPs upto 15-bytes in length. +def FeatureFast15ByteNOP + : SubtargetFeature< + "fast-15bytenop", "HasFast15ByteNOP", "true", + "Target can quickly decode up to 15 byte NOPs">; +// Sandy Bridge and newer processors can use SHLD with the same source on both +// inputs to implement rotate to avoid the partial flag update of the normal +// rotate instructions. +def FeatureFastSHLDRotate + : SubtargetFeature< + "fast-shld-rotate", "HasFastSHLDRotate", "true", + "SHLD can be used as a faster rotate">; + +// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka +// "string operations"). See "REP String Enhancement" in the Intel Software +// Development Manual. This feature essentially means that REP MOVSB will copy +// using the largest available size instead of copying bytes one by one, making +// it at least as fast as REPMOVS{W,D,Q}. +def FeatureERMSB + : SubtargetFeature< + "ermsb", "HasERMSB", "true", + "REP MOVS/STOS are fast">; + +// Sandy Bridge and newer processors have many instructions that can be +// fused with conditional branches and pass through the CPU as a single +// operation. +def FeatureMacroFusion + : SubtargetFeature<"macrofusion", "HasMacroFusion", "true", + "Various instructions can be fused with conditional branches">; + +// Gather is available since Haswell (AVX2 set). So technically, we can +// generate Gathers on all AVX2 processors. But the overhead on HSW is high. +// Skylake Client processor has faster Gathers than HSW and performance is +// similar to Skylake Server (AVX-512). +def FeatureHasFastGather + : SubtargetFeature<"fast-gather", "HasFastGather", "true", + "Indicates if gather is reasonably fast.">; + +def FeaturePrefer256Bit + : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true", + "Prefer 256-bit AVX instructions">; + +// Enable mitigation of some aspects of speculative execution related +// vulnerabilities by removing speculatable indirect branches. This disables +// jump-table formation, rewrites explicit `indirectbr` instructions into +// `switch` instructions, and uses a special construct called a "retpoline" to +// prevent speculation of the remaining indirect branches (indirect calls and +// tail calls). +def FeatureRetpoline + : SubtargetFeature<"retpoline", "UseRetpoline", "true", + "Remove speculation of indirect branches from the " + "generated code, either by avoiding them entirely or " + "lowering them with a speculation blocking construct.">; + +// Rely on external thunks for the emitted retpoline calls. This allows users +// to provide their own custom thunk definitions in highly specialized +// environments such as a kernel that does boot-time hot patching. +def FeatureRetpolineExternalThunk + : SubtargetFeature< + "retpoline-external-thunk", "UseRetpolineExternalThunk", "true", + "Enable retpoline, but with an externally provided thunk.", + [FeatureRetpoline]>; + +// Direct Move instructions. +def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true", + "Support movdiri instruction">; +def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true", + "Support movdir64b instruction">; + +//===----------------------------------------------------------------------===// +// Register File Description +//===----------------------------------------------------------------------===// + +include "X86RegisterInfo.td" +include "X86RegisterBanks.td" + +//===----------------------------------------------------------------------===// +// Instruction Descriptions +//===----------------------------------------------------------------------===// + +include "X86Schedule.td" +include "X86InstrInfo.td" +include "X86SchedPredicates.td" + +def X86InstrInfo : InstrInfo; + +//===----------------------------------------------------------------------===// +// X86 processors supported. +//===----------------------------------------------------------------------===// + +include "X86ScheduleAtom.td" +include "X86SchedSandyBridge.td" +include "X86SchedHaswell.td" +include "X86SchedBroadwell.td" +include "X86ScheduleSLM.td" +include "X86ScheduleZnver1.td" +include "X86ScheduleBtVer2.td" +include "X86SchedSkylakeClient.td" +include "X86SchedSkylakeServer.td" + +def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom", + "Intel Atom processors">; +def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM", + "Intel Silvermont processors">; +def ProcIntelGLM : SubtargetFeature<"glm", "X86ProcFamily", "IntelGLM", + "Intel Goldmont processors">; +def ProcIntelGLP : SubtargetFeature<"glp", "X86ProcFamily", "IntelGLP", + "Intel Goldmont Plus processors">; +def ProcIntelTRM : SubtargetFeature<"tremont", "X86ProcFamily", "IntelTRM", + "Intel Tremont processors">; +def ProcIntelHSW : SubtargetFeature<"haswell", "X86ProcFamily", + "IntelHaswell", "Intel Haswell processors">; +def ProcIntelBDW : SubtargetFeature<"broadwell", "X86ProcFamily", + "IntelBroadwell", "Intel Broadwell processors">; +def ProcIntelSKL : SubtargetFeature<"skylake", "X86ProcFamily", + "IntelSkylake", "Intel Skylake processors">; +def ProcIntelKNL : SubtargetFeature<"knl", "X86ProcFamily", + "IntelKNL", "Intel Knights Landing processors">; +def ProcIntelSKX : SubtargetFeature<"skx", "X86ProcFamily", + "IntelSKX", "Intel Skylake Server processors">; +def ProcIntelCNL : SubtargetFeature<"cannonlake", "X86ProcFamily", + "IntelCannonlake", "Intel Cannonlake processors">; +def ProcIntelICL : SubtargetFeature<"icelake-client", "X86ProcFamily", + "IntelIcelakeClient", "Intel Icelake processors">; +def ProcIntelICX : SubtargetFeature<"icelake-server", "X86ProcFamily", + "IntelIcelakeServer", "Intel Icelake Server processors">; + +class Proc Features> + : ProcessorModel; + +def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; + +def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>; +def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV, + FeatureNOPL]>; + +def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureCMOV, FeatureFXSR, FeatureNOPL]>; + +foreach P = ["pentium3", "pentium3m"] in { + def : Proc; +} + +// Enable the PostRAScheduler for SSE2 and SSE3 class cpus. +// The intent is to enable it for pentium4 which is the current default +// processor in a vanilla 32-bit clang compilation when no specific +// architecture is specified. This generally gives a nice performance +// increase on silvermont, with largely neutral behavior on other +// contemporary large core processors. +// pentium-m, pentium4m, prescott and nocona are included as a preventative +// measure to avoid performance surprises, in case clang's default cpu +// changes slightly. + +def : ProcessorModel<"pentium-m", GenericPostRAModel, + [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureSSE2, FeatureFXSR, FeatureNOPL]>; + +foreach P = ["pentium4", "pentium4m"] in { + def : ProcessorModel; +} + +// Intel Quark. +def : Proc<"lakemont", []>; + +// Intel Core Duo. +def : ProcessorModel<"yonah", SandyBridgeModel, + [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, + FeatureFXSR, FeatureNOPL]>; + +// NetBurst. +def : ProcessorModel<"prescott", GenericPostRAModel, + [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, + FeatureFXSR, FeatureNOPL]>; +def : ProcessorModel<"nocona", GenericPostRAModel, [ + FeatureX87, + FeatureSlowUAMem16, + FeatureMMX, + FeatureSSE3, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B +]>; + +// Intel Core 2 Solo/Duo. +def : ProcessorModel<"core2", SandyBridgeModel, [ + FeatureX87, + FeatureSlowUAMem16, + FeatureMMX, + FeatureSSSE3, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B, + FeatureLAHFSAHF, + FeatureMacroFusion +]>; +def : ProcessorModel<"penryn", SandyBridgeModel, [ + FeatureX87, + FeatureSlowUAMem16, + FeatureMMX, + FeatureSSE41, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B, + FeatureLAHFSAHF, + FeatureMacroFusion +]>; + +// Atom CPUs. +class BonnellProc : ProcessorModel; +def : BonnellProc<"bonnell">; +def : BonnellProc<"atom">; // Pin the generic name to the baseline. + +class SilvermontProc : ProcessorModel; +def : SilvermontProc<"silvermont">; +def : SilvermontProc<"slm">; // Legacy alias. + +class ProcessorFeatures Inherited, + list NewFeatures> { + list Value = !listconcat(Inherited, NewFeatures); +} + +class ProcModel ProcFeatures, + list OtherFeatures> : + ProcessorModel; + +def GLMFeatures : ProcessorFeatures<[], [ + FeatureX87, + FeatureMMX, + FeatureSSE42, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B, + FeatureMOVBE, + FeaturePOPCNT, + FeaturePCLMUL, + FeatureAES, + FeaturePRFCHW, + FeatureSlowTwoMemOps, + FeatureSlowLEA, + FeatureSlowIncDec, + FeatureLAHFSAHF, + FeatureMPX, + FeatureSHA, + FeatureRDRAND, + FeatureRDSEED, + FeatureXSAVE, + FeatureXSAVEOPT, + FeatureXSAVEC, + FeatureXSAVES, + FeatureCLFLUSHOPT, + FeatureFSGSBase +]>; + +class GoldmontProc : ProcModel; +def : GoldmontProc<"goldmont">; + +def GLPFeatures : ProcessorFeatures; + +class GoldmontPlusProc : ProcModel; +def : GoldmontPlusProc<"goldmont-plus">; + +class TremontProc : ProcModel; +def : TremontProc<"tremont">; + +// "Arrandale" along with corei3 and corei5 +class NehalemProc : ProcessorModel; +def : NehalemProc<"nehalem">; +def : NehalemProc<"corei7">; + +// Westmere is a similar machine to nehalem with some additional features. +// Westmere is the corei3/i5/i7 path from nehalem to sandybridge +class WestmereProc : ProcessorModel; +def : WestmereProc<"westmere">; + +// SSE is not listed here since llvm treats AVX as a reimplementation of SSE, +// rather than a superset. +def SNBFeatures : ProcessorFeatures<[], [ + FeatureX87, + FeatureMMX, + FeatureAVX, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B, + FeaturePOPCNT, + FeatureAES, + FeatureSlowDivide64, + FeaturePCLMUL, + FeatureXSAVE, + FeatureXSAVEOPT, + FeatureLAHFSAHF, + FeatureSlow3OpsLEA, + FeatureFastScalarFSQRT, + FeatureFastSHLDRotate, + FeatureSlowIncDec, + FeatureMacroFusion +]>; + +class SandyBridgeProc : ProcModel; +def : SandyBridgeProc<"sandybridge">; +def : SandyBridgeProc<"corei7-avx">; // Legacy alias. + +def IVBFeatures : ProcessorFeatures; + +class IvyBridgeProc : ProcModel; +def : IvyBridgeProc<"ivybridge">; +def : IvyBridgeProc<"core-avx-i">; // Legacy alias. + +def HSWFeatures : ProcessorFeatures; + +class HaswellProc : ProcModel; +def : HaswellProc<"haswell">; +def : HaswellProc<"core-avx2">; // Legacy alias. + +def BDWFeatures : ProcessorFeatures; +class BroadwellProc : ProcModel; +def : BroadwellProc<"broadwell">; + +def SKLFeatures : ProcessorFeatures; + +class SkylakeClientProc : ProcModel; +def : SkylakeClientProc<"skylake">; + +def KNLFeatures : ProcessorFeatures; + +// FIXME: define KNL model +class KnightsLandingProc : ProcModel; +def : KnightsLandingProc<"knl">; + +class KnightsMillProc : ProcModel; +def : KnightsMillProc<"knm">; // TODO Add AVX5124FMAPS/AVX5124VNNIW features + +def SKXFeatures : ProcessorFeatures; + +class SkylakeServerProc : ProcModel; +def : SkylakeServerProc<"skylake-avx512">; +def : SkylakeServerProc<"skx">; // Legacy alias. + +def CNLFeatures : ProcessorFeatures; + +class CannonlakeProc : ProcModel; +def : CannonlakeProc<"cannonlake">; + +def ICLFeatures : ProcessorFeatures; + +class IcelakeClientProc : ProcModel; +def : IcelakeClientProc<"icelake-client">; + +class IcelakeServerProc : ProcModel; +def : IcelakeServerProc<"icelake-server">; + +// AMD CPUs. + +def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; +def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; +def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; + +foreach P = ["athlon", "athlon-tbird"] in { + def : Proc; +} + +foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in { + def : Proc; +} + +foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in { + def : Proc; +} + +foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in { + def : Proc; +} + +foreach P = ["amdfam10", "barcelona"] in { + def : Proc; +} + +// Bobcat +def : Proc<"btver1", [ + FeatureX87, + FeatureMMX, + FeatureSSSE3, + FeatureSSE4A, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B, + FeaturePRFCHW, + FeatureLZCNT, + FeaturePOPCNT, + FeatureSlowSHLD, + FeatureLAHFSAHF, + FeatureFast15ByteNOP +]>; + +// Jaguar +def : ProcessorModel<"btver2", BtVer2Model, [ + FeatureX87, + FeatureMMX, + FeatureAVX, + FeatureFXSR, + FeatureNOPL, + FeatureSSE4A, + FeatureCMPXCHG16B, + FeaturePRFCHW, + FeatureAES, + FeaturePCLMUL, + FeatureBMI, + FeatureF16C, + FeatureMOVBE, + FeatureLZCNT, + FeatureFastLZCNT, + FeaturePOPCNT, + FeatureXSAVE, + FeatureXSAVEOPT, + FeatureSlowSHLD, + FeatureLAHFSAHF, + FeatureFast15ByteNOP, + FeatureFastPartialYMMorZMMWrite +]>; + +// Bulldozer +def : Proc<"bdver1", [ + FeatureX87, + FeatureXOP, + FeatureFMA4, + FeatureCMPXCHG16B, + FeatureAES, + FeaturePRFCHW, + FeaturePCLMUL, + FeatureMMX, + FeatureAVX, + FeatureFXSR, + FeatureNOPL, + FeatureSSE4A, + FeatureLZCNT, + FeaturePOPCNT, + FeatureXSAVE, + FeatureLWP, + FeatureSlowSHLD, + FeatureLAHFSAHF, + FeatureFast11ByteNOP, + FeatureMacroFusion +]>; +// Piledriver +def : Proc<"bdver2", [ + FeatureX87, + FeatureXOP, + FeatureFMA4, + FeatureCMPXCHG16B, + FeatureAES, + FeaturePRFCHW, + FeaturePCLMUL, + FeatureMMX, + FeatureAVX, + FeatureFXSR, + FeatureNOPL, + FeatureSSE4A, + FeatureF16C, + FeatureLZCNT, + FeaturePOPCNT, + FeatureXSAVE, + FeatureBMI, + FeatureTBM, + FeatureLWP, + FeatureFMA, + FeatureSlowSHLD, + FeatureLAHFSAHF, + FeatureFast11ByteNOP, + FeatureMacroFusion +]>; + +// Steamroller +def : Proc<"bdver3", [ + FeatureX87, + FeatureXOP, + FeatureFMA4, + FeatureCMPXCHG16B, + FeatureAES, + FeaturePRFCHW, + FeaturePCLMUL, + FeatureMMX, + FeatureAVX, + FeatureFXSR, + FeatureNOPL, + FeatureSSE4A, + FeatureF16C, + FeatureLZCNT, + FeaturePOPCNT, + FeatureXSAVE, + FeatureBMI, + FeatureTBM, + FeatureLWP, + FeatureFMA, + FeatureXSAVEOPT, + FeatureSlowSHLD, + FeatureFSGSBase, + FeatureLAHFSAHF, + FeatureFast11ByteNOP, + FeatureMacroFusion +]>; + +// Excavator +def : Proc<"bdver4", [ + FeatureX87, + FeatureMMX, + FeatureAVX2, + FeatureFXSR, + FeatureNOPL, + FeatureXOP, + FeatureFMA4, + FeatureCMPXCHG16B, + FeatureAES, + FeaturePRFCHW, + FeaturePCLMUL, + FeatureF16C, + FeatureLZCNT, + FeaturePOPCNT, + FeatureXSAVE, + FeatureBMI, + FeatureBMI2, + FeatureTBM, + FeatureLWP, + FeatureFMA, + FeatureXSAVEOPT, + FeatureSlowSHLD, + FeatureFSGSBase, + FeatureLAHFSAHF, + FeatureFast11ByteNOP, + FeatureMWAITX, + FeatureMacroFusion +]>; + +// Znver1 +def: ProcessorModel<"znver1", Znver1Model, [ + FeatureADX, + FeatureAES, + FeatureAVX2, + FeatureBMI, + FeatureBMI2, + FeatureCLFLUSHOPT, + FeatureCLZERO, + FeatureCMPXCHG16B, + FeatureF16C, + FeatureFMA, + FeatureFSGSBase, + FeatureFXSR, + FeatureNOPL, + FeatureFastLZCNT, + FeatureLAHFSAHF, + FeatureLZCNT, + FeatureFast15ByteNOP, + FeatureMacroFusion, + FeatureMMX, + FeatureMOVBE, + FeatureMWAITX, + FeaturePCLMUL, + FeaturePOPCNT, + FeaturePRFCHW, + FeatureRDRAND, + FeatureRDSEED, + FeatureSHA, + FeatureSSE4A, + FeatureSlowSHLD, + FeatureX87, + FeatureXSAVE, + FeatureXSAVEC, + FeatureXSAVEOPT, + FeatureXSAVES]>; + +def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>; + +def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; +def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; +def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; +def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureSSE1, FeatureFXSR]>; + +// We also provide a generic 64-bit specific x86 processor model which tries to +// be good for modern chips without enabling instruction set encodings past the +// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and +// modern 64-bit x86 chip, and enables features that are generally beneficial. +// +// We currently use the Sandy Bridge model as the default scheduling model as +// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which +// covers a huge swath of x86 processors. If there are specific scheduling +// knobs which need to be tuned differently for AMD chips, we might consider +// forming a common base for them. +def : ProcessorModel<"x86-64", SandyBridgeModel, [ + FeatureX87, + FeatureMMX, + FeatureSSE2, + FeatureFXSR, + FeatureNOPL, + Feature64Bit, + FeatureSlow3OpsLEA, + FeatureSlowIncDec, + FeatureMacroFusion +]>; + +//===----------------------------------------------------------------------===// +// Calling Conventions +//===----------------------------------------------------------------------===// + +include "X86CallingConv.td" + + +//===----------------------------------------------------------------------===// +// Assembly Parser +//===----------------------------------------------------------------------===// + +def ATTAsmParserVariant : AsmParserVariant { + int Variant = 0; + + // Variant name. + string Name = "att"; + + // Discard comments in assembly strings. + string CommentDelimiter = "#"; + + // Recognize hard coded registers. + string RegisterPrefix = "%"; +} + +def IntelAsmParserVariant : AsmParserVariant { + int Variant = 1; + + // Variant name. + string Name = "intel"; + + // Discard comments in assembly strings. + string CommentDelimiter = ";"; + + // Recognize hard coded registers. + string RegisterPrefix = ""; +} + +//===----------------------------------------------------------------------===// +// Assembly Printers +//===----------------------------------------------------------------------===// + +// The X86 target supports two different syntaxes for emitting machine code. +// This is controlled by the -x86-asm-syntax={att|intel} +def ATTAsmWriter : AsmWriter { + string AsmWriterClassName = "ATTInstPrinter"; + int Variant = 0; +} +def IntelAsmWriter : AsmWriter { + string AsmWriterClassName = "IntelInstPrinter"; + int Variant = 1; +} + +def X86 : Target { + // Information about the instructions... + let InstructionSet = X86InstrInfo; + let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant]; + let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; + let AllowRegisterRenaming = 1; +} + +//===----------------------------------------------------------------------===// +// Pfm Counters +//===----------------------------------------------------------------------===// + +include "X86PfmCounters.td" diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86CallingConv.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86CallingConv.td new file mode 100644 index 0000000..fcc9a29 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86CallingConv.td @@ -0,0 +1,1150 @@ +//===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This describes the calling conventions for the X86-32 and X86-64 +// architectures. +// +//===----------------------------------------------------------------------===// + +/// CCIfSubtarget - Match if the current subtarget has a feature F. +class CCIfSubtarget + : CCIf" + "(State.getMachineFunction().getSubtarget()).", F), + A>; + +/// CCIfNotSubtarget - Match if the current subtarget doesn't has a feature F. +class CCIfNotSubtarget + : CCIf" + "(State.getMachineFunction().getSubtarget()).", F), + A>; + +// Register classes for RegCall +class RC_X86_RegCall { + list GPR_8 = []; + list GPR_16 = []; + list GPR_32 = []; + list GPR_64 = []; + list FP_CALL = [FP0]; + list FP_RET = [FP0, FP1]; + list XMM = []; + list YMM = []; + list ZMM = []; +} + +// RegCall register classes for 32 bits +def RC_X86_32_RegCall : RC_X86_RegCall { + let GPR_8 = [AL, CL, DL, DIL, SIL]; + let GPR_16 = [AX, CX, DX, DI, SI]; + let GPR_32 = [EAX, ECX, EDX, EDI, ESI]; + let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle [] + ///< \todo Fix AssignToReg to enable empty lists + let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]; + let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7]; + let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]; +} + +class RC_X86_64_RegCall : RC_X86_RegCall { + let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, + XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]; + let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, + YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15]; + let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, + ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15]; +} + +def RC_X86_64_RegCall_Win : RC_X86_64_RegCall { + let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B]; + let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W]; + let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D]; + let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15]; +} + +def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall { + let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B]; + let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W]; + let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D]; + let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15]; +} + +// X86-64 Intel regcall calling convention. +multiclass X86_RegCall_base { +def CC_#NAME : CallingConv<[ + // Handles byval parameters. + CCIfSubtarget<"is64Bit()", CCIfByVal>>, + CCIfByVal>, + + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + // Promote v8i1/v16i1/v32i1 arguments to i32. + CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType>, + + // bool, char, int, enum, long, pointer --> GPR + CCIfType<[i32], CCAssignToReg>, + + // long long, __int64 --> GPR + CCIfType<[i64], CCAssignToReg>, + + // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) + CCIfType<[v64i1], CCPromoteToType>, + CCIfSubtarget<"is64Bit()", CCIfType<[i64], + CCAssignToReg>>, + CCIfSubtarget<"is32Bit()", CCIfType<[i64], + CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, + + // float, double, float128 --> XMM + // In the case of SSE disabled --> save to stack + CCIfType<[f32, f64, f128], + CCIfSubtarget<"hasSSE1()", CCAssignToReg>>, + + // long double --> FP + CCIfType<[f80], CCAssignToReg>, + + // __m128, __m128i, __m128d --> XMM + // In the case of SSE disabled --> save to stack + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCIfSubtarget<"hasSSE1()", CCAssignToReg>>, + + // __m256, __m256i, __m256d --> YMM + // In the case of SSE disabled --> save to stack + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCIfSubtarget<"hasAVX()", CCAssignToReg>>, + + // __m512, __m512i, __m512d --> ZMM + // In the case of SSE disabled --> save to stack + CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], + CCIfSubtarget<"hasAVX512()",CCAssignToReg>>, + + // If no register was found -> assign to stack + + // In 64 bit, assign 64/32 bit values to 8 byte stack + CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64], + CCAssignToStack<8, 8>>>, + + // In 32 bit, assign 64/32 bit values to 8/4 byte stack + CCIfType<[i32, f32], CCAssignToStack<4, 4>>, + CCIfType<[i64, f64], CCAssignToStack<8, 4>>, + + // MMX type gets 8 byte slot in stack , while alignment depends on target + CCIfSubtarget<"is64Bit()", CCIfType<[x86mmx], CCAssignToStack<8, 8>>>, + CCIfType<[x86mmx], CCAssignToStack<8, 4>>, + + // float 128 get stack slots whose size and alignment depends + // on the subtarget. + CCIfType<[f80, f128], CCAssignToStack<0, 0>>, + + // Vectors get 16-byte stack slots that are 16-byte aligned. + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCAssignToStack<16, 16>>, + + // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCAssignToStack<32, 32>>, + + // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. + CCIfType<[v16i32, v8i64, v16f32, v8f64], CCAssignToStack<64, 64>> +]>; + +def RetCC_#NAME : CallingConv<[ + // Promote i1, v1i1, v8i1 arguments to i8. + CCIfType<[i1, v1i1, v8i1], CCPromoteToType>, + + // Promote v16i1 arguments to i16. + CCIfType<[v16i1], CCPromoteToType>, + + // Promote v32i1 arguments to i32. + CCIfType<[v32i1], CCPromoteToType>, + + // bool, char, int, enum, long, pointer --> GPR + CCIfType<[i8], CCAssignToReg>, + CCIfType<[i16], CCAssignToReg>, + CCIfType<[i32], CCAssignToReg>, + + // long long, __int64 --> GPR + CCIfType<[i64], CCAssignToReg>, + + // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) + CCIfType<[v64i1], CCPromoteToType>, + CCIfSubtarget<"is64Bit()", CCIfType<[i64], + CCAssignToReg>>, + CCIfSubtarget<"is32Bit()", CCIfType<[i64], + CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, + + // long double --> FP + CCIfType<[f80], CCAssignToReg>, + + // float, double, float128 --> XMM + CCIfType<[f32, f64, f128], + CCIfSubtarget<"hasSSE1()", CCAssignToReg>>, + + // __m128, __m128i, __m128d --> XMM + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCIfSubtarget<"hasSSE1()", CCAssignToReg>>, + + // __m256, __m256i, __m256d --> YMM + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCIfSubtarget<"hasAVX()", CCAssignToReg>>, + + // __m512, __m512i, __m512d --> ZMM + CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], + CCIfSubtarget<"hasAVX512()", CCAssignToReg>> +]>; +} + +//===----------------------------------------------------------------------===// +// Return Value Calling Conventions +//===----------------------------------------------------------------------===// + +// Return-value conventions common to all X86 CC's. +def RetCC_X86Common : CallingConv<[ + // Scalar values are returned in AX first, then DX. For i8, the ABI + // requires the values to be in AL and AH, however this code uses AL and DL + // instead. This is because using AH for the second register conflicts with + // the way LLVM does multiple return values -- a return of {i16,i8} would end + // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI + // for functions that return two i8 values are currently expected to pack the + // values into an i16 (which uses AX, and thus AL:AH). + // + // For code that doesn't care about the ABI, we allow returning more than two + // integer values in registers. + CCIfType<[v1i1], CCPromoteToType>, + CCIfType<[i1], CCPromoteToType>, + CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>, + CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, + CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, + CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>, + + // Boolean vectors of AVX-512 are returned in SIMD registers. + // The call from AVX to AVX-512 function should work, + // since the boolean types in AVX/AVX2 are promoted by default. + CCIfType<[v2i1], CCPromoteToType>, + CCIfType<[v4i1], CCPromoteToType>, + CCIfType<[v8i1], CCPromoteToType>, + CCIfType<[v16i1], CCPromoteToType>, + CCIfType<[v32i1], CCPromoteToType>, + CCIfType<[v64i1], CCPromoteToType>, + + // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 + // can only be used by ABI non-compliant code. If the target doesn't have XMM + // registers, it won't have vector types. + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, + + // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3 + // can only be used by ABI non-compliant code. This vector type is only + // supported while using the AVX target feature. + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, + + // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3 + // can only be used by ABI non-compliant code. This vector type is only + // supported while using the AVX-512 target feature. + CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], + CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, + + // MMX vector types are always returned in MM0. If the target doesn't have + // MM0, it doesn't support these vector types. + CCIfType<[x86mmx], CCAssignToReg<[MM0]>>, + + // Long double types are always returned in FP0 (even with SSE), + // except on Win64. + CCIfNotSubtarget<"isTargetWin64()", CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>> +]>; + +// X86-32 C return-value convention. +def RetCC_X86_32_C : CallingConv<[ + // The X86-32 calling convention returns FP values in FP0, unless marked + // with "inreg" (used here to distinguish one kind of reg from another, + // weirdly; this is really the sse-regparm calling convention) in which + // case they use XMM0, otherwise it is the same as the common X86 calling + // conv. + CCIfInReg>>>, + CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>, + CCDelegateTo +]>; + +// X86-32 FastCC return-value convention. +def RetCC_X86_32_Fast : CallingConv<[ + // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has + // SSE2. + // This can happen when a float, 2 x float, or 3 x float vector is split by + // target lowering, and is returned in 1-3 sse regs. + CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, + CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, + + // For integers, ECX can be used as an extra return register + CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>, + CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, + CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, + + // Otherwise, it is the same as the common X86 calling convention. + CCDelegateTo +]>; + +// Intel_OCL_BI return-value convention. +def RetCC_Intel_OCL_BI : CallingConv<[ + // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. + CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], + CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, + + // 256-bit FP vectors + // No more than 4 registers + CCIfType<[v8f32, v4f64, v8i32, v4i64], + CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, + + // 512-bit FP vectors + CCIfType<[v16f32, v8f64, v16i32, v8i64], + CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, + + // i32, i64 in the standard way + CCDelegateTo +]>; + +// X86-32 HiPE return-value convention. +def RetCC_X86_32_HiPE : CallingConv<[ + // Promote all types to i32 + CCIfType<[i8, i16], CCPromoteToType>, + + // Return: HP, P, VAL1, VAL2 + CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>> +]>; + +// X86-32 Vectorcall return-value convention. +def RetCC_X86_32_VectorCall : CallingConv<[ + // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3. + CCIfType<[f32, f64, f128], + CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, + + // Return integers in the standard way. + CCDelegateTo +]>; + +// X86-64 C return-value convention. +def RetCC_X86_64_C : CallingConv<[ + // The X86-64 calling convention always returns FP values in XMM0. + CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>, + CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>, + CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>, + + // MMX vector types are always returned in XMM0. + CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>, + + CCIfSwiftError>>, + + CCDelegateTo +]>; + +// X86-Win64 C return-value convention. +def RetCC_X86_Win64_C : CallingConv<[ + // The X86-Win64 calling convention always returns __m64 values in RAX. + CCIfType<[x86mmx], CCBitConvertToType>, + + // Otherwise, everything is the same as 'normal' X86-64 C CC. + CCDelegateTo +]>; + +// X86-64 vectorcall return-value convention. +def RetCC_X86_64_Vectorcall : CallingConv<[ + // Vectorcall calling convention always returns FP values in XMMs. + CCIfType<[f32, f64, f128], + CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, + + // Otherwise, everything is the same as Windows X86-64 C CC. + CCDelegateTo +]>; + +// X86-64 HiPE return-value convention. +def RetCC_X86_64_HiPE : CallingConv<[ + // Promote all types to i64 + CCIfType<[i8, i16, i32], CCPromoteToType>, + + // Return: HP, P, VAL1, VAL2 + CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>> +]>; + +// X86-64 WebKit_JS return-value convention. +def RetCC_X86_64_WebKit_JS : CallingConv<[ + // Promote all types to i64 + CCIfType<[i8, i16, i32], CCPromoteToType>, + + // Return: RAX + CCIfType<[i64], CCAssignToReg<[RAX]>> +]>; + +def RetCC_X86_64_Swift : CallingConv<[ + + CCIfSwiftError>>, + + // For integers, ECX, R8D can be used as extra return registers. + CCIfType<[v1i1], CCPromoteToType>, + CCIfType<[i1], CCPromoteToType>, + CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>, + CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>, + CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>, + CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>, + + // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values. + CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, + CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, + CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, + + // MMX vector types are returned in XMM0, XMM1, XMM2 and XMM3. + CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, + CCDelegateTo +]>; + +// X86-64 AnyReg return-value convention. No explicit register is specified for +// the return-value. The register allocator is allowed and expected to choose +// any free register. +// +// This calling convention is currently only supported by the stackmap and +// patchpoint intrinsics. All other uses will result in an assert on Debug +// builds. On Release builds we fallback to the X86 C calling convention. +def RetCC_X86_64_AnyReg : CallingConv<[ + CCCustom<"CC_X86_AnyReg_Error"> +]>; + +// X86-64 HHVM return-value convention. +def RetCC_X86_64_HHVM: CallingConv<[ + // Promote all types to i64 + CCIfType<[i8, i16, i32], CCPromoteToType>, + + // Return: could return in any GP register save RSP and R12. + CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9, + RAX, R10, R11, R13, R14, R15]>> +]>; + + +defm X86_32_RegCall : + X86_RegCall_base; +defm X86_Win64_RegCall : + X86_RegCall_base; +defm X86_SysV64_RegCall : + X86_RegCall_base; + +// This is the root return-value convention for the X86-32 backend. +def RetCC_X86_32 : CallingConv<[ + // If FastCC, use RetCC_X86_32_Fast. + CCIfCC<"CallingConv::Fast", CCDelegateTo>, + // If HiPE, use RetCC_X86_32_HiPE. + CCIfCC<"CallingConv::HiPE", CCDelegateTo>, + CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo>, + CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo>, + + // Otherwise, use RetCC_X86_32_C. + CCDelegateTo +]>; + +// This is the root return-value convention for the X86-64 backend. +def RetCC_X86_64 : CallingConv<[ + // HiPE uses RetCC_X86_64_HiPE + CCIfCC<"CallingConv::HiPE", CCDelegateTo>, + + // Handle JavaScript calls. + CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo>, + CCIfCC<"CallingConv::AnyReg", CCDelegateTo>, + + // Handle Swift calls. + CCIfCC<"CallingConv::Swift", CCDelegateTo>, + + // Handle explicit CC selection + CCIfCC<"CallingConv::Win64", CCDelegateTo>, + CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo>, + + // Handle Vectorcall CC + CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo>, + + // Handle HHVM calls. + CCIfCC<"CallingConv::HHVM", CCDelegateTo>, + + CCIfCC<"CallingConv::X86_RegCall", + CCIfSubtarget<"isTargetWin64()", + CCDelegateTo>>, + CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo>, + + // Mingw64 and native Win64 use Win64 CC + CCIfSubtarget<"isTargetWin64()", CCDelegateTo>, + + // Otherwise, drop to normal X86-64 CC + CCDelegateTo +]>; + +// This is the return-value convention used for the entire X86 backend. +def RetCC_X86 : CallingConv<[ + + // Check if this is the Intel OpenCL built-ins calling convention + CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo>, + + CCIfSubtarget<"is64Bit()", CCDelegateTo>, + CCDelegateTo +]>; + +//===----------------------------------------------------------------------===// +// X86-64 Argument Calling Conventions +//===----------------------------------------------------------------------===// + +def CC_X86_64_C : CallingConv<[ + // Handles byval parameters. + CCIfByVal>, + + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + // The 'nest' parameter, if any, is passed in R10. + CCIfNest>>, + CCIfNest>, + + // Pass SwiftSelf in a callee saved register. + CCIfSwiftSelf>>, + + // A SwiftError is passed in R12. + CCIfSwiftError>>, + + // For Swift Calling Convention, pass sret in %rax. + CCIfCC<"CallingConv::Swift", + CCIfSRet>>>, + + // The first 6 integer arguments are passed in integer registers. + CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, + CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, + + // The first 8 MMX vector arguments are passed in XMM registers on Darwin. + CCIfType<[x86mmx], + CCIfSubtarget<"isTargetDarwin()", + CCIfSubtarget<"hasSSE2()", + CCPromoteToType>>>, + + // Boolean vectors of AVX-512 are passed in SIMD registers. + // The call from AVX to AVX-512 function should work, + // since the boolean types in AVX/AVX2 are promoted by default. + CCIfType<[v2i1], CCPromoteToType>, + CCIfType<[v4i1], CCPromoteToType>, + CCIfType<[v8i1], CCPromoteToType>, + CCIfType<[v16i1], CCPromoteToType>, + CCIfType<[v32i1], CCPromoteToType>, + CCIfType<[v64i1], CCPromoteToType>, + + // The first 8 FP/Vector arguments are passed in XMM registers. + CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCIfSubtarget<"hasSSE1()", + CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, + + // The first 8 256-bit vector arguments are passed in YMM registers, unless + // this is a vararg function. + // FIXME: This isn't precisely correct; the x86-64 ABI document says that + // fixed arguments to vararg functions are supposed to be passed in + // registers. Actually modeling that would be a lot of work, though. + CCIfNotVarArg>>>, + + // The first 8 512-bit vector arguments are passed in ZMM registers. + CCIfNotVarArg>>>, + + // Integer/FP values get stored in stack slots that are 8 bytes in size and + // 8-byte aligned if there are no more registers to hold them. + CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, + + // Long doubles get stack slots whose size and alignment depends on the + // subtarget. + CCIfType<[f80, f128], CCAssignToStack<0, 0>>, + + // Vectors get 16-byte stack slots that are 16-byte aligned. + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, + + // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCAssignToStack<32, 32>>, + + // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. + CCIfType<[v16i32, v8i64, v16f32, v8f64], + CCAssignToStack<64, 64>> +]>; + +// Calling convention for X86-64 HHVM. +def CC_X86_64_HHVM : CallingConv<[ + // Use all/any GP registers for args, except RSP. + CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15, + RDI, RSI, RDX, RCX, R8, R9, + RAX, R10, R11, R13, R14]>> +]>; + +// Calling convention for helper functions in HHVM. +def CC_X86_64_HHVM_C : CallingConv<[ + // Pass the first argument in RBP. + CCIfType<[i64], CCAssignToReg<[RBP]>>, + + // Otherwise it's the same as the regular C calling convention. + CCDelegateTo +]>; + +// Calling convention used on Win64 +def CC_X86_Win64_C : CallingConv<[ + // FIXME: Handle byval stuff. + // FIXME: Handle varargs. + + // Promote i1/v1i1 arguments to i8. + CCIfType<[i1, v1i1], CCPromoteToType>, + + // The 'nest' parameter, if any, is passed in R10. + CCIfNest>, + + // A SwiftError is passed in R12. + CCIfSwiftError>>, + + // 128 bit vectors are passed by pointer + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect>, + + + // 256 bit vectors are passed by pointer + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect>, + + // 512 bit vectors are passed by pointer + CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect>, + + // Long doubles are passed by pointer + CCIfType<[f80], CCPassIndirect>, + + // The first 4 MMX vector arguments are passed in GPRs. + CCIfType<[x86mmx], CCBitConvertToType>, + + // The first 4 integer arguments are passed in integer registers. + CCIfType<[i8 ], CCAssignToRegWithShadow<[CL , DL , R8B , R9B ], + [XMM0, XMM1, XMM2, XMM3]>>, + CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ], + [XMM0, XMM1, XMM2, XMM3]>>, + CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ], + [XMM0, XMM1, XMM2, XMM3]>>, + + // Do not pass the sret argument in RCX, the Win64 thiscall calling + // convention requires "this" to be passed in RCX. + CCIfCC<"CallingConv::X86_ThisCall", + CCIfSRet>>>, + + CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], + [XMM0, XMM1, XMM2, XMM3]>>, + + // The first 4 FP/Vector arguments are passed in XMM registers. + CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3], + [RCX , RDX , R8 , R9 ]>>, + + // Integer/FP values get stored in stack slots that are 8 bytes in size and + // 8-byte aligned if there are no more registers to hold them. + CCIfType<[i8, i16, i32, i64, f32, f64], CCAssignToStack<8, 8>> +]>; + +def CC_X86_Win64_VectorCall : CallingConv<[ + CCCustom<"CC_X86_64_VectorCall">, + + // Delegate to fastcall to handle integer types. + CCDelegateTo +]>; + + +def CC_X86_64_GHC : CallingConv<[ + // Promote i8/i16/i32 arguments to i64. + CCIfType<[i8, i16, i32], CCPromoteToType>, + + // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim + CCIfType<[i64], + CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>, + + // Pass in STG registers: F1, F2, F3, F4, D1, D2 + CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCIfSubtarget<"hasSSE1()", + CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, + // AVX + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCIfSubtarget<"hasAVX()", + CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>, + // AVX-512 + CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], + CCIfSubtarget<"hasAVX512()", + CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>> +]>; + +def CC_X86_64_HiPE : CallingConv<[ + // Promote i8/i16/i32 arguments to i64. + CCIfType<[i8, i16, i32], CCPromoteToType>, + + // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3 + CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>, + + // Integer/FP values get stored in stack slots that are 8 bytes in size and + // 8-byte aligned if there are no more registers to hold them. + CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>> +]>; + +def CC_X86_64_WebKit_JS : CallingConv<[ + // Promote i8/i16 arguments to i32. + CCIfType<[i8, i16], CCPromoteToType>, + + // Only the first integer argument is passed in register. + CCIfType<[i32], CCAssignToReg<[EAX]>>, + CCIfType<[i64], CCAssignToReg<[RAX]>>, + + // The remaining integer arguments are passed on the stack. 32bit integer and + // floating-point arguments are aligned to 4 byte and stored in 4 byte slots. + // 64bit integer and floating-point arguments are aligned to 8 byte and stored + // in 8 byte stack slots. + CCIfType<[i32, f32], CCAssignToStack<4, 4>>, + CCIfType<[i64, f64], CCAssignToStack<8, 8>> +]>; + +// No explicit register is specified for the AnyReg calling convention. The +// register allocator may assign the arguments to any free register. +// +// This calling convention is currently only supported by the stackmap and +// patchpoint intrinsics. All other uses will result in an assert on Debug +// builds. On Release builds we fallback to the X86 C calling convention. +def CC_X86_64_AnyReg : CallingConv<[ + CCCustom<"CC_X86_AnyReg_Error"> +]>; + +//===----------------------------------------------------------------------===// +// X86 C Calling Convention +//===----------------------------------------------------------------------===// + +/// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector +/// values are spilled on the stack. +def CC_X86_32_Vector_Common : CallingConv<[ + // Other SSE vectors get 16-byte stack slots that are 16-byte aligned. + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, + + // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned. + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCAssignToStack<32, 32>>, + + // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned. + CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], + CCAssignToStack<64, 64>> +]>; + +// CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in +// vector registers +def CC_X86_32_Vector_Standard : CallingConv<[ + // SSE vector arguments are passed in XMM registers. + CCIfNotVarArg>>, + + // AVX 256-bit vector arguments are passed in YMM registers. + CCIfNotVarArg>>>, + + // AVX 512-bit vector arguments are passed in ZMM registers. + CCIfNotVarArg>>, + + CCDelegateTo +]>; + +// CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in +// vector registers. +def CC_X86_32_Vector_Darwin : CallingConv<[ + // SSE vector arguments are passed in XMM registers. + CCIfNotVarArg>>, + + // AVX 256-bit vector arguments are passed in YMM registers. + CCIfNotVarArg>>>, + + // AVX 512-bit vector arguments are passed in ZMM registers. + CCIfNotVarArg>>, + + CCDelegateTo +]>; + +/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP +/// values are spilled on the stack. +def CC_X86_32_Common : CallingConv<[ + // Handles byval parameters. + CCIfByVal>, + + // The first 3 float or double arguments, if marked 'inreg' and if the call + // is not a vararg call and if SSE2 is available, are passed in SSE registers. + CCIfNotVarArg>>>>, + + // The first 3 __m64 vector arguments are passed in mmx registers if the + // call is not a vararg call. + CCIfNotVarArg>>, + + // Integer/Float values get stored in stack slots that are 4 bytes in + // size and 4-byte aligned. + CCIfType<[i32, f32], CCAssignToStack<4, 4>>, + + // Doubles get 8-byte slots that are 4-byte aligned. + CCIfType<[f64], CCAssignToStack<8, 4>>, + + // Long doubles get slots whose size depends on the subtarget. + CCIfType<[f80], CCAssignToStack<0, 4>>, + + // Boolean vectors of AVX-512 are passed in SIMD registers. + // The call from AVX to AVX-512 function should work, + // since the boolean types in AVX/AVX2 are promoted by default. + CCIfType<[v2i1], CCPromoteToType>, + CCIfType<[v4i1], CCPromoteToType>, + CCIfType<[v8i1], CCPromoteToType>, + CCIfType<[v16i1], CCPromoteToType>, + CCIfType<[v32i1], CCPromoteToType>, + CCIfType<[v64i1], CCPromoteToType>, + + // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are + // passed in the parameter area. + CCIfType<[x86mmx], CCAssignToStack<8, 4>>, + + // Darwin passes vectors in a form that differs from the i386 psABI + CCIfSubtarget<"isTargetDarwin()", CCDelegateTo>, + + // Otherwise, drop to 'normal' X86-32 CC + CCDelegateTo +]>; + +def CC_X86_32_C : CallingConv<[ + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + // The 'nest' parameter, if any, is passed in ECX. + CCIfNest>, + + // The first 3 integer arguments, if marked 'inreg' and if the call is not + // a vararg call, are passed in integer registers. + CCIfNotVarArg>>>, + + // Otherwise, same as everything else. + CCDelegateTo +]>; + +def CC_X86_32_MCU : CallingConv<[ + // Handles byval parameters. Note that, like FastCC, we can't rely on + // the delegation to CC_X86_32_Common because that happens after code that + // puts arguments in registers. + CCIfByVal>, + + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + // If the call is not a vararg call, some arguments may be passed + // in integer registers. + CCIfNotVarArg>>, + + // Otherwise, same as everything else. + CCDelegateTo +]>; + +def CC_X86_32_FastCall : CallingConv<[ + // Promote i1 to i8. + CCIfType<[i1], CCPromoteToType>, + + // The 'nest' parameter, if any, is passed in EAX. + CCIfNest>, + + // The first 2 integer arguments are passed in ECX/EDX + CCIfInReg>>, + CCIfInReg>>, + CCIfInReg>>, + + // Otherwise, same as everything else. + CCDelegateTo +]>; + +def CC_X86_Win32_VectorCall : CallingConv<[ + // Pass floating point in XMMs + CCCustom<"CC_X86_32_VectorCall">, + + // Delegate to fastcall to handle integer types. + CCDelegateTo +]>; + +def CC_X86_32_ThisCall_Common : CallingConv<[ + // The first integer argument is passed in ECX + CCIfType<[i32], CCAssignToReg<[ECX]>>, + + // Otherwise, same as everything else. + CCDelegateTo +]>; + +def CC_X86_32_ThisCall_Mingw : CallingConv<[ + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + CCDelegateTo +]>; + +def CC_X86_32_ThisCall_Win : CallingConv<[ + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + // Pass sret arguments indirectly through stack. + CCIfSRet>, + + CCDelegateTo +]>; + +def CC_X86_32_ThisCall : CallingConv<[ + CCIfSubtarget<"isTargetCygMing()", CCDelegateTo>, + CCDelegateTo +]>; + +def CC_X86_32_FastCC : CallingConv<[ + // Handles byval parameters. Note that we can't rely on the delegation + // to CC_X86_32_Common for this because that happens after code that + // puts arguments in registers. + CCIfByVal>, + + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + // The 'nest' parameter, if any, is passed in EAX. + CCIfNest>, + + // The first 2 integer arguments are passed in ECX/EDX + CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>, + + // The first 3 float or double arguments, if the call is not a vararg + // call and if SSE2 is available, are passed in SSE registers. + CCIfNotVarArg>>>, + + // Doubles get 8-byte slots that are 8-byte aligned. + CCIfType<[f64], CCAssignToStack<8, 8>>, + + // Otherwise, same as everything else. + CCDelegateTo +]>; + +def CC_X86_32_GHC : CallingConv<[ + // Promote i8/i16 arguments to i32. + CCIfType<[i8, i16], CCPromoteToType>, + + // Pass in STG registers: Base, Sp, Hp, R1 + CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>> +]>; + +def CC_X86_32_HiPE : CallingConv<[ + // Promote i8/i16 arguments to i32. + CCIfType<[i8, i16], CCPromoteToType>, + + // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2 + CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>, + + // Integer/Float values get stored in stack slots that are 4 bytes in + // size and 4-byte aligned. + CCIfType<[i32, f32], CCAssignToStack<4, 4>> +]>; + +// X86-64 Intel OpenCL built-ins calling convention. +def CC_Intel_OCL_BI : CallingConv<[ + + CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>, + CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>, + + CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>, + CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>, + + CCIfType<[i32], CCAssignToStack<4, 4>>, + + // The SSE vector arguments are passed in XMM registers. + CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], + CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, + + // The 256-bit vector arguments are passed in YMM registers. + CCIfType<[v8f32, v4f64, v8i32, v4i64], + CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>, + + // The 512-bit vector arguments are passed in ZMM registers. + CCIfType<[v16f32, v8f64, v16i32, v8i64], + CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>, + + // Pass masks in mask registers + CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>, + + CCIfSubtarget<"isTargetWin64()", CCDelegateTo>, + CCIfSubtarget<"is64Bit()", CCDelegateTo>, + CCDelegateTo +]>; + +def CC_X86_32_Intr : CallingConv<[ + CCAssignToStack<4, 4> +]>; + +def CC_X86_64_Intr : CallingConv<[ + CCAssignToStack<8, 8> +]>; + +//===----------------------------------------------------------------------===// +// X86 Root Argument Calling Conventions +//===----------------------------------------------------------------------===// + +// This is the root argument convention for the X86-32 backend. +def CC_X86_32 : CallingConv<[ + // X86_INTR calling convention is valid in MCU target and should override the + // MCU calling convention. Thus, this should be checked before isTargetMCU(). + CCIfCC<"CallingConv::X86_INTR", CCDelegateTo>, + CCIfSubtarget<"isTargetMCU()", CCDelegateTo>, + CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo>, + CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo>, + CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo>, + CCIfCC<"CallingConv::Fast", CCDelegateTo>, + CCIfCC<"CallingConv::GHC", CCDelegateTo>, + CCIfCC<"CallingConv::HiPE", CCDelegateTo>, + CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo>, + + // Otherwise, drop to normal X86-32 CC + CCDelegateTo +]>; + +// This is the root argument convention for the X86-64 backend. +def CC_X86_64 : CallingConv<[ + CCIfCC<"CallingConv::GHC", CCDelegateTo>, + CCIfCC<"CallingConv::HiPE", CCDelegateTo>, + CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo>, + CCIfCC<"CallingConv::AnyReg", CCDelegateTo>, + CCIfCC<"CallingConv::Win64", CCDelegateTo>, + CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo>, + CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo>, + CCIfCC<"CallingConv::HHVM", CCDelegateTo>, + CCIfCC<"CallingConv::HHVM_C", CCDelegateTo>, + CCIfCC<"CallingConv::X86_RegCall", + CCIfSubtarget<"isTargetWin64()", CCDelegateTo>>, + CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo>, + CCIfCC<"CallingConv::X86_INTR", CCDelegateTo>, + + // Mingw64 and native Win64 use Win64 CC + CCIfSubtarget<"isTargetWin64()", CCDelegateTo>, + + // Otherwise, drop to normal X86-64 CC + CCDelegateTo +]>; + +// This is the argument convention used for the entire X86 backend. +def CC_X86 : CallingConv<[ + CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo>, + CCIfSubtarget<"is64Bit()", CCDelegateTo>, + CCDelegateTo +]>; + +//===----------------------------------------------------------------------===// +// Callee-saved Registers. +//===----------------------------------------------------------------------===// + +def CSR_NoRegs : CalleeSavedRegs<(add)>; + +def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; +def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>; + +def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>; + +def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>; +def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>; + +def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>; + +def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE, + (sequence "XMM%u", 6, 15))>; + +def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>; + +// The function used by Darwin to obtain the address of a thread-local variable +// uses rdi to pass a single parameter and rax for the return value. All other +// GPRs are preserved. +def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI, + R8, R9, R10, R11)>; + +// CSRs that are handled by prologue, epilogue. +def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>; + +// CSRs that are handled explicitly via copies. +def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>; + +// All GPRs - except r11 +def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI, + R8, R9, R10, RSP)>; + +// All registers - except r11 +def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, + (sequence "XMM%u", 0, 15))>; +def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs, + (sequence "YMM%u", 0, 15))>; + +def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10, + R11, R12, R13, R14, R15, RBP, + (sequence "XMM%u", 0, 15))>; + +def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI, + EDI)>; +def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs, + (sequence "XMM%u", 0, 7))>; +def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs, + (sequence "YMM%u", 0, 7))>; +def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs, + (sequence "ZMM%u", 0, 7), + (sequence "K%u", 0, 7))>; + +def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>; +def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9, + R10, R11, R12, R13, R14, R15, RBP)>; +def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, + (sequence "YMM%u", 0, 15)), + (sequence "XMM%u", 0, 15))>; +def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, + (sequence "ZMM%u", 0, 31), + (sequence "K%u", 0, 7)), + (sequence "XMM%u", 0, 15))>; + +// Standard C + YMM6-15 +def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, + R13, R14, R15, + (sequence "YMM%u", 6, 15))>; + +def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, + R12, R13, R14, R15, + (sequence "ZMM%u", 6, 21), + K4, K5, K6, K7)>; +//Standard C + XMM 8-15 +def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64, + (sequence "XMM%u", 8, 15))>; + +//Standard C + YMM 8-15 +def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64, + (sequence "YMM%u", 8, 15))>; + +def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15, + (sequence "ZMM%u", 16, 31), + K4, K5, K6, K7)>; + +// Only R12 is preserved for PHP calls in HHVM. +def CSR_64_HHVM : CalleeSavedRegs<(add R12)>; + +// Register calling convention preserves few GPR and XMM8-15 +def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP, ESP)>; +def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, + (sequence "XMM%u", 4, 7))>; +def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP, + (sequence "R%u", 10, 15))>; +def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE, + (sequence "XMM%u", 8, 15))>; +def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP, + (sequence "R%u", 12, 15))>; +def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE, + (sequence "XMM%u", 8, 15))>; + diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86Capstone.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86Capstone.td new file mode 100644 index 0000000..ca21b63 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86Capstone.td @@ -0,0 +1,7 @@ +// Capstone definitions fix for X86 LLVM instructions. + +let Defs = [EFLAGS] in + def INT1 : I<0xf1, RawFrm, (outs), (ins), "int1", []>; + +// def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>; +def FSETPM : I<0xDB, MRM_E4, (outs), (ins), "fsetpm", []>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86Instr3DNow.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86Instr3DNow.td new file mode 100644 index 0000000..46dc6bf --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86Instr3DNow.td @@ -0,0 +1,111 @@ +//===-- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the 3DNow! instruction set, which extends MMX to support +// floating point and also adds a few more random instructions for good measure. +// +//===----------------------------------------------------------------------===// + +class I3DNow o, Format F, dag outs, dag ins, string asm, list pat> + : I, Requires<[Has3DNow]> { +} + +class I3DNow_binop o, Format F, dag ins, string Mnemonic, list pat> + : I3DNow, ThreeDNow { + let Constraints = "$src1 = $dst"; +} + +class I3DNow_conv o, Format F, dag ins, string Mnemonic, list pat> + : I3DNow, ThreeDNow; + +multiclass I3DNow_binop_rm_int opc, string Mn, + X86FoldableSchedWrite sched, bit Commutable = 0, + string Ver = ""> { + let isCommutable = Commutable in + def rr : I3DNow_binop( + !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))]>, + Sched<[sched]>; + def rm : I3DNow_binop( + !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, + (bitconvert (load_mmx addr:$src2))))]>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass I3DNow_conv_rm_int opc, string Mn, + X86FoldableSchedWrite sched, string Ver = ""> { + def rr : I3DNow_conv( + !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))]>, + Sched<[sched]>; + def rm : I3DNow_conv( + !strconcat("int_x86_3dnow", Ver, "_", Mn)) + (bitconvert (load_mmx addr:$src))))]>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", SchedWriteVecALU.MMX, 1>; +defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id", WriteCvtPS2I>; +defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc", WriteFAdd>; +defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd", WriteFAdd, 1>; +defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq", WriteFAdd, 1>; +defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge", WriteFAdd>; +defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt", WriteFAdd>; +defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax", WriteFAdd>; +defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin", WriteFAdd>; +defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul", WriteFAdd, 1>; +defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp", WriteFAdd>; +defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1", WriteFAdd>; +defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2", WriteFAdd>; +defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1", WriteFAdd>; +defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt", WriteFAdd>; +defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub", WriteFAdd, 1>; +defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", WriteFAdd, 1>; +defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd", WriteCvtI2PS>; +defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", SchedWriteVecIMul.MMX, 1>; + +let SchedRW = [WriteEMMS] in +def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", + [(int_x86_mmx_femms)]>, TB; + +// PREFETCHWT1 is supported we want to use it for everything but T0. +def PrefetchWLevel : PatFrag<(ops), (i32 imm), [{ + return N->getSExtValue() == 3 || !Subtarget->hasPREFETCHWT1(); +}]>; + +// Use PREFETCHWT1 for NTA, T2, T1. +def PrefetchWT1Level : ImmLeaf; + +let SchedRW = [WriteLoad] in { +let Predicates = [Has3DNow, NoSSEPrefetch] in +def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr), + "prefetch\t$addr", + [(prefetch addr:$addr, imm, imm, (i32 1))]>, TB; + +def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr", + [(prefetch addr:$addr, (i32 1), (i32 PrefetchWLevel), (i32 1))]>, + TB, Requires<[HasPrefetchW]>; + +def PREFETCHWT1 : I<0x0D, MRM2m, (outs), (ins i8mem:$addr), "prefetchwt1\t$addr", + [(prefetch addr:$addr, (i32 1), (i32 PrefetchWT1Level), (i32 1))]>, + TB, Requires<[HasPREFETCHWT1]>; +} + +// "3DNowA" instructions +defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", WriteCvtPS2I, "a">; +defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", WriteCvtI2PS, "a">; +defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", WriteFAdd, 0, "a">; +defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", WriteFAdd, 0, "a">; +defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", SchedWriteShuffle.MMX, "a">; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrAVX512.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrAVX512.td new file mode 100644 index 0000000..3872b12 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrAVX512.td @@ -0,0 +1,11968 @@ +//===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 AVX512 instruction set, defining the +// instructions, and properties of the instructions which are needed for code +// generation, machine code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +// Group template arguments that can be derived from the vector type (EltNum x +// EltVT). These are things like the register class for the writemask, etc. +// The idea is to pass one of these as the template argument rather than the +// individual arguments. +// The template is also used for scalar types, in this case numelts is 1. +class X86VectorVTInfo { + RegisterClass RC = rc; + ValueType EltVT = eltvt; + int NumElts = numelts; + + // Corresponding mask register class. + RegisterClass KRC = !cast("VK" # NumElts); + + // Corresponding write-mask register class. + RegisterClass KRCWM = !cast("VK" # NumElts # "WM"); + + // The mask VT. + ValueType KVT = !cast("v" # NumElts # "i1"); + + // Suffix used in the instruction mnemonic. + string Suffix = suffix; + + // VTName is a string name for vector VT. For vector types it will be + // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32 + // It is a little bit complex for scalar types, where NumElts = 1. + // In this case we build v4f32 or v2f64 + string VTName = "v" # !if (!eq (NumElts, 1), + !if (!eq (EltVT.Size, 32), 4, + !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT; + + // The vector VT. + ValueType VT = !cast(VTName); + + string EltTypeName = !cast(EltVT); + // Size of the element type in bits, e.g. 32 for v16i32. + string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName)); + int EltSize = EltVT.Size; + + // "i" for integer types and "f" for floating-point types + string TypeVariantName = !subst(EltSizeName, "", EltTypeName); + + // Size of RC in bits, e.g. 512 for VR512. + int Size = VT.Size; + + // The corresponding memory operand, e.g. i512mem for VR512. + X86MemOperand MemOp = !cast(TypeVariantName # Size # "mem"); + X86MemOperand ScalarMemOp = !cast(EltVT # "mem"); + // FP scalar memory operand for intrinsics - ssmem/sdmem. + Operand IntScalarMemOp = !if (!eq (EltTypeName, "f32"), !cast("ssmem"), + !if (!eq (EltTypeName, "f64"), !cast("sdmem"), ?)); + + // Load patterns + // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64 + // due to load promotion during legalization + PatFrag LdFrag = !cast("load" # + !if (!eq (TypeVariantName, "i"), + !if (!eq (Size, 128), "v2i64", + !if (!eq (Size, 256), "v4i64", + !if (!eq (Size, 512), "v8i64", + VTName))), VTName)); + + PatFrag AlignedLdFrag = !cast("alignedload" # + !if (!eq (TypeVariantName, "i"), + !if (!eq (Size, 128), "v2i64", + !if (!eq (Size, 256), "v4i64", + !if (!eq (Size, 512), "v8i64", + VTName))), VTName)); + + PatFrag ScalarLdFrag = !cast("load" # EltVT); + + ComplexPattern ScalarIntMemCPat = !if (!eq (EltTypeName, "f32"), + !cast("sse_load_f32"), + !if (!eq (EltTypeName, "f64"), + !cast("sse_load_f64"), + ?)); + + // The string to specify embedded broadcast in assembly. + string BroadcastStr = "{1to" # NumElts # "}"; + + // 8-bit compressed displacement tuple/subvector format. This is only + // defined for NumElts <= 8. + CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0), + !cast("CD8VT" # NumElts), ?); + + SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm, + !if (!eq (Size, 256), sub_ymm, ?)); + + Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle, + !if (!eq (EltTypeName, "f64"), SSEPackedDouble, + SSEPackedInt)); + + RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X); + + // A vector type of the same width with element type i64. This is used to + // create patterns for logic ops. + ValueType i64VT = !cast("v" # !srl(Size, 6) # "i64"); + + // A vector type of the same width with element type i32. This is used to + // create the canonical constant zero node ImmAllZerosV. + ValueType i32VT = !cast("v" # !srl(Size, 5) # "i32"); + dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV))); + + string ZSuffix = !if (!eq (Size, 128), "Z128", + !if (!eq (Size, 256), "Z256", "Z")); +} + +def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">; +def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">; +def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">; +def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">; +def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">; +def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">; + +// "x" in v32i8x_info means RC = VR256X +def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">; +def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">; +def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">; +def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">; +def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">; +def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">; + +def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">; +def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">; +def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">; +def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">; +def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">; +def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">; + +// We map scalar types to the smallest (128-bit) vector type +// with the appropriate element type. This allows to use the same masking logic. +def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">; +def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">; +def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">; +def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">; + +class AVX512VLVectorVTInfo { + X86VectorVTInfo info512 = i512; + X86VectorVTInfo info256 = i256; + X86VectorVTInfo info128 = i128; +} + +def avx512vl_i8_info : AVX512VLVectorVTInfo; +def avx512vl_i16_info : AVX512VLVectorVTInfo; +def avx512vl_i32_info : AVX512VLVectorVTInfo; +def avx512vl_i64_info : AVX512VLVectorVTInfo; +def avx512vl_f32_info : AVX512VLVectorVTInfo; +def avx512vl_f64_info : AVX512VLVectorVTInfo; + +class X86KVectorVTInfo { + RegisterClass KRC = _krc; + RegisterClass KRCWM = _krcwm; + ValueType KVT = _vt; +} + +def v1i1_info : X86KVectorVTInfo; +def v2i1_info : X86KVectorVTInfo; +def v4i1_info : X86KVectorVTInfo; +def v8i1_info : X86KVectorVTInfo; +def v16i1_info : X86KVectorVTInfo; +def v32i1_info : X86KVectorVTInfo; +def v64i1_info : X86KVectorVTInfo; + +// This multiclass generates the masking variants from the non-masking +// variant. It only provides the assembly pieces for the masking variants. +// It assumes custom ISel patterns for masking which can be provided as +// template arguments. +multiclass AVX512_maskable_custom O, Format F, + dag Outs, + dag Ins, dag MaskingIns, dag ZeroMaskingIns, + string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + list Pattern, + list MaskingPattern, + list ZeroMaskingPattern, + string MaskingConstraint = "", + bit IsCommutable = 0, + bit IsKCommutable = 0, + bit IsKZCommutable = IsCommutable> { + let isCommutable = IsCommutable in + def NAME: AVX512; + + // Prefer over VMOV*rrk Pat<> + let isCommutable = IsKCommutable in + def NAME#k: AVX512, + EVEX_K { + // In case of the 3src subclass this is overridden with a let. + string Constraints = MaskingConstraint; + } + + // Zero mask does not add any restrictions to commute operands transformation. + // So, it is Ok to use IsCommutable instead of IsKCommutable. + let isCommutable = IsKZCommutable in // Prefer over VMOV*rrkz Pat<> + def NAME#kz: AVX512, + EVEX_KZ; +} + + +// Common base class of AVX512_maskable and AVX512_maskable_3src. +multiclass AVX512_maskable_common O, Format F, X86VectorVTInfo _, + dag Outs, + dag Ins, dag MaskingIns, dag ZeroMaskingIns, + string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, dag MaskingRHS, + SDNode Select = vselect, + string MaskingConstraint = "", + bit IsCommutable = 0, + bit IsKCommutable = 0, + bit IsKZCommutable = IsCommutable> : + AVX512_maskable_custom; + +// This multiclass generates the unconditional/non-masking, the masking and +// the zero-masking variant of the vector instruction. In the masking case, the +// preserved vector elements come from a new dummy input operand tied to $dst. +// This version uses a separate dag for non-masking and masking. +multiclass AVX512_maskable_split O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, dag MaskRHS, + bit IsCommutable = 0, bit IsKCommutable = 0, + SDNode Select = vselect> : + AVX512_maskable_custom; + +// This multiclass generates the unconditional/non-masking, the masking and +// the zero-masking variant of the vector instruction. In the masking case, the +// preserved vector elements come from a new dummy input operand tied to $dst. +multiclass AVX512_maskable O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, + bit IsCommutable = 0, bit IsKCommutable = 0, + bit IsKZCommutable = IsCommutable, + SDNode Select = vselect> : + AVX512_maskable_common; + +// This multiclass generates the unconditional/non-masking, the masking and +// the zero-masking variant of the scalar instruction. +multiclass AVX512_maskable_scalar O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, + bit IsCommutable = 0> : + AVX512_maskable; + +// Similar to AVX512_maskable but in this case one of the source operands +// ($src1) is already tied to $dst so we just use that for the preserved +// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude +// $src1. +multiclass AVX512_maskable_3src O, Format F, X86VectorVTInfo _, + dag Outs, dag NonTiedIns, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, + bit IsCommutable = 0, + bit IsKCommutable = 0, + SDNode Select = vselect, + bit MaskOnly = 0> : + AVX512_maskable_common; + +// Similar to AVX512_maskable_3src but in this case the input VT for the tied +// operand differs from the output VT. This requires a bitconvert on +// the preserved vector going into the vselect. +// NOTE: The unmasked pattern is disabled. +multiclass AVX512_maskable_3src_cast O, Format F, X86VectorVTInfo OutVT, + X86VectorVTInfo InVT, + dag Outs, dag NonTiedIns, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, bit IsCommutable = 0> : + AVX512_maskable_common; + +multiclass AVX512_maskable_3src_scalar O, Format F, X86VectorVTInfo _, + dag Outs, dag NonTiedIns, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, + bit IsCommutable = 0, + bit IsKCommutable = 0, + bit MaskOnly = 0> : + AVX512_maskable_3src; + +multiclass AVX512_maskable_in_asm O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, + string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + list Pattern> : + AVX512_maskable_custom; + +multiclass AVX512_maskable_3src_in_asm O, Format F, X86VectorVTInfo _, + dag Outs, dag NonTiedIns, + string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + list Pattern> : + AVX512_maskable_custom; + +// Instruction with mask that puts result in mask register, +// like "compare" and "vptest" +multiclass AVX512_maskable_custom_cmp O, Format F, + dag Outs, + dag Ins, dag MaskingIns, + string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + list Pattern, + list MaskingPattern, + bit IsCommutable = 0> { + let isCommutable = IsCommutable in + def NAME: AVX512; + + def NAME#k: AVX512, EVEX_K; +} + +multiclass AVX512_maskable_common_cmp O, Format F, X86VectorVTInfo _, + dag Outs, + dag Ins, dag MaskingIns, + string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, dag MaskingRHS, + bit IsCommutable = 0> : + AVX512_maskable_custom_cmp; + +multiclass AVX512_maskable_cmp O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, bit IsCommutable = 0> : + AVX512_maskable_common_cmp; + +multiclass AVX512_maskable_cmp_alt O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm> : + AVX512_maskable_custom_cmp; + +// This multiclass generates the unconditional/non-masking, the masking and +// the zero-masking variant of the vector instruction. In the masking case, the +// preserved vector elements come from a new dummy input operand tied to $dst. +multiclass AVX512_maskable_logic O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, dag MaskedRHS, + bit IsCommutable = 0, SDNode Select = vselect> : + AVX512_maskable_custom; + + +// Alias instruction that maps zero vector to pxor / xorp* for AVX-512. +// This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then +// swizzled by ExecutionDomainFix to pxor. +// We set canFoldAsLoad because this can be converted to a constant-pool +// load of an all-zeros value if folding it would be beneficial. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, Predicates = [HasAVX512], SchedRW = [WriteZero] in { +def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "", + [(set VR512:$dst, (v16i32 immAllZerosV))]>; +def AVX512_512_SETALLONES : I<0, Pseudo, (outs VR512:$dst), (ins), "", + [(set VR512:$dst, (v16i32 immAllOnesV))]>; +} + +// Alias instructions that allow VPTERNLOG to be used with a mask to create +// a mix of all ones and all zeros elements. This is done this way to force +// the same register to be used as input for all three sources. +let isPseudo = 1, Predicates = [HasAVX512], SchedRW = [WriteVecALU] in { +def AVX512_512_SEXT_MASK_32 : I<0, Pseudo, (outs VR512:$dst), + (ins VK16WM:$mask), "", + [(set VR512:$dst, (vselect (v16i1 VK16WM:$mask), + (v16i32 immAllOnesV), + (v16i32 immAllZerosV)))]>; +def AVX512_512_SEXT_MASK_64 : I<0, Pseudo, (outs VR512:$dst), + (ins VK8WM:$mask), "", + [(set VR512:$dst, (vselect (v8i1 VK8WM:$mask), + (bc_v8i64 (v16i32 immAllOnesV)), + (bc_v8i64 (v16i32 immAllZerosV))))]>; +} + +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, Predicates = [HasAVX512], SchedRW = [WriteZero] in { +def AVX512_128_SET0 : I<0, Pseudo, (outs VR128X:$dst), (ins), "", + [(set VR128X:$dst, (v4i32 immAllZerosV))]>; +def AVX512_256_SET0 : I<0, Pseudo, (outs VR256X:$dst), (ins), "", + [(set VR256X:$dst, (v8i32 immAllZerosV))]>; +} + +// Alias instructions that map fld0 to xorps for sse or vxorps for avx. +// This is expanded by ExpandPostRAPseudos. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, SchedRW = [WriteZero], Predicates = [HasAVX512] in { + def AVX512_FsFLD0SS : I<0, Pseudo, (outs FR32X:$dst), (ins), "", + [(set FR32X:$dst, fp32imm0)]>; + def AVX512_FsFLD0SD : I<0, Pseudo, (outs FR64X:$dst), (ins), "", + [(set FR64X:$dst, fpimm0)]>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 - VECTOR INSERT +// + +// Supports two different pattern operators for mask and unmasked ops. Allows +// null_frag to be passed for one. +multiclass vinsert_for_size_split { + let hasSideEffects = 0, ExeDomain = To.ExeDomain in { + defm rr : AVX512_maskable_split, + AVX512AIi8Base, EVEX_4V, Sched<[sched]>; + let mayLoad = 1 in + defm rm : AVX512_maskable_split, AVX512AIi8Base, EVEX_4V, + EVEX_CD8, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +// Passes the same pattern operator for masked and unmasked ops. +multiclass vinsert_for_size : + vinsert_for_size_split; + +multiclass vinsert_for_size_lowering p> { + let Predicates = p in { + def : Pat<(vinsert_insert:$ins + (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)), + (To.VT (!cast(InstrStr#"rr") + To.RC:$src1, From.RC:$src2, + (INSERT_get_vinsert_imm To.RC:$ins)))>; + + def : Pat<(vinsert_insert:$ins + (To.VT To.RC:$src1), + (From.VT (bitconvert (From.LdFrag addr:$src2))), + (iPTR imm)), + (To.VT (!cast(InstrStr#"rm") + To.RC:$src1, addr:$src2, + (INSERT_get_vinsert_imm To.RC:$ins)))>; + } +} + +multiclass vinsert_for_type { + + let Predicates = [HasVLX] in + defm NAME # "32x4Z256" : vinsert_for_size, + X86VectorVTInfo< 8, EltVT32, VR256X>, + vinsert128_insert, sched>, EVEX_V256; + + defm NAME # "32x4Z" : vinsert_for_size, + X86VectorVTInfo<16, EltVT32, VR512>, + vinsert128_insert, sched>, EVEX_V512; + + defm NAME # "64x4Z" : vinsert_for_size, + X86VectorVTInfo< 8, EltVT64, VR512>, + vinsert256_insert, sched>, VEX_W, EVEX_V512; + + // Even with DQI we'd like to only use these instructions for masking. + let Predicates = [HasVLX, HasDQI] in + defm NAME # "64x2Z256" : vinsert_for_size_split, + X86VectorVTInfo< 4, EltVT64, VR256X>, + null_frag, vinsert128_insert, sched>, + VEX_W1X, EVEX_V256; + + // Even with DQI we'd like to only use these instructions for masking. + let Predicates = [HasDQI] in { + defm NAME # "64x2Z" : vinsert_for_size_split, + X86VectorVTInfo< 8, EltVT64, VR512>, + null_frag, vinsert128_insert, sched>, + VEX_W, EVEX_V512; + + defm NAME # "32x8Z" : vinsert_for_size_split, + X86VectorVTInfo<16, EltVT32, VR512>, + null_frag, vinsert256_insert, sched>, + EVEX_V512; + } +} + +// FIXME: Is there a better scheduler class for VINSERTF/VINSERTI? +defm VINSERTF : vinsert_for_type; +defm VINSERTI : vinsert_for_type; + +// Codegen pattern with the alternative types, +// Even with AVX512DQ we'll still use these for unmasked operations. +defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; +defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; + +defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; +defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; + +defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info, + vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; +defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info, + vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; + +// Codegen pattern with the alternative types insert VEC128 into VEC256 +defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; +defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; +// Codegen pattern with the alternative types insert VEC128 into VEC512 +defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; +defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; +// Codegen pattern with the alternative types insert VEC256 into VEC512 +defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info, + vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; +defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info, + vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; + + +multiclass vinsert_for_mask_cast p> { +let Predicates = p in { + def : Pat<(Cast.VT + (vselect Cast.KRCWM:$mask, + (bitconvert + (vinsert_insert:$ins (To.VT To.RC:$src1), + (From.VT From.RC:$src2), + (iPTR imm))), + Cast.RC:$src0)), + (!cast(InstrStr#"rrk") + Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2, + (INSERT_get_vinsert_imm To.RC:$ins))>; + def : Pat<(Cast.VT + (vselect Cast.KRCWM:$mask, + (bitconvert + (vinsert_insert:$ins (To.VT To.RC:$src1), + (From.VT + (bitconvert + (From.LdFrag addr:$src2))), + (iPTR imm))), + Cast.RC:$src0)), + (!cast(InstrStr#"rmk") + Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, addr:$src2, + (INSERT_get_vinsert_imm To.RC:$ins))>; + + def : Pat<(Cast.VT + (vselect Cast.KRCWM:$mask, + (bitconvert + (vinsert_insert:$ins (To.VT To.RC:$src1), + (From.VT From.RC:$src2), + (iPTR imm))), + Cast.ImmAllZerosV)), + (!cast(InstrStr#"rrkz") + Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2, + (INSERT_get_vinsert_imm To.RC:$ins))>; + def : Pat<(Cast.VT + (vselect Cast.KRCWM:$mask, + (bitconvert + (vinsert_insert:$ins (To.VT To.RC:$src1), + (From.VT + (bitconvert + (From.LdFrag addr:$src2))), + (iPTR imm))), + Cast.ImmAllZerosV)), + (!cast(InstrStr#"rmkz") + Cast.KRCWM:$mask, To.RC:$src1, addr:$src2, + (INSERT_get_vinsert_imm To.RC:$ins))>; +} +} + +defm : vinsert_for_mask_cast<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info, + v8f32x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasVLX]>; +defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v4f32x_info, v8f32x_info, + v4f64x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>; + +defm : vinsert_for_mask_cast<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info, + v8i32x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasVLX]>; +defm : vinsert_for_mask_cast<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info, + v8i32x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasVLX]>; +defm : vinsert_for_mask_cast<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info, + v8i32x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasVLX]>; +defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v4i32x_info, v8i32x_info, + v4i64x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>; +defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v8i16x_info, v16i16x_info, + v4i64x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>; +defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v16i8x_info, v32i8x_info, + v4i64x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>; + +defm : vinsert_for_mask_cast<"VINSERTF32x4Z", v2f64x_info, v8f64_info, + v16f32_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasAVX512]>; +defm : vinsert_for_mask_cast<"VINSERTF64x2Z", v4f32x_info, v16f32_info, + v8f64_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI]>; + +defm : vinsert_for_mask_cast<"VINSERTI32x4Z", v2i64x_info, v8i64_info, + v16i32_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasAVX512]>; +defm : vinsert_for_mask_cast<"VINSERTI32x4Z", v8i16x_info, v32i16_info, + v16i32_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasAVX512]>; +defm : vinsert_for_mask_cast<"VINSERTI32x4Z", v16i8x_info, v64i8_info, + v16i32_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasAVX512]>; +defm : vinsert_for_mask_cast<"VINSERTI64x2Z", v4i32x_info, v16i32_info, + v8i64_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI]>; +defm : vinsert_for_mask_cast<"VINSERTI64x2Z", v8i16x_info, v32i16_info, + v8i64_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI]>; +defm : vinsert_for_mask_cast<"VINSERTI64x2Z", v16i8x_info, v64i8_info, + v8i64_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI]>; + +defm : vinsert_for_mask_cast<"VINSERTF32x8Z", v4f64x_info, v8f64_info, + v16f32_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasDQI]>; +defm : vinsert_for_mask_cast<"VINSERTF64x4Z", v8f32x_info, v16f32_info, + v8f64_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasAVX512]>; + +defm : vinsert_for_mask_cast<"VINSERTI32x8Z", v4i64x_info, v8i64_info, + v16i32_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasDQI]>; +defm : vinsert_for_mask_cast<"VINSERTI32x8Z", v16i16x_info, v32i16_info, + v16i32_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasDQI]>; +defm : vinsert_for_mask_cast<"VINSERTI32x8Z", v32i8x_info, v64i8_info, + v16i32_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasDQI]>; +defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v8i32x_info, v16i32_info, + v8i64_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasAVX512]>; +defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v16i16x_info, v32i16_info, + v8i64_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasAVX512]>; +defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v32i8x_info, v64i8_info, + v8i64_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasAVX512]>; + +// vinsertps - insert f32 to XMM +let ExeDomain = SSEPackedSingle in { +def VINSERTPSZrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst), + (ins VR128X:$src1, VR128X:$src2, u8imm:$src3), + "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>, + EVEX_4V, Sched<[SchedWriteFShuffle.XMM]>; +def VINSERTPSZrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst), + (ins VR128X:$src1, f32mem:$src2, u8imm:$src3), + "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set VR128X:$dst, (X86insertps VR128X:$src1, + (v4f32 (scalar_to_vector (loadf32 addr:$src2))), + imm:$src3))]>, + EVEX_4V, EVEX_CD8<32, CD8VT1>, + Sched<[SchedWriteFShuffle.XMM.Folded, ReadAfterLd]>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 VECTOR EXTRACT +//--- + +// Supports two different pattern operators for mask and unmasked ops. Allows +// null_frag to be passed for one. +multiclass vextract_for_size_split { + + let hasSideEffects = 0, ExeDomain = To.ExeDomain in { + defm rr : AVX512_maskable_split, + AVX512AIi8Base, EVEX, Sched<[SchedRR]>; + + def mr : AVX512AIi8, EVEX, + Sched<[SchedMR]>; + + let mayStore = 1, hasSideEffects = 0 in + def mrk : AVX512AIi8, + EVEX_K, EVEX, Sched<[SchedMR]>, NotMemoryFoldable; + } +} + +// Passes the same pattern operator for masked and unmasked ops. +multiclass vextract_for_size : + vextract_for_size_split; + +// Codegen pattern for the alternative types +multiclass vextract_for_size_lowering p> { + let Predicates = p in { + def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)), + (To.VT (!cast(InstrStr#"rr") + From.RC:$src1, + (EXTRACT_get_vextract_imm To.RC:$ext)))>; + def : Pat<(store (To.VT (vextract_extract:$ext (From.VT From.RC:$src1), + (iPTR imm))), addr:$dst), + (!cast(InstrStr#"mr") addr:$dst, From.RC:$src1, + (EXTRACT_get_vextract_imm To.RC:$ext))>; + } +} + +multiclass vextract_for_type { + let Predicates = [HasAVX512] in { + defm NAME # "32x4Z" : vextract_for_size, + X86VectorVTInfo< 4, EltVT32, VR128X>, + vextract128_extract, SchedRR, SchedMR>, + EVEX_V512, EVEX_CD8<32, CD8VT4>; + defm NAME # "64x4Z" : vextract_for_size, + X86VectorVTInfo< 4, EltVT64, VR256X>, + vextract256_extract, SchedRR, SchedMR>, + VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>; + } + let Predicates = [HasVLX] in + defm NAME # "32x4Z256" : vextract_for_size, + X86VectorVTInfo< 4, EltVT32, VR128X>, + vextract128_extract, SchedRR, SchedMR>, + EVEX_V256, EVEX_CD8<32, CD8VT4>; + + // Even with DQI we'd like to only use these instructions for masking. + let Predicates = [HasVLX, HasDQI] in + defm NAME # "64x2Z256" : vextract_for_size_split, + X86VectorVTInfo< 2, EltVT64, VR128X>, + null_frag, vextract128_extract, SchedRR, SchedMR>, + VEX_W1X, EVEX_V256, EVEX_CD8<64, CD8VT2>; + + // Even with DQI we'd like to only use these instructions for masking. + let Predicates = [HasDQI] in { + defm NAME # "64x2Z" : vextract_for_size_split, + X86VectorVTInfo< 2, EltVT64, VR128X>, + null_frag, vextract128_extract, SchedRR, SchedMR>, + VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>; + defm NAME # "32x8Z" : vextract_for_size_split, + X86VectorVTInfo< 8, EltVT32, VR256X>, + null_frag, vextract256_extract, SchedRR, SchedMR>, + EVEX_V512, EVEX_CD8<32, CD8VT8>; + } +} + +// TODO - replace WriteFStore/WriteVecStore with X86SchedWriteMoveLSWidths types. +defm VEXTRACTF : vextract_for_type; +defm VEXTRACTI : vextract_for_type; + +// extract_subvector codegen patterns with the alternative types. +// Even with AVX512DQ we'll still use these for unmasked operations. +defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; +defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; + +defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info, + vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; +defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info, + vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; + +defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; +defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; + +// Codegen pattern with the alternative types extract VEC128 from VEC256 +defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v16i16x_info, v8i16x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; +defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v32i8x_info, v16i8x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; + +// Codegen pattern with the alternative types extract VEC128 from VEC512 +defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; +defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; +// Codegen pattern with the alternative types extract VEC256 from VEC512 +defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info, + vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; +defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info, + vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; + + +// A 128-bit extract from bits [255:128] of a 512-bit vector should use a +// smaller extract to enable EVEX->VEX. +let Predicates = [NoVLX] in { +def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))), + (v2i64 (VEXTRACTI128rr + (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))), + (v2f64 (VEXTRACTF128rr + (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))), + (v4i32 (VEXTRACTI128rr + (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))), + (v4f32 (VEXTRACTF128rr + (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))), + (v8i16 (VEXTRACTI128rr + (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))), + (v16i8 (VEXTRACTI128rr + (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)), + (iPTR 1)))>; +} + +// A 128-bit extract from bits [255:128] of a 512-bit vector should use a +// smaller extract to enable EVEX->VEX. +let Predicates = [HasVLX] in { +def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))), + (v2i64 (VEXTRACTI32x4Z256rr + (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))), + (v2f64 (VEXTRACTF32x4Z256rr + (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))), + (v4i32 (VEXTRACTI32x4Z256rr + (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))), + (v4f32 (VEXTRACTF32x4Z256rr + (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))), + (v8i16 (VEXTRACTI32x4Z256rr + (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))), + (v16i8 (VEXTRACTI32x4Z256rr + (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)), + (iPTR 1)))>; +} + + +// Additional patterns for handling a bitcast between the vselect and the +// extract_subvector. +multiclass vextract_for_mask_cast p> { +let Predicates = p in { + def : Pat<(Cast.VT (vselect Cast.KRCWM:$mask, + (bitconvert + (To.VT (vextract_extract:$ext + (From.VT From.RC:$src), (iPTR imm)))), + To.RC:$src0)), + (Cast.VT (!cast(InstrStr#"rrk") + Cast.RC:$src0, Cast.KRCWM:$mask, From.RC:$src, + (EXTRACT_get_vextract_imm To.RC:$ext)))>; + + def : Pat<(Cast.VT (vselect Cast.KRCWM:$mask, + (bitconvert + (To.VT (vextract_extract:$ext + (From.VT From.RC:$src), (iPTR imm)))), + Cast.ImmAllZerosV)), + (Cast.VT (!cast(InstrStr#"rrkz") + Cast.KRCWM:$mask, From.RC:$src, + (EXTRACT_get_vextract_imm To.RC:$ext)))>; +} +} + +defm : vextract_for_mask_cast<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info, + v4f32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasVLX]>; +defm : vextract_for_mask_cast<"VEXTRACTF64x2Z256", v8f32x_info, v4f32x_info, + v2f64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI, HasVLX]>; + +defm : vextract_for_mask_cast<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info, + v4i32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasVLX]>; +defm : vextract_for_mask_cast<"VEXTRACTI32x4Z256", v16i16x_info, v8i16x_info, + v4i32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasVLX]>; +defm : vextract_for_mask_cast<"VEXTRACTI32x4Z256", v32i8x_info, v16i8x_info, + v4i32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasVLX]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x2Z256", v8i32x_info, v4i32x_info, + v2i64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI, HasVLX]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x2Z256", v16i16x_info, v8i16x_info, + v2i64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI, HasVLX]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x2Z256", v32i8x_info, v16i8x_info, + v2i64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI, HasVLX]>; + +defm : vextract_for_mask_cast<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info, + v4f32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasAVX512]>; +defm : vextract_for_mask_cast<"VEXTRACTF64x2Z", v16f32_info, v4f32x_info, + v2f64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI]>; + +defm : vextract_for_mask_cast<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info, + v4i32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasAVX512]>; +defm : vextract_for_mask_cast<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info, + v4i32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasAVX512]>; +defm : vextract_for_mask_cast<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info, + v4i32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasAVX512]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x2Z", v16i32_info, v4i32x_info, + v2i64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x2Z", v32i16_info, v8i16x_info, + v2i64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x2Z", v64i8_info, v16i8x_info, + v2i64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI]>; + +defm : vextract_for_mask_cast<"VEXTRACTF32x8Z", v8f64_info, v4f64x_info, + v8f32x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasDQI]>; +defm : vextract_for_mask_cast<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info, + v4f64x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasAVX512]>; + +defm : vextract_for_mask_cast<"VEXTRACTI32x8Z", v8i64_info, v4i64x_info, + v8i32x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasDQI]>; +defm : vextract_for_mask_cast<"VEXTRACTI32x8Z", v32i16_info, v16i16x_info, + v8i32x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasDQI]>; +defm : vextract_for_mask_cast<"VEXTRACTI32x8Z", v64i8_info, v32i8x_info, + v8i32x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasDQI]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info, + v4i64x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasAVX512]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info, + v4i64x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasAVX512]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info, + v4i64x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasAVX512]>; + +// vextractps - extract 32 bits from XMM +def VEXTRACTPSZrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst), + (ins VR128X:$src1, u8imm:$src2), + "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>, + EVEX, VEX_WIG, Sched<[WriteVecExtract]>; + +def VEXTRACTPSZmr : AVX512AIi8<0x17, MRMDestMem, (outs), + (ins f32mem:$dst, VR128X:$src1, u8imm:$src2), + "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2), + addr:$dst)]>, + EVEX, VEX_WIG, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecExtractSt]>; + +//===---------------------------------------------------------------------===// +// AVX-512 BROADCAST +//--- +// broadcast with a scalar argument. +multiclass avx512_broadcast_scalar opc, string OpcodeStr, + string Name, + X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> { + def : Pat<(DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)), + (!cast(Name#DestInfo.ZSuffix#r) + (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>; + def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask, + (X86VBroadcast SrcInfo.FRC:$src), + DestInfo.RC:$src0)), + (!cast(Name#DestInfo.ZSuffix#rk) + DestInfo.RC:$src0, DestInfo.KRCWM:$mask, + (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>; + def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask, + (X86VBroadcast SrcInfo.FRC:$src), + DestInfo.ImmAllZerosV)), + (!cast(Name#DestInfo.ZSuffix#rkz) + DestInfo.KRCWM:$mask, (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>; +} + +// Split version to allow mask and broadcast node to be different types. This +// helps support the 32x2 broadcasts. +multiclass avx512_broadcast_rm_split opc, string OpcodeStr, + string Name, + SchedWrite SchedRR, SchedWrite SchedRM, + X86VectorVTInfo MaskInfo, + X86VectorVTInfo DestInfo, + X86VectorVTInfo SrcInfo, + SDPatternOperator UnmaskedOp = X86VBroadcast> { + let ExeDomain = DestInfo.ExeDomain, hasSideEffects = 0 in { + defm r : AVX512_maskable_split, + T8PD, EVEX, Sched<[SchedRR]>; + let mayLoad = 1 in + defm m : AVX512_maskable_split, + T8PD, EVEX, EVEX_CD8, + Sched<[SchedRM]>; + } + + def : Pat<(MaskInfo.VT + (bitconvert + (DestInfo.VT (UnmaskedOp + (SrcInfo.VT (scalar_to_vector + (SrcInfo.ScalarLdFrag addr:$src))))))), + (!cast(Name#MaskInfo.ZSuffix#m) addr:$src)>; + def : Pat<(MaskInfo.VT (vselect MaskInfo.KRCWM:$mask, + (bitconvert + (DestInfo.VT + (X86VBroadcast + (SrcInfo.VT (scalar_to_vector + (SrcInfo.ScalarLdFrag addr:$src)))))), + MaskInfo.RC:$src0)), + (!cast(Name#DestInfo.ZSuffix#mk) + MaskInfo.RC:$src0, MaskInfo.KRCWM:$mask, addr:$src)>; + def : Pat<(MaskInfo.VT (vselect MaskInfo.KRCWM:$mask, + (bitconvert + (DestInfo.VT + (X86VBroadcast + (SrcInfo.VT (scalar_to_vector + (SrcInfo.ScalarLdFrag addr:$src)))))), + MaskInfo.ImmAllZerosV)), + (!cast(Name#MaskInfo.ZSuffix#mkz) + MaskInfo.KRCWM:$mask, addr:$src)>; +} + +// Helper class to force mask and broadcast result to same type. +multiclass avx512_broadcast_rm opc, string OpcodeStr, string Name, + SchedWrite SchedRR, SchedWrite SchedRM, + X86VectorVTInfo DestInfo, + X86VectorVTInfo SrcInfo> : + avx512_broadcast_rm_split; + +multiclass avx512_fp_broadcast_sd opc, string OpcodeStr, + AVX512VLVectorVTInfo _> { + let Predicates = [HasAVX512] in { + defm Z : avx512_broadcast_rm, + avx512_broadcast_scalar, + EVEX_V512; + } + + let Predicates = [HasVLX] in { + defm Z256 : avx512_broadcast_rm, + avx512_broadcast_scalar, + EVEX_V256; + } +} + +multiclass avx512_fp_broadcast_ss opc, string OpcodeStr, + AVX512VLVectorVTInfo _> { + let Predicates = [HasAVX512] in { + defm Z : avx512_broadcast_rm, + avx512_broadcast_scalar, + EVEX_V512; + } + + let Predicates = [HasVLX] in { + defm Z256 : avx512_broadcast_rm, + avx512_broadcast_scalar, + EVEX_V256; + defm Z128 : avx512_broadcast_rm, + avx512_broadcast_scalar, + EVEX_V128; + } +} +defm VBROADCASTSS : avx512_fp_broadcast_ss<0x18, "vbroadcastss", + avx512vl_f32_info>; +defm VBROADCASTSD : avx512_fp_broadcast_sd<0x19, "vbroadcastsd", + avx512vl_f64_info>, VEX_W1X; + +multiclass avx512_int_broadcast_reg opc, SchedWrite SchedRR, + X86VectorVTInfo _, SDPatternOperator OpNode, + RegisterClass SrcRC> { + let ExeDomain = _.ExeDomain in + defm r : AVX512_maskable, T8PD, EVEX, + Sched<[SchedRR]>; +} + +multiclass avx512_int_broadcastbw_reg opc, string Name, SchedWrite SchedRR, + X86VectorVTInfo _, SDPatternOperator OpNode, + RegisterClass SrcRC, SubRegIndex Subreg> { + let hasSideEffects = 0, ExeDomain = _.ExeDomain in + defm r : AVX512_maskable_custom, T8PD, EVEX, Sched<[SchedRR]>; + + def : Pat <(_.VT (OpNode SrcRC:$src)), + (!cast(Name#r) + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>; + + def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.RC:$src0), + (!cast(Name#rk) _.RC:$src0, _.KRCWM:$mask, + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>; + + def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.ImmAllZerosV), + (!cast(Name#rkz) _.KRCWM:$mask, + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>; +} + +multiclass avx512_int_broadcastbw_reg_vl opc, string Name, + AVX512VLVectorVTInfo _, SDPatternOperator OpNode, + RegisterClass SrcRC, SubRegIndex Subreg, Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_int_broadcastbw_reg, EVEX_V512; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_int_broadcastbw_reg, EVEX_V256; + defm Z128 : avx512_int_broadcastbw_reg, EVEX_V128; + } +} + +multiclass avx512_int_broadcast_reg_vl opc, AVX512VLVectorVTInfo _, + SDPatternOperator OpNode, + RegisterClass SrcRC, Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_int_broadcast_reg, EVEX_V512; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_int_broadcast_reg, EVEX_V256; + defm Z128 : avx512_int_broadcast_reg, EVEX_V128; + } +} + +defm VPBROADCASTBr : avx512_int_broadcastbw_reg_vl<0x7A, "VPBROADCASTBr", + avx512vl_i8_info, X86VBroadcast, GR8, sub_8bit, HasBWI>; +defm VPBROADCASTWr : avx512_int_broadcastbw_reg_vl<0x7B, "VPBROADCASTWr", + avx512vl_i16_info, X86VBroadcast, GR16, sub_16bit, + HasBWI>; +defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, + X86VBroadcast, GR32, HasAVX512>; +defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, + X86VBroadcast, GR64, HasAVX512>, VEX_W; + +// Provide aliases for broadcast from the same register class that +// automatically does the extract. +multiclass avx512_int_broadcast_rm_lowering { + def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))), + (!cast(Name#DestInfo.ZSuffix#"r") + (ExtInfo.VT (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm)))>; +} + +multiclass avx512_int_broadcast_rm_vl opc, string OpcodeStr, + AVX512VLVectorVTInfo _, Predicate prd> { + let Predicates = [prd] in { + defm Z : avx512_broadcast_rm, + avx512_int_broadcast_rm_lowering, + EVEX_V512; + // Defined separately to avoid redefinition. + defm Z_Alt : avx512_int_broadcast_rm_lowering; + } + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_broadcast_rm, + avx512_int_broadcast_rm_lowering, + EVEX_V256; + defm Z128 : avx512_broadcast_rm, + EVEX_V128; + } +} + +defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb", + avx512vl_i8_info, HasBWI>; +defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw", + avx512vl_i16_info, HasBWI>; +defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd", + avx512vl_i32_info, HasAVX512>; +defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq", + avx512vl_i64_info, HasAVX512>, VEX_W1X; + +multiclass avx512_subvec_broadcast_rm opc, string OpcodeStr, + X86VectorVTInfo _Dst, X86VectorVTInfo _Src> { + defm rm : AVX512_maskable, + Sched<[SchedWriteShuffle.YMM.Folded]>, + AVX5128IBase, EVEX; +} + +// This should be used for the AVX512DQ broadcast instructions. It disables +// the unmasked patterns so that we only use the DQ instructions when masking +// is requested. +multiclass avx512_subvec_broadcast_rm_dq opc, string OpcodeStr, + X86VectorVTInfo _Dst, X86VectorVTInfo _Src> { + let hasSideEffects = 0, mayLoad = 1 in + defm rm : AVX512_maskable_split, + Sched<[SchedWriteShuffle.YMM.Folded]>, + AVX5128IBase, EVEX; +} + +let Predicates = [HasAVX512] in { + // 32-bit targets will fail to load a i64 directly but can use ZEXT_LOAD. + def : Pat<(v8i64 (X86VBroadcast (v8i64 (X86vzload addr:$src)))), + (VPBROADCASTQZm addr:$src)>; +} + +let Predicates = [HasVLX] in { + // 32-bit targets will fail to load a i64 directly but can use ZEXT_LOAD. + def : Pat<(v2i64 (X86VBroadcast (v2i64 (X86vzload addr:$src)))), + (VPBROADCASTQZ128m addr:$src)>; + def : Pat<(v4i64 (X86VBroadcast (v4i64 (X86vzload addr:$src)))), + (VPBROADCASTQZ256m addr:$src)>; +} +let Predicates = [HasVLX, HasBWI] in { + // loadi16 is tricky to fold, because !isTypeDesirableForOp, justifiably. + // This means we'll encounter truncated i32 loads; match that here. + def : Pat<(v8i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))), + (VPBROADCASTWZ128m addr:$src)>; + def : Pat<(v16i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))), + (VPBROADCASTWZ256m addr:$src)>; + def : Pat<(v8i16 (X86VBroadcast + (i16 (trunc (i32 (zextloadi16 addr:$src)))))), + (VPBROADCASTWZ128m addr:$src)>; + def : Pat<(v16i16 (X86VBroadcast + (i16 (trunc (i32 (zextloadi16 addr:$src)))))), + (VPBROADCASTWZ256m addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 BROADCAST SUBVECTORS +// + +defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4", + v16i32_info, v4i32x_info>, + EVEX_V512, EVEX_CD8<32, CD8VT4>; +defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4", + v16f32_info, v4f32x_info>, + EVEX_V512, EVEX_CD8<32, CD8VT4>; +defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4", + v8i64_info, v4i64x_info>, VEX_W, + EVEX_V512, EVEX_CD8<64, CD8VT4>; +defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4", + v8f64_info, v4f64x_info>, VEX_W, + EVEX_V512, EVEX_CD8<64, CD8VT4>; + +let Predicates = [HasAVX512] in { +def : Pat<(v16f32 (X86SubVBroadcast (loadv8f32 addr:$src))), + (VBROADCASTF64X4rm addr:$src)>; +def : Pat<(v16i32 (X86SubVBroadcast (bc_v8i32 (loadv4i64 addr:$src)))), + (VBROADCASTI64X4rm addr:$src)>; +def : Pat<(v32i16 (X86SubVBroadcast (bc_v16i16 (loadv4i64 addr:$src)))), + (VBROADCASTI64X4rm addr:$src)>; +def : Pat<(v64i8 (X86SubVBroadcast (bc_v32i8 (loadv4i64 addr:$src)))), + (VBROADCASTI64X4rm addr:$src)>; + +// Provide fallback in case the load node that is used in the patterns above +// is used by additional users, which prevents the pattern selection. +def : Pat<(v8f64 (X86SubVBroadcast (v4f64 VR256X:$src))), + (VINSERTF64x4Zrr (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (v4f64 VR256X:$src), 1)>; +def : Pat<(v16f32 (X86SubVBroadcast (v8f32 VR256X:$src))), + (VINSERTF64x4Zrr (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (v8f32 VR256X:$src), 1)>; +def : Pat<(v8i64 (X86SubVBroadcast (v4i64 VR256X:$src))), + (VINSERTI64x4Zrr (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (v4i64 VR256X:$src), 1)>; +def : Pat<(v16i32 (X86SubVBroadcast (v8i32 VR256X:$src))), + (VINSERTI64x4Zrr (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (v8i32 VR256X:$src), 1)>; +def : Pat<(v32i16 (X86SubVBroadcast (v16i16 VR256X:$src))), + (VINSERTI64x4Zrr (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (v16i16 VR256X:$src), 1)>; +def : Pat<(v64i8 (X86SubVBroadcast (v32i8 VR256X:$src))), + (VINSERTI64x4Zrr (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (v32i8 VR256X:$src), 1)>; + +def : Pat<(v8f64 (X86SubVBroadcast (loadv2f64 addr:$src))), + (VBROADCASTF32X4rm addr:$src)>; +def : Pat<(v8i64 (X86SubVBroadcast (loadv2i64 addr:$src))), + (VBROADCASTI32X4rm addr:$src)>; +def : Pat<(v32i16 (X86SubVBroadcast (bc_v8i16 (loadv2i64 addr:$src)))), + (VBROADCASTI32X4rm addr:$src)>; +def : Pat<(v64i8 (X86SubVBroadcast (bc_v16i8 (loadv2i64 addr:$src)))), + (VBROADCASTI32X4rm addr:$src)>; + +// Patterns for selects of bitcasted operations. +def : Pat<(vselect VK16WM:$mask, + (bc_v16f32 (v8f64 (X86SubVBroadcast (loadv2f64 addr:$src)))), + (bc_v16f32 (v16i32 immAllZerosV))), + (VBROADCASTF32X4rmkz VK16WM:$mask, addr:$src)>; +def : Pat<(vselect VK16WM:$mask, + (bc_v16f32 (v8f64 (X86SubVBroadcast (loadv2f64 addr:$src)))), + VR512:$src0), + (VBROADCASTF32X4rmk VR512:$src0, VK16WM:$mask, addr:$src)>; +def : Pat<(vselect VK16WM:$mask, + (bc_v16i32 (v8i64 (X86SubVBroadcast (loadv2i64 addr:$src)))), + (v16i32 immAllZerosV)), + (VBROADCASTI32X4rmkz VK16WM:$mask, addr:$src)>; +def : Pat<(vselect VK16WM:$mask, + (bc_v16i32 (v8i64 (X86SubVBroadcast (loadv2i64 addr:$src)))), + VR512:$src0), + (VBROADCASTI32X4rmk VR512:$src0, VK16WM:$mask, addr:$src)>; + +def : Pat<(vselect VK8WM:$mask, + (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv8f32 addr:$src)))), + (bc_v8f64 (v16i32 immAllZerosV))), + (VBROADCASTF64X4rmkz VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv8f32 addr:$src)))), + VR512:$src0), + (VBROADCASTF64X4rmk VR512:$src0, VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8i64 (v16i32 (X86SubVBroadcast (bc_v8i32 (loadv4i64 addr:$src))))), + (bc_v8i64 (v16i32 immAllZerosV))), + (VBROADCASTI64X4rmkz VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8i64 (v16i32 (X86SubVBroadcast (bc_v8i32 (loadv4i64 addr:$src))))), + VR512:$src0), + (VBROADCASTI64X4rmk VR512:$src0, VK8WM:$mask, addr:$src)>; +} + +let Predicates = [HasVLX] in { +defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4", + v8i32x_info, v4i32x_info>, + EVEX_V256, EVEX_CD8<32, CD8VT4>; +defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4", + v8f32x_info, v4f32x_info>, + EVEX_V256, EVEX_CD8<32, CD8VT4>; + +def : Pat<(v4f64 (X86SubVBroadcast (loadv2f64 addr:$src))), + (VBROADCASTF32X4Z256rm addr:$src)>; +def : Pat<(v4i64 (X86SubVBroadcast (loadv2i64 addr:$src))), + (VBROADCASTI32X4Z256rm addr:$src)>; +def : Pat<(v16i16 (X86SubVBroadcast (bc_v8i16 (loadv2i64 addr:$src)))), + (VBROADCASTI32X4Z256rm addr:$src)>; +def : Pat<(v32i8 (X86SubVBroadcast (bc_v16i8 (loadv2i64 addr:$src)))), + (VBROADCASTI32X4Z256rm addr:$src)>; + +// Patterns for selects of bitcasted operations. +def : Pat<(vselect VK8WM:$mask, + (bc_v8f32 (v4f64 (X86SubVBroadcast (loadv2f64 addr:$src)))), + (bc_v8f32 (v8i32 immAllZerosV))), + (VBROADCASTF32X4Z256rmkz VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8f32 (v4f64 (X86SubVBroadcast (loadv2f64 addr:$src)))), + VR256X:$src0), + (VBROADCASTF32X4Z256rmk VR256X:$src0, VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8i32 (v4i64 (X86SubVBroadcast (loadv2i64 addr:$src)))), + (v8i32 immAllZerosV)), + (VBROADCASTI32X4Z256rmkz VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8i32 (v4i64 (X86SubVBroadcast (loadv2i64 addr:$src)))), + VR256X:$src0), + (VBROADCASTI32X4Z256rmk VR256X:$src0, VK8WM:$mask, addr:$src)>; + + +// Provide fallback in case the load node that is used in the patterns above +// is used by additional users, which prevents the pattern selection. +def : Pat<(v4f64 (X86SubVBroadcast (v2f64 VR128X:$src))), + (VINSERTF32x4Z256rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (v2f64 VR128X:$src), 1)>; +def : Pat<(v8f32 (X86SubVBroadcast (v4f32 VR128X:$src))), + (VINSERTF32x4Z256rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (v4f32 VR128X:$src), 1)>; +def : Pat<(v4i64 (X86SubVBroadcast (v2i64 VR128X:$src))), + (VINSERTI32x4Z256rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (v2i64 VR128X:$src), 1)>; +def : Pat<(v8i32 (X86SubVBroadcast (v4i32 VR128X:$src))), + (VINSERTI32x4Z256rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (v4i32 VR128X:$src), 1)>; +def : Pat<(v16i16 (X86SubVBroadcast (v8i16 VR128X:$src))), + (VINSERTI32x4Z256rr (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (v8i16 VR128X:$src), 1)>; +def : Pat<(v32i8 (X86SubVBroadcast (v16i8 VR128X:$src))), + (VINSERTI32x4Z256rr (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (v16i8 VR128X:$src), 1)>; +} + +let Predicates = [HasVLX, HasDQI] in { +defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm_dq<0x5a, "vbroadcasti64x2", + v4i64x_info, v2i64x_info>, VEX_W1X, + EVEX_V256, EVEX_CD8<64, CD8VT2>; +defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm_dq<0x1a, "vbroadcastf64x2", + v4f64x_info, v2f64x_info>, VEX_W1X, + EVEX_V256, EVEX_CD8<64, CD8VT2>; + +// Patterns for selects of bitcasted operations. +def : Pat<(vselect VK4WM:$mask, + (bc_v4f64 (v8f32 (X86SubVBroadcast (loadv4f32 addr:$src)))), + (bc_v4f64 (v8i32 immAllZerosV))), + (VBROADCASTF64X2Z128rmkz VK4WM:$mask, addr:$src)>; +def : Pat<(vselect VK4WM:$mask, + (bc_v4f64 (v8f32 (X86SubVBroadcast (loadv4f32 addr:$src)))), + VR256X:$src0), + (VBROADCASTF64X2Z128rmk VR256X:$src0, VK4WM:$mask, addr:$src)>; +def : Pat<(vselect VK4WM:$mask, + (bc_v4i64 (v8i32 (X86SubVBroadcast (bc_v4i32 (loadv2i64 addr:$src))))), + (bc_v4i64 (v8i32 immAllZerosV))), + (VBROADCASTI64X2Z128rmkz VK4WM:$mask, addr:$src)>; +def : Pat<(vselect VK4WM:$mask, + (bc_v4i64 (v8i32 (X86SubVBroadcast (bc_v4i32 (loadv2i64 addr:$src))))), + VR256X:$src0), + (VBROADCASTI64X2Z128rmk VR256X:$src0, VK4WM:$mask, addr:$src)>; +} + +let Predicates = [HasDQI] in { +defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm_dq<0x5a, "vbroadcasti64x2", + v8i64_info, v2i64x_info>, VEX_W, + EVEX_V512, EVEX_CD8<64, CD8VT2>; +defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm_dq<0x5b, "vbroadcasti32x8", + v16i32_info, v8i32x_info>, + EVEX_V512, EVEX_CD8<32, CD8VT8>; +defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm_dq<0x1a, "vbroadcastf64x2", + v8f64_info, v2f64x_info>, VEX_W, + EVEX_V512, EVEX_CD8<64, CD8VT2>; +defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm_dq<0x1b, "vbroadcastf32x8", + v16f32_info, v8f32x_info>, + EVEX_V512, EVEX_CD8<32, CD8VT8>; + +// Patterns for selects of bitcasted operations. +def : Pat<(vselect VK16WM:$mask, + (bc_v16f32 (v8f64 (X86SubVBroadcast (loadv4f64 addr:$src)))), + (bc_v16f32 (v16i32 immAllZerosV))), + (VBROADCASTF32X8rmkz VK16WM:$mask, addr:$src)>; +def : Pat<(vselect VK16WM:$mask, + (bc_v16f32 (v8f64 (X86SubVBroadcast (loadv4f64 addr:$src)))), + VR512:$src0), + (VBROADCASTF32X8rmk VR512:$src0, VK16WM:$mask, addr:$src)>; +def : Pat<(vselect VK16WM:$mask, + (bc_v16i32 (v8i64 (X86SubVBroadcast (loadv4i64 addr:$src)))), + (v16i32 immAllZerosV)), + (VBROADCASTI32X8rmkz VK16WM:$mask, addr:$src)>; +def : Pat<(vselect VK16WM:$mask, + (bc_v16i32 (v8i64 (X86SubVBroadcast (loadv4i64 addr:$src)))), + VR512:$src0), + (VBROADCASTI32X8rmk VR512:$src0, VK16WM:$mask, addr:$src)>; + +def : Pat<(vselect VK8WM:$mask, + (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv4f32 addr:$src)))), + (bc_v8f64 (v16i32 immAllZerosV))), + (VBROADCASTF64X2rmkz VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv4f32 addr:$src)))), + VR512:$src0), + (VBROADCASTF64X2rmk VR512:$src0, VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8i64 (v16i32 (X86SubVBroadcast (bc_v4i32 (loadv2i64 addr:$src))))), + (bc_v8i64 (v16i32 immAllZerosV))), + (VBROADCASTI64X2rmkz VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8i64 (v16i32 (X86SubVBroadcast (bc_v4i32 (loadv2i64 addr:$src))))), + VR512:$src0), + (VBROADCASTI64X2rmk VR512:$src0, VK8WM:$mask, addr:$src)>; +} + +multiclass avx512_common_broadcast_32x2 opc, string OpcodeStr, + AVX512VLVectorVTInfo _Dst, AVX512VLVectorVTInfo _Src> { + let Predicates = [HasDQI] in + defm Z : avx512_broadcast_rm_split, + EVEX_V512; + let Predicates = [HasDQI, HasVLX] in + defm Z256 : avx512_broadcast_rm_split, + EVEX_V256; +} + +multiclass avx512_common_broadcast_i32x2 opc, string OpcodeStr, + AVX512VLVectorVTInfo _Dst, AVX512VLVectorVTInfo _Src> : + avx512_common_broadcast_32x2 { + + let Predicates = [HasDQI, HasVLX] in + defm Z128 : avx512_broadcast_rm_split, + EVEX_V128; +} + +defm VBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2", + avx512vl_i32_info, avx512vl_i64_info>; +defm VBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2", + avx512vl_f32_info, avx512vl_f64_info>; + +let Predicates = [HasVLX] in { +def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256X:$src))), + (VBROADCASTSSZ256r (v4f32 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)))>; +def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256X:$src))), + (VBROADCASTSDZ256r (v2f64 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)))>; +} + +def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))), + (VBROADCASTSSZr (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm)))>; +def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))), + (VBROADCASTSSZr (v4f32 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)))>; + +def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))), + (VBROADCASTSDZr (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm)))>; +def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))), + (VBROADCASTSDZr (v2f64 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)))>; + +//===----------------------------------------------------------------------===// +// AVX-512 BROADCAST MASK TO VECTOR REGISTER +//--- +multiclass avx512_mask_broadcastm opc, string OpcodeStr, + X86VectorVTInfo _, RegisterClass KRC> { + def rr : AVX512XS8I, + EVEX, Sched<[WriteShuffle]>; +} + +multiclass avx512_mask_broadcast opc, string OpcodeStr, + AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> { + let Predicates = [HasCDI] in + defm Z : avx512_mask_broadcastm, EVEX_V512; + let Predicates = [HasCDI, HasVLX] in { + defm Z256 : avx512_mask_broadcastm, EVEX_V256; + defm Z128 : avx512_mask_broadcastm, EVEX_V128; + } +} + +defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", + avx512vl_i32_info, VK16>; +defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", + avx512vl_i64_info, VK8>, VEX_W; + +//===----------------------------------------------------------------------===// +// -- VPERMI2 - 3 source operands form -- +multiclass avx512_perm_i opc, string OpcodeStr, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, X86VectorVTInfo IdxVT> { +let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, + hasSideEffects = 0 in { + defm rr: AVX512_maskable_3src_cast, + EVEX_4V, AVX5128IBase, Sched<[sched]>; + + let mayLoad = 1 in + defm rm: AVX512_maskable_3src_cast, + EVEX_4V, AVX5128IBase, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_perm_i_mb opc, string OpcodeStr, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, X86VectorVTInfo IdxVT> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, + hasSideEffects = 0, mayLoad = 1 in + defm rmb: AVX512_maskable_3src_cast, + AVX5128IBase, EVEX_4V, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_perm_i_sizes opc, string OpcodeStr, + X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTInfo, + AVX512VLVectorVTInfo ShuffleMask> { + defm NAME: avx512_perm_i, + avx512_perm_i_mb, EVEX_V512; + let Predicates = [HasVLX] in { + defm NAME#128: avx512_perm_i, + avx512_perm_i_mb, EVEX_V128; + defm NAME#256: avx512_perm_i, + avx512_perm_i_mb, EVEX_V256; + } +} + +multiclass avx512_perm_i_sizes_bw opc, string OpcodeStr, + X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTInfo, + AVX512VLVectorVTInfo Idx, + Predicate Prd> { + let Predicates = [Prd] in + defm NAME: avx512_perm_i, EVEX_V512; + let Predicates = [Prd, HasVLX] in { + defm NAME#128: avx512_perm_i, EVEX_V128; + defm NAME#256: avx512_perm_i, EVEX_V256; + } +} + +defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d", WriteVarShuffle256, + avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; +defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q", WriteVarShuffle256, + avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; +defm VPERMI2W : avx512_perm_i_sizes_bw<0x75, "vpermi2w", WriteVarShuffle256, + avx512vl_i16_info, avx512vl_i16_info, HasBWI>, + VEX_W, EVEX_CD8<16, CD8VF>; +defm VPERMI2B : avx512_perm_i_sizes_bw<0x75, "vpermi2b", WriteVarShuffle256, + avx512vl_i8_info, avx512vl_i8_info, HasVBMI>, + EVEX_CD8<8, CD8VF>; +defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps", WriteFVarShuffle256, + avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; +defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd", WriteFVarShuffle256, + avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; + +// Extra patterns to deal with extra bitcasts due to passthru and index being +// different types on the fp versions. +multiclass avx512_perm_i_lowering { + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86VPermt2 (_.VT _.RC:$src2), + (IdxVT.VT (bitconvert (CastVT.VT _.RC:$src1))), _.RC:$src3), + (_.VT (bitconvert (CastVT.VT _.RC:$src1))))), + (!cast(InstrStr#"rrk") _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, _.RC:$src3)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86VPermt2 _.RC:$src2, + (IdxVT.VT (bitconvert (CastVT.VT _.RC:$src1))), + (_.LdFrag addr:$src3)), + (_.VT (bitconvert (CastVT.VT _.RC:$src1))))), + (!cast(InstrStr#"rmk") _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86VPermt2 _.RC:$src2, + (IdxVT.VT (bitconvert (CastVT.VT _.RC:$src1))), + (X86VBroadcast (_.ScalarLdFrag addr:$src3))), + (_.VT (bitconvert (CastVT.VT _.RC:$src1))))), + (!cast(InstrStr#"rmbk") _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3)>; +} + +// TODO: Should we add more casts? The vXi64 case is common due to ABI. +defm : avx512_perm_i_lowering<"VPERMI2PS", v16f32_info, v16i32_info, v8i64_info>; +defm : avx512_perm_i_lowering<"VPERMI2PS256", v8f32x_info, v8i32x_info, v4i64x_info>; +defm : avx512_perm_i_lowering<"VPERMI2PS128", v4f32x_info, v4i32x_info, v2i64x_info>; + +// VPERMT2 +multiclass avx512_perm_t opc, string OpcodeStr, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, X86VectorVTInfo IdxVT> { +let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { + defm rr: AVX512_maskable_3src, + EVEX_4V, AVX5128IBase, Sched<[sched]>; + + defm rm: AVX512_maskable_3src, + EVEX_4V, AVX5128IBase, Sched<[sched.Folded, ReadAfterLd]>; + } +} +multiclass avx512_perm_t_mb opc, string OpcodeStr, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, X86VectorVTInfo IdxVT> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in + defm rmb: AVX512_maskable_3src, + AVX5128IBase, EVEX_4V, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_perm_t_sizes opc, string OpcodeStr, + X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTInfo, + AVX512VLVectorVTInfo ShuffleMask> { + defm NAME: avx512_perm_t, + avx512_perm_t_mb, EVEX_V512; + let Predicates = [HasVLX] in { + defm NAME#128: avx512_perm_t, + avx512_perm_t_mb, EVEX_V128; + defm NAME#256: avx512_perm_t, + avx512_perm_t_mb, EVEX_V256; + } +} + +multiclass avx512_perm_t_sizes_bw opc, string OpcodeStr, + X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTInfo, + AVX512VLVectorVTInfo Idx, Predicate Prd> { + let Predicates = [Prd] in + defm NAME: avx512_perm_t, EVEX_V512; + let Predicates = [Prd, HasVLX] in { + defm NAME#128: avx512_perm_t, EVEX_V128; + defm NAME#256: avx512_perm_t, EVEX_V256; + } +} + +defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d", WriteVarShuffle256, + avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; +defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q", WriteVarShuffle256, + avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; +defm VPERMT2W : avx512_perm_t_sizes_bw<0x7D, "vpermt2w", WriteVarShuffle256, + avx512vl_i16_info, avx512vl_i16_info, HasBWI>, + VEX_W, EVEX_CD8<16, CD8VF>; +defm VPERMT2B : avx512_perm_t_sizes_bw<0x7D, "vpermt2b", WriteVarShuffle256, + avx512vl_i8_info, avx512vl_i8_info, HasVBMI>, + EVEX_CD8<8, CD8VF>; +defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps", WriteFVarShuffle256, + avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; +defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd", WriteFVarShuffle256, + avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; + +//===----------------------------------------------------------------------===// +// AVX-512 - BLEND using mask +// + +multiclass WriteFVarBlendask opc, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain, hasSideEffects = 0 in { + def rr : AVX5128I, + EVEX_4V, Sched<[sched]>; + def rrk : AVX5128I, EVEX_4V, EVEX_K, Sched<[sched]>; + def rrkz : AVX5128I, EVEX_4V, EVEX_KZ, Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in { + def rm : AVX5128I, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + def rmk : AVX5128I, EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + def rmkz : AVX5128I, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable; + } + } +} +multiclass WriteFVarBlendask_rmb opc, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let mayLoad = 1, hasSideEffects = 0 in { + def rmbk : AVX5128I, + EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + + def rmbkz : AVX5128I, + EVEX_4V, EVEX_KZ, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable; + + def rmb : AVX5128I, + EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass blendmask_dq opc, string OpcodeStr, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo> { + defm Z : WriteFVarBlendask, + WriteFVarBlendask_rmb, + EVEX_V512; + + let Predicates = [HasVLX] in { + defm Z256 : WriteFVarBlendask, + WriteFVarBlendask_rmb, + EVEX_V256; + defm Z128 : WriteFVarBlendask, + WriteFVarBlendask_rmb, + EVEX_V128; + } +} + +multiclass blendmask_bw opc, string OpcodeStr, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo> { + let Predicates = [HasBWI] in + defm Z : WriteFVarBlendask, + EVEX_V512; + + let Predicates = [HasBWI, HasVLX] in { + defm Z256 : WriteFVarBlendask, + EVEX_V256; + defm Z128 : WriteFVarBlendask, + EVEX_V128; + } +} + +defm VBLENDMPS : blendmask_dq<0x65, "vblendmps", SchedWriteFVarBlend, + avx512vl_f32_info>; +defm VBLENDMPD : blendmask_dq<0x65, "vblendmpd", SchedWriteFVarBlend, + avx512vl_f64_info>, VEX_W; +defm VPBLENDMD : blendmask_dq<0x64, "vpblendmd", SchedWriteVarBlend, + avx512vl_i32_info>; +defm VPBLENDMQ : blendmask_dq<0x64, "vpblendmq", SchedWriteVarBlend, + avx512vl_i64_info>, VEX_W; +defm VPBLENDMB : blendmask_bw<0x66, "vpblendmb", SchedWriteVarBlend, + avx512vl_i8_info>; +defm VPBLENDMW : blendmask_bw<0x66, "vpblendmw", SchedWriteVarBlend, + avx512vl_i16_info>, VEX_W; + +//===----------------------------------------------------------------------===// +// Compare Instructions +//===----------------------------------------------------------------------===// + +// avx512_cmp_scalar - AVX512 CMPSS and CMPSD + +multiclass avx512_cmp_scalar { + defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "$src2, $src1", "$src1, $src2", + (OpNode (_.VT _.RC:$src1), + (_.VT _.RC:$src2), + imm:$cc)>, EVEX_4V, Sched<[sched]>; + let mayLoad = 1 in + defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.IntScalarMemOp:$src2, AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "$src2, $src1", "$src1, $src2", + (OpNode (_.VT _.RC:$src1), _.ScalarIntMemCPat:$src2, + imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[sched.Folded, ReadAfterLd]>; + + defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "{sae}, $src2, $src1", "$src1, $src2, {sae}", + (OpNodeRnd (_.VT _.RC:$src1), + (_.VT _.RC:$src2), + imm:$cc, + (i32 FROUND_NO_EXC))>, + EVEX_4V, EVEX_B, Sched<[sched]>; + // Accept explicit immediate argument form instead of comparison code. + let isAsmParserOnly = 1, hasSideEffects = 0 in { + defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _, + (outs VK1:$dst), + (ins _.RC:$src1, _.RC:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V, + Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in + defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, $src2, $src1", "$src1, $src2, $cc">, + EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable; + + defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.RC:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, {sae}, $src2, $src1","$src1, $src2, {sae}, $cc">, + EVEX_4V, EVEX_B, Sched<[sched]>, NotMemoryFoldable; + }// let isAsmParserOnly = 1, hasSideEffects = 0 + + let isCodeGenOnly = 1 in { + let isCommutable = 1 in + def rr : AVX512Ii8<0xC2, MRMSrcReg, + (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc), + !strconcat("vcmp${cc}", _.Suffix, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set _.KRC:$dst, (OpNode _.FRC:$src1, + _.FRC:$src2, + imm:$cc))]>, + EVEX_4V, Sched<[sched]>; + def rm : AVX512Ii8<0xC2, MRMSrcMem, + (outs _.KRC:$dst), + (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc), + !strconcat("vcmp${cc}", _.Suffix, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set _.KRC:$dst, (OpNode _.FRC:$src1, + (_.ScalarLdFrag addr:$src2), + imm:$cc))]>, + EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +let Predicates = [HasAVX512] in { + let ExeDomain = SSEPackedSingle in + defm VCMPSSZ : avx512_cmp_scalar, AVX512XSIi8Base; + let ExeDomain = SSEPackedDouble in + defm VCMPSDZ : avx512_cmp_scalar, AVX512XDIi8Base, VEX_W; +} + +multiclass avx512_icmp_packed opc, string OpcodeStr, PatFrag OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + bit IsCommutable> { + let isCommutable = IsCommutable in + def rr : AVX512BI, + EVEX_4V, Sched<[sched]>; + def rm : AVX512BI, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + let isCommutable = IsCommutable in + def rrk : AVX512BI, + EVEX_4V, EVEX_K, Sched<[sched]>; + def rmk : AVX512BI, + EVEX_4V, EVEX_K, Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_icmp_packed_rmb opc, string OpcodeStr, PatFrag OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + bit IsCommutable> : + avx512_icmp_packed { + def rmb : AVX512BI, + EVEX_4V, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + def rmbk : AVX512BI, + EVEX_4V, EVEX_K, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_icmp_packed_vl opc, string OpcodeStr, PatFrag OpNode, + X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo, Predicate prd, + bit IsCommutable = 0> { + let Predicates = [prd] in + defm Z : avx512_icmp_packed, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_icmp_packed, EVEX_V256; + defm Z128 : avx512_icmp_packed, EVEX_V128; + } +} + +multiclass avx512_icmp_packed_rmb_vl opc, string OpcodeStr, + PatFrag OpNode, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo, + Predicate prd, bit IsCommutable = 0> { + let Predicates = [prd] in + defm Z : avx512_icmp_packed_rmb, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_icmp_packed_rmb, EVEX_V256; + defm Z128 : avx512_icmp_packed_rmb, EVEX_V128; + } +} + +// This fragment treats X86cmpm as commutable to help match loads in both +// operands for PCMPEQ. +def X86setcc_commute : SDNode<"ISD::SETCC", SDTSetCC, [SDNPCommutative]>; +def X86pcmpeqm_c : PatFrag<(ops node:$src1, node:$src2), + (X86setcc_commute node:$src1, node:$src2, SETEQ)>; +def X86pcmpgtm : PatFrag<(ops node:$src1, node:$src2), + (setcc node:$src1, node:$src2, SETGT)>; + +// AddedComplexity is needed because the explicit SETEQ/SETGT CondCode doesn't +// increase the pattern complexity the way an immediate would. +let AddedComplexity = 2 in { +// FIXME: Is there a better scheduler class for VPCMP? +defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm_c, + SchedWriteVecALU, avx512vl_i8_info, HasBWI, 1>, + EVEX_CD8<8, CD8VF>, VEX_WIG; + +defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm_c, + SchedWriteVecALU, avx512vl_i16_info, HasBWI, 1>, + EVEX_CD8<16, CD8VF>, VEX_WIG; + +defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm_c, + SchedWriteVecALU, avx512vl_i32_info, HasAVX512, 1>, + EVEX_CD8<32, CD8VF>; + +defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm_c, + SchedWriteVecALU, avx512vl_i64_info, HasAVX512, 1>, + T8PD, VEX_W, EVEX_CD8<64, CD8VF>; + +defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm, + SchedWriteVecALU, avx512vl_i8_info, HasBWI>, + EVEX_CD8<8, CD8VF>, VEX_WIG; + +defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm, + SchedWriteVecALU, avx512vl_i16_info, HasBWI>, + EVEX_CD8<16, CD8VF>, VEX_WIG; + +defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm, + SchedWriteVecALU, avx512vl_i32_info, HasAVX512>, + EVEX_CD8<32, CD8VF>; + +defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm, + SchedWriteVecALU, avx512vl_i64_info, HasAVX512>, + T8PD, VEX_W, EVEX_CD8<64, CD8VF>; +} + +multiclass avx512_icmp_cc opc, string Suffix, PatFrag Frag, + PatFrag CommFrag, X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Name> { + let isCommutable = 1 in + def rri : AVX512AIi8, + EVEX_4V, Sched<[sched]>; + def rmi : AVX512AIi8, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + let isCommutable = 1 in + def rrik : AVX512AIi8, + EVEX_4V, EVEX_K, Sched<[sched]>; + def rmik : AVX512AIi8, + EVEX_4V, EVEX_K, Sched<[sched.Folded, ReadAfterLd]>; + + // Accept explicit immediate argument form instead of comparison code. + let isAsmParserOnly = 1, hasSideEffects = 0 in { + def rri_alt : AVX512AIi8, + EVEX_4V, Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in + def rmi_alt : AVX512AIi8, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable; + def rrik_alt : AVX512AIi8, + EVEX_4V, EVEX_K, Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in + def rmik_alt : AVX512AIi8, + EVEX_4V, EVEX_K, Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + } + + def : Pat<(_.KVT (CommFrag:$cc (bitconvert (_.LdFrag addr:$src2)), + (_.VT _.RC:$src1), cond)), + (!cast(Name#_.ZSuffix#"rmi") + _.RC:$src1, addr:$src2, (CommFrag.OperandTransform $cc))>; + + def : Pat<(and _.KRCWM:$mask, + (_.KVT (CommFrag:$cc (bitconvert (_.LdFrag addr:$src2)), + (_.VT _.RC:$src1), cond))), + (!cast(Name#_.ZSuffix#"rmik") + _.KRCWM:$mask, _.RC:$src1, addr:$src2, + (CommFrag.OperandTransform $cc))>; +} + +multiclass avx512_icmp_cc_rmb opc, string Suffix, PatFrag Frag, + PatFrag CommFrag, X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Name> : + avx512_icmp_cc { + def rmib : AVX512AIi8, + EVEX_4V, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + def rmibk : AVX512AIi8, + EVEX_4V, EVEX_K, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + + // Accept explicit immediate argument form instead of comparison code. + let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in { + def rmib_alt : AVX512AIi8, + EVEX_4V, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + def rmibk_alt : AVX512AIi8, + EVEX_4V, EVEX_K, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + } + + def : Pat<(_.KVT (CommFrag:$cc (X86VBroadcast (_.ScalarLdFrag addr:$src2)), + (_.VT _.RC:$src1), cond)), + (!cast(Name#_.ZSuffix#"rmib") + _.RC:$src1, addr:$src2, (CommFrag.OperandTransform $cc))>; + + def : Pat<(and _.KRCWM:$mask, + (_.KVT (CommFrag:$cc (X86VBroadcast + (_.ScalarLdFrag addr:$src2)), + (_.VT _.RC:$src1), cond))), + (!cast(Name#_.ZSuffix#"rmibk") + _.KRCWM:$mask, _.RC:$src1, addr:$src2, + (CommFrag.OperandTransform $cc))>; +} + +multiclass avx512_icmp_cc_vl opc, string Suffix, PatFrag Frag, + PatFrag CommFrag, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo, Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_icmp_cc, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_icmp_cc, EVEX_V256; + defm Z128 : avx512_icmp_cc, EVEX_V128; + } +} + +multiclass avx512_icmp_cc_rmb_vl opc, string Suffix, PatFrag Frag, + PatFrag CommFrag, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo, Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_icmp_cc_rmb, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_icmp_cc_rmb, EVEX_V256; + defm Z128 : avx512_icmp_cc_rmb, EVEX_V128; + } +} + +def X86pcmpm_imm : SDNodeXForm(N->getOperand(2))->get(); + uint8_t SSECC = X86::getVPCMPImmForCond(CC); + return getI8Imm(SSECC, SDLoc(N)); +}]>; + +// Swapped operand version of the above. +def X86pcmpm_imm_commute : SDNodeXForm(N->getOperand(2))->get(); + uint8_t SSECC = X86::getVPCMPImmForCond(CC); + SSECC = X86::getSwappedVPCMPImm(SSECC); + return getI8Imm(SSECC, SDLoc(N)); +}]>; + +def X86pcmpm : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (setcc node:$src1, node:$src2, node:$cc), [{ + ISD::CondCode CC = cast(N->getOperand(2))->get(); + return !ISD::isUnsignedIntSetCC(CC); +}], X86pcmpm_imm>; + +// Same as above, but commutes immediate. Use for load folding. +def X86pcmpm_commute : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (setcc node:$src1, node:$src2, node:$cc), [{ + ISD::CondCode CC = cast(N->getOperand(2))->get(); + return !ISD::isUnsignedIntSetCC(CC); +}], X86pcmpm_imm_commute>; + +def X86pcmpum : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (setcc node:$src1, node:$src2, node:$cc), [{ + ISD::CondCode CC = cast(N->getOperand(2))->get(); + return ISD::isUnsignedIntSetCC(CC); +}], X86pcmpm_imm>; + +// Same as above, but commutes immediate. Use for load folding. +def X86pcmpum_commute : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (setcc node:$src1, node:$src2, node:$cc), [{ + ISD::CondCode CC = cast(N->getOperand(2))->get(); + return ISD::isUnsignedIntSetCC(CC); +}], X86pcmpm_imm_commute>; + +// FIXME: Is there a better scheduler class for VPCMP/VPCMPU? +defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86pcmpm, X86pcmpm_commute, + SchedWriteVecALU, avx512vl_i8_info, HasBWI>, + EVEX_CD8<8, CD8VF>; +defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86pcmpum, X86pcmpum_commute, + SchedWriteVecALU, avx512vl_i8_info, HasBWI>, + EVEX_CD8<8, CD8VF>; + +defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86pcmpm, X86pcmpm_commute, + SchedWriteVecALU, avx512vl_i16_info, HasBWI>, + VEX_W, EVEX_CD8<16, CD8VF>; +defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86pcmpum, X86pcmpum_commute, + SchedWriteVecALU, avx512vl_i16_info, HasBWI>, + VEX_W, EVEX_CD8<16, CD8VF>; + +defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86pcmpm, X86pcmpm_commute, + SchedWriteVecALU, avx512vl_i32_info, + HasAVX512>, EVEX_CD8<32, CD8VF>; +defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86pcmpum, X86pcmpum_commute, + SchedWriteVecALU, avx512vl_i32_info, + HasAVX512>, EVEX_CD8<32, CD8VF>; + +defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86pcmpm, X86pcmpm_commute, + SchedWriteVecALU, avx512vl_i64_info, + HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>; +defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86pcmpum, X86pcmpum_commute, + SchedWriteVecALU, avx512vl_i64_info, + HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>; + +multiclass avx512_vcmp_common { + defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "$src2, $src1", "$src1, $src2", + (X86cmpm (_.VT _.RC:$src1), + (_.VT _.RC:$src2), + imm:$cc), 1>, + Sched<[sched]>; + + defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _, + (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "$src2, $src1", "$src1, $src2", + (X86cmpm (_.VT _.RC:$src1), + (_.VT (bitconvert (_.LdFrag addr:$src2))), + imm:$cc)>, + Sched<[sched.Folded, ReadAfterLd]>; + + defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "${src2}"##_.BroadcastStr##", $src1", + "$src1, ${src2}"##_.BroadcastStr, + (X86cmpm (_.VT _.RC:$src1), + (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))), + imm:$cc)>, + EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + // Accept explicit immediate argument form instead of comparison code. + let isAsmParserOnly = 1, hasSideEffects = 0 in { + defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.RC:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, $src2, $src1", "$src1, $src2, $cc">, + Sched<[sched]>, NotMemoryFoldable; + + let mayLoad = 1 in { + defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, $src2, $src1", "$src1, $src2, $cc">, + Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + + defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, ${src2}"##_.BroadcastStr##", $src1", + "$src1, ${src2}"##_.BroadcastStr##", $cc">, + EVEX_B, Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + } + } + + // Patterns for selecting with loads in other operand. + def : Pat<(X86cmpm (_.LdFrag addr:$src2), (_.VT _.RC:$src1), + CommutableCMPCC:$cc), + (!cast(Name#_.ZSuffix#"rmi") _.RC:$src1, addr:$src2, + imm:$cc)>; + + def : Pat<(and _.KRCWM:$mask, (X86cmpm (_.LdFrag addr:$src2), + (_.VT _.RC:$src1), + CommutableCMPCC:$cc)), + (!cast(Name#_.ZSuffix#"rmik") _.KRCWM:$mask, + _.RC:$src1, addr:$src2, + imm:$cc)>; + + def : Pat<(X86cmpm (X86VBroadcast (_.ScalarLdFrag addr:$src2)), + (_.VT _.RC:$src1), CommutableCMPCC:$cc), + (!cast(Name#_.ZSuffix#"rmbi") _.RC:$src1, addr:$src2, + imm:$cc)>; + + def : Pat<(and _.KRCWM:$mask, (X86cmpm (X86VBroadcast + (_.ScalarLdFrag addr:$src2)), + (_.VT _.RC:$src1), + CommutableCMPCC:$cc)), + (!cast(Name#_.ZSuffix#"rmbik") _.KRCWM:$mask, + _.RC:$src1, addr:$src2, + imm:$cc)>; +} + +multiclass avx512_vcmp_sae { + // comparison code form (VCMP[EQ/LT/LE/...] + defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "{sae}, $src2, $src1", "$src1, $src2, {sae}", + (X86cmpmRnd (_.VT _.RC:$src1), + (_.VT _.RC:$src2), + imm:$cc, + (i32 FROUND_NO_EXC))>, + EVEX_B, Sched<[sched]>; + + let isAsmParserOnly = 1, hasSideEffects = 0 in { + defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.RC:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, {sae}, $src2, $src1", + "$src1, $src2, {sae}, $cc">, + EVEX_B, Sched<[sched]>, NotMemoryFoldable; + } +} + +multiclass avx512_vcmp { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcmp_common, + avx512_vcmp_sae, EVEX_V512; + + } + let Predicates = [HasAVX512,HasVLX] in { + defm Z128 : avx512_vcmp_common, EVEX_V128; + defm Z256 : avx512_vcmp_common, EVEX_V256; + } +} + +defm VCMPPD : avx512_vcmp, + AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; +defm VCMPPS : avx512_vcmp, + AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; + +// Patterns to select fp compares with load as first operand. +let Predicates = [HasAVX512] in { + def : Pat<(v1i1 (X86cmpms (loadf64 addr:$src2), FR64X:$src1, + CommutableCMPCC:$cc)), + (VCMPSDZrm FR64X:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(v1i1 (X86cmpms (loadf32 addr:$src2), FR32X:$src1, + CommutableCMPCC:$cc)), + (VCMPSSZrm FR32X:$src1, addr:$src2, imm:$cc)>; +} + +// ---------------------------------------------------------------- +// FPClass +//handle fpclass instruction mask = op(reg_scalar,imm) +// op(mem_scalar,imm) +multiclass avx512_scalar_fpclass opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + Predicate prd> { + let Predicates = [prd], ExeDomain = _.ExeDomain in { + def rr : AVX512, + Sched<[sched]>; + def rrk : AVX512, + EVEX_K, Sched<[sched]>; + def rm : AVX512, + Sched<[sched.Folded, ReadAfterLd]>; + def rmk : AVX512, + EVEX_K, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +//handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm) +// fpclass(reg_vec, mem_vec, imm) +// fpclass(reg_vec, broadcast(eltVt), imm) +multiclass avx512_vector_fpclass opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + string mem, string broadcast>{ + let ExeDomain = _.ExeDomain in { + def rr : AVX512, + Sched<[sched]>; + def rrk : AVX512, + EVEX_K, Sched<[sched]>; + def rm : AVX512, + Sched<[sched.Folded, ReadAfterLd]>; + def rmk : AVX512, + EVEX_K, Sched<[sched.Folded, ReadAfterLd]>; + def rmb : AVX512, + EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + def rmbk : AVX512, + EVEX_B, EVEX_K, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_vector_fpclass_all opc, SDNode OpNode, + X86SchedWriteWidths sched, Predicate prd, + string broadcast>{ + let Predicates = [prd] in { + defm Z : avx512_vector_fpclass, EVEX_V512; + } + let Predicates = [prd, HasVLX] in { + defm Z128 : avx512_vector_fpclass, EVEX_V128; + defm Z256 : avx512_vector_fpclass, EVEX_V256; + } +} + +multiclass avx512_fp_fpclass_all opcVec, + bits<8> opcScalar, SDNode VecOpNode, + SDNode ScalarOpNode, X86SchedWriteWidths sched, + Predicate prd> { + defm PS : avx512_vector_fpclass_all, + EVEX_CD8<32, CD8VF>; + defm PD : avx512_vector_fpclass_all, + EVEX_CD8<64, CD8VF> , VEX_W; + defm SSZ : avx512_scalar_fpclass, + EVEX_CD8<32, CD8VT1>; + defm SDZ : avx512_scalar_fpclass, + EVEX_CD8<64, CD8VT1>, VEX_W; +} + +defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass, + X86Vfpclasss, SchedWriteFCmp, HasDQI>, + AVX512AIi8Base, EVEX; + +//----------------------------------------------------------------- +// Mask register copy, including +// - copy between mask registers +// - load/store mask registers +// - copy from GPR to mask register and vice versa +// +multiclass avx512_mask_mov opc_kk, bits<8> opc_km, bits<8> opc_mk, + string OpcodeStr, RegisterClass KRC, + ValueType vvt, X86MemOperand x86memop> { + let isMoveReg = 1, hasSideEffects = 0, SchedRW = [WriteMove] in + def kk : I, + Sched<[WriteMove]>; + def km : I, + Sched<[WriteLoad]>; + def mk : I, + Sched<[WriteStore]>; +} + +multiclass avx512_mask_mov_gpr opc_kr, bits<8> opc_rk, + string OpcodeStr, + RegisterClass KRC, RegisterClass GRC> { + let hasSideEffects = 0 in { + def kr : I, + Sched<[WriteMove]>; + def rk : I, + Sched<[WriteMove]>; + } +} + +let Predicates = [HasDQI] in + defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>, + avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>, + VEX, PD; + +let Predicates = [HasAVX512] in + defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>, + avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>, + VEX, PS; + +let Predicates = [HasBWI] in { + defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>, + VEX, PD, VEX_W; + defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>, + VEX, XD; + defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>, + VEX, PS, VEX_W; + defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>, + VEX, XD, VEX_W; +} + +// GR from/to mask register +def : Pat<(v16i1 (bitconvert (i16 GR16:$src))), + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit)), VK16)>; +def : Pat<(i16 (bitconvert (v16i1 VK16:$src))), + (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK16:$src, GR32)), sub_16bit)>; + +def : Pat<(v8i1 (bitconvert (i8 GR8:$src))), + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), GR8:$src, sub_8bit)), VK8)>; +def : Pat<(i8 (bitconvert (v8i1 VK8:$src))), + (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK8:$src, GR32)), sub_8bit)>; + +def : Pat<(i32 (zext (i16 (bitconvert (v16i1 VK16:$src))))), + (KMOVWrk VK16:$src)>; +def : Pat<(i32 (anyext (i16 (bitconvert (v16i1 VK16:$src))))), + (COPY_TO_REGCLASS VK16:$src, GR32)>; + +def : Pat<(i32 (zext (i8 (bitconvert (v8i1 VK8:$src))))), + (KMOVBrk VK8:$src)>, Requires<[HasDQI]>; +def : Pat<(i32 (anyext (i8 (bitconvert (v8i1 VK8:$src))))), + (COPY_TO_REGCLASS VK8:$src, GR32)>; + +def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), + (COPY_TO_REGCLASS GR32:$src, VK32)>; +def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), + (COPY_TO_REGCLASS VK32:$src, GR32)>; +def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), + (COPY_TO_REGCLASS GR64:$src, VK64)>; +def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), + (COPY_TO_REGCLASS VK64:$src, GR64)>; + +// Load/store kreg +let Predicates = [HasDQI] in { + def : Pat<(store VK1:$src, addr:$dst), + (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK8))>; + + def : Pat<(v1i1 (load addr:$src)), + (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK1)>; + def : Pat<(v2i1 (load addr:$src)), + (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK2)>; + def : Pat<(v4i1 (load addr:$src)), + (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK4)>; +} + +let Predicates = [HasAVX512] in { + def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))), + (COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK8)>; +} + +let Predicates = [HasAVX512] in { + multiclass operation_gpr_mask_copy_lowering { + def : Pat<(maskVT (scalar_to_vector GR32:$src)), + (COPY_TO_REGCLASS GR32:$src, maskRC)>; + + def : Pat<(maskVT (scalar_to_vector GR8:$src)), + (COPY_TO_REGCLASS (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, sub_8bit), maskRC)>; + } + + defm : operation_gpr_mask_copy_lowering; + defm : operation_gpr_mask_copy_lowering; + defm : operation_gpr_mask_copy_lowering; + defm : operation_gpr_mask_copy_lowering; + defm : operation_gpr_mask_copy_lowering; + defm : operation_gpr_mask_copy_lowering; + defm : operation_gpr_mask_copy_lowering; + + def : Pat<(insert_subvector (v16i1 immAllZerosV), + (v1i1 (scalar_to_vector GR8:$src)), (iPTR 0)), + (COPY_TO_REGCLASS + (KMOVWkr (AND32ri8 + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, sub_8bit), + (i32 1))), VK16)>; +} + +// Mask unary operation +// - KNOT +multiclass avx512_mask_unop opc, string OpcodeStr, + RegisterClass KRC, SDPatternOperator OpNode, + X86FoldableSchedWrite sched, Predicate prd> { + let Predicates = [prd] in + def rr : I, + Sched<[sched]>; +} + +multiclass avx512_mask_unop_all opc, string OpcodeStr, + SDPatternOperator OpNode, + X86FoldableSchedWrite sched> { + defm B : avx512_mask_unop, VEX, PD; + defm W : avx512_mask_unop, VEX, PS; + defm D : avx512_mask_unop, VEX, PD, VEX_W; + defm Q : avx512_mask_unop, VEX, PS, VEX_W; +} + +// TODO - do we need a X86SchedWriteWidths::KMASK type? +defm KNOT : avx512_mask_unop_all<0x44, "knot", vnot, SchedWriteVecLogic.XMM>; + +// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit +let Predicates = [HasAVX512, NoDQI] in +def : Pat<(vnot VK8:$src), + (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>; + +def : Pat<(vnot VK4:$src), + (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src, VK16)), VK4)>; +def : Pat<(vnot VK2:$src), + (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src, VK16)), VK2)>; + +// Mask binary operation +// - KAND, KANDN, KOR, KXNOR, KXOR +multiclass avx512_mask_binop opc, string OpcodeStr, + RegisterClass KRC, SDPatternOperator OpNode, + X86FoldableSchedWrite sched, Predicate prd, + bit IsCommutable> { + let Predicates = [prd], isCommutable = IsCommutable in + def rr : I, + Sched<[sched]>; +} + +multiclass avx512_mask_binop_all opc, string OpcodeStr, + SDPatternOperator OpNode, + X86FoldableSchedWrite sched, bit IsCommutable, + Predicate prdW = HasAVX512> { + defm B : avx512_mask_binop, VEX_4V, VEX_L, PD; + defm W : avx512_mask_binop, VEX_4V, VEX_L, PS; + defm D : avx512_mask_binop, VEX_4V, VEX_L, VEX_W, PD; + defm Q : avx512_mask_binop, VEX_4V, VEX_L, VEX_W, PS; +} + +def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>; +def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>; +// These nodes use 'vnot' instead of 'not' to support vectors. +def vandn : PatFrag<(ops node:$i0, node:$i1), (and (vnot node:$i0), node:$i1)>; +def vxnor : PatFrag<(ops node:$i0, node:$i1), (vnot (xor node:$i0, node:$i1))>; + +// TODO - do we need a X86SchedWriteWidths::KMASK type? +defm KAND : avx512_mask_binop_all<0x41, "kand", and, SchedWriteVecLogic.XMM, 1>; +defm KOR : avx512_mask_binop_all<0x45, "kor", or, SchedWriteVecLogic.XMM, 1>; +defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", vxnor, SchedWriteVecLogic.XMM, 1>; +defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, SchedWriteVecLogic.XMM, 1>; +defm KANDN : avx512_mask_binop_all<0x42, "kandn", vandn, SchedWriteVecLogic.XMM, 0>; +defm KADD : avx512_mask_binop_all<0x4A, "kadd", X86kadd, SchedWriteVecLogic.XMM, 1, HasDQI>; + +multiclass avx512_binop_pat { + // With AVX512F, 8-bit mask is promoted to 16-bit mask, + // for the DQI set, this type is legal and KxxxB instruction is used + let Predicates = [NoDQI] in + def : Pat<(VOpNode VK8:$src1, VK8:$src2), + (COPY_TO_REGCLASS + (Inst (COPY_TO_REGCLASS VK8:$src1, VK16), + (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>; + + // All types smaller than 8 bits require conversion anyway + def : Pat<(OpNode VK1:$src1, VK1:$src2), + (COPY_TO_REGCLASS (Inst + (COPY_TO_REGCLASS VK1:$src1, VK16), + (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>; + def : Pat<(VOpNode VK2:$src1, VK2:$src2), + (COPY_TO_REGCLASS (Inst + (COPY_TO_REGCLASS VK2:$src1, VK16), + (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>; + def : Pat<(VOpNode VK4:$src1, VK4:$src2), + (COPY_TO_REGCLASS (Inst + (COPY_TO_REGCLASS VK4:$src1, VK16), + (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>; +} + +defm : avx512_binop_pat; +defm : avx512_binop_pat; +defm : avx512_binop_pat; +defm : avx512_binop_pat; +defm : avx512_binop_pat; + +// Mask unpacking +multiclass avx512_mask_unpck { + let Predicates = [prd] in { + let hasSideEffects = 0 in + def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst), + (ins KRC:$src1, KRC:$src2), + "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + VEX_4V, VEX_L, Sched<[sched]>; + + def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)), + (!cast(NAME##rr) + (COPY_TO_REGCLASS KRCSrc:$src2, KRC), + (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>; + } +} + +defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, WriteShuffle, HasAVX512>, PD; +defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, WriteShuffle, HasBWI>, PS; +defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, WriteShuffle, HasBWI>, PS, VEX_W; + +// Mask bit testing +multiclass avx512_mask_testop opc, string OpcodeStr, RegisterClass KRC, + SDNode OpNode, X86FoldableSchedWrite sched, + Predicate prd> { + let Predicates = [prd], Defs = [EFLAGS] in + def rr : I, + Sched<[sched]>; +} + +multiclass avx512_mask_testop_w opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + Predicate prdW = HasAVX512> { + defm B : avx512_mask_testop, + VEX, PD; + defm W : avx512_mask_testop, + VEX, PS; + defm Q : avx512_mask_testop, + VEX, PS, VEX_W; + defm D : avx512_mask_testop, + VEX, PD, VEX_W; +} + +// TODO - do we need a X86SchedWriteWidths::KMASK type? +defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest, SchedWriteVecLogic.XMM>; +defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, SchedWriteVecLogic.XMM, HasDQI>; + +// Mask shift +multiclass avx512_mask_shiftop opc, string OpcodeStr, RegisterClass KRC, + SDNode OpNode, X86FoldableSchedWrite sched> { + let Predicates = [HasAVX512] in + def ri : Ii8, + Sched<[sched]>; +} + +multiclass avx512_mask_shiftop_w opc1, bits<8> opc2, string OpcodeStr, + SDNode OpNode, X86FoldableSchedWrite sched> { + defm W : avx512_mask_shiftop, VEX, TAPD, VEX_W; + let Predicates = [HasDQI] in + defm B : avx512_mask_shiftop, VEX, TAPD; + let Predicates = [HasBWI] in { + defm Q : avx512_mask_shiftop, VEX, TAPD, VEX_W; + defm D : avx512_mask_shiftop, VEX, TAPD; + } +} + +defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86kshiftl, WriteShuffle>; +defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86kshiftr, WriteShuffle>; + +// Patterns for comparing 128/256-bit integer vectors using 512-bit instruction. +multiclass axv512_icmp_packed_no_vlx_lowering { + def : Pat<(Narrow.KVT (Frag (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2))), + (COPY_TO_REGCLASS + (!cast(InstStr#"Zrr") + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx))), + Narrow.KRC)>; + + def : Pat<(Narrow.KVT (and Narrow.KRC:$mask, + (Frag (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2)))), + (COPY_TO_REGCLASS + (!cast(InstStr#"Zrrk") + (COPY_TO_REGCLASS Narrow.KRC:$mask, Wide.KRC), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx))), + Narrow.KRC)>; +} + +// Patterns for comparing 128/256-bit integer vectors using 512-bit instruction. +multiclass axv512_icmp_packed_cc_no_vlx_lowering { +def : Pat<(Narrow.KVT (Frag:$cc (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2), cond)), + (COPY_TO_REGCLASS + (!cast(InstStr##Zrri) + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)), + (Frag.OperandTransform $cc)), Narrow.KRC)>; + +def : Pat<(Narrow.KVT (and Narrow.KRC:$mask, + (Narrow.KVT (Frag:$cc (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2), + cond)))), + (COPY_TO_REGCLASS (!cast(InstStr##Zrrik) + (COPY_TO_REGCLASS Narrow.KRC:$mask, Wide.KRC), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)), + (Frag.OperandTransform $cc)), Narrow.KRC)>; +} + +// Same as above, but for fp types which don't use PatFrags. +multiclass axv512_cmp_packed_cc_no_vlx_lowering { +def : Pat<(Narrow.KVT (OpNode (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2), imm:$cc)), + (COPY_TO_REGCLASS + (!cast(InstStr##Zrri) + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)), + imm:$cc), Narrow.KRC)>; + +def : Pat<(Narrow.KVT (and Narrow.KRC:$mask, + (OpNode (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2), imm:$cc))), + (COPY_TO_REGCLASS (!cast(InstStr##Zrrik) + (COPY_TO_REGCLASS Narrow.KRC:$mask, Wide.KRC), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)), + imm:$cc), Narrow.KRC)>; +} + +let Predicates = [HasAVX512, NoVLX] in { + // AddedComplexity is needed because the explicit SETEQ/SETGT CondCode doesn't + // increase the pattern complexity the way an immediate would. + let AddedComplexity = 2 in { + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + } + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_cmp_packed_cc_no_vlx_lowering; + defm : axv512_cmp_packed_cc_no_vlx_lowering; + defm : axv512_cmp_packed_cc_no_vlx_lowering; + defm : axv512_cmp_packed_cc_no_vlx_lowering; +} + +let Predicates = [HasBWI, NoVLX] in { + // AddedComplexity is needed because the explicit SETEQ/SETGT CondCode doesn't + // increase the pattern complexity the way an immediate would. + let AddedComplexity = 2 in { + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + } + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; +} + +// Mask setting all 0s or 1s +multiclass avx512_mask_setop { + let Predicates = [HasAVX512] in + let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1, + SchedRW = [WriteZero] in + def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "", + [(set KRC:$dst, (VT Val))]>; +} + +multiclass avx512_mask_setop_w { + defm W : avx512_mask_setop; + defm D : avx512_mask_setop; + defm Q : avx512_mask_setop; +} + +defm KSET0 : avx512_mask_setop_w; +defm KSET1 : avx512_mask_setop_w; + +// With AVX-512 only, 8-bit mask is promoted to 16-bit mask. +let Predicates = [HasAVX512] in { + def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>; + def : Pat<(v4i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK4)>; + def : Pat<(v2i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK2)>; + def : Pat<(v1i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK1)>; + def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>; + def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>; + def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>; + def : Pat<(v1i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK1)>; +} + +// Patterns for kmask insert_subvector/extract_subvector to/from index=0 +multiclass operation_subvector_mask_lowering { + def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))), + (subVT (COPY_TO_REGCLASS RC:$src, subRC))>; + + def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))), + (VT (COPY_TO_REGCLASS subRC:$src, RC))>; +} +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; + +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; + +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; + +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; + +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; + +defm : operation_subvector_mask_lowering; + +//===----------------------------------------------------------------------===// +// AVX-512 - Aligned and unaligned load and store +// + +multiclass avx512_load opc, string OpcodeStr, string Name, + X86VectorVTInfo _, PatFrag ld_frag, PatFrag mload, + X86SchedWriteMoveLS Sched, string EVEX2VEXOvrd, + bit NoRMPattern = 0, + SDPatternOperator SelectOprr = vselect> { + let hasSideEffects = 0 in { + let isMoveReg = 1 in + def rr : AVX512PI, EVEX, Sched<[Sched.RR]>, + EVEX2VEXOverride; + def rrkz : AVX512PI, + EVEX, EVEX_KZ, Sched<[Sched.RR]>; + + let mayLoad = 1, canFoldAsLoad = 1, isReMaterializable = 1 in + def rm : AVX512PI, EVEX, Sched<[Sched.RM]>, + EVEX2VEXOverride; + + let Constraints = "$src0 = $dst", isConvertibleToThreeAddress = 1 in { + def rrk : AVX512PI, + EVEX, EVEX_K, Sched<[Sched.RR]>; + def rmk : AVX512PI, + EVEX, EVEX_K, Sched<[Sched.RM]>; + } + def rmkz : AVX512PI, EVEX, EVEX_KZ, Sched<[Sched.RM]>; + } + def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)), + (!cast(Name#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>; + + def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)), + (!cast(Name#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>; + + def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))), + (!cast(Name#_.ZSuffix##rmk) _.RC:$src0, + _.KRCWM:$mask, addr:$ptr)>; +} + +multiclass avx512_alignedload_vl opc, string OpcodeStr, + AVX512VLVectorVTInfo _, Predicate prd, + X86SchedWriteMoveLSWidths Sched, + string EVEX2VEXOvrd, bit NoRMPattern = 0> { + let Predicates = [prd] in + defm Z : avx512_load, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_load, EVEX_V256; + defm Z128 : avx512_load, EVEX_V128; + } +} + +multiclass avx512_load_vl opc, string OpcodeStr, + AVX512VLVectorVTInfo _, Predicate prd, + X86SchedWriteMoveLSWidths Sched, + string EVEX2VEXOvrd, bit NoRMPattern = 0, + SDPatternOperator SelectOprr = vselect> { + let Predicates = [prd] in + defm Z : avx512_load, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_load, EVEX_V256; + defm Z128 : avx512_load, EVEX_V128; + } +} + +multiclass avx512_store opc, string OpcodeStr, string BaseName, + X86VectorVTInfo _, PatFrag st_frag, PatFrag mstore, + X86SchedWriteMoveLS Sched, string EVEX2VEXOvrd, + bit NoMRPattern = 0> { + let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { + let isMoveReg = 1 in + def rr_REV : AVX512PI, EVEX, + FoldGenData, Sched<[Sched.RR]>, + EVEX2VEXOverride; + def rrk_REV : AVX512PI, EVEX, EVEX_K, + FoldGenData, + Sched<[Sched.RR]>; + def rrkz_REV : AVX512PI, EVEX, EVEX_KZ, + FoldGenData, + Sched<[Sched.RR]>; + } + + let hasSideEffects = 0, mayStore = 1 in + def mr : AVX512PI, EVEX, Sched<[Sched.MR]>, + EVEX2VEXOverride; + def mrk : AVX512PI, EVEX, EVEX_K, Sched<[Sched.MR]>, + NotMemoryFoldable; + + def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)), + (!cast(BaseName#_.ZSuffix#mrk) addr:$ptr, + _.KRCWM:$mask, _.RC:$src)>; + + // def : InstAlias(BaseName#_.ZSuffix#"rr_REV") + // _.RC:$dst, _.RC:$src), 0>; + // def : InstAlias(BaseName#_.ZSuffix#"rrk_REV") + // _.RC:$dst, _.KRCWM:$mask, _.RC:$src), 0>; + // def : InstAlias(BaseName#_.ZSuffix#"rrkz_REV") + // _.RC:$dst, _.KRCWM:$mask, _.RC:$src), 0>; +} + +multiclass avx512_store_vl< bits<8> opc, string OpcodeStr, + AVX512VLVectorVTInfo _, Predicate prd, + X86SchedWriteMoveLSWidths Sched, + string EVEX2VEXOvrd, bit NoMRPattern = 0> { + let Predicates = [prd] in + defm Z : avx512_store, EVEX_V512; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_store, EVEX_V256; + defm Z128 : avx512_store, EVEX_V128; + } +} + +multiclass avx512_alignedstore_vl opc, string OpcodeStr, + AVX512VLVectorVTInfo _, Predicate prd, + X86SchedWriteMoveLSWidths Sched, + string EVEX2VEXOvrd, bit NoMRPattern = 0> { + let Predicates = [prd] in + defm Z : avx512_store, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_store, EVEX_V256; + defm Z128 : avx512_store, EVEX_V128; + } +} + +defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info, + HasAVX512, SchedWriteFMoveLS, "VMOVAPS">, + avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info, + HasAVX512, SchedWriteFMoveLS, "VMOVAPS">, + PS, EVEX_CD8<32, CD8VF>; + +defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info, + HasAVX512, SchedWriteFMoveLS, "VMOVAPD">, + avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info, + HasAVX512, SchedWriteFMoveLS, "VMOVAPD">, + PD, VEX_W, EVEX_CD8<64, CD8VF>; + +defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512, + SchedWriteFMoveLS, "VMOVUPS", 0, null_frag>, + avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512, + SchedWriteFMoveLS, "VMOVUPS">, + PS, EVEX_CD8<32, CD8VF>; + +defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, + SchedWriteFMoveLS, "VMOVUPD", 0, null_frag>, + avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512, + SchedWriteFMoveLS, "VMOVUPD">, + PD, VEX_W, EVEX_CD8<64, CD8VF>; + +defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info, + HasAVX512, SchedWriteVecMoveLS, + "VMOVDQA", 1>, + avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info, + HasAVX512, SchedWriteVecMoveLS, + "VMOVDQA", 1>, + PD, EVEX_CD8<32, CD8VF>; + +defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info, + HasAVX512, SchedWriteVecMoveLS, + "VMOVDQA">, + avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info, + HasAVX512, SchedWriteVecMoveLS, + "VMOVDQA">, + PD, VEX_W, EVEX_CD8<64, CD8VF>; + +defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI, + SchedWriteVecMoveLS, "VMOVDQU", 1>, + avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info, HasBWI, + SchedWriteVecMoveLS, "VMOVDQU", 1>, + XD, EVEX_CD8<8, CD8VF>; + +defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI, + SchedWriteVecMoveLS, "VMOVDQU", 1>, + avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info, HasBWI, + SchedWriteVecMoveLS, "VMOVDQU", 1>, + XD, VEX_W, EVEX_CD8<16, CD8VF>; + +defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512, + SchedWriteVecMoveLS, "VMOVDQU", 1, null_frag>, + avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info, HasAVX512, + SchedWriteVecMoveLS, "VMOVDQU", 1>, + XS, EVEX_CD8<32, CD8VF>; + +defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512, + SchedWriteVecMoveLS, "VMOVDQU", 0, null_frag>, + avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info, HasAVX512, + SchedWriteVecMoveLS, "VMOVDQU">, + XS, VEX_W, EVEX_CD8<64, CD8VF>; + +/* +// Special instructions to help with spilling when we don't have VLX. We need +// to load or store from a ZMM register instead. These are converted in +// expandPostRAPseudos. +let isReMaterializable = 1, canFoldAsLoad = 1, + isPseudo = 1, mayLoad = 1, hasSideEffects = 0 in { +def VMOVAPSZ128rm_NOVLX : I<0, Pseudo, (outs VR128X:$dst), (ins f128mem:$src), + "", []>, Sched<[WriteFLoadX]>; +def VMOVAPSZ256rm_NOVLX : I<0, Pseudo, (outs VR256X:$dst), (ins f256mem:$src), + "", []>, Sched<[WriteFLoadY]>; +def VMOVUPSZ128rm_NOVLX : I<0, Pseudo, (outs VR128X:$dst), (ins f128mem:$src), + "", []>, Sched<[WriteFLoadX]>; +def VMOVUPSZ256rm_NOVLX : I<0, Pseudo, (outs VR256X:$dst), (ins f256mem:$src), + "", []>, Sched<[WriteFLoadY]>; +} + +let isPseudo = 1, mayStore = 1, hasSideEffects = 0 in { +def VMOVAPSZ128mr_NOVLX : I<0, Pseudo, (outs), (ins f128mem:$dst, VR128X:$src), + "", []>, Sched<[WriteFStoreX]>; +def VMOVAPSZ256mr_NOVLX : I<0, Pseudo, (outs), (ins f256mem:$dst, VR256X:$src), + "", []>, Sched<[WriteFStoreY]>; +def VMOVUPSZ128mr_NOVLX : I<0, Pseudo, (outs), (ins f128mem:$dst, VR128X:$src), + "", []>, Sched<[WriteFStoreX]>; +def VMOVUPSZ256mr_NOVLX : I<0, Pseudo, (outs), (ins f256mem:$dst, VR256X:$src), + "", []>, Sched<[WriteFStoreY]>; +} +*/ + +def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)), + (v8i64 VR512:$src))), + (VMOVDQA64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)), + VK8), VR512:$src)>; + +def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV), + (v16i32 VR512:$src))), + (VMOVDQA32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>; + +// These patterns exist to prevent the above patterns from introducing a second +// mask inversion when one already exists. +def : Pat<(v8i64 (vselect (xor VK8:$mask, (v8i1 immAllOnesV)), + (bc_v8i64 (v16i32 immAllZerosV)), + (v8i64 VR512:$src))), + (VMOVDQA64Zrrkz VK8:$mask, VR512:$src)>; +def : Pat<(v16i32 (vselect (xor VK16:$mask, (v16i1 immAllOnesV)), + (v16i32 immAllZerosV), + (v16i32 VR512:$src))), + (VMOVDQA32Zrrkz VK16WM:$mask, VR512:$src)>; + +multiclass mask_move_lowering { + def : Pat<(Narrow.VT (vselect (Narrow.KVT Narrow.KRCWM:$mask), + Narrow.RC:$src1, Narrow.RC:$src0)), + (EXTRACT_SUBREG + (Wide.VT + (!cast(InstrStr#"rrk") + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src0, Narrow.SubRegIdx)), + (COPY_TO_REGCLASS Narrow.KRCWM:$mask, Wide.KRCWM), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)))), + Narrow.SubRegIdx)>; + + def : Pat<(Narrow.VT (vselect (Narrow.KVT Narrow.KRCWM:$mask), + Narrow.RC:$src1, Narrow.ImmAllZerosV)), + (EXTRACT_SUBREG + (Wide.VT + (!cast(InstrStr#"rrkz") + (COPY_TO_REGCLASS Narrow.KRCWM:$mask, Wide.KRCWM), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)))), + Narrow.SubRegIdx)>; +} + +// Patterns for handling v8i1 selects of 256-bit vectors when VLX isn't +// available. Use a 512-bit operation and extract. +let Predicates = [HasAVX512, NoVLX] in { + defm : mask_move_lowering<"VMOVAPSZ", v4f32x_info, v16f32_info>; + defm : mask_move_lowering<"VMOVDQA32Z", v4i32x_info, v16i32_info>; + defm : mask_move_lowering<"VMOVAPSZ", v8f32x_info, v16f32_info>; + defm : mask_move_lowering<"VMOVDQA32Z", v8i32x_info, v16i32_info>; + + defm : mask_move_lowering<"VMOVAPDZ", v2f64x_info, v8f64_info>; + defm : mask_move_lowering<"VMOVDQA64Z", v2i64x_info, v8i64_info>; + defm : mask_move_lowering<"VMOVAPDZ", v4f64x_info, v8f64_info>; + defm : mask_move_lowering<"VMOVDQA64Z", v4i64x_info, v8i64_info>; +} + +let Predicates = [HasBWI, NoVLX] in { + defm : mask_move_lowering<"VMOVDQU8Z", v16i8x_info, v64i8_info>; + defm : mask_move_lowering<"VMOVDQU8Z", v32i8x_info, v64i8_info>; + + defm : mask_move_lowering<"VMOVDQU16Z", v8i16x_info, v32i16_info>; + defm : mask_move_lowering<"VMOVDQU16Z", v16i16x_info, v32i16_info>; +} + +let Predicates = [HasAVX512] in { + // 512-bit store. + def : Pat<(alignedstore (v16i32 VR512:$src), addr:$dst), + (VMOVDQA64Zmr addr:$dst, VR512:$src)>; + def : Pat<(alignedstore (v32i16 VR512:$src), addr:$dst), + (VMOVDQA64Zmr addr:$dst, VR512:$src)>; + def : Pat<(alignedstore (v64i8 VR512:$src), addr:$dst), + (VMOVDQA64Zmr addr:$dst, VR512:$src)>; + def : Pat<(store (v16i32 VR512:$src), addr:$dst), + (VMOVDQU64Zmr addr:$dst, VR512:$src)>; + def : Pat<(store (v32i16 VR512:$src), addr:$dst), + (VMOVDQU64Zmr addr:$dst, VR512:$src)>; + def : Pat<(store (v64i8 VR512:$src), addr:$dst), + (VMOVDQU64Zmr addr:$dst, VR512:$src)>; +} + +let Predicates = [HasVLX] in { + // 128-bit store. + def : Pat<(alignedstore (v4i32 VR128X:$src), addr:$dst), + (VMOVDQA64Z128mr addr:$dst, VR128X:$src)>; + def : Pat<(alignedstore (v8i16 VR128X:$src), addr:$dst), + (VMOVDQA64Z128mr addr:$dst, VR128X:$src)>; + def : Pat<(alignedstore (v16i8 VR128X:$src), addr:$dst), + (VMOVDQA64Z128mr addr:$dst, VR128X:$src)>; + def : Pat<(store (v4i32 VR128X:$src), addr:$dst), + (VMOVDQU64Z128mr addr:$dst, VR128X:$src)>; + def : Pat<(store (v8i16 VR128X:$src), addr:$dst), + (VMOVDQU64Z128mr addr:$dst, VR128X:$src)>; + def : Pat<(store (v16i8 VR128X:$src), addr:$dst), + (VMOVDQU64Z128mr addr:$dst, VR128X:$src)>; + + // 256-bit store. + def : Pat<(alignedstore (v8i32 VR256X:$src), addr:$dst), + (VMOVDQA64Z256mr addr:$dst, VR256X:$src)>; + def : Pat<(alignedstore (v16i16 VR256X:$src), addr:$dst), + (VMOVDQA64Z256mr addr:$dst, VR256X:$src)>; + def : Pat<(alignedstore (v32i8 VR256X:$src), addr:$dst), + (VMOVDQA64Z256mr addr:$dst, VR256X:$src)>; + def : Pat<(store (v8i32 VR256X:$src), addr:$dst), + (VMOVDQU64Z256mr addr:$dst, VR256X:$src)>; + def : Pat<(store (v16i16 VR256X:$src), addr:$dst), + (VMOVDQU64Z256mr addr:$dst, VR256X:$src)>; + def : Pat<(store (v32i8 VR256X:$src), addr:$dst), + (VMOVDQU64Z256mr addr:$dst, VR256X:$src)>; +} + +multiclass masked_move_for_extract { + def : Pat<(Cast.VT (vselect Cast.KRCWM:$mask, + (bitconvert + (To.VT (extract_subvector + (From.VT From.RC:$src), (iPTR 0)))), + To.RC:$src0)), + (Cast.VT (!cast(InstrStr#"rrk") + Cast.RC:$src0, Cast.KRCWM:$mask, + (To.VT (EXTRACT_SUBREG From.RC:$src, To.SubRegIdx))))>; + + def : Pat<(Cast.VT (vselect Cast.KRCWM:$mask, + (bitconvert + (To.VT (extract_subvector + (From.VT From.RC:$src), (iPTR 0)))), + Cast.ImmAllZerosV)), + (Cast.VT (!cast(InstrStr#"rrkz") + Cast.KRCWM:$mask, + (To.VT (EXTRACT_SUBREG From.RC:$src, To.SubRegIdx))))>; +} + + +let Predicates = [HasVLX] in { +// A masked extract from the first 128-bits of a 256-bit vector can be +// implemented with masked move. +defm : masked_move_for_extract<"VMOVDQA64Z128", v4i64x_info, v2i64x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z128", v8i32x_info, v4i32x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z128", v16i16x_info, v8i16x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z128", v32i8x_info, v16i8x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v4i64x_info, v2i64x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v8i32x_info, v4i32x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v16i16x_info, v8i16x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v32i8x_info, v16i8x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVAPDZ128", v4f64x_info, v2f64x_info, v2f64x_info>; +defm : masked_move_for_extract<"VMOVAPDZ128", v8f32x_info, v4f32x_info, v2f64x_info>; +defm : masked_move_for_extract<"VMOVAPSZ128", v4f64x_info, v2f64x_info, v4f32x_info>; +defm : masked_move_for_extract<"VMOVAPSZ128", v8f32x_info, v4f32x_info, v4f32x_info>; + +// A masked extract from the first 128-bits of a 512-bit vector can be +// implemented with masked move. +defm : masked_move_for_extract<"VMOVDQA64Z128", v8i64_info, v2i64x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z128", v16i32_info, v4i32x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z128", v32i16_info, v8i16x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z128", v64i8_info, v16i8x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v8i64_info, v2i64x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v16i32_info, v4i32x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v32i16_info, v8i16x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v64i8_info, v16i8x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVAPDZ128", v8f64_info, v2f64x_info, v2f64x_info>; +defm : masked_move_for_extract<"VMOVAPDZ128", v16f32_info, v4f32x_info, v2f64x_info>; +defm : masked_move_for_extract<"VMOVAPSZ128", v8f64_info, v2f64x_info, v4f32x_info>; +defm : masked_move_for_extract<"VMOVAPSZ128", v16f32_info, v4f32x_info, v4f32x_info>; + +// A masked extract from the first 256-bits of a 512-bit vector can be +// implemented with masked move. +defm : masked_move_for_extract<"VMOVDQA64Z256", v8i64_info, v4i64x_info, v4i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z256", v16i32_info, v8i32x_info, v4i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z256", v32i16_info, v16i16x_info, v4i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z256", v64i8_info, v32i8x_info, v4i64x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z256", v8i64_info, v4i64x_info, v8i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z256", v16i32_info, v8i32x_info, v8i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z256", v32i16_info, v16i16x_info, v8i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z256", v64i8_info, v32i8x_info, v8i32x_info>; +defm : masked_move_for_extract<"VMOVAPDZ256", v8f64_info, v4f64x_info, v4f64x_info>; +defm : masked_move_for_extract<"VMOVAPDZ256", v16f32_info, v8f32x_info, v4f64x_info>; +defm : masked_move_for_extract<"VMOVAPSZ256", v8f64_info, v4f64x_info, v8f32x_info>; +defm : masked_move_for_extract<"VMOVAPSZ256", v16f32_info, v8f32x_info, v8f32x_info>; +} + +// Move Int Doubleword to Packed Double Int +// +let ExeDomain = SSEPackedInt in { +def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(set VR128X:$dst, + (v4i32 (scalar_to_vector GR32:$src)))]>, + EVEX, Sched<[WriteVecMoveFromGpr]>; +def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(set VR128X:$dst, + (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>, + EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecLoad]>; +def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set VR128X:$dst, + (v2i64 (scalar_to_vector GR64:$src)))]>, + EVEX, VEX_W, Sched<[WriteVecMoveFromGpr]>; +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in +def VMOV64toPQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), + (ins i64mem:$src), + "vmovq\t{$src, $dst|$dst, $src}", []>, + EVEX, VEX_W, EVEX_CD8<64, CD8VT1>, Sched<[WriteVecLoad]>; +let isCodeGenOnly = 1 in { +def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64X:$dst), (ins GR64:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set FR64X:$dst, (bitconvert GR64:$src))]>, + EVEX, VEX_W, Sched<[WriteVecMoveFromGpr]>; +def VMOV64toSDZrm : AVX512XSI<0x7E, MRMSrcMem, (outs FR64X:$dst), (ins i64mem:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set FR64X:$dst, (bitconvert (loadi64 addr:$src)))]>, + EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteVecLoad]>; +def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64X:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (bitconvert FR64X:$src))]>, + EVEX, VEX_W, Sched<[WriteVecMoveFromGpr]>; +def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64X:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(store (i64 (bitconvert FR64X:$src)), addr:$dst)]>, + EVEX, VEX_W, Sched<[WriteVecStore]>, + EVEX_CD8<64, CD8VT1>; +} +} // ExeDomain = SSEPackedInt + +// Move Int Doubleword to Single Scalar +// +let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in { +def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(set FR32X:$dst, (bitconvert GR32:$src))]>, + EVEX, Sched<[WriteVecMoveFromGpr]>; + +def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))]>, + EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecLoad]>; +} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1 + +// Move doubleword from xmm register to r/m32 +// +let ExeDomain = SSEPackedInt in { +def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (extractelt (v4i32 VR128X:$src), + (iPTR 0)))]>, + EVEX, Sched<[WriteVecMoveToGpr]>; +def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs), + (ins i32mem:$dst, VR128X:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(store (i32 (extractelt (v4i32 VR128X:$src), + (iPTR 0))), addr:$dst)]>, + EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecStore]>; +} // ExeDomain = SSEPackedInt + +// Move quadword from xmm1 register to r/m64 +// +let ExeDomain = SSEPackedInt in { +def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (extractelt (v2i64 VR128X:$src), + (iPTR 0)))]>, + PD, EVEX, VEX_W, Sched<[WriteVecMoveToGpr]>, + Requires<[HasAVX512]>; + +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in +def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128X:$src), + "vmovq\t{$src, $dst|$dst, $src}", []>, PD, + EVEX, VEX_W, Sched<[WriteVecStore]>, + Requires<[HasAVX512, In64BitMode]>; + +def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs), + (ins i64mem:$dst, VR128X:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)), + addr:$dst)]>, + EVEX, PD, VEX_W, EVEX_CD8<64, CD8VT1>, + Sched<[WriteVecStore]>, Requires<[HasAVX512]>; + +let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in +def VMOVPQI2QIZrr : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst), + (ins VR128X:$src), + "vmovq\t{$src, $dst|$dst, $src}", []>, + EVEX, VEX_W, Sched<[SchedWriteVecLogic.XMM]>; +} // ExeDomain = SSEPackedInt + +// def : InstAlias<"vmovq.s\t{$src, $dst|$dst, $src}", +// (VMOVPQI2QIZrr VR128X:$dst, VR128X:$src), 0>; + +// Move Scalar Single to Double Int +// +let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in { +def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), + (ins FR32X:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (bitconvert FR32X:$src))]>, + EVEX, Sched<[WriteVecMoveToGpr]>; +def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs), + (ins i32mem:$dst, FR32X:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(store (i32 (bitconvert FR32X:$src)), addr:$dst)]>, + EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecStore]>; +} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1 + +// Move Quadword Int to Packed Quadword Int +// +let ExeDomain = SSEPackedInt in { +def VMOVQI2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst), + (ins i64mem:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set VR128X:$dst, + (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, + EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteVecLoad]>; +} // ExeDomain = SSEPackedInt + +// Allow "vmovd" but print "vmovq". +// def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}", +// (VMOV64toPQIZrr VR128X:$dst, GR64:$src), 0>; +// def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}", +// (VMOVPQIto64Zrr GR64:$dst, VR128X:$src), 0>; + +//===----------------------------------------------------------------------===// +// AVX-512 MOVSS, MOVSD +//===----------------------------------------------------------------------===// + +multiclass avx512_move_scalar { + let Predicates = [HasAVX512, OptForSize] in + def rr : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst), + (ins _.RC:$src1, _.RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2)))], + _.ExeDomain>, EVEX_4V, Sched<[SchedWriteFShuffle.XMM]>; + def rrkz : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst), + (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst {${mask}} {z}|", + "$dst {${mask}} {z}, $src1, $src2}"), + [(set _.RC:$dst, (_.VT (X86selects _.KRCWM:$mask, + (_.VT (OpNode _.RC:$src1, _.RC:$src2)), + _.ImmAllZerosV)))], + _.ExeDomain>, EVEX_4V, EVEX_KZ, Sched<[SchedWriteFShuffle.XMM]>; + let Constraints = "$src0 = $dst" in + def rrk : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst), + (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1, _.RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst {${mask}}|", + "$dst {${mask}}, $src1, $src2}"), + [(set _.RC:$dst, (_.VT (X86selects _.KRCWM:$mask, + (_.VT (OpNode _.RC:$src1, _.RC:$src2)), + (_.VT _.RC:$src0))))], + _.ExeDomain>, EVEX_4V, EVEX_K, Sched<[SchedWriteFShuffle.XMM]>; + let canFoldAsLoad = 1, isReMaterializable = 1 in + def rm : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), (ins _.ScalarMemOp:$src), + !strconcat(asm, "\t{$src, $dst|$dst, $src}"), + [(set _.FRC:$dst, (_.ScalarLdFrag addr:$src))], + _.ExeDomain>, EVEX, Sched<[WriteFLoad]>; + let mayLoad = 1, hasSideEffects = 0 in { + let Constraints = "$src0 = $dst" in + def rmk : AVX512PI<0x10, MRMSrcMem, (outs _.RC:$dst), + (ins _.RC:$src0, _.KRCWM:$mask, _.ScalarMemOp:$src), + !strconcat(asm, "\t{$src, $dst {${mask}}|", + "$dst {${mask}}, $src}"), + [], _.ExeDomain>, EVEX, EVEX_K, Sched<[WriteFLoad]>; + def rmkz : AVX512PI<0x10, MRMSrcMem, (outs _.RC:$dst), + (ins _.KRCWM:$mask, _.ScalarMemOp:$src), + !strconcat(asm, "\t{$src, $dst {${mask}} {z}|", + "$dst {${mask}} {z}, $src}"), + [], _.ExeDomain>, EVEX, EVEX_KZ, Sched<[WriteFLoad]>; + } + def mr: AVX512PI<0x11, MRMDestMem, (outs), (ins _.ScalarMemOp:$dst, _.FRC:$src), + !strconcat(asm, "\t{$src, $dst|$dst, $src}"), + [(store _.FRC:$src, addr:$dst)], _.ExeDomain>, + EVEX, Sched<[WriteFStore]>; + let mayStore = 1, hasSideEffects = 0 in + def mrk: AVX512PI<0x11, MRMDestMem, (outs), + (ins _.ScalarMemOp:$dst, VK1WM:$mask, _.FRC:$src), + !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"), + [], _.ExeDomain>, EVEX, EVEX_K, Sched<[WriteFStore]>, + NotMemoryFoldable; +} + +defm VMOVSSZ : avx512_move_scalar<"vmovss", X86Movss, f32x_info>, + VEX_LIG, XS, EVEX_CD8<32, CD8VT1>; + +defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, f64x_info>, + VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>; + + +multiclass avx512_move_scalar_lowering { + +def : Pat<(_.VT (OpNode _.RC:$src0, + (_.VT (scalar_to_vector + (_.EltVT (X86selects VK1WM:$mask, + (_.EltVT _.FRC:$src1), + (_.EltVT _.FRC:$src2))))))), + (!cast(InstrStr#rrk) + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, _.RC)), + VK1WM:$mask, + (_.VT _.RC:$src0), + (_.VT (COPY_TO_REGCLASS _.FRC:$src1, _.RC)))>; + +def : Pat<(_.VT (OpNode _.RC:$src0, + (_.VT (scalar_to_vector + (_.EltVT (X86selects VK1WM:$mask, + (_.EltVT _.FRC:$src1), + (_.EltVT ZeroFP))))))), + (!cast(InstrStr#rrkz) + VK1WM:$mask, + (_.VT _.RC:$src0), + (_.VT (COPY_TO_REGCLASS _.FRC:$src1, _.RC)))>; +} + +multiclass avx512_store_scalar_lowering { + +def : Pat<(masked_store addr:$dst, Mask, + (_.info512.VT (insert_subvector undef, + (_.info128.VT _.info128.RC:$src), + (iPTR 0)))), + (!cast(InstrStr#mrk) addr:$dst, + (COPY_TO_REGCLASS MaskRC:$mask, VK1WM), + (COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>; + +} + +multiclass avx512_store_scalar_lowering_subreg { + +def : Pat<(masked_store addr:$dst, Mask, + (_.info512.VT (insert_subvector undef, + (_.info128.VT _.info128.RC:$src), + (iPTR 0)))), + (!cast(InstrStr#mrk) addr:$dst, + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + (COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>; + +} + +// This matches the more recent codegen from clang that avoids emitting a 512 +// bit masked store directly. Codegen will widen 128-bit masked store to 512 +// bits on AVX512F only targets. +multiclass avx512_store_scalar_lowering_subreg2 { + +// AVX512F pattern. +def : Pat<(masked_store addr:$dst, Mask512, + (_.info512.VT (insert_subvector undef, + (_.info128.VT _.info128.RC:$src), + (iPTR 0)))), + (!cast(InstrStr#mrk) addr:$dst, + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + (COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>; + +// AVX512VL pattern. +def : Pat<(masked_store addr:$dst, Mask128, (_.info128.VT _.info128.RC:$src)), + (!cast(InstrStr#mrk) addr:$dst, + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + (COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>; +} + +multiclass avx512_load_scalar_lowering { + +def : Pat<(_.info128.VT (extract_subvector + (_.info512.VT (masked_load addr:$srcAddr, Mask, + (_.info512.VT (bitconvert + (v16i32 immAllZerosV))))), + (iPTR 0))), + (!cast(InstrStr#rmkz) + (COPY_TO_REGCLASS MaskRC:$mask, VK1WM), + addr:$srcAddr)>; + +def : Pat<(_.info128.VT (extract_subvector + (_.info512.VT (masked_load addr:$srcAddr, Mask, + (_.info512.VT (insert_subvector undef, + (_.info128.VT (X86vzmovl _.info128.RC:$src)), + (iPTR 0))))), + (iPTR 0))), + (!cast(InstrStr#rmk) _.info128.RC:$src, + (COPY_TO_REGCLASS MaskRC:$mask, VK1WM), + addr:$srcAddr)>; + +} + +multiclass avx512_load_scalar_lowering_subreg { + +def : Pat<(_.info128.VT (extract_subvector + (_.info512.VT (masked_load addr:$srcAddr, Mask, + (_.info512.VT (bitconvert + (v16i32 immAllZerosV))))), + (iPTR 0))), + (!cast(InstrStr#rmkz) + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + addr:$srcAddr)>; + +def : Pat<(_.info128.VT (extract_subvector + (_.info512.VT (masked_load addr:$srcAddr, Mask, + (_.info512.VT (insert_subvector undef, + (_.info128.VT (X86vzmovl _.info128.RC:$src)), + (iPTR 0))))), + (iPTR 0))), + (!cast(InstrStr#rmk) _.info128.RC:$src, + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + addr:$srcAddr)>; + +} + +// This matches the more recent codegen from clang that avoids emitting a 512 +// bit masked load directly. Codegen will widen 128-bit masked load to 512 +// bits on AVX512F only targets. +multiclass avx512_load_scalar_lowering_subreg2 { +// AVX512F patterns. +def : Pat<(_.info128.VT (extract_subvector + (_.info512.VT (masked_load addr:$srcAddr, Mask512, + (_.info512.VT (bitconvert + (v16i32 immAllZerosV))))), + (iPTR 0))), + (!cast(InstrStr#rmkz) + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + addr:$srcAddr)>; + +def : Pat<(_.info128.VT (extract_subvector + (_.info512.VT (masked_load addr:$srcAddr, Mask512, + (_.info512.VT (insert_subvector undef, + (_.info128.VT (X86vzmovl _.info128.RC:$src)), + (iPTR 0))))), + (iPTR 0))), + (!cast(InstrStr#rmk) _.info128.RC:$src, + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + addr:$srcAddr)>; + +// AVX512Vl patterns. +def : Pat<(_.info128.VT (masked_load addr:$srcAddr, Mask128, + (_.info128.VT (bitconvert (v4i32 immAllZerosV))))), + (!cast(InstrStr#rmkz) + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + addr:$srcAddr)>; + +def : Pat<(_.info128.VT (masked_load addr:$srcAddr, Mask128, + (_.info128.VT (X86vzmovl _.info128.RC:$src)))), + (!cast(InstrStr#rmk) _.info128.RC:$src, + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + addr:$srcAddr)>; +} + +defm : avx512_move_scalar_lowering<"VMOVSSZ", X86Movss, fp32imm0, v4f32x_info>; +defm : avx512_move_scalar_lowering<"VMOVSDZ", X86Movsd, fp64imm0, v2f64x_info>; + +defm : avx512_store_scalar_lowering<"VMOVSSZ", avx512vl_f32_info, + (v16i1 (bitconvert (i16 (trunc (and GR32:$mask, (i32 1)))))), GR32>; +defm : avx512_store_scalar_lowering_subreg<"VMOVSSZ", avx512vl_f32_info, + (v16i1 (bitconvert (i16 (and GR16:$mask, (i16 1))))), GR16, sub_16bit>; +defm : avx512_store_scalar_lowering_subreg<"VMOVSDZ", avx512vl_f64_info, + (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), GR8, sub_8bit>; + +defm : avx512_store_scalar_lowering_subreg2<"VMOVSSZ", avx512vl_f32_info, + (v16i1 (insert_subvector + (v16i1 immAllZerosV), + (v4i1 (extract_subvector + (v8i1 (bitconvert (and GR8:$mask, (i8 1)))), + (iPTR 0))), + (iPTR 0))), + (v4i1 (extract_subvector + (v8i1 (bitconvert (and GR8:$mask, (i8 1)))), + (iPTR 0))), GR8, sub_8bit>; +defm : avx512_store_scalar_lowering_subreg2<"VMOVSDZ", avx512vl_f64_info, + (v8i1 + (extract_subvector + (v16i1 + (insert_subvector + (v16i1 immAllZerosV), + (v2i1 (extract_subvector + (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), + (iPTR 0))), + (iPTR 0))), + (iPTR 0))), + (v2i1 (extract_subvector + (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), + (iPTR 0))), GR8, sub_8bit>; + +defm : avx512_load_scalar_lowering<"VMOVSSZ", avx512vl_f32_info, + (v16i1 (bitconvert (i16 (trunc (and GR32:$mask, (i32 1)))))), GR32>; +defm : avx512_load_scalar_lowering_subreg<"VMOVSSZ", avx512vl_f32_info, + (v16i1 (bitconvert (i16 (and GR16:$mask, (i16 1))))), GR16, sub_16bit>; +defm : avx512_load_scalar_lowering_subreg<"VMOVSDZ", avx512vl_f64_info, + (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), GR8, sub_8bit>; + +defm : avx512_load_scalar_lowering_subreg2<"VMOVSSZ", avx512vl_f32_info, + (v16i1 (insert_subvector + (v16i1 immAllZerosV), + (v4i1 (extract_subvector + (v8i1 (bitconvert (and GR8:$mask, (i8 1)))), + (iPTR 0))), + (iPTR 0))), + (v4i1 (extract_subvector + (v8i1 (bitconvert (and GR8:$mask, (i8 1)))), + (iPTR 0))), GR8, sub_8bit>; +defm : avx512_load_scalar_lowering_subreg2<"VMOVSDZ", avx512vl_f64_info, + (v8i1 + (extract_subvector + (v16i1 + (insert_subvector + (v16i1 immAllZerosV), + (v2i1 (extract_subvector + (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), + (iPTR 0))), + (iPTR 0))), + (iPTR 0))), + (v2i1 (extract_subvector + (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), + (iPTR 0))), GR8, sub_8bit>; + +def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))), + (COPY_TO_REGCLASS (v4f32 (VMOVSSZrrk + (v4f32 (COPY_TO_REGCLASS FR32X:$src2, VR128X)), + VK1WM:$mask, (v4f32 (IMPLICIT_DEF)), + (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)))), FR32X)>; + +def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), fp32imm0)), + (COPY_TO_REGCLASS (v4f32 (VMOVSSZrrkz VK1WM:$mask, (v4f32 (IMPLICIT_DEF)), + (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)))), FR32X)>; + +def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))), + (COPY_TO_REGCLASS (v2f64 (VMOVSDZrrk + (v2f64 (COPY_TO_REGCLASS FR64X:$src2, VR128X)), + VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), + (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)))), FR64X)>; + +def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), fpimm0)), + (COPY_TO_REGCLASS (v2f64 (VMOVSDZrrkz VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), + (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)))), FR64X)>; + +let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { + def VMOVSSZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), + (ins VR128X:$src1, VR128X:$src2), + "vmovss\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, XS, EVEX_4V, VEX_LIG, + FoldGenData<"VMOVSSZrr">, + Sched<[SchedWriteFShuffle.XMM]>; + + let Constraints = "$src0 = $dst" in + def VMOVSSZrrk_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), + (ins f32x_info.RC:$src0, f32x_info.KRCWM:$mask, + VR128X:$src1, VR128X:$src2), + "vmovss\t{$src2, $src1, $dst {${mask}}|"# + "$dst {${mask}}, $src1, $src2}", + []>, EVEX_K, XS, EVEX_4V, VEX_LIG, + FoldGenData<"VMOVSSZrrk">, + Sched<[SchedWriteFShuffle.XMM]>; + + def VMOVSSZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), + (ins f32x_info.KRCWM:$mask, VR128X:$src1, VR128X:$src2), + "vmovss\t{$src2, $src1, $dst {${mask}} {z}|"# + "$dst {${mask}} {z}, $src1, $src2}", + []>, EVEX_KZ, XS, EVEX_4V, VEX_LIG, + FoldGenData<"VMOVSSZrrkz">, + Sched<[SchedWriteFShuffle.XMM]>; + + def VMOVSDZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), + (ins VR128X:$src1, VR128X:$src2), + "vmovsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, XD, EVEX_4V, VEX_LIG, VEX_W, + FoldGenData<"VMOVSDZrr">, + Sched<[SchedWriteFShuffle.XMM]>; + + let Constraints = "$src0 = $dst" in + def VMOVSDZrrk_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), + (ins f64x_info.RC:$src0, f64x_info.KRCWM:$mask, + VR128X:$src1, VR128X:$src2), + "vmovsd\t{$src2, $src1, $dst {${mask}}|"# + "$dst {${mask}}, $src1, $src2}", + []>, EVEX_K, XD, EVEX_4V, VEX_LIG, + VEX_W, FoldGenData<"VMOVSDZrrk">, + Sched<[SchedWriteFShuffle.XMM]>; + + def VMOVSDZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), + (ins f64x_info.KRCWM:$mask, VR128X:$src1, + VR128X:$src2), + "vmovsd\t{$src2, $src1, $dst {${mask}} {z}|"# + "$dst {${mask}} {z}, $src1, $src2}", + []>, EVEX_KZ, XD, EVEX_4V, VEX_LIG, + VEX_W, FoldGenData<"VMOVSDZrrkz">, + Sched<[SchedWriteFShuffle.XMM]>; +} + +// def : InstAlias<"vmovss.s\t{$src2, $src1, $dst|$dst, $src1, $src2}", +// (VMOVSSZrr_REV VR128X:$dst, VR128X:$src1, VR128X:$src2), 0>; +// def : InstAlias<"vmovss.s\t{$src2, $src1, $dst {${mask}}|"# +// "$dst {${mask}}, $src1, $src2}", +// (VMOVSSZrrk_REV VR128X:$dst, VK1WM:$mask, +// VR128X:$src1, VR128X:$src2), 0>; +// def : InstAlias<"vmovss.s\t{$src2, $src1, $dst {${mask}} {z}|"# +// "$dst {${mask}} {z}, $src1, $src2}", +// (VMOVSSZrrkz_REV VR128X:$dst, VK1WM:$mask, +// VR128X:$src1, VR128X:$src2), 0>; +// def : InstAlias<"vmovsd.s\t{$src2, $src1, $dst|$dst, $src1, $src2}", +// (VMOVSDZrr_REV VR128X:$dst, VR128X:$src1, VR128X:$src2), 0>; +// def : InstAlias<"vmovsd.s\t{$src2, $src1, $dst {${mask}}|"# +// "$dst {${mask}}, $src1, $src2}", +// (VMOVSDZrrk_REV VR128X:$dst, VK1WM:$mask, +// VR128X:$src1, VR128X:$src2), 0>; +// def : InstAlias<"vmovsd.s\t{$src2, $src1, $dst {${mask}} {z}|"# +// "$dst {${mask}} {z}, $src1, $src2}", +// (VMOVSDZrrkz_REV VR128X:$dst, VK1WM:$mask, +// VR128X:$src1, VR128X:$src2), 0>; + +let Predicates = [HasAVX512, OptForSize] in { + def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))), + (VMOVSSZrr (v4f32 (AVX512_128_SET0)), VR128X:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))), + (VMOVSSZrr (v4i32 (AVX512_128_SET0)), VR128X:$src)>; + + // Move low f32 and clear high bits. + def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))), + (SUBREG_TO_REG (i32 0), + (v4f32 (VMOVSSZrr (v4f32 (AVX512_128_SET0)), + (v4f32 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)))), sub_xmm)>; + def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))), + (SUBREG_TO_REG (i32 0), + (v4i32 (VMOVSSZrr (v4i32 (AVX512_128_SET0)), + (v4i32 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)))), sub_xmm)>; + + def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))), + (SUBREG_TO_REG (i32 0), + (v2f64 (VMOVSDZrr (v2f64 (AVX512_128_SET0)), + (v2f64 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)))), sub_xmm)>; + def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))), + (SUBREG_TO_REG (i32 0), + (v2i64 (VMOVSDZrr (v2i64 (AVX512_128_SET0)), + (v2i64 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)))), sub_xmm)>; + + def : Pat<(v16f32 (X86vzmovl (v16f32 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v4f32 (VMOVSSZrr (v4f32 (AVX512_128_SET0)), + (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm)))), sub_xmm)>; + def : Pat<(v16i32 (X86vzmovl (v16i32 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v4i32 (VMOVSSZrr (v4i32 (AVX512_128_SET0)), + (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm)))), sub_xmm)>; + + def : Pat<(v8f64 (X86vzmovl (v8f64 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v2f64 (VMOVSDZrr (v2f64 (AVX512_128_SET0)), + (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm)))), sub_xmm)>; + + def : Pat<(v8i64 (X86vzmovl (v8i64 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v2i64 (VMOVSDZrr (v2i64 (AVX512_128_SET0)), + (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm)))), sub_xmm)>; + +} + +// Use 128-bit blends for OptForSpeed since BLENDs have better throughput than +// VMOVSS/SD. Unfortunately, loses the ability to use XMM16-31. +let Predicates = [HasAVX512, OptForSpeed] in { + def : Pat<(v16f32 (X86vzmovl (v16f32 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v4f32 (VBLENDPSrri (v4f32 (V_SET0)), + (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm)), + (i8 1))), sub_xmm)>; + def : Pat<(v16i32 (X86vzmovl (v16i32 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v4i32 (VPBLENDWrri (v4i32 (V_SET0)), + (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm)), + (i8 3))), sub_xmm)>; + + def : Pat<(v8f64 (X86vzmovl (v8f64 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v2f64 (VBLENDPDrri (v2f64 (V_SET0)), + (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm)), + (i8 1))), sub_xmm)>; + def : Pat<(v8i64 (X86vzmovl (v8i64 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v2i64 (VPBLENDWrri (v2i64 (V_SET0)), + (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm)), + (i8 0xf))), sub_xmm)>; +} + +let Predicates = [HasAVX512] in { + + // MOVSSrm zeros the high parts of the register; represent this + // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 + def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))), + (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>; + def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), + (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>; + def : Pat<(v4f32 (X86vzload addr:$src)), + (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>; + + // MOVSDrm zeros the high parts of the register; represent this + // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 + def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))), + (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; + def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), + (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; + def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), + (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; + def : Pat<(v2f64 (X86vzload addr:$src)), + (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; + + // Represent the same patterns above but in the form they appear for + // 256-bit types + def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; + def : Pat<(v8f32 (X86vzmovl (insert_subvector undef, + (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; + def : Pat<(v8f32 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; + def : Pat<(v4f64 (X86vzmovl (insert_subvector undef, + (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; + def : Pat<(v4f64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; + + // Represent the same patterns above but in the form they appear for + // 512-bit types + def : Pat<(v16i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; + def : Pat<(v16f32 (X86vzmovl (insert_subvector undef, + (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; + def : Pat<(v16f32 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; + def : Pat<(v8f64 (X86vzmovl (insert_subvector undef, + (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; + def : Pat<(v8f64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; + + def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, + (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; + + // Extract and store. + def : Pat<(store (f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))), + addr:$dst), + (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>; +} + +let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecLogic.XMM] in { +def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst), + (ins VR128X:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set VR128X:$dst, (v2i64 (X86vzmovl + (v2i64 VR128X:$src))))]>, + EVEX, VEX_W; +} + +let Predicates = [HasAVX512] in { + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))), + (VMOVDI2PDIZrr GR32:$src)>; + + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))), + (VMOV64toPQIZrr GR64:$src)>; + + def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, + (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOV64toPQIZrr GR64:$src)), sub_xmm)>; + + def : Pat<(v8i64 (X86vzmovl (insert_subvector undef, + (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOV64toPQIZrr GR64:$src)), sub_xmm)>; + + // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part. + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (zextloadi64i32 addr:$src))))), + (VMOVDI2PDIZrm addr:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))), + (VMOVDI2PDIZrm addr:$src)>; + def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))), + (VMOVDI2PDIZrm addr:$src)>; + def : Pat<(v4i32 (X86vzload addr:$src)), + (VMOVDI2PDIZrm addr:$src)>; + def : Pat<(v8i32 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; + def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))), + (VMOVQI2PQIZrm addr:$src)>; + def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))), + (VMOVZPQILo2PQIZrr VR128X:$src)>; + def : Pat<(v2i64 (X86vzload addr:$src)), + (VMOVQI2PQIZrm addr:$src)>; + def : Pat<(v4i64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; + + // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext. + def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrr GR32:$src)), sub_xmm)>; + def : Pat<(v16i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrr GR32:$src)), sub_xmm)>; + + // Use regular 128-bit instructions to match 512-bit scalar_to_vec+zext. + def : Pat<(v16i32 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; + def : Pat<(v8i64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 - Non-temporals +//===----------------------------------------------------------------------===// + +def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst), + (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}", + [], SSEPackedInt>, Sched<[SchedWriteVecMoveLS.ZMM.RM]>, + EVEX, T8PD, EVEX_V512, EVEX_CD8<64, CD8VF>; + +let Predicates = [HasVLX] in { + def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst), + (ins i256mem:$src), + "vmovntdqa\t{$src, $dst|$dst, $src}", + [], SSEPackedInt>, Sched<[SchedWriteVecMoveLS.YMM.RM]>, + EVEX, T8PD, EVEX_V256, EVEX_CD8<64, CD8VF>; + + def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst), + (ins i128mem:$src), + "vmovntdqa\t{$src, $dst|$dst, $src}", + [], SSEPackedInt>, Sched<[SchedWriteVecMoveLS.XMM.RM]>, + EVEX, T8PD, EVEX_V128, EVEX_CD8<64, CD8VF>; +} + +multiclass avx512_movnt opc, string OpcodeStr, X86VectorVTInfo _, + X86SchedWriteMoveLS Sched, + PatFrag st_frag = alignednontemporalstore> { + let SchedRW = [Sched.MR], AddedComplexity = 400 in + def mr : AVX512PI, EVEX, EVEX_CD8<_.EltSize, CD8VF>; +} + +multiclass avx512_movnt_vl opc, string OpcodeStr, + AVX512VLVectorVTInfo VTInfo, + X86SchedWriteMoveLSWidths Sched> { + let Predicates = [HasAVX512] in + defm Z : avx512_movnt, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in { + defm Z256 : avx512_movnt, EVEX_V256; + defm Z128 : avx512_movnt, EVEX_V128; + } +} + +defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", avx512vl_i64_info, + SchedWriteVecMoveLSNT>, PD; +defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", avx512vl_f64_info, + SchedWriteFMoveLSNT>, PD, VEX_W; +defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", avx512vl_f32_info, + SchedWriteFMoveLSNT>, PS; + +let Predicates = [HasAVX512], AddedComplexity = 400 in { + def : Pat<(alignednontemporalstore (v16i32 VR512:$src), addr:$dst), + (VMOVNTDQZmr addr:$dst, VR512:$src)>; + def : Pat<(alignednontemporalstore (v32i16 VR512:$src), addr:$dst), + (VMOVNTDQZmr addr:$dst, VR512:$src)>; + def : Pat<(alignednontemporalstore (v64i8 VR512:$src), addr:$dst), + (VMOVNTDQZmr addr:$dst, VR512:$src)>; + + def : Pat<(v8f64 (alignednontemporalload addr:$src)), + (VMOVNTDQAZrm addr:$src)>; + def : Pat<(v16f32 (alignednontemporalload addr:$src)), + (VMOVNTDQAZrm addr:$src)>; + def : Pat<(v8i64 (alignednontemporalload addr:$src)), + (VMOVNTDQAZrm addr:$src)>; +} + +let Predicates = [HasVLX], AddedComplexity = 400 in { + def : Pat<(alignednontemporalstore (v8i32 VR256X:$src), addr:$dst), + (VMOVNTDQZ256mr addr:$dst, VR256X:$src)>; + def : Pat<(alignednontemporalstore (v16i16 VR256X:$src), addr:$dst), + (VMOVNTDQZ256mr addr:$dst, VR256X:$src)>; + def : Pat<(alignednontemporalstore (v32i8 VR256X:$src), addr:$dst), + (VMOVNTDQZ256mr addr:$dst, VR256X:$src)>; + + def : Pat<(v4f64 (alignednontemporalload addr:$src)), + (VMOVNTDQAZ256rm addr:$src)>; + def : Pat<(v8f32 (alignednontemporalload addr:$src)), + (VMOVNTDQAZ256rm addr:$src)>; + def : Pat<(v4i64 (alignednontemporalload addr:$src)), + (VMOVNTDQAZ256rm addr:$src)>; + + def : Pat<(alignednontemporalstore (v4i32 VR128X:$src), addr:$dst), + (VMOVNTDQZ128mr addr:$dst, VR128X:$src)>; + def : Pat<(alignednontemporalstore (v8i16 VR128X:$src), addr:$dst), + (VMOVNTDQZ128mr addr:$dst, VR128X:$src)>; + def : Pat<(alignednontemporalstore (v16i8 VR128X:$src), addr:$dst), + (VMOVNTDQZ128mr addr:$dst, VR128X:$src)>; + + def : Pat<(v2f64 (alignednontemporalload addr:$src)), + (VMOVNTDQAZ128rm addr:$src)>; + def : Pat<(v4f32 (alignednontemporalload addr:$src)), + (VMOVNTDQAZ128rm addr:$src)>; + def : Pat<(v2i64 (alignednontemporalload addr:$src)), + (VMOVNTDQAZ128rm addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 - Integer arithmetic +// +multiclass avx512_binop_rm opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _, X86FoldableSchedWrite sched, + bit IsCommutable = 0> { + defm rr : AVX512_maskable, AVX512BIBase, EVEX_4V, + Sched<[sched]>; + + defm rm : AVX512_maskable, + AVX512BIBase, EVEX_4V, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_binop_rmb opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _, X86FoldableSchedWrite sched, + bit IsCommutable = 0> : + avx512_binop_rm { + defm rmb : AVX512_maskable, + AVX512BIBase, EVEX_4V, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_binop_rm_vl opc, string OpcodeStr, SDNode OpNode, + AVX512VLVectorVTInfo VTInfo, + X86SchedWriteWidths sched, Predicate prd, + bit IsCommutable = 0> { + let Predicates = [prd] in + defm Z : avx512_binop_rm, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_binop_rm, EVEX_V256; + defm Z128 : avx512_binop_rm, EVEX_V128; + } +} + +multiclass avx512_binop_rmb_vl opc, string OpcodeStr, SDNode OpNode, + AVX512VLVectorVTInfo VTInfo, + X86SchedWriteWidths sched, Predicate prd, + bit IsCommutable = 0> { + let Predicates = [prd] in + defm Z : avx512_binop_rmb, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_binop_rmb, EVEX_V256; + defm Z128 : avx512_binop_rmb, EVEX_V128; + } +} + +multiclass avx512_binop_rm_vl_q opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate prd, + bit IsCommutable = 0> { + defm NAME : avx512_binop_rmb_vl, + VEX_W, EVEX_CD8<64, CD8VF>; +} + +multiclass avx512_binop_rm_vl_d opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate prd, + bit IsCommutable = 0> { + defm NAME : avx512_binop_rmb_vl, EVEX_CD8<32, CD8VF>; +} + +multiclass avx512_binop_rm_vl_w opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate prd, + bit IsCommutable = 0> { + defm NAME : avx512_binop_rm_vl, EVEX_CD8<16, CD8VF>, + VEX_WIG; +} + +multiclass avx512_binop_rm_vl_b opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate prd, + bit IsCommutable = 0> { + defm NAME : avx512_binop_rm_vl, EVEX_CD8<8, CD8VF>, + VEX_WIG; +} + +multiclass avx512_binop_rm_vl_dq opc_d, bits<8> opc_q, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched, + Predicate prd, bit IsCommutable = 0> { + defm Q : avx512_binop_rm_vl_q; + + defm D : avx512_binop_rm_vl_d; +} + +multiclass avx512_binop_rm_vl_bw opc_b, bits<8> opc_w, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched, + Predicate prd, bit IsCommutable = 0> { + defm W : avx512_binop_rm_vl_w; + + defm B : avx512_binop_rm_vl_b; +} + +multiclass avx512_binop_rm_vl_all opc_b, bits<8> opc_w, + bits<8> opc_d, bits<8> opc_q, + string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, + bit IsCommutable = 0> { + defm NAME : avx512_binop_rm_vl_dq, + avx512_binop_rm_vl_bw; +} + +multiclass avx512_binop_rm2 opc, string OpcodeStr, + X86FoldableSchedWrite sched, + SDNode OpNode,X86VectorVTInfo _Src, + X86VectorVTInfo _Dst, X86VectorVTInfo _Brdct, + bit IsCommutable = 0> { + defm rr : AVX512_maskable, + AVX512BIBase, EVEX_4V, Sched<[sched]>; + defm rm : AVX512_maskable, + AVX512BIBase, EVEX_4V, + Sched<[sched.Folded, ReadAfterLd]>; + + defm rmb : AVX512_maskable, + AVX512BIBase, EVEX_4V, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add, + SchedWriteVecALU, 1>; +defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub, + SchedWriteVecALU, 0>; +defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds, + SchedWriteVecALU, HasBWI, 1>; +defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs, + SchedWriteVecALU, HasBWI, 0>; +defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus, + SchedWriteVecALU, HasBWI, 1>; +defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus, + SchedWriteVecALU, HasBWI, 0>; +defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul, + SchedWritePMULLD, HasAVX512, 1>, T8PD; +defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul, + SchedWriteVecIMul, HasBWI, 1>; +defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul, + SchedWriteVecIMul, HasDQI, 1>, T8PD, + NotEVEX2VEXConvertible; +defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SchedWriteVecIMul, + HasBWI, 1>; +defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SchedWriteVecIMul, + HasBWI, 1>; +defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, + SchedWriteVecIMul, HasBWI, 1>, T8PD; +defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg, + SchedWriteVecALU, HasBWI, 1>; +defm VPMULDQ : avx512_binop_rm_vl_q<0x28, "vpmuldq", X86pmuldq, + SchedWriteVecIMul, HasAVX512, 1>, T8PD; +defm VPMULUDQ : avx512_binop_rm_vl_q<0xF4, "vpmuludq", X86pmuludq, + SchedWriteVecIMul, HasAVX512, 1>; + +multiclass avx512_binop_all opc, string OpcodeStr, + X86SchedWriteWidths sched, + AVX512VLVectorVTInfo _SrcVTInfo, + AVX512VLVectorVTInfo _DstVTInfo, + SDNode OpNode, Predicate prd, bit IsCommutable = 0> { + let Predicates = [prd] in + defm NAME#Z : avx512_binop_rm2, + EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W; + let Predicates = [HasVLX, prd] in { + defm NAME#Z256 : avx512_binop_rm2, + EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W; + defm NAME#Z128 : avx512_binop_rm2, + EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W; + } +} + +defm VPMULTISHIFTQB : avx512_binop_all<0x83, "vpmultishiftqb", SchedWriteVecALU, + avx512vl_i8_info, avx512vl_i8_info, + X86multishift, HasVBMI, 0>, T8PD; + +multiclass avx512_packs_rmb opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _Src, X86VectorVTInfo _Dst, + X86FoldableSchedWrite sched> { + defm rmb : AVX512_maskable, + EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_packs_rm opc, string OpcodeStr, + SDNode OpNode,X86VectorVTInfo _Src, + X86VectorVTInfo _Dst, X86FoldableSchedWrite sched, + bit IsCommutable = 0> { + defm rr : AVX512_maskable, + EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V, Sched<[sched]>; + defm rm : AVX512_maskable, + EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_packs_all_i32_i16 opc, string OpcodeStr, + SDNode OpNode> { + let Predicates = [HasBWI] in + defm NAME#Z : avx512_packs_rm, + avx512_packs_rmb, EVEX_V512; + let Predicates = [HasBWI, HasVLX] in { + defm NAME#Z256 : avx512_packs_rm, + avx512_packs_rmb, + EVEX_V256; + defm NAME#Z128 : avx512_packs_rm, + avx512_packs_rmb, + EVEX_V128; + } +} +multiclass avx512_packs_all_i16_i8 opc, string OpcodeStr, + SDNode OpNode> { + let Predicates = [HasBWI] in + defm NAME#Z : avx512_packs_rm, EVEX_V512, VEX_WIG; + let Predicates = [HasBWI, HasVLX] in { + defm NAME#Z256 : avx512_packs_rm, + EVEX_V256, VEX_WIG; + defm NAME#Z128 : avx512_packs_rm, + EVEX_V128, VEX_WIG; + } +} + +multiclass avx512_vpmadd opc, string OpcodeStr, + SDNode OpNode, AVX512VLVectorVTInfo _Src, + AVX512VLVectorVTInfo _Dst, bit IsCommutable = 0> { + let Predicates = [HasBWI] in + defm NAME#Z : avx512_packs_rm, EVEX_V512; + let Predicates = [HasBWI, HasVLX] in { + defm NAME#Z256 : avx512_packs_rm, EVEX_V256; + defm NAME#Z128 : avx512_packs_rm, EVEX_V128; + } +} + +defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, AVX512BIBase; +defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, AVX5128IBase; +defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase; +defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase; + +defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw, + avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD, VEX_WIG; +defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd, + avx512vl_i16_info, avx512vl_i32_info, 1>, AVX512BIBase, VEX_WIG; + +defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax, + SchedWriteVecALU, HasBWI, 1>, T8PD; +defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax, + SchedWriteVecALU, HasBWI, 1>; +defm VPMAXSD : avx512_binop_rm_vl_d<0x3D, "vpmaxsd", smax, + SchedWriteVecALU, HasAVX512, 1>, T8PD; +defm VPMAXSQ : avx512_binop_rm_vl_q<0x3D, "vpmaxsq", smax, + SchedWriteVecALU, HasAVX512, 1>, T8PD, + NotEVEX2VEXConvertible; + +defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax, + SchedWriteVecALU, HasBWI, 1>; +defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax, + SchedWriteVecALU, HasBWI, 1>, T8PD; +defm VPMAXUD : avx512_binop_rm_vl_d<0x3F, "vpmaxud", umax, + SchedWriteVecALU, HasAVX512, 1>, T8PD; +defm VPMAXUQ : avx512_binop_rm_vl_q<0x3F, "vpmaxuq", umax, + SchedWriteVecALU, HasAVX512, 1>, T8PD, + NotEVEX2VEXConvertible; + +defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin, + SchedWriteVecALU, HasBWI, 1>, T8PD; +defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin, + SchedWriteVecALU, HasBWI, 1>; +defm VPMINSD : avx512_binop_rm_vl_d<0x39, "vpminsd", smin, + SchedWriteVecALU, HasAVX512, 1>, T8PD; +defm VPMINSQ : avx512_binop_rm_vl_q<0x39, "vpminsq", smin, + SchedWriteVecALU, HasAVX512, 1>, T8PD, + NotEVEX2VEXConvertible; + +defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin, + SchedWriteVecALU, HasBWI, 1>; +defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin, + SchedWriteVecALU, HasBWI, 1>, T8PD; +defm VPMINUD : avx512_binop_rm_vl_d<0x3B, "vpminud", umin, + SchedWriteVecALU, HasAVX512, 1>, T8PD; +defm VPMINUQ : avx512_binop_rm_vl_q<0x3B, "vpminuq", umin, + SchedWriteVecALU, HasAVX512, 1>, T8PD, + NotEVEX2VEXConvertible; + +// PMULLQ: Use 512bit version to implement 128/256 bit in case NoVLX. +let Predicates = [HasDQI, NoVLX] in { + def : Pat<(v4i64 (mul (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))), + (EXTRACT_SUBREG + (VPMULLQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)), + sub_ymm)>; + + def : Pat<(v2i64 (mul (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG + (VPMULLQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)), + sub_xmm)>; +} + +// PMULLQ: Use 512bit version to implement 128/256 bit in case NoVLX. +let Predicates = [HasDQI, NoVLX] in { + def : Pat<(v4i64 (mul (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))), + (EXTRACT_SUBREG + (VPMULLQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)), + sub_ymm)>; + + def : Pat<(v2i64 (mul (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG + (VPMULLQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)), + sub_xmm)>; +} + +multiclass avx512_min_max_lowering { + def : Pat<(v4i64 (OpNode VR256X:$src1, VR256X:$src2)), + (EXTRACT_SUBREG + (Instr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)), + sub_ymm)>; + + def : Pat<(v2i64 (OpNode VR128X:$src1, VR128X:$src2)), + (EXTRACT_SUBREG + (Instr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)), + sub_xmm)>; +} + +let Predicates = [HasAVX512, NoVLX] in { + defm : avx512_min_max_lowering; + defm : avx512_min_max_lowering; + defm : avx512_min_max_lowering; + defm : avx512_min_max_lowering; +} + +//===----------------------------------------------------------------------===// +// AVX-512 Logical Instructions +//===----------------------------------------------------------------------===// + +// OpNodeMsk is the OpNode to use when element size is important. OpNode will +// be set to null_frag for 32-bit elements. +multiclass avx512_logic_rm opc, string OpcodeStr, + SDPatternOperator OpNode, + SDNode OpNodeMsk, X86FoldableSchedWrite sched, + X86VectorVTInfo _, bit IsCommutable = 0> { + let hasSideEffects = 0 in + defm rr : AVX512_maskable_logic, AVX512BIBase, EVEX_4V, + Sched<[sched]>; + + let hasSideEffects = 0, mayLoad = 1 in + defm rm : AVX512_maskable_logic, + AVX512BIBase, EVEX_4V, + Sched<[sched.Folded, ReadAfterLd]>; +} + +// OpNodeMsk is the OpNode to use where element size is important. So use +// for all of the broadcast patterns. +multiclass avx512_logic_rmb opc, string OpcodeStr, + SDPatternOperator OpNode, + SDNode OpNodeMsk, X86FoldableSchedWrite sched, X86VectorVTInfo _, + bit IsCommutable = 0> : + avx512_logic_rm { + defm rmb : AVX512_maskable_logic, + AVX512BIBase, EVEX_4V, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_logic_rmb_vl opc, string OpcodeStr, + SDPatternOperator OpNode, + SDNode OpNodeMsk, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo, + bit IsCommutable = 0> { + let Predicates = [HasAVX512] in + defm Z : avx512_logic_rmb, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in { + defm Z256 : avx512_logic_rmb, EVEX_V256; + defm Z128 : avx512_logic_rmb, EVEX_V128; + } +} + +multiclass avx512_logic_rm_vl_dq opc_d, bits<8> opc_q, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched, + bit IsCommutable = 0> { + defm Q : avx512_logic_rmb_vl, + VEX_W, EVEX_CD8<64, CD8VF>; + defm D : avx512_logic_rmb_vl, + EVEX_CD8<32, CD8VF>; +} + +defm VPAND : avx512_logic_rm_vl_dq<0xDB, 0xDB, "vpand", and, + SchedWriteVecLogic, 1>; +defm VPOR : avx512_logic_rm_vl_dq<0xEB, 0xEB, "vpor", or, + SchedWriteVecLogic, 1>; +defm VPXOR : avx512_logic_rm_vl_dq<0xEF, 0xEF, "vpxor", xor, + SchedWriteVecLogic, 1>; +defm VPANDN : avx512_logic_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp, + SchedWriteVecLogic>; + +//===----------------------------------------------------------------------===// +// AVX-512 FP arithmetic +//===----------------------------------------------------------------------===// + +multiclass avx512_fp_scalar opc, string OpcodeStr,X86VectorVTInfo _, + SDNode OpNode, SDNode VecNode, + X86FoldableSchedWrite sched, bit IsCommutable> { + let ExeDomain = _.ExeDomain in { + defm rr_Int : AVX512_maskable_scalar, + Sched<[sched]>; + + defm rm_Int : AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + let isCodeGenOnly = 1, Predicates = [HasAVX512] in { + def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst), + (ins _.FRC:$src1, _.FRC:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>, + Sched<[sched]> { + let isCommutable = IsCommutable; + } + def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst), + (ins _.FRC:$src1, _.ScalarMemOp:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.FRC:$dst, (OpNode _.FRC:$src1, + (_.ScalarLdFrag addr:$src2)))]>, + Sched<[sched.Folded, ReadAfterLd]>; + } + } +} + +multiclass avx512_fp_scalar_round opc, string OpcodeStr,X86VectorVTInfo _, + SDNode VecNode, X86FoldableSchedWrite sched, + bit IsCommutable = 0> { + let ExeDomain = _.ExeDomain in + defm rrb_Int : AVX512_maskable_scalar, + EVEX_B, EVEX_RC, Sched<[sched]>; +} +multiclass avx512_fp_scalar_sae opc, string OpcodeStr,X86VectorVTInfo _, + SDNode OpNode, SDNode VecNode, SDNode SaeNode, + X86FoldableSchedWrite sched, bit IsCommutable> { + let ExeDomain = _.ExeDomain in { + defm rr_Int : AVX512_maskable_scalar, + Sched<[sched]>; + + defm rm_Int : AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + + let isCodeGenOnly = 1, Predicates = [HasAVX512] in { + def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst), + (ins _.FRC:$src1, _.FRC:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>, + Sched<[sched]> { + let isCommutable = IsCommutable; + } + def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst), + (ins _.FRC:$src1, _.ScalarMemOp:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.FRC:$dst, (OpNode _.FRC:$src1, + (_.ScalarLdFrag addr:$src2)))]>, + Sched<[sched.Folded, ReadAfterLd]>; + } + + defm rrb_Int : AVX512_maskable_scalar, EVEX_B, + Sched<[sched]>; + } +} + +multiclass avx512_binop_s_round opc, string OpcodeStr, SDNode OpNode, + SDNode VecNode, X86SchedWriteSizes sched, + bit IsCommutable> { + defm SSZ : avx512_fp_scalar, + avx512_fp_scalar_round, + XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>; + defm SDZ : avx512_fp_scalar, + avx512_fp_scalar_round, + XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>; +} + +multiclass avx512_binop_s_sae opc, string OpcodeStr, SDNode OpNode, + SDNode VecNode, SDNode SaeNode, + X86SchedWriteSizes sched, bit IsCommutable> { + defm SSZ : avx512_fp_scalar_sae, + XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>; + defm SDZ : avx512_fp_scalar_sae, + XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>; +} +defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnds, + SchedWriteFAddSizes, 1>; +defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnds, + SchedWriteFMulSizes, 1>; +defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnds, + SchedWriteFAddSizes, 0>; +defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnds, + SchedWriteFDivSizes, 0>; +defm VMIN : avx512_binop_s_sae<0x5D, "vmin", X86fmin, X86fmins, X86fminRnds, + SchedWriteFCmpSizes, 0>; +defm VMAX : avx512_binop_s_sae<0x5F, "vmax", X86fmax, X86fmaxs, X86fmaxRnds, + SchedWriteFCmpSizes, 0>; + +// MIN/MAX nodes are commutable under "unsafe-fp-math". In this case we use +// X86fminc and X86fmaxc instead of X86fmin and X86fmax +multiclass avx512_comutable_binop_s opc, string OpcodeStr, + X86VectorVTInfo _, SDNode OpNode, + X86FoldableSchedWrite sched> { + let isCodeGenOnly = 1, Predicates = [HasAVX512], ExeDomain = _.ExeDomain in { + def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst), + (ins _.FRC:$src1, _.FRC:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>, + Sched<[sched]> { + let isCommutable = 1; + } + def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst), + (ins _.FRC:$src1, _.ScalarMemOp:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.FRC:$dst, (OpNode _.FRC:$src1, + (_.ScalarLdFrag addr:$src2)))]>, + Sched<[sched.Folded, ReadAfterLd]>; + } +} +defm VMINCSSZ : avx512_comutable_binop_s<0x5D, "vminss", f32x_info, X86fminc, + SchedWriteFCmp.Scl>, XS, EVEX_4V, + VEX_LIG, EVEX_CD8<32, CD8VT1>; + +defm VMINCSDZ : avx512_comutable_binop_s<0x5D, "vminsd", f64x_info, X86fminc, + SchedWriteFCmp.Scl>, XD, VEX_W, EVEX_4V, + VEX_LIG, EVEX_CD8<64, CD8VT1>; + +defm VMAXCSSZ : avx512_comutable_binop_s<0x5F, "vmaxss", f32x_info, X86fmaxc, + SchedWriteFCmp.Scl>, XS, EVEX_4V, + VEX_LIG, EVEX_CD8<32, CD8VT1>; + +defm VMAXCSDZ : avx512_comutable_binop_s<0x5F, "vmaxsd", f64x_info, X86fmaxc, + SchedWriteFCmp.Scl>, XD, VEX_W, EVEX_4V, + VEX_LIG, EVEX_CD8<64, CD8VT1>; + +multiclass avx512_fp_packed opc, string OpcodeStr, SDPatternOperator OpNode, + X86VectorVTInfo _, X86FoldableSchedWrite sched, + bit IsCommutable, + bit IsKZCommutable = IsCommutable> { + let ExeDomain = _.ExeDomain, hasSideEffects = 0 in { + defm rr: AVX512_maskable, + EVEX_4V, Sched<[sched]>; + let mayLoad = 1 in { + defm rm: AVX512_maskable, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + defm rmb: AVX512_maskable, + EVEX_4V, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } + } +} + +multiclass avx512_fp_round_packed opc, string OpcodeStr, + SDPatternOperator OpNodeRnd, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm rrb: AVX512_maskable, + EVEX_4V, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +multiclass avx512_fp_sae_packed opc, string OpcodeStr, + SDPatternOperator OpNodeRnd, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm rrb: AVX512_maskable, + EVEX_4V, EVEX_B, Sched<[sched]>; +} + +multiclass avx512_fp_binop_p opc, string OpcodeStr, SDPatternOperator OpNode, + Predicate prd, X86SchedWriteSizes sched, + bit IsCommutable = 0, + bit IsPD128Commutable = IsCommutable> { + let Predicates = [prd] in { + defm PSZ : avx512_fp_packed, EVEX_V512, PS, + EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp_packed, EVEX_V512, PD, VEX_W, + EVEX_CD8<64, CD8VF>; + } + + // Define only if AVX512VL feature is present. + let Predicates = [prd, HasVLX] in { + defm PSZ128 : avx512_fp_packed, EVEX_V128, PS, + EVEX_CD8<32, CD8VF>; + defm PSZ256 : avx512_fp_packed, EVEX_V256, PS, + EVEX_CD8<32, CD8VF>; + defm PDZ128 : avx512_fp_packed, EVEX_V128, PD, VEX_W, + EVEX_CD8<64, CD8VF>; + defm PDZ256 : avx512_fp_packed, EVEX_V256, PD, VEX_W, + EVEX_CD8<64, CD8VF>; + } +} + +multiclass avx512_fp_binop_p_round opc, string OpcodeStr, SDNode OpNodeRnd, + X86SchedWriteSizes sched> { + defm PSZ : avx512_fp_round_packed, + EVEX_V512, PS, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp_round_packed, + EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>; +} + +multiclass avx512_fp_binop_p_sae opc, string OpcodeStr, SDNode OpNodeRnd, + X86SchedWriteSizes sched> { + defm PSZ : avx512_fp_sae_packed, + EVEX_V512, PS, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp_sae_packed, + EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>; +} + +defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, HasAVX512, + SchedWriteFAddSizes, 1>, + avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd, SchedWriteFAddSizes>; +defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, HasAVX512, + SchedWriteFMulSizes, 1>, + avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd, SchedWriteFMulSizes>; +defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub, HasAVX512, + SchedWriteFAddSizes>, + avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd, SchedWriteFAddSizes>; +defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv, HasAVX512, + SchedWriteFDivSizes>, + avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd, SchedWriteFDivSizes>; +defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, HasAVX512, + SchedWriteFCmpSizes, 0>, + avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd, SchedWriteFCmpSizes>; +defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, HasAVX512, + SchedWriteFCmpSizes, 0>, + avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd, SchedWriteFCmpSizes>; +let isCodeGenOnly = 1 in { + defm VMINC : avx512_fp_binop_p<0x5D, "vmin", X86fminc, HasAVX512, + SchedWriteFCmpSizes, 1>; + defm VMAXC : avx512_fp_binop_p<0x5F, "vmax", X86fmaxc, HasAVX512, + SchedWriteFCmpSizes, 1>; +} +defm VAND : avx512_fp_binop_p<0x54, "vand", null_frag, HasDQI, + SchedWriteFLogicSizes, 1>; +defm VANDN : avx512_fp_binop_p<0x55, "vandn", null_frag, HasDQI, + SchedWriteFLogicSizes, 0>; +defm VOR : avx512_fp_binop_p<0x56, "vor", null_frag, HasDQI, + SchedWriteFLogicSizes, 1>; +defm VXOR : avx512_fp_binop_p<0x57, "vxor", null_frag, HasDQI, + SchedWriteFLogicSizes, 1>; + +// Patterns catch floating point selects with bitcasted integer logic ops. +multiclass avx512_fp_logical_lowering { +let Predicates = [prd] in { + // Masked register-register logical operations. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (bitconvert (_.i64VT (OpNode _.RC:$src1, _.RC:$src2))), + _.RC:$src0)), + (!cast(InstrStr#rrk) _.RC:$src0, _.KRCWM:$mask, + _.RC:$src1, _.RC:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (bitconvert (_.i64VT (OpNode _.RC:$src1, _.RC:$src2))), + _.ImmAllZerosV)), + (!cast(InstrStr#rrkz) _.KRCWM:$mask, _.RC:$src1, + _.RC:$src2)>; + // Masked register-memory logical operations. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (bitconvert (_.i64VT (OpNode _.RC:$src1, + (load addr:$src2)))), + _.RC:$src0)), + (!cast(InstrStr#rmk) _.RC:$src0, _.KRCWM:$mask, + _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (bitconvert (_.i64VT (OpNode _.RC:$src1, (load addr:$src2)))), + _.ImmAllZerosV)), + (!cast(InstrStr#rmkz) _.KRCWM:$mask, _.RC:$src1, + addr:$src2)>; + // Register-broadcast logical operations. + def : Pat<(_.i64VT (OpNode _.RC:$src1, + (bitconvert (_.VT (X86VBroadcast + (_.ScalarLdFrag addr:$src2)))))), + (!cast(InstrStr#rmb) _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (bitconvert + (_.i64VT (OpNode _.RC:$src1, + (bitconvert (_.VT + (X86VBroadcast + (_.ScalarLdFrag addr:$src2))))))), + _.RC:$src0)), + (!cast(InstrStr#rmbk) _.RC:$src0, _.KRCWM:$mask, + _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (bitconvert + (_.i64VT (OpNode _.RC:$src1, + (bitconvert (_.VT + (X86VBroadcast + (_.ScalarLdFrag addr:$src2))))))), + _.ImmAllZerosV)), + (!cast(InstrStr#rmbkz) _.KRCWM:$mask, + _.RC:$src1, addr:$src2)>; +} +} + +multiclass avx512_fp_logical_lowering_sizes { + defm : avx512_fp_logical_lowering; + defm : avx512_fp_logical_lowering; + defm : avx512_fp_logical_lowering; + defm : avx512_fp_logical_lowering; + defm : avx512_fp_logical_lowering; + defm : avx512_fp_logical_lowering; +} + +defm : avx512_fp_logical_lowering_sizes<"VPAND", and>; +defm : avx512_fp_logical_lowering_sizes<"VPOR", or>; +defm : avx512_fp_logical_lowering_sizes<"VPXOR", xor>; +defm : avx512_fp_logical_lowering_sizes<"VPANDN", X86andnp>; + +let Predicates = [HasVLX,HasDQI] in { + // Use packed logical operations for scalar ops. + def : Pat<(f64 (X86fand FR64X:$src1, FR64X:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VANDPDZ128rr (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)), + (v2f64 (COPY_TO_REGCLASS FR64X:$src2, VR128X)))), + FR64X)>; + def : Pat<(f64 (X86for FR64X:$src1, FR64X:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VORPDZ128rr (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)), + (v2f64 (COPY_TO_REGCLASS FR64X:$src2, VR128X)))), + FR64X)>; + def : Pat<(f64 (X86fxor FR64X:$src1, FR64X:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VXORPDZ128rr (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)), + (v2f64 (COPY_TO_REGCLASS FR64X:$src2, VR128X)))), + FR64X)>; + def : Pat<(f64 (X86fandn FR64X:$src1, FR64X:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VANDNPDZ128rr (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)), + (v2f64 (COPY_TO_REGCLASS FR64X:$src2, VR128X)))), + FR64X)>; + + def : Pat<(f32 (X86fand FR32X:$src1, FR32X:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VANDPSZ128rr (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)), + (v4f32 (COPY_TO_REGCLASS FR32X:$src2, VR128X)))), + FR32X)>; + def : Pat<(f32 (X86for FR32X:$src1, FR32X:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VORPSZ128rr (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)), + (v4f32 (COPY_TO_REGCLASS FR32X:$src2, VR128X)))), + FR32X)>; + def : Pat<(f32 (X86fxor FR32X:$src1, FR32X:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VXORPSZ128rr (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)), + (v4f32 (COPY_TO_REGCLASS FR32X:$src2, VR128X)))), + FR32X)>; + def : Pat<(f32 (X86fandn FR32X:$src1, FR32X:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VANDNPSZ128rr (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)), + (v4f32 (COPY_TO_REGCLASS FR32X:$src2, VR128X)))), + FR32X)>; +} + +multiclass avx512_fp_scalef_p opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rr: AVX512_maskable, + EVEX_4V, Sched<[sched]>; + defm rm: AVX512_maskable, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + defm rmb: AVX512_maskable, + EVEX_4V, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fp_scalef_scalar opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rr: AVX512_maskable_scalar, + Sched<[sched]>; + defm rm: AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fp_scalef_all opc, bits<8> opcScaler, string OpcodeStr, + SDNode OpNode, SDNode OpNodeScal, + X86SchedWriteWidths sched> { + defm PSZ : avx512_fp_scalef_p, + avx512_fp_round_packed, + EVEX_V512, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp_scalef_p, + avx512_fp_round_packed, + EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; + defm SSZ : avx512_fp_scalef_scalar, + avx512_fp_scalar_round, + EVEX_4V,EVEX_CD8<32, CD8VT1>; + defm SDZ : avx512_fp_scalef_scalar, + avx512_fp_scalar_round, + EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; + + // Define only if AVX512VL feature is present. + let Predicates = [HasVLX] in { + defm PSZ128 : avx512_fp_scalef_p, + EVEX_V128, EVEX_CD8<32, CD8VF>; + defm PSZ256 : avx512_fp_scalef_p, + EVEX_V256, EVEX_CD8<32, CD8VF>; + defm PDZ128 : avx512_fp_scalef_p, + EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>; + defm PDZ256 : avx512_fp_scalef_p, + EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>; + } +} +defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef, X86scalefs, + SchedWriteFAdd>, T8PD, NotEVEX2VEXConvertible; + +//===----------------------------------------------------------------------===// +// AVX-512 VPTESTM instructions +//===----------------------------------------------------------------------===// + +multiclass avx512_vptest opc, string OpcodeStr, PatFrag OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + string Name> { + let ExeDomain = _.ExeDomain in { + let isCommutable = 1 in + defm rr : AVX512_maskable_cmp, + EVEX_4V, Sched<[sched]>; + defm rm : AVX512_maskable_cmp, + EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + } + + // Patterns for compare with 0 that just use the same source twice. + def : Pat<(_.KVT (OpNode _.RC:$src, _.ImmAllZerosV)), + (_.KVT (!cast(Name # _.ZSuffix # "rr") + _.RC:$src, _.RC:$src))>; + + def : Pat<(_.KVT (and _.KRC:$mask, (OpNode _.RC:$src, _.ImmAllZerosV))), + (_.KVT (!cast(Name # _.ZSuffix # "rrk") + _.KRC:$mask, _.RC:$src, _.RC:$src))>; +} + +multiclass avx512_vptest_mb opc, string OpcodeStr, PatFrag OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm rmb : AVX512_maskable_cmp, + EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +// Use 512bit version to implement 128/256 bit in case NoVLX. +multiclass avx512_vptest_lowering { + def : Pat<(_.KVT (OpNode (bitconvert (_.i64VT (and _.RC:$src1, _.RC:$src2))), + _.ImmAllZerosV)), + (_.KVT (COPY_TO_REGCLASS + (!cast(Name # "Zrr") + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src1, _.SubRegIdx), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src2, _.SubRegIdx)), + _.KRC))>; + + def : Pat<(_.KVT (and _.KRC:$mask, + (OpNode (bitconvert (_.i64VT (and _.RC:$src1, _.RC:$src2))), + _.ImmAllZerosV))), + (COPY_TO_REGCLASS + (!cast(Name # "Zrrk") + (COPY_TO_REGCLASS _.KRC:$mask, ExtendInfo.KRC), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src1, _.SubRegIdx), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src2, _.SubRegIdx)), + _.KRC)>; + + def : Pat<(_.KVT (OpNode _.RC:$src, _.ImmAllZerosV)), + (_.KVT (COPY_TO_REGCLASS + (!cast(Name # "Zrr") + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src, _.SubRegIdx), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src, _.SubRegIdx)), + _.KRC))>; + + def : Pat<(_.KVT (and _.KRC:$mask, (OpNode _.RC:$src, _.ImmAllZerosV))), + (COPY_TO_REGCLASS + (!cast(Name # "Zrrk") + (COPY_TO_REGCLASS _.KRC:$mask, ExtendInfo.KRC), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src, _.SubRegIdx), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src, _.SubRegIdx)), + _.KRC)>; +} + +multiclass avx512_vptest_dq_sizes opc, string OpcodeStr, PatFrag OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo _> { + let Predicates = [HasAVX512] in + defm Z : avx512_vptest, + avx512_vptest_mb, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in { + defm Z256 : avx512_vptest, + avx512_vptest_mb, EVEX_V256; + defm Z128 : avx512_vptest, + avx512_vptest_mb, EVEX_V128; + } + let Predicates = [HasAVX512, NoVLX] in { + defm Z256_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info256, NAME>; + defm Z128_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info128, NAME>; + } +} + +multiclass avx512_vptest_dq opc, string OpcodeStr, PatFrag OpNode, + X86SchedWriteWidths sched> { + defm D : avx512_vptest_dq_sizes; + defm Q : avx512_vptest_dq_sizes, VEX_W; +} + +multiclass avx512_vptest_wb opc, string OpcodeStr, + PatFrag OpNode, X86SchedWriteWidths sched> { + let Predicates = [HasBWI] in { + defm WZ: avx512_vptest, EVEX_V512, VEX_W; + defm BZ: avx512_vptest, EVEX_V512; + } + let Predicates = [HasVLX, HasBWI] in { + + defm WZ256: avx512_vptest, EVEX_V256, VEX_W; + defm WZ128: avx512_vptest, EVEX_V128, VEX_W; + defm BZ256: avx512_vptest, EVEX_V256; + defm BZ128: avx512_vptest, EVEX_V128; + } + + let Predicates = [HasAVX512, NoVLX] in { + defm BZ256_Alt : avx512_vptest_lowering; + defm BZ128_Alt : avx512_vptest_lowering; + defm WZ256_Alt : avx512_vptest_lowering; + defm WZ128_Alt : avx512_vptest_lowering; + } +} + +// These patterns are used to match vptestm/vptestnm. We don't treat pcmpeqm +// as commutable here because we already canonicalized all zeros vectors to the +// RHS during lowering. +def X86pcmpeqm : PatFrag<(ops node:$src1, node:$src2), + (setcc node:$src1, node:$src2, SETEQ)>; +def X86pcmpnem : PatFrag<(ops node:$src1, node:$src2), + (setcc node:$src1, node:$src2, SETNE)>; + +multiclass avx512_vptest_all_forms opc_wb, bits<8> opc_dq, string OpcodeStr, + PatFrag OpNode, X86SchedWriteWidths sched> : + avx512_vptest_wb, + avx512_vptest_dq; + +defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86pcmpnem, + SchedWriteVecLogic>, T8PD; +defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86pcmpeqm, + SchedWriteVecLogic>, T8XS; + +//===----------------------------------------------------------------------===// +// AVX-512 Shift instructions +//===----------------------------------------------------------------------===// + +multiclass avx512_shift_rmi opc, Format ImmFormR, Format ImmFormM, + string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm ri : AVX512_maskable, + Sched<[sched]>; + defm mi : AVX512_maskable, + Sched<[sched.Folded]>; + } +} + +multiclass avx512_shift_rmbi opc, Format ImmFormM, + string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm mbi : AVX512_maskable, + EVEX_B, Sched<[sched.Folded]>; +} + +multiclass avx512_shift_rrm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, ValueType SrcVT, + PatFrag bc_frag, X86VectorVTInfo _> { + // src2 is always 128-bit + let ExeDomain = _.ExeDomain in { + defm rr : AVX512_maskable, + AVX512BIBase, EVEX_4V, Sched<[sched]>; + defm rm : AVX512_maskable, + AVX512BIBase, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_shift_sizes opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, ValueType SrcVT, + PatFrag bc_frag, AVX512VLVectorVTInfo VTInfo, + Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_shift_rrm, EVEX_V512, + EVEX_CD8 ; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_shift_rrm, EVEX_V256, + EVEX_CD8; + defm Z128 : avx512_shift_rrm, EVEX_V128, + EVEX_CD8; + } +} + +multiclass avx512_shift_types opcd, bits<8> opcq, bits<8> opcw, + string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, + bit NotEVEX2VEXConvertibleQ = 0> { + defm D : avx512_shift_sizes; + let notEVEX2VEXConvertible = NotEVEX2VEXConvertibleQ in + defm Q : avx512_shift_sizes, VEX_W; + defm W : avx512_shift_sizes; +} + +multiclass avx512_shift_rmi_sizes opc, Format ImmFormR, Format ImmFormM, + string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo> { + let Predicates = [HasAVX512] in + defm Z: avx512_shift_rmi, + avx512_shift_rmbi, EVEX_V512; + let Predicates = [HasAVX512, HasVLX] in { + defm Z256: avx512_shift_rmi, + avx512_shift_rmbi, EVEX_V256; + defm Z128: avx512_shift_rmi, + avx512_shift_rmbi, EVEX_V128; + } +} + +multiclass avx512_shift_rmi_w opcw, Format ImmFormR, Format ImmFormM, + string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + let Predicates = [HasBWI] in + defm WZ: avx512_shift_rmi, EVEX_V512, VEX_WIG; + let Predicates = [HasVLX, HasBWI] in { + defm WZ256: avx512_shift_rmi, EVEX_V256, VEX_WIG; + defm WZ128: avx512_shift_rmi, EVEX_V128, VEX_WIG; + } +} + +multiclass avx512_shift_rmi_dq opcd, bits<8> opcq, + Format ImmFormR, Format ImmFormM, + string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, + bit NotEVEX2VEXConvertibleQ = 0> { + defm D: avx512_shift_rmi_sizes, EVEX_CD8<32, CD8VF>; + let notEVEX2VEXConvertible = NotEVEX2VEXConvertibleQ in + defm Q: avx512_shift_rmi_sizes, EVEX_CD8<64, CD8VF>, VEX_W; +} + +defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli, + SchedWriteVecShiftImm>, + avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli, + SchedWriteVecShiftImm>, AVX512BIi8Base, EVEX_4V; + +defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli, + SchedWriteVecShiftImm>, + avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli, + SchedWriteVecShiftImm>, AVX512BIi8Base, EVEX_4V; + +defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai, + SchedWriteVecShiftImm, 1>, + avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai, + SchedWriteVecShiftImm>, AVX512BIi8Base, EVEX_4V; + +defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", X86vrotri, + SchedWriteVecShiftImm>, AVX512BIi8Base, EVEX_4V; +defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", X86vrotli, + SchedWriteVecShiftImm>, AVX512BIi8Base, EVEX_4V; + +defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl, + SchedWriteVecShift>; +defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra, + SchedWriteVecShift, 1>; +defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl, + SchedWriteVecShift>; + +// Use 512bit VPSRA/VPSRAI version to implement v2i64/v4i64 in case NoVLX. +let Predicates = [HasAVX512, NoVLX] in { + def : Pat<(v4i64 (X86vsra (v4i64 VR256X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPSRAQZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + VR128X:$src2)), sub_ymm)>; + + def : Pat<(v2i64 (X86vsra (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPSRAQZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + VR128X:$src2)), sub_xmm)>; + + def : Pat<(v4i64 (X86vsrai (v4i64 VR256X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPSRAQZri + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + imm:$src2)), sub_ymm)>; + + def : Pat<(v2i64 (X86vsrai (v2i64 VR128X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPSRAQZri + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + imm:$src2)), sub_xmm)>; +} + +//===-------------------------------------------------------------------===// +// Variable Bit Shifts +//===-------------------------------------------------------------------===// + +multiclass avx512_var_shift opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rr : AVX512_maskable, + AVX5128IBase, EVEX_4V, Sched<[sched]>; + defm rm : AVX512_maskable, + AVX5128IBase, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_var_shift_mb opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm rmb : AVX512_maskable, + AVX5128IBase, EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_var_shift_sizes opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo _> { + let Predicates = [HasAVX512] in + defm Z : avx512_var_shift, + avx512_var_shift_mb, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in { + defm Z256 : avx512_var_shift, + avx512_var_shift_mb, EVEX_V256; + defm Z128 : avx512_var_shift, + avx512_var_shift_mb, EVEX_V128; + } +} + +multiclass avx512_var_shift_types opc, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched> { + defm D : avx512_var_shift_sizes; + defm Q : avx512_var_shift_sizes, VEX_W; +} + +// Use 512bit version to implement 128/256 bit in case NoVLX. +multiclass avx512_var_shift_lowering p> { + let Predicates = p in { + def : Pat<(_.info256.VT (OpNode (_.info256.VT _.info256.RC:$src1), + (_.info256.VT _.info256.RC:$src2))), + (EXTRACT_SUBREG + (!cast(OpcodeStr#"Zrr") + (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src1, sub_ymm), + (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)), + sub_ymm)>; + + def : Pat<(_.info128.VT (OpNode (_.info128.VT _.info128.RC:$src1), + (_.info128.VT _.info128.RC:$src2))), + (EXTRACT_SUBREG + (!cast(OpcodeStr#"Zrr") + (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src1, sub_xmm), + (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)), + sub_xmm)>; + } +} +multiclass avx512_var_shift_w opc, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched> { + let Predicates = [HasBWI] in + defm WZ: avx512_var_shift, + EVEX_V512, VEX_W; + let Predicates = [HasVLX, HasBWI] in { + + defm WZ256: avx512_var_shift, + EVEX_V256, VEX_W; + defm WZ128: avx512_var_shift, + EVEX_V128, VEX_W; + } +} + +defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl, SchedWriteVarVecShift>, + avx512_var_shift_w<0x12, "vpsllvw", shl, SchedWriteVarVecShift>; + +defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra, SchedWriteVarVecShift>, + avx512_var_shift_w<0x11, "vpsravw", sra, SchedWriteVarVecShift>; + +defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl, SchedWriteVarVecShift>, + avx512_var_shift_w<0x10, "vpsrlvw", srl, SchedWriteVarVecShift>; + +defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr, SchedWriteVarVecShift>; +defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl, SchedWriteVarVecShift>; + +defm : avx512_var_shift_lowering; +defm : avx512_var_shift_lowering; +defm : avx512_var_shift_lowering; +defm : avx512_var_shift_lowering; + +// Special handing for handling VPSRAV intrinsics. +multiclass avx512_var_shift_int_lowering p> { + let Predicates = p in { + def : Pat<(_.VT (X86vsrav _.RC:$src1, _.RC:$src2)), + (!cast(InstrStr#_.ZSuffix#rr) _.RC:$src1, + _.RC:$src2)>; + def : Pat<(_.VT (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2)))), + (!cast(InstrStr#_.ZSuffix##rm) + _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86vsrav _.RC:$src1, _.RC:$src2), _.RC:$src0)), + (!cast(InstrStr#_.ZSuffix#rrk) _.RC:$src0, + _.KRC:$mask, _.RC:$src1, _.RC:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2))), + _.RC:$src0)), + (!cast(InstrStr#_.ZSuffix##rmk) _.RC:$src0, + _.KRC:$mask, _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86vsrav _.RC:$src1, _.RC:$src2), _.ImmAllZerosV)), + (!cast(InstrStr#_.ZSuffix#rrkz) _.KRC:$mask, + _.RC:$src1, _.RC:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2))), + _.ImmAllZerosV)), + (!cast(InstrStr#_.ZSuffix##rmkz) _.KRC:$mask, + _.RC:$src1, addr:$src2)>; + } +} + +multiclass avx512_var_shift_int_lowering_mb p> : + avx512_var_shift_int_lowering { + let Predicates = p in { + def : Pat<(_.VT (X86vsrav _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src2)))), + (!cast(InstrStr#_.ZSuffix##rmb) + _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86vsrav _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src2))), + _.RC:$src0)), + (!cast(InstrStr#_.ZSuffix##rmbk) _.RC:$src0, + _.KRC:$mask, _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86vsrav _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src2))), + _.ImmAllZerosV)), + (!cast(InstrStr#_.ZSuffix##rmbkz) _.KRC:$mask, + _.RC:$src1, addr:$src2)>; + } +} + +defm : avx512_var_shift_int_lowering<"VPSRAVW", v8i16x_info, [HasVLX, HasBWI]>; +defm : avx512_var_shift_int_lowering<"VPSRAVW", v16i16x_info, [HasVLX, HasBWI]>; +defm : avx512_var_shift_int_lowering<"VPSRAVW", v32i16_info, [HasBWI]>; +defm : avx512_var_shift_int_lowering_mb<"VPSRAVD", v4i32x_info, [HasVLX]>; +defm : avx512_var_shift_int_lowering_mb<"VPSRAVD", v8i32x_info, [HasVLX]>; +defm : avx512_var_shift_int_lowering_mb<"VPSRAVD", v16i32_info, [HasAVX512]>; +defm : avx512_var_shift_int_lowering_mb<"VPSRAVQ", v2i64x_info, [HasVLX]>; +defm : avx512_var_shift_int_lowering_mb<"VPSRAVQ", v4i64x_info, [HasVLX]>; +defm : avx512_var_shift_int_lowering_mb<"VPSRAVQ", v8i64_info, [HasAVX512]>; + +// Use 512bit VPROL/VPROLI version to implement v2i64/v4i64 + v4i32/v8i32 in case NoVLX. +let Predicates = [HasAVX512, NoVLX] in { + def : Pat<(v2i64 (rotl (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPROLVQZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src2, sub_xmm)))), + sub_xmm)>; + def : Pat<(v4i64 (rotl (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPROLVQZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm)))), + sub_ymm)>; + + def : Pat<(v4i32 (rotl (v4i32 VR128X:$src1), (v4i32 VR128X:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPROLVDZrr + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src2, sub_xmm)))), + sub_xmm)>; + def : Pat<(v8i32 (rotl (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPROLVDZrr + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm)))), + sub_ymm)>; + + def : Pat<(v2i64 (X86vrotli (v2i64 VR128X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPROLQZri + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + imm:$src2)), sub_xmm)>; + def : Pat<(v4i64 (X86vrotli (v4i64 VR256X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPROLQZri + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + imm:$src2)), sub_ymm)>; + + def : Pat<(v4i32 (X86vrotli (v4i32 VR128X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPROLDZri + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + imm:$src2)), sub_xmm)>; + def : Pat<(v8i32 (X86vrotli (v8i32 VR256X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPROLDZri + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + imm:$src2)), sub_ymm)>; +} + +// Use 512bit VPROR/VPRORI version to implement v2i64/v4i64 + v4i32/v8i32 in case NoVLX. +let Predicates = [HasAVX512, NoVLX] in { + def : Pat<(v2i64 (rotr (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPRORVQZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src2, sub_xmm)))), + sub_xmm)>; + def : Pat<(v4i64 (rotr (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPRORVQZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm)))), + sub_ymm)>; + + def : Pat<(v4i32 (rotr (v4i32 VR128X:$src1), (v4i32 VR128X:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPRORVDZrr + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src2, sub_xmm)))), + sub_xmm)>; + def : Pat<(v8i32 (rotr (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPRORVDZrr + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm)))), + sub_ymm)>; + + def : Pat<(v2i64 (X86vrotri (v2i64 VR128X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPRORQZri + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + imm:$src2)), sub_xmm)>; + def : Pat<(v4i64 (X86vrotri (v4i64 VR256X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPRORQZri + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + imm:$src2)), sub_ymm)>; + + def : Pat<(v4i32 (X86vrotri (v4i32 VR128X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPRORDZri + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + imm:$src2)), sub_xmm)>; + def : Pat<(v8i32 (X86vrotri (v8i32 VR256X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPRORDZri + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + imm:$src2)), sub_ymm)>; +} + +//===-------------------------------------------------------------------===// +// 1-src variable permutation VPERMW/D/Q +//===-------------------------------------------------------------------===// + +multiclass avx512_vperm_dq_sizes opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, AVX512VLVectorVTInfo _> { + let Predicates = [HasAVX512] in + defm Z : avx512_var_shift, + avx512_var_shift_mb, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in + defm Z256 : avx512_var_shift, + avx512_var_shift_mb, EVEX_V256; +} + +multiclass avx512_vpermi_dq_sizes opc, Format ImmFormR, Format ImmFormM, + string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, AVX512VLVectorVTInfo VTInfo> { + let Predicates = [HasAVX512] in + defm Z: avx512_shift_rmi, + avx512_shift_rmbi, EVEX_V512; + let Predicates = [HasAVX512, HasVLX] in + defm Z256: avx512_shift_rmi, + avx512_shift_rmbi, EVEX_V256; +} + +multiclass avx512_vperm_bw opc, string OpcodeStr, + Predicate prd, SDNode OpNode, + X86FoldableSchedWrite sched, AVX512VLVectorVTInfo _> { + let Predicates = [prd] in + defm Z: avx512_var_shift, + EVEX_V512 ; + let Predicates = [HasVLX, prd] in { + defm Z256: avx512_var_shift, + EVEX_V256 ; + defm Z128: avx512_var_shift, + EVEX_V128 ; + } +} + +defm VPERMW : avx512_vperm_bw<0x8D, "vpermw", HasBWI, X86VPermv, + WriteVarShuffle256, avx512vl_i16_info>, VEX_W; +defm VPERMB : avx512_vperm_bw<0x8D, "vpermb", HasVBMI, X86VPermv, + WriteVarShuffle256, avx512vl_i8_info>; + +defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv, + WriteVarShuffle256, avx512vl_i32_info>; +defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv, + WriteVarShuffle256, avx512vl_i64_info>, VEX_W; +defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv, + WriteFVarShuffle256, avx512vl_f32_info>; +defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv, + WriteFVarShuffle256, avx512vl_f64_info>, VEX_W; + +defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq", + X86VPermi, WriteShuffle256, avx512vl_i64_info>, + EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W; +defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd", + X86VPermi, WriteFShuffle256, avx512vl_f64_info>, + EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W; + +//===----------------------------------------------------------------------===// +// AVX-512 - VPERMIL +//===----------------------------------------------------------------------===// + +multiclass avx512_permil_vec OpcVar, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + X86VectorVTInfo Ctrl> { + defm rr: AVX512_maskable, + T8PD, EVEX_4V, Sched<[sched]>; + defm rm: AVX512_maskable, + T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + defm rmb: AVX512_maskable, + T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_permil_vec_common OpcVar, + X86SchedWriteWidths sched, + AVX512VLVectorVTInfo _, + AVX512VLVectorVTInfo Ctrl> { + let Predicates = [HasAVX512] in { + defm Z : avx512_permil_vec, EVEX_V512; + } + let Predicates = [HasAVX512, HasVLX] in { + defm Z128 : avx512_permil_vec, EVEX_V128; + defm Z256 : avx512_permil_vec, EVEX_V256; + } +} + +multiclass avx512_permil OpcImm, bits<8> OpcVar, + AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{ + defm NAME: avx512_permil_vec_common; + defm NAME: avx512_shift_rmi_sizes, + EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>; +} + +let ExeDomain = SSEPackedSingle in +defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info, + avx512vl_i32_info>; +let ExeDomain = SSEPackedDouble in +defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info, + avx512vl_i64_info>, VEX_W1X; + +//===----------------------------------------------------------------------===// +// AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW +//===----------------------------------------------------------------------===// + +defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd", + X86PShufd, SchedWriteShuffle, avx512vl_i32_info>, + EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>; +defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw", + X86PShufhw, SchedWriteShuffle>, + EVEX, AVX512XSIi8Base; +defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw", + X86PShuflw, SchedWriteShuffle>, + EVEX, AVX512XDIi8Base; + +//===----------------------------------------------------------------------===// +// AVX-512 - VPSHUFB +//===----------------------------------------------------------------------===// + +multiclass avx512_pshufb_sizes opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + let Predicates = [HasBWI] in + defm Z: avx512_var_shift, + EVEX_V512; + + let Predicates = [HasVLX, HasBWI] in { + defm Z256: avx512_var_shift, + EVEX_V256; + defm Z128: avx512_var_shift, + EVEX_V128; + } +} + +defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb, + SchedWriteVarShuffle>, VEX_WIG; + +//===----------------------------------------------------------------------===// +// Move Low to High and High to Low packed FP Instructions +//===----------------------------------------------------------------------===// + +def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst), + (ins VR128X:$src1, VR128X:$src2), + "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))]>, + Sched<[SchedWriteFShuffle.XMM]>, EVEX_4V; +let isCommutable = 1 in +def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst), + (ins VR128X:$src1, VR128X:$src2), + "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))]>, + Sched<[SchedWriteFShuffle.XMM]>, EVEX_4V, NotMemoryFoldable; + +//===----------------------------------------------------------------------===// +// VMOVHPS/PD VMOVLPS Instructions +// All patterns was taken from SSS implementation. +//===----------------------------------------------------------------------===// + +multiclass avx512_mov_hilo_packed opc, string OpcodeStr, + SDPatternOperator OpNode, + X86VectorVTInfo _> { + let hasSideEffects = 0, mayLoad = 1, ExeDomain = _.ExeDomain in + def rm : AVX512, + Sched<[SchedWriteFShuffle.XMM.Folded, ReadAfterLd]>, EVEX_4V; +} + +// No patterns for MOVLPS/MOVHPS as the Movlhps node should only be created in +// SSE1. And MOVLPS pattern is even more complex. +defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", null_frag, + v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS; +defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Unpckl, + v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W; +defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", null_frag, + v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS; +defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movsd, + v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W; + +let Predicates = [HasAVX512] in { + // VMOVHPD patterns + def : Pat<(v2f64 (X86Unpckl VR128X:$src1, + (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))), + (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>; +} + +let SchedRW = [WriteFStore] in { +def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs), + (ins f64mem:$dst, VR128X:$src), + "vmovhps\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt + (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)), + (bc_v2f64 (v4f32 VR128X:$src))), + (iPTR 0))), addr:$dst)]>, + EVEX, EVEX_CD8<32, CD8VT2>; +def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs), + (ins f64mem:$dst, VR128X:$src), + "vmovhpd\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt + (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)), + (iPTR 0))), addr:$dst)]>, + EVEX, EVEX_CD8<64, CD8VT1>, VEX_W; +def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs), + (ins f64mem:$dst, VR128X:$src), + "vmovlps\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt (bc_v2f64 (v4f32 VR128X:$src)), + (iPTR 0))), addr:$dst)]>, + EVEX, EVEX_CD8<32, CD8VT2>; +def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs), + (ins f64mem:$dst, VR128X:$src), + "vmovlpd\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt (v2f64 VR128X:$src), + (iPTR 0))), addr:$dst)]>, + EVEX, EVEX_CD8<64, CD8VT1>, VEX_W; +} // SchedRW + +let Predicates = [HasAVX512] in { + // VMOVHPD patterns + def : Pat<(store (f64 (extractelt + (v2f64 (X86VPermilpi VR128X:$src, (i8 1))), + (iPTR 0))), addr:$dst), + (VMOVHPDZ128mr addr:$dst, VR128X:$src)>; +} +//===----------------------------------------------------------------------===// +// FMA - Fused Multiply Operations +// + +multiclass avx512_fma3p_213_rm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Suff> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in { + defm r: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched]>; + + defm m: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched.Folded, ReadAfterLd]>; + + defm mb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fma3_213_round opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Suff> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in + defm rb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +multiclass avx512_fma3p_213_common opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo _, string Suff> { + let Predicates = [HasAVX512] in { + defm Z : avx512_fma3p_213_rm, + avx512_fma3_213_round, + EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>; + } + let Predicates = [HasVLX, HasAVX512] in { + defm Z256 : avx512_fma3p_213_rm, + EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>; + defm Z128 : avx512_fma3p_213_rm, + EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>; + } +} + +multiclass avx512_fma3p_213_f opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd> { + defm PS : avx512_fma3p_213_common; + defm PD : avx512_fma3p_213_common, + VEX_W; +} + +defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>; +defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>; +defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>; +defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>; +defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>; +defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>; + + +multiclass avx512_fma3p_231_rm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Suff> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in { + defm r: AVX512_maskable_3src, AVX512FMA3Base, Sched<[sched]>; + + defm m: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched.Folded, ReadAfterLd]>; + + defm mb: AVX512_maskable_3src, AVX512FMA3Base, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fma3_231_round opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Suff> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in + defm rb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +multiclass avx512_fma3p_231_common opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo _, string Suff> { + let Predicates = [HasAVX512] in { + defm Z : avx512_fma3p_231_rm, + avx512_fma3_231_round, + EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>; + } + let Predicates = [HasVLX, HasAVX512] in { + defm Z256 : avx512_fma3p_231_rm, + EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>; + defm Z128 : avx512_fma3p_231_rm, + EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>; + } +} + +multiclass avx512_fma3p_231_f opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd > { + defm PS : avx512_fma3p_231_common; + defm PD : avx512_fma3p_231_common, + VEX_W; +} + +defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>; +defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>; +defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>; +defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>; +defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>; +defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>; + +multiclass avx512_fma3p_132_rm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Suff> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in { + defm r: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched]>; + + // Pattern is 312 order so that the load is in a different place from the + // 213 and 231 patterns this helps tablegen's duplicate pattern detection. + defm m: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched.Folded, ReadAfterLd]>; + + // Pattern is 312 order so that the load is in a different place from the + // 213 and 231 patterns this helps tablegen's duplicate pattern detection. + defm mb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fma3_132_round opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Suff> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in + defm rb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +multiclass avx512_fma3p_132_common opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo _, string Suff> { + let Predicates = [HasAVX512] in { + defm Z : avx512_fma3p_132_rm, + avx512_fma3_132_round, + EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>; + } + let Predicates = [HasVLX, HasAVX512] in { + defm Z256 : avx512_fma3p_132_rm, + EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>; + defm Z128 : avx512_fma3p_132_rm, + EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>; + } +} + +multiclass avx512_fma3p_132_f opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd > { + defm PS : avx512_fma3p_132_common; + defm PD : avx512_fma3p_132_common, + VEX_W; +} + +defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>; +defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>; +defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>; +defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>; +defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>; +defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>; + +// Scalar FMA +multiclass avx512_fma3s_common opc, string OpcodeStr, X86VectorVTInfo _, + dag RHS_r, dag RHS_m, dag RHS_b, bit MaskOnlyReg> { +let Constraints = "$src1 = $dst", hasSideEffects = 0 in { + defm r_Int: AVX512_maskable_3src_scalar, + AVX512FMA3Base, Sched<[SchedWriteFMA.Scl]>; + + let mayLoad = 1 in + defm m_Int: AVX512_maskable_3src_scalar, + AVX512FMA3Base, Sched<[SchedWriteFMA.Scl.Folded, ReadAfterLd]>; + + defm rb_Int: AVX512_maskable_3src_scalar, + AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[SchedWriteFMA.Scl]>; + + let isCodeGenOnly = 1, isCommutable = 1 in { + def r : AVX512FMA3S, Sched<[SchedWriteFMA.Scl]>; + def m : AVX512FMA3S, Sched<[SchedWriteFMA.Scl.Folded, ReadAfterLd]>; + + def rb : AVX512FMA3S, EVEX_B, EVEX_RC, + Sched<[SchedWriteFMA.Scl]>; + }// isCodeGenOnly = 1 +}// Constraints = "$src1 = $dst" +} + +multiclass avx512_fma3s_all opc213, bits<8> opc231, bits<8> opc132, + string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, + X86VectorVTInfo _, string SUFF> { + let ExeDomain = _.ExeDomain in { + defm NAME#213#SUFF#Z: avx512_fma3s_common; + + defm NAME#231#SUFF#Z: avx512_fma3s_common; + + // One pattern is 312 order so that the load is in a different place from the + // 213 and 231 patterns this helps tablegen's duplicate pattern detection. + defm NAME#132#SUFF#Z: avx512_fma3s_common; + } +} + +multiclass avx512_fma3s opc213, bits<8> opc231, bits<8> opc132, + string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd> { + let Predicates = [HasAVX512] in { + defm NAME : avx512_fma3s_all, + EVEX_CD8<32, CD8VT1>, VEX_LIG; + defm NAME : avx512_fma3s_all, + EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W; + } +} + +defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>; +defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>; +defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>; +defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>; + +multiclass avx512_scalar_fma_patterns { + let Predicates = [HasAVX512] in { + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (Op _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src3))))), + (!cast(Prefix#"213"#Suffix#"Zr_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)))>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (Op _.FRC:$src2, _.FRC:$src3, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"Zr_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)))>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (Op _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (_.ScalarLdFrag addr:$src3)))))), + (!cast(Prefix#"213"#Suffix#"Zm_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (Op (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (_.ScalarLdFrag addr:$src3), _.FRC:$src2))))), + (!cast(Prefix#"132"#Suffix#"Zm_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (Op _.FRC:$src2, (_.ScalarLdFrag addr:$src3), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"Zm_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src3), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"213"#Suffix#"Zr_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)))>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (_.ScalarLdFrag addr:$src3)), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"213"#Suffix#"Zm_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (_.ScalarLdFrag addr:$src3), _.FRC:$src2), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"132"#Suffix#"Zm_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, _.FRC:$src3, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"Zr_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)))>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, (_.ScalarLdFrag addr:$src3), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"Zm_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src3), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"213"#Suffix#"Zr_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)))>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, _.FRC:$src3, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"231"#Suffix#"Zr_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)))>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (_.ScalarLdFrag addr:$src3)), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"213"#Suffix#"Zm_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src2, (_.ScalarLdFrag addr:$src3)), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"132"#Suffix#"Zm_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, (_.ScalarLdFrag addr:$src3), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"231"#Suffix#"Zm_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), addr:$src3)>; + + // Patterns with rounding mode. + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (RndOp _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src3, (i32 imm:$rc)))))), + (!cast(Prefix#"213"#Suffix#"Zrb_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), imm:$rc)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (RndOp _.FRC:$src2, _.FRC:$src3, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (i32 imm:$rc)))))), + (!cast(Prefix#"231"#Suffix#"Zrb_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), imm:$rc)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (RndOp _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src3, (i32 imm:$rc)), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"213"#Suffix#"Zrb_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), imm:$rc)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (RndOp _.FRC:$src2, _.FRC:$src3, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (i32 imm:$rc)), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"Zrb_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), imm:$rc)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (RndOp _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src3, (i32 imm:$rc)), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"213"#Suffix#"Zrb_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), imm:$rc)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (RndOp _.FRC:$src2, _.FRC:$src3, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (i32 imm:$rc)), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"231"#Suffix#"Zrb_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), imm:$rc)>; + } +} + +defm : avx512_scalar_fma_patterns; +defm : avx512_scalar_fma_patterns; +defm : avx512_scalar_fma_patterns; +defm : avx512_scalar_fma_patterns; + +defm : avx512_scalar_fma_patterns; +defm : avx512_scalar_fma_patterns; +defm : avx512_scalar_fma_patterns; +defm : avx512_scalar_fma_patterns; + +//===----------------------------------------------------------------------===// +// AVX-512 Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit IFMA +//===----------------------------------------------------------------------===// +let Constraints = "$src1 = $dst" in { +multiclass avx512_pmadd52_rm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + // NOTE: The SDNode have the multiply operands first with the add last. + // This enables commuted load patterns to be autogenerated by tablegen. + let ExeDomain = _.ExeDomain in { + defm r: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched]>; + + defm m: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched.Folded, ReadAfterLd]>; + + defm mb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } +} +} // Constraints = "$src1 = $dst" + +multiclass avx512_pmadd52_common opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo _> { + let Predicates = [HasIFMA] in { + defm Z : avx512_pmadd52_rm, + EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>; + } + let Predicates = [HasVLX, HasIFMA] in { + defm Z256 : avx512_pmadd52_rm, + EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>; + defm Z128 : avx512_pmadd52_rm, + EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>; + } +} + +defm VPMADD52LUQ : avx512_pmadd52_common<0xb4, "vpmadd52luq", x86vpmadd52l, + SchedWriteVecIMul, avx512vl_i64_info>, + VEX_W; +defm VPMADD52HUQ : avx512_pmadd52_common<0xb5, "vpmadd52huq", x86vpmadd52h, + SchedWriteVecIMul, avx512vl_i64_info>, + VEX_W; + +//===----------------------------------------------------------------------===// +// AVX-512 Scalar convert from sign integer to float/double +//===----------------------------------------------------------------------===// + +multiclass avx512_vcvtsi opc, SDNode OpNode, X86FoldableSchedWrite sched, + RegisterClass SrcRC, X86VectorVTInfo DstVT, + X86MemOperand x86memop, PatFrag ld_frag, string asm> { + let hasSideEffects = 0 in { + def rr : SI, + EVEX_4V, Sched<[sched]>; + let mayLoad = 1 in + def rm : SI, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + } // hasSideEffects = 0 + let isCodeGenOnly = 1 in { + def rr_Int : SI, + EVEX_4V, Sched<[sched]>; + + def rm_Int : SI, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + }//isCodeGenOnly = 1 +} + +multiclass avx512_vcvtsi_round opc, SDNode OpNode, + X86FoldableSchedWrite sched, RegisterClass SrcRC, + X86VectorVTInfo DstVT, string asm> { + def rrb_Int : SI, + EVEX_4V, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +multiclass avx512_vcvtsi_common opc, SDNode OpNode, + X86FoldableSchedWrite sched, + RegisterClass SrcRC, X86VectorVTInfo DstVT, + X86MemOperand x86memop, PatFrag ld_frag, string asm> { + defm NAME : avx512_vcvtsi_round, + avx512_vcvtsi, VEX_LIG; +} + +let Predicates = [HasAVX512] in { +defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, WriteCvtI2SS, GR32, + v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">, + XS, EVEX_CD8<32, CD8VT1>; +defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, WriteCvtI2SS, GR64, + v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">, + XS, VEX_W, EVEX_CD8<64, CD8VT1>; +defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, WriteCvtI2SD, GR32, + v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">, + XD, EVEX_CD8<32, CD8VT1>; +defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, WriteCvtI2SD, GR64, + v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">, + XD, VEX_W, EVEX_CD8<64, CD8VT1>; + +// def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}", +// (VCVTSI2SSZrm FR64X:$dst, FR64X:$src1, i32mem:$src), 0, "att">; +// def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}", +// (VCVTSI2SDZrm FR64X:$dst, FR64X:$src1, i32mem:$src), 0, "att">; + +def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))), + (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; +def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))), + (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; +def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))), + (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; +def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))), + (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; + +def : Pat<(f32 (sint_to_fp GR32:$src)), + (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>; +def : Pat<(f32 (sint_to_fp GR64:$src)), + (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>; +def : Pat<(f64 (sint_to_fp GR32:$src)), + (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>; +def : Pat<(f64 (sint_to_fp GR64:$src)), + (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>; + +defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, WriteCvtI2SS, GR32, + v4f32x_info, i32mem, loadi32, + "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>; +defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, WriteCvtI2SS, GR64, + v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">, + XS, VEX_W, EVEX_CD8<64, CD8VT1>; +defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, WriteCvtI2SD, GR32, v2f64x_info, + i32mem, loadi32, "cvtusi2sd{l}">, + XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; +defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, WriteCvtI2SD, GR64, + v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">, + XD, VEX_W, EVEX_CD8<64, CD8VT1>; + +// def : InstAlias<"vcvtusi2ss\t{$src, $src1, $dst|$dst, $src1, $src}", +// (VCVTUSI2SSZrm FR64X:$dst, FR64X:$src1, i32mem:$src), 0, "att">; +// def : InstAlias<"vcvtusi2sd\t{$src, $src1, $dst|$dst, $src1, $src}", +// (VCVTUSI2SDZrm FR64X:$dst, FR64X:$src1, i32mem:$src), 0, "att">; + +def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))), + (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; +def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))), + (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; +def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))), + (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; +def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))), + (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; + +def : Pat<(f32 (uint_to_fp GR32:$src)), + (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>; +def : Pat<(f32 (uint_to_fp GR64:$src)), + (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>; +def : Pat<(f64 (uint_to_fp GR32:$src)), + (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>; +def : Pat<(f64 (uint_to_fp GR64:$src)), + (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 Scalar convert from float/double to integer +//===----------------------------------------------------------------------===// + +multiclass avx512_cvt_s_int_round opc, X86VectorVTInfo SrcVT, + X86VectorVTInfo DstVT, SDNode OpNode, + X86FoldableSchedWrite sched, string asm, + string aliasStr, + bit CodeGenOnly = 1> { + let Predicates = [HasAVX512] in { + def rr_Int : SI, + EVEX, VEX_LIG, Sched<[sched]>; + def rrb_Int : SI, + EVEX, VEX_LIG, EVEX_B, EVEX_RC, + Sched<[sched]>; + let isCodeGenOnly = CodeGenOnly, ForceDisassemble = CodeGenOnly in + def rm_Int : SI, + EVEX, VEX_LIG, Sched<[sched.Folded, ReadAfterLd]>; + + // def : InstAlias<"v" # asm # aliasStr # "\t{$src, $dst|$dst, $src}", + // (!cast(NAME # "rr_Int") DstVT.RC:$dst, SrcVT.RC:$src), 0, "att">; + // def : InstAlias<"v" # asm # aliasStr # "\t{$rc, $src, $dst|$dst, $src, $rc}", + // (!cast(NAME # "rrb_Int") DstVT.RC:$dst, SrcVT.RC:$src, AVX512RC:$rc), 0, "att">; + } // Predicates = [HasAVX512] +} + +multiclass avx512_cvt_s_int_round_aliases opc, X86VectorVTInfo SrcVT, + X86VectorVTInfo DstVT, SDNode OpNode, + X86FoldableSchedWrite sched, string asm, + string aliasStr> : + avx512_cvt_s_int_round { + let Predicates = [HasAVX512] in { + // def : InstAlias<"v" # asm # aliasStr # "\t{$src, $dst|$dst, $src}", + // (!cast(NAME # "rm_Int") DstVT.RC:$dst, + // SrcVT.IntScalarMemOp:$src), 0, "att">; + } // Predicates = [HasAVX512] +} + +// Convert float/double to signed/unsigned int 32/64 +defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, f32x_info, i32x_info, + X86cvts2si, WriteCvtSS2I, "cvtss2si", "{l}">, + XS, EVEX_CD8<32, CD8VT1>; +defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info, + X86cvts2si, WriteCvtSS2I, "cvtss2si", "{q}">, + XS, VEX_W, EVEX_CD8<32, CD8VT1>; +defm VCVTSS2USIZ: avx512_cvt_s_int_round_aliases<0x79, f32x_info, i32x_info, + X86cvts2usi, WriteCvtSS2I, "cvtss2usi", "{l}">, + XS, EVEX_CD8<32, CD8VT1>; +defm VCVTSS2USI64Z: avx512_cvt_s_int_round_aliases<0x79, f32x_info, i64x_info, + X86cvts2usi, WriteCvtSS2I, "cvtss2usi", "{q}">, + XS, VEX_W, EVEX_CD8<32, CD8VT1>; +defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info, + X86cvts2si, WriteCvtSD2I, "cvtsd2si", "{l}">, + XD, EVEX_CD8<64, CD8VT1>; +defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, f64x_info, i64x_info, + X86cvts2si, WriteCvtSD2I, "cvtsd2si", "{q}">, + XD, VEX_W, EVEX_CD8<64, CD8VT1>; +defm VCVTSD2USIZ: avx512_cvt_s_int_round_aliases<0x79, f64x_info, i32x_info, + X86cvts2usi, WriteCvtSD2I, "cvtsd2usi", "{l}">, + XD, EVEX_CD8<64, CD8VT1>; +defm VCVTSD2USI64Z: avx512_cvt_s_int_round_aliases<0x79, f64x_info, i64x_info, + X86cvts2usi, WriteCvtSD2I, "cvtsd2usi", "{q}">, + XD, VEX_W, EVEX_CD8<64, CD8VT1>; + +// The SSE version of these instructions are disabled for AVX512. +// Therefore, the SSE intrinsics are mapped to the AVX512 instructions. +let Predicates = [HasAVX512] in { + def : Pat<(i32 (int_x86_sse_cvtss2si (v4f32 VR128X:$src))), + (VCVTSS2SIZrr_Int VR128X:$src)>; + def : Pat<(i32 (int_x86_sse_cvtss2si sse_load_f32:$src)), + (VCVTSS2SIZrm_Int sse_load_f32:$src)>; + def : Pat<(i64 (int_x86_sse_cvtss2si64 (v4f32 VR128X:$src))), + (VCVTSS2SI64Zrr_Int VR128X:$src)>; + def : Pat<(i64 (int_x86_sse_cvtss2si64 sse_load_f32:$src)), + (VCVTSS2SI64Zrm_Int sse_load_f32:$src)>; + def : Pat<(i32 (int_x86_sse2_cvtsd2si (v2f64 VR128X:$src))), + (VCVTSD2SIZrr_Int VR128X:$src)>; + def : Pat<(i32 (int_x86_sse2_cvtsd2si sse_load_f64:$src)), + (VCVTSD2SIZrm_Int sse_load_f64:$src)>; + def : Pat<(i64 (int_x86_sse2_cvtsd2si64 (v2f64 VR128X:$src))), + (VCVTSD2SI64Zrr_Int VR128X:$src)>; + def : Pat<(i64 (int_x86_sse2_cvtsd2si64 sse_load_f64:$src)), + (VCVTSD2SI64Zrm_Int sse_load_f64:$src)>; +} // HasAVX512 + +// Patterns used for matching vcvtsi2s{s,d} intrinsic sequences from clang +// which produce unnecessary vmovs{s,d} instructions +let Predicates = [HasAVX512] in { +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp GR64:$src)))))), + (VCVTSI642SSZrr_Int VR128X:$dst, GR64:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi64 addr:$src))))))), + (VCVTSI642SSZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp GR32:$src)))))), + (VCVTSI2SSZrr_Int VR128X:$dst, GR32:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi32 addr:$src))))))), + (VCVTSI2SSZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp GR64:$src)))))), + (VCVTSI642SDZrr_Int VR128X:$dst, GR64:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi64 addr:$src))))))), + (VCVTSI642SDZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp GR32:$src)))))), + (VCVTSI2SDZrr_Int VR128X:$dst, GR32:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi32 addr:$src))))))), + (VCVTSI2SDZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (uint_to_fp GR64:$src)))))), + (VCVTUSI642SSZrr_Int VR128X:$dst, GR64:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (uint_to_fp (loadi64 addr:$src))))))), + (VCVTUSI642SSZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (uint_to_fp GR32:$src)))))), + (VCVTUSI2SSZrr_Int VR128X:$dst, GR32:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (uint_to_fp (loadi32 addr:$src))))))), + (VCVTUSI2SSZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (uint_to_fp GR64:$src)))))), + (VCVTUSI642SDZrr_Int VR128X:$dst, GR64:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (uint_to_fp (loadi64 addr:$src))))))), + (VCVTUSI642SDZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (uint_to_fp GR32:$src)))))), + (VCVTUSI2SDZrr_Int VR128X:$dst, GR32:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (uint_to_fp (loadi32 addr:$src))))))), + (VCVTUSI2SDZrm_Int VR128X:$dst, addr:$src)>; +} // Predicates = [HasAVX512] + +// Convert float/double to signed/unsigned int 32/64 with truncation +multiclass avx512_cvt_s_all opc, string asm, X86VectorVTInfo _SrcRC, + X86VectorVTInfo _DstRC, SDNode OpNode, + SDNode OpNodeRnd, X86FoldableSchedWrite sched, + string aliasStr, bit CodeGenOnly = 1>{ +let Predicates = [HasAVX512] in { + let isCodeGenOnly = 1 in { + def rr : AVX512, + EVEX, Sched<[sched]>; + def rm : AVX512, + EVEX, Sched<[sched.Folded, ReadAfterLd]>; + } + + def rr_Int : AVX512, + EVEX, VEX_LIG, Sched<[sched]>; + def rrb_Int : AVX512, + EVEX,VEX_LIG , EVEX_B, Sched<[sched]>; + let isCodeGenOnly = CodeGenOnly, ForceDisassemble = CodeGenOnly in + def rm_Int : AVX512, + EVEX, VEX_LIG, Sched<[sched.Folded, ReadAfterLd]>; + + // def : InstAlias(NAME # "rr_Int") _DstRC.RC:$dst, _SrcRC.RC:$src), 0, "att">; + // def : InstAlias(NAME # "rrb_Int") _DstRC.RC:$dst, _SrcRC.RC:$src), 0, "att">; +} //HasAVX512 +} + +multiclass avx512_cvt_s_all_unsigned opc, string asm, + X86VectorVTInfo _SrcRC, + X86VectorVTInfo _DstRC, SDNode OpNode, + SDNode OpNodeRnd, X86FoldableSchedWrite sched, + string aliasStr> : + avx512_cvt_s_all { +let Predicates = [HasAVX512] in { + // def : InstAlias(NAME # "rm_Int") _DstRC.RC:$dst, + // _SrcRC.IntScalarMemOp:$src), 0, "att">; +} +} + +defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "vcvttss2si", f32x_info, i32x_info, + fp_to_sint, X86cvtts2IntRnd, WriteCvtSS2I, "{l}">, + XS, EVEX_CD8<32, CD8VT1>; +defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "vcvttss2si", f32x_info, i64x_info, + fp_to_sint, X86cvtts2IntRnd, WriteCvtSS2I, "{q}">, + VEX_W, XS, EVEX_CD8<32, CD8VT1>; +defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "vcvttsd2si", f64x_info, i32x_info, + fp_to_sint, X86cvtts2IntRnd, WriteCvtSD2I, "{l}">, + XD, EVEX_CD8<64, CD8VT1>; +defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "vcvttsd2si", f64x_info, i64x_info, + fp_to_sint, X86cvtts2IntRnd, WriteCvtSD2I, "{q}">, + VEX_W, XD, EVEX_CD8<64, CD8VT1>; + +defm VCVTTSS2USIZ: avx512_cvt_s_all_unsigned<0x78, "vcvttss2usi", f32x_info, i32x_info, + fp_to_uint, X86cvtts2UIntRnd, WriteCvtSS2I, "{l}">, + XS, EVEX_CD8<32, CD8VT1>; +defm VCVTTSS2USI64Z: avx512_cvt_s_all_unsigned<0x78, "vcvttss2usi", f32x_info, i64x_info, + fp_to_uint, X86cvtts2UIntRnd, WriteCvtSS2I, "{q}">, + XS,VEX_W, EVEX_CD8<32, CD8VT1>; +defm VCVTTSD2USIZ: avx512_cvt_s_all_unsigned<0x78, "vcvttsd2usi", f64x_info, i32x_info, + fp_to_uint, X86cvtts2UIntRnd, WriteCvtSD2I, "{l}">, + XD, EVEX_CD8<64, CD8VT1>; +defm VCVTTSD2USI64Z: avx512_cvt_s_all_unsigned<0x78, "vcvttsd2usi", f64x_info, i64x_info, + fp_to_uint, X86cvtts2UIntRnd, WriteCvtSD2I, "{q}">, + XD, VEX_W, EVEX_CD8<64, CD8VT1>; + +let Predicates = [HasAVX512] in { + def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))), + (VCVTTSS2SIZrr_Int VR128X:$src)>; + def : Pat<(i32 (int_x86_sse_cvttss2si sse_load_f32:$src)), + (VCVTTSS2SIZrm_Int ssmem:$src)>; + def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))), + (VCVTTSS2SI64Zrr_Int VR128X:$src)>; + def : Pat<(i64 (int_x86_sse_cvttss2si64 sse_load_f32:$src)), + (VCVTTSS2SI64Zrm_Int ssmem:$src)>; + def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))), + (VCVTTSD2SIZrr_Int VR128X:$src)>; + def : Pat<(i32 (int_x86_sse2_cvttsd2si sse_load_f64:$src)), + (VCVTTSD2SIZrm_Int sdmem:$src)>; + def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))), + (VCVTTSD2SI64Zrr_Int VR128X:$src)>; + def : Pat<(i64 (int_x86_sse2_cvttsd2si64 sse_load_f64:$src)), + (VCVTTSD2SI64Zrm_Int sdmem:$src)>; +} // HasAVX512 + +//===----------------------------------------------------------------------===// +// AVX-512 Convert form float to double and back +//===----------------------------------------------------------------------===// + +multiclass avx512_cvt_fp_scalar opc, string OpcodeStr, X86VectorVTInfo _, + X86VectorVTInfo _Src, SDNode OpNode, + X86FoldableSchedWrite sched> { + defm rr_Int : AVX512_maskable_scalar, + EVEX_4V, VEX_LIG, Sched<[sched]>; + defm rm_Int : AVX512_maskable_scalar, + EVEX_4V, VEX_LIG, + Sched<[sched.Folded, ReadAfterLd]>; + + let isCodeGenOnly = 1, hasSideEffects = 0 in { + def rr : I, + EVEX_4V, VEX_LIG, Sched<[sched]>; + let mayLoad = 1 in + def rm : I, + EVEX_4V, VEX_LIG, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +// Scalar Conversion with SAE - suppress all exceptions +multiclass avx512_cvt_fp_sae_scalar opc, string OpcodeStr, X86VectorVTInfo _, + X86VectorVTInfo _Src, SDNode OpNodeRnd, + X86FoldableSchedWrite sched> { + defm rrb_Int : AVX512_maskable_scalar, + EVEX_4V, VEX_LIG, EVEX_B, Sched<[sched]>; +} + +// Scalar Conversion with rounding control (RC) +multiclass avx512_cvt_fp_rc_scalar opc, string OpcodeStr, X86VectorVTInfo _, + X86VectorVTInfo _Src, SDNode OpNodeRnd, + X86FoldableSchedWrite sched> { + defm rrb_Int : AVX512_maskable_scalar, + EVEX_4V, VEX_LIG, Sched<[sched]>, + EVEX_B, EVEX_RC; +} +multiclass avx512_cvt_fp_scalar_sd2ss opc, string OpcodeStr, + SDNode OpNodeRnd, X86FoldableSchedWrite sched, + X86VectorVTInfo _src, X86VectorVTInfo _dst> { + let Predicates = [HasAVX512] in { + defm Z : avx512_cvt_fp_scalar, + avx512_cvt_fp_rc_scalar, VEX_W, EVEX_CD8<64, CD8VT1>, XD; + } +} + +multiclass avx512_cvt_fp_scalar_ss2sd opc, string OpcodeStr, SDNode OpNodeRnd, + X86FoldableSchedWrite sched, + X86VectorVTInfo _src, X86VectorVTInfo _dst> { + let Predicates = [HasAVX512] in { + defm Z : avx512_cvt_fp_scalar, + avx512_cvt_fp_sae_scalar, + EVEX_CD8<32, CD8VT1>, XS; + } +} +defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", + X86froundRnd, WriteCvtSD2SS, f64x_info, + f32x_info>; +defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", + X86fpextRnd, WriteCvtSS2SD, f32x_info, + f64x_info>; + +def : Pat<(f64 (fpextend FR32X:$src)), + (VCVTSS2SDZrr (f64 (IMPLICIT_DEF)), FR32X:$src)>, + Requires<[HasAVX512]>; +def : Pat<(f64 (fpextend (loadf32 addr:$src))), + (VCVTSS2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>, + Requires<[HasAVX512, OptForSize]>; + +def : Pat<(f64 (extloadf32 addr:$src)), + (VCVTSS2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>, + Requires<[HasAVX512, OptForSize]>; + +def : Pat<(f64 (extloadf32 addr:$src)), + (VCVTSS2SDZrr (f64 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>, + Requires<[HasAVX512, OptForSpeed]>; + +def : Pat<(f32 (fpround FR64X:$src)), + (VCVTSD2SSZrr (f32 (IMPLICIT_DEF)), FR64X:$src)>, + Requires<[HasAVX512]>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector + (f32 (fpround (f64 (extractelt VR128X:$src, (iPTR 0))))))))), + (VCVTSD2SSZrr_Int VR128X:$dst, VR128X:$src)>, + Requires<[HasAVX512]>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector + (f64 (fpextend (f32 (extractelt VR128X:$src, (iPTR 0))))))))), + (VCVTSS2SDZrr_Int VR128X:$dst, VR128X:$src)>, + Requires<[HasAVX512]>; + +//===----------------------------------------------------------------------===// +// AVX-512 Vector convert from signed/unsigned integer to float/double +// and from float/double to signed/unsigned integer +//===----------------------------------------------------------------------===// + +multiclass avx512_vcvt_fp opc, string OpcodeStr, X86VectorVTInfo _, + X86VectorVTInfo _Src, SDNode OpNode, + X86FoldableSchedWrite sched, + string Broadcast = _.BroadcastStr, + string Alias = "", X86MemOperand MemOp = _Src.MemOp> { + + defm rr : AVX512_maskable, + EVEX, Sched<[sched]>; + + defm rm : AVX512_maskable, + EVEX, Sched<[sched.Folded]>; + + defm rmb : AVX512_maskable, EVEX, EVEX_B, + Sched<[sched.Folded]>; +} +// Conversion with SAE - suppress all exceptions +multiclass avx512_vcvt_fp_sae opc, string OpcodeStr, X86VectorVTInfo _, + X86VectorVTInfo _Src, SDNode OpNodeRnd, + X86FoldableSchedWrite sched> { + defm rrb : AVX512_maskable, + EVEX, EVEX_B, Sched<[sched]>; +} + +// Conversion with rounding control (RC) +multiclass avx512_vcvt_fp_rc opc, string OpcodeStr, X86VectorVTInfo _, + X86VectorVTInfo _Src, SDNode OpNodeRnd, + X86FoldableSchedWrite sched> { + defm rrb : AVX512_maskable, + EVEX, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +// Extend Float to Double +multiclass avx512_cvtps2pd opc, string OpcodeStr, + X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_sae, EVEX_V512; + } + let Predicates = [HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Truncate Double to Float +multiclass avx512_cvtpd2ps opc, string OpcodeStr, X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + + // def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; + // def : InstAlias(NAME # "Z128rm") VR128X:$dst, f128mem:$src), 0, "intel">; + // def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; + // def : InstAlias(NAME # "Z256rm") VR128X:$dst, f256mem:$src), 0, "intel">; + } +} + +defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps", SchedWriteCvtPD2PS>, + VEX_W, PD, EVEX_CD8<64, CD8VF>; +defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd", SchedWriteCvtPS2PD>, + PS, EVEX_CD8<32, CD8VH>; + +def : Pat<(v8f64 (extloadv8f32 addr:$src)), + (VCVTPS2PDZrm addr:$src)>; + +let Predicates = [HasVLX] in { + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86vfpround (v2f64 VR128X:$src)))))), + (VCVTPD2PSZ128rr VR128X:$src)>; + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86vfpround (loadv2f64 addr:$src)))))), + (VCVTPD2PSZ128rm addr:$src)>; + def : Pat<(v2f64 (extloadv2f32 addr:$src)), + (VCVTPS2PDZ128rm addr:$src)>; + def : Pat<(v4f64 (extloadv4f32 addr:$src)), + (VCVTPS2PDZ256rm addr:$src)>; +} + +// Convert Signed/Unsigned Doubleword to Double +multiclass avx512_cvtdq2pd opc, string OpcodeStr, SDNode OpNode, + SDNode OpNode128, X86SchedWriteWidths sched> { + // No rounding in this op + let Predicates = [HasAVX512] in + defm Z : avx512_vcvt_fp, EVEX_V512; + + let Predicates = [HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Signed/Unsigned Doubleword to Float +multiclass avx512_cvtdq2ps opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + + let Predicates = [HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Float to Signed/Unsigned Doubleword with truncation +multiclass avx512_cvttps2dq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_sae, EVEX_V512; + } + let Predicates = [HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Float to Signed/Unsigned Doubleword +multiclass avx512_cvtps2dq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Double to Signed/Unsigned Doubleword with truncation +multiclass avx512_cvttpd2dq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_sae, EVEX_V512; + } + let Predicates = [HasVLX] in { + // we need "x"/"y" suffixes in order to distinguish between 128 and 256 + // memory forms of these instructions in Asm Parser. They have the same + // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly + // due to the same reason. + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + + // def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; + // def : InstAlias(NAME # "Z128rm") VR128X:$dst, i128mem:$src), 0, "intel">; + // def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; + // def : InstAlias(NAME # "Z256rm") VR128X:$dst, i256mem:$src), 0, "intel">; + } +} + +// Convert Double to Signed/Unsigned Doubleword +multiclass avx512_cvtpd2dq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasVLX] in { + // we need "x"/"y" suffixes in order to distinguish between 128 and 256 + // memory forms of these instructions in Asm Parcer. They have the same + // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly + // due to the same reason. + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + + // def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; + // def : InstAlias(NAME # "Z128rm") VR128X:$dst, f128mem:$src), 0, "intel">; + // def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; + // def : InstAlias(NAME # "Z256rm") VR128X:$dst, f256mem:$src), 0, "intel">; + } +} + +// Convert Double to Signed/Unsigned Quardword +multiclass avx512_cvtpd2qq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasDQI] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasDQI, HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Double to Signed/Unsigned Quardword with truncation +multiclass avx512_cvttpd2qq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasDQI] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_sae, EVEX_V512; + } + let Predicates = [HasDQI, HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Signed/Unsigned Quardword to Double +multiclass avx512_cvtqq2pd opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasDQI] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasDQI, HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128, NotEVEX2VEXConvertible; + defm Z256 : avx512_vcvt_fp, EVEX_V256, NotEVEX2VEXConvertible; + } +} + +// Convert Float to Signed/Unsigned Quardword +multiclass avx512_cvtps2qq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasDQI] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasDQI, HasVLX] in { + // Explicitly specified broadcast string, since we take only 2 elements + // from v4f32x_info source + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Float to Signed/Unsigned Quardword with truncation +multiclass avx512_cvttps2qq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasDQI] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_sae, EVEX_V512; + } + let Predicates = [HasDQI, HasVLX] in { + // Explicitly specified broadcast string, since we take only 2 elements + // from v4f32x_info source + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Signed/Unsigned Quardword to Float +multiclass avx512_cvtqq2ps opc, string OpcodeStr, SDNode OpNode, + SDNode OpNode128, SDNode OpNodeRnd, + X86SchedWriteWidths sched> { + let Predicates = [HasDQI] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasDQI, HasVLX] in { + // we need "x"/"y" suffixes in order to distinguish between 128 and 256 + // memory forms of these instructions in Asm Parcer. They have the same + // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly + // due to the same reason. + defm Z128 : avx512_vcvt_fp, EVEX_V128, + NotEVEX2VEXConvertible; + defm Z256 : avx512_vcvt_fp, EVEX_V256, + NotEVEX2VEXConvertible; + + // def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; + // def : InstAlias(NAME # "Z128rm") VR128X:$dst, i128mem:$src), 0, "intel">; + // def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; + // def : InstAlias(NAME # "Z256rm") VR128X:$dst, i256mem:$src), 0, "intel">; + } +} + +defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86VSintToFP, + SchedWriteCvtDQ2PD>, XS, EVEX_CD8<32, CD8VH>; + +defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp, + X86VSintToFpRnd, SchedWriteCvtDQ2PS>, + PS, EVEX_CD8<32, CD8VF>; + +defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", X86cvttp2si, + X86cvttp2siRnd, SchedWriteCvtPS2DQ>, + XS, EVEX_CD8<32, CD8VF>; + +defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", X86cvttp2si, + X86cvttp2siRnd, SchedWriteCvtPD2DQ>, + PD, VEX_W, EVEX_CD8<64, CD8VF>; + +defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", X86cvttp2ui, + X86cvttp2uiRnd, SchedWriteCvtPS2DQ>, PS, + EVEX_CD8<32, CD8VF>; + +defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", X86cvttp2ui, + X86cvttp2uiRnd, SchedWriteCvtPD2DQ>, + PS, VEX_W, EVEX_CD8<64, CD8VF>; + +defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, + X86VUintToFP, SchedWriteCvtDQ2PD>, XS, + EVEX_CD8<32, CD8VH>; + +defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp, + X86VUintToFpRnd, SchedWriteCvtDQ2PS>, XD, + EVEX_CD8<32, CD8VF>; + +defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtp2Int, + X86cvtp2IntRnd, SchedWriteCvtPS2DQ>, PD, + EVEX_CD8<32, CD8VF>; + +defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtp2Int, + X86cvtp2IntRnd, SchedWriteCvtPD2DQ>, XD, + VEX_W, EVEX_CD8<64, CD8VF>; + +defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtp2UInt, + X86cvtp2UIntRnd, SchedWriteCvtPS2DQ>, + PS, EVEX_CD8<32, CD8VF>; + +defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtp2UInt, + X86cvtp2UIntRnd, SchedWriteCvtPD2DQ>, VEX_W, + PS, EVEX_CD8<64, CD8VF>; + +defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtp2Int, + X86cvtp2IntRnd, SchedWriteCvtPD2DQ>, VEX_W, + PD, EVEX_CD8<64, CD8VF>; + +defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtp2Int, + X86cvtp2IntRnd, SchedWriteCvtPS2DQ>, PD, + EVEX_CD8<32, CD8VH>; + +defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtp2UInt, + X86cvtp2UIntRnd, SchedWriteCvtPD2DQ>, VEX_W, + PD, EVEX_CD8<64, CD8VF>; + +defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtp2UInt, + X86cvtp2UIntRnd, SchedWriteCvtPS2DQ>, PD, + EVEX_CD8<32, CD8VH>; + +defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", X86cvttp2si, + X86cvttp2siRnd, SchedWriteCvtPD2DQ>, VEX_W, + PD, EVEX_CD8<64, CD8VF>; + +defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", X86cvttp2si, + X86cvttp2siRnd, SchedWriteCvtPS2DQ>, PD, + EVEX_CD8<32, CD8VH>; + +defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", X86cvttp2ui, + X86cvttp2uiRnd, SchedWriteCvtPD2DQ>, VEX_W, + PD, EVEX_CD8<64, CD8VF>; + +defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", X86cvttp2ui, + X86cvttp2uiRnd, SchedWriteCvtPS2DQ>, PD, + EVEX_CD8<32, CD8VH>; + +defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp, + X86VSintToFpRnd, SchedWriteCvtDQ2PD>, VEX_W, XS, + EVEX_CD8<64, CD8VF>; + +defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp, + X86VUintToFpRnd, SchedWriteCvtDQ2PD>, VEX_W, XS, + EVEX_CD8<64, CD8VF>; + +defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp, X86VSintToFP, + X86VSintToFpRnd, SchedWriteCvtDQ2PS>, VEX_W, PS, + EVEX_CD8<64, CD8VF>; + +defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp, X86VUintToFP, + X86VUintToFpRnd, SchedWriteCvtDQ2PS>, VEX_W, XD, + EVEX_CD8<64, CD8VF>; + +let Predicates = [HasAVX512] in { + def : Pat<(v16i32 (fp_to_sint (v16f32 VR512:$src))), + (VCVTTPS2DQZrr VR512:$src)>; + def : Pat<(v16i32 (fp_to_sint (loadv16f32 addr:$src))), + (VCVTTPS2DQZrm addr:$src)>; + + def : Pat<(v16i32 (fp_to_uint (v16f32 VR512:$src))), + (VCVTTPS2UDQZrr VR512:$src)>; + def : Pat<(v16i32 (fp_to_uint (loadv16f32 addr:$src))), + (VCVTTPS2UDQZrm addr:$src)>; + + def : Pat<(v8i32 (fp_to_sint (v8f64 VR512:$src))), + (VCVTTPD2DQZrr VR512:$src)>; + def : Pat<(v8i32 (fp_to_sint (loadv8f64 addr:$src))), + (VCVTTPD2DQZrm addr:$src)>; + + def : Pat<(v8i32 (fp_to_uint (v8f64 VR512:$src))), + (VCVTTPD2UDQZrr VR512:$src)>; + def : Pat<(v8i32 (fp_to_uint (loadv8f64 addr:$src))), + (VCVTTPD2UDQZrm addr:$src)>; +} + +let Predicates = [HasVLX] in { + def : Pat<(v4i32 (fp_to_sint (v4f32 VR128X:$src))), + (VCVTTPS2DQZ128rr VR128X:$src)>; + def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))), + (VCVTTPS2DQZ128rm addr:$src)>; + + def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src))), + (VCVTTPS2UDQZ128rr VR128X:$src)>; + def : Pat<(v4i32 (fp_to_uint (loadv4f32 addr:$src))), + (VCVTTPS2UDQZ128rm addr:$src)>; + + def : Pat<(v8i32 (fp_to_sint (v8f32 VR256X:$src))), + (VCVTTPS2DQZ256rr VR256X:$src)>; + def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))), + (VCVTTPS2DQZ256rm addr:$src)>; + + def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src))), + (VCVTTPS2UDQZ256rr VR256X:$src)>; + def : Pat<(v8i32 (fp_to_uint (loadv8f32 addr:$src))), + (VCVTTPS2UDQZ256rm addr:$src)>; + + def : Pat<(v4i32 (fp_to_sint (v4f64 VR256X:$src))), + (VCVTTPD2DQZ256rr VR256X:$src)>; + def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))), + (VCVTTPD2DQZ256rm addr:$src)>; + + def : Pat<(v4i32 (fp_to_uint (v4f64 VR256X:$src))), + (VCVTTPD2UDQZ256rr VR256X:$src)>; + def : Pat<(v4i32 (fp_to_uint (loadv4f64 addr:$src))), + (VCVTTPD2UDQZ256rm addr:$src)>; +} + +let Predicates = [HasDQI] in { + def : Pat<(v8i64 (fp_to_sint (v8f32 VR256X:$src))), + (VCVTTPS2QQZrr VR256X:$src)>; + def : Pat<(v8i64 (fp_to_sint (loadv8f32 addr:$src))), + (VCVTTPS2QQZrm addr:$src)>; + + def : Pat<(v8i64 (fp_to_uint (v8f32 VR256X:$src))), + (VCVTTPS2UQQZrr VR256X:$src)>; + def : Pat<(v8i64 (fp_to_uint (loadv8f32 addr:$src))), + (VCVTTPS2UQQZrm addr:$src)>; + + def : Pat<(v8i64 (fp_to_sint (v8f64 VR512:$src))), + (VCVTTPD2QQZrr VR512:$src)>; + def : Pat<(v8i64 (fp_to_sint (loadv8f64 addr:$src))), + (VCVTTPD2QQZrm addr:$src)>; + + def : Pat<(v8i64 (fp_to_uint (v8f64 VR512:$src))), + (VCVTTPD2UQQZrr VR512:$src)>; + def : Pat<(v8i64 (fp_to_uint (loadv8f64 addr:$src))), + (VCVTTPD2UQQZrm addr:$src)>; +} + +let Predicates = [HasDQI, HasVLX] in { + def : Pat<(v4i64 (fp_to_sint (v4f32 VR128X:$src))), + (VCVTTPS2QQZ256rr VR128X:$src)>; + def : Pat<(v4i64 (fp_to_sint (loadv4f32 addr:$src))), + (VCVTTPS2QQZ256rm addr:$src)>; + + def : Pat<(v4i64 (fp_to_uint (v4f32 VR128X:$src))), + (VCVTTPS2UQQZ256rr VR128X:$src)>; + def : Pat<(v4i64 (fp_to_uint (loadv4f32 addr:$src))), + (VCVTTPS2UQQZ256rm addr:$src)>; + + def : Pat<(v2i64 (fp_to_sint (v2f64 VR128X:$src))), + (VCVTTPD2QQZ128rr VR128X:$src)>; + def : Pat<(v2i64 (fp_to_sint (loadv2f64 addr:$src))), + (VCVTTPD2QQZ128rm addr:$src)>; + + def : Pat<(v2i64 (fp_to_uint (v2f64 VR128X:$src))), + (VCVTTPD2UQQZ128rr VR128X:$src)>; + def : Pat<(v2i64 (fp_to_uint (loadv2f64 addr:$src))), + (VCVTTPD2UQQZ128rm addr:$src)>; + + def : Pat<(v4i64 (fp_to_sint (v4f64 VR256X:$src))), + (VCVTTPD2QQZ256rr VR256X:$src)>; + def : Pat<(v4i64 (fp_to_sint (loadv4f64 addr:$src))), + (VCVTTPD2QQZ256rm addr:$src)>; + + def : Pat<(v4i64 (fp_to_uint (v4f64 VR256X:$src))), + (VCVTTPD2UQQZ256rr VR256X:$src)>; + def : Pat<(v4i64 (fp_to_uint (loadv4f64 addr:$src))), + (VCVTTPD2UQQZ256rm addr:$src)>; +} + +let Predicates = [HasAVX512, NoVLX] in { +def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))), + (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr + (v16f32 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_ymm)>; + +def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))), + (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr + (v16f32 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; + +def : Pat<(v4i32 (fp_to_uint (v4f64 VR256X:$src1))), + (EXTRACT_SUBREG (v8i32 (VCVTTPD2UDQZrr + (v8f64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_xmm)>; + +def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))), + (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_ymm)>; + +def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))), + (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; + +def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))), + (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr + (v8i32 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_ymm)>; + +def : Pat<(v2f64 (X86VUintToFP (v4i32 VR128X:$src1))), + (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr + (v8i32 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; +} + +let Predicates = [HasAVX512, HasVLX] in { + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2Int (v2f64 VR128X:$src)))))), + (VCVTPD2DQZ128rr VR128X:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2Int (loadv2f64 addr:$src)))))), + (VCVTPD2DQZ128rm addr:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2UInt (v2f64 VR128X:$src)))))), + (VCVTPD2UDQZ128rr VR128X:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2si (v2f64 VR128X:$src)))))), + (VCVTTPD2DQZ128rr VR128X:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2si (loadv2f64 addr:$src)))))), + (VCVTTPD2DQZ128rm addr:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2ui (v2f64 VR128X:$src)))))), + (VCVTTPD2UDQZ128rr VR128X:$src)>; + + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (VCVTDQ2PDZ128rm addr:$src)>; + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (X86vzload addr:$src))))), + (VCVTDQ2PDZ128rm addr:$src)>; + + def : Pat<(v2f64 (X86VUintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (VCVTUDQ2PDZ128rm addr:$src)>; + def : Pat<(v2f64 (X86VUintToFP (bc_v4i32 (v2i64 (X86vzload addr:$src))))), + (VCVTUDQ2PDZ128rm addr:$src)>; +} + +let Predicates = [HasAVX512] in { + def : Pat<(v8f32 (fpround (loadv8f64 addr:$src))), + (VCVTPD2PSZrm addr:$src)>; + def : Pat<(v8f64 (extloadv8f32 addr:$src)), + (VCVTPS2PDZrm addr:$src)>; +} + +let Predicates = [HasDQI, HasVLX] in { + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86VSintToFP (v2i64 VR128X:$src)))))), + (VCVTQQ2PSZ128rr VR128X:$src)>; + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86VUintToFP (v2i64 VR128X:$src)))))), + (VCVTUQQ2PSZ128rr VR128X:$src)>; +} + +let Predicates = [HasDQI, NoVLX] in { +def : Pat<(v2i64 (fp_to_sint (v2f64 VR128X:$src1))), + (EXTRACT_SUBREG (v8i64 (VCVTTPD2QQZrr + (v8f64 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; + +def : Pat<(v4i64 (fp_to_sint (v4f32 VR128X:$src1))), + (EXTRACT_SUBREG (v8i64 (VCVTTPS2QQZrr + (v8f32 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_ymm)>; + +def : Pat<(v4i64 (fp_to_sint (v4f64 VR256X:$src1))), + (EXTRACT_SUBREG (v8i64 (VCVTTPD2QQZrr + (v8f64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_ymm)>; + +def : Pat<(v2i64 (fp_to_uint (v2f64 VR128X:$src1))), + (EXTRACT_SUBREG (v8i64 (VCVTTPD2UQQZrr + (v8f64 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; + +def : Pat<(v4i64 (fp_to_uint (v4f32 VR128X:$src1))), + (EXTRACT_SUBREG (v8i64 (VCVTTPS2UQQZrr + (v8f32 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_ymm)>; + +def : Pat<(v4i64 (fp_to_uint (v4f64 VR256X:$src1))), + (EXTRACT_SUBREG (v8i64 (VCVTTPD2UQQZrr + (v8f64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_ymm)>; + +def : Pat<(v4f32 (sint_to_fp (v4i64 VR256X:$src1))), + (EXTRACT_SUBREG (v8f32 (VCVTQQ2PSZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_xmm)>; + +def : Pat<(v2f64 (sint_to_fp (v2i64 VR128X:$src1))), + (EXTRACT_SUBREG (v8f64 (VCVTQQ2PDZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; + +def : Pat<(v4f64 (sint_to_fp (v4i64 VR256X:$src1))), + (EXTRACT_SUBREG (v8f64 (VCVTQQ2PDZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_ymm)>; + +def : Pat<(v4f32 (uint_to_fp (v4i64 VR256X:$src1))), + (EXTRACT_SUBREG (v8f32 (VCVTUQQ2PSZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_xmm)>; + +def : Pat<(v2f64 (uint_to_fp (v2i64 VR128X:$src1))), + (EXTRACT_SUBREG (v8f64 (VCVTUQQ2PDZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; + +def : Pat<(v4f64 (uint_to_fp (v4i64 VR256X:$src1))), + (EXTRACT_SUBREG (v8f64 (VCVTUQQ2PDZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_ymm)>; +} + +//===----------------------------------------------------------------------===// +// Half precision conversion instructions +//===----------------------------------------------------------------------===// + +multiclass avx512_cvtph2ps { + defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), + (ins _src.RC:$src), "vcvtph2ps", "$src", "$src", + (X86cvtph2ps (_src.VT _src.RC:$src))>, + T8PD, Sched<[sched]>; + defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), + (ins x86memop:$src), "vcvtph2ps", "$src", "$src", + (X86cvtph2ps (_src.VT + (bitconvert + (ld_frag addr:$src))))>, + T8PD, Sched<[sched.Folded]>; +} + +multiclass avx512_cvtph2ps_sae { + defm rrb : AVX512_maskable<0x13, MRMSrcReg, _dest, (outs _dest.RC:$dst), + (ins _src.RC:$src), "vcvtph2ps", + "{sae}, $src", "$src, {sae}", + (X86cvtph2psRnd (_src.VT _src.RC:$src), + (i32 FROUND_NO_EXC))>, + T8PD, EVEX_B, Sched<[sched]>; +} + +let Predicates = [HasAVX512] in + defm VCVTPH2PSZ : avx512_cvtph2ps, + avx512_cvtph2ps_sae, + EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>; + +let Predicates = [HasVLX] in { + defm VCVTPH2PSZ256 : avx512_cvtph2ps, EVEX, EVEX_V256, + EVEX_CD8<32, CD8VH>; + defm VCVTPH2PSZ128 : avx512_cvtph2ps, EVEX, EVEX_V128, + EVEX_CD8<32, CD8VH>; + + // Pattern match vcvtph2ps of a scalar i64 load. + def : Pat<(v4f32 (X86cvtph2ps (v8i16 (vzmovl_v2i64 addr:$src)))), + (VCVTPH2PSZ128rm addr:$src)>; + def : Pat<(v4f32 (X86cvtph2ps (v8i16 (vzload_v2i64 addr:$src)))), + (VCVTPH2PSZ128rm addr:$src)>; + def : Pat<(v4f32 (X86cvtph2ps (v8i16 (bitconvert + (v2i64 (scalar_to_vector (loadi64 addr:$src))))))), + (VCVTPH2PSZ128rm addr:$src)>; +} + +multiclass avx512_cvtps2ph { + defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst), + (ins _src.RC:$src1, i32u8imm:$src2), + "vcvtps2ph", "$src2, $src1", "$src1, $src2", + (X86cvtps2ph (_src.VT _src.RC:$src1), + (i32 imm:$src2)), 0, 0>, + AVX512AIi8Base, Sched<[RR]>; + let hasSideEffects = 0, mayStore = 1 in { + def mr : AVX512AIi8<0x1D, MRMDestMem, (outs), + (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2), + "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + Sched<[MR]>; + def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs), + (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2), + "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}", []>, + EVEX_K, Sched<[MR]>, NotMemoryFoldable; + } +} + +multiclass avx512_cvtps2ph_sae { + let hasSideEffects = 0 in + defm rrb : AVX512_maskable_in_asm<0x1D, MRMDestReg, _dest, + (outs _dest.RC:$dst), + (ins _src.RC:$src1, i32u8imm:$src2), + "vcvtps2ph", "$src2, {sae}, $src1", "$src1, {sae}, $src2", []>, + EVEX_B, AVX512AIi8Base, Sched<[Sched]>; +} + +let Predicates = [HasAVX512] in { + defm VCVTPS2PHZ : avx512_cvtps2ph, + avx512_cvtps2ph_sae, + EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>; + let Predicates = [HasVLX] in { + defm VCVTPS2PHZ256 : avx512_cvtps2ph, + EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>; + defm VCVTPS2PHZ128 : avx512_cvtps2ph, + EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>; + } + + def : Pat<(store (f64 (extractelt + (bc_v2f64 (v8i16 (X86cvtps2ph VR128X:$src1, i32:$src2))), + (iPTR 0))), addr:$dst), + (VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, imm:$src2)>; + def : Pat<(store (i64 (extractelt + (bc_v2i64 (v8i16 (X86cvtps2ph VR128X:$src1, i32:$src2))), + (iPTR 0))), addr:$dst), + (VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, imm:$src2)>; + def : Pat<(store (v8i16 (X86cvtps2ph VR256X:$src1, i32:$src2)), addr:$dst), + (VCVTPS2PHZ256mr addr:$dst, VR256X:$src1, imm:$src2)>; + def : Pat<(store (v16i16 (X86cvtps2ph VR512:$src1, i32:$src2)), addr:$dst), + (VCVTPS2PHZmr addr:$dst, VR512:$src1, imm:$src2)>; +} + +// Patterns for matching conversions from float to half-float and vice versa. +let Predicates = [HasVLX] in { + // Use MXCSR.RC for rounding instead of explicitly specifying the default + // rounding mode (Nearest-Even, encoded as 0). Both are equivalent in the + // configurations we support (the default). However, falling back to MXCSR is + // more consistent with other instructions, which are always controlled by it. + // It's encoded as 0b100. + def : Pat<(fp_to_f16 FR32X:$src), + (i16 (EXTRACT_SUBREG (VMOVPDI2DIZrr (v8i16 (VCVTPS2PHZ128rr + (v4f32 (COPY_TO_REGCLASS FR32X:$src, VR128X)), 4))), sub_16bit))>; + + def : Pat<(f16_to_fp GR16:$src), + (f32 (COPY_TO_REGCLASS (v4f32 (VCVTPH2PSZ128rr + (v8i16 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128X)))), FR32X)) >; + + def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32X:$src))), + (f32 (COPY_TO_REGCLASS (v4f32 (VCVTPH2PSZ128rr + (v8i16 (VCVTPS2PHZ128rr + (v4f32 (COPY_TO_REGCLASS FR32X:$src, VR128X)), 4)))), FR32X)) >; +} + +// Unordered/Ordered scalar fp compare with Sea and set EFLAGS +multiclass avx512_ord_cmp_sae opc, X86VectorVTInfo _, + string OpcodeStr, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def rrb: AVX512, + EVEX, EVEX_B, VEX_LIG, EVEX_V128, Sched<[sched]>; +} + +let Defs = [EFLAGS], Predicates = [HasAVX512] in { + defm VUCOMISSZ : avx512_ord_cmp_sae<0x2E, v4f32x_info, "vucomiss", WriteFCom>, + AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>; + defm VUCOMISDZ : avx512_ord_cmp_sae<0x2E, v2f64x_info, "vucomisd", WriteFCom>, + AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>; + defm VCOMISSZ : avx512_ord_cmp_sae<0x2F, v4f32x_info, "vcomiss", WriteFCom>, + AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>; + defm VCOMISDZ : avx512_ord_cmp_sae<0x2F, v2f64x_info, "vcomisd", WriteFCom>, + AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>; +} + +let Defs = [EFLAGS], Predicates = [HasAVX512] in { + defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32, + "ucomiss", WriteFCom>, PS, EVEX, VEX_LIG, + EVEX_CD8<32, CD8VT1>; + defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64, + "ucomisd", WriteFCom>, PD, EVEX, + VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; + let Pattern = [] in { + defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32, + "comiss", WriteFCom>, PS, EVEX, VEX_LIG, + EVEX_CD8<32, CD8VT1>; + defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64, + "comisd", WriteFCom>, PD, EVEX, + VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; + } + let isCodeGenOnly = 1 in { + defm VUCOMISSZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v4f32, ssmem, + sse_load_f32, "ucomiss", WriteFCom>, PS, EVEX, VEX_LIG, + EVEX_CD8<32, CD8VT1>; + defm VUCOMISDZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v2f64, sdmem, + sse_load_f64, "ucomisd", WriteFCom>, PD, EVEX, + VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; + + defm VCOMISSZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v4f32, ssmem, + sse_load_f32, "comiss", WriteFCom>, PS, EVEX, VEX_LIG, + EVEX_CD8<32, CD8VT1>; + defm VCOMISDZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v2f64, sdmem, + sse_load_f64, "comisd", WriteFCom>, PD, EVEX, + VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; + } +} + +/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd +multiclass avx512_fp14_s opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let Predicates = [HasAVX512], ExeDomain = _.ExeDomain in { + defm rr : AVX512_maskable_scalar, + EVEX_4V, Sched<[sched]>; + defm rm : AVX512_maskable_scalar, EVEX_4V, + Sched<[sched.Folded, ReadAfterLd]>; +} +} + +defm VRCP14SSZ : avx512_fp14_s<0x4D, "vrcp14ss", X86rcp14s, SchedWriteFRcp.Scl, + f32x_info>, EVEX_CD8<32, CD8VT1>, + T8PD; +defm VRCP14SDZ : avx512_fp14_s<0x4D, "vrcp14sd", X86rcp14s, SchedWriteFRcp.Scl, + f64x_info>, VEX_W, EVEX_CD8<64, CD8VT1>, + T8PD; +defm VRSQRT14SSZ : avx512_fp14_s<0x4F, "vrsqrt14ss", X86rsqrt14s, + SchedWriteFRsqrt.Scl, f32x_info>, + EVEX_CD8<32, CD8VT1>, T8PD; +defm VRSQRT14SDZ : avx512_fp14_s<0x4F, "vrsqrt14sd", X86rsqrt14s, + SchedWriteFRsqrt.Scl, f64x_info>, VEX_W, + EVEX_CD8<64, CD8VT1>, T8PD; + +/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd +multiclass avx512_fp14_p opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm r: AVX512_maskable, EVEX, T8PD, + Sched<[sched]>; + defm m: AVX512_maskable, EVEX, T8PD, + Sched<[sched.Folded, ReadAfterLd]>; + defm mb: AVX512_maskable, + EVEX, T8PD, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fp14_p_vl_all opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + defm PSZ : avx512_fp14_p, EVEX_V512, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp14_p, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; + + // Define only if AVX512VL feature is present. + let Predicates = [HasVLX] in { + defm PSZ128 : avx512_fp14_p, + EVEX_V128, EVEX_CD8<32, CD8VF>; + defm PSZ256 : avx512_fp14_p, + EVEX_V256, EVEX_CD8<32, CD8VF>; + defm PDZ128 : avx512_fp14_p, + EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>; + defm PDZ256 : avx512_fp14_p, + EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>; + } +} + +defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86rsqrt14, SchedWriteFRsqrt>; +defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86rcp14, SchedWriteFRcp>; + +/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd +multiclass avx512_fp28_s opc, string OpcodeStr,X86VectorVTInfo _, + SDNode OpNode, X86FoldableSchedWrite sched> { + let ExeDomain = _.ExeDomain in { + defm r : AVX512_maskable_scalar, + Sched<[sched]>; + + defm rb : AVX512_maskable_scalar, EVEX_B, + Sched<[sched]>; + + defm m : AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_eri_s opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched> { + defm SSZ : avx512_fp28_s, + EVEX_CD8<32, CD8VT1>; + defm SDZ : avx512_fp28_s, + EVEX_CD8<64, CD8VT1>, VEX_W; +} + +let Predicates = [HasERI] in { + defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s, SchedWriteFRcp.Scl>, + T8PD, EVEX_4V; + defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s, + SchedWriteFRsqrt.Scl>, T8PD, EVEX_4V; +} + +defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds, + SchedWriteFRnd.Scl>, T8PD, EVEX_4V; +/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd + +multiclass avx512_fp28_p opc, string OpcodeStr, X86VectorVTInfo _, + SDNode OpNode, X86FoldableSchedWrite sched> { + let ExeDomain = _.ExeDomain in { + defm r : AVX512_maskable, + Sched<[sched]>; + + defm m : AVX512_maskable, + Sched<[sched.Folded, ReadAfterLd]>; + + defm mb : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } +} +multiclass avx512_fp28_p_round opc, string OpcodeStr, X86VectorVTInfo _, + SDNode OpNode, X86FoldableSchedWrite sched> { + let ExeDomain = _.ExeDomain in + defm rb : AVX512_maskable, + EVEX_B, Sched<[sched]>; +} + +multiclass avx512_eri opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + defm PSZ : avx512_fp28_p, + avx512_fp28_p_round, + T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp28_p, + avx512_fp28_p_round, + T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; +} + +multiclass avx512_fp_unaryop_packed opc, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched> { + // Define only if AVX512VL feature is present. + let Predicates = [HasVLX] in { + defm PSZ128 : avx512_fp28_p, + EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>; + defm PSZ256 : avx512_fp28_p, + EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>; + defm PDZ128 : avx512_fp28_p, + EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>; + defm PDZ256 : avx512_fp28_p, + EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>; + } +} + +let Predicates = [HasERI] in { + defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28, SchedWriteFRsqrt>, EVEX; + defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28, SchedWriteFRcp>, EVEX; + defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2, SchedWriteFAdd>, EVEX; +} +defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd, SchedWriteFRnd>, + avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd, + SchedWriteFRnd>, EVEX; + +multiclass avx512_sqrt_packed_round opc, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _>{ + let ExeDomain = _.ExeDomain in + defm rb: AVX512_maskable, + EVEX, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +multiclass avx512_sqrt_packed opc, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _>{ + let ExeDomain = _.ExeDomain in { + defm r: AVX512_maskable, EVEX, + Sched<[sched]>; + defm m: AVX512_maskable, EVEX, + Sched<[sched.Folded, ReadAfterLd]>; + defm mb: AVX512_maskable, + EVEX, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_sqrt_packed_all opc, string OpcodeStr, + X86SchedWriteSizes sched> { + defm PSZ : avx512_sqrt_packed, + EVEX_V512, PS, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_sqrt_packed, + EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>; + // Define only if AVX512VL feature is present. + let Predicates = [HasVLX] in { + defm PSZ128 : avx512_sqrt_packed, + EVEX_V128, PS, EVEX_CD8<32, CD8VF>; + defm PSZ256 : avx512_sqrt_packed, + EVEX_V256, PS, EVEX_CD8<32, CD8VF>; + defm PDZ128 : avx512_sqrt_packed, + EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>; + defm PDZ256 : avx512_sqrt_packed, + EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>; + } +} + +multiclass avx512_sqrt_packed_all_round opc, string OpcodeStr, + X86SchedWriteSizes sched> { + defm PSZ : avx512_sqrt_packed_round, + EVEX_V512, PS, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_sqrt_packed_round, + EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>; +} + +multiclass avx512_sqrt_scalar opc, string OpcodeStr, X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Name> { + let ExeDomain = _.ExeDomain in { + defm r_Int : AVX512_maskable_scalar, + Sched<[sched]>; + defm m_Int : AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + defm rb_Int : AVX512_maskable_scalar, + EVEX_B, EVEX_RC, Sched<[sched]>; + + let isCodeGenOnly = 1, hasSideEffects = 0, Predicates=[HasAVX512] in { + def r : I, + Sched<[sched]>; + let mayLoad = 1 in + def m : I, + Sched<[sched.Folded, ReadAfterLd]>; + } + } + + let Predicates = [HasAVX512] in { + def : Pat<(_.EltVT (fsqrt _.FRC:$src)), + (!cast(Name#Zr) + (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>; + } + + let Predicates = [HasAVX512, OptForSize] in { + def : Pat<(_.EltVT (fsqrt (load addr:$src))), + (!cast(Name#Zm) + (_.EltVT (IMPLICIT_DEF)), addr:$src)>; + } +} + +multiclass avx512_sqrt_scalar_all opc, string OpcodeStr, + X86SchedWriteSizes sched> { + defm SSZ : avx512_sqrt_scalar, + EVEX_CD8<32, CD8VT1>, EVEX_4V, XS; + defm SDZ : avx512_sqrt_scalar, + EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W; +} + +defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", SchedWriteFSqrtSizes>, + avx512_sqrt_packed_all_round<0x51, "vsqrt", SchedWriteFSqrtSizes>; + +defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt", SchedWriteFSqrtSizes>, VEX_LIG; + +multiclass avx512_rndscale_scalar opc, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm r_Int : AVX512_maskable_scalar, + Sched<[sched]>; + + defm rb_Int : AVX512_maskable_scalar, EVEX_B, + Sched<[sched]>; + + defm m_Int : AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + + let isCodeGenOnly = 1, hasSideEffects = 0, Predicates = [HasAVX512] in { + def r : I, Sched<[sched]>; + + let mayLoad = 1 in + def m : I, Sched<[sched.Folded, ReadAfterLd]>; + } + } + + let Predicates = [HasAVX512] in { + def : Pat<(ffloor _.FRC:$src), + (_.EltVT (!cast(NAME##r) (_.EltVT (IMPLICIT_DEF)), + _.FRC:$src, (i32 0x9)))>; + def : Pat<(fceil _.FRC:$src), + (_.EltVT (!cast(NAME##r) (_.EltVT (IMPLICIT_DEF)), + _.FRC:$src, (i32 0xa)))>; + def : Pat<(ftrunc _.FRC:$src), + (_.EltVT (!cast(NAME##r) (_.EltVT (IMPLICIT_DEF)), + _.FRC:$src, (i32 0xb)))>; + def : Pat<(frint _.FRC:$src), + (_.EltVT (!cast(NAME##r) (_.EltVT (IMPLICIT_DEF)), + _.FRC:$src, (i32 0x4)))>; + def : Pat<(fnearbyint _.FRC:$src), + (_.EltVT (!cast(NAME##r) (_.EltVT (IMPLICIT_DEF)), + _.FRC:$src, (i32 0xc)))>; + } + + let Predicates = [HasAVX512, OptForSize] in { + def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), + (_.EltVT (!cast(NAME##m) (_.EltVT (IMPLICIT_DEF)), + addr:$src, (i32 0x9)))>; + def : Pat<(fceil (_.ScalarLdFrag addr:$src)), + (_.EltVT (!cast(NAME##m) (_.EltVT (IMPLICIT_DEF)), + addr:$src, (i32 0xa)))>; + def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), + (_.EltVT (!cast(NAME##m) (_.EltVT (IMPLICIT_DEF)), + addr:$src, (i32 0xb)))>; + def : Pat<(frint (_.ScalarLdFrag addr:$src)), + (_.EltVT (!cast(NAME##m) (_.EltVT (IMPLICIT_DEF)), + addr:$src, (i32 0x4)))>; + def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), + (_.EltVT (!cast(NAME##m) (_.EltVT (IMPLICIT_DEF)), + addr:$src, (i32 0xc)))>; + } +} + +defm VRNDSCALESSZ : avx512_rndscale_scalar<0x0A, "vrndscaless", + SchedWriteFRnd.Scl, f32x_info>, + AVX512AIi8Base, EVEX_4V, + EVEX_CD8<32, CD8VT1>; + +defm VRNDSCALESDZ : avx512_rndscale_scalar<0x0B, "vrndscalesd", + SchedWriteFRnd.Scl, f64x_info>, + VEX_W, AVX512AIi8Base, EVEX_4V, + EVEX_CD8<64, CD8VT1>; + +multiclass avx512_masked_scalar { + let Predicates = [BasePredicate] in { + def : Pat<(Move _.VT:$src1, (scalar_to_vector (X86selects Mask, + (OpNode (extractelt _.VT:$src2, (iPTR 0))), + (extractelt _.VT:$dst, (iPTR 0))))), + (!cast("V"#OpcPrefix#r_Intk) + _.VT:$dst, OutMask, _.VT:$src2, _.VT:$src1)>; + + def : Pat<(Move _.VT:$src1, (scalar_to_vector (X86selects Mask, + (OpNode (extractelt _.VT:$src2, (iPTR 0))), + ZeroFP))), + (!cast("V"#OpcPrefix#r_Intkz) + OutMask, _.VT:$src2, _.VT:$src1)>; + } +} + +defm : avx512_masked_scalar; +defm : avx512_masked_scalar; + +multiclass avx512_masked_scalar_imm ImmV, Predicate BasePredicate> { + let Predicates = [BasePredicate] in { + def : Pat<(Move _.VT:$src1, (scalar_to_vector (X86selects VK1WM:$mask, + (OpNode (extractelt _.VT:$src2, (iPTR 0))), + (extractelt _.VT:$dst, (iPTR 0))))), + (!cast("V"#OpcPrefix#Zr_Intk) + _.VT:$dst, VK1WM:$mask, _.VT:$src1, _.VT:$src2, (i32 ImmV))>; + + def : Pat<(Move _.VT:$src1, (scalar_to_vector (X86selects VK1WM:$mask, + (OpNode (extractelt _.VT:$src2, (iPTR 0))), ZeroFP))), + (!cast("V"#OpcPrefix#Zr_Intkz) + VK1WM:$mask, _.VT:$src1, _.VT:$src2, (i32 ImmV))>; + } +} + +defm : avx512_masked_scalar_imm; +defm : avx512_masked_scalar_imm; +defm : avx512_masked_scalar_imm; +defm : avx512_masked_scalar_imm; + + +//------------------------------------------------- +// Integer truncate and extend operations +//------------------------------------------------- + +multiclass avx512_trunc_common opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo SrcInfo, + X86VectorVTInfo DestInfo, X86MemOperand x86memop> { + let ExeDomain = DestInfo.ExeDomain in + defm rr : AVX512_maskable, + EVEX, T8XS, Sched<[sched]>; + + let mayStore = 1, hasSideEffects = 0, ExeDomain = DestInfo.ExeDomain in { + def mr : AVX512XS8I, + EVEX, Sched<[sched.Folded]>; + + def mrk : AVX512XS8I, + EVEX, EVEX_K, Sched<[sched.Folded]>, NotMemoryFoldable; + }//mayStore = 1, hasSideEffects = 0 +} + +multiclass avx512_trunc_mr_lowering { + + def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst), + (!cast(Name#SrcInfo.ZSuffix##mr) + addr:$dst, SrcInfo.RC:$src)>; + + def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask, + (SrcInfo.VT SrcInfo.RC:$src)), + (!cast(Name#SrcInfo.ZSuffix##mrk) + addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>; +} + +multiclass avx512_trunc opc, string OpcodeStr, SDNode OpNode128, + SDNode OpNode256, SDNode OpNode512, X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTSrcInfo, + X86VectorVTInfo DestInfoZ128, + X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ, + X86MemOperand x86memopZ128, X86MemOperand x86memopZ256, + X86MemOperand x86memopZ, PatFrag truncFrag, + PatFrag mtruncFrag, Predicate prd = HasAVX512>{ + + let Predicates = [HasVLX, prd] in { + defm Z128: avx512_trunc_common, + avx512_trunc_mr_lowering, EVEX_V128; + + defm Z256: avx512_trunc_common, + avx512_trunc_mr_lowering, EVEX_V256; + } + let Predicates = [prd] in + defm Z: avx512_trunc_common, + avx512_trunc_mr_lowering, EVEX_V512; +} + +multiclass avx512_trunc_qb opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag StoreNode, + PatFrag MaskedStoreNode, SDNode InVecNode = OpNode> { + defm NAME: avx512_trunc, EVEX_CD8<8, CD8VO>; +} + +multiclass avx512_trunc_qw opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag StoreNode, + PatFrag MaskedStoreNode, SDNode InVecNode = OpNode> { + defm NAME: avx512_trunc, EVEX_CD8<16, CD8VQ>; +} + +multiclass avx512_trunc_qd opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag StoreNode, + PatFrag MaskedStoreNode, SDNode InVecNode = OpNode> { + defm NAME: avx512_trunc, EVEX_CD8<32, CD8VH>; +} + +multiclass avx512_trunc_db opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag StoreNode, + PatFrag MaskedStoreNode, SDNode InVecNode = OpNode> { + defm NAME: avx512_trunc, EVEX_CD8<8, CD8VQ>; +} + +multiclass avx512_trunc_dw opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag StoreNode, + PatFrag MaskedStoreNode, SDNode InVecNode = OpNode> { + defm NAME: avx512_trunc, EVEX_CD8<16, CD8VH>; +} + +multiclass avx512_trunc_wb opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag StoreNode, + PatFrag MaskedStoreNode, SDNode InVecNode = OpNode> { + defm NAME: avx512_trunc, EVEX_CD8<16, CD8VH>; +} + +defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", trunc, WriteShuffle256, + truncstorevi8, masked_truncstorevi8, X86vtrunc>; +defm VPMOVSQB : avx512_trunc_qb<0x22, "vpmovsqb", X86vtruncs, WriteShuffle256, + truncstore_s_vi8, masked_truncstore_s_vi8>; +defm VPMOVUSQB : avx512_trunc_qb<0x12, "vpmovusqb", X86vtruncus, WriteShuffle256, + truncstore_us_vi8, masked_truncstore_us_vi8>; + +defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", trunc, WriteShuffle256, + truncstorevi16, masked_truncstorevi16, X86vtrunc>; +defm VPMOVSQW : avx512_trunc_qw<0x24, "vpmovsqw", X86vtruncs, WriteShuffle256, + truncstore_s_vi16, masked_truncstore_s_vi16>; +defm VPMOVUSQW : avx512_trunc_qw<0x14, "vpmovusqw", X86vtruncus, WriteShuffle256, + truncstore_us_vi16, masked_truncstore_us_vi16>; + +defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", trunc, WriteShuffle256, + truncstorevi32, masked_truncstorevi32, X86vtrunc>; +defm VPMOVSQD : avx512_trunc_qd<0x25, "vpmovsqd", X86vtruncs, WriteShuffle256, + truncstore_s_vi32, masked_truncstore_s_vi32>; +defm VPMOVUSQD : avx512_trunc_qd<0x15, "vpmovusqd", X86vtruncus, WriteShuffle256, + truncstore_us_vi32, masked_truncstore_us_vi32>; + +defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", trunc, WriteShuffle256, + truncstorevi8, masked_truncstorevi8, X86vtrunc>; +defm VPMOVSDB : avx512_trunc_db<0x21, "vpmovsdb", X86vtruncs, WriteShuffle256, + truncstore_s_vi8, masked_truncstore_s_vi8>; +defm VPMOVUSDB : avx512_trunc_db<0x11, "vpmovusdb", X86vtruncus, WriteShuffle256, + truncstore_us_vi8, masked_truncstore_us_vi8>; + +defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", trunc, WriteShuffle256, + truncstorevi16, masked_truncstorevi16, X86vtrunc>; +defm VPMOVSDW : avx512_trunc_dw<0x23, "vpmovsdw", X86vtruncs, WriteShuffle256, + truncstore_s_vi16, masked_truncstore_s_vi16>; +defm VPMOVUSDW : avx512_trunc_dw<0x13, "vpmovusdw", X86vtruncus, WriteShuffle256, + truncstore_us_vi16, masked_truncstore_us_vi16>; + +defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", trunc, WriteShuffle256, + truncstorevi8, masked_truncstorevi8, X86vtrunc>; +defm VPMOVSWB : avx512_trunc_wb<0x20, "vpmovswb", X86vtruncs, WriteShuffle256, + truncstore_s_vi8, masked_truncstore_s_vi8>; +defm VPMOVUSWB : avx512_trunc_wb<0x10, "vpmovuswb", X86vtruncus, WriteShuffle256, + truncstore_us_vi8, masked_truncstore_us_vi8>; + +let Predicates = [HasAVX512, NoVLX] in { +def: Pat<(v8i16 (trunc (v8i32 VR256X:$src))), + (v8i16 (EXTRACT_SUBREG + (v16i16 (VPMOVDWZrr (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src, sub_ymm)))), sub_xmm))>; +def: Pat<(v4i32 (trunc (v4i64 VR256X:$src))), + (v4i32 (EXTRACT_SUBREG + (v8i32 (VPMOVQDZrr (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src, sub_ymm)))), sub_xmm))>; +} + +let Predicates = [HasBWI, NoVLX] in { +def: Pat<(v16i8 (trunc (v16i16 VR256X:$src))), + (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src, sub_ymm))), sub_xmm))>; +} + +multiclass WriteShuffle256_common opc, string OpcodeStr, X86FoldableSchedWrite sched, + X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo, + X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{ + let ExeDomain = DestInfo.ExeDomain in { + defm rr : AVX512_maskable, + EVEX, Sched<[sched]>; + + defm rm : AVX512_maskable, + EVEX, Sched<[sched.Folded]>; + } +} + +multiclass WriteShuffle256_BW opc, string OpcodeStr, + SDNode OpNode, SDNode InVecNode, string ExtTy, + X86FoldableSchedWrite sched, PatFrag LdFrag = !cast(ExtTy#"extloadvi8")> { + let Predicates = [HasVLX, HasBWI] in { + defm Z128: WriteShuffle256_common, + EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128, VEX_WIG; + + defm Z256: WriteShuffle256_common, + EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256, VEX_WIG; + } + let Predicates = [HasBWI] in { + defm Z : WriteShuffle256_common, + EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512, VEX_WIG; + } +} + +multiclass WriteShuffle256_BD opc, string OpcodeStr, + SDNode OpNode, SDNode InVecNode, string ExtTy, + X86FoldableSchedWrite sched, PatFrag LdFrag = !cast(ExtTy#"extloadvi8")> { + let Predicates = [HasVLX, HasAVX512] in { + defm Z128: WriteShuffle256_common, + EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128, VEX_WIG; + + defm Z256: WriteShuffle256_common, + EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256, VEX_WIG; + } + let Predicates = [HasAVX512] in { + defm Z : WriteShuffle256_common, + EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512, VEX_WIG; + } +} + +multiclass WriteShuffle256_BQ opc, string OpcodeStr, + SDNode OpNode, SDNode InVecNode, string ExtTy, + X86FoldableSchedWrite sched, PatFrag LdFrag = !cast(ExtTy#"extloadvi8")> { + let Predicates = [HasVLX, HasAVX512] in { + defm Z128: WriteShuffle256_common, + EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128, VEX_WIG; + + defm Z256: WriteShuffle256_common, + EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256, VEX_WIG; + } + let Predicates = [HasAVX512] in { + defm Z : WriteShuffle256_common, + EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512, VEX_WIG; + } +} + +multiclass WriteShuffle256_WD opc, string OpcodeStr, + SDNode OpNode, SDNode InVecNode, string ExtTy, + X86FoldableSchedWrite sched, PatFrag LdFrag = !cast(ExtTy#"extloadvi16")> { + let Predicates = [HasVLX, HasAVX512] in { + defm Z128: WriteShuffle256_common, + EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128, VEX_WIG; + + defm Z256: WriteShuffle256_common, + EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256, VEX_WIG; + } + let Predicates = [HasAVX512] in { + defm Z : WriteShuffle256_common, + EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512, VEX_WIG; + } +} + +multiclass WriteShuffle256_WQ opc, string OpcodeStr, + SDNode OpNode, SDNode InVecNode, string ExtTy, + X86FoldableSchedWrite sched, PatFrag LdFrag = !cast(ExtTy#"extloadvi16")> { + let Predicates = [HasVLX, HasAVX512] in { + defm Z128: WriteShuffle256_common, + EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128, VEX_WIG; + + defm Z256: WriteShuffle256_common, + EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256, VEX_WIG; + } + let Predicates = [HasAVX512] in { + defm Z : WriteShuffle256_common, + EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512, VEX_WIG; + } +} + +multiclass WriteShuffle256_DQ opc, string OpcodeStr, + SDNode OpNode, SDNode InVecNode, string ExtTy, + X86FoldableSchedWrite sched, PatFrag LdFrag = !cast(ExtTy#"extloadvi32")> { + + let Predicates = [HasVLX, HasAVX512] in { + defm Z128: WriteShuffle256_common, + EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128; + + defm Z256: WriteShuffle256_common, + EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256; + } + let Predicates = [HasAVX512] in { + defm Z : WriteShuffle256_common, + EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512; + } +} + +defm VPMOVZXBW : WriteShuffle256_BW<0x30, "vpmovzxbw", X86vzext, zext_invec, "z", WriteShuffle256>; +defm VPMOVZXBD : WriteShuffle256_BD<0x31, "vpmovzxbd", X86vzext, zext_invec, "z", WriteShuffle256>; +defm VPMOVZXBQ : WriteShuffle256_BQ<0x32, "vpmovzxbq", X86vzext, zext_invec, "z", WriteShuffle256>; +defm VPMOVZXWD : WriteShuffle256_WD<0x33, "vpmovzxwd", X86vzext, zext_invec, "z", WriteShuffle256>; +defm VPMOVZXWQ : WriteShuffle256_WQ<0x34, "vpmovzxwq", X86vzext, zext_invec, "z", WriteShuffle256>; +defm VPMOVZXDQ : WriteShuffle256_DQ<0x35, "vpmovzxdq", X86vzext, zext_invec, "z", WriteShuffle256>; + +defm VPMOVSXBW: WriteShuffle256_BW<0x20, "vpmovsxbw", X86vsext, sext_invec, "s", WriteShuffle256>; +defm VPMOVSXBD: WriteShuffle256_BD<0x21, "vpmovsxbd", X86vsext, sext_invec, "s", WriteShuffle256>; +defm VPMOVSXBQ: WriteShuffle256_BQ<0x22, "vpmovsxbq", X86vsext, sext_invec, "s", WriteShuffle256>; +defm VPMOVSXWD: WriteShuffle256_WD<0x23, "vpmovsxwd", X86vsext, sext_invec, "s", WriteShuffle256>; +defm VPMOVSXWQ: WriteShuffle256_WQ<0x24, "vpmovsxwq", X86vsext, sext_invec, "s", WriteShuffle256>; +defm VPMOVSXDQ: WriteShuffle256_DQ<0x25, "vpmovsxdq", X86vsext, sext_invec, "s", WriteShuffle256>; + + +multiclass AVX512_pmovx_patterns { + // 128-bit patterns + let Predicates = [HasVLX, HasBWI] in { + def : Pat<(v8i16 (InVecOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#BWZ128rm) addr:$src)>; + def : Pat<(v8i16 (InVecOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))), + (!cast(OpcPrefix#BWZ128rm) addr:$src)>; + def : Pat<(v8i16 (InVecOp (v16i8 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWZ128rm) addr:$src)>; + def : Pat<(v8i16 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWZ128rm) addr:$src)>; + def : Pat<(v8i16 (InVecOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BWZ128rm) addr:$src)>; + } + let Predicates = [HasVLX] in { + def : Pat<(v4i32 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))), + (!cast(OpcPrefix#BDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (v16i8 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#BDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BDZ128rm) addr:$src)>; + + def : Pat<(v2i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (extloadi32i16 addr:$src)))))), + (!cast(OpcPrefix#BQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (v16i8 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#BQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BQZ128rm) addr:$src)>; + + def : Pat<(v4i32 (InVecOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#WDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))), + (!cast(OpcPrefix#WDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (v8i16 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WDZ128rm) addr:$src)>; + + def : Pat<(v2i64 (InVecOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))), + (!cast(OpcPrefix#WQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (v8i16 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#WQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WQZ128rm) addr:$src)>; + + def : Pat<(v2i64 (InVecOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#DQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))), + (!cast(OpcPrefix#DQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (v4i32 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (v4i32 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (bc_v4i32 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#DQZ128rm) addr:$src)>; + } + // 256-bit patterns + let Predicates = [HasVLX, HasBWI] in { + def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BWZ256rm) addr:$src)>; + def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWZ256rm) addr:$src)>; + def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWZ256rm) addr:$src)>; + } + let Predicates = [HasVLX] in { + def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#BDZ256rm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#BDZ256rm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BDZ256rm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BDZ256rm) addr:$src)>; + + def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))), + (!cast(OpcPrefix#BQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#BQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BQZ256rm) addr:$src)>; + + def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WDZ256rm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDZ256rm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDZ256rm) addr:$src)>; + + def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#WQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#WQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WQZ256rm) addr:$src)>; + + def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#DQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQZ256rm) addr:$src)>; + } + // 512-bit patterns + let Predicates = [HasBWI] in { + def : Pat<(v32i16 (ExtOp (bc_v32i8 (loadv4i64 addr:$src)))), + (!cast(OpcPrefix#BWZrm) addr:$src)>; + } + let Predicates = [HasAVX512] in { + def : Pat<(v16i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BDZrm) addr:$src)>; + + def : Pat<(v8i64 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#BQZrm) addr:$src)>; + def : Pat<(v8i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BQZrm) addr:$src)>; + + def : Pat<(v16i32 (ExtOp (bc_v16i16 (loadv4i64 addr:$src)))), + (!cast(OpcPrefix#WDZrm) addr:$src)>; + + def : Pat<(v8i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WQZrm) addr:$src)>; + + def : Pat<(v8i64 (ExtOp (bc_v8i32 (loadv4i64 addr:$src)))), + (!cast(OpcPrefix#DQZrm) addr:$src)>; + } +} + +defm : AVX512_pmovx_patterns<"VPMOVSX", X86vsext, sext_invec>; +defm : AVX512_pmovx_patterns<"VPMOVZX", X86vzext, zext_invec>; + +//===----------------------------------------------------------------------===// +// GATHER - SCATTER Operations + +// FIXME: Improve scheduling of gather/scatter instructions. +multiclass avx512_gather opc, string OpcodeStr, X86VectorVTInfo _, + X86MemOperand memop, PatFrag GatherNode, + RegisterClass MaskRC = _.KRCWM> { + let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb", + ExeDomain = _.ExeDomain in + def rm : AVX5128I, EVEX, EVEX_K, + EVEX_CD8<_.EltSize, CD8VT1>, Sched<[WriteLoad]>; +} + +multiclass avx512_gather_q_pd dopc, bits<8> qopc, + AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { + defm NAME##D##SUFF##Z: avx512_gather, EVEX_V512, VEX_W; + defm NAME##Q##SUFF##Z: avx512_gather, EVEX_V512, VEX_W; +let Predicates = [HasVLX] in { + defm NAME##D##SUFF##Z256: avx512_gather, EVEX_V256, VEX_W; + defm NAME##Q##SUFF##Z256: avx512_gather, EVEX_V256, VEX_W; + defm NAME##D##SUFF##Z128: avx512_gather, EVEX_V128, VEX_W; + defm NAME##Q##SUFF##Z128: avx512_gather, EVEX_V128, VEX_W; +} +} + +multiclass avx512_gather_d_ps dopc, bits<8> qopc, + AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { + defm NAME##D##SUFF##Z: avx512_gather, EVEX_V512; + defm NAME##Q##SUFF##Z: avx512_gather, EVEX_V512; +let Predicates = [HasVLX] in { + defm NAME##D##SUFF##Z256: avx512_gather, EVEX_V256; + defm NAME##Q##SUFF##Z256: avx512_gather, EVEX_V256; + defm NAME##D##SUFF##Z128: avx512_gather, EVEX_V128; + defm NAME##Q##SUFF##Z128: avx512_gather, + EVEX_V128; +} +} + + +defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">, + avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">; + +defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">, + avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">; + +multiclass avx512_scatter opc, string OpcodeStr, X86VectorVTInfo _, + X86MemOperand memop, PatFrag ScatterNode, + RegisterClass MaskRC = _.KRCWM> { + +let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in + + def mr : AVX5128I, + EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[WriteStore]>; +} + +multiclass avx512_scatter_q_pd dopc, bits<8> qopc, + AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { + defm NAME##D##SUFF##Z: avx512_scatter, EVEX_V512, VEX_W; + defm NAME##Q##SUFF##Z: avx512_scatter, EVEX_V512, VEX_W; +let Predicates = [HasVLX] in { + defm NAME##D##SUFF##Z256: avx512_scatter, EVEX_V256, VEX_W; + defm NAME##Q##SUFF##Z256: avx512_scatter, EVEX_V256, VEX_W; + defm NAME##D##SUFF##Z128: avx512_scatter, EVEX_V128, VEX_W; + defm NAME##Q##SUFF##Z128: avx512_scatter, EVEX_V128, VEX_W; +} +} + +multiclass avx512_scatter_d_ps dopc, bits<8> qopc, + AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { + defm NAME##D##SUFF##Z: avx512_scatter, EVEX_V512; + defm NAME##Q##SUFF##Z: avx512_scatter, EVEX_V512; +let Predicates = [HasVLX] in { + defm NAME##D##SUFF##Z256: avx512_scatter, EVEX_V256; + defm NAME##Q##SUFF##Z256: avx512_scatter, EVEX_V256; + defm NAME##D##SUFF##Z128: avx512_scatter, EVEX_V128; + defm NAME##Q##SUFF##Z128: avx512_scatter, + EVEX_V128; +} +} + +defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">, + avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">; + +defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">, + avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">; + +// prefetch +multiclass avx512_gather_scatter_prefetch opc, Format F, string OpcodeStr, + RegisterClass KRC, X86MemOperand memop> { + let Predicates = [HasPFI], mayLoad = 1, mayStore = 1 in + def m : AVX5128I, + EVEX, EVEX_K, Sched<[WriteLoad]>; +} + +defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps", + VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; + +defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps", + VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; + +defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd", + VK8WM, vy512xmem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; + +defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd", + VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; + +defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps", + VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; + +defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps", + VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; + +defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd", + VK8WM, vy512xmem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; + +defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd", + VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; + +defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps", + VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; + +defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps", + VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; + +defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd", + VK8WM, vy512xmem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; + +defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd", + VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; + +defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps", + VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; + +defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps", + VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; + +defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd", + VK8WM, vy512xmem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; + +defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd", + VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; + +multiclass cvt_by_vec_width opc, X86VectorVTInfo Vec, string OpcodeStr > { +def rr : AVX512XS8I, + EVEX, Sched<[WriteMove]>; // TODO - WriteVecTrunc? +} + +multiclass cvt_mask_by_elt_width opc, AVX512VLVectorVTInfo VTInfo, + string OpcodeStr, Predicate prd> { +let Predicates = [prd] in + defm Z : cvt_by_vec_width, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : cvt_by_vec_width, EVEX_V256; + defm Z128 : cvt_by_vec_width, EVEX_V128; + } +} + +defm VPMOVM2B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, "vpmovm2" , HasBWI>; +defm VPMOVM2W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, "vpmovm2", HasBWI> , VEX_W; +defm VPMOVM2D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, "vpmovm2", HasDQI>; +defm VPMOVM2Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, "vpmovm2", HasDQI> , VEX_W; + +multiclass convert_vector_to_mask_common opc, X86VectorVTInfo _, string OpcodeStr > { + def rr : AVX512XS8I, + EVEX, Sched<[WriteMove]>; +} + +// Use 512bit version to implement 128/256 bit in case NoVLX. +multiclass convert_vector_to_mask_lowering { + + def : Pat<(_.KVT (X86pcmpgtm _.ImmAllZerosV, (_.VT _.RC:$src))), + (_.KVT (COPY_TO_REGCLASS + (!cast(Name#"Zrr") + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src, _.SubRegIdx)), + _.KRC))>; +} + +multiclass avx512_convert_vector_to_mask opc, string OpcodeStr, + AVX512VLVectorVTInfo VTInfo, Predicate prd> { + let Predicates = [prd] in + defm Z : convert_vector_to_mask_common , + EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : convert_vector_to_mask_common, + EVEX_V256; + defm Z128 : convert_vector_to_mask_common, + EVEX_V128; + } + let Predicates = [prd, NoVLX] in { + defm Z256_Alt : convert_vector_to_mask_lowering; + defm Z128_Alt : convert_vector_to_mask_lowering; + } +} + +defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m", + avx512vl_i8_info, HasBWI>; +defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m", + avx512vl_i16_info, HasBWI>, VEX_W; +defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m", + avx512vl_i32_info, HasDQI>; +defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m", + avx512vl_i64_info, HasDQI>, VEX_W; + +// Patterns for handling sext from a mask register to v16i8/v16i16 when DQI +// is available, but BWI is not. We can't handle this in lowering because +// a target independent DAG combine likes to combine sext and trunc. +let Predicates = [HasDQI, NoBWI] in { + def : Pat<(v16i8 (sext (v16i1 VK16:$src))), + (VPMOVDBZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>; + def : Pat<(v16i16 (sext (v16i1 VK16:$src))), + (VPMOVDWZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 - COMPRESS and EXPAND +// + +multiclass compress_by_vec_width_common opc, X86VectorVTInfo _, + string OpcodeStr, X86FoldableSchedWrite sched> { + defm rr : AVX512_maskable, AVX5128IBase, + Sched<[sched]>; + + let mayStore = 1, hasSideEffects = 0 in + def mr : AVX5128I, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[sched.Folded]>; + + def mrk : AVX5128I, + EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[sched.Folded]>; +} + +multiclass compress_by_vec_width_lowering { + def : Pat<(X86mCompressingStore addr:$dst, _.KRCWM:$mask, + (_.VT _.RC:$src)), + (!cast(Name#_.ZSuffix##mrk) + addr:$dst, _.KRCWM:$mask, _.RC:$src)>; +} + +multiclass compress_by_elt_width opc, string OpcodeStr, + X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTInfo, + Predicate Pred = HasAVX512> { + let Predicates = [Pred] in + defm Z : compress_by_vec_width_common, + compress_by_vec_width_lowering, EVEX_V512; + + let Predicates = [Pred, HasVLX] in { + defm Z256 : compress_by_vec_width_common, + compress_by_vec_width_lowering, EVEX_V256; + defm Z128 : compress_by_vec_width_common, + compress_by_vec_width_lowering, EVEX_V128; + } +} + +// FIXME: Is there a better scheduler class for VPCOMPRESS? +defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", WriteVarShuffle256, + avx512vl_i32_info>, EVEX, NotMemoryFoldable; +defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", WriteVarShuffle256, + avx512vl_i64_info>, EVEX, VEX_W, NotMemoryFoldable; +defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", WriteVarShuffle256, + avx512vl_f32_info>, EVEX, NotMemoryFoldable; +defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", WriteVarShuffle256, + avx512vl_f64_info>, EVEX, VEX_W, NotMemoryFoldable; + +// expand +multiclass expand_by_vec_width opc, X86VectorVTInfo _, + string OpcodeStr, X86FoldableSchedWrite sched> { + defm rr : AVX512_maskable, AVX5128IBase, + Sched<[sched]>; + + defm rm : AVX512_maskable, + AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass expand_by_vec_width_lowering { + + def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, undef)), + (!cast(Name#_.ZSuffix##rmkz) + _.KRCWM:$mask, addr:$src)>; + + def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, _.ImmAllZerosV)), + (!cast(Name#_.ZSuffix##rmkz) + _.KRCWM:$mask, addr:$src)>; + + def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, + (_.VT _.RC:$src0))), + (!cast(Name#_.ZSuffix##rmk) + _.RC:$src0, _.KRCWM:$mask, addr:$src)>; +} + +multiclass expand_by_elt_width opc, string OpcodeStr, + X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTInfo, + Predicate Pred = HasAVX512> { + let Predicates = [Pred] in + defm Z : expand_by_vec_width, + expand_by_vec_width_lowering, EVEX_V512; + + let Predicates = [Pred, HasVLX] in { + defm Z256 : expand_by_vec_width, + expand_by_vec_width_lowering, EVEX_V256; + defm Z128 : expand_by_vec_width, + expand_by_vec_width_lowering, EVEX_V128; + } +} + +// FIXME: Is there a better scheduler class for VPEXPAND? +defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", WriteVarShuffle256, + avx512vl_i32_info>, EVEX; +defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", WriteVarShuffle256, + avx512vl_i64_info>, EVEX, VEX_W; +defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", WriteVarShuffle256, + avx512vl_f32_info>, EVEX; +defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", WriteVarShuffle256, + avx512vl_f64_info>, EVEX, VEX_W; + +//handle instruction reg_vec1 = op(reg_vec,imm) +// op(mem_vec,imm) +// op(broadcast(eltVt),imm) +//all instruction created with FROUND_CURRENT +multiclass avx512_unary_fp_packed_imm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable, Sched<[sched]>; + defm rmi : AVX512_maskable, + Sched<[sched.Folded, ReadAfterLd]>; + defm rmbi : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae} +multiclass avx512_unary_fp_sae_packed_imm opc, string OpcodeStr, + SDNode OpNode, X86FoldableSchedWrite sched, + X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm rrib : AVX512_maskable, + EVEX_B, Sched<[sched]>; +} + +multiclass avx512_common_unary_fp_sae_packed_imm opc, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, Predicate prd>{ + let Predicates = [prd] in { + defm Z : avx512_unary_fp_packed_imm, + avx512_unary_fp_sae_packed_imm, EVEX_V512; + } + let Predicates = [prd, HasVLX] in { + defm Z128 : avx512_unary_fp_packed_imm, EVEX_V128; + defm Z256 : avx512_unary_fp_packed_imm, EVEX_V256; + } +} + +//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm) +// op(reg_vec2,mem_vec,imm) +// op(reg_vec2,broadcast(eltVt),imm) +//all instruction created with FROUND_CURRENT +multiclass avx512_fp_packed_imm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _>{ + let ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable, + Sched<[sched]>; + defm rmi : AVX512_maskable, + Sched<[sched.Folded, ReadAfterLd]>; + defm rmbi : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm) +// op(reg_vec2,mem_vec,imm) +multiclass avx512_3Op_rm_imm8 opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo DestInfo, + X86VectorVTInfo SrcInfo>{ + let ExeDomain = DestInfo.ExeDomain in { + defm rri : AVX512_maskable, + Sched<[sched]>; + defm rmi : AVX512_maskable, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm) +// op(reg_vec2,mem_vec,imm) +// op(reg_vec2,broadcast(eltVt),imm) +multiclass avx512_3Op_imm8 opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _>: + avx512_3Op_rm_imm8{ + + let ExeDomain = _.ExeDomain in + defm rmbi : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +//handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm) +// op(reg_vec2,mem_scalar,imm) +multiclass avx512_fp_scalar_imm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable_scalar, + Sched<[sched]>; + defm rmi : AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae} +multiclass avx512_fp_sae_packed_imm opc, string OpcodeStr, + SDNode OpNode, X86FoldableSchedWrite sched, + X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm rrib : AVX512_maskable, + EVEX_B, Sched<[sched]>; +} + +//handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae} +multiclass avx512_fp_sae_scalar_imm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm NAME#rrib : AVX512_maskable_scalar, + EVEX_B, Sched<[sched]>; +} + +multiclass avx512_common_fp_sae_packed_imm opc, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, Predicate prd>{ + let Predicates = [prd] in { + defm Z : avx512_fp_packed_imm, + avx512_fp_sae_packed_imm, + EVEX_V512; + + } + let Predicates = [prd, HasVLX] in { + defm Z128 : avx512_fp_packed_imm, + EVEX_V128; + defm Z256 : avx512_fp_packed_imm, + EVEX_V256; + } +} + +multiclass avx512_common_3Op_rm_imm8 opc, SDNode OpNode, string OpStr, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo DestInfo, + AVX512VLVectorVTInfo SrcInfo, Predicate Pred = HasBWI> { + let Predicates = [Pred] in { + defm Z : avx512_3Op_rm_imm8, EVEX_V512, AVX512AIi8Base, EVEX_4V; + } + let Predicates = [Pred, HasVLX] in { + defm Z128 : avx512_3Op_rm_imm8, EVEX_V128, AVX512AIi8Base, EVEX_4V; + defm Z256 : avx512_3Op_rm_imm8, EVEX_V256, AVX512AIi8Base, EVEX_4V; + } +} + +multiclass avx512_common_3Op_imm8 opc, SDNode OpNode, X86SchedWriteWidths sched, + Predicate Pred = HasAVX512> { + let Predicates = [Pred] in { + defm Z : avx512_3Op_imm8, + EVEX_V512; + } + let Predicates = [Pred, HasVLX] in { + defm Z128 : avx512_3Op_imm8, + EVEX_V128; + defm Z256 : avx512_3Op_imm8, + EVEX_V256; + } +} + +multiclass avx512_common_fp_sae_scalar_imm opc, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, Predicate prd> { + let Predicates = [prd] in { + defm Z : avx512_fp_scalar_imm, + avx512_fp_sae_scalar_imm; + } +} + +multiclass avx512_common_unary_fp_sae_packed_imm_all opcPs, bits<8> opcPd, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, Predicate prd>{ + defm PS : avx512_common_unary_fp_sae_packed_imm, + EVEX_CD8<32, CD8VF>; + defm PD : avx512_common_unary_fp_sae_packed_imm, + EVEX_CD8<64, CD8VF>, VEX_W; +} + +defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56, + X86VReduce, X86VReduceRnd, SchedWriteFRnd, HasDQI>, + AVX512AIi8Base, EVEX; +defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09, + X86VRndScale, X86VRndScaleRnd, SchedWriteFRnd, HasAVX512>, + AVX512AIi8Base, EVEX; +defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26, + X86VGetMant, X86VGetMantRnd, SchedWriteFRnd, HasAVX512>, + AVX512AIi8Base, EVEX; + +defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info, + 0x50, X86VRange, X86VRangeRnd, + SchedWriteFAdd, HasDQI>, + AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; +defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info, + 0x50, X86VRange, X86VRangeRnd, + SchedWriteFAdd, HasDQI>, + AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; + +defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", + f64x_info, 0x51, X86Ranges, X86RangesRnd, SchedWriteFAdd, HasDQI>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; +defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info, + 0x51, X86Ranges, X86RangesRnd, SchedWriteFAdd, HasDQI>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; + +defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info, + 0x57, X86Reduces, X86ReducesRnd, SchedWriteFRnd, HasDQI>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; +defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info, + 0x57, X86Reduces, X86ReducesRnd, SchedWriteFRnd, HasDQI>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; + +defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info, + 0x27, X86GetMants, X86GetMantsRnd, SchedWriteFRnd, HasAVX512>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; +defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info, + 0x27, X86GetMants, X86GetMantsRnd, SchedWriteFRnd, HasAVX512>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; + + +multiclass AVX512_rndscale_lowering { + // Register + def : Pat<(_.VT (ffloor _.RC:$src)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rri") + _.RC:$src, (i32 0x9))>; + def : Pat<(_.VT (fnearbyint _.RC:$src)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rri") + _.RC:$src, (i32 0xC))>; + def : Pat<(_.VT (fceil _.RC:$src)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rri") + _.RC:$src, (i32 0xA))>; + def : Pat<(_.VT (frint _.RC:$src)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rri") + _.RC:$src, (i32 0x4))>; + def : Pat<(_.VT (ftrunc _.RC:$src)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rri") + _.RC:$src, (i32 0xB))>; + + // Merge-masking + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ffloor _.RC:$src), _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrik") + _.RC:$dst, _.KRCWM:$mask, _.RC:$src, (i32 0x9))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fnearbyint _.RC:$src), _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrik") + _.RC:$dst, _.KRCWM:$mask, _.RC:$src, (i32 0xC))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fceil _.RC:$src), _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrik") + _.RC:$dst, _.KRCWM:$mask, _.RC:$src, (i32 0xA))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (frint _.RC:$src), _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrik") + _.RC:$dst, _.KRCWM:$mask, _.RC:$src, (i32 0x4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ftrunc _.RC:$src), _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrik") + _.RC:$dst, _.KRCWM:$mask, _.RC:$src, (i32 0xB))>; + + // Zero-masking + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ffloor _.RC:$src), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrikz") + _.KRCWM:$mask, _.RC:$src, (i32 0x9))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fnearbyint _.RC:$src), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrikz") + _.KRCWM:$mask, _.RC:$src, (i32 0xC))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fceil _.RC:$src), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrikz") + _.KRCWM:$mask, _.RC:$src, (i32 0xA))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (frint _.RC:$src), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrikz") + _.KRCWM:$mask, _.RC:$src, (i32 0x4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ftrunc _.RC:$src), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrikz") + _.KRCWM:$mask, _.RC:$src, (i32 0xB))>; + + // Load + def : Pat<(_.VT (ffloor (_.LdFrag addr:$src))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmi") + addr:$src, (i32 0x9))>; + def : Pat<(_.VT (fnearbyint (_.LdFrag addr:$src))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmi") + addr:$src, (i32 0xC))>; + def : Pat<(_.VT (fceil (_.LdFrag addr:$src))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmi") + addr:$src, (i32 0xA))>; + def : Pat<(_.VT (frint (_.LdFrag addr:$src))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmi") + addr:$src, (i32 0x4))>; + def : Pat<(_.VT (ftrunc (_.LdFrag addr:$src))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmi") + addr:$src, (i32 0xB))>; + + // Merge-masking + load + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ffloor (_.LdFrag addr:$src)), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0x9))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fnearbyint (_.LdFrag addr:$src)), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0xC))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fceil (_.LdFrag addr:$src)), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0xA))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (frint (_.LdFrag addr:$src)), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0x4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ftrunc (_.LdFrag addr:$src)), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0xB))>; + + // Zero-masking + load + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ffloor (_.LdFrag addr:$src)), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmikz") + _.KRCWM:$mask, addr:$src, (i32 0x9))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fnearbyint (_.LdFrag addr:$src)), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmikz") + _.KRCWM:$mask, addr:$src, (i32 0xC))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fceil (_.LdFrag addr:$src)), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmikz") + _.KRCWM:$mask, addr:$src, (i32 0xA))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (frint (_.LdFrag addr:$src)), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmikz") + _.KRCWM:$mask, addr:$src, (i32 0x4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ftrunc (_.LdFrag addr:$src)), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmikz") + _.KRCWM:$mask, addr:$src, (i32 0xB))>; + + // Broadcast load + def : Pat<(_.VT (ffloor (X86VBroadcast (_.ScalarLdFrag addr:$src)))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbi") + addr:$src, (i32 0x9))>; + def : Pat<(_.VT (fnearbyint (X86VBroadcast (_.ScalarLdFrag addr:$src)))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbi") + addr:$src, (i32 0xC))>; + def : Pat<(_.VT (fceil (X86VBroadcast (_.ScalarLdFrag addr:$src)))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbi") + addr:$src, (i32 0xA))>; + def : Pat<(_.VT (frint (X86VBroadcast (_.ScalarLdFrag addr:$src)))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbi") + addr:$src, (i32 0x4))>; + def : Pat<(_.VT (ftrunc (X86VBroadcast (_.ScalarLdFrag addr:$src)))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbi") + addr:$src, (i32 0xB))>; + + // Merge-masking + broadcast load + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (ffloor (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0x9))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (fnearbyint (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0xC))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (fceil (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0xA))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (frint (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0x4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (ftrunc (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0xB))>; + + // Zero-masking + broadcast load + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (ffloor (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbikz") + _.KRCWM:$mask, addr:$src, (i32 0x9))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (fnearbyint (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbikz") + _.KRCWM:$mask, addr:$src, (i32 0xC))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (fceil (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbikz") + _.KRCWM:$mask, addr:$src, (i32 0xA))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (frint (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbikz") + _.KRCWM:$mask, addr:$src, (i32 0x4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (ftrunc (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbikz") + _.KRCWM:$mask, addr:$src, (i32 0xB))>; +} + +let Predicates = [HasAVX512] in { + defm : AVX512_rndscale_lowering; + defm : AVX512_rndscale_lowering; +} + +let Predicates = [HasVLX] in { + defm : AVX512_rndscale_lowering; + defm : AVX512_rndscale_lowering; + defm : AVX512_rndscale_lowering; + defm : AVX512_rndscale_lowering; +} + +multiclass avx512_shuff_packed_128_common opc, string OpcodeStr, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, + X86VectorVTInfo CastInfo, + string EVEX2VEXOvrd> { + let ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable, + Sched<[sched]>, EVEX2VEXOverride; + defm rmi : AVX512_maskable, + Sched<[sched.Folded, ReadAfterLd]>, + EVEX2VEXOverride; + defm rmbi : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_shuff_packed_128 opc, + string EVEX2VEXOvrd>{ + let Predicates = [HasAVX512] in + defm Z : avx512_shuff_packed_128_common, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in + defm Z256 : avx512_shuff_packed_128_common, EVEX_V256; +} + +defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4", WriteFShuffle256, + avx512vl_f32_info, avx512vl_f64_info, 0x23, "VPERM2F128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; +defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2", WriteFShuffle256, + avx512vl_f64_info, avx512vl_f64_info, 0x23, "VPERM2F128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; +defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4", WriteFShuffle256, + avx512vl_i32_info, avx512vl_i64_info, 0x43, "VPERM2I128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; +defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2", WriteFShuffle256, + avx512vl_i64_info, avx512vl_i64_info, 0x43, "VPERM2I128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; + +let Predicates = [HasAVX512] in { +// Provide fallback in case the load node that is used in the broadcast +// patterns above is used by additional users, which prevents the pattern +// selection. +def : Pat<(v8f64 (X86SubVBroadcast (v2f64 VR128X:$src))), + (VSHUFF64X2Zrri (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + 0)>; +def : Pat<(v8i64 (X86SubVBroadcast (v2i64 VR128X:$src))), + (VSHUFI64X2Zrri (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + 0)>; + +def : Pat<(v16f32 (X86SubVBroadcast (v4f32 VR128X:$src))), + (VSHUFF32X4Zrri (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + 0)>; +def : Pat<(v16i32 (X86SubVBroadcast (v4i32 VR128X:$src))), + (VSHUFI32X4Zrri (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + 0)>; + +def : Pat<(v32i16 (X86SubVBroadcast (v8i16 VR128X:$src))), + (VSHUFI32X4Zrri (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + 0)>; + +def : Pat<(v64i8 (X86SubVBroadcast (v16i8 VR128X:$src))), + (VSHUFI32X4Zrri (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + 0)>; +} + +multiclass avx512_valign opc, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _>{ + // NOTE: EVEX2VEXOverride changed back to Unset for 256-bit at the + // instantiation of this class. + let ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable, + Sched<[sched]>, EVEX2VEXOverride<"VPALIGNRrri">; + defm rmi : AVX512_maskable, + Sched<[sched.Folded, ReadAfterLd]>, + EVEX2VEXOverride<"VPALIGNRrmi">; + + defm rmbi : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_valign_common { + let Predicates = [HasAVX512] in { + defm Z : avx512_valign<0x03, OpcodeStr, sched.ZMM, _.info512>, + AVX512AIi8Base, EVEX_4V, EVEX_V512; + } + let Predicates = [HasAVX512, HasVLX] in { + defm Z128 : avx512_valign<0x03, OpcodeStr, sched.XMM, _.info128>, + AVX512AIi8Base, EVEX_4V, EVEX_V128; + // We can't really override the 256-bit version so change it back to unset. + let EVEX2VEXOverride = ? in + defm Z256 : avx512_valign<0x03, OpcodeStr, sched.YMM, _.info256>, + AVX512AIi8Base, EVEX_4V, EVEX_V256; + } +} + +defm VALIGND: avx512_valign_common<"valignd", SchedWriteShuffle, + avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; +defm VALIGNQ: avx512_valign_common<"valignq", SchedWriteShuffle, + avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, + VEX_W; + +defm VPALIGNR: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr", + SchedWriteShuffle, avx512vl_i8_info, + avx512vl_i8_info>, EVEX_CD8<8, CD8VF>; + +// Fragments to help convert valignq into masked valignd. Or valignq/valignd +// into vpalignr. +def ValignqImm32XForm : SDNodeXFormgetZExtValue() * 2, SDLoc(N)); +}]>; +def ValignqImm8XForm : SDNodeXFormgetZExtValue() * 8, SDLoc(N)); +}]>; +def ValigndImm8XForm : SDNodeXFormgetZExtValue() * 4, SDLoc(N)); +}]>; + +multiclass avx512_vpalign_mask_lowering { + def : Pat<(To.VT (vselect To.KRCWM:$mask, + (bitconvert + (From.VT (OpNode From.RC:$src1, From.RC:$src2, + imm:$src3))), + To.RC:$src0)), + (!cast(OpcodeStr#"rrik") To.RC:$src0, To.KRCWM:$mask, + To.RC:$src1, To.RC:$src2, + (ImmXForm imm:$src3))>; + + def : Pat<(To.VT (vselect To.KRCWM:$mask, + (bitconvert + (From.VT (OpNode From.RC:$src1, From.RC:$src2, + imm:$src3))), + To.ImmAllZerosV)), + (!cast(OpcodeStr#"rrikz") To.KRCWM:$mask, + To.RC:$src1, To.RC:$src2, + (ImmXForm imm:$src3))>; + + def : Pat<(To.VT (vselect To.KRCWM:$mask, + (bitconvert + (From.VT (OpNode From.RC:$src1, + (bitconvert (To.LdFrag addr:$src2)), + imm:$src3))), + To.RC:$src0)), + (!cast(OpcodeStr#"rmik") To.RC:$src0, To.KRCWM:$mask, + To.RC:$src1, addr:$src2, + (ImmXForm imm:$src3))>; + + def : Pat<(To.VT (vselect To.KRCWM:$mask, + (bitconvert + (From.VT (OpNode From.RC:$src1, + (bitconvert (To.LdFrag addr:$src2)), + imm:$src3))), + To.ImmAllZerosV)), + (!cast(OpcodeStr#"rmikz") To.KRCWM:$mask, + To.RC:$src1, addr:$src2, + (ImmXForm imm:$src3))>; +} + +multiclass avx512_vpalign_mask_lowering_mb : + avx512_vpalign_mask_lowering { + def : Pat<(From.VT (OpNode From.RC:$src1, + (bitconvert (To.VT (X86VBroadcast + (To.ScalarLdFrag addr:$src2)))), + imm:$src3)), + (!cast(OpcodeStr#"rmbi") To.RC:$src1, addr:$src2, + (ImmXForm imm:$src3))>; + + def : Pat<(To.VT (vselect To.KRCWM:$mask, + (bitconvert + (From.VT (OpNode From.RC:$src1, + (bitconvert + (To.VT (X86VBroadcast + (To.ScalarLdFrag addr:$src2)))), + imm:$src3))), + To.RC:$src0)), + (!cast(OpcodeStr#"rmbik") To.RC:$src0, To.KRCWM:$mask, + To.RC:$src1, addr:$src2, + (ImmXForm imm:$src3))>; + + def : Pat<(To.VT (vselect To.KRCWM:$mask, + (bitconvert + (From.VT (OpNode From.RC:$src1, + (bitconvert + (To.VT (X86VBroadcast + (To.ScalarLdFrag addr:$src2)))), + imm:$src3))), + To.ImmAllZerosV)), + (!cast(OpcodeStr#"rmbikz") To.KRCWM:$mask, + To.RC:$src1, addr:$src2, + (ImmXForm imm:$src3))>; +} + +let Predicates = [HasAVX512] in { + // For 512-bit we lower to the widest element type we can. So we only need + // to handle converting valignq to valignd. + defm : avx512_vpalign_mask_lowering_mb<"VALIGNDZ", X86VAlign, v8i64_info, + v16i32_info, ValignqImm32XForm>; +} + +let Predicates = [HasVLX] in { + // For 128-bit we lower to the widest element type we can. So we only need + // to handle converting valignq to valignd. + defm : avx512_vpalign_mask_lowering_mb<"VALIGNDZ128", X86VAlign, v2i64x_info, + v4i32x_info, ValignqImm32XForm>; + // For 256-bit we lower to the widest element type we can. So we only need + // to handle converting valignq to valignd. + defm : avx512_vpalign_mask_lowering_mb<"VALIGNDZ256", X86VAlign, v4i64x_info, + v8i32x_info, ValignqImm32XForm>; +} + +let Predicates = [HasVLX, HasBWI] in { + // We can turn 128 and 256 bit VALIGND/VALIGNQ into VPALIGNR. + defm : avx512_vpalign_mask_lowering<"VPALIGNRZ128", X86VAlign, v2i64x_info, + v16i8x_info, ValignqImm8XForm>; + defm : avx512_vpalign_mask_lowering<"VPALIGNRZ128", X86VAlign, v4i32x_info, + v16i8x_info, ValigndImm8XForm>; +} + +defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw", + SchedWritePSADBW, avx512vl_i16_info, avx512vl_i8_info>, + EVEX_CD8<8, CD8VF>, NotEVEX2VEXConvertible; + +multiclass avx512_unary_rm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rr : AVX512_maskable, EVEX, AVX5128IBase, + Sched<[sched]>; + + defm rm : AVX512_maskable, + EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded]>; + } +} + +multiclass avx512_unary_rmb opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> : + avx512_unary_rm { + defm rmb : AVX512_maskable, + EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded]>; +} + +multiclass avx512_unary_rm_vl opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo, Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_unary_rm, + EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_unary_rm, + EVEX_V256; + defm Z128 : avx512_unary_rm, + EVEX_V128; + } +} + +multiclass avx512_unary_rmb_vl opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo VTInfo, + Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_unary_rmb, + EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_unary_rmb, + EVEX_V256; + defm Z128 : avx512_unary_rmb, + EVEX_V128; + } +} + +multiclass avx512_unary_rm_vl_dq opc_d, bits<8> opc_q, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched, + Predicate prd> { + defm Q : avx512_unary_rmb_vl, VEX_W; + defm D : avx512_unary_rmb_vl; +} + +multiclass avx512_unary_rm_vl_bw opc_b, bits<8> opc_w, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched, + Predicate prd> { + defm W : avx512_unary_rm_vl, VEX_WIG; + defm B : avx512_unary_rm_vl, VEX_WIG; +} + +multiclass avx512_unary_rm_vl_all opc_b, bits<8> opc_w, + bits<8> opc_d, bits<8> opc_q, + string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + defm NAME : avx512_unary_rm_vl_dq, + avx512_unary_rm_vl_bw; +} + +defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", abs, + SchedWriteVecALU>; + +// VPABS: Use 512bit version to implement 128/256 bit in case NoVLX. +let Predicates = [HasAVX512, NoVLX] in { + def : Pat<(v4i64 (abs VR256X:$src)), + (EXTRACT_SUBREG + (VPABSQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)), + sub_ymm)>; + def : Pat<(v2i64 (abs VR128X:$src)), + (EXTRACT_SUBREG + (VPABSQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)), + sub_xmm)>; +} + +// Use 512bit version to implement 128/256 bit. +multiclass avx512_unary_lowering { + let Predicates = [prd, NoVLX] in { + def : Pat<(_.info256.VT(OpNode _.info256.RC:$src1)), + (EXTRACT_SUBREG + (!cast(InstrStr # "Zrr") + (INSERT_SUBREG(_.info512.VT(IMPLICIT_DEF)), + _.info256.RC:$src1, + _.info256.SubRegIdx)), + _.info256.SubRegIdx)>; + + def : Pat<(_.info128.VT(OpNode _.info128.RC:$src1)), + (EXTRACT_SUBREG + (!cast(InstrStr # "Zrr") + (INSERT_SUBREG(_.info512.VT(IMPLICIT_DEF)), + _.info128.RC:$src1, + _.info128.SubRegIdx)), + _.info128.SubRegIdx)>; + } +} + +defm VPLZCNT : avx512_unary_rm_vl_dq<0x44, 0x44, "vplzcnt", ctlz, + SchedWriteVecIMul, HasCDI>; + +// FIXME: Is there a better scheduler class for VPCONFLICT? +defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, + SchedWriteVecALU, HasCDI>; + +// VPLZCNT: Use 512bit version to implement 128/256 bit in case NoVLX. +defm : avx512_unary_lowering<"VPLZCNTQ", ctlz, avx512vl_i64_info, HasCDI>; +defm : avx512_unary_lowering<"VPLZCNTD", ctlz, avx512vl_i32_info, HasCDI>; + +//===---------------------------------------------------------------------===// +// Counts number of ones - VPOPCNTD and VPOPCNTQ +//===---------------------------------------------------------------------===// + +// FIXME: Is there a better scheduler class for VPOPCNTD/VPOPCNTQ? +defm VPOPCNT : avx512_unary_rm_vl_dq<0x55, 0x55, "vpopcnt", ctpop, + SchedWriteVecALU, HasVPOPCNTDQ>; + +defm : avx512_unary_lowering<"VPOPCNTQ", ctpop, avx512vl_i64_info, HasVPOPCNTDQ>; +defm : avx512_unary_lowering<"VPOPCNTD", ctpop, avx512vl_i32_info, HasVPOPCNTDQ>; + +//===---------------------------------------------------------------------===// +// Replicate Single FP - MOVSHDUP and MOVSLDUP +//===---------------------------------------------------------------------===// + +multiclass avx512_replicate opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + defm NAME: avx512_unary_rm_vl, XS; +} + +defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup, + SchedWriteFShuffle>; +defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup, + SchedWriteFShuffle>; + +//===----------------------------------------------------------------------===// +// AVX-512 - MOVDDUP +//===----------------------------------------------------------------------===// + +multiclass avx512_movddup_128 opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rr : AVX512_maskable, EVEX, + Sched<[sched]>; + defm rm : AVX512_maskable, + EVEX, EVEX_CD8<_.EltSize, CD8VH>, + Sched<[sched.Folded]>; + } +} + +multiclass avx512_movddup_common opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo VTInfo> { + defm Z : avx512_unary_rm, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in { + defm Z256 : avx512_unary_rm, EVEX_V256; + defm Z128 : avx512_movddup_128, EVEX_V128; + } +} + +multiclass avx512_movddup opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + defm NAME: avx512_movddup_common, XD, VEX_W; +} + +defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", X86Movddup, SchedWriteFShuffle>; + +let Predicates = [HasVLX] in { +def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))), + (VMOVDDUPZ128rm addr:$src)>; +def : Pat<(v2f64 (X86VBroadcast f64:$src)), + (VMOVDDUPZ128rr (v2f64 (COPY_TO_REGCLASS FR64X:$src, VR128X)))>; +def : Pat<(v2f64 (X86VBroadcast (loadv2f64 addr:$src))), + (VMOVDDUPZ128rm addr:$src)>; + +def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast f64:$src)), + (v2f64 VR128X:$src0)), + (VMOVDDUPZ128rrk VR128X:$src0, VK2WM:$mask, + (v2f64 (COPY_TO_REGCLASS FR64X:$src, VR128X)))>; +def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast f64:$src)), + (bitconvert (v4i32 immAllZerosV))), + (VMOVDDUPZ128rrkz VK2WM:$mask, (v2f64 (COPY_TO_REGCLASS FR64X:$src, VR128X)))>; + +def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadf64 addr:$src))), + (v2f64 VR128X:$src0)), + (VMOVDDUPZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>; +def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadf64 addr:$src))), + (bitconvert (v4i32 immAllZerosV))), + (VMOVDDUPZ128rmkz VK2WM:$mask, addr:$src)>; + +def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadv2f64 addr:$src))), + (v2f64 VR128X:$src0)), + (VMOVDDUPZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>; +def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadv2f64 addr:$src))), + (bitconvert (v4i32 immAllZerosV))), + (VMOVDDUPZ128rmkz VK2WM:$mask, addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 - Unpack Instructions +//===----------------------------------------------------------------------===// + +defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh, HasAVX512, + SchedWriteFShuffleSizes, 0, 1>; +defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl, HasAVX512, + SchedWriteFShuffleSizes>; + +defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl, + SchedWriteShuffle, HasBWI>; +defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh, + SchedWriteShuffle, HasBWI>; +defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl, + SchedWriteShuffle, HasBWI>; +defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh, + SchedWriteShuffle, HasBWI>; + +defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl, + SchedWriteShuffle, HasAVX512>; +defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh, + SchedWriteShuffle, HasAVX512>; +defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl, + SchedWriteShuffle, HasAVX512>; +defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh, + SchedWriteShuffle, HasAVX512>; + +//===----------------------------------------------------------------------===// +// AVX-512 - Extract & Insert Integer Instructions +//===----------------------------------------------------------------------===// + +multiclass avx512_extract_elt_bw_m opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _> { + def mr : AVX512Ii8, + EVEX, EVEX_CD8<_.EltSize, CD8VT1>, Sched<[WriteVecExtractSt]>; +} + +multiclass avx512_extract_elt_b { + let Predicates = [HasBWI] in { + def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst), + (ins _.RC:$src1, u8imm:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32orGR64:$dst, + (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>, + EVEX, TAPD, Sched<[WriteVecExtract]>; + + defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD; + } +} + +multiclass avx512_extract_elt_w { + let Predicates = [HasBWI] in { + def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst), + (ins _.RC:$src1, u8imm:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32orGR64:$dst, + (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>, + EVEX, PD, Sched<[WriteVecExtract]>; + + let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in + def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst), + (ins _.RC:$src1, u8imm:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + EVEX, TAPD, FoldGenData, + Sched<[WriteVecExtract]>; + + defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD; + } +} + +multiclass avx512_extract_elt_dq { + let Predicates = [HasDQI] in { + def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst), + (ins _.RC:$src1, u8imm:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GRC:$dst, + (extractelt (_.VT _.RC:$src1), imm:$src2))]>, + EVEX, TAPD, Sched<[WriteVecExtract]>; + + def mr : AVX512Ii8<0x16, MRMDestMem, (outs), + (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(store (extractelt (_.VT _.RC:$src1), + imm:$src2),addr:$dst)]>, + EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD, + Sched<[WriteVecExtractSt]>; + } +} + +defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>, VEX_WIG; +defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>, VEX_WIG; +defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>; +defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W; + +multiclass avx512_insert_elt_m opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _, PatFrag LdFrag> { + def rm : AVX512Ii8, + EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>, Sched<[WriteVecInsertLd, ReadAfterLd]>; +} + +multiclass avx512_insert_elt_bw opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _, PatFrag LdFrag> { + let Predicates = [HasBWI] in { + def rr : AVX512Ii8, EVEX_4V, + Sched<[WriteVecInsert]>; + + defm NAME : avx512_insert_elt_m; + } +} + +multiclass avx512_insert_elt_dq opc, string OpcodeStr, + X86VectorVTInfo _, RegisterClass GRC> { + let Predicates = [HasDQI] in { + def rr : AVX512Ii8, + EVEX_4V, TAPD, Sched<[WriteVecInsert]>; + + defm NAME : avx512_insert_elt_m, TAPD; + } +} + +defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info, + extloadi8>, TAPD, VEX_WIG; +defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info, + extloadi16>, PD, VEX_WIG; +defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>; +defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W; + +//===----------------------------------------------------------------------===// +// VSHUFPS - VSHUFPD Operations +//===----------------------------------------------------------------------===// + +multiclass avx512_shufp{ + defm NAME: avx512_common_3Op_imm8, + EVEX_CD8, + AVX512AIi8Base, EVEX_4V; +} + +defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS; +defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W; + +//===----------------------------------------------------------------------===// +// AVX-512 - Byte shift Left/Right +//===----------------------------------------------------------------------===// + +// FIXME: The SSE/AVX names are PSLLDQri etc. - should we add the i here as well? +multiclass avx512_shift_packed opc, SDNode OpNode, Format MRMr, + Format MRMm, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _>{ + def rr : AVX512, + Sched<[sched]>; + def rm : AVX512, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_shift_packed_all opc, SDNode OpNode, Format MRMr, + Format MRMm, string OpcodeStr, + X86SchedWriteWidths sched, Predicate prd>{ + let Predicates = [prd] in + defm Z : avx512_shift_packed, EVEX_V512; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_shift_packed, EVEX_V256; + defm Z128 : avx512_shift_packed, EVEX_V128; + } +} +defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq", + SchedWriteShuffle, HasBWI>, + AVX512PDIi8Base, EVEX_4V, VEX_WIG; +defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq", + SchedWriteShuffle, HasBWI>, + AVX512PDIi8Base, EVEX_4V, VEX_WIG; + +multiclass avx512_psadbw_packed opc, SDNode OpNode, + string OpcodeStr, X86FoldableSchedWrite sched, + X86VectorVTInfo _dst, X86VectorVTInfo _src> { + def rr : AVX512BI, + Sched<[sched]>; + def rm : AVX512BI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_psadbw_packed_all opc, SDNode OpNode, + string OpcodeStr, X86SchedWriteWidths sched, + Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_psadbw_packed, EVEX_V512; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_psadbw_packed, EVEX_V256; + defm Z128 : avx512_psadbw_packed, EVEX_V128; + } +} + +defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw", + SchedWritePSADBW, HasBWI>, EVEX_4V, VEX_WIG; + +// Transforms to swizzle an immediate to enable better matching when +// memory operand isn't in the right place. +def VPTERNLOG321_imm8 : SDNodeXFormgetZExtValue(); + // Swap bits 1/4 and 3/6. + uint8_t NewImm = Imm & 0xa5; + if (Imm & 0x02) NewImm |= 0x10; + if (Imm & 0x10) NewImm |= 0x02; + if (Imm & 0x08) NewImm |= 0x40; + if (Imm & 0x40) NewImm |= 0x08; + return getI8Imm(NewImm, SDLoc(N)); +}]>; +def VPTERNLOG213_imm8 : SDNodeXFormgetZExtValue(); + // Swap bits 2/4 and 3/5. + uint8_t NewImm = Imm & 0xc3; + if (Imm & 0x04) NewImm |= 0x10; + if (Imm & 0x10) NewImm |= 0x04; + if (Imm & 0x08) NewImm |= 0x20; + if (Imm & 0x20) NewImm |= 0x08; + return getI8Imm(NewImm, SDLoc(N)); +}]>; +def VPTERNLOG132_imm8 : SDNodeXFormgetZExtValue(); + // Swap bits 1/2 and 5/6. + uint8_t NewImm = Imm & 0x99; + if (Imm & 0x02) NewImm |= 0x04; + if (Imm & 0x04) NewImm |= 0x02; + if (Imm & 0x20) NewImm |= 0x40; + if (Imm & 0x40) NewImm |= 0x20; + return getI8Imm(NewImm, SDLoc(N)); +}]>; +def VPTERNLOG231_imm8 : SDNodeXFormgetZExtValue(); + // Move bits 1->2, 2->4, 3->6, 4->1, 5->3, 6->5 + uint8_t NewImm = Imm & 0x81; + if (Imm & 0x02) NewImm |= 0x04; + if (Imm & 0x04) NewImm |= 0x10; + if (Imm & 0x08) NewImm |= 0x40; + if (Imm & 0x10) NewImm |= 0x02; + if (Imm & 0x20) NewImm |= 0x08; + if (Imm & 0x40) NewImm |= 0x20; + return getI8Imm(NewImm, SDLoc(N)); +}]>; +def VPTERNLOG312_imm8 : SDNodeXFormgetZExtValue(); + // Move bits 1->4, 2->1, 3->5, 4->2, 5->6, 6->3 + uint8_t NewImm = Imm & 0x81; + if (Imm & 0x02) NewImm |= 0x10; + if (Imm & 0x04) NewImm |= 0x02; + if (Imm & 0x08) NewImm |= 0x20; + if (Imm & 0x10) NewImm |= 0x04; + if (Imm & 0x20) NewImm |= 0x40; + if (Imm & 0x40) NewImm |= 0x08; + return getI8Imm(NewImm, SDLoc(N)); +}]>; + +multiclass avx512_ternlog opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + string Name>{ + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable_3src, + AVX512AIi8Base, EVEX_4V, Sched<[sched]>; + defm rmi : AVX512_maskable_3src, + AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + defm rmbi : AVX512_maskable_3src, EVEX_B, + AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + }// Constraints = "$src1 = $dst" + + // Additional patterns for matching passthru operand in other positions. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src3, _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, _.RC:$src3, (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, _.RC:$src3, (VPTERNLOG213_imm8 imm:$src4))>; + + // Additional patterns for matching loads in other positions. + def : Pat<(_.VT (OpNode (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src2, _.RC:$src1, (i8 imm:$src4))), + (!cast(Name#_.ZSuffix#rmi) _.RC:$src1, _.RC:$src2, + addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (OpNode _.RC:$src1, + (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src2, (i8 imm:$src4))), + (!cast(Name#_.ZSuffix#rmi) _.RC:$src1, _.RC:$src2, + addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; + + // Additional patterns for matching zero masking with loads in other + // positions. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), + _.ImmAllZerosV)), + (!cast(Name#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src2, (i8 imm:$src4)), + _.ImmAllZerosV)), + (!cast(Name#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; + + // Additional patterns for matching masked loads with different + // operand orders. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src2, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src2, _.RC:$src1, + (bitconvert (_.LdFrag addr:$src3)), (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG213_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src2, (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src1, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG231_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src1, _.RC:$src2, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG312_imm8 imm:$src4))>; + + // Additional patterns for matching broadcasts in other positions. + def : Pat<(_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src2, _.RC:$src1, (i8 imm:$src4))), + (!cast(Name#_.ZSuffix#rmbi) _.RC:$src1, _.RC:$src2, + addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (OpNode _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src2, (i8 imm:$src4))), + (!cast(Name#_.ZSuffix#rmbi) _.RC:$src1, _.RC:$src2, + addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; + + // Additional patterns for matching zero masking with broadcasts in other + // positions. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), + _.ImmAllZerosV)), + (!cast(Name#_.ZSuffix#rmbikz) _.RC:$src1, + _.KRCWM:$mask, _.RC:$src2, addr:$src3, + (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src2, (i8 imm:$src4)), + _.ImmAllZerosV)), + (!cast(Name#_.ZSuffix#rmbikz) _.RC:$src1, + _.KRCWM:$mask, _.RC:$src2, addr:$src3, + (VPTERNLOG132_imm8 imm:$src4))>; + + // Additional patterns for matching masked broadcasts with different + // operand orders. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src2, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src2, _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + (i8 imm:$src4)), _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG213_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src2, + (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src1, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG231_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src1, _.RC:$src2, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG312_imm8 imm:$src4))>; +} + +multiclass avx512_common_ternlog { + let Predicates = [HasAVX512] in + defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, sched.ZMM, + _.info512, NAME>, EVEX_V512; + let Predicates = [HasAVX512, HasVLX] in { + defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, sched.XMM, + _.info128, NAME>, EVEX_V128; + defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, sched.YMM, + _.info256, NAME>, EVEX_V256; + } +} + +defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", SchedWriteVecALU, + avx512vl_i32_info>; +defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", SchedWriteVecALU, + avx512vl_i64_info>, VEX_W; + +// Patterns to implement vnot using vpternlog instead of creating all ones +// using pcmpeq or vpternlog and then xoring with that. The value 15 is chosen +// so that the result is only dependent on src0. But we use the same source +// for all operands to prevent a false dependency. +// TODO: We should maybe have a more generalized algorithm for folding to +// vpternlog. +let Predicates = [HasAVX512] in { + def : Pat<(v8i64 (xor VR512:$src, (bc_v8i64 (v16i32 immAllOnesV)))), + (VPTERNLOGQZrri VR512:$src, VR512:$src, VR512:$src, (i8 15))>; +} + +let Predicates = [HasAVX512, NoVLX] in { + def : Pat<(v2i64 (xor VR128X:$src, (bc_v2i64 (v4i32 immAllOnesV)))), + (EXTRACT_SUBREG + (VPTERNLOGQZrri + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (i8 15)), sub_xmm)>; + def : Pat<(v4i64 (xor VR256X:$src, (bc_v4i64 (v8i32 immAllOnesV)))), + (EXTRACT_SUBREG + (VPTERNLOGQZrri + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (i8 15)), sub_ymm)>; +} + +let Predicates = [HasVLX] in { + def : Pat<(v2i64 (xor VR128X:$src, (bc_v2i64 (v4i32 immAllOnesV)))), + (VPTERNLOGQZ128rri VR128X:$src, VR128X:$src, VR128X:$src, (i8 15))>; + def : Pat<(v4i64 (xor VR256X:$src, (bc_v4i64 (v8i32 immAllOnesV)))), + (VPTERNLOGQZ256rri VR256X:$src, VR256X:$src, VR256X:$src, (i8 15))>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 - FixupImm +//===----------------------------------------------------------------------===// + +multiclass avx512_fixupimm_packed opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + X86VectorVTInfo TblVT>{ + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable_3src, Sched<[sched]>; + defm rmi : AVX512_maskable_3src, + Sched<[sched.Folded, ReadAfterLd]>; + defm rmbi : AVX512_maskable_3src, + EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } // Constraints = "$src1 = $dst" +} + +multiclass avx512_fixupimm_packed_sae opc, string OpcodeStr, + SDNode OpNode, X86FoldableSchedWrite sched, + X86VectorVTInfo _, X86VectorVTInfo TblVT>{ +let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { + defm rrib : AVX512_maskable_3src, + EVEX_B, Sched<[sched]>; + } +} + +multiclass avx512_fixupimm_scalar opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + X86VectorVTInfo _src3VT> { + let Constraints = "$src1 = $dst" , Predicates = [HasAVX512], + ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable_3src_scalar, Sched<[sched]>; + defm rrib : AVX512_maskable_3src_scalar, + EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + defm rmi : AVX512_maskable_3src_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fixupimm_packed_all { + let Predicates = [HasAVX512] in + defm Z : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, sched.ZMM, + _Vec.info512, _Tbl.info512>, + avx512_fixupimm_packed_sae<0x54, "vfixupimm", X86VFixupimm, sched.ZMM, + _Vec.info512, _Tbl.info512>, AVX512AIi8Base, + EVEX_4V, EVEX_V512; + let Predicates = [HasAVX512, HasVLX] in { + defm Z128 : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, sched.XMM, + _Vec.info128, _Tbl.info128>, AVX512AIi8Base, + EVEX_4V, EVEX_V128; + defm Z256 : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, sched.YMM, + _Vec.info256, _Tbl.info256>, AVX512AIi8Base, + EVEX_4V, EVEX_V256; + } +} + +defm VFIXUPIMMSSZ : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar, + SchedWriteFAdd.Scl, f32x_info, v4i32x_info>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; +defm VFIXUPIMMSDZ : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar, + SchedWriteFAdd.Scl, f64x_info, v2i64x_info>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; +defm VFIXUPIMMPS : avx512_fixupimm_packed_all, EVEX_CD8<32, CD8VF>; +defm VFIXUPIMMPD : avx512_fixupimm_packed_all, EVEX_CD8<64, CD8VF>, VEX_W; + +// Patterns used to select SSE scalar fp arithmetic instructions from +// either: +// +// (1) a scalar fp operation followed by a blend +// +// The effect is that the backend no longer emits unnecessary vector +// insert instructions immediately after SSE scalar fp instructions +// like addss or mulss. +// +// For example, given the following code: +// __m128 foo(__m128 A, __m128 B) { +// A[0] += B[0]; +// return A; +// } +// +// Previously we generated: +// addss %xmm0, %xmm1 +// movss %xmm1, %xmm0 +// +// We now generate: +// addss %xmm1, %xmm0 +// +// (2) a vector packed single/double fp operation followed by a vector insert +// +// The effect is that the backend converts the packed fp instruction +// followed by a vector insert into a single SSE scalar fp instruction. +// +// For example, given the following code: +// __m128 foo(__m128 A, __m128 B) { +// __m128 C = A + B; +// return (__m128) {c[0], a[1], a[2], a[3]}; +// } +// +// Previously we generated: +// addps %xmm0, %xmm1 +// movss %xmm1, %xmm0 +// +// We now generate: +// addss %xmm1, %xmm0 + +// TODO: Some canonicalization in lowering would simplify the number of +// patterns we have to try to match. +multiclass AVX512_scalar_math_fp_patterns { + let Predicates = [HasAVX512] in { + // extracted scalar math op with insert via movss + def : Pat<(MoveNode + (_.VT VR128X:$dst), + (_.VT (scalar_to_vector + (Op (_.EltVT (extractelt (_.VT VR128X:$dst), (iPTR 0))), + _.FRC:$src)))), + (!cast("V"#OpcPrefix#Zrr_Int) _.VT:$dst, + (_.VT (COPY_TO_REGCLASS _.FRC:$src, VR128X)))>; + + // extracted masked scalar math op with insert via movss + def : Pat<(MoveNode (_.VT VR128X:$src1), + (scalar_to_vector + (X86selects VK1WM:$mask, + (Op (_.EltVT + (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src2), + _.FRC:$src0))), + (!cast("V"#OpcPrefix#Zrr_Intk) + (_.VT (COPY_TO_REGCLASS _.FRC:$src0, VR128X)), + VK1WM:$mask, _.VT:$src1, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)))>; + + // extracted masked scalar math op with insert via movss + def : Pat<(MoveNode (_.VT VR128X:$src1), + (scalar_to_vector + (X86selects VK1WM:$mask, + (Op (_.EltVT + (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src2), (_.EltVT ZeroFP)))), + (!cast("V"#OpcPrefix#Zrr_Intkz) + VK1WM:$mask, _.VT:$src1, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)))>; + } +} + +defm : AVX512_scalar_math_fp_patterns; +defm : AVX512_scalar_math_fp_patterns; +defm : AVX512_scalar_math_fp_patterns; +defm : AVX512_scalar_math_fp_patterns; + +defm : AVX512_scalar_math_fp_patterns; +defm : AVX512_scalar_math_fp_patterns; +defm : AVX512_scalar_math_fp_patterns; +defm : AVX512_scalar_math_fp_patterns; + +multiclass AVX512_scalar_unary_math_patterns { + let Predicates = [HasAVX512] in { + def : Pat<(_.VT (Move _.VT:$dst, + (scalar_to_vector (OpNode (extractelt _.VT:$src, 0))))), + (!cast("V"#OpcPrefix#Zr_Int) _.VT:$dst, _.VT:$src)>; + } +} + +defm : AVX512_scalar_unary_math_patterns; +defm : AVX512_scalar_unary_math_patterns; + +multiclass AVX512_scalar_unary_math_imm_patterns ImmV> { + let Predicates = [HasAVX512] in { + def : Pat<(_.VT (Move _.VT:$dst, + (scalar_to_vector (OpNode (extractelt _.VT:$src, 0))))), + (!cast("V"#OpcPrefix#Zr_Int) _.VT:$dst, _.VT:$src, + (i32 ImmV))>; + } +} + +defm : AVX512_scalar_unary_math_imm_patterns; +defm : AVX512_scalar_unary_math_imm_patterns; +defm : AVX512_scalar_unary_math_imm_patterns; +defm : AVX512_scalar_unary_math_imm_patterns; + +//===----------------------------------------------------------------------===// +// AES instructions +//===----------------------------------------------------------------------===// + +multiclass avx512_vaes Op, string OpStr, string IntPrefix> { + let Predicates = [HasVLX, HasVAES] in { + defm Z128 : AESI_binop_rm_int(IntPrefix), + loadv2i64, 0, VR128X, i128mem>, + EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V128, VEX_WIG; + defm Z256 : AESI_binop_rm_int(IntPrefix##"_256"), + loadv4i64, 0, VR256X, i256mem>, + EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V256, VEX_WIG; + } + let Predicates = [HasAVX512, HasVAES] in + defm Z : AESI_binop_rm_int(IntPrefix##"_512"), + loadv8i64, 0, VR512, i512mem>, + EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_WIG; +} + +defm VAESENC : avx512_vaes<0xDC, "vaesenc", "int_x86_aesni_aesenc">; +defm VAESENCLAST : avx512_vaes<0xDD, "vaesenclast", "int_x86_aesni_aesenclast">; +defm VAESDEC : avx512_vaes<0xDE, "vaesdec", "int_x86_aesni_aesdec">; +defm VAESDECLAST : avx512_vaes<0xDF, "vaesdeclast", "int_x86_aesni_aesdeclast">; + +//===----------------------------------------------------------------------===// +// PCLMUL instructions - Carry less multiplication +//===----------------------------------------------------------------------===// + +let Predicates = [HasAVX512, HasVPCLMULQDQ] in +defm VPCLMULQDQZ : vpclmulqdq, + EVEX_4V, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_WIG; + +let Predicates = [HasVLX, HasVPCLMULQDQ] in { +defm VPCLMULQDQZ128 : vpclmulqdq, + EVEX_4V, EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_WIG; + +defm VPCLMULQDQZ256: vpclmulqdq, EVEX_4V, EVEX_V256, + EVEX_CD8<64, CD8VF>, VEX_WIG; +} + +// Aliases +//defm : vpclmulqdq_aliases<"VPCLMULQDQZ", VR512, i512mem>; +//defm : vpclmulqdq_aliases<"VPCLMULQDQZ128", VR128X, i128mem>; +//defm : vpclmulqdq_aliases<"VPCLMULQDQZ256", VR256X, i256mem>; + +//===----------------------------------------------------------------------===// +// VBMI2 +//===----------------------------------------------------------------------===// + +multiclass VBMI2_shift_var_rm Op, string OpStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo VTI> { + let Constraints = "$src1 = $dst", + ExeDomain = VTI.ExeDomain in { + defm r: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched]>; + defm m: AVX512_maskable_3src, + AVX512FMA3Base, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass VBMI2_shift_var_rmb Op, string OpStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo VTI> + : VBMI2_shift_var_rm { + let Constraints = "$src1 = $dst", + ExeDomain = VTI.ExeDomain in + defm mb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass VBMI2_shift_var_rm_common Op, string OpStr, SDNode OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo VTI> { + let Predicates = [HasVBMI2] in + defm Z : VBMI2_shift_var_rm, + EVEX_V512; + let Predicates = [HasVBMI2, HasVLX] in { + defm Z256 : VBMI2_shift_var_rm, + EVEX_V256; + defm Z128 : VBMI2_shift_var_rm, + EVEX_V128; + } +} + +multiclass VBMI2_shift_var_rmb_common Op, string OpStr, SDNode OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo VTI> { + let Predicates = [HasVBMI2] in + defm Z : VBMI2_shift_var_rmb, + EVEX_V512; + let Predicates = [HasVBMI2, HasVLX] in { + defm Z256 : VBMI2_shift_var_rmb, + EVEX_V256; + defm Z128 : VBMI2_shift_var_rmb, + EVEX_V128; + } +} +multiclass VBMI2_shift_var wOp, bits<8> dqOp, string Prefix, + SDNode OpNode, X86SchedWriteWidths sched> { + defm W : VBMI2_shift_var_rm_common, VEX_W, EVEX_CD8<16, CD8VF>; + defm D : VBMI2_shift_var_rmb_common, EVEX_CD8<32, CD8VF>; + defm Q : VBMI2_shift_var_rmb_common, VEX_W, EVEX_CD8<64, CD8VF>; +} + +multiclass VBMI2_shift_imm wOp, bits<8> dqOp, string Prefix, + SDNode OpNode, X86SchedWriteWidths sched> { + defm W : avx512_common_3Op_rm_imm8, + VEX_W, EVEX_CD8<16, CD8VF>; + defm D : avx512_common_3Op_imm8, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; + defm Q : avx512_common_3Op_imm8, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; +} + +// Concat & Shift +defm VPSHLDV : VBMI2_shift_var<0x70, 0x71, "vpshldv", X86VShldv, SchedWriteVecIMul>; +defm VPSHRDV : VBMI2_shift_var<0x72, 0x73, "vpshrdv", X86VShrdv, SchedWriteVecIMul>; +defm VPSHLD : VBMI2_shift_imm<0x70, 0x71, "vpshld", X86VShld, SchedWriteVecIMul>; +defm VPSHRD : VBMI2_shift_imm<0x72, 0x73, "vpshrd", X86VShrd, SchedWriteVecIMul>; + +// Compress +defm VPCOMPRESSB : compress_by_elt_width<0x63, "vpcompressb", WriteVarShuffle256, + avx512vl_i8_info, HasVBMI2>, EVEX, + NotMemoryFoldable; +defm VPCOMPRESSW : compress_by_elt_width <0x63, "vpcompressw", WriteVarShuffle256, + avx512vl_i16_info, HasVBMI2>, EVEX, VEX_W, + NotMemoryFoldable; +// Expand +defm VPEXPANDB : expand_by_elt_width <0x62, "vpexpandb", WriteVarShuffle256, + avx512vl_i8_info, HasVBMI2>, EVEX; +defm VPEXPANDW : expand_by_elt_width <0x62, "vpexpandw", WriteVarShuffle256, + avx512vl_i16_info, HasVBMI2>, EVEX, VEX_W; + +//===----------------------------------------------------------------------===// +// VNNI +//===----------------------------------------------------------------------===// + +let Constraints = "$src1 = $dst" in +multiclass VNNI_rmb Op, string OpStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo VTI> { + defm r : AVX512_maskable_3src, + EVEX_4V, T8PD, Sched<[sched]>; + defm m : AVX512_maskable_3src, + EVEX_4V, EVEX_CD8<32, CD8VF>, T8PD, + Sched<[sched.Folded, ReadAfterLd]>; + defm mb : AVX512_maskable_3src, + EVEX_4V, EVEX_CD8<32, CD8VF>, EVEX_B, + T8PD, Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass VNNI_common Op, string OpStr, SDNode OpNode, + X86SchedWriteWidths sched> { + let Predicates = [HasVNNI] in + defm Z : VNNI_rmb, EVEX_V512; + let Predicates = [HasVNNI, HasVLX] in { + defm Z256 : VNNI_rmb, EVEX_V256; + defm Z128 : VNNI_rmb, EVEX_V128; + } +} + +// FIXME: Is there a better scheduler class for VPDP? +defm VPDPBUSD : VNNI_common<0x50, "vpdpbusd", X86Vpdpbusd, SchedWriteVecIMul>; +defm VPDPBUSDS : VNNI_common<0x51, "vpdpbusds", X86Vpdpbusds, SchedWriteVecIMul>; +defm VPDPWSSD : VNNI_common<0x52, "vpdpwssd", X86Vpdpwssd, SchedWriteVecIMul>; +defm VPDPWSSDS : VNNI_common<0x53, "vpdpwssds", X86Vpdpwssds, SchedWriteVecIMul>; + +//===----------------------------------------------------------------------===// +// Bit Algorithms +//===----------------------------------------------------------------------===// + +// FIXME: Is there a better scheduler class for VPOPCNTB/VPOPCNTW? +defm VPOPCNTB : avx512_unary_rm_vl<0x54, "vpopcntb", ctpop, SchedWriteVecALU, + avx512vl_i8_info, HasBITALG>; +defm VPOPCNTW : avx512_unary_rm_vl<0x54, "vpopcntw", ctpop, SchedWriteVecALU, + avx512vl_i16_info, HasBITALG>, VEX_W; + +defm : avx512_unary_lowering<"VPOPCNTB", ctpop, avx512vl_i8_info, HasBITALG>; +defm : avx512_unary_lowering<"VPOPCNTW", ctpop, avx512vl_i16_info, HasBITALG>; + +multiclass VPSHUFBITQMB_rm { + defm rr : AVX512_maskable_cmp<0x8F, MRMSrcReg, VTI, (outs VTI.KRC:$dst), + (ins VTI.RC:$src1, VTI.RC:$src2), + "vpshufbitqmb", + "$src2, $src1", "$src1, $src2", + (X86Vpshufbitqmb (VTI.VT VTI.RC:$src1), + (VTI.VT VTI.RC:$src2))>, EVEX_4V, T8PD, + Sched<[sched]>; + defm rm : AVX512_maskable_cmp<0x8F, MRMSrcMem, VTI, (outs VTI.KRC:$dst), + (ins VTI.RC:$src1, VTI.MemOp:$src2), + "vpshufbitqmb", + "$src2, $src1", "$src1, $src2", + (X86Vpshufbitqmb (VTI.VT VTI.RC:$src1), + (VTI.VT (bitconvert (VTI.LdFrag addr:$src2))))>, + EVEX_4V, EVEX_CD8<8, CD8VF>, T8PD, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass VPSHUFBITQMB_common { + let Predicates = [HasBITALG] in + defm Z : VPSHUFBITQMB_rm, EVEX_V512; + let Predicates = [HasBITALG, HasVLX] in { + defm Z256 : VPSHUFBITQMB_rm, EVEX_V256; + defm Z128 : VPSHUFBITQMB_rm, EVEX_V128; + } +} + +// FIXME: Is there a better scheduler class for VPSHUFBITQMB? +defm VPSHUFBITQMB : VPSHUFBITQMB_common; + +//===----------------------------------------------------------------------===// +// GFNI +//===----------------------------------------------------------------------===// + +multiclass GF2P8MULB_avx512_common Op, string OpStr, SDNode OpNode, + X86SchedWriteWidths sched> { + let Predicates = [HasGFNI, HasAVX512, HasBWI] in + defm Z : avx512_binop_rm, + EVEX_V512; + let Predicates = [HasGFNI, HasVLX, HasBWI] in { + defm Z256 : avx512_binop_rm, + EVEX_V256; + defm Z128 : avx512_binop_rm, + EVEX_V128; + } +} + +defm VGF2P8MULB : GF2P8MULB_avx512_common<0xCF, "vgf2p8mulb", X86GF2P8mulb, + SchedWriteVecALU>, + EVEX_CD8<8, CD8VF>, T8PD; + +multiclass GF2P8AFFINE_avx512_rmb_imm Op, string OpStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo VTI, + X86VectorVTInfo BcstVTI> + : avx512_3Op_rm_imm8 { + let ExeDomain = VTI.ExeDomain in + defm rmbi : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass GF2P8AFFINE_avx512_common Op, string OpStr, SDNode OpNode, + X86SchedWriteWidths sched> { + let Predicates = [HasGFNI, HasAVX512, HasBWI] in + defm Z : GF2P8AFFINE_avx512_rmb_imm, EVEX_V512; + let Predicates = [HasGFNI, HasVLX, HasBWI] in { + defm Z256 : GF2P8AFFINE_avx512_rmb_imm, EVEX_V256; + defm Z128 : GF2P8AFFINE_avx512_rmb_imm, EVEX_V128; + } +} + +defm VGF2P8AFFINEINVQB : GF2P8AFFINE_avx512_common<0xCF, "vgf2p8affineinvqb", + X86GF2P8affineinvqb, SchedWriteVecIMul>, + EVEX_4V, EVEX_CD8<8, CD8VF>, VEX_W, AVX512AIi8Base; +defm VGF2P8AFFINEQB : GF2P8AFFINE_avx512_common<0xCE, "vgf2p8affineqb", + X86GF2P8affineqb, SchedWriteVecIMul>, + EVEX_4V, EVEX_CD8<8, CD8VF>, VEX_W, AVX512AIi8Base; + + +//===----------------------------------------------------------------------===// +// AVX5124FMAPS +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 1, ExeDomain = SSEPackedSingle, + Constraints = "$src1 = $dst" in { +defm V4FMADDPSrm : AVX512_maskable_3src_in_asm<0x9A, MRMSrcMem, v16f32_info, + (outs VR512:$dst), (ins VR512:$src2, f128mem:$src3), + "v4fmaddps", "$src3, $src2", "$src2, $src3", + []>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>, + Sched<[SchedWriteFMA.ZMM.Folded]>; + +defm V4FNMADDPSrm : AVX512_maskable_3src_in_asm<0xAA, MRMSrcMem, v16f32_info, + (outs VR512:$dst), (ins VR512:$src2, f128mem:$src3), + "v4fnmaddps", "$src3, $src2", "$src2, $src3", + []>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>, + Sched<[SchedWriteFMA.ZMM.Folded]>; + +defm V4FMADDSSrm : AVX512_maskable_3src_in_asm<0x9B, MRMSrcMem, f32x_info, + (outs VR128X:$dst), (ins VR128X:$src2, f128mem:$src3), + "v4fmaddss", "$src3, $src2", "$src2, $src3", + []>, EVEX_V128, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>, + Sched<[SchedWriteFMA.Scl.Folded]>; + +defm V4FNMADDSSrm : AVX512_maskable_3src_in_asm<0xAB, MRMSrcMem, f32x_info, + (outs VR128X:$dst), (ins VR128X:$src2, f128mem:$src3), + "v4fnmaddss", "$src3, $src2", "$src2, $src3", + []>, EVEX_V128, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>, + Sched<[SchedWriteFMA.Scl.Folded]>; +} + +//===----------------------------------------------------------------------===// +// AVX5124VNNIW +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 1, ExeDomain = SSEPackedInt, + Constraints = "$src1 = $dst" in { +defm VP4DPWSSDrm : AVX512_maskable_3src_in_asm<0x52, MRMSrcMem, v16i32_info, + (outs VR512:$dst), (ins VR512:$src2, f128mem:$src3), + "vp4dpwssd", "$src3, $src2", "$src2, $src3", + []>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>, + Sched<[SchedWriteFMA.ZMM.Folded]>; + +defm VP4DPWSSDSrm : AVX512_maskable_3src_in_asm<0x53, MRMSrcMem, v16i32_info, + (outs VR512:$dst), (ins VR512:$src2, f128mem:$src3), + "vp4dpwssds", "$src3, $src2", "$src2, $src3", + []>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>, + Sched<[SchedWriteFMA.ZMM.Folded]>; +} + diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrArithmetic.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrArithmetic.td new file mode 100644 index 0000000..d150114 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrArithmetic.td @@ -0,0 +1,1350 @@ +//===-- X86InstrArithmetic.td - Integer Arithmetic Instrs --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the integer arithmetic instructions in the X86 +// architecture. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// LEA - Load Effective Address +let SchedRW = [WriteLEA] in { +let hasSideEffects = 0 in +def LEA16r : I<0x8D, MRMSrcMem, + (outs GR16:$dst), (ins anymem:$src), + "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize16; +let isReMaterializable = 1 in +def LEA32r : I<0x8D, MRMSrcMem, + (outs GR32:$dst), (ins anymem:$src), + "lea{l}\t{$src|$dst}, {$dst|$src}", + [(set GR32:$dst, lea32addr:$src)]>, + OpSize32, Requires<[Not64BitMode]>; + +def LEA64_32r : I<0x8D, MRMSrcMem, + (outs GR32:$dst), (ins lea64_32mem:$src), + "lea{l}\t{$src|$dst}, {$dst|$src}", + [(set GR32:$dst, lea64_32addr:$src)]>, + OpSize32, Requires<[In64BitMode]>; + +let isReMaterializable = 1 in +def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src), + "lea{q}\t{$src|$dst}, {$dst|$src}", + [(set GR64:$dst, lea64addr:$src)]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Fixed-Register Multiplication and Division Instructions. +// + +// SchedModel info for instruction that loads one value and gets the second +// (and possibly third) value from a register. +// This is used for instructions that put the memory operands before other +// uses. +class SchedLoadReg : Sched<[SW, + // Memory operand. + ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, + // Register reads (implicit or explicit). + ReadAfterLd, ReadAfterLd]>; + +// Extra precision multiplication + +// AL is really implied by AX, but the registers in Defs must match the +// SDNode results (i8, i32). +// AL,AH = AL*GR8 +let Defs = [AL,EFLAGS,AX], Uses = [AL] in +def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src", + // FIXME: Used for 8-bit mul, ignore result upper 8 bits. + // This probably ought to be moved to a def : Pat<> if the + // syntax can be accepted. + [(set AL, (mul AL, GR8:$src)), + (implicit EFLAGS)]>, Sched<[WriteIMul]>; +// AX,DX = AX*GR16 +let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in +def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), + "mul{w}\t$src", + []>, OpSize16, Sched<[WriteIMul]>; +// EAX,EDX = EAX*GR32 +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in +def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), + "mul{l}\t$src", + [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/]>, + OpSize32, Sched<[WriteIMul]>; +// RAX,RDX = RAX*GR64 +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in +def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src), + "mul{q}\t$src", + [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>, + Sched<[WriteIMul64]>; +// AL,AH = AL*[mem8] +let Defs = [AL,EFLAGS,AX], Uses = [AL] in +def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src), + "mul{b}\t$src", + // FIXME: Used for 8-bit mul, ignore result upper 8 bits. + // This probably ought to be moved to a def : Pat<> if the + // syntax can be accepted. + [(set AL, (mul AL, (loadi8 addr:$src))), + (implicit EFLAGS)]>, SchedLoadReg; +// AX,DX = AX*[mem16] +let mayLoad = 1, hasSideEffects = 0 in { +let Defs = [AX,DX,EFLAGS], Uses = [AX] in +def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src), + "mul{w}\t$src", []>, OpSize16, SchedLoadReg; +// EAX,EDX = EAX*[mem32] +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in +def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src), + "mul{l}\t$src", []>, OpSize32, SchedLoadReg; +// RAX,RDX = RAX*[mem64] +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in +def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src), + "mul{q}\t$src", []>, SchedLoadReg, + Requires<[In64BitMode]>; +} + +let hasSideEffects = 0 in { +// AL,AH = AL*GR8 +let Defs = [AL,EFLAGS,AX], Uses = [AL] in +def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>, + Sched<[WriteIMul]>; +// AX,DX = AX*GR16 +let Defs = [AX,DX,EFLAGS], Uses = [AX] in +def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>, + OpSize16, Sched<[WriteIMul]>; +// EAX,EDX = EAX*GR32 +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in +def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>, + OpSize32, Sched<[WriteIMul]>; +// RAX,RDX = RAX*GR64 +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in +def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>, + Sched<[WriteIMul64]>; + +let mayLoad = 1 in { +// AL,AH = AL*[mem8] +let Defs = [AL,EFLAGS,AX], Uses = [AL] in +def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src), + "imul{b}\t$src", []>, SchedLoadReg; +// AX,DX = AX*[mem16] +let Defs = [AX,DX,EFLAGS], Uses = [AX] in +def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src), + "imul{w}\t$src", []>, OpSize16, SchedLoadReg; +// EAX,EDX = EAX*[mem32] +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in +def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src), + "imul{l}\t$src", []>, OpSize32, SchedLoadReg; +// RAX,RDX = RAX*[mem64] +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in +def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src), + "imul{q}\t$src", []>, SchedLoadReg, + Requires<[In64BitMode]>; +} +} // hasSideEffects + + +let Defs = [EFLAGS] in { +let Constraints = "$src1 = $dst" in { + +let isCommutable = 1 in { +// X = IMUL Y, Z --> X = IMUL Z, Y +// Register-Register Signed Integer Multiply +def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), + "imul{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, EFLAGS, + (X86smul_flag GR16:$src1, GR16:$src2))]>, + Sched<[WriteIMul]>, TB, OpSize16; +def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), + "imul{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, EFLAGS, + (X86smul_flag GR32:$src1, GR32:$src2))]>, + Sched<[WriteIMul]>, TB, OpSize32; +def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), + "imul{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, EFLAGS, + (X86smul_flag GR64:$src1, GR64:$src2))]>, + Sched<[WriteIMul64]>, TB; +} // isCommutable + +// Register-Memory Signed Integer Multiply +def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), + (ins GR16:$src1, i16mem:$src2), + "imul{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, EFLAGS, + (X86smul_flag GR16:$src1, (loadi16 addr:$src2)))]>, + Sched<[WriteIMul.Folded, ReadAfterLd]>, TB, OpSize16; +def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$src1, i32mem:$src2), + "imul{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, EFLAGS, + (X86smul_flag GR32:$src1, (loadi32 addr:$src2)))]>, + Sched<[WriteIMul.Folded, ReadAfterLd]>, TB, OpSize32; +def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$src1, i64mem:$src2), + "imul{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, EFLAGS, + (X86smul_flag GR64:$src1, (loadi64 addr:$src2)))]>, + Sched<[WriteIMul64.Folded, ReadAfterLd]>, TB; +} // Constraints = "$src1 = $dst" + +} // Defs = [EFLAGS] + +// Surprisingly enough, these are not two address instructions! +let Defs = [EFLAGS] in { +// Register-Integer Signed Integer Multiply +def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 + (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), + "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR16:$dst, EFLAGS, + (X86smul_flag GR16:$src1, imm:$src2))]>, + Sched<[WriteIMul]>, OpSize16; +def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 + (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR16:$dst, EFLAGS, + (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>, + Sched<[WriteIMul]>, OpSize16; +def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 + (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), + "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32:$dst, EFLAGS, + (X86smul_flag GR32:$src1, imm:$src2))]>, + Sched<[WriteIMul]>, OpSize32; +def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 + (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32:$dst, EFLAGS, + (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>, + Sched<[WriteIMul]>, OpSize32; +def IMUL64rri32 : RIi32S<0x69, MRMSrcReg, // GR64 = GR64*I32 + (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), + "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR64:$dst, EFLAGS, + (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>, + Sched<[WriteIMul64]>; +def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8 + (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR64:$dst, EFLAGS, + (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>, + Sched<[WriteIMul64]>; + +// Memory-Integer Signed Integer Multiply +def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 + (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2), + "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR16:$dst, EFLAGS, + (X86smul_flag (loadi16 addr:$src1), imm:$src2))]>, + Sched<[WriteIMul.Folded]>, OpSize16; +def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 + (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2), + "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR16:$dst, EFLAGS, + (X86smul_flag (loadi16 addr:$src1), + i16immSExt8:$src2))]>, + Sched<[WriteIMul.Folded]>, OpSize16; +def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 + (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2), + "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32:$dst, EFLAGS, + (X86smul_flag (loadi32 addr:$src1), imm:$src2))]>, + Sched<[WriteIMul.Folded]>, OpSize32; +def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 + (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2), + "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32:$dst, EFLAGS, + (X86smul_flag (loadi32 addr:$src1), + i32immSExt8:$src2))]>, + Sched<[WriteIMul.Folded]>, OpSize32; +def IMUL64rmi32 : RIi32S<0x69, MRMSrcMem, // GR64 = [mem64]*I32 + (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2), + "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR64:$dst, EFLAGS, + (X86smul_flag (loadi64 addr:$src1), + i64immSExt32:$src2))]>, + Sched<[WriteIMul64.Folded]>; +def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8 + (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2), + "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR64:$dst, EFLAGS, + (X86smul_flag (loadi64 addr:$src1), + i64immSExt8:$src2))]>, + Sched<[WriteIMul64.Folded]>; +} // Defs = [EFLAGS] + +// unsigned division/remainder +let hasSideEffects = 1 in { // so that we don't speculatively execute +let Defs = [AL,AH,EFLAGS], Uses = [AX] in +def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH + "div{b}\t$src", []>, Sched<[WriteDiv8]>; +let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in +def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX + "div{w}\t$src", []>, Sched<[WriteDiv16]>, OpSize16; +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in +def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX + "div{l}\t$src", []>, Sched<[WriteDiv32]>, OpSize32; +// RDX:RAX/r64 = RAX,RDX +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in +def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), + "div{q}\t$src", []>, Sched<[WriteDiv64]>; + +let mayLoad = 1 in { +let Defs = [AL,AH,EFLAGS], Uses = [AX] in +def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH + "div{b}\t$src", []>, SchedLoadReg; +let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in +def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX + "div{w}\t$src", []>, OpSize16, SchedLoadReg; +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX +def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), + "div{l}\t$src", []>, SchedLoadReg, OpSize32; +// RDX:RAX/[mem64] = RAX,RDX +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in +def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), + "div{q}\t$src", []>, SchedLoadReg, + Requires<[In64BitMode]>; +} + +// Signed division/remainder. +let Defs = [AL,AH,EFLAGS], Uses = [AX] in +def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH + "idiv{b}\t$src", []>, Sched<[WriteIDiv8]>; +let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in +def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX + "idiv{w}\t$src", []>, Sched<[WriteIDiv16]>, OpSize16; +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in +def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX + "idiv{l}\t$src", []>, Sched<[WriteIDiv32]>, OpSize32; +// RDX:RAX/r64 = RAX,RDX +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in +def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), + "idiv{q}\t$src", []>, Sched<[WriteIDiv64]>; + +let mayLoad = 1 in { +let Defs = [AL,AH,EFLAGS], Uses = [AX] in +def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH + "idiv{b}\t$src", []>, SchedLoadReg; +let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in +def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX + "idiv{w}\t$src", []>, OpSize16, SchedLoadReg; +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX +def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), + "idiv{l}\t$src", []>, OpSize32, SchedLoadReg; +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX +def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), + "idiv{q}\t$src", []>, SchedLoadReg, + Requires<[In64BitMode]>; +} +} // hasSideEffects = 0 + +//===----------------------------------------------------------------------===// +// Two address Instructions. +// + +// unary instructions +let CodeSize = 2 in { +let Defs = [EFLAGS] in { +let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { +def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1), + "neg{b}\t$dst", + [(set GR8:$dst, (ineg GR8:$src1)), + (implicit EFLAGS)]>; +def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1), + "neg{w}\t$dst", + [(set GR16:$dst, (ineg GR16:$src1)), + (implicit EFLAGS)]>, OpSize16; +def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1), + "neg{l}\t$dst", + [(set GR32:$dst, (ineg GR32:$src1)), + (implicit EFLAGS)]>, OpSize32; +def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst", + [(set GR64:$dst, (ineg GR64:$src1)), + (implicit EFLAGS)]>; +} // Constraints = "$src1 = $dst", SchedRW + +// Read-modify-write negate. +let SchedRW = [WriteALURMW] in { +def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), + "neg{b}\t$dst", + [(store (ineg (loadi8 addr:$dst)), addr:$dst), + (implicit EFLAGS)]>; +def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), + "neg{w}\t$dst", + [(store (ineg (loadi16 addr:$dst)), addr:$dst), + (implicit EFLAGS)]>, OpSize16; +def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), + "neg{l}\t$dst", + [(store (ineg (loadi32 addr:$dst)), addr:$dst), + (implicit EFLAGS)]>, OpSize32; +def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst", + [(store (ineg (loadi64 addr:$dst)), addr:$dst), + (implicit EFLAGS)]>, + Requires<[In64BitMode]>; +} // SchedRW +} // Defs = [EFLAGS] + + +// Note: NOT does not set EFLAGS! + +let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { +def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1), + "not{b}\t$dst", + [(set GR8:$dst, (not GR8:$src1))]>; +def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1), + "not{w}\t$dst", + [(set GR16:$dst, (not GR16:$src1))]>, OpSize16; +def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1), + "not{l}\t$dst", + [(set GR32:$dst, (not GR32:$src1))]>, OpSize32; +def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst", + [(set GR64:$dst, (not GR64:$src1))]>; +} // Constraints = "$src1 = $dst", SchedRW + +let SchedRW = [WriteALURMW] in { +def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), + "not{b}\t$dst", + [(store (not (loadi8 addr:$dst)), addr:$dst)]>; +def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), + "not{w}\t$dst", + [(store (not (loadi16 addr:$dst)), addr:$dst)]>, + OpSize16; +def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), + "not{l}\t$dst", + [(store (not (loadi32 addr:$dst)), addr:$dst)]>, + OpSize32; +def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst", + [(store (not (loadi64 addr:$dst)), addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW +} // CodeSize + +// TODO: inc/dec is slow for P4, but fast for Pentium-M. +let Defs = [EFLAGS] in { +let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { +let CodeSize = 2 in +def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), + "inc{b}\t$dst", + [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>; +let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA. +def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1), + "inc{w}\t$dst", + [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>, OpSize16; +def INC32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1), + "inc{l}\t$dst", + [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>, OpSize32; +def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst", + [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))]>; +} // isConvertibleToThreeAddress = 1, CodeSize = 2 + +// Short forms only valid in 32-bit mode. Selected during MCInst lowering. +let CodeSize = 1, hasSideEffects = 0 in { +def INC16r_alt : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1), + "inc{w}\t$dst", []>, + OpSize16, Requires<[Not64BitMode]>; +def INC32r_alt : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1), + "inc{l}\t$dst", []>, + OpSize32, Requires<[Not64BitMode]>; +} // CodeSize = 1, hasSideEffects = 0 +} // Constraints = "$src1 = $dst", SchedRW + +let CodeSize = 2, SchedRW = [WriteALURMW] in { +let Predicates = [UseIncDec] in { + def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst", + [(store (add (loadi8 addr:$dst), 1), addr:$dst), + (implicit EFLAGS)]>; + def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", + [(store (add (loadi16 addr:$dst), 1), addr:$dst), + (implicit EFLAGS)]>, OpSize16; + def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", + [(store (add (loadi32 addr:$dst), 1), addr:$dst), + (implicit EFLAGS)]>, OpSize32; +} // Predicates +let Predicates = [UseIncDec, In64BitMode] in { + def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst", + [(store (add (loadi64 addr:$dst), 1), addr:$dst), + (implicit EFLAGS)]>; +} // Predicates +} // CodeSize = 2, SchedRW + +let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { +let CodeSize = 2 in +def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), + "dec{b}\t$dst", + [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>; +let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA. +def DEC16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1), + "dec{w}\t$dst", + [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>, OpSize16; +def DEC32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1), + "dec{l}\t$dst", + [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>, OpSize32; +def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst", + [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))]>; +} // isConvertibleToThreeAddress = 1, CodeSize = 2 + +// Short forms only valid in 32-bit mode. Selected during MCInst lowering. +let CodeSize = 1, hasSideEffects = 0 in { +def DEC16r_alt : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1), + "dec{w}\t$dst", []>, + OpSize16, Requires<[Not64BitMode]>; +def DEC32r_alt : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1), + "dec{l}\t$dst", []>, + OpSize32, Requires<[Not64BitMode]>; +} // CodeSize = 1, hasSideEffects = 0 +} // Constraints = "$src1 = $dst", SchedRW + + +let CodeSize = 2, SchedRW = [WriteALURMW] in { +let Predicates = [UseIncDec] in { + def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst", + [(store (add (loadi8 addr:$dst), -1), addr:$dst), + (implicit EFLAGS)]>; + def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", + [(store (add (loadi16 addr:$dst), -1), addr:$dst), + (implicit EFLAGS)]>, OpSize16; + def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", + [(store (add (loadi32 addr:$dst), -1), addr:$dst), + (implicit EFLAGS)]>, OpSize32; +} // Predicates +let Predicates = [UseIncDec, In64BitMode] in { + def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst", + [(store (add (loadi64 addr:$dst), -1), addr:$dst), + (implicit EFLAGS)]>; +} // Predicates +} // CodeSize = 2, SchedRW +} // Defs = [EFLAGS] + +/// X86TypeInfo - This is a bunch of information that describes relevant X86 +/// information about value types. For example, it can tell you what the +/// register class and preferred load to use. +class X86TypeInfo { + /// VT - This is the value type itself. + ValueType VT = vt; + + /// InstrSuffix - This is the suffix used on instructions with this type. For + /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q". + string InstrSuffix = instrsuffix; + + /// RegClass - This is the register class associated with this type. For + /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64. + RegisterClass RegClass = regclass; + + /// LoadNode - This is the load node associated with this type. For + /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64. + PatFrag LoadNode = loadnode; + + /// MemOperand - This is the memory operand associated with this type. For + /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem. + X86MemOperand MemOperand = memoperand; + + /// ImmEncoding - This is the encoding of an immediate of this type. For + /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32 + /// since the immediate fields of i64 instructions is a 32-bit sign extended + /// value. + ImmType ImmEncoding = immkind; + + /// ImmOperand - This is the operand kind of an immediate of this type. For + /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 -> + /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign + /// extended value. + Operand ImmOperand = immoperand; + + /// ImmOperator - This is the operator that should be used to match an + /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32). + SDPatternOperator ImmOperator = immoperator; + + /// Imm8Operand - This is the operand kind to use for an imm8 of this type. + /// For example, i8 -> , i16 -> i16i8imm, i32 -> i32i8imm. This is + /// only used for instructions that have a sign-extended imm8 field form. + Operand Imm8Operand = imm8operand; + + /// Imm8Operator - This is the operator that should be used to match an 8-bit + /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8). + SDPatternOperator Imm8Operator = imm8operator; + + /// HasOddOpcode - This bit is true if the instruction should have an odd (as + /// opposed to even) opcode. Operations on i8 are usually even, operations on + /// other datatypes are odd. + bit HasOddOpcode = hasOddOpcode; + + /// OpSize - Selects whether the instruction needs a 0x66 prefix based on + /// 16-bit vs 32-bit mode. i8/i64 set this to OpSizeFixed. i16 sets this + /// to Opsize16. i32 sets this to OpSize32. + OperandSize OpSize = opSize; + + /// HasREX_WPrefix - This bit is set to true if the instruction should have + /// the 0x40 REX prefix. This is set for i64 types. + bit HasREX_WPrefix = hasREX_WPrefix; +} + +def invalid_node : SDNode<"<>", SDTIntLeaf,[],"<>">; + + +def Xi8 : X86TypeInfo; +def Xi16 : X86TypeInfo; +def Xi32 : X86TypeInfo; +def Xi64 : X86TypeInfo; + +/// ITy - This instruction base class takes the type info for the instruction. +/// Using this, it: +/// 1. Concatenates together the instruction mnemonic with the appropriate +/// suffix letter, a tab, and the arguments. +/// 2. Infers whether the instruction should have a 0x66 prefix byte. +/// 3. Infers whether the instruction should have a 0x40 REX_W prefix. +/// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations) +/// or 1 (for i16,i32,i64 operations). +class ITy opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins, + string mnemonic, string args, list pattern> + : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4}, + opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode }, + f, outs, ins, + !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> { + + // Infer instruction prefixes from type info. + let OpSize = typeinfo.OpSize; + let hasREX_WPrefix = typeinfo.HasREX_WPrefix; +} + +// BinOpRR - Instructions like "add reg, reg, reg". +class BinOpRR opcode, string mnemonic, X86TypeInfo typeinfo, + dag outlist, X86FoldableSchedWrite sched, list pattern> + : ITy, + Sched<[sched]>; + +// BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has +// just a EFLAGS as a result. +class BinOpRR_F opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode> + : BinOpRR; + +// BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has +// both a regclass and EFLAGS as a result. +class BinOpRR_RF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpRR; + +// BinOpRR_RFF - Instructions like "adc reg, reg, reg", where the pattern has +// both a regclass and EFLAGS as a result, and has EFLAGS as input. +class BinOpRR_RFF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpRR; + +// BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding). +class BinOpRR_Rev opcode, string mnemonic, X86TypeInfo typeinfo, + X86FoldableSchedWrite sched = WriteALU> + : ITy, + Sched<[sched]> { + // The disassembler should know about this, but not the asmparser. + let isCodeGenOnly = 1; + let ForceDisassemble = 1; + let hasSideEffects = 0; +} + +// BinOpRR_RDD_Rev - Instructions like "adc reg, reg, reg" (reversed encoding). +class BinOpRR_RFF_Rev opcode, string mnemonic, X86TypeInfo typeinfo> + : BinOpRR_Rev; + +// BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding). +class BinOpRR_F_Rev opcode, string mnemonic, X86TypeInfo typeinfo> + : ITy, + Sched<[WriteALU]> { + // The disassembler should know about this, but not the asmparser. + let isCodeGenOnly = 1; + let ForceDisassemble = 1; + let hasSideEffects = 0; +} + +// BinOpRM - Instructions like "add reg, reg, [mem]". +class BinOpRM opcode, string mnemonic, X86TypeInfo typeinfo, + dag outlist, X86FoldableSchedWrite sched, list pattern> + : ITy, + Sched<[sched.Folded, ReadAfterLd]>; + +// BinOpRM_F - Instructions like "cmp reg, [mem]". +class BinOpRM_F opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpRM; + +// BinOpRM_RF - Instructions like "add reg, reg, [mem]". +class BinOpRM_RF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpRM; + +// BinOpRM_RFF - Instructions like "adc reg, reg, [mem]". +class BinOpRM_RFF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpRM; + +// BinOpRI - Instructions like "add reg, reg, imm". +class BinOpRI opcode, string mnemonic, X86TypeInfo typeinfo, + Format f, dag outlist, X86FoldableSchedWrite sched, list pattern> + : ITy, + Sched<[sched]> { + let ImmT = typeinfo.ImmEncoding; +} + +// BinOpRI_F - Instructions like "cmp reg, imm". +class BinOpRI_F opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode, Format f> + : BinOpRI; + +// BinOpRI_RF - Instructions like "add reg, reg, imm". +class BinOpRI_RF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode, Format f> + : BinOpRI; +// BinOpRI_RFF - Instructions like "adc reg, reg, imm". +class BinOpRI_RFF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode, Format f> + : BinOpRI; + +// BinOpRI8 - Instructions like "add reg, reg, imm8". +class BinOpRI8 opcode, string mnemonic, X86TypeInfo typeinfo, + Format f, dag outlist, X86FoldableSchedWrite sched, list pattern> + : ITy, + Sched<[sched]> { + let ImmT = Imm8; // Always 8-bit immediate. +} + +// BinOpRI8_F - Instructions like "cmp reg, imm8". +class BinOpRI8_F opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode, Format f> + : BinOpRI8; + +// BinOpRI8_RF - Instructions like "add reg, reg, imm8". +class BinOpRI8_RF opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode, Format f> + : BinOpRI8; + +// BinOpRI8_RFF - Instructions like "adc reg, reg, imm8". +class BinOpRI8_RFF opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode, Format f> + : BinOpRI8; + +// BinOpMR - Instructions like "add [mem], reg". +class BinOpMR opcode, string mnemonic, X86TypeInfo typeinfo, + list pattern> + : ITy; + +// BinOpMR_RMW - Instructions like "add [mem], reg". +class BinOpMR_RMW opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpMR, Sched<[WriteALURMW]>; + +// BinOpMR_RMW_FF - Instructions like "adc [mem], reg". +class BinOpMR_RMW_FF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpMR, Sched<[WriteADCRMW]>; + +// BinOpMR_F - Instructions like "cmp [mem], reg". +class BinOpMR_F opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode> + : BinOpMR, + Sched<[WriteALULd, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, ReadDefault, ReadAfterLd]>; + +// BinOpMI - Instructions like "add [mem], imm". +class BinOpMI opcode, string mnemonic, X86TypeInfo typeinfo, + Format f, list pattern> + : ITy { + let ImmT = typeinfo.ImmEncoding; +} + +// BinOpMI_RMW - Instructions like "add [mem], imm". +class BinOpMI_RMW opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode, Format f> + : BinOpMI, Sched<[WriteALURMW]>; +// BinOpMI_RMW_FF - Instructions like "adc [mem], imm". +class BinOpMI_RMW_FF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode, Format f> + : BinOpMI, Sched<[WriteADCRMW]>; + +// BinOpMI_F - Instructions like "cmp [mem], imm". +class BinOpMI_F opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode, Format f> + : BinOpMI, + Sched<[WriteALULd]>; + +// BinOpMI8 - Instructions like "add [mem], imm8". +class BinOpMI8 pattern> + : ITy<0x82, f, typeinfo, + (outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src), + mnemonic, "{$src, $dst|$dst, $src}", pattern> { + let ImmT = Imm8; // Always 8-bit immediate. +} + +// BinOpMI8_RMW - Instructions like "add [mem], imm8". +class BinOpMI8_RMW + : BinOpMI8, Sched<[WriteALURMW]>; + +// BinOpMI8_RMW_FF - Instructions like "adc [mem], imm8". +class BinOpMI8_RMW_FF + : BinOpMI8, Sched<[WriteADCRMW]>; + +// BinOpMI8_F - Instructions like "cmp [mem], imm8". +class BinOpMI8_F + : BinOpMI8, + Sched<[WriteALULd]>; + +// BinOpAI - Instructions like "add %eax, %eax, imm", that imp-def EFLAGS. +class BinOpAI opcode, string mnemonic, X86TypeInfo typeinfo, + Register areg, string operands, X86FoldableSchedWrite sched = WriteALU> + : ITy, Sched<[sched]> { + let ImmT = typeinfo.ImmEncoding; + let Uses = [areg]; + let Defs = [areg, EFLAGS]; + let hasSideEffects = 0; +} + +// BinOpAI_RFF - Instructions like "adc %eax, %eax, imm", that implicitly define +// and use EFLAGS. +class BinOpAI_RFF opcode, string mnemonic, X86TypeInfo typeinfo, + Register areg, string operands> + : BinOpAI { + let Uses = [areg, EFLAGS]; +} + +// BinOpAI_F - Instructions like "cmp %eax, %eax, imm", that imp-def EFLAGS. +class BinOpAI_F opcode, string mnemonic, X86TypeInfo typeinfo, + Register areg, string operands> + : BinOpAI { + let Defs = [EFLAGS]; +} + +/// ArithBinOp_RF - This is an arithmetic binary operator where the pattern is +/// defined with "(set GPR:$dst, EFLAGS, (...". +/// +/// It would be nice to get rid of the second and third argument here, but +/// tblgen can't handle dependent type references aggressively enough: PR8330 +multiclass ArithBinOp_RF BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, + string mnemonic, Format RegMRM, Format MemMRM, + SDNode opnodeflag, SDNode opnode, + bit CommutableRR, bit ConvertibleToThreeAddress> { + let Defs = [EFLAGS] in { + let Constraints = "$src1 = $dst" in { + let isCommutable = CommutableRR in { + def NAME#8rr : BinOpRR_RF; + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { + def NAME#16rr : BinOpRR_RF; + def NAME#32rr : BinOpRR_RF; + def NAME#64rr : BinOpRR_RF; + } // isConvertibleToThreeAddress + } // isCommutable + + def NAME#8rr_REV : BinOpRR_Rev, FoldGenData; + def NAME#16rr_REV : BinOpRR_Rev, FoldGenData; + def NAME#32rr_REV : BinOpRR_Rev, FoldGenData; + def NAME#64rr_REV : BinOpRR_Rev, FoldGenData; + + def NAME#8rm : BinOpRM_RF; + def NAME#16rm : BinOpRM_RF; + def NAME#32rm : BinOpRM_RF; + def NAME#64rm : BinOpRM_RF; + + def NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>; + + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { + // NOTE: These are order specific, we want the ri8 forms to be listed + // first so that they are slightly preferred to the ri forms. + def NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>; + def NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>; + def NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>; + + def NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>; + def NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>; + def NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>; + } + } // Constraints = "$src1 = $dst" + + let mayLoad = 1, mayStore = 1 in { + def NAME#8mr : BinOpMR_RMW; + def NAME#16mr : BinOpMR_RMW; + def NAME#32mr : BinOpMR_RMW; + def NAME#64mr : BinOpMR_RMW; + } + + // NOTE: These are order specific, we want the mi8 forms to be listed + // first so that they are slightly preferred to the mi forms. + def NAME#16mi8 : BinOpMI8_RMW; + def NAME#32mi8 : BinOpMI8_RMW; + let Predicates = [In64BitMode] in + def NAME#64mi8 : BinOpMI8_RMW; + + def NAME#8mi : BinOpMI_RMW<0x80, mnemonic, Xi8 , opnode, MemMRM>; + def NAME#16mi : BinOpMI_RMW<0x80, mnemonic, Xi16, opnode, MemMRM>; + def NAME#32mi : BinOpMI_RMW<0x80, mnemonic, Xi32, opnode, MemMRM>; + let Predicates = [In64BitMode] in + def NAME#64mi32 : BinOpMI_RMW<0x80, mnemonic, Xi64, opnode, MemMRM>; + + // These are for the disassembler since 0x82 opcode behaves like 0x80, but + // not in 64-bit mode. + let Predicates = [Not64BitMode], isCodeGenOnly = 1, ForceDisassemble = 1, + hasSideEffects = 0 in { + let Constraints = "$src1 = $dst" in + def NAME#8ri8 : BinOpRI8_RF<0x82, mnemonic, Xi8, null_frag, RegMRM>; + let mayLoad = 1, mayStore = 1 in + def NAME#8mi8 : BinOpMI8_RMW; + } + } // Defs = [EFLAGS] + + def NAME#8i8 : BinOpAI; + def NAME#16i16 : BinOpAI; + def NAME#32i32 : BinOpAI; + def NAME#64i32 : BinOpAI; +} + +/// ArithBinOp_RFF - This is an arithmetic binary operator where the pattern is +/// defined with "(set GPR:$dst, EFLAGS, (node LHS, RHS, EFLAGS))" like ADC and +/// SBB. +/// +/// It would be nice to get rid of the second and third argument here, but +/// tblgen can't handle dependent type references aggressively enough: PR8330 +multiclass ArithBinOp_RFF BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, + string mnemonic, Format RegMRM, Format MemMRM, + SDNode opnode, bit CommutableRR, + bit ConvertibleToThreeAddress> { + let Uses = [EFLAGS], Defs = [EFLAGS] in { + let Constraints = "$src1 = $dst" in { + let isCommutable = CommutableRR in { + def NAME#8rr : BinOpRR_RFF; + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { + def NAME#16rr : BinOpRR_RFF; + def NAME#32rr : BinOpRR_RFF; + def NAME#64rr : BinOpRR_RFF; + } // isConvertibleToThreeAddress + } // isCommutable + + def NAME#8rr_REV : BinOpRR_RFF_Rev, FoldGenData; + def NAME#16rr_REV : BinOpRR_RFF_Rev, FoldGenData; + def NAME#32rr_REV : BinOpRR_RFF_Rev, FoldGenData; + def NAME#64rr_REV : BinOpRR_RFF_Rev, FoldGenData; + + def NAME#8rm : BinOpRM_RFF; + def NAME#16rm : BinOpRM_RFF; + def NAME#32rm : BinOpRM_RFF; + def NAME#64rm : BinOpRM_RFF; + + def NAME#8ri : BinOpRI_RFF<0x80, mnemonic, Xi8 , opnode, RegMRM>; + + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { + // NOTE: These are order specific, we want the ri8 forms to be listed + // first so that they are slightly preferred to the ri forms. + def NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, opnode, RegMRM>; + def NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, opnode, RegMRM>; + def NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, opnode, RegMRM>; + + def NAME#16ri : BinOpRI_RFF<0x80, mnemonic, Xi16, opnode, RegMRM>; + def NAME#32ri : BinOpRI_RFF<0x80, mnemonic, Xi32, opnode, RegMRM>; + def NAME#64ri32: BinOpRI_RFF<0x80, mnemonic, Xi64, opnode, RegMRM>; + } + } // Constraints = "$src1 = $dst" + + def NAME#8mr : BinOpMR_RMW_FF; + def NAME#16mr : BinOpMR_RMW_FF; + def NAME#32mr : BinOpMR_RMW_FF; + def NAME#64mr : BinOpMR_RMW_FF; + + // NOTE: These are order specific, we want the mi8 forms to be listed + // first so that they are slightly preferred to the mi forms. + def NAME#16mi8 : BinOpMI8_RMW_FF; + def NAME#32mi8 : BinOpMI8_RMW_FF; + let Predicates = [In64BitMode] in + def NAME#64mi8 : BinOpMI8_RMW_FF; + + def NAME#8mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi8 , opnode, MemMRM>; + def NAME#16mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi16, opnode, MemMRM>; + def NAME#32mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi32, opnode, MemMRM>; + let Predicates = [In64BitMode] in + def NAME#64mi32 : BinOpMI_RMW_FF<0x80, mnemonic, Xi64, opnode, MemMRM>; + + // These are for the disassembler since 0x82 opcode behaves like 0x80, but + // not in 64-bit mode. + let Predicates = [Not64BitMode], isCodeGenOnly = 1, ForceDisassemble = 1, + hasSideEffects = 0 in { + let Constraints = "$src1 = $dst" in + def NAME#8ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi8, null_frag, RegMRM>; + let mayLoad = 1, mayStore = 1 in + def NAME#8mi8 : BinOpMI8_RMW_FF; + } + } // Uses = [EFLAGS], Defs = [EFLAGS] + + def NAME#8i8 : BinOpAI_RFF; + def NAME#16i16 : BinOpAI_RFF; + def NAME#32i32 : BinOpAI_RFF; + def NAME#64i32 : BinOpAI_RFF; +} + +/// ArithBinOp_F - This is an arithmetic binary operator where the pattern is +/// defined with "(set EFLAGS, (...". It would be really nice to find a way +/// to factor this with the other ArithBinOp_*. +/// +multiclass ArithBinOp_F BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, + string mnemonic, Format RegMRM, Format MemMRM, + SDNode opnode, + bit CommutableRR, bit ConvertibleToThreeAddress> { + let Defs = [EFLAGS] in { + let isCommutable = CommutableRR in { + def NAME#8rr : BinOpRR_F; + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { + def NAME#16rr : BinOpRR_F; + def NAME#32rr : BinOpRR_F; + def NAME#64rr : BinOpRR_F; + } + } // isCommutable + + def NAME#8rr_REV : BinOpRR_F_Rev, FoldGenData; + def NAME#16rr_REV : BinOpRR_F_Rev, FoldGenData; + def NAME#32rr_REV : BinOpRR_F_Rev, FoldGenData; + def NAME#64rr_REV : BinOpRR_F_Rev, FoldGenData; + + def NAME#8rm : BinOpRM_F; + def NAME#16rm : BinOpRM_F; + def NAME#32rm : BinOpRM_F; + def NAME#64rm : BinOpRM_F; + + def NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>; + + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { + // NOTE: These are order specific, we want the ri8 forms to be listed + // first so that they are slightly preferred to the ri forms. + def NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>; + def NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>; + def NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>; + + def NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>; + def NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>; + def NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>; + } + + def NAME#8mr : BinOpMR_F; + def NAME#16mr : BinOpMR_F; + def NAME#32mr : BinOpMR_F; + def NAME#64mr : BinOpMR_F; + + // NOTE: These are order specific, we want the mi8 forms to be listed + // first so that they are slightly preferred to the mi forms. + def NAME#16mi8 : BinOpMI8_F; + def NAME#32mi8 : BinOpMI8_F; + let Predicates = [In64BitMode] in + def NAME#64mi8 : BinOpMI8_F; + + def NAME#8mi : BinOpMI_F<0x80, mnemonic, Xi8 , opnode, MemMRM>; + def NAME#16mi : BinOpMI_F<0x80, mnemonic, Xi16, opnode, MemMRM>; + def NAME#32mi : BinOpMI_F<0x80, mnemonic, Xi32, opnode, MemMRM>; + let Predicates = [In64BitMode] in + def NAME#64mi32 : BinOpMI_F<0x80, mnemonic, Xi64, opnode, MemMRM>; + + // These are for the disassembler since 0x82 opcode behaves like 0x80, but + // not in 64-bit mode. + let Predicates = [Not64BitMode], isCodeGenOnly = 1, ForceDisassemble = 1, + hasSideEffects = 0 in { + def NAME#8ri8 : BinOpRI8_F<0x82, mnemonic, Xi8, null_frag, RegMRM>; + let mayLoad = 1 in + def NAME#8mi8 : BinOpMI8_F; + } + } // Defs = [EFLAGS] + + def NAME#8i8 : BinOpAI_F; + def NAME#16i16 : BinOpAI_F; + def NAME#32i32 : BinOpAI_F; + def NAME#64i32 : BinOpAI_F; +} + + +defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m, + X86and_flag, and, 1, 0>; +defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m, + X86or_flag, or, 1, 0>; +defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m, + X86xor_flag, xor, 1, 0>; +defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m, + X86add_flag, add, 1, 1>; +let isCompare = 1 in { +defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m, + X86sub_flag, sub, 0, 0>; +} + +// Arithmetic. +defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag, + 1, 0>; +defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag, + 0, 0>; + +let isCompare = 1 in { +defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>; +} + + +//===----------------------------------------------------------------------===// +// Semantically, test instructions are similar like AND, except they don't +// generate a result. From an encoding perspective, they are very different: +// they don't have all the usual imm8 and REV forms, and are encoded into a +// different space. +def X86testpat : PatFrag<(ops node:$lhs, node:$rhs), + (X86cmp (and_su node:$lhs, node:$rhs), 0)>; + +let isCompare = 1 in { + let Defs = [EFLAGS] in { + let isCommutable = 1 in { + def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat>; + def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat>; + def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat>; + def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat>; + } // isCommutable + + def TEST8mr : BinOpMR_F<0x84, "test", Xi8 , X86testpat>; + def TEST16mr : BinOpMR_F<0x84, "test", Xi16, X86testpat>; + def TEST32mr : BinOpMR_F<0x84, "test", Xi32, X86testpat>; + def TEST64mr : BinOpMR_F<0x84, "test", Xi64, X86testpat>; + + def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>; + def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>; + def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>; + let Predicates = [In64BitMode] in + def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>; + + def TEST8mi : BinOpMI_F<0xF6, "test", Xi8 , X86testpat, MRM0m>; + def TEST16mi : BinOpMI_F<0xF6, "test", Xi16, X86testpat, MRM0m>; + def TEST32mi : BinOpMI_F<0xF6, "test", Xi32, X86testpat, MRM0m>; + let Predicates = [In64BitMode] in + def TEST64mi32 : BinOpMI_F<0xF6, "test", Xi64, X86testpat, MRM0m>; + + def TEST8mi_alt: BinOpMI_F<0xF6, "test", Xi8 , X86testpat, MRM1m>; + def TEST16mi_alt : BinOpMI_F<0xF6, "test", Xi16, X86testpat, MRM1m>; + def TEST32mi_alt: BinOpMI_F<0xF6, "test", Xi32, X86testpat, MRM1m>; + let Predicates = [In64BitMode] in + def TEST64mi32_alt: BinOpMI_F<0xF6, "test", Xi64, X86testpat, MRM1m>; + + def TEST8ri_alt : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM1r>; + def TEST16ri_alt : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM1r>; + def TEST32ri_alt : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM1r>; + let Predicates = [In64BitMode] in + def TEST64ri32_alt : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM1r>; + } // Defs = [EFLAGS] + + def TEST8i8 : BinOpAI_F<0xA8, "test", Xi8 , AL, + "{$src, %al|al, $src}">; + def TEST16i16 : BinOpAI_F<0xA8, "test", Xi16, AX, + "{$src, %ax|ax, $src}">; + def TEST32i32 : BinOpAI_F<0xA8, "test", Xi32, EAX, + "{$src, %eax|eax, $src}">; + def TEST64i32 : BinOpAI_F<0xA8, "test", Xi64, RAX, + "{$src, %rax|rax, $src}">; +} // isCompare + +//===----------------------------------------------------------------------===// +// ANDN Instruction +// +multiclass bmi_andn { + def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>, + Sched<[WriteALU]>; + def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, EFLAGS, + (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>, + Sched<[WriteALULd, ReadAfterLd]>; +} + +// Complexity is reduced to give and with immediate a chance to match first. +let Predicates = [HasBMI], Defs = [EFLAGS], AddedComplexity = -6 in { + defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8PS, VEX_4V; + defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8PS, VEX_4V, VEX_W; +} + +let Predicates = [HasBMI], AddedComplexity = -6 in { + def : Pat<(and (not GR32:$src1), GR32:$src2), + (ANDN32rr GR32:$src1, GR32:$src2)>; + def : Pat<(and (not GR64:$src1), GR64:$src2), + (ANDN64rr GR64:$src1, GR64:$src2)>; + def : Pat<(and (not GR32:$src1), (loadi32 addr:$src2)), + (ANDN32rm GR32:$src1, addr:$src2)>; + def : Pat<(and (not GR64:$src1), (loadi64 addr:$src2)), + (ANDN64rm GR64:$src1, addr:$src2)>; +} + +//===----------------------------------------------------------------------===// +// MULX Instruction +// +multiclass bmi_mulx { +let hasSideEffects = 0 in { + let isCommutable = 1 in + def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src), + !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"), + []>, T8XD, VEX_4V, Sched<[sched, WriteIMulH]>; + + let mayLoad = 1 in + def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src), + !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"), + []>, T8XD, VEX_4V, Sched<[sched.Folded, WriteIMulH]>; +} +} + +let Predicates = [HasBMI2] in { + let Uses = [EDX] in + defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, WriteIMul>; + let Uses = [RDX] in + defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteIMul64>, VEX_W; +} + +//===----------------------------------------------------------------------===// +// ADCX and ADOX Instructions +// +let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS], + Constraints = "$src1 = $dst", AddedComplexity = 10 in { + let SchedRW = [WriteADC] in { + def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2), + "adcx{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, EFLAGS, + (X86adc_flag GR32:$src1, GR32:$src2, EFLAGS))]>, T8PD; + def ADCX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), + "adcx{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, EFLAGS, + (X86adc_flag GR64:$src1, GR64:$src2, EFLAGS))]>, T8PD; + + // We don't have patterns for ADOX yet. + let hasSideEffects = 0 in { + def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2), + "adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS; + + def ADOX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), + "adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS; + } // hasSideEffects = 0 + } // SchedRW + + let mayLoad = 1, SchedRW = [WriteADCLd, ReadAfterLd] in { + def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$src1, i32mem:$src2), + "adcx{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, EFLAGS, + (X86adc_flag GR32:$src1, (loadi32 addr:$src2), EFLAGS))]>, + T8PD; + + def ADCX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$src1, i64mem:$src2), + "adcx{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, EFLAGS, + (X86adc_flag GR64:$src1, (loadi64 addr:$src2), EFLAGS))]>, + T8PD; + + // We don't have patterns for ADOX yet. + let hasSideEffects = 0 in { + def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$src1, i32mem:$src2), + "adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS; + + def ADOX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$src1, i64mem:$src2), + "adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS; + } // hasSideEffects = 0 + } // mayLoad = 1, SchedRW = [WriteADCLd] +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrCMovSetCC.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrCMovSetCC.td new file mode 100644 index 0000000..eda4ba5 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrCMovSetCC.td @@ -0,0 +1,116 @@ +//===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 conditional move and set on condition +// instructions. +// +//===----------------------------------------------------------------------===// + + +// CMOV instructions. +multiclass CMOV opc, string Mnemonic, X86FoldableSchedWrite Sched, + PatLeaf CondNode> { + let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", + isCommutable = 1, SchedRW = [Sched] in { + def NAME#16rr + : I, + TB, OpSize16; + def NAME#32rr + : I, + TB, OpSize32; + def NAME#64rr + :RI, TB; + } + + let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", + SchedRW = [Sched.Folded, ReadAfterLd] in { + def NAME#16rm + : I, TB, OpSize16; + def NAME#32rm + : I, TB, OpSize32; + def NAME#64rm + :RI, TB; + } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst" +} // end multiclass + + +// Conditional Moves. +defm CMOVO : CMOV<0x40, "cmovo" , WriteCMOV, X86_COND_O>; +defm CMOVNO : CMOV<0x41, "cmovno", WriteCMOV, X86_COND_NO>; +defm CMOVB : CMOV<0x42, "cmovb" , WriteCMOV, X86_COND_B>; +defm CMOVAE : CMOV<0x43, "cmovae", WriteCMOV, X86_COND_AE>; +defm CMOVE : CMOV<0x44, "cmove" , WriteCMOV, X86_COND_E>; +defm CMOVNE : CMOV<0x45, "cmovne", WriteCMOV, X86_COND_NE>; +defm CMOVBE : CMOV<0x46, "cmovbe", WriteCMOV2, X86_COND_BE>; +defm CMOVA : CMOV<0x47, "cmova" , WriteCMOV2, X86_COND_A>; +defm CMOVS : CMOV<0x48, "cmovs" , WriteCMOV, X86_COND_S>; +defm CMOVNS : CMOV<0x49, "cmovns", WriteCMOV, X86_COND_NS>; +defm CMOVP : CMOV<0x4A, "cmovp" , WriteCMOV, X86_COND_P>; +defm CMOVNP : CMOV<0x4B, "cmovnp", WriteCMOV, X86_COND_NP>; +defm CMOVL : CMOV<0x4C, "cmovl" , WriteCMOV, X86_COND_L>; +defm CMOVGE : CMOV<0x4D, "cmovge", WriteCMOV, X86_COND_GE>; +defm CMOVLE : CMOV<0x4E, "cmovle", WriteCMOV, X86_COND_LE>; +defm CMOVG : CMOV<0x4F, "cmovg" , WriteCMOV, X86_COND_G>; + + +// SetCC instructions. +multiclass SETCC opc, string Mnemonic, PatLeaf OpNode> { + let Uses = [EFLAGS] in { + def r : I, + TB, Sched<[WriteSETCC]>; + def m : I, + TB, Sched<[WriteSETCCStore]>; + } // Uses = [EFLAGS] +} + +defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set +defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set +defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than +defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal +defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to +defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to +defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal +defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than +defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set +defm SETNS : SETCC<0x99, "setns", X86_COND_NS>; // is not signed +defm SETP : SETCC<0x9A, "setp", X86_COND_P>; // is parity bit set +defm SETNP : SETCC<0x9B, "setnp", X86_COND_NP>; // is parity bit not set +defm SETL : SETCC<0x9C, "setl", X86_COND_L>; // signed less than +defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>; // signed greater or equal +defm SETLE : SETCC<0x9E, "setle", X86_COND_LE>; // signed less than or equal +defm SETG : SETCC<0x9F, "setg", X86_COND_G>; // signed greater than + +// SALC is an undocumented instruction. Information for this instruction can be found +// here http://www.rcollins.org/secrets/opcodes/SALC.html +// Set AL if carry. +let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in { + def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>, Requires<[Not64BitMode]>; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrCompiler.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrCompiler.td new file mode 100644 index 0000000..76b93bd --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrCompiler.td @@ -0,0 +1,2103 @@ +//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the various pseudo instructions used by the compiler, +// as well as Pat patterns used during instruction selection. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Pattern Matching Support + +def GetLo32XForm : SDNodeXFormgetZExtValue(), SDLoc(N)); +}]>; + +def GetLo8XForm : SDNodeXFormgetZExtValue(), SDLoc(N)); +}]>; + + +//===----------------------------------------------------------------------===// +// Random Pseudo Instructions. + +// PIC base construction. This expands to code that looks like this: +// call $next_inst +// popl %destreg" +let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP], + SchedRW = [WriteJump] in + def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), + "", []>; + +// 64-bit large code model PIC base construction. +let hasSideEffects = 0, mayLoad = 1, isNotDuplicable = 1, SchedRW = [WriteJump] in + def MOVGOT64r : PseudoI<(outs GR64:$reg), + (ins GR64:$scratch, i64i32imm_pcrel:$got), []>; + +// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into +// a stack adjustment and the codegen must know that they may modify the stack +// pointer before prolog-epilog rewriting occurs. +// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become +// sub / add which can clobber EFLAGS. +let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in { +def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), + (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), + "#ADJCALLSTACKDOWN", []>, Requires<[NotLP64]>; +def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), + "#ADJCALLSTACKUP", + [(X86callseq_end timm:$amt1, timm:$amt2)]>, + Requires<[NotLP64]>; +} +def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), + (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>; + + +// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into +// a stack adjustment and the codegen must know that they may modify the stack +// pointer before prolog-epilog rewriting occurs. +// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become +// sub / add which can clobber EFLAGS. +let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in { +def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), + (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), + "#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>; +def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), + "#ADJCALLSTACKUP", + [(X86callseq_end timm:$amt1, timm:$amt2)]>, + Requires<[IsLP64]>; +} +def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), + (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>; + +let SchedRW = [WriteSystem] in { + +// x86-64 va_start lowering magic. +let usesCustomInserter = 1, Defs = [EFLAGS] in { +def VASTART_SAVE_XMM_REGS : I<0, Pseudo, + (outs), + (ins GR8:$al, + i64imm:$regsavefi, i64imm:$offset, + variable_ops), + "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", + [(X86vastart_save_xmm_regs GR8:$al, + imm:$regsavefi, + imm:$offset), + (implicit EFLAGS)]>; + +// The VAARG_64 pseudo-instruction takes the address of the va_list, +// and places the address of the next argument into a register. +let Defs = [EFLAGS] in +def VAARG_64 : I<0, Pseudo, + (outs GR64:$dst), + (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), + "#VAARG_64 $dst, $ap, $size, $mode, $align", + [(set GR64:$dst, + (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), + (implicit EFLAGS)]>; + + +// When using segmented stacks these are lowered into instructions which first +// check if the current stacklet has enough free memory. If it does, memory is +// allocated by bumping the stack pointer. Otherwise memory is allocated from +// the heap. + +let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in +def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), + "# variable sized alloca for segmented stacks", + [(set GR32:$dst, + (X86SegAlloca GR32:$size))]>, + Requires<[NotLP64]>; + +let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in +def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), + "# variable sized alloca for segmented stacks", + [(set GR64:$dst, + (X86SegAlloca GR64:$size))]>, + Requires<[In64BitMode]>; +} + +// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows +// targets. These calls are needed to probe the stack when allocating more than +// 4k bytes in one go. Touching the stack at 4K increments is necessary to +// ensure that the guard pages used by the OS virtual memory manager are +// allocated in correct sequence. +// The main point of having separate instruction are extra unmodelled effects +// (compared to ordinary calls) like stack pointer change. + +let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in +def WIN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size), + "# dynamic stack allocation", + [(X86WinAlloca GR32:$size)]>, + Requires<[NotLP64]>; + +let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in +def WIN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size), + "# dynamic stack allocation", + [(X86WinAlloca GR64:$size)]>, + Requires<[In64BitMode]>; +} // SchedRW + +// These instructions XOR the frame pointer into a GPR. They are used in some +// stack protection schemes. These are post-RA pseudos because we only know the +// frame register after register allocation. +let Constraints = "$src = $dst", isPseudo = 1, Defs = [EFLAGS] in { + def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src), + "xorl\t$$FP, $src", []>, + Requires<[NotLP64]>, Sched<[WriteALU]>; + def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src), + "xorq\t$$FP $src", []>, + Requires<[In64BitMode]>, Sched<[WriteALU]>; +} + +//===----------------------------------------------------------------------===// +// EH Pseudo Instructions +// +let SchedRW = [WriteSystem] in { +let isTerminator = 1, isReturn = 1, isBarrier = 1, + hasCtrlDep = 1, isCodeGenOnly = 1 in { +def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), + "ret\t#eh_return, addr: $addr", + [(X86ehret GR32:$addr)]>, Sched<[WriteJumpLd]>; + +} + +let isTerminator = 1, isReturn = 1, isBarrier = 1, + hasCtrlDep = 1, isCodeGenOnly = 1 in { +def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), + "ret\t#eh_return, addr: $addr", + [(X86ehret GR64:$addr)]>, Sched<[WriteJumpLd]>; + +} + +let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, + isCodeGenOnly = 1, isReturn = 1 in { + def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>; + + // CATCHRET needs a custom inserter for SEH. + let usesCustomInserter = 1 in + def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from), + "# CATCHRET", + [(catchret bb:$dst, bb:$from)]>; +} + +let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1, + usesCustomInserter = 1 in +def CATCHPAD : I<0, Pseudo, (outs), (ins), "# CATCHPAD", [(catchpad)]>; + +// This instruction is responsible for re-establishing stack pointers after an +// exception has been caught and we are rejoining normal control flow in the +// parent function or funclet. It generally sets ESP and EBP, and optionally +// ESI. It is only needed for 32-bit WinEH, as the runtime restores CSRs for us +// elsewhere. +let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in +def EH_RESTORE : I<0, Pseudo, (outs), (ins), "# EH_RESTORE", []>; + +let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, + usesCustomInserter = 1 in { + def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), + "#EH_SJLJ_SETJMP32", + [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, + Requires<[Not64BitMode]>; + def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), + "#EH_SJLJ_SETJMP64", + [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, + Requires<[In64BitMode]>; + let isTerminator = 1 in { + def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), + "#EH_SJLJ_LONGJMP32", + [(X86eh_sjlj_longjmp addr:$buf)]>, + Requires<[Not64BitMode]>; + def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), + "#EH_SJLJ_LONGJMP64", + [(X86eh_sjlj_longjmp addr:$buf)]>, + Requires<[In64BitMode]>; + } +} + +let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { + def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), + "#EH_SjLj_Setup\t$dst", []>; +} +} // SchedRW + +//===----------------------------------------------------------------------===// +// Pseudo instructions used by unwind info. +// +let isPseudo = 1, SchedRW = [WriteSystem] in { + def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), + "#SEH_PushReg $reg", []>; + def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), + "#SEH_SaveReg $reg, $dst", []>; + def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), + "#SEH_SaveXMM $reg, $dst", []>; + def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), + "#SEH_StackAlloc $size", []>; + def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), + "#SEH_SetFrame $reg, $offset", []>; + def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), + "#SEH_PushFrame $mode", []>; + def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), + "#SEH_EndPrologue", []>; + def SEH_Epilogue : I<0, Pseudo, (outs), (ins), + "#SEH_Epilogue", []>; +} + +//===----------------------------------------------------------------------===// +// Pseudo instructions used by segmented stacks. +// + +// This is lowered into a RET instruction by MCInstLower. We need +// this so that we don't have to have a MachineBasicBlock which ends +// with a RET and also has successors. +let isPseudo = 1, SchedRW = [WriteJumpLd] in { +def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>; + +// This instruction is lowered to a RET followed by a MOV. The two +// instructions are not generated on a higher level since then the +// verifier sees a MachineBasicBlock ending with a non-terminator. +def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>; +} + +//===----------------------------------------------------------------------===// +// Alias Instructions +//===----------------------------------------------------------------------===// + +// Alias instruction mapping movr0 to xor. +// FIXME: remove when we can teach regalloc that xor reg, reg is ok. +let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, + isPseudo = 1, AddedComplexity = 10 in +def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", + [(set GR32:$dst, 0)]>, Sched<[WriteZero]>; + +// Other widths can also make use of the 32-bit xor, which may have a smaller +// encoding and avoid partial register updates. +let AddedComplexity = 10 in { +def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; +def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; +def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>; +} + +let Predicates = [OptForSize, Not64BitMode], + AddedComplexity = 10 in { + let SchedRW = [WriteALU] in { + // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC, + // which only require 3 bytes compared to MOV32ri which requires 5. + let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in { + def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", + [(set GR32:$dst, 1)]>; + def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", + [(set GR32:$dst, -1)]>; + } + } // SchedRW + + // MOV16ri is 4 bytes, so the instructions above are smaller. + def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>; + def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>; +} + +let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5, + SchedRW = [WriteALU] in { +// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1. +def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "", + [(set GR32:$dst, i32immSExt8:$src)]>, + Requires<[OptForMinSize, NotWin64WithoutFP]>; +def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", + [(set GR64:$dst, i64immSExt8:$src)]>, + Requires<[OptForMinSize, NotWin64WithoutFP]>; +} + +// Materialize i64 constant where top 32-bits are zero. This could theoretically +// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however +// that would make it more difficult to rematerialize. +let isReMaterializable = 1, isAsCheapAsAMove = 1, + isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteMove] in +def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", []>; + +// This 64-bit pseudo-move can be used for both a 64-bit constant that is +// actually the zero-extension of a 32-bit constant and for labels in the +// x86-64 small code model. +def mov64imm32 : ComplexPattern; + +let AddedComplexity = 1 in +def : Pat<(i64 mov64imm32:$src), + (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>; + +// Use sbb to materialize carry bit. +let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in { +// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. +// However, Pat<> can't replicate the destination reg into the inputs of the +// result. +def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "", + [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; +def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "", + [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; +def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", + [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; +def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", + [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; +} // isCodeGenOnly + + +def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C16r)>; +def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C32r)>; +def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C64r)>; + +def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C16r)>; +def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C32r)>; +def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C64r)>; + +// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and +// will be eliminated and that the sbb can be extended up to a wider type. When +// this happens, it is great. However, if we are left with an 8-bit sbb and an +// and, we might as well just match it as a setb. +def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), + (SETBr)>; + +// (add OP, SETB) -> (adc OP, 0) +def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op), + (ADC8ri GR8:$op, 0)>; +def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op), + (ADC32ri8 GR32:$op, 0)>; +def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op), + (ADC64ri8 GR64:$op, 0)>; + +// (sub OP, SETB) -> (sbb OP, 0) +def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)), + (SBB8ri GR8:$op, 0)>; +def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)), + (SBB32ri8 GR32:$op, 0)>; +def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)), + (SBB64ri8 GR64:$op, 0)>; + +// (sub OP, SETCC_CARRY) -> (adc OP, 0) +def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))), + (ADC8ri GR8:$op, 0)>; +def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))), + (ADC32ri8 GR32:$op, 0)>; +def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))), + (ADC64ri8 GR64:$op, 0)>; + +//===----------------------------------------------------------------------===// +// String Pseudo Instructions +// +let SchedRW = [WriteMicrocoded] in { +let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { +def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", + [(X86rep_movs i8)]>, REP, + Requires<[Not64BitMode]>; +def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", + [(X86rep_movs i16)]>, REP, OpSize16, + Requires<[Not64BitMode]>; +def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", + [(X86rep_movs i32)]>, REP, OpSize32, + Requires<[Not64BitMode]>; +} + +let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { +def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", + [(X86rep_movs i8)]>, REP, + Requires<[In64BitMode]>; +def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", + [(X86rep_movs i16)]>, REP, OpSize16, + Requires<[In64BitMode]>; +def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", + [(X86rep_movs i32)]>, REP, OpSize32, + Requires<[In64BitMode]>; +def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", + [(X86rep_movs i64)]>, REP, + Requires<[In64BitMode]>; +} + +// FIXME: Should use "(X86rep_stos AL)" as the pattern. +let Defs = [ECX,EDI], isCodeGenOnly = 1 in { + let Uses = [AL,ECX,EDI] in + def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", + [(X86rep_stos i8)]>, REP, + Requires<[Not64BitMode]>; + let Uses = [AX,ECX,EDI] in + def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", + [(X86rep_stos i16)]>, REP, OpSize16, + Requires<[Not64BitMode]>; + let Uses = [EAX,ECX,EDI] in + def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", + [(X86rep_stos i32)]>, REP, OpSize32, + Requires<[Not64BitMode]>; +} + +let Defs = [RCX,RDI], isCodeGenOnly = 1 in { + let Uses = [AL,RCX,RDI] in + def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", + [(X86rep_stos i8)]>, REP, + Requires<[In64BitMode]>; + let Uses = [AX,RCX,RDI] in + def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", + [(X86rep_stos i16)]>, REP, OpSize16, + Requires<[In64BitMode]>; + let Uses = [RAX,RCX,RDI] in + def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", + [(X86rep_stos i32)]>, REP, OpSize32, + Requires<[In64BitMode]>; + + let Uses = [RAX,RCX,RDI] in + def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", + [(X86rep_stos i64)]>, REP, + Requires<[In64BitMode]>; +} +} // SchedRW + +//===----------------------------------------------------------------------===// +// Thread Local Storage Instructions +// +let SchedRW = [WriteSystem] in { + +// ELF TLS Support +// All calls clobber the non-callee saved registers. ESP is marked as +// a use to prevent stack-pointer assignments that appear immediately +// before calls from potentially appearing dead. +let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, + ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, + MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, + XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, + XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], + usesCustomInserter = 1, Uses = [ESP, SSP] in { +def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), + "# TLS_addr32", + [(X86tlsaddr tls32addr:$sym)]>, + Requires<[Not64BitMode]>; +def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), + "# TLS_base_addr32", + [(X86tlsbaseaddr tls32baseaddr:$sym)]>, + Requires<[Not64BitMode]>; +} + +// All calls clobber the non-callee saved registers. RSP is marked as +// a use to prevent stack-pointer assignments that appear immediately +// before calls from potentially appearing dead. +let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, + FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, + ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, + MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, + XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, + XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], + usesCustomInserter = 1, Uses = [RSP, SSP] in { +def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), + "# TLS_addr64", + [(X86tlsaddr tls64addr:$sym)]>, + Requires<[In64BitMode]>; +def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), + "# TLS_base_addr64", + [(X86tlsbaseaddr tls64baseaddr:$sym)]>, + Requires<[In64BitMode]>; +} + +// Darwin TLS Support +// For i386, the address of the thunk is passed on the stack, on return the +// address of the variable is in %eax. %ecx is trashed during the function +// call. All other registers are preserved. +let Defs = [EAX, ECX, EFLAGS, DF], + Uses = [ESP, SSP], + usesCustomInserter = 1 in +def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), + "# TLSCall_32", + [(X86TLSCall addr:$sym)]>, + Requires<[Not64BitMode]>; + +// For x86_64, the address of the thunk is passed in %rdi, but the +// pseudo directly use the symbol, so do not add an implicit use of +// %rdi. The lowering will do the right thing with RDI. +// On return the address of the variable is in %rax. All other +// registers are preserved. +let Defs = [RAX, EFLAGS, DF], + Uses = [RSP, SSP], + usesCustomInserter = 1 in +def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), + "# TLSCall_64", + [(X86TLSCall addr:$sym)]>, + Requires<[In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Conditional Move Pseudo Instructions + +// CMOV* - Used to implement the SELECT DAG operation. Expanded after +// instruction selection into a branch sequence. +multiclass CMOVrr_PSEUDO { + def CMOV#NAME : I<0, Pseudo, + (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond), + "#CMOV_"#NAME#" PSEUDO!", + [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond, + EFLAGS)))]>; +} + +let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in { + // X86 doesn't have 8-bit conditional moves. Use a customInserter to + // emit control flow. An alternative to this is to mark i8 SELECT as Promote, + // however that requires promoting the operands, and can induce additional + // i8 register pressure. + defm _GR8 : CMOVrr_PSEUDO; + + let Predicates = [NoCMov] in { + defm _GR32 : CMOVrr_PSEUDO; + defm _GR16 : CMOVrr_PSEUDO; + } // Predicates = [NoCMov] + + // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no + // SSE1/SSE2. + let Predicates = [FPStackf32] in + defm _RFP32 : CMOVrr_PSEUDO; + + let Predicates = [FPStackf64] in + defm _RFP64 : CMOVrr_PSEUDO; + + defm _RFP80 : CMOVrr_PSEUDO; + + defm _FR32 : CMOVrr_PSEUDO; + defm _FR64 : CMOVrr_PSEUDO; + defm _F128 : CMOVrr_PSEUDO; + defm _V4F32 : CMOVrr_PSEUDO; + defm _V2F64 : CMOVrr_PSEUDO; + defm _V2I64 : CMOVrr_PSEUDO; + defm _V8F32 : CMOVrr_PSEUDO; + defm _V4F64 : CMOVrr_PSEUDO; + defm _V4I64 : CMOVrr_PSEUDO; + defm _V8I64 : CMOVrr_PSEUDO; + defm _V8F64 : CMOVrr_PSEUDO; + defm _V16F32 : CMOVrr_PSEUDO; + defm _V8I1 : CMOVrr_PSEUDO; + defm _V16I1 : CMOVrr_PSEUDO; + defm _V32I1 : CMOVrr_PSEUDO; + defm _V64I1 : CMOVrr_PSEUDO; +} // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] + +//===----------------------------------------------------------------------===// +// Normal-Instructions-With-Lock-Prefix Pseudo Instructions +//===----------------------------------------------------------------------===// + +// FIXME: Use normal instructions and add lock prefix dynamically. + +// Memory barriers + +// TODO: Get this to fold the constant into the instruction. +let isCodeGenOnly = 1, Defs = [EFLAGS] in +def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero), + "or{l}\t{$zero, $dst|$dst, $zero}", []>, + Requires<[Not64BitMode]>, OpSize32, LOCK, + Sched<[WriteALULd, WriteRMW]>; + +let hasSideEffects = 1 in +def Int_MemBarrier : I<0, Pseudo, (outs), (ins), + "#MEMBARRIER", + [(X86MemBarrier)]>, Sched<[WriteLoad]>; + +// RegOpc corresponds to the mr version of the instruction +// ImmOpc corresponds to the mi version of the instruction +// ImmOpc8 corresponds to the mi8 version of the instruction +// ImmMod corresponds to the instruction format of the mi and mi8 versions +multiclass LOCK_ArithBinOp RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, + Format ImmMod, SDNode Op, string mnemonic> { +let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, + SchedRW = [WriteALULd, WriteRMW] in { + +def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, + RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, + MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), + !strconcat(mnemonic, "{b}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK; + +def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, + RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, + MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), + !strconcat(mnemonic, "{w}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>, + OpSize16, LOCK; + +def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, + RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, + MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), + !strconcat(mnemonic, "{l}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>, + OpSize32, LOCK; + +def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, + RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, + MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), + !strconcat(mnemonic, "{q}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK; + +def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, + ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, + ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), + !strconcat(mnemonic, "{b}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK; + +def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, + ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, + ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), + !strconcat(mnemonic, "{w}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>, + OpSize16, LOCK; + +def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, + ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, + ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), + !strconcat(mnemonic, "{l}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>, + OpSize32, LOCK; + +def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, + ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, + ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), + !strconcat(mnemonic, "{q}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>, + LOCK; + +def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, + ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, + ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), + !strconcat(mnemonic, "{w}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>, + OpSize16, LOCK; + +def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, + ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, + ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), + !strconcat(mnemonic, "{l}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>, + OpSize32, LOCK; + +def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, + ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, + ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), + !strconcat(mnemonic, "{q}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>, + LOCK; +} + +} + +defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">; +defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">; +defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">; +defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">; +defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">; + +multiclass LOCK_ArithUnOp Opc8, bits<8> Opc, Format Form, + string frag, string mnemonic> { +let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, + SchedRW = [WriteALULd, WriteRMW] in { +def NAME#8m : I(frag # "_8") addr:$dst))]>, + LOCK; +def NAME#16m : I(frag # "_16") addr:$dst))]>, + OpSize16, LOCK; +def NAME#32m : I(frag # "_32") addr:$dst))]>, + OpSize32, LOCK; +def NAME#64m : RI(frag # "_64") addr:$dst))]>, + LOCK; +} +} + +multiclass unary_atomic_intrin { + def _8 : PatFrag<(ops node:$ptr), + (atomic_op node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i8; + }]>; + def _16 : PatFrag<(ops node:$ptr), + (atomic_op node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i16; + }]>; + def _32 : PatFrag<(ops node:$ptr), + (atomic_op node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i32; + }]>; + def _64 : PatFrag<(ops node:$ptr), + (atomic_op node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i64; + }]>; +} + +defm X86lock_inc : unary_atomic_intrin; +defm X86lock_dec : unary_atomic_intrin; + +defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "X86lock_inc", "inc">; +defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "X86lock_dec", "dec">; + +// Atomic compare and swap. +multiclass LCMPXCHG_UnOp Opc, Format Form, string mnemonic, + SDPatternOperator frag, X86MemOperand x86memop> { +let isCodeGenOnly = 1, usesCustomInserter = 1 in { + def NAME : I, TB, LOCK; +} +} + +multiclass LCMPXCHG_BinOp Opc8, bits<8> Opc, Format Form, + string mnemonic, SDPatternOperator frag> { +let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in { + let Defs = [AL, EFLAGS], Uses = [AL] in + def NAME#8 : I, TB, LOCK; + let Defs = [AX, EFLAGS], Uses = [AX] in + def NAME#16 : I, TB, OpSize16, LOCK; + let Defs = [EAX, EFLAGS], Uses = [EAX] in + def NAME#32 : I, TB, OpSize32, LOCK; + let Defs = [RAX, EFLAGS], Uses = [RAX] in + def NAME#64 : RI, TB, LOCK; +} +} + +let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], + SchedRW = [WriteALULd, WriteRMW] in { +defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", X86cas8, i64mem>; +} + +// This pseudo must be used when the frame uses RBX as +// the base pointer. Indeed, in such situation RBX is a reserved +// register and the register allocator will ignore any use/def of +// it. In other words, the register will not fix the clobbering of +// RBX that will happen when setting the arguments for the instruction. +// +// Unlike the actual related instruction, we mark that this one +// defines EBX (instead of using EBX). +// The rationale is that we will define RBX during the expansion of +// the pseudo. The argument feeding EBX is ebx_input. +// +// The additional argument, $ebx_save, is a temporary register used to +// save the value of RBX across the actual instruction. +// +// To make sure the register assigned to $ebx_save does not interfere with +// the definition of the actual instruction, we use a definition $dst which +// is tied to $rbx_save. That way, the live-range of $rbx_save spans across +// the instruction and we are sure we will have a valid register to restore +// the value of RBX. +let Defs = [EAX, EDX, EBX, EFLAGS], Uses = [EAX, ECX, EDX], + SchedRW = [WriteALULd, WriteRMW], isCodeGenOnly = 1, isPseudo = 1, + Constraints = "$ebx_save = $dst", usesCustomInserter = 1 in { +def LCMPXCHG8B_SAVE_EBX : + I<0, Pseudo, (outs GR32:$dst), + (ins i64mem:$ptr, GR32:$ebx_input, GR32:$ebx_save), + !strconcat("cmpxchg8b", "\t$ptr"), + [(set GR32:$dst, (X86cas8save_ebx addr:$ptr, GR32:$ebx_input, + GR32:$ebx_save))]>; +} + + +let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], + Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in { +defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b", + X86cas16, i128mem>, REX_W; +} + +// Same as LCMPXCHG8B_SAVE_RBX but for the 16 Bytes variant. +let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX], + Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW], + isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst", + usesCustomInserter = 1 in { +def LCMPXCHG16B_SAVE_RBX : + I<0, Pseudo, (outs GR64:$dst), + (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), + !strconcat("cmpxchg16b", "\t$ptr"), + [(set GR64:$dst, (X86cas16save_rbx addr:$ptr, GR64:$rbx_input, + GR64:$rbx_save))]>; +} + +defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>; + +// Atomic exchange and add +multiclass ATOMIC_LOAD_BINOP opc8, bits<8> opc, string mnemonic, + string frag> { + let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1, + SchedRW = [WriteALULd, WriteRMW] in { + def NAME#8 : I(frag # "_8") addr:$ptr, GR8:$val))]>; + def NAME#16 : I(frag # "_16") addr:$ptr, GR16:$val))]>, + OpSize16; + def NAME#32 : I(frag # "_32") addr:$ptr, GR32:$val))]>, + OpSize32; + def NAME#64 : RI(frag # "_64") addr:$ptr, GR64:$val))]>; + } +} + +defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK; + +/* The following multiclass tries to make sure that in code like + * x.store (immediate op x.load(acquire), release) + * and + * x.store (register op x.load(acquire), release) + * an operation directly on memory is generated instead of wasting a register. + * It is not automatic as atomic_store/load are only lowered to MOV instructions + * extremely late to prevent them from being accidentally reordered in the backend + * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) + */ +multiclass RELEASE_BINOP_MI { + def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), + "#BINOP "#NAME#"8mi PSEUDO!", + [(atomic_store_8 addr:$dst, (op + (atomic_load_8 addr:$dst), (i8 imm:$src)))]>; + def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src), + "#BINOP "#NAME#"8mr PSEUDO!", + [(atomic_store_8 addr:$dst, (op + (atomic_load_8 addr:$dst), GR8:$src))]>; + // NAME#16 is not generated as 16-bit arithmetic instructions are considered + // costly and avoided as far as possible by this backend anyway + def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), + "#BINOP "#NAME#"32mi PSEUDO!", + [(atomic_store_32 addr:$dst, (op + (atomic_load_32 addr:$dst), (i32 imm:$src)))]>; + def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), + "#BINOP "#NAME#"32mr PSEUDO!", + [(atomic_store_32 addr:$dst, (op + (atomic_load_32 addr:$dst), GR32:$src))]>; + def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), + "#BINOP "#NAME#"64mi32 PSEUDO!", + [(atomic_store_64 addr:$dst, (op + (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>; + def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), + "#BINOP "#NAME#"64mr PSEUDO!", + [(atomic_store_64 addr:$dst, (op + (atomic_load_64 addr:$dst), GR64:$src))]>; +} +let Defs = [EFLAGS], SchedRW = [WriteMicrocoded] in { + defm RELEASE_ADD : RELEASE_BINOP_MI; + defm RELEASE_AND : RELEASE_BINOP_MI; + defm RELEASE_OR : RELEASE_BINOP_MI; + defm RELEASE_XOR : RELEASE_BINOP_MI; + // Note: we don't deal with sub, because substractions of constants are + // optimized into additions before this code can run. +} + +// Same as above, but for floating-point. +// FIXME: imm version. +// FIXME: Version that doesn't clobber $src, using AVX's VADDSS. +// FIXME: This could also handle SIMD operations with *ps and *pd instructions. +let usesCustomInserter = 1, SchedRW = [WriteMicrocoded] in { +multiclass RELEASE_FP_BINOP_MI { + def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src), + "#BINOP "#NAME#"32mr PSEUDO!", + [(atomic_store_32 addr:$dst, + (i32 (bitconvert (op + (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))), + FR32:$src))))]>, Requires<[HasSSE1]>; + def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src), + "#BINOP "#NAME#"64mr PSEUDO!", + [(atomic_store_64 addr:$dst, + (i64 (bitconvert (op + (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))), + FR64:$src))))]>, Requires<[HasSSE2]>; +} +defm RELEASE_FADD : RELEASE_FP_BINOP_MI; +// FIXME: Add fsub, fmul, fdiv, ... +} + +multiclass RELEASE_UNOP { + def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst), + "#UNOP "#NAME#"8m PSEUDO!", + [(atomic_store_8 addr:$dst, dag8)]>; + def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst), + "#UNOP "#NAME#"16m PSEUDO!", + [(atomic_store_16 addr:$dst, dag16)]>; + def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst), + "#UNOP "#NAME#"32m PSEUDO!", + [(atomic_store_32 addr:$dst, dag32)]>; + def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst), + "#UNOP "#NAME#"64m PSEUDO!", + [(atomic_store_64 addr:$dst, dag64)]>; +} + +let Defs = [EFLAGS], Predicates = [UseIncDec], SchedRW = [WriteMicrocoded] in { + defm RELEASE_INC : RELEASE_UNOP< + (add (atomic_load_8 addr:$dst), (i8 1)), + (add (atomic_load_16 addr:$dst), (i16 1)), + (add (atomic_load_32 addr:$dst), (i32 1)), + (add (atomic_load_64 addr:$dst), (i64 1))>; + defm RELEASE_DEC : RELEASE_UNOP< + (add (atomic_load_8 addr:$dst), (i8 -1)), + (add (atomic_load_16 addr:$dst), (i16 -1)), + (add (atomic_load_32 addr:$dst), (i32 -1)), + (add (atomic_load_64 addr:$dst), (i64 -1))>; +} +/* +TODO: These don't work because the type inference of TableGen fails. +TODO: find a way to fix it. +let Defs = [EFLAGS] in { + defm RELEASE_NEG : RELEASE_UNOP< + (ineg (atomic_load_8 addr:$dst)), + (ineg (atomic_load_16 addr:$dst)), + (ineg (atomic_load_32 addr:$dst)), + (ineg (atomic_load_64 addr:$dst))>; +} +// NOT doesn't set flags. +defm RELEASE_NOT : RELEASE_UNOP< + (not (atomic_load_8 addr:$dst)), + (not (atomic_load_16 addr:$dst)), + (not (atomic_load_32 addr:$dst)), + (not (atomic_load_64 addr:$dst))>; +*/ + +let SchedRW = [WriteMicrocoded] in { +def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), + "#RELEASE_MOV8mi PSEUDO!", + [(atomic_store_8 addr:$dst, (i8 imm:$src))]>; +def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src), + "#RELEASE_MOV16mi PSEUDO!", + [(atomic_store_16 addr:$dst, (i16 imm:$src))]>; +def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), + "#RELEASE_MOV32mi PSEUDO!", + [(atomic_store_32 addr:$dst, (i32 imm:$src))]>; +def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), + "#RELEASE_MOV64mi32 PSEUDO!", + [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>; + +def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src), + "#RELEASE_MOV8mr PSEUDO!", + [(atomic_store_8 addr:$dst, GR8 :$src)]>; +def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src), + "#RELEASE_MOV16mr PSEUDO!", + [(atomic_store_16 addr:$dst, GR16:$src)]>; +def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), + "#RELEASE_MOV32mr PSEUDO!", + [(atomic_store_32 addr:$dst, GR32:$src)]>; +def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), + "#RELEASE_MOV64mr PSEUDO!", + [(atomic_store_64 addr:$dst, GR64:$src)]>; + +def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src), + "#ACQUIRE_MOV8rm PSEUDO!", + [(set GR8:$dst, (atomic_load_8 addr:$src))]>; +def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src), + "#ACQUIRE_MOV16rm PSEUDO!", + [(set GR16:$dst, (atomic_load_16 addr:$src))]>; +def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src), + "#ACQUIRE_MOV32rm PSEUDO!", + [(set GR32:$dst, (atomic_load_32 addr:$src))]>; +def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src), + "#ACQUIRE_MOV64rm PSEUDO!", + [(set GR64:$dst, (atomic_load_64 addr:$src))]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// DAG Pattern Matching Rules +//===----------------------------------------------------------------------===// + +// Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves +// binary size compared to a regular MOV, but it introduces an unnecessary +// load, so is not suitable for regular or optsize functions. +let Predicates = [OptForMinSize] in { +def : Pat<(store (i16 0), addr:$dst), (AND16mi8 addr:$dst, 0)>; +def : Pat<(store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>; +def : Pat<(store (i64 0), addr:$dst), (AND64mi8 addr:$dst, 0)>; +def : Pat<(store (i16 -1), addr:$dst), (OR16mi8 addr:$dst, -1)>; +def : Pat<(store (i32 -1), addr:$dst), (OR32mi8 addr:$dst, -1)>; +def : Pat<(store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>; +} + +// In kernel code model, we can get the address of a label +// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of +// the MOV64ri32 should accept these. +def : Pat<(i64 (X86Wrapper tconstpool :$dst)), + (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; +def : Pat<(i64 (X86Wrapper tjumptable :$dst)), + (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; +def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), + (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; +def : Pat<(i64 (X86Wrapper texternalsym:$dst)), + (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; +def : Pat<(i64 (X86Wrapper mcsym:$dst)), + (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>; +def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), + (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; + +// If we have small model and -static mode, it is safe to store global addresses +// directly as immediates. FIXME: This is really a hack, the 'imm' predicate +// for MOV64mi32 should handle this sort of thing. +def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), + (MOV64mi32 addr:$dst, tconstpool:$src)>, + Requires<[NearData, IsNotPIC]>; +def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), + (MOV64mi32 addr:$dst, tjumptable:$src)>, + Requires<[NearData, IsNotPIC]>; +def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), + (MOV64mi32 addr:$dst, tglobaladdr:$src)>, + Requires<[NearData, IsNotPIC]>; +def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), + (MOV64mi32 addr:$dst, texternalsym:$src)>, + Requires<[NearData, IsNotPIC]>; +def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst), + (MOV64mi32 addr:$dst, mcsym:$src)>, + Requires<[NearData, IsNotPIC]>; +def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), + (MOV64mi32 addr:$dst, tblockaddress:$src)>, + Requires<[NearData, IsNotPIC]>; + +def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>; +def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>; + +// Calls + +// tls has some funny stuff here... +// This corresponds to movabs $foo@tpoff, %rax +def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), + (MOV64ri32 tglobaltlsaddr :$dst)>; +// This corresponds to add $foo@tpoff, %rax +def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), + (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; + + +// Direct PC relative function call for small code model. 32-bit displacement +// sign extended to 64-bit. +def : Pat<(X86call (i64 tglobaladdr:$dst)), + (CALL64pcrel32 tglobaladdr:$dst)>; +def : Pat<(X86call (i64 texternalsym:$dst)), + (CALL64pcrel32 texternalsym:$dst)>; + +// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they +// can never use callee-saved registers. That is the purpose of the GR64_TC +// register classes. +// +// The only volatile register that is never used by the calling convention is +// %r11. This happens when calling a vararg function with 6 arguments. +// +// Match an X86tcret that uses less than 7 volatile registers. +def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), + (X86tcret node:$ptr, node:$off), [{ + // X86tcret args: (*chain, ptr, imm, regs..., glue) + unsigned NumRegs = 0; + for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) + if (isa(N->getOperand(i)) && ++NumRegs > 6) + return false; + return true; +}]>; + +def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), + (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>, + Requires<[Not64BitMode, NotUseRetpoline]>; + +// FIXME: This is disabled for 32-bit PIC mode because the global base +// register which is part of the address mode may be assigned a +// callee-saved register. +def : Pat<(X86tcret (load addr:$dst), imm:$off), + (TCRETURNmi addr:$dst, imm:$off)>, + Requires<[Not64BitMode, IsNotPIC, NotUseRetpoline]>; + +def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), + (TCRETURNdi tglobaladdr:$dst, imm:$off)>, + Requires<[NotLP64]>; + +def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), + (TCRETURNdi texternalsym:$dst, imm:$off)>, + Requires<[NotLP64]>; + +def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), + (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, + Requires<[In64BitMode, NotUseRetpoline]>; + +// Don't fold loads into X86tcret requiring more than 6 regs. +// There wouldn't be enough scratch registers for base+index. +def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off), + (TCRETURNmi64 addr:$dst, imm:$off)>, + Requires<[In64BitMode, NotUseRetpoline]>; + +def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), + (RETPOLINE_TCRETURN64 ptr_rc_tailcall:$dst, imm:$off)>, + Requires<[In64BitMode, UseRetpoline]>; + +def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), + (RETPOLINE_TCRETURN32 ptr_rc_tailcall:$dst, imm:$off)>, + Requires<[Not64BitMode, UseRetpoline]>; + +def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), + (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, + Requires<[IsLP64]>; + +def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), + (TCRETURNdi64 texternalsym:$dst, imm:$off)>, + Requires<[IsLP64]>; + +// Normal calls, with various flavors of addresses. +def : Pat<(X86call (i32 tglobaladdr:$dst)), + (CALLpcrel32 tglobaladdr:$dst)>; +def : Pat<(X86call (i32 texternalsym:$dst)), + (CALLpcrel32 texternalsym:$dst)>; +def : Pat<(X86call (i32 imm:$dst)), + (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; + +// Comparisons. + +// TEST R,R is smaller than CMP R,0 +def : Pat<(X86cmp GR8:$src1, 0), + (TEST8rr GR8:$src1, GR8:$src1)>; +def : Pat<(X86cmp GR16:$src1, 0), + (TEST16rr GR16:$src1, GR16:$src1)>; +def : Pat<(X86cmp GR32:$src1, 0), + (TEST32rr GR32:$src1, GR32:$src1)>; +def : Pat<(X86cmp GR64:$src1, 0), + (TEST64rr GR64:$src1, GR64:$src1)>; + +// Conditional moves with folded loads with operands swapped and conditions +// inverted. +multiclass CMOVmr { + let Predicates = [HasCMov] in { + def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS), + (Inst16 GR16:$src2, addr:$src1)>; + def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS), + (Inst32 GR32:$src2, addr:$src1)>; + def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS), + (Inst64 GR64:$src2, addr:$src1)>; + } +} + +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; + +// zextload bool -> zextload byte +// i1 stored in one byte in zero-extended form. +// Upper bits cleanup should be executed before Store. +def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; +def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; +def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; +def : Pat<(zextloadi64i1 addr:$src), + (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; + +// extload bool -> extload byte +// When extloading from 16-bit and smaller memory locations into 64-bit +// registers, use zero-extending loads so that the entire 64-bit register is +// defined, avoiding partial-register updates. + +def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; +def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; +def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; +def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; +def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; +def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; + +// For other extloads, use subregs, since the high contents of the register are +// defined after an extload. +def : Pat<(extloadi64i1 addr:$src), + (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; +def : Pat<(extloadi64i8 addr:$src), + (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; +def : Pat<(extloadi64i16 addr:$src), + (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; +def : Pat<(extloadi64i32 addr:$src), + (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; + +// anyext. Define these to do an explicit zero-extend to +// avoid partial-register updates. +def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG + (MOVZX32rr8 GR8 :$src), sub_16bit)>; +def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; + +// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. +def : Pat<(i32 (anyext GR16:$src)), + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; + +def : Pat<(i64 (anyext GR8 :$src)), + (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; +def : Pat<(i64 (anyext GR16:$src)), + (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; +def : Pat<(i64 (anyext GR32:$src)), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>; + + +// Any instruction that defines a 32-bit result leaves the high half of the +// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may +// be copying from a truncate. Any other 32-bit operation will zero-extend +// up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper +// 32 bits, they're probably just qualifying a CopyFromReg. +def def32 : PatLeaf<(i32 GR32:$src), [{ + return N->getOpcode() != ISD::TRUNCATE && + N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && + N->getOpcode() != ISD::CopyFromReg && + N->getOpcode() != ISD::AssertSext && + N->getOpcode() != ISD::AssertZext; +}]>; + +// In the case of a 32-bit def that is known to implicitly zero-extend, +// we can use a SUBREG_TO_REG. +def : Pat<(i64 (zext def32:$src)), + (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; + +//===----------------------------------------------------------------------===// +// Pattern match OR as ADD +//===----------------------------------------------------------------------===// + +// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be +// 3-addressified into an LEA instruction to avoid copies. However, we also +// want to finally emit these instructions as an or at the end of the code +// generator to make the generated code easier to read. To do this, we select +// into "disjoint bits" pseudo ops. + +// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. +def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ + if (ConstantSDNode *CN = dyn_cast(N->getOperand(1))) + return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); + + KnownBits Known0; + CurDAG->computeKnownBits(N->getOperand(0), Known0, 0); + KnownBits Known1; + CurDAG->computeKnownBits(N->getOperand(1), Known1, 0); + return (~Known0.Zero & ~Known1.Zero) == 0; +}]>; + + +// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. +// Try this before the selecting to OR. +let AddedComplexity = 5, SchedRW = [WriteALU] in { + +let isConvertibleToThreeAddress = 1, + Constraints = "$src1 = $dst", Defs = [EFLAGS] in { +let isCommutable = 1 in { +def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "", // orw/addw REG, REG + [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; +def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "", // orl/addl REG, REG + [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; +def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "", // orq/addq REG, REG + [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; +} // isCommutable + +// NOTE: These are order specific, we want the ri8 forms to be listed +// first so that they are slightly preferred to the ri forms. + +def ADD16ri8_DB : I<0, Pseudo, + (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "", // orw/addw REG, imm8 + [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; +def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), + "", // orw/addw REG, imm + [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; + +def ADD32ri8_DB : I<0, Pseudo, + (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "", // orl/addl REG, imm8 + [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; +def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), + "", // orl/addl REG, imm + [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; + + +def ADD64ri8_DB : I<0, Pseudo, + (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "", // orq/addq REG, imm8 + [(set GR64:$dst, (or_is_add GR64:$src1, + i64immSExt8:$src2))]>; +def ADD64ri32_DB : I<0, Pseudo, + (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), + "", // orq/addq REG, imm + [(set GR64:$dst, (or_is_add GR64:$src1, + i64immSExt32:$src2))]>; +} +} // AddedComplexity, SchedRW + +//===----------------------------------------------------------------------===// +// Pattern match SUB as XOR +//===----------------------------------------------------------------------===// + +// An immediate in the LHS of a subtract can't be encoded in the instruction. +// If there is no possibility of a borrow we can use an XOR instead of a SUB +// to enable the immediate to be folded. +// TODO: Move this to a DAG combine? + +def sub_is_xor : PatFrag<(ops node:$lhs, node:$rhs), (sub node:$lhs, node:$rhs),[{ + if (ConstantSDNode *CN = dyn_cast(N->getOperand(0))) { + KnownBits Known; + CurDAG->computeKnownBits(N->getOperand(1), Known); + + // If all possible ones in the RHS are set in the LHS then there can't be + // a borrow and we can use xor. + return (~Known.Zero).isSubsetOf(CN->getAPIntValue()); + } + + return false; +}]>; + +let AddedComplexity = 5 in { +def : Pat<(sub_is_xor imm:$src2, GR8:$src1), + (XOR8ri GR8:$src1, imm:$src2)>; +def : Pat<(sub_is_xor i16immSExt8:$src2, GR16:$src1), + (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(sub_is_xor imm:$src2, GR16:$src1), + (XOR16ri GR16:$src1, imm:$src2)>; +def : Pat<(sub_is_xor i32immSExt8:$src2, GR32:$src1), + (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(sub_is_xor imm:$src2, GR32:$src1), + (XOR32ri GR32:$src1, imm:$src2)>; +def : Pat<(sub_is_xor i64immSExt8:$src2, GR64:$src1), + (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(sub_is_xor i64immSExt32:$src2, GR64:$src1), + (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; +} + +//===----------------------------------------------------------------------===// +// Some peepholes +//===----------------------------------------------------------------------===// + +// Odd encoding trick: -128 fits into an 8-bit immediate field while +// +128 doesn't, so in this special case use a sub instead of an add. +def : Pat<(add GR16:$src1, 128), + (SUB16ri8 GR16:$src1, -128)>; +def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), + (SUB16mi8 addr:$dst, -128)>; + +def : Pat<(add GR32:$src1, 128), + (SUB32ri8 GR32:$src1, -128)>; +def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), + (SUB32mi8 addr:$dst, -128)>; + +def : Pat<(add GR64:$src1, 128), + (SUB64ri8 GR64:$src1, -128)>; +def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), + (SUB64mi8 addr:$dst, -128)>; + +// The same trick applies for 32-bit immediate fields in 64-bit +// instructions. +def : Pat<(add GR64:$src1, 0x0000000080000000), + (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; +def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst), + (SUB64mi32 addr:$dst, 0xffffffff80000000)>; + +// To avoid needing to materialize an immediate in a register, use a 32-bit and +// with implicit zero-extension instead of a 64-bit and if the immediate has at +// least 32 bits of leading zeros. If in addition the last 32 bits can be +// represented with a sign extension of a 8 bit constant, use that. +// This can also reduce instruction size by eliminating the need for the REX +// prefix. + +// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. +let AddedComplexity = 1 in { +def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), + (SUBREG_TO_REG + (i64 0), + (AND32ri8 + (EXTRACT_SUBREG GR64:$src, sub_32bit), + (i32 (GetLo8XForm imm:$imm))), + sub_32bit)>; + +def : Pat<(and GR64:$src, i64immZExt32:$imm), + (SUBREG_TO_REG + (i64 0), + (AND32ri + (EXTRACT_SUBREG GR64:$src, sub_32bit), + (i32 (GetLo32XForm imm:$imm))), + sub_32bit)>; +} // AddedComplexity = 1 + + +// AddedComplexity is needed due to the increased complexity on the +// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all +// the MOVZX patterns keeps thems together in DAGIsel tables. +let AddedComplexity = 1 in { +// r & (2^16-1) ==> movz +def : Pat<(and GR32:$src1, 0xffff), + (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; +// r & (2^8-1) ==> movz +def : Pat<(and GR32:$src1, 0xff), + (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>; +// r & (2^8-1) ==> movz +def : Pat<(and GR16:$src1, 0xff), + (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)), + sub_16bit)>; + +// r & (2^32-1) ==> movz +def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), + (SUBREG_TO_REG (i64 0), + (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), + sub_32bit)>; +// r & (2^16-1) ==> movz +def : Pat<(and GR64:$src, 0xffff), + (SUBREG_TO_REG (i64 0), + (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), + sub_32bit)>; +// r & (2^8-1) ==> movz +def : Pat<(and GR64:$src, 0xff), + (SUBREG_TO_REG (i64 0), + (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), + sub_32bit)>; +} // AddedComplexity = 1 + + +// Try to use BTS/BTR/BTC for single bit operations on the upper 32-bits. + +def BTRXForm : SDNodeXFormgetAPIntValue().countTrailingOnes(), SDLoc(N)); +}]>; + +def BTCBTSXForm : SDNodeXFormgetAPIntValue().countTrailingZeros(), SDLoc(N)); +}]>; + +def BTRMask64 : ImmLeaf(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm); +}]>; + +def BTCBTSMask64 : ImmLeaf(Imm) && isPowerOf2_64(Imm); +}]>; + +// For now only do this for optsize. +let AddedComplexity = 1, Predicates=[OptForSize] in { + def : Pat<(and GR64:$src1, BTRMask64:$mask), + (BTR64ri8 GR64:$src1, (BTRXForm imm:$mask))>; + def : Pat<(or GR64:$src1, BTCBTSMask64:$mask), + (BTS64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; + def : Pat<(xor GR64:$src1, BTCBTSMask64:$mask), + (BTC64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; +} + + +// sext_inreg patterns +def : Pat<(sext_inreg GR32:$src, i16), + (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; +def : Pat<(sext_inreg GR32:$src, i8), + (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>; + +def : Pat<(sext_inreg GR16:$src, i8), + (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)), + sub_16bit)>; + +def : Pat<(sext_inreg GR64:$src, i32), + (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; +def : Pat<(sext_inreg GR64:$src, i16), + (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; +def : Pat<(sext_inreg GR64:$src, i8), + (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; + +// sext, sext_load, zext, zext_load +def: Pat<(i16 (sext GR8:$src)), + (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; +def: Pat<(sextloadi16i8 addr:$src), + (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; +def: Pat<(i16 (zext GR8:$src)), + (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; +def: Pat<(zextloadi16i8 addr:$src), + (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; + +// trunc patterns +def : Pat<(i16 (trunc GR32:$src)), + (EXTRACT_SUBREG GR32:$src, sub_16bit)>; +def : Pat<(i8 (trunc GR32:$src)), + (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), + sub_8bit)>, + Requires<[Not64BitMode]>; +def : Pat<(i8 (trunc GR16:$src)), + (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), + sub_8bit)>, + Requires<[Not64BitMode]>; +def : Pat<(i32 (trunc GR64:$src)), + (EXTRACT_SUBREG GR64:$src, sub_32bit)>; +def : Pat<(i16 (trunc GR64:$src)), + (EXTRACT_SUBREG GR64:$src, sub_16bit)>; +def : Pat<(i8 (trunc GR64:$src)), + (EXTRACT_SUBREG GR64:$src, sub_8bit)>; +def : Pat<(i8 (trunc GR32:$src)), + (EXTRACT_SUBREG GR32:$src, sub_8bit)>, + Requires<[In64BitMode]>; +def : Pat<(i8 (trunc GR16:$src)), + (EXTRACT_SUBREG GR16:$src, sub_8bit)>, + Requires<[In64BitMode]>; + +def immff00_ffff : ImmLeaf= 0xff00 && Imm <= 0xffff; +}]>; + +// h-register tricks +def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), + (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, + Requires<[Not64BitMode]>; +def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))), + (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, + Requires<[Not64BitMode]>; +def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), + (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>, + Requires<[Not64BitMode]>; +def : Pat<(srl GR16:$src, (i8 8)), + (EXTRACT_SUBREG + (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), + sub_16bit)>; +def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), + (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; +def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), + (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; +def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), + (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; +def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)), + (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; + +// h-register tricks. +// For now, be conservative on x86-64 and use an h-register extract only if the +// value is immediately zero-extended or stored, which are somewhat common +// cases. This uses a bunch of code to prevent a register requiring a REX prefix +// from being allocated in the same instruction as the h register, as there's +// currently no way to describe this requirement to the register allocator. + +// h-register extract and zero-extend. +def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), + (SUBREG_TO_REG + (i64 0), + (MOVZX32rr8_NOREX + (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)), + sub_32bit)>; +def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), + (SUBREG_TO_REG + (i64 0), + (MOVZX32rr8_NOREX + (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), + sub_32bit)>; +def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), + (SUBREG_TO_REG + (i64 0), + (MOVZX32rr8_NOREX + (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), + sub_32bit)>; + +// h-register extract and store. +def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), + (MOV8mr_NOREX + addr:$dst, + (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>; +def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), + (MOV8mr_NOREX + addr:$dst, + (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, + Requires<[In64BitMode]>; +def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), + (MOV8mr_NOREX + addr:$dst, + (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, + Requires<[In64BitMode]>; + + +// (shl x, 1) ==> (add x, x) +// Note that if x is undef (immediate or otherwise), we could theoretically +// end up with the two uses of x getting different values, producing a result +// where the least significant bit is not 0. However, the probability of this +// happening is considered low enough that this is officially not a +// "real problem". +def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; +def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; +def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; +def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; + +// Helper imms to check if a mask doesn't change significant shift/rotate bits. +def immShift8 : ImmLeaf(Imm) >= 3; +}]>; +def immShift16 : ImmLeaf(Imm) >= 4; +}]>; +def immShift32 : ImmLeaf(Imm) >= 5; +}]>; +def immShift64 : ImmLeaf(Imm) >= 6; +}]>; + +// Shift amount is implicitly masked. +multiclass MaskedShiftAmountPats { + // (shift x (and y, 31)) ==> (shift x, y) + def : Pat<(frag GR8:$src1, (and CL, immShift32)), + (!cast(name # "8rCL") GR8:$src1)>; + def : Pat<(frag GR16:$src1, (and CL, immShift32)), + (!cast(name # "16rCL") GR16:$src1)>; + def : Pat<(frag GR32:$src1, (and CL, immShift32)), + (!cast(name # "32rCL") GR32:$src1)>; + def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), + (!cast(name # "8mCL") addr:$dst)>; + def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), + (!cast(name # "16mCL") addr:$dst)>; + def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), + (!cast(name # "32mCL") addr:$dst)>; + + // (shift x (and y, 63)) ==> (shift x, y) + def : Pat<(frag GR64:$src1, (and CL, immShift64)), + (!cast(name # "64rCL") GR64:$src1)>; + def : Pat<(store (frag (loadi64 addr:$dst), (and CL, immShift64)), addr:$dst), + (!cast(name # "64mCL") addr:$dst)>; +} + +defm : MaskedShiftAmountPats; +defm : MaskedShiftAmountPats; +defm : MaskedShiftAmountPats; + +// ROL/ROR instructions allow a stronger mask optimization than shift for 8- and +// 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount +// because over-rotating produces the same result. This is noted in the Intel +// docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation +// amount could affect EFLAGS results, but that does not matter because we are +// not tracking flags for these nodes. +multiclass MaskedRotateAmountPats { + // (rot x (and y, BitWidth - 1)) ==> (rot x, y) + def : Pat<(frag GR8:$src1, (and CL, immShift8)), + (!cast(name # "8rCL") GR8:$src1)>; + def : Pat<(frag GR16:$src1, (and CL, immShift16)), + (!cast(name # "16rCL") GR16:$src1)>; + def : Pat<(frag GR32:$src1, (and CL, immShift32)), + (!cast(name # "32rCL") GR32:$src1)>; + def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift8)), addr:$dst), + (!cast(name # "8mCL") addr:$dst)>; + def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift16)), addr:$dst), + (!cast(name # "16mCL") addr:$dst)>; + def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), + (!cast(name # "32mCL") addr:$dst)>; + + // (rot x (and y, 63)) ==> (rot x, y) + def : Pat<(frag GR64:$src1, (and CL, immShift64)), + (!cast(name # "64rCL") GR64:$src1)>; + def : Pat<(store (frag (loadi64 addr:$dst), (and CL, immShift64)), addr:$dst), + (!cast(name # "64mCL") addr:$dst)>; +} + + +defm : MaskedRotateAmountPats; +defm : MaskedRotateAmountPats; + +// Double shift amount is implicitly masked. +multiclass MaskedDoubleShiftAmountPats { + // (shift x (and y, 31)) ==> (shift x, y) + def : Pat<(frag GR16:$src1, GR16:$src2, (and CL, immShift32)), + (!cast(name # "16rrCL") GR16:$src1, GR16:$src2)>; + def : Pat<(frag GR32:$src1, GR32:$src2, (and CL, immShift32)), + (!cast(name # "32rrCL") GR32:$src1, GR32:$src2)>; + + // (shift x (and y, 63)) ==> (shift x, y) + def : Pat<(frag GR64:$src1, GR64:$src2, (and CL, immShift64)), + (!cast(name # "64rrCL") GR64:$src1, GR64:$src2)>; +} + +defm : MaskedDoubleShiftAmountPats; +defm : MaskedDoubleShiftAmountPats; + +let Predicates = [HasBMI2] in { + let AddedComplexity = 1 in { + def : Pat<(sra GR32:$src1, (and GR8:$src2, immShift32)), + (SARX32rr GR32:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(sra GR64:$src1, (and GR8:$src2, immShift64)), + (SARX64rr GR64:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(srl GR32:$src1, (and GR8:$src2, immShift32)), + (SHRX32rr GR32:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(srl GR64:$src1, (and GR8:$src2, immShift64)), + (SHRX64rr GR64:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(shl GR32:$src1, (and GR8:$src2, immShift32)), + (SHLX32rr GR32:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(shl GR64:$src1, (and GR8:$src2, immShift64)), + (SHLX64rr GR64:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + } + + def : Pat<(sra (loadi32 addr:$src1), (and GR8:$src2, immShift32)), + (SARX32rm addr:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(sra (loadi64 addr:$src1), (and GR8:$src2, immShift64)), + (SARX64rm addr:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(srl (loadi32 addr:$src1), (and GR8:$src2, immShift32)), + (SHRX32rm addr:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(srl (loadi64 addr:$src1), (and GR8:$src2, immShift64)), + (SHRX64rm addr:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(shl (loadi32 addr:$src1), (and GR8:$src2, immShift32)), + (SHLX32rm addr:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(shl (loadi64 addr:$src1), (and GR8:$src2, immShift64)), + (SHLX64rm addr:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; +} + +// Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location. +multiclass one_bit_patterns { + def : Pat<(and RC:$src1, (rotl -2, GR8:$src2)), + (BTR RC:$src1, + (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(or RC:$src1, (shl 1, GR8:$src2)), + (BTS RC:$src1, + (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(xor RC:$src1, (shl 1, GR8:$src2)), + (BTC RC:$src1, + (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + // Similar to above, but removing unneeded masking of the shift amount. + def : Pat<(and RC:$src1, (rotl -2, (and GR8:$src2, ImmShift))), + (BTR RC:$src1, + (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(or RC:$src1, (shl 1, (and GR8:$src2, ImmShift))), + (BTS RC:$src1, + (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(xor RC:$src1, (shl 1, (and GR8:$src2, ImmShift))), + (BTC RC:$src1, + (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; +} + +defm : one_bit_patterns; +defm : one_bit_patterns; +defm : one_bit_patterns; + + +// (anyext (setcc_carry)) -> (setcc_carry) +def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C16r)>; +def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C32r)>; +def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C32r)>; + +//===----------------------------------------------------------------------===// +// EFLAGS-defining Patterns +//===----------------------------------------------------------------------===// + +// add reg, reg +def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; +def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; +def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; +def : Pat<(add GR64:$src1, GR64:$src2), (ADD64rr GR64:$src1, GR64:$src2)>; + +// add reg, mem +def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), + (ADD8rm GR8:$src1, addr:$src2)>; +def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), + (ADD16rm GR16:$src1, addr:$src2)>; +def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), + (ADD32rm GR32:$src1, addr:$src2)>; +def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), + (ADD64rm GR64:$src1, addr:$src2)>; + +// add reg, imm +def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; +def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; +def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; +def : Pat<(add GR16:$src1, i16immSExt8:$src2), + (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(add GR32:$src1, i32immSExt8:$src2), + (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(add GR64:$src1, i64immSExt8:$src2), + (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(add GR64:$src1, i64immSExt32:$src2), + (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; + +// sub reg, reg +def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; +def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; +def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; +def : Pat<(sub GR64:$src1, GR64:$src2), (SUB64rr GR64:$src1, GR64:$src2)>; + +// sub reg, mem +def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), + (SUB8rm GR8:$src1, addr:$src2)>; +def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), + (SUB16rm GR16:$src1, addr:$src2)>; +def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), + (SUB32rm GR32:$src1, addr:$src2)>; +def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), + (SUB64rm GR64:$src1, addr:$src2)>; + +// sub reg, imm +def : Pat<(sub GR8:$src1, imm:$src2), + (SUB8ri GR8:$src1, imm:$src2)>; +def : Pat<(sub GR16:$src1, imm:$src2), + (SUB16ri GR16:$src1, imm:$src2)>; +def : Pat<(sub GR32:$src1, imm:$src2), + (SUB32ri GR32:$src1, imm:$src2)>; +def : Pat<(sub GR16:$src1, i16immSExt8:$src2), + (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(sub GR32:$src1, i32immSExt8:$src2), + (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(sub GR64:$src1, i64immSExt8:$src2), + (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(sub GR64:$src1, i64immSExt32:$src2), + (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; + +// sub 0, reg +def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; +def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; +def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; +def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; + +// sub reg, relocImm +def : Pat<(X86sub_flag GR64:$src1, i64relocImmSExt8_su:$src2), + (SUB64ri8 GR64:$src1, i64relocImmSExt8_su:$src2)>; +def : Pat<(X86sub_flag GR64:$src1, i64relocImmSExt32_su:$src2), + (SUB64ri32 GR64:$src1, i64relocImmSExt32_su:$src2)>; + +// mul reg, reg +def : Pat<(mul GR16:$src1, GR16:$src2), + (IMUL16rr GR16:$src1, GR16:$src2)>; +def : Pat<(mul GR32:$src1, GR32:$src2), + (IMUL32rr GR32:$src1, GR32:$src2)>; +def : Pat<(mul GR64:$src1, GR64:$src2), + (IMUL64rr GR64:$src1, GR64:$src2)>; + +// mul reg, mem +def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), + (IMUL16rm GR16:$src1, addr:$src2)>; +def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), + (IMUL32rm GR32:$src1, addr:$src2)>; +def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), + (IMUL64rm GR64:$src1, addr:$src2)>; + +// mul reg, imm +def : Pat<(mul GR16:$src1, imm:$src2), + (IMUL16rri GR16:$src1, imm:$src2)>; +def : Pat<(mul GR32:$src1, imm:$src2), + (IMUL32rri GR32:$src1, imm:$src2)>; +def : Pat<(mul GR16:$src1, i16immSExt8:$src2), + (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(mul GR32:$src1, i32immSExt8:$src2), + (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(mul GR64:$src1, i64immSExt8:$src2), + (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(mul GR64:$src1, i64immSExt32:$src2), + (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; + +// reg = mul mem, imm +def : Pat<(mul (loadi16 addr:$src1), imm:$src2), + (IMUL16rmi addr:$src1, imm:$src2)>; +def : Pat<(mul (loadi32 addr:$src1), imm:$src2), + (IMUL32rmi addr:$src1, imm:$src2)>; +def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), + (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; +def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), + (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; +def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), + (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; +def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), + (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; + +// Increment/Decrement reg. +// Do not make INC/DEC if it is slow +let Predicates = [UseIncDec] in { + def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>; + def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>; + def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>; + def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; + def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>; + def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>; + def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>; + def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; +} + +// or reg/reg. +def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; +def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; +def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; +def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; + +// or reg/mem +def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), + (OR8rm GR8:$src1, addr:$src2)>; +def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), + (OR16rm GR16:$src1, addr:$src2)>; +def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), + (OR32rm GR32:$src1, addr:$src2)>; +def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), + (OR64rm GR64:$src1, addr:$src2)>; + +// or reg/imm +def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; +def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; +def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; +def : Pat<(or GR16:$src1, i16immSExt8:$src2), + (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(or GR32:$src1, i32immSExt8:$src2), + (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(or GR64:$src1, i64immSExt8:$src2), + (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(or GR64:$src1, i64immSExt32:$src2), + (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; + +// xor reg/reg +def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; +def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; +def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; +def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; + +// xor reg/mem +def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), + (XOR8rm GR8:$src1, addr:$src2)>; +def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), + (XOR16rm GR16:$src1, addr:$src2)>; +def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), + (XOR32rm GR32:$src1, addr:$src2)>; +def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), + (XOR64rm GR64:$src1, addr:$src2)>; + +// xor reg/imm +def : Pat<(xor GR8:$src1, imm:$src2), + (XOR8ri GR8:$src1, imm:$src2)>; +def : Pat<(xor GR16:$src1, imm:$src2), + (XOR16ri GR16:$src1, imm:$src2)>; +def : Pat<(xor GR32:$src1, imm:$src2), + (XOR32ri GR32:$src1, imm:$src2)>; +def : Pat<(xor GR16:$src1, i16immSExt8:$src2), + (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(xor GR32:$src1, i32immSExt8:$src2), + (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(xor GR64:$src1, i64immSExt8:$src2), + (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(xor GR64:$src1, i64immSExt32:$src2), + (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; + +// and reg/reg +def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; +def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; +def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; +def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; + +// and reg/mem +def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), + (AND8rm GR8:$src1, addr:$src2)>; +def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), + (AND16rm GR16:$src1, addr:$src2)>; +def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), + (AND32rm GR32:$src1, addr:$src2)>; +def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), + (AND64rm GR64:$src1, addr:$src2)>; + +// and reg/imm +def : Pat<(and GR8:$src1, imm:$src2), + (AND8ri GR8:$src1, imm:$src2)>; +def : Pat<(and GR16:$src1, imm:$src2), + (AND16ri GR16:$src1, imm:$src2)>; +def : Pat<(and GR32:$src1, imm:$src2), + (AND32ri GR32:$src1, imm:$src2)>; +def : Pat<(and GR16:$src1, i16immSExt8:$src2), + (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(and GR32:$src1, i32immSExt8:$src2), + (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(and GR64:$src1, i64immSExt8:$src2), + (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(and GR64:$src1, i64immSExt32:$src2), + (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; + +// Bit scan instruction patterns to match explicit zero-undef behavior. +def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; +def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; +def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; +def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; +def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; +def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; + +// When HasMOVBE is enabled it is possible to get a non-legalized +// register-register 16 bit bswap. This maps it to a ROL instruction. +let Predicates = [HasMOVBE] in { + def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; +} + +// These patterns are selected by some custom code in X86ISelDAGToDAG.cpp that +// custom combines and+srl into BEXTR. We use these patterns to avoid a bunch +// of manual code for folding loads. +let Predicates = [HasBMI, NoTBM] in { + def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)), + (BEXTR32rr GR32:$src1, (MOV32ri imm:$src2))>; + def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)), + (BEXTR32rm addr:$src1, (MOV32ri imm:$src2))>; + def : Pat<(X86bextr GR64:$src1, mov64imm32:$src2), + (BEXTR64rr GR64:$src1, + (SUBREG_TO_REG (i64 0), + (MOV32ri64 mov64imm32:$src2), + sub_32bit))>; + def : Pat<(X86bextr (loadi64 addr:$src1), mov64imm32:$src2), + (BEXTR64rm addr:$src1, + (SUBREG_TO_REG (i64 0), + (MOV32ri64 mov64imm32:$src2), + sub_32bit))>; +} // HasBMI, NoTBM diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrControl.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrControl.td new file mode 100644 index 0000000..3271b43 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrControl.td @@ -0,0 +1,413 @@ +//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 jump, return, call, and related instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Control Flow Instructions. +// + +// Return instructions. +// +// The X86retflag return instructions are variadic because we may add ST0 and +// ST1 arguments when returning values on the x87 stack. +let isTerminator = 1, isReturn = 1, isBarrier = 1, + hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in { + def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops), + "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>; + def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops), + "ret{q}", []>, OpSize32, Requires<[In64BitMode]>; + def RETW : I <0xC3, RawFrm, (outs), (ins), + "ret{w}", []>, OpSize16; + def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), + "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>; + def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), + "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>; + def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), + "ret{w}\t$amt", []>, OpSize16; + def LRETL : I <0xCB, RawFrm, (outs), (ins), + "{l}ret{l|f}", []>, OpSize32; + def LRETQ : RI <0xCB, RawFrm, (outs), (ins), + "{l}ret{|f}q", []>, Requires<[In64BitMode]>; + def LRETW : I <0xCB, RawFrm, (outs), (ins), + "{l}ret{w|f}", []>, OpSize16; + def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), + "{l}ret{l|f}\t$amt", []>, OpSize32; + def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt), + "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>; + def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), + "{l}ret{w|f}\t$amt", []>, OpSize16; + + // The machine return from interrupt instruction, but sometimes we need to + // perform a post-epilogue stack adjustment. Codegen emits the pseudo form + // which expands to include an SP adjustment if necessary. + def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", []>, + OpSize16; + def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32; + def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>; + // let isCodeGenOnly = 1 in + // def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>; + // def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>; +} + +// Unconditional branches. +let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { + def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), + "jmp\t$dst", [(br bb:$dst)]>; + let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { + def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst), + "jmp\t$dst", []>, OpSize16; + def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst), + "jmp\t$dst", []>, OpSize32; + } +} + +// Conditional Branches. +let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in { + multiclass ICBr opc1, bits<8> opc4, string asm, PatFrag Cond> { + def _1 : Ii8PCRel ; + let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { + def _2 : Ii16PCRel, OpSize16, TB; + def _4 : Ii32PCRel, TB, OpSize32; + } + } +} + +defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>; +defm JNO : ICBr<0x71, 0x81, "jno\t$dst", X86_COND_NO>; +defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>; +defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>; +defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>; +defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>; +defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>; +defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>; +defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>; +defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>; +defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>; +defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>; +defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>; +defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>; +defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>; +defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>; + +// jcx/jecx/jrcx instructions. +let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in { + // These are the 32-bit versions of this instruction for the asmparser. In + // 32-bit mode, the address size prefix is jcxz and the unprefixed version is + // jecxz. + let Uses = [CX] in + def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), + "jcxz\t$dst", []>, AdSize16, Requires<[Not64BitMode]>; + let Uses = [ECX] in + def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), + "jecxz\t$dst", []>, AdSize32; + + let Uses = [RCX] in + def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), + "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>; +} + +// Indirect branches +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { + def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst", + [(brind GR16:$dst)]>, Requires<[Not64BitMode]>, + OpSize16, Sched<[WriteJump]>; + def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst", + [(brind (loadi16 addr:$dst))]>, Requires<[Not64BitMode]>, + OpSize16, Sched<[WriteJumpLd]>; + + def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", + [(brind GR32:$dst)]>, Requires<[Not64BitMode]>, + OpSize32, Sched<[WriteJump]>; + def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", + [(brind (loadi32 addr:$dst))]>, Requires<[Not64BitMode]>, + OpSize32, Sched<[WriteJumpLd]>; + + def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", + [(brind GR64:$dst)]>, Requires<[In64BitMode]>, + Sched<[WriteJump]>; + def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", + [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>, + Sched<[WriteJumpLd]>; + + // Non-tracking jumps for IBT, use with caution. + let isCodeGenOnly = 1 in { + def JMP16r_NT : I<0xFF, MRM4r, (outs), (ins GR16 : $dst), "jmp{w}\t{*}$dst", + [(X86NoTrackBrind GR16 : $dst)]>, Requires<[Not64BitMode]>, + OpSize16, Sched<[WriteJump]>, NOTRACK; + + def JMP16m_NT : I<0xFF, MRM4m, (outs), (ins i16mem : $dst), "jmp{w}\t{*}$dst", + [(X86NoTrackBrind (loadi16 addr : $dst))]>, + Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>, + NOTRACK; + + def JMP32r_NT : I<0xFF, MRM4r, (outs), (ins GR32 : $dst), "jmp{l}\t{*}$dst", + [(X86NoTrackBrind GR32 : $dst)]>, Requires<[Not64BitMode]>, + OpSize32, Sched<[WriteJump]>, NOTRACK; + def JMP32m_NT : I<0xFF, MRM4m, (outs), (ins i32mem : $dst), "jmp{l}\t{*}$dst", + [(X86NoTrackBrind (loadi32 addr : $dst))]>, + Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>, + NOTRACK; + + def JMP64r_NT : I<0xFF, MRM4r, (outs), (ins GR64 : $dst), "jmp{q}\t{*}$dst", + [(X86NoTrackBrind GR64 : $dst)]>, Requires<[In64BitMode]>, + Sched<[WriteJump]>, NOTRACK; + def JMP64m_NT : I<0xFF, MRM4m, (outs), (ins i64mem : $dst), "jmp{q}\t{*}$dst", + [(X86NoTrackBrind(loadi64 addr : $dst))]>, + Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK; + } + + let Predicates = [Not64BitMode], AsmVariantName = "att" in { + def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), + (ins i16imm:$off, i16imm:$seg), + "ljmp{w}\t$seg : $off", []>, + OpSize16, Sched<[WriteJump]>; + def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), + (ins i32imm:$off, i16imm:$seg), + "ljmp{l}\t$seg : $off", []>, + OpSize32, Sched<[WriteJump]>; + } + def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaquemem:$dst), + "ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>; + + let AsmVariantName = "att" in + def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), + "ljmp{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; + def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), + "{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; +} + +// Loop instructions +let SchedRW = [WriteJump] in { +def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>; +def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>; +def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>; +} + +//===----------------------------------------------------------------------===// +// Call Instructions... +// +let isCall = 1 in + // All calls clobber the non-callee saved registers. ESP is marked as + // a use to prevent stack-pointer assignments that appear immediately + // before calls from potentially appearing dead. Uses for argument + // registers are added manually. + let Uses = [ESP, SSP] in { + def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm, + (outs), (ins i32imm_pcrel:$dst), + "call{l}\t$dst", []>, OpSize32, + Requires<[Not64BitMode]>, Sched<[WriteJump]>; + let hasSideEffects = 0 in + def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm, + (outs), (ins i16imm_pcrel:$dst), + "call{w}\t$dst", []>, OpSize16, + Sched<[WriteJump]>; + def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst), + "call{w}\t{*}$dst", [(X86call GR16:$dst)]>, + OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>; + def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst), + "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))]>, + OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, + Sched<[WriteJumpLd]>; + def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst), + "call{l}\t{*}$dst", [(X86call GR32:$dst)]>, OpSize32, + Requires<[Not64BitMode,NotUseRetpoline]>, Sched<[WriteJump]>; + def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst), + "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>, + OpSize32, + Requires<[Not64BitMode,FavorMemIndirectCall,NotUseRetpoline]>, + Sched<[WriteJumpLd]>; + + // Non-tracking calls for IBT, use with caution. + let isCodeGenOnly = 1 in { + def CALL16r_NT : I<0xFF, MRM2r, (outs), (ins GR16 : $dst), + "call{w}\t{*}$dst",[(X86NoTrackCall GR16 : $dst)]>, + OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK; + def CALL16m_NT : I<0xFF, MRM2m, (outs), (ins i16mem : $dst), + "call{w}\t{*}$dst",[(X86NoTrackCall(loadi16 addr : $dst))]>, + OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, + Sched<[WriteJumpLd]>, NOTRACK; + def CALL32r_NT : I<0xFF, MRM2r, (outs), (ins GR32 : $dst), + "call{l}\t{*}$dst",[(X86NoTrackCall GR32 : $dst)]>, + OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK; + def CALL32m_NT : I<0xFF, MRM2m, (outs), (ins i32mem : $dst), + "call{l}\t{*}$dst",[(X86NoTrackCall(loadi32 addr : $dst))]>, + OpSize32, Requires<[Not64BitMode,FavorMemIndirectCall]>, + Sched<[WriteJumpLd]>, NOTRACK; + } + + let Predicates = [Not64BitMode], AsmVariantName = "att" in { + def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), + (ins i16imm:$off, i16imm:$seg), + "lcall{w}\t$seg : $off", []>, + OpSize16, Sched<[WriteJump]>; + def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), + (ins i32imm:$off, i16imm:$seg), + "lcall{l}\t$seg : $off", []>, + OpSize32, Sched<[WriteJump]>; + } + + def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), + "lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; + def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), + "{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; + } + + +/* +// Tail call stuff. +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, + isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in + let Uses = [ESP, SSP] in { + def TCRETURNdi : PseudoI<(outs), + (ins i32imm_pcrel:$dst, i32imm:$offset), []>, NotMemoryFoldable; + def TCRETURNri : PseudoI<(outs), + (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>, NotMemoryFoldable; + let mayLoad = 1 in + def TCRETURNmi : PseudoI<(outs), + (ins i32mem_TC:$dst, i32imm:$offset), []>; + + // FIXME: The should be pseudo instructions that are lowered when going to + // mcinst. + def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs), + (ins i32imm_pcrel:$dst), "jmp\t$dst", []>; + + def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), + "", []>; // FIXME: Remove encoding when JIT is dead. + let mayLoad = 1 in + def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst), + "jmp{l}\t{*}$dst", []>; +} + +// Conditional tail calls are similar to the above, but they are branches +// rather than barriers, and they use EFLAGS. +let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, + isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in + let Uses = [ESP, EFLAGS, SSP] in { + def TCRETURNdicc : PseudoI<(outs), + (ins i32imm_pcrel:$dst, i32imm:$offset, i32imm:$cond), []>; + + // This gets substituted to a conditional jump instruction in MC lowering. + def TAILJMPd_CC : Ii32PCRel<0x80, RawFrm, (outs), + (ins i32imm_pcrel:$dst, i32imm:$cond), "", []>; +} +*/ + + +//===----------------------------------------------------------------------===// +// Call Instructions... +// + +// RSP is marked as a use to prevent stack-pointer assignments that appear +// immediately before calls from potentially appearing dead. Uses for argument +// registers are added manually. +let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in { + // NOTE: this pattern doesn't match "X86call imm", because we do not know + // that the offset between an arbitrary immediate and the call will fit in + // the 32-bit pcrel field that we have. + def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm, + (outs), (ins i64i32imm_pcrel:$dst), + "call{q}\t$dst", []>, OpSize32, + Requires<[In64BitMode]>; + def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst), + "call{q}\t{*}$dst", [(X86call GR64:$dst)]>, + Requires<[In64BitMode,NotUseRetpoline]>; + def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst), + "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>, + Requires<[In64BitMode,FavorMemIndirectCall, + NotUseRetpoline]>; + + // Non-tracking calls for IBT, use with caution. + let isCodeGenOnly = 1 in { + def CALL64r_NT : I<0xFF, MRM2r, (outs), (ins GR64 : $dst), + "call{q}\t{*}$dst",[(X86NoTrackCall GR64 : $dst)]>, + Requires<[In64BitMode]>, NOTRACK; + def CALL64m_NT : I<0xFF, MRM2m, (outs), (ins i64mem : $dst), + "call{q}\t{*}$dst", + [(X86NoTrackCall(loadi64 addr : $dst))]>, + Requires<[In64BitMode,FavorMemIndirectCall]>, NOTRACK; + } + + def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst), + "lcall{q}\t{*}$dst", []>; +} + +/* +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, + isCodeGenOnly = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in { + def TCRETURNdi64 : PseudoI<(outs), + (ins i64i32imm_pcrel:$dst, i32imm:$offset), + []>; + def TCRETURNri64 : PseudoI<(outs), + (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>, NotMemoryFoldable; + let mayLoad = 1 in + def TCRETURNmi64 : PseudoI<(outs), + (ins i64mem_TC:$dst, i32imm:$offset), []>, NotMemoryFoldable; + + def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), (ins i64i32imm_pcrel:$dst), + "jmp\t$dst", []>; + + def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), + "jmp{q}\t{*}$dst", []>; + + let mayLoad = 1 in + def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), + "jmp{q}\t{*}$dst", []>; + + // Win64 wants indirect jumps leaving the function to have a REX_W prefix. + let hasREX_WPrefix = 1 in { + def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), + "rex64 jmp{q}\t{*}$dst", []>; + + let mayLoad = 1 in + def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), + "rex64 jmp{q}\t{*}$dst", []>; + } +} + +let isPseudo = 1, isCall = 1, isCodeGenOnly = 1, + Uses = [RSP, SSP], + usesCustomInserter = 1, + SchedRW = [WriteJump] in { + def RETPOLINE_CALL32 : + PseudoI<(outs), (ins GR32:$dst), [(X86call GR32:$dst)]>, + Requires<[Not64BitMode,UseRetpoline]>; + + def RETPOLINE_CALL64 : + PseudoI<(outs), (ins GR64:$dst), [(X86call GR64:$dst)]>, + Requires<[In64BitMode,UseRetpoline]>; + + // Retpoline variant of indirect tail calls. + let isTerminator = 1, isReturn = 1, isBarrier = 1 in { + def RETPOLINE_TCRETURN64 : + PseudoI<(outs), (ins GR64:$dst, i32imm:$offset), []>; + def RETPOLINE_TCRETURN32 : + PseudoI<(outs), (ins GR32:$dst, i32imm:$offset), []>; + } +} + +// Conditional tail calls are similar to the above, but they are branches +// rather than barriers, and they use EFLAGS. +let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, + isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in + let Uses = [RSP, EFLAGS, SSP] in { + def TCRETURNdi64cc : PseudoI<(outs), + (ins i64i32imm_pcrel:$dst, i32imm:$offset, + i32imm:$cond), []>; + + // This gets substituted to a conditional jump instruction in MC lowering. + def TAILJMPd64_CC : Ii32PCRel<0x80, RawFrm, (outs), + (ins i64i32imm_pcrel:$dst, i32imm:$cond), "", []>; +} +*/ diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrExtension.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrExtension.td new file mode 100644 index 0000000..421792c --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrExtension.td @@ -0,0 +1,204 @@ +//===-- X86InstrExtension.td - Sign and Zero Extensions ----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the sign and zero extension operations. +// +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0 in { + let Defs = [AX], Uses = [AL] in // AX = signext(AL) + def CBW : I<0x98, RawFrm, (outs), (ins), + "{cbtw|cbw}", []>, OpSize16, Sched<[WriteALU]>; + let Defs = [EAX], Uses = [AX] in // EAX = signext(AX) + def CWDE : I<0x98, RawFrm, (outs), (ins), + "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>; + + let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX) + def CWD : I<0x99, RawFrm, (outs), (ins), + "{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>; + let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX) + def CDQ : I<0x99, RawFrm, (outs), (ins), + "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>; + + + let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX) + def CDQE : RI<0x98, RawFrm, (outs), (ins), + "{cltq|cdqe}", []>, Sched<[WriteALU]>; + + let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX) + def CQO : RI<0x99, RawFrm, (outs), (ins), + "{cqto|cqo}", []>, Sched<[WriteALU]>; +} + +// Sign/Zero extenders +let hasSideEffects = 0 in { +def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), + "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, + TB, OpSize16, Sched<[WriteALU]>; +let mayLoad = 1 in +def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), + "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, + TB, OpSize16, Sched<[WriteALULd]>; +} // hasSideEffects = 0 +def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src), + "movs{bl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (sext GR8:$src))]>, TB, + OpSize32, Sched<[WriteALU]>; +def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), + "movs{bl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB, + OpSize32, Sched<[WriteALULd]>; +def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), + "movs{wl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (sext GR16:$src))]>, TB, + OpSize32, Sched<[WriteALU]>; +def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), + "movs{wl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, + OpSize32, TB, Sched<[WriteALULd]>; + +let hasSideEffects = 0 in { +def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), + "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, + TB, OpSize16, Sched<[WriteALU]>; +let mayLoad = 1 in +def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), + "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, + TB, OpSize16, Sched<[WriteALULd]>; +} // hasSideEffects = 0 +def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), + "movz{bl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (zext GR8:$src))]>, TB, + OpSize32, Sched<[WriteALU]>; +def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), + "movz{bl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB, + OpSize32, Sched<[WriteALULd]>; +def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), + "movz{wl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (zext GR16:$src))]>, TB, + OpSize32, Sched<[WriteALU]>; +def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), + "movz{wl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, + TB, OpSize32, Sched<[WriteALULd]>; + +// These instructions exist as a consequence of operand size prefix having +// control of the destination size, but not the input size. Only support them +// for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { +def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "movs{ww|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable; +def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "movz{ww|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable; +let mayLoad = 1 in { +def MOVSX16rm16: I<0xBF, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "movs{ww|x}\t{$src, $dst|$dst, $src}", + []>, OpSize16, TB, Sched<[WriteALULd]>, NotMemoryFoldable; +def MOVZX16rm16: I<0xB7, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "movz{ww|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize16, Sched<[WriteALULd]>, NotMemoryFoldable; +} // mayLoad = 1 +} // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 + +// These are the same as the regular MOVZX32rr8 and MOVZX32rm8 +// except that they use GR32_NOREX for the output operand register class +// instead of GR32. This allows them to operate on h registers on x86-64. +let hasSideEffects = 0, isCodeGenOnly = 1 in { +def MOVZX32rr8_NOREX : I<0xB6, MRMSrcReg, + (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src), + "movz{bl|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize32, Sched<[WriteALU]>; +let mayLoad = 1 in +def MOVZX32rm8_NOREX : I<0xB6, MRMSrcMem, + (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src), + "movz{bl|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize32, Sched<[WriteALULd]>; + +def MOVSX32rr8_NOREX : I<0xBE, MRMSrcReg, + (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src), + "movs{bl|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize32, Sched<[WriteALU]>; +let mayLoad = 1 in +def MOVSX32rm8_NOREX : I<0xBE, MRMSrcMem, + (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src), + "movs{bl|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize32, Sched<[WriteALULd]>; +} + +// MOVSX64rr8 always has a REX prefix and it has an 8-bit register +// operand, which makes it a rare instruction with an 8-bit register +// operand that can never access an h register. If support for h registers +// were generalized, this would require a special register class. +def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src), + "movs{bq|x}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (sext GR8:$src))]>, TB, + Sched<[WriteALU]>; +def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src), + "movs{bq|x}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, + TB, Sched<[WriteALULd]>; +def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), + "movs{wq|x}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (sext GR16:$src))]>, TB, + Sched<[WriteALU]>; +def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), + "movs{wq|x}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, + TB, Sched<[WriteALULd]>; +def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), + "movs{lq|xd}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (sext GR32:$src))]>, + Sched<[WriteALU]>, Requires<[In64BitMode]>; +def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), + "movs{lq|xd}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (sextloadi64i32 addr:$src))]>, + Sched<[WriteALULd]>, Requires<[In64BitMode]>; + +// movzbq and movzwq encodings for the disassembler +let hasSideEffects = 0 in { +def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src), + "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, + TB, Sched<[WriteALU]>; +let mayLoad = 1 in +def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src), + "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, + TB, Sched<[WriteALULd]>; +def MOVZX64rr16 : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), + "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, + TB, Sched<[WriteALU]>; +let mayLoad = 1 in +def MOVZX64rm16 : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), + "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, + TB, Sched<[WriteALULd]>; +} + +// 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a +// 32-bit register. +def : Pat<(i64 (zext GR8:$src)), + (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>; +def : Pat<(zextloadi64i8 addr:$src), + (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; + +def : Pat<(i64 (zext GR16:$src)), + (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>; +def : Pat<(zextloadi64i16 addr:$src), + (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; + +// The preferred way to do 32-bit-to-64-bit zero extension on x86-64 is to use a +// SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible +// when the 32-bit value is defined by a truncate or is copied from something +// where the high bits aren't necessarily all zero. In such cases, we fall back +// to these explicit zext instructions. +def : Pat<(i64 (zext GR32:$src)), + (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>; +def : Pat<(i64 (zextloadi64i32 addr:$src)), + (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrFMA.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrFMA.td new file mode 100644 index 0000000..1827741 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrFMA.td @@ -0,0 +1,636 @@ +//===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes FMA (Fused Multiply-Add) instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// FMA3 - Intel 3 operand Fused Multiply-Add instructions +//===----------------------------------------------------------------------===// + +// For all FMA opcodes declared in fma3p_rm_* and fma3s_rm_* multiclasses +// defined below, both the register and memory variants are commutable. +// For the register form the commutable operands are 1, 2 and 3. +// For the memory variant the folded operand must be in 3. Thus, +// in that case, only the operands 1 and 2 can be swapped. +// Commuting some of operands may require the opcode change. +// FMA*213*: +// operands 1 and 2 (memory & register forms): *213* --> *213*(no changes); +// operands 1 and 3 (register forms only): *213* --> *231*; +// operands 2 and 3 (register forms only): *213* --> *132*. +// FMA*132*: +// operands 1 and 2 (memory & register forms): *132* --> *231*; +// operands 1 and 3 (register forms only): *132* --> *132*(no changes); +// operands 2 and 3 (register forms only): *132* --> *213*. +// FMA*231*: +// operands 1 and 2 (memory & register forms): *231* --> *132*; +// operands 1 and 3 (register forms only): *231* --> *213*; +// operands 2 and 3 (register forms only): *231* --> *231*(no changes). + +multiclass fma3p_rm_213 opc, string OpcodeStr, RegisterClass RC, + ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, + SDNode Op, X86FoldableSchedWrite sched> { + def r : FMA3, + Sched<[sched]>; + + let mayLoad = 1 in + def m : FMA3, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +multiclass fma3p_rm_231 opc, string OpcodeStr, RegisterClass RC, + ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, + SDNode Op, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def r : FMA3, Sched<[sched]>; + + let mayLoad = 1 in + def m : FMA3, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +multiclass fma3p_rm_132 opc, string OpcodeStr, RegisterClass RC, + ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, + SDNode Op, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def r : FMA3, Sched<[sched]>; + + // Pattern is 312 order so that the load is in a different place from the + // 213 and 231 patterns this helps tablegen's duplicate pattern detection. + let mayLoad = 1 in + def m : FMA3, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +let Constraints = "$src1 = $dst", hasSideEffects = 0, isCommutable = 1 in +multiclass fma3p_forms opc132, bits<8> opc213, bits<8> opc231, + string OpcodeStr, string PackTy, string Suff, + PatFrag MemFrag128, PatFrag MemFrag256, + SDNode Op, ValueType OpTy128, ValueType OpTy256, + X86SchedWriteWidths sched> { + defm NAME#213#Suff : fma3p_rm_213; + defm NAME#231#Suff : fma3p_rm_231; + defm NAME#132#Suff : fma3p_rm_132; + + defm NAME#213#Suff#Y : fma3p_rm_213, + VEX_L; + defm NAME#231#Suff#Y : fma3p_rm_231, + VEX_L; + defm NAME#132#Suff#Y : fma3p_rm_132, + VEX_L; +} + +// Fused Multiply-Add +let ExeDomain = SSEPackedSingle in { + defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", "PS", + loadv4f32, loadv8f32, X86Fmadd, v4f32, v8f32, + SchedWriteFMA>; + defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", "PS", + loadv4f32, loadv8f32, X86Fmsub, v4f32, v8f32, + SchedWriteFMA>; + defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps", "PS", + loadv4f32, loadv8f32, X86Fmaddsub, v4f32, v8f32, + SchedWriteFMA>; + defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps", "PS", + loadv4f32, loadv8f32, X86Fmsubadd, v4f32, v8f32, + SchedWriteFMA>; +} + +let ExeDomain = SSEPackedDouble in { + defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", "PD", + loadv2f64, loadv4f64, X86Fmadd, v2f64, + v4f64, SchedWriteFMA>, VEX_W; + defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", "PD", + loadv2f64, loadv4f64, X86Fmsub, v2f64, + v4f64, SchedWriteFMA>, VEX_W; + defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", "PD", + loadv2f64, loadv4f64, X86Fmaddsub, + v2f64, v4f64, SchedWriteFMA>, VEX_W; + defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", "PD", + loadv2f64, loadv4f64, X86Fmsubadd, + v2f64, v4f64, SchedWriteFMA>, VEX_W; +} + +// Fused Negative Multiply-Add +let ExeDomain = SSEPackedSingle in { + defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", "PS", loadv4f32, + loadv8f32, X86Fnmadd, v4f32, v8f32, SchedWriteFMA>; + defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", "PS", loadv4f32, + loadv8f32, X86Fnmsub, v4f32, v8f32, SchedWriteFMA>; +} +let ExeDomain = SSEPackedDouble in { + defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", "PD", loadv2f64, + loadv4f64, X86Fnmadd, v2f64, v4f64, SchedWriteFMA>, VEX_W; + defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd", "PD", loadv2f64, + loadv4f64, X86Fnmsub, v2f64, v4f64, SchedWriteFMA>, VEX_W; +} + +// All source register operands of FMA opcodes defined in fma3s_rm multiclass +// can be commuted. In many cases such commute transformation requires an opcode +// adjustment, for example, commuting the operands 1 and 2 in FMA*132 form +// would require an opcode change to FMA*231: +// FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2; +// --> +// FMA*231* reg2, reg1, reg3; // reg1 * reg3 + reg2; +// Please see more detailed comment at the very beginning of the section +// defining FMA3 opcodes above. +multiclass fma3s_rm_213 opc, string OpcodeStr, + X86MemOperand x86memop, RegisterClass RC, + SDPatternOperator OpNode, + X86FoldableSchedWrite sched> { + def r : FMA3S, + Sched<[sched]>; + + let mayLoad = 1 in + def m : FMA3S, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +multiclass fma3s_rm_231 opc, string OpcodeStr, + X86MemOperand x86memop, RegisterClass RC, + SDPatternOperator OpNode, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def r : FMA3S, Sched<[sched]>; + + let mayLoad = 1 in + def m : FMA3S, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +multiclass fma3s_rm_132 opc, string OpcodeStr, + X86MemOperand x86memop, RegisterClass RC, + SDPatternOperator OpNode, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def r : FMA3S, Sched<[sched]>; + + // Pattern is 312 order so that the load is in a different place from the + // 213 and 231 patterns this helps tablegen's duplicate pattern detection. + let mayLoad = 1 in + def m : FMA3S, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +let Constraints = "$src1 = $dst", isCommutable = 1, hasSideEffects = 0 in +multiclass fma3s_forms opc132, bits<8> opc213, bits<8> opc231, + string OpStr, string PackTy, string Suff, + SDNode OpNode, RegisterClass RC, + X86MemOperand x86memop, X86FoldableSchedWrite sched> { + defm NAME#213#Suff : fma3s_rm_213; + defm NAME#231#Suff : fma3s_rm_231; + defm NAME#132#Suff : fma3s_rm_132; +} + +// These FMA*_Int instructions are defined specially for being used when +// the scalar FMA intrinsics are lowered to machine instructions, and in that +// sense, they are similar to existing ADD*_Int, SUB*_Int, MUL*_Int, etc. +// instructions. +// +// All of the FMA*_Int opcodes are defined as commutable here. +// Commuting the 2nd and 3rd source register operands of FMAs is quite trivial +// and the corresponding optimizations have been developed. +// Commuting the 1st operand of FMA*_Int requires some additional analysis, +// the commute optimization is legal only if all users of FMA*_Int use only +// the lowest element of the FMA*_Int instruction. Even though such analysis +// may be not implemented yet we allow the routines doing the actual commute +// transformation to decide if one or another instruction is commutable or not. +let Constraints = "$src1 = $dst", isCommutable = 1, isCodeGenOnly = 1, + hasSideEffects = 0 in +multiclass fma3s_rm_int opc, string OpcodeStr, + Operand memopr, RegisterClass RC, + X86FoldableSchedWrite sched> { + def r_Int : FMA3S_Int, Sched<[sched]>; + + let mayLoad = 1 in + def m_Int : FMA3S_Int, Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +// The FMA 213 form is created for lowering of scalar FMA intrinscis +// to machine instructions. +// The FMA 132 form can trivially be get by commuting the 2nd and 3rd operands +// of FMA 213 form. +// The FMA 231 form can be get only by commuting the 1st operand of 213 or 132 +// forms and is possible only after special analysis of all uses of the initial +// instruction. Such analysis do not exist yet and thus introducing the 231 +// form of FMA*_Int instructions is done using an optimistic assumption that +// such analysis will be implemented eventually. +multiclass fma3s_int_forms opc132, bits<8> opc213, bits<8> opc231, + string OpStr, string PackTy, string Suff, + RegisterClass RC, Operand memop, + X86FoldableSchedWrite sched> { + defm NAME#132#Suff : fma3s_rm_int; + defm NAME#213#Suff : fma3s_rm_int; + defm NAME#231#Suff : fma3s_rm_int; +} + +multiclass fma3s opc132, bits<8> opc213, bits<8> opc231, + string OpStr, SDNode OpNode, X86FoldableSchedWrite sched> { + let ExeDomain = SSEPackedSingle in + defm NAME : fma3s_forms, + fma3s_int_forms; + + let ExeDomain = SSEPackedDouble in + defm NAME : fma3s_forms, + fma3s_int_forms, VEX_W; +} + +defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", X86Fmadd, + SchedWriteFMA.Scl>, VEX_LIG; +defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", X86Fmsub, + SchedWriteFMA.Scl>, VEX_LIG; + +defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", X86Fnmadd, + SchedWriteFMA.Scl>, VEX_LIG; +defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", X86Fnmsub, + SchedWriteFMA.Scl>, VEX_LIG; + +multiclass scalar_fma_patterns { + let Predicates = [HasFMA, NoAVX512] in { + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op RC:$src2, + (EltVT (extractelt (VT VR128:$src1), (iPTR 0))), + RC:$src3))))), + (!cast(Prefix#"213"#Suffix#"r_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; + + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op RC:$src2, RC:$src3, + (EltVT (extractelt (VT VR128:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"r_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; + + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op RC:$src2, + (EltVT (extractelt (VT VR128:$src1), (iPTR 0))), + (mem_frag addr:$src3)))))), + (!cast(Prefix#"213"#Suffix#"m_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + addr:$src3)>; + + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op (EltVT (extractelt (VT VR128:$src1), (iPTR 0))), + (mem_frag addr:$src3), RC:$src2))))), + (!cast(Prefix#"132"#Suffix#"m_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + addr:$src3)>; + + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op RC:$src2, (mem_frag addr:$src3), + (EltVT (extractelt (VT VR128:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"m_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + addr:$src3)>; + } +} + +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; + +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; + +//===----------------------------------------------------------------------===// +// FMA4 - AMD 4 operand Fused Multiply-Add instructions +//===----------------------------------------------------------------------===// + +multiclass fma4s opc, string OpcodeStr, RegisterClass RC, + X86MemOperand x86memop, ValueType OpVT, SDNode OpNode, + PatFrag mem_frag, X86FoldableSchedWrite sched> { + let isCommutable = 1 in + def rr : FMA4S, VEX_W, VEX_LIG, + Sched<[sched]>; + def rm : FMA4S, VEX_W, VEX_LIG, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; + def mr : FMA4S, VEX_LIG, + Sched<[sched.Folded, ReadAfterLd, + // x86memop:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src3 + ReadAfterLd]>; +// For disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rr_REV : FMA4S, + VEX_LIG, FoldGenData, Sched<[sched]>; +} + +multiclass fma4s_int opc, string OpcodeStr, Operand memop, + ValueType VT, X86FoldableSchedWrite sched> { +let isCodeGenOnly = 1, hasSideEffects = 0 in { + def rr_Int : FMA4S_Int, VEX_W, VEX_LIG, Sched<[sched]>; + let mayLoad = 1 in + def rm_Int : FMA4S_Int, VEX_W, VEX_LIG, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; + let mayLoad = 1 in + def mr_Int : FMA4S_Int, + VEX_LIG, Sched<[sched.Folded, ReadAfterLd, + // memop:$src2 + ReadDefault, ReadDefault, ReadDefault, + ReadDefault, ReadDefault, + // VR128::$src3 + ReadAfterLd]>; + def rr_Int_REV : FMA4S_Int, VEX_LIG, FoldGenData, Sched<[sched]>; +} // isCodeGenOnly = 1 +} + +multiclass fma4p opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT128, ValueType OpVT256, + PatFrag ld_frag128, PatFrag ld_frag256, + X86SchedWriteWidths sched> { + let isCommutable = 1 in + def rr : FMA4, + VEX_W, Sched<[sched.XMM]>; + def rm : FMA4, VEX_W, + Sched<[sched.XMM.Folded, ReadAfterLd, ReadAfterLd]>; + def mr : FMA4, + Sched<[sched.XMM.Folded, ReadAfterLd, + // f128mem:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // VR128::$src3 + ReadAfterLd]>; + let isCommutable = 1 in + def Yrr : FMA4, + VEX_W, VEX_L, Sched<[sched.YMM]>; + def Yrm : FMA4, VEX_W, VEX_L, + Sched<[sched.YMM.Folded, ReadAfterLd, ReadAfterLd]>; + def Ymr : FMA4, VEX_L, + Sched<[sched.YMM.Folded, ReadAfterLd, + // f256mem:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // VR256::$src3 + ReadAfterLd]>; +// For disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { + def rr_REV : FMA4, + Sched<[sched.XMM]>, FoldGenData; + def Yrr_REV : FMA4, + VEX_L, Sched<[sched.YMM]>, FoldGenData; +} // isCodeGenOnly = 1 +} + +let ExeDomain = SSEPackedSingle in { + // Scalar Instructions + defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32, + SchedWriteFMA.Scl>, + fma4s_int<0x6A, "vfmaddss", ssmem, v4f32, + SchedWriteFMA.Scl>; + defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32, + SchedWriteFMA.Scl>, + fma4s_int<0x6E, "vfmsubss", ssmem, v4f32, + SchedWriteFMA.Scl>; + defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32, + X86Fnmadd, loadf32, SchedWriteFMA.Scl>, + fma4s_int<0x7A, "vfnmaddss", ssmem, v4f32, + SchedWriteFMA.Scl>; + defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32, + X86Fnmsub, loadf32, SchedWriteFMA.Scl>, + fma4s_int<0x7E, "vfnmsubss", ssmem, v4f32, + SchedWriteFMA.Scl>; + // Packed Instructions + defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; +} + +let ExeDomain = SSEPackedDouble in { + // Scalar Instructions + defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64, + SchedWriteFMA.Scl>, + fma4s_int<0x6B, "vfmaddsd", sdmem, v2f64, + SchedWriteFMA.Scl>; + defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64, + SchedWriteFMA.Scl>, + fma4s_int<0x6F, "vfmsubsd", sdmem, v2f64, + SchedWriteFMA.Scl>; + defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64, + X86Fnmadd, loadf64, SchedWriteFMA.Scl>, + fma4s_int<0x7B, "vfnmaddsd", sdmem, v2f64, + SchedWriteFMA.Scl>; + defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64, + X86Fnmsub, loadf64, SchedWriteFMA.Scl>, + fma4s_int<0x7F, "vfnmsubsd", sdmem, v2f64, + SchedWriteFMA.Scl>; + // Packed Instructions + defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; +} + +multiclass scalar_fma4_patterns { + let Predicates = [HasFMA4] in { + def : Pat<(VT (X86vzmovl (VT (scalar_to_vector + (Op RC:$src1, RC:$src2, RC:$src3))))), + (!cast(Name#"rr_Int") + (VT (COPY_TO_REGCLASS RC:$src1, VR128)), + (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; + + def : Pat<(VT (X86vzmovl (VT (scalar_to_vector + (Op RC:$src1, RC:$src2, + (mem_frag addr:$src3)))))), + (!cast(Name#"rm_Int") + (VT (COPY_TO_REGCLASS RC:$src1, VR128)), + (VT (COPY_TO_REGCLASS RC:$src2, VR128)), addr:$src3)>; + + def : Pat<(VT (X86vzmovl (VT (scalar_to_vector + (Op RC:$src1, (mem_frag addr:$src2), + RC:$src3))))), + (!cast(Name#"mr_Int") + (VT (COPY_TO_REGCLASS RC:$src1, VR128)), addr:$src2, + (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; + } +} + +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; + +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrFPStack.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrFPStack.td new file mode 100644 index 0000000..a21f077 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrFPStack.td @@ -0,0 +1,748 @@ +//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 x87 FPU instruction set, defining the +// instructions, and properties of the instructions which are needed for code +// generation, machine code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// FPStack specific DAG Nodes. +//===----------------------------------------------------------------------===// + +def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>, + SDTCisVT<1, f80>]>; +def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, + SDTCisPtrTy<1>, + SDTCisVT<2, OtherVT>]>; +def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, + SDTCisPtrTy<1>, + SDTCisVT<2, OtherVT>]>; +def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, + SDTCisVT<2, OtherVT>]>; +def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; +def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; + +def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; + +def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; +def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, + [SDNPHasChain, SDNPInGlue, SDNPMayStore, + SDNPMemOperand]>; +def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; +def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, + [SDNPHasChain, SDNPOutGlue, SDNPMayLoad, + SDNPMemOperand]>; +def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; +def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, + [SDNPHasChain, SDNPMayStore, SDNPSideEffect, + SDNPMemOperand]>; + +//===----------------------------------------------------------------------===// +// FPStack pattern fragments +//===----------------------------------------------------------------------===// + +def fpimm0 : FPImmLeaf; + +def fpimmneg0 : FPImmLeaf; + +def fpimm1 : FPImmLeaf; + +def fpimmneg1 : FPImmLeaf; + +/* +// Some 'special' instructions - expanded after instruction selection. +let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { + def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), + [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; + def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), + [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; + def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), + [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; + def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), + [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; + def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), + [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; + def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), + [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; + def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), + [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; + def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), + [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; + def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), + [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; +} +*/ + +// All FP Stack operations are represented with four instructions here. The +// first three instructions, generated by the instruction selector, use "RFP32" +// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, +// 64-bit or 80-bit floating point values. These sizes apply to the values, +// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be +// copied to each other without losing information. These instructions are all +// pseudo instructions and use the "_Fp" suffix. +// In some cases there are additional variants with a mixture of different +// register sizes. +// The second instruction is defined with FPI, which is the actual instruction +// emitted by the assembler. These use "RST" registers, although frequently +// the actual register(s) used are implicit. These are always 80 bits. +// The FP stackifier pass converts one to the other after register allocation +// occurs. +// +// Note that the FpI instruction should have instruction selection info (e.g. +// a pattern) and the FPI instruction should have emission info (e.g. opcode +// encoding and asm printing info). + +// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. +// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. +// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. +// f80 instructions cannot use SSE and use neither of these. +class FpIf32 pattern> : + FpI_, Requires<[FPStackf32]>; +class FpIf64 pattern> : + FpI_, Requires<[FPStackf64]>; + +// Factoring for arithmetic. +multiclass FPBinary_rr { +// Register op register -> register +// These are separated out because they have no reversed form. +def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, + [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; +def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, + [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; +def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, + [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; +} +// The FopST0 series are not included here because of the irregularities +// in where the 'r' goes in assembly output. +// These instructions cannot address 80-bit memory. +multiclass FPBinary { +let mayLoad = 1, hasSideEffects = 1 in { +// ST(0) = ST(0) + [mem] +def _Fp32m : FpIf32<(outs RFP32:$dst), + (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, + [!if(Forward, + (set RFP32:$dst, + (OpNode RFP32:$src1, (loadf32 addr:$src2))), + (set RFP32:$dst, + (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; +def _Fp64m : FpIf64<(outs RFP64:$dst), + (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, + [!if(Forward, + (set RFP64:$dst, + (OpNode RFP64:$src1, (loadf64 addr:$src2))), + (set RFP64:$dst, + (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; +def _Fp64m32: FpIf64<(outs RFP64:$dst), + (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, + [!if(Forward, + (set RFP64:$dst, + (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), + (set RFP64:$dst, + (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; +def _Fp80m32: FpI_<(outs RFP80:$dst), + (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, + [!if(Forward, + (set RFP80:$dst, + (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), + (set RFP80:$dst, + (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; +def _Fp80m64: FpI_<(outs RFP80:$dst), + (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, + [!if(Forward, + (set RFP80:$dst, + (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), + (set RFP80:$dst, + (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; +def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), + !strconcat("f", asmstring, "{s}\t$src")>; +def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), + !strconcat("f", asmstring, "{l}\t$src")>; +// ST(0) = ST(0) + [memint] +def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), + OneArgFPRW, + [!if(Forward, + (set RFP32:$dst, + (OpNode RFP32:$src1, (X86fild addr:$src2, i16))), + (set RFP32:$dst, + (OpNode (X86fild addr:$src2, i16), RFP32:$src1)))]>; +def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), + OneArgFPRW, + [!if(Forward, + (set RFP32:$dst, + (OpNode RFP32:$src1, (X86fild addr:$src2, i32))), + (set RFP32:$dst, + (OpNode (X86fild addr:$src2, i32), RFP32:$src1)))]>; +def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), + OneArgFPRW, + [!if(Forward, + (set RFP64:$dst, + (OpNode RFP64:$src1, (X86fild addr:$src2, i16))), + (set RFP64:$dst, + (OpNode (X86fild addr:$src2, i16), RFP64:$src1)))]>; +def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), + OneArgFPRW, + [!if(Forward, + (set RFP64:$dst, + (OpNode RFP64:$src1, (X86fild addr:$src2, i32))), + (set RFP64:$dst, + (OpNode (X86fild addr:$src2, i32), RFP64:$src1)))]>; +def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), + OneArgFPRW, + [!if(Forward, + (set RFP80:$dst, + (OpNode RFP80:$src1, (X86fild addr:$src2, i16))), + (set RFP80:$dst, + (OpNode (X86fild addr:$src2, i16), RFP80:$src1)))]>; +def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), + OneArgFPRW, + [!if(Forward, + (set RFP80:$dst, + (OpNode RFP80:$src1, (X86fild addr:$src2, i32))), + (set RFP80:$dst, + (OpNode (X86fild addr:$src2, i32), RFP80:$src1)))]>; +def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), + !strconcat("fi", asmstring, "{s}\t$src")>; +def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), + !strconcat("fi", asmstring, "{l}\t$src")>; +} // mayLoad = 1, hasSideEffects = 1 +} + +let Defs = [FPSW] in { +// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling +// resources. +let hasNoSchedulingInfo = 1 in { +defm ADD : FPBinary_rr; +defm SUB : FPBinary_rr; +defm MUL : FPBinary_rr; +defm DIV : FPBinary_rr; +} + +// Sets the scheduling resources for the actual NAME#_Fm definitions. +let SchedRW = [WriteFAddLd] in { +defm ADD : FPBinary; +defm SUB : FPBinary; +defm SUBR: FPBinary; +} + +let SchedRW = [WriteFMulLd] in { +defm MUL : FPBinary; +} + +let SchedRW = [WriteFDivLd] in { +defm DIV : FPBinary; +defm DIVR: FPBinary; +} +} // Defs = [FPSW] + +class FPST0rInst + : FPI<0xD8, fp, (outs), (ins RST:$op), asm>; +class FPrST0Inst + : FPI<0xDC, fp, (outs), (ins RST:$op), asm>; +class FPrST0PInst + : FPI<0xDE, fp, (outs), (ins RST:$op), asm>; + +// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion +// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, +// we have to put some 'r's in and take them out of weird places. +let SchedRW = [WriteFAdd] in { +def ADD_FST0r : FPST0rInst ; +def ADD_FrST0 : FPrST0Inst ; +def ADD_FPrST0 : FPrST0PInst; +def SUBR_FST0r : FPST0rInst ; +def SUB_FrST0 : FPrST0Inst ; +def SUB_FPrST0 : FPrST0PInst; +def SUB_FST0r : FPST0rInst ; +def SUBR_FrST0 : FPrST0Inst ; +def SUBR_FPrST0 : FPrST0PInst; +} // SchedRW +let SchedRW = [WriteFCom] in { +def COM_FST0r : FPST0rInst ; +def COMP_FST0r : FPST0rInst ; +} // SchedRW +let SchedRW = [WriteFMul] in { +def MUL_FST0r : FPST0rInst ; +def MUL_FrST0 : FPrST0Inst ; +def MUL_FPrST0 : FPrST0PInst; +} // SchedRW +let SchedRW = [WriteFDiv] in { +def DIVR_FST0r : FPST0rInst ; +def DIV_FrST0 : FPrST0Inst ; +def DIV_FPrST0 : FPrST0PInst; +def DIV_FST0r : FPST0rInst ; +def DIVR_FrST0 : FPrST0Inst ; +def DIVR_FPrST0 : FPrST0PInst; +} // SchedRW + +// Unary operations. +multiclass FPUnary { +def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, + [(set RFP32:$dst, (OpNode RFP32:$src))]>; +def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, + [(set RFP64:$dst, (OpNode RFP64:$src))]>; +def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, + [(set RFP80:$dst, (OpNode RFP80:$src))]>; +def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; +} + +let Defs = [FPSW] in { + +let SchedRW = [WriteFSign] in { +defm CHS : FPUnary; +defm ABS : FPUnary; +} + +let SchedRW = [WriteFSqrt80] in +defm SQRT: FPUnary; + +let SchedRW = [WriteMicrocoded] in { +defm SIN : FPUnary; +defm COS : FPUnary; +} + +let SchedRW = [WriteFCom] in { +let hasSideEffects = 0 in { +def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; +def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; +def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; +} // hasSideEffects + +def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; +} // SchedRW +} // Defs = [FPSW] + +// Versions of FP instructions that take a single memory operand. Added for the +// disassembler; remove as they are included with patterns elsewhere. +let SchedRW = [WriteFComLd] in { +def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; +def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; + +def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; +def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; + +def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; +def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; + +def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; +def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; +} // SchedRW + +let SchedRW = [WriteMicrocoded] in { +def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; +def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">; + +def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">; +def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">; +def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; + +def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\ttbyte ptr $src">; +def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\ttbyte ptr $dst">; +} // SchedRW + +// Floating point cmovs. +class FpIf32CMov pattern> : + FpI_, Requires<[FPStackf32, HasCMov]>; +class FpIf64CMov pattern> : + FpI_, Requires<[FPStackf64, HasCMov]>; + +multiclass FPCMov { + def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), + CondMovFP, + [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, + cc, EFLAGS))]>; + def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), + CondMovFP, + [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, + cc, EFLAGS))]>; + def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), + CondMovFP, + [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, + cc, EFLAGS))]>, + Requires<[HasCMov]>; +} + +let Defs = [FPSW] in { +let SchedRW = [WriteFCMOV] in { +let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { +defm CMOVB : FPCMov; +defm CMOVBE : FPCMov; +defm CMOVE : FPCMov; +defm CMOVP : FPCMov; +defm CMOVNB : FPCMov; +defm CMOVNBE: FPCMov; +defm CMOVNE : FPCMov; +defm CMOVNP : FPCMov; +} // Uses = [EFLAGS], Constraints = "$src1 = $dst" + +let Predicates = [HasCMov] in { +// These are not factored because there's no clean way to pass DA/DB. +def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RST:$op), + "fcmovb\t{$op, %st(0)|st(0), $op}">; +def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RST:$op), + "fcmovbe\t{$op, %st(0)|st(0), $op}">; +def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op), + "fcmove\t{$op, %st(0)|st(0), $op}">; +def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RST:$op), + "fcmovu\t{$op, %st(0)|st(0), $op}">; +def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RST:$op), + "fcmovnb\t{$op, %st(0)|st(0), $op}">; +def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RST:$op), + "fcmovnbe\t{$op, %st(0)|st(0), $op}">; +def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op), + "fcmovne\t{$op, %st(0)|st(0), $op}">; +def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op), + "fcmovnu\t{$op, %st(0)|st(0), $op}">; +} // Predicates = [HasCMov] +} // SchedRW + +// Floating point loads & stores. +let SchedRW = [WriteLoad] in { +let canFoldAsLoad = 1 in { +def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, + [(set RFP32:$dst, (loadf32 addr:$src))]>; +let isReMaterializable = 1 in + def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, + [(set RFP64:$dst, (loadf64 addr:$src))]>; +def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, + [(set RFP80:$dst, (loadf80 addr:$src))]>; +} // canFoldAsLoad +def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, + [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; +def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, + [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; +def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, + [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; +def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, + [(set RFP32:$dst, (X86fild addr:$src, i16))]>; +def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, + [(set RFP32:$dst, (X86fild addr:$src, i32))]>; +def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, + [(set RFP32:$dst, (X86fild addr:$src, i64))]>; +def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, + [(set RFP64:$dst, (X86fild addr:$src, i16))]>; +def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, + [(set RFP64:$dst, (X86fild addr:$src, i32))]>; +def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, + [(set RFP64:$dst, (X86fild addr:$src, i64))]>; +def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, + [(set RFP80:$dst, (X86fild addr:$src, i16))]>; +def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, + [(set RFP80:$dst, (X86fild addr:$src, i32))]>; +def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, + [(set RFP80:$dst, (X86fild addr:$src, i64))]>; +} // SchedRW + +let SchedRW = [WriteStore] in { +def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, + [(store RFP32:$src, addr:$op)]>; +def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, + [(truncstoref32 RFP64:$src, addr:$op)]>; +def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, + [(store RFP64:$src, addr:$op)]>; +def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, + [(truncstoref32 RFP80:$src, addr:$op)]>; +def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, + [(truncstoref64 RFP80:$src, addr:$op)]>; +// FST does not support 80-bit memory target; FSTP must be used. + +let mayStore = 1, hasSideEffects = 0 in { +def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; +def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; +def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; +def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; +def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; +} // mayStore + +def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, + [(store RFP80:$src, addr:$op)]>; + +let mayStore = 1, hasSideEffects = 0 in { +def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; +def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; +def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; +} // mayStore +} // SchedRW + +let mayLoad = 1, SchedRW = [WriteLoad] in { +def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; +def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">; +def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">; +def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">; +def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; +def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; +} +let mayStore = 1, SchedRW = [WriteStore] in { +def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; +def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; +def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; +def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">; +def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">; +def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">; +def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">; +def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">; +def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">; +def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">; +} + +// FISTTP requires SSE3 even though it's a FPStack op. +let Predicates = [HasSSE3], SchedRW = [WriteStore] in { +def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, + [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; +def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, + [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; +def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, + [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; +def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, + [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; +def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, + [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; +def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, + [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; +def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, + [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; +def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, + [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; +def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, + [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; +} // Predicates = [HasSSE3] + +let mayStore = 1, SchedRW = [WriteStore] in { +def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; +def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; +def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; +} + +// FP Stack manipulation instructions. +let SchedRW = [WriteMove] in { +def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op">; +def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op">; +def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op">; +def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op">; +} + +// Floating point constant loads. +let isReMaterializable = 1, SchedRW = [WriteZero] in { +def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, + [(set RFP32:$dst, fpimm0)]>; +def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, + [(set RFP32:$dst, fpimm1)]>; +def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, + [(set RFP64:$dst, fpimm0)]>; +def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, + [(set RFP64:$dst, fpimm1)]>; +def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, + [(set RFP80:$dst, fpimm0)]>; +def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, + [(set RFP80:$dst, fpimm1)]>; +} + +let SchedRW = [WriteFLD0] in +def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; + +let SchedRW = [WriteFLD1] in +def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">; + +let SchedRW = [WriteFLDC], Defs = [FPSW] in { +def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>; +def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>; +def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>; +def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>; +def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>; +} // SchedRW + +// Floating point compares. +let SchedRW = [WriteFCom] in { +def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, + [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>; +def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, + [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>; +def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, + [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>; +} // SchedRW +} // Defs = [FPSW] + +let SchedRW = [WriteFCom] in { +// CC = ST(0) cmp ST(i) +let Defs = [EFLAGS, FPSW] in { +def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, + [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>; +def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, + [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>; +def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; +} + +let Defs = [FPSW], Uses = [ST0] in { +def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) + (outs), (ins RST:$reg), "fucom\t$reg">; +def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop + (outs), (ins RST:$reg), "fucomp\t$reg">; +def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop + (outs), (ins), "fucompp">; +} + +let Defs = [EFLAGS, FPSW], Uses = [ST0] in { +def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) + (outs), (ins RST:$reg), "fucomi\t$reg">; +def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop + (outs), (ins RST:$reg), "fucompi\t$reg">; +} + +let Defs = [EFLAGS, FPSW] in { +def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg), "fcomi\t$reg">; +def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), "fcompi\t$reg">; +} +} // SchedRW + +// Floating point flag ops. +let SchedRW = [WriteALU] in { +let Defs = [AX], Uses = [FPSW] in +def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags + (outs), (ins), "fnstsw\t{%ax|ax}", + [(set AX, (X86fp_stsw FPSW))]>; +let Defs = [FPSW] in +def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world + (outs), (ins i16mem:$dst), "fnstcw\t$dst", + [(X86fp_cwd_get16 addr:$dst)]>; +} // SchedRW +let Defs = [FPSW], mayLoad = 1 in +def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] + (outs), (ins i16mem:$dst), "fldcw\t$dst", []>, + Sched<[WriteLoad]>; + +// FPU control instructions +let SchedRW = [WriteMicrocoded] in { +let Defs = [FPSW] in { +def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>; +def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), "ffree\t$reg">; +def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RST:$reg), "ffreep\t$reg">; + +def FPNCEST0r : FPI<0xD9, MRM3r, (outs RST:$op), (ins), + "fstpnce\t{%st(0), $op|$op, st(0)}">; + +def FENI8087_NOP : I<0xDB, MRM_E0, (outs), (ins), "feni8087_nop", []>; + +def FDISI8087_NOP : I<0xDB, MRM_E1, (outs), (ins), "fdisi8087_nop", []>; + +// Clear exceptions +def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>; +} // Defs = [FPSW] +} // SchedRW + +// Operand-less floating-point instructions for the disassembler. +def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>; + +let SchedRW = [WriteMicrocoded] in { +let Defs = [FPSW] in { +def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; +def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>; +def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>; +def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>; +def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>; +def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>; +def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>; +def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>; +def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>; +def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>; +def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>; +def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>; +def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>; +def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>; +def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>; +def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>; +} // Defs = [FPSW] + +def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst), + "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB, + Requires<[HasFXSR]>; +def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst), + "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>, + TB, Requires<[HasFXSR, In64BitMode]>; +def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src), + "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>, + TB, Requires<[HasFXSR]>; +def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src), + "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>, + TB, Requires<[HasFXSR, In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Non-Instruction Patterns +//===----------------------------------------------------------------------===// + +// Required for RET of f32 / f64 / f80 values. +def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>; +def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>; +def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>; + +// Required for CALL which return f32 / f64 / f80 values. +def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>; +def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, + RFP64:$src)>; +def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>; +def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, + RFP80:$src)>; +def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, + RFP80:$src)>; +def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, + RFP80:$src)>; + +// Floating point constant -0.0 and -1.0 +def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; +def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; +def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; +def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; +def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; +def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; + +// Used to conv. i64 to f64 since there isn't a SSE version. +def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>; + +// FP extensions map onto simple pseudo-value conversions if they are to/from +// the FP stack. +def : Pat<(f64 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, + Requires<[FPStackf32]>; +def : Pat<(f80 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, + Requires<[FPStackf32]>; +def : Pat<(f80 (fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, + Requires<[FPStackf64]>; + +// FP truncations map onto simple pseudo-value conversions if they are to/from +// the FP stack. We have validated that only value-preserving truncations make +// it through isel. +def : Pat<(f32 (fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, + Requires<[FPStackf32]>; +def : Pat<(f32 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, + Requires<[FPStackf32]>; +def : Pat<(f64 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, + Requires<[FPStackf64]>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrFormats.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrFormats.td new file mode 100644 index 0000000..47d4719 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrFormats.td @@ -0,0 +1,993 @@ +//===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// X86 Instruction Format Definitions. +// + +// Format specifies the encoding used by the instruction. This is part of the +// ad-hoc solution used to emit machine instruction encodings by our machine +// code emitter. +class Format val> { + bits<7> Value = val; +} + +def Pseudo : Format<0>; +def RawFrm : Format<1>; +def AddRegFrm : Format<2>; +def RawFrmMemOffs : Format<3>; +def RawFrmSrc : Format<4>; +def RawFrmDst : Format<5>; +def RawFrmDstSrc : Format<6>; +def RawFrmImm8 : Format<7>; +def RawFrmImm16 : Format<8>; +def MRMDestMem : Format<32>; +def MRMSrcMem : Format<33>; +def MRMSrcMem4VOp3 : Format<34>; +def MRMSrcMemOp4 : Format<35>; +def MRMXm : Format<39>; +def MRM0m : Format<40>; def MRM1m : Format<41>; def MRM2m : Format<42>; +def MRM3m : Format<43>; def MRM4m : Format<44>; def MRM5m : Format<45>; +def MRM6m : Format<46>; def MRM7m : Format<47>; +def MRMDestReg : Format<48>; +def MRMSrcReg : Format<49>; +def MRMSrcReg4VOp3 : Format<50>; +def MRMSrcRegOp4 : Format<51>; +def MRMXr : Format<55>; +def MRM0r : Format<56>; def MRM1r : Format<57>; def MRM2r : Format<58>; +def MRM3r : Format<59>; def MRM4r : Format<60>; def MRM5r : Format<61>; +def MRM6r : Format<62>; def MRM7r : Format<63>; +def MRM_C0 : Format<64>; def MRM_C1 : Format<65>; def MRM_C2 : Format<66>; +def MRM_C3 : Format<67>; def MRM_C4 : Format<68>; def MRM_C5 : Format<69>; +def MRM_C6 : Format<70>; def MRM_C7 : Format<71>; def MRM_C8 : Format<72>; +def MRM_C9 : Format<73>; def MRM_CA : Format<74>; def MRM_CB : Format<75>; +def MRM_CC : Format<76>; def MRM_CD : Format<77>; def MRM_CE : Format<78>; +def MRM_CF : Format<79>; def MRM_D0 : Format<80>; def MRM_D1 : Format<81>; +def MRM_D2 : Format<82>; def MRM_D3 : Format<83>; def MRM_D4 : Format<84>; +def MRM_D5 : Format<85>; def MRM_D6 : Format<86>; def MRM_D7 : Format<87>; +def MRM_D8 : Format<88>; def MRM_D9 : Format<89>; def MRM_DA : Format<90>; +def MRM_DB : Format<91>; def MRM_DC : Format<92>; def MRM_DD : Format<93>; +def MRM_DE : Format<94>; def MRM_DF : Format<95>; def MRM_E0 : Format<96>; +def MRM_E1 : Format<97>; def MRM_E2 : Format<98>; def MRM_E3 : Format<99>; +def MRM_E4 : Format<100>; def MRM_E5 : Format<101>; def MRM_E6 : Format<102>; +def MRM_E7 : Format<103>; def MRM_E8 : Format<104>; def MRM_E9 : Format<105>; +def MRM_EA : Format<106>; def MRM_EB : Format<107>; def MRM_EC : Format<108>; +def MRM_ED : Format<109>; def MRM_EE : Format<110>; def MRM_EF : Format<111>; +def MRM_F0 : Format<112>; def MRM_F1 : Format<113>; def MRM_F2 : Format<114>; +def MRM_F3 : Format<115>; def MRM_F4 : Format<116>; def MRM_F5 : Format<117>; +def MRM_F6 : Format<118>; def MRM_F7 : Format<119>; def MRM_F8 : Format<120>; +def MRM_F9 : Format<121>; def MRM_FA : Format<122>; def MRM_FB : Format<123>; +def MRM_FC : Format<124>; def MRM_FD : Format<125>; def MRM_FE : Format<126>; +def MRM_FF : Format<127>; + +// ImmType - This specifies the immediate type used by an instruction. This is +// part of the ad-hoc solution used to emit machine instruction encodings by our +// machine code emitter. +class ImmType val> { + bits<4> Value = val; +} +def NoImm : ImmType<0>; +def Imm8 : ImmType<1>; +def Imm8PCRel : ImmType<2>; +def Imm8Reg : ImmType<3>; // Register encoded in [7:4]. +def Imm16 : ImmType<4>; +def Imm16PCRel : ImmType<5>; +def Imm32 : ImmType<6>; +def Imm32PCRel : ImmType<7>; +def Imm32S : ImmType<8>; +def Imm64 : ImmType<9>; + +// FPFormat - This specifies what form this FP instruction has. This is used by +// the Floating-Point stackifier pass. +class FPFormat val> { + bits<3> Value = val; +} +def NotFP : FPFormat<0>; +def ZeroArgFP : FPFormat<1>; +def OneArgFP : FPFormat<2>; +def OneArgFPRW : FPFormat<3>; +def TwoArgFP : FPFormat<4>; +def CompareFP : FPFormat<5>; +def CondMovFP : FPFormat<6>; +def SpecialFP : FPFormat<7>; + +// Class specifying the SSE execution domain, used by the SSEDomainFix pass. +// Keep in sync with tables in X86InstrInfo.cpp. +class Domain val> { + bits<2> Value = val; +} +def GenericDomain : Domain<0>; +def SSEPackedSingle : Domain<1>; +def SSEPackedDouble : Domain<2>; +def SSEPackedInt : Domain<3>; + +// Class specifying the vector form of the decompressed +// displacement of 8-bit. +class CD8VForm val> { + bits<3> Value = val; +} +def CD8VF : CD8VForm<0>; // v := VL +def CD8VH : CD8VForm<1>; // v := VL/2 +def CD8VQ : CD8VForm<2>; // v := VL/4 +def CD8VO : CD8VForm<3>; // v := VL/8 +// The tuple (subvector) forms. +def CD8VT1 : CD8VForm<4>; // v := 1 +def CD8VT2 : CD8VForm<5>; // v := 2 +def CD8VT4 : CD8VForm<6>; // v := 4 +def CD8VT8 : CD8VForm<7>; // v := 8 + +// Class specifying the prefix used an opcode extension. +class Prefix val> { + bits<3> Value = val; +} +def NoPrfx : Prefix<0>; +def PD : Prefix<1>; +def XS : Prefix<2>; +def XD : Prefix<3>; +def PS : Prefix<4>; // Similar to NoPrfx, but disassembler uses this to know + // that other instructions with this opcode use PD/XS/XD + // and if any of those is not supported they shouldn't + // decode to this instruction. e.g. ANDSS/ANDSD don't + // exist, but the 0xf2/0xf3 encoding shouldn't + // disable to ANDPS. + +// Class specifying the opcode map. +class Map val> { + bits<3> Value = val; +} +def OB : Map<0>; +def TB : Map<1>; +def T8 : Map<2>; +def TA : Map<3>; +def XOP8 : Map<4>; +def XOP9 : Map<5>; +def XOPA : Map<6>; +def ThreeDNow : Map<7>; + +// Class specifying the encoding +class Encoding val> { + bits<2> Value = val; +} +def EncNormal : Encoding<0>; +def EncVEX : Encoding<1>; +def EncXOP : Encoding<2>; +def EncEVEX : Encoding<3>; + +// Operand size for encodings that change based on mode. +class OperandSize val> { + bits<2> Value = val; +} +def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix. +def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode. +def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode. + +// Address size for encodings that change based on mode. +class AddressSize val> { + bits<2> Value = val; +} +def AdSizeX : AddressSize<0>; // Address size determined using addr operand. +def AdSize16 : AddressSize<1>; // Encodes a 16-bit address. +def AdSize32 : AddressSize<2>; // Encodes a 32-bit address. +def AdSize64 : AddressSize<3>; // Encodes a 64-bit address. + +// Prefix byte classes which are used to indicate to the ad-hoc machine code +// emitter that various prefix bytes are required. +class OpSize16 { OperandSize OpSize = OpSize16; } +class OpSize32 { OperandSize OpSize = OpSize32; } +class AdSize16 { AddressSize AdSize = AdSize16; } +class AdSize32 { AddressSize AdSize = AdSize32; } +class AdSize64 { AddressSize AdSize = AdSize64; } +class REX_W { bit hasREX_WPrefix = 1; } +class LOCK { bit hasLockPrefix = 1; } +class REP { bit hasREPPrefix = 1; } +class TB { Map OpMap = TB; } +class T8 { Map OpMap = T8; } +class TA { Map OpMap = TA; } +class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; } +class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; } +class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; } +class ThreeDNow { Map OpMap = ThreeDNow; } +class OBXS { Prefix OpPrefix = XS; } +class PS : TB { Prefix OpPrefix = PS; } +class PD : TB { Prefix OpPrefix = PD; } +class XD : TB { Prefix OpPrefix = XD; } +class XS : TB { Prefix OpPrefix = XS; } +class T8PS : T8 { Prefix OpPrefix = PS; } +class T8PD : T8 { Prefix OpPrefix = PD; } +class T8XD : T8 { Prefix OpPrefix = XD; } +class T8XS : T8 { Prefix OpPrefix = XS; } +class TAPS : TA { Prefix OpPrefix = PS; } +class TAPD : TA { Prefix OpPrefix = PD; } +class TAXD : TA { Prefix OpPrefix = XD; } +class VEX { Encoding OpEnc = EncVEX; } +class VEX_W { bits<2> VEX_WPrefix = 1; } +class VEX_WIG { bits<2> VEX_WPrefix = 2; } +// Special version of VEX_W that can be changed to VEX.W==0 for EVEX2VEX. +// FIXME: We should consider adding separate bits for VEX_WIG and the extra +// part of W1X. This would probably simplify the tablegen emitters and +// the TSFlags creation below. +class VEX_W1X { bits<2> VEX_WPrefix = 3; } +class VEX_4V : VEX { bit hasVEX_4V = 1; } +class VEX_L { bit hasVEX_L = 1; } +class VEX_LIG { bit ignoresVEX_L = 1; } +class EVEX { Encoding OpEnc = EncEVEX; } +class EVEX_4V : EVEX { bit hasVEX_4V = 1; } +class EVEX_K { bit hasEVEX_K = 1; } +class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; } +class EVEX_B { bit hasEVEX_B = 1; } +class EVEX_RC { bit hasEVEX_RC = 1; } +class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; } +class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; } +class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; } +class NOTRACK { bit hasNoTrackPrefix = 1; } + +// Specify AVX512 8-bit compressed displacement encoding based on the vector +// element size in bits (8, 16, 32, 64) and the CDisp8 form. +class EVEX_CD8 { + int CD8_EltSize = !srl(esize, 3); + bits<3> CD8_Form = form.Value; +} + +class XOP { Encoding OpEnc = EncXOP; } +class XOP_4V : XOP { bit hasVEX_4V = 1; } + +// Specify the alternative register form instruction to replace the current +// instruction in case it was picked during generation of memory folding tables +class FoldGenData { + string FoldGenRegForm = _RegisterForm; +} + +// Provide a specific instruction to be used by the EVEX2VEX conversion. +class EVEX2VEXOverride { + string EVEX2VEXOverride = VEXInstrName; +} + +// Mark the instruction as "illegal to memory fold/unfold" +class NotMemoryFoldable { bit isMemoryFoldable = 0; } + +// Prevent EVEX->VEX conversion from considering this instruction. +class NotEVEX2VEXConvertible { bit notEVEX2VEXConvertible = 1; } + +class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, + string AsmStr, Domain d = GenericDomain> + : Instruction { + let Namespace = "X86"; + + bits<8> Opcode = opcod; + Format Form = f; + bits<7> FormBits = Form.Value; + ImmType ImmT = i; + + dag OutOperandList = outs; + dag InOperandList = ins; + string AsmString = AsmStr; + + // If this is a pseudo instruction, mark it isCodeGenOnly. + let isCodeGenOnly = !eq(!cast(f), "Pseudo"); + + // + // Attributes specific to X86 instructions... + // + bit ForceDisassemble = 0; // Force instruction to disassemble even though it's + // isCodeGenonly. Needed to hide an ambiguous + // AsmString from the parser, but still disassemble. + + OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change + // based on operand size of the mode? + bits<2> OpSizeBits = OpSize.Value; + AddressSize AdSize = AdSizeX; // Does this instruction's encoding change + // based on address size of the mode? + bits<2> AdSizeBits = AdSize.Value; + + Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have? + bits<3> OpPrefixBits = OpPrefix.Value; + Map OpMap = OB; // Which opcode map does this inst have? + bits<3> OpMapBits = OpMap.Value; + bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix? + FPFormat FPForm = NotFP; // What flavor of FP instruction is this? + bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? + Domain ExeDomain = d; + bit hasREPPrefix = 0; // Does this inst have a REP prefix? + Encoding OpEnc = EncNormal; // Encoding used by this instruction + bits<2> OpEncBits = OpEnc.Value; + bits<2> VEX_WPrefix = 0; // Does this inst set the VEX_W field? + bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field? + bit hasVEX_L = 0; // Does this inst use large (256-bit) registers? + bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit + bit hasEVEX_K = 0; // Does this inst require masking? + bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field? + bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field? + bit hasEVEX_B = 0; // Does this inst set the EVEX_B field? + bits<3> CD8_Form = 0; // Compressed disp8 form - vector-width. + // Declare it int rather than bits<4> so that all bits are defined when + // assigning to bits<7>. + int CD8_EltSize = 0; // Compressed disp8 form - element-size in bytes. + bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction. + bit hasNoTrackPrefix = 0; // Does this inst has 0x3E (NoTrack) prefix? + + bits<2> EVEX_LL; + let EVEX_LL{0} = hasVEX_L; + let EVEX_LL{1} = hasEVEX_L2; + // Vector size in bytes. + bits<7> VectSize = !shl(16, EVEX_LL); + + // The scaling factor for AVX512's compressed displacement is either + // - the size of a power-of-two number of elements or + // - the size of a single element for broadcasts or + // - the total vector size divided by a power-of-two number. + // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64. + bits<7> CD8_Scale = !if (!eq (OpEnc.Value, EncEVEX.Value), + !if (CD8_Form{2}, + !shl(CD8_EltSize, CD8_Form{1-0}), + !if (hasEVEX_B, + CD8_EltSize, + !srl(VectSize, CD8_Form{1-0}))), 0); + + // Used in the memory folding generation (TableGen backend) to point to an alternative + // instruction to replace the current one in case it got picked during generation. + string FoldGenRegForm = ?; + + // Used to prevent an explicit EVEX2VEX override for this instruction. + string EVEX2VEXOverride = ?; + + bit isMemoryFoldable = 1; // Is it allowed to memory fold/unfold this instruction? + bit notEVEX2VEXConvertible = 0; // Prevent EVEX->VEX conversion. + + // TSFlags layout should be kept in sync with X86BaseInfo.h. + let TSFlags{6-0} = FormBits; + let TSFlags{8-7} = OpSizeBits; + let TSFlags{10-9} = AdSizeBits; + // No need for 3rd bit, we don't need to distinguish NoPrfx from PS. + let TSFlags{12-11} = OpPrefixBits{1-0}; + let TSFlags{15-13} = OpMapBits; + let TSFlags{16} = hasREX_WPrefix; + let TSFlags{20-17} = ImmT.Value; + let TSFlags{23-21} = FPForm.Value; + let TSFlags{24} = hasLockPrefix; + let TSFlags{25} = hasREPPrefix; + let TSFlags{27-26} = ExeDomain.Value; + let TSFlags{29-28} = OpEncBits; + let TSFlags{37-30} = Opcode; + // Currently no need for second bit in TSFlags - W Ignore is equivalent to 0. + let TSFlags{38} = VEX_WPrefix{0}; + let TSFlags{39} = hasVEX_4V; + let TSFlags{40} = hasVEX_L; + let TSFlags{41} = hasEVEX_K; + let TSFlags{42} = hasEVEX_Z; + let TSFlags{43} = hasEVEX_L2; + let TSFlags{44} = hasEVEX_B; + // If we run out of TSFlags bits, it's possible to encode this in 3 bits. + let TSFlags{51-45} = CD8_Scale; + let TSFlags{52} = hasEVEX_RC; + let TSFlags{53} = hasNoTrackPrefix; +} + +class PseudoI pattern> + : X86Inst<0, Pseudo, NoImm, oops, iops, ""> { + let Pattern = pattern; +} + +class I o, Format f, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii8 o, Format f, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii8Reg o, Format f, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii8PCRel o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii16 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii32 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii32S o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +class Ii64 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +class Ii16PCRel o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +class Ii32PCRel o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +// FPStack Instruction Templates: +// FPI - Floating Point Instruction template. +class FPI o, Format F, dag outs, dag ins, string asm> + : I {} + +// FpI_ - Floating Point Pseudo Instruction template. Not Predicated. +class FpI_ pattern> + : PseudoI { + let FPForm = fp; +} + +// Templates for instructions that use a 16- or 32-bit segmented address as +// their only operand: lcall (FAR CALL) and ljmp (FAR JMP) +// +// Iseg16 - 16-bit segment selector, 16-bit offset +// Iseg32 - 16-bit segment selector, 32-bit offset + +class Iseg16 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +class Iseg32 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +// SI - SSE 1 & 2 scalar instructions +class SI o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : I { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], + !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], + !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], + !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], + [UseSSE1]))))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} + +// SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512 +class SI_Int o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : I { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], + !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], + !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], + !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], + [UseSSE1]))))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} +// SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512 +class SIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8 { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], + !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], + [UseSSE2]))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} + +// PI - SSE 1 & 2 packed instructions +class PI o, Format F, dag outs, dag ins, string asm, list pattern, + Domain d> + : I { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], + !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], + [UseSSE1]))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} + +// MMXPI - SSE 1 & 2 packed instructions with MMX operands +class MMXPI o, Format F, dag outs, dag ins, string asm, list pattern, + Domain d> + : I { + let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasMMX, HasSSE2], + [HasMMX, HasSSE1]); +} + +// PIi8 - SSE 1 & 2 packed instructions with immediate +class PIi8 o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d> + : Ii8 { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], + !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], + [UseSSE1]))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} + +// SSE1 Instruction Templates: +// +// SSI - SSE1 instructions with XS prefix. +// PSI - SSE1 instructions with PS prefix. +// PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix. +// VSSI - SSE1 instructions with XS prefix in AVX form. +// VPSI - SSE1 instructions with PS prefix in AVX form, packed single. + +class SSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, Requires<[UseSSE1]>; +class SSIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[UseSSE1]>; +class PSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, + Requires<[UseSSE1]>; +class PSIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, PS, + Requires<[UseSSE1]>; +class VSSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, + Requires<[HasAVX]>; +class VPSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, + Requires<[HasAVX]>; + +// SSE2 Instruction Templates: +// +// SDI - SSE2 instructions with XD prefix. +// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. +// S2SI - SSE2 instructions with XS prefix. +// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. +// PDI - SSE2 instructions with PD prefix, packed double domain. +// PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix. +// VSDI - SSE2 scalar instructions with XD prefix in AVX form. +// VPDI - SSE2 vector instructions with PD prefix in AVX form, +// packed double domain. +// VS2I - SSE2 scalar instructions with PD prefix in AVX form. +// S2I - SSE2 scalar instructions with PD prefix. +// MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as +// MMX operands. +// MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as +// MMX operands. + +class SDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XD, Requires<[UseSSE2]>; +class SDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XD, Requires<[UseSSE2]>; +class S2SI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, Requires<[UseSSE2]>; +class S2SIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[UseSSE2]>; +class PDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[UseSSE2]>; +class PDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, PD, + Requires<[UseSSE2]>; +class VSDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XD, + Requires<[UseAVX]>; +class VS2SI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, + Requires<[HasAVX]>; +class VPDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, + PD, Requires<[HasAVX]>; +class VS2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[UseAVX]>; +class S2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, Requires<[UseSSE2]>; +class MMXSDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XD, Requires<[HasMMX, HasSSE2]>; +class MMXS2SIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[HasMMX, HasSSE2]>; + +// SSE3 Instruction Templates: +// +// S3I - SSE3 instructions with PD prefixes. +// S3SI - SSE3 instructions with XS prefix. +// S3DI - SSE3 instructions with XD prefix. + +class S3SI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, + Requires<[UseSSE3]>; +class S3DI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XD, + Requires<[UseSSE3]>; +class S3I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[UseSSE3]>; + + +// SSSE3 Instruction Templates: +// +// SS38I - SSSE3 instructions with T8 prefix. +// SS3AI - SSSE3 instructions with TA prefix. +// MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands. +// MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands. +// +// Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version +// uses the MMX registers. The 64-bit versions are grouped with the MMX +// classes. They need to be enabled even if AVX is enabled. + +class SS38I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[UseSSSE3]>; +class SS3AI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[UseSSSE3]>; +class MMXSS38I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PS, + Requires<[HasMMX, HasSSSE3]>; +class MMXSS3AI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPS, + Requires<[HasMMX, HasSSSE3]>; + +// SSE4.1 Instruction Templates: +// +// SS48I - SSE 4.1 instructions with T8 prefix. +// SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. +// +class SS48I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[UseSSE41]>; +class SS4AIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[UseSSE41]>; + +// SSE4.2 Instruction Templates: +// +// SS428I - SSE 4.2 instructions with T8 prefix. +class SS428I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[UseSSE42]>; + +// SS42FI - SSE 4.2 instructions with T8XD prefix. +// NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns. +class SS42FI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8XD, Requires<[HasSSE42]>; + +// SS42AI = SSE 4.2 instructions with TA prefix +class SS42AI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[UseSSE42]>; + +// AVX Instruction Templates: +// Instructions introduced in AVX (no SSE equivalent forms) +// +// AVX8I - AVX instructions with T8PD prefix. +// AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8. +class AVX8I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[HasAVX]>; +class AVXAIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[HasAVX]>; + +// AVX2 Instruction Templates: +// Instructions introduced in AVX2 (no SSE equivalent forms) +// +// AVX28I - AVX2 instructions with T8PD prefix. +// AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8. +class AVX28I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[HasAVX2]>; +class AVX2AIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[HasAVX2]>; + + +// AVX-512 Instruction Templates: +// Instructions introduced in AVX-512 (no SSE equivalent forms) +// +// AVX5128I - AVX-512 instructions with T8PD prefix. +// AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8. +// AVX512PDI - AVX-512 instructions with PD, double packed. +// AVX512PSI - AVX-512 instructions with PS, single packed. +// AVX512XS8I - AVX-512 instructions with T8 and XS prefixes. +// AVX512XSI - AVX-512 instructions with XS prefix, generic domain. +// AVX512BI - AVX-512 instructions with PD, int packed domain. +// AVX512SI - AVX-512 scalar instructions with PD prefix. + +class AVX5128I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[HasAVX512]>; +class AVX5128IBase : T8PD { + Domain ExeDomain = SSEPackedInt; +} +class AVX512XS8I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8XS, + Requires<[HasAVX512]>; +class AVX512XSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, + Requires<[HasAVX512]>; +class AVX512XDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XD, + Requires<[HasAVX512]>; +class AVX512BI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[HasAVX512]>; +class AVX512BIBase : PD { + Domain ExeDomain = SSEPackedInt; +} +class AVX512BIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, PD, + Requires<[HasAVX512]>; +class AVX512BIi8Base : PD { + Domain ExeDomain = SSEPackedInt; + ImmType ImmT = Imm8; +} +class AVX512XSIi8Base : XS { + Domain ExeDomain = SSEPackedInt; + ImmType ImmT = Imm8; +} +class AVX512XDIi8Base : XD { + Domain ExeDomain = SSEPackedInt; + ImmType ImmT = Imm8; +} +class AVX512PSIi8Base : PS { + Domain ExeDomain = SSEPackedSingle; + ImmType ImmT = Imm8; +} +class AVX512PDIi8Base : PD { + Domain ExeDomain = SSEPackedDouble; + ImmType ImmT = Imm8; +} +class AVX512AIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[HasAVX512]>; +class AVX512AIi8Base : TAPD { + ImmType ImmT = Imm8; +} +class AVX512Ii8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, + Requires<[HasAVX512]>; +class AVX512PDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[HasAVX512]>; +class AVX512PSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, + Requires<[HasAVX512]>; +class AVX512PIi8 o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d> + : Ii8, Requires<[HasAVX512]>; +class AVX512PI o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d> + : I, Requires<[HasAVX512]>; +class AVX512FMA3S o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + EVEX_4V, Requires<[HasAVX512]>; +class AVX512FMA3Base : T8PD, EVEX_4V; + +class AVX512 o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, Requires<[HasAVX512]>; + +// AES Instruction Templates: +// +// AES8I +// These use the same encoding as the SSE4.2 T8 and TA encodings. +class AES8I o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + Requires<[NoAVX, HasAES]>; + +class AESAI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[NoAVX, HasAES]>; + +// PCLMUL Instruction Templates +class PCLMULIi8 o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8, TAPD; + +// FMA3 Instruction Templates +class FMA3 o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoVLX]>; +class FMA3S o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoAVX512]>; +class FMA3S_Int o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + VEX_4V, FMASC, Requires<[HasFMA, NoAVX512]>; + +// FMA4 Instruction Templates +class FMA4 o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8Reg, TAPD, + VEX_4V, FMASC, Requires<[HasFMA4, NoVLX]>; +class FMA4S o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8Reg, TAPD, + VEX_4V, FMASC, Requires<[HasFMA4, NoAVX512]>; +class FMA4S_Int o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8Reg, TAPD, + VEX_4V, FMASC, Requires<[HasFMA4]>; + +// XOP 2, 3 and 4 Operand Instruction Template +class IXOP o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, + XOP9, Requires<[HasXOP]>; + +// XOP 2 and 3 Operand Instruction Templates with imm byte +class IXOPi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, + XOP8, Requires<[HasXOP]>; +// XOP 4 Operand Instruction Templates with imm byte +class IXOPi8Reg o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8Reg, + XOP8, Requires<[HasXOP]>; + +// XOP 5 operand instruction (VEX encoding!) +class IXOP5 o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8Reg, TAPD, + VEX_4V, Requires<[HasXOP]>; + +// X86-64 Instruction templates... +// + +class RI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, REX_W; +class RIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, REX_W; +class RIi16 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii16, REX_W; +class RIi32 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii32, REX_W; +class RIi32S o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii32S, REX_W; +class RIi64 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii64, REX_W; + +class RS2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : S2I, REX_W; +class VRS2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : VS2I, VEX_W; + +// MMX Instruction templates +// + +// MMXI - MMX instructions with TB prefix. +// MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode. +// MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode. +// MMX2I - MMX / SSE2 instructions with PD prefix. +// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. +// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. +// MMXID - MMX instructions with XD prefix. +// MMXIS - MMX instructions with XS prefix. +class MMXI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, Requires<[HasMMX]>; +class MMXI32 o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, Requires<[HasMMX,Not64BitMode]>; +class MMXI64 o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, Requires<[HasMMX,In64BitMode]>; +class MMXRI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, REX_W, Requires<[HasMMX]>; +class MMX2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, Requires<[HasMMX]>; +class MMXIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, PS, Requires<[HasMMX]>; +class MMXID o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XD, Requires<[HasMMX]>; +class MMXIS o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[HasMMX]>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrFragmentsSIMD.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrFragmentsSIMD.td new file mode 100644 index 0000000..7392759 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrFragmentsSIMD.td @@ -0,0 +1,1075 @@ +//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides pattern fragments useful for SIMD instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// MMX specific DAG Nodes. +//===----------------------------------------------------------------------===// + +// Low word of MMX to GPR. +def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1, + [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>; +// GPR to low word of MMX. +def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1, + [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>; + +//===----------------------------------------------------------------------===// +// MMX Pattern Fragments +//===----------------------------------------------------------------------===// + +def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>; + +//===----------------------------------------------------------------------===// +// SSE specific DAG Nodes. +//===----------------------------------------------------------------------===// + +def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, + SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, + SDTCisVT<3, i8>]>; + +def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; +def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; +def X86fmins : SDNode<"X86ISD::FMINS", SDTFPBinOp>; +def X86fmaxs : SDNode<"X86ISD::FMAXS", SDTFPBinOp>; + +// Commutative and Associative FMIN and FMAX. +def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; + +def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp>; +def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; +def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; +def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; +def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; +def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>; +def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>; +def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; +def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; +def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>; +def X86pshufb : SDNode<"X86ISD::PSHUFB", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>]>>; +def X86psadbw : SDNode<"X86ISD::PSADBW", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, + SDTCVecEltisVT<1, i8>, + SDTCisSameSizeAs<0,1>, + SDTCisSameAs<1,2>]>, [SDNPCommutative]>; +def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW", + SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>, + SDTCVecEltisVT<1, i8>, + SDTCisSameSizeAs<0,1>, + SDTCisSameAs<1,2>, SDTCisInt<3>]>>; +def X86andnp : SDNode<"X86ISD::ANDNP", + SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>]>>; +def X86multishift : SDNode<"X86ISD::MULTISHIFT", + SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisSameAs<1,2>]>>; +def X86pextrb : SDNode<"X86ISD::PEXTRB", + SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>, + SDTCisPtrTy<2>]>>; +def X86pextrw : SDNode<"X86ISD::PEXTRW", + SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>, + SDTCisPtrTy<2>]>>; +def X86pinsrb : SDNode<"X86ISD::PINSRB", + SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, + SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; +def X86pinsrw : SDNode<"X86ISD::PINSRW", + SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, + SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; +def X86insertps : SDNode<"X86ISD::INSERTPS", + SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, + SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>; +def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", + SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; + +def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; + +def X86vzext : SDNode<"X86ISD::VZEXT", + SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisInt<0>, SDTCisInt<1>, + SDTCisOpSmallerThanOp<1, 0>]>>; + +def X86vsext : SDNode<"X86ISD::VSEXT", + SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisInt<0>, SDTCisInt<1>, + SDTCisOpSmallerThanOp<1, 0>]>>; + +def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisInt<0>, SDTCisInt<1>, + SDTCisOpSmallerThanOp<0, 1>]>; + +def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>; +def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>; +def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>; + +def X86vfpext : SDNode<"X86ISD::VFPEXT", + SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>, + SDTCVecEltisVT<1, f32>, + SDTCisSameSizeAs<0, 1>]>>; +def X86vfpround: SDNode<"X86ISD::VFPROUND", + SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, + SDTCVecEltisVT<1, f64>, + SDTCisSameSizeAs<0, 1>]>>; + +def X86froundRnd: SDNode<"X86ISD::VFPROUNDS_RND", + SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, + SDTCisSameAs<0, 1>, + SDTCVecEltisVT<2, f64>, + SDTCisSameSizeAs<0, 2>, + SDTCisVT<3, i32>]>>; + +def X86fpextRnd : SDNode<"X86ISD::VFPEXTS_RND", + SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f64>, + SDTCisSameAs<0, 1>, + SDTCVecEltisVT<2, f32>, + SDTCisSameSizeAs<0, 2>, + SDTCisVT<3, i32>]>>; + +def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisVT<2, i8>, SDTCisInt<0>]>; + +def X86vshldq : SDNode<"X86ISD::VSHLDQ", X86vshiftimm>; +def X86vshrdq : SDNode<"X86ISD::VSRLDQ", X86vshiftimm>; +def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>; +def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>; +def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>; + +def X86CmpMaskCC : + SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>, + SDTCisVec<1>, SDTCisSameAs<2, 1>, + SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>; +def X86CmpMaskCCRound : + SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>, + SDTCisVec<1>, SDTCisFP<1>, SDTCisSameAs<2, 1>, + SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>, + SDTCisVT<4, i32>]>; +def X86CmpMaskCCScalar : + SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>, + SDTCisVT<3, i8>]>; + +def X86CmpMaskCCScalarRound : + SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>, + SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; + +def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>; +// Hack to make CMPM commutable in tablegen patterns for load folding. +def X86cmpm_c : SDNode<"X86ISD::CMPM", X86CmpMaskCC, [SDNPCommutative]>; +def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>; +def X86cmpms : SDNode<"X86ISD::FSETCCM", X86CmpMaskCCScalar>; +def X86cmpmsRnd : SDNode<"X86ISD::FSETCCM_RND", X86CmpMaskCCScalarRound>; + +def X86phminpos: SDNode<"X86ISD::PHMINPOS", + SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>; + +def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisVec<2>, SDTCisInt<0>, + SDTCisInt<1>]>; + +def X86vshl : SDNode<"X86ISD::VSHL", X86vshiftuniform>; +def X86vsrl : SDNode<"X86ISD::VSRL", X86vshiftuniform>; +def X86vsra : SDNode<"X86ISD::VSRA", X86vshiftuniform>; + +def X86vshiftvariable : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, SDTCisInt<0>]>; + +def X86vsrav : SDNode<"X86ISD::VSRAV", X86vshiftvariable>; + +def X86vshli : SDNode<"X86ISD::VSHLI", X86vshiftimm>; +def X86vsrli : SDNode<"X86ISD::VSRLI", X86vshiftimm>; +def X86vsrai : SDNode<"X86ISD::VSRAI", X86vshiftimm>; + +def X86kshiftl : SDNode<"X86ISD::KSHIFTL", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, + SDTCisSameAs<0, 1>, + SDTCisVT<2, i8>]>>; +def X86kshiftr : SDNode<"X86ISD::KSHIFTR", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, + SDTCisSameAs<0, 1>, + SDTCisVT<2, i8>]>>; + +def X86kadd : SDNode<"X86ISD::KADD", SDTIntBinOp, [SDNPCommutative]>; + +def X86vrotli : SDNode<"X86ISD::VROTLI", X86vshiftimm>; +def X86vrotri : SDNode<"X86ISD::VROTRI", X86vshiftimm>; + +def X86vpshl : SDNode<"X86ISD::VPSHL", X86vshiftvariable>; +def X86vpsha : SDNode<"X86ISD::VPSHA", X86vshiftvariable>; + +def X86vpcom : SDNode<"X86ISD::VPCOM", + SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisVT<3, i8>, SDTCisInt<0>]>>; +def X86vpcomu : SDNode<"X86ISD::VPCOMU", + SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisVT<3, i8>, SDTCisInt<0>]>>; +def X86vpermil2 : SDNode<"X86ISD::VPERMIL2", + SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisFP<0>, SDTCisInt<3>, + SDTCisSameNumEltsAs<0, 3>, + SDTCisSameSizeAs<0,3>, + SDTCisVT<4, i8>]>>; +def X86vpperm : SDNode<"X86ISD::VPPERM", + SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, SDTCisSameAs<0, 3>]>>; + +def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, + SDTCisVec<1>, + SDTCisSameAs<2, 1>]>; + +def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp, [SDNPCommutative]>; +def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>; +def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp, [SDNPCommutative]>; +def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>; +def X86mulhrs : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>; +def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>; +def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; +def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>; +def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>; +def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>; + +def X86movmsk : SDNode<"X86ISD::MOVMSK", + SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>; + +def X86selects : SDNode<"X86ISD::SELECTS", + SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<2, 3>]>>; + +def X86pmuludq : SDNode<"X86ISD::PMULUDQ", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, + SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>]>, + [SDNPCommutative]>; +def X86pmuldq : SDNode<"X86ISD::PMULDQ", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, + SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>]>, + [SDNPCommutative]>; + +def X86extrqi : SDNode<"X86ISD::EXTRQI", + SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, + SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>; +def X86insertqi : SDNode<"X86ISD::INSERTQI", + SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>, SDTCisVT<3, i8>, + SDTCisVT<4, i8>]>>; + +// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get +// translated into one of the target nodes below during lowering. +// Note: this is a work in progress... +def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; +def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>]>; +def SDTShuff2OpFP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, + SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>; + +def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisFP<0>, SDTCisInt<2>, + SDTCisSameNumEltsAs<0,2>, + SDTCisSameSizeAs<0,2>]>; +def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>, + SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>; +def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>; +def SDTFPBinOpImm: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, + SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisVT<3, i32>]>; +def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisVec<0>, + SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisVT<3, i32>, + SDTCisVT<4, i32>]>; +def SDTFPTernaryOpImmRound: SDTypeProfile<1, 5, [SDTCisFP<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisInt<3>, + SDTCisSameSizeAs<0, 3>, + SDTCisSameNumEltsAs<0, 3>, + SDTCisVT<4, i32>, + SDTCisVT<5, i32>]>; +def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisVec<0>, + SDTCisSameAs<0,1>, + SDTCisVT<2, i32>]>; +def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, + SDTCisSameAs<0,1>, + SDTCisVT<2, i32>, + SDTCisVT<3, i32>]>; + +def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>; +def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>, + SDTCisInt<0>, SDTCisInt<1>]>; + +def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>; + +def SDTTernlog : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisVec<0>, + SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, + SDTCisSameAs<0,3>, SDTCisVT<4, i8>]>; + +def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc. + SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>; + +def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc. + SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>; + +def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, + SDTCisFP<0>, SDTCisVT<4, i32>]>; + +def X86PAlignr : SDNode<"X86ISD::PALIGNR", + SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>, + SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisVT<3, i8>]>>; +def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>; + +def X86VShld : SDNode<"X86ISD::VSHLD", SDTShuff3OpI>; +def X86VShrd : SDNode<"X86ISD::VSHRD", SDTShuff3OpI>; +def X86VShldv : SDNode<"X86ISD::VSHLDV", + SDTypeProfile<1, 3, [SDTCisVec<0>, + SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisSameAs<0,3>]>>; +def X86VShrdv : SDNode<"X86ISD::VSHRDV", + SDTypeProfile<1, 3, [SDTCisVec<0>, + SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisSameAs<0,3>]>>; + +def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>; + +def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>; +def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>; +def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>; + +def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>; +def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>; + +def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>; +def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>; +def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>; + +def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2OpFP>; +def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2OpFP>; + +def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2OpFP>; +def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2OpFP>; + +def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>, + SDTCisVec<1>, SDTCisInt<1>, + SDTCisSameSizeAs<0,1>, + SDTCisSameAs<1,2>, + SDTCisOpSmallerThanOp<0, 1>]>; +def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>; +def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>; + +def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>; +def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>; + +def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, + SDTCVecEltisVT<1, i8>, + SDTCisSameSizeAs<0,1>, + SDTCisSameAs<1,2>]>>; +def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i32>, + SDTCVecEltisVT<1, i16>, + SDTCisSameSizeAs<0,1>, + SDTCisSameAs<1,2>]>, + [SDNPCommutative]>; + +def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>; +def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>; +def X86VPermv : SDNode<"X86ISD::VPERMV", + SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>, + SDTCisSameNumEltsAs<0,1>, + SDTCisSameSizeAs<0,1>, + SDTCisSameAs<0,2>]>>; +def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>; +def X86VPermt2 : SDNode<"X86ISD::VPERMV3", + SDTypeProfile<1, 3, [SDTCisVec<0>, + SDTCisSameAs<0,1>, SDTCisInt<2>, + SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>, + SDTCisSameSizeAs<0,2>, + SDTCisSameAs<0,3>]>, []>; + +def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>; + +def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>; + +def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImmRound>; +def X86VFixupimmScalar : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImmRound>; +def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImm>; +def X86VRangeRnd : SDNode<"X86ISD::VRANGE_RND", SDTFPBinOpImmRound>; +def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImm>; +def X86VReduceRnd : SDNode<"X86ISD::VREDUCE_RND", SDTFPUnaryOpImmRound>; +def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImm>; +def X86VRndScaleRnd: SDNode<"X86ISD::VRNDSCALE_RND", SDTFPUnaryOpImmRound>; +def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImm>; +def X86VGetMantRnd : SDNode<"X86ISD::VGETMANT_RND", SDTFPUnaryOpImmRound>; +def X86Vfpclass : SDNode<"X86ISD::VFPCLASS", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, + SDTCisFP<1>, + SDTCisSameNumEltsAs<0,1>, + SDTCisVT<2, i32>]>, []>; +def X86Vfpclasss : SDNode<"X86ISD::VFPCLASSS", + SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>, + SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>; + +def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST", + SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisSubVecOfVec<1, 0>]>, []>; + +def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>; +def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>; + +def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>; + +def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>; + +def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>; +def X86faddRnds : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>; +def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>; +def X86fsubRnds : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>; +def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>; +def X86fmulRnds : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>; +def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>; +def X86fdivRnds : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>; +def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>; +def X86fmaxRnds : SDNode<"X86ISD::FMAXS_RND", SDTFPBinOpRound>; +def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>; +def X86fminRnds : SDNode<"X86ISD::FMINS_RND", SDTFPBinOpRound>; +def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>; +def X86scalefs : SDNode<"X86ISD::SCALEFS", SDTFPBinOpRound>; +def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>; +def X86fsqrtRnds : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>; +def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>; +def X86fgetexpRnds : SDNode<"X86ISD::FGETEXPS_RND", SDTFPBinOpRound>; + +def X86Fmadd : SDNode<"ISD::FMA", SDTFPTernaryOp, [SDNPCommutative]>; +def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFPTernaryOp, [SDNPCommutative]>; +def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>; +def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFPTernaryOp, [SDNPCommutative]>; +def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFPTernaryOp, [SDNPCommutative]>; +def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFPTernaryOp, [SDNPCommutative]>; + +def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound, [SDNPCommutative]>; +def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound, [SDNPCommutative]>; +def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound, [SDNPCommutative]>; +def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound, [SDNPCommutative]>; +def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound, [SDNPCommutative]>; +def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound, [SDNPCommutative]>; + +def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; +def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>; +def x86vpmadd52h : SDNode<"X86ISD::VPMADD52H", SDTIFma, [SDNPCommutative]>; + +def X86rsqrt14 : SDNode<"X86ISD::RSQRT14", SDTFPUnaryOp>; +def X86rcp14 : SDNode<"X86ISD::RCP14", SDTFPUnaryOp>; + +// VNNI +def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; +def X86Vpdpbusd : SDNode<"X86ISD::VPDPBUSD", SDTVnni>; +def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>; +def X86Vpdpwssd : SDNode<"X86ISD::VPDPWSSD", SDTVnni>; +def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>; + +def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", SDTFPUnaryOpRound>; +def X86rcp28 : SDNode<"X86ISD::RCP28", SDTFPUnaryOpRound>; +def X86exp2 : SDNode<"X86ISD::EXP2", SDTFPUnaryOpRound>; + +def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>; +def X86rcp14s : SDNode<"X86ISD::RCP14S", SDTFPBinOp>; +def X86rsqrt28s : SDNode<"X86ISD::RSQRT28S", SDTFPBinOpRound>; +def X86rcp28s : SDNode<"X86ISD::RCP28S", SDTFPBinOpRound>; +def X86Ranges : SDNode<"X86ISD::VRANGES", SDTFPBinOpImm>; +def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImm>; +def X86Reduces : SDNode<"X86ISD::VREDUCES", SDTFPBinOpImm>; +def X86GetMants : SDNode<"X86ISD::VGETMANTS", SDTFPBinOpImm>; +def X86RangesRnd : SDNode<"X86ISD::VRANGES_RND", SDTFPBinOpImmRound>; +def X86RndScalesRnd : SDNode<"X86ISD::VRNDSCALES_RND", SDTFPBinOpImmRound>; +def X86ReducesRnd : SDNode<"X86ISD::VREDUCES_RND", SDTFPBinOpImmRound>; +def X86GetMantsRnd : SDNode<"X86ISD::VGETMANTS_RND", SDTFPBinOpImmRound>; + +def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1, + [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>; +def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1, + [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>; + +// vpshufbitqmb +def X86Vpshufbitqmb : SDNode<"X86ISD::VPSHUFBITQMB", + SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisSameAs<1,2>, + SDTCVecEltisVT<0,i1>, + SDTCisSameNumEltsAs<0,1>]>>; + +def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>, + SDTCisSameAs<0,1>, SDTCisInt<2>, + SDTCisVT<3, i32>]>; + +def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisInt<0>, SDTCisFP<1>]>; +def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisInt<0>, SDTCisFP<1>, + SDTCisVT<2, i32>]>; +def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>, + SDTCisVec<1>, SDTCisVT<2, i32>]>; + +def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisFP<0>, SDTCisInt<1>]>; +def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisFP<0>, SDTCisInt<1>, + SDTCisVT<2, i32>]>; + +// Scalar +def X86SintToFpRnd : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND", SDTintToFPRound>; +def X86UintToFpRnd : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND", SDTintToFPRound>; + +def X86cvtts2IntRnd : SDNode<"X86ISD::CVTTS2SI_RND", SDTSFloatToIntRnd>; +def X86cvtts2UIntRnd : SDNode<"X86ISD::CVTTS2UI_RND", SDTSFloatToIntRnd>; + +def X86cvts2si : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>; +def X86cvts2usi : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>; + +// Vector with rounding mode + +// cvtt fp-to-int staff +def X86cvttp2siRnd : SDNode<"X86ISD::CVTTP2SI_RND", SDTFloatToIntRnd>; +def X86cvttp2uiRnd : SDNode<"X86ISD::CVTTP2UI_RND", SDTFloatToIntRnd>; + +def X86VSintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTVintToFPRound>; +def X86VUintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTVintToFPRound>; + +// cvt fp-to-int staff +def X86cvtp2IntRnd : SDNode<"X86ISD::CVTP2SI_RND", SDTFloatToIntRnd>; +def X86cvtp2UIntRnd : SDNode<"X86ISD::CVTP2UI_RND", SDTFloatToIntRnd>; + +// Vector without rounding mode + +// cvtt fp-to-int staff +def X86cvttp2si : SDNode<"X86ISD::CVTTP2SI", SDTFloatToInt>; +def X86cvttp2ui : SDNode<"X86ISD::CVTTP2UI", SDTFloatToInt>; + +def X86VSintToFP : SDNode<"X86ISD::CVTSI2P", SDTVintToFP>; +def X86VUintToFP : SDNode<"X86ISD::CVTUI2P", SDTVintToFP>; + +// cvt int-to-fp staff +def X86cvtp2Int : SDNode<"X86ISD::CVTP2SI", SDTFloatToInt>; +def X86cvtp2UInt : SDNode<"X86ISD::CVTP2UI", SDTFloatToInt>; + + +def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS", + SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, + SDTCVecEltisVT<1, i16>]> >; + +def X86cvtph2psRnd : SDNode<"X86ISD::CVTPH2PS_RND", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, + SDTCVecEltisVT<1, i16>, + SDTCisVT<2, i32>]> >; + +def X86cvtps2ph : SDNode<"X86ISD::CVTPS2PH", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, + SDTCVecEltisVT<1, f32>, + SDTCisVT<2, i32>]> >; +def X86vfpextRnd : SDNode<"X86ISD::VFPEXT_RND", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>, + SDTCVecEltisVT<1, f32>, + SDTCisOpSmallerThanOp<1, 0>, + SDTCisVT<2, i32>]>>; +def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, + SDTCVecEltisVT<1, f64>, + SDTCisOpSmallerThanOp<0, 1>, + SDTCisVT<2, i32>]>>; + +// galois field arithmetic +def X86GF2P8affineinvqb : SDNode<"X86ISD::GF2P8AFFINEINVQB", SDTBlend>; +def X86GF2P8affineqb : SDNode<"X86ISD::GF2P8AFFINEQB", SDTBlend>; +def X86GF2P8mulb : SDNode<"X86ISD::GF2P8MULB", SDTIntBinOp>; + +//===----------------------------------------------------------------------===// +// SSE Complex Patterns +//===----------------------------------------------------------------------===// + +// These are 'extloads' from a scalar to the low element of a vector, zeroing +// the top elements. These are used for the SSE 'ss' and 'sd' instruction +// forms. +def sse_load_f32 : ComplexPattern; +def sse_load_f64 : ComplexPattern; + +def ssmem : Operand { + let PrintMethod = "printf32mem"; + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); + let ParserMatchClass = X86Mem32AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} +def sdmem : Operand { + let PrintMethod = "printf64mem"; + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); + let ParserMatchClass = X86Mem64AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +//===----------------------------------------------------------------------===// +// SSE pattern fragments +//===----------------------------------------------------------------------===// + +// Vector load wrappers to prevent folding of non-temporal aligned loads on +// supporting targets. +def vecload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return !useNonTemporalLoad(cast(N)); +}]>; + +// 128-bit load pattern fragments +// NOTE: all 128-bit integer vector loads are promoted to v2i64 +def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (vecload node:$ptr))>; +def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (vecload node:$ptr))>; +def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (vecload node:$ptr))>; + +// 256-bit load pattern fragments +// NOTE: all 256-bit integer vector loads are promoted to v4i64 +def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (vecload node:$ptr))>; +def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (vecload node:$ptr))>; +def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (vecload node:$ptr))>; + +// 512-bit load pattern fragments +def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (vecload node:$ptr))>; +def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (vecload node:$ptr))>; +def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (vecload node:$ptr))>; + +// 128-/256-/512-bit extload pattern fragments +def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>; +def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>; +def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>; + +// Like 'store', but always requires vector size alignment. +def alignedstore : PatFrag<(ops node:$val, node:$ptr), + (store node:$val, node:$ptr), [{ + auto *St = cast(N); + return St->getAlignment() >= St->getMemoryVT().getStoreSize(); +}]>; + +// Like 'load', but always requires 128-bit vector alignment. +def alignedvecload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + auto *Ld = cast(N); + return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize() && + !useNonTemporalLoad(cast(N)); +}]>; + +// 128-bit aligned load pattern fragments +// NOTE: all 128-bit integer vector loads are promoted to v2i64 +def alignedloadv4f32 : PatFrag<(ops node:$ptr), + (v4f32 (alignedvecload node:$ptr))>; +def alignedloadv2f64 : PatFrag<(ops node:$ptr), + (v2f64 (alignedvecload node:$ptr))>; +def alignedloadv2i64 : PatFrag<(ops node:$ptr), + (v2i64 (alignedvecload node:$ptr))>; + +// 256-bit aligned load pattern fragments +// NOTE: all 256-bit integer vector loads are promoted to v4i64 +def alignedloadv8f32 : PatFrag<(ops node:$ptr), + (v8f32 (alignedvecload node:$ptr))>; +def alignedloadv4f64 : PatFrag<(ops node:$ptr), + (v4f64 (alignedvecload node:$ptr))>; +def alignedloadv4i64 : PatFrag<(ops node:$ptr), + (v4i64 (alignedvecload node:$ptr))>; + +// 512-bit aligned load pattern fragments +def alignedloadv16f32 : PatFrag<(ops node:$ptr), + (v16f32 (alignedvecload node:$ptr))>; +def alignedloadv8f64 : PatFrag<(ops node:$ptr), + (v8f64 (alignedvecload node:$ptr))>; +def alignedloadv8i64 : PatFrag<(ops node:$ptr), + (v8i64 (alignedvecload node:$ptr))>; + +// Like 'vecload', but uses special alignment checks suitable for use in +// memory operands in most SSE instructions, which are required to +// be naturally aligned on some targets but not on others. If the subtarget +// allows unaligned accesses, match any load, though this may require +// setting a feature bit in the processor (on startup, for example). +// Opteron 10h and later implement such a feature. +def memop : PatFrag<(ops node:$ptr), (vecload node:$ptr), [{ + auto *Ld = cast(N); + return Subtarget->hasSSEUnalignedMem() || + Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); +}]>; + +// 128-bit memop pattern fragments +// NOTE: all 128-bit integer vector loads are promoted to v2i64 +def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; +def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; +def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; + +def X86masked_gather : SDNode<"X86ISD::MGATHER", + SDTypeProfile<2, 3, [SDTCisVec<0>, + SDTCisVec<1>, SDTCisInt<1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<1, 3>, + SDTCisPtrTy<4>]>, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; + +def X86masked_scatter : SDNode<"X86ISD::MSCATTER", + SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisSameAs<0, 2>, + SDTCVecEltisVT<0, i1>, + SDTCisPtrTy<3>]>, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ + X86MaskedGatherSDNode *Mgt = cast(N); + return Mgt->getIndex().getValueType() == MVT::v4i32; +}]>; + +def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ + X86MaskedGatherSDNode *Mgt = cast(N); + return Mgt->getIndex().getValueType() == MVT::v8i32; +}]>; + +def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ + X86MaskedGatherSDNode *Mgt = cast(N); + return Mgt->getIndex().getValueType() == MVT::v2i64; +}]>; +def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ + X86MaskedGatherSDNode *Mgt = cast(N); + return Mgt->getIndex().getValueType() == MVT::v4i64; +}]>; +def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ + X86MaskedGatherSDNode *Mgt = cast(N); + return Mgt->getIndex().getValueType() == MVT::v8i64; +}]>; +def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ + X86MaskedGatherSDNode *Mgt = cast(N); + return Mgt->getIndex().getValueType() == MVT::v16i32; +}]>; + +def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ + X86MaskedScatterSDNode *Sc = cast(N); + return Sc->getIndex().getValueType() == MVT::v2i64; +}]>; + +def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ + X86MaskedScatterSDNode *Sc = cast(N); + return Sc->getIndex().getValueType() == MVT::v4i32; +}]>; + +def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ + X86MaskedScatterSDNode *Sc = cast(N); + return Sc->getIndex().getValueType() == MVT::v4i64; +}]>; + +def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ + X86MaskedScatterSDNode *Sc = cast(N); + return Sc->getIndex().getValueType() == MVT::v8i32; +}]>; + +def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ + X86MaskedScatterSDNode *Sc = cast(N); + return Sc->getIndex().getValueType() == MVT::v8i64; +}]>; +def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ + X86MaskedScatterSDNode *Sc = cast(N); + return Sc->getIndex().getValueType() == MVT::v16i32; +}]>; + +// 128-bit bitconvert pattern fragments +def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; +def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; +def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; +def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; +def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; +def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; + +// 256-bit bitconvert pattern fragments +def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>; +def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>; +def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>; +def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>; +def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>; +def bc_v4f64 : PatFrag<(ops node:$in), (v4f64 (bitconvert node:$in))>; + +// 512-bit bitconvert pattern fragments +def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>; +def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>; +def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>; +def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>; +def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>; + +def vzmovl_v2i64 : PatFrag<(ops node:$src), + (bitconvert (v2i64 (X86vzmovl + (v2i64 (scalar_to_vector (loadi64 node:$src))))))>; +def vzmovl_v4i32 : PatFrag<(ops node:$src), + (bitconvert (v4i32 (X86vzmovl + (v4i32 (scalar_to_vector (loadi32 node:$src))))))>; + +def vzload_v2i64 : PatFrag<(ops node:$src), + (bitconvert (v2i64 (X86vzload node:$src)))>; + + +def fp32imm0 : PatLeaf<(f32 fpimm), [{ + return N->isExactlyValue(+0.0); +}]>; + +def fp64imm0 : PatLeaf<(f64 fpimm), [{ + return N->isExactlyValue(+0.0); +}]>; + +def I8Imm : SDNodeXFormgetZExtValue(), SDLoc(N)); +}]>; + +def FROUND_NO_EXC : PatLeaf<(i32 8)>; +def FROUND_CURRENT : PatLeaf<(i32 4)>; + +// BYTE_imm - Transform bit immediates into byte immediates. +def BYTE_imm : SDNodeXForm> 3 + return getI32Imm(N->getZExtValue() >> 3, SDLoc(N)); +}]>; + +// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index +// to VEXTRACTF128/VEXTRACTI128 imm. +def EXTRACT_get_vextract128_imm : SDNodeXForm; + +// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to +// VINSERTF128/VINSERTI128 imm. +def INSERT_get_vinsert128_imm : SDNodeXForm; + +// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index +// to VEXTRACTF64x4 imm. +def EXTRACT_get_vextract256_imm : SDNodeXForm; + +// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to +// VINSERTF64x4 imm. +def INSERT_get_vinsert256_imm : SDNodeXForm; + +def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index), + (extract_subvector node:$bigvec, + node:$index), [{}], + EXTRACT_get_vextract128_imm>; + +def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec, + node:$index), + (insert_subvector node:$bigvec, node:$smallvec, + node:$index), [{}], + INSERT_get_vinsert128_imm>; + +def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index), + (extract_subvector node:$bigvec, + node:$index), [{}], + EXTRACT_get_vextract256_imm>; + +def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec, + node:$index), + (insert_subvector node:$bigvec, node:$smallvec, + node:$index), [{}], + INSERT_get_vinsert256_imm>; + +def X86mload : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_load node:$src1, node:$src2, node:$src3), [{ + return !cast(N)->isExpandingLoad() && + cast(N)->getExtensionType() == ISD::NON_EXTLOAD; +}]>; + +def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mload node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getAlignment() >= 16; +}]>; + +def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mload node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getAlignment() >= 32; +}]>; + +def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mload node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getAlignment() >= 64; +}]>; + +def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_load node:$src1, node:$src2, node:$src3), [{ + return !cast(N)->isExpandingLoad() && + cast(N)->getExtensionType() == ISD::NON_EXTLOAD; +}]>; + +def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_load node:$src1, node:$src2, node:$src3), [{ + return cast(N)->isExpandingLoad(); +}]>; + +// Masked store fragments. +// X86mstore can't be implemented in core DAG files because some targets +// do not support vector types (llvm-tblgen will fail). +def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_store node:$src1, node:$src2, node:$src3), [{ + return (!cast(N)->isTruncatingStore()) && + (!cast(N)->isCompressingStore()); +}]>; + +def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mstore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getAlignment() >= 16; +}]>; + +def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mstore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getAlignment() >= 32; +}]>; + +def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mstore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getAlignment() >= 64; +}]>; + +def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_store node:$src1, node:$src2, node:$src3), [{ + return (!cast(N)->isTruncatingStore()) && + (!cast(N)->isCompressingStore()); +}]>; + +def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_store node:$src1, node:$src2, node:$src3), [{ + return cast(N)->isCompressingStore(); +}]>; + +// masked truncstore fragments +// X86mtruncstore can't be implemented in core DAG files because some targets +// doesn't support vector type ( llvm-tblgen will fail) +def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_store node:$src1, node:$src2, node:$src3), [{ + return cast(N)->isTruncatingStore(); +}]>; +def masked_truncstorevi8 : + PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i8; +}]>; +def masked_truncstorevi16 : + PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i16; +}]>; +def masked_truncstorevi32 : + PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i32; +}]>; + +def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES", SDTStore, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS", SDTStore, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES", SDTMaskedStore, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS", SDTMaskedStore, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr), + (X86TruncSStore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i8; +}]>; + +def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr), + (X86TruncUSStore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i8; +}]>; + +def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr), + (X86TruncSStore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i16; +}]>; + +def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr), + (X86TruncUSStore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i16; +}]>; + +def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr), + (X86TruncSStore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i32; +}]>; + +def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr), + (X86TruncUSStore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i32; +}]>; + +def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i8; +}]>; + +def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i8; +}]>; + +def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i16; +}]>; + +def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i16; +}]>; + +def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i32; +}]>; + +def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i32; +}]>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrInfo.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrInfo.td new file mode 100644 index 0000000..56927c8 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrInfo.td @@ -0,0 +1,3582 @@ +//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 instruction set, defining the instructions, and +// properties of the instructions which are needed for code generation, machine +// code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// X86 specific DAG Nodes. +// + +def SDTIntShiftDOp: SDTypeProfile<1, 3, + [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, + SDTCisInt<0>, SDTCisInt<3>]>; + +def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; + +def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; +//def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; + +def SDTX86Cmov : SDTypeProfile<1, 4, + [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, + SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; + +// Unary and binary operator instructions that set EFLAGS as a side-effect. +def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, + [SDTCisSameAs<0, 2>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; + +def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, + [SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; + +// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS +def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, + [SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, + SDTCisVT<1, i32>, + SDTCisVT<4, i32>]>; +// RES1, RES2, FLAGS = op LHS, RHS +def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, + [SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; +def SDTX86BrCond : SDTypeProfile<0, 3, + [SDTCisVT<0, OtherVT>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; + +def SDTX86SetCC : SDTypeProfile<1, 2, + [SDTCisVT<0, i8>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; +def SDTX86SetCC_C : SDTypeProfile<1, 2, + [SDTCisInt<0>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; + +def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; + +def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; + +def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, + SDTCisVT<2, i8>]>; +def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; +def SDTX86caspairSaveEbx8 : SDTypeProfile<1, 3, + [SDTCisVT<0, i32>, SDTCisPtrTy<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; +def SDTX86caspairSaveRbx16 : SDTypeProfile<1, 3, + [SDTCisVT<0, i64>, SDTCisPtrTy<1>, + SDTCisVT<2, i64>, SDTCisVT<3, i64>]>; + +def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, + SDTCisPtrTy<1>, + SDTCisInt<2>]>; + +def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, + SDTCisPtrTy<1>]>; + +def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; + +def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; +def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; + +def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, + SDTCisVT<1, iPTR>, + SDTCisVT<2, iPTR>]>; + +def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, + SDTCisPtrTy<1>, + SDTCisVT<2, i32>, + SDTCisVT<3, i8>, + SDTCisVT<4, i32>]>; + +def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; + +def SDTX86Void : SDTypeProfile<0, 0, []>; + +def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; + +def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86WIN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; + +def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; + +def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; + +def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, + [SDNPHasChain,SDNPSideEffect]>; +def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, + [SDNPHasChain]>; + + +def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; +def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; +def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; +def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; + +def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; +def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; + +def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; +def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, + [SDNPHasChain]>; +def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; +def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; + +def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; + +def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, + [SDNPHasChain, SDNPSideEffect]>; + +def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, + [SDNPHasChain, SDNPSideEffect]>; + +def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas8save_ebx : SDNode<"X86ISD::LCMPXCHG8_SAVE_EBX_DAG", + SDTX86caspairSaveEbx8, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, + SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; +def X86cas16save_rbx : SDNode<"X86ISD::LCMPXCHG16_SAVE_RBX_DAG", + SDTX86caspairSaveRbx16, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, + SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; + +def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; +def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, + [SDNPHasChain, SDNPOptInGlue]>; + +def X86vastart_save_xmm_regs : + SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", + SDT_X86VASTART_SAVE_XMM_REGS, + [SDNPHasChain, SDNPVariadic]>; +def X86vaarg64 : + SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, + SDNPMemOperand]>; +def X86callseq_start : + SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, + [SDNPHasChain, SDNPOutGlue]>; +def X86callseq_end : + SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, + SDNPVariadic]>; + +def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, + SDNPVariadic]>; +def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind, + [SDNPHasChain]>; + +def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; +def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad]>; + +def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; +def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; +def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; + +def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; +def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; + +def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", + SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, + SDTCisInt<1>]>>; + +def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, + [SDNPHasChain]>; + +def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", + SDTypeProfile<1, 1, [SDTCisInt<0>, + SDTCisPtrTy<1>]>, + [SDNPHasChain, SDNPSideEffect]>; +def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", + SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, + [SDNPHasChain, SDNPSideEffect]>; +def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH", + SDTypeProfile<0, 0, []>, + [SDNPHasChain, SDNPSideEffect]>; + +def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; + +def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; +def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, + [SDNPCommutative]>; +def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; +def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; + +def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; +def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; +def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, + [SDNPCommutative]>; + +def X86lock_add : SDNode<"X86ISD::LADD", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_sub : SDNode<"X86ISD::LSUB", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_or : SDNode<"X86ISD::LOR", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; + +def X86lock_inc : SDNode<"X86ISD::LINC", SDTLockUnaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_dec : SDNode<"X86ISD::LDEC", SDTLockUnaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; + +def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; + +def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; + +def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDT_X86WIN_ALLOCA, + [SDNPHasChain, SDNPOutGlue]>; + +def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, + [SDNPHasChain]>; + +def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86lwpins : SDNode<"X86ISD::LWPINS", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; + +def X86umwait : SDNode<"X86ISD::UMWAIT", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +def X86tpause : SDNode<"X86ISD::TPAUSE", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +//===----------------------------------------------------------------------===// +// X86 Operand Definitions. +// + +// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for +// the index operand of an address, to conform to x86 encoding restrictions. +def ptr_rc_nosp : PointerLikeRegClass<1>; + +// *mem - Operand definitions for the funky X86 addressing mode operands. +// +def X86MemAsmOperand : AsmOperandClass { + let Name = "Mem"; +} +let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in { + def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } + def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } + def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } + def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } + def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } + def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } + def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } + def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } + // Gather mem operands + def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; } + def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; } + def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; } + def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; } + def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; } + + def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; } + def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; } + def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; } + def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; } + def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; } + def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; } + def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; } + def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; } +} + +def X86AbsMemAsmOperand : AsmOperandClass { + let Name = "AbsMem"; + let SuperClasses = [X86MemAsmOperand]; +} + +class X86MemOperand : Operand { + let PrintMethod = printMethod; + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); + let ParserMatchClass = parserMatchClass; + let OperandType = "OPERAND_MEMORY"; +} + +// Gather mem operands +class X86VMemOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG); +} + +def anymem : X86MemOperand<"printanymem">; + +// FIXME: Right now we allow any size during parsing, but we might want to +// restrict to only unsized memory. +def opaquemem : X86MemOperand<"printopaquemem">; + +def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>; +def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>; +def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>; +def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>; +def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>; +def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>; +def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>; +def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>; +def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>; +def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>; +def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>; +def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>; +def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>; + +def v512mem : X86VMemOperand; + +// Gather mem operands +def vx64mem : X86VMemOperand; +def vx128mem : X86VMemOperand; +def vx256mem : X86VMemOperand; +def vy128mem : X86VMemOperand; +def vy256mem : X86VMemOperand; + +def vx64xmem : X86VMemOperand; +def vx128xmem : X86VMemOperand; +def vx256xmem : X86VMemOperand; +def vy128xmem : X86VMemOperand; +def vy256xmem : X86VMemOperand; +def vy512xmem : X86VMemOperand; +def vz256mem : X86VMemOperand; +def vz512mem : X86VMemOperand; + +// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead +// of a plain GPR, so that it doesn't potentially require a REX prefix. +def ptr_rc_norex : PointerLikeRegClass<2>; +def ptr_rc_norex_nosp : PointerLikeRegClass<3>; + +def i8mem_NOREX : Operand { + let PrintMethod = "printi8mem"; + let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, + SEGMENT_REG); + let ParserMatchClass = X86Mem8AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +// GPRs available for tailcall. +// It represents GR32_TC, GR64_TC or GR64_TCW64. +def ptr_rc_tailcall : PointerLikeRegClass<4>; + +// Special i32mem for addresses of load folding tail calls. These are not +// allowed to use callee-saved registers since they must be scheduled +// after callee-saved register are popped. +def i32mem_TC : Operand { + let PrintMethod = "printi32mem"; + let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, + i32imm, SEGMENT_REG); + let ParserMatchClass = X86Mem32AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +// Special i64mem for addresses of load folding tail calls. These are not +// allowed to use callee-saved registers since they must be scheduled +// after callee-saved register are popped. +def i64mem_TC : Operand { + let PrintMethod = "printi64mem"; + let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, + ptr_rc_tailcall, i32imm, SEGMENT_REG); + let ParserMatchClass = X86Mem64AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +let OperandType = "OPERAND_PCREL", + ParserMatchClass = X86AbsMemAsmOperand, + PrintMethod = "printPCRelImm" in { +def i32imm_pcrel : Operand; +def i16imm_pcrel : Operand; + +// Branch targets have OtherVT type and print as pc-relative values. +def brtarget : Operand; +def brtarget8 : Operand; + +} + +// Special parser to detect 16-bit mode to select 16-bit displacement. +def X86AbsMem16AsmOperand : AsmOperandClass { + let Name = "AbsMem16"; + let RenderMethod = "addAbsMemOperands"; + let SuperClasses = [X86AbsMemAsmOperand]; +} + +// Branch targets have OtherVT type and print as pc-relative values. +let OperandType = "OPERAND_PCREL", + PrintMethod = "printPCRelImm" in { +let ParserMatchClass = X86AbsMem16AsmOperand in + def brtarget16 : Operand; +let ParserMatchClass = X86AbsMemAsmOperand in + def brtarget32 : Operand; +} + +let RenderMethod = "addSrcIdxOperands" in { + def X86SrcIdx8Operand : AsmOperandClass { + let Name = "SrcIdx8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86SrcIdx16Operand : AsmOperandClass { + let Name = "SrcIdx16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86SrcIdx32Operand : AsmOperandClass { + let Name = "SrcIdx32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86SrcIdx64Operand : AsmOperandClass { + let Name = "SrcIdx64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addSrcIdxOperands" + +let RenderMethod = "addDstIdxOperands" in { + def X86DstIdx8Operand : AsmOperandClass { + let Name = "DstIdx8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86DstIdx16Operand : AsmOperandClass { + let Name = "DstIdx16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86DstIdx32Operand : AsmOperandClass { + let Name = "DstIdx32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86DstIdx64Operand : AsmOperandClass { + let Name = "DstIdx64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addDstIdxOperands" + +let RenderMethod = "addMemOffsOperands" in { + def X86MemOffs16_8AsmOperand : AsmOperandClass { + let Name = "MemOffs16_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs16_16AsmOperand : AsmOperandClass { + let Name = "MemOffs16_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs16_32AsmOperand : AsmOperandClass { + let Name = "MemOffs16_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs32_8AsmOperand : AsmOperandClass { + let Name = "MemOffs32_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs32_16AsmOperand : AsmOperandClass { + let Name = "MemOffs32_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs32_32AsmOperand : AsmOperandClass { + let Name = "MemOffs32_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs32_64AsmOperand : AsmOperandClass { + let Name = "MemOffs32_64"; + let SuperClasses = [X86Mem64AsmOperand]; + } + def X86MemOffs64_8AsmOperand : AsmOperandClass { + let Name = "MemOffs64_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs64_16AsmOperand : AsmOperandClass { + let Name = "MemOffs64_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs64_32AsmOperand : AsmOperandClass { + let Name = "MemOffs64_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs64_64AsmOperand : AsmOperandClass { + let Name = "MemOffs64_64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addMemOffsOperands" + +class X86SrcIdxOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc, SEGMENT_REG); +} + +class X86DstIdxOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc); +} + +def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; +def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; +def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; +def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; +def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; +def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; +def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; +def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; + +class X86MemOffsOperand + : X86MemOperand { + let MIOperandInfo = (ops immOperand, SEGMENT_REG); +} + +def offset16_8 : X86MemOffsOperand; +def offset16_16 : X86MemOffsOperand; +def offset16_32 : X86MemOffsOperand; +def offset32_8 : X86MemOffsOperand; +def offset32_16 : X86MemOffsOperand; +def offset32_32 : X86MemOffsOperand; +def offset32_64 : X86MemOffsOperand; +def offset64_8 : X86MemOffsOperand; +def offset64_16 : X86MemOffsOperand; +def offset64_32 : X86MemOffsOperand; +def offset64_64 : X86MemOffsOperand; + +def SSECC : Operand { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def AVXCC : Operand { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def AVX512ICC : Operand { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def XOPCC : Operand { + let PrintMethod = "printXOPCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +class ImmSExtAsmOperandClass : AsmOperandClass { + let SuperClasses = [ImmAsmOperand]; + let RenderMethod = "addImmOperands"; +} + +def X86GR32orGR64AsmOperand : AsmOperandClass { + let Name = "GR32orGR64"; +} + +def GR32orGR64 : RegisterOperand { + let ParserMatchClass = X86GR32orGR64AsmOperand; +} +def AVX512RCOperand : AsmOperandClass { + let Name = "AVX512RC"; +} +def AVX512RC : Operand { + let PrintMethod = "printRoundingControl"; + let OperandType = "OPERAND_IMMEDIATE"; + let ParserMatchClass = AVX512RCOperand; +} + +// Sign-extended immediate classes. We don't need to define the full lattice +// here because there is no instruction with an ambiguity between ImmSExti64i32 +// and ImmSExti32i8. +// +// The strange ranges come from the fact that the assembler always works with +// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" +// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). + +// [0, 0x7FFFFFFF] | +// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] +def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti64i32"; +} + +// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti16i8"; + let SuperClasses = [ImmSExti64i32AsmOperand]; +} + +// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti32i8"; +} + +// [0, 0x0000007F] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti64i8"; + let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, + ImmSExti64i32AsmOperand]; +} + +// Unsigned immediate used by SSE/AVX instructions +// [0, 0xFF] +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmUnsignedi8AsmOperand : AsmOperandClass { + let Name = "ImmUnsignedi8"; + let RenderMethod = "addImmOperands"; +} + +// A couple of more descriptive operand definitions. +// 16-bits but only 8 bits are significant. +def i16i8imm : Operand { + let ParserMatchClass = ImmSExti16i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} +// 32-bits but only 8 bits are significant. +def i32i8imm : Operand { + let ParserMatchClass = ImmSExti32i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 32 bits are significant. +def i64i32imm : Operand { + let ParserMatchClass = ImmSExti64i32AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 8 bits are significant. +def i64i8imm : Operand { + let ParserMatchClass = ImmSExti64i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// Unsigned 8-bit immediate used by SSE/AVX instructions. +def u8imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 32-bit immediate but only 8-bits are significant and they are unsigned. +// Used by some SSE/AVX instructions that use intrinsics. +def i32u8imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 32 bits are significant, and those bits are treated as being +// pc relative. +def i64i32imm_pcrel : Operand { + let PrintMethod = "printPCRelImm"; + let ParserMatchClass = X86AbsMemAsmOperand; + let OperandType = "OPERAND_PCREL"; +} + +def lea64_32mem : Operand { + let PrintMethod = "printanymem"; + let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); + let ParserMatchClass = X86MemAsmOperand; +} + +// Memory operands that use 64-bit pointers in both ILP32 and LP64. +def lea64mem : Operand { + let PrintMethod = "printanymem"; + let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); + let ParserMatchClass = X86MemAsmOperand; +} + + +//===----------------------------------------------------------------------===// +// X86 Complex Pattern Definitions. +// + +// Define X86-specific addressing mode. +def addr : ComplexPattern; +def lea32addr : ComplexPattern; +// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. +def lea64_32addr : ComplexPattern; + +def tls32addr : ComplexPattern; + +def tls32baseaddr : ComplexPattern; + +def lea64addr : ComplexPattern; + +def tls64addr : ComplexPattern; + +def tls64baseaddr : ComplexPattern; + +def vectoraddr : ComplexPattern; + +// A relocatable immediate is either an immediate operand or an operand that can +// be relocated by the linker to an immediate, such as a regular symbol in +// non-PIC code. +def relocImm : ComplexPattern; + +//===----------------------------------------------------------------------===// +// X86 Instruction Predicate Definitions. +def TruePredicate : Predicate<"true">; + +def HasCMov : Predicate<"Subtarget->hasCMov()">; +def NoCMov : Predicate<"!Subtarget->hasCMov()">; + +def HasMMX : Predicate<"Subtarget->hasMMX()">; +def Has3DNow : Predicate<"Subtarget->has3DNow()">; +def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; +def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; +def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; +def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; +def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; +def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; +def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; +def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; +def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; +def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; +def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; +def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; +def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; +def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; +def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; +def NoAVX : Predicate<"!Subtarget->hasAVX()">; +def HasAVX : Predicate<"Subtarget->hasAVX()">; +def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; +def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; +def HasAVX512 : Predicate<"Subtarget->hasAVX512()">; +def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; +def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; +def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; +def HasCDI : Predicate<"Subtarget->hasCDI()">; +def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">; +def HasPFI : Predicate<"Subtarget->hasPFI()">; +def HasERI : Predicate<"Subtarget->hasERI()">; +def HasDQI : Predicate<"Subtarget->hasDQI()">; +def NoDQI : Predicate<"!Subtarget->hasDQI()">; +def HasBWI : Predicate<"Subtarget->hasBWI()">; +def NoBWI : Predicate<"!Subtarget->hasBWI()">; +def HasVLX : Predicate<"Subtarget->hasVLX()">; +def NoVLX : Predicate<"!Subtarget->hasVLX()">; +def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">; +def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">; +def PKU : Predicate<"Subtarget->hasPKU()">; +def HasVNNI : Predicate<"Subtarget->hasVNNI()">; + +def HasBITALG : Predicate<"Subtarget->hasBITALG()">; +def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; +def HasAES : Predicate<"Subtarget->hasAES()">; +def HasVAES : Predicate<"Subtarget->hasVAES()">; +def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">; +def HasFXSR : Predicate<"Subtarget->hasFXSR()">; +def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">; +def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">; +def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">; +def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">; +def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; +def NoVLX_Or_NoVPCLMULQDQ : + Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()">; +def HasVPCLMULQDQ : Predicate<"Subtarget->hasVPCLMULQDQ()">; +def HasGFNI : Predicate<"Subtarget->hasGFNI()">; +def HasFMA : Predicate<"Subtarget->hasFMA()">; +def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; +def NoFMA4 : Predicate<"!Subtarget->hasFMA4()">; +def HasXOP : Predicate<"Subtarget->hasXOP()">; +def HasTBM : Predicate<"Subtarget->hasTBM()">; +def NoTBM : Predicate<"!Subtarget->hasTBM()">; +def HasLWP : Predicate<"Subtarget->hasLWP()">; +def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; +def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; +def HasF16C : Predicate<"Subtarget->hasF16C()">; +def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; +def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; +def HasBMI : Predicate<"Subtarget->hasBMI()">; +def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; +def NoBMI2 : Predicate<"!Subtarget->hasBMI2()">; +def HasVBMI : Predicate<"Subtarget->hasVBMI()">; +def HasVBMI2 : Predicate<"Subtarget->hasVBMI2()">; +def HasIFMA : Predicate<"Subtarget->hasIFMA()">; +def HasRTM : Predicate<"Subtarget->hasRTM()">; +def HasADX : Predicate<"Subtarget->hasADX()">; +def HasSHA : Predicate<"Subtarget->hasSHA()">; +def HasSGX : Predicate<"Subtarget->hasSGX()">; +def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; +def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; +def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">; +def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">; +def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; +def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">; +def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">; +def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">; +def HasCLZERO : Predicate<"Subtarget->hasCLZERO()">; +def HasCLDEMOTE : Predicate<"Subtarget->hasCLDEMOTE()">; +def HasMOVDIRI : Predicate<"Subtarget->hasMOVDIRI()">; +def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">; +def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">; +def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; +def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; +def HasMPX : Predicate<"Subtarget->hasMPX()">; +def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; +def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; +def HasCLWB : Predicate<"Subtarget->hasCLWB()">; +def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">; +def HasRDPID : Predicate<"Subtarget->hasRDPID()">; +def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">; +def HasINVPCID : Predicate<"Subtarget->hasINVPCID()">; +def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; +def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">; +def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, + AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; +def In64BitMode : Predicate<"Subtarget->is64Bit()">, + AssemblerPredicate<"Mode64Bit", "64-bit mode">; +def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; +def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; +def In16BitMode : Predicate<"Subtarget->is16Bit()">, + AssemblerPredicate<"Mode16Bit", "16-bit mode">; +def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, + AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; +def In32BitMode : Predicate<"Subtarget->is32Bit()">, + AssemblerPredicate<"Mode32Bit", "32-bit mode">; +def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; +def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; +def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||" + "Subtarget->getFrameLowering()->hasFP(*MF)"> { + let RecomputePerFunction = 1; +} +def IsPS4 : Predicate<"Subtarget->isTargetPS4()">; +def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">; +def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; +def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; +def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; +def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; +def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" + "TM.getCodeModel() == CodeModel::Kernel">; +def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; + +// We could compute these on a per-module basis but doing so requires accessing +// the Function object through the Subtarget and objections were raised +// to that (see post-commit review comments for r301750). +let RecomputePerFunction = 1 in { + def OptForSize : Predicate<"MF->getFunction().optForSize()">; + def OptForMinSize : Predicate<"MF->getFunction().optForMinSize()">; + def OptForSpeed : Predicate<"!MF->getFunction().optForSize()">; + def UseIncDec : Predicate<"!Subtarget->slowIncDec() || " + "MF->getFunction().optForSize()">; + def NoSSE41_Or_OptForSize : Predicate<"MF->getFunction().optForSize() || " + "!Subtarget->hasSSE41()">; +} + +def CallImmAddr : Predicate<"Subtarget->isLegalToCallImmediateAddr()">; +def FavorMemIndirectCall : Predicate<"!Subtarget->slowTwoMemOps()">; +def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; +def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">; +def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">; +def HasERMSB : Predicate<"Subtarget->hasERMSB()">; +def HasMFence : Predicate<"Subtarget->hasMFence()">; +def UseRetpoline : Predicate<"Subtarget->useRetpoline()">; +def NotUseRetpoline : Predicate<"!Subtarget->useRetpoline()">; + +//===----------------------------------------------------------------------===// +// X86 Instruction Format Definitions. +// + +include "X86InstrFormats.td" + +//===----------------------------------------------------------------------===// +// Pattern fragments. +// + +// X86 specific condition code. These correspond to CondCode in +// X86InstrInfo.h. They must be kept in synch. +def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE +def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC +def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C +def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA +def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z +def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE +def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL +def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE +def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG +def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ +def X86_COND_NO : PatLeaf<(i8 10)>; +def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO +def X86_COND_NS : PatLeaf<(i8 12)>; +def X86_COND_O : PatLeaf<(i8 13)>; +def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE +def X86_COND_S : PatLeaf<(i8 15)>; + +def i16immSExt8 : ImmLeaf(Imm); }]>; +def i32immSExt8 : ImmLeaf(Imm); }]>; +def i64immSExt8 : ImmLeaf(Imm); }]>; +def i64immSExt32 : ImmLeaf(Imm); }]>; + +// FIXME: Ideally we would just replace the above i*immSExt* matchers with +// relocImm-based matchers, but then FastISel would be unable to use them. +def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{ + return isSExtRelocImm<8>(N); +}]>; +def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{ + return isSExtRelocImm<32>(N); +}]>; + +// If we have multiple users of an immediate, it's much smaller to reuse +// the register, rather than encode the immediate in every instruction. +// This has the risk of increasing register pressure from stretched live +// ranges, however, the immediates should be trivial to rematerialize by +// the RA in the event of high register pressure. +// TODO : This is currently enabled for stores and binary ops. There are more +// cases for which this can be enabled, though this catches the bulk of the +// issues. +// TODO2 : This should really also be enabled under O2, but there's currently +// an issue with RA where we don't pull the constants into their users +// when we rematerialize them. I'll follow-up on enabling O2 after we fix that +// issue. +// TODO3 : This is currently limited to single basic blocks (DAG creation +// pulls block immediates to the top and merges them if necessary). +// Eventually, it would be nice to allow ConstantHoisting to merge constants +// globally for potentially added savings. +// +def imm8_su : PatLeaf<(i8 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def imm16_su : PatLeaf<(i16 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def imm32_su : PatLeaf<(i32 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64immSExt32_su : PatLeaf<(i64immSExt32), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i32immSExt8_su : PatLeaf<(i32immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64immSExt8_su : PatLeaf<(i64immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit +// unsigned field. +def i64immZExt32 : ImmLeaf(Imm); }]>; + +def i64immZExt32SExt8 : ImmLeaf(Imm) && isInt<8>(static_cast(Imm)); +}]>; + +// Helper fragments for loads. + +// It's safe to fold a zextload/extload from i1 as a regular i8 load. The +// upper bits are guaranteed to be zero and we were going to emit a MOV8rm +// which might get folded during peephole anyway. +def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD || + ExtType == ISD::ZEXTLOAD; +}]>; + +// It's always safe to treat a anyext i16 load as a i32 load if the i16 is +// known to be 32-bit aligned or better. Ditto for i8 to i16. +def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + if (ExtType == ISD::NON_EXTLOAD) + return true; + if (ExtType == ISD::EXTLOAD) + return LD->getAlignment() >= 2 && !LD->isVolatile(); + return false; +}]>; + +def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + if (ExtType == ISD::NON_EXTLOAD) + return true; + if (ExtType == ISD::EXTLOAD) + return LD->getAlignment() >= 4 && !LD->isVolatile(); + return false; +}]>; + +def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; +def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; +def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; +def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; +def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>; +def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ + LoadSDNode *Ld = cast(N); + return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); +}]>; +def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ + LoadSDNode *Ld = cast(N); + return Subtarget->hasSSEUnalignedMem() || + Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); +}]>; + +def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; +def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; +def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; +def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; +def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; +def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; + +def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; +def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; +def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; +def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; +def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; +def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; +def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; +def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; +def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; +def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; + +def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; +def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; +def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; +def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; +def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; +def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; +def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; +def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; +def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; +def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; + + +// An 'and' node with a single use. +def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ + return N->hasOneUse(); +}]>; +// An 'srl' node with a single use. +def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ + return N->hasOneUse(); +}]>; +// An 'trunc' node with a single use. +def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ + return N->hasOneUse(); +}]>; + +//===----------------------------------------------------------------------===// +// Instruction list. +// + +// Nop +let hasSideEffects = 0, SchedRW = [WriteNop] in { + def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; + def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; + def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; + def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero), + "nop{q}\t$zero", []>, TB, NotMemoryFoldable, + Requires<[In64BitMode]>; + // Also allow register so we can assemble/disassemble + def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; + def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; + def NOOPQr : RI<0x1f, MRMXr, (outs), (ins GR64:$zero), + "nop{q}\t$zero", []>, TB, NotMemoryFoldable, + Requires<[In64BitMode]>; + def NOOPW_19 : I<0x19, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOPL_19 : I<0x19, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + //def NOOPW_1a : I<0x1a, MRMXm, (outs), (ins i16mem:$zero), + // "nop{w}\t$zero", []>, TB, OpSize16; + //def NOOPL_1a : I<0x1a, MRMXm, (outs), (ins i32mem:$zero), + // "nop{l}\t$zero", []>, TB, OpSize32; + //def NOOPW_1b : I<0x1b, MRMXm, (outs), (ins i16mem:$zero), + // "nop{w}\t$zero", []>, TB, OpSize16; + //def NOOPL_1b : I<0x1b, MRMXm, (outs), (ins i32mem:$zero), + // "nop{l}\t$zero", []>, TB, OpSize32; + def NOOPW_1c : I<0x1c, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + //def NOOPL_1c : I<0x1c, MRMXm, (outs), (ins i32mem:$zero), + // "nop{l}\t$zero", []>, TB, OpSize32; + def NOOPW_1d : I<0x1d, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOPL_1d : I<0x1d, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + def NOOPW_1e : I<0x1e, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOPL_1e : I<0x1e, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m4 : I<0x18, MRM4m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m4 : I<0x18, MRM4m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r4 : I<0x18, MRM4r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r4 : I<0x18, MRM4r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m5 : I<0x18, MRM5m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m5 : I<0x18, MRM5m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r5 : I<0x18, MRM5r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r5 : I<0x18, MRM5r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m6 : I<0x18, MRM6m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m6 : I<0x18, MRM6m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r6 : I<0x18, MRM6r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r6 : I<0x18, MRM6r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m7 : I<0x18, MRM7m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m7 : I<0x18, MRM7m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r7 : I<0x18, MRM7r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r7 : I<0x18, MRM7r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; +} + + +// Constructing a stack frame. +def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), + "enter\t$len, $lvl", []>, Sched<[WriteMicrocoded]>; + +let SchedRW = [WriteALU] in { +let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in +def LEAVE : I<0xC9, RawFrm, (outs), (ins), "leave", []>, + Requires<[Not64BitMode]>; + +let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in +def LEAVE64 : I<0xC9, RawFrm, (outs), (ins), "leave", []>, + Requires<[In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Miscellaneous Instructions. +// + +/* +let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1, + SchedRW = [WriteSystem] in + def Int_eh_sjlj_setup_dispatch + : PseudoI<(outs), (ins), [(X86eh_sjlj_setup_dispatch)]>; +*/ + +let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { +let mayLoad = 1, SchedRW = [WriteLoad] in { +def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, + OpSize16; +def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, + OpSize32, Requires<[Not64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, + OpSize16, NotMemoryFoldable; +def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, + OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 +} // mayLoad, SchedRW +let mayStore = 1, mayLoad = 1, SchedRW = [WriteRMW] in { +def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>, + OpSize16; +def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>, + OpSize32, Requires<[Not64BitMode]>; +} // mayStore, mayLoad, WriteRMW + +let mayStore = 1, SchedRW = [WriteStore] in { +def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, + OpSize16; +def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, + OpSize32, Requires<[Not64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, + OpSize16, NotMemoryFoldable; +def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, + OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 + +def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), + "push{w}\t$imm", []>, OpSize16; +def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), + "push{w}\t$imm", []>, OpSize16; + +def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), + "push{l}\t$imm", []>, OpSize32, + Requires<[Not64BitMode]>; +def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), + "push{l}\t$imm", []>, OpSize32, + Requires<[Not64BitMode]>; +} // mayStore, SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { +def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>, + OpSize16; +def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>, + OpSize32, Requires<[Not64BitMode]>; +} // mayLoad, mayStore, SchedRW + +} + +/* +let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, + SchedRW = [WriteRMW], Defs = [ESP] in { + let Uses = [ESP] in + def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins), + [(set GR32:$dst, (int_x86_flags_read_u32))]>, + Requires<[Not64BitMode]>; + + let Uses = [RSP] in + def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins), + [(set GR64:$dst, (int_x86_flags_read_u64))]>, + Requires<[In64BitMode]>; +} + +let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, + SchedRW = [WriteRMW] in { + let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in + def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src), + [(int_x86_flags_write_u32 GR32:$src)]>, + Requires<[Not64BitMode]>; + + let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in + def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src), + [(int_x86_flags_write_u64 GR64:$src)]>, + Requires<[In64BitMode]>; +} +*/ + +let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0, + SchedRW = [WriteLoad] in { +def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize16; +def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, OpSize32, + Requires<[Not64BitMode]>; +} + +let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0, + SchedRW = [WriteStore] in { +def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize16; +def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, OpSize32, + Requires<[Not64BitMode]>; +} + +let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { +let mayLoad = 1, SchedRW = [WriteLoad] in { +def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 +} // mayLoad, SchedRW +let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in +def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>, + OpSize32, Requires<[In64BitMode]>; +let mayStore = 1, SchedRW = [WriteStore] in { +def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 +} // mayStore, SchedRW +let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { +def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>, + OpSize32, Requires<[In64BitMode]>; +} // mayLoad, mayStore, SchedRW +} + +let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, + SchedRW = [WriteStore] in { +def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), + "push{q}\t$imm", []>, OpSize32, + Requires<[In64BitMode]>; +def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), + "push{q}\t$imm", []>, OpSize32, + Requires<[In64BitMode]>; +} + +let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in +def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, + OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; +let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in +def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, + OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; + +let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], + mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { +def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", []>, + OpSize32, Requires<[Not64BitMode]>; +def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", []>, + OpSize16, Requires<[Not64BitMode]>; +} +let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], + mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { +def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", []>, + OpSize32, Requires<[Not64BitMode]>; +def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", []>, + OpSize16, Requires<[Not64BitMode]>; +} + +let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in { +// This instruction is a consequence of BSWAP32r observing operand size. The +// encoding is valid, but the behavior is undefined. +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in +def BSWAP16r_BAD : I<0xC8, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), + "bswap{w}\t$dst", []>, OpSize16, TB; +// GR32 = bswap GR32 +def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), + "bswap{l}\t$dst", + [(set GR32:$dst, (bswap GR32:$src))]>, OpSize32, TB; + +let SchedRW = [WriteBSWAP64] in +def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), + "bswap{q}\t$dst", + [(set GR64:$dst, (bswap GR64:$src))]>, TB; +} // Constraints = "$src = $dst", SchedRW + +// Bit scan instructions. +let Defs = [EFLAGS] in { +def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "bsf{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, + PS, OpSize16, Sched<[WriteBSF]>; +def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "bsf{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, + PS, OpSize16, Sched<[WriteBSFLd]>; +def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "bsf{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, + PS, OpSize32, Sched<[WriteBSF]>; +def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "bsf{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, + PS, OpSize32, Sched<[WriteBSFLd]>; +def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "bsf{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, + PS, Sched<[WriteBSF]>; +def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "bsf{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, + PS, Sched<[WriteBSFLd]>; + +def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "bsr{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, + PS, OpSize16, Sched<[WriteBSR]>; +def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "bsr{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, + PS, OpSize16, Sched<[WriteBSRLd]>; +def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "bsr{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, + PS, OpSize32, Sched<[WriteBSR]>; +def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "bsr{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, + PS, OpSize32, Sched<[WriteBSRLd]>; +def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "bsr{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, + PS, Sched<[WriteBSR]>; +def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "bsr{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, + PS, Sched<[WriteBSRLd]>; +} // Defs = [EFLAGS] + +let SchedRW = [WriteMicrocoded] in { +let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in { +def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), + "movsb\t{$src, $dst|$dst, $src}", []>; +def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), + "movsw\t{$src, $dst|$dst, $src}", []>, OpSize16; +def MOVSL : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), + "movs{l|d}\t{$src, $dst|$dst, $src}", []>, OpSize32; +def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), + "movsq\t{$src, $dst|$dst, $src}", []>, + Requires<[In64BitMode]>; +} + +let Defs = [EDI], Uses = [AL,EDI,DF] in +def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst), + "stosb\t{%al, $dst|$dst, al}", []>; +let Defs = [EDI], Uses = [AX,EDI,DF] in +def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst), + "stosw\t{%ax, $dst|$dst, ax}", []>, OpSize16; +let Defs = [EDI], Uses = [EAX,EDI,DF] in +def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst), + "stos{l|d}\t{%eax, $dst|$dst, eax}", []>, OpSize32; +let Defs = [RDI], Uses = [RAX,RDI,DF] in +def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst), + "stosq\t{%rax, $dst|$dst, rax}", []>, + Requires<[In64BitMode]>; + +let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in +def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), + "scasb\t{$dst, %al|al, $dst}", []>; +let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in +def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), + "scasw\t{$dst, %ax|ax, $dst}", []>, OpSize16; +let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in +def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), + "scas{l|d}\t{$dst, %eax|eax, $dst}", []>, OpSize32; +let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in +def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), + "scasq\t{$dst, %rax|rax, $dst}", []>, + Requires<[In64BitMode]>; + +let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in { +def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), + "cmpsb\t{$dst, $src|$src, $dst}", []>; +def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), + "cmpsw\t{$dst, $src|$src, $dst}", []>, OpSize16; +def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), + "cmps{l|d}\t{$dst, $src|$src, $dst}", []>, OpSize32; +def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), + "cmpsq\t{$dst, $src|$src, $dst}", []>, + Requires<[In64BitMode]>; +} +} // SchedRW + +//===----------------------------------------------------------------------===// +// Move Instructions. +// +let SchedRW = [WriteMove] in { +let hasSideEffects = 0, isMoveReg = 1 in { +def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>; +def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; +def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; +def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>; +} + +let isReMaterializable = 1, isAsCheapAsAMove = 1 in { +def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(set GR8:$dst, imm:$src)]>; +def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, imm:$src)]>, OpSize16; +def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, relocImm:$src)]>, OpSize32; +def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, i64immSExt32:$src)]>; +} +let isReMaterializable = 1 in { +def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), + "movabs{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, relocImm:$src)]>; +} + +// Longer forms that use a ModR/M byte. Needed for disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { +def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOV8ri">; +def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, + FoldGenData<"MOV16ri">; +def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, + FoldGenData<"MOV32ri">; +} +} // SchedRW + +let SchedRW = [WriteStore] in { +def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(store (i8 imm8_su:$src), addr:$dst)]>; +def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(store (i16 imm16_su:$src), addr:$dst)]>, OpSize16; +def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(store (i32 imm32_su:$src), addr:$dst)]>, OpSize32; +def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(store i64immSExt32_su:$src, addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW + +let hasSideEffects = 0 in { + +/// Memory offset versions of moves. The immediate is an address mode sized +/// offset from the segment base. +let SchedRW = [WriteALU] in { +let mayLoad = 1 in { +let Defs = [AL] in +def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), + "mov{b}\t{$src, %al|al, $src}", []>, + AdSize32; +let Defs = [AX] in +def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), + "mov{w}\t{$src, %ax|ax, $src}", []>, + OpSize16, AdSize32; +let Defs = [EAX] in +def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), + "mov{l}\t{$src, %eax|eax, $src}", []>, + OpSize32, AdSize32; +let Defs = [RAX] in +def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), + "mov{q}\t{$src, %rax|rax, $src}", []>, + AdSize32; + +let Defs = [AL] in +def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), + "mov{b}\t{$src, %al|al, $src}", []>, AdSize16; +let Defs = [AX] in +def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), + "mov{w}\t{$src, %ax|ax, $src}", []>, + OpSize16, AdSize16; +let Defs = [EAX] in +def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), + "mov{l}\t{$src, %eax|eax, $src}", []>, + AdSize16, OpSize32; +} // mayLoad +let mayStore = 1 in { +let Uses = [AL] in +def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst), + "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize32; +let Uses = [AX] in +def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_16:$dst), + "mov{w}\t{%ax, $dst|$dst, ax}", []>, + OpSize16, AdSize32; +let Uses = [EAX] in +def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_32:$dst), + "mov{l}\t{%eax, $dst|$dst, eax}", []>, + OpSize32, AdSize32; +let Uses = [RAX] in +def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs), (ins offset32_64:$dst), + "mov{q}\t{%rax, $dst|$dst, rax}", []>, + AdSize32; + +let Uses = [AL] in +def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs), (ins offset16_8:$dst), + "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize16; +let Uses = [AX] in +def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_16:$dst), + "mov{w}\t{%ax, $dst|$dst, ax}", []>, + OpSize16, AdSize16; +let Uses = [EAX] in +def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst), + "mov{l}\t{%eax, $dst|$dst, eax}", []>, + OpSize32, AdSize16; +} // mayStore + +// These forms all have full 64-bit absolute addresses in their instructions +// and use the movabs mnemonic to indicate this specific form. +let mayLoad = 1 in { +let Defs = [AL] in +def MOV8ao64 : Ii64<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), + "movabs{b}\t{$src, %al|al, $src}", []>, + AdSize64; +let Defs = [AX] in +def MOV16ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), + "movabs{w}\t{$src, %ax|ax, $src}", []>, + OpSize16, AdSize64; +let Defs = [EAX] in +def MOV32ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), + "movabs{l}\t{$src, %eax|eax, $src}", []>, + OpSize32, AdSize64; +let Defs = [RAX] in +def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), + "movabs{q}\t{$src, %rax|rax, $src}", []>, + AdSize64; +} // mayLoad + +let mayStore = 1 in { +let Uses = [AL] in +def MOV8o64a : Ii64<0xA2, RawFrmMemOffs, (outs), (ins offset64_8:$dst), + "movabs{b}\t{%al, $dst|$dst, al}", []>, + AdSize64; +let Uses = [AX] in +def MOV16o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_16:$dst), + "movabs{w}\t{%ax, $dst|$dst, ax}", []>, + OpSize16, AdSize64; +let Uses = [EAX] in +def MOV32o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_32:$dst), + "movabs{l}\t{%eax, $dst|$dst, eax}", []>, + OpSize32, AdSize64; +let Uses = [RAX] in +def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst), + "movabs{q}\t{%rax, $dst|$dst, rax}", []>, + AdSize64; +} // mayStore +} // SchedRW +} // hasSideEffects = 0 + +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, + SchedRW = [WriteMove], isMoveReg = 1 in { +def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOV8rr">; +def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, + FoldGenData<"MOV16rr">; +def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, + FoldGenData<"MOV32rr">; +def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOV64rr">; +} + +// Reversed version with ".s" suffix for GAS compatibility. +//// def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}", +// (MOV8rr_REV GR8:$dst, GR8:$src), 0>; +//// def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}", +// (MOV16rr_REV GR16:$dst, GR16:$src), 0>; +//// def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}", +// (MOV32rr_REV GR32:$dst, GR32:$src), 0>; +//// def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}", +// (MOV64rr_REV GR64:$dst, GR64:$src), 0>; +//// def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">; +//// def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">; +//// def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">; +//// def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">; + +let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { +def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(set GR8:$dst, (loadi8 addr:$src))]>; +def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize16; +def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (loadi32 addr:$src))]>, OpSize32; +def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (load addr:$src))]>; +} + +let SchedRW = [WriteStore] in { +def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(store GR8:$src, addr:$dst)]>; +def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(store GR16:$src, addr:$dst)]>, OpSize16; +def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(store GR32:$src, addr:$dst)]>, OpSize32; +def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(store GR64:$src, addr:$dst)]>; +} // SchedRW + +// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so +// that they can be used for copying and storing h registers, which can't be +// encoded when a REX prefix is present. +let isCodeGenOnly = 1 in { +let hasSideEffects = 0, isMoveReg = 1 in +def MOV8rr_NOREX : I<0x88, MRMDestReg, + (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteMove]>; +let mayStore = 1, hasSideEffects = 0 in +def MOV8mr_NOREX : I<0x88, MRMDestMem, + (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteStore]>; +let mayLoad = 1, hasSideEffects = 0, + canFoldAsLoad = 1, isReMaterializable = 1 in +def MOV8rm_NOREX : I<0x8A, MRMSrcMem, + (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteLoad]>; +} + + +// Condition code ops, incl. set if equal/not equal/... +let SchedRW = [WriteLAHFSAHF] in { +let Defs = [EFLAGS], Uses = [AH] in +def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", + [(set EFLAGS, (X86sahf AH))]>, + Requires<[HasLAHFSAHF]>; +let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in +def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags + Requires<[HasLAHFSAHF]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Bit tests instructions: BT, BTS, BTR, BTC. + +let Defs = [EFLAGS] in { +let SchedRW = [WriteBitTest] in { +def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, + OpSize16, TB, NotMemoryFoldable; +def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, + OpSize32, TB, NotMemoryFoldable; +def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB, + NotMemoryFoldable; +} // SchedRW + +// Unlike with the register+register form, the memory+register form of the +// bt instruction does not ignore the high bits of the index. From ISel's +// perspective, this is pretty bizarre. Make these instructions disassembly +// only for now. These instructions are also slow on modern CPUs so that's +// another reason to avoid generating them. + +let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { + def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + []>, OpSize16, TB, NotMemoryFoldable; + def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + []>, OpSize32, TB, NotMemoryFoldable; + def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + []>, TB, NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest] in { +def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>, + OpSize16, TB; +def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, + OpSize32, TB; +def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB; +} // SchedRW + +// Note that these instructions aren't slow because that only applies when the +// other operand is in a register. When it's an immediate, bt is still fast. +let SchedRW = [WriteALU] in { +def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi16 addr:$src1), + i16immSExt8:$src2))]>, + OpSize16, TB; +def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi32 addr:$src1), + i32immSExt8:$src2))]>, + OpSize32, TB; +def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi64 addr:$src1), + i64immSExt8:$src2))]>, TB, + Requires<[In64BitMode]>; +} // SchedRW + +let hasSideEffects = 0 in { +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTC32rr : I<0xBB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTC64rr : RI<0xBB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTC64ri8 : RIi8<0xBA, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + Requires<[In64BitMode]>; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTR32rr : I<0xB3, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTR64rr : RI<0xB3, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB; +def BTR32ri8 : Ii8<0xBA, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB; +def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB; +def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB; +def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + Requires<[In64BitMode]>; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTS32rr : I<0xAB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTS64rr : RI<0xAB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTS64ri8 : RIi8<0xBA, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + Requires<[In64BitMode]>; +} +} // hasSideEffects = 0 +} // Defs = [EFLAGS] + + +//===----------------------------------------------------------------------===// +// Atomic support +// + +// Atomic swap. These are just normal xchg instructions. But since a memory +// operand is referenced, the atomicity is ensured. +multiclass ATOMIC_SWAP opc8, bits<8> opc, string mnemonic, string frag> { + let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { + def NAME#8rm : I(frag # "_8") addr:$ptr, GR8:$val))]>; + def NAME#16rm : I(frag # "_16") addr:$ptr, GR16:$val))]>, + OpSize16; + def NAME#32rm : I(frag # "_32") addr:$ptr, GR32:$val))]>, + OpSize32; + def NAME#64rm : RI(frag # "_64") addr:$ptr, GR64:$val))]>; + } +} + +defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">, NotMemoryFoldable; + +// Swap between registers. +let SchedRW = [WriteALU] in { +let Constraints = "$src1 = $dst1, $src2 = $dst2", hasSideEffects = 0 in { +def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2), + (ins GR8:$src1, GR8:$src2), + "xchg{b}\t{$src1, $src2|$src2, $src1}", []>, NotMemoryFoldable; +def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2), + (ins GR16:$src1, GR16:$src2), + "xchg{w}\t{$src1, $src2|$src2, $src1}", []>, + OpSize16, NotMemoryFoldable; +def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2), + (ins GR32:$src1, GR32:$src2), + "xchg{l}\t{$src1, $src2|$src2, $src1}", []>, + OpSize32, NotMemoryFoldable; +def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst1, GR64:$dst2), + (ins GR64:$src1 ,GR64:$src2), + "xchg{q}\t{$src1, $src2|$src2, $src1}", []>, NotMemoryFoldable; +} + +def NOOP19rr: I<0x19, MRMSrcReg, (outs), (ins GR32:$val, GR32:$src), + "nop\t{$val, $src|$src, $val}", []>, TB, + OpSize32; + +// Swap between EAX and other registers. +let Constraints = "$src = $dst", hasSideEffects = 0 in { +let Uses = [AX], Defs = [AX] in +def XCHG16ar : I<0x90, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), + "xchg{w}\t{%ax, $src|$src, ax}", []>, OpSize16; +let Uses = [EAX], Defs = [EAX] in +def XCHG32ar : I<0x90, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), + "xchg{l}\t{%eax, $src|$src, eax}", []>, OpSize32; +let Uses = [RAX], Defs = [RAX] in +def XCHG64ar : RI<0x90, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), + "xchg{q}\t{%rax, $src|$src, rax}", []>; +} +} // SchedRW + +let hasSideEffects = 0, Constraints = "$src1 = $dst1, $src2 = $dst2", + Defs = [EFLAGS], SchedRW = [WriteALU] in { +def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst1, GR8:$dst2), + (ins GR8:$src1, GR8:$src2), + "xadd{b}\t{$src2, $src1|$src1, $src2}", []>, TB; +def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst1, GR16:$dst2), + (ins GR16:$src1, GR16:$src2), + "xadd{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16; +def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst1, GR32:$dst2), + (ins GR32:$src1, GR32:$src2), + "xadd{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32; +def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst1, GR64:$dst2), + (ins GR64:$src1, GR64:$src2), + "xadd{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, hasSideEffects = 0, Constraints = "$val = $dst", + Defs = [EFLAGS], SchedRW = [WriteALULd, WriteRMW] in { +def XADD8rm : I<0xC0, MRMSrcMem, (outs GR8:$dst), + (ins GR8:$val, i8mem:$ptr), + "xadd{b}\t{$val, $ptr|$ptr, $val}", []>, TB; +def XADD16rm : I<0xC1, MRMSrcMem, (outs GR16:$dst), + (ins GR16:$val, i16mem:$ptr), + "xadd{w}\t{$val, $ptr|$ptr, $val}", []>, TB, + OpSize16; +def XADD32rm : I<0xC1, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$val, i32mem:$ptr), + "xadd{l}\t{$val, $ptr|$ptr, $val}", []>, TB, + OpSize32; +def XADD64rm : RI<0xC1, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$val, i64mem:$ptr), + "xadd{q}\t{$val, $ptr|$ptr, $val}", []>, TB; + +} + +let SchedRW = [WriteALU], hasSideEffects = 0 in { +let Defs = [AL, EFLAGS], Uses = [AL] in +def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), + "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; +let Defs = [AX, EFLAGS], Uses = [AX] in +def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), + "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, + NotMemoryFoldable; +let Defs = [EAX, EFLAGS], Uses = [EAX] in +def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), + "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, + NotMemoryFoldable; +let Defs = [RAX, EFLAGS], Uses = [RAX] in +def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), + "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; +} // SchedRW, hasSideEffects + +let SchedRW = [WriteALULd, WriteRMW], mayLoad = 1, mayStore = 1, + hasSideEffects = 0 in { +let Defs = [AL, EFLAGS], Uses = [AL] in +def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), + "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; +let Defs = [AX, EFLAGS], Uses = [AX] in +def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, + NotMemoryFoldable; +let Defs = [EAX, EFLAGS], Uses = [EAX] in +def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, + NotMemoryFoldable; +let Defs = [RAX, EFLAGS], Uses = [RAX] in +def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; + +let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in +def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), + "cmpxchg8b\t$dst", []>, TB; + +let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in +def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), + "cmpxchg16b\t$dst", []>, + TB, Requires<[HasCmpxchg16b, In64BitMode]>; +} // SchedRW, mayLoad, mayStore, hasSideEffects + + +// Lock instruction prefix +let SchedRW = [WriteMicrocoded] in +def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; + +let SchedRW = [WriteNop] in { + +// Rex64 instruction prefix +def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>, + Requires<[In64BitMode]>; + +// Data16 instruction prefix +def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; +} // SchedRW + +// Repeat string operation instruction prefixes +let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in { +// Repeat (used with INS, OUTS, MOVS, LODS and STOS) +def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; +// Repeat while not equal (used with CMPS and SCAS) +def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; +} + +// String manipulation instructions +let SchedRW = [WriteMicrocoded] in { +let Defs = [AL,ESI], Uses = [ESI,DF] in +def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), + "lodsb\t{$src, %al|al, $src}", []>; +let Defs = [AX,ESI], Uses = [ESI,DF] in +def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), + "lodsw\t{$src, %ax|ax, $src}", []>, OpSize16; +let Defs = [EAX,ESI], Uses = [ESI,DF] in +def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), + "lods{l|d}\t{$src, %eax|eax, $src}", []>, OpSize32; +let Defs = [RAX,ESI], Uses = [ESI,DF] in +def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), + "lodsq\t{$src, %rax|rax, $src}", []>, + Requires<[In64BitMode]>; +} + +let SchedRW = [WriteSystem] in { +let Defs = [ESI], Uses = [DX,ESI,DF] in { +def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), + "outsb\t{$src, %dx|dx, $src}", []>; +def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), + "outsw\t{$src, %dx|dx, $src}", []>, OpSize16; +def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), + "outs{l|d}\t{$src, %dx|dx, $src}", []>, OpSize32; +} + +let Defs = [EDI], Uses = [DX,EDI,DF] in { +def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst), + "insb\t{%dx, $dst|$dst, dx}", []>; +def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst), + "insw\t{%dx, $dst|$dst, dx}", []>, OpSize16; +def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst), + "ins{l|d}\t{%dx, $dst|$dst, dx}", []>, OpSize32; +} +} + +// EFLAGS management instructions. +let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { +def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; +def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; +def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; +} + +// DF management instructions. +let SchedRW = [WriteALU], Defs = [DF] in { +def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; +def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; +} + +// Table lookup instructions +let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in +def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>, Sched<[WriteLoad]>; + +let SchedRW = [WriteMicrocoded] in { +// ASCII Adjust After Addition +let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, + Requires<[Not64BitMode]>; + +// ASCII Adjust AX Before Division +let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), + "aad\t$src", []>, Requires<[Not64BitMode]>; + +// ASCII Adjust AX After Multiply +let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), + "aam\t$src", []>, Requires<[Not64BitMode]>; + +// ASCII Adjust AL After Subtraction - sets +let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, + Requires<[Not64BitMode]>; + +// Decimal Adjust AL after Addition +let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in +def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, + Requires<[Not64BitMode]>; + +// Decimal Adjust AL after Subtraction +let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in +def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, + Requires<[Not64BitMode]>; +} // SchedRW + +let SchedRW = [WriteSystem] in { +// Check Array Index Against Bounds +// Note: "bound" does not have reversed operands in at&t syntax. +def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i32mem:$src), + "bound\t$dst, $src", []>, OpSize16, + Requires<[Not64BitMode]>; +def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i64mem:$src), + "bound\t$dst, $src", []>, OpSize32, + Requires<[Not64BitMode]>; + +// Adjust RPL Field of Segment Selector +def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), + "arpl\t{$src, $dst|$dst, $src}", []>, + Requires<[Not64BitMode]>, NotMemoryFoldable; +let mayStore = 1 in +def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "arpl\t{$src, $dst|$dst, $src}", []>, + Requires<[Not64BitMode]>, NotMemoryFoldable; +} // SchedRW + +//===----------------------------------------------------------------------===// +// MOVBE Instructions +// +let Predicates = [HasMOVBE] in { + let SchedRW = [WriteALULd] in { + def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "movbe{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, + OpSize16, T8PS; + def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "movbe{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, + OpSize32, T8PS; + def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "movbe{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, + T8PS; + } + let SchedRW = [WriteStore] in { + def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "movbe{w}\t{$src, $dst|$dst, $src}", + [(store (bswap GR16:$src), addr:$dst)]>, + OpSize16, T8PS; + def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "movbe{l}\t{$src, $dst|$dst, $src}", + [(store (bswap GR32:$src), addr:$dst)]>, + OpSize32, T8PS; + def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "movbe{q}\t{$src, $dst|$dst, $src}", + [(store (bswap GR64:$src), addr:$dst)]>, + T8PS; + } +} + +//===----------------------------------------------------------------------===// +// RDRAND Instruction +// +let Predicates = [HasRDRAND], Defs = [EFLAGS], SchedRW = [WriteSystem] in { + def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), + "rdrand{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86rdrand))]>, + OpSize16, PS; + def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), + "rdrand{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86rdrand))]>, + OpSize32, PS; + def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), + "rdrand{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86rdrand))]>, + PS; +} + +//===----------------------------------------------------------------------===// +// RDSEED Instruction +// +let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in { + def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), "rdseed{w}\t$dst", + [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, PS; + def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), "rdseed{l}\t$dst", + [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, PS; + def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdseed{q}\t$dst", + [(set GR64:$dst, EFLAGS, (X86rdseed))]>, PS; +} + +//===----------------------------------------------------------------------===// +// LZCNT Instruction +// +let Predicates = [HasLZCNT], Defs = [EFLAGS] in { + def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "lzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, + XS, OpSize16, Sched<[WriteLZCNT]>; + def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "lzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (ctlz (loadi16 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteLZCNTLd]>; + + def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "lzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, + XS, OpSize32, Sched<[WriteLZCNT]>; + def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "lzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (ctlz (loadi32 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteLZCNTLd]>; + + def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "lzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, + XS, Sched<[WriteLZCNT]>; + def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "lzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (ctlz (loadi64 addr:$src))), + (implicit EFLAGS)]>, XS, Sched<[WriteLZCNTLd]>; +} + +//===----------------------------------------------------------------------===// +// BMI Instructions +// +let Predicates = [HasBMI], Defs = [EFLAGS] in { + def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "tzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, + XS, OpSize16, Sched<[WriteTZCNT]>; + def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "tzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (cttz (loadi16 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteTZCNTLd]>; + + def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "tzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, + XS, OpSize32, Sched<[WriteTZCNT]>; + def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "tzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (cttz (loadi32 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteTZCNTLd]>; + + def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "tzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, + XS, Sched<[WriteTZCNT]>; + def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "tzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (cttz (loadi64 addr:$src))), + (implicit EFLAGS)]>, XS, Sched<[WriteTZCNTLd]>; +} + +multiclass bmi_bls { +let hasSideEffects = 0 in { + def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), + !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, + T8PS, VEX_4V, Sched<[WriteALU]>; + let mayLoad = 1 in + def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), + !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, + T8PS, VEX_4V, Sched<[WriteALULd]>; +} +} + +let Predicates = [HasBMI], Defs = [EFLAGS] in { + defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; + defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W; + defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>; + defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W; + defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>; + defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W; +} + +//===----------------------------------------------------------------------===// +// Pattern fragments to auto generate BMI instructions. +//===----------------------------------------------------------------------===// + +let Predicates = [HasBMI] in { + // FIXME: patterns for the load versions are not implemented + def : Pat<(and GR32:$src, (add GR32:$src, -1)), + (BLSR32rr GR32:$src)>; + def : Pat<(and GR64:$src, (add GR64:$src, -1)), + (BLSR64rr GR64:$src)>; + + def : Pat<(xor GR32:$src, (add GR32:$src, -1)), + (BLSMSK32rr GR32:$src)>; + def : Pat<(xor GR64:$src, (add GR64:$src, -1)), + (BLSMSK64rr GR64:$src)>; + + def : Pat<(and GR32:$src, (ineg GR32:$src)), + (BLSI32rr GR32:$src)>; + def : Pat<(and GR64:$src, (ineg GR64:$src)), + (BLSI64rr GR64:$src)>; +} + +multiclass bmi_bextr opc, string mnemonic, RegisterClass RC, + X86MemOperand x86memop, SDNode OpNode, + PatFrag ld_frag, X86FoldableSchedWrite Sched> { + def rr : I, + T8PS, VEX, Sched<[Sched]>; + def rm : I, T8PS, VEX, + Sched<[Sched.Folded, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + ReadAfterLd]>; +} + +let Predicates = [HasBMI], Defs = [EFLAGS] in { + defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem, + X86bextr, loadi32, WriteBEXTR>; + defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem, + X86bextr, loadi64, WriteBEXTR>, VEX_W; +} + +multiclass bmi_bzhi opc, string mnemonic, RegisterClass RC, + X86MemOperand x86memop, Intrinsic Int, + PatFrag ld_frag, X86FoldableSchedWrite Sched> { + def rr : I, + T8PS, VEX, Sched<[Sched]>; + def rm : I, T8PS, VEX, + Sched<[Sched.Folded, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + ReadAfterLd]>; +} + +let Predicates = [HasBMI2], Defs = [EFLAGS] in { + defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem, + int_x86_bmi_bzhi_32, loadi32, WriteBZHI>; + defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem, + int_x86_bmi_bzhi_64, loadi64, WriteBZHI>, VEX_W; +} + +def CountTrailingOnes : SDNodeXFormgetZExtValue()), SDLoc(N)); +}]>; + +def BEXTRMaskXForm : SDNodeXFormgetZExtValue()); + return getI32Imm(Length << 8, SDLoc(N)); +}]>; + +def AndMask64 : ImmLeaf(Imm); +}]>; + +// Use BEXTR for 64-bit 'and' with large immediate 'mask'. +let Predicates = [HasBMI, NoBMI2, NoTBM] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BEXTR64rr GR64:$src, + (SUBREG_TO_REG (i64 0), + (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BEXTR64rm addr:$src, + (SUBREG_TO_REG (i64 0), + (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; +} + +// Use BZHI for 64-bit 'and' with large immediate 'mask'. +let Predicates = [HasBMI2, NoTBM] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; +} + +let Predicates = [HasBMI2] in { + multiclass _bmi_bzhi_pattern { + def : Pat; + def : Pat; + } + + multiclass bmi_bzhi_patterns { + // x & ((1 << y) - 1) + defm : _bmi_bzhi_pattern<(and RC:$src, (add (shl 1, GR8:$lz), -1)), + (and (x86memop addr:$src), + (add (shl 1, GR8:$lz), -1)), + RC, VT, DstInst, DstMemInst>; + + // x & ~(-1 << y) + defm : _bmi_bzhi_pattern<(and RC:$src, (xor (shl -1, GR8:$lz), -1)), + (and (x86memop addr:$src), + (xor (shl -1, GR8:$lz), -1)), + RC, VT, DstInst, DstMemInst>; + + // x & (-1 >> (bitwidth - y)) + defm : _bmi_bzhi_pattern<(and RC:$src, (srl -1, (sub bitwidth, GR8:$lz))), + (and (x86memop addr:$src), + (srl -1, (sub bitwidth, GR8:$lz))), + RC, VT, DstInst, DstMemInst>; + + // x << (bitwidth - y) >> (bitwidth - y) + defm : _bmi_bzhi_pattern<(srl (shl RC:$src, (sub bitwidth, GR8:$lz)), + (sub bitwidth, GR8:$lz)), + (srl (shl (x86memop addr:$src), + (sub bitwidth, GR8:$lz)), + (sub bitwidth, GR8:$lz)), + RC, VT, DstInst, DstMemInst>; + } + + defm : bmi_bzhi_patterns; + defm : bmi_bzhi_patterns; + + // x & (-1 >> (32 - y)) + def : Pat<(and GR32:$src, (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), + (BZHI32rr GR32:$src, GR32:$lz)>; + def : Pat<(and (loadi32 addr:$src), (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), + (BZHI32rm addr:$src, GR32:$lz)>; + + // x & (-1 >> (64 - y)) + def : Pat<(and GR64:$src, (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + def : Pat<(and (loadi64 addr:$src), (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + + // x << (32 - y) >> (32 - y) + def : Pat<(srl (shl GR32:$src, (i8 (trunc (sub 32, GR32:$lz)))), + (i8 (trunc (sub 32, GR32:$lz)))), + (BZHI32rr GR32:$src, GR32:$lz)>; + def : Pat<(srl (shl (loadi32 addr:$src), (i8 (trunc (sub 32, GR32:$lz)))), + (i8 (trunc (sub 32, GR32:$lz)))), + (BZHI32rm addr:$src, GR32:$lz)>; + + // x << (64 - y) >> (64 - y) + def : Pat<(srl (shl GR64:$src, (i8 (trunc (sub 64, GR32:$lz)))), + (i8 (trunc (sub 64, GR32:$lz)))), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + def : Pat<(srl (shl (loadi64 addr:$src), (i8 (trunc (sub 64, GR32:$lz)))), + (i8 (trunc (sub 64, GR32:$lz)))), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; +} // HasBMI2 + +multiclass bmi_pdep_pext { + def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, + VEX_4V, Sched<[WriteALU]>; + def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, + VEX_4V, Sched<[WriteALULd, ReadAfterLd]>; +} + +let Predicates = [HasBMI2] in { + defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, + int_x86_bmi_pdep_32, loadi32>, T8XD; + defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, + int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; + defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, + int_x86_bmi_pext_32, loadi32>, T8XS; + defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, + int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; +} + +//===----------------------------------------------------------------------===// +// TBM Instructions +// +let Predicates = [HasTBM], Defs = [EFLAGS] in { + +multiclass tbm_ternary_imm opc, RegisterClass RC, string OpcodeStr, + X86MemOperand x86memop, PatFrag ld_frag, + SDNode OpNode, Operand immtype, + SDPatternOperator immoperator, + X86FoldableSchedWrite Sched> { + def ri : Ii32, + XOP, XOPA, Sched<[Sched]>; + def mi : Ii32, + XOP, XOPA, Sched<[Sched.Folded]>; +} + +defm BEXTRI32 : tbm_ternary_imm<0x10, GR32, "bextr{l}", i32mem, loadi32, + X86bextr, i32imm, imm, WriteBEXTR>; +let ImmT = Imm32S in +defm BEXTRI64 : tbm_ternary_imm<0x10, GR64, "bextr{q}", i64mem, loadi64, + X86bextr, i64i32imm, + i64immSExt32, WriteBEXTR>, VEX_W; + +multiclass tbm_binary_rm opc, Format FormReg, Format FormMem, + RegisterClass RC, string OpcodeStr, + X86MemOperand x86memop, X86FoldableSchedWrite Sched> { +let hasSideEffects = 0 in { + def rr : I, + XOP_4V, XOP9, Sched<[Sched]>; + let mayLoad = 1 in + def rm : I, + XOP_4V, XOP9, Sched<[Sched.Folded]>; +} +} + +multiclass tbm_binary_intr opc, string OpcodeStr, + X86FoldableSchedWrite Sched, + Format FormReg, Format FormMem> { + defm NAME#32 : tbm_binary_rm; + defm NAME#64 : tbm_binary_rm, VEX_W; +} + +defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>; +defm BLCI : tbm_binary_intr<0x02, "blci", WriteALU, MRM6r, MRM6m>; +defm BLCIC : tbm_binary_intr<0x01, "blcic", WriteALU, MRM5r, MRM5m>; +defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", WriteALU, MRM1r, MRM1m>; +defm BLCS : tbm_binary_intr<0x01, "blcs", WriteALU, MRM3r, MRM3m>; +defm BLSFILL : tbm_binary_intr<0x01, "blsfill", WriteALU, MRM2r, MRM2m>; +defm BLSIC : tbm_binary_intr<0x01, "blsic", WriteALU, MRM6r, MRM6m>; +defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", WriteALU, MRM7r, MRM7m>; +defm TZMSK : tbm_binary_intr<0x01, "tzmsk", WriteALU, MRM4r, MRM4m>; +} // HasTBM, EFLAGS + +// Use BEXTRI for 64-bit 'and' with large immediate 'mask'. +let Predicates = [HasTBM] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BEXTRI64ri GR64:$src, (BEXTRMaskXForm imm:$mask))>; + + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BEXTRI64mi addr:$src, (BEXTRMaskXForm imm:$mask))>; +} + +//===----------------------------------------------------------------------===// +// Lightweight Profiling Instructions + +let Predicates = [HasLWP], SchedRW = [WriteSystem] in { + +def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", + [(int_x86_llwpcb GR32:$src)]>, XOP, XOP9; +def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", + [(set GR32:$dst, (int_x86_slwpcb))]>, XOP, XOP9; + +def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", + [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, VEX_W; +def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", + [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, VEX_W; + +multiclass lwpins_intr { + def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), + "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, imm:$cntl))]>, + XOP_4V, XOPA; + let mayLoad = 1 in + def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), + "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), imm:$cntl))]>, + XOP_4V, XOPA; +} + +let Defs = [EFLAGS] in { + defm LWPINS32 : lwpins_intr; + defm LWPINS64 : lwpins_intr, VEX_W; +} // EFLAGS + +multiclass lwpval_intr { + def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), + "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(Int RC:$src0, GR32:$src1, imm:$cntl)]>, XOP_4V, XOPA; + let mayLoad = 1 in + def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), + "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(Int RC:$src0, (loadi32 addr:$src1), imm:$cntl)]>, + XOP_4V, XOPA; +} + +defm LWPVAL32 : lwpval_intr; +defm LWPVAL64 : lwpval_intr, VEX_W; + +} // HasLWP, SchedRW + +//===----------------------------------------------------------------------===// +// MONITORX/MWAITX Instructions +// +let SchedRW = [ WriteSystem ] in { +/* + let usesCustomInserter = 1 in { + def MONITORX : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3), + [(int_x86_monitorx addr:$src1, GR32:$src2, GR32:$src3)]>, + Requires<[ HasMWAITX ]>; + } +*/ + + let Uses = [ EAX, ECX, EDX ] in { + def MONITORXrrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, + TB, Requires<[ HasMWAITX ]>; + } + + let Uses = [ ECX, EAX, EBX ] in { + def MWAITXrrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", + [(int_x86_mwaitx ECX, EAX, EBX)]>, + TB, Requires<[ HasMWAITX ]>; + } +} // SchedRW + +// def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrrr)>, +// Requires<[ Not64BitMode ]>; +// def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>, +// Requires<[ In64BitMode ]>; + +// def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORXrrr)>, +// Requires<[ Not64BitMode ]>; +// def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>, +// Requires<[ In64BitMode ]>; + +//===----------------------------------------------------------------------===// +// WAITPKG Instructions +// +let SchedRW = [WriteSystem] in { + def UMONITOR16 : I<0xAE, MRM6r, (outs), (ins GR16:$src), + "umonitor\t$src", [(int_x86_umonitor GR16:$src)]>, + XS, AdSize16, Requires<[HasWAITPKG, Not64BitMode]>; + def UMONITOR32 : I<0xAE, MRM6r, (outs), (ins GR32:$src), + "umonitor\t$src", [(int_x86_umonitor GR32:$src)]>, + XS, AdSize32, Requires<[HasWAITPKG]>; + def UMONITOR64 : I<0xAE, MRM6r, (outs), (ins GR64:$src), + "umonitor\t$src", [(int_x86_umonitor GR64:$src)]>, + XS, AdSize64, Requires<[HasWAITPKG, In64BitMode]>; + let Uses = [EAX, EDX], Defs = [EFLAGS] in { + def UMWAIT : I<0xAE, MRM6r, + (outs), (ins GR32orGR64:$src), "umwait\t$src", + [(set EFLAGS, (X86umwait GR32orGR64:$src, EDX, EAX))]>, + XD, Requires<[HasWAITPKG]>; + def TPAUSE : I<0xAE, MRM6r, + (outs), (ins GR32orGR64:$src), "tpause\t$src", + [(set EFLAGS, (X86tpause GR32orGR64:$src, EDX, EAX))]>, + PD, Requires<[HasWAITPKG]>, NotMemoryFoldable; + } +} // SchedRW + +//===----------------------------------------------------------------------===// +// MOVDIRI - Move doubleword/quadword as direct store +// +let SchedRW = [WriteStore] in { +def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "movdiri\t{$src, $dst|$dst, $src}", + [(int_x86_directstore32 addr:$dst, GR32:$src)]>, + T8, Requires<[HasMOVDIRI]>; +def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "movdiri\t{$src, $dst|$dst, $src}", + [(int_x86_directstore64 addr:$dst, GR64:$src)]>, + T8, Requires<[In64BitMode, HasMOVDIRI]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// MOVDIR64B - Move 64 bytes as direct store +// +let SchedRW = [WriteStore] in { +def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), + "movdir64b\t{$src, $dst|$dst, $src}", []>, + T8PD, AdSize16, Requires<[HasMOVDIR64B, Not64BitMode]>; +def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), + "movdir64b\t{$src, $dst|$dst, $src}", + [(int_x86_movdir64b GR32:$dst, addr:$src)]>, + T8PD, AdSize32, Requires<[HasMOVDIR64B]>; +def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), + "movdir64b\t{$src, $dst|$dst, $src}", + [(int_x86_movdir64b GR64:$dst, addr:$src)]>, + T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// CLZERO Instruction +// +let SchedRW = [WriteSystem] in { + let Uses = [EAX] in + def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, + TB, Requires<[HasCLZERO]>; + +/* + let usesCustomInserter = 1 in { + def CLZERO : PseudoI<(outs), (ins i32mem:$src1), + [(int_x86_clzero addr:$src1)]>, Requires<[HasCLZERO]>; + } +*/ +} // SchedRW + +// def : InstAlias<"clzero\t{%eax|eax}", (CLZEROr)>, Requires<[Not64BitMode]>; +// def : InstAlias<"clzero\t{%rax|rax}", (CLZEROr)>, Requires<[In64BitMode]>; + +//===----------------------------------------------------------------------===// +// Pattern fragments to auto generate TBM instructions. +//===----------------------------------------------------------------------===// + +let Predicates = [HasTBM] in { + // FIXME: patterns for the load versions are not implemented + def : Pat<(and GR32:$src, (add GR32:$src, 1)), + (BLCFILL32rr GR32:$src)>; + def : Pat<(and GR64:$src, (add GR64:$src, 1)), + (BLCFILL64rr GR64:$src)>; + + def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), + (BLCI32rr GR32:$src)>; + def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), + (BLCI64rr GR64:$src)>; + + // Extra patterns because opt can optimize the above patterns to this. + def : Pat<(or GR32:$src, (sub -2, GR32:$src)), + (BLCI32rr GR32:$src)>; + def : Pat<(or GR64:$src, (sub -2, GR64:$src)), + (BLCI64rr GR64:$src)>; + + def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), + (BLCIC32rr GR32:$src)>; + def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), + (BLCIC64rr GR64:$src)>; + + def : Pat<(xor GR32:$src, (add GR32:$src, 1)), + (BLCMSK32rr GR32:$src)>; + def : Pat<(xor GR64:$src, (add GR64:$src, 1)), + (BLCMSK64rr GR64:$src)>; + + def : Pat<(or GR32:$src, (add GR32:$src, 1)), + (BLCS32rr GR32:$src)>; + def : Pat<(or GR64:$src, (add GR64:$src, 1)), + (BLCS64rr GR64:$src)>; + + def : Pat<(or GR32:$src, (add GR32:$src, -1)), + (BLSFILL32rr GR32:$src)>; + def : Pat<(or GR64:$src, (add GR64:$src, -1)), + (BLSFILL64rr GR64:$src)>; + + def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), + (BLSIC32rr GR32:$src)>; + def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), + (BLSIC64rr GR64:$src)>; + + def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), + (T1MSKC32rr GR32:$src)>; + def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), + (T1MSKC64rr GR64:$src)>; + + def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), + (TZMSK32rr GR32:$src)>; + def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), + (TZMSK64rr GR64:$src)>; +} // HasTBM + +//===----------------------------------------------------------------------===// +// Memory Instructions +// + +let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in +def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), + "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD; + +let Predicates = [HasCLWB], SchedRW = [WriteLoad] in +def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", + [(int_x86_clwb addr:$src)]>, PD, NotMemoryFoldable; + +let Predicates = [HasCLDEMOTE], SchedRW = [WriteLoad] in +def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src", + [(int_x86_cldemote addr:$src)]>, TB; + +//===----------------------------------------------------------------------===// +// Subsystems. +//===----------------------------------------------------------------------===// + +include "X86Capstone.td" + +include "X86InstrArithmetic.td" +include "X86InstrCMovSetCC.td" +include "X86InstrExtension.td" +include "X86InstrControl.td" +include "X86InstrShiftRotate.td" + +// X87 Floating Point Stack. +include "X86InstrFPStack.td" + +// SIMD support (SSE, MMX and AVX) +include "X86InstrFragmentsSIMD.td" + +// FMA - Fused Multiply-Add support (requires FMA) +include "X86InstrFMA.td" + +// XOP +include "X86InstrXOP.td" + +// SSE, MMX and 3DNow! vector support. +include "X86InstrSSE.td" +include "X86InstrAVX512.td" +include "X86InstrMMX.td" +include "X86Instr3DNow.td" + +// MPX instructions +include "X86InstrMPX.td" + +include "X86InstrVMX.td" +include "X86InstrSVM.td" + +include "X86InstrTSX.td" +include "X86InstrSGX.td" + +// System instructions. +include "X86InstrSystem.td" + +// Compiler Pseudo Instructions and Pat Patterns +//include "X86InstrCompiler.td" +//include "X86InstrVecCompiler.td" + +//===----------------------------------------------------------------------===// +// Assembler Mnemonic Aliases +//===----------------------------------------------------------------------===// + +def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; + +def : MnemonicAlias<"cbw", "cbtw", "att">; +def : MnemonicAlias<"cwde", "cwtl", "att">; +def : MnemonicAlias<"cwd", "cwtd", "att">; +def : MnemonicAlias<"cdq", "cltd", "att">; +def : MnemonicAlias<"cdqe", "cltq", "att">; +def : MnemonicAlias<"cqo", "cqto", "att">; + +// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. +def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; + +def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; +def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; + +def : MnemonicAlias<"loopz", "loope">; +def : MnemonicAlias<"loopnz", "loopne">; + +def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"popf", "popfq", "intel">, Requires<[In64BitMode]>; +def : MnemonicAlias<"popfd", "popfl", "att">; + +// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in +// all modes. However: "push (addr)" and "push $42" should default to +// pushl/pushq depending on the current mode. Similar for "pop %bx" +def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"pushf", "pushfq", "intel">, Requires<[In64BitMode]>; +def : MnemonicAlias<"pushfd", "pushfl", "att">; + +def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; +def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; +def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; +def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; + +def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; + +def : MnemonicAlias<"repe", "rep">; +def : MnemonicAlias<"repz", "rep">; +def : MnemonicAlias<"repnz", "repne">; + +def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; + +// Apply 'ret' behavior to 'retn' +def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"retn", "ret", "intel">; + +def : MnemonicAlias<"sal", "shl", "intel">; +def : MnemonicAlias<"salb", "shlb", "att">; +def : MnemonicAlias<"salw", "shlw", "att">; +def : MnemonicAlias<"sall", "shll", "att">; +def : MnemonicAlias<"salq", "shlq", "att">; + +def : MnemonicAlias<"smovb", "movsb", "att">; +def : MnemonicAlias<"smovw", "movsw", "att">; +def : MnemonicAlias<"smovl", "movsl", "att">; +def : MnemonicAlias<"smovq", "movsq", "att">; + +def : MnemonicAlias<"ud2a", "ud2", "att">; +def : MnemonicAlias<"verrw", "verr", "att">; + +// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release' +def : MnemonicAlias<"acquire", "xacquire", "intel">; +def : MnemonicAlias<"release", "xrelease", "intel">; + +// System instruction aliases. +def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; +def : MnemonicAlias<"sysret", "sysretl", "att">; +def : MnemonicAlias<"sysexit", "sysexitl", "att">; + +def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; +//def : MnemonicAlias<"lgdt", "lgdtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"lgdt", "lgdtd", "intel">, Requires<[In32BitMode]>; +//def : MnemonicAlias<"lidt", "lidtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"lidt", "lidtd", "intel">, Requires<[In32BitMode]>; +//def : MnemonicAlias<"sgdt", "sgdtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"sgdt", "sgdtd", "intel">, Requires<[In32BitMode]>; +//def : MnemonicAlias<"sidt", "sidtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"sidt", "sidtd", "intel">, Requires<[In32BitMode]>; + + +// Floating point stack aliases. +def : MnemonicAlias<"fcmovz", "fcmove", "att">; +def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; +def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; +def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; +def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; +def : MnemonicAlias<"fcomip", "fcompi">; +def : MnemonicAlias<"fildq", "fildll", "att">; +def : MnemonicAlias<"fistpq", "fistpll", "att">; +def : MnemonicAlias<"fisttpq", "fisttpll", "att">; +def : MnemonicAlias<"fldcww", "fldcw", "att">; +def : MnemonicAlias<"fnstcww", "fnstcw", "att">; +def : MnemonicAlias<"fnstsww", "fnstsw", "att">; +def : MnemonicAlias<"fucomip", "fucompi">; +def : MnemonicAlias<"fwait", "wait">; + +def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; +def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; +def : MnemonicAlias<"xsaveq", "xsave64", "att">; +def : MnemonicAlias<"xrstorq", "xrstor64", "att">; +def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; +def : MnemonicAlias<"xrstorsq", "xrstors64", "att">; +def : MnemonicAlias<"xsavecq", "xsavec64", "att">; +def : MnemonicAlias<"xsavesq", "xsaves64", "att">; + +class CondCodeAlias + : MnemonicAlias; + +/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of +/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for +/// example "setz" -> "sete". +multiclass IntegerCondCodeMnemonicAlias { + def C : CondCodeAlias; // setc -> setb + def Z : CondCodeAlias; // setz -> sete + def NA : CondCodeAlias; // setna -> setbe + def NB : CondCodeAlias; // setnb -> setae + def NC : CondCodeAlias; // setnc -> setae + def NG : CondCodeAlias; // setng -> setle + def NL : CondCodeAlias; // setnl -> setge + def NZ : CondCodeAlias; // setnz -> setne + def PE : CondCodeAlias; // setpe -> setp + def PO : CondCodeAlias; // setpo -> setnp + + def NAE : CondCodeAlias; // setnae -> setb + def NBE : CondCodeAlias; // setnbe -> seta + def NGE : CondCodeAlias; // setnge -> setl + def NLE : CondCodeAlias; // setnle -> setg +} + +// Aliases for set +defm : IntegerCondCodeMnemonicAlias<"set", "">; +// Aliases for j +defm : IntegerCondCodeMnemonicAlias<"j", "">; +// Aliases for cmov{w,l,q} +defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; +defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; +defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; +// No size suffix for intel-style asm. +defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; + + +//===----------------------------------------------------------------------===// +// Assembler Instruction Aliases +//===----------------------------------------------------------------------===// + +// aad/aam default to base 10 if no operand is specified. +// def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>; +// def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>; + +// Disambiguate the mem/imm form of bt-without-a-suffix as btl. +// Likewise for btc/btr/bts. +// def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}", +// (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; +// def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}", +// (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; +// def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}", +// (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; +// def : InstAlias<"bts\t{$imm, $mem|$mem, $imm}", +// (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; + +// clr aliases. +// def : InstAlias<"clr{b}\t$reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; +// def : InstAlias<"clr{w}\t$reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; +// def : InstAlias<"clr{l}\t$reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; +// def : InstAlias<"clr{q}\t$reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; + +// lods aliases. Accept the destination being omitted because it's implicit +// in the mnemonic, or the mnemonic suffix being omitted because it's implicit +// in the destination. +// def : InstAlias<"lodsb\t$src", (LODSB srcidx8:$src), 0>; +// def : InstAlias<"lodsw\t$src", (LODSW srcidx16:$src), 0>; +// def : InstAlias<"lods{l|d}\t$src", (LODSL srcidx32:$src), 0>; +// def : InstAlias<"lodsq\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; +// def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; +// def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; +// def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; +// def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; +// def : InstAlias<"lods\t$src", (LODSB srcidx8:$src), 0, "intel">; +// def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0, "intel">; +// def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0, "intel">; +// def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; + + +// stos aliases. Accept the source being omitted because it's implicit in +// the mnemonic, or the mnemonic suffix being omitted because it's implicit +// in the source. +// def : InstAlias<"stosb\t$dst", (STOSB dstidx8:$dst), 0>; +// def : InstAlias<"stosw\t$dst", (STOSW dstidx16:$dst), 0>; +// def : InstAlias<"stos{l|d}\t$dst", (STOSL dstidx32:$dst), 0>; +// def : InstAlias<"stosq\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +// def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; +// def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; +// def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; +// def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +// def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst), 0, "intel">; +// def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0, "intel">; +// def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0, "intel">; +// def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; + + +// scas aliases. Accept the destination being omitted because it's implicit +// in the mnemonic, or the mnemonic suffix being omitted because it's implicit +// in the destination. +// def : InstAlias<"scasb\t$dst", (SCASB dstidx8:$dst), 0>; +// def : InstAlias<"scasw\t$dst", (SCASW dstidx16:$dst), 0>; +// def : InstAlias<"scas{l|d}\t$dst", (SCASL dstidx32:$dst), 0>; +// def : InstAlias<"scasq\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +// def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; +// def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; +// def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; +// def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +// def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst), 0, "intel">; +// def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0, "intel">; +// def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0, "intel">; +// def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; + +// cmps aliases. Mnemonic suffix being omitted because it's implicit +// in the destination. +// def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0, "intel">; +// def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0, "intel">; +// def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0, "intel">; +// def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; + +// movs aliases. Mnemonic suffix being omitted because it's implicit +// in the destination. +// def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0, "intel">; +// def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0, "intel">; +// def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0, "intel">; +// def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; + +// div and idiv aliases for explicit A register. +// def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; +// def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; +// def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; +// def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; +// def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; +// def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; +// def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; +// def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; +// def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; +// def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; +// def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; +// def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; +// def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; +// def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; +// def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; +// def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; + + + +// Various unary fpstack operations default to operating on ST1. +// For example, "fxch" -> "fxch %st(1)" +// def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; +//def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; +// def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; +// def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; +// def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; +// def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; +// def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; +// def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; +// def : InstAlias<"fxch", (XCH_F ST1), 0>; +// def : InstAlias<"fcom", (COM_FST0r ST1), 0>; +// def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; +// def : InstAlias<"fcomi", (COM_FIr ST1), 0>; +// def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; +// def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; +// def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; +// def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; +// def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; + +/* +// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. +// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate +// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with +// gas. +//multiclass FpUnaryAlias { + def : InstAlias; + def : InstAlias; +} + +defm : FpUnaryAlias<"fadd", ADD_FST0r>; +defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; +defm : FpUnaryAlias<"fsub", SUB_FST0r>; +defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; +defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; +defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; +defm : FpUnaryAlias<"fmul", MUL_FST0r>; +defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; +defm : FpUnaryAlias<"fdiv", DIV_FST0r>; +defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; +defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; +defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; +defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; +defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; +defm : FpUnaryAlias<"fcompi", COM_FIPr>; +defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; +*/ + + +// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they +// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, +// solely because gas supports it. +// def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; +// def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; +// def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; +// def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; +// def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; +// def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; + +// def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; + +// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but +// this is compatible with what GAS does. +// def : InstAlias<"lcall\t$seg : $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; +// def : InstAlias<"ljmp\t$seg : $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; +// def : InstAlias<"lcall\t{*}$dst", (FARCALL32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; +// def : InstAlias<"ljmp\t{*}$dst", (FARJMP32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; +// def : InstAlias<"lcall\t$seg : $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; +// def : InstAlias<"ljmp\t$seg : $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; +// def : InstAlias<"lcall\t{*}$dst", (FARCALL16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; +// def : InstAlias<"ljmp\t{*}$dst", (FARJMP16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; + +// def : InstAlias<"jmp\t{*}$dst", (JMP64m i64mem:$dst), 0, "att">, Requires<[In64BitMode]>; +// def : InstAlias<"jmp\t{*}$dst", (JMP32m i32mem:$dst), 0, "att">, Requires<[In32BitMode]>; +// def : InstAlias<"jmp\t{*}$dst", (JMP16m i16mem:$dst), 0, "att">, Requires<[In16BitMode]>; + + +// "imul , B" is an alias for "imul , B, B". +// def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; +// def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; +// def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; +// def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; +// def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; +// def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; + +// ins aliases. Accept the mnemonic suffix being omitted because it's implicit +// in the destination. +// def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0, "intel">; +// def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0, "intel">; +// def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0, "intel">; + +// outs aliases. Accept the mnemonic suffix being omitted because it's implicit +// in the source. +// def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0, "intel">; +// def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0, "intel">; +// def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0, "intel">; + +// inb %dx -> inb %al, %dx +// def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; +// def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; +// def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; +// def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>; +// def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>; +// def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>; + + +// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp +// def : InstAlias<"call\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; +// def : InstAlias<"jmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; +// def : InstAlias<"call\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; +// def : InstAlias<"jmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; +// def : InstAlias<"callw\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; +// def : InstAlias<"jmpw\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; +// def : InstAlias<"calll\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; +// def : InstAlias<"jmpl\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; + +// Match 'movq , ' as an alias for movabsq. +// def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; + +// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, +// which supports this due to an old AMD documentation bug when 64-bit mode was +// created. +// def : InstAlias<"movd\t{$src, $dst|$dst, $src}", +// (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; +// def : InstAlias<"movd\t{$src, $dst|$dst, $src}", +// (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; + +// movsx aliases +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0, "att">; +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0, "att">; +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0, "att">; +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0, "att">; +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0, "att">; +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0, "att">; +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0, "att">; + +// movzx aliases +// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0, "att">; +// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0, "att">; +// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0, "att">; +// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0, "att">; +// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr8 GR64:$dst, GR8:$src), 0, "att">; +// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr16 GR64:$dst, GR16:$src), 0, "att">; +// Note: No GR32->GR64 movzx form. + +// outb %dx -> outb %al, %dx +// def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; +// def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; +// def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; +// def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>; +// def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>; +// def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>; + +// 'sldt ' can be encoded with either sldtw or sldtq with the same +// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity +// errors, since its encoding is the most compact. +// def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; + +// shld/shrd op,op -> shld op, op, CL +// def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; +// def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; +// def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; +// def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; +// def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; +// def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; + +// def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; +// def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; +// def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; +// def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; +// def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; +// def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; + +/* FIXME: This is disabled because the asm matcher is currently incapable of + * matching a fixed immediate like $1. +// "shl X, $1" is an alias for "shl X". +multiclass ShiftRotateByOneAlias { + // def : InstAlias(!strconcat(Opc, "8r1")) GR8:$op)>; + // def : InstAlias(!strconcat(Opc, "16r1")) GR16:$op)>; + // def : InstAlias(!strconcat(Opc, "32r1")) GR32:$op)>; + // def : InstAlias(!strconcat(Opc, "64r1")) GR64:$op)>; + // def : InstAlias(!strconcat(Opc, "8m1")) i8mem:$op)>; + // def : InstAlias(!strconcat(Opc, "16m1")) i16mem:$op)>; + // def : InstAlias(!strconcat(Opc, "32m1")) i32mem:$op)>; + // def : InstAlias(!strconcat(Opc, "64m1")) i64mem:$op)>; +} + +defm : ShiftRotateByOneAlias<"rcl", "RCL">; +defm : ShiftRotateByOneAlias<"rcr", "RCR">; +defm : ShiftRotateByOneAlias<"rol", "ROL">; +defm : ShiftRotateByOneAlias<"ror", "ROR">; +FIXME */ + +// test: We accept "testX , " and "testX , " as synonyms. +// def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}", +// (TEST8mr i8mem :$mem, GR8 :$val), 0>; +// def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}", +// (TEST16mr i16mem:$mem, GR16:$val), 0>; +// def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}", +// (TEST32mr i32mem:$mem, GR32:$val), 0>; +// def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}", +// (TEST64mr i64mem:$mem, GR64:$val), 0>; + +// xchg: We accept "xchgX , " and "xchgX , " as synonyms. +// def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", +// (XCHG8rm GR8 :$val, i8mem :$mem), 0>; +// def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", +// (XCHG16rm GR16:$val, i16mem:$mem), 0>; +// def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", +// (XCHG32rm GR32:$val, i32mem:$mem), 0>; +// def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", +// (XCHG64rm GR64:$val, i64mem:$mem), 0>; + +// xchg: We accept "xchgX , %eax" and "xchgX %eax, " as synonyms. +// def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; +// def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src), 0>; +// def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; + +// In 64-bit mode, xchg %eax, %eax can't be encoded with the 0x90 opcode we +// would get by default because it's defined as NOP. But xchg %eax, %eax implies +// implicit zeroing of the upper 32 bits. So alias to the longer encoding. +// def : InstAlias<"xchg{l}\t{%eax, %eax|eax, eax}", +// (XCHG32rr EAX, EAX), 0>, Requires<[In64BitMode]>; + +// xchg %rax, %rax is a nop in x86-64 and can be encoded as such. Without this +// we emit an unneeded REX.w prefix. +// def : InstAlias<"xchg{q}\t{%rax, %rax|rax, rax}", (NOOP), 0>; + +// These aliases exist to get the parser to prioritize matching 8-bit +// immediate encodings over matching the implicit ax/eax/rax encodings. By +// explicitly mentioning the A register here, these entries will be ordered +// first due to the more explicit immediate type. +// def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>; + +// def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>; + +// def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrInfo_reduce.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrInfo_reduce.td new file mode 100644 index 0000000..2237c9c --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrInfo_reduce.td @@ -0,0 +1,3582 @@ +//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 instruction set, defining the instructions, and +// properties of the instructions which are needed for code generation, machine +// code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// X86 specific DAG Nodes. +// + +def SDTIntShiftDOp: SDTypeProfile<1, 3, + [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, + SDTCisInt<0>, SDTCisInt<3>]>; + +def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; + +def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; +//def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; + +def SDTX86Cmov : SDTypeProfile<1, 4, + [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, + SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; + +// Unary and binary operator instructions that set EFLAGS as a side-effect. +def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, + [SDTCisSameAs<0, 2>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; + +def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, + [SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; + +// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS +def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, + [SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, + SDTCisVT<1, i32>, + SDTCisVT<4, i32>]>; +// RES1, RES2, FLAGS = op LHS, RHS +def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, + [SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; +def SDTX86BrCond : SDTypeProfile<0, 3, + [SDTCisVT<0, OtherVT>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; + +def SDTX86SetCC : SDTypeProfile<1, 2, + [SDTCisVT<0, i8>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; +def SDTX86SetCC_C : SDTypeProfile<1, 2, + [SDTCisInt<0>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; + +def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; + +def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; + +def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, + SDTCisVT<2, i8>]>; +def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; +def SDTX86caspairSaveEbx8 : SDTypeProfile<1, 3, + [SDTCisVT<0, i32>, SDTCisPtrTy<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; +def SDTX86caspairSaveRbx16 : SDTypeProfile<1, 3, + [SDTCisVT<0, i64>, SDTCisPtrTy<1>, + SDTCisVT<2, i64>, SDTCisVT<3, i64>]>; + +def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, + SDTCisPtrTy<1>, + SDTCisInt<2>]>; + +def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, + SDTCisPtrTy<1>]>; + +def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; + +def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; +def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; + +def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, + SDTCisVT<1, iPTR>, + SDTCisVT<2, iPTR>]>; + +def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, + SDTCisPtrTy<1>, + SDTCisVT<2, i32>, + SDTCisVT<3, i8>, + SDTCisVT<4, i32>]>; + +def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; + +def SDTX86Void : SDTypeProfile<0, 0, []>; + +def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; + +def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86WIN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; + +def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; + +def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; + +def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, + [SDNPHasChain,SDNPSideEffect]>; +def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, + [SDNPHasChain]>; + + +def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; +def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; +def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; +def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; + +def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; +def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; + +def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; +def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, + [SDNPHasChain]>; +def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; +def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; + +def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; + +def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, + [SDNPHasChain, SDNPSideEffect]>; + +def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, + [SDNPHasChain, SDNPSideEffect]>; + +def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas8save_ebx : SDNode<"X86ISD::LCMPXCHG8_SAVE_EBX_DAG", + SDTX86caspairSaveEbx8, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, + SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; +def X86cas16save_rbx : SDNode<"X86ISD::LCMPXCHG16_SAVE_RBX_DAG", + SDTX86caspairSaveRbx16, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, + SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; + +def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; +def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, + [SDNPHasChain, SDNPOptInGlue]>; + +def X86vastart_save_xmm_regs : + SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", + SDT_X86VASTART_SAVE_XMM_REGS, + [SDNPHasChain, SDNPVariadic]>; +def X86vaarg64 : + SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, + SDNPMemOperand]>; +def X86callseq_start : + SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, + [SDNPHasChain, SDNPOutGlue]>; +def X86callseq_end : + SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, + SDNPVariadic]>; + +def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, + SDNPVariadic]>; +def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind, + [SDNPHasChain]>; + +def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; +def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad]>; + +def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; +def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; +def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; + +def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; +def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; + +def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", + SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, + SDTCisInt<1>]>>; + +def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, + [SDNPHasChain]>; + +def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", + SDTypeProfile<1, 1, [SDTCisInt<0>, + SDTCisPtrTy<1>]>, + [SDNPHasChain, SDNPSideEffect]>; +def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", + SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, + [SDNPHasChain, SDNPSideEffect]>; +def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH", + SDTypeProfile<0, 0, []>, + [SDNPHasChain, SDNPSideEffect]>; + +def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; + +def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; +def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, + [SDNPCommutative]>; +def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; +def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; + +def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; +def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; +def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, + [SDNPCommutative]>; + +def X86lock_add : SDNode<"X86ISD::LADD", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_sub : SDNode<"X86ISD::LSUB", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_or : SDNode<"X86ISD::LOR", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; + +def X86lock_inc : SDNode<"X86ISD::LINC", SDTLockUnaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_dec : SDNode<"X86ISD::LDEC", SDTLockUnaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; + +def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; + +def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; + +def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDT_X86WIN_ALLOCA, + [SDNPHasChain, SDNPOutGlue]>; + +def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, + [SDNPHasChain]>; + +def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86lwpins : SDNode<"X86ISD::LWPINS", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; + +def X86umwait : SDNode<"X86ISD::UMWAIT", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +def X86tpause : SDNode<"X86ISD::TPAUSE", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +//===----------------------------------------------------------------------===// +// X86 Operand Definitions. +// + +// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for +// the index operand of an address, to conform to x86 encoding restrictions. +def ptr_rc_nosp : PointerLikeRegClass<1>; + +// *mem - Operand definitions for the funky X86 addressing mode operands. +// +def X86MemAsmOperand : AsmOperandClass { + let Name = "Mem"; +} +let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in { + def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } + def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } + def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } + def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } + def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } + def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } + def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } + def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } + // Gather mem operands + def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; } + def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; } + def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; } + def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; } + def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; } + + def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; } + def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; } + def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; } + def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; } + def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; } + def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; } + def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; } + def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; } +} + +def X86AbsMemAsmOperand : AsmOperandClass { + let Name = "AbsMem"; + let SuperClasses = [X86MemAsmOperand]; +} + +class X86MemOperand : Operand { + let PrintMethod = printMethod; + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); + let ParserMatchClass = parserMatchClass; + let OperandType = "OPERAND_MEMORY"; +} + +// Gather mem operands +class X86VMemOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG); +} + +def anymem : X86MemOperand<"printanymem">; + +// FIXME: Right now we allow any size during parsing, but we might want to +// restrict to only unsized memory. +def opaquemem : X86MemOperand<"printopaquemem">; + +def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>; +def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>; +def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>; +def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>; +def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>; +def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>; +def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>; +def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>; +def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>; +def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>; +def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>; +def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>; +def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>; + +def v512mem : X86VMemOperand; + +// Gather mem operands +def vx64mem : X86VMemOperand; +def vx128mem : X86VMemOperand; +def vx256mem : X86VMemOperand; +def vy128mem : X86VMemOperand; +def vy256mem : X86VMemOperand; + +def vx64xmem : X86VMemOperand; +def vx128xmem : X86VMemOperand; +def vx256xmem : X86VMemOperand; +def vy128xmem : X86VMemOperand; +def vy256xmem : X86VMemOperand; +def vy512xmem : X86VMemOperand; +def vz256mem : X86VMemOperand; +def vz512mem : X86VMemOperand; + +// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead +// of a plain GPR, so that it doesn't potentially require a REX prefix. +def ptr_rc_norex : PointerLikeRegClass<2>; +def ptr_rc_norex_nosp : PointerLikeRegClass<3>; + +def i8mem_NOREX : Operand { + let PrintMethod = "printi8mem"; + let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, + SEGMENT_REG); + let ParserMatchClass = X86Mem8AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +// GPRs available for tailcall. +// It represents GR32_TC, GR64_TC or GR64_TCW64. +def ptr_rc_tailcall : PointerLikeRegClass<4>; + +// Special i32mem for addresses of load folding tail calls. These are not +// allowed to use callee-saved registers since they must be scheduled +// after callee-saved register are popped. +def i32mem_TC : Operand { + let PrintMethod = "printi32mem"; + let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, + i32imm, SEGMENT_REG); + let ParserMatchClass = X86Mem32AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +// Special i64mem for addresses of load folding tail calls. These are not +// allowed to use callee-saved registers since they must be scheduled +// after callee-saved register are popped. +def i64mem_TC : Operand { + let PrintMethod = "printi64mem"; + let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, + ptr_rc_tailcall, i32imm, SEGMENT_REG); + let ParserMatchClass = X86Mem64AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +let OperandType = "OPERAND_PCREL", + ParserMatchClass = X86AbsMemAsmOperand, + PrintMethod = "printPCRelImm" in { +def i32imm_pcrel : Operand; +def i16imm_pcrel : Operand; + +// Branch targets have OtherVT type and print as pc-relative values. +def brtarget : Operand; +def brtarget8 : Operand; + +} + +// Special parser to detect 16-bit mode to select 16-bit displacement. +def X86AbsMem16AsmOperand : AsmOperandClass { + let Name = "AbsMem16"; + let RenderMethod = "addAbsMemOperands"; + let SuperClasses = [X86AbsMemAsmOperand]; +} + +// Branch targets have OtherVT type and print as pc-relative values. +let OperandType = "OPERAND_PCREL", + PrintMethod = "printPCRelImm" in { +let ParserMatchClass = X86AbsMem16AsmOperand in + def brtarget16 : Operand; +let ParserMatchClass = X86AbsMemAsmOperand in + def brtarget32 : Operand; +} + +let RenderMethod = "addSrcIdxOperands" in { + def X86SrcIdx8Operand : AsmOperandClass { + let Name = "SrcIdx8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86SrcIdx16Operand : AsmOperandClass { + let Name = "SrcIdx16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86SrcIdx32Operand : AsmOperandClass { + let Name = "SrcIdx32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86SrcIdx64Operand : AsmOperandClass { + let Name = "SrcIdx64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addSrcIdxOperands" + +let RenderMethod = "addDstIdxOperands" in { + def X86DstIdx8Operand : AsmOperandClass { + let Name = "DstIdx8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86DstIdx16Operand : AsmOperandClass { + let Name = "DstIdx16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86DstIdx32Operand : AsmOperandClass { + let Name = "DstIdx32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86DstIdx64Operand : AsmOperandClass { + let Name = "DstIdx64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addDstIdxOperands" + +let RenderMethod = "addMemOffsOperands" in { + def X86MemOffs16_8AsmOperand : AsmOperandClass { + let Name = "MemOffs16_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs16_16AsmOperand : AsmOperandClass { + let Name = "MemOffs16_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs16_32AsmOperand : AsmOperandClass { + let Name = "MemOffs16_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs32_8AsmOperand : AsmOperandClass { + let Name = "MemOffs32_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs32_16AsmOperand : AsmOperandClass { + let Name = "MemOffs32_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs32_32AsmOperand : AsmOperandClass { + let Name = "MemOffs32_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs32_64AsmOperand : AsmOperandClass { + let Name = "MemOffs32_64"; + let SuperClasses = [X86Mem64AsmOperand]; + } + def X86MemOffs64_8AsmOperand : AsmOperandClass { + let Name = "MemOffs64_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs64_16AsmOperand : AsmOperandClass { + let Name = "MemOffs64_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs64_32AsmOperand : AsmOperandClass { + let Name = "MemOffs64_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs64_64AsmOperand : AsmOperandClass { + let Name = "MemOffs64_64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addMemOffsOperands" + +class X86SrcIdxOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc, SEGMENT_REG); +} + +class X86DstIdxOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc); +} + +def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; +def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; +def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; +def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; +def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; +def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; +def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; +def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; + +class X86MemOffsOperand + : X86MemOperand { + let MIOperandInfo = (ops immOperand, SEGMENT_REG); +} + +def offset16_8 : X86MemOffsOperand; +def offset16_16 : X86MemOffsOperand; +def offset16_32 : X86MemOffsOperand; +def offset32_8 : X86MemOffsOperand; +def offset32_16 : X86MemOffsOperand; +def offset32_32 : X86MemOffsOperand; +def offset32_64 : X86MemOffsOperand; +def offset64_8 : X86MemOffsOperand; +def offset64_16 : X86MemOffsOperand; +def offset64_32 : X86MemOffsOperand; +def offset64_64 : X86MemOffsOperand; + +def SSECC : Operand { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def AVXCC : Operand { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def AVX512ICC : Operand { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def XOPCC : Operand { + let PrintMethod = "printXOPCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +class ImmSExtAsmOperandClass : AsmOperandClass { + let SuperClasses = [ImmAsmOperand]; + let RenderMethod = "addImmOperands"; +} + +def X86GR32orGR64AsmOperand : AsmOperandClass { + let Name = "GR32orGR64"; +} + +def GR32orGR64 : RegisterOperand { + let ParserMatchClass = X86GR32orGR64AsmOperand; +} +def AVX512RCOperand : AsmOperandClass { + let Name = "AVX512RC"; +} +def AVX512RC : Operand { + let PrintMethod = "printRoundingControl"; + let OperandType = "OPERAND_IMMEDIATE"; + let ParserMatchClass = AVX512RCOperand; +} + +// Sign-extended immediate classes. We don't need to define the full lattice +// here because there is no instruction with an ambiguity between ImmSExti64i32 +// and ImmSExti32i8. +// +// The strange ranges come from the fact that the assembler always works with +// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" +// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). + +// [0, 0x7FFFFFFF] | +// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] +def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti64i32"; +} + +// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti16i8"; + let SuperClasses = [ImmSExti64i32AsmOperand]; +} + +// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti32i8"; +} + +// [0, 0x0000007F] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti64i8"; + let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, + ImmSExti64i32AsmOperand]; +} + +// Unsigned immediate used by SSE/AVX instructions +// [0, 0xFF] +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmUnsignedi8AsmOperand : AsmOperandClass { + let Name = "ImmUnsignedi8"; + let RenderMethod = "addImmOperands"; +} + +// A couple of more descriptive operand definitions. +// 16-bits but only 8 bits are significant. +def i16i8imm : Operand { + let ParserMatchClass = ImmSExti16i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} +// 32-bits but only 8 bits are significant. +def i32i8imm : Operand { + let ParserMatchClass = ImmSExti32i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 32 bits are significant. +def i64i32imm : Operand { + let ParserMatchClass = ImmSExti64i32AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 8 bits are significant. +def i64i8imm : Operand { + let ParserMatchClass = ImmSExti64i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// Unsigned 8-bit immediate used by SSE/AVX instructions. +def u8imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 32-bit immediate but only 8-bits are significant and they are unsigned. +// Used by some SSE/AVX instructions that use intrinsics. +def i32u8imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 32 bits are significant, and those bits are treated as being +// pc relative. +def i64i32imm_pcrel : Operand { + let PrintMethod = "printPCRelImm"; + let ParserMatchClass = X86AbsMemAsmOperand; + let OperandType = "OPERAND_PCREL"; +} + +def lea64_32mem : Operand { + let PrintMethod = "printanymem"; + let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); + let ParserMatchClass = X86MemAsmOperand; +} + +// Memory operands that use 64-bit pointers in both ILP32 and LP64. +def lea64mem : Operand { + let PrintMethod = "printanymem"; + let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); + let ParserMatchClass = X86MemAsmOperand; +} + + +//===----------------------------------------------------------------------===// +// X86 Complex Pattern Definitions. +// + +// Define X86-specific addressing mode. +def addr : ComplexPattern; +def lea32addr : ComplexPattern; +// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. +def lea64_32addr : ComplexPattern; + +def tls32addr : ComplexPattern; + +def tls32baseaddr : ComplexPattern; + +def lea64addr : ComplexPattern; + +def tls64addr : ComplexPattern; + +def tls64baseaddr : ComplexPattern; + +def vectoraddr : ComplexPattern; + +// A relocatable immediate is either an immediate operand or an operand that can +// be relocated by the linker to an immediate, such as a regular symbol in +// non-PIC code. +def relocImm : ComplexPattern; + +//===----------------------------------------------------------------------===// +// X86 Instruction Predicate Definitions. +def TruePredicate : Predicate<"true">; + +def HasCMov : Predicate<"Subtarget->hasCMov()">; +def NoCMov : Predicate<"!Subtarget->hasCMov()">; + +def HasMMX : Predicate<"Subtarget->hasMMX()">; +def Has3DNow : Predicate<"Subtarget->has3DNow()">; +def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; +def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; +def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; +def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; +def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; +def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; +def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; +def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; +def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; +def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; +def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; +def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; +def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; +def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; +def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; +def NoAVX : Predicate<"!Subtarget->hasAVX()">; +def HasAVX : Predicate<"Subtarget->hasAVX()">; +def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; +def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; +def HasAVX512 : Predicate<"Subtarget->hasAVX512()">; +def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; +def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; +def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; +def HasCDI : Predicate<"Subtarget->hasCDI()">; +def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">; +def HasPFI : Predicate<"Subtarget->hasPFI()">; +def HasERI : Predicate<"Subtarget->hasERI()">; +def HasDQI : Predicate<"Subtarget->hasDQI()">; +def NoDQI : Predicate<"!Subtarget->hasDQI()">; +def HasBWI : Predicate<"Subtarget->hasBWI()">; +def NoBWI : Predicate<"!Subtarget->hasBWI()">; +def HasVLX : Predicate<"Subtarget->hasVLX()">; +def NoVLX : Predicate<"!Subtarget->hasVLX()">; +def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">; +def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">; +def PKU : Predicate<"Subtarget->hasPKU()">; +def HasVNNI : Predicate<"Subtarget->hasVNNI()">; + +def HasBITALG : Predicate<"Subtarget->hasBITALG()">; +def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; +def HasAES : Predicate<"Subtarget->hasAES()">; +def HasVAES : Predicate<"Subtarget->hasVAES()">; +def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">; +def HasFXSR : Predicate<"Subtarget->hasFXSR()">; +def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">; +def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">; +def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">; +def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">; +def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; +def NoVLX_Or_NoVPCLMULQDQ : + Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()">; +def HasVPCLMULQDQ : Predicate<"Subtarget->hasVPCLMULQDQ()">; +def HasGFNI : Predicate<"Subtarget->hasGFNI()">; +def HasFMA : Predicate<"Subtarget->hasFMA()">; +def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; +def NoFMA4 : Predicate<"!Subtarget->hasFMA4()">; +def HasXOP : Predicate<"Subtarget->hasXOP()">; +def HasTBM : Predicate<"Subtarget->hasTBM()">; +def NoTBM : Predicate<"!Subtarget->hasTBM()">; +def HasLWP : Predicate<"Subtarget->hasLWP()">; +def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; +def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; +def HasF16C : Predicate<"Subtarget->hasF16C()">; +def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; +def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; +def HasBMI : Predicate<"Subtarget->hasBMI()">; +def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; +def NoBMI2 : Predicate<"!Subtarget->hasBMI2()">; +def HasVBMI : Predicate<"Subtarget->hasVBMI()">; +def HasVBMI2 : Predicate<"Subtarget->hasVBMI2()">; +def HasIFMA : Predicate<"Subtarget->hasIFMA()">; +def HasRTM : Predicate<"Subtarget->hasRTM()">; +def HasADX : Predicate<"Subtarget->hasADX()">; +def HasSHA : Predicate<"Subtarget->hasSHA()">; +def HasSGX : Predicate<"Subtarget->hasSGX()">; +def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; +def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; +def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">; +def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">; +def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; +def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">; +def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">; +def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">; +def HasCLZERO : Predicate<"Subtarget->hasCLZERO()">; +def HasCLDEMOTE : Predicate<"Subtarget->hasCLDEMOTE()">; +def HasMOVDIRI : Predicate<"Subtarget->hasMOVDIRI()">; +def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">; +def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">; +def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; +def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; +def HasMPX : Predicate<"Subtarget->hasMPX()">; +def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; +def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; +def HasCLWB : Predicate<"Subtarget->hasCLWB()">; +def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">; +def HasRDPID : Predicate<"Subtarget->hasRDPID()">; +def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">; +def HasINVPCID : Predicate<"Subtarget->hasINVPCID()">; +def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; +def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">; +def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, + AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; +def In64BitMode : Predicate<"Subtarget->is64Bit()">, + AssemblerPredicate<"Mode64Bit", "64-bit mode">; +def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; +def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; +def In16BitMode : Predicate<"Subtarget->is16Bit()">, + AssemblerPredicate<"Mode16Bit", "16-bit mode">; +def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, + AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; +def In32BitMode : Predicate<"Subtarget->is32Bit()">, + AssemblerPredicate<"Mode32Bit", "32-bit mode">; +def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; +def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; +def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||" + "Subtarget->getFrameLowering()->hasFP(*MF)"> { + let RecomputePerFunction = 1; +} +def IsPS4 : Predicate<"Subtarget->isTargetPS4()">; +def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">; +def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; +def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; +def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; +def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; +def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" + "TM.getCodeModel() == CodeModel::Kernel">; +def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; + +// We could compute these on a per-module basis but doing so requires accessing +// the Function object through the Subtarget and objections were raised +// to that (see post-commit review comments for r301750). +let RecomputePerFunction = 1 in { + def OptForSize : Predicate<"MF->getFunction().optForSize()">; + def OptForMinSize : Predicate<"MF->getFunction().optForMinSize()">; + def OptForSpeed : Predicate<"!MF->getFunction().optForSize()">; + def UseIncDec : Predicate<"!Subtarget->slowIncDec() || " + "MF->getFunction().optForSize()">; + def NoSSE41_Or_OptForSize : Predicate<"MF->getFunction().optForSize() || " + "!Subtarget->hasSSE41()">; +} + +def CallImmAddr : Predicate<"Subtarget->isLegalToCallImmediateAddr()">; +def FavorMemIndirectCall : Predicate<"!Subtarget->slowTwoMemOps()">; +def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; +def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">; +def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">; +def HasERMSB : Predicate<"Subtarget->hasERMSB()">; +def HasMFence : Predicate<"Subtarget->hasMFence()">; +def UseRetpoline : Predicate<"Subtarget->useRetpoline()">; +def NotUseRetpoline : Predicate<"!Subtarget->useRetpoline()">; + +//===----------------------------------------------------------------------===// +// X86 Instruction Format Definitions. +// + +include "X86InstrFormats.td" + +//===----------------------------------------------------------------------===// +// Pattern fragments. +// + +// X86 specific condition code. These correspond to CondCode in +// X86InstrInfo.h. They must be kept in synch. +def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE +def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC +def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C +def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA +def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z +def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE +def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL +def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE +def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG +def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ +def X86_COND_NO : PatLeaf<(i8 10)>; +def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO +def X86_COND_NS : PatLeaf<(i8 12)>; +def X86_COND_O : PatLeaf<(i8 13)>; +def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE +def X86_COND_S : PatLeaf<(i8 15)>; + +def i16immSExt8 : ImmLeaf(Imm); }]>; +def i32immSExt8 : ImmLeaf(Imm); }]>; +def i64immSExt8 : ImmLeaf(Imm); }]>; +def i64immSExt32 : ImmLeaf(Imm); }]>; + +// FIXME: Ideally we would just replace the above i*immSExt* matchers with +// relocImm-based matchers, but then FastISel would be unable to use them. +def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{ + return isSExtRelocImm<8>(N); +}]>; +def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{ + return isSExtRelocImm<32>(N); +}]>; + +// If we have multiple users of an immediate, it's much smaller to reuse +// the register, rather than encode the immediate in every instruction. +// This has the risk of increasing register pressure from stretched live +// ranges, however, the immediates should be trivial to rematerialize by +// the RA in the event of high register pressure. +// TODO : This is currently enabled for stores and binary ops. There are more +// cases for which this can be enabled, though this catches the bulk of the +// issues. +// TODO2 : This should really also be enabled under O2, but there's currently +// an issue with RA where we don't pull the constants into their users +// when we rematerialize them. I'll follow-up on enabling O2 after we fix that +// issue. +// TODO3 : This is currently limited to single basic blocks (DAG creation +// pulls block immediates to the top and merges them if necessary). +// Eventually, it would be nice to allow ConstantHoisting to merge constants +// globally for potentially added savings. +// +def imm8_su : PatLeaf<(i8 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def imm16_su : PatLeaf<(i16 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def imm32_su : PatLeaf<(i32 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64immSExt32_su : PatLeaf<(i64immSExt32), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i32immSExt8_su : PatLeaf<(i32immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64immSExt8_su : PatLeaf<(i64immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit +// unsigned field. +def i64immZExt32 : ImmLeaf(Imm); }]>; + +def i64immZExt32SExt8 : ImmLeaf(Imm) && isInt<8>(static_cast(Imm)); +}]>; + +// Helper fragments for loads. + +// It's safe to fold a zextload/extload from i1 as a regular i8 load. The +// upper bits are guaranteed to be zero and we were going to emit a MOV8rm +// which might get folded during peephole anyway. +def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD || + ExtType == ISD::ZEXTLOAD; +}]>; + +// It's always safe to treat a anyext i16 load as a i32 load if the i16 is +// known to be 32-bit aligned or better. Ditto for i8 to i16. +def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + if (ExtType == ISD::NON_EXTLOAD) + return true; + if (ExtType == ISD::EXTLOAD) + return LD->getAlignment() >= 2 && !LD->isVolatile(); + return false; +}]>; + +def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + if (ExtType == ISD::NON_EXTLOAD) + return true; + if (ExtType == ISD::EXTLOAD) + return LD->getAlignment() >= 4 && !LD->isVolatile(); + return false; +}]>; + +def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; +def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; +def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; +def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; +def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>; +def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ + LoadSDNode *Ld = cast(N); + return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); +}]>; +def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ + LoadSDNode *Ld = cast(N); + return Subtarget->hasSSEUnalignedMem() || + Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); +}]>; + +def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; +def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; +def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; +def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; +def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; +def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; + +def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; +def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; +def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; +def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; +def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; +def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; +def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; +def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; +def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; +def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; + +def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; +def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; +def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; +def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; +def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; +def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; +def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; +def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; +def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; +def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; + + +// An 'and' node with a single use. +def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ + return N->hasOneUse(); +}]>; +// An 'srl' node with a single use. +def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ + return N->hasOneUse(); +}]>; +// An 'trunc' node with a single use. +def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ + return N->hasOneUse(); +}]>; + +//===----------------------------------------------------------------------===// +// Instruction list. +// + +// Nop +let hasSideEffects = 0, SchedRW = [WriteNop] in { + def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; + def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; + def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; + def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero), + "nop{q}\t$zero", []>, TB, NotMemoryFoldable, + Requires<[In64BitMode]>; + // Also allow register so we can assemble/disassemble + def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; + def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; + def NOOPQr : RI<0x1f, MRMXr, (outs), (ins GR64:$zero), + "nop{q}\t$zero", []>, TB, NotMemoryFoldable, + Requires<[In64BitMode]>; + def NOOPW_19 : I<0x19, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOPL_19 : I<0x19, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + //def NOOPW_1a : I<0x1a, MRMXm, (outs), (ins i16mem:$zero), + // "nop{w}\t$zero", []>, TB, OpSize16; + //def NOOPL_1a : I<0x1a, MRMXm, (outs), (ins i32mem:$zero), + // "nop{l}\t$zero", []>, TB, OpSize32; + //def NOOPW_1b : I<0x1b, MRMXm, (outs), (ins i16mem:$zero), + // "nop{w}\t$zero", []>, TB, OpSize16; + //def NOOPL_1b : I<0x1b, MRMXm, (outs), (ins i32mem:$zero), + // "nop{l}\t$zero", []>, TB, OpSize32; + def NOOPW_1c : I<0x1c, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + //def NOOPL_1c : I<0x1c, MRMXm, (outs), (ins i32mem:$zero), + // "nop{l}\t$zero", []>, TB, OpSize32; + def NOOPW_1d : I<0x1d, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOPL_1d : I<0x1d, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + def NOOPW_1e : I<0x1e, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOPL_1e : I<0x1e, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m4 : I<0x18, MRM4m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m4 : I<0x18, MRM4m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r4 : I<0x18, MRM4r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r4 : I<0x18, MRM4r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m5 : I<0x18, MRM5m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m5 : I<0x18, MRM5m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r5 : I<0x18, MRM5r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r5 : I<0x18, MRM5r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m6 : I<0x18, MRM6m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m6 : I<0x18, MRM6m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r6 : I<0x18, MRM6r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r6 : I<0x18, MRM6r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m7 : I<0x18, MRM7m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m7 : I<0x18, MRM7m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r7 : I<0x18, MRM7r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r7 : I<0x18, MRM7r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; +} + + +// Constructing a stack frame. +def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), + "enter\t$len, $lvl", []>, Sched<[WriteMicrocoded]>; + +let SchedRW = [WriteALU] in { +let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in +def LEAVE : I<0xC9, RawFrm, (outs), (ins), "leave", []>, + Requires<[Not64BitMode]>; + +let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in +def LEAVE64 : I<0xC9, RawFrm, (outs), (ins), "leave", []>, + Requires<[In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Miscellaneous Instructions. +// + +/* +let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1, + SchedRW = [WriteSystem] in + def Int_eh_sjlj_setup_dispatch + : PseudoI<(outs), (ins), [(X86eh_sjlj_setup_dispatch)]>; +*/ + +let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { +let mayLoad = 1, SchedRW = [WriteLoad] in { +def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, + OpSize16; +def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, + OpSize32, Requires<[Not64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, + OpSize16, NotMemoryFoldable; +def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, + OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 +} // mayLoad, SchedRW +let mayStore = 1, mayLoad = 1, SchedRW = [WriteRMW] in { +def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>, + OpSize16; +def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>, + OpSize32, Requires<[Not64BitMode]>; +} // mayStore, mayLoad, WriteRMW + +let mayStore = 1, SchedRW = [WriteStore] in { +def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, + OpSize16; +def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, + OpSize32, Requires<[Not64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, + OpSize16, NotMemoryFoldable; +def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, + OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 + +def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), + "push{w}\t$imm", []>, OpSize16; +def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), + "push{w}\t$imm", []>, OpSize16; + +def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), + "push{l}\t$imm", []>, OpSize32, + Requires<[Not64BitMode]>; +def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), + "push{l}\t$imm", []>, OpSize32, + Requires<[Not64BitMode]>; +} // mayStore, SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { +def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>, + OpSize16; +def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>, + OpSize32, Requires<[Not64BitMode]>; +} // mayLoad, mayStore, SchedRW + +} + +/* +let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, + SchedRW = [WriteRMW], Defs = [ESP] in { + let Uses = [ESP] in + def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins), + [(set GR32:$dst, (int_x86_flags_read_u32))]>, + Requires<[Not64BitMode]>; + + let Uses = [RSP] in + def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins), + [(set GR64:$dst, (int_x86_flags_read_u64))]>, + Requires<[In64BitMode]>; +} + +let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, + SchedRW = [WriteRMW] in { + let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in + def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src), + [(int_x86_flags_write_u32 GR32:$src)]>, + Requires<[Not64BitMode]>; + + let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in + def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src), + [(int_x86_flags_write_u64 GR64:$src)]>, + Requires<[In64BitMode]>; +} +*/ + +let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0, + SchedRW = [WriteLoad] in { +def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize16; +def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, OpSize32, + Requires<[Not64BitMode]>; +} + +let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0, + SchedRW = [WriteStore] in { +def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize16; +def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, OpSize32, + Requires<[Not64BitMode]>; +} + +let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { +let mayLoad = 1, SchedRW = [WriteLoad] in { +def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 +} // mayLoad, SchedRW +let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in +def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>, + OpSize32, Requires<[In64BitMode]>; +let mayStore = 1, SchedRW = [WriteStore] in { +def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 +} // mayStore, SchedRW +let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { +def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>, + OpSize32, Requires<[In64BitMode]>; +} // mayLoad, mayStore, SchedRW +} + +let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, + SchedRW = [WriteStore] in { +def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), + "push{q}\t$imm", []>, OpSize32, + Requires<[In64BitMode]>; +def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), + "push{q}\t$imm", []>, OpSize32, + Requires<[In64BitMode]>; +} + +let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in +def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, + OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; +let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in +def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, + OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; + +let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], + mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { +def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", []>, + OpSize32, Requires<[Not64BitMode]>; +def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", []>, + OpSize16, Requires<[Not64BitMode]>; +} +let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], + mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { +def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", []>, + OpSize32, Requires<[Not64BitMode]>; +def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", []>, + OpSize16, Requires<[Not64BitMode]>; +} + +let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in { +// This instruction is a consequence of BSWAP32r observing operand size. The +// encoding is valid, but the behavior is undefined. +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in +def BSWAP16r_BAD : I<0xC8, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), + "bswap{w}\t$dst", []>, OpSize16, TB; +// GR32 = bswap GR32 +def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), + "bswap{l}\t$dst", + [(set GR32:$dst, (bswap GR32:$src))]>, OpSize32, TB; + +let SchedRW = [WriteBSWAP64] in +def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), + "bswap{q}\t$dst", + [(set GR64:$dst, (bswap GR64:$src))]>, TB; +} // Constraints = "$src = $dst", SchedRW + +// Bit scan instructions. +let Defs = [EFLAGS] in { +def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "bsf{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, + PS, OpSize16, Sched<[WriteBSF]>; +def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "bsf{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, + PS, OpSize16, Sched<[WriteBSFLd]>; +def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "bsf{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, + PS, OpSize32, Sched<[WriteBSF]>; +def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "bsf{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, + PS, OpSize32, Sched<[WriteBSFLd]>; +def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "bsf{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, + PS, Sched<[WriteBSF]>; +def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "bsf{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, + PS, Sched<[WriteBSFLd]>; + +def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "bsr{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, + PS, OpSize16, Sched<[WriteBSR]>; +def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "bsr{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, + PS, OpSize16, Sched<[WriteBSRLd]>; +def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "bsr{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, + PS, OpSize32, Sched<[WriteBSR]>; +def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "bsr{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, + PS, OpSize32, Sched<[WriteBSRLd]>; +def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "bsr{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, + PS, Sched<[WriteBSR]>; +def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "bsr{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, + PS, Sched<[WriteBSRLd]>; +} // Defs = [EFLAGS] + +let SchedRW = [WriteMicrocoded] in { +let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in { +def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), + "movsb\t{$src, $dst|$dst, $src}", []>; +def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), + "movsw\t{$src, $dst|$dst, $src}", []>, OpSize16; +def MOVSL : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), + "movs{l|d}\t{$src, $dst|$dst, $src}", []>, OpSize32; +def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), + "movsq\t{$src, $dst|$dst, $src}", []>, + Requires<[In64BitMode]>; +} + +let Defs = [EDI], Uses = [AL,EDI,DF] in +def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst), + "stosb\t{%al, $dst|$dst, al}", []>; +let Defs = [EDI], Uses = [AX,EDI,DF] in +def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst), + "stosw\t{%ax, $dst|$dst, ax}", []>, OpSize16; +let Defs = [EDI], Uses = [EAX,EDI,DF] in +def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst), + "stos{l|d}\t{%eax, $dst|$dst, eax}", []>, OpSize32; +let Defs = [RDI], Uses = [RAX,RDI,DF] in +def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst), + "stosq\t{%rax, $dst|$dst, rax}", []>, + Requires<[In64BitMode]>; + +let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in +def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), + "scasb\t{$dst, %al|al, $dst}", []>; +let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in +def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), + "scasw\t{$dst, %ax|ax, $dst}", []>, OpSize16; +let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in +def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), + "scas{l|d}\t{$dst, %eax|eax, $dst}", []>, OpSize32; +let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in +def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), + "scasq\t{$dst, %rax|rax, $dst}", []>, + Requires<[In64BitMode]>; + +let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in { +def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), + "cmpsb\t{$dst, $src|$src, $dst}", []>; +def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), + "cmpsw\t{$dst, $src|$src, $dst}", []>, OpSize16; +def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), + "cmps{l|d}\t{$dst, $src|$src, $dst}", []>, OpSize32; +def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), + "cmpsq\t{$dst, $src|$src, $dst}", []>, + Requires<[In64BitMode]>; +} +} // SchedRW + +//===----------------------------------------------------------------------===// +// Move Instructions. +// +let SchedRW = [WriteMove] in { +let hasSideEffects = 0, isMoveReg = 1 in { +def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>; +def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; +def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; +def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>; +} + +let isReMaterializable = 1, isAsCheapAsAMove = 1 in { +def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(set GR8:$dst, imm:$src)]>; +def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, imm:$src)]>, OpSize16; +def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, relocImm:$src)]>, OpSize32; +def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, i64immSExt32:$src)]>; +} +let isReMaterializable = 1 in { +def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), + "movabs{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, relocImm:$src)]>; +} + +// Longer forms that use a ModR/M byte. Needed for disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { +def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOV8ri">; +def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, + FoldGenData<"MOV16ri">; +def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, + FoldGenData<"MOV32ri">; +} +} // SchedRW + +let SchedRW = [WriteStore] in { +def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(store (i8 imm8_su:$src), addr:$dst)]>; +def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(store (i16 imm16_su:$src), addr:$dst)]>, OpSize16; +def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(store (i32 imm32_su:$src), addr:$dst)]>, OpSize32; +def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(store i64immSExt32_su:$src, addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW + +let hasSideEffects = 0 in { + +/// Memory offset versions of moves. The immediate is an address mode sized +/// offset from the segment base. +let SchedRW = [WriteALU] in { +let mayLoad = 1 in { +let Defs = [AL] in +def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), + "mov{b}\t{$src, %al|al, $src}", []>, + AdSize32; +let Defs = [AX] in +def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), + "mov{w}\t{$src, %ax|ax, $src}", []>, + OpSize16, AdSize32; +let Defs = [EAX] in +def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), + "mov{l}\t{$src, %eax|eax, $src}", []>, + OpSize32, AdSize32; +let Defs = [RAX] in +def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), + "mov{q}\t{$src, %rax|rax, $src}", []>, + AdSize32; + +let Defs = [AL] in +def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), + "mov{b}\t{$src, %al|al, $src}", []>, AdSize16; +let Defs = [AX] in +def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), + "mov{w}\t{$src, %ax|ax, $src}", []>, + OpSize16, AdSize16; +let Defs = [EAX] in +def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), + "mov{l}\t{$src, %eax|eax, $src}", []>, + AdSize16, OpSize32; +} // mayLoad +let mayStore = 1 in { +let Uses = [AL] in +def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst), + "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize32; +let Uses = [AX] in +def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_16:$dst), + "mov{w}\t{%ax, $dst|$dst, ax}", []>, + OpSize16, AdSize32; +let Uses = [EAX] in +def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_32:$dst), + "mov{l}\t{%eax, $dst|$dst, eax}", []>, + OpSize32, AdSize32; +let Uses = [RAX] in +def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs), (ins offset32_64:$dst), + "mov{q}\t{%rax, $dst|$dst, rax}", []>, + AdSize32; + +let Uses = [AL] in +def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs), (ins offset16_8:$dst), + "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize16; +let Uses = [AX] in +def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_16:$dst), + "mov{w}\t{%ax, $dst|$dst, ax}", []>, + OpSize16, AdSize16; +let Uses = [EAX] in +def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst), + "mov{l}\t{%eax, $dst|$dst, eax}", []>, + OpSize32, AdSize16; +} // mayStore + +// These forms all have full 64-bit absolute addresses in their instructions +// and use the movabs mnemonic to indicate this specific form. +let mayLoad = 1 in { +let Defs = [AL] in +def MOV8ao64 : Ii64<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), + "movabs{b}\t{$src, %al|al, $src}", []>, + AdSize64; +let Defs = [AX] in +def MOV16ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), + "movabs{w}\t{$src, %ax|ax, $src}", []>, + OpSize16, AdSize64; +let Defs = [EAX] in +def MOV32ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), + "movabs{l}\t{$src, %eax|eax, $src}", []>, + OpSize32, AdSize64; +let Defs = [RAX] in +def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), + "movabs{q}\t{$src, %rax|rax, $src}", []>, + AdSize64; +} // mayLoad + +let mayStore = 1 in { +let Uses = [AL] in +def MOV8o64a : Ii64<0xA2, RawFrmMemOffs, (outs), (ins offset64_8:$dst), + "movabs{b}\t{%al, $dst|$dst, al}", []>, + AdSize64; +let Uses = [AX] in +def MOV16o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_16:$dst), + "movabs{w}\t{%ax, $dst|$dst, ax}", []>, + OpSize16, AdSize64; +let Uses = [EAX] in +def MOV32o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_32:$dst), + "movabs{l}\t{%eax, $dst|$dst, eax}", []>, + OpSize32, AdSize64; +let Uses = [RAX] in +def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst), + "movabs{q}\t{%rax, $dst|$dst, rax}", []>, + AdSize64; +} // mayStore +} // SchedRW +} // hasSideEffects = 0 + +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, + SchedRW = [WriteMove], isMoveReg = 1 in { +def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOV8rr">; +def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, + FoldGenData<"MOV16rr">; +def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, + FoldGenData<"MOV32rr">; +def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOV64rr">; +} + +// Reversed version with ".s" suffix for GAS compatibility. +//// def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}", +// (MOV8rr_REV GR8:$dst, GR8:$src), 0>; +//// def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}", +// (MOV16rr_REV GR16:$dst, GR16:$src), 0>; +//// def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}", +// (MOV32rr_REV GR32:$dst, GR32:$src), 0>; +//// def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}", +// (MOV64rr_REV GR64:$dst, GR64:$src), 0>; +//// def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">; +//// def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">; +//// def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">; +//// def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">; + +let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { +def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(set GR8:$dst, (loadi8 addr:$src))]>; +def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize16; +def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (loadi32 addr:$src))]>, OpSize32; +def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (load addr:$src))]>; +} + +let SchedRW = [WriteStore] in { +def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(store GR8:$src, addr:$dst)]>; +def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(store GR16:$src, addr:$dst)]>, OpSize16; +def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(store GR32:$src, addr:$dst)]>, OpSize32; +def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(store GR64:$src, addr:$dst)]>; +} // SchedRW + +// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so +// that they can be used for copying and storing h registers, which can't be +// encoded when a REX prefix is present. +let isCodeGenOnly = 1 in { +let hasSideEffects = 0, isMoveReg = 1 in +def MOV8rr_NOREX : I<0x88, MRMDestReg, + (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteMove]>; +let mayStore = 1, hasSideEffects = 0 in +def MOV8mr_NOREX : I<0x88, MRMDestMem, + (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteStore]>; +let mayLoad = 1, hasSideEffects = 0, + canFoldAsLoad = 1, isReMaterializable = 1 in +def MOV8rm_NOREX : I<0x8A, MRMSrcMem, + (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteLoad]>; +} + + +// Condition code ops, incl. set if equal/not equal/... +let SchedRW = [WriteLAHFSAHF] in { +let Defs = [EFLAGS], Uses = [AH] in +def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", + [(set EFLAGS, (X86sahf AH))]>, + Requires<[HasLAHFSAHF]>; +let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in +def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags + Requires<[HasLAHFSAHF]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Bit tests instructions: BT, BTS, BTR, BTC. + +let Defs = [EFLAGS] in { +let SchedRW = [WriteBitTest] in { +def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, + OpSize16, TB, NotMemoryFoldable; +def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, + OpSize32, TB, NotMemoryFoldable; +def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB, + NotMemoryFoldable; +} // SchedRW + +// Unlike with the register+register form, the memory+register form of the +// bt instruction does not ignore the high bits of the index. From ISel's +// perspective, this is pretty bizarre. Make these instructions disassembly +// only for now. These instructions are also slow on modern CPUs so that's +// another reason to avoid generating them. + +let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { + def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + []>, OpSize16, TB, NotMemoryFoldable; + def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + []>, OpSize32, TB, NotMemoryFoldable; + def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + []>, TB, NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest] in { +def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>, + OpSize16, TB; +def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, + OpSize32, TB; +def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB; +} // SchedRW + +// Note that these instructions aren't slow because that only applies when the +// other operand is in a register. When it's an immediate, bt is still fast. +let SchedRW = [WriteALU] in { +def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi16 addr:$src1), + i16immSExt8:$src2))]>, + OpSize16, TB; +def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi32 addr:$src1), + i32immSExt8:$src2))]>, + OpSize32, TB; +def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi64 addr:$src1), + i64immSExt8:$src2))]>, TB, + Requires<[In64BitMode]>; +} // SchedRW + +let hasSideEffects = 0 in { +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTC32rr : I<0xBB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTC64rr : RI<0xBB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTC64ri8 : RIi8<0xBA, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + Requires<[In64BitMode]>; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTR32rr : I<0xB3, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTR64rr : RI<0xB3, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB; +def BTR32ri8 : Ii8<0xBA, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB; +def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB; +def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB; +def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + Requires<[In64BitMode]>; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTS32rr : I<0xAB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTS64rr : RI<0xAB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTS64ri8 : RIi8<0xBA, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + Requires<[In64BitMode]>; +} +} // hasSideEffects = 0 +} // Defs = [EFLAGS] + + +//===----------------------------------------------------------------------===// +// Atomic support +// + +// Atomic swap. These are just normal xchg instructions. But since a memory +// operand is referenced, the atomicity is ensured. +multiclass ATOMIC_SWAP opc8, bits<8> opc, string mnemonic, string frag> { + let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { + def NAME#8rm : I(frag # "_8") addr:$ptr, GR8:$val))]>; + def NAME#16rm : I(frag # "_16") addr:$ptr, GR16:$val))]>, + OpSize16; + def NAME#32rm : I(frag # "_32") addr:$ptr, GR32:$val))]>, + OpSize32; + def NAME#64rm : RI(frag # "_64") addr:$ptr, GR64:$val))]>; + } +} + +defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">, NotMemoryFoldable; + +// Swap between registers. +let SchedRW = [WriteALU] in { +let Constraints = "$src1 = $dst1, $src2 = $dst2", hasSideEffects = 0 in { +def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2), + (ins GR8:$src1, GR8:$src2), + "xchg{b}\t{$src1, $src2|$src2, $src1}", []>, NotMemoryFoldable; +def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2), + (ins GR16:$src1, GR16:$src2), + "xchg{w}\t{$src1, $src2|$src2, $src1}", []>, + OpSize16, NotMemoryFoldable; +def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2), + (ins GR32:$src1, GR32:$src2), + "xchg{l}\t{$src1, $src2|$src2, $src1}", []>, + OpSize32, NotMemoryFoldable; +def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst1, GR64:$dst2), + (ins GR64:$src1 ,GR64:$src2), + "xchg{q}\t{$src1, $src2|$src2, $src1}", []>, NotMemoryFoldable; +} + +def NOOP19rr: I<0x19, MRMSrcReg, (outs), (ins GR32:$val, GR32:$src), + "nop\t{$val, $src|$src, $val}", []>, TB, + OpSize32; + +// Swap between EAX and other registers. +let Constraints = "$src = $dst", hasSideEffects = 0 in { +let Uses = [AX], Defs = [AX] in +def XCHG16ar : I<0x90, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), + "xchg{w}\t{%ax, $src|$src, ax}", []>, OpSize16; +let Uses = [EAX], Defs = [EAX] in +def XCHG32ar : I<0x90, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), + "xchg{l}\t{%eax, $src|$src, eax}", []>, OpSize32; +let Uses = [RAX], Defs = [RAX] in +def XCHG64ar : RI<0x90, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), + "xchg{q}\t{%rax, $src|$src, rax}", []>; +} +} // SchedRW + +let hasSideEffects = 0, Constraints = "$src1 = $dst1, $src2 = $dst2", + Defs = [EFLAGS], SchedRW = [WriteALU] in { +def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst1, GR8:$dst2), + (ins GR8:$src1, GR8:$src2), + "xadd{b}\t{$src2, $src1|$src1, $src2}", []>, TB; +def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst1, GR16:$dst2), + (ins GR16:$src1, GR16:$src2), + "xadd{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16; +def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst1, GR32:$dst2), + (ins GR32:$src1, GR32:$src2), + "xadd{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32; +def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst1, GR64:$dst2), + (ins GR64:$src1, GR64:$src2), + "xadd{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, hasSideEffects = 0, Constraints = "$val = $dst", + Defs = [EFLAGS], SchedRW = [WriteALULd, WriteRMW] in { +def XADD8rm : I<0xC0, MRMSrcMem, (outs GR8:$dst), + (ins GR8:$val, i8mem:$ptr), + "xadd{b}\t{$val, $ptr|$ptr, $val}", []>, TB; +def XADD16rm : I<0xC1, MRMSrcMem, (outs GR16:$dst), + (ins GR16:$val, i16mem:$ptr), + "xadd{w}\t{$val, $ptr|$ptr, $val}", []>, TB, + OpSize16; +def XADD32rm : I<0xC1, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$val, i32mem:$ptr), + "xadd{l}\t{$val, $ptr|$ptr, $val}", []>, TB, + OpSize32; +def XADD64rm : RI<0xC1, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$val, i64mem:$ptr), + "xadd{q}\t{$val, $ptr|$ptr, $val}", []>, TB; + +} + +let SchedRW = [WriteALU], hasSideEffects = 0 in { +let Defs = [AL, EFLAGS], Uses = [AL] in +def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), + "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; +let Defs = [AX, EFLAGS], Uses = [AX] in +def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), + "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, + NotMemoryFoldable; +let Defs = [EAX, EFLAGS], Uses = [EAX] in +def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), + "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, + NotMemoryFoldable; +let Defs = [RAX, EFLAGS], Uses = [RAX] in +def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), + "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; +} // SchedRW, hasSideEffects + +let SchedRW = [WriteALULd, WriteRMW], mayLoad = 1, mayStore = 1, + hasSideEffects = 0 in { +let Defs = [AL, EFLAGS], Uses = [AL] in +def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), + "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; +let Defs = [AX, EFLAGS], Uses = [AX] in +def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, + NotMemoryFoldable; +let Defs = [EAX, EFLAGS], Uses = [EAX] in +def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, + NotMemoryFoldable; +let Defs = [RAX, EFLAGS], Uses = [RAX] in +def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; + +let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in +def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), + "cmpxchg8b\t$dst", []>, TB; + +let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in +def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), + "cmpxchg16b\t$dst", []>, + TB, Requires<[HasCmpxchg16b, In64BitMode]>; +} // SchedRW, mayLoad, mayStore, hasSideEffects + + +// Lock instruction prefix +let SchedRW = [WriteMicrocoded] in +def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; + +let SchedRW = [WriteNop] in { + +// Rex64 instruction prefix +def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>, + Requires<[In64BitMode]>; + +// Data16 instruction prefix +def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; +} // SchedRW + +// Repeat string operation instruction prefixes +let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in { +// Repeat (used with INS, OUTS, MOVS, LODS and STOS) +def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; +// Repeat while not equal (used with CMPS and SCAS) +def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; +} + +// String manipulation instructions +let SchedRW = [WriteMicrocoded] in { +let Defs = [AL,ESI], Uses = [ESI,DF] in +def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), + "lodsb\t{$src, %al|al, $src}", []>; +let Defs = [AX,ESI], Uses = [ESI,DF] in +def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), + "lodsw\t{$src, %ax|ax, $src}", []>, OpSize16; +let Defs = [EAX,ESI], Uses = [ESI,DF] in +def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), + "lods{l|d}\t{$src, %eax|eax, $src}", []>, OpSize32; +let Defs = [RAX,ESI], Uses = [ESI,DF] in +def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), + "lodsq\t{$src, %rax|rax, $src}", []>, + Requires<[In64BitMode]>; +} + +let SchedRW = [WriteSystem] in { +let Defs = [ESI], Uses = [DX,ESI,DF] in { +def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), + "outsb\t{$src, %dx|dx, $src}", []>; +def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), + "outsw\t{$src, %dx|dx, $src}", []>, OpSize16; +def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), + "outs{l|d}\t{$src, %dx|dx, $src}", []>, OpSize32; +} + +let Defs = [EDI], Uses = [DX,EDI,DF] in { +def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst), + "insb\t{%dx, $dst|$dst, dx}", []>; +def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst), + "insw\t{%dx, $dst|$dst, dx}", []>, OpSize16; +def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst), + "ins{l|d}\t{%dx, $dst|$dst, dx}", []>, OpSize32; +} +} + +// EFLAGS management instructions. +let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { +def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; +def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; +def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; +} + +// DF management instructions. +let SchedRW = [WriteALU], Defs = [DF] in { +def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; +def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; +} + +// Table lookup instructions +let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in +def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>, Sched<[WriteLoad]>; + +let SchedRW = [WriteMicrocoded] in { +// ASCII Adjust After Addition +let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, + Requires<[Not64BitMode]>; + +// ASCII Adjust AX Before Division +let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), + "aad\t$src", []>, Requires<[Not64BitMode]>; + +// ASCII Adjust AX After Multiply +let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), + "aam\t$src", []>, Requires<[Not64BitMode]>; + +// ASCII Adjust AL After Subtraction - sets +let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, + Requires<[Not64BitMode]>; + +// Decimal Adjust AL after Addition +let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in +def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, + Requires<[Not64BitMode]>; + +// Decimal Adjust AL after Subtraction +let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in +def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, + Requires<[Not64BitMode]>; +} // SchedRW + +let SchedRW = [WriteSystem] in { +// Check Array Index Against Bounds +// Note: "bound" does not have reversed operands in at&t syntax. +def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i32mem:$src), + "bound\t$dst, $src", []>, OpSize16, + Requires<[Not64BitMode]>; +def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i64mem:$src), + "bound\t$dst, $src", []>, OpSize32, + Requires<[Not64BitMode]>; + +// Adjust RPL Field of Segment Selector +def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), + "arpl\t{$src, $dst|$dst, $src}", []>, + Requires<[Not64BitMode]>, NotMemoryFoldable; +let mayStore = 1 in +def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "arpl\t{$src, $dst|$dst, $src}", []>, + Requires<[Not64BitMode]>, NotMemoryFoldable; +} // SchedRW + +//===----------------------------------------------------------------------===// +// MOVBE Instructions +// +let Predicates = [HasMOVBE] in { + let SchedRW = [WriteALULd] in { + def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "movbe{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, + OpSize16, T8PS; + def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "movbe{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, + OpSize32, T8PS; + def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "movbe{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, + T8PS; + } + let SchedRW = [WriteStore] in { + def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "movbe{w}\t{$src, $dst|$dst, $src}", + [(store (bswap GR16:$src), addr:$dst)]>, + OpSize16, T8PS; + def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "movbe{l}\t{$src, $dst|$dst, $src}", + [(store (bswap GR32:$src), addr:$dst)]>, + OpSize32, T8PS; + def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "movbe{q}\t{$src, $dst|$dst, $src}", + [(store (bswap GR64:$src), addr:$dst)]>, + T8PS; + } +} + +//===----------------------------------------------------------------------===// +// RDRAND Instruction +// +let Predicates = [HasRDRAND], Defs = [EFLAGS], SchedRW = [WriteSystem] in { + def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), + "rdrand{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86rdrand))]>, + OpSize16, PS; + def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), + "rdrand{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86rdrand))]>, + OpSize32, PS; + def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), + "rdrand{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86rdrand))]>, + PS; +} + +//===----------------------------------------------------------------------===// +// RDSEED Instruction +// +let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in { + def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), "rdseed{w}\t$dst", + [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, PS; + def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), "rdseed{l}\t$dst", + [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, PS; + def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdseed{q}\t$dst", + [(set GR64:$dst, EFLAGS, (X86rdseed))]>, PS; +} + +//===----------------------------------------------------------------------===// +// LZCNT Instruction +// +let Predicates = [HasLZCNT], Defs = [EFLAGS] in { + def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "lzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, + XS, OpSize16, Sched<[WriteLZCNT]>; + def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "lzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (ctlz (loadi16 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteLZCNTLd]>; + + def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "lzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, + XS, OpSize32, Sched<[WriteLZCNT]>; + def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "lzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (ctlz (loadi32 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteLZCNTLd]>; + + def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "lzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, + XS, Sched<[WriteLZCNT]>; + def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "lzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (ctlz (loadi64 addr:$src))), + (implicit EFLAGS)]>, XS, Sched<[WriteLZCNTLd]>; +} + +//===----------------------------------------------------------------------===// +// BMI Instructions +// +let Predicates = [HasBMI], Defs = [EFLAGS] in { + def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "tzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, + XS, OpSize16, Sched<[WriteTZCNT]>; + def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "tzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (cttz (loadi16 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteTZCNTLd]>; + + def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "tzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, + XS, OpSize32, Sched<[WriteTZCNT]>; + def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "tzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (cttz (loadi32 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteTZCNTLd]>; + + def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "tzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, + XS, Sched<[WriteTZCNT]>; + def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "tzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (cttz (loadi64 addr:$src))), + (implicit EFLAGS)]>, XS, Sched<[WriteTZCNTLd]>; +} + +multiclass bmi_bls { +let hasSideEffects = 0 in { + def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), + !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, + T8PS, VEX_4V, Sched<[WriteALU]>; + let mayLoad = 1 in + def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), + !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, + T8PS, VEX_4V, Sched<[WriteALULd]>; +} +} + +let Predicates = [HasBMI], Defs = [EFLAGS] in { + defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; + defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W; + defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>; + defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W; + defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>; + defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W; +} + +//===----------------------------------------------------------------------===// +// Pattern fragments to auto generate BMI instructions. +//===----------------------------------------------------------------------===// + +let Predicates = [HasBMI] in { + // FIXME: patterns for the load versions are not implemented + def : Pat<(and GR32:$src, (add GR32:$src, -1)), + (BLSR32rr GR32:$src)>; + def : Pat<(and GR64:$src, (add GR64:$src, -1)), + (BLSR64rr GR64:$src)>; + + def : Pat<(xor GR32:$src, (add GR32:$src, -1)), + (BLSMSK32rr GR32:$src)>; + def : Pat<(xor GR64:$src, (add GR64:$src, -1)), + (BLSMSK64rr GR64:$src)>; + + def : Pat<(and GR32:$src, (ineg GR32:$src)), + (BLSI32rr GR32:$src)>; + def : Pat<(and GR64:$src, (ineg GR64:$src)), + (BLSI64rr GR64:$src)>; +} + +multiclass bmi_bextr opc, string mnemonic, RegisterClass RC, + X86MemOperand x86memop, SDNode OpNode, + PatFrag ld_frag, X86FoldableSchedWrite Sched> { + def rr : I, + T8PS, VEX, Sched<[Sched]>; + def rm : I, T8PS, VEX, + Sched<[Sched.Folded, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + ReadAfterLd]>; +} + +let Predicates = [HasBMI], Defs = [EFLAGS] in { + defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem, + X86bextr, loadi32, WriteBEXTR>; + defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem, + X86bextr, loadi64, WriteBEXTR>, VEX_W; +} + +multiclass bmi_bzhi opc, string mnemonic, RegisterClass RC, + X86MemOperand x86memop, Intrinsic Int, + PatFrag ld_frag, X86FoldableSchedWrite Sched> { + def rr : I, + T8PS, VEX, Sched<[Sched]>; + def rm : I, T8PS, VEX, + Sched<[Sched.Folded, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + ReadAfterLd]>; +} + +let Predicates = [HasBMI2], Defs = [EFLAGS] in { + defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem, + int_x86_bmi_bzhi_32, loadi32, WriteBZHI>; + defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem, + int_x86_bmi_bzhi_64, loadi64, WriteBZHI>, VEX_W; +} + +def CountTrailingOnes : SDNodeXFormgetZExtValue()), SDLoc(N)); +}]>; + +def BEXTRMaskXForm : SDNodeXFormgetZExtValue()); + return getI32Imm(Length << 8, SDLoc(N)); +}]>; + +def AndMask64 : ImmLeaf(Imm); +}]>; + +// Use BEXTR for 64-bit 'and' with large immediate 'mask'. +let Predicates = [HasBMI, NoBMI2, NoTBM] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BEXTR64rr GR64:$src, + (SUBREG_TO_REG (i64 0), + (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BEXTR64rm addr:$src, + (SUBREG_TO_REG (i64 0), + (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; +} + +// Use BZHI for 64-bit 'and' with large immediate 'mask'. +let Predicates = [HasBMI2, NoTBM] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; +} + +let Predicates = [HasBMI2] in { + multiclass _bmi_bzhi_pattern { + def : Pat; + def : Pat; + } + + multiclass bmi_bzhi_patterns { + // x & ((1 << y) - 1) + defm : _bmi_bzhi_pattern<(and RC:$src, (add (shl 1, GR8:$lz), -1)), + (and (x86memop addr:$src), + (add (shl 1, GR8:$lz), -1)), + RC, VT, DstInst, DstMemInst>; + + // x & ~(-1 << y) + defm : _bmi_bzhi_pattern<(and RC:$src, (xor (shl -1, GR8:$lz), -1)), + (and (x86memop addr:$src), + (xor (shl -1, GR8:$lz), -1)), + RC, VT, DstInst, DstMemInst>; + + // x & (-1 >> (bitwidth - y)) + defm : _bmi_bzhi_pattern<(and RC:$src, (srl -1, (sub bitwidth, GR8:$lz))), + (and (x86memop addr:$src), + (srl -1, (sub bitwidth, GR8:$lz))), + RC, VT, DstInst, DstMemInst>; + + // x << (bitwidth - y) >> (bitwidth - y) + defm : _bmi_bzhi_pattern<(srl (shl RC:$src, (sub bitwidth, GR8:$lz)), + (sub bitwidth, GR8:$lz)), + (srl (shl (x86memop addr:$src), + (sub bitwidth, GR8:$lz)), + (sub bitwidth, GR8:$lz)), + RC, VT, DstInst, DstMemInst>; + } + + defm : bmi_bzhi_patterns; + defm : bmi_bzhi_patterns; + + // x & (-1 >> (32 - y)) + def : Pat<(and GR32:$src, (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), + (BZHI32rr GR32:$src, GR32:$lz)>; + def : Pat<(and (loadi32 addr:$src), (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), + (BZHI32rm addr:$src, GR32:$lz)>; + + // x & (-1 >> (64 - y)) + def : Pat<(and GR64:$src, (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + def : Pat<(and (loadi64 addr:$src), (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + + // x << (32 - y) >> (32 - y) + def : Pat<(srl (shl GR32:$src, (i8 (trunc (sub 32, GR32:$lz)))), + (i8 (trunc (sub 32, GR32:$lz)))), + (BZHI32rr GR32:$src, GR32:$lz)>; + def : Pat<(srl (shl (loadi32 addr:$src), (i8 (trunc (sub 32, GR32:$lz)))), + (i8 (trunc (sub 32, GR32:$lz)))), + (BZHI32rm addr:$src, GR32:$lz)>; + + // x << (64 - y) >> (64 - y) + def : Pat<(srl (shl GR64:$src, (i8 (trunc (sub 64, GR32:$lz)))), + (i8 (trunc (sub 64, GR32:$lz)))), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + def : Pat<(srl (shl (loadi64 addr:$src), (i8 (trunc (sub 64, GR32:$lz)))), + (i8 (trunc (sub 64, GR32:$lz)))), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; +} // HasBMI2 + +multiclass bmi_pdep_pext { + def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, + VEX_4V, Sched<[WriteALU]>; + def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, + VEX_4V, Sched<[WriteALULd, ReadAfterLd]>; +} + +let Predicates = [HasBMI2] in { + defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, + int_x86_bmi_pdep_32, loadi32>, T8XD; + defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, + int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; + defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, + int_x86_bmi_pext_32, loadi32>, T8XS; + defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, + int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; +} + +//===----------------------------------------------------------------------===// +// TBM Instructions +// +let Predicates = [HasTBM], Defs = [EFLAGS] in { + +multiclass tbm_ternary_imm opc, RegisterClass RC, string OpcodeStr, + X86MemOperand x86memop, PatFrag ld_frag, + SDNode OpNode, Operand immtype, + SDPatternOperator immoperator, + X86FoldableSchedWrite Sched> { + def ri : Ii32, + XOP, XOPA, Sched<[Sched]>; + def mi : Ii32, + XOP, XOPA, Sched<[Sched.Folded]>; +} + +defm BEXTRI32 : tbm_ternary_imm<0x10, GR32, "bextr{l}", i32mem, loadi32, + X86bextr, i32imm, imm, WriteBEXTR>; +let ImmT = Imm32S in +defm BEXTRI64 : tbm_ternary_imm<0x10, GR64, "bextr{q}", i64mem, loadi64, + X86bextr, i64i32imm, + i64immSExt32, WriteBEXTR>, VEX_W; + +multiclass tbm_binary_rm opc, Format FormReg, Format FormMem, + RegisterClass RC, string OpcodeStr, + X86MemOperand x86memop, X86FoldableSchedWrite Sched> { +let hasSideEffects = 0 in { + def rr : I, + XOP_4V, XOP9, Sched<[Sched]>; + let mayLoad = 1 in + def rm : I, + XOP_4V, XOP9, Sched<[Sched.Folded]>; +} +} + +multiclass tbm_binary_intr opc, string OpcodeStr, + X86FoldableSchedWrite Sched, + Format FormReg, Format FormMem> { + defm NAME#32 : tbm_binary_rm; + defm NAME#64 : tbm_binary_rm, VEX_W; +} + +defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>; +defm BLCI : tbm_binary_intr<0x02, "blci", WriteALU, MRM6r, MRM6m>; +defm BLCIC : tbm_binary_intr<0x01, "blcic", WriteALU, MRM5r, MRM5m>; +defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", WriteALU, MRM1r, MRM1m>; +defm BLCS : tbm_binary_intr<0x01, "blcs", WriteALU, MRM3r, MRM3m>; +defm BLSFILL : tbm_binary_intr<0x01, "blsfill", WriteALU, MRM2r, MRM2m>; +defm BLSIC : tbm_binary_intr<0x01, "blsic", WriteALU, MRM6r, MRM6m>; +defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", WriteALU, MRM7r, MRM7m>; +defm TZMSK : tbm_binary_intr<0x01, "tzmsk", WriteALU, MRM4r, MRM4m>; +} // HasTBM, EFLAGS + +// Use BEXTRI for 64-bit 'and' with large immediate 'mask'. +let Predicates = [HasTBM] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BEXTRI64ri GR64:$src, (BEXTRMaskXForm imm:$mask))>; + + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BEXTRI64mi addr:$src, (BEXTRMaskXForm imm:$mask))>; +} + +//===----------------------------------------------------------------------===// +// Lightweight Profiling Instructions + +let Predicates = [HasLWP], SchedRW = [WriteSystem] in { + +def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", + [(int_x86_llwpcb GR32:$src)]>, XOP, XOP9; +def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", + [(set GR32:$dst, (int_x86_slwpcb))]>, XOP, XOP9; + +def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", + [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, VEX_W; +def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", + [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, VEX_W; + +multiclass lwpins_intr { + def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), + "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, imm:$cntl))]>, + XOP_4V, XOPA; + let mayLoad = 1 in + def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), + "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), imm:$cntl))]>, + XOP_4V, XOPA; +} + +let Defs = [EFLAGS] in { + defm LWPINS32 : lwpins_intr; + defm LWPINS64 : lwpins_intr, VEX_W; +} // EFLAGS + +multiclass lwpval_intr { + def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), + "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(Int RC:$src0, GR32:$src1, imm:$cntl)]>, XOP_4V, XOPA; + let mayLoad = 1 in + def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), + "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(Int RC:$src0, (loadi32 addr:$src1), imm:$cntl)]>, + XOP_4V, XOPA; +} + +defm LWPVAL32 : lwpval_intr; +defm LWPVAL64 : lwpval_intr, VEX_W; + +} // HasLWP, SchedRW + +//===----------------------------------------------------------------------===// +// MONITORX/MWAITX Instructions +// +let SchedRW = [ WriteSystem ] in { +/* + let usesCustomInserter = 1 in { + def MONITORX : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3), + [(int_x86_monitorx addr:$src1, GR32:$src2, GR32:$src3)]>, + Requires<[ HasMWAITX ]>; + } +*/ + + let Uses = [ EAX, ECX, EDX ] in { + def MONITORXrrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, + TB, Requires<[ HasMWAITX ]>; + } + + let Uses = [ ECX, EAX, EBX ] in { + def MWAITXrrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", + [(int_x86_mwaitx ECX, EAX, EBX)]>, + TB, Requires<[ HasMWAITX ]>; + } +} // SchedRW + +// def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrrr)>, +// Requires<[ Not64BitMode ]>; +// def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>, +// Requires<[ In64BitMode ]>; + +// def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORXrrr)>, +// Requires<[ Not64BitMode ]>; +// def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>, +// Requires<[ In64BitMode ]>; + +//===----------------------------------------------------------------------===// +// WAITPKG Instructions +// +let SchedRW = [WriteSystem] in { + def UMONITOR16 : I<0xAE, MRM6r, (outs), (ins GR16:$src), + "umonitor\t$src", [(int_x86_umonitor GR16:$src)]>, + XS, AdSize16, Requires<[HasWAITPKG, Not64BitMode]>; + def UMONITOR32 : I<0xAE, MRM6r, (outs), (ins GR32:$src), + "umonitor\t$src", [(int_x86_umonitor GR32:$src)]>, + XS, AdSize32, Requires<[HasWAITPKG]>; + def UMONITOR64 : I<0xAE, MRM6r, (outs), (ins GR64:$src), + "umonitor\t$src", [(int_x86_umonitor GR64:$src)]>, + XS, AdSize64, Requires<[HasWAITPKG, In64BitMode]>; + let Uses = [EAX, EDX], Defs = [EFLAGS] in { + def UMWAIT : I<0xAE, MRM6r, + (outs), (ins GR32orGR64:$src), "umwait\t$src", + [(set EFLAGS, (X86umwait GR32orGR64:$src, EDX, EAX))]>, + XD, Requires<[HasWAITPKG]>; + def TPAUSE : I<0xAE, MRM6r, + (outs), (ins GR32orGR64:$src), "tpause\t$src", + [(set EFLAGS, (X86tpause GR32orGR64:$src, EDX, EAX))]>, + PD, Requires<[HasWAITPKG]>, NotMemoryFoldable; + } +} // SchedRW + +//===----------------------------------------------------------------------===// +// MOVDIRI - Move doubleword/quadword as direct store +// +let SchedRW = [WriteStore] in { +def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "movdiri\t{$src, $dst|$dst, $src}", + [(int_x86_directstore32 addr:$dst, GR32:$src)]>, + T8, Requires<[HasMOVDIRI]>; +def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "movdiri\t{$src, $dst|$dst, $src}", + [(int_x86_directstore64 addr:$dst, GR64:$src)]>, + T8, Requires<[In64BitMode, HasMOVDIRI]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// MOVDIR64B - Move 64 bytes as direct store +// +let SchedRW = [WriteStore] in { +def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), + "movdir64b\t{$src, $dst|$dst, $src}", []>, + T8PD, AdSize16, Requires<[HasMOVDIR64B, Not64BitMode]>; +def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), + "movdir64b\t{$src, $dst|$dst, $src}", + [(int_x86_movdir64b GR32:$dst, addr:$src)]>, + T8PD, AdSize32, Requires<[HasMOVDIR64B]>; +def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), + "movdir64b\t{$src, $dst|$dst, $src}", + [(int_x86_movdir64b GR64:$dst, addr:$src)]>, + T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// CLZERO Instruction +// +let SchedRW = [WriteSystem] in { + let Uses = [EAX] in + def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, + TB, Requires<[HasCLZERO]>; + +/* + let usesCustomInserter = 1 in { + def CLZERO : PseudoI<(outs), (ins i32mem:$src1), + [(int_x86_clzero addr:$src1)]>, Requires<[HasCLZERO]>; + } +*/ +} // SchedRW + +// def : InstAlias<"clzero\t{%eax|eax}", (CLZEROr)>, Requires<[Not64BitMode]>; +// def : InstAlias<"clzero\t{%rax|rax}", (CLZEROr)>, Requires<[In64BitMode]>; + +//===----------------------------------------------------------------------===// +// Pattern fragments to auto generate TBM instructions. +//===----------------------------------------------------------------------===// + +let Predicates = [HasTBM] in { + // FIXME: patterns for the load versions are not implemented + def : Pat<(and GR32:$src, (add GR32:$src, 1)), + (BLCFILL32rr GR32:$src)>; + def : Pat<(and GR64:$src, (add GR64:$src, 1)), + (BLCFILL64rr GR64:$src)>; + + def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), + (BLCI32rr GR32:$src)>; + def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), + (BLCI64rr GR64:$src)>; + + // Extra patterns because opt can optimize the above patterns to this. + def : Pat<(or GR32:$src, (sub -2, GR32:$src)), + (BLCI32rr GR32:$src)>; + def : Pat<(or GR64:$src, (sub -2, GR64:$src)), + (BLCI64rr GR64:$src)>; + + def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), + (BLCIC32rr GR32:$src)>; + def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), + (BLCIC64rr GR64:$src)>; + + def : Pat<(xor GR32:$src, (add GR32:$src, 1)), + (BLCMSK32rr GR32:$src)>; + def : Pat<(xor GR64:$src, (add GR64:$src, 1)), + (BLCMSK64rr GR64:$src)>; + + def : Pat<(or GR32:$src, (add GR32:$src, 1)), + (BLCS32rr GR32:$src)>; + def : Pat<(or GR64:$src, (add GR64:$src, 1)), + (BLCS64rr GR64:$src)>; + + def : Pat<(or GR32:$src, (add GR32:$src, -1)), + (BLSFILL32rr GR32:$src)>; + def : Pat<(or GR64:$src, (add GR64:$src, -1)), + (BLSFILL64rr GR64:$src)>; + + def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), + (BLSIC32rr GR32:$src)>; + def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), + (BLSIC64rr GR64:$src)>; + + def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), + (T1MSKC32rr GR32:$src)>; + def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), + (T1MSKC64rr GR64:$src)>; + + def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), + (TZMSK32rr GR32:$src)>; + def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), + (TZMSK64rr GR64:$src)>; +} // HasTBM + +//===----------------------------------------------------------------------===// +// Memory Instructions +// + +let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in +def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), + "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD; + +let Predicates = [HasCLWB], SchedRW = [WriteLoad] in +def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", + [(int_x86_clwb addr:$src)]>, PD, NotMemoryFoldable; + +let Predicates = [HasCLDEMOTE], SchedRW = [WriteLoad] in +def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src", + [(int_x86_cldemote addr:$src)]>, TB; + +//===----------------------------------------------------------------------===// +// Subsystems. +//===----------------------------------------------------------------------===// + +include "X86Capstone.td" + +include "X86InstrArithmetic.td" +include "X86InstrCMovSetCC.td" +include "X86InstrExtension.td" +include "X86InstrControl.td" +include "X86InstrShiftRotate.td" + +// X87 Floating Point Stack. +//include "X86InstrFPStack.td" + +// SIMD support (SSE, MMX and AVX) +//include "X86InstrFragmentsSIMD.td" + +// FMA - Fused Multiply-Add support (requires FMA) +//include "X86InstrFMA.td" + +// XOP +//include "X86InstrXOP.td" + +// SSE, MMX and 3DNow! vector support. +//include "X86InstrSSE.td" +//include "X86InstrAVX512.td" +//include "X86InstrMMX.td" +//include "X86Instr3DNow.td" + +// MPX instructions +//include "X86InstrMPX.td" + +include "X86InstrVMX.td" +include "X86InstrSVM.td" + +//include "X86InstrTSX.td" +//include "X86InstrSGX.td" + +// System instructions. +include "X86InstrSystem.td" + +// Compiler Pseudo Instructions and Pat Patterns +//include "X86InstrCompiler.td" +//include "X86InstrVecCompiler.td" + +//===----------------------------------------------------------------------===// +// Assembler Mnemonic Aliases +//===----------------------------------------------------------------------===// + +def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; + +def : MnemonicAlias<"cbw", "cbtw", "att">; +def : MnemonicAlias<"cwde", "cwtl", "att">; +def : MnemonicAlias<"cwd", "cwtd", "att">; +def : MnemonicAlias<"cdq", "cltd", "att">; +def : MnemonicAlias<"cdqe", "cltq", "att">; +def : MnemonicAlias<"cqo", "cqto", "att">; + +// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. +def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; + +def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; +def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; + +def : MnemonicAlias<"loopz", "loope">; +def : MnemonicAlias<"loopnz", "loopne">; + +def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"popf", "popfq", "intel">, Requires<[In64BitMode]>; +def : MnemonicAlias<"popfd", "popfl", "att">; + +// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in +// all modes. However: "push (addr)" and "push $42" should default to +// pushl/pushq depending on the current mode. Similar for "pop %bx" +def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"pushf", "pushfq", "intel">, Requires<[In64BitMode]>; +def : MnemonicAlias<"pushfd", "pushfl", "att">; + +def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; +def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; +def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; +def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; + +def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; + +def : MnemonicAlias<"repe", "rep">; +def : MnemonicAlias<"repz", "rep">; +def : MnemonicAlias<"repnz", "repne">; + +def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; + +// Apply 'ret' behavior to 'retn' +def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"retn", "ret", "intel">; + +def : MnemonicAlias<"sal", "shl", "intel">; +def : MnemonicAlias<"salb", "shlb", "att">; +def : MnemonicAlias<"salw", "shlw", "att">; +def : MnemonicAlias<"sall", "shll", "att">; +def : MnemonicAlias<"salq", "shlq", "att">; + +def : MnemonicAlias<"smovb", "movsb", "att">; +def : MnemonicAlias<"smovw", "movsw", "att">; +def : MnemonicAlias<"smovl", "movsl", "att">; +def : MnemonicAlias<"smovq", "movsq", "att">; + +def : MnemonicAlias<"ud2a", "ud2", "att">; +def : MnemonicAlias<"verrw", "verr", "att">; + +// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release' +def : MnemonicAlias<"acquire", "xacquire", "intel">; +def : MnemonicAlias<"release", "xrelease", "intel">; + +// System instruction aliases. +def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; +def : MnemonicAlias<"sysret", "sysretl", "att">; +def : MnemonicAlias<"sysexit", "sysexitl", "att">; + +def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; +//def : MnemonicAlias<"lgdt", "lgdtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"lgdt", "lgdtd", "intel">, Requires<[In32BitMode]>; +//def : MnemonicAlias<"lidt", "lidtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"lidt", "lidtd", "intel">, Requires<[In32BitMode]>; +//def : MnemonicAlias<"sgdt", "sgdtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"sgdt", "sgdtd", "intel">, Requires<[In32BitMode]>; +//def : MnemonicAlias<"sidt", "sidtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"sidt", "sidtd", "intel">, Requires<[In32BitMode]>; + + +// Floating point stack aliases. +def : MnemonicAlias<"fcmovz", "fcmove", "att">; +def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; +def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; +def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; +def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; +def : MnemonicAlias<"fcomip", "fcompi">; +def : MnemonicAlias<"fildq", "fildll", "att">; +def : MnemonicAlias<"fistpq", "fistpll", "att">; +def : MnemonicAlias<"fisttpq", "fisttpll", "att">; +def : MnemonicAlias<"fldcww", "fldcw", "att">; +def : MnemonicAlias<"fnstcww", "fnstcw", "att">; +def : MnemonicAlias<"fnstsww", "fnstsw", "att">; +def : MnemonicAlias<"fucomip", "fucompi">; +def : MnemonicAlias<"fwait", "wait">; + +def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; +def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; +def : MnemonicAlias<"xsaveq", "xsave64", "att">; +def : MnemonicAlias<"xrstorq", "xrstor64", "att">; +def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; +def : MnemonicAlias<"xrstorsq", "xrstors64", "att">; +def : MnemonicAlias<"xsavecq", "xsavec64", "att">; +def : MnemonicAlias<"xsavesq", "xsaves64", "att">; + +class CondCodeAlias + : MnemonicAlias; + +/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of +/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for +/// example "setz" -> "sete". +multiclass IntegerCondCodeMnemonicAlias { + def C : CondCodeAlias; // setc -> setb + def Z : CondCodeAlias; // setz -> sete + def NA : CondCodeAlias; // setna -> setbe + def NB : CondCodeAlias; // setnb -> setae + def NC : CondCodeAlias; // setnc -> setae + def NG : CondCodeAlias; // setng -> setle + def NL : CondCodeAlias; // setnl -> setge + def NZ : CondCodeAlias; // setnz -> setne + def PE : CondCodeAlias; // setpe -> setp + def PO : CondCodeAlias; // setpo -> setnp + + def NAE : CondCodeAlias; // setnae -> setb + def NBE : CondCodeAlias; // setnbe -> seta + def NGE : CondCodeAlias; // setnge -> setl + def NLE : CondCodeAlias; // setnle -> setg +} + +// Aliases for set +defm : IntegerCondCodeMnemonicAlias<"set", "">; +// Aliases for j +defm : IntegerCondCodeMnemonicAlias<"j", "">; +// Aliases for cmov{w,l,q} +defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; +defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; +defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; +// No size suffix for intel-style asm. +defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; + + +//===----------------------------------------------------------------------===// +// Assembler Instruction Aliases +//===----------------------------------------------------------------------===// + +// aad/aam default to base 10 if no operand is specified. +// def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>; +// def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>; + +// Disambiguate the mem/imm form of bt-without-a-suffix as btl. +// Likewise for btc/btr/bts. +// def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}", +// (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; +// def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}", +// (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; +// def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}", +// (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; +// def : InstAlias<"bts\t{$imm, $mem|$mem, $imm}", +// (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; + +// clr aliases. +// def : InstAlias<"clr{b}\t$reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; +// def : InstAlias<"clr{w}\t$reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; +// def : InstAlias<"clr{l}\t$reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; +// def : InstAlias<"clr{q}\t$reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; + +// lods aliases. Accept the destination being omitted because it's implicit +// in the mnemonic, or the mnemonic suffix being omitted because it's implicit +// in the destination. +// def : InstAlias<"lodsb\t$src", (LODSB srcidx8:$src), 0>; +// def : InstAlias<"lodsw\t$src", (LODSW srcidx16:$src), 0>; +// def : InstAlias<"lods{l|d}\t$src", (LODSL srcidx32:$src), 0>; +// def : InstAlias<"lodsq\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; +// def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; +// def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; +// def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; +// def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; +// def : InstAlias<"lods\t$src", (LODSB srcidx8:$src), 0, "intel">; +// def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0, "intel">; +// def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0, "intel">; +// def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; + + +// stos aliases. Accept the source being omitted because it's implicit in +// the mnemonic, or the mnemonic suffix being omitted because it's implicit +// in the source. +// def : InstAlias<"stosb\t$dst", (STOSB dstidx8:$dst), 0>; +// def : InstAlias<"stosw\t$dst", (STOSW dstidx16:$dst), 0>; +// def : InstAlias<"stos{l|d}\t$dst", (STOSL dstidx32:$dst), 0>; +// def : InstAlias<"stosq\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +// def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; +// def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; +// def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; +// def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +// def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst), 0, "intel">; +// def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0, "intel">; +// def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0, "intel">; +// def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; + + +// scas aliases. Accept the destination being omitted because it's implicit +// in the mnemonic, or the mnemonic suffix being omitted because it's implicit +// in the destination. +// def : InstAlias<"scasb\t$dst", (SCASB dstidx8:$dst), 0>; +// def : InstAlias<"scasw\t$dst", (SCASW dstidx16:$dst), 0>; +// def : InstAlias<"scas{l|d}\t$dst", (SCASL dstidx32:$dst), 0>; +// def : InstAlias<"scasq\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +// def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; +// def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; +// def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; +// def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +// def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst), 0, "intel">; +// def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0, "intel">; +// def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0, "intel">; +// def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; + +// cmps aliases. Mnemonic suffix being omitted because it's implicit +// in the destination. +// def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0, "intel">; +// def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0, "intel">; +// def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0, "intel">; +// def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; + +// movs aliases. Mnemonic suffix being omitted because it's implicit +// in the destination. +// def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0, "intel">; +// def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0, "intel">; +// def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0, "intel">; +// def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; + +// div and idiv aliases for explicit A register. +// def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; +// def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; +// def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; +// def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; +// def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; +// def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; +// def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; +// def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; +// def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; +// def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; +// def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; +// def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; +// def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; +// def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; +// def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; +// def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; + + + +// Various unary fpstack operations default to operating on ST1. +// For example, "fxch" -> "fxch %st(1)" +// def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; +//def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; +// def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; +// def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; +// def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; +// def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; +// def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; +// def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; +// def : InstAlias<"fxch", (XCH_F ST1), 0>; +// def : InstAlias<"fcom", (COM_FST0r ST1), 0>; +// def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; +// def : InstAlias<"fcomi", (COM_FIr ST1), 0>; +// def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; +// def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; +// def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; +// def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; +// def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; + +/* +// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. +// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate +// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with +// gas. +//multiclass FpUnaryAlias { + def : InstAlias; + def : InstAlias; +} + +defm : FpUnaryAlias<"fadd", ADD_FST0r>; +defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; +defm : FpUnaryAlias<"fsub", SUB_FST0r>; +defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; +defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; +defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; +defm : FpUnaryAlias<"fmul", MUL_FST0r>; +defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; +defm : FpUnaryAlias<"fdiv", DIV_FST0r>; +defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; +defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; +defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; +defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; +defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; +defm : FpUnaryAlias<"fcompi", COM_FIPr>; +defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; +*/ + + +// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they +// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, +// solely because gas supports it. +// def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; +// def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; +// def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; +// def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; +// def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; +// def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; + +// def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; + +// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but +// this is compatible with what GAS does. +// def : InstAlias<"lcall\t$seg : $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; +// def : InstAlias<"ljmp\t$seg : $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; +// def : InstAlias<"lcall\t{*}$dst", (FARCALL32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; +// def : InstAlias<"ljmp\t{*}$dst", (FARJMP32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; +// def : InstAlias<"lcall\t$seg : $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; +// def : InstAlias<"ljmp\t$seg : $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; +// def : InstAlias<"lcall\t{*}$dst", (FARCALL16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; +// def : InstAlias<"ljmp\t{*}$dst", (FARJMP16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; + +// def : InstAlias<"jmp\t{*}$dst", (JMP64m i64mem:$dst), 0, "att">, Requires<[In64BitMode]>; +// def : InstAlias<"jmp\t{*}$dst", (JMP32m i32mem:$dst), 0, "att">, Requires<[In32BitMode]>; +// def : InstAlias<"jmp\t{*}$dst", (JMP16m i16mem:$dst), 0, "att">, Requires<[In16BitMode]>; + + +// "imul , B" is an alias for "imul , B, B". +// def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; +// def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; +// def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; +// def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; +// def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; +// def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; + +// ins aliases. Accept the mnemonic suffix being omitted because it's implicit +// in the destination. +// def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0, "intel">; +// def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0, "intel">; +// def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0, "intel">; + +// outs aliases. Accept the mnemonic suffix being omitted because it's implicit +// in the source. +// def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0, "intel">; +// def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0, "intel">; +// def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0, "intel">; + +// inb %dx -> inb %al, %dx +// def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; +// def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; +// def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; +// def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>; +// def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>; +// def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>; + + +// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp +// def : InstAlias<"call\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; +// def : InstAlias<"jmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; +// def : InstAlias<"call\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; +// def : InstAlias<"jmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; +// def : InstAlias<"callw\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; +// def : InstAlias<"jmpw\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; +// def : InstAlias<"calll\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; +// def : InstAlias<"jmpl\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; + +// Match 'movq , ' as an alias for movabsq. +// def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; + +// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, +// which supports this due to an old AMD documentation bug when 64-bit mode was +// created. +// def : InstAlias<"movd\t{$src, $dst|$dst, $src}", +// (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; +// def : InstAlias<"movd\t{$src, $dst|$dst, $src}", +// (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; + +// movsx aliases +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0, "att">; +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0, "att">; +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0, "att">; +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0, "att">; +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0, "att">; +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0, "att">; +// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0, "att">; + +// movzx aliases +// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0, "att">; +// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0, "att">; +// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0, "att">; +// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0, "att">; +// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr8 GR64:$dst, GR8:$src), 0, "att">; +// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr16 GR64:$dst, GR16:$src), 0, "att">; +// Note: No GR32->GR64 movzx form. + +// outb %dx -> outb %al, %dx +// def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; +// def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; +// def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; +// def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>; +// def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>; +// def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>; + +// 'sldt ' can be encoded with either sldtw or sldtq with the same +// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity +// errors, since its encoding is the most compact. +// def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; + +// shld/shrd op,op -> shld op, op, CL +// def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; +// def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; +// def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; +// def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; +// def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; +// def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; + +// def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; +// def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; +// def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; +// def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; +// def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; +// def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; + +/* FIXME: This is disabled because the asm matcher is currently incapable of + * matching a fixed immediate like $1. +// "shl X, $1" is an alias for "shl X". +multiclass ShiftRotateByOneAlias { + // def : InstAlias(!strconcat(Opc, "8r1")) GR8:$op)>; + // def : InstAlias(!strconcat(Opc, "16r1")) GR16:$op)>; + // def : InstAlias(!strconcat(Opc, "32r1")) GR32:$op)>; + // def : InstAlias(!strconcat(Opc, "64r1")) GR64:$op)>; + // def : InstAlias(!strconcat(Opc, "8m1")) i8mem:$op)>; + // def : InstAlias(!strconcat(Opc, "16m1")) i16mem:$op)>; + // def : InstAlias(!strconcat(Opc, "32m1")) i32mem:$op)>; + // def : InstAlias(!strconcat(Opc, "64m1")) i64mem:$op)>; +} + +defm : ShiftRotateByOneAlias<"rcl", "RCL">; +defm : ShiftRotateByOneAlias<"rcr", "RCR">; +defm : ShiftRotateByOneAlias<"rol", "ROL">; +defm : ShiftRotateByOneAlias<"ror", "ROR">; +FIXME */ + +// test: We accept "testX , " and "testX , " as synonyms. +// def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}", +// (TEST8mr i8mem :$mem, GR8 :$val), 0>; +// def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}", +// (TEST16mr i16mem:$mem, GR16:$val), 0>; +// def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}", +// (TEST32mr i32mem:$mem, GR32:$val), 0>; +// def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}", +// (TEST64mr i64mem:$mem, GR64:$val), 0>; + +// xchg: We accept "xchgX , " and "xchgX , " as synonyms. +// def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", +// (XCHG8rm GR8 :$val, i8mem :$mem), 0>; +// def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", +// (XCHG16rm GR16:$val, i16mem:$mem), 0>; +// def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", +// (XCHG32rm GR32:$val, i32mem:$mem), 0>; +// def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", +// (XCHG64rm GR64:$val, i64mem:$mem), 0>; + +// xchg: We accept "xchgX , %eax" and "xchgX %eax, " as synonyms. +// def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; +// def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src), 0>; +// def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; + +// In 64-bit mode, xchg %eax, %eax can't be encoded with the 0x90 opcode we +// would get by default because it's defined as NOP. But xchg %eax, %eax implies +// implicit zeroing of the upper 32 bits. So alias to the longer encoding. +// def : InstAlias<"xchg{l}\t{%eax, %eax|eax, eax}", +// (XCHG32rr EAX, EAX), 0>, Requires<[In64BitMode]>; + +// xchg %rax, %rax is a nop in x86-64 and can be encoded as such. Without this +// we emit an unneeded REX.w prefix. +// def : InstAlias<"xchg{q}\t{%rax, %rax|rax, rax}", (NOOP), 0>; + +// These aliases exist to get the parser to prioritize matching 8-bit +// immediate encodings over matching the implicit ax/eax/rax encodings. By +// explicitly mentioning the A register here, these entries will be ordered +// first due to the more explicit immediate type. +// def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>; +// def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>; + +// def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>; +// def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>; + +// def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>; +// def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrMMX.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrMMX.td new file mode 100644 index 0000000..c2be946 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrMMX.td @@ -0,0 +1,612 @@ +//===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 MMX instruction set, defining the instructions, +// and properties of the instructions which are needed for code generation, +// machine code emission, and analysis. +// +// All instructions that use MMX should be in this file, even if they also use +// SSE. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// MMX Multiclasses +//===----------------------------------------------------------------------===// + +// Alias instruction that maps zero vector to pxor mmx. +// This is expanded by ExpandPostRAPseudos to an pxor. +// We set canFoldAsLoad because this can be converted to a constant-pool +// load of an all-zeros value if folding it would be beneficial. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, SchedRW = [WriteZero] in { +def MMX_SET0 : I<0, Pseudo, (outs VR64:$dst), (ins), "", []>; +} + +let Constraints = "$src1 = $dst" in { + // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic. + // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp. + multiclass MMXI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId, + X86FoldableSchedWrite sched, bit Commutable = 0, + X86MemOperand OType = i64mem> { + def irr : MMXI, + Sched<[sched]> { + let isCommutable = Commutable; + } + def irm : MMXI, + Sched<[sched.Folded, ReadAfterLd]>; + } + + multiclass MMXI_binop_rmi_int opc, bits<8> opc2, Format ImmForm, + string OpcodeStr, Intrinsic IntId, + Intrinsic IntId2, X86FoldableSchedWrite sched, + X86FoldableSchedWrite schedImm> { + def rr : MMXI, + Sched<[sched]>; + def rm : MMXI, + Sched<[sched.Folded, ReadAfterLd]>; + def ri : MMXIi8, + Sched<[schedImm]>; + } +} + +/// Unary MMX instructions requiring SSSE3. +multiclass SS3I_unop_rm_int_mm opc, string OpcodeStr, + Intrinsic IntId64, X86FoldableSchedWrite sched> { + def rr : MMXSS38I, + Sched<[sched]>; + + def rm : MMXSS38I, + Sched<[sched.Folded]>; +} + +/// Binary MMX instructions requiring SSSE3. +let ImmT = NoImm, Constraints = "$src1 = $dst" in { +multiclass SS3I_binop_rm_int_mm opc, string OpcodeStr, + Intrinsic IntId64, X86FoldableSchedWrite sched, + bit Commutable = 0> { + let isCommutable = Commutable in + def rr : MMXSS38I, + Sched<[sched]>; + def rm : MMXSS38I, + Sched<[sched.Folded, ReadAfterLd]>; +} +} + +/// PALIGN MMX instructions (require SSSE3). +multiclass ssse3_palign_mm { + def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), + (ins VR64:$src1, VR64:$src2, u8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>, + Sched<[sched]>; + def rmi : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), + (ins VR64:$src1, i64mem:$src2, u8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + [(set VR64:$dst, (IntId VR64:$src1, + (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass sse12_cvt_pint opc, RegisterClass SrcRC, RegisterClass DstRC, + Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag, + string asm, X86FoldableSchedWrite sched, Domain d> { + def irr : MMXPI, + Sched<[sched]>; + def irm : MMXPI, + Sched<[sched.Folded]>; +} + +multiclass sse12_cvt_pint_3addr opc, RegisterClass SrcRC, + RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, + PatFrag ld_frag, string asm, Domain d> { + def irr : MMXPI, + Sched<[WriteCvtI2PS]>; + def irm : MMXPI, + Sched<[WriteCvtI2PS.Folded]>; +} + +//===----------------------------------------------------------------------===// +// MMX EMMS Instruction +//===----------------------------------------------------------------------===// + +let SchedRW = [WriteEMMS] in +def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>; + +//===----------------------------------------------------------------------===// +// MMX Scalar Instructions +//===----------------------------------------------------------------------===// + +// Data Transfer Instructions +def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, + (x86mmx (scalar_to_vector GR32:$src)))]>, + Sched<[WriteVecMoveFromGpr]>; +def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, + (x86mmx (scalar_to_vector (loadi32 addr:$src))))]>, + Sched<[WriteVecLoad]>; + +let Predicates = [HasMMX] in { + def : Pat<(x86mmx (MMX_X86movw2d GR32:$src)), + (MMX_MOVD64rr GR32:$src)>; + def : Pat<(x86mmx (MMX_X86movw2d (i32 0))), + (MMX_SET0)>; + def : Pat<(x86mmx (MMX_X86movw2d (loadi32 addr:$src))), + (MMX_MOVD64rm addr:$src)>; +} + +let mayStore = 1 in +def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src), + "movd\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteVecStore]>; + +def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, + (MMX_X86movd2w (x86mmx VR64:$src)))]>, + Sched<[WriteVecMoveToGpr]>, FoldGenData<"MMX_MOVD64rr">; + +let isBitcast = 1 in +def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, (bitconvert GR64:$src))]>, + Sched<[WriteVecMoveFromGpr]>; + +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in +def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst), + (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}", + []>, Sched<[SchedWriteVecMoveLS.MMX.RM]>; + +let isBitcast = 1 in { +def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg, + (outs GR64:$dst), (ins VR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (bitconvert VR64:$src))]>, + Sched<[WriteVecMoveToGpr]>; +let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in { +def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), + "movq\t{$src, $dst|$dst, $src}", []>; +let isCodeGenOnly = 1, ForceDisassemble = 1 in +def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src), + "movq\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MMX_MOVQ64rr">; +} // SchedRW, hasSideEffects, isMoveReg +} // isBitcast + +// def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}", +// (MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>; + +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in +def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem, + (outs), (ins i64mem:$dst, VR64:$src), + "movq\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.MMX.MR]>; + +let SchedRW = [SchedWriteVecMoveLS.MMX.RM] in { +let canFoldAsLoad = 1 in +def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, (load_mmx addr:$src))]>; +} // SchedRW + +let SchedRW = [SchedWriteVecMoveLS.MMX.MR] in +def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(store (x86mmx VR64:$src), addr:$dst)]>; + +let SchedRW = [SchedWriteVecMoveLS.XMM.RR] in { +def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), + (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, + (x86mmx (bitconvert + (i64 (extractelt (v2i64 VR128:$src), + (iPTR 0))))))]>; + +def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst), + (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 + (scalar_to_vector + (i64 (bitconvert (x86mmx VR64:$src))))))]>; + +let isCodeGenOnly = 1, hasSideEffects = 1 in { +def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst), + (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", + []>; + +def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), + (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}", + []>; +} +} // SchedRW + +let Predicates = [HasMMX, HasSSE1] in +def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), + "movntq\t{$src, $dst|$dst, $src}", + [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>, + Sched<[SchedWriteVecMoveLSNT.MMX.MR]>; + +let Predicates = [HasMMX] in { + // movd to MMX register zero-extends + def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))), + (MMX_MOVD64rr GR32:$src)>; + def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector (loadi32 addr:$src))))), + (MMX_MOVD64rm addr:$src)>; +} + +// Arithmetic Instructions +defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b, + SchedWriteVecALU.MMX>; +defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w, + SchedWriteVecALU.MMX>; +defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d, + SchedWriteVecALU.MMX>; +// -- Addition +defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, + SchedWriteVecALU.MMX, 1>; +defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, + SchedWriteVecALU.MMX, 1>; +defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, + SchedWriteVecALU.MMX, 1>; +let Predicates = [HasMMX, HasSSE2] in +defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, + SchedWriteVecALU.MMX, 1>; +defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, + SchedWriteVecALU.MMX, 1>; +defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, + SchedWriteVecALU.MMX, 1>; + +defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, + SchedWriteVecALU.MMX, 1>; +defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, + SchedWriteVecALU.MMX, 1>; + +defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w, + SchedWritePHAdd.MMX>; +defm MMX_PHADDD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d, + SchedWritePHAdd.MMX>; +defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw, + SchedWritePHAdd.MMX>; + +// -- Subtraction +defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b, + SchedWriteVecALU.MMX>; +defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w, + SchedWriteVecALU.MMX>; +defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d, + SchedWriteVecALU.MMX>; +let Predicates = [HasMMX, HasSSE2] in +defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q, + SchedWriteVecALU.MMX>; + +defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b, + SchedWriteVecALU.MMX>; +defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w, + SchedWriteVecALU.MMX>; + +defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b, + SchedWriteVecALU.MMX>; +defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w, + SchedWriteVecALU.MMX>; + +defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w, + SchedWritePHAdd.MMX>; +defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d, + SchedWritePHAdd.MMX>; +defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw, + SchedWritePHAdd.MMX>; + +// -- Multiplication +defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, + SchedWriteVecIMul.MMX, 1>; + +defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, + SchedWriteVecIMul.MMX, 1>; +let Predicates = [HasMMX, HasSSE1] in +defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, + SchedWriteVecIMul.MMX, 1>; +let Predicates = [HasMMX, HasSSE2] in +defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, + SchedWriteVecIMul.MMX, 1>; +defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", + int_x86_ssse3_pmul_hr_sw, + SchedWriteVecIMul.MMX, 1>; + +// -- Miscellanea +defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, + SchedWriteVecIMul.MMX, 1>; + +defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw", + int_x86_ssse3_pmadd_ub_sw, + SchedWriteVecIMul.MMX>; +let Predicates = [HasMMX, HasSSE1] in { +defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, + SchedWriteVecALU.MMX, 1>; +defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, + SchedWriteVecALU.MMX, 1>; + +defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, + SchedWriteVecALU.MMX, 1>; +defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, + SchedWriteVecALU.MMX, 1>; + +defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, + SchedWriteVecALU.MMX, 1>; +defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, + SchedWriteVecALU.MMX, 1>; + +defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, + SchedWritePSADBW.MMX, 1>; +} + +defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b, + SchedWriteVecALU.MMX>; +defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w, + SchedWriteVecALU.MMX>; +defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d, + SchedWriteVecALU.MMX>; +let Constraints = "$src1 = $dst" in + defm MMX_PALIGNR : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b, + SchedWriteShuffle.MMX>; + +// Logical Instructions +defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, + SchedWriteVecLogic.MMX, 1>; +defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, + SchedWriteVecLogic.MMX, 1>; +defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, + SchedWriteVecLogic.MMX, 1>; +defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn, + SchedWriteVecLogic.MMX>; + +// Shift Instructions +defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", + int_x86_mmx_psrl_w, int_x86_mmx_psrli_w, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; +defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", + int_x86_mmx_psrl_d, int_x86_mmx_psrli_d, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; +defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", + int_x86_mmx_psrl_q, int_x86_mmx_psrli_q, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; + +defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", + int_x86_mmx_psll_w, int_x86_mmx_pslli_w, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; +defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", + int_x86_mmx_psll_d, int_x86_mmx_pslli_d, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; +defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", + int_x86_mmx_psll_q, int_x86_mmx_pslli_q, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; + +defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", + int_x86_mmx_psra_w, int_x86_mmx_psrai_w, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; +defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", + int_x86_mmx_psra_d, int_x86_mmx_psrai_d, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; + +// Comparison Instructions +defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b, + SchedWriteVecALU.MMX>; +defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w, + SchedWriteVecALU.MMX>; +defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d, + SchedWriteVecALU.MMX>; + +defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b, + SchedWriteVecALU.MMX>; +defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w, + SchedWriteVecALU.MMX>; +defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d, + SchedWriteVecALU.MMX>; + +// -- Unpack Instructions +defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw", + int_x86_mmx_punpckhbw, + SchedWriteShuffle.MMX>; +defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd", + int_x86_mmx_punpckhwd, + SchedWriteShuffle.MMX>; +defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq", + int_x86_mmx_punpckhdq, + SchedWriteShuffle.MMX>; +defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw", + int_x86_mmx_punpcklbw, + SchedWriteShuffle.MMX, + 0, i32mem>; +defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd", + int_x86_mmx_punpcklwd, + SchedWriteShuffle.MMX, + 0, i32mem>; +defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq", + int_x86_mmx_punpckldq, + SchedWriteShuffle.MMX, + 0, i32mem>; + +// -- Pack Instructions +defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb, + SchedWriteShuffle.MMX>; +defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw, + SchedWriteShuffle.MMX>; +defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb, + SchedWriteShuffle.MMX>; + +// -- Shuffle Instructions +defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b, + SchedWriteVarShuffle.MMX>; + +def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg, + (outs VR64:$dst), (ins VR64:$src1, u8imm:$src2), + "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR64:$dst, + (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))]>, + Sched<[SchedWriteShuffle.MMX]>; +def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem, + (outs VR64:$dst), (ins i64mem:$src1, u8imm:$src2), + "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR64:$dst, + (int_x86_sse_pshuf_w (load_mmx addr:$src1), + imm:$src2))]>, + Sched<[SchedWriteShuffle.MMX.Folded]>; + +// -- Conversion Instructions +defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi, + f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}", + WriteCvtPS2I, SSEPackedSingle>, PS; +defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi, + f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}", + WriteCvtPD2I, SSEPackedDouble>, PD; +defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi, + f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}", + WriteCvtPS2I, SSEPackedSingle>, PS; +defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi, + f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}", + WriteCvtPD2I, SSEPackedDouble>, PD; +defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd, + i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}", + WriteCvtI2PD, SSEPackedDouble>, PD; +let Constraints = "$src1 = $dst" in { + defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128, + int_x86_sse_cvtpi2ps, + i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}", + SSEPackedSingle>, PS; +} + +// Extract / Insert +let Predicates = [HasMMX, HasSSE1] in +def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg, + (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2), + "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1, + imm:$src2))]>, + Sched<[WriteVecExtract]>; +let Constraints = "$src1 = $dst" in { +let Predicates = [HasMMX, HasSSE1] in { + def MMX_PINSRWrr : MMXIi8<0xC4, MRMSrcReg, + (outs VR64:$dst), + (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3), + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, + GR32orGR64:$src2, imm:$src3))]>, + Sched<[WriteVecInsert]>; + + def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem, + (outs VR64:$dst), + (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3), + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, + (i32 (anyext (loadi16 addr:$src2))), + imm:$src3))]>, + Sched<[WriteVecInsertLd, ReadAfterLd]>; +} +} + +// Mask creation +let Predicates = [HasMMX, HasSSE1] in +def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), + (ins VR64:$src), + "pmovmskb\t{$src, $dst|$dst, $src}", + [(set GR32orGR64:$dst, + (int_x86_mmx_pmovmskb VR64:$src))]>, + Sched<[WriteMMXMOVMSK]>; + +// Low word of XMM to MMX. +def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1, + [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>; + +def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)), + (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>; + +def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))), + (x86mmx (MMX_MOVQ64rm addr:$src))>; + +// Misc. +let SchedRW = [SchedWriteShuffle.MMX] in { +let Uses = [EDI], Predicates = [HasMMX, HasSSE1,Not64BitMode] in +def MMX_MASKMOVQ : MMXI32<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), + "maskmovq\t{$mask, $src|$src, $mask}", + [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>; +let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in +def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), + "maskmovq\t{$mask, $src|$src, $mask}", + [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>; +} + +// 64-bit bit convert. +let Predicates = [HasMMX, HasSSE2] in { +def : Pat<(f64 (bitconvert (x86mmx VR64:$src))), + (MMX_MOVQ2FR64rr VR64:$src)>; +def : Pat<(x86mmx (bitconvert (f64 FR64:$src))), + (MMX_MOVFR642Qrr FR64:$src)>; +def : Pat<(x86mmx (MMX_X86movdq2q + (bc_v2i64 (v4i32 (X86cvtp2Int (v4f32 VR128:$src)))))), + (MMX_CVTPS2PIirr VR128:$src)>; +def : Pat<(x86mmx (MMX_X86movdq2q + (bc_v2i64 (v4i32 (X86cvttp2si (v4f32 VR128:$src)))))), + (MMX_CVTTPS2PIirr VR128:$src)>; +def : Pat<(x86mmx (MMX_X86movdq2q + (bc_v2i64 (v4i32 (fp_to_sint (v4f32 VR128:$src)))))), + (MMX_CVTTPS2PIirr VR128:$src)>; +def : Pat<(x86mmx (MMX_X86movdq2q + (bc_v2i64 (v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))), + (MMX_CVTPD2PIirr VR128:$src)>; +def : Pat<(x86mmx (MMX_X86movdq2q + (bc_v2i64 (v4i32 (X86cvttp2si (v2f64 VR128:$src)))))), + (MMX_CVTTPD2PIirr VR128:$src)>; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrMPX.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrMPX.td new file mode 100644 index 0000000..c1a8cc7 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrMPX.td @@ -0,0 +1,80 @@ +//===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 MPX instruction set, defining the +// instructions, and properties of the instructions which are needed for code +// generation, machine code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +// FIXME: Investigate a better scheduler class once MPX is used inside LLVM. +let SchedRW = [WriteSystem] in { + +multiclass mpx_bound_make opc, string OpcodeStr> { + def 32rm: I, + Requires<[HasMPX, Not64BitMode]>; + def 64rm: I, + Requires<[HasMPX, In64BitMode]>; +} + +defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS; + +multiclass mpx_bound_check opc, string OpcodeStr> { + def 32rm: I, + Requires<[HasMPX, Not64BitMode]>; + def 64rm: I, + Requires<[HasMPX, In64BitMode]>; + + def 32rr: I, + Requires<[HasMPX, Not64BitMode]>; + def 64rr: I, + Requires<[HasMPX, In64BitMode]>; +} +defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable; +defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable; +defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD, NotMemoryFoldable; + +def BNDMOVrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src), + "bndmov\t{$src, $dst|$dst, $src}", []>, PD, + Requires<[HasMPX]>, NotMemoryFoldable; +let mayLoad = 1 in { +def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src), + "bndmov\t{$src, $dst|$dst, $src}", []>, PD, + Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable; +def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src), + "bndmov\t{$src, $dst|$dst, $src}", []>, PD, + Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable; +} +let isCodeGenOnly = 1, ForceDisassemble = 1 in +def BNDMOVrr_REV : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src), + "bndmov\t{$src, $dst|$dst, $src}", []>, PD, + Requires<[HasMPX]>, NotMemoryFoldable; +let mayStore = 1 in { +def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src), + "bndmov\t{$src, $dst|$dst, $src}", []>, PD, + Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable; +def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src), + "bndmov\t{$src, $dst|$dst, $src}", []>, PD, + Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable; + +def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src), + "bndstx\t{$src, $dst|$dst, $src}", []>, PS, + Requires<[HasMPX]>; +} +let mayLoad = 1 in +def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src), + "bndldx\t{$src, $dst|$dst, $src}", []>, PS, + Requires<[HasMPX]>; +} // SchedRW diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrSGX.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrSGX.td new file mode 100644 index 0000000..488cc44 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrSGX.td @@ -0,0 +1,30 @@ +//===-- X86InstrSGX.td - SGX Instruction Set Extension -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the Intel SGX instruction +// set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// SGX instructions + +let SchedRW = [WriteSystem], Predicates = [HasSGX] in { +// ENCLS - Execute an Enclave System Function of Specified Leaf Number +def ENCLS : I<0x01, MRM_CF, (outs), (ins), + "encls", []>, TB; + +// ENCLU - Execute an Enclave User Function of Specified Leaf Number +def ENCLU : I<0x01, MRM_D7, (outs), (ins), + "enclu", []>, TB; + +// ENCLV - Execute an Enclave VMM Function of Specified Leaf Number +def ENCLV : I<0x01, MRM_C0, (outs), (ins), + "enclv", []>, TB; +} // SchedRW diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrSSE.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrSSE.td new file mode 100644 index 0000000..5c6b415 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrSSE.td @@ -0,0 +1,8258 @@ +//===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 SSE instruction set, defining the instructions, +// and properties of the instructions which are needed for code generation, +// machine code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 Instructions Classes +//===----------------------------------------------------------------------===// + +/// sse12_fp_scalar - SSE 1 & 2 scalar instructions class +multiclass sse12_fp_scalar opc, string OpcodeStr, SDNode OpNode, + RegisterClass RC, X86MemOperand x86memop, + Domain d, X86FoldableSchedWrite sched, + bit Is2Addr = 1> { + let isCommutable = 1 in { + def rr : SI, + Sched<[sched]>; + } + def rm : SI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +/// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class +multiclass sse12_fp_scalar_int opc, string OpcodeStr, + SDPatternOperator OpNode, RegisterClass RC, + ValueType VT, string asm, Operand memopr, + ComplexPattern mem_cpat, Domain d, + X86FoldableSchedWrite sched, bit Is2Addr = 1> { +let isCodeGenOnly = 1, hasSideEffects = 0 in { + def rr_Int : SI_Int, + Sched<[sched]>; + let mayLoad = 1 in + def rm_Int : SI_Int, + Sched<[sched.Folded, ReadAfterLd]>; +} +} + +/// sse12_fp_packed - SSE 1 & 2 packed instructions class +multiclass sse12_fp_packed opc, string OpcodeStr, SDNode OpNode, + RegisterClass RC, ValueType vt, + X86MemOperand x86memop, PatFrag mem_frag, + Domain d, X86FoldableSchedWrite sched, + bit Is2Addr = 1> { + let isCommutable = 1 in + def rr : PI, + Sched<[sched]>; + let mayLoad = 1 in + def rm : PI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +/// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class +multiclass sse12_fp_packed_logical_rm opc, RegisterClass RC, Domain d, + string OpcodeStr, X86MemOperand x86memop, + X86FoldableSchedWrite sched, + list pat_rr, list pat_rm, + bit Is2Addr = 1> { + let isCommutable = 1, hasSideEffects = 0 in + def rr : PI, + Sched<[sched]>; + let hasSideEffects = 0, mayLoad = 1 in + def rm : PI, + Sched<[sched.Folded, ReadAfterLd]>; +} + + +/* +// Alias instructions that map fld0 to xorps for sse or vxorps for avx. +// This is expanded by ExpandPostRAPseudos. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, SchedRW = [WriteZero] in { + def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "", + [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1, NoAVX512]>; + def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "", + [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2, NoAVX512]>; +} +*/ + +//===----------------------------------------------------------------------===// +// AVX & SSE - Zero/One Vectors +//===----------------------------------------------------------------------===// + +// Alias instruction that maps zero vector to pxor / xorp* for sse. +// This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then +// swizzled by ExecutionDomainFix to pxor. +// We set canFoldAsLoad because this can be converted to a constant-pool +// load of an all-zeros value if folding it would be beneficial. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, SchedRW = [WriteZero] in { +def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4f32 immAllZerosV))]>; +} + +let Predicates = [NoAVX512] in +def : Pat<(v4i32 immAllZerosV), (V_SET0)>; + + +// The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI, +// and doesn't need it because on sandy bridge the register is set to zero +// at the rename stage without using any execution unit, so SET0PSY +// and SET0PDY can be used for vector int instructions without penalty +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, Predicates = [NoAVX512], SchedRW = [WriteZero] in { +def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "", + [(set VR256:$dst, (v8i32 immAllZerosV))]>; +} + +// We set canFoldAsLoad because this can be converted to a constant-pool +// load of an all-ones value if folding it would be beneficial. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, SchedRW = [WriteZero] in { + def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4i32 immAllOnesV))]>; + let Predicates = [HasAVX1Only, OptForMinSize] in { + def AVX1_SETALLONES: I<0, Pseudo, (outs VR256:$dst), (ins), "", + [(set VR256:$dst, (v8i32 immAllOnesV))]>; + } + let Predicates = [HasAVX2] in + def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "", + [(set VR256:$dst, (v8i32 immAllOnesV))]>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Move FP Scalar Instructions +// +// Move Instructions. Register-to-register movss/movsd is not used for FR32/64 +// register copies because it's a partial register update; Register-to-register +// movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires +// that the insert be implementable in terms of a copy, and just mentioned, we +// don't use movss/movsd for copies. +//===----------------------------------------------------------------------===// + +multiclass sse12_move_rr { + let isCommutable = 1 in + def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + !strconcat(base_opc, asm_opr), + [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))], d>, + Sched<[SchedWriteFShuffle.XMM]>; + + // For the disassembler + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + !strconcat(base_opc, asm_opr), []>, + Sched<[SchedWriteFShuffle.XMM]>, FoldGenData; +} + +multiclass sse12_move { + // AVX + let Predicates = [UseAVX, OptForSize] in + defm V#NAME : sse12_move_rr, + VEX_4V, VEX_LIG, VEX_WIG; + + def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(store RC:$src, addr:$dst)], d>, + VEX, VEX_LIG, Sched<[WriteFStore]>, VEX_WIG; + // SSE1 & 2 + let Constraints = "$src1 = $dst" in { + let Predicates = [pred, NoSSE41_Or_OptForSize] in + defm NAME : sse12_move_rr; + } + + def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(store RC:$src, addr:$dst)], d>, + Sched<[WriteFStore]>; + + // def : InstAlias<"v"#OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", + // (!cast("V"#NAME#"rr_REV") + // VR128:$dst, VR128:$src1, VR128:$src2), 0>; + // def : InstAlias(NAME#"rr_REV") + // VR128:$dst, VR128:$src2), 0>; +} + +// Loading from memory automatically zeroing upper bits. +multiclass sse12_move_rm { + def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set RC:$dst, (mem_pat addr:$src))], d>, + VEX, VEX_LIG, Sched<[WriteFLoad]>, VEX_WIG; + def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set RC:$dst, (mem_pat addr:$src))], d>, + Sched<[WriteFLoad]>; +} + +defm MOVSS : sse12_move, XS; +defm MOVSD : sse12_move, XD; + +let canFoldAsLoad = 1, isReMaterializable = 1 in { + defm MOVSS : sse12_move_rm, XS; + defm MOVSD : sse12_move_rm, XD; +} + +// Patterns +let Predicates = [UseAVX] in { + // MOVSSrm zeros the high parts of the register; represent this + // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 + def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))), + (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>; + def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), + (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>; + def : Pat<(v4f32 (X86vzload addr:$src)), + (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>; + + // MOVSDrm zeros the high parts of the register; represent this + // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 + def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))), + (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>; + def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), + (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>; + def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), + (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>; + def : Pat<(v2f64 (X86vzload addr:$src)), + (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>; + + // Represent the same patterns above but in the form they appear for + // 256-bit types + def : Pat<(v8f32 (X86vzmovl (insert_subvector undef, + (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>; + def : Pat<(v8f32 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>; + def : Pat<(v4f64 (X86vzmovl (insert_subvector undef, + (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>; + def : Pat<(v4f64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>; + + // Extract and store. + def : Pat<(store (f32 (extractelt (v4f32 VR128:$src), (iPTR 0))), + addr:$dst), + (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>; +} + +let Predicates = [UseAVX, OptForSize] in { + // Move scalar to XMM zero-extended, zeroing a VR128 then do a + // MOVSS to the lower bits. + def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), + (VMOVSSrr (v4f32 (V_SET0)), VR128:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), + (VMOVSSrr (v4i32 (V_SET0)), VR128:$src)>; + + // Move low f32 and clear high bits. + def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v4f32 (VMOVSSrr (v4f32 (V_SET0)), + (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)))), sub_xmm)>; + def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v4i32 (VMOVSSrr (v4i32 (V_SET0)), + (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)))), sub_xmm)>; + + def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v2f64 (VMOVSDrr (v2f64 (V_SET0)), + (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)))), + sub_xmm)>; + def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v2i64 (VMOVSDrr (v2i64 (V_SET0)), + (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)))), + sub_xmm)>; +} + +let Predicates = [UseSSE1] in { + let Predicates = [UseSSE1, NoSSE41_Or_OptForSize] in { + // Move scalar to XMM zero-extended, zeroing a VR128 then do a + // MOVSS to the lower bits. + def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), + (MOVSSrr (v4f32 (V_SET0)), VR128:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), + (MOVSSrr (v4i32 (V_SET0)), VR128:$src)>; + } + + // MOVSSrm already zeros the high parts of the register. + def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))), + (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>; + def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), + (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>; + def : Pat<(v4f32 (X86vzload addr:$src)), + (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>; + + // Extract and store. + def : Pat<(store (f32 (extractelt (v4f32 VR128:$src), (iPTR 0))), + addr:$dst), + (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>; +} + +let Predicates = [UseSSE2] in { + // MOVSDrm already zeros the high parts of the register. + def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))), + (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>; + def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), + (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>; + def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), + (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>; + def : Pat<(v2f64 (X86vzload addr:$src)), + (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>; +} + +// Aliases to help the assembler pick two byte VEX encodings by swapping the +// operands relative to the normal instructions to use VEX.R instead of VEX.B. +// def : InstAlias<"vmovss\t{$src2, $src1, $dst|$dst, $src1, $src2}", +// (VMOVSSrr_REV VR128L:$dst, VR128:$src1, VR128H:$src2), 0>; +// def : InstAlias<"vmovsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", +// (VMOVSDrr_REV VR128L:$dst, VR128:$src1, VR128H:$src2), 0>; + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Move Aligned/Unaligned FP Instructions +//===----------------------------------------------------------------------===// + +multiclass sse12_mov_packed opc, RegisterClass RC, + X86MemOperand x86memop, PatFrag ld_frag, + string asm, Domain d, + X86SchedWriteMoveLS sched> { +let hasSideEffects = 0, isMoveReg = 1 in + def rr : PI, + Sched<[sched.RR]>; +let canFoldAsLoad = 1, isReMaterializable = 1 in + def rm : PI, + Sched<[sched.RM]>; +} + +let Predicates = [HasAVX, NoVLX] in { +defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32, "movaps", + SSEPackedSingle, SchedWriteFMoveLS.XMM>, + PS, VEX, VEX_WIG; +defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64, "movapd", + SSEPackedDouble, SchedWriteFMoveLS.XMM>, + PD, VEX, VEX_WIG; +defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32, "movups", + SSEPackedSingle, SchedWriteFMoveLS.XMM>, + PS, VEX, VEX_WIG; +defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64, "movupd", + SSEPackedDouble, SchedWriteFMoveLS.XMM>, + PD, VEX, VEX_WIG; + +defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32, "movaps", + SSEPackedSingle, SchedWriteFMoveLS.YMM>, + PS, VEX, VEX_L, VEX_WIG; +defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64, "movapd", + SSEPackedDouble, SchedWriteFMoveLS.YMM>, + PD, VEX, VEX_L, VEX_WIG; +defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32, "movups", + SSEPackedSingle, SchedWriteFMoveLS.YMM>, + PS, VEX, VEX_L, VEX_WIG; +defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64, "movupd", + SSEPackedDouble, SchedWriteFMoveLS.YMM>, + PD, VEX, VEX_L, VEX_WIG; +} + +let Predicates = [UseSSE1] in { +defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32, "movaps", + SSEPackedSingle, SchedWriteFMoveLS.XMM>, + PS; +defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32, "movups", + SSEPackedSingle, SchedWriteFMoveLS.XMM>, + PS; +} +let Predicates = [UseSSE2] in { +defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64, "movapd", + SSEPackedDouble, SchedWriteFMoveLS.XMM>, + PD; +defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64, "movupd", + SSEPackedDouble, SchedWriteFMoveLS.XMM>, + PD; +} + +let Predicates = [HasAVX, NoVLX] in { +let SchedRW = [SchedWriteFMoveLS.XMM.MR] in { +def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movaps\t{$src, $dst|$dst, $src}", + [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, + VEX, VEX_WIG; +def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movapd\t{$src, $dst|$dst, $src}", + [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, + VEX, VEX_WIG; +def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movups\t{$src, $dst|$dst, $src}", + [(store (v4f32 VR128:$src), addr:$dst)]>, + VEX, VEX_WIG; +def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movupd\t{$src, $dst|$dst, $src}", + [(store (v2f64 VR128:$src), addr:$dst)]>, + VEX, VEX_WIG; +} // SchedRW + +let SchedRW = [SchedWriteFMoveLS.YMM.MR] in { +def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src), + "movaps\t{$src, $dst|$dst, $src}", + [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, + VEX, VEX_L, VEX_WIG; +def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src), + "movapd\t{$src, $dst|$dst, $src}", + [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, + VEX, VEX_L, VEX_WIG; +def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src), + "movups\t{$src, $dst|$dst, $src}", + [(store (v8f32 VR256:$src), addr:$dst)]>, + VEX, VEX_L, VEX_WIG; +def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src), + "movupd\t{$src, $dst|$dst, $src}", + [(store (v4f64 VR256:$src), addr:$dst)]>, + VEX, VEX_L, VEX_WIG; +} // SchedRW +} // Predicate + +// For disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, + isMoveReg = 1 in { +let SchedRW = [SchedWriteFMoveLS.XMM.RR] in { + def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst), + (ins VR128:$src), + "movaps\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_WIG, FoldGenData<"VMOVAPSrr">; + def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst), + (ins VR128:$src), + "movapd\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_WIG, FoldGenData<"VMOVAPDrr">; + def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst), + (ins VR128:$src), + "movups\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_WIG, FoldGenData<"VMOVUPSrr">; + def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst), + (ins VR128:$src), + "movupd\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_WIG, FoldGenData<"VMOVUPDrr">; +} // SchedRW + +let SchedRW = [SchedWriteFMoveLS.YMM.RR] in { + def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst), + (ins VR256:$src), + "movaps\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_L, VEX_WIG, FoldGenData<"VMOVAPSYrr">; + def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst), + (ins VR256:$src), + "movapd\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_L, VEX_WIG, FoldGenData<"VMOVAPDYrr">; + def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst), + (ins VR256:$src), + "movups\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_L, VEX_WIG, FoldGenData<"VMOVUPSYrr">; + def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst), + (ins VR256:$src), + "movupd\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_L, VEX_WIG, FoldGenData<"VMOVUPDYrr">; +} // SchedRW +} // Predicate + +// Aliases to help the assembler pick two byte VEX encodings by swapping the +// operands relative to the normal instructions to use VEX.R instead of VEX.B. +// def : InstAlias<"vmovaps\t{$src, $dst|$dst, $src}", +// (VMOVAPSrr_REV VR128L:$dst, VR128H:$src), 0>; +// def : InstAlias<"vmovapd\t{$src, $dst|$dst, $src}", +// (VMOVAPDrr_REV VR128L:$dst, VR128H:$src), 0>; +// def : InstAlias<"vmovups\t{$src, $dst|$dst, $src}", +// (VMOVUPSrr_REV VR128L:$dst, VR128H:$src), 0>; +// def : InstAlias<"vmovupd\t{$src, $dst|$dst, $src}", +// (VMOVUPDrr_REV VR128L:$dst, VR128H:$src), 0>; +// def : InstAlias<"vmovaps\t{$src, $dst|$dst, $src}", +// (VMOVAPSYrr_REV VR256L:$dst, VR256H:$src), 0>; +// def : InstAlias<"vmovapd\t{$src, $dst|$dst, $src}", +// (VMOVAPDYrr_REV VR256L:$dst, VR256H:$src), 0>; +// def : InstAlias<"vmovups\t{$src, $dst|$dst, $src}", +// (VMOVUPSYrr_REV VR256L:$dst, VR256H:$src), 0>; +// def : InstAlias<"vmovupd\t{$src, $dst|$dst, $src}", +// (VMOVUPDYrr_REV VR256L:$dst, VR256H:$src), 0>; + +// Reversed version with ".s" suffix for GAS compatibility. +// def : InstAlias<"vmovaps.s\t{$src, $dst|$dst, $src}", +// (VMOVAPSrr_REV VR128:$dst, VR128:$src), 0>; +// def : InstAlias<"vmovapd.s\t{$src, $dst|$dst, $src}", +// (VMOVAPDrr_REV VR128:$dst, VR128:$src), 0>; +// def : InstAlias<"vmovups.s\t{$src, $dst|$dst, $src}", +// (VMOVUPSrr_REV VR128:$dst, VR128:$src), 0>; +// def : InstAlias<"vmovupd.s\t{$src, $dst|$dst, $src}", +// (VMOVUPDrr_REV VR128:$dst, VR128:$src), 0>; +// def : InstAlias<"vmovaps.s\t{$src, $dst|$dst, $src}", +// (VMOVAPSYrr_REV VR256:$dst, VR256:$src), 0>; +// def : InstAlias<"vmovapd.s\t{$src, $dst|$dst, $src}", +// (VMOVAPDYrr_REV VR256:$dst, VR256:$src), 0>; +// def : InstAlias<"vmovups.s\t{$src, $dst|$dst, $src}", +// (VMOVUPSYrr_REV VR256:$dst, VR256:$src), 0>; +// def : InstAlias<"vmovupd.s\t{$src, $dst|$dst, $src}", +// (VMOVUPDYrr_REV VR256:$dst, VR256:$src), 0>; + +let SchedRW = [SchedWriteFMoveLS.XMM.MR] in { +def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movaps\t{$src, $dst|$dst, $src}", + [(alignedstore (v4f32 VR128:$src), addr:$dst)]>; +def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movapd\t{$src, $dst|$dst, $src}", + [(alignedstore (v2f64 VR128:$src), addr:$dst)]>; +def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movups\t{$src, $dst|$dst, $src}", + [(store (v4f32 VR128:$src), addr:$dst)]>; +def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movupd\t{$src, $dst|$dst, $src}", + [(store (v2f64 VR128:$src), addr:$dst)]>; +} // SchedRW + +// For disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, + isMoveReg = 1, SchedRW = [SchedWriteFMoveLS.XMM.RR] in { + def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movaps\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOVAPSrr">; + def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movapd\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOVAPDrr">; + def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movups\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOVUPSrr">; + def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movupd\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOVUPDrr">; +} + +// Reversed version with ".s" suffix for GAS compatibility. +// def : InstAlias<"movaps.s\t{$src, $dst|$dst, $src}", +// (MOVAPSrr_REV VR128:$dst, VR128:$src), 0>; +// def : InstAlias<"movapd.s\t{$src, $dst|$dst, $src}", +// (MOVAPDrr_REV VR128:$dst, VR128:$src), 0>; +// def : InstAlias<"movups.s\t{$src, $dst|$dst, $src}", +// (MOVUPSrr_REV VR128:$dst, VR128:$src), 0>; +// def : InstAlias<"movupd.s\t{$src, $dst|$dst, $src}", +// (MOVUPDrr_REV VR128:$dst, VR128:$src), 0>; + +let Predicates = [HasAVX, NoVLX] in { + // 256-bit load/store need to use floating point load/store in case we don't + // have AVX2. Execution domain fixing will convert to integer if AVX2 is + // available and changing the domain is beneficial. + def : Pat<(alignedloadv4i64 addr:$src), + (VMOVAPSYrm addr:$src)>; + def : Pat<(loadv4i64 addr:$src), + (VMOVUPSYrm addr:$src)>; + def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst), + (VMOVAPSYmr addr:$dst, VR256:$src)>; + def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst), + (VMOVAPSYmr addr:$dst, VR256:$src)>; + def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst), + (VMOVAPSYmr addr:$dst, VR256:$src)>; + def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst), + (VMOVAPSYmr addr:$dst, VR256:$src)>; + def : Pat<(store (v4i64 VR256:$src), addr:$dst), + (VMOVUPSYmr addr:$dst, VR256:$src)>; + def : Pat<(store (v8i32 VR256:$src), addr:$dst), + (VMOVUPSYmr addr:$dst, VR256:$src)>; + def : Pat<(store (v16i16 VR256:$src), addr:$dst), + (VMOVUPSYmr addr:$dst, VR256:$src)>; + def : Pat<(store (v32i8 VR256:$src), addr:$dst), + (VMOVUPSYmr addr:$dst, VR256:$src)>; +} + +// Use movaps / movups for SSE integer load / store (one byte shorter). +// The instructions selected below are then converted to MOVDQA/MOVDQU +// during the SSE domain pass. +let Predicates = [UseSSE1] in { + def : Pat<(alignedloadv2i64 addr:$src), + (MOVAPSrm addr:$src)>; + def : Pat<(loadv2i64 addr:$src), + (MOVUPSrm addr:$src)>; + + def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v2i64 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v4i32 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v8i16 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v16i8 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, VR128:$src)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Move Low packed FP Instructions +//===----------------------------------------------------------------------===// + +multiclass sse12_mov_hilo_packed_baseopc, SDNode pdnode, + string base_opc, string asm_opr> { + // No pattern as they need be special cased between high and low. + let hasSideEffects = 0, mayLoad = 1 in + def PSrm : PI, PS, + Sched<[SchedWriteFShuffle.XMM.Folded, ReadAfterLd]>; + + def PDrm : PI, PD, + Sched<[SchedWriteFShuffle.XMM.Folded, ReadAfterLd]>; +} + +multiclass sse12_mov_hilo_packedopc, SDPatternOperator pdnode, + string base_opc> { + let Predicates = [UseAVX] in + defm V#NAME : sse12_mov_hilo_packed_base, + VEX_4V, VEX_WIG; + + let Constraints = "$src1 = $dst" in + defm NAME : sse12_mov_hilo_packed_base; +} + +defm MOVL : sse12_mov_hilo_packed<0x12, X86Movsd, "movlp">; + +let SchedRW = [WriteFStore] in { +let Predicates = [UseAVX] in { +def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movlps\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt (bc_v2f64 (v4f32 VR128:$src)), + (iPTR 0))), addr:$dst)]>, + VEX, VEX_WIG; +def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movlpd\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt (v2f64 VR128:$src), + (iPTR 0))), addr:$dst)]>, + VEX, VEX_WIG; +}// UseAVX +def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movlps\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt (bc_v2f64 (v4f32 VR128:$src)), + (iPTR 0))), addr:$dst)]>; +def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movlpd\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt (v2f64 VR128:$src), + (iPTR 0))), addr:$dst)]>; +} // SchedRW + +let Predicates = [UseSSE1] in { + // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS + def : Pat<(store (i64 (extractelt (bc_v2i64 (v4f32 VR128:$src2)), + (iPTR 0))), addr:$src1), + (MOVLPSmr addr:$src1, VR128:$src2)>; + + // This pattern helps select MOVLPS on SSE1 only targets. With SSE2 we'll + // end up with a movsd or blend instead of shufp. + // No need for aligned load, we're only loading 64-bits. + def : Pat<(X86Shufp (loadv4f32 addr:$src2), VR128:$src1, (i8 -28)), + (MOVLPSrm VR128:$src1, addr:$src2)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Move Hi packed FP Instructions +//===----------------------------------------------------------------------===// + +defm MOVH : sse12_mov_hilo_packed<0x16, X86Unpckl, "movhp">; + +let SchedRW = [WriteFStore] in { +// v2f64 extract element 1 is always custom lowered to unpack high to low +// and extract element 0 so the non-store version isn't too horrible. +let Predicates = [UseAVX] in { +def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movhps\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt + (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)), + (bc_v2f64 (v4f32 VR128:$src))), + (iPTR 0))), addr:$dst)]>, VEX, VEX_WIG; +def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movhpd\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt + (v2f64 (X86Unpckh VR128:$src, VR128:$src)), + (iPTR 0))), addr:$dst)]>, VEX, VEX_WIG; +} // UseAVX +def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movhps\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt + (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)), + (bc_v2f64 (v4f32 VR128:$src))), + (iPTR 0))), addr:$dst)]>; +def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movhpd\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt + (v2f64 (X86Unpckh VR128:$src, VR128:$src)), + (iPTR 0))), addr:$dst)]>; +} // SchedRW + +let Predicates = [UseAVX] in { + // Also handle an i64 load because that may get selected as a faster way to + // load the data. + def : Pat<(v2f64 (X86Unpckl VR128:$src1, + (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))), + (VMOVHPDrm VR128:$src1, addr:$src2)>; + + def : Pat<(store (f64 (extractelt + (v2f64 (X86VPermilpi VR128:$src, (i8 1))), + (iPTR 0))), addr:$dst), + (VMOVHPDmr addr:$dst, VR128:$src)>; +} + +let Predicates = [UseSSE1] in { + // This pattern helps select MOVHPS on SSE1 only targets. With SSE2 we'll + // end up with a movsd or blend instead of shufp. + // No need for aligned load, we're only loading 64-bits. + def : Pat<(X86Movlhps VR128:$src1, (loadv4f32 addr:$src2)), + (MOVHPSrm VR128:$src1, addr:$src2)>; +} + +let Predicates = [UseSSE2] in { + // MOVHPD patterns + + // Also handle an i64 load because that may get selected as a faster way to + // load the data. + def : Pat<(v2f64 (X86Unpckl VR128:$src1, + (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))), + (MOVHPDrm VR128:$src1, addr:$src2)>; + + def : Pat<(store (f64 (extractelt + (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))), + (iPTR 0))), addr:$dst), + (MOVHPDmr addr:$dst, VR128:$src)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [UseAVX] in { + def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))]>, + VEX_4V, Sched<[SchedWriteFShuffle.XMM]>, VEX_WIG; + let isCommutable = 1 in + def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))]>, + VEX_4V, Sched<[SchedWriteFShuffle.XMM]>, VEX_WIG, + NotMemoryFoldable; +} +let Constraints = "$src1 = $dst" in { + def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + "movlhps\t{$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))]>, + Sched<[SchedWriteFShuffle.XMM]>; + let isCommutable = 1 in + def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + "movhlps\t{$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))]>, + Sched<[SchedWriteFShuffle.XMM]>, NotMemoryFoldable; +} + +// TODO: This is largely to trick fastisel into ignoring the pattern. +def UnpckhUnary : PatFrag<(ops node:$src1, node:$src2), + (X86Unpckh node:$src1, node:$src2), [{ + return N->getOperand(0) == N->getOperand(1); +}]>; + +let Predicates = [UseSSE2] in { + // TODO: This is a hack pattern to allow lowering to emit unpckh instead of + // movhlps for sse2 without changing a bunch of tests. + def : Pat<(v2f64 (UnpckhUnary VR128:$src, VR128:$src)), + (MOVHLPSrr VR128:$src, VR128:$src)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Conversion Instructions +//===----------------------------------------------------------------------===// + +multiclass sse12_cvt_s opc, RegisterClass SrcRC, RegisterClass DstRC, + SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag, + string asm, X86FoldableSchedWrite sched> { + def rr : SI, + Sched<[sched]>; + def rm : SI, + Sched<[sched.Folded]>; +} + +multiclass sse12_cvt_p opc, RegisterClass RC, X86MemOperand x86memop, + ValueType DstTy, ValueType SrcTy, PatFrag ld_frag, + string asm, Domain d, X86FoldableSchedWrite sched> { +let hasSideEffects = 0 in { + def rr : I, + Sched<[sched]>; + let mayLoad = 1 in + def rm : I, + Sched<[sched.Folded]>; +} +} + +multiclass sse12_vcvt_avx opc, RegisterClass SrcRC, RegisterClass DstRC, + X86MemOperand x86memop, string asm, + X86FoldableSchedWrite sched> { +let hasSideEffects = 0, Predicates = [UseAVX] in { + def rr : SI, + Sched<[sched]>; + let mayLoad = 1 in + def rm : SI, + Sched<[sched.Folded, ReadAfterLd]>; +} // hasSideEffects = 0 +} + +let Predicates = [UseAVX] in { +defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32, + "cvttss2si\t{$src, $dst|$dst, $src}", + WriteCvtSS2I>, + XS, VEX, VEX_LIG; +defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32, + "cvttss2si\t{$src, $dst|$dst, $src}", + WriteCvtSS2I>, + XS, VEX, VEX_W, VEX_LIG; +defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64, + "cvttsd2si\t{$src, $dst|$dst, $src}", + WriteCvtSD2I>, + XD, VEX, VEX_LIG; +defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64, + "cvttsd2si\t{$src, $dst|$dst, $src}", + WriteCvtSD2I>, + XD, VEX, VEX_W, VEX_LIG; + +// def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}", +// (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0, "att">; +// def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}", +// (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0, "att">; +// def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}", +// (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0, "att">; +// def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}", +// (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0, "att">; +// def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}", +// (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0, "att">; +// def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}", +// (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0, "att">; +// def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}", +// (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0, "att">; +// def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}", +// (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0, "att">; +} +// The assembler can recognize rr 64-bit instructions by seeing a rxx +// register, but the same isn't true when only using memory operands, +// provide other assembly "l" and "q" forms to address this explicitly +// where appropriate to do so. +defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}", + WriteCvtI2SS>, XS, VEX_4V, VEX_LIG; +defm VCVTSI642SS : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}", + WriteCvtI2SS>, XS, VEX_4V, VEX_W, VEX_LIG; +defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}", + WriteCvtI2SD>, XD, VEX_4V, VEX_LIG; +defm VCVTSI642SD : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}", + WriteCvtI2SD>, XD, VEX_4V, VEX_W, VEX_LIG; + +let Predicates = [UseAVX] in { + // def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}", + // (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0, "att">; + // def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}", + // (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0, "att">; + + def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))), + (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>; + def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))), + (VCVTSI642SSrm (f32 (IMPLICIT_DEF)), addr:$src)>; + def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))), + (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>; + def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))), + (VCVTSI642SDrm (f64 (IMPLICIT_DEF)), addr:$src)>; + + def : Pat<(f32 (sint_to_fp GR32:$src)), + (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>; + def : Pat<(f32 (sint_to_fp GR64:$src)), + (VCVTSI642SSrr (f32 (IMPLICIT_DEF)), GR64:$src)>; + def : Pat<(f64 (sint_to_fp GR32:$src)), + (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>; + def : Pat<(f64 (sint_to_fp GR64:$src)), + (VCVTSI642SDrr (f64 (IMPLICIT_DEF)), GR64:$src)>; +} + +defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32, + "cvttss2si\t{$src, $dst|$dst, $src}", + WriteCvtSS2I>, XS; +defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32, + "cvttss2si\t{$src, $dst|$dst, $src}", + WriteCvtSS2I>, XS, REX_W; +defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64, + "cvttsd2si\t{$src, $dst|$dst, $src}", + WriteCvtSD2I>, XD; +defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64, + "cvttsd2si\t{$src, $dst|$dst, $src}", + WriteCvtSD2I>, XD, REX_W; +defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32, + "cvtsi2ss{l}\t{$src, $dst|$dst, $src}", + WriteCvtI2SS>, XS; +defm CVTSI642SS : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64, + "cvtsi2ss{q}\t{$src, $dst|$dst, $src}", + WriteCvtI2SS>, XS, REX_W; +defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32, + "cvtsi2sd{l}\t{$src, $dst|$dst, $src}", + WriteCvtI2SD>, XD; +defm CVTSI642SD : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64, + "cvtsi2sd{q}\t{$src, $dst|$dst, $src}", + WriteCvtI2SD>, XD, REX_W; + +// def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}", +// (CVTTSS2SIrr GR32:$dst, FR32:$src), 0, "att">; +// def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}", +// (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0, "att">; +// def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}", +// (CVTTSD2SIrr GR32:$dst, FR64:$src), 0, "att">; +// def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}", +// (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0, "att">; +// def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}", +// (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0, "att">; +// def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}", +// (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0, "att">; +// def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}", +// (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0, "att">; +// def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}", +// (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0, "att">; + +// def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}", +// (CVTSI2SSrm FR64:$dst, i32mem:$src), 0, "att">; +// def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}", +// (CVTSI2SDrm FR64:$dst, i32mem:$src), 0, "att">; + +// Conversion Instructions Intrinsics - Match intrinsics which expect MM +// and/or XMM operand(s). + +// FIXME: We probably want to match the rm form only when optimizing for +// size, to avoid false dependencies (see sse_fp_unop_s for details) +multiclass sse12_cvt_sint opc, RegisterClass SrcRC, RegisterClass DstRC, + Intrinsic Int, Operand memop, ComplexPattern mem_cpat, + string asm, X86FoldableSchedWrite sched> { + def rr_Int : SI, + Sched<[sched]>; + def rm_Int : SI, + Sched<[sched.Folded]>; +} + +multiclass sse12_cvt_sint_3addr opc, RegisterClass SrcRC, + RegisterClass DstRC, X86MemOperand x86memop, + string asm, X86FoldableSchedWrite sched, + bit Is2Addr = 1> { +let hasSideEffects = 0 in { + def rr_Int : SI, Sched<[sched]>; + let mayLoad = 1 in + def rm_Int : SI, Sched<[sched.Folded, ReadAfterLd]>; +} +} + +let Predicates = [UseAVX] in { +defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, + int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si", + WriteCvtSD2I>, XD, VEX, VEX_LIG; +defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, + int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si", + WriteCvtSD2I>, XD, VEX, VEX_W, VEX_LIG; +} +defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si, + sdmem, sse_load_f64, "cvtsd2si", WriteCvtSD2I>, XD; +defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64, + sdmem, sse_load_f64, "cvtsd2si", WriteCvtSD2I>, XD, REX_W; + + +let isCodeGenOnly = 1 in { + let Predicates = [UseAVX] in { + defm VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128, + i32mem, "cvtsi2ss{l}", WriteCvtI2SS, 0>, XS, VEX_4V; + defm VCVTSI642SS : sse12_cvt_sint_3addr<0x2A, GR64, VR128, + i64mem, "cvtsi2ss{q}", WriteCvtI2SS, 0>, XS, VEX_4V, VEX_W; + defm VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128, + i32mem, "cvtsi2sd{l}", WriteCvtI2SD, 0>, XD, VEX_4V; + defm VCVTSI642SD : sse12_cvt_sint_3addr<0x2A, GR64, VR128, + i64mem, "cvtsi2sd{q}", WriteCvtI2SD, 0>, XD, VEX_4V, VEX_W; + } + let Constraints = "$src1 = $dst" in { + defm CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128, + i32mem, "cvtsi2ss{l}", WriteCvtI2SS>, XS; + defm CVTSI642SS : sse12_cvt_sint_3addr<0x2A, GR64, VR128, + i64mem, "cvtsi2ss{q}", WriteCvtI2SS>, XS, REX_W; + defm CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128, + i32mem, "cvtsi2sd{l}", WriteCvtI2SD>, XD; + defm CVTSI642SD : sse12_cvt_sint_3addr<0x2A, GR64, VR128, + i64mem, "cvtsi2sd{q}", WriteCvtI2SD>, XD, REX_W; + } +} // isCodeGenOnly = 1 + +/// SSE 1 Only + +// Aliases for intrinsics +let isCodeGenOnly = 1 in { +let Predicates = [UseAVX] in { +defm VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si, + ssmem, sse_load_f32, "cvttss2si", + WriteCvtSS2I>, XS, VEX; +defm VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, + int_x86_sse_cvttss2si64, ssmem, sse_load_f32, + "cvttss2si", WriteCvtSS2I>, + XS, VEX, VEX_W; +defm VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si, + sdmem, sse_load_f64, "cvttsd2si", + WriteCvtSS2I>, XD, VEX; +defm VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, + int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64, + "cvttsd2si", WriteCvtSS2I>, + XD, VEX, VEX_W; +} +defm CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si, + ssmem, sse_load_f32, "cvttss2si", + WriteCvtSS2I>, XS; +defm CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, + int_x86_sse_cvttss2si64, ssmem, sse_load_f32, + "cvttss2si", WriteCvtSS2I>, XS, REX_W; +defm CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si, + sdmem, sse_load_f64, "cvttsd2si", + WriteCvtSD2I>, XD; +defm CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, + int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64, + "cvttsd2si", WriteCvtSD2I>, XD, REX_W; +} // isCodeGenOnly = 1 + +let Predicates = [UseAVX] in { +defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si, + ssmem, sse_load_f32, "cvtss2si", + WriteCvtSS2I>, XS, VEX, VEX_LIG; +defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64, + ssmem, sse_load_f32, "cvtss2si", + WriteCvtSS2I>, XS, VEX, VEX_W, VEX_LIG; +} +defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si, + ssmem, sse_load_f32, "cvtss2si", + WriteCvtSS2I>, XS; +defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64, + ssmem, sse_load_f32, "cvtss2si", + WriteCvtSS2I>, XS, REX_W; + +defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, i128mem, v4f32, v4i32, loadv2i64, + "vcvtdq2ps\t{$src, $dst|$dst, $src}", + SSEPackedSingle, WriteCvtI2PS>, + PS, VEX, Requires<[HasAVX, NoVLX]>, VEX_WIG; +defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, i256mem, v8f32, v8i32, loadv4i64, + "vcvtdq2ps\t{$src, $dst|$dst, $src}", + SSEPackedSingle, WriteCvtI2PSY>, + PS, VEX, VEX_L, Requires<[HasAVX, NoVLX]>, VEX_WIG; + +defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, i128mem, v4f32, v4i32, memopv2i64, + "cvtdq2ps\t{$src, $dst|$dst, $src}", + SSEPackedSingle, WriteCvtI2PS>, + PS, Requires<[UseSSE2]>; + +let Predicates = [UseAVX] in { +// def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}", +// (VCVTSS2SIrr_Int GR32:$dst, VR128:$src), 0, "att">; +// def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}", +// (VCVTSS2SIrm_Int GR32:$dst, ssmem:$src), 0, "att">; +// def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}", +// (VCVTSD2SIrr_Int GR32:$dst, VR128:$src), 0, "att">; +// def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}", +// (VCVTSD2SIrm_Int GR32:$dst, sdmem:$src), 0, "att">; +// def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}", +// (VCVTSS2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">; +// def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}", +// (VCVTSS2SI64rm_Int GR64:$dst, ssmem:$src), 0, "att">; +// def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}", +// (VCVTSD2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">; +// def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}", +// (VCVTSD2SI64rm_Int GR64:$dst, sdmem:$src), 0, "att">; +} + +// def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}", +// (CVTSS2SIrr_Int GR32:$dst, VR128:$src), 0, "att">; +// def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}", +// (CVTSS2SIrm_Int GR32:$dst, ssmem:$src), 0, "att">; +// def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}", +// (CVTSD2SIrr_Int GR32:$dst, VR128:$src), 0, "att">; +// def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}", +// (CVTSD2SIrm_Int GR32:$dst, sdmem:$src), 0, "att">; +// def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}", +// (CVTSS2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">; +// def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}", +// (CVTSS2SI64rm_Int GR64:$dst, ssmem:$src), 0, "att">; +// def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}", +// (CVTSD2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">; +// def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}", +// (CVTSD2SI64rm_Int GR64:$dst, sdmem:$src), 0, "att">; + +/// SSE 2 Only + +// Convert scalar double to scalar single +let hasSideEffects = 0, Predicates = [UseAVX] in { +def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst), + (ins FR32:$src1, FR64:$src2), + "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + VEX_4V, VEX_LIG, VEX_WIG, + Sched<[WriteCvtSD2SS]>; +let mayLoad = 1 in +def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), + (ins FR32:$src1, f64mem:$src2), + "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + XD, VEX_4V, VEX_LIG, VEX_WIG, + Sched<[WriteCvtSD2SS.Folded, ReadAfterLd]>; +} + +def : Pat<(f32 (fpround FR64:$src)), + (VCVTSD2SSrr (f32 (IMPLICIT_DEF)), FR64:$src)>, + Requires<[UseAVX]>; + +def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src), + "cvtsd2ss\t{$src, $dst|$dst, $src}", + [(set FR32:$dst, (fpround FR64:$src))]>, + Sched<[WriteCvtSD2SS]>; +def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src), + "cvtsd2ss\t{$src, $dst|$dst, $src}", + [(set FR32:$dst, (fpround (loadf64 addr:$src)))]>, + XD, Requires<[UseSSE2, OptForSize]>, + Sched<[WriteCvtSD2SS.Folded]>; + +let isCodeGenOnly = 1 in { +def VCVTSD2SSrr_Int: I<0x5A, MRMSrcReg, + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), + "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))]>, + XD, VEX_4V, VEX_WIG, Requires<[HasAVX]>, + Sched<[WriteCvtSD2SS]>; +def VCVTSD2SSrm_Int: I<0x5A, MRMSrcMem, + (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2), + "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, (int_x86_sse2_cvtsd2ss + VR128:$src1, sse_load_f64:$src2))]>, + XD, VEX_4V, VEX_WIG, Requires<[HasAVX]>, + Sched<[WriteCvtSD2SS.Folded, ReadAfterLd]>; +let Constraints = "$src1 = $dst" in { +def CVTSD2SSrr_Int: I<0x5A, MRMSrcReg, + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), + "cvtsd2ss\t{$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))]>, + XD, Requires<[UseSSE2]>, Sched<[WriteCvtSD2SS]>; +def CVTSD2SSrm_Int: I<0x5A, MRMSrcMem, + (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2), + "cvtsd2ss\t{$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_cvtsd2ss + VR128:$src1, sse_load_f64:$src2))]>, + XD, Requires<[UseSSE2]>, + Sched<[WriteCvtSD2SS.Folded, ReadAfterLd]>; +} +} // isCodeGenOnly = 1 + +// Convert scalar single to scalar double +// SSE2 instructions with XS prefix +let hasSideEffects = 0 in { +def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), + (ins FR64:$src1, FR32:$src2), + "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + XS, VEX_4V, VEX_LIG, VEX_WIG, + Sched<[WriteCvtSS2SD]>, Requires<[UseAVX]>; +let mayLoad = 1 in +def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), + (ins FR64:$src1, f32mem:$src2), + "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + XS, VEX_4V, VEX_LIG, VEX_WIG, + Sched<[WriteCvtSS2SD.Folded, ReadAfterLd]>, + Requires<[UseAVX, OptForSize]>; +} + +def : Pat<(f64 (fpextend FR32:$src)), + (VCVTSS2SDrr (f64 (IMPLICIT_DEF)), FR32:$src)>, Requires<[UseAVX]>; +def : Pat<(fpextend (loadf32 addr:$src)), + (VCVTSS2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX, OptForSize]>; + +def : Pat<(extloadf32 addr:$src), + (VCVTSS2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>, + Requires<[UseAVX, OptForSize]>; +def : Pat<(extloadf32 addr:$src), + (VCVTSS2SDrr (f64 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>, + Requires<[UseAVX, OptForSpeed]>; + +def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src), + "cvtss2sd\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (fpextend FR32:$src))]>, + XS, Requires<[UseSSE2]>, Sched<[WriteCvtSS2SD]>; +def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src), + "cvtss2sd\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (extloadf32 addr:$src))]>, + XS, Requires<[UseSSE2, OptForSize]>, + Sched<[WriteCvtSS2SD.Folded]>; + +// extload f32 -> f64. This matches load+fpextend because we have a hack in +// the isel (PreprocessForFPConvert) that can introduce loads after dag +// combine. +// Since these loads aren't folded into the fpextend, we have to match it +// explicitly here. +def : Pat<(fpextend (loadf32 addr:$src)), + (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2, OptForSize]>; +def : Pat<(extloadf32 addr:$src), + (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>; + +let isCodeGenOnly = 1, hasSideEffects = 0 in { +def VCVTSS2SDrr_Int: I<0x5A, MRMSrcReg, + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), + "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, XS, VEX_4V, VEX_WIG, + Requires<[HasAVX]>, Sched<[WriteCvtSS2SD]>; +let mayLoad = 1 in +def VCVTSS2SDrm_Int: I<0x5A, MRMSrcMem, + (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2), + "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, XS, VEX_4V, VEX_WIG, Requires<[HasAVX]>, + Sched<[WriteCvtSS2SD.Folded, ReadAfterLd]>; +let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix +def CVTSS2SDrr_Int: I<0x5A, MRMSrcReg, + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), + "cvtss2sd\t{$src2, $dst|$dst, $src2}", + []>, XS, Requires<[UseSSE2]>, + Sched<[WriteCvtSS2SD]>; +let mayLoad = 1 in +def CVTSS2SDrm_Int: I<0x5A, MRMSrcMem, + (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2), + "cvtss2sd\t{$src2, $dst|$dst, $src2}", + []>, XS, Requires<[UseSSE2]>, + Sched<[WriteCvtSS2SD.Folded, ReadAfterLd]>; +} +} // isCodeGenOnly = 1 + +// Patterns used for matching (v)cvtsi2ss, (v)cvtsi2sd, (v)cvtsd2ss and +// (v)cvtss2sd intrinsic sequences from clang which produce unnecessary +// vmovs{s,d} instructions +let Predicates = [UseAVX] in { +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector + (f32 (fpround (f64 (extractelt VR128:$src, (iPTR 0))))))))), + (VCVTSD2SSrr_Int VR128:$dst, VR128:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector + (f64 (fpextend (f32 (extractelt VR128:$src, (iPTR 0))))))))), + (VCVTSS2SDrr_Int VR128:$dst, VR128:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp GR64:$src)))))), + (VCVTSI642SSrr_Int VR128:$dst, GR64:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi64 addr:$src))))))), + (VCVTSI642SSrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp GR32:$src)))))), + (VCVTSI2SSrr_Int VR128:$dst, GR32:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi32 addr:$src))))))), + (VCVTSI2SSrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp GR64:$src)))))), + (VCVTSI642SDrr_Int VR128:$dst, GR64:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi64 addr:$src))))))), + (VCVTSI642SDrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp GR32:$src)))))), + (VCVTSI2SDrr_Int VR128:$dst, GR32:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi32 addr:$src))))))), + (VCVTSI2SDrm_Int VR128:$dst, addr:$src)>; +} // Predicates = [UseAVX] + +let Predicates = [UseSSE2] in { +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector + (f32 (fpround (f64 (extractelt VR128:$src, (iPTR 0))))))))), + (CVTSD2SSrr_Int VR128:$dst, VR128:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector + (f64 (fpextend (f32 (extractelt VR128:$src, (iPTR 0))))))))), + (CVTSS2SDrr_Int VR128:$dst, VR128:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp GR64:$src)))))), + (CVTSI642SDrr_Int VR128:$dst, GR64:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi64 addr:$src))))))), + (CVTSI642SDrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp GR32:$src)))))), + (CVTSI2SDrr_Int VR128:$dst, GR32:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi32 addr:$src))))))), + (CVTSI2SDrm_Int VR128:$dst, addr:$src)>; +} // Predicates = [UseSSE2] + +let Predicates = [UseSSE1] in { +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp GR64:$src)))))), + (CVTSI642SSrr_Int VR128:$dst, GR64:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi64 addr:$src))))))), + (CVTSI642SSrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp GR32:$src)))))), + (CVTSI2SSrr_Int VR128:$dst, GR32:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi32 addr:$src))))))), + (CVTSI2SSrm_Int VR128:$dst, addr:$src)>; +} // Predicates = [UseSSE1] + +let Predicates = [HasAVX, NoVLX] in { +// Convert packed single/double fp to doubleword +def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v4i32 (X86cvtp2Int (v4f32 VR128:$src))))]>, + VEX, Sched<[WriteCvtPS2I]>, VEX_WIG; +def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (loadv4f32 addr:$src))))]>, + VEX, Sched<[WriteCvtPS2ILd]>, VEX_WIG; +def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, + (v8i32 (X86cvtp2Int (v8f32 VR256:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPS2IY]>, VEX_WIG; +def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, + (v8i32 (X86cvtp2Int (loadv8f32 addr:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPS2IYLd]>, VEX_WIG; +} +def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v4i32 (X86cvtp2Int (v4f32 VR128:$src))))]>, + Sched<[WriteCvtPS2I]>; +def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (memopv4f32 addr:$src))))]>, + Sched<[WriteCvtPS2ILd]>; + + +// Convert Packed Double FP to Packed DW Integers +let Predicates = [HasAVX, NoVLX] in { +// The assembler can recognize rr 256-bit instructions by seeing a ymm +// register, but the same isn't true when using memory operands instead. +// Provide other assembly rr and rm forms to address this explicitly. +def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "vcvtpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (v2f64 VR128:$src))))]>, + VEX, Sched<[WriteCvtPD2I]>, VEX_WIG; + +// XMM only +// def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}", +// (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>; +def VCVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "vcvtpd2dq{x}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (loadv2f64 addr:$src))))]>, VEX, + Sched<[WriteCvtPD2ILd]>, VEX_WIG; +// def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}", +// (VCVTPD2DQrm VR128:$dst, f128mem:$src), 0, "intel">; + +// YMM only +def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), + "vcvtpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (v4f64 VR256:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPD2IY]>, VEX_WIG; +def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), + "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (loadv4f64 addr:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPD2IYLd]>, VEX_WIG; +// def : InstAlias<"vcvtpd2dqy\t{$src, $dst|$dst, $src}", +// (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>; +// def : InstAlias<"vcvtpd2dqy\t{$src, $dst|$dst, $src}", +// (VCVTPD2DQYrm VR128:$dst, f256mem:$src), 0, "intel">; +} + +def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvtpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (memopv2f64 addr:$src))))]>, + Sched<[WriteCvtPD2ILd]>; +def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (v2f64 VR128:$src))))]>, + Sched<[WriteCvtPD2I]>; + +// Convert with truncation packed single/double fp to doubleword +// SSE2 packed instructions with XS prefix +let Predicates = [HasAVX, NoVLX] in { +def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (v4f32 VR128:$src))))]>, + VEX, Sched<[WriteCvtPS2I]>, VEX_WIG; +def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (loadv4f32 addr:$src))))]>, + VEX, Sched<[WriteCvtPS2ILd]>, VEX_WIG; +def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, + (v8i32 (X86cvttp2si (v8f32 VR256:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPS2IY]>, VEX_WIG; +def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, + (v8i32 (X86cvttp2si (loadv8f32 addr:$src))))]>, + VEX, VEX_L, + Sched<[WriteCvtPS2IYLd]>, VEX_WIG; +} + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))), + (VCVTTPS2DQrr VR128:$src)>; + def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))), + (VCVTTPS2DQrm addr:$src)>; + def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))), + (VCVTTPS2DQYrr VR256:$src)>; + def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))), + (VCVTTPS2DQYrm addr:$src)>; +} + +def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (v4f32 VR128:$src))))]>, + Sched<[WriteCvtPS2I]>; +def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (memopv4f32 addr:$src))))]>, + Sched<[WriteCvtPS2ILd]>; + +let Predicates = [UseSSE2] in { + def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))), + (CVTTPS2DQrr VR128:$src)>; + def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))), + (CVTTPS2DQrm addr:$src)>; +} + +let Predicates = [HasAVX, NoVLX] in +def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvttpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (v2f64 VR128:$src))))]>, + VEX, Sched<[WriteCvtPD2I]>, VEX_WIG; + +// The assembler can recognize rr 256-bit instructions by seeing a ymm +// register, but the same isn't true when using memory operands instead. +// Provide other assembly rr and rm forms to address this explicitly. + +// XMM only +// def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}", +// (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>; + +let Predicates = [HasAVX, NoVLX] in +def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvttpd2dq{x}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (loadv2f64 addr:$src))))]>, + VEX, Sched<[WriteCvtPD2ILd]>, VEX_WIG; +// def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}", +// (VCVTTPD2DQrm VR128:$dst, f128mem:$src), 0, "intel">; + +// YMM only +let Predicates = [HasAVX, NoVLX] in { +def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), + "cvttpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (v4f64 VR256:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPD2IY]>, VEX_WIG; +def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), + "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (loadv4f64 addr:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPD2IYLd]>, VEX_WIG; +} +// def : InstAlias<"vcvttpd2dqy\t{$src, $dst|$dst, $src}", +// (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>; +// def : InstAlias<"vcvttpd2dqy\t{$src, $dst|$dst, $src}", +// (VCVTTPD2DQYrm VR128:$dst, f256mem:$src), 0, "intel">; + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))), + (VCVTTPD2DQYrr VR256:$src)>; + def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))), + (VCVTTPD2DQYrm addr:$src)>; +} + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))), + (VCVTPD2DQrr VR128:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2Int (loadv2f64 addr:$src)))))), + (VCVTPD2DQrm addr:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2si (v2f64 VR128:$src)))))), + (VCVTTPD2DQrr VR128:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2si (loadv2f64 addr:$src)))))), + (VCVTTPD2DQrm addr:$src)>; +} // Predicates = [HasAVX, NoVLX] + +def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvttpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (v2f64 VR128:$src))))]>, + Sched<[WriteCvtPD2I]>; +def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src), + "cvttpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (memopv2f64 addr:$src))))]>, + Sched<[WriteCvtPD2ILd]>; + +let Predicates = [UseSSE2] in { + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))), + (CVTPD2DQrr VR128:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2Int (memopv2f64 addr:$src)))))), + (CVTPD2DQrm addr:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2si (v2f64 VR128:$src)))))), + (CVTTPD2DQrr VR128:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2si (memopv2f64 addr:$src)))))), + (CVTTPD2DQrm addr:$src)>; +} // Predicates = [UseSSE2] + +// Convert packed single to packed double +let Predicates = [HasAVX, NoVLX] in { + // SSE2 instructions without OpSize prefix +def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "vcvtps2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2f64 (X86vfpext (v4f32 VR128:$src))))]>, + PS, VEX, Sched<[WriteCvtPS2PD]>, VEX_WIG; +def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), + "vcvtps2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))]>, + PS, VEX, Sched<[WriteCvtPS2PD.Folded]>, VEX_WIG; +def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src), + "vcvtps2pd\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, (v4f64 (fpextend (v4f32 VR128:$src))))]>, + PS, VEX, VEX_L, Sched<[WriteCvtPS2PDY]>, VEX_WIG; +def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src), + "vcvtps2pd\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, (v4f64 (extloadv4f32 addr:$src)))]>, + PS, VEX, VEX_L, Sched<[WriteCvtPS2PDY.Folded]>, VEX_WIG; +} + +let Predicates = [UseSSE2] in { +def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtps2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2f64 (X86vfpext (v4f32 VR128:$src))))]>, + PS, Sched<[WriteCvtPS2PD]>; +def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), + "cvtps2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))]>, + PS, Sched<[WriteCvtPS2PD.Folded]>; +} + +// Convert Packed DW Integers to Packed Double FP +let Predicates = [HasAVX, NoVLX] in { +let hasSideEffects = 0, mayLoad = 1 in +def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), + "vcvtdq2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2f64 (X86VSintToFP (bc_v4i32 (loadv2i64 addr:$src)))))]>, + VEX, Sched<[WriteCvtI2PDLd]>, VEX_WIG; +def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "vcvtdq2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2f64 (X86VSintToFP (v4i32 VR128:$src))))]>, + VEX, Sched<[WriteCvtI2PD]>, VEX_WIG; +def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src), + "vcvtdq2pd\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, + (v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))))]>, + VEX, VEX_L, Sched<[WriteCvtI2PDYLd]>, + VEX_WIG; +def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src), + "vcvtdq2pd\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, + (v4f64 (sint_to_fp (v4i32 VR128:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtI2PDY]>, VEX_WIG; +} + +let hasSideEffects = 0, mayLoad = 1 in +def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), + "cvtdq2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2f64 (X86VSintToFP (bc_v4i32 (loadv2i64 addr:$src)))))]>, + Sched<[WriteCvtI2PDLd]>; +def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtdq2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2f64 (X86VSintToFP (v4i32 VR128:$src))))]>, + Sched<[WriteCvtI2PD]>; + +// AVX register conversion intrinsics +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (VCVTDQ2PDrm addr:$src)>; + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (X86vzload addr:$src))))), + (VCVTDQ2PDrm addr:$src)>; +} // Predicates = [HasAVX, NoVLX] + +// SSE2 register conversion intrinsics +let Predicates = [UseSSE2] in { + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (CVTDQ2PDrm addr:$src)>; + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (X86vzload addr:$src))))), + (CVTDQ2PDrm addr:$src)>; +} // Predicates = [UseSSE2] + +// Convert packed double to packed single +// The assembler can recognize rr 256-bit instructions by seeing a ymm +// register, but the same isn't true when using memory operands instead. +// Provide other assembly rr and rm forms to address this explicitly. +let Predicates = [HasAVX, NoVLX] in +def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtpd2ps\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (X86vfpround (v2f64 VR128:$src)))]>, + VEX, Sched<[WriteCvtPD2PS]>, VEX_WIG; + +// XMM only +// def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}", +// (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>; +let Predicates = [HasAVX, NoVLX] in +def VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvtpd2ps{x}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (X86vfpround (loadv2f64 addr:$src)))]>, + VEX, Sched<[WriteCvtPD2PS.Folded]>, VEX_WIG; +// def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}", +// (VCVTPD2PSrm VR128:$dst, f128mem:$src), 0, "intel">; + +// YMM only +let Predicates = [HasAVX, NoVLX] in { +def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), + "cvtpd2ps\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (fpround VR256:$src))]>, + VEX, VEX_L, Sched<[WriteCvtPD2PSY]>, VEX_WIG; +def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), + "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (fpround (loadv4f64 addr:$src)))]>, + VEX, VEX_L, Sched<[WriteCvtPD2PSY.Folded]>, VEX_WIG; +} +// def : InstAlias<"vcvtpd2psy\t{$src, $dst|$dst, $src}", +// (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>; +// def : InstAlias<"vcvtpd2psy\t{$src, $dst|$dst, $src}", +// (VCVTPD2PSYrm VR128:$dst, f256mem:$src), 0, "intel">; + +def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtpd2ps\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (X86vfpround (v2f64 VR128:$src)))]>, + Sched<[WriteCvtPD2PS]>; +def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvtpd2ps\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (X86vfpround (memopv2f64 addr:$src)))]>, + Sched<[WriteCvtPD2PS.Folded]>; + +// AVX 256-bit register conversion intrinsics +// FIXME: Migrate SSE conversion intrinsics matching to use patterns as below +// whenever possible to avoid declaring two versions of each one. + +let Predicates = [HasAVX, NoVLX] in { + // Match fpround and fpextend for 128/256-bit conversions + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86vfpround (v2f64 VR128:$src)))))), + (VCVTPD2PSrr VR128:$src)>; + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86vfpround (loadv2f64 addr:$src)))))), + (VCVTPD2PSrm addr:$src)>; +} + +let Predicates = [UseSSE2] in { + // Match fpround and fpextend for 128 conversions + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86vfpround (v2f64 VR128:$src)))))), + (CVTPD2PSrr VR128:$src)>; + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86vfpround (memopv2f64 addr:$src)))))), + (CVTPD2PSrm addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Compare Instructions +//===----------------------------------------------------------------------===// + +// sse12_cmp_scalar - sse 1 & 2 compare scalar instructions +multiclass sse12_cmp_scalar { + let isCommutable = 1 in + def rr : SIi8<0xC2, MRMSrcReg, + (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, + [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>, + Sched<[sched]>; + def rm : SIi8<0xC2, MRMSrcMem, + (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, + [(set RC:$dst, (OpNode (VT RC:$src1), + (ld_frag addr:$src2), imm:$cc))]>, + Sched<[sched.Folded, ReadAfterLd]>; + + // Accept explicit immediate argument form instead of comparison code. + let isAsmParserOnly = 1, hasSideEffects = 0 in { + def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst), + (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, []>, + Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in + def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst), + (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, []>, + Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable; + } +} + +let ExeDomain = SSEPackedSingle in +defm VCMPSS : sse12_cmp_scalar, XS, VEX_4V, VEX_LIG, VEX_WIG; +let ExeDomain = SSEPackedDouble in +defm VCMPSD : sse12_cmp_scalar, + XD, VEX_4V, VEX_LIG, VEX_WIG; + +let Constraints = "$src1 = $dst" in { + let ExeDomain = SSEPackedSingle in + defm CMPSS : sse12_cmp_scalar, XS; + let ExeDomain = SSEPackedDouble in + defm CMPSD : sse12_cmp_scalar, XD; +} + +multiclass sse12_cmp_scalar_int { + def rr_Int : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src, CC:$cc), asm, + [(set VR128:$dst, (Int VR128:$src1, + VR128:$src, imm:$cc))]>, + Sched<[sched]>; +let mayLoad = 1 in + def rm_Int : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, memop:$src, CC:$cc), asm, + [(set VR128:$dst, (Int VR128:$src1, + mem_cpat:$src, imm:$cc))]>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let isCodeGenOnly = 1 in { + // Aliases to match intrinsics which expect XMM operand(s). + let ExeDomain = SSEPackedSingle in + defm VCMPSS : sse12_cmp_scalar_int, XS, VEX_4V; + let ExeDomain = SSEPackedDouble in + defm VCMPSD : sse12_cmp_scalar_int, + XD, VEX_4V; + let Constraints = "$src1 = $dst" in { + let ExeDomain = SSEPackedSingle in + defm CMPSS : sse12_cmp_scalar_int, XS; + let ExeDomain = SSEPackedDouble in + defm CMPSD : sse12_cmp_scalar_int, XD; +} +} + + +// sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS +multiclass sse12_ord_cmp opc, RegisterClass RC, SDNode OpNode, + ValueType vt, X86MemOperand x86memop, + PatFrag ld_frag, string OpcodeStr, + X86FoldableSchedWrite sched> { +let hasSideEffects = 0 in { + def rr: SI, + Sched<[sched]>; +let mayLoad = 1 in + def rm: SI, + Sched<[sched.Folded, ReadAfterLd]>; +} +} + +// sse12_ord_cmp_int - Intrinsic version of sse12_ord_cmp +multiclass sse12_ord_cmp_int opc, RegisterClass RC, SDNode OpNode, + ValueType vt, Operand memop, + ComplexPattern mem_cpat, string OpcodeStr, + X86FoldableSchedWrite sched> { + def rr_Int: SI, + Sched<[sched]>; +let mayLoad = 1 in + def rm_Int: SI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Defs = [EFLAGS] in { + defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32, + "ucomiss", WriteFCom>, PS, VEX, VEX_LIG, VEX_WIG; + defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, + "ucomisd", WriteFCom>, PD, VEX, VEX_LIG, VEX_WIG; + let Pattern = [] in { + defm VCOMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32, + "comiss", WriteFCom>, PS, VEX, VEX_LIG, VEX_WIG; + defm VCOMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64, + "comisd", WriteFCom>, PD, VEX, VEX_LIG, VEX_WIG; + } + + let isCodeGenOnly = 1 in { + defm VUCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem, + sse_load_f32, "ucomiss", WriteFCom>, PS, VEX, VEX_WIG; + defm VUCOMISD : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v2f64, sdmem, + sse_load_f64, "ucomisd", WriteFCom>, PD, VEX, VEX_WIG; + + defm VCOMISS : sse12_ord_cmp_int<0x2F, VR128, X86comi, v4f32, ssmem, + sse_load_f32, "comiss", WriteFCom>, PS, VEX, VEX_WIG; + defm VCOMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem, + sse_load_f64, "comisd", WriteFCom>, PD, VEX, VEX_WIG; + } + defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32, + "ucomiss", WriteFCom>, PS; + defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, + "ucomisd", WriteFCom>, PD; + + let Pattern = [] in { + defm COMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32, + "comiss", WriteFCom>, PS; + defm COMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64, + "comisd", WriteFCom>, PD; + } + + let isCodeGenOnly = 1 in { + defm UCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem, + sse_load_f32, "ucomiss", WriteFCom>, PS; + defm UCOMISD : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v2f64, sdmem, + sse_load_f64, "ucomisd", WriteFCom>, PD; + + defm COMISS : sse12_ord_cmp_int<0x2F, VR128, X86comi, v4f32, ssmem, + sse_load_f32, "comiss", WriteFCom>, PS; + defm COMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem, + sse_load_f64, "comisd", WriteFCom>, PD; + } +} // Defs = [EFLAGS] + +// sse12_cmp_packed - sse 1 & 2 compare packed instructions +multiclass sse12_cmp_packed { + let isCommutable = 1 in + def rri : PIi8<0xC2, MRMSrcReg, + (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, + [(set RC:$dst, (VT (X86cmpp RC:$src1, RC:$src2, imm:$cc)))], d>, + Sched<[sched]>; + def rmi : PIi8<0xC2, MRMSrcMem, + (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, + [(set RC:$dst, + (VT (X86cmpp RC:$src1, (ld_frag addr:$src2), imm:$cc)))], d>, + Sched<[sched.Folded, ReadAfterLd]>; + + // Accept explicit immediate argument form instead of comparison code. + let isAsmParserOnly = 1, hasSideEffects = 0 in { + def rri_alt : PIi8<0xC2, MRMSrcReg, + (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc), + asm_alt, [], d>, Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in + def rmi_alt : PIi8<0xC2, MRMSrcMem, + (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc), + asm_alt, [], d>, Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + } +} + +defm VCMPPS : sse12_cmp_packed, PS, VEX_4V, VEX_WIG; +defm VCMPPD : sse12_cmp_packed, PD, VEX_4V, VEX_WIG; +defm VCMPPSY : sse12_cmp_packed, PS, VEX_4V, VEX_L, VEX_WIG; +defm VCMPPDY : sse12_cmp_packed, PD, VEX_4V, VEX_L, VEX_WIG; +let Constraints = "$src1 = $dst" in { + defm CMPPS : sse12_cmp_packed, PS; + defm CMPPD : sse12_cmp_packed, PD; +} + +def CommutableCMPCC : PatLeaf<(imm), [{ + uint64_t Imm = N->getZExtValue() & 0x7; + return (Imm == 0x00 || Imm == 0x03 || Imm == 0x04 || Imm == 0x07); +}]>; + +// Patterns to select compares with loads in first operand. +let Predicates = [HasAVX] in { + def : Pat<(v4f64 (X86cmpp (loadv4f64 addr:$src2), VR256:$src1, + CommutableCMPCC:$cc)), + (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(v8f32 (X86cmpp (loadv8f32 addr:$src2), VR256:$src1, + CommutableCMPCC:$cc)), + (VCMPPSYrmi VR256:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(v2f64 (X86cmpp (loadv2f64 addr:$src2), VR128:$src1, + CommutableCMPCC:$cc)), + (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(v4f32 (X86cmpp (loadv4f32 addr:$src2), VR128:$src1, + CommutableCMPCC:$cc)), + (VCMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(f64 (X86cmps (loadf64 addr:$src2), FR64:$src1, + CommutableCMPCC:$cc)), + (VCMPSDrm FR64:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(f32 (X86cmps (loadf32 addr:$src2), FR32:$src1, + CommutableCMPCC:$cc)), + (VCMPSSrm FR32:$src1, addr:$src2, imm:$cc)>; +} + +let Predicates = [UseSSE2] in { + def : Pat<(v2f64 (X86cmpp (memopv2f64 addr:$src2), VR128:$src1, + CommutableCMPCC:$cc)), + (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(f64 (X86cmps (loadf64 addr:$src2), FR64:$src1, + CommutableCMPCC:$cc)), + (CMPSDrm FR64:$src1, addr:$src2, imm:$cc)>; +} + +let Predicates = [UseSSE1] in { + def : Pat<(v4f32 (X86cmpp (memopv4f32 addr:$src2), VR128:$src1, + CommutableCMPCC:$cc)), + (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(f32 (X86cmps (loadf32 addr:$src2), FR32:$src1, + CommutableCMPCC:$cc)), + (CMPSSrm FR32:$src1, addr:$src2, imm:$cc)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Shuffle Instructions +//===----------------------------------------------------------------------===// + +/// sse12_shuffle - sse 1 & 2 fp shuffle instructions +multiclass sse12_shuffle { + def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst), + (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm, + [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2), + (i8 imm:$src3))))], d>, + Sched<[sched.Folded, ReadAfterLd]>; + def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst), + (ins RC:$src1, RC:$src2, u8imm:$src3), asm, + [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2, + (i8 imm:$src3))))], d>, + Sched<[sched]>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm VSHUFPS : sse12_shuffle, + PS, VEX_4V, VEX_WIG; + defm VSHUFPSY : sse12_shuffle, + PS, VEX_4V, VEX_L, VEX_WIG; + defm VSHUFPD : sse12_shuffle, + PD, VEX_4V, VEX_WIG; + defm VSHUFPDY : sse12_shuffle, + PD, VEX_4V, VEX_L, VEX_WIG; +} +let Constraints = "$src1 = $dst" in { + defm SHUFPS : sse12_shuffle, PS; + defm SHUFPD : sse12_shuffle, PD; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Unpack FP Instructions +//===----------------------------------------------------------------------===// + +/// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave +multiclass sse12_unpack_interleave opc, SDNode OpNode, ValueType vt, + PatFrag mem_frag, RegisterClass RC, + X86MemOperand x86memop, string asm, + X86FoldableSchedWrite sched, Domain d, + bit IsCommutable = 0> { + let isCommutable = IsCommutable in + def rr : PI, + Sched<[sched]>; + def rm : PI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoVLX] in { +defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32, + VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.XMM, SSEPackedSingle>, PS, VEX_4V, VEX_WIG; +defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64, + VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.XMM, SSEPackedDouble, 1>, PD, VEX_4V, VEX_WIG; +defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32, + VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.XMM, SSEPackedSingle>, PS, VEX_4V, VEX_WIG; +defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64, + VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.XMM, SSEPackedDouble>, PD, VEX_4V, VEX_WIG; + +defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32, + VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.YMM, SSEPackedSingle>, PS, VEX_4V, VEX_L, VEX_WIG; +defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64, + VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.YMM, SSEPackedDouble>, PD, VEX_4V, VEX_L, VEX_WIG; +defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32, + VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.YMM, SSEPackedSingle>, PS, VEX_4V, VEX_L, VEX_WIG; +defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64, + VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.YMM, SSEPackedDouble>, PD, VEX_4V, VEX_L, VEX_WIG; +}// Predicates = [HasAVX, NoVLX] + +let Constraints = "$src1 = $dst" in { + defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32, + VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}", + SchedWriteFShuffle.XMM, SSEPackedSingle>, PS; + defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64, + VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}", + SchedWriteFShuffle.XMM, SSEPackedDouble, 1>, PD; + defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32, + VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}", + SchedWriteFShuffle.XMM, SSEPackedSingle>, PS; + defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64, + VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}", + SchedWriteFShuffle.XMM, SSEPackedDouble>, PD; +} // Constraints = "$src1 = $dst" + +let Predicates = [HasAVX1Only] in { + def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))), + (VUNPCKLPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)), + (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))), + (VUNPCKHPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)), + (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>; + + def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))), + (VUNPCKLPDYrm VR256:$src1, addr:$src2)>; + def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)), + (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))), + (VUNPCKHPDYrm VR256:$src1, addr:$src2)>; + def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)), + (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Extract Floating-Point Sign mask +//===----------------------------------------------------------------------===// + +/// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave +multiclass sse12_extr_sign_mask { + def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src), + !strconcat(asm, "\t{$src, $dst|$dst, $src}"), + [(set GR32orGR64:$dst, (X86movmsk (vt RC:$src)))], d>, + Sched<[WriteFMOVMSK]>; +} + +let Predicates = [HasAVX] in { + defm VMOVMSKPS : sse12_extr_sign_mask, PS, VEX, VEX_WIG; + defm VMOVMSKPD : sse12_extr_sign_mask, PD, VEX, VEX_WIG; + defm VMOVMSKPSY : sse12_extr_sign_mask, PS, VEX, VEX_L, VEX_WIG; + defm VMOVMSKPDY : sse12_extr_sign_mask, PD, VEX, VEX_L, VEX_WIG; +} + +defm MOVMSKPS : sse12_extr_sign_mask, PS; +defm MOVMSKPD : sse12_extr_sign_mask, PD; + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Logical Instructions +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { // SSE integer instructions + +/// PDI_binop_rm - Simple SSE2 binary operator. +multiclass PDI_binop_rm opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT, RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, X86FoldableSchedWrite sched, + bit IsCommutable, bit Is2Addr> { + let isCommutable = IsCommutable in + def rr : PDI, + Sched<[sched]>; + def rm : PDI, + Sched<[sched.Folded, ReadAfterLd]>; +} +} // ExeDomain = SSEPackedInt + +multiclass PDI_binop_all opc, string OpcodeStr, SDNode Opcode, + ValueType OpVT128, ValueType OpVT256, + X86SchedWriteWidths sched, bit IsCommutable, + Predicate prd> { +let Predicates = [HasAVX, prd] in + defm V#NAME : PDI_binop_rm, VEX_4V, VEX_WIG; + +let Constraints = "$src1 = $dst" in + defm NAME : PDI_binop_rm; + +let Predicates = [HasAVX2, prd] in + defm V#NAME#Y : PDI_binop_rm, VEX_4V, VEX_L, VEX_WIG; +} + +// These are ordered here for pattern ordering requirements with the fp versions + +defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, + SchedWriteVecLogic, 1, NoVLX>; +defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, + SchedWriteVecLogic, 1, NoVLX>; +defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, + SchedWriteVecLogic, 1, NoVLX>; +defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64, + SchedWriteVecLogic, 0, NoVLX>; + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Logical Instructions +//===----------------------------------------------------------------------===// + +/// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops +/// +/// There are no patterns here because isel prefers integer versions for SSE2 +/// and later. There are SSE1 v4f32 patterns later. +multiclass sse12_fp_packed_logical opc, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched> { + let Predicates = [HasAVX, NoVLX] in { + defm V#NAME#PSY : sse12_fp_packed_logical_rm, PS, VEX_4V, VEX_L, VEX_WIG; + + defm V#NAME#PDY : sse12_fp_packed_logical_rm, PD, VEX_4V, VEX_L, VEX_WIG; + + defm V#NAME#PS : sse12_fp_packed_logical_rm, PS, VEX_4V, VEX_WIG; + + defm V#NAME#PD : sse12_fp_packed_logical_rm, PD, VEX_4V, VEX_WIG; + } + + let Constraints = "$src1 = $dst" in { + defm PS : sse12_fp_packed_logical_rm, PS; + + defm PD : sse12_fp_packed_logical_rm, PD; + } +} + +defm AND : sse12_fp_packed_logical<0x54, "and", and, SchedWriteFLogic>; +defm OR : sse12_fp_packed_logical<0x56, "or", or, SchedWriteFLogic>; +defm XOR : sse12_fp_packed_logical<0x57, "xor", xor, SchedWriteFLogic>; +let isCommutable = 0 in + defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp, SchedWriteFLogic>; + +// If only AVX1 is supported, we need to handle integer operations with +// floating point instructions since the integer versions aren't available. +let Predicates = [HasAVX1Only] in { + def : Pat<(v4i64 (and VR256:$src1, VR256:$src2)), + (VANDPSYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (or VR256:$src1, VR256:$src2)), + (VORPSYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (xor VR256:$src1, VR256:$src2)), + (VXORPSYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (X86andnp VR256:$src1, VR256:$src2)), + (VANDNPSYrr VR256:$src1, VR256:$src2)>; + + def : Pat<(and VR256:$src1, (loadv4i64 addr:$src2)), + (VANDPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(or VR256:$src1, (loadv4i64 addr:$src2)), + (VORPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(xor VR256:$src1, (loadv4i64 addr:$src2)), + (VXORPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(X86andnp VR256:$src1, (loadv4i64 addr:$src2)), + (VANDNPSYrm VR256:$src1, addr:$src2)>; +} + +let Predicates = [HasAVX, NoVLX_Or_NoDQI] in { + // Use packed logical operations for scalar ops. + def : Pat<(f64 (X86fand FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VANDPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + def : Pat<(f64 (X86for FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VORPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + def : Pat<(f64 (X86fxor FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VXORPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + def : Pat<(f64 (X86fandn FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VANDNPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + + def : Pat<(f32 (X86fand FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VANDPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; + def : Pat<(f32 (X86for FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VORPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; + def : Pat<(f32 (X86fxor FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VXORPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; + def : Pat<(f32 (X86fandn FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VANDNPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; +} + +let Predicates = [UseSSE1] in { + // Use packed logical operations for scalar ops. + def : Pat<(f32 (X86fand FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (ANDPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; + def : Pat<(f32 (X86for FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (ORPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; + def : Pat<(f32 (X86fxor FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (XORPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; + def : Pat<(f32 (X86fandn FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (ANDNPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; +} + +let Predicates = [UseSSE2] in { + // Use packed logical operations for scalar ops. + def : Pat<(f64 (X86fand FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (ANDPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + def : Pat<(f64 (X86for FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (ORPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + def : Pat<(f64 (X86fxor FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (XORPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + def : Pat<(f64 (X86fandn FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (ANDNPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; +} + +// Patterns for packed operations when we don't have integer type available. +def : Pat<(v4f32 (X86fand VR128:$src1, VR128:$src2)), + (ANDPSrr VR128:$src1, VR128:$src2)>; +def : Pat<(v4f32 (X86for VR128:$src1, VR128:$src2)), + (ORPSrr VR128:$src1, VR128:$src2)>; +def : Pat<(v4f32 (X86fxor VR128:$src1, VR128:$src2)), + (XORPSrr VR128:$src1, VR128:$src2)>; +def : Pat<(v4f32 (X86fandn VR128:$src1, VR128:$src2)), + (ANDNPSrr VR128:$src1, VR128:$src2)>; + +def : Pat<(X86fand VR128:$src1, (memopv4f32 addr:$src2)), + (ANDPSrm VR128:$src1, addr:$src2)>; +def : Pat<(X86for VR128:$src1, (memopv4f32 addr:$src2)), + (ORPSrm VR128:$src1, addr:$src2)>; +def : Pat<(X86fxor VR128:$src1, (memopv4f32 addr:$src2)), + (XORPSrm VR128:$src1, addr:$src2)>; +def : Pat<(X86fandn VR128:$src1, (memopv4f32 addr:$src2)), + (ANDNPSrm VR128:$src1, addr:$src2)>; + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Arithmetic Instructions +//===----------------------------------------------------------------------===// + +/// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and +/// vector forms. +/// +/// In addition, we also have a special variant of the scalar form here to +/// represent the associated intrinsic operation. This form is unlike the +/// plain scalar form, in that it takes an entire vector (instead of a scalar) +/// and leaves the top elements unmodified (therefore these cannot be commuted). +/// +/// These three forms can each be reg+reg or reg+mem. +/// + +/// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those +/// classes below +multiclass basic_sse12_fp_binop_p opc, string OpcodeStr, + SDNode OpNode, X86SchedWriteSizes sched> { + let Predicates = [HasAVX, NoVLX] in { + defm V#NAME#PS : sse12_fp_packed, PS, VEX_4V, VEX_WIG; + defm V#NAME#PD : sse12_fp_packed, PD, VEX_4V, VEX_WIG; + + defm V#NAME#PSY : sse12_fp_packed, PS, VEX_4V, VEX_L, VEX_WIG; + defm V#NAME#PDY : sse12_fp_packed, PD, VEX_4V, VEX_L, VEX_WIG; + } + + let Constraints = "$src1 = $dst" in { + defm PS : sse12_fp_packed, PS; + defm PD : sse12_fp_packed, PD; + } +} + +multiclass basic_sse12_fp_binop_s opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteSizes sched> { + defm V#NAME#SS : sse12_fp_scalar, + XS, VEX_4V, VEX_LIG, VEX_WIG; + defm V#NAME#SD : sse12_fp_scalar, + XD, VEX_4V, VEX_LIG, VEX_WIG; + + let Constraints = "$src1 = $dst" in { + defm SS : sse12_fp_scalar, XS; + defm SD : sse12_fp_scalar, XD; + } +} + +multiclass basic_sse12_fp_binop_s_int opc, string OpcodeStr, + SDPatternOperator OpNode, + X86SchedWriteSizes sched> { + defm V#NAME#SS : sse12_fp_scalar_int, XS, VEX_4V, VEX_LIG, VEX_WIG; + defm V#NAME#SD : sse12_fp_scalar_int, XD, VEX_4V, VEX_LIG, VEX_WIG; + + let Constraints = "$src1 = $dst" in { + defm SS : sse12_fp_scalar_int, XS; + defm SD : sse12_fp_scalar_int, XD; + } +} + +// Binary Arithmetic instructions +defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SchedWriteFAddSizes>, + basic_sse12_fp_binop_s<0x58, "add", fadd, SchedWriteFAddSizes>, + basic_sse12_fp_binop_s_int<0x58, "add", null_frag, SchedWriteFAddSizes>; +defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SchedWriteFMulSizes>, + basic_sse12_fp_binop_s<0x59, "mul", fmul, SchedWriteFMulSizes>, + basic_sse12_fp_binop_s_int<0x59, "mul", null_frag, SchedWriteFMulSizes>; +let isCommutable = 0 in { + defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SchedWriteFAddSizes>, + basic_sse12_fp_binop_s<0x5C, "sub", fsub, SchedWriteFAddSizes>, + basic_sse12_fp_binop_s_int<0x5C, "sub", null_frag, SchedWriteFAddSizes>; + defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SchedWriteFDivSizes>, + basic_sse12_fp_binop_s<0x5E, "div", fdiv, SchedWriteFDivSizes>, + basic_sse12_fp_binop_s_int<0x5E, "div", null_frag, SchedWriteFDivSizes>; + defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SchedWriteFCmpSizes>, + basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SchedWriteFCmpSizes>, + basic_sse12_fp_binop_s_int<0x5F, "max", X86fmaxs, SchedWriteFCmpSizes>; + defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SchedWriteFCmpSizes>, + basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SchedWriteFCmpSizes>, + basic_sse12_fp_binop_s_int<0x5D, "min", X86fmins, SchedWriteFCmpSizes>; +} + +let isCodeGenOnly = 1 in { + defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SchedWriteFCmpSizes>, + basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SchedWriteFCmpSizes>; + defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SchedWriteFCmpSizes>, + basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SchedWriteFCmpSizes>; +} + +// Patterns used to select SSE scalar fp arithmetic instructions from +// either: +// +// (1) a scalar fp operation followed by a blend +// +// The effect is that the backend no longer emits unnecessary vector +// insert instructions immediately after SSE scalar fp instructions +// like addss or mulss. +// +// For example, given the following code: +// __m128 foo(__m128 A, __m128 B) { +// A[0] += B[0]; +// return A; +// } +// +// Previously we generated: +// addss %xmm0, %xmm1 +// movss %xmm1, %xmm0 +// +// We now generate: +// addss %xmm1, %xmm0 +// +// (2) a vector packed single/double fp operation followed by a vector insert +// +// The effect is that the backend converts the packed fp instruction +// followed by a vector insert into a single SSE scalar fp instruction. +// +// For example, given the following code: +// __m128 foo(__m128 A, __m128 B) { +// __m128 C = A + B; +// return (__m128) {c[0], a[1], a[2], a[3]}; +// } +// +// Previously we generated: +// addps %xmm0, %xmm1 +// movss %xmm1, %xmm0 +// +// We now generate: +// addss %xmm1, %xmm0 + +// TODO: Some canonicalization in lowering would simplify the number of +// patterns we have to try to match. +multiclass scalar_math_patterns { + let Predicates = [BasePredicate] in { + // extracted scalar math op with insert via movss/movsd + def : Pat<(VT (Move (VT VR128:$dst), + (VT (scalar_to_vector + (Op (EltTy (extractelt (VT VR128:$dst), (iPTR 0))), + RC:$src))))), + (!cast(OpcPrefix#rr_Int) VT:$dst, + (VT (COPY_TO_REGCLASS RC:$src, VR128)))>; + } + + // Repeat for AVX versions of the instructions. + let Predicates = [UseAVX] in { + // extracted scalar math op with insert via movss/movsd + def : Pat<(VT (Move (VT VR128:$dst), + (VT (scalar_to_vector + (Op (EltTy (extractelt (VT VR128:$dst), (iPTR 0))), + RC:$src))))), + (!cast("V"#OpcPrefix#rr_Int) VT:$dst, + (VT (COPY_TO_REGCLASS RC:$src, VR128)))>; + } +} + +defm : scalar_math_patterns; +defm : scalar_math_patterns; +defm : scalar_math_patterns; +defm : scalar_math_patterns; + +defm : scalar_math_patterns; +defm : scalar_math_patterns; +defm : scalar_math_patterns; +defm : scalar_math_patterns; + +/// Unop Arithmetic +/// In addition, we also have a special variant of the scalar form here to +/// represent the associated intrinsic operation. This form is unlike the +/// plain scalar form, in that it takes an entire vector (instead of a +/// scalar) and leaves the top elements undefined. +/// +/// And, we have a special variant form for a full-vector intrinsic form. + +/// sse_fp_unop_s - SSE1 unops in scalar form +/// For the non-AVX defs, we need $src1 to be tied to $dst because +/// the HW instructions are 2 operand / destructive. +multiclass sse_fp_unop_s opc, string OpcodeStr, RegisterClass RC, + ValueType ScalarVT, X86MemOperand x86memop, + Operand intmemop, SDNode OpNode, Domain d, + X86FoldableSchedWrite sched, Predicate target> { + let hasSideEffects = 0 in { + def r : I, Sched<[sched]>, + Requires<[target]>; + let mayLoad = 1 in + def m : I, + Sched<[sched.Folded, ReadAfterLd]>, + Requires<[target, OptForSize]>; + + let isCodeGenOnly = 1, Constraints = "$src1 = $dst", ExeDomain = d in { + def r_Int : I, + Sched<[sched]>; + let mayLoad = 1 in + def m_Int : I, + Sched<[sched.Folded, ReadAfterLd]>; + } + } + +} + +multiclass sse_fp_unop_s_intr { + let Predicates = [target] in { + // These are unary operations, but they are modeled as having 2 source operands + // because the high elements of the destination are unchanged in SSE. + def : Pat<(Intr VR128:$src), + (!cast(NAME#r_Int) VR128:$src, VR128:$src)>; + } + // We don't want to fold scalar loads into these instructions unless + // optimizing for size. This is because the folded instruction will have a + // partial register update, while the unfolded sequence will not, e.g. + // movss mem, %xmm0 + // rcpss %xmm0, %xmm0 + // which has a clobber before the rcp, vs. + // rcpss mem, %xmm0 + let Predicates = [target, OptForSize] in { + def : Pat<(Intr int_cpat:$src2), + (!cast(NAME#m_Int) + (vt (IMPLICIT_DEF)), addr:$src2)>; + } +} + +multiclass avx_fp_unop_s_intr { + let Predicates = [target] in { + def : Pat<(Intr VR128:$src), + (!cast(NAME#r_Int) VR128:$src, + VR128:$src)>; + } + let Predicates = [target, OptForSize] in { + def : Pat<(Intr int_cpat:$src2), + (!cast(NAME#m_Int) + (vt (IMPLICIT_DEF)), addr:$src2)>; + } +} + +multiclass avx_fp_unop_s opc, string OpcodeStr, RegisterClass RC, + ValueType ScalarVT, X86MemOperand x86memop, + Operand intmemop, SDNode OpNode, Domain d, + X86FoldableSchedWrite sched, Predicate target> { + let hasSideEffects = 0 in { + def r : I, Sched<[sched]>; + let mayLoad = 1 in + def m : I, Sched<[sched.Folded, ReadAfterLd]>; + let isCodeGenOnly = 1, ExeDomain = d in { + def r_Int : I, Sched<[sched]>; + let mayLoad = 1 in + def m_Int : I, Sched<[sched.Folded, ReadAfterLd]>; + } + } + + // We don't want to fold scalar loads into these instructions unless + // optimizing for size. This is because the folded instruction will have a + // partial register update, while the unfolded sequence will not, e.g. + // vmovss mem, %xmm0 + // vrcpss %xmm0, %xmm0, %xmm0 + // which has a clobber before the rcp, vs. + // vrcpss mem, %xmm0, %xmm0 + // TODO: In theory, we could fold the load, and avoid the stall caused by + // the partial register store, either in BreakFalseDeps or with smarter RA. + let Predicates = [target] in { + def : Pat<(OpNode RC:$src), (!cast(NAME#r) + (ScalarVT (IMPLICIT_DEF)), RC:$src)>; + } + let Predicates = [target, OptForSize] in { + def : Pat<(ScalarVT (OpNode (load addr:$src))), + (!cast(NAME#m) (ScalarVT (IMPLICIT_DEF)), + addr:$src)>; + } +} + +/// sse1_fp_unop_p - SSE1 unops in packed form. +multiclass sse1_fp_unop_p opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, list prds> { +let Predicates = prds in { + def V#NAME#PSr : PSI, + VEX, Sched<[sched.XMM]>, VEX_WIG; + def V#NAME#PSm : PSI, + VEX, Sched<[sched.XMM.Folded]>, VEX_WIG; + def V#NAME#PSYr : PSI, + VEX, VEX_L, Sched<[sched.YMM]>, VEX_WIG; + def V#NAME#PSYm : PSI, + VEX, VEX_L, Sched<[sched.YMM.Folded]>, VEX_WIG; +} + + def PSr : PSI, + Sched<[sched.XMM]>; + def PSm : PSI, + Sched<[sched.XMM.Folded]>; +} + +/// sse2_fp_unop_p - SSE2 unops in vector forms. +multiclass sse2_fp_unop_p opc, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched> { +let Predicates = [HasAVX, NoVLX] in { + def V#NAME#PDr : PDI, + VEX, Sched<[sched.XMM]>, VEX_WIG; + def V#NAME#PDm : PDI, + VEX, Sched<[sched.XMM.Folded]>, VEX_WIG; + def V#NAME#PDYr : PDI, + VEX, VEX_L, Sched<[sched.YMM]>, VEX_WIG; + def V#NAME#PDYm : PDI, + VEX, VEX_L, Sched<[sched.YMM.Folded]>, VEX_WIG; +} + + def PDr : PDI, + Sched<[sched.XMM]>; + def PDm : PDI, + Sched<[sched.XMM.Folded]>; +} + +multiclass sse1_fp_unop_s_intr opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate AVXTarget> { + defm SS : sse_fp_unop_s_intr("int_x86_sse_"##OpcodeStr##_ss), + UseSSE1, "SS">, XS; + defm V#NAME#SS : avx_fp_unop_s_intr("int_x86_sse_"##OpcodeStr##_ss), + AVXTarget>, + XS, VEX_4V, VEX_LIG, VEX_WIG, NotMemoryFoldable; +} + +multiclass sse1_fp_unop_s opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate AVXTarget> { + defm SS : sse_fp_unop_s, XS; + defm V#NAME#SS : avx_fp_unop_s, + XS, VEX_4V, VEX_LIG, VEX_WIG; +} + +multiclass sse2_fp_unop_s opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate AVXTarget> { + defm SD : sse_fp_unop_s, XD; + defm V#NAME#SD : avx_fp_unop_s, + XD, VEX_4V, VEX_LIG, VEX_WIG; +} + +// Square root. +defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SchedWriteFSqrt, UseAVX>, + sse1_fp_unop_p<0x51, "sqrt", fsqrt, SchedWriteFSqrt, [HasAVX, NoVLX]>, + sse2_fp_unop_s<0x51, "sqrt", fsqrt, SchedWriteFSqrt64, UseAVX>, + sse2_fp_unop_p<0x51, "sqrt", fsqrt, SchedWriteFSqrt64>; + +// Reciprocal approximations. Note that these typically require refinement +// in order to obtain suitable precision. +defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SchedWriteFRsqrt, HasAVX>, + sse1_fp_unop_s_intr<0x52, "rsqrt", X86frsqrt, SchedWriteFRsqrt, HasAVX>, + sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SchedWriteFRsqrt, [HasAVX]>; +defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SchedWriteFRcp, HasAVX>, + sse1_fp_unop_s_intr<0x53, "rcp", X86frcp, SchedWriteFRcp, HasAVX>, + sse1_fp_unop_p<0x53, "rcp", X86frcp, SchedWriteFRcp, [HasAVX]>; + +// There is no f64 version of the reciprocal approximation instructions. + +multiclass scalar_unary_math_patterns { + let Predicates = [BasePredicate] in { + def : Pat<(VT (Move VT:$dst, (scalar_to_vector + (OpNode (extractelt VT:$src, 0))))), + (!cast(OpcPrefix#r_Int) VT:$dst, VT:$src)>; + } + + // Repeat for AVX versions of the instructions. + let Predicates = [UseAVX] in { + def : Pat<(VT (Move VT:$dst, (scalar_to_vector + (OpNode (extractelt VT:$src, 0))))), + (!cast("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>; + } +} + +multiclass scalar_unary_math_imm_patterns ImmV, + Predicate BasePredicate> { + let Predicates = [BasePredicate] in { + def : Pat<(VT (Move VT:$dst, (scalar_to_vector + (OpNode (extractelt VT:$src, 0))))), + (!cast(OpcPrefix#r_Int) VT:$dst, VT:$src, (i32 ImmV))>; + } + + // Repeat for AVX versions of the instructions. + let Predicates = [UseAVX] in { + def : Pat<(VT (Move VT:$dst, (scalar_to_vector + (OpNode (extractelt VT:$src, 0))))), + (!cast("V"#OpcPrefix#r_Int) VT:$dst, VT:$src, (i32 ImmV))>; + } +} + +defm : scalar_unary_math_patterns; +defm : scalar_unary_math_patterns; + +multiclass scalar_unary_math_intr_patterns { + let Predicates = [BasePredicate] in { + def : Pat<(VT (Move VT:$dst, (Intr VT:$src))), + (!cast(OpcPrefix#r_Int) VT:$dst, VT:$src)>; + } + + // Repeat for AVX versions of the instructions. + let Predicates = [HasAVX] in { + def : Pat<(VT (Move VT:$dst, (Intr VT:$src))), + (!cast("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>; + } +} + +defm : scalar_unary_math_intr_patterns; +defm : scalar_unary_math_intr_patterns; + + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Non-temporal stores +//===----------------------------------------------------------------------===// + +let AddedComplexity = 400 in { // Prefer non-temporal versions +let Predicates = [HasAVX, NoVLX] in { +let SchedRW = [SchedWriteFMoveLSNT.XMM.MR] in { +def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs), + (ins f128mem:$dst, VR128:$src), + "movntps\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v4f32 VR128:$src), + addr:$dst)]>, VEX, VEX_WIG; +def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs), + (ins f128mem:$dst, VR128:$src), + "movntpd\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v2f64 VR128:$src), + addr:$dst)]>, VEX, VEX_WIG; +} // SchedRW + +let SchedRW = [SchedWriteFMoveLSNT.YMM.MR] in { +def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs), + (ins f256mem:$dst, VR256:$src), + "movntps\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v8f32 VR256:$src), + addr:$dst)]>, VEX, VEX_L, VEX_WIG; +def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs), + (ins f256mem:$dst, VR256:$src), + "movntpd\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v4f64 VR256:$src), + addr:$dst)]>, VEX, VEX_L, VEX_WIG; +} // SchedRW + +let ExeDomain = SSEPackedInt in { +def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs), + (ins i128mem:$dst, VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v2i64 VR128:$src), + addr:$dst)]>, VEX, VEX_WIG, + Sched<[SchedWriteVecMoveLSNT.XMM.MR]>; +def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs), + (ins i256mem:$dst, VR256:$src), + "movntdq\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v4i64 VR256:$src), + addr:$dst)]>, VEX, VEX_L, VEX_WIG, + Sched<[SchedWriteVecMoveLSNT.YMM.MR]>; +} // ExeDomain +} // Predicates + +let SchedRW = [SchedWriteFMoveLSNT.XMM.MR] in { +def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movntps\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>; +def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movntpd\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>; +} // SchedRW + +let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecMoveLSNT.XMM.MR] in +def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)]>; + +let SchedRW = [WriteStoreNT] in { +// There is no AVX form for instructions below this point +def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "movnti{l}\t{$src, $dst|$dst, $src}", + [(nontemporalstore (i32 GR32:$src), addr:$dst)]>, + PS, Requires<[HasSSE2]>; +def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "movnti{q}\t{$src, $dst|$dst, $src}", + [(nontemporalstore (i64 GR64:$src), addr:$dst)]>, + PS, Requires<[HasSSE2]>; +} // SchedRW = [WriteStoreNT] + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(alignednontemporalstore (v8i32 VR256:$src), addr:$dst), + (VMOVNTDQYmr addr:$dst, VR256:$src)>; + def : Pat<(alignednontemporalstore (v16i16 VR256:$src), addr:$dst), + (VMOVNTDQYmr addr:$dst, VR256:$src)>; + def : Pat<(alignednontemporalstore (v32i8 VR256:$src), addr:$dst), + (VMOVNTDQYmr addr:$dst, VR256:$src)>; + + def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst), + (VMOVNTDQmr addr:$dst, VR128:$src)>; + def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst), + (VMOVNTDQmr addr:$dst, VR128:$src)>; + def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst), + (VMOVNTDQmr addr:$dst, VR128:$src)>; +} + +let Predicates = [UseSSE2] in { + def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst), + (MOVNTDQmr addr:$dst, VR128:$src)>; + def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst), + (MOVNTDQmr addr:$dst, VR128:$src)>; + def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst), + (MOVNTDQmr addr:$dst, VR128:$src)>; +} + +} // AddedComplexity + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Prefetch and memory fence +//===----------------------------------------------------------------------===// + +// Prefetch intrinsic. +let Predicates = [HasSSEPrefetch], SchedRW = [WriteLoad] in { +def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src), + "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>, TB; +def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src), + "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>, TB; +def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src), + "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>, TB; +def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src), + "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>, TB; +} + +// FIXME: How should flush instruction be modeled? +let SchedRW = [WriteLoad] in { +// Flush cache +def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src), + "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>, + PS, Requires<[HasSSE2]>; +} + +let SchedRW = [WriteNop] in { +// Pause. This "instruction" is encoded as "rep; nop", so even though it +// was introduced with SSE2, it's backward compatible. +def PAUSE : I<0x90, RawFrm, (outs), (ins), + "pause", [(int_x86_sse2_pause)]>, OBXS; +} + +let SchedRW = [WriteFence] in { +// Load, store, and memory fence +// TODO: As with mfence, we may want to ease the availability of sfence/lfence +// to include any 64-bit target. +def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>, + PS, Requires<[HasSSE1]>; +def LFENCE : I<0xAE, MRM_E8, (outs), (ins), "lfence", [(int_x86_sse2_lfence)]>, + PS, Requires<[HasSSE2]>; +def MFENCE : I<0xAE, MRM_F0, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>, + PS, Requires<[HasMFence]>; +} // SchedRW + +def : Pat<(X86MFence), (MFENCE)>; + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Load/Store XCSR register +//===----------------------------------------------------------------------===// + +def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src), + "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, + VEX, Sched<[WriteLDMXCSR]>, VEX_WIG; +def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst), + "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, + VEX, Sched<[WriteSTMXCSR]>, VEX_WIG; + +def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src), + "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, + TB, Sched<[WriteLDMXCSR]>; +def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst), + "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, + TB, Sched<[WriteSTMXCSR]>; + +//===---------------------------------------------------------------------===// +// SSE2 - Move Aligned/Unaligned Packed Integer Instructions +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { // SSE integer instructions + +let hasSideEffects = 0 in { +def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.XMM.RR]>, VEX, VEX_WIG; +def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "movdqu\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.XMM.RR]>, VEX, VEX_WIG; +def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.RR]>, VEX, VEX_L, VEX_WIG; +def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + "movdqu\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.RR]>, VEX, VEX_L, VEX_WIG; +} + +// For Disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { +def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.XMM.RR]>, + VEX, VEX_WIG, FoldGenData<"VMOVDQArr">; +def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.RR]>, + VEX, VEX_L, VEX_WIG, FoldGenData<"VMOVDQAYrr">; +def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movdqu\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.XMM.RR]>, + VEX, VEX_WIG, FoldGenData<"VMOVDQUrr">; +def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src), + "movdqu\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.RR]>, + VEX, VEX_L, VEX_WIG, FoldGenData<"VMOVDQUYrr">; +} + +let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, + hasSideEffects = 0, Predicates = [HasAVX,NoVLX] in { +def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "movdqa\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (alignedloadv2i64 addr:$src))]>, + Sched<[SchedWriteVecMoveLS.XMM.RM]>, VEX, VEX_WIG; +def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.RM]>, + VEX, VEX_L, VEX_WIG; +def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "vmovdqu\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (loadv2i64 addr:$src))]>, + Sched<[SchedWriteVecMoveLS.XMM.RM]>, + XS, VEX, VEX_WIG; +def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src), + "vmovdqu\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.RM]>, + XS, VEX, VEX_L, VEX_WIG; +} + +let mayStore = 1, hasSideEffects = 0, Predicates = [HasAVX,NoVLX] in { +def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs), + (ins i128mem:$dst, VR128:$src), + "movdqa\t{$src, $dst|$dst, $src}", + [(alignedstore (v2i64 VR128:$src), addr:$dst)]>, + Sched<[SchedWriteVecMoveLS.XMM.MR]>, VEX, VEX_WIG; +def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs), + (ins i256mem:$dst, VR256:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.MR]>, VEX, VEX_L, VEX_WIG; +def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), + "vmovdqu\t{$src, $dst|$dst, $src}", + [(store (v2i64 VR128:$src), addr:$dst)]>, + Sched<[SchedWriteVecMoveLS.XMM.MR]>, XS, VEX, VEX_WIG; +def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src), + "vmovdqu\t{$src, $dst|$dst, $src}",[]>, + Sched<[SchedWriteVecMoveLS.YMM.MR]>, XS, VEX, VEX_L, VEX_WIG; +} + +let SchedRW = [SchedWriteVecMoveLS.XMM.RR] in { +let hasSideEffects = 0 in { +def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>; + +def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "movdqu\t{$src, $dst|$dst, $src}", []>, + XS, Requires<[UseSSE2]>; +} + +// For Disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { +def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOVDQArr">; + +def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movdqu\t{$src, $dst|$dst, $src}", []>, + XS, Requires<[UseSSE2]>, FoldGenData<"MOVDQUrr">; +} +} // SchedRW + +let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, + hasSideEffects = 0, SchedRW = [SchedWriteVecMoveLS.XMM.RM] in { +def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "movdqa\t{$src, $dst|$dst, $src}", + [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>; +def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "movdqu\t{$src, $dst|$dst, $src}", + [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>, + XS, Requires<[UseSSE2]>; +} + +let mayStore = 1, hasSideEffects = 0, + SchedRW = [SchedWriteVecMoveLS.XMM.MR] in { +def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), + "movdqa\t{$src, $dst|$dst, $src}", + [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>; +def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), + "movdqu\t{$src, $dst|$dst, $src}", + [/*(store (v2i64 VR128:$src), addr:$dst)*/]>, + XS, Requires<[UseSSE2]>; +} + +} // ExeDomain = SSEPackedInt + +// Aliases to help the assembler pick two byte VEX encodings by swapping the +// operands relative to the normal instructions to use VEX.R instead of VEX.B. +// def : InstAlias<"vmovdqa\t{$src, $dst|$dst, $src}", +// (VMOVDQArr_REV VR128L:$dst, VR128H:$src), 0>; +// def : InstAlias<"vmovdqa\t{$src, $dst|$dst, $src}", +// (VMOVDQAYrr_REV VR256L:$dst, VR256H:$src), 0>; +// def : InstAlias<"vmovdqu\t{$src, $dst|$dst, $src}", +// (VMOVDQUrr_REV VR128L:$dst, VR128H:$src), 0>; +// def : InstAlias<"vmovdqu\t{$src, $dst|$dst, $src}", +// (VMOVDQUYrr_REV VR256L:$dst, VR256H:$src), 0>; + +// Reversed version with ".s" suffix for GAS compatibility. +// def : InstAlias<"vmovdqa.s\t{$src, $dst|$dst, $src}", +// (VMOVDQArr_REV VR128:$dst, VR128:$src), 0>; +// def : InstAlias<"vmovdqa.s\t{$src, $dst|$dst, $src}", +// (VMOVDQAYrr_REV VR256:$dst, VR256:$src), 0>; +// def : InstAlias<"vmovdqu.s\t{$src, $dst|$dst, $src}", +// (VMOVDQUrr_REV VR128:$dst, VR128:$src), 0>; +// def : InstAlias<"vmovdqu.s\t{$src, $dst|$dst, $src}", +// (VMOVDQUYrr_REV VR256:$dst, VR256:$src), 0>; + +// Reversed version with ".s" suffix for GAS compatibility. +// def : InstAlias<"movdqa.s\t{$src, $dst|$dst, $src}", +// (MOVDQArr_REV VR128:$dst, VR128:$src), 0>; +// def : InstAlias<"movdqu.s\t{$src, $dst|$dst, $src}", +// (MOVDQUrr_REV VR128:$dst, VR128:$src), 0>; + +let Predicates = [HasAVX, NoVLX] in { + // Additional patterns for other integer sizes. + def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst), + (VMOVDQAmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst), + (VMOVDQAmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst), + (VMOVDQAmr addr:$dst, VR128:$src)>; + def : Pat<(store (v4i32 VR128:$src), addr:$dst), + (VMOVDQUmr addr:$dst, VR128:$src)>; + def : Pat<(store (v8i16 VR128:$src), addr:$dst), + (VMOVDQUmr addr:$dst, VR128:$src)>; + def : Pat<(store (v16i8 VR128:$src), addr:$dst), + (VMOVDQUmr addr:$dst, VR128:$src)>; +} + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Arithmetic Instructions +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { // SSE integer instructions + +/// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types +multiclass PDI_binop_rm2 opc, string OpcodeStr, SDNode OpNode, + ValueType DstVT, ValueType SrcVT, RegisterClass RC, + PatFrag memop_frag, X86MemOperand x86memop, + X86FoldableSchedWrite sched, bit Is2Addr = 1> { + let isCommutable = 1 in + def rr : PDI, + Sched<[sched]>; + def rm : PDI, + Sched<[sched.Folded, ReadAfterLd]>; +} +} // ExeDomain = SSEPackedInt + +defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32, + SchedWriteVecALU, 1, NoVLX>; +defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64, + SchedWriteVecALU, 1, NoVLX>; +defm PADDSB : PDI_binop_all<0xEC, "paddsb", X86adds, v16i8, v32i8, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PADDSW : PDI_binop_all<0xED, "paddsw", X86adds, v8i16, v16i16, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PADDUSB : PDI_binop_all<0xDC, "paddusb", X86addus, v16i8, v32i8, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PADDUSW : PDI_binop_all<0xDD, "paddusw", X86addus, v8i16, v16i16, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16, + SchedWriteVecIMul, 1, NoVLX_Or_NoBWI>; +defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16, + SchedWriteVecIMul, 1, NoVLX_Or_NoBWI>; +defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16, + SchedWriteVecIMul, 1, NoVLX_Or_NoBWI>; +defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8, + SchedWriteVecALU, 0, NoVLX_Or_NoBWI>; +defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16, + SchedWriteVecALU, 0, NoVLX_Or_NoBWI>; +defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32, + SchedWriteVecALU, 0, NoVLX>; +defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64, + SchedWriteVecALU, 0, NoVLX>; +defm PSUBSB : PDI_binop_all<0xE8, "psubsb", X86subs, v16i8, v32i8, + SchedWriteVecALU, 0, NoVLX_Or_NoBWI>; +defm PSUBSW : PDI_binop_all<0xE9, "psubsw", X86subs, v8i16, v16i16, + SchedWriteVecALU, 0, NoVLX_Or_NoBWI>; +defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8, + SchedWriteVecALU, 0, NoVLX_Or_NoBWI>; +defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16, + SchedWriteVecALU, 0, NoVLX_Or_NoBWI>; +defm PMINUB : PDI_binop_all<0xDA, "pminub", umin, v16i8, v32i8, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PMINSW : PDI_binop_all<0xEA, "pminsw", smin, v8i16, v16i16, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", umax, v16i8, v32i8, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", smax, v8i16, v16i16, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PAVGB : PDI_binop_all<0xE0, "pavgb", X86avg, v16i8, v32i8, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PAVGW : PDI_binop_all<0xE3, "pavgw", X86avg, v8i16, v16i16, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PMULUDQ : PDI_binop_all<0xF4, "pmuludq", X86pmuludq, v2i64, v4i64, + SchedWriteVecIMul, 1, NoVLX>; + +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in +defm VPMADDWD : PDI_binop_rm2<0xF5, "vpmaddwd", X86vpmaddwd, v4i32, v8i16, VR128, + loadv2i64, i128mem, SchedWriteVecIMul.XMM, 0>, + VEX_4V, VEX_WIG; + +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in +defm VPMADDWDY : PDI_binop_rm2<0xF5, "vpmaddwd", X86vpmaddwd, v8i32, v16i16, + VR256, loadv4i64, i256mem, SchedWriteVecIMul.YMM, + 0>, VEX_4V, VEX_L, VEX_WIG; +let Constraints = "$src1 = $dst" in +defm PMADDWD : PDI_binop_rm2<0xF5, "pmaddwd", X86vpmaddwd, v4i32, v8i16, VR128, + memopv2i64, i128mem, SchedWriteVecIMul.XMM>; + +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in +defm VPSADBW : PDI_binop_rm2<0xF6, "vpsadbw", X86psadbw, v2i64, v16i8, VR128, + loadv2i64, i128mem, SchedWritePSADBW.XMM, 0>, + VEX_4V, VEX_WIG; +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in +defm VPSADBWY : PDI_binop_rm2<0xF6, "vpsadbw", X86psadbw, v4i64, v32i8, VR256, + loadv4i64, i256mem, SchedWritePSADBW.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; +let Constraints = "$src1 = $dst" in +defm PSADBW : PDI_binop_rm2<0xF6, "psadbw", X86psadbw, v2i64, v16i8, VR128, + memopv2i64, i128mem, SchedWritePSADBW.XMM>; + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Logical Instructions +//===---------------------------------------------------------------------===// + +multiclass PDI_binop_rmi opc, bits<8> opc2, Format ImmForm, + string OpcodeStr, SDNode OpNode, + SDNode OpNode2, RegisterClass RC, + X86FoldableSchedWrite sched, + X86FoldableSchedWrite schedImm, + ValueType DstVT, ValueType SrcVT, + PatFrag ld_frag, bit Is2Addr = 1> { + // src2 is always 128-bit + def rr : PDI, + Sched<[sched]>; + def rm : PDI, + Sched<[sched.Folded, ReadAfterLd]>; + def ri : PDIi8, + Sched<[schedImm]>; +} + +multiclass PDI_binop_rmi_all opc, bits<8> opc2, Format ImmForm, + string OpcodeStr, SDNode OpNode, + SDNode OpNode2, ValueType DstVT128, + ValueType DstVT256, ValueType SrcVT, + X86SchedWriteWidths sched, + X86SchedWriteWidths schedImm, Predicate prd> { +let Predicates = [HasAVX, prd] in + defm V#NAME : PDI_binop_rmi, VEX_4V, VEX_WIG; +let Predicates = [HasAVX2, prd] in + defm V#NAME#Y : PDI_binop_rmi, VEX_4V, VEX_L, + VEX_WIG; +let Constraints = "$src1 = $dst" in + defm NAME : PDI_binop_rmi; +} + +multiclass PDI_binop_ri opc, Format ImmForm, string OpcodeStr, + SDNode OpNode, RegisterClass RC, ValueType VT, + X86FoldableSchedWrite sched, bit Is2Addr = 1> { + def ri : PDIi8, + Sched<[sched]>; +} + +multiclass PDI_binop_ri_all opc, Format ImmForm, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched> { +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in + defm V#NAME : PDI_binop_ri, VEX_4V, VEX_WIG; +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in + defm V#NAME#Y : PDI_binop_ri, + VEX_4V, VEX_L, VEX_WIG; +let Constraints = "$src1 = $dst" in + defm NAME : PDI_binop_ri; +} + +let ExeDomain = SSEPackedInt in { + defm PSLLW : PDI_binop_rmi_all<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli, + v8i16, v16i16, v8i16, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX_Or_NoBWI>; + defm PSLLD : PDI_binop_rmi_all<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli, + v4i32, v8i32, v4i32, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX>; + defm PSLLQ : PDI_binop_rmi_all<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli, + v2i64, v4i64, v2i64, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX>; + + defm PSRLW : PDI_binop_rmi_all<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli, + v8i16, v16i16, v8i16, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX_Or_NoBWI>; + defm PSRLD : PDI_binop_rmi_all<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli, + v4i32, v8i32, v4i32, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX>; + defm PSRLQ : PDI_binop_rmi_all<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli, + v2i64, v4i64, v2i64, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX>; + + defm PSRAW : PDI_binop_rmi_all<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai, + v8i16, v16i16, v8i16, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX_Or_NoBWI>; + defm PSRAD : PDI_binop_rmi_all<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai, + v4i32, v8i32, v4i32, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX>; + + defm PSLLDQ : PDI_binop_ri_all<0x73, MRM7r, "pslldq", X86vshldq, + SchedWriteShuffle>; + defm PSRLDQ : PDI_binop_ri_all<0x73, MRM3r, "psrldq", X86vshrdq, + SchedWriteShuffle>; +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Comparison Instructions +//===---------------------------------------------------------------------===// + +defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8, + SchedWriteVecALU, 1, TruePredicate>; +defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16, + SchedWriteVecALU, 1, TruePredicate>; +defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32, + SchedWriteVecALU, 1, TruePredicate>; +defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8, + SchedWriteVecALU, 0, TruePredicate>; +defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16, + SchedWriteVecALU, 0, TruePredicate>; +defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32, + SchedWriteVecALU, 0, TruePredicate>; + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Shuffle Instructions +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { +multiclass sse2_pshuffle { +let Predicates = [HasAVX, prd] in { + def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, u8imm:$src2), + !strconcat("v", OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR128:$dst, + (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))]>, + VEX, Sched<[sched.XMM]>, VEX_WIG; + def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst), + (ins i128mem:$src1, u8imm:$src2), + !strconcat("v", OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR128:$dst, + (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)), + (i8 imm:$src2))))]>, VEX, + Sched<[sched.XMM.Folded]>, VEX_WIG; +} + +let Predicates = [HasAVX2, prd] in { + def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst), + (ins VR256:$src1, u8imm:$src2), + !strconcat("v", OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR256:$dst, + (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))]>, + VEX, VEX_L, Sched<[sched.YMM]>, VEX_WIG; + def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst), + (ins i256mem:$src1, u8imm:$src2), + !strconcat("v", OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR256:$dst, + (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)), + (i8 imm:$src2))))]>, VEX, VEX_L, + Sched<[sched.YMM.Folded]>, VEX_WIG; +} + +let Predicates = [UseSSE2] in { + def ri : Ii8<0x70, MRMSrcReg, + (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2), + !strconcat(OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR128:$dst, + (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))]>, + Sched<[sched.XMM]>; + def mi : Ii8<0x70, MRMSrcMem, + (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2), + !strconcat(OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR128:$dst, + (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)), + (i8 imm:$src2))))]>, + Sched<[sched.XMM.Folded]>; +} +} +} // ExeDomain = SSEPackedInt + +defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd, + SchedWriteShuffle, NoVLX>, PD; +defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw, + SchedWriteShuffle, NoVLX_Or_NoBWI>, XS; +defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw, + SchedWriteShuffle, NoVLX_Or_NoBWI>, XD; + +//===---------------------------------------------------------------------===// +// Packed Integer Pack Instructions (SSE & AVX) +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { +multiclass sse2_pack opc, string OpcodeStr, ValueType OutVT, + ValueType ArgVT, SDNode OpNode, RegisterClass RC, + X86MemOperand x86memop, X86FoldableSchedWrite sched, + PatFrag ld_frag, bit Is2Addr = 1> { + def rr : PDI, + Sched<[sched]>; + def rm : PDI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass sse4_pack opc, string OpcodeStr, ValueType OutVT, + ValueType ArgVT, SDNode OpNode, RegisterClass RC, + X86MemOperand x86memop, X86FoldableSchedWrite sched, + PatFrag ld_frag, bit Is2Addr = 1> { + def rr : SS48I, + Sched<[sched]>; + def rm : SS48I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + + defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V; +} + +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { + defm VPACKSSWBY : sse2_pack<0x63, "vpacksswb", v32i8, v16i16, X86Packss, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPACKSSDWY : sse2_pack<0x6B, "vpackssdw", v16i16, v8i32, X86Packss, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + + defm VPACKUSWBY : sse2_pack<0x67, "vpackuswb", v32i8, v16i16, X86Packus, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPACKUSDWY : sse4_pack<0x2B, "vpackusdw", v16i16, v8i32, X86Packus, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L; +} + +let Constraints = "$src1 = $dst" in { + defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + + defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + + defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; +} +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Unpack Instructions +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { +multiclass sse2_unpack opc, string OpcodeStr, ValueType vt, + SDNode OpNode, RegisterClass RC, X86MemOperand x86memop, + X86FoldableSchedWrite sched, PatFrag ld_frag, + bit Is2Addr = 1> { + def rr : PDI, + Sched<[sched]>; + def rm : PDI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; +} + +let Predicates = [HasAVX, NoVLX] in { + defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; +} + +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { + defm VPUNPCKLBWY : sse2_unpack<0x60, "vpunpcklbw", v32i8, X86Unpckl, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPUNPCKLWDY : sse2_unpack<0x61, "vpunpcklwd", v16i16, X86Unpckl, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPUNPCKHBWY : sse2_unpack<0x68, "vpunpckhbw", v32i8, X86Unpckh, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPUNPCKHWDY : sse2_unpack<0x69, "vpunpckhwd", v16i16, X86Unpckh, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; +} + +let Predicates = [HasAVX2, NoVLX] in { + defm VPUNPCKLDQY : sse2_unpack<0x62, "vpunpckldq", v8i32, X86Unpckl, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPUNPCKLQDQY : sse2_unpack<0x6C, "vpunpcklqdq", v4i64, X86Unpckl, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPUNPCKHDQY : sse2_unpack<0x6A, "vpunpckhdq", v8i32, X86Unpckh, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPUNPCKHQDQY : sse2_unpack<0x6D, "vpunpckhqdq", v4i64, X86Unpckh, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; +} + +let Constraints = "$src1 = $dst" in { + defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + + defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; +} +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Extract and Insert +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { +multiclass sse2_pinsrw { + def rr : Ii8<0xC4, MRMSrcReg, + (outs VR128:$dst), (ins VR128:$src1, + GR32orGR64:$src2, u8imm:$src3), + !if(Is2Addr, + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), + [(set VR128:$dst, + (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))]>, + Sched<[WriteVecInsert]>; + def rm : Ii8<0xC4, MRMSrcMem, + (outs VR128:$dst), (ins VR128:$src1, + i16mem:$src2, u8imm:$src3), + !if(Is2Addr, + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), + [(set VR128:$dst, + (X86pinsrw VR128:$src1, (extloadi16 addr:$src2), + imm:$src3))]>, + Sched<[WriteVecInsertLd, ReadAfterLd]>; +} + +// Extract +let Predicates = [HasAVX, NoBWI] in +def VPEXTRWrr : Ii8<0xC5, MRMSrcReg, + (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2), + "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1), + imm:$src2))]>, + PD, VEX, Sched<[WriteVecExtract]>; +def PEXTRWrr : PDIi8<0xC5, MRMSrcReg, + (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2), + "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1), + imm:$src2))]>, + Sched<[WriteVecExtract]>; + +// Insert +let Predicates = [HasAVX, NoBWI] in +defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V; + +let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in +defm PINSRW : sse2_pinsrw, PD; + +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Mask Creation +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { + +def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), + (ins VR128:$src), + "pmovmskb\t{$src, $dst|$dst, $src}", + [(set GR32orGR64:$dst, (X86movmsk (v16i8 VR128:$src)))]>, + Sched<[WriteVecMOVMSK]>, VEX, VEX_WIG; + +let Predicates = [HasAVX2] in { +def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), + (ins VR256:$src), + "pmovmskb\t{$src, $dst|$dst, $src}", + [(set GR32orGR64:$dst, (X86movmsk (v32i8 VR256:$src)))]>, + Sched<[WriteVecMOVMSKY]>, VEX, VEX_L, VEX_WIG; +} + +def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src), + "pmovmskb\t{$src, $dst|$dst, $src}", + [(set GR32orGR64:$dst, (X86movmsk (v16i8 VR128:$src)))]>, + Sched<[WriteVecMOVMSK]>; + +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// SSE2 - Conditional Store +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecMoveLS.XMM.MR] in { +let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in +def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs), + (ins VR128:$src, VR128:$mask), + "maskmovdqu\t{$mask, $src|$src, $mask}", + [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, + VEX, VEX_WIG; +let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in +def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs), + (ins VR128:$src, VR128:$mask), + "maskmovdqu\t{$mask, $src|$src, $mask}", + [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, + VEX, VEX_WIG; + +let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in +def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask), + "maskmovdqu\t{$mask, $src|$src, $mask}", + [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>; +let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in +def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask), + "maskmovdqu\t{$mask, $src|$src, $mask}", + [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>; + +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// SSE2 - Move Doubleword/Quadword +//===---------------------------------------------------------------------===// + +//===---------------------------------------------------------------------===// +// Move Int Doubleword to Packed Double Int +// +let ExeDomain = SSEPackedInt in { +def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (scalar_to_vector GR32:$src)))]>, + VEX, Sched<[WriteVecMoveFromGpr]>; +def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>, + VEX, Sched<[WriteVecLoad]>; +def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector GR64:$src)))]>, + VEX, Sched<[WriteVecMoveFromGpr]>; +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in +def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), + "movq\t{$src, $dst|$dst, $src}", []>, + VEX, Sched<[WriteVecLoad]>; +let isCodeGenOnly = 1 in +def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (bitconvert GR64:$src))]>, + VEX, Sched<[WriteVecMoveFromGpr]>; + +def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (scalar_to_vector GR32:$src)))]>, + Sched<[WriteVecMoveFromGpr]>; +def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>, + Sched<[WriteVecLoad]>; +def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector GR64:$src)))]>, + Sched<[WriteVecMoveFromGpr]>; +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in +def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), + "movq\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteVecLoad]>; +let isCodeGenOnly = 1 in +def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (bitconvert GR64:$src))]>, + Sched<[WriteVecMoveFromGpr]>; +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// Move Int Doubleword to Single Scalar +// +let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in { + def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set FR32:$dst, (bitconvert GR32:$src))]>, + VEX, Sched<[WriteVecMoveFromGpr]>; + + def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>, + VEX, Sched<[WriteVecLoad]>; + def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set FR32:$dst, (bitconvert GR32:$src))]>, + Sched<[WriteVecMoveFromGpr]>; + + def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>, + Sched<[WriteVecLoad]>; +} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1 + +//===---------------------------------------------------------------------===// +// Move Packed Doubleword Int to Packed Double Int +// +let ExeDomain = SSEPackedInt in { +def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (extractelt (v4i32 VR128:$src), + (iPTR 0)))]>, VEX, + Sched<[WriteVecMoveToGpr]>; +def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs), + (ins i32mem:$dst, VR128:$src), + "movd\t{$src, $dst|$dst, $src}", + [(store (i32 (extractelt (v4i32 VR128:$src), + (iPTR 0))), addr:$dst)]>, + VEX, Sched<[WriteVecStore]>; +def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (extractelt (v4i32 VR128:$src), + (iPTR 0)))]>, + Sched<[WriteVecMoveToGpr]>; +def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src), + "movd\t{$src, $dst|$dst, $src}", + [(store (i32 (extractelt (v4i32 VR128:$src), + (iPTR 0))), addr:$dst)]>, + Sched<[WriteVecStore]>; +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// Move Packed Doubleword Int first element to Doubleword Int +// +let ExeDomain = SSEPackedInt in { +let SchedRW = [WriteVecMoveToGpr] in { +def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (extractelt (v2i64 VR128:$src), + (iPTR 0)))]>, + VEX; + +def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (extractelt (v2i64 VR128:$src), + (iPTR 0)))]>; +} //SchedRW + +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in +def VMOVPQIto64mr : VRS2I<0x7E, MRMDestMem, (outs), + (ins i64mem:$dst, VR128:$src), + "movq\t{$src, $dst|$dst, $src}", []>, + VEX, Sched<[WriteVecStore]>; +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in +def MOVPQIto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), + "movq\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteVecStore]>; +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// Bitcast FR64 <-> GR64 +// +let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in { + let Predicates = [UseAVX] in + def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>, + VEX, Sched<[WriteVecLoad]>; + def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (bitconvert FR64:$src))]>, + VEX, Sched<[WriteVecMoveToGpr]>; + def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>, + VEX, Sched<[WriteVecStore]>; + + def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>, + Sched<[WriteVecLoad]>; + def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (bitconvert FR64:$src))]>, + Sched<[WriteVecMoveToGpr]>; + def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>, + Sched<[WriteVecStore]>; +} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1 + +//===---------------------------------------------------------------------===// +// Move Scalar Single to Double Int +// +let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in { + def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (bitconvert FR32:$src))]>, + VEX, Sched<[WriteVecMoveToGpr]>; + def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, + VEX, Sched<[WriteVecStore]>; + def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (bitconvert FR32:$src))]>, + Sched<[WriteVecMoveToGpr]>; + def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, + Sched<[WriteVecStore]>; +} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1 + +let Predicates = [UseAVX] in { + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))), + (VMOVDI2PDIrr GR32:$src)>; + + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))), + (VMOV64toPQIrr GR64:$src)>; + + def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, + (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOV64toPQIrr GR64:$src)), sub_xmm)>; + // AVX 128-bit movd/movq instructions write zeros in the high 128-bit part. + // These instructions also write zeros in the high part of a 256-bit register. + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (zextloadi64i32 addr:$src))))), + (VMOVDI2PDIrm addr:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))), + (VMOVDI2PDIrm addr:$src)>; + def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))), + (VMOVDI2PDIrm addr:$src)>; + def : Pat<(v4i32 (X86vzload addr:$src)), + (VMOVDI2PDIrm addr:$src)>; + def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIrm addr:$src)), sub_xmm)>; + def : Pat<(v8i32 (X86vzload addr:$src)), + (SUBREG_TO_REG (i64 0), (v4i32 (VMOVDI2PDIrm addr:$src)), sub_xmm)>; + // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext. + def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIrr GR32:$src)), sub_xmm)>; +} + +let Predicates = [UseSSE2] in { + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))), + (MOVDI2PDIrr GR32:$src)>; + + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))), + (MOV64toPQIrr GR64:$src)>; + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (zextloadi64i32 addr:$src))))), + (MOVDI2PDIrm addr:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))), + (MOVDI2PDIrm addr:$src)>; + def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))), + (MOVDI2PDIrm addr:$src)>; + def : Pat<(v4i32 (X86vzload addr:$src)), + (MOVDI2PDIrm addr:$src)>; +} + +// Before the MC layer of LLVM existed, clang emitted "movd" assembly instead of +// "movq" due to MacOS parsing limitation. In order to parse old assembly, we add +// these aliases. +// def : InstAlias<"movd\t{$src, $dst|$dst, $src}", +// (MOV64toPQIrr VR128:$dst, GR64:$src), 0>; +// def : InstAlias<"movd\t{$src, $dst|$dst, $src}", +// (MOVPQIto64rr GR64:$dst, VR128:$src), 0>; +// Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX. +// def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}", +// (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>; +// def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}", +// (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>; + +//===---------------------------------------------------------------------===// +// SSE2 - Move Quadword +//===---------------------------------------------------------------------===// + +//===---------------------------------------------------------------------===// +// Move Quadword Int to Packed Quadword Int +// + +let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLoad] in { +def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS, + VEX, Requires<[UseAVX]>, VEX_WIG; +def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, + XS, Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix +} // ExeDomain, SchedRW + +//===---------------------------------------------------------------------===// +// Move Packed Quadword Int to Quadword Int +// +let ExeDomain = SSEPackedInt, SchedRW = [WriteVecStore] in { +def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), + "movq\t{$src, $dst|$dst, $src}", + [(store (i64 (extractelt (v2i64 VR128:$src), + (iPTR 0))), addr:$dst)]>, + VEX, VEX_WIG; +def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), + "movq\t{$src, $dst|$dst, $src}", + [(store (i64 (extractelt (v2i64 VR128:$src), + (iPTR 0))), addr:$dst)]>; +} // ExeDomain, SchedRW + +// For disassembler only +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, + SchedRW = [SchedWriteVecLogic.XMM] in { +def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_WIG; +def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movq\t{$src, $dst|$dst, $src}", []>; +} + +// Aliases to help the assembler pick two byte VEX encodings by swapping the +// operands relative to the normal instructions to use VEX.R instead of VEX.B. +// def : InstAlias<"vmovq\t{$src, $dst|$dst, $src}", +// (VMOVPQI2QIrr VR128L:$dst, VR128H:$src), 0>; + +// def : InstAlias<"vmovq.s\t{$src, $dst|$dst, $src}", +// (VMOVPQI2QIrr VR128:$dst, VR128:$src), 0>; +// def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}", +// (MOVPQI2QIrr VR128:$dst, VR128:$src), 0>; + +let Predicates = [UseAVX] in { + def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))), + (VMOVQI2PQIrm addr:$src)>; + def : Pat<(v2i64 (X86vzload addr:$src)), + (VMOVQI2PQIrm addr:$src)>; + def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, + (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIrm addr:$src)), sub_xmm)>; + def : Pat<(v4i64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIrm addr:$src)), sub_xmm)>; +} + +let Predicates = [UseSSE2] in { + def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))), + (MOVQI2PQIrm addr:$src)>; + def : Pat<(v2i64 (X86vzload addr:$src)), (MOVQI2PQIrm addr:$src)>; +} + +//===---------------------------------------------------------------------===// +// Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in +// IA32 document. movq xmm1, xmm2 does clear the high bits. +// +let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecLogic.XMM] in { +def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>, + XS, VEX, Requires<[UseAVX]>, VEX_WIG; +def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>, + XS, Requires<[UseSSE2]>; +} // ExeDomain, SchedRW + +let Predicates = [UseAVX] in { + def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))), + (VMOVZPQILo2PQIrr VR128:$src)>; +} +let Predicates = [UseSSE2] in { + def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))), + (MOVZPQILo2PQIrr VR128:$src)>; +} + +//===---------------------------------------------------------------------===// +// SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP +//===---------------------------------------------------------------------===// + +multiclass sse3_replicate_sfp op, SDNode OpNode, string OpcodeStr, + ValueType vt, RegisterClass RC, PatFrag mem_frag, + X86MemOperand x86memop, X86FoldableSchedWrite sched> { +def rr : S3SI, + Sched<[sched]>; +def rm : S3SI, + Sched<[sched.Folded]>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup", + v4f32, VR128, loadv4f32, f128mem, + SchedWriteFShuffle.XMM>, VEX, VEX_WIG; + defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup", + v4f32, VR128, loadv4f32, f128mem, + SchedWriteFShuffle.XMM>, VEX, VEX_WIG; + defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup", + v8f32, VR256, loadv8f32, f256mem, + SchedWriteFShuffle.YMM>, VEX, VEX_L, VEX_WIG; + defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup", + v8f32, VR256, loadv8f32, f256mem, + SchedWriteFShuffle.YMM>, VEX, VEX_L, VEX_WIG; +} +defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128, + memopv4f32, f128mem, SchedWriteFShuffle.XMM>; +defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128, + memopv4f32, f128mem, SchedWriteFShuffle.XMM>; + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4i32 (X86Movshdup VR128:$src)), + (VMOVSHDUPrr VR128:$src)>; + def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))), + (VMOVSHDUPrm addr:$src)>; + def : Pat<(v4i32 (X86Movsldup VR128:$src)), + (VMOVSLDUPrr VR128:$src)>; + def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))), + (VMOVSLDUPrm addr:$src)>; + def : Pat<(v8i32 (X86Movshdup VR256:$src)), + (VMOVSHDUPYrr VR256:$src)>; + def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))), + (VMOVSHDUPYrm addr:$src)>; + def : Pat<(v8i32 (X86Movsldup VR256:$src)), + (VMOVSLDUPYrr VR256:$src)>; + def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))), + (VMOVSLDUPYrm addr:$src)>; +} + +let Predicates = [UseSSE3] in { + def : Pat<(v4i32 (X86Movshdup VR128:$src)), + (MOVSHDUPrr VR128:$src)>; + def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))), + (MOVSHDUPrm addr:$src)>; + def : Pat<(v4i32 (X86Movsldup VR128:$src)), + (MOVSLDUPrr VR128:$src)>; + def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))), + (MOVSLDUPrm addr:$src)>; +} + +//===---------------------------------------------------------------------===// +// SSE3 - Replicate Double FP - MOVDDUP +//===---------------------------------------------------------------------===// + +multiclass sse3_replicate_dfp { +def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))]>, + Sched<[sched.XMM]>; +def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set VR128:$dst, + (v2f64 (X86Movddup + (scalar_to_vector (loadf64 addr:$src)))))]>, + Sched<[sched.XMM.Folded]>; +} + +// FIXME: Merge with above classes when there are patterns for the ymm version +multiclass sse3_replicate_dfp_y { +def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>, + Sched<[sched.YMM]>; +def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set VR256:$dst, + (v4f64 (X86Movddup (loadv4f64 addr:$src))))]>, + Sched<[sched.YMM.Folded]>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm VMOVDDUP : sse3_replicate_dfp<"vmovddup", SchedWriteFShuffle>, + VEX, VEX_WIG; + defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup", SchedWriteFShuffle>, + VEX, VEX_L, VEX_WIG; +} + +defm MOVDDUP : sse3_replicate_dfp<"movddup", SchedWriteFShuffle>; + + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(X86Movddup (loadv2f64 addr:$src)), + (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; +} + +let Predicates = [UseSSE3] in { + // No need for aligned memory as this only loads 64-bits. + def : Pat<(X86Movddup (loadv2f64 addr:$src)), + (MOVDDUPrm addr:$src)>; +} + +//===---------------------------------------------------------------------===// +// SSE3 - Move Unaligned Integer +//===---------------------------------------------------------------------===// + +let Predicates = [HasAVX] in { + def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "vlddqu\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, + Sched<[SchedWriteVecMoveLS.XMM.RM]>, VEX, VEX_WIG; + def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src), + "vlddqu\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, + Sched<[SchedWriteVecMoveLS.YMM.RM]>, VEX, VEX_L, VEX_WIG; +} // Predicates + +def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "lddqu\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, + Sched<[SchedWriteVecMoveLS.XMM.RM]>; + +//===---------------------------------------------------------------------===// +// SSE3 - Arithmetic +//===---------------------------------------------------------------------===// + +multiclass sse3_addsub { + def rr : I<0xD0, MRMSrcReg, + (outs RC:$dst), (ins RC:$src1, RC:$src2), + !if(Is2Addr, + !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), + [(set RC:$dst, (vt (X86Addsub RC:$src1, RC:$src2)))]>, + Sched<[sched]>; + def rm : I<0xD0, MRMSrcMem, + (outs RC:$dst), (ins RC:$src1, x86memop:$src2), + !if(Is2Addr, + !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), + [(set RC:$dst, (vt (X86Addsub RC:$src1, (ld_frag addr:$src2))))]>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX] in { + let ExeDomain = SSEPackedSingle in { + defm VADDSUBPS : sse3_addsub<"vaddsubps", v4f32, VR128, f128mem, + SchedWriteFAddSizes.PS.XMM, loadv4f32, 0>, + XD, VEX_4V, VEX_WIG; + defm VADDSUBPSY : sse3_addsub<"vaddsubps", v8f32, VR256, f256mem, + SchedWriteFAddSizes.PS.YMM, loadv8f32, 0>, + XD, VEX_4V, VEX_L, VEX_WIG; + } + let ExeDomain = SSEPackedDouble in { + defm VADDSUBPD : sse3_addsub<"vaddsubpd", v2f64, VR128, f128mem, + SchedWriteFAddSizes.PD.XMM, loadv2f64, 0>, + PD, VEX_4V, VEX_WIG; + defm VADDSUBPDY : sse3_addsub<"vaddsubpd", v4f64, VR256, f256mem, + SchedWriteFAddSizes.PD.YMM, loadv4f64, 0>, + PD, VEX_4V, VEX_L, VEX_WIG; + } +} +let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in { + let ExeDomain = SSEPackedSingle in + defm ADDSUBPS : sse3_addsub<"addsubps", v4f32, VR128, f128mem, + SchedWriteFAddSizes.PS.XMM, memopv4f32>, XD; + let ExeDomain = SSEPackedDouble in + defm ADDSUBPD : sse3_addsub<"addsubpd", v2f64, VR128, f128mem, + SchedWriteFAddSizes.PD.XMM, memopv2f64>, PD; +} + +//===---------------------------------------------------------------------===// +// SSE3 Instructions +//===---------------------------------------------------------------------===// + +// Horizontal ops +multiclass S3D_Int o, string OpcodeStr, ValueType vt, RegisterClass RC, + X86MemOperand x86memop, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag ld_frag, + bit Is2Addr = 1> { + def rr : S3DI, + Sched<[sched]>; + + def rm : S3DI, + Sched<[sched.Folded, ReadAfterLd]>; +} +multiclass S3_Int o, string OpcodeStr, ValueType vt, RegisterClass RC, + X86MemOperand x86memop, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag ld_frag, + bit Is2Addr = 1> { + def rr : S3I, + Sched<[sched]>; + + def rm : S3I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX] in { + let ExeDomain = SSEPackedSingle in { + defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem, + X86fhadd, WriteFHAdd, loadv4f32, 0>, VEX_4V, VEX_WIG; + defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem, + X86fhsub, WriteFHAdd, loadv4f32, 0>, VEX_4V, VEX_WIG; + defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem, + X86fhadd, WriteFHAddY, loadv8f32, 0>, VEX_4V, VEX_L, VEX_WIG; + defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem, + X86fhsub, WriteFHAddY, loadv8f32, 0>, VEX_4V, VEX_L, VEX_WIG; + } + let ExeDomain = SSEPackedDouble in { + defm VHADDPD : S3_Int<0x7C, "vhaddpd", v2f64, VR128, f128mem, + X86fhadd, WriteFHAdd, loadv2f64, 0>, VEX_4V, VEX_WIG; + defm VHSUBPD : S3_Int<0x7D, "vhsubpd", v2f64, VR128, f128mem, + X86fhsub, WriteFHAdd, loadv2f64, 0>, VEX_4V, VEX_WIG; + defm VHADDPDY : S3_Int<0x7C, "vhaddpd", v4f64, VR256, f256mem, + X86fhadd, WriteFHAddY, loadv4f64, 0>, VEX_4V, VEX_L, VEX_WIG; + defm VHSUBPDY : S3_Int<0x7D, "vhsubpd", v4f64, VR256, f256mem, + X86fhsub, WriteFHAddY, loadv4f64, 0>, VEX_4V, VEX_L, VEX_WIG; + } +} + +let Constraints = "$src1 = $dst" in { + let ExeDomain = SSEPackedSingle in { + defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd, + WriteFHAdd, memopv4f32>; + defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub, + WriteFHAdd, memopv4f32>; + } + let ExeDomain = SSEPackedDouble in { + defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd, + WriteFHAdd, memopv2f64>; + defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub, + WriteFHAdd, memopv2f64>; + } +} + +//===---------------------------------------------------------------------===// +// SSSE3 - Packed Absolute Instructions +//===---------------------------------------------------------------------===// + +/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}. +multiclass SS3I_unop_rm opc, string OpcodeStr, ValueType vt, + SDNode OpNode, X86SchedWriteWidths sched, PatFrag ld_frag> { + def rr : SS38I, + Sched<[sched.XMM]>; + + def rm : SS38I, + Sched<[sched.XMM.Folded]>; +} + +/// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}. +multiclass SS3I_unop_rm_y opc, string OpcodeStr, ValueType vt, + SDNode OpNode, X86SchedWriteWidths sched> { + def Yrr : SS38I, + Sched<[sched.YMM]>; + + def Yrm : SS38I, + Sched<[sched.YMM.Folded]>; +} + +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + defm VPABSB : SS3I_unop_rm<0x1C, "vpabsb", v16i8, abs, SchedWriteVecALU, + loadv2i64>, VEX, VEX_WIG; + defm VPABSW : SS3I_unop_rm<0x1D, "vpabsw", v8i16, abs, SchedWriteVecALU, + loadv2i64>, VEX, VEX_WIG; +} +let Predicates = [HasAVX, NoVLX] in { + defm VPABSD : SS3I_unop_rm<0x1E, "vpabsd", v4i32, abs, SchedWriteVecALU, + loadv2i64>, VEX, VEX_WIG; +} +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { + defm VPABSB : SS3I_unop_rm_y<0x1C, "vpabsb", v32i8, abs, SchedWriteVecALU>, + VEX, VEX_L, VEX_WIG; + defm VPABSW : SS3I_unop_rm_y<0x1D, "vpabsw", v16i16, abs, SchedWriteVecALU>, + VEX, VEX_L, VEX_WIG; +} +let Predicates = [HasAVX2, NoVLX] in { + defm VPABSD : SS3I_unop_rm_y<0x1E, "vpabsd", v8i32, abs, SchedWriteVecALU>, + VEX, VEX_L, VEX_WIG; +} + +defm PABSB : SS3I_unop_rm<0x1C, "pabsb", v16i8, abs, SchedWriteVecALU, + memopv2i64>; +defm PABSW : SS3I_unop_rm<0x1D, "pabsw", v8i16, abs, SchedWriteVecALU, + memopv2i64>; +defm PABSD : SS3I_unop_rm<0x1E, "pabsd", v4i32, abs, SchedWriteVecALU, + memopv2i64>; + +//===---------------------------------------------------------------------===// +// SSSE3 - Packed Binary Operator Instructions +//===---------------------------------------------------------------------===// + +/// SS3I_binop_rm - Simple SSSE3 bin op +multiclass SS3I_binop_rm opc, string OpcodeStr, SDNode OpNode, + ValueType DstVT, ValueType OpVT, RegisterClass RC, + PatFrag memop_frag, X86MemOperand x86memop, + X86FoldableSchedWrite sched, bit Is2Addr = 1> { + let isCommutable = 1 in + def rr : SS38I, + Sched<[sched]>; + def rm : SS38I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +/// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}. +multiclass SS3I_binop_rm_int opc, string OpcodeStr, + Intrinsic IntId128, X86FoldableSchedWrite sched, + PatFrag ld_frag, bit Is2Addr = 1> { + let isCommutable = 1 in + def rr : SS38I, + Sched<[sched]>; + def rm : SS38I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass SS3I_binop_rm_int_y opc, string OpcodeStr, + Intrinsic IntId256, + X86FoldableSchedWrite sched> { + let isCommutable = 1 in + def Yrr : SS38I, + Sched<[sched]>; + def Yrm : SS38I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let ImmT = NoImm, Predicates = [HasAVX, NoVLX_Or_NoBWI] in { +let isCommutable = 0 in { + defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, v16i8, + VR128, loadv2i64, i128mem, + SchedWriteVarShuffle.XMM, 0>, VEX_4V, VEX_WIG; + defm VPMADDUBSW : SS3I_binop_rm<0x04, "vpmaddubsw", X86vpmaddubsw, v8i16, + v16i8, VR128, loadv2i64, i128mem, + SchedWriteVecIMul.XMM, 0>, VEX_4V, VEX_WIG; +} +defm VPMULHRSW : SS3I_binop_rm<0x0B, "vpmulhrsw", X86mulhrs, v8i16, v8i16, + VR128, loadv2i64, i128mem, + SchedWriteVecIMul.XMM, 0>, VEX_4V, VEX_WIG; +} + +let ImmT = NoImm, Predicates = [HasAVX] in { +let isCommutable = 0 in { + defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, v8i16, VR128, + loadv2i64, i128mem, + SchedWritePHAdd.XMM, 0>, VEX_4V, VEX_WIG; + defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, v4i32, VR128, + loadv2i64, i128mem, + SchedWritePHAdd.XMM, 0>, VEX_4V, VEX_WIG; + defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, v8i16, VR128, + loadv2i64, i128mem, + SchedWritePHAdd.XMM, 0>, VEX_4V, VEX_WIG; + defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, v4i32, VR128, + loadv2i64, i128mem, + SchedWritePHAdd.XMM, 0>, VEX_4V; + defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", + int_x86_ssse3_psign_b_128, + SchedWriteVecALU.XMM, loadv2i64, 0>, VEX_4V, VEX_WIG; + defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", + int_x86_ssse3_psign_w_128, + SchedWriteVecALU.XMM, loadv2i64, 0>, VEX_4V, VEX_WIG; + defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", + int_x86_ssse3_psign_d_128, + SchedWriteVecALU.XMM, loadv2i64, 0>, VEX_4V, VEX_WIG; + defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", + int_x86_ssse3_phadd_sw_128, + SchedWritePHAdd.XMM, loadv2i64, 0>, VEX_4V, VEX_WIG; + defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", + int_x86_ssse3_phsub_sw_128, + SchedWritePHAdd.XMM, loadv2i64, 0>, VEX_4V, VEX_WIG; +} +} + +let ImmT = NoImm, Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { +let isCommutable = 0 in { + defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, v32i8, + VR256, loadv4i64, i256mem, + SchedWriteVarShuffle.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; + defm VPMADDUBSWY : SS3I_binop_rm<0x04, "vpmaddubsw", X86vpmaddubsw, v16i16, + v32i8, VR256, loadv4i64, i256mem, + SchedWriteVecIMul.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; +} +defm VPMULHRSWY : SS3I_binop_rm<0x0B, "vpmulhrsw", X86mulhrs, v16i16, v16i16, + VR256, loadv4i64, i256mem, + SchedWriteVecIMul.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; +} + +let ImmT = NoImm, Predicates = [HasAVX2] in { +let isCommutable = 0 in { + defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, v16i16, + VR256, loadv4i64, i256mem, + SchedWritePHAdd.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; + defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, v8i32, VR256, + loadv4i64, i256mem, + SchedWritePHAdd.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; + defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, v16i16, + VR256, loadv4i64, i256mem, + SchedWritePHAdd.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; + defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, v8i32, VR256, + loadv4i64, i256mem, + SchedWritePHAdd.YMM, 0>, VEX_4V, VEX_L; + defm VPSIGNB : SS3I_binop_rm_int_y<0x08, "vpsignb", int_x86_avx2_psign_b, + SchedWriteVecALU.YMM>, VEX_4V, VEX_L, VEX_WIG; + defm VPSIGNW : SS3I_binop_rm_int_y<0x09, "vpsignw", int_x86_avx2_psign_w, + SchedWriteVecALU.YMM>, VEX_4V, VEX_L, VEX_WIG; + defm VPSIGND : SS3I_binop_rm_int_y<0x0A, "vpsignd", int_x86_avx2_psign_d, + SchedWriteVecALU.YMM>, VEX_4V, VEX_L, VEX_WIG; + defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw", + int_x86_avx2_phadd_sw, + SchedWritePHAdd.YMM>, VEX_4V, VEX_L, VEX_WIG; + defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw", + int_x86_avx2_phsub_sw, + SchedWritePHAdd.YMM>, VEX_4V, VEX_L, VEX_WIG; +} +} + +// None of these have i8 immediate fields. +let ImmT = NoImm, Constraints = "$src1 = $dst" in { +let isCommutable = 0 in { + defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, v8i16, VR128, + memopv2i64, i128mem, SchedWritePHAdd.XMM>; + defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, v4i32, VR128, + memopv2i64, i128mem, SchedWritePHAdd.XMM>; + defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, v8i16, VR128, + memopv2i64, i128mem, SchedWritePHAdd.XMM>; + defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, v4i32, VR128, + memopv2i64, i128mem, SchedWritePHAdd.XMM>; + defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", int_x86_ssse3_psign_b_128, + SchedWriteVecALU.XMM, memopv2i64>; + defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", int_x86_ssse3_psign_w_128, + SchedWriteVecALU.XMM, memopv2i64>; + defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", int_x86_ssse3_psign_d_128, + SchedWriteVecALU.XMM, memopv2i64>; + defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, v16i8, VR128, + memopv2i64, i128mem, SchedWriteVarShuffle.XMM>; + defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", + int_x86_ssse3_phadd_sw_128, + SchedWritePHAdd.XMM, memopv2i64>; + defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", + int_x86_ssse3_phsub_sw_128, + SchedWritePHAdd.XMM, memopv2i64>; + defm PMADDUBSW : SS3I_binop_rm<0x04, "pmaddubsw", X86vpmaddubsw, v8i16, + v16i8, VR128, memopv2i64, i128mem, + SchedWriteVecIMul.XMM>; +} +defm PMULHRSW : SS3I_binop_rm<0x0B, "pmulhrsw", X86mulhrs, v8i16, v8i16, + VR128, memopv2i64, i128mem, SchedWriteVecIMul.XMM>; +} + +//===---------------------------------------------------------------------===// +// SSSE3 - Packed Align Instruction Patterns +//===---------------------------------------------------------------------===// + +multiclass ssse3_palignr { + let hasSideEffects = 0 in { + def rri : SS3AI<0x0F, MRMSrcReg, (outs RC:$dst), + (ins RC:$src1, RC:$src2, u8imm:$src3), + !if(Is2Addr, + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + !strconcat(asm, + "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")), + [(set RC:$dst, (VT (X86PAlignr RC:$src1, RC:$src2, (i8 imm:$src3))))]>, + Sched<[sched]>; + let mayLoad = 1 in + def rmi : SS3AI<0x0F, MRMSrcMem, (outs RC:$dst), + (ins RC:$src1, x86memop:$src2, u8imm:$src3), + !if(Is2Addr, + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + !strconcat(asm, + "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")), + [(set RC:$dst, (VT (X86PAlignr RC:$src1, + (bitconvert (memop_frag addr:$src2)), + (i8 imm:$src3))))]>, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in + defm VPALIGNR : ssse3_palignr<"vpalignr", v16i8, VR128, loadv2i64, i128mem, + SchedWriteShuffle.XMM, 0>, VEX_4V, VEX_WIG; +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in + defm VPALIGNRY : ssse3_palignr<"vpalignr", v32i8, VR256, loadv4i64, i256mem, + SchedWriteShuffle.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; +let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in + defm PALIGNR : ssse3_palignr<"palignr", v16i8, VR128, memopv2i64, i128mem, + SchedWriteShuffle.XMM>; + +//===---------------------------------------------------------------------===// +// SSSE3 - Thread synchronization +//===---------------------------------------------------------------------===// + +let SchedRW = [WriteSystem] in { +/* +let usesCustomInserter = 1 in { +def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3), + [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>, + Requires<[HasSSE3]>; +} +*/ + +let Uses = [EAX, ECX, EDX] in +def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, + TB, Requires<[HasSSE3]>; + +let Uses = [ECX, EAX] in +def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", + [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>; +} // SchedRW + +// def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>; +// def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>; + +// def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>, +// Requires<[Not64BitMode]>; +// def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>, +// Requires<[In64BitMode]>; + +//===----------------------------------------------------------------------===// +// SSE4.1 - Packed Move with Sign/Zero Extend +//===----------------------------------------------------------------------===// + +multiclass SS41I_pmovx_rrrm opc, string OpcodeStr, X86MemOperand MemOp, + RegisterClass OutRC, RegisterClass InRC, + X86FoldableSchedWrite sched> { + def rr : SS48I, + Sched<[sched]>; + + def rm : SS48I, + Sched<[sched.Folded]>; +} + +multiclass SS41I_pmovx_rm_all opc, string OpcodeStr, + X86MemOperand MemOp, X86MemOperand MemYOp, + Predicate prd> { + defm NAME : SS41I_pmovx_rrrm; + let Predicates = [HasAVX, prd] in + defm V#NAME : SS41I_pmovx_rrrm, + VEX, VEX_WIG; + let Predicates = [HasAVX2, prd] in + defm V#NAME#Y : SS41I_pmovx_rrrm, + VEX, VEX_L, VEX_WIG; +} + +multiclass SS41I_pmovx_rm opc, string OpcodeStr, X86MemOperand MemOp, + X86MemOperand MemYOp, Predicate prd> { + defm PMOVSX#NAME : SS41I_pmovx_rm_all; + defm PMOVZX#NAME : SS41I_pmovx_rm_all; +} + +defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem, NoVLX_Or_NoBWI>; +defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem, NoVLX>; +defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem, NoVLX>; + +defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem, NoVLX>; +defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem, NoVLX>; + +defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem, NoVLX>; + +// AVX2 Patterns +multiclass SS41I_pmovx_avx2_patterns { + // Register-Register patterns + let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))), + (!cast(OpcPrefix#BWYrr) VR128:$src)>; + } + let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))), + (!cast(OpcPrefix#BDYrr) VR128:$src)>; + def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))), + (!cast(OpcPrefix#BQYrr) VR128:$src)>; + + def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))), + (!cast(OpcPrefix#WDYrr) VR128:$src)>; + def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))), + (!cast(OpcPrefix#WQYrr) VR128:$src)>; + + def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))), + (!cast(OpcPrefix#DQYrr) VR128:$src)>; + } + + // Simple Register-Memory patterns + let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + def : Pat<(v16i16 (!cast(ExtTy#"extloadvi8") addr:$src)), + (!cast(OpcPrefix#BWYrm) addr:$src)>; + } + let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v8i32 (!cast(ExtTy#"extloadvi8") addr:$src)), + (!cast(OpcPrefix#BDYrm) addr:$src)>; + def : Pat<(v4i64 (!cast(ExtTy#"extloadvi8") addr:$src)), + (!cast(OpcPrefix#BQYrm) addr:$src)>; + + def : Pat<(v8i32 (!cast(ExtTy#"extloadvi16") addr:$src)), + (!cast(OpcPrefix#WDYrm) addr:$src)>; + def : Pat<(v4i64 (!cast(ExtTy#"extloadvi16") addr:$src)), + (!cast(OpcPrefix#WQYrm) addr:$src)>; + + def : Pat<(v4i64 (!cast(ExtTy#"extloadvi32") addr:$src)), + (!cast(OpcPrefix#DQYrm) addr:$src)>; + } + + // AVX2 Register-Memory patterns + let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BWYrm) addr:$src)>; + def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWYrm) addr:$src)>; + def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWYrm) addr:$src)>; + } + let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#BDYrm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#BDYrm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BDYrm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BDYrm) addr:$src)>; + + def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))), + (!cast(OpcPrefix#BQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#BQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BQYrm) addr:$src)>; + + def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WDYrm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDYrm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDYrm) addr:$src)>; + + def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#WQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#WQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WQYrm) addr:$src)>; + + def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#DQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQYrm) addr:$src)>; + } +} + +defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>; +defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>; + +// SSE4.1/AVX patterns. +multiclass SS41I_pmovx_patterns { + let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))), + (!cast(OpcPrefix#BWrr) VR128:$src)>; + } + let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))), + (!cast(OpcPrefix#BDrr) VR128:$src)>; + def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))), + (!cast(OpcPrefix#BQrr) VR128:$src)>; + + def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))), + (!cast(OpcPrefix#WDrr) VR128:$src)>; + def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))), + (!cast(OpcPrefix#WQrr) VR128:$src)>; + + def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))), + (!cast(OpcPrefix#DQrr) VR128:$src)>; + } + let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + def : Pat<(v8i16 (!cast(ExtTy#"extloadvi8") addr:$src)), + (!cast(OpcPrefix#BWrm) addr:$src)>; + } + let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4i32 (!cast(ExtTy#"extloadvi8") addr:$src)), + (!cast(OpcPrefix#BDrm) addr:$src)>; + def : Pat<(v2i64 (!cast(ExtTy#"extloadvi8") addr:$src)), + (!cast(OpcPrefix#BQrm) addr:$src)>; + + def : Pat<(v4i32 (!cast(ExtTy#"extloadvi16") addr:$src)), + (!cast(OpcPrefix#WDrm) addr:$src)>; + def : Pat<(v2i64 (!cast(ExtTy#"extloadvi16") addr:$src)), + (!cast(OpcPrefix#WQrm) addr:$src)>; + + def : Pat<(v2i64 (!cast(ExtTy#"extloadvi32") addr:$src)), + (!cast(OpcPrefix#DQrm) addr:$src)>; + } + let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#BWrm) addr:$src)>; + def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))), + (!cast(OpcPrefix#BWrm) addr:$src)>; + def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWrm) addr:$src)>; + def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWrm) addr:$src)>; + def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BWrm) addr:$src)>; + } + let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))), + (!cast(OpcPrefix#BDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#BDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BDrm) addr:$src)>; + + def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (extloadi32i16 addr:$src)))))), + (!cast(OpcPrefix#BQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#BQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BQrm) addr:$src)>; + + def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#WDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))), + (!cast(OpcPrefix#WDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WDrm) addr:$src)>; + + def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))), + (!cast(OpcPrefix#WQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#WQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WQrm) addr:$src)>; + + def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#DQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))), + (!cast(OpcPrefix#DQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#DQrm) addr:$src)>; + } +} + +defm : SS41I_pmovx_patterns<"VPMOVSX", "s", sext_invec>; +defm : SS41I_pmovx_patterns<"VPMOVZX", "z", zext_invec>; + +let Predicates = [UseSSE41] in { + defm : SS41I_pmovx_patterns<"PMOVSX", "s", sext_invec>; + defm : SS41I_pmovx_patterns<"PMOVZX", "z", zext_invec>; +} + +//===----------------------------------------------------------------------===// +// SSE4.1 - Extract Instructions +//===----------------------------------------------------------------------===// + +/// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem +multiclass SS41I_extract8 opc, string OpcodeStr> { + def rr : SS4AIi8, + Sched<[WriteVecExtract]>; + let hasSideEffects = 0, mayStore = 1 in + def mr : SS4AIi8, Sched<[WriteVecExtractSt]>; +} + +let Predicates = [HasAVX, NoBWI] in + defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX; + +defm PEXTRB : SS41I_extract8<0x14, "pextrb">; + + +/// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination +multiclass SS41I_extract16 opc, string OpcodeStr> { + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rr_REV : SS4AIi8, + Sched<[WriteVecExtract]>, FoldGenData; + + let hasSideEffects = 0, mayStore = 1 in + def mr : SS4AIi8, Sched<[WriteVecExtractSt]>; +} + +let Predicates = [HasAVX, NoBWI] in + defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX; + +defm PEXTRW : SS41I_extract16<0x15, "pextrw">; + + +/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination +multiclass SS41I_extract32 opc, string OpcodeStr> { + def rr : SS4AIi8, + Sched<[WriteVecExtract]>; + def mr : SS4AIi8, Sched<[WriteVecExtractSt]>; +} + +let Predicates = [HasAVX, NoDQI] in + defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX; + +defm PEXTRD : SS41I_extract32<0x16, "pextrd">; + +/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination +multiclass SS41I_extract64 opc, string OpcodeStr> { + def rr : SS4AIi8, + Sched<[WriteVecExtract]>; + def mr : SS4AIi8, Sched<[WriteVecExtractSt]>; +} + +let Predicates = [HasAVX, NoDQI] in + defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W; + +defm PEXTRQ : SS41I_extract64<0x16, "pextrq">, REX_W; + +/// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory +/// destination +multiclass SS41I_extractf32 opc, string OpcodeStr> { + def rr : SS4AIi8, + Sched<[WriteVecExtract]>; + def mr : SS4AIi8, Sched<[WriteVecExtractSt]>; +} + +let ExeDomain = SSEPackedSingle in { + let Predicates = [UseAVX] in + defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX, VEX_WIG; + defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">; +} + +// Also match an EXTRACTPS store when the store is done as f32 instead of i32. +def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)), + imm:$src2))), + addr:$dst), + (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>, + Requires<[HasAVX]>; +def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)), + imm:$src2))), + addr:$dst), + (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>, + Requires<[UseSSE41]>; + +//===----------------------------------------------------------------------===// +// SSE4.1 - Insert Instructions +//===----------------------------------------------------------------------===// + +multiclass SS41I_insert8 opc, string asm, bit Is2Addr = 1> { + def rr : SS4AIi8, + Sched<[WriteVecInsert]>; + def rm : SS4AIi8, Sched<[WriteVecInsertLd, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoBWI] in + defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V; +let Constraints = "$src1 = $dst" in + defm PINSRB : SS41I_insert8<0x20, "pinsrb">; + +multiclass SS41I_insert32 opc, string asm, bit Is2Addr = 1> { + def rr : SS4AIi8, + Sched<[WriteVecInsert]>; + def rm : SS4AIi8, Sched<[WriteVecInsertLd, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoDQI] in + defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V; +let Constraints = "$src1 = $dst" in + defm PINSRD : SS41I_insert32<0x22, "pinsrd">; + +multiclass SS41I_insert64 opc, string asm, bit Is2Addr = 1> { + def rr : SS4AIi8, + Sched<[WriteVecInsert]>; + def rm : SS4AIi8, Sched<[WriteVecInsertLd, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoDQI] in + defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W; +let Constraints = "$src1 = $dst" in + defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W; + +// insertps has a few different modes, there's the first two here below which +// are optimized inserts that won't zero arbitrary elements in the destination +// vector. The next one matches the intrinsic and could zero arbitrary elements +// in the target vector. +multiclass SS41I_insertf32 opc, string asm, bit Is2Addr = 1> { + def rr : SS4AIi8, + Sched<[SchedWriteFShuffle.XMM]>; + def rm : SS4AIi8, + Sched<[SchedWriteFShuffle.XMM.Folded, ReadAfterLd]>; +} + +let ExeDomain = SSEPackedSingle in { + let Predicates = [UseAVX] in + defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, + VEX_4V, VEX_WIG; + let Constraints = "$src1 = $dst" in + defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1>; +} + +let Predicates = [UseAVX] in { + // If we're inserting an element from a vbroadcast of a load, fold the + // load into the X86insertps instruction. + def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), + (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)), + (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>; + def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), + (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)), + (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>; +} + +//===----------------------------------------------------------------------===// +// SSE4.1 - Round Instructions +//===----------------------------------------------------------------------===// + +multiclass sse41_fp_unop_p opc, string OpcodeStr, + X86MemOperand x86memop, RegisterClass RC, + ValueType VT, PatFrag mem_frag, SDNode OpNode, + X86FoldableSchedWrite sched> { + // Intrinsic operation, reg. + // Vector intrinsic operation, reg + def r : SS4AIi8, + Sched<[sched]>; + + // Vector intrinsic operation, mem + def m : SS4AIi8, + Sched<[sched.Folded]>; +} + +multiclass avx_fp_unop_rm opcss, bits<8> opcsd, + string OpcodeStr, X86FoldableSchedWrite sched> { +let ExeDomain = SSEPackedSingle, hasSideEffects = 0 in { + def SSr : SS4AIi8, Sched<[sched]>; + + let mayLoad = 1 in + def SSm : SS4AIi8, Sched<[sched.Folded, ReadAfterLd]>; +} // ExeDomain = SSEPackedSingle, hasSideEffects = 0 + +let ExeDomain = SSEPackedDouble, hasSideEffects = 0 in { + def SDr : SS4AIi8, Sched<[sched]>; + + let mayLoad = 1 in + def SDm : SS4AIi8, Sched<[sched.Folded, ReadAfterLd]>; +} // ExeDomain = SSEPackedDouble, hasSideEffects = 0 +} + +multiclass sse41_fp_unop_s opcss, bits<8> opcsd, + string OpcodeStr, X86FoldableSchedWrite sched> { +let ExeDomain = SSEPackedSingle, hasSideEffects = 0 in { + def SSr : SS4AIi8, Sched<[sched]>; + + let mayLoad = 1 in + def SSm : SS4AIi8, Sched<[sched.Folded, ReadAfterLd]>; +} // ExeDomain = SSEPackedSingle, hasSideEffects = 0 + +let ExeDomain = SSEPackedDouble, hasSideEffects = 0 in { + def SDr : SS4AIi8, Sched<[sched]>; + + let mayLoad = 1 in + def SDm : SS4AIi8, Sched<[sched.Folded, ReadAfterLd]>; +} // ExeDomain = SSEPackedDouble, hasSideEffects = 0 +} + +multiclass sse41_fp_binop_s opcss, bits<8> opcsd, + string OpcodeStr, X86FoldableSchedWrite sched, + ValueType VT32, ValueType VT64, + SDNode OpNode, bit Is2Addr = 1> { +let ExeDomain = SSEPackedSingle, isCodeGenOnly = 1 in { + def SSr_Int : SS4AIi8, + Sched<[sched]>; + + def SSm_Int : SS4AIi8, + Sched<[sched.Folded, ReadAfterLd]>; +} // ExeDomain = SSEPackedSingle, isCodeGenOnly = 1 + +let ExeDomain = SSEPackedDouble, isCodeGenOnly = 1 in { + def SDr_Int : SS4AIi8, + Sched<[sched]>; + + def SDm_Int : SS4AIi8, + Sched<[sched.Folded, ReadAfterLd]>; +} // ExeDomain = SSEPackedDouble, isCodeGenOnly = 1 +} + +// FP round - roundss, roundps, roundsd, roundpd +let Predicates = [HasAVX, NoVLX] in { + let ExeDomain = SSEPackedSingle in { + // Intrinsic form + defm VROUNDPS : sse41_fp_unop_p<0x08, "vroundps", f128mem, VR128, v4f32, + loadv4f32, X86VRndScale, SchedWriteFRnd.XMM>, + VEX, VEX_WIG; + defm VROUNDPSY : sse41_fp_unop_p<0x08, "vroundps", f256mem, VR256, v8f32, + loadv8f32, X86VRndScale, SchedWriteFRnd.YMM>, + VEX, VEX_L, VEX_WIG; + } + + let ExeDomain = SSEPackedDouble in { + defm VROUNDPD : sse41_fp_unop_p<0x09, "vroundpd", f128mem, VR128, v2f64, + loadv2f64, X86VRndScale, SchedWriteFRnd.XMM>, + VEX, VEX_WIG; + defm VROUNDPDY : sse41_fp_unop_p<0x09, "vroundpd", f256mem, VR256, v4f64, + loadv4f64, X86VRndScale, SchedWriteFRnd.YMM>, + VEX, VEX_L, VEX_WIG; + } +} +let Predicates = [HasAVX, NoAVX512] in { + defm VROUND : sse41_fp_binop_s<0x0A, 0x0B, "vround", SchedWriteFRnd.Scl, + v4f32, v2f64, X86RndScales, 0>, + VEX_4V, VEX_LIG, VEX_WIG; + defm VROUND : avx_fp_unop_rm<0x0A, 0x0B, "vround", SchedWriteFRnd.Scl>, + VEX_4V, VEX_LIG, VEX_WIG; +} + +let Predicates = [UseAVX] in { + def : Pat<(ffloor FR32:$src), + (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x9))>; + def : Pat<(f32 (fnearbyint FR32:$src)), + (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>; + def : Pat<(f32 (fceil FR32:$src)), + (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xA))>; + def : Pat<(f32 (frint FR32:$src)), + (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>; + def : Pat<(f32 (ftrunc FR32:$src)), + (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xB))>; + + def : Pat<(f64 (ffloor FR64:$src)), + (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x9))>; + def : Pat<(f64 (fnearbyint FR64:$src)), + (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>; + def : Pat<(f64 (fceil FR64:$src)), + (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xA))>; + def : Pat<(f64 (frint FR64:$src)), + (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>; + def : Pat<(f64 (ftrunc FR64:$src)), + (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xB))>; +} + +let Predicates = [UseAVX, OptForSize] in { + def : Pat<(ffloor (loadf32 addr:$src)), + (VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0x9))>; + def : Pat<(f32 (fnearbyint (loadf32 addr:$src))), + (VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0xC))>; + def : Pat<(f32 (fceil (loadf32 addr:$src))), + (VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0xA))>; + def : Pat<(f32 (frint (loadf32 addr:$src))), + (VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0x4))>; + def : Pat<(f32 (ftrunc (loadf32 addr:$src))), + (VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0xB))>; + + def : Pat<(f64 (ffloor (loadf64 addr:$src))), + (VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0x9))>; + def : Pat<(f64 (fnearbyint (loadf64 addr:$src))), + (VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0xC))>; + def : Pat<(f64 (fceil (loadf64 addr:$src))), + (VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0xA))>; + def : Pat<(f64 (frint (loadf64 addr:$src))), + (VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0x4))>; + def : Pat<(f64 (ftrunc (loadf64 addr:$src))), + (VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0xB))>; +} + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4f32 (ffloor VR128:$src)), + (VROUNDPSr VR128:$src, (i32 0x9))>; + def : Pat<(v4f32 (fnearbyint VR128:$src)), + (VROUNDPSr VR128:$src, (i32 0xC))>; + def : Pat<(v4f32 (fceil VR128:$src)), + (VROUNDPSr VR128:$src, (i32 0xA))>; + def : Pat<(v4f32 (frint VR128:$src)), + (VROUNDPSr VR128:$src, (i32 0x4))>; + def : Pat<(v4f32 (ftrunc VR128:$src)), + (VROUNDPSr VR128:$src, (i32 0xB))>; + + def : Pat<(v4f32 (ffloor (loadv4f32 addr:$src))), + (VROUNDPSm addr:$src, (i32 0x9))>; + def : Pat<(v4f32 (fnearbyint (loadv4f32 addr:$src))), + (VROUNDPSm addr:$src, (i32 0xC))>; + def : Pat<(v4f32 (fceil (loadv4f32 addr:$src))), + (VROUNDPSm addr:$src, (i32 0xA))>; + def : Pat<(v4f32 (frint (loadv4f32 addr:$src))), + (VROUNDPSm addr:$src, (i32 0x4))>; + def : Pat<(v4f32 (ftrunc (loadv4f32 addr:$src))), + (VROUNDPSm addr:$src, (i32 0xB))>; + + def : Pat<(v2f64 (ffloor VR128:$src)), + (VROUNDPDr VR128:$src, (i32 0x9))>; + def : Pat<(v2f64 (fnearbyint VR128:$src)), + (VROUNDPDr VR128:$src, (i32 0xC))>; + def : Pat<(v2f64 (fceil VR128:$src)), + (VROUNDPDr VR128:$src, (i32 0xA))>; + def : Pat<(v2f64 (frint VR128:$src)), + (VROUNDPDr VR128:$src, (i32 0x4))>; + def : Pat<(v2f64 (ftrunc VR128:$src)), + (VROUNDPDr VR128:$src, (i32 0xB))>; + + def : Pat<(v2f64 (ffloor (loadv2f64 addr:$src))), + (VROUNDPDm addr:$src, (i32 0x9))>; + def : Pat<(v2f64 (fnearbyint (loadv2f64 addr:$src))), + (VROUNDPDm addr:$src, (i32 0xC))>; + def : Pat<(v2f64 (fceil (loadv2f64 addr:$src))), + (VROUNDPDm addr:$src, (i32 0xA))>; + def : Pat<(v2f64 (frint (loadv2f64 addr:$src))), + (VROUNDPDm addr:$src, (i32 0x4))>; + def : Pat<(v2f64 (ftrunc (loadv2f64 addr:$src))), + (VROUNDPDm addr:$src, (i32 0xB))>; + + def : Pat<(v8f32 (ffloor VR256:$src)), + (VROUNDPSYr VR256:$src, (i32 0x9))>; + def : Pat<(v8f32 (fnearbyint VR256:$src)), + (VROUNDPSYr VR256:$src, (i32 0xC))>; + def : Pat<(v8f32 (fceil VR256:$src)), + (VROUNDPSYr VR256:$src, (i32 0xA))>; + def : Pat<(v8f32 (frint VR256:$src)), + (VROUNDPSYr VR256:$src, (i32 0x4))>; + def : Pat<(v8f32 (ftrunc VR256:$src)), + (VROUNDPSYr VR256:$src, (i32 0xB))>; + + def : Pat<(v8f32 (ffloor (loadv8f32 addr:$src))), + (VROUNDPSYm addr:$src, (i32 0x9))>; + def : Pat<(v8f32 (fnearbyint (loadv8f32 addr:$src))), + (VROUNDPSYm addr:$src, (i32 0xC))>; + def : Pat<(v8f32 (fceil (loadv8f32 addr:$src))), + (VROUNDPSYm addr:$src, (i32 0xA))>; + def : Pat<(v8f32 (frint (loadv8f32 addr:$src))), + (VROUNDPSYm addr:$src, (i32 0x4))>; + def : Pat<(v8f32 (ftrunc (loadv8f32 addr:$src))), + (VROUNDPSYm addr:$src, (i32 0xB))>; + + def : Pat<(v4f64 (ffloor VR256:$src)), + (VROUNDPDYr VR256:$src, (i32 0x9))>; + def : Pat<(v4f64 (fnearbyint VR256:$src)), + (VROUNDPDYr VR256:$src, (i32 0xC))>; + def : Pat<(v4f64 (fceil VR256:$src)), + (VROUNDPDYr VR256:$src, (i32 0xA))>; + def : Pat<(v4f64 (frint VR256:$src)), + (VROUNDPDYr VR256:$src, (i32 0x4))>; + def : Pat<(v4f64 (ftrunc VR256:$src)), + (VROUNDPDYr VR256:$src, (i32 0xB))>; + + def : Pat<(v4f64 (ffloor (loadv4f64 addr:$src))), + (VROUNDPDYm addr:$src, (i32 0x9))>; + def : Pat<(v4f64 (fnearbyint (loadv4f64 addr:$src))), + (VROUNDPDYm addr:$src, (i32 0xC))>; + def : Pat<(v4f64 (fceil (loadv4f64 addr:$src))), + (VROUNDPDYm addr:$src, (i32 0xA))>; + def : Pat<(v4f64 (frint (loadv4f64 addr:$src))), + (VROUNDPDYm addr:$src, (i32 0x4))>; + def : Pat<(v4f64 (ftrunc (loadv4f64 addr:$src))), + (VROUNDPDYm addr:$src, (i32 0xB))>; +} + +let ExeDomain = SSEPackedSingle in +defm ROUNDPS : sse41_fp_unop_p<0x08, "roundps", f128mem, VR128, v4f32, + memopv4f32, X86VRndScale, SchedWriteFRnd.XMM>; +let ExeDomain = SSEPackedDouble in +defm ROUNDPD : sse41_fp_unop_p<0x09, "roundpd", f128mem, VR128, v2f64, + memopv2f64, X86VRndScale, SchedWriteFRnd.XMM>; + +defm ROUND : sse41_fp_unop_s<0x0A, 0x0B, "round", SchedWriteFRnd.Scl>; + +let Constraints = "$src1 = $dst" in +defm ROUND : sse41_fp_binop_s<0x0A, 0x0B, "round", SchedWriteFRnd.Scl, + v4f32, v2f64, X86RndScales>; + +let Predicates = [UseSSE41] in { + def : Pat<(ffloor FR32:$src), + (ROUNDSSr FR32:$src, (i32 0x9))>; + def : Pat<(f32 (fnearbyint FR32:$src)), + (ROUNDSSr FR32:$src, (i32 0xC))>; + def : Pat<(f32 (fceil FR32:$src)), + (ROUNDSSr FR32:$src, (i32 0xA))>; + def : Pat<(f32 (frint FR32:$src)), + (ROUNDSSr FR32:$src, (i32 0x4))>; + def : Pat<(f32 (ftrunc FR32:$src)), + (ROUNDSSr FR32:$src, (i32 0xB))>; + + def : Pat<(f64 (ffloor FR64:$src)), + (ROUNDSDr FR64:$src, (i32 0x9))>; + def : Pat<(f64 (fnearbyint FR64:$src)), + (ROUNDSDr FR64:$src, (i32 0xC))>; + def : Pat<(f64 (fceil FR64:$src)), + (ROUNDSDr FR64:$src, (i32 0xA))>; + def : Pat<(f64 (frint FR64:$src)), + (ROUNDSDr FR64:$src, (i32 0x4))>; + def : Pat<(f64 (ftrunc FR64:$src)), + (ROUNDSDr FR64:$src, (i32 0xB))>; +} + +let Predicates = [UseSSE41, OptForSize] in { + def : Pat<(ffloor (loadf32 addr:$src)), + (ROUNDSSm addr:$src, (i32 0x9))>; + def : Pat<(f32 (fnearbyint (loadf32 addr:$src))), + (ROUNDSSm addr:$src, (i32 0xC))>; + def : Pat<(f32 (fceil (loadf32 addr:$src))), + (ROUNDSSm addr:$src, (i32 0xA))>; + def : Pat<(f32 (frint (loadf32 addr:$src))), + (ROUNDSSm addr:$src, (i32 0x4))>; + def : Pat<(f32 (ftrunc (loadf32 addr:$src))), + (ROUNDSSm addr:$src, (i32 0xB))>; + + def : Pat<(f64 (ffloor (loadf64 addr:$src))), + (ROUNDSDm addr:$src, (i32 0x9))>; + def : Pat<(f64 (fnearbyint (loadf64 addr:$src))), + (ROUNDSDm addr:$src, (i32 0xC))>; + def : Pat<(f64 (fceil (loadf64 addr:$src))), + (ROUNDSDm addr:$src, (i32 0xA))>; + def : Pat<(f64 (frint (loadf64 addr:$src))), + (ROUNDSDm addr:$src, (i32 0x4))>; + def : Pat<(f64 (ftrunc (loadf64 addr:$src))), + (ROUNDSDm addr:$src, (i32 0xB))>; +} + +let Predicates = [UseSSE41] in { + def : Pat<(v4f32 (ffloor VR128:$src)), + (ROUNDPSr VR128:$src, (i32 0x9))>; + def : Pat<(v4f32 (fnearbyint VR128:$src)), + (ROUNDPSr VR128:$src, (i32 0xC))>; + def : Pat<(v4f32 (fceil VR128:$src)), + (ROUNDPSr VR128:$src, (i32 0xA))>; + def : Pat<(v4f32 (frint VR128:$src)), + (ROUNDPSr VR128:$src, (i32 0x4))>; + def : Pat<(v4f32 (ftrunc VR128:$src)), + (ROUNDPSr VR128:$src, (i32 0xB))>; + + def : Pat<(v4f32 (ffloor (memopv4f32 addr:$src))), + (ROUNDPSm addr:$src, (i32 0x9))>; + def : Pat<(v4f32 (fnearbyint (memopv4f32 addr:$src))), + (ROUNDPSm addr:$src, (i32 0xC))>; + def : Pat<(v4f32 (fceil (memopv4f32 addr:$src))), + (ROUNDPSm addr:$src, (i32 0xA))>; + def : Pat<(v4f32 (frint (memopv4f32 addr:$src))), + (ROUNDPSm addr:$src, (i32 0x4))>; + def : Pat<(v4f32 (ftrunc (memopv4f32 addr:$src))), + (ROUNDPSm addr:$src, (i32 0xB))>; + + def : Pat<(v2f64 (ffloor VR128:$src)), + (ROUNDPDr VR128:$src, (i32 0x9))>; + def : Pat<(v2f64 (fnearbyint VR128:$src)), + (ROUNDPDr VR128:$src, (i32 0xC))>; + def : Pat<(v2f64 (fceil VR128:$src)), + (ROUNDPDr VR128:$src, (i32 0xA))>; + def : Pat<(v2f64 (frint VR128:$src)), + (ROUNDPDr VR128:$src, (i32 0x4))>; + def : Pat<(v2f64 (ftrunc VR128:$src)), + (ROUNDPDr VR128:$src, (i32 0xB))>; + + def : Pat<(v2f64 (ffloor (memopv2f64 addr:$src))), + (ROUNDPDm addr:$src, (i32 0x9))>; + def : Pat<(v2f64 (fnearbyint (memopv2f64 addr:$src))), + (ROUNDPDm addr:$src, (i32 0xC))>; + def : Pat<(v2f64 (fceil (memopv2f64 addr:$src))), + (ROUNDPDm addr:$src, (i32 0xA))>; + def : Pat<(v2f64 (frint (memopv2f64 addr:$src))), + (ROUNDPDm addr:$src, (i32 0x4))>; + def : Pat<(v2f64 (ftrunc (memopv2f64 addr:$src))), + (ROUNDPDm addr:$src, (i32 0xB))>; +} + +defm : scalar_unary_math_imm_patterns; +defm : scalar_unary_math_imm_patterns; +defm : scalar_unary_math_imm_patterns; +defm : scalar_unary_math_imm_patterns; + +//===----------------------------------------------------------------------===// +// SSE4.1 - Packed Bit Test +//===----------------------------------------------------------------------===// + +// ptest instruction we'll lower to this in X86ISelLowering primarily from +// the intel intrinsic that corresponds to this. +let Defs = [EFLAGS], Predicates = [HasAVX] in { +def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), + "vptest\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>, + Sched<[SchedWriteVecTest.XMM]>, VEX, VEX_WIG; +def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2), + "vptest\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>, + Sched<[SchedWriteVecTest.XMM.Folded, ReadAfterLd]>, + VEX, VEX_WIG; + +def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2), + "vptest\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>, + Sched<[SchedWriteVecTest.YMM]>, VEX, VEX_L, VEX_WIG; +def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2), + "vptest\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>, + Sched<[SchedWriteVecTest.YMM.Folded, ReadAfterLd]>, + VEX, VEX_L, VEX_WIG; +} + +let Defs = [EFLAGS] in { +def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), + "ptest\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>, + Sched<[SchedWriteVecTest.XMM]>; +def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2), + "ptest\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>, + Sched<[SchedWriteVecTest.XMM.Folded, ReadAfterLd]>; +} + +// The bit test instructions below are AVX only +multiclass avx_bittest opc, string OpcodeStr, RegisterClass RC, + X86MemOperand x86memop, PatFrag mem_frag, ValueType vt, + X86FoldableSchedWrite sched> { + def rr : SS48I, + Sched<[sched]>, VEX; + def rm : SS48I, + Sched<[sched.Folded, ReadAfterLd]>, VEX; +} + +let Defs = [EFLAGS], Predicates = [HasAVX] in { +let ExeDomain = SSEPackedSingle in { +defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32, + SchedWriteFTest.XMM>; +defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32, + SchedWriteFTest.YMM>, VEX_L; +} +let ExeDomain = SSEPackedDouble in { +defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64, + SchedWriteFTest.XMM>; +defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64, + SchedWriteFTest.YMM>, VEX_L; +} +} + +//===----------------------------------------------------------------------===// +// SSE4.1 - Misc Instructions +//===----------------------------------------------------------------------===// + +let Defs = [EFLAGS], Predicates = [HasPOPCNT] in { + def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "popcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>, + Sched<[WritePOPCNT]>, OpSize16, XS; + def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "popcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (ctpop (loadi16 addr:$src))), + (implicit EFLAGS)]>, + Sched<[WritePOPCNT.Folded]>, OpSize16, XS; + + def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "popcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>, + Sched<[WritePOPCNT]>, OpSize32, XS; + + def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "popcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (ctpop (loadi32 addr:$src))), + (implicit EFLAGS)]>, + Sched<[WritePOPCNT.Folded]>, OpSize32, XS; + + def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "popcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>, + Sched<[WritePOPCNT]>, XS; + def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "popcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (ctpop (loadi64 addr:$src))), + (implicit EFLAGS)]>, + Sched<[WritePOPCNT.Folded]>, XS; +} + +// SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16. +multiclass SS41I_unop_rm_int_v16 opc, string OpcodeStr, + SDNode OpNode, PatFrag ld_frag, + X86FoldableSchedWrite Sched> { + def rr : SS48I, + Sched<[Sched]>; + def rm : SS48I, + Sched<[Sched.Folded]>; +} + +// PHMIN has the same profile as PSAD, thus we use the same scheduling +// model, although the naming is misleading. +let Predicates = [HasAVX] in +defm VPHMINPOSUW : SS41I_unop_rm_int_v16<0x41, "vphminposuw", + X86phminpos, loadv2i64, + WritePHMINPOS>, VEX, VEX_WIG; +defm PHMINPOSUW : SS41I_unop_rm_int_v16<0x41, "phminposuw", + X86phminpos, memopv2i64, + WritePHMINPOS>; + +/// SS48I_binop_rm - Simple SSE41 binary operator. +multiclass SS48I_binop_rm opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT, RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, X86FoldableSchedWrite sched, + bit Is2Addr = 1> { + let isCommutable = 1 in + def rr : SS48I, + Sched<[sched]>; + def rm : SS48I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", smin, v4i32, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", umin, v4i32, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v4i32, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", umax, v4i32, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMULDQ : SS48I_binop_rm<0x28, "vpmuldq", X86pmuldq, v2i64, VR128, + loadv2i64, i128mem, SchedWriteVecIMul.XMM, 0>, + VEX_4V, VEX_WIG; +} +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", smin, v16i8, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", umin, v8i16, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v16i8, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v8i16, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; +} + +let Predicates = [HasAVX2, NoVLX] in { + defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", smin, v8i32, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", umin, v8i32, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v8i32, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", umax, v8i32, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMULDQY : SS48I_binop_rm<0x28, "vpmuldq", X86pmuldq, v4i64, VR256, + loadv4i64, i256mem, SchedWriteVecIMul.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; +} +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { + defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", smin, v32i8, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", umin, v16i16, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v32i8, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v16i16, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; +} + +let Constraints = "$src1 = $dst" in { + defm PMINSB : SS48I_binop_rm<0x38, "pminsb", smin, v16i8, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMINSD : SS48I_binop_rm<0x39, "pminsd", smin, v4i32, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMINUD : SS48I_binop_rm<0x3B, "pminud", umin, v4i32, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", umin, v8i16, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", smax, v16i8, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", smax, v4i32, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", umax, v4i32, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", umax, v8i16, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMULDQ : SS48I_binop_rm<0x28, "pmuldq", X86pmuldq, v2i64, VR128, + memopv2i64, i128mem, SchedWriteVecIMul.XMM, 1>; +} + +let Predicates = [HasAVX, NoVLX] in + defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128, + loadv2i64, i128mem, SchedWritePMULLD.XMM, 0>, + VEX_4V, VEX_WIG; +let Predicates = [HasAVX] in + defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + +let Predicates = [HasAVX2, NoVLX] in + defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256, + loadv4i64, i256mem, SchedWritePMULLD.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; +let Predicates = [HasAVX2] in + defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + +let Constraints = "$src1 = $dst" in { + defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128, + memopv2i64, i128mem, SchedWritePMULLD.XMM, 1>; + defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; +} + +/// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate +multiclass SS41I_binop_rmi_int opc, string OpcodeStr, + Intrinsic IntId, RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, bit Is2Addr, + X86FoldableSchedWrite sched> { + let isCommutable = 1 in + def rri : SS4AIi8, + Sched<[sched]>; + def rmi : SS4AIi8, + Sched<[sched.Folded, ReadAfterLd]>; +} + +/// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate +multiclass SS41I_binop_rmi opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT, RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, bit Is2Addr, + X86FoldableSchedWrite sched> { + let isCommutable = 1 in + def rri : SS4AIi8, + Sched<[sched]>; + def rmi : SS4AIi8, + Sched<[sched.Folded, ReadAfterLd]>; +} + +def BlendCommuteImm2 : SDNodeXFormgetZExtValue() & 0x03; + return getI8Imm(Imm ^ 0x03, SDLoc(N)); +}]>; + +def BlendCommuteImm4 : SDNodeXFormgetZExtValue() & 0x0f; + return getI8Imm(Imm ^ 0x0f, SDLoc(N)); +}]>; + +def BlendCommuteImm8 : SDNodeXFormgetZExtValue() & 0xff; + return getI8Imm(Imm ^ 0xff, SDLoc(N)); +}]>; + +let Predicates = [HasAVX] in { + let isCommutable = 0 in { + defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw, + VR128, loadv2i64, i128mem, 0, + SchedWriteMPSAD.XMM>, VEX_4V, VEX_WIG; + } + + let ExeDomain = SSEPackedSingle in + defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps, + VR128, loadv4f32, f128mem, 0, + SchedWriteDPPS.XMM>, VEX_4V, VEX_WIG; + let ExeDomain = SSEPackedDouble in + defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd, + VR128, loadv2f64, f128mem, 0, + SchedWriteDPPD.XMM>, VEX_4V, VEX_WIG; + let ExeDomain = SSEPackedSingle in + defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256, + VR256, loadv8f32, i256mem, 0, + SchedWriteDPPS.YMM>, VEX_4V, VEX_L, VEX_WIG; +} + +let Predicates = [HasAVX2] in { + let isCommutable = 0 in { + defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw, + VR256, loadv4i64, i256mem, 0, + SchedWriteMPSAD.YMM>, VEX_4V, VEX_L, VEX_WIG; + } +} + +let Constraints = "$src1 = $dst" in { + let isCommutable = 0 in { + defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw, + VR128, memopv2i64, i128mem, 1, + SchedWriteMPSAD.XMM>; + } + + let ExeDomain = SSEPackedSingle in + defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps, + VR128, memopv4f32, f128mem, 1, + SchedWriteDPPS.XMM>; + let ExeDomain = SSEPackedDouble in + defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd, + VR128, memopv2f64, f128mem, 1, + SchedWriteDPPD.XMM>; +} + +/// SS41I_blend_rmi - SSE 4.1 blend with 8-bit immediate +multiclass SS41I_blend_rmi opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT, RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, bit Is2Addr, Domain d, + X86FoldableSchedWrite sched, SDNodeXForm commuteXForm> { +let ExeDomain = d, Constraints = !if(Is2Addr, "$src1 = $dst", "") in { + let isCommutable = 1 in + def rri : SS4AIi8, + Sched<[sched]>; + def rmi : SS4AIi8, + Sched<[sched.Folded, ReadAfterLd]>; +} + + // Pattern to commute if load is in first source. + def : Pat<(OpVT (OpNode (bitconvert (memop_frag addr:$src2)), + RC:$src1, imm:$src3)), + (!cast(NAME#"rmi") RC:$src1, addr:$src2, + (commuteXForm imm:$src3))>; +} + +let Predicates = [HasAVX] in { + defm VBLENDPS : SS41I_blend_rmi<0x0C, "vblendps", X86Blendi, v4f32, + VR128, loadv4f32, f128mem, 0, SSEPackedSingle, + SchedWriteFBlend.XMM, BlendCommuteImm4>, + VEX_4V, VEX_WIG; + defm VBLENDPSY : SS41I_blend_rmi<0x0C, "vblendps", X86Blendi, v8f32, + VR256, loadv8f32, f256mem, 0, SSEPackedSingle, + SchedWriteFBlend.YMM, BlendCommuteImm8>, + VEX_4V, VEX_L, VEX_WIG; + defm VBLENDPD : SS41I_blend_rmi<0x0D, "vblendpd", X86Blendi, v2f64, + VR128, loadv2f64, f128mem, 0, SSEPackedDouble, + SchedWriteFBlend.XMM, BlendCommuteImm2>, + VEX_4V, VEX_WIG; + defm VBLENDPDY : SS41I_blend_rmi<0x0D, "vblendpd", X86Blendi, v4f64, + VR256, loadv4f64, f256mem, 0, SSEPackedDouble, + SchedWriteFBlend.YMM, BlendCommuteImm4>, + VEX_4V, VEX_L, VEX_WIG; + defm VPBLENDW : SS41I_blend_rmi<0x0E, "vpblendw", X86Blendi, v8i16, + VR128, loadv2i64, i128mem, 0, SSEPackedInt, + SchedWriteBlend.XMM, BlendCommuteImm8>, + VEX_4V, VEX_WIG; +} + +let Predicates = [HasAVX2] in { + defm VPBLENDWY : SS41I_blend_rmi<0x0E, "vpblendw", X86Blendi, v16i16, + VR256, loadv4i64, i256mem, 0, SSEPackedInt, + SchedWriteBlend.YMM, BlendCommuteImm8>, + VEX_4V, VEX_L, VEX_WIG; +} + +defm BLENDPS : SS41I_blend_rmi<0x0C, "blendps", X86Blendi, v4f32, + VR128, memopv4f32, f128mem, 1, SSEPackedSingle, + SchedWriteFBlend.XMM, BlendCommuteImm4>; +defm BLENDPD : SS41I_blend_rmi<0x0D, "blendpd", X86Blendi, v2f64, + VR128, memopv2f64, f128mem, 1, SSEPackedDouble, + SchedWriteFBlend.XMM, BlendCommuteImm2>; +defm PBLENDW : SS41I_blend_rmi<0x0E, "pblendw", X86Blendi, v8i16, + VR128, memopv2i64, i128mem, 1, SSEPackedInt, + SchedWriteBlend.XMM, BlendCommuteImm8>; + +// For insertion into the zero index (low half) of a 256-bit vector, it is +// more efficient to generate a blend with immediate instead of an insert*128. +let Predicates = [HasAVX] in { +def : Pat<(insert_subvector (v4f64 VR256:$src1), (v2f64 VR128:$src2), (iPTR 0)), + (VBLENDPDYrri VR256:$src1, + (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0x3)>; +def : Pat<(insert_subvector (v8f32 VR256:$src1), (v4f32 VR128:$src2), (iPTR 0)), + (VBLENDPSYrri VR256:$src1, + (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +} + +/// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators +multiclass SS41I_quaternary_int_avx opc, string OpcodeStr, + RegisterClass RC, X86MemOperand x86memop, + PatFrag mem_frag, Intrinsic IntId, + X86FoldableSchedWrite sched> { + def rr : Ii8Reg, TAPD, VEX_4V, + Sched<[sched]>; + + def rm : Ii8Reg, TAPD, VEX_4V, + Sched<[sched.Folded, ReadAfterLd, + // x86memop:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC::$src3 + ReadAfterLd]>; +} + +let Predicates = [HasAVX] in { +let ExeDomain = SSEPackedDouble in { +defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem, + loadv2f64, int_x86_sse41_blendvpd, + SchedWriteFVarBlend.XMM>; +defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem, + loadv4f64, int_x86_avx_blendv_pd_256, + SchedWriteFVarBlend.YMM>, VEX_L; +} // ExeDomain = SSEPackedDouble +let ExeDomain = SSEPackedSingle in { +defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem, + loadv4f32, int_x86_sse41_blendvps, + SchedWriteFVarBlend.XMM>; +defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem, + loadv8f32, int_x86_avx_blendv_ps_256, + SchedWriteFVarBlend.YMM>, VEX_L; +} // ExeDomain = SSEPackedSingle +defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem, + loadv2i64, int_x86_sse41_pblendvb, + SchedWriteVarBlend.XMM>; +} + +let Predicates = [HasAVX2] in { +defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem, + loadv4i64, int_x86_avx2_pblendvb, + SchedWriteVarBlend.YMM>, VEX_L; +} + +let Predicates = [HasAVX] in { + def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1), + (v16i8 VR128:$src2))), + (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>; + def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1), + (v4i32 VR128:$src2))), + (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>; + def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1), + (v4f32 VR128:$src2))), + (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>; + def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1), + (v2i64 VR128:$src2))), + (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>; + def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1), + (v2f64 VR128:$src2))), + (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>; + def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1), + (v8i32 VR256:$src2))), + (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>; + def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1), + (v8f32 VR256:$src2))), + (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>; + def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1), + (v4i64 VR256:$src2))), + (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>; + def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1), + (v4f64 VR256:$src2))), + (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>; +} + +let Predicates = [HasAVX2] in { + def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1), + (v32i8 VR256:$src2))), + (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>; +} + +// Prefer a movss or movsd over a blendps when optimizing for size. these were +// changed to use blends because blends have better throughput on sandybridge +// and haswell, but movs[s/d] are 1-2 byte shorter instructions. +let Predicates = [HasAVX, OptForSpeed] in { + def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), + (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>; + def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), + (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>; + + def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)), + (VBLENDPSrri VR128:$src1, VR128:$src2, (i8 1))>; + def : Pat<(v4f32 (X86Movss VR128:$src1, (loadv4f32 addr:$src2))), + (VBLENDPSrmi VR128:$src1, addr:$src2, (i8 1))>; + def : Pat<(v4f32 (X86Movss (loadv4f32 addr:$src2), VR128:$src1)), + (VBLENDPSrmi VR128:$src1, addr:$src2, (i8 0xe))>; + + def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)), + (VBLENDPDrri VR128:$src1, VR128:$src2, (i8 1))>; + def : Pat<(v2f64 (X86Movsd VR128:$src1, (loadv2f64 addr:$src2))), + (VBLENDPDrmi VR128:$src1, addr:$src2, (i8 1))>; + def : Pat<(v2f64 (X86Movsd (loadv2f64 addr:$src2), VR128:$src1)), + (VBLENDPDrmi VR128:$src1, addr:$src2, (i8 2))>; + + // Move low f32 and clear high bits. + def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v4f32 (VBLENDPSrri (v4f32 (V_SET0)), + (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), + (i8 1))), sub_xmm)>; + def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v4i32 (VPBLENDWrri (v4i32 (V_SET0)), + (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), + (i8 3))), sub_xmm)>; + + def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v2f64 (VBLENDPDrri (v2f64 (V_SET0)), + (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), + (i8 1))), sub_xmm)>; + def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v2i64 (VPBLENDWrri (v2i64 (V_SET0)), + (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), + (i8 0xf))), sub_xmm)>; +} + +// Prefer a movss or movsd over a blendps when optimizing for size. these were +// changed to use blends because blends have better throughput on sandybridge +// and haswell, but movs[s/d] are 1-2 byte shorter instructions. +let Predicates = [UseSSE41, OptForSpeed] in { + // With SSE41 we can use blends for these patterns. + def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), + (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>; + def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), + (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>; + + def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)), + (BLENDPSrri VR128:$src1, VR128:$src2, (i8 1))>; + def : Pat<(v4f32 (X86Movss VR128:$src1, (memopv4f32 addr:$src2))), + (BLENDPSrmi VR128:$src1, addr:$src2, (i8 1))>; + def : Pat<(v4f32 (X86Movss (memopv4f32 addr:$src2), VR128:$src1)), + (BLENDPSrmi VR128:$src1, addr:$src2, (i8 0xe))>; + + def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)), + (BLENDPDrri VR128:$src1, VR128:$src2, (i8 1))>; + def : Pat<(v2f64 (X86Movsd VR128:$src1, (memopv2f64 addr:$src2))), + (BLENDPDrmi VR128:$src1, addr:$src2, (i8 1))>; + def : Pat<(v2f64 (X86Movsd (memopv2f64 addr:$src2), VR128:$src1)), + (BLENDPDrmi VR128:$src1, addr:$src2, (i8 2))>; +} + + +/// SS41I_ternary_int - SSE 4.1 ternary operator +let Uses = [XMM0], Constraints = "$src1 = $dst" in { + multiclass SS41I_ternary_int opc, string OpcodeStr, PatFrag mem_frag, + X86MemOperand x86memop, Intrinsic IntId, + X86FoldableSchedWrite sched> { + def rr0 : SS48I, + Sched<[sched]>; + + def rm0 : SS48I, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +let ExeDomain = SSEPackedDouble in +defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem, + int_x86_sse41_blendvpd, SchedWriteFVarBlend.XMM>; +let ExeDomain = SSEPackedSingle in +defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem, + int_x86_sse41_blendvps, SchedWriteFVarBlend.XMM>; +defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem, + int_x86_sse41_pblendvb, SchedWriteVarBlend.XMM>; + +// Aliases with the implicit xmm0 argument +// def : InstAlias<"blendvpd\t{$src2, $dst|$dst, $src2}", +// (BLENDVPDrr0 VR128:$dst, VR128:$src2), 0>; +// def : InstAlias<"blendvpd\t{$src2, $dst|$dst, $src2}", +// (BLENDVPDrm0 VR128:$dst, f128mem:$src2), 0>; +// def : InstAlias<"blendvps\t{$src2, $dst|$dst, $src2}", +// (BLENDVPSrr0 VR128:$dst, VR128:$src2), 0>; +// def : InstAlias<"blendvps\t{$src2, $dst|$dst, $src2}", +// (BLENDVPSrm0 VR128:$dst, f128mem:$src2), 0>; +// def : InstAlias<"pblendvb\t{$src2, $dst|$dst, $src2}", +// (PBLENDVBrr0 VR128:$dst, VR128:$src2), 0>; +// def : InstAlias<"pblendvb\t{$src2, $dst|$dst, $src2}", +// (PBLENDVBrm0 VR128:$dst, i128mem:$src2), 0>; + +let Predicates = [UseSSE41] in { + def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1), + (v16i8 VR128:$src2))), + (PBLENDVBrr0 VR128:$src2, VR128:$src1)>; + def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1), + (v4i32 VR128:$src2))), + (BLENDVPSrr0 VR128:$src2, VR128:$src1)>; + def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1), + (v4f32 VR128:$src2))), + (BLENDVPSrr0 VR128:$src2, VR128:$src1)>; + def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1), + (v2i64 VR128:$src2))), + (BLENDVPDrr0 VR128:$src2, VR128:$src1)>; + def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1), + (v2f64 VR128:$src2))), + (BLENDVPDrr0 VR128:$src2, VR128:$src1)>; +} + +let AddedComplexity = 400 in { // Prefer non-temporal versions + +let Predicates = [HasAVX, NoVLX] in +def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "vmovntdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLSNT.XMM.RM]>, VEX, VEX_WIG; +let Predicates = [HasAVX2, NoVLX] in +def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src), + "vmovntdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLSNT.YMM.RM]>, VEX, VEX_L, VEX_WIG; +def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "movntdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLSNT.XMM.RM]>; + +let Predicates = [HasAVX2, NoVLX] in { + def : Pat<(v8f32 (alignednontemporalload addr:$src)), + (VMOVNTDQAYrm addr:$src)>; + def : Pat<(v4f64 (alignednontemporalload addr:$src)), + (VMOVNTDQAYrm addr:$src)>; + def : Pat<(v4i64 (alignednontemporalload addr:$src)), + (VMOVNTDQAYrm addr:$src)>; +} + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4f32 (alignednontemporalload addr:$src)), + (VMOVNTDQArm addr:$src)>; + def : Pat<(v2f64 (alignednontemporalload addr:$src)), + (VMOVNTDQArm addr:$src)>; + def : Pat<(v2i64 (alignednontemporalload addr:$src)), + (VMOVNTDQArm addr:$src)>; +} + +let Predicates = [UseSSE41] in { + def : Pat<(v4f32 (alignednontemporalload addr:$src)), + (MOVNTDQArm addr:$src)>; + def : Pat<(v2f64 (alignednontemporalload addr:$src)), + (MOVNTDQArm addr:$src)>; + def : Pat<(v2i64 (alignednontemporalload addr:$src)), + (MOVNTDQArm addr:$src)>; +} + +} // AddedComplexity + +//===----------------------------------------------------------------------===// +// SSE4.2 - Compare Instructions +//===----------------------------------------------------------------------===// + +/// SS42I_binop_rm - Simple SSE 4.2 binary operator +multiclass SS42I_binop_rm opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT, RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, X86FoldableSchedWrite sched, + bit Is2Addr = 1> { + def rr : SS428I, + Sched<[sched]>; + def rm : SS428I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX] in + defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + +let Predicates = [HasAVX2] in + defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + +let Constraints = "$src1 = $dst" in + defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM>; + +//===----------------------------------------------------------------------===// +// SSE4.2 - String/text Processing Instructions +//===----------------------------------------------------------------------===// + +multiclass pcmpistrm_SS42AI { + def rr : SS42AI<0x62, MRMSrcReg, (outs), + (ins VR128:$src1, VR128:$src2, u8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"), + []>, Sched<[WritePCmpIStrM]>; + let mayLoad = 1 in + def rm :SS42AI<0x62, MRMSrcMem, (outs), + (ins VR128:$src1, i128mem:$src2, u8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"), + []>, Sched<[WritePCmpIStrM.Folded, ReadAfterLd]>; +} + +let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in { + let Predicates = [HasAVX] in + defm VPCMPISTRM : pcmpistrm_SS42AI<"vpcmpistrm">, VEX; + defm PCMPISTRM : pcmpistrm_SS42AI<"pcmpistrm"> ; +} + +multiclass SS42AI_pcmpestrm { + def rr : SS42AI<0x60, MRMSrcReg, (outs), + (ins VR128:$src1, VR128:$src3, u8imm:$src5), + !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"), + []>, Sched<[WritePCmpEStrM]>; + let mayLoad = 1 in + def rm : SS42AI<0x60, MRMSrcMem, (outs), + (ins VR128:$src1, i128mem:$src3, u8imm:$src5), + !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"), + []>, Sched<[WritePCmpEStrM.Folded, ReadAfterLd]>; +} + +let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in { + let Predicates = [HasAVX] in + defm VPCMPESTRM : SS42AI_pcmpestrm<"vpcmpestrm">, VEX; + defm PCMPESTRM : SS42AI_pcmpestrm<"pcmpestrm">; +} + +multiclass SS42AI_pcmpistri { + def rr : SS42AI<0x63, MRMSrcReg, (outs), + (ins VR128:$src1, VR128:$src2, u8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"), + []>, Sched<[WritePCmpIStrI]>; + let mayLoad = 1 in + def rm : SS42AI<0x63, MRMSrcMem, (outs), + (ins VR128:$src1, i128mem:$src2, u8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"), + []>, Sched<[WritePCmpIStrI.Folded, ReadAfterLd]>; +} + +let Defs = [ECX, EFLAGS], hasSideEffects = 0 in { + let Predicates = [HasAVX] in + defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX; + defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">; +} + +multiclass SS42AI_pcmpestri { + def rr : SS42AI<0x61, MRMSrcReg, (outs), + (ins VR128:$src1, VR128:$src3, u8imm:$src5), + !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"), + []>, Sched<[WritePCmpEStrI]>; + let mayLoad = 1 in + def rm : SS42AI<0x61, MRMSrcMem, (outs), + (ins VR128:$src1, i128mem:$src3, u8imm:$src5), + !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"), + []>, Sched<[WritePCmpEStrI.Folded, ReadAfterLd]>; +} + +let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in { + let Predicates = [HasAVX] in + defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX; + defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">; +} + +//===----------------------------------------------------------------------===// +// SSE4.2 - CRC Instructions +//===----------------------------------------------------------------------===// + +// No CRC instructions have AVX equivalents + +// crc intrinsic instruction +// This set of instructions are only rm, the only difference is the size +// of r and m. +class SS42I_crc32r opc, string asm, RegisterClass RCOut, + RegisterClass RCIn, SDPatternOperator Int> : + SS42FI, + Sched<[WriteCRC32]>; + +class SS42I_crc32m opc, string asm, RegisterClass RCOut, + X86MemOperand x86memop, SDPatternOperator Int> : + SS42FI, + Sched<[WriteCRC32.Folded, ReadAfterLd]>; + +let Constraints = "$src1 = $dst" in { + def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem, + int_x86_sse42_crc32_32_8>; + def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8, + int_x86_sse42_crc32_32_8>; + def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem, + int_x86_sse42_crc32_32_16>, OpSize16; + def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16, + int_x86_sse42_crc32_32_16>, OpSize16; + def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem, + int_x86_sse42_crc32_32_32>, OpSize32; + def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32, + int_x86_sse42_crc32_32_32>, OpSize32; + def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem, + int_x86_sse42_crc32_64_64>, REX_W; + def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64, + int_x86_sse42_crc32_64_64>, REX_W; + let hasSideEffects = 0 in { + let mayLoad = 1 in + def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem, + null_frag>, REX_W; + def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8, + null_frag>, REX_W; + } +} + +//===----------------------------------------------------------------------===// +// SHA-NI Instructions +//===----------------------------------------------------------------------===// + +// FIXME: Is there a better scheduler class for SHA than WriteVecIMul? +multiclass SHAI_binop Opc, string OpcodeStr, Intrinsic IntId, + X86FoldableSchedWrite sched, bit UsesXMM0 = 0> { + def rr : I, + T8, Sched<[sched]>; + + def rm : I, T8, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Constraints = "$src1 = $dst", Predicates = [HasSHA] in { + def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2, u8imm:$src3), + "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR128:$dst, + (int_x86_sha1rnds4 VR128:$src1, VR128:$src2, + (i8 imm:$src3)))]>, TA, + Sched<[SchedWriteVecIMul.XMM]>; + def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, i128mem:$src2, u8imm:$src3), + "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR128:$dst, + (int_x86_sha1rnds4 VR128:$src1, + (bc_v4i32 (memopv2i64 addr:$src2)), + (i8 imm:$src3)))]>, TA, + Sched<[SchedWriteVecIMul.XMM.Folded, ReadAfterLd]>; + + defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte, + SchedWriteVecIMul.XMM>; + defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1, + SchedWriteVecIMul.XMM>; + defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2, + SchedWriteVecIMul.XMM>; + + let Uses=[XMM0] in + defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, + SchedWriteVecIMul.XMM, 1>; + + defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1, + SchedWriteVecIMul.XMM>; + defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2, + SchedWriteVecIMul.XMM>; +} + +// Aliases with explicit %xmm0 +// def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", +// (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>; +// def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", +// (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>; + +//===----------------------------------------------------------------------===// +// AES-NI Instructions +//===----------------------------------------------------------------------===// + +multiclass AESI_binop_rm_int opc, string OpcodeStr, + Intrinsic IntId, PatFrag ld_frag, + bit Is2Addr = 0, RegisterClass RC = VR128, + X86MemOperand MemOp = i128mem> { + let AsmString = OpcodeStr## + !if(Is2Addr, "\t{$src2, $dst|$dst, $src2}", + "\t{$src2, $src1, $dst|$dst, $src1, $src2}") in { + def rr : AES8I, + Sched<[WriteAESDecEnc]>; + def rm : AES8I, + Sched<[WriteAESDecEnc.Folded, ReadAfterLd]>; + } +} + +// Perform One Round of an AES Encryption/Decryption Flow +let Predicates = [HasAVX, NoVLX_Or_NoVAES, HasAES] in { + defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc", + int_x86_aesni_aesenc, loadv2i64>, VEX_4V, VEX_WIG; + defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast", + int_x86_aesni_aesenclast, loadv2i64>, VEX_4V, VEX_WIG; + defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec", + int_x86_aesni_aesdec, loadv2i64>, VEX_4V, VEX_WIG; + defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast", + int_x86_aesni_aesdeclast, loadv2i64>, VEX_4V, VEX_WIG; +} + +let Predicates = [NoVLX, HasVAES] in { + defm VAESENCY : AESI_binop_rm_int<0xDC, "vaesenc", + int_x86_aesni_aesenc_256, loadv4i64, 0, VR256, + i256mem>, VEX_4V, VEX_L, VEX_WIG; + defm VAESENCLASTY : AESI_binop_rm_int<0xDD, "vaesenclast", + int_x86_aesni_aesenclast_256, loadv4i64, 0, VR256, + i256mem>, VEX_4V, VEX_L, VEX_WIG; + defm VAESDECY : AESI_binop_rm_int<0xDE, "vaesdec", + int_x86_aesni_aesdec_256, loadv4i64, 0, VR256, + i256mem>, VEX_4V, VEX_L, VEX_WIG; + defm VAESDECLASTY : AESI_binop_rm_int<0xDF, "vaesdeclast", + int_x86_aesni_aesdeclast_256, loadv4i64, 0, VR256, + i256mem>, VEX_4V, VEX_L, VEX_WIG; +} + +let Constraints = "$src1 = $dst" in { + defm AESENC : AESI_binop_rm_int<0xDC, "aesenc", + int_x86_aesni_aesenc, memopv2i64, 1>; + defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast", + int_x86_aesni_aesenclast, memopv2i64, 1>; + defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec", + int_x86_aesni_aesdec, memopv2i64, 1>; + defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast", + int_x86_aesni_aesdeclast, memopv2i64, 1>; +} + +// Perform the AES InvMixColumn Transformation +let Predicates = [HasAVX, HasAES] in { + def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1), + "vaesimc\t{$src1, $dst|$dst, $src1}", + [(set VR128:$dst, + (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>, + VEX, VEX_WIG; + def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst), + (ins i128mem:$src1), + "vaesimc\t{$src1, $dst|$dst, $src1}", + [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>, + Sched<[WriteAESIMC.Folded]>, VEX, VEX_WIG; +} +def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1), + "aesimc\t{$src1, $dst|$dst, $src1}", + [(set VR128:$dst, + (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>; +def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst), + (ins i128mem:$src1), + "aesimc\t{$src1, $dst|$dst, $src1}", + [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>, + Sched<[WriteAESIMC.Folded]>; + +// AES Round Key Generation Assist +let Predicates = [HasAVX, HasAES] in { + def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, u8imm:$src2), + "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>, + Sched<[WriteAESKeyGen]>, VEX, VEX_WIG; + def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst), + (ins i128mem:$src1, u8imm:$src2), + "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>, + Sched<[WriteAESKeyGen.Folded]>, VEX, VEX_WIG; +} +def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, u8imm:$src2), + "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>, + Sched<[WriteAESKeyGen]>; +def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst), + (ins i128mem:$src1, u8imm:$src2), + "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>, + Sched<[WriteAESKeyGen.Folded]>; + +//===----------------------------------------------------------------------===// +// PCLMUL Instructions +//===----------------------------------------------------------------------===// + +// Immediate transform to help with commuting. +def PCLMULCommuteImm : SDNodeXFormgetZExtValue(); + return getI8Imm((uint8_t)((Imm >> 4) | (Imm << 4)), SDLoc(N)); +}]>; + +// SSE carry-less Multiplication instructions +let Predicates = [NoAVX, HasPCLMUL] in { + let Constraints = "$src1 = $dst" in { + let isCommutable = 1 in + def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2, u8imm:$src3), + "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR128:$dst, + (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>, + Sched<[WriteCLMul]>; + + def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, i128mem:$src2, u8imm:$src3), + "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR128:$dst, + (int_x86_pclmulqdq VR128:$src1, (memopv2i64 addr:$src2), + imm:$src3))]>, + Sched<[WriteCLMul.Folded, ReadAfterLd]>; + } // Constraints = "$src1 = $dst" + + def : Pat<(int_x86_pclmulqdq (memopv2i64 addr:$src2), VR128:$src1, + (i8 imm:$src3)), + (PCLMULQDQrm VR128:$src1, addr:$src2, + (PCLMULCommuteImm imm:$src3))>; +} // Predicates = [NoAVX, HasPCLMUL] + +// SSE aliases +foreach HI = ["hq","lq"] in +foreach LO = ["hq","lq"] in { + // def : InstAlias<"pclmul" # HI # LO # "dq\t{$src, $dst|$dst, $src}", + // (PCLMULQDQrr VR128:$dst, VR128:$src, + // !add(!shl(!eq(LO,"hq"),4),!eq(HI,"hq"))), 0>; + // def : InstAlias<"pclmul" # HI # LO # "dq\t{$src, $dst|$dst, $src}", + // (PCLMULQDQrm VR128:$dst, i128mem:$src, + // !add(!shl(!eq(LO,"hq"),4),!eq(HI,"hq"))), 0>; +} + +// AVX carry-less Multiplication instructions +multiclass vpclmulqdq { + let isCommutable = 1 in + def rr : PCLMULIi8<0x44, MRMSrcReg, (outs RC:$dst), + (ins RC:$src1, RC:$src2, u8imm:$src3), + "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set RC:$dst, + (IntId RC:$src1, RC:$src2, imm:$src3))]>, + Sched<[WriteCLMul]>; + + def rm : PCLMULIi8<0x44, MRMSrcMem, (outs RC:$dst), + (ins RC:$src1, MemOp:$src2, u8imm:$src3), + "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set RC:$dst, + (IntId RC:$src1, (LdFrag addr:$src2), imm:$src3))]>, + Sched<[WriteCLMul.Folded, ReadAfterLd]>; + + // We can commute a load in the first operand by swapping the sources and + // rotating the immediate. + def : Pat<(IntId (LdFrag addr:$src2), RC:$src1, (i8 imm:$src3)), + (!cast(NAME#"rm") RC:$src1, addr:$src2, + (PCLMULCommuteImm imm:$src3))>; +} + +let Predicates = [HasAVX, NoVLX_Or_NoVPCLMULQDQ, HasPCLMUL] in +defm VPCLMULQDQ : vpclmulqdq, VEX_4V, VEX_WIG; + +let Predicates = [NoVLX, HasVPCLMULQDQ] in +defm VPCLMULQDQY : vpclmulqdq, VEX_4V, VEX_L, VEX_WIG; + +/* +multiclass vpclmulqdq_aliases_impl { + // def : InstAlias<"vpclmul"##Hi##Lo##"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}", + // (!cast(InstStr # "rr") RC:$dst, RC:$src1, RC:$src2, + // !add(!shl(!eq(Lo,"hq"),4),!eq(Hi,"hq"))), 0>; + // def : InstAlias<"vpclmul"##Hi##Lo##"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}", + // (!cast(InstStr # "rm") RC:$dst, RC:$src1, MemOp:$src2, + // !add(!shl(!eq(Lo,"hq"),4),!eq(Hi,"hq"))), 0>; +} + +multiclass vpclmulqdq_aliases { + defm : vpclmulqdq_aliases_impl; + defm : vpclmulqdq_aliases_impl; + defm : vpclmulqdq_aliases_impl; + defm : vpclmulqdq_aliases_impl; +} + +// AVX aliases +defm : vpclmulqdq_aliases<"VPCLMULQDQ", VR128, i128mem>; +defm : vpclmulqdq_aliases<"VPCLMULQDQY", VR256, i256mem>; +*/ + +//===----------------------------------------------------------------------===// +// SSE4A Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasSSE4A] in { + +let ExeDomain = SSEPackedInt in { +let Constraints = "$src = $dst" in { +def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst), + (ins VR128:$src, u8imm:$len, u8imm:$idx), + "extrq\t{$idx, $len, $src|$src, $len, $idx}", + [(set VR128:$dst, (X86extrqi VR128:$src, imm:$len, + imm:$idx))]>, + PD, Sched<[SchedWriteVecALU.XMM]>; +def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src, VR128:$mask), + "extrq\t{$mask, $src|$src, $mask}", + [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src, + VR128:$mask))]>, + PD, Sched<[SchedWriteVecALU.XMM]>; + +def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx), + "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}", + [(set VR128:$dst, (X86insertqi VR128:$src, VR128:$src2, + imm:$len, imm:$idx))]>, + XD, Sched<[SchedWriteVecALU.XMM]>; +def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src, VR128:$mask), + "insertq\t{$mask, $src|$src, $mask}", + [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src, + VR128:$mask))]>, + XD, Sched<[SchedWriteVecALU.XMM]>; +} +} // ExeDomain = SSEPackedInt + +// Non-temporal (unaligned) scalar stores. +let AddedComplexity = 400 in { // Prefer non-temporal versions +let hasSideEffects = 0, mayStore = 1, SchedRW = [SchedWriteFMoveLSNT.Scl.MR] in { +def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src), + "movntss\t{$src, $dst|$dst, $src}", []>, XS; + +def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movntsd\t{$src, $dst|$dst, $src}", []>, XD; +} // SchedRW + +def : Pat<(nontemporalstore FR32:$src, addr:$dst), + (MOVNTSS addr:$dst, (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)))>; + +def : Pat<(nontemporalstore FR64:$src, addr:$dst), + (MOVNTSD addr:$dst, (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))>; + +} // AddedComplexity +} // HasSSE4A + +//===----------------------------------------------------------------------===// +// AVX Instructions +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// VBROADCAST - Load from memory and broadcast to all elements of the +// destination operand +// +class avx_broadcast_rm opc, string OpcodeStr, RegisterClass RC, + X86MemOperand x86memop, ValueType VT, + PatFrag ld_frag, SchedWrite Sched> : + AVX8I, + Sched<[Sched]>, VEX; + +// AVX2 adds register forms +class avx2_broadcast_rr opc, string OpcodeStr, RegisterClass RC, + ValueType ResVT, ValueType OpVT, SchedWrite Sched> : + AVX28I, + Sched<[Sched]>, VEX; + +let ExeDomain = SSEPackedSingle, Predicates = [HasAVX, NoVLX] in { + def VBROADCASTSSrm : avx_broadcast_rm<0x18, "vbroadcastss", VR128, + f32mem, v4f32, loadf32, + SchedWriteFShuffle.XMM.Folded>; + def VBROADCASTSSYrm : avx_broadcast_rm<0x18, "vbroadcastss", VR256, + f32mem, v8f32, loadf32, + SchedWriteFShuffle.XMM.Folded>, VEX_L; +} +let ExeDomain = SSEPackedDouble, Predicates = [HasAVX, NoVLX] in +def VBROADCASTSDYrm : avx_broadcast_rm<0x19, "vbroadcastsd", VR256, f64mem, + v4f64, loadf64, + SchedWriteFShuffle.XMM.Folded>, VEX_L; + +let ExeDomain = SSEPackedSingle, Predicates = [HasAVX2, NoVLX] in { + def VBROADCASTSSrr : avx2_broadcast_rr<0x18, "vbroadcastss", VR128, + v4f32, v4f32, SchedWriteFShuffle.XMM>; + def VBROADCASTSSYrr : avx2_broadcast_rr<0x18, "vbroadcastss", VR256, + v8f32, v4f32, WriteFShuffle256>, VEX_L; +} +let ExeDomain = SSEPackedDouble, Predicates = [HasAVX2, NoVLX] in +def VBROADCASTSDYrr : avx2_broadcast_rr<0x19, "vbroadcastsd", VR256, + v4f64, v2f64, WriteFShuffle256>, VEX_L; + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4f32 (X86VBroadcast (v4f32 (scalar_to_vector (loadf32 addr:$src))))), + (VBROADCASTSSrm addr:$src)>; + def : Pat<(v8f32 (X86VBroadcast (v4f32 (scalar_to_vector (loadf32 addr:$src))))), + (VBROADCASTSSYrm addr:$src)>; + def : Pat<(v4f64 (X86VBroadcast (v2f64 (scalar_to_vector (loadf64 addr:$src))))), + (VBROADCASTSDYrm addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// VBROADCAST*128 - Load from memory and broadcast 128-bit vector to both +// halves of a 256-bit vector. +// +let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX2] in +def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst), + (ins i128mem:$src), + "vbroadcasti128\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteShuffleLd]>, VEX, VEX_L; + +let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX], + ExeDomain = SSEPackedSingle in +def VBROADCASTF128 : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst), + (ins f128mem:$src), + "vbroadcastf128\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteFShuffle.XMM.Folded]>, VEX, VEX_L; + +let Predicates = [HasAVX2, NoVLX] in { +def : Pat<(v4i64 (X86SubVBroadcast (loadv2i64 addr:$src))), + (VBROADCASTI128 addr:$src)>; +def : Pat<(v8i32 (X86SubVBroadcast (bc_v4i32 (loadv2i64 addr:$src)))), + (VBROADCASTI128 addr:$src)>; +def : Pat<(v16i16 (X86SubVBroadcast (bc_v8i16 (loadv2i64 addr:$src)))), + (VBROADCASTI128 addr:$src)>; +def : Pat<(v32i8 (X86SubVBroadcast (bc_v16i8 (loadv2i64 addr:$src)))), + (VBROADCASTI128 addr:$src)>; +} + +let Predicates = [HasAVX, NoVLX] in { +def : Pat<(v4f64 (X86SubVBroadcast (loadv2f64 addr:$src))), + (VBROADCASTF128 addr:$src)>; +def : Pat<(v8f32 (X86SubVBroadcast (loadv4f32 addr:$src))), + (VBROADCASTF128 addr:$src)>; +} + +let Predicates = [HasAVX1Only] in { +def : Pat<(v4i64 (X86SubVBroadcast (loadv2i64 addr:$src))), + (VBROADCASTF128 addr:$src)>; +def : Pat<(v8i32 (X86SubVBroadcast (bc_v4i32 (loadv2i64 addr:$src)))), + (VBROADCASTF128 addr:$src)>; +def : Pat<(v16i16 (X86SubVBroadcast (bc_v8i16 (loadv2i64 addr:$src)))), + (VBROADCASTF128 addr:$src)>; +def : Pat<(v32i8 (X86SubVBroadcast (bc_v16i8 (loadv2i64 addr:$src)))), + (VBROADCASTF128 addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// VINSERTF128 - Insert packed floating-point values +// +let hasSideEffects = 0, ExeDomain = SSEPackedSingle in { +def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst), + (ins VR256:$src1, VR128:$src2, u8imm:$src3), + "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + []>, Sched<[WriteFShuffle256]>, VEX_4V, VEX_L; +let mayLoad = 1 in +def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst), + (ins VR256:$src1, f128mem:$src2, u8imm:$src3), + "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + []>, Sched<[WriteFShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L; +} + +// To create a 256-bit all ones value, we should produce VCMPTRUEPS +// with YMM register containing zero. +// FIXME: Avoid producing vxorps to clear the fake inputs. +let Predicates = [HasAVX1Only] in { +def : Pat<(v8i32 immAllOnesV), (VCMPPSYrri (AVX_SET0), (AVX_SET0), 0xf)>; +} + +multiclass vinsert_lowering { + def : Pat<(vinsert128_insert:$ins (To VR256:$src1), (From VR128:$src2), + (iPTR imm)), + (!cast(InstrStr#rr) VR256:$src1, VR128:$src2, + (INSERT_get_vinsert128_imm VR256:$ins))>; + def : Pat<(vinsert128_insert:$ins (To VR256:$src1), + (From (bitconvert (memop_frag addr:$src2))), + (iPTR imm)), + (!cast(InstrStr#rm) VR256:$src1, addr:$src2, + (INSERT_get_vinsert128_imm VR256:$ins))>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm : vinsert_lowering<"VINSERTF128", v4f32, v8f32, loadv4f32>; + defm : vinsert_lowering<"VINSERTF128", v2f64, v4f64, loadv2f64>; +} + +let Predicates = [HasAVX1Only] in { + defm : vinsert_lowering<"VINSERTF128", v2i64, v4i64, loadv2i64>; + defm : vinsert_lowering<"VINSERTF128", v4i32, v8i32, loadv2i64>; + defm : vinsert_lowering<"VINSERTF128", v8i16, v16i16, loadv2i64>; + defm : vinsert_lowering<"VINSERTF128", v16i8, v32i8, loadv2i64>; +} + +//===----------------------------------------------------------------------===// +// VEXTRACTF128 - Extract packed floating-point values +// +let hasSideEffects = 0, ExeDomain = SSEPackedSingle in { +def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst), + (ins VR256:$src1, u8imm:$src2), + "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, Sched<[WriteFShuffle256]>, VEX, VEX_L; +let mayStore = 1 in +def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs), + (ins f128mem:$dst, VR256:$src1, u8imm:$src2), + "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, Sched<[WriteFStoreX]>, VEX, VEX_L; +} + +multiclass vextract_lowering { + def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)), + (To (!cast(InstrStr#rr) + (From VR256:$src1), + (EXTRACT_get_vextract128_imm VR128:$ext)))>; + def : Pat<(store (To (vextract128_extract:$ext (From VR256:$src1), + (iPTR imm))), addr:$dst), + (!cast(InstrStr#mr) addr:$dst, VR256:$src1, + (EXTRACT_get_vextract128_imm VR128:$ext))>; +} + +// AVX1 patterns +let Predicates = [HasAVX, NoVLX] in { + defm : vextract_lowering<"VEXTRACTF128", v8f32, v4f32>; + defm : vextract_lowering<"VEXTRACTF128", v4f64, v2f64>; +} + +let Predicates = [HasAVX1Only] in { + defm : vextract_lowering<"VEXTRACTF128", v4i64, v2i64>; + defm : vextract_lowering<"VEXTRACTF128", v8i32, v4i32>; + defm : vextract_lowering<"VEXTRACTF128", v16i16, v8i16>; + defm : vextract_lowering<"VEXTRACTF128", v32i8, v16i8>; +} + +//===----------------------------------------------------------------------===// +// VMASKMOV - Conditional SIMD Packed Loads and Stores +// +multiclass avx_movmask_rm opc_rm, bits<8> opc_mr, string OpcodeStr, + Intrinsic IntLd, Intrinsic IntLd256, + Intrinsic IntSt, Intrinsic IntSt256> { + def rm : AVX8I, + VEX_4V, Sched<[WriteFMaskedLoad]>; + def Yrm : AVX8I, + VEX_4V, VEX_L, Sched<[WriteFMaskedLoadY]>; + def mr : AVX8I, + VEX_4V, Sched<[WriteFMaskedStore]>; + def Ymr : AVX8I, + VEX_4V, VEX_L, Sched<[WriteFMaskedStoreY]>; +} + +let ExeDomain = SSEPackedSingle in +defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps", + int_x86_avx_maskload_ps, + int_x86_avx_maskload_ps_256, + int_x86_avx_maskstore_ps, + int_x86_avx_maskstore_ps_256>; +let ExeDomain = SSEPackedDouble in +defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd", + int_x86_avx_maskload_pd, + int_x86_avx_maskload_pd_256, + int_x86_avx_maskstore_pd, + int_x86_avx_maskstore_pd_256>; + +//===----------------------------------------------------------------------===// +// VPERMIL - Permute Single and Double Floating-Point Values +// + +multiclass avx_permil opc_rm, bits<8> opc_rmi, string OpcodeStr, + RegisterClass RC, X86MemOperand x86memop_f, + X86MemOperand x86memop_i, PatFrag i_frag, + ValueType f_vt, ValueType i_vt, + X86FoldableSchedWrite sched, + X86FoldableSchedWrite varsched> { + let Predicates = [HasAVX, NoVLX] in { + def rr : AVX8I, VEX_4V, + Sched<[varsched]>; + def rm : AVX8I, VEX_4V, + Sched<[varsched.Folded, ReadAfterLd]>; + + def ri : AVXAIi8, VEX, + Sched<[sched]>; + def mi : AVXAIi8, VEX, + Sched<[sched.Folded]>; + }// Predicates = [HasAVX, NoVLX] +} + +let ExeDomain = SSEPackedSingle in { + defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem, + loadv2i64, v4f32, v4i32, SchedWriteFShuffle.XMM, + SchedWriteFVarShuffle.XMM>; + defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem, + loadv4i64, v8f32, v8i32, SchedWriteFShuffle.YMM, + SchedWriteFVarShuffle.YMM>, VEX_L; +} +let ExeDomain = SSEPackedDouble in { + defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem, + loadv2i64, v2f64, v2i64, SchedWriteFShuffle.XMM, + SchedWriteFVarShuffle.XMM>; + defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem, + loadv4i64, v4f64, v4i64, SchedWriteFShuffle.YMM, + SchedWriteFVarShuffle.YMM>, VEX_L; +} + +//===----------------------------------------------------------------------===// +// VPERM2F128 - Permute Floating-Point Values in 128-bit chunks +// + +let ExeDomain = SSEPackedSingle in { +let isCommutable = 1 in +def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst), + (ins VR256:$src1, VR256:$src2, u8imm:$src3), + "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set VR256:$dst, (v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, + (i8 imm:$src3))))]>, VEX_4V, VEX_L, + Sched<[WriteFShuffle256]>; +def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst), + (ins VR256:$src1, f256mem:$src2, u8imm:$src3), + "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4f64 addr:$src2), + (i8 imm:$src3)))]>, VEX_4V, VEX_L, + Sched<[WriteFShuffle256Ld, ReadAfterLd]>; +} + +// Immediate transform to help with commuting. +def Perm2XCommuteImm : SDNodeXFormgetZExtValue() ^ 0x22, SDLoc(N)); +}]>; + +let Predicates = [HasAVX] in { +// Pattern with load in other operand. +def : Pat<(v4f64 (X86VPerm2x128 (loadv4f64 addr:$src2), + VR256:$src1, (i8 imm:$imm))), + (VPERM2F128rm VR256:$src1, addr:$src2, (Perm2XCommuteImm imm:$imm))>; +} + +let Predicates = [HasAVX1Only] in { +def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))), + (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>; +def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, + (loadv4i64 addr:$src2), (i8 imm:$imm))), + (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>; +// Pattern with load in other operand. +def : Pat<(v4i64 (X86VPerm2x128 (loadv4i64 addr:$src2), + VR256:$src1, (i8 imm:$imm))), + (VPERM2F128rm VR256:$src1, addr:$src2, (Perm2XCommuteImm imm:$imm))>; +} + +//===----------------------------------------------------------------------===// +// VZERO - Zero YMM registers +// Note: These instruction do not affect the YMM16-YMM31. +// + +let SchedRW = [WriteSystem] in { +let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, + YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in { + // Zero All YMM registers + def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", + [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, + Requires<[HasAVX]>, VEX_WIG; + + // Zero Upper bits of YMM registers + def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", + [(int_x86_avx_vzeroupper)]>, PS, VEX, + Requires<[HasAVX]>, VEX_WIG; +} // Defs +} // SchedRW + +//===----------------------------------------------------------------------===// +// Half precision conversion instructions +// + +multiclass f16c_ph2ps { + def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src), + "vcvtph2ps\t{$src, $dst|$dst, $src}", + [(set RC:$dst, (X86cvtph2ps VR128:$src))]>, + T8PD, VEX, Sched<[sched]>; + let hasSideEffects = 0, mayLoad = 1 in + def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), + "vcvtph2ps\t{$src, $dst|$dst, $src}", + [(set RC:$dst, (X86cvtph2ps (bc_v8i16 + (loadv2i64 addr:$src))))]>, + T8PD, VEX, Sched<[sched.Folded]>; +} + +multiclass f16c_ps2ph { + def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst), + (ins RC:$src1, i32u8imm:$src2), + "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, (X86cvtps2ph RC:$src1, imm:$src2))]>, + TAPD, VEX, Sched<[RR]>; + let hasSideEffects = 0, mayStore = 1 in + def mr : Ii8<0x1D, MRMDestMem, (outs), + (ins x86memop:$dst, RC:$src1, i32u8imm:$src2), + "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + TAPD, VEX, Sched<[MR]>; +} + +let Predicates = [HasF16C, NoVLX] in { + defm VCVTPH2PS : f16c_ph2ps; + defm VCVTPH2PSY : f16c_ph2ps, VEX_L; + defm VCVTPS2PH : f16c_ps2ph; + defm VCVTPS2PHY : f16c_ps2ph, VEX_L; + + // Pattern match vcvtph2ps of a scalar i64 load. + def : Pat<(v4f32 (X86cvtph2ps (v8i16 (vzmovl_v2i64 addr:$src)))), + (VCVTPH2PSrm addr:$src)>; + def : Pat<(v4f32 (X86cvtph2ps (v8i16 (vzload_v2i64 addr:$src)))), + (VCVTPH2PSrm addr:$src)>; + def : Pat<(v4f32 (X86cvtph2ps (v8i16 (bitconvert + (v2i64 (scalar_to_vector (loadi64 addr:$src))))))), + (VCVTPH2PSrm addr:$src)>; + + def : Pat<(store (f64 (extractelt + (bc_v2f64 (v8i16 (X86cvtps2ph VR128:$src1, i32:$src2))), + (iPTR 0))), addr:$dst), + (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>; + def : Pat<(store (i64 (extractelt + (bc_v2i64 (v8i16 (X86cvtps2ph VR128:$src1, i32:$src2))), + (iPTR 0))), addr:$dst), + (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>; + def : Pat<(store (v8i16 (X86cvtps2ph VR256:$src1, i32:$src2)), addr:$dst), + (VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>; +} + +// Patterns for matching conversions from float to half-float and vice versa. +let Predicates = [HasF16C, NoVLX] in { + // Use MXCSR.RC for rounding instead of explicitly specifying the default + // rounding mode (Nearest-Even, encoded as 0). Both are equivalent in the + // configurations we support (the default). However, falling back to MXCSR is + // more consistent with other instructions, which are always controlled by it. + // It's encoded as 0b100. + def : Pat<(fp_to_f16 FR32:$src), + (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (v8i16 (VCVTPS2PHrr + (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 4))), sub_16bit))>; + + def : Pat<(f16_to_fp GR16:$src), + (f32 (COPY_TO_REGCLASS (v4f32 (VCVTPH2PSrr + (v4i32 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)))), FR32)) >; + + def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))), + (f32 (COPY_TO_REGCLASS (v4f32 (VCVTPH2PSrr + (v8i16 (VCVTPS2PHrr (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 4)))), FR32)) >; +} + +//===----------------------------------------------------------------------===// +// AVX2 Instructions +//===----------------------------------------------------------------------===// + +/// AVX2_blend_rmi - AVX2 blend with 8-bit immediate +multiclass AVX2_blend_rmi opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT, X86FoldableSchedWrite sched, + RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, SDNodeXForm commuteXForm> { + let isCommutable = 1 in + def rri : AVX2AIi8, + Sched<[sched]>, VEX_4V; + def rmi : AVX2AIi8, + Sched<[sched.Folded, ReadAfterLd]>, VEX_4V; + + // Pattern to commute if load is in first source. + def : Pat<(OpVT (OpNode (bitconvert (memop_frag addr:$src2)), + RC:$src1, imm:$src3)), + (!cast(NAME#"rmi") RC:$src1, addr:$src2, + (commuteXForm imm:$src3))>; +} + +defm VPBLENDD : AVX2_blend_rmi<0x02, "vpblendd", X86Blendi, v4i32, + SchedWriteBlend.XMM, VR128, loadv2i64, i128mem, + BlendCommuteImm4>; +defm VPBLENDDY : AVX2_blend_rmi<0x02, "vpblendd", X86Blendi, v8i32, + SchedWriteBlend.YMM, VR256, loadv4i64, i256mem, + BlendCommuteImm8>, VEX_L; + +// For insertion into the zero index (low half) of a 256-bit vector, it is +// more efficient to generate a blend with immediate instead of an insert*128. +let Predicates = [HasAVX2] in { +def : Pat<(insert_subvector (v8i32 VR256:$src1), (v4i32 VR128:$src2), (iPTR 0)), + (VPBLENDDYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +def : Pat<(insert_subvector (v4i64 VR256:$src1), (v2i64 VR128:$src2), (iPTR 0)), + (VPBLENDDYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +def : Pat<(insert_subvector (v16i16 VR256:$src1), (v8i16 VR128:$src2), (iPTR 0)), + (VPBLENDDYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +def : Pat<(insert_subvector (v32i8 VR256:$src1), (v16i8 VR128:$src2), (iPTR 0)), + (VPBLENDDYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +} + +let Predicates = [HasAVX1Only] in { +def : Pat<(insert_subvector (v8i32 VR256:$src1), (v4i32 VR128:$src2), (iPTR 0)), + (VBLENDPSYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +def : Pat<(insert_subvector (v4i64 VR256:$src1), (v2i64 VR128:$src2), (iPTR 0)), + (VBLENDPSYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +def : Pat<(insert_subvector (v16i16 VR256:$src1), (v8i16 VR128:$src2), (iPTR 0)), + (VBLENDPSYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +def : Pat<(insert_subvector (v32i8 VR256:$src1), (v16i8 VR128:$src2), (iPTR 0)), + (VBLENDPSYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +} + +//===----------------------------------------------------------------------===// +// VPBROADCAST - Load from memory and broadcast to all elements of the +// destination operand +// +multiclass avx2_broadcast opc, string OpcodeStr, + X86MemOperand x86memop, PatFrag ld_frag, + ValueType OpVT128, ValueType OpVT256, Predicate prd> { + let Predicates = [HasAVX2, prd] in { + def rr : AVX28I, + Sched<[SchedWriteShuffle.XMM]>, VEX; + def rm : AVX28I, + Sched<[SchedWriteShuffle.XMM.Folded]>, VEX; + def Yrr : AVX28I, + Sched<[WriteShuffle256]>, VEX, VEX_L; + def Yrm : AVX28I, + Sched<[SchedWriteShuffle.XMM.Folded]>, VEX, VEX_L; + + // Provide aliases for broadcast from the same register class that + // automatically does the extract. + def : Pat<(OpVT256 (X86VBroadcast (OpVT256 VR256:$src))), + (!cast(NAME#"Yrr") + (OpVT128 (EXTRACT_SUBREG (OpVT256 VR256:$src),sub_xmm)))>; + } +} + +defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8, + v16i8, v32i8, NoVLX_Or_NoBWI>; +defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16, + v8i16, v16i16, NoVLX_Or_NoBWI>; +defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32, + v4i32, v8i32, NoVLX>; +defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64, + v2i64, v4i64, NoVLX>; + +let Predicates = [HasAVX2, NoVLX] in { + // 32-bit targets will fail to load a i64 directly but can use ZEXT_LOAD. + def : Pat<(v2i64 (X86VBroadcast (v2i64 (X86vzload addr:$src)))), + (VPBROADCASTQrm addr:$src)>; + def : Pat<(v4i64 (X86VBroadcast (v4i64 (X86vzload addr:$src)))), + (VPBROADCASTQYrm addr:$src)>; + + def : Pat<(v4i32 (X86VBroadcast (v4i32 (scalar_to_vector (loadi32 addr:$src))))), + (VPBROADCASTDrm addr:$src)>; + def : Pat<(v8i32 (X86VBroadcast (v4i32 (scalar_to_vector (loadi32 addr:$src))))), + (VPBROADCASTDYrm addr:$src)>; + def : Pat<(v2i64 (X86VBroadcast (v2i64 (scalar_to_vector (loadi64 addr:$src))))), + (VPBROADCASTQrm addr:$src)>; + def : Pat<(v4i64 (X86VBroadcast (v2i64 (scalar_to_vector (loadi64 addr:$src))))), + (VPBROADCASTQYrm addr:$src)>; +} +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { + // loadi16 is tricky to fold, because !isTypeDesirableForOp, justifiably. + // This means we'll encounter truncated i32 loads; match that here. + def : Pat<(v8i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))), + (VPBROADCASTWrm addr:$src)>; + def : Pat<(v16i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))), + (VPBROADCASTWYrm addr:$src)>; + def : Pat<(v8i16 (X86VBroadcast + (i16 (trunc (i32 (zextloadi16 addr:$src)))))), + (VPBROADCASTWrm addr:$src)>; + def : Pat<(v16i16 (X86VBroadcast + (i16 (trunc (i32 (zextloadi16 addr:$src)))))), + (VPBROADCASTWYrm addr:$src)>; +} + +let Predicates = [HasAVX2, NoVLX] in { + // Provide aliases for broadcast from the same register class that + // automatically does the extract. + def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))), + (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), + sub_xmm)))>; + def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))), + (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), + sub_xmm)))>; +} + +let Predicates = [HasAVX2, NoVLX] in { + // Provide fallback in case the load node that is used in the patterns above + // is used by additional users, which prevents the pattern selection. + def : Pat<(v4f32 (X86VBroadcast FR32:$src)), + (VBROADCASTSSrr (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)))>; + def : Pat<(v8f32 (X86VBroadcast FR32:$src)), + (VBROADCASTSSYrr (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)))>; + def : Pat<(v4f64 (X86VBroadcast FR64:$src)), + (VBROADCASTSDYrr (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))>; +} + +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { + def : Pat<(v16i8 (X86VBroadcast GR8:$src)), + (VPBROADCASTBrr (v16i8 (COPY_TO_REGCLASS + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), + GR8:$src, sub_8bit)), + VR128)))>; + def : Pat<(v32i8 (X86VBroadcast GR8:$src)), + (VPBROADCASTBYrr (v16i8 (COPY_TO_REGCLASS + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), + GR8:$src, sub_8bit)), + VR128)))>; + + def : Pat<(v8i16 (X86VBroadcast GR16:$src)), + (VPBROADCASTWrr (v8i16 (COPY_TO_REGCLASS + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), + GR16:$src, sub_16bit)), + VR128)))>; + def : Pat<(v16i16 (X86VBroadcast GR16:$src)), + (VPBROADCASTWYrr (v8i16 (COPY_TO_REGCLASS + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), + GR16:$src, sub_16bit)), + VR128)))>; +} +let Predicates = [HasAVX2, NoVLX] in { + def : Pat<(v4i32 (X86VBroadcast GR32:$src)), + (VPBROADCASTDrr (v4i32 (COPY_TO_REGCLASS GR32:$src, VR128)))>; + def : Pat<(v8i32 (X86VBroadcast GR32:$src)), + (VPBROADCASTDYrr (v4i32 (COPY_TO_REGCLASS GR32:$src, VR128)))>; + def : Pat<(v2i64 (X86VBroadcast GR64:$src)), + (VPBROADCASTQrr (v2i64 (COPY_TO_REGCLASS GR64:$src, VR128)))>; + def : Pat<(v4i64 (X86VBroadcast GR64:$src)), + (VPBROADCASTQYrr (v2i64 (COPY_TO_REGCLASS GR64:$src, VR128)))>; +} + +// AVX1 broadcast patterns +let Predicates = [HasAVX1Only] in { +def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))), + (VBROADCASTSSYrm addr:$src)>; +def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))), + (VBROADCASTSDYrm addr:$src)>; +def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))), + (VBROADCASTSSrm addr:$src)>; +} + + // Provide fallback in case the load node that is used in the patterns above + // is used by additional users, which prevents the pattern selection. +let Predicates = [HasAVX, NoVLX] in { + // 128bit broadcasts: + def : Pat<(v2f64 (X86VBroadcast f64:$src)), + (VMOVDDUPrr (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))>; + def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))), + (VMOVDDUPrm addr:$src)>; + + def : Pat<(v2f64 (X86VBroadcast v2f64:$src)), + (VMOVDDUPrr VR128:$src)>; + def : Pat<(v2f64 (X86VBroadcast (loadv2f64 addr:$src))), + (VMOVDDUPrm addr:$src)>; +} + +let Predicates = [HasAVX1Only] in { + def : Pat<(v4f32 (X86VBroadcast FR32:$src)), + (VPERMILPSri (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 0)>; + def : Pat<(v8f32 (X86VBroadcast FR32:$src)), + (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), + (v4f32 (VPERMILPSri (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 0)), sub_xmm), + (v4f32 (VPERMILPSri (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 0)), 1)>; + def : Pat<(v4f64 (X86VBroadcast FR64:$src)), + (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), + (v2f64 (VMOVDDUPrr (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))), sub_xmm), + (v2f64 (VMOVDDUPrr (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))), 1)>; + + def : Pat<(v4i32 (X86VBroadcast GR32:$src)), + (VPSHUFDri (v4i32 (COPY_TO_REGCLASS GR32:$src, VR128)), 0)>; + def : Pat<(v8i32 (X86VBroadcast GR32:$src)), + (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + (v4i32 (VPSHUFDri (v4i32 (COPY_TO_REGCLASS GR32:$src, VR128)), 0)), sub_xmm), + (v4i32 (VPSHUFDri (v4i32 (COPY_TO_REGCLASS GR32:$src, VR128)), 0)), 1)>; + def : Pat<(v4i64 (X86VBroadcast GR64:$src)), + (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), + (v4i32 (VPSHUFDri (v4i32 (COPY_TO_REGCLASS GR64:$src, VR128)), 0x44)), sub_xmm), + (v4i32 (VPSHUFDri (v4i32 (COPY_TO_REGCLASS GR64:$src, VR128)), 0x44)), 1)>; + + def : Pat<(v2i64 (X86VBroadcast i64:$src)), + (VPSHUFDri (v4i32 (COPY_TO_REGCLASS GR64:$src, VR128)), 0x44)>; + def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))), + (VMOVDDUPrm addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// VPERM - Permute instructions +// + +multiclass avx2_perm opc, string OpcodeStr, PatFrag mem_frag, + ValueType OpVT, X86FoldableSchedWrite Sched, + X86MemOperand memOp> { + let Predicates = [HasAVX2, NoVLX] in { + def Yrr : AVX28I, + Sched<[Sched]>, VEX_4V, VEX_L; + def Yrm : AVX28I, + Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L; + } +} + +defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteVarShuffle256, + i256mem>; +let ExeDomain = SSEPackedSingle in +defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFVarShuffle256, + f256mem>; + +multiclass avx2_perm_imm opc, string OpcodeStr, PatFrag mem_frag, + ValueType OpVT, X86FoldableSchedWrite Sched, + X86MemOperand memOp> { + let Predicates = [HasAVX2, NoVLX] in { + def Yri : AVX2AIi8, + Sched<[Sched]>, VEX, VEX_L; + def Ymi : AVX2AIi8, + Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L; + } +} + +defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64, + WriteShuffle256, i256mem>, VEX_W; +let ExeDomain = SSEPackedDouble in +defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64, + WriteFShuffle256, f256mem>, VEX_W; + +//===----------------------------------------------------------------------===// +// VPERM2I128 - Permute Floating-Point Values in 128-bit chunks +// +let isCommutable = 1 in +def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst), + (ins VR256:$src1, VR256:$src2, u8imm:$src3), + "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, + (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>, + VEX_4V, VEX_L; +def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst), + (ins VR256:$src1, f256mem:$src2, u8imm:$src3), + "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2), + (i8 imm:$src3)))]>, + Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L; + +let Predicates = [HasAVX2] in +def : Pat<(v4i64 (X86VPerm2x128 (loadv4i64 addr:$src2), + VR256:$src1, (i8 imm:$imm))), + (VPERM2I128rm VR256:$src1, addr:$src2, (Perm2XCommuteImm imm:$imm))>; + + +//===----------------------------------------------------------------------===// +// VINSERTI128 - Insert packed integer values +// +let hasSideEffects = 0 in { +def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst), + (ins VR256:$src1, VR128:$src2, u8imm:$src3), + "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L; +let mayLoad = 1 in +def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst), + (ins VR256:$src1, i128mem:$src2, u8imm:$src3), + "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L; +} + +let Predicates = [HasAVX2, NoVLX] in { + defm : vinsert_lowering<"VINSERTI128", v2i64, v4i64, loadv2i64>; + defm : vinsert_lowering<"VINSERTI128", v4i32, v8i32, loadv2i64>; + defm : vinsert_lowering<"VINSERTI128", v8i16, v16i16, loadv2i64>; + defm : vinsert_lowering<"VINSERTI128", v16i8, v32i8, loadv2i64>; +} + +//===----------------------------------------------------------------------===// +// VEXTRACTI128 - Extract packed integer values +// +def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst), + (ins VR256:$src1, u8imm:$src2), + "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + Sched<[WriteShuffle256]>, VEX, VEX_L; +let hasSideEffects = 0, mayStore = 1 in +def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs), + (ins i128mem:$dst, VR256:$src1, u8imm:$src2), + "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + Sched<[SchedWriteVecMoveLS.XMM.MR]>, VEX, VEX_L; + +let Predicates = [HasAVX2, NoVLX] in { + defm : vextract_lowering<"VEXTRACTI128", v4i64, v2i64>; + defm : vextract_lowering<"VEXTRACTI128", v8i32, v4i32>; + defm : vextract_lowering<"VEXTRACTI128", v16i16, v8i16>; + defm : vextract_lowering<"VEXTRACTI128", v32i8, v16i8>; +} + +//===----------------------------------------------------------------------===// +// VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores +// +multiclass avx2_pmovmask { + def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, i128mem:$src2), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, + VEX_4V, Sched<[WriteVecMaskedLoad]>; + def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst), + (ins VR256:$src1, i256mem:$src2), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, + VEX_4V, VEX_L, Sched<[WriteVecMaskedLoadY]>; + def mr : AVX28I<0x8e, MRMDestMem, (outs), + (ins i128mem:$dst, VR128:$src1, VR128:$src2), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, + VEX_4V, Sched<[WriteVecMaskedStore]>; + def Ymr : AVX28I<0x8e, MRMDestMem, (outs), + (ins i256mem:$dst, VR256:$src1, VR256:$src2), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, + VEX_4V, VEX_L, Sched<[WriteVecMaskedStoreY]>; +} + +defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd", + int_x86_avx2_maskload_d, + int_x86_avx2_maskload_d_256, + int_x86_avx2_maskstore_d, + int_x86_avx2_maskstore_d_256>; +defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq", + int_x86_avx2_maskload_q, + int_x86_avx2_maskload_q_256, + int_x86_avx2_maskstore_q, + int_x86_avx2_maskstore_q_256>, VEX_W; + +multiclass maskmov_lowering { + // masked store + def: Pat<(X86mstore addr:$ptr, (MaskVT RC:$mask), (VT RC:$src)), + (!cast(InstrStr#"mr") addr:$ptr, RC:$mask, RC:$src)>; + // masked load + def: Pat<(VT (X86mload addr:$ptr, (MaskVT RC:$mask), undef)), + (!cast(InstrStr#"rm") RC:$mask, addr:$ptr)>; + def: Pat<(VT (X86mload addr:$ptr, (MaskVT RC:$mask), + (VT (bitconvert (ZeroVT immAllZerosV))))), + (!cast(InstrStr#"rm") RC:$mask, addr:$ptr)>; + def: Pat<(VT (X86mload addr:$ptr, (MaskVT RC:$mask), (VT RC:$src0))), + (!cast(BlendStr#"rr") + RC:$src0, + (VT (!cast(InstrStr#"rm") RC:$mask, addr:$ptr)), + RC:$mask)>; +} +let Predicates = [HasAVX] in { + defm : maskmov_lowering<"VMASKMOVPS", VR128, v4f32, v4i32, "VBLENDVPS", v4i32>; + defm : maskmov_lowering<"VMASKMOVPD", VR128, v2f64, v2i64, "VBLENDVPD", v4i32>; + defm : maskmov_lowering<"VMASKMOVPSY", VR256, v8f32, v8i32, "VBLENDVPSY", v8i32>; + defm : maskmov_lowering<"VMASKMOVPDY", VR256, v4f64, v4i64, "VBLENDVPDY", v8i32>; +} +let Predicates = [HasAVX1Only] in { + // load/store i32/i64 not supported use ps/pd version + defm : maskmov_lowering<"VMASKMOVPSY", VR256, v8i32, v8i32, "VBLENDVPSY", v8i32>; + defm : maskmov_lowering<"VMASKMOVPDY", VR256, v4i64, v4i64, "VBLENDVPDY", v8i32>; + defm : maskmov_lowering<"VMASKMOVPS", VR128, v4i32, v4i32, "VBLENDVPS", v4i32>; + defm : maskmov_lowering<"VMASKMOVPD", VR128, v2i64, v2i64, "VBLENDVPD", v4i32>; +} +let Predicates = [HasAVX2] in { + defm : maskmov_lowering<"VPMASKMOVDY", VR256, v8i32, v8i32, "VBLENDVPSY", v8i32>; + defm : maskmov_lowering<"VPMASKMOVQY", VR256, v4i64, v4i64, "VBLENDVPDY", v8i32>; + defm : maskmov_lowering<"VPMASKMOVD", VR128, v4i32, v4i32, "VBLENDVPS", v4i32>; + defm : maskmov_lowering<"VPMASKMOVQ", VR128, v2i64, v2i64, "VBLENDVPD", v4i32>; +} + +//===----------------------------------------------------------------------===// +// SubVector Broadcasts +// Provide fallback in case the load node that is used in the patterns above +// is used by additional users, which prevents the pattern selection. + +let Predicates = [HasAVX2, NoVLX] in { +def : Pat<(v4i64 (X86SubVBroadcast (v2i64 VR128:$src))), + (VINSERTI128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v2i64 VR128:$src), 1)>; +def : Pat<(v8i32 (X86SubVBroadcast (v4i32 VR128:$src))), + (VINSERTI128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v4i32 VR128:$src), 1)>; +def : Pat<(v16i16 (X86SubVBroadcast (v8i16 VR128:$src))), + (VINSERTI128rr (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v8i16 VR128:$src), 1)>; +def : Pat<(v32i8 (X86SubVBroadcast (v16i8 VR128:$src))), + (VINSERTI128rr (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v16i8 VR128:$src), 1)>; +} + +let Predicates = [HasAVX, NoVLX] in { +def : Pat<(v4f64 (X86SubVBroadcast (v2f64 VR128:$src))), + (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v2f64 VR128:$src), 1)>; +def : Pat<(v8f32 (X86SubVBroadcast (v4f32 VR128:$src))), + (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v4f32 VR128:$src), 1)>; +} + +let Predicates = [HasAVX1Only] in { +def : Pat<(v4i64 (X86SubVBroadcast (v2i64 VR128:$src))), + (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v2i64 VR128:$src), 1)>; +def : Pat<(v8i32 (X86SubVBroadcast (v4i32 VR128:$src))), + (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v4i32 VR128:$src), 1)>; +def : Pat<(v16i16 (X86SubVBroadcast (v8i16 VR128:$src))), + (VINSERTF128rr (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v8i16 VR128:$src), 1)>; +def : Pat<(v32i8 (X86SubVBroadcast (v16i8 VR128:$src))), + (VINSERTF128rr (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v16i8 VR128:$src), 1)>; +} + +//===----------------------------------------------------------------------===// +// Variable Bit Shifts +// +multiclass avx2_var_shift opc, string OpcodeStr, SDNode OpNode, + ValueType vt128, ValueType vt256> { + def rr : AVX28I, + VEX_4V, Sched<[SchedWriteVarVecShift.XMM]>; + def rm : AVX28I, + VEX_4V, Sched<[SchedWriteVarVecShift.XMM.Folded, ReadAfterLd]>; + def Yrr : AVX28I, + VEX_4V, VEX_L, Sched<[SchedWriteVarVecShift.YMM]>; + def Yrm : AVX28I, + VEX_4V, VEX_L, Sched<[SchedWriteVarVecShift.YMM.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX2, NoVLX] in { + defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>; + defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W; + defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>; + defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W; + defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>; + + def : Pat<(v4i32 (X86vsrav VR128:$src1, VR128:$src2)), + (VPSRAVDrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4i32 (X86vsrav VR128:$src1, + (bitconvert (loadv2i64 addr:$src2)))), + (VPSRAVDrm VR128:$src1, addr:$src2)>; + def : Pat<(v8i32 (X86vsrav VR256:$src1, VR256:$src2)), + (VPSRAVDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (X86vsrav VR256:$src1, + (bitconvert (loadv4i64 addr:$src2)))), + (VPSRAVDYrm VR256:$src1, addr:$src2)>; +} + +//===----------------------------------------------------------------------===// +// VGATHER - GATHER Operations + +// FIXME: Improve scheduling of gather instructions. +multiclass avx2_gather opc, string OpcodeStr, ValueType VTx, + ValueType VTy, PatFrag GatherNode128, + PatFrag GatherNode256, RegisterClass RC256, + X86MemOperand memop128, X86MemOperand memop256, + ValueType MTx = VTx, ValueType MTy = VTy> { + def rm : AVX28I, + VEX, Sched<[WriteLoad]>; + def Yrm : AVX28I, + VEX, VEX_L, Sched<[WriteLoad]>; +} + +let Predicates = [UseAVX2] in { + let mayLoad = 1, hasSideEffects = 0, Constraints + = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb" + in { + defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", v2i64, v4i64, mgatherv4i32, + mgatherv4i32, VR256, vx128mem, vx256mem>, VEX_W; + defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", v2i64, v4i64, mgatherv2i64, + mgatherv4i64, VR256, vx128mem, vy256mem>, VEX_W; + defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", v4i32, v8i32, mgatherv4i32, + mgatherv8i32, VR256, vx128mem, vy256mem>; + defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", v4i32, v4i32, mgatherv2i64, + mgatherv4i64, VR128, vx64mem, vy128mem>; + + let ExeDomain = SSEPackedDouble in { + defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", v2f64, v4f64, mgatherv4i32, + mgatherv4i32, VR256, vx128mem, vx256mem, + v2i64, v4i64>, VEX_W; + defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", v2f64, v4f64, mgatherv2i64, + mgatherv4i64, VR256, vx128mem, vy256mem, + v2i64, v4i64>, VEX_W; + } + + let ExeDomain = SSEPackedSingle in { + defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", v4f32, v8f32, mgatherv4i32, + mgatherv8i32, VR256, vx128mem, vy256mem, + v4i32, v8i32>; + defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", v4f32, v4f32, mgatherv2i64, + mgatherv4i64, VR128, vx64mem, vy128mem, + v4i32, v4i32>; + } + } +} + +//===----------------------------------------------------------------------===// +// Extra selection patterns for f128, f128mem + +// movaps is shorter than movdqa. movaps is in SSE and movdqa is in SSE2. +def : Pat<(alignedstore (f128 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, (COPY_TO_REGCLASS (f128 VR128:$src), VR128))>; +def : Pat<(store (f128 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, (COPY_TO_REGCLASS (f128 VR128:$src), VR128))>; + +def : Pat<(alignedloadf128 addr:$src), + (COPY_TO_REGCLASS (MOVAPSrm addr:$src), VR128)>; +def : Pat<(loadf128 addr:$src), + (COPY_TO_REGCLASS (MOVUPSrm addr:$src), VR128)>; + +// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2 +def : Pat<(f128 (X86fand VR128:$src1, (memopf128 addr:$src2))), + (COPY_TO_REGCLASS + (ANDPSrm (COPY_TO_REGCLASS VR128:$src1, VR128), f128mem:$src2), + VR128)>; + +def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)), + (COPY_TO_REGCLASS + (ANDPSrr (COPY_TO_REGCLASS VR128:$src1, VR128), + (COPY_TO_REGCLASS VR128:$src2, VR128)), VR128)>; + +def : Pat<(f128 (X86for VR128:$src1, (memopf128 addr:$src2))), + (COPY_TO_REGCLASS + (ORPSrm (COPY_TO_REGCLASS VR128:$src1, VR128), f128mem:$src2), + VR128)>; + +def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)), + (COPY_TO_REGCLASS + (ORPSrr (COPY_TO_REGCLASS VR128:$src1, VR128), + (COPY_TO_REGCLASS VR128:$src2, VR128)), VR128)>; + +def : Pat<(f128 (X86fxor VR128:$src1, (memopf128 addr:$src2))), + (COPY_TO_REGCLASS + (XORPSrm (COPY_TO_REGCLASS VR128:$src1, VR128), f128mem:$src2), + VR128)>; + +def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)), + (COPY_TO_REGCLASS + (XORPSrr (COPY_TO_REGCLASS VR128:$src1, VR128), + (COPY_TO_REGCLASS VR128:$src2, VR128)), VR128)>; + +//===----------------------------------------------------------------------===// +// GFNI instructions +//===----------------------------------------------------------------------===// + +multiclass GF2P8MULB_rm { + let ExeDomain = SSEPackedInt, + AsmString = !if(Is2Addr, + OpcodeStr##"\t{$src2, $dst|$dst, $src2}", + OpcodeStr##"\t{$src2, $src1, $dst|$dst, $src1, $src2}") in { + let isCommutable = 1 in + def rr : PDI<0xCF, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), "", + [(set RC:$dst, (OpVT (X86GF2P8mulb RC:$src1, RC:$src2)))]>, + Sched<[SchedWriteVecALU.XMM]>, T8PD; + + def rm : PDI<0xCF, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, X86MemOp:$src2), "", + [(set RC:$dst, (OpVT (X86GF2P8mulb RC:$src1, + (bitconvert (MemOpFrag addr:$src2)))))]>, + Sched<[SchedWriteVecALU.XMM.Folded, ReadAfterLd]>, T8PD; + } +} + +multiclass GF2P8AFFINE_rmi Op, string OpStr, ValueType OpVT, + SDNode OpNode, RegisterClass RC, PatFrag MemOpFrag, + X86MemOperand X86MemOp, bit Is2Addr = 0> { + let AsmString = !if(Is2Addr, + OpStr##"\t{$src3, $src2, $dst|$dst, $src2, $src3}", + OpStr##"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}") in { + def rri : Ii8, Sched<[SchedWriteVecALU.XMM]>; + def rmi : Ii8, + Sched<[SchedWriteVecALU.XMM.Folded, ReadAfterLd]>; + } +} + +multiclass GF2P8AFFINE_common Op, string OpStr, SDNode OpNode> { + let Constraints = "$src1 = $dst", + Predicates = [HasGFNI, UseSSE2] in + defm NAME : GF2P8AFFINE_rmi; + let Predicates = [HasGFNI, HasAVX, NoVLX_Or_NoBWI] in { + defm V##NAME : GF2P8AFFINE_rmi, VEX_4V, VEX_W; + defm V##NAME##Y : GF2P8AFFINE_rmi, VEX_4V, VEX_L, VEX_W; + } +} + +// GF2P8MULB +let Constraints = "$src1 = $dst", + Predicates = [HasGFNI, UseSSE2] in +defm GF2P8MULB : GF2P8MULB_rm<"gf2p8mulb", v16i8, VR128, memopv2i64, + i128mem, 1>; +let Predicates = [HasGFNI, HasAVX, NoVLX_Or_NoBWI] in { + defm VGF2P8MULB : GF2P8MULB_rm<"vgf2p8mulb", v16i8, VR128, loadv2i64, + i128mem>, VEX_4V; + defm VGF2P8MULBY : GF2P8MULB_rm<"vgf2p8mulb", v32i8, VR256, loadv4i64, + i256mem>, VEX_4V, VEX_L; +} +// GF2P8AFFINEINVQB, GF2P8AFFINEQB +let isCommutable = 0 in { + defm GF2P8AFFINEINVQB : GF2P8AFFINE_common<0xCF, "gf2p8affineinvqb", + X86GF2P8affineinvqb>, TAPD; + defm GF2P8AFFINEQB : GF2P8AFFINE_common<0xCE, "gf2p8affineqb", + X86GF2P8affineqb>, TAPD; +} + diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrSVM.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrSVM.td new file mode 100644 index 0000000..2dc6e8b --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrSVM.td @@ -0,0 +1,63 @@ +//===-- X86InstrSVM.td - SVM Instruction Set Extension -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the AMD SVM instruction +// set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// SVM instructions + +let SchedRW = [WriteSystem] in { +// 0F 01 D9 +def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB; + +// 0F 01 DC +def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB; + +// 0F 01 DD +def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB; + +// 0F 01 DE +let Uses = [EAX] in +def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB; + +// 0F 01 D8 +let Uses = [EAX] in +def VMRUN32 : I<0x01, MRM_D8, (outs), (ins), "vmrun\t{%eax|eax}", []>, TB, + Requires<[Not64BitMode]>; +let Uses = [RAX] in +def VMRUN64 : I<0x01, MRM_D8, (outs), (ins), "vmrun\t{%rax|rax}", []>, TB, + Requires<[In64BitMode]>; + +// 0F 01 DA +let Uses = [EAX] in +def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins), "vmload\t{%eax|eax}", []>, TB, + Requires<[Not64BitMode]>; +let Uses = [RAX] in +def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins), "vmload\t{%rax|rax}", []>, TB, + Requires<[In64BitMode]>; + +// 0F 01 DB +let Uses = [EAX] in +def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins), "vmsave\t{%eax|eax}", []>, TB, + Requires<[Not64BitMode]>; +let Uses = [RAX] in +def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins), "vmsave\t{%rax|rax}", []>, TB, + Requires<[In64BitMode]>; + +// 0F 01 DF +let Uses = [EAX, ECX] in +def INVLPGA32 : I<0x01, MRM_DF, (outs), (ins), + "invlpga\t{%eax, %ecx|eax, ecx}", []>, TB, Requires<[Not64BitMode]>; +let Uses = [RAX, ECX] in +def INVLPGA64 : I<0x01, MRM_DF, (outs), (ins), + "invlpga\t{%rax, %ecx|rax, ecx}", []>, TB, Requires<[In64BitMode]>; +} // SchedRW diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrShiftRotate.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrShiftRotate.td new file mode 100644 index 0000000..cbcb1da --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrShiftRotate.td @@ -0,0 +1,1031 @@ +//===-- X86InstrShiftRotate.td - Shift and Rotate Instrs ---*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the shift and rotate instructions. +// +//===----------------------------------------------------------------------===// + +// FIXME: Someone needs to smear multipattern goodness all over this file. + +let Defs = [EFLAGS] in { + +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { +let Uses = [CL] in { +def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1), + "shl{b}\t{%cl, $dst|$dst, cl}", + [(set GR8:$dst, (shl GR8:$src1, CL))]>; +def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1), + "shl{w}\t{%cl, $dst|$dst, cl}", + [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize16; +def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1), + "shl{l}\t{%cl, $dst|$dst, cl}", + [(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32; +def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1), + "shl{q}\t{%cl, $dst|$dst, cl}", + [(set GR64:$dst, (shl GR64:$src1, CL))]>; +} // Uses = [CL] + +def SAL8rCL : I<0xD2, MRM6r, (outs GR8 :$dst), (ins GR8 :$src1), "sal{b}\t{%cl, $dst|$dst, cl}", []>; +def SAL16rCL : I<0xD3, MRM6r, (outs GR16:$dst), (ins GR16:$src1), + "sal{w}\t{%cl, $dst|$dst, cl}", + []>, OpSize16; +def SAL32rCL : I<0xD3, MRM6r, (outs GR32:$dst), (ins GR32:$src1), + "sal{l}\t{%cl, $dst|$dst, cl}", + []>, OpSize32; +def SAL64rCL : RI<0xD3, MRM6r, (outs GR64:$dst), (ins GR64:$src1), + "sal{q}\t{%cl, $dst|$dst, cl}", + []>; + +def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), + "shl{b}\t{$src2, $dst|$dst, $src2}", + [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; + +def SAL8ri : Ii8<0xC0, MRM6r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), + "sal{b}\t{$src2, $dst|$dst, $src2}", + []>; + +let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. +def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), + "shl{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, + OpSize16; +def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), + "shl{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>, + OpSize32; +def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), + (ins GR64:$src1, u8imm:$src2), + "shl{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>; + +def SAL16ri : Ii8<0xC1, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), + "sal{w}\t{$src2, $dst|$dst, $src2}", + []>, + OpSize16; +def SAL32ri : Ii8<0xC1, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), + "sal{l}\t{$src2, $dst|$dst, $src2}", + []>, + OpSize32; +def SAL64ri : RIi8<0xC1, MRM6r, (outs GR64:$dst), + (ins GR64:$src1, i8imm:$src2), + "sal{q}\t{$src2, $dst|$dst, $src2}", + []>; +} // isConvertibleToThreeAddress = 1 + +// NOTE: We don't include patterns for shifts of a register by one, because +// 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one). +let hasSideEffects = 0 in { +def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1), + "shl{b}\t{$$1, $dst|$dst, 1}", []>; +def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1), + "shl{w}\t{$$1, $dst|$dst, 1}", []>, OpSize16; +def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1), + "shl{l}\t{$$1, $dst|$dst, 1}", []>, OpSize32; +def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), + "shl{q}\t{$$1, $dst|$dst, 1}", []>; +def SAL8r1 : I<0xD0, MRM6r, (outs GR8:$dst), (ins GR8:$src1), + "sal{b}\t{$$1, $dst|$dst, 1}", []>; +def SAL16r1 : I<0xD1, MRM6r, (outs GR16:$dst), (ins GR16:$src1), + "sal{w}\t{$$1, $dst|$dst, 1}", []>, OpSize16; +def SAL32r1 : I<0xD1, MRM6r, (outs GR32:$dst), (ins GR32:$src1), + "sal{l}\t{$$1, $dst|$dst, 1}", []>, OpSize32; +def SAL64r1 : RI<0xD1, MRM6r, (outs GR64:$dst), (ins GR64:$src1), + "sal{q}\t{$$1, $dst|$dst, 1}", []>; +} // hasSideEffects = 0 +} // Constraints = "$src = $dst", SchedRW + + +let SchedRW = [WriteShiftLd, WriteRMW] in { +// FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern +// using CL? +let Uses = [CL] in { +def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), + "shl{b}\t{%cl, $dst|$dst, cl}", + [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>; +def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), + "shl{w}\t{%cl, $dst|$dst, cl}", + [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, + OpSize16; +def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), + "shl{l}\t{%cl, $dst|$dst, cl}", + [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>, + OpSize32; +def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst), + "shl{q}\t{%cl, $dst|$dst, cl}", + [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>, + Requires<[In64BitMode]>; +def SAL8mCL : I<0xD2, MRM6m, (outs), (ins i8mem :$dst), + "sal{b}\t{%cl, $dst|$dst, cl}", + []>; +def SAL16mCL : I<0xD3, MRM6m, (outs), (ins i16mem:$dst), + "sal{w}\t{%cl, $dst|$dst, cl}", + []>, + OpSize16; +def SAL32mCL : I<0xD3, MRM6m, (outs), (ins i32mem:$dst), + "sal{l}\t{%cl, $dst|$dst, cl}", + []>, + OpSize32; +def SAL64mCL : RI<0xD3, MRM6m, (outs), (ins i64mem:$dst), + "sal{q}\t{%cl, $dst|$dst, cl}", + []>; +} +def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, u8imm:$src), + "shl{b}\t{$src, $dst|$dst, $src}", + [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; +def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, u8imm:$src), + "shl{w}\t{$src, $dst|$dst, $src}", + [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize16; +def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, u8imm:$src), + "shl{l}\t{$src, $dst|$dst, $src}", + [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize32; +def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, u8imm:$src), + "shl{q}\t{$src, $dst|$dst, $src}", + [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + Requires<[In64BitMode]>; +def SAL8mi : Ii8<0xC0, MRM6m, (outs), (ins i8mem :$dst, i8imm:$src), + "sal{b}\t{$src, $dst|$dst, $src}", + []>; +def SAL16mi : Ii8<0xC1, MRM6m, (outs), (ins i16mem:$dst, i8imm:$src), + "sal{w}\t{$src, $dst|$dst, $src}", + []>, OpSize16; +def SAL32mi : Ii8<0xC1, MRM6m, (outs), (ins i32mem:$dst, i8imm:$src), + "sal{l}\t{$src, $dst|$dst, $src}", + []>, OpSize32; +def SAL64mi : RIi8<0xC1, MRM6m, (outs), (ins i64mem:$dst, i8imm:$src), + "sal{q}\t{$src, $dst|$dst, $src}", + []>; + +// Shift by 1 +def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst), + "shl{b}\t{$dst|$dst, 1}", + [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; +def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), + "shl{w}\t{$dst|$dst, 1}", + [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize16; +def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), + "shl{l}\t{$dst|$dst, 1}", + [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize32; +def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst), + "shl{q}\t{$dst|$dst, 1}", + [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>, + Requires<[In64BitMode]>; +def SAL8m1 : I<0xD0, MRM6m, (outs), (ins i8mem :$dst), + "sal{b}\t{$dst|$dst, 1}", + []>; +def SAL16m1 : I<0xD1, MRM6m, (outs), (ins i16mem:$dst), + "sal{w}\t{$dst|$dst, 1}", + []>, OpSize16; +def SAL32m1 : I<0xD1, MRM6m, (outs), (ins i32mem:$dst), + "sal{l}\t{$dst|$dst, 1}", + []>, OpSize32; +def SAL64m1 : RI<0xD1, MRM6m, (outs), (ins i64mem:$dst), + "sal{q}\t{$dst|$dst, 1}", + []>; +} // SchedRW + +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { +let Uses = [CL] in { +def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1), + "shr{b}\t{%cl, $dst|$dst, cl}", + [(set GR8:$dst, (srl GR8:$src1, CL))]>; +def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1), + "shr{w}\t{%cl, $dst|$dst, cl}", + [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize16; +def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1), + "shr{l}\t{%cl, $dst|$dst, cl}", + [(set GR32:$dst, (srl GR32:$src1, CL))]>, OpSize32; +def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1), + "shr{q}\t{%cl, $dst|$dst, cl}", + [(set GR64:$dst, (srl GR64:$src1, CL))]>; +} + +def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2), + "shr{b}\t{$src2, $dst|$dst, $src2}", + [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>; +def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), + "shr{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, + OpSize16; +def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), + "shr{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>, + OpSize32; +def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2), + "shr{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>; + +// Shift right by 1 +def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), + "shr{b}\t{$$1, $dst|$dst, 1}", + [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>; +def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), + "shr{w}\t{$$1, $dst|$dst, 1}", + [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize16; +def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), + "shr{l}\t{$$1, $dst|$dst, 1}", + [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>, OpSize32; +def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1), + "shr{q}\t{$$1, $dst|$dst, 1}", + [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>; +} // Constraints = "$src = $dst", SchedRW + + +let SchedRW = [WriteShiftLd, WriteRMW] in { +let Uses = [CL] in { +def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), + "shr{b}\t{%cl, $dst|$dst, cl}", + [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>; +def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), + "shr{w}\t{%cl, $dst|$dst, cl}", + [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, + OpSize16; +def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), + "shr{l}\t{%cl, $dst|$dst, cl}", + [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>, + OpSize32; +def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst), + "shr{q}\t{%cl, $dst|$dst, cl}", + [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>, + Requires<[In64BitMode]>; +} +def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, u8imm:$src), + "shr{b}\t{$src, $dst|$dst, $src}", + [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; +def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, u8imm:$src), + "shr{w}\t{$src, $dst|$dst, $src}", + [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize16; +def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, u8imm:$src), + "shr{l}\t{$src, $dst|$dst, $src}", + [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize32; +def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, u8imm:$src), + "shr{q}\t{$src, $dst|$dst, $src}", + [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + Requires<[In64BitMode]>; + +// Shift by 1 +def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst), + "shr{b}\t{$dst|$dst, 1}", + [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; +def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), + "shr{w}\t{$dst|$dst, 1}", + [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize16; +def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), + "shr{l}\t{$dst|$dst, 1}", + [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize32; +def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst), + "shr{q}\t{$dst|$dst, 1}", + [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW + +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { +let Uses = [CL] in { +def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), + "sar{b}\t{%cl, $dst|$dst, cl}", + [(set GR8:$dst, (sra GR8:$src1, CL))]>; +def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1), + "sar{w}\t{%cl, $dst|$dst, cl}", + [(set GR16:$dst, (sra GR16:$src1, CL))]>, + OpSize16; +def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1), + "sar{l}\t{%cl, $dst|$dst, cl}", + [(set GR32:$dst, (sra GR32:$src1, CL))]>, + OpSize32; +def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1), + "sar{q}\t{%cl, $dst|$dst, cl}", + [(set GR64:$dst, (sra GR64:$src1, CL))]>; +} + +def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), + "sar{b}\t{$src2, $dst|$dst, $src2}", + [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>; +def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), + "sar{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>, + OpSize16; +def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), + "sar{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>, + OpSize32; +def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), + (ins GR64:$src1, u8imm:$src2), + "sar{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>; + +// Shift by 1 +def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), + "sar{b}\t{$$1, $dst|$dst, 1}", + [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>; +def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), + "sar{w}\t{$$1, $dst|$dst, 1}", + [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize16; +def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), + "sar{l}\t{$$1, $dst|$dst, 1}", + [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>, OpSize32; +def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1), + "sar{q}\t{$$1, $dst|$dst, 1}", + [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>; +} // Constraints = "$src = $dst", SchedRW + + +let SchedRW = [WriteShiftLd, WriteRMW] in { +let Uses = [CL] in { +def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), + "sar{b}\t{%cl, $dst|$dst, cl}", + [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>; +def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), + "sar{w}\t{%cl, $dst|$dst, cl}", + [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, + OpSize16; +def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), + "sar{l}\t{%cl, $dst|$dst, cl}", + [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>, + OpSize32; +def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst), + "sar{q}\t{%cl, $dst|$dst, cl}", + [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>, + Requires<[In64BitMode]>; +} +def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, u8imm:$src), + "sar{b}\t{$src, $dst|$dst, $src}", + [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; +def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, u8imm:$src), + "sar{w}\t{$src, $dst|$dst, $src}", + [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize16; +def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, u8imm:$src), + "sar{l}\t{$src, $dst|$dst, $src}", + [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize32; +def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, u8imm:$src), + "sar{q}\t{$src, $dst|$dst, $src}", + [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + Requires<[In64BitMode]>; + +// Shift by 1 +def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst), + "sar{b}\t{$dst|$dst, 1}", + [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; +def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), + "sar{w}\t{$dst|$dst, 1}", + [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize16; +def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), + "sar{l}\t{$dst|$dst, 1}", + [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize32; +def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst), + "sar{q}\t{$dst|$dst, 1}", + [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Rotate instructions +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0 in { +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { + +let Uses = [CL, EFLAGS] in { +def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1), + "rcl{b}\t{%cl, $dst|$dst, cl}", []>; +def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1), + "rcl{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16; +def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1), + "rcl{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32; +def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1), + "rcl{q}\t{%cl, $dst|$dst, cl}", []>; +} // Uses = [CL, EFLAGS] + +let Uses = [EFLAGS] in { +def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1), + "rcl{b}\t{$$1, $dst|$dst, 1}", []>; +def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt), + "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; +def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1), + "rcl{w}\t{$$1, $dst|$dst, 1}", []>, OpSize16; +def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt), + "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16; +def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1), + "rcl{l}\t{$$1, $dst|$dst, 1}", []>, OpSize32; +def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt), + "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32; +def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1), + "rcl{q}\t{$$1, $dst|$dst, 1}", []>; +def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt), + "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>; +} // Uses = [EFLAGS] + +let Uses = [CL, EFLAGS] in { +def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1), + "rcr{b}\t{%cl, $dst|$dst, cl}", []>; +def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1), + "rcr{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16; +def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1), + "rcr{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32; +def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1), + "rcr{q}\t{%cl, $dst|$dst, cl}", []>; +} // Uses = [CL, EFLAGS] + +let Uses = [EFLAGS] in { +def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1), + "rcr{b}\t{$$1, $dst|$dst, 1}", []>; +def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt), + "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; +def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1), + "rcr{w}\t{$$1, $dst|$dst, 1}", []>, OpSize16; +def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt), + "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16; +def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1), + "rcr{l}\t{$$1, $dst|$dst, 1}", []>, OpSize32; +def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt), + "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32; +def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1), + "rcr{q}\t{$$1, $dst|$dst, 1}", []>; +def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt), + "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>; +} // Uses = [EFLAGS] + +} // Constraints = "$src = $dst" + +let SchedRW = [WriteShiftLd, WriteRMW], mayStore = 1 in { +let Uses = [EFLAGS] in { +def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst), + "rcl{b}\t$dst", []>; +def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, u8imm:$cnt), + "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; +def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst), + "rcl{w}\t$dst", []>, OpSize16; +def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, u8imm:$cnt), + "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16; +def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst), + "rcl{l}\t$dst", []>, OpSize32; +def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, u8imm:$cnt), + "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32; +def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst), + "rcl{q}\t$dst", []>, Requires<[In64BitMode]>; +def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, u8imm:$cnt), + "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>, + Requires<[In64BitMode]>; + +def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst), + "rcr{b}\t{$$1, $dst|$dst, 1}", []>; +def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, u8imm:$cnt), + "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; +def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst), + "rcr{w}\t{$$1, $dst|$dst, 1}", []>, OpSize16; +def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, u8imm:$cnt), + "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16; +def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst), + "rcr{l}\t{$$1, $dst|$dst, 1}", []>, OpSize32; +def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, u8imm:$cnt), + "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32; +def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst), + "rcr{q}\t{$$1, $dst|$dst, 1}", []>, Requires<[In64BitMode]>; +def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, u8imm:$cnt), + "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>, + Requires<[In64BitMode]>; +} // Uses = [EFLAGS] + +let Uses = [CL, EFLAGS] in { +def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst), + "rcl{b}\t{%cl, $dst|$dst, cl}", []>; +def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst), + "rcl{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16; +def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst), + "rcl{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32; +def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst), + "rcl{q}\t{%cl, $dst|$dst, cl}", []>, + Requires<[In64BitMode]>; + +def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst), + "rcr{b}\t{%cl, $dst|$dst, cl}", []>; +def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst), + "rcr{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16; +def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst), + "rcr{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32; +def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst), + "rcr{q}\t{%cl, $dst|$dst, cl}", []>, + Requires<[In64BitMode]>; +} // Uses = [CL, EFLAGS] +} // SchedRW +} // hasSideEffects = 0 + +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { +// FIXME: provide shorter instructions when imm8 == 1 +let Uses = [CL] in { +def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), + "rol{b}\t{%cl, $dst|$dst, cl}", + [(set GR8:$dst, (rotl GR8:$src1, CL))]>; +def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1), + "rol{w}\t{%cl, $dst|$dst, cl}", + [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize16; +def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1), + "rol{l}\t{%cl, $dst|$dst, cl}", + [(set GR32:$dst, (rotl GR32:$src1, CL))]>, OpSize32; +def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1), + "rol{q}\t{%cl, $dst|$dst, cl}", + [(set GR64:$dst, (rotl GR64:$src1, CL))]>; +} + +def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), + "rol{b}\t{$src2, $dst|$dst, $src2}", + [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; +def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), + "rol{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize16; +def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), + "rol{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>, OpSize32; +def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), + (ins GR64:$src1, u8imm:$src2), + "rol{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>; + +// Rotate by 1 +def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), + "rol{b}\t{$$1, $dst|$dst, 1}", + [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>; +def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), + "rol{w}\t{$$1, $dst|$dst, 1}", + [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize16; +def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), + "rol{l}\t{$$1, $dst|$dst, 1}", + [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>, OpSize32; +def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1), + "rol{q}\t{$$1, $dst|$dst, 1}", + [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>; +} // Constraints = "$src = $dst", SchedRW + +let SchedRW = [WriteShiftLd, WriteRMW] in { +let Uses = [CL] in { +def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), + "rol{b}\t{%cl, $dst|$dst, cl}", + [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>; +def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), + "rol{w}\t{%cl, $dst|$dst, cl}", + [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize16; +def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), + "rol{l}\t{%cl, $dst|$dst, cl}", + [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>, OpSize32; +def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst), + "rol{q}\t{%cl, $dst|$dst, cl}", + [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>, + Requires<[In64BitMode]>; +} +def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, u8imm:$src1), + "rol{b}\t{$src1, $dst|$dst, $src1}", + [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)]>; +def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, u8imm:$src1), + "rol{w}\t{$src1, $dst|$dst, $src1}", + [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)]>, + OpSize16; +def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, u8imm:$src1), + "rol{l}\t{$src1, $dst|$dst, $src1}", + [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)]>, + OpSize32; +def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, u8imm:$src1), + "rol{q}\t{$src1, $dst|$dst, $src1}", + [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)]>, + Requires<[In64BitMode]>; + +// Rotate by 1 +def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst), + "rol{b}\t{$dst|$dst, 1}", + [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; +def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), + "rol{w}\t{$dst|$dst, 1}", + [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize16; +def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), + "rol{l}\t{$dst|$dst, 1}", + [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize32; +def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst), + "rol{q}\t{$dst|$dst, 1}", + [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW + +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { +let Uses = [CL] in { +def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), + "ror{b}\t{%cl, $dst|$dst, cl}", + [(set GR8:$dst, (rotr GR8:$src1, CL))]>; +def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1), + "ror{w}\t{%cl, $dst|$dst, cl}", + [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize16; +def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1), + "ror{l}\t{%cl, $dst|$dst, cl}", + [(set GR32:$dst, (rotr GR32:$src1, CL))]>, OpSize32; +def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), + "ror{q}\t{%cl, $dst|$dst, cl}", + [(set GR64:$dst, (rotr GR64:$src1, CL))]>; +} + +def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), + "ror{b}\t{$src2, $dst|$dst, $src2}", + [(set GR8:$dst, (rotr GR8:$src1, (i8 relocImm:$src2)))]>; +def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), + "ror{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, (rotr GR16:$src1, (i8 relocImm:$src2)))]>, + OpSize16; +def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), + "ror{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, (rotr GR32:$src1, (i8 relocImm:$src2)))]>, + OpSize32; +def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), + (ins GR64:$src1, u8imm:$src2), + "ror{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, (rotr GR64:$src1, (i8 relocImm:$src2)))]>; + +// Rotate by 1 +def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), + "ror{b}\t{$$1, $dst|$dst, 1}", + [(set GR8:$dst, (rotl GR8:$src1, (i8 7)))]>; +def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), + "ror{w}\t{$$1, $dst|$dst, 1}", + [(set GR16:$dst, (rotl GR16:$src1, (i8 15)))]>, OpSize16; +def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), + "ror{l}\t{$$1, $dst|$dst, 1}", + [(set GR32:$dst, (rotl GR32:$src1, (i8 31)))]>, OpSize32; +def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1), + "ror{q}\t{$$1, $dst|$dst, 1}", + [(set GR64:$dst, (rotl GR64:$src1, (i8 63)))]>; +} // Constraints = "$src = $dst", SchedRW + +let SchedRW = [WriteShiftLd, WriteRMW] in { +let Uses = [CL] in { +def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), + "ror{b}\t{%cl, $dst|$dst, cl}", + [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>; +def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), + "ror{w}\t{%cl, $dst|$dst, cl}", + [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize16; +def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), + "ror{l}\t{%cl, $dst|$dst, cl}", + [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>, OpSize32; +def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst), + "ror{q}\t{%cl, $dst|$dst, cl}", + [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>, + Requires<[In64BitMode]>; +} +def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, u8imm:$src), + "ror{b}\t{$src, $dst|$dst, $src}", + [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; +def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, u8imm:$src), + "ror{w}\t{$src, $dst|$dst, $src}", + [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize16; +def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, u8imm:$src), + "ror{l}\t{$src, $dst|$dst, $src}", + [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize32; +def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, u8imm:$src), + "ror{q}\t{$src, $dst|$dst, $src}", + [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + Requires<[In64BitMode]>; + +// Rotate by 1 +def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), + "ror{b}\t{$dst|$dst, 1}", + [(store (rotl (loadi8 addr:$dst), (i8 7)), addr:$dst)]>; +def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), + "ror{w}\t{$dst|$dst, 1}", + [(store (rotl (loadi16 addr:$dst), (i8 15)), addr:$dst)]>, + OpSize16; +def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), + "ror{l}\t{$dst|$dst, 1}", + [(store (rotl (loadi32 addr:$dst), (i8 31)), addr:$dst)]>, + OpSize32; +def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst), + "ror{q}\t{$dst|$dst, 1}", + [(store (rotl (loadi64 addr:$dst), (i8 63)), addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW + + +//===----------------------------------------------------------------------===// +// Double shift instructions (generalizations of rotate) +//===----------------------------------------------------------------------===// + +let Constraints = "$src1 = $dst" in { + +let Uses = [CL], SchedRW = [WriteSHDrrcl] in { +def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), + (ins GR16:$src1, GR16:$src2), + "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>, + TB, OpSize16; +def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), + (ins GR16:$src1, GR16:$src2), + "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>, + TB, OpSize16; +def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2), + "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, + TB, OpSize32; +def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2), + "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, + TB, OpSize32; +def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), + "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, + TB; +def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), + "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, + TB; +} // SchedRW + +let isCommutable = 1, SchedRW = [WriteSHDrri] in { // These instructions commute to each other. +def SHLD16rri8 : Ii8<0xA4, MRMDestReg, + (outs GR16:$dst), + (ins GR16:$src1, GR16:$src2, u8imm:$src3), + "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, + (i8 imm:$src3)))]>, + TB, OpSize16; +def SHRD16rri8 : Ii8<0xAC, MRMDestReg, + (outs GR16:$dst), + (ins GR16:$src1, GR16:$src2, u8imm:$src3), + "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, + (i8 imm:$src3)))]>, + TB, OpSize16; +def SHLD32rri8 : Ii8<0xA4, MRMDestReg, + (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2, u8imm:$src3), + "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, + (i8 imm:$src3)))]>, + TB, OpSize32; +def SHRD32rri8 : Ii8<0xAC, MRMDestReg, + (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2, u8imm:$src3), + "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, + (i8 imm:$src3)))]>, + TB, OpSize32; +def SHLD64rri8 : RIi8<0xA4, MRMDestReg, + (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2, u8imm:$src3), + "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, + (i8 imm:$src3)))]>, + TB; +def SHRD64rri8 : RIi8<0xAC, MRMDestReg, + (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2, u8imm:$src3), + "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, + (i8 imm:$src3)))]>, + TB; +} // SchedRW +} // Constraints = "$src = $dst" + +let Uses = [CL], SchedRW = [WriteSHDmrcl] in { +def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), + "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), + addr:$dst)]>, TB, OpSize16; +def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), + "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), + addr:$dst)]>, TB, OpSize16; + +def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), + "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), + addr:$dst)]>, TB, OpSize32; +def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), + "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), + addr:$dst)]>, TB, OpSize32; + +def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), + "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL), + addr:$dst)]>, TB; +def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), + "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL), + addr:$dst)]>, TB; +} // SchedRW + +let SchedRW = [WriteSHDmri] in { +def SHLD16mri8 : Ii8<0xA4, MRMDestMem, + (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3), + "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(store (X86shld (loadi16 addr:$dst), GR16:$src2, + (i8 imm:$src3)), addr:$dst)]>, + TB, OpSize16; +def SHRD16mri8 : Ii8<0xAC, MRMDestMem, + (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3), + "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, + (i8 imm:$src3)), addr:$dst)]>, + TB, OpSize16; + +def SHLD32mri8 : Ii8<0xA4, MRMDestMem, + (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3), + "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(store (X86shld (loadi32 addr:$dst), GR32:$src2, + (i8 imm:$src3)), addr:$dst)]>, + TB, OpSize32; +def SHRD32mri8 : Ii8<0xAC, MRMDestMem, + (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3), + "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, + (i8 imm:$src3)), addr:$dst)]>, + TB, OpSize32; + +def SHLD64mri8 : RIi8<0xA4, MRMDestMem, + (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3), + "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(store (X86shld (loadi64 addr:$dst), GR64:$src2, + (i8 imm:$src3)), addr:$dst)]>, + TB; +def SHRD64mri8 : RIi8<0xAC, MRMDestMem, + (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3), + "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, + (i8 imm:$src3)), addr:$dst)]>, + TB; +} // SchedRW + +} // Defs = [EFLAGS] + +// Sandy Bridge and newer Intel processors support faster rotates using +// SHLD to avoid a partial flag update on the normal rotate instructions. +let Predicates = [HasFastSHLDRotate], AddedComplexity = 5 in { + def : Pat<(rotl GR32:$src, (i8 imm:$shamt)), + (SHLD32rri8 GR32:$src, GR32:$src, imm:$shamt)>; + def : Pat<(rotl GR64:$src, (i8 imm:$shamt)), + (SHLD64rri8 GR64:$src, GR64:$src, imm:$shamt)>; +} + +def ROT32L2R_imm8 : SDNodeXFormgetZExtValue(), SDLoc(N)); +}]>; + +def ROT64L2R_imm8 : SDNodeXFormgetZExtValue(), SDLoc(N)); +}]>; + +multiclass bmi_rotate { +let hasSideEffects = 0 in { + def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + []>, TAXD, VEX, Sched<[WriteShift]>; + let mayLoad = 1 in + def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst), + (ins x86memop:$src1, u8imm:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + []>, TAXD, VEX, Sched<[WriteShiftLd]>; +} +} + +multiclass bmi_shift { +let hasSideEffects = 0 in { + def rr : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, + VEX, Sched<[WriteShift]>; + let mayLoad = 1 in + def rm : I<0xF7, MRMSrcMem4VOp3, + (outs RC:$dst), (ins x86memop:$src1, RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, + VEX, Sched<[WriteShiftLd, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + ReadAfterLd]>; +} +} + +let Predicates = [HasBMI2] in { + defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>; + defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W; + defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS; + defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W; + defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD; + defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W; + defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD; + defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, VEX_W; + + // Prefer RORX which is non-destructive and doesn't update EFLAGS. + let AddedComplexity = 10 in { + def : Pat<(rotl GR32:$src, (i8 imm:$shamt)), + (RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>; + def : Pat<(rotl GR64:$src, (i8 imm:$shamt)), + (RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>; + } + + def : Pat<(rotl (loadi32 addr:$src), (i8 imm:$shamt)), + (RORX32mi addr:$src, (ROT32L2R_imm8 imm:$shamt))>; + def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)), + (RORX64mi addr:$src, (ROT64L2R_imm8 imm:$shamt))>; + + // Prefer SARX/SHRX/SHLX over SAR/SHR/SHL with variable shift BUT not + // immedidate shift, i.e. the following code is considered better + // + // mov %edi, %esi + // shl $imm, %esi + // ... %edi, ... + // + // than + // + // movb $imm, %sil + // shlx %sil, %edi, %esi + // ... %edi, ... + // + let AddedComplexity = 1 in { + def : Pat<(sra GR32:$src1, GR8:$src2), + (SARX32rr GR32:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(sra GR64:$src1, GR8:$src2), + (SARX64rr GR64:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(srl GR32:$src1, GR8:$src2), + (SHRX32rr GR32:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(srl GR64:$src1, GR8:$src2), + (SHRX64rr GR64:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(shl GR32:$src1, GR8:$src2), + (SHLX32rr GR32:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(shl GR64:$src1, GR8:$src2), + (SHLX64rr GR64:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + } + + // We prefer to use + // mov (%ecx), %esi + // shl $imm, $esi + // + // over + // + // movb $imm, %al + // shlx %al, (%ecx), %esi + // + // This priority is enforced by IsProfitableToFoldLoad. + def : Pat<(sra (loadi32 addr:$src1), GR8:$src2), + (SARX32rm addr:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(sra (loadi64 addr:$src1), GR8:$src2), + (SARX64rm addr:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(srl (loadi32 addr:$src1), GR8:$src2), + (SHRX32rm addr:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(srl (loadi64 addr:$src1), GR8:$src2), + (SHRX64rm addr:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(shl (loadi32 addr:$src1), GR8:$src2), + (SHLX32rm addr:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(shl (loadi64 addr:$src1), GR8:$src2), + (SHLX64rm addr:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrSystem.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrSystem.td new file mode 100644 index 0000000..5bc58e2 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrSystem.td @@ -0,0 +1,755 @@ +//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 instructions that are generally used in +// privileged modes. These are not typically used by the compiler, but are +// supported for the assembler and disassembler. +// +//===----------------------------------------------------------------------===// + +let SchedRW = [WriteSystem] in { +let Defs = [RAX, RDX] in + def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB; + +let Defs = [RAX, RCX, RDX] in + def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB; + +// CPU flow control instructions + +let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in { + def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; + + def UD1Wm : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2), + "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16; + def UD1Lm : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2), + "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32; + def UD1Qm : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2), + "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB; + + def UD1Wr : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2), + "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16; + def UD1Lr : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2), + "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32; + def UD1Qr : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2), + "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB; +} + +def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>; +def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB; + +// Interrupt and SysCall Instructions. +let Uses = [EFLAGS] in + def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>; + +def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>; +} // SchedRW + +// The long form of "int $3" turns into int3 as a size optimization. +// FIXME: This doesn't work because InstAlias can't match immediate constants. +//// def : InstAlias<"int\t$3", (INT3)>; + +let SchedRW = [WriteSystem] in { + +def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap", + [(int_x86_int imm:$trap)]>; + + +def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB; +def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB; +def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB, + Requires<[In64BitMode]>; + +def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB; + +def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB; +def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB, + Requires<[In64BitMode]>; +} // SchedRW + +def : Pat<(debugtrap), + (INT3)>, Requires<[NotPS4]>; +def : Pat<(debugtrap), + (INT (i8 0x41))>, Requires<[IsPS4]>; + +//===----------------------------------------------------------------------===// +// Input/Output Instructions. +// +let SchedRW = [WriteSystem] in { +let Defs = [AL], Uses = [DX] in +def IN8rr : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>; +let Defs = [AX], Uses = [DX] in +def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>, + OpSize16; +let Defs = [EAX], Uses = [DX] in +def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>, + OpSize32; + +let Defs = [AL] in +def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port), + "in{b}\t{$port, %al|al, $port}", []>; +let Defs = [AX] in +def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port), + "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16; +let Defs = [EAX] in +def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port), + "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32; + +let Uses = [DX, AL] in +def OUT8rr : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>; +let Uses = [DX, AX] in +def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>, + OpSize16; +let Uses = [DX, EAX] in +def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>, + OpSize32; + +let Uses = [AL] in +def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port), + "out{b}\t{%al, $port|$port, al}", []>; +let Uses = [AX] in +def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port), + "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16; +let Uses = [EAX] in +def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port), + "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32; + +} // SchedRW + +//===----------------------------------------------------------------------===// +// Moves to and from debug registers + +let SchedRW = [WriteSystem] in { +def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[Not64BitMode]>; +def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[In64BitMode]>; + +def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[Not64BitMode]>; +def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Moves to and from control registers + +let SchedRW = [WriteSystem] in { +def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[Not64BitMode]>; +def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[In64BitMode]>; + +def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[Not64BitMode]>; +def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Segment override instruction prefixes + +//let SchedRW = [WriteNop] in { +//def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>; +//def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>; +//def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>; +//def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>; +//def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>; +//def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>; +//} // SchedRW + +//===----------------------------------------------------------------------===// +// Moves to and from segment registers. +// + +let SchedRW = [WriteMove] in { +def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; +def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; +def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>; +let mayStore = 1 in { +def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>; +} +def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; +def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; +def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>; +let mayLoad = 1 in { +def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>; +} +} // SchedRW + +//===----------------------------------------------------------------------===// +// Segmentation support instructions. + +let SchedRW = [WriteSystem] in { +def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB; + +let mayLoad = 1 in +def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize16, NotMemoryFoldable; +def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize16, NotMemoryFoldable; + +// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo. +let mayLoad = 1 in +def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), + "lar{l}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize32, NotMemoryFoldable; +def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "lar{l}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize32, NotMemoryFoldable; +// i16mem operand in LAR64rm and GR32 operand in LAR64rr is not a typo. +let mayLoad = 1 in +def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), + "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; +def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), + "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; + +// i16mem operand in LSL32rm and GR32 operand in LSL32rr is not a typo. +let mayLoad = 1 in +def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize16, NotMemoryFoldable; +def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize16, NotMemoryFoldable; +// i16mem operand in LSL64rm and GR32 operand in LSL64rr is not a typo. +let mayLoad = 1 in +def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), + "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize32, NotMemoryFoldable; +def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize32, NotMemoryFoldable; +let mayLoad = 1 in +def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), + "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; +def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), + "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; + +def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB; + +def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins), + "str{w}\t$dst", []>, TB, OpSize16; +def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins), + "str{l}\t$dst", []>, TB, OpSize32; +def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins), + "str{q}\t$dst", []>, TB; +let mayStore = 1 in +def STRm : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB; + +def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable; +let mayLoad = 1 in +def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable; + +def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>, + OpSize16, Requires<[Not64BitMode]>; +def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>, + OpSize32, Requires<[Not64BitMode]>; +def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>, + OpSize16, Requires<[Not64BitMode]>; +def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>, + OpSize32, Requires<[Not64BitMode]>; +def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>, + OpSize16, Requires<[Not64BitMode]>; +def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>, + OpSize32, Requires<[Not64BitMode]>; +def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>, + OpSize16, Requires<[Not64BitMode]>; +def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>, + OpSize32, Requires<[Not64BitMode]>; +def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>, + OpSize16, TB; +def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB, + OpSize32, Requires<[Not64BitMode]>; +def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>, + OpSize16, TB; +def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB, + OpSize32, Requires<[Not64BitMode]>; +def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB, + OpSize32, Requires<[In64BitMode]>; +def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB, + OpSize32, Requires<[In64BitMode]>; + +// No "pop cs" instruction. +def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>, + OpSize16, Requires<[Not64BitMode]>; +def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>, + OpSize32, Requires<[Not64BitMode]>; + +def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>, + OpSize16, Requires<[Not64BitMode]>; +def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>, + OpSize32, Requires<[Not64BitMode]>; + +def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>, + OpSize16, Requires<[Not64BitMode]>; +def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>, + OpSize32, Requires<[Not64BitMode]>; + +def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>, + OpSize16, TB; +def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB, + OpSize32, Requires<[Not64BitMode]>; +def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB, + OpSize32, Requires<[In64BitMode]>; + +def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>, + OpSize16, TB; +def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB, + OpSize32, Requires<[Not64BitMode]>; +def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB, + OpSize32, Requires<[In64BitMode]>; + +def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), + "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, + Requires<[Not64BitMode]>; +def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), + "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, + Requires<[Not64BitMode]>; + +def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), + "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; +def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), + "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; +def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), + "lss{q}\t{$src, $dst|$dst, $src}", []>, TB; + +def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), + "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, + Requires<[Not64BitMode]>; +def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), + "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, + Requires<[Not64BitMode]>; + +def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), + "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; +def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), + "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; +def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), + "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB; + +def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), + "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; +def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), + "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; + +def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), + "lgs\t{$src, $dst|$dst, $src}", []>, TB; + +def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable; +def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable; +let mayLoad = 1 in { +def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable; +def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable; +} +} // SchedRW + +//===----------------------------------------------------------------------===// +// Descriptor-table support instructions + +let SchedRW = [WriteSystem] in { +def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), + "sgdt{w}\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; +def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), + "sgdt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; +def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), + "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; +def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), + "sidt{w}\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; +def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), + "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; +def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), + "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; +def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins), + "sldt{w}\t$dst", []>, TB, OpSize16; +let mayStore = 1 in +def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst), + "sldt{w}\t$dst", []>, TB; +def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins), + "sldt{l}\t$dst", []>, OpSize32, TB; + +// LLDT is not interpreted specially in 64-bit mode because there is no sign +// extension. +def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins), + "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>; + +def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), + "lgdt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; +def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), + "lgdt{l}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; +def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), + "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>; +def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), + "lidt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; +def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), + "lidt{l}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; +def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), + "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>; +def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src), + "lldt{w}\t$src", []>, TB, NotMemoryFoldable; +let mayLoad = 1 in +def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src), + "lldt{w}\t$src", []>, TB, NotMemoryFoldable; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Specialized register support +let SchedRW = [WriteSystem] in { +let Uses = [EAX, ECX, EDX] in +def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB; +let Defs = [EAX, EDX], Uses = [ECX] in +def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB; + +let Defs = [RAX, RDX], Uses = [ECX] in + def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)]>, TB; + +def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins), + "smsw{w}\t$dst", []>, OpSize16, TB; +def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins), + "smsw{l}\t$dst", []>, OpSize32, TB; +// no m form encodable; use SMSW16m +def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins), + "smsw{q}\t$dst", []>, TB; + +// For memory operands, there is only a 16-bit form +def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst), + "smsw{w}\t$dst", []>, TB; + +def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src), + "lmsw{w}\t$src", []>, TB, NotMemoryFoldable; +let mayLoad = 1 in +def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src), + "lmsw{w}\t$src", []>, TB, NotMemoryFoldable; + +let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in + def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Cache instructions +let SchedRW = [WriteSystem] in { +def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB; +def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, TB; + +// wbnoinvd is like wbinvd, except without invalidation +// encoding: like wbinvd + an 0xF3 prefix +def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd", + [(int_x86_wbnoinvd)]>, XS, + Requires<[HasWBNOINVD]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// CET instructions +// Use with caution, availability is not predicated on features. +let SchedRW = [WriteSystem] in { + let Uses = [SSP] in { + let Defs = [SSP] in { + def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src", + [(int_x86_incsspd GR32:$src)]>, XS; + def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src", + [(int_x86_incsspq GR64:$src)]>, XS; + } // Defs SSP + + let Constraints = "$src = $dst" in { + def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src), + "rdsspd\t$dst", + [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS; + def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src), + "rdsspq\t$dst", + [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS; + } + + let Defs = [SSP] in { + def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp", + [(int_x86_saveprevssp)]>, XS; + def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src), + "rstorssp\t$src", + [(int_x86_rstorssp addr:$src)]>, XS; + } // Defs SSP + } // Uses SSP + + def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "wrssd\t{$src, $dst|$dst, $src}", + [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS; + def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "wrssq\t{$src, $dst|$dst, $src}", + [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS; + def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "wrussd\t{$src, $dst|$dst, $src}", + [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD; + def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "wrussq\t{$src, $dst|$dst, $src}", + [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD; + + let Defs = [SSP] in { + let Uses = [SSP] in { + def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy", + [(int_x86_setssbsy)]>, XS; + } // Uses SSP + + def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src), + "clrssbsy\t$src", + [(int_x86_clrssbsy addr:$src)]>, XS; + } // Defs SSP +} // SchedRW + +let SchedRW = [WriteSystem] in { + def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS; + def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS; +} // SchedRW + +//===----------------------------------------------------------------------===// +// XSAVE instructions +let SchedRW = [WriteSystem] in { +let Predicates = [HasXSAVE] in { +let Defs = [EDX, EAX], Uses = [ECX] in + def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB; + +let Uses = [EDX, EAX, ECX] in + def XSETBV : I<0x01, MRM_D1, (outs), (ins), + "xsetbv", + [(int_x86_xsetbv ECX, EDX, EAX)]>, TB; + +} // HasXSAVE + +let Uses = [EDX, EAX] in { +def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst), + "xsave\t$dst", + [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>; +def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst), + "xsave64\t$dst", + [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; +def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst), + "xrstor\t$dst", + [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>; +def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst), + "xrstor64\t$dst", + [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; +def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst), + "xsaveopt\t$dst", + [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>; +def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst), + "xsaveopt64\t$dst", + [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>; +def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst), + "xsavec\t$dst", + [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>; +def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst), + "xsavec64\t$dst", + [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>; +def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst), + "xsaves\t$dst", + [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>; +def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst), + "xsaves64\t$dst", + [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>; +def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst), + "xrstors\t$dst", + [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>; +def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst), + "xrstors64\t$dst", + [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>; +} // Uses +} // SchedRW + +//===----------------------------------------------------------------------===// +// VIA PadLock crypto instructions +let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in + def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB; + +// def : InstAlias<"xstorerng", (XSTORE)>; + +let SchedRW = [WriteSystem] in { +let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in { + def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB; + def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB; + def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB; + def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB; + def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB; +} + +let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in { + def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB; + def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB; +} +let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in + def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB; +} // SchedRW + +/* +//==-----------------------------------------------------------------------===// +// PKU - enable protection key +let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { + def WRPKRU : PseudoI<(outs), (ins GR32:$src), + [(int_x86_wrpkru GR32:$src)]>; + def RDPKRU : PseudoI<(outs GR32:$dst), (ins), + [(set GR32:$dst, (int_x86_rdpkru))]>; +} +*/ + +let SchedRW = [WriteSystem] in { +let Defs = [EAX, EDX], Uses = [ECX] in + def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", []>, TB; +let Uses = [EAX, ECX, EDX] in + def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", []>, TB; +} // SchedRW + +//===----------------------------------------------------------------------===// +// FS/GS Base Instructions +let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in { + def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins), + "rdfsbase{l}\t$dst", + [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS; + def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins), + "rdfsbase{q}\t$dst", + [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS; + def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), + "rdgsbase{l}\t$dst", + [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS; + def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins), + "rdgsbase{q}\t$dst", + [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS; + def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src), + "wrfsbase{l}\t$src", + [(int_x86_wrfsbase_32 GR32:$src)]>, XS; + def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src), + "wrfsbase{q}\t$src", + [(int_x86_wrfsbase_64 GR64:$src)]>, XS; + def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src), + "wrgsbase{l}\t$src", + [(int_x86_wrgsbase_32 GR32:$src)]>, XS; + def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src), + "wrgsbase{q}\t$src", + [(int_x86_wrgsbase_64 GR64:$src)]>, XS; +} + +//===----------------------------------------------------------------------===// +// INVPCID Instruction +let SchedRW = [WriteSystem] in { +def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), + "invpcid\t{$src2, $src1|$src1, $src2}", + [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8PD, + Requires<[Not64BitMode, HasINVPCID]>; +def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), + "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD, + Requires<[In64BitMode, HasINVPCID]>; +} // SchedRW + +let Predicates = [In64BitMode, HasINVPCID] in { + // The instruction can only use a 64 bit register as the register argument + // in 64 bit mode, while the intrinsic only accepts a 32 bit argument + // corresponding to it. + // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID + // type),/ so it doesn't hurt us that one can't supply a 64 bit value here. + def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2), + (INVPCID64 + (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit), + addr:$src2)>; +} + + +//===----------------------------------------------------------------------===// +// SMAP Instruction +let Defs = [EFLAGS], SchedRW = [WriteSystem] in { + def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB; + def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB; +} + +//===----------------------------------------------------------------------===// +// SMX Instruction +let SchedRW = [WriteSystem] in { +let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in { + def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB; +} // Uses, Defs +} // SchedRW + +//===----------------------------------------------------------------------===// +// TS flag control instruction. +let SchedRW = [WriteSystem] in { +def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB; +} + +//===----------------------------------------------------------------------===// +// IF (inside EFLAGS) management instructions. +let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in { +def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>; +def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>; +} + +//===----------------------------------------------------------------------===// +// RDPID Instruction +let SchedRW = [WriteSystem] in { +def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins), + "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, XS, + Requires<[Not64BitMode, HasRDPID]>; +def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS, + Requires<[In64BitMode, HasRDPID]>; +} // SchedRW + +let Predicates = [In64BitMode, HasRDPID] in { + // Due to silly instruction definition, we have to compensate for the + // instruction outputting a 64-bit register. + def : Pat<(int_x86_rdpid), + (EXTRACT_SUBREG (RDPID64), sub_32bit)>; +} + + +//===----------------------------------------------------------------------===// +// PTWRITE Instruction - Write Data to a Processor Trace Packet +let SchedRW = [WriteSystem] in { +def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst), + "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS, + Requires<[HasPTWRITE]>; +def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst), + "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS, + Requires<[In64BitMode, HasPTWRITE]>; + +def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst), + "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS, + Requires<[HasPTWRITE]>; +def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst), + "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS, + Requires<[In64BitMode, HasPTWRITE]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Platform Configuration instruction + +// From ISA docs: +// "This instruction is used to execute functions for configuring platform +// features. +// EAX: Leaf function to be invoked. +// RBX/RCX/RDX: Leaf-specific purpose." +// "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF, +// AF, OF, and SF are cleared. In case of failure, the failure reason is +// indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared." +// Thus all these mentioned registers are considered clobbered. + +let SchedRW = [WriteSystem] in { +let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in + def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB, + Requires<[HasPCONFIG]>; +} // SchedRW diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrTSX.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrTSX.td new file mode 100644 index 0000000..8b9f723 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrTSX.td @@ -0,0 +1,60 @@ +//===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the Intel TSX instruction +// set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// TSX instructions + +def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +let SchedRW = [WriteSystem] in { + +//let usesCustomInserter = 1 in +//def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins), +// "# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>, +// Requires<[HasRTM]>; + +let isBranch = 1, isTerminator = 1, Defs = [EAX] in { +def XBEGIN_2 : Ii16PCRel<0xc7, MRM_F8, (outs), (ins brtarget16:$dst), + "xbegin\t$dst", []>, OpSize16; +def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst), + "xbegin\t$dst", []>, OpSize32; +} + +// Pseudo instruction to fake the definition of EAX on the fallback code path. +//let isPseudo = 1, Defs = [EAX] in { +//def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>; +//} + +def XEND : I<0x01, MRM_D5, (outs), (ins), + "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>; + +let Defs = [EFLAGS] in +def XTEST : I<0x01, MRM_D6, (outs), (ins), + "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasRTM]>; + +def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm), + "xabort\t$imm", + [(int_x86_xabort imm:$imm)]>, Requires<[HasRTM]>; +} // SchedRW + +// HLE prefixes +let SchedRW = [WriteSystem] in { + +let isAsmParserOnly = 1 in { +def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>; +def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>; +} + +} // SchedRW diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrVMX.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrVMX.td new file mode 100644 index 0000000..06a438e --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrVMX.td @@ -0,0 +1,88 @@ +//===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the Intel VMX instruction +// set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// VMX instructions + +let SchedRW = [WriteSystem] in { +// 66 0F 38 80 +def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), + "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD, + Requires<[Not64BitMode]>; +def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), + "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD, + Requires<[In64BitMode]>; + +// 66 0F 38 81 +def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), + "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD, + Requires<[Not64BitMode]>; +def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), + "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD, + Requires<[In64BitMode]>; + +// 0F 01 C1 +def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB; +def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), + "vmclear\t$vmcs", []>, PD; + +// OF 01 D4 +def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB; + +// 0F 01 C2 +def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB; + +// 0F 01 C3 +def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB; +def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), + "vmptrld\t$vmcs", []>, PS; +def VMPTRSTm : I<0xC7, MRM7m, (outs), (ins i64mem:$vmcs), + "vmptrst\t$vmcs", []>, PS; +def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), + "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>, + NotMemoryFoldable; +def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), + "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>, + NotMemoryFoldable; + +let mayStore = 1 in { +def VMREAD64mr : I<0x78, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>, + NotMemoryFoldable; +def VMREAD32mr : I<0x78, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>, + NotMemoryFoldable; +} // mayStore + +def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>, + NotMemoryFoldable; +def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>, + NotMemoryFoldable; + +let mayLoad = 1 in { +def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>, + NotMemoryFoldable; +def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>, + NotMemoryFoldable; +} // mayLoad + +// 0F 01 C4 +def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB; +def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon), + "vmxon\t$vmxon", []>, XS; +} // SchedRW diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrVecCompiler.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrVecCompiler.td new file mode 100644 index 0000000..322bdb7 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrVecCompiler.td @@ -0,0 +1,511 @@ +//===- X86InstrVecCompiler.td - Vector Compiler Patterns ---*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the various vector pseudo instructions used by the +// compiler, as well as Pat patterns used during instruction selection. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// No op bitconverts +//===----------------------------------------------------------------------===// + +// Bitcasts between 128-bit vector types. Return the original type since +// no instruction is needed for the conversion +def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; +def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; +def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; +def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; +def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; +def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; +def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; +def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; +def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; +def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; +def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; +def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; +def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; +def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; +def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; +def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; +def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; +def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; +def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; +def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; +def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; +def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; +def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; +def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; +def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; +def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; +def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; +def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; +def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; +def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; + +// Bitcasts between 256-bit vector types. Return the original type since +// no instruction is needed for the conversion +def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>; +def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>; +def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>; +def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>; +def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>; +def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>; +def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>; +def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>; +def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>; +def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>; +def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>; +def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>; +def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>; +def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>; +def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>; +def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>; +def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>; +def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>; +def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>; +def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>; +def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>; +def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>; +def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>; +def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>; +def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>; +def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>; +def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>; +def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>; +def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>; +def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>; + +// Bitcasts between 512-bit vector types. Return the original type since +// no instruction is needed for the conversion. +def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>; +def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>; +def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>; +def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>; +def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>; +def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>; +def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>; +def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>; +def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>; +def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>; +def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>; +def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>; +def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>; +def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>; +def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>; +def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>; +def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>; +def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>; +def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>; +def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>; +def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>; +def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>; +def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>; +def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>; +def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>; +def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>; +def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>; +def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>; +def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>; +def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>; + + +//===----------------------------------------------------------------------===// +// Non-instruction patterns +//===----------------------------------------------------------------------===// + +// A vector extract of the first f32/f64 position is a subregister copy +def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))), + (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>; +def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))), + (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>; + +// Implicitly promote a 32-bit scalar to a vector. +def : Pat<(v4f32 (scalar_to_vector FR32:$src)), + (COPY_TO_REGCLASS FR32:$src, VR128)>; +// Implicitly promote a 64-bit scalar to a vector. +def : Pat<(v2f64 (scalar_to_vector FR64:$src)), + (COPY_TO_REGCLASS FR64:$src, VR128)>; + + +//===----------------------------------------------------------------------===// +// Subvector tricks +//===----------------------------------------------------------------------===// + +// Patterns for insert_subvector/extract_subvector to/from index=0 +multiclass subvector_subreg_lowering { + def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))), + (subVT (EXTRACT_SUBREG RC:$src, subIdx))>; + + def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))), + (VT (INSERT_SUBREG (IMPLICIT_DEF), subRC:$src, subIdx))>; +} + +// A 128-bit subvector extract from the first 256-bit vector position is a +// subregister copy that needs no instruction. Likewise, a 128-bit subvector +// insert to the first 256-bit vector position is a subregister copy that needs +// no instruction. +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; + +// A 128-bit subvector extract from the first 512-bit vector position is a +// subregister copy that needs no instruction. Likewise, a 128-bit subvector +// insert to the first 512-bit vector position is a subregister copy that needs +// no instruction. +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; + +// A 128-bit subvector extract from the first 512-bit vector position is a +// subregister copy that needs no instruction. Likewise, a 128-bit subvector +// insert to the first 512-bit vector position is a subregister copy that needs +// no instruction. +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; + + +multiclass subvector_store_lowering { + def : Pat<(alignedstore (DstTy (extract_subvector + (SrcTy RC:$src), (iPTR 0))), addr:$dst), + (!cast("VMOV"#AlignedStr#"mr") addr:$dst, + (DstTy (EXTRACT_SUBREG RC:$src, SubIdx)))>; + + def : Pat<(store (DstTy (extract_subvector + (SrcTy RC:$src), (iPTR 0))), addr:$dst), + (!cast("VMOV"#UnalignedStr#"mr") addr:$dst, + (DstTy (EXTRACT_SUBREG RC:$src, SubIdx)))>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm : subvector_store_lowering<"APD", "UPD", VR256X, v2f64, v4f64, sub_xmm>; + defm : subvector_store_lowering<"APS", "UPS", VR256X, v4f32, v8f32, sub_xmm>; + defm : subvector_store_lowering<"DQA", "DQU", VR256X, v2i64, v4i64, sub_xmm>; + defm : subvector_store_lowering<"DQA", "DQU", VR256X, v4i32, v8i32, sub_xmm>; + defm : subvector_store_lowering<"DQA", "DQU", VR256X, v8i16, v16i16, sub_xmm>; + defm : subvector_store_lowering<"DQA", "DQU", VR256X, v16i8, v32i8, sub_xmm>; +} + +let Predicates = [HasVLX] in { + // Special patterns for storing subvector extracts of lower 128-bits + // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr + defm : subvector_store_lowering<"APDZ128", "UPDZ128", VR256X, v2f64, v4f64, + sub_xmm>; + defm : subvector_store_lowering<"APSZ128", "UPSZ128", VR256X, v4f32, v8f32, + sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR256X, v2i64, + v4i64, sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR256X, v4i32, + v8i32, sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR256X, v8i16, + v16i16, sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR256X, v16i8, + v32i8, sub_xmm>; + + // Special patterns for storing subvector extracts of lower 128-bits of 512. + // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr + defm : subvector_store_lowering<"APDZ128", "UPDZ128", VR512, v2f64, v8f64, + sub_xmm>; + defm : subvector_store_lowering<"APSZ128", "UPSZ128", VR512, v4f32, v16f32, + sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR512, v2i64, + v8i64, sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR512, v4i32, + v16i32, sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR512, v8i16, + v32i16, sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR512, v16i8, + v64i8, sub_xmm>; + + // Special patterns for storing subvector extracts of lower 256-bits of 512. + // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr + defm : subvector_store_lowering<"APDZ256", "UPDZ256", VR512, v4f64, v8f64, + sub_ymm>; + defm : subvector_store_lowering<"APSZ256", "UPSZ256", VR512, v8f32, v16f32, + sub_ymm>; + defm : subvector_store_lowering<"DQA64Z256", "DQU64Z256", VR512, v4i64, + v8i64, sub_ymm>; + defm : subvector_store_lowering<"DQA64Z256", "DQU64Z256", VR512, v8i32, + v16i32, sub_ymm>; + defm : subvector_store_lowering<"DQA64Z256", "DQU64Z256", VR512, v16i16, + v32i16, sub_ymm>; + defm : subvector_store_lowering<"DQA64Z256", "DQU64Z256", VR512, v32i8, + v64i8, sub_ymm>; +} + +// If we're inserting into an all zeros vector, just use a plain move which +// will zero the upper bits. A post-isel hook will take care of removing +// any moves that we can prove are unnecessary. +multiclass subvec_zero_lowering { + def : Pat<(DstTy (insert_subvector (bitconvert (ZeroTy immAllZerosV)), + (SrcTy RC:$src), (iPTR 0))), + (SUBREG_TO_REG (i64 0), + (SrcTy (!cast("VMOV"#MoveStr#"rr") RC:$src)), SubIdx)>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm : subvec_zero_lowering<"APD", VR128, v4f64, v2f64, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"APS", VR128, v8f32, v4f32, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v4i64, v2i64, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v8i32, v4i32, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v16i16, v8i16, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v32i8, v16i8, v8i32, sub_xmm>; +} + +let Predicates = [HasVLX] in { + defm : subvec_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v4i64, v2i64, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i32, v4i32, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i16, v8i16, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i8, v16i8, v8i32, sub_xmm>; + + defm : subvec_zero_lowering<"APDZ128", VR128X, v8f64, v2f64, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i32, v4i32, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i16, v8i16, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, v16i32, sub_xmm>; + + defm : subvec_zero_lowering<"APDZ256", VR256X, v8f64, v4f64, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQA64Z256", VR256X, v16i32, v8i32, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQA64Z256", VR256X, v32i16, v16i16, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, v16i32, sub_ymm>; +} + +let Predicates = [HasAVX512, NoVLX] in { + defm : subvec_zero_lowering<"APD", VR128, v8f64, v2f64, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"APS", VR128, v16f32, v4f32, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v8i64, v2i64, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v16i32, v4i32, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v32i16, v8i16, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v64i8, v16i8, v16i32, sub_xmm>; + + defm : subvec_zero_lowering<"APDY", VR256, v8f64, v4f64, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"APSY", VR256, v16f32, v8f32, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQAY", VR256, v8i64, v4i64, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQAY", VR256, v16i32, v8i32, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQAY", VR256, v32i16, v16i16, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQAY", VR256, v64i8, v32i8, v16i32, sub_ymm>; +} + +class maskzeroupper : + PatLeaf<(vt RC:$src), [{ + return isMaskZeroExtended(N); + }]>; + +def maskzeroupperv1i1 : maskzeroupper; +def maskzeroupperv2i1 : maskzeroupper; +def maskzeroupperv4i1 : maskzeroupper; +def maskzeroupperv8i1 : maskzeroupper; +def maskzeroupperv16i1 : maskzeroupper; +def maskzeroupperv32i1 : maskzeroupper; + +// The patterns determine if we can depend on the upper bits of a mask register +// being zeroed by the previous operation so that we can skip explicit +// zeroing. +let Predicates = [HasBWI] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + maskzeroupperv1i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK1:$src, VK32)>; + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + maskzeroupperv8i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK8:$src, VK32)>; + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + maskzeroupperv16i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK16:$src, VK32)>; + + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + maskzeroupperv1i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK1:$src, VK64)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + maskzeroupperv8i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK8:$src, VK64)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + maskzeroupperv16i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK16:$src, VK64)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + maskzeroupperv32i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK32:$src, VK64)>; +} + +let Predicates = [HasAVX512] in { + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + maskzeroupperv1i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK1:$src, VK16)>; + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + maskzeroupperv8i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK8:$src, VK16)>; +} + +let Predicates = [HasDQI] in { + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + maskzeroupperv1i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK1:$src, VK8)>; +} + +let Predicates = [HasVLX, HasDQI] in { + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + maskzeroupperv2i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK2:$src, VK8)>; + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + maskzeroupperv4i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK4:$src, VK8)>; +} + +let Predicates = [HasVLX] in { + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + maskzeroupperv2i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK2:$src, VK16)>; + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + maskzeroupperv4i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK4:$src, VK16)>; +} + +let Predicates = [HasBWI, HasVLX] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + maskzeroupperv2i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK2:$src, VK32)>; + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + maskzeroupperv4i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK4:$src, VK32)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + maskzeroupperv2i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK2:$src, VK64)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + maskzeroupperv4i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK4:$src, VK64)>; +} + +// If the bits are not zero we have to fall back to explicitly zeroing by +// using shifts. +let Predicates = [HasAVX512] in { + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + (v1i1 VK1:$mask), (iPTR 0))), + (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK1:$mask, VK16), + (i8 15)), (i8 15))>; + + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + (v2i1 VK2:$mask), (iPTR 0))), + (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK2:$mask, VK16), + (i8 14)), (i8 14))>; + + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + (v4i1 VK4:$mask), (iPTR 0))), + (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK4:$mask, VK16), + (i8 12)), (i8 12))>; +} + +let Predicates = [HasAVX512, NoDQI] in { + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK8:$mask, VK16), + (i8 8)), (i8 8))>; +} + +let Predicates = [HasDQI] in { + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK16)>; + + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + (v1i1 VK1:$mask), (iPTR 0))), + (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK1:$mask, VK8), + (i8 7)), (i8 7))>; + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + (v2i1 VK2:$mask), (iPTR 0))), + (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK2:$mask, VK8), + (i8 6)), (i8 6))>; + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + (v4i1 VK4:$mask), (iPTR 0))), + (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK4:$mask, VK8), + (i8 4)), (i8 4))>; +} + +let Predicates = [HasBWI] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v16i1 VK16:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK32)>; + + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v16i1 VK16:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK64)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v32i1 VK32:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVDkk VK32:$mask), VK64)>; +} + +let Predicates = [HasBWI, NoDQI] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK8:$mask, VK32), + (i8 24)), (i8 24))>; + + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK8:$mask, VK64), + (i8 56)), (i8 56))>; +} + +let Predicates = [HasBWI, HasDQI] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK32)>; + + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK64)>; +} + +let Predicates = [HasBWI, HasVLX] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v1i1 VK1:$mask), (iPTR 0))), + (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK1:$mask, VK32), + (i8 31)), (i8 31))>; + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v2i1 VK2:$mask), (iPTR 0))), + (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK2:$mask, VK32), + (i8 30)), (i8 30))>; + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v4i1 VK4:$mask), (iPTR 0))), + (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK4:$mask, VK32), + (i8 28)), (i8 28))>; + + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v1i1 VK1:$mask), (iPTR 0))), + (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK1:$mask, VK64), + (i8 63)), (i8 63))>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v2i1 VK2:$mask), (iPTR 0))), + (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK2:$mask, VK64), + (i8 62)), (i8 62))>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v4i1 VK4:$mask), (iPTR 0))), + (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK4:$mask, VK64), + (i8 60)), (i8 60))>; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrXOP.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrXOP.td new file mode 100644 index 0000000..ff3e3be --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86InstrXOP.td @@ -0,0 +1,446 @@ +//===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes XOP (eXtended OPerations) +// +//===----------------------------------------------------------------------===// + +multiclass xop2op opc, string OpcodeStr, Intrinsic Int, PatFrag memop> { + def rr : IXOP, XOP, Sched<[SchedWritePHAdd.XMM]>; + def rm : IXOP, XOP, + Sched<[SchedWritePHAdd.XMM.Folded, ReadAfterLd]>; +} + +let ExeDomain = SSEPackedInt in { + defm VPHSUBWD : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, loadv2i64>; + defm VPHSUBDQ : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, loadv2i64>; + defm VPHSUBBW : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, loadv2i64>; + defm VPHADDWQ : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, loadv2i64>; + defm VPHADDWD : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, loadv2i64>; + defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, loadv2i64>; + defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, loadv2i64>; + defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, loadv2i64>; + defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, loadv2i64>; + defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, loadv2i64>; + defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, loadv2i64>; + defm VPHADDDQ : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, loadv2i64>; + defm VPHADDBW : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, loadv2i64>; + defm VPHADDBQ : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, loadv2i64>; + defm VPHADDBD : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, loadv2i64>; +} + +// Scalar load 2 addr operand instructions +multiclass xop2opsld opc, string OpcodeStr, Intrinsic Int, + Operand memop, ComplexPattern mem_cpat, + X86FoldableSchedWrite sched> { + def rr : IXOP, XOP, Sched<[sched]>; + def rm : IXOP, XOP, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass xop2op128 opc, string OpcodeStr, Intrinsic Int, + PatFrag memop, X86FoldableSchedWrite sched> { + def rr : IXOP, XOP, Sched<[sched]>; + def rm : IXOP, XOP, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass xop2op256 opc, string OpcodeStr, Intrinsic Int, + PatFrag memop, X86FoldableSchedWrite sched> { + def Yrr : IXOP, XOP, VEX_L, Sched<[sched]>; + def Yrm : IXOP, XOP, VEX_L, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let ExeDomain = SSEPackedSingle in { + defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss, + ssmem, sse_load_f32, SchedWriteFRnd.Scl>; + defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, loadv4f32, + SchedWriteFRnd.XMM>; + defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256, loadv8f32, + SchedWriteFRnd.YMM>; +} + +let ExeDomain = SSEPackedDouble in { + defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd, + sdmem, sse_load_f64, SchedWriteFRnd.Scl>; + defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, loadv2f64, + SchedWriteFRnd.XMM>; + defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256, loadv4f64, + SchedWriteFRnd.YMM>; +} + +multiclass xop3op opc, string OpcodeStr, SDNode OpNode, + ValueType vt128, X86FoldableSchedWrite sched> { + def rr : IXOP, + XOP, Sched<[sched]>; + def rm : IXOP, + XOP_4V, VEX_W, Sched<[sched.Folded, ReadAfterLd]>; + def mr : IXOP, + XOP, Sched<[sched.Folded, ReadAfterLd]>; + // For disassembler + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rr_REV : IXOP, + XOP_4V, VEX_W, Sched<[sched]>, FoldGenData; +} + +let ExeDomain = SSEPackedInt in { + defm VPROTB : xop3op<0x90, "vprotb", rotl, v16i8, SchedWriteVarVecShift.XMM>; + defm VPROTD : xop3op<0x92, "vprotd", rotl, v4i32, SchedWriteVarVecShift.XMM>; + defm VPROTQ : xop3op<0x93, "vprotq", rotl, v2i64, SchedWriteVarVecShift.XMM>; + defm VPROTW : xop3op<0x91, "vprotw", rotl, v8i16, SchedWriteVarVecShift.XMM>; + defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8, SchedWriteVarVecShift.XMM>; + defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32, SchedWriteVarVecShift.XMM>; + defm VPSHAQ : xop3op<0x9B, "vpshaq", X86vpsha, v2i64, SchedWriteVarVecShift.XMM>; + defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16, SchedWriteVarVecShift.XMM>; + defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8, SchedWriteVarVecShift.XMM>; + defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32, SchedWriteVarVecShift.XMM>; + defm VPSHLQ : xop3op<0x97, "vpshlq", X86vpshl, v2i64, SchedWriteVarVecShift.XMM>; + defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16, SchedWriteVarVecShift.XMM>; +} + +multiclass xop3opimm opc, string OpcodeStr, SDNode OpNode, + ValueType vt128, X86FoldableSchedWrite sched> { + def ri : IXOPi8, + XOP, Sched<[sched]>; + def mi : IXOPi8, + XOP, Sched<[sched.Folded, ReadAfterLd]>; +} + +let ExeDomain = SSEPackedInt in { + defm VPROTB : xop3opimm<0xC0, "vprotb", X86vrotli, v16i8, + SchedWriteVecShiftImm.XMM>; + defm VPROTD : xop3opimm<0xC2, "vprotd", X86vrotli, v4i32, + SchedWriteVecShiftImm.XMM>; + defm VPROTQ : xop3opimm<0xC3, "vprotq", X86vrotli, v2i64, + SchedWriteVecShiftImm.XMM>; + defm VPROTW : xop3opimm<0xC1, "vprotw", X86vrotli, v8i16, + SchedWriteVecShiftImm.XMM>; +} + +// Instruction where second source can be memory, but third must be register +multiclass xop4opm2 opc, string OpcodeStr, Intrinsic Int, + X86FoldableSchedWrite sched> { + let isCommutable = 1 in + def rr : IXOPi8Reg, XOP_4V, + Sched<[sched]>; + def rm : IXOPi8Reg, XOP_4V, Sched<[sched.Folded, ReadAfterLd]>; +} + +let ExeDomain = SSEPackedInt in { + defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd", + int_x86_xop_vpmadcswd, SchedWriteVecIMul.XMM>; + defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", + int_x86_xop_vpmadcsswd, SchedWriteVecIMul.XMM>; + defm VPMACSWW : xop4opm2<0x95, "vpmacsww", + int_x86_xop_vpmacsww, SchedWriteVecIMul.XMM>; + defm VPMACSWD : xop4opm2<0x96, "vpmacswd", + int_x86_xop_vpmacswd, SchedWriteVecIMul.XMM>; + defm VPMACSSWW : xop4opm2<0x85, "vpmacssww", + int_x86_xop_vpmacssww, SchedWriteVecIMul.XMM>; + defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd", + int_x86_xop_vpmacsswd, SchedWriteVecIMul.XMM>; + defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", + int_x86_xop_vpmacssdql, SchedWritePMULLD.XMM>; + defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", + int_x86_xop_vpmacssdqh, SchedWritePMULLD.XMM>; + defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd", + int_x86_xop_vpmacssdd, SchedWritePMULLD.XMM>; + defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql", + int_x86_xop_vpmacsdql, SchedWritePMULLD.XMM>; + defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh", + int_x86_xop_vpmacsdqh, SchedWritePMULLD.XMM>; + defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd", + int_x86_xop_vpmacsdd, SchedWritePMULLD.XMM>; +} + +// IFMA patterns - for cases where we can safely ignore the overflow bits from +// the multiply or easily match with existing intrinsics. +let Predicates = [HasXOP] in { + def : Pat<(v8i16 (add (mul (v8i16 VR128:$src1), (v8i16 VR128:$src2)), + (v8i16 VR128:$src3))), + (VPMACSWWrr VR128:$src1, VR128:$src2, VR128:$src3)>; + def : Pat<(v4i32 (add (mul (v4i32 VR128:$src1), (v4i32 VR128:$src2)), + (v4i32 VR128:$src3))), + (VPMACSDDrr VR128:$src1, VR128:$src2, VR128:$src3)>; + def : Pat<(v2i64 (add (X86pmuldq (bc_v2i64 (X86PShufd (v4i32 VR128:$src1), (i8 -11))), + (bc_v2i64 (X86PShufd (v4i32 VR128:$src2), (i8 -11)))), + (v2i64 VR128:$src3))), + (VPMACSDQHrr VR128:$src1, VR128:$src2, VR128:$src3)>; + def : Pat<(v2i64 (add (X86pmuldq (v2i64 VR128:$src1), (v2i64 VR128:$src2)), + (v2i64 VR128:$src3))), + (VPMACSDQLrr VR128:$src1, VR128:$src2, VR128:$src3)>; + def : Pat<(v4i32 (add (X86vpmaddwd (v8i16 VR128:$src1), (v8i16 VR128:$src2)), + (v4i32 VR128:$src3))), + (VPMADCSWDrr VR128:$src1, VR128:$src2, VR128:$src3)>; +} + +// Transforms to swizzle an immediate to help matching memory operand in first +// operand. +def CommuteVPCOMCC : SDNodeXFormgetZExtValue() & 0x7; + Imm = X86::getSwappedVPCOMImm(Imm); + return getI8Imm(Imm, SDLoc(N)); +}]>; + +// Instruction where second source can be memory, third must be imm8 +multiclass xopvpcom opc, string Suffix, SDNode OpNode, ValueType vt128, + X86FoldableSchedWrite sched> { + let ExeDomain = SSEPackedInt in { // SSE integer instructions + let isCommutable = 1 in + def ri : IXOPi8, + XOP_4V, Sched<[sched]>; + def mi : IXOPi8, + XOP_4V, Sched<[sched.Folded, ReadAfterLd]>; + let isAsmParserOnly = 1, hasSideEffects = 0 in { + def ri_alt : IXOPi8, XOP_4V, Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in + def mi_alt : IXOPi8, XOP_4V, Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + } + } + + def : Pat<(OpNode (bitconvert (loadv2i64 addr:$src2)), + (vt128 VR128:$src1), imm:$cc), + (!cast(NAME#"mi") VR128:$src1, addr:$src2, + (CommuteVPCOMCC imm:$cc))>; +} + +defm VPCOMB : xopvpcom<0xCC, "b", X86vpcom, v16i8, SchedWriteVecALU.XMM>; +defm VPCOMW : xopvpcom<0xCD, "w", X86vpcom, v8i16, SchedWriteVecALU.XMM>; +defm VPCOMD : xopvpcom<0xCE, "d", X86vpcom, v4i32, SchedWriteVecALU.XMM>; +defm VPCOMQ : xopvpcom<0xCF, "q", X86vpcom, v2i64, SchedWriteVecALU.XMM>; +defm VPCOMUB : xopvpcom<0xEC, "ub", X86vpcomu, v16i8, SchedWriteVecALU.XMM>; +defm VPCOMUW : xopvpcom<0xED, "uw", X86vpcomu, v8i16, SchedWriteVecALU.XMM>; +defm VPCOMUD : xopvpcom<0xEE, "ud", X86vpcomu, v4i32, SchedWriteVecALU.XMM>; +defm VPCOMUQ : xopvpcom<0xEF, "uq", X86vpcomu, v2i64, SchedWriteVecALU.XMM>; + +multiclass xop4op opc, string OpcodeStr, SDNode OpNode, + ValueType vt128, X86FoldableSchedWrite sched> { + def rrr : IXOPi8Reg, + XOP_4V, Sched<[sched]>; + def rrm : IXOPi8Reg, + XOP_4V, VEX_W, Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; + def rmr : IXOPi8Reg, + XOP_4V, Sched<[sched.Folded, ReadAfterLd, + // 128mem:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // VR128:$src3 + ReadAfterLd]>; + // For disassembler + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rrr_REV : IXOPi8Reg, XOP_4V, VEX_W, Sched<[sched]>, FoldGenData; +} + +let ExeDomain = SSEPackedInt in { + defm VPPERM : xop4op<0xA3, "vpperm", X86vpperm, v16i8, + SchedWriteVarShuffle.XMM>; +} + +// Instruction where either second or third source can be memory +multiclass xop4op_int opc, string OpcodeStr, RegisterClass RC, + X86MemOperand x86memop, ValueType VT, + X86FoldableSchedWrite sched> { + def rrr : IXOPi8Reg, XOP_4V, + Sched<[sched]>; + def rrm : IXOPi8Reg, + XOP_4V, VEX_W, Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; + def rmr : IXOPi8Reg, + XOP_4V, Sched<[sched.Folded, ReadAfterLd, + // x86memop:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC::$src3 + ReadAfterLd]>; + // For disassembler + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rrr_REV : IXOPi8Reg, XOP_4V, VEX_W, Sched<[sched]>, FoldGenData; +} + +let ExeDomain = SSEPackedInt in { + defm VPCMOV : xop4op_int<0xA2, "vpcmov", VR128, i128mem, v2i64, + SchedWriteShuffle.XMM>; + defm VPCMOVY : xop4op_int<0xA2, "vpcmov", VR256, i256mem, v4i64, + SchedWriteShuffle.YMM>, VEX_L; +} + +multiclass xop_vpermil2 Opc, string OpcodeStr, RegisterClass RC, + X86MemOperand intmemop, X86MemOperand fpmemop, + ValueType VT, PatFrag FPLdFrag, PatFrag IntLdFrag, + X86FoldableSchedWrite sched> { + def rr : IXOP5, + Sched<[sched]>; + def rm : IXOP5, VEX_W, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; + def mr : IXOP5, + Sched<[sched.Folded, ReadAfterLd, + // fpmemop:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, + // RC:$src3 + ReadAfterLd]>; + // For disassembler + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rr_REV : IXOP5, VEX_W, Sched<[sched]>, FoldGenData; +} + +let ExeDomain = SSEPackedDouble in { + defm VPERMIL2PD : xop_vpermil2<0x49, "vpermil2pd", VR128, i128mem, f128mem, + v2f64, loadv2f64, loadv2i64, + SchedWriteFVarShuffle.XMM>; + defm VPERMIL2PDY : xop_vpermil2<0x49, "vpermil2pd", VR256, i256mem, f256mem, + v4f64, loadv4f64, loadv4i64, + SchedWriteFVarShuffle.YMM>, VEX_L; +} + +let ExeDomain = SSEPackedSingle in { + defm VPERMIL2PS : xop_vpermil2<0x48, "vpermil2ps", VR128, i128mem, f128mem, + v4f32, loadv4f32, loadv2i64, + SchedWriteFVarShuffle.XMM>; + defm VPERMIL2PSY : xop_vpermil2<0x48, "vpermil2ps", VR256, i256mem, f256mem, + v8f32, loadv8f32, loadv4i64, + SchedWriteFVarShuffle.YMM>, VEX_L; +} + diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86PfmCounters.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86PfmCounters.td new file mode 100644 index 0000000..093fbaf --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86PfmCounters.td @@ -0,0 +1,77 @@ +//===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This describes the available hardware counters for various subtargets. +// +//===----------------------------------------------------------------------===// + +let SchedModel = SandyBridgeModel in { +def SBCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; +def SBPort0Counter : PfmIssueCounter; +def SBPort1Counter : PfmIssueCounter; +def SBPort23Counter : PfmIssueCounter; +def SBPort4Counter : PfmIssueCounter; +def SBPort5Counter : PfmIssueCounter; +} + +let SchedModel = HaswellModel in { +def HWCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; +def HWPort0Counter : PfmIssueCounter; +def HWPort1Counter : PfmIssueCounter; +def HWPort2Counter : PfmIssueCounter; +def HWPort3Counter : PfmIssueCounter; +def HWPort4Counter : PfmIssueCounter; +def HWPort5Counter : PfmIssueCounter; +def HWPort6Counter : PfmIssueCounter; +def HWPort7Counter : PfmIssueCounter; +} + +let SchedModel = BroadwellModel in { +def BWCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; +def BWPort0Counter : PfmIssueCounter; +def BWPort1Counter : PfmIssueCounter; +def BWPort2Counter : PfmIssueCounter; +def BWPort3Counter : PfmIssueCounter; +def BWPort4Counter : PfmIssueCounter; +def BWPort5Counter : PfmIssueCounter; +def BWPort6Counter : PfmIssueCounter; +def BWPort7Counter : PfmIssueCounter; +} + +let SchedModel = SkylakeClientModel in { +def SKLCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; +def SKLPort0Counter : PfmIssueCounter; +def SKLPort1Counter : PfmIssueCounter; +def SKLPort2Counter : PfmIssueCounter; +def SKLPort3Counter : PfmIssueCounter; +def SKLPort4Counter : PfmIssueCounter; +def SKLPort5Counter : PfmIssueCounter; +def SKLPort6Counter : PfmIssueCounter; +def SKLPort7Counter : PfmIssueCounter; +} + +let SchedModel = SkylakeServerModel in { +def SKXCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; +def SKXPort0Counter : PfmIssueCounter; +def SKXPort1Counter : PfmIssueCounter; +def SKXPort2Counter : PfmIssueCounter; +def SKXPort3Counter : PfmIssueCounter; +def SKXPort4Counter : PfmIssueCounter; +def SKXPort5Counter : PfmIssueCounter; +def SKXPort6Counter : PfmIssueCounter; +def SKXPort7Counter : PfmIssueCounter; +} + +let SchedModel = BtVer2Model in { +def JCycleCounter : PfmCycleCounter<"cpu_clk_unhalted">; +def JFPU0Counter : PfmIssueCounter; +def JFPU1Counter : PfmIssueCounter; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86RegisterBanks.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86RegisterBanks.td new file mode 100644 index 0000000..6d17cd5 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86RegisterBanks.td @@ -0,0 +1,17 @@ +//=- X86RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +/// General Purpose Registers: RAX, RCX,... +def GPRRegBank : RegisterBank<"GPR", [GR64]>; + +/// Floating Point/Vector Registers +def VECRRegBank : RegisterBank<"VECR", [VR512]>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86RegisterInfo.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86RegisterInfo.td new file mode 100644 index 0000000..907d402 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86RegisterInfo.td @@ -0,0 +1,591 @@ +//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 Register file, defining the registers themselves, +// aliases between the registers, and the register classes built out of the +// registers. +// +//===----------------------------------------------------------------------===// + +class X86Reg Enc, list subregs = []> : Register { + let Namespace = "X86"; + let HWEncoding = Enc; + let SubRegs = subregs; +} + +// Subregister indices. +let Namespace = "X86" in { + def sub_8bit : SubRegIndex<8>; + def sub_8bit_hi : SubRegIndex<8, 8>; + def sub_8bit_hi_phony : SubRegIndex<8, 8>; + def sub_16bit : SubRegIndex<16>; + def sub_16bit_hi : SubRegIndex<16, 16>; + def sub_32bit : SubRegIndex<32>; + def sub_xmm : SubRegIndex<128>; + def sub_ymm : SubRegIndex<256>; +} + +//===----------------------------------------------------------------------===// +// Register definitions... +// + +// In the register alias definitions below, we define which registers alias +// which others. We only specify which registers the small registers alias, +// because the register file generator is smart enough to figure out that +// AL aliases AX if we tell it that AX aliased AL (for example). + +// Dwarf numbering is different for 32-bit and 64-bit, and there are +// variations by target as well. Currently the first entry is for X86-64, +// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux +// and debug information on X86-32/Darwin) + +// 8-bit registers +// Low registers +def AL : X86Reg<"al", 0>; +def DL : X86Reg<"dl", 2>; +def CL : X86Reg<"cl", 1>; +def BL : X86Reg<"bl", 3>; + +// High registers. On x86-64, these cannot be used in any instruction +// with a REX prefix. +def AH : X86Reg<"ah", 4>; +def DH : X86Reg<"dh", 6>; +def CH : X86Reg<"ch", 5>; +def BH : X86Reg<"bh", 7>; + +// X86-64 only, requires REX. +let CostPerUse = 1 in { +def SIL : X86Reg<"sil", 6>; +def DIL : X86Reg<"dil", 7>; +def BPL : X86Reg<"bpl", 5>; +def SPL : X86Reg<"spl", 4>; +def R8B : X86Reg<"r8b", 8>; +def R9B : X86Reg<"r9b", 9>; +def R10B : X86Reg<"r10b", 10>; +def R11B : X86Reg<"r11b", 11>; +def R12B : X86Reg<"r12b", 12>; +def R13B : X86Reg<"r13b", 13>; +def R14B : X86Reg<"r14b", 14>; +def R15B : X86Reg<"r15b", 15>; +} + +let isArtificial = 1 in { +// High byte of the low 16 bits of the super-register: +def SIH : X86Reg<"", -1>; +def DIH : X86Reg<"", -1>; +def BPH : X86Reg<"", -1>; +def SPH : X86Reg<"", -1>; +def R8BH : X86Reg<"", -1>; +def R9BH : X86Reg<"", -1>; +def R10BH : X86Reg<"", -1>; +def R11BH : X86Reg<"", -1>; +def R12BH : X86Reg<"", -1>; +def R13BH : X86Reg<"", -1>; +def R14BH : X86Reg<"", -1>; +def R15BH : X86Reg<"", -1>; +// High word of the low 32 bits of the super-register: +def HAX : X86Reg<"", -1>; +def HDX : X86Reg<"", -1>; +def HCX : X86Reg<"", -1>; +def HBX : X86Reg<"", -1>; +def HSI : X86Reg<"", -1>; +def HDI : X86Reg<"", -1>; +def HBP : X86Reg<"", -1>; +def HSP : X86Reg<"", -1>; +def HIP : X86Reg<"", -1>; +def R8WH : X86Reg<"", -1>; +def R9WH : X86Reg<"", -1>; +def R10WH : X86Reg<"", -1>; +def R11WH : X86Reg<"", -1>; +def R12WH : X86Reg<"", -1>; +def R13WH : X86Reg<"", -1>; +def R14WH : X86Reg<"", -1>; +def R15WH : X86Reg<"", -1>; +} + +// 16-bit registers +let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in { +def AX : X86Reg<"ax", 0, [AL,AH]>; +def DX : X86Reg<"dx", 2, [DL,DH]>; +def CX : X86Reg<"cx", 1, [CL,CH]>; +def BX : X86Reg<"bx", 3, [BL,BH]>; +} +let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in { +def SI : X86Reg<"si", 6, [SIL,SIH]>; +def DI : X86Reg<"di", 7, [DIL,DIH]>; +def BP : X86Reg<"bp", 5, [BPL,BPH]>; +def SP : X86Reg<"sp", 4, [SPL,SPH]>; +} +def IP : X86Reg<"ip", 0>; + +// X86-64 only, requires REX. +let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CostPerUse = 1, + CoveredBySubRegs = 1 in { +def R8W : X86Reg<"r8w", 8, [R8B,R8BH]>; +def R9W : X86Reg<"r9w", 9, [R9B,R9BH]>; +def R10W : X86Reg<"r10w", 10, [R10B,R10BH]>; +def R11W : X86Reg<"r11w", 11, [R11B,R11BH]>; +def R12W : X86Reg<"r12w", 12, [R12B,R12BH]>; +def R13W : X86Reg<"r13w", 13, [R13B,R13BH]>; +def R14W : X86Reg<"r14w", 14, [R14B,R14BH]>; +def R15W : X86Reg<"r15w", 15, [R15B,R15BH]>; +} + +// 32-bit registers +let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in { +def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>; +def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>; +def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>; +def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>; +def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>; +def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>; +def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>; +def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>; +def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>; +} + +// X86-64 only, requires REX +let SubRegIndices = [sub_16bit, sub_16bit_hi], CostPerUse = 1, + CoveredBySubRegs = 1 in { +def R8D : X86Reg<"r8d", 8, [R8W,R8WH]>; +def R9D : X86Reg<"r9d", 9, [R9W,R9WH]>; +def R10D : X86Reg<"r10d", 10, [R10W,R10WH]>; +def R11D : X86Reg<"r11d", 11, [R11W,R11WH]>; +def R12D : X86Reg<"r12d", 12, [R12W,R12WH]>; +def R13D : X86Reg<"r13d", 13, [R13W,R13WH]>; +def R14D : X86Reg<"r14d", 14, [R14W,R14WH]>; +def R15D : X86Reg<"r15d", 15, [R15W,R15WH]>; +} + +// 64-bit registers, X86-64 only +let SubRegIndices = [sub_32bit] in { +def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>; +def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>; +def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>; +def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>; +def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>; +def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>; +def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>; +def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>; + +// These also require REX. +let CostPerUse = 1 in { +def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>; +def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>; +def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>; +def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>; +def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>; +def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>; +def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>; +def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>; +def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>; +}} + +// MMX Registers. These are actually aliased to ST0 .. ST7 +def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>; +def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>; +def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>; +def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>; +def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>; +def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>; +def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>; +def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>; + +// Pseudo Floating Point registers +def FP0 : X86Reg<"fp0", 0>; +def FP1 : X86Reg<"fp1", 0>; +def FP2 : X86Reg<"fp2", 0>; +def FP3 : X86Reg<"fp3", 0>; +def FP4 : X86Reg<"fp4", 0>; +def FP5 : X86Reg<"fp5", 0>; +def FP6 : X86Reg<"fp6", 0>; +def FP7 : X86Reg<"fp7", 0>; + +// XMM Registers, used by the various SSE instruction set extensions. +def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>; +def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>; +def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>; +def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>; +def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>; +def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>; +def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>; +def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>; + +// X86-64 only +let CostPerUse = 1 in { +def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>; +def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>; +def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>; +def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>; +def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>; +def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>; +def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>; +def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>; + +def XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[67, -2, -2]>; +def XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[68, -2, -2]>; +def XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[69, -2, -2]>; +def XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[70, -2, -2]>; +def XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[71, -2, -2]>; +def XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[72, -2, -2]>; +def XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[73, -2, -2]>; +def XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[74, -2, -2]>; +def XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[75, -2, -2]>; +def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[76, -2, -2]>; +def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[77, -2, -2]>; +def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[78, -2, -2]>; +def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[79, -2, -2]>; +def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[80, -2, -2]>; +def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[81, -2, -2]>; +def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[82, -2, -2]>; + +} // CostPerUse + +// YMM0-15 registers, used by AVX instructions and +// YMM16-31 registers, used by AVX-512 instructions. +let SubRegIndices = [sub_xmm] in { + foreach Index = 0-31 in { + def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast("XMM"#Index)]>, + DwarfRegAlias("XMM"#Index)>; + } +} + +// ZMM Registers, used by AVX-512 instructions. +let SubRegIndices = [sub_ymm] in { + foreach Index = 0-31 in { + def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast("YMM"#Index)]>, + DwarfRegAlias("XMM"#Index)>; + } +} + +// Mask Registers, used by AVX-512 instructions. +def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>; +def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>; +def K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, 95, 95]>; +def K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, 96, 96]>; +def K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, 97, 97]>; +def K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, 98, 98]>; +def K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, 99, 99]>; +def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>; + +// Floating point stack registers. These don't map one-to-one to the FP +// pseudo registers, but we still mark them as aliasing FP registers. That +// way both kinds can be live without exceeding the stack depth. ST registers +// are only live around inline assembly. +def ST0 : X86Reg<"st(0)", 0>, DwarfRegNum<[33, 12, 11]>; +def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>; +def ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>; +def ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>; +def ST4 : X86Reg<"st(4)", 4>, DwarfRegNum<[37, 16, 15]>; +def ST5 : X86Reg<"st(5)", 5>, DwarfRegNum<[38, 17, 16]>; +def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>; +def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>; + +// Floating-point status word +def FPSW : X86Reg<"fpsw", 0>; + +// Status flags register. +// +// Note that some flags that are commonly thought of as part of the status +// flags register are modeled separately. Typically this is due to instructions +// reading and updating those flags independently of all the others. We don't +// want to create false dependencies between these instructions and so we use +// a separate register to model them. +def EFLAGS : X86Reg<"flags", 0>; + +// The direction flag. +def DF : X86Reg<"dirflag", 0>; + + +// Segment registers +def CS : X86Reg<"cs", 1>; +def DS : X86Reg<"ds", 3>; +def SS : X86Reg<"ss", 2>; +def ES : X86Reg<"es", 0>; +def FS : X86Reg<"fs", 4>; +def GS : X86Reg<"gs", 5>; + +// Debug registers +def DR0 : X86Reg<"dr0", 0>; +def DR1 : X86Reg<"dr1", 1>; +def DR2 : X86Reg<"dr2", 2>; +def DR3 : X86Reg<"dr3", 3>; +def DR4 : X86Reg<"dr4", 4>; +def DR5 : X86Reg<"dr5", 5>; +def DR6 : X86Reg<"dr6", 6>; +def DR7 : X86Reg<"dr7", 7>; +def DR8 : X86Reg<"dr8", 8>; +def DR9 : X86Reg<"dr9", 9>; +def DR10 : X86Reg<"dr10", 10>; +def DR11 : X86Reg<"dr11", 11>; +def DR12 : X86Reg<"dr12", 12>; +def DR13 : X86Reg<"dr13", 13>; +def DR14 : X86Reg<"dr14", 14>; +def DR15 : X86Reg<"dr15", 15>; + +// Control registers +def CR0 : X86Reg<"cr0", 0>; +def CR1 : X86Reg<"cr1", 1>; +def CR2 : X86Reg<"cr2", 2>; +def CR3 : X86Reg<"cr3", 3>; +def CR4 : X86Reg<"cr4", 4>; +def CR5 : X86Reg<"cr5", 5>; +def CR6 : X86Reg<"cr6", 6>; +def CR7 : X86Reg<"cr7", 7>; +def CR8 : X86Reg<"cr8", 8>; +def CR9 : X86Reg<"cr9", 9>; +def CR10 : X86Reg<"cr10", 10>; +def CR11 : X86Reg<"cr11", 11>; +def CR12 : X86Reg<"cr12", 12>; +def CR13 : X86Reg<"cr13", 13>; +def CR14 : X86Reg<"cr14", 14>; +def CR15 : X86Reg<"cr15", 15>; + +// Pseudo index registers +def EIZ : X86Reg<"eiz", 4>; +def RIZ : X86Reg<"riz", 4>; + +// Bound registers, used in MPX instructions +def BND0 : X86Reg<"bnd0", 0>; +def BND1 : X86Reg<"bnd1", 1>; +def BND2 : X86Reg<"bnd2", 2>; +def BND3 : X86Reg<"bnd3", 3>; + +// CET registers - Shadow Stack Pointer +def SSP : X86Reg<"ssp", 0>; + +//===----------------------------------------------------------------------===// +// Register Class Definitions... now that we have all of the pieces, define the +// top-level register classes. The order specified in the register list is +// implicitly defined to be the register allocation order. +// + +// List call-clobbered registers before callee-save registers. RBX, RBP, (and +// R12, R13, R14, and R15 for X86-64) are callee-save registers. +// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and +// R8B, ... R15B. +// Allocate R12 and R13 last, as these require an extra byte when +// encoded in x86_64 instructions. +// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in +// 64-bit mode. The main complication is that they cannot be encoded in an +// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc. +// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d" +// cannot be encoded. +def GR8 : RegisterClass<"X86", [i8], 8, + (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, + R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B)> { + let AltOrders = [(sub GR8, AH, BH, CH, DH)]; + let AltOrderSelect = [{ + return MF.getSubtarget().is64Bit(); + }]; +} + +let isAllocatable = 0 in +def GRH8 : RegisterClass<"X86", [i8], 8, + (add SIH, DIH, BPH, SPH, R8BH, R9BH, R10BH, R11BH, + R12BH, R13BH, R14BH, R15BH)>; + +def GR16 : RegisterClass<"X86", [i16], 16, + (add AX, CX, DX, SI, DI, BX, BP, SP, + R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W)>; + +let isAllocatable = 0 in +def GRH16 : RegisterClass<"X86", [i16], 16, + (add HAX, HCX, HDX, HSI, HDI, HBX, HBP, HSP, HIP, + R8WH, R9WH, R10WH, R11WH, R12WH, R13WH, R14WH, + R15WH)>; + +def GR32 : RegisterClass<"X86", [i32], 32, + (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, + R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D)>; + +// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since +// RIP isn't really a register and it can't be used anywhere except in an +// address, but it doesn't cause trouble. +// FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra +// tests because of the inclusion of RIP in this register class. +def GR64 : RegisterClass<"X86", [i64], 64, + (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, + RBX, R14, R15, R12, R13, RBP, RSP, RIP)>; + +// Segment registers for use by MOV instructions (and others) that have a +// segment register as one operand. Always contain a 16-bit segment +// descriptor. +def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; + +// Debug registers. +def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 15)>; + +// Control registers. +def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>; + +// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of +// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" +// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers +// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD, +// and GR64_ABCD are classes for registers that support 8-bit h-register +// operations. +def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>; +def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; +def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>; +def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>; +def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>; +def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX)>; +def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, + R8, R9, R11, RIP)>; +def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, + R8, R9, R10, R11, RIP)>; + +// GR8_NOREX - GR8 registers which do not require a REX prefix. +def GR8_NOREX : RegisterClass<"X86", [i8], 8, + (add AL, CL, DL, AH, CH, DH, BL, BH)> { + let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)]; + let AltOrderSelect = [{ + return MF.getSubtarget().is64Bit(); + }]; +} +// GR16_NOREX - GR16 registers which do not require a REX prefix. +def GR16_NOREX : RegisterClass<"X86", [i16], 16, + (add AX, CX, DX, SI, DI, BX, BP, SP)>; +// GR32_NOREX - GR32 registers which do not require a REX prefix. +def GR32_NOREX : RegisterClass<"X86", [i32], 32, + (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>; +// GR64_NOREX - GR64 registers which do not require a REX prefix. +def GR64_NOREX : RegisterClass<"X86", [i64], 64, + (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>; + +// GR32_NOSP - GR32 registers except ESP. +def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; + +// GR64_NOSP - GR64 registers except RSP (and RIP). +def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>; + +// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except +// ESP. +def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32, + (and GR32_NOREX, GR32_NOSP)>; + +// GR64_NOREX_NOSP - GR64_NOREX registers except RSP. +def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, + (and GR64_NOREX, GR64_NOSP)>; + +// Register classes used for ABIs that use 32-bit address accesses, +// while using the whole x84_64 ISA. + +// In such cases, it is fine to use RIP as we are sure the 32 high +// bits are not set. We do not need variants for NOSP as RIP is not +// allowed there. +// RIP is not spilled anywhere for now, so stick to 32-bit alignment +// to save on memory space. +// FIXME: We could allow all 64bit registers, but we would need +// something to check that the 32 high bits are not set, +// which we do not have right now. +def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; + +// When RBP is used as a base pointer in a 32-bit addresses environment, +// this is also safe to use the full register to access addresses. +// Since RBP will never be spilled, stick to a 32 alignment to save +// on memory consumption. +def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32, + (add LOW32_ADDR_ACCESS, RBP)>; + +// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX. +def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; +def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>; + +// Scalar SSE2 floating point registers. +def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; + +def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; + + +// FIXME: This sets up the floating point register files as though they are f64 +// values, though they really are f80 values. This will cause us to spill +// values as 64-bit quantities instead of 80-bit quantities, which is much much +// faster on common hardware. In reality, this should be controlled by a +// command line option or something. + +def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>; +def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>; +def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>; + +// Floating point stack registers (these are not allocatable by the +// register allocator - the floating point stackifier is responsible +// for transforming FPn allocations to STn registers) +def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> { + let isAllocatable = 0; +} + +// Generic vector registers: VR64 and VR128. +// Ensure that float types are declared first - only float is legal on SSE1. +def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>; +def VR128 : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], + 128, (add FR32)>; +def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], + 256, (sequence "YMM%u", 0, 15)>; + +// Special classes that help the assembly parser choose some alternate +// instructions to favor 2-byte VEX encodings. +def VR128L : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], + 128, (sequence "XMM%u", 0, 7)>; +def VR128H : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], + 128, (sequence "XMM%u", 8, 15)>; +def VR256L : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], + 256, (sequence "YMM%u", 0, 7)>; +def VR256H : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], + 256, (sequence "YMM%u", 8, 15)>; + +// Status flags registers. +def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> { + let CopyCost = -1; // Don't allow copying of status registers. + let isAllocatable = 0; +} +def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> { + let CopyCost = -1; // Don't allow copying of status registers. + let isAllocatable = 0; +} +def DFCCR : RegisterClass<"X86", [i32], 32, (add DF)> { + let CopyCost = -1; // Don't allow copying of status registers. + let isAllocatable = 0; +} + +// AVX-512 vector/mask registers. +def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], + 512, (sequence "ZMM%u", 0, 31)>; + +// Scalar AVX-512 floating point registers. +def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>; + +def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>; + +// Extended VR128 and VR256 for AVX-512 instructions +def VR128X : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], + 128, (add FR32X)>; +def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], + 256, (sequence "YMM%u", 0, 31)>; + +// Mask registers +def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;} +def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;} +def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;} +def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;} +def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;} +def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;} +def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;} + +def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;} +def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;} +def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;} +def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;} +def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;} +def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;} +def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;} + +// Bound registers +def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedBroadwell.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedBroadwell.td new file mode 100644 index 0000000..6334d9e --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedBroadwell.td @@ -0,0 +1,1692 @@ +//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Broadwell to support instruction +// scheduling and other instruction cost heuristics. +// +//===----------------------------------------------------------------------===// + +def BroadwellModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and BW can decode 4 + // instructions per cycle. + let IssueWidth = 4; + let MicroOpBufferSize = 192; // Based on the reorder buffer. + let LoadLatency = 5; + let MispredictPenalty = 16; + + // Based on the LSD (loop-stream detector) queue size and benchmarking data. + let LoopMicroOpBufferSize = 50; + + // This flag is set to allow the scheduler to assign a default model to + // unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = BroadwellModel in { + +// Broadwell can issue micro-ops to 8 different ports in one cycle. + +// Ports 0, 1, 5, and 6 handle all computation. +// Port 4 gets the data half of stores. Store data can be available later than +// the store address, but since we don't model the latency of stores, we can +// ignore that. +// Ports 2 and 3 are identical. They handle loads and the address half of +// stores. Port 7 can handle address calculations. +def BWPort0 : ProcResource<1>; +def BWPort1 : ProcResource<1>; +def BWPort2 : ProcResource<1>; +def BWPort3 : ProcResource<1>; +def BWPort4 : ProcResource<1>; +def BWPort5 : ProcResource<1>; +def BWPort6 : ProcResource<1>; +def BWPort7 : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>; +def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>; +def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>; +def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>; +def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>; +def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>; +def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>; +def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>; +def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>; +def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>; +def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>; +def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>; + +// 60 Entry Unified Scheduler +def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4, + BWPort5, BWPort6, BWPort7]> { + let BufferSize=60; +} + +// Integer division issued on port 0. +def BWDivider : ProcResource<1>; +// FP division and sqrt on port 0. +def BWFPDivider : ProcResource<1>; + +// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass BWWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 5> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to + // the latency (default = 5). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = !add(UOps, 1); + } +} + +// A folded store needs a cycle on port 4 for the store data, and an extra port +// 2/3/7 cycle to recompute the address. +def : WriteRes; + +// Arithmetic. +defm : BWWriteResPair; // Simple integer ALU op. +defm : BWWriteResPair; // Integer ALU + flags op. +defm : BWWriteResPair; // Integer multiplication. +defm : BWWriteResPair; // Integer 64-bit multiplication. +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : BWWriteResPair; +def : WriteRes { let Latency = 3; } // Integer multiplication, high part. + +def : WriteRes; // LEA instructions can't fold loads. + +defm : BWWriteResPair; // Conditional move. +defm : BWWriteResPair; // // Conditional (CF + ZF flag) move. +defm : X86WriteRes; // x87 conditional move. + +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} +def : WriteRes; +def : WriteRes; // Bit Test instrs + +// Bit counts. +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; + +// Integer shifts and rotates. +defm : BWWriteResPair; + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// BMI1 BEXTR, BMI2 BZHI +defm : BWWriteResPair; +defm : BWWriteResPair; + +// Loads, stores, and moves, not folded with other operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +def : WriteRes; + +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +defm : BWWriteResPair; + +// Floating point. This covers both scalar and vector operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : BWWriteResPair; // Floating point add/sub. +defm : BWWriteResPair; // Floating point add/sub (XMM). +defm : BWWriteResPair; // Floating point add/sub (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point double add/sub. +defm : BWWriteResPair; // Floating point double add/sub (XMM). +defm : BWWriteResPair; // Floating point double add/sub (YMM/ZMM). +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; // Floating point compare. +defm : BWWriteResPair; // Floating point compare (XMM). +defm : BWWriteResPair; // Floating point compare (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point double compare. +defm : BWWriteResPair; // Floating point double compare (XMM). +defm : BWWriteResPair; // Floating point double compare (YMM/ZMM). +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; // Floating point compare to flags. + +defm : BWWriteResPair; // Floating point multiplication. +defm : BWWriteResPair; // Floating point multiplication (XMM). +defm : BWWriteResPair; // Floating point multiplication (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point double multiplication. +defm : BWWriteResPair; // Floating point double multiplication (XMM). +defm : BWWriteResPair; // Floating point double multiplication (YMM/ZMM). +defm : X86WriteResPairUnsupported; + +//defm : BWWriteResPair; // Floating point division. +defm : BWWriteResPair; // Floating point division (XMM). +defm : BWWriteResPair; // Floating point division (YMM). +defm : X86WriteResPairUnsupported; +//defm : BWWriteResPair; // Floating point division. +defm : BWWriteResPair; // Floating point division (XMM). +defm : BWWriteResPair; // Floating point division (YMM). +defm : X86WriteResPairUnsupported; + +defm : X86WriteRes; // Floating point square root. +defm : X86WriteRes; +defm : BWWriteResPair; // Floating point square root (XMM). +defm : BWWriteResPair; // Floating point square root (YMM). +defm : X86WriteResPairUnsupported; +defm : X86WriteRes; // Floating point double square root. +defm : X86WriteRes; +defm : BWWriteResPair; // Floating point double square root (XMM). +defm : BWWriteResPair; // Floating point double square root (YMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point long double square root. + +defm : BWWriteResPair; // Floating point reciprocal estimate. +defm : BWWriteResPair; // Floating point reciprocal estimate (XMM). +defm : BWWriteResPair; // Floating point reciprocal estimate (YMM/ZMM). +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; // Floating point reciprocal square root estimate. +defm : BWWriteResPair; // Floating point reciprocal square root estimate (XMM). +defm : BWWriteResPair; // Floating point reciprocal square root estimate (YMM/ZMM). +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; // Fused Multiply Add. +defm : BWWriteResPair; // Fused Multiply Add (XMM). +defm : BWWriteResPair; // Fused Multiply Add (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point double dot product. +defm : BWWriteResPair; // Floating point single dot product. +defm : BWWriteResPair; // Floating point single dot product (YMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point fabs/fchs. +defm : X86WriteRes; // Floating point rounding. +defm : X86WriteRes; // Floating point rounding (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; +defm : BWWriteResPair; // Floating point and/or/xor logicals. +defm : BWWriteResPair; // Floating point and/or/xor logicals (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point TEST instructions. +defm : BWWriteResPair; // Floating point TEST instructions (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point vector shuffles. +defm : BWWriteResPair; // Floating point vector shuffles (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point vector variable shuffles. +defm : BWWriteResPair; // Floating point vector variable shuffles. +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point vector blends. +defm : BWWriteResPair; // Floating point vector blends. +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Fp vector variable blends. +defm : BWWriteResPair; // Fp vector variable blends. +defm : X86WriteResPairUnsupported; + +// FMA Scheduling helper class. +// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } + +// Vector integer operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; + +defm : BWWriteResPair; // Vector integer ALU op, no logicals. +defm : BWWriteResPair; // Vector integer ALU op, no logicals. +defm : BWWriteResPair; // Vector integer ALU op, no logicals (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector integer and/or/xor. +defm : BWWriteResPair; // Vector integer and/or/xor. +defm : BWWriteResPair; // Vector integer and/or/xor (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector integer TEST instructions. +defm : BWWriteResPair; // Vector integer TEST instructions (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector integer multiply. +defm : BWWriteResPair; // Vector integer multiply. +defm : BWWriteResPair; // Vector integer multiply. +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector PMULLD. +defm : BWWriteResPair; // Vector PMULLD (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector shuffles. +defm : BWWriteResPair; // Vector shuffles. +defm : BWWriteResPair; // Vector shuffles (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector variable shuffles. +defm : BWWriteResPair; // Vector variable shuffles. +defm : BWWriteResPair; // Vector variable shuffles (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector blends. +defm : BWWriteResPair; // Vector blends (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector variable blends. +defm : BWWriteResPair; // Vector variable blends (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector MPSAD. +defm : BWWriteResPair; // Vector MPSAD. +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector PSADBW. +defm : BWWriteResPair; // Vector PSADBW. +defm : BWWriteResPair; // Vector PSADBW (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector PHMINPOS. + +// Vector integer shifts. +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; +defm : BWWriteResPair; // Vector integer immediate shifts (XMM). +defm : BWWriteResPair; // Vector integer immediate shifts (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Variable vector shifts. +defm : BWWriteResPair; // Variable vector shifts (YMM/ZMM). +defm : X86WriteResPairUnsupported; + +// Vector insert/extract operations. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 6; + let NumMicroOps = 2; +} + +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + +// Conversion between integer and float. +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; + +// Strings instructions. + +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 19; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} +def : WriteRes { + let Latency = 24; + let NumMicroOps = 10; + let ResourceCycles = [4,3,1,1,1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [4,3,1]; +} +def : WriteRes { + let Latency = 23; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 1; } + +// AES instructions. +def : WriteRes { // Decryption, encryption. + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +def : WriteRes { // InvMixColumn. + let Latency = 14; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 19; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} + +def : WriteRes { // Key Generation. + let Latency = 29; + let NumMicroOps = 11; + let ResourceCycles = [2,7,2]; +} +def : WriteRes { + let Latency = 33; + let NumMicroOps = 11; + let ResourceCycles = [2,7,1,1]; +} + +// Carry-less multiplication instructions. +defm : BWWriteResPair; + +// Catch-all for expensive system instructions. +def : WriteRes { let Latency = 100; } // def WriteSystem : SchedWrite; + +// AVX2. +defm : BWWriteResPair; // Fp 256-bit width vector shuffles. +defm : BWWriteResPair; // Fp 256-bit width vector variable shuffles. +defm : BWWriteResPair; // 256-bit width vector shuffles. +defm : BWWriteResPair; // 256-bit width vector variable shuffles. + +// Old microcoded instructions that nobody use. +def : WriteRes { let Latency = 100; } // def WriteMicrocoded : SchedWrite; + +// Fence instructions. +def : WriteRes; + +// Load/store MXCSR. +def : WriteRes { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } +def : WriteRes { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } + +// Nop, not very useful expect it provides a model for nops! +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; + +// Remaining instrs. + +def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr", + "VPSRLVQ(Y?)rr")>; + +def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r", + "UCOM_F(P?)r")>; + +def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVQ2DQrr")>; + +def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>; + +def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>; + +def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>; + +def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr", + "BLSI(32|64)rr", + "BLSMSK(32|64)rr", + "BLSR(32|64)rr")>; + +def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>; + +def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup9], (instregex "SGDT64m", + "SIDT64m", + "SMSW16m", + "STRm", + "SYSCALL")>; + +def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm", + "ST_FP(32|64|80)m")>; + +def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>; + +def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1", + "ROL(8|16|32|64)ri", + "ROR(8|16|32|64)r1", + "ROR(8|16|32|64)ri")>; + +def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[BWWriteResGroup14], (instrs LFENCE, + MFENCE, + WAIT, + XGETBV)>; + +def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup15], (instregex "(V?)CVTPS2PDrr", + "(V?)CVTSS2SDrr")>; + +def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>; + +def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>; + +def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>; + +def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup20], (instrs CWD)>; +def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>; +def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8", + "ADC8ri", + "SBB8i8", + "SBB8ri", + "SET(A|BE)r")>; + +def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>; + +def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>; + +def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, + STOSB, STOSL, STOSQ, STOSW)>; +def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr", + "PUSH64i8")>; + +def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup27], (instregex "MMX_CVTPI2PSirr", + "PDEP(32|64)rr", + "PEXT(32|64)rr", + "(V?)CVTDQ2PS(Y?)rr")>; + +def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>; + +def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup28], (instregex "VPBROADCASTBrr", + "VPBROADCASTWrr")>; + +def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[BWWriteResGroup30], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr, + XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr, + XCHG16ar, XCHG32ar, XCHG64ar)>; + +def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr", + "MMX_PACKSSWBirr", + "MMX_PACKUSWBirr")>; + +def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[BWWriteResGroup34], (instregex "CLD")>; + +def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1", + "RCL(8|16|32|64)ri", + "RCR(8|16|32|64)r1", + "RCR(8|16|32|64)ri")>; + +def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL", + "ROR(8|16|32|64)rCL", + "SAR(8|16|32|64)rCL", + "SHL(8|16|32|64)rCL", + "SHR(8|16|32|64)rCL")>; + +def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>; + +def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>; +def: InstRW<[BWWriteResGroup38], (instregex "SET(A|BE)m")>; + +def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr", + "(V?)CVT(T?)SD2SIrr", + "(V?)CVT(T?)SS2SI64rr", + "(V?)CVT(T?)SS2SIrr")>; + +def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr")>; + +def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>; + +def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>; +def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPI2PDirr", + "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", + "(V?)CVTDQ2PDrr", + "(V?)CVTPD2PSrr", + "(V?)CVTSD2SSrr", + "(V?)CVTSI642SDrr", + "(V?)CVTSI2SDrr", + "(V?)CVTSI2SSrr", + "(V?)CVT(T?)PD2DQrr")>; + +def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>; + +def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>; + +def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m", + "IST_F(16|32)m")>; + +def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [4]; +} +def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>; + +def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>; + +def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup47], (instregex "(V?)PCMPGTQ(Y?)rr", + "MUL_(FPrST0|FST0r|FrST0)")>; + +def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm16", + "MOVSX(16|32|64)rm32", + "MOVSX(16|32|64)rm8", + "MOVZX(16|32|64)rm16", + "MOVZX(16|32|64)rm8", + "VBROADCASTSSrm", + "(V?)MOVDDUPrm", + "(V?)MOVSHDUPrm", + "(V?)MOVSLDUPrm", + "VPBROADCASTDrm", + "VPBROADCASTQrm")>; + +def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>; + +def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>; + +def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup52], (instrs IMUL32r, MUL32r, MULX32rr)>; + +def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>; + +def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>; + +def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [2,3]; +} +def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>; + +def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { + let Latency = 5; + let NumMicroOps = 6; + let ResourceCycles = [1,1,4]; +} +def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>; + +def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m", + "VBROADCASTF128", + "VBROADCASTI128", + "VBROADCASTSDYrm", + "VBROADCASTSSYrm", + "VMOVDDUPYrm", + "VMOVSHDUPYrm", + "VMOVSLDUPYrm", + "VPBROADCASTDYrm", + "VPBROADCASTQYrm")>; + +def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup59], (instregex "(V?)CVTPS2PDrm", + "(V?)CVTSS2SDrm", + "VPSLLVQrm", + "VPSRLVQrm")>; + +def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr", + "VCVTPD2PSYrr", + "VCVT(T?)PD2DQYrr")>; + +def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64", + "JMP(16|32|64)m")>; + +def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8")>; + +def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm", + "BLSI(32|64)rm", + "BLSMSK(32|64)rm", + "BLSR(32|64)rm", + "MOVBE(16|32|64)rm")>; + +def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup65], (instregex "VINSERTF128rm", + "VINSERTI128rm", + "VPBLENDDrmi")>; + +def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>; +def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>; + +def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>; + +def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8", + "BTR(16|32|64)mi8", + "BTS(16|32|64)mi8", + "SAR(8|16|32|64)m1", + "SAR(8|16|32|64)mi", + "SHL(8|16|32|64)m1", + "SHL(8|16|32|64)mi", + "SHR(8|16|32|64)m1", + "SHR(8|16|32|64)mi")>; + +def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm", + "PUSH(16|32|64)rmm")>; + +def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> { + let Latency = 6; + let NumMicroOps = 6; + let ResourceCycles = [1,5]; +} +def: InstRW<[BWWriteResGroup71], (instrs STD)>; + +def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup73], (instregex "VPSLLVQYrm", + "VPSRLVQYrm")>; + +def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>; + +def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup77], (instregex "VPBLENDDYrmi")>; + +def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[BWWriteResGroup79], (instregex "MMX_PACKSSDWirm", + "MMX_PACKSSWBirm", + "MMX_PACKUSWBirm")>; + +def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64, + SCASB, SCASL, SCASQ, SCASW)>; + +def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>; + +def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>; + +def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1", + "ROL(8|16|32|64)mi", + "ROR(8|16|32|64)m1", + "ROR(8|16|32|64)mi")>; + +def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>; + +def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,1,1]; +} +def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m", + "FARCALL64")>; + +def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> { + let Latency = 7; + let NumMicroOps = 7; + let ResourceCycles = [2,2,1,2]; +} +def: InstRW<[BWWriteResGroup90], (instrs LOOP)>; + +def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm", + "PDEP(32|64)rm", + "PEXT(32|64)rm", + "(V?)CVTDQ2PSrm")>; + +def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rmi, IMUL16rmi8)>; + +def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort06, BWPort0156, BWPort23]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>; + +def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm", + "VPMOVSXBQYrm", + "VPMOVSXBWYrm", + "VPMOVSXDQYrm", + "VPMOVSXWDYrm", + "VPMOVSXWQYrm", + "VPMOVZXWDYrm")>; + +def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1", + "RCL(8|16|32|64)mi", + "RCR(8|16|32|64)m1", + "RCR(8|16|32|64)mi")>; + +def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>; + +def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,3]; +} +def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>; + +def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,2,1]; +} +def : SchedAlias; +def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG(8|16|32|64)rm", + "ROL(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; + +def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", + "ILD_F(16|32|64)m", + "VCVTPS2DQYrm", + "VCVTTPS2DQYrm")>; + +def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm", + "(V?)CVT(T?)SD2SI64rm", + "(V?)CVT(T?)SD2SIrm", + "VCVTTSS2SI64rm", + "(V?)CVTTSS2SIrm")>; + +def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>; + +def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>; +def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2PSrm", + "CVT(T?)PD2DQrm", + "MMX_CVTPI2PDirm", + "MMX_CVT(T?)PD2PIirm", + "(V?)CVTDQ2PDrm", + "(V?)CVTSD2SSrm")>; + +def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm", + "VPBROADCASTW(Y?)rm")>; + +def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,3]; +} +def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>; + +def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm", + "LSL(16|32|64)rm")>; + +def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>; + +def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>; + +def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> { + let Latency = 10; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>; + +def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>; + +def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { + let Latency = 11; + let NumMicroOps = 1; + let ResourceCycles = [1,3]; // Really 2.5 cycle throughput +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m", + "VPCMPGTQYrm")>; + +def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>; + +def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { + let Latency = 11; + let NumMicroOps = 7; + let ResourceCycles = [2,2,3]; +} +def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL", + "RCR(16|32|64)rCL")>; + +def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { + let Latency = 11; + let NumMicroOps = 9; + let ResourceCycles = [1,4,1,3]; +} +def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>; + +def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> { + let Latency = 11; + let NumMicroOps = 11; + let ResourceCycles = [2,9]; +} +def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>; +def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>; + +def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; + +def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1,4]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>; + +def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { + let Latency = 14; + let NumMicroOps = 8; + let ResourceCycles = [2,2,1,3]; +} +def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>; + +def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { + let Latency = 14; + let NumMicroOps = 10; + let ResourceCycles = [2,3,1,4]; +} +def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>; + +def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> { + let Latency = 14; + let NumMicroOps = 12; + let ResourceCycles = [2,1,4,5]; +} +def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>; + +def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> { + let Latency = 15; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; + +def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { + let Latency = 15; + let NumMicroOps = 10; + let ResourceCycles = [1,1,1,4,1,2]; +} +def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>; + +def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { + let Latency = 16; + let NumMicroOps = 2; + let ResourceCycles = [1,1,5]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { + let Latency = 16; + let NumMicroOps = 14; + let ResourceCycles = [1,1,1,4,2,5]; +} +def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>; + +def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> { + let Latency = 16; + let NumMicroOps = 16; + let ResourceCycles = [16]; +} +def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>; + +def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,5]; +} +def: InstRW<[BWWriteResGroup159], (instrs CPUID)>; +def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>; + +def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { + let Latency = 18; + let NumMicroOps = 11; + let ResourceCycles = [2,1,1,3,1,3]; +} +def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>; + +def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { + let Latency = 19; + let NumMicroOps = 2; + let ResourceCycles = [1,1,8]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> { + let Latency = 20; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; + +def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { + let Latency = 20; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,1,2]; +} +def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>; + +def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> { + let Latency = 21; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>; + +def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> { + let Latency = 21; + let NumMicroOps = 19; + let ResourceCycles = [2,1,4,1,1,4,6]; +} +def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>; + +def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { + let Latency = 22; + let NumMicroOps = 18; + let ResourceCycles = [1,1,16]; +} +def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>; + +def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { + let Latency = 23; + let NumMicroOps = 19; + let ResourceCycles = [3,1,15]; +} +def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>; + +def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { + let Latency = 24; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>; + +def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> { + let Latency = 26; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>; + +def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { + let Latency = 29; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>; + +def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 22; + let NumMicroOps = 7; + let ResourceCycles = [1,3,2,1]; +} +def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>; + +def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 23; + let NumMicroOps = 9; + let ResourceCycles = [1,3,4,1]; +} +def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>; + +def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 24; + let NumMicroOps = 9; + let ResourceCycles = [1,5,2,1]; +} +def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>; + +def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 25; + let NumMicroOps = 7; + let ResourceCycles = [1,3,2,1]; +} +def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm, + VGATHERDPSrm)>; + +def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 26; + let NumMicroOps = 9; + let ResourceCycles = [1,5,2,1]; +} +def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>; + +def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 26; + let NumMicroOps = 14; + let ResourceCycles = [1,4,8,1]; +} +def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>; + +def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 27; + let NumMicroOps = 9; + let ResourceCycles = [1,5,2,1]; +} +def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>; + +def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { + let Latency = 29; + let NumMicroOps = 27; + let ResourceCycles = [1,5,1,1,19]; +} +def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>; + +def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { + let Latency = 30; + let NumMicroOps = 28; + let ResourceCycles = [1,6,1,1,19]; +} +def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>; +def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; + +def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> { + let Latency = 34; + let NumMicroOps = 8; + let ResourceCycles = [2,2,2,1,1]; +} +def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>; + +def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> { + let Latency = 34; + let NumMicroOps = 23; + let ResourceCycles = [1,5,3,4,10]; +} +def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri", + "IN(8|16|32)rr")>; + +def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> { + let Latency = 35; + let NumMicroOps = 8; + let ResourceCycles = [2,2,2,1,1]; +} +def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>; + +def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,2,1,4,10]; +} +def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir", + "OUT(8|16|32)rr")>; + +def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> { + let Latency = 42; + let NumMicroOps = 22; + let ResourceCycles = [2,20]; +} +def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>; + +def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> { + let Latency = 60; + let NumMicroOps = 64; + let ResourceCycles = [2,2,8,1,10,2,39]; +} +def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>; + +def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { + let Latency = 63; + let NumMicroOps = 88; + let ResourceCycles = [4,4,31,1,2,1,45]; +} +def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>; + +def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { + let Latency = 63; + let NumMicroOps = 90; + let ResourceCycles = [4,2,33,1,2,1,47]; +} +def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>; + +def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> { + let Latency = 75; + let NumMicroOps = 15; + let ResourceCycles = [6,3,6]; +} +def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>; + +def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> { + let Latency = 80; + let NumMicroOps = 32; + let ResourceCycles = [7,7,3,3,1,11]; +} +def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>; + +def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> { + let Latency = 115; + let NumMicroOps = 100; + let ResourceCycles = [9,9,11,8,1,11,21,30]; +} +def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>; + +def: InstRW<[WriteZero], (instrs CLC)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedHaswell.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedHaswell.td new file mode 100644 index 0000000..876c3e4 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedHaswell.td @@ -0,0 +1,1975 @@ +//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Haswell to support instruction +// scheduling and other instruction cost heuristics. +// +// Note that we define some instructions here that are not supported by haswell, +// but we still have to define them because KNL uses the HSW model. +// They are currently tagged with a comment `Unsupported = 1`. +// FIXME: Use Unsupported = 1 once KNL has its own model. +// +//===----------------------------------------------------------------------===// + +def HaswellModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and HW can decode 4 + // instructions per cycle. + let IssueWidth = 4; + let MicroOpBufferSize = 192; // Based on the reorder buffer. + let LoadLatency = 5; + let MispredictPenalty = 16; + + // Based on the LSD (loop-stream detector) queue size and benchmarking data. + let LoopMicroOpBufferSize = 50; + + // This flag is set to allow the scheduler to assign a default model to + // unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = HaswellModel in { + +// Haswell can issue micro-ops to 8 different ports in one cycle. + +// Ports 0, 1, 5, and 6 handle all computation. +// Port 4 gets the data half of stores. Store data can be available later than +// the store address, but since we don't model the latency of stores, we can +// ignore that. +// Ports 2 and 3 are identical. They handle loads and the address half of +// stores. Port 7 can handle address calculations. +def HWPort0 : ProcResource<1>; +def HWPort1 : ProcResource<1>; +def HWPort2 : ProcResource<1>; +def HWPort3 : ProcResource<1>; +def HWPort4 : ProcResource<1>; +def HWPort5 : ProcResource<1>; +def HWPort6 : ProcResource<1>; +def HWPort7 : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def HWPort01 : ProcResGroup<[HWPort0, HWPort1]>; +def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>; +def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>; +def HWPort04 : ProcResGroup<[HWPort0, HWPort4]>; +def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>; +def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>; +def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>; +def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>; +def HWPort56 : ProcResGroup<[HWPort5, HWPort6]>; +def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; +def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>; +def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; + +// 60 Entry Unified Scheduler +def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4, + HWPort5, HWPort6, HWPort7]> { + let BufferSize=60; +} + +// Integer division issued on port 0. +def HWDivider : ProcResource<1>; +// FP division and sqrt on port 0. +def HWFPDivider : ProcResource<1>; + +// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass HWWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 5> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to + // the latency (default = 5). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = !add(UOps, 1); + } +} + +// A folded store needs a cycle on port 4 for the store data, and an extra port +// 2/3/7 cycle to recompute the address. +def : WriteRes; + +// Store_addr on 237. +// Store_data on 4. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +def : WriteRes; + +// Arithmetic. +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; + +def : WriteRes { let Latency = 3; } + +// Integer shifts and rotates. +defm : HWWriteResPair; + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : HWWriteResPair; +defm : HWWriteResPair; + +defm : HWWriteResPair; // Conditional move. +defm : HWWriteResPair; // Conditional (CF + ZF flag) move. +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} +def : WriteRes; +def : WriteRes; + +// This is for simple LEAs with one or two input operands. +// The complex ones can only execute on port 1, and they require two cycles on +// the port to read all inputs. We don't model that. +def : WriteRes; + +// Bit counts. +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; + +// BMI1 BEXTR, BMI2 BZHI +defm : HWWriteResPair; +defm : HWWriteResPair; + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; + +// Scalar and vector floating point. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +// Conversion between integer and float. +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 + +// Vector integer operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; + +// Vector integer shifts. +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +// Vector insert/extract operations. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 6; + let NumMicroOps = 2; +} +def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; + +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + +// String instructions. + +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 17; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 19; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} +def : WriteRes { + let Latency = 25; + let NumMicroOps = 10; + let ResourceCycles = [4,3,1,1,1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 17; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [4,3,1]; +} +def : WriteRes { + let Latency = 24; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 1; } + +// AES Instructions. +def : WriteRes { + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 13; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +def : WriteRes { + let Latency = 14; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 20; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} + +def : WriteRes { + let Latency = 29; + let NumMicroOps = 11; + let ResourceCycles = [2,7,2]; +} +def : WriteRes { + let Latency = 34; + let NumMicroOps = 11; + let ResourceCycles = [2,7,1,1]; +} + +// Carry-less multiplication instructions. +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def : WriteRes { + let Latency = 17; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} + +// Load/store MXCSR. +def : WriteRes { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } +def : WriteRes { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } + +def : WriteRes { let Latency = 100; } +def : WriteRes { let Latency = 100; } +def : WriteRes; +def : WriteRes; + +//================ Exceptions ================// + +//-- Specific Scheduling Models --// + +// Starting with P0. +def HWWriteP0 : SchedWriteRes<[HWPort0]>; + +def HWWriteP01 : SchedWriteRes<[HWPort01]>; + +def HWWrite2P01 : SchedWriteRes<[HWPort01]> { + let NumMicroOps = 2; +} +def HWWrite3P01 : SchedWriteRes<[HWPort01]> { + let NumMicroOps = 3; +} + +def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { + let NumMicroOps = 2; +} + +def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { + let NumMicroOps = 3; + let ResourceCycles = [2, 1]; +} + +// Starting with P1. +def HWWriteP1 : SchedWriteRes<[HWPort1]>; + + +def HWWrite2P1 : SchedWriteRes<[HWPort1]> { + let NumMicroOps = 2; + let ResourceCycles = [2]; +} + +// Notation: +// - r: register. +// - mm: 64 bit mmx register. +// - x = 128 bit xmm register. +// - (x)mm = mmx or xmm register. +// - y = 256 bit ymm register. +// - v = any vector register. +// - m = memory. + +//=== Integer Instructions ===// +//-- Move instructions --// + +// XLAT. +def HWWriteXLAT : SchedWriteRes<[]> { + let Latency = 7; + let NumMicroOps = 3; +} +def : InstRW<[HWWriteXLAT], (instrs XLAT)>; + +// PUSHA. +def HWWritePushA : SchedWriteRes<[]> { + let NumMicroOps = 19; +} +def : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>; + +// POPA. +def HWWritePopA : SchedWriteRes<[]> { + let NumMicroOps = 18; +} +def : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>; + +//-- Arithmetic instructions --// + +// DIV. +// r8. +def HWWriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { + let Latency = 22; + let NumMicroOps = 9; +} +def : InstRW<[HWWriteDiv8], (instregex "DIV8r")>; + +// IDIV. +// r8. +def HWWriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { + let Latency = 23; + let NumMicroOps = 9; +} +def : InstRW<[HWWriteIDiv8], (instregex "IDIV8r")>; + +// BT. +// m,r. +def HWWriteBTmr : SchedWriteRes<[]> { + let NumMicroOps = 10; +} +def : InstRW<[HWWriteBTmr], (instregex "BT(16|32|64)mr")>; + +// BTR BTS BTC. +// m,r. +def HWWriteBTRSCmr : SchedWriteRes<[]> { + let NumMicroOps = 11; +} +def : InstRW<[HWWriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>; + +//-- Control transfer instructions --// + +// CALL. +// i. +def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> { + let NumMicroOps = 4; + let ResourceCycles = [1, 2, 1]; +} +def : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>; + +// BOUND. +// r,m. +def HWWriteBOUND : SchedWriteRes<[]> { + let NumMicroOps = 15; +} +def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>; + +// INTO. +def HWWriteINTO : SchedWriteRes<[]> { + let NumMicroOps = 4; +} +def : InstRW<[HWWriteINTO], (instrs INTO)>; + +//-- String instructions --// + +// LODSB/W. +def : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>; + +// LODSD/Q. +def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>; + +// MOVS. +def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> { + let Latency = 4; + let NumMicroOps = 5; + let ResourceCycles = [2, 1, 2]; +} +def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; + +// CMPS. +def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> { + let Latency = 4; + let NumMicroOps = 5; + let ResourceCycles = [2, 3]; +} +def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>; + +//-- Other --// + +// RDPMC.f +def HWWriteRDPMC : SchedWriteRes<[]> { + let NumMicroOps = 34; +} +def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>; + +// RDRAND. +def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> { + let NumMicroOps = 17; + let ResourceCycles = [1, 16]; +} +def : InstRW<[HWWriteRDRAND], (instregex "RDRAND(16|32|64)r")>; + +//=== Floating Point x87 Instructions ===// +//-- Move instructions --// + +// FLD. +// m80. +def : InstRW<[HWWriteP01], (instregex "LD_Frr")>; + +// FBLD. +// m80. +def HWWriteFBLD : SchedWriteRes<[]> { + let Latency = 47; + let NumMicroOps = 43; +} +def : InstRW<[HWWriteFBLD], (instregex "FBLDm")>; + +// FST(P). +// r. +def : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>; + +// FFREE. +def : InstRW<[HWWriteP01], (instregex "FFREE")>; + +// FNSAVE. +def HWWriteFNSAVE : SchedWriteRes<[]> { + let NumMicroOps = 147; +} +def : InstRW<[HWWriteFNSAVE], (instregex "FSAVEm")>; + +// FRSTOR. +def HWWriteFRSTOR : SchedWriteRes<[]> { + let NumMicroOps = 90; +} +def : InstRW<[HWWriteFRSTOR], (instregex "FRSTORm")>; + +//-- Arithmetic instructions --// + +// FCOMPP FUCOMPP. +// r. +def : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>; + +// FCOMI(P) FUCOMI(P). +// m. +def : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; + +// FTST. +def : InstRW<[HWWriteP1], (instregex "TST_F")>; + +// FXAM. +def : InstRW<[HWWrite2P1], (instrs FXAM)>; + +// FPREM. +def HWWriteFPREM : SchedWriteRes<[]> { + let Latency = 19; + let NumMicroOps = 28; +} +def : InstRW<[HWWriteFPREM], (instrs FPREM)>; + +// FPREM1. +def HWWriteFPREM1 : SchedWriteRes<[]> { + let Latency = 27; + let NumMicroOps = 41; +} +def : InstRW<[HWWriteFPREM1], (instrs FPREM1)>; + +// FRNDINT. +def HWWriteFRNDINT : SchedWriteRes<[]> { + let Latency = 11; + let NumMicroOps = 17; +} +def : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>; + +//-- Math instructions --// + +// FSCALE. +def HWWriteFSCALE : SchedWriteRes<[]> { + let Latency = 75; // 49-125 + let NumMicroOps = 50; // 25-75 +} +def : InstRW<[HWWriteFSCALE], (instrs FSCALE)>; + +// FXTRACT. +def HWWriteFXTRACT : SchedWriteRes<[]> { + let Latency = 15; + let NumMicroOps = 17; +} +def : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; + +//=== Floating Point XMM and YMM Instructions ===// + +// Remaining instrs. + +def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSrm", + "(V?)MOVSHDUPrm", + "(V?)MOVSLDUPrm", + "VPBROADCAST(D|Q)rm")>; + +def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> { + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m", + "VBROADCASTF128", + "VBROADCASTI128", + "VBROADCASTSDYrm", + "VBROADCASTSSYrm", + "VMOVDDUPYrm", + "VMOVSHDUPYrm", + "VMOVSLDUPYrm", + "VPBROADCAST(D|Q)Yrm")>; + +def HWWriteResGroup0_2 : SchedWriteRes<[HWPort23]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm16", + "MOVSX(16|32|64)rm32", + "MOVSX(16|32|64)rm8", + "MOVZX(16|32|64)rm16", + "MOVZX(16|32|64)rm8", + "(V?)MOVDDUPrm")>; + +def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup1], (instregex "FBSTPm", + "ST_FP(32|64|80)m", + "VMPTRSTm")>; + +def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr", + "VPSRLVQ(Y?)rr")>; + +def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r", + "UCOM_F(P?)r")>; + +def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVQ2DQrr")>; + +def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>; + +def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>; + +def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>; + +def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr", + "BLSI(32|64)rr", + "BLSMSK(32|64)rr", + "BLSR(32|64)rr")>; + +def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>; + +def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE, + CMC, STC)>; +def: InstRW<[HWWriteResGroup10], (instregex "SGDT64m", + "SIDT64m", + "SMSW16m", + "STRm", + "SYSCALL")>; + +def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup11], (instregex "(V?)CVTPS2PDrm")>; + +def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup11_1], (instregex "(V?)CVTSS2SDrm", + "VPSLLVQrm", + "VPSRLVQrm")>; + +def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup11_2], (instregex "VPSLLVQYrm", + "VPSRLVQYrm")>; + +def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup12], (instregex "MMX_CVTPI2PSirm", + "PDEP(32|64)rm", + "PEXT(32|64)rm")>; + +def HWWriteResGroup12_1 : SchedWriteRes<[HWPort1,HWPort0156,HWPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup12_1], (instrs IMUL16rmi, IMUL16rmi8)>; + +def HWWriteResGroup12_2 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156,HWPort23]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[HWWriteResGroup12_2], (instrs IMUL16m, MUL16m)>; + +def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm", + "(V?)PMOV(SX|ZX)BQrm", + "(V?)PMOV(SX|ZX)BWrm", + "(V?)PMOV(SX|ZX)DQrm", + "(V?)PMOV(SX|ZX)WDrm", + "(V?)PMOV(SX|ZX)WQrm")>; + +def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup13_1], (instregex "VPMOVSXBDYrm", + "VPMOVSXBQYrm", + "VPMOVSXWQYrm")>; + +def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup14], (instregex "FARJMP64", + "JMP(16|32|64)m")>; + +def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort06]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8")>; + +def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm", + "BLSI(32|64)rm", + "BLSMSK(32|64)rm", + "BLSR(32|64)rm", + "MOVBE(16|32|64)rm")>; + +def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup17], (instregex "VINSERTF128rm", + "VINSERTI128rm", + "VPBLENDDrmi")>; + +def HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup17_2], (instregex "VPBLENDDYrmi")>; + +def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>; +def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>; + +def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>; + +def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>; + +def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>; + +def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>; + +def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, + STOSB, STOSL, STOSQ, STOSW)>; +def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr", + "PUSH64i8")>; + +def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup25], (instregex "BTC(16|32|64)mi8", + "BTR(16|32|64)mi8", + "BTS(16|32|64)mi8", + "SAR(8|16|32|64)m1", + "SAR(8|16|32|64)mi", + "SHL(8|16|32|64)m1", + "SHL(8|16|32|64)mi", + "SHR(8|16|32|64)m1", + "SHR(8|16|32|64)mi")>; + +def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm", + "PUSH(16|32|64)rmm")>; + +def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>; + +def HWWriteResGroup29 : SchedWriteRes<[HWPort06]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[HWWriteResGroup29], (instregex "ROL(8|16|32|64)r1", + "ROL(8|16|32|64)ri", + "ROR(8|16|32|64)r1", + "ROR(8|16|32|64)ri")>; + +def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[HWWriteResGroup30], (instrs LFENCE, + MFENCE, + WAIT, + XGETBV)>; + +def HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup31], (instregex "(V?)CVTPS2PDrr", + "(V?)CVTSS2SDrr")>; + +def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>; + +def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup33], (instregex "MMX_MOVDQ2Qrr")>; + +def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>; +def: InstRW<[HWWriteResGroup35], (instregex "SET(A|BE)r")>; + +def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[HWWriteResGroup36_2], (instregex "MMX_PACKSSDWirm", + "MMX_PACKSSWBirm", + "MMX_PACKUSWBirm")>; + +def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64, + SCASB, SCASL, SCASQ, SCASW)>; + +def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>; + +def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup41], (instrs LRETQ, RETL, RETQ)>; + +def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>; + +def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>; +def: InstRW<[HWWriteResGroup45], (instregex "SET(A|BE)m")>; + +def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m1", + "ROL(8|16|32|64)mi", + "ROR(8|16|32|64)m1", + "ROR(8|16|32|64)mi")>; + +def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>; + +def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,1,1]; +} +def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m", + "FARCALL64")>; + +def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPI2PSirr", + "PDEP(32|64)rr", + "PEXT(32|64)rr", + "(V?)CVTDQ2PS(Y?)rr")>; + +def HWWriteResGroup50_16i : SchedWriteRes<[HWPort1, HWPort0156]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup50_16i], (instrs IMUL16rri, IMUL16rri8)>; + +def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>; + +def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup52], (instregex "(V?)CVTPS2DQrm", + "(V?)CVTTPS2DQrm")>; + +def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m", + "ILD_F(16|32|64)m", + "VCVTDQ2PSYrm", + "VCVTPS2DQYrm", + "VCVTTPS2DQYrm")>; + +def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup53_1], (instregex "VPMOVSXBWYrm", + "VPMOVSXDQYrm", + "VPMOVSXWDYrm", + "VPMOVZXWDYrm")>; + +def HWWriteResGroup54 : SchedWriteRes<[HWPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[HWWriteResGroup54], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr, + XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr, + XCHG16ar, XCHG32ar, XCHG64ar)>; + +def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[HWWriteResGroup57], (instregex "MMX_PACKSSDWirr", + "MMX_PACKSSWBirr", + "MMX_PACKUSWBirr")>; + +def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[HWWriteResGroup58], (instregex "CLD")>; + +def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r1", + "RCL(8|16|32|64)ri", + "RCR(8|16|32|64)r1", + "RCR(8|16|32|64)ri")>; + +def HWWriteResGroup60 : SchedWriteRes<[HWPort06,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[HWWriteResGroup60], (instregex "ROL(8|16|32|64)rCL", + "ROR(8|16|32|64)rCL", + "SAR(8|16|32|64)rCL", + "SHL(8|16|32|64)rCL", + "SHR(8|16|32|64)rCL")>; + +def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>; + +def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m", + "IST_F(16|32)m")>; + +def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m1", + "RCL(8|16|32|64)mi", + "RCR(8|16|32|64)m1", + "RCR(8|16|32|64)mi")>; + +def HWWriteResGroup67 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[HWWriteResGroup67], (instregex "ROR(8|16|32|64)mCL")>; + +def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,3]; +} +def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>; + +def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,2,1]; +} +def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG(8|16|32|64)rm", + "ROL(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; +def: SchedAlias; + +def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup70], (instregex "(V?)CVT(T?)SD2SI(64)?rr", + "(V?)CVT(T?)SS2SI(64)?rr")>; + +def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup71], (instregex "VCVTPS2PDYrr")>; + +def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>; + +def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPI2PDirr", + "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", + "(V?)CVTDQ2PDrr", + "(V?)CVTPD2PSrr", + "(V?)CVTSD2SSrr", + "(V?)CVTSI(64)?2SDrr", + "(V?)CVTSI2SSrr", + "(V?)CVT(T?)PD2DQrr")>; + +def HWWriteResGroup74 : SchedWriteRes<[HWPort1,HWPort6]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup74], (instrs IMUL64r, MUL64r, MULX64rr)>; + +def HWWriteResGroup74_16 : SchedWriteRes<[HWPort1, HWPort06, HWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[HWWriteResGroup74_16], (instrs IMUL16r, MUL16r)>; + +def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>; + +def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm", + "(V?)CVTSS2SI(64)?rm", + "(V?)CVTTSD2SI(64)?rm", + "VCVTTSS2SI64rm", + "(V?)CVTTSS2SIrm")>; + +def HWWriteResGroup77 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup77], (instregex "VCVTPS2PDYrm")>; + +def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup78], (instregex "CVTPD2PSrm", + "CVT(T?)PD2DQrm", + "MMX_CVT(T?)PD2PIirm", + "(V?)CVTDQ2PDrm")>; + +def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup78_1], (instregex "MMX_CVTPI2PDirm", + "(V?)CVTSD2SSrm")>; + +def HWWriteResGroup79 : SchedWriteRes<[HWPort1,HWPort6,HWPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup79], (instrs IMUL64m, MUL64m, MULX64rm)>; + +def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>; + +def HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [4]; +} +def: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>; + +def HWWriteResGroup82 : SchedWriteRes<[HWPort015,HWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>; + +def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>; + +def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm", + "LSL(16|32|64)rm")>; + +def HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { + let Latency = 5; + let NumMicroOps = 6; + let ResourceCycles = [1,1,4]; +} +def: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>; + +def HWWriteResGroup89 : SchedWriteRes<[HWPort0]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup89], (instregex "(V?)PCMPGTQ(Y?)rr", + "MUL_(FPrST0|FST0r|FrST0)")>; + +def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>; + +def HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m", + "VPCMPGTQYrm")>; + +def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>; + +def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>; + +def HWWriteResGroup95 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup95], (instrs IMUL32r, MUL32r, MULX32rr)>; + +def HWWriteResGroup97 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> { + let Latency = 10; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup97], (instregex "CVTTSS2SI64rm")>; + +def HWWriteResGroup98 : SchedWriteRes<[HWPort1,HWPort23,HWPort06,HWPort0156]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup98], (instrs IMUL32m, MUL32m, MULX32rm)>; + +def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>; + +def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>; + +def HWWriteResGroup101 : SchedWriteRes<[HWPort06,HWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [2,3]; +} +def: InstRW<[HWWriteResGroup101], (instregex "CMPXCHG(8|16|32|64)rr")>; + +def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup102], (instregex "VCVTDQ2PDYrr", + "VCVTPD2PSYrr", + "VCVT(T?)PD2DQYrr")>; + +def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; + +def HWWriteResGroup104 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup104], (instregex "VCVTDQ2PDYrm")>; + +def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>; + +def HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> { + let Latency = 6; + let NumMicroOps = 6; + let ResourceCycles = [1,5]; +} +def: InstRW<[HWWriteResGroup108], (instrs STD)>; + +def HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> { + let Latency = 7; + let NumMicroOps = 7; + let ResourceCycles = [2,2,1,2]; +} +def: InstRW<[HWWriteResGroup114], (instrs LOOP)>; + +def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { + let Latency = 15; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>; + +def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { + let Latency = 16; + let NumMicroOps = 10; + let ResourceCycles = [1,1,1,4,1,2]; +} +def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>; + +def HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> { + let Latency = 11; + let NumMicroOps = 7; + let ResourceCycles = [2,2,3]; +} +def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL", + "RCR(16|32|64)rCL")>; + +def HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> { + let Latency = 11; + let NumMicroOps = 9; + let ResourceCycles = [1,4,1,3]; +} +def: InstRW<[HWWriteResGroup130], (instregex "RCL8rCL")>; + +def HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> { + let Latency = 11; + let NumMicroOps = 11; + let ResourceCycles = [2,9]; +} +def: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>; + +def HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { + let Latency = 17; + let NumMicroOps = 14; + let ResourceCycles = [1,1,1,4,2,5]; +} +def: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>; + +def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { + let Latency = 19; + let NumMicroOps = 11; + let ResourceCycles = [2,1,1,3,1,3]; +} +def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>; + +def HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> { + let Latency = 14; + let NumMicroOps = 10; + let ResourceCycles = [2,3,1,4]; +} +def: InstRW<[HWWriteResGroup142], (instregex "RCR8rCL")>; + +def HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> { + let Latency = 19; + let NumMicroOps = 15; + let ResourceCycles = [1,14]; +} +def: InstRW<[HWWriteResGroup143], (instregex "POPF16")>; + +def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> { + let Latency = 21; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,1,2]; +} +def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>; + +def HWWriteResGroup145 : SchedWriteRes<[HWPort5]> { + let Latency = 16; + let NumMicroOps = 16; + let ResourceCycles = [16]; +} +def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>; + +def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> { + let Latency = 22; + let NumMicroOps = 19; + let ResourceCycles = [2,1,4,1,1,4,6]; +} +def: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>; + +def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> { + let Latency = 17; + let NumMicroOps = 15; + let ResourceCycles = [2,1,2,4,2,4]; +} +def: InstRW<[HWWriteResGroup147], (instrs XCH_F)>; + +def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,5]; +} +def: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>; + +def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { + let Latency = 23; + let NumMicroOps = 19; + let ResourceCycles = [3,1,15]; +} +def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>; + +def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> { + let Latency = 20; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; + +def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 27; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>; + +def HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> { + let Latency = 20; + let NumMicroOps = 10; + let ResourceCycles = [1,2,7]; +} +def: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>; + +def HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { + let Latency = 30; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>; + +def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> { + let Latency = 24; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; + +def HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 31; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>; + +def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { + let Latency = 30; + let NumMicroOps = 27; + let ResourceCycles = [1,5,1,1,19]; +} +def: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>; + +def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { + let Latency = 31; + let NumMicroOps = 28; + let ResourceCycles = [1,6,1,1,19]; +} +def: InstRW<[HWWriteResGroup165], (instrs XSAVE)>; +def: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; + +def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { + let Latency = 34; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>; + +def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,3,4,10]; +} +def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri", + "IN(8|16|32)rr")>; + +def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> { + let Latency = 36; + let NumMicroOps = 23; + let ResourceCycles = [1,5,2,1,4,10]; +} +def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir", + "OUT(8|16|32)rr")>; + +def HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> { + let Latency = 41; + let NumMicroOps = 18; + let ResourceCycles = [1,1,2,3,1,1,1,8]; +} +def: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>; + +def HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> { + let Latency = 42; + let NumMicroOps = 22; + let ResourceCycles = [2,20]; +} +def: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>; + +def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> { + let Latency = 61; + let NumMicroOps = 64; + let ResourceCycles = [2,2,8,1,10,2,39]; +} +def: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>; + +def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { + let Latency = 64; + let NumMicroOps = 88; + let ResourceCycles = [4,4,31,1,2,1,45]; +} +def: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>; + +def HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { + let Latency = 64; + let NumMicroOps = 90; + let ResourceCycles = [4,2,33,1,2,1,47]; +} +def: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>; + +def HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> { + let Latency = 75; + let NumMicroOps = 15; + let ResourceCycles = [6,3,6]; +} +def: InstRW<[HWWriteResGroup180], (instrs FNINIT)>; + +def HWWriteResGroup181 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> { + let Latency = 98; + let NumMicroOps = 32; + let ResourceCycles = [7,7,3,3,1,11]; +} +def: InstRW<[HWWriteResGroup181], (instregex "DIV(16|32|64)r")>; + +def HWWriteResGroup182 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156]> { + let Latency = 112; + let NumMicroOps = 66; + let ResourceCycles = [4,2,4,8,14,34]; +} +def: InstRW<[HWWriteResGroup182], (instregex "IDIV(16|32|64)r")>; + +def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> { + let Latency = 115; + let NumMicroOps = 100; + let ResourceCycles = [9,9,11,8,1,11,21,30]; +} +def: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>; + +def HWWriteResGroup184 : SchedWriteRes<[HWPort0, HWPort5, HWPort15, HWPort015, HWPort06, HWPort23]> { + let Latency = 26; + let NumMicroOps = 12; + let ResourceCycles = [2,2,1,3,2,2]; +} +def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm, + VPGATHERDQrm, + VPGATHERDDrm)>; + +def HWWriteResGroup185 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 24; + let NumMicroOps = 22; + let ResourceCycles = [5,3,4,1,5,4]; +} +def: InstRW<[HWWriteResGroup185], (instrs VGATHERQPDYrm, + VPGATHERQQYrm)>; + +def HWWriteResGroup186 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 28; + let NumMicroOps = 22; + let ResourceCycles = [5,3,4,1,5,4]; +} +def: InstRW<[HWWriteResGroup186], (instrs VPGATHERQDYrm)>; + +def HWWriteResGroup187 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 25; + let NumMicroOps = 22; + let ResourceCycles = [5,3,4,1,5,4]; +} +def: InstRW<[HWWriteResGroup187], (instrs VPGATHERQDrm)>; + +def HWWriteResGroup188 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 27; + let NumMicroOps = 20; + let ResourceCycles = [3,3,4,1,5,4]; +} +def: InstRW<[HWWriteResGroup188], (instrs VGATHERDPDYrm, + VPGATHERDQYrm)>; + +def HWWriteResGroup189 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 27; + let NumMicroOps = 34; + let ResourceCycles = [5,3,8,1,9,8]; +} +def: InstRW<[HWWriteResGroup189], (instrs VGATHERDPSYrm, + VPGATHERDDYrm)>; + +def HWWriteResGroup190 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 23; + let NumMicroOps = 14; + let ResourceCycles = [3,3,2,1,3,2]; +} +def: InstRW<[HWWriteResGroup190], (instrs VGATHERQPDrm, + VPGATHERQQrm)>; + +def HWWriteResGroup191 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 28; + let NumMicroOps = 15; + let ResourceCycles = [3,3,2,1,4,2]; +} +def: InstRW<[HWWriteResGroup191], (instrs VGATHERQPSYrm)>; + +def HWWriteResGroup192 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 25; + let NumMicroOps = 15; + let ResourceCycles = [3,3,2,1,4,2]; +} +def: InstRW<[HWWriteResGroup192], (instrs VGATHERQPSrm, + VGATHERDPSrm)>; + +def: InstRW<[WriteZero], (instrs CLC)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedPredicates.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedPredicates.td new file mode 100644 index 0000000..27aaeb1 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedPredicates.td @@ -0,0 +1,49 @@ +//===-- X86SchedPredicates.td - X86 Scheduling Predicates --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines scheduling predicate definitions that are common to +// all X86 subtargets. +// +//===----------------------------------------------------------------------===// + +// A predicate used to identify dependency-breaking instructions that clear the +// content of the destination register. Note that this predicate only checks if +// input registers are the same. This predicate doesn't make any assumptions on +// the expected instruction opcodes, because different processors may implement +// different zero-idioms. +def ZeroIdiomPredicate : CheckSameRegOperand<1, 2>; + +// A predicate used to check if an instruction is a LEA, and if it uses all +// three source operands: base, index, and offset. +def IsThreeOperandsLEAPredicate: CheckAll<[ + CheckOpcode<[LEA32r, LEA64r, LEA64_32r, LEA16r]>, + + // isRegOperand(Base) + CheckIsRegOperand<1>, + CheckNot>, + + // isRegOperand(Index) + CheckIsRegOperand<3>, + CheckNot>, + + // hasLEAOffset(Offset) + CheckAny<[ + CheckAll<[ + CheckIsImmOperand<4>, + CheckNot> + ]>, + CheckNonPortable<"MI.getOperand(4).isGlobal()"> + ]> +]>; + +// This predicate evaluates to true only if the input machine instruction is a +// 3-operands LEA. Tablegen automatically generates a new method for it in +// X86GenInstrInfo. +def IsThreeOperandsLEAFn : + TIIPredicate<"X86", "isThreeOperandsLEA", IsThreeOperandsLEAPredicate>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedSandyBridge.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedSandyBridge.td new file mode 100644 index 0000000..6b7bbde --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedSandyBridge.td @@ -0,0 +1,1159 @@ +//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Sandy Bridge to support instruction +// scheduling and other instruction cost heuristics. +// +// Note that we define some instructions here that are not supported by SNB, +// but we still have to define them because SNB is the default subtarget for +// X86. These instructions are tagged with a comment `Unsupported = 1`. +// +//===----------------------------------------------------------------------===// + +def SandyBridgeModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and SB can decode 4 + // instructions per cycle. + // FIXME: Identify instructions that aren't a single fused micro-op. + let IssueWidth = 4; + let MicroOpBufferSize = 168; // Based on the reorder buffer. + let LoadLatency = 5; + let MispredictPenalty = 16; + + // Based on the LSD (loop-stream detector) queue size. + let LoopMicroOpBufferSize = 28; + + // This flag is set to allow the scheduler to assign + // a default model to unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = SandyBridgeModel in { + +// Sandy Bridge can issue micro-ops to 6 different ports in one cycle. + +// Ports 0, 1, and 5 handle all computation. +def SBPort0 : ProcResource<1>; +def SBPort1 : ProcResource<1>; +def SBPort5 : ProcResource<1>; + +// Ports 2 and 3 are identical. They handle loads and the address half of +// stores. +def SBPort23 : ProcResource<2>; + +// Port 4 gets the data half of stores. Store data can be available later than +// the store address, but since we don't model the latency of stores, we can +// ignore that. +def SBPort4 : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; +def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; +def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; +def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; + +// 54 Entry Unified Scheduler +def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> { + let BufferSize=54; +} + +// Integer division issued on port 0. +def SBDivider : ProcResource<1>; +// FP division and sqrt on port 0. +def SBFPDivider : ProcResource<1>; + +// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass SBWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 5> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to + // the latency (default = 5). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = !add(UOps, 1); + } +} + +// A folded store needs a cycle on port 4 for the store data, and an extra port +// 2/3 cycle to recompute the address. +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes { let Latency = 5; } +def : WriteRes; +def : WriteRes; + +// Arithmetic. +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; + +def : WriteRes { let Latency = 3; } + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; + +defm : SBWriteResPair; // Conditional move. +defm : SBWriteResPair; // Conditional (CF + ZF flag) move. +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} +def : WriteRes; +def : WriteRes; + +// This is for simple LEAs with one or two input operands. +// The complex ones can only execute on port 1, and they require two cycles on +// the port to read all inputs. We don't model that. +def : WriteRes; + +// Bit counts. +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; + +// BMI1 BEXTR, BMI2 BZHI +// NOTE: These don't exist on Sandy Bridge. Ports are guesses. +defm : SBWriteResPair; +defm : SBWriteResPair; + +// Scalar and vector floating point. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +// Conversion between integer and float. +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 + +defm : X86WriteRes; +defm : X86WriteRes; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 + +defm : SBWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 + +// Vector integer operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; // TODO this is probably wrong for 256/512-bit for the "generic" model +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; + +// Vector integer shifts. +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +// Vector insert/extract operations. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 7; + let NumMicroOps = 2; +} + +def : WriteRes { + let Latency = 3; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 5; + let NumMicroOps = 3; +} + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +//////////////////////////////////////////////////////////////////////////////// +// String instructions. +//////////////////////////////////////////////////////////////////////////////// + +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 17; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 11; + let ResourceCycles = [8]; +} +def : WriteRes { + let Latency = 11; + let ResourceCycles = [7, 1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 17; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 4; + let ResourceCycles = [8]; +} +def : WriteRes { + let Latency = 4; + let ResourceCycles = [7, 1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 1; } + +// AES Instructions. +def : WriteRes { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def : WriteRes { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} + +def : WriteRes { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 18; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} + +def : WriteRes { + let Latency = 8; + let ResourceCycles = [11]; +} +def : WriteRes { + let Latency = 8; + let ResourceCycles = [10, 1]; +} + +// Carry-less multiplication instructions. +def : WriteRes { + let Latency = 14; + let ResourceCycles = [18]; +} +def : WriteRes { + let Latency = 14; + let ResourceCycles = [17, 1]; +} + +// Load/store MXCSR. +// FIXME: This is probably wrong. Only STMXCSR should require Port4. +def : WriteRes { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } +def : WriteRes { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } + +def : WriteRes { let Latency = 100; } +def : WriteRes { let Latency = 100; } +def : WriteRes; +def : WriteRes; + +// AVX2/FMA is not supported on that architecture, but we should define the basic +// scheduling resources anyway. +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +// Remaining SNB instrs. + +def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r, + COM_FST0r, + UCOM_FPr, + UCOM_Fr)>; + +def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP, + LD_Frr, ST_Frr, ST_FPrr)>; +def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs. +def: InstRW<[SBWriteResGroup2], (instrs RETQ)>; + +def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>; + +def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABS(B|D|W)rr", + "MMX_PADDQirr", + "MMX_PALIGNRrri", + "MMX_PSIGN(B|D|W)rr")>; + +def SBWriteResGroup9 : SchedWriteRes<[SBPort05]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SBWriteResGroup9], (instregex "ROL(8|16|32|64)r1", + "ROL(8|16|32|64)ri", + "ROR(8|16|32|64)r1", + "ROR(8|16|32|64)ri", + "SET(A|BE)r")>; + +def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SBWriteResGroup11], (instrs SCASB, + SCASL, + SCASQ, + SCASW)>; + +def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup12], (instregex "(V?)COMISDrr", + "(V?)COMISSrr", + "(V?)UCOMISDrr", + "(V?)UCOMISSrr")>; + +def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup15], (instrs CWD, + FNSTSW16r)>; + +def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ)>; +def: InstRW<[SBWriteResGroup18], (instregex "MMX_MOVDQ2Qrr")>; + +def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup21], (instregex "PUSHFS64")>; + +def SBWriteResGroup21_16i : SchedWriteRes<[SBPort1, SBPort015]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup21_16i], (instrs IMUL16rri, IMUL16rri8)>; + +def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> { + let Latency = 3; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>; + +def SBWriteResGroup23_2 : SchedWriteRes<[SBPort05]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SBWriteResGroup23_2], (instregex "ROL(8|16|32|64)rCL", + "ROR(8|16|32|64)rCL", + "SAR(8|16|32|64)rCL", + "SHL(8|16|32|64)rCL", + "SHR(8|16|32|64)rCL")>; + +def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SBWriteResGroup25], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr, + XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr, + XCHG16ar, XCHG32ar, XCHG64ar)>; + +def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>; + +def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; + +def SBWriteResGroup27 : SchedWriteRes<[SBPort0,SBPort1]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup27], (instrs IMUL64r, MUL64r)>; + +def SBWriteResGroup27_1 : SchedWriteRes<[SBPort1,SBPort05,SBPort015]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup27_1], (instrs IMUL32r, MUL32r)>; + +def SBWriteResGroup27_2 : SchedWriteRes<[SBPort1,SBPort05,SBPort015]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup27_2], (instrs IMUL16r, MUL16r)>; + +def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup29], (instregex "MOV64sr")>; + +def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>; + +def SBWriteResGroup30 : SchedWriteRes<[SBPort0]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup30], (instregex "(V?)PCMPGTQrr")>; + +def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm(8|16|32)", + "MOVZX(16|32|64)rm(8|16)")>; + +def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>; + +def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup35], (instrs CLI)>; + +def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m", + "PUSHGS64")>; + +def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>; +def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r", + "(V?)EXTRACTPSmr")>; + +def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>; + +def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>; + +def SBWriteResGroup42 : SchedWriteRes<[SBPort05,SBPort015]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG(8|16|32|64)rr")>; + +def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup43], (instregex "SET(A|BE)m")>; + +def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr", + "PUSHF(16|64)")>; + +def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>; + +def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>; + +def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup48], (instregex "MMX_MOVD64from64rm", + "POP(16|32|64)r", + "VBROADCASTSSrm", + "(V?)MOV64toPQIrm", + "(V?)MOVDDUPrm", + "(V?)MOVDI2PDIrm", + "(V?)MOVQI2PQIrm", + "(V?)MOVSDrm", + "(V?)MOVSHDUPrm", + "(V?)MOVSLDUPrm", + "(V?)MOVSSrm")>; + +def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup49], (instregex "MOV16sm")>; + +def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort05]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup50], (instregex "BT(16|32|64)mi8")>; + +def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABS(B|D|W)rm", + "MMX_PALIGNRrmi", + "MMX_PSIGN(B|D|W)rm")>; + +def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup52], (instrs LODSL, LODSQ)>; + +def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> { + let Latency = 6; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m", + "ST_FP(32|64|80)m")>; + +def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> { + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSDYrm", + "VBROADCASTSSYrm", + "VMOVDDUPYrm", + "VMOVSHDUPYrm", + "VMOVSLDUPYrm")>; + +def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup58], (instrs VINSERTF128rm)>; + +def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup59], (instregex "MMX_PADDQirm")>; + +def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SBWriteResGroup62], (instregex "VER(R|W)m")>; + +def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>; + +def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup64], (instrs FARJMP64)>; + +def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup66], (instrs FNSTSWm)>; + +def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r", + "STR(16|32|64)r")>; + +def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup68], (instrs FNSTCW16m)>; +def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>; + +def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SBWriteResGroup69], (instregex "BTC(16|32|64)mi8", + "BTR(16|32|64)mi8", + "BTS(16|32|64)mi8", + "SAR(8|16|32|64)m1", + "SAR(8|16|32|64)mi", + "SHL(8|16|32|64)m1", + "SHL(8|16|32|64)mi", + "SHR(8|16|32|64)m1", + "SHR(8|16|32|64)mi")>; + +def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>; + +def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 8; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16|32|64)rm")>; + +def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [2,3]; +} +def: InstRW<[SBWriteResGroup83], (instrs CMPSB, + CMPSL, + CMPSQ, + CMPSW)>; + +def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,2,2]; +} +def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>; + +def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,2,2]; +} +def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m1", + "ROL(8|16|32|64)mi", + "ROR(8|16|32|64)m1", + "ROR(8|16|32|64)mi")>; + +def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,2,2]; +} +def: InstRW<[SBWriteResGroup86], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; +def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>; + +def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SBWriteResGroup87], (instrs FARCALL64)>; + +def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)SD2SI(64)?rm", + "CVT(T?)SS2SI(64)?rm")>; + +def SBWriteResGroup93_1 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup93_1], (instrs IMUL64m, MUL64m)>; + +def SBWriteResGroup93_2 : SchedWriteRes<[SBPort1,SBPort23,SBPort05,SBPort015]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SBWriteResGroup93_2], (instrs IMUL32m, MUL32m)>; + +def SBWriteResGroup93_3 : SchedWriteRes<[SBPort1,SBPort05,SBPort015,SBPort23]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[SBWriteResGroup93_3], (instrs IMUL16m, MUL16m)>; + +def SBWriteResGroup93_4 : SchedWriteRes<[SBPort1,SBPort015,SBPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup93_4], (instrs IMUL16rmi, IMUL16rmi8)>; + +def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>; + +def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m", + "IST_FP(16|32|64)m")>; + +def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,2,3]; +} +def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL", + "ROR(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; + +def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,2,3]; +} +def: SchedAlias; + +def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,2,2,1]; +} +def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr, + SBB8mr, SBB16mr, SBB32mr, SBB64mr)>; + +def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,1,2,1,1]; +} +def: InstRW<[SBWriteResGroup100], (instregex "BT(16|32|64)mr", + "BTC(16|32|64)mr", + "BTR(16|32|64)mr", + "BTS(16|32|64)mr")>; + +def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", + "ILD_F(16|32|64)m")>; + +def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>; + +def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>; + +def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m")>; + +def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; + +def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 15; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>; + +def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 31; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>; + +def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 34; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>; + +def: InstRW<[WriteZero], (instrs CLC)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedSkylakeClient.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedSkylakeClient.td new file mode 100644 index 0000000..bda088e --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedSkylakeClient.td @@ -0,0 +1,1850 @@ +//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Skylake Client to support +// instruction scheduling and other instruction cost heuristics. +// +//===----------------------------------------------------------------------===// + +def SkylakeClientModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and SKylake can + // decode 6 instructions per cycle. + let IssueWidth = 6; + let MicroOpBufferSize = 224; // Based on the reorder buffer. + let LoadLatency = 5; + let MispredictPenalty = 14; + + // Based on the LSD (loop-stream detector) queue size and benchmarking data. + let LoopMicroOpBufferSize = 50; + + // This flag is set to allow the scheduler to assign a default model to + // unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = SkylakeClientModel in { + +// Skylake Client can issue micro-ops to 8 different ports in one cycle. + +// Ports 0, 1, 5, and 6 handle all computation. +// Port 4 gets the data half of stores. Store data can be available later than +// the store address, but since we don't model the latency of stores, we can +// ignore that. +// Ports 2 and 3 are identical. They handle loads and the address half of +// stores. Port 7 can handle address calculations. +def SKLPort0 : ProcResource<1>; +def SKLPort1 : ProcResource<1>; +def SKLPort2 : ProcResource<1>; +def SKLPort3 : ProcResource<1>; +def SKLPort4 : ProcResource<1>; +def SKLPort5 : ProcResource<1>; +def SKLPort6 : ProcResource<1>; +def SKLPort7 : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>; +def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>; +def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>; +def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>; +def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>; +def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>; +def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>; +def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>; +def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>; +def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>; +def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>; +def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>; + +def SKLDivider : ProcResource<1>; // Integer division issued on port 0. +// FP division and sqrt on port 0. +def SKLFPDivider : ProcResource<1>; + +// 60 Entry Unified Scheduler +def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4, + SKLPort5, SKLPort6, SKLPort7]> { + let BufferSize=60; +} + +// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass SKLWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 5> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to + // the latency (default = 5). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = !add(UOps, 1); + } +} + +// A folded store needs a cycle on port 4 for the store data, and an extra port +// 2/3/7 cycle to recompute the address. +def : WriteRes; + +// Arithmetic. +defm : SKLWriteResPair; // Simple integer ALU op. +defm : SKLWriteResPair; // Integer ALU + flags op. +defm : SKLWriteResPair; // Integer multiplication. +defm : SKLWriteResPair; // Integer 64-bit multiplication. + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; + +defm : SKLWriteResPair; + +def : WriteRes { let Latency = 3; } // Integer multiplication, high part. +def : WriteRes; // LEA instructions can't fold loads. + +defm : SKLWriteResPair; // Conditional move. +defm : SKLWriteResPair; // Conditional (CF + ZF flag) move. +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} +def : WriteRes; +def : WriteRes; // + +// Bit counts. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; + +// Integer shifts and rotates. +defm : SKLWriteResPair; + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// BMI1 BEXTR, BMI2 BZHI +defm : SKLWriteResPair; +defm : SKLWriteResPair; + +// Loads, stores, and moves, not folded with other operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +def : WriteRes; + +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +defm : SKLWriteResPair; + +// Floating point. This covers both scalar and vector operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKLWriteResPair; // Floating point add/sub. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point double add/sub. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Floating point compare. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point double compare. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Floating point compare to flags. + +defm : SKLWriteResPair; // Floating point multiplication. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point double multiplication. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Floating point division. +//defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +//defm : SKLWriteResPair; // Floating point double division. +//defm : SKLWriteResPair; +//defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Floating point square root. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point double square root. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point long double square root. + +defm : SKLWriteResPair; // Floating point reciprocal estimate. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Floating point reciprocal square root estimate. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Fused Multiply Add. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point double dot product. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point fabs/fchs. +defm : SKLWriteResPair; // Floating point rounding. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point and/or/xor logicals. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point TEST instructions. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point vector shuffles. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point vector shuffles. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point vector blends. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Fp vector variable blends. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +// FMA Scheduling helper class. +// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } + +// Vector integer operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKLWriteResPair; // Vector integer ALU op, no logicals. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector integer and/or/xor. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector integer TEST instructions. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector integer multiply. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector PMULLD. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector shuffles. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector shuffles. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector blends. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector variable blends. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector MPSAD. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector PSADBW. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector PHMINPOS. + +// Vector integer shifts. +defm : SKLWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Vector integer immediate shifts. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Variable vector shifts. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +// Vector insert/extract operations. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 6; + let NumMicroOps = 2; +} +def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; + +def : WriteRes { + let Latency = 3; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + +// Conversion between integer and float. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; + +// Strings instructions. + +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 19; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} +def : WriteRes { + let Latency = 25; + let NumMicroOps = 10; + let ResourceCycles = [4,3,1,1,1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [4,3,1]; +} +def : WriteRes { + let Latency = 24; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } + +// AES instructions. +def : WriteRes { // Decryption, encryption. + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +def : WriteRes { // InvMixColumn. + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} + +def : WriteRes { // Key Generation. + let Latency = 20; + let NumMicroOps = 11; + let ResourceCycles = [3,6,2]; +} +def : WriteRes { + let Latency = 25; + let NumMicroOps = 11; + let ResourceCycles = [3,6,1,1]; +} + +// Carry-less multiplication instructions. +def : WriteRes { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +// Catch-all for expensive system instructions. +def : WriteRes { let Latency = 100; } // def WriteSystem : SchedWrite; + +// AVX2. +defm : SKLWriteResPair; // Fp 256-bit width vector shuffles. +defm : SKLWriteResPair; // Fp 256-bit width vector variable shuffles. +defm : SKLWriteResPair; // 256-bit width vector shuffles. +defm : SKLWriteResPair; // 256-bit width vector variable shuffles. + +// Old microcoded instructions that nobody use. +def : WriteRes { let Latency = 100; } // def WriteMicrocoded : SchedWrite; + +// Fence instructions. +def : WriteRes; + +// Load/store MXCSR. +def : WriteRes { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } +def : WriteRes { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } + +// Nop, not very useful expect it provides a model for nops! +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; + +// Remaining instrs. + +def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr", + "MMX_PADDUS(B|W)irr", + "MMX_PAVG(B|W)irr", + "MMX_PCMPEQ(B|D|W)irr", + "MMX_PCMPGT(B|D|W)irr", + "MMX_P(MAX|MIN)SWirr", + "MMX_P(MAX|MIN)UBirr", + "MMX_PSUBS(B|W)irr", + "MMX_PSUBUS(B|W)irr")>; + +def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r", + "UCOM_F(P?)r")>; + +def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>; + +def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>; + +def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; + +def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr", + "BLSI(32|64)rr", + "BLSMSK(32|64)rr", + "BLSR(32|64)rr")>; + +def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr", + "VPBLENDD(Y?)rri", + "(V?)PSUB(B|D|Q|W)(Y?)rr")>; + +def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE, + CMC, STC)>; +def: InstRW<[SKLWriteResGroup10], (instregex "SGDT64m", + "SIDT64m", + "SMSW16m", + "STRm", + "SYSCALL")>; + +def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm", + "ST_FP(32|64|80)m", + "VMPTRSTm")>; + +def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>; + +def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP)>; +def: InstRW<[SKLWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>; + +def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKLWriteResGroup15], (instregex "ROL(8|16|32|64)r1", + "ROL(8|16|32|64)ri", + "ROR(8|16|32|64)r1", + "ROR(8|16|32|64)ri", + "SET(A|BE)r")>; + +def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKLWriteResGroup17], (instrs LFENCE, + WAIT, + XGETBV)>; + +def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>; + +def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>; + +def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup23], (instrs CWD)>; +def: InstRW<[SKLWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>; +def: InstRW<[SKLWriteResGroup23], (instregex "ADC8i8", + "ADC8ri", + "SBB8i8", + "SBB8ri")>; + +def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>; + +def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; + +def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, + STOSB, STOSL, STOSQ, STOSW)>; +def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr", + "PUSH64i8")>; + +def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr", + "PEXT(32|64)rr")>; + +def SKLWriteResGroup29_16i : SchedWriteRes<[SKLPort1, SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup29_16i], (instrs IMUL16rri, IMUL16rri8)>; + +def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", + "VPBROADCASTBrr", + "VPBROADCASTWrr", + "(V?)PCMPGTQ(Y?)rr")>; + +def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>; + +def SKLWriteResGroup33 : SchedWriteRes<[SKLPort06]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SKLWriteResGroup33], (instregex "ROL(8|16|32|64)rCL", + "ROR(8|16|32|64)rCL", + "SAR(8|16|32|64)rCL", + "SHL(8|16|32|64)rCL", + "SHR(8|16|32|64)rCL")>; + +def SKLWriteResGroup34 : SchedWriteRes<[SKLPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SKLWriteResGroup34], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr, + XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr, + XCHG16ar, XCHG32ar, XCHG64ar)>; + +def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>; + +def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr", + "(V?)PHSUBSW(Y?)rr")>; + +def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKSSDWirr", + "MMX_PACKSSWBirr", + "MMX_PACKUSWBirr")>; + +def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>; + +def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>; + +def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r1", + "RCL(8|16|32|64)ri", + "RCR(8|16|32|64)r1", + "RCR(8|16|32|64)ri")>; + +def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>; + +def SKLWriteResGroup44 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SKLWriteResGroup44], (instregex "SET(A|BE)m")>; + +def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>; + +def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>; + +def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; + +def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr", + "(V?)CVT(T?)PS2DQ(Y?)rr")>; + +def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup51], (instrs IMUL64r, MUL64r, MULX64rr)>; + +def SKLWriteResGroup51_16 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SKLWriteResGroup51_16], (instrs IMUL16r, MUL16r)>; + +def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m", + "IST_F(16|32)m")>; + +def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [4]; +} +def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>; + +def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>; + +def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>; + +def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>; + +def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm16", + "MOVSX(16|32|64)rm32", + "MOVSX(16|32|64)rm8", + "MOVZX(16|32|64)rm16", + "MOVZX(16|32|64)rm8", + "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67? + +def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup59], (instregex "MMX_CVTPI2PDirr", + "(V?)CVTDQ2PDrr")>; + +def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", + "(V?)CVT(T?)PD2DQrr", + "(V?)CVTPD2PSrr", + "(V?)CVTPS2PDrr", + "(V?)CVTSD2SSrr", + "(V?)CVTSI642SDrr", + "(V?)CVTSI2SDrr", + "(V?)CVTSI2SSrr", + "(V?)CVTSS2SDrr")>; + +def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>; + +def SKLWriteResGroup62 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup62], (instrs IMUL32r, MUL32r, MULX32rr)>; + +def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>; + +def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [2,3]; +} +def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(8|16|32|64)rr")>; + +def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { + let Latency = 5; + let NumMicroOps = 6; + let ResourceCycles = [1,1,4]; +} +def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>; + +def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup67], (instregex "VBROADCASTSSrm", + "(V?)MOVSHDUPrm", + "(V?)MOVSLDUPrm", + "VPBROADCASTDrm", + "VPBROADCASTQrm")>; + +def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKLWriteResGroup68], (instregex "MMX_CVTPI2PSirr")>; + +def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm", + "MMX_PADDSWirm", + "MMX_PADDUSBirm", + "MMX_PADDUSWirm", + "MMX_PAVGBirm", + "MMX_PAVGWirm", + "MMX_PCMPEQBirm", + "MMX_PCMPEQDirm", + "MMX_PCMPEQWirm", + "MMX_PCMPGTBirm", + "MMX_PCMPGTDirm", + "MMX_PCMPGTWirm", + "MMX_PMAXSWirm", + "MMX_PMAXUBirm", + "MMX_PMINSWirm", + "MMX_PMINUBirm", + "MMX_PSUBSBirm", + "MMX_PSUBSWirm", + "MMX_PSUBUSBirm", + "MMX_PSUBUSWirm")>; + +def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr", + "(V?)CVT(T?)SD2SI(64)?rr")>; + +def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup72], (instregex "FARJMP64", + "JMP(16|32|64)m")>; + +def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>; + +def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm", + "BLSI(32|64)rm", + "BLSMSK(32|64)rm", + "BLSR(32|64)rm", + "MOVBE(16|32|64)rm")>; + +def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>; +def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>; + +def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> { + let Latency = 6; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>; + +def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>; + +def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup82], (instregex "BTC(16|32|64)mi8", + "BTR(16|32|64)mi8", + "BTS(16|32|64)mi8", + "SAR(8|16|32|64)m1", + "SAR(8|16|32|64)mi", + "SHL(8|16|32|64)m1", + "SHL(8|16|32|64)mi", + "SHR(8|16|32|64)m1", + "SHR(8|16|32|64)mi")>; + +def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm", + "PUSH(16|32|64)rmm")>; + +def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> { + let Latency = 6; + let NumMicroOps = 6; + let ResourceCycles = [1,5]; +} +def: InstRW<[SKLWriteResGroup84], (instrs STD)>; + +def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> { + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m", + "VBROADCASTF128", + "VBROADCASTI128", + "VBROADCASTSDYrm", + "VBROADCASTSSYrm", + "VMOVDDUPYrm", + "VMOVSHDUPYrm", + "VMOVSLDUPYrm", + "VPBROADCASTDYrm", + "VPBROADCASTQYrm")>; + +def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup86], (instregex "VCVTDQ2PDYrr")>; + +def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm", + "(V?)PMOV(SX|ZX)BQrm", + "(V?)PMOV(SX|ZX)BWrm", + "(V?)PMOV(SX|ZX)DQrm", + "(V?)PMOV(SX|ZX)WDrm", + "(V?)PMOV(SX|ZX)WQrm")>; + +def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2PSYrr", + "VCVTPS2PDYrr", + "VCVT(T?)PD2DQYrr")>; + +def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup91], (instregex "(V?)INSERTF128rm", + "(V?)INSERTI128rm", + "(V?)PADD(B|D|Q|W)rm", + "(V?)PBLENDDrmi", + "(V?)PSUB(B|D|Q|W)rm")>; + +def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSDWirm", + "MMX_PACKSSWBirm", + "MMX_PACKUSWBirm")>; + +def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64, + SCASB, SCASL, SCASQ, SCASW)>; + +def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>; + +def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>; + +def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>; + +def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m1", + "ROL(8|16|32|64)mi", + "ROR(8|16|32|64)m1", + "ROR(8|16|32|64)mi")>; + +def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>; + +def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m", + "FARCALL64")>; + +def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 7; + let NumMicroOps = 7; + let ResourceCycles = [1,3,1,2]; +} +def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>; + +def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm", + "PEXT(32|64)rm")>; + +def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup107_16], (instrs IMUL16rmi, IMUL16rmi8)>; + +def SKLWriteResGroup107_16_2 : SchedWriteRes<[SKLPort1, SKLPort06, SKLPort0156, SKLPort23]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[SKLWriteResGroup107_16_2], (instrs IMUL16m, MUL16m)>; + +def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m", + "VPBROADCASTBYrm", + "VPBROADCASTWYrm", + "VPMOVSXBDYrm", + "VPMOVSXBQYrm", + "VPMOVSXWQYrm")>; + +def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup110], (instregex "VPADD(B|D|Q|W)Yrm", + "VPBLENDDYrmi", + "VPSUB(B|D|Q|W)Yrm")>; + +def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 8; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>; + +def SKLWriteResGroup115 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,3]; +} +def: InstRW<[SKLWriteResGroup115], (instregex "ROR(8|16|32|64)mCL")>; + +def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m1", + "RCL(8|16|32|64)mi", + "RCR(8|16|32|64)m1", + "RCR(8|16|32|64)mi")>; + +def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,3]; +} +def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; + +def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,2,1]; +} +def: SchedAlias; +def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(8|16|32|64)rm")>; + +def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm")>; + +def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup121], (instregex "(V?)PCMPGTQrm", + "VPMOVSXBWYrm", + "VPMOVSXDQYrm", + "VPMOVSXWDYrm", + "VPMOVZXWDYrm")>; + +def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm", + "(V?)CVTPS2PDrm")>; + +def SKLWriteResGroup127 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup127], (instrs IMUL64m, MUL64m, MULX64rm)>; + +def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm", + "(V?)PHSUBSWrm")>; + +def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm", + "LSL(16|32|64)rm")>; + +def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m", + "ILD_F(16|32|64)m", + "VPCMPGTQYrm")>; + +def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm", + "(V?)CVTPS2DQrm", + "(V?)CVTSS2SDrm", + "(V?)CVTTPS2DQrm")>; + +def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm")>; + +def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>; + +def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { + let Latency = 10; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKLWriteResGroup140], (instregex "VPHADDSWYrm", + "VPHSUBSWYrm")>; + +def SKLWriteResGroup142 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort06,SKLPort0156]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup142], (instrs IMUL32m, MUL32m, MULX32rm)>; + +def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 10; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,3]; +} +def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>; + +def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { + let Latency = 11; + let NumMicroOps = 1; + let ResourceCycles = [1,3]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>; + +def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup147], (instregex "VCVTDQ2PSYrm", + "VCVTPS2PDYrm", + "VCVT(T?)PS2DQYrm")>; + +def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>; + +def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>; + +def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm", + "(V?)CVT(T?)SD2SI(64)?rm", + "VCVTTSS2SI64rm", + "(V?)CVT(T?)SS2SIrm")>; + +def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2PSrm", + "CVT(T?)PD2DQrm", + "MMX_CVT(T?)PD2PIirm")>; + +def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { + let Latency = 11; + let NumMicroOps = 7; + let ResourceCycles = [2,3,2]; +} +def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL", + "RCR(16|32|64)rCL")>; + +def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 11; + let NumMicroOps = 9; + let ResourceCycles = [1,5,1,2]; +} +def: InstRW<[SKLWriteResGroup155], (instregex "RCL8rCL")>; + +def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> { + let Latency = 11; + let NumMicroOps = 11; + let ResourceCycles = [2,9]; +} +def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>; + +def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> { + let Latency = 12; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>; + +def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; + +def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup163], (instregex "VCVTDQ2PDYrm")>; + +def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1,3]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1,5]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>; + +def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 14; + let NumMicroOps = 10; + let ResourceCycles = [2,4,1,3]; +} +def: InstRW<[SKLWriteResGroup170], (instregex "RCR8rCL")>; + +def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> { + let Latency = 15; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; + +def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 15; + let NumMicroOps = 10; + let ResourceCycles = [1,1,1,5,1,1]; +} +def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>; + +def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 16; + let NumMicroOps = 14; + let ResourceCycles = [1,1,1,4,2,5]; +} +def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>; + +def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> { + let Latency = 16; + let NumMicroOps = 16; + let ResourceCycles = [16]; +} +def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>; + +def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { + let Latency = 17; + let NumMicroOps = 2; + let ResourceCycles = [1,1,5]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> { + let Latency = 17; + let NumMicroOps = 15; + let ResourceCycles = [2,1,2,4,2,4]; +} +def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>; + +def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,5]; +} +def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>; + +def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 18; + let NumMicroOps = 11; + let ResourceCycles = [2,1,1,4,1,2]; +} +def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>; + +def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { + let Latency = 19; + let NumMicroOps = 2; + let ResourceCycles = [1,1,4]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> { + let Latency = 20; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; + +def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { + let Latency = 20; + let NumMicroOps = 2; + let ResourceCycles = [1,1,4]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 20; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,1,2]; +} +def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>; + +def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> { + let Latency = 20; + let NumMicroOps = 10; + let ResourceCycles = [1,2,7]; +} +def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>; + +def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { + let Latency = 21; + let NumMicroOps = 2; + let ResourceCycles = [1,1,8]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> { + let Latency = 22; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>; + +def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { + let Latency = 22; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm, + VGATHERDPDrm, + VGATHERQPDrm, + VGATHERQPSrm, + VPGATHERDDrm, + VPGATHERDQrm, + VPGATHERQDrm, + VPGATHERQQrm)>; + +def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { + let Latency = 25; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm, + VGATHERQPDYrm, + VGATHERQPSYrm, + VPGATHERDDYrm, + VPGATHERDQYrm, + VPGATHERQDYrm, + VPGATHERQQYrm, + VGATHERDPDYrm)>; + +def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 23; + let NumMicroOps = 19; + let ResourceCycles = [2,1,4,1,1,4,6]; +} +def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>; + +def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 25; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>; + +def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> { + let Latency = 27; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>; + +def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> { + let Latency = 28; + let NumMicroOps = 8; + let ResourceCycles = [2,4,1,1]; +} +def: InstRW<[SKLWriteResGroup207], (instregex "IDIV(8|16|32|64)m")>; + +def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 30; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>; + +def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,3,4,10]; +} +def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri", + "IN(8|16|32)rr")>; + +def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,2,1,4,10]; +} +def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir", + "OUT(8|16|32)rr")>; + +def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { + let Latency = 37; + let NumMicroOps = 31; + let ResourceCycles = [1,8,1,21]; +} +def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>; + +def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> { + let Latency = 40; + let NumMicroOps = 18; + let ResourceCycles = [1,1,2,3,1,1,1,8]; +} +def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>; + +def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { + let Latency = 41; + let NumMicroOps = 39; + let ResourceCycles = [1,10,1,1,26]; +} +def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>; + +def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> { + let Latency = 42; + let NumMicroOps = 22; + let ResourceCycles = [2,20]; +} +def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>; + +def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { + let Latency = 42; + let NumMicroOps = 40; + let ResourceCycles = [1,11,1,1,26]; +} +def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>; +def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>; + +def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { + let Latency = 46; + let NumMicroOps = 44; + let ResourceCycles = [1,11,1,1,30]; +} +def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>; + +def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> { + let Latency = 62; + let NumMicroOps = 64; + let ResourceCycles = [2,8,5,10,39]; +} +def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>; + +def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 63; + let NumMicroOps = 88; + let ResourceCycles = [4,4,31,1,2,1,45]; +} +def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>; + +def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 63; + let NumMicroOps = 90; + let ResourceCycles = [4,2,33,1,2,1,47]; +} +def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>; + +def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> { + let Latency = 75; + let NumMicroOps = 15; + let ResourceCycles = [6,3,6]; +} +def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>; + +def SKLWriteResGroup221 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> { + let Latency = 76; + let NumMicroOps = 32; + let ResourceCycles = [7,2,8,3,1,11]; +} +def: InstRW<[SKLWriteResGroup221], (instregex "DIV(16|32|64)r")>; + +def SKLWriteResGroup222 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> { + let Latency = 102; + let NumMicroOps = 66; + let ResourceCycles = [4,2,4,8,14,34]; +} +def: InstRW<[SKLWriteResGroup222], (instregex "IDIV(16|32|64)r")>; + +def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 106; + let NumMicroOps = 100; + let ResourceCycles = [9,1,11,16,1,11,21,30]; +} +def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>; + +def: InstRW<[WriteZero], (instrs CLC)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedSkylakeServer.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedSkylakeServer.td new file mode 100644 index 0000000..9d5f855 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86SchedSkylakeServer.td @@ -0,0 +1,2580 @@ +//=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Skylake Server to support +// instruction scheduling and other instruction cost heuristics. +// +//===----------------------------------------------------------------------===// + +def SkylakeServerModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and SKylake can + // decode 6 instructions per cycle. + let IssueWidth = 6; + let MicroOpBufferSize = 224; // Based on the reorder buffer. + let LoadLatency = 5; + let MispredictPenalty = 14; + + // Based on the LSD (loop-stream detector) queue size and benchmarking data. + let LoopMicroOpBufferSize = 50; + + // This flag is set to allow the scheduler to assign a default model to + // unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = SkylakeServerModel in { + +// Skylake Server can issue micro-ops to 8 different ports in one cycle. + +// Ports 0, 1, 5, and 6 handle all computation. +// Port 4 gets the data half of stores. Store data can be available later than +// the store address, but since we don't model the latency of stores, we can +// ignore that. +// Ports 2 and 3 are identical. They handle loads and the address half of +// stores. Port 7 can handle address calculations. +def SKXPort0 : ProcResource<1>; +def SKXPort1 : ProcResource<1>; +def SKXPort2 : ProcResource<1>; +def SKXPort3 : ProcResource<1>; +def SKXPort4 : ProcResource<1>; +def SKXPort5 : ProcResource<1>; +def SKXPort6 : ProcResource<1>; +def SKXPort7 : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def SKXPort01 : ProcResGroup<[SKXPort0, SKXPort1]>; +def SKXPort23 : ProcResGroup<[SKXPort2, SKXPort3]>; +def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>; +def SKXPort04 : ProcResGroup<[SKXPort0, SKXPort4]>; +def SKXPort05 : ProcResGroup<[SKXPort0, SKXPort5]>; +def SKXPort06 : ProcResGroup<[SKXPort0, SKXPort6]>; +def SKXPort15 : ProcResGroup<[SKXPort1, SKXPort5]>; +def SKXPort16 : ProcResGroup<[SKXPort1, SKXPort6]>; +def SKXPort56 : ProcResGroup<[SKXPort5, SKXPort6]>; +def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>; +def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>; +def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>; + +def SKXDivider : ProcResource<1>; // Integer division issued on port 0. +// FP division and sqrt on port 0. +def SKXFPDivider : ProcResource<1>; + +// 60 Entry Unified Scheduler +def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4, + SKXPort5, SKXPort6, SKXPort7]> { + let BufferSize=60; +} + +// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass SKXWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 5> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to + // the latency (default = 5). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = !add(UOps, 1); + } +} + +// A folded store needs a cycle on port 4 for the store data, and an extra port +// 2/3/7 cycle to recompute the address. +def : WriteRes; + +// Arithmetic. +defm : SKXWriteResPair; // Simple integer ALU op. +defm : SKXWriteResPair; // Integer ALU + flags op. +defm : SKXWriteResPair; // Integer multiplication. +defm : SKXWriteResPair; // Integer 64-bit multiplication. + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; + +def : WriteRes { let Latency = 3; } // Integer multiplication, high part. +def : WriteRes; // LEA instructions can't fold loads. + +defm : SKXWriteResPair; // Conditional move. +defm : SKXWriteResPair; // Conditional (CF + ZF flag) move. +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} +def : WriteRes; +def : WriteRes; // + +// Integer shifts and rotates. +defm : SKXWriteResPair; + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Bit counts. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +// BMI1 BEXTR, BMI2 BZHI +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +// Loads, stores, and moves, not folded with other operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +def : WriteRes; + +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +defm : SKXWriteResPair; + +// Floating point. This covers both scalar and vector operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKXWriteResPair; // Floating point add/sub. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point double add/sub. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; // Floating point compare. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point double compare. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; // Floating point compare to flags. + +defm : SKXWriteResPair; // Floating point multiplication. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point double multiplication. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; // 10-14 cycles. // Floating point division. +//defm : SKXWriteResPair; // 10-14 cycles. +defm : SKXWriteResPair; // 10-14 cycles. +defm : SKXWriteResPair; // 10-14 cycles. +//defm : SKXWriteResPair; // 10-14 cycles. // Floating point division. +//defm : SKXWriteResPair; // 10-14 cycles. +//defm : SKXWriteResPair; // 10-14 cycles. +defm : SKXWriteResPair; // 10-14 cycles. + +defm : SKXWriteResPair; // Floating point square root. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point double square root. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point long double square root. + +defm : SKXWriteResPair; // Floating point reciprocal estimate. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; // Floating point reciprocal square root estimate. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; // Fused Multiply Add. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point double dot product. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point fabs/fchs. +defm : SKXWriteResPair; // Floating point rounding. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point and/or/xor logicals. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point TEST instructions. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point vector shuffles. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point vector variable shuffles. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point vector blends. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Fp vector variable blends. +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +// FMA Scheduling helper class. +// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } + +// Vector integer operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKXWriteResPair; // Vector integer ALU op, no logicals. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector integer and/or/xor. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector integer TEST instructions. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector integer multiply. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector PMULLD. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector shuffles. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector variable shuffles. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector blends. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector variable blends. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector MPSAD. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector PSADBW. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector PHMINPOS. + +// Vector integer shifts. +defm : SKXWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector integer immediate shifts. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Variable vector shifts. +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +// Vector insert/extract operations. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 6; + let NumMicroOps = 2; +} +def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; + +def : WriteRes { + let Latency = 3; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + +// Conversion between integer and float. +defm : SKXWriteResPair; // Needs more work: DD vs DQ. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Needs more work: DD vs DQ. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Strings instructions. + +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 19; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} +def : WriteRes { + let Latency = 25; + let NumMicroOps = 10; + let ResourceCycles = [4,3,1,1,1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [4,3,1]; +} +def : WriteRes { + let Latency = 24; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } + +// AES instructions. +def : WriteRes { // Decryption, encryption. + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +def : WriteRes { // InvMixColumn. + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} + +def : WriteRes { // Key Generation. + let Latency = 20; + let NumMicroOps = 11; + let ResourceCycles = [3,6,2]; +} +def : WriteRes { + let Latency = 25; + let NumMicroOps = 11; + let ResourceCycles = [3,6,1,1]; +} + +// Carry-less multiplication instructions. +def : WriteRes { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +// Catch-all for expensive system instructions. +def : WriteRes { let Latency = 100; } // def WriteSystem : SchedWrite; + +// AVX2. +defm : SKXWriteResPair; // Fp 256-bit width vector shuffles. +defm : SKXWriteResPair; // Fp 256-bit width vector variable shuffles. +defm : SKXWriteResPair; // 256-bit width vector shuffles. +defm : SKXWriteResPair; // 256-bit width vector variable shuffles. + +// Old microcoded instructions that nobody use. +def : WriteRes { let Latency = 100; } // def WriteMicrocoded : SchedWrite; + +// Fence instructions. +def : WriteRes; + +// Load/store MXCSR. +def : WriteRes { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } +def : WriteRes { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } + +// Nop, not very useful expect it provides a model for nops! +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +// Remaining instrs. + +def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr", + "KANDN(B|D|Q|W)rr", + "KMOV(B|D|Q|W)kk", + "KNOT(B|D|Q|W)rr", + "KOR(B|D|Q|W)rr", + "KXNOR(B|D|Q|W)rr", + "KXOR(B|D|Q|W)rr", + "MMX_PADDS(B|W)irr", + "MMX_PADDUS(B|W)irr", + "MMX_PAVG(B|W)irr", + "MMX_PCMPEQ(B|D|W)irr", + "MMX_PCMPGT(B|D|W)irr", + "MMX_P(MAX|MIN)SWirr", + "MMX_P(MAX|MIN)UBirr", + "MMX_PSUBS(B|W)irr", + "MMX_PSUBUS(B|W)irr", + "VPMOVB2M(Z|Z128|Z256)rr", + "VPMOVD2M(Z|Z128|Z256)rr", + "VPMOVQ2M(Z|Z128|Z256)rr", + "VPMOVW2M(Z|Z128|Z256)rr")>; + +def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r", + "KMOV(B|D|Q|W)kr", + "UCOM_F(P?)r")>; + +def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>; + +def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>; + +def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; + +def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr", + "BLSI(32|64)rr", + "BLSMSK(32|64)rr", + "BLSR(32|64)rr")>; + +def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr", + "VBLENDMPS(Z128|Z256)rr", + "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr", + "(V?)PADD(B|D|Q|W)rr", + "VPBLENDD(Y?)rri", + "VPBLENDMB(Z128|Z256)rr", + "VPBLENDMD(Z128|Z256)rr", + "VPBLENDMQ(Z128|Z256)rr", + "VPBLENDMW(Z128|Z256)rr", + "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rr", + "(V?)PSUB(B|D|Q|W)rr", + "VPTERNLOGD(Z|Z128|Z256)rri", + "VPTERNLOGQ(Z|Z128|Z256)rri")>; + +def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE, + CMC, STC)>; +def: InstRW<[SKXWriteResGroup10], (instregex "SGDT64m", + "SIDT64m", + "SMSW16m", + "STRm", + "SYSCALL")>; + +def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup11], (instregex "FBSTPm", + "KMOV(B|D|Q|W)mk", + "ST_FP(32|64|80)m", + "VMPTRSTm")>; + +def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>; + +def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP)>; +def: InstRW<[SKXWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>; + +def SKXWriteResGroup15 : SchedWriteRes<[SKXPort06]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup15], (instregex "ROL(8|16|32|64)r1", + "ROL(8|16|32|64)ri", + "ROR(8|16|32|64)r1", + "ROR(8|16|32|64)ri", + "SET(A|BE)r")>; + +def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup17], (instrs LFENCE, + WAIT, + XGETBV)>; + +def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>; + +def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>; + +def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup23], (instrs CWD)>; +def: InstRW<[SKXWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>; +def: InstRW<[SKXWriteResGroup23], (instregex "ADC8i8", + "ADC8ri", + "SBB8i8", + "SBB8ri")>; + +def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>; + +def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; + +def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, + STOSB, STOSL, STOSQ, STOSW)>; +def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr", + "PUSH64i8")>; + +def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { + let Latency = 2; + let NumMicroOps = 5; + let ResourceCycles = [2,2,1]; +} +def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>; + +def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk", + "KORTEST(B|D|Q|W)rr", + "KTEST(B|D|Q|W)rr")>; + +def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr", + "PEXT(32|64)rr")>; + +def SKXWriteResGroup31_16i : SchedWriteRes<[SKXPort1, SKXPort0156]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup31_16i], (instrs IMUL16rri, IMUL16rri8)>; + + +def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", + "KADD(B|D|Q|W)rr", + "KSHIFTL(B|D|Q|W)ri", + "KSHIFTR(B|D|Q|W)ri", + "KUNPCKBWrr", + "KUNPCKDQrr", + "KUNPCKWDrr", + "VALIGND(Z|Z128|Z256)rri", + "VALIGNQ(Z|Z128|Z256)rri", + "VCMPPD(Z|Z128|Z256)rri", + "VCMPPS(Z|Z128|Z256)rri", + "VCMPSDZrr", + "VCMPSSZrr", + "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined. + "VFPCLASSPD(Z|Z128|Z256)rr", + "VFPCLASSPS(Z|Z128|Z256)rr", + "VFPCLASSSDZrr", + "VFPCLASSSSZrr", + "VPBROADCASTBrr", + "VPBROADCASTWrr", + "VPCMPB(Z|Z128|Z256)rri", + "VPCMPD(Z|Z128|Z256)rri", + "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr", + "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr", + "(V?)PCMPGTQ(Y?)rr", + "VPCMPQ(Z|Z128|Z256)rri", + "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri", + "VPCMPW(Z|Z128|Z256)rri", + "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr", + "VPSADBWZrr", // TODO: 512-bit ops require ports 0/1 to be joined. + "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>; + +def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>; + +def SKXWriteResGroup35 : SchedWriteRes<[SKXPort06]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SKXWriteResGroup35], (instregex "ROL(8|16|32|64)rCL", + "ROR(8|16|32|64)rCL", + "SAR(8|16|32|64)rCL", + "SHL(8|16|32|64)rCL", + "SHR(8|16|32|64)rCL")>; + +def SKXWriteResGroup36 : SchedWriteRes<[SKXPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SKXWriteResGroup36], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr, + XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr, + XCHG16ar, XCHG32ar, XCHG64ar)>; + +def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>; + +def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>; + +def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup41], (instregex "MMX_PACKSSDWirr", + "MMX_PACKSSWBirr", + "MMX_PACKUSWBirr")>; + +def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>; + +def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>; + +def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r1", + "RCL(8|16|32|64)ri", + "RCR(8|16|32|64)r1", + "RCR(8|16|32|64)ri")>; + +def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>; + +def SKXWriteResGroup46 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SKXWriteResGroup46], (instregex "SET(A|BE)m")>; + +def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>; + +def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>; + +def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; + +def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr", + "(V?)CVTDQ2PSrr", + "VCVTPD2QQ(Z128|Z256)rr", + "VCVTPD2UQQ(Z128|Z256)rr", + "VCVTPS2DQ(Y|Z128|Z256)rr", + "(V?)CVTPS2DQrr", + "VCVTPS2UDQ(Z128|Z256)rr", + "VCVTQQ2PD(Z128|Z256)rr", + "VCVTTPD2QQ(Z128|Z256)rr", + "VCVTTPD2UQQ(Z128|Z256)rr", + "VCVTTPS2DQ(Z128|Z256)rr", + "(V?)CVTTPS2DQrr", + "VCVTTPS2UDQ(Z128|Z256)rr", + "VCVTUDQ2PS(Z128|Z256)rr", + "VCVTUQQ2PD(Z128|Z256)rr")>; + +def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr, + VCVTPD2QQZrr, + VCVTPD2UQQZrr, + VCVTPS2DQZrr, + VCVTPS2UDQZrr, + VCVTQQ2PDZrr, + VCVTTPD2QQZrr, + VCVTTPD2UQQZrr, + VCVTTPS2DQZrr, + VCVTTPS2UDQZrr, + VCVTUDQ2PSZrr, + VCVTUQQ2PDZrr)>; + +def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr", + "VEXPANDPS(Z|Z128|Z256)rr", + "VPEXPANDD(Z|Z128|Z256)rr", + "VPEXPANDQ(Z|Z128|Z256)rr", + "VPMOVDB(Z|Z128|Z256)rr", + "VPMOVDW(Z|Z128|Z256)rr", + "VPMOVQB(Z|Z128|Z256)rr", + "VPMOVQW(Z|Z128|Z256)rr", + "VPMOVSDB(Z|Z128|Z256)rr", + "VPMOVSDW(Z|Z128|Z256)rr", + "VPMOVSQB(Z|Z128|Z256)rr", + "VPMOVSQD(Z|Z128|Z256)rr", + "VPMOVSQW(Z|Z128|Z256)rr", + "VPMOVSWB(Z|Z128|Z256)rr", + "VPMOVUSDB(Z|Z128|Z256)rr", + "VPMOVUSDW(Z|Z128|Z256)rr", + "VPMOVUSQB(Z|Z128|Z256)rr", + "VPMOVUSQD(Z|Z128|Z256)rr", + "VPMOVUSWB(Z|Z128|Z256)rr", + "VPMOVWB(Z|Z128|Z256)rr")>; + +def SKXWriteResGroup52 : SchedWriteRes<[SKXPort1,SKXPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup52], (instrs IMUL64r, MUL64r, MULX64rr)>; + +def SKXWriteResGroup52_16 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SKXWriteResGroup52_16], (instrs IMUL16r, MUL16r)>; + +def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m", + "IST_F(16|32)m", + "VPMOVQD(Z|Z128|Z256)mr(b?)")>; + +def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [4]; +} +def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>; + +def SKXWriteResGroup56 : SchedWriteRes<[SKXPort015,SKXPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>; + +def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>; + +def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm16", + "MOVSX(16|32|64)rm32", + "MOVSX(16|32|64)rm8", + "MOVZX(16|32|64)rm16", + "MOVZX(16|32|64)rm8", + "(V?)MOVDDUPrm")>; // TODO: Should this be SKXWriteResGroup71? + +def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", + "VCVTDQ2PDZ128rr", + "VCVTPD2DQZ128rr", + "(V?)CVT(T?)PD2DQrr", + "VCVTPD2PSZ128rr", + "(V?)CVTPD2PSrr", + "VCVTPD2UDQZ128rr", + "VCVTPS2PDZ128rr", + "(V?)CVTPS2PDrr", + "VCVTPS2QQZ128rr", + "VCVTPS2UQQZ128rr", + "VCVTQQ2PSZ128rr", + "(V?)CVTSD2SS(Z?)rr", + "(V?)CVTSI(64)?2SDrr", + "VCVTSI2SSZrr", + "(V?)CVTSI2SSrr", + "VCVTSI(64)?2SDZrr", + "VCVTSS2SDZrr", + "(V?)CVTSS2SDrr", + "VCVTTPD2DQZ128rr", + "VCVTTPD2UDQZ128rr", + "VCVTTPS2QQZ128rr", + "VCVTTPS2UQQZ128rr", + "VCVTUDQ2PDZ128rr", + "VCVTUQQ2PSZ128rr", + "VCVTUSI2SSZrr", + "VCVTUSI(64)?2SDZrr")>; + +def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>; + +def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>; + +def SKXWriteResGroup64 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup64], (instrs IMUL32r, MUL32r, MULX32rr)>; + +def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)", + "VCVTPS2PHZ256mr(b?)", + "VCVTPS2PHZmr(b?)")>; + +def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)", + "VPMOVDW(Z|Z128|Z256)mr(b?)", + "VPMOVQB(Z|Z128|Z256)mr(b?)", + "VPMOVQW(Z|Z128|Z256)mr(b?)", + "VPMOVSDB(Z|Z128|Z256)mr(b?)", + "VPMOVSDW(Z|Z128|Z256)mr(b?)", + "VPMOVSQB(Z|Z128|Z256)mr(b?)", + "VPMOVSQD(Z|Z128|Z256)mr(b?)", + "VPMOVSQW(Z|Z128|Z256)mr(b?)", + "VPMOVSWB(Z|Z128|Z256)mr(b?)", + "VPMOVUSDB(Z|Z128|Z256)mr(b?)", + "VPMOVUSDW(Z|Z128|Z256)mr(b?)", + "VPMOVUSQB(Z|Z128|Z256)mr(b?)", + "VPMOVUSQD(Z|Z128|Z256)mr(b?)", + "VPMOVUSQW(Z|Z128|Z256)mr(b?)", + "VPMOVUSWB(Z|Z128|Z256)mr(b?)", + "VPMOVWB(Z|Z128|Z256)mr(b?)")>; + +def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>; + +def SKXWriteResGroup68 : SchedWriteRes<[SKXPort06,SKXPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [2,3]; +} +def: InstRW<[SKXWriteResGroup68], (instregex "CMPXCHG(8|16|32|64)rr")>; + +def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> { + let Latency = 5; + let NumMicroOps = 6; + let ResourceCycles = [1,1,4]; +} +def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>; + +def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup71], (instregex "VBROADCASTSSrm", + "(V?)MOVSHDUPrm", + "(V?)MOVSLDUPrm", + "VPBROADCASTDrm", + "VPBROADCASTQrm")>; + +def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup72], (instregex "MMX_CVTPI2PSirr", + "VCOMPRESSPD(Z|Z128|Z256)rr", + "VCOMPRESSPS(Z|Z128|Z256)rr", + "VPCOMPRESSD(Z|Z128|Z256)rr", + "VPCOMPRESSQ(Z|Z128|Z256)rr", + "VPERMW(Z|Z128|Z256)rr")>; + +def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup73], (instregex "MMX_PADDSBirm", + "MMX_PADDSWirm", + "MMX_PADDUSBirm", + "MMX_PADDUSWirm", + "MMX_PAVGBirm", + "MMX_PAVGWirm", + "MMX_PCMPEQBirm", + "MMX_PCMPEQDirm", + "MMX_PCMPEQWirm", + "MMX_PCMPGTBirm", + "MMX_PCMPGTDirm", + "MMX_PCMPGTWirm", + "MMX_PMAXSWirm", + "MMX_PMAXUBirm", + "MMX_PMINSWirm", + "MMX_PMINUBirm", + "MMX_PSUBSBirm", + "MMX_PSUBSWirm", + "MMX_PSUBUSBirm", + "MMX_PSUBUSWirm")>; + +def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup76], (instregex "FARJMP64", + "JMP(16|32|64)m")>; + +def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8")>; + +def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm", + "BLSI(32|64)rm", + "BLSMSK(32|64)rm", + "BLSR(32|64)rm", + "MOVBE(16|32|64)rm")>; + +def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)", + "VMOVDI2PDIZrm(b?)")>; + +def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>; +def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>; + +def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> { + let Latency = 6; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr", + "VCVTSI642SSZrr", + "VCVTUSI642SSZrr")>; + +def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>; + +def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup86], (instregex "BTC(16|32|64)mi8", + "BTR(16|32|64)mi8", + "BTS(16|32|64)mi8", + "SAR(8|16|32|64)m1", + "SAR(8|16|32|64)mi", + "SHL(8|16|32|64)m1", + "SHL(8|16|32|64)mi", + "SHR(8|16|32|64)m1", + "SHR(8|16|32|64)mi")>; + +def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm", + "PUSH(16|32|64)rmm")>; + +def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> { + let Latency = 6; + let NumMicroOps = 6; + let ResourceCycles = [1,5]; +} +def: InstRW<[SKXWriteResGroup88], (instrs STD)>; + +def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> { + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m", + "VBROADCASTF128", + "VBROADCASTI128", + "VBROADCASTSDYrm", + "VBROADCASTSSYrm", + "VMOVDDUPYrm", + "VMOVSHDUPYrm", + "VMOVSLDUPYrm", + "VPBROADCASTDYrm", + "VPBROADCASTQYrm")>; + +def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup90], (instregex "VCVTDQ2PDYrr")>; + +def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)", + "VMOVSSZrm(b?)")>; + +def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm", + "(V?)PMOV(SX|ZX)BQrm", + "(V?)PMOV(SX|ZX)BWrm", + "(V?)PMOV(SX|ZX)DQrm", + "(V?)PMOV(SX|ZX)WDrm", + "(V?)PMOV(SX|ZX)WQrm")>; + +def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr", + "VCVTPD2DQ(Y|Z256)rr", + "VCVTPD2PS(Y|Z256)rr", + "VCVTPD2UDQZ256rr", + "VCVTPS2PD(Y|Z256)rr", + "VCVTPS2QQZ256rr", + "VCVTPS2UQQZ256rr", + "VCVTQQ2PSZ256rr", + "VCVTTPD2DQ(Y|Z256)rr", + "VCVTTPD2UDQZ256rr", + "VCVTTPS2QQZ256rr", + "VCVTTPS2UQQZ256rr", + "VCVTUDQ2PDZ256rr", + "VCVTUQQ2PSZ256rr")>; + +def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr, + VCVTPD2DQZrr, + VCVTPD2PSZrr, + VCVTPD2UDQZrr, + VCVTPS2PDZrr, + VCVTPS2QQZrr, + VCVTPS2UQQZrr, + VCVTQQ2PSZrr, + VCVTTPD2DQZrr, + VCVTTPD2UDQZrr, + VCVTTPS2QQZrr, + VCVTTPS2UQQZrr, + VCVTUDQ2PDZrr, + VCVTUQQ2PSZrr)>; + +def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup95], (instregex "VBLENDMPDZ128rm(b?)", + "VBLENDMPSZ128rm(b?)", + "VBROADCASTI32X2Z128m(b?)", + "VBROADCASTSSZ128m(b?)", + "VINSERTF128rm", + "VINSERTI128rm", + "VMOVAPDZ128rm(b?)", + "VMOVAPSZ128rm(b?)", + "VMOVDDUPZ128rm(b?)", + "VMOVDQA32Z128rm(b?)", + "VMOVDQA64Z128rm(b?)", + "VMOVDQU16Z128rm(b?)", + "VMOVDQU32Z128rm(b?)", + "VMOVDQU64Z128rm(b?)", + "VMOVDQU8Z128rm(b?)", + "VMOVNTDQAZ128rm(b?)", + "VMOVSHDUPZ128rm(b?)", + "VMOVSLDUPZ128rm(b?)", + "VMOVUPDZ128rm(b?)", + "VMOVUPSZ128rm(b?)", + "VPADD(B|D|Q|W)Z128rm(b?)", + "(V?)PADD(B|D|Q|W)rm", + "VPBLENDDrmi", + "VPBLENDM(B|D|Q|W)Z128rm(b?)", + "VPBROADCASTDZ128m(b?)", + "VPBROADCASTQZ128m(b?)", + "VPSUB(B|D|Q|W)Z128rm(b?)", + "(V?)PSUB(B|D|Q|W)rm", + "VPTERNLOGDZ128rm(b?)i", + "VPTERNLOGQZ128rm(b?)i")>; + +def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup96], (instregex "MMX_PACKSSDWirm", + "MMX_PACKSSWBirm", + "MMX_PACKUSWBirm")>; + +def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr", + "VPERMI2W256rr", + "VPERMI2Wrr", + "VPERMT2W128rr", + "VPERMT2W256rr", + "VPERMT2Wrr")>; + +def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64, + SCASB, SCASL, SCASQ, SCASW)>; + +def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr", + "(V?)CVTSS2SI64(Z?)rr", + "(V?)CVTTSS2SI64(Z?)rr", + "VCVTTSS2USI64Zrr")>; + +def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>; + +def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; + +def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>; + +def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", + "VCOMPRESSPS(Z|Z128|Z256)mr(b?)", + "VPCOMPRESSD(Z|Z128|Z256)mr(b?)", + "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>; + +def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m1", + "ROL(8|16|32|64)mi", + "ROR(8|16|32|64)m1", + "ROR(8|16|32|64)mi")>; + +def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>; + +def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m", + "FARCALL64")>; + +def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 7; + let ResourceCycles = [1,2,2,2]; +} +def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr, + VPSCATTERQQZ128mr, + VSCATTERDPDZ128mr, + VSCATTERQPDZ128mr)>; + +def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 7; + let ResourceCycles = [1,3,1,2]; +} +def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>; + +def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 11; + let ResourceCycles = [1,4,4,2]; +} +def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr, + VPSCATTERQQZ256mr, + VSCATTERDPDZ256mr, + VSCATTERQPDZ256mr)>; + +def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 19; + let ResourceCycles = [1,8,8,2]; +} +def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr, + VPSCATTERQQZmr, + VSCATTERDPDZmr, + VSCATTERQPDZmr)>; + +def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 36; + let ResourceCycles = [1,16,1,16,2]; +} +def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>; + +def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm", + "PEXT(32|64)rm")>; + +def SKXWriteResGroup118_16_1 : SchedWriteRes<[SKXPort1, SKXPort0156, SKXPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup118_16_1], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>; + +def SKXWriteResGroup118_16_2 : SchedWriteRes<[SKXPort1, SKXPort06, SKXPort0156, SKXPort23]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[SKXWriteResGroup118_16_2], (instrs IMUL16m, MUL16m)>; + +def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m", + "VFPCLASSSDZrm(b?)", + "VPBROADCASTBYrm", + "VPBROADCASTB(Z|Z256)m(b?)", + "VPBROADCASTWYrm", + "VPBROADCASTW(Z|Z256)m(b?)", + "VPMOVSXBDYrm", + "VPMOVSXBQYrm", + "VPMOVSXWQYrm")>; + +def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup121], (instregex "VBLENDMPD(Z|Z256)rm(b?)", + "VBLENDMPS(Z|Z256)rm(b?)", + "VBROADCASTF32X2Z256m(b?)", + "VBROADCASTF32X2Zm(b?)", + "VBROADCASTF32X4Z256rm(b?)", + "VBROADCASTF32X4rm(b?)", + "VBROADCASTF32X8rm(b?)", + "VBROADCASTF64X2Z128rm(b?)", + "VBROADCASTF64X2rm(b?)", + "VBROADCASTF64X4rm(b?)", + "VBROADCASTI32X2Z256m(b?)", + "VBROADCASTI32X2Zm(b?)", + "VBROADCASTI32X4Z256rm(b?)", + "VBROADCASTI32X4rm(b?)", + "VBROADCASTI32X8rm(b?)", + "VBROADCASTI64X2Z128rm(b?)", + "VBROADCASTI64X2rm(b?)", + "VBROADCASTI64X4rm(b?)", + "VBROADCASTSD(Z|Z256)m(b?)", + "VBROADCASTSS(Z|Z256)m(b?)", + "VINSERTF32x4(Z|Z256)rm(b?)", + "VINSERTF32x8Zrm(b?)", + "VINSERTF64x2(Z|Z256)rm(b?)", + "VINSERTF64x4Zrm(b?)", + "VINSERTI32x4(Z|Z256)rm(b?)", + "VINSERTI32x8Zrm(b?)", + "VINSERTI64x2(Z|Z256)rm(b?)", + "VINSERTI64x4Zrm(b?)", + "VMOVAPD(Z|Z256)rm(b?)", + "VMOVAPS(Z|Z256)rm(b?)", + "VMOVDDUP(Z|Z256)rm(b?)", + "VMOVDQA32(Z|Z256)rm(b?)", + "VMOVDQA64(Z|Z256)rm(b?)", + "VMOVDQU16(Z|Z256)rm(b?)", + "VMOVDQU32(Z|Z256)rm(b?)", + "VMOVDQU64(Z|Z256)rm(b?)", + "VMOVDQU8(Z|Z256)rm(b?)", + "VMOVNTDQAZ256rm(b?)", + "VMOVSHDUP(Z|Z256)rm(b?)", + "VMOVSLDUP(Z|Z256)rm(b?)", + "VMOVUPD(Z|Z256)rm(b?)", + "VMOVUPS(Z|Z256)rm(b?)", + "VPADD(B|D|Q|W)Yrm", + "VPADD(B|D|Q|W)(Z|Z256)rm(b?)", + "VPBLENDDYrmi", + "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)", + "VPBROADCASTD(Z|Z256)m(b?)", + "VPBROADCASTQ(Z|Z256)m(b?)", + "VPSUB(B|D|Q|W)Yrm", + "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)", + "VPTERNLOGD(Z|Z256)rm(b?)i", + "VPTERNLOGQ(Z|Z256)rm(b?)i")>; + +def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { + let Latency = 8; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>; + +def SKXWriteResGroup126 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,3]; +} +def: InstRW<[SKXWriteResGroup126], (instregex "ROR(8|16|32|64)mCL")>; + +def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m1", + "RCL(8|16|32|64)mi", + "RCR(8|16|32|64)m1", + "RCR(8|16|32|64)mi")>; + +def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,3]; +} +def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; + +def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,2,1]; +} +def: SchedAlias; +def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG(8|16|32|64)rm")>; + +def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { + let Latency = 8; + let NumMicroOps = 8; + let ResourceCycles = [1,2,1,2,2]; +} +def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr, + VPSCATTERQDZ256mr, + VSCATTERQPSZ128mr, + VSCATTERQPSZ256mr)>; + +def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { + let Latency = 8; + let NumMicroOps = 12; + let ResourceCycles = [1,4,1,4,2]; +} +def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr, + VSCATTERDPSZ128mr)>; + +def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { + let Latency = 8; + let NumMicroOps = 20; + let ResourceCycles = [1,8,1,8,2]; +} +def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr, + VSCATTERDPSZ256mr)>; + +def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { + let Latency = 8; + let NumMicroOps = 36; + let ResourceCycles = [1,16,1,16,2]; +} +def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>; + +def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup135], (instregex "MMX_CVTPI2PSirm")>; + +def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup136], (instregex "VALIGNDZ128rm(b?)i", + "VALIGNQZ128rm(b?)i", + "VCMPPDZ128rm(b?)i", + "VCMPPSZ128rm(b?)i", + "VCMPSDZrm", + "VCMPSSZrm", + "VFPCLASSSSZrm(b?)", + "VPCMPBZ128rmi(b?)", + "VPCMPDZ128rmi(b?)", + "VPCMPEQ(B|D|Q|W)Z128rm(b?)", + "VPCMPGT(B|D|Q|W)Z128rm(b?)", + "(V?)PCMPGTQrm", + "VPCMPQZ128rmi(b?)", + "VPCMPU(B|D|Q|W)Z128rmi(b?)", + "VPCMPWZ128rmi(b?)", + "VPERMI2D128rm(b?)", + "VPERMI2PD128rm(b?)", + "VPERMI2PS128rm(b?)", + "VPERMI2Q128rm(b?)", + "VPERMT2D128rm(b?)", + "VPERMT2PD128rm(b?)", + "VPERMT2PS128rm(b?)", + "VPERMT2Q128rm(b?)", + "VPMAXSQZ128rm(b?)", + "VPMAXUQZ128rm(b?)", + "VPMINSQZ128rm(b?)", + "VPMINUQZ128rm(b?)", + "VPMOVSXBDZ128rm(b?)", + "VPMOVSXBQZ128rm(b?)", + "VPMOVSXBWYrm", + "VPMOVSXBWZ128rm(b?)", + "VPMOVSXDQYrm", + "VPMOVSXDQZ128rm(b?)", + "VPMOVSXWDYrm", + "VPMOVSXWDZ128rm(b?)", + "VPMOVSXWQZ128rm(b?)", + "VPMOVZXBDZ128rm(b?)", + "VPMOVZXBQZ128rm(b?)", + "VPMOVZXBWZ128rm(b?)", + "VPMOVZXDQZ128rm(b?)", + "VPMOVZXWDYrm", + "VPMOVZXWDZ128rm(b?)", + "VPMOVZXWQZ128rm(b?)", + "VPTESTMBZ128rm(b?)", + "VPTESTMDZ128rm(b?)", + "VPTESTMQZ128rm(b?)", + "VPTESTMWZ128rm(b?)", + "VPTESTNMBZ128rm(b?)", + "VPTESTNMDZ128rm(b?)", + "VPTESTNMQZ128rm(b?)", + "VPTESTNMWZ128rm(b?)")>; + +def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm", + "(V?)CVTPS2PDrm")>; + +def SKXWriteResGroup142 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup142], (instrs IMUL64m, MUL64m, MULX64rm)>; + +def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm", + "(V?)PHSUBSWrm")>; + +def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm", + "LSL(16|32|64)rm")>; + +def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m", + "ILD_F(16|32|64)m", + "VALIGND(Z|Z256)rm(b?)i", + "VALIGNQ(Z|Z256)rm(b?)i", + "VCMPPD(Z|Z256)rm(b?)i", + "VCMPPS(Z|Z256)rm(b?)i", + "VPCMPB(Z|Z256)rmi(b?)", + "VPCMPD(Z|Z256)rmi(b?)", + "VPCMPEQB(Z|Z256)rm(b?)", + "VPCMPEQD(Z|Z256)rm(b?)", + "VPCMPEQQ(Z|Z256)rm(b?)", + "VPCMPEQW(Z|Z256)rm(b?)", + "VPCMPGTB(Z|Z256)rm(b?)", + "VPCMPGTD(Z|Z256)rm(b?)", + "VPCMPGTQYrm", + "VPCMPGTQ(Z|Z256)rm(b?)", + "VPCMPGTW(Z|Z256)rm(b?)", + "VPCMPQ(Z|Z256)rmi(b?)", + "VPCMPU(B|D|Q|W)Z256rmi(b?)", + "VPCMPU(B|D|Q|W)Zrmi(b?)", + "VPCMPW(Z|Z256)rmi(b?)", + "VPMAXSQ(Z|Z256)rm(b?)", + "VPMAXUQ(Z|Z256)rm(b?)", + "VPMINSQ(Z|Z256)rm(b?)", + "VPMINUQ(Z|Z256)rm(b?)", + "VPTESTM(B|D|Q|W)Z256rm(b?)", + "VPTESTM(B|D|Q|W)Zrm(b?)", + "VPTESTNM(B|D|Q|W)Z256rm(b?)", + "VPTESTNM(B|D|Q|W)Zrm(b?)")>; + +def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)", + "VCVTDQ2PSZ128rm(b?)", + "(V?)CVTDQ2PSrm", + "VCVTPD2QQZ128rm(b?)", + "VCVTPD2UQQZ128rm(b?)", + "VCVTPH2PSZ128rm(b?)", + "VCVTPS2DQZ128rm(b?)", + "(V?)CVTPS2DQrm", + "VCVTPS2PDZ128rm(b?)", + "VCVTPS2QQZ128rm(b?)", + "VCVTPS2UDQZ128rm(b?)", + "VCVTPS2UQQZ128rm(b?)", + "VCVTQQ2PDZ128rm(b?)", + "VCVTQQ2PSZ128rm(b?)", + "VCVTSS2SDZrm", + "(V?)CVTSS2SDrm", + "VCVTTPD2QQZ128rm(b?)", + "VCVTTPD2UQQZ128rm(b?)", + "VCVTTPS2DQZ128rm(b?)", + "(V?)CVTTPS2DQrm", + "VCVTTPS2QQZ128rm(b?)", + "VCVTTPS2UDQZ128rm(b?)", + "VCVTTPS2UQQZ128rm(b?)", + "VCVTUDQ2PDZ128rm(b?)", + "VCVTUDQ2PSZ128rm(b?)", + "VCVTUQQ2PDZ128rm(b?)", + "VCVTUQQ2PSZ128rm(b?)")>; + +def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)", + "VEXPANDPSZ128rm(b?)", + "VPEXPANDDZ128rm(b?)", + "VPEXPANDQZ128rm(b?)")>; + +def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>; + +def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> { + let Latency = 10; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKXWriteResGroup154], (instregex "VPHADDSWYrm", + "VPHSUBSWYrm")>; + +def SKXWriteResGroup156 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort06,SKXPort0156]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup156], (instrs IMUL32m, MUL32m, MULX32rm)>; + +def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 10; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,3]; +} +def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>; + +def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { + let Latency = 11; + let NumMicroOps = 1; + let ResourceCycles = [1,3]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>; + +def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2PD(Z|Z256)rm(b?)", + "VCVTDQ2PSYrm", + "VCVTDQ2PS(Z|Z256)rm(b?)", + "VCVTPH2PS(Z|Z256)rm(b?)", + "VCVTPS2PDYrm", + "VCVTPS2PD(Z|Z256)rm(b?)", + "VCVTQQ2PD(Z|Z256)rm(b?)", + "VCVTQQ2PSZ256rm(b?)", + "VCVT(T?)PD2QQ(Z|Z256)rm(b?)", + "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)", + "VCVT(T?)PS2DQYrm", + "VCVT(T?)PS2DQ(Z|Z256)rm(b?)", + "VCVT(T?)PS2QQZ256rm(b?)", + "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)", + "VCVT(T?)PS2UQQZ256rm(b?)", + "VCVTUDQ2PD(Z|Z256)rm(b?)", + "VCVTUDQ2PS(Z|Z256)rm(b?)", + "VCVTUQQ2PD(Z|Z256)rm(b?)", + "VCVTUQQ2PSZ256rm(b?)")>; + +def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m", + "VEXPANDPD(Z|Z256)rm(b?)", + "VEXPANDPS(Z|Z256)rm(b?)", + "VPEXPANDD(Z|Z256)rm(b?)", + "VPEXPANDQ(Z|Z256)rm(b?)")>; + +def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>; + +def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>; + +def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup166], (instregex "CVTPD2PSrm", + "CVT(T?)PD2DQrm", + "MMX_CVT(T?)PD2PIirm")>; + +def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 11; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>; + +def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { + let Latency = 11; + let NumMicroOps = 7; + let ResourceCycles = [2,3,2]; +} +def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL", + "RCR(16|32|64)rCL")>; + +def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 11; + let NumMicroOps = 9; + let ResourceCycles = [1,5,1,2]; +} +def: InstRW<[SKXWriteResGroup170], (instregex "RCL8rCL")>; + +def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> { + let Latency = 11; + let NumMicroOps = 11; + let ResourceCycles = [2,9]; +} +def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>; + +def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>; + +def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>; + +def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>; + +def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)", + "VCVT(T?)SS2USI64Zrm(b?)")>; + +def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)", + "VCVT(T?)PS2UQQZrm(b?)")>; + +def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 12; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>; + +def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m", + "VPERMWZ256rm(b?)", + "VPERMWZrm(b?)")>; + +def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup181], (instregex "VCVTDQ2PDYrm")>; + +def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 13; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)", + "VPERMT2W128rm(b?)")>; + +def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1,3]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1,5]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>; + +def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)", + "VCVTPD2PSZrm(b?)", + "VCVTPD2UDQZrm(b?)", + "VCVTQQ2PSZrm(b?)", + "VCVTTPD2DQZrm(b?)", + "VCVTTPD2UDQZrm(b?)", + "VCVTUQQ2PSZrm(b?)")>; + +def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 14; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)", + "VPERMI2Wrm(b?)", + "VPERMT2W256rm(b?)", + "VPERMT2Wrm(b?)")>; + +def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 14; + let NumMicroOps = 10; + let ResourceCycles = [2,4,1,3]; +} +def: InstRW<[SKXWriteResGroup190], (instregex "RCR8rCL")>; + +def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> { + let Latency = 15; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; + +def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { + let Latency = 15; + let NumMicroOps = 8; + let ResourceCycles = [1,2,2,1,2]; +} +def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>; + +def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 15; + let NumMicroOps = 10; + let ResourceCycles = [1,1,1,5,1,1]; +} +def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>; + +def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 16; + let NumMicroOps = 14; + let ResourceCycles = [1,1,1,4,2,5]; +} +def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>; + +def SKXWriteResGroup200 : SchedWriteRes<[SKXPort0156]> { + let Latency = 16; + let NumMicroOps = 16; + let ResourceCycles = [16]; +} +def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>; + +def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { + let Latency = 17; + let NumMicroOps = 2; + let ResourceCycles = [1,1,5]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> { + let Latency = 17; + let NumMicroOps = 15; + let ResourceCycles = [2,1,2,4,2,4]; +} +def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>; + +def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 18; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>; + +def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,5]; +} +def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>; + +def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 18; + let NumMicroOps = 11; + let ResourceCycles = [2,1,1,4,1,2]; +} +def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>; + +def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { + let Latency = 19; + let NumMicroOps = 2; + let ResourceCycles = [1,1,4]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 19; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)", + "VPMULLQZrm(b?)")>; + +def SKXWriteResGroup214 : SchedWriteRes<[]> { + let Latency = 20; + let NumMicroOps = 0; +} +def: InstRW<[SKXWriteResGroup214], (instrs VGATHERDPSZ128rm, + VGATHERQPSZrm, + VPGATHERDDZ128rm)>; + +def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> { + let Latency = 20; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; + +def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { + let Latency = 20; + let NumMicroOps = 2; + let ResourceCycles = [1,1,4]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup218 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { + let Latency = 20; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup218], (instrs VGATHERQPSZ128rm, + VGATHERQPSZ256rm, + VPGATHERQDZ128rm, + VPGATHERQDZ256rm)>; + +def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 20; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,1,2]; +} +def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>; + +def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> { + let Latency = 20; + let NumMicroOps = 10; + let ResourceCycles = [1,2,7]; +} +def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>; + +def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { + let Latency = 21; + let NumMicroOps = 2; + let ResourceCycles = [1,1,8]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> { + let Latency = 22; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>; + +def SKXWriteResGroup224 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { + let Latency = 22; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup224], (instrs VGATHERDPDZ128rm, + VGATHERQPDZ128rm, + VPGATHERDQZ128rm, + VPGATHERQQZ128rm)>; + +def SKXWriteResGroup224_2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> { + let Latency = 22; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup224_2], (instrs VGATHERDPSrm, + VGATHERDPDrm, + VGATHERQPDrm, + VGATHERQPSrm, + VPGATHERDDrm, + VPGATHERDQrm, + VPGATHERQDrm, + VPGATHERQQrm, + VPGATHERDDrm, + VPGATHERQDrm, + VPGATHERDQrm, + VPGATHERQQrm, + VGATHERDPSrm, + VGATHERQPSrm, + VGATHERDPDrm, + VGATHERQPDrm)>; + +def SKXWriteResGroup224_3 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> { + let Latency = 25; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup224_3], (instrs VGATHERDPSYrm, + VGATHERQPDYrm, + VGATHERQPSYrm, + VPGATHERDDYrm, + VPGATHERDQYrm, + VPGATHERQDYrm, + VPGATHERQQYrm, + VPGATHERDDYrm, + VPGATHERQDYrm, + VPGATHERDQYrm, + VPGATHERQQYrm, + VGATHERDPSYrm, + VGATHERQPSYrm, + VGATHERDPDYrm)>; + +def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { + let Latency = 22; + let NumMicroOps = 14; + let ResourceCycles = [5,5,4]; +} +def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr", + "VPCONFLICTQZ256rr")>; + +def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 23; + let NumMicroOps = 19; + let ResourceCycles = [2,1,4,1,1,4,6]; +} +def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>; + +def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { + let Latency = 25; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>; + +def SKXWriteResGroup234 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { + let Latency = 25; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup234], (instrs VGATHERDPDZ256rm, + VGATHERQPDZ256rm, + VPGATHERDQZ256rm, + VPGATHERQDZrm, + VPGATHERQQZ256rm)>; + +def SKXWriteResGroup238 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { + let Latency = 26; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup238], (instrs VGATHERDPDZrm, + VGATHERQPDZrm, + VPGATHERDQZrm, + VPGATHERQQZrm)>; + +def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> { + let Latency = 27; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>; + +def SKXWriteResGroup240 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { + let Latency = 27; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup240], (instrs VGATHERDPSZ256rm, + VPGATHERDDZ256rm)>; + +def SKXWriteResGroup241 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort0156]> { + let Latency = 28; + let NumMicroOps = 8; + let ResourceCycles = [2,4,1,1]; +} +def: InstRW<[SKXWriteResGroup241], (instregex "IDIV(8|16|32|64)m")>; + +def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { + let Latency = 29; + let NumMicroOps = 15; + let ResourceCycles = [5,5,1,4]; +} +def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>; + +def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { + let Latency = 30; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>; + +def SKXWriteResGroup245 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { + let Latency = 30; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup245], (instrs VGATHERDPSZrm, + VPGATHERDDZrm)>; + +def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,3,4,10]; +} +def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri", + "IN(8|16|32)rr")>; + +def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,2,1,4,10]; +} +def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir", + "OUT(8|16|32)rr")>; + +def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { + let Latency = 37; + let NumMicroOps = 21; + let ResourceCycles = [9,7,5]; +} +def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr", + "VPCONFLICTQZrr")>; + +def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> { + let Latency = 37; + let NumMicroOps = 31; + let ResourceCycles = [1,8,1,21]; +} +def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>; + +def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> { + let Latency = 40; + let NumMicroOps = 18; + let ResourceCycles = [1,1,2,3,1,1,1,8]; +} +def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>; + +def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { + let Latency = 41; + let NumMicroOps = 39; + let ResourceCycles = [1,10,1,1,26]; +} +def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>; + +def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> { + let Latency = 42; + let NumMicroOps = 22; + let ResourceCycles = [2,20]; +} +def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>; + +def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { + let Latency = 42; + let NumMicroOps = 40; + let ResourceCycles = [1,11,1,1,26]; +} +def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>; +def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; + +def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { + let Latency = 44; + let NumMicroOps = 22; + let ResourceCycles = [9,7,1,5]; +} +def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)", + "VPCONFLICTQZrm(b?)")>; + +def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> { + let Latency = 62; + let NumMicroOps = 64; + let ResourceCycles = [2,8,5,10,39]; +} +def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>; + +def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 63; + let NumMicroOps = 88; + let ResourceCycles = [4,4,31,1,2,1,45]; +} +def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>; + +def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 63; + let NumMicroOps = 90; + let ResourceCycles = [4,2,33,1,2,1,47]; +} +def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>; + +def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { + let Latency = 67; + let NumMicroOps = 35; + let ResourceCycles = [17,11,7]; +} +def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>; + +def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { + let Latency = 74; + let NumMicroOps = 36; + let ResourceCycles = [17,11,1,7]; +} +def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>; + +def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> { + let Latency = 75; + let NumMicroOps = 15; + let ResourceCycles = [6,3,6]; +} +def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>; + +def SKXWriteResGroup264 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> { + let Latency = 76; + let NumMicroOps = 32; + let ResourceCycles = [7,2,8,3,1,11]; +} +def: InstRW<[SKXWriteResGroup264], (instregex "DIV(16|32|64)r")>; + +def SKXWriteResGroup265 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> { + let Latency = 102; + let NumMicroOps = 66; + let ResourceCycles = [4,2,4,8,14,34]; +} +def: InstRW<[SKXWriteResGroup265], (instregex "IDIV(16|32|64)r")>; + +def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 106; + let NumMicroOps = 100; + let ResourceCycles = [9,1,11,16,1,11,21,30]; +} +def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>; + +def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> { + let Latency = 140; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>; + +def: InstRW<[WriteZero], (instrs CLC)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86Schedule.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86Schedule.td new file mode 100644 index 0000000..6215d58 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86Schedule.td @@ -0,0 +1,661 @@ +//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// InstrSchedModel annotations for out-of-order CPUs. + +// Instructions with folded loads need to read the memory operand immediately, +// but other register operands don't have to be read until the load is ready. +// These operands are marked with ReadAfterLd. +def ReadAfterLd : SchedRead; + +// Instructions with both a load and a store folded are modeled as a folded +// load + WriteRMW. +def WriteRMW : SchedWrite; + +// Helper to set SchedWrite ExePorts/Latency/ResourceCycles/NumMicroOps. +multiclass X86WriteRes ExePorts, + int Lat, list Res, int UOps> { + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } +} + +// Most instructions can fold loads, so almost every SchedWrite comes in two +// variants: With and without a folded load. +// An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite +// with a folded load. +class X86FoldableSchedWrite : SchedWrite { + // The SchedWrite to use when a load is folded into the instruction. + SchedWrite Folded; +} + +// Multiclass that produces a linked pair of SchedWrites. +multiclass X86SchedWritePair { + // Register-Memory operation. + def Ld : SchedWrite; + // Register-Register operation. + def NAME : X86FoldableSchedWrite { + let Folded = !cast(NAME#"Ld"); + } +} + +// Helpers to mark SchedWrites as unsupported. +multiclass X86WriteResUnsupported { + let Unsupported = 1 in { + def : WriteRes; + } +} +multiclass X86WriteResPairUnsupported { + let Unsupported = 1 in { + def : WriteRes; + def : WriteRes; + } +} + +// Multiclass that wraps X86FoldableSchedWrite for each vector width. +class X86SchedWriteWidths { + X86FoldableSchedWrite Scl = sScl; // Scalar float/double operations. + X86FoldableSchedWrite MMX = sScl; // MMX operations. + X86FoldableSchedWrite XMM = s128; // XMM operations. + X86FoldableSchedWrite YMM = s256; // YMM operations. + X86FoldableSchedWrite ZMM = s512; // ZMM operations. +} + +// Multiclass that wraps X86SchedWriteWidths for each fp vector type. +class X86SchedWriteSizes { + X86SchedWriteWidths PS = sPS; + X86SchedWriteWidths PD = sPD; +} + +// Multiclass that wraps move/load/store triple for a vector width. +class X86SchedWriteMoveLS { + SchedWrite RR = MoveRR; + SchedWrite RM = LoadRM; + SchedWrite MR = StoreMR; +} + +// Multiclass that wraps X86SchedWriteMoveLS for each vector width. +class X86SchedWriteMoveLSWidths { + X86SchedWriteMoveLS Scl = sScl; // Scalar float/double operations. + X86SchedWriteMoveLS MMX = sScl; // MMX operations. + X86SchedWriteMoveLS XMM = s128; // XMM operations. + X86SchedWriteMoveLS YMM = s256; // YMM operations. + X86SchedWriteMoveLS ZMM = s512; // ZMM operations. +} + +// Loads, stores, and moves, not folded with other operations. +def WriteLoad : SchedWrite; +def WriteStore : SchedWrite; +def WriteStoreNT : SchedWrite; +def WriteMove : SchedWrite; + +// Arithmetic. +defm WriteALU : X86SchedWritePair; // Simple integer ALU op. +defm WriteADC : X86SchedWritePair; // Integer ALU + flags op. +def WriteALURMW : WriteSequence<[WriteALULd, WriteStore]>; +def WriteADCRMW : WriteSequence<[WriteADCLd, WriteStore]>; +defm WriteIMul : X86SchedWritePair; // Integer multiplication. +defm WriteIMul64 : X86SchedWritePair; // Integer 64-bit multiplication. +def WriteIMulH : SchedWrite; // Integer multiplication, high part. +def WriteLEA : SchedWrite; // LEA instructions can't fold loads. + +def WriteBSWAP32 : SchedWrite; // Byte Order (Endianness) 32-bit Swap. +def WriteBSWAP64 : SchedWrite; // Byte Order (Endianness) 64-bit Swap. + +// Integer division. +defm WriteDiv8 : X86SchedWritePair; +defm WriteDiv16 : X86SchedWritePair; +defm WriteDiv32 : X86SchedWritePair; +defm WriteDiv64 : X86SchedWritePair; +defm WriteIDiv8 : X86SchedWritePair; +defm WriteIDiv16 : X86SchedWritePair; +defm WriteIDiv32 : X86SchedWritePair; +defm WriteIDiv64 : X86SchedWritePair; + +defm WriteBSF : X86SchedWritePair; // Bit scan forward. +defm WriteBSR : X86SchedWritePair; // Bit scan reverse. +defm WritePOPCNT : X86SchedWritePair; // Bit population count. +defm WriteLZCNT : X86SchedWritePair; // Leading zero count. +defm WriteTZCNT : X86SchedWritePair; // Trailing zero count. +defm WriteCMOV : X86SchedWritePair; // Conditional move. +defm WriteCMOV2 : X86SchedWritePair; // Conditional (CF + ZF flag) move. +def WriteFCMOV : SchedWrite; // X87 conditional move. +def WriteSETCC : SchedWrite; // Set register based on condition code. +def WriteSETCCStore : SchedWrite; +def WriteLAHFSAHF : SchedWrite; // Load/Store flags in AH. +def WriteBitTest : SchedWrite; // Bit Test - TODO add memory folding support + +// Integer shifts and rotates. +defm WriteShift : X86SchedWritePair; +// Double shift instructions. +def WriteSHDrri : SchedWrite; +def WriteSHDrrcl : SchedWrite; +def WriteSHDmri : SchedWrite; +def WriteSHDmrcl : SchedWrite; + +// BMI1 BEXTR, BMI2 BZHI +defm WriteBEXTR : X86SchedWritePair; +defm WriteBZHI : X86SchedWritePair; + +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +def WriteZero : SchedWrite; + +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +defm WriteJump : X86SchedWritePair; + +// Floating point. This covers both scalar and vector operations. +def WriteFLD0 : SchedWrite; +def WriteFLD1 : SchedWrite; +def WriteFLDC : SchedWrite; +def WriteFLoad : SchedWrite; +def WriteFLoadX : SchedWrite; +def WriteFLoadY : SchedWrite; +def WriteFMaskedLoad : SchedWrite; +def WriteFMaskedLoadY : SchedWrite; +def WriteFStore : SchedWrite; +def WriteFStoreX : SchedWrite; +def WriteFStoreY : SchedWrite; +def WriteFStoreNT : SchedWrite; +def WriteFStoreNTX : SchedWrite; +def WriteFStoreNTY : SchedWrite; +def WriteFMaskedStore : SchedWrite; +def WriteFMaskedStoreY : SchedWrite; +def WriteFMove : SchedWrite; +def WriteFMoveX : SchedWrite; +def WriteFMoveY : SchedWrite; + +defm WriteFAdd : X86SchedWritePair; // Floating point add/sub. +defm WriteFAddX : X86SchedWritePair; // Floating point add/sub (XMM). +defm WriteFAddY : X86SchedWritePair; // Floating point add/sub (YMM). +defm WriteFAddZ : X86SchedWritePair; // Floating point add/sub (ZMM). +defm WriteFAdd64 : X86SchedWritePair; // Floating point double add/sub. +defm WriteFAdd64X : X86SchedWritePair; // Floating point double add/sub (XMM). +defm WriteFAdd64Y : X86SchedWritePair; // Floating point double add/sub (YMM). +defm WriteFAdd64Z : X86SchedWritePair; // Floating point double add/sub (ZMM). +defm WriteFCmp : X86SchedWritePair; // Floating point compare. +defm WriteFCmpX : X86SchedWritePair; // Floating point compare (XMM). +defm WriteFCmpY : X86SchedWritePair; // Floating point compare (YMM). +defm WriteFCmpZ : X86SchedWritePair; // Floating point compare (ZMM). +defm WriteFCmp64 : X86SchedWritePair; // Floating point double compare. +defm WriteFCmp64X : X86SchedWritePair; // Floating point double compare (XMM). +defm WriteFCmp64Y : X86SchedWritePair; // Floating point double compare (YMM). +defm WriteFCmp64Z : X86SchedWritePair; // Floating point double compare (ZMM). +defm WriteFCom : X86SchedWritePair; // Floating point compare to flags. +defm WriteFMul : X86SchedWritePair; // Floating point multiplication. +defm WriteFMulX : X86SchedWritePair; // Floating point multiplication (XMM). +defm WriteFMulY : X86SchedWritePair; // Floating point multiplication (YMM). +defm WriteFMulZ : X86SchedWritePair; // Floating point multiplication (YMM). +defm WriteFMul64 : X86SchedWritePair; // Floating point double multiplication. +defm WriteFMul64X : X86SchedWritePair; // Floating point double multiplication (XMM). +defm WriteFMul64Y : X86SchedWritePair; // Floating point double multiplication (YMM). +defm WriteFMul64Z : X86SchedWritePair; // Floating point double multiplication (ZMM). +defm WriteFDiv : X86SchedWritePair; // Floating point division. +defm WriteFDivX : X86SchedWritePair; // Floating point division (XMM). +defm WriteFDivY : X86SchedWritePair; // Floating point division (YMM). +defm WriteFDivZ : X86SchedWritePair; // Floating point division (ZMM). +defm WriteFDiv64 : X86SchedWritePair; // Floating point double division. +defm WriteFDiv64X : X86SchedWritePair; // Floating point double division (XMM). +defm WriteFDiv64Y : X86SchedWritePair; // Floating point double division (YMM). +defm WriteFDiv64Z : X86SchedWritePair; // Floating point double division (ZMM). +defm WriteFSqrt : X86SchedWritePair; // Floating point square root. +defm WriteFSqrtX : X86SchedWritePair; // Floating point square root (XMM). +defm WriteFSqrtY : X86SchedWritePair; // Floating point square root (YMM). +defm WriteFSqrtZ : X86SchedWritePair; // Floating point square root (ZMM). +defm WriteFSqrt64 : X86SchedWritePair; // Floating point double square root. +defm WriteFSqrt64X : X86SchedWritePair; // Floating point double square root (XMM). +defm WriteFSqrt64Y : X86SchedWritePair; // Floating point double square root (YMM). +defm WriteFSqrt64Z : X86SchedWritePair; // Floating point double square root (ZMM). +defm WriteFSqrt80 : X86SchedWritePair; // Floating point long double square root. +defm WriteFRcp : X86SchedWritePair; // Floating point reciprocal estimate. +defm WriteFRcpX : X86SchedWritePair; // Floating point reciprocal estimate (XMM). +defm WriteFRcpY : X86SchedWritePair; // Floating point reciprocal estimate (YMM). +defm WriteFRcpZ : X86SchedWritePair; // Floating point reciprocal estimate (ZMM). +defm WriteFRsqrt : X86SchedWritePair; // Floating point reciprocal square root estimate. +defm WriteFRsqrtX: X86SchedWritePair; // Floating point reciprocal square root estimate (XMM). +defm WriteFRsqrtY: X86SchedWritePair; // Floating point reciprocal square root estimate (YMM). +defm WriteFRsqrtZ: X86SchedWritePair; // Floating point reciprocal square root estimate (ZMM). +defm WriteFMA : X86SchedWritePair; // Fused Multiply Add. +defm WriteFMAX : X86SchedWritePair; // Fused Multiply Add (XMM). +defm WriteFMAY : X86SchedWritePair; // Fused Multiply Add (YMM). +defm WriteFMAZ : X86SchedWritePair; // Fused Multiply Add (ZMM). +defm WriteDPPD : X86SchedWritePair; // Floating point double dot product. +defm WriteDPPS : X86SchedWritePair; // Floating point single dot product. +defm WriteDPPSY : X86SchedWritePair; // Floating point single dot product (YMM). +defm WriteDPPSZ : X86SchedWritePair; // Floating point single dot product (ZMM). +defm WriteFSign : X86SchedWritePair; // Floating point fabs/fchs. +defm WriteFRnd : X86SchedWritePair; // Floating point rounding. +defm WriteFRndY : X86SchedWritePair; // Floating point rounding (YMM). +defm WriteFRndZ : X86SchedWritePair; // Floating point rounding (ZMM). +defm WriteFLogic : X86SchedWritePair; // Floating point and/or/xor logicals. +defm WriteFLogicY : X86SchedWritePair; // Floating point and/or/xor logicals (YMM). +defm WriteFLogicZ : X86SchedWritePair; // Floating point and/or/xor logicals (ZMM). +defm WriteFTest : X86SchedWritePair; // Floating point TEST instructions. +defm WriteFTestY : X86SchedWritePair; // Floating point TEST instructions (YMM). +defm WriteFTestZ : X86SchedWritePair; // Floating point TEST instructions (ZMM). +defm WriteFShuffle : X86SchedWritePair; // Floating point vector shuffles. +defm WriteFShuffleY : X86SchedWritePair; // Floating point vector shuffles (YMM). +defm WriteFShuffleZ : X86SchedWritePair; // Floating point vector shuffles (ZMM). +defm WriteFVarShuffle : X86SchedWritePair; // Floating point vector variable shuffles. +defm WriteFVarShuffleY : X86SchedWritePair; // Floating point vector variable shuffles (YMM). +defm WriteFVarShuffleZ : X86SchedWritePair; // Floating point vector variable shuffles (ZMM). +defm WriteFBlend : X86SchedWritePair; // Floating point vector blends. +defm WriteFBlendY : X86SchedWritePair; // Floating point vector blends (YMM). +defm WriteFBlendZ : X86SchedWritePair; // Floating point vector blends (ZMM). +defm WriteFVarBlend : X86SchedWritePair; // Fp vector variable blends. +defm WriteFVarBlendY : X86SchedWritePair; // Fp vector variable blends (YMM). +defm WriteFVarBlendZ : X86SchedWritePair; // Fp vector variable blends (YMZMM). + +// FMA Scheduling helper class. +class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } + +// Horizontal Add/Sub (float and integer) +defm WriteFHAdd : X86SchedWritePair; +defm WriteFHAddY : X86SchedWritePair; +defm WriteFHAddZ : X86SchedWritePair; +defm WritePHAdd : X86SchedWritePair; +defm WritePHAddX : X86SchedWritePair; +defm WritePHAddY : X86SchedWritePair; +defm WritePHAddZ : X86SchedWritePair; + +// Vector integer operations. +def WriteVecLoad : SchedWrite; +def WriteVecLoadX : SchedWrite; +def WriteVecLoadY : SchedWrite; +def WriteVecLoadNT : SchedWrite; +def WriteVecLoadNTY : SchedWrite; +def WriteVecMaskedLoad : SchedWrite; +def WriteVecMaskedLoadY : SchedWrite; +def WriteVecStore : SchedWrite; +def WriteVecStoreX : SchedWrite; +def WriteVecStoreY : SchedWrite; +def WriteVecStoreNT : SchedWrite; +def WriteVecStoreNTY : SchedWrite; +def WriteVecMaskedStore : SchedWrite; +def WriteVecMaskedStoreY : SchedWrite; +def WriteVecMove : SchedWrite; +def WriteVecMoveX : SchedWrite; +def WriteVecMoveY : SchedWrite; +def WriteVecMoveToGpr : SchedWrite; +def WriteVecMoveFromGpr : SchedWrite; + +defm WriteVecALU : X86SchedWritePair; // Vector integer ALU op, no logicals. +defm WriteVecALUX : X86SchedWritePair; // Vector integer ALU op, no logicals (XMM). +defm WriteVecALUY : X86SchedWritePair; // Vector integer ALU op, no logicals (YMM). +defm WriteVecALUZ : X86SchedWritePair; // Vector integer ALU op, no logicals (ZMM). +defm WriteVecLogic : X86SchedWritePair; // Vector integer and/or/xor logicals. +defm WriteVecLogicX : X86SchedWritePair; // Vector integer and/or/xor logicals (XMM). +defm WriteVecLogicY : X86SchedWritePair; // Vector integer and/or/xor logicals (YMM). +defm WriteVecLogicZ : X86SchedWritePair; // Vector integer and/or/xor logicals (ZMM). +defm WriteVecTest : X86SchedWritePair; // Vector integer TEST instructions. +defm WriteVecTestY : X86SchedWritePair; // Vector integer TEST instructions (YMM). +defm WriteVecTestZ : X86SchedWritePair; // Vector integer TEST instructions (ZMM). +defm WriteVecShift : X86SchedWritePair; // Vector integer shifts (default). +defm WriteVecShiftX : X86SchedWritePair; // Vector integer shifts (XMM). +defm WriteVecShiftY : X86SchedWritePair; // Vector integer shifts (YMM). +defm WriteVecShiftZ : X86SchedWritePair; // Vector integer shifts (ZMM). +defm WriteVecShiftImm : X86SchedWritePair; // Vector integer immediate shifts (default). +defm WriteVecShiftImmX: X86SchedWritePair; // Vector integer immediate shifts (XMM). +defm WriteVecShiftImmY: X86SchedWritePair; // Vector integer immediate shifts (YMM). +defm WriteVecShiftImmZ: X86SchedWritePair; // Vector integer immediate shifts (ZMM). +defm WriteVecIMul : X86SchedWritePair; // Vector integer multiply (default). +defm WriteVecIMulX : X86SchedWritePair; // Vector integer multiply (XMM). +defm WriteVecIMulY : X86SchedWritePair; // Vector integer multiply (YMM). +defm WriteVecIMulZ : X86SchedWritePair; // Vector integer multiply (ZMM). +defm WritePMULLD : X86SchedWritePair; // Vector PMULLD. +defm WritePMULLDY : X86SchedWritePair; // Vector PMULLD (YMM). +defm WritePMULLDZ : X86SchedWritePair; // Vector PMULLD (ZMM). +defm WriteShuffle : X86SchedWritePair; // Vector shuffles. +defm WriteShuffleX : X86SchedWritePair; // Vector shuffles (XMM). +defm WriteShuffleY : X86SchedWritePair; // Vector shuffles (YMM). +defm WriteShuffleZ : X86SchedWritePair; // Vector shuffles (ZMM). +defm WriteVarShuffle : X86SchedWritePair; // Vector variable shuffles. +defm WriteVarShuffleX : X86SchedWritePair; // Vector variable shuffles (XMM). +defm WriteVarShuffleY : X86SchedWritePair; // Vector variable shuffles (YMM). +defm WriteVarShuffleZ : X86SchedWritePair; // Vector variable shuffles (ZMM). +defm WriteBlend : X86SchedWritePair; // Vector blends. +defm WriteBlendY : X86SchedWritePair; // Vector blends (YMM). +defm WriteBlendZ : X86SchedWritePair; // Vector blends (ZMM). +defm WriteVarBlend : X86SchedWritePair; // Vector variable blends. +defm WriteVarBlendY : X86SchedWritePair; // Vector variable blends (YMM). +defm WriteVarBlendZ : X86SchedWritePair; // Vector variable blends (ZMM). +defm WritePSADBW : X86SchedWritePair; // Vector PSADBW. +defm WritePSADBWX : X86SchedWritePair; // Vector PSADBW (XMM). +defm WritePSADBWY : X86SchedWritePair; // Vector PSADBW (YMM). +defm WritePSADBWZ : X86SchedWritePair; // Vector PSADBW (ZMM). +defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD. +defm WriteMPSADY : X86SchedWritePair; // Vector MPSAD (YMM). +defm WriteMPSADZ : X86SchedWritePair; // Vector MPSAD (ZMM). +defm WritePHMINPOS : X86SchedWritePair; // Vector PHMINPOS. + +// Vector insert/extract operations. +defm WriteVecInsert : X86SchedWritePair; // Insert gpr to vector element. +def WriteVecExtract : SchedWrite; // Extract vector element to gpr. +def WriteVecExtractSt : SchedWrite; // Extract vector element and store. + +// MOVMSK operations. +def WriteFMOVMSK : SchedWrite; +def WriteVecMOVMSK : SchedWrite; +def WriteVecMOVMSKY : SchedWrite; +def WriteMMXMOVMSK : SchedWrite; + +// Conversion between integer and float. +defm WriteCvtSD2I : X86SchedWritePair; // Double -> Integer. +defm WriteCvtPD2I : X86SchedWritePair; // Double -> Integer (XMM). +defm WriteCvtPD2IY : X86SchedWritePair; // Double -> Integer (YMM). +defm WriteCvtPD2IZ : X86SchedWritePair; // Double -> Integer (ZMM). + +defm WriteCvtSS2I : X86SchedWritePair; // Float -> Integer. +defm WriteCvtPS2I : X86SchedWritePair; // Float -> Integer (XMM). +defm WriteCvtPS2IY : X86SchedWritePair; // Float -> Integer (YMM). +defm WriteCvtPS2IZ : X86SchedWritePair; // Float -> Integer (ZMM). + +defm WriteCvtI2SD : X86SchedWritePair; // Integer -> Double. +defm WriteCvtI2PD : X86SchedWritePair; // Integer -> Double (XMM). +defm WriteCvtI2PDY : X86SchedWritePair; // Integer -> Double (YMM). +defm WriteCvtI2PDZ : X86SchedWritePair; // Integer -> Double (ZMM). + +defm WriteCvtI2SS : X86SchedWritePair; // Integer -> Float. +defm WriteCvtI2PS : X86SchedWritePair; // Integer -> Float (XMM). +defm WriteCvtI2PSY : X86SchedWritePair; // Integer -> Float (YMM). +defm WriteCvtI2PSZ : X86SchedWritePair; // Integer -> Float (ZMM). + +defm WriteCvtSS2SD : X86SchedWritePair; // Float -> Double size conversion. +defm WriteCvtPS2PD : X86SchedWritePair; // Float -> Double size conversion (XMM). +defm WriteCvtPS2PDY : X86SchedWritePair; // Float -> Double size conversion (YMM). +defm WriteCvtPS2PDZ : X86SchedWritePair; // Float -> Double size conversion (ZMM). + +defm WriteCvtSD2SS : X86SchedWritePair; // Double -> Float size conversion. +defm WriteCvtPD2PS : X86SchedWritePair; // Double -> Float size conversion (XMM). +defm WriteCvtPD2PSY : X86SchedWritePair; // Double -> Float size conversion (YMM). +defm WriteCvtPD2PSZ : X86SchedWritePair; // Double -> Float size conversion (ZMM). + +defm WriteCvtPH2PS : X86SchedWritePair; // Half -> Float size conversion. +defm WriteCvtPH2PSY : X86SchedWritePair; // Half -> Float size conversion (YMM). +defm WriteCvtPH2PSZ : X86SchedWritePair; // Half -> Float size conversion (ZMM). + +def WriteCvtPS2PH : SchedWrite; // // Float -> Half size conversion. +def WriteCvtPS2PHY : SchedWrite; // // Float -> Half size conversion (YMM). +def WriteCvtPS2PHZ : SchedWrite; // // Float -> Half size conversion (ZMM). +def WriteCvtPS2PHSt : SchedWrite; // // Float -> Half + store size conversion. +def WriteCvtPS2PHYSt : SchedWrite; // // Float -> Half + store size conversion (YMM). +def WriteCvtPS2PHZSt : SchedWrite; // // Float -> Half + store size conversion (ZMM). + +// CRC32 instruction. +defm WriteCRC32 : X86SchedWritePair; + +// Strings instructions. +// Packed Compare Implicit Length Strings, Return Mask +defm WritePCmpIStrM : X86SchedWritePair; +// Packed Compare Explicit Length Strings, Return Mask +defm WritePCmpEStrM : X86SchedWritePair; +// Packed Compare Implicit Length Strings, Return Index +defm WritePCmpIStrI : X86SchedWritePair; +// Packed Compare Explicit Length Strings, Return Index +defm WritePCmpEStrI : X86SchedWritePair; + +// AES instructions. +defm WriteAESDecEnc : X86SchedWritePair; // Decryption, encryption. +defm WriteAESIMC : X86SchedWritePair; // InvMixColumn. +defm WriteAESKeyGen : X86SchedWritePair; // Key Generation. + +// Carry-less multiplication instructions. +defm WriteCLMul : X86SchedWritePair; + +// EMMS/FEMMS +def WriteEMMS : SchedWrite; + +// Load/store MXCSR +def WriteLDMXCSR : SchedWrite; +def WriteSTMXCSR : SchedWrite; + +// Catch-all for expensive system instructions. +def WriteSystem : SchedWrite; + +// AVX2. +defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles. +defm WriteFVarShuffle256 : X86SchedWritePair; // Fp 256-bit width variable shuffles. +defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles. +defm WriteVarShuffle256 : X86SchedWritePair; // 256-bit width vector variable shuffles. +defm WriteVarVecShift : X86SchedWritePair; // Variable vector shifts. +defm WriteVarVecShiftY : X86SchedWritePair; // Variable vector shifts (YMM). +defm WriteVarVecShiftZ : X86SchedWritePair; // Variable vector shifts (ZMM). + +// Old microcoded instructions that nobody use. +def WriteMicrocoded : SchedWrite; + +// Fence instructions. +def WriteFence : SchedWrite; + +// Nop, not very useful expect it provides a model for nops! +def WriteNop : SchedWrite; + +// Move/Load/Store wrappers. +def WriteFMoveLS + : X86SchedWriteMoveLS; +def WriteFMoveLSX + : X86SchedWriteMoveLS; +def WriteFMoveLSY + : X86SchedWriteMoveLS; +def SchedWriteFMoveLS + : X86SchedWriteMoveLSWidths; + +def WriteFMoveLSNT + : X86SchedWriteMoveLS; +def WriteFMoveLSNTX + : X86SchedWriteMoveLS; +def WriteFMoveLSNTY + : X86SchedWriteMoveLS; +def SchedWriteFMoveLSNT + : X86SchedWriteMoveLSWidths; + +def WriteVecMoveLS + : X86SchedWriteMoveLS; +def WriteVecMoveLSX + : X86SchedWriteMoveLS; +def WriteVecMoveLSY + : X86SchedWriteMoveLS; +def SchedWriteVecMoveLS + : X86SchedWriteMoveLSWidths; + +def WriteVecMoveLSNT + : X86SchedWriteMoveLS; +def WriteVecMoveLSNTX + : X86SchedWriteMoveLS; +def WriteVecMoveLSNTY + : X86SchedWriteMoveLS; +def SchedWriteVecMoveLSNT + : X86SchedWriteMoveLSWidths; + +// Vector width wrappers. +def SchedWriteFAdd + : X86SchedWriteWidths; +def SchedWriteFAdd64 + : X86SchedWriteWidths; +def SchedWriteFHAdd + : X86SchedWriteWidths; +def SchedWriteFCmp + : X86SchedWriteWidths; +def SchedWriteFCmp64 + : X86SchedWriteWidths; +def SchedWriteFMul + : X86SchedWriteWidths; +def SchedWriteFMul64 + : X86SchedWriteWidths; +def SchedWriteFMA + : X86SchedWriteWidths; +def SchedWriteDPPD + : X86SchedWriteWidths; +def SchedWriteDPPS + : X86SchedWriteWidths; +def SchedWriteFDiv + : X86SchedWriteWidths; +def SchedWriteFDiv64 + : X86SchedWriteWidths; +def SchedWriteFSqrt + : X86SchedWriteWidths; +def SchedWriteFSqrt64 + : X86SchedWriteWidths; +def SchedWriteFRcp + : X86SchedWriteWidths; +def SchedWriteFRsqrt + : X86SchedWriteWidths; +def SchedWriteFRnd + : X86SchedWriteWidths; +def SchedWriteFLogic + : X86SchedWriteWidths; +def SchedWriteFTest + : X86SchedWriteWidths; + +def SchedWriteFShuffle + : X86SchedWriteWidths; +def SchedWriteFVarShuffle + : X86SchedWriteWidths; +def SchedWriteFBlend + : X86SchedWriteWidths; +def SchedWriteFVarBlend + : X86SchedWriteWidths; + +def SchedWriteCvtDQ2PD + : X86SchedWriteWidths; +def SchedWriteCvtDQ2PS + : X86SchedWriteWidths; +def SchedWriteCvtPD2DQ + : X86SchedWriteWidths; +def SchedWriteCvtPS2DQ + : X86SchedWriteWidths; +def SchedWriteCvtPS2PD + : X86SchedWriteWidths; +def SchedWriteCvtPD2PS + : X86SchedWriteWidths; + +def SchedWriteVecALU + : X86SchedWriteWidths; +def SchedWritePHAdd + : X86SchedWriteWidths; +def SchedWriteVecLogic + : X86SchedWriteWidths; +def SchedWriteVecTest + : X86SchedWriteWidths; +def SchedWriteVecShift + : X86SchedWriteWidths; +def SchedWriteVecShiftImm + : X86SchedWriteWidths; +def SchedWriteVarVecShift + : X86SchedWriteWidths; +def SchedWriteVecIMul + : X86SchedWriteWidths; +def SchedWritePMULLD + : X86SchedWriteWidths; +def SchedWriteMPSAD + : X86SchedWriteWidths; +def SchedWritePSADBW + : X86SchedWriteWidths; + +def SchedWriteShuffle + : X86SchedWriteWidths; +def SchedWriteVarShuffle + : X86SchedWriteWidths; +def SchedWriteBlend + : X86SchedWriteWidths; +def SchedWriteVarBlend + : X86SchedWriteWidths; + +// Vector size wrappers. +def SchedWriteFAddSizes + : X86SchedWriteSizes; +def SchedWriteFCmpSizes + : X86SchedWriteSizes; +def SchedWriteFMulSizes + : X86SchedWriteSizes; +def SchedWriteFDivSizes + : X86SchedWriteSizes; +def SchedWriteFSqrtSizes + : X86SchedWriteSizes; +def SchedWriteFLogicSizes + : X86SchedWriteSizes; +def SchedWriteFShuffleSizes + : X86SchedWriteSizes; + +//===----------------------------------------------------------------------===// +// Generic Processor Scheduler Models. + +// IssueWidth is analogous to the number of decode units. Core and its +// descendants, including Nehalem and SandyBridge have 4 decoders. +// Resources beyond the decoder operate on micro-ops and are buffered +// so adjacent micro-ops don't directly compete. +// +// MicroOpBufferSize > 1 indicates that RAW dependencies can be +// decoded in the same cycle. The value 32 is a reasonably arbitrary +// number of in-flight instructions. +// +// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef +// indicates high latency opcodes. Alternatively, InstrItinData +// entries may be included here to define specific operand +// latencies. Since these latencies are not used for pipeline hazards, +// they do not need to be exact. +// +// The GenericX86Model contains no instruction schedules +// and disables PostRAScheduler. +class GenericX86Model : SchedMachineModel { + let IssueWidth = 4; + let MicroOpBufferSize = 32; + let LoadLatency = 4; + let HighLatency = 10; + let PostRAScheduler = 0; + let CompleteModel = 0; +} + +def GenericModel : GenericX86Model; + +// Define a model with the PostRAScheduler enabled. +def GenericPostRAModel : GenericX86Model { + let PostRAScheduler = 1; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86ScheduleAtom.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86ScheduleAtom.td new file mode 100644 index 0000000..daa6fc7 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86ScheduleAtom.td @@ -0,0 +1,917 @@ +//===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the schedule class data for the Intel Atom +// in order (Saltwell-32nm/Bonnell-45nm) processors. +// +//===----------------------------------------------------------------------===// + +// +// Scheduling information derived from the "Intel 64 and IA32 Architectures +// Optimization Reference Manual", Chapter 13, Section 4. + +// Atom machine model. +def AtomModel : SchedMachineModel { + let IssueWidth = 2; // Allows 2 instructions per scheduling group. + let MicroOpBufferSize = 0; // In-order execution, always hide latency. + let LoadLatency = 3; // Expected cycles, may be overridden. + let HighLatency = 30;// Expected, may be overridden. + + // On the Atom, the throughput for taken branches is 2 cycles. For small + // simple loops, expand by a small factor to hide the backedge cost. + let LoopMicroOpBufferSize = 10; + let PostRAScheduler = 1; + let CompleteModel = 0; +} + +let SchedModel = AtomModel in { + +// Functional Units +def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store + // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide +def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA + // SIMD/FP: SIMD ALU, FP Adder + +def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>; + +// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when dispatched by the schedulers. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass AtomWriteResPair RRPorts, + list RMPorts, + int RRLat = 1, int RMLat = 1, + list RRRes = [1], + list RMRes = [1]> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = RRLat; + let ResourceCycles = RRRes; + } + + // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the + // latency. + def : WriteRes { + let Latency = RMLat; + let ResourceCycles = RMRes; + } +} + +// A folded store needs a cycle on Port0 for the store data. +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Arithmetic. +//////////////////////////////////////////////////////////////////////////////// + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; + +defm : X86WriteResPairUnsupported; + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteRes; // x87 conditional move. + +def : WriteRes; +def : WriteRes { + let Latency = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 2; + let ResourceCycles = [2]; +} +def : WriteRes; + +defm : X86WriteResUnsupported; + +// This is for simple LEAs with one or two input operands. +def : WriteRes; + +def AtomWriteIMul16Ld : SchedWriteRes<[AtomPort01]> { + let Latency = 8; + let ResourceCycles = [8]; +} +def : InstRW<[AtomWriteIMul16Ld], (instrs MUL16m, IMUL16m)>; + +def AtomWriteIMul32 : SchedWriteRes<[AtomPort01]> { + let Latency = 6; + let ResourceCycles = [6]; +} +def : InstRW<[AtomWriteIMul32], (instrs MUL32r, IMUL32r)>; + +def AtomWriteIMul64I : SchedWriteRes<[AtomPort01]> { + let Latency = 14; + let ResourceCycles = [14]; +} +def : InstRW<[AtomWriteIMul64I], (instrs IMUL64rri8, IMUL64rri32, + IMUL64rmi8, IMUL64rmi32)>; + +// Bit counts. +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +// BMI1 BEXTR, BMI2 BZHI +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Integer shifts and rotates. +//////////////////////////////////////////////////////////////////////////////// + +defm : AtomWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Loads, stores, and moves, not folded with other operations. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + +//////////////////////////////////////////////////////////////////////////////// +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +//////////////////////////////////////////////////////////////////////////////// + +defm : AtomWriteResPair; + +//////////////////////////////////////////////////////////////////////////////// +// Special case scheduling classes. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes { let Latency = 100; } +def : WriteRes { let Latency = 100; } +def : WriteRes; + +// Nops don't have dependencies, so there's no actual latency, but we set this +// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle. +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Floating point. This covers both scalar and vector operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteRes; +defm : X86WriteRes; +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; + +defm : X86WriteRes; + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Conversions. +//////////////////////////////////////////////////////////////////////////////// + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Vector integer operations. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; +def : WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; +def : WriteRes; +defm : X86WriteResUnsupported; +def : WriteRes; +defm : X86WriteResUnsupported; + +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Vector insert/extract operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : AtomWriteResPair; +def : WriteRes; +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// SSE42 String instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// MOVMSK Instructions. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes { let Latency = 3; let ResourceCycles = [3]; } +def : WriteRes { let Latency = 3; let ResourceCycles = [3]; } +defm : X86WriteResUnsupported; +def : WriteRes { let Latency = 3; let ResourceCycles = [3]; } + +//////////////////////////////////////////////////////////////////////////////// +// AES instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; + +//////////////////////////////////////////////////////////////////////////////// +// Carry-less multiplication instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Load/store MXCSR. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes { let Latency = 5; let ResourceCycles = [5]; } +def : WriteRes { let Latency = 15; let ResourceCycles = [15]; } + +//////////////////////////////////////////////////////////////////////////////// +// Special Cases. +//////////////////////////////////////////////////////////////////////////////// + +// Port0 +def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> { + let Latency = 1; + let ResourceCycles = [1]; +} +def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr, + MOVSX64rr32)>; +def : SchedAlias; +def : SchedAlias; +def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m", + "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>; + +def AtomWrite0_5 : SchedWriteRes<[AtomPort0]> { + let Latency = 5; + let ResourceCycles = [5]; +} +def : InstRW<[AtomWrite0_5], (instregex "IMUL32(rm|rr)")>; + +// Port1 +def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> { + let Latency = 1; + let ResourceCycles = [1]; +} +def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>; +def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r", + "BT(C|R|S)?(16|32|64)(rr|ri8)")>; + +def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> { + let Latency = 5; + let ResourceCycles = [5]; +} +def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm, + MMX_CVTPS2PIirr, MMX_CVTTPS2PIirr)>; + +// Port0 and Port1 +def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> { + let Latency = 1; + let ResourceCycles = [1, 1]; +} +def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r, + POP16rmr, POP32rmr, POP64rmr, + PUSH16r, PUSH32r, PUSH64r, + PUSHi16, PUSHi32, + PUSH16rmr, PUSH32rmr, PUSH64rmr, + PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32, + XCH_F)>; +def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$", + "IRET(16|32|64)?")>; + +def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> { + let Latency = 5; + let ResourceCycles = [5, 5]; +} +def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>; +def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>; + +// Port0 or Port1 +def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> { + let Latency = 1; + let ResourceCycles = [1]; +} +def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT, + LFENCE, + STOSB, STOSL, STOSQ, STOSW, + MOVSSrr, MOVSSrr_REV, + PSLLDQri, PSRLDQri)>; +def : InstRW<[AtomWrite01_1], (instregex "MMX_PACK(SSDW|SSWB|USWB)irr", + "MMX_PUNPCKH(BW|DQ|WD)irr")>; + +def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> { + let Latency = 2; + let ResourceCycles = [2]; +} +def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r, + PUSH16rmm, PUSH32rmm, PUSH64rmm, + LODSB, LODSL, LODSQ, LODSW, + SCASB, SCASL, SCASQ, SCASW)>; +def : InstRW<[AtomWrite01_2], (instregex "BT(C|R|S)(16|32|64)mi8", + "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)", + "XADD(8|16|32|64)rr", + "XCHG(8|16|32|64)(ar|rr)", + "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)", + "MMX_P(ADD|SUB)Qirr", + "MOV(S|Z)X16rr8", + "MOV(UPS|UPD|DQU)mr", + "MASKMOVDQU(64)?", + "P(ADD|SUB)Qrr")>; + +def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> { + let Latency = 3; + let ResourceCycles = [3]; +} +def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm, + CMPSB, CMPSL, CMPSQ, CMPSW, + MOVSB, MOVSL, MOVSQ, MOVSW, + POP16rmm, POP32rmm, POP64rmm)>; +def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm", + "XCHG(8|16|32|64)rm", + "PH(ADD|SUB)Drr", + "MOV(S|Z)X16rm8", + "MMX_P(ADD|SUB)Qirm", + "MOV(UPS|UPD|DQU)rm", + "P(ADD|SUB)Qrm")>; + +def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> { + let Latency = 4; + let ResourceCycles = [4]; +} +def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO, + JCXZ, JECXZ, JRCXZ, + LD_F80m)>; +def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm", + "(MMX_)?PEXTRWrr(_REV)?")>; + +def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> { + let Latency = 5; + let ResourceCycles = [5]; +} +def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>; +def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>; + +def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> { + let Latency = 6; + let ResourceCycles = [6]; +} +def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT, + SHLD16rrCL, SHRD16rrCL, + SHLD16rri8, SHRD16rri8, + SHLD16mrCL, SHRD16mrCL, + SHLD16mri8, SHRD16mri8)>; +def : InstRW<[AtomWrite01_6], (instregex "IMUL16rr", + "IST_F(P)?(16|32|64)?m", + "MMX_PH(ADD|SUB)S?Wrm")>; + +def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> { + let Latency = 7; + let ResourceCycles = [7]; +} +def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>; + +def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> { + let Latency = 8; + let ResourceCycles = [8]; +} +def : InstRW<[AtomWrite01_8], (instrs LOOPE, + PUSHA16, PUSHA32, + SHLD64rrCL, SHRD64rrCL, + FNSTCW16m)>; + +def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> { + let Latency = 9; + let ResourceCycles = [9]; +} +def : InstRW<[AtomWrite01_9], (instrs BT16mr, BT32mr, BT64mr, + POPA16, POPA32, + PUSHF16, PUSHF32, PUSHF64, + SHLD64mrCL, SHRD64mrCL, + SHLD64mri8, SHRD64mri8, + SHLD64rri8, SHRD64rri8, + CMPXCHG8rr)>; +def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F", + "(U)?COMIS(D|S)rr", + "CVT(T)?SS2SI64rr(_Int)?")>; + +def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> { + let Latency = 10; + let ResourceCycles = [10]; +} +def : SchedAlias; +def : InstRW<[AtomWrite01_10], (instregex "(U)?COMIS(D|S)rm", + "CVT(T)?SS2SI64rm(_Int)?")>; + +def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> { + let Latency = 11; + let ResourceCycles = [11]; +} +def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>; +def : InstRW<[AtomWrite01_11], (instregex "BT(C|R|S)(16|32|64)mr")>; + +def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> { + let Latency = 13; + let ResourceCycles = [13]; +} +def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>; + +def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> { + let Latency = 14; + let ResourceCycles = [14]; +} +def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>; + +def AtomWrite01_15 : SchedWriteRes<[AtomPort01]> { + let Latency = 15; + let ResourceCycles = [15]; +} +def : InstRW<[AtomWrite01_15], (instrs CMPXCHG16rr, CMPXCHG32rr, CMPXCHG64rr)>; + +def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> { + let Latency = 17; + let ResourceCycles = [17]; +} +def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>; + +def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> { + let Latency = 18; + let ResourceCycles = [18]; +} +def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>; + +def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> { + let Latency = 20; + let ResourceCycles = [20]; +} +def : InstRW<[AtomWrite01_20], (instrs DAS)>; + +def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> { + let Latency = 21; + let ResourceCycles = [21]; +} +def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>; + +def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> { + let Latency = 22; + let ResourceCycles = [22]; +} +def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>; + +def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> { + let Latency = 23; + let ResourceCycles = [23]; +} +def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>; + +def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> { + let Latency = 25; + let ResourceCycles = [25]; +} +def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>; + +def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> { + let Latency = 26; + let ResourceCycles = [26]; +} +def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>; + +def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> { + let Latency = 29; + let ResourceCycles = [29]; +} +def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>; + +def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> { + let Latency = 30; + let ResourceCycles = [30]; +} +def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>; + +def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> { + let Latency = 32; + let ResourceCycles = [32]; +} +def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>; + +def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> { + let Latency = 45; + let ResourceCycles = [45]; +} +def : InstRW<[AtomWrite01_45], (instrs MONITORrrr)>; + +def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> { + let Latency = 46; + let ResourceCycles = [46]; +} +def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>; + +def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> { + let Latency = 48; + let ResourceCycles = [48]; +} +def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>; + +def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> { + let Latency = 55; + let ResourceCycles = [55]; +} +def : InstRW<[AtomWrite01_55], (instrs FPREM)>; + +def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> { + let Latency = 59; + let ResourceCycles = [59]; +} +def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>; + +def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> { + let Latency = 63; + let ResourceCycles = [63]; +} +def : InstRW<[AtomWrite01_63], (instrs FNINIT)>; + +def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> { + let Latency = 68; + let ResourceCycles = [68]; +} +def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>; + +def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> { + let Latency = 71; + let ResourceCycles = [71]; +} +def : InstRW<[AtomWrite01_71], (instrs FPREM1, + INVLPG, INVLPGA32, INVLPGA64)>; + +def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> { + let Latency = 72; + let ResourceCycles = [72]; +} +def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>; + +def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> { + let Latency = 74; + let ResourceCycles = [74]; +} +def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>; + +def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> { + let Latency = 77; + let ResourceCycles = [77]; +} +def : InstRW<[AtomWrite01_77], (instrs FSCALE)>; + +def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> { + let Latency = 78; + let ResourceCycles = [78]; +} +def : InstRW<[AtomWrite01_78], (instrs RDMSR)>; + +def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> { + let Latency = 79; + let ResourceCycles = [79]; +} +def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$", + "LRETI?(L|Q|W)")>; + +def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> { + let Latency = 92; + let ResourceCycles = [92]; +} +def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>; + +def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> { + let Latency = 94; + let ResourceCycles = [94]; +} +def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>; + +def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> { + let Latency = 99; + let ResourceCycles = [99]; +} +def : InstRW<[AtomWrite01_99], (instrs F2XM1)>; + +def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> { + let Latency = 121; + let ResourceCycles = [121]; +} +def : InstRW<[AtomWrite01_121], (instrs CPUID)>; + +def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> { + let Latency = 127; + let ResourceCycles = [127]; +} +def : InstRW<[AtomWrite01_127], (instrs INT)>; + +def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> { + let Latency = 130; + let ResourceCycles = [130]; +} +def : InstRW<[AtomWrite01_130], (instrs INT3)>; + +def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> { + let Latency = 140; + let ResourceCycles = [140]; +} +def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>; + +def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> { + let Latency = 141; + let ResourceCycles = [141]; +} +def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>; + +def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> { + let Latency = 146; + let ResourceCycles = [146]; +} +def : InstRW<[AtomWrite01_146], (instrs FYL2X)>; + +def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> { + let Latency = 147; + let ResourceCycles = [147]; +} +def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>; + +def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> { + let Latency = 168; + let ResourceCycles = [168]; +} +def : InstRW<[AtomWrite01_168], (instrs FPTAN)>; + +def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> { + let Latency = 174; + let ResourceCycles = [174]; +} +def : InstRW<[AtomWrite01_174], (instrs FSINCOS)>; +def : InstRW<[AtomWrite01_174], (instregex "(COS|SIN)_F")>; + +def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> { + let Latency = 183; + let ResourceCycles = [183]; +} +def : InstRW<[AtomWrite01_183], (instrs FPATAN)>; + +def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> { + let Latency = 202; + let ResourceCycles = [202]; +} +def : InstRW<[AtomWrite01_202], (instrs WRMSR)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86ScheduleBtVer2.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86ScheduleBtVer2.td new file mode 100644 index 0000000..719e71c --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86ScheduleBtVer2.td @@ -0,0 +1,682 @@ +//=- X86ScheduleBtVer2.td - X86 BtVer2 (Jaguar) Scheduling ---*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for AMD btver2 (Jaguar) to support +// instruction scheduling and other instruction cost heuristics. Based off AMD Software +// Optimization Guide for AMD Family 16h Processors & Instruction Latency appendix. +// +//===----------------------------------------------------------------------===// + +def BtVer2Model : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and btver2 can + // decode 2 instructions per cycle. + let IssueWidth = 2; + let MicroOpBufferSize = 64; // Retire Control Unit + let LoadLatency = 5; // FPU latency (worse case cf Integer 3 cycle latency) + let HighLatency = 25; + let MispredictPenalty = 14; // Minimum branch misdirection penalty + let PostRAScheduler = 1; + + // FIXME: SSE4/AVX is unimplemented. This flag is set to allow + // the scheduler to assign a default model to unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = BtVer2Model in { + +// Jaguar can issue up to 6 micro-ops in one cycle +def JALU0 : ProcResource<1>; // Integer Pipe0: integer ALU0 (also handle FP->INT jam) +def JALU1 : ProcResource<1>; // Integer Pipe1: integer ALU1/MUL/DIV +def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU +def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA) +def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA +def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM + +// The Integer PRF for Jaguar is 64 entries, and it holds the architectural and +// speculative version of the 64-bit integer registers. +// Reference: www.realworldtech.com/jaguar/4/ +// +// The processor always keeps the different parts of an integer register +// together. An instruction that writes to a part of a register will therefore +// have a false dependence on any previous write to the same register or any +// part of it. +// Reference: Section 21.10 "AMD Bobcat and Jaguar pipeline: Partial register +// access" - Agner Fog's "microarchitecture.pdf". +def JIntegerPRF : RegisterFile<64, [GR64, CCR]>; + +// The Jaguar FP Retire Queue renames SIMD and FP uOps onto a pool of 72 SSE +// registers. Operations on 256-bit data types are cracked into two COPs. +// Reference: www.realworldtech.com/jaguar/4/ +def JFpuPRF: RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]>; + +// The retire control unit (RCU) can track up to 64 macro-ops in-flight. It can +// retire up to two macro-ops per cycle. +// Reference: "Software Optimization Guide for AMD Family 16h Processors" +def JRCU : RetireControlUnit<64, 2>; + +// Integer Pipe Scheduler +def JALU01 : ProcResGroup<[JALU0, JALU1]> { + let BufferSize=20; +} + +// AGU Pipe Scheduler +def JLSAGU : ProcResGroup<[JLAGU, JSAGU]> { + let BufferSize=12; +} + +// Fpu Pipe Scheduler +def JFPU01 : ProcResGroup<[JFPU0, JFPU1]> { + let BufferSize=18; +} + +// Functional units +def JDiv : ProcResource<1>; // integer division +def JMul : ProcResource<1>; // integer multiplication +def JVALU0 : ProcResource<1>; // vector integer +def JVALU1 : ProcResource<1>; // vector integer +def JVIMUL : ProcResource<1>; // vector integer multiplication +def JSTC : ProcResource<1>; // vector store/convert +def JFPM : ProcResource<1>; // FP multiplication +def JFPA : ProcResource<1>; // FP addition + +// Functional unit groups +def JFPX : ProcResGroup<[JFPA, JFPM]>; +def JVALU : ProcResGroup<[JVALU0, JVALU1]>; + +// Integer loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when dispatched by the schedulers. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass JWriteResIntPair ExePorts, + int Lat, list Res = [], int UOps = 1> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the + // latency. + def : WriteRes { + let Latency = !add(Lat, 3); + let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res)); + let NumMicroOps = UOps; + } +} + +multiclass JWriteResFpuPair ExePorts, + int Lat, list Res = [], int UOps = 1> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on JLAGU and adds 5 cycles to the + // latency. + def : WriteRes { + let Latency = !add(Lat, 5); + let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res)); + let NumMicroOps = UOps; + } +} + +multiclass JWriteResYMMPair ExePorts, + int Lat, list Res = [2], int UOps = 2> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses 2 cycles on JLAGU and adds 5 cycles to the + // latency. + def : WriteRes { + let Latency = !add(Lat, 5); + let ResourceCycles = !listconcat([2], Res); + let NumMicroOps = UOps; + } +} + +// A folded store needs a cycle on the SAGU for the store data. +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Arithmetic. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; // i8/i16/i32 multiplication +defm : JWriteResIntPair; // i64 multiplication +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; + +defm : JWriteResIntPair; + +defm : JWriteResIntPair; // Conditional move. +defm : JWriteResIntPair; // Conditional (CF + ZF flag) move. +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; // Setcc. +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// This is for simple LEAs with one or two input operands. +def : WriteRes; + +// Bit counts. +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; + +// BMI1 BEXTR, BMI2 BZHI +defm : JWriteResIntPair; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Integer shifts and rotates. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResIntPair; + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Loads, stores, and moves, not folded with other operations. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes { let Latency = 5; } +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// Load/store MXCSR. +// FIXME: These are copy and pasted from WriteLoad/Store. +def : WriteRes { let Latency = 5; } +def : WriteRes; + +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + +//////////////////////////////////////////////////////////////////////////////// +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResIntPair; + +//////////////////////////////////////////////////////////////////////////////// +// Special case scheduling classes. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes { let Latency = 100; } +def : WriteRes { let Latency = 100; } +def : WriteRes; + +// Nops don't have dependencies, so there's no actual latency, but we set this +// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle. +def : WriteRes { let Latency = 1; } + +//////////////////////////////////////////////////////////////////////////////// +// Floating point. This covers both scalar and vector operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Conversions. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; + +// FIXME: f+3 ST, LD+STC latency +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; + +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Vector integer operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Vector insert/extract operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// SSE42 String instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; + +//////////////////////////////////////////////////////////////////////////////// +// MOVMSK Instructions. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +defm : X86WriteResUnsupported; +def : WriteRes { let Latency = 3; } + +//////////////////////////////////////////////////////////////////////////////// +// AES Instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Carry-less multiplication instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResFpuPair; + +//////////////////////////////////////////////////////////////////////////////// +// SSE4A instructions. +//////////////////////////////////////////////////////////////////////////////// + +def JWriteINSERTQ: SchedWriteRes<[JFPU01, JVALU]> { + let Latency = 2; + let ResourceCycles = [1, 4]; +} +def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>; + +//////////////////////////////////////////////////////////////////////////////// +// AVX instructions. +//////////////////////////////////////////////////////////////////////////////// + +def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> { + let Latency = 6; + let ResourceCycles = [1, 2, 4]; + let NumMicroOps = 2; +} +def : InstRW<[JWriteVBROADCASTYLd, ReadAfterLd], (instrs VBROADCASTSDYrm, + VBROADCASTSSYrm)>; + +def JWriteJVZEROALL: SchedWriteRes<[]> { + let Latency = 90; + let NumMicroOps = 73; +} +def : InstRW<[JWriteJVZEROALL], (instrs VZEROALL)>; + +def JWriteJVZEROUPPER: SchedWriteRes<[]> { + let Latency = 46; + let NumMicroOps = 37; +} +def : InstRW<[JWriteJVZEROUPPER], (instrs VZEROUPPER)>; + +/////////////////////////////////////////////////////////////////////////////// +// SchedWriteVariant definitions. +/////////////////////////////////////////////////////////////////////////////// + +def JWriteZeroLatency : SchedWriteRes<[]> { + let Latency = 0; +} + +// Certain instructions that use the same register for both source +// operands do not have a real dependency on the previous contents of the +// register, and thus, do not have to wait before completing. They can be +// optimized out at register renaming stage. +// Reference: Section 10.8 of the "Software Optimization Guide for AMD Family +// 15h Processors". +// Reference: Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", +// Section 21.8 [Dependency-breaking instructions]. + +def JWriteZeroIdiom : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteALU]> +]>; +def : InstRW<[JWriteZeroIdiom], (instrs SUB32rr, SUB64rr, + XOR32rr, XOR64rr)>; + +def JWriteFZeroIdiom : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteFLogic]> +]>; +def : InstRW<[JWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, VXORPDrr, + ANDNPSrr, VANDNPSrr, + ANDNPDrr, VANDNPDrr)>; + +def JWriteVZeroIdiomLogic : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteVecLogic]> +]>; +def : InstRW<[JWriteVZeroIdiomLogic], (instrs MMX_PXORirr, MMX_PANDNirr)>; + +def JWriteVZeroIdiomLogicX : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteVecLogicX]> +]>; +def : InstRW<[JWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr, + PANDNrr, VPANDNrr)>; + +def JWriteVZeroIdiomALU : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteVecALU]> +]>; +def : InstRW<[JWriteVZeroIdiomALU], (instrs MMX_PSUBBirr, MMX_PSUBDirr, + MMX_PSUBQirr, MMX_PSUBWirr, + MMX_PCMPGTBirr, MMX_PCMPGTDirr, + MMX_PCMPGTWirr)>; + +def JWriteVZeroIdiomALUX : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteVecALUX]> +]>; +def : InstRW<[JWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, + PSUBDrr, VPSUBDrr, + PSUBQrr, VPSUBQrr, + PSUBWrr, VPSUBWrr, + PCMPGTBrr, VPCMPGTBrr, + PCMPGTDrr, VPCMPGTDrr, + PCMPGTQrr, VPCMPGTQrr, + PCMPGTWrr, VPCMPGTWrr)>; + +// This write is used for slow LEA instructions. +def JWrite3OpsLEA : SchedWriteRes<[JALU1, JSAGU]> { + let Latency = 2; +} + +// On Jaguar, a slow LEA is either a 3Ops LEA (base, index, offset), or an LEA +// with a `Scale` value different than 1. +def JSlowLEAPredicate : MCSchedPredicate< + CheckAny<[ + // A 3-operand LEA (base, index, offset). + IsThreeOperandsLEAFn, + // An LEA with a "Scale" different than 1. + CheckAll<[ + CheckIsImmOperand<2>, + CheckNot> + ]> + ]> +>; + +def JWriteLEA : SchedWriteVariant<[ + SchedVar, + SchedVar, [WriteLEA]> +]>; + +def : InstRW<[JWriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>; + +def JSlowLEA16r : SchedWriteRes<[JALU01]> { + let Latency = 3; + let ResourceCycles = [4]; +} + +def : InstRW<[JSlowLEA16r], (instrs LEA16r)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86ScheduleSLM.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86ScheduleSLM.td new file mode 100644 index 0000000..b1e8430 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86ScheduleSLM.td @@ -0,0 +1,486 @@ +//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Intel Silvermont to support +// instruction scheduling and other instruction cost heuristics. +// +//===----------------------------------------------------------------------===// + +def SLMModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and SLM can decode 2 + // instructions per cycle. + let IssueWidth = 2; + let MicroOpBufferSize = 32; // Based on the reorder buffer. + let LoadLatency = 3; + let MispredictPenalty = 10; + let PostRAScheduler = 1; + + // For small loops, expand by a small factor to hide the backedge cost. + let LoopMicroOpBufferSize = 10; + + // FIXME: SSE4 is unimplemented. This flag is set to allow + // the scheduler to assign a default model to unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = SLMModel in { + +// Silvermont has 5 reservation stations for micro-ops +def SLM_IEC_RSV0 : ProcResource<1>; +def SLM_IEC_RSV1 : ProcResource<1>; +def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; } +def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; } +def SLM_MEC_RSV : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def SLM_IEC_RSV01 : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>; +def SLM_FPC_RSV01 : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>; + +def SLMDivider : ProcResource<1>; +def SLMFPMultiplier : ProcResource<1>; +def SLMFPDivider : ProcResource<1>; + +// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass SLMWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 3> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to + // the latency (default = 3). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = UOps; + } +} + +// A folded store needs a cycle on MEC_RSV for the store data, but it does not +// need an extra port cycle to recompute the address. +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes { let Latency = 3; } +def : WriteRes; +def : WriteRes; + +// Load/store MXCSR. +// FIXME: These are probably wrong. They are copy pasted from WriteStore/Load. +def : WriteRes; +def : WriteRes { let Latency = 3; } + +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SLMWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; +def : WriteRes { + // FIXME Latency and NumMicrOps? + let ResourceCycles = [2,1]; +} +def : WriteRes; +def : WriteRes; + +// This is for simple LEAs with one or two input operands. +// The complex ones can only execute on port 1, and they require two cycles on +// the port to read all inputs. We don't model that. +def : WriteRes; + +// Bit counts. +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; + +// BMI1 BEXTR, BMI2 BZHI +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; + +// Scalar and vector floating point. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +defm : X86WriteRes; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; + +// Conversion between integer and float. +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; + +// Vector integer operations. +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +// FIXME: The below is closer to correct, but caused some perf regressions. +//defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; + +// Vector insert/extract operations. +defm : SLMWriteResPair; + +def : WriteRes; +def : WriteRes { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1, 2]; +} + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; + +// String instructions. +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 13; + let ResourceCycles = [13]; +} +def : WriteRes { + let Latency = 13; + let ResourceCycles = [13, 1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 17; + let ResourceCycles = [17]; +} +def : WriteRes { + let Latency = 17; + let ResourceCycles = [17, 1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 17; + let ResourceCycles = [17]; +} +def : WriteRes { + let Latency = 17; + let ResourceCycles = [17, 1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 21; + let ResourceCycles = [21]; +} +def : WriteRes { + let Latency = 21; + let ResourceCycles = [21, 1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 4; } +def : WriteRes { let Latency = 4; } +def : WriteRes { let Latency = 4; } +def : WriteRes { let Latency = 4; } + +// AES Instructions. +def : WriteRes { + let Latency = 8; + let ResourceCycles = [5]; +} +def : WriteRes { + let Latency = 8; + let ResourceCycles = [5, 1]; +} + +def : WriteRes { + let Latency = 8; + let ResourceCycles = [5]; +} +def : WriteRes { + let Latency = 8; + let ResourceCycles = [5, 1]; +} + +def : WriteRes { + let Latency = 8; + let ResourceCycles = [5]; +} +def : WriteRes { + let Latency = 8; + let ResourceCycles = [5, 1]; +} + +// Carry-less multiplication instructions. +def : WriteRes { + let Latency = 10; + let ResourceCycles = [10]; +} +def : WriteRes { + let Latency = 10; + let ResourceCycles = [10, 1]; +} + +def : WriteRes { let Latency = 100; } +def : WriteRes { let Latency = 100; } +def : WriteRes; +def : WriteRes; + +// AVX/FMA is not supported on that architecture, but we should define the basic +// scheduling resources anyway. +def : WriteRes; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86ScheduleZnver1.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86ScheduleZnver1.td new file mode 100644 index 0000000..7184b85 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86ScheduleZnver1.td @@ -0,0 +1,1544 @@ +//=- X86ScheduleZnver1.td - X86 Znver1 Scheduling -------------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Znver1 to support instruction +// scheduling and other instruction cost heuristics. +// +//===----------------------------------------------------------------------===// + +def Znver1Model : SchedMachineModel { + // Zen can decode 4 instructions per cycle. + let IssueWidth = 4; + // Based on the reorder buffer we define MicroOpBufferSize + let MicroOpBufferSize = 192; + let LoadLatency = 4; + let MispredictPenalty = 17; + let HighLatency = 25; + let PostRAScheduler = 1; + + // FIXME: This variable is required for incomplete model. + // We haven't catered all instructions. + // So, we reset the value of this variable so as to + // say that the model is incomplete. + let CompleteModel = 0; +} + +let SchedModel = Znver1Model in { + +// Zen can issue micro-ops to 10 different units in one cycle. +// These are +// * Four integer ALU units (ZALU0, ZALU1, ZALU2, ZALU3) +// * Two AGU units (ZAGU0, ZAGU1) +// * Four FPU units (ZFPU0, ZFPU1, ZFPU2, ZFPU3) +// AGUs feed load store queues @two loads and 1 store per cycle. + +// Four ALU units are defined below +def ZnALU0 : ProcResource<1>; +def ZnALU1 : ProcResource<1>; +def ZnALU2 : ProcResource<1>; +def ZnALU3 : ProcResource<1>; + +// Two AGU units are defined below +def ZnAGU0 : ProcResource<1>; +def ZnAGU1 : ProcResource<1>; + +// Four FPU units are defined below +def ZnFPU0 : ProcResource<1>; +def ZnFPU1 : ProcResource<1>; +def ZnFPU2 : ProcResource<1>; +def ZnFPU3 : ProcResource<1>; + +// FPU grouping +def ZnFPU013 : ProcResGroup<[ZnFPU0, ZnFPU1, ZnFPU3]>; +def ZnFPU01 : ProcResGroup<[ZnFPU0, ZnFPU1]>; +def ZnFPU12 : ProcResGroup<[ZnFPU1, ZnFPU2]>; +def ZnFPU13 : ProcResGroup<[ZnFPU1, ZnFPU3]>; +def ZnFPU23 : ProcResGroup<[ZnFPU2, ZnFPU3]>; +def ZnFPU02 : ProcResGroup<[ZnFPU0, ZnFPU2]>; +def ZnFPU03 : ProcResGroup<[ZnFPU0, ZnFPU3]>; + +// Below are the grouping of the units. +// Micro-ops to be issued to multiple units are tackled this way. + +// ALU grouping +// ZnALU03 - 0,3 grouping +def ZnALU03: ProcResGroup<[ZnALU0, ZnALU3]>; + +// 56 Entry (14x4 entries) Int Scheduler +def ZnALU : ProcResGroup<[ZnALU0, ZnALU1, ZnALU2, ZnALU3]> { + let BufferSize=56; +} + +// 28 Entry (14x2) AGU group. AGUs can't be used for all ALU operations +// but are relevant for some instructions +def ZnAGU : ProcResGroup<[ZnAGU0, ZnAGU1]> { + let BufferSize=28; +} + +// Integer Multiplication issued on ALU1. +def ZnMultiplier : ProcResource<1>; + +// Integer division issued on ALU2. +def ZnDivider : ProcResource<1>; + +// 4 Cycles load-to use Latency is captured +def : ReadAdvance; + +// The Integer PRF for Zen is 168 entries, and it holds the architectural and +// speculative version of the 64-bit integer registers. +// Reference: "Software Optimization Guide for AMD Family 17h Processors" +def ZnIntegerPRF : RegisterFile<168, [GR64, CCR]>; + +// 36 Entry (9x4 entries) floating-point Scheduler +def ZnFPU : ProcResGroup<[ZnFPU0, ZnFPU1, ZnFPU2, ZnFPU3]> { +let BufferSize=36; +} + +// The Zen FP Retire Queue renames SIMD and FP uOps onto a pool of 160 128-bit +// registers. Operations on 256-bit data types are cracked into two COPs. +// Reference: "Software Optimization Guide for AMD Family 17h Processors" +def ZnFpuPRF: RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>; + +// The unit can track up to 192 macro ops in-flight. +// The retire unit handles in-order commit of up to 8 macro ops per cycle. +// Reference: "Software Optimization Guide for AMD Family 17h Processors" +// To be noted, the retire unit is shared between integer and FP ops. +// In SMT mode it is 96 entry per thread. But, we do not use the conservative +// value here because there is currently no way to fully mode the SMT mode, +// so there is no point in trying. +def ZnRCU : RetireControlUnit<192, 8>; + +// FIXME: there are 72 read buffers and 44 write buffers. + +// (a folded load is an instruction that loads and does some operation) +// Ex: ADDPD xmm,[mem]-> This instruction has two micro-ops +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops. +// a. load and +// b. addpd +// This multiclass is for folded loads for integer units. +multiclass ZnWriteResPair ExePorts, + int Lat, list Res = [], int UOps = 1, + int LoadLat = 4, int LoadUOps = 1> { + // Register variant takes 1-cycle on Execution Port. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on ZnAGU + // adds LoadLat cycles to the latency (default = 4). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res)); + let NumMicroOps = !add(UOps, LoadUOps); + } +} + +// This multiclass is for folded loads for floating point units. +multiclass ZnWriteResFpuPair ExePorts, + int Lat, list Res = [], int UOps = 1, + int LoadLat = 7, int LoadUOps = 0> { + // Register variant takes 1-cycle on Execution Port. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on ZnAGU + // adds LoadLat cycles to the latency (default = 7). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res)); + let NumMicroOps = !add(UOps, LoadUOps); + } +} + +// WriteRMW is set for instructions with Memory write +// operation in codegen +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes { let Latency = 8; } + +def : WriteRes; +def : WriteRes; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : ZnWriteResPair; + +defm : X86WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +defm : ZnWriteResPair; +defm : ZnWriteResFpuPair; + +defm : ZnWriteResPair; +defm : ZnWriteResPair; +def : WriteRes; +def : WriteRes; +defm : X86WriteRes; +def : WriteRes; + +// Bit counts. +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; + +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + +// BMI1 BEXTR, BMI2 BZHI +defm : ZnWriteResPair; +defm : ZnWriteResPair; + +// IDIV +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; + +// IMULH +def : WriteRes{ + let Latency = 4; +} + +// Floating point operations +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +//defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +//defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; // FIXME: Should folds require 1 extra uops? +defm : ZnWriteResFpuPair; // FIXME: Should folds require 1 extra uops? +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +//defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +//defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; + +// Vector integer operations which uses FPU units +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; // FIXME +defm : ZnWriteResFpuPair; // FIXME +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; + +// Vector Shift Operations +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; + +// Vector insert/extract operations. +defm : ZnWriteResFpuPair; + +def : WriteRes { + let Latency = 2; + let ResourceCycles = [1, 2]; +} +def : WriteRes { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1, 2, 3]; +} + +// MOVMSK Instructions. +def : WriteRes; +def : WriteRes; +def : WriteRes; + +def : WriteRes { + let NumMicroOps = 2; + let Latency = 2; + let ResourceCycles = [2]; +} + +// AES Instructions. +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; + +def : WriteRes; +def : WriteRes; + +// Following instructions with latency=100 are microcoded. +// We set long latency so as to block the entire pipeline. +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; + +// Microcoded Instructions +def ZnWriteMicrocoded : SchedWriteRes<[]> { + let Latency = 100; +} + +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; + +//=== Regex based InstRW ===// +// Notation: +// - r: register. +// - m = memory. +// - i = immediate +// - mm: 64 bit mmx register. +// - x = 128 bit xmm register. +// - (x)mm = mmx or xmm register. +// - y = 256 bit ymm register. +// - v = any vector register. + +//=== Integer Instructions ===// +//-- Move instructions --// +// MOV. +// r16,m. +def : InstRW<[WriteALULd, ReadAfterLd], (instregex "MOV16rm")>; + +// MOVSX, MOVZX. +// r,m. +def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>; + +// XCHG. +// r,r. +def ZnWriteXCHG : SchedWriteRes<[ZnALU]> { + let NumMicroOps = 2; + let ResourceCycles = [2]; +} + +def : InstRW<[ZnWriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>; + +// r,m. +def ZnWriteXCHGrm : SchedWriteRes<[ZnAGU, ZnALU]> { + let Latency = 5; + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteXCHGrm, ReadAfterLd], (instregex "XCHG(8|16|32|64)rm")>; + +def : InstRW<[WriteMicrocoded], (instrs XLAT)>; + +// POP16. +// r. +def ZnWritePop16r : SchedWriteRes<[ZnAGU]>{ + let Latency = 5; + let NumMicroOps = 2; +} +def : InstRW<[ZnWritePop16r], (instregex "POP16rmm")>; +def : InstRW<[WriteMicrocoded], (instregex "POPF(16|32)")>; +def : InstRW<[WriteMicrocoded], (instregex "POPA(16|32)")>; + + +// PUSH. +// r. Has default values. +// m. +def ZnWritePUSH : SchedWriteRes<[ZnAGU]>{ + let Latency = 4; +} +def : InstRW<[ZnWritePUSH], (instregex "PUSH(16|32)rmm")>; + +//PUSHF +def : InstRW<[WriteMicrocoded], (instregex "PUSHF(16|32)")>; + +// PUSHA. +def ZnWritePushA : SchedWriteRes<[ZnAGU]> { + let Latency = 8; +} +def : InstRW<[ZnWritePushA], (instregex "PUSHA(16|32)")>; + +//LAHF +def : InstRW<[WriteMicrocoded], (instrs LAHF)>; + +// MOVBE. +// r,m. +def ZnWriteMOVBE : SchedWriteRes<[ZnAGU, ZnALU]> { + let Latency = 5; +} +def : InstRW<[ZnWriteMOVBE, ReadAfterLd], (instregex "MOVBE(16|32|64)rm")>; + +// m16,r16. +def : InstRW<[ZnWriteMOVBE], (instregex "MOVBE(16|32|64)mr")>; + +//-- Arithmetic instructions --// + +// ADD SUB. +// m,r/i. +def : InstRW<[WriteALULd], (instregex "(ADD|SUB)(8|16|32|64)m(r|i)", + "(ADD|SUB)(8|16|32|64)mi8", + "(ADD|SUB)64mi32")>; + +// ADC SBB. +// m,r/i. +def : InstRW<[WriteALULd], + (instregex "(ADC|SBB)(8|16|32|64)m(r|i)", + "(ADC|SBB)(16|32|64)mi8", + "(ADC|SBB)64mi32")>; + +// INC DEC NOT NEG. +// m. +def : InstRW<[WriteALULd], + (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m")>; + +// MUL IMUL. +// r16. +def ZnWriteMul16 : SchedWriteRes<[ZnALU1, ZnMultiplier]> { + let Latency = 3; +} +def : InstRW<[ZnWriteMul16], (instrs IMUL16r, MUL16r)>; +def : InstRW<[ZnWriteMul16], (instrs IMUL16rr, IMUL16rri, IMUL16rri8)>; // TODO: is this right? +def : InstRW<[ZnWriteMul16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>; // TODO: this is definitely wrong but matches what the instregex did. + +// m16. +def ZnWriteMul16Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { + let Latency = 8; +} +def : InstRW<[ZnWriteMul16Ld, ReadAfterLd], (instrs IMUL16m, MUL16m)>; + +// r32. +def ZnWriteMul32 : SchedWriteRes<[ZnALU1, ZnMultiplier]> { + let Latency = 3; +} +def : InstRW<[ZnWriteMul32], (instrs IMUL32r, MUL32r)>; +def : InstRW<[ZnWriteMul32], (instrs IMUL32rr, IMUL32rri, IMUL32rri8)>; // TODO: is this right? +def : InstRW<[ZnWriteMul32], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8)>; // TODO: this is definitely wrong but matches what the instregex did. + +// m32. +def ZnWriteMul32Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { + let Latency = 8; +} +def : InstRW<[ZnWriteMul32Ld, ReadAfterLd], (instrs IMUL32m, MUL32m)>; + +// r64. +def ZnWriteMul64 : SchedWriteRes<[ZnALU1, ZnMultiplier]> { + let Latency = 4; + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteMul64], (instrs IMUL64r, MUL64r)>; +def : InstRW<[ZnWriteMul64], (instrs IMUL64rr, IMUL64rri8, IMUL64rri32)>; // TODO: is this right? +def : InstRW<[ZnWriteMul64], (instrs IMUL64rm, IMUL64rmi32, IMUL64rmi8)>; // TODO: this is definitely wrong but matches what the instregex did. + +// m64. +def ZnWriteMul64Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { + let Latency = 9; + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteMul64Ld, ReadAfterLd], (instrs IMUL64m, MUL64m)>; + +// MULX. +// r32,r32,r32. +def ZnWriteMulX32 : SchedWriteRes<[ZnALU1, ZnMultiplier]> { + let Latency = 3; + let ResourceCycles = [1, 2]; +} +def : InstRW<[ZnWriteMulX32], (instrs MULX32rr)>; + +// r32,r32,m32. +def ZnWriteMulX32Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { + let Latency = 8; + let ResourceCycles = [1, 2, 2]; +} +def : InstRW<[ZnWriteMulX32Ld, ReadAfterLd], (instrs MULX32rm)>; + +// r64,r64,r64. +def ZnWriteMulX64 : SchedWriteRes<[ZnALU1]> { + let Latency = 3; +} +def : InstRW<[ZnWriteMulX64], (instrs MULX64rr)>; + +// r64,r64,m64. +def ZnWriteMulX64Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { + let Latency = 8; +} +def : InstRW<[ZnWriteMulX64Ld, ReadAfterLd], (instrs MULX64rm)>; + +//-- Control transfer instructions --// + +// J(E|R)CXZ. +def ZnWriteJCXZ : SchedWriteRes<[ZnALU03]>; +def : InstRW<[ZnWriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>; + +// INTO +def : InstRW<[WriteMicrocoded], (instrs INTO)>; + +// LOOP. +def ZnWriteLOOP : SchedWriteRes<[ZnALU03]>; +def : InstRW<[ZnWriteLOOP], (instrs LOOP)>; + +// LOOP(N)E, LOOP(N)Z +def ZnWriteLOOPE : SchedWriteRes<[ZnALU03]>; +def : InstRW<[ZnWriteLOOPE], (instrs LOOPE, LOOPNE)>; + +// CALL. +// r. +def ZnWriteCALLr : SchedWriteRes<[ZnAGU, ZnALU03]>; +def : InstRW<[ZnWriteCALLr], (instregex "CALL(16|32)r")>; + +def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>; + +// RET. +def ZnWriteRET : SchedWriteRes<[ZnALU03]> { + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)", + "IRET(16|32|64)")>; + +//-- Logic instructions --// + +// AND OR XOR. +// m,r/i. +def : InstRW<[WriteALULd], + (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)", + "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>; + +// Define ALU latency variants +def ZnWriteALULat2 : SchedWriteRes<[ZnALU]> { + let Latency = 2; +} +def ZnWriteALULat2Ld : SchedWriteRes<[ZnAGU, ZnALU]> { + let Latency = 6; +} + +// BT. +// m,i. +def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>; + +// BTR BTS BTC. +// r,r,i. +def ZnWriteBTRSC : SchedWriteRes<[ZnALU]> { + let Latency = 2; + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteBTRSC], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>; + +// m,r,i. +def ZnWriteBTRSCm : SchedWriteRes<[ZnAGU, ZnALU]> { + let Latency = 6; + let NumMicroOps = 2; +} +// m,r,i. +def : InstRW<[ZnWriteBTRSCm], (instregex "BT(R|S|C)(16|32|64)m(r|i8)")>; + +// BLSI BLSMSK BLSR. +// r,r. +def : InstRW<[ZnWriteALULat2], (instregex "BLS(I|MSK|R)(32|64)rr")>; +// r,m. +def : InstRW<[ZnWriteALULat2Ld], (instregex "BLS(I|MSK|R)(32|64)rm")>; + +// CLD STD. +def : InstRW<[WriteALU], (instrs STD, CLD)>; + +// PDEP PEXT. +// r,r,r. +def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>; +// r,r,m. +def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>; + +// RCR RCL. +// m,i. +def : InstRW<[WriteMicrocoded], (instregex "RC(R|L)(8|16|32|64)m(1|i|CL)")>; + +// SHR SHL SAR. +// m,i. +def : InstRW<[WriteShiftLd], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>; + +// SHRD SHLD. +// m,r +def : InstRW<[WriteShiftLd], (instregex "SH(R|L)D(16|32|64)mri8")>; + +// r,r,cl. +def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)rrCL")>; + +// m,r,cl. +def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>; + +//-- Misc instructions --// +// CMPXCHG. +def ZnWriteCMPXCHG : SchedWriteRes<[ZnAGU, ZnALU]> { + let Latency = 8; + let NumMicroOps = 5; +} +def : InstRW<[ZnWriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>; + +// CMPXCHG8B. +def ZnWriteCMPXCHG8B : SchedWriteRes<[ZnAGU, ZnALU]> { + let NumMicroOps = 18; +} +def : InstRW<[ZnWriteCMPXCHG8B], (instrs CMPXCHG8B)>; + +def : InstRW<[WriteMicrocoded], (instrs CMPXCHG16B)>; + +// LEAVE +def ZnWriteLEAVE : SchedWriteRes<[ZnALU, ZnAGU]> { + let Latency = 8; + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteLEAVE], (instregex "LEAVE")>; + +// PAUSE. +def : InstRW<[WriteMicrocoded], (instrs PAUSE)>; + +// RDTSC. +def : InstRW<[WriteMicrocoded], (instregex "RDTSC")>; + +// RDPMC. +def : InstRW<[WriteMicrocoded], (instrs RDPMC)>; + +// RDRAND. +def : InstRW<[WriteMicrocoded], (instregex "RDRAND(16|32|64)r")>; + +// XGETBV. +def : InstRW<[WriteMicrocoded], (instregex "XGETBV")>; + +//-- String instructions --// +// CMPS. +def : InstRW<[WriteMicrocoded], (instregex "CMPS(B|L|Q|W)")>; + +// LODSB/W. +def : InstRW<[WriteMicrocoded], (instregex "LODS(B|W)")>; + +// LODSD/Q. +def : InstRW<[WriteMicrocoded], (instregex "LODS(L|Q)")>; + +// MOVS. +def : InstRW<[WriteMicrocoded], (instregex "MOVS(B|L|Q|W)")>; + +// SCAS. +def : InstRW<[WriteMicrocoded], (instregex "SCAS(B|W|L|Q)")>; + +// STOS +def : InstRW<[WriteMicrocoded], (instregex "STOS(B|L|Q|W)")>; + +// XADD. +def : InstRW<[WriteMicrocoded], (instregex "XADD(8|16|32|64)rm")>; + +//=== Floating Point x87 Instructions ===// +//-- Move instructions --// + +def ZnWriteFLDr : SchedWriteRes<[ZnFPU13]> ; + +def ZnWriteSTr: SchedWriteRes<[ZnFPU23]> { + let Latency = 5; + let NumMicroOps = 2; +} + +// LD_F. +// r. +def : InstRW<[ZnWriteFLDr], (instregex "LD_Frr")>; + +// m. +def ZnWriteLD_F80m : SchedWriteRes<[ZnAGU, ZnFPU13]> { + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteLD_F80m], (instregex "LD_F80m")>; + +// FBLD. +def : InstRW<[WriteMicrocoded], (instregex "FBLDm")>; + +// FST(P). +// r. +def : InstRW<[ZnWriteSTr], (instregex "ST_(F|FP)rr")>; + +// m80. +def ZnWriteST_FP80m : SchedWriteRes<[ZnAGU, ZnFPU23]> { + let Latency = 5; +} +def : InstRW<[ZnWriteST_FP80m], (instregex "ST_FP80m")>; + +// FBSTP. +// m80. +def : InstRW<[WriteMicrocoded], (instregex "FBSTPm")>; + +def ZnWriteFXCH : SchedWriteRes<[ZnFPU]>; + +// FXCHG. +def : InstRW<[ZnWriteFXCH], (instrs XCH_F)>; + +// FILD. +def ZnWriteFILD : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 11; + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteFILD], (instregex "ILD_F(16|32|64)m")>; + +// FIST(P) FISTTP. +def ZnWriteFIST : SchedWriteRes<[ZnAGU, ZnFPU23]> { + let Latency = 12; +} +def : InstRW<[ZnWriteFIST], (instregex "IS(T|TT)_(F|FP)(16|32|64)m")>; + +def ZnWriteFPU13 : SchedWriteRes<[ZnAGU, ZnFPU13]> { + let Latency = 8; +} + +def ZnWriteFPU3 : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 11; +} + +// FLDZ. +def : SchedAlias; + +// FLD1. +def : SchedAlias; + +// FLDPI FLDL2E etc. +def : SchedAlias; + +// FNSTSW. +// AX. +def : InstRW<[WriteMicrocoded], (instrs FNSTSW16r)>; + +// m16. +def : InstRW<[WriteMicrocoded], (instrs FNSTSWm)>; + +// FLDCW. +def : InstRW<[WriteMicrocoded], (instrs FLDCW16m)>; + +// FNSTCW. +def : InstRW<[WriteMicrocoded], (instrs FNSTCW16m)>; + +// FINCSTP FDECSTP. +def : InstRW<[ZnWriteFPU3], (instrs FINCSTP, FDECSTP)>; + +// FFREE. +def : InstRW<[ZnWriteFPU3], (instregex "FFREE")>; + +// FNSAVE. +def : InstRW<[WriteMicrocoded], (instregex "FSAVEm")>; + +// FRSTOR. +def : InstRW<[WriteMicrocoded], (instregex "FRSTORm")>; + +//-- Arithmetic instructions --// + +def ZnWriteFPU3Lat1 : SchedWriteRes<[ZnFPU3]> ; + +def ZnWriteFPU0Lat1 : SchedWriteRes<[ZnFPU0]> ; + +def ZnWriteFPU0Lat1Ld : SchedWriteRes<[ZnAGU, ZnFPU0]> { + let Latency = 8; +} + +// FCHS. +def : InstRW<[ZnWriteFPU3Lat1], (instregex "CHS_F")>; + +// FCOM(P) FUCOM(P). +// r. +def : InstRW<[ZnWriteFPU0Lat1], (instregex "COM(P?)_FST0r", "UCOM_F(P?)r")>; +// m. +def : InstRW<[ZnWriteFPU0Lat1Ld], (instregex "FCOM(P?)(32|64)m")>; + +// FCOMPP FUCOMPP. +// r. +def : InstRW<[ZnWriteFPU0Lat1], (instrs FCOMPP, UCOM_FPPr)>; + +def ZnWriteFPU02 : SchedWriteRes<[ZnAGU, ZnFPU02]> +{ + let Latency = 9; +} + +// FCOMI(P) FUCOMI(P). +// m. +def : InstRW<[ZnWriteFPU02], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; + +def ZnWriteFPU03 : SchedWriteRes<[ZnAGU, ZnFPU03]> +{ + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,3]; +} + +// FICOM(P). +def : InstRW<[ZnWriteFPU03], (instregex "FICOM(P?)(16|32)m")>; + +// FTST. +def : InstRW<[ZnWriteFPU0Lat1], (instregex "TST_F")>; + +// FXAM. +def : InstRW<[ZnWriteFPU3Lat1], (instrs FXAM)>; + +// FPREM. +def : InstRW<[WriteMicrocoded], (instrs FPREM)>; + +// FPREM1. +def : InstRW<[WriteMicrocoded], (instrs FPREM1)>; + +// FRNDINT. +def : InstRW<[WriteMicrocoded], (instrs FRNDINT)>; + +// FSCALE. +def : InstRW<[WriteMicrocoded], (instrs FSCALE)>; + +// FXTRACT. +def : InstRW<[WriteMicrocoded], (instrs FXTRACT)>; + +// FNOP. +def : InstRW<[ZnWriteFPU0Lat1], (instrs FNOP)>; + +// WAIT. +def : InstRW<[ZnWriteFPU0Lat1], (instrs WAIT)>; + +// FNCLEX. +def : InstRW<[WriteMicrocoded], (instrs FNCLEX)>; + +// FNINIT. +def : InstRW<[WriteMicrocoded], (instrs FNINIT)>; + +//=== Integer MMX and XMM Instructions ===// + +// PACKSSWB/DW. +// mm <- mm. +def ZnWriteFPU12 : SchedWriteRes<[ZnFPU12]> ; +def ZnWriteFPU12Y : SchedWriteRes<[ZnFPU12]> { + let NumMicroOps = 2; +} +def ZnWriteFPU12m : SchedWriteRes<[ZnAGU, ZnFPU12]> ; +def ZnWriteFPU12Ym : SchedWriteRes<[ZnAGU, ZnFPU12]> { + let Latency = 8; + let NumMicroOps = 2; +} + +def : InstRW<[ZnWriteFPU12], (instrs MMX_PACKSSDWirr, + MMX_PACKSSWBirr, + MMX_PACKUSWBirr)>; +def : InstRW<[ZnWriteFPU12m], (instrs MMX_PACKSSDWirm, + MMX_PACKSSWBirm, + MMX_PACKUSWBirm)>; + +// VPMOVSX/ZX BW BD BQ WD WQ DQ. +// y <- x. +def : InstRW<[ZnWriteFPU12Y], (instregex "VPMOV(SX|ZX)(BW|BD|BQ|WD|WQ|DQ)Yrr")>; +def : InstRW<[ZnWriteFPU12Ym], (instregex "VPMOV(SX|ZX)(BW|BD|BQ|WD|WQ|DQ)Yrm")>; + +def ZnWriteFPU013 : SchedWriteRes<[ZnFPU013]> ; +def ZnWriteFPU013Y : SchedWriteRes<[ZnFPU013]> { + let Latency = 2; +} +def ZnWriteFPU013m : SchedWriteRes<[ZnAGU, ZnFPU013]> { + let Latency = 8; + let NumMicroOps = 2; +} +def ZnWriteFPU013Ld : SchedWriteRes<[ZnAGU, ZnFPU013]> { + let Latency = 8; + let NumMicroOps = 2; +} +def ZnWriteFPU013LdY : SchedWriteRes<[ZnAGU, ZnFPU013]> { + let Latency = 9; + let NumMicroOps = 2; +} + +// PBLENDW. +// x,x,i / v,v,v,i +def : InstRW<[ZnWriteFPU013], (instregex "(V?)PBLENDWrri")>; +// ymm +def : InstRW<[ZnWriteFPU013Y], (instrs VPBLENDWYrri)>; + +// x,m,i / v,v,m,i +def : InstRW<[ZnWriteFPU013Ld], (instregex "(V?)PBLENDWrmi")>; +// y,m,i +def : InstRW<[ZnWriteFPU013LdY], (instrs VPBLENDWYrmi)>; + +def ZnWriteFPU01 : SchedWriteRes<[ZnFPU01]> ; +def ZnWriteFPU01Y : SchedWriteRes<[ZnFPU01]> { + let NumMicroOps = 2; +} + +// VPBLENDD. +// v,v,v,i. +def : InstRW<[ZnWriteFPU01], (instrs VPBLENDDrri)>; +// ymm +def : InstRW<[ZnWriteFPU01Y], (instrs VPBLENDDYrri)>; + +// v,v,m,i +def ZnWriteFPU01Op2 : SchedWriteRes<[ZnAGU, ZnFPU01]> { + let NumMicroOps = 2; + let Latency = 8; + let ResourceCycles = [1, 2]; +} +def ZnWriteFPU01Op2Y : SchedWriteRes<[ZnAGU, ZnFPU01]> { + let NumMicroOps = 2; + let Latency = 9; + let ResourceCycles = [1, 3]; +} +def : InstRW<[ZnWriteFPU01Op2], (instrs VPBLENDDrmi)>; +def : InstRW<[ZnWriteFPU01Op2Y], (instrs VPBLENDDYrmi)>; + +// MASKMOVQ. +def : InstRW<[WriteMicrocoded], (instregex "MMX_MASKMOVQ(64)?")>; + +// MASKMOVDQU. +def : InstRW<[WriteMicrocoded], (instregex "(V?)MASKMOVDQU(64)?")>; + +// VPMASKMOVD. +// ymm +def : InstRW<[WriteMicrocoded], + (instregex "VPMASKMOVD(Y?)rm")>; +// m, v,v. +def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>; + +// VPBROADCAST B/W. +// x, m8/16. +def ZnWriteVPBROADCAST128Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1, 2]; +} +def : InstRW<[ZnWriteVPBROADCAST128Ld], + (instregex "VPBROADCAST(B|W)rm")>; + +// y, m8/16 +def ZnWriteVPBROADCAST256Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1, 2]; +} +def : InstRW<[ZnWriteVPBROADCAST256Ld], + (instregex "VPBROADCAST(B|W)Yrm")>; + +// VPGATHER. +def : InstRW<[WriteMicrocoded], (instregex "VPGATHER(Q|D)(Q|D)(Y?)rm")>; + +//-- Arithmetic instructions --// + +// HADD, HSUB PS/PD +// PHADD|PHSUB (S) W/D. +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; + +// PCMPGTQ. +def ZnWritePCMPGTQr : SchedWriteRes<[ZnFPU03]>; +def : InstRW<[ZnWritePCMPGTQr], (instregex "(V?)PCMPGTQ(Y?)rr")>; + +// x <- x,m. +def ZnWritePCMPGTQm : SchedWriteRes<[ZnAGU, ZnFPU03]> { + let Latency = 8; +} +// ymm. +def ZnWritePCMPGTQYm : SchedWriteRes<[ZnAGU, ZnFPU03]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,2]; +} +def : InstRW<[ZnWritePCMPGTQm], (instregex "(V?)PCMPGTQrm")>; +def : InstRW<[ZnWritePCMPGTQYm], (instrs VPCMPGTQYrm)>; + +//-- Logic instructions --// + +// PSLL,PSRL,PSRA W/D/Q. +// x,x / v,v,x. +def ZnWritePShift : SchedWriteRes<[ZnFPU2]> ; +def ZnWritePShiftY : SchedWriteRes<[ZnFPU2]> { + let Latency = 2; +} + +// PSLL,PSRL DQ. +def : InstRW<[ZnWritePShift], (instregex "(V?)PS(R|L)LDQri")>; +def : InstRW<[ZnWritePShiftY], (instregex "(V?)PS(R|L)LDQYri")>; + +//=== Floating Point XMM and YMM Instructions ===// +//-- Move instructions --// + +// VPERM2F128. +def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rr)>; +def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rm)>; + +def ZnWriteBROADCAST : SchedWriteRes<[ZnAGU, ZnFPU13]> { + let NumMicroOps = 2; + let Latency = 8; +} +// VBROADCASTF128. +def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128)>; + +// EXTRACTPS. +// r32,x,i. +def ZnWriteEXTRACTPSr : SchedWriteRes<[ZnFPU12, ZnFPU2]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1, 2]; +} +def : InstRW<[ZnWriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>; + +def ZnWriteEXTRACTPSm : SchedWriteRes<[ZnAGU,ZnFPU12, ZnFPU2]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [5, 1, 2]; +} +// m32,x,i. +def : InstRW<[ZnWriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>; + +// VEXTRACTF128. +// x,y,i. +def : InstRW<[ZnWriteFPU013], (instrs VEXTRACTF128rr)>; + +// m128,y,i. +def : InstRW<[ZnWriteFPU013m], (instrs VEXTRACTF128mr)>; + +def ZnWriteVINSERT128r: SchedWriteRes<[ZnFPU013]> { + let Latency = 2; + let ResourceCycles = [2]; +} +def ZnWriteVINSERT128Ld: SchedWriteRes<[ZnAGU,ZnFPU013]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1, 2]; +} +// VINSERTF128. +// y,y,x,i. +def : InstRW<[ZnWriteVINSERT128r], (instrs VINSERTF128rr)>; +def : InstRW<[ZnWriteVINSERT128Ld], (instrs VINSERTF128rm)>; + +// VGATHER. +def : InstRW<[WriteMicrocoded], (instregex "VGATHER(Q|D)(PD|PS)(Y?)rm")>; + +//-- Conversion instructions --// +def ZnWriteCVTPD2PSr: SchedWriteRes<[ZnFPU3]> { + let Latency = 4; +} +def ZnWriteCVTPD2PSYr: SchedWriteRes<[ZnFPU3]> { + let Latency = 5; +} + +// CVTPD2PS. +// x,x. +def : SchedAlias; +// y,y. +def : SchedAlias; +// z,z. +defm : X86WriteResUnsupported; + +def ZnWriteCVTPD2PSLd: SchedWriteRes<[ZnAGU,ZnFPU03]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,2]; +} +// x,m128. +def : SchedAlias; + +// x,m256. +def ZnWriteCVTPD2PSYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 11; +} +def : SchedAlias; +// z,m512 +defm : X86WriteResUnsupported; + +// CVTSD2SS. +// x,x. +// Same as WriteCVTPD2PSr +def : SchedAlias; + +// x,m64. +def : SchedAlias; + +// CVTPS2PD. +// x,x. +def ZnWriteCVTPS2PDr : SchedWriteRes<[ZnFPU3]> { + let Latency = 3; +} +def : SchedAlias; + +// x,m64. +// y,m128. +def ZnWriteCVTPS2PDLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 10; + let NumMicroOps = 2; +} +def : SchedAlias; +def : SchedAlias; +defm : X86WriteResUnsupported; + +// y,x. +def ZnWriteVCVTPS2PDY : SchedWriteRes<[ZnFPU3]> { + let Latency = 3; +} +def : SchedAlias; +defm : X86WriteResUnsupported; + +// CVTSS2SD. +// x,x. +def ZnWriteCVTSS2SDr : SchedWriteRes<[ZnFPU3]> { + let Latency = 4; +} +def : SchedAlias; + +// x,m32. +def ZnWriteCVTSS2SDLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1, 2]; +} +def : SchedAlias; + +def ZnWriteCVTDQ2PDr: SchedWriteRes<[ZnFPU12,ZnFPU3]> { + let Latency = 5; +} +// CVTDQ2PD. +// x,x. +def : InstRW<[ZnWriteCVTDQ2PDr], (instregex "(V)?CVTDQ2PDrr")>; + +// Same as xmm +// y,x. +def : InstRW<[ZnWriteCVTDQ2PDr], (instrs VCVTDQ2PDYrr)>; + +def ZnWriteCVTPD2DQr: SchedWriteRes<[ZnFPU12, ZnFPU3]> { + let Latency = 5; +} +// CVT(T)PD2DQ. +// x,x. +def : InstRW<[ZnWriteCVTDQ2PDr], (instregex "(V?)CVT(T?)PD2DQrr")>; + +def ZnWriteCVTPD2DQLd: SchedWriteRes<[ZnAGU,ZnFPU12,ZnFPU3]> { + let Latency = 12; + let NumMicroOps = 2; +} +// x,m128. +def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "(V?)CVT(T?)PD2DQrm")>; +// same as xmm handling +// x,y. +def : InstRW<[ZnWriteCVTPD2DQr], (instregex "VCVT(T?)PD2DQYrr")>; +// x,m256. +def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "VCVT(T?)PD2DQYrm")>; + +def ZnWriteCVTPS2PIr: SchedWriteRes<[ZnFPU3]> { + let Latency = 4; +} +// CVT(T)PS2PI. +// mm,x. +def : InstRW<[ZnWriteCVTPS2PIr], (instregex "MMX_CVT(T?)PS2PIirr")>; + +// CVTPI2PD. +// x,mm. +def : InstRW<[ZnWriteCVTPS2PDr], (instrs MMX_CVTPI2PDirr)>; + +// CVT(T)PD2PI. +// mm,x. +def : InstRW<[ZnWriteCVTPS2PIr], (instregex "MMX_CVT(T?)PD2PIirr")>; + +def ZnWriteCVSTSI2SSr: SchedWriteRes<[ZnFPU3]> { + let Latency = 5; +} + +// same as CVTPD2DQr +// CVT(T)SS2SI. +// r32,x. +def : InstRW<[ZnWriteCVTPD2DQr], (instregex "(V?)CVT(T?)SS2SI(64)?rr")>; +// same as CVTPD2DQm +// r32,m32. +def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "(V?)CVT(T?)SS2SI(64)?rm")>; + +def ZnWriteCVSTSI2SDr: SchedWriteRes<[ZnFPU013, ZnFPU3]> { + let Latency = 5; +} +// CVTSI2SD. +// x,r32/64. +def : InstRW<[ZnWriteCVSTSI2SDr], (instregex "(V?)CVTSI(64)?2SDrr")>; + + +def ZnWriteCVSTSI2SIr: SchedWriteRes<[ZnFPU3, ZnFPU2]> { + let Latency = 5; +} +def ZnWriteCVSTSI2SILd: SchedWriteRes<[ZnAGU, ZnFPU3, ZnFPU2]> { + let Latency = 12; +} +// CVTSD2SI. +// r32/64 +def : InstRW<[ZnWriteCVSTSI2SIr], (instregex "(V?)CVT(T?)SD2SI(64)?rr")>; +// r32,m32. +def : InstRW<[ZnWriteCVSTSI2SILd], (instregex "(V?)CVT(T?)SD2SI(64)?rm")>; + +// VCVTPS2PH. +// x,v,i. +def : SchedAlias; +def : SchedAlias; +defm : X86WriteResUnsupported; +// m,v,i. +def : SchedAlias; +def : SchedAlias; +defm : X86WriteResUnsupported; + +// VCVTPH2PS. +// v,x. +def : SchedAlias; +def : SchedAlias; +defm : X86WriteResUnsupported; +// v,m. +def : SchedAlias; +def : SchedAlias; +defm : X86WriteResUnsupported; + +//-- SSE4A instructions --// +// EXTRQ +def ZnWriteEXTRQ: SchedWriteRes<[ZnFPU12, ZnFPU2]> { + let Latency = 2; +} +def : InstRW<[ZnWriteEXTRQ], (instregex "EXTRQ")>; + +// INSERTQ +def ZnWriteINSERTQ: SchedWriteRes<[ZnFPU03,ZnFPU1]> { + let Latency = 4; +} +def : InstRW<[ZnWriteINSERTQ], (instregex "INSERTQ")>; + +//-- SHA instructions --// +// SHA256MSG2 +def : InstRW<[WriteMicrocoded], (instregex "SHA256MSG2(Y?)r(r|m)")>; + +// SHA1MSG1, SHA256MSG1 +// x,x. +def ZnWriteSHA1MSG1r : SchedWriteRes<[ZnFPU12]> { + let Latency = 2; + let ResourceCycles = [2]; +} +def : InstRW<[ZnWriteSHA1MSG1r], (instregex "SHA(1|256)MSG1rr")>; +// x,m. +def ZnWriteSHA1MSG1Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> { + let Latency = 9; + let ResourceCycles = [1,2]; +} +def : InstRW<[ZnWriteSHA1MSG1Ld], (instregex "SHA(1|256)MSG1rm")>; + +// SHA1MSG2 +// x,x. +def ZnWriteSHA1MSG2r : SchedWriteRes<[ZnFPU12]> ; +def : InstRW<[ZnWriteSHA1MSG2r], (instregex "SHA1MSG2rr")>; +// x,m. +def ZnWriteSHA1MSG2Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> { + let Latency = 8; +} +def : InstRW<[ZnWriteSHA1MSG2Ld], (instregex "SHA1MSG2rm")>; + +// SHA1NEXTE +// x,x. +def ZnWriteSHA1NEXTEr : SchedWriteRes<[ZnFPU1]> ; +def : InstRW<[ZnWriteSHA1NEXTEr], (instregex "SHA1NEXTErr")>; +// x,m. +def ZnWriteSHA1NEXTELd : SchedWriteRes<[ZnAGU, ZnFPU1]> { + let Latency = 8; +} +def : InstRW<[ZnWriteSHA1NEXTELd], (instregex "SHA1NEXTErm")>; + +// SHA1RNDS4 +// x,x. +def ZnWriteSHA1RNDS4r : SchedWriteRes<[ZnFPU1]> { + let Latency = 6; +} +def : InstRW<[ZnWriteSHA1RNDS4r], (instregex "SHA1RNDS4rr")>; +// x,m. +def ZnWriteSHA1RNDS4Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> { + let Latency = 13; +} +def : InstRW<[ZnWriteSHA1RNDS4Ld], (instregex "SHA1RNDS4rm")>; + +// SHA256RNDS2 +// x,x. +def ZnWriteSHA256RNDS2r : SchedWriteRes<[ZnFPU1]> { + let Latency = 4; +} +def : InstRW<[ZnWriteSHA256RNDS2r], (instregex "SHA256RNDS2rr")>; +// x,m. +def ZnWriteSHA256RNDS2Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> { + let Latency = 11; +} +def : InstRW<[ZnWriteSHA256RNDS2Ld], (instregex "SHA256RNDS2rm")>; + +//-- Arithmetic instructions --// + +// HADD, HSUB PS/PD +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; + +// VDIVPS. +// TODO - convert to ZnWriteResFpuPair +// y,y,y. +def ZnWriteVDIVPSYr : SchedWriteRes<[ZnFPU3]> { + let Latency = 12; + let ResourceCycles = [12]; +} +def : SchedAlias; + +// y,y,m256. +def ZnWriteVDIVPSYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 19; + let NumMicroOps = 2; + let ResourceCycles = [1, 19]; +} +def : SchedAlias; + +// VDIVPD. +// TODO - convert to ZnWriteResFpuPair +// y,y,y. +def ZnWriteVDIVPDY : SchedWriteRes<[ZnFPU3]> { + let Latency = 15; + let ResourceCycles = [15]; +} +def : SchedAlias; + +// y,y,m256. +def ZnWriteVDIVPDYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 22; + let NumMicroOps = 2; + let ResourceCycles = [1,22]; +} +def : SchedAlias; + +// DPPS. +// x,x,i / v,v,v,i. +def : SchedAlias; +def : SchedAlias; + +// x,m,i / v,v,m,i. +def : SchedAlias; +def : SchedAlias; + +// DPPD. +// x,x,i. +def : SchedAlias; + +// x,m,i. +def : SchedAlias; + +// RSQRTSS +// TODO - convert to ZnWriteResFpuPair +// x,x. +def ZnWriteRSQRTSSr : SchedWriteRes<[ZnFPU02]> { + let Latency = 5; +} +def : SchedAlias; + +// x,m128. +def ZnWriteRSQRTSSLd: SchedWriteRes<[ZnAGU, ZnFPU02]> { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,2]; // FIXME: Is this right? +} +def : SchedAlias; + +// RSQRTPS +// TODO - convert to ZnWriteResFpuPair +// y,y. +def ZnWriteRSQRTPSYr : SchedWriteRes<[ZnFPU01]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : SchedAlias; + +// y,m256. +def ZnWriteRSQRTPSYLd : SchedWriteRes<[ZnAGU, ZnFPU01]> { + let Latency = 12; + let NumMicroOps = 2; +} +def : SchedAlias; + +//-- Other instructions --// + +// VZEROUPPER. +def : InstRW<[WriteMicrocoded], (instrs VZEROUPPER)>; + +// VZEROALL. +def : InstRW<[WriteMicrocoded], (instrs VZEROALL)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/X86_reduce.td b/thirdparty/capstone/suite/synctools/tablegen/X86/X86_reduce.td new file mode 100644 index 0000000..cf2ce68 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/X86_reduce.td @@ -0,0 +1,459 @@ +//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This is a target description file for the Intel i386 architecture, referred +// to here as the "X86" architecture. +// +//===----------------------------------------------------------------------===// + +// Get the target-independent interfaces which we are implementing... +// +include "llvm/Target/Target.td" + +//===----------------------------------------------------------------------===// +// X86 Subtarget state +// + +def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", + "64-bit mode (x86_64)">; +def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true", + "32-bit mode (80386)">; +def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true", + "16-bit mode (i8086)">; + +//===----------------------------------------------------------------------===// +// X86 Subtarget features +//===----------------------------------------------------------------------===// + +def FeatureX87 : SubtargetFeature<"x87","HasX87", "true", + "Enable X87 float instructions">; + +def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true", + "Enable NOPL instruction">; + +def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", + "Enable conditional move instructions">; + +def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", + "Support POPCNT instruction">; + +def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true", + "Support fxsave/fxrestore instructions">; + +def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true", + "Support xsave instructions">; + +def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true", + "Support xsaveopt instructions">; + +def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true", + "Support xsavec instructions">; + +def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true", + "Support xsaves instructions">; + +def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", + "Enable SSE instructions", + // SSE codegen depends on cmovs, and all + // SSE1+ processors support them. + [FeatureCMOV]>; +def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", + "Enable SSE2 instructions", + [FeatureSSE1]>; +def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", + "Enable SSE3 instructions", + [FeatureSSE2]>; +def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", + "Enable SSSE3 instructions", + [FeatureSSE3]>; +def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41", + "Enable SSE 4.1 instructions", + [FeatureSSSE3]>; +def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42", + "Enable SSE 4.2 instructions", + [FeatureSSE41]>; +// The MMX subtarget feature is separate from the rest of the SSE features +// because it's important (for odd compatibility reasons) to be able to +// turn it off explicitly while allowing SSE+ to be on. +def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX", + "Enable MMX instructions">; +def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", + "Enable 3DNow! instructions", + [FeatureMMX]>; +def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", + "Enable 3DNow! Athlon instructions", + [Feature3DNow]>; +// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied +// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) +// without disabling 64-bit mode. +def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", + "Support 64-bit instructions", + [FeatureCMOV]>; +def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true", + "64-bit with cmpxchg16b", + [Feature64Bit]>; +def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true", + "SHLD instruction is slow">; +def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true", + "PMULLD instruction is slow">; +// FIXME: This should not apply to CPUs that do not have SSE. +def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", + "IsUAMem16Slow", "true", + "Slow unaligned 16-byte memory access">; +def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32", + "IsUAMem32Slow", "true", + "Slow unaligned 32-byte memory access">; +def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", + "Support SSE 4a instructions", + [FeatureSSE3]>; + +def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", + "Enable AVX instructions", + [FeatureSSE42]>; +def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", + "Enable AVX2 instructions", + [FeatureAVX]>; +def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", + "Enable three-operand fused multiple-add", + [FeatureAVX]>; +def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", + "Support 16-bit floating point conversion instructions", + [FeatureAVX]>; +def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F", + "Enable AVX-512 instructions", + [FeatureAVX2, FeatureFMA, FeatureF16C]>; +def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true", + "Enable AVX-512 Exponential and Reciprocal Instructions", + [FeatureAVX512]>; +def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true", + "Enable AVX-512 Conflict Detection Instructions", + [FeatureAVX512]>; +def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ", + "true", "Enable AVX-512 Population Count Instructions", + [FeatureAVX512]>; +def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true", + "Enable AVX-512 PreFetch Instructions", + [FeatureAVX512]>; +def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1", + "true", + "Prefetch with Intent to Write and T1 Hint">; +def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true", + "Enable AVX-512 Doubleword and Quadword Instructions", + [FeatureAVX512]>; +def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true", + "Enable AVX-512 Byte and Word Instructions", + [FeatureAVX512]>; +def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true", + "Enable AVX-512 Vector Length eXtensions", + [FeatureAVX512]>; +def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true", + "Enable AVX-512 Vector Byte Manipulation Instructions", + [FeatureBWI]>; +def FeatureVBMI2 : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true", + "Enable AVX-512 further Vector Byte Manipulation Instructions", + [FeatureBWI]>; +def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true", + "Enable AVX-512 Integer Fused Multiple-Add", + [FeatureAVX512]>; +def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true", + "Enable protection keys">; +def FeatureVNNI : SubtargetFeature<"avx512vnni", "HasVNNI", "true", + "Enable AVX-512 Vector Neural Network Instructions", + [FeatureAVX512]>; +def FeatureBITALG : SubtargetFeature<"avx512bitalg", "HasBITALG", "true", + "Enable AVX-512 Bit Algorithms", + [FeatureBWI]>; +def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", + "Enable packed carry-less multiplication instructions", + [FeatureSSE2]>; +def FeatureGFNI : SubtargetFeature<"gfni", "HasGFNI", "true", + "Enable Galois Field Arithmetic Instructions", + [FeatureSSE2]>; +def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true", + "Enable vpclmulqdq instructions", + [FeatureAVX, FeaturePCLMUL]>; +def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", + "Enable four-operand fused multiple-add", + [FeatureAVX, FeatureSSE4A]>; +def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", + "Enable XOP instructions", + [FeatureFMA4]>; +def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem", + "HasSSEUnalignedMem", "true", + "Allow unaligned memory operands with SSE instructions">; +def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", + "Enable AES instructions", + [FeatureSSE2]>; +def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true", + "Promote selected AES instructions to AVX512/AVX registers", + [FeatureAVX, FeatureAES]>; +def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", + "Enable TBM instructions">; +def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true", + "Enable LWP instructions">; +def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", + "Support MOVBE instruction">; +def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", + "Support RDRAND instruction">; +def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true", + "Support FS/GS Base instructions">; +def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true", + "Support LZCNT instruction">; +def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true", + "Support BMI instructions">; +def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true", + "Support BMI2 instructions">; +def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true", + "Support RTM instructions">; +def FeatureADX : SubtargetFeature<"adx", "HasADX", "true", + "Support ADX instructions">; +def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true", + "Enable SHA instructions", + [FeatureSSE2]>; +def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true", + "Support CET Shadow-Stack instructions">; +def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", + "Support PRFCHW instructions">; +def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", + "Support RDSEED instruction">; +def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true", + "Support LAHF and SAHF instructions">; +def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true", + "Enable MONITORX/MWAITX timer functionality">; +def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true", + "Enable Cache Line Zero">; +def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true", + "Enable Cache Demote">; +def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true", + "Support ptwrite instruction">; +def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true", + "Support MPX instructions">; +def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", + "Use LEA for adjusting the stack pointer">; +def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb", + "HasSlowDivide32", "true", + "Use 8-bit divide for positive values less than 256">; +def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl", + "HasSlowDivide64", "true", + "Use 32-bit divide for positive values less than 2^32">; +def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", + "PadShortFunctions", "true", + "Pad short functions">; +def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", + "Invalidate Process-Context Identifier">; +def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", + "Enable Software Guard Extensions">; +def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", + "Flush A Cache Line Optimized">; +def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true", + "Cache Line Write Back">; +def FeatureWBNOINVD : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true", + "Write Back No Invalidate">; +def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true", + "Support RDPID instructions">; +def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true", + "Wait and pause enhancements">; +// On some processors, instructions that implicitly take two memory operands are +// slow. In practice, this means that CALL, PUSH, and POP with memory operands +// should be avoided in favor of a MOV + register CALL/PUSH/POP. +def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops", + "SlowTwoMemOps", "true", + "Two memory operand instructions are slow">; +def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", + "LEA instruction needs inputs at AG stage">; +def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", + "LEA instruction with certain arguments is slow">; +def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true", + "LEA instruction with 3 ops or certain registers is slow">; +def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true", + "INC and DEC instructions are slower than ADD and SUB">; +def FeatureSoftFloat + : SubtargetFeature<"soft-float", "UseSoftFloat", "true", + "Use software floating point features.">; +def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt", + "HasPOPCNTFalseDeps", "true", + "POPCNT has a false dependency on dest register">; +def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt", + "HasLZCNTFalseDeps", "true", + "LZCNT/TZCNT have a false dependency on dest register">; +def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true", + "platform configuration instruction">; +// On recent X86 (port bound) processors, its preferable to combine to a single shuffle +// using a variable mask over multiple fixed shuffles. +def FeatureFastVariableShuffle + : SubtargetFeature<"fast-variable-shuffle", + "HasFastVariableShuffle", + "true", "Shuffles with variable masks are fast">; +// On some X86 processors, there is no performance hazard to writing only the +// lower parts of a YMM or ZMM register without clearing the upper part. +def FeatureFastPartialYMMorZMMWrite + : SubtargetFeature<"fast-partial-ymm-or-zmm-write", + "HasFastPartialYMMorZMMWrite", + "true", "Partial writes to YMM/ZMM registers are fast">; +// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency +// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if +// vector FSQRT has higher throughput than the corresponding NR code. +// The idea is that throughput bound code is likely to be vectorized, so for +// vectorized code we should care about the throughput of SQRT operations. +// But if the code is scalar that probably means that the code has some kind of +// dependency and we should care more about reducing the latency. +def FeatureFastScalarFSQRT + : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT", + "true", "Scalar SQRT is fast (disable Newton-Raphson)">; +def FeatureFastVectorFSQRT + : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT", + "true", "Vector SQRT is fast (disable Newton-Raphson)">; +// If lzcnt has equivalent latency/throughput to most simple integer ops, it can +// be used to replace test/set sequences. +def FeatureFastLZCNT + : SubtargetFeature< + "fast-lzcnt", "HasFastLZCNT", "true", + "LZCNT instructions are as fast as most simple integer ops">; +// If the target can efficiently decode NOPs upto 11-bytes in length. +def FeatureFast11ByteNOP + : SubtargetFeature< + "fast-11bytenop", "HasFast11ByteNOP", "true", + "Target can quickly decode up to 11 byte NOPs">; +// If the target can efficiently decode NOPs upto 15-bytes in length. +def FeatureFast15ByteNOP + : SubtargetFeature< + "fast-15bytenop", "HasFast15ByteNOP", "true", + "Target can quickly decode up to 15 byte NOPs">; +// Sandy Bridge and newer processors can use SHLD with the same source on both +// inputs to implement rotate to avoid the partial flag update of the normal +// rotate instructions. +def FeatureFastSHLDRotate + : SubtargetFeature< + "fast-shld-rotate", "HasFastSHLDRotate", "true", + "SHLD can be used as a faster rotate">; + +// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka +// "string operations"). See "REP String Enhancement" in the Intel Software +// Development Manual. This feature essentially means that REP MOVSB will copy +// using the largest available size instead of copying bytes one by one, making +// it at least as fast as REPMOVS{W,D,Q}. +def FeatureERMSB + : SubtargetFeature< + "ermsb", "HasERMSB", "true", + "REP MOVS/STOS are fast">; + +// Sandy Bridge and newer processors have many instructions that can be +// fused with conditional branches and pass through the CPU as a single +// operation. +def FeatureMacroFusion + : SubtargetFeature<"macrofusion", "HasMacroFusion", "true", + "Various instructions can be fused with conditional branches">; + +// Gather is available since Haswell (AVX2 set). So technically, we can +// generate Gathers on all AVX2 processors. But the overhead on HSW is high. +// Skylake Client processor has faster Gathers than HSW and performance is +// similar to Skylake Server (AVX-512). +def FeatureHasFastGather + : SubtargetFeature<"fast-gather", "HasFastGather", "true", + "Indicates if gather is reasonably fast.">; + +def FeaturePrefer256Bit + : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true", + "Prefer 256-bit AVX instructions">; + +// Enable mitigation of some aspects of speculative execution related +// vulnerabilities by removing speculatable indirect branches. This disables +// jump-table formation, rewrites explicit `indirectbr` instructions into +// `switch` instructions, and uses a special construct called a "retpoline" to +// prevent speculation of the remaining indirect branches (indirect calls and +// tail calls). +def FeatureRetpoline + : SubtargetFeature<"retpoline", "UseRetpoline", "true", + "Remove speculation of indirect branches from the " + "generated code, either by avoiding them entirely or " + "lowering them with a speculation blocking construct.">; + +// Rely on external thunks for the emitted retpoline calls. This allows users +// to provide their own custom thunk definitions in highly specialized +// environments such as a kernel that does boot-time hot patching. +def FeatureRetpolineExternalThunk + : SubtargetFeature< + "retpoline-external-thunk", "UseRetpolineExternalThunk", "true", + "Enable retpoline, but with an externally provided thunk.", + [FeatureRetpoline]>; + +// Direct Move instructions. +def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true", + "Support movdiri instruction">; +def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true", + "Support movdir64b instruction">; + +//===----------------------------------------------------------------------===// +// Register File Description +//===----------------------------------------------------------------------===// + +include "X86RegisterInfo.td" +include "X86RegisterBanks.td" + +//===----------------------------------------------------------------------===// +// Instruction Descriptions +//===----------------------------------------------------------------------===// + +include "X86Schedule.td" +include "X86InstrInfo_reduce.td" + +def X86InstrInfo : InstrInfo; + +//===----------------------------------------------------------------------===// +// Assembly Parser +//===----------------------------------------------------------------------===// + +def ATTAsmParserVariant : AsmParserVariant { + int Variant = 0; + + // Variant name. + string Name = "att"; + + // Discard comments in assembly strings. + string CommentDelimiter = "#"; + + // Recognize hard coded registers. + string RegisterPrefix = "%"; +} + +def IntelAsmParserVariant : AsmParserVariant { + int Variant = 1; + + // Variant name. + string Name = "intel"; + + // Discard comments in assembly strings. + string CommentDelimiter = ";"; + + // Recognize hard coded registers. + string RegisterPrefix = ""; +} + +//===----------------------------------------------------------------------===// +// Assembly Printers +//===----------------------------------------------------------------------===// + +// The X86 target supports two different syntaxes for emitting machine code. +// This is controlled by the -x86-asm-syntax={att|intel} +def ATTAsmWriter : AsmWriter { + string AsmWriterClassName = "ATTInstPrinter"; + int Variant = 0; +} +def IntelAsmWriter : AsmWriter { + string AsmWriterClassName = "IntelInstPrinter"; + int Variant = 1; +} + +def X86 : Target { + // Information about the instructions... + let InstructionSet = X86InstrInfo; + let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant]; + let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; + let AllowRegisterRenaming = 1; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86.td new file mode 100644 index 0000000..63c2dc4 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86.td @@ -0,0 +1,1203 @@ +//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This is a target description file for the Intel i386 architecture, referred +// to here as the "X86" architecture. +// +//===----------------------------------------------------------------------===// + +// Get the target-independent interfaces which we are implementing... +// +include "llvm/Target/Target.td" + +//===----------------------------------------------------------------------===// +// X86 Subtarget state +// + +def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", + "64-bit mode (x86_64)">; +def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true", + "32-bit mode (80386)">; +def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true", + "16-bit mode (i8086)">; + +//===----------------------------------------------------------------------===// +// X86 Subtarget features +//===----------------------------------------------------------------------===// + +def FeatureX87 : SubtargetFeature<"x87","HasX87", "true", + "Enable X87 float instructions">; + +def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true", + "Enable NOPL instruction">; + +def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", + "Enable conditional move instructions">; + +def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", + "Support POPCNT instruction">; + +def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true", + "Support fxsave/fxrestore instructions">; + +def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true", + "Support xsave instructions">; + +def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true", + "Support xsaveopt instructions">; + +def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true", + "Support xsavec instructions">; + +def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true", + "Support xsaves instructions">; + +def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", + "Enable SSE instructions", + // SSE codegen depends on cmovs, and all + // SSE1+ processors support them. + [FeatureCMOV]>; +def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", + "Enable SSE2 instructions", + [FeatureSSE1]>; +def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", + "Enable SSE3 instructions", + [FeatureSSE2]>; +def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", + "Enable SSSE3 instructions", + [FeatureSSE3]>; +def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41", + "Enable SSE 4.1 instructions", + [FeatureSSSE3]>; +def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42", + "Enable SSE 4.2 instructions", + [FeatureSSE41]>; +// The MMX subtarget feature is separate from the rest of the SSE features +// because it's important (for odd compatibility reasons) to be able to +// turn it off explicitly while allowing SSE+ to be on. +def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX", + "Enable MMX instructions">; +def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", + "Enable 3DNow! instructions", + [FeatureMMX]>; +def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", + "Enable 3DNow! Athlon instructions", + [Feature3DNow]>; +// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied +// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) +// without disabling 64-bit mode. +def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", + "Support 64-bit instructions", + [FeatureCMOV]>; +def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true", + "64-bit with cmpxchg16b", + [Feature64Bit]>; +def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true", + "SHLD instruction is slow">; +def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true", + "PMULLD instruction is slow">; +// FIXME: This should not apply to CPUs that do not have SSE. +def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", + "IsUAMem16Slow", "true", + "Slow unaligned 16-byte memory access">; +def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32", + "IsUAMem32Slow", "true", + "Slow unaligned 32-byte memory access">; +def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", + "Support SSE 4a instructions", + [FeatureSSE3]>; + +def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", + "Enable AVX instructions", + [FeatureSSE42]>; +def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", + "Enable AVX2 instructions", + [FeatureAVX]>; +def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", + "Enable three-operand fused multiple-add", + [FeatureAVX]>; +def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", + "Support 16-bit floating point conversion instructions", + [FeatureAVX]>; +def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F", + "Enable AVX-512 instructions", + [FeatureAVX2, FeatureFMA, FeatureF16C]>; +def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true", + "Enable AVX-512 Exponential and Reciprocal Instructions", + [FeatureAVX512]>; +def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true", + "Enable AVX-512 Conflict Detection Instructions", + [FeatureAVX512]>; +def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ", + "true", "Enable AVX-512 Population Count Instructions", + [FeatureAVX512]>; +def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true", + "Enable AVX-512 PreFetch Instructions", + [FeatureAVX512]>; +def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1", + "true", + "Prefetch with Intent to Write and T1 Hint">; +def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true", + "Enable AVX-512 Doubleword and Quadword Instructions", + [FeatureAVX512]>; +def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true", + "Enable AVX-512 Byte and Word Instructions", + [FeatureAVX512]>; +def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true", + "Enable AVX-512 Vector Length eXtensions", + [FeatureAVX512]>; +def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true", + "Enable AVX-512 Vector Byte Manipulation Instructions", + [FeatureBWI]>; +def FeatureVBMI2 : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true", + "Enable AVX-512 further Vector Byte Manipulation Instructions", + [FeatureBWI]>; +def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true", + "Enable AVX-512 Integer Fused Multiple-Add", + [FeatureAVX512]>; +def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true", + "Enable protection keys">; +def FeatureVNNI : SubtargetFeature<"avx512vnni", "HasVNNI", "true", + "Enable AVX-512 Vector Neural Network Instructions", + [FeatureAVX512]>; +def FeatureBITALG : SubtargetFeature<"avx512bitalg", "HasBITALG", "true", + "Enable AVX-512 Bit Algorithms", + [FeatureBWI]>; +def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", + "Enable packed carry-less multiplication instructions", + [FeatureSSE2]>; +def FeatureGFNI : SubtargetFeature<"gfni", "HasGFNI", "true", + "Enable Galois Field Arithmetic Instructions", + [FeatureSSE2]>; +def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true", + "Enable vpclmulqdq instructions", + [FeatureAVX, FeaturePCLMUL]>; +def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", + "Enable four-operand fused multiple-add", + [FeatureAVX, FeatureSSE4A]>; +def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", + "Enable XOP instructions", + [FeatureFMA4]>; +def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem", + "HasSSEUnalignedMem", "true", + "Allow unaligned memory operands with SSE instructions">; +def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", + "Enable AES instructions", + [FeatureSSE2]>; +def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true", + "Promote selected AES instructions to AVX512/AVX registers", + [FeatureAVX, FeatureAES]>; +def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", + "Enable TBM instructions">; +def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true", + "Enable LWP instructions">; +def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", + "Support MOVBE instruction">; +def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", + "Support RDRAND instruction">; +def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true", + "Support FS/GS Base instructions">; +def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true", + "Support LZCNT instruction">; +def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true", + "Support BMI instructions">; +def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true", + "Support BMI2 instructions">; +def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true", + "Support RTM instructions">; +def FeatureADX : SubtargetFeature<"adx", "HasADX", "true", + "Support ADX instructions">; +def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true", + "Enable SHA instructions", + [FeatureSSE2]>; +def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true", + "Support CET Shadow-Stack instructions">; +def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", + "Support PRFCHW instructions">; +def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", + "Support RDSEED instruction">; +def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true", + "Support LAHF and SAHF instructions">; +def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true", + "Enable MONITORX/MWAITX timer functionality">; +def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true", + "Enable Cache Line Zero">; +def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true", + "Enable Cache Demote">; +def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true", + "Support ptwrite instruction">; +def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true", + "Support MPX instructions">; +def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", + "Use LEA for adjusting the stack pointer">; +def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb", + "HasSlowDivide32", "true", + "Use 8-bit divide for positive values less than 256">; +def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl", + "HasSlowDivide64", "true", + "Use 32-bit divide for positive values less than 2^32">; +def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", + "PadShortFunctions", "true", + "Pad short functions">; +def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", + "Invalidate Process-Context Identifier">; +def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", + "Enable Software Guard Extensions">; +def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", + "Flush A Cache Line Optimized">; +def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true", + "Cache Line Write Back">; +def FeatureWBNOINVD : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true", + "Write Back No Invalidate">; +def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true", + "Support RDPID instructions">; +def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true", + "Wait and pause enhancements">; +// On some processors, instructions that implicitly take two memory operands are +// slow. In practice, this means that CALL, PUSH, and POP with memory operands +// should be avoided in favor of a MOV + register CALL/PUSH/POP. +def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops", + "SlowTwoMemOps", "true", + "Two memory operand instructions are slow">; +def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", + "LEA instruction needs inputs at AG stage">; +def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", + "LEA instruction with certain arguments is slow">; +def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true", + "LEA instruction with 3 ops or certain registers is slow">; +def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true", + "INC and DEC instructions are slower than ADD and SUB">; +def FeatureSoftFloat + : SubtargetFeature<"soft-float", "UseSoftFloat", "true", + "Use software floating point features.">; +def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt", + "HasPOPCNTFalseDeps", "true", + "POPCNT has a false dependency on dest register">; +def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt", + "HasLZCNTFalseDeps", "true", + "LZCNT/TZCNT have a false dependency on dest register">; +def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true", + "platform configuration instruction">; +// On recent X86 (port bound) processors, its preferable to combine to a single shuffle +// using a variable mask over multiple fixed shuffles. +def FeatureFastVariableShuffle + : SubtargetFeature<"fast-variable-shuffle", + "HasFastVariableShuffle", + "true", "Shuffles with variable masks are fast">; +// On some X86 processors, there is no performance hazard to writing only the +// lower parts of a YMM or ZMM register without clearing the upper part. +def FeatureFastPartialYMMorZMMWrite + : SubtargetFeature<"fast-partial-ymm-or-zmm-write", + "HasFastPartialYMMorZMMWrite", + "true", "Partial writes to YMM/ZMM registers are fast">; +// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency +// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if +// vector FSQRT has higher throughput than the corresponding NR code. +// The idea is that throughput bound code is likely to be vectorized, so for +// vectorized code we should care about the throughput of SQRT operations. +// But if the code is scalar that probably means that the code has some kind of +// dependency and we should care more about reducing the latency. +def FeatureFastScalarFSQRT + : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT", + "true", "Scalar SQRT is fast (disable Newton-Raphson)">; +def FeatureFastVectorFSQRT + : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT", + "true", "Vector SQRT is fast (disable Newton-Raphson)">; +// If lzcnt has equivalent latency/throughput to most simple integer ops, it can +// be used to replace test/set sequences. +def FeatureFastLZCNT + : SubtargetFeature< + "fast-lzcnt", "HasFastLZCNT", "true", + "LZCNT instructions are as fast as most simple integer ops">; +// If the target can efficiently decode NOPs upto 11-bytes in length. +def FeatureFast11ByteNOP + : SubtargetFeature< + "fast-11bytenop", "HasFast11ByteNOP", "true", + "Target can quickly decode up to 11 byte NOPs">; +// If the target can efficiently decode NOPs upto 15-bytes in length. +def FeatureFast15ByteNOP + : SubtargetFeature< + "fast-15bytenop", "HasFast15ByteNOP", "true", + "Target can quickly decode up to 15 byte NOPs">; +// Sandy Bridge and newer processors can use SHLD with the same source on both +// inputs to implement rotate to avoid the partial flag update of the normal +// rotate instructions. +def FeatureFastSHLDRotate + : SubtargetFeature< + "fast-shld-rotate", "HasFastSHLDRotate", "true", + "SHLD can be used as a faster rotate">; + +// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka +// "string operations"). See "REP String Enhancement" in the Intel Software +// Development Manual. This feature essentially means that REP MOVSB will copy +// using the largest available size instead of copying bytes one by one, making +// it at least as fast as REPMOVS{W,D,Q}. +def FeatureERMSB + : SubtargetFeature< + "ermsb", "HasERMSB", "true", + "REP MOVS/STOS are fast">; + +// Sandy Bridge and newer processors have many instructions that can be +// fused with conditional branches and pass through the CPU as a single +// operation. +def FeatureMacroFusion + : SubtargetFeature<"macrofusion", "HasMacroFusion", "true", + "Various instructions can be fused with conditional branches">; + +// Gather is available since Haswell (AVX2 set). So technically, we can +// generate Gathers on all AVX2 processors. But the overhead on HSW is high. +// Skylake Client processor has faster Gathers than HSW and performance is +// similar to Skylake Server (AVX-512). +def FeatureHasFastGather + : SubtargetFeature<"fast-gather", "HasFastGather", "true", + "Indicates if gather is reasonably fast.">; + +def FeaturePrefer256Bit + : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true", + "Prefer 256-bit AVX instructions">; + +// Enable mitigation of some aspects of speculative execution related +// vulnerabilities by removing speculatable indirect branches. This disables +// jump-table formation, rewrites explicit `indirectbr` instructions into +// `switch` instructions, and uses a special construct called a "retpoline" to +// prevent speculation of the remaining indirect branches (indirect calls and +// tail calls). +def FeatureRetpoline + : SubtargetFeature<"retpoline", "UseRetpoline", "true", + "Remove speculation of indirect branches from the " + "generated code, either by avoiding them entirely or " + "lowering them with a speculation blocking construct.">; + +// Rely on external thunks for the emitted retpoline calls. This allows users +// to provide their own custom thunk definitions in highly specialized +// environments such as a kernel that does boot-time hot patching. +def FeatureRetpolineExternalThunk + : SubtargetFeature< + "retpoline-external-thunk", "UseRetpolineExternalThunk", "true", + "Enable retpoline, but with an externally provided thunk.", + [FeatureRetpoline]>; + +// Direct Move instructions. +def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true", + "Support movdiri instruction">; +def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true", + "Support movdir64b instruction">; + +//===----------------------------------------------------------------------===// +// Register File Description +//===----------------------------------------------------------------------===// + +include "X86RegisterInfo.td" +include "X86RegisterBanks.td" + +//===----------------------------------------------------------------------===// +// Instruction Descriptions +//===----------------------------------------------------------------------===// + +include "X86Schedule.td" +include "X86InstrInfo.td" +include "X86SchedPredicates.td" + +def X86InstrInfo : InstrInfo; + +//===----------------------------------------------------------------------===// +// X86 processors supported. +//===----------------------------------------------------------------------===// + +include "X86ScheduleAtom.td" +include "X86SchedSandyBridge.td" +include "X86SchedHaswell.td" +include "X86SchedBroadwell.td" +include "X86ScheduleSLM.td" +include "X86ScheduleZnver1.td" +include "X86ScheduleBtVer2.td" +include "X86SchedSkylakeClient.td" +include "X86SchedSkylakeServer.td" + +def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom", + "Intel Atom processors">; +def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM", + "Intel Silvermont processors">; +def ProcIntelGLM : SubtargetFeature<"glm", "X86ProcFamily", "IntelGLM", + "Intel Goldmont processors">; +def ProcIntelGLP : SubtargetFeature<"glp", "X86ProcFamily", "IntelGLP", + "Intel Goldmont Plus processors">; +def ProcIntelTRM : SubtargetFeature<"tremont", "X86ProcFamily", "IntelTRM", + "Intel Tremont processors">; +def ProcIntelHSW : SubtargetFeature<"haswell", "X86ProcFamily", + "IntelHaswell", "Intel Haswell processors">; +def ProcIntelBDW : SubtargetFeature<"broadwell", "X86ProcFamily", + "IntelBroadwell", "Intel Broadwell processors">; +def ProcIntelSKL : SubtargetFeature<"skylake", "X86ProcFamily", + "IntelSkylake", "Intel Skylake processors">; +def ProcIntelKNL : SubtargetFeature<"knl", "X86ProcFamily", + "IntelKNL", "Intel Knights Landing processors">; +def ProcIntelSKX : SubtargetFeature<"skx", "X86ProcFamily", + "IntelSKX", "Intel Skylake Server processors">; +def ProcIntelCNL : SubtargetFeature<"cannonlake", "X86ProcFamily", + "IntelCannonlake", "Intel Cannonlake processors">; +def ProcIntelICL : SubtargetFeature<"icelake-client", "X86ProcFamily", + "IntelIcelakeClient", "Intel Icelake processors">; +def ProcIntelICX : SubtargetFeature<"icelake-server", "X86ProcFamily", + "IntelIcelakeServer", "Intel Icelake Server processors">; + +class Proc Features> + : ProcessorModel; + +def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>; +def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; + +def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>; +def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV, + FeatureNOPL]>; + +def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureCMOV, FeatureFXSR, FeatureNOPL]>; + +foreach P = ["pentium3", "pentium3m"] in { + def : Proc; +} + +// Enable the PostRAScheduler for SSE2 and SSE3 class cpus. +// The intent is to enable it for pentium4 which is the current default +// processor in a vanilla 32-bit clang compilation when no specific +// architecture is specified. This generally gives a nice performance +// increase on silvermont, with largely neutral behavior on other +// contemporary large core processors. +// pentium-m, pentium4m, prescott and nocona are included as a preventative +// measure to avoid performance surprises, in case clang's default cpu +// changes slightly. + +def : ProcessorModel<"pentium-m", GenericPostRAModel, + [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureSSE2, FeatureFXSR, FeatureNOPL]>; + +foreach P = ["pentium4", "pentium4m"] in { + def : ProcessorModel; +} + +// Intel Quark. +def : Proc<"lakemont", []>; + +// Intel Core Duo. +def : ProcessorModel<"yonah", SandyBridgeModel, + [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, + FeatureFXSR, FeatureNOPL]>; + +// NetBurst. +def : ProcessorModel<"prescott", GenericPostRAModel, + [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, + FeatureFXSR, FeatureNOPL]>; +def : ProcessorModel<"nocona", GenericPostRAModel, [ + FeatureX87, + FeatureSlowUAMem16, + FeatureMMX, + FeatureSSE3, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B +]>; + +// Intel Core 2 Solo/Duo. +def : ProcessorModel<"core2", SandyBridgeModel, [ + FeatureX87, + FeatureSlowUAMem16, + FeatureMMX, + FeatureSSSE3, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B, + FeatureLAHFSAHF, + FeatureMacroFusion +]>; +def : ProcessorModel<"penryn", SandyBridgeModel, [ + FeatureX87, + FeatureSlowUAMem16, + FeatureMMX, + FeatureSSE41, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B, + FeatureLAHFSAHF, + FeatureMacroFusion +]>; + +// Atom CPUs. +class BonnellProc : ProcessorModel; +def : BonnellProc<"bonnell">; +def : BonnellProc<"atom">; // Pin the generic name to the baseline. + +class SilvermontProc : ProcessorModel; +def : SilvermontProc<"silvermont">; +def : SilvermontProc<"slm">; // Legacy alias. + +class ProcessorFeatures Inherited, + list NewFeatures> { + list Value = !listconcat(Inherited, NewFeatures); +} + +class ProcModel ProcFeatures, + list OtherFeatures> : + ProcessorModel; + +def GLMFeatures : ProcessorFeatures<[], [ + FeatureX87, + FeatureMMX, + FeatureSSE42, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B, + FeatureMOVBE, + FeaturePOPCNT, + FeaturePCLMUL, + FeatureAES, + FeaturePRFCHW, + FeatureSlowTwoMemOps, + FeatureSlowLEA, + FeatureSlowIncDec, + FeatureLAHFSAHF, + FeatureMPX, + FeatureSHA, + FeatureRDRAND, + FeatureRDSEED, + FeatureXSAVE, + FeatureXSAVEOPT, + FeatureXSAVEC, + FeatureXSAVES, + FeatureCLFLUSHOPT, + FeatureFSGSBase +]>; + +class GoldmontProc : ProcModel; +def : GoldmontProc<"goldmont">; + +def GLPFeatures : ProcessorFeatures; + +class GoldmontPlusProc : ProcModel; +def : GoldmontPlusProc<"goldmont-plus">; + +class TremontProc : ProcModel; +def : TremontProc<"tremont">; + +// "Arrandale" along with corei3 and corei5 +class NehalemProc : ProcessorModel; +def : NehalemProc<"nehalem">; +def : NehalemProc<"corei7">; + +// Westmere is a similar machine to nehalem with some additional features. +// Westmere is the corei3/i5/i7 path from nehalem to sandybridge +class WestmereProc : ProcessorModel; +def : WestmereProc<"westmere">; + +// SSE is not listed here since llvm treats AVX as a reimplementation of SSE, +// rather than a superset. +def SNBFeatures : ProcessorFeatures<[], [ + FeatureX87, + FeatureMMX, + FeatureAVX, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B, + FeaturePOPCNT, + FeatureAES, + FeatureSlowDivide64, + FeaturePCLMUL, + FeatureXSAVE, + FeatureXSAVEOPT, + FeatureLAHFSAHF, + FeatureSlow3OpsLEA, + FeatureFastScalarFSQRT, + FeatureFastSHLDRotate, + FeatureSlowIncDec, + FeatureMacroFusion +]>; + +class SandyBridgeProc : ProcModel; +def : SandyBridgeProc<"sandybridge">; +def : SandyBridgeProc<"corei7-avx">; // Legacy alias. + +def IVBFeatures : ProcessorFeatures; + +class IvyBridgeProc : ProcModel; +def : IvyBridgeProc<"ivybridge">; +def : IvyBridgeProc<"core-avx-i">; // Legacy alias. + +def HSWFeatures : ProcessorFeatures; + +class HaswellProc : ProcModel; +def : HaswellProc<"haswell">; +def : HaswellProc<"core-avx2">; // Legacy alias. + +def BDWFeatures : ProcessorFeatures; +class BroadwellProc : ProcModel; +def : BroadwellProc<"broadwell">; + +def SKLFeatures : ProcessorFeatures; + +class SkylakeClientProc : ProcModel; +def : SkylakeClientProc<"skylake">; + +def KNLFeatures : ProcessorFeatures; + +// FIXME: define KNL model +class KnightsLandingProc : ProcModel; +def : KnightsLandingProc<"knl">; + +class KnightsMillProc : ProcModel; +def : KnightsMillProc<"knm">; // TODO Add AVX5124FMAPS/AVX5124VNNIW features + +def SKXFeatures : ProcessorFeatures; + +class SkylakeServerProc : ProcModel; +def : SkylakeServerProc<"skylake-avx512">; +def : SkylakeServerProc<"skx">; // Legacy alias. + +def CNLFeatures : ProcessorFeatures; + +class CannonlakeProc : ProcModel; +def : CannonlakeProc<"cannonlake">; + +def ICLFeatures : ProcessorFeatures; + +class IcelakeClientProc : ProcModel; +def : IcelakeClientProc<"icelake-client">; + +class IcelakeServerProc : ProcModel; +def : IcelakeServerProc<"icelake-server">; + +// AMD CPUs. + +def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; +def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; +def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; + +foreach P = ["athlon", "athlon-tbird"] in { + def : Proc; +} + +foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in { + def : Proc; +} + +foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in { + def : Proc; +} + +foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in { + def : Proc; +} + +foreach P = ["amdfam10", "barcelona"] in { + def : Proc; +} + +// Bobcat +def : Proc<"btver1", [ + FeatureX87, + FeatureMMX, + FeatureSSSE3, + FeatureSSE4A, + FeatureFXSR, + FeatureNOPL, + FeatureCMPXCHG16B, + FeaturePRFCHW, + FeatureLZCNT, + FeaturePOPCNT, + FeatureSlowSHLD, + FeatureLAHFSAHF, + FeatureFast15ByteNOP +]>; + +// Jaguar +def : ProcessorModel<"btver2", BtVer2Model, [ + FeatureX87, + FeatureMMX, + FeatureAVX, + FeatureFXSR, + FeatureNOPL, + FeatureSSE4A, + FeatureCMPXCHG16B, + FeaturePRFCHW, + FeatureAES, + FeaturePCLMUL, + FeatureBMI, + FeatureF16C, + FeatureMOVBE, + FeatureLZCNT, + FeatureFastLZCNT, + FeaturePOPCNT, + FeatureXSAVE, + FeatureXSAVEOPT, + FeatureSlowSHLD, + FeatureLAHFSAHF, + FeatureFast15ByteNOP, + FeatureFastPartialYMMorZMMWrite +]>; + +// Bulldozer +def : Proc<"bdver1", [ + FeatureX87, + FeatureXOP, + FeatureFMA4, + FeatureCMPXCHG16B, + FeatureAES, + FeaturePRFCHW, + FeaturePCLMUL, + FeatureMMX, + FeatureAVX, + FeatureFXSR, + FeatureNOPL, + FeatureSSE4A, + FeatureLZCNT, + FeaturePOPCNT, + FeatureXSAVE, + FeatureLWP, + FeatureSlowSHLD, + FeatureLAHFSAHF, + FeatureFast11ByteNOP, + FeatureMacroFusion +]>; +// Piledriver +def : Proc<"bdver2", [ + FeatureX87, + FeatureXOP, + FeatureFMA4, + FeatureCMPXCHG16B, + FeatureAES, + FeaturePRFCHW, + FeaturePCLMUL, + FeatureMMX, + FeatureAVX, + FeatureFXSR, + FeatureNOPL, + FeatureSSE4A, + FeatureF16C, + FeatureLZCNT, + FeaturePOPCNT, + FeatureXSAVE, + FeatureBMI, + FeatureTBM, + FeatureLWP, + FeatureFMA, + FeatureSlowSHLD, + FeatureLAHFSAHF, + FeatureFast11ByteNOP, + FeatureMacroFusion +]>; + +// Steamroller +def : Proc<"bdver3", [ + FeatureX87, + FeatureXOP, + FeatureFMA4, + FeatureCMPXCHG16B, + FeatureAES, + FeaturePRFCHW, + FeaturePCLMUL, + FeatureMMX, + FeatureAVX, + FeatureFXSR, + FeatureNOPL, + FeatureSSE4A, + FeatureF16C, + FeatureLZCNT, + FeaturePOPCNT, + FeatureXSAVE, + FeatureBMI, + FeatureTBM, + FeatureLWP, + FeatureFMA, + FeatureXSAVEOPT, + FeatureSlowSHLD, + FeatureFSGSBase, + FeatureLAHFSAHF, + FeatureFast11ByteNOP, + FeatureMacroFusion +]>; + +// Excavator +def : Proc<"bdver4", [ + FeatureX87, + FeatureMMX, + FeatureAVX2, + FeatureFXSR, + FeatureNOPL, + FeatureXOP, + FeatureFMA4, + FeatureCMPXCHG16B, + FeatureAES, + FeaturePRFCHW, + FeaturePCLMUL, + FeatureF16C, + FeatureLZCNT, + FeaturePOPCNT, + FeatureXSAVE, + FeatureBMI, + FeatureBMI2, + FeatureTBM, + FeatureLWP, + FeatureFMA, + FeatureXSAVEOPT, + FeatureSlowSHLD, + FeatureFSGSBase, + FeatureLAHFSAHF, + FeatureFast11ByteNOP, + FeatureMWAITX, + FeatureMacroFusion +]>; + +// Znver1 +def: ProcessorModel<"znver1", Znver1Model, [ + FeatureADX, + FeatureAES, + FeatureAVX2, + FeatureBMI, + FeatureBMI2, + FeatureCLFLUSHOPT, + FeatureCLZERO, + FeatureCMPXCHG16B, + FeatureF16C, + FeatureFMA, + FeatureFSGSBase, + FeatureFXSR, + FeatureNOPL, + FeatureFastLZCNT, + FeatureLAHFSAHF, + FeatureLZCNT, + FeatureFast15ByteNOP, + FeatureMacroFusion, + FeatureMMX, + FeatureMOVBE, + FeatureMWAITX, + FeaturePCLMUL, + FeaturePOPCNT, + FeaturePRFCHW, + FeatureRDRAND, + FeatureRDSEED, + FeatureSHA, + FeatureSSE4A, + FeatureSlowSHLD, + FeatureX87, + FeatureXSAVE, + FeatureXSAVEC, + FeatureXSAVEOPT, + FeatureXSAVES]>; + +def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>; + +def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; +def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; +def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; +def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + FeatureSSE1, FeatureFXSR]>; + +// We also provide a generic 64-bit specific x86 processor model which tries to +// be good for modern chips without enabling instruction set encodings past the +// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and +// modern 64-bit x86 chip, and enables features that are generally beneficial. +// +// We currently use the Sandy Bridge model as the default scheduling model as +// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which +// covers a huge swath of x86 processors. If there are specific scheduling +// knobs which need to be tuned differently for AMD chips, we might consider +// forming a common base for them. +def : ProcessorModel<"x86-64", SandyBridgeModel, [ + FeatureX87, + FeatureMMX, + FeatureSSE2, + FeatureFXSR, + FeatureNOPL, + Feature64Bit, + FeatureSlow3OpsLEA, + FeatureSlowIncDec, + FeatureMacroFusion +]>; + +//===----------------------------------------------------------------------===// +// Calling Conventions +//===----------------------------------------------------------------------===// + +include "X86CallingConv.td" + + +//===----------------------------------------------------------------------===// +// Assembly Parser +//===----------------------------------------------------------------------===// + +def ATTAsmParserVariant : AsmParserVariant { + int Variant = 0; + + // Variant name. + string Name = "att"; + + // Discard comments in assembly strings. + string CommentDelimiter = "#"; + + // Recognize hard coded registers. + string RegisterPrefix = "%"; +} + +def IntelAsmParserVariant : AsmParserVariant { + int Variant = 1; + + // Variant name. + string Name = "intel"; + + // Discard comments in assembly strings. + string CommentDelimiter = ";"; + + // Recognize hard coded registers. + string RegisterPrefix = ""; +} + +//===----------------------------------------------------------------------===// +// Assembly Printers +//===----------------------------------------------------------------------===// + +// The X86 target supports two different syntaxes for emitting machine code. +// This is controlled by the -x86-asm-syntax={att|intel} +def ATTAsmWriter : AsmWriter { + string AsmWriterClassName = "ATTInstPrinter"; + int Variant = 0; +} +def IntelAsmWriter : AsmWriter { + string AsmWriterClassName = "IntelInstPrinter"; + int Variant = 1; +} + +def X86 : Target { + // Information about the instructions... + let InstructionSet = X86InstrInfo; + let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant]; + let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; + let AllowRegisterRenaming = 1; +} + +//===----------------------------------------------------------------------===// +// Pfm Counters +//===----------------------------------------------------------------------===// + +include "X86PfmCounters.td" diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86CallingConv.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86CallingConv.td new file mode 100644 index 0000000..fcc9a29 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86CallingConv.td @@ -0,0 +1,1150 @@ +//===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This describes the calling conventions for the X86-32 and X86-64 +// architectures. +// +//===----------------------------------------------------------------------===// + +/// CCIfSubtarget - Match if the current subtarget has a feature F. +class CCIfSubtarget + : CCIf" + "(State.getMachineFunction().getSubtarget()).", F), + A>; + +/// CCIfNotSubtarget - Match if the current subtarget doesn't has a feature F. +class CCIfNotSubtarget + : CCIf" + "(State.getMachineFunction().getSubtarget()).", F), + A>; + +// Register classes for RegCall +class RC_X86_RegCall { + list GPR_8 = []; + list GPR_16 = []; + list GPR_32 = []; + list GPR_64 = []; + list FP_CALL = [FP0]; + list FP_RET = [FP0, FP1]; + list XMM = []; + list YMM = []; + list ZMM = []; +} + +// RegCall register classes for 32 bits +def RC_X86_32_RegCall : RC_X86_RegCall { + let GPR_8 = [AL, CL, DL, DIL, SIL]; + let GPR_16 = [AX, CX, DX, DI, SI]; + let GPR_32 = [EAX, ECX, EDX, EDI, ESI]; + let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle [] + ///< \todo Fix AssignToReg to enable empty lists + let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]; + let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7]; + let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]; +} + +class RC_X86_64_RegCall : RC_X86_RegCall { + let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, + XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]; + let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, + YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15]; + let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, + ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15]; +} + +def RC_X86_64_RegCall_Win : RC_X86_64_RegCall { + let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B]; + let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W]; + let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D]; + let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15]; +} + +def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall { + let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B]; + let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W]; + let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D]; + let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15]; +} + +// X86-64 Intel regcall calling convention. +multiclass X86_RegCall_base { +def CC_#NAME : CallingConv<[ + // Handles byval parameters. + CCIfSubtarget<"is64Bit()", CCIfByVal>>, + CCIfByVal>, + + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + // Promote v8i1/v16i1/v32i1 arguments to i32. + CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType>, + + // bool, char, int, enum, long, pointer --> GPR + CCIfType<[i32], CCAssignToReg>, + + // long long, __int64 --> GPR + CCIfType<[i64], CCAssignToReg>, + + // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) + CCIfType<[v64i1], CCPromoteToType>, + CCIfSubtarget<"is64Bit()", CCIfType<[i64], + CCAssignToReg>>, + CCIfSubtarget<"is32Bit()", CCIfType<[i64], + CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, + + // float, double, float128 --> XMM + // In the case of SSE disabled --> save to stack + CCIfType<[f32, f64, f128], + CCIfSubtarget<"hasSSE1()", CCAssignToReg>>, + + // long double --> FP + CCIfType<[f80], CCAssignToReg>, + + // __m128, __m128i, __m128d --> XMM + // In the case of SSE disabled --> save to stack + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCIfSubtarget<"hasSSE1()", CCAssignToReg>>, + + // __m256, __m256i, __m256d --> YMM + // In the case of SSE disabled --> save to stack + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCIfSubtarget<"hasAVX()", CCAssignToReg>>, + + // __m512, __m512i, __m512d --> ZMM + // In the case of SSE disabled --> save to stack + CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], + CCIfSubtarget<"hasAVX512()",CCAssignToReg>>, + + // If no register was found -> assign to stack + + // In 64 bit, assign 64/32 bit values to 8 byte stack + CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64], + CCAssignToStack<8, 8>>>, + + // In 32 bit, assign 64/32 bit values to 8/4 byte stack + CCIfType<[i32, f32], CCAssignToStack<4, 4>>, + CCIfType<[i64, f64], CCAssignToStack<8, 4>>, + + // MMX type gets 8 byte slot in stack , while alignment depends on target + CCIfSubtarget<"is64Bit()", CCIfType<[x86mmx], CCAssignToStack<8, 8>>>, + CCIfType<[x86mmx], CCAssignToStack<8, 4>>, + + // float 128 get stack slots whose size and alignment depends + // on the subtarget. + CCIfType<[f80, f128], CCAssignToStack<0, 0>>, + + // Vectors get 16-byte stack slots that are 16-byte aligned. + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCAssignToStack<16, 16>>, + + // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCAssignToStack<32, 32>>, + + // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. + CCIfType<[v16i32, v8i64, v16f32, v8f64], CCAssignToStack<64, 64>> +]>; + +def RetCC_#NAME : CallingConv<[ + // Promote i1, v1i1, v8i1 arguments to i8. + CCIfType<[i1, v1i1, v8i1], CCPromoteToType>, + + // Promote v16i1 arguments to i16. + CCIfType<[v16i1], CCPromoteToType>, + + // Promote v32i1 arguments to i32. + CCIfType<[v32i1], CCPromoteToType>, + + // bool, char, int, enum, long, pointer --> GPR + CCIfType<[i8], CCAssignToReg>, + CCIfType<[i16], CCAssignToReg>, + CCIfType<[i32], CCAssignToReg>, + + // long long, __int64 --> GPR + CCIfType<[i64], CCAssignToReg>, + + // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) + CCIfType<[v64i1], CCPromoteToType>, + CCIfSubtarget<"is64Bit()", CCIfType<[i64], + CCAssignToReg>>, + CCIfSubtarget<"is32Bit()", CCIfType<[i64], + CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, + + // long double --> FP + CCIfType<[f80], CCAssignToReg>, + + // float, double, float128 --> XMM + CCIfType<[f32, f64, f128], + CCIfSubtarget<"hasSSE1()", CCAssignToReg>>, + + // __m128, __m128i, __m128d --> XMM + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCIfSubtarget<"hasSSE1()", CCAssignToReg>>, + + // __m256, __m256i, __m256d --> YMM + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCIfSubtarget<"hasAVX()", CCAssignToReg>>, + + // __m512, __m512i, __m512d --> ZMM + CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], + CCIfSubtarget<"hasAVX512()", CCAssignToReg>> +]>; +} + +//===----------------------------------------------------------------------===// +// Return Value Calling Conventions +//===----------------------------------------------------------------------===// + +// Return-value conventions common to all X86 CC's. +def RetCC_X86Common : CallingConv<[ + // Scalar values are returned in AX first, then DX. For i8, the ABI + // requires the values to be in AL and AH, however this code uses AL and DL + // instead. This is because using AH for the second register conflicts with + // the way LLVM does multiple return values -- a return of {i16,i8} would end + // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI + // for functions that return two i8 values are currently expected to pack the + // values into an i16 (which uses AX, and thus AL:AH). + // + // For code that doesn't care about the ABI, we allow returning more than two + // integer values in registers. + CCIfType<[v1i1], CCPromoteToType>, + CCIfType<[i1], CCPromoteToType>, + CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>, + CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, + CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, + CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>, + + // Boolean vectors of AVX-512 are returned in SIMD registers. + // The call from AVX to AVX-512 function should work, + // since the boolean types in AVX/AVX2 are promoted by default. + CCIfType<[v2i1], CCPromoteToType>, + CCIfType<[v4i1], CCPromoteToType>, + CCIfType<[v8i1], CCPromoteToType>, + CCIfType<[v16i1], CCPromoteToType>, + CCIfType<[v32i1], CCPromoteToType>, + CCIfType<[v64i1], CCPromoteToType>, + + // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 + // can only be used by ABI non-compliant code. If the target doesn't have XMM + // registers, it won't have vector types. + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, + + // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3 + // can only be used by ABI non-compliant code. This vector type is only + // supported while using the AVX target feature. + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, + + // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3 + // can only be used by ABI non-compliant code. This vector type is only + // supported while using the AVX-512 target feature. + CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], + CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, + + // MMX vector types are always returned in MM0. If the target doesn't have + // MM0, it doesn't support these vector types. + CCIfType<[x86mmx], CCAssignToReg<[MM0]>>, + + // Long double types are always returned in FP0 (even with SSE), + // except on Win64. + CCIfNotSubtarget<"isTargetWin64()", CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>> +]>; + +// X86-32 C return-value convention. +def RetCC_X86_32_C : CallingConv<[ + // The X86-32 calling convention returns FP values in FP0, unless marked + // with "inreg" (used here to distinguish one kind of reg from another, + // weirdly; this is really the sse-regparm calling convention) in which + // case they use XMM0, otherwise it is the same as the common X86 calling + // conv. + CCIfInReg>>>, + CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>, + CCDelegateTo +]>; + +// X86-32 FastCC return-value convention. +def RetCC_X86_32_Fast : CallingConv<[ + // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has + // SSE2. + // This can happen when a float, 2 x float, or 3 x float vector is split by + // target lowering, and is returned in 1-3 sse regs. + CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, + CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, + + // For integers, ECX can be used as an extra return register + CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>, + CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, + CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, + + // Otherwise, it is the same as the common X86 calling convention. + CCDelegateTo +]>; + +// Intel_OCL_BI return-value convention. +def RetCC_Intel_OCL_BI : CallingConv<[ + // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. + CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], + CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, + + // 256-bit FP vectors + // No more than 4 registers + CCIfType<[v8f32, v4f64, v8i32, v4i64], + CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, + + // 512-bit FP vectors + CCIfType<[v16f32, v8f64, v16i32, v8i64], + CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, + + // i32, i64 in the standard way + CCDelegateTo +]>; + +// X86-32 HiPE return-value convention. +def RetCC_X86_32_HiPE : CallingConv<[ + // Promote all types to i32 + CCIfType<[i8, i16], CCPromoteToType>, + + // Return: HP, P, VAL1, VAL2 + CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>> +]>; + +// X86-32 Vectorcall return-value convention. +def RetCC_X86_32_VectorCall : CallingConv<[ + // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3. + CCIfType<[f32, f64, f128], + CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, + + // Return integers in the standard way. + CCDelegateTo +]>; + +// X86-64 C return-value convention. +def RetCC_X86_64_C : CallingConv<[ + // The X86-64 calling convention always returns FP values in XMM0. + CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>, + CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>, + CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>, + + // MMX vector types are always returned in XMM0. + CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>, + + CCIfSwiftError>>, + + CCDelegateTo +]>; + +// X86-Win64 C return-value convention. +def RetCC_X86_Win64_C : CallingConv<[ + // The X86-Win64 calling convention always returns __m64 values in RAX. + CCIfType<[x86mmx], CCBitConvertToType>, + + // Otherwise, everything is the same as 'normal' X86-64 C CC. + CCDelegateTo +]>; + +// X86-64 vectorcall return-value convention. +def RetCC_X86_64_Vectorcall : CallingConv<[ + // Vectorcall calling convention always returns FP values in XMMs. + CCIfType<[f32, f64, f128], + CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, + + // Otherwise, everything is the same as Windows X86-64 C CC. + CCDelegateTo +]>; + +// X86-64 HiPE return-value convention. +def RetCC_X86_64_HiPE : CallingConv<[ + // Promote all types to i64 + CCIfType<[i8, i16, i32], CCPromoteToType>, + + // Return: HP, P, VAL1, VAL2 + CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>> +]>; + +// X86-64 WebKit_JS return-value convention. +def RetCC_X86_64_WebKit_JS : CallingConv<[ + // Promote all types to i64 + CCIfType<[i8, i16, i32], CCPromoteToType>, + + // Return: RAX + CCIfType<[i64], CCAssignToReg<[RAX]>> +]>; + +def RetCC_X86_64_Swift : CallingConv<[ + + CCIfSwiftError>>, + + // For integers, ECX, R8D can be used as extra return registers. + CCIfType<[v1i1], CCPromoteToType>, + CCIfType<[i1], CCPromoteToType>, + CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>, + CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>, + CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>, + CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>, + + // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values. + CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, + CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, + CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, + + // MMX vector types are returned in XMM0, XMM1, XMM2 and XMM3. + CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, + CCDelegateTo +]>; + +// X86-64 AnyReg return-value convention. No explicit register is specified for +// the return-value. The register allocator is allowed and expected to choose +// any free register. +// +// This calling convention is currently only supported by the stackmap and +// patchpoint intrinsics. All other uses will result in an assert on Debug +// builds. On Release builds we fallback to the X86 C calling convention. +def RetCC_X86_64_AnyReg : CallingConv<[ + CCCustom<"CC_X86_AnyReg_Error"> +]>; + +// X86-64 HHVM return-value convention. +def RetCC_X86_64_HHVM: CallingConv<[ + // Promote all types to i64 + CCIfType<[i8, i16, i32], CCPromoteToType>, + + // Return: could return in any GP register save RSP and R12. + CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9, + RAX, R10, R11, R13, R14, R15]>> +]>; + + +defm X86_32_RegCall : + X86_RegCall_base; +defm X86_Win64_RegCall : + X86_RegCall_base; +defm X86_SysV64_RegCall : + X86_RegCall_base; + +// This is the root return-value convention for the X86-32 backend. +def RetCC_X86_32 : CallingConv<[ + // If FastCC, use RetCC_X86_32_Fast. + CCIfCC<"CallingConv::Fast", CCDelegateTo>, + // If HiPE, use RetCC_X86_32_HiPE. + CCIfCC<"CallingConv::HiPE", CCDelegateTo>, + CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo>, + CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo>, + + // Otherwise, use RetCC_X86_32_C. + CCDelegateTo +]>; + +// This is the root return-value convention for the X86-64 backend. +def RetCC_X86_64 : CallingConv<[ + // HiPE uses RetCC_X86_64_HiPE + CCIfCC<"CallingConv::HiPE", CCDelegateTo>, + + // Handle JavaScript calls. + CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo>, + CCIfCC<"CallingConv::AnyReg", CCDelegateTo>, + + // Handle Swift calls. + CCIfCC<"CallingConv::Swift", CCDelegateTo>, + + // Handle explicit CC selection + CCIfCC<"CallingConv::Win64", CCDelegateTo>, + CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo>, + + // Handle Vectorcall CC + CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo>, + + // Handle HHVM calls. + CCIfCC<"CallingConv::HHVM", CCDelegateTo>, + + CCIfCC<"CallingConv::X86_RegCall", + CCIfSubtarget<"isTargetWin64()", + CCDelegateTo>>, + CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo>, + + // Mingw64 and native Win64 use Win64 CC + CCIfSubtarget<"isTargetWin64()", CCDelegateTo>, + + // Otherwise, drop to normal X86-64 CC + CCDelegateTo +]>; + +// This is the return-value convention used for the entire X86 backend. +def RetCC_X86 : CallingConv<[ + + // Check if this is the Intel OpenCL built-ins calling convention + CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo>, + + CCIfSubtarget<"is64Bit()", CCDelegateTo>, + CCDelegateTo +]>; + +//===----------------------------------------------------------------------===// +// X86-64 Argument Calling Conventions +//===----------------------------------------------------------------------===// + +def CC_X86_64_C : CallingConv<[ + // Handles byval parameters. + CCIfByVal>, + + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + // The 'nest' parameter, if any, is passed in R10. + CCIfNest>>, + CCIfNest>, + + // Pass SwiftSelf in a callee saved register. + CCIfSwiftSelf>>, + + // A SwiftError is passed in R12. + CCIfSwiftError>>, + + // For Swift Calling Convention, pass sret in %rax. + CCIfCC<"CallingConv::Swift", + CCIfSRet>>>, + + // The first 6 integer arguments are passed in integer registers. + CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, + CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, + + // The first 8 MMX vector arguments are passed in XMM registers on Darwin. + CCIfType<[x86mmx], + CCIfSubtarget<"isTargetDarwin()", + CCIfSubtarget<"hasSSE2()", + CCPromoteToType>>>, + + // Boolean vectors of AVX-512 are passed in SIMD registers. + // The call from AVX to AVX-512 function should work, + // since the boolean types in AVX/AVX2 are promoted by default. + CCIfType<[v2i1], CCPromoteToType>, + CCIfType<[v4i1], CCPromoteToType>, + CCIfType<[v8i1], CCPromoteToType>, + CCIfType<[v16i1], CCPromoteToType>, + CCIfType<[v32i1], CCPromoteToType>, + CCIfType<[v64i1], CCPromoteToType>, + + // The first 8 FP/Vector arguments are passed in XMM registers. + CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCIfSubtarget<"hasSSE1()", + CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, + + // The first 8 256-bit vector arguments are passed in YMM registers, unless + // this is a vararg function. + // FIXME: This isn't precisely correct; the x86-64 ABI document says that + // fixed arguments to vararg functions are supposed to be passed in + // registers. Actually modeling that would be a lot of work, though. + CCIfNotVarArg>>>, + + // The first 8 512-bit vector arguments are passed in ZMM registers. + CCIfNotVarArg>>>, + + // Integer/FP values get stored in stack slots that are 8 bytes in size and + // 8-byte aligned if there are no more registers to hold them. + CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, + + // Long doubles get stack slots whose size and alignment depends on the + // subtarget. + CCIfType<[f80, f128], CCAssignToStack<0, 0>>, + + // Vectors get 16-byte stack slots that are 16-byte aligned. + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, + + // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCAssignToStack<32, 32>>, + + // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. + CCIfType<[v16i32, v8i64, v16f32, v8f64], + CCAssignToStack<64, 64>> +]>; + +// Calling convention for X86-64 HHVM. +def CC_X86_64_HHVM : CallingConv<[ + // Use all/any GP registers for args, except RSP. + CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15, + RDI, RSI, RDX, RCX, R8, R9, + RAX, R10, R11, R13, R14]>> +]>; + +// Calling convention for helper functions in HHVM. +def CC_X86_64_HHVM_C : CallingConv<[ + // Pass the first argument in RBP. + CCIfType<[i64], CCAssignToReg<[RBP]>>, + + // Otherwise it's the same as the regular C calling convention. + CCDelegateTo +]>; + +// Calling convention used on Win64 +def CC_X86_Win64_C : CallingConv<[ + // FIXME: Handle byval stuff. + // FIXME: Handle varargs. + + // Promote i1/v1i1 arguments to i8. + CCIfType<[i1, v1i1], CCPromoteToType>, + + // The 'nest' parameter, if any, is passed in R10. + CCIfNest>, + + // A SwiftError is passed in R12. + CCIfSwiftError>>, + + // 128 bit vectors are passed by pointer + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect>, + + + // 256 bit vectors are passed by pointer + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect>, + + // 512 bit vectors are passed by pointer + CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect>, + + // Long doubles are passed by pointer + CCIfType<[f80], CCPassIndirect>, + + // The first 4 MMX vector arguments are passed in GPRs. + CCIfType<[x86mmx], CCBitConvertToType>, + + // The first 4 integer arguments are passed in integer registers. + CCIfType<[i8 ], CCAssignToRegWithShadow<[CL , DL , R8B , R9B ], + [XMM0, XMM1, XMM2, XMM3]>>, + CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ], + [XMM0, XMM1, XMM2, XMM3]>>, + CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ], + [XMM0, XMM1, XMM2, XMM3]>>, + + // Do not pass the sret argument in RCX, the Win64 thiscall calling + // convention requires "this" to be passed in RCX. + CCIfCC<"CallingConv::X86_ThisCall", + CCIfSRet>>>, + + CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], + [XMM0, XMM1, XMM2, XMM3]>>, + + // The first 4 FP/Vector arguments are passed in XMM registers. + CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3], + [RCX , RDX , R8 , R9 ]>>, + + // Integer/FP values get stored in stack slots that are 8 bytes in size and + // 8-byte aligned if there are no more registers to hold them. + CCIfType<[i8, i16, i32, i64, f32, f64], CCAssignToStack<8, 8>> +]>; + +def CC_X86_Win64_VectorCall : CallingConv<[ + CCCustom<"CC_X86_64_VectorCall">, + + // Delegate to fastcall to handle integer types. + CCDelegateTo +]>; + + +def CC_X86_64_GHC : CallingConv<[ + // Promote i8/i16/i32 arguments to i64. + CCIfType<[i8, i16, i32], CCPromoteToType>, + + // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim + CCIfType<[i64], + CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>, + + // Pass in STG registers: F1, F2, F3, F4, D1, D2 + CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCIfSubtarget<"hasSSE1()", + CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, + // AVX + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCIfSubtarget<"hasAVX()", + CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>, + // AVX-512 + CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], + CCIfSubtarget<"hasAVX512()", + CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>> +]>; + +def CC_X86_64_HiPE : CallingConv<[ + // Promote i8/i16/i32 arguments to i64. + CCIfType<[i8, i16, i32], CCPromoteToType>, + + // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3 + CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>, + + // Integer/FP values get stored in stack slots that are 8 bytes in size and + // 8-byte aligned if there are no more registers to hold them. + CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>> +]>; + +def CC_X86_64_WebKit_JS : CallingConv<[ + // Promote i8/i16 arguments to i32. + CCIfType<[i8, i16], CCPromoteToType>, + + // Only the first integer argument is passed in register. + CCIfType<[i32], CCAssignToReg<[EAX]>>, + CCIfType<[i64], CCAssignToReg<[RAX]>>, + + // The remaining integer arguments are passed on the stack. 32bit integer and + // floating-point arguments are aligned to 4 byte and stored in 4 byte slots. + // 64bit integer and floating-point arguments are aligned to 8 byte and stored + // in 8 byte stack slots. + CCIfType<[i32, f32], CCAssignToStack<4, 4>>, + CCIfType<[i64, f64], CCAssignToStack<8, 8>> +]>; + +// No explicit register is specified for the AnyReg calling convention. The +// register allocator may assign the arguments to any free register. +// +// This calling convention is currently only supported by the stackmap and +// patchpoint intrinsics. All other uses will result in an assert on Debug +// builds. On Release builds we fallback to the X86 C calling convention. +def CC_X86_64_AnyReg : CallingConv<[ + CCCustom<"CC_X86_AnyReg_Error"> +]>; + +//===----------------------------------------------------------------------===// +// X86 C Calling Convention +//===----------------------------------------------------------------------===// + +/// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector +/// values are spilled on the stack. +def CC_X86_32_Vector_Common : CallingConv<[ + // Other SSE vectors get 16-byte stack slots that are 16-byte aligned. + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, + + // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned. + CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], + CCAssignToStack<32, 32>>, + + // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned. + CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], + CCAssignToStack<64, 64>> +]>; + +// CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in +// vector registers +def CC_X86_32_Vector_Standard : CallingConv<[ + // SSE vector arguments are passed in XMM registers. + CCIfNotVarArg>>, + + // AVX 256-bit vector arguments are passed in YMM registers. + CCIfNotVarArg>>>, + + // AVX 512-bit vector arguments are passed in ZMM registers. + CCIfNotVarArg>>, + + CCDelegateTo +]>; + +// CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in +// vector registers. +def CC_X86_32_Vector_Darwin : CallingConv<[ + // SSE vector arguments are passed in XMM registers. + CCIfNotVarArg>>, + + // AVX 256-bit vector arguments are passed in YMM registers. + CCIfNotVarArg>>>, + + // AVX 512-bit vector arguments are passed in ZMM registers. + CCIfNotVarArg>>, + + CCDelegateTo +]>; + +/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP +/// values are spilled on the stack. +def CC_X86_32_Common : CallingConv<[ + // Handles byval parameters. + CCIfByVal>, + + // The first 3 float or double arguments, if marked 'inreg' and if the call + // is not a vararg call and if SSE2 is available, are passed in SSE registers. + CCIfNotVarArg>>>>, + + // The first 3 __m64 vector arguments are passed in mmx registers if the + // call is not a vararg call. + CCIfNotVarArg>>, + + // Integer/Float values get stored in stack slots that are 4 bytes in + // size and 4-byte aligned. + CCIfType<[i32, f32], CCAssignToStack<4, 4>>, + + // Doubles get 8-byte slots that are 4-byte aligned. + CCIfType<[f64], CCAssignToStack<8, 4>>, + + // Long doubles get slots whose size depends on the subtarget. + CCIfType<[f80], CCAssignToStack<0, 4>>, + + // Boolean vectors of AVX-512 are passed in SIMD registers. + // The call from AVX to AVX-512 function should work, + // since the boolean types in AVX/AVX2 are promoted by default. + CCIfType<[v2i1], CCPromoteToType>, + CCIfType<[v4i1], CCPromoteToType>, + CCIfType<[v8i1], CCPromoteToType>, + CCIfType<[v16i1], CCPromoteToType>, + CCIfType<[v32i1], CCPromoteToType>, + CCIfType<[v64i1], CCPromoteToType>, + + // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are + // passed in the parameter area. + CCIfType<[x86mmx], CCAssignToStack<8, 4>>, + + // Darwin passes vectors in a form that differs from the i386 psABI + CCIfSubtarget<"isTargetDarwin()", CCDelegateTo>, + + // Otherwise, drop to 'normal' X86-32 CC + CCDelegateTo +]>; + +def CC_X86_32_C : CallingConv<[ + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + // The 'nest' parameter, if any, is passed in ECX. + CCIfNest>, + + // The first 3 integer arguments, if marked 'inreg' and if the call is not + // a vararg call, are passed in integer registers. + CCIfNotVarArg>>>, + + // Otherwise, same as everything else. + CCDelegateTo +]>; + +def CC_X86_32_MCU : CallingConv<[ + // Handles byval parameters. Note that, like FastCC, we can't rely on + // the delegation to CC_X86_32_Common because that happens after code that + // puts arguments in registers. + CCIfByVal>, + + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + // If the call is not a vararg call, some arguments may be passed + // in integer registers. + CCIfNotVarArg>>, + + // Otherwise, same as everything else. + CCDelegateTo +]>; + +def CC_X86_32_FastCall : CallingConv<[ + // Promote i1 to i8. + CCIfType<[i1], CCPromoteToType>, + + // The 'nest' parameter, if any, is passed in EAX. + CCIfNest>, + + // The first 2 integer arguments are passed in ECX/EDX + CCIfInReg>>, + CCIfInReg>>, + CCIfInReg>>, + + // Otherwise, same as everything else. + CCDelegateTo +]>; + +def CC_X86_Win32_VectorCall : CallingConv<[ + // Pass floating point in XMMs + CCCustom<"CC_X86_32_VectorCall">, + + // Delegate to fastcall to handle integer types. + CCDelegateTo +]>; + +def CC_X86_32_ThisCall_Common : CallingConv<[ + // The first integer argument is passed in ECX + CCIfType<[i32], CCAssignToReg<[ECX]>>, + + // Otherwise, same as everything else. + CCDelegateTo +]>; + +def CC_X86_32_ThisCall_Mingw : CallingConv<[ + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + CCDelegateTo +]>; + +def CC_X86_32_ThisCall_Win : CallingConv<[ + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + // Pass sret arguments indirectly through stack. + CCIfSRet>, + + CCDelegateTo +]>; + +def CC_X86_32_ThisCall : CallingConv<[ + CCIfSubtarget<"isTargetCygMing()", CCDelegateTo>, + CCDelegateTo +]>; + +def CC_X86_32_FastCC : CallingConv<[ + // Handles byval parameters. Note that we can't rely on the delegation + // to CC_X86_32_Common for this because that happens after code that + // puts arguments in registers. + CCIfByVal>, + + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType>, + + // The 'nest' parameter, if any, is passed in EAX. + CCIfNest>, + + // The first 2 integer arguments are passed in ECX/EDX + CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>, + + // The first 3 float or double arguments, if the call is not a vararg + // call and if SSE2 is available, are passed in SSE registers. + CCIfNotVarArg>>>, + + // Doubles get 8-byte slots that are 8-byte aligned. + CCIfType<[f64], CCAssignToStack<8, 8>>, + + // Otherwise, same as everything else. + CCDelegateTo +]>; + +def CC_X86_32_GHC : CallingConv<[ + // Promote i8/i16 arguments to i32. + CCIfType<[i8, i16], CCPromoteToType>, + + // Pass in STG registers: Base, Sp, Hp, R1 + CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>> +]>; + +def CC_X86_32_HiPE : CallingConv<[ + // Promote i8/i16 arguments to i32. + CCIfType<[i8, i16], CCPromoteToType>, + + // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2 + CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>, + + // Integer/Float values get stored in stack slots that are 4 bytes in + // size and 4-byte aligned. + CCIfType<[i32, f32], CCAssignToStack<4, 4>> +]>; + +// X86-64 Intel OpenCL built-ins calling convention. +def CC_Intel_OCL_BI : CallingConv<[ + + CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>, + CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>, + + CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>, + CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>, + + CCIfType<[i32], CCAssignToStack<4, 4>>, + + // The SSE vector arguments are passed in XMM registers. + CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], + CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, + + // The 256-bit vector arguments are passed in YMM registers. + CCIfType<[v8f32, v4f64, v8i32, v4i64], + CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>, + + // The 512-bit vector arguments are passed in ZMM registers. + CCIfType<[v16f32, v8f64, v16i32, v8i64], + CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>, + + // Pass masks in mask registers + CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>, + + CCIfSubtarget<"isTargetWin64()", CCDelegateTo>, + CCIfSubtarget<"is64Bit()", CCDelegateTo>, + CCDelegateTo +]>; + +def CC_X86_32_Intr : CallingConv<[ + CCAssignToStack<4, 4> +]>; + +def CC_X86_64_Intr : CallingConv<[ + CCAssignToStack<8, 8> +]>; + +//===----------------------------------------------------------------------===// +// X86 Root Argument Calling Conventions +//===----------------------------------------------------------------------===// + +// This is the root argument convention for the X86-32 backend. +def CC_X86_32 : CallingConv<[ + // X86_INTR calling convention is valid in MCU target and should override the + // MCU calling convention. Thus, this should be checked before isTargetMCU(). + CCIfCC<"CallingConv::X86_INTR", CCDelegateTo>, + CCIfSubtarget<"isTargetMCU()", CCDelegateTo>, + CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo>, + CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo>, + CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo>, + CCIfCC<"CallingConv::Fast", CCDelegateTo>, + CCIfCC<"CallingConv::GHC", CCDelegateTo>, + CCIfCC<"CallingConv::HiPE", CCDelegateTo>, + CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo>, + + // Otherwise, drop to normal X86-32 CC + CCDelegateTo +]>; + +// This is the root argument convention for the X86-64 backend. +def CC_X86_64 : CallingConv<[ + CCIfCC<"CallingConv::GHC", CCDelegateTo>, + CCIfCC<"CallingConv::HiPE", CCDelegateTo>, + CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo>, + CCIfCC<"CallingConv::AnyReg", CCDelegateTo>, + CCIfCC<"CallingConv::Win64", CCDelegateTo>, + CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo>, + CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo>, + CCIfCC<"CallingConv::HHVM", CCDelegateTo>, + CCIfCC<"CallingConv::HHVM_C", CCDelegateTo>, + CCIfCC<"CallingConv::X86_RegCall", + CCIfSubtarget<"isTargetWin64()", CCDelegateTo>>, + CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo>, + CCIfCC<"CallingConv::X86_INTR", CCDelegateTo>, + + // Mingw64 and native Win64 use Win64 CC + CCIfSubtarget<"isTargetWin64()", CCDelegateTo>, + + // Otherwise, drop to normal X86-64 CC + CCDelegateTo +]>; + +// This is the argument convention used for the entire X86 backend. +def CC_X86 : CallingConv<[ + CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo>, + CCIfSubtarget<"is64Bit()", CCDelegateTo>, + CCDelegateTo +]>; + +//===----------------------------------------------------------------------===// +// Callee-saved Registers. +//===----------------------------------------------------------------------===// + +def CSR_NoRegs : CalleeSavedRegs<(add)>; + +def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; +def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>; + +def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>; + +def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>; +def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>; + +def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>; + +def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE, + (sequence "XMM%u", 6, 15))>; + +def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>; + +// The function used by Darwin to obtain the address of a thread-local variable +// uses rdi to pass a single parameter and rax for the return value. All other +// GPRs are preserved. +def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI, + R8, R9, R10, R11)>; + +// CSRs that are handled by prologue, epilogue. +def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>; + +// CSRs that are handled explicitly via copies. +def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>; + +// All GPRs - except r11 +def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI, + R8, R9, R10, RSP)>; + +// All registers - except r11 +def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, + (sequence "XMM%u", 0, 15))>; +def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs, + (sequence "YMM%u", 0, 15))>; + +def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10, + R11, R12, R13, R14, R15, RBP, + (sequence "XMM%u", 0, 15))>; + +def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI, + EDI)>; +def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs, + (sequence "XMM%u", 0, 7))>; +def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs, + (sequence "YMM%u", 0, 7))>; +def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs, + (sequence "ZMM%u", 0, 7), + (sequence "K%u", 0, 7))>; + +def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>; +def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9, + R10, R11, R12, R13, R14, R15, RBP)>; +def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, + (sequence "YMM%u", 0, 15)), + (sequence "XMM%u", 0, 15))>; +def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, + (sequence "ZMM%u", 0, 31), + (sequence "K%u", 0, 7)), + (sequence "XMM%u", 0, 15))>; + +// Standard C + YMM6-15 +def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, + R13, R14, R15, + (sequence "YMM%u", 6, 15))>; + +def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, + R12, R13, R14, R15, + (sequence "ZMM%u", 6, 21), + K4, K5, K6, K7)>; +//Standard C + XMM 8-15 +def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64, + (sequence "XMM%u", 8, 15))>; + +//Standard C + YMM 8-15 +def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64, + (sequence "YMM%u", 8, 15))>; + +def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15, + (sequence "ZMM%u", 16, 31), + K4, K5, K6, K7)>; + +// Only R12 is preserved for PHP calls in HHVM. +def CSR_64_HHVM : CalleeSavedRegs<(add R12)>; + +// Register calling convention preserves few GPR and XMM8-15 +def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP, ESP)>; +def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, + (sequence "XMM%u", 4, 7))>; +def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP, + (sequence "R%u", 10, 15))>; +def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE, + (sequence "XMM%u", 8, 15))>; +def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP, + (sequence "R%u", 12, 15))>; +def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE, + (sequence "XMM%u", 8, 15))>; + diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86Capstone.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86Capstone.td new file mode 100644 index 0000000..ca21b63 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86Capstone.td @@ -0,0 +1,7 @@ +// Capstone definitions fix for X86 LLVM instructions. + +let Defs = [EFLAGS] in + def INT1 : I<0xf1, RawFrm, (outs), (ins), "int1", []>; + +// def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>; +def FSETPM : I<0xDB, MRM_E4, (outs), (ins), "fsetpm", []>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86CapstoneFull.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86CapstoneFull.td new file mode 100644 index 0000000..5bd4095 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86CapstoneFull.td @@ -0,0 +1,103 @@ +// Capstone definitions fix for X86 LLVM instructions. + +let Defs = [EFLAGS] in + def INT1 : I<0xf1, RawFrm, (outs), (ins), "int1", []>; + +def FSETPM : I<0xDB, MRM_E4, (outs), (ins), "fsetpm", []>; + +// Capstone: comment out below lines for X86 Reduce mode + +/* +// X87 Floating Point Stack. +include "X86InstrFPStack.td" + +// SIMD support (SSE, MMX and AVX) +include "X86InstrFragmentsSIMD.td" + +// FMA - Fused Multiply-Add support (requires FMA) +include "X86InstrFMA.td" + +// XOP +include "X86InstrXOP.td" + +// SSE, MMX and 3DNow! vector support. +include "X86InstrSSE.td" +include "X86InstrAVX512.td" +include "X86InstrMMX.td" +include "X86Instr3DNow.td" + +// MPX instructions +include "X86InstrMPX.td" + +//include "X86InstrTSX.td" +include "X86InstrSGX.td" + +// Various unary fpstack operations default to operating on ST1. +// For example, "fxch" -> "fxch %st(1)" +def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; +def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; +def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; +def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; +def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; +def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; +def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; +def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; +def : InstAlias<"fxch", (XCH_F ST1), 0>; +def : InstAlias<"fcom", (COM_FST0r ST1), 0>; +def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; +def : InstAlias<"fcomi", (COM_FIr ST1), 0>; +def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; +def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; +def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; +def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; +def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; + +// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. +// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate +// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with +// gas. +multiclass FpUnaryAlias { + def : InstAlias; + def : InstAlias; +} + +defm : FpUnaryAlias<"fadd", ADD_FST0r>; +defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; +defm : FpUnaryAlias<"fsub", SUB_FST0r>; +defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; +defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; +defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; +defm : FpUnaryAlias<"fmul", MUL_FST0r>; +defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; +defm : FpUnaryAlias<"fdiv", DIV_FST0r>; +defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; +defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; +defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; +defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; +defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; +defm : FpUnaryAlias<"fcompi", COM_FIPr>; +defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; + + +// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they +// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, +// solely because gas supports it. +def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; +def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; +def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; +def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; +def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; +def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; + +def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; + +// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, +// which supports this due to an old AMD documentation bug when 64-bit mode was +// created. +def : InstAlias<"movd\t{$src, $dst|$dst, $src}", + (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; +def : InstAlias<"movd\t{$src, $dst|$dst, $src}", + (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; +*/ diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86CapstoneReduce.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86CapstoneReduce.td new file mode 100644 index 0000000..2c0920e --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86CapstoneReduce.td @@ -0,0 +1,101 @@ +// Capstone definitions fix for X86 LLVM instructions. + +let Defs = [EFLAGS] in + def INT1 : I<0xf1, RawFrm, (outs), (ins), "int1", []>; + +def FSETPM : I<0xDB, MRM_E4, (outs), (ins), "fsetpm", []>; + +// Capstone: comment out below lines for X86 Reduce mode + +// X87 Floating Point Stack. +//include "X86InstrFPStack.td" + +// SIMD support (SSE, MMX and AVX) +//include "X86InstrFragmentsSIMD.td" + +// FMA - Fused Multiply-Add support (requires FMA) +//include "X86InstrFMA.td" + +// XOP +//include "X86InstrXOP.td" + +// SSE, MMX and 3DNow! vector support. +//include "X86InstrSSE.td" +//include "X86InstrAVX512.td" +//include "X86InstrMMX.td" +//include "X86Instr3DNow.td" + +// MPX instructions +//include "X86InstrMPX.td" + +//include "X86InstrTSX.td" +//include "X86InstrSGX.td" + +// Various unary fpstack operations default to operating on ST1. +// For example, "fxch" -> "fxch %st(1)" +//def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; +//def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; +//def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; +//def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; +//def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; +//def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; +//def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; +//def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; +//def : InstAlias<"fxch", (XCH_F ST1), 0>; +//def : InstAlias<"fcom", (COM_FST0r ST1), 0>; +//def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; +//def : InstAlias<"fcomi", (COM_FIr ST1), 0>; +//def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; +//def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; +//def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; +//def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; +//def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; + +// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. +// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate +// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with +// gas. +multiclass FpUnaryAlias { + def : InstAlias; + def : InstAlias; +} + +//defm : FpUnaryAlias<"fadd", ADD_FST0r>; +//defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; +//defm : FpUnaryAlias<"fsub", SUB_FST0r>; +//defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; +//defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; +//defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; +//defm : FpUnaryAlias<"fmul", MUL_FST0r>; +//defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; +//defm : FpUnaryAlias<"fdiv", DIV_FST0r>; +//defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; +//defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; +//defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; +//defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; +//defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; +//defm : FpUnaryAlias<"fcompi", COM_FIPr>; +//defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; + + +// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they +// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, +// solely because gas supports it. +//def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; +//def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; +//def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; +//def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; +//def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; +//def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; +// +//def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; + +// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, +// which supports this due to an old AMD documentation bug when 64-bit mode was +// created. +//def : InstAlias<"movd\t{$src, $dst|$dst, $src}", +// (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; +//def : InstAlias<"movd\t{$src, $dst|$dst, $src}", +// (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86Instr3DNow.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86Instr3DNow.td new file mode 100644 index 0000000..46dc6bf --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86Instr3DNow.td @@ -0,0 +1,111 @@ +//===-- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the 3DNow! instruction set, which extends MMX to support +// floating point and also adds a few more random instructions for good measure. +// +//===----------------------------------------------------------------------===// + +class I3DNow o, Format F, dag outs, dag ins, string asm, list pat> + : I, Requires<[Has3DNow]> { +} + +class I3DNow_binop o, Format F, dag ins, string Mnemonic, list pat> + : I3DNow, ThreeDNow { + let Constraints = "$src1 = $dst"; +} + +class I3DNow_conv o, Format F, dag ins, string Mnemonic, list pat> + : I3DNow, ThreeDNow; + +multiclass I3DNow_binop_rm_int opc, string Mn, + X86FoldableSchedWrite sched, bit Commutable = 0, + string Ver = ""> { + let isCommutable = Commutable in + def rr : I3DNow_binop( + !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))]>, + Sched<[sched]>; + def rm : I3DNow_binop( + !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, + (bitconvert (load_mmx addr:$src2))))]>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass I3DNow_conv_rm_int opc, string Mn, + X86FoldableSchedWrite sched, string Ver = ""> { + def rr : I3DNow_conv( + !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))]>, + Sched<[sched]>; + def rm : I3DNow_conv( + !strconcat("int_x86_3dnow", Ver, "_", Mn)) + (bitconvert (load_mmx addr:$src))))]>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", SchedWriteVecALU.MMX, 1>; +defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id", WriteCvtPS2I>; +defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc", WriteFAdd>; +defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd", WriteFAdd, 1>; +defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq", WriteFAdd, 1>; +defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge", WriteFAdd>; +defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt", WriteFAdd>; +defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax", WriteFAdd>; +defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin", WriteFAdd>; +defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul", WriteFAdd, 1>; +defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp", WriteFAdd>; +defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1", WriteFAdd>; +defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2", WriteFAdd>; +defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1", WriteFAdd>; +defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt", WriteFAdd>; +defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub", WriteFAdd, 1>; +defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", WriteFAdd, 1>; +defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd", WriteCvtI2PS>; +defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", SchedWriteVecIMul.MMX, 1>; + +let SchedRW = [WriteEMMS] in +def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", + [(int_x86_mmx_femms)]>, TB; + +// PREFETCHWT1 is supported we want to use it for everything but T0. +def PrefetchWLevel : PatFrag<(ops), (i32 imm), [{ + return N->getSExtValue() == 3 || !Subtarget->hasPREFETCHWT1(); +}]>; + +// Use PREFETCHWT1 for NTA, T2, T1. +def PrefetchWT1Level : ImmLeaf; + +let SchedRW = [WriteLoad] in { +let Predicates = [Has3DNow, NoSSEPrefetch] in +def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr), + "prefetch\t$addr", + [(prefetch addr:$addr, imm, imm, (i32 1))]>, TB; + +def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr", + [(prefetch addr:$addr, (i32 1), (i32 PrefetchWLevel), (i32 1))]>, + TB, Requires<[HasPrefetchW]>; + +def PREFETCHWT1 : I<0x0D, MRM2m, (outs), (ins i8mem:$addr), "prefetchwt1\t$addr", + [(prefetch addr:$addr, (i32 1), (i32 PrefetchWT1Level), (i32 1))]>, + TB, Requires<[HasPREFETCHWT1]>; +} + +// "3DNowA" instructions +defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", WriteCvtPS2I, "a">; +defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", WriteCvtI2PS, "a">; +defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", WriteFAdd, 0, "a">; +defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", WriteFAdd, 0, "a">; +defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", SchedWriteShuffle.MMX, "a">; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrAVX512.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrAVX512.td new file mode 100644 index 0000000..fcb3723 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrAVX512.td @@ -0,0 +1,11968 @@ +//===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 AVX512 instruction set, defining the +// instructions, and properties of the instructions which are needed for code +// generation, machine code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +// Group template arguments that can be derived from the vector type (EltNum x +// EltVT). These are things like the register class for the writemask, etc. +// The idea is to pass one of these as the template argument rather than the +// individual arguments. +// The template is also used for scalar types, in this case numelts is 1. +class X86VectorVTInfo { + RegisterClass RC = rc; + ValueType EltVT = eltvt; + int NumElts = numelts; + + // Corresponding mask register class. + RegisterClass KRC = !cast("VK" # NumElts); + + // Corresponding write-mask register class. + RegisterClass KRCWM = !cast("VK" # NumElts # "WM"); + + // The mask VT. + ValueType KVT = !cast("v" # NumElts # "i1"); + + // Suffix used in the instruction mnemonic. + string Suffix = suffix; + + // VTName is a string name for vector VT. For vector types it will be + // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32 + // It is a little bit complex for scalar types, where NumElts = 1. + // In this case we build v4f32 or v2f64 + string VTName = "v" # !if (!eq (NumElts, 1), + !if (!eq (EltVT.Size, 32), 4, + !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT; + + // The vector VT. + ValueType VT = !cast(VTName); + + string EltTypeName = !cast(EltVT); + // Size of the element type in bits, e.g. 32 for v16i32. + string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName)); + int EltSize = EltVT.Size; + + // "i" for integer types and "f" for floating-point types + string TypeVariantName = !subst(EltSizeName, "", EltTypeName); + + // Size of RC in bits, e.g. 512 for VR512. + int Size = VT.Size; + + // The corresponding memory operand, e.g. i512mem for VR512. + X86MemOperand MemOp = !cast(TypeVariantName # Size # "mem"); + X86MemOperand ScalarMemOp = !cast(EltVT # "mem"); + // FP scalar memory operand for intrinsics - ssmem/sdmem. + Operand IntScalarMemOp = !if (!eq (EltTypeName, "f32"), !cast("ssmem"), + !if (!eq (EltTypeName, "f64"), !cast("sdmem"), ?)); + + // Load patterns + // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64 + // due to load promotion during legalization + PatFrag LdFrag = !cast("load" # + !if (!eq (TypeVariantName, "i"), + !if (!eq (Size, 128), "v2i64", + !if (!eq (Size, 256), "v4i64", + !if (!eq (Size, 512), "v8i64", + VTName))), VTName)); + + PatFrag AlignedLdFrag = !cast("alignedload" # + !if (!eq (TypeVariantName, "i"), + !if (!eq (Size, 128), "v2i64", + !if (!eq (Size, 256), "v4i64", + !if (!eq (Size, 512), "v8i64", + VTName))), VTName)); + + PatFrag ScalarLdFrag = !cast("load" # EltVT); + + ComplexPattern ScalarIntMemCPat = !if (!eq (EltTypeName, "f32"), + !cast("sse_load_f32"), + !if (!eq (EltTypeName, "f64"), + !cast("sse_load_f64"), + ?)); + + // The string to specify embedded broadcast in assembly. + string BroadcastStr = "{1to" # NumElts # "}"; + + // 8-bit compressed displacement tuple/subvector format. This is only + // defined for NumElts <= 8. + CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0), + !cast("CD8VT" # NumElts), ?); + + SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm, + !if (!eq (Size, 256), sub_ymm, ?)); + + Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle, + !if (!eq (EltTypeName, "f64"), SSEPackedDouble, + SSEPackedInt)); + + RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X); + + // A vector type of the same width with element type i64. This is used to + // create patterns for logic ops. + ValueType i64VT = !cast("v" # !srl(Size, 6) # "i64"); + + // A vector type of the same width with element type i32. This is used to + // create the canonical constant zero node ImmAllZerosV. + ValueType i32VT = !cast("v" # !srl(Size, 5) # "i32"); + dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV))); + + string ZSuffix = !if (!eq (Size, 128), "Z128", + !if (!eq (Size, 256), "Z256", "Z")); +} + +def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">; +def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">; +def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">; +def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">; +def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">; +def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">; + +// "x" in v32i8x_info means RC = VR256X +def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">; +def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">; +def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">; +def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">; +def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">; +def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">; + +def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">; +def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">; +def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">; +def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">; +def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">; +def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">; + +// We map scalar types to the smallest (128-bit) vector type +// with the appropriate element type. This allows to use the same masking logic. +def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">; +def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">; +def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">; +def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">; + +class AVX512VLVectorVTInfo { + X86VectorVTInfo info512 = i512; + X86VectorVTInfo info256 = i256; + X86VectorVTInfo info128 = i128; +} + +def avx512vl_i8_info : AVX512VLVectorVTInfo; +def avx512vl_i16_info : AVX512VLVectorVTInfo; +def avx512vl_i32_info : AVX512VLVectorVTInfo; +def avx512vl_i64_info : AVX512VLVectorVTInfo; +def avx512vl_f32_info : AVX512VLVectorVTInfo; +def avx512vl_f64_info : AVX512VLVectorVTInfo; + +class X86KVectorVTInfo { + RegisterClass KRC = _krc; + RegisterClass KRCWM = _krcwm; + ValueType KVT = _vt; +} + +def v1i1_info : X86KVectorVTInfo; +def v2i1_info : X86KVectorVTInfo; +def v4i1_info : X86KVectorVTInfo; +def v8i1_info : X86KVectorVTInfo; +def v16i1_info : X86KVectorVTInfo; +def v32i1_info : X86KVectorVTInfo; +def v64i1_info : X86KVectorVTInfo; + +// This multiclass generates the masking variants from the non-masking +// variant. It only provides the assembly pieces for the masking variants. +// It assumes custom ISel patterns for masking which can be provided as +// template arguments. +multiclass AVX512_maskable_custom O, Format F, + dag Outs, + dag Ins, dag MaskingIns, dag ZeroMaskingIns, + string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + list Pattern, + list MaskingPattern, + list ZeroMaskingPattern, + string MaskingConstraint = "", + bit IsCommutable = 0, + bit IsKCommutable = 0, + bit IsKZCommutable = IsCommutable> { + let isCommutable = IsCommutable in + def NAME: AVX512; + + // Prefer over VMOV*rrk Pat<> + let isCommutable = IsKCommutable in + def NAME#k: AVX512, + EVEX_K { + // In case of the 3src subclass this is overridden with a let. + string Constraints = MaskingConstraint; + } + + // Zero mask does not add any restrictions to commute operands transformation. + // So, it is Ok to use IsCommutable instead of IsKCommutable. + let isCommutable = IsKZCommutable in // Prefer over VMOV*rrkz Pat<> + def NAME#kz: AVX512, + EVEX_KZ; +} + + +// Common base class of AVX512_maskable and AVX512_maskable_3src. +multiclass AVX512_maskable_common O, Format F, X86VectorVTInfo _, + dag Outs, + dag Ins, dag MaskingIns, dag ZeroMaskingIns, + string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, dag MaskingRHS, + SDNode Select = vselect, + string MaskingConstraint = "", + bit IsCommutable = 0, + bit IsKCommutable = 0, + bit IsKZCommutable = IsCommutable> : + AVX512_maskable_custom; + +// This multiclass generates the unconditional/non-masking, the masking and +// the zero-masking variant of the vector instruction. In the masking case, the +// preserved vector elements come from a new dummy input operand tied to $dst. +// This version uses a separate dag for non-masking and masking. +multiclass AVX512_maskable_split O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, dag MaskRHS, + bit IsCommutable = 0, bit IsKCommutable = 0, + SDNode Select = vselect> : + AVX512_maskable_custom; + +// This multiclass generates the unconditional/non-masking, the masking and +// the zero-masking variant of the vector instruction. In the masking case, the +// preserved vector elements come from a new dummy input operand tied to $dst. +multiclass AVX512_maskable O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, + bit IsCommutable = 0, bit IsKCommutable = 0, + bit IsKZCommutable = IsCommutable, + SDNode Select = vselect> : + AVX512_maskable_common; + +// This multiclass generates the unconditional/non-masking, the masking and +// the zero-masking variant of the scalar instruction. +multiclass AVX512_maskable_scalar O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, + bit IsCommutable = 0> : + AVX512_maskable; + +// Similar to AVX512_maskable but in this case one of the source operands +// ($src1) is already tied to $dst so we just use that for the preserved +// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude +// $src1. +multiclass AVX512_maskable_3src O, Format F, X86VectorVTInfo _, + dag Outs, dag NonTiedIns, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, + bit IsCommutable = 0, + bit IsKCommutable = 0, + SDNode Select = vselect, + bit MaskOnly = 0> : + AVX512_maskable_common; + +// Similar to AVX512_maskable_3src but in this case the input VT for the tied +// operand differs from the output VT. This requires a bitconvert on +// the preserved vector going into the vselect. +// NOTE: The unmasked pattern is disabled. +multiclass AVX512_maskable_3src_cast O, Format F, X86VectorVTInfo OutVT, + X86VectorVTInfo InVT, + dag Outs, dag NonTiedIns, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, bit IsCommutable = 0> : + AVX512_maskable_common; + +multiclass AVX512_maskable_3src_scalar O, Format F, X86VectorVTInfo _, + dag Outs, dag NonTiedIns, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, + bit IsCommutable = 0, + bit IsKCommutable = 0, + bit MaskOnly = 0> : + AVX512_maskable_3src; + +multiclass AVX512_maskable_in_asm O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, + string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + list Pattern> : + AVX512_maskable_custom; + +multiclass AVX512_maskable_3src_in_asm O, Format F, X86VectorVTInfo _, + dag Outs, dag NonTiedIns, + string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + list Pattern> : + AVX512_maskable_custom; + +// Instruction with mask that puts result in mask register, +// like "compare" and "vptest" +multiclass AVX512_maskable_custom_cmp O, Format F, + dag Outs, + dag Ins, dag MaskingIns, + string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + list Pattern, + list MaskingPattern, + bit IsCommutable = 0> { + let isCommutable = IsCommutable in + def NAME: AVX512; + + def NAME#k: AVX512, EVEX_K; +} + +multiclass AVX512_maskable_common_cmp O, Format F, X86VectorVTInfo _, + dag Outs, + dag Ins, dag MaskingIns, + string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, dag MaskingRHS, + bit IsCommutable = 0> : + AVX512_maskable_custom_cmp; + +multiclass AVX512_maskable_cmp O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, bit IsCommutable = 0> : + AVX512_maskable_common_cmp; + +multiclass AVX512_maskable_cmp_alt O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm> : + AVX512_maskable_custom_cmp; + +// This multiclass generates the unconditional/non-masking, the masking and +// the zero-masking variant of the vector instruction. In the masking case, the +// preserved vector elements come from a new dummy input operand tied to $dst. +multiclass AVX512_maskable_logic O, Format F, X86VectorVTInfo _, + dag Outs, dag Ins, string OpcodeStr, + string AttSrcAsm, string IntelSrcAsm, + dag RHS, dag MaskedRHS, + bit IsCommutable = 0, SDNode Select = vselect> : + AVX512_maskable_custom; + + +// Alias instruction that maps zero vector to pxor / xorp* for AVX-512. +// This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then +// swizzled by ExecutionDomainFix to pxor. +// We set canFoldAsLoad because this can be converted to a constant-pool +// load of an all-zeros value if folding it would be beneficial. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, Predicates = [HasAVX512], SchedRW = [WriteZero] in { +def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "", + [(set VR512:$dst, (v16i32 immAllZerosV))]>; +def AVX512_512_SETALLONES : I<0, Pseudo, (outs VR512:$dst), (ins), "", + [(set VR512:$dst, (v16i32 immAllOnesV))]>; +} + +// Alias instructions that allow VPTERNLOG to be used with a mask to create +// a mix of all ones and all zeros elements. This is done this way to force +// the same register to be used as input for all three sources. +let isPseudo = 1, Predicates = [HasAVX512], SchedRW = [WriteVecALU] in { +def AVX512_512_SEXT_MASK_32 : I<0, Pseudo, (outs VR512:$dst), + (ins VK16WM:$mask), "", + [(set VR512:$dst, (vselect (v16i1 VK16WM:$mask), + (v16i32 immAllOnesV), + (v16i32 immAllZerosV)))]>; +def AVX512_512_SEXT_MASK_64 : I<0, Pseudo, (outs VR512:$dst), + (ins VK8WM:$mask), "", + [(set VR512:$dst, (vselect (v8i1 VK8WM:$mask), + (bc_v8i64 (v16i32 immAllOnesV)), + (bc_v8i64 (v16i32 immAllZerosV))))]>; +} + +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, Predicates = [HasAVX512], SchedRW = [WriteZero] in { +def AVX512_128_SET0 : I<0, Pseudo, (outs VR128X:$dst), (ins), "", + [(set VR128X:$dst, (v4i32 immAllZerosV))]>; +def AVX512_256_SET0 : I<0, Pseudo, (outs VR256X:$dst), (ins), "", + [(set VR256X:$dst, (v8i32 immAllZerosV))]>; +} + +// Alias instructions that map fld0 to xorps for sse or vxorps for avx. +// This is expanded by ExpandPostRAPseudos. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, SchedRW = [WriteZero], Predicates = [HasAVX512] in { + def AVX512_FsFLD0SS : I<0, Pseudo, (outs FR32X:$dst), (ins), "", + [(set FR32X:$dst, fp32imm0)]>; + def AVX512_FsFLD0SD : I<0, Pseudo, (outs FR64X:$dst), (ins), "", + [(set FR64X:$dst, fpimm0)]>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 - VECTOR INSERT +// + +// Supports two different pattern operators for mask and unmasked ops. Allows +// null_frag to be passed for one. +multiclass vinsert_for_size_split { + let hasSideEffects = 0, ExeDomain = To.ExeDomain in { + defm rr : AVX512_maskable_split, + AVX512AIi8Base, EVEX_4V, Sched<[sched]>; + let mayLoad = 1 in + defm rm : AVX512_maskable_split, AVX512AIi8Base, EVEX_4V, + EVEX_CD8, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +// Passes the same pattern operator for masked and unmasked ops. +multiclass vinsert_for_size : + vinsert_for_size_split; + +multiclass vinsert_for_size_lowering p> { + let Predicates = p in { + def : Pat<(vinsert_insert:$ins + (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)), + (To.VT (!cast(InstrStr#"rr") + To.RC:$src1, From.RC:$src2, + (INSERT_get_vinsert_imm To.RC:$ins)))>; + + def : Pat<(vinsert_insert:$ins + (To.VT To.RC:$src1), + (From.VT (bitconvert (From.LdFrag addr:$src2))), + (iPTR imm)), + (To.VT (!cast(InstrStr#"rm") + To.RC:$src1, addr:$src2, + (INSERT_get_vinsert_imm To.RC:$ins)))>; + } +} + +multiclass vinsert_for_type { + + let Predicates = [HasVLX] in + defm NAME # "32x4Z256" : vinsert_for_size, + X86VectorVTInfo< 8, EltVT32, VR256X>, + vinsert128_insert, sched>, EVEX_V256; + + defm NAME # "32x4Z" : vinsert_for_size, + X86VectorVTInfo<16, EltVT32, VR512>, + vinsert128_insert, sched>, EVEX_V512; + + defm NAME # "64x4Z" : vinsert_for_size, + X86VectorVTInfo< 8, EltVT64, VR512>, + vinsert256_insert, sched>, VEX_W, EVEX_V512; + + // Even with DQI we'd like to only use these instructions for masking. + let Predicates = [HasVLX, HasDQI] in + defm NAME # "64x2Z256" : vinsert_for_size_split, + X86VectorVTInfo< 4, EltVT64, VR256X>, + null_frag, vinsert128_insert, sched>, + VEX_W1X, EVEX_V256; + + // Even with DQI we'd like to only use these instructions for masking. + let Predicates = [HasDQI] in { + defm NAME # "64x2Z" : vinsert_for_size_split, + X86VectorVTInfo< 8, EltVT64, VR512>, + null_frag, vinsert128_insert, sched>, + VEX_W, EVEX_V512; + + defm NAME # "32x8Z" : vinsert_for_size_split, + X86VectorVTInfo<16, EltVT32, VR512>, + null_frag, vinsert256_insert, sched>, + EVEX_V512; + } +} + +// FIXME: Is there a better scheduler class for VINSERTF/VINSERTI? +defm VINSERTF : vinsert_for_type; +defm VINSERTI : vinsert_for_type; + +// Codegen pattern with the alternative types, +// Even with AVX512DQ we'll still use these for unmasked operations. +defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; +defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; + +defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; +defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; + +defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info, + vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; +defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info, + vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; + +// Codegen pattern with the alternative types insert VEC128 into VEC256 +defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; +defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; +// Codegen pattern with the alternative types insert VEC128 into VEC512 +defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; +defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info, + vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; +// Codegen pattern with the alternative types insert VEC256 into VEC512 +defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info, + vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; +defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info, + vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; + + +multiclass vinsert_for_mask_cast p> { +let Predicates = p in { + def : Pat<(Cast.VT + (vselect Cast.KRCWM:$mask, + (bitconvert + (vinsert_insert:$ins (To.VT To.RC:$src1), + (From.VT From.RC:$src2), + (iPTR imm))), + Cast.RC:$src0)), + (!cast(InstrStr#"rrk") + Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2, + (INSERT_get_vinsert_imm To.RC:$ins))>; + def : Pat<(Cast.VT + (vselect Cast.KRCWM:$mask, + (bitconvert + (vinsert_insert:$ins (To.VT To.RC:$src1), + (From.VT + (bitconvert + (From.LdFrag addr:$src2))), + (iPTR imm))), + Cast.RC:$src0)), + (!cast(InstrStr#"rmk") + Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, addr:$src2, + (INSERT_get_vinsert_imm To.RC:$ins))>; + + def : Pat<(Cast.VT + (vselect Cast.KRCWM:$mask, + (bitconvert + (vinsert_insert:$ins (To.VT To.RC:$src1), + (From.VT From.RC:$src2), + (iPTR imm))), + Cast.ImmAllZerosV)), + (!cast(InstrStr#"rrkz") + Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2, + (INSERT_get_vinsert_imm To.RC:$ins))>; + def : Pat<(Cast.VT + (vselect Cast.KRCWM:$mask, + (bitconvert + (vinsert_insert:$ins (To.VT To.RC:$src1), + (From.VT + (bitconvert + (From.LdFrag addr:$src2))), + (iPTR imm))), + Cast.ImmAllZerosV)), + (!cast(InstrStr#"rmkz") + Cast.KRCWM:$mask, To.RC:$src1, addr:$src2, + (INSERT_get_vinsert_imm To.RC:$ins))>; +} +} + +defm : vinsert_for_mask_cast<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info, + v8f32x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasVLX]>; +defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v4f32x_info, v8f32x_info, + v4f64x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>; + +defm : vinsert_for_mask_cast<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info, + v8i32x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasVLX]>; +defm : vinsert_for_mask_cast<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info, + v8i32x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasVLX]>; +defm : vinsert_for_mask_cast<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info, + v8i32x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasVLX]>; +defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v4i32x_info, v8i32x_info, + v4i64x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>; +defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v8i16x_info, v16i16x_info, + v4i64x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>; +defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v16i8x_info, v32i8x_info, + v4i64x_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>; + +defm : vinsert_for_mask_cast<"VINSERTF32x4Z", v2f64x_info, v8f64_info, + v16f32_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasAVX512]>; +defm : vinsert_for_mask_cast<"VINSERTF64x2Z", v4f32x_info, v16f32_info, + v8f64_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI]>; + +defm : vinsert_for_mask_cast<"VINSERTI32x4Z", v2i64x_info, v8i64_info, + v16i32_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasAVX512]>; +defm : vinsert_for_mask_cast<"VINSERTI32x4Z", v8i16x_info, v32i16_info, + v16i32_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasAVX512]>; +defm : vinsert_for_mask_cast<"VINSERTI32x4Z", v16i8x_info, v64i8_info, + v16i32_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasAVX512]>; +defm : vinsert_for_mask_cast<"VINSERTI64x2Z", v4i32x_info, v16i32_info, + v8i64_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI]>; +defm : vinsert_for_mask_cast<"VINSERTI64x2Z", v8i16x_info, v32i16_info, + v8i64_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI]>; +defm : vinsert_for_mask_cast<"VINSERTI64x2Z", v16i8x_info, v64i8_info, + v8i64_info, vinsert128_insert, + INSERT_get_vinsert128_imm, [HasDQI]>; + +defm : vinsert_for_mask_cast<"VINSERTF32x8Z", v4f64x_info, v8f64_info, + v16f32_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasDQI]>; +defm : vinsert_for_mask_cast<"VINSERTF64x4Z", v8f32x_info, v16f32_info, + v8f64_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasAVX512]>; + +defm : vinsert_for_mask_cast<"VINSERTI32x8Z", v4i64x_info, v8i64_info, + v16i32_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasDQI]>; +defm : vinsert_for_mask_cast<"VINSERTI32x8Z", v16i16x_info, v32i16_info, + v16i32_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasDQI]>; +defm : vinsert_for_mask_cast<"VINSERTI32x8Z", v32i8x_info, v64i8_info, + v16i32_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasDQI]>; +defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v8i32x_info, v16i32_info, + v8i64_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasAVX512]>; +defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v16i16x_info, v32i16_info, + v8i64_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasAVX512]>; +defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v32i8x_info, v64i8_info, + v8i64_info, vinsert256_insert, + INSERT_get_vinsert256_imm, [HasAVX512]>; + +// vinsertps - insert f32 to XMM +let ExeDomain = SSEPackedSingle in { +def VINSERTPSZrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst), + (ins VR128X:$src1, VR128X:$src2, u8imm:$src3), + "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>, + EVEX_4V, Sched<[SchedWriteFShuffle.XMM]>; +def VINSERTPSZrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst), + (ins VR128X:$src1, f32mem:$src2, u8imm:$src3), + "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set VR128X:$dst, (X86insertps VR128X:$src1, + (v4f32 (scalar_to_vector (loadf32 addr:$src2))), + imm:$src3))]>, + EVEX_4V, EVEX_CD8<32, CD8VT1>, + Sched<[SchedWriteFShuffle.XMM.Folded, ReadAfterLd]>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 VECTOR EXTRACT +//--- + +// Supports two different pattern operators for mask and unmasked ops. Allows +// null_frag to be passed for one. +multiclass vextract_for_size_split { + + let hasSideEffects = 0, ExeDomain = To.ExeDomain in { + defm rr : AVX512_maskable_split, + AVX512AIi8Base, EVEX, Sched<[SchedRR]>; + + def mr : AVX512AIi8, EVEX, + Sched<[SchedMR]>; + + let mayStore = 1, hasSideEffects = 0 in + def mrk : AVX512AIi8, + EVEX_K, EVEX, Sched<[SchedMR]>, NotMemoryFoldable; + } +} + +// Passes the same pattern operator for masked and unmasked ops. +multiclass vextract_for_size : + vextract_for_size_split; + +// Codegen pattern for the alternative types +multiclass vextract_for_size_lowering p> { + let Predicates = p in { + def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)), + (To.VT (!cast(InstrStr#"rr") + From.RC:$src1, + (EXTRACT_get_vextract_imm To.RC:$ext)))>; + def : Pat<(store (To.VT (vextract_extract:$ext (From.VT From.RC:$src1), + (iPTR imm))), addr:$dst), + (!cast(InstrStr#"mr") addr:$dst, From.RC:$src1, + (EXTRACT_get_vextract_imm To.RC:$ext))>; + } +} + +multiclass vextract_for_type { + let Predicates = [HasAVX512] in { + defm NAME # "32x4Z" : vextract_for_size, + X86VectorVTInfo< 4, EltVT32, VR128X>, + vextract128_extract, SchedRR, SchedMR>, + EVEX_V512, EVEX_CD8<32, CD8VT4>; + defm NAME # "64x4Z" : vextract_for_size, + X86VectorVTInfo< 4, EltVT64, VR256X>, + vextract256_extract, SchedRR, SchedMR>, + VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>; + } + let Predicates = [HasVLX] in + defm NAME # "32x4Z256" : vextract_for_size, + X86VectorVTInfo< 4, EltVT32, VR128X>, + vextract128_extract, SchedRR, SchedMR>, + EVEX_V256, EVEX_CD8<32, CD8VT4>; + + // Even with DQI we'd like to only use these instructions for masking. + let Predicates = [HasVLX, HasDQI] in + defm NAME # "64x2Z256" : vextract_for_size_split, + X86VectorVTInfo< 2, EltVT64, VR128X>, + null_frag, vextract128_extract, SchedRR, SchedMR>, + VEX_W1X, EVEX_V256, EVEX_CD8<64, CD8VT2>; + + // Even with DQI we'd like to only use these instructions for masking. + let Predicates = [HasDQI] in { + defm NAME # "64x2Z" : vextract_for_size_split, + X86VectorVTInfo< 2, EltVT64, VR128X>, + null_frag, vextract128_extract, SchedRR, SchedMR>, + VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>; + defm NAME # "32x8Z" : vextract_for_size_split, + X86VectorVTInfo< 8, EltVT32, VR256X>, + null_frag, vextract256_extract, SchedRR, SchedMR>, + EVEX_V512, EVEX_CD8<32, CD8VT8>; + } +} + +// TODO - replace WriteFStore/WriteVecStore with X86SchedWriteMoveLSWidths types. +defm VEXTRACTF : vextract_for_type; +defm VEXTRACTI : vextract_for_type; + +// extract_subvector codegen patterns with the alternative types. +// Even with AVX512DQ we'll still use these for unmasked operations. +defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; +defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; + +defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info, + vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; +defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info, + vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; + +defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; +defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; + +// Codegen pattern with the alternative types extract VEC128 from VEC256 +defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v16i16x_info, v8i16x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; +defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v32i8x_info, v16i8x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; + +// Codegen pattern with the alternative types extract VEC128 from VEC512 +defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; +defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info, + vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; +// Codegen pattern with the alternative types extract VEC256 from VEC512 +defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info, + vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; +defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info, + vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; + + +// A 128-bit extract from bits [255:128] of a 512-bit vector should use a +// smaller extract to enable EVEX->VEX. +let Predicates = [NoVLX] in { +def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))), + (v2i64 (VEXTRACTI128rr + (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))), + (v2f64 (VEXTRACTF128rr + (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))), + (v4i32 (VEXTRACTI128rr + (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))), + (v4f32 (VEXTRACTF128rr + (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))), + (v8i16 (VEXTRACTI128rr + (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))), + (v16i8 (VEXTRACTI128rr + (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)), + (iPTR 1)))>; +} + +// A 128-bit extract from bits [255:128] of a 512-bit vector should use a +// smaller extract to enable EVEX->VEX. +let Predicates = [HasVLX] in { +def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))), + (v2i64 (VEXTRACTI32x4Z256rr + (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))), + (v2f64 (VEXTRACTF32x4Z256rr + (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))), + (v4i32 (VEXTRACTI32x4Z256rr + (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))), + (v4f32 (VEXTRACTF32x4Z256rr + (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))), + (v8i16 (VEXTRACTI32x4Z256rr + (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)), + (iPTR 1)))>; +def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))), + (v16i8 (VEXTRACTI32x4Z256rr + (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)), + (iPTR 1)))>; +} + + +// Additional patterns for handling a bitcast between the vselect and the +// extract_subvector. +multiclass vextract_for_mask_cast p> { +let Predicates = p in { + def : Pat<(Cast.VT (vselect Cast.KRCWM:$mask, + (bitconvert + (To.VT (vextract_extract:$ext + (From.VT From.RC:$src), (iPTR imm)))), + To.RC:$src0)), + (Cast.VT (!cast(InstrStr#"rrk") + Cast.RC:$src0, Cast.KRCWM:$mask, From.RC:$src, + (EXTRACT_get_vextract_imm To.RC:$ext)))>; + + def : Pat<(Cast.VT (vselect Cast.KRCWM:$mask, + (bitconvert + (To.VT (vextract_extract:$ext + (From.VT From.RC:$src), (iPTR imm)))), + Cast.ImmAllZerosV)), + (Cast.VT (!cast(InstrStr#"rrkz") + Cast.KRCWM:$mask, From.RC:$src, + (EXTRACT_get_vextract_imm To.RC:$ext)))>; +} +} + +defm : vextract_for_mask_cast<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info, + v4f32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasVLX]>; +defm : vextract_for_mask_cast<"VEXTRACTF64x2Z256", v8f32x_info, v4f32x_info, + v2f64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI, HasVLX]>; + +defm : vextract_for_mask_cast<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info, + v4i32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasVLX]>; +defm : vextract_for_mask_cast<"VEXTRACTI32x4Z256", v16i16x_info, v8i16x_info, + v4i32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasVLX]>; +defm : vextract_for_mask_cast<"VEXTRACTI32x4Z256", v32i8x_info, v16i8x_info, + v4i32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasVLX]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x2Z256", v8i32x_info, v4i32x_info, + v2i64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI, HasVLX]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x2Z256", v16i16x_info, v8i16x_info, + v2i64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI, HasVLX]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x2Z256", v32i8x_info, v16i8x_info, + v2i64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI, HasVLX]>; + +defm : vextract_for_mask_cast<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info, + v4f32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasAVX512]>; +defm : vextract_for_mask_cast<"VEXTRACTF64x2Z", v16f32_info, v4f32x_info, + v2f64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI]>; + +defm : vextract_for_mask_cast<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info, + v4i32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasAVX512]>; +defm : vextract_for_mask_cast<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info, + v4i32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasAVX512]>; +defm : vextract_for_mask_cast<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info, + v4i32x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasAVX512]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x2Z", v16i32_info, v4i32x_info, + v2i64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x2Z", v32i16_info, v8i16x_info, + v2i64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x2Z", v64i8_info, v16i8x_info, + v2i64x_info, vextract128_extract, + EXTRACT_get_vextract128_imm, [HasDQI]>; + +defm : vextract_for_mask_cast<"VEXTRACTF32x8Z", v8f64_info, v4f64x_info, + v8f32x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasDQI]>; +defm : vextract_for_mask_cast<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info, + v4f64x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasAVX512]>; + +defm : vextract_for_mask_cast<"VEXTRACTI32x8Z", v8i64_info, v4i64x_info, + v8i32x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasDQI]>; +defm : vextract_for_mask_cast<"VEXTRACTI32x8Z", v32i16_info, v16i16x_info, + v8i32x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasDQI]>; +defm : vextract_for_mask_cast<"VEXTRACTI32x8Z", v64i8_info, v32i8x_info, + v8i32x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasDQI]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info, + v4i64x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasAVX512]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info, + v4i64x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasAVX512]>; +defm : vextract_for_mask_cast<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info, + v4i64x_info, vextract256_extract, + EXTRACT_get_vextract256_imm, [HasAVX512]>; + +// vextractps - extract 32 bits from XMM +def VEXTRACTPSZrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst), + (ins VR128X:$src1, u8imm:$src2), + "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>, + EVEX, VEX_WIG, Sched<[WriteVecExtract]>; + +def VEXTRACTPSZmr : AVX512AIi8<0x17, MRMDestMem, (outs), + (ins f32mem:$dst, VR128X:$src1, u8imm:$src2), + "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2), + addr:$dst)]>, + EVEX, VEX_WIG, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecExtractSt]>; + +//===---------------------------------------------------------------------===// +// AVX-512 BROADCAST +//--- +// broadcast with a scalar argument. +multiclass avx512_broadcast_scalar opc, string OpcodeStr, + string Name, + X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> { + def : Pat<(DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)), + (!cast(Name#DestInfo.ZSuffix#r) + (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>; + def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask, + (X86VBroadcast SrcInfo.FRC:$src), + DestInfo.RC:$src0)), + (!cast(Name#DestInfo.ZSuffix#rk) + DestInfo.RC:$src0, DestInfo.KRCWM:$mask, + (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>; + def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask, + (X86VBroadcast SrcInfo.FRC:$src), + DestInfo.ImmAllZerosV)), + (!cast(Name#DestInfo.ZSuffix#rkz) + DestInfo.KRCWM:$mask, (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>; +} + +// Split version to allow mask and broadcast node to be different types. This +// helps support the 32x2 broadcasts. +multiclass avx512_broadcast_rm_split opc, string OpcodeStr, + string Name, + SchedWrite SchedRR, SchedWrite SchedRM, + X86VectorVTInfo MaskInfo, + X86VectorVTInfo DestInfo, + X86VectorVTInfo SrcInfo, + SDPatternOperator UnmaskedOp = X86VBroadcast> { + let ExeDomain = DestInfo.ExeDomain, hasSideEffects = 0 in { + defm r : AVX512_maskable_split, + T8PD, EVEX, Sched<[SchedRR]>; + let mayLoad = 1 in + defm m : AVX512_maskable_split, + T8PD, EVEX, EVEX_CD8, + Sched<[SchedRM]>; + } + + def : Pat<(MaskInfo.VT + (bitconvert + (DestInfo.VT (UnmaskedOp + (SrcInfo.VT (scalar_to_vector + (SrcInfo.ScalarLdFrag addr:$src))))))), + (!cast(Name#MaskInfo.ZSuffix#m) addr:$src)>; + def : Pat<(MaskInfo.VT (vselect MaskInfo.KRCWM:$mask, + (bitconvert + (DestInfo.VT + (X86VBroadcast + (SrcInfo.VT (scalar_to_vector + (SrcInfo.ScalarLdFrag addr:$src)))))), + MaskInfo.RC:$src0)), + (!cast(Name#DestInfo.ZSuffix#mk) + MaskInfo.RC:$src0, MaskInfo.KRCWM:$mask, addr:$src)>; + def : Pat<(MaskInfo.VT (vselect MaskInfo.KRCWM:$mask, + (bitconvert + (DestInfo.VT + (X86VBroadcast + (SrcInfo.VT (scalar_to_vector + (SrcInfo.ScalarLdFrag addr:$src)))))), + MaskInfo.ImmAllZerosV)), + (!cast(Name#MaskInfo.ZSuffix#mkz) + MaskInfo.KRCWM:$mask, addr:$src)>; +} + +// Helper class to force mask and broadcast result to same type. +multiclass avx512_broadcast_rm opc, string OpcodeStr, string Name, + SchedWrite SchedRR, SchedWrite SchedRM, + X86VectorVTInfo DestInfo, + X86VectorVTInfo SrcInfo> : + avx512_broadcast_rm_split; + +multiclass avx512_fp_broadcast_sd opc, string OpcodeStr, + AVX512VLVectorVTInfo _> { + let Predicates = [HasAVX512] in { + defm Z : avx512_broadcast_rm, + avx512_broadcast_scalar, + EVEX_V512; + } + + let Predicates = [HasVLX] in { + defm Z256 : avx512_broadcast_rm, + avx512_broadcast_scalar, + EVEX_V256; + } +} + +multiclass avx512_fp_broadcast_ss opc, string OpcodeStr, + AVX512VLVectorVTInfo _> { + let Predicates = [HasAVX512] in { + defm Z : avx512_broadcast_rm, + avx512_broadcast_scalar, + EVEX_V512; + } + + let Predicates = [HasVLX] in { + defm Z256 : avx512_broadcast_rm, + avx512_broadcast_scalar, + EVEX_V256; + defm Z128 : avx512_broadcast_rm, + avx512_broadcast_scalar, + EVEX_V128; + } +} +defm VBROADCASTSS : avx512_fp_broadcast_ss<0x18, "vbroadcastss", + avx512vl_f32_info>; +defm VBROADCASTSD : avx512_fp_broadcast_sd<0x19, "vbroadcastsd", + avx512vl_f64_info>, VEX_W1X; + +multiclass avx512_int_broadcast_reg opc, SchedWrite SchedRR, + X86VectorVTInfo _, SDPatternOperator OpNode, + RegisterClass SrcRC> { + let ExeDomain = _.ExeDomain in + defm r : AVX512_maskable, T8PD, EVEX, + Sched<[SchedRR]>; +} + +multiclass avx512_int_broadcastbw_reg opc, string Name, SchedWrite SchedRR, + X86VectorVTInfo _, SDPatternOperator OpNode, + RegisterClass SrcRC, SubRegIndex Subreg> { + let hasSideEffects = 0, ExeDomain = _.ExeDomain in + defm r : AVX512_maskable_custom, T8PD, EVEX, Sched<[SchedRR]>; + + def : Pat <(_.VT (OpNode SrcRC:$src)), + (!cast(Name#r) + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>; + + def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.RC:$src0), + (!cast(Name#rk) _.RC:$src0, _.KRCWM:$mask, + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>; + + def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.ImmAllZerosV), + (!cast(Name#rkz) _.KRCWM:$mask, + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>; +} + +multiclass avx512_int_broadcastbw_reg_vl opc, string Name, + AVX512VLVectorVTInfo _, SDPatternOperator OpNode, + RegisterClass SrcRC, SubRegIndex Subreg, Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_int_broadcastbw_reg, EVEX_V512; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_int_broadcastbw_reg, EVEX_V256; + defm Z128 : avx512_int_broadcastbw_reg, EVEX_V128; + } +} + +multiclass avx512_int_broadcast_reg_vl opc, AVX512VLVectorVTInfo _, + SDPatternOperator OpNode, + RegisterClass SrcRC, Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_int_broadcast_reg, EVEX_V512; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_int_broadcast_reg, EVEX_V256; + defm Z128 : avx512_int_broadcast_reg, EVEX_V128; + } +} + +defm VPBROADCASTBr : avx512_int_broadcastbw_reg_vl<0x7A, "VPBROADCASTBr", + avx512vl_i8_info, X86VBroadcast, GR8, sub_8bit, HasBWI>; +defm VPBROADCASTWr : avx512_int_broadcastbw_reg_vl<0x7B, "VPBROADCASTWr", + avx512vl_i16_info, X86VBroadcast, GR16, sub_16bit, + HasBWI>; +defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, + X86VBroadcast, GR32, HasAVX512>; +defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, + X86VBroadcast, GR64, HasAVX512>, VEX_W; + +// Provide aliases for broadcast from the same register class that +// automatically does the extract. +multiclass avx512_int_broadcast_rm_lowering { + def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))), + (!cast(Name#DestInfo.ZSuffix#"r") + (ExtInfo.VT (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm)))>; +} + +multiclass avx512_int_broadcast_rm_vl opc, string OpcodeStr, + AVX512VLVectorVTInfo _, Predicate prd> { + let Predicates = [prd] in { + defm Z : avx512_broadcast_rm, + avx512_int_broadcast_rm_lowering, + EVEX_V512; + // Defined separately to avoid redefinition. + defm Z_Alt : avx512_int_broadcast_rm_lowering; + } + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_broadcast_rm, + avx512_int_broadcast_rm_lowering, + EVEX_V256; + defm Z128 : avx512_broadcast_rm, + EVEX_V128; + } +} + +defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb", + avx512vl_i8_info, HasBWI>; +defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw", + avx512vl_i16_info, HasBWI>; +defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd", + avx512vl_i32_info, HasAVX512>; +defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq", + avx512vl_i64_info, HasAVX512>, VEX_W1X; + +multiclass avx512_subvec_broadcast_rm opc, string OpcodeStr, + X86VectorVTInfo _Dst, X86VectorVTInfo _Src> { + defm rm : AVX512_maskable, + Sched<[SchedWriteShuffle.YMM.Folded]>, + AVX5128IBase, EVEX; +} + +// This should be used for the AVX512DQ broadcast instructions. It disables +// the unmasked patterns so that we only use the DQ instructions when masking +// is requested. +multiclass avx512_subvec_broadcast_rm_dq opc, string OpcodeStr, + X86VectorVTInfo _Dst, X86VectorVTInfo _Src> { + let hasSideEffects = 0, mayLoad = 1 in + defm rm : AVX512_maskable_split, + Sched<[SchedWriteShuffle.YMM.Folded]>, + AVX5128IBase, EVEX; +} + +let Predicates = [HasAVX512] in { + // 32-bit targets will fail to load a i64 directly but can use ZEXT_LOAD. + def : Pat<(v8i64 (X86VBroadcast (v8i64 (X86vzload addr:$src)))), + (VPBROADCASTQZm addr:$src)>; +} + +let Predicates = [HasVLX] in { + // 32-bit targets will fail to load a i64 directly but can use ZEXT_LOAD. + def : Pat<(v2i64 (X86VBroadcast (v2i64 (X86vzload addr:$src)))), + (VPBROADCASTQZ128m addr:$src)>; + def : Pat<(v4i64 (X86VBroadcast (v4i64 (X86vzload addr:$src)))), + (VPBROADCASTQZ256m addr:$src)>; +} +let Predicates = [HasVLX, HasBWI] in { + // loadi16 is tricky to fold, because !isTypeDesirableForOp, justifiably. + // This means we'll encounter truncated i32 loads; match that here. + def : Pat<(v8i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))), + (VPBROADCASTWZ128m addr:$src)>; + def : Pat<(v16i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))), + (VPBROADCASTWZ256m addr:$src)>; + def : Pat<(v8i16 (X86VBroadcast + (i16 (trunc (i32 (zextloadi16 addr:$src)))))), + (VPBROADCASTWZ128m addr:$src)>; + def : Pat<(v16i16 (X86VBroadcast + (i16 (trunc (i32 (zextloadi16 addr:$src)))))), + (VPBROADCASTWZ256m addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 BROADCAST SUBVECTORS +// + +defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4", + v16i32_info, v4i32x_info>, + EVEX_V512, EVEX_CD8<32, CD8VT4>; +defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4", + v16f32_info, v4f32x_info>, + EVEX_V512, EVEX_CD8<32, CD8VT4>; +defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4", + v8i64_info, v4i64x_info>, VEX_W, + EVEX_V512, EVEX_CD8<64, CD8VT4>; +defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4", + v8f64_info, v4f64x_info>, VEX_W, + EVEX_V512, EVEX_CD8<64, CD8VT4>; + +let Predicates = [HasAVX512] in { +def : Pat<(v16f32 (X86SubVBroadcast (loadv8f32 addr:$src))), + (VBROADCASTF64X4rm addr:$src)>; +def : Pat<(v16i32 (X86SubVBroadcast (bc_v8i32 (loadv4i64 addr:$src)))), + (VBROADCASTI64X4rm addr:$src)>; +def : Pat<(v32i16 (X86SubVBroadcast (bc_v16i16 (loadv4i64 addr:$src)))), + (VBROADCASTI64X4rm addr:$src)>; +def : Pat<(v64i8 (X86SubVBroadcast (bc_v32i8 (loadv4i64 addr:$src)))), + (VBROADCASTI64X4rm addr:$src)>; + +// Provide fallback in case the load node that is used in the patterns above +// is used by additional users, which prevents the pattern selection. +def : Pat<(v8f64 (X86SubVBroadcast (v4f64 VR256X:$src))), + (VINSERTF64x4Zrr (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (v4f64 VR256X:$src), 1)>; +def : Pat<(v16f32 (X86SubVBroadcast (v8f32 VR256X:$src))), + (VINSERTF64x4Zrr (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (v8f32 VR256X:$src), 1)>; +def : Pat<(v8i64 (X86SubVBroadcast (v4i64 VR256X:$src))), + (VINSERTI64x4Zrr (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (v4i64 VR256X:$src), 1)>; +def : Pat<(v16i32 (X86SubVBroadcast (v8i32 VR256X:$src))), + (VINSERTI64x4Zrr (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (v8i32 VR256X:$src), 1)>; +def : Pat<(v32i16 (X86SubVBroadcast (v16i16 VR256X:$src))), + (VINSERTI64x4Zrr (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (v16i16 VR256X:$src), 1)>; +def : Pat<(v64i8 (X86SubVBroadcast (v32i8 VR256X:$src))), + (VINSERTI64x4Zrr (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (v32i8 VR256X:$src), 1)>; + +def : Pat<(v8f64 (X86SubVBroadcast (loadv2f64 addr:$src))), + (VBROADCASTF32X4rm addr:$src)>; +def : Pat<(v8i64 (X86SubVBroadcast (loadv2i64 addr:$src))), + (VBROADCASTI32X4rm addr:$src)>; +def : Pat<(v32i16 (X86SubVBroadcast (bc_v8i16 (loadv2i64 addr:$src)))), + (VBROADCASTI32X4rm addr:$src)>; +def : Pat<(v64i8 (X86SubVBroadcast (bc_v16i8 (loadv2i64 addr:$src)))), + (VBROADCASTI32X4rm addr:$src)>; + +// Patterns for selects of bitcasted operations. +def : Pat<(vselect VK16WM:$mask, + (bc_v16f32 (v8f64 (X86SubVBroadcast (loadv2f64 addr:$src)))), + (bc_v16f32 (v16i32 immAllZerosV))), + (VBROADCASTF32X4rmkz VK16WM:$mask, addr:$src)>; +def : Pat<(vselect VK16WM:$mask, + (bc_v16f32 (v8f64 (X86SubVBroadcast (loadv2f64 addr:$src)))), + VR512:$src0), + (VBROADCASTF32X4rmk VR512:$src0, VK16WM:$mask, addr:$src)>; +def : Pat<(vselect VK16WM:$mask, + (bc_v16i32 (v8i64 (X86SubVBroadcast (loadv2i64 addr:$src)))), + (v16i32 immAllZerosV)), + (VBROADCASTI32X4rmkz VK16WM:$mask, addr:$src)>; +def : Pat<(vselect VK16WM:$mask, + (bc_v16i32 (v8i64 (X86SubVBroadcast (loadv2i64 addr:$src)))), + VR512:$src0), + (VBROADCASTI32X4rmk VR512:$src0, VK16WM:$mask, addr:$src)>; + +def : Pat<(vselect VK8WM:$mask, + (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv8f32 addr:$src)))), + (bc_v8f64 (v16i32 immAllZerosV))), + (VBROADCASTF64X4rmkz VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv8f32 addr:$src)))), + VR512:$src0), + (VBROADCASTF64X4rmk VR512:$src0, VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8i64 (v16i32 (X86SubVBroadcast (bc_v8i32 (loadv4i64 addr:$src))))), + (bc_v8i64 (v16i32 immAllZerosV))), + (VBROADCASTI64X4rmkz VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8i64 (v16i32 (X86SubVBroadcast (bc_v8i32 (loadv4i64 addr:$src))))), + VR512:$src0), + (VBROADCASTI64X4rmk VR512:$src0, VK8WM:$mask, addr:$src)>; +} + +let Predicates = [HasVLX] in { +defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4", + v8i32x_info, v4i32x_info>, + EVEX_V256, EVEX_CD8<32, CD8VT4>; +defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4", + v8f32x_info, v4f32x_info>, + EVEX_V256, EVEX_CD8<32, CD8VT4>; + +def : Pat<(v4f64 (X86SubVBroadcast (loadv2f64 addr:$src))), + (VBROADCASTF32X4Z256rm addr:$src)>; +def : Pat<(v4i64 (X86SubVBroadcast (loadv2i64 addr:$src))), + (VBROADCASTI32X4Z256rm addr:$src)>; +def : Pat<(v16i16 (X86SubVBroadcast (bc_v8i16 (loadv2i64 addr:$src)))), + (VBROADCASTI32X4Z256rm addr:$src)>; +def : Pat<(v32i8 (X86SubVBroadcast (bc_v16i8 (loadv2i64 addr:$src)))), + (VBROADCASTI32X4Z256rm addr:$src)>; + +// Patterns for selects of bitcasted operations. +def : Pat<(vselect VK8WM:$mask, + (bc_v8f32 (v4f64 (X86SubVBroadcast (loadv2f64 addr:$src)))), + (bc_v8f32 (v8i32 immAllZerosV))), + (VBROADCASTF32X4Z256rmkz VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8f32 (v4f64 (X86SubVBroadcast (loadv2f64 addr:$src)))), + VR256X:$src0), + (VBROADCASTF32X4Z256rmk VR256X:$src0, VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8i32 (v4i64 (X86SubVBroadcast (loadv2i64 addr:$src)))), + (v8i32 immAllZerosV)), + (VBROADCASTI32X4Z256rmkz VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8i32 (v4i64 (X86SubVBroadcast (loadv2i64 addr:$src)))), + VR256X:$src0), + (VBROADCASTI32X4Z256rmk VR256X:$src0, VK8WM:$mask, addr:$src)>; + + +// Provide fallback in case the load node that is used in the patterns above +// is used by additional users, which prevents the pattern selection. +def : Pat<(v4f64 (X86SubVBroadcast (v2f64 VR128X:$src))), + (VINSERTF32x4Z256rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (v2f64 VR128X:$src), 1)>; +def : Pat<(v8f32 (X86SubVBroadcast (v4f32 VR128X:$src))), + (VINSERTF32x4Z256rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (v4f32 VR128X:$src), 1)>; +def : Pat<(v4i64 (X86SubVBroadcast (v2i64 VR128X:$src))), + (VINSERTI32x4Z256rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (v2i64 VR128X:$src), 1)>; +def : Pat<(v8i32 (X86SubVBroadcast (v4i32 VR128X:$src))), + (VINSERTI32x4Z256rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (v4i32 VR128X:$src), 1)>; +def : Pat<(v16i16 (X86SubVBroadcast (v8i16 VR128X:$src))), + (VINSERTI32x4Z256rr (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (v8i16 VR128X:$src), 1)>; +def : Pat<(v32i8 (X86SubVBroadcast (v16i8 VR128X:$src))), + (VINSERTI32x4Z256rr (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (v16i8 VR128X:$src), 1)>; +} + +let Predicates = [HasVLX, HasDQI] in { +defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm_dq<0x5a, "vbroadcasti64x2", + v4i64x_info, v2i64x_info>, VEX_W1X, + EVEX_V256, EVEX_CD8<64, CD8VT2>; +defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm_dq<0x1a, "vbroadcastf64x2", + v4f64x_info, v2f64x_info>, VEX_W1X, + EVEX_V256, EVEX_CD8<64, CD8VT2>; + +// Patterns for selects of bitcasted operations. +def : Pat<(vselect VK4WM:$mask, + (bc_v4f64 (v8f32 (X86SubVBroadcast (loadv4f32 addr:$src)))), + (bc_v4f64 (v8i32 immAllZerosV))), + (VBROADCASTF64X2Z128rmkz VK4WM:$mask, addr:$src)>; +def : Pat<(vselect VK4WM:$mask, + (bc_v4f64 (v8f32 (X86SubVBroadcast (loadv4f32 addr:$src)))), + VR256X:$src0), + (VBROADCASTF64X2Z128rmk VR256X:$src0, VK4WM:$mask, addr:$src)>; +def : Pat<(vselect VK4WM:$mask, + (bc_v4i64 (v8i32 (X86SubVBroadcast (bc_v4i32 (loadv2i64 addr:$src))))), + (bc_v4i64 (v8i32 immAllZerosV))), + (VBROADCASTI64X2Z128rmkz VK4WM:$mask, addr:$src)>; +def : Pat<(vselect VK4WM:$mask, + (bc_v4i64 (v8i32 (X86SubVBroadcast (bc_v4i32 (loadv2i64 addr:$src))))), + VR256X:$src0), + (VBROADCASTI64X2Z128rmk VR256X:$src0, VK4WM:$mask, addr:$src)>; +} + +let Predicates = [HasDQI] in { +defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm_dq<0x5a, "vbroadcasti64x2", + v8i64_info, v2i64x_info>, VEX_W, + EVEX_V512, EVEX_CD8<64, CD8VT2>; +defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm_dq<0x5b, "vbroadcasti32x8", + v16i32_info, v8i32x_info>, + EVEX_V512, EVEX_CD8<32, CD8VT8>; +defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm_dq<0x1a, "vbroadcastf64x2", + v8f64_info, v2f64x_info>, VEX_W, + EVEX_V512, EVEX_CD8<64, CD8VT2>; +defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm_dq<0x1b, "vbroadcastf32x8", + v16f32_info, v8f32x_info>, + EVEX_V512, EVEX_CD8<32, CD8VT8>; + +// Patterns for selects of bitcasted operations. +def : Pat<(vselect VK16WM:$mask, + (bc_v16f32 (v8f64 (X86SubVBroadcast (loadv4f64 addr:$src)))), + (bc_v16f32 (v16i32 immAllZerosV))), + (VBROADCASTF32X8rmkz VK16WM:$mask, addr:$src)>; +def : Pat<(vselect VK16WM:$mask, + (bc_v16f32 (v8f64 (X86SubVBroadcast (loadv4f64 addr:$src)))), + VR512:$src0), + (VBROADCASTF32X8rmk VR512:$src0, VK16WM:$mask, addr:$src)>; +def : Pat<(vselect VK16WM:$mask, + (bc_v16i32 (v8i64 (X86SubVBroadcast (loadv4i64 addr:$src)))), + (v16i32 immAllZerosV)), + (VBROADCASTI32X8rmkz VK16WM:$mask, addr:$src)>; +def : Pat<(vselect VK16WM:$mask, + (bc_v16i32 (v8i64 (X86SubVBroadcast (loadv4i64 addr:$src)))), + VR512:$src0), + (VBROADCASTI32X8rmk VR512:$src0, VK16WM:$mask, addr:$src)>; + +def : Pat<(vselect VK8WM:$mask, + (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv4f32 addr:$src)))), + (bc_v8f64 (v16i32 immAllZerosV))), + (VBROADCASTF64X2rmkz VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv4f32 addr:$src)))), + VR512:$src0), + (VBROADCASTF64X2rmk VR512:$src0, VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8i64 (v16i32 (X86SubVBroadcast (bc_v4i32 (loadv2i64 addr:$src))))), + (bc_v8i64 (v16i32 immAllZerosV))), + (VBROADCASTI64X2rmkz VK8WM:$mask, addr:$src)>; +def : Pat<(vselect VK8WM:$mask, + (bc_v8i64 (v16i32 (X86SubVBroadcast (bc_v4i32 (loadv2i64 addr:$src))))), + VR512:$src0), + (VBROADCASTI64X2rmk VR512:$src0, VK8WM:$mask, addr:$src)>; +} + +multiclass avx512_common_broadcast_32x2 opc, string OpcodeStr, + AVX512VLVectorVTInfo _Dst, AVX512VLVectorVTInfo _Src> { + let Predicates = [HasDQI] in + defm Z : avx512_broadcast_rm_split, + EVEX_V512; + let Predicates = [HasDQI, HasVLX] in + defm Z256 : avx512_broadcast_rm_split, + EVEX_V256; +} + +multiclass avx512_common_broadcast_i32x2 opc, string OpcodeStr, + AVX512VLVectorVTInfo _Dst, AVX512VLVectorVTInfo _Src> : + avx512_common_broadcast_32x2 { + + let Predicates = [HasDQI, HasVLX] in + defm Z128 : avx512_broadcast_rm_split, + EVEX_V128; +} + +defm VBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2", + avx512vl_i32_info, avx512vl_i64_info>; +defm VBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2", + avx512vl_f32_info, avx512vl_f64_info>; + +let Predicates = [HasVLX] in { +def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256X:$src))), + (VBROADCASTSSZ256r (v4f32 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)))>; +def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256X:$src))), + (VBROADCASTSDZ256r (v2f64 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)))>; +} + +def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))), + (VBROADCASTSSZr (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm)))>; +def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))), + (VBROADCASTSSZr (v4f32 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)))>; + +def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))), + (VBROADCASTSDZr (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm)))>; +def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))), + (VBROADCASTSDZr (v2f64 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)))>; + +//===----------------------------------------------------------------------===// +// AVX-512 BROADCAST MASK TO VECTOR REGISTER +//--- +multiclass avx512_mask_broadcastm opc, string OpcodeStr, + X86VectorVTInfo _, RegisterClass KRC> { + def rr : AVX512XS8I, + EVEX, Sched<[WriteShuffle]>; +} + +multiclass avx512_mask_broadcast opc, string OpcodeStr, + AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> { + let Predicates = [HasCDI] in + defm Z : avx512_mask_broadcastm, EVEX_V512; + let Predicates = [HasCDI, HasVLX] in { + defm Z256 : avx512_mask_broadcastm, EVEX_V256; + defm Z128 : avx512_mask_broadcastm, EVEX_V128; + } +} + +defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", + avx512vl_i32_info, VK16>; +defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", + avx512vl_i64_info, VK8>, VEX_W; + +//===----------------------------------------------------------------------===// +// -- VPERMI2 - 3 source operands form -- +multiclass avx512_perm_i opc, string OpcodeStr, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, X86VectorVTInfo IdxVT> { +let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, + hasSideEffects = 0 in { + defm rr: AVX512_maskable_3src_cast, + EVEX_4V, AVX5128IBase, Sched<[sched]>; + + let mayLoad = 1 in + defm rm: AVX512_maskable_3src_cast, + EVEX_4V, AVX5128IBase, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_perm_i_mb opc, string OpcodeStr, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, X86VectorVTInfo IdxVT> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, + hasSideEffects = 0, mayLoad = 1 in + defm rmb: AVX512_maskable_3src_cast, + AVX5128IBase, EVEX_4V, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_perm_i_sizes opc, string OpcodeStr, + X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTInfo, + AVX512VLVectorVTInfo ShuffleMask> { + defm NAME: avx512_perm_i, + avx512_perm_i_mb, EVEX_V512; + let Predicates = [HasVLX] in { + defm NAME#128: avx512_perm_i, + avx512_perm_i_mb, EVEX_V128; + defm NAME#256: avx512_perm_i, + avx512_perm_i_mb, EVEX_V256; + } +} + +multiclass avx512_perm_i_sizes_bw opc, string OpcodeStr, + X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTInfo, + AVX512VLVectorVTInfo Idx, + Predicate Prd> { + let Predicates = [Prd] in + defm NAME: avx512_perm_i, EVEX_V512; + let Predicates = [Prd, HasVLX] in { + defm NAME#128: avx512_perm_i, EVEX_V128; + defm NAME#256: avx512_perm_i, EVEX_V256; + } +} + +defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d", WriteVarShuffle256, + avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; +defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q", WriteVarShuffle256, + avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; +defm VPERMI2W : avx512_perm_i_sizes_bw<0x75, "vpermi2w", WriteVarShuffle256, + avx512vl_i16_info, avx512vl_i16_info, HasBWI>, + VEX_W, EVEX_CD8<16, CD8VF>; +defm VPERMI2B : avx512_perm_i_sizes_bw<0x75, "vpermi2b", WriteVarShuffle256, + avx512vl_i8_info, avx512vl_i8_info, HasVBMI>, + EVEX_CD8<8, CD8VF>; +defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps", WriteFVarShuffle256, + avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; +defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd", WriteFVarShuffle256, + avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; + +// Extra patterns to deal with extra bitcasts due to passthru and index being +// different types on the fp versions. +multiclass avx512_perm_i_lowering { + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86VPermt2 (_.VT _.RC:$src2), + (IdxVT.VT (bitconvert (CastVT.VT _.RC:$src1))), _.RC:$src3), + (_.VT (bitconvert (CastVT.VT _.RC:$src1))))), + (!cast(InstrStr#"rrk") _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, _.RC:$src3)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86VPermt2 _.RC:$src2, + (IdxVT.VT (bitconvert (CastVT.VT _.RC:$src1))), + (_.LdFrag addr:$src3)), + (_.VT (bitconvert (CastVT.VT _.RC:$src1))))), + (!cast(InstrStr#"rmk") _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86VPermt2 _.RC:$src2, + (IdxVT.VT (bitconvert (CastVT.VT _.RC:$src1))), + (X86VBroadcast (_.ScalarLdFrag addr:$src3))), + (_.VT (bitconvert (CastVT.VT _.RC:$src1))))), + (!cast(InstrStr#"rmbk") _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3)>; +} + +// TODO: Should we add more casts? The vXi64 case is common due to ABI. +defm : avx512_perm_i_lowering<"VPERMI2PS", v16f32_info, v16i32_info, v8i64_info>; +defm : avx512_perm_i_lowering<"VPERMI2PS256", v8f32x_info, v8i32x_info, v4i64x_info>; +defm : avx512_perm_i_lowering<"VPERMI2PS128", v4f32x_info, v4i32x_info, v2i64x_info>; + +// VPERMT2 +multiclass avx512_perm_t opc, string OpcodeStr, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, X86VectorVTInfo IdxVT> { +let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { + defm rr: AVX512_maskable_3src, + EVEX_4V, AVX5128IBase, Sched<[sched]>; + + defm rm: AVX512_maskable_3src, + EVEX_4V, AVX5128IBase, Sched<[sched.Folded, ReadAfterLd]>; + } +} +multiclass avx512_perm_t_mb opc, string OpcodeStr, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, X86VectorVTInfo IdxVT> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in + defm rmb: AVX512_maskable_3src, + AVX5128IBase, EVEX_4V, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_perm_t_sizes opc, string OpcodeStr, + X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTInfo, + AVX512VLVectorVTInfo ShuffleMask> { + defm NAME: avx512_perm_t, + avx512_perm_t_mb, EVEX_V512; + let Predicates = [HasVLX] in { + defm NAME#128: avx512_perm_t, + avx512_perm_t_mb, EVEX_V128; + defm NAME#256: avx512_perm_t, + avx512_perm_t_mb, EVEX_V256; + } +} + +multiclass avx512_perm_t_sizes_bw opc, string OpcodeStr, + X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTInfo, + AVX512VLVectorVTInfo Idx, Predicate Prd> { + let Predicates = [Prd] in + defm NAME: avx512_perm_t, EVEX_V512; + let Predicates = [Prd, HasVLX] in { + defm NAME#128: avx512_perm_t, EVEX_V128; + defm NAME#256: avx512_perm_t, EVEX_V256; + } +} + +defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d", WriteVarShuffle256, + avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; +defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q", WriteVarShuffle256, + avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; +defm VPERMT2W : avx512_perm_t_sizes_bw<0x7D, "vpermt2w", WriteVarShuffle256, + avx512vl_i16_info, avx512vl_i16_info, HasBWI>, + VEX_W, EVEX_CD8<16, CD8VF>; +defm VPERMT2B : avx512_perm_t_sizes_bw<0x7D, "vpermt2b", WriteVarShuffle256, + avx512vl_i8_info, avx512vl_i8_info, HasVBMI>, + EVEX_CD8<8, CD8VF>; +defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps", WriteFVarShuffle256, + avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; +defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd", WriteFVarShuffle256, + avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; + +//===----------------------------------------------------------------------===// +// AVX-512 - BLEND using mask +// + +multiclass WriteFVarBlendask opc, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain, hasSideEffects = 0 in { + def rr : AVX5128I, + EVEX_4V, Sched<[sched]>; + def rrk : AVX5128I, EVEX_4V, EVEX_K, Sched<[sched]>; + def rrkz : AVX5128I, EVEX_4V, EVEX_KZ, Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in { + def rm : AVX5128I, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + def rmk : AVX5128I, EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + def rmkz : AVX5128I, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable; + } + } +} +multiclass WriteFVarBlendask_rmb opc, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let mayLoad = 1, hasSideEffects = 0 in { + def rmbk : AVX5128I, + EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + + def rmbkz : AVX5128I, + EVEX_4V, EVEX_KZ, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable; + + def rmb : AVX5128I, + EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass blendmask_dq opc, string OpcodeStr, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo> { + defm Z : WriteFVarBlendask, + WriteFVarBlendask_rmb, + EVEX_V512; + + let Predicates = [HasVLX] in { + defm Z256 : WriteFVarBlendask, + WriteFVarBlendask_rmb, + EVEX_V256; + defm Z128 : WriteFVarBlendask, + WriteFVarBlendask_rmb, + EVEX_V128; + } +} + +multiclass blendmask_bw opc, string OpcodeStr, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo> { + let Predicates = [HasBWI] in + defm Z : WriteFVarBlendask, + EVEX_V512; + + let Predicates = [HasBWI, HasVLX] in { + defm Z256 : WriteFVarBlendask, + EVEX_V256; + defm Z128 : WriteFVarBlendask, + EVEX_V128; + } +} + +defm VBLENDMPS : blendmask_dq<0x65, "vblendmps", SchedWriteFVarBlend, + avx512vl_f32_info>; +defm VBLENDMPD : blendmask_dq<0x65, "vblendmpd", SchedWriteFVarBlend, + avx512vl_f64_info>, VEX_W; +defm VPBLENDMD : blendmask_dq<0x64, "vpblendmd", SchedWriteVarBlend, + avx512vl_i32_info>; +defm VPBLENDMQ : blendmask_dq<0x64, "vpblendmq", SchedWriteVarBlend, + avx512vl_i64_info>, VEX_W; +defm VPBLENDMB : blendmask_bw<0x66, "vpblendmb", SchedWriteVarBlend, + avx512vl_i8_info>; +defm VPBLENDMW : blendmask_bw<0x66, "vpblendmw", SchedWriteVarBlend, + avx512vl_i16_info>, VEX_W; + +//===----------------------------------------------------------------------===// +// Compare Instructions +//===----------------------------------------------------------------------===// + +// avx512_cmp_scalar - AVX512 CMPSS and CMPSD + +multiclass avx512_cmp_scalar { + defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "$src2, $src1", "$src1, $src2", + (OpNode (_.VT _.RC:$src1), + (_.VT _.RC:$src2), + imm:$cc)>, EVEX_4V, Sched<[sched]>; + let mayLoad = 1 in + defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.IntScalarMemOp:$src2, AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "$src2, $src1", "$src1, $src2", + (OpNode (_.VT _.RC:$src1), _.ScalarIntMemCPat:$src2, + imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[sched.Folded, ReadAfterLd]>; + + defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "{sae}, $src2, $src1", "$src1, $src2, {sae}", + (OpNodeRnd (_.VT _.RC:$src1), + (_.VT _.RC:$src2), + imm:$cc, + (i32 FROUND_NO_EXC))>, + EVEX_4V, EVEX_B, Sched<[sched]>; + // Accept explicit immediate argument form instead of comparison code. + let isAsmParserOnly = 1, hasSideEffects = 0 in { + defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _, + (outs VK1:$dst), + (ins _.RC:$src1, _.RC:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V, + Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in + defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, $src2, $src1", "$src1, $src2, $cc">, + EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable; + + defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.RC:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, {sae}, $src2, $src1","$src1, $src2, {sae}, $cc">, + EVEX_4V, EVEX_B, Sched<[sched]>, NotMemoryFoldable; + }// let isAsmParserOnly = 1, hasSideEffects = 0 + + let isCodeGenOnly = 1 in { + let isCommutable = 1 in + def rr : AVX512Ii8<0xC2, MRMSrcReg, + (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc), + !strconcat("vcmp${cc}", _.Suffix, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set _.KRC:$dst, (OpNode _.FRC:$src1, + _.FRC:$src2, + imm:$cc))]>, + EVEX_4V, Sched<[sched]>; + def rm : AVX512Ii8<0xC2, MRMSrcMem, + (outs _.KRC:$dst), + (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc), + !strconcat("vcmp${cc}", _.Suffix, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set _.KRC:$dst, (OpNode _.FRC:$src1, + (_.ScalarLdFrag addr:$src2), + imm:$cc))]>, + EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +let Predicates = [HasAVX512] in { + let ExeDomain = SSEPackedSingle in + defm VCMPSSZ : avx512_cmp_scalar, AVX512XSIi8Base; + let ExeDomain = SSEPackedDouble in + defm VCMPSDZ : avx512_cmp_scalar, AVX512XDIi8Base, VEX_W; +} + +multiclass avx512_icmp_packed opc, string OpcodeStr, PatFrag OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + bit IsCommutable> { + let isCommutable = IsCommutable in + def rr : AVX512BI, + EVEX_4V, Sched<[sched]>; + def rm : AVX512BI, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + let isCommutable = IsCommutable in + def rrk : AVX512BI, + EVEX_4V, EVEX_K, Sched<[sched]>; + def rmk : AVX512BI, + EVEX_4V, EVEX_K, Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_icmp_packed_rmb opc, string OpcodeStr, PatFrag OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + bit IsCommutable> : + avx512_icmp_packed { + def rmb : AVX512BI, + EVEX_4V, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + def rmbk : AVX512BI, + EVEX_4V, EVEX_K, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_icmp_packed_vl opc, string OpcodeStr, PatFrag OpNode, + X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo, Predicate prd, + bit IsCommutable = 0> { + let Predicates = [prd] in + defm Z : avx512_icmp_packed, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_icmp_packed, EVEX_V256; + defm Z128 : avx512_icmp_packed, EVEX_V128; + } +} + +multiclass avx512_icmp_packed_rmb_vl opc, string OpcodeStr, + PatFrag OpNode, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo, + Predicate prd, bit IsCommutable = 0> { + let Predicates = [prd] in + defm Z : avx512_icmp_packed_rmb, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_icmp_packed_rmb, EVEX_V256; + defm Z128 : avx512_icmp_packed_rmb, EVEX_V128; + } +} + +// This fragment treats X86cmpm as commutable to help match loads in both +// operands for PCMPEQ. +def X86setcc_commute : SDNode<"ISD::SETCC", SDTSetCC, [SDNPCommutative]>; +def X86pcmpeqm_c : PatFrag<(ops node:$src1, node:$src2), + (X86setcc_commute node:$src1, node:$src2, SETEQ)>; +def X86pcmpgtm : PatFrag<(ops node:$src1, node:$src2), + (setcc node:$src1, node:$src2, SETGT)>; + +// AddedComplexity is needed because the explicit SETEQ/SETGT CondCode doesn't +// increase the pattern complexity the way an immediate would. +let AddedComplexity = 2 in { +// FIXME: Is there a better scheduler class for VPCMP? +defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm_c, + SchedWriteVecALU, avx512vl_i8_info, HasBWI, 1>, + EVEX_CD8<8, CD8VF>, VEX_WIG; + +defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm_c, + SchedWriteVecALU, avx512vl_i16_info, HasBWI, 1>, + EVEX_CD8<16, CD8VF>, VEX_WIG; + +defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm_c, + SchedWriteVecALU, avx512vl_i32_info, HasAVX512, 1>, + EVEX_CD8<32, CD8VF>; + +defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm_c, + SchedWriteVecALU, avx512vl_i64_info, HasAVX512, 1>, + T8PD, VEX_W, EVEX_CD8<64, CD8VF>; + +defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm, + SchedWriteVecALU, avx512vl_i8_info, HasBWI>, + EVEX_CD8<8, CD8VF>, VEX_WIG; + +defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm, + SchedWriteVecALU, avx512vl_i16_info, HasBWI>, + EVEX_CD8<16, CD8VF>, VEX_WIG; + +defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm, + SchedWriteVecALU, avx512vl_i32_info, HasAVX512>, + EVEX_CD8<32, CD8VF>; + +defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm, + SchedWriteVecALU, avx512vl_i64_info, HasAVX512>, + T8PD, VEX_W, EVEX_CD8<64, CD8VF>; +} + +multiclass avx512_icmp_cc opc, string Suffix, PatFrag Frag, + PatFrag CommFrag, X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Name> { + let isCommutable = 1 in + def rri : AVX512AIi8, + EVEX_4V, Sched<[sched]>; + def rmi : AVX512AIi8, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + let isCommutable = 1 in + def rrik : AVX512AIi8, + EVEX_4V, EVEX_K, Sched<[sched]>; + def rmik : AVX512AIi8, + EVEX_4V, EVEX_K, Sched<[sched.Folded, ReadAfterLd]>; + + // Accept explicit immediate argument form instead of comparison code. + let isAsmParserOnly = 1, hasSideEffects = 0 in { + def rri_alt : AVX512AIi8, + EVEX_4V, Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in + def rmi_alt : AVX512AIi8, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable; + def rrik_alt : AVX512AIi8, + EVEX_4V, EVEX_K, Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in + def rmik_alt : AVX512AIi8, + EVEX_4V, EVEX_K, Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + } + + def : Pat<(_.KVT (CommFrag:$cc (bitconvert (_.LdFrag addr:$src2)), + (_.VT _.RC:$src1), cond)), + (!cast(Name#_.ZSuffix#"rmi") + _.RC:$src1, addr:$src2, (CommFrag.OperandTransform $cc))>; + + def : Pat<(and _.KRCWM:$mask, + (_.KVT (CommFrag:$cc (bitconvert (_.LdFrag addr:$src2)), + (_.VT _.RC:$src1), cond))), + (!cast(Name#_.ZSuffix#"rmik") + _.KRCWM:$mask, _.RC:$src1, addr:$src2, + (CommFrag.OperandTransform $cc))>; +} + +multiclass avx512_icmp_cc_rmb opc, string Suffix, PatFrag Frag, + PatFrag CommFrag, X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Name> : + avx512_icmp_cc { + def rmib : AVX512AIi8, + EVEX_4V, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + def rmibk : AVX512AIi8, + EVEX_4V, EVEX_K, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + + // Accept explicit immediate argument form instead of comparison code. + let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in { + def rmib_alt : AVX512AIi8, + EVEX_4V, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + def rmibk_alt : AVX512AIi8, + EVEX_4V, EVEX_K, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + } + + def : Pat<(_.KVT (CommFrag:$cc (X86VBroadcast (_.ScalarLdFrag addr:$src2)), + (_.VT _.RC:$src1), cond)), + (!cast(Name#_.ZSuffix#"rmib") + _.RC:$src1, addr:$src2, (CommFrag.OperandTransform $cc))>; + + def : Pat<(and _.KRCWM:$mask, + (_.KVT (CommFrag:$cc (X86VBroadcast + (_.ScalarLdFrag addr:$src2)), + (_.VT _.RC:$src1), cond))), + (!cast(Name#_.ZSuffix#"rmibk") + _.KRCWM:$mask, _.RC:$src1, addr:$src2, + (CommFrag.OperandTransform $cc))>; +} + +multiclass avx512_icmp_cc_vl opc, string Suffix, PatFrag Frag, + PatFrag CommFrag, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo, Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_icmp_cc, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_icmp_cc, EVEX_V256; + defm Z128 : avx512_icmp_cc, EVEX_V128; + } +} + +multiclass avx512_icmp_cc_rmb_vl opc, string Suffix, PatFrag Frag, + PatFrag CommFrag, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo, Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_icmp_cc_rmb, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_icmp_cc_rmb, EVEX_V256; + defm Z128 : avx512_icmp_cc_rmb, EVEX_V128; + } +} + +def X86pcmpm_imm : SDNodeXForm(N->getOperand(2))->get(); + uint8_t SSECC = X86::getVPCMPImmForCond(CC); + return getI8Imm(SSECC, SDLoc(N)); +}]>; + +// Swapped operand version of the above. +def X86pcmpm_imm_commute : SDNodeXForm(N->getOperand(2))->get(); + uint8_t SSECC = X86::getVPCMPImmForCond(CC); + SSECC = X86::getSwappedVPCMPImm(SSECC); + return getI8Imm(SSECC, SDLoc(N)); +}]>; + +def X86pcmpm : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (setcc node:$src1, node:$src2, node:$cc), [{ + ISD::CondCode CC = cast(N->getOperand(2))->get(); + return !ISD::isUnsignedIntSetCC(CC); +}], X86pcmpm_imm>; + +// Same as above, but commutes immediate. Use for load folding. +def X86pcmpm_commute : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (setcc node:$src1, node:$src2, node:$cc), [{ + ISD::CondCode CC = cast(N->getOperand(2))->get(); + return !ISD::isUnsignedIntSetCC(CC); +}], X86pcmpm_imm_commute>; + +def X86pcmpum : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (setcc node:$src1, node:$src2, node:$cc), [{ + ISD::CondCode CC = cast(N->getOperand(2))->get(); + return ISD::isUnsignedIntSetCC(CC); +}], X86pcmpm_imm>; + +// Same as above, but commutes immediate. Use for load folding. +def X86pcmpum_commute : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (setcc node:$src1, node:$src2, node:$cc), [{ + ISD::CondCode CC = cast(N->getOperand(2))->get(); + return ISD::isUnsignedIntSetCC(CC); +}], X86pcmpm_imm_commute>; + +// FIXME: Is there a better scheduler class for VPCMP/VPCMPU? +defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86pcmpm, X86pcmpm_commute, + SchedWriteVecALU, avx512vl_i8_info, HasBWI>, + EVEX_CD8<8, CD8VF>; +defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86pcmpum, X86pcmpum_commute, + SchedWriteVecALU, avx512vl_i8_info, HasBWI>, + EVEX_CD8<8, CD8VF>; + +defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86pcmpm, X86pcmpm_commute, + SchedWriteVecALU, avx512vl_i16_info, HasBWI>, + VEX_W, EVEX_CD8<16, CD8VF>; +defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86pcmpum, X86pcmpum_commute, + SchedWriteVecALU, avx512vl_i16_info, HasBWI>, + VEX_W, EVEX_CD8<16, CD8VF>; + +defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86pcmpm, X86pcmpm_commute, + SchedWriteVecALU, avx512vl_i32_info, + HasAVX512>, EVEX_CD8<32, CD8VF>; +defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86pcmpum, X86pcmpum_commute, + SchedWriteVecALU, avx512vl_i32_info, + HasAVX512>, EVEX_CD8<32, CD8VF>; + +defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86pcmpm, X86pcmpm_commute, + SchedWriteVecALU, avx512vl_i64_info, + HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>; +defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86pcmpum, X86pcmpum_commute, + SchedWriteVecALU, avx512vl_i64_info, + HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>; + +multiclass avx512_vcmp_common { + defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "$src2, $src1", "$src1, $src2", + (X86cmpm (_.VT _.RC:$src1), + (_.VT _.RC:$src2), + imm:$cc), 1>, + Sched<[sched]>; + + defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _, + (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "$src2, $src1", "$src1, $src2", + (X86cmpm (_.VT _.RC:$src1), + (_.VT (bitconvert (_.LdFrag addr:$src2))), + imm:$cc)>, + Sched<[sched.Folded, ReadAfterLd]>; + + defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "${src2}"##_.BroadcastStr##", $src1", + "$src1, ${src2}"##_.BroadcastStr, + (X86cmpm (_.VT _.RC:$src1), + (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))), + imm:$cc)>, + EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + // Accept explicit immediate argument form instead of comparison code. + let isAsmParserOnly = 1, hasSideEffects = 0 in { + defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.RC:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, $src2, $src1", "$src1, $src2, $cc">, + Sched<[sched]>, NotMemoryFoldable; + + let mayLoad = 1 in { + defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, $src2, $src1", "$src1, $src2, $cc">, + Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + + defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, ${src2}"##_.BroadcastStr##", $src1", + "$src1, ${src2}"##_.BroadcastStr##", $cc">, + EVEX_B, Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + } + } + + // Patterns for selecting with loads in other operand. + def : Pat<(X86cmpm (_.LdFrag addr:$src2), (_.VT _.RC:$src1), + CommutableCMPCC:$cc), + (!cast(Name#_.ZSuffix#"rmi") _.RC:$src1, addr:$src2, + imm:$cc)>; + + def : Pat<(and _.KRCWM:$mask, (X86cmpm (_.LdFrag addr:$src2), + (_.VT _.RC:$src1), + CommutableCMPCC:$cc)), + (!cast(Name#_.ZSuffix#"rmik") _.KRCWM:$mask, + _.RC:$src1, addr:$src2, + imm:$cc)>; + + def : Pat<(X86cmpm (X86VBroadcast (_.ScalarLdFrag addr:$src2)), + (_.VT _.RC:$src1), CommutableCMPCC:$cc), + (!cast(Name#_.ZSuffix#"rmbi") _.RC:$src1, addr:$src2, + imm:$cc)>; + + def : Pat<(and _.KRCWM:$mask, (X86cmpm (X86VBroadcast + (_.ScalarLdFrag addr:$src2)), + (_.VT _.RC:$src1), + CommutableCMPCC:$cc)), + (!cast(Name#_.ZSuffix#"rmbik") _.KRCWM:$mask, + _.RC:$src1, addr:$src2, + imm:$cc)>; +} + +multiclass avx512_vcmp_sae { + // comparison code form (VCMP[EQ/LT/LE/...] + defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc), + "vcmp${cc}"#_.Suffix, + "{sae}, $src2, $src1", "$src1, $src2, {sae}", + (X86cmpmRnd (_.VT _.RC:$src1), + (_.VT _.RC:$src2), + imm:$cc, + (i32 FROUND_NO_EXC))>, + EVEX_B, Sched<[sched]>; + + let isAsmParserOnly = 1, hasSideEffects = 0 in { + defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _, + (outs _.KRC:$dst), + (ins _.RC:$src1, _.RC:$src2, u8imm:$cc), + "vcmp"#_.Suffix, + "$cc, {sae}, $src2, $src1", + "$src1, $src2, {sae}, $cc">, + EVEX_B, Sched<[sched]>, NotMemoryFoldable; + } +} + +multiclass avx512_vcmp { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcmp_common, + avx512_vcmp_sae, EVEX_V512; + + } + let Predicates = [HasAVX512,HasVLX] in { + defm Z128 : avx512_vcmp_common, EVEX_V128; + defm Z256 : avx512_vcmp_common, EVEX_V256; + } +} + +defm VCMPPD : avx512_vcmp, + AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; +defm VCMPPS : avx512_vcmp, + AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; + +// Patterns to select fp compares with load as first operand. +let Predicates = [HasAVX512] in { + def : Pat<(v1i1 (X86cmpms (loadf64 addr:$src2), FR64X:$src1, + CommutableCMPCC:$cc)), + (VCMPSDZrm FR64X:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(v1i1 (X86cmpms (loadf32 addr:$src2), FR32X:$src1, + CommutableCMPCC:$cc)), + (VCMPSSZrm FR32X:$src1, addr:$src2, imm:$cc)>; +} + +// ---------------------------------------------------------------- +// FPClass +//handle fpclass instruction mask = op(reg_scalar,imm) +// op(mem_scalar,imm) +multiclass avx512_scalar_fpclass opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + Predicate prd> { + let Predicates = [prd], ExeDomain = _.ExeDomain in { + def rr : AVX512, + Sched<[sched]>; + def rrk : AVX512, + EVEX_K, Sched<[sched]>; + def rm : AVX512, + Sched<[sched.Folded, ReadAfterLd]>; + def rmk : AVX512, + EVEX_K, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +//handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm) +// fpclass(reg_vec, mem_vec, imm) +// fpclass(reg_vec, broadcast(eltVt), imm) +multiclass avx512_vector_fpclass opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + string mem, string broadcast>{ + let ExeDomain = _.ExeDomain in { + def rr : AVX512, + Sched<[sched]>; + def rrk : AVX512, + EVEX_K, Sched<[sched]>; + def rm : AVX512, + Sched<[sched.Folded, ReadAfterLd]>; + def rmk : AVX512, + EVEX_K, Sched<[sched.Folded, ReadAfterLd]>; + def rmb : AVX512, + EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + def rmbk : AVX512, + EVEX_B, EVEX_K, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_vector_fpclass_all opc, SDNode OpNode, + X86SchedWriteWidths sched, Predicate prd, + string broadcast>{ + let Predicates = [prd] in { + defm Z : avx512_vector_fpclass, EVEX_V512; + } + let Predicates = [prd, HasVLX] in { + defm Z128 : avx512_vector_fpclass, EVEX_V128; + defm Z256 : avx512_vector_fpclass, EVEX_V256; + } +} + +multiclass avx512_fp_fpclass_all opcVec, + bits<8> opcScalar, SDNode VecOpNode, + SDNode ScalarOpNode, X86SchedWriteWidths sched, + Predicate prd> { + defm PS : avx512_vector_fpclass_all, + EVEX_CD8<32, CD8VF>; + defm PD : avx512_vector_fpclass_all, + EVEX_CD8<64, CD8VF> , VEX_W; + defm SSZ : avx512_scalar_fpclass, + EVEX_CD8<32, CD8VT1>; + defm SDZ : avx512_scalar_fpclass, + EVEX_CD8<64, CD8VT1>, VEX_W; +} + +defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass, + X86Vfpclasss, SchedWriteFCmp, HasDQI>, + AVX512AIi8Base, EVEX; + +//----------------------------------------------------------------- +// Mask register copy, including +// - copy between mask registers +// - load/store mask registers +// - copy from GPR to mask register and vice versa +// +multiclass avx512_mask_mov opc_kk, bits<8> opc_km, bits<8> opc_mk, + string OpcodeStr, RegisterClass KRC, + ValueType vvt, X86MemOperand x86memop> { + let isMoveReg = 1, hasSideEffects = 0, SchedRW = [WriteMove] in + def kk : I, + Sched<[WriteMove]>; + def km : I, + Sched<[WriteLoad]>; + def mk : I, + Sched<[WriteStore]>; +} + +multiclass avx512_mask_mov_gpr opc_kr, bits<8> opc_rk, + string OpcodeStr, + RegisterClass KRC, RegisterClass GRC> { + let hasSideEffects = 0 in { + def kr : I, + Sched<[WriteMove]>; + def rk : I, + Sched<[WriteMove]>; + } +} + +let Predicates = [HasDQI] in + defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>, + avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>, + VEX, PD; + +let Predicates = [HasAVX512] in + defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>, + avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>, + VEX, PS; + +let Predicates = [HasBWI] in { + defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>, + VEX, PD, VEX_W; + defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>, + VEX, XD; + defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>, + VEX, PS, VEX_W; + defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>, + VEX, XD, VEX_W; +} + +// GR from/to mask register +def : Pat<(v16i1 (bitconvert (i16 GR16:$src))), + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit)), VK16)>; +def : Pat<(i16 (bitconvert (v16i1 VK16:$src))), + (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK16:$src, GR32)), sub_16bit)>; + +def : Pat<(v8i1 (bitconvert (i8 GR8:$src))), + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), GR8:$src, sub_8bit)), VK8)>; +def : Pat<(i8 (bitconvert (v8i1 VK8:$src))), + (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK8:$src, GR32)), sub_8bit)>; + +def : Pat<(i32 (zext (i16 (bitconvert (v16i1 VK16:$src))))), + (KMOVWrk VK16:$src)>; +def : Pat<(i32 (anyext (i16 (bitconvert (v16i1 VK16:$src))))), + (COPY_TO_REGCLASS VK16:$src, GR32)>; + +def : Pat<(i32 (zext (i8 (bitconvert (v8i1 VK8:$src))))), + (KMOVBrk VK8:$src)>, Requires<[HasDQI]>; +def : Pat<(i32 (anyext (i8 (bitconvert (v8i1 VK8:$src))))), + (COPY_TO_REGCLASS VK8:$src, GR32)>; + +def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), + (COPY_TO_REGCLASS GR32:$src, VK32)>; +def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), + (COPY_TO_REGCLASS VK32:$src, GR32)>; +def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), + (COPY_TO_REGCLASS GR64:$src, VK64)>; +def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), + (COPY_TO_REGCLASS VK64:$src, GR64)>; + +// Load/store kreg +let Predicates = [HasDQI] in { + def : Pat<(store VK1:$src, addr:$dst), + (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK8))>; + + def : Pat<(v1i1 (load addr:$src)), + (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK1)>; + def : Pat<(v2i1 (load addr:$src)), + (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK2)>; + def : Pat<(v4i1 (load addr:$src)), + (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK4)>; +} + +let Predicates = [HasAVX512] in { + def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))), + (COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK8)>; +} + +let Predicates = [HasAVX512] in { + multiclass operation_gpr_mask_copy_lowering { + def : Pat<(maskVT (scalar_to_vector GR32:$src)), + (COPY_TO_REGCLASS GR32:$src, maskRC)>; + + def : Pat<(maskVT (scalar_to_vector GR8:$src)), + (COPY_TO_REGCLASS (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, sub_8bit), maskRC)>; + } + + defm : operation_gpr_mask_copy_lowering; + defm : operation_gpr_mask_copy_lowering; + defm : operation_gpr_mask_copy_lowering; + defm : operation_gpr_mask_copy_lowering; + defm : operation_gpr_mask_copy_lowering; + defm : operation_gpr_mask_copy_lowering; + defm : operation_gpr_mask_copy_lowering; + + def : Pat<(insert_subvector (v16i1 immAllZerosV), + (v1i1 (scalar_to_vector GR8:$src)), (iPTR 0)), + (COPY_TO_REGCLASS + (KMOVWkr (AND32ri8 + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, sub_8bit), + (i32 1))), VK16)>; +} + +// Mask unary operation +// - KNOT +multiclass avx512_mask_unop opc, string OpcodeStr, + RegisterClass KRC, SDPatternOperator OpNode, + X86FoldableSchedWrite sched, Predicate prd> { + let Predicates = [prd] in + def rr : I, + Sched<[sched]>; +} + +multiclass avx512_mask_unop_all opc, string OpcodeStr, + SDPatternOperator OpNode, + X86FoldableSchedWrite sched> { + defm B : avx512_mask_unop, VEX, PD; + defm W : avx512_mask_unop, VEX, PS; + defm D : avx512_mask_unop, VEX, PD, VEX_W; + defm Q : avx512_mask_unop, VEX, PS, VEX_W; +} + +// TODO - do we need a X86SchedWriteWidths::KMASK type? +defm KNOT : avx512_mask_unop_all<0x44, "knot", vnot, SchedWriteVecLogic.XMM>; + +// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit +let Predicates = [HasAVX512, NoDQI] in +def : Pat<(vnot VK8:$src), + (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>; + +def : Pat<(vnot VK4:$src), + (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src, VK16)), VK4)>; +def : Pat<(vnot VK2:$src), + (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src, VK16)), VK2)>; + +// Mask binary operation +// - KAND, KANDN, KOR, KXNOR, KXOR +multiclass avx512_mask_binop opc, string OpcodeStr, + RegisterClass KRC, SDPatternOperator OpNode, + X86FoldableSchedWrite sched, Predicate prd, + bit IsCommutable> { + let Predicates = [prd], isCommutable = IsCommutable in + def rr : I, + Sched<[sched]>; +} + +multiclass avx512_mask_binop_all opc, string OpcodeStr, + SDPatternOperator OpNode, + X86FoldableSchedWrite sched, bit IsCommutable, + Predicate prdW = HasAVX512> { + defm B : avx512_mask_binop, VEX_4V, VEX_L, PD; + defm W : avx512_mask_binop, VEX_4V, VEX_L, PS; + defm D : avx512_mask_binop, VEX_4V, VEX_L, VEX_W, PD; + defm Q : avx512_mask_binop, VEX_4V, VEX_L, VEX_W, PS; +} + +def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>; +def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>; +// These nodes use 'vnot' instead of 'not' to support vectors. +def vandn : PatFrag<(ops node:$i0, node:$i1), (and (vnot node:$i0), node:$i1)>; +def vxnor : PatFrag<(ops node:$i0, node:$i1), (vnot (xor node:$i0, node:$i1))>; + +// TODO - do we need a X86SchedWriteWidths::KMASK type? +defm KAND : avx512_mask_binop_all<0x41, "kand", and, SchedWriteVecLogic.XMM, 1>; +defm KOR : avx512_mask_binop_all<0x45, "kor", or, SchedWriteVecLogic.XMM, 1>; +defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", vxnor, SchedWriteVecLogic.XMM, 1>; +defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, SchedWriteVecLogic.XMM, 1>; +defm KANDN : avx512_mask_binop_all<0x42, "kandn", vandn, SchedWriteVecLogic.XMM, 0>; +defm KADD : avx512_mask_binop_all<0x4A, "kadd", X86kadd, SchedWriteVecLogic.XMM, 1, HasDQI>; + +multiclass avx512_binop_pat { + // With AVX512F, 8-bit mask is promoted to 16-bit mask, + // for the DQI set, this type is legal and KxxxB instruction is used + let Predicates = [NoDQI] in + def : Pat<(VOpNode VK8:$src1, VK8:$src2), + (COPY_TO_REGCLASS + (Inst (COPY_TO_REGCLASS VK8:$src1, VK16), + (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>; + + // All types smaller than 8 bits require conversion anyway + def : Pat<(OpNode VK1:$src1, VK1:$src2), + (COPY_TO_REGCLASS (Inst + (COPY_TO_REGCLASS VK1:$src1, VK16), + (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>; + def : Pat<(VOpNode VK2:$src1, VK2:$src2), + (COPY_TO_REGCLASS (Inst + (COPY_TO_REGCLASS VK2:$src1, VK16), + (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>; + def : Pat<(VOpNode VK4:$src1, VK4:$src2), + (COPY_TO_REGCLASS (Inst + (COPY_TO_REGCLASS VK4:$src1, VK16), + (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>; +} + +defm : avx512_binop_pat; +defm : avx512_binop_pat; +defm : avx512_binop_pat; +defm : avx512_binop_pat; +defm : avx512_binop_pat; + +// Mask unpacking +multiclass avx512_mask_unpck { + let Predicates = [prd] in { + let hasSideEffects = 0 in + def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst), + (ins KRC:$src1, KRC:$src2), + "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + VEX_4V, VEX_L, Sched<[sched]>; + + def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)), + (!cast(NAME##rr) + (COPY_TO_REGCLASS KRCSrc:$src2, KRC), + (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>; + } +} + +defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, WriteShuffle, HasAVX512>, PD; +defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, WriteShuffle, HasBWI>, PS; +defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, WriteShuffle, HasBWI>, PS, VEX_W; + +// Mask bit testing +multiclass avx512_mask_testop opc, string OpcodeStr, RegisterClass KRC, + SDNode OpNode, X86FoldableSchedWrite sched, + Predicate prd> { + let Predicates = [prd], Defs = [EFLAGS] in + def rr : I, + Sched<[sched]>; +} + +multiclass avx512_mask_testop_w opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + Predicate prdW = HasAVX512> { + defm B : avx512_mask_testop, + VEX, PD; + defm W : avx512_mask_testop, + VEX, PS; + defm Q : avx512_mask_testop, + VEX, PS, VEX_W; + defm D : avx512_mask_testop, + VEX, PD, VEX_W; +} + +// TODO - do we need a X86SchedWriteWidths::KMASK type? +defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest, SchedWriteVecLogic.XMM>; +defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, SchedWriteVecLogic.XMM, HasDQI>; + +// Mask shift +multiclass avx512_mask_shiftop opc, string OpcodeStr, RegisterClass KRC, + SDNode OpNode, X86FoldableSchedWrite sched> { + let Predicates = [HasAVX512] in + def ri : Ii8, + Sched<[sched]>; +} + +multiclass avx512_mask_shiftop_w opc1, bits<8> opc2, string OpcodeStr, + SDNode OpNode, X86FoldableSchedWrite sched> { + defm W : avx512_mask_shiftop, VEX, TAPD, VEX_W; + let Predicates = [HasDQI] in + defm B : avx512_mask_shiftop, VEX, TAPD; + let Predicates = [HasBWI] in { + defm Q : avx512_mask_shiftop, VEX, TAPD, VEX_W; + defm D : avx512_mask_shiftop, VEX, TAPD; + } +} + +defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86kshiftl, WriteShuffle>; +defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86kshiftr, WriteShuffle>; + +// Patterns for comparing 128/256-bit integer vectors using 512-bit instruction. +multiclass axv512_icmp_packed_no_vlx_lowering { + def : Pat<(Narrow.KVT (Frag (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2))), + (COPY_TO_REGCLASS + (!cast(InstStr#"Zrr") + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx))), + Narrow.KRC)>; + + def : Pat<(Narrow.KVT (and Narrow.KRC:$mask, + (Frag (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2)))), + (COPY_TO_REGCLASS + (!cast(InstStr#"Zrrk") + (COPY_TO_REGCLASS Narrow.KRC:$mask, Wide.KRC), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx))), + Narrow.KRC)>; +} + +// Patterns for comparing 128/256-bit integer vectors using 512-bit instruction. +multiclass axv512_icmp_packed_cc_no_vlx_lowering { +def : Pat<(Narrow.KVT (Frag:$cc (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2), cond)), + (COPY_TO_REGCLASS + (!cast(InstStr##Zrri) + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)), + (Frag.OperandTransform $cc)), Narrow.KRC)>; + +def : Pat<(Narrow.KVT (and Narrow.KRC:$mask, + (Narrow.KVT (Frag:$cc (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2), + cond)))), + (COPY_TO_REGCLASS (!cast(InstStr##Zrrik) + (COPY_TO_REGCLASS Narrow.KRC:$mask, Wide.KRC), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)), + (Frag.OperandTransform $cc)), Narrow.KRC)>; +} + +// Same as above, but for fp types which don't use PatFrags. +multiclass axv512_cmp_packed_cc_no_vlx_lowering { +def : Pat<(Narrow.KVT (OpNode (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2), imm:$cc)), + (COPY_TO_REGCLASS + (!cast(InstStr##Zrri) + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)), + imm:$cc), Narrow.KRC)>; + +def : Pat<(Narrow.KVT (and Narrow.KRC:$mask, + (OpNode (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2), imm:$cc))), + (COPY_TO_REGCLASS (!cast(InstStr##Zrrik) + (COPY_TO_REGCLASS Narrow.KRC:$mask, Wide.KRC), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)), + imm:$cc), Narrow.KRC)>; +} + +let Predicates = [HasAVX512, NoVLX] in { + // AddedComplexity is needed because the explicit SETEQ/SETGT CondCode doesn't + // increase the pattern complexity the way an immediate would. + let AddedComplexity = 2 in { + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + } + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_cmp_packed_cc_no_vlx_lowering; + defm : axv512_cmp_packed_cc_no_vlx_lowering; + defm : axv512_cmp_packed_cc_no_vlx_lowering; + defm : axv512_cmp_packed_cc_no_vlx_lowering; +} + +let Predicates = [HasBWI, NoVLX] in { + // AddedComplexity is needed because the explicit SETEQ/SETGT CondCode doesn't + // increase the pattern complexity the way an immediate would. + let AddedComplexity = 2 in { + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + + defm : axv512_icmp_packed_no_vlx_lowering; + defm : axv512_icmp_packed_no_vlx_lowering; + } + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; + + defm : axv512_icmp_packed_cc_no_vlx_lowering; + defm : axv512_icmp_packed_cc_no_vlx_lowering; +} + +// Mask setting all 0s or 1s +multiclass avx512_mask_setop { + let Predicates = [HasAVX512] in + let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1, + SchedRW = [WriteZero] in + def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "", + [(set KRC:$dst, (VT Val))]>; +} + +multiclass avx512_mask_setop_w { + defm W : avx512_mask_setop; + defm D : avx512_mask_setop; + defm Q : avx512_mask_setop; +} + +defm KSET0 : avx512_mask_setop_w; +defm KSET1 : avx512_mask_setop_w; + +// With AVX-512 only, 8-bit mask is promoted to 16-bit mask. +let Predicates = [HasAVX512] in { + def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>; + def : Pat<(v4i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK4)>; + def : Pat<(v2i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK2)>; + def : Pat<(v1i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK1)>; + def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>; + def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>; + def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>; + def : Pat<(v1i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK1)>; +} + +// Patterns for kmask insert_subvector/extract_subvector to/from index=0 +multiclass operation_subvector_mask_lowering { + def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))), + (subVT (COPY_TO_REGCLASS RC:$src, subRC))>; + + def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))), + (VT (COPY_TO_REGCLASS subRC:$src, RC))>; +} +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; + +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; + +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; + +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; + +defm : operation_subvector_mask_lowering; +defm : operation_subvector_mask_lowering; + +defm : operation_subvector_mask_lowering; + +//===----------------------------------------------------------------------===// +// AVX-512 - Aligned and unaligned load and store +// + +multiclass avx512_load opc, string OpcodeStr, string Name, + X86VectorVTInfo _, PatFrag ld_frag, PatFrag mload, + X86SchedWriteMoveLS Sched, string EVEX2VEXOvrd, + bit NoRMPattern = 0, + SDPatternOperator SelectOprr = vselect> { + let hasSideEffects = 0 in { + let isMoveReg = 1 in + def rr : AVX512PI, EVEX, Sched<[Sched.RR]>, + EVEX2VEXOverride; + def rrkz : AVX512PI, + EVEX, EVEX_KZ, Sched<[Sched.RR]>; + + let mayLoad = 1, canFoldAsLoad = 1, isReMaterializable = 1 in + def rm : AVX512PI, EVEX, Sched<[Sched.RM]>, + EVEX2VEXOverride; + + let Constraints = "$src0 = $dst", isConvertibleToThreeAddress = 1 in { + def rrk : AVX512PI, + EVEX, EVEX_K, Sched<[Sched.RR]>; + def rmk : AVX512PI, + EVEX, EVEX_K, Sched<[Sched.RM]>; + } + def rmkz : AVX512PI, EVEX, EVEX_KZ, Sched<[Sched.RM]>; + } + def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)), + (!cast(Name#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>; + + def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)), + (!cast(Name#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>; + + def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))), + (!cast(Name#_.ZSuffix##rmk) _.RC:$src0, + _.KRCWM:$mask, addr:$ptr)>; +} + +multiclass avx512_alignedload_vl opc, string OpcodeStr, + AVX512VLVectorVTInfo _, Predicate prd, + X86SchedWriteMoveLSWidths Sched, + string EVEX2VEXOvrd, bit NoRMPattern = 0> { + let Predicates = [prd] in + defm Z : avx512_load, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_load, EVEX_V256; + defm Z128 : avx512_load, EVEX_V128; + } +} + +multiclass avx512_load_vl opc, string OpcodeStr, + AVX512VLVectorVTInfo _, Predicate prd, + X86SchedWriteMoveLSWidths Sched, + string EVEX2VEXOvrd, bit NoRMPattern = 0, + SDPatternOperator SelectOprr = vselect> { + let Predicates = [prd] in + defm Z : avx512_load, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_load, EVEX_V256; + defm Z128 : avx512_load, EVEX_V128; + } +} + +multiclass avx512_store opc, string OpcodeStr, string BaseName, + X86VectorVTInfo _, PatFrag st_frag, PatFrag mstore, + X86SchedWriteMoveLS Sched, string EVEX2VEXOvrd, + bit NoMRPattern = 0> { + let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { + let isMoveReg = 1 in + def rr_REV : AVX512PI, EVEX, + FoldGenData, Sched<[Sched.RR]>, + EVEX2VEXOverride; + def rrk_REV : AVX512PI, EVEX, EVEX_K, + FoldGenData, + Sched<[Sched.RR]>; + def rrkz_REV : AVX512PI, EVEX, EVEX_KZ, + FoldGenData, + Sched<[Sched.RR]>; + } + + let hasSideEffects = 0, mayStore = 1 in + def mr : AVX512PI, EVEX, Sched<[Sched.MR]>, + EVEX2VEXOverride; + def mrk : AVX512PI, EVEX, EVEX_K, Sched<[Sched.MR]>, + NotMemoryFoldable; + + def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)), + (!cast(BaseName#_.ZSuffix#mrk) addr:$ptr, + _.KRCWM:$mask, _.RC:$src)>; + + def : InstAlias(BaseName#_.ZSuffix#"rr_REV") + _.RC:$dst, _.RC:$src), 0>; + def : InstAlias(BaseName#_.ZSuffix#"rrk_REV") + _.RC:$dst, _.KRCWM:$mask, _.RC:$src), 0>; + def : InstAlias(BaseName#_.ZSuffix#"rrkz_REV") + _.RC:$dst, _.KRCWM:$mask, _.RC:$src), 0>; +} + +multiclass avx512_store_vl< bits<8> opc, string OpcodeStr, + AVX512VLVectorVTInfo _, Predicate prd, + X86SchedWriteMoveLSWidths Sched, + string EVEX2VEXOvrd, bit NoMRPattern = 0> { + let Predicates = [prd] in + defm Z : avx512_store, EVEX_V512; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_store, EVEX_V256; + defm Z128 : avx512_store, EVEX_V128; + } +} + +multiclass avx512_alignedstore_vl opc, string OpcodeStr, + AVX512VLVectorVTInfo _, Predicate prd, + X86SchedWriteMoveLSWidths Sched, + string EVEX2VEXOvrd, bit NoMRPattern = 0> { + let Predicates = [prd] in + defm Z : avx512_store, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_store, EVEX_V256; + defm Z128 : avx512_store, EVEX_V128; + } +} + +defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info, + HasAVX512, SchedWriteFMoveLS, "VMOVAPS">, + avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info, + HasAVX512, SchedWriteFMoveLS, "VMOVAPS">, + PS, EVEX_CD8<32, CD8VF>; + +defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info, + HasAVX512, SchedWriteFMoveLS, "VMOVAPD">, + avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info, + HasAVX512, SchedWriteFMoveLS, "VMOVAPD">, + PD, VEX_W, EVEX_CD8<64, CD8VF>; + +defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512, + SchedWriteFMoveLS, "VMOVUPS", 0, null_frag>, + avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512, + SchedWriteFMoveLS, "VMOVUPS">, + PS, EVEX_CD8<32, CD8VF>; + +defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, + SchedWriteFMoveLS, "VMOVUPD", 0, null_frag>, + avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512, + SchedWriteFMoveLS, "VMOVUPD">, + PD, VEX_W, EVEX_CD8<64, CD8VF>; + +defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info, + HasAVX512, SchedWriteVecMoveLS, + "VMOVDQA", 1>, + avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info, + HasAVX512, SchedWriteVecMoveLS, + "VMOVDQA", 1>, + PD, EVEX_CD8<32, CD8VF>; + +defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info, + HasAVX512, SchedWriteVecMoveLS, + "VMOVDQA">, + avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info, + HasAVX512, SchedWriteVecMoveLS, + "VMOVDQA">, + PD, VEX_W, EVEX_CD8<64, CD8VF>; + +defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI, + SchedWriteVecMoveLS, "VMOVDQU", 1>, + avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info, HasBWI, + SchedWriteVecMoveLS, "VMOVDQU", 1>, + XD, EVEX_CD8<8, CD8VF>; + +defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI, + SchedWriteVecMoveLS, "VMOVDQU", 1>, + avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info, HasBWI, + SchedWriteVecMoveLS, "VMOVDQU", 1>, + XD, VEX_W, EVEX_CD8<16, CD8VF>; + +defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512, + SchedWriteVecMoveLS, "VMOVDQU", 1, null_frag>, + avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info, HasAVX512, + SchedWriteVecMoveLS, "VMOVDQU", 1>, + XS, EVEX_CD8<32, CD8VF>; + +defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512, + SchedWriteVecMoveLS, "VMOVDQU", 0, null_frag>, + avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info, HasAVX512, + SchedWriteVecMoveLS, "VMOVDQU">, + XS, VEX_W, EVEX_CD8<64, CD8VF>; + +/* +// Special instructions to help with spilling when we don't have VLX. We need +// to load or store from a ZMM register instead. These are converted in +// expandPostRAPseudos. +let isReMaterializable = 1, canFoldAsLoad = 1, + isPseudo = 1, mayLoad = 1, hasSideEffects = 0 in { +def VMOVAPSZ128rm_NOVLX : I<0, Pseudo, (outs VR128X:$dst), (ins f128mem:$src), + "", []>, Sched<[WriteFLoadX]>; +def VMOVAPSZ256rm_NOVLX : I<0, Pseudo, (outs VR256X:$dst), (ins f256mem:$src), + "", []>, Sched<[WriteFLoadY]>; +def VMOVUPSZ128rm_NOVLX : I<0, Pseudo, (outs VR128X:$dst), (ins f128mem:$src), + "", []>, Sched<[WriteFLoadX]>; +def VMOVUPSZ256rm_NOVLX : I<0, Pseudo, (outs VR256X:$dst), (ins f256mem:$src), + "", []>, Sched<[WriteFLoadY]>; +} + +let isPseudo = 1, mayStore = 1, hasSideEffects = 0 in { +def VMOVAPSZ128mr_NOVLX : I<0, Pseudo, (outs), (ins f128mem:$dst, VR128X:$src), + "", []>, Sched<[WriteFStoreX]>; +def VMOVAPSZ256mr_NOVLX : I<0, Pseudo, (outs), (ins f256mem:$dst, VR256X:$src), + "", []>, Sched<[WriteFStoreY]>; +def VMOVUPSZ128mr_NOVLX : I<0, Pseudo, (outs), (ins f128mem:$dst, VR128X:$src), + "", []>, Sched<[WriteFStoreX]>; +def VMOVUPSZ256mr_NOVLX : I<0, Pseudo, (outs), (ins f256mem:$dst, VR256X:$src), + "", []>, Sched<[WriteFStoreY]>; +} +*/ + +def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)), + (v8i64 VR512:$src))), + (VMOVDQA64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)), + VK8), VR512:$src)>; + +def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV), + (v16i32 VR512:$src))), + (VMOVDQA32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>; + +// These patterns exist to prevent the above patterns from introducing a second +// mask inversion when one already exists. +def : Pat<(v8i64 (vselect (xor VK8:$mask, (v8i1 immAllOnesV)), + (bc_v8i64 (v16i32 immAllZerosV)), + (v8i64 VR512:$src))), + (VMOVDQA64Zrrkz VK8:$mask, VR512:$src)>; +def : Pat<(v16i32 (vselect (xor VK16:$mask, (v16i1 immAllOnesV)), + (v16i32 immAllZerosV), + (v16i32 VR512:$src))), + (VMOVDQA32Zrrkz VK16WM:$mask, VR512:$src)>; + +multiclass mask_move_lowering { + def : Pat<(Narrow.VT (vselect (Narrow.KVT Narrow.KRCWM:$mask), + Narrow.RC:$src1, Narrow.RC:$src0)), + (EXTRACT_SUBREG + (Wide.VT + (!cast(InstrStr#"rrk") + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src0, Narrow.SubRegIdx)), + (COPY_TO_REGCLASS Narrow.KRCWM:$mask, Wide.KRCWM), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)))), + Narrow.SubRegIdx)>; + + def : Pat<(Narrow.VT (vselect (Narrow.KVT Narrow.KRCWM:$mask), + Narrow.RC:$src1, Narrow.ImmAllZerosV)), + (EXTRACT_SUBREG + (Wide.VT + (!cast(InstrStr#"rrkz") + (COPY_TO_REGCLASS Narrow.KRCWM:$mask, Wide.KRCWM), + (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)))), + Narrow.SubRegIdx)>; +} + +// Patterns for handling v8i1 selects of 256-bit vectors when VLX isn't +// available. Use a 512-bit operation and extract. +let Predicates = [HasAVX512, NoVLX] in { + defm : mask_move_lowering<"VMOVAPSZ", v4f32x_info, v16f32_info>; + defm : mask_move_lowering<"VMOVDQA32Z", v4i32x_info, v16i32_info>; + defm : mask_move_lowering<"VMOVAPSZ", v8f32x_info, v16f32_info>; + defm : mask_move_lowering<"VMOVDQA32Z", v8i32x_info, v16i32_info>; + + defm : mask_move_lowering<"VMOVAPDZ", v2f64x_info, v8f64_info>; + defm : mask_move_lowering<"VMOVDQA64Z", v2i64x_info, v8i64_info>; + defm : mask_move_lowering<"VMOVAPDZ", v4f64x_info, v8f64_info>; + defm : mask_move_lowering<"VMOVDQA64Z", v4i64x_info, v8i64_info>; +} + +let Predicates = [HasBWI, NoVLX] in { + defm : mask_move_lowering<"VMOVDQU8Z", v16i8x_info, v64i8_info>; + defm : mask_move_lowering<"VMOVDQU8Z", v32i8x_info, v64i8_info>; + + defm : mask_move_lowering<"VMOVDQU16Z", v8i16x_info, v32i16_info>; + defm : mask_move_lowering<"VMOVDQU16Z", v16i16x_info, v32i16_info>; +} + +let Predicates = [HasAVX512] in { + // 512-bit store. + def : Pat<(alignedstore (v16i32 VR512:$src), addr:$dst), + (VMOVDQA64Zmr addr:$dst, VR512:$src)>; + def : Pat<(alignedstore (v32i16 VR512:$src), addr:$dst), + (VMOVDQA64Zmr addr:$dst, VR512:$src)>; + def : Pat<(alignedstore (v64i8 VR512:$src), addr:$dst), + (VMOVDQA64Zmr addr:$dst, VR512:$src)>; + def : Pat<(store (v16i32 VR512:$src), addr:$dst), + (VMOVDQU64Zmr addr:$dst, VR512:$src)>; + def : Pat<(store (v32i16 VR512:$src), addr:$dst), + (VMOVDQU64Zmr addr:$dst, VR512:$src)>; + def : Pat<(store (v64i8 VR512:$src), addr:$dst), + (VMOVDQU64Zmr addr:$dst, VR512:$src)>; +} + +let Predicates = [HasVLX] in { + // 128-bit store. + def : Pat<(alignedstore (v4i32 VR128X:$src), addr:$dst), + (VMOVDQA64Z128mr addr:$dst, VR128X:$src)>; + def : Pat<(alignedstore (v8i16 VR128X:$src), addr:$dst), + (VMOVDQA64Z128mr addr:$dst, VR128X:$src)>; + def : Pat<(alignedstore (v16i8 VR128X:$src), addr:$dst), + (VMOVDQA64Z128mr addr:$dst, VR128X:$src)>; + def : Pat<(store (v4i32 VR128X:$src), addr:$dst), + (VMOVDQU64Z128mr addr:$dst, VR128X:$src)>; + def : Pat<(store (v8i16 VR128X:$src), addr:$dst), + (VMOVDQU64Z128mr addr:$dst, VR128X:$src)>; + def : Pat<(store (v16i8 VR128X:$src), addr:$dst), + (VMOVDQU64Z128mr addr:$dst, VR128X:$src)>; + + // 256-bit store. + def : Pat<(alignedstore (v8i32 VR256X:$src), addr:$dst), + (VMOVDQA64Z256mr addr:$dst, VR256X:$src)>; + def : Pat<(alignedstore (v16i16 VR256X:$src), addr:$dst), + (VMOVDQA64Z256mr addr:$dst, VR256X:$src)>; + def : Pat<(alignedstore (v32i8 VR256X:$src), addr:$dst), + (VMOVDQA64Z256mr addr:$dst, VR256X:$src)>; + def : Pat<(store (v8i32 VR256X:$src), addr:$dst), + (VMOVDQU64Z256mr addr:$dst, VR256X:$src)>; + def : Pat<(store (v16i16 VR256X:$src), addr:$dst), + (VMOVDQU64Z256mr addr:$dst, VR256X:$src)>; + def : Pat<(store (v32i8 VR256X:$src), addr:$dst), + (VMOVDQU64Z256mr addr:$dst, VR256X:$src)>; +} + +multiclass masked_move_for_extract { + def : Pat<(Cast.VT (vselect Cast.KRCWM:$mask, + (bitconvert + (To.VT (extract_subvector + (From.VT From.RC:$src), (iPTR 0)))), + To.RC:$src0)), + (Cast.VT (!cast(InstrStr#"rrk") + Cast.RC:$src0, Cast.KRCWM:$mask, + (To.VT (EXTRACT_SUBREG From.RC:$src, To.SubRegIdx))))>; + + def : Pat<(Cast.VT (vselect Cast.KRCWM:$mask, + (bitconvert + (To.VT (extract_subvector + (From.VT From.RC:$src), (iPTR 0)))), + Cast.ImmAllZerosV)), + (Cast.VT (!cast(InstrStr#"rrkz") + Cast.KRCWM:$mask, + (To.VT (EXTRACT_SUBREG From.RC:$src, To.SubRegIdx))))>; +} + + +let Predicates = [HasVLX] in { +// A masked extract from the first 128-bits of a 256-bit vector can be +// implemented with masked move. +defm : masked_move_for_extract<"VMOVDQA64Z128", v4i64x_info, v2i64x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z128", v8i32x_info, v4i32x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z128", v16i16x_info, v8i16x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z128", v32i8x_info, v16i8x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v4i64x_info, v2i64x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v8i32x_info, v4i32x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v16i16x_info, v8i16x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v32i8x_info, v16i8x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVAPDZ128", v4f64x_info, v2f64x_info, v2f64x_info>; +defm : masked_move_for_extract<"VMOVAPDZ128", v8f32x_info, v4f32x_info, v2f64x_info>; +defm : masked_move_for_extract<"VMOVAPSZ128", v4f64x_info, v2f64x_info, v4f32x_info>; +defm : masked_move_for_extract<"VMOVAPSZ128", v8f32x_info, v4f32x_info, v4f32x_info>; + +// A masked extract from the first 128-bits of a 512-bit vector can be +// implemented with masked move. +defm : masked_move_for_extract<"VMOVDQA64Z128", v8i64_info, v2i64x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z128", v16i32_info, v4i32x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z128", v32i16_info, v8i16x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z128", v64i8_info, v16i8x_info, v2i64x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v8i64_info, v2i64x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v16i32_info, v4i32x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v32i16_info, v8i16x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z128", v64i8_info, v16i8x_info, v4i32x_info>; +defm : masked_move_for_extract<"VMOVAPDZ128", v8f64_info, v2f64x_info, v2f64x_info>; +defm : masked_move_for_extract<"VMOVAPDZ128", v16f32_info, v4f32x_info, v2f64x_info>; +defm : masked_move_for_extract<"VMOVAPSZ128", v8f64_info, v2f64x_info, v4f32x_info>; +defm : masked_move_for_extract<"VMOVAPSZ128", v16f32_info, v4f32x_info, v4f32x_info>; + +// A masked extract from the first 256-bits of a 512-bit vector can be +// implemented with masked move. +defm : masked_move_for_extract<"VMOVDQA64Z256", v8i64_info, v4i64x_info, v4i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z256", v16i32_info, v8i32x_info, v4i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z256", v32i16_info, v16i16x_info, v4i64x_info>; +defm : masked_move_for_extract<"VMOVDQA64Z256", v64i8_info, v32i8x_info, v4i64x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z256", v8i64_info, v4i64x_info, v8i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z256", v16i32_info, v8i32x_info, v8i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z256", v32i16_info, v16i16x_info, v8i32x_info>; +defm : masked_move_for_extract<"VMOVDQA32Z256", v64i8_info, v32i8x_info, v8i32x_info>; +defm : masked_move_for_extract<"VMOVAPDZ256", v8f64_info, v4f64x_info, v4f64x_info>; +defm : masked_move_for_extract<"VMOVAPDZ256", v16f32_info, v8f32x_info, v4f64x_info>; +defm : masked_move_for_extract<"VMOVAPSZ256", v8f64_info, v4f64x_info, v8f32x_info>; +defm : masked_move_for_extract<"VMOVAPSZ256", v16f32_info, v8f32x_info, v8f32x_info>; +} + +// Move Int Doubleword to Packed Double Int +// +let ExeDomain = SSEPackedInt in { +def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(set VR128X:$dst, + (v4i32 (scalar_to_vector GR32:$src)))]>, + EVEX, Sched<[WriteVecMoveFromGpr]>; +def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(set VR128X:$dst, + (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>, + EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecLoad]>; +def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set VR128X:$dst, + (v2i64 (scalar_to_vector GR64:$src)))]>, + EVEX, VEX_W, Sched<[WriteVecMoveFromGpr]>; +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in +def VMOV64toPQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), + (ins i64mem:$src), + "vmovq\t{$src, $dst|$dst, $src}", []>, + EVEX, VEX_W, EVEX_CD8<64, CD8VT1>, Sched<[WriteVecLoad]>; +let isCodeGenOnly = 1 in { +def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64X:$dst), (ins GR64:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set FR64X:$dst, (bitconvert GR64:$src))]>, + EVEX, VEX_W, Sched<[WriteVecMoveFromGpr]>; +def VMOV64toSDZrm : AVX512XSI<0x7E, MRMSrcMem, (outs FR64X:$dst), (ins i64mem:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set FR64X:$dst, (bitconvert (loadi64 addr:$src)))]>, + EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteVecLoad]>; +def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64X:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (bitconvert FR64X:$src))]>, + EVEX, VEX_W, Sched<[WriteVecMoveFromGpr]>; +def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64X:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(store (i64 (bitconvert FR64X:$src)), addr:$dst)]>, + EVEX, VEX_W, Sched<[WriteVecStore]>, + EVEX_CD8<64, CD8VT1>; +} +} // ExeDomain = SSEPackedInt + +// Move Int Doubleword to Single Scalar +// +let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in { +def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(set FR32X:$dst, (bitconvert GR32:$src))]>, + EVEX, Sched<[WriteVecMoveFromGpr]>; + +def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))]>, + EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecLoad]>; +} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1 + +// Move doubleword from xmm register to r/m32 +// +let ExeDomain = SSEPackedInt in { +def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (extractelt (v4i32 VR128X:$src), + (iPTR 0)))]>, + EVEX, Sched<[WriteVecMoveToGpr]>; +def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs), + (ins i32mem:$dst, VR128X:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(store (i32 (extractelt (v4i32 VR128X:$src), + (iPTR 0))), addr:$dst)]>, + EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecStore]>; +} // ExeDomain = SSEPackedInt + +// Move quadword from xmm1 register to r/m64 +// +let ExeDomain = SSEPackedInt in { +def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (extractelt (v2i64 VR128X:$src), + (iPTR 0)))]>, + PD, EVEX, VEX_W, Sched<[WriteVecMoveToGpr]>, + Requires<[HasAVX512]>; + +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in +def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128X:$src), + "vmovq\t{$src, $dst|$dst, $src}", []>, PD, + EVEX, VEX_W, Sched<[WriteVecStore]>, + Requires<[HasAVX512, In64BitMode]>; + +def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs), + (ins i64mem:$dst, VR128X:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)), + addr:$dst)]>, + EVEX, PD, VEX_W, EVEX_CD8<64, CD8VT1>, + Sched<[WriteVecStore]>, Requires<[HasAVX512]>; + +let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in +def VMOVPQI2QIZrr : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst), + (ins VR128X:$src), + "vmovq\t{$src, $dst|$dst, $src}", []>, + EVEX, VEX_W, Sched<[SchedWriteVecLogic.XMM]>; +} // ExeDomain = SSEPackedInt + +def : InstAlias<"vmovq.s\t{$src, $dst|$dst, $src}", + (VMOVPQI2QIZrr VR128X:$dst, VR128X:$src), 0>; + +// Move Scalar Single to Double Int +// +let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in { +def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), + (ins FR32X:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (bitconvert FR32X:$src))]>, + EVEX, Sched<[WriteVecMoveToGpr]>; +def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs), + (ins i32mem:$dst, FR32X:$src), + "vmovd\t{$src, $dst|$dst, $src}", + [(store (i32 (bitconvert FR32X:$src)), addr:$dst)]>, + EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecStore]>; +} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1 + +// Move Quadword Int to Packed Quadword Int +// +let ExeDomain = SSEPackedInt in { +def VMOVQI2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst), + (ins i64mem:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set VR128X:$dst, + (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, + EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteVecLoad]>; +} // ExeDomain = SSEPackedInt + +// Allow "vmovd" but print "vmovq". +def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}", + (VMOV64toPQIZrr VR128X:$dst, GR64:$src), 0>; +def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}", + (VMOVPQIto64Zrr GR64:$dst, VR128X:$src), 0>; + +//===----------------------------------------------------------------------===// +// AVX-512 MOVSS, MOVSD +//===----------------------------------------------------------------------===// + +multiclass avx512_move_scalar { + let Predicates = [HasAVX512, OptForSize] in + def rr : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst), + (ins _.RC:$src1, _.RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2)))], + _.ExeDomain>, EVEX_4V, Sched<[SchedWriteFShuffle.XMM]>; + def rrkz : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst), + (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst {${mask}} {z}|", + "$dst {${mask}} {z}, $src1, $src2}"), + [(set _.RC:$dst, (_.VT (X86selects _.KRCWM:$mask, + (_.VT (OpNode _.RC:$src1, _.RC:$src2)), + _.ImmAllZerosV)))], + _.ExeDomain>, EVEX_4V, EVEX_KZ, Sched<[SchedWriteFShuffle.XMM]>; + let Constraints = "$src0 = $dst" in + def rrk : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst), + (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1, _.RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst {${mask}}|", + "$dst {${mask}}, $src1, $src2}"), + [(set _.RC:$dst, (_.VT (X86selects _.KRCWM:$mask, + (_.VT (OpNode _.RC:$src1, _.RC:$src2)), + (_.VT _.RC:$src0))))], + _.ExeDomain>, EVEX_4V, EVEX_K, Sched<[SchedWriteFShuffle.XMM]>; + let canFoldAsLoad = 1, isReMaterializable = 1 in + def rm : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), (ins _.ScalarMemOp:$src), + !strconcat(asm, "\t{$src, $dst|$dst, $src}"), + [(set _.FRC:$dst, (_.ScalarLdFrag addr:$src))], + _.ExeDomain>, EVEX, Sched<[WriteFLoad]>; + let mayLoad = 1, hasSideEffects = 0 in { + let Constraints = "$src0 = $dst" in + def rmk : AVX512PI<0x10, MRMSrcMem, (outs _.RC:$dst), + (ins _.RC:$src0, _.KRCWM:$mask, _.ScalarMemOp:$src), + !strconcat(asm, "\t{$src, $dst {${mask}}|", + "$dst {${mask}}, $src}"), + [], _.ExeDomain>, EVEX, EVEX_K, Sched<[WriteFLoad]>; + def rmkz : AVX512PI<0x10, MRMSrcMem, (outs _.RC:$dst), + (ins _.KRCWM:$mask, _.ScalarMemOp:$src), + !strconcat(asm, "\t{$src, $dst {${mask}} {z}|", + "$dst {${mask}} {z}, $src}"), + [], _.ExeDomain>, EVEX, EVEX_KZ, Sched<[WriteFLoad]>; + } + def mr: AVX512PI<0x11, MRMDestMem, (outs), (ins _.ScalarMemOp:$dst, _.FRC:$src), + !strconcat(asm, "\t{$src, $dst|$dst, $src}"), + [(store _.FRC:$src, addr:$dst)], _.ExeDomain>, + EVEX, Sched<[WriteFStore]>; + let mayStore = 1, hasSideEffects = 0 in + def mrk: AVX512PI<0x11, MRMDestMem, (outs), + (ins _.ScalarMemOp:$dst, VK1WM:$mask, _.FRC:$src), + !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"), + [], _.ExeDomain>, EVEX, EVEX_K, Sched<[WriteFStore]>, + NotMemoryFoldable; +} + +defm VMOVSSZ : avx512_move_scalar<"vmovss", X86Movss, f32x_info>, + VEX_LIG, XS, EVEX_CD8<32, CD8VT1>; + +defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, f64x_info>, + VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>; + + +multiclass avx512_move_scalar_lowering { + +def : Pat<(_.VT (OpNode _.RC:$src0, + (_.VT (scalar_to_vector + (_.EltVT (X86selects VK1WM:$mask, + (_.EltVT _.FRC:$src1), + (_.EltVT _.FRC:$src2))))))), + (!cast(InstrStr#rrk) + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, _.RC)), + VK1WM:$mask, + (_.VT _.RC:$src0), + (_.VT (COPY_TO_REGCLASS _.FRC:$src1, _.RC)))>; + +def : Pat<(_.VT (OpNode _.RC:$src0, + (_.VT (scalar_to_vector + (_.EltVT (X86selects VK1WM:$mask, + (_.EltVT _.FRC:$src1), + (_.EltVT ZeroFP))))))), + (!cast(InstrStr#rrkz) + VK1WM:$mask, + (_.VT _.RC:$src0), + (_.VT (COPY_TO_REGCLASS _.FRC:$src1, _.RC)))>; +} + +multiclass avx512_store_scalar_lowering { + +def : Pat<(masked_store addr:$dst, Mask, + (_.info512.VT (insert_subvector undef, + (_.info128.VT _.info128.RC:$src), + (iPTR 0)))), + (!cast(InstrStr#mrk) addr:$dst, + (COPY_TO_REGCLASS MaskRC:$mask, VK1WM), + (COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>; + +} + +multiclass avx512_store_scalar_lowering_subreg { + +def : Pat<(masked_store addr:$dst, Mask, + (_.info512.VT (insert_subvector undef, + (_.info128.VT _.info128.RC:$src), + (iPTR 0)))), + (!cast(InstrStr#mrk) addr:$dst, + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + (COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>; + +} + +// This matches the more recent codegen from clang that avoids emitting a 512 +// bit masked store directly. Codegen will widen 128-bit masked store to 512 +// bits on AVX512F only targets. +multiclass avx512_store_scalar_lowering_subreg2 { + +// AVX512F pattern. +def : Pat<(masked_store addr:$dst, Mask512, + (_.info512.VT (insert_subvector undef, + (_.info128.VT _.info128.RC:$src), + (iPTR 0)))), + (!cast(InstrStr#mrk) addr:$dst, + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + (COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>; + +// AVX512VL pattern. +def : Pat<(masked_store addr:$dst, Mask128, (_.info128.VT _.info128.RC:$src)), + (!cast(InstrStr#mrk) addr:$dst, + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + (COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>; +} + +multiclass avx512_load_scalar_lowering { + +def : Pat<(_.info128.VT (extract_subvector + (_.info512.VT (masked_load addr:$srcAddr, Mask, + (_.info512.VT (bitconvert + (v16i32 immAllZerosV))))), + (iPTR 0))), + (!cast(InstrStr#rmkz) + (COPY_TO_REGCLASS MaskRC:$mask, VK1WM), + addr:$srcAddr)>; + +def : Pat<(_.info128.VT (extract_subvector + (_.info512.VT (masked_load addr:$srcAddr, Mask, + (_.info512.VT (insert_subvector undef, + (_.info128.VT (X86vzmovl _.info128.RC:$src)), + (iPTR 0))))), + (iPTR 0))), + (!cast(InstrStr#rmk) _.info128.RC:$src, + (COPY_TO_REGCLASS MaskRC:$mask, VK1WM), + addr:$srcAddr)>; + +} + +multiclass avx512_load_scalar_lowering_subreg { + +def : Pat<(_.info128.VT (extract_subvector + (_.info512.VT (masked_load addr:$srcAddr, Mask, + (_.info512.VT (bitconvert + (v16i32 immAllZerosV))))), + (iPTR 0))), + (!cast(InstrStr#rmkz) + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + addr:$srcAddr)>; + +def : Pat<(_.info128.VT (extract_subvector + (_.info512.VT (masked_load addr:$srcAddr, Mask, + (_.info512.VT (insert_subvector undef, + (_.info128.VT (X86vzmovl _.info128.RC:$src)), + (iPTR 0))))), + (iPTR 0))), + (!cast(InstrStr#rmk) _.info128.RC:$src, + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + addr:$srcAddr)>; + +} + +// This matches the more recent codegen from clang that avoids emitting a 512 +// bit masked load directly. Codegen will widen 128-bit masked load to 512 +// bits on AVX512F only targets. +multiclass avx512_load_scalar_lowering_subreg2 { +// AVX512F patterns. +def : Pat<(_.info128.VT (extract_subvector + (_.info512.VT (masked_load addr:$srcAddr, Mask512, + (_.info512.VT (bitconvert + (v16i32 immAllZerosV))))), + (iPTR 0))), + (!cast(InstrStr#rmkz) + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + addr:$srcAddr)>; + +def : Pat<(_.info128.VT (extract_subvector + (_.info512.VT (masked_load addr:$srcAddr, Mask512, + (_.info512.VT (insert_subvector undef, + (_.info128.VT (X86vzmovl _.info128.RC:$src)), + (iPTR 0))))), + (iPTR 0))), + (!cast(InstrStr#rmk) _.info128.RC:$src, + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + addr:$srcAddr)>; + +// AVX512Vl patterns. +def : Pat<(_.info128.VT (masked_load addr:$srcAddr, Mask128, + (_.info128.VT (bitconvert (v4i32 immAllZerosV))))), + (!cast(InstrStr#rmkz) + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + addr:$srcAddr)>; + +def : Pat<(_.info128.VT (masked_load addr:$srcAddr, Mask128, + (_.info128.VT (X86vzmovl _.info128.RC:$src)))), + (!cast(InstrStr#rmk) _.info128.RC:$src, + (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM), + addr:$srcAddr)>; +} + +defm : avx512_move_scalar_lowering<"VMOVSSZ", X86Movss, fp32imm0, v4f32x_info>; +defm : avx512_move_scalar_lowering<"VMOVSDZ", X86Movsd, fp64imm0, v2f64x_info>; + +defm : avx512_store_scalar_lowering<"VMOVSSZ", avx512vl_f32_info, + (v16i1 (bitconvert (i16 (trunc (and GR32:$mask, (i32 1)))))), GR32>; +defm : avx512_store_scalar_lowering_subreg<"VMOVSSZ", avx512vl_f32_info, + (v16i1 (bitconvert (i16 (and GR16:$mask, (i16 1))))), GR16, sub_16bit>; +defm : avx512_store_scalar_lowering_subreg<"VMOVSDZ", avx512vl_f64_info, + (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), GR8, sub_8bit>; + +defm : avx512_store_scalar_lowering_subreg2<"VMOVSSZ", avx512vl_f32_info, + (v16i1 (insert_subvector + (v16i1 immAllZerosV), + (v4i1 (extract_subvector + (v8i1 (bitconvert (and GR8:$mask, (i8 1)))), + (iPTR 0))), + (iPTR 0))), + (v4i1 (extract_subvector + (v8i1 (bitconvert (and GR8:$mask, (i8 1)))), + (iPTR 0))), GR8, sub_8bit>; +defm : avx512_store_scalar_lowering_subreg2<"VMOVSDZ", avx512vl_f64_info, + (v8i1 + (extract_subvector + (v16i1 + (insert_subvector + (v16i1 immAllZerosV), + (v2i1 (extract_subvector + (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), + (iPTR 0))), + (iPTR 0))), + (iPTR 0))), + (v2i1 (extract_subvector + (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), + (iPTR 0))), GR8, sub_8bit>; + +defm : avx512_load_scalar_lowering<"VMOVSSZ", avx512vl_f32_info, + (v16i1 (bitconvert (i16 (trunc (and GR32:$mask, (i32 1)))))), GR32>; +defm : avx512_load_scalar_lowering_subreg<"VMOVSSZ", avx512vl_f32_info, + (v16i1 (bitconvert (i16 (and GR16:$mask, (i16 1))))), GR16, sub_16bit>; +defm : avx512_load_scalar_lowering_subreg<"VMOVSDZ", avx512vl_f64_info, + (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), GR8, sub_8bit>; + +defm : avx512_load_scalar_lowering_subreg2<"VMOVSSZ", avx512vl_f32_info, + (v16i1 (insert_subvector + (v16i1 immAllZerosV), + (v4i1 (extract_subvector + (v8i1 (bitconvert (and GR8:$mask, (i8 1)))), + (iPTR 0))), + (iPTR 0))), + (v4i1 (extract_subvector + (v8i1 (bitconvert (and GR8:$mask, (i8 1)))), + (iPTR 0))), GR8, sub_8bit>; +defm : avx512_load_scalar_lowering_subreg2<"VMOVSDZ", avx512vl_f64_info, + (v8i1 + (extract_subvector + (v16i1 + (insert_subvector + (v16i1 immAllZerosV), + (v2i1 (extract_subvector + (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), + (iPTR 0))), + (iPTR 0))), + (iPTR 0))), + (v2i1 (extract_subvector + (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), + (iPTR 0))), GR8, sub_8bit>; + +def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))), + (COPY_TO_REGCLASS (v4f32 (VMOVSSZrrk + (v4f32 (COPY_TO_REGCLASS FR32X:$src2, VR128X)), + VK1WM:$mask, (v4f32 (IMPLICIT_DEF)), + (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)))), FR32X)>; + +def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), fp32imm0)), + (COPY_TO_REGCLASS (v4f32 (VMOVSSZrrkz VK1WM:$mask, (v4f32 (IMPLICIT_DEF)), + (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)))), FR32X)>; + +def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))), + (COPY_TO_REGCLASS (v2f64 (VMOVSDZrrk + (v2f64 (COPY_TO_REGCLASS FR64X:$src2, VR128X)), + VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), + (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)))), FR64X)>; + +def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), fpimm0)), + (COPY_TO_REGCLASS (v2f64 (VMOVSDZrrkz VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), + (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)))), FR64X)>; + +let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { + def VMOVSSZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), + (ins VR128X:$src1, VR128X:$src2), + "vmovss\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, XS, EVEX_4V, VEX_LIG, + FoldGenData<"VMOVSSZrr">, + Sched<[SchedWriteFShuffle.XMM]>; + + let Constraints = "$src0 = $dst" in + def VMOVSSZrrk_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), + (ins f32x_info.RC:$src0, f32x_info.KRCWM:$mask, + VR128X:$src1, VR128X:$src2), + "vmovss\t{$src2, $src1, $dst {${mask}}|"# + "$dst {${mask}}, $src1, $src2}", + []>, EVEX_K, XS, EVEX_4V, VEX_LIG, + FoldGenData<"VMOVSSZrrk">, + Sched<[SchedWriteFShuffle.XMM]>; + + def VMOVSSZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), + (ins f32x_info.KRCWM:$mask, VR128X:$src1, VR128X:$src2), + "vmovss\t{$src2, $src1, $dst {${mask}} {z}|"# + "$dst {${mask}} {z}, $src1, $src2}", + []>, EVEX_KZ, XS, EVEX_4V, VEX_LIG, + FoldGenData<"VMOVSSZrrkz">, + Sched<[SchedWriteFShuffle.XMM]>; + + def VMOVSDZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), + (ins VR128X:$src1, VR128X:$src2), + "vmovsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, XD, EVEX_4V, VEX_LIG, VEX_W, + FoldGenData<"VMOVSDZrr">, + Sched<[SchedWriteFShuffle.XMM]>; + + let Constraints = "$src0 = $dst" in + def VMOVSDZrrk_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), + (ins f64x_info.RC:$src0, f64x_info.KRCWM:$mask, + VR128X:$src1, VR128X:$src2), + "vmovsd\t{$src2, $src1, $dst {${mask}}|"# + "$dst {${mask}}, $src1, $src2}", + []>, EVEX_K, XD, EVEX_4V, VEX_LIG, + VEX_W, FoldGenData<"VMOVSDZrrk">, + Sched<[SchedWriteFShuffle.XMM]>; + + def VMOVSDZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), + (ins f64x_info.KRCWM:$mask, VR128X:$src1, + VR128X:$src2), + "vmovsd\t{$src2, $src1, $dst {${mask}} {z}|"# + "$dst {${mask}} {z}, $src1, $src2}", + []>, EVEX_KZ, XD, EVEX_4V, VEX_LIG, + VEX_W, FoldGenData<"VMOVSDZrrkz">, + Sched<[SchedWriteFShuffle.XMM]>; +} + +def : InstAlias<"vmovss.s\t{$src2, $src1, $dst|$dst, $src1, $src2}", + (VMOVSSZrr_REV VR128X:$dst, VR128X:$src1, VR128X:$src2), 0>; +def : InstAlias<"vmovss.s\t{$src2, $src1, $dst {${mask}}|"# + "$dst {${mask}}, $src1, $src2}", + (VMOVSSZrrk_REV VR128X:$dst, VK1WM:$mask, + VR128X:$src1, VR128X:$src2), 0>; +def : InstAlias<"vmovss.s\t{$src2, $src1, $dst {${mask}} {z}|"# + "$dst {${mask}} {z}, $src1, $src2}", + (VMOVSSZrrkz_REV VR128X:$dst, VK1WM:$mask, + VR128X:$src1, VR128X:$src2), 0>; +def : InstAlias<"vmovsd.s\t{$src2, $src1, $dst|$dst, $src1, $src2}", + (VMOVSDZrr_REV VR128X:$dst, VR128X:$src1, VR128X:$src2), 0>; +def : InstAlias<"vmovsd.s\t{$src2, $src1, $dst {${mask}}|"# + "$dst {${mask}}, $src1, $src2}", + (VMOVSDZrrk_REV VR128X:$dst, VK1WM:$mask, + VR128X:$src1, VR128X:$src2), 0>; +def : InstAlias<"vmovsd.s\t{$src2, $src1, $dst {${mask}} {z}|"# + "$dst {${mask}} {z}, $src1, $src2}", + (VMOVSDZrrkz_REV VR128X:$dst, VK1WM:$mask, + VR128X:$src1, VR128X:$src2), 0>; + +let Predicates = [HasAVX512, OptForSize] in { + def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))), + (VMOVSSZrr (v4f32 (AVX512_128_SET0)), VR128X:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))), + (VMOVSSZrr (v4i32 (AVX512_128_SET0)), VR128X:$src)>; + + // Move low f32 and clear high bits. + def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))), + (SUBREG_TO_REG (i32 0), + (v4f32 (VMOVSSZrr (v4f32 (AVX512_128_SET0)), + (v4f32 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)))), sub_xmm)>; + def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))), + (SUBREG_TO_REG (i32 0), + (v4i32 (VMOVSSZrr (v4i32 (AVX512_128_SET0)), + (v4i32 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)))), sub_xmm)>; + + def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))), + (SUBREG_TO_REG (i32 0), + (v2f64 (VMOVSDZrr (v2f64 (AVX512_128_SET0)), + (v2f64 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)))), sub_xmm)>; + def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))), + (SUBREG_TO_REG (i32 0), + (v2i64 (VMOVSDZrr (v2i64 (AVX512_128_SET0)), + (v2i64 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)))), sub_xmm)>; + + def : Pat<(v16f32 (X86vzmovl (v16f32 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v4f32 (VMOVSSZrr (v4f32 (AVX512_128_SET0)), + (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm)))), sub_xmm)>; + def : Pat<(v16i32 (X86vzmovl (v16i32 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v4i32 (VMOVSSZrr (v4i32 (AVX512_128_SET0)), + (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm)))), sub_xmm)>; + + def : Pat<(v8f64 (X86vzmovl (v8f64 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v2f64 (VMOVSDZrr (v2f64 (AVX512_128_SET0)), + (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm)))), sub_xmm)>; + + def : Pat<(v8i64 (X86vzmovl (v8i64 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v2i64 (VMOVSDZrr (v2i64 (AVX512_128_SET0)), + (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm)))), sub_xmm)>; + +} + +// Use 128-bit blends for OptForSpeed since BLENDs have better throughput than +// VMOVSS/SD. Unfortunately, loses the ability to use XMM16-31. +let Predicates = [HasAVX512, OptForSpeed] in { + def : Pat<(v16f32 (X86vzmovl (v16f32 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v4f32 (VBLENDPSrri (v4f32 (V_SET0)), + (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm)), + (i8 1))), sub_xmm)>; + def : Pat<(v16i32 (X86vzmovl (v16i32 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v4i32 (VPBLENDWrri (v4i32 (V_SET0)), + (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm)), + (i8 3))), sub_xmm)>; + + def : Pat<(v8f64 (X86vzmovl (v8f64 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v2f64 (VBLENDPDrri (v2f64 (V_SET0)), + (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm)), + (i8 1))), sub_xmm)>; + def : Pat<(v8i64 (X86vzmovl (v8i64 VR512:$src))), + (SUBREG_TO_REG (i32 0), + (v2i64 (VPBLENDWrri (v2i64 (V_SET0)), + (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm)), + (i8 0xf))), sub_xmm)>; +} + +let Predicates = [HasAVX512] in { + + // MOVSSrm zeros the high parts of the register; represent this + // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 + def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))), + (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>; + def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), + (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>; + def : Pat<(v4f32 (X86vzload addr:$src)), + (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>; + + // MOVSDrm zeros the high parts of the register; represent this + // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 + def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))), + (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; + def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), + (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; + def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), + (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; + def : Pat<(v2f64 (X86vzload addr:$src)), + (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; + + // Represent the same patterns above but in the form they appear for + // 256-bit types + def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; + def : Pat<(v8f32 (X86vzmovl (insert_subvector undef, + (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; + def : Pat<(v8f32 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; + def : Pat<(v4f64 (X86vzmovl (insert_subvector undef, + (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; + def : Pat<(v4f64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; + + // Represent the same patterns above but in the form they appear for + // 512-bit types + def : Pat<(v16i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; + def : Pat<(v16f32 (X86vzmovl (insert_subvector undef, + (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; + def : Pat<(v16f32 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; + def : Pat<(v8f64 (X86vzmovl (insert_subvector undef, + (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; + def : Pat<(v8f64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; + + def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, + (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; + + // Extract and store. + def : Pat<(store (f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))), + addr:$dst), + (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>; +} + +let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecLogic.XMM] in { +def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst), + (ins VR128X:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set VR128X:$dst, (v2i64 (X86vzmovl + (v2i64 VR128X:$src))))]>, + EVEX, VEX_W; +} + +let Predicates = [HasAVX512] in { + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))), + (VMOVDI2PDIZrr GR32:$src)>; + + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))), + (VMOV64toPQIZrr GR64:$src)>; + + def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, + (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOV64toPQIZrr GR64:$src)), sub_xmm)>; + + def : Pat<(v8i64 (X86vzmovl (insert_subvector undef, + (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOV64toPQIZrr GR64:$src)), sub_xmm)>; + + // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part. + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (zextloadi64i32 addr:$src))))), + (VMOVDI2PDIZrm addr:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))), + (VMOVDI2PDIZrm addr:$src)>; + def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))), + (VMOVDI2PDIZrm addr:$src)>; + def : Pat<(v4i32 (X86vzload addr:$src)), + (VMOVDI2PDIZrm addr:$src)>; + def : Pat<(v8i32 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; + def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))), + (VMOVQI2PQIZrm addr:$src)>; + def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))), + (VMOVZPQILo2PQIZrr VR128X:$src)>; + def : Pat<(v2i64 (X86vzload addr:$src)), + (VMOVQI2PQIZrm addr:$src)>; + def : Pat<(v4i64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; + + // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext. + def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrr GR32:$src)), sub_xmm)>; + def : Pat<(v16i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrr GR32:$src)), sub_xmm)>; + + // Use regular 128-bit instructions to match 512-bit scalar_to_vec+zext. + def : Pat<(v16i32 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; + def : Pat<(v8i64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 - Non-temporals +//===----------------------------------------------------------------------===// + +def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst), + (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}", + [], SSEPackedInt>, Sched<[SchedWriteVecMoveLS.ZMM.RM]>, + EVEX, T8PD, EVEX_V512, EVEX_CD8<64, CD8VF>; + +let Predicates = [HasVLX] in { + def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst), + (ins i256mem:$src), + "vmovntdqa\t{$src, $dst|$dst, $src}", + [], SSEPackedInt>, Sched<[SchedWriteVecMoveLS.YMM.RM]>, + EVEX, T8PD, EVEX_V256, EVEX_CD8<64, CD8VF>; + + def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst), + (ins i128mem:$src), + "vmovntdqa\t{$src, $dst|$dst, $src}", + [], SSEPackedInt>, Sched<[SchedWriteVecMoveLS.XMM.RM]>, + EVEX, T8PD, EVEX_V128, EVEX_CD8<64, CD8VF>; +} + +multiclass avx512_movnt opc, string OpcodeStr, X86VectorVTInfo _, + X86SchedWriteMoveLS Sched, + PatFrag st_frag = alignednontemporalstore> { + let SchedRW = [Sched.MR], AddedComplexity = 400 in + def mr : AVX512PI, EVEX, EVEX_CD8<_.EltSize, CD8VF>; +} + +multiclass avx512_movnt_vl opc, string OpcodeStr, + AVX512VLVectorVTInfo VTInfo, + X86SchedWriteMoveLSWidths Sched> { + let Predicates = [HasAVX512] in + defm Z : avx512_movnt, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in { + defm Z256 : avx512_movnt, EVEX_V256; + defm Z128 : avx512_movnt, EVEX_V128; + } +} + +defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", avx512vl_i64_info, + SchedWriteVecMoveLSNT>, PD; +defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", avx512vl_f64_info, + SchedWriteFMoveLSNT>, PD, VEX_W; +defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", avx512vl_f32_info, + SchedWriteFMoveLSNT>, PS; + +let Predicates = [HasAVX512], AddedComplexity = 400 in { + def : Pat<(alignednontemporalstore (v16i32 VR512:$src), addr:$dst), + (VMOVNTDQZmr addr:$dst, VR512:$src)>; + def : Pat<(alignednontemporalstore (v32i16 VR512:$src), addr:$dst), + (VMOVNTDQZmr addr:$dst, VR512:$src)>; + def : Pat<(alignednontemporalstore (v64i8 VR512:$src), addr:$dst), + (VMOVNTDQZmr addr:$dst, VR512:$src)>; + + def : Pat<(v8f64 (alignednontemporalload addr:$src)), + (VMOVNTDQAZrm addr:$src)>; + def : Pat<(v16f32 (alignednontemporalload addr:$src)), + (VMOVNTDQAZrm addr:$src)>; + def : Pat<(v8i64 (alignednontemporalload addr:$src)), + (VMOVNTDQAZrm addr:$src)>; +} + +let Predicates = [HasVLX], AddedComplexity = 400 in { + def : Pat<(alignednontemporalstore (v8i32 VR256X:$src), addr:$dst), + (VMOVNTDQZ256mr addr:$dst, VR256X:$src)>; + def : Pat<(alignednontemporalstore (v16i16 VR256X:$src), addr:$dst), + (VMOVNTDQZ256mr addr:$dst, VR256X:$src)>; + def : Pat<(alignednontemporalstore (v32i8 VR256X:$src), addr:$dst), + (VMOVNTDQZ256mr addr:$dst, VR256X:$src)>; + + def : Pat<(v4f64 (alignednontemporalload addr:$src)), + (VMOVNTDQAZ256rm addr:$src)>; + def : Pat<(v8f32 (alignednontemporalload addr:$src)), + (VMOVNTDQAZ256rm addr:$src)>; + def : Pat<(v4i64 (alignednontemporalload addr:$src)), + (VMOVNTDQAZ256rm addr:$src)>; + + def : Pat<(alignednontemporalstore (v4i32 VR128X:$src), addr:$dst), + (VMOVNTDQZ128mr addr:$dst, VR128X:$src)>; + def : Pat<(alignednontemporalstore (v8i16 VR128X:$src), addr:$dst), + (VMOVNTDQZ128mr addr:$dst, VR128X:$src)>; + def : Pat<(alignednontemporalstore (v16i8 VR128X:$src), addr:$dst), + (VMOVNTDQZ128mr addr:$dst, VR128X:$src)>; + + def : Pat<(v2f64 (alignednontemporalload addr:$src)), + (VMOVNTDQAZ128rm addr:$src)>; + def : Pat<(v4f32 (alignednontemporalload addr:$src)), + (VMOVNTDQAZ128rm addr:$src)>; + def : Pat<(v2i64 (alignednontemporalload addr:$src)), + (VMOVNTDQAZ128rm addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 - Integer arithmetic +// +multiclass avx512_binop_rm opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _, X86FoldableSchedWrite sched, + bit IsCommutable = 0> { + defm rr : AVX512_maskable, AVX512BIBase, EVEX_4V, + Sched<[sched]>; + + defm rm : AVX512_maskable, + AVX512BIBase, EVEX_4V, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_binop_rmb opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _, X86FoldableSchedWrite sched, + bit IsCommutable = 0> : + avx512_binop_rm { + defm rmb : AVX512_maskable, + AVX512BIBase, EVEX_4V, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_binop_rm_vl opc, string OpcodeStr, SDNode OpNode, + AVX512VLVectorVTInfo VTInfo, + X86SchedWriteWidths sched, Predicate prd, + bit IsCommutable = 0> { + let Predicates = [prd] in + defm Z : avx512_binop_rm, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_binop_rm, EVEX_V256; + defm Z128 : avx512_binop_rm, EVEX_V128; + } +} + +multiclass avx512_binop_rmb_vl opc, string OpcodeStr, SDNode OpNode, + AVX512VLVectorVTInfo VTInfo, + X86SchedWriteWidths sched, Predicate prd, + bit IsCommutable = 0> { + let Predicates = [prd] in + defm Z : avx512_binop_rmb, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_binop_rmb, EVEX_V256; + defm Z128 : avx512_binop_rmb, EVEX_V128; + } +} + +multiclass avx512_binop_rm_vl_q opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate prd, + bit IsCommutable = 0> { + defm NAME : avx512_binop_rmb_vl, + VEX_W, EVEX_CD8<64, CD8VF>; +} + +multiclass avx512_binop_rm_vl_d opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate prd, + bit IsCommutable = 0> { + defm NAME : avx512_binop_rmb_vl, EVEX_CD8<32, CD8VF>; +} + +multiclass avx512_binop_rm_vl_w opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate prd, + bit IsCommutable = 0> { + defm NAME : avx512_binop_rm_vl, EVEX_CD8<16, CD8VF>, + VEX_WIG; +} + +multiclass avx512_binop_rm_vl_b opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate prd, + bit IsCommutable = 0> { + defm NAME : avx512_binop_rm_vl, EVEX_CD8<8, CD8VF>, + VEX_WIG; +} + +multiclass avx512_binop_rm_vl_dq opc_d, bits<8> opc_q, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched, + Predicate prd, bit IsCommutable = 0> { + defm Q : avx512_binop_rm_vl_q; + + defm D : avx512_binop_rm_vl_d; +} + +multiclass avx512_binop_rm_vl_bw opc_b, bits<8> opc_w, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched, + Predicate prd, bit IsCommutable = 0> { + defm W : avx512_binop_rm_vl_w; + + defm B : avx512_binop_rm_vl_b; +} + +multiclass avx512_binop_rm_vl_all opc_b, bits<8> opc_w, + bits<8> opc_d, bits<8> opc_q, + string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, + bit IsCommutable = 0> { + defm NAME : avx512_binop_rm_vl_dq, + avx512_binop_rm_vl_bw; +} + +multiclass avx512_binop_rm2 opc, string OpcodeStr, + X86FoldableSchedWrite sched, + SDNode OpNode,X86VectorVTInfo _Src, + X86VectorVTInfo _Dst, X86VectorVTInfo _Brdct, + bit IsCommutable = 0> { + defm rr : AVX512_maskable, + AVX512BIBase, EVEX_4V, Sched<[sched]>; + defm rm : AVX512_maskable, + AVX512BIBase, EVEX_4V, + Sched<[sched.Folded, ReadAfterLd]>; + + defm rmb : AVX512_maskable, + AVX512BIBase, EVEX_4V, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add, + SchedWriteVecALU, 1>; +defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub, + SchedWriteVecALU, 0>; +defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds, + SchedWriteVecALU, HasBWI, 1>; +defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs, + SchedWriteVecALU, HasBWI, 0>; +defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus, + SchedWriteVecALU, HasBWI, 1>; +defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus, + SchedWriteVecALU, HasBWI, 0>; +defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul, + SchedWritePMULLD, HasAVX512, 1>, T8PD; +defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul, + SchedWriteVecIMul, HasBWI, 1>; +defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul, + SchedWriteVecIMul, HasDQI, 1>, T8PD, + NotEVEX2VEXConvertible; +defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SchedWriteVecIMul, + HasBWI, 1>; +defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SchedWriteVecIMul, + HasBWI, 1>; +defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, + SchedWriteVecIMul, HasBWI, 1>, T8PD; +defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg, + SchedWriteVecALU, HasBWI, 1>; +defm VPMULDQ : avx512_binop_rm_vl_q<0x28, "vpmuldq", X86pmuldq, + SchedWriteVecIMul, HasAVX512, 1>, T8PD; +defm VPMULUDQ : avx512_binop_rm_vl_q<0xF4, "vpmuludq", X86pmuludq, + SchedWriteVecIMul, HasAVX512, 1>; + +multiclass avx512_binop_all opc, string OpcodeStr, + X86SchedWriteWidths sched, + AVX512VLVectorVTInfo _SrcVTInfo, + AVX512VLVectorVTInfo _DstVTInfo, + SDNode OpNode, Predicate prd, bit IsCommutable = 0> { + let Predicates = [prd] in + defm NAME#Z : avx512_binop_rm2, + EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W; + let Predicates = [HasVLX, prd] in { + defm NAME#Z256 : avx512_binop_rm2, + EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W; + defm NAME#Z128 : avx512_binop_rm2, + EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W; + } +} + +defm VPMULTISHIFTQB : avx512_binop_all<0x83, "vpmultishiftqb", SchedWriteVecALU, + avx512vl_i8_info, avx512vl_i8_info, + X86multishift, HasVBMI, 0>, T8PD; + +multiclass avx512_packs_rmb opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _Src, X86VectorVTInfo _Dst, + X86FoldableSchedWrite sched> { + defm rmb : AVX512_maskable, + EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_packs_rm opc, string OpcodeStr, + SDNode OpNode,X86VectorVTInfo _Src, + X86VectorVTInfo _Dst, X86FoldableSchedWrite sched, + bit IsCommutable = 0> { + defm rr : AVX512_maskable, + EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V, Sched<[sched]>; + defm rm : AVX512_maskable, + EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_packs_all_i32_i16 opc, string OpcodeStr, + SDNode OpNode> { + let Predicates = [HasBWI] in + defm NAME#Z : avx512_packs_rm, + avx512_packs_rmb, EVEX_V512; + let Predicates = [HasBWI, HasVLX] in { + defm NAME#Z256 : avx512_packs_rm, + avx512_packs_rmb, + EVEX_V256; + defm NAME#Z128 : avx512_packs_rm, + avx512_packs_rmb, + EVEX_V128; + } +} +multiclass avx512_packs_all_i16_i8 opc, string OpcodeStr, + SDNode OpNode> { + let Predicates = [HasBWI] in + defm NAME#Z : avx512_packs_rm, EVEX_V512, VEX_WIG; + let Predicates = [HasBWI, HasVLX] in { + defm NAME#Z256 : avx512_packs_rm, + EVEX_V256, VEX_WIG; + defm NAME#Z128 : avx512_packs_rm, + EVEX_V128, VEX_WIG; + } +} + +multiclass avx512_vpmadd opc, string OpcodeStr, + SDNode OpNode, AVX512VLVectorVTInfo _Src, + AVX512VLVectorVTInfo _Dst, bit IsCommutable = 0> { + let Predicates = [HasBWI] in + defm NAME#Z : avx512_packs_rm, EVEX_V512; + let Predicates = [HasBWI, HasVLX] in { + defm NAME#Z256 : avx512_packs_rm, EVEX_V256; + defm NAME#Z128 : avx512_packs_rm, EVEX_V128; + } +} + +defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, AVX512BIBase; +defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, AVX5128IBase; +defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase; +defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase; + +defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw, + avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD, VEX_WIG; +defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd, + avx512vl_i16_info, avx512vl_i32_info, 1>, AVX512BIBase, VEX_WIG; + +defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax, + SchedWriteVecALU, HasBWI, 1>, T8PD; +defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax, + SchedWriteVecALU, HasBWI, 1>; +defm VPMAXSD : avx512_binop_rm_vl_d<0x3D, "vpmaxsd", smax, + SchedWriteVecALU, HasAVX512, 1>, T8PD; +defm VPMAXSQ : avx512_binop_rm_vl_q<0x3D, "vpmaxsq", smax, + SchedWriteVecALU, HasAVX512, 1>, T8PD, + NotEVEX2VEXConvertible; + +defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax, + SchedWriteVecALU, HasBWI, 1>; +defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax, + SchedWriteVecALU, HasBWI, 1>, T8PD; +defm VPMAXUD : avx512_binop_rm_vl_d<0x3F, "vpmaxud", umax, + SchedWriteVecALU, HasAVX512, 1>, T8PD; +defm VPMAXUQ : avx512_binop_rm_vl_q<0x3F, "vpmaxuq", umax, + SchedWriteVecALU, HasAVX512, 1>, T8PD, + NotEVEX2VEXConvertible; + +defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin, + SchedWriteVecALU, HasBWI, 1>, T8PD; +defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin, + SchedWriteVecALU, HasBWI, 1>; +defm VPMINSD : avx512_binop_rm_vl_d<0x39, "vpminsd", smin, + SchedWriteVecALU, HasAVX512, 1>, T8PD; +defm VPMINSQ : avx512_binop_rm_vl_q<0x39, "vpminsq", smin, + SchedWriteVecALU, HasAVX512, 1>, T8PD, + NotEVEX2VEXConvertible; + +defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin, + SchedWriteVecALU, HasBWI, 1>; +defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin, + SchedWriteVecALU, HasBWI, 1>, T8PD; +defm VPMINUD : avx512_binop_rm_vl_d<0x3B, "vpminud", umin, + SchedWriteVecALU, HasAVX512, 1>, T8PD; +defm VPMINUQ : avx512_binop_rm_vl_q<0x3B, "vpminuq", umin, + SchedWriteVecALU, HasAVX512, 1>, T8PD, + NotEVEX2VEXConvertible; + +// PMULLQ: Use 512bit version to implement 128/256 bit in case NoVLX. +let Predicates = [HasDQI, NoVLX] in { + def : Pat<(v4i64 (mul (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))), + (EXTRACT_SUBREG + (VPMULLQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)), + sub_ymm)>; + + def : Pat<(v2i64 (mul (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG + (VPMULLQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)), + sub_xmm)>; +} + +// PMULLQ: Use 512bit version to implement 128/256 bit in case NoVLX. +let Predicates = [HasDQI, NoVLX] in { + def : Pat<(v4i64 (mul (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))), + (EXTRACT_SUBREG + (VPMULLQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)), + sub_ymm)>; + + def : Pat<(v2i64 (mul (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG + (VPMULLQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)), + sub_xmm)>; +} + +multiclass avx512_min_max_lowering { + def : Pat<(v4i64 (OpNode VR256X:$src1, VR256X:$src2)), + (EXTRACT_SUBREG + (Instr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)), + sub_ymm)>; + + def : Pat<(v2i64 (OpNode VR128X:$src1, VR128X:$src2)), + (EXTRACT_SUBREG + (Instr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)), + sub_xmm)>; +} + +let Predicates = [HasAVX512, NoVLX] in { + defm : avx512_min_max_lowering; + defm : avx512_min_max_lowering; + defm : avx512_min_max_lowering; + defm : avx512_min_max_lowering; +} + +//===----------------------------------------------------------------------===// +// AVX-512 Logical Instructions +//===----------------------------------------------------------------------===// + +// OpNodeMsk is the OpNode to use when element size is important. OpNode will +// be set to null_frag for 32-bit elements. +multiclass avx512_logic_rm opc, string OpcodeStr, + SDPatternOperator OpNode, + SDNode OpNodeMsk, X86FoldableSchedWrite sched, + X86VectorVTInfo _, bit IsCommutable = 0> { + let hasSideEffects = 0 in + defm rr : AVX512_maskable_logic, AVX512BIBase, EVEX_4V, + Sched<[sched]>; + + let hasSideEffects = 0, mayLoad = 1 in + defm rm : AVX512_maskable_logic, + AVX512BIBase, EVEX_4V, + Sched<[sched.Folded, ReadAfterLd]>; +} + +// OpNodeMsk is the OpNode to use where element size is important. So use +// for all of the broadcast patterns. +multiclass avx512_logic_rmb opc, string OpcodeStr, + SDPatternOperator OpNode, + SDNode OpNodeMsk, X86FoldableSchedWrite sched, X86VectorVTInfo _, + bit IsCommutable = 0> : + avx512_logic_rm { + defm rmb : AVX512_maskable_logic, + AVX512BIBase, EVEX_4V, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_logic_rmb_vl opc, string OpcodeStr, + SDPatternOperator OpNode, + SDNode OpNodeMsk, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo, + bit IsCommutable = 0> { + let Predicates = [HasAVX512] in + defm Z : avx512_logic_rmb, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in { + defm Z256 : avx512_logic_rmb, EVEX_V256; + defm Z128 : avx512_logic_rmb, EVEX_V128; + } +} + +multiclass avx512_logic_rm_vl_dq opc_d, bits<8> opc_q, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched, + bit IsCommutable = 0> { + defm Q : avx512_logic_rmb_vl, + VEX_W, EVEX_CD8<64, CD8VF>; + defm D : avx512_logic_rmb_vl, + EVEX_CD8<32, CD8VF>; +} + +defm VPAND : avx512_logic_rm_vl_dq<0xDB, 0xDB, "vpand", and, + SchedWriteVecLogic, 1>; +defm VPOR : avx512_logic_rm_vl_dq<0xEB, 0xEB, "vpor", or, + SchedWriteVecLogic, 1>; +defm VPXOR : avx512_logic_rm_vl_dq<0xEF, 0xEF, "vpxor", xor, + SchedWriteVecLogic, 1>; +defm VPANDN : avx512_logic_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp, + SchedWriteVecLogic>; + +//===----------------------------------------------------------------------===// +// AVX-512 FP arithmetic +//===----------------------------------------------------------------------===// + +multiclass avx512_fp_scalar opc, string OpcodeStr,X86VectorVTInfo _, + SDNode OpNode, SDNode VecNode, + X86FoldableSchedWrite sched, bit IsCommutable> { + let ExeDomain = _.ExeDomain in { + defm rr_Int : AVX512_maskable_scalar, + Sched<[sched]>; + + defm rm_Int : AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + let isCodeGenOnly = 1, Predicates = [HasAVX512] in { + def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst), + (ins _.FRC:$src1, _.FRC:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>, + Sched<[sched]> { + let isCommutable = IsCommutable; + } + def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst), + (ins _.FRC:$src1, _.ScalarMemOp:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.FRC:$dst, (OpNode _.FRC:$src1, + (_.ScalarLdFrag addr:$src2)))]>, + Sched<[sched.Folded, ReadAfterLd]>; + } + } +} + +multiclass avx512_fp_scalar_round opc, string OpcodeStr,X86VectorVTInfo _, + SDNode VecNode, X86FoldableSchedWrite sched, + bit IsCommutable = 0> { + let ExeDomain = _.ExeDomain in + defm rrb_Int : AVX512_maskable_scalar, + EVEX_B, EVEX_RC, Sched<[sched]>; +} +multiclass avx512_fp_scalar_sae opc, string OpcodeStr,X86VectorVTInfo _, + SDNode OpNode, SDNode VecNode, SDNode SaeNode, + X86FoldableSchedWrite sched, bit IsCommutable> { + let ExeDomain = _.ExeDomain in { + defm rr_Int : AVX512_maskable_scalar, + Sched<[sched]>; + + defm rm_Int : AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + + let isCodeGenOnly = 1, Predicates = [HasAVX512] in { + def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst), + (ins _.FRC:$src1, _.FRC:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>, + Sched<[sched]> { + let isCommutable = IsCommutable; + } + def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst), + (ins _.FRC:$src1, _.ScalarMemOp:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.FRC:$dst, (OpNode _.FRC:$src1, + (_.ScalarLdFrag addr:$src2)))]>, + Sched<[sched.Folded, ReadAfterLd]>; + } + + defm rrb_Int : AVX512_maskable_scalar, EVEX_B, + Sched<[sched]>; + } +} + +multiclass avx512_binop_s_round opc, string OpcodeStr, SDNode OpNode, + SDNode VecNode, X86SchedWriteSizes sched, + bit IsCommutable> { + defm SSZ : avx512_fp_scalar, + avx512_fp_scalar_round, + XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>; + defm SDZ : avx512_fp_scalar, + avx512_fp_scalar_round, + XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>; +} + +multiclass avx512_binop_s_sae opc, string OpcodeStr, SDNode OpNode, + SDNode VecNode, SDNode SaeNode, + X86SchedWriteSizes sched, bit IsCommutable> { + defm SSZ : avx512_fp_scalar_sae, + XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>; + defm SDZ : avx512_fp_scalar_sae, + XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>; +} +defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnds, + SchedWriteFAddSizes, 1>; +defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnds, + SchedWriteFMulSizes, 1>; +defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnds, + SchedWriteFAddSizes, 0>; +defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnds, + SchedWriteFDivSizes, 0>; +defm VMIN : avx512_binop_s_sae<0x5D, "vmin", X86fmin, X86fmins, X86fminRnds, + SchedWriteFCmpSizes, 0>; +defm VMAX : avx512_binop_s_sae<0x5F, "vmax", X86fmax, X86fmaxs, X86fmaxRnds, + SchedWriteFCmpSizes, 0>; + +// MIN/MAX nodes are commutable under "unsafe-fp-math". In this case we use +// X86fminc and X86fmaxc instead of X86fmin and X86fmax +multiclass avx512_comutable_binop_s opc, string OpcodeStr, + X86VectorVTInfo _, SDNode OpNode, + X86FoldableSchedWrite sched> { + let isCodeGenOnly = 1, Predicates = [HasAVX512], ExeDomain = _.ExeDomain in { + def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst), + (ins _.FRC:$src1, _.FRC:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>, + Sched<[sched]> { + let isCommutable = 1; + } + def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst), + (ins _.FRC:$src1, _.ScalarMemOp:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set _.FRC:$dst, (OpNode _.FRC:$src1, + (_.ScalarLdFrag addr:$src2)))]>, + Sched<[sched.Folded, ReadAfterLd]>; + } +} +defm VMINCSSZ : avx512_comutable_binop_s<0x5D, "vminss", f32x_info, X86fminc, + SchedWriteFCmp.Scl>, XS, EVEX_4V, + VEX_LIG, EVEX_CD8<32, CD8VT1>; + +defm VMINCSDZ : avx512_comutable_binop_s<0x5D, "vminsd", f64x_info, X86fminc, + SchedWriteFCmp.Scl>, XD, VEX_W, EVEX_4V, + VEX_LIG, EVEX_CD8<64, CD8VT1>; + +defm VMAXCSSZ : avx512_comutable_binop_s<0x5F, "vmaxss", f32x_info, X86fmaxc, + SchedWriteFCmp.Scl>, XS, EVEX_4V, + VEX_LIG, EVEX_CD8<32, CD8VT1>; + +defm VMAXCSDZ : avx512_comutable_binop_s<0x5F, "vmaxsd", f64x_info, X86fmaxc, + SchedWriteFCmp.Scl>, XD, VEX_W, EVEX_4V, + VEX_LIG, EVEX_CD8<64, CD8VT1>; + +multiclass avx512_fp_packed opc, string OpcodeStr, SDPatternOperator OpNode, + X86VectorVTInfo _, X86FoldableSchedWrite sched, + bit IsCommutable, + bit IsKZCommutable = IsCommutable> { + let ExeDomain = _.ExeDomain, hasSideEffects = 0 in { + defm rr: AVX512_maskable, + EVEX_4V, Sched<[sched]>; + let mayLoad = 1 in { + defm rm: AVX512_maskable, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + defm rmb: AVX512_maskable, + EVEX_4V, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } + } +} + +multiclass avx512_fp_round_packed opc, string OpcodeStr, + SDPatternOperator OpNodeRnd, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm rrb: AVX512_maskable, + EVEX_4V, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +multiclass avx512_fp_sae_packed opc, string OpcodeStr, + SDPatternOperator OpNodeRnd, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm rrb: AVX512_maskable, + EVEX_4V, EVEX_B, Sched<[sched]>; +} + +multiclass avx512_fp_binop_p opc, string OpcodeStr, SDPatternOperator OpNode, + Predicate prd, X86SchedWriteSizes sched, + bit IsCommutable = 0, + bit IsPD128Commutable = IsCommutable> { + let Predicates = [prd] in { + defm PSZ : avx512_fp_packed, EVEX_V512, PS, + EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp_packed, EVEX_V512, PD, VEX_W, + EVEX_CD8<64, CD8VF>; + } + + // Define only if AVX512VL feature is present. + let Predicates = [prd, HasVLX] in { + defm PSZ128 : avx512_fp_packed, EVEX_V128, PS, + EVEX_CD8<32, CD8VF>; + defm PSZ256 : avx512_fp_packed, EVEX_V256, PS, + EVEX_CD8<32, CD8VF>; + defm PDZ128 : avx512_fp_packed, EVEX_V128, PD, VEX_W, + EVEX_CD8<64, CD8VF>; + defm PDZ256 : avx512_fp_packed, EVEX_V256, PD, VEX_W, + EVEX_CD8<64, CD8VF>; + } +} + +multiclass avx512_fp_binop_p_round opc, string OpcodeStr, SDNode OpNodeRnd, + X86SchedWriteSizes sched> { + defm PSZ : avx512_fp_round_packed, + EVEX_V512, PS, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp_round_packed, + EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>; +} + +multiclass avx512_fp_binop_p_sae opc, string OpcodeStr, SDNode OpNodeRnd, + X86SchedWriteSizes sched> { + defm PSZ : avx512_fp_sae_packed, + EVEX_V512, PS, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp_sae_packed, + EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>; +} + +defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, HasAVX512, + SchedWriteFAddSizes, 1>, + avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd, SchedWriteFAddSizes>; +defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, HasAVX512, + SchedWriteFMulSizes, 1>, + avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd, SchedWriteFMulSizes>; +defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub, HasAVX512, + SchedWriteFAddSizes>, + avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd, SchedWriteFAddSizes>; +defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv, HasAVX512, + SchedWriteFDivSizes>, + avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd, SchedWriteFDivSizes>; +defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, HasAVX512, + SchedWriteFCmpSizes, 0>, + avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd, SchedWriteFCmpSizes>; +defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, HasAVX512, + SchedWriteFCmpSizes, 0>, + avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd, SchedWriteFCmpSizes>; +let isCodeGenOnly = 1 in { + defm VMINC : avx512_fp_binop_p<0x5D, "vmin", X86fminc, HasAVX512, + SchedWriteFCmpSizes, 1>; + defm VMAXC : avx512_fp_binop_p<0x5F, "vmax", X86fmaxc, HasAVX512, + SchedWriteFCmpSizes, 1>; +} +defm VAND : avx512_fp_binop_p<0x54, "vand", null_frag, HasDQI, + SchedWriteFLogicSizes, 1>; +defm VANDN : avx512_fp_binop_p<0x55, "vandn", null_frag, HasDQI, + SchedWriteFLogicSizes, 0>; +defm VOR : avx512_fp_binop_p<0x56, "vor", null_frag, HasDQI, + SchedWriteFLogicSizes, 1>; +defm VXOR : avx512_fp_binop_p<0x57, "vxor", null_frag, HasDQI, + SchedWriteFLogicSizes, 1>; + +// Patterns catch floating point selects with bitcasted integer logic ops. +multiclass avx512_fp_logical_lowering { +let Predicates = [prd] in { + // Masked register-register logical operations. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (bitconvert (_.i64VT (OpNode _.RC:$src1, _.RC:$src2))), + _.RC:$src0)), + (!cast(InstrStr#rrk) _.RC:$src0, _.KRCWM:$mask, + _.RC:$src1, _.RC:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (bitconvert (_.i64VT (OpNode _.RC:$src1, _.RC:$src2))), + _.ImmAllZerosV)), + (!cast(InstrStr#rrkz) _.KRCWM:$mask, _.RC:$src1, + _.RC:$src2)>; + // Masked register-memory logical operations. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (bitconvert (_.i64VT (OpNode _.RC:$src1, + (load addr:$src2)))), + _.RC:$src0)), + (!cast(InstrStr#rmk) _.RC:$src0, _.KRCWM:$mask, + _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (bitconvert (_.i64VT (OpNode _.RC:$src1, (load addr:$src2)))), + _.ImmAllZerosV)), + (!cast(InstrStr#rmkz) _.KRCWM:$mask, _.RC:$src1, + addr:$src2)>; + // Register-broadcast logical operations. + def : Pat<(_.i64VT (OpNode _.RC:$src1, + (bitconvert (_.VT (X86VBroadcast + (_.ScalarLdFrag addr:$src2)))))), + (!cast(InstrStr#rmb) _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (bitconvert + (_.i64VT (OpNode _.RC:$src1, + (bitconvert (_.VT + (X86VBroadcast + (_.ScalarLdFrag addr:$src2))))))), + _.RC:$src0)), + (!cast(InstrStr#rmbk) _.RC:$src0, _.KRCWM:$mask, + _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (bitconvert + (_.i64VT (OpNode _.RC:$src1, + (bitconvert (_.VT + (X86VBroadcast + (_.ScalarLdFrag addr:$src2))))))), + _.ImmAllZerosV)), + (!cast(InstrStr#rmbkz) _.KRCWM:$mask, + _.RC:$src1, addr:$src2)>; +} +} + +multiclass avx512_fp_logical_lowering_sizes { + defm : avx512_fp_logical_lowering; + defm : avx512_fp_logical_lowering; + defm : avx512_fp_logical_lowering; + defm : avx512_fp_logical_lowering; + defm : avx512_fp_logical_lowering; + defm : avx512_fp_logical_lowering; +} + +defm : avx512_fp_logical_lowering_sizes<"VPAND", and>; +defm : avx512_fp_logical_lowering_sizes<"VPOR", or>; +defm : avx512_fp_logical_lowering_sizes<"VPXOR", xor>; +defm : avx512_fp_logical_lowering_sizes<"VPANDN", X86andnp>; + +let Predicates = [HasVLX,HasDQI] in { + // Use packed logical operations for scalar ops. + def : Pat<(f64 (X86fand FR64X:$src1, FR64X:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VANDPDZ128rr (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)), + (v2f64 (COPY_TO_REGCLASS FR64X:$src2, VR128X)))), + FR64X)>; + def : Pat<(f64 (X86for FR64X:$src1, FR64X:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VORPDZ128rr (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)), + (v2f64 (COPY_TO_REGCLASS FR64X:$src2, VR128X)))), + FR64X)>; + def : Pat<(f64 (X86fxor FR64X:$src1, FR64X:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VXORPDZ128rr (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)), + (v2f64 (COPY_TO_REGCLASS FR64X:$src2, VR128X)))), + FR64X)>; + def : Pat<(f64 (X86fandn FR64X:$src1, FR64X:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VANDNPDZ128rr (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)), + (v2f64 (COPY_TO_REGCLASS FR64X:$src2, VR128X)))), + FR64X)>; + + def : Pat<(f32 (X86fand FR32X:$src1, FR32X:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VANDPSZ128rr (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)), + (v4f32 (COPY_TO_REGCLASS FR32X:$src2, VR128X)))), + FR32X)>; + def : Pat<(f32 (X86for FR32X:$src1, FR32X:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VORPSZ128rr (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)), + (v4f32 (COPY_TO_REGCLASS FR32X:$src2, VR128X)))), + FR32X)>; + def : Pat<(f32 (X86fxor FR32X:$src1, FR32X:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VXORPSZ128rr (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)), + (v4f32 (COPY_TO_REGCLASS FR32X:$src2, VR128X)))), + FR32X)>; + def : Pat<(f32 (X86fandn FR32X:$src1, FR32X:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VANDNPSZ128rr (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)), + (v4f32 (COPY_TO_REGCLASS FR32X:$src2, VR128X)))), + FR32X)>; +} + +multiclass avx512_fp_scalef_p opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rr: AVX512_maskable, + EVEX_4V, Sched<[sched]>; + defm rm: AVX512_maskable, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + defm rmb: AVX512_maskable, + EVEX_4V, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fp_scalef_scalar opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rr: AVX512_maskable_scalar, + Sched<[sched]>; + defm rm: AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fp_scalef_all opc, bits<8> opcScaler, string OpcodeStr, + SDNode OpNode, SDNode OpNodeScal, + X86SchedWriteWidths sched> { + defm PSZ : avx512_fp_scalef_p, + avx512_fp_round_packed, + EVEX_V512, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp_scalef_p, + avx512_fp_round_packed, + EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; + defm SSZ : avx512_fp_scalef_scalar, + avx512_fp_scalar_round, + EVEX_4V,EVEX_CD8<32, CD8VT1>; + defm SDZ : avx512_fp_scalef_scalar, + avx512_fp_scalar_round, + EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; + + // Define only if AVX512VL feature is present. + let Predicates = [HasVLX] in { + defm PSZ128 : avx512_fp_scalef_p, + EVEX_V128, EVEX_CD8<32, CD8VF>; + defm PSZ256 : avx512_fp_scalef_p, + EVEX_V256, EVEX_CD8<32, CD8VF>; + defm PDZ128 : avx512_fp_scalef_p, + EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>; + defm PDZ256 : avx512_fp_scalef_p, + EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>; + } +} +defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef, X86scalefs, + SchedWriteFAdd>, T8PD, NotEVEX2VEXConvertible; + +//===----------------------------------------------------------------------===// +// AVX-512 VPTESTM instructions +//===----------------------------------------------------------------------===// + +multiclass avx512_vptest opc, string OpcodeStr, PatFrag OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + string Name> { + let ExeDomain = _.ExeDomain in { + let isCommutable = 1 in + defm rr : AVX512_maskable_cmp, + EVEX_4V, Sched<[sched]>; + defm rm : AVX512_maskable_cmp, + EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + } + + // Patterns for compare with 0 that just use the same source twice. + def : Pat<(_.KVT (OpNode _.RC:$src, _.ImmAllZerosV)), + (_.KVT (!cast(Name # _.ZSuffix # "rr") + _.RC:$src, _.RC:$src))>; + + def : Pat<(_.KVT (and _.KRC:$mask, (OpNode _.RC:$src, _.ImmAllZerosV))), + (_.KVT (!cast(Name # _.ZSuffix # "rrk") + _.KRC:$mask, _.RC:$src, _.RC:$src))>; +} + +multiclass avx512_vptest_mb opc, string OpcodeStr, PatFrag OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm rmb : AVX512_maskable_cmp, + EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +// Use 512bit version to implement 128/256 bit in case NoVLX. +multiclass avx512_vptest_lowering { + def : Pat<(_.KVT (OpNode (bitconvert (_.i64VT (and _.RC:$src1, _.RC:$src2))), + _.ImmAllZerosV)), + (_.KVT (COPY_TO_REGCLASS + (!cast(Name # "Zrr") + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src1, _.SubRegIdx), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src2, _.SubRegIdx)), + _.KRC))>; + + def : Pat<(_.KVT (and _.KRC:$mask, + (OpNode (bitconvert (_.i64VT (and _.RC:$src1, _.RC:$src2))), + _.ImmAllZerosV))), + (COPY_TO_REGCLASS + (!cast(Name # "Zrrk") + (COPY_TO_REGCLASS _.KRC:$mask, ExtendInfo.KRC), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src1, _.SubRegIdx), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src2, _.SubRegIdx)), + _.KRC)>; + + def : Pat<(_.KVT (OpNode _.RC:$src, _.ImmAllZerosV)), + (_.KVT (COPY_TO_REGCLASS + (!cast(Name # "Zrr") + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src, _.SubRegIdx), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src, _.SubRegIdx)), + _.KRC))>; + + def : Pat<(_.KVT (and _.KRC:$mask, (OpNode _.RC:$src, _.ImmAllZerosV))), + (COPY_TO_REGCLASS + (!cast(Name # "Zrrk") + (COPY_TO_REGCLASS _.KRC:$mask, ExtendInfo.KRC), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src, _.SubRegIdx), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src, _.SubRegIdx)), + _.KRC)>; +} + +multiclass avx512_vptest_dq_sizes opc, string OpcodeStr, PatFrag OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo _> { + let Predicates = [HasAVX512] in + defm Z : avx512_vptest, + avx512_vptest_mb, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in { + defm Z256 : avx512_vptest, + avx512_vptest_mb, EVEX_V256; + defm Z128 : avx512_vptest, + avx512_vptest_mb, EVEX_V128; + } + let Predicates = [HasAVX512, NoVLX] in { + defm Z256_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info256, NAME>; + defm Z128_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info128, NAME>; + } +} + +multiclass avx512_vptest_dq opc, string OpcodeStr, PatFrag OpNode, + X86SchedWriteWidths sched> { + defm D : avx512_vptest_dq_sizes; + defm Q : avx512_vptest_dq_sizes, VEX_W; +} + +multiclass avx512_vptest_wb opc, string OpcodeStr, + PatFrag OpNode, X86SchedWriteWidths sched> { + let Predicates = [HasBWI] in { + defm WZ: avx512_vptest, EVEX_V512, VEX_W; + defm BZ: avx512_vptest, EVEX_V512; + } + let Predicates = [HasVLX, HasBWI] in { + + defm WZ256: avx512_vptest, EVEX_V256, VEX_W; + defm WZ128: avx512_vptest, EVEX_V128, VEX_W; + defm BZ256: avx512_vptest, EVEX_V256; + defm BZ128: avx512_vptest, EVEX_V128; + } + + let Predicates = [HasAVX512, NoVLX] in { + defm BZ256_Alt : avx512_vptest_lowering; + defm BZ128_Alt : avx512_vptest_lowering; + defm WZ256_Alt : avx512_vptest_lowering; + defm WZ128_Alt : avx512_vptest_lowering; + } +} + +// These patterns are used to match vptestm/vptestnm. We don't treat pcmpeqm +// as commutable here because we already canonicalized all zeros vectors to the +// RHS during lowering. +def X86pcmpeqm : PatFrag<(ops node:$src1, node:$src2), + (setcc node:$src1, node:$src2, SETEQ)>; +def X86pcmpnem : PatFrag<(ops node:$src1, node:$src2), + (setcc node:$src1, node:$src2, SETNE)>; + +multiclass avx512_vptest_all_forms opc_wb, bits<8> opc_dq, string OpcodeStr, + PatFrag OpNode, X86SchedWriteWidths sched> : + avx512_vptest_wb, + avx512_vptest_dq; + +defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86pcmpnem, + SchedWriteVecLogic>, T8PD; +defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86pcmpeqm, + SchedWriteVecLogic>, T8XS; + +//===----------------------------------------------------------------------===// +// AVX-512 Shift instructions +//===----------------------------------------------------------------------===// + +multiclass avx512_shift_rmi opc, Format ImmFormR, Format ImmFormM, + string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm ri : AVX512_maskable, + Sched<[sched]>; + defm mi : AVX512_maskable, + Sched<[sched.Folded]>; + } +} + +multiclass avx512_shift_rmbi opc, Format ImmFormM, + string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm mbi : AVX512_maskable, + EVEX_B, Sched<[sched.Folded]>; +} + +multiclass avx512_shift_rrm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, ValueType SrcVT, + PatFrag bc_frag, X86VectorVTInfo _> { + // src2 is always 128-bit + let ExeDomain = _.ExeDomain in { + defm rr : AVX512_maskable, + AVX512BIBase, EVEX_4V, Sched<[sched]>; + defm rm : AVX512_maskable, + AVX512BIBase, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_shift_sizes opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, ValueType SrcVT, + PatFrag bc_frag, AVX512VLVectorVTInfo VTInfo, + Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_shift_rrm, EVEX_V512, + EVEX_CD8 ; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_shift_rrm, EVEX_V256, + EVEX_CD8; + defm Z128 : avx512_shift_rrm, EVEX_V128, + EVEX_CD8; + } +} + +multiclass avx512_shift_types opcd, bits<8> opcq, bits<8> opcw, + string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, + bit NotEVEX2VEXConvertibleQ = 0> { + defm D : avx512_shift_sizes; + let notEVEX2VEXConvertible = NotEVEX2VEXConvertibleQ in + defm Q : avx512_shift_sizes, VEX_W; + defm W : avx512_shift_sizes; +} + +multiclass avx512_shift_rmi_sizes opc, Format ImmFormR, Format ImmFormM, + string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo> { + let Predicates = [HasAVX512] in + defm Z: avx512_shift_rmi, + avx512_shift_rmbi, EVEX_V512; + let Predicates = [HasAVX512, HasVLX] in { + defm Z256: avx512_shift_rmi, + avx512_shift_rmbi, EVEX_V256; + defm Z128: avx512_shift_rmi, + avx512_shift_rmbi, EVEX_V128; + } +} + +multiclass avx512_shift_rmi_w opcw, Format ImmFormR, Format ImmFormM, + string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + let Predicates = [HasBWI] in + defm WZ: avx512_shift_rmi, EVEX_V512, VEX_WIG; + let Predicates = [HasVLX, HasBWI] in { + defm WZ256: avx512_shift_rmi, EVEX_V256, VEX_WIG; + defm WZ128: avx512_shift_rmi, EVEX_V128, VEX_WIG; + } +} + +multiclass avx512_shift_rmi_dq opcd, bits<8> opcq, + Format ImmFormR, Format ImmFormM, + string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, + bit NotEVEX2VEXConvertibleQ = 0> { + defm D: avx512_shift_rmi_sizes, EVEX_CD8<32, CD8VF>; + let notEVEX2VEXConvertible = NotEVEX2VEXConvertibleQ in + defm Q: avx512_shift_rmi_sizes, EVEX_CD8<64, CD8VF>, VEX_W; +} + +defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli, + SchedWriteVecShiftImm>, + avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli, + SchedWriteVecShiftImm>, AVX512BIi8Base, EVEX_4V; + +defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli, + SchedWriteVecShiftImm>, + avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli, + SchedWriteVecShiftImm>, AVX512BIi8Base, EVEX_4V; + +defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai, + SchedWriteVecShiftImm, 1>, + avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai, + SchedWriteVecShiftImm>, AVX512BIi8Base, EVEX_4V; + +defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", X86vrotri, + SchedWriteVecShiftImm>, AVX512BIi8Base, EVEX_4V; +defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", X86vrotli, + SchedWriteVecShiftImm>, AVX512BIi8Base, EVEX_4V; + +defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl, + SchedWriteVecShift>; +defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra, + SchedWriteVecShift, 1>; +defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl, + SchedWriteVecShift>; + +// Use 512bit VPSRA/VPSRAI version to implement v2i64/v4i64 in case NoVLX. +let Predicates = [HasAVX512, NoVLX] in { + def : Pat<(v4i64 (X86vsra (v4i64 VR256X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPSRAQZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + VR128X:$src2)), sub_ymm)>; + + def : Pat<(v2i64 (X86vsra (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPSRAQZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + VR128X:$src2)), sub_xmm)>; + + def : Pat<(v4i64 (X86vsrai (v4i64 VR256X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPSRAQZri + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + imm:$src2)), sub_ymm)>; + + def : Pat<(v2i64 (X86vsrai (v2i64 VR128X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPSRAQZri + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + imm:$src2)), sub_xmm)>; +} + +//===-------------------------------------------------------------------===// +// Variable Bit Shifts +//===-------------------------------------------------------------------===// + +multiclass avx512_var_shift opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rr : AVX512_maskable, + AVX5128IBase, EVEX_4V, Sched<[sched]>; + defm rm : AVX512_maskable, + AVX5128IBase, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_var_shift_mb opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm rmb : AVX512_maskable, + AVX5128IBase, EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_var_shift_sizes opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo _> { + let Predicates = [HasAVX512] in + defm Z : avx512_var_shift, + avx512_var_shift_mb, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in { + defm Z256 : avx512_var_shift, + avx512_var_shift_mb, EVEX_V256; + defm Z128 : avx512_var_shift, + avx512_var_shift_mb, EVEX_V128; + } +} + +multiclass avx512_var_shift_types opc, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched> { + defm D : avx512_var_shift_sizes; + defm Q : avx512_var_shift_sizes, VEX_W; +} + +// Use 512bit version to implement 128/256 bit in case NoVLX. +multiclass avx512_var_shift_lowering p> { + let Predicates = p in { + def : Pat<(_.info256.VT (OpNode (_.info256.VT _.info256.RC:$src1), + (_.info256.VT _.info256.RC:$src2))), + (EXTRACT_SUBREG + (!cast(OpcodeStr#"Zrr") + (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src1, sub_ymm), + (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)), + sub_ymm)>; + + def : Pat<(_.info128.VT (OpNode (_.info128.VT _.info128.RC:$src1), + (_.info128.VT _.info128.RC:$src2))), + (EXTRACT_SUBREG + (!cast(OpcodeStr#"Zrr") + (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src1, sub_xmm), + (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)), + sub_xmm)>; + } +} +multiclass avx512_var_shift_w opc, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched> { + let Predicates = [HasBWI] in + defm WZ: avx512_var_shift, + EVEX_V512, VEX_W; + let Predicates = [HasVLX, HasBWI] in { + + defm WZ256: avx512_var_shift, + EVEX_V256, VEX_W; + defm WZ128: avx512_var_shift, + EVEX_V128, VEX_W; + } +} + +defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl, SchedWriteVarVecShift>, + avx512_var_shift_w<0x12, "vpsllvw", shl, SchedWriteVarVecShift>; + +defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra, SchedWriteVarVecShift>, + avx512_var_shift_w<0x11, "vpsravw", sra, SchedWriteVarVecShift>; + +defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl, SchedWriteVarVecShift>, + avx512_var_shift_w<0x10, "vpsrlvw", srl, SchedWriteVarVecShift>; + +defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr, SchedWriteVarVecShift>; +defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl, SchedWriteVarVecShift>; + +defm : avx512_var_shift_lowering; +defm : avx512_var_shift_lowering; +defm : avx512_var_shift_lowering; +defm : avx512_var_shift_lowering; + +// Special handing for handling VPSRAV intrinsics. +multiclass avx512_var_shift_int_lowering p> { + let Predicates = p in { + def : Pat<(_.VT (X86vsrav _.RC:$src1, _.RC:$src2)), + (!cast(InstrStr#_.ZSuffix#rr) _.RC:$src1, + _.RC:$src2)>; + def : Pat<(_.VT (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2)))), + (!cast(InstrStr#_.ZSuffix##rm) + _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86vsrav _.RC:$src1, _.RC:$src2), _.RC:$src0)), + (!cast(InstrStr#_.ZSuffix#rrk) _.RC:$src0, + _.KRC:$mask, _.RC:$src1, _.RC:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2))), + _.RC:$src0)), + (!cast(InstrStr#_.ZSuffix##rmk) _.RC:$src0, + _.KRC:$mask, _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86vsrav _.RC:$src1, _.RC:$src2), _.ImmAllZerosV)), + (!cast(InstrStr#_.ZSuffix#rrkz) _.KRC:$mask, + _.RC:$src1, _.RC:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2))), + _.ImmAllZerosV)), + (!cast(InstrStr#_.ZSuffix##rmkz) _.KRC:$mask, + _.RC:$src1, addr:$src2)>; + } +} + +multiclass avx512_var_shift_int_lowering_mb p> : + avx512_var_shift_int_lowering { + let Predicates = p in { + def : Pat<(_.VT (X86vsrav _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src2)))), + (!cast(InstrStr#_.ZSuffix##rmb) + _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86vsrav _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src2))), + _.RC:$src0)), + (!cast(InstrStr#_.ZSuffix##rmbk) _.RC:$src0, + _.KRC:$mask, _.RC:$src1, addr:$src2)>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (X86vsrav _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src2))), + _.ImmAllZerosV)), + (!cast(InstrStr#_.ZSuffix##rmbkz) _.KRC:$mask, + _.RC:$src1, addr:$src2)>; + } +} + +defm : avx512_var_shift_int_lowering<"VPSRAVW", v8i16x_info, [HasVLX, HasBWI]>; +defm : avx512_var_shift_int_lowering<"VPSRAVW", v16i16x_info, [HasVLX, HasBWI]>; +defm : avx512_var_shift_int_lowering<"VPSRAVW", v32i16_info, [HasBWI]>; +defm : avx512_var_shift_int_lowering_mb<"VPSRAVD", v4i32x_info, [HasVLX]>; +defm : avx512_var_shift_int_lowering_mb<"VPSRAVD", v8i32x_info, [HasVLX]>; +defm : avx512_var_shift_int_lowering_mb<"VPSRAVD", v16i32_info, [HasAVX512]>; +defm : avx512_var_shift_int_lowering_mb<"VPSRAVQ", v2i64x_info, [HasVLX]>; +defm : avx512_var_shift_int_lowering_mb<"VPSRAVQ", v4i64x_info, [HasVLX]>; +defm : avx512_var_shift_int_lowering_mb<"VPSRAVQ", v8i64_info, [HasAVX512]>; + +// Use 512bit VPROL/VPROLI version to implement v2i64/v4i64 + v4i32/v8i32 in case NoVLX. +let Predicates = [HasAVX512, NoVLX] in { + def : Pat<(v2i64 (rotl (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPROLVQZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src2, sub_xmm)))), + sub_xmm)>; + def : Pat<(v4i64 (rotl (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPROLVQZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm)))), + sub_ymm)>; + + def : Pat<(v4i32 (rotl (v4i32 VR128X:$src1), (v4i32 VR128X:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPROLVDZrr + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src2, sub_xmm)))), + sub_xmm)>; + def : Pat<(v8i32 (rotl (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPROLVDZrr + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm)))), + sub_ymm)>; + + def : Pat<(v2i64 (X86vrotli (v2i64 VR128X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPROLQZri + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + imm:$src2)), sub_xmm)>; + def : Pat<(v4i64 (X86vrotli (v4i64 VR256X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPROLQZri + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + imm:$src2)), sub_ymm)>; + + def : Pat<(v4i32 (X86vrotli (v4i32 VR128X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPROLDZri + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + imm:$src2)), sub_xmm)>; + def : Pat<(v8i32 (X86vrotli (v8i32 VR256X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPROLDZri + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + imm:$src2)), sub_ymm)>; +} + +// Use 512bit VPROR/VPRORI version to implement v2i64/v4i64 + v4i32/v8i32 in case NoVLX. +let Predicates = [HasAVX512, NoVLX] in { + def : Pat<(v2i64 (rotr (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPRORVQZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src2, sub_xmm)))), + sub_xmm)>; + def : Pat<(v4i64 (rotr (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPRORVQZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm)))), + sub_ymm)>; + + def : Pat<(v4i32 (rotr (v4i32 VR128X:$src1), (v4i32 VR128X:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPRORVDZrr + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src2, sub_xmm)))), + sub_xmm)>; + def : Pat<(v8i32 (rotr (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPRORVDZrr + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src2, sub_ymm)))), + sub_ymm)>; + + def : Pat<(v2i64 (X86vrotri (v2i64 VR128X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPRORQZri + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + imm:$src2)), sub_xmm)>; + def : Pat<(v4i64 (X86vrotri (v4i64 VR256X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v8i64 + (VPRORQZri + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + imm:$src2)), sub_ymm)>; + + def : Pat<(v4i32 (X86vrotri (v4i32 VR128X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPRORDZri + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)), + imm:$src2)), sub_xmm)>; + def : Pat<(v8i32 (X86vrotri (v8i32 VR256X:$src1), (i8 imm:$src2))), + (EXTRACT_SUBREG (v16i32 + (VPRORDZri + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)), + imm:$src2)), sub_ymm)>; +} + +//===-------------------------------------------------------------------===// +// 1-src variable permutation VPERMW/D/Q +//===-------------------------------------------------------------------===// + +multiclass avx512_vperm_dq_sizes opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, AVX512VLVectorVTInfo _> { + let Predicates = [HasAVX512] in + defm Z : avx512_var_shift, + avx512_var_shift_mb, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in + defm Z256 : avx512_var_shift, + avx512_var_shift_mb, EVEX_V256; +} + +multiclass avx512_vpermi_dq_sizes opc, Format ImmFormR, Format ImmFormM, + string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, AVX512VLVectorVTInfo VTInfo> { + let Predicates = [HasAVX512] in + defm Z: avx512_shift_rmi, + avx512_shift_rmbi, EVEX_V512; + let Predicates = [HasAVX512, HasVLX] in + defm Z256: avx512_shift_rmi, + avx512_shift_rmbi, EVEX_V256; +} + +multiclass avx512_vperm_bw opc, string OpcodeStr, + Predicate prd, SDNode OpNode, + X86FoldableSchedWrite sched, AVX512VLVectorVTInfo _> { + let Predicates = [prd] in + defm Z: avx512_var_shift, + EVEX_V512 ; + let Predicates = [HasVLX, prd] in { + defm Z256: avx512_var_shift, + EVEX_V256 ; + defm Z128: avx512_var_shift, + EVEX_V128 ; + } +} + +defm VPERMW : avx512_vperm_bw<0x8D, "vpermw", HasBWI, X86VPermv, + WriteVarShuffle256, avx512vl_i16_info>, VEX_W; +defm VPERMB : avx512_vperm_bw<0x8D, "vpermb", HasVBMI, X86VPermv, + WriteVarShuffle256, avx512vl_i8_info>; + +defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv, + WriteVarShuffle256, avx512vl_i32_info>; +defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv, + WriteVarShuffle256, avx512vl_i64_info>, VEX_W; +defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv, + WriteFVarShuffle256, avx512vl_f32_info>; +defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv, + WriteFVarShuffle256, avx512vl_f64_info>, VEX_W; + +defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq", + X86VPermi, WriteShuffle256, avx512vl_i64_info>, + EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W; +defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd", + X86VPermi, WriteFShuffle256, avx512vl_f64_info>, + EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W; + +//===----------------------------------------------------------------------===// +// AVX-512 - VPERMIL +//===----------------------------------------------------------------------===// + +multiclass avx512_permil_vec OpcVar, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + X86VectorVTInfo Ctrl> { + defm rr: AVX512_maskable, + T8PD, EVEX_4V, Sched<[sched]>; + defm rm: AVX512_maskable, + T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + defm rmb: AVX512_maskable, + T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_permil_vec_common OpcVar, + X86SchedWriteWidths sched, + AVX512VLVectorVTInfo _, + AVX512VLVectorVTInfo Ctrl> { + let Predicates = [HasAVX512] in { + defm Z : avx512_permil_vec, EVEX_V512; + } + let Predicates = [HasAVX512, HasVLX] in { + defm Z128 : avx512_permil_vec, EVEX_V128; + defm Z256 : avx512_permil_vec, EVEX_V256; + } +} + +multiclass avx512_permil OpcImm, bits<8> OpcVar, + AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{ + defm NAME: avx512_permil_vec_common; + defm NAME: avx512_shift_rmi_sizes, + EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>; +} + +let ExeDomain = SSEPackedSingle in +defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info, + avx512vl_i32_info>; +let ExeDomain = SSEPackedDouble in +defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info, + avx512vl_i64_info>, VEX_W1X; + +//===----------------------------------------------------------------------===// +// AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW +//===----------------------------------------------------------------------===// + +defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd", + X86PShufd, SchedWriteShuffle, avx512vl_i32_info>, + EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>; +defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw", + X86PShufhw, SchedWriteShuffle>, + EVEX, AVX512XSIi8Base; +defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw", + X86PShuflw, SchedWriteShuffle>, + EVEX, AVX512XDIi8Base; + +//===----------------------------------------------------------------------===// +// AVX-512 - VPSHUFB +//===----------------------------------------------------------------------===// + +multiclass avx512_pshufb_sizes opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + let Predicates = [HasBWI] in + defm Z: avx512_var_shift, + EVEX_V512; + + let Predicates = [HasVLX, HasBWI] in { + defm Z256: avx512_var_shift, + EVEX_V256; + defm Z128: avx512_var_shift, + EVEX_V128; + } +} + +defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb, + SchedWriteVarShuffle>, VEX_WIG; + +//===----------------------------------------------------------------------===// +// Move Low to High and High to Low packed FP Instructions +//===----------------------------------------------------------------------===// + +def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst), + (ins VR128X:$src1, VR128X:$src2), + "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))]>, + Sched<[SchedWriteFShuffle.XMM]>, EVEX_4V; +let isCommutable = 1 in +def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst), + (ins VR128X:$src1, VR128X:$src2), + "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))]>, + Sched<[SchedWriteFShuffle.XMM]>, EVEX_4V, NotMemoryFoldable; + +//===----------------------------------------------------------------------===// +// VMOVHPS/PD VMOVLPS Instructions +// All patterns was taken from SSS implementation. +//===----------------------------------------------------------------------===// + +multiclass avx512_mov_hilo_packed opc, string OpcodeStr, + SDPatternOperator OpNode, + X86VectorVTInfo _> { + let hasSideEffects = 0, mayLoad = 1, ExeDomain = _.ExeDomain in + def rm : AVX512, + Sched<[SchedWriteFShuffle.XMM.Folded, ReadAfterLd]>, EVEX_4V; +} + +// No patterns for MOVLPS/MOVHPS as the Movlhps node should only be created in +// SSE1. And MOVLPS pattern is even more complex. +defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", null_frag, + v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS; +defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Unpckl, + v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W; +defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", null_frag, + v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS; +defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movsd, + v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W; + +let Predicates = [HasAVX512] in { + // VMOVHPD patterns + def : Pat<(v2f64 (X86Unpckl VR128X:$src1, + (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))), + (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>; +} + +let SchedRW = [WriteFStore] in { +def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs), + (ins f64mem:$dst, VR128X:$src), + "vmovhps\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt + (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)), + (bc_v2f64 (v4f32 VR128X:$src))), + (iPTR 0))), addr:$dst)]>, + EVEX, EVEX_CD8<32, CD8VT2>; +def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs), + (ins f64mem:$dst, VR128X:$src), + "vmovhpd\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt + (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)), + (iPTR 0))), addr:$dst)]>, + EVEX, EVEX_CD8<64, CD8VT1>, VEX_W; +def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs), + (ins f64mem:$dst, VR128X:$src), + "vmovlps\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt (bc_v2f64 (v4f32 VR128X:$src)), + (iPTR 0))), addr:$dst)]>, + EVEX, EVEX_CD8<32, CD8VT2>; +def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs), + (ins f64mem:$dst, VR128X:$src), + "vmovlpd\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt (v2f64 VR128X:$src), + (iPTR 0))), addr:$dst)]>, + EVEX, EVEX_CD8<64, CD8VT1>, VEX_W; +} // SchedRW + +let Predicates = [HasAVX512] in { + // VMOVHPD patterns + def : Pat<(store (f64 (extractelt + (v2f64 (X86VPermilpi VR128X:$src, (i8 1))), + (iPTR 0))), addr:$dst), + (VMOVHPDZ128mr addr:$dst, VR128X:$src)>; +} +//===----------------------------------------------------------------------===// +// FMA - Fused Multiply Operations +// + +multiclass avx512_fma3p_213_rm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Suff> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in { + defm r: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched]>; + + defm m: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched.Folded, ReadAfterLd]>; + + defm mb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fma3_213_round opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Suff> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in + defm rb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +multiclass avx512_fma3p_213_common opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo _, string Suff> { + let Predicates = [HasAVX512] in { + defm Z : avx512_fma3p_213_rm, + avx512_fma3_213_round, + EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>; + } + let Predicates = [HasVLX, HasAVX512] in { + defm Z256 : avx512_fma3p_213_rm, + EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>; + defm Z128 : avx512_fma3p_213_rm, + EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>; + } +} + +multiclass avx512_fma3p_213_f opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd> { + defm PS : avx512_fma3p_213_common; + defm PD : avx512_fma3p_213_common, + VEX_W; +} + +defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>; +defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>; +defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>; +defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>; +defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>; +defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>; + + +multiclass avx512_fma3p_231_rm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Suff> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in { + defm r: AVX512_maskable_3src, AVX512FMA3Base, Sched<[sched]>; + + defm m: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched.Folded, ReadAfterLd]>; + + defm mb: AVX512_maskable_3src, AVX512FMA3Base, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fma3_231_round opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Suff> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in + defm rb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +multiclass avx512_fma3p_231_common opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo _, string Suff> { + let Predicates = [HasAVX512] in { + defm Z : avx512_fma3p_231_rm, + avx512_fma3_231_round, + EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>; + } + let Predicates = [HasVLX, HasAVX512] in { + defm Z256 : avx512_fma3p_231_rm, + EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>; + defm Z128 : avx512_fma3p_231_rm, + EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>; + } +} + +multiclass avx512_fma3p_231_f opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd > { + defm PS : avx512_fma3p_231_common; + defm PD : avx512_fma3p_231_common, + VEX_W; +} + +defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>; +defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>; +defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>; +defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>; +defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>; +defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>; + +multiclass avx512_fma3p_132_rm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Suff> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in { + defm r: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched]>; + + // Pattern is 312 order so that the load is in a different place from the + // 213 and 231 patterns this helps tablegen's duplicate pattern detection. + defm m: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched.Folded, ReadAfterLd]>; + + // Pattern is 312 order so that the load is in a different place from the + // 213 and 231 patterns this helps tablegen's duplicate pattern detection. + defm mb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fma3_132_round opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Suff> { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in + defm rb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +multiclass avx512_fma3p_132_common opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo _, string Suff> { + let Predicates = [HasAVX512] in { + defm Z : avx512_fma3p_132_rm, + avx512_fma3_132_round, + EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>; + } + let Predicates = [HasVLX, HasAVX512] in { + defm Z256 : avx512_fma3p_132_rm, + EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>; + defm Z128 : avx512_fma3p_132_rm, + EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>; + } +} + +multiclass avx512_fma3p_132_f opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd > { + defm PS : avx512_fma3p_132_common; + defm PD : avx512_fma3p_132_common, + VEX_W; +} + +defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>; +defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>; +defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>; +defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>; +defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>; +defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>; + +// Scalar FMA +multiclass avx512_fma3s_common opc, string OpcodeStr, X86VectorVTInfo _, + dag RHS_r, dag RHS_m, dag RHS_b, bit MaskOnlyReg> { +let Constraints = "$src1 = $dst", hasSideEffects = 0 in { + defm r_Int: AVX512_maskable_3src_scalar, + AVX512FMA3Base, Sched<[SchedWriteFMA.Scl]>; + + let mayLoad = 1 in + defm m_Int: AVX512_maskable_3src_scalar, + AVX512FMA3Base, Sched<[SchedWriteFMA.Scl.Folded, ReadAfterLd]>; + + defm rb_Int: AVX512_maskable_3src_scalar, + AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[SchedWriteFMA.Scl]>; + + let isCodeGenOnly = 1, isCommutable = 1 in { + def r : AVX512FMA3S, Sched<[SchedWriteFMA.Scl]>; + def m : AVX512FMA3S, Sched<[SchedWriteFMA.Scl.Folded, ReadAfterLd]>; + + def rb : AVX512FMA3S, EVEX_B, EVEX_RC, + Sched<[SchedWriteFMA.Scl]>; + }// isCodeGenOnly = 1 +}// Constraints = "$src1 = $dst" +} + +multiclass avx512_fma3s_all opc213, bits<8> opc231, bits<8> opc132, + string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, + X86VectorVTInfo _, string SUFF> { + let ExeDomain = _.ExeDomain in { + defm NAME#213#SUFF#Z: avx512_fma3s_common; + + defm NAME#231#SUFF#Z: avx512_fma3s_common; + + // One pattern is 312 order so that the load is in a different place from the + // 213 and 231 patterns this helps tablegen's duplicate pattern detection. + defm NAME#132#SUFF#Z: avx512_fma3s_common; + } +} + +multiclass avx512_fma3s opc213, bits<8> opc231, bits<8> opc132, + string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd> { + let Predicates = [HasAVX512] in { + defm NAME : avx512_fma3s_all, + EVEX_CD8<32, CD8VT1>, VEX_LIG; + defm NAME : avx512_fma3s_all, + EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W; + } +} + +defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>; +defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>; +defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>; +defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>; + +multiclass avx512_scalar_fma_patterns { + let Predicates = [HasAVX512] in { + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (Op _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src3))))), + (!cast(Prefix#"213"#Suffix#"Zr_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)))>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (Op _.FRC:$src2, _.FRC:$src3, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"Zr_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)))>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (Op _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (_.ScalarLdFrag addr:$src3)))))), + (!cast(Prefix#"213"#Suffix#"Zm_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (Op (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (_.ScalarLdFrag addr:$src3), _.FRC:$src2))))), + (!cast(Prefix#"132"#Suffix#"Zm_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (Op _.FRC:$src2, (_.ScalarLdFrag addr:$src3), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"Zm_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src3), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"213"#Suffix#"Zr_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)))>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (_.ScalarLdFrag addr:$src3)), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"213"#Suffix#"Zm_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (_.ScalarLdFrag addr:$src3), _.FRC:$src2), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"132"#Suffix#"Zm_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, _.FRC:$src3, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"Zr_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)))>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, (_.ScalarLdFrag addr:$src3), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"Zm_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src3), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"213"#Suffix#"Zr_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)))>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, _.FRC:$src3, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"231"#Suffix#"Zr_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)))>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (_.ScalarLdFrag addr:$src3)), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"213"#Suffix#"Zm_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src2, (_.ScalarLdFrag addr:$src3)), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"132"#Suffix#"Zm_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), addr:$src3)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (Op _.FRC:$src2, (_.ScalarLdFrag addr:$src3), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"231"#Suffix#"Zm_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), addr:$src3)>; + + // Patterns with rounding mode. + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (RndOp _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src3, (i32 imm:$rc)))))), + (!cast(Prefix#"213"#Suffix#"Zrb_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), imm:$rc)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (RndOp _.FRC:$src2, _.FRC:$src3, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (i32 imm:$rc)))))), + (!cast(Prefix#"231"#Suffix#"Zrb_Int") + VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), imm:$rc)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (RndOp _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src3, (i32 imm:$rc)), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"213"#Suffix#"Zrb_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), imm:$rc)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (RndOp _.FRC:$src2, _.FRC:$src3, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (i32 imm:$rc)), + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"Zrb_Intk") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), imm:$rc)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (RndOp _.FRC:$src2, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src3, (i32 imm:$rc)), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"213"#Suffix#"Zrb_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), imm:$rc)>; + + def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector + (X86selects VK1WM:$mask, + (RndOp _.FRC:$src2, _.FRC:$src3, + (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))), + (i32 imm:$rc)), + (_.EltVT ZeroFP)))))), + (!cast(Prefix#"231"#Suffix#"Zrb_Intkz") + VR128X:$src1, VK1WM:$mask, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), + (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), imm:$rc)>; + } +} + +defm : avx512_scalar_fma_patterns; +defm : avx512_scalar_fma_patterns; +defm : avx512_scalar_fma_patterns; +defm : avx512_scalar_fma_patterns; + +defm : avx512_scalar_fma_patterns; +defm : avx512_scalar_fma_patterns; +defm : avx512_scalar_fma_patterns; +defm : avx512_scalar_fma_patterns; + +//===----------------------------------------------------------------------===// +// AVX-512 Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit IFMA +//===----------------------------------------------------------------------===// +let Constraints = "$src1 = $dst" in { +multiclass avx512_pmadd52_rm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + // NOTE: The SDNode have the multiply operands first with the add last. + // This enables commuted load patterns to be autogenerated by tablegen. + let ExeDomain = _.ExeDomain in { + defm r: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched]>; + + defm m: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched.Folded, ReadAfterLd]>; + + defm mb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } +} +} // Constraints = "$src1 = $dst" + +multiclass avx512_pmadd52_common opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo _> { + let Predicates = [HasIFMA] in { + defm Z : avx512_pmadd52_rm, + EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>; + } + let Predicates = [HasVLX, HasIFMA] in { + defm Z256 : avx512_pmadd52_rm, + EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>; + defm Z128 : avx512_pmadd52_rm, + EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>; + } +} + +defm VPMADD52LUQ : avx512_pmadd52_common<0xb4, "vpmadd52luq", x86vpmadd52l, + SchedWriteVecIMul, avx512vl_i64_info>, + VEX_W; +defm VPMADD52HUQ : avx512_pmadd52_common<0xb5, "vpmadd52huq", x86vpmadd52h, + SchedWriteVecIMul, avx512vl_i64_info>, + VEX_W; + +//===----------------------------------------------------------------------===// +// AVX-512 Scalar convert from sign integer to float/double +//===----------------------------------------------------------------------===// + +multiclass avx512_vcvtsi opc, SDNode OpNode, X86FoldableSchedWrite sched, + RegisterClass SrcRC, X86VectorVTInfo DstVT, + X86MemOperand x86memop, PatFrag ld_frag, string asm> { + let hasSideEffects = 0 in { + def rr : SI, + EVEX_4V, Sched<[sched]>; + let mayLoad = 1 in + def rm : SI, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + } // hasSideEffects = 0 + let isCodeGenOnly = 1 in { + def rr_Int : SI, + EVEX_4V, Sched<[sched]>; + + def rm_Int : SI, + EVEX_4V, Sched<[sched.Folded, ReadAfterLd]>; + }//isCodeGenOnly = 1 +} + +multiclass avx512_vcvtsi_round opc, SDNode OpNode, + X86FoldableSchedWrite sched, RegisterClass SrcRC, + X86VectorVTInfo DstVT, string asm> { + def rrb_Int : SI, + EVEX_4V, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +multiclass avx512_vcvtsi_common opc, SDNode OpNode, + X86FoldableSchedWrite sched, + RegisterClass SrcRC, X86VectorVTInfo DstVT, + X86MemOperand x86memop, PatFrag ld_frag, string asm> { + defm NAME : avx512_vcvtsi_round, + avx512_vcvtsi, VEX_LIG; +} + +let Predicates = [HasAVX512] in { +defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, WriteCvtI2SS, GR32, + v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">, + XS, EVEX_CD8<32, CD8VT1>; +defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, WriteCvtI2SS, GR64, + v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">, + XS, VEX_W, EVEX_CD8<64, CD8VT1>; +defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, WriteCvtI2SD, GR32, + v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">, + XD, EVEX_CD8<32, CD8VT1>; +defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, WriteCvtI2SD, GR64, + v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">, + XD, VEX_W, EVEX_CD8<64, CD8VT1>; + +def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}", + (VCVTSI2SSZrm FR64X:$dst, FR64X:$src1, i32mem:$src), 0, "att">; +def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}", + (VCVTSI2SDZrm FR64X:$dst, FR64X:$src1, i32mem:$src), 0, "att">; + +def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))), + (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; +def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))), + (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; +def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))), + (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; +def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))), + (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; + +def : Pat<(f32 (sint_to_fp GR32:$src)), + (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>; +def : Pat<(f32 (sint_to_fp GR64:$src)), + (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>; +def : Pat<(f64 (sint_to_fp GR32:$src)), + (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>; +def : Pat<(f64 (sint_to_fp GR64:$src)), + (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>; + +defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, WriteCvtI2SS, GR32, + v4f32x_info, i32mem, loadi32, + "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>; +defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, WriteCvtI2SS, GR64, + v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">, + XS, VEX_W, EVEX_CD8<64, CD8VT1>; +defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, WriteCvtI2SD, GR32, v2f64x_info, + i32mem, loadi32, "cvtusi2sd{l}">, + XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; +defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, WriteCvtI2SD, GR64, + v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">, + XD, VEX_W, EVEX_CD8<64, CD8VT1>; + +def : InstAlias<"vcvtusi2ss\t{$src, $src1, $dst|$dst, $src1, $src}", + (VCVTUSI2SSZrm FR64X:$dst, FR64X:$src1, i32mem:$src), 0, "att">; +def : InstAlias<"vcvtusi2sd\t{$src, $src1, $dst|$dst, $src1, $src}", + (VCVTUSI2SDZrm FR64X:$dst, FR64X:$src1, i32mem:$src), 0, "att">; + +def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))), + (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; +def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))), + (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; +def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))), + (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; +def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))), + (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; + +def : Pat<(f32 (uint_to_fp GR32:$src)), + (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>; +def : Pat<(f32 (uint_to_fp GR64:$src)), + (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>; +def : Pat<(f64 (uint_to_fp GR32:$src)), + (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>; +def : Pat<(f64 (uint_to_fp GR64:$src)), + (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 Scalar convert from float/double to integer +//===----------------------------------------------------------------------===// + +multiclass avx512_cvt_s_int_round opc, X86VectorVTInfo SrcVT, + X86VectorVTInfo DstVT, SDNode OpNode, + X86FoldableSchedWrite sched, string asm, + string aliasStr, + bit CodeGenOnly = 1> { + let Predicates = [HasAVX512] in { + def rr_Int : SI, + EVEX, VEX_LIG, Sched<[sched]>; + def rrb_Int : SI, + EVEX, VEX_LIG, EVEX_B, EVEX_RC, + Sched<[sched]>; + let isCodeGenOnly = CodeGenOnly, ForceDisassemble = CodeGenOnly in + def rm_Int : SI, + EVEX, VEX_LIG, Sched<[sched.Folded, ReadAfterLd]>; + + def : InstAlias<"v" # asm # aliasStr # "\t{$src, $dst|$dst, $src}", + (!cast(NAME # "rr_Int") DstVT.RC:$dst, SrcVT.RC:$src), 0, "att">; + def : InstAlias<"v" # asm # aliasStr # "\t{$rc, $src, $dst|$dst, $src, $rc}", + (!cast(NAME # "rrb_Int") DstVT.RC:$dst, SrcVT.RC:$src, AVX512RC:$rc), 0, "att">; + } // Predicates = [HasAVX512] +} + +multiclass avx512_cvt_s_int_round_aliases opc, X86VectorVTInfo SrcVT, + X86VectorVTInfo DstVT, SDNode OpNode, + X86FoldableSchedWrite sched, string asm, + string aliasStr> : + avx512_cvt_s_int_round { + let Predicates = [HasAVX512] in { + def : InstAlias<"v" # asm # aliasStr # "\t{$src, $dst|$dst, $src}", + (!cast(NAME # "rm_Int") DstVT.RC:$dst, + SrcVT.IntScalarMemOp:$src), 0, "att">; + } // Predicates = [HasAVX512] +} + +// Convert float/double to signed/unsigned int 32/64 +defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, f32x_info, i32x_info, + X86cvts2si, WriteCvtSS2I, "cvtss2si", "{l}">, + XS, EVEX_CD8<32, CD8VT1>; +defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info, + X86cvts2si, WriteCvtSS2I, "cvtss2si", "{q}">, + XS, VEX_W, EVEX_CD8<32, CD8VT1>; +defm VCVTSS2USIZ: avx512_cvt_s_int_round_aliases<0x79, f32x_info, i32x_info, + X86cvts2usi, WriteCvtSS2I, "cvtss2usi", "{l}">, + XS, EVEX_CD8<32, CD8VT1>; +defm VCVTSS2USI64Z: avx512_cvt_s_int_round_aliases<0x79, f32x_info, i64x_info, + X86cvts2usi, WriteCvtSS2I, "cvtss2usi", "{q}">, + XS, VEX_W, EVEX_CD8<32, CD8VT1>; +defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info, + X86cvts2si, WriteCvtSD2I, "cvtsd2si", "{l}">, + XD, EVEX_CD8<64, CD8VT1>; +defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, f64x_info, i64x_info, + X86cvts2si, WriteCvtSD2I, "cvtsd2si", "{q}">, + XD, VEX_W, EVEX_CD8<64, CD8VT1>; +defm VCVTSD2USIZ: avx512_cvt_s_int_round_aliases<0x79, f64x_info, i32x_info, + X86cvts2usi, WriteCvtSD2I, "cvtsd2usi", "{l}">, + XD, EVEX_CD8<64, CD8VT1>; +defm VCVTSD2USI64Z: avx512_cvt_s_int_round_aliases<0x79, f64x_info, i64x_info, + X86cvts2usi, WriteCvtSD2I, "cvtsd2usi", "{q}">, + XD, VEX_W, EVEX_CD8<64, CD8VT1>; + +// The SSE version of these instructions are disabled for AVX512. +// Therefore, the SSE intrinsics are mapped to the AVX512 instructions. +let Predicates = [HasAVX512] in { + def : Pat<(i32 (int_x86_sse_cvtss2si (v4f32 VR128X:$src))), + (VCVTSS2SIZrr_Int VR128X:$src)>; + def : Pat<(i32 (int_x86_sse_cvtss2si sse_load_f32:$src)), + (VCVTSS2SIZrm_Int sse_load_f32:$src)>; + def : Pat<(i64 (int_x86_sse_cvtss2si64 (v4f32 VR128X:$src))), + (VCVTSS2SI64Zrr_Int VR128X:$src)>; + def : Pat<(i64 (int_x86_sse_cvtss2si64 sse_load_f32:$src)), + (VCVTSS2SI64Zrm_Int sse_load_f32:$src)>; + def : Pat<(i32 (int_x86_sse2_cvtsd2si (v2f64 VR128X:$src))), + (VCVTSD2SIZrr_Int VR128X:$src)>; + def : Pat<(i32 (int_x86_sse2_cvtsd2si sse_load_f64:$src)), + (VCVTSD2SIZrm_Int sse_load_f64:$src)>; + def : Pat<(i64 (int_x86_sse2_cvtsd2si64 (v2f64 VR128X:$src))), + (VCVTSD2SI64Zrr_Int VR128X:$src)>; + def : Pat<(i64 (int_x86_sse2_cvtsd2si64 sse_load_f64:$src)), + (VCVTSD2SI64Zrm_Int sse_load_f64:$src)>; +} // HasAVX512 + +// Patterns used for matching vcvtsi2s{s,d} intrinsic sequences from clang +// which produce unnecessary vmovs{s,d} instructions +let Predicates = [HasAVX512] in { +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp GR64:$src)))))), + (VCVTSI642SSZrr_Int VR128X:$dst, GR64:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi64 addr:$src))))))), + (VCVTSI642SSZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp GR32:$src)))))), + (VCVTSI2SSZrr_Int VR128X:$dst, GR32:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi32 addr:$src))))))), + (VCVTSI2SSZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp GR64:$src)))))), + (VCVTSI642SDZrr_Int VR128X:$dst, GR64:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi64 addr:$src))))))), + (VCVTSI642SDZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp GR32:$src)))))), + (VCVTSI2SDZrr_Int VR128X:$dst, GR32:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi32 addr:$src))))))), + (VCVTSI2SDZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (uint_to_fp GR64:$src)))))), + (VCVTUSI642SSZrr_Int VR128X:$dst, GR64:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (uint_to_fp (loadi64 addr:$src))))))), + (VCVTUSI642SSZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (uint_to_fp GR32:$src)))))), + (VCVTUSI2SSZrr_Int VR128X:$dst, GR32:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (uint_to_fp (loadi32 addr:$src))))))), + (VCVTUSI2SSZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (uint_to_fp GR64:$src)))))), + (VCVTUSI642SDZrr_Int VR128X:$dst, GR64:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (uint_to_fp (loadi64 addr:$src))))))), + (VCVTUSI642SDZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (uint_to_fp GR32:$src)))))), + (VCVTUSI2SDZrr_Int VR128X:$dst, GR32:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (uint_to_fp (loadi32 addr:$src))))))), + (VCVTUSI2SDZrm_Int VR128X:$dst, addr:$src)>; +} // Predicates = [HasAVX512] + +// Convert float/double to signed/unsigned int 32/64 with truncation +multiclass avx512_cvt_s_all opc, string asm, X86VectorVTInfo _SrcRC, + X86VectorVTInfo _DstRC, SDNode OpNode, + SDNode OpNodeRnd, X86FoldableSchedWrite sched, + string aliasStr, bit CodeGenOnly = 1>{ +let Predicates = [HasAVX512] in { + let isCodeGenOnly = 1 in { + def rr : AVX512, + EVEX, Sched<[sched]>; + def rm : AVX512, + EVEX, Sched<[sched.Folded, ReadAfterLd]>; + } + + def rr_Int : AVX512, + EVEX, VEX_LIG, Sched<[sched]>; + def rrb_Int : AVX512, + EVEX,VEX_LIG , EVEX_B, Sched<[sched]>; + let isCodeGenOnly = CodeGenOnly, ForceDisassemble = CodeGenOnly in + def rm_Int : AVX512, + EVEX, VEX_LIG, Sched<[sched.Folded, ReadAfterLd]>; + + def : InstAlias(NAME # "rr_Int") _DstRC.RC:$dst, _SrcRC.RC:$src), 0, "att">; + def : InstAlias(NAME # "rrb_Int") _DstRC.RC:$dst, _SrcRC.RC:$src), 0, "att">; +} //HasAVX512 +} + +multiclass avx512_cvt_s_all_unsigned opc, string asm, + X86VectorVTInfo _SrcRC, + X86VectorVTInfo _DstRC, SDNode OpNode, + SDNode OpNodeRnd, X86FoldableSchedWrite sched, + string aliasStr> : + avx512_cvt_s_all { +let Predicates = [HasAVX512] in { + def : InstAlias(NAME # "rm_Int") _DstRC.RC:$dst, + _SrcRC.IntScalarMemOp:$src), 0, "att">; +} +} + +defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "vcvttss2si", f32x_info, i32x_info, + fp_to_sint, X86cvtts2IntRnd, WriteCvtSS2I, "{l}">, + XS, EVEX_CD8<32, CD8VT1>; +defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "vcvttss2si", f32x_info, i64x_info, + fp_to_sint, X86cvtts2IntRnd, WriteCvtSS2I, "{q}">, + VEX_W, XS, EVEX_CD8<32, CD8VT1>; +defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "vcvttsd2si", f64x_info, i32x_info, + fp_to_sint, X86cvtts2IntRnd, WriteCvtSD2I, "{l}">, + XD, EVEX_CD8<64, CD8VT1>; +defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "vcvttsd2si", f64x_info, i64x_info, + fp_to_sint, X86cvtts2IntRnd, WriteCvtSD2I, "{q}">, + VEX_W, XD, EVEX_CD8<64, CD8VT1>; + +defm VCVTTSS2USIZ: avx512_cvt_s_all_unsigned<0x78, "vcvttss2usi", f32x_info, i32x_info, + fp_to_uint, X86cvtts2UIntRnd, WriteCvtSS2I, "{l}">, + XS, EVEX_CD8<32, CD8VT1>; +defm VCVTTSS2USI64Z: avx512_cvt_s_all_unsigned<0x78, "vcvttss2usi", f32x_info, i64x_info, + fp_to_uint, X86cvtts2UIntRnd, WriteCvtSS2I, "{q}">, + XS,VEX_W, EVEX_CD8<32, CD8VT1>; +defm VCVTTSD2USIZ: avx512_cvt_s_all_unsigned<0x78, "vcvttsd2usi", f64x_info, i32x_info, + fp_to_uint, X86cvtts2UIntRnd, WriteCvtSD2I, "{l}">, + XD, EVEX_CD8<64, CD8VT1>; +defm VCVTTSD2USI64Z: avx512_cvt_s_all_unsigned<0x78, "vcvttsd2usi", f64x_info, i64x_info, + fp_to_uint, X86cvtts2UIntRnd, WriteCvtSD2I, "{q}">, + XD, VEX_W, EVEX_CD8<64, CD8VT1>; + +let Predicates = [HasAVX512] in { + def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))), + (VCVTTSS2SIZrr_Int VR128X:$src)>; + def : Pat<(i32 (int_x86_sse_cvttss2si sse_load_f32:$src)), + (VCVTTSS2SIZrm_Int ssmem:$src)>; + def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))), + (VCVTTSS2SI64Zrr_Int VR128X:$src)>; + def : Pat<(i64 (int_x86_sse_cvttss2si64 sse_load_f32:$src)), + (VCVTTSS2SI64Zrm_Int ssmem:$src)>; + def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))), + (VCVTTSD2SIZrr_Int VR128X:$src)>; + def : Pat<(i32 (int_x86_sse2_cvttsd2si sse_load_f64:$src)), + (VCVTTSD2SIZrm_Int sdmem:$src)>; + def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))), + (VCVTTSD2SI64Zrr_Int VR128X:$src)>; + def : Pat<(i64 (int_x86_sse2_cvttsd2si64 sse_load_f64:$src)), + (VCVTTSD2SI64Zrm_Int sdmem:$src)>; +} // HasAVX512 + +//===----------------------------------------------------------------------===// +// AVX-512 Convert form float to double and back +//===----------------------------------------------------------------------===// + +multiclass avx512_cvt_fp_scalar opc, string OpcodeStr, X86VectorVTInfo _, + X86VectorVTInfo _Src, SDNode OpNode, + X86FoldableSchedWrite sched> { + defm rr_Int : AVX512_maskable_scalar, + EVEX_4V, VEX_LIG, Sched<[sched]>; + defm rm_Int : AVX512_maskable_scalar, + EVEX_4V, VEX_LIG, + Sched<[sched.Folded, ReadAfterLd]>; + + let isCodeGenOnly = 1, hasSideEffects = 0 in { + def rr : I, + EVEX_4V, VEX_LIG, Sched<[sched]>; + let mayLoad = 1 in + def rm : I, + EVEX_4V, VEX_LIG, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +// Scalar Conversion with SAE - suppress all exceptions +multiclass avx512_cvt_fp_sae_scalar opc, string OpcodeStr, X86VectorVTInfo _, + X86VectorVTInfo _Src, SDNode OpNodeRnd, + X86FoldableSchedWrite sched> { + defm rrb_Int : AVX512_maskable_scalar, + EVEX_4V, VEX_LIG, EVEX_B, Sched<[sched]>; +} + +// Scalar Conversion with rounding control (RC) +multiclass avx512_cvt_fp_rc_scalar opc, string OpcodeStr, X86VectorVTInfo _, + X86VectorVTInfo _Src, SDNode OpNodeRnd, + X86FoldableSchedWrite sched> { + defm rrb_Int : AVX512_maskable_scalar, + EVEX_4V, VEX_LIG, Sched<[sched]>, + EVEX_B, EVEX_RC; +} +multiclass avx512_cvt_fp_scalar_sd2ss opc, string OpcodeStr, + SDNode OpNodeRnd, X86FoldableSchedWrite sched, + X86VectorVTInfo _src, X86VectorVTInfo _dst> { + let Predicates = [HasAVX512] in { + defm Z : avx512_cvt_fp_scalar, + avx512_cvt_fp_rc_scalar, VEX_W, EVEX_CD8<64, CD8VT1>, XD; + } +} + +multiclass avx512_cvt_fp_scalar_ss2sd opc, string OpcodeStr, SDNode OpNodeRnd, + X86FoldableSchedWrite sched, + X86VectorVTInfo _src, X86VectorVTInfo _dst> { + let Predicates = [HasAVX512] in { + defm Z : avx512_cvt_fp_scalar, + avx512_cvt_fp_sae_scalar, + EVEX_CD8<32, CD8VT1>, XS; + } +} +defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", + X86froundRnd, WriteCvtSD2SS, f64x_info, + f32x_info>; +defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", + X86fpextRnd, WriteCvtSS2SD, f32x_info, + f64x_info>; + +def : Pat<(f64 (fpextend FR32X:$src)), + (VCVTSS2SDZrr (f64 (IMPLICIT_DEF)), FR32X:$src)>, + Requires<[HasAVX512]>; +def : Pat<(f64 (fpextend (loadf32 addr:$src))), + (VCVTSS2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>, + Requires<[HasAVX512, OptForSize]>; + +def : Pat<(f64 (extloadf32 addr:$src)), + (VCVTSS2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>, + Requires<[HasAVX512, OptForSize]>; + +def : Pat<(f64 (extloadf32 addr:$src)), + (VCVTSS2SDZrr (f64 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>, + Requires<[HasAVX512, OptForSpeed]>; + +def : Pat<(f32 (fpround FR64X:$src)), + (VCVTSD2SSZrr (f32 (IMPLICIT_DEF)), FR64X:$src)>, + Requires<[HasAVX512]>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector + (f32 (fpround (f64 (extractelt VR128X:$src, (iPTR 0))))))))), + (VCVTSD2SSZrr_Int VR128X:$dst, VR128X:$src)>, + Requires<[HasAVX512]>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector + (f64 (fpextend (f32 (extractelt VR128X:$src, (iPTR 0))))))))), + (VCVTSS2SDZrr_Int VR128X:$dst, VR128X:$src)>, + Requires<[HasAVX512]>; + +//===----------------------------------------------------------------------===// +// AVX-512 Vector convert from signed/unsigned integer to float/double +// and from float/double to signed/unsigned integer +//===----------------------------------------------------------------------===// + +multiclass avx512_vcvt_fp opc, string OpcodeStr, X86VectorVTInfo _, + X86VectorVTInfo _Src, SDNode OpNode, + X86FoldableSchedWrite sched, + string Broadcast = _.BroadcastStr, + string Alias = "", X86MemOperand MemOp = _Src.MemOp> { + + defm rr : AVX512_maskable, + EVEX, Sched<[sched]>; + + defm rm : AVX512_maskable, + EVEX, Sched<[sched.Folded]>; + + defm rmb : AVX512_maskable, EVEX, EVEX_B, + Sched<[sched.Folded]>; +} +// Conversion with SAE - suppress all exceptions +multiclass avx512_vcvt_fp_sae opc, string OpcodeStr, X86VectorVTInfo _, + X86VectorVTInfo _Src, SDNode OpNodeRnd, + X86FoldableSchedWrite sched> { + defm rrb : AVX512_maskable, + EVEX, EVEX_B, Sched<[sched]>; +} + +// Conversion with rounding control (RC) +multiclass avx512_vcvt_fp_rc opc, string OpcodeStr, X86VectorVTInfo _, + X86VectorVTInfo _Src, SDNode OpNodeRnd, + X86FoldableSchedWrite sched> { + defm rrb : AVX512_maskable, + EVEX, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +// Extend Float to Double +multiclass avx512_cvtps2pd opc, string OpcodeStr, + X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_sae, EVEX_V512; + } + let Predicates = [HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Truncate Double to Float +multiclass avx512_cvtpd2ps opc, string OpcodeStr, X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + + def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; + def : InstAlias(NAME # "Z128rm") VR128X:$dst, f128mem:$src), 0, "intel">; + def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; + def : InstAlias(NAME # "Z256rm") VR128X:$dst, f256mem:$src), 0, "intel">; + } +} + +defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps", SchedWriteCvtPD2PS>, + VEX_W, PD, EVEX_CD8<64, CD8VF>; +defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd", SchedWriteCvtPS2PD>, + PS, EVEX_CD8<32, CD8VH>; + +def : Pat<(v8f64 (extloadv8f32 addr:$src)), + (VCVTPS2PDZrm addr:$src)>; + +let Predicates = [HasVLX] in { + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86vfpround (v2f64 VR128X:$src)))))), + (VCVTPD2PSZ128rr VR128X:$src)>; + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86vfpround (loadv2f64 addr:$src)))))), + (VCVTPD2PSZ128rm addr:$src)>; + def : Pat<(v2f64 (extloadv2f32 addr:$src)), + (VCVTPS2PDZ128rm addr:$src)>; + def : Pat<(v4f64 (extloadv4f32 addr:$src)), + (VCVTPS2PDZ256rm addr:$src)>; +} + +// Convert Signed/Unsigned Doubleword to Double +multiclass avx512_cvtdq2pd opc, string OpcodeStr, SDNode OpNode, + SDNode OpNode128, X86SchedWriteWidths sched> { + // No rounding in this op + let Predicates = [HasAVX512] in + defm Z : avx512_vcvt_fp, EVEX_V512; + + let Predicates = [HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Signed/Unsigned Doubleword to Float +multiclass avx512_cvtdq2ps opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + + let Predicates = [HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Float to Signed/Unsigned Doubleword with truncation +multiclass avx512_cvttps2dq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_sae, EVEX_V512; + } + let Predicates = [HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Float to Signed/Unsigned Doubleword +multiclass avx512_cvtps2dq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Double to Signed/Unsigned Doubleword with truncation +multiclass avx512_cvttpd2dq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_sae, EVEX_V512; + } + let Predicates = [HasVLX] in { + // we need "x"/"y" suffixes in order to distinguish between 128 and 256 + // memory forms of these instructions in Asm Parser. They have the same + // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly + // due to the same reason. + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + + def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; + def : InstAlias(NAME # "Z128rm") VR128X:$dst, i128mem:$src), 0, "intel">; + def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; + def : InstAlias(NAME # "Z256rm") VR128X:$dst, i256mem:$src), 0, "intel">; + } +} + +// Convert Double to Signed/Unsigned Doubleword +multiclass avx512_cvtpd2dq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasAVX512] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasVLX] in { + // we need "x"/"y" suffixes in order to distinguish between 128 and 256 + // memory forms of these instructions in Asm Parcer. They have the same + // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly + // due to the same reason. + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + + def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; + def : InstAlias(NAME # "Z128rm") VR128X:$dst, f128mem:$src), 0, "intel">; + def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; + def : InstAlias(NAME # "Z256rm") VR128X:$dst, f256mem:$src), 0, "intel">; + } +} + +// Convert Double to Signed/Unsigned Quardword +multiclass avx512_cvtpd2qq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasDQI] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasDQI, HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Double to Signed/Unsigned Quardword with truncation +multiclass avx512_cvttpd2qq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasDQI] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_sae, EVEX_V512; + } + let Predicates = [HasDQI, HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Signed/Unsigned Quardword to Double +multiclass avx512_cvtqq2pd opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasDQI] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasDQI, HasVLX] in { + defm Z128 : avx512_vcvt_fp, EVEX_V128, NotEVEX2VEXConvertible; + defm Z256 : avx512_vcvt_fp, EVEX_V256, NotEVEX2VEXConvertible; + } +} + +// Convert Float to Signed/Unsigned Quardword +multiclass avx512_cvtps2qq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasDQI] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasDQI, HasVLX] in { + // Explicitly specified broadcast string, since we take only 2 elements + // from v4f32x_info source + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Float to Signed/Unsigned Quardword with truncation +multiclass avx512_cvttps2qq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched> { + let Predicates = [HasDQI] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_sae, EVEX_V512; + } + let Predicates = [HasDQI, HasVLX] in { + // Explicitly specified broadcast string, since we take only 2 elements + // from v4f32x_info source + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; + } +} + +// Convert Signed/Unsigned Quardword to Float +multiclass avx512_cvtqq2ps opc, string OpcodeStr, SDNode OpNode, + SDNode OpNode128, SDNode OpNodeRnd, + X86SchedWriteWidths sched> { + let Predicates = [HasDQI] in { + defm Z : avx512_vcvt_fp, + avx512_vcvt_fp_rc, EVEX_V512; + } + let Predicates = [HasDQI, HasVLX] in { + // we need "x"/"y" suffixes in order to distinguish between 128 and 256 + // memory forms of these instructions in Asm Parcer. They have the same + // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly + // due to the same reason. + defm Z128 : avx512_vcvt_fp, EVEX_V128, + NotEVEX2VEXConvertible; + defm Z256 : avx512_vcvt_fp, EVEX_V256, + NotEVEX2VEXConvertible; + + def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; + def : InstAlias(NAME # "Z128rm") VR128X:$dst, i128mem:$src), 0, "intel">; + def : InstAlias(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>; + def : InstAlias(NAME # "Z256rm") VR128X:$dst, i256mem:$src), 0, "intel">; + } +} + +defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86VSintToFP, + SchedWriteCvtDQ2PD>, XS, EVEX_CD8<32, CD8VH>; + +defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp, + X86VSintToFpRnd, SchedWriteCvtDQ2PS>, + PS, EVEX_CD8<32, CD8VF>; + +defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", X86cvttp2si, + X86cvttp2siRnd, SchedWriteCvtPS2DQ>, + XS, EVEX_CD8<32, CD8VF>; + +defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", X86cvttp2si, + X86cvttp2siRnd, SchedWriteCvtPD2DQ>, + PD, VEX_W, EVEX_CD8<64, CD8VF>; + +defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", X86cvttp2ui, + X86cvttp2uiRnd, SchedWriteCvtPS2DQ>, PS, + EVEX_CD8<32, CD8VF>; + +defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", X86cvttp2ui, + X86cvttp2uiRnd, SchedWriteCvtPD2DQ>, + PS, VEX_W, EVEX_CD8<64, CD8VF>; + +defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, + X86VUintToFP, SchedWriteCvtDQ2PD>, XS, + EVEX_CD8<32, CD8VH>; + +defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp, + X86VUintToFpRnd, SchedWriteCvtDQ2PS>, XD, + EVEX_CD8<32, CD8VF>; + +defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtp2Int, + X86cvtp2IntRnd, SchedWriteCvtPS2DQ>, PD, + EVEX_CD8<32, CD8VF>; + +defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtp2Int, + X86cvtp2IntRnd, SchedWriteCvtPD2DQ>, XD, + VEX_W, EVEX_CD8<64, CD8VF>; + +defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtp2UInt, + X86cvtp2UIntRnd, SchedWriteCvtPS2DQ>, + PS, EVEX_CD8<32, CD8VF>; + +defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtp2UInt, + X86cvtp2UIntRnd, SchedWriteCvtPD2DQ>, VEX_W, + PS, EVEX_CD8<64, CD8VF>; + +defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtp2Int, + X86cvtp2IntRnd, SchedWriteCvtPD2DQ>, VEX_W, + PD, EVEX_CD8<64, CD8VF>; + +defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtp2Int, + X86cvtp2IntRnd, SchedWriteCvtPS2DQ>, PD, + EVEX_CD8<32, CD8VH>; + +defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtp2UInt, + X86cvtp2UIntRnd, SchedWriteCvtPD2DQ>, VEX_W, + PD, EVEX_CD8<64, CD8VF>; + +defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtp2UInt, + X86cvtp2UIntRnd, SchedWriteCvtPS2DQ>, PD, + EVEX_CD8<32, CD8VH>; + +defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", X86cvttp2si, + X86cvttp2siRnd, SchedWriteCvtPD2DQ>, VEX_W, + PD, EVEX_CD8<64, CD8VF>; + +defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", X86cvttp2si, + X86cvttp2siRnd, SchedWriteCvtPS2DQ>, PD, + EVEX_CD8<32, CD8VH>; + +defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", X86cvttp2ui, + X86cvttp2uiRnd, SchedWriteCvtPD2DQ>, VEX_W, + PD, EVEX_CD8<64, CD8VF>; + +defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", X86cvttp2ui, + X86cvttp2uiRnd, SchedWriteCvtPS2DQ>, PD, + EVEX_CD8<32, CD8VH>; + +defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp, + X86VSintToFpRnd, SchedWriteCvtDQ2PD>, VEX_W, XS, + EVEX_CD8<64, CD8VF>; + +defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp, + X86VUintToFpRnd, SchedWriteCvtDQ2PD>, VEX_W, XS, + EVEX_CD8<64, CD8VF>; + +defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp, X86VSintToFP, + X86VSintToFpRnd, SchedWriteCvtDQ2PS>, VEX_W, PS, + EVEX_CD8<64, CD8VF>; + +defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp, X86VUintToFP, + X86VUintToFpRnd, SchedWriteCvtDQ2PS>, VEX_W, XD, + EVEX_CD8<64, CD8VF>; + +let Predicates = [HasAVX512] in { + def : Pat<(v16i32 (fp_to_sint (v16f32 VR512:$src))), + (VCVTTPS2DQZrr VR512:$src)>; + def : Pat<(v16i32 (fp_to_sint (loadv16f32 addr:$src))), + (VCVTTPS2DQZrm addr:$src)>; + + def : Pat<(v16i32 (fp_to_uint (v16f32 VR512:$src))), + (VCVTTPS2UDQZrr VR512:$src)>; + def : Pat<(v16i32 (fp_to_uint (loadv16f32 addr:$src))), + (VCVTTPS2UDQZrm addr:$src)>; + + def : Pat<(v8i32 (fp_to_sint (v8f64 VR512:$src))), + (VCVTTPD2DQZrr VR512:$src)>; + def : Pat<(v8i32 (fp_to_sint (loadv8f64 addr:$src))), + (VCVTTPD2DQZrm addr:$src)>; + + def : Pat<(v8i32 (fp_to_uint (v8f64 VR512:$src))), + (VCVTTPD2UDQZrr VR512:$src)>; + def : Pat<(v8i32 (fp_to_uint (loadv8f64 addr:$src))), + (VCVTTPD2UDQZrm addr:$src)>; +} + +let Predicates = [HasVLX] in { + def : Pat<(v4i32 (fp_to_sint (v4f32 VR128X:$src))), + (VCVTTPS2DQZ128rr VR128X:$src)>; + def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))), + (VCVTTPS2DQZ128rm addr:$src)>; + + def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src))), + (VCVTTPS2UDQZ128rr VR128X:$src)>; + def : Pat<(v4i32 (fp_to_uint (loadv4f32 addr:$src))), + (VCVTTPS2UDQZ128rm addr:$src)>; + + def : Pat<(v8i32 (fp_to_sint (v8f32 VR256X:$src))), + (VCVTTPS2DQZ256rr VR256X:$src)>; + def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))), + (VCVTTPS2DQZ256rm addr:$src)>; + + def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src))), + (VCVTTPS2UDQZ256rr VR256X:$src)>; + def : Pat<(v8i32 (fp_to_uint (loadv8f32 addr:$src))), + (VCVTTPS2UDQZ256rm addr:$src)>; + + def : Pat<(v4i32 (fp_to_sint (v4f64 VR256X:$src))), + (VCVTTPD2DQZ256rr VR256X:$src)>; + def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))), + (VCVTTPD2DQZ256rm addr:$src)>; + + def : Pat<(v4i32 (fp_to_uint (v4f64 VR256X:$src))), + (VCVTTPD2UDQZ256rr VR256X:$src)>; + def : Pat<(v4i32 (fp_to_uint (loadv4f64 addr:$src))), + (VCVTTPD2UDQZ256rm addr:$src)>; +} + +let Predicates = [HasDQI] in { + def : Pat<(v8i64 (fp_to_sint (v8f32 VR256X:$src))), + (VCVTTPS2QQZrr VR256X:$src)>; + def : Pat<(v8i64 (fp_to_sint (loadv8f32 addr:$src))), + (VCVTTPS2QQZrm addr:$src)>; + + def : Pat<(v8i64 (fp_to_uint (v8f32 VR256X:$src))), + (VCVTTPS2UQQZrr VR256X:$src)>; + def : Pat<(v8i64 (fp_to_uint (loadv8f32 addr:$src))), + (VCVTTPS2UQQZrm addr:$src)>; + + def : Pat<(v8i64 (fp_to_sint (v8f64 VR512:$src))), + (VCVTTPD2QQZrr VR512:$src)>; + def : Pat<(v8i64 (fp_to_sint (loadv8f64 addr:$src))), + (VCVTTPD2QQZrm addr:$src)>; + + def : Pat<(v8i64 (fp_to_uint (v8f64 VR512:$src))), + (VCVTTPD2UQQZrr VR512:$src)>; + def : Pat<(v8i64 (fp_to_uint (loadv8f64 addr:$src))), + (VCVTTPD2UQQZrm addr:$src)>; +} + +let Predicates = [HasDQI, HasVLX] in { + def : Pat<(v4i64 (fp_to_sint (v4f32 VR128X:$src))), + (VCVTTPS2QQZ256rr VR128X:$src)>; + def : Pat<(v4i64 (fp_to_sint (loadv4f32 addr:$src))), + (VCVTTPS2QQZ256rm addr:$src)>; + + def : Pat<(v4i64 (fp_to_uint (v4f32 VR128X:$src))), + (VCVTTPS2UQQZ256rr VR128X:$src)>; + def : Pat<(v4i64 (fp_to_uint (loadv4f32 addr:$src))), + (VCVTTPS2UQQZ256rm addr:$src)>; + + def : Pat<(v2i64 (fp_to_sint (v2f64 VR128X:$src))), + (VCVTTPD2QQZ128rr VR128X:$src)>; + def : Pat<(v2i64 (fp_to_sint (loadv2f64 addr:$src))), + (VCVTTPD2QQZ128rm addr:$src)>; + + def : Pat<(v2i64 (fp_to_uint (v2f64 VR128X:$src))), + (VCVTTPD2UQQZ128rr VR128X:$src)>; + def : Pat<(v2i64 (fp_to_uint (loadv2f64 addr:$src))), + (VCVTTPD2UQQZ128rm addr:$src)>; + + def : Pat<(v4i64 (fp_to_sint (v4f64 VR256X:$src))), + (VCVTTPD2QQZ256rr VR256X:$src)>; + def : Pat<(v4i64 (fp_to_sint (loadv4f64 addr:$src))), + (VCVTTPD2QQZ256rm addr:$src)>; + + def : Pat<(v4i64 (fp_to_uint (v4f64 VR256X:$src))), + (VCVTTPD2UQQZ256rr VR256X:$src)>; + def : Pat<(v4i64 (fp_to_uint (loadv4f64 addr:$src))), + (VCVTTPD2UQQZ256rm addr:$src)>; +} + +let Predicates = [HasAVX512, NoVLX] in { +def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))), + (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr + (v16f32 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_ymm)>; + +def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))), + (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr + (v16f32 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; + +def : Pat<(v4i32 (fp_to_uint (v4f64 VR256X:$src1))), + (EXTRACT_SUBREG (v8i32 (VCVTTPD2UDQZrr + (v8f64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_xmm)>; + +def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))), + (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_ymm)>; + +def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))), + (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr + (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; + +def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))), + (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr + (v8i32 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_ymm)>; + +def : Pat<(v2f64 (X86VUintToFP (v4i32 VR128X:$src1))), + (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr + (v8i32 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; +} + +let Predicates = [HasAVX512, HasVLX] in { + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2Int (v2f64 VR128X:$src)))))), + (VCVTPD2DQZ128rr VR128X:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2Int (loadv2f64 addr:$src)))))), + (VCVTPD2DQZ128rm addr:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2UInt (v2f64 VR128X:$src)))))), + (VCVTPD2UDQZ128rr VR128X:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2si (v2f64 VR128X:$src)))))), + (VCVTTPD2DQZ128rr VR128X:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2si (loadv2f64 addr:$src)))))), + (VCVTTPD2DQZ128rm addr:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2ui (v2f64 VR128X:$src)))))), + (VCVTTPD2UDQZ128rr VR128X:$src)>; + + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (VCVTDQ2PDZ128rm addr:$src)>; + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (X86vzload addr:$src))))), + (VCVTDQ2PDZ128rm addr:$src)>; + + def : Pat<(v2f64 (X86VUintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (VCVTUDQ2PDZ128rm addr:$src)>; + def : Pat<(v2f64 (X86VUintToFP (bc_v4i32 (v2i64 (X86vzload addr:$src))))), + (VCVTUDQ2PDZ128rm addr:$src)>; +} + +let Predicates = [HasAVX512] in { + def : Pat<(v8f32 (fpround (loadv8f64 addr:$src))), + (VCVTPD2PSZrm addr:$src)>; + def : Pat<(v8f64 (extloadv8f32 addr:$src)), + (VCVTPS2PDZrm addr:$src)>; +} + +let Predicates = [HasDQI, HasVLX] in { + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86VSintToFP (v2i64 VR128X:$src)))))), + (VCVTQQ2PSZ128rr VR128X:$src)>; + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86VUintToFP (v2i64 VR128X:$src)))))), + (VCVTUQQ2PSZ128rr VR128X:$src)>; +} + +let Predicates = [HasDQI, NoVLX] in { +def : Pat<(v2i64 (fp_to_sint (v2f64 VR128X:$src1))), + (EXTRACT_SUBREG (v8i64 (VCVTTPD2QQZrr + (v8f64 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; + +def : Pat<(v4i64 (fp_to_sint (v4f32 VR128X:$src1))), + (EXTRACT_SUBREG (v8i64 (VCVTTPS2QQZrr + (v8f32 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_ymm)>; + +def : Pat<(v4i64 (fp_to_sint (v4f64 VR256X:$src1))), + (EXTRACT_SUBREG (v8i64 (VCVTTPD2QQZrr + (v8f64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_ymm)>; + +def : Pat<(v2i64 (fp_to_uint (v2f64 VR128X:$src1))), + (EXTRACT_SUBREG (v8i64 (VCVTTPD2UQQZrr + (v8f64 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; + +def : Pat<(v4i64 (fp_to_uint (v4f32 VR128X:$src1))), + (EXTRACT_SUBREG (v8i64 (VCVTTPS2UQQZrr + (v8f32 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_ymm)>; + +def : Pat<(v4i64 (fp_to_uint (v4f64 VR256X:$src1))), + (EXTRACT_SUBREG (v8i64 (VCVTTPD2UQQZrr + (v8f64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_ymm)>; + +def : Pat<(v4f32 (sint_to_fp (v4i64 VR256X:$src1))), + (EXTRACT_SUBREG (v8f32 (VCVTQQ2PSZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_xmm)>; + +def : Pat<(v2f64 (sint_to_fp (v2i64 VR128X:$src1))), + (EXTRACT_SUBREG (v8f64 (VCVTQQ2PDZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; + +def : Pat<(v4f64 (sint_to_fp (v4i64 VR256X:$src1))), + (EXTRACT_SUBREG (v8f64 (VCVTQQ2PDZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_ymm)>; + +def : Pat<(v4f32 (uint_to_fp (v4i64 VR256X:$src1))), + (EXTRACT_SUBREG (v8f32 (VCVTUQQ2PSZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_xmm)>; + +def : Pat<(v2f64 (uint_to_fp (v2i64 VR128X:$src1))), + (EXTRACT_SUBREG (v8f64 (VCVTUQQ2PDZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR128X:$src1, sub_xmm)))), sub_xmm)>; + +def : Pat<(v4f64 (uint_to_fp (v4i64 VR256X:$src1))), + (EXTRACT_SUBREG (v8f64 (VCVTUQQ2PDZrr + (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src1, sub_ymm)))), sub_ymm)>; +} + +//===----------------------------------------------------------------------===// +// Half precision conversion instructions +//===----------------------------------------------------------------------===// + +multiclass avx512_cvtph2ps { + defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), + (ins _src.RC:$src), "vcvtph2ps", "$src", "$src", + (X86cvtph2ps (_src.VT _src.RC:$src))>, + T8PD, Sched<[sched]>; + defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), + (ins x86memop:$src), "vcvtph2ps", "$src", "$src", + (X86cvtph2ps (_src.VT + (bitconvert + (ld_frag addr:$src))))>, + T8PD, Sched<[sched.Folded]>; +} + +multiclass avx512_cvtph2ps_sae { + defm rrb : AVX512_maskable<0x13, MRMSrcReg, _dest, (outs _dest.RC:$dst), + (ins _src.RC:$src), "vcvtph2ps", + "{sae}, $src", "$src, {sae}", + (X86cvtph2psRnd (_src.VT _src.RC:$src), + (i32 FROUND_NO_EXC))>, + T8PD, EVEX_B, Sched<[sched]>; +} + +let Predicates = [HasAVX512] in + defm VCVTPH2PSZ : avx512_cvtph2ps, + avx512_cvtph2ps_sae, + EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>; + +let Predicates = [HasVLX] in { + defm VCVTPH2PSZ256 : avx512_cvtph2ps, EVEX, EVEX_V256, + EVEX_CD8<32, CD8VH>; + defm VCVTPH2PSZ128 : avx512_cvtph2ps, EVEX, EVEX_V128, + EVEX_CD8<32, CD8VH>; + + // Pattern match vcvtph2ps of a scalar i64 load. + def : Pat<(v4f32 (X86cvtph2ps (v8i16 (vzmovl_v2i64 addr:$src)))), + (VCVTPH2PSZ128rm addr:$src)>; + def : Pat<(v4f32 (X86cvtph2ps (v8i16 (vzload_v2i64 addr:$src)))), + (VCVTPH2PSZ128rm addr:$src)>; + def : Pat<(v4f32 (X86cvtph2ps (v8i16 (bitconvert + (v2i64 (scalar_to_vector (loadi64 addr:$src))))))), + (VCVTPH2PSZ128rm addr:$src)>; +} + +multiclass avx512_cvtps2ph { + defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst), + (ins _src.RC:$src1, i32u8imm:$src2), + "vcvtps2ph", "$src2, $src1", "$src1, $src2", + (X86cvtps2ph (_src.VT _src.RC:$src1), + (i32 imm:$src2)), 0, 0>, + AVX512AIi8Base, Sched<[RR]>; + let hasSideEffects = 0, mayStore = 1 in { + def mr : AVX512AIi8<0x1D, MRMDestMem, (outs), + (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2), + "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + Sched<[MR]>; + def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs), + (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2), + "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}", []>, + EVEX_K, Sched<[MR]>, NotMemoryFoldable; + } +} + +multiclass avx512_cvtps2ph_sae { + let hasSideEffects = 0 in + defm rrb : AVX512_maskable_in_asm<0x1D, MRMDestReg, _dest, + (outs _dest.RC:$dst), + (ins _src.RC:$src1, i32u8imm:$src2), + "vcvtps2ph", "$src2, {sae}, $src1", "$src1, {sae}, $src2", []>, + EVEX_B, AVX512AIi8Base, Sched<[Sched]>; +} + +let Predicates = [HasAVX512] in { + defm VCVTPS2PHZ : avx512_cvtps2ph, + avx512_cvtps2ph_sae, + EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>; + let Predicates = [HasVLX] in { + defm VCVTPS2PHZ256 : avx512_cvtps2ph, + EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>; + defm VCVTPS2PHZ128 : avx512_cvtps2ph, + EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>; + } + + def : Pat<(store (f64 (extractelt + (bc_v2f64 (v8i16 (X86cvtps2ph VR128X:$src1, i32:$src2))), + (iPTR 0))), addr:$dst), + (VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, imm:$src2)>; + def : Pat<(store (i64 (extractelt + (bc_v2i64 (v8i16 (X86cvtps2ph VR128X:$src1, i32:$src2))), + (iPTR 0))), addr:$dst), + (VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, imm:$src2)>; + def : Pat<(store (v8i16 (X86cvtps2ph VR256X:$src1, i32:$src2)), addr:$dst), + (VCVTPS2PHZ256mr addr:$dst, VR256X:$src1, imm:$src2)>; + def : Pat<(store (v16i16 (X86cvtps2ph VR512:$src1, i32:$src2)), addr:$dst), + (VCVTPS2PHZmr addr:$dst, VR512:$src1, imm:$src2)>; +} + +// Patterns for matching conversions from float to half-float and vice versa. +let Predicates = [HasVLX] in { + // Use MXCSR.RC for rounding instead of explicitly specifying the default + // rounding mode (Nearest-Even, encoded as 0). Both are equivalent in the + // configurations we support (the default). However, falling back to MXCSR is + // more consistent with other instructions, which are always controlled by it. + // It's encoded as 0b100. + def : Pat<(fp_to_f16 FR32X:$src), + (i16 (EXTRACT_SUBREG (VMOVPDI2DIZrr (v8i16 (VCVTPS2PHZ128rr + (v4f32 (COPY_TO_REGCLASS FR32X:$src, VR128X)), 4))), sub_16bit))>; + + def : Pat<(f16_to_fp GR16:$src), + (f32 (COPY_TO_REGCLASS (v4f32 (VCVTPH2PSZ128rr + (v8i16 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128X)))), FR32X)) >; + + def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32X:$src))), + (f32 (COPY_TO_REGCLASS (v4f32 (VCVTPH2PSZ128rr + (v8i16 (VCVTPS2PHZ128rr + (v4f32 (COPY_TO_REGCLASS FR32X:$src, VR128X)), 4)))), FR32X)) >; +} + +// Unordered/Ordered scalar fp compare with Sea and set EFLAGS +multiclass avx512_ord_cmp_sae opc, X86VectorVTInfo _, + string OpcodeStr, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def rrb: AVX512, + EVEX, EVEX_B, VEX_LIG, EVEX_V128, Sched<[sched]>; +} + +let Defs = [EFLAGS], Predicates = [HasAVX512] in { + defm VUCOMISSZ : avx512_ord_cmp_sae<0x2E, v4f32x_info, "vucomiss", WriteFCom>, + AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>; + defm VUCOMISDZ : avx512_ord_cmp_sae<0x2E, v2f64x_info, "vucomisd", WriteFCom>, + AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>; + defm VCOMISSZ : avx512_ord_cmp_sae<0x2F, v4f32x_info, "vcomiss", WriteFCom>, + AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>; + defm VCOMISDZ : avx512_ord_cmp_sae<0x2F, v2f64x_info, "vcomisd", WriteFCom>, + AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>; +} + +let Defs = [EFLAGS], Predicates = [HasAVX512] in { + defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32, + "ucomiss", WriteFCom>, PS, EVEX, VEX_LIG, + EVEX_CD8<32, CD8VT1>; + defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64, + "ucomisd", WriteFCom>, PD, EVEX, + VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; + let Pattern = [] in { + defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32, + "comiss", WriteFCom>, PS, EVEX, VEX_LIG, + EVEX_CD8<32, CD8VT1>; + defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64, + "comisd", WriteFCom>, PD, EVEX, + VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; + } + let isCodeGenOnly = 1 in { + defm VUCOMISSZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v4f32, ssmem, + sse_load_f32, "ucomiss", WriteFCom>, PS, EVEX, VEX_LIG, + EVEX_CD8<32, CD8VT1>; + defm VUCOMISDZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v2f64, sdmem, + sse_load_f64, "ucomisd", WriteFCom>, PD, EVEX, + VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; + + defm VCOMISSZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v4f32, ssmem, + sse_load_f32, "comiss", WriteFCom>, PS, EVEX, VEX_LIG, + EVEX_CD8<32, CD8VT1>; + defm VCOMISDZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v2f64, sdmem, + sse_load_f64, "comisd", WriteFCom>, PD, EVEX, + VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; + } +} + +/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd +multiclass avx512_fp14_s opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let Predicates = [HasAVX512], ExeDomain = _.ExeDomain in { + defm rr : AVX512_maskable_scalar, + EVEX_4V, Sched<[sched]>; + defm rm : AVX512_maskable_scalar, EVEX_4V, + Sched<[sched.Folded, ReadAfterLd]>; +} +} + +defm VRCP14SSZ : avx512_fp14_s<0x4D, "vrcp14ss", X86rcp14s, SchedWriteFRcp.Scl, + f32x_info>, EVEX_CD8<32, CD8VT1>, + T8PD; +defm VRCP14SDZ : avx512_fp14_s<0x4D, "vrcp14sd", X86rcp14s, SchedWriteFRcp.Scl, + f64x_info>, VEX_W, EVEX_CD8<64, CD8VT1>, + T8PD; +defm VRSQRT14SSZ : avx512_fp14_s<0x4F, "vrsqrt14ss", X86rsqrt14s, + SchedWriteFRsqrt.Scl, f32x_info>, + EVEX_CD8<32, CD8VT1>, T8PD; +defm VRSQRT14SDZ : avx512_fp14_s<0x4F, "vrsqrt14sd", X86rsqrt14s, + SchedWriteFRsqrt.Scl, f64x_info>, VEX_W, + EVEX_CD8<64, CD8VT1>, T8PD; + +/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd +multiclass avx512_fp14_p opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm r: AVX512_maskable, EVEX, T8PD, + Sched<[sched]>; + defm m: AVX512_maskable, EVEX, T8PD, + Sched<[sched.Folded, ReadAfterLd]>; + defm mb: AVX512_maskable, + EVEX, T8PD, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fp14_p_vl_all opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + defm PSZ : avx512_fp14_p, EVEX_V512, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp14_p, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; + + // Define only if AVX512VL feature is present. + let Predicates = [HasVLX] in { + defm PSZ128 : avx512_fp14_p, + EVEX_V128, EVEX_CD8<32, CD8VF>; + defm PSZ256 : avx512_fp14_p, + EVEX_V256, EVEX_CD8<32, CD8VF>; + defm PDZ128 : avx512_fp14_p, + EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>; + defm PDZ256 : avx512_fp14_p, + EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>; + } +} + +defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86rsqrt14, SchedWriteFRsqrt>; +defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86rcp14, SchedWriteFRcp>; + +/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd +multiclass avx512_fp28_s opc, string OpcodeStr,X86VectorVTInfo _, + SDNode OpNode, X86FoldableSchedWrite sched> { + let ExeDomain = _.ExeDomain in { + defm r : AVX512_maskable_scalar, + Sched<[sched]>; + + defm rb : AVX512_maskable_scalar, EVEX_B, + Sched<[sched]>; + + defm m : AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_eri_s opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched> { + defm SSZ : avx512_fp28_s, + EVEX_CD8<32, CD8VT1>; + defm SDZ : avx512_fp28_s, + EVEX_CD8<64, CD8VT1>, VEX_W; +} + +let Predicates = [HasERI] in { + defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s, SchedWriteFRcp.Scl>, + T8PD, EVEX_4V; + defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s, + SchedWriteFRsqrt.Scl>, T8PD, EVEX_4V; +} + +defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds, + SchedWriteFRnd.Scl>, T8PD, EVEX_4V; +/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd + +multiclass avx512_fp28_p opc, string OpcodeStr, X86VectorVTInfo _, + SDNode OpNode, X86FoldableSchedWrite sched> { + let ExeDomain = _.ExeDomain in { + defm r : AVX512_maskable, + Sched<[sched]>; + + defm m : AVX512_maskable, + Sched<[sched.Folded, ReadAfterLd]>; + + defm mb : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } +} +multiclass avx512_fp28_p_round opc, string OpcodeStr, X86VectorVTInfo _, + SDNode OpNode, X86FoldableSchedWrite sched> { + let ExeDomain = _.ExeDomain in + defm rb : AVX512_maskable, + EVEX_B, Sched<[sched]>; +} + +multiclass avx512_eri opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + defm PSZ : avx512_fp28_p, + avx512_fp28_p_round, + T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp28_p, + avx512_fp28_p_round, + T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; +} + +multiclass avx512_fp_unaryop_packed opc, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched> { + // Define only if AVX512VL feature is present. + let Predicates = [HasVLX] in { + defm PSZ128 : avx512_fp28_p, + EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>; + defm PSZ256 : avx512_fp28_p, + EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>; + defm PDZ128 : avx512_fp28_p, + EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>; + defm PDZ256 : avx512_fp28_p, + EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>; + } +} + +let Predicates = [HasERI] in { + defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28, SchedWriteFRsqrt>, EVEX; + defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28, SchedWriteFRcp>, EVEX; + defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2, SchedWriteFAdd>, EVEX; +} +defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd, SchedWriteFRnd>, + avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd, + SchedWriteFRnd>, EVEX; + +multiclass avx512_sqrt_packed_round opc, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _>{ + let ExeDomain = _.ExeDomain in + defm rb: AVX512_maskable, + EVEX, EVEX_B, EVEX_RC, Sched<[sched]>; +} + +multiclass avx512_sqrt_packed opc, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _>{ + let ExeDomain = _.ExeDomain in { + defm r: AVX512_maskable, EVEX, + Sched<[sched]>; + defm m: AVX512_maskable, EVEX, + Sched<[sched.Folded, ReadAfterLd]>; + defm mb: AVX512_maskable, + EVEX, EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_sqrt_packed_all opc, string OpcodeStr, + X86SchedWriteSizes sched> { + defm PSZ : avx512_sqrt_packed, + EVEX_V512, PS, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_sqrt_packed, + EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>; + // Define only if AVX512VL feature is present. + let Predicates = [HasVLX] in { + defm PSZ128 : avx512_sqrt_packed, + EVEX_V128, PS, EVEX_CD8<32, CD8VF>; + defm PSZ256 : avx512_sqrt_packed, + EVEX_V256, PS, EVEX_CD8<32, CD8VF>; + defm PDZ128 : avx512_sqrt_packed, + EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>; + defm PDZ256 : avx512_sqrt_packed, + EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>; + } +} + +multiclass avx512_sqrt_packed_all_round opc, string OpcodeStr, + X86SchedWriteSizes sched> { + defm PSZ : avx512_sqrt_packed_round, + EVEX_V512, PS, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_sqrt_packed_round, + EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>; +} + +multiclass avx512_sqrt_scalar opc, string OpcodeStr, X86FoldableSchedWrite sched, + X86VectorVTInfo _, string Name> { + let ExeDomain = _.ExeDomain in { + defm r_Int : AVX512_maskable_scalar, + Sched<[sched]>; + defm m_Int : AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + defm rb_Int : AVX512_maskable_scalar, + EVEX_B, EVEX_RC, Sched<[sched]>; + + let isCodeGenOnly = 1, hasSideEffects = 0, Predicates=[HasAVX512] in { + def r : I, + Sched<[sched]>; + let mayLoad = 1 in + def m : I, + Sched<[sched.Folded, ReadAfterLd]>; + } + } + + let Predicates = [HasAVX512] in { + def : Pat<(_.EltVT (fsqrt _.FRC:$src)), + (!cast(Name#Zr) + (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>; + } + + let Predicates = [HasAVX512, OptForSize] in { + def : Pat<(_.EltVT (fsqrt (load addr:$src))), + (!cast(Name#Zm) + (_.EltVT (IMPLICIT_DEF)), addr:$src)>; + } +} + +multiclass avx512_sqrt_scalar_all opc, string OpcodeStr, + X86SchedWriteSizes sched> { + defm SSZ : avx512_sqrt_scalar, + EVEX_CD8<32, CD8VT1>, EVEX_4V, XS; + defm SDZ : avx512_sqrt_scalar, + EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W; +} + +defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", SchedWriteFSqrtSizes>, + avx512_sqrt_packed_all_round<0x51, "vsqrt", SchedWriteFSqrtSizes>; + +defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt", SchedWriteFSqrtSizes>, VEX_LIG; + +multiclass avx512_rndscale_scalar opc, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm r_Int : AVX512_maskable_scalar, + Sched<[sched]>; + + defm rb_Int : AVX512_maskable_scalar, EVEX_B, + Sched<[sched]>; + + defm m_Int : AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + + let isCodeGenOnly = 1, hasSideEffects = 0, Predicates = [HasAVX512] in { + def r : I, Sched<[sched]>; + + let mayLoad = 1 in + def m : I, Sched<[sched.Folded, ReadAfterLd]>; + } + } + + let Predicates = [HasAVX512] in { + def : Pat<(ffloor _.FRC:$src), + (_.EltVT (!cast(NAME##r) (_.EltVT (IMPLICIT_DEF)), + _.FRC:$src, (i32 0x9)))>; + def : Pat<(fceil _.FRC:$src), + (_.EltVT (!cast(NAME##r) (_.EltVT (IMPLICIT_DEF)), + _.FRC:$src, (i32 0xa)))>; + def : Pat<(ftrunc _.FRC:$src), + (_.EltVT (!cast(NAME##r) (_.EltVT (IMPLICIT_DEF)), + _.FRC:$src, (i32 0xb)))>; + def : Pat<(frint _.FRC:$src), + (_.EltVT (!cast(NAME##r) (_.EltVT (IMPLICIT_DEF)), + _.FRC:$src, (i32 0x4)))>; + def : Pat<(fnearbyint _.FRC:$src), + (_.EltVT (!cast(NAME##r) (_.EltVT (IMPLICIT_DEF)), + _.FRC:$src, (i32 0xc)))>; + } + + let Predicates = [HasAVX512, OptForSize] in { + def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), + (_.EltVT (!cast(NAME##m) (_.EltVT (IMPLICIT_DEF)), + addr:$src, (i32 0x9)))>; + def : Pat<(fceil (_.ScalarLdFrag addr:$src)), + (_.EltVT (!cast(NAME##m) (_.EltVT (IMPLICIT_DEF)), + addr:$src, (i32 0xa)))>; + def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), + (_.EltVT (!cast(NAME##m) (_.EltVT (IMPLICIT_DEF)), + addr:$src, (i32 0xb)))>; + def : Pat<(frint (_.ScalarLdFrag addr:$src)), + (_.EltVT (!cast(NAME##m) (_.EltVT (IMPLICIT_DEF)), + addr:$src, (i32 0x4)))>; + def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), + (_.EltVT (!cast(NAME##m) (_.EltVT (IMPLICIT_DEF)), + addr:$src, (i32 0xc)))>; + } +} + +defm VRNDSCALESSZ : avx512_rndscale_scalar<0x0A, "vrndscaless", + SchedWriteFRnd.Scl, f32x_info>, + AVX512AIi8Base, EVEX_4V, + EVEX_CD8<32, CD8VT1>; + +defm VRNDSCALESDZ : avx512_rndscale_scalar<0x0B, "vrndscalesd", + SchedWriteFRnd.Scl, f64x_info>, + VEX_W, AVX512AIi8Base, EVEX_4V, + EVEX_CD8<64, CD8VT1>; + +multiclass avx512_masked_scalar { + let Predicates = [BasePredicate] in { + def : Pat<(Move _.VT:$src1, (scalar_to_vector (X86selects Mask, + (OpNode (extractelt _.VT:$src2, (iPTR 0))), + (extractelt _.VT:$dst, (iPTR 0))))), + (!cast("V"#OpcPrefix#r_Intk) + _.VT:$dst, OutMask, _.VT:$src2, _.VT:$src1)>; + + def : Pat<(Move _.VT:$src1, (scalar_to_vector (X86selects Mask, + (OpNode (extractelt _.VT:$src2, (iPTR 0))), + ZeroFP))), + (!cast("V"#OpcPrefix#r_Intkz) + OutMask, _.VT:$src2, _.VT:$src1)>; + } +} + +defm : avx512_masked_scalar; +defm : avx512_masked_scalar; + +multiclass avx512_masked_scalar_imm ImmV, Predicate BasePredicate> { + let Predicates = [BasePredicate] in { + def : Pat<(Move _.VT:$src1, (scalar_to_vector (X86selects VK1WM:$mask, + (OpNode (extractelt _.VT:$src2, (iPTR 0))), + (extractelt _.VT:$dst, (iPTR 0))))), + (!cast("V"#OpcPrefix#Zr_Intk) + _.VT:$dst, VK1WM:$mask, _.VT:$src1, _.VT:$src2, (i32 ImmV))>; + + def : Pat<(Move _.VT:$src1, (scalar_to_vector (X86selects VK1WM:$mask, + (OpNode (extractelt _.VT:$src2, (iPTR 0))), ZeroFP))), + (!cast("V"#OpcPrefix#Zr_Intkz) + VK1WM:$mask, _.VT:$src1, _.VT:$src2, (i32 ImmV))>; + } +} + +defm : avx512_masked_scalar_imm; +defm : avx512_masked_scalar_imm; +defm : avx512_masked_scalar_imm; +defm : avx512_masked_scalar_imm; + + +//------------------------------------------------- +// Integer truncate and extend operations +//------------------------------------------------- + +multiclass avx512_trunc_common opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo SrcInfo, + X86VectorVTInfo DestInfo, X86MemOperand x86memop> { + let ExeDomain = DestInfo.ExeDomain in + defm rr : AVX512_maskable, + EVEX, T8XS, Sched<[sched]>; + + let mayStore = 1, hasSideEffects = 0, ExeDomain = DestInfo.ExeDomain in { + def mr : AVX512XS8I, + EVEX, Sched<[sched.Folded]>; + + def mrk : AVX512XS8I, + EVEX, EVEX_K, Sched<[sched.Folded]>, NotMemoryFoldable; + }//mayStore = 1, hasSideEffects = 0 +} + +multiclass avx512_trunc_mr_lowering { + + def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst), + (!cast(Name#SrcInfo.ZSuffix##mr) + addr:$dst, SrcInfo.RC:$src)>; + + def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask, + (SrcInfo.VT SrcInfo.RC:$src)), + (!cast(Name#SrcInfo.ZSuffix##mrk) + addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>; +} + +multiclass avx512_trunc opc, string OpcodeStr, SDNode OpNode128, + SDNode OpNode256, SDNode OpNode512, X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTSrcInfo, + X86VectorVTInfo DestInfoZ128, + X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ, + X86MemOperand x86memopZ128, X86MemOperand x86memopZ256, + X86MemOperand x86memopZ, PatFrag truncFrag, + PatFrag mtruncFrag, Predicate prd = HasAVX512>{ + + let Predicates = [HasVLX, prd] in { + defm Z128: avx512_trunc_common, + avx512_trunc_mr_lowering, EVEX_V128; + + defm Z256: avx512_trunc_common, + avx512_trunc_mr_lowering, EVEX_V256; + } + let Predicates = [prd] in + defm Z: avx512_trunc_common, + avx512_trunc_mr_lowering, EVEX_V512; +} + +multiclass avx512_trunc_qb opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag StoreNode, + PatFrag MaskedStoreNode, SDNode InVecNode = OpNode> { + defm NAME: avx512_trunc, EVEX_CD8<8, CD8VO>; +} + +multiclass avx512_trunc_qw opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag StoreNode, + PatFrag MaskedStoreNode, SDNode InVecNode = OpNode> { + defm NAME: avx512_trunc, EVEX_CD8<16, CD8VQ>; +} + +multiclass avx512_trunc_qd opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag StoreNode, + PatFrag MaskedStoreNode, SDNode InVecNode = OpNode> { + defm NAME: avx512_trunc, EVEX_CD8<32, CD8VH>; +} + +multiclass avx512_trunc_db opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag StoreNode, + PatFrag MaskedStoreNode, SDNode InVecNode = OpNode> { + defm NAME: avx512_trunc, EVEX_CD8<8, CD8VQ>; +} + +multiclass avx512_trunc_dw opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag StoreNode, + PatFrag MaskedStoreNode, SDNode InVecNode = OpNode> { + defm NAME: avx512_trunc, EVEX_CD8<16, CD8VH>; +} + +multiclass avx512_trunc_wb opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag StoreNode, + PatFrag MaskedStoreNode, SDNode InVecNode = OpNode> { + defm NAME: avx512_trunc, EVEX_CD8<16, CD8VH>; +} + +defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", trunc, WriteShuffle256, + truncstorevi8, masked_truncstorevi8, X86vtrunc>; +defm VPMOVSQB : avx512_trunc_qb<0x22, "vpmovsqb", X86vtruncs, WriteShuffle256, + truncstore_s_vi8, masked_truncstore_s_vi8>; +defm VPMOVUSQB : avx512_trunc_qb<0x12, "vpmovusqb", X86vtruncus, WriteShuffle256, + truncstore_us_vi8, masked_truncstore_us_vi8>; + +defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", trunc, WriteShuffle256, + truncstorevi16, masked_truncstorevi16, X86vtrunc>; +defm VPMOVSQW : avx512_trunc_qw<0x24, "vpmovsqw", X86vtruncs, WriteShuffle256, + truncstore_s_vi16, masked_truncstore_s_vi16>; +defm VPMOVUSQW : avx512_trunc_qw<0x14, "vpmovusqw", X86vtruncus, WriteShuffle256, + truncstore_us_vi16, masked_truncstore_us_vi16>; + +defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", trunc, WriteShuffle256, + truncstorevi32, masked_truncstorevi32, X86vtrunc>; +defm VPMOVSQD : avx512_trunc_qd<0x25, "vpmovsqd", X86vtruncs, WriteShuffle256, + truncstore_s_vi32, masked_truncstore_s_vi32>; +defm VPMOVUSQD : avx512_trunc_qd<0x15, "vpmovusqd", X86vtruncus, WriteShuffle256, + truncstore_us_vi32, masked_truncstore_us_vi32>; + +defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", trunc, WriteShuffle256, + truncstorevi8, masked_truncstorevi8, X86vtrunc>; +defm VPMOVSDB : avx512_trunc_db<0x21, "vpmovsdb", X86vtruncs, WriteShuffle256, + truncstore_s_vi8, masked_truncstore_s_vi8>; +defm VPMOVUSDB : avx512_trunc_db<0x11, "vpmovusdb", X86vtruncus, WriteShuffle256, + truncstore_us_vi8, masked_truncstore_us_vi8>; + +defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", trunc, WriteShuffle256, + truncstorevi16, masked_truncstorevi16, X86vtrunc>; +defm VPMOVSDW : avx512_trunc_dw<0x23, "vpmovsdw", X86vtruncs, WriteShuffle256, + truncstore_s_vi16, masked_truncstore_s_vi16>; +defm VPMOVUSDW : avx512_trunc_dw<0x13, "vpmovusdw", X86vtruncus, WriteShuffle256, + truncstore_us_vi16, masked_truncstore_us_vi16>; + +defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", trunc, WriteShuffle256, + truncstorevi8, masked_truncstorevi8, X86vtrunc>; +defm VPMOVSWB : avx512_trunc_wb<0x20, "vpmovswb", X86vtruncs, WriteShuffle256, + truncstore_s_vi8, masked_truncstore_s_vi8>; +defm VPMOVUSWB : avx512_trunc_wb<0x10, "vpmovuswb", X86vtruncus, WriteShuffle256, + truncstore_us_vi8, masked_truncstore_us_vi8>; + +let Predicates = [HasAVX512, NoVLX] in { +def: Pat<(v8i16 (trunc (v8i32 VR256X:$src))), + (v8i16 (EXTRACT_SUBREG + (v16i16 (VPMOVDWZrr (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src, sub_ymm)))), sub_xmm))>; +def: Pat<(v4i32 (trunc (v4i64 VR256X:$src))), + (v4i32 (EXTRACT_SUBREG + (v8i32 (VPMOVQDZrr (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src, sub_ymm)))), sub_xmm))>; +} + +let Predicates = [HasBWI, NoVLX] in { +def: Pat<(v16i8 (trunc (v16i16 VR256X:$src))), + (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (INSERT_SUBREG (IMPLICIT_DEF), + VR256X:$src, sub_ymm))), sub_xmm))>; +} + +multiclass WriteShuffle256_common opc, string OpcodeStr, X86FoldableSchedWrite sched, + X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo, + X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{ + let ExeDomain = DestInfo.ExeDomain in { + defm rr : AVX512_maskable, + EVEX, Sched<[sched]>; + + defm rm : AVX512_maskable, + EVEX, Sched<[sched.Folded]>; + } +} + +multiclass WriteShuffle256_BW opc, string OpcodeStr, + SDNode OpNode, SDNode InVecNode, string ExtTy, + X86FoldableSchedWrite sched, PatFrag LdFrag = !cast(ExtTy#"extloadvi8")> { + let Predicates = [HasVLX, HasBWI] in { + defm Z128: WriteShuffle256_common, + EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128, VEX_WIG; + + defm Z256: WriteShuffle256_common, + EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256, VEX_WIG; + } + let Predicates = [HasBWI] in { + defm Z : WriteShuffle256_common, + EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512, VEX_WIG; + } +} + +multiclass WriteShuffle256_BD opc, string OpcodeStr, + SDNode OpNode, SDNode InVecNode, string ExtTy, + X86FoldableSchedWrite sched, PatFrag LdFrag = !cast(ExtTy#"extloadvi8")> { + let Predicates = [HasVLX, HasAVX512] in { + defm Z128: WriteShuffle256_common, + EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128, VEX_WIG; + + defm Z256: WriteShuffle256_common, + EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256, VEX_WIG; + } + let Predicates = [HasAVX512] in { + defm Z : WriteShuffle256_common, + EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512, VEX_WIG; + } +} + +multiclass WriteShuffle256_BQ opc, string OpcodeStr, + SDNode OpNode, SDNode InVecNode, string ExtTy, + X86FoldableSchedWrite sched, PatFrag LdFrag = !cast(ExtTy#"extloadvi8")> { + let Predicates = [HasVLX, HasAVX512] in { + defm Z128: WriteShuffle256_common, + EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128, VEX_WIG; + + defm Z256: WriteShuffle256_common, + EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256, VEX_WIG; + } + let Predicates = [HasAVX512] in { + defm Z : WriteShuffle256_common, + EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512, VEX_WIG; + } +} + +multiclass WriteShuffle256_WD opc, string OpcodeStr, + SDNode OpNode, SDNode InVecNode, string ExtTy, + X86FoldableSchedWrite sched, PatFrag LdFrag = !cast(ExtTy#"extloadvi16")> { + let Predicates = [HasVLX, HasAVX512] in { + defm Z128: WriteShuffle256_common, + EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128, VEX_WIG; + + defm Z256: WriteShuffle256_common, + EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256, VEX_WIG; + } + let Predicates = [HasAVX512] in { + defm Z : WriteShuffle256_common, + EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512, VEX_WIG; + } +} + +multiclass WriteShuffle256_WQ opc, string OpcodeStr, + SDNode OpNode, SDNode InVecNode, string ExtTy, + X86FoldableSchedWrite sched, PatFrag LdFrag = !cast(ExtTy#"extloadvi16")> { + let Predicates = [HasVLX, HasAVX512] in { + defm Z128: WriteShuffle256_common, + EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128, VEX_WIG; + + defm Z256: WriteShuffle256_common, + EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256, VEX_WIG; + } + let Predicates = [HasAVX512] in { + defm Z : WriteShuffle256_common, + EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512, VEX_WIG; + } +} + +multiclass WriteShuffle256_DQ opc, string OpcodeStr, + SDNode OpNode, SDNode InVecNode, string ExtTy, + X86FoldableSchedWrite sched, PatFrag LdFrag = !cast(ExtTy#"extloadvi32")> { + + let Predicates = [HasVLX, HasAVX512] in { + defm Z128: WriteShuffle256_common, + EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128; + + defm Z256: WriteShuffle256_common, + EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256; + } + let Predicates = [HasAVX512] in { + defm Z : WriteShuffle256_common, + EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512; + } +} + +defm VPMOVZXBW : WriteShuffle256_BW<0x30, "vpmovzxbw", X86vzext, zext_invec, "z", WriteShuffle256>; +defm VPMOVZXBD : WriteShuffle256_BD<0x31, "vpmovzxbd", X86vzext, zext_invec, "z", WriteShuffle256>; +defm VPMOVZXBQ : WriteShuffle256_BQ<0x32, "vpmovzxbq", X86vzext, zext_invec, "z", WriteShuffle256>; +defm VPMOVZXWD : WriteShuffle256_WD<0x33, "vpmovzxwd", X86vzext, zext_invec, "z", WriteShuffle256>; +defm VPMOVZXWQ : WriteShuffle256_WQ<0x34, "vpmovzxwq", X86vzext, zext_invec, "z", WriteShuffle256>; +defm VPMOVZXDQ : WriteShuffle256_DQ<0x35, "vpmovzxdq", X86vzext, zext_invec, "z", WriteShuffle256>; + +defm VPMOVSXBW: WriteShuffle256_BW<0x20, "vpmovsxbw", X86vsext, sext_invec, "s", WriteShuffle256>; +defm VPMOVSXBD: WriteShuffle256_BD<0x21, "vpmovsxbd", X86vsext, sext_invec, "s", WriteShuffle256>; +defm VPMOVSXBQ: WriteShuffle256_BQ<0x22, "vpmovsxbq", X86vsext, sext_invec, "s", WriteShuffle256>; +defm VPMOVSXWD: WriteShuffle256_WD<0x23, "vpmovsxwd", X86vsext, sext_invec, "s", WriteShuffle256>; +defm VPMOVSXWQ: WriteShuffle256_WQ<0x24, "vpmovsxwq", X86vsext, sext_invec, "s", WriteShuffle256>; +defm VPMOVSXDQ: WriteShuffle256_DQ<0x25, "vpmovsxdq", X86vsext, sext_invec, "s", WriteShuffle256>; + + +multiclass AVX512_pmovx_patterns { + // 128-bit patterns + let Predicates = [HasVLX, HasBWI] in { + def : Pat<(v8i16 (InVecOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#BWZ128rm) addr:$src)>; + def : Pat<(v8i16 (InVecOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))), + (!cast(OpcPrefix#BWZ128rm) addr:$src)>; + def : Pat<(v8i16 (InVecOp (v16i8 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWZ128rm) addr:$src)>; + def : Pat<(v8i16 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWZ128rm) addr:$src)>; + def : Pat<(v8i16 (InVecOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BWZ128rm) addr:$src)>; + } + let Predicates = [HasVLX] in { + def : Pat<(v4i32 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))), + (!cast(OpcPrefix#BDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (v16i8 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#BDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BDZ128rm) addr:$src)>; + + def : Pat<(v2i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (extloadi32i16 addr:$src)))))), + (!cast(OpcPrefix#BQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (v16i8 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#BQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BQZ128rm) addr:$src)>; + + def : Pat<(v4i32 (InVecOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#WDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))), + (!cast(OpcPrefix#WDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (v8i16 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDZ128rm) addr:$src)>; + def : Pat<(v4i32 (InVecOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WDZ128rm) addr:$src)>; + + def : Pat<(v2i64 (InVecOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))), + (!cast(OpcPrefix#WQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (v8i16 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#WQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WQZ128rm) addr:$src)>; + + def : Pat<(v2i64 (InVecOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#DQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))), + (!cast(OpcPrefix#DQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (v4i32 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (v4i32 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQZ128rm) addr:$src)>; + def : Pat<(v2i64 (InVecOp (bc_v4i32 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#DQZ128rm) addr:$src)>; + } + // 256-bit patterns + let Predicates = [HasVLX, HasBWI] in { + def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BWZ256rm) addr:$src)>; + def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWZ256rm) addr:$src)>; + def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWZ256rm) addr:$src)>; + } + let Predicates = [HasVLX] in { + def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#BDZ256rm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#BDZ256rm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BDZ256rm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BDZ256rm) addr:$src)>; + + def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))), + (!cast(OpcPrefix#BQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#BQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BQZ256rm) addr:$src)>; + + def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WDZ256rm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDZ256rm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDZ256rm) addr:$src)>; + + def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#WQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#WQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WQZ256rm) addr:$src)>; + + def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#DQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQZ256rm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQZ256rm) addr:$src)>; + } + // 512-bit patterns + let Predicates = [HasBWI] in { + def : Pat<(v32i16 (ExtOp (bc_v32i8 (loadv4i64 addr:$src)))), + (!cast(OpcPrefix#BWZrm) addr:$src)>; + } + let Predicates = [HasAVX512] in { + def : Pat<(v16i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BDZrm) addr:$src)>; + + def : Pat<(v8i64 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#BQZrm) addr:$src)>; + def : Pat<(v8i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BQZrm) addr:$src)>; + + def : Pat<(v16i32 (ExtOp (bc_v16i16 (loadv4i64 addr:$src)))), + (!cast(OpcPrefix#WDZrm) addr:$src)>; + + def : Pat<(v8i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WQZrm) addr:$src)>; + + def : Pat<(v8i64 (ExtOp (bc_v8i32 (loadv4i64 addr:$src)))), + (!cast(OpcPrefix#DQZrm) addr:$src)>; + } +} + +defm : AVX512_pmovx_patterns<"VPMOVSX", X86vsext, sext_invec>; +defm : AVX512_pmovx_patterns<"VPMOVZX", X86vzext, zext_invec>; + +//===----------------------------------------------------------------------===// +// GATHER - SCATTER Operations + +// FIXME: Improve scheduling of gather/scatter instructions. +multiclass avx512_gather opc, string OpcodeStr, X86VectorVTInfo _, + X86MemOperand memop, PatFrag GatherNode, + RegisterClass MaskRC = _.KRCWM> { + let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb", + ExeDomain = _.ExeDomain in + def rm : AVX5128I, EVEX, EVEX_K, + EVEX_CD8<_.EltSize, CD8VT1>, Sched<[WriteLoad]>; +} + +multiclass avx512_gather_q_pd dopc, bits<8> qopc, + AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { + defm NAME##D##SUFF##Z: avx512_gather, EVEX_V512, VEX_W; + defm NAME##Q##SUFF##Z: avx512_gather, EVEX_V512, VEX_W; +let Predicates = [HasVLX] in { + defm NAME##D##SUFF##Z256: avx512_gather, EVEX_V256, VEX_W; + defm NAME##Q##SUFF##Z256: avx512_gather, EVEX_V256, VEX_W; + defm NAME##D##SUFF##Z128: avx512_gather, EVEX_V128, VEX_W; + defm NAME##Q##SUFF##Z128: avx512_gather, EVEX_V128, VEX_W; +} +} + +multiclass avx512_gather_d_ps dopc, bits<8> qopc, + AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { + defm NAME##D##SUFF##Z: avx512_gather, EVEX_V512; + defm NAME##Q##SUFF##Z: avx512_gather, EVEX_V512; +let Predicates = [HasVLX] in { + defm NAME##D##SUFF##Z256: avx512_gather, EVEX_V256; + defm NAME##Q##SUFF##Z256: avx512_gather, EVEX_V256; + defm NAME##D##SUFF##Z128: avx512_gather, EVEX_V128; + defm NAME##Q##SUFF##Z128: avx512_gather, + EVEX_V128; +} +} + + +defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">, + avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">; + +defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">, + avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">; + +multiclass avx512_scatter opc, string OpcodeStr, X86VectorVTInfo _, + X86MemOperand memop, PatFrag ScatterNode, + RegisterClass MaskRC = _.KRCWM> { + +let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in + + def mr : AVX5128I, + EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[WriteStore]>; +} + +multiclass avx512_scatter_q_pd dopc, bits<8> qopc, + AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { + defm NAME##D##SUFF##Z: avx512_scatter, EVEX_V512, VEX_W; + defm NAME##Q##SUFF##Z: avx512_scatter, EVEX_V512, VEX_W; +let Predicates = [HasVLX] in { + defm NAME##D##SUFF##Z256: avx512_scatter, EVEX_V256, VEX_W; + defm NAME##Q##SUFF##Z256: avx512_scatter, EVEX_V256, VEX_W; + defm NAME##D##SUFF##Z128: avx512_scatter, EVEX_V128, VEX_W; + defm NAME##Q##SUFF##Z128: avx512_scatter, EVEX_V128, VEX_W; +} +} + +multiclass avx512_scatter_d_ps dopc, bits<8> qopc, + AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { + defm NAME##D##SUFF##Z: avx512_scatter, EVEX_V512; + defm NAME##Q##SUFF##Z: avx512_scatter, EVEX_V512; +let Predicates = [HasVLX] in { + defm NAME##D##SUFF##Z256: avx512_scatter, EVEX_V256; + defm NAME##Q##SUFF##Z256: avx512_scatter, EVEX_V256; + defm NAME##D##SUFF##Z128: avx512_scatter, EVEX_V128; + defm NAME##Q##SUFF##Z128: avx512_scatter, + EVEX_V128; +} +} + +defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">, + avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">; + +defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">, + avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">; + +// prefetch +multiclass avx512_gather_scatter_prefetch opc, Format F, string OpcodeStr, + RegisterClass KRC, X86MemOperand memop> { + let Predicates = [HasPFI], mayLoad = 1, mayStore = 1 in + def m : AVX5128I, + EVEX, EVEX_K, Sched<[WriteLoad]>; +} + +defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps", + VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; + +defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps", + VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; + +defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd", + VK8WM, vy512xmem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; + +defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd", + VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; + +defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps", + VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; + +defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps", + VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; + +defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd", + VK8WM, vy512xmem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; + +defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd", + VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; + +defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps", + VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; + +defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps", + VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; + +defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd", + VK8WM, vy512xmem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; + +defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd", + VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; + +defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps", + VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; + +defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps", + VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; + +defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd", + VK8WM, vy512xmem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; + +defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd", + VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; + +multiclass cvt_by_vec_width opc, X86VectorVTInfo Vec, string OpcodeStr > { +def rr : AVX512XS8I, + EVEX, Sched<[WriteMove]>; // TODO - WriteVecTrunc? +} + +multiclass cvt_mask_by_elt_width opc, AVX512VLVectorVTInfo VTInfo, + string OpcodeStr, Predicate prd> { +let Predicates = [prd] in + defm Z : cvt_by_vec_width, EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : cvt_by_vec_width, EVEX_V256; + defm Z128 : cvt_by_vec_width, EVEX_V128; + } +} + +defm VPMOVM2B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, "vpmovm2" , HasBWI>; +defm VPMOVM2W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, "vpmovm2", HasBWI> , VEX_W; +defm VPMOVM2D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, "vpmovm2", HasDQI>; +defm VPMOVM2Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, "vpmovm2", HasDQI> , VEX_W; + +multiclass convert_vector_to_mask_common opc, X86VectorVTInfo _, string OpcodeStr > { + def rr : AVX512XS8I, + EVEX, Sched<[WriteMove]>; +} + +// Use 512bit version to implement 128/256 bit in case NoVLX. +multiclass convert_vector_to_mask_lowering { + + def : Pat<(_.KVT (X86pcmpgtm _.ImmAllZerosV, (_.VT _.RC:$src))), + (_.KVT (COPY_TO_REGCLASS + (!cast(Name#"Zrr") + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src, _.SubRegIdx)), + _.KRC))>; +} + +multiclass avx512_convert_vector_to_mask opc, string OpcodeStr, + AVX512VLVectorVTInfo VTInfo, Predicate prd> { + let Predicates = [prd] in + defm Z : convert_vector_to_mask_common , + EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : convert_vector_to_mask_common, + EVEX_V256; + defm Z128 : convert_vector_to_mask_common, + EVEX_V128; + } + let Predicates = [prd, NoVLX] in { + defm Z256_Alt : convert_vector_to_mask_lowering; + defm Z128_Alt : convert_vector_to_mask_lowering; + } +} + +defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m", + avx512vl_i8_info, HasBWI>; +defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m", + avx512vl_i16_info, HasBWI>, VEX_W; +defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m", + avx512vl_i32_info, HasDQI>; +defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m", + avx512vl_i64_info, HasDQI>, VEX_W; + +// Patterns for handling sext from a mask register to v16i8/v16i16 when DQI +// is available, but BWI is not. We can't handle this in lowering because +// a target independent DAG combine likes to combine sext and trunc. +let Predicates = [HasDQI, NoBWI] in { + def : Pat<(v16i8 (sext (v16i1 VK16:$src))), + (VPMOVDBZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>; + def : Pat<(v16i16 (sext (v16i1 VK16:$src))), + (VPMOVDWZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 - COMPRESS and EXPAND +// + +multiclass compress_by_vec_width_common opc, X86VectorVTInfo _, + string OpcodeStr, X86FoldableSchedWrite sched> { + defm rr : AVX512_maskable, AVX5128IBase, + Sched<[sched]>; + + let mayStore = 1, hasSideEffects = 0 in + def mr : AVX5128I, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[sched.Folded]>; + + def mrk : AVX5128I, + EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[sched.Folded]>; +} + +multiclass compress_by_vec_width_lowering { + def : Pat<(X86mCompressingStore addr:$dst, _.KRCWM:$mask, + (_.VT _.RC:$src)), + (!cast(Name#_.ZSuffix##mrk) + addr:$dst, _.KRCWM:$mask, _.RC:$src)>; +} + +multiclass compress_by_elt_width opc, string OpcodeStr, + X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTInfo, + Predicate Pred = HasAVX512> { + let Predicates = [Pred] in + defm Z : compress_by_vec_width_common, + compress_by_vec_width_lowering, EVEX_V512; + + let Predicates = [Pred, HasVLX] in { + defm Z256 : compress_by_vec_width_common, + compress_by_vec_width_lowering, EVEX_V256; + defm Z128 : compress_by_vec_width_common, + compress_by_vec_width_lowering, EVEX_V128; + } +} + +// FIXME: Is there a better scheduler class for VPCOMPRESS? +defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", WriteVarShuffle256, + avx512vl_i32_info>, EVEX, NotMemoryFoldable; +defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", WriteVarShuffle256, + avx512vl_i64_info>, EVEX, VEX_W, NotMemoryFoldable; +defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", WriteVarShuffle256, + avx512vl_f32_info>, EVEX, NotMemoryFoldable; +defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", WriteVarShuffle256, + avx512vl_f64_info>, EVEX, VEX_W, NotMemoryFoldable; + +// expand +multiclass expand_by_vec_width opc, X86VectorVTInfo _, + string OpcodeStr, X86FoldableSchedWrite sched> { + defm rr : AVX512_maskable, AVX5128IBase, + Sched<[sched]>; + + defm rm : AVX512_maskable, + AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass expand_by_vec_width_lowering { + + def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, undef)), + (!cast(Name#_.ZSuffix##rmkz) + _.KRCWM:$mask, addr:$src)>; + + def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, _.ImmAllZerosV)), + (!cast(Name#_.ZSuffix##rmkz) + _.KRCWM:$mask, addr:$src)>; + + def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, + (_.VT _.RC:$src0))), + (!cast(Name#_.ZSuffix##rmk) + _.RC:$src0, _.KRCWM:$mask, addr:$src)>; +} + +multiclass expand_by_elt_width opc, string OpcodeStr, + X86FoldableSchedWrite sched, + AVX512VLVectorVTInfo VTInfo, + Predicate Pred = HasAVX512> { + let Predicates = [Pred] in + defm Z : expand_by_vec_width, + expand_by_vec_width_lowering, EVEX_V512; + + let Predicates = [Pred, HasVLX] in { + defm Z256 : expand_by_vec_width, + expand_by_vec_width_lowering, EVEX_V256; + defm Z128 : expand_by_vec_width, + expand_by_vec_width_lowering, EVEX_V128; + } +} + +// FIXME: Is there a better scheduler class for VPEXPAND? +defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", WriteVarShuffle256, + avx512vl_i32_info>, EVEX; +defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", WriteVarShuffle256, + avx512vl_i64_info>, EVEX, VEX_W; +defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", WriteVarShuffle256, + avx512vl_f32_info>, EVEX; +defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", WriteVarShuffle256, + avx512vl_f64_info>, EVEX, VEX_W; + +//handle instruction reg_vec1 = op(reg_vec,imm) +// op(mem_vec,imm) +// op(broadcast(eltVt),imm) +//all instruction created with FROUND_CURRENT +multiclass avx512_unary_fp_packed_imm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable, Sched<[sched]>; + defm rmi : AVX512_maskable, + Sched<[sched.Folded, ReadAfterLd]>; + defm rmbi : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae} +multiclass avx512_unary_fp_sae_packed_imm opc, string OpcodeStr, + SDNode OpNode, X86FoldableSchedWrite sched, + X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm rrib : AVX512_maskable, + EVEX_B, Sched<[sched]>; +} + +multiclass avx512_common_unary_fp_sae_packed_imm opc, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, Predicate prd>{ + let Predicates = [prd] in { + defm Z : avx512_unary_fp_packed_imm, + avx512_unary_fp_sae_packed_imm, EVEX_V512; + } + let Predicates = [prd, HasVLX] in { + defm Z128 : avx512_unary_fp_packed_imm, EVEX_V128; + defm Z256 : avx512_unary_fp_packed_imm, EVEX_V256; + } +} + +//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm) +// op(reg_vec2,mem_vec,imm) +// op(reg_vec2,broadcast(eltVt),imm) +//all instruction created with FROUND_CURRENT +multiclass avx512_fp_packed_imm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _>{ + let ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable, + Sched<[sched]>; + defm rmi : AVX512_maskable, + Sched<[sched.Folded, ReadAfterLd]>; + defm rmbi : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm) +// op(reg_vec2,mem_vec,imm) +multiclass avx512_3Op_rm_imm8 opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo DestInfo, + X86VectorVTInfo SrcInfo>{ + let ExeDomain = DestInfo.ExeDomain in { + defm rri : AVX512_maskable, + Sched<[sched]>; + defm rmi : AVX512_maskable, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm) +// op(reg_vec2,mem_vec,imm) +// op(reg_vec2,broadcast(eltVt),imm) +multiclass avx512_3Op_imm8 opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _>: + avx512_3Op_rm_imm8{ + + let ExeDomain = _.ExeDomain in + defm rmbi : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +//handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm) +// op(reg_vec2,mem_scalar,imm) +multiclass avx512_fp_scalar_imm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable_scalar, + Sched<[sched]>; + defm rmi : AVX512_maskable_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae} +multiclass avx512_fp_sae_packed_imm opc, string OpcodeStr, + SDNode OpNode, X86FoldableSchedWrite sched, + X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm rrib : AVX512_maskable, + EVEX_B, Sched<[sched]>; +} + +//handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae} +multiclass avx512_fp_sae_scalar_imm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in + defm NAME#rrib : AVX512_maskable_scalar, + EVEX_B, Sched<[sched]>; +} + +multiclass avx512_common_fp_sae_packed_imm opc, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, Predicate prd>{ + let Predicates = [prd] in { + defm Z : avx512_fp_packed_imm, + avx512_fp_sae_packed_imm, + EVEX_V512; + + } + let Predicates = [prd, HasVLX] in { + defm Z128 : avx512_fp_packed_imm, + EVEX_V128; + defm Z256 : avx512_fp_packed_imm, + EVEX_V256; + } +} + +multiclass avx512_common_3Op_rm_imm8 opc, SDNode OpNode, string OpStr, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo DestInfo, + AVX512VLVectorVTInfo SrcInfo, Predicate Pred = HasBWI> { + let Predicates = [Pred] in { + defm Z : avx512_3Op_rm_imm8, EVEX_V512, AVX512AIi8Base, EVEX_4V; + } + let Predicates = [Pred, HasVLX] in { + defm Z128 : avx512_3Op_rm_imm8, EVEX_V128, AVX512AIi8Base, EVEX_4V; + defm Z256 : avx512_3Op_rm_imm8, EVEX_V256, AVX512AIi8Base, EVEX_4V; + } +} + +multiclass avx512_common_3Op_imm8 opc, SDNode OpNode, X86SchedWriteWidths sched, + Predicate Pred = HasAVX512> { + let Predicates = [Pred] in { + defm Z : avx512_3Op_imm8, + EVEX_V512; + } + let Predicates = [Pred, HasVLX] in { + defm Z128 : avx512_3Op_imm8, + EVEX_V128; + defm Z256 : avx512_3Op_imm8, + EVEX_V256; + } +} + +multiclass avx512_common_fp_sae_scalar_imm opc, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, Predicate prd> { + let Predicates = [prd] in { + defm Z : avx512_fp_scalar_imm, + avx512_fp_sae_scalar_imm; + } +} + +multiclass avx512_common_unary_fp_sae_packed_imm_all opcPs, bits<8> opcPd, SDNode OpNode, + SDNode OpNodeRnd, X86SchedWriteWidths sched, Predicate prd>{ + defm PS : avx512_common_unary_fp_sae_packed_imm, + EVEX_CD8<32, CD8VF>; + defm PD : avx512_common_unary_fp_sae_packed_imm, + EVEX_CD8<64, CD8VF>, VEX_W; +} + +defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56, + X86VReduce, X86VReduceRnd, SchedWriteFRnd, HasDQI>, + AVX512AIi8Base, EVEX; +defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09, + X86VRndScale, X86VRndScaleRnd, SchedWriteFRnd, HasAVX512>, + AVX512AIi8Base, EVEX; +defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26, + X86VGetMant, X86VGetMantRnd, SchedWriteFRnd, HasAVX512>, + AVX512AIi8Base, EVEX; + +defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info, + 0x50, X86VRange, X86VRangeRnd, + SchedWriteFAdd, HasDQI>, + AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; +defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info, + 0x50, X86VRange, X86VRangeRnd, + SchedWriteFAdd, HasDQI>, + AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; + +defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", + f64x_info, 0x51, X86Ranges, X86RangesRnd, SchedWriteFAdd, HasDQI>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; +defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info, + 0x51, X86Ranges, X86RangesRnd, SchedWriteFAdd, HasDQI>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; + +defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info, + 0x57, X86Reduces, X86ReducesRnd, SchedWriteFRnd, HasDQI>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; +defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info, + 0x57, X86Reduces, X86ReducesRnd, SchedWriteFRnd, HasDQI>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; + +defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info, + 0x27, X86GetMants, X86GetMantsRnd, SchedWriteFRnd, HasAVX512>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; +defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info, + 0x27, X86GetMants, X86GetMantsRnd, SchedWriteFRnd, HasAVX512>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; + + +multiclass AVX512_rndscale_lowering { + // Register + def : Pat<(_.VT (ffloor _.RC:$src)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rri") + _.RC:$src, (i32 0x9))>; + def : Pat<(_.VT (fnearbyint _.RC:$src)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rri") + _.RC:$src, (i32 0xC))>; + def : Pat<(_.VT (fceil _.RC:$src)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rri") + _.RC:$src, (i32 0xA))>; + def : Pat<(_.VT (frint _.RC:$src)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rri") + _.RC:$src, (i32 0x4))>; + def : Pat<(_.VT (ftrunc _.RC:$src)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rri") + _.RC:$src, (i32 0xB))>; + + // Merge-masking + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ffloor _.RC:$src), _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrik") + _.RC:$dst, _.KRCWM:$mask, _.RC:$src, (i32 0x9))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fnearbyint _.RC:$src), _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrik") + _.RC:$dst, _.KRCWM:$mask, _.RC:$src, (i32 0xC))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fceil _.RC:$src), _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrik") + _.RC:$dst, _.KRCWM:$mask, _.RC:$src, (i32 0xA))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (frint _.RC:$src), _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrik") + _.RC:$dst, _.KRCWM:$mask, _.RC:$src, (i32 0x4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ftrunc _.RC:$src), _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrik") + _.RC:$dst, _.KRCWM:$mask, _.RC:$src, (i32 0xB))>; + + // Zero-masking + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ffloor _.RC:$src), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrikz") + _.KRCWM:$mask, _.RC:$src, (i32 0x9))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fnearbyint _.RC:$src), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrikz") + _.KRCWM:$mask, _.RC:$src, (i32 0xC))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fceil _.RC:$src), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrikz") + _.KRCWM:$mask, _.RC:$src, (i32 0xA))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (frint _.RC:$src), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrikz") + _.KRCWM:$mask, _.RC:$src, (i32 0x4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ftrunc _.RC:$src), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rrikz") + _.KRCWM:$mask, _.RC:$src, (i32 0xB))>; + + // Load + def : Pat<(_.VT (ffloor (_.LdFrag addr:$src))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmi") + addr:$src, (i32 0x9))>; + def : Pat<(_.VT (fnearbyint (_.LdFrag addr:$src))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmi") + addr:$src, (i32 0xC))>; + def : Pat<(_.VT (fceil (_.LdFrag addr:$src))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmi") + addr:$src, (i32 0xA))>; + def : Pat<(_.VT (frint (_.LdFrag addr:$src))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmi") + addr:$src, (i32 0x4))>; + def : Pat<(_.VT (ftrunc (_.LdFrag addr:$src))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmi") + addr:$src, (i32 0xB))>; + + // Merge-masking + load + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ffloor (_.LdFrag addr:$src)), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0x9))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fnearbyint (_.LdFrag addr:$src)), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0xC))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fceil (_.LdFrag addr:$src)), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0xA))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (frint (_.LdFrag addr:$src)), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0x4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ftrunc (_.LdFrag addr:$src)), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0xB))>; + + // Zero-masking + load + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ffloor (_.LdFrag addr:$src)), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmikz") + _.KRCWM:$mask, addr:$src, (i32 0x9))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fnearbyint (_.LdFrag addr:$src)), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmikz") + _.KRCWM:$mask, addr:$src, (i32 0xC))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (fceil (_.LdFrag addr:$src)), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmikz") + _.KRCWM:$mask, addr:$src, (i32 0xA))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (frint (_.LdFrag addr:$src)), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmikz") + _.KRCWM:$mask, addr:$src, (i32 0x4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, (ftrunc (_.LdFrag addr:$src)), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmikz") + _.KRCWM:$mask, addr:$src, (i32 0xB))>; + + // Broadcast load + def : Pat<(_.VT (ffloor (X86VBroadcast (_.ScalarLdFrag addr:$src)))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbi") + addr:$src, (i32 0x9))>; + def : Pat<(_.VT (fnearbyint (X86VBroadcast (_.ScalarLdFrag addr:$src)))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbi") + addr:$src, (i32 0xC))>; + def : Pat<(_.VT (fceil (X86VBroadcast (_.ScalarLdFrag addr:$src)))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbi") + addr:$src, (i32 0xA))>; + def : Pat<(_.VT (frint (X86VBroadcast (_.ScalarLdFrag addr:$src)))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbi") + addr:$src, (i32 0x4))>; + def : Pat<(_.VT (ftrunc (X86VBroadcast (_.ScalarLdFrag addr:$src)))), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbi") + addr:$src, (i32 0xB))>; + + // Merge-masking + broadcast load + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (ffloor (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0x9))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (fnearbyint (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0xC))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (fceil (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0xA))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (frint (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0x4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (ftrunc (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.RC:$dst)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbik") + _.RC:$dst, _.KRCWM:$mask, addr:$src, (i32 0xB))>; + + // Zero-masking + broadcast load + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (ffloor (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbikz") + _.KRCWM:$mask, addr:$src, (i32 0x9))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (fnearbyint (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbikz") + _.KRCWM:$mask, addr:$src, (i32 0xC))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (fceil (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbikz") + _.KRCWM:$mask, addr:$src, (i32 0xA))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (frint (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbikz") + _.KRCWM:$mask, addr:$src, (i32 0x4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (ftrunc (X86VBroadcast (_.ScalarLdFrag addr:$src))), + _.ImmAllZerosV)), + (!cast("VRNDSCALE"#Suffix#_.ZSuffix#"rmbikz") + _.KRCWM:$mask, addr:$src, (i32 0xB))>; +} + +let Predicates = [HasAVX512] in { + defm : AVX512_rndscale_lowering; + defm : AVX512_rndscale_lowering; +} + +let Predicates = [HasVLX] in { + defm : AVX512_rndscale_lowering; + defm : AVX512_rndscale_lowering; + defm : AVX512_rndscale_lowering; + defm : AVX512_rndscale_lowering; +} + +multiclass avx512_shuff_packed_128_common opc, string OpcodeStr, + X86FoldableSchedWrite sched, + X86VectorVTInfo _, + X86VectorVTInfo CastInfo, + string EVEX2VEXOvrd> { + let ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable, + Sched<[sched]>, EVEX2VEXOverride; + defm rmi : AVX512_maskable, + Sched<[sched.Folded, ReadAfterLd]>, + EVEX2VEXOverride; + defm rmbi : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_shuff_packed_128 opc, + string EVEX2VEXOvrd>{ + let Predicates = [HasAVX512] in + defm Z : avx512_shuff_packed_128_common, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in + defm Z256 : avx512_shuff_packed_128_common, EVEX_V256; +} + +defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4", WriteFShuffle256, + avx512vl_f32_info, avx512vl_f64_info, 0x23, "VPERM2F128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; +defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2", WriteFShuffle256, + avx512vl_f64_info, avx512vl_f64_info, 0x23, "VPERM2F128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; +defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4", WriteFShuffle256, + avx512vl_i32_info, avx512vl_i64_info, 0x43, "VPERM2I128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; +defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2", WriteFShuffle256, + avx512vl_i64_info, avx512vl_i64_info, 0x43, "VPERM2I128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; + +let Predicates = [HasAVX512] in { +// Provide fallback in case the load node that is used in the broadcast +// patterns above is used by additional users, which prevents the pattern +// selection. +def : Pat<(v8f64 (X86SubVBroadcast (v2f64 VR128X:$src))), + (VSHUFF64X2Zrri (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + 0)>; +def : Pat<(v8i64 (X86SubVBroadcast (v2i64 VR128X:$src))), + (VSHUFI64X2Zrri (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + 0)>; + +def : Pat<(v16f32 (X86SubVBroadcast (v4f32 VR128X:$src))), + (VSHUFF32X4Zrri (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + 0)>; +def : Pat<(v16i32 (X86SubVBroadcast (v4i32 VR128X:$src))), + (VSHUFI32X4Zrri (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + 0)>; + +def : Pat<(v32i16 (X86SubVBroadcast (v8i16 VR128X:$src))), + (VSHUFI32X4Zrri (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + 0)>; + +def : Pat<(v64i8 (X86SubVBroadcast (v16i8 VR128X:$src))), + (VSHUFI32X4Zrri (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + 0)>; +} + +multiclass avx512_valign opc, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _>{ + // NOTE: EVEX2VEXOverride changed back to Unset for 256-bit at the + // instantiation of this class. + let ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable, + Sched<[sched]>, EVEX2VEXOverride<"VPALIGNRrri">; + defm rmi : AVX512_maskable, + Sched<[sched.Folded, ReadAfterLd]>, + EVEX2VEXOverride<"VPALIGNRrmi">; + + defm rmbi : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_valign_common { + let Predicates = [HasAVX512] in { + defm Z : avx512_valign<0x03, OpcodeStr, sched.ZMM, _.info512>, + AVX512AIi8Base, EVEX_4V, EVEX_V512; + } + let Predicates = [HasAVX512, HasVLX] in { + defm Z128 : avx512_valign<0x03, OpcodeStr, sched.XMM, _.info128>, + AVX512AIi8Base, EVEX_4V, EVEX_V128; + // We can't really override the 256-bit version so change it back to unset. + let EVEX2VEXOverride = ? in + defm Z256 : avx512_valign<0x03, OpcodeStr, sched.YMM, _.info256>, + AVX512AIi8Base, EVEX_4V, EVEX_V256; + } +} + +defm VALIGND: avx512_valign_common<"valignd", SchedWriteShuffle, + avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; +defm VALIGNQ: avx512_valign_common<"valignq", SchedWriteShuffle, + avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, + VEX_W; + +defm VPALIGNR: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr", + SchedWriteShuffle, avx512vl_i8_info, + avx512vl_i8_info>, EVEX_CD8<8, CD8VF>; + +// Fragments to help convert valignq into masked valignd. Or valignq/valignd +// into vpalignr. +def ValignqImm32XForm : SDNodeXFormgetZExtValue() * 2, SDLoc(N)); +}]>; +def ValignqImm8XForm : SDNodeXFormgetZExtValue() * 8, SDLoc(N)); +}]>; +def ValigndImm8XForm : SDNodeXFormgetZExtValue() * 4, SDLoc(N)); +}]>; + +multiclass avx512_vpalign_mask_lowering { + def : Pat<(To.VT (vselect To.KRCWM:$mask, + (bitconvert + (From.VT (OpNode From.RC:$src1, From.RC:$src2, + imm:$src3))), + To.RC:$src0)), + (!cast(OpcodeStr#"rrik") To.RC:$src0, To.KRCWM:$mask, + To.RC:$src1, To.RC:$src2, + (ImmXForm imm:$src3))>; + + def : Pat<(To.VT (vselect To.KRCWM:$mask, + (bitconvert + (From.VT (OpNode From.RC:$src1, From.RC:$src2, + imm:$src3))), + To.ImmAllZerosV)), + (!cast(OpcodeStr#"rrikz") To.KRCWM:$mask, + To.RC:$src1, To.RC:$src2, + (ImmXForm imm:$src3))>; + + def : Pat<(To.VT (vselect To.KRCWM:$mask, + (bitconvert + (From.VT (OpNode From.RC:$src1, + (bitconvert (To.LdFrag addr:$src2)), + imm:$src3))), + To.RC:$src0)), + (!cast(OpcodeStr#"rmik") To.RC:$src0, To.KRCWM:$mask, + To.RC:$src1, addr:$src2, + (ImmXForm imm:$src3))>; + + def : Pat<(To.VT (vselect To.KRCWM:$mask, + (bitconvert + (From.VT (OpNode From.RC:$src1, + (bitconvert (To.LdFrag addr:$src2)), + imm:$src3))), + To.ImmAllZerosV)), + (!cast(OpcodeStr#"rmikz") To.KRCWM:$mask, + To.RC:$src1, addr:$src2, + (ImmXForm imm:$src3))>; +} + +multiclass avx512_vpalign_mask_lowering_mb : + avx512_vpalign_mask_lowering { + def : Pat<(From.VT (OpNode From.RC:$src1, + (bitconvert (To.VT (X86VBroadcast + (To.ScalarLdFrag addr:$src2)))), + imm:$src3)), + (!cast(OpcodeStr#"rmbi") To.RC:$src1, addr:$src2, + (ImmXForm imm:$src3))>; + + def : Pat<(To.VT (vselect To.KRCWM:$mask, + (bitconvert + (From.VT (OpNode From.RC:$src1, + (bitconvert + (To.VT (X86VBroadcast + (To.ScalarLdFrag addr:$src2)))), + imm:$src3))), + To.RC:$src0)), + (!cast(OpcodeStr#"rmbik") To.RC:$src0, To.KRCWM:$mask, + To.RC:$src1, addr:$src2, + (ImmXForm imm:$src3))>; + + def : Pat<(To.VT (vselect To.KRCWM:$mask, + (bitconvert + (From.VT (OpNode From.RC:$src1, + (bitconvert + (To.VT (X86VBroadcast + (To.ScalarLdFrag addr:$src2)))), + imm:$src3))), + To.ImmAllZerosV)), + (!cast(OpcodeStr#"rmbikz") To.KRCWM:$mask, + To.RC:$src1, addr:$src2, + (ImmXForm imm:$src3))>; +} + +let Predicates = [HasAVX512] in { + // For 512-bit we lower to the widest element type we can. So we only need + // to handle converting valignq to valignd. + defm : avx512_vpalign_mask_lowering_mb<"VALIGNDZ", X86VAlign, v8i64_info, + v16i32_info, ValignqImm32XForm>; +} + +let Predicates = [HasVLX] in { + // For 128-bit we lower to the widest element type we can. So we only need + // to handle converting valignq to valignd. + defm : avx512_vpalign_mask_lowering_mb<"VALIGNDZ128", X86VAlign, v2i64x_info, + v4i32x_info, ValignqImm32XForm>; + // For 256-bit we lower to the widest element type we can. So we only need + // to handle converting valignq to valignd. + defm : avx512_vpalign_mask_lowering_mb<"VALIGNDZ256", X86VAlign, v4i64x_info, + v8i32x_info, ValignqImm32XForm>; +} + +let Predicates = [HasVLX, HasBWI] in { + // We can turn 128 and 256 bit VALIGND/VALIGNQ into VPALIGNR. + defm : avx512_vpalign_mask_lowering<"VPALIGNRZ128", X86VAlign, v2i64x_info, + v16i8x_info, ValignqImm8XForm>; + defm : avx512_vpalign_mask_lowering<"VPALIGNRZ128", X86VAlign, v4i32x_info, + v16i8x_info, ValigndImm8XForm>; +} + +defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw", + SchedWritePSADBW, avx512vl_i16_info, avx512vl_i8_info>, + EVEX_CD8<8, CD8VF>, NotEVEX2VEXConvertible; + +multiclass avx512_unary_rm opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rr : AVX512_maskable, EVEX, AVX5128IBase, + Sched<[sched]>; + + defm rm : AVX512_maskable, + EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded]>; + } +} + +multiclass avx512_unary_rmb opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> : + avx512_unary_rm { + defm rmb : AVX512_maskable, + EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded]>; +} + +multiclass avx512_unary_rm_vl opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, + AVX512VLVectorVTInfo VTInfo, Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_unary_rm, + EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_unary_rm, + EVEX_V256; + defm Z128 : avx512_unary_rm, + EVEX_V128; + } +} + +multiclass avx512_unary_rmb_vl opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo VTInfo, + Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_unary_rmb, + EVEX_V512; + + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_unary_rmb, + EVEX_V256; + defm Z128 : avx512_unary_rmb, + EVEX_V128; + } +} + +multiclass avx512_unary_rm_vl_dq opc_d, bits<8> opc_q, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched, + Predicate prd> { + defm Q : avx512_unary_rmb_vl, VEX_W; + defm D : avx512_unary_rmb_vl; +} + +multiclass avx512_unary_rm_vl_bw opc_b, bits<8> opc_w, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched, + Predicate prd> { + defm W : avx512_unary_rm_vl, VEX_WIG; + defm B : avx512_unary_rm_vl, VEX_WIG; +} + +multiclass avx512_unary_rm_vl_all opc_b, bits<8> opc_w, + bits<8> opc_d, bits<8> opc_q, + string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + defm NAME : avx512_unary_rm_vl_dq, + avx512_unary_rm_vl_bw; +} + +defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", abs, + SchedWriteVecALU>; + +// VPABS: Use 512bit version to implement 128/256 bit in case NoVLX. +let Predicates = [HasAVX512, NoVLX] in { + def : Pat<(v4i64 (abs VR256X:$src)), + (EXTRACT_SUBREG + (VPABSQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)), + sub_ymm)>; + def : Pat<(v2i64 (abs VR128X:$src)), + (EXTRACT_SUBREG + (VPABSQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)), + sub_xmm)>; +} + +// Use 512bit version to implement 128/256 bit. +multiclass avx512_unary_lowering { + let Predicates = [prd, NoVLX] in { + def : Pat<(_.info256.VT(OpNode _.info256.RC:$src1)), + (EXTRACT_SUBREG + (!cast(InstrStr # "Zrr") + (INSERT_SUBREG(_.info512.VT(IMPLICIT_DEF)), + _.info256.RC:$src1, + _.info256.SubRegIdx)), + _.info256.SubRegIdx)>; + + def : Pat<(_.info128.VT(OpNode _.info128.RC:$src1)), + (EXTRACT_SUBREG + (!cast(InstrStr # "Zrr") + (INSERT_SUBREG(_.info512.VT(IMPLICIT_DEF)), + _.info128.RC:$src1, + _.info128.SubRegIdx)), + _.info128.SubRegIdx)>; + } +} + +defm VPLZCNT : avx512_unary_rm_vl_dq<0x44, 0x44, "vplzcnt", ctlz, + SchedWriteVecIMul, HasCDI>; + +// FIXME: Is there a better scheduler class for VPCONFLICT? +defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, + SchedWriteVecALU, HasCDI>; + +// VPLZCNT: Use 512bit version to implement 128/256 bit in case NoVLX. +defm : avx512_unary_lowering<"VPLZCNTQ", ctlz, avx512vl_i64_info, HasCDI>; +defm : avx512_unary_lowering<"VPLZCNTD", ctlz, avx512vl_i32_info, HasCDI>; + +//===---------------------------------------------------------------------===// +// Counts number of ones - VPOPCNTD and VPOPCNTQ +//===---------------------------------------------------------------------===// + +// FIXME: Is there a better scheduler class for VPOPCNTD/VPOPCNTQ? +defm VPOPCNT : avx512_unary_rm_vl_dq<0x55, 0x55, "vpopcnt", ctpop, + SchedWriteVecALU, HasVPOPCNTDQ>; + +defm : avx512_unary_lowering<"VPOPCNTQ", ctpop, avx512vl_i64_info, HasVPOPCNTDQ>; +defm : avx512_unary_lowering<"VPOPCNTD", ctpop, avx512vl_i32_info, HasVPOPCNTDQ>; + +//===---------------------------------------------------------------------===// +// Replicate Single FP - MOVSHDUP and MOVSLDUP +//===---------------------------------------------------------------------===// + +multiclass avx512_replicate opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + defm NAME: avx512_unary_rm_vl, XS; +} + +defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup, + SchedWriteFShuffle>; +defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup, + SchedWriteFShuffle>; + +//===----------------------------------------------------------------------===// +// AVX-512 - MOVDDUP +//===----------------------------------------------------------------------===// + +multiclass avx512_movddup_128 opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain in { + defm rr : AVX512_maskable, EVEX, + Sched<[sched]>; + defm rm : AVX512_maskable, + EVEX, EVEX_CD8<_.EltSize, CD8VH>, + Sched<[sched.Folded]>; + } +} + +multiclass avx512_movddup_common opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo VTInfo> { + defm Z : avx512_unary_rm, EVEX_V512; + + let Predicates = [HasAVX512, HasVLX] in { + defm Z256 : avx512_unary_rm, EVEX_V256; + defm Z128 : avx512_movddup_128, EVEX_V128; + } +} + +multiclass avx512_movddup opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched> { + defm NAME: avx512_movddup_common, XD, VEX_W; +} + +defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", X86Movddup, SchedWriteFShuffle>; + +let Predicates = [HasVLX] in { +def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))), + (VMOVDDUPZ128rm addr:$src)>; +def : Pat<(v2f64 (X86VBroadcast f64:$src)), + (VMOVDDUPZ128rr (v2f64 (COPY_TO_REGCLASS FR64X:$src, VR128X)))>; +def : Pat<(v2f64 (X86VBroadcast (loadv2f64 addr:$src))), + (VMOVDDUPZ128rm addr:$src)>; + +def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast f64:$src)), + (v2f64 VR128X:$src0)), + (VMOVDDUPZ128rrk VR128X:$src0, VK2WM:$mask, + (v2f64 (COPY_TO_REGCLASS FR64X:$src, VR128X)))>; +def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast f64:$src)), + (bitconvert (v4i32 immAllZerosV))), + (VMOVDDUPZ128rrkz VK2WM:$mask, (v2f64 (COPY_TO_REGCLASS FR64X:$src, VR128X)))>; + +def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadf64 addr:$src))), + (v2f64 VR128X:$src0)), + (VMOVDDUPZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>; +def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadf64 addr:$src))), + (bitconvert (v4i32 immAllZerosV))), + (VMOVDDUPZ128rmkz VK2WM:$mask, addr:$src)>; + +def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadv2f64 addr:$src))), + (v2f64 VR128X:$src0)), + (VMOVDDUPZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>; +def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadv2f64 addr:$src))), + (bitconvert (v4i32 immAllZerosV))), + (VMOVDDUPZ128rmkz VK2WM:$mask, addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 - Unpack Instructions +//===----------------------------------------------------------------------===// + +defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh, HasAVX512, + SchedWriteFShuffleSizes, 0, 1>; +defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl, HasAVX512, + SchedWriteFShuffleSizes>; + +defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl, + SchedWriteShuffle, HasBWI>; +defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh, + SchedWriteShuffle, HasBWI>; +defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl, + SchedWriteShuffle, HasBWI>; +defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh, + SchedWriteShuffle, HasBWI>; + +defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl, + SchedWriteShuffle, HasAVX512>; +defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh, + SchedWriteShuffle, HasAVX512>; +defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl, + SchedWriteShuffle, HasAVX512>; +defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh, + SchedWriteShuffle, HasAVX512>; + +//===----------------------------------------------------------------------===// +// AVX-512 - Extract & Insert Integer Instructions +//===----------------------------------------------------------------------===// + +multiclass avx512_extract_elt_bw_m opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _> { + def mr : AVX512Ii8, + EVEX, EVEX_CD8<_.EltSize, CD8VT1>, Sched<[WriteVecExtractSt]>; +} + +multiclass avx512_extract_elt_b { + let Predicates = [HasBWI] in { + def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst), + (ins _.RC:$src1, u8imm:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32orGR64:$dst, + (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>, + EVEX, TAPD, Sched<[WriteVecExtract]>; + + defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD; + } +} + +multiclass avx512_extract_elt_w { + let Predicates = [HasBWI] in { + def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst), + (ins _.RC:$src1, u8imm:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32orGR64:$dst, + (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>, + EVEX, PD, Sched<[WriteVecExtract]>; + + let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in + def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst), + (ins _.RC:$src1, u8imm:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + EVEX, TAPD, FoldGenData, + Sched<[WriteVecExtract]>; + + defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD; + } +} + +multiclass avx512_extract_elt_dq { + let Predicates = [HasDQI] in { + def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst), + (ins _.RC:$src1, u8imm:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GRC:$dst, + (extractelt (_.VT _.RC:$src1), imm:$src2))]>, + EVEX, TAPD, Sched<[WriteVecExtract]>; + + def mr : AVX512Ii8<0x16, MRMDestMem, (outs), + (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2), + OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(store (extractelt (_.VT _.RC:$src1), + imm:$src2),addr:$dst)]>, + EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD, + Sched<[WriteVecExtractSt]>; + } +} + +defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>, VEX_WIG; +defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>, VEX_WIG; +defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>; +defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W; + +multiclass avx512_insert_elt_m opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _, PatFrag LdFrag> { + def rm : AVX512Ii8, + EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>, Sched<[WriteVecInsertLd, ReadAfterLd]>; +} + +multiclass avx512_insert_elt_bw opc, string OpcodeStr, SDNode OpNode, + X86VectorVTInfo _, PatFrag LdFrag> { + let Predicates = [HasBWI] in { + def rr : AVX512Ii8, EVEX_4V, + Sched<[WriteVecInsert]>; + + defm NAME : avx512_insert_elt_m; + } +} + +multiclass avx512_insert_elt_dq opc, string OpcodeStr, + X86VectorVTInfo _, RegisterClass GRC> { + let Predicates = [HasDQI] in { + def rr : AVX512Ii8, + EVEX_4V, TAPD, Sched<[WriteVecInsert]>; + + defm NAME : avx512_insert_elt_m, TAPD; + } +} + +defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info, + extloadi8>, TAPD, VEX_WIG; +defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info, + extloadi16>, PD, VEX_WIG; +defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>; +defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W; + +//===----------------------------------------------------------------------===// +// VSHUFPS - VSHUFPD Operations +//===----------------------------------------------------------------------===// + +multiclass avx512_shufp{ + defm NAME: avx512_common_3Op_imm8, + EVEX_CD8, + AVX512AIi8Base, EVEX_4V; +} + +defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS; +defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W; + +//===----------------------------------------------------------------------===// +// AVX-512 - Byte shift Left/Right +//===----------------------------------------------------------------------===// + +// FIXME: The SSE/AVX names are PSLLDQri etc. - should we add the i here as well? +multiclass avx512_shift_packed opc, SDNode OpNode, Format MRMr, + Format MRMm, string OpcodeStr, + X86FoldableSchedWrite sched, X86VectorVTInfo _>{ + def rr : AVX512, + Sched<[sched]>; + def rm : AVX512, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_shift_packed_all opc, SDNode OpNode, Format MRMr, + Format MRMm, string OpcodeStr, + X86SchedWriteWidths sched, Predicate prd>{ + let Predicates = [prd] in + defm Z : avx512_shift_packed, EVEX_V512; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_shift_packed, EVEX_V256; + defm Z128 : avx512_shift_packed, EVEX_V128; + } +} +defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq", + SchedWriteShuffle, HasBWI>, + AVX512PDIi8Base, EVEX_4V, VEX_WIG; +defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq", + SchedWriteShuffle, HasBWI>, + AVX512PDIi8Base, EVEX_4V, VEX_WIG; + +multiclass avx512_psadbw_packed opc, SDNode OpNode, + string OpcodeStr, X86FoldableSchedWrite sched, + X86VectorVTInfo _dst, X86VectorVTInfo _src> { + def rr : AVX512BI, + Sched<[sched]>; + def rm : AVX512BI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass avx512_psadbw_packed_all opc, SDNode OpNode, + string OpcodeStr, X86SchedWriteWidths sched, + Predicate prd> { + let Predicates = [prd] in + defm Z : avx512_psadbw_packed, EVEX_V512; + let Predicates = [prd, HasVLX] in { + defm Z256 : avx512_psadbw_packed, EVEX_V256; + defm Z128 : avx512_psadbw_packed, EVEX_V128; + } +} + +defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw", + SchedWritePSADBW, HasBWI>, EVEX_4V, VEX_WIG; + +// Transforms to swizzle an immediate to enable better matching when +// memory operand isn't in the right place. +def VPTERNLOG321_imm8 : SDNodeXFormgetZExtValue(); + // Swap bits 1/4 and 3/6. + uint8_t NewImm = Imm & 0xa5; + if (Imm & 0x02) NewImm |= 0x10; + if (Imm & 0x10) NewImm |= 0x02; + if (Imm & 0x08) NewImm |= 0x40; + if (Imm & 0x40) NewImm |= 0x08; + return getI8Imm(NewImm, SDLoc(N)); +}]>; +def VPTERNLOG213_imm8 : SDNodeXFormgetZExtValue(); + // Swap bits 2/4 and 3/5. + uint8_t NewImm = Imm & 0xc3; + if (Imm & 0x04) NewImm |= 0x10; + if (Imm & 0x10) NewImm |= 0x04; + if (Imm & 0x08) NewImm |= 0x20; + if (Imm & 0x20) NewImm |= 0x08; + return getI8Imm(NewImm, SDLoc(N)); +}]>; +def VPTERNLOG132_imm8 : SDNodeXFormgetZExtValue(); + // Swap bits 1/2 and 5/6. + uint8_t NewImm = Imm & 0x99; + if (Imm & 0x02) NewImm |= 0x04; + if (Imm & 0x04) NewImm |= 0x02; + if (Imm & 0x20) NewImm |= 0x40; + if (Imm & 0x40) NewImm |= 0x20; + return getI8Imm(NewImm, SDLoc(N)); +}]>; +def VPTERNLOG231_imm8 : SDNodeXFormgetZExtValue(); + // Move bits 1->2, 2->4, 3->6, 4->1, 5->3, 6->5 + uint8_t NewImm = Imm & 0x81; + if (Imm & 0x02) NewImm |= 0x04; + if (Imm & 0x04) NewImm |= 0x10; + if (Imm & 0x08) NewImm |= 0x40; + if (Imm & 0x10) NewImm |= 0x02; + if (Imm & 0x20) NewImm |= 0x08; + if (Imm & 0x40) NewImm |= 0x20; + return getI8Imm(NewImm, SDLoc(N)); +}]>; +def VPTERNLOG312_imm8 : SDNodeXFormgetZExtValue(); + // Move bits 1->4, 2->1, 3->5, 4->2, 5->6, 6->3 + uint8_t NewImm = Imm & 0x81; + if (Imm & 0x02) NewImm |= 0x10; + if (Imm & 0x04) NewImm |= 0x02; + if (Imm & 0x08) NewImm |= 0x20; + if (Imm & 0x10) NewImm |= 0x04; + if (Imm & 0x20) NewImm |= 0x40; + if (Imm & 0x40) NewImm |= 0x08; + return getI8Imm(NewImm, SDLoc(N)); +}]>; + +multiclass avx512_ternlog opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + string Name>{ + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable_3src, + AVX512AIi8Base, EVEX_4V, Sched<[sched]>; + defm rmi : AVX512_maskable_3src, + AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + defm rmbi : AVX512_maskable_3src, EVEX_B, + AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[sched.Folded, ReadAfterLd]>; + }// Constraints = "$src1 = $dst" + + // Additional patterns for matching passthru operand in other positions. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src3, _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, _.RC:$src3, (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, _.RC:$src3, (VPTERNLOG213_imm8 imm:$src4))>; + + // Additional patterns for matching loads in other positions. + def : Pat<(_.VT (OpNode (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src2, _.RC:$src1, (i8 imm:$src4))), + (!cast(Name#_.ZSuffix#rmi) _.RC:$src1, _.RC:$src2, + addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (OpNode _.RC:$src1, + (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src2, (i8 imm:$src4))), + (!cast(Name#_.ZSuffix#rmi) _.RC:$src1, _.RC:$src2, + addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; + + // Additional patterns for matching zero masking with loads in other + // positions. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), + _.ImmAllZerosV)), + (!cast(Name#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src2, (i8 imm:$src4)), + _.ImmAllZerosV)), + (!cast(Name#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; + + // Additional patterns for matching masked loads with different + // operand orders. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src2, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src2, _.RC:$src1, + (bitconvert (_.LdFrag addr:$src3)), (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG213_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src2, (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src1, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG231_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode (bitconvert (_.LdFrag addr:$src3)), + _.RC:$src1, _.RC:$src2, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG312_imm8 imm:$src4))>; + + // Additional patterns for matching broadcasts in other positions. + def : Pat<(_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src2, _.RC:$src1, (i8 imm:$src4))), + (!cast(Name#_.ZSuffix#rmbi) _.RC:$src1, _.RC:$src2, + addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (OpNode _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src2, (i8 imm:$src4))), + (!cast(Name#_.ZSuffix#rmbi) _.RC:$src1, _.RC:$src2, + addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; + + // Additional patterns for matching zero masking with broadcasts in other + // positions. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), + _.ImmAllZerosV)), + (!cast(Name#_.ZSuffix#rmbikz) _.RC:$src1, + _.KRCWM:$mask, _.RC:$src2, addr:$src3, + (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src2, (i8 imm:$src4)), + _.ImmAllZerosV)), + (!cast(Name#_.ZSuffix#rmbikz) _.RC:$src1, + _.KRCWM:$mask, _.RC:$src2, addr:$src3, + (VPTERNLOG132_imm8 imm:$src4))>; + + // Additional patterns for matching masked broadcasts with different + // operand orders. + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src2, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src2, _.RC:$src1, + (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + (i8 imm:$src4)), _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG213_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode _.RC:$src2, + (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src1, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG231_imm8 imm:$src4))>; + def : Pat<(_.VT (vselect _.KRCWM:$mask, + (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)), + _.RC:$src1, _.RC:$src2, (i8 imm:$src4)), + _.RC:$src1)), + (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask, + _.RC:$src2, addr:$src3, (VPTERNLOG312_imm8 imm:$src4))>; +} + +multiclass avx512_common_ternlog { + let Predicates = [HasAVX512] in + defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, sched.ZMM, + _.info512, NAME>, EVEX_V512; + let Predicates = [HasAVX512, HasVLX] in { + defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, sched.XMM, + _.info128, NAME>, EVEX_V128; + defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, sched.YMM, + _.info256, NAME>, EVEX_V256; + } +} + +defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", SchedWriteVecALU, + avx512vl_i32_info>; +defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", SchedWriteVecALU, + avx512vl_i64_info>, VEX_W; + +// Patterns to implement vnot using vpternlog instead of creating all ones +// using pcmpeq or vpternlog and then xoring with that. The value 15 is chosen +// so that the result is only dependent on src0. But we use the same source +// for all operands to prevent a false dependency. +// TODO: We should maybe have a more generalized algorithm for folding to +// vpternlog. +let Predicates = [HasAVX512] in { + def : Pat<(v8i64 (xor VR512:$src, (bc_v8i64 (v16i32 immAllOnesV)))), + (VPTERNLOGQZrri VR512:$src, VR512:$src, VR512:$src, (i8 15))>; +} + +let Predicates = [HasAVX512, NoVLX] in { + def : Pat<(v2i64 (xor VR128X:$src, (bc_v2i64 (v4i32 immAllOnesV)))), + (EXTRACT_SUBREG + (VPTERNLOGQZrri + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), + (i8 15)), sub_xmm)>; + def : Pat<(v4i64 (xor VR256X:$src, (bc_v4i64 (v8i32 immAllOnesV)))), + (EXTRACT_SUBREG + (VPTERNLOGQZrri + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm), + (i8 15)), sub_ymm)>; +} + +let Predicates = [HasVLX] in { + def : Pat<(v2i64 (xor VR128X:$src, (bc_v2i64 (v4i32 immAllOnesV)))), + (VPTERNLOGQZ128rri VR128X:$src, VR128X:$src, VR128X:$src, (i8 15))>; + def : Pat<(v4i64 (xor VR256X:$src, (bc_v4i64 (v8i32 immAllOnesV)))), + (VPTERNLOGQZ256rri VR256X:$src, VR256X:$src, VR256X:$src, (i8 15))>; +} + +//===----------------------------------------------------------------------===// +// AVX-512 - FixupImm +//===----------------------------------------------------------------------===// + +multiclass avx512_fixupimm_packed opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + X86VectorVTInfo TblVT>{ + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable_3src, Sched<[sched]>; + defm rmi : AVX512_maskable_3src, + Sched<[sched.Folded, ReadAfterLd]>; + defm rmbi : AVX512_maskable_3src, + EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + } // Constraints = "$src1 = $dst" +} + +multiclass avx512_fixupimm_packed_sae opc, string OpcodeStr, + SDNode OpNode, X86FoldableSchedWrite sched, + X86VectorVTInfo _, X86VectorVTInfo TblVT>{ +let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { + defm rrib : AVX512_maskable_3src, + EVEX_B, Sched<[sched]>; + } +} + +multiclass avx512_fixupimm_scalar opc, string OpcodeStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo _, + X86VectorVTInfo _src3VT> { + let Constraints = "$src1 = $dst" , Predicates = [HasAVX512], + ExeDomain = _.ExeDomain in { + defm rri : AVX512_maskable_3src_scalar, Sched<[sched]>; + defm rrib : AVX512_maskable_3src_scalar, + EVEX_B, Sched<[sched.Folded, ReadAfterLd]>; + defm rmi : AVX512_maskable_3src_scalar, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass avx512_fixupimm_packed_all { + let Predicates = [HasAVX512] in + defm Z : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, sched.ZMM, + _Vec.info512, _Tbl.info512>, + avx512_fixupimm_packed_sae<0x54, "vfixupimm", X86VFixupimm, sched.ZMM, + _Vec.info512, _Tbl.info512>, AVX512AIi8Base, + EVEX_4V, EVEX_V512; + let Predicates = [HasAVX512, HasVLX] in { + defm Z128 : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, sched.XMM, + _Vec.info128, _Tbl.info128>, AVX512AIi8Base, + EVEX_4V, EVEX_V128; + defm Z256 : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, sched.YMM, + _Vec.info256, _Tbl.info256>, AVX512AIi8Base, + EVEX_4V, EVEX_V256; + } +} + +defm VFIXUPIMMSSZ : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar, + SchedWriteFAdd.Scl, f32x_info, v4i32x_info>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; +defm VFIXUPIMMSDZ : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar, + SchedWriteFAdd.Scl, f64x_info, v2i64x_info>, + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; +defm VFIXUPIMMPS : avx512_fixupimm_packed_all, EVEX_CD8<32, CD8VF>; +defm VFIXUPIMMPD : avx512_fixupimm_packed_all, EVEX_CD8<64, CD8VF>, VEX_W; + +// Patterns used to select SSE scalar fp arithmetic instructions from +// either: +// +// (1) a scalar fp operation followed by a blend +// +// The effect is that the backend no longer emits unnecessary vector +// insert instructions immediately after SSE scalar fp instructions +// like addss or mulss. +// +// For example, given the following code: +// __m128 foo(__m128 A, __m128 B) { +// A[0] += B[0]; +// return A; +// } +// +// Previously we generated: +// addss %xmm0, %xmm1 +// movss %xmm1, %xmm0 +// +// We now generate: +// addss %xmm1, %xmm0 +// +// (2) a vector packed single/double fp operation followed by a vector insert +// +// The effect is that the backend converts the packed fp instruction +// followed by a vector insert into a single SSE scalar fp instruction. +// +// For example, given the following code: +// __m128 foo(__m128 A, __m128 B) { +// __m128 C = A + B; +// return (__m128) {c[0], a[1], a[2], a[3]}; +// } +// +// Previously we generated: +// addps %xmm0, %xmm1 +// movss %xmm1, %xmm0 +// +// We now generate: +// addss %xmm1, %xmm0 + +// TODO: Some canonicalization in lowering would simplify the number of +// patterns we have to try to match. +multiclass AVX512_scalar_math_fp_patterns { + let Predicates = [HasAVX512] in { + // extracted scalar math op with insert via movss + def : Pat<(MoveNode + (_.VT VR128X:$dst), + (_.VT (scalar_to_vector + (Op (_.EltVT (extractelt (_.VT VR128X:$dst), (iPTR 0))), + _.FRC:$src)))), + (!cast("V"#OpcPrefix#Zrr_Int) _.VT:$dst, + (_.VT (COPY_TO_REGCLASS _.FRC:$src, VR128X)))>; + + // extracted masked scalar math op with insert via movss + def : Pat<(MoveNode (_.VT VR128X:$src1), + (scalar_to_vector + (X86selects VK1WM:$mask, + (Op (_.EltVT + (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src2), + _.FRC:$src0))), + (!cast("V"#OpcPrefix#Zrr_Intk) + (_.VT (COPY_TO_REGCLASS _.FRC:$src0, VR128X)), + VK1WM:$mask, _.VT:$src1, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)))>; + + // extracted masked scalar math op with insert via movss + def : Pat<(MoveNode (_.VT VR128X:$src1), + (scalar_to_vector + (X86selects VK1WM:$mask, + (Op (_.EltVT + (extractelt (_.VT VR128X:$src1), (iPTR 0))), + _.FRC:$src2), (_.EltVT ZeroFP)))), + (!cast("V"#OpcPrefix#Zrr_Intkz) + VK1WM:$mask, _.VT:$src1, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)))>; + } +} + +defm : AVX512_scalar_math_fp_patterns; +defm : AVX512_scalar_math_fp_patterns; +defm : AVX512_scalar_math_fp_patterns; +defm : AVX512_scalar_math_fp_patterns; + +defm : AVX512_scalar_math_fp_patterns; +defm : AVX512_scalar_math_fp_patterns; +defm : AVX512_scalar_math_fp_patterns; +defm : AVX512_scalar_math_fp_patterns; + +multiclass AVX512_scalar_unary_math_patterns { + let Predicates = [HasAVX512] in { + def : Pat<(_.VT (Move _.VT:$dst, + (scalar_to_vector (OpNode (extractelt _.VT:$src, 0))))), + (!cast("V"#OpcPrefix#Zr_Int) _.VT:$dst, _.VT:$src)>; + } +} + +defm : AVX512_scalar_unary_math_patterns; +defm : AVX512_scalar_unary_math_patterns; + +multiclass AVX512_scalar_unary_math_imm_patterns ImmV> { + let Predicates = [HasAVX512] in { + def : Pat<(_.VT (Move _.VT:$dst, + (scalar_to_vector (OpNode (extractelt _.VT:$src, 0))))), + (!cast("V"#OpcPrefix#Zr_Int) _.VT:$dst, _.VT:$src, + (i32 ImmV))>; + } +} + +defm : AVX512_scalar_unary_math_imm_patterns; +defm : AVX512_scalar_unary_math_imm_patterns; +defm : AVX512_scalar_unary_math_imm_patterns; +defm : AVX512_scalar_unary_math_imm_patterns; + +//===----------------------------------------------------------------------===// +// AES instructions +//===----------------------------------------------------------------------===// + +multiclass avx512_vaes Op, string OpStr, string IntPrefix> { + let Predicates = [HasVLX, HasVAES] in { + defm Z128 : AESI_binop_rm_int(IntPrefix), + loadv2i64, 0, VR128X, i128mem>, + EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V128, VEX_WIG; + defm Z256 : AESI_binop_rm_int(IntPrefix##"_256"), + loadv4i64, 0, VR256X, i256mem>, + EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V256, VEX_WIG; + } + let Predicates = [HasAVX512, HasVAES] in + defm Z : AESI_binop_rm_int(IntPrefix##"_512"), + loadv8i64, 0, VR512, i512mem>, + EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_WIG; +} + +defm VAESENC : avx512_vaes<0xDC, "vaesenc", "int_x86_aesni_aesenc">; +defm VAESENCLAST : avx512_vaes<0xDD, "vaesenclast", "int_x86_aesni_aesenclast">; +defm VAESDEC : avx512_vaes<0xDE, "vaesdec", "int_x86_aesni_aesdec">; +defm VAESDECLAST : avx512_vaes<0xDF, "vaesdeclast", "int_x86_aesni_aesdeclast">; + +//===----------------------------------------------------------------------===// +// PCLMUL instructions - Carry less multiplication +//===----------------------------------------------------------------------===// + +let Predicates = [HasAVX512, HasVPCLMULQDQ] in +defm VPCLMULQDQZ : vpclmulqdq, + EVEX_4V, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_WIG; + +let Predicates = [HasVLX, HasVPCLMULQDQ] in { +defm VPCLMULQDQZ128 : vpclmulqdq, + EVEX_4V, EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_WIG; + +defm VPCLMULQDQZ256: vpclmulqdq, EVEX_4V, EVEX_V256, + EVEX_CD8<64, CD8VF>, VEX_WIG; +} + +// Aliases +defm : vpclmulqdq_aliases<"VPCLMULQDQZ", VR512, i512mem>; +defm : vpclmulqdq_aliases<"VPCLMULQDQZ128", VR128X, i128mem>; +defm : vpclmulqdq_aliases<"VPCLMULQDQZ256", VR256X, i256mem>; + +//===----------------------------------------------------------------------===// +// VBMI2 +//===----------------------------------------------------------------------===// + +multiclass VBMI2_shift_var_rm Op, string OpStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo VTI> { + let Constraints = "$src1 = $dst", + ExeDomain = VTI.ExeDomain in { + defm r: AVX512_maskable_3src, + AVX512FMA3Base, Sched<[sched]>; + defm m: AVX512_maskable_3src, + AVX512FMA3Base, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +multiclass VBMI2_shift_var_rmb Op, string OpStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo VTI> + : VBMI2_shift_var_rm { + let Constraints = "$src1 = $dst", + ExeDomain = VTI.ExeDomain in + defm mb: AVX512_maskable_3src, + AVX512FMA3Base, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass VBMI2_shift_var_rm_common Op, string OpStr, SDNode OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo VTI> { + let Predicates = [HasVBMI2] in + defm Z : VBMI2_shift_var_rm, + EVEX_V512; + let Predicates = [HasVBMI2, HasVLX] in { + defm Z256 : VBMI2_shift_var_rm, + EVEX_V256; + defm Z128 : VBMI2_shift_var_rm, + EVEX_V128; + } +} + +multiclass VBMI2_shift_var_rmb_common Op, string OpStr, SDNode OpNode, + X86SchedWriteWidths sched, AVX512VLVectorVTInfo VTI> { + let Predicates = [HasVBMI2] in + defm Z : VBMI2_shift_var_rmb, + EVEX_V512; + let Predicates = [HasVBMI2, HasVLX] in { + defm Z256 : VBMI2_shift_var_rmb, + EVEX_V256; + defm Z128 : VBMI2_shift_var_rmb, + EVEX_V128; + } +} +multiclass VBMI2_shift_var wOp, bits<8> dqOp, string Prefix, + SDNode OpNode, X86SchedWriteWidths sched> { + defm W : VBMI2_shift_var_rm_common, VEX_W, EVEX_CD8<16, CD8VF>; + defm D : VBMI2_shift_var_rmb_common, EVEX_CD8<32, CD8VF>; + defm Q : VBMI2_shift_var_rmb_common, VEX_W, EVEX_CD8<64, CD8VF>; +} + +multiclass VBMI2_shift_imm wOp, bits<8> dqOp, string Prefix, + SDNode OpNode, X86SchedWriteWidths sched> { + defm W : avx512_common_3Op_rm_imm8, + VEX_W, EVEX_CD8<16, CD8VF>; + defm D : avx512_common_3Op_imm8, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; + defm Q : avx512_common_3Op_imm8, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; +} + +// Concat & Shift +defm VPSHLDV : VBMI2_shift_var<0x70, 0x71, "vpshldv", X86VShldv, SchedWriteVecIMul>; +defm VPSHRDV : VBMI2_shift_var<0x72, 0x73, "vpshrdv", X86VShrdv, SchedWriteVecIMul>; +defm VPSHLD : VBMI2_shift_imm<0x70, 0x71, "vpshld", X86VShld, SchedWriteVecIMul>; +defm VPSHRD : VBMI2_shift_imm<0x72, 0x73, "vpshrd", X86VShrd, SchedWriteVecIMul>; + +// Compress +defm VPCOMPRESSB : compress_by_elt_width<0x63, "vpcompressb", WriteVarShuffle256, + avx512vl_i8_info, HasVBMI2>, EVEX, + NotMemoryFoldable; +defm VPCOMPRESSW : compress_by_elt_width <0x63, "vpcompressw", WriteVarShuffle256, + avx512vl_i16_info, HasVBMI2>, EVEX, VEX_W, + NotMemoryFoldable; +// Expand +defm VPEXPANDB : expand_by_elt_width <0x62, "vpexpandb", WriteVarShuffle256, + avx512vl_i8_info, HasVBMI2>, EVEX; +defm VPEXPANDW : expand_by_elt_width <0x62, "vpexpandw", WriteVarShuffle256, + avx512vl_i16_info, HasVBMI2>, EVEX, VEX_W; + +//===----------------------------------------------------------------------===// +// VNNI +//===----------------------------------------------------------------------===// + +let Constraints = "$src1 = $dst" in +multiclass VNNI_rmb Op, string OpStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo VTI> { + defm r : AVX512_maskable_3src, + EVEX_4V, T8PD, Sched<[sched]>; + defm m : AVX512_maskable_3src, + EVEX_4V, EVEX_CD8<32, CD8VF>, T8PD, + Sched<[sched.Folded, ReadAfterLd]>; + defm mb : AVX512_maskable_3src, + EVEX_4V, EVEX_CD8<32, CD8VF>, EVEX_B, + T8PD, Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass VNNI_common Op, string OpStr, SDNode OpNode, + X86SchedWriteWidths sched> { + let Predicates = [HasVNNI] in + defm Z : VNNI_rmb, EVEX_V512; + let Predicates = [HasVNNI, HasVLX] in { + defm Z256 : VNNI_rmb, EVEX_V256; + defm Z128 : VNNI_rmb, EVEX_V128; + } +} + +// FIXME: Is there a better scheduler class for VPDP? +defm VPDPBUSD : VNNI_common<0x50, "vpdpbusd", X86Vpdpbusd, SchedWriteVecIMul>; +defm VPDPBUSDS : VNNI_common<0x51, "vpdpbusds", X86Vpdpbusds, SchedWriteVecIMul>; +defm VPDPWSSD : VNNI_common<0x52, "vpdpwssd", X86Vpdpwssd, SchedWriteVecIMul>; +defm VPDPWSSDS : VNNI_common<0x53, "vpdpwssds", X86Vpdpwssds, SchedWriteVecIMul>; + +//===----------------------------------------------------------------------===// +// Bit Algorithms +//===----------------------------------------------------------------------===// + +// FIXME: Is there a better scheduler class for VPOPCNTB/VPOPCNTW? +defm VPOPCNTB : avx512_unary_rm_vl<0x54, "vpopcntb", ctpop, SchedWriteVecALU, + avx512vl_i8_info, HasBITALG>; +defm VPOPCNTW : avx512_unary_rm_vl<0x54, "vpopcntw", ctpop, SchedWriteVecALU, + avx512vl_i16_info, HasBITALG>, VEX_W; + +defm : avx512_unary_lowering<"VPOPCNTB", ctpop, avx512vl_i8_info, HasBITALG>; +defm : avx512_unary_lowering<"VPOPCNTW", ctpop, avx512vl_i16_info, HasBITALG>; + +multiclass VPSHUFBITQMB_rm { + defm rr : AVX512_maskable_cmp<0x8F, MRMSrcReg, VTI, (outs VTI.KRC:$dst), + (ins VTI.RC:$src1, VTI.RC:$src2), + "vpshufbitqmb", + "$src2, $src1", "$src1, $src2", + (X86Vpshufbitqmb (VTI.VT VTI.RC:$src1), + (VTI.VT VTI.RC:$src2))>, EVEX_4V, T8PD, + Sched<[sched]>; + defm rm : AVX512_maskable_cmp<0x8F, MRMSrcMem, VTI, (outs VTI.KRC:$dst), + (ins VTI.RC:$src1, VTI.MemOp:$src2), + "vpshufbitqmb", + "$src2, $src1", "$src1, $src2", + (X86Vpshufbitqmb (VTI.VT VTI.RC:$src1), + (VTI.VT (bitconvert (VTI.LdFrag addr:$src2))))>, + EVEX_4V, EVEX_CD8<8, CD8VF>, T8PD, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass VPSHUFBITQMB_common { + let Predicates = [HasBITALG] in + defm Z : VPSHUFBITQMB_rm, EVEX_V512; + let Predicates = [HasBITALG, HasVLX] in { + defm Z256 : VPSHUFBITQMB_rm, EVEX_V256; + defm Z128 : VPSHUFBITQMB_rm, EVEX_V128; + } +} + +// FIXME: Is there a better scheduler class for VPSHUFBITQMB? +defm VPSHUFBITQMB : VPSHUFBITQMB_common; + +//===----------------------------------------------------------------------===// +// GFNI +//===----------------------------------------------------------------------===// + +multiclass GF2P8MULB_avx512_common Op, string OpStr, SDNode OpNode, + X86SchedWriteWidths sched> { + let Predicates = [HasGFNI, HasAVX512, HasBWI] in + defm Z : avx512_binop_rm, + EVEX_V512; + let Predicates = [HasGFNI, HasVLX, HasBWI] in { + defm Z256 : avx512_binop_rm, + EVEX_V256; + defm Z128 : avx512_binop_rm, + EVEX_V128; + } +} + +defm VGF2P8MULB : GF2P8MULB_avx512_common<0xCF, "vgf2p8mulb", X86GF2P8mulb, + SchedWriteVecALU>, + EVEX_CD8<8, CD8VF>, T8PD; + +multiclass GF2P8AFFINE_avx512_rmb_imm Op, string OpStr, SDNode OpNode, + X86FoldableSchedWrite sched, X86VectorVTInfo VTI, + X86VectorVTInfo BcstVTI> + : avx512_3Op_rm_imm8 { + let ExeDomain = VTI.ExeDomain in + defm rmbi : AVX512_maskable, EVEX_B, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass GF2P8AFFINE_avx512_common Op, string OpStr, SDNode OpNode, + X86SchedWriteWidths sched> { + let Predicates = [HasGFNI, HasAVX512, HasBWI] in + defm Z : GF2P8AFFINE_avx512_rmb_imm, EVEX_V512; + let Predicates = [HasGFNI, HasVLX, HasBWI] in { + defm Z256 : GF2P8AFFINE_avx512_rmb_imm, EVEX_V256; + defm Z128 : GF2P8AFFINE_avx512_rmb_imm, EVEX_V128; + } +} + +defm VGF2P8AFFINEINVQB : GF2P8AFFINE_avx512_common<0xCF, "vgf2p8affineinvqb", + X86GF2P8affineinvqb, SchedWriteVecIMul>, + EVEX_4V, EVEX_CD8<8, CD8VF>, VEX_W, AVX512AIi8Base; +defm VGF2P8AFFINEQB : GF2P8AFFINE_avx512_common<0xCE, "vgf2p8affineqb", + X86GF2P8affineqb, SchedWriteVecIMul>, + EVEX_4V, EVEX_CD8<8, CD8VF>, VEX_W, AVX512AIi8Base; + + +//===----------------------------------------------------------------------===// +// AVX5124FMAPS +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 1, ExeDomain = SSEPackedSingle, + Constraints = "$src1 = $dst" in { +defm V4FMADDPSrm : AVX512_maskable_3src_in_asm<0x9A, MRMSrcMem, v16f32_info, + (outs VR512:$dst), (ins VR512:$src2, f128mem:$src3), + "v4fmaddps", "$src3, $src2", "$src2, $src3", + []>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>, + Sched<[SchedWriteFMA.ZMM.Folded]>; + +defm V4FNMADDPSrm : AVX512_maskable_3src_in_asm<0xAA, MRMSrcMem, v16f32_info, + (outs VR512:$dst), (ins VR512:$src2, f128mem:$src3), + "v4fnmaddps", "$src3, $src2", "$src2, $src3", + []>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>, + Sched<[SchedWriteFMA.ZMM.Folded]>; + +defm V4FMADDSSrm : AVX512_maskable_3src_in_asm<0x9B, MRMSrcMem, f32x_info, + (outs VR128X:$dst), (ins VR128X:$src2, f128mem:$src3), + "v4fmaddss", "$src3, $src2", "$src2, $src3", + []>, EVEX_V128, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>, + Sched<[SchedWriteFMA.Scl.Folded]>; + +defm V4FNMADDSSrm : AVX512_maskable_3src_in_asm<0xAB, MRMSrcMem, f32x_info, + (outs VR128X:$dst), (ins VR128X:$src2, f128mem:$src3), + "v4fnmaddss", "$src3, $src2", "$src2, $src3", + []>, EVEX_V128, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>, + Sched<[SchedWriteFMA.Scl.Folded]>; +} + +//===----------------------------------------------------------------------===// +// AVX5124VNNIW +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 1, ExeDomain = SSEPackedInt, + Constraints = "$src1 = $dst" in { +defm VP4DPWSSDrm : AVX512_maskable_3src_in_asm<0x52, MRMSrcMem, v16i32_info, + (outs VR512:$dst), (ins VR512:$src2, f128mem:$src3), + "vp4dpwssd", "$src3, $src2", "$src2, $src3", + []>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>, + Sched<[SchedWriteFMA.ZMM.Folded]>; + +defm VP4DPWSSDSrm : AVX512_maskable_3src_in_asm<0x53, MRMSrcMem, v16i32_info, + (outs VR512:$dst), (ins VR512:$src2, f128mem:$src3), + "vp4dpwssds", "$src3, $src2", "$src2, $src3", + []>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>, + Sched<[SchedWriteFMA.ZMM.Folded]>; +} + diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrArithmetic.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrArithmetic.td new file mode 100644 index 0000000..c444fa7 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrArithmetic.td @@ -0,0 +1,1338 @@ +//===-- X86InstrArithmetic.td - Integer Arithmetic Instrs --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the integer arithmetic instructions in the X86 +// architecture. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// LEA - Load Effective Address +let SchedRW = [WriteLEA] in { +let hasSideEffects = 0 in +def LEA16r : I<0x8D, MRMSrcMem, + (outs GR16:$dst), (ins anymem:$src), + "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize16; +let isReMaterializable = 1 in +def LEA32r : I<0x8D, MRMSrcMem, + (outs GR32:$dst), (ins anymem:$src), + "lea{l}\t{$src|$dst}, {$dst|$src}", + [(set GR32:$dst, lea32addr:$src)]>, + OpSize32, Requires<[Not64BitMode]>; + +def LEA64_32r : I<0x8D, MRMSrcMem, + (outs GR32:$dst), (ins lea64_32mem:$src), + "lea{l}\t{$src|$dst}, {$dst|$src}", + [(set GR32:$dst, lea64_32addr:$src)]>, + OpSize32, Requires<[In64BitMode]>; + +let isReMaterializable = 1 in +def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src), + "lea{q}\t{$src|$dst}, {$dst|$src}", + [(set GR64:$dst, lea64addr:$src)]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Fixed-Register Multiplication and Division Instructions. +// + +// SchedModel info for instruction that loads one value and gets the second +// (and possibly third) value from a register. +// This is used for instructions that put the memory operands before other +// uses. +class SchedLoadReg : Sched<[SW, + // Memory operand. + ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, + // Register reads (implicit or explicit). + ReadAfterLd, ReadAfterLd]>; + +// Extra precision multiplication + +// AL is really implied by AX, but the registers in Defs must match the +// SDNode results (i8, i32). +// AL,AH = AL*GR8 +let Defs = [AL,EFLAGS,AX], Uses = [AL] in +def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src", + // FIXME: Used for 8-bit mul, ignore result upper 8 bits. + // This probably ought to be moved to a def : Pat<> if the + // syntax can be accepted. + [(set AL, (mul AL, GR8:$src)), + (implicit EFLAGS)]>, Sched<[WriteIMul]>; +// AX,DX = AX*GR16 +let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in +def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), + "mul{w}\t$src", + []>, OpSize16, Sched<[WriteIMul]>; +// EAX,EDX = EAX*GR32 +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in +def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), + "mul{l}\t$src", + [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/]>, + OpSize32, Sched<[WriteIMul]>; +// RAX,RDX = RAX*GR64 +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in +def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src), + "mul{q}\t$src", + [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>, + Sched<[WriteIMul64]>; +// AL,AH = AL*[mem8] +let Defs = [AL,EFLAGS,AX], Uses = [AL] in +def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src), + "mul{b}\t$src", + // FIXME: Used for 8-bit mul, ignore result upper 8 bits. + // This probably ought to be moved to a def : Pat<> if the + // syntax can be accepted. + [(set AL, (mul AL, (loadi8 addr:$src))), + (implicit EFLAGS)]>, SchedLoadReg; +// AX,DX = AX*[mem16] +let mayLoad = 1, hasSideEffects = 0 in { +let Defs = [AX,DX,EFLAGS], Uses = [AX] in +def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src), + "mul{w}\t$src", []>, OpSize16, SchedLoadReg; +// EAX,EDX = EAX*[mem32] +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in +def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src), + "mul{l}\t$src", []>, OpSize32, SchedLoadReg; +// RAX,RDX = RAX*[mem64] +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in +def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src), + "mul{q}\t$src", []>, SchedLoadReg, + Requires<[In64BitMode]>; +} + +let hasSideEffects = 0 in { +// AL,AH = AL*GR8 +let Defs = [AL,EFLAGS,AX], Uses = [AL] in +def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>, + Sched<[WriteIMul]>; +// AX,DX = AX*GR16 +let Defs = [AX,DX,EFLAGS], Uses = [AX] in +def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>, + OpSize16, Sched<[WriteIMul]>; +// EAX,EDX = EAX*GR32 +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in +def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>, + OpSize32, Sched<[WriteIMul]>; +// RAX,RDX = RAX*GR64 +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in +def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>, + Sched<[WriteIMul64]>; + +let mayLoad = 1 in { +// AL,AH = AL*[mem8] +let Defs = [AL,EFLAGS,AX], Uses = [AL] in +def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src), + "imul{b}\t$src", []>, SchedLoadReg; +// AX,DX = AX*[mem16] +let Defs = [AX,DX,EFLAGS], Uses = [AX] in +def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src), + "imul{w}\t$src", []>, OpSize16, SchedLoadReg; +// EAX,EDX = EAX*[mem32] +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in +def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src), + "imul{l}\t$src", []>, OpSize32, SchedLoadReg; +// RAX,RDX = RAX*[mem64] +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in +def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src), + "imul{q}\t$src", []>, SchedLoadReg, + Requires<[In64BitMode]>; +} +} // hasSideEffects + + +let Defs = [EFLAGS] in { +let Constraints = "$src1 = $dst" in { + +let isCommutable = 1 in { +// X = IMUL Y, Z --> X = IMUL Z, Y +// Register-Register Signed Integer Multiply +def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), + "imul{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, EFLAGS, + (X86smul_flag GR16:$src1, GR16:$src2))]>, + Sched<[WriteIMul]>, TB, OpSize16; +def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), + "imul{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, EFLAGS, + (X86smul_flag GR32:$src1, GR32:$src2))]>, + Sched<[WriteIMul]>, TB, OpSize32; +def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), + "imul{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, EFLAGS, + (X86smul_flag GR64:$src1, GR64:$src2))]>, + Sched<[WriteIMul64]>, TB; +} // isCommutable + +// Register-Memory Signed Integer Multiply +def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), + (ins GR16:$src1, i16mem:$src2), + "imul{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, EFLAGS, + (X86smul_flag GR16:$src1, (loadi16 addr:$src2)))]>, + Sched<[WriteIMul.Folded, ReadAfterLd]>, TB, OpSize16; +def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$src1, i32mem:$src2), + "imul{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, EFLAGS, + (X86smul_flag GR32:$src1, (loadi32 addr:$src2)))]>, + Sched<[WriteIMul.Folded, ReadAfterLd]>, TB, OpSize32; +def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$src1, i64mem:$src2), + "imul{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, EFLAGS, + (X86smul_flag GR64:$src1, (loadi64 addr:$src2)))]>, + Sched<[WriteIMul64.Folded, ReadAfterLd]>, TB; +} // Constraints = "$src1 = $dst" + +} // Defs = [EFLAGS] + +// Surprisingly enough, these are not two address instructions! +let Defs = [EFLAGS] in { +// Register-Integer Signed Integer Multiply +def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 + (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), + "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR16:$dst, EFLAGS, + (X86smul_flag GR16:$src1, imm:$src2))]>, + Sched<[WriteIMul]>, OpSize16; +def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 + (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR16:$dst, EFLAGS, + (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>, + Sched<[WriteIMul]>, OpSize16; +def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 + (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), + "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32:$dst, EFLAGS, + (X86smul_flag GR32:$src1, imm:$src2))]>, + Sched<[WriteIMul]>, OpSize32; +def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 + (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32:$dst, EFLAGS, + (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>, + Sched<[WriteIMul]>, OpSize32; +def IMUL64rri32 : RIi32S<0x69, MRMSrcReg, // GR64 = GR64*I32 + (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), + "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR64:$dst, EFLAGS, + (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>, + Sched<[WriteIMul64]>; +def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8 + (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR64:$dst, EFLAGS, + (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>, + Sched<[WriteIMul64]>; + +// Memory-Integer Signed Integer Multiply +def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 + (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2), + "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR16:$dst, EFLAGS, + (X86smul_flag (loadi16 addr:$src1), imm:$src2))]>, + Sched<[WriteIMul.Folded]>, OpSize16; +def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 + (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2), + "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR16:$dst, EFLAGS, + (X86smul_flag (loadi16 addr:$src1), + i16immSExt8:$src2))]>, + Sched<[WriteIMul.Folded]>, OpSize16; +def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 + (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2), + "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32:$dst, EFLAGS, + (X86smul_flag (loadi32 addr:$src1), imm:$src2))]>, + Sched<[WriteIMul.Folded]>, OpSize32; +def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 + (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2), + "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32:$dst, EFLAGS, + (X86smul_flag (loadi32 addr:$src1), + i32immSExt8:$src2))]>, + Sched<[WriteIMul.Folded]>, OpSize32; +def IMUL64rmi32 : RIi32S<0x69, MRMSrcMem, // GR64 = [mem64]*I32 + (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2), + "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR64:$dst, EFLAGS, + (X86smul_flag (loadi64 addr:$src1), + i64immSExt32:$src2))]>, + Sched<[WriteIMul64.Folded]>; +def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8 + (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2), + "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR64:$dst, EFLAGS, + (X86smul_flag (loadi64 addr:$src1), + i64immSExt8:$src2))]>, + Sched<[WriteIMul64.Folded]>; +} // Defs = [EFLAGS] + +// unsigned division/remainder +let hasSideEffects = 1 in { // so that we don't speculatively execute +let Defs = [AL,AH,EFLAGS], Uses = [AX] in +def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH + "div{b}\t$src", []>, Sched<[WriteDiv8]>; +let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in +def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX + "div{w}\t$src", []>, Sched<[WriteDiv16]>, OpSize16; +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in +def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX + "div{l}\t$src", []>, Sched<[WriteDiv32]>, OpSize32; +// RDX:RAX/r64 = RAX,RDX +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in +def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), + "div{q}\t$src", []>, Sched<[WriteDiv64]>; + +let mayLoad = 1 in { +let Defs = [AL,AH,EFLAGS], Uses = [AX] in +def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH + "div{b}\t$src", []>, SchedLoadReg; +let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in +def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX + "div{w}\t$src", []>, OpSize16, SchedLoadReg; +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX +def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), + "div{l}\t$src", []>, SchedLoadReg, OpSize32; +// RDX:RAX/[mem64] = RAX,RDX +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in +def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), + "div{q}\t$src", []>, SchedLoadReg, + Requires<[In64BitMode]>; +} + +// Signed division/remainder. +let Defs = [AL,AH,EFLAGS], Uses = [AX] in +def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH + "idiv{b}\t$src", []>, Sched<[WriteIDiv8]>; +let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in +def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX + "idiv{w}\t$src", []>, Sched<[WriteIDiv16]>, OpSize16; +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in +def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX + "idiv{l}\t$src", []>, Sched<[WriteIDiv32]>, OpSize32; +// RDX:RAX/r64 = RAX,RDX +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in +def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), + "idiv{q}\t$src", []>, Sched<[WriteIDiv64]>; + +let mayLoad = 1 in { +let Defs = [AL,AH,EFLAGS], Uses = [AX] in +def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH + "idiv{b}\t$src", []>, SchedLoadReg; +let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in +def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX + "idiv{w}\t$src", []>, OpSize16, SchedLoadReg; +let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX +def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), + "idiv{l}\t$src", []>, OpSize32, SchedLoadReg; +let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX +def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), + "idiv{q}\t$src", []>, SchedLoadReg, + Requires<[In64BitMode]>; +} +} // hasSideEffects = 0 + +//===----------------------------------------------------------------------===// +// Two address Instructions. +// + +// unary instructions +let CodeSize = 2 in { +let Defs = [EFLAGS] in { +let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { +def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1), + "neg{b}\t$dst", + [(set GR8:$dst, (ineg GR8:$src1)), + (implicit EFLAGS)]>; +def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1), + "neg{w}\t$dst", + [(set GR16:$dst, (ineg GR16:$src1)), + (implicit EFLAGS)]>, OpSize16; +def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1), + "neg{l}\t$dst", + [(set GR32:$dst, (ineg GR32:$src1)), + (implicit EFLAGS)]>, OpSize32; +def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst", + [(set GR64:$dst, (ineg GR64:$src1)), + (implicit EFLAGS)]>; +} // Constraints = "$src1 = $dst", SchedRW + +// Read-modify-write negate. +let SchedRW = [WriteALURMW] in { +def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), + "neg{b}\t$dst", + [(store (ineg (loadi8 addr:$dst)), addr:$dst), + (implicit EFLAGS)]>; +def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), + "neg{w}\t$dst", + [(store (ineg (loadi16 addr:$dst)), addr:$dst), + (implicit EFLAGS)]>, OpSize16; +def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), + "neg{l}\t$dst", + [(store (ineg (loadi32 addr:$dst)), addr:$dst), + (implicit EFLAGS)]>, OpSize32; +def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst", + [(store (ineg (loadi64 addr:$dst)), addr:$dst), + (implicit EFLAGS)]>, + Requires<[In64BitMode]>; +} // SchedRW +} // Defs = [EFLAGS] + + +// Note: NOT does not set EFLAGS! + +let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { +def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1), + "not{b}\t$dst", + [(set GR8:$dst, (not GR8:$src1))]>; +def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1), + "not{w}\t$dst", + [(set GR16:$dst, (not GR16:$src1))]>, OpSize16; +def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1), + "not{l}\t$dst", + [(set GR32:$dst, (not GR32:$src1))]>, OpSize32; +def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst", + [(set GR64:$dst, (not GR64:$src1))]>; +} // Constraints = "$src1 = $dst", SchedRW + +let SchedRW = [WriteALURMW] in { +def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), + "not{b}\t$dst", + [(store (not (loadi8 addr:$dst)), addr:$dst)]>; +def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), + "not{w}\t$dst", + [(store (not (loadi16 addr:$dst)), addr:$dst)]>, + OpSize16; +def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), + "not{l}\t$dst", + [(store (not (loadi32 addr:$dst)), addr:$dst)]>, + OpSize32; +def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst", + [(store (not (loadi64 addr:$dst)), addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW +} // CodeSize + +// TODO: inc/dec is slow for P4, but fast for Pentium-M. +let Defs = [EFLAGS] in { +let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { +let CodeSize = 2 in +def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), + "inc{b}\t$dst", + [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>; +let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA. +def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1), + "inc{w}\t$dst", + [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>, OpSize16; +def INC32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1), + "inc{l}\t$dst", + [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>, OpSize32; +def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst", + [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))]>; +} // isConvertibleToThreeAddress = 1, CodeSize = 2 + +// Short forms only valid in 32-bit mode. Selected during MCInst lowering. +let CodeSize = 1, hasSideEffects = 0 in { +def INC16r_alt : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1), + "inc{w}\t$dst", []>, + OpSize16, Requires<[Not64BitMode]>; +def INC32r_alt : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1), + "inc{l}\t$dst", []>, + OpSize32, Requires<[Not64BitMode]>; +} // CodeSize = 1, hasSideEffects = 0 +} // Constraints = "$src1 = $dst", SchedRW + +let CodeSize = 2, SchedRW = [WriteALURMW] in { +let Predicates = [UseIncDec] in { + def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst", + [(store (add (loadi8 addr:$dst), 1), addr:$dst), + (implicit EFLAGS)]>; + def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", + [(store (add (loadi16 addr:$dst), 1), addr:$dst), + (implicit EFLAGS)]>, OpSize16; + def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", + [(store (add (loadi32 addr:$dst), 1), addr:$dst), + (implicit EFLAGS)]>, OpSize32; +} // Predicates +let Predicates = [UseIncDec, In64BitMode] in { + def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst", + [(store (add (loadi64 addr:$dst), 1), addr:$dst), + (implicit EFLAGS)]>; +} // Predicates +} // CodeSize = 2, SchedRW + +let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { +let CodeSize = 2 in +def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), + "dec{b}\t$dst", + [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>; +let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA. +def DEC16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1), + "dec{w}\t$dst", + [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>, OpSize16; +def DEC32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1), + "dec{l}\t$dst", + [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>, OpSize32; +def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst", + [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))]>; +} // isConvertibleToThreeAddress = 1, CodeSize = 2 + +// Short forms only valid in 32-bit mode. Selected during MCInst lowering. +let CodeSize = 1, hasSideEffects = 0 in { +def DEC16r_alt : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1), + "dec{w}\t$dst", []>, + OpSize16, Requires<[Not64BitMode]>; +def DEC32r_alt : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1), + "dec{l}\t$dst", []>, + OpSize32, Requires<[Not64BitMode]>; +} // CodeSize = 1, hasSideEffects = 0 +} // Constraints = "$src1 = $dst", SchedRW + + +let CodeSize = 2, SchedRW = [WriteALURMW] in { +let Predicates = [UseIncDec] in { + def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst", + [(store (add (loadi8 addr:$dst), -1), addr:$dst), + (implicit EFLAGS)]>; + def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", + [(store (add (loadi16 addr:$dst), -1), addr:$dst), + (implicit EFLAGS)]>, OpSize16; + def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", + [(store (add (loadi32 addr:$dst), -1), addr:$dst), + (implicit EFLAGS)]>, OpSize32; +} // Predicates +let Predicates = [UseIncDec, In64BitMode] in { + def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst", + [(store (add (loadi64 addr:$dst), -1), addr:$dst), + (implicit EFLAGS)]>; +} // Predicates +} // CodeSize = 2, SchedRW +} // Defs = [EFLAGS] + +/// X86TypeInfo - This is a bunch of information that describes relevant X86 +/// information about value types. For example, it can tell you what the +/// register class and preferred load to use. +class X86TypeInfo { + /// VT - This is the value type itself. + ValueType VT = vt; + + /// InstrSuffix - This is the suffix used on instructions with this type. For + /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q". + string InstrSuffix = instrsuffix; + + /// RegClass - This is the register class associated with this type. For + /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64. + RegisterClass RegClass = regclass; + + /// LoadNode - This is the load node associated with this type. For + /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64. + PatFrag LoadNode = loadnode; + + /// MemOperand - This is the memory operand associated with this type. For + /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem. + X86MemOperand MemOperand = memoperand; + + /// ImmEncoding - This is the encoding of an immediate of this type. For + /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32 + /// since the immediate fields of i64 instructions is a 32-bit sign extended + /// value. + ImmType ImmEncoding = immkind; + + /// ImmOperand - This is the operand kind of an immediate of this type. For + /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 -> + /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign + /// extended value. + Operand ImmOperand = immoperand; + + /// ImmOperator - This is the operator that should be used to match an + /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32). + SDPatternOperator ImmOperator = immoperator; + + /// Imm8Operand - This is the operand kind to use for an imm8 of this type. + /// For example, i8 -> , i16 -> i16i8imm, i32 -> i32i8imm. This is + /// only used for instructions that have a sign-extended imm8 field form. + Operand Imm8Operand = imm8operand; + + /// Imm8Operator - This is the operator that should be used to match an 8-bit + /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8). + SDPatternOperator Imm8Operator = imm8operator; + + /// HasOddOpcode - This bit is true if the instruction should have an odd (as + /// opposed to even) opcode. Operations on i8 are usually even, operations on + /// other datatypes are odd. + bit HasOddOpcode = hasOddOpcode; + + /// OpSize - Selects whether the instruction needs a 0x66 prefix based on + /// 16-bit vs 32-bit mode. i8/i64 set this to OpSizeFixed. i16 sets this + /// to Opsize16. i32 sets this to OpSize32. + OperandSize OpSize = opSize; + + /// HasREX_WPrefix - This bit is set to true if the instruction should have + /// the 0x40 REX prefix. This is set for i64 types. + bit HasREX_WPrefix = hasREX_WPrefix; +} + +def invalid_node : SDNode<"<>", SDTIntLeaf,[],"<>">; + + +def Xi8 : X86TypeInfo; +def Xi16 : X86TypeInfo; +def Xi32 : X86TypeInfo; +def Xi64 : X86TypeInfo; + +/// ITy - This instruction base class takes the type info for the instruction. +/// Using this, it: +/// 1. Concatenates together the instruction mnemonic with the appropriate +/// suffix letter, a tab, and the arguments. +/// 2. Infers whether the instruction should have a 0x66 prefix byte. +/// 3. Infers whether the instruction should have a 0x40 REX_W prefix. +/// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations) +/// or 1 (for i16,i32,i64 operations). +class ITy opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins, + string mnemonic, string args, list pattern> + : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4}, + opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode }, + f, outs, ins, + !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> { + + // Infer instruction prefixes from type info. + let OpSize = typeinfo.OpSize; + let hasREX_WPrefix = typeinfo.HasREX_WPrefix; +} + +// BinOpRR - Instructions like "add reg, reg, reg". +class BinOpRR opcode, string mnemonic, X86TypeInfo typeinfo, + dag outlist, X86FoldableSchedWrite sched, list pattern> + : ITy, + Sched<[sched]>; + +// BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has +// just a EFLAGS as a result. +class BinOpRR_F opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode> + : BinOpRR; + +// BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has +// both a regclass and EFLAGS as a result. +class BinOpRR_RF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpRR; + +// BinOpRR_RFF - Instructions like "adc reg, reg, reg", where the pattern has +// both a regclass and EFLAGS as a result, and has EFLAGS as input. +class BinOpRR_RFF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpRR; + +// BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding). +class BinOpRR_Rev opcode, string mnemonic, X86TypeInfo typeinfo, + X86FoldableSchedWrite sched = WriteALU> + : ITy, + Sched<[sched]> { + // The disassembler should know about this, but not the asmparser. + let isCodeGenOnly = 1; + let ForceDisassemble = 1; + let hasSideEffects = 0; +} + +// BinOpRR_RDD_Rev - Instructions like "adc reg, reg, reg" (reversed encoding). +class BinOpRR_RFF_Rev opcode, string mnemonic, X86TypeInfo typeinfo> + : BinOpRR_Rev; + +// BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding). +class BinOpRR_F_Rev opcode, string mnemonic, X86TypeInfo typeinfo> + : ITy, + Sched<[WriteALU]> { + // The disassembler should know about this, but not the asmparser. + let isCodeGenOnly = 1; + let ForceDisassemble = 1; + let hasSideEffects = 0; +} + +// BinOpRM - Instructions like "add reg, reg, [mem]". +class BinOpRM opcode, string mnemonic, X86TypeInfo typeinfo, + dag outlist, X86FoldableSchedWrite sched, list pattern> + : ITy, + Sched<[sched.Folded, ReadAfterLd]>; + +// BinOpRM_F - Instructions like "cmp reg, [mem]". +class BinOpRM_F opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpRM; + +// BinOpRM_RF - Instructions like "add reg, reg, [mem]". +class BinOpRM_RF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpRM; + +// BinOpRM_RFF - Instructions like "adc reg, reg, [mem]". +class BinOpRM_RFF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpRM; + +// BinOpRI - Instructions like "add reg, reg, imm". +class BinOpRI opcode, string mnemonic, X86TypeInfo typeinfo, + Format f, dag outlist, X86FoldableSchedWrite sched, list pattern> + : ITy, + Sched<[sched]> { + let ImmT = typeinfo.ImmEncoding; +} + +// BinOpRI_F - Instructions like "cmp reg, imm". +class BinOpRI_F opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode, Format f> + : BinOpRI; + +// BinOpRI_RF - Instructions like "add reg, reg, imm". +class BinOpRI_RF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode, Format f> + : BinOpRI; +// BinOpRI_RFF - Instructions like "adc reg, reg, imm". +class BinOpRI_RFF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode, Format f> + : BinOpRI; + +// BinOpRI8 - Instructions like "add reg, reg, imm8". +class BinOpRI8 opcode, string mnemonic, X86TypeInfo typeinfo, + Format f, dag outlist, X86FoldableSchedWrite sched, list pattern> + : ITy, + Sched<[sched]> { + let ImmT = Imm8; // Always 8-bit immediate. +} + +// BinOpRI8_F - Instructions like "cmp reg, imm8". +class BinOpRI8_F opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode, Format f> + : BinOpRI8; + +// BinOpRI8_RF - Instructions like "add reg, reg, imm8". +class BinOpRI8_RF opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode, Format f> + : BinOpRI8; + +// BinOpRI8_RFF - Instructions like "adc reg, reg, imm8". +class BinOpRI8_RFF opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode, Format f> + : BinOpRI8; + +// BinOpMR - Instructions like "add [mem], reg". +class BinOpMR opcode, string mnemonic, X86TypeInfo typeinfo, + list pattern> + : ITy; + +// BinOpMR_RMW - Instructions like "add [mem], reg". +class BinOpMR_RMW opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpMR, Sched<[WriteALURMW]>; + +// BinOpMR_RMW_FF - Instructions like "adc [mem], reg". +class BinOpMR_RMW_FF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode> + : BinOpMR, Sched<[WriteADCRMW]>; + +// BinOpMR_F - Instructions like "cmp [mem], reg". +class BinOpMR_F opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode> + : BinOpMR, + Sched<[WriteALULd, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, ReadDefault, ReadAfterLd]>; + +// BinOpMI - Instructions like "add [mem], imm". +class BinOpMI opcode, string mnemonic, X86TypeInfo typeinfo, + Format f, list pattern> + : ITy { + let ImmT = typeinfo.ImmEncoding; +} + +// BinOpMI_RMW - Instructions like "add [mem], imm". +class BinOpMI_RMW opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode, Format f> + : BinOpMI, Sched<[WriteALURMW]>; +// BinOpMI_RMW_FF - Instructions like "adc [mem], imm". +class BinOpMI_RMW_FF opcode, string mnemonic, X86TypeInfo typeinfo, + SDNode opnode, Format f> + : BinOpMI, Sched<[WriteADCRMW]>; + +// BinOpMI_F - Instructions like "cmp [mem], imm". +class BinOpMI_F opcode, string mnemonic, X86TypeInfo typeinfo, + SDPatternOperator opnode, Format f> + : BinOpMI, + Sched<[WriteALULd]>; + +// BinOpMI8 - Instructions like "add [mem], imm8". +class BinOpMI8 pattern> + : ITy<0x82, f, typeinfo, + (outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src), + mnemonic, "{$src, $dst|$dst, $src}", pattern> { + let ImmT = Imm8; // Always 8-bit immediate. +} + +// BinOpMI8_RMW - Instructions like "add [mem], imm8". +class BinOpMI8_RMW + : BinOpMI8, Sched<[WriteALURMW]>; + +// BinOpMI8_RMW_FF - Instructions like "adc [mem], imm8". +class BinOpMI8_RMW_FF + : BinOpMI8, Sched<[WriteADCRMW]>; + +// BinOpMI8_F - Instructions like "cmp [mem], imm8". +class BinOpMI8_F + : BinOpMI8, + Sched<[WriteALULd]>; + +// BinOpAI - Instructions like "add %eax, %eax, imm", that imp-def EFLAGS. +class BinOpAI opcode, string mnemonic, X86TypeInfo typeinfo, + Register areg, string operands, X86FoldableSchedWrite sched = WriteALU> + : ITy, Sched<[sched]> { + let ImmT = typeinfo.ImmEncoding; + let Uses = [areg]; + let Defs = [areg, EFLAGS]; + let hasSideEffects = 0; +} + +// BinOpAI_RFF - Instructions like "adc %eax, %eax, imm", that implicitly define +// and use EFLAGS. +class BinOpAI_RFF opcode, string mnemonic, X86TypeInfo typeinfo, + Register areg, string operands> + : BinOpAI { + let Uses = [areg, EFLAGS]; +} + +// BinOpAI_F - Instructions like "cmp %eax, %eax, imm", that imp-def EFLAGS. +class BinOpAI_F opcode, string mnemonic, X86TypeInfo typeinfo, + Register areg, string operands> + : BinOpAI { + let Defs = [EFLAGS]; +} + +/// ArithBinOp_RF - This is an arithmetic binary operator where the pattern is +/// defined with "(set GPR:$dst, EFLAGS, (...". +/// +/// It would be nice to get rid of the second and third argument here, but +/// tblgen can't handle dependent type references aggressively enough: PR8330 +multiclass ArithBinOp_RF BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, + string mnemonic, Format RegMRM, Format MemMRM, + SDNode opnodeflag, SDNode opnode, + bit CommutableRR, bit ConvertibleToThreeAddress> { + let Defs = [EFLAGS] in { + let Constraints = "$src1 = $dst" in { + let isCommutable = CommutableRR in { + def NAME#8rr : BinOpRR_RF; + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { + def NAME#16rr : BinOpRR_RF; + def NAME#32rr : BinOpRR_RF; + def NAME#64rr : BinOpRR_RF; + } // isConvertibleToThreeAddress + } // isCommutable + + def NAME#8rr_REV : BinOpRR_Rev, FoldGenData; + def NAME#16rr_REV : BinOpRR_Rev, FoldGenData; + def NAME#32rr_REV : BinOpRR_Rev, FoldGenData; + def NAME#64rr_REV : BinOpRR_Rev, FoldGenData; + + def NAME#8rm : BinOpRM_RF; + def NAME#16rm : BinOpRM_RF; + def NAME#32rm : BinOpRM_RF; + def NAME#64rm : BinOpRM_RF; + + def NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>; + + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { + // NOTE: These are order specific, we want the ri8 forms to be listed + // first so that they are slightly preferred to the ri forms. + def NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>; + def NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>; + def NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>; + + def NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>; + def NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>; + def NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>; + } + } // Constraints = "$src1 = $dst" + + let mayLoad = 1, mayStore = 1 in { + def NAME#8mr : BinOpMR_RMW; + def NAME#16mr : BinOpMR_RMW; + def NAME#32mr : BinOpMR_RMW; + def NAME#64mr : BinOpMR_RMW; + } + + // NOTE: These are order specific, we want the mi8 forms to be listed + // first so that they are slightly preferred to the mi forms. + def NAME#16mi8 : BinOpMI8_RMW; + def NAME#32mi8 : BinOpMI8_RMW; + let Predicates = [In64BitMode] in + def NAME#64mi8 : BinOpMI8_RMW; + + def NAME#8mi : BinOpMI_RMW<0x80, mnemonic, Xi8 , opnode, MemMRM>; + def NAME#16mi : BinOpMI_RMW<0x80, mnemonic, Xi16, opnode, MemMRM>; + def NAME#32mi : BinOpMI_RMW<0x80, mnemonic, Xi32, opnode, MemMRM>; + let Predicates = [In64BitMode] in + def NAME#64mi32 : BinOpMI_RMW<0x80, mnemonic, Xi64, opnode, MemMRM>; + + // These are for the disassembler since 0x82 opcode behaves like 0x80, but + // not in 64-bit mode. + let Predicates = [Not64BitMode], isCodeGenOnly = 1, ForceDisassemble = 1, + hasSideEffects = 0 in { + let Constraints = "$src1 = $dst" in + def NAME#8ri8 : BinOpRI8_RF<0x82, mnemonic, Xi8, null_frag, RegMRM>; + let mayLoad = 1, mayStore = 1 in + def NAME#8mi8 : BinOpMI8_RMW; + } + } // Defs = [EFLAGS] + + def NAME#8i8 : BinOpAI; + def NAME#16i16 : BinOpAI; + def NAME#32i32 : BinOpAI; + def NAME#64i32 : BinOpAI; +} + +/// ArithBinOp_RFF - This is an arithmetic binary operator where the pattern is +/// defined with "(set GPR:$dst, EFLAGS, (node LHS, RHS, EFLAGS))" like ADC and +/// SBB. +/// +/// It would be nice to get rid of the second and third argument here, but +/// tblgen can't handle dependent type references aggressively enough: PR8330 +multiclass ArithBinOp_RFF BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, + string mnemonic, Format RegMRM, Format MemMRM, + SDNode opnode, bit CommutableRR, + bit ConvertibleToThreeAddress> { + let Uses = [EFLAGS], Defs = [EFLAGS] in { + let Constraints = "$src1 = $dst" in { + let isCommutable = CommutableRR in { + def NAME#8rr : BinOpRR_RFF; + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { + def NAME#16rr : BinOpRR_RFF; + def NAME#32rr : BinOpRR_RFF; + def NAME#64rr : BinOpRR_RFF; + } // isConvertibleToThreeAddress + } // isCommutable + + def NAME#8rr_REV : BinOpRR_RFF_Rev, FoldGenData; + def NAME#16rr_REV : BinOpRR_RFF_Rev, FoldGenData; + def NAME#32rr_REV : BinOpRR_RFF_Rev, FoldGenData; + def NAME#64rr_REV : BinOpRR_RFF_Rev, FoldGenData; + + def NAME#8rm : BinOpRM_RFF; + def NAME#16rm : BinOpRM_RFF; + def NAME#32rm : BinOpRM_RFF; + def NAME#64rm : BinOpRM_RFF; + + def NAME#8ri : BinOpRI_RFF<0x80, mnemonic, Xi8 , opnode, RegMRM>; + + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { + // NOTE: These are order specific, we want the ri8 forms to be listed + // first so that they are slightly preferred to the ri forms. + def NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, opnode, RegMRM>; + def NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, opnode, RegMRM>; + def NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, opnode, RegMRM>; + + def NAME#16ri : BinOpRI_RFF<0x80, mnemonic, Xi16, opnode, RegMRM>; + def NAME#32ri : BinOpRI_RFF<0x80, mnemonic, Xi32, opnode, RegMRM>; + def NAME#64ri32: BinOpRI_RFF<0x80, mnemonic, Xi64, opnode, RegMRM>; + } + } // Constraints = "$src1 = $dst" + + def NAME#8mr : BinOpMR_RMW_FF; + def NAME#16mr : BinOpMR_RMW_FF; + def NAME#32mr : BinOpMR_RMW_FF; + def NAME#64mr : BinOpMR_RMW_FF; + + // NOTE: These are order specific, we want the mi8 forms to be listed + // first so that they are slightly preferred to the mi forms. + def NAME#16mi8 : BinOpMI8_RMW_FF; + def NAME#32mi8 : BinOpMI8_RMW_FF; + let Predicates = [In64BitMode] in + def NAME#64mi8 : BinOpMI8_RMW_FF; + + def NAME#8mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi8 , opnode, MemMRM>; + def NAME#16mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi16, opnode, MemMRM>; + def NAME#32mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi32, opnode, MemMRM>; + let Predicates = [In64BitMode] in + def NAME#64mi32 : BinOpMI_RMW_FF<0x80, mnemonic, Xi64, opnode, MemMRM>; + + // These are for the disassembler since 0x82 opcode behaves like 0x80, but + // not in 64-bit mode. + let Predicates = [Not64BitMode], isCodeGenOnly = 1, ForceDisassemble = 1, + hasSideEffects = 0 in { + let Constraints = "$src1 = $dst" in + def NAME#8ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi8, null_frag, RegMRM>; + let mayLoad = 1, mayStore = 1 in + def NAME#8mi8 : BinOpMI8_RMW_FF; + } + } // Uses = [EFLAGS], Defs = [EFLAGS] + + def NAME#8i8 : BinOpAI_RFF; + def NAME#16i16 : BinOpAI_RFF; + def NAME#32i32 : BinOpAI_RFF; + def NAME#64i32 : BinOpAI_RFF; +} + +/// ArithBinOp_F - This is an arithmetic binary operator where the pattern is +/// defined with "(set EFLAGS, (...". It would be really nice to find a way +/// to factor this with the other ArithBinOp_*. +/// +multiclass ArithBinOp_F BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, + string mnemonic, Format RegMRM, Format MemMRM, + SDNode opnode, + bit CommutableRR, bit ConvertibleToThreeAddress> { + let Defs = [EFLAGS] in { + let isCommutable = CommutableRR in { + def NAME#8rr : BinOpRR_F; + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { + def NAME#16rr : BinOpRR_F; + def NAME#32rr : BinOpRR_F; + def NAME#64rr : BinOpRR_F; + } + } // isCommutable + + def NAME#8rr_REV : BinOpRR_F_Rev, FoldGenData; + def NAME#16rr_REV : BinOpRR_F_Rev, FoldGenData; + def NAME#32rr_REV : BinOpRR_F_Rev, FoldGenData; + def NAME#64rr_REV : BinOpRR_F_Rev, FoldGenData; + + def NAME#8rm : BinOpRM_F; + def NAME#16rm : BinOpRM_F; + def NAME#32rm : BinOpRM_F; + def NAME#64rm : BinOpRM_F; + + def NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>; + + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { + // NOTE: These are order specific, we want the ri8 forms to be listed + // first so that they are slightly preferred to the ri forms. + def NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>; + def NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>; + def NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>; + + def NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>; + def NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>; + def NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>; + } + + def NAME#8mr : BinOpMR_F; + def NAME#16mr : BinOpMR_F; + def NAME#32mr : BinOpMR_F; + def NAME#64mr : BinOpMR_F; + + // NOTE: These are order specific, we want the mi8 forms to be listed + // first so that they are slightly preferred to the mi forms. + def NAME#16mi8 : BinOpMI8_F; + def NAME#32mi8 : BinOpMI8_F; + let Predicates = [In64BitMode] in + def NAME#64mi8 : BinOpMI8_F; + + def NAME#8mi : BinOpMI_F<0x80, mnemonic, Xi8 , opnode, MemMRM>; + def NAME#16mi : BinOpMI_F<0x80, mnemonic, Xi16, opnode, MemMRM>; + def NAME#32mi : BinOpMI_F<0x80, mnemonic, Xi32, opnode, MemMRM>; + let Predicates = [In64BitMode] in + def NAME#64mi32 : BinOpMI_F<0x80, mnemonic, Xi64, opnode, MemMRM>; + + // These are for the disassembler since 0x82 opcode behaves like 0x80, but + // not in 64-bit mode. + let Predicates = [Not64BitMode], isCodeGenOnly = 1, ForceDisassemble = 1, + hasSideEffects = 0 in { + def NAME#8ri8 : BinOpRI8_F<0x82, mnemonic, Xi8, null_frag, RegMRM>; + let mayLoad = 1 in + def NAME#8mi8 : BinOpMI8_F; + } + } // Defs = [EFLAGS] + + def NAME#8i8 : BinOpAI_F; + def NAME#16i16 : BinOpAI_F; + def NAME#32i32 : BinOpAI_F; + def NAME#64i32 : BinOpAI_F; +} + + +defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m, + X86and_flag, and, 1, 0>; +defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m, + X86or_flag, or, 1, 0>; +defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m, + X86xor_flag, xor, 1, 0>; +defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m, + X86add_flag, add, 1, 1>; +let isCompare = 1 in { +defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m, + X86sub_flag, sub, 0, 0>; +} + +// Arithmetic. +defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag, + 1, 0>; +defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag, + 0, 0>; + +let isCompare = 1 in { +defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>; +} + + +//===----------------------------------------------------------------------===// +// Semantically, test instructions are similar like AND, except they don't +// generate a result. From an encoding perspective, they are very different: +// they don't have all the usual imm8 and REV forms, and are encoded into a +// different space. +def X86testpat : PatFrag<(ops node:$lhs, node:$rhs), + (X86cmp (and_su node:$lhs, node:$rhs), 0)>; + +let isCompare = 1 in { + let Defs = [EFLAGS] in { + let isCommutable = 1 in { + def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat>; + def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat>; + def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat>; + def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat>; + } // isCommutable + + def TEST8mr : BinOpMR_F<0x84, "test", Xi8 , X86testpat>; + def TEST16mr : BinOpMR_F<0x84, "test", Xi16, X86testpat>; + def TEST32mr : BinOpMR_F<0x84, "test", Xi32, X86testpat>; + def TEST64mr : BinOpMR_F<0x84, "test", Xi64, X86testpat>; + + def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>; + def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>; + def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>; + let Predicates = [In64BitMode] in + def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>; + + def TEST8mi : BinOpMI_F<0xF6, "test", Xi8 , X86testpat, MRM0m>; + def TEST16mi : BinOpMI_F<0xF6, "test", Xi16, X86testpat, MRM0m>; + def TEST32mi : BinOpMI_F<0xF6, "test", Xi32, X86testpat, MRM0m>; + let Predicates = [In64BitMode] in + def TEST64mi32 : BinOpMI_F<0xF6, "test", Xi64, X86testpat, MRM0m>; + } // Defs = [EFLAGS] + + def TEST8i8 : BinOpAI_F<0xA8, "test", Xi8 , AL, + "{$src, %al|al, $src}">; + def TEST16i16 : BinOpAI_F<0xA8, "test", Xi16, AX, + "{$src, %ax|ax, $src}">; + def TEST32i32 : BinOpAI_F<0xA8, "test", Xi32, EAX, + "{$src, %eax|eax, $src}">; + def TEST64i32 : BinOpAI_F<0xA8, "test", Xi64, RAX, + "{$src, %rax|rax, $src}">; +} // isCompare + +//===----------------------------------------------------------------------===// +// ANDN Instruction +// +multiclass bmi_andn { + def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>, + Sched<[WriteALU]>; + def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, EFLAGS, + (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>, + Sched<[WriteALULd, ReadAfterLd]>; +} + +// Complexity is reduced to give and with immediate a chance to match first. +let Predicates = [HasBMI], Defs = [EFLAGS], AddedComplexity = -6 in { + defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8PS, VEX_4V; + defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8PS, VEX_4V, VEX_W; +} + +let Predicates = [HasBMI], AddedComplexity = -6 in { + def : Pat<(and (not GR32:$src1), GR32:$src2), + (ANDN32rr GR32:$src1, GR32:$src2)>; + def : Pat<(and (not GR64:$src1), GR64:$src2), + (ANDN64rr GR64:$src1, GR64:$src2)>; + def : Pat<(and (not GR32:$src1), (loadi32 addr:$src2)), + (ANDN32rm GR32:$src1, addr:$src2)>; + def : Pat<(and (not GR64:$src1), (loadi64 addr:$src2)), + (ANDN64rm GR64:$src1, addr:$src2)>; +} + +//===----------------------------------------------------------------------===// +// MULX Instruction +// +multiclass bmi_mulx { +let hasSideEffects = 0 in { + let isCommutable = 1 in + def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src), + !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"), + []>, T8XD, VEX_4V, Sched<[sched, WriteIMulH]>; + + let mayLoad = 1 in + def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src), + !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"), + []>, T8XD, VEX_4V, Sched<[sched.Folded, WriteIMulH]>; +} +} + +let Predicates = [HasBMI2] in { + let Uses = [EDX] in + defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, WriteIMul>; + let Uses = [RDX] in + defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteIMul64>, VEX_W; +} + +//===----------------------------------------------------------------------===// +// ADCX and ADOX Instructions +// +let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS], + Constraints = "$src1 = $dst", AddedComplexity = 10 in { + let SchedRW = [WriteADC] in { + def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2), + "adcx{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, EFLAGS, + (X86adc_flag GR32:$src1, GR32:$src2, EFLAGS))]>, T8PD; + def ADCX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), + "adcx{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, EFLAGS, + (X86adc_flag GR64:$src1, GR64:$src2, EFLAGS))]>, T8PD; + + // We don't have patterns for ADOX yet. + let hasSideEffects = 0 in { + def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2), + "adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS; + + def ADOX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), + "adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS; + } // hasSideEffects = 0 + } // SchedRW + + let mayLoad = 1, SchedRW = [WriteADCLd, ReadAfterLd] in { + def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$src1, i32mem:$src2), + "adcx{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, EFLAGS, + (X86adc_flag GR32:$src1, (loadi32 addr:$src2), EFLAGS))]>, + T8PD; + + def ADCX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$src1, i64mem:$src2), + "adcx{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, EFLAGS, + (X86adc_flag GR64:$src1, (loadi64 addr:$src2), EFLAGS))]>, + T8PD; + + // We don't have patterns for ADOX yet. + let hasSideEffects = 0 in { + def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$src1, i32mem:$src2), + "adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS; + + def ADOX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$src1, i64mem:$src2), + "adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS; + } // hasSideEffects = 0 + } // mayLoad = 1, SchedRW = [WriteADCLd] +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrCMovSetCC.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrCMovSetCC.td new file mode 100644 index 0000000..eda4ba5 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrCMovSetCC.td @@ -0,0 +1,116 @@ +//===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 conditional move and set on condition +// instructions. +// +//===----------------------------------------------------------------------===// + + +// CMOV instructions. +multiclass CMOV opc, string Mnemonic, X86FoldableSchedWrite Sched, + PatLeaf CondNode> { + let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", + isCommutable = 1, SchedRW = [Sched] in { + def NAME#16rr + : I, + TB, OpSize16; + def NAME#32rr + : I, + TB, OpSize32; + def NAME#64rr + :RI, TB; + } + + let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", + SchedRW = [Sched.Folded, ReadAfterLd] in { + def NAME#16rm + : I, TB, OpSize16; + def NAME#32rm + : I, TB, OpSize32; + def NAME#64rm + :RI, TB; + } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst" +} // end multiclass + + +// Conditional Moves. +defm CMOVO : CMOV<0x40, "cmovo" , WriteCMOV, X86_COND_O>; +defm CMOVNO : CMOV<0x41, "cmovno", WriteCMOV, X86_COND_NO>; +defm CMOVB : CMOV<0x42, "cmovb" , WriteCMOV, X86_COND_B>; +defm CMOVAE : CMOV<0x43, "cmovae", WriteCMOV, X86_COND_AE>; +defm CMOVE : CMOV<0x44, "cmove" , WriteCMOV, X86_COND_E>; +defm CMOVNE : CMOV<0x45, "cmovne", WriteCMOV, X86_COND_NE>; +defm CMOVBE : CMOV<0x46, "cmovbe", WriteCMOV2, X86_COND_BE>; +defm CMOVA : CMOV<0x47, "cmova" , WriteCMOV2, X86_COND_A>; +defm CMOVS : CMOV<0x48, "cmovs" , WriteCMOV, X86_COND_S>; +defm CMOVNS : CMOV<0x49, "cmovns", WriteCMOV, X86_COND_NS>; +defm CMOVP : CMOV<0x4A, "cmovp" , WriteCMOV, X86_COND_P>; +defm CMOVNP : CMOV<0x4B, "cmovnp", WriteCMOV, X86_COND_NP>; +defm CMOVL : CMOV<0x4C, "cmovl" , WriteCMOV, X86_COND_L>; +defm CMOVGE : CMOV<0x4D, "cmovge", WriteCMOV, X86_COND_GE>; +defm CMOVLE : CMOV<0x4E, "cmovle", WriteCMOV, X86_COND_LE>; +defm CMOVG : CMOV<0x4F, "cmovg" , WriteCMOV, X86_COND_G>; + + +// SetCC instructions. +multiclass SETCC opc, string Mnemonic, PatLeaf OpNode> { + let Uses = [EFLAGS] in { + def r : I, + TB, Sched<[WriteSETCC]>; + def m : I, + TB, Sched<[WriteSETCCStore]>; + } // Uses = [EFLAGS] +} + +defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set +defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set +defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than +defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal +defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to +defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to +defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal +defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than +defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set +defm SETNS : SETCC<0x99, "setns", X86_COND_NS>; // is not signed +defm SETP : SETCC<0x9A, "setp", X86_COND_P>; // is parity bit set +defm SETNP : SETCC<0x9B, "setnp", X86_COND_NP>; // is parity bit not set +defm SETL : SETCC<0x9C, "setl", X86_COND_L>; // signed less than +defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>; // signed greater or equal +defm SETLE : SETCC<0x9E, "setle", X86_COND_LE>; // signed less than or equal +defm SETG : SETCC<0x9F, "setg", X86_COND_G>; // signed greater than + +// SALC is an undocumented instruction. Information for this instruction can be found +// here http://www.rcollins.org/secrets/opcodes/SALC.html +// Set AL if carry. +let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in { + def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>, Requires<[Not64BitMode]>; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrCompiler.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrCompiler.td new file mode 100644 index 0000000..76b93bd --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrCompiler.td @@ -0,0 +1,2103 @@ +//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the various pseudo instructions used by the compiler, +// as well as Pat patterns used during instruction selection. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Pattern Matching Support + +def GetLo32XForm : SDNodeXFormgetZExtValue(), SDLoc(N)); +}]>; + +def GetLo8XForm : SDNodeXFormgetZExtValue(), SDLoc(N)); +}]>; + + +//===----------------------------------------------------------------------===// +// Random Pseudo Instructions. + +// PIC base construction. This expands to code that looks like this: +// call $next_inst +// popl %destreg" +let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP], + SchedRW = [WriteJump] in + def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), + "", []>; + +// 64-bit large code model PIC base construction. +let hasSideEffects = 0, mayLoad = 1, isNotDuplicable = 1, SchedRW = [WriteJump] in + def MOVGOT64r : PseudoI<(outs GR64:$reg), + (ins GR64:$scratch, i64i32imm_pcrel:$got), []>; + +// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into +// a stack adjustment and the codegen must know that they may modify the stack +// pointer before prolog-epilog rewriting occurs. +// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become +// sub / add which can clobber EFLAGS. +let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in { +def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), + (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), + "#ADJCALLSTACKDOWN", []>, Requires<[NotLP64]>; +def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), + "#ADJCALLSTACKUP", + [(X86callseq_end timm:$amt1, timm:$amt2)]>, + Requires<[NotLP64]>; +} +def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), + (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>; + + +// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into +// a stack adjustment and the codegen must know that they may modify the stack +// pointer before prolog-epilog rewriting occurs. +// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become +// sub / add which can clobber EFLAGS. +let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in { +def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), + (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), + "#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>; +def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), + "#ADJCALLSTACKUP", + [(X86callseq_end timm:$amt1, timm:$amt2)]>, + Requires<[IsLP64]>; +} +def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), + (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>; + +let SchedRW = [WriteSystem] in { + +// x86-64 va_start lowering magic. +let usesCustomInserter = 1, Defs = [EFLAGS] in { +def VASTART_SAVE_XMM_REGS : I<0, Pseudo, + (outs), + (ins GR8:$al, + i64imm:$regsavefi, i64imm:$offset, + variable_ops), + "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", + [(X86vastart_save_xmm_regs GR8:$al, + imm:$regsavefi, + imm:$offset), + (implicit EFLAGS)]>; + +// The VAARG_64 pseudo-instruction takes the address of the va_list, +// and places the address of the next argument into a register. +let Defs = [EFLAGS] in +def VAARG_64 : I<0, Pseudo, + (outs GR64:$dst), + (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), + "#VAARG_64 $dst, $ap, $size, $mode, $align", + [(set GR64:$dst, + (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), + (implicit EFLAGS)]>; + + +// When using segmented stacks these are lowered into instructions which first +// check if the current stacklet has enough free memory. If it does, memory is +// allocated by bumping the stack pointer. Otherwise memory is allocated from +// the heap. + +let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in +def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), + "# variable sized alloca for segmented stacks", + [(set GR32:$dst, + (X86SegAlloca GR32:$size))]>, + Requires<[NotLP64]>; + +let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in +def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), + "# variable sized alloca for segmented stacks", + [(set GR64:$dst, + (X86SegAlloca GR64:$size))]>, + Requires<[In64BitMode]>; +} + +// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows +// targets. These calls are needed to probe the stack when allocating more than +// 4k bytes in one go. Touching the stack at 4K increments is necessary to +// ensure that the guard pages used by the OS virtual memory manager are +// allocated in correct sequence. +// The main point of having separate instruction are extra unmodelled effects +// (compared to ordinary calls) like stack pointer change. + +let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in +def WIN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size), + "# dynamic stack allocation", + [(X86WinAlloca GR32:$size)]>, + Requires<[NotLP64]>; + +let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in +def WIN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size), + "# dynamic stack allocation", + [(X86WinAlloca GR64:$size)]>, + Requires<[In64BitMode]>; +} // SchedRW + +// These instructions XOR the frame pointer into a GPR. They are used in some +// stack protection schemes. These are post-RA pseudos because we only know the +// frame register after register allocation. +let Constraints = "$src = $dst", isPseudo = 1, Defs = [EFLAGS] in { + def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src), + "xorl\t$$FP, $src", []>, + Requires<[NotLP64]>, Sched<[WriteALU]>; + def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src), + "xorq\t$$FP $src", []>, + Requires<[In64BitMode]>, Sched<[WriteALU]>; +} + +//===----------------------------------------------------------------------===// +// EH Pseudo Instructions +// +let SchedRW = [WriteSystem] in { +let isTerminator = 1, isReturn = 1, isBarrier = 1, + hasCtrlDep = 1, isCodeGenOnly = 1 in { +def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), + "ret\t#eh_return, addr: $addr", + [(X86ehret GR32:$addr)]>, Sched<[WriteJumpLd]>; + +} + +let isTerminator = 1, isReturn = 1, isBarrier = 1, + hasCtrlDep = 1, isCodeGenOnly = 1 in { +def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), + "ret\t#eh_return, addr: $addr", + [(X86ehret GR64:$addr)]>, Sched<[WriteJumpLd]>; + +} + +let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, + isCodeGenOnly = 1, isReturn = 1 in { + def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>; + + // CATCHRET needs a custom inserter for SEH. + let usesCustomInserter = 1 in + def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from), + "# CATCHRET", + [(catchret bb:$dst, bb:$from)]>; +} + +let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1, + usesCustomInserter = 1 in +def CATCHPAD : I<0, Pseudo, (outs), (ins), "# CATCHPAD", [(catchpad)]>; + +// This instruction is responsible for re-establishing stack pointers after an +// exception has been caught and we are rejoining normal control flow in the +// parent function or funclet. It generally sets ESP and EBP, and optionally +// ESI. It is only needed for 32-bit WinEH, as the runtime restores CSRs for us +// elsewhere. +let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in +def EH_RESTORE : I<0, Pseudo, (outs), (ins), "# EH_RESTORE", []>; + +let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, + usesCustomInserter = 1 in { + def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), + "#EH_SJLJ_SETJMP32", + [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, + Requires<[Not64BitMode]>; + def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), + "#EH_SJLJ_SETJMP64", + [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, + Requires<[In64BitMode]>; + let isTerminator = 1 in { + def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), + "#EH_SJLJ_LONGJMP32", + [(X86eh_sjlj_longjmp addr:$buf)]>, + Requires<[Not64BitMode]>; + def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), + "#EH_SJLJ_LONGJMP64", + [(X86eh_sjlj_longjmp addr:$buf)]>, + Requires<[In64BitMode]>; + } +} + +let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { + def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), + "#EH_SjLj_Setup\t$dst", []>; +} +} // SchedRW + +//===----------------------------------------------------------------------===// +// Pseudo instructions used by unwind info. +// +let isPseudo = 1, SchedRW = [WriteSystem] in { + def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), + "#SEH_PushReg $reg", []>; + def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), + "#SEH_SaveReg $reg, $dst", []>; + def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), + "#SEH_SaveXMM $reg, $dst", []>; + def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), + "#SEH_StackAlloc $size", []>; + def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), + "#SEH_SetFrame $reg, $offset", []>; + def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), + "#SEH_PushFrame $mode", []>; + def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), + "#SEH_EndPrologue", []>; + def SEH_Epilogue : I<0, Pseudo, (outs), (ins), + "#SEH_Epilogue", []>; +} + +//===----------------------------------------------------------------------===// +// Pseudo instructions used by segmented stacks. +// + +// This is lowered into a RET instruction by MCInstLower. We need +// this so that we don't have to have a MachineBasicBlock which ends +// with a RET and also has successors. +let isPseudo = 1, SchedRW = [WriteJumpLd] in { +def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>; + +// This instruction is lowered to a RET followed by a MOV. The two +// instructions are not generated on a higher level since then the +// verifier sees a MachineBasicBlock ending with a non-terminator. +def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>; +} + +//===----------------------------------------------------------------------===// +// Alias Instructions +//===----------------------------------------------------------------------===// + +// Alias instruction mapping movr0 to xor. +// FIXME: remove when we can teach regalloc that xor reg, reg is ok. +let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, + isPseudo = 1, AddedComplexity = 10 in +def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", + [(set GR32:$dst, 0)]>, Sched<[WriteZero]>; + +// Other widths can also make use of the 32-bit xor, which may have a smaller +// encoding and avoid partial register updates. +let AddedComplexity = 10 in { +def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; +def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; +def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>; +} + +let Predicates = [OptForSize, Not64BitMode], + AddedComplexity = 10 in { + let SchedRW = [WriteALU] in { + // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC, + // which only require 3 bytes compared to MOV32ri which requires 5. + let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in { + def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", + [(set GR32:$dst, 1)]>; + def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", + [(set GR32:$dst, -1)]>; + } + } // SchedRW + + // MOV16ri is 4 bytes, so the instructions above are smaller. + def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>; + def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>; +} + +let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5, + SchedRW = [WriteALU] in { +// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1. +def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "", + [(set GR32:$dst, i32immSExt8:$src)]>, + Requires<[OptForMinSize, NotWin64WithoutFP]>; +def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", + [(set GR64:$dst, i64immSExt8:$src)]>, + Requires<[OptForMinSize, NotWin64WithoutFP]>; +} + +// Materialize i64 constant where top 32-bits are zero. This could theoretically +// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however +// that would make it more difficult to rematerialize. +let isReMaterializable = 1, isAsCheapAsAMove = 1, + isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteMove] in +def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", []>; + +// This 64-bit pseudo-move can be used for both a 64-bit constant that is +// actually the zero-extension of a 32-bit constant and for labels in the +// x86-64 small code model. +def mov64imm32 : ComplexPattern; + +let AddedComplexity = 1 in +def : Pat<(i64 mov64imm32:$src), + (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>; + +// Use sbb to materialize carry bit. +let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in { +// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. +// However, Pat<> can't replicate the destination reg into the inputs of the +// result. +def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "", + [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; +def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "", + [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; +def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", + [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; +def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", + [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; +} // isCodeGenOnly + + +def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C16r)>; +def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C32r)>; +def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C64r)>; + +def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C16r)>; +def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C32r)>; +def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C64r)>; + +// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and +// will be eliminated and that the sbb can be extended up to a wider type. When +// this happens, it is great. However, if we are left with an 8-bit sbb and an +// and, we might as well just match it as a setb. +def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), + (SETBr)>; + +// (add OP, SETB) -> (adc OP, 0) +def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op), + (ADC8ri GR8:$op, 0)>; +def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op), + (ADC32ri8 GR32:$op, 0)>; +def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op), + (ADC64ri8 GR64:$op, 0)>; + +// (sub OP, SETB) -> (sbb OP, 0) +def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)), + (SBB8ri GR8:$op, 0)>; +def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)), + (SBB32ri8 GR32:$op, 0)>; +def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)), + (SBB64ri8 GR64:$op, 0)>; + +// (sub OP, SETCC_CARRY) -> (adc OP, 0) +def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))), + (ADC8ri GR8:$op, 0)>; +def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))), + (ADC32ri8 GR32:$op, 0)>; +def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))), + (ADC64ri8 GR64:$op, 0)>; + +//===----------------------------------------------------------------------===// +// String Pseudo Instructions +// +let SchedRW = [WriteMicrocoded] in { +let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { +def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", + [(X86rep_movs i8)]>, REP, + Requires<[Not64BitMode]>; +def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", + [(X86rep_movs i16)]>, REP, OpSize16, + Requires<[Not64BitMode]>; +def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", + [(X86rep_movs i32)]>, REP, OpSize32, + Requires<[Not64BitMode]>; +} + +let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { +def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", + [(X86rep_movs i8)]>, REP, + Requires<[In64BitMode]>; +def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", + [(X86rep_movs i16)]>, REP, OpSize16, + Requires<[In64BitMode]>; +def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", + [(X86rep_movs i32)]>, REP, OpSize32, + Requires<[In64BitMode]>; +def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", + [(X86rep_movs i64)]>, REP, + Requires<[In64BitMode]>; +} + +// FIXME: Should use "(X86rep_stos AL)" as the pattern. +let Defs = [ECX,EDI], isCodeGenOnly = 1 in { + let Uses = [AL,ECX,EDI] in + def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", + [(X86rep_stos i8)]>, REP, + Requires<[Not64BitMode]>; + let Uses = [AX,ECX,EDI] in + def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", + [(X86rep_stos i16)]>, REP, OpSize16, + Requires<[Not64BitMode]>; + let Uses = [EAX,ECX,EDI] in + def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", + [(X86rep_stos i32)]>, REP, OpSize32, + Requires<[Not64BitMode]>; +} + +let Defs = [RCX,RDI], isCodeGenOnly = 1 in { + let Uses = [AL,RCX,RDI] in + def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", + [(X86rep_stos i8)]>, REP, + Requires<[In64BitMode]>; + let Uses = [AX,RCX,RDI] in + def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", + [(X86rep_stos i16)]>, REP, OpSize16, + Requires<[In64BitMode]>; + let Uses = [RAX,RCX,RDI] in + def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", + [(X86rep_stos i32)]>, REP, OpSize32, + Requires<[In64BitMode]>; + + let Uses = [RAX,RCX,RDI] in + def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", + [(X86rep_stos i64)]>, REP, + Requires<[In64BitMode]>; +} +} // SchedRW + +//===----------------------------------------------------------------------===// +// Thread Local Storage Instructions +// +let SchedRW = [WriteSystem] in { + +// ELF TLS Support +// All calls clobber the non-callee saved registers. ESP is marked as +// a use to prevent stack-pointer assignments that appear immediately +// before calls from potentially appearing dead. +let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, + ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, + MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, + XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, + XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], + usesCustomInserter = 1, Uses = [ESP, SSP] in { +def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), + "# TLS_addr32", + [(X86tlsaddr tls32addr:$sym)]>, + Requires<[Not64BitMode]>; +def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), + "# TLS_base_addr32", + [(X86tlsbaseaddr tls32baseaddr:$sym)]>, + Requires<[Not64BitMode]>; +} + +// All calls clobber the non-callee saved registers. RSP is marked as +// a use to prevent stack-pointer assignments that appear immediately +// before calls from potentially appearing dead. +let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, + FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, + ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, + MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, + XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, + XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], + usesCustomInserter = 1, Uses = [RSP, SSP] in { +def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), + "# TLS_addr64", + [(X86tlsaddr tls64addr:$sym)]>, + Requires<[In64BitMode]>; +def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), + "# TLS_base_addr64", + [(X86tlsbaseaddr tls64baseaddr:$sym)]>, + Requires<[In64BitMode]>; +} + +// Darwin TLS Support +// For i386, the address of the thunk is passed on the stack, on return the +// address of the variable is in %eax. %ecx is trashed during the function +// call. All other registers are preserved. +let Defs = [EAX, ECX, EFLAGS, DF], + Uses = [ESP, SSP], + usesCustomInserter = 1 in +def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), + "# TLSCall_32", + [(X86TLSCall addr:$sym)]>, + Requires<[Not64BitMode]>; + +// For x86_64, the address of the thunk is passed in %rdi, but the +// pseudo directly use the symbol, so do not add an implicit use of +// %rdi. The lowering will do the right thing with RDI. +// On return the address of the variable is in %rax. All other +// registers are preserved. +let Defs = [RAX, EFLAGS, DF], + Uses = [RSP, SSP], + usesCustomInserter = 1 in +def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), + "# TLSCall_64", + [(X86TLSCall addr:$sym)]>, + Requires<[In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Conditional Move Pseudo Instructions + +// CMOV* - Used to implement the SELECT DAG operation. Expanded after +// instruction selection into a branch sequence. +multiclass CMOVrr_PSEUDO { + def CMOV#NAME : I<0, Pseudo, + (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond), + "#CMOV_"#NAME#" PSEUDO!", + [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond, + EFLAGS)))]>; +} + +let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in { + // X86 doesn't have 8-bit conditional moves. Use a customInserter to + // emit control flow. An alternative to this is to mark i8 SELECT as Promote, + // however that requires promoting the operands, and can induce additional + // i8 register pressure. + defm _GR8 : CMOVrr_PSEUDO; + + let Predicates = [NoCMov] in { + defm _GR32 : CMOVrr_PSEUDO; + defm _GR16 : CMOVrr_PSEUDO; + } // Predicates = [NoCMov] + + // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no + // SSE1/SSE2. + let Predicates = [FPStackf32] in + defm _RFP32 : CMOVrr_PSEUDO; + + let Predicates = [FPStackf64] in + defm _RFP64 : CMOVrr_PSEUDO; + + defm _RFP80 : CMOVrr_PSEUDO; + + defm _FR32 : CMOVrr_PSEUDO; + defm _FR64 : CMOVrr_PSEUDO; + defm _F128 : CMOVrr_PSEUDO; + defm _V4F32 : CMOVrr_PSEUDO; + defm _V2F64 : CMOVrr_PSEUDO; + defm _V2I64 : CMOVrr_PSEUDO; + defm _V8F32 : CMOVrr_PSEUDO; + defm _V4F64 : CMOVrr_PSEUDO; + defm _V4I64 : CMOVrr_PSEUDO; + defm _V8I64 : CMOVrr_PSEUDO; + defm _V8F64 : CMOVrr_PSEUDO; + defm _V16F32 : CMOVrr_PSEUDO; + defm _V8I1 : CMOVrr_PSEUDO; + defm _V16I1 : CMOVrr_PSEUDO; + defm _V32I1 : CMOVrr_PSEUDO; + defm _V64I1 : CMOVrr_PSEUDO; +} // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] + +//===----------------------------------------------------------------------===// +// Normal-Instructions-With-Lock-Prefix Pseudo Instructions +//===----------------------------------------------------------------------===// + +// FIXME: Use normal instructions and add lock prefix dynamically. + +// Memory barriers + +// TODO: Get this to fold the constant into the instruction. +let isCodeGenOnly = 1, Defs = [EFLAGS] in +def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero), + "or{l}\t{$zero, $dst|$dst, $zero}", []>, + Requires<[Not64BitMode]>, OpSize32, LOCK, + Sched<[WriteALULd, WriteRMW]>; + +let hasSideEffects = 1 in +def Int_MemBarrier : I<0, Pseudo, (outs), (ins), + "#MEMBARRIER", + [(X86MemBarrier)]>, Sched<[WriteLoad]>; + +// RegOpc corresponds to the mr version of the instruction +// ImmOpc corresponds to the mi version of the instruction +// ImmOpc8 corresponds to the mi8 version of the instruction +// ImmMod corresponds to the instruction format of the mi and mi8 versions +multiclass LOCK_ArithBinOp RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, + Format ImmMod, SDNode Op, string mnemonic> { +let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, + SchedRW = [WriteALULd, WriteRMW] in { + +def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, + RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, + MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), + !strconcat(mnemonic, "{b}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK; + +def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, + RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, + MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), + !strconcat(mnemonic, "{w}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>, + OpSize16, LOCK; + +def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, + RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, + MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), + !strconcat(mnemonic, "{l}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>, + OpSize32, LOCK; + +def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, + RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, + MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), + !strconcat(mnemonic, "{q}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK; + +def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, + ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, + ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), + !strconcat(mnemonic, "{b}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK; + +def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, + ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, + ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), + !strconcat(mnemonic, "{w}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>, + OpSize16, LOCK; + +def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, + ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, + ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), + !strconcat(mnemonic, "{l}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>, + OpSize32, LOCK; + +def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, + ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, + ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), + !strconcat(mnemonic, "{q}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>, + LOCK; + +def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, + ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, + ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), + !strconcat(mnemonic, "{w}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>, + OpSize16, LOCK; + +def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, + ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, + ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), + !strconcat(mnemonic, "{l}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>, + OpSize32, LOCK; + +def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, + ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, + ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), + !strconcat(mnemonic, "{q}\t", + "{$src2, $dst|$dst, $src2}"), + [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>, + LOCK; +} + +} + +defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">; +defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">; +defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">; +defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">; +defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">; + +multiclass LOCK_ArithUnOp Opc8, bits<8> Opc, Format Form, + string frag, string mnemonic> { +let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, + SchedRW = [WriteALULd, WriteRMW] in { +def NAME#8m : I(frag # "_8") addr:$dst))]>, + LOCK; +def NAME#16m : I(frag # "_16") addr:$dst))]>, + OpSize16, LOCK; +def NAME#32m : I(frag # "_32") addr:$dst))]>, + OpSize32, LOCK; +def NAME#64m : RI(frag # "_64") addr:$dst))]>, + LOCK; +} +} + +multiclass unary_atomic_intrin { + def _8 : PatFrag<(ops node:$ptr), + (atomic_op node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i8; + }]>; + def _16 : PatFrag<(ops node:$ptr), + (atomic_op node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i16; + }]>; + def _32 : PatFrag<(ops node:$ptr), + (atomic_op node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i32; + }]>; + def _64 : PatFrag<(ops node:$ptr), + (atomic_op node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i64; + }]>; +} + +defm X86lock_inc : unary_atomic_intrin; +defm X86lock_dec : unary_atomic_intrin; + +defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "X86lock_inc", "inc">; +defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "X86lock_dec", "dec">; + +// Atomic compare and swap. +multiclass LCMPXCHG_UnOp Opc, Format Form, string mnemonic, + SDPatternOperator frag, X86MemOperand x86memop> { +let isCodeGenOnly = 1, usesCustomInserter = 1 in { + def NAME : I, TB, LOCK; +} +} + +multiclass LCMPXCHG_BinOp Opc8, bits<8> Opc, Format Form, + string mnemonic, SDPatternOperator frag> { +let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in { + let Defs = [AL, EFLAGS], Uses = [AL] in + def NAME#8 : I, TB, LOCK; + let Defs = [AX, EFLAGS], Uses = [AX] in + def NAME#16 : I, TB, OpSize16, LOCK; + let Defs = [EAX, EFLAGS], Uses = [EAX] in + def NAME#32 : I, TB, OpSize32, LOCK; + let Defs = [RAX, EFLAGS], Uses = [RAX] in + def NAME#64 : RI, TB, LOCK; +} +} + +let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], + SchedRW = [WriteALULd, WriteRMW] in { +defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", X86cas8, i64mem>; +} + +// This pseudo must be used when the frame uses RBX as +// the base pointer. Indeed, in such situation RBX is a reserved +// register and the register allocator will ignore any use/def of +// it. In other words, the register will not fix the clobbering of +// RBX that will happen when setting the arguments for the instruction. +// +// Unlike the actual related instruction, we mark that this one +// defines EBX (instead of using EBX). +// The rationale is that we will define RBX during the expansion of +// the pseudo. The argument feeding EBX is ebx_input. +// +// The additional argument, $ebx_save, is a temporary register used to +// save the value of RBX across the actual instruction. +// +// To make sure the register assigned to $ebx_save does not interfere with +// the definition of the actual instruction, we use a definition $dst which +// is tied to $rbx_save. That way, the live-range of $rbx_save spans across +// the instruction and we are sure we will have a valid register to restore +// the value of RBX. +let Defs = [EAX, EDX, EBX, EFLAGS], Uses = [EAX, ECX, EDX], + SchedRW = [WriteALULd, WriteRMW], isCodeGenOnly = 1, isPseudo = 1, + Constraints = "$ebx_save = $dst", usesCustomInserter = 1 in { +def LCMPXCHG8B_SAVE_EBX : + I<0, Pseudo, (outs GR32:$dst), + (ins i64mem:$ptr, GR32:$ebx_input, GR32:$ebx_save), + !strconcat("cmpxchg8b", "\t$ptr"), + [(set GR32:$dst, (X86cas8save_ebx addr:$ptr, GR32:$ebx_input, + GR32:$ebx_save))]>; +} + + +let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], + Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in { +defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b", + X86cas16, i128mem>, REX_W; +} + +// Same as LCMPXCHG8B_SAVE_RBX but for the 16 Bytes variant. +let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX], + Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW], + isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst", + usesCustomInserter = 1 in { +def LCMPXCHG16B_SAVE_RBX : + I<0, Pseudo, (outs GR64:$dst), + (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), + !strconcat("cmpxchg16b", "\t$ptr"), + [(set GR64:$dst, (X86cas16save_rbx addr:$ptr, GR64:$rbx_input, + GR64:$rbx_save))]>; +} + +defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>; + +// Atomic exchange and add +multiclass ATOMIC_LOAD_BINOP opc8, bits<8> opc, string mnemonic, + string frag> { + let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1, + SchedRW = [WriteALULd, WriteRMW] in { + def NAME#8 : I(frag # "_8") addr:$ptr, GR8:$val))]>; + def NAME#16 : I(frag # "_16") addr:$ptr, GR16:$val))]>, + OpSize16; + def NAME#32 : I(frag # "_32") addr:$ptr, GR32:$val))]>, + OpSize32; + def NAME#64 : RI(frag # "_64") addr:$ptr, GR64:$val))]>; + } +} + +defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK; + +/* The following multiclass tries to make sure that in code like + * x.store (immediate op x.load(acquire), release) + * and + * x.store (register op x.load(acquire), release) + * an operation directly on memory is generated instead of wasting a register. + * It is not automatic as atomic_store/load are only lowered to MOV instructions + * extremely late to prevent them from being accidentally reordered in the backend + * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) + */ +multiclass RELEASE_BINOP_MI { + def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), + "#BINOP "#NAME#"8mi PSEUDO!", + [(atomic_store_8 addr:$dst, (op + (atomic_load_8 addr:$dst), (i8 imm:$src)))]>; + def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src), + "#BINOP "#NAME#"8mr PSEUDO!", + [(atomic_store_8 addr:$dst, (op + (atomic_load_8 addr:$dst), GR8:$src))]>; + // NAME#16 is not generated as 16-bit arithmetic instructions are considered + // costly and avoided as far as possible by this backend anyway + def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), + "#BINOP "#NAME#"32mi PSEUDO!", + [(atomic_store_32 addr:$dst, (op + (atomic_load_32 addr:$dst), (i32 imm:$src)))]>; + def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), + "#BINOP "#NAME#"32mr PSEUDO!", + [(atomic_store_32 addr:$dst, (op + (atomic_load_32 addr:$dst), GR32:$src))]>; + def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), + "#BINOP "#NAME#"64mi32 PSEUDO!", + [(atomic_store_64 addr:$dst, (op + (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>; + def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), + "#BINOP "#NAME#"64mr PSEUDO!", + [(atomic_store_64 addr:$dst, (op + (atomic_load_64 addr:$dst), GR64:$src))]>; +} +let Defs = [EFLAGS], SchedRW = [WriteMicrocoded] in { + defm RELEASE_ADD : RELEASE_BINOP_MI; + defm RELEASE_AND : RELEASE_BINOP_MI; + defm RELEASE_OR : RELEASE_BINOP_MI; + defm RELEASE_XOR : RELEASE_BINOP_MI; + // Note: we don't deal with sub, because substractions of constants are + // optimized into additions before this code can run. +} + +// Same as above, but for floating-point. +// FIXME: imm version. +// FIXME: Version that doesn't clobber $src, using AVX's VADDSS. +// FIXME: This could also handle SIMD operations with *ps and *pd instructions. +let usesCustomInserter = 1, SchedRW = [WriteMicrocoded] in { +multiclass RELEASE_FP_BINOP_MI { + def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src), + "#BINOP "#NAME#"32mr PSEUDO!", + [(atomic_store_32 addr:$dst, + (i32 (bitconvert (op + (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))), + FR32:$src))))]>, Requires<[HasSSE1]>; + def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src), + "#BINOP "#NAME#"64mr PSEUDO!", + [(atomic_store_64 addr:$dst, + (i64 (bitconvert (op + (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))), + FR64:$src))))]>, Requires<[HasSSE2]>; +} +defm RELEASE_FADD : RELEASE_FP_BINOP_MI; +// FIXME: Add fsub, fmul, fdiv, ... +} + +multiclass RELEASE_UNOP { + def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst), + "#UNOP "#NAME#"8m PSEUDO!", + [(atomic_store_8 addr:$dst, dag8)]>; + def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst), + "#UNOP "#NAME#"16m PSEUDO!", + [(atomic_store_16 addr:$dst, dag16)]>; + def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst), + "#UNOP "#NAME#"32m PSEUDO!", + [(atomic_store_32 addr:$dst, dag32)]>; + def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst), + "#UNOP "#NAME#"64m PSEUDO!", + [(atomic_store_64 addr:$dst, dag64)]>; +} + +let Defs = [EFLAGS], Predicates = [UseIncDec], SchedRW = [WriteMicrocoded] in { + defm RELEASE_INC : RELEASE_UNOP< + (add (atomic_load_8 addr:$dst), (i8 1)), + (add (atomic_load_16 addr:$dst), (i16 1)), + (add (atomic_load_32 addr:$dst), (i32 1)), + (add (atomic_load_64 addr:$dst), (i64 1))>; + defm RELEASE_DEC : RELEASE_UNOP< + (add (atomic_load_8 addr:$dst), (i8 -1)), + (add (atomic_load_16 addr:$dst), (i16 -1)), + (add (atomic_load_32 addr:$dst), (i32 -1)), + (add (atomic_load_64 addr:$dst), (i64 -1))>; +} +/* +TODO: These don't work because the type inference of TableGen fails. +TODO: find a way to fix it. +let Defs = [EFLAGS] in { + defm RELEASE_NEG : RELEASE_UNOP< + (ineg (atomic_load_8 addr:$dst)), + (ineg (atomic_load_16 addr:$dst)), + (ineg (atomic_load_32 addr:$dst)), + (ineg (atomic_load_64 addr:$dst))>; +} +// NOT doesn't set flags. +defm RELEASE_NOT : RELEASE_UNOP< + (not (atomic_load_8 addr:$dst)), + (not (atomic_load_16 addr:$dst)), + (not (atomic_load_32 addr:$dst)), + (not (atomic_load_64 addr:$dst))>; +*/ + +let SchedRW = [WriteMicrocoded] in { +def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), + "#RELEASE_MOV8mi PSEUDO!", + [(atomic_store_8 addr:$dst, (i8 imm:$src))]>; +def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src), + "#RELEASE_MOV16mi PSEUDO!", + [(atomic_store_16 addr:$dst, (i16 imm:$src))]>; +def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), + "#RELEASE_MOV32mi PSEUDO!", + [(atomic_store_32 addr:$dst, (i32 imm:$src))]>; +def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), + "#RELEASE_MOV64mi32 PSEUDO!", + [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>; + +def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src), + "#RELEASE_MOV8mr PSEUDO!", + [(atomic_store_8 addr:$dst, GR8 :$src)]>; +def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src), + "#RELEASE_MOV16mr PSEUDO!", + [(atomic_store_16 addr:$dst, GR16:$src)]>; +def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), + "#RELEASE_MOV32mr PSEUDO!", + [(atomic_store_32 addr:$dst, GR32:$src)]>; +def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), + "#RELEASE_MOV64mr PSEUDO!", + [(atomic_store_64 addr:$dst, GR64:$src)]>; + +def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src), + "#ACQUIRE_MOV8rm PSEUDO!", + [(set GR8:$dst, (atomic_load_8 addr:$src))]>; +def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src), + "#ACQUIRE_MOV16rm PSEUDO!", + [(set GR16:$dst, (atomic_load_16 addr:$src))]>; +def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src), + "#ACQUIRE_MOV32rm PSEUDO!", + [(set GR32:$dst, (atomic_load_32 addr:$src))]>; +def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src), + "#ACQUIRE_MOV64rm PSEUDO!", + [(set GR64:$dst, (atomic_load_64 addr:$src))]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// DAG Pattern Matching Rules +//===----------------------------------------------------------------------===// + +// Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves +// binary size compared to a regular MOV, but it introduces an unnecessary +// load, so is not suitable for regular or optsize functions. +let Predicates = [OptForMinSize] in { +def : Pat<(store (i16 0), addr:$dst), (AND16mi8 addr:$dst, 0)>; +def : Pat<(store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>; +def : Pat<(store (i64 0), addr:$dst), (AND64mi8 addr:$dst, 0)>; +def : Pat<(store (i16 -1), addr:$dst), (OR16mi8 addr:$dst, -1)>; +def : Pat<(store (i32 -1), addr:$dst), (OR32mi8 addr:$dst, -1)>; +def : Pat<(store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>; +} + +// In kernel code model, we can get the address of a label +// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of +// the MOV64ri32 should accept these. +def : Pat<(i64 (X86Wrapper tconstpool :$dst)), + (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; +def : Pat<(i64 (X86Wrapper tjumptable :$dst)), + (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; +def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), + (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; +def : Pat<(i64 (X86Wrapper texternalsym:$dst)), + (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; +def : Pat<(i64 (X86Wrapper mcsym:$dst)), + (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>; +def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), + (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; + +// If we have small model and -static mode, it is safe to store global addresses +// directly as immediates. FIXME: This is really a hack, the 'imm' predicate +// for MOV64mi32 should handle this sort of thing. +def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), + (MOV64mi32 addr:$dst, tconstpool:$src)>, + Requires<[NearData, IsNotPIC]>; +def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), + (MOV64mi32 addr:$dst, tjumptable:$src)>, + Requires<[NearData, IsNotPIC]>; +def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), + (MOV64mi32 addr:$dst, tglobaladdr:$src)>, + Requires<[NearData, IsNotPIC]>; +def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), + (MOV64mi32 addr:$dst, texternalsym:$src)>, + Requires<[NearData, IsNotPIC]>; +def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst), + (MOV64mi32 addr:$dst, mcsym:$src)>, + Requires<[NearData, IsNotPIC]>; +def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), + (MOV64mi32 addr:$dst, tblockaddress:$src)>, + Requires<[NearData, IsNotPIC]>; + +def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>; +def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>; + +// Calls + +// tls has some funny stuff here... +// This corresponds to movabs $foo@tpoff, %rax +def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), + (MOV64ri32 tglobaltlsaddr :$dst)>; +// This corresponds to add $foo@tpoff, %rax +def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), + (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; + + +// Direct PC relative function call for small code model. 32-bit displacement +// sign extended to 64-bit. +def : Pat<(X86call (i64 tglobaladdr:$dst)), + (CALL64pcrel32 tglobaladdr:$dst)>; +def : Pat<(X86call (i64 texternalsym:$dst)), + (CALL64pcrel32 texternalsym:$dst)>; + +// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they +// can never use callee-saved registers. That is the purpose of the GR64_TC +// register classes. +// +// The only volatile register that is never used by the calling convention is +// %r11. This happens when calling a vararg function with 6 arguments. +// +// Match an X86tcret that uses less than 7 volatile registers. +def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), + (X86tcret node:$ptr, node:$off), [{ + // X86tcret args: (*chain, ptr, imm, regs..., glue) + unsigned NumRegs = 0; + for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) + if (isa(N->getOperand(i)) && ++NumRegs > 6) + return false; + return true; +}]>; + +def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), + (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>, + Requires<[Not64BitMode, NotUseRetpoline]>; + +// FIXME: This is disabled for 32-bit PIC mode because the global base +// register which is part of the address mode may be assigned a +// callee-saved register. +def : Pat<(X86tcret (load addr:$dst), imm:$off), + (TCRETURNmi addr:$dst, imm:$off)>, + Requires<[Not64BitMode, IsNotPIC, NotUseRetpoline]>; + +def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), + (TCRETURNdi tglobaladdr:$dst, imm:$off)>, + Requires<[NotLP64]>; + +def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), + (TCRETURNdi texternalsym:$dst, imm:$off)>, + Requires<[NotLP64]>; + +def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), + (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, + Requires<[In64BitMode, NotUseRetpoline]>; + +// Don't fold loads into X86tcret requiring more than 6 regs. +// There wouldn't be enough scratch registers for base+index. +def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off), + (TCRETURNmi64 addr:$dst, imm:$off)>, + Requires<[In64BitMode, NotUseRetpoline]>; + +def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), + (RETPOLINE_TCRETURN64 ptr_rc_tailcall:$dst, imm:$off)>, + Requires<[In64BitMode, UseRetpoline]>; + +def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), + (RETPOLINE_TCRETURN32 ptr_rc_tailcall:$dst, imm:$off)>, + Requires<[Not64BitMode, UseRetpoline]>; + +def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), + (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, + Requires<[IsLP64]>; + +def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), + (TCRETURNdi64 texternalsym:$dst, imm:$off)>, + Requires<[IsLP64]>; + +// Normal calls, with various flavors of addresses. +def : Pat<(X86call (i32 tglobaladdr:$dst)), + (CALLpcrel32 tglobaladdr:$dst)>; +def : Pat<(X86call (i32 texternalsym:$dst)), + (CALLpcrel32 texternalsym:$dst)>; +def : Pat<(X86call (i32 imm:$dst)), + (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; + +// Comparisons. + +// TEST R,R is smaller than CMP R,0 +def : Pat<(X86cmp GR8:$src1, 0), + (TEST8rr GR8:$src1, GR8:$src1)>; +def : Pat<(X86cmp GR16:$src1, 0), + (TEST16rr GR16:$src1, GR16:$src1)>; +def : Pat<(X86cmp GR32:$src1, 0), + (TEST32rr GR32:$src1, GR32:$src1)>; +def : Pat<(X86cmp GR64:$src1, 0), + (TEST64rr GR64:$src1, GR64:$src1)>; + +// Conditional moves with folded loads with operands swapped and conditions +// inverted. +multiclass CMOVmr { + let Predicates = [HasCMov] in { + def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS), + (Inst16 GR16:$src2, addr:$src1)>; + def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS), + (Inst32 GR32:$src2, addr:$src1)>; + def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS), + (Inst64 GR64:$src2, addr:$src1)>; + } +} + +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; +defm : CMOVmr; + +// zextload bool -> zextload byte +// i1 stored in one byte in zero-extended form. +// Upper bits cleanup should be executed before Store. +def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; +def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; +def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; +def : Pat<(zextloadi64i1 addr:$src), + (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; + +// extload bool -> extload byte +// When extloading from 16-bit and smaller memory locations into 64-bit +// registers, use zero-extending loads so that the entire 64-bit register is +// defined, avoiding partial-register updates. + +def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; +def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; +def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; +def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; +def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; +def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; + +// For other extloads, use subregs, since the high contents of the register are +// defined after an extload. +def : Pat<(extloadi64i1 addr:$src), + (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; +def : Pat<(extloadi64i8 addr:$src), + (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; +def : Pat<(extloadi64i16 addr:$src), + (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; +def : Pat<(extloadi64i32 addr:$src), + (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; + +// anyext. Define these to do an explicit zero-extend to +// avoid partial-register updates. +def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG + (MOVZX32rr8 GR8 :$src), sub_16bit)>; +def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; + +// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. +def : Pat<(i32 (anyext GR16:$src)), + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; + +def : Pat<(i64 (anyext GR8 :$src)), + (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; +def : Pat<(i64 (anyext GR16:$src)), + (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; +def : Pat<(i64 (anyext GR32:$src)), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>; + + +// Any instruction that defines a 32-bit result leaves the high half of the +// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may +// be copying from a truncate. Any other 32-bit operation will zero-extend +// up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper +// 32 bits, they're probably just qualifying a CopyFromReg. +def def32 : PatLeaf<(i32 GR32:$src), [{ + return N->getOpcode() != ISD::TRUNCATE && + N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && + N->getOpcode() != ISD::CopyFromReg && + N->getOpcode() != ISD::AssertSext && + N->getOpcode() != ISD::AssertZext; +}]>; + +// In the case of a 32-bit def that is known to implicitly zero-extend, +// we can use a SUBREG_TO_REG. +def : Pat<(i64 (zext def32:$src)), + (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; + +//===----------------------------------------------------------------------===// +// Pattern match OR as ADD +//===----------------------------------------------------------------------===// + +// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be +// 3-addressified into an LEA instruction to avoid copies. However, we also +// want to finally emit these instructions as an or at the end of the code +// generator to make the generated code easier to read. To do this, we select +// into "disjoint bits" pseudo ops. + +// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. +def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ + if (ConstantSDNode *CN = dyn_cast(N->getOperand(1))) + return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); + + KnownBits Known0; + CurDAG->computeKnownBits(N->getOperand(0), Known0, 0); + KnownBits Known1; + CurDAG->computeKnownBits(N->getOperand(1), Known1, 0); + return (~Known0.Zero & ~Known1.Zero) == 0; +}]>; + + +// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. +// Try this before the selecting to OR. +let AddedComplexity = 5, SchedRW = [WriteALU] in { + +let isConvertibleToThreeAddress = 1, + Constraints = "$src1 = $dst", Defs = [EFLAGS] in { +let isCommutable = 1 in { +def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "", // orw/addw REG, REG + [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; +def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "", // orl/addl REG, REG + [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; +def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "", // orq/addq REG, REG + [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; +} // isCommutable + +// NOTE: These are order specific, we want the ri8 forms to be listed +// first so that they are slightly preferred to the ri forms. + +def ADD16ri8_DB : I<0, Pseudo, + (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "", // orw/addw REG, imm8 + [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; +def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), + "", // orw/addw REG, imm + [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; + +def ADD32ri8_DB : I<0, Pseudo, + (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "", // orl/addl REG, imm8 + [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; +def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), + "", // orl/addl REG, imm + [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; + + +def ADD64ri8_DB : I<0, Pseudo, + (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "", // orq/addq REG, imm8 + [(set GR64:$dst, (or_is_add GR64:$src1, + i64immSExt8:$src2))]>; +def ADD64ri32_DB : I<0, Pseudo, + (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), + "", // orq/addq REG, imm + [(set GR64:$dst, (or_is_add GR64:$src1, + i64immSExt32:$src2))]>; +} +} // AddedComplexity, SchedRW + +//===----------------------------------------------------------------------===// +// Pattern match SUB as XOR +//===----------------------------------------------------------------------===// + +// An immediate in the LHS of a subtract can't be encoded in the instruction. +// If there is no possibility of a borrow we can use an XOR instead of a SUB +// to enable the immediate to be folded. +// TODO: Move this to a DAG combine? + +def sub_is_xor : PatFrag<(ops node:$lhs, node:$rhs), (sub node:$lhs, node:$rhs),[{ + if (ConstantSDNode *CN = dyn_cast(N->getOperand(0))) { + KnownBits Known; + CurDAG->computeKnownBits(N->getOperand(1), Known); + + // If all possible ones in the RHS are set in the LHS then there can't be + // a borrow and we can use xor. + return (~Known.Zero).isSubsetOf(CN->getAPIntValue()); + } + + return false; +}]>; + +let AddedComplexity = 5 in { +def : Pat<(sub_is_xor imm:$src2, GR8:$src1), + (XOR8ri GR8:$src1, imm:$src2)>; +def : Pat<(sub_is_xor i16immSExt8:$src2, GR16:$src1), + (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(sub_is_xor imm:$src2, GR16:$src1), + (XOR16ri GR16:$src1, imm:$src2)>; +def : Pat<(sub_is_xor i32immSExt8:$src2, GR32:$src1), + (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(sub_is_xor imm:$src2, GR32:$src1), + (XOR32ri GR32:$src1, imm:$src2)>; +def : Pat<(sub_is_xor i64immSExt8:$src2, GR64:$src1), + (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(sub_is_xor i64immSExt32:$src2, GR64:$src1), + (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; +} + +//===----------------------------------------------------------------------===// +// Some peepholes +//===----------------------------------------------------------------------===// + +// Odd encoding trick: -128 fits into an 8-bit immediate field while +// +128 doesn't, so in this special case use a sub instead of an add. +def : Pat<(add GR16:$src1, 128), + (SUB16ri8 GR16:$src1, -128)>; +def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), + (SUB16mi8 addr:$dst, -128)>; + +def : Pat<(add GR32:$src1, 128), + (SUB32ri8 GR32:$src1, -128)>; +def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), + (SUB32mi8 addr:$dst, -128)>; + +def : Pat<(add GR64:$src1, 128), + (SUB64ri8 GR64:$src1, -128)>; +def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), + (SUB64mi8 addr:$dst, -128)>; + +// The same trick applies for 32-bit immediate fields in 64-bit +// instructions. +def : Pat<(add GR64:$src1, 0x0000000080000000), + (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; +def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst), + (SUB64mi32 addr:$dst, 0xffffffff80000000)>; + +// To avoid needing to materialize an immediate in a register, use a 32-bit and +// with implicit zero-extension instead of a 64-bit and if the immediate has at +// least 32 bits of leading zeros. If in addition the last 32 bits can be +// represented with a sign extension of a 8 bit constant, use that. +// This can also reduce instruction size by eliminating the need for the REX +// prefix. + +// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. +let AddedComplexity = 1 in { +def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), + (SUBREG_TO_REG + (i64 0), + (AND32ri8 + (EXTRACT_SUBREG GR64:$src, sub_32bit), + (i32 (GetLo8XForm imm:$imm))), + sub_32bit)>; + +def : Pat<(and GR64:$src, i64immZExt32:$imm), + (SUBREG_TO_REG + (i64 0), + (AND32ri + (EXTRACT_SUBREG GR64:$src, sub_32bit), + (i32 (GetLo32XForm imm:$imm))), + sub_32bit)>; +} // AddedComplexity = 1 + + +// AddedComplexity is needed due to the increased complexity on the +// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all +// the MOVZX patterns keeps thems together in DAGIsel tables. +let AddedComplexity = 1 in { +// r & (2^16-1) ==> movz +def : Pat<(and GR32:$src1, 0xffff), + (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; +// r & (2^8-1) ==> movz +def : Pat<(and GR32:$src1, 0xff), + (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>; +// r & (2^8-1) ==> movz +def : Pat<(and GR16:$src1, 0xff), + (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)), + sub_16bit)>; + +// r & (2^32-1) ==> movz +def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), + (SUBREG_TO_REG (i64 0), + (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), + sub_32bit)>; +// r & (2^16-1) ==> movz +def : Pat<(and GR64:$src, 0xffff), + (SUBREG_TO_REG (i64 0), + (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), + sub_32bit)>; +// r & (2^8-1) ==> movz +def : Pat<(and GR64:$src, 0xff), + (SUBREG_TO_REG (i64 0), + (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), + sub_32bit)>; +} // AddedComplexity = 1 + + +// Try to use BTS/BTR/BTC for single bit operations on the upper 32-bits. + +def BTRXForm : SDNodeXFormgetAPIntValue().countTrailingOnes(), SDLoc(N)); +}]>; + +def BTCBTSXForm : SDNodeXFormgetAPIntValue().countTrailingZeros(), SDLoc(N)); +}]>; + +def BTRMask64 : ImmLeaf(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm); +}]>; + +def BTCBTSMask64 : ImmLeaf(Imm) && isPowerOf2_64(Imm); +}]>; + +// For now only do this for optsize. +let AddedComplexity = 1, Predicates=[OptForSize] in { + def : Pat<(and GR64:$src1, BTRMask64:$mask), + (BTR64ri8 GR64:$src1, (BTRXForm imm:$mask))>; + def : Pat<(or GR64:$src1, BTCBTSMask64:$mask), + (BTS64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; + def : Pat<(xor GR64:$src1, BTCBTSMask64:$mask), + (BTC64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; +} + + +// sext_inreg patterns +def : Pat<(sext_inreg GR32:$src, i16), + (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; +def : Pat<(sext_inreg GR32:$src, i8), + (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>; + +def : Pat<(sext_inreg GR16:$src, i8), + (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)), + sub_16bit)>; + +def : Pat<(sext_inreg GR64:$src, i32), + (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; +def : Pat<(sext_inreg GR64:$src, i16), + (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; +def : Pat<(sext_inreg GR64:$src, i8), + (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; + +// sext, sext_load, zext, zext_load +def: Pat<(i16 (sext GR8:$src)), + (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; +def: Pat<(sextloadi16i8 addr:$src), + (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; +def: Pat<(i16 (zext GR8:$src)), + (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; +def: Pat<(zextloadi16i8 addr:$src), + (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; + +// trunc patterns +def : Pat<(i16 (trunc GR32:$src)), + (EXTRACT_SUBREG GR32:$src, sub_16bit)>; +def : Pat<(i8 (trunc GR32:$src)), + (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), + sub_8bit)>, + Requires<[Not64BitMode]>; +def : Pat<(i8 (trunc GR16:$src)), + (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), + sub_8bit)>, + Requires<[Not64BitMode]>; +def : Pat<(i32 (trunc GR64:$src)), + (EXTRACT_SUBREG GR64:$src, sub_32bit)>; +def : Pat<(i16 (trunc GR64:$src)), + (EXTRACT_SUBREG GR64:$src, sub_16bit)>; +def : Pat<(i8 (trunc GR64:$src)), + (EXTRACT_SUBREG GR64:$src, sub_8bit)>; +def : Pat<(i8 (trunc GR32:$src)), + (EXTRACT_SUBREG GR32:$src, sub_8bit)>, + Requires<[In64BitMode]>; +def : Pat<(i8 (trunc GR16:$src)), + (EXTRACT_SUBREG GR16:$src, sub_8bit)>, + Requires<[In64BitMode]>; + +def immff00_ffff : ImmLeaf= 0xff00 && Imm <= 0xffff; +}]>; + +// h-register tricks +def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), + (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, + Requires<[Not64BitMode]>; +def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))), + (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, + Requires<[Not64BitMode]>; +def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), + (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>, + Requires<[Not64BitMode]>; +def : Pat<(srl GR16:$src, (i8 8)), + (EXTRACT_SUBREG + (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), + sub_16bit)>; +def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), + (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; +def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), + (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; +def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), + (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; +def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)), + (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; + +// h-register tricks. +// For now, be conservative on x86-64 and use an h-register extract only if the +// value is immediately zero-extended or stored, which are somewhat common +// cases. This uses a bunch of code to prevent a register requiring a REX prefix +// from being allocated in the same instruction as the h register, as there's +// currently no way to describe this requirement to the register allocator. + +// h-register extract and zero-extend. +def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), + (SUBREG_TO_REG + (i64 0), + (MOVZX32rr8_NOREX + (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)), + sub_32bit)>; +def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), + (SUBREG_TO_REG + (i64 0), + (MOVZX32rr8_NOREX + (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), + sub_32bit)>; +def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), + (SUBREG_TO_REG + (i64 0), + (MOVZX32rr8_NOREX + (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), + sub_32bit)>; + +// h-register extract and store. +def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), + (MOV8mr_NOREX + addr:$dst, + (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>; +def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), + (MOV8mr_NOREX + addr:$dst, + (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, + Requires<[In64BitMode]>; +def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), + (MOV8mr_NOREX + addr:$dst, + (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, + Requires<[In64BitMode]>; + + +// (shl x, 1) ==> (add x, x) +// Note that if x is undef (immediate or otherwise), we could theoretically +// end up with the two uses of x getting different values, producing a result +// where the least significant bit is not 0. However, the probability of this +// happening is considered low enough that this is officially not a +// "real problem". +def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; +def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; +def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; +def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; + +// Helper imms to check if a mask doesn't change significant shift/rotate bits. +def immShift8 : ImmLeaf(Imm) >= 3; +}]>; +def immShift16 : ImmLeaf(Imm) >= 4; +}]>; +def immShift32 : ImmLeaf(Imm) >= 5; +}]>; +def immShift64 : ImmLeaf(Imm) >= 6; +}]>; + +// Shift amount is implicitly masked. +multiclass MaskedShiftAmountPats { + // (shift x (and y, 31)) ==> (shift x, y) + def : Pat<(frag GR8:$src1, (and CL, immShift32)), + (!cast(name # "8rCL") GR8:$src1)>; + def : Pat<(frag GR16:$src1, (and CL, immShift32)), + (!cast(name # "16rCL") GR16:$src1)>; + def : Pat<(frag GR32:$src1, (and CL, immShift32)), + (!cast(name # "32rCL") GR32:$src1)>; + def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), + (!cast(name # "8mCL") addr:$dst)>; + def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), + (!cast(name # "16mCL") addr:$dst)>; + def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), + (!cast(name # "32mCL") addr:$dst)>; + + // (shift x (and y, 63)) ==> (shift x, y) + def : Pat<(frag GR64:$src1, (and CL, immShift64)), + (!cast(name # "64rCL") GR64:$src1)>; + def : Pat<(store (frag (loadi64 addr:$dst), (and CL, immShift64)), addr:$dst), + (!cast(name # "64mCL") addr:$dst)>; +} + +defm : MaskedShiftAmountPats; +defm : MaskedShiftAmountPats; +defm : MaskedShiftAmountPats; + +// ROL/ROR instructions allow a stronger mask optimization than shift for 8- and +// 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount +// because over-rotating produces the same result. This is noted in the Intel +// docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation +// amount could affect EFLAGS results, but that does not matter because we are +// not tracking flags for these nodes. +multiclass MaskedRotateAmountPats { + // (rot x (and y, BitWidth - 1)) ==> (rot x, y) + def : Pat<(frag GR8:$src1, (and CL, immShift8)), + (!cast(name # "8rCL") GR8:$src1)>; + def : Pat<(frag GR16:$src1, (and CL, immShift16)), + (!cast(name # "16rCL") GR16:$src1)>; + def : Pat<(frag GR32:$src1, (and CL, immShift32)), + (!cast(name # "32rCL") GR32:$src1)>; + def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift8)), addr:$dst), + (!cast(name # "8mCL") addr:$dst)>; + def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift16)), addr:$dst), + (!cast(name # "16mCL") addr:$dst)>; + def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), + (!cast(name # "32mCL") addr:$dst)>; + + // (rot x (and y, 63)) ==> (rot x, y) + def : Pat<(frag GR64:$src1, (and CL, immShift64)), + (!cast(name # "64rCL") GR64:$src1)>; + def : Pat<(store (frag (loadi64 addr:$dst), (and CL, immShift64)), addr:$dst), + (!cast(name # "64mCL") addr:$dst)>; +} + + +defm : MaskedRotateAmountPats; +defm : MaskedRotateAmountPats; + +// Double shift amount is implicitly masked. +multiclass MaskedDoubleShiftAmountPats { + // (shift x (and y, 31)) ==> (shift x, y) + def : Pat<(frag GR16:$src1, GR16:$src2, (and CL, immShift32)), + (!cast(name # "16rrCL") GR16:$src1, GR16:$src2)>; + def : Pat<(frag GR32:$src1, GR32:$src2, (and CL, immShift32)), + (!cast(name # "32rrCL") GR32:$src1, GR32:$src2)>; + + // (shift x (and y, 63)) ==> (shift x, y) + def : Pat<(frag GR64:$src1, GR64:$src2, (and CL, immShift64)), + (!cast(name # "64rrCL") GR64:$src1, GR64:$src2)>; +} + +defm : MaskedDoubleShiftAmountPats; +defm : MaskedDoubleShiftAmountPats; + +let Predicates = [HasBMI2] in { + let AddedComplexity = 1 in { + def : Pat<(sra GR32:$src1, (and GR8:$src2, immShift32)), + (SARX32rr GR32:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(sra GR64:$src1, (and GR8:$src2, immShift64)), + (SARX64rr GR64:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(srl GR32:$src1, (and GR8:$src2, immShift32)), + (SHRX32rr GR32:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(srl GR64:$src1, (and GR8:$src2, immShift64)), + (SHRX64rr GR64:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(shl GR32:$src1, (and GR8:$src2, immShift32)), + (SHLX32rr GR32:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(shl GR64:$src1, (and GR8:$src2, immShift64)), + (SHLX64rr GR64:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + } + + def : Pat<(sra (loadi32 addr:$src1), (and GR8:$src2, immShift32)), + (SARX32rm addr:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(sra (loadi64 addr:$src1), (and GR8:$src2, immShift64)), + (SARX64rm addr:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(srl (loadi32 addr:$src1), (and GR8:$src2, immShift32)), + (SHRX32rm addr:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(srl (loadi64 addr:$src1), (and GR8:$src2, immShift64)), + (SHRX64rm addr:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(shl (loadi32 addr:$src1), (and GR8:$src2, immShift32)), + (SHLX32rm addr:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(shl (loadi64 addr:$src1), (and GR8:$src2, immShift64)), + (SHLX64rm addr:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; +} + +// Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location. +multiclass one_bit_patterns { + def : Pat<(and RC:$src1, (rotl -2, GR8:$src2)), + (BTR RC:$src1, + (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(or RC:$src1, (shl 1, GR8:$src2)), + (BTS RC:$src1, + (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(xor RC:$src1, (shl 1, GR8:$src2)), + (BTC RC:$src1, + (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + // Similar to above, but removing unneeded masking of the shift amount. + def : Pat<(and RC:$src1, (rotl -2, (and GR8:$src2, ImmShift))), + (BTR RC:$src1, + (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(or RC:$src1, (shl 1, (and GR8:$src2, ImmShift))), + (BTS RC:$src1, + (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(xor RC:$src1, (shl 1, (and GR8:$src2, ImmShift))), + (BTC RC:$src1, + (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; +} + +defm : one_bit_patterns; +defm : one_bit_patterns; +defm : one_bit_patterns; + + +// (anyext (setcc_carry)) -> (setcc_carry) +def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C16r)>; +def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C32r)>; +def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), + (SETB_C32r)>; + +//===----------------------------------------------------------------------===// +// EFLAGS-defining Patterns +//===----------------------------------------------------------------------===// + +// add reg, reg +def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; +def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; +def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; +def : Pat<(add GR64:$src1, GR64:$src2), (ADD64rr GR64:$src1, GR64:$src2)>; + +// add reg, mem +def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), + (ADD8rm GR8:$src1, addr:$src2)>; +def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), + (ADD16rm GR16:$src1, addr:$src2)>; +def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), + (ADD32rm GR32:$src1, addr:$src2)>; +def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), + (ADD64rm GR64:$src1, addr:$src2)>; + +// add reg, imm +def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; +def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; +def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; +def : Pat<(add GR16:$src1, i16immSExt8:$src2), + (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(add GR32:$src1, i32immSExt8:$src2), + (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(add GR64:$src1, i64immSExt8:$src2), + (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(add GR64:$src1, i64immSExt32:$src2), + (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; + +// sub reg, reg +def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; +def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; +def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; +def : Pat<(sub GR64:$src1, GR64:$src2), (SUB64rr GR64:$src1, GR64:$src2)>; + +// sub reg, mem +def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), + (SUB8rm GR8:$src1, addr:$src2)>; +def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), + (SUB16rm GR16:$src1, addr:$src2)>; +def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), + (SUB32rm GR32:$src1, addr:$src2)>; +def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), + (SUB64rm GR64:$src1, addr:$src2)>; + +// sub reg, imm +def : Pat<(sub GR8:$src1, imm:$src2), + (SUB8ri GR8:$src1, imm:$src2)>; +def : Pat<(sub GR16:$src1, imm:$src2), + (SUB16ri GR16:$src1, imm:$src2)>; +def : Pat<(sub GR32:$src1, imm:$src2), + (SUB32ri GR32:$src1, imm:$src2)>; +def : Pat<(sub GR16:$src1, i16immSExt8:$src2), + (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(sub GR32:$src1, i32immSExt8:$src2), + (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(sub GR64:$src1, i64immSExt8:$src2), + (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(sub GR64:$src1, i64immSExt32:$src2), + (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; + +// sub 0, reg +def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; +def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; +def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; +def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; + +// sub reg, relocImm +def : Pat<(X86sub_flag GR64:$src1, i64relocImmSExt8_su:$src2), + (SUB64ri8 GR64:$src1, i64relocImmSExt8_su:$src2)>; +def : Pat<(X86sub_flag GR64:$src1, i64relocImmSExt32_su:$src2), + (SUB64ri32 GR64:$src1, i64relocImmSExt32_su:$src2)>; + +// mul reg, reg +def : Pat<(mul GR16:$src1, GR16:$src2), + (IMUL16rr GR16:$src1, GR16:$src2)>; +def : Pat<(mul GR32:$src1, GR32:$src2), + (IMUL32rr GR32:$src1, GR32:$src2)>; +def : Pat<(mul GR64:$src1, GR64:$src2), + (IMUL64rr GR64:$src1, GR64:$src2)>; + +// mul reg, mem +def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), + (IMUL16rm GR16:$src1, addr:$src2)>; +def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), + (IMUL32rm GR32:$src1, addr:$src2)>; +def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), + (IMUL64rm GR64:$src1, addr:$src2)>; + +// mul reg, imm +def : Pat<(mul GR16:$src1, imm:$src2), + (IMUL16rri GR16:$src1, imm:$src2)>; +def : Pat<(mul GR32:$src1, imm:$src2), + (IMUL32rri GR32:$src1, imm:$src2)>; +def : Pat<(mul GR16:$src1, i16immSExt8:$src2), + (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(mul GR32:$src1, i32immSExt8:$src2), + (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(mul GR64:$src1, i64immSExt8:$src2), + (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(mul GR64:$src1, i64immSExt32:$src2), + (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; + +// reg = mul mem, imm +def : Pat<(mul (loadi16 addr:$src1), imm:$src2), + (IMUL16rmi addr:$src1, imm:$src2)>; +def : Pat<(mul (loadi32 addr:$src1), imm:$src2), + (IMUL32rmi addr:$src1, imm:$src2)>; +def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), + (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; +def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), + (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; +def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), + (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; +def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), + (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; + +// Increment/Decrement reg. +// Do not make INC/DEC if it is slow +let Predicates = [UseIncDec] in { + def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>; + def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>; + def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>; + def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; + def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>; + def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>; + def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>; + def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; +} + +// or reg/reg. +def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; +def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; +def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; +def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; + +// or reg/mem +def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), + (OR8rm GR8:$src1, addr:$src2)>; +def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), + (OR16rm GR16:$src1, addr:$src2)>; +def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), + (OR32rm GR32:$src1, addr:$src2)>; +def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), + (OR64rm GR64:$src1, addr:$src2)>; + +// or reg/imm +def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; +def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; +def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; +def : Pat<(or GR16:$src1, i16immSExt8:$src2), + (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(or GR32:$src1, i32immSExt8:$src2), + (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(or GR64:$src1, i64immSExt8:$src2), + (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(or GR64:$src1, i64immSExt32:$src2), + (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; + +// xor reg/reg +def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; +def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; +def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; +def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; + +// xor reg/mem +def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), + (XOR8rm GR8:$src1, addr:$src2)>; +def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), + (XOR16rm GR16:$src1, addr:$src2)>; +def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), + (XOR32rm GR32:$src1, addr:$src2)>; +def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), + (XOR64rm GR64:$src1, addr:$src2)>; + +// xor reg/imm +def : Pat<(xor GR8:$src1, imm:$src2), + (XOR8ri GR8:$src1, imm:$src2)>; +def : Pat<(xor GR16:$src1, imm:$src2), + (XOR16ri GR16:$src1, imm:$src2)>; +def : Pat<(xor GR32:$src1, imm:$src2), + (XOR32ri GR32:$src1, imm:$src2)>; +def : Pat<(xor GR16:$src1, i16immSExt8:$src2), + (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(xor GR32:$src1, i32immSExt8:$src2), + (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(xor GR64:$src1, i64immSExt8:$src2), + (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(xor GR64:$src1, i64immSExt32:$src2), + (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; + +// and reg/reg +def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; +def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; +def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; +def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; + +// and reg/mem +def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), + (AND8rm GR8:$src1, addr:$src2)>; +def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), + (AND16rm GR16:$src1, addr:$src2)>; +def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), + (AND32rm GR32:$src1, addr:$src2)>; +def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), + (AND64rm GR64:$src1, addr:$src2)>; + +// and reg/imm +def : Pat<(and GR8:$src1, imm:$src2), + (AND8ri GR8:$src1, imm:$src2)>; +def : Pat<(and GR16:$src1, imm:$src2), + (AND16ri GR16:$src1, imm:$src2)>; +def : Pat<(and GR32:$src1, imm:$src2), + (AND32ri GR32:$src1, imm:$src2)>; +def : Pat<(and GR16:$src1, i16immSExt8:$src2), + (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; +def : Pat<(and GR32:$src1, i32immSExt8:$src2), + (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; +def : Pat<(and GR64:$src1, i64immSExt8:$src2), + (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; +def : Pat<(and GR64:$src1, i64immSExt32:$src2), + (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; + +// Bit scan instruction patterns to match explicit zero-undef behavior. +def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; +def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; +def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; +def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; +def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; +def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; + +// When HasMOVBE is enabled it is possible to get a non-legalized +// register-register 16 bit bswap. This maps it to a ROL instruction. +let Predicates = [HasMOVBE] in { + def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; +} + +// These patterns are selected by some custom code in X86ISelDAGToDAG.cpp that +// custom combines and+srl into BEXTR. We use these patterns to avoid a bunch +// of manual code for folding loads. +let Predicates = [HasBMI, NoTBM] in { + def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)), + (BEXTR32rr GR32:$src1, (MOV32ri imm:$src2))>; + def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)), + (BEXTR32rm addr:$src1, (MOV32ri imm:$src2))>; + def : Pat<(X86bextr GR64:$src1, mov64imm32:$src2), + (BEXTR64rr GR64:$src1, + (SUBREG_TO_REG (i64 0), + (MOV32ri64 mov64imm32:$src2), + sub_32bit))>; + def : Pat<(X86bextr (loadi64 addr:$src1), mov64imm32:$src2), + (BEXTR64rm addr:$src1, + (SUBREG_TO_REG (i64 0), + (MOV32ri64 mov64imm32:$src2), + sub_32bit))>; +} // HasBMI, NoTBM diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrControl.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrControl.td new file mode 100644 index 0000000..3271b43 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrControl.td @@ -0,0 +1,413 @@ +//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 jump, return, call, and related instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Control Flow Instructions. +// + +// Return instructions. +// +// The X86retflag return instructions are variadic because we may add ST0 and +// ST1 arguments when returning values on the x87 stack. +let isTerminator = 1, isReturn = 1, isBarrier = 1, + hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in { + def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops), + "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>; + def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops), + "ret{q}", []>, OpSize32, Requires<[In64BitMode]>; + def RETW : I <0xC3, RawFrm, (outs), (ins), + "ret{w}", []>, OpSize16; + def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), + "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>; + def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), + "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>; + def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), + "ret{w}\t$amt", []>, OpSize16; + def LRETL : I <0xCB, RawFrm, (outs), (ins), + "{l}ret{l|f}", []>, OpSize32; + def LRETQ : RI <0xCB, RawFrm, (outs), (ins), + "{l}ret{|f}q", []>, Requires<[In64BitMode]>; + def LRETW : I <0xCB, RawFrm, (outs), (ins), + "{l}ret{w|f}", []>, OpSize16; + def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), + "{l}ret{l|f}\t$amt", []>, OpSize32; + def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt), + "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>; + def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), + "{l}ret{w|f}\t$amt", []>, OpSize16; + + // The machine return from interrupt instruction, but sometimes we need to + // perform a post-epilogue stack adjustment. Codegen emits the pseudo form + // which expands to include an SP adjustment if necessary. + def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", []>, + OpSize16; + def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32; + def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>; + // let isCodeGenOnly = 1 in + // def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>; + // def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>; +} + +// Unconditional branches. +let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { + def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), + "jmp\t$dst", [(br bb:$dst)]>; + let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { + def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst), + "jmp\t$dst", []>, OpSize16; + def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst), + "jmp\t$dst", []>, OpSize32; + } +} + +// Conditional Branches. +let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in { + multiclass ICBr opc1, bits<8> opc4, string asm, PatFrag Cond> { + def _1 : Ii8PCRel ; + let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { + def _2 : Ii16PCRel, OpSize16, TB; + def _4 : Ii32PCRel, TB, OpSize32; + } + } +} + +defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>; +defm JNO : ICBr<0x71, 0x81, "jno\t$dst", X86_COND_NO>; +defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>; +defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>; +defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>; +defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>; +defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>; +defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>; +defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>; +defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>; +defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>; +defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>; +defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>; +defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>; +defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>; +defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>; + +// jcx/jecx/jrcx instructions. +let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in { + // These are the 32-bit versions of this instruction for the asmparser. In + // 32-bit mode, the address size prefix is jcxz and the unprefixed version is + // jecxz. + let Uses = [CX] in + def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), + "jcxz\t$dst", []>, AdSize16, Requires<[Not64BitMode]>; + let Uses = [ECX] in + def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), + "jecxz\t$dst", []>, AdSize32; + + let Uses = [RCX] in + def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), + "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>; +} + +// Indirect branches +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { + def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst", + [(brind GR16:$dst)]>, Requires<[Not64BitMode]>, + OpSize16, Sched<[WriteJump]>; + def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst", + [(brind (loadi16 addr:$dst))]>, Requires<[Not64BitMode]>, + OpSize16, Sched<[WriteJumpLd]>; + + def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", + [(brind GR32:$dst)]>, Requires<[Not64BitMode]>, + OpSize32, Sched<[WriteJump]>; + def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", + [(brind (loadi32 addr:$dst))]>, Requires<[Not64BitMode]>, + OpSize32, Sched<[WriteJumpLd]>; + + def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", + [(brind GR64:$dst)]>, Requires<[In64BitMode]>, + Sched<[WriteJump]>; + def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", + [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>, + Sched<[WriteJumpLd]>; + + // Non-tracking jumps for IBT, use with caution. + let isCodeGenOnly = 1 in { + def JMP16r_NT : I<0xFF, MRM4r, (outs), (ins GR16 : $dst), "jmp{w}\t{*}$dst", + [(X86NoTrackBrind GR16 : $dst)]>, Requires<[Not64BitMode]>, + OpSize16, Sched<[WriteJump]>, NOTRACK; + + def JMP16m_NT : I<0xFF, MRM4m, (outs), (ins i16mem : $dst), "jmp{w}\t{*}$dst", + [(X86NoTrackBrind (loadi16 addr : $dst))]>, + Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>, + NOTRACK; + + def JMP32r_NT : I<0xFF, MRM4r, (outs), (ins GR32 : $dst), "jmp{l}\t{*}$dst", + [(X86NoTrackBrind GR32 : $dst)]>, Requires<[Not64BitMode]>, + OpSize32, Sched<[WriteJump]>, NOTRACK; + def JMP32m_NT : I<0xFF, MRM4m, (outs), (ins i32mem : $dst), "jmp{l}\t{*}$dst", + [(X86NoTrackBrind (loadi32 addr : $dst))]>, + Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>, + NOTRACK; + + def JMP64r_NT : I<0xFF, MRM4r, (outs), (ins GR64 : $dst), "jmp{q}\t{*}$dst", + [(X86NoTrackBrind GR64 : $dst)]>, Requires<[In64BitMode]>, + Sched<[WriteJump]>, NOTRACK; + def JMP64m_NT : I<0xFF, MRM4m, (outs), (ins i64mem : $dst), "jmp{q}\t{*}$dst", + [(X86NoTrackBrind(loadi64 addr : $dst))]>, + Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK; + } + + let Predicates = [Not64BitMode], AsmVariantName = "att" in { + def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), + (ins i16imm:$off, i16imm:$seg), + "ljmp{w}\t$seg : $off", []>, + OpSize16, Sched<[WriteJump]>; + def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), + (ins i32imm:$off, i16imm:$seg), + "ljmp{l}\t$seg : $off", []>, + OpSize32, Sched<[WriteJump]>; + } + def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaquemem:$dst), + "ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>; + + let AsmVariantName = "att" in + def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), + "ljmp{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; + def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), + "{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; +} + +// Loop instructions +let SchedRW = [WriteJump] in { +def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>; +def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>; +def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>; +} + +//===----------------------------------------------------------------------===// +// Call Instructions... +// +let isCall = 1 in + // All calls clobber the non-callee saved registers. ESP is marked as + // a use to prevent stack-pointer assignments that appear immediately + // before calls from potentially appearing dead. Uses for argument + // registers are added manually. + let Uses = [ESP, SSP] in { + def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm, + (outs), (ins i32imm_pcrel:$dst), + "call{l}\t$dst", []>, OpSize32, + Requires<[Not64BitMode]>, Sched<[WriteJump]>; + let hasSideEffects = 0 in + def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm, + (outs), (ins i16imm_pcrel:$dst), + "call{w}\t$dst", []>, OpSize16, + Sched<[WriteJump]>; + def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst), + "call{w}\t{*}$dst", [(X86call GR16:$dst)]>, + OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>; + def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst), + "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))]>, + OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, + Sched<[WriteJumpLd]>; + def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst), + "call{l}\t{*}$dst", [(X86call GR32:$dst)]>, OpSize32, + Requires<[Not64BitMode,NotUseRetpoline]>, Sched<[WriteJump]>; + def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst), + "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>, + OpSize32, + Requires<[Not64BitMode,FavorMemIndirectCall,NotUseRetpoline]>, + Sched<[WriteJumpLd]>; + + // Non-tracking calls for IBT, use with caution. + let isCodeGenOnly = 1 in { + def CALL16r_NT : I<0xFF, MRM2r, (outs), (ins GR16 : $dst), + "call{w}\t{*}$dst",[(X86NoTrackCall GR16 : $dst)]>, + OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK; + def CALL16m_NT : I<0xFF, MRM2m, (outs), (ins i16mem : $dst), + "call{w}\t{*}$dst",[(X86NoTrackCall(loadi16 addr : $dst))]>, + OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, + Sched<[WriteJumpLd]>, NOTRACK; + def CALL32r_NT : I<0xFF, MRM2r, (outs), (ins GR32 : $dst), + "call{l}\t{*}$dst",[(X86NoTrackCall GR32 : $dst)]>, + OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK; + def CALL32m_NT : I<0xFF, MRM2m, (outs), (ins i32mem : $dst), + "call{l}\t{*}$dst",[(X86NoTrackCall(loadi32 addr : $dst))]>, + OpSize32, Requires<[Not64BitMode,FavorMemIndirectCall]>, + Sched<[WriteJumpLd]>, NOTRACK; + } + + let Predicates = [Not64BitMode], AsmVariantName = "att" in { + def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), + (ins i16imm:$off, i16imm:$seg), + "lcall{w}\t$seg : $off", []>, + OpSize16, Sched<[WriteJump]>; + def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), + (ins i32imm:$off, i16imm:$seg), + "lcall{l}\t$seg : $off", []>, + OpSize32, Sched<[WriteJump]>; + } + + def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), + "lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; + def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), + "{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; + } + + +/* +// Tail call stuff. +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, + isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in + let Uses = [ESP, SSP] in { + def TCRETURNdi : PseudoI<(outs), + (ins i32imm_pcrel:$dst, i32imm:$offset), []>, NotMemoryFoldable; + def TCRETURNri : PseudoI<(outs), + (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>, NotMemoryFoldable; + let mayLoad = 1 in + def TCRETURNmi : PseudoI<(outs), + (ins i32mem_TC:$dst, i32imm:$offset), []>; + + // FIXME: The should be pseudo instructions that are lowered when going to + // mcinst. + def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs), + (ins i32imm_pcrel:$dst), "jmp\t$dst", []>; + + def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), + "", []>; // FIXME: Remove encoding when JIT is dead. + let mayLoad = 1 in + def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst), + "jmp{l}\t{*}$dst", []>; +} + +// Conditional tail calls are similar to the above, but they are branches +// rather than barriers, and they use EFLAGS. +let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, + isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in + let Uses = [ESP, EFLAGS, SSP] in { + def TCRETURNdicc : PseudoI<(outs), + (ins i32imm_pcrel:$dst, i32imm:$offset, i32imm:$cond), []>; + + // This gets substituted to a conditional jump instruction in MC lowering. + def TAILJMPd_CC : Ii32PCRel<0x80, RawFrm, (outs), + (ins i32imm_pcrel:$dst, i32imm:$cond), "", []>; +} +*/ + + +//===----------------------------------------------------------------------===// +// Call Instructions... +// + +// RSP is marked as a use to prevent stack-pointer assignments that appear +// immediately before calls from potentially appearing dead. Uses for argument +// registers are added manually. +let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in { + // NOTE: this pattern doesn't match "X86call imm", because we do not know + // that the offset between an arbitrary immediate and the call will fit in + // the 32-bit pcrel field that we have. + def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm, + (outs), (ins i64i32imm_pcrel:$dst), + "call{q}\t$dst", []>, OpSize32, + Requires<[In64BitMode]>; + def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst), + "call{q}\t{*}$dst", [(X86call GR64:$dst)]>, + Requires<[In64BitMode,NotUseRetpoline]>; + def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst), + "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>, + Requires<[In64BitMode,FavorMemIndirectCall, + NotUseRetpoline]>; + + // Non-tracking calls for IBT, use with caution. + let isCodeGenOnly = 1 in { + def CALL64r_NT : I<0xFF, MRM2r, (outs), (ins GR64 : $dst), + "call{q}\t{*}$dst",[(X86NoTrackCall GR64 : $dst)]>, + Requires<[In64BitMode]>, NOTRACK; + def CALL64m_NT : I<0xFF, MRM2m, (outs), (ins i64mem : $dst), + "call{q}\t{*}$dst", + [(X86NoTrackCall(loadi64 addr : $dst))]>, + Requires<[In64BitMode,FavorMemIndirectCall]>, NOTRACK; + } + + def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst), + "lcall{q}\t{*}$dst", []>; +} + +/* +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, + isCodeGenOnly = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in { + def TCRETURNdi64 : PseudoI<(outs), + (ins i64i32imm_pcrel:$dst, i32imm:$offset), + []>; + def TCRETURNri64 : PseudoI<(outs), + (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>, NotMemoryFoldable; + let mayLoad = 1 in + def TCRETURNmi64 : PseudoI<(outs), + (ins i64mem_TC:$dst, i32imm:$offset), []>, NotMemoryFoldable; + + def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), (ins i64i32imm_pcrel:$dst), + "jmp\t$dst", []>; + + def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), + "jmp{q}\t{*}$dst", []>; + + let mayLoad = 1 in + def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), + "jmp{q}\t{*}$dst", []>; + + // Win64 wants indirect jumps leaving the function to have a REX_W prefix. + let hasREX_WPrefix = 1 in { + def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), + "rex64 jmp{q}\t{*}$dst", []>; + + let mayLoad = 1 in + def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), + "rex64 jmp{q}\t{*}$dst", []>; + } +} + +let isPseudo = 1, isCall = 1, isCodeGenOnly = 1, + Uses = [RSP, SSP], + usesCustomInserter = 1, + SchedRW = [WriteJump] in { + def RETPOLINE_CALL32 : + PseudoI<(outs), (ins GR32:$dst), [(X86call GR32:$dst)]>, + Requires<[Not64BitMode,UseRetpoline]>; + + def RETPOLINE_CALL64 : + PseudoI<(outs), (ins GR64:$dst), [(X86call GR64:$dst)]>, + Requires<[In64BitMode,UseRetpoline]>; + + // Retpoline variant of indirect tail calls. + let isTerminator = 1, isReturn = 1, isBarrier = 1 in { + def RETPOLINE_TCRETURN64 : + PseudoI<(outs), (ins GR64:$dst, i32imm:$offset), []>; + def RETPOLINE_TCRETURN32 : + PseudoI<(outs), (ins GR32:$dst, i32imm:$offset), []>; + } +} + +// Conditional tail calls are similar to the above, but they are branches +// rather than barriers, and they use EFLAGS. +let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, + isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in + let Uses = [RSP, EFLAGS, SSP] in { + def TCRETURNdi64cc : PseudoI<(outs), + (ins i64i32imm_pcrel:$dst, i32imm:$offset, + i32imm:$cond), []>; + + // This gets substituted to a conditional jump instruction in MC lowering. + def TAILJMPd64_CC : Ii32PCRel<0x80, RawFrm, (outs), + (ins i64i32imm_pcrel:$dst, i32imm:$cond), "", []>; +} +*/ diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrExtension.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrExtension.td new file mode 100644 index 0000000..421792c --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrExtension.td @@ -0,0 +1,204 @@ +//===-- X86InstrExtension.td - Sign and Zero Extensions ----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the sign and zero extension operations. +// +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0 in { + let Defs = [AX], Uses = [AL] in // AX = signext(AL) + def CBW : I<0x98, RawFrm, (outs), (ins), + "{cbtw|cbw}", []>, OpSize16, Sched<[WriteALU]>; + let Defs = [EAX], Uses = [AX] in // EAX = signext(AX) + def CWDE : I<0x98, RawFrm, (outs), (ins), + "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>; + + let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX) + def CWD : I<0x99, RawFrm, (outs), (ins), + "{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>; + let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX) + def CDQ : I<0x99, RawFrm, (outs), (ins), + "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>; + + + let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX) + def CDQE : RI<0x98, RawFrm, (outs), (ins), + "{cltq|cdqe}", []>, Sched<[WriteALU]>; + + let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX) + def CQO : RI<0x99, RawFrm, (outs), (ins), + "{cqto|cqo}", []>, Sched<[WriteALU]>; +} + +// Sign/Zero extenders +let hasSideEffects = 0 in { +def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), + "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, + TB, OpSize16, Sched<[WriteALU]>; +let mayLoad = 1 in +def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), + "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, + TB, OpSize16, Sched<[WriteALULd]>; +} // hasSideEffects = 0 +def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src), + "movs{bl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (sext GR8:$src))]>, TB, + OpSize32, Sched<[WriteALU]>; +def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), + "movs{bl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB, + OpSize32, Sched<[WriteALULd]>; +def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), + "movs{wl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (sext GR16:$src))]>, TB, + OpSize32, Sched<[WriteALU]>; +def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), + "movs{wl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, + OpSize32, TB, Sched<[WriteALULd]>; + +let hasSideEffects = 0 in { +def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), + "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, + TB, OpSize16, Sched<[WriteALU]>; +let mayLoad = 1 in +def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), + "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, + TB, OpSize16, Sched<[WriteALULd]>; +} // hasSideEffects = 0 +def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), + "movz{bl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (zext GR8:$src))]>, TB, + OpSize32, Sched<[WriteALU]>; +def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), + "movz{bl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB, + OpSize32, Sched<[WriteALULd]>; +def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), + "movz{wl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (zext GR16:$src))]>, TB, + OpSize32, Sched<[WriteALU]>; +def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), + "movz{wl|x}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, + TB, OpSize32, Sched<[WriteALULd]>; + +// These instructions exist as a consequence of operand size prefix having +// control of the destination size, but not the input size. Only support them +// for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { +def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "movs{ww|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable; +def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "movz{ww|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable; +let mayLoad = 1 in { +def MOVSX16rm16: I<0xBF, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "movs{ww|x}\t{$src, $dst|$dst, $src}", + []>, OpSize16, TB, Sched<[WriteALULd]>, NotMemoryFoldable; +def MOVZX16rm16: I<0xB7, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "movz{ww|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize16, Sched<[WriteALULd]>, NotMemoryFoldable; +} // mayLoad = 1 +} // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 + +// These are the same as the regular MOVZX32rr8 and MOVZX32rm8 +// except that they use GR32_NOREX for the output operand register class +// instead of GR32. This allows them to operate on h registers on x86-64. +let hasSideEffects = 0, isCodeGenOnly = 1 in { +def MOVZX32rr8_NOREX : I<0xB6, MRMSrcReg, + (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src), + "movz{bl|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize32, Sched<[WriteALU]>; +let mayLoad = 1 in +def MOVZX32rm8_NOREX : I<0xB6, MRMSrcMem, + (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src), + "movz{bl|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize32, Sched<[WriteALULd]>; + +def MOVSX32rr8_NOREX : I<0xBE, MRMSrcReg, + (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src), + "movs{bl|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize32, Sched<[WriteALU]>; +let mayLoad = 1 in +def MOVSX32rm8_NOREX : I<0xBE, MRMSrcMem, + (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src), + "movs{bl|x}\t{$src, $dst|$dst, $src}", + []>, TB, OpSize32, Sched<[WriteALULd]>; +} + +// MOVSX64rr8 always has a REX prefix and it has an 8-bit register +// operand, which makes it a rare instruction with an 8-bit register +// operand that can never access an h register. If support for h registers +// were generalized, this would require a special register class. +def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src), + "movs{bq|x}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (sext GR8:$src))]>, TB, + Sched<[WriteALU]>; +def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src), + "movs{bq|x}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, + TB, Sched<[WriteALULd]>; +def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), + "movs{wq|x}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (sext GR16:$src))]>, TB, + Sched<[WriteALU]>; +def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), + "movs{wq|x}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, + TB, Sched<[WriteALULd]>; +def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), + "movs{lq|xd}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (sext GR32:$src))]>, + Sched<[WriteALU]>, Requires<[In64BitMode]>; +def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), + "movs{lq|xd}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (sextloadi64i32 addr:$src))]>, + Sched<[WriteALULd]>, Requires<[In64BitMode]>; + +// movzbq and movzwq encodings for the disassembler +let hasSideEffects = 0 in { +def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src), + "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, + TB, Sched<[WriteALU]>; +let mayLoad = 1 in +def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src), + "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, + TB, Sched<[WriteALULd]>; +def MOVZX64rr16 : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), + "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, + TB, Sched<[WriteALU]>; +let mayLoad = 1 in +def MOVZX64rm16 : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), + "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, + TB, Sched<[WriteALULd]>; +} + +// 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a +// 32-bit register. +def : Pat<(i64 (zext GR8:$src)), + (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>; +def : Pat<(zextloadi64i8 addr:$src), + (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; + +def : Pat<(i64 (zext GR16:$src)), + (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>; +def : Pat<(zextloadi64i16 addr:$src), + (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; + +// The preferred way to do 32-bit-to-64-bit zero extension on x86-64 is to use a +// SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible +// when the 32-bit value is defined by a truncate or is copied from something +// where the high bits aren't necessarily all zero. In such cases, we fall back +// to these explicit zext instructions. +def : Pat<(i64 (zext GR32:$src)), + (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>; +def : Pat<(i64 (zextloadi64i32 addr:$src)), + (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrFMA.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrFMA.td new file mode 100644 index 0000000..1827741 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrFMA.td @@ -0,0 +1,636 @@ +//===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes FMA (Fused Multiply-Add) instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// FMA3 - Intel 3 operand Fused Multiply-Add instructions +//===----------------------------------------------------------------------===// + +// For all FMA opcodes declared in fma3p_rm_* and fma3s_rm_* multiclasses +// defined below, both the register and memory variants are commutable. +// For the register form the commutable operands are 1, 2 and 3. +// For the memory variant the folded operand must be in 3. Thus, +// in that case, only the operands 1 and 2 can be swapped. +// Commuting some of operands may require the opcode change. +// FMA*213*: +// operands 1 and 2 (memory & register forms): *213* --> *213*(no changes); +// operands 1 and 3 (register forms only): *213* --> *231*; +// operands 2 and 3 (register forms only): *213* --> *132*. +// FMA*132*: +// operands 1 and 2 (memory & register forms): *132* --> *231*; +// operands 1 and 3 (register forms only): *132* --> *132*(no changes); +// operands 2 and 3 (register forms only): *132* --> *213*. +// FMA*231*: +// operands 1 and 2 (memory & register forms): *231* --> *132*; +// operands 1 and 3 (register forms only): *231* --> *213*; +// operands 2 and 3 (register forms only): *231* --> *231*(no changes). + +multiclass fma3p_rm_213 opc, string OpcodeStr, RegisterClass RC, + ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, + SDNode Op, X86FoldableSchedWrite sched> { + def r : FMA3, + Sched<[sched]>; + + let mayLoad = 1 in + def m : FMA3, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +multiclass fma3p_rm_231 opc, string OpcodeStr, RegisterClass RC, + ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, + SDNode Op, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def r : FMA3, Sched<[sched]>; + + let mayLoad = 1 in + def m : FMA3, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +multiclass fma3p_rm_132 opc, string OpcodeStr, RegisterClass RC, + ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, + SDNode Op, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def r : FMA3, Sched<[sched]>; + + // Pattern is 312 order so that the load is in a different place from the + // 213 and 231 patterns this helps tablegen's duplicate pattern detection. + let mayLoad = 1 in + def m : FMA3, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +let Constraints = "$src1 = $dst", hasSideEffects = 0, isCommutable = 1 in +multiclass fma3p_forms opc132, bits<8> opc213, bits<8> opc231, + string OpcodeStr, string PackTy, string Suff, + PatFrag MemFrag128, PatFrag MemFrag256, + SDNode Op, ValueType OpTy128, ValueType OpTy256, + X86SchedWriteWidths sched> { + defm NAME#213#Suff : fma3p_rm_213; + defm NAME#231#Suff : fma3p_rm_231; + defm NAME#132#Suff : fma3p_rm_132; + + defm NAME#213#Suff#Y : fma3p_rm_213, + VEX_L; + defm NAME#231#Suff#Y : fma3p_rm_231, + VEX_L; + defm NAME#132#Suff#Y : fma3p_rm_132, + VEX_L; +} + +// Fused Multiply-Add +let ExeDomain = SSEPackedSingle in { + defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", "PS", + loadv4f32, loadv8f32, X86Fmadd, v4f32, v8f32, + SchedWriteFMA>; + defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", "PS", + loadv4f32, loadv8f32, X86Fmsub, v4f32, v8f32, + SchedWriteFMA>; + defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps", "PS", + loadv4f32, loadv8f32, X86Fmaddsub, v4f32, v8f32, + SchedWriteFMA>; + defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps", "PS", + loadv4f32, loadv8f32, X86Fmsubadd, v4f32, v8f32, + SchedWriteFMA>; +} + +let ExeDomain = SSEPackedDouble in { + defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", "PD", + loadv2f64, loadv4f64, X86Fmadd, v2f64, + v4f64, SchedWriteFMA>, VEX_W; + defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", "PD", + loadv2f64, loadv4f64, X86Fmsub, v2f64, + v4f64, SchedWriteFMA>, VEX_W; + defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", "PD", + loadv2f64, loadv4f64, X86Fmaddsub, + v2f64, v4f64, SchedWriteFMA>, VEX_W; + defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", "PD", + loadv2f64, loadv4f64, X86Fmsubadd, + v2f64, v4f64, SchedWriteFMA>, VEX_W; +} + +// Fused Negative Multiply-Add +let ExeDomain = SSEPackedSingle in { + defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", "PS", loadv4f32, + loadv8f32, X86Fnmadd, v4f32, v8f32, SchedWriteFMA>; + defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", "PS", loadv4f32, + loadv8f32, X86Fnmsub, v4f32, v8f32, SchedWriteFMA>; +} +let ExeDomain = SSEPackedDouble in { + defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", "PD", loadv2f64, + loadv4f64, X86Fnmadd, v2f64, v4f64, SchedWriteFMA>, VEX_W; + defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd", "PD", loadv2f64, + loadv4f64, X86Fnmsub, v2f64, v4f64, SchedWriteFMA>, VEX_W; +} + +// All source register operands of FMA opcodes defined in fma3s_rm multiclass +// can be commuted. In many cases such commute transformation requires an opcode +// adjustment, for example, commuting the operands 1 and 2 in FMA*132 form +// would require an opcode change to FMA*231: +// FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2; +// --> +// FMA*231* reg2, reg1, reg3; // reg1 * reg3 + reg2; +// Please see more detailed comment at the very beginning of the section +// defining FMA3 opcodes above. +multiclass fma3s_rm_213 opc, string OpcodeStr, + X86MemOperand x86memop, RegisterClass RC, + SDPatternOperator OpNode, + X86FoldableSchedWrite sched> { + def r : FMA3S, + Sched<[sched]>; + + let mayLoad = 1 in + def m : FMA3S, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +multiclass fma3s_rm_231 opc, string OpcodeStr, + X86MemOperand x86memop, RegisterClass RC, + SDPatternOperator OpNode, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def r : FMA3S, Sched<[sched]>; + + let mayLoad = 1 in + def m : FMA3S, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +multiclass fma3s_rm_132 opc, string OpcodeStr, + X86MemOperand x86memop, RegisterClass RC, + SDPatternOperator OpNode, X86FoldableSchedWrite sched> { + let hasSideEffects = 0 in + def r : FMA3S, Sched<[sched]>; + + // Pattern is 312 order so that the load is in a different place from the + // 213 and 231 patterns this helps tablegen's duplicate pattern detection. + let mayLoad = 1 in + def m : FMA3S, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +let Constraints = "$src1 = $dst", isCommutable = 1, hasSideEffects = 0 in +multiclass fma3s_forms opc132, bits<8> opc213, bits<8> opc231, + string OpStr, string PackTy, string Suff, + SDNode OpNode, RegisterClass RC, + X86MemOperand x86memop, X86FoldableSchedWrite sched> { + defm NAME#213#Suff : fma3s_rm_213; + defm NAME#231#Suff : fma3s_rm_231; + defm NAME#132#Suff : fma3s_rm_132; +} + +// These FMA*_Int instructions are defined specially for being used when +// the scalar FMA intrinsics are lowered to machine instructions, and in that +// sense, they are similar to existing ADD*_Int, SUB*_Int, MUL*_Int, etc. +// instructions. +// +// All of the FMA*_Int opcodes are defined as commutable here. +// Commuting the 2nd and 3rd source register operands of FMAs is quite trivial +// and the corresponding optimizations have been developed. +// Commuting the 1st operand of FMA*_Int requires some additional analysis, +// the commute optimization is legal only if all users of FMA*_Int use only +// the lowest element of the FMA*_Int instruction. Even though such analysis +// may be not implemented yet we allow the routines doing the actual commute +// transformation to decide if one or another instruction is commutable or not. +let Constraints = "$src1 = $dst", isCommutable = 1, isCodeGenOnly = 1, + hasSideEffects = 0 in +multiclass fma3s_rm_int opc, string OpcodeStr, + Operand memopr, RegisterClass RC, + X86FoldableSchedWrite sched> { + def r_Int : FMA3S_Int, Sched<[sched]>; + + let mayLoad = 1 in + def m_Int : FMA3S_Int, Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; +} + +// The FMA 213 form is created for lowering of scalar FMA intrinscis +// to machine instructions. +// The FMA 132 form can trivially be get by commuting the 2nd and 3rd operands +// of FMA 213 form. +// The FMA 231 form can be get only by commuting the 1st operand of 213 or 132 +// forms and is possible only after special analysis of all uses of the initial +// instruction. Such analysis do not exist yet and thus introducing the 231 +// form of FMA*_Int instructions is done using an optimistic assumption that +// such analysis will be implemented eventually. +multiclass fma3s_int_forms opc132, bits<8> opc213, bits<8> opc231, + string OpStr, string PackTy, string Suff, + RegisterClass RC, Operand memop, + X86FoldableSchedWrite sched> { + defm NAME#132#Suff : fma3s_rm_int; + defm NAME#213#Suff : fma3s_rm_int; + defm NAME#231#Suff : fma3s_rm_int; +} + +multiclass fma3s opc132, bits<8> opc213, bits<8> opc231, + string OpStr, SDNode OpNode, X86FoldableSchedWrite sched> { + let ExeDomain = SSEPackedSingle in + defm NAME : fma3s_forms, + fma3s_int_forms; + + let ExeDomain = SSEPackedDouble in + defm NAME : fma3s_forms, + fma3s_int_forms, VEX_W; +} + +defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", X86Fmadd, + SchedWriteFMA.Scl>, VEX_LIG; +defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", X86Fmsub, + SchedWriteFMA.Scl>, VEX_LIG; + +defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", X86Fnmadd, + SchedWriteFMA.Scl>, VEX_LIG; +defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", X86Fnmsub, + SchedWriteFMA.Scl>, VEX_LIG; + +multiclass scalar_fma_patterns { + let Predicates = [HasFMA, NoAVX512] in { + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op RC:$src2, + (EltVT (extractelt (VT VR128:$src1), (iPTR 0))), + RC:$src3))))), + (!cast(Prefix#"213"#Suffix#"r_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; + + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op RC:$src2, RC:$src3, + (EltVT (extractelt (VT VR128:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"r_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; + + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op RC:$src2, + (EltVT (extractelt (VT VR128:$src1), (iPTR 0))), + (mem_frag addr:$src3)))))), + (!cast(Prefix#"213"#Suffix#"m_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + addr:$src3)>; + + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op (EltVT (extractelt (VT VR128:$src1), (iPTR 0))), + (mem_frag addr:$src3), RC:$src2))))), + (!cast(Prefix#"132"#Suffix#"m_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + addr:$src3)>; + + def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector + (Op RC:$src2, (mem_frag addr:$src3), + (EltVT (extractelt (VT VR128:$src1), (iPTR 0)))))))), + (!cast(Prefix#"231"#Suffix#"m_Int") + VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + addr:$src3)>; + } +} + +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; + +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; +defm : scalar_fma_patterns; + +//===----------------------------------------------------------------------===// +// FMA4 - AMD 4 operand Fused Multiply-Add instructions +//===----------------------------------------------------------------------===// + +multiclass fma4s opc, string OpcodeStr, RegisterClass RC, + X86MemOperand x86memop, ValueType OpVT, SDNode OpNode, + PatFrag mem_frag, X86FoldableSchedWrite sched> { + let isCommutable = 1 in + def rr : FMA4S, VEX_W, VEX_LIG, + Sched<[sched]>; + def rm : FMA4S, VEX_W, VEX_LIG, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; + def mr : FMA4S, VEX_LIG, + Sched<[sched.Folded, ReadAfterLd, + // x86memop:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src3 + ReadAfterLd]>; +// For disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rr_REV : FMA4S, + VEX_LIG, FoldGenData, Sched<[sched]>; +} + +multiclass fma4s_int opc, string OpcodeStr, Operand memop, + ValueType VT, X86FoldableSchedWrite sched> { +let isCodeGenOnly = 1, hasSideEffects = 0 in { + def rr_Int : FMA4S_Int, VEX_W, VEX_LIG, Sched<[sched]>; + let mayLoad = 1 in + def rm_Int : FMA4S_Int, VEX_W, VEX_LIG, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; + let mayLoad = 1 in + def mr_Int : FMA4S_Int, + VEX_LIG, Sched<[sched.Folded, ReadAfterLd, + // memop:$src2 + ReadDefault, ReadDefault, ReadDefault, + ReadDefault, ReadDefault, + // VR128::$src3 + ReadAfterLd]>; + def rr_Int_REV : FMA4S_Int, VEX_LIG, FoldGenData, Sched<[sched]>; +} // isCodeGenOnly = 1 +} + +multiclass fma4p opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT128, ValueType OpVT256, + PatFrag ld_frag128, PatFrag ld_frag256, + X86SchedWriteWidths sched> { + let isCommutable = 1 in + def rr : FMA4, + VEX_W, Sched<[sched.XMM]>; + def rm : FMA4, VEX_W, + Sched<[sched.XMM.Folded, ReadAfterLd, ReadAfterLd]>; + def mr : FMA4, + Sched<[sched.XMM.Folded, ReadAfterLd, + // f128mem:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // VR128::$src3 + ReadAfterLd]>; + let isCommutable = 1 in + def Yrr : FMA4, + VEX_W, VEX_L, Sched<[sched.YMM]>; + def Yrm : FMA4, VEX_W, VEX_L, + Sched<[sched.YMM.Folded, ReadAfterLd, ReadAfterLd]>; + def Ymr : FMA4, VEX_L, + Sched<[sched.YMM.Folded, ReadAfterLd, + // f256mem:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // VR256::$src3 + ReadAfterLd]>; +// For disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { + def rr_REV : FMA4, + Sched<[sched.XMM]>, FoldGenData; + def Yrr_REV : FMA4, + VEX_L, Sched<[sched.YMM]>, FoldGenData; +} // isCodeGenOnly = 1 +} + +let ExeDomain = SSEPackedSingle in { + // Scalar Instructions + defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32, + SchedWriteFMA.Scl>, + fma4s_int<0x6A, "vfmaddss", ssmem, v4f32, + SchedWriteFMA.Scl>; + defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32, + SchedWriteFMA.Scl>, + fma4s_int<0x6E, "vfmsubss", ssmem, v4f32, + SchedWriteFMA.Scl>; + defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32, + X86Fnmadd, loadf32, SchedWriteFMA.Scl>, + fma4s_int<0x7A, "vfnmaddss", ssmem, v4f32, + SchedWriteFMA.Scl>; + defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32, + X86Fnmsub, loadf32, SchedWriteFMA.Scl>, + fma4s_int<0x7E, "vfnmsubss", ssmem, v4f32, + SchedWriteFMA.Scl>; + // Packed Instructions + defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; + defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32, + loadv4f32, loadv8f32, SchedWriteFMA>; +} + +let ExeDomain = SSEPackedDouble in { + // Scalar Instructions + defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64, + SchedWriteFMA.Scl>, + fma4s_int<0x6B, "vfmaddsd", sdmem, v2f64, + SchedWriteFMA.Scl>; + defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64, + SchedWriteFMA.Scl>, + fma4s_int<0x6F, "vfmsubsd", sdmem, v2f64, + SchedWriteFMA.Scl>; + defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64, + X86Fnmadd, loadf64, SchedWriteFMA.Scl>, + fma4s_int<0x7B, "vfnmaddsd", sdmem, v2f64, + SchedWriteFMA.Scl>; + defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64, + X86Fnmsub, loadf64, SchedWriteFMA.Scl>, + fma4s_int<0x7F, "vfnmsubsd", sdmem, v2f64, + SchedWriteFMA.Scl>; + // Packed Instructions + defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; + defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64, + loadv2f64, loadv4f64, SchedWriteFMA>; +} + +multiclass scalar_fma4_patterns { + let Predicates = [HasFMA4] in { + def : Pat<(VT (X86vzmovl (VT (scalar_to_vector + (Op RC:$src1, RC:$src2, RC:$src3))))), + (!cast(Name#"rr_Int") + (VT (COPY_TO_REGCLASS RC:$src1, VR128)), + (VT (COPY_TO_REGCLASS RC:$src2, VR128)), + (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; + + def : Pat<(VT (X86vzmovl (VT (scalar_to_vector + (Op RC:$src1, RC:$src2, + (mem_frag addr:$src3)))))), + (!cast(Name#"rm_Int") + (VT (COPY_TO_REGCLASS RC:$src1, VR128)), + (VT (COPY_TO_REGCLASS RC:$src2, VR128)), addr:$src3)>; + + def : Pat<(VT (X86vzmovl (VT (scalar_to_vector + (Op RC:$src1, (mem_frag addr:$src2), + RC:$src3))))), + (!cast(Name#"mr_Int") + (VT (COPY_TO_REGCLASS RC:$src1, VR128)), addr:$src2, + (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; + } +} + +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; + +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrFPStack.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrFPStack.td new file mode 100644 index 0000000..a21f077 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrFPStack.td @@ -0,0 +1,748 @@ +//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 x87 FPU instruction set, defining the +// instructions, and properties of the instructions which are needed for code +// generation, machine code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// FPStack specific DAG Nodes. +//===----------------------------------------------------------------------===// + +def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>, + SDTCisVT<1, f80>]>; +def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, + SDTCisPtrTy<1>, + SDTCisVT<2, OtherVT>]>; +def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, + SDTCisPtrTy<1>, + SDTCisVT<2, OtherVT>]>; +def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, + SDTCisVT<2, OtherVT>]>; +def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; +def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; + +def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; + +def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; +def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, + [SDNPHasChain, SDNPInGlue, SDNPMayStore, + SDNPMemOperand]>; +def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; +def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, + [SDNPHasChain, SDNPOutGlue, SDNPMayLoad, + SDNPMemOperand]>; +def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; +def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, + [SDNPHasChain, SDNPMayStore, SDNPSideEffect, + SDNPMemOperand]>; + +//===----------------------------------------------------------------------===// +// FPStack pattern fragments +//===----------------------------------------------------------------------===// + +def fpimm0 : FPImmLeaf; + +def fpimmneg0 : FPImmLeaf; + +def fpimm1 : FPImmLeaf; + +def fpimmneg1 : FPImmLeaf; + +/* +// Some 'special' instructions - expanded after instruction selection. +let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { + def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), + [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; + def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), + [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; + def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), + [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; + def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), + [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; + def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), + [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; + def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), + [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; + def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), + [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; + def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), + [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; + def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), + [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; +} +*/ + +// All FP Stack operations are represented with four instructions here. The +// first three instructions, generated by the instruction selector, use "RFP32" +// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, +// 64-bit or 80-bit floating point values. These sizes apply to the values, +// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be +// copied to each other without losing information. These instructions are all +// pseudo instructions and use the "_Fp" suffix. +// In some cases there are additional variants with a mixture of different +// register sizes. +// The second instruction is defined with FPI, which is the actual instruction +// emitted by the assembler. These use "RST" registers, although frequently +// the actual register(s) used are implicit. These are always 80 bits. +// The FP stackifier pass converts one to the other after register allocation +// occurs. +// +// Note that the FpI instruction should have instruction selection info (e.g. +// a pattern) and the FPI instruction should have emission info (e.g. opcode +// encoding and asm printing info). + +// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. +// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. +// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. +// f80 instructions cannot use SSE and use neither of these. +class FpIf32 pattern> : + FpI_, Requires<[FPStackf32]>; +class FpIf64 pattern> : + FpI_, Requires<[FPStackf64]>; + +// Factoring for arithmetic. +multiclass FPBinary_rr { +// Register op register -> register +// These are separated out because they have no reversed form. +def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, + [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; +def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, + [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; +def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, + [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; +} +// The FopST0 series are not included here because of the irregularities +// in where the 'r' goes in assembly output. +// These instructions cannot address 80-bit memory. +multiclass FPBinary { +let mayLoad = 1, hasSideEffects = 1 in { +// ST(0) = ST(0) + [mem] +def _Fp32m : FpIf32<(outs RFP32:$dst), + (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, + [!if(Forward, + (set RFP32:$dst, + (OpNode RFP32:$src1, (loadf32 addr:$src2))), + (set RFP32:$dst, + (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; +def _Fp64m : FpIf64<(outs RFP64:$dst), + (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, + [!if(Forward, + (set RFP64:$dst, + (OpNode RFP64:$src1, (loadf64 addr:$src2))), + (set RFP64:$dst, + (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; +def _Fp64m32: FpIf64<(outs RFP64:$dst), + (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, + [!if(Forward, + (set RFP64:$dst, + (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), + (set RFP64:$dst, + (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; +def _Fp80m32: FpI_<(outs RFP80:$dst), + (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, + [!if(Forward, + (set RFP80:$dst, + (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), + (set RFP80:$dst, + (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; +def _Fp80m64: FpI_<(outs RFP80:$dst), + (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, + [!if(Forward, + (set RFP80:$dst, + (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), + (set RFP80:$dst, + (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; +def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), + !strconcat("f", asmstring, "{s}\t$src")>; +def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), + !strconcat("f", asmstring, "{l}\t$src")>; +// ST(0) = ST(0) + [memint] +def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), + OneArgFPRW, + [!if(Forward, + (set RFP32:$dst, + (OpNode RFP32:$src1, (X86fild addr:$src2, i16))), + (set RFP32:$dst, + (OpNode (X86fild addr:$src2, i16), RFP32:$src1)))]>; +def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), + OneArgFPRW, + [!if(Forward, + (set RFP32:$dst, + (OpNode RFP32:$src1, (X86fild addr:$src2, i32))), + (set RFP32:$dst, + (OpNode (X86fild addr:$src2, i32), RFP32:$src1)))]>; +def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), + OneArgFPRW, + [!if(Forward, + (set RFP64:$dst, + (OpNode RFP64:$src1, (X86fild addr:$src2, i16))), + (set RFP64:$dst, + (OpNode (X86fild addr:$src2, i16), RFP64:$src1)))]>; +def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), + OneArgFPRW, + [!if(Forward, + (set RFP64:$dst, + (OpNode RFP64:$src1, (X86fild addr:$src2, i32))), + (set RFP64:$dst, + (OpNode (X86fild addr:$src2, i32), RFP64:$src1)))]>; +def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), + OneArgFPRW, + [!if(Forward, + (set RFP80:$dst, + (OpNode RFP80:$src1, (X86fild addr:$src2, i16))), + (set RFP80:$dst, + (OpNode (X86fild addr:$src2, i16), RFP80:$src1)))]>; +def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), + OneArgFPRW, + [!if(Forward, + (set RFP80:$dst, + (OpNode RFP80:$src1, (X86fild addr:$src2, i32))), + (set RFP80:$dst, + (OpNode (X86fild addr:$src2, i32), RFP80:$src1)))]>; +def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), + !strconcat("fi", asmstring, "{s}\t$src")>; +def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), + !strconcat("fi", asmstring, "{l}\t$src")>; +} // mayLoad = 1, hasSideEffects = 1 +} + +let Defs = [FPSW] in { +// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling +// resources. +let hasNoSchedulingInfo = 1 in { +defm ADD : FPBinary_rr; +defm SUB : FPBinary_rr; +defm MUL : FPBinary_rr; +defm DIV : FPBinary_rr; +} + +// Sets the scheduling resources for the actual NAME#_Fm definitions. +let SchedRW = [WriteFAddLd] in { +defm ADD : FPBinary; +defm SUB : FPBinary; +defm SUBR: FPBinary; +} + +let SchedRW = [WriteFMulLd] in { +defm MUL : FPBinary; +} + +let SchedRW = [WriteFDivLd] in { +defm DIV : FPBinary; +defm DIVR: FPBinary; +} +} // Defs = [FPSW] + +class FPST0rInst + : FPI<0xD8, fp, (outs), (ins RST:$op), asm>; +class FPrST0Inst + : FPI<0xDC, fp, (outs), (ins RST:$op), asm>; +class FPrST0PInst + : FPI<0xDE, fp, (outs), (ins RST:$op), asm>; + +// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion +// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, +// we have to put some 'r's in and take them out of weird places. +let SchedRW = [WriteFAdd] in { +def ADD_FST0r : FPST0rInst ; +def ADD_FrST0 : FPrST0Inst ; +def ADD_FPrST0 : FPrST0PInst; +def SUBR_FST0r : FPST0rInst ; +def SUB_FrST0 : FPrST0Inst ; +def SUB_FPrST0 : FPrST0PInst; +def SUB_FST0r : FPST0rInst ; +def SUBR_FrST0 : FPrST0Inst ; +def SUBR_FPrST0 : FPrST0PInst; +} // SchedRW +let SchedRW = [WriteFCom] in { +def COM_FST0r : FPST0rInst ; +def COMP_FST0r : FPST0rInst ; +} // SchedRW +let SchedRW = [WriteFMul] in { +def MUL_FST0r : FPST0rInst ; +def MUL_FrST0 : FPrST0Inst ; +def MUL_FPrST0 : FPrST0PInst; +} // SchedRW +let SchedRW = [WriteFDiv] in { +def DIVR_FST0r : FPST0rInst ; +def DIV_FrST0 : FPrST0Inst ; +def DIV_FPrST0 : FPrST0PInst; +def DIV_FST0r : FPST0rInst ; +def DIVR_FrST0 : FPrST0Inst ; +def DIVR_FPrST0 : FPrST0PInst; +} // SchedRW + +// Unary operations. +multiclass FPUnary { +def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, + [(set RFP32:$dst, (OpNode RFP32:$src))]>; +def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, + [(set RFP64:$dst, (OpNode RFP64:$src))]>; +def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, + [(set RFP80:$dst, (OpNode RFP80:$src))]>; +def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; +} + +let Defs = [FPSW] in { + +let SchedRW = [WriteFSign] in { +defm CHS : FPUnary; +defm ABS : FPUnary; +} + +let SchedRW = [WriteFSqrt80] in +defm SQRT: FPUnary; + +let SchedRW = [WriteMicrocoded] in { +defm SIN : FPUnary; +defm COS : FPUnary; +} + +let SchedRW = [WriteFCom] in { +let hasSideEffects = 0 in { +def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; +def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; +def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; +} // hasSideEffects + +def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; +} // SchedRW +} // Defs = [FPSW] + +// Versions of FP instructions that take a single memory operand. Added for the +// disassembler; remove as they are included with patterns elsewhere. +let SchedRW = [WriteFComLd] in { +def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; +def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; + +def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; +def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; + +def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; +def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; + +def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; +def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; +} // SchedRW + +let SchedRW = [WriteMicrocoded] in { +def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; +def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">; + +def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">; +def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">; +def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; + +def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\ttbyte ptr $src">; +def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\ttbyte ptr $dst">; +} // SchedRW + +// Floating point cmovs. +class FpIf32CMov pattern> : + FpI_, Requires<[FPStackf32, HasCMov]>; +class FpIf64CMov pattern> : + FpI_, Requires<[FPStackf64, HasCMov]>; + +multiclass FPCMov { + def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), + CondMovFP, + [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, + cc, EFLAGS))]>; + def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), + CondMovFP, + [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, + cc, EFLAGS))]>; + def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), + CondMovFP, + [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, + cc, EFLAGS))]>, + Requires<[HasCMov]>; +} + +let Defs = [FPSW] in { +let SchedRW = [WriteFCMOV] in { +let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { +defm CMOVB : FPCMov; +defm CMOVBE : FPCMov; +defm CMOVE : FPCMov; +defm CMOVP : FPCMov; +defm CMOVNB : FPCMov; +defm CMOVNBE: FPCMov; +defm CMOVNE : FPCMov; +defm CMOVNP : FPCMov; +} // Uses = [EFLAGS], Constraints = "$src1 = $dst" + +let Predicates = [HasCMov] in { +// These are not factored because there's no clean way to pass DA/DB. +def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RST:$op), + "fcmovb\t{$op, %st(0)|st(0), $op}">; +def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RST:$op), + "fcmovbe\t{$op, %st(0)|st(0), $op}">; +def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op), + "fcmove\t{$op, %st(0)|st(0), $op}">; +def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RST:$op), + "fcmovu\t{$op, %st(0)|st(0), $op}">; +def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RST:$op), + "fcmovnb\t{$op, %st(0)|st(0), $op}">; +def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RST:$op), + "fcmovnbe\t{$op, %st(0)|st(0), $op}">; +def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op), + "fcmovne\t{$op, %st(0)|st(0), $op}">; +def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op), + "fcmovnu\t{$op, %st(0)|st(0), $op}">; +} // Predicates = [HasCMov] +} // SchedRW + +// Floating point loads & stores. +let SchedRW = [WriteLoad] in { +let canFoldAsLoad = 1 in { +def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, + [(set RFP32:$dst, (loadf32 addr:$src))]>; +let isReMaterializable = 1 in + def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, + [(set RFP64:$dst, (loadf64 addr:$src))]>; +def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, + [(set RFP80:$dst, (loadf80 addr:$src))]>; +} // canFoldAsLoad +def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, + [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; +def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, + [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; +def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, + [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; +def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, + [(set RFP32:$dst, (X86fild addr:$src, i16))]>; +def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, + [(set RFP32:$dst, (X86fild addr:$src, i32))]>; +def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, + [(set RFP32:$dst, (X86fild addr:$src, i64))]>; +def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, + [(set RFP64:$dst, (X86fild addr:$src, i16))]>; +def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, + [(set RFP64:$dst, (X86fild addr:$src, i32))]>; +def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, + [(set RFP64:$dst, (X86fild addr:$src, i64))]>; +def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, + [(set RFP80:$dst, (X86fild addr:$src, i16))]>; +def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, + [(set RFP80:$dst, (X86fild addr:$src, i32))]>; +def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, + [(set RFP80:$dst, (X86fild addr:$src, i64))]>; +} // SchedRW + +let SchedRW = [WriteStore] in { +def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, + [(store RFP32:$src, addr:$op)]>; +def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, + [(truncstoref32 RFP64:$src, addr:$op)]>; +def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, + [(store RFP64:$src, addr:$op)]>; +def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, + [(truncstoref32 RFP80:$src, addr:$op)]>; +def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, + [(truncstoref64 RFP80:$src, addr:$op)]>; +// FST does not support 80-bit memory target; FSTP must be used. + +let mayStore = 1, hasSideEffects = 0 in { +def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; +def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; +def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; +def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; +def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; +} // mayStore + +def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, + [(store RFP80:$src, addr:$op)]>; + +let mayStore = 1, hasSideEffects = 0 in { +def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; +def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; +def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; +} // mayStore +} // SchedRW + +let mayLoad = 1, SchedRW = [WriteLoad] in { +def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; +def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">; +def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">; +def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">; +def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; +def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; +} +let mayStore = 1, SchedRW = [WriteStore] in { +def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; +def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; +def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; +def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">; +def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">; +def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">; +def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">; +def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">; +def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">; +def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">; +} + +// FISTTP requires SSE3 even though it's a FPStack op. +let Predicates = [HasSSE3], SchedRW = [WriteStore] in { +def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, + [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; +def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, + [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; +def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, + [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; +def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, + [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; +def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, + [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; +def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, + [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; +def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, + [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; +def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, + [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; +def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, + [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; +} // Predicates = [HasSSE3] + +let mayStore = 1, SchedRW = [WriteStore] in { +def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; +def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; +def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; +} + +// FP Stack manipulation instructions. +let SchedRW = [WriteMove] in { +def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op">; +def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op">; +def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op">; +def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op">; +} + +// Floating point constant loads. +let isReMaterializable = 1, SchedRW = [WriteZero] in { +def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, + [(set RFP32:$dst, fpimm0)]>; +def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, + [(set RFP32:$dst, fpimm1)]>; +def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, + [(set RFP64:$dst, fpimm0)]>; +def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, + [(set RFP64:$dst, fpimm1)]>; +def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, + [(set RFP80:$dst, fpimm0)]>; +def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, + [(set RFP80:$dst, fpimm1)]>; +} + +let SchedRW = [WriteFLD0] in +def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; + +let SchedRW = [WriteFLD1] in +def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">; + +let SchedRW = [WriteFLDC], Defs = [FPSW] in { +def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>; +def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>; +def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>; +def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>; +def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>; +} // SchedRW + +// Floating point compares. +let SchedRW = [WriteFCom] in { +def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, + [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>; +def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, + [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>; +def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, + [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>; +} // SchedRW +} // Defs = [FPSW] + +let SchedRW = [WriteFCom] in { +// CC = ST(0) cmp ST(i) +let Defs = [EFLAGS, FPSW] in { +def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, + [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>; +def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, + [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>; +def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; +} + +let Defs = [FPSW], Uses = [ST0] in { +def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) + (outs), (ins RST:$reg), "fucom\t$reg">; +def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop + (outs), (ins RST:$reg), "fucomp\t$reg">; +def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop + (outs), (ins), "fucompp">; +} + +let Defs = [EFLAGS, FPSW], Uses = [ST0] in { +def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) + (outs), (ins RST:$reg), "fucomi\t$reg">; +def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop + (outs), (ins RST:$reg), "fucompi\t$reg">; +} + +let Defs = [EFLAGS, FPSW] in { +def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg), "fcomi\t$reg">; +def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), "fcompi\t$reg">; +} +} // SchedRW + +// Floating point flag ops. +let SchedRW = [WriteALU] in { +let Defs = [AX], Uses = [FPSW] in +def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags + (outs), (ins), "fnstsw\t{%ax|ax}", + [(set AX, (X86fp_stsw FPSW))]>; +let Defs = [FPSW] in +def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world + (outs), (ins i16mem:$dst), "fnstcw\t$dst", + [(X86fp_cwd_get16 addr:$dst)]>; +} // SchedRW +let Defs = [FPSW], mayLoad = 1 in +def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] + (outs), (ins i16mem:$dst), "fldcw\t$dst", []>, + Sched<[WriteLoad]>; + +// FPU control instructions +let SchedRW = [WriteMicrocoded] in { +let Defs = [FPSW] in { +def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>; +def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), "ffree\t$reg">; +def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RST:$reg), "ffreep\t$reg">; + +def FPNCEST0r : FPI<0xD9, MRM3r, (outs RST:$op), (ins), + "fstpnce\t{%st(0), $op|$op, st(0)}">; + +def FENI8087_NOP : I<0xDB, MRM_E0, (outs), (ins), "feni8087_nop", []>; + +def FDISI8087_NOP : I<0xDB, MRM_E1, (outs), (ins), "fdisi8087_nop", []>; + +// Clear exceptions +def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>; +} // Defs = [FPSW] +} // SchedRW + +// Operand-less floating-point instructions for the disassembler. +def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>; + +let SchedRW = [WriteMicrocoded] in { +let Defs = [FPSW] in { +def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; +def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>; +def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>; +def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>; +def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>; +def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>; +def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>; +def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>; +def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>; +def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>; +def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>; +def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>; +def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>; +def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>; +def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>; +def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>; +} // Defs = [FPSW] + +def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst), + "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB, + Requires<[HasFXSR]>; +def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst), + "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>, + TB, Requires<[HasFXSR, In64BitMode]>; +def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src), + "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>, + TB, Requires<[HasFXSR]>; +def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src), + "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>, + TB, Requires<[HasFXSR, In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Non-Instruction Patterns +//===----------------------------------------------------------------------===// + +// Required for RET of f32 / f64 / f80 values. +def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>; +def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>; +def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>; + +// Required for CALL which return f32 / f64 / f80 values. +def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>; +def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, + RFP64:$src)>; +def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>; +def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, + RFP80:$src)>; +def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, + RFP80:$src)>; +def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, + RFP80:$src)>; + +// Floating point constant -0.0 and -1.0 +def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; +def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; +def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; +def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; +def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; +def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; + +// Used to conv. i64 to f64 since there isn't a SSE version. +def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>; + +// FP extensions map onto simple pseudo-value conversions if they are to/from +// the FP stack. +def : Pat<(f64 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, + Requires<[FPStackf32]>; +def : Pat<(f80 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, + Requires<[FPStackf32]>; +def : Pat<(f80 (fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, + Requires<[FPStackf64]>; + +// FP truncations map onto simple pseudo-value conversions if they are to/from +// the FP stack. We have validated that only value-preserving truncations make +// it through isel. +def : Pat<(f32 (fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, + Requires<[FPStackf32]>; +def : Pat<(f32 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, + Requires<[FPStackf32]>; +def : Pat<(f64 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, + Requires<[FPStackf64]>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrFormats.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrFormats.td new file mode 100644 index 0000000..47d4719 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrFormats.td @@ -0,0 +1,993 @@ +//===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// X86 Instruction Format Definitions. +// + +// Format specifies the encoding used by the instruction. This is part of the +// ad-hoc solution used to emit machine instruction encodings by our machine +// code emitter. +class Format val> { + bits<7> Value = val; +} + +def Pseudo : Format<0>; +def RawFrm : Format<1>; +def AddRegFrm : Format<2>; +def RawFrmMemOffs : Format<3>; +def RawFrmSrc : Format<4>; +def RawFrmDst : Format<5>; +def RawFrmDstSrc : Format<6>; +def RawFrmImm8 : Format<7>; +def RawFrmImm16 : Format<8>; +def MRMDestMem : Format<32>; +def MRMSrcMem : Format<33>; +def MRMSrcMem4VOp3 : Format<34>; +def MRMSrcMemOp4 : Format<35>; +def MRMXm : Format<39>; +def MRM0m : Format<40>; def MRM1m : Format<41>; def MRM2m : Format<42>; +def MRM3m : Format<43>; def MRM4m : Format<44>; def MRM5m : Format<45>; +def MRM6m : Format<46>; def MRM7m : Format<47>; +def MRMDestReg : Format<48>; +def MRMSrcReg : Format<49>; +def MRMSrcReg4VOp3 : Format<50>; +def MRMSrcRegOp4 : Format<51>; +def MRMXr : Format<55>; +def MRM0r : Format<56>; def MRM1r : Format<57>; def MRM2r : Format<58>; +def MRM3r : Format<59>; def MRM4r : Format<60>; def MRM5r : Format<61>; +def MRM6r : Format<62>; def MRM7r : Format<63>; +def MRM_C0 : Format<64>; def MRM_C1 : Format<65>; def MRM_C2 : Format<66>; +def MRM_C3 : Format<67>; def MRM_C4 : Format<68>; def MRM_C5 : Format<69>; +def MRM_C6 : Format<70>; def MRM_C7 : Format<71>; def MRM_C8 : Format<72>; +def MRM_C9 : Format<73>; def MRM_CA : Format<74>; def MRM_CB : Format<75>; +def MRM_CC : Format<76>; def MRM_CD : Format<77>; def MRM_CE : Format<78>; +def MRM_CF : Format<79>; def MRM_D0 : Format<80>; def MRM_D1 : Format<81>; +def MRM_D2 : Format<82>; def MRM_D3 : Format<83>; def MRM_D4 : Format<84>; +def MRM_D5 : Format<85>; def MRM_D6 : Format<86>; def MRM_D7 : Format<87>; +def MRM_D8 : Format<88>; def MRM_D9 : Format<89>; def MRM_DA : Format<90>; +def MRM_DB : Format<91>; def MRM_DC : Format<92>; def MRM_DD : Format<93>; +def MRM_DE : Format<94>; def MRM_DF : Format<95>; def MRM_E0 : Format<96>; +def MRM_E1 : Format<97>; def MRM_E2 : Format<98>; def MRM_E3 : Format<99>; +def MRM_E4 : Format<100>; def MRM_E5 : Format<101>; def MRM_E6 : Format<102>; +def MRM_E7 : Format<103>; def MRM_E8 : Format<104>; def MRM_E9 : Format<105>; +def MRM_EA : Format<106>; def MRM_EB : Format<107>; def MRM_EC : Format<108>; +def MRM_ED : Format<109>; def MRM_EE : Format<110>; def MRM_EF : Format<111>; +def MRM_F0 : Format<112>; def MRM_F1 : Format<113>; def MRM_F2 : Format<114>; +def MRM_F3 : Format<115>; def MRM_F4 : Format<116>; def MRM_F5 : Format<117>; +def MRM_F6 : Format<118>; def MRM_F7 : Format<119>; def MRM_F8 : Format<120>; +def MRM_F9 : Format<121>; def MRM_FA : Format<122>; def MRM_FB : Format<123>; +def MRM_FC : Format<124>; def MRM_FD : Format<125>; def MRM_FE : Format<126>; +def MRM_FF : Format<127>; + +// ImmType - This specifies the immediate type used by an instruction. This is +// part of the ad-hoc solution used to emit machine instruction encodings by our +// machine code emitter. +class ImmType val> { + bits<4> Value = val; +} +def NoImm : ImmType<0>; +def Imm8 : ImmType<1>; +def Imm8PCRel : ImmType<2>; +def Imm8Reg : ImmType<3>; // Register encoded in [7:4]. +def Imm16 : ImmType<4>; +def Imm16PCRel : ImmType<5>; +def Imm32 : ImmType<6>; +def Imm32PCRel : ImmType<7>; +def Imm32S : ImmType<8>; +def Imm64 : ImmType<9>; + +// FPFormat - This specifies what form this FP instruction has. This is used by +// the Floating-Point stackifier pass. +class FPFormat val> { + bits<3> Value = val; +} +def NotFP : FPFormat<0>; +def ZeroArgFP : FPFormat<1>; +def OneArgFP : FPFormat<2>; +def OneArgFPRW : FPFormat<3>; +def TwoArgFP : FPFormat<4>; +def CompareFP : FPFormat<5>; +def CondMovFP : FPFormat<6>; +def SpecialFP : FPFormat<7>; + +// Class specifying the SSE execution domain, used by the SSEDomainFix pass. +// Keep in sync with tables in X86InstrInfo.cpp. +class Domain val> { + bits<2> Value = val; +} +def GenericDomain : Domain<0>; +def SSEPackedSingle : Domain<1>; +def SSEPackedDouble : Domain<2>; +def SSEPackedInt : Domain<3>; + +// Class specifying the vector form of the decompressed +// displacement of 8-bit. +class CD8VForm val> { + bits<3> Value = val; +} +def CD8VF : CD8VForm<0>; // v := VL +def CD8VH : CD8VForm<1>; // v := VL/2 +def CD8VQ : CD8VForm<2>; // v := VL/4 +def CD8VO : CD8VForm<3>; // v := VL/8 +// The tuple (subvector) forms. +def CD8VT1 : CD8VForm<4>; // v := 1 +def CD8VT2 : CD8VForm<5>; // v := 2 +def CD8VT4 : CD8VForm<6>; // v := 4 +def CD8VT8 : CD8VForm<7>; // v := 8 + +// Class specifying the prefix used an opcode extension. +class Prefix val> { + bits<3> Value = val; +} +def NoPrfx : Prefix<0>; +def PD : Prefix<1>; +def XS : Prefix<2>; +def XD : Prefix<3>; +def PS : Prefix<4>; // Similar to NoPrfx, but disassembler uses this to know + // that other instructions with this opcode use PD/XS/XD + // and if any of those is not supported they shouldn't + // decode to this instruction. e.g. ANDSS/ANDSD don't + // exist, but the 0xf2/0xf3 encoding shouldn't + // disable to ANDPS. + +// Class specifying the opcode map. +class Map val> { + bits<3> Value = val; +} +def OB : Map<0>; +def TB : Map<1>; +def T8 : Map<2>; +def TA : Map<3>; +def XOP8 : Map<4>; +def XOP9 : Map<5>; +def XOPA : Map<6>; +def ThreeDNow : Map<7>; + +// Class specifying the encoding +class Encoding val> { + bits<2> Value = val; +} +def EncNormal : Encoding<0>; +def EncVEX : Encoding<1>; +def EncXOP : Encoding<2>; +def EncEVEX : Encoding<3>; + +// Operand size for encodings that change based on mode. +class OperandSize val> { + bits<2> Value = val; +} +def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix. +def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode. +def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode. + +// Address size for encodings that change based on mode. +class AddressSize val> { + bits<2> Value = val; +} +def AdSizeX : AddressSize<0>; // Address size determined using addr operand. +def AdSize16 : AddressSize<1>; // Encodes a 16-bit address. +def AdSize32 : AddressSize<2>; // Encodes a 32-bit address. +def AdSize64 : AddressSize<3>; // Encodes a 64-bit address. + +// Prefix byte classes which are used to indicate to the ad-hoc machine code +// emitter that various prefix bytes are required. +class OpSize16 { OperandSize OpSize = OpSize16; } +class OpSize32 { OperandSize OpSize = OpSize32; } +class AdSize16 { AddressSize AdSize = AdSize16; } +class AdSize32 { AddressSize AdSize = AdSize32; } +class AdSize64 { AddressSize AdSize = AdSize64; } +class REX_W { bit hasREX_WPrefix = 1; } +class LOCK { bit hasLockPrefix = 1; } +class REP { bit hasREPPrefix = 1; } +class TB { Map OpMap = TB; } +class T8 { Map OpMap = T8; } +class TA { Map OpMap = TA; } +class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; } +class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; } +class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; } +class ThreeDNow { Map OpMap = ThreeDNow; } +class OBXS { Prefix OpPrefix = XS; } +class PS : TB { Prefix OpPrefix = PS; } +class PD : TB { Prefix OpPrefix = PD; } +class XD : TB { Prefix OpPrefix = XD; } +class XS : TB { Prefix OpPrefix = XS; } +class T8PS : T8 { Prefix OpPrefix = PS; } +class T8PD : T8 { Prefix OpPrefix = PD; } +class T8XD : T8 { Prefix OpPrefix = XD; } +class T8XS : T8 { Prefix OpPrefix = XS; } +class TAPS : TA { Prefix OpPrefix = PS; } +class TAPD : TA { Prefix OpPrefix = PD; } +class TAXD : TA { Prefix OpPrefix = XD; } +class VEX { Encoding OpEnc = EncVEX; } +class VEX_W { bits<2> VEX_WPrefix = 1; } +class VEX_WIG { bits<2> VEX_WPrefix = 2; } +// Special version of VEX_W that can be changed to VEX.W==0 for EVEX2VEX. +// FIXME: We should consider adding separate bits for VEX_WIG and the extra +// part of W1X. This would probably simplify the tablegen emitters and +// the TSFlags creation below. +class VEX_W1X { bits<2> VEX_WPrefix = 3; } +class VEX_4V : VEX { bit hasVEX_4V = 1; } +class VEX_L { bit hasVEX_L = 1; } +class VEX_LIG { bit ignoresVEX_L = 1; } +class EVEX { Encoding OpEnc = EncEVEX; } +class EVEX_4V : EVEX { bit hasVEX_4V = 1; } +class EVEX_K { bit hasEVEX_K = 1; } +class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; } +class EVEX_B { bit hasEVEX_B = 1; } +class EVEX_RC { bit hasEVEX_RC = 1; } +class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; } +class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; } +class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; } +class NOTRACK { bit hasNoTrackPrefix = 1; } + +// Specify AVX512 8-bit compressed displacement encoding based on the vector +// element size in bits (8, 16, 32, 64) and the CDisp8 form. +class EVEX_CD8 { + int CD8_EltSize = !srl(esize, 3); + bits<3> CD8_Form = form.Value; +} + +class XOP { Encoding OpEnc = EncXOP; } +class XOP_4V : XOP { bit hasVEX_4V = 1; } + +// Specify the alternative register form instruction to replace the current +// instruction in case it was picked during generation of memory folding tables +class FoldGenData { + string FoldGenRegForm = _RegisterForm; +} + +// Provide a specific instruction to be used by the EVEX2VEX conversion. +class EVEX2VEXOverride { + string EVEX2VEXOverride = VEXInstrName; +} + +// Mark the instruction as "illegal to memory fold/unfold" +class NotMemoryFoldable { bit isMemoryFoldable = 0; } + +// Prevent EVEX->VEX conversion from considering this instruction. +class NotEVEX2VEXConvertible { bit notEVEX2VEXConvertible = 1; } + +class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, + string AsmStr, Domain d = GenericDomain> + : Instruction { + let Namespace = "X86"; + + bits<8> Opcode = opcod; + Format Form = f; + bits<7> FormBits = Form.Value; + ImmType ImmT = i; + + dag OutOperandList = outs; + dag InOperandList = ins; + string AsmString = AsmStr; + + // If this is a pseudo instruction, mark it isCodeGenOnly. + let isCodeGenOnly = !eq(!cast(f), "Pseudo"); + + // + // Attributes specific to X86 instructions... + // + bit ForceDisassemble = 0; // Force instruction to disassemble even though it's + // isCodeGenonly. Needed to hide an ambiguous + // AsmString from the parser, but still disassemble. + + OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change + // based on operand size of the mode? + bits<2> OpSizeBits = OpSize.Value; + AddressSize AdSize = AdSizeX; // Does this instruction's encoding change + // based on address size of the mode? + bits<2> AdSizeBits = AdSize.Value; + + Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have? + bits<3> OpPrefixBits = OpPrefix.Value; + Map OpMap = OB; // Which opcode map does this inst have? + bits<3> OpMapBits = OpMap.Value; + bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix? + FPFormat FPForm = NotFP; // What flavor of FP instruction is this? + bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? + Domain ExeDomain = d; + bit hasREPPrefix = 0; // Does this inst have a REP prefix? + Encoding OpEnc = EncNormal; // Encoding used by this instruction + bits<2> OpEncBits = OpEnc.Value; + bits<2> VEX_WPrefix = 0; // Does this inst set the VEX_W field? + bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field? + bit hasVEX_L = 0; // Does this inst use large (256-bit) registers? + bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit + bit hasEVEX_K = 0; // Does this inst require masking? + bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field? + bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field? + bit hasEVEX_B = 0; // Does this inst set the EVEX_B field? + bits<3> CD8_Form = 0; // Compressed disp8 form - vector-width. + // Declare it int rather than bits<4> so that all bits are defined when + // assigning to bits<7>. + int CD8_EltSize = 0; // Compressed disp8 form - element-size in bytes. + bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction. + bit hasNoTrackPrefix = 0; // Does this inst has 0x3E (NoTrack) prefix? + + bits<2> EVEX_LL; + let EVEX_LL{0} = hasVEX_L; + let EVEX_LL{1} = hasEVEX_L2; + // Vector size in bytes. + bits<7> VectSize = !shl(16, EVEX_LL); + + // The scaling factor for AVX512's compressed displacement is either + // - the size of a power-of-two number of elements or + // - the size of a single element for broadcasts or + // - the total vector size divided by a power-of-two number. + // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64. + bits<7> CD8_Scale = !if (!eq (OpEnc.Value, EncEVEX.Value), + !if (CD8_Form{2}, + !shl(CD8_EltSize, CD8_Form{1-0}), + !if (hasEVEX_B, + CD8_EltSize, + !srl(VectSize, CD8_Form{1-0}))), 0); + + // Used in the memory folding generation (TableGen backend) to point to an alternative + // instruction to replace the current one in case it got picked during generation. + string FoldGenRegForm = ?; + + // Used to prevent an explicit EVEX2VEX override for this instruction. + string EVEX2VEXOverride = ?; + + bit isMemoryFoldable = 1; // Is it allowed to memory fold/unfold this instruction? + bit notEVEX2VEXConvertible = 0; // Prevent EVEX->VEX conversion. + + // TSFlags layout should be kept in sync with X86BaseInfo.h. + let TSFlags{6-0} = FormBits; + let TSFlags{8-7} = OpSizeBits; + let TSFlags{10-9} = AdSizeBits; + // No need for 3rd bit, we don't need to distinguish NoPrfx from PS. + let TSFlags{12-11} = OpPrefixBits{1-0}; + let TSFlags{15-13} = OpMapBits; + let TSFlags{16} = hasREX_WPrefix; + let TSFlags{20-17} = ImmT.Value; + let TSFlags{23-21} = FPForm.Value; + let TSFlags{24} = hasLockPrefix; + let TSFlags{25} = hasREPPrefix; + let TSFlags{27-26} = ExeDomain.Value; + let TSFlags{29-28} = OpEncBits; + let TSFlags{37-30} = Opcode; + // Currently no need for second bit in TSFlags - W Ignore is equivalent to 0. + let TSFlags{38} = VEX_WPrefix{0}; + let TSFlags{39} = hasVEX_4V; + let TSFlags{40} = hasVEX_L; + let TSFlags{41} = hasEVEX_K; + let TSFlags{42} = hasEVEX_Z; + let TSFlags{43} = hasEVEX_L2; + let TSFlags{44} = hasEVEX_B; + // If we run out of TSFlags bits, it's possible to encode this in 3 bits. + let TSFlags{51-45} = CD8_Scale; + let TSFlags{52} = hasEVEX_RC; + let TSFlags{53} = hasNoTrackPrefix; +} + +class PseudoI pattern> + : X86Inst<0, Pseudo, NoImm, oops, iops, ""> { + let Pattern = pattern; +} + +class I o, Format f, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii8 o, Format f, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii8Reg o, Format f, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii8PCRel o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii16 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii32 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii32S o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +class Ii64 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +class Ii16PCRel o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +class Ii32PCRel o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +// FPStack Instruction Templates: +// FPI - Floating Point Instruction template. +class FPI o, Format F, dag outs, dag ins, string asm> + : I {} + +// FpI_ - Floating Point Pseudo Instruction template. Not Predicated. +class FpI_ pattern> + : PseudoI { + let FPForm = fp; +} + +// Templates for instructions that use a 16- or 32-bit segmented address as +// their only operand: lcall (FAR CALL) and ljmp (FAR JMP) +// +// Iseg16 - 16-bit segment selector, 16-bit offset +// Iseg32 - 16-bit segment selector, 32-bit offset + +class Iseg16 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +class Iseg32 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +// SI - SSE 1 & 2 scalar instructions +class SI o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : I { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], + !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], + !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], + !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], + [UseSSE1]))))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} + +// SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512 +class SI_Int o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : I { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], + !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], + !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], + !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], + [UseSSE1]))))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} +// SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512 +class SIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8 { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], + !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], + [UseSSE2]))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} + +// PI - SSE 1 & 2 packed instructions +class PI o, Format F, dag outs, dag ins, string asm, list pattern, + Domain d> + : I { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], + !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], + [UseSSE1]))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} + +// MMXPI - SSE 1 & 2 packed instructions with MMX operands +class MMXPI o, Format F, dag outs, dag ins, string asm, list pattern, + Domain d> + : I { + let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasMMX, HasSSE2], + [HasMMX, HasSSE1]); +} + +// PIi8 - SSE 1 & 2 packed instructions with immediate +class PIi8 o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d> + : Ii8 { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], + !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], + [UseSSE1]))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} + +// SSE1 Instruction Templates: +// +// SSI - SSE1 instructions with XS prefix. +// PSI - SSE1 instructions with PS prefix. +// PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix. +// VSSI - SSE1 instructions with XS prefix in AVX form. +// VPSI - SSE1 instructions with PS prefix in AVX form, packed single. + +class SSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, Requires<[UseSSE1]>; +class SSIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[UseSSE1]>; +class PSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, + Requires<[UseSSE1]>; +class PSIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, PS, + Requires<[UseSSE1]>; +class VSSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, + Requires<[HasAVX]>; +class VPSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, + Requires<[HasAVX]>; + +// SSE2 Instruction Templates: +// +// SDI - SSE2 instructions with XD prefix. +// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. +// S2SI - SSE2 instructions with XS prefix. +// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. +// PDI - SSE2 instructions with PD prefix, packed double domain. +// PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix. +// VSDI - SSE2 scalar instructions with XD prefix in AVX form. +// VPDI - SSE2 vector instructions with PD prefix in AVX form, +// packed double domain. +// VS2I - SSE2 scalar instructions with PD prefix in AVX form. +// S2I - SSE2 scalar instructions with PD prefix. +// MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as +// MMX operands. +// MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as +// MMX operands. + +class SDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XD, Requires<[UseSSE2]>; +class SDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XD, Requires<[UseSSE2]>; +class S2SI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, Requires<[UseSSE2]>; +class S2SIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[UseSSE2]>; +class PDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[UseSSE2]>; +class PDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, PD, + Requires<[UseSSE2]>; +class VSDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XD, + Requires<[UseAVX]>; +class VS2SI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, + Requires<[HasAVX]>; +class VPDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, + PD, Requires<[HasAVX]>; +class VS2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[UseAVX]>; +class S2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, Requires<[UseSSE2]>; +class MMXSDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XD, Requires<[HasMMX, HasSSE2]>; +class MMXS2SIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[HasMMX, HasSSE2]>; + +// SSE3 Instruction Templates: +// +// S3I - SSE3 instructions with PD prefixes. +// S3SI - SSE3 instructions with XS prefix. +// S3DI - SSE3 instructions with XD prefix. + +class S3SI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, + Requires<[UseSSE3]>; +class S3DI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XD, + Requires<[UseSSE3]>; +class S3I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[UseSSE3]>; + + +// SSSE3 Instruction Templates: +// +// SS38I - SSSE3 instructions with T8 prefix. +// SS3AI - SSSE3 instructions with TA prefix. +// MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands. +// MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands. +// +// Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version +// uses the MMX registers. The 64-bit versions are grouped with the MMX +// classes. They need to be enabled even if AVX is enabled. + +class SS38I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[UseSSSE3]>; +class SS3AI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[UseSSSE3]>; +class MMXSS38I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PS, + Requires<[HasMMX, HasSSSE3]>; +class MMXSS3AI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPS, + Requires<[HasMMX, HasSSSE3]>; + +// SSE4.1 Instruction Templates: +// +// SS48I - SSE 4.1 instructions with T8 prefix. +// SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. +// +class SS48I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[UseSSE41]>; +class SS4AIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[UseSSE41]>; + +// SSE4.2 Instruction Templates: +// +// SS428I - SSE 4.2 instructions with T8 prefix. +class SS428I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[UseSSE42]>; + +// SS42FI - SSE 4.2 instructions with T8XD prefix. +// NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns. +class SS42FI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8XD, Requires<[HasSSE42]>; + +// SS42AI = SSE 4.2 instructions with TA prefix +class SS42AI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[UseSSE42]>; + +// AVX Instruction Templates: +// Instructions introduced in AVX (no SSE equivalent forms) +// +// AVX8I - AVX instructions with T8PD prefix. +// AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8. +class AVX8I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[HasAVX]>; +class AVXAIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[HasAVX]>; + +// AVX2 Instruction Templates: +// Instructions introduced in AVX2 (no SSE equivalent forms) +// +// AVX28I - AVX2 instructions with T8PD prefix. +// AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8. +class AVX28I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[HasAVX2]>; +class AVX2AIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[HasAVX2]>; + + +// AVX-512 Instruction Templates: +// Instructions introduced in AVX-512 (no SSE equivalent forms) +// +// AVX5128I - AVX-512 instructions with T8PD prefix. +// AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8. +// AVX512PDI - AVX-512 instructions with PD, double packed. +// AVX512PSI - AVX-512 instructions with PS, single packed. +// AVX512XS8I - AVX-512 instructions with T8 and XS prefixes. +// AVX512XSI - AVX-512 instructions with XS prefix, generic domain. +// AVX512BI - AVX-512 instructions with PD, int packed domain. +// AVX512SI - AVX-512 scalar instructions with PD prefix. + +class AVX5128I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[HasAVX512]>; +class AVX5128IBase : T8PD { + Domain ExeDomain = SSEPackedInt; +} +class AVX512XS8I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8XS, + Requires<[HasAVX512]>; +class AVX512XSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, + Requires<[HasAVX512]>; +class AVX512XDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XD, + Requires<[HasAVX512]>; +class AVX512BI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[HasAVX512]>; +class AVX512BIBase : PD { + Domain ExeDomain = SSEPackedInt; +} +class AVX512BIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, PD, + Requires<[HasAVX512]>; +class AVX512BIi8Base : PD { + Domain ExeDomain = SSEPackedInt; + ImmType ImmT = Imm8; +} +class AVX512XSIi8Base : XS { + Domain ExeDomain = SSEPackedInt; + ImmType ImmT = Imm8; +} +class AVX512XDIi8Base : XD { + Domain ExeDomain = SSEPackedInt; + ImmType ImmT = Imm8; +} +class AVX512PSIi8Base : PS { + Domain ExeDomain = SSEPackedSingle; + ImmType ImmT = Imm8; +} +class AVX512PDIi8Base : PD { + Domain ExeDomain = SSEPackedDouble; + ImmType ImmT = Imm8; +} +class AVX512AIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[HasAVX512]>; +class AVX512AIi8Base : TAPD { + ImmType ImmT = Imm8; +} +class AVX512Ii8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, + Requires<[HasAVX512]>; +class AVX512PDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[HasAVX512]>; +class AVX512PSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, + Requires<[HasAVX512]>; +class AVX512PIi8 o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d> + : Ii8, Requires<[HasAVX512]>; +class AVX512PI o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d> + : I, Requires<[HasAVX512]>; +class AVX512FMA3S o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + EVEX_4V, Requires<[HasAVX512]>; +class AVX512FMA3Base : T8PD, EVEX_4V; + +class AVX512 o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, Requires<[HasAVX512]>; + +// AES Instruction Templates: +// +// AES8I +// These use the same encoding as the SSE4.2 T8 and TA encodings. +class AES8I o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + Requires<[NoAVX, HasAES]>; + +class AESAI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[NoAVX, HasAES]>; + +// PCLMUL Instruction Templates +class PCLMULIi8 o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8, TAPD; + +// FMA3 Instruction Templates +class FMA3 o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoVLX]>; +class FMA3S o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoAVX512]>; +class FMA3S_Int o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + VEX_4V, FMASC, Requires<[HasFMA, NoAVX512]>; + +// FMA4 Instruction Templates +class FMA4 o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8Reg, TAPD, + VEX_4V, FMASC, Requires<[HasFMA4, NoVLX]>; +class FMA4S o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8Reg, TAPD, + VEX_4V, FMASC, Requires<[HasFMA4, NoAVX512]>; +class FMA4S_Int o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8Reg, TAPD, + VEX_4V, FMASC, Requires<[HasFMA4]>; + +// XOP 2, 3 and 4 Operand Instruction Template +class IXOP o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, + XOP9, Requires<[HasXOP]>; + +// XOP 2 and 3 Operand Instruction Templates with imm byte +class IXOPi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, + XOP8, Requires<[HasXOP]>; +// XOP 4 Operand Instruction Templates with imm byte +class IXOPi8Reg o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8Reg, + XOP8, Requires<[HasXOP]>; + +// XOP 5 operand instruction (VEX encoding!) +class IXOP5 o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8Reg, TAPD, + VEX_4V, Requires<[HasXOP]>; + +// X86-64 Instruction templates... +// + +class RI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, REX_W; +class RIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, REX_W; +class RIi16 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii16, REX_W; +class RIi32 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii32, REX_W; +class RIi32S o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii32S, REX_W; +class RIi64 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii64, REX_W; + +class RS2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : S2I, REX_W; +class VRS2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : VS2I, VEX_W; + +// MMX Instruction templates +// + +// MMXI - MMX instructions with TB prefix. +// MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode. +// MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode. +// MMX2I - MMX / SSE2 instructions with PD prefix. +// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. +// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. +// MMXID - MMX instructions with XD prefix. +// MMXIS - MMX instructions with XS prefix. +class MMXI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, Requires<[HasMMX]>; +class MMXI32 o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, Requires<[HasMMX,Not64BitMode]>; +class MMXI64 o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, Requires<[HasMMX,In64BitMode]>; +class MMXRI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, REX_W, Requires<[HasMMX]>; +class MMX2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, Requires<[HasMMX]>; +class MMXIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, PS, Requires<[HasMMX]>; +class MMXID o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XD, Requires<[HasMMX]>; +class MMXIS o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[HasMMX]>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrFragmentsSIMD.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrFragmentsSIMD.td new file mode 100644 index 0000000..7392759 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrFragmentsSIMD.td @@ -0,0 +1,1075 @@ +//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides pattern fragments useful for SIMD instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// MMX specific DAG Nodes. +//===----------------------------------------------------------------------===// + +// Low word of MMX to GPR. +def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1, + [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>; +// GPR to low word of MMX. +def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1, + [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>; + +//===----------------------------------------------------------------------===// +// MMX Pattern Fragments +//===----------------------------------------------------------------------===// + +def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>; + +//===----------------------------------------------------------------------===// +// SSE specific DAG Nodes. +//===----------------------------------------------------------------------===// + +def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, + SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, + SDTCisVT<3, i8>]>; + +def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; +def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; +def X86fmins : SDNode<"X86ISD::FMINS", SDTFPBinOp>; +def X86fmaxs : SDNode<"X86ISD::FMAXS", SDTFPBinOp>; + +// Commutative and Associative FMIN and FMAX. +def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; + +def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp>; +def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; +def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; +def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; +def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; +def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>; +def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>; +def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; +def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; +def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>; +def X86pshufb : SDNode<"X86ISD::PSHUFB", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>]>>; +def X86psadbw : SDNode<"X86ISD::PSADBW", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, + SDTCVecEltisVT<1, i8>, + SDTCisSameSizeAs<0,1>, + SDTCisSameAs<1,2>]>, [SDNPCommutative]>; +def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW", + SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>, + SDTCVecEltisVT<1, i8>, + SDTCisSameSizeAs<0,1>, + SDTCisSameAs<1,2>, SDTCisInt<3>]>>; +def X86andnp : SDNode<"X86ISD::ANDNP", + SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>]>>; +def X86multishift : SDNode<"X86ISD::MULTISHIFT", + SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisSameAs<1,2>]>>; +def X86pextrb : SDNode<"X86ISD::PEXTRB", + SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>, + SDTCisPtrTy<2>]>>; +def X86pextrw : SDNode<"X86ISD::PEXTRW", + SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>, + SDTCisPtrTy<2>]>>; +def X86pinsrb : SDNode<"X86ISD::PINSRB", + SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, + SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; +def X86pinsrw : SDNode<"X86ISD::PINSRW", + SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, + SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; +def X86insertps : SDNode<"X86ISD::INSERTPS", + SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, + SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>; +def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", + SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; + +def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; + +def X86vzext : SDNode<"X86ISD::VZEXT", + SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisInt<0>, SDTCisInt<1>, + SDTCisOpSmallerThanOp<1, 0>]>>; + +def X86vsext : SDNode<"X86ISD::VSEXT", + SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisInt<0>, SDTCisInt<1>, + SDTCisOpSmallerThanOp<1, 0>]>>; + +def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisInt<0>, SDTCisInt<1>, + SDTCisOpSmallerThanOp<0, 1>]>; + +def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>; +def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>; +def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>; + +def X86vfpext : SDNode<"X86ISD::VFPEXT", + SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>, + SDTCVecEltisVT<1, f32>, + SDTCisSameSizeAs<0, 1>]>>; +def X86vfpround: SDNode<"X86ISD::VFPROUND", + SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, + SDTCVecEltisVT<1, f64>, + SDTCisSameSizeAs<0, 1>]>>; + +def X86froundRnd: SDNode<"X86ISD::VFPROUNDS_RND", + SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, + SDTCisSameAs<0, 1>, + SDTCVecEltisVT<2, f64>, + SDTCisSameSizeAs<0, 2>, + SDTCisVT<3, i32>]>>; + +def X86fpextRnd : SDNode<"X86ISD::VFPEXTS_RND", + SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f64>, + SDTCisSameAs<0, 1>, + SDTCVecEltisVT<2, f32>, + SDTCisSameSizeAs<0, 2>, + SDTCisVT<3, i32>]>>; + +def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisVT<2, i8>, SDTCisInt<0>]>; + +def X86vshldq : SDNode<"X86ISD::VSHLDQ", X86vshiftimm>; +def X86vshrdq : SDNode<"X86ISD::VSRLDQ", X86vshiftimm>; +def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>; +def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>; +def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>; + +def X86CmpMaskCC : + SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>, + SDTCisVec<1>, SDTCisSameAs<2, 1>, + SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>; +def X86CmpMaskCCRound : + SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>, + SDTCisVec<1>, SDTCisFP<1>, SDTCisSameAs<2, 1>, + SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>, + SDTCisVT<4, i32>]>; +def X86CmpMaskCCScalar : + SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>, + SDTCisVT<3, i8>]>; + +def X86CmpMaskCCScalarRound : + SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>, + SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; + +def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>; +// Hack to make CMPM commutable in tablegen patterns for load folding. +def X86cmpm_c : SDNode<"X86ISD::CMPM", X86CmpMaskCC, [SDNPCommutative]>; +def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>; +def X86cmpms : SDNode<"X86ISD::FSETCCM", X86CmpMaskCCScalar>; +def X86cmpmsRnd : SDNode<"X86ISD::FSETCCM_RND", X86CmpMaskCCScalarRound>; + +def X86phminpos: SDNode<"X86ISD::PHMINPOS", + SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>; + +def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisVec<2>, SDTCisInt<0>, + SDTCisInt<1>]>; + +def X86vshl : SDNode<"X86ISD::VSHL", X86vshiftuniform>; +def X86vsrl : SDNode<"X86ISD::VSRL", X86vshiftuniform>; +def X86vsra : SDNode<"X86ISD::VSRA", X86vshiftuniform>; + +def X86vshiftvariable : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, SDTCisInt<0>]>; + +def X86vsrav : SDNode<"X86ISD::VSRAV", X86vshiftvariable>; + +def X86vshli : SDNode<"X86ISD::VSHLI", X86vshiftimm>; +def X86vsrli : SDNode<"X86ISD::VSRLI", X86vshiftimm>; +def X86vsrai : SDNode<"X86ISD::VSRAI", X86vshiftimm>; + +def X86kshiftl : SDNode<"X86ISD::KSHIFTL", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, + SDTCisSameAs<0, 1>, + SDTCisVT<2, i8>]>>; +def X86kshiftr : SDNode<"X86ISD::KSHIFTR", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, + SDTCisSameAs<0, 1>, + SDTCisVT<2, i8>]>>; + +def X86kadd : SDNode<"X86ISD::KADD", SDTIntBinOp, [SDNPCommutative]>; + +def X86vrotli : SDNode<"X86ISD::VROTLI", X86vshiftimm>; +def X86vrotri : SDNode<"X86ISD::VROTRI", X86vshiftimm>; + +def X86vpshl : SDNode<"X86ISD::VPSHL", X86vshiftvariable>; +def X86vpsha : SDNode<"X86ISD::VPSHA", X86vshiftvariable>; + +def X86vpcom : SDNode<"X86ISD::VPCOM", + SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisVT<3, i8>, SDTCisInt<0>]>>; +def X86vpcomu : SDNode<"X86ISD::VPCOMU", + SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisVT<3, i8>, SDTCisInt<0>]>>; +def X86vpermil2 : SDNode<"X86ISD::VPERMIL2", + SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisFP<0>, SDTCisInt<3>, + SDTCisSameNumEltsAs<0, 3>, + SDTCisSameSizeAs<0,3>, + SDTCisVT<4, i8>]>>; +def X86vpperm : SDNode<"X86ISD::VPPERM", + SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, SDTCisSameAs<0, 3>]>>; + +def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, + SDTCisVec<1>, + SDTCisSameAs<2, 1>]>; + +def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp, [SDNPCommutative]>; +def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>; +def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp, [SDNPCommutative]>; +def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>; +def X86mulhrs : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>; +def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>; +def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; +def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>; +def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>; +def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>; + +def X86movmsk : SDNode<"X86ISD::MOVMSK", + SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>; + +def X86selects : SDNode<"X86ISD::SELECTS", + SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<2, 3>]>>; + +def X86pmuludq : SDNode<"X86ISD::PMULUDQ", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, + SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>]>, + [SDNPCommutative]>; +def X86pmuldq : SDNode<"X86ISD::PMULDQ", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, + SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>]>, + [SDNPCommutative]>; + +def X86extrqi : SDNode<"X86ISD::EXTRQI", + SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, + SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>; +def X86insertqi : SDNode<"X86ISD::INSERTQI", + SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>, SDTCisVT<3, i8>, + SDTCisVT<4, i8>]>>; + +// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get +// translated into one of the target nodes below during lowering. +// Note: this is a work in progress... +def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; +def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>]>; +def SDTShuff2OpFP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, + SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>; + +def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisFP<0>, SDTCisInt<2>, + SDTCisSameNumEltsAs<0,2>, + SDTCisSameSizeAs<0,2>]>; +def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>, + SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>; +def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>; +def SDTFPBinOpImm: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, + SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisVT<3, i32>]>; +def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisVec<0>, + SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisVT<3, i32>, + SDTCisVT<4, i32>]>; +def SDTFPTernaryOpImmRound: SDTypeProfile<1, 5, [SDTCisFP<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisInt<3>, + SDTCisSameSizeAs<0, 3>, + SDTCisSameNumEltsAs<0, 3>, + SDTCisVT<4, i32>, + SDTCisVT<5, i32>]>; +def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisVec<0>, + SDTCisSameAs<0,1>, + SDTCisVT<2, i32>]>; +def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, + SDTCisSameAs<0,1>, + SDTCisVT<2, i32>, + SDTCisVT<3, i32>]>; + +def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>; +def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>, + SDTCisInt<0>, SDTCisInt<1>]>; + +def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>; + +def SDTTernlog : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisVec<0>, + SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, + SDTCisSameAs<0,3>, SDTCisVT<4, i8>]>; + +def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc. + SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>; + +def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc. + SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>; + +def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, + SDTCisFP<0>, SDTCisVT<4, i32>]>; + +def X86PAlignr : SDNode<"X86ISD::PALIGNR", + SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>, + SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisVT<3, i8>]>>; +def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>; + +def X86VShld : SDNode<"X86ISD::VSHLD", SDTShuff3OpI>; +def X86VShrd : SDNode<"X86ISD::VSHRD", SDTShuff3OpI>; +def X86VShldv : SDNode<"X86ISD::VSHLDV", + SDTypeProfile<1, 3, [SDTCisVec<0>, + SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisSameAs<0,3>]>>; +def X86VShrdv : SDNode<"X86ISD::VSHRDV", + SDTypeProfile<1, 3, [SDTCisVec<0>, + SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisSameAs<0,3>]>>; + +def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>; + +def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>; +def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>; +def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>; + +def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>; +def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>; + +def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>; +def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>; +def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>; + +def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2OpFP>; +def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2OpFP>; + +def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2OpFP>; +def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2OpFP>; + +def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>, + SDTCisVec<1>, SDTCisInt<1>, + SDTCisSameSizeAs<0,1>, + SDTCisSameAs<1,2>, + SDTCisOpSmallerThanOp<0, 1>]>; +def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>; +def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>; + +def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>; +def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>; + +def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, + SDTCVecEltisVT<1, i8>, + SDTCisSameSizeAs<0,1>, + SDTCisSameAs<1,2>]>>; +def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i32>, + SDTCVecEltisVT<1, i16>, + SDTCisSameSizeAs<0,1>, + SDTCisSameAs<1,2>]>, + [SDNPCommutative]>; + +def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>; +def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>; +def X86VPermv : SDNode<"X86ISD::VPERMV", + SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>, + SDTCisSameNumEltsAs<0,1>, + SDTCisSameSizeAs<0,1>, + SDTCisSameAs<0,2>]>>; +def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>; +def X86VPermt2 : SDNode<"X86ISD::VPERMV3", + SDTypeProfile<1, 3, [SDTCisVec<0>, + SDTCisSameAs<0,1>, SDTCisInt<2>, + SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>, + SDTCisSameSizeAs<0,2>, + SDTCisSameAs<0,3>]>, []>; + +def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>; + +def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>; + +def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImmRound>; +def X86VFixupimmScalar : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImmRound>; +def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImm>; +def X86VRangeRnd : SDNode<"X86ISD::VRANGE_RND", SDTFPBinOpImmRound>; +def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImm>; +def X86VReduceRnd : SDNode<"X86ISD::VREDUCE_RND", SDTFPUnaryOpImmRound>; +def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImm>; +def X86VRndScaleRnd: SDNode<"X86ISD::VRNDSCALE_RND", SDTFPUnaryOpImmRound>; +def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImm>; +def X86VGetMantRnd : SDNode<"X86ISD::VGETMANT_RND", SDTFPUnaryOpImmRound>; +def X86Vfpclass : SDNode<"X86ISD::VFPCLASS", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, + SDTCisFP<1>, + SDTCisSameNumEltsAs<0,1>, + SDTCisVT<2, i32>]>, []>; +def X86Vfpclasss : SDNode<"X86ISD::VFPCLASSS", + SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>, + SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>; + +def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST", + SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisSubVecOfVec<1, 0>]>, []>; + +def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>; +def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>; + +def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>; + +def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>; + +def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>; +def X86faddRnds : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>; +def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>; +def X86fsubRnds : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>; +def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>; +def X86fmulRnds : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>; +def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>; +def X86fdivRnds : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>; +def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>; +def X86fmaxRnds : SDNode<"X86ISD::FMAXS_RND", SDTFPBinOpRound>; +def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>; +def X86fminRnds : SDNode<"X86ISD::FMINS_RND", SDTFPBinOpRound>; +def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>; +def X86scalefs : SDNode<"X86ISD::SCALEFS", SDTFPBinOpRound>; +def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>; +def X86fsqrtRnds : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>; +def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>; +def X86fgetexpRnds : SDNode<"X86ISD::FGETEXPS_RND", SDTFPBinOpRound>; + +def X86Fmadd : SDNode<"ISD::FMA", SDTFPTernaryOp, [SDNPCommutative]>; +def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFPTernaryOp, [SDNPCommutative]>; +def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>; +def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFPTernaryOp, [SDNPCommutative]>; +def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFPTernaryOp, [SDNPCommutative]>; +def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFPTernaryOp, [SDNPCommutative]>; + +def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound, [SDNPCommutative]>; +def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound, [SDNPCommutative]>; +def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound, [SDNPCommutative]>; +def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound, [SDNPCommutative]>; +def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound, [SDNPCommutative]>; +def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound, [SDNPCommutative]>; + +def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; +def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>; +def x86vpmadd52h : SDNode<"X86ISD::VPMADD52H", SDTIFma, [SDNPCommutative]>; + +def X86rsqrt14 : SDNode<"X86ISD::RSQRT14", SDTFPUnaryOp>; +def X86rcp14 : SDNode<"X86ISD::RCP14", SDTFPUnaryOp>; + +// VNNI +def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, + SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; +def X86Vpdpbusd : SDNode<"X86ISD::VPDPBUSD", SDTVnni>; +def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>; +def X86Vpdpwssd : SDNode<"X86ISD::VPDPWSSD", SDTVnni>; +def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>; + +def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", SDTFPUnaryOpRound>; +def X86rcp28 : SDNode<"X86ISD::RCP28", SDTFPUnaryOpRound>; +def X86exp2 : SDNode<"X86ISD::EXP2", SDTFPUnaryOpRound>; + +def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>; +def X86rcp14s : SDNode<"X86ISD::RCP14S", SDTFPBinOp>; +def X86rsqrt28s : SDNode<"X86ISD::RSQRT28S", SDTFPBinOpRound>; +def X86rcp28s : SDNode<"X86ISD::RCP28S", SDTFPBinOpRound>; +def X86Ranges : SDNode<"X86ISD::VRANGES", SDTFPBinOpImm>; +def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImm>; +def X86Reduces : SDNode<"X86ISD::VREDUCES", SDTFPBinOpImm>; +def X86GetMants : SDNode<"X86ISD::VGETMANTS", SDTFPBinOpImm>; +def X86RangesRnd : SDNode<"X86ISD::VRANGES_RND", SDTFPBinOpImmRound>; +def X86RndScalesRnd : SDNode<"X86ISD::VRNDSCALES_RND", SDTFPBinOpImmRound>; +def X86ReducesRnd : SDNode<"X86ISD::VREDUCES_RND", SDTFPBinOpImmRound>; +def X86GetMantsRnd : SDNode<"X86ISD::VGETMANTS_RND", SDTFPBinOpImmRound>; + +def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1, + [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>; +def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1, + [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>; + +// vpshufbitqmb +def X86Vpshufbitqmb : SDNode<"X86ISD::VPSHUFBITQMB", + SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisSameAs<1,2>, + SDTCVecEltisVT<0,i1>, + SDTCisSameNumEltsAs<0,1>]>>; + +def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>, + SDTCisSameAs<0,1>, SDTCisInt<2>, + SDTCisVT<3, i32>]>; + +def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisInt<0>, SDTCisFP<1>]>; +def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisInt<0>, SDTCisFP<1>, + SDTCisVT<2, i32>]>; +def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>, + SDTCisVec<1>, SDTCisVT<2, i32>]>; + +def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisFP<0>, SDTCisInt<1>]>; +def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisFP<0>, SDTCisInt<1>, + SDTCisVT<2, i32>]>; + +// Scalar +def X86SintToFpRnd : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND", SDTintToFPRound>; +def X86UintToFpRnd : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND", SDTintToFPRound>; + +def X86cvtts2IntRnd : SDNode<"X86ISD::CVTTS2SI_RND", SDTSFloatToIntRnd>; +def X86cvtts2UIntRnd : SDNode<"X86ISD::CVTTS2UI_RND", SDTSFloatToIntRnd>; + +def X86cvts2si : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>; +def X86cvts2usi : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>; + +// Vector with rounding mode + +// cvtt fp-to-int staff +def X86cvttp2siRnd : SDNode<"X86ISD::CVTTP2SI_RND", SDTFloatToIntRnd>; +def X86cvttp2uiRnd : SDNode<"X86ISD::CVTTP2UI_RND", SDTFloatToIntRnd>; + +def X86VSintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTVintToFPRound>; +def X86VUintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTVintToFPRound>; + +// cvt fp-to-int staff +def X86cvtp2IntRnd : SDNode<"X86ISD::CVTP2SI_RND", SDTFloatToIntRnd>; +def X86cvtp2UIntRnd : SDNode<"X86ISD::CVTP2UI_RND", SDTFloatToIntRnd>; + +// Vector without rounding mode + +// cvtt fp-to-int staff +def X86cvttp2si : SDNode<"X86ISD::CVTTP2SI", SDTFloatToInt>; +def X86cvttp2ui : SDNode<"X86ISD::CVTTP2UI", SDTFloatToInt>; + +def X86VSintToFP : SDNode<"X86ISD::CVTSI2P", SDTVintToFP>; +def X86VUintToFP : SDNode<"X86ISD::CVTUI2P", SDTVintToFP>; + +// cvt int-to-fp staff +def X86cvtp2Int : SDNode<"X86ISD::CVTP2SI", SDTFloatToInt>; +def X86cvtp2UInt : SDNode<"X86ISD::CVTP2UI", SDTFloatToInt>; + + +def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS", + SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, + SDTCVecEltisVT<1, i16>]> >; + +def X86cvtph2psRnd : SDNode<"X86ISD::CVTPH2PS_RND", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, + SDTCVecEltisVT<1, i16>, + SDTCisVT<2, i32>]> >; + +def X86cvtps2ph : SDNode<"X86ISD::CVTPS2PH", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, + SDTCVecEltisVT<1, f32>, + SDTCisVT<2, i32>]> >; +def X86vfpextRnd : SDNode<"X86ISD::VFPEXT_RND", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>, + SDTCVecEltisVT<1, f32>, + SDTCisOpSmallerThanOp<1, 0>, + SDTCisVT<2, i32>]>>; +def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND", + SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, + SDTCVecEltisVT<1, f64>, + SDTCisOpSmallerThanOp<0, 1>, + SDTCisVT<2, i32>]>>; + +// galois field arithmetic +def X86GF2P8affineinvqb : SDNode<"X86ISD::GF2P8AFFINEINVQB", SDTBlend>; +def X86GF2P8affineqb : SDNode<"X86ISD::GF2P8AFFINEQB", SDTBlend>; +def X86GF2P8mulb : SDNode<"X86ISD::GF2P8MULB", SDTIntBinOp>; + +//===----------------------------------------------------------------------===// +// SSE Complex Patterns +//===----------------------------------------------------------------------===// + +// These are 'extloads' from a scalar to the low element of a vector, zeroing +// the top elements. These are used for the SSE 'ss' and 'sd' instruction +// forms. +def sse_load_f32 : ComplexPattern; +def sse_load_f64 : ComplexPattern; + +def ssmem : Operand { + let PrintMethod = "printf32mem"; + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); + let ParserMatchClass = X86Mem32AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} +def sdmem : Operand { + let PrintMethod = "printf64mem"; + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); + let ParserMatchClass = X86Mem64AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +//===----------------------------------------------------------------------===// +// SSE pattern fragments +//===----------------------------------------------------------------------===// + +// Vector load wrappers to prevent folding of non-temporal aligned loads on +// supporting targets. +def vecload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return !useNonTemporalLoad(cast(N)); +}]>; + +// 128-bit load pattern fragments +// NOTE: all 128-bit integer vector loads are promoted to v2i64 +def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (vecload node:$ptr))>; +def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (vecload node:$ptr))>; +def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (vecload node:$ptr))>; + +// 256-bit load pattern fragments +// NOTE: all 256-bit integer vector loads are promoted to v4i64 +def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (vecload node:$ptr))>; +def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (vecload node:$ptr))>; +def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (vecload node:$ptr))>; + +// 512-bit load pattern fragments +def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (vecload node:$ptr))>; +def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (vecload node:$ptr))>; +def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (vecload node:$ptr))>; + +// 128-/256-/512-bit extload pattern fragments +def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>; +def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>; +def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>; + +// Like 'store', but always requires vector size alignment. +def alignedstore : PatFrag<(ops node:$val, node:$ptr), + (store node:$val, node:$ptr), [{ + auto *St = cast(N); + return St->getAlignment() >= St->getMemoryVT().getStoreSize(); +}]>; + +// Like 'load', but always requires 128-bit vector alignment. +def alignedvecload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + auto *Ld = cast(N); + return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize() && + !useNonTemporalLoad(cast(N)); +}]>; + +// 128-bit aligned load pattern fragments +// NOTE: all 128-bit integer vector loads are promoted to v2i64 +def alignedloadv4f32 : PatFrag<(ops node:$ptr), + (v4f32 (alignedvecload node:$ptr))>; +def alignedloadv2f64 : PatFrag<(ops node:$ptr), + (v2f64 (alignedvecload node:$ptr))>; +def alignedloadv2i64 : PatFrag<(ops node:$ptr), + (v2i64 (alignedvecload node:$ptr))>; + +// 256-bit aligned load pattern fragments +// NOTE: all 256-bit integer vector loads are promoted to v4i64 +def alignedloadv8f32 : PatFrag<(ops node:$ptr), + (v8f32 (alignedvecload node:$ptr))>; +def alignedloadv4f64 : PatFrag<(ops node:$ptr), + (v4f64 (alignedvecload node:$ptr))>; +def alignedloadv4i64 : PatFrag<(ops node:$ptr), + (v4i64 (alignedvecload node:$ptr))>; + +// 512-bit aligned load pattern fragments +def alignedloadv16f32 : PatFrag<(ops node:$ptr), + (v16f32 (alignedvecload node:$ptr))>; +def alignedloadv8f64 : PatFrag<(ops node:$ptr), + (v8f64 (alignedvecload node:$ptr))>; +def alignedloadv8i64 : PatFrag<(ops node:$ptr), + (v8i64 (alignedvecload node:$ptr))>; + +// Like 'vecload', but uses special alignment checks suitable for use in +// memory operands in most SSE instructions, which are required to +// be naturally aligned on some targets but not on others. If the subtarget +// allows unaligned accesses, match any load, though this may require +// setting a feature bit in the processor (on startup, for example). +// Opteron 10h and later implement such a feature. +def memop : PatFrag<(ops node:$ptr), (vecload node:$ptr), [{ + auto *Ld = cast(N); + return Subtarget->hasSSEUnalignedMem() || + Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); +}]>; + +// 128-bit memop pattern fragments +// NOTE: all 128-bit integer vector loads are promoted to v2i64 +def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; +def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; +def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; + +def X86masked_gather : SDNode<"X86ISD::MGATHER", + SDTypeProfile<2, 3, [SDTCisVec<0>, + SDTCisVec<1>, SDTCisInt<1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<1, 3>, + SDTCisPtrTy<4>]>, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; + +def X86masked_scatter : SDNode<"X86ISD::MSCATTER", + SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisSameAs<0, 2>, + SDTCVecEltisVT<0, i1>, + SDTCisPtrTy<3>]>, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ + X86MaskedGatherSDNode *Mgt = cast(N); + return Mgt->getIndex().getValueType() == MVT::v4i32; +}]>; + +def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ + X86MaskedGatherSDNode *Mgt = cast(N); + return Mgt->getIndex().getValueType() == MVT::v8i32; +}]>; + +def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ + X86MaskedGatherSDNode *Mgt = cast(N); + return Mgt->getIndex().getValueType() == MVT::v2i64; +}]>; +def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ + X86MaskedGatherSDNode *Mgt = cast(N); + return Mgt->getIndex().getValueType() == MVT::v4i64; +}]>; +def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ + X86MaskedGatherSDNode *Mgt = cast(N); + return Mgt->getIndex().getValueType() == MVT::v8i64; +}]>; +def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ + X86MaskedGatherSDNode *Mgt = cast(N); + return Mgt->getIndex().getValueType() == MVT::v16i32; +}]>; + +def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ + X86MaskedScatterSDNode *Sc = cast(N); + return Sc->getIndex().getValueType() == MVT::v2i64; +}]>; + +def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ + X86MaskedScatterSDNode *Sc = cast(N); + return Sc->getIndex().getValueType() == MVT::v4i32; +}]>; + +def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ + X86MaskedScatterSDNode *Sc = cast(N); + return Sc->getIndex().getValueType() == MVT::v4i64; +}]>; + +def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ + X86MaskedScatterSDNode *Sc = cast(N); + return Sc->getIndex().getValueType() == MVT::v8i32; +}]>; + +def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ + X86MaskedScatterSDNode *Sc = cast(N); + return Sc->getIndex().getValueType() == MVT::v8i64; +}]>; +def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ + X86MaskedScatterSDNode *Sc = cast(N); + return Sc->getIndex().getValueType() == MVT::v16i32; +}]>; + +// 128-bit bitconvert pattern fragments +def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; +def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; +def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; +def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; +def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; +def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; + +// 256-bit bitconvert pattern fragments +def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>; +def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>; +def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>; +def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>; +def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>; +def bc_v4f64 : PatFrag<(ops node:$in), (v4f64 (bitconvert node:$in))>; + +// 512-bit bitconvert pattern fragments +def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>; +def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>; +def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>; +def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>; +def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>; + +def vzmovl_v2i64 : PatFrag<(ops node:$src), + (bitconvert (v2i64 (X86vzmovl + (v2i64 (scalar_to_vector (loadi64 node:$src))))))>; +def vzmovl_v4i32 : PatFrag<(ops node:$src), + (bitconvert (v4i32 (X86vzmovl + (v4i32 (scalar_to_vector (loadi32 node:$src))))))>; + +def vzload_v2i64 : PatFrag<(ops node:$src), + (bitconvert (v2i64 (X86vzload node:$src)))>; + + +def fp32imm0 : PatLeaf<(f32 fpimm), [{ + return N->isExactlyValue(+0.0); +}]>; + +def fp64imm0 : PatLeaf<(f64 fpimm), [{ + return N->isExactlyValue(+0.0); +}]>; + +def I8Imm : SDNodeXFormgetZExtValue(), SDLoc(N)); +}]>; + +def FROUND_NO_EXC : PatLeaf<(i32 8)>; +def FROUND_CURRENT : PatLeaf<(i32 4)>; + +// BYTE_imm - Transform bit immediates into byte immediates. +def BYTE_imm : SDNodeXForm> 3 + return getI32Imm(N->getZExtValue() >> 3, SDLoc(N)); +}]>; + +// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index +// to VEXTRACTF128/VEXTRACTI128 imm. +def EXTRACT_get_vextract128_imm : SDNodeXForm; + +// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to +// VINSERTF128/VINSERTI128 imm. +def INSERT_get_vinsert128_imm : SDNodeXForm; + +// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index +// to VEXTRACTF64x4 imm. +def EXTRACT_get_vextract256_imm : SDNodeXForm; + +// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to +// VINSERTF64x4 imm. +def INSERT_get_vinsert256_imm : SDNodeXForm; + +def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index), + (extract_subvector node:$bigvec, + node:$index), [{}], + EXTRACT_get_vextract128_imm>; + +def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec, + node:$index), + (insert_subvector node:$bigvec, node:$smallvec, + node:$index), [{}], + INSERT_get_vinsert128_imm>; + +def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index), + (extract_subvector node:$bigvec, + node:$index), [{}], + EXTRACT_get_vextract256_imm>; + +def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec, + node:$index), + (insert_subvector node:$bigvec, node:$smallvec, + node:$index), [{}], + INSERT_get_vinsert256_imm>; + +def X86mload : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_load node:$src1, node:$src2, node:$src3), [{ + return !cast(N)->isExpandingLoad() && + cast(N)->getExtensionType() == ISD::NON_EXTLOAD; +}]>; + +def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mload node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getAlignment() >= 16; +}]>; + +def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mload node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getAlignment() >= 32; +}]>; + +def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mload node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getAlignment() >= 64; +}]>; + +def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_load node:$src1, node:$src2, node:$src3), [{ + return !cast(N)->isExpandingLoad() && + cast(N)->getExtensionType() == ISD::NON_EXTLOAD; +}]>; + +def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_load node:$src1, node:$src2, node:$src3), [{ + return cast(N)->isExpandingLoad(); +}]>; + +// Masked store fragments. +// X86mstore can't be implemented in core DAG files because some targets +// do not support vector types (llvm-tblgen will fail). +def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_store node:$src1, node:$src2, node:$src3), [{ + return (!cast(N)->isTruncatingStore()) && + (!cast(N)->isCompressingStore()); +}]>; + +def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mstore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getAlignment() >= 16; +}]>; + +def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mstore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getAlignment() >= 32; +}]>; + +def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mstore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getAlignment() >= 64; +}]>; + +def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_store node:$src1, node:$src2, node:$src3), [{ + return (!cast(N)->isTruncatingStore()) && + (!cast(N)->isCompressingStore()); +}]>; + +def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_store node:$src1, node:$src2, node:$src3), [{ + return cast(N)->isCompressingStore(); +}]>; + +// masked truncstore fragments +// X86mtruncstore can't be implemented in core DAG files because some targets +// doesn't support vector type ( llvm-tblgen will fail) +def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (masked_store node:$src1, node:$src2, node:$src3), [{ + return cast(N)->isTruncatingStore(); +}]>; +def masked_truncstorevi8 : + PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i8; +}]>; +def masked_truncstorevi16 : + PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i16; +}]>; +def masked_truncstorevi32 : + PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i32; +}]>; + +def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES", SDTStore, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS", SDTStore, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES", SDTMaskedStore, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS", SDTMaskedStore, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr), + (X86TruncSStore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i8; +}]>; + +def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr), + (X86TruncUSStore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i8; +}]>; + +def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr), + (X86TruncSStore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i16; +}]>; + +def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr), + (X86TruncUSStore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i16; +}]>; + +def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr), + (X86TruncSStore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i32; +}]>; + +def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr), + (X86TruncUSStore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i32; +}]>; + +def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i8; +}]>; + +def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i8; +}]>; + +def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i16; +}]>; + +def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i16; +}]>; + +def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i32; +}]>; + +def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ + return cast(N)->getMemoryVT().getScalarType() == MVT::i32; +}]>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrInfo.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrInfo.td new file mode 100644 index 0000000..b43ea8f --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrInfo.td @@ -0,0 +1,3580 @@ +//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 instruction set, defining the instructions, and +// properties of the instructions which are needed for code generation, machine +// code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// X86 specific DAG Nodes. +// + +def SDTIntShiftDOp: SDTypeProfile<1, 3, + [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, + SDTCisInt<0>, SDTCisInt<3>]>; + +def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; + +def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; +//def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; + +def SDTX86Cmov : SDTypeProfile<1, 4, + [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, + SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; + +// Unary and binary operator instructions that set EFLAGS as a side-effect. +def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, + [SDTCisSameAs<0, 2>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; + +def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, + [SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; + +// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS +def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, + [SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, + SDTCisVT<1, i32>, + SDTCisVT<4, i32>]>; +// RES1, RES2, FLAGS = op LHS, RHS +def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, + [SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; +def SDTX86BrCond : SDTypeProfile<0, 3, + [SDTCisVT<0, OtherVT>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; + +def SDTX86SetCC : SDTypeProfile<1, 2, + [SDTCisVT<0, i8>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; +def SDTX86SetCC_C : SDTypeProfile<1, 2, + [SDTCisInt<0>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; + +def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; + +def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; + +def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, + SDTCisVT<2, i8>]>; +def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; +def SDTX86caspairSaveEbx8 : SDTypeProfile<1, 3, + [SDTCisVT<0, i32>, SDTCisPtrTy<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; +def SDTX86caspairSaveRbx16 : SDTypeProfile<1, 3, + [SDTCisVT<0, i64>, SDTCisPtrTy<1>, + SDTCisVT<2, i64>, SDTCisVT<3, i64>]>; + +def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, + SDTCisPtrTy<1>, + SDTCisInt<2>]>; + +def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, + SDTCisPtrTy<1>]>; + +def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; + +def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; +def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; + +def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, + SDTCisVT<1, iPTR>, + SDTCisVT<2, iPTR>]>; + +def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, + SDTCisPtrTy<1>, + SDTCisVT<2, i32>, + SDTCisVT<3, i8>, + SDTCisVT<4, i32>]>; + +def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; + +def SDTX86Void : SDTypeProfile<0, 0, []>; + +def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; + +def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86WIN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; + +def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; + +def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; + +def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, + [SDNPHasChain,SDNPSideEffect]>; +def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, + [SDNPHasChain]>; + + +def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; +def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; +def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; +def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; + +def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; +def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; + +def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; +def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, + [SDNPHasChain]>; +def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; +def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; + +def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; + +def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, + [SDNPHasChain, SDNPSideEffect]>; + +def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, + [SDNPHasChain, SDNPSideEffect]>; + +def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas8save_ebx : SDNode<"X86ISD::LCMPXCHG8_SAVE_EBX_DAG", + SDTX86caspairSaveEbx8, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, + SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; +def X86cas16save_rbx : SDNode<"X86ISD::LCMPXCHG16_SAVE_RBX_DAG", + SDTX86caspairSaveRbx16, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, + SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; + +def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; +def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, + [SDNPHasChain, SDNPOptInGlue]>; + +def X86vastart_save_xmm_regs : + SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", + SDT_X86VASTART_SAVE_XMM_REGS, + [SDNPHasChain, SDNPVariadic]>; +def X86vaarg64 : + SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, + SDNPMemOperand]>; +def X86callseq_start : + SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, + [SDNPHasChain, SDNPOutGlue]>; +def X86callseq_end : + SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, + SDNPVariadic]>; + +def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, + SDNPVariadic]>; +def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind, + [SDNPHasChain]>; + +def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; +def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad]>; + +def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; +def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; +def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; + +def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; +def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; + +def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", + SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, + SDTCisInt<1>]>>; + +def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, + [SDNPHasChain]>; + +def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", + SDTypeProfile<1, 1, [SDTCisInt<0>, + SDTCisPtrTy<1>]>, + [SDNPHasChain, SDNPSideEffect]>; +def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", + SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, + [SDNPHasChain, SDNPSideEffect]>; +def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH", + SDTypeProfile<0, 0, []>, + [SDNPHasChain, SDNPSideEffect]>; + +def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; + +def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; +def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, + [SDNPCommutative]>; +def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; +def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; + +def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; +def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; +def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, + [SDNPCommutative]>; + +def X86lock_add : SDNode<"X86ISD::LADD", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_sub : SDNode<"X86ISD::LSUB", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_or : SDNode<"X86ISD::LOR", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; + +def X86lock_inc : SDNode<"X86ISD::LINC", SDTLockUnaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_dec : SDNode<"X86ISD::LDEC", SDTLockUnaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; + +def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; + +def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; + +def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDT_X86WIN_ALLOCA, + [SDNPHasChain, SDNPOutGlue]>; + +def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, + [SDNPHasChain]>; + +def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86lwpins : SDNode<"X86ISD::LWPINS", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; + +def X86umwait : SDNode<"X86ISD::UMWAIT", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +def X86tpause : SDNode<"X86ISD::TPAUSE", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +//===----------------------------------------------------------------------===// +// X86 Operand Definitions. +// + +// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for +// the index operand of an address, to conform to x86 encoding restrictions. +def ptr_rc_nosp : PointerLikeRegClass<1>; + +// *mem - Operand definitions for the funky X86 addressing mode operands. +// +def X86MemAsmOperand : AsmOperandClass { + let Name = "Mem"; +} +let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in { + def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } + def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } + def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } + def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } + def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } + def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } + def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } + def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } + // Gather mem operands + def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; } + def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; } + def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; } + def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; } + def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; } + + def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; } + def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; } + def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; } + def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; } + def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; } + def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; } + def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; } + def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; } +} + +def X86AbsMemAsmOperand : AsmOperandClass { + let Name = "AbsMem"; + let SuperClasses = [X86MemAsmOperand]; +} + +class X86MemOperand : Operand { + let PrintMethod = printMethod; + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); + let ParserMatchClass = parserMatchClass; + let OperandType = "OPERAND_MEMORY"; +} + +// Gather mem operands +class X86VMemOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG); +} + +def anymem : X86MemOperand<"printanymem">; + +// FIXME: Right now we allow any size during parsing, but we might want to +// restrict to only unsized memory. +def opaquemem : X86MemOperand<"printopaquemem">; + +def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>; +def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>; +def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>; +def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>; +def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>; +def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>; +def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>; +def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>; +def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>; +def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>; +def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>; +def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>; +def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>; + +def v512mem : X86VMemOperand; + +// Gather mem operands +def vx64mem : X86VMemOperand; +def vx128mem : X86VMemOperand; +def vx256mem : X86VMemOperand; +def vy128mem : X86VMemOperand; +def vy256mem : X86VMemOperand; + +def vx64xmem : X86VMemOperand; +def vx128xmem : X86VMemOperand; +def vx256xmem : X86VMemOperand; +def vy128xmem : X86VMemOperand; +def vy256xmem : X86VMemOperand; +def vy512xmem : X86VMemOperand; +def vz256mem : X86VMemOperand; +def vz512mem : X86VMemOperand; + +// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead +// of a plain GPR, so that it doesn't potentially require a REX prefix. +def ptr_rc_norex : PointerLikeRegClass<2>; +def ptr_rc_norex_nosp : PointerLikeRegClass<3>; + +def i8mem_NOREX : Operand { + let PrintMethod = "printi8mem"; + let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, + SEGMENT_REG); + let ParserMatchClass = X86Mem8AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +// GPRs available for tailcall. +// It represents GR32_TC, GR64_TC or GR64_TCW64. +def ptr_rc_tailcall : PointerLikeRegClass<4>; + +// Special i32mem for addresses of load folding tail calls. These are not +// allowed to use callee-saved registers since they must be scheduled +// after callee-saved register are popped. +def i32mem_TC : Operand { + let PrintMethod = "printi32mem"; + let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, + i32imm, SEGMENT_REG); + let ParserMatchClass = X86Mem32AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +// Special i64mem for addresses of load folding tail calls. These are not +// allowed to use callee-saved registers since they must be scheduled +// after callee-saved register are popped. +def i64mem_TC : Operand { + let PrintMethod = "printi64mem"; + let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, + ptr_rc_tailcall, i32imm, SEGMENT_REG); + let ParserMatchClass = X86Mem64AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +let OperandType = "OPERAND_PCREL", + ParserMatchClass = X86AbsMemAsmOperand, + PrintMethod = "printPCRelImm" in { +def i32imm_pcrel : Operand; +def i16imm_pcrel : Operand; + +// Branch targets have OtherVT type and print as pc-relative values. +def brtarget : Operand; +def brtarget8 : Operand; + +} + +// Special parser to detect 16-bit mode to select 16-bit displacement. +def X86AbsMem16AsmOperand : AsmOperandClass { + let Name = "AbsMem16"; + let RenderMethod = "addAbsMemOperands"; + let SuperClasses = [X86AbsMemAsmOperand]; +} + +// Branch targets have OtherVT type and print as pc-relative values. +let OperandType = "OPERAND_PCREL", + PrintMethod = "printPCRelImm" in { +let ParserMatchClass = X86AbsMem16AsmOperand in + def brtarget16 : Operand; +let ParserMatchClass = X86AbsMemAsmOperand in + def brtarget32 : Operand; +} + +let RenderMethod = "addSrcIdxOperands" in { + def X86SrcIdx8Operand : AsmOperandClass { + let Name = "SrcIdx8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86SrcIdx16Operand : AsmOperandClass { + let Name = "SrcIdx16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86SrcIdx32Operand : AsmOperandClass { + let Name = "SrcIdx32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86SrcIdx64Operand : AsmOperandClass { + let Name = "SrcIdx64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addSrcIdxOperands" + +let RenderMethod = "addDstIdxOperands" in { + def X86DstIdx8Operand : AsmOperandClass { + let Name = "DstIdx8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86DstIdx16Operand : AsmOperandClass { + let Name = "DstIdx16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86DstIdx32Operand : AsmOperandClass { + let Name = "DstIdx32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86DstIdx64Operand : AsmOperandClass { + let Name = "DstIdx64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addDstIdxOperands" + +let RenderMethod = "addMemOffsOperands" in { + def X86MemOffs16_8AsmOperand : AsmOperandClass { + let Name = "MemOffs16_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs16_16AsmOperand : AsmOperandClass { + let Name = "MemOffs16_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs16_32AsmOperand : AsmOperandClass { + let Name = "MemOffs16_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs32_8AsmOperand : AsmOperandClass { + let Name = "MemOffs32_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs32_16AsmOperand : AsmOperandClass { + let Name = "MemOffs32_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs32_32AsmOperand : AsmOperandClass { + let Name = "MemOffs32_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs32_64AsmOperand : AsmOperandClass { + let Name = "MemOffs32_64"; + let SuperClasses = [X86Mem64AsmOperand]; + } + def X86MemOffs64_8AsmOperand : AsmOperandClass { + let Name = "MemOffs64_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs64_16AsmOperand : AsmOperandClass { + let Name = "MemOffs64_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs64_32AsmOperand : AsmOperandClass { + let Name = "MemOffs64_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs64_64AsmOperand : AsmOperandClass { + let Name = "MemOffs64_64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addMemOffsOperands" + +class X86SrcIdxOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc, SEGMENT_REG); +} + +class X86DstIdxOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc); +} + +def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; +def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; +def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; +def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; +def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; +def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; +def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; +def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; + +class X86MemOffsOperand + : X86MemOperand { + let MIOperandInfo = (ops immOperand, SEGMENT_REG); +} + +def offset16_8 : X86MemOffsOperand; +def offset16_16 : X86MemOffsOperand; +def offset16_32 : X86MemOffsOperand; +def offset32_8 : X86MemOffsOperand; +def offset32_16 : X86MemOffsOperand; +def offset32_32 : X86MemOffsOperand; +def offset32_64 : X86MemOffsOperand; +def offset64_8 : X86MemOffsOperand; +def offset64_16 : X86MemOffsOperand; +def offset64_32 : X86MemOffsOperand; +def offset64_64 : X86MemOffsOperand; + +def SSECC : Operand { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def AVXCC : Operand { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def AVX512ICC : Operand { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def XOPCC : Operand { + let PrintMethod = "printXOPCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +class ImmSExtAsmOperandClass : AsmOperandClass { + let SuperClasses = [ImmAsmOperand]; + let RenderMethod = "addImmOperands"; +} + +def X86GR32orGR64AsmOperand : AsmOperandClass { + let Name = "GR32orGR64"; +} + +def GR32orGR64 : RegisterOperand { + let ParserMatchClass = X86GR32orGR64AsmOperand; +} +def AVX512RCOperand : AsmOperandClass { + let Name = "AVX512RC"; +} +def AVX512RC : Operand { + let PrintMethod = "printRoundingControl"; + let OperandType = "OPERAND_IMMEDIATE"; + let ParserMatchClass = AVX512RCOperand; +} + +// Sign-extended immediate classes. We don't need to define the full lattice +// here because there is no instruction with an ambiguity between ImmSExti64i32 +// and ImmSExti32i8. +// +// The strange ranges come from the fact that the assembler always works with +// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" +// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). + +// [0, 0x7FFFFFFF] | +// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] +def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti64i32"; +} + +// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti16i8"; + let SuperClasses = [ImmSExti64i32AsmOperand]; +} + +// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti32i8"; +} + +// [0, 0x0000007F] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti64i8"; + let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, + ImmSExti64i32AsmOperand]; +} + +// Unsigned immediate used by SSE/AVX instructions +// [0, 0xFF] +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmUnsignedi8AsmOperand : AsmOperandClass { + let Name = "ImmUnsignedi8"; + let RenderMethod = "addImmOperands"; +} + +// A couple of more descriptive operand definitions. +// 16-bits but only 8 bits are significant. +def i16i8imm : Operand { + let ParserMatchClass = ImmSExti16i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} +// 32-bits but only 8 bits are significant. +def i32i8imm : Operand { + let ParserMatchClass = ImmSExti32i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 32 bits are significant. +def i64i32imm : Operand { + let ParserMatchClass = ImmSExti64i32AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 8 bits are significant. +def i64i8imm : Operand { + let ParserMatchClass = ImmSExti64i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// Unsigned 8-bit immediate used by SSE/AVX instructions. +def u8imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 32-bit immediate but only 8-bits are significant and they are unsigned. +// Used by some SSE/AVX instructions that use intrinsics. +def i32u8imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 32 bits are significant, and those bits are treated as being +// pc relative. +def i64i32imm_pcrel : Operand { + let PrintMethod = "printPCRelImm"; + let ParserMatchClass = X86AbsMemAsmOperand; + let OperandType = "OPERAND_PCREL"; +} + +def lea64_32mem : Operand { + let PrintMethod = "printanymem"; + let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); + let ParserMatchClass = X86MemAsmOperand; +} + +// Memory operands that use 64-bit pointers in both ILP32 and LP64. +def lea64mem : Operand { + let PrintMethod = "printanymem"; + let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); + let ParserMatchClass = X86MemAsmOperand; +} + + +//===----------------------------------------------------------------------===// +// X86 Complex Pattern Definitions. +// + +// Define X86-specific addressing mode. +def addr : ComplexPattern; +def lea32addr : ComplexPattern; +// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. +def lea64_32addr : ComplexPattern; + +def tls32addr : ComplexPattern; + +def tls32baseaddr : ComplexPattern; + +def lea64addr : ComplexPattern; + +def tls64addr : ComplexPattern; + +def tls64baseaddr : ComplexPattern; + +def vectoraddr : ComplexPattern; + +// A relocatable immediate is either an immediate operand or an operand that can +// be relocated by the linker to an immediate, such as a regular symbol in +// non-PIC code. +def relocImm : ComplexPattern; + +//===----------------------------------------------------------------------===// +// X86 Instruction Predicate Definitions. +def TruePredicate : Predicate<"true">; + +def HasCMov : Predicate<"Subtarget->hasCMov()">; +def NoCMov : Predicate<"!Subtarget->hasCMov()">; + +def HasMMX : Predicate<"Subtarget->hasMMX()">; +def Has3DNow : Predicate<"Subtarget->has3DNow()">; +def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; +def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; +def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; +def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; +def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; +def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; +def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; +def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; +def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; +def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; +def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; +def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; +def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; +def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; +def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; +def NoAVX : Predicate<"!Subtarget->hasAVX()">; +def HasAVX : Predicate<"Subtarget->hasAVX()">; +def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; +def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; +def HasAVX512 : Predicate<"Subtarget->hasAVX512()">; +def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; +def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; +def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; +def HasCDI : Predicate<"Subtarget->hasCDI()">; +def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">; +def HasPFI : Predicate<"Subtarget->hasPFI()">; +def HasERI : Predicate<"Subtarget->hasERI()">; +def HasDQI : Predicate<"Subtarget->hasDQI()">; +def NoDQI : Predicate<"!Subtarget->hasDQI()">; +def HasBWI : Predicate<"Subtarget->hasBWI()">; +def NoBWI : Predicate<"!Subtarget->hasBWI()">; +def HasVLX : Predicate<"Subtarget->hasVLX()">; +def NoVLX : Predicate<"!Subtarget->hasVLX()">; +def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">; +def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">; +def PKU : Predicate<"Subtarget->hasPKU()">; +def HasVNNI : Predicate<"Subtarget->hasVNNI()">; + +def HasBITALG : Predicate<"Subtarget->hasBITALG()">; +def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; +def HasAES : Predicate<"Subtarget->hasAES()">; +def HasVAES : Predicate<"Subtarget->hasVAES()">; +def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">; +def HasFXSR : Predicate<"Subtarget->hasFXSR()">; +def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">; +def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">; +def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">; +def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">; +def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; +def NoVLX_Or_NoVPCLMULQDQ : + Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()">; +def HasVPCLMULQDQ : Predicate<"Subtarget->hasVPCLMULQDQ()">; +def HasGFNI : Predicate<"Subtarget->hasGFNI()">; +def HasFMA : Predicate<"Subtarget->hasFMA()">; +def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; +def NoFMA4 : Predicate<"!Subtarget->hasFMA4()">; +def HasXOP : Predicate<"Subtarget->hasXOP()">; +def HasTBM : Predicate<"Subtarget->hasTBM()">; +def NoTBM : Predicate<"!Subtarget->hasTBM()">; +def HasLWP : Predicate<"Subtarget->hasLWP()">; +def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; +def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; +def HasF16C : Predicate<"Subtarget->hasF16C()">; +def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; +def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; +def HasBMI : Predicate<"Subtarget->hasBMI()">; +def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; +def NoBMI2 : Predicate<"!Subtarget->hasBMI2()">; +def HasVBMI : Predicate<"Subtarget->hasVBMI()">; +def HasVBMI2 : Predicate<"Subtarget->hasVBMI2()">; +def HasIFMA : Predicate<"Subtarget->hasIFMA()">; +def HasRTM : Predicate<"Subtarget->hasRTM()">; +def HasADX : Predicate<"Subtarget->hasADX()">; +def HasSHA : Predicate<"Subtarget->hasSHA()">; +def HasSGX : Predicate<"Subtarget->hasSGX()">; +def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; +def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; +def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">; +def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">; +def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; +def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">; +def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">; +def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">; +def HasCLZERO : Predicate<"Subtarget->hasCLZERO()">; +def HasCLDEMOTE : Predicate<"Subtarget->hasCLDEMOTE()">; +def HasMOVDIRI : Predicate<"Subtarget->hasMOVDIRI()">; +def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">; +def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">; +def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; +def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; +def HasMPX : Predicate<"Subtarget->hasMPX()">; +def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; +def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; +def HasCLWB : Predicate<"Subtarget->hasCLWB()">; +def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">; +def HasRDPID : Predicate<"Subtarget->hasRDPID()">; +def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">; +def HasINVPCID : Predicate<"Subtarget->hasINVPCID()">; +def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; +def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">; +def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, + AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; +def In64BitMode : Predicate<"Subtarget->is64Bit()">, + AssemblerPredicate<"Mode64Bit", "64-bit mode">; +def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; +def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; +def In16BitMode : Predicate<"Subtarget->is16Bit()">, + AssemblerPredicate<"Mode16Bit", "16-bit mode">; +def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, + AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; +def In32BitMode : Predicate<"Subtarget->is32Bit()">, + AssemblerPredicate<"Mode32Bit", "32-bit mode">; +def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; +def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; +def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||" + "Subtarget->getFrameLowering()->hasFP(*MF)"> { + let RecomputePerFunction = 1; +} +def IsPS4 : Predicate<"Subtarget->isTargetPS4()">; +def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">; +def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; +def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; +def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; +def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; +def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" + "TM.getCodeModel() == CodeModel::Kernel">; +def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; + +// We could compute these on a per-module basis but doing so requires accessing +// the Function object through the Subtarget and objections were raised +// to that (see post-commit review comments for r301750). +let RecomputePerFunction = 1 in { + def OptForSize : Predicate<"MF->getFunction().optForSize()">; + def OptForMinSize : Predicate<"MF->getFunction().optForMinSize()">; + def OptForSpeed : Predicate<"!MF->getFunction().optForSize()">; + def UseIncDec : Predicate<"!Subtarget->slowIncDec() || " + "MF->getFunction().optForSize()">; + def NoSSE41_Or_OptForSize : Predicate<"MF->getFunction().optForSize() || " + "!Subtarget->hasSSE41()">; +} + +def CallImmAddr : Predicate<"Subtarget->isLegalToCallImmediateAddr()">; +def FavorMemIndirectCall : Predicate<"!Subtarget->slowTwoMemOps()">; +def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; +def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">; +def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">; +def HasERMSB : Predicate<"Subtarget->hasERMSB()">; +def HasMFence : Predicate<"Subtarget->hasMFence()">; +def UseRetpoline : Predicate<"Subtarget->useRetpoline()">; +def NotUseRetpoline : Predicate<"!Subtarget->useRetpoline()">; + +//===----------------------------------------------------------------------===// +// X86 Instruction Format Definitions. +// + +include "X86InstrFormats.td" + +//===----------------------------------------------------------------------===// +// Pattern fragments. +// + +// X86 specific condition code. These correspond to CondCode in +// X86InstrInfo.h. They must be kept in synch. +def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE +def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC +def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C +def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA +def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z +def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE +def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL +def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE +def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG +def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ +def X86_COND_NO : PatLeaf<(i8 10)>; +def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO +def X86_COND_NS : PatLeaf<(i8 12)>; +def X86_COND_O : PatLeaf<(i8 13)>; +def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE +def X86_COND_S : PatLeaf<(i8 15)>; + +def i16immSExt8 : ImmLeaf(Imm); }]>; +def i32immSExt8 : ImmLeaf(Imm); }]>; +def i64immSExt8 : ImmLeaf(Imm); }]>; +def i64immSExt32 : ImmLeaf(Imm); }]>; + +// FIXME: Ideally we would just replace the above i*immSExt* matchers with +// relocImm-based matchers, but then FastISel would be unable to use them. +def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{ + return isSExtRelocImm<8>(N); +}]>; +def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{ + return isSExtRelocImm<32>(N); +}]>; + +// If we have multiple users of an immediate, it's much smaller to reuse +// the register, rather than encode the immediate in every instruction. +// This has the risk of increasing register pressure from stretched live +// ranges, however, the immediates should be trivial to rematerialize by +// the RA in the event of high register pressure. +// TODO : This is currently enabled for stores and binary ops. There are more +// cases for which this can be enabled, though this catches the bulk of the +// issues. +// TODO2 : This should really also be enabled under O2, but there's currently +// an issue with RA where we don't pull the constants into their users +// when we rematerialize them. I'll follow-up on enabling O2 after we fix that +// issue. +// TODO3 : This is currently limited to single basic blocks (DAG creation +// pulls block immediates to the top and merges them if necessary). +// Eventually, it would be nice to allow ConstantHoisting to merge constants +// globally for potentially added savings. +// +def imm8_su : PatLeaf<(i8 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def imm16_su : PatLeaf<(i16 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def imm32_su : PatLeaf<(i32 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64immSExt32_su : PatLeaf<(i64immSExt32), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i32immSExt8_su : PatLeaf<(i32immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64immSExt8_su : PatLeaf<(i64immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit +// unsigned field. +def i64immZExt32 : ImmLeaf(Imm); }]>; + +def i64immZExt32SExt8 : ImmLeaf(Imm) && isInt<8>(static_cast(Imm)); +}]>; + +// Helper fragments for loads. + +// It's safe to fold a zextload/extload from i1 as a regular i8 load. The +// upper bits are guaranteed to be zero and we were going to emit a MOV8rm +// which might get folded during peephole anyway. +def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD || + ExtType == ISD::ZEXTLOAD; +}]>; + +// It's always safe to treat a anyext i16 load as a i32 load if the i16 is +// known to be 32-bit aligned or better. Ditto for i8 to i16. +def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + if (ExtType == ISD::NON_EXTLOAD) + return true; + if (ExtType == ISD::EXTLOAD) + return LD->getAlignment() >= 2 && !LD->isVolatile(); + return false; +}]>; + +def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + if (ExtType == ISD::NON_EXTLOAD) + return true; + if (ExtType == ISD::EXTLOAD) + return LD->getAlignment() >= 4 && !LD->isVolatile(); + return false; +}]>; + +def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; +def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; +def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; +def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; +def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>; +def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ + LoadSDNode *Ld = cast(N); + return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); +}]>; +def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ + LoadSDNode *Ld = cast(N); + return Subtarget->hasSSEUnalignedMem() || + Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); +}]>; + +def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; +def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; +def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; +def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; +def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; +def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; + +def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; +def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; +def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; +def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; +def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; +def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; +def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; +def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; +def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; +def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; + +def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; +def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; +def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; +def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; +def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; +def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; +def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; +def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; +def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; +def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; + + +// An 'and' node with a single use. +def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ + return N->hasOneUse(); +}]>; +// An 'srl' node with a single use. +def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ + return N->hasOneUse(); +}]>; +// An 'trunc' node with a single use. +def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ + return N->hasOneUse(); +}]>; + +//===----------------------------------------------------------------------===// +// Instruction list. +// + +// Nop +let hasSideEffects = 0, SchedRW = [WriteNop] in { + def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; + def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; + def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; + def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero), + "nop{q}\t$zero", []>, TB, NotMemoryFoldable, + Requires<[In64BitMode]>; + // Also allow register so we can assemble/disassemble + def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; + def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; + def NOOPQr : RI<0x1f, MRMXr, (outs), (ins GR64:$zero), + "nop{q}\t$zero", []>, TB, NotMemoryFoldable, + Requires<[In64BitMode]>; + def NOOPW_19 : I<0x19, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOPL_19 : I<0x19, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + //def NOOPW_1a : I<0x1a, MRMXm, (outs), (ins i16mem:$zero), + // "nop{w}\t$zero", []>, TB, OpSize16; + //def NOOPL_1a : I<0x1a, MRMXm, (outs), (ins i32mem:$zero), + // "nop{l}\t$zero", []>, TB, OpSize32; + //def NOOPW_1b : I<0x1b, MRMXm, (outs), (ins i16mem:$zero), + // "nop{w}\t$zero", []>, TB, OpSize16; + //def NOOPL_1b : I<0x1b, MRMXm, (outs), (ins i32mem:$zero), + // "nop{l}\t$zero", []>, TB, OpSize32; + def NOOPW_1c : I<0x1c, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + //def NOOPL_1c : I<0x1c, MRMXm, (outs), (ins i32mem:$zero), + // "nop{l}\t$zero", []>, TB, OpSize32; + def NOOPW_1d : I<0x1d, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOPL_1d : I<0x1d, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + def NOOPW_1e : I<0x1e, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOPL_1e : I<0x1e, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m4 : I<0x18, MRM4m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m4 : I<0x18, MRM4m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r4 : I<0x18, MRM4r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r4 : I<0x18, MRM4r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m5 : I<0x18, MRM5m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m5 : I<0x18, MRM5m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r5 : I<0x18, MRM5r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r5 : I<0x18, MRM5r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m6 : I<0x18, MRM6m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m6 : I<0x18, MRM6m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r6 : I<0x18, MRM6r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r6 : I<0x18, MRM6r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m7 : I<0x18, MRM7m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m7 : I<0x18, MRM7m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r7 : I<0x18, MRM7r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r7 : I<0x18, MRM7r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; +} + + +// Constructing a stack frame. +def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), + "enter\t$len, $lvl", []>, Sched<[WriteMicrocoded]>; + +let SchedRW = [WriteALU] in { +let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in +def LEAVE : I<0xC9, RawFrm, (outs), (ins), "leave", []>, + Requires<[Not64BitMode]>; + +let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in +def LEAVE64 : I<0xC9, RawFrm, (outs), (ins), "leave", []>, + Requires<[In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Miscellaneous Instructions. +// + +/* +let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1, + SchedRW = [WriteSystem] in + def Int_eh_sjlj_setup_dispatch + : PseudoI<(outs), (ins), [(X86eh_sjlj_setup_dispatch)]>; +*/ + +let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { +let mayLoad = 1, SchedRW = [WriteLoad] in { +def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, + OpSize16; +def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, + OpSize32, Requires<[Not64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, + OpSize16, NotMemoryFoldable; +def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, + OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 +} // mayLoad, SchedRW +let mayStore = 1, mayLoad = 1, SchedRW = [WriteRMW] in { +def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>, + OpSize16; +def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>, + OpSize32, Requires<[Not64BitMode]>; +} // mayStore, mayLoad, WriteRMW + +let mayStore = 1, SchedRW = [WriteStore] in { +def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, + OpSize16; +def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, + OpSize32, Requires<[Not64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, + OpSize16, NotMemoryFoldable; +def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, + OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 + +def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), + "push{w}\t$imm", []>, OpSize16; +def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), + "push{w}\t$imm", []>, OpSize16; + +def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), + "push{l}\t$imm", []>, OpSize32, + Requires<[Not64BitMode]>; +def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), + "push{l}\t$imm", []>, OpSize32, + Requires<[Not64BitMode]>; +} // mayStore, SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { +def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>, + OpSize16; +def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>, + OpSize32, Requires<[Not64BitMode]>; +} // mayLoad, mayStore, SchedRW + +} + +/* +let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, + SchedRW = [WriteRMW], Defs = [ESP] in { + let Uses = [ESP] in + def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins), + [(set GR32:$dst, (int_x86_flags_read_u32))]>, + Requires<[Not64BitMode]>; + + let Uses = [RSP] in + def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins), + [(set GR64:$dst, (int_x86_flags_read_u64))]>, + Requires<[In64BitMode]>; +} + +let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, + SchedRW = [WriteRMW] in { + let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in + def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src), + [(int_x86_flags_write_u32 GR32:$src)]>, + Requires<[Not64BitMode]>; + + let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in + def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src), + [(int_x86_flags_write_u64 GR64:$src)]>, + Requires<[In64BitMode]>; +} +*/ + +let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0, + SchedRW = [WriteLoad] in { +def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize16; +def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, OpSize32, + Requires<[Not64BitMode]>; +} + +let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0, + SchedRW = [WriteStore] in { +def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize16; +def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, OpSize32, + Requires<[Not64BitMode]>; +} + +let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { +let mayLoad = 1, SchedRW = [WriteLoad] in { +def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 +} // mayLoad, SchedRW +let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in +def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>, + OpSize32, Requires<[In64BitMode]>; +let mayStore = 1, SchedRW = [WriteStore] in { +def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 +} // mayStore, SchedRW +let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { +def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>, + OpSize32, Requires<[In64BitMode]>; +} // mayLoad, mayStore, SchedRW +} + +let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, + SchedRW = [WriteStore] in { +def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), + "push{q}\t$imm", []>, OpSize32, + Requires<[In64BitMode]>; +def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), + "push{q}\t$imm", []>, OpSize32, + Requires<[In64BitMode]>; +} + +let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in +def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, + OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; +let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in +def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, + OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; + +let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], + mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { +def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", []>, + OpSize32, Requires<[Not64BitMode]>; +def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", []>, + OpSize16, Requires<[Not64BitMode]>; +} +let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], + mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { +def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", []>, + OpSize32, Requires<[Not64BitMode]>; +def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", []>, + OpSize16, Requires<[Not64BitMode]>; +} + +let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in { +// This instruction is a consequence of BSWAP32r observing operand size. The +// encoding is valid, but the behavior is undefined. +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in +def BSWAP16r_BAD : I<0xC8, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), + "bswap{w}\t$dst", []>, OpSize16, TB; +// GR32 = bswap GR32 +def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), + "bswap{l}\t$dst", + [(set GR32:$dst, (bswap GR32:$src))]>, OpSize32, TB; + +let SchedRW = [WriteBSWAP64] in +def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), + "bswap{q}\t$dst", + [(set GR64:$dst, (bswap GR64:$src))]>, TB; +} // Constraints = "$src = $dst", SchedRW + +// Bit scan instructions. +let Defs = [EFLAGS] in { +def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "bsf{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, + PS, OpSize16, Sched<[WriteBSF]>; +def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "bsf{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, + PS, OpSize16, Sched<[WriteBSFLd]>; +def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "bsf{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, + PS, OpSize32, Sched<[WriteBSF]>; +def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "bsf{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, + PS, OpSize32, Sched<[WriteBSFLd]>; +def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "bsf{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, + PS, Sched<[WriteBSF]>; +def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "bsf{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, + PS, Sched<[WriteBSFLd]>; + +def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "bsr{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, + PS, OpSize16, Sched<[WriteBSR]>; +def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "bsr{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, + PS, OpSize16, Sched<[WriteBSRLd]>; +def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "bsr{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, + PS, OpSize32, Sched<[WriteBSR]>; +def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "bsr{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, + PS, OpSize32, Sched<[WriteBSRLd]>; +def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "bsr{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, + PS, Sched<[WriteBSR]>; +def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "bsr{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, + PS, Sched<[WriteBSRLd]>; +} // Defs = [EFLAGS] + +let SchedRW = [WriteMicrocoded] in { +let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in { +def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), + "movsb\t{$src, $dst|$dst, $src}", []>; +def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), + "movsw\t{$src, $dst|$dst, $src}", []>, OpSize16; +def MOVSL : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), + "movs{l|d}\t{$src, $dst|$dst, $src}", []>, OpSize32; +def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), + "movsq\t{$src, $dst|$dst, $src}", []>, + Requires<[In64BitMode]>; +} + +let Defs = [EDI], Uses = [AL,EDI,DF] in +def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst), + "stosb\t{%al, $dst|$dst, al}", []>; +let Defs = [EDI], Uses = [AX,EDI,DF] in +def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst), + "stosw\t{%ax, $dst|$dst, ax}", []>, OpSize16; +let Defs = [EDI], Uses = [EAX,EDI,DF] in +def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst), + "stos{l|d}\t{%eax, $dst|$dst, eax}", []>, OpSize32; +let Defs = [RDI], Uses = [RAX,RDI,DF] in +def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst), + "stosq\t{%rax, $dst|$dst, rax}", []>, + Requires<[In64BitMode]>; + +let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in +def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), + "scasb\t{$dst, %al|al, $dst}", []>; +let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in +def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), + "scasw\t{$dst, %ax|ax, $dst}", []>, OpSize16; +let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in +def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), + "scas{l|d}\t{$dst, %eax|eax, $dst}", []>, OpSize32; +let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in +def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), + "scasq\t{$dst, %rax|rax, $dst}", []>, + Requires<[In64BitMode]>; + +let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in { +def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), + "cmpsb\t{$dst, $src|$src, $dst}", []>; +def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), + "cmpsw\t{$dst, $src|$src, $dst}", []>, OpSize16; +def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), + "cmps{l|d}\t{$dst, $src|$src, $dst}", []>, OpSize32; +def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), + "cmpsq\t{$dst, $src|$src, $dst}", []>, + Requires<[In64BitMode]>; +} +} // SchedRW + +//===----------------------------------------------------------------------===// +// Move Instructions. +// +let SchedRW = [WriteMove] in { +let hasSideEffects = 0, isMoveReg = 1 in { +def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>; +def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; +def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; +def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>; +} + +let isReMaterializable = 1, isAsCheapAsAMove = 1 in { +def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(set GR8:$dst, imm:$src)]>; +def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, imm:$src)]>, OpSize16; +def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, relocImm:$src)]>, OpSize32; +def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, i64immSExt32:$src)]>; +} +let isReMaterializable = 1 in { +def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), + "movabs{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, relocImm:$src)]>; +} + +// Longer forms that use a ModR/M byte. Needed for disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { +def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOV8ri">; +def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, + FoldGenData<"MOV16ri">; +def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, + FoldGenData<"MOV32ri">; +} +} // SchedRW + +let SchedRW = [WriteStore] in { +def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(store (i8 imm8_su:$src), addr:$dst)]>; +def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(store (i16 imm16_su:$src), addr:$dst)]>, OpSize16; +def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(store (i32 imm32_su:$src), addr:$dst)]>, OpSize32; +def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(store i64immSExt32_su:$src, addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW + +let hasSideEffects = 0 in { + +/// Memory offset versions of moves. The immediate is an address mode sized +/// offset from the segment base. +let SchedRW = [WriteALU] in { +let mayLoad = 1 in { +let Defs = [AL] in +def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), + "mov{b}\t{$src, %al|al, $src}", []>, + AdSize32; +let Defs = [AX] in +def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), + "mov{w}\t{$src, %ax|ax, $src}", []>, + OpSize16, AdSize32; +let Defs = [EAX] in +def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), + "mov{l}\t{$src, %eax|eax, $src}", []>, + OpSize32, AdSize32; +let Defs = [RAX] in +def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), + "mov{q}\t{$src, %rax|rax, $src}", []>, + AdSize32; + +let Defs = [AL] in +def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), + "mov{b}\t{$src, %al|al, $src}", []>, AdSize16; +let Defs = [AX] in +def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), + "mov{w}\t{$src, %ax|ax, $src}", []>, + OpSize16, AdSize16; +let Defs = [EAX] in +def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), + "mov{l}\t{$src, %eax|eax, $src}", []>, + AdSize16, OpSize32; +} // mayLoad +let mayStore = 1 in { +let Uses = [AL] in +def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst), + "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize32; +let Uses = [AX] in +def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_16:$dst), + "mov{w}\t{%ax, $dst|$dst, ax}", []>, + OpSize16, AdSize32; +let Uses = [EAX] in +def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_32:$dst), + "mov{l}\t{%eax, $dst|$dst, eax}", []>, + OpSize32, AdSize32; +let Uses = [RAX] in +def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs), (ins offset32_64:$dst), + "mov{q}\t{%rax, $dst|$dst, rax}", []>, + AdSize32; + +let Uses = [AL] in +def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs), (ins offset16_8:$dst), + "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize16; +let Uses = [AX] in +def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_16:$dst), + "mov{w}\t{%ax, $dst|$dst, ax}", []>, + OpSize16, AdSize16; +let Uses = [EAX] in +def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst), + "mov{l}\t{%eax, $dst|$dst, eax}", []>, + OpSize32, AdSize16; +} // mayStore + +// These forms all have full 64-bit absolute addresses in their instructions +// and use the movabs mnemonic to indicate this specific form. +let mayLoad = 1 in { +let Defs = [AL] in +def MOV8ao64 : Ii64<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), + "movabs{b}\t{$src, %al|al, $src}", []>, + AdSize64; +let Defs = [AX] in +def MOV16ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), + "movabs{w}\t{$src, %ax|ax, $src}", []>, + OpSize16, AdSize64; +let Defs = [EAX] in +def MOV32ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), + "movabs{l}\t{$src, %eax|eax, $src}", []>, + OpSize32, AdSize64; +let Defs = [RAX] in +def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), + "movabs{q}\t{$src, %rax|rax, $src}", []>, + AdSize64; +} // mayLoad + +let mayStore = 1 in { +let Uses = [AL] in +def MOV8o64a : Ii64<0xA2, RawFrmMemOffs, (outs), (ins offset64_8:$dst), + "movabs{b}\t{%al, $dst|$dst, al}", []>, + AdSize64; +let Uses = [AX] in +def MOV16o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_16:$dst), + "movabs{w}\t{%ax, $dst|$dst, ax}", []>, + OpSize16, AdSize64; +let Uses = [EAX] in +def MOV32o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_32:$dst), + "movabs{l}\t{%eax, $dst|$dst, eax}", []>, + OpSize32, AdSize64; +let Uses = [RAX] in +def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst), + "movabs{q}\t{%rax, $dst|$dst, rax}", []>, + AdSize64; +} // mayStore +} // SchedRW +} // hasSideEffects = 0 + +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, + SchedRW = [WriteMove], isMoveReg = 1 in { +def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOV8rr">; +def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, + FoldGenData<"MOV16rr">; +def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, + FoldGenData<"MOV32rr">; +def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOV64rr">; +} + +// Reversed version with ".s" suffix for GAS compatibility. +//def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}", +// (MOV8rr_REV GR8:$dst, GR8:$src), 0>; +//def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}", +// (MOV16rr_REV GR16:$dst, GR16:$src), 0>; +//def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}", +// (MOV32rr_REV GR32:$dst, GR32:$src), 0>; +//def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}", +// (MOV64rr_REV GR64:$dst, GR64:$src), 0>; +//def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">; +//def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">; +//def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">; +//def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">; + +let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { +def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(set GR8:$dst, (loadi8 addr:$src))]>; +def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize16; +def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (loadi32 addr:$src))]>, OpSize32; +def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (load addr:$src))]>; +} + +let SchedRW = [WriteStore] in { +def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(store GR8:$src, addr:$dst)]>; +def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(store GR16:$src, addr:$dst)]>, OpSize16; +def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(store GR32:$src, addr:$dst)]>, OpSize32; +def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(store GR64:$src, addr:$dst)]>; +} // SchedRW + +// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so +// that they can be used for copying and storing h registers, which can't be +// encoded when a REX prefix is present. +let isCodeGenOnly = 1 in { +let hasSideEffects = 0, isMoveReg = 1 in +def MOV8rr_NOREX : I<0x88, MRMDestReg, + (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteMove]>; +let mayStore = 1, hasSideEffects = 0 in +def MOV8mr_NOREX : I<0x88, MRMDestMem, + (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteStore]>; +let mayLoad = 1, hasSideEffects = 0, + canFoldAsLoad = 1, isReMaterializable = 1 in +def MOV8rm_NOREX : I<0x8A, MRMSrcMem, + (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteLoad]>; +} + + +// Condition code ops, incl. set if equal/not equal/... +let SchedRW = [WriteLAHFSAHF] in { +let Defs = [EFLAGS], Uses = [AH] in +def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", + [(set EFLAGS, (X86sahf AH))]>, + Requires<[HasLAHFSAHF]>; +let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in +def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags + Requires<[HasLAHFSAHF]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Bit tests instructions: BT, BTS, BTR, BTC. + +let Defs = [EFLAGS] in { +let SchedRW = [WriteBitTest] in { +def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, + OpSize16, TB, NotMemoryFoldable; +def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, + OpSize32, TB, NotMemoryFoldable; +def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB, + NotMemoryFoldable; +} // SchedRW + +// Unlike with the register+register form, the memory+register form of the +// bt instruction does not ignore the high bits of the index. From ISel's +// perspective, this is pretty bizarre. Make these instructions disassembly +// only for now. These instructions are also slow on modern CPUs so that's +// another reason to avoid generating them. + +let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { + def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + []>, OpSize16, TB, NotMemoryFoldable; + def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + []>, OpSize32, TB, NotMemoryFoldable; + def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + []>, TB, NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest] in { +def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>, + OpSize16, TB; +def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, + OpSize32, TB; +def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB; +} // SchedRW + +// Note that these instructions aren't slow because that only applies when the +// other operand is in a register. When it's an immediate, bt is still fast. +let SchedRW = [WriteALU] in { +def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi16 addr:$src1), + i16immSExt8:$src2))]>, + OpSize16, TB; +def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi32 addr:$src1), + i32immSExt8:$src2))]>, + OpSize32, TB; +def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi64 addr:$src1), + i64immSExt8:$src2))]>, TB, + Requires<[In64BitMode]>; +} // SchedRW + +let hasSideEffects = 0 in { +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTC32rr : I<0xBB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTC64rr : RI<0xBB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTC64ri8 : RIi8<0xBA, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + Requires<[In64BitMode]>; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTR32rr : I<0xB3, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTR64rr : RI<0xB3, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB; +def BTR32ri8 : Ii8<0xBA, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB; +def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB; +def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB; +def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + Requires<[In64BitMode]>; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTS32rr : I<0xAB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTS64rr : RI<0xAB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTS64ri8 : RIi8<0xBA, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + Requires<[In64BitMode]>; +} +} // hasSideEffects = 0 +} // Defs = [EFLAGS] + + +//===----------------------------------------------------------------------===// +// Atomic support +// + +// Atomic swap. These are just normal xchg instructions. But since a memory +// operand is referenced, the atomicity is ensured. +multiclass ATOMIC_SWAP opc8, bits<8> opc, string mnemonic, string frag> { + let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { + def NAME#8rm : I(frag # "_8") addr:$ptr, GR8:$val))]>; + def NAME#16rm : I(frag # "_16") addr:$ptr, GR16:$val))]>, + OpSize16; + def NAME#32rm : I(frag # "_32") addr:$ptr, GR32:$val))]>, + OpSize32; + def NAME#64rm : RI(frag # "_64") addr:$ptr, GR64:$val))]>; + } +} + +defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">, NotMemoryFoldable; + +// Swap between registers. +let SchedRW = [WriteALU] in { +let Constraints = "$src1 = $dst1, $src2 = $dst2", hasSideEffects = 0 in { +def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2), + (ins GR8:$src1, GR8:$src2), + "xchg{b}\t{$src1, $src2|$src2, $src1}", []>, NotMemoryFoldable; +def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2), + (ins GR16:$src1, GR16:$src2), + "xchg{w}\t{$src1, $src2|$src2, $src1}", []>, + OpSize16, NotMemoryFoldable; +def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2), + (ins GR32:$src1, GR32:$src2), + "xchg{l}\t{$src1, $src2|$src2, $src1}", []>, + OpSize32, NotMemoryFoldable; +def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst1, GR64:$dst2), + (ins GR64:$src1 ,GR64:$src2), + "xchg{q}\t{$src1, $src2|$src2, $src1}", []>, NotMemoryFoldable; +} + +def NOOP19rr: I<0x19, MRMSrcReg, (outs), (ins GR32:$val, GR32:$src), + "nop\t{$val, $src|$src, $val}", []>, TB, + OpSize32; + +// Swap between EAX and other registers. +let Constraints = "$src = $dst", hasSideEffects = 0 in { +let Uses = [AX], Defs = [AX] in +def XCHG16ar : I<0x90, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), + "xchg{w}\t{%ax, $src|$src, ax}", []>, OpSize16; +let Uses = [EAX], Defs = [EAX] in +def XCHG32ar : I<0x90, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), + "xchg{l}\t{%eax, $src|$src, eax}", []>, OpSize32; +let Uses = [RAX], Defs = [RAX] in +def XCHG64ar : RI<0x90, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), + "xchg{q}\t{%rax, $src|$src, rax}", []>; +} +} // SchedRW + +let hasSideEffects = 0, Constraints = "$src1 = $dst1, $src2 = $dst2", + Defs = [EFLAGS], SchedRW = [WriteALU] in { +def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst1, GR8:$dst2), + (ins GR8:$src1, GR8:$src2), + "xadd{b}\t{$src2, $src1|$src1, $src2}", []>, TB; +def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst1, GR16:$dst2), + (ins GR16:$src1, GR16:$src2), + "xadd{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16; +def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst1, GR32:$dst2), + (ins GR32:$src1, GR32:$src2), + "xadd{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32; +def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst1, GR64:$dst2), + (ins GR64:$src1, GR64:$src2), + "xadd{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, hasSideEffects = 0, Constraints = "$val = $dst", + Defs = [EFLAGS], SchedRW = [WriteALULd, WriteRMW] in { +def XADD8rm : I<0xC0, MRMSrcMem, (outs GR8:$dst), + (ins GR8:$val, i8mem:$ptr), + "xadd{b}\t{$val, $ptr|$ptr, $val}", []>, TB; +def XADD16rm : I<0xC1, MRMSrcMem, (outs GR16:$dst), + (ins GR16:$val, i16mem:$ptr), + "xadd{w}\t{$val, $ptr|$ptr, $val}", []>, TB, + OpSize16; +def XADD32rm : I<0xC1, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$val, i32mem:$ptr), + "xadd{l}\t{$val, $ptr|$ptr, $val}", []>, TB, + OpSize32; +def XADD64rm : RI<0xC1, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$val, i64mem:$ptr), + "xadd{q}\t{$val, $ptr|$ptr, $val}", []>, TB; + +} + +let SchedRW = [WriteALU], hasSideEffects = 0 in { +let Defs = [AL, EFLAGS], Uses = [AL] in +def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), + "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; +let Defs = [AX, EFLAGS], Uses = [AX] in +def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), + "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, + NotMemoryFoldable; +let Defs = [EAX, EFLAGS], Uses = [EAX] in +def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), + "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, + NotMemoryFoldable; +let Defs = [RAX, EFLAGS], Uses = [RAX] in +def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), + "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; +} // SchedRW, hasSideEffects + +let SchedRW = [WriteALULd, WriteRMW], mayLoad = 1, mayStore = 1, + hasSideEffects = 0 in { +let Defs = [AL, EFLAGS], Uses = [AL] in +def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), + "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; +let Defs = [AX, EFLAGS], Uses = [AX] in +def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, + NotMemoryFoldable; +let Defs = [EAX, EFLAGS], Uses = [EAX] in +def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, + NotMemoryFoldable; +let Defs = [RAX, EFLAGS], Uses = [RAX] in +def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; + +let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in +def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), + "cmpxchg8b\t$dst", []>, TB; + +let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in +def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), + "cmpxchg16b\t$dst", []>, + TB, Requires<[HasCmpxchg16b, In64BitMode]>; +} // SchedRW, mayLoad, mayStore, hasSideEffects + + +// Lock instruction prefix +let SchedRW = [WriteMicrocoded] in +def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; + +let SchedRW = [WriteNop] in { + +// Rex64 instruction prefix +def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>, + Requires<[In64BitMode]>; + +// Data16 instruction prefix +def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; +} // SchedRW + +// Repeat string operation instruction prefixes +let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in { +// Repeat (used with INS, OUTS, MOVS, LODS and STOS) +def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; +// Repeat while not equal (used with CMPS and SCAS) +def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; +} + +// String manipulation instructions +let SchedRW = [WriteMicrocoded] in { +let Defs = [AL,ESI], Uses = [ESI,DF] in +def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), + "lodsb\t{$src, %al|al, $src}", []>; +let Defs = [AX,ESI], Uses = [ESI,DF] in +def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), + "lodsw\t{$src, %ax|ax, $src}", []>, OpSize16; +let Defs = [EAX,ESI], Uses = [ESI,DF] in +def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), + "lods{l|d}\t{$src, %eax|eax, $src}", []>, OpSize32; +let Defs = [RAX,ESI], Uses = [ESI,DF] in +def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), + "lodsq\t{$src, %rax|rax, $src}", []>, + Requires<[In64BitMode]>; +} + +let SchedRW = [WriteSystem] in { +let Defs = [ESI], Uses = [DX,ESI,DF] in { +def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), + "outsb\t{$src, %dx|dx, $src}", []>; +def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), + "outsw\t{$src, %dx|dx, $src}", []>, OpSize16; +def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), + "outs{l|d}\t{$src, %dx|dx, $src}", []>, OpSize32; +} + +let Defs = [EDI], Uses = [DX,EDI,DF] in { +def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst), + "insb\t{%dx, $dst|$dst, dx}", []>; +def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst), + "insw\t{%dx, $dst|$dst, dx}", []>, OpSize16; +def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst), + "ins{l|d}\t{%dx, $dst|$dst, dx}", []>, OpSize32; +} +} + +// EFLAGS management instructions. +let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { +def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; +def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; +def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; +} + +// DF management instructions. +let SchedRW = [WriteALU], Defs = [DF] in { +def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; +def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; +} + +// Table lookup instructions +let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in +def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>, Sched<[WriteLoad]>; + +let SchedRW = [WriteMicrocoded] in { +// ASCII Adjust After Addition +let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, + Requires<[Not64BitMode]>; + +// ASCII Adjust AX Before Division +let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), + "aad\t$src", []>, Requires<[Not64BitMode]>; + +// ASCII Adjust AX After Multiply +let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), + "aam\t$src", []>, Requires<[Not64BitMode]>; + +// ASCII Adjust AL After Subtraction - sets +let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, + Requires<[Not64BitMode]>; + +// Decimal Adjust AL after Addition +let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in +def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, + Requires<[Not64BitMode]>; + +// Decimal Adjust AL after Subtraction +let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in +def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, + Requires<[Not64BitMode]>; +} // SchedRW + +let SchedRW = [WriteSystem] in { +// Check Array Index Against Bounds +// Note: "bound" does not have reversed operands in at&t syntax. +def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i32mem:$src), + "bound\t$dst, $src", []>, OpSize16, + Requires<[Not64BitMode]>; +def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i64mem:$src), + "bound\t$dst, $src", []>, OpSize32, + Requires<[Not64BitMode]>; + +// Adjust RPL Field of Segment Selector +def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), + "arpl\t{$src, $dst|$dst, $src}", []>, + Requires<[Not64BitMode]>, NotMemoryFoldable; +let mayStore = 1 in +def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "arpl\t{$src, $dst|$dst, $src}", []>, + Requires<[Not64BitMode]>, NotMemoryFoldable; +} // SchedRW + +//===----------------------------------------------------------------------===// +// MOVBE Instructions +// +let Predicates = [HasMOVBE] in { + let SchedRW = [WriteALULd] in { + def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "movbe{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, + OpSize16, T8PS; + def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "movbe{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, + OpSize32, T8PS; + def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "movbe{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, + T8PS; + } + let SchedRW = [WriteStore] in { + def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "movbe{w}\t{$src, $dst|$dst, $src}", + [(store (bswap GR16:$src), addr:$dst)]>, + OpSize16, T8PS; + def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "movbe{l}\t{$src, $dst|$dst, $src}", + [(store (bswap GR32:$src), addr:$dst)]>, + OpSize32, T8PS; + def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "movbe{q}\t{$src, $dst|$dst, $src}", + [(store (bswap GR64:$src), addr:$dst)]>, + T8PS; + } +} + +//===----------------------------------------------------------------------===// +// RDRAND Instruction +// +let Predicates = [HasRDRAND], Defs = [EFLAGS], SchedRW = [WriteSystem] in { + def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), + "rdrand{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86rdrand))]>, + OpSize16, PS; + def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), + "rdrand{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86rdrand))]>, + OpSize32, PS; + def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), + "rdrand{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86rdrand))]>, + PS; +} + +//===----------------------------------------------------------------------===// +// RDSEED Instruction +// +let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in { + def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), "rdseed{w}\t$dst", + [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, PS; + def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), "rdseed{l}\t$dst", + [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, PS; + def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdseed{q}\t$dst", + [(set GR64:$dst, EFLAGS, (X86rdseed))]>, PS; +} + +//===----------------------------------------------------------------------===// +// LZCNT Instruction +// +let Predicates = [HasLZCNT], Defs = [EFLAGS] in { + def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "lzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, + XS, OpSize16, Sched<[WriteLZCNT]>; + def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "lzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (ctlz (loadi16 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteLZCNTLd]>; + + def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "lzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, + XS, OpSize32, Sched<[WriteLZCNT]>; + def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "lzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (ctlz (loadi32 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteLZCNTLd]>; + + def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "lzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, + XS, Sched<[WriteLZCNT]>; + def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "lzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (ctlz (loadi64 addr:$src))), + (implicit EFLAGS)]>, XS, Sched<[WriteLZCNTLd]>; +} + +//===----------------------------------------------------------------------===// +// BMI Instructions +// +let Predicates = [HasBMI], Defs = [EFLAGS] in { + def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "tzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, + XS, OpSize16, Sched<[WriteTZCNT]>; + def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "tzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (cttz (loadi16 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteTZCNTLd]>; + + def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "tzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, + XS, OpSize32, Sched<[WriteTZCNT]>; + def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "tzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (cttz (loadi32 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteTZCNTLd]>; + + def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "tzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, + XS, Sched<[WriteTZCNT]>; + def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "tzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (cttz (loadi64 addr:$src))), + (implicit EFLAGS)]>, XS, Sched<[WriteTZCNTLd]>; +} + +multiclass bmi_bls { +let hasSideEffects = 0 in { + def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), + !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, + T8PS, VEX_4V, Sched<[WriteALU]>; + let mayLoad = 1 in + def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), + !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, + T8PS, VEX_4V, Sched<[WriteALULd]>; +} +} + +let Predicates = [HasBMI], Defs = [EFLAGS] in { + defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; + defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W; + defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>; + defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W; + defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>; + defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W; +} + +//===----------------------------------------------------------------------===// +// Pattern fragments to auto generate BMI instructions. +//===----------------------------------------------------------------------===// + +let Predicates = [HasBMI] in { + // FIXME: patterns for the load versions are not implemented + def : Pat<(and GR32:$src, (add GR32:$src, -1)), + (BLSR32rr GR32:$src)>; + def : Pat<(and GR64:$src, (add GR64:$src, -1)), + (BLSR64rr GR64:$src)>; + + def : Pat<(xor GR32:$src, (add GR32:$src, -1)), + (BLSMSK32rr GR32:$src)>; + def : Pat<(xor GR64:$src, (add GR64:$src, -1)), + (BLSMSK64rr GR64:$src)>; + + def : Pat<(and GR32:$src, (ineg GR32:$src)), + (BLSI32rr GR32:$src)>; + def : Pat<(and GR64:$src, (ineg GR64:$src)), + (BLSI64rr GR64:$src)>; +} + +multiclass bmi_bextr opc, string mnemonic, RegisterClass RC, + X86MemOperand x86memop, SDNode OpNode, + PatFrag ld_frag, X86FoldableSchedWrite Sched> { + def rr : I, + T8PS, VEX, Sched<[Sched]>; + def rm : I, T8PS, VEX, + Sched<[Sched.Folded, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + ReadAfterLd]>; +} + +let Predicates = [HasBMI], Defs = [EFLAGS] in { + defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem, + X86bextr, loadi32, WriteBEXTR>; + defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem, + X86bextr, loadi64, WriteBEXTR>, VEX_W; +} + +multiclass bmi_bzhi opc, string mnemonic, RegisterClass RC, + X86MemOperand x86memop, Intrinsic Int, + PatFrag ld_frag, X86FoldableSchedWrite Sched> { + def rr : I, + T8PS, VEX, Sched<[Sched]>; + def rm : I, T8PS, VEX, + Sched<[Sched.Folded, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + ReadAfterLd]>; +} + +let Predicates = [HasBMI2], Defs = [EFLAGS] in { + defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem, + int_x86_bmi_bzhi_32, loadi32, WriteBZHI>; + defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem, + int_x86_bmi_bzhi_64, loadi64, WriteBZHI>, VEX_W; +} + +def CountTrailingOnes : SDNodeXFormgetZExtValue()), SDLoc(N)); +}]>; + +def BEXTRMaskXForm : SDNodeXFormgetZExtValue()); + return getI32Imm(Length << 8, SDLoc(N)); +}]>; + +def AndMask64 : ImmLeaf(Imm); +}]>; + +// Use BEXTR for 64-bit 'and' with large immediate 'mask'. +let Predicates = [HasBMI, NoBMI2, NoTBM] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BEXTR64rr GR64:$src, + (SUBREG_TO_REG (i64 0), + (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BEXTR64rm addr:$src, + (SUBREG_TO_REG (i64 0), + (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; +} + +// Use BZHI for 64-bit 'and' with large immediate 'mask'. +let Predicates = [HasBMI2, NoTBM] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; +} + +let Predicates = [HasBMI2] in { + multiclass _bmi_bzhi_pattern { + def : Pat; + def : Pat; + } + + multiclass bmi_bzhi_patterns { + // x & ((1 << y) - 1) + defm : _bmi_bzhi_pattern<(and RC:$src, (add (shl 1, GR8:$lz), -1)), + (and (x86memop addr:$src), + (add (shl 1, GR8:$lz), -1)), + RC, VT, DstInst, DstMemInst>; + + // x & ~(-1 << y) + defm : _bmi_bzhi_pattern<(and RC:$src, (xor (shl -1, GR8:$lz), -1)), + (and (x86memop addr:$src), + (xor (shl -1, GR8:$lz), -1)), + RC, VT, DstInst, DstMemInst>; + + // x & (-1 >> (bitwidth - y)) + defm : _bmi_bzhi_pattern<(and RC:$src, (srl -1, (sub bitwidth, GR8:$lz))), + (and (x86memop addr:$src), + (srl -1, (sub bitwidth, GR8:$lz))), + RC, VT, DstInst, DstMemInst>; + + // x << (bitwidth - y) >> (bitwidth - y) + defm : _bmi_bzhi_pattern<(srl (shl RC:$src, (sub bitwidth, GR8:$lz)), + (sub bitwidth, GR8:$lz)), + (srl (shl (x86memop addr:$src), + (sub bitwidth, GR8:$lz)), + (sub bitwidth, GR8:$lz)), + RC, VT, DstInst, DstMemInst>; + } + + defm : bmi_bzhi_patterns; + defm : bmi_bzhi_patterns; + + // x & (-1 >> (32 - y)) + def : Pat<(and GR32:$src, (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), + (BZHI32rr GR32:$src, GR32:$lz)>; + def : Pat<(and (loadi32 addr:$src), (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), + (BZHI32rm addr:$src, GR32:$lz)>; + + // x & (-1 >> (64 - y)) + def : Pat<(and GR64:$src, (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + def : Pat<(and (loadi64 addr:$src), (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + + // x << (32 - y) >> (32 - y) + def : Pat<(srl (shl GR32:$src, (i8 (trunc (sub 32, GR32:$lz)))), + (i8 (trunc (sub 32, GR32:$lz)))), + (BZHI32rr GR32:$src, GR32:$lz)>; + def : Pat<(srl (shl (loadi32 addr:$src), (i8 (trunc (sub 32, GR32:$lz)))), + (i8 (trunc (sub 32, GR32:$lz)))), + (BZHI32rm addr:$src, GR32:$lz)>; + + // x << (64 - y) >> (64 - y) + def : Pat<(srl (shl GR64:$src, (i8 (trunc (sub 64, GR32:$lz)))), + (i8 (trunc (sub 64, GR32:$lz)))), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + def : Pat<(srl (shl (loadi64 addr:$src), (i8 (trunc (sub 64, GR32:$lz)))), + (i8 (trunc (sub 64, GR32:$lz)))), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; +} // HasBMI2 + +multiclass bmi_pdep_pext { + def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, + VEX_4V, Sched<[WriteALU]>; + def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, + VEX_4V, Sched<[WriteALULd, ReadAfterLd]>; +} + +let Predicates = [HasBMI2] in { + defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, + int_x86_bmi_pdep_32, loadi32>, T8XD; + defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, + int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; + defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, + int_x86_bmi_pext_32, loadi32>, T8XS; + defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, + int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; +} + +//===----------------------------------------------------------------------===// +// TBM Instructions +// +let Predicates = [HasTBM], Defs = [EFLAGS] in { + +multiclass tbm_ternary_imm opc, RegisterClass RC, string OpcodeStr, + X86MemOperand x86memop, PatFrag ld_frag, + SDNode OpNode, Operand immtype, + SDPatternOperator immoperator, + X86FoldableSchedWrite Sched> { + def ri : Ii32, + XOP, XOPA, Sched<[Sched]>; + def mi : Ii32, + XOP, XOPA, Sched<[Sched.Folded]>; +} + +defm BEXTRI32 : tbm_ternary_imm<0x10, GR32, "bextr{l}", i32mem, loadi32, + X86bextr, i32imm, imm, WriteBEXTR>; +let ImmT = Imm32S in +defm BEXTRI64 : tbm_ternary_imm<0x10, GR64, "bextr{q}", i64mem, loadi64, + X86bextr, i64i32imm, + i64immSExt32, WriteBEXTR>, VEX_W; + +multiclass tbm_binary_rm opc, Format FormReg, Format FormMem, + RegisterClass RC, string OpcodeStr, + X86MemOperand x86memop, X86FoldableSchedWrite Sched> { +let hasSideEffects = 0 in { + def rr : I, + XOP_4V, XOP9, Sched<[Sched]>; + let mayLoad = 1 in + def rm : I, + XOP_4V, XOP9, Sched<[Sched.Folded]>; +} +} + +multiclass tbm_binary_intr opc, string OpcodeStr, + X86FoldableSchedWrite Sched, + Format FormReg, Format FormMem> { + defm NAME#32 : tbm_binary_rm; + defm NAME#64 : tbm_binary_rm, VEX_W; +} + +defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>; +defm BLCI : tbm_binary_intr<0x02, "blci", WriteALU, MRM6r, MRM6m>; +defm BLCIC : tbm_binary_intr<0x01, "blcic", WriteALU, MRM5r, MRM5m>; +defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", WriteALU, MRM1r, MRM1m>; +defm BLCS : tbm_binary_intr<0x01, "blcs", WriteALU, MRM3r, MRM3m>; +defm BLSFILL : tbm_binary_intr<0x01, "blsfill", WriteALU, MRM2r, MRM2m>; +defm BLSIC : tbm_binary_intr<0x01, "blsic", WriteALU, MRM6r, MRM6m>; +defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", WriteALU, MRM7r, MRM7m>; +defm TZMSK : tbm_binary_intr<0x01, "tzmsk", WriteALU, MRM4r, MRM4m>; +} // HasTBM, EFLAGS + +// Use BEXTRI for 64-bit 'and' with large immediate 'mask'. +let Predicates = [HasTBM] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BEXTRI64ri GR64:$src, (BEXTRMaskXForm imm:$mask))>; + + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BEXTRI64mi addr:$src, (BEXTRMaskXForm imm:$mask))>; +} + +//===----------------------------------------------------------------------===// +// Lightweight Profiling Instructions + +let Predicates = [HasLWP], SchedRW = [WriteSystem] in { + +def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", + [(int_x86_llwpcb GR32:$src)]>, XOP, XOP9; +def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", + [(set GR32:$dst, (int_x86_slwpcb))]>, XOP, XOP9; + +def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", + [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, VEX_W; +def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", + [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, VEX_W; + +multiclass lwpins_intr { + def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), + "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, imm:$cntl))]>, + XOP_4V, XOPA; + let mayLoad = 1 in + def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), + "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), imm:$cntl))]>, + XOP_4V, XOPA; +} + +let Defs = [EFLAGS] in { + defm LWPINS32 : lwpins_intr; + defm LWPINS64 : lwpins_intr, VEX_W; +} // EFLAGS + +multiclass lwpval_intr { + def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), + "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(Int RC:$src0, GR32:$src1, imm:$cntl)]>, XOP_4V, XOPA; + let mayLoad = 1 in + def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), + "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(Int RC:$src0, (loadi32 addr:$src1), imm:$cntl)]>, + XOP_4V, XOPA; +} + +defm LWPVAL32 : lwpval_intr; +defm LWPVAL64 : lwpval_intr, VEX_W; + +} // HasLWP, SchedRW + +//===----------------------------------------------------------------------===// +// MONITORX/MWAITX Instructions +// +let SchedRW = [ WriteSystem ] in { +/* + let usesCustomInserter = 1 in { + def MONITORX : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3), + [(int_x86_monitorx addr:$src1, GR32:$src2, GR32:$src3)]>, + Requires<[ HasMWAITX ]>; + } +*/ + + let Uses = [ EAX, ECX, EDX ] in { + def MONITORXrrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, + TB, Requires<[ HasMWAITX ]>; + } + + let Uses = [ ECX, EAX, EBX ] in { + def MWAITXrrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", + [(int_x86_mwaitx ECX, EAX, EBX)]>, + TB, Requires<[ HasMWAITX ]>; + } +} // SchedRW + +def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrrr)>, + Requires<[ Not64BitMode ]>; +def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>, + Requires<[ In64BitMode ]>; + +def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORXrrr)>, + Requires<[ Not64BitMode ]>; +def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>, + Requires<[ In64BitMode ]>; + +//===----------------------------------------------------------------------===// +// WAITPKG Instructions +// +let SchedRW = [WriteSystem] in { + def UMONITOR16 : I<0xAE, MRM6r, (outs), (ins GR16:$src), + "umonitor\t$src", [(int_x86_umonitor GR16:$src)]>, + XS, AdSize16, Requires<[HasWAITPKG, Not64BitMode]>; + def UMONITOR32 : I<0xAE, MRM6r, (outs), (ins GR32:$src), + "umonitor\t$src", [(int_x86_umonitor GR32:$src)]>, + XS, AdSize32, Requires<[HasWAITPKG]>; + def UMONITOR64 : I<0xAE, MRM6r, (outs), (ins GR64:$src), + "umonitor\t$src", [(int_x86_umonitor GR64:$src)]>, + XS, AdSize64, Requires<[HasWAITPKG, In64BitMode]>; + let Uses = [EAX, EDX], Defs = [EFLAGS] in { + def UMWAIT : I<0xAE, MRM6r, + (outs), (ins GR32orGR64:$src), "umwait\t$src", + [(set EFLAGS, (X86umwait GR32orGR64:$src, EDX, EAX))]>, + XD, Requires<[HasWAITPKG]>; + def TPAUSE : I<0xAE, MRM6r, + (outs), (ins GR32orGR64:$src), "tpause\t$src", + [(set EFLAGS, (X86tpause GR32orGR64:$src, EDX, EAX))]>, + PD, Requires<[HasWAITPKG]>, NotMemoryFoldable; + } +} // SchedRW + +//===----------------------------------------------------------------------===// +// MOVDIRI - Move doubleword/quadword as direct store +// +let SchedRW = [WriteStore] in { +def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "movdiri\t{$src, $dst|$dst, $src}", + [(int_x86_directstore32 addr:$dst, GR32:$src)]>, + T8, Requires<[HasMOVDIRI]>; +def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "movdiri\t{$src, $dst|$dst, $src}", + [(int_x86_directstore64 addr:$dst, GR64:$src)]>, + T8, Requires<[In64BitMode, HasMOVDIRI]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// MOVDIR64B - Move 64 bytes as direct store +// +let SchedRW = [WriteStore] in { +def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), + "movdir64b\t{$src, $dst|$dst, $src}", []>, + T8PD, AdSize16, Requires<[HasMOVDIR64B, Not64BitMode]>; +def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), + "movdir64b\t{$src, $dst|$dst, $src}", + [(int_x86_movdir64b GR32:$dst, addr:$src)]>, + T8PD, AdSize32, Requires<[HasMOVDIR64B]>; +def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), + "movdir64b\t{$src, $dst|$dst, $src}", + [(int_x86_movdir64b GR64:$dst, addr:$src)]>, + T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// CLZERO Instruction +// +let SchedRW = [WriteSystem] in { + let Uses = [EAX] in + def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, + TB, Requires<[HasCLZERO]>; + +/* + let usesCustomInserter = 1 in { + def CLZERO : PseudoI<(outs), (ins i32mem:$src1), + [(int_x86_clzero addr:$src1)]>, Requires<[HasCLZERO]>; + } +*/ +} // SchedRW + +def : InstAlias<"clzero\t{%eax|eax}", (CLZEROr)>, Requires<[Not64BitMode]>; +def : InstAlias<"clzero\t{%rax|rax}", (CLZEROr)>, Requires<[In64BitMode]>; + +//===----------------------------------------------------------------------===// +// Pattern fragments to auto generate TBM instructions. +//===----------------------------------------------------------------------===// + +let Predicates = [HasTBM] in { + // FIXME: patterns for the load versions are not implemented + def : Pat<(and GR32:$src, (add GR32:$src, 1)), + (BLCFILL32rr GR32:$src)>; + def : Pat<(and GR64:$src, (add GR64:$src, 1)), + (BLCFILL64rr GR64:$src)>; + + def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), + (BLCI32rr GR32:$src)>; + def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), + (BLCI64rr GR64:$src)>; + + // Extra patterns because opt can optimize the above patterns to this. + def : Pat<(or GR32:$src, (sub -2, GR32:$src)), + (BLCI32rr GR32:$src)>; + def : Pat<(or GR64:$src, (sub -2, GR64:$src)), + (BLCI64rr GR64:$src)>; + + def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), + (BLCIC32rr GR32:$src)>; + def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), + (BLCIC64rr GR64:$src)>; + + def : Pat<(xor GR32:$src, (add GR32:$src, 1)), + (BLCMSK32rr GR32:$src)>; + def : Pat<(xor GR64:$src, (add GR64:$src, 1)), + (BLCMSK64rr GR64:$src)>; + + def : Pat<(or GR32:$src, (add GR32:$src, 1)), + (BLCS32rr GR32:$src)>; + def : Pat<(or GR64:$src, (add GR64:$src, 1)), + (BLCS64rr GR64:$src)>; + + def : Pat<(or GR32:$src, (add GR32:$src, -1)), + (BLSFILL32rr GR32:$src)>; + def : Pat<(or GR64:$src, (add GR64:$src, -1)), + (BLSFILL64rr GR64:$src)>; + + def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), + (BLSIC32rr GR32:$src)>; + def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), + (BLSIC64rr GR64:$src)>; + + def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), + (T1MSKC32rr GR32:$src)>; + def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), + (T1MSKC64rr GR64:$src)>; + + def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), + (TZMSK32rr GR32:$src)>; + def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), + (TZMSK64rr GR64:$src)>; +} // HasTBM + +//===----------------------------------------------------------------------===// +// Memory Instructions +// + +let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in +def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), + "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD; + +let Predicates = [HasCLWB], SchedRW = [WriteLoad] in +def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", + [(int_x86_clwb addr:$src)]>, PD, NotMemoryFoldable; + +let Predicates = [HasCLDEMOTE], SchedRW = [WriteLoad] in +def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src", + [(int_x86_cldemote addr:$src)]>, TB; + +//===----------------------------------------------------------------------===// +// Subsystems. +//===----------------------------------------------------------------------===// + +include "X86Capstone.td" + +include "X86InstrArithmetic.td" +include "X86InstrCMovSetCC.td" +include "X86InstrExtension.td" +include "X86InstrControl.td" +include "X86InstrShiftRotate.td" + +// X87 Floating Point Stack. +include "X86InstrFPStack.td" + +// SIMD support (SSE, MMX and AVX) +include "X86InstrFragmentsSIMD.td" + +// FMA - Fused Multiply-Add support (requires FMA) +include "X86InstrFMA.td" + +// XOP +include "X86InstrXOP.td" + +// SSE, MMX and 3DNow! vector support. +include "X86InstrSSE.td" +include "X86InstrAVX512.td" +include "X86InstrMMX.td" +include "X86Instr3DNow.td" + +// MPX instructions +include "X86InstrMPX.td" + +include "X86InstrVMX.td" +include "X86InstrSVM.td" + +include "X86InstrTSX.td" +include "X86InstrSGX.td" + +// System instructions. +include "X86InstrSystem.td" + +// Compiler Pseudo Instructions and Pat Patterns +//include "X86InstrCompiler.td" +//include "X86InstrVecCompiler.td" + +//===----------------------------------------------------------------------===// +// Assembler Mnemonic Aliases +//===----------------------------------------------------------------------===// + +def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; + +def : MnemonicAlias<"cbw", "cbtw", "att">; +def : MnemonicAlias<"cwde", "cwtl", "att">; +def : MnemonicAlias<"cwd", "cwtd", "att">; +def : MnemonicAlias<"cdq", "cltd", "att">; +def : MnemonicAlias<"cdqe", "cltq", "att">; +def : MnemonicAlias<"cqo", "cqto", "att">; + +// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. +def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; + +def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; +def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; + +def : MnemonicAlias<"loopz", "loope">; +def : MnemonicAlias<"loopnz", "loopne">; + +def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"popf", "popfq", "intel">, Requires<[In64BitMode]>; +def : MnemonicAlias<"popfd", "popfl", "att">; + +// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in +// all modes. However: "push (addr)" and "push $42" should default to +// pushl/pushq depending on the current mode. Similar for "pop %bx" +def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"pushf", "pushfq", "intel">, Requires<[In64BitMode]>; +def : MnemonicAlias<"pushfd", "pushfl", "att">; + +def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; +def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; +def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; +def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; + +def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; + +def : MnemonicAlias<"repe", "rep">; +def : MnemonicAlias<"repz", "rep">; +def : MnemonicAlias<"repnz", "repne">; + +def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; + +// Apply 'ret' behavior to 'retn' +def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"retn", "ret", "intel">; + +def : MnemonicAlias<"sal", "shl", "intel">; +def : MnemonicAlias<"salb", "shlb", "att">; +def : MnemonicAlias<"salw", "shlw", "att">; +def : MnemonicAlias<"sall", "shll", "att">; +def : MnemonicAlias<"salq", "shlq", "att">; + +def : MnemonicAlias<"smovb", "movsb", "att">; +def : MnemonicAlias<"smovw", "movsw", "att">; +def : MnemonicAlias<"smovl", "movsl", "att">; +def : MnemonicAlias<"smovq", "movsq", "att">; + +def : MnemonicAlias<"ud2a", "ud2", "att">; +def : MnemonicAlias<"verrw", "verr", "att">; + +// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release' +def : MnemonicAlias<"acquire", "xacquire", "intel">; +def : MnemonicAlias<"release", "xrelease", "intel">; + +// System instruction aliases. +def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; +def : MnemonicAlias<"sysret", "sysretl", "att">; +def : MnemonicAlias<"sysexit", "sysexitl", "att">; + +def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; +//def : MnemonicAlias<"lgdt", "lgdtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"lgdt", "lgdtd", "intel">, Requires<[In32BitMode]>; +//def : MnemonicAlias<"lidt", "lidtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"lidt", "lidtd", "intel">, Requires<[In32BitMode]>; +//def : MnemonicAlias<"sgdt", "sgdtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"sgdt", "sgdtd", "intel">, Requires<[In32BitMode]>; +//def : MnemonicAlias<"sidt", "sidtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"sidt", "sidtd", "intel">, Requires<[In32BitMode]>; + + +// Floating point stack aliases. +def : MnemonicAlias<"fcmovz", "fcmove", "att">; +def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; +def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; +def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; +def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; +def : MnemonicAlias<"fcomip", "fcompi">; +def : MnemonicAlias<"fildq", "fildll", "att">; +def : MnemonicAlias<"fistpq", "fistpll", "att">; +def : MnemonicAlias<"fisttpq", "fisttpll", "att">; +def : MnemonicAlias<"fldcww", "fldcw", "att">; +def : MnemonicAlias<"fnstcww", "fnstcw", "att">; +def : MnemonicAlias<"fnstsww", "fnstsw", "att">; +def : MnemonicAlias<"fucomip", "fucompi">; +def : MnemonicAlias<"fwait", "wait">; + +def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; +def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; +def : MnemonicAlias<"xsaveq", "xsave64", "att">; +def : MnemonicAlias<"xrstorq", "xrstor64", "att">; +def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; +def : MnemonicAlias<"xrstorsq", "xrstors64", "att">; +def : MnemonicAlias<"xsavecq", "xsavec64", "att">; +def : MnemonicAlias<"xsavesq", "xsaves64", "att">; + +class CondCodeAlias + : MnemonicAlias; + +/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of +/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for +/// example "setz" -> "sete". +multiclass IntegerCondCodeMnemonicAlias { + def C : CondCodeAlias; // setc -> setb + def Z : CondCodeAlias; // setz -> sete + def NA : CondCodeAlias; // setna -> setbe + def NB : CondCodeAlias; // setnb -> setae + def NC : CondCodeAlias; // setnc -> setae + def NG : CondCodeAlias; // setng -> setle + def NL : CondCodeAlias; // setnl -> setge + def NZ : CondCodeAlias; // setnz -> setne + def PE : CondCodeAlias; // setpe -> setp + def PO : CondCodeAlias; // setpo -> setnp + + def NAE : CondCodeAlias; // setnae -> setb + def NBE : CondCodeAlias; // setnbe -> seta + def NGE : CondCodeAlias; // setnge -> setl + def NLE : CondCodeAlias; // setnle -> setg +} + +// Aliases for set +defm : IntegerCondCodeMnemonicAlias<"set", "">; +// Aliases for j +defm : IntegerCondCodeMnemonicAlias<"j", "">; +// Aliases for cmov{w,l,q} +defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; +defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; +defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; +// No size suffix for intel-style asm. +defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; + + +//===----------------------------------------------------------------------===// +// Assembler Instruction Aliases +//===----------------------------------------------------------------------===// + +// aad/aam default to base 10 if no operand is specified. +def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>; +def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>; + +// Disambiguate the mem/imm form of bt-without-a-suffix as btl. +// Likewise for btc/btr/bts. +def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}", + (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; +def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}", + (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; +def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}", + (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; +def : InstAlias<"bts\t{$imm, $mem|$mem, $imm}", + (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; + +// clr aliases. +def : InstAlias<"clr{b}\t$reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; +def : InstAlias<"clr{w}\t$reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; +def : InstAlias<"clr{l}\t$reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; +def : InstAlias<"clr{q}\t$reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; + +// lods aliases. Accept the destination being omitted because it's implicit +// in the mnemonic, or the mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"lodsb\t$src", (LODSB srcidx8:$src), 0>; +def : InstAlias<"lodsw\t$src", (LODSW srcidx16:$src), 0>; +def : InstAlias<"lods{l|d}\t$src", (LODSL srcidx32:$src), 0>; +def : InstAlias<"lodsq\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; +def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; +def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; +def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; +def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; +def : InstAlias<"lods\t$src", (LODSB srcidx8:$src), 0, "intel">; +def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0, "intel">; +def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0, "intel">; +def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; + + +// stos aliases. Accept the source being omitted because it's implicit in +// the mnemonic, or the mnemonic suffix being omitted because it's implicit +// in the source. +def : InstAlias<"stosb\t$dst", (STOSB dstidx8:$dst), 0>; +def : InstAlias<"stosw\t$dst", (STOSW dstidx16:$dst), 0>; +def : InstAlias<"stos{l|d}\t$dst", (STOSL dstidx32:$dst), 0>; +def : InstAlias<"stosq\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; +def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; +def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; +def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst), 0, "intel">; +def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0, "intel">; +def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0, "intel">; +def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; + + +// scas aliases. Accept the destination being omitted because it's implicit +// in the mnemonic, or the mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"scasb\t$dst", (SCASB dstidx8:$dst), 0>; +def : InstAlias<"scasw\t$dst", (SCASW dstidx16:$dst), 0>; +def : InstAlias<"scas{l|d}\t$dst", (SCASL dstidx32:$dst), 0>; +def : InstAlias<"scasq\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; +def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; +def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; +def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst), 0, "intel">; +def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0, "intel">; +def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0, "intel">; +def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; + +// cmps aliases. Mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0, "intel">; +def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0, "intel">; +def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0, "intel">; +def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; + +// movs aliases. Mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0, "intel">; +def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0, "intel">; +def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0, "intel">; +def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; + +// div and idiv aliases for explicit A register. +def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; +def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; +def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; +def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; +def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; +def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; +def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; +def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; +def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; +def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; +def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; +def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; +def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; +def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; +def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; +def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; + + + +// Various unary fpstack operations default to operating on ST1. +// For example, "fxch" -> "fxch %st(1)" +def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; +def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; +def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; +def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; +def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; +def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; +def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; +def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; +def : InstAlias<"fxch", (XCH_F ST1), 0>; +def : InstAlias<"fcom", (COM_FST0r ST1), 0>; +def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; +def : InstAlias<"fcomi", (COM_FIr ST1), 0>; +def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; +def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; +def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; +def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; +def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; + +// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. +// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate +// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with +// gas. +multiclass FpUnaryAlias { + def : InstAlias; + def : InstAlias; +} + +defm : FpUnaryAlias<"fadd", ADD_FST0r>; +defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; +defm : FpUnaryAlias<"fsub", SUB_FST0r>; +defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; +defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; +defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; +defm : FpUnaryAlias<"fmul", MUL_FST0r>; +defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; +defm : FpUnaryAlias<"fdiv", DIV_FST0r>; +defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; +defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; +defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; +defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; +defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; +defm : FpUnaryAlias<"fcompi", COM_FIPr>; +defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; + + +// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they +// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, +// solely because gas supports it. +def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; +def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; +def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; +def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; +def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; +def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; + +def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; + +// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but +// this is compatible with what GAS does. +def : InstAlias<"lcall\t$seg : $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; +def : InstAlias<"ljmp\t$seg : $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; +def : InstAlias<"lcall\t{*}$dst", (FARCALL32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; +def : InstAlias<"ljmp\t{*}$dst", (FARJMP32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; +def : InstAlias<"lcall\t$seg : $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; +def : InstAlias<"ljmp\t$seg : $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; +def : InstAlias<"lcall\t{*}$dst", (FARCALL16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; +def : InstAlias<"ljmp\t{*}$dst", (FARJMP16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; + +def : InstAlias<"jmp\t{*}$dst", (JMP64m i64mem:$dst), 0, "att">, Requires<[In64BitMode]>; +def : InstAlias<"jmp\t{*}$dst", (JMP32m i32mem:$dst), 0, "att">, Requires<[In32BitMode]>; +def : InstAlias<"jmp\t{*}$dst", (JMP16m i16mem:$dst), 0, "att">, Requires<[In16BitMode]>; + + +// "imul , B" is an alias for "imul , B, B". +def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; +def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; +def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; +def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; +def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; +def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; + +// ins aliases. Accept the mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0, "intel">; +def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0, "intel">; +def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0, "intel">; + +// outs aliases. Accept the mnemonic suffix being omitted because it's implicit +// in the source. +def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0, "intel">; +def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0, "intel">; +def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0, "intel">; + +// inb %dx -> inb %al, %dx +def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; +def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; +def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; +def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>; +def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>; +def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>; + + +// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp +def : InstAlias<"call\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; +def : InstAlias<"jmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; +def : InstAlias<"call\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; +def : InstAlias<"jmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; +def : InstAlias<"callw\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; +def : InstAlias<"jmpw\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; +def : InstAlias<"calll\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; +def : InstAlias<"jmpl\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; + +// Match 'movq , ' as an alias for movabsq. +def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; + +// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, +// which supports this due to an old AMD documentation bug when 64-bit mode was +// created. +def : InstAlias<"movd\t{$src, $dst|$dst, $src}", + (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; +def : InstAlias<"movd\t{$src, $dst|$dst, $src}", + (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; + +// movsx aliases +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0, "att">; +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0, "att">; +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0, "att">; +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0, "att">; +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0, "att">; +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0, "att">; +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0, "att">; + +// movzx aliases +def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0, "att">; +def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0, "att">; +def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0, "att">; +def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0, "att">; +def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr8 GR64:$dst, GR8:$src), 0, "att">; +def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr16 GR64:$dst, GR16:$src), 0, "att">; +// Note: No GR32->GR64 movzx form. + +// outb %dx -> outb %al, %dx +def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; +def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; +def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; +def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>; +def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>; +def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>; + +// 'sldt ' can be encoded with either sldtw or sldtq with the same +// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity +// errors, since its encoding is the most compact. +def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; + +// shld/shrd op,op -> shld op, op, CL +def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; +def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; +def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; +def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; +def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; +def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; + +def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; +def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; +def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; +def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; +def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; +def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; + +/* FIXME: This is disabled because the asm matcher is currently incapable of + * matching a fixed immediate like $1. +// "shl X, $1" is an alias for "shl X". +multiclass ShiftRotateByOneAlias { + def : InstAlias(!strconcat(Opc, "8r1")) GR8:$op)>; + def : InstAlias(!strconcat(Opc, "16r1")) GR16:$op)>; + def : InstAlias(!strconcat(Opc, "32r1")) GR32:$op)>; + def : InstAlias(!strconcat(Opc, "64r1")) GR64:$op)>; + def : InstAlias(!strconcat(Opc, "8m1")) i8mem:$op)>; + def : InstAlias(!strconcat(Opc, "16m1")) i16mem:$op)>; + def : InstAlias(!strconcat(Opc, "32m1")) i32mem:$op)>; + def : InstAlias(!strconcat(Opc, "64m1")) i64mem:$op)>; +} + +defm : ShiftRotateByOneAlias<"rcl", "RCL">; +defm : ShiftRotateByOneAlias<"rcr", "RCR">; +defm : ShiftRotateByOneAlias<"rol", "ROL">; +defm : ShiftRotateByOneAlias<"ror", "ROR">; +FIXME */ + +// test: We accept "testX , " and "testX , " as synonyms. +def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}", + (TEST8mr i8mem :$mem, GR8 :$val), 0>; +def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}", + (TEST16mr i16mem:$mem, GR16:$val), 0>; +def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}", + (TEST32mr i32mem:$mem, GR32:$val), 0>; +def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}", + (TEST64mr i64mem:$mem, GR64:$val), 0>; + +// xchg: We accept "xchgX , " and "xchgX , " as synonyms. +def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", + (XCHG8rm GR8 :$val, i8mem :$mem), 0>; +def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", + (XCHG16rm GR16:$val, i16mem:$mem), 0>; +def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", + (XCHG32rm GR32:$val, i32mem:$mem), 0>; +def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", + (XCHG64rm GR64:$val, i64mem:$mem), 0>; + +// xchg: We accept "xchgX , %eax" and "xchgX %eax, " as synonyms. +def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; +def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src), 0>; +def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; + +// In 64-bit mode, xchg %eax, %eax can't be encoded with the 0x90 opcode we +// would get by default because it's defined as NOP. But xchg %eax, %eax implies +// implicit zeroing of the upper 32 bits. So alias to the longer encoding. +def : InstAlias<"xchg{l}\t{%eax, %eax|eax, eax}", + (XCHG32rr EAX, EAX), 0>, Requires<[In64BitMode]>; + +// xchg %rax, %rax is a nop in x86-64 and can be encoded as such. Without this +// we emit an unneeded REX.w prefix. +def : InstAlias<"xchg{q}\t{%rax, %rax|rax, rax}", (NOOP), 0>; + +// These aliases exist to get the parser to prioritize matching 8-bit +// immediate encodings over matching the implicit ax/eax/rax encodings. By +// explicitly mentioning the A register here, these entries will be ordered +// first due to the more explicit immediate type. +def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>; + +def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>; + +def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrInfo_reduce.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrInfo_reduce.td new file mode 100644 index 0000000..9aa8425 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrInfo_reduce.td @@ -0,0 +1,3572 @@ +//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 instruction set, defining the instructions, and +// properties of the instructions which are needed for code generation, machine +// code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// X86 specific DAG Nodes. +// + +def SDTIntShiftDOp: SDTypeProfile<1, 3, + [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, + SDTCisInt<0>, SDTCisInt<3>]>; + +def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; + +def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; +//def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; + +def SDTX86Cmov : SDTypeProfile<1, 4, + [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, + SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; + +// Unary and binary operator instructions that set EFLAGS as a side-effect. +def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, + [SDTCisSameAs<0, 2>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; + +def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, + [SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; + +// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS +def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, + [SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, + SDTCisVT<1, i32>, + SDTCisVT<4, i32>]>; +// RES1, RES2, FLAGS = op LHS, RHS +def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, + [SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; +def SDTX86BrCond : SDTypeProfile<0, 3, + [SDTCisVT<0, OtherVT>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; + +def SDTX86SetCC : SDTypeProfile<1, 2, + [SDTCisVT<0, i8>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; +def SDTX86SetCC_C : SDTypeProfile<1, 2, + [SDTCisInt<0>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; + +def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; + +def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; + +def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, + SDTCisVT<2, i8>]>; +def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; +def SDTX86caspairSaveEbx8 : SDTypeProfile<1, 3, + [SDTCisVT<0, i32>, SDTCisPtrTy<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; +def SDTX86caspairSaveRbx16 : SDTypeProfile<1, 3, + [SDTCisVT<0, i64>, SDTCisPtrTy<1>, + SDTCisVT<2, i64>, SDTCisVT<3, i64>]>; + +def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, + SDTCisPtrTy<1>, + SDTCisInt<2>]>; + +def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, + SDTCisPtrTy<1>]>; + +def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; + +def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; +def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; + +def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, + SDTCisVT<1, iPTR>, + SDTCisVT<2, iPTR>]>; + +def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, + SDTCisPtrTy<1>, + SDTCisVT<2, i32>, + SDTCisVT<3, i8>, + SDTCisVT<4, i32>]>; + +def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; + +def SDTX86Void : SDTypeProfile<0, 0, []>; + +def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; + +def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86WIN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; + +def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; + +def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; + +def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, + [SDNPHasChain,SDNPSideEffect]>; +def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, + [SDNPHasChain]>; + + +def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; +def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; +def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; +def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; + +def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; +def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; + +def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; +def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, + [SDNPHasChain]>; +def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; +def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; + +def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; + +def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, + [SDNPHasChain, SDNPSideEffect]>; + +def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, + [SDNPHasChain, SDNPSideEffect]>; + +def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas8save_ebx : SDNode<"X86ISD::LCMPXCHG8_SAVE_EBX_DAG", + SDTX86caspairSaveEbx8, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, + SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; +def X86cas16save_rbx : SDNode<"X86ISD::LCMPXCHG16_SAVE_RBX_DAG", + SDTX86caspairSaveRbx16, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, + SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; + +def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; +def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, + [SDNPHasChain, SDNPOptInGlue]>; + +def X86vastart_save_xmm_regs : + SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", + SDT_X86VASTART_SAVE_XMM_REGS, + [SDNPHasChain, SDNPVariadic]>; +def X86vaarg64 : + SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, + SDNPMemOperand]>; +def X86callseq_start : + SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, + [SDNPHasChain, SDNPOutGlue]>; +def X86callseq_end : + SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, + SDNPVariadic]>; + +def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, + SDNPVariadic]>; +def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind, + [SDNPHasChain]>; + +def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; +def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad]>; + +def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; +def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; +def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; + +def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; +def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; + +def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", + SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, + SDTCisInt<1>]>>; + +def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, + [SDNPHasChain]>; + +def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", + SDTypeProfile<1, 1, [SDTCisInt<0>, + SDTCisPtrTy<1>]>, + [SDNPHasChain, SDNPSideEffect]>; +def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", + SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, + [SDNPHasChain, SDNPSideEffect]>; +def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH", + SDTypeProfile<0, 0, []>, + [SDNPHasChain, SDNPSideEffect]>; + +def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; + +def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; +def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, + [SDNPCommutative]>; +def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; +def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; + +def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; +def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; +def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, + [SDNPCommutative]>; + +def X86lock_add : SDNode<"X86ISD::LADD", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_sub : SDNode<"X86ISD::LSUB", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_or : SDNode<"X86ISD::LOR", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; + +def X86lock_inc : SDNode<"X86ISD::LINC", SDTLockUnaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_dec : SDNode<"X86ISD::LDEC", SDTLockUnaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; + +def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; + +def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; + +def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDT_X86WIN_ALLOCA, + [SDNPHasChain, SDNPOutGlue]>; + +def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, + [SDNPHasChain]>; + +def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86lwpins : SDNode<"X86ISD::LWPINS", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; + +def X86umwait : SDNode<"X86ISD::UMWAIT", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +def X86tpause : SDNode<"X86ISD::TPAUSE", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +//===----------------------------------------------------------------------===// +// X86 Operand Definitions. +// + +// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for +// the index operand of an address, to conform to x86 encoding restrictions. +def ptr_rc_nosp : PointerLikeRegClass<1>; + +// *mem - Operand definitions for the funky X86 addressing mode operands. +// +def X86MemAsmOperand : AsmOperandClass { + let Name = "Mem"; +} +let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in { + def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } + def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } + def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } + def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } + def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } + def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } + def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } + def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } + // Gather mem operands + def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; } + def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; } + def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; } + def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; } + def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; } + + def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; } + def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; } + def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; } + def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; } + def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; } + def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; } + def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; } + def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; } +} + +def X86AbsMemAsmOperand : AsmOperandClass { + let Name = "AbsMem"; + let SuperClasses = [X86MemAsmOperand]; +} + +class X86MemOperand : Operand { + let PrintMethod = printMethod; + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); + let ParserMatchClass = parserMatchClass; + let OperandType = "OPERAND_MEMORY"; +} + +// Gather mem operands +class X86VMemOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG); +} + +def anymem : X86MemOperand<"printanymem">; + +// FIXME: Right now we allow any size during parsing, but we might want to +// restrict to only unsized memory. +def opaquemem : X86MemOperand<"printopaquemem">; + +def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>; +def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>; +def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>; +def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>; +def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>; +def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>; +def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>; +def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>; +def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>; +def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>; +def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>; +def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>; +def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>; + +def v512mem : X86VMemOperand; + +// Gather mem operands +def vx64mem : X86VMemOperand; +def vx128mem : X86VMemOperand; +def vx256mem : X86VMemOperand; +def vy128mem : X86VMemOperand; +def vy256mem : X86VMemOperand; + +def vx64xmem : X86VMemOperand; +def vx128xmem : X86VMemOperand; +def vx256xmem : X86VMemOperand; +def vy128xmem : X86VMemOperand; +def vy256xmem : X86VMemOperand; +def vy512xmem : X86VMemOperand; +def vz256mem : X86VMemOperand; +def vz512mem : X86VMemOperand; + +// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead +// of a plain GPR, so that it doesn't potentially require a REX prefix. +def ptr_rc_norex : PointerLikeRegClass<2>; +def ptr_rc_norex_nosp : PointerLikeRegClass<3>; + +def i8mem_NOREX : Operand { + let PrintMethod = "printi8mem"; + let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, + SEGMENT_REG); + let ParserMatchClass = X86Mem8AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +// GPRs available for tailcall. +// It represents GR32_TC, GR64_TC or GR64_TCW64. +def ptr_rc_tailcall : PointerLikeRegClass<4>; + +// Special i32mem for addresses of load folding tail calls. These are not +// allowed to use callee-saved registers since they must be scheduled +// after callee-saved register are popped. +def i32mem_TC : Operand { + let PrintMethod = "printi32mem"; + let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, + i32imm, SEGMENT_REG); + let ParserMatchClass = X86Mem32AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +// Special i64mem for addresses of load folding tail calls. These are not +// allowed to use callee-saved registers since they must be scheduled +// after callee-saved register are popped. +def i64mem_TC : Operand { + let PrintMethod = "printi64mem"; + let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, + ptr_rc_tailcall, i32imm, SEGMENT_REG); + let ParserMatchClass = X86Mem64AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + +let OperandType = "OPERAND_PCREL", + ParserMatchClass = X86AbsMemAsmOperand, + PrintMethod = "printPCRelImm" in { +def i32imm_pcrel : Operand; +def i16imm_pcrel : Operand; + +// Branch targets have OtherVT type and print as pc-relative values. +def brtarget : Operand; +def brtarget8 : Operand; + +} + +// Special parser to detect 16-bit mode to select 16-bit displacement. +def X86AbsMem16AsmOperand : AsmOperandClass { + let Name = "AbsMem16"; + let RenderMethod = "addAbsMemOperands"; + let SuperClasses = [X86AbsMemAsmOperand]; +} + +// Branch targets have OtherVT type and print as pc-relative values. +let OperandType = "OPERAND_PCREL", + PrintMethod = "printPCRelImm" in { +let ParserMatchClass = X86AbsMem16AsmOperand in + def brtarget16 : Operand; +let ParserMatchClass = X86AbsMemAsmOperand in + def brtarget32 : Operand; +} + +let RenderMethod = "addSrcIdxOperands" in { + def X86SrcIdx8Operand : AsmOperandClass { + let Name = "SrcIdx8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86SrcIdx16Operand : AsmOperandClass { + let Name = "SrcIdx16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86SrcIdx32Operand : AsmOperandClass { + let Name = "SrcIdx32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86SrcIdx64Operand : AsmOperandClass { + let Name = "SrcIdx64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addSrcIdxOperands" + +let RenderMethod = "addDstIdxOperands" in { + def X86DstIdx8Operand : AsmOperandClass { + let Name = "DstIdx8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86DstIdx16Operand : AsmOperandClass { + let Name = "DstIdx16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86DstIdx32Operand : AsmOperandClass { + let Name = "DstIdx32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86DstIdx64Operand : AsmOperandClass { + let Name = "DstIdx64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addDstIdxOperands" + +let RenderMethod = "addMemOffsOperands" in { + def X86MemOffs16_8AsmOperand : AsmOperandClass { + let Name = "MemOffs16_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs16_16AsmOperand : AsmOperandClass { + let Name = "MemOffs16_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs16_32AsmOperand : AsmOperandClass { + let Name = "MemOffs16_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs32_8AsmOperand : AsmOperandClass { + let Name = "MemOffs32_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs32_16AsmOperand : AsmOperandClass { + let Name = "MemOffs32_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs32_32AsmOperand : AsmOperandClass { + let Name = "MemOffs32_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs32_64AsmOperand : AsmOperandClass { + let Name = "MemOffs32_64"; + let SuperClasses = [X86Mem64AsmOperand]; + } + def X86MemOffs64_8AsmOperand : AsmOperandClass { + let Name = "MemOffs64_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs64_16AsmOperand : AsmOperandClass { + let Name = "MemOffs64_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs64_32AsmOperand : AsmOperandClass { + let Name = "MemOffs64_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs64_64AsmOperand : AsmOperandClass { + let Name = "MemOffs64_64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addMemOffsOperands" + +class X86SrcIdxOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc, SEGMENT_REG); +} + +class X86DstIdxOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc); +} + +def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; +def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; +def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; +def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; +def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; +def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; +def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; +def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; + +class X86MemOffsOperand + : X86MemOperand { + let MIOperandInfo = (ops immOperand, SEGMENT_REG); +} + +def offset16_8 : X86MemOffsOperand; +def offset16_16 : X86MemOffsOperand; +def offset16_32 : X86MemOffsOperand; +def offset32_8 : X86MemOffsOperand; +def offset32_16 : X86MemOffsOperand; +def offset32_32 : X86MemOffsOperand; +def offset32_64 : X86MemOffsOperand; +def offset64_8 : X86MemOffsOperand; +def offset64_16 : X86MemOffsOperand; +def offset64_32 : X86MemOffsOperand; +def offset64_64 : X86MemOffsOperand; + +def SSECC : Operand { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def AVXCC : Operand { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def AVX512ICC : Operand { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def XOPCC : Operand { + let PrintMethod = "printXOPCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +class ImmSExtAsmOperandClass : AsmOperandClass { + let SuperClasses = [ImmAsmOperand]; + let RenderMethod = "addImmOperands"; +} + +def X86GR32orGR64AsmOperand : AsmOperandClass { + let Name = "GR32orGR64"; +} + +def GR32orGR64 : RegisterOperand { + let ParserMatchClass = X86GR32orGR64AsmOperand; +} +def AVX512RCOperand : AsmOperandClass { + let Name = "AVX512RC"; +} +def AVX512RC : Operand { + let PrintMethod = "printRoundingControl"; + let OperandType = "OPERAND_IMMEDIATE"; + let ParserMatchClass = AVX512RCOperand; +} + +// Sign-extended immediate classes. We don't need to define the full lattice +// here because there is no instruction with an ambiguity between ImmSExti64i32 +// and ImmSExti32i8. +// +// The strange ranges come from the fact that the assembler always works with +// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" +// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). + +// [0, 0x7FFFFFFF] | +// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] +def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti64i32"; +} + +// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti16i8"; + let SuperClasses = [ImmSExti64i32AsmOperand]; +} + +// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti32i8"; +} + +// [0, 0x0000007F] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti64i8"; + let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, + ImmSExti64i32AsmOperand]; +} + +// Unsigned immediate used by SSE/AVX instructions +// [0, 0xFF] +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmUnsignedi8AsmOperand : AsmOperandClass { + let Name = "ImmUnsignedi8"; + let RenderMethod = "addImmOperands"; +} + +// A couple of more descriptive operand definitions. +// 16-bits but only 8 bits are significant. +def i16i8imm : Operand { + let ParserMatchClass = ImmSExti16i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} +// 32-bits but only 8 bits are significant. +def i32i8imm : Operand { + let ParserMatchClass = ImmSExti32i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 32 bits are significant. +def i64i32imm : Operand { + let ParserMatchClass = ImmSExti64i32AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 8 bits are significant. +def i64i8imm : Operand { + let ParserMatchClass = ImmSExti64i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// Unsigned 8-bit immediate used by SSE/AVX instructions. +def u8imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 32-bit immediate but only 8-bits are significant and they are unsigned. +// Used by some SSE/AVX instructions that use intrinsics. +def i32u8imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 32 bits are significant, and those bits are treated as being +// pc relative. +def i64i32imm_pcrel : Operand { + let PrintMethod = "printPCRelImm"; + let ParserMatchClass = X86AbsMemAsmOperand; + let OperandType = "OPERAND_PCREL"; +} + +def lea64_32mem : Operand { + let PrintMethod = "printanymem"; + let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); + let ParserMatchClass = X86MemAsmOperand; +} + +// Memory operands that use 64-bit pointers in both ILP32 and LP64. +def lea64mem : Operand { + let PrintMethod = "printanymem"; + let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); + let ParserMatchClass = X86MemAsmOperand; +} + + +//===----------------------------------------------------------------------===// +// X86 Complex Pattern Definitions. +// + +// Define X86-specific addressing mode. +def addr : ComplexPattern; +def lea32addr : ComplexPattern; +// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. +def lea64_32addr : ComplexPattern; + +def tls32addr : ComplexPattern; + +def tls32baseaddr : ComplexPattern; + +def lea64addr : ComplexPattern; + +def tls64addr : ComplexPattern; + +def tls64baseaddr : ComplexPattern; + +def vectoraddr : ComplexPattern; + +// A relocatable immediate is either an immediate operand or an operand that can +// be relocated by the linker to an immediate, such as a regular symbol in +// non-PIC code. +def relocImm : ComplexPattern; + +//===----------------------------------------------------------------------===// +// X86 Instruction Predicate Definitions. +def TruePredicate : Predicate<"true">; + +def HasCMov : Predicate<"Subtarget->hasCMov()">; +def NoCMov : Predicate<"!Subtarget->hasCMov()">; + +def HasMMX : Predicate<"Subtarget->hasMMX()">; +def Has3DNow : Predicate<"Subtarget->has3DNow()">; +def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; +def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; +def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; +def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; +def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; +def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; +def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; +def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; +def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; +def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; +def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; +def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; +def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; +def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; +def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; +def NoAVX : Predicate<"!Subtarget->hasAVX()">; +def HasAVX : Predicate<"Subtarget->hasAVX()">; +def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; +def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; +def HasAVX512 : Predicate<"Subtarget->hasAVX512()">; +def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; +def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; +def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; +def HasCDI : Predicate<"Subtarget->hasCDI()">; +def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">; +def HasPFI : Predicate<"Subtarget->hasPFI()">; +def HasERI : Predicate<"Subtarget->hasERI()">; +def HasDQI : Predicate<"Subtarget->hasDQI()">; +def NoDQI : Predicate<"!Subtarget->hasDQI()">; +def HasBWI : Predicate<"Subtarget->hasBWI()">; +def NoBWI : Predicate<"!Subtarget->hasBWI()">; +def HasVLX : Predicate<"Subtarget->hasVLX()">; +def NoVLX : Predicate<"!Subtarget->hasVLX()">; +def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">; +def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">; +def PKU : Predicate<"Subtarget->hasPKU()">; +def HasVNNI : Predicate<"Subtarget->hasVNNI()">; + +def HasBITALG : Predicate<"Subtarget->hasBITALG()">; +def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; +def HasAES : Predicate<"Subtarget->hasAES()">; +def HasVAES : Predicate<"Subtarget->hasVAES()">; +def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">; +def HasFXSR : Predicate<"Subtarget->hasFXSR()">; +def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">; +def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">; +def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">; +def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">; +def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; +def NoVLX_Or_NoVPCLMULQDQ : + Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()">; +def HasVPCLMULQDQ : Predicate<"Subtarget->hasVPCLMULQDQ()">; +def HasGFNI : Predicate<"Subtarget->hasGFNI()">; +def HasFMA : Predicate<"Subtarget->hasFMA()">; +def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; +def NoFMA4 : Predicate<"!Subtarget->hasFMA4()">; +def HasXOP : Predicate<"Subtarget->hasXOP()">; +def HasTBM : Predicate<"Subtarget->hasTBM()">; +def NoTBM : Predicate<"!Subtarget->hasTBM()">; +def HasLWP : Predicate<"Subtarget->hasLWP()">; +def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; +def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; +def HasF16C : Predicate<"Subtarget->hasF16C()">; +def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; +def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; +def HasBMI : Predicate<"Subtarget->hasBMI()">; +def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; +def NoBMI2 : Predicate<"!Subtarget->hasBMI2()">; +def HasVBMI : Predicate<"Subtarget->hasVBMI()">; +def HasVBMI2 : Predicate<"Subtarget->hasVBMI2()">; +def HasIFMA : Predicate<"Subtarget->hasIFMA()">; +def HasRTM : Predicate<"Subtarget->hasRTM()">; +def HasADX : Predicate<"Subtarget->hasADX()">; +def HasSHA : Predicate<"Subtarget->hasSHA()">; +def HasSGX : Predicate<"Subtarget->hasSGX()">; +def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; +def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; +def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">; +def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">; +def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; +def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">; +def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">; +def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">; +def HasCLZERO : Predicate<"Subtarget->hasCLZERO()">; +def HasCLDEMOTE : Predicate<"Subtarget->hasCLDEMOTE()">; +def HasMOVDIRI : Predicate<"Subtarget->hasMOVDIRI()">; +def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">; +def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">; +def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; +def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; +def HasMPX : Predicate<"Subtarget->hasMPX()">; +def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; +def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; +def HasCLWB : Predicate<"Subtarget->hasCLWB()">; +def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">; +def HasRDPID : Predicate<"Subtarget->hasRDPID()">; +def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">; +def HasINVPCID : Predicate<"Subtarget->hasINVPCID()">; +def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; +def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">; +def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, + AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; +def In64BitMode : Predicate<"Subtarget->is64Bit()">, + AssemblerPredicate<"Mode64Bit", "64-bit mode">; +def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; +def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; +def In16BitMode : Predicate<"Subtarget->is16Bit()">, + AssemblerPredicate<"Mode16Bit", "16-bit mode">; +def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, + AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; +def In32BitMode : Predicate<"Subtarget->is32Bit()">, + AssemblerPredicate<"Mode32Bit", "32-bit mode">; +def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; +def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; +def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||" + "Subtarget->getFrameLowering()->hasFP(*MF)"> { + let RecomputePerFunction = 1; +} +def IsPS4 : Predicate<"Subtarget->isTargetPS4()">; +def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">; +def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; +def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; +def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; +def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; +def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" + "TM.getCodeModel() == CodeModel::Kernel">; +def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; + +// We could compute these on a per-module basis but doing so requires accessing +// the Function object through the Subtarget and objections were raised +// to that (see post-commit review comments for r301750). +let RecomputePerFunction = 1 in { + def OptForSize : Predicate<"MF->getFunction().optForSize()">; + def OptForMinSize : Predicate<"MF->getFunction().optForMinSize()">; + def OptForSpeed : Predicate<"!MF->getFunction().optForSize()">; + def UseIncDec : Predicate<"!Subtarget->slowIncDec() || " + "MF->getFunction().optForSize()">; + def NoSSE41_Or_OptForSize : Predicate<"MF->getFunction().optForSize() || " + "!Subtarget->hasSSE41()">; +} + +def CallImmAddr : Predicate<"Subtarget->isLegalToCallImmediateAddr()">; +def FavorMemIndirectCall : Predicate<"!Subtarget->slowTwoMemOps()">; +def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; +def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">; +def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">; +def HasERMSB : Predicate<"Subtarget->hasERMSB()">; +def HasMFence : Predicate<"Subtarget->hasMFence()">; +def UseRetpoline : Predicate<"Subtarget->useRetpoline()">; +def NotUseRetpoline : Predicate<"!Subtarget->useRetpoline()">; + +//===----------------------------------------------------------------------===// +// X86 Instruction Format Definitions. +// + +include "X86InstrFormats.td" + +//===----------------------------------------------------------------------===// +// Pattern fragments. +// + +// X86 specific condition code. These correspond to CondCode in +// X86InstrInfo.h. They must be kept in synch. +def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE +def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC +def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C +def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA +def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z +def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE +def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL +def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE +def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG +def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ +def X86_COND_NO : PatLeaf<(i8 10)>; +def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO +def X86_COND_NS : PatLeaf<(i8 12)>; +def X86_COND_O : PatLeaf<(i8 13)>; +def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE +def X86_COND_S : PatLeaf<(i8 15)>; + +def i16immSExt8 : ImmLeaf(Imm); }]>; +def i32immSExt8 : ImmLeaf(Imm); }]>; +def i64immSExt8 : ImmLeaf(Imm); }]>; +def i64immSExt32 : ImmLeaf(Imm); }]>; + +// FIXME: Ideally we would just replace the above i*immSExt* matchers with +// relocImm-based matchers, but then FastISel would be unable to use them. +def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{ + return isSExtRelocImm<8>(N); +}]>; +def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{ + return isSExtRelocImm<32>(N); +}]>; + +// If we have multiple users of an immediate, it's much smaller to reuse +// the register, rather than encode the immediate in every instruction. +// This has the risk of increasing register pressure from stretched live +// ranges, however, the immediates should be trivial to rematerialize by +// the RA in the event of high register pressure. +// TODO : This is currently enabled for stores and binary ops. There are more +// cases for which this can be enabled, though this catches the bulk of the +// issues. +// TODO2 : This should really also be enabled under O2, but there's currently +// an issue with RA where we don't pull the constants into their users +// when we rematerialize them. I'll follow-up on enabling O2 after we fix that +// issue. +// TODO3 : This is currently limited to single basic blocks (DAG creation +// pulls block immediates to the top and merges them if necessary). +// Eventually, it would be nice to allow ConstantHoisting to merge constants +// globally for potentially added savings. +// +def imm8_su : PatLeaf<(i8 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def imm16_su : PatLeaf<(i16 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def imm32_su : PatLeaf<(i32 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64immSExt32_su : PatLeaf<(i64immSExt32), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i32immSExt8_su : PatLeaf<(i32immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64immSExt8_su : PatLeaf<(i64immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit +// unsigned field. +def i64immZExt32 : ImmLeaf(Imm); }]>; + +def i64immZExt32SExt8 : ImmLeaf(Imm) && isInt<8>(static_cast(Imm)); +}]>; + +// Helper fragments for loads. + +// It's safe to fold a zextload/extload from i1 as a regular i8 load. The +// upper bits are guaranteed to be zero and we were going to emit a MOV8rm +// which might get folded during peephole anyway. +def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD || + ExtType == ISD::ZEXTLOAD; +}]>; + +// It's always safe to treat a anyext i16 load as a i32 load if the i16 is +// known to be 32-bit aligned or better. Ditto for i8 to i16. +def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + if (ExtType == ISD::NON_EXTLOAD) + return true; + if (ExtType == ISD::EXTLOAD) + return LD->getAlignment() >= 2 && !LD->isVolatile(); + return false; +}]>; + +def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + if (ExtType == ISD::NON_EXTLOAD) + return true; + if (ExtType == ISD::EXTLOAD) + return LD->getAlignment() >= 4 && !LD->isVolatile(); + return false; +}]>; + +def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; +def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; +def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; +def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; +def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>; +def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ + LoadSDNode *Ld = cast(N); + return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); +}]>; +def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ + LoadSDNode *Ld = cast(N); + return Subtarget->hasSSEUnalignedMem() || + Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); +}]>; + +def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; +def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; +def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; +def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; +def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; +def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; + +def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; +def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; +def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; +def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; +def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; +def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; +def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; +def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; +def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; +def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; + +def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; +def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; +def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; +def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; +def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; +def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; +def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; +def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; +def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; +def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; + + +// An 'and' node with a single use. +def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ + return N->hasOneUse(); +}]>; +// An 'srl' node with a single use. +def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ + return N->hasOneUse(); +}]>; +// An 'trunc' node with a single use. +def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ + return N->hasOneUse(); +}]>; + +//===----------------------------------------------------------------------===// +// Instruction list. +// + +// Nop +let hasSideEffects = 0, SchedRW = [WriteNop] in { + def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; + def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; + def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; + def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero), + "nop{q}\t$zero", []>, TB, NotMemoryFoldable, + Requires<[In64BitMode]>; + // Also allow register so we can assemble/disassemble + def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; + def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; + def NOOPQr : RI<0x1f, MRMXr, (outs), (ins GR64:$zero), + "nop{q}\t$zero", []>, TB, NotMemoryFoldable, + Requires<[In64BitMode]>; + def NOOPW_19 : I<0x19, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOPL_19 : I<0x19, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + //def NOOPW_1a : I<0x1a, MRMXm, (outs), (ins i16mem:$zero), + // "nop{w}\t$zero", []>, TB, OpSize16; + //def NOOPL_1a : I<0x1a, MRMXm, (outs), (ins i32mem:$zero), + // "nop{l}\t$zero", []>, TB, OpSize32; + //def NOOPW_1b : I<0x1b, MRMXm, (outs), (ins i16mem:$zero), + // "nop{w}\t$zero", []>, TB, OpSize16; + //def NOOPL_1b : I<0x1b, MRMXm, (outs), (ins i32mem:$zero), + // "nop{l}\t$zero", []>, TB, OpSize32; + def NOOPW_1c : I<0x1c, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + //def NOOPL_1c : I<0x1c, MRMXm, (outs), (ins i32mem:$zero), + // "nop{l}\t$zero", []>, TB, OpSize32; + def NOOPW_1d : I<0x1d, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOPL_1d : I<0x1d, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + def NOOPW_1e : I<0x1e, MRMXm, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOPL_1e : I<0x1e, MRMXm, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m4 : I<0x18, MRM4m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m4 : I<0x18, MRM4m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r4 : I<0x18, MRM4r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r4 : I<0x18, MRM4r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m5 : I<0x18, MRM5m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m5 : I<0x18, MRM5m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r5 : I<0x18, MRM5r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r5 : I<0x18, MRM5r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m6 : I<0x18, MRM6m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m6 : I<0x18, MRM6m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r6 : I<0x18, MRM6r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r6 : I<0x18, MRM6r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16m7 : I<0x18, MRM7m, (outs), (ins i16mem:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_m7 : I<0x18, MRM7m, (outs), (ins i32mem:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; + + def NOOP18_16r7 : I<0x18, MRM7r, (outs), (ins GR16:$zero), + "nop{w}\t$zero", []>, TB, OpSize16; + def NOOP18_r7 : I<0x18, MRM7r, (outs), (ins GR32:$zero), + "nop{l}\t$zero", []>, TB, OpSize32; +} + + +// Constructing a stack frame. +def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), + "enter\t$len, $lvl", []>, Sched<[WriteMicrocoded]>; + +let SchedRW = [WriteALU] in { +let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in +def LEAVE : I<0xC9, RawFrm, (outs), (ins), "leave", []>, + Requires<[Not64BitMode]>; + +let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in +def LEAVE64 : I<0xC9, RawFrm, (outs), (ins), "leave", []>, + Requires<[In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Miscellaneous Instructions. +// + +let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1, + SchedRW = [WriteSystem] in + def Int_eh_sjlj_setup_dispatch + : PseudoI<(outs), (ins), [(X86eh_sjlj_setup_dispatch)]>; + +let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { +let mayLoad = 1, SchedRW = [WriteLoad] in { +def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, + OpSize16; +def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, + OpSize32, Requires<[Not64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, + OpSize16, NotMemoryFoldable; +def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, + OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 +} // mayLoad, SchedRW +let mayStore = 1, mayLoad = 1, SchedRW = [WriteRMW] in { +def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>, + OpSize16; +def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>, + OpSize32, Requires<[Not64BitMode]>; +} // mayStore, mayLoad, WriteRMW + +let mayStore = 1, SchedRW = [WriteStore] in { +def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, + OpSize16; +def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, + OpSize32, Requires<[Not64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, + OpSize16, NotMemoryFoldable; +def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, + OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 + +def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), + "push{w}\t$imm", []>, OpSize16; +def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), + "push{w}\t$imm", []>, OpSize16; + +def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), + "push{l}\t$imm", []>, OpSize32, + Requires<[Not64BitMode]>; +def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), + "push{l}\t$imm", []>, OpSize32, + Requires<[Not64BitMode]>; +} // mayStore, SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { +def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>, + OpSize16; +def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>, + OpSize32, Requires<[Not64BitMode]>; +} // mayLoad, mayStore, SchedRW + +} + +let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, + SchedRW = [WriteRMW], Defs = [ESP] in { + let Uses = [ESP] in + def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins), + [(set GR32:$dst, (int_x86_flags_read_u32))]>, + Requires<[Not64BitMode]>; + + let Uses = [RSP] in + def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins), + [(set GR64:$dst, (int_x86_flags_read_u64))]>, + Requires<[In64BitMode]>; +} + +let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, + SchedRW = [WriteRMW] in { + let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in + def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src), + [(int_x86_flags_write_u32 GR32:$src)]>, + Requires<[Not64BitMode]>; + + let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in + def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src), + [(int_x86_flags_write_u64 GR64:$src)]>, + Requires<[In64BitMode]>; +} + +let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0, + SchedRW = [WriteLoad] in { +def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize16; +def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, OpSize32, + Requires<[Not64BitMode]>; +} + +let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0, + SchedRW = [WriteStore] in { +def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize16; +def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, OpSize32, + Requires<[Not64BitMode]>; +} + +let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { +let mayLoad = 1, SchedRW = [WriteLoad] in { +def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 +} // mayLoad, SchedRW +let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in +def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>, + OpSize32, Requires<[In64BitMode]>; +let mayStore = 1, SchedRW = [WriteStore] in { +def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>; +// Long form for the disassembler. +let isCodeGenOnly = 1, ForceDisassemble = 1 in { +def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; +} // isCodeGenOnly = 1, ForceDisassemble = 1 +} // mayStore, SchedRW +let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { +def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>, + OpSize32, Requires<[In64BitMode]>; +} // mayLoad, mayStore, SchedRW +} + +let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, + SchedRW = [WriteStore] in { +def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), + "push{q}\t$imm", []>, OpSize32, + Requires<[In64BitMode]>; +def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), + "push{q}\t$imm", []>, OpSize32, + Requires<[In64BitMode]>; +} + +let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in +def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, + OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; +let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in +def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, + OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; + +let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], + mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { +def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", []>, + OpSize32, Requires<[Not64BitMode]>; +def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", []>, + OpSize16, Requires<[Not64BitMode]>; +} +let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], + mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { +def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", []>, + OpSize32, Requires<[Not64BitMode]>; +def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", []>, + OpSize16, Requires<[Not64BitMode]>; +} + +let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in { +// This instruction is a consequence of BSWAP32r observing operand size. The +// encoding is valid, but the behavior is undefined. +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in +def BSWAP16r_BAD : I<0xC8, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), + "bswap{w}\t$dst", []>, OpSize16, TB; +// GR32 = bswap GR32 +def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), + "bswap{l}\t$dst", + [(set GR32:$dst, (bswap GR32:$src))]>, OpSize32, TB; + +let SchedRW = [WriteBSWAP64] in +def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), + "bswap{q}\t$dst", + [(set GR64:$dst, (bswap GR64:$src))]>, TB; +} // Constraints = "$src = $dst", SchedRW + +// Bit scan instructions. +let Defs = [EFLAGS] in { +def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "bsf{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, + PS, OpSize16, Sched<[WriteBSF]>; +def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "bsf{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, + PS, OpSize16, Sched<[WriteBSFLd]>; +def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "bsf{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, + PS, OpSize32, Sched<[WriteBSF]>; +def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "bsf{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, + PS, OpSize32, Sched<[WriteBSFLd]>; +def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "bsf{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, + PS, Sched<[WriteBSF]>; +def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "bsf{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, + PS, Sched<[WriteBSFLd]>; + +def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "bsr{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, + PS, OpSize16, Sched<[WriteBSR]>; +def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "bsr{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, + PS, OpSize16, Sched<[WriteBSRLd]>; +def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "bsr{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, + PS, OpSize32, Sched<[WriteBSR]>; +def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "bsr{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, + PS, OpSize32, Sched<[WriteBSRLd]>; +def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "bsr{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, + PS, Sched<[WriteBSR]>; +def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "bsr{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, + PS, Sched<[WriteBSRLd]>; +} // Defs = [EFLAGS] + +let SchedRW = [WriteMicrocoded] in { +let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in { +def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), + "movsb\t{$src, $dst|$dst, $src}", []>; +def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), + "movsw\t{$src, $dst|$dst, $src}", []>, OpSize16; +def MOVSL : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), + "movs{l|d}\t{$src, $dst|$dst, $src}", []>, OpSize32; +def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), + "movsq\t{$src, $dst|$dst, $src}", []>, + Requires<[In64BitMode]>; +} + +let Defs = [EDI], Uses = [AL,EDI,DF] in +def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst), + "stosb\t{%al, $dst|$dst, al}", []>; +let Defs = [EDI], Uses = [AX,EDI,DF] in +def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst), + "stosw\t{%ax, $dst|$dst, ax}", []>, OpSize16; +let Defs = [EDI], Uses = [EAX,EDI,DF] in +def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst), + "stos{l|d}\t{%eax, $dst|$dst, eax}", []>, OpSize32; +let Defs = [RDI], Uses = [RAX,RDI,DF] in +def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst), + "stosq\t{%rax, $dst|$dst, rax}", []>, + Requires<[In64BitMode]>; + +let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in +def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), + "scasb\t{$dst, %al|al, $dst}", []>; +let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in +def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), + "scasw\t{$dst, %ax|ax, $dst}", []>, OpSize16; +let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in +def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), + "scas{l|d}\t{$dst, %eax|eax, $dst}", []>, OpSize32; +let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in +def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), + "scasq\t{$dst, %rax|rax, $dst}", []>, + Requires<[In64BitMode]>; + +let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in { +def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), + "cmpsb\t{$dst, $src|$src, $dst}", []>; +def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), + "cmpsw\t{$dst, $src|$src, $dst}", []>, OpSize16; +def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), + "cmps{l|d}\t{$dst, $src|$src, $dst}", []>, OpSize32; +def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), + "cmpsq\t{$dst, $src|$src, $dst}", []>, + Requires<[In64BitMode]>; +} +} // SchedRW + +//===----------------------------------------------------------------------===// +// Move Instructions. +// +let SchedRW = [WriteMove] in { +let hasSideEffects = 0, isMoveReg = 1 in { +def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>; +def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; +def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; +def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>; +} + +let isReMaterializable = 1, isAsCheapAsAMove = 1 in { +def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(set GR8:$dst, imm:$src)]>; +def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, imm:$src)]>, OpSize16; +def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, relocImm:$src)]>, OpSize32; +def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, i64immSExt32:$src)]>; +} +let isReMaterializable = 1 in { +def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), + "movabs{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, relocImm:$src)]>; +} + +// Longer forms that use a ModR/M byte. Needed for disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { +def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOV8ri">; +def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, + FoldGenData<"MOV16ri">; +def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, + FoldGenData<"MOV32ri">; +} +} // SchedRW + +let SchedRW = [WriteStore] in { +def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(store (i8 imm8_su:$src), addr:$dst)]>; +def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(store (i16 imm16_su:$src), addr:$dst)]>, OpSize16; +def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(store (i32 imm32_su:$src), addr:$dst)]>, OpSize32; +def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(store i64immSExt32_su:$src, addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW + +let hasSideEffects = 0 in { + +/// Memory offset versions of moves. The immediate is an address mode sized +/// offset from the segment base. +let SchedRW = [WriteALU] in { +let mayLoad = 1 in { +let Defs = [AL] in +def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), + "mov{b}\t{$src, %al|al, $src}", []>, + AdSize32; +let Defs = [AX] in +def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), + "mov{w}\t{$src, %ax|ax, $src}", []>, + OpSize16, AdSize32; +let Defs = [EAX] in +def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), + "mov{l}\t{$src, %eax|eax, $src}", []>, + OpSize32, AdSize32; +let Defs = [RAX] in +def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), + "mov{q}\t{$src, %rax|rax, $src}", []>, + AdSize32; + +let Defs = [AL] in +def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), + "mov{b}\t{$src, %al|al, $src}", []>, AdSize16; +let Defs = [AX] in +def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), + "mov{w}\t{$src, %ax|ax, $src}", []>, + OpSize16, AdSize16; +let Defs = [EAX] in +def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), + "mov{l}\t{$src, %eax|eax, $src}", []>, + AdSize16, OpSize32; +} // mayLoad +let mayStore = 1 in { +let Uses = [AL] in +def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst), + "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize32; +let Uses = [AX] in +def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_16:$dst), + "mov{w}\t{%ax, $dst|$dst, ax}", []>, + OpSize16, AdSize32; +let Uses = [EAX] in +def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_32:$dst), + "mov{l}\t{%eax, $dst|$dst, eax}", []>, + OpSize32, AdSize32; +let Uses = [RAX] in +def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs), (ins offset32_64:$dst), + "mov{q}\t{%rax, $dst|$dst, rax}", []>, + AdSize32; + +let Uses = [AL] in +def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs), (ins offset16_8:$dst), + "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize16; +let Uses = [AX] in +def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_16:$dst), + "mov{w}\t{%ax, $dst|$dst, ax}", []>, + OpSize16, AdSize16; +let Uses = [EAX] in +def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst), + "mov{l}\t{%eax, $dst|$dst, eax}", []>, + OpSize32, AdSize16; +} // mayStore + +// These forms all have full 64-bit absolute addresses in their instructions +// and use the movabs mnemonic to indicate this specific form. +let mayLoad = 1 in { +let Defs = [AL] in +def MOV8ao64 : Ii64<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), + "movabs{b}\t{$src, %al|al, $src}", []>, + AdSize64; +let Defs = [AX] in +def MOV16ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), + "movabs{w}\t{$src, %ax|ax, $src}", []>, + OpSize16, AdSize64; +let Defs = [EAX] in +def MOV32ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), + "movabs{l}\t{$src, %eax|eax, $src}", []>, + OpSize32, AdSize64; +let Defs = [RAX] in +def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), + "movabs{q}\t{$src, %rax|rax, $src}", []>, + AdSize64; +} // mayLoad + +let mayStore = 1 in { +let Uses = [AL] in +def MOV8o64a : Ii64<0xA2, RawFrmMemOffs, (outs), (ins offset64_8:$dst), + "movabs{b}\t{%al, $dst|$dst, al}", []>, + AdSize64; +let Uses = [AX] in +def MOV16o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_16:$dst), + "movabs{w}\t{%ax, $dst|$dst, ax}", []>, + OpSize16, AdSize64; +let Uses = [EAX] in +def MOV32o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_32:$dst), + "movabs{l}\t{%eax, $dst|$dst, eax}", []>, + OpSize32, AdSize64; +let Uses = [RAX] in +def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst), + "movabs{q}\t{%rax, $dst|$dst, rax}", []>, + AdSize64; +} // mayStore +} // SchedRW +} // hasSideEffects = 0 + +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, + SchedRW = [WriteMove], isMoveReg = 1 in { +def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOV8rr">; +def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, + FoldGenData<"MOV16rr">; +def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, + FoldGenData<"MOV32rr">; +def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOV64rr">; +} + +// Reversed version with ".s" suffix for GAS compatibility. +//def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}", +// (MOV8rr_REV GR8:$dst, GR8:$src), 0>; +//def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}", +// (MOV16rr_REV GR16:$dst, GR16:$src), 0>; +//def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}", +// (MOV32rr_REV GR32:$dst, GR32:$src), 0>; +//def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}", +// (MOV64rr_REV GR64:$dst, GR64:$src), 0>; +//def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">; +//def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">; +//def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">; +//def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", +// (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">; + +let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { +def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(set GR8:$dst, (loadi8 addr:$src))]>; +def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize16; +def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (loadi32 addr:$src))]>, OpSize32; +def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (load addr:$src))]>; +} + +let SchedRW = [WriteStore] in { +def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), + "mov{b}\t{$src, $dst|$dst, $src}", + [(store GR8:$src, addr:$dst)]>; +def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", + [(store GR16:$src, addr:$dst)]>, OpSize16; +def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", + [(store GR32:$src, addr:$dst)]>, OpSize32; +def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", + [(store GR64:$src, addr:$dst)]>; +} // SchedRW + +// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so +// that they can be used for copying and storing h registers, which can't be +// encoded when a REX prefix is present. +let isCodeGenOnly = 1 in { +let hasSideEffects = 0, isMoveReg = 1 in +def MOV8rr_NOREX : I<0x88, MRMDestReg, + (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteMove]>; +let mayStore = 1, hasSideEffects = 0 in +def MOV8mr_NOREX : I<0x88, MRMDestMem, + (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteStore]>; +let mayLoad = 1, hasSideEffects = 0, + canFoldAsLoad = 1, isReMaterializable = 1 in +def MOV8rm_NOREX : I<0x8A, MRMSrcMem, + (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteLoad]>; +} + + +// Condition code ops, incl. set if equal/not equal/... +let SchedRW = [WriteLAHFSAHF] in { +let Defs = [EFLAGS], Uses = [AH] in +def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", + [(set EFLAGS, (X86sahf AH))]>, + Requires<[HasLAHFSAHF]>; +let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in +def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags + Requires<[HasLAHFSAHF]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Bit tests instructions: BT, BTS, BTR, BTC. + +let Defs = [EFLAGS] in { +let SchedRW = [WriteBitTest] in { +def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, + OpSize16, TB, NotMemoryFoldable; +def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, + OpSize32, TB, NotMemoryFoldable; +def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB, + NotMemoryFoldable; +} // SchedRW + +// Unlike with the register+register form, the memory+register form of the +// bt instruction does not ignore the high bits of the index. From ISel's +// perspective, this is pretty bizarre. Make these instructions disassembly +// only for now. These instructions are also slow on modern CPUs so that's +// another reason to avoid generating them. + +let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { + def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + []>, OpSize16, TB, NotMemoryFoldable; + def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + []>, OpSize32, TB, NotMemoryFoldable; + def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + []>, TB, NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest] in { +def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>, + OpSize16, TB; +def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, + OpSize32, TB; +def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB; +} // SchedRW + +// Note that these instructions aren't slow because that only applies when the +// other operand is in a register. When it's an immediate, bt is still fast. +let SchedRW = [WriteALU] in { +def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi16 addr:$src1), + i16immSExt8:$src2))]>, + OpSize16, TB; +def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi32 addr:$src1), + i32immSExt8:$src2))]>, + OpSize32, TB; +def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "bt{q}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi64 addr:$src1), + i64immSExt8:$src2))]>, TB, + Requires<[In64BitMode]>; +} // SchedRW + +let hasSideEffects = 0 in { +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTC32rr : I<0xBB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTC64rr : RI<0xBB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTC64ri8 : RIi8<0xBA, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + Requires<[In64BitMode]>; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTR32rr : I<0xB3, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTR64rr : RI<0xB3, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB; +def BTR32ri8 : Ii8<0xBA, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB; +def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB; +def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB; +def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + Requires<[In64BitMode]>; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTS32rr : I<0xAB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTS64rr : RI<0xAB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, + OpSize16, TB, NotMemoryFoldable; +def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, + OpSize32, TB, NotMemoryFoldable; +def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + NotMemoryFoldable; +} + +let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { +def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTS64ri8 : RIi8<0xBA, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { +def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; +def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; +def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, + Requires<[In64BitMode]>; +} +} // hasSideEffects = 0 +} // Defs = [EFLAGS] + + +//===----------------------------------------------------------------------===// +// Atomic support +// + +// Atomic swap. These are just normal xchg instructions. But since a memory +// operand is referenced, the atomicity is ensured. +multiclass ATOMIC_SWAP opc8, bits<8> opc, string mnemonic, string frag> { + let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { + def NAME#8rm : I(frag # "_8") addr:$ptr, GR8:$val))]>; + def NAME#16rm : I(frag # "_16") addr:$ptr, GR16:$val))]>, + OpSize16; + def NAME#32rm : I(frag # "_32") addr:$ptr, GR32:$val))]>, + OpSize32; + def NAME#64rm : RI(frag # "_64") addr:$ptr, GR64:$val))]>; + } +} + +defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">, NotMemoryFoldable; + +// Swap between registers. +let SchedRW = [WriteALU] in { +let Constraints = "$src1 = $dst1, $src2 = $dst2", hasSideEffects = 0 in { +def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2), + (ins GR8:$src1, GR8:$src2), + "xchg{b}\t{$src1, $src2|$src2, $src1}", []>, NotMemoryFoldable; +def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2), + (ins GR16:$src1, GR16:$src2), + "xchg{w}\t{$src1, $src2|$src2, $src1}", []>, + OpSize16, NotMemoryFoldable; +def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2), + (ins GR32:$src1, GR32:$src2), + "xchg{l}\t{$src1, $src2|$src2, $src1}", []>, + OpSize32, NotMemoryFoldable; +def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst1, GR64:$dst2), + (ins GR64:$src1 ,GR64:$src2), + "xchg{q}\t{$src1, $src2|$src2, $src1}", []>, NotMemoryFoldable; +} + +def NOOP19rr: I<0x19, MRMSrcReg, (outs), (ins GR32:$val, GR32:$src), + "nop\t{$val, $src|$src, $val}", []>, TB, + OpSize32; + +// Swap between EAX and other registers. +let Constraints = "$src = $dst", hasSideEffects = 0 in { +let Uses = [AX], Defs = [AX] in +def XCHG16ar : I<0x90, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), + "xchg{w}\t{%ax, $src|$src, ax}", []>, OpSize16; +let Uses = [EAX], Defs = [EAX] in +def XCHG32ar : I<0x90, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), + "xchg{l}\t{%eax, $src|$src, eax}", []>, OpSize32; +let Uses = [RAX], Defs = [RAX] in +def XCHG64ar : RI<0x90, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), + "xchg{q}\t{%rax, $src|$src, rax}", []>; +} +} // SchedRW + +let hasSideEffects = 0, Constraints = "$src1 = $dst1, $src2 = $dst2", + Defs = [EFLAGS], SchedRW = [WriteALU] in { +def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst1, GR8:$dst2), + (ins GR8:$src1, GR8:$src2), + "xadd{b}\t{$src2, $src1|$src1, $src2}", []>, TB; +def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst1, GR16:$dst2), + (ins GR16:$src1, GR16:$src2), + "xadd{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16; +def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst1, GR32:$dst2), + (ins GR32:$src1, GR32:$src2), + "xadd{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32; +def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst1, GR64:$dst2), + (ins GR64:$src1, GR64:$src2), + "xadd{q}\t{$src2, $src1|$src1, $src2}", []>, TB; +} // SchedRW + +let mayLoad = 1, mayStore = 1, hasSideEffects = 0, Constraints = "$val = $dst", + Defs = [EFLAGS], SchedRW = [WriteALULd, WriteRMW] in { +def XADD8rm : I<0xC0, MRMSrcMem, (outs GR8:$dst), + (ins GR8:$val, i8mem:$ptr), + "xadd{b}\t{$val, $ptr|$ptr, $val}", []>, TB; +def XADD16rm : I<0xC1, MRMSrcMem, (outs GR16:$dst), + (ins GR16:$val, i16mem:$ptr), + "xadd{w}\t{$val, $ptr|$ptr, $val}", []>, TB, + OpSize16; +def XADD32rm : I<0xC1, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$val, i32mem:$ptr), + "xadd{l}\t{$val, $ptr|$ptr, $val}", []>, TB, + OpSize32; +def XADD64rm : RI<0xC1, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$val, i64mem:$ptr), + "xadd{q}\t{$val, $ptr|$ptr, $val}", []>, TB; + +} + +let SchedRW = [WriteALU], hasSideEffects = 0 in { +let Defs = [AL, EFLAGS], Uses = [AL] in +def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), + "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; +let Defs = [AX, EFLAGS], Uses = [AX] in +def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), + "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, + NotMemoryFoldable; +let Defs = [EAX, EFLAGS], Uses = [EAX] in +def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), + "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, + NotMemoryFoldable; +let Defs = [RAX, EFLAGS], Uses = [RAX] in +def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), + "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; +} // SchedRW, hasSideEffects + +let SchedRW = [WriteALULd, WriteRMW], mayLoad = 1, mayStore = 1, + hasSideEffects = 0 in { +let Defs = [AL, EFLAGS], Uses = [AL] in +def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), + "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; +let Defs = [AX, EFLAGS], Uses = [AX] in +def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, + NotMemoryFoldable; +let Defs = [EAX, EFLAGS], Uses = [EAX] in +def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, + NotMemoryFoldable; +let Defs = [RAX, EFLAGS], Uses = [RAX] in +def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, + NotMemoryFoldable; + +let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in +def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), + "cmpxchg8b\t$dst", []>, TB; + +let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in +def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), + "cmpxchg16b\t$dst", []>, + TB, Requires<[HasCmpxchg16b, In64BitMode]>; +} // SchedRW, mayLoad, mayStore, hasSideEffects + + +// Lock instruction prefix +let SchedRW = [WriteMicrocoded] in +def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; + +let SchedRW = [WriteNop] in { + +// Rex64 instruction prefix +def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>, + Requires<[In64BitMode]>; + +// Data16 instruction prefix +def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; +} // SchedRW + +// Repeat string operation instruction prefixes +let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in { +// Repeat (used with INS, OUTS, MOVS, LODS and STOS) +def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; +// Repeat while not equal (used with CMPS and SCAS) +def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; +} + +// String manipulation instructions +let SchedRW = [WriteMicrocoded] in { +let Defs = [AL,ESI], Uses = [ESI,DF] in +def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), + "lodsb\t{$src, %al|al, $src}", []>; +let Defs = [AX,ESI], Uses = [ESI,DF] in +def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), + "lodsw\t{$src, %ax|ax, $src}", []>, OpSize16; +let Defs = [EAX,ESI], Uses = [ESI,DF] in +def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), + "lods{l|d}\t{$src, %eax|eax, $src}", []>, OpSize32; +let Defs = [RAX,ESI], Uses = [ESI,DF] in +def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), + "lodsq\t{$src, %rax|rax, $src}", []>, + Requires<[In64BitMode]>; +} + +let SchedRW = [WriteSystem] in { +let Defs = [ESI], Uses = [DX,ESI,DF] in { +def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), + "outsb\t{$src, %dx|dx, $src}", []>; +def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), + "outsw\t{$src, %dx|dx, $src}", []>, OpSize16; +def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), + "outs{l|d}\t{$src, %dx|dx, $src}", []>, OpSize32; +} + +let Defs = [EDI], Uses = [DX,EDI,DF] in { +def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst), + "insb\t{%dx, $dst|$dst, dx}", []>; +def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst), + "insw\t{%dx, $dst|$dst, dx}", []>, OpSize16; +def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst), + "ins{l|d}\t{%dx, $dst|$dst, dx}", []>, OpSize32; +} +} + +// EFLAGS management instructions. +let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { +def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; +def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; +def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; +} + +// DF management instructions. +let SchedRW = [WriteALU], Defs = [DF] in { +def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; +def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; +} + +// Table lookup instructions +let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in +def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>, Sched<[WriteLoad]>; + +let SchedRW = [WriteMicrocoded] in { +// ASCII Adjust After Addition +let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, + Requires<[Not64BitMode]>; + +// ASCII Adjust AX Before Division +let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), + "aad\t$src", []>, Requires<[Not64BitMode]>; + +// ASCII Adjust AX After Multiply +let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), + "aam\t$src", []>, Requires<[Not64BitMode]>; + +// ASCII Adjust AL After Subtraction - sets +let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in +def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, + Requires<[Not64BitMode]>; + +// Decimal Adjust AL after Addition +let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in +def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, + Requires<[Not64BitMode]>; + +// Decimal Adjust AL after Subtraction +let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in +def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, + Requires<[Not64BitMode]>; +} // SchedRW + +let SchedRW = [WriteSystem] in { +// Check Array Index Against Bounds +// Note: "bound" does not have reversed operands in at&t syntax. +def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i32mem:$src), + "bound\t$dst, $src", []>, OpSize16, + Requires<[Not64BitMode]>; +def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i64mem:$src), + "bound\t$dst, $src", []>, OpSize32, + Requires<[Not64BitMode]>; + +// Adjust RPL Field of Segment Selector +def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), + "arpl\t{$src, $dst|$dst, $src}", []>, + Requires<[Not64BitMode]>, NotMemoryFoldable; +let mayStore = 1 in +def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "arpl\t{$src, $dst|$dst, $src}", []>, + Requires<[Not64BitMode]>, NotMemoryFoldable; +} // SchedRW + +//===----------------------------------------------------------------------===// +// MOVBE Instructions +// +let Predicates = [HasMOVBE] in { + let SchedRW = [WriteALULd] in { + def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "movbe{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, + OpSize16, T8PS; + def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "movbe{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, + OpSize32, T8PS; + def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "movbe{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, + T8PS; + } + let SchedRW = [WriteStore] in { + def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), + "movbe{w}\t{$src, $dst|$dst, $src}", + [(store (bswap GR16:$src), addr:$dst)]>, + OpSize16, T8PS; + def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "movbe{l}\t{$src, $dst|$dst, $src}", + [(store (bswap GR32:$src), addr:$dst)]>, + OpSize32, T8PS; + def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "movbe{q}\t{$src, $dst|$dst, $src}", + [(store (bswap GR64:$src), addr:$dst)]>, + T8PS; + } +} + +//===----------------------------------------------------------------------===// +// RDRAND Instruction +// +let Predicates = [HasRDRAND], Defs = [EFLAGS], SchedRW = [WriteSystem] in { + def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), + "rdrand{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86rdrand))]>, + OpSize16, PS; + def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), + "rdrand{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86rdrand))]>, + OpSize32, PS; + def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), + "rdrand{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86rdrand))]>, + PS; +} + +//===----------------------------------------------------------------------===// +// RDSEED Instruction +// +let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in { + def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), "rdseed{w}\t$dst", + [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, PS; + def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), "rdseed{l}\t$dst", + [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, PS; + def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdseed{q}\t$dst", + [(set GR64:$dst, EFLAGS, (X86rdseed))]>, PS; +} + +//===----------------------------------------------------------------------===// +// LZCNT Instruction +// +let Predicates = [HasLZCNT], Defs = [EFLAGS] in { + def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "lzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, + XS, OpSize16, Sched<[WriteLZCNT]>; + def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "lzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (ctlz (loadi16 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteLZCNTLd]>; + + def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "lzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, + XS, OpSize32, Sched<[WriteLZCNT]>; + def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "lzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (ctlz (loadi32 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteLZCNTLd]>; + + def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "lzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, + XS, Sched<[WriteLZCNT]>; + def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "lzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (ctlz (loadi64 addr:$src))), + (implicit EFLAGS)]>, XS, Sched<[WriteLZCNTLd]>; +} + +//===----------------------------------------------------------------------===// +// BMI Instructions +// +let Predicates = [HasBMI], Defs = [EFLAGS] in { + def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "tzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, + XS, OpSize16, Sched<[WriteTZCNT]>; + def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "tzcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (cttz (loadi16 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteTZCNTLd]>; + + def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "tzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, + XS, OpSize32, Sched<[WriteTZCNT]>; + def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "tzcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (cttz (loadi32 addr:$src))), + (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteTZCNTLd]>; + + def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "tzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, + XS, Sched<[WriteTZCNT]>; + def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "tzcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (cttz (loadi64 addr:$src))), + (implicit EFLAGS)]>, XS, Sched<[WriteTZCNTLd]>; +} + +multiclass bmi_bls { +let hasSideEffects = 0 in { + def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), + !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, + T8PS, VEX_4V, Sched<[WriteALU]>; + let mayLoad = 1 in + def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), + !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, + T8PS, VEX_4V, Sched<[WriteALULd]>; +} +} + +let Predicates = [HasBMI], Defs = [EFLAGS] in { + defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; + defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W; + defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>; + defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W; + defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>; + defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W; +} + +//===----------------------------------------------------------------------===// +// Pattern fragments to auto generate BMI instructions. +//===----------------------------------------------------------------------===// + +let Predicates = [HasBMI] in { + // FIXME: patterns for the load versions are not implemented + def : Pat<(and GR32:$src, (add GR32:$src, -1)), + (BLSR32rr GR32:$src)>; + def : Pat<(and GR64:$src, (add GR64:$src, -1)), + (BLSR64rr GR64:$src)>; + + def : Pat<(xor GR32:$src, (add GR32:$src, -1)), + (BLSMSK32rr GR32:$src)>; + def : Pat<(xor GR64:$src, (add GR64:$src, -1)), + (BLSMSK64rr GR64:$src)>; + + def : Pat<(and GR32:$src, (ineg GR32:$src)), + (BLSI32rr GR32:$src)>; + def : Pat<(and GR64:$src, (ineg GR64:$src)), + (BLSI64rr GR64:$src)>; +} + +multiclass bmi_bextr opc, string mnemonic, RegisterClass RC, + X86MemOperand x86memop, SDNode OpNode, + PatFrag ld_frag, X86FoldableSchedWrite Sched> { + def rr : I, + T8PS, VEX, Sched<[Sched]>; + def rm : I, T8PS, VEX, + Sched<[Sched.Folded, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + ReadAfterLd]>; +} + +let Predicates = [HasBMI], Defs = [EFLAGS] in { + defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem, + X86bextr, loadi32, WriteBEXTR>; + defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem, + X86bextr, loadi64, WriteBEXTR>, VEX_W; +} + +multiclass bmi_bzhi opc, string mnemonic, RegisterClass RC, + X86MemOperand x86memop, Intrinsic Int, + PatFrag ld_frag, X86FoldableSchedWrite Sched> { + def rr : I, + T8PS, VEX, Sched<[Sched]>; + def rm : I, T8PS, VEX, + Sched<[Sched.Folded, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + ReadAfterLd]>; +} + +let Predicates = [HasBMI2], Defs = [EFLAGS] in { + defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem, + int_x86_bmi_bzhi_32, loadi32, WriteBZHI>; + defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem, + int_x86_bmi_bzhi_64, loadi64, WriteBZHI>, VEX_W; +} + +def CountTrailingOnes : SDNodeXFormgetZExtValue()), SDLoc(N)); +}]>; + +def BEXTRMaskXForm : SDNodeXFormgetZExtValue()); + return getI32Imm(Length << 8, SDLoc(N)); +}]>; + +def AndMask64 : ImmLeaf(Imm); +}]>; + +// Use BEXTR for 64-bit 'and' with large immediate 'mask'. +let Predicates = [HasBMI, NoBMI2, NoTBM] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BEXTR64rr GR64:$src, + (SUBREG_TO_REG (i64 0), + (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BEXTR64rm addr:$src, + (SUBREG_TO_REG (i64 0), + (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; +} + +// Use BZHI for 64-bit 'and' with large immediate 'mask'. +let Predicates = [HasBMI2, NoTBM] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; +} + +let Predicates = [HasBMI2] in { + multiclass _bmi_bzhi_pattern { + def : Pat; + def : Pat; + } + + multiclass bmi_bzhi_patterns { + // x & ((1 << y) - 1) + defm : _bmi_bzhi_pattern<(and RC:$src, (add (shl 1, GR8:$lz), -1)), + (and (x86memop addr:$src), + (add (shl 1, GR8:$lz), -1)), + RC, VT, DstInst, DstMemInst>; + + // x & ~(-1 << y) + defm : _bmi_bzhi_pattern<(and RC:$src, (xor (shl -1, GR8:$lz), -1)), + (and (x86memop addr:$src), + (xor (shl -1, GR8:$lz), -1)), + RC, VT, DstInst, DstMemInst>; + + // x & (-1 >> (bitwidth - y)) + defm : _bmi_bzhi_pattern<(and RC:$src, (srl -1, (sub bitwidth, GR8:$lz))), + (and (x86memop addr:$src), + (srl -1, (sub bitwidth, GR8:$lz))), + RC, VT, DstInst, DstMemInst>; + + // x << (bitwidth - y) >> (bitwidth - y) + defm : _bmi_bzhi_pattern<(srl (shl RC:$src, (sub bitwidth, GR8:$lz)), + (sub bitwidth, GR8:$lz)), + (srl (shl (x86memop addr:$src), + (sub bitwidth, GR8:$lz)), + (sub bitwidth, GR8:$lz)), + RC, VT, DstInst, DstMemInst>; + } + + defm : bmi_bzhi_patterns; + defm : bmi_bzhi_patterns; + + // x & (-1 >> (32 - y)) + def : Pat<(and GR32:$src, (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), + (BZHI32rr GR32:$src, GR32:$lz)>; + def : Pat<(and (loadi32 addr:$src), (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), + (BZHI32rm addr:$src, GR32:$lz)>; + + // x & (-1 >> (64 - y)) + def : Pat<(and GR64:$src, (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + def : Pat<(and (loadi64 addr:$src), (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + + // x << (32 - y) >> (32 - y) + def : Pat<(srl (shl GR32:$src, (i8 (trunc (sub 32, GR32:$lz)))), + (i8 (trunc (sub 32, GR32:$lz)))), + (BZHI32rr GR32:$src, GR32:$lz)>; + def : Pat<(srl (shl (loadi32 addr:$src), (i8 (trunc (sub 32, GR32:$lz)))), + (i8 (trunc (sub 32, GR32:$lz)))), + (BZHI32rm addr:$src, GR32:$lz)>; + + // x << (64 - y) >> (64 - y) + def : Pat<(srl (shl GR64:$src, (i8 (trunc (sub 64, GR32:$lz)))), + (i8 (trunc (sub 64, GR32:$lz)))), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + def : Pat<(srl (shl (loadi64 addr:$src), (i8 (trunc (sub 64, GR32:$lz)))), + (i8 (trunc (sub 64, GR32:$lz)))), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; +} // HasBMI2 + +multiclass bmi_pdep_pext { + def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, + VEX_4V, Sched<[WriteALU]>; + def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), + !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, + VEX_4V, Sched<[WriteALULd, ReadAfterLd]>; +} + +let Predicates = [HasBMI2] in { + defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, + int_x86_bmi_pdep_32, loadi32>, T8XD; + defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, + int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; + defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, + int_x86_bmi_pext_32, loadi32>, T8XS; + defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, + int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; +} + +//===----------------------------------------------------------------------===// +// TBM Instructions +// +let Predicates = [HasTBM], Defs = [EFLAGS] in { + +multiclass tbm_ternary_imm opc, RegisterClass RC, string OpcodeStr, + X86MemOperand x86memop, PatFrag ld_frag, + SDNode OpNode, Operand immtype, + SDPatternOperator immoperator, + X86FoldableSchedWrite Sched> { + def ri : Ii32, + XOP, XOPA, Sched<[Sched]>; + def mi : Ii32, + XOP, XOPA, Sched<[Sched.Folded]>; +} + +defm BEXTRI32 : tbm_ternary_imm<0x10, GR32, "bextr{l}", i32mem, loadi32, + X86bextr, i32imm, imm, WriteBEXTR>; +let ImmT = Imm32S in +defm BEXTRI64 : tbm_ternary_imm<0x10, GR64, "bextr{q}", i64mem, loadi64, + X86bextr, i64i32imm, + i64immSExt32, WriteBEXTR>, VEX_W; + +multiclass tbm_binary_rm opc, Format FormReg, Format FormMem, + RegisterClass RC, string OpcodeStr, + X86MemOperand x86memop, X86FoldableSchedWrite Sched> { +let hasSideEffects = 0 in { + def rr : I, + XOP_4V, XOP9, Sched<[Sched]>; + let mayLoad = 1 in + def rm : I, + XOP_4V, XOP9, Sched<[Sched.Folded]>; +} +} + +multiclass tbm_binary_intr opc, string OpcodeStr, + X86FoldableSchedWrite Sched, + Format FormReg, Format FormMem> { + defm NAME#32 : tbm_binary_rm; + defm NAME#64 : tbm_binary_rm, VEX_W; +} + +defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>; +defm BLCI : tbm_binary_intr<0x02, "blci", WriteALU, MRM6r, MRM6m>; +defm BLCIC : tbm_binary_intr<0x01, "blcic", WriteALU, MRM5r, MRM5m>; +defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", WriteALU, MRM1r, MRM1m>; +defm BLCS : tbm_binary_intr<0x01, "blcs", WriteALU, MRM3r, MRM3m>; +defm BLSFILL : tbm_binary_intr<0x01, "blsfill", WriteALU, MRM2r, MRM2m>; +defm BLSIC : tbm_binary_intr<0x01, "blsic", WriteALU, MRM6r, MRM6m>; +defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", WriteALU, MRM7r, MRM7m>; +defm TZMSK : tbm_binary_intr<0x01, "tzmsk", WriteALU, MRM4r, MRM4m>; +} // HasTBM, EFLAGS + +// Use BEXTRI for 64-bit 'and' with large immediate 'mask'. +let Predicates = [HasTBM] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BEXTRI64ri GR64:$src, (BEXTRMaskXForm imm:$mask))>; + + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BEXTRI64mi addr:$src, (BEXTRMaskXForm imm:$mask))>; +} + +//===----------------------------------------------------------------------===// +// Lightweight Profiling Instructions + +let Predicates = [HasLWP], SchedRW = [WriteSystem] in { + +def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", + [(int_x86_llwpcb GR32:$src)]>, XOP, XOP9; +def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", + [(set GR32:$dst, (int_x86_slwpcb))]>, XOP, XOP9; + +def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", + [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, VEX_W; +def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", + [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, VEX_W; + +multiclass lwpins_intr { + def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), + "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, imm:$cntl))]>, + XOP_4V, XOPA; + let mayLoad = 1 in + def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), + "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), imm:$cntl))]>, + XOP_4V, XOPA; +} + +let Defs = [EFLAGS] in { + defm LWPINS32 : lwpins_intr; + defm LWPINS64 : lwpins_intr, VEX_W; +} // EFLAGS + +multiclass lwpval_intr { + def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), + "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(Int RC:$src0, GR32:$src1, imm:$cntl)]>, XOP_4V, XOPA; + let mayLoad = 1 in + def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), + "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(Int RC:$src0, (loadi32 addr:$src1), imm:$cntl)]>, + XOP_4V, XOPA; +} + +defm LWPVAL32 : lwpval_intr; +defm LWPVAL64 : lwpval_intr, VEX_W; + +} // HasLWP, SchedRW + +//===----------------------------------------------------------------------===// +// MONITORX/MWAITX Instructions +// +let SchedRW = [ WriteSystem ] in { + let usesCustomInserter = 1 in { + def MONITORX : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3), + [(int_x86_monitorx addr:$src1, GR32:$src2, GR32:$src3)]>, + Requires<[ HasMWAITX ]>; + } + + let Uses = [ EAX, ECX, EDX ] in { + def MONITORXrrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, + TB, Requires<[ HasMWAITX ]>; + } + + let Uses = [ ECX, EAX, EBX ] in { + def MWAITXrrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", + [(int_x86_mwaitx ECX, EAX, EBX)]>, + TB, Requires<[ HasMWAITX ]>; + } +} // SchedRW + +def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrrr)>, + Requires<[ Not64BitMode ]>; +def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>, + Requires<[ In64BitMode ]>; + +def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORXrrr)>, + Requires<[ Not64BitMode ]>; +def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>, + Requires<[ In64BitMode ]>; + +//===----------------------------------------------------------------------===// +// WAITPKG Instructions +// +let SchedRW = [WriteSystem] in { + def UMONITOR16 : I<0xAE, MRM6r, (outs), (ins GR16:$src), + "umonitor\t$src", [(int_x86_umonitor GR16:$src)]>, + XS, AdSize16, Requires<[HasWAITPKG, Not64BitMode]>; + def UMONITOR32 : I<0xAE, MRM6r, (outs), (ins GR32:$src), + "umonitor\t$src", [(int_x86_umonitor GR32:$src)]>, + XS, AdSize32, Requires<[HasWAITPKG]>; + def UMONITOR64 : I<0xAE, MRM6r, (outs), (ins GR64:$src), + "umonitor\t$src", [(int_x86_umonitor GR64:$src)]>, + XS, AdSize64, Requires<[HasWAITPKG, In64BitMode]>; + let Uses = [EAX, EDX], Defs = [EFLAGS] in { + def UMWAIT : I<0xAE, MRM6r, + (outs), (ins GR32orGR64:$src), "umwait\t$src", + [(set EFLAGS, (X86umwait GR32orGR64:$src, EDX, EAX))]>, + XD, Requires<[HasWAITPKG]>; + def TPAUSE : I<0xAE, MRM6r, + (outs), (ins GR32orGR64:$src), "tpause\t$src", + [(set EFLAGS, (X86tpause GR32orGR64:$src, EDX, EAX))]>, + PD, Requires<[HasWAITPKG]>, NotMemoryFoldable; + } +} // SchedRW + +//===----------------------------------------------------------------------===// +// MOVDIRI - Move doubleword/quadword as direct store +// +let SchedRW = [WriteStore] in { +def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "movdiri\t{$src, $dst|$dst, $src}", + [(int_x86_directstore32 addr:$dst, GR32:$src)]>, + T8, Requires<[HasMOVDIRI]>; +def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "movdiri\t{$src, $dst|$dst, $src}", + [(int_x86_directstore64 addr:$dst, GR64:$src)]>, + T8, Requires<[In64BitMode, HasMOVDIRI]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// MOVDIR64B - Move 64 bytes as direct store +// +let SchedRW = [WriteStore] in { +def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), + "movdir64b\t{$src, $dst|$dst, $src}", []>, + T8PD, AdSize16, Requires<[HasMOVDIR64B, Not64BitMode]>; +def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), + "movdir64b\t{$src, $dst|$dst, $src}", + [(int_x86_movdir64b GR32:$dst, addr:$src)]>, + T8PD, AdSize32, Requires<[HasMOVDIR64B]>; +def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), + "movdir64b\t{$src, $dst|$dst, $src}", + [(int_x86_movdir64b GR64:$dst, addr:$src)]>, + T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// CLZERO Instruction +// +let SchedRW = [WriteSystem] in { + let Uses = [EAX] in + def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, + TB, Requires<[HasCLZERO]>; + + let usesCustomInserter = 1 in { + def CLZERO : PseudoI<(outs), (ins i32mem:$src1), + [(int_x86_clzero addr:$src1)]>, Requires<[HasCLZERO]>; + } +} // SchedRW + +def : InstAlias<"clzero\t{%eax|eax}", (CLZEROr)>, Requires<[Not64BitMode]>; +def : InstAlias<"clzero\t{%rax|rax}", (CLZEROr)>, Requires<[In64BitMode]>; + +//===----------------------------------------------------------------------===// +// Pattern fragments to auto generate TBM instructions. +//===----------------------------------------------------------------------===// + +let Predicates = [HasTBM] in { + // FIXME: patterns for the load versions are not implemented + def : Pat<(and GR32:$src, (add GR32:$src, 1)), + (BLCFILL32rr GR32:$src)>; + def : Pat<(and GR64:$src, (add GR64:$src, 1)), + (BLCFILL64rr GR64:$src)>; + + def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), + (BLCI32rr GR32:$src)>; + def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), + (BLCI64rr GR64:$src)>; + + // Extra patterns because opt can optimize the above patterns to this. + def : Pat<(or GR32:$src, (sub -2, GR32:$src)), + (BLCI32rr GR32:$src)>; + def : Pat<(or GR64:$src, (sub -2, GR64:$src)), + (BLCI64rr GR64:$src)>; + + def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), + (BLCIC32rr GR32:$src)>; + def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), + (BLCIC64rr GR64:$src)>; + + def : Pat<(xor GR32:$src, (add GR32:$src, 1)), + (BLCMSK32rr GR32:$src)>; + def : Pat<(xor GR64:$src, (add GR64:$src, 1)), + (BLCMSK64rr GR64:$src)>; + + def : Pat<(or GR32:$src, (add GR32:$src, 1)), + (BLCS32rr GR32:$src)>; + def : Pat<(or GR64:$src, (add GR64:$src, 1)), + (BLCS64rr GR64:$src)>; + + def : Pat<(or GR32:$src, (add GR32:$src, -1)), + (BLSFILL32rr GR32:$src)>; + def : Pat<(or GR64:$src, (add GR64:$src, -1)), + (BLSFILL64rr GR64:$src)>; + + def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), + (BLSIC32rr GR32:$src)>; + def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), + (BLSIC64rr GR64:$src)>; + + def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), + (T1MSKC32rr GR32:$src)>; + def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), + (T1MSKC64rr GR64:$src)>; + + def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), + (TZMSK32rr GR32:$src)>; + def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), + (TZMSK64rr GR64:$src)>; +} // HasTBM + +//===----------------------------------------------------------------------===// +// Memory Instructions +// + +let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in +def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), + "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD; + +let Predicates = [HasCLWB], SchedRW = [WriteLoad] in +def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", + [(int_x86_clwb addr:$src)]>, PD, NotMemoryFoldable; + +let Predicates = [HasCLDEMOTE], SchedRW = [WriteLoad] in +def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src", + [(int_x86_cldemote addr:$src)]>, TB; + +//===----------------------------------------------------------------------===// +// Subsystems. +//===----------------------------------------------------------------------===// + +include "X86Capstone.td" + +include "X86InstrArithmetic.td" +include "X86InstrCMovSetCC.td" +include "X86InstrExtension.td" +include "X86InstrControl.td" +include "X86InstrShiftRotate.td" + +// X87 Floating Point Stack. +//include "X86InstrFPStack.td" + +// SIMD support (SSE, MMX and AVX) +//include "X86InstrFragmentsSIMD.td" + +// FMA - Fused Multiply-Add support (requires FMA) +//include "X86InstrFMA.td" + +// XOP +//include "X86InstrXOP.td" + +// SSE, MMX and 3DNow! vector support. +//include "X86InstrSSE.td" +//include "X86InstrAVX512.td" +//include "X86InstrMMX.td" +//include "X86Instr3DNow.td" + +// MPX instructions +//include "X86InstrMPX.td" + +include "X86InstrVMX.td" +include "X86InstrSVM.td" + +//include "X86InstrTSX.td" +//include "X86InstrSGX.td" + +// System instructions. +include "X86InstrSystem.td" + +// Compiler Pseudo Instructions and Pat Patterns +//include "X86InstrCompiler.td" +//include "X86InstrVecCompiler.td" + +//===----------------------------------------------------------------------===// +// Assembler Mnemonic Aliases +//===----------------------------------------------------------------------===// + +def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; + +def : MnemonicAlias<"cbw", "cbtw", "att">; +def : MnemonicAlias<"cwde", "cwtl", "att">; +def : MnemonicAlias<"cwd", "cwtd", "att">; +def : MnemonicAlias<"cdq", "cltd", "att">; +def : MnemonicAlias<"cdqe", "cltq", "att">; +def : MnemonicAlias<"cqo", "cqto", "att">; + +// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. +def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; + +def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; +def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; + +def : MnemonicAlias<"loopz", "loope">; +def : MnemonicAlias<"loopnz", "loopne">; + +def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"popf", "popfq", "intel">, Requires<[In64BitMode]>; +def : MnemonicAlias<"popfd", "popfl", "att">; + +// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in +// all modes. However: "push (addr)" and "push $42" should default to +// pushl/pushq depending on the current mode. Similar for "pop %bx" +def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"pushf", "pushfq", "intel">, Requires<[In64BitMode]>; +def : MnemonicAlias<"pushfd", "pushfl", "att">; + +def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; +def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; +def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; +def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; + +def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; + +def : MnemonicAlias<"repe", "rep">; +def : MnemonicAlias<"repz", "rep">; +def : MnemonicAlias<"repnz", "repne">; + +def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; + +// Apply 'ret' behavior to 'retn' +def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"retn", "ret", "intel">; + +def : MnemonicAlias<"sal", "shl", "intel">; +def : MnemonicAlias<"salb", "shlb", "att">; +def : MnemonicAlias<"salw", "shlw", "att">; +def : MnemonicAlias<"sall", "shll", "att">; +def : MnemonicAlias<"salq", "shlq", "att">; + +def : MnemonicAlias<"smovb", "movsb", "att">; +def : MnemonicAlias<"smovw", "movsw", "att">; +def : MnemonicAlias<"smovl", "movsl", "att">; +def : MnemonicAlias<"smovq", "movsq", "att">; + +def : MnemonicAlias<"ud2a", "ud2", "att">; +def : MnemonicAlias<"verrw", "verr", "att">; + +// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release' +def : MnemonicAlias<"acquire", "xacquire", "intel">; +def : MnemonicAlias<"release", "xrelease", "intel">; + +// System instruction aliases. +def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; +def : MnemonicAlias<"sysret", "sysretl", "att">; +def : MnemonicAlias<"sysexit", "sysexitl", "att">; + +def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; +//def : MnemonicAlias<"lgdt", "lgdtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"lgdt", "lgdtd", "intel">, Requires<[In32BitMode]>; +//def : MnemonicAlias<"lidt", "lidtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"lidt", "lidtd", "intel">, Requires<[In32BitMode]>; +//def : MnemonicAlias<"sgdt", "sgdtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"sgdt", "sgdtd", "intel">, Requires<[In32BitMode]>; +//def : MnemonicAlias<"sidt", "sidtw", "intel">, Requires<[In16BitMode]>; +//def : MnemonicAlias<"sidt", "sidtd", "intel">, Requires<[In32BitMode]>; + + +// Floating point stack aliases. +def : MnemonicAlias<"fcmovz", "fcmove", "att">; +def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; +def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; +def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; +def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; +def : MnemonicAlias<"fcomip", "fcompi">; +def : MnemonicAlias<"fildq", "fildll", "att">; +def : MnemonicAlias<"fistpq", "fistpll", "att">; +def : MnemonicAlias<"fisttpq", "fisttpll", "att">; +def : MnemonicAlias<"fldcww", "fldcw", "att">; +def : MnemonicAlias<"fnstcww", "fnstcw", "att">; +def : MnemonicAlias<"fnstsww", "fnstsw", "att">; +def : MnemonicAlias<"fucomip", "fucompi">; +def : MnemonicAlias<"fwait", "wait">; + +def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; +def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; +def : MnemonicAlias<"xsaveq", "xsave64", "att">; +def : MnemonicAlias<"xrstorq", "xrstor64", "att">; +def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; +def : MnemonicAlias<"xrstorsq", "xrstors64", "att">; +def : MnemonicAlias<"xsavecq", "xsavec64", "att">; +def : MnemonicAlias<"xsavesq", "xsaves64", "att">; + +class CondCodeAlias + : MnemonicAlias; + +/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of +/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for +/// example "setz" -> "sete". +multiclass IntegerCondCodeMnemonicAlias { + def C : CondCodeAlias; // setc -> setb + def Z : CondCodeAlias; // setz -> sete + def NA : CondCodeAlias; // setna -> setbe + def NB : CondCodeAlias; // setnb -> setae + def NC : CondCodeAlias; // setnc -> setae + def NG : CondCodeAlias; // setng -> setle + def NL : CondCodeAlias; // setnl -> setge + def NZ : CondCodeAlias; // setnz -> setne + def PE : CondCodeAlias; // setpe -> setp + def PO : CondCodeAlias; // setpo -> setnp + + def NAE : CondCodeAlias; // setnae -> setb + def NBE : CondCodeAlias; // setnbe -> seta + def NGE : CondCodeAlias; // setnge -> setl + def NLE : CondCodeAlias; // setnle -> setg +} + +// Aliases for set +defm : IntegerCondCodeMnemonicAlias<"set", "">; +// Aliases for j +defm : IntegerCondCodeMnemonicAlias<"j", "">; +// Aliases for cmov{w,l,q} +defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; +defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; +defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; +// No size suffix for intel-style asm. +defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; + + +//===----------------------------------------------------------------------===// +// Assembler Instruction Aliases +//===----------------------------------------------------------------------===// + +// aad/aam default to base 10 if no operand is specified. +def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>; +def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>; + +// Disambiguate the mem/imm form of bt-without-a-suffix as btl. +// Likewise for btc/btr/bts. +def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}", + (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; +def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}", + (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; +def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}", + (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; +def : InstAlias<"bts\t{$imm, $mem|$mem, $imm}", + (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; + +// clr aliases. +def : InstAlias<"clr{b}\t$reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; +def : InstAlias<"clr{w}\t$reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; +def : InstAlias<"clr{l}\t$reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; +def : InstAlias<"clr{q}\t$reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; + +// lods aliases. Accept the destination being omitted because it's implicit +// in the mnemonic, or the mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"lodsb\t$src", (LODSB srcidx8:$src), 0>; +def : InstAlias<"lodsw\t$src", (LODSW srcidx16:$src), 0>; +def : InstAlias<"lods{l|d}\t$src", (LODSL srcidx32:$src), 0>; +def : InstAlias<"lodsq\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; +def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; +def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; +def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; +def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; +def : InstAlias<"lods\t$src", (LODSB srcidx8:$src), 0, "intel">; +def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0, "intel">; +def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0, "intel">; +def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; + + +// stos aliases. Accept the source being omitted because it's implicit in +// the mnemonic, or the mnemonic suffix being omitted because it's implicit +// in the source. +def : InstAlias<"stosb\t$dst", (STOSB dstidx8:$dst), 0>; +def : InstAlias<"stosw\t$dst", (STOSW dstidx16:$dst), 0>; +def : InstAlias<"stos{l|d}\t$dst", (STOSL dstidx32:$dst), 0>; +def : InstAlias<"stosq\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; +def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; +def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; +def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst), 0, "intel">; +def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0, "intel">; +def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0, "intel">; +def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; + + +// scas aliases. Accept the destination being omitted because it's implicit +// in the mnemonic, or the mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"scasb\t$dst", (SCASB dstidx8:$dst), 0>; +def : InstAlias<"scasw\t$dst", (SCASW dstidx16:$dst), 0>; +def : InstAlias<"scas{l|d}\t$dst", (SCASL dstidx32:$dst), 0>; +def : InstAlias<"scasq\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; +def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; +def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; +def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst), 0, "intel">; +def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0, "intel">; +def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0, "intel">; +def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; + +// cmps aliases. Mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0, "intel">; +def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0, "intel">; +def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0, "intel">; +def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; + +// movs aliases. Mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0, "intel">; +def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0, "intel">; +def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0, "intel">; +def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; + +// div and idiv aliases for explicit A register. +def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; +def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; +def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; +def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; +def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; +def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; +def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; +def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; +def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; +def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; +def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; +def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; +def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; +def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; +def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; +def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; + + + +// Various unary fpstack operations default to operating on ST1. +// For example, "fxch" -> "fxch %st(1)" +def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; +def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; +def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; +def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; +def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; +def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; +def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; +def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; +def : InstAlias<"fxch", (XCH_F ST1), 0>; +def : InstAlias<"fcom", (COM_FST0r ST1), 0>; +def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; +def : InstAlias<"fcomi", (COM_FIr ST1), 0>; +def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; +def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; +def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; +def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; +def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; + +// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. +// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate +// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with +// gas. +multiclass FpUnaryAlias { + def : InstAlias; + def : InstAlias; +} + +defm : FpUnaryAlias<"fadd", ADD_FST0r>; +defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; +defm : FpUnaryAlias<"fsub", SUB_FST0r>; +defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; +defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; +defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; +defm : FpUnaryAlias<"fmul", MUL_FST0r>; +defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; +defm : FpUnaryAlias<"fdiv", DIV_FST0r>; +defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; +defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; +defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; +defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; +defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; +defm : FpUnaryAlias<"fcompi", COM_FIPr>; +defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; + + +// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they +// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, +// solely because gas supports it. +def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; +def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; +def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; +def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; +def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; +def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; + +def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; + +// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but +// this is compatible with what GAS does. +def : InstAlias<"lcall\t$seg : $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; +def : InstAlias<"ljmp\t$seg : $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; +def : InstAlias<"lcall\t{*}$dst", (FARCALL32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; +def : InstAlias<"ljmp\t{*}$dst", (FARJMP32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; +def : InstAlias<"lcall\t$seg : $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; +def : InstAlias<"ljmp\t$seg : $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; +def : InstAlias<"lcall\t{*}$dst", (FARCALL16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; +def : InstAlias<"ljmp\t{*}$dst", (FARJMP16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; + +def : InstAlias<"jmp\t{*}$dst", (JMP64m i64mem:$dst), 0, "att">, Requires<[In64BitMode]>; +def : InstAlias<"jmp\t{*}$dst", (JMP32m i32mem:$dst), 0, "att">, Requires<[In32BitMode]>; +def : InstAlias<"jmp\t{*}$dst", (JMP16m i16mem:$dst), 0, "att">, Requires<[In16BitMode]>; + + +// "imul , B" is an alias for "imul , B, B". +def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; +def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; +def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; +def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; +def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; +def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; + +// ins aliases. Accept the mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0, "intel">; +def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0, "intel">; +def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0, "intel">; + +// outs aliases. Accept the mnemonic suffix being omitted because it's implicit +// in the source. +def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0, "intel">; +def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0, "intel">; +def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0, "intel">; + +// inb %dx -> inb %al, %dx +def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; +def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; +def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; +def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>; +def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>; +def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>; + + +// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp +def : InstAlias<"call\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; +def : InstAlias<"jmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; +def : InstAlias<"call\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; +def : InstAlias<"jmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; +def : InstAlias<"callw\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; +def : InstAlias<"jmpw\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; +def : InstAlias<"calll\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; +def : InstAlias<"jmpl\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; + +// Match 'movq , ' as an alias for movabsq. +def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; + +// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, +// which supports this due to an old AMD documentation bug when 64-bit mode was +// created. +def : InstAlias<"movd\t{$src, $dst|$dst, $src}", + (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; +def : InstAlias<"movd\t{$src, $dst|$dst, $src}", + (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; + +// movsx aliases +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0, "att">; +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0, "att">; +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0, "att">; +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0, "att">; +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0, "att">; +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0, "att">; +def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0, "att">; + +// movzx aliases +def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0, "att">; +def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0, "att">; +def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0, "att">; +def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0, "att">; +def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr8 GR64:$dst, GR8:$src), 0, "att">; +def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr16 GR64:$dst, GR16:$src), 0, "att">; +// Note: No GR32->GR64 movzx form. + +// outb %dx -> outb %al, %dx +def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; +def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; +def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; +def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>; +def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>; +def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>; + +// 'sldt ' can be encoded with either sldtw or sldtq with the same +// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity +// errors, since its encoding is the most compact. +def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; + +// shld/shrd op,op -> shld op, op, CL +def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; +def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; +def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; +def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; +def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; +def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; + +def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; +def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; +def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; +def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; +def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; +def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; + +/* FIXME: This is disabled because the asm matcher is currently incapable of + * matching a fixed immediate like $1. +// "shl X, $1" is an alias for "shl X". +multiclass ShiftRotateByOneAlias { + def : InstAlias(!strconcat(Opc, "8r1")) GR8:$op)>; + def : InstAlias(!strconcat(Opc, "16r1")) GR16:$op)>; + def : InstAlias(!strconcat(Opc, "32r1")) GR32:$op)>; + def : InstAlias(!strconcat(Opc, "64r1")) GR64:$op)>; + def : InstAlias(!strconcat(Opc, "8m1")) i8mem:$op)>; + def : InstAlias(!strconcat(Opc, "16m1")) i16mem:$op)>; + def : InstAlias(!strconcat(Opc, "32m1")) i32mem:$op)>; + def : InstAlias(!strconcat(Opc, "64m1")) i64mem:$op)>; +} + +defm : ShiftRotateByOneAlias<"rcl", "RCL">; +defm : ShiftRotateByOneAlias<"rcr", "RCR">; +defm : ShiftRotateByOneAlias<"rol", "ROL">; +defm : ShiftRotateByOneAlias<"ror", "ROR">; +FIXME */ + +// test: We accept "testX , " and "testX , " as synonyms. +def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}", + (TEST8mr i8mem :$mem, GR8 :$val), 0>; +def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}", + (TEST16mr i16mem:$mem, GR16:$val), 0>; +def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}", + (TEST32mr i32mem:$mem, GR32:$val), 0>; +def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}", + (TEST64mr i64mem:$mem, GR64:$val), 0>; + +// xchg: We accept "xchgX , " and "xchgX , " as synonyms. +def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", + (XCHG8rm GR8 :$val, i8mem :$mem), 0>; +def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", + (XCHG16rm GR16:$val, i16mem:$mem), 0>; +def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", + (XCHG32rm GR32:$val, i32mem:$mem), 0>; +def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", + (XCHG64rm GR64:$val, i64mem:$mem), 0>; + +// xchg: We accept "xchgX , %eax" and "xchgX %eax, " as synonyms. +def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; +def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src), 0>; +def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; + +// In 64-bit mode, xchg %eax, %eax can't be encoded with the 0x90 opcode we +// would get by default because it's defined as NOP. But xchg %eax, %eax implies +// implicit zeroing of the upper 32 bits. So alias to the longer encoding. +def : InstAlias<"xchg{l}\t{%eax, %eax|eax, eax}", + (XCHG32rr EAX, EAX), 0>, Requires<[In64BitMode]>; + +// xchg %rax, %rax is a nop in x86-64 and can be encoded as such. Without this +// we emit an unneeded REX.w prefix. +def : InstAlias<"xchg{q}\t{%rax, %rax|rax, rax}", (NOOP), 0>; + +// These aliases exist to get the parser to prioritize matching 8-bit +// immediate encodings over matching the implicit ax/eax/rax encodings. By +// explicitly mentioning the A register here, these entries will be ordered +// first due to the more explicit immediate type. +def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>; +def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>; + +def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>; +def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>; + +def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>; +def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrMMX.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrMMX.td new file mode 100644 index 0000000..aefeffe --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrMMX.td @@ -0,0 +1,612 @@ +//===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 MMX instruction set, defining the instructions, +// and properties of the instructions which are needed for code generation, +// machine code emission, and analysis. +// +// All instructions that use MMX should be in this file, even if they also use +// SSE. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// MMX Multiclasses +//===----------------------------------------------------------------------===// + +// Alias instruction that maps zero vector to pxor mmx. +// This is expanded by ExpandPostRAPseudos to an pxor. +// We set canFoldAsLoad because this can be converted to a constant-pool +// load of an all-zeros value if folding it would be beneficial. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, SchedRW = [WriteZero] in { +def MMX_SET0 : I<0, Pseudo, (outs VR64:$dst), (ins), "", []>; +} + +let Constraints = "$src1 = $dst" in { + // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic. + // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp. + multiclass MMXI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId, + X86FoldableSchedWrite sched, bit Commutable = 0, + X86MemOperand OType = i64mem> { + def irr : MMXI, + Sched<[sched]> { + let isCommutable = Commutable; + } + def irm : MMXI, + Sched<[sched.Folded, ReadAfterLd]>; + } + + multiclass MMXI_binop_rmi_int opc, bits<8> opc2, Format ImmForm, + string OpcodeStr, Intrinsic IntId, + Intrinsic IntId2, X86FoldableSchedWrite sched, + X86FoldableSchedWrite schedImm> { + def rr : MMXI, + Sched<[sched]>; + def rm : MMXI, + Sched<[sched.Folded, ReadAfterLd]>; + def ri : MMXIi8, + Sched<[schedImm]>; + } +} + +/// Unary MMX instructions requiring SSSE3. +multiclass SS3I_unop_rm_int_mm opc, string OpcodeStr, + Intrinsic IntId64, X86FoldableSchedWrite sched> { + def rr : MMXSS38I, + Sched<[sched]>; + + def rm : MMXSS38I, + Sched<[sched.Folded]>; +} + +/// Binary MMX instructions requiring SSSE3. +let ImmT = NoImm, Constraints = "$src1 = $dst" in { +multiclass SS3I_binop_rm_int_mm opc, string OpcodeStr, + Intrinsic IntId64, X86FoldableSchedWrite sched, + bit Commutable = 0> { + let isCommutable = Commutable in + def rr : MMXSS38I, + Sched<[sched]>; + def rm : MMXSS38I, + Sched<[sched.Folded, ReadAfterLd]>; +} +} + +/// PALIGN MMX instructions (require SSSE3). +multiclass ssse3_palign_mm { + def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), + (ins VR64:$src1, VR64:$src2, u8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>, + Sched<[sched]>; + def rmi : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), + (ins VR64:$src1, i64mem:$src2, u8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + [(set VR64:$dst, (IntId VR64:$src1, + (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass sse12_cvt_pint opc, RegisterClass SrcRC, RegisterClass DstRC, + Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag, + string asm, X86FoldableSchedWrite sched, Domain d> { + def irr : MMXPI, + Sched<[sched]>; + def irm : MMXPI, + Sched<[sched.Folded]>; +} + +multiclass sse12_cvt_pint_3addr opc, RegisterClass SrcRC, + RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, + PatFrag ld_frag, string asm, Domain d> { + def irr : MMXPI, + Sched<[WriteCvtI2PS]>; + def irm : MMXPI, + Sched<[WriteCvtI2PS.Folded]>; +} + +//===----------------------------------------------------------------------===// +// MMX EMMS Instruction +//===----------------------------------------------------------------------===// + +let SchedRW = [WriteEMMS] in +def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>; + +//===----------------------------------------------------------------------===// +// MMX Scalar Instructions +//===----------------------------------------------------------------------===// + +// Data Transfer Instructions +def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, + (x86mmx (scalar_to_vector GR32:$src)))]>, + Sched<[WriteVecMoveFromGpr]>; +def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, + (x86mmx (scalar_to_vector (loadi32 addr:$src))))]>, + Sched<[WriteVecLoad]>; + +let Predicates = [HasMMX] in { + def : Pat<(x86mmx (MMX_X86movw2d GR32:$src)), + (MMX_MOVD64rr GR32:$src)>; + def : Pat<(x86mmx (MMX_X86movw2d (i32 0))), + (MMX_SET0)>; + def : Pat<(x86mmx (MMX_X86movw2d (loadi32 addr:$src))), + (MMX_MOVD64rm addr:$src)>; +} + +let mayStore = 1 in +def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src), + "movd\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteVecStore]>; + +def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, + (MMX_X86movd2w (x86mmx VR64:$src)))]>, + Sched<[WriteVecMoveToGpr]>, FoldGenData<"MMX_MOVD64rr">; + +let isBitcast = 1 in +def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, (bitconvert GR64:$src))]>, + Sched<[WriteVecMoveFromGpr]>; + +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in +def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst), + (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}", + []>, Sched<[SchedWriteVecMoveLS.MMX.RM]>; + +let isBitcast = 1 in { +def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg, + (outs GR64:$dst), (ins VR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (bitconvert VR64:$src))]>, + Sched<[WriteVecMoveToGpr]>; +let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in { +def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), + "movq\t{$src, $dst|$dst, $src}", []>; +let isCodeGenOnly = 1, ForceDisassemble = 1 in +def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src), + "movq\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MMX_MOVQ64rr">; +} // SchedRW, hasSideEffects, isMoveReg +} // isBitcast + +def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}", + (MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>; + +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in +def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem, + (outs), (ins i64mem:$dst, VR64:$src), + "movq\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.MMX.MR]>; + +let SchedRW = [SchedWriteVecMoveLS.MMX.RM] in { +let canFoldAsLoad = 1 in +def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, (load_mmx addr:$src))]>; +} // SchedRW + +let SchedRW = [SchedWriteVecMoveLS.MMX.MR] in +def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(store (x86mmx VR64:$src), addr:$dst)]>; + +let SchedRW = [SchedWriteVecMoveLS.XMM.RR] in { +def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), + (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, + (x86mmx (bitconvert + (i64 (extractelt (v2i64 VR128:$src), + (iPTR 0))))))]>; + +def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst), + (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 + (scalar_to_vector + (i64 (bitconvert (x86mmx VR64:$src))))))]>; + +let isCodeGenOnly = 1, hasSideEffects = 1 in { +def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst), + (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", + []>; + +def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), + (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}", + []>; +} +} // SchedRW + +let Predicates = [HasMMX, HasSSE1] in +def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), + "movntq\t{$src, $dst|$dst, $src}", + [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>, + Sched<[SchedWriteVecMoveLSNT.MMX.MR]>; + +let Predicates = [HasMMX] in { + // movd to MMX register zero-extends + def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))), + (MMX_MOVD64rr GR32:$src)>; + def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector (loadi32 addr:$src))))), + (MMX_MOVD64rm addr:$src)>; +} + +// Arithmetic Instructions +defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b, + SchedWriteVecALU.MMX>; +defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w, + SchedWriteVecALU.MMX>; +defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d, + SchedWriteVecALU.MMX>; +// -- Addition +defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, + SchedWriteVecALU.MMX, 1>; +defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, + SchedWriteVecALU.MMX, 1>; +defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, + SchedWriteVecALU.MMX, 1>; +let Predicates = [HasMMX, HasSSE2] in +defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, + SchedWriteVecALU.MMX, 1>; +defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, + SchedWriteVecALU.MMX, 1>; +defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, + SchedWriteVecALU.MMX, 1>; + +defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, + SchedWriteVecALU.MMX, 1>; +defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, + SchedWriteVecALU.MMX, 1>; + +defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w, + SchedWritePHAdd.MMX>; +defm MMX_PHADDD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d, + SchedWritePHAdd.MMX>; +defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw, + SchedWritePHAdd.MMX>; + +// -- Subtraction +defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b, + SchedWriteVecALU.MMX>; +defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w, + SchedWriteVecALU.MMX>; +defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d, + SchedWriteVecALU.MMX>; +let Predicates = [HasMMX, HasSSE2] in +defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q, + SchedWriteVecALU.MMX>; + +defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b, + SchedWriteVecALU.MMX>; +defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w, + SchedWriteVecALU.MMX>; + +defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b, + SchedWriteVecALU.MMX>; +defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w, + SchedWriteVecALU.MMX>; + +defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w, + SchedWritePHAdd.MMX>; +defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d, + SchedWritePHAdd.MMX>; +defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw, + SchedWritePHAdd.MMX>; + +// -- Multiplication +defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, + SchedWriteVecIMul.MMX, 1>; + +defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, + SchedWriteVecIMul.MMX, 1>; +let Predicates = [HasMMX, HasSSE1] in +defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, + SchedWriteVecIMul.MMX, 1>; +let Predicates = [HasMMX, HasSSE2] in +defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, + SchedWriteVecIMul.MMX, 1>; +defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", + int_x86_ssse3_pmul_hr_sw, + SchedWriteVecIMul.MMX, 1>; + +// -- Miscellanea +defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, + SchedWriteVecIMul.MMX, 1>; + +defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw", + int_x86_ssse3_pmadd_ub_sw, + SchedWriteVecIMul.MMX>; +let Predicates = [HasMMX, HasSSE1] in { +defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, + SchedWriteVecALU.MMX, 1>; +defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, + SchedWriteVecALU.MMX, 1>; + +defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, + SchedWriteVecALU.MMX, 1>; +defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, + SchedWriteVecALU.MMX, 1>; + +defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, + SchedWriteVecALU.MMX, 1>; +defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, + SchedWriteVecALU.MMX, 1>; + +defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, + SchedWritePSADBW.MMX, 1>; +} + +defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b, + SchedWriteVecALU.MMX>; +defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w, + SchedWriteVecALU.MMX>; +defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d, + SchedWriteVecALU.MMX>; +let Constraints = "$src1 = $dst" in + defm MMX_PALIGNR : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b, + SchedWriteShuffle.MMX>; + +// Logical Instructions +defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, + SchedWriteVecLogic.MMX, 1>; +defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, + SchedWriteVecLogic.MMX, 1>; +defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, + SchedWriteVecLogic.MMX, 1>; +defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn, + SchedWriteVecLogic.MMX>; + +// Shift Instructions +defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", + int_x86_mmx_psrl_w, int_x86_mmx_psrli_w, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; +defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", + int_x86_mmx_psrl_d, int_x86_mmx_psrli_d, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; +defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", + int_x86_mmx_psrl_q, int_x86_mmx_psrli_q, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; + +defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", + int_x86_mmx_psll_w, int_x86_mmx_pslli_w, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; +defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", + int_x86_mmx_psll_d, int_x86_mmx_pslli_d, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; +defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", + int_x86_mmx_psll_q, int_x86_mmx_pslli_q, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; + +defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", + int_x86_mmx_psra_w, int_x86_mmx_psrai_w, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; +defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", + int_x86_mmx_psra_d, int_x86_mmx_psrai_d, + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; + +// Comparison Instructions +defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b, + SchedWriteVecALU.MMX>; +defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w, + SchedWriteVecALU.MMX>; +defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d, + SchedWriteVecALU.MMX>; + +defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b, + SchedWriteVecALU.MMX>; +defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w, + SchedWriteVecALU.MMX>; +defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d, + SchedWriteVecALU.MMX>; + +// -- Unpack Instructions +defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw", + int_x86_mmx_punpckhbw, + SchedWriteShuffle.MMX>; +defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd", + int_x86_mmx_punpckhwd, + SchedWriteShuffle.MMX>; +defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq", + int_x86_mmx_punpckhdq, + SchedWriteShuffle.MMX>; +defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw", + int_x86_mmx_punpcklbw, + SchedWriteShuffle.MMX, + 0, i32mem>; +defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd", + int_x86_mmx_punpcklwd, + SchedWriteShuffle.MMX, + 0, i32mem>; +defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq", + int_x86_mmx_punpckldq, + SchedWriteShuffle.MMX, + 0, i32mem>; + +// -- Pack Instructions +defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb, + SchedWriteShuffle.MMX>; +defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw, + SchedWriteShuffle.MMX>; +defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb, + SchedWriteShuffle.MMX>; + +// -- Shuffle Instructions +defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b, + SchedWriteVarShuffle.MMX>; + +def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg, + (outs VR64:$dst), (ins VR64:$src1, u8imm:$src2), + "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR64:$dst, + (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))]>, + Sched<[SchedWriteShuffle.MMX]>; +def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem, + (outs VR64:$dst), (ins i64mem:$src1, u8imm:$src2), + "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR64:$dst, + (int_x86_sse_pshuf_w (load_mmx addr:$src1), + imm:$src2))]>, + Sched<[SchedWriteShuffle.MMX.Folded]>; + +// -- Conversion Instructions +defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi, + f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}", + WriteCvtPS2I, SSEPackedSingle>, PS; +defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi, + f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}", + WriteCvtPD2I, SSEPackedDouble>, PD; +defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi, + f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}", + WriteCvtPS2I, SSEPackedSingle>, PS; +defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi, + f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}", + WriteCvtPD2I, SSEPackedDouble>, PD; +defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd, + i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}", + WriteCvtI2PD, SSEPackedDouble>, PD; +let Constraints = "$src1 = $dst" in { + defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128, + int_x86_sse_cvtpi2ps, + i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}", + SSEPackedSingle>, PS; +} + +// Extract / Insert +let Predicates = [HasMMX, HasSSE1] in +def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg, + (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2), + "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1, + imm:$src2))]>, + Sched<[WriteVecExtract]>; +let Constraints = "$src1 = $dst" in { +let Predicates = [HasMMX, HasSSE1] in { + def MMX_PINSRWrr : MMXIi8<0xC4, MRMSrcReg, + (outs VR64:$dst), + (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3), + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, + GR32orGR64:$src2, imm:$src3))]>, + Sched<[WriteVecInsert]>; + + def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem, + (outs VR64:$dst), + (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3), + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, + (i32 (anyext (loadi16 addr:$src2))), + imm:$src3))]>, + Sched<[WriteVecInsertLd, ReadAfterLd]>; +} +} + +// Mask creation +let Predicates = [HasMMX, HasSSE1] in +def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), + (ins VR64:$src), + "pmovmskb\t{$src, $dst|$dst, $src}", + [(set GR32orGR64:$dst, + (int_x86_mmx_pmovmskb VR64:$src))]>, + Sched<[WriteMMXMOVMSK]>; + +// Low word of XMM to MMX. +def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1, + [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>; + +def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)), + (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>; + +def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))), + (x86mmx (MMX_MOVQ64rm addr:$src))>; + +// Misc. +let SchedRW = [SchedWriteShuffle.MMX] in { +let Uses = [EDI], Predicates = [HasMMX, HasSSE1,Not64BitMode] in +def MMX_MASKMOVQ : MMXI32<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), + "maskmovq\t{$mask, $src|$src, $mask}", + [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>; +let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in +def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), + "maskmovq\t{$mask, $src|$src, $mask}", + [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>; +} + +// 64-bit bit convert. +let Predicates = [HasMMX, HasSSE2] in { +def : Pat<(f64 (bitconvert (x86mmx VR64:$src))), + (MMX_MOVQ2FR64rr VR64:$src)>; +def : Pat<(x86mmx (bitconvert (f64 FR64:$src))), + (MMX_MOVFR642Qrr FR64:$src)>; +def : Pat<(x86mmx (MMX_X86movdq2q + (bc_v2i64 (v4i32 (X86cvtp2Int (v4f32 VR128:$src)))))), + (MMX_CVTPS2PIirr VR128:$src)>; +def : Pat<(x86mmx (MMX_X86movdq2q + (bc_v2i64 (v4i32 (X86cvttp2si (v4f32 VR128:$src)))))), + (MMX_CVTTPS2PIirr VR128:$src)>; +def : Pat<(x86mmx (MMX_X86movdq2q + (bc_v2i64 (v4i32 (fp_to_sint (v4f32 VR128:$src)))))), + (MMX_CVTTPS2PIirr VR128:$src)>; +def : Pat<(x86mmx (MMX_X86movdq2q + (bc_v2i64 (v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))), + (MMX_CVTPD2PIirr VR128:$src)>; +def : Pat<(x86mmx (MMX_X86movdq2q + (bc_v2i64 (v4i32 (X86cvttp2si (v2f64 VR128:$src)))))), + (MMX_CVTTPD2PIirr VR128:$src)>; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrMPX.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrMPX.td new file mode 100644 index 0000000..c1a8cc7 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrMPX.td @@ -0,0 +1,80 @@ +//===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 MPX instruction set, defining the +// instructions, and properties of the instructions which are needed for code +// generation, machine code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +// FIXME: Investigate a better scheduler class once MPX is used inside LLVM. +let SchedRW = [WriteSystem] in { + +multiclass mpx_bound_make opc, string OpcodeStr> { + def 32rm: I, + Requires<[HasMPX, Not64BitMode]>; + def 64rm: I, + Requires<[HasMPX, In64BitMode]>; +} + +defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS; + +multiclass mpx_bound_check opc, string OpcodeStr> { + def 32rm: I, + Requires<[HasMPX, Not64BitMode]>; + def 64rm: I, + Requires<[HasMPX, In64BitMode]>; + + def 32rr: I, + Requires<[HasMPX, Not64BitMode]>; + def 64rr: I, + Requires<[HasMPX, In64BitMode]>; +} +defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable; +defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable; +defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD, NotMemoryFoldable; + +def BNDMOVrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src), + "bndmov\t{$src, $dst|$dst, $src}", []>, PD, + Requires<[HasMPX]>, NotMemoryFoldable; +let mayLoad = 1 in { +def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src), + "bndmov\t{$src, $dst|$dst, $src}", []>, PD, + Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable; +def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src), + "bndmov\t{$src, $dst|$dst, $src}", []>, PD, + Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable; +} +let isCodeGenOnly = 1, ForceDisassemble = 1 in +def BNDMOVrr_REV : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src), + "bndmov\t{$src, $dst|$dst, $src}", []>, PD, + Requires<[HasMPX]>, NotMemoryFoldable; +let mayStore = 1 in { +def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src), + "bndmov\t{$src, $dst|$dst, $src}", []>, PD, + Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable; +def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src), + "bndmov\t{$src, $dst|$dst, $src}", []>, PD, + Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable; + +def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src), + "bndstx\t{$src, $dst|$dst, $src}", []>, PS, + Requires<[HasMPX]>; +} +let mayLoad = 1 in +def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src), + "bndldx\t{$src, $dst|$dst, $src}", []>, PS, + Requires<[HasMPX]>; +} // SchedRW diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrSGX.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrSGX.td new file mode 100644 index 0000000..488cc44 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrSGX.td @@ -0,0 +1,30 @@ +//===-- X86InstrSGX.td - SGX Instruction Set Extension -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the Intel SGX instruction +// set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// SGX instructions + +let SchedRW = [WriteSystem], Predicates = [HasSGX] in { +// ENCLS - Execute an Enclave System Function of Specified Leaf Number +def ENCLS : I<0x01, MRM_CF, (outs), (ins), + "encls", []>, TB; + +// ENCLU - Execute an Enclave User Function of Specified Leaf Number +def ENCLU : I<0x01, MRM_D7, (outs), (ins), + "enclu", []>, TB; + +// ENCLV - Execute an Enclave VMM Function of Specified Leaf Number +def ENCLV : I<0x01, MRM_C0, (outs), (ins), + "enclv", []>, TB; +} // SchedRW diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrSSE.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrSSE.td new file mode 100644 index 0000000..54db881 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrSSE.td @@ -0,0 +1,8256 @@ +//===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 SSE instruction set, defining the instructions, +// and properties of the instructions which are needed for code generation, +// machine code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 Instructions Classes +//===----------------------------------------------------------------------===// + +/// sse12_fp_scalar - SSE 1 & 2 scalar instructions class +multiclass sse12_fp_scalar opc, string OpcodeStr, SDNode OpNode, + RegisterClass RC, X86MemOperand x86memop, + Domain d, X86FoldableSchedWrite sched, + bit Is2Addr = 1> { + let isCommutable = 1 in { + def rr : SI, + Sched<[sched]>; + } + def rm : SI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +/// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class +multiclass sse12_fp_scalar_int opc, string OpcodeStr, + SDPatternOperator OpNode, RegisterClass RC, + ValueType VT, string asm, Operand memopr, + ComplexPattern mem_cpat, Domain d, + X86FoldableSchedWrite sched, bit Is2Addr = 1> { +let isCodeGenOnly = 1, hasSideEffects = 0 in { + def rr_Int : SI_Int, + Sched<[sched]>; + let mayLoad = 1 in + def rm_Int : SI_Int, + Sched<[sched.Folded, ReadAfterLd]>; +} +} + +/// sse12_fp_packed - SSE 1 & 2 packed instructions class +multiclass sse12_fp_packed opc, string OpcodeStr, SDNode OpNode, + RegisterClass RC, ValueType vt, + X86MemOperand x86memop, PatFrag mem_frag, + Domain d, X86FoldableSchedWrite sched, + bit Is2Addr = 1> { + let isCommutable = 1 in + def rr : PI, + Sched<[sched]>; + let mayLoad = 1 in + def rm : PI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +/// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class +multiclass sse12_fp_packed_logical_rm opc, RegisterClass RC, Domain d, + string OpcodeStr, X86MemOperand x86memop, + X86FoldableSchedWrite sched, + list pat_rr, list pat_rm, + bit Is2Addr = 1> { + let isCommutable = 1, hasSideEffects = 0 in + def rr : PI, + Sched<[sched]>; + let hasSideEffects = 0, mayLoad = 1 in + def rm : PI, + Sched<[sched.Folded, ReadAfterLd]>; +} + + +/* +// Alias instructions that map fld0 to xorps for sse or vxorps for avx. +// This is expanded by ExpandPostRAPseudos. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, SchedRW = [WriteZero] in { + def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "", + [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1, NoAVX512]>; + def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "", + [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2, NoAVX512]>; +} +*/ + +//===----------------------------------------------------------------------===// +// AVX & SSE - Zero/One Vectors +//===----------------------------------------------------------------------===// + +// Alias instruction that maps zero vector to pxor / xorp* for sse. +// This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then +// swizzled by ExecutionDomainFix to pxor. +// We set canFoldAsLoad because this can be converted to a constant-pool +// load of an all-zeros value if folding it would be beneficial. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, SchedRW = [WriteZero] in { +def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4f32 immAllZerosV))]>; +} + +let Predicates = [NoAVX512] in +def : Pat<(v4i32 immAllZerosV), (V_SET0)>; + + +// The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI, +// and doesn't need it because on sandy bridge the register is set to zero +// at the rename stage without using any execution unit, so SET0PSY +// and SET0PDY can be used for vector int instructions without penalty +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, Predicates = [NoAVX512], SchedRW = [WriteZero] in { +def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "", + [(set VR256:$dst, (v8i32 immAllZerosV))]>; +} + +// We set canFoldAsLoad because this can be converted to a constant-pool +// load of an all-ones value if folding it would be beneficial. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isPseudo = 1, SchedRW = [WriteZero] in { + def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4i32 immAllOnesV))]>; + let Predicates = [HasAVX1Only, OptForMinSize] in { + def AVX1_SETALLONES: I<0, Pseudo, (outs VR256:$dst), (ins), "", + [(set VR256:$dst, (v8i32 immAllOnesV))]>; + } + let Predicates = [HasAVX2] in + def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "", + [(set VR256:$dst, (v8i32 immAllOnesV))]>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Move FP Scalar Instructions +// +// Move Instructions. Register-to-register movss/movsd is not used for FR32/64 +// register copies because it's a partial register update; Register-to-register +// movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires +// that the insert be implementable in terms of a copy, and just mentioned, we +// don't use movss/movsd for copies. +//===----------------------------------------------------------------------===// + +multiclass sse12_move_rr { + let isCommutable = 1 in + def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + !strconcat(base_opc, asm_opr), + [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))], d>, + Sched<[SchedWriteFShuffle.XMM]>; + + // For the disassembler + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + !strconcat(base_opc, asm_opr), []>, + Sched<[SchedWriteFShuffle.XMM]>, FoldGenData; +} + +multiclass sse12_move { + // AVX + let Predicates = [UseAVX, OptForSize] in + defm V#NAME : sse12_move_rr, + VEX_4V, VEX_LIG, VEX_WIG; + + def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(store RC:$src, addr:$dst)], d>, + VEX, VEX_LIG, Sched<[WriteFStore]>, VEX_WIG; + // SSE1 & 2 + let Constraints = "$src1 = $dst" in { + let Predicates = [pred, NoSSE41_Or_OptForSize] in + defm NAME : sse12_move_rr; + } + + def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(store RC:$src, addr:$dst)], d>, + Sched<[WriteFStore]>; + + def : InstAlias<"v"#OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", + (!cast("V"#NAME#"rr_REV") + VR128:$dst, VR128:$src1, VR128:$src2), 0>; + def : InstAlias(NAME#"rr_REV") + VR128:$dst, VR128:$src2), 0>; +} + +// Loading from memory automatically zeroing upper bits. +multiclass sse12_move_rm { + def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set RC:$dst, (mem_pat addr:$src))], d>, + VEX, VEX_LIG, Sched<[WriteFLoad]>, VEX_WIG; + def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set RC:$dst, (mem_pat addr:$src))], d>, + Sched<[WriteFLoad]>; +} + +defm MOVSS : sse12_move, XS; +defm MOVSD : sse12_move, XD; + +let canFoldAsLoad = 1, isReMaterializable = 1 in { + defm MOVSS : sse12_move_rm, XS; + defm MOVSD : sse12_move_rm, XD; +} + +// Patterns +let Predicates = [UseAVX] in { + // MOVSSrm zeros the high parts of the register; represent this + // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 + def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))), + (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>; + def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), + (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>; + def : Pat<(v4f32 (X86vzload addr:$src)), + (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>; + + // MOVSDrm zeros the high parts of the register; represent this + // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 + def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))), + (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>; + def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), + (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>; + def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), + (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>; + def : Pat<(v2f64 (X86vzload addr:$src)), + (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>; + + // Represent the same patterns above but in the form they appear for + // 256-bit types + def : Pat<(v8f32 (X86vzmovl (insert_subvector undef, + (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>; + def : Pat<(v8f32 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>; + def : Pat<(v4f64 (X86vzmovl (insert_subvector undef, + (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>; + def : Pat<(v4f64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>; + + // Extract and store. + def : Pat<(store (f32 (extractelt (v4f32 VR128:$src), (iPTR 0))), + addr:$dst), + (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>; +} + +let Predicates = [UseAVX, OptForSize] in { + // Move scalar to XMM zero-extended, zeroing a VR128 then do a + // MOVSS to the lower bits. + def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), + (VMOVSSrr (v4f32 (V_SET0)), VR128:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), + (VMOVSSrr (v4i32 (V_SET0)), VR128:$src)>; + + // Move low f32 and clear high bits. + def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v4f32 (VMOVSSrr (v4f32 (V_SET0)), + (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)))), sub_xmm)>; + def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v4i32 (VMOVSSrr (v4i32 (V_SET0)), + (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)))), sub_xmm)>; + + def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v2f64 (VMOVSDrr (v2f64 (V_SET0)), + (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)))), + sub_xmm)>; + def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v2i64 (VMOVSDrr (v2i64 (V_SET0)), + (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)))), + sub_xmm)>; +} + +let Predicates = [UseSSE1] in { + let Predicates = [UseSSE1, NoSSE41_Or_OptForSize] in { + // Move scalar to XMM zero-extended, zeroing a VR128 then do a + // MOVSS to the lower bits. + def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), + (MOVSSrr (v4f32 (V_SET0)), VR128:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), + (MOVSSrr (v4i32 (V_SET0)), VR128:$src)>; + } + + // MOVSSrm already zeros the high parts of the register. + def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))), + (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>; + def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), + (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>; + def : Pat<(v4f32 (X86vzload addr:$src)), + (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>; + + // Extract and store. + def : Pat<(store (f32 (extractelt (v4f32 VR128:$src), (iPTR 0))), + addr:$dst), + (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>; +} + +let Predicates = [UseSSE2] in { + // MOVSDrm already zeros the high parts of the register. + def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))), + (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>; + def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), + (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>; + def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), + (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>; + def : Pat<(v2f64 (X86vzload addr:$src)), + (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>; +} + +// Aliases to help the assembler pick two byte VEX encodings by swapping the +// operands relative to the normal instructions to use VEX.R instead of VEX.B. +def : InstAlias<"vmovss\t{$src2, $src1, $dst|$dst, $src1, $src2}", + (VMOVSSrr_REV VR128L:$dst, VR128:$src1, VR128H:$src2), 0>; +def : InstAlias<"vmovsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + (VMOVSDrr_REV VR128L:$dst, VR128:$src1, VR128H:$src2), 0>; + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Move Aligned/Unaligned FP Instructions +//===----------------------------------------------------------------------===// + +multiclass sse12_mov_packed opc, RegisterClass RC, + X86MemOperand x86memop, PatFrag ld_frag, + string asm, Domain d, + X86SchedWriteMoveLS sched> { +let hasSideEffects = 0, isMoveReg = 1 in + def rr : PI, + Sched<[sched.RR]>; +let canFoldAsLoad = 1, isReMaterializable = 1 in + def rm : PI, + Sched<[sched.RM]>; +} + +let Predicates = [HasAVX, NoVLX] in { +defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32, "movaps", + SSEPackedSingle, SchedWriteFMoveLS.XMM>, + PS, VEX, VEX_WIG; +defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64, "movapd", + SSEPackedDouble, SchedWriteFMoveLS.XMM>, + PD, VEX, VEX_WIG; +defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32, "movups", + SSEPackedSingle, SchedWriteFMoveLS.XMM>, + PS, VEX, VEX_WIG; +defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64, "movupd", + SSEPackedDouble, SchedWriteFMoveLS.XMM>, + PD, VEX, VEX_WIG; + +defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32, "movaps", + SSEPackedSingle, SchedWriteFMoveLS.YMM>, + PS, VEX, VEX_L, VEX_WIG; +defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64, "movapd", + SSEPackedDouble, SchedWriteFMoveLS.YMM>, + PD, VEX, VEX_L, VEX_WIG; +defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32, "movups", + SSEPackedSingle, SchedWriteFMoveLS.YMM>, + PS, VEX, VEX_L, VEX_WIG; +defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64, "movupd", + SSEPackedDouble, SchedWriteFMoveLS.YMM>, + PD, VEX, VEX_L, VEX_WIG; +} + +let Predicates = [UseSSE1] in { +defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32, "movaps", + SSEPackedSingle, SchedWriteFMoveLS.XMM>, + PS; +defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32, "movups", + SSEPackedSingle, SchedWriteFMoveLS.XMM>, + PS; +} +let Predicates = [UseSSE2] in { +defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64, "movapd", + SSEPackedDouble, SchedWriteFMoveLS.XMM>, + PD; +defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64, "movupd", + SSEPackedDouble, SchedWriteFMoveLS.XMM>, + PD; +} + +let Predicates = [HasAVX, NoVLX] in { +let SchedRW = [SchedWriteFMoveLS.XMM.MR] in { +def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movaps\t{$src, $dst|$dst, $src}", + [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, + VEX, VEX_WIG; +def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movapd\t{$src, $dst|$dst, $src}", + [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, + VEX, VEX_WIG; +def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movups\t{$src, $dst|$dst, $src}", + [(store (v4f32 VR128:$src), addr:$dst)]>, + VEX, VEX_WIG; +def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movupd\t{$src, $dst|$dst, $src}", + [(store (v2f64 VR128:$src), addr:$dst)]>, + VEX, VEX_WIG; +} // SchedRW + +let SchedRW = [SchedWriteFMoveLS.YMM.MR] in { +def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src), + "movaps\t{$src, $dst|$dst, $src}", + [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, + VEX, VEX_L, VEX_WIG; +def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src), + "movapd\t{$src, $dst|$dst, $src}", + [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, + VEX, VEX_L, VEX_WIG; +def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src), + "movups\t{$src, $dst|$dst, $src}", + [(store (v8f32 VR256:$src), addr:$dst)]>, + VEX, VEX_L, VEX_WIG; +def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src), + "movupd\t{$src, $dst|$dst, $src}", + [(store (v4f64 VR256:$src), addr:$dst)]>, + VEX, VEX_L, VEX_WIG; +} // SchedRW +} // Predicate + +// For disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, + isMoveReg = 1 in { +let SchedRW = [SchedWriteFMoveLS.XMM.RR] in { + def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst), + (ins VR128:$src), + "movaps\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_WIG, FoldGenData<"VMOVAPSrr">; + def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst), + (ins VR128:$src), + "movapd\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_WIG, FoldGenData<"VMOVAPDrr">; + def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst), + (ins VR128:$src), + "movups\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_WIG, FoldGenData<"VMOVUPSrr">; + def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst), + (ins VR128:$src), + "movupd\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_WIG, FoldGenData<"VMOVUPDrr">; +} // SchedRW + +let SchedRW = [SchedWriteFMoveLS.YMM.RR] in { + def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst), + (ins VR256:$src), + "movaps\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_L, VEX_WIG, FoldGenData<"VMOVAPSYrr">; + def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst), + (ins VR256:$src), + "movapd\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_L, VEX_WIG, FoldGenData<"VMOVAPDYrr">; + def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst), + (ins VR256:$src), + "movups\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_L, VEX_WIG, FoldGenData<"VMOVUPSYrr">; + def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst), + (ins VR256:$src), + "movupd\t{$src, $dst|$dst, $src}", []>, + VEX, VEX_L, VEX_WIG, FoldGenData<"VMOVUPDYrr">; +} // SchedRW +} // Predicate + +// Aliases to help the assembler pick two byte VEX encodings by swapping the +// operands relative to the normal instructions to use VEX.R instead of VEX.B. +def : InstAlias<"vmovaps\t{$src, $dst|$dst, $src}", + (VMOVAPSrr_REV VR128L:$dst, VR128H:$src), 0>; +def : InstAlias<"vmovapd\t{$src, $dst|$dst, $src}", + (VMOVAPDrr_REV VR128L:$dst, VR128H:$src), 0>; +def : InstAlias<"vmovups\t{$src, $dst|$dst, $src}", + (VMOVUPSrr_REV VR128L:$dst, VR128H:$src), 0>; +def : InstAlias<"vmovupd\t{$src, $dst|$dst, $src}", + (VMOVUPDrr_REV VR128L:$dst, VR128H:$src), 0>; +def : InstAlias<"vmovaps\t{$src, $dst|$dst, $src}", + (VMOVAPSYrr_REV VR256L:$dst, VR256H:$src), 0>; +def : InstAlias<"vmovapd\t{$src, $dst|$dst, $src}", + (VMOVAPDYrr_REV VR256L:$dst, VR256H:$src), 0>; +def : InstAlias<"vmovups\t{$src, $dst|$dst, $src}", + (VMOVUPSYrr_REV VR256L:$dst, VR256H:$src), 0>; +def : InstAlias<"vmovupd\t{$src, $dst|$dst, $src}", + (VMOVUPDYrr_REV VR256L:$dst, VR256H:$src), 0>; + +// Reversed version with ".s" suffix for GAS compatibility. +def : InstAlias<"vmovaps.s\t{$src, $dst|$dst, $src}", + (VMOVAPSrr_REV VR128:$dst, VR128:$src), 0>; +def : InstAlias<"vmovapd.s\t{$src, $dst|$dst, $src}", + (VMOVAPDrr_REV VR128:$dst, VR128:$src), 0>; +def : InstAlias<"vmovups.s\t{$src, $dst|$dst, $src}", + (VMOVUPSrr_REV VR128:$dst, VR128:$src), 0>; +def : InstAlias<"vmovupd.s\t{$src, $dst|$dst, $src}", + (VMOVUPDrr_REV VR128:$dst, VR128:$src), 0>; +def : InstAlias<"vmovaps.s\t{$src, $dst|$dst, $src}", + (VMOVAPSYrr_REV VR256:$dst, VR256:$src), 0>; +def : InstAlias<"vmovapd.s\t{$src, $dst|$dst, $src}", + (VMOVAPDYrr_REV VR256:$dst, VR256:$src), 0>; +def : InstAlias<"vmovups.s\t{$src, $dst|$dst, $src}", + (VMOVUPSYrr_REV VR256:$dst, VR256:$src), 0>; +def : InstAlias<"vmovupd.s\t{$src, $dst|$dst, $src}", + (VMOVUPDYrr_REV VR256:$dst, VR256:$src), 0>; + +let SchedRW = [SchedWriteFMoveLS.XMM.MR] in { +def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movaps\t{$src, $dst|$dst, $src}", + [(alignedstore (v4f32 VR128:$src), addr:$dst)]>; +def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movapd\t{$src, $dst|$dst, $src}", + [(alignedstore (v2f64 VR128:$src), addr:$dst)]>; +def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movups\t{$src, $dst|$dst, $src}", + [(store (v4f32 VR128:$src), addr:$dst)]>; +def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movupd\t{$src, $dst|$dst, $src}", + [(store (v2f64 VR128:$src), addr:$dst)]>; +} // SchedRW + +// For disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, + isMoveReg = 1, SchedRW = [SchedWriteFMoveLS.XMM.RR] in { + def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movaps\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOVAPSrr">; + def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movapd\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOVAPDrr">; + def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movups\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOVUPSrr">; + def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movupd\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOVUPDrr">; +} + +// Reversed version with ".s" suffix for GAS compatibility. +def : InstAlias<"movaps.s\t{$src, $dst|$dst, $src}", + (MOVAPSrr_REV VR128:$dst, VR128:$src), 0>; +def : InstAlias<"movapd.s\t{$src, $dst|$dst, $src}", + (MOVAPDrr_REV VR128:$dst, VR128:$src), 0>; +def : InstAlias<"movups.s\t{$src, $dst|$dst, $src}", + (MOVUPSrr_REV VR128:$dst, VR128:$src), 0>; +def : InstAlias<"movupd.s\t{$src, $dst|$dst, $src}", + (MOVUPDrr_REV VR128:$dst, VR128:$src), 0>; + +let Predicates = [HasAVX, NoVLX] in { + // 256-bit load/store need to use floating point load/store in case we don't + // have AVX2. Execution domain fixing will convert to integer if AVX2 is + // available and changing the domain is beneficial. + def : Pat<(alignedloadv4i64 addr:$src), + (VMOVAPSYrm addr:$src)>; + def : Pat<(loadv4i64 addr:$src), + (VMOVUPSYrm addr:$src)>; + def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst), + (VMOVAPSYmr addr:$dst, VR256:$src)>; + def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst), + (VMOVAPSYmr addr:$dst, VR256:$src)>; + def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst), + (VMOVAPSYmr addr:$dst, VR256:$src)>; + def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst), + (VMOVAPSYmr addr:$dst, VR256:$src)>; + def : Pat<(store (v4i64 VR256:$src), addr:$dst), + (VMOVUPSYmr addr:$dst, VR256:$src)>; + def : Pat<(store (v8i32 VR256:$src), addr:$dst), + (VMOVUPSYmr addr:$dst, VR256:$src)>; + def : Pat<(store (v16i16 VR256:$src), addr:$dst), + (VMOVUPSYmr addr:$dst, VR256:$src)>; + def : Pat<(store (v32i8 VR256:$src), addr:$dst), + (VMOVUPSYmr addr:$dst, VR256:$src)>; +} + +// Use movaps / movups for SSE integer load / store (one byte shorter). +// The instructions selected below are then converted to MOVDQA/MOVDQU +// during the SSE domain pass. +let Predicates = [UseSSE1] in { + def : Pat<(alignedloadv2i64 addr:$src), + (MOVAPSrm addr:$src)>; + def : Pat<(loadv2i64 addr:$src), + (MOVUPSrm addr:$src)>; + + def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v2i64 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v4i32 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v8i16 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v16i8 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, VR128:$src)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Move Low packed FP Instructions +//===----------------------------------------------------------------------===// + +multiclass sse12_mov_hilo_packed_baseopc, SDNode pdnode, + string base_opc, string asm_opr> { + // No pattern as they need be special cased between high and low. + let hasSideEffects = 0, mayLoad = 1 in + def PSrm : PI, PS, + Sched<[SchedWriteFShuffle.XMM.Folded, ReadAfterLd]>; + + def PDrm : PI, PD, + Sched<[SchedWriteFShuffle.XMM.Folded, ReadAfterLd]>; +} + +multiclass sse12_mov_hilo_packedopc, SDPatternOperator pdnode, + string base_opc> { + let Predicates = [UseAVX] in + defm V#NAME : sse12_mov_hilo_packed_base, + VEX_4V, VEX_WIG; + + let Constraints = "$src1 = $dst" in + defm NAME : sse12_mov_hilo_packed_base; +} + +defm MOVL : sse12_mov_hilo_packed<0x12, X86Movsd, "movlp">; + +let SchedRW = [WriteFStore] in { +let Predicates = [UseAVX] in { +def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movlps\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt (bc_v2f64 (v4f32 VR128:$src)), + (iPTR 0))), addr:$dst)]>, + VEX, VEX_WIG; +def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movlpd\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt (v2f64 VR128:$src), + (iPTR 0))), addr:$dst)]>, + VEX, VEX_WIG; +}// UseAVX +def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movlps\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt (bc_v2f64 (v4f32 VR128:$src)), + (iPTR 0))), addr:$dst)]>; +def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movlpd\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt (v2f64 VR128:$src), + (iPTR 0))), addr:$dst)]>; +} // SchedRW + +let Predicates = [UseSSE1] in { + // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS + def : Pat<(store (i64 (extractelt (bc_v2i64 (v4f32 VR128:$src2)), + (iPTR 0))), addr:$src1), + (MOVLPSmr addr:$src1, VR128:$src2)>; + + // This pattern helps select MOVLPS on SSE1 only targets. With SSE2 we'll + // end up with a movsd or blend instead of shufp. + // No need for aligned load, we're only loading 64-bits. + def : Pat<(X86Shufp (loadv4f32 addr:$src2), VR128:$src1, (i8 -28)), + (MOVLPSrm VR128:$src1, addr:$src2)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Move Hi packed FP Instructions +//===----------------------------------------------------------------------===// + +defm MOVH : sse12_mov_hilo_packed<0x16, X86Unpckl, "movhp">; + +let SchedRW = [WriteFStore] in { +// v2f64 extract element 1 is always custom lowered to unpack high to low +// and extract element 0 so the non-store version isn't too horrible. +let Predicates = [UseAVX] in { +def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movhps\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt + (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)), + (bc_v2f64 (v4f32 VR128:$src))), + (iPTR 0))), addr:$dst)]>, VEX, VEX_WIG; +def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movhpd\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt + (v2f64 (X86Unpckh VR128:$src, VR128:$src)), + (iPTR 0))), addr:$dst)]>, VEX, VEX_WIG; +} // UseAVX +def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movhps\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt + (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)), + (bc_v2f64 (v4f32 VR128:$src))), + (iPTR 0))), addr:$dst)]>; +def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movhpd\t{$src, $dst|$dst, $src}", + [(store (f64 (extractelt + (v2f64 (X86Unpckh VR128:$src, VR128:$src)), + (iPTR 0))), addr:$dst)]>; +} // SchedRW + +let Predicates = [UseAVX] in { + // Also handle an i64 load because that may get selected as a faster way to + // load the data. + def : Pat<(v2f64 (X86Unpckl VR128:$src1, + (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))), + (VMOVHPDrm VR128:$src1, addr:$src2)>; + + def : Pat<(store (f64 (extractelt + (v2f64 (X86VPermilpi VR128:$src, (i8 1))), + (iPTR 0))), addr:$dst), + (VMOVHPDmr addr:$dst, VR128:$src)>; +} + +let Predicates = [UseSSE1] in { + // This pattern helps select MOVHPS on SSE1 only targets. With SSE2 we'll + // end up with a movsd or blend instead of shufp. + // No need for aligned load, we're only loading 64-bits. + def : Pat<(X86Movlhps VR128:$src1, (loadv4f32 addr:$src2)), + (MOVHPSrm VR128:$src1, addr:$src2)>; +} + +let Predicates = [UseSSE2] in { + // MOVHPD patterns + + // Also handle an i64 load because that may get selected as a faster way to + // load the data. + def : Pat<(v2f64 (X86Unpckl VR128:$src1, + (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))), + (MOVHPDrm VR128:$src1, addr:$src2)>; + + def : Pat<(store (f64 (extractelt + (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))), + (iPTR 0))), addr:$dst), + (MOVHPDmr addr:$dst, VR128:$src)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [UseAVX] in { + def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))]>, + VEX_4V, Sched<[SchedWriteFShuffle.XMM]>, VEX_WIG; + let isCommutable = 1 in + def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))]>, + VEX_4V, Sched<[SchedWriteFShuffle.XMM]>, VEX_WIG, + NotMemoryFoldable; +} +let Constraints = "$src1 = $dst" in { + def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + "movlhps\t{$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))]>, + Sched<[SchedWriteFShuffle.XMM]>; + let isCommutable = 1 in + def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + "movhlps\t{$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))]>, + Sched<[SchedWriteFShuffle.XMM]>, NotMemoryFoldable; +} + +// TODO: This is largely to trick fastisel into ignoring the pattern. +def UnpckhUnary : PatFrag<(ops node:$src1, node:$src2), + (X86Unpckh node:$src1, node:$src2), [{ + return N->getOperand(0) == N->getOperand(1); +}]>; + +let Predicates = [UseSSE2] in { + // TODO: This is a hack pattern to allow lowering to emit unpckh instead of + // movhlps for sse2 without changing a bunch of tests. + def : Pat<(v2f64 (UnpckhUnary VR128:$src, VR128:$src)), + (MOVHLPSrr VR128:$src, VR128:$src)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Conversion Instructions +//===----------------------------------------------------------------------===// + +multiclass sse12_cvt_s opc, RegisterClass SrcRC, RegisterClass DstRC, + SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag, + string asm, X86FoldableSchedWrite sched> { + def rr : SI, + Sched<[sched]>; + def rm : SI, + Sched<[sched.Folded]>; +} + +multiclass sse12_cvt_p opc, RegisterClass RC, X86MemOperand x86memop, + ValueType DstTy, ValueType SrcTy, PatFrag ld_frag, + string asm, Domain d, X86FoldableSchedWrite sched> { +let hasSideEffects = 0 in { + def rr : I, + Sched<[sched]>; + let mayLoad = 1 in + def rm : I, + Sched<[sched.Folded]>; +} +} + +multiclass sse12_vcvt_avx opc, RegisterClass SrcRC, RegisterClass DstRC, + X86MemOperand x86memop, string asm, + X86FoldableSchedWrite sched> { +let hasSideEffects = 0, Predicates = [UseAVX] in { + def rr : SI, + Sched<[sched]>; + let mayLoad = 1 in + def rm : SI, + Sched<[sched.Folded, ReadAfterLd]>; +} // hasSideEffects = 0 +} + +let Predicates = [UseAVX] in { +defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32, + "cvttss2si\t{$src, $dst|$dst, $src}", + WriteCvtSS2I>, + XS, VEX, VEX_LIG; +defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32, + "cvttss2si\t{$src, $dst|$dst, $src}", + WriteCvtSS2I>, + XS, VEX, VEX_W, VEX_LIG; +defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64, + "cvttsd2si\t{$src, $dst|$dst, $src}", + WriteCvtSD2I>, + XD, VEX, VEX_LIG; +defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64, + "cvttsd2si\t{$src, $dst|$dst, $src}", + WriteCvtSD2I>, + XD, VEX, VEX_W, VEX_LIG; + +def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}", + (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0, "att">; +def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}", + (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0, "att">; +def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}", + (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0, "att">; +def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}", + (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0, "att">; +def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}", + (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0, "att">; +def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}", + (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0, "att">; +def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}", + (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0, "att">; +def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}", + (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0, "att">; +} +// The assembler can recognize rr 64-bit instructions by seeing a rxx +// register, but the same isn't true when only using memory operands, +// provide other assembly "l" and "q" forms to address this explicitly +// where appropriate to do so. +defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}", + WriteCvtI2SS>, XS, VEX_4V, VEX_LIG; +defm VCVTSI642SS : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}", + WriteCvtI2SS>, XS, VEX_4V, VEX_W, VEX_LIG; +defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}", + WriteCvtI2SD>, XD, VEX_4V, VEX_LIG; +defm VCVTSI642SD : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}", + WriteCvtI2SD>, XD, VEX_4V, VEX_W, VEX_LIG; + +let Predicates = [UseAVX] in { + def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}", + (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0, "att">; + def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}", + (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0, "att">; + + def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))), + (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>; + def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))), + (VCVTSI642SSrm (f32 (IMPLICIT_DEF)), addr:$src)>; + def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))), + (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>; + def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))), + (VCVTSI642SDrm (f64 (IMPLICIT_DEF)), addr:$src)>; + + def : Pat<(f32 (sint_to_fp GR32:$src)), + (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>; + def : Pat<(f32 (sint_to_fp GR64:$src)), + (VCVTSI642SSrr (f32 (IMPLICIT_DEF)), GR64:$src)>; + def : Pat<(f64 (sint_to_fp GR32:$src)), + (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>; + def : Pat<(f64 (sint_to_fp GR64:$src)), + (VCVTSI642SDrr (f64 (IMPLICIT_DEF)), GR64:$src)>; +} + +defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32, + "cvttss2si\t{$src, $dst|$dst, $src}", + WriteCvtSS2I>, XS; +defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32, + "cvttss2si\t{$src, $dst|$dst, $src}", + WriteCvtSS2I>, XS, REX_W; +defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64, + "cvttsd2si\t{$src, $dst|$dst, $src}", + WriteCvtSD2I>, XD; +defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64, + "cvttsd2si\t{$src, $dst|$dst, $src}", + WriteCvtSD2I>, XD, REX_W; +defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32, + "cvtsi2ss{l}\t{$src, $dst|$dst, $src}", + WriteCvtI2SS>, XS; +defm CVTSI642SS : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64, + "cvtsi2ss{q}\t{$src, $dst|$dst, $src}", + WriteCvtI2SS>, XS, REX_W; +defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32, + "cvtsi2sd{l}\t{$src, $dst|$dst, $src}", + WriteCvtI2SD>, XD; +defm CVTSI642SD : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64, + "cvtsi2sd{q}\t{$src, $dst|$dst, $src}", + WriteCvtI2SD>, XD, REX_W; + +def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}", + (CVTTSS2SIrr GR32:$dst, FR32:$src), 0, "att">; +def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}", + (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0, "att">; +def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}", + (CVTTSD2SIrr GR32:$dst, FR64:$src), 0, "att">; +def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}", + (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0, "att">; +def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}", + (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0, "att">; +def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}", + (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0, "att">; +def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}", + (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0, "att">; +def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}", + (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0, "att">; + +def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}", + (CVTSI2SSrm FR64:$dst, i32mem:$src), 0, "att">; +def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}", + (CVTSI2SDrm FR64:$dst, i32mem:$src), 0, "att">; + +// Conversion Instructions Intrinsics - Match intrinsics which expect MM +// and/or XMM operand(s). + +// FIXME: We probably want to match the rm form only when optimizing for +// size, to avoid false dependencies (see sse_fp_unop_s for details) +multiclass sse12_cvt_sint opc, RegisterClass SrcRC, RegisterClass DstRC, + Intrinsic Int, Operand memop, ComplexPattern mem_cpat, + string asm, X86FoldableSchedWrite sched> { + def rr_Int : SI, + Sched<[sched]>; + def rm_Int : SI, + Sched<[sched.Folded]>; +} + +multiclass sse12_cvt_sint_3addr opc, RegisterClass SrcRC, + RegisterClass DstRC, X86MemOperand x86memop, + string asm, X86FoldableSchedWrite sched, + bit Is2Addr = 1> { +let hasSideEffects = 0 in { + def rr_Int : SI, Sched<[sched]>; + let mayLoad = 1 in + def rm_Int : SI, Sched<[sched.Folded, ReadAfterLd]>; +} +} + +let Predicates = [UseAVX] in { +defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, + int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si", + WriteCvtSD2I>, XD, VEX, VEX_LIG; +defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, + int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si", + WriteCvtSD2I>, XD, VEX, VEX_W, VEX_LIG; +} +defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si, + sdmem, sse_load_f64, "cvtsd2si", WriteCvtSD2I>, XD; +defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64, + sdmem, sse_load_f64, "cvtsd2si", WriteCvtSD2I>, XD, REX_W; + + +let isCodeGenOnly = 1 in { + let Predicates = [UseAVX] in { + defm VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128, + i32mem, "cvtsi2ss{l}", WriteCvtI2SS, 0>, XS, VEX_4V; + defm VCVTSI642SS : sse12_cvt_sint_3addr<0x2A, GR64, VR128, + i64mem, "cvtsi2ss{q}", WriteCvtI2SS, 0>, XS, VEX_4V, VEX_W; + defm VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128, + i32mem, "cvtsi2sd{l}", WriteCvtI2SD, 0>, XD, VEX_4V; + defm VCVTSI642SD : sse12_cvt_sint_3addr<0x2A, GR64, VR128, + i64mem, "cvtsi2sd{q}", WriteCvtI2SD, 0>, XD, VEX_4V, VEX_W; + } + let Constraints = "$src1 = $dst" in { + defm CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128, + i32mem, "cvtsi2ss{l}", WriteCvtI2SS>, XS; + defm CVTSI642SS : sse12_cvt_sint_3addr<0x2A, GR64, VR128, + i64mem, "cvtsi2ss{q}", WriteCvtI2SS>, XS, REX_W; + defm CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128, + i32mem, "cvtsi2sd{l}", WriteCvtI2SD>, XD; + defm CVTSI642SD : sse12_cvt_sint_3addr<0x2A, GR64, VR128, + i64mem, "cvtsi2sd{q}", WriteCvtI2SD>, XD, REX_W; + } +} // isCodeGenOnly = 1 + +/// SSE 1 Only + +// Aliases for intrinsics +let isCodeGenOnly = 1 in { +let Predicates = [UseAVX] in { +defm VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si, + ssmem, sse_load_f32, "cvttss2si", + WriteCvtSS2I>, XS, VEX; +defm VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, + int_x86_sse_cvttss2si64, ssmem, sse_load_f32, + "cvttss2si", WriteCvtSS2I>, + XS, VEX, VEX_W; +defm VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si, + sdmem, sse_load_f64, "cvttsd2si", + WriteCvtSS2I>, XD, VEX; +defm VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, + int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64, + "cvttsd2si", WriteCvtSS2I>, + XD, VEX, VEX_W; +} +defm CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si, + ssmem, sse_load_f32, "cvttss2si", + WriteCvtSS2I>, XS; +defm CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, + int_x86_sse_cvttss2si64, ssmem, sse_load_f32, + "cvttss2si", WriteCvtSS2I>, XS, REX_W; +defm CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si, + sdmem, sse_load_f64, "cvttsd2si", + WriteCvtSD2I>, XD; +defm CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, + int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64, + "cvttsd2si", WriteCvtSD2I>, XD, REX_W; +} // isCodeGenOnly = 1 + +let Predicates = [UseAVX] in { +defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si, + ssmem, sse_load_f32, "cvtss2si", + WriteCvtSS2I>, XS, VEX, VEX_LIG; +defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64, + ssmem, sse_load_f32, "cvtss2si", + WriteCvtSS2I>, XS, VEX, VEX_W, VEX_LIG; +} +defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si, + ssmem, sse_load_f32, "cvtss2si", + WriteCvtSS2I>, XS; +defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64, + ssmem, sse_load_f32, "cvtss2si", + WriteCvtSS2I>, XS, REX_W; + +defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, i128mem, v4f32, v4i32, loadv2i64, + "vcvtdq2ps\t{$src, $dst|$dst, $src}", + SSEPackedSingle, WriteCvtI2PS>, + PS, VEX, Requires<[HasAVX, NoVLX]>, VEX_WIG; +defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, i256mem, v8f32, v8i32, loadv4i64, + "vcvtdq2ps\t{$src, $dst|$dst, $src}", + SSEPackedSingle, WriteCvtI2PSY>, + PS, VEX, VEX_L, Requires<[HasAVX, NoVLX]>, VEX_WIG; + +defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, i128mem, v4f32, v4i32, memopv2i64, + "cvtdq2ps\t{$src, $dst|$dst, $src}", + SSEPackedSingle, WriteCvtI2PS>, + PS, Requires<[UseSSE2]>; + +let Predicates = [UseAVX] in { +def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}", + (VCVTSS2SIrr_Int GR32:$dst, VR128:$src), 0, "att">; +def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}", + (VCVTSS2SIrm_Int GR32:$dst, ssmem:$src), 0, "att">; +def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}", + (VCVTSD2SIrr_Int GR32:$dst, VR128:$src), 0, "att">; +def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}", + (VCVTSD2SIrm_Int GR32:$dst, sdmem:$src), 0, "att">; +def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}", + (VCVTSS2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">; +def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}", + (VCVTSS2SI64rm_Int GR64:$dst, ssmem:$src), 0, "att">; +def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}", + (VCVTSD2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">; +def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}", + (VCVTSD2SI64rm_Int GR64:$dst, sdmem:$src), 0, "att">; +} + +def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}", + (CVTSS2SIrr_Int GR32:$dst, VR128:$src), 0, "att">; +def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}", + (CVTSS2SIrm_Int GR32:$dst, ssmem:$src), 0, "att">; +def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}", + (CVTSD2SIrr_Int GR32:$dst, VR128:$src), 0, "att">; +def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}", + (CVTSD2SIrm_Int GR32:$dst, sdmem:$src), 0, "att">; +def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}", + (CVTSS2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">; +def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}", + (CVTSS2SI64rm_Int GR64:$dst, ssmem:$src), 0, "att">; +def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}", + (CVTSD2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">; +def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}", + (CVTSD2SI64rm_Int GR64:$dst, sdmem:$src), 0, "att">; + +/// SSE 2 Only + +// Convert scalar double to scalar single +let hasSideEffects = 0, Predicates = [UseAVX] in { +def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst), + (ins FR32:$src1, FR64:$src2), + "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + VEX_4V, VEX_LIG, VEX_WIG, + Sched<[WriteCvtSD2SS]>; +let mayLoad = 1 in +def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), + (ins FR32:$src1, f64mem:$src2), + "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + XD, VEX_4V, VEX_LIG, VEX_WIG, + Sched<[WriteCvtSD2SS.Folded, ReadAfterLd]>; +} + +def : Pat<(f32 (fpround FR64:$src)), + (VCVTSD2SSrr (f32 (IMPLICIT_DEF)), FR64:$src)>, + Requires<[UseAVX]>; + +def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src), + "cvtsd2ss\t{$src, $dst|$dst, $src}", + [(set FR32:$dst, (fpround FR64:$src))]>, + Sched<[WriteCvtSD2SS]>; +def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src), + "cvtsd2ss\t{$src, $dst|$dst, $src}", + [(set FR32:$dst, (fpround (loadf64 addr:$src)))]>, + XD, Requires<[UseSSE2, OptForSize]>, + Sched<[WriteCvtSD2SS.Folded]>; + +let isCodeGenOnly = 1 in { +def VCVTSD2SSrr_Int: I<0x5A, MRMSrcReg, + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), + "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))]>, + XD, VEX_4V, VEX_WIG, Requires<[HasAVX]>, + Sched<[WriteCvtSD2SS]>; +def VCVTSD2SSrm_Int: I<0x5A, MRMSrcMem, + (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2), + "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, (int_x86_sse2_cvtsd2ss + VR128:$src1, sse_load_f64:$src2))]>, + XD, VEX_4V, VEX_WIG, Requires<[HasAVX]>, + Sched<[WriteCvtSD2SS.Folded, ReadAfterLd]>; +let Constraints = "$src1 = $dst" in { +def CVTSD2SSrr_Int: I<0x5A, MRMSrcReg, + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), + "cvtsd2ss\t{$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))]>, + XD, Requires<[UseSSE2]>, Sched<[WriteCvtSD2SS]>; +def CVTSD2SSrm_Int: I<0x5A, MRMSrcMem, + (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2), + "cvtsd2ss\t{$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_cvtsd2ss + VR128:$src1, sse_load_f64:$src2))]>, + XD, Requires<[UseSSE2]>, + Sched<[WriteCvtSD2SS.Folded, ReadAfterLd]>; +} +} // isCodeGenOnly = 1 + +// Convert scalar single to scalar double +// SSE2 instructions with XS prefix +let hasSideEffects = 0 in { +def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), + (ins FR64:$src1, FR32:$src2), + "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + XS, VEX_4V, VEX_LIG, VEX_WIG, + Sched<[WriteCvtSS2SD]>, Requires<[UseAVX]>; +let mayLoad = 1 in +def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), + (ins FR64:$src1, f32mem:$src2), + "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + XS, VEX_4V, VEX_LIG, VEX_WIG, + Sched<[WriteCvtSS2SD.Folded, ReadAfterLd]>, + Requires<[UseAVX, OptForSize]>; +} + +def : Pat<(f64 (fpextend FR32:$src)), + (VCVTSS2SDrr (f64 (IMPLICIT_DEF)), FR32:$src)>, Requires<[UseAVX]>; +def : Pat<(fpextend (loadf32 addr:$src)), + (VCVTSS2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX, OptForSize]>; + +def : Pat<(extloadf32 addr:$src), + (VCVTSS2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>, + Requires<[UseAVX, OptForSize]>; +def : Pat<(extloadf32 addr:$src), + (VCVTSS2SDrr (f64 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>, + Requires<[UseAVX, OptForSpeed]>; + +def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src), + "cvtss2sd\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (fpextend FR32:$src))]>, + XS, Requires<[UseSSE2]>, Sched<[WriteCvtSS2SD]>; +def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src), + "cvtss2sd\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (extloadf32 addr:$src))]>, + XS, Requires<[UseSSE2, OptForSize]>, + Sched<[WriteCvtSS2SD.Folded]>; + +// extload f32 -> f64. This matches load+fpextend because we have a hack in +// the isel (PreprocessForFPConvert) that can introduce loads after dag +// combine. +// Since these loads aren't folded into the fpextend, we have to match it +// explicitly here. +def : Pat<(fpextend (loadf32 addr:$src)), + (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2, OptForSize]>; +def : Pat<(extloadf32 addr:$src), + (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>; + +let isCodeGenOnly = 1, hasSideEffects = 0 in { +def VCVTSS2SDrr_Int: I<0x5A, MRMSrcReg, + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), + "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, XS, VEX_4V, VEX_WIG, + Requires<[HasAVX]>, Sched<[WriteCvtSS2SD]>; +let mayLoad = 1 in +def VCVTSS2SDrm_Int: I<0x5A, MRMSrcMem, + (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2), + "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, XS, VEX_4V, VEX_WIG, Requires<[HasAVX]>, + Sched<[WriteCvtSS2SD.Folded, ReadAfterLd]>; +let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix +def CVTSS2SDrr_Int: I<0x5A, MRMSrcReg, + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), + "cvtss2sd\t{$src2, $dst|$dst, $src2}", + []>, XS, Requires<[UseSSE2]>, + Sched<[WriteCvtSS2SD]>; +let mayLoad = 1 in +def CVTSS2SDrm_Int: I<0x5A, MRMSrcMem, + (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2), + "cvtss2sd\t{$src2, $dst|$dst, $src2}", + []>, XS, Requires<[UseSSE2]>, + Sched<[WriteCvtSS2SD.Folded, ReadAfterLd]>; +} +} // isCodeGenOnly = 1 + +// Patterns used for matching (v)cvtsi2ss, (v)cvtsi2sd, (v)cvtsd2ss and +// (v)cvtss2sd intrinsic sequences from clang which produce unnecessary +// vmovs{s,d} instructions +let Predicates = [UseAVX] in { +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector + (f32 (fpround (f64 (extractelt VR128:$src, (iPTR 0))))))))), + (VCVTSD2SSrr_Int VR128:$dst, VR128:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector + (f64 (fpextend (f32 (extractelt VR128:$src, (iPTR 0))))))))), + (VCVTSS2SDrr_Int VR128:$dst, VR128:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp GR64:$src)))))), + (VCVTSI642SSrr_Int VR128:$dst, GR64:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi64 addr:$src))))))), + (VCVTSI642SSrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp GR32:$src)))))), + (VCVTSI2SSrr_Int VR128:$dst, GR32:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi32 addr:$src))))))), + (VCVTSI2SSrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp GR64:$src)))))), + (VCVTSI642SDrr_Int VR128:$dst, GR64:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi64 addr:$src))))))), + (VCVTSI642SDrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp GR32:$src)))))), + (VCVTSI2SDrr_Int VR128:$dst, GR32:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi32 addr:$src))))))), + (VCVTSI2SDrm_Int VR128:$dst, addr:$src)>; +} // Predicates = [UseAVX] + +let Predicates = [UseSSE2] in { +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector + (f32 (fpround (f64 (extractelt VR128:$src, (iPTR 0))))))))), + (CVTSD2SSrr_Int VR128:$dst, VR128:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector + (f64 (fpextend (f32 (extractelt VR128:$src, (iPTR 0))))))))), + (CVTSS2SDrr_Int VR128:$dst, VR128:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp GR64:$src)))))), + (CVTSI642SDrr_Int VR128:$dst, GR64:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi64 addr:$src))))))), + (CVTSI642SDrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp GR32:$src)))))), + (CVTSI2SDrr_Int VR128:$dst, GR32:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi32 addr:$src))))))), + (CVTSI2SDrm_Int VR128:$dst, addr:$src)>; +} // Predicates = [UseSSE2] + +let Predicates = [UseSSE1] in { +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp GR64:$src)))))), + (CVTSI642SSrr_Int VR128:$dst, GR64:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi64 addr:$src))))))), + (CVTSI642SSrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp GR32:$src)))))), + (CVTSI2SSrr_Int VR128:$dst, GR32:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi32 addr:$src))))))), + (CVTSI2SSrm_Int VR128:$dst, addr:$src)>; +} // Predicates = [UseSSE1] + +let Predicates = [HasAVX, NoVLX] in { +// Convert packed single/double fp to doubleword +def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v4i32 (X86cvtp2Int (v4f32 VR128:$src))))]>, + VEX, Sched<[WriteCvtPS2I]>, VEX_WIG; +def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (loadv4f32 addr:$src))))]>, + VEX, Sched<[WriteCvtPS2ILd]>, VEX_WIG; +def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, + (v8i32 (X86cvtp2Int (v8f32 VR256:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPS2IY]>, VEX_WIG; +def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, + (v8i32 (X86cvtp2Int (loadv8f32 addr:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPS2IYLd]>, VEX_WIG; +} +def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v4i32 (X86cvtp2Int (v4f32 VR128:$src))))]>, + Sched<[WriteCvtPS2I]>; +def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (memopv4f32 addr:$src))))]>, + Sched<[WriteCvtPS2ILd]>; + + +// Convert Packed Double FP to Packed DW Integers +let Predicates = [HasAVX, NoVLX] in { +// The assembler can recognize rr 256-bit instructions by seeing a ymm +// register, but the same isn't true when using memory operands instead. +// Provide other assembly rr and rm forms to address this explicitly. +def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "vcvtpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (v2f64 VR128:$src))))]>, + VEX, Sched<[WriteCvtPD2I]>, VEX_WIG; + +// XMM only +def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}", + (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>; +def VCVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "vcvtpd2dq{x}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (loadv2f64 addr:$src))))]>, VEX, + Sched<[WriteCvtPD2ILd]>, VEX_WIG; +def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}", + (VCVTPD2DQrm VR128:$dst, f128mem:$src), 0, "intel">; + +// YMM only +def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), + "vcvtpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (v4f64 VR256:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPD2IY]>, VEX_WIG; +def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), + "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (loadv4f64 addr:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPD2IYLd]>, VEX_WIG; +def : InstAlias<"vcvtpd2dqy\t{$src, $dst|$dst, $src}", + (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>; +def : InstAlias<"vcvtpd2dqy\t{$src, $dst|$dst, $src}", + (VCVTPD2DQYrm VR128:$dst, f256mem:$src), 0, "intel">; +} + +def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvtpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (memopv2f64 addr:$src))))]>, + Sched<[WriteCvtPD2ILd]>; +def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvtp2Int (v2f64 VR128:$src))))]>, + Sched<[WriteCvtPD2I]>; + +// Convert with truncation packed single/double fp to doubleword +// SSE2 packed instructions with XS prefix +let Predicates = [HasAVX, NoVLX] in { +def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (v4f32 VR128:$src))))]>, + VEX, Sched<[WriteCvtPS2I]>, VEX_WIG; +def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (loadv4f32 addr:$src))))]>, + VEX, Sched<[WriteCvtPS2ILd]>, VEX_WIG; +def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, + (v8i32 (X86cvttp2si (v8f32 VR256:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPS2IY]>, VEX_WIG; +def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, + (v8i32 (X86cvttp2si (loadv8f32 addr:$src))))]>, + VEX, VEX_L, + Sched<[WriteCvtPS2IYLd]>, VEX_WIG; +} + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))), + (VCVTTPS2DQrr VR128:$src)>; + def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))), + (VCVTTPS2DQrm addr:$src)>; + def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))), + (VCVTTPS2DQYrr VR256:$src)>; + def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))), + (VCVTTPS2DQYrm addr:$src)>; +} + +def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (v4f32 VR128:$src))))]>, + Sched<[WriteCvtPS2I]>; +def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (memopv4f32 addr:$src))))]>, + Sched<[WriteCvtPS2ILd]>; + +let Predicates = [UseSSE2] in { + def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))), + (CVTTPS2DQrr VR128:$src)>; + def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))), + (CVTTPS2DQrm addr:$src)>; +} + +let Predicates = [HasAVX, NoVLX] in +def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvttpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (v2f64 VR128:$src))))]>, + VEX, Sched<[WriteCvtPD2I]>, VEX_WIG; + +// The assembler can recognize rr 256-bit instructions by seeing a ymm +// register, but the same isn't true when using memory operands instead. +// Provide other assembly rr and rm forms to address this explicitly. + +// XMM only +def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}", + (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>; + +let Predicates = [HasAVX, NoVLX] in +def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvttpd2dq{x}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (loadv2f64 addr:$src))))]>, + VEX, Sched<[WriteCvtPD2ILd]>, VEX_WIG; +def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}", + (VCVTTPD2DQrm VR128:$dst, f128mem:$src), 0, "intel">; + +// YMM only +let Predicates = [HasAVX, NoVLX] in { +def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), + "cvttpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (v4f64 VR256:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPD2IY]>, VEX_WIG; +def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), + "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (loadv4f64 addr:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtPD2IYLd]>, VEX_WIG; +} +def : InstAlias<"vcvttpd2dqy\t{$src, $dst|$dst, $src}", + (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>; +def : InstAlias<"vcvttpd2dqy\t{$src, $dst|$dst, $src}", + (VCVTTPD2DQYrm VR128:$dst, f256mem:$src), 0, "intel">; + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))), + (VCVTTPD2DQYrr VR256:$src)>; + def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))), + (VCVTTPD2DQYrm addr:$src)>; +} + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))), + (VCVTPD2DQrr VR128:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2Int (loadv2f64 addr:$src)))))), + (VCVTPD2DQrm addr:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2si (v2f64 VR128:$src)))))), + (VCVTTPD2DQrr VR128:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2si (loadv2f64 addr:$src)))))), + (VCVTTPD2DQrm addr:$src)>; +} // Predicates = [HasAVX, NoVLX] + +def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvttpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (v2f64 VR128:$src))))]>, + Sched<[WriteCvtPD2I]>; +def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src), + "cvttpd2dq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86cvttp2si (memopv2f64 addr:$src))))]>, + Sched<[WriteCvtPD2ILd]>; + +let Predicates = [UseSSE2] in { + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))), + (CVTPD2DQrr VR128:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvtp2Int (memopv2f64 addr:$src)))))), + (CVTPD2DQrm addr:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2si (v2f64 VR128:$src)))))), + (CVTTPD2DQrr VR128:$src)>; + def : Pat<(X86vzmovl (v2i64 (bitconvert + (v4i32 (X86cvttp2si (memopv2f64 addr:$src)))))), + (CVTTPD2DQrm addr:$src)>; +} // Predicates = [UseSSE2] + +// Convert packed single to packed double +let Predicates = [HasAVX, NoVLX] in { + // SSE2 instructions without OpSize prefix +def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "vcvtps2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2f64 (X86vfpext (v4f32 VR128:$src))))]>, + PS, VEX, Sched<[WriteCvtPS2PD]>, VEX_WIG; +def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), + "vcvtps2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))]>, + PS, VEX, Sched<[WriteCvtPS2PD.Folded]>, VEX_WIG; +def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src), + "vcvtps2pd\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, (v4f64 (fpextend (v4f32 VR128:$src))))]>, + PS, VEX, VEX_L, Sched<[WriteCvtPS2PDY]>, VEX_WIG; +def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src), + "vcvtps2pd\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, (v4f64 (extloadv4f32 addr:$src)))]>, + PS, VEX, VEX_L, Sched<[WriteCvtPS2PDY.Folded]>, VEX_WIG; +} + +let Predicates = [UseSSE2] in { +def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtps2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2f64 (X86vfpext (v4f32 VR128:$src))))]>, + PS, Sched<[WriteCvtPS2PD]>; +def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), + "cvtps2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))]>, + PS, Sched<[WriteCvtPS2PD.Folded]>; +} + +// Convert Packed DW Integers to Packed Double FP +let Predicates = [HasAVX, NoVLX] in { +let hasSideEffects = 0, mayLoad = 1 in +def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), + "vcvtdq2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2f64 (X86VSintToFP (bc_v4i32 (loadv2i64 addr:$src)))))]>, + VEX, Sched<[WriteCvtI2PDLd]>, VEX_WIG; +def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "vcvtdq2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2f64 (X86VSintToFP (v4i32 VR128:$src))))]>, + VEX, Sched<[WriteCvtI2PD]>, VEX_WIG; +def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src), + "vcvtdq2pd\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, + (v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))))]>, + VEX, VEX_L, Sched<[WriteCvtI2PDYLd]>, + VEX_WIG; +def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src), + "vcvtdq2pd\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, + (v4f64 (sint_to_fp (v4i32 VR128:$src))))]>, + VEX, VEX_L, Sched<[WriteCvtI2PDY]>, VEX_WIG; +} + +let hasSideEffects = 0, mayLoad = 1 in +def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), + "cvtdq2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2f64 (X86VSintToFP (bc_v4i32 (loadv2i64 addr:$src)))))]>, + Sched<[WriteCvtI2PDLd]>; +def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtdq2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2f64 (X86VSintToFP (v4i32 VR128:$src))))]>, + Sched<[WriteCvtI2PD]>; + +// AVX register conversion intrinsics +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (VCVTDQ2PDrm addr:$src)>; + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (X86vzload addr:$src))))), + (VCVTDQ2PDrm addr:$src)>; +} // Predicates = [HasAVX, NoVLX] + +// SSE2 register conversion intrinsics +let Predicates = [UseSSE2] in { + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (CVTDQ2PDrm addr:$src)>; + def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (X86vzload addr:$src))))), + (CVTDQ2PDrm addr:$src)>; +} // Predicates = [UseSSE2] + +// Convert packed double to packed single +// The assembler can recognize rr 256-bit instructions by seeing a ymm +// register, but the same isn't true when using memory operands instead. +// Provide other assembly rr and rm forms to address this explicitly. +let Predicates = [HasAVX, NoVLX] in +def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtpd2ps\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (X86vfpround (v2f64 VR128:$src)))]>, + VEX, Sched<[WriteCvtPD2PS]>, VEX_WIG; + +// XMM only +def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}", + (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>; +let Predicates = [HasAVX, NoVLX] in +def VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvtpd2ps{x}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (X86vfpround (loadv2f64 addr:$src)))]>, + VEX, Sched<[WriteCvtPD2PS.Folded]>, VEX_WIG; +def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}", + (VCVTPD2PSrm VR128:$dst, f128mem:$src), 0, "intel">; + +// YMM only +let Predicates = [HasAVX, NoVLX] in { +def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), + "cvtpd2ps\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (fpround VR256:$src))]>, + VEX, VEX_L, Sched<[WriteCvtPD2PSY]>, VEX_WIG; +def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), + "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (fpround (loadv4f64 addr:$src)))]>, + VEX, VEX_L, Sched<[WriteCvtPD2PSY.Folded]>, VEX_WIG; +} +def : InstAlias<"vcvtpd2psy\t{$src, $dst|$dst, $src}", + (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>; +def : InstAlias<"vcvtpd2psy\t{$src, $dst|$dst, $src}", + (VCVTPD2PSYrm VR128:$dst, f256mem:$src), 0, "intel">; + +def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtpd2ps\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (X86vfpround (v2f64 VR128:$src)))]>, + Sched<[WriteCvtPD2PS]>; +def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvtpd2ps\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (X86vfpround (memopv2f64 addr:$src)))]>, + Sched<[WriteCvtPD2PS.Folded]>; + +// AVX 256-bit register conversion intrinsics +// FIXME: Migrate SSE conversion intrinsics matching to use patterns as below +// whenever possible to avoid declaring two versions of each one. + +let Predicates = [HasAVX, NoVLX] in { + // Match fpround and fpextend for 128/256-bit conversions + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86vfpround (v2f64 VR128:$src)))))), + (VCVTPD2PSrr VR128:$src)>; + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86vfpround (loadv2f64 addr:$src)))))), + (VCVTPD2PSrm addr:$src)>; +} + +let Predicates = [UseSSE2] in { + // Match fpround and fpextend for 128 conversions + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86vfpround (v2f64 VR128:$src)))))), + (CVTPD2PSrr VR128:$src)>; + def : Pat<(X86vzmovl (v2f64 (bitconvert + (v4f32 (X86vfpround (memopv2f64 addr:$src)))))), + (CVTPD2PSrm addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Compare Instructions +//===----------------------------------------------------------------------===// + +// sse12_cmp_scalar - sse 1 & 2 compare scalar instructions +multiclass sse12_cmp_scalar { + let isCommutable = 1 in + def rr : SIi8<0xC2, MRMSrcReg, + (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, + [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>, + Sched<[sched]>; + def rm : SIi8<0xC2, MRMSrcMem, + (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, + [(set RC:$dst, (OpNode (VT RC:$src1), + (ld_frag addr:$src2), imm:$cc))]>, + Sched<[sched.Folded, ReadAfterLd]>; + + // Accept explicit immediate argument form instead of comparison code. + let isAsmParserOnly = 1, hasSideEffects = 0 in { + def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst), + (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, []>, + Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in + def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst), + (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, []>, + Sched<[sched.Folded, ReadAfterLd]>, NotMemoryFoldable; + } +} + +let ExeDomain = SSEPackedSingle in +defm VCMPSS : sse12_cmp_scalar, XS, VEX_4V, VEX_LIG, VEX_WIG; +let ExeDomain = SSEPackedDouble in +defm VCMPSD : sse12_cmp_scalar, + XD, VEX_4V, VEX_LIG, VEX_WIG; + +let Constraints = "$src1 = $dst" in { + let ExeDomain = SSEPackedSingle in + defm CMPSS : sse12_cmp_scalar, XS; + let ExeDomain = SSEPackedDouble in + defm CMPSD : sse12_cmp_scalar, XD; +} + +multiclass sse12_cmp_scalar_int { + def rr_Int : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src, CC:$cc), asm, + [(set VR128:$dst, (Int VR128:$src1, + VR128:$src, imm:$cc))]>, + Sched<[sched]>; +let mayLoad = 1 in + def rm_Int : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, memop:$src, CC:$cc), asm, + [(set VR128:$dst, (Int VR128:$src1, + mem_cpat:$src, imm:$cc))]>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let isCodeGenOnly = 1 in { + // Aliases to match intrinsics which expect XMM operand(s). + let ExeDomain = SSEPackedSingle in + defm VCMPSS : sse12_cmp_scalar_int, XS, VEX_4V; + let ExeDomain = SSEPackedDouble in + defm VCMPSD : sse12_cmp_scalar_int, + XD, VEX_4V; + let Constraints = "$src1 = $dst" in { + let ExeDomain = SSEPackedSingle in + defm CMPSS : sse12_cmp_scalar_int, XS; + let ExeDomain = SSEPackedDouble in + defm CMPSD : sse12_cmp_scalar_int, XD; +} +} + + +// sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS +multiclass sse12_ord_cmp opc, RegisterClass RC, SDNode OpNode, + ValueType vt, X86MemOperand x86memop, + PatFrag ld_frag, string OpcodeStr, + X86FoldableSchedWrite sched> { +let hasSideEffects = 0 in { + def rr: SI, + Sched<[sched]>; +let mayLoad = 1 in + def rm: SI, + Sched<[sched.Folded, ReadAfterLd]>; +} +} + +// sse12_ord_cmp_int - Intrinsic version of sse12_ord_cmp +multiclass sse12_ord_cmp_int opc, RegisterClass RC, SDNode OpNode, + ValueType vt, Operand memop, + ComplexPattern mem_cpat, string OpcodeStr, + X86FoldableSchedWrite sched> { + def rr_Int: SI, + Sched<[sched]>; +let mayLoad = 1 in + def rm_Int: SI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Defs = [EFLAGS] in { + defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32, + "ucomiss", WriteFCom>, PS, VEX, VEX_LIG, VEX_WIG; + defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, + "ucomisd", WriteFCom>, PD, VEX, VEX_LIG, VEX_WIG; + let Pattern = [] in { + defm VCOMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32, + "comiss", WriteFCom>, PS, VEX, VEX_LIG, VEX_WIG; + defm VCOMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64, + "comisd", WriteFCom>, PD, VEX, VEX_LIG, VEX_WIG; + } + + let isCodeGenOnly = 1 in { + defm VUCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem, + sse_load_f32, "ucomiss", WriteFCom>, PS, VEX, VEX_WIG; + defm VUCOMISD : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v2f64, sdmem, + sse_load_f64, "ucomisd", WriteFCom>, PD, VEX, VEX_WIG; + + defm VCOMISS : sse12_ord_cmp_int<0x2F, VR128, X86comi, v4f32, ssmem, + sse_load_f32, "comiss", WriteFCom>, PS, VEX, VEX_WIG; + defm VCOMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem, + sse_load_f64, "comisd", WriteFCom>, PD, VEX, VEX_WIG; + } + defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32, + "ucomiss", WriteFCom>, PS; + defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, + "ucomisd", WriteFCom>, PD; + + let Pattern = [] in { + defm COMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32, + "comiss", WriteFCom>, PS; + defm COMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64, + "comisd", WriteFCom>, PD; + } + + let isCodeGenOnly = 1 in { + defm UCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem, + sse_load_f32, "ucomiss", WriteFCom>, PS; + defm UCOMISD : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v2f64, sdmem, + sse_load_f64, "ucomisd", WriteFCom>, PD; + + defm COMISS : sse12_ord_cmp_int<0x2F, VR128, X86comi, v4f32, ssmem, + sse_load_f32, "comiss", WriteFCom>, PS; + defm COMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem, + sse_load_f64, "comisd", WriteFCom>, PD; + } +} // Defs = [EFLAGS] + +// sse12_cmp_packed - sse 1 & 2 compare packed instructions +multiclass sse12_cmp_packed { + let isCommutable = 1 in + def rri : PIi8<0xC2, MRMSrcReg, + (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, + [(set RC:$dst, (VT (X86cmpp RC:$src1, RC:$src2, imm:$cc)))], d>, + Sched<[sched]>; + def rmi : PIi8<0xC2, MRMSrcMem, + (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, + [(set RC:$dst, + (VT (X86cmpp RC:$src1, (ld_frag addr:$src2), imm:$cc)))], d>, + Sched<[sched.Folded, ReadAfterLd]>; + + // Accept explicit immediate argument form instead of comparison code. + let isAsmParserOnly = 1, hasSideEffects = 0 in { + def rri_alt : PIi8<0xC2, MRMSrcReg, + (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc), + asm_alt, [], d>, Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in + def rmi_alt : PIi8<0xC2, MRMSrcMem, + (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc), + asm_alt, [], d>, Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + } +} + +defm VCMPPS : sse12_cmp_packed, PS, VEX_4V, VEX_WIG; +defm VCMPPD : sse12_cmp_packed, PD, VEX_4V, VEX_WIG; +defm VCMPPSY : sse12_cmp_packed, PS, VEX_4V, VEX_L, VEX_WIG; +defm VCMPPDY : sse12_cmp_packed, PD, VEX_4V, VEX_L, VEX_WIG; +let Constraints = "$src1 = $dst" in { + defm CMPPS : sse12_cmp_packed, PS; + defm CMPPD : sse12_cmp_packed, PD; +} + +def CommutableCMPCC : PatLeaf<(imm), [{ + uint64_t Imm = N->getZExtValue() & 0x7; + return (Imm == 0x00 || Imm == 0x03 || Imm == 0x04 || Imm == 0x07); +}]>; + +// Patterns to select compares with loads in first operand. +let Predicates = [HasAVX] in { + def : Pat<(v4f64 (X86cmpp (loadv4f64 addr:$src2), VR256:$src1, + CommutableCMPCC:$cc)), + (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(v8f32 (X86cmpp (loadv8f32 addr:$src2), VR256:$src1, + CommutableCMPCC:$cc)), + (VCMPPSYrmi VR256:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(v2f64 (X86cmpp (loadv2f64 addr:$src2), VR128:$src1, + CommutableCMPCC:$cc)), + (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(v4f32 (X86cmpp (loadv4f32 addr:$src2), VR128:$src1, + CommutableCMPCC:$cc)), + (VCMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(f64 (X86cmps (loadf64 addr:$src2), FR64:$src1, + CommutableCMPCC:$cc)), + (VCMPSDrm FR64:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(f32 (X86cmps (loadf32 addr:$src2), FR32:$src1, + CommutableCMPCC:$cc)), + (VCMPSSrm FR32:$src1, addr:$src2, imm:$cc)>; +} + +let Predicates = [UseSSE2] in { + def : Pat<(v2f64 (X86cmpp (memopv2f64 addr:$src2), VR128:$src1, + CommutableCMPCC:$cc)), + (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(f64 (X86cmps (loadf64 addr:$src2), FR64:$src1, + CommutableCMPCC:$cc)), + (CMPSDrm FR64:$src1, addr:$src2, imm:$cc)>; +} + +let Predicates = [UseSSE1] in { + def : Pat<(v4f32 (X86cmpp (memopv4f32 addr:$src2), VR128:$src1, + CommutableCMPCC:$cc)), + (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>; + + def : Pat<(f32 (X86cmps (loadf32 addr:$src2), FR32:$src1, + CommutableCMPCC:$cc)), + (CMPSSrm FR32:$src1, addr:$src2, imm:$cc)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Shuffle Instructions +//===----------------------------------------------------------------------===// + +/// sse12_shuffle - sse 1 & 2 fp shuffle instructions +multiclass sse12_shuffle { + def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst), + (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm, + [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2), + (i8 imm:$src3))))], d>, + Sched<[sched.Folded, ReadAfterLd]>; + def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst), + (ins RC:$src1, RC:$src2, u8imm:$src3), asm, + [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2, + (i8 imm:$src3))))], d>, + Sched<[sched]>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm VSHUFPS : sse12_shuffle, + PS, VEX_4V, VEX_WIG; + defm VSHUFPSY : sse12_shuffle, + PS, VEX_4V, VEX_L, VEX_WIG; + defm VSHUFPD : sse12_shuffle, + PD, VEX_4V, VEX_WIG; + defm VSHUFPDY : sse12_shuffle, + PD, VEX_4V, VEX_L, VEX_WIG; +} +let Constraints = "$src1 = $dst" in { + defm SHUFPS : sse12_shuffle, PS; + defm SHUFPD : sse12_shuffle, PD; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Unpack FP Instructions +//===----------------------------------------------------------------------===// + +/// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave +multiclass sse12_unpack_interleave opc, SDNode OpNode, ValueType vt, + PatFrag mem_frag, RegisterClass RC, + X86MemOperand x86memop, string asm, + X86FoldableSchedWrite sched, Domain d, + bit IsCommutable = 0> { + let isCommutable = IsCommutable in + def rr : PI, + Sched<[sched]>; + def rm : PI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoVLX] in { +defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32, + VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.XMM, SSEPackedSingle>, PS, VEX_4V, VEX_WIG; +defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64, + VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.XMM, SSEPackedDouble, 1>, PD, VEX_4V, VEX_WIG; +defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32, + VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.XMM, SSEPackedSingle>, PS, VEX_4V, VEX_WIG; +defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64, + VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.XMM, SSEPackedDouble>, PD, VEX_4V, VEX_WIG; + +defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32, + VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.YMM, SSEPackedSingle>, PS, VEX_4V, VEX_L, VEX_WIG; +defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64, + VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.YMM, SSEPackedDouble>, PD, VEX_4V, VEX_L, VEX_WIG; +defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32, + VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.YMM, SSEPackedSingle>, PS, VEX_4V, VEX_L, VEX_WIG; +defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64, + VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + SchedWriteFShuffle.YMM, SSEPackedDouble>, PD, VEX_4V, VEX_L, VEX_WIG; +}// Predicates = [HasAVX, NoVLX] + +let Constraints = "$src1 = $dst" in { + defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32, + VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}", + SchedWriteFShuffle.XMM, SSEPackedSingle>, PS; + defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64, + VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}", + SchedWriteFShuffle.XMM, SSEPackedDouble, 1>, PD; + defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32, + VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}", + SchedWriteFShuffle.XMM, SSEPackedSingle>, PS; + defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64, + VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}", + SchedWriteFShuffle.XMM, SSEPackedDouble>, PD; +} // Constraints = "$src1 = $dst" + +let Predicates = [HasAVX1Only] in { + def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))), + (VUNPCKLPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)), + (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))), + (VUNPCKHPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)), + (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>; + + def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))), + (VUNPCKLPDYrm VR256:$src1, addr:$src2)>; + def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)), + (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))), + (VUNPCKHPDYrm VR256:$src1, addr:$src2)>; + def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)), + (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Extract Floating-Point Sign mask +//===----------------------------------------------------------------------===// + +/// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave +multiclass sse12_extr_sign_mask { + def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src), + !strconcat(asm, "\t{$src, $dst|$dst, $src}"), + [(set GR32orGR64:$dst, (X86movmsk (vt RC:$src)))], d>, + Sched<[WriteFMOVMSK]>; +} + +let Predicates = [HasAVX] in { + defm VMOVMSKPS : sse12_extr_sign_mask, PS, VEX, VEX_WIG; + defm VMOVMSKPD : sse12_extr_sign_mask, PD, VEX, VEX_WIG; + defm VMOVMSKPSY : sse12_extr_sign_mask, PS, VEX, VEX_L, VEX_WIG; + defm VMOVMSKPDY : sse12_extr_sign_mask, PD, VEX, VEX_L, VEX_WIG; +} + +defm MOVMSKPS : sse12_extr_sign_mask, PS; +defm MOVMSKPD : sse12_extr_sign_mask, PD; + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Logical Instructions +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { // SSE integer instructions + +/// PDI_binop_rm - Simple SSE2 binary operator. +multiclass PDI_binop_rm opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT, RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, X86FoldableSchedWrite sched, + bit IsCommutable, bit Is2Addr> { + let isCommutable = IsCommutable in + def rr : PDI, + Sched<[sched]>; + def rm : PDI, + Sched<[sched.Folded, ReadAfterLd]>; +} +} // ExeDomain = SSEPackedInt + +multiclass PDI_binop_all opc, string OpcodeStr, SDNode Opcode, + ValueType OpVT128, ValueType OpVT256, + X86SchedWriteWidths sched, bit IsCommutable, + Predicate prd> { +let Predicates = [HasAVX, prd] in + defm V#NAME : PDI_binop_rm, VEX_4V, VEX_WIG; + +let Constraints = "$src1 = $dst" in + defm NAME : PDI_binop_rm; + +let Predicates = [HasAVX2, prd] in + defm V#NAME#Y : PDI_binop_rm, VEX_4V, VEX_L, VEX_WIG; +} + +// These are ordered here for pattern ordering requirements with the fp versions + +defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, + SchedWriteVecLogic, 1, NoVLX>; +defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, + SchedWriteVecLogic, 1, NoVLX>; +defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, + SchedWriteVecLogic, 1, NoVLX>; +defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64, + SchedWriteVecLogic, 0, NoVLX>; + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Logical Instructions +//===----------------------------------------------------------------------===// + +/// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops +/// +/// There are no patterns here because isel prefers integer versions for SSE2 +/// and later. There are SSE1 v4f32 patterns later. +multiclass sse12_fp_packed_logical opc, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched> { + let Predicates = [HasAVX, NoVLX] in { + defm V#NAME#PSY : sse12_fp_packed_logical_rm, PS, VEX_4V, VEX_L, VEX_WIG; + + defm V#NAME#PDY : sse12_fp_packed_logical_rm, PD, VEX_4V, VEX_L, VEX_WIG; + + defm V#NAME#PS : sse12_fp_packed_logical_rm, PS, VEX_4V, VEX_WIG; + + defm V#NAME#PD : sse12_fp_packed_logical_rm, PD, VEX_4V, VEX_WIG; + } + + let Constraints = "$src1 = $dst" in { + defm PS : sse12_fp_packed_logical_rm, PS; + + defm PD : sse12_fp_packed_logical_rm, PD; + } +} + +defm AND : sse12_fp_packed_logical<0x54, "and", and, SchedWriteFLogic>; +defm OR : sse12_fp_packed_logical<0x56, "or", or, SchedWriteFLogic>; +defm XOR : sse12_fp_packed_logical<0x57, "xor", xor, SchedWriteFLogic>; +let isCommutable = 0 in + defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp, SchedWriteFLogic>; + +// If only AVX1 is supported, we need to handle integer operations with +// floating point instructions since the integer versions aren't available. +let Predicates = [HasAVX1Only] in { + def : Pat<(v4i64 (and VR256:$src1, VR256:$src2)), + (VANDPSYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (or VR256:$src1, VR256:$src2)), + (VORPSYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (xor VR256:$src1, VR256:$src2)), + (VXORPSYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (X86andnp VR256:$src1, VR256:$src2)), + (VANDNPSYrr VR256:$src1, VR256:$src2)>; + + def : Pat<(and VR256:$src1, (loadv4i64 addr:$src2)), + (VANDPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(or VR256:$src1, (loadv4i64 addr:$src2)), + (VORPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(xor VR256:$src1, (loadv4i64 addr:$src2)), + (VXORPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(X86andnp VR256:$src1, (loadv4i64 addr:$src2)), + (VANDNPSYrm VR256:$src1, addr:$src2)>; +} + +let Predicates = [HasAVX, NoVLX_Or_NoDQI] in { + // Use packed logical operations for scalar ops. + def : Pat<(f64 (X86fand FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VANDPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + def : Pat<(f64 (X86for FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VORPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + def : Pat<(f64 (X86fxor FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VXORPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + def : Pat<(f64 (X86fandn FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (VANDNPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + + def : Pat<(f32 (X86fand FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VANDPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; + def : Pat<(f32 (X86for FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VORPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; + def : Pat<(f32 (X86fxor FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VXORPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; + def : Pat<(f32 (X86fandn FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (VANDNPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; +} + +let Predicates = [UseSSE1] in { + // Use packed logical operations for scalar ops. + def : Pat<(f32 (X86fand FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (ANDPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; + def : Pat<(f32 (X86for FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (ORPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; + def : Pat<(f32 (X86fxor FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (XORPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; + def : Pat<(f32 (X86fandn FR32:$src1, FR32:$src2)), + (COPY_TO_REGCLASS + (v4f32 (ANDNPSrr (v4f32 (COPY_TO_REGCLASS FR32:$src1, VR128)), + (v4f32 (COPY_TO_REGCLASS FR32:$src2, VR128)))), + FR32)>; +} + +let Predicates = [UseSSE2] in { + // Use packed logical operations for scalar ops. + def : Pat<(f64 (X86fand FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (ANDPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + def : Pat<(f64 (X86for FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (ORPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + def : Pat<(f64 (X86fxor FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (XORPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; + def : Pat<(f64 (X86fandn FR64:$src1, FR64:$src2)), + (COPY_TO_REGCLASS + (v2f64 (ANDNPDrr (v2f64 (COPY_TO_REGCLASS FR64:$src1, VR128)), + (v2f64 (COPY_TO_REGCLASS FR64:$src2, VR128)))), + FR64)>; +} + +// Patterns for packed operations when we don't have integer type available. +def : Pat<(v4f32 (X86fand VR128:$src1, VR128:$src2)), + (ANDPSrr VR128:$src1, VR128:$src2)>; +def : Pat<(v4f32 (X86for VR128:$src1, VR128:$src2)), + (ORPSrr VR128:$src1, VR128:$src2)>; +def : Pat<(v4f32 (X86fxor VR128:$src1, VR128:$src2)), + (XORPSrr VR128:$src1, VR128:$src2)>; +def : Pat<(v4f32 (X86fandn VR128:$src1, VR128:$src2)), + (ANDNPSrr VR128:$src1, VR128:$src2)>; + +def : Pat<(X86fand VR128:$src1, (memopv4f32 addr:$src2)), + (ANDPSrm VR128:$src1, addr:$src2)>; +def : Pat<(X86for VR128:$src1, (memopv4f32 addr:$src2)), + (ORPSrm VR128:$src1, addr:$src2)>; +def : Pat<(X86fxor VR128:$src1, (memopv4f32 addr:$src2)), + (XORPSrm VR128:$src1, addr:$src2)>; +def : Pat<(X86fandn VR128:$src1, (memopv4f32 addr:$src2)), + (ANDNPSrm VR128:$src1, addr:$src2)>; + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Arithmetic Instructions +//===----------------------------------------------------------------------===// + +/// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and +/// vector forms. +/// +/// In addition, we also have a special variant of the scalar form here to +/// represent the associated intrinsic operation. This form is unlike the +/// plain scalar form, in that it takes an entire vector (instead of a scalar) +/// and leaves the top elements unmodified (therefore these cannot be commuted). +/// +/// These three forms can each be reg+reg or reg+mem. +/// + +/// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those +/// classes below +multiclass basic_sse12_fp_binop_p opc, string OpcodeStr, + SDNode OpNode, X86SchedWriteSizes sched> { + let Predicates = [HasAVX, NoVLX] in { + defm V#NAME#PS : sse12_fp_packed, PS, VEX_4V, VEX_WIG; + defm V#NAME#PD : sse12_fp_packed, PD, VEX_4V, VEX_WIG; + + defm V#NAME#PSY : sse12_fp_packed, PS, VEX_4V, VEX_L, VEX_WIG; + defm V#NAME#PDY : sse12_fp_packed, PD, VEX_4V, VEX_L, VEX_WIG; + } + + let Constraints = "$src1 = $dst" in { + defm PS : sse12_fp_packed, PS; + defm PD : sse12_fp_packed, PD; + } +} + +multiclass basic_sse12_fp_binop_s opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteSizes sched> { + defm V#NAME#SS : sse12_fp_scalar, + XS, VEX_4V, VEX_LIG, VEX_WIG; + defm V#NAME#SD : sse12_fp_scalar, + XD, VEX_4V, VEX_LIG, VEX_WIG; + + let Constraints = "$src1 = $dst" in { + defm SS : sse12_fp_scalar, XS; + defm SD : sse12_fp_scalar, XD; + } +} + +multiclass basic_sse12_fp_binop_s_int opc, string OpcodeStr, + SDPatternOperator OpNode, + X86SchedWriteSizes sched> { + defm V#NAME#SS : sse12_fp_scalar_int, XS, VEX_4V, VEX_LIG, VEX_WIG; + defm V#NAME#SD : sse12_fp_scalar_int, XD, VEX_4V, VEX_LIG, VEX_WIG; + + let Constraints = "$src1 = $dst" in { + defm SS : sse12_fp_scalar_int, XS; + defm SD : sse12_fp_scalar_int, XD; + } +} + +// Binary Arithmetic instructions +defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SchedWriteFAddSizes>, + basic_sse12_fp_binop_s<0x58, "add", fadd, SchedWriteFAddSizes>, + basic_sse12_fp_binop_s_int<0x58, "add", null_frag, SchedWriteFAddSizes>; +defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SchedWriteFMulSizes>, + basic_sse12_fp_binop_s<0x59, "mul", fmul, SchedWriteFMulSizes>, + basic_sse12_fp_binop_s_int<0x59, "mul", null_frag, SchedWriteFMulSizes>; +let isCommutable = 0 in { + defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SchedWriteFAddSizes>, + basic_sse12_fp_binop_s<0x5C, "sub", fsub, SchedWriteFAddSizes>, + basic_sse12_fp_binop_s_int<0x5C, "sub", null_frag, SchedWriteFAddSizes>; + defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SchedWriteFDivSizes>, + basic_sse12_fp_binop_s<0x5E, "div", fdiv, SchedWriteFDivSizes>, + basic_sse12_fp_binop_s_int<0x5E, "div", null_frag, SchedWriteFDivSizes>; + defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SchedWriteFCmpSizes>, + basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SchedWriteFCmpSizes>, + basic_sse12_fp_binop_s_int<0x5F, "max", X86fmaxs, SchedWriteFCmpSizes>; + defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SchedWriteFCmpSizes>, + basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SchedWriteFCmpSizes>, + basic_sse12_fp_binop_s_int<0x5D, "min", X86fmins, SchedWriteFCmpSizes>; +} + +let isCodeGenOnly = 1 in { + defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SchedWriteFCmpSizes>, + basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SchedWriteFCmpSizes>; + defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SchedWriteFCmpSizes>, + basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SchedWriteFCmpSizes>; +} + +// Patterns used to select SSE scalar fp arithmetic instructions from +// either: +// +// (1) a scalar fp operation followed by a blend +// +// The effect is that the backend no longer emits unnecessary vector +// insert instructions immediately after SSE scalar fp instructions +// like addss or mulss. +// +// For example, given the following code: +// __m128 foo(__m128 A, __m128 B) { +// A[0] += B[0]; +// return A; +// } +// +// Previously we generated: +// addss %xmm0, %xmm1 +// movss %xmm1, %xmm0 +// +// We now generate: +// addss %xmm1, %xmm0 +// +// (2) a vector packed single/double fp operation followed by a vector insert +// +// The effect is that the backend converts the packed fp instruction +// followed by a vector insert into a single SSE scalar fp instruction. +// +// For example, given the following code: +// __m128 foo(__m128 A, __m128 B) { +// __m128 C = A + B; +// return (__m128) {c[0], a[1], a[2], a[3]}; +// } +// +// Previously we generated: +// addps %xmm0, %xmm1 +// movss %xmm1, %xmm0 +// +// We now generate: +// addss %xmm1, %xmm0 + +// TODO: Some canonicalization in lowering would simplify the number of +// patterns we have to try to match. +multiclass scalar_math_patterns { + let Predicates = [BasePredicate] in { + // extracted scalar math op with insert via movss/movsd + def : Pat<(VT (Move (VT VR128:$dst), + (VT (scalar_to_vector + (Op (EltTy (extractelt (VT VR128:$dst), (iPTR 0))), + RC:$src))))), + (!cast(OpcPrefix#rr_Int) VT:$dst, + (VT (COPY_TO_REGCLASS RC:$src, VR128)))>; + } + + // Repeat for AVX versions of the instructions. + let Predicates = [UseAVX] in { + // extracted scalar math op with insert via movss/movsd + def : Pat<(VT (Move (VT VR128:$dst), + (VT (scalar_to_vector + (Op (EltTy (extractelt (VT VR128:$dst), (iPTR 0))), + RC:$src))))), + (!cast("V"#OpcPrefix#rr_Int) VT:$dst, + (VT (COPY_TO_REGCLASS RC:$src, VR128)))>; + } +} + +defm : scalar_math_patterns; +defm : scalar_math_patterns; +defm : scalar_math_patterns; +defm : scalar_math_patterns; + +defm : scalar_math_patterns; +defm : scalar_math_patterns; +defm : scalar_math_patterns; +defm : scalar_math_patterns; + +/// Unop Arithmetic +/// In addition, we also have a special variant of the scalar form here to +/// represent the associated intrinsic operation. This form is unlike the +/// plain scalar form, in that it takes an entire vector (instead of a +/// scalar) and leaves the top elements undefined. +/// +/// And, we have a special variant form for a full-vector intrinsic form. + +/// sse_fp_unop_s - SSE1 unops in scalar form +/// For the non-AVX defs, we need $src1 to be tied to $dst because +/// the HW instructions are 2 operand / destructive. +multiclass sse_fp_unop_s opc, string OpcodeStr, RegisterClass RC, + ValueType ScalarVT, X86MemOperand x86memop, + Operand intmemop, SDNode OpNode, Domain d, + X86FoldableSchedWrite sched, Predicate target> { + let hasSideEffects = 0 in { + def r : I, Sched<[sched]>, + Requires<[target]>; + let mayLoad = 1 in + def m : I, + Sched<[sched.Folded, ReadAfterLd]>, + Requires<[target, OptForSize]>; + + let isCodeGenOnly = 1, Constraints = "$src1 = $dst", ExeDomain = d in { + def r_Int : I, + Sched<[sched]>; + let mayLoad = 1 in + def m_Int : I, + Sched<[sched.Folded, ReadAfterLd]>; + } + } + +} + +multiclass sse_fp_unop_s_intr { + let Predicates = [target] in { + // These are unary operations, but they are modeled as having 2 source operands + // because the high elements of the destination are unchanged in SSE. + def : Pat<(Intr VR128:$src), + (!cast(NAME#r_Int) VR128:$src, VR128:$src)>; + } + // We don't want to fold scalar loads into these instructions unless + // optimizing for size. This is because the folded instruction will have a + // partial register update, while the unfolded sequence will not, e.g. + // movss mem, %xmm0 + // rcpss %xmm0, %xmm0 + // which has a clobber before the rcp, vs. + // rcpss mem, %xmm0 + let Predicates = [target, OptForSize] in { + def : Pat<(Intr int_cpat:$src2), + (!cast(NAME#m_Int) + (vt (IMPLICIT_DEF)), addr:$src2)>; + } +} + +multiclass avx_fp_unop_s_intr { + let Predicates = [target] in { + def : Pat<(Intr VR128:$src), + (!cast(NAME#r_Int) VR128:$src, + VR128:$src)>; + } + let Predicates = [target, OptForSize] in { + def : Pat<(Intr int_cpat:$src2), + (!cast(NAME#m_Int) + (vt (IMPLICIT_DEF)), addr:$src2)>; + } +} + +multiclass avx_fp_unop_s opc, string OpcodeStr, RegisterClass RC, + ValueType ScalarVT, X86MemOperand x86memop, + Operand intmemop, SDNode OpNode, Domain d, + X86FoldableSchedWrite sched, Predicate target> { + let hasSideEffects = 0 in { + def r : I, Sched<[sched]>; + let mayLoad = 1 in + def m : I, Sched<[sched.Folded, ReadAfterLd]>; + let isCodeGenOnly = 1, ExeDomain = d in { + def r_Int : I, Sched<[sched]>; + let mayLoad = 1 in + def m_Int : I, Sched<[sched.Folded, ReadAfterLd]>; + } + } + + // We don't want to fold scalar loads into these instructions unless + // optimizing for size. This is because the folded instruction will have a + // partial register update, while the unfolded sequence will not, e.g. + // vmovss mem, %xmm0 + // vrcpss %xmm0, %xmm0, %xmm0 + // which has a clobber before the rcp, vs. + // vrcpss mem, %xmm0, %xmm0 + // TODO: In theory, we could fold the load, and avoid the stall caused by + // the partial register store, either in BreakFalseDeps or with smarter RA. + let Predicates = [target] in { + def : Pat<(OpNode RC:$src), (!cast(NAME#r) + (ScalarVT (IMPLICIT_DEF)), RC:$src)>; + } + let Predicates = [target, OptForSize] in { + def : Pat<(ScalarVT (OpNode (load addr:$src))), + (!cast(NAME#m) (ScalarVT (IMPLICIT_DEF)), + addr:$src)>; + } +} + +/// sse1_fp_unop_p - SSE1 unops in packed form. +multiclass sse1_fp_unop_p opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, list prds> { +let Predicates = prds in { + def V#NAME#PSr : PSI, + VEX, Sched<[sched.XMM]>, VEX_WIG; + def V#NAME#PSm : PSI, + VEX, Sched<[sched.XMM.Folded]>, VEX_WIG; + def V#NAME#PSYr : PSI, + VEX, VEX_L, Sched<[sched.YMM]>, VEX_WIG; + def V#NAME#PSYm : PSI, + VEX, VEX_L, Sched<[sched.YMM.Folded]>, VEX_WIG; +} + + def PSr : PSI, + Sched<[sched.XMM]>; + def PSm : PSI, + Sched<[sched.XMM.Folded]>; +} + +/// sse2_fp_unop_p - SSE2 unops in vector forms. +multiclass sse2_fp_unop_p opc, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched> { +let Predicates = [HasAVX, NoVLX] in { + def V#NAME#PDr : PDI, + VEX, Sched<[sched.XMM]>, VEX_WIG; + def V#NAME#PDm : PDI, + VEX, Sched<[sched.XMM.Folded]>, VEX_WIG; + def V#NAME#PDYr : PDI, + VEX, VEX_L, Sched<[sched.YMM]>, VEX_WIG; + def V#NAME#PDYm : PDI, + VEX, VEX_L, Sched<[sched.YMM.Folded]>, VEX_WIG; +} + + def PDr : PDI, + Sched<[sched.XMM]>; + def PDm : PDI, + Sched<[sched.XMM.Folded]>; +} + +multiclass sse1_fp_unop_s_intr opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate AVXTarget> { + defm SS : sse_fp_unop_s_intr("int_x86_sse_"##OpcodeStr##_ss), + UseSSE1, "SS">, XS; + defm V#NAME#SS : avx_fp_unop_s_intr("int_x86_sse_"##OpcodeStr##_ss), + AVXTarget>, + XS, VEX_4V, VEX_LIG, VEX_WIG, NotMemoryFoldable; +} + +multiclass sse1_fp_unop_s opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate AVXTarget> { + defm SS : sse_fp_unop_s, XS; + defm V#NAME#SS : avx_fp_unop_s, + XS, VEX_4V, VEX_LIG, VEX_WIG; +} + +multiclass sse2_fp_unop_s opc, string OpcodeStr, SDNode OpNode, + X86SchedWriteWidths sched, Predicate AVXTarget> { + defm SD : sse_fp_unop_s, XD; + defm V#NAME#SD : avx_fp_unop_s, + XD, VEX_4V, VEX_LIG, VEX_WIG; +} + +// Square root. +defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SchedWriteFSqrt, UseAVX>, + sse1_fp_unop_p<0x51, "sqrt", fsqrt, SchedWriteFSqrt, [HasAVX, NoVLX]>, + sse2_fp_unop_s<0x51, "sqrt", fsqrt, SchedWriteFSqrt64, UseAVX>, + sse2_fp_unop_p<0x51, "sqrt", fsqrt, SchedWriteFSqrt64>; + +// Reciprocal approximations. Note that these typically require refinement +// in order to obtain suitable precision. +defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SchedWriteFRsqrt, HasAVX>, + sse1_fp_unop_s_intr<0x52, "rsqrt", X86frsqrt, SchedWriteFRsqrt, HasAVX>, + sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SchedWriteFRsqrt, [HasAVX]>; +defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SchedWriteFRcp, HasAVX>, + sse1_fp_unop_s_intr<0x53, "rcp", X86frcp, SchedWriteFRcp, HasAVX>, + sse1_fp_unop_p<0x53, "rcp", X86frcp, SchedWriteFRcp, [HasAVX]>; + +// There is no f64 version of the reciprocal approximation instructions. + +multiclass scalar_unary_math_patterns { + let Predicates = [BasePredicate] in { + def : Pat<(VT (Move VT:$dst, (scalar_to_vector + (OpNode (extractelt VT:$src, 0))))), + (!cast(OpcPrefix#r_Int) VT:$dst, VT:$src)>; + } + + // Repeat for AVX versions of the instructions. + let Predicates = [UseAVX] in { + def : Pat<(VT (Move VT:$dst, (scalar_to_vector + (OpNode (extractelt VT:$src, 0))))), + (!cast("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>; + } +} + +multiclass scalar_unary_math_imm_patterns ImmV, + Predicate BasePredicate> { + let Predicates = [BasePredicate] in { + def : Pat<(VT (Move VT:$dst, (scalar_to_vector + (OpNode (extractelt VT:$src, 0))))), + (!cast(OpcPrefix#r_Int) VT:$dst, VT:$src, (i32 ImmV))>; + } + + // Repeat for AVX versions of the instructions. + let Predicates = [UseAVX] in { + def : Pat<(VT (Move VT:$dst, (scalar_to_vector + (OpNode (extractelt VT:$src, 0))))), + (!cast("V"#OpcPrefix#r_Int) VT:$dst, VT:$src, (i32 ImmV))>; + } +} + +defm : scalar_unary_math_patterns; +defm : scalar_unary_math_patterns; + +multiclass scalar_unary_math_intr_patterns { + let Predicates = [BasePredicate] in { + def : Pat<(VT (Move VT:$dst, (Intr VT:$src))), + (!cast(OpcPrefix#r_Int) VT:$dst, VT:$src)>; + } + + // Repeat for AVX versions of the instructions. + let Predicates = [HasAVX] in { + def : Pat<(VT (Move VT:$dst, (Intr VT:$src))), + (!cast("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>; + } +} + +defm : scalar_unary_math_intr_patterns; +defm : scalar_unary_math_intr_patterns; + + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Non-temporal stores +//===----------------------------------------------------------------------===// + +let AddedComplexity = 400 in { // Prefer non-temporal versions +let Predicates = [HasAVX, NoVLX] in { +let SchedRW = [SchedWriteFMoveLSNT.XMM.MR] in { +def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs), + (ins f128mem:$dst, VR128:$src), + "movntps\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v4f32 VR128:$src), + addr:$dst)]>, VEX, VEX_WIG; +def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs), + (ins f128mem:$dst, VR128:$src), + "movntpd\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v2f64 VR128:$src), + addr:$dst)]>, VEX, VEX_WIG; +} // SchedRW + +let SchedRW = [SchedWriteFMoveLSNT.YMM.MR] in { +def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs), + (ins f256mem:$dst, VR256:$src), + "movntps\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v8f32 VR256:$src), + addr:$dst)]>, VEX, VEX_L, VEX_WIG; +def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs), + (ins f256mem:$dst, VR256:$src), + "movntpd\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v4f64 VR256:$src), + addr:$dst)]>, VEX, VEX_L, VEX_WIG; +} // SchedRW + +let ExeDomain = SSEPackedInt in { +def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs), + (ins i128mem:$dst, VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v2i64 VR128:$src), + addr:$dst)]>, VEX, VEX_WIG, + Sched<[SchedWriteVecMoveLSNT.XMM.MR]>; +def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs), + (ins i256mem:$dst, VR256:$src), + "movntdq\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v4i64 VR256:$src), + addr:$dst)]>, VEX, VEX_L, VEX_WIG, + Sched<[SchedWriteVecMoveLSNT.YMM.MR]>; +} // ExeDomain +} // Predicates + +let SchedRW = [SchedWriteFMoveLSNT.XMM.MR] in { +def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movntps\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>; +def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movntpd\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>; +} // SchedRW + +let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecMoveLSNT.XMM.MR] in +def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)]>; + +let SchedRW = [WriteStoreNT] in { +// There is no AVX form for instructions below this point +def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "movnti{l}\t{$src, $dst|$dst, $src}", + [(nontemporalstore (i32 GR32:$src), addr:$dst)]>, + PS, Requires<[HasSSE2]>; +def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "movnti{q}\t{$src, $dst|$dst, $src}", + [(nontemporalstore (i64 GR64:$src), addr:$dst)]>, + PS, Requires<[HasSSE2]>; +} // SchedRW = [WriteStoreNT] + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(alignednontemporalstore (v8i32 VR256:$src), addr:$dst), + (VMOVNTDQYmr addr:$dst, VR256:$src)>; + def : Pat<(alignednontemporalstore (v16i16 VR256:$src), addr:$dst), + (VMOVNTDQYmr addr:$dst, VR256:$src)>; + def : Pat<(alignednontemporalstore (v32i8 VR256:$src), addr:$dst), + (VMOVNTDQYmr addr:$dst, VR256:$src)>; + + def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst), + (VMOVNTDQmr addr:$dst, VR128:$src)>; + def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst), + (VMOVNTDQmr addr:$dst, VR128:$src)>; + def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst), + (VMOVNTDQmr addr:$dst, VR128:$src)>; +} + +let Predicates = [UseSSE2] in { + def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst), + (MOVNTDQmr addr:$dst, VR128:$src)>; + def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst), + (MOVNTDQmr addr:$dst, VR128:$src)>; + def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst), + (MOVNTDQmr addr:$dst, VR128:$src)>; +} + +} // AddedComplexity + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Prefetch and memory fence +//===----------------------------------------------------------------------===// + +// Prefetch intrinsic. +let Predicates = [HasSSEPrefetch], SchedRW = [WriteLoad] in { +def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src), + "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>, TB; +def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src), + "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>, TB; +def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src), + "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>, TB; +def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src), + "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>, TB; +} + +// FIXME: How should flush instruction be modeled? +let SchedRW = [WriteLoad] in { +// Flush cache +def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src), + "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>, + PS, Requires<[HasSSE2]>; +} + +let SchedRW = [WriteNop] in { +// Pause. This "instruction" is encoded as "rep; nop", so even though it +// was introduced with SSE2, it's backward compatible. +def PAUSE : I<0x90, RawFrm, (outs), (ins), + "pause", [(int_x86_sse2_pause)]>, OBXS; +} + +let SchedRW = [WriteFence] in { +// Load, store, and memory fence +// TODO: As with mfence, we may want to ease the availability of sfence/lfence +// to include any 64-bit target. +def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>, + PS, Requires<[HasSSE1]>; +def LFENCE : I<0xAE, MRM_E8, (outs), (ins), "lfence", [(int_x86_sse2_lfence)]>, + PS, Requires<[HasSSE2]>; +def MFENCE : I<0xAE, MRM_F0, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>, + PS, Requires<[HasMFence]>; +} // SchedRW + +def : Pat<(X86MFence), (MFENCE)>; + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Load/Store XCSR register +//===----------------------------------------------------------------------===// + +def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src), + "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, + VEX, Sched<[WriteLDMXCSR]>, VEX_WIG; +def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst), + "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, + VEX, Sched<[WriteSTMXCSR]>, VEX_WIG; + +def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src), + "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, + TB, Sched<[WriteLDMXCSR]>; +def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst), + "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, + TB, Sched<[WriteSTMXCSR]>; + +//===---------------------------------------------------------------------===// +// SSE2 - Move Aligned/Unaligned Packed Integer Instructions +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { // SSE integer instructions + +let hasSideEffects = 0 in { +def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.XMM.RR]>, VEX, VEX_WIG; +def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "movdqu\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.XMM.RR]>, VEX, VEX_WIG; +def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.RR]>, VEX, VEX_L, VEX_WIG; +def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + "movdqu\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.RR]>, VEX, VEX_L, VEX_WIG; +} + +// For Disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { +def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.XMM.RR]>, + VEX, VEX_WIG, FoldGenData<"VMOVDQArr">; +def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.RR]>, + VEX, VEX_L, VEX_WIG, FoldGenData<"VMOVDQAYrr">; +def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movdqu\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.XMM.RR]>, + VEX, VEX_WIG, FoldGenData<"VMOVDQUrr">; +def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src), + "movdqu\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.RR]>, + VEX, VEX_L, VEX_WIG, FoldGenData<"VMOVDQUYrr">; +} + +let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, + hasSideEffects = 0, Predicates = [HasAVX,NoVLX] in { +def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "movdqa\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (alignedloadv2i64 addr:$src))]>, + Sched<[SchedWriteVecMoveLS.XMM.RM]>, VEX, VEX_WIG; +def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.RM]>, + VEX, VEX_L, VEX_WIG; +def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "vmovdqu\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (loadv2i64 addr:$src))]>, + Sched<[SchedWriteVecMoveLS.XMM.RM]>, + XS, VEX, VEX_WIG; +def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src), + "vmovdqu\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.RM]>, + XS, VEX, VEX_L, VEX_WIG; +} + +let mayStore = 1, hasSideEffects = 0, Predicates = [HasAVX,NoVLX] in { +def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs), + (ins i128mem:$dst, VR128:$src), + "movdqa\t{$src, $dst|$dst, $src}", + [(alignedstore (v2i64 VR128:$src), addr:$dst)]>, + Sched<[SchedWriteVecMoveLS.XMM.MR]>, VEX, VEX_WIG; +def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs), + (ins i256mem:$dst, VR256:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLS.YMM.MR]>, VEX, VEX_L, VEX_WIG; +def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), + "vmovdqu\t{$src, $dst|$dst, $src}", + [(store (v2i64 VR128:$src), addr:$dst)]>, + Sched<[SchedWriteVecMoveLS.XMM.MR]>, XS, VEX, VEX_WIG; +def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src), + "vmovdqu\t{$src, $dst|$dst, $src}",[]>, + Sched<[SchedWriteVecMoveLS.YMM.MR]>, XS, VEX, VEX_L, VEX_WIG; +} + +let SchedRW = [SchedWriteVecMoveLS.XMM.RR] in { +let hasSideEffects = 0 in { +def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>; + +def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "movdqu\t{$src, $dst|$dst, $src}", []>, + XS, Requires<[UseSSE2]>; +} + +// For Disassembler +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { +def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movdqa\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MOVDQArr">; + +def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movdqu\t{$src, $dst|$dst, $src}", []>, + XS, Requires<[UseSSE2]>, FoldGenData<"MOVDQUrr">; +} +} // SchedRW + +let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, + hasSideEffects = 0, SchedRW = [SchedWriteVecMoveLS.XMM.RM] in { +def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "movdqa\t{$src, $dst|$dst, $src}", + [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>; +def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "movdqu\t{$src, $dst|$dst, $src}", + [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>, + XS, Requires<[UseSSE2]>; +} + +let mayStore = 1, hasSideEffects = 0, + SchedRW = [SchedWriteVecMoveLS.XMM.MR] in { +def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), + "movdqa\t{$src, $dst|$dst, $src}", + [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>; +def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), + "movdqu\t{$src, $dst|$dst, $src}", + [/*(store (v2i64 VR128:$src), addr:$dst)*/]>, + XS, Requires<[UseSSE2]>; +} + +} // ExeDomain = SSEPackedInt + +// Aliases to help the assembler pick two byte VEX encodings by swapping the +// operands relative to the normal instructions to use VEX.R instead of VEX.B. +def : InstAlias<"vmovdqa\t{$src, $dst|$dst, $src}", + (VMOVDQArr_REV VR128L:$dst, VR128H:$src), 0>; +def : InstAlias<"vmovdqa\t{$src, $dst|$dst, $src}", + (VMOVDQAYrr_REV VR256L:$dst, VR256H:$src), 0>; +def : InstAlias<"vmovdqu\t{$src, $dst|$dst, $src}", + (VMOVDQUrr_REV VR128L:$dst, VR128H:$src), 0>; +def : InstAlias<"vmovdqu\t{$src, $dst|$dst, $src}", + (VMOVDQUYrr_REV VR256L:$dst, VR256H:$src), 0>; + +// Reversed version with ".s" suffix for GAS compatibility. +def : InstAlias<"vmovdqa.s\t{$src, $dst|$dst, $src}", + (VMOVDQArr_REV VR128:$dst, VR128:$src), 0>; +def : InstAlias<"vmovdqa.s\t{$src, $dst|$dst, $src}", + (VMOVDQAYrr_REV VR256:$dst, VR256:$src), 0>; +def : InstAlias<"vmovdqu.s\t{$src, $dst|$dst, $src}", + (VMOVDQUrr_REV VR128:$dst, VR128:$src), 0>; +def : InstAlias<"vmovdqu.s\t{$src, $dst|$dst, $src}", + (VMOVDQUYrr_REV VR256:$dst, VR256:$src), 0>; + +// Reversed version with ".s" suffix for GAS compatibility. +def : InstAlias<"movdqa.s\t{$src, $dst|$dst, $src}", + (MOVDQArr_REV VR128:$dst, VR128:$src), 0>; +def : InstAlias<"movdqu.s\t{$src, $dst|$dst, $src}", + (MOVDQUrr_REV VR128:$dst, VR128:$src), 0>; + +let Predicates = [HasAVX, NoVLX] in { + // Additional patterns for other integer sizes. + def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst), + (VMOVDQAmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst), + (VMOVDQAmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst), + (VMOVDQAmr addr:$dst, VR128:$src)>; + def : Pat<(store (v4i32 VR128:$src), addr:$dst), + (VMOVDQUmr addr:$dst, VR128:$src)>; + def : Pat<(store (v8i16 VR128:$src), addr:$dst), + (VMOVDQUmr addr:$dst, VR128:$src)>; + def : Pat<(store (v16i8 VR128:$src), addr:$dst), + (VMOVDQUmr addr:$dst, VR128:$src)>; +} + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Arithmetic Instructions +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { // SSE integer instructions + +/// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types +multiclass PDI_binop_rm2 opc, string OpcodeStr, SDNode OpNode, + ValueType DstVT, ValueType SrcVT, RegisterClass RC, + PatFrag memop_frag, X86MemOperand x86memop, + X86FoldableSchedWrite sched, bit Is2Addr = 1> { + let isCommutable = 1 in + def rr : PDI, + Sched<[sched]>; + def rm : PDI, + Sched<[sched.Folded, ReadAfterLd]>; +} +} // ExeDomain = SSEPackedInt + +defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32, + SchedWriteVecALU, 1, NoVLX>; +defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64, + SchedWriteVecALU, 1, NoVLX>; +defm PADDSB : PDI_binop_all<0xEC, "paddsb", X86adds, v16i8, v32i8, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PADDSW : PDI_binop_all<0xED, "paddsw", X86adds, v8i16, v16i16, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PADDUSB : PDI_binop_all<0xDC, "paddusb", X86addus, v16i8, v32i8, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PADDUSW : PDI_binop_all<0xDD, "paddusw", X86addus, v8i16, v16i16, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16, + SchedWriteVecIMul, 1, NoVLX_Or_NoBWI>; +defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16, + SchedWriteVecIMul, 1, NoVLX_Or_NoBWI>; +defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16, + SchedWriteVecIMul, 1, NoVLX_Or_NoBWI>; +defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8, + SchedWriteVecALU, 0, NoVLX_Or_NoBWI>; +defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16, + SchedWriteVecALU, 0, NoVLX_Or_NoBWI>; +defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32, + SchedWriteVecALU, 0, NoVLX>; +defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64, + SchedWriteVecALU, 0, NoVLX>; +defm PSUBSB : PDI_binop_all<0xE8, "psubsb", X86subs, v16i8, v32i8, + SchedWriteVecALU, 0, NoVLX_Or_NoBWI>; +defm PSUBSW : PDI_binop_all<0xE9, "psubsw", X86subs, v8i16, v16i16, + SchedWriteVecALU, 0, NoVLX_Or_NoBWI>; +defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8, + SchedWriteVecALU, 0, NoVLX_Or_NoBWI>; +defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16, + SchedWriteVecALU, 0, NoVLX_Or_NoBWI>; +defm PMINUB : PDI_binop_all<0xDA, "pminub", umin, v16i8, v32i8, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PMINSW : PDI_binop_all<0xEA, "pminsw", smin, v8i16, v16i16, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", umax, v16i8, v32i8, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", smax, v8i16, v16i16, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PAVGB : PDI_binop_all<0xE0, "pavgb", X86avg, v16i8, v32i8, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PAVGW : PDI_binop_all<0xE3, "pavgw", X86avg, v8i16, v16i16, + SchedWriteVecALU, 1, NoVLX_Or_NoBWI>; +defm PMULUDQ : PDI_binop_all<0xF4, "pmuludq", X86pmuludq, v2i64, v4i64, + SchedWriteVecIMul, 1, NoVLX>; + +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in +defm VPMADDWD : PDI_binop_rm2<0xF5, "vpmaddwd", X86vpmaddwd, v4i32, v8i16, VR128, + loadv2i64, i128mem, SchedWriteVecIMul.XMM, 0>, + VEX_4V, VEX_WIG; + +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in +defm VPMADDWDY : PDI_binop_rm2<0xF5, "vpmaddwd", X86vpmaddwd, v8i32, v16i16, + VR256, loadv4i64, i256mem, SchedWriteVecIMul.YMM, + 0>, VEX_4V, VEX_L, VEX_WIG; +let Constraints = "$src1 = $dst" in +defm PMADDWD : PDI_binop_rm2<0xF5, "pmaddwd", X86vpmaddwd, v4i32, v8i16, VR128, + memopv2i64, i128mem, SchedWriteVecIMul.XMM>; + +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in +defm VPSADBW : PDI_binop_rm2<0xF6, "vpsadbw", X86psadbw, v2i64, v16i8, VR128, + loadv2i64, i128mem, SchedWritePSADBW.XMM, 0>, + VEX_4V, VEX_WIG; +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in +defm VPSADBWY : PDI_binop_rm2<0xF6, "vpsadbw", X86psadbw, v4i64, v32i8, VR256, + loadv4i64, i256mem, SchedWritePSADBW.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; +let Constraints = "$src1 = $dst" in +defm PSADBW : PDI_binop_rm2<0xF6, "psadbw", X86psadbw, v2i64, v16i8, VR128, + memopv2i64, i128mem, SchedWritePSADBW.XMM>; + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Logical Instructions +//===---------------------------------------------------------------------===// + +multiclass PDI_binop_rmi opc, bits<8> opc2, Format ImmForm, + string OpcodeStr, SDNode OpNode, + SDNode OpNode2, RegisterClass RC, + X86FoldableSchedWrite sched, + X86FoldableSchedWrite schedImm, + ValueType DstVT, ValueType SrcVT, + PatFrag ld_frag, bit Is2Addr = 1> { + // src2 is always 128-bit + def rr : PDI, + Sched<[sched]>; + def rm : PDI, + Sched<[sched.Folded, ReadAfterLd]>; + def ri : PDIi8, + Sched<[schedImm]>; +} + +multiclass PDI_binop_rmi_all opc, bits<8> opc2, Format ImmForm, + string OpcodeStr, SDNode OpNode, + SDNode OpNode2, ValueType DstVT128, + ValueType DstVT256, ValueType SrcVT, + X86SchedWriteWidths sched, + X86SchedWriteWidths schedImm, Predicate prd> { +let Predicates = [HasAVX, prd] in + defm V#NAME : PDI_binop_rmi, VEX_4V, VEX_WIG; +let Predicates = [HasAVX2, prd] in + defm V#NAME#Y : PDI_binop_rmi, VEX_4V, VEX_L, + VEX_WIG; +let Constraints = "$src1 = $dst" in + defm NAME : PDI_binop_rmi; +} + +multiclass PDI_binop_ri opc, Format ImmForm, string OpcodeStr, + SDNode OpNode, RegisterClass RC, ValueType VT, + X86FoldableSchedWrite sched, bit Is2Addr = 1> { + def ri : PDIi8, + Sched<[sched]>; +} + +multiclass PDI_binop_ri_all opc, Format ImmForm, string OpcodeStr, + SDNode OpNode, X86SchedWriteWidths sched> { +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in + defm V#NAME : PDI_binop_ri, VEX_4V, VEX_WIG; +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in + defm V#NAME#Y : PDI_binop_ri, + VEX_4V, VEX_L, VEX_WIG; +let Constraints = "$src1 = $dst" in + defm NAME : PDI_binop_ri; +} + +let ExeDomain = SSEPackedInt in { + defm PSLLW : PDI_binop_rmi_all<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli, + v8i16, v16i16, v8i16, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX_Or_NoBWI>; + defm PSLLD : PDI_binop_rmi_all<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli, + v4i32, v8i32, v4i32, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX>; + defm PSLLQ : PDI_binop_rmi_all<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli, + v2i64, v4i64, v2i64, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX>; + + defm PSRLW : PDI_binop_rmi_all<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli, + v8i16, v16i16, v8i16, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX_Or_NoBWI>; + defm PSRLD : PDI_binop_rmi_all<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli, + v4i32, v8i32, v4i32, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX>; + defm PSRLQ : PDI_binop_rmi_all<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli, + v2i64, v4i64, v2i64, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX>; + + defm PSRAW : PDI_binop_rmi_all<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai, + v8i16, v16i16, v8i16, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX_Or_NoBWI>; + defm PSRAD : PDI_binop_rmi_all<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai, + v4i32, v8i32, v4i32, SchedWriteVecShift, + SchedWriteVecShiftImm, NoVLX>; + + defm PSLLDQ : PDI_binop_ri_all<0x73, MRM7r, "pslldq", X86vshldq, + SchedWriteShuffle>; + defm PSRLDQ : PDI_binop_ri_all<0x73, MRM3r, "psrldq", X86vshrdq, + SchedWriteShuffle>; +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Comparison Instructions +//===---------------------------------------------------------------------===// + +defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8, + SchedWriteVecALU, 1, TruePredicate>; +defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16, + SchedWriteVecALU, 1, TruePredicate>; +defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32, + SchedWriteVecALU, 1, TruePredicate>; +defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8, + SchedWriteVecALU, 0, TruePredicate>; +defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16, + SchedWriteVecALU, 0, TruePredicate>; +defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32, + SchedWriteVecALU, 0, TruePredicate>; + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Shuffle Instructions +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { +multiclass sse2_pshuffle { +let Predicates = [HasAVX, prd] in { + def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, u8imm:$src2), + !strconcat("v", OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR128:$dst, + (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))]>, + VEX, Sched<[sched.XMM]>, VEX_WIG; + def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst), + (ins i128mem:$src1, u8imm:$src2), + !strconcat("v", OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR128:$dst, + (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)), + (i8 imm:$src2))))]>, VEX, + Sched<[sched.XMM.Folded]>, VEX_WIG; +} + +let Predicates = [HasAVX2, prd] in { + def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst), + (ins VR256:$src1, u8imm:$src2), + !strconcat("v", OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR256:$dst, + (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))]>, + VEX, VEX_L, Sched<[sched.YMM]>, VEX_WIG; + def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst), + (ins i256mem:$src1, u8imm:$src2), + !strconcat("v", OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR256:$dst, + (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)), + (i8 imm:$src2))))]>, VEX, VEX_L, + Sched<[sched.YMM.Folded]>, VEX_WIG; +} + +let Predicates = [UseSSE2] in { + def ri : Ii8<0x70, MRMSrcReg, + (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2), + !strconcat(OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR128:$dst, + (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))]>, + Sched<[sched.XMM]>; + def mi : Ii8<0x70, MRMSrcMem, + (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2), + !strconcat(OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR128:$dst, + (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)), + (i8 imm:$src2))))]>, + Sched<[sched.XMM.Folded]>; +} +} +} // ExeDomain = SSEPackedInt + +defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd, + SchedWriteShuffle, NoVLX>, PD; +defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw, + SchedWriteShuffle, NoVLX_Or_NoBWI>, XS; +defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw, + SchedWriteShuffle, NoVLX_Or_NoBWI>, XD; + +//===---------------------------------------------------------------------===// +// Packed Integer Pack Instructions (SSE & AVX) +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { +multiclass sse2_pack opc, string OpcodeStr, ValueType OutVT, + ValueType ArgVT, SDNode OpNode, RegisterClass RC, + X86MemOperand x86memop, X86FoldableSchedWrite sched, + PatFrag ld_frag, bit Is2Addr = 1> { + def rr : PDI, + Sched<[sched]>; + def rm : PDI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass sse4_pack opc, string OpcodeStr, ValueType OutVT, + ValueType ArgVT, SDNode OpNode, RegisterClass RC, + X86MemOperand x86memop, X86FoldableSchedWrite sched, + PatFrag ld_frag, bit Is2Addr = 1> { + def rr : SS48I, + Sched<[sched]>; + def rm : SS48I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + + defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V; +} + +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { + defm VPACKSSWBY : sse2_pack<0x63, "vpacksswb", v32i8, v16i16, X86Packss, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPACKSSDWY : sse2_pack<0x6B, "vpackssdw", v16i16, v8i32, X86Packss, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + + defm VPACKUSWBY : sse2_pack<0x67, "vpackuswb", v32i8, v16i16, X86Packus, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPACKUSDWY : sse4_pack<0x2B, "vpackusdw", v16i16, v8i32, X86Packus, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L; +} + +let Constraints = "$src1 = $dst" in { + defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + + defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + + defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; +} +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Unpack Instructions +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { +multiclass sse2_unpack opc, string OpcodeStr, ValueType vt, + SDNode OpNode, RegisterClass RC, X86MemOperand x86memop, + X86FoldableSchedWrite sched, PatFrag ld_frag, + bit Is2Addr = 1> { + def rr : PDI, + Sched<[sched]>; + def rm : PDI, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; +} + +let Predicates = [HasAVX, NoVLX] in { + defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; + defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, loadv2i64, 0>, + VEX_4V, VEX_WIG; +} + +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { + defm VPUNPCKLBWY : sse2_unpack<0x60, "vpunpcklbw", v32i8, X86Unpckl, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPUNPCKLWDY : sse2_unpack<0x61, "vpunpcklwd", v16i16, X86Unpckl, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPUNPCKHBWY : sse2_unpack<0x68, "vpunpckhbw", v32i8, X86Unpckh, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPUNPCKHWDY : sse2_unpack<0x69, "vpunpckhwd", v16i16, X86Unpckh, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; +} + +let Predicates = [HasAVX2, NoVLX] in { + defm VPUNPCKLDQY : sse2_unpack<0x62, "vpunpckldq", v8i32, X86Unpckl, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPUNPCKLQDQY : sse2_unpack<0x6C, "vpunpcklqdq", v4i64, X86Unpckl, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPUNPCKHDQY : sse2_unpack<0x6A, "vpunpckhdq", v8i32, X86Unpckh, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPUNPCKHQDQY : sse2_unpack<0x6D, "vpunpckhqdq", v4i64, X86Unpckh, VR256, + i256mem, SchedWriteShuffle.YMM, loadv4i64, 0>, + VEX_4V, VEX_L, VEX_WIG; +} + +let Constraints = "$src1 = $dst" in { + defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + + defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; + defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh, VR128, + i128mem, SchedWriteShuffle.XMM, memopv2i64>; +} +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Integer Extract and Insert +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { +multiclass sse2_pinsrw { + def rr : Ii8<0xC4, MRMSrcReg, + (outs VR128:$dst), (ins VR128:$src1, + GR32orGR64:$src2, u8imm:$src3), + !if(Is2Addr, + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), + [(set VR128:$dst, + (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))]>, + Sched<[WriteVecInsert]>; + def rm : Ii8<0xC4, MRMSrcMem, + (outs VR128:$dst), (ins VR128:$src1, + i16mem:$src2, u8imm:$src3), + !if(Is2Addr, + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), + [(set VR128:$dst, + (X86pinsrw VR128:$src1, (extloadi16 addr:$src2), + imm:$src3))]>, + Sched<[WriteVecInsertLd, ReadAfterLd]>; +} + +// Extract +let Predicates = [HasAVX, NoBWI] in +def VPEXTRWrr : Ii8<0xC5, MRMSrcReg, + (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2), + "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1), + imm:$src2))]>, + PD, VEX, Sched<[WriteVecExtract]>; +def PEXTRWrr : PDIi8<0xC5, MRMSrcReg, + (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2), + "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1), + imm:$src2))]>, + Sched<[WriteVecExtract]>; + +// Insert +let Predicates = [HasAVX, NoBWI] in +defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V; + +let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in +defm PINSRW : sse2_pinsrw, PD; + +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// SSE2 - Packed Mask Creation +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt in { + +def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), + (ins VR128:$src), + "pmovmskb\t{$src, $dst|$dst, $src}", + [(set GR32orGR64:$dst, (X86movmsk (v16i8 VR128:$src)))]>, + Sched<[WriteVecMOVMSK]>, VEX, VEX_WIG; + +let Predicates = [HasAVX2] in { +def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), + (ins VR256:$src), + "pmovmskb\t{$src, $dst|$dst, $src}", + [(set GR32orGR64:$dst, (X86movmsk (v32i8 VR256:$src)))]>, + Sched<[WriteVecMOVMSKY]>, VEX, VEX_L, VEX_WIG; +} + +def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src), + "pmovmskb\t{$src, $dst|$dst, $src}", + [(set GR32orGR64:$dst, (X86movmsk (v16i8 VR128:$src)))]>, + Sched<[WriteVecMOVMSK]>; + +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// SSE2 - Conditional Store +//===---------------------------------------------------------------------===// + +let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecMoveLS.XMM.MR] in { +let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in +def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs), + (ins VR128:$src, VR128:$mask), + "maskmovdqu\t{$mask, $src|$src, $mask}", + [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, + VEX, VEX_WIG; +let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in +def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs), + (ins VR128:$src, VR128:$mask), + "maskmovdqu\t{$mask, $src|$src, $mask}", + [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, + VEX, VEX_WIG; + +let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in +def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask), + "maskmovdqu\t{$mask, $src|$src, $mask}", + [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>; +let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in +def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask), + "maskmovdqu\t{$mask, $src|$src, $mask}", + [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>; + +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// SSE2 - Move Doubleword/Quadword +//===---------------------------------------------------------------------===// + +//===---------------------------------------------------------------------===// +// Move Int Doubleword to Packed Double Int +// +let ExeDomain = SSEPackedInt in { +def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (scalar_to_vector GR32:$src)))]>, + VEX, Sched<[WriteVecMoveFromGpr]>; +def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>, + VEX, Sched<[WriteVecLoad]>; +def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector GR64:$src)))]>, + VEX, Sched<[WriteVecMoveFromGpr]>; +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in +def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), + "movq\t{$src, $dst|$dst, $src}", []>, + VEX, Sched<[WriteVecLoad]>; +let isCodeGenOnly = 1 in +def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (bitconvert GR64:$src))]>, + VEX, Sched<[WriteVecMoveFromGpr]>; + +def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (scalar_to_vector GR32:$src)))]>, + Sched<[WriteVecMoveFromGpr]>; +def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>, + Sched<[WriteVecLoad]>; +def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector GR64:$src)))]>, + Sched<[WriteVecMoveFromGpr]>; +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in +def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), + "movq\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteVecLoad]>; +let isCodeGenOnly = 1 in +def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (bitconvert GR64:$src))]>, + Sched<[WriteVecMoveFromGpr]>; +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// Move Int Doubleword to Single Scalar +// +let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in { + def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set FR32:$dst, (bitconvert GR32:$src))]>, + VEX, Sched<[WriteVecMoveFromGpr]>; + + def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>, + VEX, Sched<[WriteVecLoad]>; + def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set FR32:$dst, (bitconvert GR32:$src))]>, + Sched<[WriteVecMoveFromGpr]>; + + def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>, + Sched<[WriteVecLoad]>; +} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1 + +//===---------------------------------------------------------------------===// +// Move Packed Doubleword Int to Packed Double Int +// +let ExeDomain = SSEPackedInt in { +def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (extractelt (v4i32 VR128:$src), + (iPTR 0)))]>, VEX, + Sched<[WriteVecMoveToGpr]>; +def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs), + (ins i32mem:$dst, VR128:$src), + "movd\t{$src, $dst|$dst, $src}", + [(store (i32 (extractelt (v4i32 VR128:$src), + (iPTR 0))), addr:$dst)]>, + VEX, Sched<[WriteVecStore]>; +def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (extractelt (v4i32 VR128:$src), + (iPTR 0)))]>, + Sched<[WriteVecMoveToGpr]>; +def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src), + "movd\t{$src, $dst|$dst, $src}", + [(store (i32 (extractelt (v4i32 VR128:$src), + (iPTR 0))), addr:$dst)]>, + Sched<[WriteVecStore]>; +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// Move Packed Doubleword Int first element to Doubleword Int +// +let ExeDomain = SSEPackedInt in { +let SchedRW = [WriteVecMoveToGpr] in { +def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (extractelt (v2i64 VR128:$src), + (iPTR 0)))]>, + VEX; + +def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (extractelt (v2i64 VR128:$src), + (iPTR 0)))]>; +} //SchedRW + +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in +def VMOVPQIto64mr : VRS2I<0x7E, MRMDestMem, (outs), + (ins i64mem:$dst, VR128:$src), + "movq\t{$src, $dst|$dst, $src}", []>, + VEX, Sched<[WriteVecStore]>; +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in +def MOVPQIto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), + "movq\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteVecStore]>; +} // ExeDomain = SSEPackedInt + +//===---------------------------------------------------------------------===// +// Bitcast FR64 <-> GR64 +// +let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in { + let Predicates = [UseAVX] in + def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>, + VEX, Sched<[WriteVecLoad]>; + def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (bitconvert FR64:$src))]>, + VEX, Sched<[WriteVecMoveToGpr]>; + def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>, + VEX, Sched<[WriteVecStore]>; + + def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>, + Sched<[WriteVecLoad]>; + def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (bitconvert FR64:$src))]>, + Sched<[WriteVecMoveToGpr]>; + def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>, + Sched<[WriteVecStore]>; +} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1 + +//===---------------------------------------------------------------------===// +// Move Scalar Single to Double Int +// +let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in { + def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (bitconvert FR32:$src))]>, + VEX, Sched<[WriteVecMoveToGpr]>; + def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, + VEX, Sched<[WriteVecStore]>; + def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (bitconvert FR32:$src))]>, + Sched<[WriteVecMoveToGpr]>; + def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src), + "movd\t{$src, $dst|$dst, $src}", + [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, + Sched<[WriteVecStore]>; +} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1 + +let Predicates = [UseAVX] in { + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))), + (VMOVDI2PDIrr GR32:$src)>; + + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))), + (VMOV64toPQIrr GR64:$src)>; + + def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, + (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOV64toPQIrr GR64:$src)), sub_xmm)>; + // AVX 128-bit movd/movq instructions write zeros in the high 128-bit part. + // These instructions also write zeros in the high part of a 256-bit register. + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (zextloadi64i32 addr:$src))))), + (VMOVDI2PDIrm addr:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))), + (VMOVDI2PDIrm addr:$src)>; + def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))), + (VMOVDI2PDIrm addr:$src)>; + def : Pat<(v4i32 (X86vzload addr:$src)), + (VMOVDI2PDIrm addr:$src)>; + def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIrm addr:$src)), sub_xmm)>; + def : Pat<(v8i32 (X86vzload addr:$src)), + (SUBREG_TO_REG (i64 0), (v4i32 (VMOVDI2PDIrm addr:$src)), sub_xmm)>; + // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext. + def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIrr GR32:$src)), sub_xmm)>; +} + +let Predicates = [UseSSE2] in { + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))), + (MOVDI2PDIrr GR32:$src)>; + + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))), + (MOV64toPQIrr GR64:$src)>; + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (zextloadi64i32 addr:$src))))), + (MOVDI2PDIrm addr:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))), + (MOVDI2PDIrm addr:$src)>; + def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))), + (MOVDI2PDIrm addr:$src)>; + def : Pat<(v4i32 (X86vzload addr:$src)), + (MOVDI2PDIrm addr:$src)>; +} + +// Before the MC layer of LLVM existed, clang emitted "movd" assembly instead of +// "movq" due to MacOS parsing limitation. In order to parse old assembly, we add +// these aliases. +def : InstAlias<"movd\t{$src, $dst|$dst, $src}", + (MOV64toPQIrr VR128:$dst, GR64:$src), 0>; +def : InstAlias<"movd\t{$src, $dst|$dst, $src}", + (MOVPQIto64rr GR64:$dst, VR128:$src), 0>; +// Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX. +def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}", + (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>; +def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}", + (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>; + +//===---------------------------------------------------------------------===// +// SSE2 - Move Quadword +//===---------------------------------------------------------------------===// + +//===---------------------------------------------------------------------===// +// Move Quadword Int to Packed Quadword Int +// + +let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLoad] in { +def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS, + VEX, Requires<[UseAVX]>, VEX_WIG; +def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, + XS, Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix +} // ExeDomain, SchedRW + +//===---------------------------------------------------------------------===// +// Move Packed Quadword Int to Quadword Int +// +let ExeDomain = SSEPackedInt, SchedRW = [WriteVecStore] in { +def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), + "movq\t{$src, $dst|$dst, $src}", + [(store (i64 (extractelt (v2i64 VR128:$src), + (iPTR 0))), addr:$dst)]>, + VEX, VEX_WIG; +def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), + "movq\t{$src, $dst|$dst, $src}", + [(store (i64 (extractelt (v2i64 VR128:$src), + (iPTR 0))), addr:$dst)]>; +} // ExeDomain, SchedRW + +// For disassembler only +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, + SchedRW = [SchedWriteVecLogic.XMM] in { +def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_WIG; +def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), + "movq\t{$src, $dst|$dst, $src}", []>; +} + +// Aliases to help the assembler pick two byte VEX encodings by swapping the +// operands relative to the normal instructions to use VEX.R instead of VEX.B. +def : InstAlias<"vmovq\t{$src, $dst|$dst, $src}", + (VMOVPQI2QIrr VR128L:$dst, VR128H:$src), 0>; + +def : InstAlias<"vmovq.s\t{$src, $dst|$dst, $src}", + (VMOVPQI2QIrr VR128:$dst, VR128:$src), 0>; +def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}", + (MOVPQI2QIrr VR128:$dst, VR128:$src), 0>; + +let Predicates = [UseAVX] in { + def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))), + (VMOVQI2PQIrm addr:$src)>; + def : Pat<(v2i64 (X86vzload addr:$src)), + (VMOVQI2PQIrm addr:$src)>; + def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, + (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIrm addr:$src)), sub_xmm)>; + def : Pat<(v4i64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIrm addr:$src)), sub_xmm)>; +} + +let Predicates = [UseSSE2] in { + def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))), + (MOVQI2PQIrm addr:$src)>; + def : Pat<(v2i64 (X86vzload addr:$src)), (MOVQI2PQIrm addr:$src)>; +} + +//===---------------------------------------------------------------------===// +// Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in +// IA32 document. movq xmm1, xmm2 does clear the high bits. +// +let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecLogic.XMM] in { +def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "vmovq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>, + XS, VEX, Requires<[UseAVX]>, VEX_WIG; +def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>, + XS, Requires<[UseSSE2]>; +} // ExeDomain, SchedRW + +let Predicates = [UseAVX] in { + def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))), + (VMOVZPQILo2PQIrr VR128:$src)>; +} +let Predicates = [UseSSE2] in { + def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))), + (MOVZPQILo2PQIrr VR128:$src)>; +} + +//===---------------------------------------------------------------------===// +// SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP +//===---------------------------------------------------------------------===// + +multiclass sse3_replicate_sfp op, SDNode OpNode, string OpcodeStr, + ValueType vt, RegisterClass RC, PatFrag mem_frag, + X86MemOperand x86memop, X86FoldableSchedWrite sched> { +def rr : S3SI, + Sched<[sched]>; +def rm : S3SI, + Sched<[sched.Folded]>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup", + v4f32, VR128, loadv4f32, f128mem, + SchedWriteFShuffle.XMM>, VEX, VEX_WIG; + defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup", + v4f32, VR128, loadv4f32, f128mem, + SchedWriteFShuffle.XMM>, VEX, VEX_WIG; + defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup", + v8f32, VR256, loadv8f32, f256mem, + SchedWriteFShuffle.YMM>, VEX, VEX_L, VEX_WIG; + defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup", + v8f32, VR256, loadv8f32, f256mem, + SchedWriteFShuffle.YMM>, VEX, VEX_L, VEX_WIG; +} +defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128, + memopv4f32, f128mem, SchedWriteFShuffle.XMM>; +defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128, + memopv4f32, f128mem, SchedWriteFShuffle.XMM>; + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4i32 (X86Movshdup VR128:$src)), + (VMOVSHDUPrr VR128:$src)>; + def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))), + (VMOVSHDUPrm addr:$src)>; + def : Pat<(v4i32 (X86Movsldup VR128:$src)), + (VMOVSLDUPrr VR128:$src)>; + def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))), + (VMOVSLDUPrm addr:$src)>; + def : Pat<(v8i32 (X86Movshdup VR256:$src)), + (VMOVSHDUPYrr VR256:$src)>; + def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))), + (VMOVSHDUPYrm addr:$src)>; + def : Pat<(v8i32 (X86Movsldup VR256:$src)), + (VMOVSLDUPYrr VR256:$src)>; + def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))), + (VMOVSLDUPYrm addr:$src)>; +} + +let Predicates = [UseSSE3] in { + def : Pat<(v4i32 (X86Movshdup VR128:$src)), + (MOVSHDUPrr VR128:$src)>; + def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))), + (MOVSHDUPrm addr:$src)>; + def : Pat<(v4i32 (X86Movsldup VR128:$src)), + (MOVSLDUPrr VR128:$src)>; + def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))), + (MOVSLDUPrm addr:$src)>; +} + +//===---------------------------------------------------------------------===// +// SSE3 - Replicate Double FP - MOVDDUP +//===---------------------------------------------------------------------===// + +multiclass sse3_replicate_dfp { +def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))]>, + Sched<[sched.XMM]>; +def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set VR128:$dst, + (v2f64 (X86Movddup + (scalar_to_vector (loadf64 addr:$src)))))]>, + Sched<[sched.XMM.Folded]>; +} + +// FIXME: Merge with above classes when there are patterns for the ymm version +multiclass sse3_replicate_dfp_y { +def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>, + Sched<[sched.YMM]>; +def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + [(set VR256:$dst, + (v4f64 (X86Movddup (loadv4f64 addr:$src))))]>, + Sched<[sched.YMM.Folded]>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm VMOVDDUP : sse3_replicate_dfp<"vmovddup", SchedWriteFShuffle>, + VEX, VEX_WIG; + defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup", SchedWriteFShuffle>, + VEX, VEX_L, VEX_WIG; +} + +defm MOVDDUP : sse3_replicate_dfp<"movddup", SchedWriteFShuffle>; + + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(X86Movddup (loadv2f64 addr:$src)), + (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; +} + +let Predicates = [UseSSE3] in { + // No need for aligned memory as this only loads 64-bits. + def : Pat<(X86Movddup (loadv2f64 addr:$src)), + (MOVDDUPrm addr:$src)>; +} + +//===---------------------------------------------------------------------===// +// SSE3 - Move Unaligned Integer +//===---------------------------------------------------------------------===// + +let Predicates = [HasAVX] in { + def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "vlddqu\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, + Sched<[SchedWriteVecMoveLS.XMM.RM]>, VEX, VEX_WIG; + def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src), + "vlddqu\t{$src, $dst|$dst, $src}", + [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, + Sched<[SchedWriteVecMoveLS.YMM.RM]>, VEX, VEX_L, VEX_WIG; +} // Predicates + +def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "lddqu\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, + Sched<[SchedWriteVecMoveLS.XMM.RM]>; + +//===---------------------------------------------------------------------===// +// SSE3 - Arithmetic +//===---------------------------------------------------------------------===// + +multiclass sse3_addsub { + def rr : I<0xD0, MRMSrcReg, + (outs RC:$dst), (ins RC:$src1, RC:$src2), + !if(Is2Addr, + !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), + [(set RC:$dst, (vt (X86Addsub RC:$src1, RC:$src2)))]>, + Sched<[sched]>; + def rm : I<0xD0, MRMSrcMem, + (outs RC:$dst), (ins RC:$src1, x86memop:$src2), + !if(Is2Addr, + !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), + [(set RC:$dst, (vt (X86Addsub RC:$src1, (ld_frag addr:$src2))))]>, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX] in { + let ExeDomain = SSEPackedSingle in { + defm VADDSUBPS : sse3_addsub<"vaddsubps", v4f32, VR128, f128mem, + SchedWriteFAddSizes.PS.XMM, loadv4f32, 0>, + XD, VEX_4V, VEX_WIG; + defm VADDSUBPSY : sse3_addsub<"vaddsubps", v8f32, VR256, f256mem, + SchedWriteFAddSizes.PS.YMM, loadv8f32, 0>, + XD, VEX_4V, VEX_L, VEX_WIG; + } + let ExeDomain = SSEPackedDouble in { + defm VADDSUBPD : sse3_addsub<"vaddsubpd", v2f64, VR128, f128mem, + SchedWriteFAddSizes.PD.XMM, loadv2f64, 0>, + PD, VEX_4V, VEX_WIG; + defm VADDSUBPDY : sse3_addsub<"vaddsubpd", v4f64, VR256, f256mem, + SchedWriteFAddSizes.PD.YMM, loadv4f64, 0>, + PD, VEX_4V, VEX_L, VEX_WIG; + } +} +let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in { + let ExeDomain = SSEPackedSingle in + defm ADDSUBPS : sse3_addsub<"addsubps", v4f32, VR128, f128mem, + SchedWriteFAddSizes.PS.XMM, memopv4f32>, XD; + let ExeDomain = SSEPackedDouble in + defm ADDSUBPD : sse3_addsub<"addsubpd", v2f64, VR128, f128mem, + SchedWriteFAddSizes.PD.XMM, memopv2f64>, PD; +} + +//===---------------------------------------------------------------------===// +// SSE3 Instructions +//===---------------------------------------------------------------------===// + +// Horizontal ops +multiclass S3D_Int o, string OpcodeStr, ValueType vt, RegisterClass RC, + X86MemOperand x86memop, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag ld_frag, + bit Is2Addr = 1> { + def rr : S3DI, + Sched<[sched]>; + + def rm : S3DI, + Sched<[sched.Folded, ReadAfterLd]>; +} +multiclass S3_Int o, string OpcodeStr, ValueType vt, RegisterClass RC, + X86MemOperand x86memop, SDNode OpNode, + X86FoldableSchedWrite sched, PatFrag ld_frag, + bit Is2Addr = 1> { + def rr : S3I, + Sched<[sched]>; + + def rm : S3I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX] in { + let ExeDomain = SSEPackedSingle in { + defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem, + X86fhadd, WriteFHAdd, loadv4f32, 0>, VEX_4V, VEX_WIG; + defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem, + X86fhsub, WriteFHAdd, loadv4f32, 0>, VEX_4V, VEX_WIG; + defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem, + X86fhadd, WriteFHAddY, loadv8f32, 0>, VEX_4V, VEX_L, VEX_WIG; + defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem, + X86fhsub, WriteFHAddY, loadv8f32, 0>, VEX_4V, VEX_L, VEX_WIG; + } + let ExeDomain = SSEPackedDouble in { + defm VHADDPD : S3_Int<0x7C, "vhaddpd", v2f64, VR128, f128mem, + X86fhadd, WriteFHAdd, loadv2f64, 0>, VEX_4V, VEX_WIG; + defm VHSUBPD : S3_Int<0x7D, "vhsubpd", v2f64, VR128, f128mem, + X86fhsub, WriteFHAdd, loadv2f64, 0>, VEX_4V, VEX_WIG; + defm VHADDPDY : S3_Int<0x7C, "vhaddpd", v4f64, VR256, f256mem, + X86fhadd, WriteFHAddY, loadv4f64, 0>, VEX_4V, VEX_L, VEX_WIG; + defm VHSUBPDY : S3_Int<0x7D, "vhsubpd", v4f64, VR256, f256mem, + X86fhsub, WriteFHAddY, loadv4f64, 0>, VEX_4V, VEX_L, VEX_WIG; + } +} + +let Constraints = "$src1 = $dst" in { + let ExeDomain = SSEPackedSingle in { + defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd, + WriteFHAdd, memopv4f32>; + defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub, + WriteFHAdd, memopv4f32>; + } + let ExeDomain = SSEPackedDouble in { + defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd, + WriteFHAdd, memopv2f64>; + defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub, + WriteFHAdd, memopv2f64>; + } +} + +//===---------------------------------------------------------------------===// +// SSSE3 - Packed Absolute Instructions +//===---------------------------------------------------------------------===// + +/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}. +multiclass SS3I_unop_rm opc, string OpcodeStr, ValueType vt, + SDNode OpNode, X86SchedWriteWidths sched, PatFrag ld_frag> { + def rr : SS38I, + Sched<[sched.XMM]>; + + def rm : SS38I, + Sched<[sched.XMM.Folded]>; +} + +/// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}. +multiclass SS3I_unop_rm_y opc, string OpcodeStr, ValueType vt, + SDNode OpNode, X86SchedWriteWidths sched> { + def Yrr : SS38I, + Sched<[sched.YMM]>; + + def Yrm : SS38I, + Sched<[sched.YMM.Folded]>; +} + +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + defm VPABSB : SS3I_unop_rm<0x1C, "vpabsb", v16i8, abs, SchedWriteVecALU, + loadv2i64>, VEX, VEX_WIG; + defm VPABSW : SS3I_unop_rm<0x1D, "vpabsw", v8i16, abs, SchedWriteVecALU, + loadv2i64>, VEX, VEX_WIG; +} +let Predicates = [HasAVX, NoVLX] in { + defm VPABSD : SS3I_unop_rm<0x1E, "vpabsd", v4i32, abs, SchedWriteVecALU, + loadv2i64>, VEX, VEX_WIG; +} +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { + defm VPABSB : SS3I_unop_rm_y<0x1C, "vpabsb", v32i8, abs, SchedWriteVecALU>, + VEX, VEX_L, VEX_WIG; + defm VPABSW : SS3I_unop_rm_y<0x1D, "vpabsw", v16i16, abs, SchedWriteVecALU>, + VEX, VEX_L, VEX_WIG; +} +let Predicates = [HasAVX2, NoVLX] in { + defm VPABSD : SS3I_unop_rm_y<0x1E, "vpabsd", v8i32, abs, SchedWriteVecALU>, + VEX, VEX_L, VEX_WIG; +} + +defm PABSB : SS3I_unop_rm<0x1C, "pabsb", v16i8, abs, SchedWriteVecALU, + memopv2i64>; +defm PABSW : SS3I_unop_rm<0x1D, "pabsw", v8i16, abs, SchedWriteVecALU, + memopv2i64>; +defm PABSD : SS3I_unop_rm<0x1E, "pabsd", v4i32, abs, SchedWriteVecALU, + memopv2i64>; + +//===---------------------------------------------------------------------===// +// SSSE3 - Packed Binary Operator Instructions +//===---------------------------------------------------------------------===// + +/// SS3I_binop_rm - Simple SSSE3 bin op +multiclass SS3I_binop_rm opc, string OpcodeStr, SDNode OpNode, + ValueType DstVT, ValueType OpVT, RegisterClass RC, + PatFrag memop_frag, X86MemOperand x86memop, + X86FoldableSchedWrite sched, bit Is2Addr = 1> { + let isCommutable = 1 in + def rr : SS38I, + Sched<[sched]>; + def rm : SS38I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +/// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}. +multiclass SS3I_binop_rm_int opc, string OpcodeStr, + Intrinsic IntId128, X86FoldableSchedWrite sched, + PatFrag ld_frag, bit Is2Addr = 1> { + let isCommutable = 1 in + def rr : SS38I, + Sched<[sched]>; + def rm : SS38I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass SS3I_binop_rm_int_y opc, string OpcodeStr, + Intrinsic IntId256, + X86FoldableSchedWrite sched> { + let isCommutable = 1 in + def Yrr : SS38I, + Sched<[sched]>; + def Yrm : SS38I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let ImmT = NoImm, Predicates = [HasAVX, NoVLX_Or_NoBWI] in { +let isCommutable = 0 in { + defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, v16i8, + VR128, loadv2i64, i128mem, + SchedWriteVarShuffle.XMM, 0>, VEX_4V, VEX_WIG; + defm VPMADDUBSW : SS3I_binop_rm<0x04, "vpmaddubsw", X86vpmaddubsw, v8i16, + v16i8, VR128, loadv2i64, i128mem, + SchedWriteVecIMul.XMM, 0>, VEX_4V, VEX_WIG; +} +defm VPMULHRSW : SS3I_binop_rm<0x0B, "vpmulhrsw", X86mulhrs, v8i16, v8i16, + VR128, loadv2i64, i128mem, + SchedWriteVecIMul.XMM, 0>, VEX_4V, VEX_WIG; +} + +let ImmT = NoImm, Predicates = [HasAVX] in { +let isCommutable = 0 in { + defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, v8i16, VR128, + loadv2i64, i128mem, + SchedWritePHAdd.XMM, 0>, VEX_4V, VEX_WIG; + defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, v4i32, VR128, + loadv2i64, i128mem, + SchedWritePHAdd.XMM, 0>, VEX_4V, VEX_WIG; + defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, v8i16, VR128, + loadv2i64, i128mem, + SchedWritePHAdd.XMM, 0>, VEX_4V, VEX_WIG; + defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, v4i32, VR128, + loadv2i64, i128mem, + SchedWritePHAdd.XMM, 0>, VEX_4V; + defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", + int_x86_ssse3_psign_b_128, + SchedWriteVecALU.XMM, loadv2i64, 0>, VEX_4V, VEX_WIG; + defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", + int_x86_ssse3_psign_w_128, + SchedWriteVecALU.XMM, loadv2i64, 0>, VEX_4V, VEX_WIG; + defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", + int_x86_ssse3_psign_d_128, + SchedWriteVecALU.XMM, loadv2i64, 0>, VEX_4V, VEX_WIG; + defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", + int_x86_ssse3_phadd_sw_128, + SchedWritePHAdd.XMM, loadv2i64, 0>, VEX_4V, VEX_WIG; + defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", + int_x86_ssse3_phsub_sw_128, + SchedWritePHAdd.XMM, loadv2i64, 0>, VEX_4V, VEX_WIG; +} +} + +let ImmT = NoImm, Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { +let isCommutable = 0 in { + defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, v32i8, + VR256, loadv4i64, i256mem, + SchedWriteVarShuffle.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; + defm VPMADDUBSWY : SS3I_binop_rm<0x04, "vpmaddubsw", X86vpmaddubsw, v16i16, + v32i8, VR256, loadv4i64, i256mem, + SchedWriteVecIMul.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; +} +defm VPMULHRSWY : SS3I_binop_rm<0x0B, "vpmulhrsw", X86mulhrs, v16i16, v16i16, + VR256, loadv4i64, i256mem, + SchedWriteVecIMul.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; +} + +let ImmT = NoImm, Predicates = [HasAVX2] in { +let isCommutable = 0 in { + defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, v16i16, + VR256, loadv4i64, i256mem, + SchedWritePHAdd.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; + defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, v8i32, VR256, + loadv4i64, i256mem, + SchedWritePHAdd.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; + defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, v16i16, + VR256, loadv4i64, i256mem, + SchedWritePHAdd.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; + defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, v8i32, VR256, + loadv4i64, i256mem, + SchedWritePHAdd.YMM, 0>, VEX_4V, VEX_L; + defm VPSIGNB : SS3I_binop_rm_int_y<0x08, "vpsignb", int_x86_avx2_psign_b, + SchedWriteVecALU.YMM>, VEX_4V, VEX_L, VEX_WIG; + defm VPSIGNW : SS3I_binop_rm_int_y<0x09, "vpsignw", int_x86_avx2_psign_w, + SchedWriteVecALU.YMM>, VEX_4V, VEX_L, VEX_WIG; + defm VPSIGND : SS3I_binop_rm_int_y<0x0A, "vpsignd", int_x86_avx2_psign_d, + SchedWriteVecALU.YMM>, VEX_4V, VEX_L, VEX_WIG; + defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw", + int_x86_avx2_phadd_sw, + SchedWritePHAdd.YMM>, VEX_4V, VEX_L, VEX_WIG; + defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw", + int_x86_avx2_phsub_sw, + SchedWritePHAdd.YMM>, VEX_4V, VEX_L, VEX_WIG; +} +} + +// None of these have i8 immediate fields. +let ImmT = NoImm, Constraints = "$src1 = $dst" in { +let isCommutable = 0 in { + defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, v8i16, VR128, + memopv2i64, i128mem, SchedWritePHAdd.XMM>; + defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, v4i32, VR128, + memopv2i64, i128mem, SchedWritePHAdd.XMM>; + defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, v8i16, VR128, + memopv2i64, i128mem, SchedWritePHAdd.XMM>; + defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, v4i32, VR128, + memopv2i64, i128mem, SchedWritePHAdd.XMM>; + defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", int_x86_ssse3_psign_b_128, + SchedWriteVecALU.XMM, memopv2i64>; + defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", int_x86_ssse3_psign_w_128, + SchedWriteVecALU.XMM, memopv2i64>; + defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", int_x86_ssse3_psign_d_128, + SchedWriteVecALU.XMM, memopv2i64>; + defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, v16i8, VR128, + memopv2i64, i128mem, SchedWriteVarShuffle.XMM>; + defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", + int_x86_ssse3_phadd_sw_128, + SchedWritePHAdd.XMM, memopv2i64>; + defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", + int_x86_ssse3_phsub_sw_128, + SchedWritePHAdd.XMM, memopv2i64>; + defm PMADDUBSW : SS3I_binop_rm<0x04, "pmaddubsw", X86vpmaddubsw, v8i16, + v16i8, VR128, memopv2i64, i128mem, + SchedWriteVecIMul.XMM>; +} +defm PMULHRSW : SS3I_binop_rm<0x0B, "pmulhrsw", X86mulhrs, v8i16, v8i16, + VR128, memopv2i64, i128mem, SchedWriteVecIMul.XMM>; +} + +//===---------------------------------------------------------------------===// +// SSSE3 - Packed Align Instruction Patterns +//===---------------------------------------------------------------------===// + +multiclass ssse3_palignr { + let hasSideEffects = 0 in { + def rri : SS3AI<0x0F, MRMSrcReg, (outs RC:$dst), + (ins RC:$src1, RC:$src2, u8imm:$src3), + !if(Is2Addr, + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + !strconcat(asm, + "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")), + [(set RC:$dst, (VT (X86PAlignr RC:$src1, RC:$src2, (i8 imm:$src3))))]>, + Sched<[sched]>; + let mayLoad = 1 in + def rmi : SS3AI<0x0F, MRMSrcMem, (outs RC:$dst), + (ins RC:$src1, x86memop:$src2, u8imm:$src3), + !if(Is2Addr, + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + !strconcat(asm, + "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")), + [(set RC:$dst, (VT (X86PAlignr RC:$src1, + (bitconvert (memop_frag addr:$src2)), + (i8 imm:$src3))))]>, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in + defm VPALIGNR : ssse3_palignr<"vpalignr", v16i8, VR128, loadv2i64, i128mem, + SchedWriteShuffle.XMM, 0>, VEX_4V, VEX_WIG; +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in + defm VPALIGNRY : ssse3_palignr<"vpalignr", v32i8, VR256, loadv4i64, i256mem, + SchedWriteShuffle.YMM, 0>, VEX_4V, VEX_L, VEX_WIG; +let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in + defm PALIGNR : ssse3_palignr<"palignr", v16i8, VR128, memopv2i64, i128mem, + SchedWriteShuffle.XMM>; + +//===---------------------------------------------------------------------===// +// SSSE3 - Thread synchronization +//===---------------------------------------------------------------------===// + +let SchedRW = [WriteSystem] in { +/* +let usesCustomInserter = 1 in { +def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3), + [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>, + Requires<[HasSSE3]>; +} +*/ + +let Uses = [EAX, ECX, EDX] in +def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, + TB, Requires<[HasSSE3]>; + +let Uses = [ECX, EAX] in +def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", + [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>; +} // SchedRW + +def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>; +def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>; + +def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>, + Requires<[Not64BitMode]>; +def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>, + Requires<[In64BitMode]>; + +//===----------------------------------------------------------------------===// +// SSE4.1 - Packed Move with Sign/Zero Extend +//===----------------------------------------------------------------------===// + +multiclass SS41I_pmovx_rrrm opc, string OpcodeStr, X86MemOperand MemOp, + RegisterClass OutRC, RegisterClass InRC, + X86FoldableSchedWrite sched> { + def rr : SS48I, + Sched<[sched]>; + + def rm : SS48I, + Sched<[sched.Folded]>; +} + +multiclass SS41I_pmovx_rm_all opc, string OpcodeStr, + X86MemOperand MemOp, X86MemOperand MemYOp, + Predicate prd> { + defm NAME : SS41I_pmovx_rrrm; + let Predicates = [HasAVX, prd] in + defm V#NAME : SS41I_pmovx_rrrm, + VEX, VEX_WIG; + let Predicates = [HasAVX2, prd] in + defm V#NAME#Y : SS41I_pmovx_rrrm, + VEX, VEX_L, VEX_WIG; +} + +multiclass SS41I_pmovx_rm opc, string OpcodeStr, X86MemOperand MemOp, + X86MemOperand MemYOp, Predicate prd> { + defm PMOVSX#NAME : SS41I_pmovx_rm_all; + defm PMOVZX#NAME : SS41I_pmovx_rm_all; +} + +defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem, NoVLX_Or_NoBWI>; +defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem, NoVLX>; +defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem, NoVLX>; + +defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem, NoVLX>; +defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem, NoVLX>; + +defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem, NoVLX>; + +// AVX2 Patterns +multiclass SS41I_pmovx_avx2_patterns { + // Register-Register patterns + let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))), + (!cast(OpcPrefix#BWYrr) VR128:$src)>; + } + let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))), + (!cast(OpcPrefix#BDYrr) VR128:$src)>; + def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))), + (!cast(OpcPrefix#BQYrr) VR128:$src)>; + + def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))), + (!cast(OpcPrefix#WDYrr) VR128:$src)>; + def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))), + (!cast(OpcPrefix#WQYrr) VR128:$src)>; + + def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))), + (!cast(OpcPrefix#DQYrr) VR128:$src)>; + } + + // Simple Register-Memory patterns + let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + def : Pat<(v16i16 (!cast(ExtTy#"extloadvi8") addr:$src)), + (!cast(OpcPrefix#BWYrm) addr:$src)>; + } + let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v8i32 (!cast(ExtTy#"extloadvi8") addr:$src)), + (!cast(OpcPrefix#BDYrm) addr:$src)>; + def : Pat<(v4i64 (!cast(ExtTy#"extloadvi8") addr:$src)), + (!cast(OpcPrefix#BQYrm) addr:$src)>; + + def : Pat<(v8i32 (!cast(ExtTy#"extloadvi16") addr:$src)), + (!cast(OpcPrefix#WDYrm) addr:$src)>; + def : Pat<(v4i64 (!cast(ExtTy#"extloadvi16") addr:$src)), + (!cast(OpcPrefix#WQYrm) addr:$src)>; + + def : Pat<(v4i64 (!cast(ExtTy#"extloadvi32") addr:$src)), + (!cast(OpcPrefix#DQYrm) addr:$src)>; + } + + // AVX2 Register-Memory patterns + let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BWYrm) addr:$src)>; + def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWYrm) addr:$src)>; + def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWYrm) addr:$src)>; + } + let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#BDYrm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#BDYrm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BDYrm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BDYrm) addr:$src)>; + + def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))), + (!cast(OpcPrefix#BQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#BQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BQYrm) addr:$src)>; + + def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WDYrm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDYrm) addr:$src)>; + def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDYrm) addr:$src)>; + + def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#WQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#WQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WQYrm) addr:$src)>; + + def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#DQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQYrm) addr:$src)>; + def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQYrm) addr:$src)>; + } +} + +defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>; +defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>; + +// SSE4.1/AVX patterns. +multiclass SS41I_pmovx_patterns { + let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))), + (!cast(OpcPrefix#BWrr) VR128:$src)>; + } + let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))), + (!cast(OpcPrefix#BDrr) VR128:$src)>; + def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))), + (!cast(OpcPrefix#BQrr) VR128:$src)>; + + def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))), + (!cast(OpcPrefix#WDrr) VR128:$src)>; + def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))), + (!cast(OpcPrefix#WQrr) VR128:$src)>; + + def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))), + (!cast(OpcPrefix#DQrr) VR128:$src)>; + } + let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + def : Pat<(v8i16 (!cast(ExtTy#"extloadvi8") addr:$src)), + (!cast(OpcPrefix#BWrm) addr:$src)>; + } + let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4i32 (!cast(ExtTy#"extloadvi8") addr:$src)), + (!cast(OpcPrefix#BDrm) addr:$src)>; + def : Pat<(v2i64 (!cast(ExtTy#"extloadvi8") addr:$src)), + (!cast(OpcPrefix#BQrm) addr:$src)>; + + def : Pat<(v4i32 (!cast(ExtTy#"extloadvi16") addr:$src)), + (!cast(OpcPrefix#WDrm) addr:$src)>; + def : Pat<(v2i64 (!cast(ExtTy#"extloadvi16") addr:$src)), + (!cast(OpcPrefix#WQrm) addr:$src)>; + + def : Pat<(v2i64 (!cast(ExtTy#"extloadvi32") addr:$src)), + (!cast(OpcPrefix#DQrm) addr:$src)>; + } + let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#BWrm) addr:$src)>; + def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))), + (!cast(OpcPrefix#BWrm) addr:$src)>; + def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWrm) addr:$src)>; + def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BWrm) addr:$src)>; + def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BWrm) addr:$src)>; + } + let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))), + (!cast(OpcPrefix#BDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#BDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BDrm) addr:$src)>; + + def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (extloadi32i16 addr:$src)))))), + (!cast(OpcPrefix#BQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#BQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#BQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#BQrm) addr:$src)>; + + def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#WDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))), + (!cast(OpcPrefix#WDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WDrm) addr:$src)>; + def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WDrm) addr:$src)>; + + def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))), + (!cast(OpcPrefix#WQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))), + (!cast(OpcPrefix#WQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#WQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#WQrm) addr:$src)>; + + def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), + (!cast(OpcPrefix#DQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))), + (!cast(OpcPrefix#DQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))), + (!cast(OpcPrefix#DQrm) addr:$src)>; + def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))), + (!cast(OpcPrefix#DQrm) addr:$src)>; + } +} + +defm : SS41I_pmovx_patterns<"VPMOVSX", "s", sext_invec>; +defm : SS41I_pmovx_patterns<"VPMOVZX", "z", zext_invec>; + +let Predicates = [UseSSE41] in { + defm : SS41I_pmovx_patterns<"PMOVSX", "s", sext_invec>; + defm : SS41I_pmovx_patterns<"PMOVZX", "z", zext_invec>; +} + +//===----------------------------------------------------------------------===// +// SSE4.1 - Extract Instructions +//===----------------------------------------------------------------------===// + +/// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem +multiclass SS41I_extract8 opc, string OpcodeStr> { + def rr : SS4AIi8, + Sched<[WriteVecExtract]>; + let hasSideEffects = 0, mayStore = 1 in + def mr : SS4AIi8, Sched<[WriteVecExtractSt]>; +} + +let Predicates = [HasAVX, NoBWI] in + defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX; + +defm PEXTRB : SS41I_extract8<0x14, "pextrb">; + + +/// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination +multiclass SS41I_extract16 opc, string OpcodeStr> { + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rr_REV : SS4AIi8, + Sched<[WriteVecExtract]>, FoldGenData; + + let hasSideEffects = 0, mayStore = 1 in + def mr : SS4AIi8, Sched<[WriteVecExtractSt]>; +} + +let Predicates = [HasAVX, NoBWI] in + defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX; + +defm PEXTRW : SS41I_extract16<0x15, "pextrw">; + + +/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination +multiclass SS41I_extract32 opc, string OpcodeStr> { + def rr : SS4AIi8, + Sched<[WriteVecExtract]>; + def mr : SS4AIi8, Sched<[WriteVecExtractSt]>; +} + +let Predicates = [HasAVX, NoDQI] in + defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX; + +defm PEXTRD : SS41I_extract32<0x16, "pextrd">; + +/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination +multiclass SS41I_extract64 opc, string OpcodeStr> { + def rr : SS4AIi8, + Sched<[WriteVecExtract]>; + def mr : SS4AIi8, Sched<[WriteVecExtractSt]>; +} + +let Predicates = [HasAVX, NoDQI] in + defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W; + +defm PEXTRQ : SS41I_extract64<0x16, "pextrq">, REX_W; + +/// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory +/// destination +multiclass SS41I_extractf32 opc, string OpcodeStr> { + def rr : SS4AIi8, + Sched<[WriteVecExtract]>; + def mr : SS4AIi8, Sched<[WriteVecExtractSt]>; +} + +let ExeDomain = SSEPackedSingle in { + let Predicates = [UseAVX] in + defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX, VEX_WIG; + defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">; +} + +// Also match an EXTRACTPS store when the store is done as f32 instead of i32. +def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)), + imm:$src2))), + addr:$dst), + (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>, + Requires<[HasAVX]>; +def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)), + imm:$src2))), + addr:$dst), + (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>, + Requires<[UseSSE41]>; + +//===----------------------------------------------------------------------===// +// SSE4.1 - Insert Instructions +//===----------------------------------------------------------------------===// + +multiclass SS41I_insert8 opc, string asm, bit Is2Addr = 1> { + def rr : SS4AIi8, + Sched<[WriteVecInsert]>; + def rm : SS4AIi8, Sched<[WriteVecInsertLd, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoBWI] in + defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V; +let Constraints = "$src1 = $dst" in + defm PINSRB : SS41I_insert8<0x20, "pinsrb">; + +multiclass SS41I_insert32 opc, string asm, bit Is2Addr = 1> { + def rr : SS4AIi8, + Sched<[WriteVecInsert]>; + def rm : SS4AIi8, Sched<[WriteVecInsertLd, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoDQI] in + defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V; +let Constraints = "$src1 = $dst" in + defm PINSRD : SS41I_insert32<0x22, "pinsrd">; + +multiclass SS41I_insert64 opc, string asm, bit Is2Addr = 1> { + def rr : SS4AIi8, + Sched<[WriteVecInsert]>; + def rm : SS4AIi8, Sched<[WriteVecInsertLd, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoDQI] in + defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W; +let Constraints = "$src1 = $dst" in + defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W; + +// insertps has a few different modes, there's the first two here below which +// are optimized inserts that won't zero arbitrary elements in the destination +// vector. The next one matches the intrinsic and could zero arbitrary elements +// in the target vector. +multiclass SS41I_insertf32 opc, string asm, bit Is2Addr = 1> { + def rr : SS4AIi8, + Sched<[SchedWriteFShuffle.XMM]>; + def rm : SS4AIi8, + Sched<[SchedWriteFShuffle.XMM.Folded, ReadAfterLd]>; +} + +let ExeDomain = SSEPackedSingle in { + let Predicates = [UseAVX] in + defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, + VEX_4V, VEX_WIG; + let Constraints = "$src1 = $dst" in + defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1>; +} + +let Predicates = [UseAVX] in { + // If we're inserting an element from a vbroadcast of a load, fold the + // load into the X86insertps instruction. + def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), + (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)), + (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>; + def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), + (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)), + (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>; +} + +//===----------------------------------------------------------------------===// +// SSE4.1 - Round Instructions +//===----------------------------------------------------------------------===// + +multiclass sse41_fp_unop_p opc, string OpcodeStr, + X86MemOperand x86memop, RegisterClass RC, + ValueType VT, PatFrag mem_frag, SDNode OpNode, + X86FoldableSchedWrite sched> { + // Intrinsic operation, reg. + // Vector intrinsic operation, reg + def r : SS4AIi8, + Sched<[sched]>; + + // Vector intrinsic operation, mem + def m : SS4AIi8, + Sched<[sched.Folded]>; +} + +multiclass avx_fp_unop_rm opcss, bits<8> opcsd, + string OpcodeStr, X86FoldableSchedWrite sched> { +let ExeDomain = SSEPackedSingle, hasSideEffects = 0 in { + def SSr : SS4AIi8, Sched<[sched]>; + + let mayLoad = 1 in + def SSm : SS4AIi8, Sched<[sched.Folded, ReadAfterLd]>; +} // ExeDomain = SSEPackedSingle, hasSideEffects = 0 + +let ExeDomain = SSEPackedDouble, hasSideEffects = 0 in { + def SDr : SS4AIi8, Sched<[sched]>; + + let mayLoad = 1 in + def SDm : SS4AIi8, Sched<[sched.Folded, ReadAfterLd]>; +} // ExeDomain = SSEPackedDouble, hasSideEffects = 0 +} + +multiclass sse41_fp_unop_s opcss, bits<8> opcsd, + string OpcodeStr, X86FoldableSchedWrite sched> { +let ExeDomain = SSEPackedSingle, hasSideEffects = 0 in { + def SSr : SS4AIi8, Sched<[sched]>; + + let mayLoad = 1 in + def SSm : SS4AIi8, Sched<[sched.Folded, ReadAfterLd]>; +} // ExeDomain = SSEPackedSingle, hasSideEffects = 0 + +let ExeDomain = SSEPackedDouble, hasSideEffects = 0 in { + def SDr : SS4AIi8, Sched<[sched]>; + + let mayLoad = 1 in + def SDm : SS4AIi8, Sched<[sched.Folded, ReadAfterLd]>; +} // ExeDomain = SSEPackedDouble, hasSideEffects = 0 +} + +multiclass sse41_fp_binop_s opcss, bits<8> opcsd, + string OpcodeStr, X86FoldableSchedWrite sched, + ValueType VT32, ValueType VT64, + SDNode OpNode, bit Is2Addr = 1> { +let ExeDomain = SSEPackedSingle, isCodeGenOnly = 1 in { + def SSr_Int : SS4AIi8, + Sched<[sched]>; + + def SSm_Int : SS4AIi8, + Sched<[sched.Folded, ReadAfterLd]>; +} // ExeDomain = SSEPackedSingle, isCodeGenOnly = 1 + +let ExeDomain = SSEPackedDouble, isCodeGenOnly = 1 in { + def SDr_Int : SS4AIi8, + Sched<[sched]>; + + def SDm_Int : SS4AIi8, + Sched<[sched.Folded, ReadAfterLd]>; +} // ExeDomain = SSEPackedDouble, isCodeGenOnly = 1 +} + +// FP round - roundss, roundps, roundsd, roundpd +let Predicates = [HasAVX, NoVLX] in { + let ExeDomain = SSEPackedSingle in { + // Intrinsic form + defm VROUNDPS : sse41_fp_unop_p<0x08, "vroundps", f128mem, VR128, v4f32, + loadv4f32, X86VRndScale, SchedWriteFRnd.XMM>, + VEX, VEX_WIG; + defm VROUNDPSY : sse41_fp_unop_p<0x08, "vroundps", f256mem, VR256, v8f32, + loadv8f32, X86VRndScale, SchedWriteFRnd.YMM>, + VEX, VEX_L, VEX_WIG; + } + + let ExeDomain = SSEPackedDouble in { + defm VROUNDPD : sse41_fp_unop_p<0x09, "vroundpd", f128mem, VR128, v2f64, + loadv2f64, X86VRndScale, SchedWriteFRnd.XMM>, + VEX, VEX_WIG; + defm VROUNDPDY : sse41_fp_unop_p<0x09, "vroundpd", f256mem, VR256, v4f64, + loadv4f64, X86VRndScale, SchedWriteFRnd.YMM>, + VEX, VEX_L, VEX_WIG; + } +} +let Predicates = [HasAVX, NoAVX512] in { + defm VROUND : sse41_fp_binop_s<0x0A, 0x0B, "vround", SchedWriteFRnd.Scl, + v4f32, v2f64, X86RndScales, 0>, + VEX_4V, VEX_LIG, VEX_WIG; + defm VROUND : avx_fp_unop_rm<0x0A, 0x0B, "vround", SchedWriteFRnd.Scl>, + VEX_4V, VEX_LIG, VEX_WIG; +} + +let Predicates = [UseAVX] in { + def : Pat<(ffloor FR32:$src), + (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x9))>; + def : Pat<(f32 (fnearbyint FR32:$src)), + (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>; + def : Pat<(f32 (fceil FR32:$src)), + (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xA))>; + def : Pat<(f32 (frint FR32:$src)), + (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>; + def : Pat<(f32 (ftrunc FR32:$src)), + (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xB))>; + + def : Pat<(f64 (ffloor FR64:$src)), + (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x9))>; + def : Pat<(f64 (fnearbyint FR64:$src)), + (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>; + def : Pat<(f64 (fceil FR64:$src)), + (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xA))>; + def : Pat<(f64 (frint FR64:$src)), + (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>; + def : Pat<(f64 (ftrunc FR64:$src)), + (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xB))>; +} + +let Predicates = [UseAVX, OptForSize] in { + def : Pat<(ffloor (loadf32 addr:$src)), + (VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0x9))>; + def : Pat<(f32 (fnearbyint (loadf32 addr:$src))), + (VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0xC))>; + def : Pat<(f32 (fceil (loadf32 addr:$src))), + (VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0xA))>; + def : Pat<(f32 (frint (loadf32 addr:$src))), + (VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0x4))>; + def : Pat<(f32 (ftrunc (loadf32 addr:$src))), + (VROUNDSSm (f32 (IMPLICIT_DEF)), addr:$src, (i32 0xB))>; + + def : Pat<(f64 (ffloor (loadf64 addr:$src))), + (VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0x9))>; + def : Pat<(f64 (fnearbyint (loadf64 addr:$src))), + (VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0xC))>; + def : Pat<(f64 (fceil (loadf64 addr:$src))), + (VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0xA))>; + def : Pat<(f64 (frint (loadf64 addr:$src))), + (VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0x4))>; + def : Pat<(f64 (ftrunc (loadf64 addr:$src))), + (VROUNDSDm (f64 (IMPLICIT_DEF)), addr:$src, (i32 0xB))>; +} + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4f32 (ffloor VR128:$src)), + (VROUNDPSr VR128:$src, (i32 0x9))>; + def : Pat<(v4f32 (fnearbyint VR128:$src)), + (VROUNDPSr VR128:$src, (i32 0xC))>; + def : Pat<(v4f32 (fceil VR128:$src)), + (VROUNDPSr VR128:$src, (i32 0xA))>; + def : Pat<(v4f32 (frint VR128:$src)), + (VROUNDPSr VR128:$src, (i32 0x4))>; + def : Pat<(v4f32 (ftrunc VR128:$src)), + (VROUNDPSr VR128:$src, (i32 0xB))>; + + def : Pat<(v4f32 (ffloor (loadv4f32 addr:$src))), + (VROUNDPSm addr:$src, (i32 0x9))>; + def : Pat<(v4f32 (fnearbyint (loadv4f32 addr:$src))), + (VROUNDPSm addr:$src, (i32 0xC))>; + def : Pat<(v4f32 (fceil (loadv4f32 addr:$src))), + (VROUNDPSm addr:$src, (i32 0xA))>; + def : Pat<(v4f32 (frint (loadv4f32 addr:$src))), + (VROUNDPSm addr:$src, (i32 0x4))>; + def : Pat<(v4f32 (ftrunc (loadv4f32 addr:$src))), + (VROUNDPSm addr:$src, (i32 0xB))>; + + def : Pat<(v2f64 (ffloor VR128:$src)), + (VROUNDPDr VR128:$src, (i32 0x9))>; + def : Pat<(v2f64 (fnearbyint VR128:$src)), + (VROUNDPDr VR128:$src, (i32 0xC))>; + def : Pat<(v2f64 (fceil VR128:$src)), + (VROUNDPDr VR128:$src, (i32 0xA))>; + def : Pat<(v2f64 (frint VR128:$src)), + (VROUNDPDr VR128:$src, (i32 0x4))>; + def : Pat<(v2f64 (ftrunc VR128:$src)), + (VROUNDPDr VR128:$src, (i32 0xB))>; + + def : Pat<(v2f64 (ffloor (loadv2f64 addr:$src))), + (VROUNDPDm addr:$src, (i32 0x9))>; + def : Pat<(v2f64 (fnearbyint (loadv2f64 addr:$src))), + (VROUNDPDm addr:$src, (i32 0xC))>; + def : Pat<(v2f64 (fceil (loadv2f64 addr:$src))), + (VROUNDPDm addr:$src, (i32 0xA))>; + def : Pat<(v2f64 (frint (loadv2f64 addr:$src))), + (VROUNDPDm addr:$src, (i32 0x4))>; + def : Pat<(v2f64 (ftrunc (loadv2f64 addr:$src))), + (VROUNDPDm addr:$src, (i32 0xB))>; + + def : Pat<(v8f32 (ffloor VR256:$src)), + (VROUNDPSYr VR256:$src, (i32 0x9))>; + def : Pat<(v8f32 (fnearbyint VR256:$src)), + (VROUNDPSYr VR256:$src, (i32 0xC))>; + def : Pat<(v8f32 (fceil VR256:$src)), + (VROUNDPSYr VR256:$src, (i32 0xA))>; + def : Pat<(v8f32 (frint VR256:$src)), + (VROUNDPSYr VR256:$src, (i32 0x4))>; + def : Pat<(v8f32 (ftrunc VR256:$src)), + (VROUNDPSYr VR256:$src, (i32 0xB))>; + + def : Pat<(v8f32 (ffloor (loadv8f32 addr:$src))), + (VROUNDPSYm addr:$src, (i32 0x9))>; + def : Pat<(v8f32 (fnearbyint (loadv8f32 addr:$src))), + (VROUNDPSYm addr:$src, (i32 0xC))>; + def : Pat<(v8f32 (fceil (loadv8f32 addr:$src))), + (VROUNDPSYm addr:$src, (i32 0xA))>; + def : Pat<(v8f32 (frint (loadv8f32 addr:$src))), + (VROUNDPSYm addr:$src, (i32 0x4))>; + def : Pat<(v8f32 (ftrunc (loadv8f32 addr:$src))), + (VROUNDPSYm addr:$src, (i32 0xB))>; + + def : Pat<(v4f64 (ffloor VR256:$src)), + (VROUNDPDYr VR256:$src, (i32 0x9))>; + def : Pat<(v4f64 (fnearbyint VR256:$src)), + (VROUNDPDYr VR256:$src, (i32 0xC))>; + def : Pat<(v4f64 (fceil VR256:$src)), + (VROUNDPDYr VR256:$src, (i32 0xA))>; + def : Pat<(v4f64 (frint VR256:$src)), + (VROUNDPDYr VR256:$src, (i32 0x4))>; + def : Pat<(v4f64 (ftrunc VR256:$src)), + (VROUNDPDYr VR256:$src, (i32 0xB))>; + + def : Pat<(v4f64 (ffloor (loadv4f64 addr:$src))), + (VROUNDPDYm addr:$src, (i32 0x9))>; + def : Pat<(v4f64 (fnearbyint (loadv4f64 addr:$src))), + (VROUNDPDYm addr:$src, (i32 0xC))>; + def : Pat<(v4f64 (fceil (loadv4f64 addr:$src))), + (VROUNDPDYm addr:$src, (i32 0xA))>; + def : Pat<(v4f64 (frint (loadv4f64 addr:$src))), + (VROUNDPDYm addr:$src, (i32 0x4))>; + def : Pat<(v4f64 (ftrunc (loadv4f64 addr:$src))), + (VROUNDPDYm addr:$src, (i32 0xB))>; +} + +let ExeDomain = SSEPackedSingle in +defm ROUNDPS : sse41_fp_unop_p<0x08, "roundps", f128mem, VR128, v4f32, + memopv4f32, X86VRndScale, SchedWriteFRnd.XMM>; +let ExeDomain = SSEPackedDouble in +defm ROUNDPD : sse41_fp_unop_p<0x09, "roundpd", f128mem, VR128, v2f64, + memopv2f64, X86VRndScale, SchedWriteFRnd.XMM>; + +defm ROUND : sse41_fp_unop_s<0x0A, 0x0B, "round", SchedWriteFRnd.Scl>; + +let Constraints = "$src1 = $dst" in +defm ROUND : sse41_fp_binop_s<0x0A, 0x0B, "round", SchedWriteFRnd.Scl, + v4f32, v2f64, X86RndScales>; + +let Predicates = [UseSSE41] in { + def : Pat<(ffloor FR32:$src), + (ROUNDSSr FR32:$src, (i32 0x9))>; + def : Pat<(f32 (fnearbyint FR32:$src)), + (ROUNDSSr FR32:$src, (i32 0xC))>; + def : Pat<(f32 (fceil FR32:$src)), + (ROUNDSSr FR32:$src, (i32 0xA))>; + def : Pat<(f32 (frint FR32:$src)), + (ROUNDSSr FR32:$src, (i32 0x4))>; + def : Pat<(f32 (ftrunc FR32:$src)), + (ROUNDSSr FR32:$src, (i32 0xB))>; + + def : Pat<(f64 (ffloor FR64:$src)), + (ROUNDSDr FR64:$src, (i32 0x9))>; + def : Pat<(f64 (fnearbyint FR64:$src)), + (ROUNDSDr FR64:$src, (i32 0xC))>; + def : Pat<(f64 (fceil FR64:$src)), + (ROUNDSDr FR64:$src, (i32 0xA))>; + def : Pat<(f64 (frint FR64:$src)), + (ROUNDSDr FR64:$src, (i32 0x4))>; + def : Pat<(f64 (ftrunc FR64:$src)), + (ROUNDSDr FR64:$src, (i32 0xB))>; +} + +let Predicates = [UseSSE41, OptForSize] in { + def : Pat<(ffloor (loadf32 addr:$src)), + (ROUNDSSm addr:$src, (i32 0x9))>; + def : Pat<(f32 (fnearbyint (loadf32 addr:$src))), + (ROUNDSSm addr:$src, (i32 0xC))>; + def : Pat<(f32 (fceil (loadf32 addr:$src))), + (ROUNDSSm addr:$src, (i32 0xA))>; + def : Pat<(f32 (frint (loadf32 addr:$src))), + (ROUNDSSm addr:$src, (i32 0x4))>; + def : Pat<(f32 (ftrunc (loadf32 addr:$src))), + (ROUNDSSm addr:$src, (i32 0xB))>; + + def : Pat<(f64 (ffloor (loadf64 addr:$src))), + (ROUNDSDm addr:$src, (i32 0x9))>; + def : Pat<(f64 (fnearbyint (loadf64 addr:$src))), + (ROUNDSDm addr:$src, (i32 0xC))>; + def : Pat<(f64 (fceil (loadf64 addr:$src))), + (ROUNDSDm addr:$src, (i32 0xA))>; + def : Pat<(f64 (frint (loadf64 addr:$src))), + (ROUNDSDm addr:$src, (i32 0x4))>; + def : Pat<(f64 (ftrunc (loadf64 addr:$src))), + (ROUNDSDm addr:$src, (i32 0xB))>; +} + +let Predicates = [UseSSE41] in { + def : Pat<(v4f32 (ffloor VR128:$src)), + (ROUNDPSr VR128:$src, (i32 0x9))>; + def : Pat<(v4f32 (fnearbyint VR128:$src)), + (ROUNDPSr VR128:$src, (i32 0xC))>; + def : Pat<(v4f32 (fceil VR128:$src)), + (ROUNDPSr VR128:$src, (i32 0xA))>; + def : Pat<(v4f32 (frint VR128:$src)), + (ROUNDPSr VR128:$src, (i32 0x4))>; + def : Pat<(v4f32 (ftrunc VR128:$src)), + (ROUNDPSr VR128:$src, (i32 0xB))>; + + def : Pat<(v4f32 (ffloor (memopv4f32 addr:$src))), + (ROUNDPSm addr:$src, (i32 0x9))>; + def : Pat<(v4f32 (fnearbyint (memopv4f32 addr:$src))), + (ROUNDPSm addr:$src, (i32 0xC))>; + def : Pat<(v4f32 (fceil (memopv4f32 addr:$src))), + (ROUNDPSm addr:$src, (i32 0xA))>; + def : Pat<(v4f32 (frint (memopv4f32 addr:$src))), + (ROUNDPSm addr:$src, (i32 0x4))>; + def : Pat<(v4f32 (ftrunc (memopv4f32 addr:$src))), + (ROUNDPSm addr:$src, (i32 0xB))>; + + def : Pat<(v2f64 (ffloor VR128:$src)), + (ROUNDPDr VR128:$src, (i32 0x9))>; + def : Pat<(v2f64 (fnearbyint VR128:$src)), + (ROUNDPDr VR128:$src, (i32 0xC))>; + def : Pat<(v2f64 (fceil VR128:$src)), + (ROUNDPDr VR128:$src, (i32 0xA))>; + def : Pat<(v2f64 (frint VR128:$src)), + (ROUNDPDr VR128:$src, (i32 0x4))>; + def : Pat<(v2f64 (ftrunc VR128:$src)), + (ROUNDPDr VR128:$src, (i32 0xB))>; + + def : Pat<(v2f64 (ffloor (memopv2f64 addr:$src))), + (ROUNDPDm addr:$src, (i32 0x9))>; + def : Pat<(v2f64 (fnearbyint (memopv2f64 addr:$src))), + (ROUNDPDm addr:$src, (i32 0xC))>; + def : Pat<(v2f64 (fceil (memopv2f64 addr:$src))), + (ROUNDPDm addr:$src, (i32 0xA))>; + def : Pat<(v2f64 (frint (memopv2f64 addr:$src))), + (ROUNDPDm addr:$src, (i32 0x4))>; + def : Pat<(v2f64 (ftrunc (memopv2f64 addr:$src))), + (ROUNDPDm addr:$src, (i32 0xB))>; +} + +defm : scalar_unary_math_imm_patterns; +defm : scalar_unary_math_imm_patterns; +defm : scalar_unary_math_imm_patterns; +defm : scalar_unary_math_imm_patterns; + +//===----------------------------------------------------------------------===// +// SSE4.1 - Packed Bit Test +//===----------------------------------------------------------------------===// + +// ptest instruction we'll lower to this in X86ISelLowering primarily from +// the intel intrinsic that corresponds to this. +let Defs = [EFLAGS], Predicates = [HasAVX] in { +def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), + "vptest\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>, + Sched<[SchedWriteVecTest.XMM]>, VEX, VEX_WIG; +def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2), + "vptest\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>, + Sched<[SchedWriteVecTest.XMM.Folded, ReadAfterLd]>, + VEX, VEX_WIG; + +def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2), + "vptest\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>, + Sched<[SchedWriteVecTest.YMM]>, VEX, VEX_L, VEX_WIG; +def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2), + "vptest\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>, + Sched<[SchedWriteVecTest.YMM.Folded, ReadAfterLd]>, + VEX, VEX_L, VEX_WIG; +} + +let Defs = [EFLAGS] in { +def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), + "ptest\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>, + Sched<[SchedWriteVecTest.XMM]>; +def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2), + "ptest\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>, + Sched<[SchedWriteVecTest.XMM.Folded, ReadAfterLd]>; +} + +// The bit test instructions below are AVX only +multiclass avx_bittest opc, string OpcodeStr, RegisterClass RC, + X86MemOperand x86memop, PatFrag mem_frag, ValueType vt, + X86FoldableSchedWrite sched> { + def rr : SS48I, + Sched<[sched]>, VEX; + def rm : SS48I, + Sched<[sched.Folded, ReadAfterLd]>, VEX; +} + +let Defs = [EFLAGS], Predicates = [HasAVX] in { +let ExeDomain = SSEPackedSingle in { +defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32, + SchedWriteFTest.XMM>; +defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32, + SchedWriteFTest.YMM>, VEX_L; +} +let ExeDomain = SSEPackedDouble in { +defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64, + SchedWriteFTest.XMM>; +defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64, + SchedWriteFTest.YMM>, VEX_L; +} +} + +//===----------------------------------------------------------------------===// +// SSE4.1 - Misc Instructions +//===----------------------------------------------------------------------===// + +let Defs = [EFLAGS], Predicates = [HasPOPCNT] in { + def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "popcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>, + Sched<[WritePOPCNT]>, OpSize16, XS; + def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "popcnt{w}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (ctpop (loadi16 addr:$src))), + (implicit EFLAGS)]>, + Sched<[WritePOPCNT.Folded]>, OpSize16, XS; + + def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "popcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>, + Sched<[WritePOPCNT]>, OpSize32, XS; + + def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "popcnt{l}\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (ctpop (loadi32 addr:$src))), + (implicit EFLAGS)]>, + Sched<[WritePOPCNT.Folded]>, OpSize32, XS; + + def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "popcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>, + Sched<[WritePOPCNT]>, XS; + def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "popcnt{q}\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (ctpop (loadi64 addr:$src))), + (implicit EFLAGS)]>, + Sched<[WritePOPCNT.Folded]>, XS; +} + +// SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16. +multiclass SS41I_unop_rm_int_v16 opc, string OpcodeStr, + SDNode OpNode, PatFrag ld_frag, + X86FoldableSchedWrite Sched> { + def rr : SS48I, + Sched<[Sched]>; + def rm : SS48I, + Sched<[Sched.Folded]>; +} + +// PHMIN has the same profile as PSAD, thus we use the same scheduling +// model, although the naming is misleading. +let Predicates = [HasAVX] in +defm VPHMINPOSUW : SS41I_unop_rm_int_v16<0x41, "vphminposuw", + X86phminpos, loadv2i64, + WritePHMINPOS>, VEX, VEX_WIG; +defm PHMINPOSUW : SS41I_unop_rm_int_v16<0x41, "phminposuw", + X86phminpos, memopv2i64, + WritePHMINPOS>; + +/// SS48I_binop_rm - Simple SSE41 binary operator. +multiclass SS48I_binop_rm opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT, RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, X86FoldableSchedWrite sched, + bit Is2Addr = 1> { + let isCommutable = 1 in + def rr : SS48I, + Sched<[sched]>; + def rm : SS48I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", smin, v4i32, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", umin, v4i32, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v4i32, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", umax, v4i32, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMULDQ : SS48I_binop_rm<0x28, "vpmuldq", X86pmuldq, v2i64, VR128, + loadv2i64, i128mem, SchedWriteVecIMul.XMM, 0>, + VEX_4V, VEX_WIG; +} +let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { + defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", smin, v16i8, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", umin, v8i16, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v16i8, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v8i16, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; +} + +let Predicates = [HasAVX2, NoVLX] in { + defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", smin, v8i32, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", umin, v8i32, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v8i32, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", umax, v8i32, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMULDQY : SS48I_binop_rm<0x28, "vpmuldq", X86pmuldq, v4i64, VR256, + loadv4i64, i256mem, SchedWriteVecIMul.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; +} +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { + defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", smin, v32i8, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", umin, v16i16, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v32i8, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v16i16, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; +} + +let Constraints = "$src1 = $dst" in { + defm PMINSB : SS48I_binop_rm<0x38, "pminsb", smin, v16i8, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMINSD : SS48I_binop_rm<0x39, "pminsd", smin, v4i32, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMINUD : SS48I_binop_rm<0x3B, "pminud", umin, v4i32, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", umin, v8i16, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", smax, v16i8, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", smax, v4i32, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", umax, v4i32, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", umax, v8i16, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; + defm PMULDQ : SS48I_binop_rm<0x28, "pmuldq", X86pmuldq, v2i64, VR128, + memopv2i64, i128mem, SchedWriteVecIMul.XMM, 1>; +} + +let Predicates = [HasAVX, NoVLX] in + defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128, + loadv2i64, i128mem, SchedWritePMULLD.XMM, 0>, + VEX_4V, VEX_WIG; +let Predicates = [HasAVX] in + defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + +let Predicates = [HasAVX2, NoVLX] in + defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256, + loadv4i64, i256mem, SchedWritePMULLD.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; +let Predicates = [HasAVX2] in + defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + +let Constraints = "$src1 = $dst" in { + defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128, + memopv2i64, i128mem, SchedWritePMULLD.XMM, 1>; + defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM, 1>; +} + +/// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate +multiclass SS41I_binop_rmi_int opc, string OpcodeStr, + Intrinsic IntId, RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, bit Is2Addr, + X86FoldableSchedWrite sched> { + let isCommutable = 1 in + def rri : SS4AIi8, + Sched<[sched]>; + def rmi : SS4AIi8, + Sched<[sched.Folded, ReadAfterLd]>; +} + +/// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate +multiclass SS41I_binop_rmi opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT, RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, bit Is2Addr, + X86FoldableSchedWrite sched> { + let isCommutable = 1 in + def rri : SS4AIi8, + Sched<[sched]>; + def rmi : SS4AIi8, + Sched<[sched.Folded, ReadAfterLd]>; +} + +def BlendCommuteImm2 : SDNodeXFormgetZExtValue() & 0x03; + return getI8Imm(Imm ^ 0x03, SDLoc(N)); +}]>; + +def BlendCommuteImm4 : SDNodeXFormgetZExtValue() & 0x0f; + return getI8Imm(Imm ^ 0x0f, SDLoc(N)); +}]>; + +def BlendCommuteImm8 : SDNodeXFormgetZExtValue() & 0xff; + return getI8Imm(Imm ^ 0xff, SDLoc(N)); +}]>; + +let Predicates = [HasAVX] in { + let isCommutable = 0 in { + defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw, + VR128, loadv2i64, i128mem, 0, + SchedWriteMPSAD.XMM>, VEX_4V, VEX_WIG; + } + + let ExeDomain = SSEPackedSingle in + defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps, + VR128, loadv4f32, f128mem, 0, + SchedWriteDPPS.XMM>, VEX_4V, VEX_WIG; + let ExeDomain = SSEPackedDouble in + defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd, + VR128, loadv2f64, f128mem, 0, + SchedWriteDPPD.XMM>, VEX_4V, VEX_WIG; + let ExeDomain = SSEPackedSingle in + defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256, + VR256, loadv8f32, i256mem, 0, + SchedWriteDPPS.YMM>, VEX_4V, VEX_L, VEX_WIG; +} + +let Predicates = [HasAVX2] in { + let isCommutable = 0 in { + defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw, + VR256, loadv4i64, i256mem, 0, + SchedWriteMPSAD.YMM>, VEX_4V, VEX_L, VEX_WIG; + } +} + +let Constraints = "$src1 = $dst" in { + let isCommutable = 0 in { + defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw, + VR128, memopv2i64, i128mem, 1, + SchedWriteMPSAD.XMM>; + } + + let ExeDomain = SSEPackedSingle in + defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps, + VR128, memopv4f32, f128mem, 1, + SchedWriteDPPS.XMM>; + let ExeDomain = SSEPackedDouble in + defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd, + VR128, memopv2f64, f128mem, 1, + SchedWriteDPPD.XMM>; +} + +/// SS41I_blend_rmi - SSE 4.1 blend with 8-bit immediate +multiclass SS41I_blend_rmi opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT, RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, bit Is2Addr, Domain d, + X86FoldableSchedWrite sched, SDNodeXForm commuteXForm> { +let ExeDomain = d, Constraints = !if(Is2Addr, "$src1 = $dst", "") in { + let isCommutable = 1 in + def rri : SS4AIi8, + Sched<[sched]>; + def rmi : SS4AIi8, + Sched<[sched.Folded, ReadAfterLd]>; +} + + // Pattern to commute if load is in first source. + def : Pat<(OpVT (OpNode (bitconvert (memop_frag addr:$src2)), + RC:$src1, imm:$src3)), + (!cast(NAME#"rmi") RC:$src1, addr:$src2, + (commuteXForm imm:$src3))>; +} + +let Predicates = [HasAVX] in { + defm VBLENDPS : SS41I_blend_rmi<0x0C, "vblendps", X86Blendi, v4f32, + VR128, loadv4f32, f128mem, 0, SSEPackedSingle, + SchedWriteFBlend.XMM, BlendCommuteImm4>, + VEX_4V, VEX_WIG; + defm VBLENDPSY : SS41I_blend_rmi<0x0C, "vblendps", X86Blendi, v8f32, + VR256, loadv8f32, f256mem, 0, SSEPackedSingle, + SchedWriteFBlend.YMM, BlendCommuteImm8>, + VEX_4V, VEX_L, VEX_WIG; + defm VBLENDPD : SS41I_blend_rmi<0x0D, "vblendpd", X86Blendi, v2f64, + VR128, loadv2f64, f128mem, 0, SSEPackedDouble, + SchedWriteFBlend.XMM, BlendCommuteImm2>, + VEX_4V, VEX_WIG; + defm VBLENDPDY : SS41I_blend_rmi<0x0D, "vblendpd", X86Blendi, v4f64, + VR256, loadv4f64, f256mem, 0, SSEPackedDouble, + SchedWriteFBlend.YMM, BlendCommuteImm4>, + VEX_4V, VEX_L, VEX_WIG; + defm VPBLENDW : SS41I_blend_rmi<0x0E, "vpblendw", X86Blendi, v8i16, + VR128, loadv2i64, i128mem, 0, SSEPackedInt, + SchedWriteBlend.XMM, BlendCommuteImm8>, + VEX_4V, VEX_WIG; +} + +let Predicates = [HasAVX2] in { + defm VPBLENDWY : SS41I_blend_rmi<0x0E, "vpblendw", X86Blendi, v16i16, + VR256, loadv4i64, i256mem, 0, SSEPackedInt, + SchedWriteBlend.YMM, BlendCommuteImm8>, + VEX_4V, VEX_L, VEX_WIG; +} + +defm BLENDPS : SS41I_blend_rmi<0x0C, "blendps", X86Blendi, v4f32, + VR128, memopv4f32, f128mem, 1, SSEPackedSingle, + SchedWriteFBlend.XMM, BlendCommuteImm4>; +defm BLENDPD : SS41I_blend_rmi<0x0D, "blendpd", X86Blendi, v2f64, + VR128, memopv2f64, f128mem, 1, SSEPackedDouble, + SchedWriteFBlend.XMM, BlendCommuteImm2>; +defm PBLENDW : SS41I_blend_rmi<0x0E, "pblendw", X86Blendi, v8i16, + VR128, memopv2i64, i128mem, 1, SSEPackedInt, + SchedWriteBlend.XMM, BlendCommuteImm8>; + +// For insertion into the zero index (low half) of a 256-bit vector, it is +// more efficient to generate a blend with immediate instead of an insert*128. +let Predicates = [HasAVX] in { +def : Pat<(insert_subvector (v4f64 VR256:$src1), (v2f64 VR128:$src2), (iPTR 0)), + (VBLENDPDYrri VR256:$src1, + (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0x3)>; +def : Pat<(insert_subvector (v8f32 VR256:$src1), (v4f32 VR128:$src2), (iPTR 0)), + (VBLENDPSYrri VR256:$src1, + (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +} + +/// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators +multiclass SS41I_quaternary_int_avx opc, string OpcodeStr, + RegisterClass RC, X86MemOperand x86memop, + PatFrag mem_frag, Intrinsic IntId, + X86FoldableSchedWrite sched> { + def rr : Ii8Reg, TAPD, VEX_4V, + Sched<[sched]>; + + def rm : Ii8Reg, TAPD, VEX_4V, + Sched<[sched.Folded, ReadAfterLd, + // x86memop:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC::$src3 + ReadAfterLd]>; +} + +let Predicates = [HasAVX] in { +let ExeDomain = SSEPackedDouble in { +defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem, + loadv2f64, int_x86_sse41_blendvpd, + SchedWriteFVarBlend.XMM>; +defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem, + loadv4f64, int_x86_avx_blendv_pd_256, + SchedWriteFVarBlend.YMM>, VEX_L; +} // ExeDomain = SSEPackedDouble +let ExeDomain = SSEPackedSingle in { +defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem, + loadv4f32, int_x86_sse41_blendvps, + SchedWriteFVarBlend.XMM>; +defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem, + loadv8f32, int_x86_avx_blendv_ps_256, + SchedWriteFVarBlend.YMM>, VEX_L; +} // ExeDomain = SSEPackedSingle +defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem, + loadv2i64, int_x86_sse41_pblendvb, + SchedWriteVarBlend.XMM>; +} + +let Predicates = [HasAVX2] in { +defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem, + loadv4i64, int_x86_avx2_pblendvb, + SchedWriteVarBlend.YMM>, VEX_L; +} + +let Predicates = [HasAVX] in { + def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1), + (v16i8 VR128:$src2))), + (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>; + def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1), + (v4i32 VR128:$src2))), + (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>; + def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1), + (v4f32 VR128:$src2))), + (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>; + def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1), + (v2i64 VR128:$src2))), + (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>; + def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1), + (v2f64 VR128:$src2))), + (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>; + def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1), + (v8i32 VR256:$src2))), + (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>; + def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1), + (v8f32 VR256:$src2))), + (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>; + def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1), + (v4i64 VR256:$src2))), + (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>; + def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1), + (v4f64 VR256:$src2))), + (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>; +} + +let Predicates = [HasAVX2] in { + def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1), + (v32i8 VR256:$src2))), + (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>; +} + +// Prefer a movss or movsd over a blendps when optimizing for size. these were +// changed to use blends because blends have better throughput on sandybridge +// and haswell, but movs[s/d] are 1-2 byte shorter instructions. +let Predicates = [HasAVX, OptForSpeed] in { + def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), + (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>; + def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), + (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>; + + def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)), + (VBLENDPSrri VR128:$src1, VR128:$src2, (i8 1))>; + def : Pat<(v4f32 (X86Movss VR128:$src1, (loadv4f32 addr:$src2))), + (VBLENDPSrmi VR128:$src1, addr:$src2, (i8 1))>; + def : Pat<(v4f32 (X86Movss (loadv4f32 addr:$src2), VR128:$src1)), + (VBLENDPSrmi VR128:$src1, addr:$src2, (i8 0xe))>; + + def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)), + (VBLENDPDrri VR128:$src1, VR128:$src2, (i8 1))>; + def : Pat<(v2f64 (X86Movsd VR128:$src1, (loadv2f64 addr:$src2))), + (VBLENDPDrmi VR128:$src1, addr:$src2, (i8 1))>; + def : Pat<(v2f64 (X86Movsd (loadv2f64 addr:$src2), VR128:$src1)), + (VBLENDPDrmi VR128:$src1, addr:$src2, (i8 2))>; + + // Move low f32 and clear high bits. + def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v4f32 (VBLENDPSrri (v4f32 (V_SET0)), + (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), + (i8 1))), sub_xmm)>; + def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v4i32 (VPBLENDWrri (v4i32 (V_SET0)), + (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), + (i8 3))), sub_xmm)>; + + def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v2f64 (VBLENDPDrri (v2f64 (V_SET0)), + (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), + (i8 1))), sub_xmm)>; + def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (v2i64 (VPBLENDWrri (v2i64 (V_SET0)), + (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), + (i8 0xf))), sub_xmm)>; +} + +// Prefer a movss or movsd over a blendps when optimizing for size. these were +// changed to use blends because blends have better throughput on sandybridge +// and haswell, but movs[s/d] are 1-2 byte shorter instructions. +let Predicates = [UseSSE41, OptForSpeed] in { + // With SSE41 we can use blends for these patterns. + def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), + (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>; + def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), + (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>; + + def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)), + (BLENDPSrri VR128:$src1, VR128:$src2, (i8 1))>; + def : Pat<(v4f32 (X86Movss VR128:$src1, (memopv4f32 addr:$src2))), + (BLENDPSrmi VR128:$src1, addr:$src2, (i8 1))>; + def : Pat<(v4f32 (X86Movss (memopv4f32 addr:$src2), VR128:$src1)), + (BLENDPSrmi VR128:$src1, addr:$src2, (i8 0xe))>; + + def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)), + (BLENDPDrri VR128:$src1, VR128:$src2, (i8 1))>; + def : Pat<(v2f64 (X86Movsd VR128:$src1, (memopv2f64 addr:$src2))), + (BLENDPDrmi VR128:$src1, addr:$src2, (i8 1))>; + def : Pat<(v2f64 (X86Movsd (memopv2f64 addr:$src2), VR128:$src1)), + (BLENDPDrmi VR128:$src1, addr:$src2, (i8 2))>; +} + + +/// SS41I_ternary_int - SSE 4.1 ternary operator +let Uses = [XMM0], Constraints = "$src1 = $dst" in { + multiclass SS41I_ternary_int opc, string OpcodeStr, PatFrag mem_frag, + X86MemOperand x86memop, Intrinsic IntId, + X86FoldableSchedWrite sched> { + def rr0 : SS48I, + Sched<[sched]>; + + def rm0 : SS48I, + Sched<[sched.Folded, ReadAfterLd]>; + } +} + +let ExeDomain = SSEPackedDouble in +defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem, + int_x86_sse41_blendvpd, SchedWriteFVarBlend.XMM>; +let ExeDomain = SSEPackedSingle in +defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem, + int_x86_sse41_blendvps, SchedWriteFVarBlend.XMM>; +defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem, + int_x86_sse41_pblendvb, SchedWriteVarBlend.XMM>; + +// Aliases with the implicit xmm0 argument +def : InstAlias<"blendvpd\t{$src2, $dst|$dst, $src2}", + (BLENDVPDrr0 VR128:$dst, VR128:$src2), 0>; +def : InstAlias<"blendvpd\t{$src2, $dst|$dst, $src2}", + (BLENDVPDrm0 VR128:$dst, f128mem:$src2), 0>; +def : InstAlias<"blendvps\t{$src2, $dst|$dst, $src2}", + (BLENDVPSrr0 VR128:$dst, VR128:$src2), 0>; +def : InstAlias<"blendvps\t{$src2, $dst|$dst, $src2}", + (BLENDVPSrm0 VR128:$dst, f128mem:$src2), 0>; +def : InstAlias<"pblendvb\t{$src2, $dst|$dst, $src2}", + (PBLENDVBrr0 VR128:$dst, VR128:$src2), 0>; +def : InstAlias<"pblendvb\t{$src2, $dst|$dst, $src2}", + (PBLENDVBrm0 VR128:$dst, i128mem:$src2), 0>; + +let Predicates = [UseSSE41] in { + def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1), + (v16i8 VR128:$src2))), + (PBLENDVBrr0 VR128:$src2, VR128:$src1)>; + def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1), + (v4i32 VR128:$src2))), + (BLENDVPSrr0 VR128:$src2, VR128:$src1)>; + def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1), + (v4f32 VR128:$src2))), + (BLENDVPSrr0 VR128:$src2, VR128:$src1)>; + def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1), + (v2i64 VR128:$src2))), + (BLENDVPDrr0 VR128:$src2, VR128:$src1)>; + def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1), + (v2f64 VR128:$src2))), + (BLENDVPDrr0 VR128:$src2, VR128:$src1)>; +} + +let AddedComplexity = 400 in { // Prefer non-temporal versions + +let Predicates = [HasAVX, NoVLX] in +def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "vmovntdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLSNT.XMM.RM]>, VEX, VEX_WIG; +let Predicates = [HasAVX2, NoVLX] in +def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src), + "vmovntdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLSNT.YMM.RM]>, VEX, VEX_L, VEX_WIG; +def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), + "movntdqa\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteVecMoveLSNT.XMM.RM]>; + +let Predicates = [HasAVX2, NoVLX] in { + def : Pat<(v8f32 (alignednontemporalload addr:$src)), + (VMOVNTDQAYrm addr:$src)>; + def : Pat<(v4f64 (alignednontemporalload addr:$src)), + (VMOVNTDQAYrm addr:$src)>; + def : Pat<(v4i64 (alignednontemporalload addr:$src)), + (VMOVNTDQAYrm addr:$src)>; +} + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4f32 (alignednontemporalload addr:$src)), + (VMOVNTDQArm addr:$src)>; + def : Pat<(v2f64 (alignednontemporalload addr:$src)), + (VMOVNTDQArm addr:$src)>; + def : Pat<(v2i64 (alignednontemporalload addr:$src)), + (VMOVNTDQArm addr:$src)>; +} + +let Predicates = [UseSSE41] in { + def : Pat<(v4f32 (alignednontemporalload addr:$src)), + (MOVNTDQArm addr:$src)>; + def : Pat<(v2f64 (alignednontemporalload addr:$src)), + (MOVNTDQArm addr:$src)>; + def : Pat<(v2i64 (alignednontemporalload addr:$src)), + (MOVNTDQArm addr:$src)>; +} + +} // AddedComplexity + +//===----------------------------------------------------------------------===// +// SSE4.2 - Compare Instructions +//===----------------------------------------------------------------------===// + +/// SS42I_binop_rm - Simple SSE 4.2 binary operator +multiclass SS42I_binop_rm opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT, RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, X86FoldableSchedWrite sched, + bit Is2Addr = 1> { + def rr : SS428I, + Sched<[sched]>; + def rm : SS428I, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX] in + defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128, + loadv2i64, i128mem, SchedWriteVecALU.XMM, 0>, + VEX_4V, VEX_WIG; + +let Predicates = [HasAVX2] in + defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256, + loadv4i64, i256mem, SchedWriteVecALU.YMM, 0>, + VEX_4V, VEX_L, VEX_WIG; + +let Constraints = "$src1 = $dst" in + defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128, + memopv2i64, i128mem, SchedWriteVecALU.XMM>; + +//===----------------------------------------------------------------------===// +// SSE4.2 - String/text Processing Instructions +//===----------------------------------------------------------------------===// + +multiclass pcmpistrm_SS42AI { + def rr : SS42AI<0x62, MRMSrcReg, (outs), + (ins VR128:$src1, VR128:$src2, u8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"), + []>, Sched<[WritePCmpIStrM]>; + let mayLoad = 1 in + def rm :SS42AI<0x62, MRMSrcMem, (outs), + (ins VR128:$src1, i128mem:$src2, u8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"), + []>, Sched<[WritePCmpIStrM.Folded, ReadAfterLd]>; +} + +let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in { + let Predicates = [HasAVX] in + defm VPCMPISTRM : pcmpistrm_SS42AI<"vpcmpistrm">, VEX; + defm PCMPISTRM : pcmpistrm_SS42AI<"pcmpistrm"> ; +} + +multiclass SS42AI_pcmpestrm { + def rr : SS42AI<0x60, MRMSrcReg, (outs), + (ins VR128:$src1, VR128:$src3, u8imm:$src5), + !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"), + []>, Sched<[WritePCmpEStrM]>; + let mayLoad = 1 in + def rm : SS42AI<0x60, MRMSrcMem, (outs), + (ins VR128:$src1, i128mem:$src3, u8imm:$src5), + !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"), + []>, Sched<[WritePCmpEStrM.Folded, ReadAfterLd]>; +} + +let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in { + let Predicates = [HasAVX] in + defm VPCMPESTRM : SS42AI_pcmpestrm<"vpcmpestrm">, VEX; + defm PCMPESTRM : SS42AI_pcmpestrm<"pcmpestrm">; +} + +multiclass SS42AI_pcmpistri { + def rr : SS42AI<0x63, MRMSrcReg, (outs), + (ins VR128:$src1, VR128:$src2, u8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"), + []>, Sched<[WritePCmpIStrI]>; + let mayLoad = 1 in + def rm : SS42AI<0x63, MRMSrcMem, (outs), + (ins VR128:$src1, i128mem:$src2, u8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"), + []>, Sched<[WritePCmpIStrI.Folded, ReadAfterLd]>; +} + +let Defs = [ECX, EFLAGS], hasSideEffects = 0 in { + let Predicates = [HasAVX] in + defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX; + defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">; +} + +multiclass SS42AI_pcmpestri { + def rr : SS42AI<0x61, MRMSrcReg, (outs), + (ins VR128:$src1, VR128:$src3, u8imm:$src5), + !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"), + []>, Sched<[WritePCmpEStrI]>; + let mayLoad = 1 in + def rm : SS42AI<0x61, MRMSrcMem, (outs), + (ins VR128:$src1, i128mem:$src3, u8imm:$src5), + !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"), + []>, Sched<[WritePCmpEStrI.Folded, ReadAfterLd]>; +} + +let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in { + let Predicates = [HasAVX] in + defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX; + defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">; +} + +//===----------------------------------------------------------------------===// +// SSE4.2 - CRC Instructions +//===----------------------------------------------------------------------===// + +// No CRC instructions have AVX equivalents + +// crc intrinsic instruction +// This set of instructions are only rm, the only difference is the size +// of r and m. +class SS42I_crc32r opc, string asm, RegisterClass RCOut, + RegisterClass RCIn, SDPatternOperator Int> : + SS42FI, + Sched<[WriteCRC32]>; + +class SS42I_crc32m opc, string asm, RegisterClass RCOut, + X86MemOperand x86memop, SDPatternOperator Int> : + SS42FI, + Sched<[WriteCRC32.Folded, ReadAfterLd]>; + +let Constraints = "$src1 = $dst" in { + def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem, + int_x86_sse42_crc32_32_8>; + def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8, + int_x86_sse42_crc32_32_8>; + def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem, + int_x86_sse42_crc32_32_16>, OpSize16; + def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16, + int_x86_sse42_crc32_32_16>, OpSize16; + def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem, + int_x86_sse42_crc32_32_32>, OpSize32; + def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32, + int_x86_sse42_crc32_32_32>, OpSize32; + def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem, + int_x86_sse42_crc32_64_64>, REX_W; + def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64, + int_x86_sse42_crc32_64_64>, REX_W; + let hasSideEffects = 0 in { + let mayLoad = 1 in + def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem, + null_frag>, REX_W; + def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8, + null_frag>, REX_W; + } +} + +//===----------------------------------------------------------------------===// +// SHA-NI Instructions +//===----------------------------------------------------------------------===// + +// FIXME: Is there a better scheduler class for SHA than WriteVecIMul? +multiclass SHAI_binop Opc, string OpcodeStr, Intrinsic IntId, + X86FoldableSchedWrite sched, bit UsesXMM0 = 0> { + def rr : I, + T8, Sched<[sched]>; + + def rm : I, T8, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let Constraints = "$src1 = $dst", Predicates = [HasSHA] in { + def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2, u8imm:$src3), + "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR128:$dst, + (int_x86_sha1rnds4 VR128:$src1, VR128:$src2, + (i8 imm:$src3)))]>, TA, + Sched<[SchedWriteVecIMul.XMM]>; + def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, i128mem:$src2, u8imm:$src3), + "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR128:$dst, + (int_x86_sha1rnds4 VR128:$src1, + (bc_v4i32 (memopv2i64 addr:$src2)), + (i8 imm:$src3)))]>, TA, + Sched<[SchedWriteVecIMul.XMM.Folded, ReadAfterLd]>; + + defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte, + SchedWriteVecIMul.XMM>; + defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1, + SchedWriteVecIMul.XMM>; + defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2, + SchedWriteVecIMul.XMM>; + + let Uses=[XMM0] in + defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, + SchedWriteVecIMul.XMM, 1>; + + defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1, + SchedWriteVecIMul.XMM>; + defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2, + SchedWriteVecIMul.XMM>; +} + +// Aliases with explicit %xmm0 +def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", + (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>; +def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", + (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>; + +//===----------------------------------------------------------------------===// +// AES-NI Instructions +//===----------------------------------------------------------------------===// + +multiclass AESI_binop_rm_int opc, string OpcodeStr, + Intrinsic IntId, PatFrag ld_frag, + bit Is2Addr = 0, RegisterClass RC = VR128, + X86MemOperand MemOp = i128mem> { + let AsmString = OpcodeStr## + !if(Is2Addr, "\t{$src2, $dst|$dst, $src2}", + "\t{$src2, $src1, $dst|$dst, $src1, $src2}") in { + def rr : AES8I, + Sched<[WriteAESDecEnc]>; + def rm : AES8I, + Sched<[WriteAESDecEnc.Folded, ReadAfterLd]>; + } +} + +// Perform One Round of an AES Encryption/Decryption Flow +let Predicates = [HasAVX, NoVLX_Or_NoVAES, HasAES] in { + defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc", + int_x86_aesni_aesenc, loadv2i64>, VEX_4V, VEX_WIG; + defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast", + int_x86_aesni_aesenclast, loadv2i64>, VEX_4V, VEX_WIG; + defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec", + int_x86_aesni_aesdec, loadv2i64>, VEX_4V, VEX_WIG; + defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast", + int_x86_aesni_aesdeclast, loadv2i64>, VEX_4V, VEX_WIG; +} + +let Predicates = [NoVLX, HasVAES] in { + defm VAESENCY : AESI_binop_rm_int<0xDC, "vaesenc", + int_x86_aesni_aesenc_256, loadv4i64, 0, VR256, + i256mem>, VEX_4V, VEX_L, VEX_WIG; + defm VAESENCLASTY : AESI_binop_rm_int<0xDD, "vaesenclast", + int_x86_aesni_aesenclast_256, loadv4i64, 0, VR256, + i256mem>, VEX_4V, VEX_L, VEX_WIG; + defm VAESDECY : AESI_binop_rm_int<0xDE, "vaesdec", + int_x86_aesni_aesdec_256, loadv4i64, 0, VR256, + i256mem>, VEX_4V, VEX_L, VEX_WIG; + defm VAESDECLASTY : AESI_binop_rm_int<0xDF, "vaesdeclast", + int_x86_aesni_aesdeclast_256, loadv4i64, 0, VR256, + i256mem>, VEX_4V, VEX_L, VEX_WIG; +} + +let Constraints = "$src1 = $dst" in { + defm AESENC : AESI_binop_rm_int<0xDC, "aesenc", + int_x86_aesni_aesenc, memopv2i64, 1>; + defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast", + int_x86_aesni_aesenclast, memopv2i64, 1>; + defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec", + int_x86_aesni_aesdec, memopv2i64, 1>; + defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast", + int_x86_aesni_aesdeclast, memopv2i64, 1>; +} + +// Perform the AES InvMixColumn Transformation +let Predicates = [HasAVX, HasAES] in { + def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1), + "vaesimc\t{$src1, $dst|$dst, $src1}", + [(set VR128:$dst, + (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>, + VEX, VEX_WIG; + def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst), + (ins i128mem:$src1), + "vaesimc\t{$src1, $dst|$dst, $src1}", + [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>, + Sched<[WriteAESIMC.Folded]>, VEX, VEX_WIG; +} +def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1), + "aesimc\t{$src1, $dst|$dst, $src1}", + [(set VR128:$dst, + (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>; +def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst), + (ins i128mem:$src1), + "aesimc\t{$src1, $dst|$dst, $src1}", + [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>, + Sched<[WriteAESIMC.Folded]>; + +// AES Round Key Generation Assist +let Predicates = [HasAVX, HasAES] in { + def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, u8imm:$src2), + "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>, + Sched<[WriteAESKeyGen]>, VEX, VEX_WIG; + def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst), + (ins i128mem:$src1, u8imm:$src2), + "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>, + Sched<[WriteAESKeyGen.Folded]>, VEX, VEX_WIG; +} +def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, u8imm:$src2), + "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>, + Sched<[WriteAESKeyGen]>; +def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst), + (ins i128mem:$src1, u8imm:$src2), + "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, + (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>, + Sched<[WriteAESKeyGen.Folded]>; + +//===----------------------------------------------------------------------===// +// PCLMUL Instructions +//===----------------------------------------------------------------------===// + +// Immediate transform to help with commuting. +def PCLMULCommuteImm : SDNodeXFormgetZExtValue(); + return getI8Imm((uint8_t)((Imm >> 4) | (Imm << 4)), SDLoc(N)); +}]>; + +// SSE carry-less Multiplication instructions +let Predicates = [NoAVX, HasPCLMUL] in { + let Constraints = "$src1 = $dst" in { + let isCommutable = 1 in + def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2, u8imm:$src3), + "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR128:$dst, + (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>, + Sched<[WriteCLMul]>; + + def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, i128mem:$src2, u8imm:$src3), + "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR128:$dst, + (int_x86_pclmulqdq VR128:$src1, (memopv2i64 addr:$src2), + imm:$src3))]>, + Sched<[WriteCLMul.Folded, ReadAfterLd]>; + } // Constraints = "$src1 = $dst" + + def : Pat<(int_x86_pclmulqdq (memopv2i64 addr:$src2), VR128:$src1, + (i8 imm:$src3)), + (PCLMULQDQrm VR128:$src1, addr:$src2, + (PCLMULCommuteImm imm:$src3))>; +} // Predicates = [NoAVX, HasPCLMUL] + +// SSE aliases +foreach HI = ["hq","lq"] in +foreach LO = ["hq","lq"] in { + def : InstAlias<"pclmul" # HI # LO # "dq\t{$src, $dst|$dst, $src}", + (PCLMULQDQrr VR128:$dst, VR128:$src, + !add(!shl(!eq(LO,"hq"),4),!eq(HI,"hq"))), 0>; + def : InstAlias<"pclmul" # HI # LO # "dq\t{$src, $dst|$dst, $src}", + (PCLMULQDQrm VR128:$dst, i128mem:$src, + !add(!shl(!eq(LO,"hq"),4),!eq(HI,"hq"))), 0>; +} + +// AVX carry-less Multiplication instructions +multiclass vpclmulqdq { + let isCommutable = 1 in + def rr : PCLMULIi8<0x44, MRMSrcReg, (outs RC:$dst), + (ins RC:$src1, RC:$src2, u8imm:$src3), + "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set RC:$dst, + (IntId RC:$src1, RC:$src2, imm:$src3))]>, + Sched<[WriteCLMul]>; + + def rm : PCLMULIi8<0x44, MRMSrcMem, (outs RC:$dst), + (ins RC:$src1, MemOp:$src2, u8imm:$src3), + "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set RC:$dst, + (IntId RC:$src1, (LdFrag addr:$src2), imm:$src3))]>, + Sched<[WriteCLMul.Folded, ReadAfterLd]>; + + // We can commute a load in the first operand by swapping the sources and + // rotating the immediate. + def : Pat<(IntId (LdFrag addr:$src2), RC:$src1, (i8 imm:$src3)), + (!cast(NAME#"rm") RC:$src1, addr:$src2, + (PCLMULCommuteImm imm:$src3))>; +} + +let Predicates = [HasAVX, NoVLX_Or_NoVPCLMULQDQ, HasPCLMUL] in +defm VPCLMULQDQ : vpclmulqdq, VEX_4V, VEX_WIG; + +let Predicates = [NoVLX, HasVPCLMULQDQ] in +defm VPCLMULQDQY : vpclmulqdq, VEX_4V, VEX_L, VEX_WIG; + +multiclass vpclmulqdq_aliases_impl { + def : InstAlias<"vpclmul"##Hi##Lo##"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}", + (!cast(InstStr # "rr") RC:$dst, RC:$src1, RC:$src2, + !add(!shl(!eq(Lo,"hq"),4),!eq(Hi,"hq"))), 0>; + def : InstAlias<"vpclmul"##Hi##Lo##"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}", + (!cast(InstStr # "rm") RC:$dst, RC:$src1, MemOp:$src2, + !add(!shl(!eq(Lo,"hq"),4),!eq(Hi,"hq"))), 0>; +} + +multiclass vpclmulqdq_aliases { + defm : vpclmulqdq_aliases_impl; + defm : vpclmulqdq_aliases_impl; + defm : vpclmulqdq_aliases_impl; + defm : vpclmulqdq_aliases_impl; +} + +// AVX aliases +defm : vpclmulqdq_aliases<"VPCLMULQDQ", VR128, i128mem>; +defm : vpclmulqdq_aliases<"VPCLMULQDQY", VR256, i256mem>; + +//===----------------------------------------------------------------------===// +// SSE4A Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasSSE4A] in { + +let ExeDomain = SSEPackedInt in { +let Constraints = "$src = $dst" in { +def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst), + (ins VR128:$src, u8imm:$len, u8imm:$idx), + "extrq\t{$idx, $len, $src|$src, $len, $idx}", + [(set VR128:$dst, (X86extrqi VR128:$src, imm:$len, + imm:$idx))]>, + PD, Sched<[SchedWriteVecALU.XMM]>; +def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src, VR128:$mask), + "extrq\t{$mask, $src|$src, $mask}", + [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src, + VR128:$mask))]>, + PD, Sched<[SchedWriteVecALU.XMM]>; + +def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx), + "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}", + [(set VR128:$dst, (X86insertqi VR128:$src, VR128:$src2, + imm:$len, imm:$idx))]>, + XD, Sched<[SchedWriteVecALU.XMM]>; +def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src, VR128:$mask), + "insertq\t{$mask, $src|$src, $mask}", + [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src, + VR128:$mask))]>, + XD, Sched<[SchedWriteVecALU.XMM]>; +} +} // ExeDomain = SSEPackedInt + +// Non-temporal (unaligned) scalar stores. +let AddedComplexity = 400 in { // Prefer non-temporal versions +let hasSideEffects = 0, mayStore = 1, SchedRW = [SchedWriteFMoveLSNT.Scl.MR] in { +def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src), + "movntss\t{$src, $dst|$dst, $src}", []>, XS; + +def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), + "movntsd\t{$src, $dst|$dst, $src}", []>, XD; +} // SchedRW + +def : Pat<(nontemporalstore FR32:$src, addr:$dst), + (MOVNTSS addr:$dst, (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)))>; + +def : Pat<(nontemporalstore FR64:$src, addr:$dst), + (MOVNTSD addr:$dst, (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))>; + +} // AddedComplexity +} // HasSSE4A + +//===----------------------------------------------------------------------===// +// AVX Instructions +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// VBROADCAST - Load from memory and broadcast to all elements of the +// destination operand +// +class avx_broadcast_rm opc, string OpcodeStr, RegisterClass RC, + X86MemOperand x86memop, ValueType VT, + PatFrag ld_frag, SchedWrite Sched> : + AVX8I, + Sched<[Sched]>, VEX; + +// AVX2 adds register forms +class avx2_broadcast_rr opc, string OpcodeStr, RegisterClass RC, + ValueType ResVT, ValueType OpVT, SchedWrite Sched> : + AVX28I, + Sched<[Sched]>, VEX; + +let ExeDomain = SSEPackedSingle, Predicates = [HasAVX, NoVLX] in { + def VBROADCASTSSrm : avx_broadcast_rm<0x18, "vbroadcastss", VR128, + f32mem, v4f32, loadf32, + SchedWriteFShuffle.XMM.Folded>; + def VBROADCASTSSYrm : avx_broadcast_rm<0x18, "vbroadcastss", VR256, + f32mem, v8f32, loadf32, + SchedWriteFShuffle.XMM.Folded>, VEX_L; +} +let ExeDomain = SSEPackedDouble, Predicates = [HasAVX, NoVLX] in +def VBROADCASTSDYrm : avx_broadcast_rm<0x19, "vbroadcastsd", VR256, f64mem, + v4f64, loadf64, + SchedWriteFShuffle.XMM.Folded>, VEX_L; + +let ExeDomain = SSEPackedSingle, Predicates = [HasAVX2, NoVLX] in { + def VBROADCASTSSrr : avx2_broadcast_rr<0x18, "vbroadcastss", VR128, + v4f32, v4f32, SchedWriteFShuffle.XMM>; + def VBROADCASTSSYrr : avx2_broadcast_rr<0x18, "vbroadcastss", VR256, + v8f32, v4f32, WriteFShuffle256>, VEX_L; +} +let ExeDomain = SSEPackedDouble, Predicates = [HasAVX2, NoVLX] in +def VBROADCASTSDYrr : avx2_broadcast_rr<0x19, "vbroadcastsd", VR256, + v4f64, v2f64, WriteFShuffle256>, VEX_L; + +let Predicates = [HasAVX, NoVLX] in { + def : Pat<(v4f32 (X86VBroadcast (v4f32 (scalar_to_vector (loadf32 addr:$src))))), + (VBROADCASTSSrm addr:$src)>; + def : Pat<(v8f32 (X86VBroadcast (v4f32 (scalar_to_vector (loadf32 addr:$src))))), + (VBROADCASTSSYrm addr:$src)>; + def : Pat<(v4f64 (X86VBroadcast (v2f64 (scalar_to_vector (loadf64 addr:$src))))), + (VBROADCASTSDYrm addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// VBROADCAST*128 - Load from memory and broadcast 128-bit vector to both +// halves of a 256-bit vector. +// +let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX2] in +def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst), + (ins i128mem:$src), + "vbroadcasti128\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteShuffleLd]>, VEX, VEX_L; + +let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX], + ExeDomain = SSEPackedSingle in +def VBROADCASTF128 : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst), + (ins f128mem:$src), + "vbroadcastf128\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteFShuffle.XMM.Folded]>, VEX, VEX_L; + +let Predicates = [HasAVX2, NoVLX] in { +def : Pat<(v4i64 (X86SubVBroadcast (loadv2i64 addr:$src))), + (VBROADCASTI128 addr:$src)>; +def : Pat<(v8i32 (X86SubVBroadcast (bc_v4i32 (loadv2i64 addr:$src)))), + (VBROADCASTI128 addr:$src)>; +def : Pat<(v16i16 (X86SubVBroadcast (bc_v8i16 (loadv2i64 addr:$src)))), + (VBROADCASTI128 addr:$src)>; +def : Pat<(v32i8 (X86SubVBroadcast (bc_v16i8 (loadv2i64 addr:$src)))), + (VBROADCASTI128 addr:$src)>; +} + +let Predicates = [HasAVX, NoVLX] in { +def : Pat<(v4f64 (X86SubVBroadcast (loadv2f64 addr:$src))), + (VBROADCASTF128 addr:$src)>; +def : Pat<(v8f32 (X86SubVBroadcast (loadv4f32 addr:$src))), + (VBROADCASTF128 addr:$src)>; +} + +let Predicates = [HasAVX1Only] in { +def : Pat<(v4i64 (X86SubVBroadcast (loadv2i64 addr:$src))), + (VBROADCASTF128 addr:$src)>; +def : Pat<(v8i32 (X86SubVBroadcast (bc_v4i32 (loadv2i64 addr:$src)))), + (VBROADCASTF128 addr:$src)>; +def : Pat<(v16i16 (X86SubVBroadcast (bc_v8i16 (loadv2i64 addr:$src)))), + (VBROADCASTF128 addr:$src)>; +def : Pat<(v32i8 (X86SubVBroadcast (bc_v16i8 (loadv2i64 addr:$src)))), + (VBROADCASTF128 addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// VINSERTF128 - Insert packed floating-point values +// +let hasSideEffects = 0, ExeDomain = SSEPackedSingle in { +def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst), + (ins VR256:$src1, VR128:$src2, u8imm:$src3), + "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + []>, Sched<[WriteFShuffle256]>, VEX_4V, VEX_L; +let mayLoad = 1 in +def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst), + (ins VR256:$src1, f128mem:$src2, u8imm:$src3), + "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + []>, Sched<[WriteFShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L; +} + +// To create a 256-bit all ones value, we should produce VCMPTRUEPS +// with YMM register containing zero. +// FIXME: Avoid producing vxorps to clear the fake inputs. +let Predicates = [HasAVX1Only] in { +def : Pat<(v8i32 immAllOnesV), (VCMPPSYrri (AVX_SET0), (AVX_SET0), 0xf)>; +} + +multiclass vinsert_lowering { + def : Pat<(vinsert128_insert:$ins (To VR256:$src1), (From VR128:$src2), + (iPTR imm)), + (!cast(InstrStr#rr) VR256:$src1, VR128:$src2, + (INSERT_get_vinsert128_imm VR256:$ins))>; + def : Pat<(vinsert128_insert:$ins (To VR256:$src1), + (From (bitconvert (memop_frag addr:$src2))), + (iPTR imm)), + (!cast(InstrStr#rm) VR256:$src1, addr:$src2, + (INSERT_get_vinsert128_imm VR256:$ins))>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm : vinsert_lowering<"VINSERTF128", v4f32, v8f32, loadv4f32>; + defm : vinsert_lowering<"VINSERTF128", v2f64, v4f64, loadv2f64>; +} + +let Predicates = [HasAVX1Only] in { + defm : vinsert_lowering<"VINSERTF128", v2i64, v4i64, loadv2i64>; + defm : vinsert_lowering<"VINSERTF128", v4i32, v8i32, loadv2i64>; + defm : vinsert_lowering<"VINSERTF128", v8i16, v16i16, loadv2i64>; + defm : vinsert_lowering<"VINSERTF128", v16i8, v32i8, loadv2i64>; +} + +//===----------------------------------------------------------------------===// +// VEXTRACTF128 - Extract packed floating-point values +// +let hasSideEffects = 0, ExeDomain = SSEPackedSingle in { +def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst), + (ins VR256:$src1, u8imm:$src2), + "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, Sched<[WriteFShuffle256]>, VEX, VEX_L; +let mayStore = 1 in +def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs), + (ins f128mem:$dst, VR256:$src1, u8imm:$src2), + "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, Sched<[WriteFStoreX]>, VEX, VEX_L; +} + +multiclass vextract_lowering { + def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)), + (To (!cast(InstrStr#rr) + (From VR256:$src1), + (EXTRACT_get_vextract128_imm VR128:$ext)))>; + def : Pat<(store (To (vextract128_extract:$ext (From VR256:$src1), + (iPTR imm))), addr:$dst), + (!cast(InstrStr#mr) addr:$dst, VR256:$src1, + (EXTRACT_get_vextract128_imm VR128:$ext))>; +} + +// AVX1 patterns +let Predicates = [HasAVX, NoVLX] in { + defm : vextract_lowering<"VEXTRACTF128", v8f32, v4f32>; + defm : vextract_lowering<"VEXTRACTF128", v4f64, v2f64>; +} + +let Predicates = [HasAVX1Only] in { + defm : vextract_lowering<"VEXTRACTF128", v4i64, v2i64>; + defm : vextract_lowering<"VEXTRACTF128", v8i32, v4i32>; + defm : vextract_lowering<"VEXTRACTF128", v16i16, v8i16>; + defm : vextract_lowering<"VEXTRACTF128", v32i8, v16i8>; +} + +//===----------------------------------------------------------------------===// +// VMASKMOV - Conditional SIMD Packed Loads and Stores +// +multiclass avx_movmask_rm opc_rm, bits<8> opc_mr, string OpcodeStr, + Intrinsic IntLd, Intrinsic IntLd256, + Intrinsic IntSt, Intrinsic IntSt256> { + def rm : AVX8I, + VEX_4V, Sched<[WriteFMaskedLoad]>; + def Yrm : AVX8I, + VEX_4V, VEX_L, Sched<[WriteFMaskedLoadY]>; + def mr : AVX8I, + VEX_4V, Sched<[WriteFMaskedStore]>; + def Ymr : AVX8I, + VEX_4V, VEX_L, Sched<[WriteFMaskedStoreY]>; +} + +let ExeDomain = SSEPackedSingle in +defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps", + int_x86_avx_maskload_ps, + int_x86_avx_maskload_ps_256, + int_x86_avx_maskstore_ps, + int_x86_avx_maskstore_ps_256>; +let ExeDomain = SSEPackedDouble in +defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd", + int_x86_avx_maskload_pd, + int_x86_avx_maskload_pd_256, + int_x86_avx_maskstore_pd, + int_x86_avx_maskstore_pd_256>; + +//===----------------------------------------------------------------------===// +// VPERMIL - Permute Single and Double Floating-Point Values +// + +multiclass avx_permil opc_rm, bits<8> opc_rmi, string OpcodeStr, + RegisterClass RC, X86MemOperand x86memop_f, + X86MemOperand x86memop_i, PatFrag i_frag, + ValueType f_vt, ValueType i_vt, + X86FoldableSchedWrite sched, + X86FoldableSchedWrite varsched> { + let Predicates = [HasAVX, NoVLX] in { + def rr : AVX8I, VEX_4V, + Sched<[varsched]>; + def rm : AVX8I, VEX_4V, + Sched<[varsched.Folded, ReadAfterLd]>; + + def ri : AVXAIi8, VEX, + Sched<[sched]>; + def mi : AVXAIi8, VEX, + Sched<[sched.Folded]>; + }// Predicates = [HasAVX, NoVLX] +} + +let ExeDomain = SSEPackedSingle in { + defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem, + loadv2i64, v4f32, v4i32, SchedWriteFShuffle.XMM, + SchedWriteFVarShuffle.XMM>; + defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem, + loadv4i64, v8f32, v8i32, SchedWriteFShuffle.YMM, + SchedWriteFVarShuffle.YMM>, VEX_L; +} +let ExeDomain = SSEPackedDouble in { + defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem, + loadv2i64, v2f64, v2i64, SchedWriteFShuffle.XMM, + SchedWriteFVarShuffle.XMM>; + defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem, + loadv4i64, v4f64, v4i64, SchedWriteFShuffle.YMM, + SchedWriteFVarShuffle.YMM>, VEX_L; +} + +//===----------------------------------------------------------------------===// +// VPERM2F128 - Permute Floating-Point Values in 128-bit chunks +// + +let ExeDomain = SSEPackedSingle in { +let isCommutable = 1 in +def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst), + (ins VR256:$src1, VR256:$src2, u8imm:$src3), + "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set VR256:$dst, (v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, + (i8 imm:$src3))))]>, VEX_4V, VEX_L, + Sched<[WriteFShuffle256]>; +def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst), + (ins VR256:$src1, f256mem:$src2, u8imm:$src3), + "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4f64 addr:$src2), + (i8 imm:$src3)))]>, VEX_4V, VEX_L, + Sched<[WriteFShuffle256Ld, ReadAfterLd]>; +} + +// Immediate transform to help with commuting. +def Perm2XCommuteImm : SDNodeXFormgetZExtValue() ^ 0x22, SDLoc(N)); +}]>; + +let Predicates = [HasAVX] in { +// Pattern with load in other operand. +def : Pat<(v4f64 (X86VPerm2x128 (loadv4f64 addr:$src2), + VR256:$src1, (i8 imm:$imm))), + (VPERM2F128rm VR256:$src1, addr:$src2, (Perm2XCommuteImm imm:$imm))>; +} + +let Predicates = [HasAVX1Only] in { +def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))), + (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>; +def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, + (loadv4i64 addr:$src2), (i8 imm:$imm))), + (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>; +// Pattern with load in other operand. +def : Pat<(v4i64 (X86VPerm2x128 (loadv4i64 addr:$src2), + VR256:$src1, (i8 imm:$imm))), + (VPERM2F128rm VR256:$src1, addr:$src2, (Perm2XCommuteImm imm:$imm))>; +} + +//===----------------------------------------------------------------------===// +// VZERO - Zero YMM registers +// Note: These instruction do not affect the YMM16-YMM31. +// + +let SchedRW = [WriteSystem] in { +let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, + YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in { + // Zero All YMM registers + def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", + [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, + Requires<[HasAVX]>, VEX_WIG; + + // Zero Upper bits of YMM registers + def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", + [(int_x86_avx_vzeroupper)]>, PS, VEX, + Requires<[HasAVX]>, VEX_WIG; +} // Defs +} // SchedRW + +//===----------------------------------------------------------------------===// +// Half precision conversion instructions +// + +multiclass f16c_ph2ps { + def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src), + "vcvtph2ps\t{$src, $dst|$dst, $src}", + [(set RC:$dst, (X86cvtph2ps VR128:$src))]>, + T8PD, VEX, Sched<[sched]>; + let hasSideEffects = 0, mayLoad = 1 in + def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), + "vcvtph2ps\t{$src, $dst|$dst, $src}", + [(set RC:$dst, (X86cvtph2ps (bc_v8i16 + (loadv2i64 addr:$src))))]>, + T8PD, VEX, Sched<[sched.Folded]>; +} + +multiclass f16c_ps2ph { + def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst), + (ins RC:$src1, i32u8imm:$src2), + "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, (X86cvtps2ph RC:$src1, imm:$src2))]>, + TAPD, VEX, Sched<[RR]>; + let hasSideEffects = 0, mayStore = 1 in + def mr : Ii8<0x1D, MRMDestMem, (outs), + (ins x86memop:$dst, RC:$src1, i32u8imm:$src2), + "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + TAPD, VEX, Sched<[MR]>; +} + +let Predicates = [HasF16C, NoVLX] in { + defm VCVTPH2PS : f16c_ph2ps; + defm VCVTPH2PSY : f16c_ph2ps, VEX_L; + defm VCVTPS2PH : f16c_ps2ph; + defm VCVTPS2PHY : f16c_ps2ph, VEX_L; + + // Pattern match vcvtph2ps of a scalar i64 load. + def : Pat<(v4f32 (X86cvtph2ps (v8i16 (vzmovl_v2i64 addr:$src)))), + (VCVTPH2PSrm addr:$src)>; + def : Pat<(v4f32 (X86cvtph2ps (v8i16 (vzload_v2i64 addr:$src)))), + (VCVTPH2PSrm addr:$src)>; + def : Pat<(v4f32 (X86cvtph2ps (v8i16 (bitconvert + (v2i64 (scalar_to_vector (loadi64 addr:$src))))))), + (VCVTPH2PSrm addr:$src)>; + + def : Pat<(store (f64 (extractelt + (bc_v2f64 (v8i16 (X86cvtps2ph VR128:$src1, i32:$src2))), + (iPTR 0))), addr:$dst), + (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>; + def : Pat<(store (i64 (extractelt + (bc_v2i64 (v8i16 (X86cvtps2ph VR128:$src1, i32:$src2))), + (iPTR 0))), addr:$dst), + (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>; + def : Pat<(store (v8i16 (X86cvtps2ph VR256:$src1, i32:$src2)), addr:$dst), + (VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>; +} + +// Patterns for matching conversions from float to half-float and vice versa. +let Predicates = [HasF16C, NoVLX] in { + // Use MXCSR.RC for rounding instead of explicitly specifying the default + // rounding mode (Nearest-Even, encoded as 0). Both are equivalent in the + // configurations we support (the default). However, falling back to MXCSR is + // more consistent with other instructions, which are always controlled by it. + // It's encoded as 0b100. + def : Pat<(fp_to_f16 FR32:$src), + (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (v8i16 (VCVTPS2PHrr + (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 4))), sub_16bit))>; + + def : Pat<(f16_to_fp GR16:$src), + (f32 (COPY_TO_REGCLASS (v4f32 (VCVTPH2PSrr + (v4i32 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)))), FR32)) >; + + def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))), + (f32 (COPY_TO_REGCLASS (v4f32 (VCVTPH2PSrr + (v8i16 (VCVTPS2PHrr (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 4)))), FR32)) >; +} + +//===----------------------------------------------------------------------===// +// AVX2 Instructions +//===----------------------------------------------------------------------===// + +/// AVX2_blend_rmi - AVX2 blend with 8-bit immediate +multiclass AVX2_blend_rmi opc, string OpcodeStr, SDNode OpNode, + ValueType OpVT, X86FoldableSchedWrite sched, + RegisterClass RC, PatFrag memop_frag, + X86MemOperand x86memop, SDNodeXForm commuteXForm> { + let isCommutable = 1 in + def rri : AVX2AIi8, + Sched<[sched]>, VEX_4V; + def rmi : AVX2AIi8, + Sched<[sched.Folded, ReadAfterLd]>, VEX_4V; + + // Pattern to commute if load is in first source. + def : Pat<(OpVT (OpNode (bitconvert (memop_frag addr:$src2)), + RC:$src1, imm:$src3)), + (!cast(NAME#"rmi") RC:$src1, addr:$src2, + (commuteXForm imm:$src3))>; +} + +defm VPBLENDD : AVX2_blend_rmi<0x02, "vpblendd", X86Blendi, v4i32, + SchedWriteBlend.XMM, VR128, loadv2i64, i128mem, + BlendCommuteImm4>; +defm VPBLENDDY : AVX2_blend_rmi<0x02, "vpblendd", X86Blendi, v8i32, + SchedWriteBlend.YMM, VR256, loadv4i64, i256mem, + BlendCommuteImm8>, VEX_L; + +// For insertion into the zero index (low half) of a 256-bit vector, it is +// more efficient to generate a blend with immediate instead of an insert*128. +let Predicates = [HasAVX2] in { +def : Pat<(insert_subvector (v8i32 VR256:$src1), (v4i32 VR128:$src2), (iPTR 0)), + (VPBLENDDYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +def : Pat<(insert_subvector (v4i64 VR256:$src1), (v2i64 VR128:$src2), (iPTR 0)), + (VPBLENDDYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +def : Pat<(insert_subvector (v16i16 VR256:$src1), (v8i16 VR128:$src2), (iPTR 0)), + (VPBLENDDYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +def : Pat<(insert_subvector (v32i8 VR256:$src1), (v16i8 VR128:$src2), (iPTR 0)), + (VPBLENDDYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +} + +let Predicates = [HasAVX1Only] in { +def : Pat<(insert_subvector (v8i32 VR256:$src1), (v4i32 VR128:$src2), (iPTR 0)), + (VBLENDPSYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +def : Pat<(insert_subvector (v4i64 VR256:$src1), (v2i64 VR128:$src2), (iPTR 0)), + (VBLENDPSYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +def : Pat<(insert_subvector (v16i16 VR256:$src1), (v8i16 VR128:$src2), (iPTR 0)), + (VBLENDPSYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +def : Pat<(insert_subvector (v32i8 VR256:$src1), (v16i8 VR128:$src2), (iPTR 0)), + (VBLENDPSYrri VR256:$src1, + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + VR128:$src2, sub_xmm), 0xf)>; +} + +//===----------------------------------------------------------------------===// +// VPBROADCAST - Load from memory and broadcast to all elements of the +// destination operand +// +multiclass avx2_broadcast opc, string OpcodeStr, + X86MemOperand x86memop, PatFrag ld_frag, + ValueType OpVT128, ValueType OpVT256, Predicate prd> { + let Predicates = [HasAVX2, prd] in { + def rr : AVX28I, + Sched<[SchedWriteShuffle.XMM]>, VEX; + def rm : AVX28I, + Sched<[SchedWriteShuffle.XMM.Folded]>, VEX; + def Yrr : AVX28I, + Sched<[WriteShuffle256]>, VEX, VEX_L; + def Yrm : AVX28I, + Sched<[SchedWriteShuffle.XMM.Folded]>, VEX, VEX_L; + + // Provide aliases for broadcast from the same register class that + // automatically does the extract. + def : Pat<(OpVT256 (X86VBroadcast (OpVT256 VR256:$src))), + (!cast(NAME#"Yrr") + (OpVT128 (EXTRACT_SUBREG (OpVT256 VR256:$src),sub_xmm)))>; + } +} + +defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8, + v16i8, v32i8, NoVLX_Or_NoBWI>; +defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16, + v8i16, v16i16, NoVLX_Or_NoBWI>; +defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32, + v4i32, v8i32, NoVLX>; +defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64, + v2i64, v4i64, NoVLX>; + +let Predicates = [HasAVX2, NoVLX] in { + // 32-bit targets will fail to load a i64 directly but can use ZEXT_LOAD. + def : Pat<(v2i64 (X86VBroadcast (v2i64 (X86vzload addr:$src)))), + (VPBROADCASTQrm addr:$src)>; + def : Pat<(v4i64 (X86VBroadcast (v4i64 (X86vzload addr:$src)))), + (VPBROADCASTQYrm addr:$src)>; + + def : Pat<(v4i32 (X86VBroadcast (v4i32 (scalar_to_vector (loadi32 addr:$src))))), + (VPBROADCASTDrm addr:$src)>; + def : Pat<(v8i32 (X86VBroadcast (v4i32 (scalar_to_vector (loadi32 addr:$src))))), + (VPBROADCASTDYrm addr:$src)>; + def : Pat<(v2i64 (X86VBroadcast (v2i64 (scalar_to_vector (loadi64 addr:$src))))), + (VPBROADCASTQrm addr:$src)>; + def : Pat<(v4i64 (X86VBroadcast (v2i64 (scalar_to_vector (loadi64 addr:$src))))), + (VPBROADCASTQYrm addr:$src)>; +} +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { + // loadi16 is tricky to fold, because !isTypeDesirableForOp, justifiably. + // This means we'll encounter truncated i32 loads; match that here. + def : Pat<(v8i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))), + (VPBROADCASTWrm addr:$src)>; + def : Pat<(v16i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))), + (VPBROADCASTWYrm addr:$src)>; + def : Pat<(v8i16 (X86VBroadcast + (i16 (trunc (i32 (zextloadi16 addr:$src)))))), + (VPBROADCASTWrm addr:$src)>; + def : Pat<(v16i16 (X86VBroadcast + (i16 (trunc (i32 (zextloadi16 addr:$src)))))), + (VPBROADCASTWYrm addr:$src)>; +} + +let Predicates = [HasAVX2, NoVLX] in { + // Provide aliases for broadcast from the same register class that + // automatically does the extract. + def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))), + (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), + sub_xmm)))>; + def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))), + (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), + sub_xmm)))>; +} + +let Predicates = [HasAVX2, NoVLX] in { + // Provide fallback in case the load node that is used in the patterns above + // is used by additional users, which prevents the pattern selection. + def : Pat<(v4f32 (X86VBroadcast FR32:$src)), + (VBROADCASTSSrr (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)))>; + def : Pat<(v8f32 (X86VBroadcast FR32:$src)), + (VBROADCASTSSYrr (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)))>; + def : Pat<(v4f64 (X86VBroadcast FR64:$src)), + (VBROADCASTSDYrr (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))>; +} + +let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { + def : Pat<(v16i8 (X86VBroadcast GR8:$src)), + (VPBROADCASTBrr (v16i8 (COPY_TO_REGCLASS + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), + GR8:$src, sub_8bit)), + VR128)))>; + def : Pat<(v32i8 (X86VBroadcast GR8:$src)), + (VPBROADCASTBYrr (v16i8 (COPY_TO_REGCLASS + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), + GR8:$src, sub_8bit)), + VR128)))>; + + def : Pat<(v8i16 (X86VBroadcast GR16:$src)), + (VPBROADCASTWrr (v8i16 (COPY_TO_REGCLASS + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), + GR16:$src, sub_16bit)), + VR128)))>; + def : Pat<(v16i16 (X86VBroadcast GR16:$src)), + (VPBROADCASTWYrr (v8i16 (COPY_TO_REGCLASS + (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), + GR16:$src, sub_16bit)), + VR128)))>; +} +let Predicates = [HasAVX2, NoVLX] in { + def : Pat<(v4i32 (X86VBroadcast GR32:$src)), + (VPBROADCASTDrr (v4i32 (COPY_TO_REGCLASS GR32:$src, VR128)))>; + def : Pat<(v8i32 (X86VBroadcast GR32:$src)), + (VPBROADCASTDYrr (v4i32 (COPY_TO_REGCLASS GR32:$src, VR128)))>; + def : Pat<(v2i64 (X86VBroadcast GR64:$src)), + (VPBROADCASTQrr (v2i64 (COPY_TO_REGCLASS GR64:$src, VR128)))>; + def : Pat<(v4i64 (X86VBroadcast GR64:$src)), + (VPBROADCASTQYrr (v2i64 (COPY_TO_REGCLASS GR64:$src, VR128)))>; +} + +// AVX1 broadcast patterns +let Predicates = [HasAVX1Only] in { +def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))), + (VBROADCASTSSYrm addr:$src)>; +def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))), + (VBROADCASTSDYrm addr:$src)>; +def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))), + (VBROADCASTSSrm addr:$src)>; +} + + // Provide fallback in case the load node that is used in the patterns above + // is used by additional users, which prevents the pattern selection. +let Predicates = [HasAVX, NoVLX] in { + // 128bit broadcasts: + def : Pat<(v2f64 (X86VBroadcast f64:$src)), + (VMOVDDUPrr (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))>; + def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))), + (VMOVDDUPrm addr:$src)>; + + def : Pat<(v2f64 (X86VBroadcast v2f64:$src)), + (VMOVDDUPrr VR128:$src)>; + def : Pat<(v2f64 (X86VBroadcast (loadv2f64 addr:$src))), + (VMOVDDUPrm addr:$src)>; +} + +let Predicates = [HasAVX1Only] in { + def : Pat<(v4f32 (X86VBroadcast FR32:$src)), + (VPERMILPSri (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 0)>; + def : Pat<(v8f32 (X86VBroadcast FR32:$src)), + (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), + (v4f32 (VPERMILPSri (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 0)), sub_xmm), + (v4f32 (VPERMILPSri (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 0)), 1)>; + def : Pat<(v4f64 (X86VBroadcast FR64:$src)), + (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), + (v2f64 (VMOVDDUPrr (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))), sub_xmm), + (v2f64 (VMOVDDUPrr (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))), 1)>; + + def : Pat<(v4i32 (X86VBroadcast GR32:$src)), + (VPSHUFDri (v4i32 (COPY_TO_REGCLASS GR32:$src, VR128)), 0)>; + def : Pat<(v8i32 (X86VBroadcast GR32:$src)), + (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), + (v4i32 (VPSHUFDri (v4i32 (COPY_TO_REGCLASS GR32:$src, VR128)), 0)), sub_xmm), + (v4i32 (VPSHUFDri (v4i32 (COPY_TO_REGCLASS GR32:$src, VR128)), 0)), 1)>; + def : Pat<(v4i64 (X86VBroadcast GR64:$src)), + (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), + (v4i32 (VPSHUFDri (v4i32 (COPY_TO_REGCLASS GR64:$src, VR128)), 0x44)), sub_xmm), + (v4i32 (VPSHUFDri (v4i32 (COPY_TO_REGCLASS GR64:$src, VR128)), 0x44)), 1)>; + + def : Pat<(v2i64 (X86VBroadcast i64:$src)), + (VPSHUFDri (v4i32 (COPY_TO_REGCLASS GR64:$src, VR128)), 0x44)>; + def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))), + (VMOVDDUPrm addr:$src)>; +} + +//===----------------------------------------------------------------------===// +// VPERM - Permute instructions +// + +multiclass avx2_perm opc, string OpcodeStr, PatFrag mem_frag, + ValueType OpVT, X86FoldableSchedWrite Sched, + X86MemOperand memOp> { + let Predicates = [HasAVX2, NoVLX] in { + def Yrr : AVX28I, + Sched<[Sched]>, VEX_4V, VEX_L; + def Yrm : AVX28I, + Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L; + } +} + +defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteVarShuffle256, + i256mem>; +let ExeDomain = SSEPackedSingle in +defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFVarShuffle256, + f256mem>; + +multiclass avx2_perm_imm opc, string OpcodeStr, PatFrag mem_frag, + ValueType OpVT, X86FoldableSchedWrite Sched, + X86MemOperand memOp> { + let Predicates = [HasAVX2, NoVLX] in { + def Yri : AVX2AIi8, + Sched<[Sched]>, VEX, VEX_L; + def Ymi : AVX2AIi8, + Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L; + } +} + +defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64, + WriteShuffle256, i256mem>, VEX_W; +let ExeDomain = SSEPackedDouble in +defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64, + WriteFShuffle256, f256mem>, VEX_W; + +//===----------------------------------------------------------------------===// +// VPERM2I128 - Permute Floating-Point Values in 128-bit chunks +// +let isCommutable = 1 in +def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst), + (ins VR256:$src1, VR256:$src2, u8imm:$src3), + "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, + (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>, + VEX_4V, VEX_L; +def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst), + (ins VR256:$src1, f256mem:$src2, u8imm:$src3), + "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2), + (i8 imm:$src3)))]>, + Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L; + +let Predicates = [HasAVX2] in +def : Pat<(v4i64 (X86VPerm2x128 (loadv4i64 addr:$src2), + VR256:$src1, (i8 imm:$imm))), + (VPERM2I128rm VR256:$src1, addr:$src2, (Perm2XCommuteImm imm:$imm))>; + + +//===----------------------------------------------------------------------===// +// VINSERTI128 - Insert packed integer values +// +let hasSideEffects = 0 in { +def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst), + (ins VR256:$src1, VR128:$src2, u8imm:$src3), + "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L; +let mayLoad = 1 in +def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst), + (ins VR256:$src1, i128mem:$src2, u8imm:$src3), + "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L; +} + +let Predicates = [HasAVX2, NoVLX] in { + defm : vinsert_lowering<"VINSERTI128", v2i64, v4i64, loadv2i64>; + defm : vinsert_lowering<"VINSERTI128", v4i32, v8i32, loadv2i64>; + defm : vinsert_lowering<"VINSERTI128", v8i16, v16i16, loadv2i64>; + defm : vinsert_lowering<"VINSERTI128", v16i8, v32i8, loadv2i64>; +} + +//===----------------------------------------------------------------------===// +// VEXTRACTI128 - Extract packed integer values +// +def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst), + (ins VR256:$src1, u8imm:$src2), + "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + Sched<[WriteShuffle256]>, VEX, VEX_L; +let hasSideEffects = 0, mayStore = 1 in +def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs), + (ins i128mem:$dst, VR256:$src1, u8imm:$src2), + "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, + Sched<[SchedWriteVecMoveLS.XMM.MR]>, VEX, VEX_L; + +let Predicates = [HasAVX2, NoVLX] in { + defm : vextract_lowering<"VEXTRACTI128", v4i64, v2i64>; + defm : vextract_lowering<"VEXTRACTI128", v8i32, v4i32>; + defm : vextract_lowering<"VEXTRACTI128", v16i16, v8i16>; + defm : vextract_lowering<"VEXTRACTI128", v32i8, v16i8>; +} + +//===----------------------------------------------------------------------===// +// VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores +// +multiclass avx2_pmovmask { + def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, i128mem:$src2), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, + VEX_4V, Sched<[WriteVecMaskedLoad]>; + def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst), + (ins VR256:$src1, i256mem:$src2), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, + VEX_4V, VEX_L, Sched<[WriteVecMaskedLoadY]>; + def mr : AVX28I<0x8e, MRMDestMem, (outs), + (ins i128mem:$dst, VR128:$src1, VR128:$src2), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, + VEX_4V, Sched<[WriteVecMaskedStore]>; + def Ymr : AVX28I<0x8e, MRMDestMem, (outs), + (ins i256mem:$dst, VR256:$src1, VR256:$src2), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, + VEX_4V, VEX_L, Sched<[WriteVecMaskedStoreY]>; +} + +defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd", + int_x86_avx2_maskload_d, + int_x86_avx2_maskload_d_256, + int_x86_avx2_maskstore_d, + int_x86_avx2_maskstore_d_256>; +defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq", + int_x86_avx2_maskload_q, + int_x86_avx2_maskload_q_256, + int_x86_avx2_maskstore_q, + int_x86_avx2_maskstore_q_256>, VEX_W; + +multiclass maskmov_lowering { + // masked store + def: Pat<(X86mstore addr:$ptr, (MaskVT RC:$mask), (VT RC:$src)), + (!cast(InstrStr#"mr") addr:$ptr, RC:$mask, RC:$src)>; + // masked load + def: Pat<(VT (X86mload addr:$ptr, (MaskVT RC:$mask), undef)), + (!cast(InstrStr#"rm") RC:$mask, addr:$ptr)>; + def: Pat<(VT (X86mload addr:$ptr, (MaskVT RC:$mask), + (VT (bitconvert (ZeroVT immAllZerosV))))), + (!cast(InstrStr#"rm") RC:$mask, addr:$ptr)>; + def: Pat<(VT (X86mload addr:$ptr, (MaskVT RC:$mask), (VT RC:$src0))), + (!cast(BlendStr#"rr") + RC:$src0, + (VT (!cast(InstrStr#"rm") RC:$mask, addr:$ptr)), + RC:$mask)>; +} +let Predicates = [HasAVX] in { + defm : maskmov_lowering<"VMASKMOVPS", VR128, v4f32, v4i32, "VBLENDVPS", v4i32>; + defm : maskmov_lowering<"VMASKMOVPD", VR128, v2f64, v2i64, "VBLENDVPD", v4i32>; + defm : maskmov_lowering<"VMASKMOVPSY", VR256, v8f32, v8i32, "VBLENDVPSY", v8i32>; + defm : maskmov_lowering<"VMASKMOVPDY", VR256, v4f64, v4i64, "VBLENDVPDY", v8i32>; +} +let Predicates = [HasAVX1Only] in { + // load/store i32/i64 not supported use ps/pd version + defm : maskmov_lowering<"VMASKMOVPSY", VR256, v8i32, v8i32, "VBLENDVPSY", v8i32>; + defm : maskmov_lowering<"VMASKMOVPDY", VR256, v4i64, v4i64, "VBLENDVPDY", v8i32>; + defm : maskmov_lowering<"VMASKMOVPS", VR128, v4i32, v4i32, "VBLENDVPS", v4i32>; + defm : maskmov_lowering<"VMASKMOVPD", VR128, v2i64, v2i64, "VBLENDVPD", v4i32>; +} +let Predicates = [HasAVX2] in { + defm : maskmov_lowering<"VPMASKMOVDY", VR256, v8i32, v8i32, "VBLENDVPSY", v8i32>; + defm : maskmov_lowering<"VPMASKMOVQY", VR256, v4i64, v4i64, "VBLENDVPDY", v8i32>; + defm : maskmov_lowering<"VPMASKMOVD", VR128, v4i32, v4i32, "VBLENDVPS", v4i32>; + defm : maskmov_lowering<"VPMASKMOVQ", VR128, v2i64, v2i64, "VBLENDVPD", v4i32>; +} + +//===----------------------------------------------------------------------===// +// SubVector Broadcasts +// Provide fallback in case the load node that is used in the patterns above +// is used by additional users, which prevents the pattern selection. + +let Predicates = [HasAVX2, NoVLX] in { +def : Pat<(v4i64 (X86SubVBroadcast (v2i64 VR128:$src))), + (VINSERTI128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v2i64 VR128:$src), 1)>; +def : Pat<(v8i32 (X86SubVBroadcast (v4i32 VR128:$src))), + (VINSERTI128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v4i32 VR128:$src), 1)>; +def : Pat<(v16i16 (X86SubVBroadcast (v8i16 VR128:$src))), + (VINSERTI128rr (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v8i16 VR128:$src), 1)>; +def : Pat<(v32i8 (X86SubVBroadcast (v16i8 VR128:$src))), + (VINSERTI128rr (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v16i8 VR128:$src), 1)>; +} + +let Predicates = [HasAVX, NoVLX] in { +def : Pat<(v4f64 (X86SubVBroadcast (v2f64 VR128:$src))), + (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v2f64 VR128:$src), 1)>; +def : Pat<(v8f32 (X86SubVBroadcast (v4f32 VR128:$src))), + (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v4f32 VR128:$src), 1)>; +} + +let Predicates = [HasAVX1Only] in { +def : Pat<(v4i64 (X86SubVBroadcast (v2i64 VR128:$src))), + (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v2i64 VR128:$src), 1)>; +def : Pat<(v8i32 (X86SubVBroadcast (v4i32 VR128:$src))), + (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v4i32 VR128:$src), 1)>; +def : Pat<(v16i16 (X86SubVBroadcast (v8i16 VR128:$src))), + (VINSERTF128rr (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v8i16 VR128:$src), 1)>; +def : Pat<(v32i8 (X86SubVBroadcast (v16i8 VR128:$src))), + (VINSERTF128rr (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm), + (v16i8 VR128:$src), 1)>; +} + +//===----------------------------------------------------------------------===// +// Variable Bit Shifts +// +multiclass avx2_var_shift opc, string OpcodeStr, SDNode OpNode, + ValueType vt128, ValueType vt256> { + def rr : AVX28I, + VEX_4V, Sched<[SchedWriteVarVecShift.XMM]>; + def rm : AVX28I, + VEX_4V, Sched<[SchedWriteVarVecShift.XMM.Folded, ReadAfterLd]>; + def Yrr : AVX28I, + VEX_4V, VEX_L, Sched<[SchedWriteVarVecShift.YMM]>; + def Yrm : AVX28I, + VEX_4V, VEX_L, Sched<[SchedWriteVarVecShift.YMM.Folded, ReadAfterLd]>; +} + +let Predicates = [HasAVX2, NoVLX] in { + defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>; + defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W; + defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>; + defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W; + defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>; + + def : Pat<(v4i32 (X86vsrav VR128:$src1, VR128:$src2)), + (VPSRAVDrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4i32 (X86vsrav VR128:$src1, + (bitconvert (loadv2i64 addr:$src2)))), + (VPSRAVDrm VR128:$src1, addr:$src2)>; + def : Pat<(v8i32 (X86vsrav VR256:$src1, VR256:$src2)), + (VPSRAVDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (X86vsrav VR256:$src1, + (bitconvert (loadv4i64 addr:$src2)))), + (VPSRAVDYrm VR256:$src1, addr:$src2)>; +} + +//===----------------------------------------------------------------------===// +// VGATHER - GATHER Operations + +// FIXME: Improve scheduling of gather instructions. +multiclass avx2_gather opc, string OpcodeStr, ValueType VTx, + ValueType VTy, PatFrag GatherNode128, + PatFrag GatherNode256, RegisterClass RC256, + X86MemOperand memop128, X86MemOperand memop256, + ValueType MTx = VTx, ValueType MTy = VTy> { + def rm : AVX28I, + VEX, Sched<[WriteLoad]>; + def Yrm : AVX28I, + VEX, VEX_L, Sched<[WriteLoad]>; +} + +let Predicates = [UseAVX2] in { + let mayLoad = 1, hasSideEffects = 0, Constraints + = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb" + in { + defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", v2i64, v4i64, mgatherv4i32, + mgatherv4i32, VR256, vx128mem, vx256mem>, VEX_W; + defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", v2i64, v4i64, mgatherv2i64, + mgatherv4i64, VR256, vx128mem, vy256mem>, VEX_W; + defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", v4i32, v8i32, mgatherv4i32, + mgatherv8i32, VR256, vx128mem, vy256mem>; + defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", v4i32, v4i32, mgatherv2i64, + mgatherv4i64, VR128, vx64mem, vy128mem>; + + let ExeDomain = SSEPackedDouble in { + defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", v2f64, v4f64, mgatherv4i32, + mgatherv4i32, VR256, vx128mem, vx256mem, + v2i64, v4i64>, VEX_W; + defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", v2f64, v4f64, mgatherv2i64, + mgatherv4i64, VR256, vx128mem, vy256mem, + v2i64, v4i64>, VEX_W; + } + + let ExeDomain = SSEPackedSingle in { + defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", v4f32, v8f32, mgatherv4i32, + mgatherv8i32, VR256, vx128mem, vy256mem, + v4i32, v8i32>; + defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", v4f32, v4f32, mgatherv2i64, + mgatherv4i64, VR128, vx64mem, vy128mem, + v4i32, v4i32>; + } + } +} + +//===----------------------------------------------------------------------===// +// Extra selection patterns for f128, f128mem + +// movaps is shorter than movdqa. movaps is in SSE and movdqa is in SSE2. +def : Pat<(alignedstore (f128 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, (COPY_TO_REGCLASS (f128 VR128:$src), VR128))>; +def : Pat<(store (f128 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, (COPY_TO_REGCLASS (f128 VR128:$src), VR128))>; + +def : Pat<(alignedloadf128 addr:$src), + (COPY_TO_REGCLASS (MOVAPSrm addr:$src), VR128)>; +def : Pat<(loadf128 addr:$src), + (COPY_TO_REGCLASS (MOVUPSrm addr:$src), VR128)>; + +// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2 +def : Pat<(f128 (X86fand VR128:$src1, (memopf128 addr:$src2))), + (COPY_TO_REGCLASS + (ANDPSrm (COPY_TO_REGCLASS VR128:$src1, VR128), f128mem:$src2), + VR128)>; + +def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)), + (COPY_TO_REGCLASS + (ANDPSrr (COPY_TO_REGCLASS VR128:$src1, VR128), + (COPY_TO_REGCLASS VR128:$src2, VR128)), VR128)>; + +def : Pat<(f128 (X86for VR128:$src1, (memopf128 addr:$src2))), + (COPY_TO_REGCLASS + (ORPSrm (COPY_TO_REGCLASS VR128:$src1, VR128), f128mem:$src2), + VR128)>; + +def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)), + (COPY_TO_REGCLASS + (ORPSrr (COPY_TO_REGCLASS VR128:$src1, VR128), + (COPY_TO_REGCLASS VR128:$src2, VR128)), VR128)>; + +def : Pat<(f128 (X86fxor VR128:$src1, (memopf128 addr:$src2))), + (COPY_TO_REGCLASS + (XORPSrm (COPY_TO_REGCLASS VR128:$src1, VR128), f128mem:$src2), + VR128)>; + +def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)), + (COPY_TO_REGCLASS + (XORPSrr (COPY_TO_REGCLASS VR128:$src1, VR128), + (COPY_TO_REGCLASS VR128:$src2, VR128)), VR128)>; + +//===----------------------------------------------------------------------===// +// GFNI instructions +//===----------------------------------------------------------------------===// + +multiclass GF2P8MULB_rm { + let ExeDomain = SSEPackedInt, + AsmString = !if(Is2Addr, + OpcodeStr##"\t{$src2, $dst|$dst, $src2}", + OpcodeStr##"\t{$src2, $src1, $dst|$dst, $src1, $src2}") in { + let isCommutable = 1 in + def rr : PDI<0xCF, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), "", + [(set RC:$dst, (OpVT (X86GF2P8mulb RC:$src1, RC:$src2)))]>, + Sched<[SchedWriteVecALU.XMM]>, T8PD; + + def rm : PDI<0xCF, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, X86MemOp:$src2), "", + [(set RC:$dst, (OpVT (X86GF2P8mulb RC:$src1, + (bitconvert (MemOpFrag addr:$src2)))))]>, + Sched<[SchedWriteVecALU.XMM.Folded, ReadAfterLd]>, T8PD; + } +} + +multiclass GF2P8AFFINE_rmi Op, string OpStr, ValueType OpVT, + SDNode OpNode, RegisterClass RC, PatFrag MemOpFrag, + X86MemOperand X86MemOp, bit Is2Addr = 0> { + let AsmString = !if(Is2Addr, + OpStr##"\t{$src3, $src2, $dst|$dst, $src2, $src3}", + OpStr##"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}") in { + def rri : Ii8, Sched<[SchedWriteVecALU.XMM]>; + def rmi : Ii8, + Sched<[SchedWriteVecALU.XMM.Folded, ReadAfterLd]>; + } +} + +multiclass GF2P8AFFINE_common Op, string OpStr, SDNode OpNode> { + let Constraints = "$src1 = $dst", + Predicates = [HasGFNI, UseSSE2] in + defm NAME : GF2P8AFFINE_rmi; + let Predicates = [HasGFNI, HasAVX, NoVLX_Or_NoBWI] in { + defm V##NAME : GF2P8AFFINE_rmi, VEX_4V, VEX_W; + defm V##NAME##Y : GF2P8AFFINE_rmi, VEX_4V, VEX_L, VEX_W; + } +} + +// GF2P8MULB +let Constraints = "$src1 = $dst", + Predicates = [HasGFNI, UseSSE2] in +defm GF2P8MULB : GF2P8MULB_rm<"gf2p8mulb", v16i8, VR128, memopv2i64, + i128mem, 1>; +let Predicates = [HasGFNI, HasAVX, NoVLX_Or_NoBWI] in { + defm VGF2P8MULB : GF2P8MULB_rm<"vgf2p8mulb", v16i8, VR128, loadv2i64, + i128mem>, VEX_4V; + defm VGF2P8MULBY : GF2P8MULB_rm<"vgf2p8mulb", v32i8, VR256, loadv4i64, + i256mem>, VEX_4V, VEX_L; +} +// GF2P8AFFINEINVQB, GF2P8AFFINEQB +let isCommutable = 0 in { + defm GF2P8AFFINEINVQB : GF2P8AFFINE_common<0xCF, "gf2p8affineinvqb", + X86GF2P8affineinvqb>, TAPD; + defm GF2P8AFFINEQB : GF2P8AFFINE_common<0xCE, "gf2p8affineqb", + X86GF2P8affineqb>, TAPD; +} + diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrSVM.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrSVM.td new file mode 100644 index 0000000..2dc6e8b --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrSVM.td @@ -0,0 +1,63 @@ +//===-- X86InstrSVM.td - SVM Instruction Set Extension -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the AMD SVM instruction +// set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// SVM instructions + +let SchedRW = [WriteSystem] in { +// 0F 01 D9 +def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB; + +// 0F 01 DC +def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB; + +// 0F 01 DD +def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB; + +// 0F 01 DE +let Uses = [EAX] in +def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB; + +// 0F 01 D8 +let Uses = [EAX] in +def VMRUN32 : I<0x01, MRM_D8, (outs), (ins), "vmrun\t{%eax|eax}", []>, TB, + Requires<[Not64BitMode]>; +let Uses = [RAX] in +def VMRUN64 : I<0x01, MRM_D8, (outs), (ins), "vmrun\t{%rax|rax}", []>, TB, + Requires<[In64BitMode]>; + +// 0F 01 DA +let Uses = [EAX] in +def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins), "vmload\t{%eax|eax}", []>, TB, + Requires<[Not64BitMode]>; +let Uses = [RAX] in +def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins), "vmload\t{%rax|rax}", []>, TB, + Requires<[In64BitMode]>; + +// 0F 01 DB +let Uses = [EAX] in +def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins), "vmsave\t{%eax|eax}", []>, TB, + Requires<[Not64BitMode]>; +let Uses = [RAX] in +def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins), "vmsave\t{%rax|rax}", []>, TB, + Requires<[In64BitMode]>; + +// 0F 01 DF +let Uses = [EAX, ECX] in +def INVLPGA32 : I<0x01, MRM_DF, (outs), (ins), + "invlpga\t{%eax, %ecx|eax, ecx}", []>, TB, Requires<[Not64BitMode]>; +let Uses = [RAX, ECX] in +def INVLPGA64 : I<0x01, MRM_DF, (outs), (ins), + "invlpga\t{%rax, %ecx|rax, ecx}", []>, TB, Requires<[In64BitMode]>; +} // SchedRW diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrShiftRotate.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrShiftRotate.td new file mode 100644 index 0000000..cbcb1f7 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrShiftRotate.td @@ -0,0 +1,1031 @@ +//===-- X86InstrShiftRotate.td - Shift and Rotate Instrs ---*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the shift and rotate instructions. +// +//===----------------------------------------------------------------------===// + +// FIXME: Someone needs to smear multipattern goodness all over this file. + +let Defs = [EFLAGS] in { + +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { +let Uses = [CL] in { +def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1), + "shl{b}\t{%cl, $dst|$dst, cl}", + [(set GR8:$dst, (shl GR8:$src1, CL))]>; +def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1), + "shl{w}\t{%cl, $dst|$dst, cl}", + [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize16; +def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1), + "shl{l}\t{%cl, $dst|$dst, cl}", + [(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32; +def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1), + "shl{q}\t{%cl, $dst|$dst, cl}", + [(set GR64:$dst, (shl GR64:$src1, CL))]>; +} // Uses = [CL] + +def SAL8rCL : I<0xD2, MRM6r, (outs GR8 :$dst), (ins GR8 :$src1), "sal{b}\t{%cl, $dst|$dst, cl}", []>; +def SAL16rCL : I<0xD3, MRM6r, (outs GR16:$dst), (ins GR16:$src1), + "sal{w}\t{%cl, $dst|$dst, cl}", + []>, OpSize16; +def SAL32rCL : I<0xD3, MRM6r, (outs GR32:$dst), (ins GR32:$src1), + "sal{l}\t{%cl, $dst|$dst, cl}", + []>, OpSize32; +def SAL64rCL : RI<0xD3, MRM6r, (outs GR64:$dst), (ins GR64:$src1), + "sal{q}\t{%cl, $dst|$dst, cl}", + []>; + +def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), + "shl{b}\t{$src2, $dst|$dst, $src2}", + [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; + +def SAL8ri : Ii8<0xC0, MRM6r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), + "sal{b}\t{$src2, $dst|$dst, $src2}", + []>; + +let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. +def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), + "shl{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, + OpSize16; +def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), + "shl{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>, + OpSize32; +def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), + (ins GR64:$src1, u8imm:$src2), + "shl{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>; + +def SAL16ri : Ii8<0xC1, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), + "sal{w}\t{$src2, $dst|$dst, $src2}", + []>, + OpSize16; +def SAL32ri : Ii8<0xC1, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), + "sal{l}\t{$src2, $dst|$dst, $src2}", + []>, + OpSize32; +def SAL64ri : RIi8<0xC1, MRM6r, (outs GR64:$dst), + (ins GR64:$src1, i8imm:$src2), + "sal{q}\t{$src2, $dst|$dst, $src2}", + []>; +} // isConvertibleToThreeAddress = 1 + +// NOTE: We don't include patterns for shifts of a register by one, because +// 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one). +let hasSideEffects = 0 in { +def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1), + "shl{b}\t{$$1, $dst|$dst, 1}", []>; +def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1), + "shl{w}\t{$$1, $dst|$dst, 1}", []>, OpSize16; +def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1), + "shl{l}\t{$$1, $dst|$dst, 1}", []>, OpSize32; +def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), + "shl{q}\t{$$1, $dst|$dst, 1}", []>; +def SAL8r1 : I<0xD0, MRM6r, (outs GR8:$dst), (ins GR8:$src1), + "sal{b}\t{$$1, $dst|$dst, 1}", []>; +def SAL16r1 : I<0xD1, MRM6r, (outs GR16:$dst), (ins GR16:$src1), + "sal{w}\t{$$1, $dst|$dst, 1}", []>, OpSize16; +def SAL32r1 : I<0xD1, MRM6r, (outs GR32:$dst), (ins GR32:$src1), + "sal{l}\t{$$1, $dst|$dst, 1}", []>, OpSize32; +def SAL64r1 : RI<0xD1, MRM6r, (outs GR64:$dst), (ins GR64:$src1), + "sal{q}\t{$$1, $dst|$dst, 1}", []>; +} // hasSideEffects = 0 +} // Constraints = "$src = $dst", SchedRW + + +let SchedRW = [WriteShiftLd, WriteRMW] in { +// FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern +// using CL? +let Uses = [CL] in { +def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), + "shl{b}\t{%cl, $dst|$dst, cl}", + [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>; +def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), + "shl{w}\t{%cl, $dst|$dst, cl}", + [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, + OpSize16; +def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), + "shl{l}\t{%cl, $dst|$dst, cl}", + [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>, + OpSize32; +def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst), + "shl{q}\t{%cl, $dst|$dst, cl}", + [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>, + Requires<[In64BitMode]>; +def SAL8mCL : I<0xD2, MRM6m, (outs), (ins i8mem :$dst), + "sal{b}\t{%cl, $dst|$dst, cl}", + []>; +def SAL16mCL : I<0xD3, MRM6m, (outs), (ins i16mem:$dst), + "sal{w}\t{%cl, $dst|$dst, cl}", + []>, + OpSize16; +def SAL32mCL : I<0xD3, MRM6m, (outs), (ins i32mem:$dst), + "sal{l}\t{%cl, $dst|$dst, cl}", + []>, + OpSize32; +def SAL64mCL : RI<0xD3, MRM6m, (outs), (ins i64mem:$dst), + "sal{q}\t{%cl, $dst|$dst, cl}", + []>; +} +def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, u8imm:$src), + "shl{b}\t{$src, $dst|$dst, $src}", + [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; +def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, u8imm:$src), + "shl{w}\t{$src, $dst|$dst, $src}", + [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize16; +def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, u8imm:$src), + "shl{l}\t{$src, $dst|$dst, $src}", + [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize32; +def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, u8imm:$src), + "shl{q}\t{$src, $dst|$dst, $src}", + [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + Requires<[In64BitMode]>; +def SAL8mi : Ii8<0xC0, MRM6m, (outs), (ins i8mem :$dst, i8imm:$src), + "sal{b}\t{$src, $dst|$dst, $src}", + []>; +def SAL16mi : Ii8<0xC1, MRM6m, (outs), (ins i16mem:$dst, i8imm:$src), + "sal{w}\t{$src, $dst|$dst, $src}", + []>, OpSize16; +def SAL32mi : Ii8<0xC1, MRM6m, (outs), (ins i32mem:$dst, i8imm:$src), + "sal{l}\t{$src, $dst|$dst, $src}", + []>, OpSize32; +def SAL64mi : RIi8<0xC1, MRM6m, (outs), (ins i64mem:$dst, i8imm:$src), + "sal{q}\t{$src, $dst|$dst, $src}", + []>; + +// Shift by 1 +def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst), + "shl{b}\t{$dst|$dst, 1}", + [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; +def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), + "shl{w}\t{$dst|$dst, 1}", + [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize16; +def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), + "shl{l}\t{$dst|$dst, 1}", + [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize32; +def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst), + "shl{q}\t{$dst|$dst, 1}", + [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>, + Requires<[In64BitMode]>; +def SAL8m1 : I<0xD0, MRM6m, (outs), (ins i8mem :$dst), + "sal{b}\t{$dst|$dst, 1}", + []>; +def SAL16m1 : I<0xD1, MRM6m, (outs), (ins i16mem:$dst), + "sal{w}\t{$dst|$dst, 1}", + []>, OpSize16; +def SAL32m1 : I<0xD1, MRM6m, (outs), (ins i32mem:$dst), + "sal{l}\t{$dst|$dst, 1}", + []>, OpSize32; +def SAL64m1 : RI<0xD1, MRM6m, (outs), (ins i64mem:$dst), + "sal{q}\t{$dst|$dst, 1}", + []>; +} // SchedRW + +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { +let Uses = [CL] in { +def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1), + "shr{b}\t{%cl, $dst|$dst, cl}", + [(set GR8:$dst, (srl GR8:$src1, CL))]>; +def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1), + "shr{w}\t{%cl, $dst|$dst, cl}", + [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize16; +def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1), + "shr{l}\t{%cl, $dst|$dst, cl}", + [(set GR32:$dst, (srl GR32:$src1, CL))]>, OpSize32; +def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1), + "shr{q}\t{%cl, $dst|$dst, cl}", + [(set GR64:$dst, (srl GR64:$src1, CL))]>; +} + +def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2), + "shr{b}\t{$src2, $dst|$dst, $src2}", + [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>; +def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), + "shr{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, + OpSize16; +def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), + "shr{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>, + OpSize32; +def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2), + "shr{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>; + +// Shift right by 1 +def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), + "shr{b}\t{$$1, $dst|$dst, 1}", + [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>; +def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), + "shr{w}\t{$$1, $dst|$dst, 1}", + [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize16; +def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), + "shr{l}\t{$$1, $dst|$dst, 1}", + [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>, OpSize32; +def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1), + "shr{q}\t{$$1, $dst|$dst, 1}", + [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>; +} // Constraints = "$src = $dst", SchedRW + + +let SchedRW = [WriteShiftLd, WriteRMW] in { +let Uses = [CL] in { +def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), + "shr{b}\t{%cl, $dst|$dst, cl}", + [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>; +def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), + "shr{w}\t{%cl, $dst|$dst, cl}", + [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, + OpSize16; +def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), + "shr{l}\t{%cl, $dst|$dst, cl}", + [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>, + OpSize32; +def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst), + "shr{q}\t{%cl, $dst|$dst, cl}", + [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>, + Requires<[In64BitMode]>; +} +def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, u8imm:$src), + "shr{b}\t{$src, $dst|$dst, $src}", + [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; +def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, u8imm:$src), + "shr{w}\t{$src, $dst|$dst, $src}", + [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize16; +def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, u8imm:$src), + "shr{l}\t{$src, $dst|$dst, $src}", + [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize32; +def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, u8imm:$src), + "shr{q}\t{$src, $dst|$dst, $src}", + [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + Requires<[In64BitMode]>; + +// Shift by 1 +def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst), + "shr{b}\t{$dst|$dst, 1}", + [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; +def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), + "shr{w}\t{$dst|$dst, 1}", + [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize16; +def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), + "shr{l}\t{$dst|$dst, 1}", + [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize32; +def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst), + "shr{q}\t{$dst|$dst, 1}", + [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW + +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { +let Uses = [CL] in { +def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), + "sar{b}\t{%cl, $dst|$dst, cl}", + [(set GR8:$dst, (sra GR8:$src1, CL))]>; +def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1), + "sar{w}\t{%cl, $dst|$dst, cl}", + [(set GR16:$dst, (sra GR16:$src1, CL))]>, + OpSize16; +def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1), + "sar{l}\t{%cl, $dst|$dst, cl}", + [(set GR32:$dst, (sra GR32:$src1, CL))]>, + OpSize32; +def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1), + "sar{q}\t{%cl, $dst|$dst, cl}", + [(set GR64:$dst, (sra GR64:$src1, CL))]>; +} + +def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), + "sar{b}\t{$src2, $dst|$dst, $src2}", + [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>; +def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), + "sar{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>, + OpSize16; +def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), + "sar{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>, + OpSize32; +def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), + (ins GR64:$src1, u8imm:$src2), + "sar{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>; + +// Shift by 1 +def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), + "sar{b}\t{$$1, $dst|$dst, 1}", + [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>; +def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), + "sar{w}\t{$$1, $dst|$dst, 1}", + [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize16; +def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), + "sar{l}\t{$$1, $dst|$dst, 1}", + [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>, OpSize32; +def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1), + "sar{q}\t{$$1, $dst|$dst, 1}", + [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>; +} // Constraints = "$src = $dst", SchedRW + + +let SchedRW = [WriteShiftLd, WriteRMW] in { +let Uses = [CL] in { +def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), + "sar{b}\t{%cl, $dst|$dst, cl}", + [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>; +def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), + "sar{w}\t{%cl, $dst|$dst, cl}", + [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, + OpSize16; +def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), + "sar{l}\t{%cl, $dst|$dst, cl}", + [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>, + OpSize32; +def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst), + "sar{q}\t{%cl, $dst|$dst, cl}", + [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>, + Requires<[In64BitMode]>; +} +def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, u8imm:$src), + "sar{b}\t{$src, $dst|$dst, $src}", + [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; +def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, u8imm:$src), + "sar{w}\t{$src, $dst|$dst, $src}", + [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize16; +def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, u8imm:$src), + "sar{l}\t{$src, $dst|$dst, $src}", + [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize32; +def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, u8imm:$src), + "sar{q}\t{$src, $dst|$dst, $src}", + [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + Requires<[In64BitMode]>; + +// Shift by 1 +def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst), + "sar{b}\t{$dst|$dst, 1}", + [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; +def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), + "sar{w}\t{$dst|$dst, 1}", + [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize16; +def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), + "sar{l}\t{$dst|$dst, 1}", + [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize32; +def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst), + "sar{q}\t{$dst|$dst, 1}", + [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Rotate instructions +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0 in { +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { + +let Uses = [CL, EFLAGS] in { +def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1), + "rcl{b}\t{%cl, $dst|$dst, cl}", []>; +def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1), + "rcl{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16; +def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1), + "rcl{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32; +def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1), + "rcl{q}\t{%cl, $dst|$dst, cl}", []>; +} // Uses = [CL, EFLAGS] + +let Uses = [EFLAGS] in { +def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1), + "rcl{b}\t{$$1, $dst|$dst, 1}", []>; +def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt), + "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; +def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1), + "rcl{w}\t{$$1, $dst|$dst, 1}", []>, OpSize16; +def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt), + "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16; +def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1), + "rcl{l}\t{$$1, $dst|$dst, 1}", []>, OpSize32; +def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt), + "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32; +def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1), + "rcl{q}\t{$$1, $dst|$dst, 1}", []>; +def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt), + "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>; +} // Uses = [EFLAGS] + +let Uses = [CL, EFLAGS] in { +def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1), + "rcr{b}\t{%cl, $dst|$dst, cl}", []>; +def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1), + "rcr{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16; +def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1), + "rcr{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32; +def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1), + "rcr{q}\t{%cl, $dst|$dst, cl}", []>; +} // Uses = [CL, EFLAGS] + +let Uses = [EFLAGS] in { +def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1), + "rcr{b}\t{$$1, $dst|$dst, 1}", []>; +def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt), + "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; +def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1), + "rcr{w}\t{$$1, $dst|$dst, 1}", []>, OpSize16; +def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt), + "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16; +def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1), + "rcr{l}\t{$$1, $dst|$dst, 1}", []>, OpSize32; +def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt), + "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32; +def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1), + "rcr{q}\t{$$1, $dst|$dst, 1}", []>; +def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt), + "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>; +} // Uses = [EFLAGS] + +} // Constraints = "$src = $dst" + +let SchedRW = [WriteShiftLd, WriteRMW], mayStore = 1 in { +let Uses = [EFLAGS] in { +def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst), + "rcl{b}\t$dst", []>; +def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, u8imm:$cnt), + "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; +def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst), + "rcl{w}\t$dst", []>, OpSize16; +def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, u8imm:$cnt), + "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16; +def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst), + "rcl{l}\t$dst", []>, OpSize32; +def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, u8imm:$cnt), + "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32; +def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst), + "rcl{q}\t$dst", []>, Requires<[In64BitMode]>; +def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, u8imm:$cnt), + "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>, + Requires<[In64BitMode]>; + +def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst), + "rcr{b}\t$dst", []>; +def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, u8imm:$cnt), + "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; +def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst), + "rcr{w}\t$dst", []>, OpSize16; +def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, u8imm:$cnt), + "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16; +def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst), + "rcr{l}\t$dst", []>, OpSize32; +def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, u8imm:$cnt), + "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32; +def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst), + "rcr{q}\t$dst", []>, Requires<[In64BitMode]>; +def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, u8imm:$cnt), + "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>, + Requires<[In64BitMode]>; +} // Uses = [EFLAGS] + +let Uses = [CL, EFLAGS] in { +def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst), + "rcl{b}\t{%cl, $dst|$dst, cl}", []>; +def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst), + "rcl{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16; +def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst), + "rcl{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32; +def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst), + "rcl{q}\t{%cl, $dst|$dst, cl}", []>, + Requires<[In64BitMode]>; + +def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst), + "rcr{b}\t{%cl, $dst|$dst, cl}", []>; +def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst), + "rcr{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16; +def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst), + "rcr{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32; +def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst), + "rcr{q}\t{%cl, $dst|$dst, cl}", []>, + Requires<[In64BitMode]>; +} // Uses = [CL, EFLAGS] +} // SchedRW +} // hasSideEffects = 0 + +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { +// FIXME: provide shorter instructions when imm8 == 1 +let Uses = [CL] in { +def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), + "rol{b}\t{%cl, $dst|$dst, cl}", + [(set GR8:$dst, (rotl GR8:$src1, CL))]>; +def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1), + "rol{w}\t{%cl, $dst|$dst, cl}", + [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize16; +def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1), + "rol{l}\t{%cl, $dst|$dst, cl}", + [(set GR32:$dst, (rotl GR32:$src1, CL))]>, OpSize32; +def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1), + "rol{q}\t{%cl, $dst|$dst, cl}", + [(set GR64:$dst, (rotl GR64:$src1, CL))]>; +} + +def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), + "rol{b}\t{$src2, $dst|$dst, $src2}", + [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; +def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), + "rol{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize16; +def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), + "rol{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>, OpSize32; +def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), + (ins GR64:$src1, u8imm:$src2), + "rol{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>; + +// Rotate by 1 +def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), + "rol{b}\t{$$1, $dst|$dst, 1}", + [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>; +def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), + "rol{w}\t{$$1, $dst|$dst, 1}", + [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize16; +def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), + "rol{l}\t{$$1, $dst|$dst, 1}", + [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>, OpSize32; +def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1), + "rol{q}\t{$$1, $dst|$dst, 1}", + [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>; +} // Constraints = "$src = $dst", SchedRW + +let SchedRW = [WriteShiftLd, WriteRMW] in { +let Uses = [CL] in { +def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), + "rol{b}\t{%cl, $dst|$dst, cl}", + [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>; +def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), + "rol{w}\t{%cl, $dst|$dst, cl}", + [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize16; +def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), + "rol{l}\t{%cl, $dst|$dst, cl}", + [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>, OpSize32; +def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst), + "rol{q}\t{%cl, $dst|$dst, cl}", + [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>, + Requires<[In64BitMode]>; +} +def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, u8imm:$src1), + "rol{b}\t{$src1, $dst|$dst, $src1}", + [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)]>; +def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, u8imm:$src1), + "rol{w}\t{$src1, $dst|$dst, $src1}", + [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)]>, + OpSize16; +def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, u8imm:$src1), + "rol{l}\t{$src1, $dst|$dst, $src1}", + [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)]>, + OpSize32; +def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, u8imm:$src1), + "rol{q}\t{$src1, $dst|$dst, $src1}", + [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)]>, + Requires<[In64BitMode]>; + +// Rotate by 1 +def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst), + "rol{b}\t{$dst|$dst, 1}", + [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; +def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), + "rol{w}\t{$dst|$dst, 1}", + [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize16; +def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), + "rol{l}\t{$dst|$dst, 1}", + [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>, + OpSize32; +def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst), + "rol{q}\t{$dst|$dst, 1}", + [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW + +let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { +let Uses = [CL] in { +def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), + "ror{b}\t{%cl, $dst|$dst, cl}", + [(set GR8:$dst, (rotr GR8:$src1, CL))]>; +def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1), + "ror{w}\t{%cl, $dst|$dst, cl}", + [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize16; +def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1), + "ror{l}\t{%cl, $dst|$dst, cl}", + [(set GR32:$dst, (rotr GR32:$src1, CL))]>, OpSize32; +def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), + "ror{q}\t{%cl, $dst|$dst, cl}", + [(set GR64:$dst, (rotr GR64:$src1, CL))]>; +} + +def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), + "ror{b}\t{$src2, $dst|$dst, $src2}", + [(set GR8:$dst, (rotr GR8:$src1, (i8 relocImm:$src2)))]>; +def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), + "ror{w}\t{$src2, $dst|$dst, $src2}", + [(set GR16:$dst, (rotr GR16:$src1, (i8 relocImm:$src2)))]>, + OpSize16; +def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), + "ror{l}\t{$src2, $dst|$dst, $src2}", + [(set GR32:$dst, (rotr GR32:$src1, (i8 relocImm:$src2)))]>, + OpSize32; +def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), + (ins GR64:$src1, u8imm:$src2), + "ror{q}\t{$src2, $dst|$dst, $src2}", + [(set GR64:$dst, (rotr GR64:$src1, (i8 relocImm:$src2)))]>; + +// Rotate by 1 +def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), + "ror{b}\t{$$1, $dst|$dst, 1}", + [(set GR8:$dst, (rotl GR8:$src1, (i8 7)))]>; +def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), + "ror{w}\t{$$1, $dst|$dst, 1}", + [(set GR16:$dst, (rotl GR16:$src1, (i8 15)))]>, OpSize16; +def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), + "ror{l}\t{$$1, $dst|$dst, 1}", + [(set GR32:$dst, (rotl GR32:$src1, (i8 31)))]>, OpSize32; +def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1), + "ror{q}\t{$$1, $dst|$dst, 1}", + [(set GR64:$dst, (rotl GR64:$src1, (i8 63)))]>; +} // Constraints = "$src = $dst", SchedRW + +let SchedRW = [WriteShiftLd, WriteRMW] in { +let Uses = [CL] in { +def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), + "ror{b}\t{%cl, $dst|$dst, cl}", + [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>; +def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), + "ror{w}\t{%cl, $dst|$dst, cl}", + [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize16; +def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), + "ror{l}\t{%cl, $dst|$dst, cl}", + [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>, OpSize32; +def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst), + "ror{q}\t{%cl, $dst|$dst, cl}", + [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>, + Requires<[In64BitMode]>; +} +def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, u8imm:$src), + "ror{b}\t{$src, $dst|$dst, $src}", + [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; +def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, u8imm:$src), + "ror{w}\t{$src, $dst|$dst, $src}", + [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize16; +def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, u8imm:$src), + "ror{l}\t{$src, $dst|$dst, $src}", + [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + OpSize32; +def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, u8imm:$src), + "ror{q}\t{$src, $dst|$dst, $src}", + [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>, + Requires<[In64BitMode]>; + +// Rotate by 1 +def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), + "ror{b}\t{$dst|$dst, 1}", + [(store (rotl (loadi8 addr:$dst), (i8 7)), addr:$dst)]>; +def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), + "ror{w}\t{$dst|$dst, 1}", + [(store (rotl (loadi16 addr:$dst), (i8 15)), addr:$dst)]>, + OpSize16; +def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), + "ror{l}\t{$dst|$dst, 1}", + [(store (rotl (loadi32 addr:$dst), (i8 31)), addr:$dst)]>, + OpSize32; +def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst), + "ror{q}\t{$dst|$dst, 1}", + [(store (rotl (loadi64 addr:$dst), (i8 63)), addr:$dst)]>, + Requires<[In64BitMode]>; +} // SchedRW + + +//===----------------------------------------------------------------------===// +// Double shift instructions (generalizations of rotate) +//===----------------------------------------------------------------------===// + +let Constraints = "$src1 = $dst" in { + +let Uses = [CL], SchedRW = [WriteSHDrrcl] in { +def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), + (ins GR16:$src1, GR16:$src2), + "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>, + TB, OpSize16; +def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), + (ins GR16:$src1, GR16:$src2), + "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>, + TB, OpSize16; +def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2), + "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, + TB, OpSize32; +def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2), + "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, + TB, OpSize32; +def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), + "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, + TB; +def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), + "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, + TB; +} // SchedRW + +let isCommutable = 1, SchedRW = [WriteSHDrri] in { // These instructions commute to each other. +def SHLD16rri8 : Ii8<0xA4, MRMDestReg, + (outs GR16:$dst), + (ins GR16:$src1, GR16:$src2, u8imm:$src3), + "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, + (i8 imm:$src3)))]>, + TB, OpSize16; +def SHRD16rri8 : Ii8<0xAC, MRMDestReg, + (outs GR16:$dst), + (ins GR16:$src1, GR16:$src2, u8imm:$src3), + "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, + (i8 imm:$src3)))]>, + TB, OpSize16; +def SHLD32rri8 : Ii8<0xA4, MRMDestReg, + (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2, u8imm:$src3), + "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, + (i8 imm:$src3)))]>, + TB, OpSize32; +def SHRD32rri8 : Ii8<0xAC, MRMDestReg, + (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2, u8imm:$src3), + "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, + (i8 imm:$src3)))]>, + TB, OpSize32; +def SHLD64rri8 : RIi8<0xA4, MRMDestReg, + (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2, u8imm:$src3), + "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, + (i8 imm:$src3)))]>, + TB; +def SHRD64rri8 : RIi8<0xAC, MRMDestReg, + (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2, u8imm:$src3), + "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, + (i8 imm:$src3)))]>, + TB; +} // SchedRW +} // Constraints = "$src = $dst" + +let Uses = [CL], SchedRW = [WriteSHDmrcl] in { +def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), + "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), + addr:$dst)]>, TB, OpSize16; +def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), + "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), + addr:$dst)]>, TB, OpSize16; + +def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), + "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), + addr:$dst)]>, TB, OpSize32; +def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), + "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), + addr:$dst)]>, TB, OpSize32; + +def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), + "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL), + addr:$dst)]>, TB; +def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), + "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", + [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL), + addr:$dst)]>, TB; +} // SchedRW + +let SchedRW = [WriteSHDmri] in { +def SHLD16mri8 : Ii8<0xA4, MRMDestMem, + (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3), + "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(store (X86shld (loadi16 addr:$dst), GR16:$src2, + (i8 imm:$src3)), addr:$dst)]>, + TB, OpSize16; +def SHRD16mri8 : Ii8<0xAC, MRMDestMem, + (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3), + "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, + (i8 imm:$src3)), addr:$dst)]>, + TB, OpSize16; + +def SHLD32mri8 : Ii8<0xA4, MRMDestMem, + (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3), + "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(store (X86shld (loadi32 addr:$dst), GR32:$src2, + (i8 imm:$src3)), addr:$dst)]>, + TB, OpSize32; +def SHRD32mri8 : Ii8<0xAC, MRMDestMem, + (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3), + "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, + (i8 imm:$src3)), addr:$dst)]>, + TB, OpSize32; + +def SHLD64mri8 : RIi8<0xA4, MRMDestMem, + (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3), + "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(store (X86shld (loadi64 addr:$dst), GR64:$src2, + (i8 imm:$src3)), addr:$dst)]>, + TB; +def SHRD64mri8 : RIi8<0xAC, MRMDestMem, + (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3), + "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, + (i8 imm:$src3)), addr:$dst)]>, + TB; +} // SchedRW + +} // Defs = [EFLAGS] + +// Sandy Bridge and newer Intel processors support faster rotates using +// SHLD to avoid a partial flag update on the normal rotate instructions. +let Predicates = [HasFastSHLDRotate], AddedComplexity = 5 in { + def : Pat<(rotl GR32:$src, (i8 imm:$shamt)), + (SHLD32rri8 GR32:$src, GR32:$src, imm:$shamt)>; + def : Pat<(rotl GR64:$src, (i8 imm:$shamt)), + (SHLD64rri8 GR64:$src, GR64:$src, imm:$shamt)>; +} + +def ROT32L2R_imm8 : SDNodeXFormgetZExtValue(), SDLoc(N)); +}]>; + +def ROT64L2R_imm8 : SDNodeXFormgetZExtValue(), SDLoc(N)); +}]>; + +multiclass bmi_rotate { +let hasSideEffects = 0 in { + def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + []>, TAXD, VEX, Sched<[WriteShift]>; + let mayLoad = 1 in + def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst), + (ins x86memop:$src1, u8imm:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + []>, TAXD, VEX, Sched<[WriteShiftLd]>; +} +} + +multiclass bmi_shift { +let hasSideEffects = 0 in { + def rr : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, + VEX, Sched<[WriteShift]>; + let mayLoad = 1 in + def rm : I<0xF7, MRMSrcMem4VOp3, + (outs RC:$dst), (ins x86memop:$src1, RC:$src2), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, + VEX, Sched<[WriteShiftLd, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + ReadAfterLd]>; +} +} + +let Predicates = [HasBMI2] in { + defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>; + defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W; + defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS; + defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W; + defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD; + defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W; + defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD; + defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, VEX_W; + + // Prefer RORX which is non-destructive and doesn't update EFLAGS. + let AddedComplexity = 10 in { + def : Pat<(rotl GR32:$src, (i8 imm:$shamt)), + (RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>; + def : Pat<(rotl GR64:$src, (i8 imm:$shamt)), + (RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>; + } + + def : Pat<(rotl (loadi32 addr:$src), (i8 imm:$shamt)), + (RORX32mi addr:$src, (ROT32L2R_imm8 imm:$shamt))>; + def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)), + (RORX64mi addr:$src, (ROT64L2R_imm8 imm:$shamt))>; + + // Prefer SARX/SHRX/SHLX over SAR/SHR/SHL with variable shift BUT not + // immedidate shift, i.e. the following code is considered better + // + // mov %edi, %esi + // shl $imm, %esi + // ... %edi, ... + // + // than + // + // movb $imm, %sil + // shlx %sil, %edi, %esi + // ... %edi, ... + // + let AddedComplexity = 1 in { + def : Pat<(sra GR32:$src1, GR8:$src2), + (SARX32rr GR32:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(sra GR64:$src1, GR8:$src2), + (SARX64rr GR64:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(srl GR32:$src1, GR8:$src2), + (SHRX32rr GR32:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(srl GR64:$src1, GR8:$src2), + (SHRX64rr GR64:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(shl GR32:$src1, GR8:$src2), + (SHLX32rr GR32:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(shl GR64:$src1, GR8:$src2), + (SHLX64rr GR64:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + } + + // We prefer to use + // mov (%ecx), %esi + // shl $imm, $esi + // + // over + // + // movb $imm, %al + // shlx %al, (%ecx), %esi + // + // This priority is enforced by IsProfitableToFoldLoad. + def : Pat<(sra (loadi32 addr:$src1), GR8:$src2), + (SARX32rm addr:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(sra (loadi64 addr:$src1), GR8:$src2), + (SARX64rm addr:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(srl (loadi32 addr:$src1), GR8:$src2), + (SHRX32rm addr:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(srl (loadi64 addr:$src1), GR8:$src2), + (SHRX64rm addr:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + + def : Pat<(shl (loadi32 addr:$src1), GR8:$src2), + (SHLX32rm addr:$src1, + (INSERT_SUBREG + (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(shl (loadi64 addr:$src1), GR8:$src2), + (SHLX64rm addr:$src1, + (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrSystem.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrSystem.td new file mode 100644 index 0000000..c0d51aa --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrSystem.td @@ -0,0 +1,743 @@ +//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 instructions that are generally used in +// privileged modes. These are not typically used by the compiler, but are +// supported for the assembler and disassembler. +// +//===----------------------------------------------------------------------===// + +let SchedRW = [WriteSystem] in { +let Defs = [RAX, RDX] in + def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB; + +let Defs = [RAX, RCX, RDX] in + def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB; + +// CPU flow control instructions + +let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in { + def UD2 : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; + def UD1 : I<0xB9, RawFrm, (outs), (ins), "ud1", []>, TB; + def UD0 : I<0xFF, RawFrm, (outs), (ins), "ud0", []>, TB; +} + +def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>; +def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB; + +// Interrupt and SysCall Instructions. +let Uses = [EFLAGS] in + def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>; + +def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>; +} // SchedRW + +// The long form of "int $3" turns into int3 as a size optimization. +// FIXME: This doesn't work because InstAlias can't match immediate constants. +//def : InstAlias<"int\t$3", (INT3)>; + +let SchedRW = [WriteSystem] in { + +def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap", + [(int_x86_int imm:$trap)]>; + + +def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB; +def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB; +def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB, + Requires<[In64BitMode]>; + +def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB; + +def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB; +def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB, + Requires<[In64BitMode]>; +} // SchedRW + +def : Pat<(debugtrap), + (INT3)>, Requires<[NotPS4]>; +def : Pat<(debugtrap), + (INT (i8 0x41))>, Requires<[IsPS4]>; + +//===----------------------------------------------------------------------===// +// Input/Output Instructions. +// +let SchedRW = [WriteSystem] in { +let Defs = [AL], Uses = [DX] in +def IN8rr : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>; +let Defs = [AX], Uses = [DX] in +def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>, + OpSize16; +let Defs = [EAX], Uses = [DX] in +def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>, + OpSize32; + +let Defs = [AL] in +def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port), + "in{b}\t{$port, %al|al, $port}", []>; +let Defs = [AX] in +def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port), + "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16; +let Defs = [EAX] in +def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port), + "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32; + +let Uses = [DX, AL] in +def OUT8rr : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>; +let Uses = [DX, AX] in +def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>, + OpSize16; +let Uses = [DX, EAX] in +def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>, + OpSize32; + +let Uses = [AL] in +def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port), + "out{b}\t{%al, $port|$port, al}", []>; +let Uses = [AX] in +def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port), + "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16; +let Uses = [EAX] in +def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port), + "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32; + +} // SchedRW + +//===----------------------------------------------------------------------===// +// Moves to and from debug registers + +let SchedRW = [WriteSystem] in { +def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[Not64BitMode]>; +def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[In64BitMode]>; + +def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[Not64BitMode]>; +def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Moves to and from control registers + +let SchedRW = [WriteSystem] in { +def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[Not64BitMode]>; +def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[In64BitMode]>; + +def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[Not64BitMode]>; +def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, + Requires<[In64BitMode]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Segment override instruction prefixes + +//let SchedRW = [WriteNop] in { +//def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>; +//def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>; +//def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>; +//def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>; +//def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>; +//def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>; +//} // SchedRW + +//===----------------------------------------------------------------------===// +// Moves to and from segment registers. +// + +let SchedRW = [WriteMove] in { +def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; +def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; +def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>; +let mayStore = 1 in { +def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>; +} +def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; +def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src), + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; +def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src), + "mov{q}\t{$src, $dst|$dst, $src}", []>; +let mayLoad = 1 in { +def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src), + "mov{w}\t{$src, $dst|$dst, $src}", []>; +} +} // SchedRW + +//===----------------------------------------------------------------------===// +// Segmentation support instructions. + +let SchedRW = [WriteSystem] in { +def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB; + +let mayLoad = 1 in +def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize16, NotMemoryFoldable; +def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize16, NotMemoryFoldable; + +// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo. +let mayLoad = 1 in +def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), + "lar{l}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize32, NotMemoryFoldable; +def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "lar{l}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize32, NotMemoryFoldable; +// i16mem operand in LAR64rm and GR32 operand in LAR64rr is not a typo. +let mayLoad = 1 in +def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), + "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; +def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), + "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; + +// i16mem operand in LSL32rm and GR32 operand in LSL32rr is not a typo. +let mayLoad = 1 in +def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), + "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize16, NotMemoryFoldable; +def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), + "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize16, NotMemoryFoldable; +// i16mem operand in LSL64rm and GR32 operand in LSL64rr is not a typo. +let mayLoad = 1 in +def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), + "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize32, NotMemoryFoldable; +def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB, + OpSize32, NotMemoryFoldable; +let mayLoad = 1 in +def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), + "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; +def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), + "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; + +def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB; + +def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins), + "str{w}\t$dst", []>, TB, OpSize16; +def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins), + "str{l}\t$dst", []>, TB, OpSize32; +def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins), + "str{q}\t$dst", []>, TB; +let mayStore = 1 in +def STRm : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB; + +def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable; +let mayLoad = 1 in +def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable; + +def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>, + OpSize16, Requires<[Not64BitMode]>; +def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>, + OpSize32, Requires<[Not64BitMode]>; +def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>, + OpSize16, Requires<[Not64BitMode]>; +def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>, + OpSize32, Requires<[Not64BitMode]>; +def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>, + OpSize16, Requires<[Not64BitMode]>; +def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>, + OpSize32, Requires<[Not64BitMode]>; +def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>, + OpSize16, Requires<[Not64BitMode]>; +def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>, + OpSize32, Requires<[Not64BitMode]>; +def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>, + OpSize16, TB; +def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB, + OpSize32, Requires<[Not64BitMode]>; +def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>, + OpSize16, TB; +def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB, + OpSize32, Requires<[Not64BitMode]>; +def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB, + OpSize32, Requires<[In64BitMode]>; +def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB, + OpSize32, Requires<[In64BitMode]>; + +// No "pop cs" instruction. +def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>, + OpSize16, Requires<[Not64BitMode]>; +def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>, + OpSize32, Requires<[Not64BitMode]>; + +def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>, + OpSize16, Requires<[Not64BitMode]>; +def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>, + OpSize32, Requires<[Not64BitMode]>; + +def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>, + OpSize16, Requires<[Not64BitMode]>; +def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>, + OpSize32, Requires<[Not64BitMode]>; + +def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>, + OpSize16, TB; +def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB, + OpSize32, Requires<[Not64BitMode]>; +def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB, + OpSize32, Requires<[In64BitMode]>; + +def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>, + OpSize16, TB; +def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB, + OpSize32, Requires<[Not64BitMode]>; +def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB, + OpSize32, Requires<[In64BitMode]>; + +def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), + "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, + Requires<[Not64BitMode]>; +def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), + "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, + Requires<[Not64BitMode]>; + +def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), + "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; +def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), + "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; +def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), + "lss{q}\t{$src, $dst|$dst, $src}", []>, TB; + +def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), + "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, + Requires<[Not64BitMode]>; +def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), + "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, + Requires<[Not64BitMode]>; + +def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), + "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; +def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), + "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; +def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), + "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB; + +def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), + "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; +def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), + "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; + +def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), + "lgs\t{$src, $dst|$dst, $src}", []>, TB; + +def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable; +def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable; +let mayLoad = 1 in { +def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable; +def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable; +} +} // SchedRW + +//===----------------------------------------------------------------------===// +// Descriptor-table support instructions + +let SchedRW = [WriteSystem] in { +def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), + "sgdt{w}\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; +def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), + "sgdt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; +def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), + "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; +def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), + "sidt{w}\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; +def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), + "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; +def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), + "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; +def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins), + "sldt{w}\t$dst", []>, TB, OpSize16; +let mayStore = 1 in +def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst), + "sldt{w}\t$dst", []>, TB; +def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins), + "sldt{l}\t$dst", []>, OpSize32, TB; + +// LLDT is not interpreted specially in 64-bit mode because there is no sign +// extension. +def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins), + "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>; + +def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), + "lgdt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; +def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), + "lgdt{l}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; +def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), + "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>; +def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), + "lidt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; +def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), + "lidt{l}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; +def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), + "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>; +def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src), + "lldt{w}\t$src", []>, TB, NotMemoryFoldable; +let mayLoad = 1 in +def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src), + "lldt{w}\t$src", []>, TB, NotMemoryFoldable; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Specialized register support +let SchedRW = [WriteSystem] in { +let Uses = [EAX, ECX, EDX] in +def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB; +let Defs = [EAX, EDX], Uses = [ECX] in +def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB; + +let Defs = [RAX, RDX], Uses = [ECX] in + def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)]>, TB; + +def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins), + "smsw{w}\t$dst", []>, OpSize16, TB; +def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins), + "smsw{l}\t$dst", []>, OpSize32, TB; +// no m form encodable; use SMSW16m +def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins), + "smsw{q}\t$dst", []>, TB; + +// For memory operands, there is only a 16-bit form +def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst), + "smsw{w}\t$dst", []>, TB; + +def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src), + "lmsw{w}\t$src", []>, TB, NotMemoryFoldable; +let mayLoad = 1 in +def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src), + "lmsw{w}\t$src", []>, TB, NotMemoryFoldable; + +let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in + def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Cache instructions +let SchedRW = [WriteSystem] in { +def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB; +def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, TB; + +// wbnoinvd is like wbinvd, except without invalidation +// encoding: like wbinvd + an 0xF3 prefix +def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd", + [(int_x86_wbnoinvd)]>, XS, + Requires<[HasWBNOINVD]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// CET instructions +// Use with caution, availability is not predicated on features. +let SchedRW = [WriteSystem] in { + let Uses = [SSP] in { + let Defs = [SSP] in { + def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src", + [(int_x86_incsspd GR32:$src)]>, XS; + def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src", + [(int_x86_incsspq GR64:$src)]>, XS; + } // Defs SSP + + let Constraints = "$src = $dst" in { + def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src), + "rdsspd\t$dst", + [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS; + def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src), + "rdsspq\t$dst", + [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS; + } + + let Defs = [SSP] in { + def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp", + [(int_x86_saveprevssp)]>, XS; + def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src), + "rstorssp\t$src", + [(int_x86_rstorssp addr:$src)]>, XS; + } // Defs SSP + } // Uses SSP + + def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "wrssd\t{$src, $dst|$dst, $src}", + [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS; + def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "wrssq\t{$src, $dst|$dst, $src}", + [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS; + def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "wrussd\t{$src, $dst|$dst, $src}", + [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD; + def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "wrussq\t{$src, $dst|$dst, $src}", + [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD; + + let Defs = [SSP] in { + let Uses = [SSP] in { + def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy", + [(int_x86_setssbsy)]>, XS; + } // Uses SSP + + def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src), + "clrssbsy\t$src", + [(int_x86_clrssbsy addr:$src)]>, XS; + } // Defs SSP +} // SchedRW + +let SchedRW = [WriteSystem] in { + def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS; + def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS; +} // SchedRW + +//===----------------------------------------------------------------------===// +// XSAVE instructions +let SchedRW = [WriteSystem] in { +let Predicates = [HasXSAVE] in { +let Defs = [EDX, EAX], Uses = [ECX] in + def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB; + +let Uses = [EDX, EAX, ECX] in + def XSETBV : I<0x01, MRM_D1, (outs), (ins), + "xsetbv", + [(int_x86_xsetbv ECX, EDX, EAX)]>, TB; + +} // HasXSAVE + +let Uses = [EDX, EAX] in { +def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst), + "xsave\t$dst", + [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>; +def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst), + "xsave64\t$dst", + [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; +def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst), + "xrstor\t$dst", + [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>; +def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst), + "xrstor64\t$dst", + [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; +def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst), + "xsaveopt\t$dst", + [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>; +def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst), + "xsaveopt64\t$dst", + [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>; +def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst), + "xsavec\t$dst", + [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>; +def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst), + "xsavec64\t$dst", + [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>; +def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst), + "xsaves\t$dst", + [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>; +def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst), + "xsaves64\t$dst", + [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>; +def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst), + "xrstors\t$dst", + [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>; +def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst), + "xrstors64\t$dst", + [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>; +} // Uses +} // SchedRW + +//===----------------------------------------------------------------------===// +// VIA PadLock crypto instructions +let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in + def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB; + +def : InstAlias<"xstorerng", (XSTORE)>; + +let SchedRW = [WriteSystem] in { +let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in { + def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB; + def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB; + def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB; + def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB; + def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB; +} + +let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in { + def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB; + def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB; +} +let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in + def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB; +} // SchedRW + +/* +//==-----------------------------------------------------------------------===// +// PKU - enable protection key +let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { + def WRPKRU : PseudoI<(outs), (ins GR32:$src), + [(int_x86_wrpkru GR32:$src)]>; + def RDPKRU : PseudoI<(outs GR32:$dst), (ins), + [(set GR32:$dst, (int_x86_rdpkru))]>; +} +*/ + +let SchedRW = [WriteSystem] in { +let Defs = [EAX, EDX], Uses = [ECX] in + def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", []>, TB; +let Uses = [EAX, ECX, EDX] in + def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", []>, TB; +} // SchedRW + +//===----------------------------------------------------------------------===// +// FS/GS Base Instructions +let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in { + def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins), + "rdfsbase{l}\t$dst", + [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS; + def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins), + "rdfsbase{q}\t$dst", + [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS; + def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), + "rdgsbase{l}\t$dst", + [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS; + def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins), + "rdgsbase{q}\t$dst", + [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS; + def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src), + "wrfsbase{l}\t$src", + [(int_x86_wrfsbase_32 GR32:$src)]>, XS; + def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src), + "wrfsbase{q}\t$src", + [(int_x86_wrfsbase_64 GR64:$src)]>, XS; + def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src), + "wrgsbase{l}\t$src", + [(int_x86_wrgsbase_32 GR32:$src)]>, XS; + def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src), + "wrgsbase{q}\t$src", + [(int_x86_wrgsbase_64 GR64:$src)]>, XS; +} + +//===----------------------------------------------------------------------===// +// INVPCID Instruction +let SchedRW = [WriteSystem] in { +def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), + "invpcid\t{$src2, $src1|$src1, $src2}", + [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8PD, + Requires<[Not64BitMode, HasINVPCID]>; +def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), + "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD, + Requires<[In64BitMode, HasINVPCID]>; +} // SchedRW + +let Predicates = [In64BitMode, HasINVPCID] in { + // The instruction can only use a 64 bit register as the register argument + // in 64 bit mode, while the intrinsic only accepts a 32 bit argument + // corresponding to it. + // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID + // type),/ so it doesn't hurt us that one can't supply a 64 bit value here. + def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2), + (INVPCID64 + (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit), + addr:$src2)>; +} + + +//===----------------------------------------------------------------------===// +// SMAP Instruction +let Defs = [EFLAGS], SchedRW = [WriteSystem] in { + def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB; + def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB; +} + +//===----------------------------------------------------------------------===// +// SMX Instruction +let SchedRW = [WriteSystem] in { +let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in { + def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB; +} // Uses, Defs +} // SchedRW + +//===----------------------------------------------------------------------===// +// TS flag control instruction. +let SchedRW = [WriteSystem] in { +def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB; +} + +//===----------------------------------------------------------------------===// +// IF (inside EFLAGS) management instructions. +let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in { +def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>; +def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>; +} + +//===----------------------------------------------------------------------===// +// RDPID Instruction +let SchedRW = [WriteSystem] in { +def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins), + "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, XS, + Requires<[Not64BitMode, HasRDPID]>; +def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS, + Requires<[In64BitMode, HasRDPID]>; +} // SchedRW + +let Predicates = [In64BitMode, HasRDPID] in { + // Due to silly instruction definition, we have to compensate for the + // instruction outputting a 64-bit register. + def : Pat<(int_x86_rdpid), + (EXTRACT_SUBREG (RDPID64), sub_32bit)>; +} + + +//===----------------------------------------------------------------------===// +// PTWRITE Instruction - Write Data to a Processor Trace Packet +let SchedRW = [WriteSystem] in { +def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst), + "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS, + Requires<[HasPTWRITE]>; +def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst), + "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS, + Requires<[In64BitMode, HasPTWRITE]>; + +def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst), + "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS, + Requires<[HasPTWRITE]>; +def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst), + "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS, + Requires<[In64BitMode, HasPTWRITE]>; +} // SchedRW + +//===----------------------------------------------------------------------===// +// Platform Configuration instruction + +// From ISA docs: +// "This instruction is used to execute functions for configuring platform +// features. +// EAX: Leaf function to be invoked. +// RBX/RCX/RDX: Leaf-specific purpose." +// "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF, +// AF, OF, and SF are cleared. In case of failure, the failure reason is +// indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared." +// Thus all these mentioned registers are considered clobbered. + +let SchedRW = [WriteSystem] in { +let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in + def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB, + Requires<[HasPCONFIG]>; +} // SchedRW diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrTSX.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrTSX.td new file mode 100644 index 0000000..8b9f723 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrTSX.td @@ -0,0 +1,60 @@ +//===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the Intel TSX instruction +// set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// TSX instructions + +def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +let SchedRW = [WriteSystem] in { + +//let usesCustomInserter = 1 in +//def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins), +// "# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>, +// Requires<[HasRTM]>; + +let isBranch = 1, isTerminator = 1, Defs = [EAX] in { +def XBEGIN_2 : Ii16PCRel<0xc7, MRM_F8, (outs), (ins brtarget16:$dst), + "xbegin\t$dst", []>, OpSize16; +def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst), + "xbegin\t$dst", []>, OpSize32; +} + +// Pseudo instruction to fake the definition of EAX on the fallback code path. +//let isPseudo = 1, Defs = [EAX] in { +//def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>; +//} + +def XEND : I<0x01, MRM_D5, (outs), (ins), + "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>; + +let Defs = [EFLAGS] in +def XTEST : I<0x01, MRM_D6, (outs), (ins), + "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasRTM]>; + +def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm), + "xabort\t$imm", + [(int_x86_xabort imm:$imm)]>, Requires<[HasRTM]>; +} // SchedRW + +// HLE prefixes +let SchedRW = [WriteSystem] in { + +let isAsmParserOnly = 1 in { +def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>; +def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>; +} + +} // SchedRW diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrVMX.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrVMX.td new file mode 100644 index 0000000..06a438e --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrVMX.td @@ -0,0 +1,88 @@ +//===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the Intel VMX instruction +// set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// VMX instructions + +let SchedRW = [WriteSystem] in { +// 66 0F 38 80 +def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), + "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD, + Requires<[Not64BitMode]>; +def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), + "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD, + Requires<[In64BitMode]>; + +// 66 0F 38 81 +def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), + "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD, + Requires<[Not64BitMode]>; +def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), + "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD, + Requires<[In64BitMode]>; + +// 0F 01 C1 +def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB; +def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), + "vmclear\t$vmcs", []>, PD; + +// OF 01 D4 +def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB; + +// 0F 01 C2 +def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB; + +// 0F 01 C3 +def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB; +def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), + "vmptrld\t$vmcs", []>, PS; +def VMPTRSTm : I<0xC7, MRM7m, (outs), (ins i64mem:$vmcs), + "vmptrst\t$vmcs", []>, PS; +def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), + "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>, + NotMemoryFoldable; +def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), + "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>, + NotMemoryFoldable; + +let mayStore = 1 in { +def VMREAD64mr : I<0x78, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>, + NotMemoryFoldable; +def VMREAD32mr : I<0x78, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>, + NotMemoryFoldable; +} // mayStore + +def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>, + NotMemoryFoldable; +def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>, + NotMemoryFoldable; + +let mayLoad = 1 in { +def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>, + NotMemoryFoldable; +def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>, + NotMemoryFoldable; +} // mayLoad + +// 0F 01 C4 +def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB; +def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon), + "vmxon\t$vmxon", []>, XS; +} // SchedRW diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrVecCompiler.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrVecCompiler.td new file mode 100644 index 0000000..322bdb7 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrVecCompiler.td @@ -0,0 +1,511 @@ +//===- X86InstrVecCompiler.td - Vector Compiler Patterns ---*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the various vector pseudo instructions used by the +// compiler, as well as Pat patterns used during instruction selection. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// No op bitconverts +//===----------------------------------------------------------------------===// + +// Bitcasts between 128-bit vector types. Return the original type since +// no instruction is needed for the conversion +def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; +def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; +def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; +def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; +def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; +def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; +def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; +def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; +def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; +def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; +def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; +def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; +def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; +def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; +def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; +def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; +def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; +def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; +def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; +def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; +def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; +def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; +def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; +def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; +def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; +def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; +def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; +def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; +def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; +def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; + +// Bitcasts between 256-bit vector types. Return the original type since +// no instruction is needed for the conversion +def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>; +def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>; +def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>; +def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>; +def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>; +def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>; +def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>; +def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>; +def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>; +def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>; +def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>; +def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>; +def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>; +def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>; +def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>; +def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>; +def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>; +def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>; +def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>; +def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>; +def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>; +def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>; +def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>; +def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>; +def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>; +def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>; +def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>; +def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>; +def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>; +def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>; + +// Bitcasts between 512-bit vector types. Return the original type since +// no instruction is needed for the conversion. +def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>; +def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>; +def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>; +def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>; +def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>; +def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>; +def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>; +def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>; +def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>; +def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>; +def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>; +def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>; +def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>; +def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>; +def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>; +def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>; +def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>; +def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>; +def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>; +def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>; +def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>; +def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>; +def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>; +def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>; +def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>; +def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>; +def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>; +def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>; +def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>; +def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>; + + +//===----------------------------------------------------------------------===// +// Non-instruction patterns +//===----------------------------------------------------------------------===// + +// A vector extract of the first f32/f64 position is a subregister copy +def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))), + (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>; +def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))), + (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>; + +// Implicitly promote a 32-bit scalar to a vector. +def : Pat<(v4f32 (scalar_to_vector FR32:$src)), + (COPY_TO_REGCLASS FR32:$src, VR128)>; +// Implicitly promote a 64-bit scalar to a vector. +def : Pat<(v2f64 (scalar_to_vector FR64:$src)), + (COPY_TO_REGCLASS FR64:$src, VR128)>; + + +//===----------------------------------------------------------------------===// +// Subvector tricks +//===----------------------------------------------------------------------===// + +// Patterns for insert_subvector/extract_subvector to/from index=0 +multiclass subvector_subreg_lowering { + def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))), + (subVT (EXTRACT_SUBREG RC:$src, subIdx))>; + + def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))), + (VT (INSERT_SUBREG (IMPLICIT_DEF), subRC:$src, subIdx))>; +} + +// A 128-bit subvector extract from the first 256-bit vector position is a +// subregister copy that needs no instruction. Likewise, a 128-bit subvector +// insert to the first 256-bit vector position is a subregister copy that needs +// no instruction. +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; + +// A 128-bit subvector extract from the first 512-bit vector position is a +// subregister copy that needs no instruction. Likewise, a 128-bit subvector +// insert to the first 512-bit vector position is a subregister copy that needs +// no instruction. +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; + +// A 128-bit subvector extract from the first 512-bit vector position is a +// subregister copy that needs no instruction. Likewise, a 128-bit subvector +// insert to the first 512-bit vector position is a subregister copy that needs +// no instruction. +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; +defm : subvector_subreg_lowering; + + +multiclass subvector_store_lowering { + def : Pat<(alignedstore (DstTy (extract_subvector + (SrcTy RC:$src), (iPTR 0))), addr:$dst), + (!cast("VMOV"#AlignedStr#"mr") addr:$dst, + (DstTy (EXTRACT_SUBREG RC:$src, SubIdx)))>; + + def : Pat<(store (DstTy (extract_subvector + (SrcTy RC:$src), (iPTR 0))), addr:$dst), + (!cast("VMOV"#UnalignedStr#"mr") addr:$dst, + (DstTy (EXTRACT_SUBREG RC:$src, SubIdx)))>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm : subvector_store_lowering<"APD", "UPD", VR256X, v2f64, v4f64, sub_xmm>; + defm : subvector_store_lowering<"APS", "UPS", VR256X, v4f32, v8f32, sub_xmm>; + defm : subvector_store_lowering<"DQA", "DQU", VR256X, v2i64, v4i64, sub_xmm>; + defm : subvector_store_lowering<"DQA", "DQU", VR256X, v4i32, v8i32, sub_xmm>; + defm : subvector_store_lowering<"DQA", "DQU", VR256X, v8i16, v16i16, sub_xmm>; + defm : subvector_store_lowering<"DQA", "DQU", VR256X, v16i8, v32i8, sub_xmm>; +} + +let Predicates = [HasVLX] in { + // Special patterns for storing subvector extracts of lower 128-bits + // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr + defm : subvector_store_lowering<"APDZ128", "UPDZ128", VR256X, v2f64, v4f64, + sub_xmm>; + defm : subvector_store_lowering<"APSZ128", "UPSZ128", VR256X, v4f32, v8f32, + sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR256X, v2i64, + v4i64, sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR256X, v4i32, + v8i32, sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR256X, v8i16, + v16i16, sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR256X, v16i8, + v32i8, sub_xmm>; + + // Special patterns for storing subvector extracts of lower 128-bits of 512. + // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr + defm : subvector_store_lowering<"APDZ128", "UPDZ128", VR512, v2f64, v8f64, + sub_xmm>; + defm : subvector_store_lowering<"APSZ128", "UPSZ128", VR512, v4f32, v16f32, + sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR512, v2i64, + v8i64, sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR512, v4i32, + v16i32, sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR512, v8i16, + v32i16, sub_xmm>; + defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR512, v16i8, + v64i8, sub_xmm>; + + // Special patterns for storing subvector extracts of lower 256-bits of 512. + // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr + defm : subvector_store_lowering<"APDZ256", "UPDZ256", VR512, v4f64, v8f64, + sub_ymm>; + defm : subvector_store_lowering<"APSZ256", "UPSZ256", VR512, v8f32, v16f32, + sub_ymm>; + defm : subvector_store_lowering<"DQA64Z256", "DQU64Z256", VR512, v4i64, + v8i64, sub_ymm>; + defm : subvector_store_lowering<"DQA64Z256", "DQU64Z256", VR512, v8i32, + v16i32, sub_ymm>; + defm : subvector_store_lowering<"DQA64Z256", "DQU64Z256", VR512, v16i16, + v32i16, sub_ymm>; + defm : subvector_store_lowering<"DQA64Z256", "DQU64Z256", VR512, v32i8, + v64i8, sub_ymm>; +} + +// If we're inserting into an all zeros vector, just use a plain move which +// will zero the upper bits. A post-isel hook will take care of removing +// any moves that we can prove are unnecessary. +multiclass subvec_zero_lowering { + def : Pat<(DstTy (insert_subvector (bitconvert (ZeroTy immAllZerosV)), + (SrcTy RC:$src), (iPTR 0))), + (SUBREG_TO_REG (i64 0), + (SrcTy (!cast("VMOV"#MoveStr#"rr") RC:$src)), SubIdx)>; +} + +let Predicates = [HasAVX, NoVLX] in { + defm : subvec_zero_lowering<"APD", VR128, v4f64, v2f64, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"APS", VR128, v8f32, v4f32, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v4i64, v2i64, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v8i32, v4i32, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v16i16, v8i16, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v32i8, v16i8, v8i32, sub_xmm>; +} + +let Predicates = [HasVLX] in { + defm : subvec_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v4i64, v2i64, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i32, v4i32, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i16, v8i16, v8i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i8, v16i8, v8i32, sub_xmm>; + + defm : subvec_zero_lowering<"APDZ128", VR128X, v8f64, v2f64, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i32, v4i32, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i16, v8i16, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, v16i32, sub_xmm>; + + defm : subvec_zero_lowering<"APDZ256", VR256X, v8f64, v4f64, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQA64Z256", VR256X, v16i32, v8i32, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQA64Z256", VR256X, v32i16, v16i16, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, v16i32, sub_ymm>; +} + +let Predicates = [HasAVX512, NoVLX] in { + defm : subvec_zero_lowering<"APD", VR128, v8f64, v2f64, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"APS", VR128, v16f32, v4f32, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v8i64, v2i64, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v16i32, v4i32, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v32i16, v8i16, v16i32, sub_xmm>; + defm : subvec_zero_lowering<"DQA", VR128, v64i8, v16i8, v16i32, sub_xmm>; + + defm : subvec_zero_lowering<"APDY", VR256, v8f64, v4f64, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"APSY", VR256, v16f32, v8f32, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQAY", VR256, v8i64, v4i64, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQAY", VR256, v16i32, v8i32, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQAY", VR256, v32i16, v16i16, v16i32, sub_ymm>; + defm : subvec_zero_lowering<"DQAY", VR256, v64i8, v32i8, v16i32, sub_ymm>; +} + +class maskzeroupper : + PatLeaf<(vt RC:$src), [{ + return isMaskZeroExtended(N); + }]>; + +def maskzeroupperv1i1 : maskzeroupper; +def maskzeroupperv2i1 : maskzeroupper; +def maskzeroupperv4i1 : maskzeroupper; +def maskzeroupperv8i1 : maskzeroupper; +def maskzeroupperv16i1 : maskzeroupper; +def maskzeroupperv32i1 : maskzeroupper; + +// The patterns determine if we can depend on the upper bits of a mask register +// being zeroed by the previous operation so that we can skip explicit +// zeroing. +let Predicates = [HasBWI] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + maskzeroupperv1i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK1:$src, VK32)>; + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + maskzeroupperv8i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK8:$src, VK32)>; + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + maskzeroupperv16i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK16:$src, VK32)>; + + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + maskzeroupperv1i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK1:$src, VK64)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + maskzeroupperv8i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK8:$src, VK64)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + maskzeroupperv16i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK16:$src, VK64)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + maskzeroupperv32i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK32:$src, VK64)>; +} + +let Predicates = [HasAVX512] in { + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + maskzeroupperv1i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK1:$src, VK16)>; + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + maskzeroupperv8i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK8:$src, VK16)>; +} + +let Predicates = [HasDQI] in { + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + maskzeroupperv1i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK1:$src, VK8)>; +} + +let Predicates = [HasVLX, HasDQI] in { + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + maskzeroupperv2i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK2:$src, VK8)>; + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + maskzeroupperv4i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK4:$src, VK8)>; +} + +let Predicates = [HasVLX] in { + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + maskzeroupperv2i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK2:$src, VK16)>; + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + maskzeroupperv4i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK4:$src, VK16)>; +} + +let Predicates = [HasBWI, HasVLX] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + maskzeroupperv2i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK2:$src, VK32)>; + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + maskzeroupperv4i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK4:$src, VK32)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + maskzeroupperv2i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK2:$src, VK64)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + maskzeroupperv4i1:$src, (iPTR 0))), + (COPY_TO_REGCLASS VK4:$src, VK64)>; +} + +// If the bits are not zero we have to fall back to explicitly zeroing by +// using shifts. +let Predicates = [HasAVX512] in { + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + (v1i1 VK1:$mask), (iPTR 0))), + (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK1:$mask, VK16), + (i8 15)), (i8 15))>; + + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + (v2i1 VK2:$mask), (iPTR 0))), + (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK2:$mask, VK16), + (i8 14)), (i8 14))>; + + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + (v4i1 VK4:$mask), (iPTR 0))), + (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK4:$mask, VK16), + (i8 12)), (i8 12))>; +} + +let Predicates = [HasAVX512, NoDQI] in { + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK8:$mask, VK16), + (i8 8)), (i8 8))>; +} + +let Predicates = [HasDQI] in { + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK16)>; + + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + (v1i1 VK1:$mask), (iPTR 0))), + (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK1:$mask, VK8), + (i8 7)), (i8 7))>; + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + (v2i1 VK2:$mask), (iPTR 0))), + (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK2:$mask, VK8), + (i8 6)), (i8 6))>; + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + (v4i1 VK4:$mask), (iPTR 0))), + (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK4:$mask, VK8), + (i8 4)), (i8 4))>; +} + +let Predicates = [HasBWI] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v16i1 VK16:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK32)>; + + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v16i1 VK16:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK64)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v32i1 VK32:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVDkk VK32:$mask), VK64)>; +} + +let Predicates = [HasBWI, NoDQI] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK8:$mask, VK32), + (i8 24)), (i8 24))>; + + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK8:$mask, VK64), + (i8 56)), (i8 56))>; +} + +let Predicates = [HasBWI, HasDQI] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK32)>; + + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK64)>; +} + +let Predicates = [HasBWI, HasVLX] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v1i1 VK1:$mask), (iPTR 0))), + (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK1:$mask, VK32), + (i8 31)), (i8 31))>; + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v2i1 VK2:$mask), (iPTR 0))), + (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK2:$mask, VK32), + (i8 30)), (i8 30))>; + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v4i1 VK4:$mask), (iPTR 0))), + (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK4:$mask, VK32), + (i8 28)), (i8 28))>; + + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v1i1 VK1:$mask), (iPTR 0))), + (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK1:$mask, VK64), + (i8 63)), (i8 63))>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v2i1 VK2:$mask), (iPTR 0))), + (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK2:$mask, VK64), + (i8 62)), (i8 62))>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v4i1 VK4:$mask), (iPTR 0))), + (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK4:$mask, VK64), + (i8 60)), (i8 60))>; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrXOP.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrXOP.td new file mode 100644 index 0000000..ff3e3be --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86InstrXOP.td @@ -0,0 +1,446 @@ +//===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes XOP (eXtended OPerations) +// +//===----------------------------------------------------------------------===// + +multiclass xop2op opc, string OpcodeStr, Intrinsic Int, PatFrag memop> { + def rr : IXOP, XOP, Sched<[SchedWritePHAdd.XMM]>; + def rm : IXOP, XOP, + Sched<[SchedWritePHAdd.XMM.Folded, ReadAfterLd]>; +} + +let ExeDomain = SSEPackedInt in { + defm VPHSUBWD : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, loadv2i64>; + defm VPHSUBDQ : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, loadv2i64>; + defm VPHSUBBW : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, loadv2i64>; + defm VPHADDWQ : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, loadv2i64>; + defm VPHADDWD : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, loadv2i64>; + defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, loadv2i64>; + defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, loadv2i64>; + defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, loadv2i64>; + defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, loadv2i64>; + defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, loadv2i64>; + defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, loadv2i64>; + defm VPHADDDQ : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, loadv2i64>; + defm VPHADDBW : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, loadv2i64>; + defm VPHADDBQ : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, loadv2i64>; + defm VPHADDBD : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, loadv2i64>; +} + +// Scalar load 2 addr operand instructions +multiclass xop2opsld opc, string OpcodeStr, Intrinsic Int, + Operand memop, ComplexPattern mem_cpat, + X86FoldableSchedWrite sched> { + def rr : IXOP, XOP, Sched<[sched]>; + def rm : IXOP, XOP, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass xop2op128 opc, string OpcodeStr, Intrinsic Int, + PatFrag memop, X86FoldableSchedWrite sched> { + def rr : IXOP, XOP, Sched<[sched]>; + def rm : IXOP, XOP, + Sched<[sched.Folded, ReadAfterLd]>; +} + +multiclass xop2op256 opc, string OpcodeStr, Intrinsic Int, + PatFrag memop, X86FoldableSchedWrite sched> { + def Yrr : IXOP, XOP, VEX_L, Sched<[sched]>; + def Yrm : IXOP, XOP, VEX_L, + Sched<[sched.Folded, ReadAfterLd]>; +} + +let ExeDomain = SSEPackedSingle in { + defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss, + ssmem, sse_load_f32, SchedWriteFRnd.Scl>; + defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, loadv4f32, + SchedWriteFRnd.XMM>; + defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256, loadv8f32, + SchedWriteFRnd.YMM>; +} + +let ExeDomain = SSEPackedDouble in { + defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd, + sdmem, sse_load_f64, SchedWriteFRnd.Scl>; + defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, loadv2f64, + SchedWriteFRnd.XMM>; + defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256, loadv4f64, + SchedWriteFRnd.YMM>; +} + +multiclass xop3op opc, string OpcodeStr, SDNode OpNode, + ValueType vt128, X86FoldableSchedWrite sched> { + def rr : IXOP, + XOP, Sched<[sched]>; + def rm : IXOP, + XOP_4V, VEX_W, Sched<[sched.Folded, ReadAfterLd]>; + def mr : IXOP, + XOP, Sched<[sched.Folded, ReadAfterLd]>; + // For disassembler + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rr_REV : IXOP, + XOP_4V, VEX_W, Sched<[sched]>, FoldGenData; +} + +let ExeDomain = SSEPackedInt in { + defm VPROTB : xop3op<0x90, "vprotb", rotl, v16i8, SchedWriteVarVecShift.XMM>; + defm VPROTD : xop3op<0x92, "vprotd", rotl, v4i32, SchedWriteVarVecShift.XMM>; + defm VPROTQ : xop3op<0x93, "vprotq", rotl, v2i64, SchedWriteVarVecShift.XMM>; + defm VPROTW : xop3op<0x91, "vprotw", rotl, v8i16, SchedWriteVarVecShift.XMM>; + defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8, SchedWriteVarVecShift.XMM>; + defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32, SchedWriteVarVecShift.XMM>; + defm VPSHAQ : xop3op<0x9B, "vpshaq", X86vpsha, v2i64, SchedWriteVarVecShift.XMM>; + defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16, SchedWriteVarVecShift.XMM>; + defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8, SchedWriteVarVecShift.XMM>; + defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32, SchedWriteVarVecShift.XMM>; + defm VPSHLQ : xop3op<0x97, "vpshlq", X86vpshl, v2i64, SchedWriteVarVecShift.XMM>; + defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16, SchedWriteVarVecShift.XMM>; +} + +multiclass xop3opimm opc, string OpcodeStr, SDNode OpNode, + ValueType vt128, X86FoldableSchedWrite sched> { + def ri : IXOPi8, + XOP, Sched<[sched]>; + def mi : IXOPi8, + XOP, Sched<[sched.Folded, ReadAfterLd]>; +} + +let ExeDomain = SSEPackedInt in { + defm VPROTB : xop3opimm<0xC0, "vprotb", X86vrotli, v16i8, + SchedWriteVecShiftImm.XMM>; + defm VPROTD : xop3opimm<0xC2, "vprotd", X86vrotli, v4i32, + SchedWriteVecShiftImm.XMM>; + defm VPROTQ : xop3opimm<0xC3, "vprotq", X86vrotli, v2i64, + SchedWriteVecShiftImm.XMM>; + defm VPROTW : xop3opimm<0xC1, "vprotw", X86vrotli, v8i16, + SchedWriteVecShiftImm.XMM>; +} + +// Instruction where second source can be memory, but third must be register +multiclass xop4opm2 opc, string OpcodeStr, Intrinsic Int, + X86FoldableSchedWrite sched> { + let isCommutable = 1 in + def rr : IXOPi8Reg, XOP_4V, + Sched<[sched]>; + def rm : IXOPi8Reg, XOP_4V, Sched<[sched.Folded, ReadAfterLd]>; +} + +let ExeDomain = SSEPackedInt in { + defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd", + int_x86_xop_vpmadcswd, SchedWriteVecIMul.XMM>; + defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", + int_x86_xop_vpmadcsswd, SchedWriteVecIMul.XMM>; + defm VPMACSWW : xop4opm2<0x95, "vpmacsww", + int_x86_xop_vpmacsww, SchedWriteVecIMul.XMM>; + defm VPMACSWD : xop4opm2<0x96, "vpmacswd", + int_x86_xop_vpmacswd, SchedWriteVecIMul.XMM>; + defm VPMACSSWW : xop4opm2<0x85, "vpmacssww", + int_x86_xop_vpmacssww, SchedWriteVecIMul.XMM>; + defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd", + int_x86_xop_vpmacsswd, SchedWriteVecIMul.XMM>; + defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", + int_x86_xop_vpmacssdql, SchedWritePMULLD.XMM>; + defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", + int_x86_xop_vpmacssdqh, SchedWritePMULLD.XMM>; + defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd", + int_x86_xop_vpmacssdd, SchedWritePMULLD.XMM>; + defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql", + int_x86_xop_vpmacsdql, SchedWritePMULLD.XMM>; + defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh", + int_x86_xop_vpmacsdqh, SchedWritePMULLD.XMM>; + defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd", + int_x86_xop_vpmacsdd, SchedWritePMULLD.XMM>; +} + +// IFMA patterns - for cases where we can safely ignore the overflow bits from +// the multiply or easily match with existing intrinsics. +let Predicates = [HasXOP] in { + def : Pat<(v8i16 (add (mul (v8i16 VR128:$src1), (v8i16 VR128:$src2)), + (v8i16 VR128:$src3))), + (VPMACSWWrr VR128:$src1, VR128:$src2, VR128:$src3)>; + def : Pat<(v4i32 (add (mul (v4i32 VR128:$src1), (v4i32 VR128:$src2)), + (v4i32 VR128:$src3))), + (VPMACSDDrr VR128:$src1, VR128:$src2, VR128:$src3)>; + def : Pat<(v2i64 (add (X86pmuldq (bc_v2i64 (X86PShufd (v4i32 VR128:$src1), (i8 -11))), + (bc_v2i64 (X86PShufd (v4i32 VR128:$src2), (i8 -11)))), + (v2i64 VR128:$src3))), + (VPMACSDQHrr VR128:$src1, VR128:$src2, VR128:$src3)>; + def : Pat<(v2i64 (add (X86pmuldq (v2i64 VR128:$src1), (v2i64 VR128:$src2)), + (v2i64 VR128:$src3))), + (VPMACSDQLrr VR128:$src1, VR128:$src2, VR128:$src3)>; + def : Pat<(v4i32 (add (X86vpmaddwd (v8i16 VR128:$src1), (v8i16 VR128:$src2)), + (v4i32 VR128:$src3))), + (VPMADCSWDrr VR128:$src1, VR128:$src2, VR128:$src3)>; +} + +// Transforms to swizzle an immediate to help matching memory operand in first +// operand. +def CommuteVPCOMCC : SDNodeXFormgetZExtValue() & 0x7; + Imm = X86::getSwappedVPCOMImm(Imm); + return getI8Imm(Imm, SDLoc(N)); +}]>; + +// Instruction where second source can be memory, third must be imm8 +multiclass xopvpcom opc, string Suffix, SDNode OpNode, ValueType vt128, + X86FoldableSchedWrite sched> { + let ExeDomain = SSEPackedInt in { // SSE integer instructions + let isCommutable = 1 in + def ri : IXOPi8, + XOP_4V, Sched<[sched]>; + def mi : IXOPi8, + XOP_4V, Sched<[sched.Folded, ReadAfterLd]>; + let isAsmParserOnly = 1, hasSideEffects = 0 in { + def ri_alt : IXOPi8, XOP_4V, Sched<[sched]>, NotMemoryFoldable; + let mayLoad = 1 in + def mi_alt : IXOPi8, XOP_4V, Sched<[sched.Folded, ReadAfterLd]>, + NotMemoryFoldable; + } + } + + def : Pat<(OpNode (bitconvert (loadv2i64 addr:$src2)), + (vt128 VR128:$src1), imm:$cc), + (!cast(NAME#"mi") VR128:$src1, addr:$src2, + (CommuteVPCOMCC imm:$cc))>; +} + +defm VPCOMB : xopvpcom<0xCC, "b", X86vpcom, v16i8, SchedWriteVecALU.XMM>; +defm VPCOMW : xopvpcom<0xCD, "w", X86vpcom, v8i16, SchedWriteVecALU.XMM>; +defm VPCOMD : xopvpcom<0xCE, "d", X86vpcom, v4i32, SchedWriteVecALU.XMM>; +defm VPCOMQ : xopvpcom<0xCF, "q", X86vpcom, v2i64, SchedWriteVecALU.XMM>; +defm VPCOMUB : xopvpcom<0xEC, "ub", X86vpcomu, v16i8, SchedWriteVecALU.XMM>; +defm VPCOMUW : xopvpcom<0xED, "uw", X86vpcomu, v8i16, SchedWriteVecALU.XMM>; +defm VPCOMUD : xopvpcom<0xEE, "ud", X86vpcomu, v4i32, SchedWriteVecALU.XMM>; +defm VPCOMUQ : xopvpcom<0xEF, "uq", X86vpcomu, v2i64, SchedWriteVecALU.XMM>; + +multiclass xop4op opc, string OpcodeStr, SDNode OpNode, + ValueType vt128, X86FoldableSchedWrite sched> { + def rrr : IXOPi8Reg, + XOP_4V, Sched<[sched]>; + def rrm : IXOPi8Reg, + XOP_4V, VEX_W, Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; + def rmr : IXOPi8Reg, + XOP_4V, Sched<[sched.Folded, ReadAfterLd, + // 128mem:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // VR128:$src3 + ReadAfterLd]>; + // For disassembler + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rrr_REV : IXOPi8Reg, XOP_4V, VEX_W, Sched<[sched]>, FoldGenData; +} + +let ExeDomain = SSEPackedInt in { + defm VPPERM : xop4op<0xA3, "vpperm", X86vpperm, v16i8, + SchedWriteVarShuffle.XMM>; +} + +// Instruction where either second or third source can be memory +multiclass xop4op_int opc, string OpcodeStr, RegisterClass RC, + X86MemOperand x86memop, ValueType VT, + X86FoldableSchedWrite sched> { + def rrr : IXOPi8Reg, XOP_4V, + Sched<[sched]>; + def rrm : IXOPi8Reg, + XOP_4V, VEX_W, Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; + def rmr : IXOPi8Reg, + XOP_4V, Sched<[sched.Folded, ReadAfterLd, + // x86memop:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC::$src3 + ReadAfterLd]>; + // For disassembler + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rrr_REV : IXOPi8Reg, XOP_4V, VEX_W, Sched<[sched]>, FoldGenData; +} + +let ExeDomain = SSEPackedInt in { + defm VPCMOV : xop4op_int<0xA2, "vpcmov", VR128, i128mem, v2i64, + SchedWriteShuffle.XMM>; + defm VPCMOVY : xop4op_int<0xA2, "vpcmov", VR256, i256mem, v4i64, + SchedWriteShuffle.YMM>, VEX_L; +} + +multiclass xop_vpermil2 Opc, string OpcodeStr, RegisterClass RC, + X86MemOperand intmemop, X86MemOperand fpmemop, + ValueType VT, PatFrag FPLdFrag, PatFrag IntLdFrag, + X86FoldableSchedWrite sched> { + def rr : IXOP5, + Sched<[sched]>; + def rm : IXOP5, VEX_W, + Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>; + def mr : IXOP5, + Sched<[sched.Folded, ReadAfterLd, + // fpmemop:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, + // RC:$src3 + ReadAfterLd]>; + // For disassembler + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rr_REV : IXOP5, VEX_W, Sched<[sched]>, FoldGenData; +} + +let ExeDomain = SSEPackedDouble in { + defm VPERMIL2PD : xop_vpermil2<0x49, "vpermil2pd", VR128, i128mem, f128mem, + v2f64, loadv2f64, loadv2i64, + SchedWriteFVarShuffle.XMM>; + defm VPERMIL2PDY : xop_vpermil2<0x49, "vpermil2pd", VR256, i256mem, f256mem, + v4f64, loadv4f64, loadv4i64, + SchedWriteFVarShuffle.YMM>, VEX_L; +} + +let ExeDomain = SSEPackedSingle in { + defm VPERMIL2PS : xop_vpermil2<0x48, "vpermil2ps", VR128, i128mem, f128mem, + v4f32, loadv4f32, loadv2i64, + SchedWriteFVarShuffle.XMM>; + defm VPERMIL2PSY : xop_vpermil2<0x48, "vpermil2ps", VR256, i256mem, f256mem, + v8f32, loadv8f32, loadv4i64, + SchedWriteFVarShuffle.YMM>, VEX_L; +} + diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86PfmCounters.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86PfmCounters.td new file mode 100644 index 0000000..093fbaf --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86PfmCounters.td @@ -0,0 +1,77 @@ +//===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This describes the available hardware counters for various subtargets. +// +//===----------------------------------------------------------------------===// + +let SchedModel = SandyBridgeModel in { +def SBCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; +def SBPort0Counter : PfmIssueCounter; +def SBPort1Counter : PfmIssueCounter; +def SBPort23Counter : PfmIssueCounter; +def SBPort4Counter : PfmIssueCounter; +def SBPort5Counter : PfmIssueCounter; +} + +let SchedModel = HaswellModel in { +def HWCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; +def HWPort0Counter : PfmIssueCounter; +def HWPort1Counter : PfmIssueCounter; +def HWPort2Counter : PfmIssueCounter; +def HWPort3Counter : PfmIssueCounter; +def HWPort4Counter : PfmIssueCounter; +def HWPort5Counter : PfmIssueCounter; +def HWPort6Counter : PfmIssueCounter; +def HWPort7Counter : PfmIssueCounter; +} + +let SchedModel = BroadwellModel in { +def BWCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; +def BWPort0Counter : PfmIssueCounter; +def BWPort1Counter : PfmIssueCounter; +def BWPort2Counter : PfmIssueCounter; +def BWPort3Counter : PfmIssueCounter; +def BWPort4Counter : PfmIssueCounter; +def BWPort5Counter : PfmIssueCounter; +def BWPort6Counter : PfmIssueCounter; +def BWPort7Counter : PfmIssueCounter; +} + +let SchedModel = SkylakeClientModel in { +def SKLCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; +def SKLPort0Counter : PfmIssueCounter; +def SKLPort1Counter : PfmIssueCounter; +def SKLPort2Counter : PfmIssueCounter; +def SKLPort3Counter : PfmIssueCounter; +def SKLPort4Counter : PfmIssueCounter; +def SKLPort5Counter : PfmIssueCounter; +def SKLPort6Counter : PfmIssueCounter; +def SKLPort7Counter : PfmIssueCounter; +} + +let SchedModel = SkylakeServerModel in { +def SKXCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; +def SKXPort0Counter : PfmIssueCounter; +def SKXPort1Counter : PfmIssueCounter; +def SKXPort2Counter : PfmIssueCounter; +def SKXPort3Counter : PfmIssueCounter; +def SKXPort4Counter : PfmIssueCounter; +def SKXPort5Counter : PfmIssueCounter; +def SKXPort6Counter : PfmIssueCounter; +def SKXPort7Counter : PfmIssueCounter; +} + +let SchedModel = BtVer2Model in { +def JCycleCounter : PfmCycleCounter<"cpu_clk_unhalted">; +def JFPU0Counter : PfmIssueCounter; +def JFPU1Counter : PfmIssueCounter; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86RegisterBanks.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86RegisterBanks.td new file mode 100644 index 0000000..6d17cd5 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86RegisterBanks.td @@ -0,0 +1,17 @@ +//=- X86RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +/// General Purpose Registers: RAX, RCX,... +def GPRRegBank : RegisterBank<"GPR", [GR64]>; + +/// Floating Point/Vector Registers +def VECRRegBank : RegisterBank<"VECR", [VR512]>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86RegisterInfo.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86RegisterInfo.td new file mode 100644 index 0000000..907d402 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86RegisterInfo.td @@ -0,0 +1,591 @@ +//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 Register file, defining the registers themselves, +// aliases between the registers, and the register classes built out of the +// registers. +// +//===----------------------------------------------------------------------===// + +class X86Reg Enc, list subregs = []> : Register { + let Namespace = "X86"; + let HWEncoding = Enc; + let SubRegs = subregs; +} + +// Subregister indices. +let Namespace = "X86" in { + def sub_8bit : SubRegIndex<8>; + def sub_8bit_hi : SubRegIndex<8, 8>; + def sub_8bit_hi_phony : SubRegIndex<8, 8>; + def sub_16bit : SubRegIndex<16>; + def sub_16bit_hi : SubRegIndex<16, 16>; + def sub_32bit : SubRegIndex<32>; + def sub_xmm : SubRegIndex<128>; + def sub_ymm : SubRegIndex<256>; +} + +//===----------------------------------------------------------------------===// +// Register definitions... +// + +// In the register alias definitions below, we define which registers alias +// which others. We only specify which registers the small registers alias, +// because the register file generator is smart enough to figure out that +// AL aliases AX if we tell it that AX aliased AL (for example). + +// Dwarf numbering is different for 32-bit and 64-bit, and there are +// variations by target as well. Currently the first entry is for X86-64, +// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux +// and debug information on X86-32/Darwin) + +// 8-bit registers +// Low registers +def AL : X86Reg<"al", 0>; +def DL : X86Reg<"dl", 2>; +def CL : X86Reg<"cl", 1>; +def BL : X86Reg<"bl", 3>; + +// High registers. On x86-64, these cannot be used in any instruction +// with a REX prefix. +def AH : X86Reg<"ah", 4>; +def DH : X86Reg<"dh", 6>; +def CH : X86Reg<"ch", 5>; +def BH : X86Reg<"bh", 7>; + +// X86-64 only, requires REX. +let CostPerUse = 1 in { +def SIL : X86Reg<"sil", 6>; +def DIL : X86Reg<"dil", 7>; +def BPL : X86Reg<"bpl", 5>; +def SPL : X86Reg<"spl", 4>; +def R8B : X86Reg<"r8b", 8>; +def R9B : X86Reg<"r9b", 9>; +def R10B : X86Reg<"r10b", 10>; +def R11B : X86Reg<"r11b", 11>; +def R12B : X86Reg<"r12b", 12>; +def R13B : X86Reg<"r13b", 13>; +def R14B : X86Reg<"r14b", 14>; +def R15B : X86Reg<"r15b", 15>; +} + +let isArtificial = 1 in { +// High byte of the low 16 bits of the super-register: +def SIH : X86Reg<"", -1>; +def DIH : X86Reg<"", -1>; +def BPH : X86Reg<"", -1>; +def SPH : X86Reg<"", -1>; +def R8BH : X86Reg<"", -1>; +def R9BH : X86Reg<"", -1>; +def R10BH : X86Reg<"", -1>; +def R11BH : X86Reg<"", -1>; +def R12BH : X86Reg<"", -1>; +def R13BH : X86Reg<"", -1>; +def R14BH : X86Reg<"", -1>; +def R15BH : X86Reg<"", -1>; +// High word of the low 32 bits of the super-register: +def HAX : X86Reg<"", -1>; +def HDX : X86Reg<"", -1>; +def HCX : X86Reg<"", -1>; +def HBX : X86Reg<"", -1>; +def HSI : X86Reg<"", -1>; +def HDI : X86Reg<"", -1>; +def HBP : X86Reg<"", -1>; +def HSP : X86Reg<"", -1>; +def HIP : X86Reg<"", -1>; +def R8WH : X86Reg<"", -1>; +def R9WH : X86Reg<"", -1>; +def R10WH : X86Reg<"", -1>; +def R11WH : X86Reg<"", -1>; +def R12WH : X86Reg<"", -1>; +def R13WH : X86Reg<"", -1>; +def R14WH : X86Reg<"", -1>; +def R15WH : X86Reg<"", -1>; +} + +// 16-bit registers +let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in { +def AX : X86Reg<"ax", 0, [AL,AH]>; +def DX : X86Reg<"dx", 2, [DL,DH]>; +def CX : X86Reg<"cx", 1, [CL,CH]>; +def BX : X86Reg<"bx", 3, [BL,BH]>; +} +let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in { +def SI : X86Reg<"si", 6, [SIL,SIH]>; +def DI : X86Reg<"di", 7, [DIL,DIH]>; +def BP : X86Reg<"bp", 5, [BPL,BPH]>; +def SP : X86Reg<"sp", 4, [SPL,SPH]>; +} +def IP : X86Reg<"ip", 0>; + +// X86-64 only, requires REX. +let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CostPerUse = 1, + CoveredBySubRegs = 1 in { +def R8W : X86Reg<"r8w", 8, [R8B,R8BH]>; +def R9W : X86Reg<"r9w", 9, [R9B,R9BH]>; +def R10W : X86Reg<"r10w", 10, [R10B,R10BH]>; +def R11W : X86Reg<"r11w", 11, [R11B,R11BH]>; +def R12W : X86Reg<"r12w", 12, [R12B,R12BH]>; +def R13W : X86Reg<"r13w", 13, [R13B,R13BH]>; +def R14W : X86Reg<"r14w", 14, [R14B,R14BH]>; +def R15W : X86Reg<"r15w", 15, [R15B,R15BH]>; +} + +// 32-bit registers +let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in { +def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>; +def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>; +def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>; +def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>; +def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>; +def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>; +def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>; +def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>; +def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>; +} + +// X86-64 only, requires REX +let SubRegIndices = [sub_16bit, sub_16bit_hi], CostPerUse = 1, + CoveredBySubRegs = 1 in { +def R8D : X86Reg<"r8d", 8, [R8W,R8WH]>; +def R9D : X86Reg<"r9d", 9, [R9W,R9WH]>; +def R10D : X86Reg<"r10d", 10, [R10W,R10WH]>; +def R11D : X86Reg<"r11d", 11, [R11W,R11WH]>; +def R12D : X86Reg<"r12d", 12, [R12W,R12WH]>; +def R13D : X86Reg<"r13d", 13, [R13W,R13WH]>; +def R14D : X86Reg<"r14d", 14, [R14W,R14WH]>; +def R15D : X86Reg<"r15d", 15, [R15W,R15WH]>; +} + +// 64-bit registers, X86-64 only +let SubRegIndices = [sub_32bit] in { +def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>; +def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>; +def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>; +def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>; +def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>; +def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>; +def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>; +def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>; + +// These also require REX. +let CostPerUse = 1 in { +def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>; +def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>; +def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>; +def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>; +def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>; +def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>; +def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>; +def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>; +def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>; +}} + +// MMX Registers. These are actually aliased to ST0 .. ST7 +def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>; +def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>; +def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>; +def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>; +def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>; +def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>; +def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>; +def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>; + +// Pseudo Floating Point registers +def FP0 : X86Reg<"fp0", 0>; +def FP1 : X86Reg<"fp1", 0>; +def FP2 : X86Reg<"fp2", 0>; +def FP3 : X86Reg<"fp3", 0>; +def FP4 : X86Reg<"fp4", 0>; +def FP5 : X86Reg<"fp5", 0>; +def FP6 : X86Reg<"fp6", 0>; +def FP7 : X86Reg<"fp7", 0>; + +// XMM Registers, used by the various SSE instruction set extensions. +def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>; +def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>; +def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>; +def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>; +def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>; +def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>; +def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>; +def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>; + +// X86-64 only +let CostPerUse = 1 in { +def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>; +def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>; +def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>; +def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>; +def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>; +def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>; +def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>; +def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>; + +def XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[67, -2, -2]>; +def XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[68, -2, -2]>; +def XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[69, -2, -2]>; +def XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[70, -2, -2]>; +def XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[71, -2, -2]>; +def XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[72, -2, -2]>; +def XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[73, -2, -2]>; +def XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[74, -2, -2]>; +def XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[75, -2, -2]>; +def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[76, -2, -2]>; +def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[77, -2, -2]>; +def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[78, -2, -2]>; +def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[79, -2, -2]>; +def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[80, -2, -2]>; +def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[81, -2, -2]>; +def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[82, -2, -2]>; + +} // CostPerUse + +// YMM0-15 registers, used by AVX instructions and +// YMM16-31 registers, used by AVX-512 instructions. +let SubRegIndices = [sub_xmm] in { + foreach Index = 0-31 in { + def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast("XMM"#Index)]>, + DwarfRegAlias("XMM"#Index)>; + } +} + +// ZMM Registers, used by AVX-512 instructions. +let SubRegIndices = [sub_ymm] in { + foreach Index = 0-31 in { + def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast("YMM"#Index)]>, + DwarfRegAlias("XMM"#Index)>; + } +} + +// Mask Registers, used by AVX-512 instructions. +def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>; +def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>; +def K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, 95, 95]>; +def K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, 96, 96]>; +def K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, 97, 97]>; +def K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, 98, 98]>; +def K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, 99, 99]>; +def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>; + +// Floating point stack registers. These don't map one-to-one to the FP +// pseudo registers, but we still mark them as aliasing FP registers. That +// way both kinds can be live without exceeding the stack depth. ST registers +// are only live around inline assembly. +def ST0 : X86Reg<"st(0)", 0>, DwarfRegNum<[33, 12, 11]>; +def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>; +def ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>; +def ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>; +def ST4 : X86Reg<"st(4)", 4>, DwarfRegNum<[37, 16, 15]>; +def ST5 : X86Reg<"st(5)", 5>, DwarfRegNum<[38, 17, 16]>; +def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>; +def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>; + +// Floating-point status word +def FPSW : X86Reg<"fpsw", 0>; + +// Status flags register. +// +// Note that some flags that are commonly thought of as part of the status +// flags register are modeled separately. Typically this is due to instructions +// reading and updating those flags independently of all the others. We don't +// want to create false dependencies between these instructions and so we use +// a separate register to model them. +def EFLAGS : X86Reg<"flags", 0>; + +// The direction flag. +def DF : X86Reg<"dirflag", 0>; + + +// Segment registers +def CS : X86Reg<"cs", 1>; +def DS : X86Reg<"ds", 3>; +def SS : X86Reg<"ss", 2>; +def ES : X86Reg<"es", 0>; +def FS : X86Reg<"fs", 4>; +def GS : X86Reg<"gs", 5>; + +// Debug registers +def DR0 : X86Reg<"dr0", 0>; +def DR1 : X86Reg<"dr1", 1>; +def DR2 : X86Reg<"dr2", 2>; +def DR3 : X86Reg<"dr3", 3>; +def DR4 : X86Reg<"dr4", 4>; +def DR5 : X86Reg<"dr5", 5>; +def DR6 : X86Reg<"dr6", 6>; +def DR7 : X86Reg<"dr7", 7>; +def DR8 : X86Reg<"dr8", 8>; +def DR9 : X86Reg<"dr9", 9>; +def DR10 : X86Reg<"dr10", 10>; +def DR11 : X86Reg<"dr11", 11>; +def DR12 : X86Reg<"dr12", 12>; +def DR13 : X86Reg<"dr13", 13>; +def DR14 : X86Reg<"dr14", 14>; +def DR15 : X86Reg<"dr15", 15>; + +// Control registers +def CR0 : X86Reg<"cr0", 0>; +def CR1 : X86Reg<"cr1", 1>; +def CR2 : X86Reg<"cr2", 2>; +def CR3 : X86Reg<"cr3", 3>; +def CR4 : X86Reg<"cr4", 4>; +def CR5 : X86Reg<"cr5", 5>; +def CR6 : X86Reg<"cr6", 6>; +def CR7 : X86Reg<"cr7", 7>; +def CR8 : X86Reg<"cr8", 8>; +def CR9 : X86Reg<"cr9", 9>; +def CR10 : X86Reg<"cr10", 10>; +def CR11 : X86Reg<"cr11", 11>; +def CR12 : X86Reg<"cr12", 12>; +def CR13 : X86Reg<"cr13", 13>; +def CR14 : X86Reg<"cr14", 14>; +def CR15 : X86Reg<"cr15", 15>; + +// Pseudo index registers +def EIZ : X86Reg<"eiz", 4>; +def RIZ : X86Reg<"riz", 4>; + +// Bound registers, used in MPX instructions +def BND0 : X86Reg<"bnd0", 0>; +def BND1 : X86Reg<"bnd1", 1>; +def BND2 : X86Reg<"bnd2", 2>; +def BND3 : X86Reg<"bnd3", 3>; + +// CET registers - Shadow Stack Pointer +def SSP : X86Reg<"ssp", 0>; + +//===----------------------------------------------------------------------===// +// Register Class Definitions... now that we have all of the pieces, define the +// top-level register classes. The order specified in the register list is +// implicitly defined to be the register allocation order. +// + +// List call-clobbered registers before callee-save registers. RBX, RBP, (and +// R12, R13, R14, and R15 for X86-64) are callee-save registers. +// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and +// R8B, ... R15B. +// Allocate R12 and R13 last, as these require an extra byte when +// encoded in x86_64 instructions. +// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in +// 64-bit mode. The main complication is that they cannot be encoded in an +// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc. +// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d" +// cannot be encoded. +def GR8 : RegisterClass<"X86", [i8], 8, + (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, + R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B)> { + let AltOrders = [(sub GR8, AH, BH, CH, DH)]; + let AltOrderSelect = [{ + return MF.getSubtarget().is64Bit(); + }]; +} + +let isAllocatable = 0 in +def GRH8 : RegisterClass<"X86", [i8], 8, + (add SIH, DIH, BPH, SPH, R8BH, R9BH, R10BH, R11BH, + R12BH, R13BH, R14BH, R15BH)>; + +def GR16 : RegisterClass<"X86", [i16], 16, + (add AX, CX, DX, SI, DI, BX, BP, SP, + R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W)>; + +let isAllocatable = 0 in +def GRH16 : RegisterClass<"X86", [i16], 16, + (add HAX, HCX, HDX, HSI, HDI, HBX, HBP, HSP, HIP, + R8WH, R9WH, R10WH, R11WH, R12WH, R13WH, R14WH, + R15WH)>; + +def GR32 : RegisterClass<"X86", [i32], 32, + (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, + R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D)>; + +// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since +// RIP isn't really a register and it can't be used anywhere except in an +// address, but it doesn't cause trouble. +// FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra +// tests because of the inclusion of RIP in this register class. +def GR64 : RegisterClass<"X86", [i64], 64, + (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, + RBX, R14, R15, R12, R13, RBP, RSP, RIP)>; + +// Segment registers for use by MOV instructions (and others) that have a +// segment register as one operand. Always contain a 16-bit segment +// descriptor. +def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; + +// Debug registers. +def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 15)>; + +// Control registers. +def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>; + +// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of +// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" +// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers +// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD, +// and GR64_ABCD are classes for registers that support 8-bit h-register +// operations. +def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>; +def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; +def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>; +def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>; +def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>; +def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX)>; +def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, + R8, R9, R11, RIP)>; +def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, + R8, R9, R10, R11, RIP)>; + +// GR8_NOREX - GR8 registers which do not require a REX prefix. +def GR8_NOREX : RegisterClass<"X86", [i8], 8, + (add AL, CL, DL, AH, CH, DH, BL, BH)> { + let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)]; + let AltOrderSelect = [{ + return MF.getSubtarget().is64Bit(); + }]; +} +// GR16_NOREX - GR16 registers which do not require a REX prefix. +def GR16_NOREX : RegisterClass<"X86", [i16], 16, + (add AX, CX, DX, SI, DI, BX, BP, SP)>; +// GR32_NOREX - GR32 registers which do not require a REX prefix. +def GR32_NOREX : RegisterClass<"X86", [i32], 32, + (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>; +// GR64_NOREX - GR64 registers which do not require a REX prefix. +def GR64_NOREX : RegisterClass<"X86", [i64], 64, + (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>; + +// GR32_NOSP - GR32 registers except ESP. +def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; + +// GR64_NOSP - GR64 registers except RSP (and RIP). +def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>; + +// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except +// ESP. +def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32, + (and GR32_NOREX, GR32_NOSP)>; + +// GR64_NOREX_NOSP - GR64_NOREX registers except RSP. +def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, + (and GR64_NOREX, GR64_NOSP)>; + +// Register classes used for ABIs that use 32-bit address accesses, +// while using the whole x84_64 ISA. + +// In such cases, it is fine to use RIP as we are sure the 32 high +// bits are not set. We do not need variants for NOSP as RIP is not +// allowed there. +// RIP is not spilled anywhere for now, so stick to 32-bit alignment +// to save on memory space. +// FIXME: We could allow all 64bit registers, but we would need +// something to check that the 32 high bits are not set, +// which we do not have right now. +def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; + +// When RBP is used as a base pointer in a 32-bit addresses environment, +// this is also safe to use the full register to access addresses. +// Since RBP will never be spilled, stick to a 32 alignment to save +// on memory consumption. +def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32, + (add LOW32_ADDR_ACCESS, RBP)>; + +// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX. +def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; +def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>; + +// Scalar SSE2 floating point registers. +def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; + +def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; + + +// FIXME: This sets up the floating point register files as though they are f64 +// values, though they really are f80 values. This will cause us to spill +// values as 64-bit quantities instead of 80-bit quantities, which is much much +// faster on common hardware. In reality, this should be controlled by a +// command line option or something. + +def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>; +def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>; +def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>; + +// Floating point stack registers (these are not allocatable by the +// register allocator - the floating point stackifier is responsible +// for transforming FPn allocations to STn registers) +def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> { + let isAllocatable = 0; +} + +// Generic vector registers: VR64 and VR128. +// Ensure that float types are declared first - only float is legal on SSE1. +def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>; +def VR128 : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], + 128, (add FR32)>; +def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], + 256, (sequence "YMM%u", 0, 15)>; + +// Special classes that help the assembly parser choose some alternate +// instructions to favor 2-byte VEX encodings. +def VR128L : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], + 128, (sequence "XMM%u", 0, 7)>; +def VR128H : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], + 128, (sequence "XMM%u", 8, 15)>; +def VR256L : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], + 256, (sequence "YMM%u", 0, 7)>; +def VR256H : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], + 256, (sequence "YMM%u", 8, 15)>; + +// Status flags registers. +def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> { + let CopyCost = -1; // Don't allow copying of status registers. + let isAllocatable = 0; +} +def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> { + let CopyCost = -1; // Don't allow copying of status registers. + let isAllocatable = 0; +} +def DFCCR : RegisterClass<"X86", [i32], 32, (add DF)> { + let CopyCost = -1; // Don't allow copying of status registers. + let isAllocatable = 0; +} + +// AVX-512 vector/mask registers. +def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], + 512, (sequence "ZMM%u", 0, 31)>; + +// Scalar AVX-512 floating point registers. +def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>; + +def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>; + +// Extended VR128 and VR256 for AVX-512 instructions +def VR128X : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], + 128, (add FR32X)>; +def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], + 256, (sequence "YMM%u", 0, 31)>; + +// Mask registers +def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;} +def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;} +def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;} +def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;} +def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;} +def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;} +def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;} + +def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;} +def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;} +def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;} +def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;} +def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;} +def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;} +def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;} + +// Bound registers +def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedBroadwell.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedBroadwell.td new file mode 100644 index 0000000..6334d9e --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedBroadwell.td @@ -0,0 +1,1692 @@ +//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Broadwell to support instruction +// scheduling and other instruction cost heuristics. +// +//===----------------------------------------------------------------------===// + +def BroadwellModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and BW can decode 4 + // instructions per cycle. + let IssueWidth = 4; + let MicroOpBufferSize = 192; // Based on the reorder buffer. + let LoadLatency = 5; + let MispredictPenalty = 16; + + // Based on the LSD (loop-stream detector) queue size and benchmarking data. + let LoopMicroOpBufferSize = 50; + + // This flag is set to allow the scheduler to assign a default model to + // unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = BroadwellModel in { + +// Broadwell can issue micro-ops to 8 different ports in one cycle. + +// Ports 0, 1, 5, and 6 handle all computation. +// Port 4 gets the data half of stores. Store data can be available later than +// the store address, but since we don't model the latency of stores, we can +// ignore that. +// Ports 2 and 3 are identical. They handle loads and the address half of +// stores. Port 7 can handle address calculations. +def BWPort0 : ProcResource<1>; +def BWPort1 : ProcResource<1>; +def BWPort2 : ProcResource<1>; +def BWPort3 : ProcResource<1>; +def BWPort4 : ProcResource<1>; +def BWPort5 : ProcResource<1>; +def BWPort6 : ProcResource<1>; +def BWPort7 : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>; +def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>; +def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>; +def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>; +def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>; +def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>; +def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>; +def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>; +def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>; +def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>; +def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>; +def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>; + +// 60 Entry Unified Scheduler +def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4, + BWPort5, BWPort6, BWPort7]> { + let BufferSize=60; +} + +// Integer division issued on port 0. +def BWDivider : ProcResource<1>; +// FP division and sqrt on port 0. +def BWFPDivider : ProcResource<1>; + +// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass BWWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 5> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to + // the latency (default = 5). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = !add(UOps, 1); + } +} + +// A folded store needs a cycle on port 4 for the store data, and an extra port +// 2/3/7 cycle to recompute the address. +def : WriteRes; + +// Arithmetic. +defm : BWWriteResPair; // Simple integer ALU op. +defm : BWWriteResPair; // Integer ALU + flags op. +defm : BWWriteResPair; // Integer multiplication. +defm : BWWriteResPair; // Integer 64-bit multiplication. +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : BWWriteResPair; +def : WriteRes { let Latency = 3; } // Integer multiplication, high part. + +def : WriteRes; // LEA instructions can't fold loads. + +defm : BWWriteResPair; // Conditional move. +defm : BWWriteResPair; // // Conditional (CF + ZF flag) move. +defm : X86WriteRes; // x87 conditional move. + +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} +def : WriteRes; +def : WriteRes; // Bit Test instrs + +// Bit counts. +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; + +// Integer shifts and rotates. +defm : BWWriteResPair; + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// BMI1 BEXTR, BMI2 BZHI +defm : BWWriteResPair; +defm : BWWriteResPair; + +// Loads, stores, and moves, not folded with other operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +def : WriteRes; + +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +defm : BWWriteResPair; + +// Floating point. This covers both scalar and vector operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : BWWriteResPair; // Floating point add/sub. +defm : BWWriteResPair; // Floating point add/sub (XMM). +defm : BWWriteResPair; // Floating point add/sub (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point double add/sub. +defm : BWWriteResPair; // Floating point double add/sub (XMM). +defm : BWWriteResPair; // Floating point double add/sub (YMM/ZMM). +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; // Floating point compare. +defm : BWWriteResPair; // Floating point compare (XMM). +defm : BWWriteResPair; // Floating point compare (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point double compare. +defm : BWWriteResPair; // Floating point double compare (XMM). +defm : BWWriteResPair; // Floating point double compare (YMM/ZMM). +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; // Floating point compare to flags. + +defm : BWWriteResPair; // Floating point multiplication. +defm : BWWriteResPair; // Floating point multiplication (XMM). +defm : BWWriteResPair; // Floating point multiplication (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point double multiplication. +defm : BWWriteResPair; // Floating point double multiplication (XMM). +defm : BWWriteResPair; // Floating point double multiplication (YMM/ZMM). +defm : X86WriteResPairUnsupported; + +//defm : BWWriteResPair; // Floating point division. +defm : BWWriteResPair; // Floating point division (XMM). +defm : BWWriteResPair; // Floating point division (YMM). +defm : X86WriteResPairUnsupported; +//defm : BWWriteResPair; // Floating point division. +defm : BWWriteResPair; // Floating point division (XMM). +defm : BWWriteResPair; // Floating point division (YMM). +defm : X86WriteResPairUnsupported; + +defm : X86WriteRes; // Floating point square root. +defm : X86WriteRes; +defm : BWWriteResPair; // Floating point square root (XMM). +defm : BWWriteResPair; // Floating point square root (YMM). +defm : X86WriteResPairUnsupported; +defm : X86WriteRes; // Floating point double square root. +defm : X86WriteRes; +defm : BWWriteResPair; // Floating point double square root (XMM). +defm : BWWriteResPair; // Floating point double square root (YMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point long double square root. + +defm : BWWriteResPair; // Floating point reciprocal estimate. +defm : BWWriteResPair; // Floating point reciprocal estimate (XMM). +defm : BWWriteResPair; // Floating point reciprocal estimate (YMM/ZMM). +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; // Floating point reciprocal square root estimate. +defm : BWWriteResPair; // Floating point reciprocal square root estimate (XMM). +defm : BWWriteResPair; // Floating point reciprocal square root estimate (YMM/ZMM). +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; // Fused Multiply Add. +defm : BWWriteResPair; // Fused Multiply Add (XMM). +defm : BWWriteResPair; // Fused Multiply Add (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point double dot product. +defm : BWWriteResPair; // Floating point single dot product. +defm : BWWriteResPair; // Floating point single dot product (YMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point fabs/fchs. +defm : X86WriteRes; // Floating point rounding. +defm : X86WriteRes; // Floating point rounding (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; +defm : BWWriteResPair; // Floating point and/or/xor logicals. +defm : BWWriteResPair; // Floating point and/or/xor logicals (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point TEST instructions. +defm : BWWriteResPair; // Floating point TEST instructions (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point vector shuffles. +defm : BWWriteResPair; // Floating point vector shuffles (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point vector variable shuffles. +defm : BWWriteResPair; // Floating point vector variable shuffles. +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Floating point vector blends. +defm : BWWriteResPair; // Floating point vector blends. +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Fp vector variable blends. +defm : BWWriteResPair; // Fp vector variable blends. +defm : X86WriteResPairUnsupported; + +// FMA Scheduling helper class. +// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } + +// Vector integer operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; + +defm : BWWriteResPair; // Vector integer ALU op, no logicals. +defm : BWWriteResPair; // Vector integer ALU op, no logicals. +defm : BWWriteResPair; // Vector integer ALU op, no logicals (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector integer and/or/xor. +defm : BWWriteResPair; // Vector integer and/or/xor. +defm : BWWriteResPair; // Vector integer and/or/xor (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector integer TEST instructions. +defm : BWWriteResPair; // Vector integer TEST instructions (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector integer multiply. +defm : BWWriteResPair; // Vector integer multiply. +defm : BWWriteResPair; // Vector integer multiply. +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector PMULLD. +defm : BWWriteResPair; // Vector PMULLD (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector shuffles. +defm : BWWriteResPair; // Vector shuffles. +defm : BWWriteResPair; // Vector shuffles (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector variable shuffles. +defm : BWWriteResPair; // Vector variable shuffles. +defm : BWWriteResPair; // Vector variable shuffles (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector blends. +defm : BWWriteResPair; // Vector blends (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector variable blends. +defm : BWWriteResPair; // Vector variable blends (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector MPSAD. +defm : BWWriteResPair; // Vector MPSAD. +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector PSADBW. +defm : BWWriteResPair; // Vector PSADBW. +defm : BWWriteResPair; // Vector PSADBW (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Vector PHMINPOS. + +// Vector integer shifts. +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; +defm : BWWriteResPair; // Vector integer immediate shifts (XMM). +defm : BWWriteResPair; // Vector integer immediate shifts (YMM/ZMM). +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; // Variable vector shifts. +defm : BWWriteResPair; // Variable vector shifts (YMM/ZMM). +defm : X86WriteResPairUnsupported; + +// Vector insert/extract operations. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 6; + let NumMicroOps = 2; +} + +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + +// Conversion between integer and float. +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteResPairUnsupported; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; + +// Strings instructions. + +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 19; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} +def : WriteRes { + let Latency = 24; + let NumMicroOps = 10; + let ResourceCycles = [4,3,1,1,1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [4,3,1]; +} +def : WriteRes { + let Latency = 23; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 1; } + +// AES instructions. +def : WriteRes { // Decryption, encryption. + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +def : WriteRes { // InvMixColumn. + let Latency = 14; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 19; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} + +def : WriteRes { // Key Generation. + let Latency = 29; + let NumMicroOps = 11; + let ResourceCycles = [2,7,2]; +} +def : WriteRes { + let Latency = 33; + let NumMicroOps = 11; + let ResourceCycles = [2,7,1,1]; +} + +// Carry-less multiplication instructions. +defm : BWWriteResPair; + +// Catch-all for expensive system instructions. +def : WriteRes { let Latency = 100; } // def WriteSystem : SchedWrite; + +// AVX2. +defm : BWWriteResPair; // Fp 256-bit width vector shuffles. +defm : BWWriteResPair; // Fp 256-bit width vector variable shuffles. +defm : BWWriteResPair; // 256-bit width vector shuffles. +defm : BWWriteResPair; // 256-bit width vector variable shuffles. + +// Old microcoded instructions that nobody use. +def : WriteRes { let Latency = 100; } // def WriteMicrocoded : SchedWrite; + +// Fence instructions. +def : WriteRes; + +// Load/store MXCSR. +def : WriteRes { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } +def : WriteRes { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } + +// Nop, not very useful expect it provides a model for nops! +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; + +// Remaining instrs. + +def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr", + "VPSRLVQ(Y?)rr")>; + +def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r", + "UCOM_F(P?)r")>; + +def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVQ2DQrr")>; + +def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>; + +def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>; + +def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>; + +def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr", + "BLSI(32|64)rr", + "BLSMSK(32|64)rr", + "BLSR(32|64)rr")>; + +def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>; + +def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup9], (instregex "SGDT64m", + "SIDT64m", + "SMSW16m", + "STRm", + "SYSCALL")>; + +def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm", + "ST_FP(32|64|80)m")>; + +def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>; + +def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1", + "ROL(8|16|32|64)ri", + "ROR(8|16|32|64)r1", + "ROR(8|16|32|64)ri")>; + +def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[BWWriteResGroup14], (instrs LFENCE, + MFENCE, + WAIT, + XGETBV)>; + +def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup15], (instregex "(V?)CVTPS2PDrr", + "(V?)CVTSS2SDrr")>; + +def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>; + +def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>; + +def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>; + +def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup20], (instrs CWD)>; +def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>; +def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8", + "ADC8ri", + "SBB8i8", + "SBB8ri", + "SET(A|BE)r")>; + +def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>; + +def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>; + +def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, + STOSB, STOSL, STOSQ, STOSW)>; +def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr", + "PUSH64i8")>; + +def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup27], (instregex "MMX_CVTPI2PSirr", + "PDEP(32|64)rr", + "PEXT(32|64)rr", + "(V?)CVTDQ2PS(Y?)rr")>; + +def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>; + +def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup28], (instregex "VPBROADCASTBrr", + "VPBROADCASTWrr")>; + +def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[BWWriteResGroup30], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr, + XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr, + XCHG16ar, XCHG32ar, XCHG64ar)>; + +def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr", + "MMX_PACKSSWBirr", + "MMX_PACKUSWBirr")>; + +def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[BWWriteResGroup34], (instregex "CLD")>; + +def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1", + "RCL(8|16|32|64)ri", + "RCR(8|16|32|64)r1", + "RCR(8|16|32|64)ri")>; + +def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL", + "ROR(8|16|32|64)rCL", + "SAR(8|16|32|64)rCL", + "SHL(8|16|32|64)rCL", + "SHR(8|16|32|64)rCL")>; + +def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>; + +def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>; +def: InstRW<[BWWriteResGroup38], (instregex "SET(A|BE)m")>; + +def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr", + "(V?)CVT(T?)SD2SIrr", + "(V?)CVT(T?)SS2SI64rr", + "(V?)CVT(T?)SS2SIrr")>; + +def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr")>; + +def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>; + +def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>; +def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPI2PDirr", + "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", + "(V?)CVTDQ2PDrr", + "(V?)CVTPD2PSrr", + "(V?)CVTSD2SSrr", + "(V?)CVTSI642SDrr", + "(V?)CVTSI2SDrr", + "(V?)CVTSI2SSrr", + "(V?)CVT(T?)PD2DQrr")>; + +def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>; + +def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>; + +def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m", + "IST_F(16|32)m")>; + +def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [4]; +} +def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>; + +def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>; + +def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup47], (instregex "(V?)PCMPGTQ(Y?)rr", + "MUL_(FPrST0|FST0r|FrST0)")>; + +def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm16", + "MOVSX(16|32|64)rm32", + "MOVSX(16|32|64)rm8", + "MOVZX(16|32|64)rm16", + "MOVZX(16|32|64)rm8", + "VBROADCASTSSrm", + "(V?)MOVDDUPrm", + "(V?)MOVSHDUPrm", + "(V?)MOVSLDUPrm", + "VPBROADCASTDrm", + "VPBROADCASTQrm")>; + +def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>; + +def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>; + +def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup52], (instrs IMUL32r, MUL32r, MULX32rr)>; + +def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>; + +def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>; + +def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [2,3]; +} +def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>; + +def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { + let Latency = 5; + let NumMicroOps = 6; + let ResourceCycles = [1,1,4]; +} +def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>; + +def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m", + "VBROADCASTF128", + "VBROADCASTI128", + "VBROADCASTSDYrm", + "VBROADCASTSSYrm", + "VMOVDDUPYrm", + "VMOVSHDUPYrm", + "VMOVSLDUPYrm", + "VPBROADCASTDYrm", + "VPBROADCASTQYrm")>; + +def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup59], (instregex "(V?)CVTPS2PDrm", + "(V?)CVTSS2SDrm", + "VPSLLVQrm", + "VPSRLVQrm")>; + +def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr", + "VCVTPD2PSYrr", + "VCVT(T?)PD2DQYrr")>; + +def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64", + "JMP(16|32|64)m")>; + +def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8")>; + +def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm", + "BLSI(32|64)rm", + "BLSMSK(32|64)rm", + "BLSR(32|64)rm", + "MOVBE(16|32|64)rm")>; + +def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup65], (instregex "VINSERTF128rm", + "VINSERTI128rm", + "VPBLENDDrmi")>; + +def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>; +def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>; + +def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>; + +def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8", + "BTR(16|32|64)mi8", + "BTS(16|32|64)mi8", + "SAR(8|16|32|64)m1", + "SAR(8|16|32|64)mi", + "SHL(8|16|32|64)m1", + "SHL(8|16|32|64)mi", + "SHR(8|16|32|64)m1", + "SHR(8|16|32|64)mi")>; + +def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm", + "PUSH(16|32|64)rmm")>; + +def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> { + let Latency = 6; + let NumMicroOps = 6; + let ResourceCycles = [1,5]; +} +def: InstRW<[BWWriteResGroup71], (instrs STD)>; + +def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup73], (instregex "VPSLLVQYrm", + "VPSRLVQYrm")>; + +def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>; + +def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup77], (instregex "VPBLENDDYrmi")>; + +def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[BWWriteResGroup79], (instregex "MMX_PACKSSDWirm", + "MMX_PACKSSWBirm", + "MMX_PACKUSWBirm")>; + +def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64, + SCASB, SCASL, SCASQ, SCASW)>; + +def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>; + +def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>; + +def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1", + "ROL(8|16|32|64)mi", + "ROR(8|16|32|64)m1", + "ROR(8|16|32|64)mi")>; + +def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>; + +def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,1,1]; +} +def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m", + "FARCALL64")>; + +def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> { + let Latency = 7; + let NumMicroOps = 7; + let ResourceCycles = [2,2,1,2]; +} +def: InstRW<[BWWriteResGroup90], (instrs LOOP)>; + +def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm", + "PDEP(32|64)rm", + "PEXT(32|64)rm", + "(V?)CVTDQ2PSrm")>; + +def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rmi, IMUL16rmi8)>; + +def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort06, BWPort0156, BWPort23]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>; + +def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm", + "VPMOVSXBQYrm", + "VPMOVSXBWYrm", + "VPMOVSXDQYrm", + "VPMOVSXWDYrm", + "VPMOVSXWQYrm", + "VPMOVZXWDYrm")>; + +def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1", + "RCL(8|16|32|64)mi", + "RCR(8|16|32|64)m1", + "RCR(8|16|32|64)mi")>; + +def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>; + +def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,3]; +} +def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>; + +def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,2,1]; +} +def : SchedAlias; +def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG(8|16|32|64)rm", + "ROL(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; + +def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", + "ILD_F(16|32|64)m", + "VCVTPS2DQYrm", + "VCVTTPS2DQYrm")>; + +def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm", + "(V?)CVT(T?)SD2SI64rm", + "(V?)CVT(T?)SD2SIrm", + "VCVTTSS2SI64rm", + "(V?)CVTTSS2SIrm")>; + +def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>; + +def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>; +def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2PSrm", + "CVT(T?)PD2DQrm", + "MMX_CVTPI2PDirm", + "MMX_CVT(T?)PD2PIirm", + "(V?)CVTDQ2PDrm", + "(V?)CVTSD2SSrm")>; + +def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm", + "VPBROADCASTW(Y?)rm")>; + +def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,3]; +} +def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>; + +def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm", + "LSL(16|32|64)rm")>; + +def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>; + +def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>; + +def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> { + let Latency = 10; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>; + +def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>; + +def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { + let Latency = 11; + let NumMicroOps = 1; + let ResourceCycles = [1,3]; // Really 2.5 cycle throughput +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m", + "VPCMPGTQYrm")>; + +def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>; + +def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { + let Latency = 11; + let NumMicroOps = 7; + let ResourceCycles = [2,2,3]; +} +def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL", + "RCR(16|32|64)rCL")>; + +def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { + let Latency = 11; + let NumMicroOps = 9; + let ResourceCycles = [1,4,1,3]; +} +def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>; + +def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> { + let Latency = 11; + let NumMicroOps = 11; + let ResourceCycles = [2,9]; +} +def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>; +def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>; + +def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; + +def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1,4]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>; + +def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { + let Latency = 14; + let NumMicroOps = 8; + let ResourceCycles = [2,2,1,3]; +} +def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>; + +def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { + let Latency = 14; + let NumMicroOps = 10; + let ResourceCycles = [2,3,1,4]; +} +def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>; + +def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> { + let Latency = 14; + let NumMicroOps = 12; + let ResourceCycles = [2,1,4,5]; +} +def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>; + +def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> { + let Latency = 15; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; + +def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { + let Latency = 15; + let NumMicroOps = 10; + let ResourceCycles = [1,1,1,4,1,2]; +} +def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>; + +def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { + let Latency = 16; + let NumMicroOps = 2; + let ResourceCycles = [1,1,5]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { + let Latency = 16; + let NumMicroOps = 14; + let ResourceCycles = [1,1,1,4,2,5]; +} +def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>; + +def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> { + let Latency = 16; + let NumMicroOps = 16; + let ResourceCycles = [16]; +} +def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>; + +def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,5]; +} +def: InstRW<[BWWriteResGroup159], (instrs CPUID)>; +def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>; + +def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { + let Latency = 18; + let NumMicroOps = 11; + let ResourceCycles = [2,1,1,3,1,3]; +} +def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>; + +def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { + let Latency = 19; + let NumMicroOps = 2; + let ResourceCycles = [1,1,8]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> { + let Latency = 20; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; + +def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { + let Latency = 20; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,1,2]; +} +def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>; + +def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> { + let Latency = 21; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>; + +def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> { + let Latency = 21; + let NumMicroOps = 19; + let ResourceCycles = [2,1,4,1,1,4,6]; +} +def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>; + +def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { + let Latency = 22; + let NumMicroOps = 18; + let ResourceCycles = [1,1,16]; +} +def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>; + +def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { + let Latency = 23; + let NumMicroOps = 19; + let ResourceCycles = [3,1,15]; +} +def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>; + +def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { + let Latency = 24; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>; + +def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> { + let Latency = 26; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>; + +def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { + let Latency = 29; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>; + +def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 22; + let NumMicroOps = 7; + let ResourceCycles = [1,3,2,1]; +} +def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>; + +def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 23; + let NumMicroOps = 9; + let ResourceCycles = [1,3,4,1]; +} +def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>; + +def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 24; + let NumMicroOps = 9; + let ResourceCycles = [1,5,2,1]; +} +def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>; + +def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 25; + let NumMicroOps = 7; + let ResourceCycles = [1,3,2,1]; +} +def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm, + VGATHERDPSrm)>; + +def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 26; + let NumMicroOps = 9; + let ResourceCycles = [1,5,2,1]; +} +def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>; + +def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 26; + let NumMicroOps = 14; + let ResourceCycles = [1,4,8,1]; +} +def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>; + +def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { + let Latency = 27; + let NumMicroOps = 9; + let ResourceCycles = [1,5,2,1]; +} +def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>; + +def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { + let Latency = 29; + let NumMicroOps = 27; + let ResourceCycles = [1,5,1,1,19]; +} +def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>; + +def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { + let Latency = 30; + let NumMicroOps = 28; + let ResourceCycles = [1,6,1,1,19]; +} +def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>; +def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; + +def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> { + let Latency = 34; + let NumMicroOps = 8; + let ResourceCycles = [2,2,2,1,1]; +} +def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>; + +def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> { + let Latency = 34; + let NumMicroOps = 23; + let ResourceCycles = [1,5,3,4,10]; +} +def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri", + "IN(8|16|32)rr")>; + +def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> { + let Latency = 35; + let NumMicroOps = 8; + let ResourceCycles = [2,2,2,1,1]; +} +def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>; + +def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,2,1,4,10]; +} +def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir", + "OUT(8|16|32)rr")>; + +def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> { + let Latency = 42; + let NumMicroOps = 22; + let ResourceCycles = [2,20]; +} +def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>; + +def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> { + let Latency = 60; + let NumMicroOps = 64; + let ResourceCycles = [2,2,8,1,10,2,39]; +} +def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>; + +def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { + let Latency = 63; + let NumMicroOps = 88; + let ResourceCycles = [4,4,31,1,2,1,45]; +} +def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>; + +def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { + let Latency = 63; + let NumMicroOps = 90; + let ResourceCycles = [4,2,33,1,2,1,47]; +} +def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>; + +def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> { + let Latency = 75; + let NumMicroOps = 15; + let ResourceCycles = [6,3,6]; +} +def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>; + +def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> { + let Latency = 80; + let NumMicroOps = 32; + let ResourceCycles = [7,7,3,3,1,11]; +} +def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>; + +def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> { + let Latency = 115; + let NumMicroOps = 100; + let ResourceCycles = [9,9,11,8,1,11,21,30]; +} +def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>; + +def: InstRW<[WriteZero], (instrs CLC)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedHaswell.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedHaswell.td new file mode 100644 index 0000000..876c3e4 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedHaswell.td @@ -0,0 +1,1975 @@ +//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Haswell to support instruction +// scheduling and other instruction cost heuristics. +// +// Note that we define some instructions here that are not supported by haswell, +// but we still have to define them because KNL uses the HSW model. +// They are currently tagged with a comment `Unsupported = 1`. +// FIXME: Use Unsupported = 1 once KNL has its own model. +// +//===----------------------------------------------------------------------===// + +def HaswellModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and HW can decode 4 + // instructions per cycle. + let IssueWidth = 4; + let MicroOpBufferSize = 192; // Based on the reorder buffer. + let LoadLatency = 5; + let MispredictPenalty = 16; + + // Based on the LSD (loop-stream detector) queue size and benchmarking data. + let LoopMicroOpBufferSize = 50; + + // This flag is set to allow the scheduler to assign a default model to + // unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = HaswellModel in { + +// Haswell can issue micro-ops to 8 different ports in one cycle. + +// Ports 0, 1, 5, and 6 handle all computation. +// Port 4 gets the data half of stores. Store data can be available later than +// the store address, but since we don't model the latency of stores, we can +// ignore that. +// Ports 2 and 3 are identical. They handle loads and the address half of +// stores. Port 7 can handle address calculations. +def HWPort0 : ProcResource<1>; +def HWPort1 : ProcResource<1>; +def HWPort2 : ProcResource<1>; +def HWPort3 : ProcResource<1>; +def HWPort4 : ProcResource<1>; +def HWPort5 : ProcResource<1>; +def HWPort6 : ProcResource<1>; +def HWPort7 : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def HWPort01 : ProcResGroup<[HWPort0, HWPort1]>; +def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>; +def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>; +def HWPort04 : ProcResGroup<[HWPort0, HWPort4]>; +def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>; +def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>; +def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>; +def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>; +def HWPort56 : ProcResGroup<[HWPort5, HWPort6]>; +def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; +def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>; +def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; + +// 60 Entry Unified Scheduler +def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4, + HWPort5, HWPort6, HWPort7]> { + let BufferSize=60; +} + +// Integer division issued on port 0. +def HWDivider : ProcResource<1>; +// FP division and sqrt on port 0. +def HWFPDivider : ProcResource<1>; + +// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass HWWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 5> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to + // the latency (default = 5). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = !add(UOps, 1); + } +} + +// A folded store needs a cycle on port 4 for the store data, and an extra port +// 2/3/7 cycle to recompute the address. +def : WriteRes; + +// Store_addr on 237. +// Store_data on 4. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +def : WriteRes; + +// Arithmetic. +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; + +def : WriteRes { let Latency = 3; } + +// Integer shifts and rotates. +defm : HWWriteResPair; + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : HWWriteResPair; +defm : HWWriteResPair; + +defm : HWWriteResPair; // Conditional move. +defm : HWWriteResPair; // Conditional (CF + ZF flag) move. +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} +def : WriteRes; +def : WriteRes; + +// This is for simple LEAs with one or two input operands. +// The complex ones can only execute on port 1, and they require two cycles on +// the port to read all inputs. We don't model that. +def : WriteRes; + +// Bit counts. +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; + +// BMI1 BEXTR, BMI2 BZHI +defm : HWWriteResPair; +defm : HWWriteResPair; + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; + +// Scalar and vector floating point. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +// Conversion between integer and float. +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 + +// Vector integer operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; + +// Vector integer shifts. +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // Unsupported = 1 + +// Vector insert/extract operations. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 6; + let NumMicroOps = 2; +} +def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; + +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + +// String instructions. + +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 17; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 19; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} +def : WriteRes { + let Latency = 25; + let NumMicroOps = 10; + let ResourceCycles = [4,3,1,1,1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 17; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [4,3,1]; +} +def : WriteRes { + let Latency = 24; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 1; } + +// AES Instructions. +def : WriteRes { + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 13; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +def : WriteRes { + let Latency = 14; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 20; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} + +def : WriteRes { + let Latency = 29; + let NumMicroOps = 11; + let ResourceCycles = [2,7,2]; +} +def : WriteRes { + let Latency = 34; + let NumMicroOps = 11; + let ResourceCycles = [2,7,1,1]; +} + +// Carry-less multiplication instructions. +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def : WriteRes { + let Latency = 17; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} + +// Load/store MXCSR. +def : WriteRes { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } +def : WriteRes { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } + +def : WriteRes { let Latency = 100; } +def : WriteRes { let Latency = 100; } +def : WriteRes; +def : WriteRes; + +//================ Exceptions ================// + +//-- Specific Scheduling Models --// + +// Starting with P0. +def HWWriteP0 : SchedWriteRes<[HWPort0]>; + +def HWWriteP01 : SchedWriteRes<[HWPort01]>; + +def HWWrite2P01 : SchedWriteRes<[HWPort01]> { + let NumMicroOps = 2; +} +def HWWrite3P01 : SchedWriteRes<[HWPort01]> { + let NumMicroOps = 3; +} + +def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { + let NumMicroOps = 2; +} + +def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { + let NumMicroOps = 3; + let ResourceCycles = [2, 1]; +} + +// Starting with P1. +def HWWriteP1 : SchedWriteRes<[HWPort1]>; + + +def HWWrite2P1 : SchedWriteRes<[HWPort1]> { + let NumMicroOps = 2; + let ResourceCycles = [2]; +} + +// Notation: +// - r: register. +// - mm: 64 bit mmx register. +// - x = 128 bit xmm register. +// - (x)mm = mmx or xmm register. +// - y = 256 bit ymm register. +// - v = any vector register. +// - m = memory. + +//=== Integer Instructions ===// +//-- Move instructions --// + +// XLAT. +def HWWriteXLAT : SchedWriteRes<[]> { + let Latency = 7; + let NumMicroOps = 3; +} +def : InstRW<[HWWriteXLAT], (instrs XLAT)>; + +// PUSHA. +def HWWritePushA : SchedWriteRes<[]> { + let NumMicroOps = 19; +} +def : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>; + +// POPA. +def HWWritePopA : SchedWriteRes<[]> { + let NumMicroOps = 18; +} +def : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>; + +//-- Arithmetic instructions --// + +// DIV. +// r8. +def HWWriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { + let Latency = 22; + let NumMicroOps = 9; +} +def : InstRW<[HWWriteDiv8], (instregex "DIV8r")>; + +// IDIV. +// r8. +def HWWriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { + let Latency = 23; + let NumMicroOps = 9; +} +def : InstRW<[HWWriteIDiv8], (instregex "IDIV8r")>; + +// BT. +// m,r. +def HWWriteBTmr : SchedWriteRes<[]> { + let NumMicroOps = 10; +} +def : InstRW<[HWWriteBTmr], (instregex "BT(16|32|64)mr")>; + +// BTR BTS BTC. +// m,r. +def HWWriteBTRSCmr : SchedWriteRes<[]> { + let NumMicroOps = 11; +} +def : InstRW<[HWWriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>; + +//-- Control transfer instructions --// + +// CALL. +// i. +def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> { + let NumMicroOps = 4; + let ResourceCycles = [1, 2, 1]; +} +def : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>; + +// BOUND. +// r,m. +def HWWriteBOUND : SchedWriteRes<[]> { + let NumMicroOps = 15; +} +def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>; + +// INTO. +def HWWriteINTO : SchedWriteRes<[]> { + let NumMicroOps = 4; +} +def : InstRW<[HWWriteINTO], (instrs INTO)>; + +//-- String instructions --// + +// LODSB/W. +def : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>; + +// LODSD/Q. +def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>; + +// MOVS. +def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> { + let Latency = 4; + let NumMicroOps = 5; + let ResourceCycles = [2, 1, 2]; +} +def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; + +// CMPS. +def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> { + let Latency = 4; + let NumMicroOps = 5; + let ResourceCycles = [2, 3]; +} +def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>; + +//-- Other --// + +// RDPMC.f +def HWWriteRDPMC : SchedWriteRes<[]> { + let NumMicroOps = 34; +} +def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>; + +// RDRAND. +def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> { + let NumMicroOps = 17; + let ResourceCycles = [1, 16]; +} +def : InstRW<[HWWriteRDRAND], (instregex "RDRAND(16|32|64)r")>; + +//=== Floating Point x87 Instructions ===// +//-- Move instructions --// + +// FLD. +// m80. +def : InstRW<[HWWriteP01], (instregex "LD_Frr")>; + +// FBLD. +// m80. +def HWWriteFBLD : SchedWriteRes<[]> { + let Latency = 47; + let NumMicroOps = 43; +} +def : InstRW<[HWWriteFBLD], (instregex "FBLDm")>; + +// FST(P). +// r. +def : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>; + +// FFREE. +def : InstRW<[HWWriteP01], (instregex "FFREE")>; + +// FNSAVE. +def HWWriteFNSAVE : SchedWriteRes<[]> { + let NumMicroOps = 147; +} +def : InstRW<[HWWriteFNSAVE], (instregex "FSAVEm")>; + +// FRSTOR. +def HWWriteFRSTOR : SchedWriteRes<[]> { + let NumMicroOps = 90; +} +def : InstRW<[HWWriteFRSTOR], (instregex "FRSTORm")>; + +//-- Arithmetic instructions --// + +// FCOMPP FUCOMPP. +// r. +def : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>; + +// FCOMI(P) FUCOMI(P). +// m. +def : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; + +// FTST. +def : InstRW<[HWWriteP1], (instregex "TST_F")>; + +// FXAM. +def : InstRW<[HWWrite2P1], (instrs FXAM)>; + +// FPREM. +def HWWriteFPREM : SchedWriteRes<[]> { + let Latency = 19; + let NumMicroOps = 28; +} +def : InstRW<[HWWriteFPREM], (instrs FPREM)>; + +// FPREM1. +def HWWriteFPREM1 : SchedWriteRes<[]> { + let Latency = 27; + let NumMicroOps = 41; +} +def : InstRW<[HWWriteFPREM1], (instrs FPREM1)>; + +// FRNDINT. +def HWWriteFRNDINT : SchedWriteRes<[]> { + let Latency = 11; + let NumMicroOps = 17; +} +def : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>; + +//-- Math instructions --// + +// FSCALE. +def HWWriteFSCALE : SchedWriteRes<[]> { + let Latency = 75; // 49-125 + let NumMicroOps = 50; // 25-75 +} +def : InstRW<[HWWriteFSCALE], (instrs FSCALE)>; + +// FXTRACT. +def HWWriteFXTRACT : SchedWriteRes<[]> { + let Latency = 15; + let NumMicroOps = 17; +} +def : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; + +//=== Floating Point XMM and YMM Instructions ===// + +// Remaining instrs. + +def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSrm", + "(V?)MOVSHDUPrm", + "(V?)MOVSLDUPrm", + "VPBROADCAST(D|Q)rm")>; + +def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> { + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m", + "VBROADCASTF128", + "VBROADCASTI128", + "VBROADCASTSDYrm", + "VBROADCASTSSYrm", + "VMOVDDUPYrm", + "VMOVSHDUPYrm", + "VMOVSLDUPYrm", + "VPBROADCAST(D|Q)Yrm")>; + +def HWWriteResGroup0_2 : SchedWriteRes<[HWPort23]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm16", + "MOVSX(16|32|64)rm32", + "MOVSX(16|32|64)rm8", + "MOVZX(16|32|64)rm16", + "MOVZX(16|32|64)rm8", + "(V?)MOVDDUPrm")>; + +def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup1], (instregex "FBSTPm", + "ST_FP(32|64|80)m", + "VMPTRSTm")>; + +def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr", + "VPSRLVQ(Y?)rr")>; + +def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r", + "UCOM_F(P?)r")>; + +def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVQ2DQrr")>; + +def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>; + +def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>; + +def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>; + +def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr", + "BLSI(32|64)rr", + "BLSMSK(32|64)rr", + "BLSR(32|64)rr")>; + +def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>; + +def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE, + CMC, STC)>; +def: InstRW<[HWWriteResGroup10], (instregex "SGDT64m", + "SIDT64m", + "SMSW16m", + "STRm", + "SYSCALL")>; + +def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup11], (instregex "(V?)CVTPS2PDrm")>; + +def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup11_1], (instregex "(V?)CVTSS2SDrm", + "VPSLLVQrm", + "VPSRLVQrm")>; + +def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup11_2], (instregex "VPSLLVQYrm", + "VPSRLVQYrm")>; + +def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup12], (instregex "MMX_CVTPI2PSirm", + "PDEP(32|64)rm", + "PEXT(32|64)rm")>; + +def HWWriteResGroup12_1 : SchedWriteRes<[HWPort1,HWPort0156,HWPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup12_1], (instrs IMUL16rmi, IMUL16rmi8)>; + +def HWWriteResGroup12_2 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156,HWPort23]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[HWWriteResGroup12_2], (instrs IMUL16m, MUL16m)>; + +def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm", + "(V?)PMOV(SX|ZX)BQrm", + "(V?)PMOV(SX|ZX)BWrm", + "(V?)PMOV(SX|ZX)DQrm", + "(V?)PMOV(SX|ZX)WDrm", + "(V?)PMOV(SX|ZX)WQrm")>; + +def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup13_1], (instregex "VPMOVSXBDYrm", + "VPMOVSXBQYrm", + "VPMOVSXWQYrm")>; + +def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup14], (instregex "FARJMP64", + "JMP(16|32|64)m")>; + +def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort06]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8")>; + +def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm", + "BLSI(32|64)rm", + "BLSMSK(32|64)rm", + "BLSR(32|64)rm", + "MOVBE(16|32|64)rm")>; + +def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup17], (instregex "VINSERTF128rm", + "VINSERTI128rm", + "VPBLENDDrmi")>; + +def HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup17_2], (instregex "VPBLENDDYrmi")>; + +def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>; +def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>; + +def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>; + +def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>; + +def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>; + +def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>; + +def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, + STOSB, STOSL, STOSQ, STOSW)>; +def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr", + "PUSH64i8")>; + +def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup25], (instregex "BTC(16|32|64)mi8", + "BTR(16|32|64)mi8", + "BTS(16|32|64)mi8", + "SAR(8|16|32|64)m1", + "SAR(8|16|32|64)mi", + "SHL(8|16|32|64)m1", + "SHL(8|16|32|64)mi", + "SHR(8|16|32|64)m1", + "SHR(8|16|32|64)mi")>; + +def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm", + "PUSH(16|32|64)rmm")>; + +def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>; + +def HWWriteResGroup29 : SchedWriteRes<[HWPort06]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[HWWriteResGroup29], (instregex "ROL(8|16|32|64)r1", + "ROL(8|16|32|64)ri", + "ROR(8|16|32|64)r1", + "ROR(8|16|32|64)ri")>; + +def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[HWWriteResGroup30], (instrs LFENCE, + MFENCE, + WAIT, + XGETBV)>; + +def HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup31], (instregex "(V?)CVTPS2PDrr", + "(V?)CVTSS2SDrr")>; + +def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>; + +def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup33], (instregex "MMX_MOVDQ2Qrr")>; + +def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>; +def: InstRW<[HWWriteResGroup35], (instregex "SET(A|BE)r")>; + +def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[HWWriteResGroup36_2], (instregex "MMX_PACKSSDWirm", + "MMX_PACKSSWBirm", + "MMX_PACKUSWBirm")>; + +def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64, + SCASB, SCASL, SCASQ, SCASW)>; + +def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>; + +def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup41], (instrs LRETQ, RETL, RETQ)>; + +def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>; + +def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>; +def: InstRW<[HWWriteResGroup45], (instregex "SET(A|BE)m")>; + +def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m1", + "ROL(8|16|32|64)mi", + "ROR(8|16|32|64)m1", + "ROR(8|16|32|64)mi")>; + +def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>; + +def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,1,1]; +} +def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m", + "FARCALL64")>; + +def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPI2PSirr", + "PDEP(32|64)rr", + "PEXT(32|64)rr", + "(V?)CVTDQ2PS(Y?)rr")>; + +def HWWriteResGroup50_16i : SchedWriteRes<[HWPort1, HWPort0156]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup50_16i], (instrs IMUL16rri, IMUL16rri8)>; + +def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>; + +def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup52], (instregex "(V?)CVTPS2DQrm", + "(V?)CVTTPS2DQrm")>; + +def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m", + "ILD_F(16|32|64)m", + "VCVTDQ2PSYrm", + "VCVTPS2DQYrm", + "VCVTTPS2DQYrm")>; + +def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup53_1], (instregex "VPMOVSXBWYrm", + "VPMOVSXDQYrm", + "VPMOVSXWDYrm", + "VPMOVZXWDYrm")>; + +def HWWriteResGroup54 : SchedWriteRes<[HWPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[HWWriteResGroup54], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr, + XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr, + XCHG16ar, XCHG32ar, XCHG64ar)>; + +def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[HWWriteResGroup57], (instregex "MMX_PACKSSDWirr", + "MMX_PACKSSWBirr", + "MMX_PACKUSWBirr")>; + +def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[HWWriteResGroup58], (instregex "CLD")>; + +def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r1", + "RCL(8|16|32|64)ri", + "RCR(8|16|32|64)r1", + "RCR(8|16|32|64)ri")>; + +def HWWriteResGroup60 : SchedWriteRes<[HWPort06,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[HWWriteResGroup60], (instregex "ROL(8|16|32|64)rCL", + "ROR(8|16|32|64)rCL", + "SAR(8|16|32|64)rCL", + "SHL(8|16|32|64)rCL", + "SHR(8|16|32|64)rCL")>; + +def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>; + +def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m", + "IST_F(16|32)m")>; + +def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m1", + "RCL(8|16|32|64)mi", + "RCR(8|16|32|64)m1", + "RCR(8|16|32|64)mi")>; + +def HWWriteResGroup67 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[HWWriteResGroup67], (instregex "ROR(8|16|32|64)mCL")>; + +def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,3]; +} +def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>; + +def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,2,1]; +} +def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG(8|16|32|64)rm", + "ROL(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; +def: SchedAlias; + +def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup70], (instregex "(V?)CVT(T?)SD2SI(64)?rr", + "(V?)CVT(T?)SS2SI(64)?rr")>; + +def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup71], (instregex "VCVTPS2PDYrr")>; + +def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>; + +def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPI2PDirr", + "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", + "(V?)CVTDQ2PDrr", + "(V?)CVTPD2PSrr", + "(V?)CVTSD2SSrr", + "(V?)CVTSI(64)?2SDrr", + "(V?)CVTSI2SSrr", + "(V?)CVT(T?)PD2DQrr")>; + +def HWWriteResGroup74 : SchedWriteRes<[HWPort1,HWPort6]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup74], (instrs IMUL64r, MUL64r, MULX64rr)>; + +def HWWriteResGroup74_16 : SchedWriteRes<[HWPort1, HWPort06, HWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[HWWriteResGroup74_16], (instrs IMUL16r, MUL16r)>; + +def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>; + +def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm", + "(V?)CVTSS2SI(64)?rm", + "(V?)CVTTSD2SI(64)?rm", + "VCVTTSS2SI64rm", + "(V?)CVTTSS2SIrm")>; + +def HWWriteResGroup77 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup77], (instregex "VCVTPS2PDYrm")>; + +def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup78], (instregex "CVTPD2PSrm", + "CVT(T?)PD2DQrm", + "MMX_CVT(T?)PD2PIirm", + "(V?)CVTDQ2PDrm")>; + +def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup78_1], (instregex "MMX_CVTPI2PDirm", + "(V?)CVTSD2SSrm")>; + +def HWWriteResGroup79 : SchedWriteRes<[HWPort1,HWPort6,HWPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup79], (instrs IMUL64m, MUL64m, MULX64rm)>; + +def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>; + +def HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [4]; +} +def: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>; + +def HWWriteResGroup82 : SchedWriteRes<[HWPort015,HWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>; + +def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>; + +def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm", + "LSL(16|32|64)rm")>; + +def HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { + let Latency = 5; + let NumMicroOps = 6; + let ResourceCycles = [1,1,4]; +} +def: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>; + +def HWWriteResGroup89 : SchedWriteRes<[HWPort0]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup89], (instregex "(V?)PCMPGTQ(Y?)rr", + "MUL_(FPrST0|FST0r|FrST0)")>; + +def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>; + +def HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m", + "VPCMPGTQYrm")>; + +def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>; + +def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>; + +def HWWriteResGroup95 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup95], (instrs IMUL32r, MUL32r, MULX32rr)>; + +def HWWriteResGroup97 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> { + let Latency = 10; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup97], (instregex "CVTTSS2SI64rm")>; + +def HWWriteResGroup98 : SchedWriteRes<[HWPort1,HWPort23,HWPort06,HWPort0156]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup98], (instrs IMUL32m, MUL32m, MULX32rm)>; + +def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>; + +def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>; + +def HWWriteResGroup101 : SchedWriteRes<[HWPort06,HWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [2,3]; +} +def: InstRW<[HWWriteResGroup101], (instregex "CMPXCHG(8|16|32|64)rr")>; + +def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup102], (instregex "VCVTDQ2PDYrr", + "VCVTPD2PSYrr", + "VCVT(T?)PD2DQYrr")>; + +def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; + +def HWWriteResGroup104 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup104], (instregex "VCVTDQ2PDYrm")>; + +def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>; + +def HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> { + let Latency = 6; + let NumMicroOps = 6; + let ResourceCycles = [1,5]; +} +def: InstRW<[HWWriteResGroup108], (instrs STD)>; + +def HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> { + let Latency = 7; + let NumMicroOps = 7; + let ResourceCycles = [2,2,1,2]; +} +def: InstRW<[HWWriteResGroup114], (instrs LOOP)>; + +def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { + let Latency = 15; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>; + +def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { + let Latency = 16; + let NumMicroOps = 10; + let ResourceCycles = [1,1,1,4,1,2]; +} +def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>; + +def HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> { + let Latency = 11; + let NumMicroOps = 7; + let ResourceCycles = [2,2,3]; +} +def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL", + "RCR(16|32|64)rCL")>; + +def HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> { + let Latency = 11; + let NumMicroOps = 9; + let ResourceCycles = [1,4,1,3]; +} +def: InstRW<[HWWriteResGroup130], (instregex "RCL8rCL")>; + +def HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> { + let Latency = 11; + let NumMicroOps = 11; + let ResourceCycles = [2,9]; +} +def: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>; + +def HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { + let Latency = 17; + let NumMicroOps = 14; + let ResourceCycles = [1,1,1,4,2,5]; +} +def: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>; + +def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { + let Latency = 19; + let NumMicroOps = 11; + let ResourceCycles = [2,1,1,3,1,3]; +} +def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>; + +def HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> { + let Latency = 14; + let NumMicroOps = 10; + let ResourceCycles = [2,3,1,4]; +} +def: InstRW<[HWWriteResGroup142], (instregex "RCR8rCL")>; + +def HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> { + let Latency = 19; + let NumMicroOps = 15; + let ResourceCycles = [1,14]; +} +def: InstRW<[HWWriteResGroup143], (instregex "POPF16")>; + +def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> { + let Latency = 21; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,1,2]; +} +def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>; + +def HWWriteResGroup145 : SchedWriteRes<[HWPort5]> { + let Latency = 16; + let NumMicroOps = 16; + let ResourceCycles = [16]; +} +def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>; + +def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> { + let Latency = 22; + let NumMicroOps = 19; + let ResourceCycles = [2,1,4,1,1,4,6]; +} +def: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>; + +def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> { + let Latency = 17; + let NumMicroOps = 15; + let ResourceCycles = [2,1,2,4,2,4]; +} +def: InstRW<[HWWriteResGroup147], (instrs XCH_F)>; + +def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,5]; +} +def: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>; + +def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { + let Latency = 23; + let NumMicroOps = 19; + let ResourceCycles = [3,1,15]; +} +def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>; + +def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> { + let Latency = 20; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; + +def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 27; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>; + +def HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> { + let Latency = 20; + let NumMicroOps = 10; + let ResourceCycles = [1,2,7]; +} +def: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>; + +def HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { + let Latency = 30; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>; + +def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> { + let Latency = 24; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; + +def HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 31; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>; + +def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { + let Latency = 30; + let NumMicroOps = 27; + let ResourceCycles = [1,5,1,1,19]; +} +def: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>; + +def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { + let Latency = 31; + let NumMicroOps = 28; + let ResourceCycles = [1,6,1,1,19]; +} +def: InstRW<[HWWriteResGroup165], (instrs XSAVE)>; +def: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; + +def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { + let Latency = 34; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>; + +def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,3,4,10]; +} +def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri", + "IN(8|16|32)rr")>; + +def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> { + let Latency = 36; + let NumMicroOps = 23; + let ResourceCycles = [1,5,2,1,4,10]; +} +def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir", + "OUT(8|16|32)rr")>; + +def HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> { + let Latency = 41; + let NumMicroOps = 18; + let ResourceCycles = [1,1,2,3,1,1,1,8]; +} +def: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>; + +def HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> { + let Latency = 42; + let NumMicroOps = 22; + let ResourceCycles = [2,20]; +} +def: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>; + +def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> { + let Latency = 61; + let NumMicroOps = 64; + let ResourceCycles = [2,2,8,1,10,2,39]; +} +def: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>; + +def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { + let Latency = 64; + let NumMicroOps = 88; + let ResourceCycles = [4,4,31,1,2,1,45]; +} +def: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>; + +def HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { + let Latency = 64; + let NumMicroOps = 90; + let ResourceCycles = [4,2,33,1,2,1,47]; +} +def: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>; + +def HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> { + let Latency = 75; + let NumMicroOps = 15; + let ResourceCycles = [6,3,6]; +} +def: InstRW<[HWWriteResGroup180], (instrs FNINIT)>; + +def HWWriteResGroup181 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> { + let Latency = 98; + let NumMicroOps = 32; + let ResourceCycles = [7,7,3,3,1,11]; +} +def: InstRW<[HWWriteResGroup181], (instregex "DIV(16|32|64)r")>; + +def HWWriteResGroup182 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156]> { + let Latency = 112; + let NumMicroOps = 66; + let ResourceCycles = [4,2,4,8,14,34]; +} +def: InstRW<[HWWriteResGroup182], (instregex "IDIV(16|32|64)r")>; + +def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> { + let Latency = 115; + let NumMicroOps = 100; + let ResourceCycles = [9,9,11,8,1,11,21,30]; +} +def: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>; + +def HWWriteResGroup184 : SchedWriteRes<[HWPort0, HWPort5, HWPort15, HWPort015, HWPort06, HWPort23]> { + let Latency = 26; + let NumMicroOps = 12; + let ResourceCycles = [2,2,1,3,2,2]; +} +def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm, + VPGATHERDQrm, + VPGATHERDDrm)>; + +def HWWriteResGroup185 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 24; + let NumMicroOps = 22; + let ResourceCycles = [5,3,4,1,5,4]; +} +def: InstRW<[HWWriteResGroup185], (instrs VGATHERQPDYrm, + VPGATHERQQYrm)>; + +def HWWriteResGroup186 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 28; + let NumMicroOps = 22; + let ResourceCycles = [5,3,4,1,5,4]; +} +def: InstRW<[HWWriteResGroup186], (instrs VPGATHERQDYrm)>; + +def HWWriteResGroup187 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 25; + let NumMicroOps = 22; + let ResourceCycles = [5,3,4,1,5,4]; +} +def: InstRW<[HWWriteResGroup187], (instrs VPGATHERQDrm)>; + +def HWWriteResGroup188 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 27; + let NumMicroOps = 20; + let ResourceCycles = [3,3,4,1,5,4]; +} +def: InstRW<[HWWriteResGroup188], (instrs VGATHERDPDYrm, + VPGATHERDQYrm)>; + +def HWWriteResGroup189 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 27; + let NumMicroOps = 34; + let ResourceCycles = [5,3,8,1,9,8]; +} +def: InstRW<[HWWriteResGroup189], (instrs VGATHERDPSYrm, + VPGATHERDDYrm)>; + +def HWWriteResGroup190 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 23; + let NumMicroOps = 14; + let ResourceCycles = [3,3,2,1,3,2]; +} +def: InstRW<[HWWriteResGroup190], (instrs VGATHERQPDrm, + VPGATHERQQrm)>; + +def HWWriteResGroup191 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 28; + let NumMicroOps = 15; + let ResourceCycles = [3,3,2,1,4,2]; +} +def: InstRW<[HWWriteResGroup191], (instrs VGATHERQPSYrm)>; + +def HWWriteResGroup192 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { + let Latency = 25; + let NumMicroOps = 15; + let ResourceCycles = [3,3,2,1,4,2]; +} +def: InstRW<[HWWriteResGroup192], (instrs VGATHERQPSrm, + VGATHERDPSrm)>; + +def: InstRW<[WriteZero], (instrs CLC)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedPredicates.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedPredicates.td new file mode 100644 index 0000000..27aaeb1 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedPredicates.td @@ -0,0 +1,49 @@ +//===-- X86SchedPredicates.td - X86 Scheduling Predicates --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines scheduling predicate definitions that are common to +// all X86 subtargets. +// +//===----------------------------------------------------------------------===// + +// A predicate used to identify dependency-breaking instructions that clear the +// content of the destination register. Note that this predicate only checks if +// input registers are the same. This predicate doesn't make any assumptions on +// the expected instruction opcodes, because different processors may implement +// different zero-idioms. +def ZeroIdiomPredicate : CheckSameRegOperand<1, 2>; + +// A predicate used to check if an instruction is a LEA, and if it uses all +// three source operands: base, index, and offset. +def IsThreeOperandsLEAPredicate: CheckAll<[ + CheckOpcode<[LEA32r, LEA64r, LEA64_32r, LEA16r]>, + + // isRegOperand(Base) + CheckIsRegOperand<1>, + CheckNot>, + + // isRegOperand(Index) + CheckIsRegOperand<3>, + CheckNot>, + + // hasLEAOffset(Offset) + CheckAny<[ + CheckAll<[ + CheckIsImmOperand<4>, + CheckNot> + ]>, + CheckNonPortable<"MI.getOperand(4).isGlobal()"> + ]> +]>; + +// This predicate evaluates to true only if the input machine instruction is a +// 3-operands LEA. Tablegen automatically generates a new method for it in +// X86GenInstrInfo. +def IsThreeOperandsLEAFn : + TIIPredicate<"X86", "isThreeOperandsLEA", IsThreeOperandsLEAPredicate>; diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedSandyBridge.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedSandyBridge.td new file mode 100644 index 0000000..6b7bbde --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedSandyBridge.td @@ -0,0 +1,1159 @@ +//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Sandy Bridge to support instruction +// scheduling and other instruction cost heuristics. +// +// Note that we define some instructions here that are not supported by SNB, +// but we still have to define them because SNB is the default subtarget for +// X86. These instructions are tagged with a comment `Unsupported = 1`. +// +//===----------------------------------------------------------------------===// + +def SandyBridgeModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and SB can decode 4 + // instructions per cycle. + // FIXME: Identify instructions that aren't a single fused micro-op. + let IssueWidth = 4; + let MicroOpBufferSize = 168; // Based on the reorder buffer. + let LoadLatency = 5; + let MispredictPenalty = 16; + + // Based on the LSD (loop-stream detector) queue size. + let LoopMicroOpBufferSize = 28; + + // This flag is set to allow the scheduler to assign + // a default model to unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = SandyBridgeModel in { + +// Sandy Bridge can issue micro-ops to 6 different ports in one cycle. + +// Ports 0, 1, and 5 handle all computation. +def SBPort0 : ProcResource<1>; +def SBPort1 : ProcResource<1>; +def SBPort5 : ProcResource<1>; + +// Ports 2 and 3 are identical. They handle loads and the address half of +// stores. +def SBPort23 : ProcResource<2>; + +// Port 4 gets the data half of stores. Store data can be available later than +// the store address, but since we don't model the latency of stores, we can +// ignore that. +def SBPort4 : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; +def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; +def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; +def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; + +// 54 Entry Unified Scheduler +def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> { + let BufferSize=54; +} + +// Integer division issued on port 0. +def SBDivider : ProcResource<1>; +// FP division and sqrt on port 0. +def SBFPDivider : ProcResource<1>; + +// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass SBWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 5> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to + // the latency (default = 5). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = !add(UOps, 1); + } +} + +// A folded store needs a cycle on port 4 for the store data, and an extra port +// 2/3 cycle to recompute the address. +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes { let Latency = 5; } +def : WriteRes; +def : WriteRes; + +// Arithmetic. +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; + +def : WriteRes { let Latency = 3; } + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; + +defm : SBWriteResPair; // Conditional move. +defm : SBWriteResPair; // Conditional (CF + ZF flag) move. +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} +def : WriteRes; +def : WriteRes; + +// This is for simple LEAs with one or two input operands. +// The complex ones can only execute on port 1, and they require two cycles on +// the port to read all inputs. We don't model that. +def : WriteRes; + +// Bit counts. +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; + +// BMI1 BEXTR, BMI2 BZHI +// NOTE: These don't exist on Sandy Bridge. Ports are guesses. +defm : SBWriteResPair; +defm : SBWriteResPair; + +// Scalar and vector floating point. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +// Conversion between integer and float. +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 + +defm : X86WriteRes; +defm : X86WriteRes; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 + +defm : SBWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; // Unsupported = 1 + +// Vector integer operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; // TODO this is probably wrong for 256/512-bit for the "generic" model +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; + +// Vector integer shifts. +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +// Vector insert/extract operations. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 7; + let NumMicroOps = 2; +} + +def : WriteRes { + let Latency = 3; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 5; + let NumMicroOps = 3; +} + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +//////////////////////////////////////////////////////////////////////////////// +// String instructions. +//////////////////////////////////////////////////////////////////////////////// + +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 17; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 11; + let ResourceCycles = [8]; +} +def : WriteRes { + let Latency = 11; + let ResourceCycles = [7, 1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 17; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 4; + let ResourceCycles = [8]; +} +def : WriteRes { + let Latency = 4; + let ResourceCycles = [7, 1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 1; } + +// AES Instructions. +def : WriteRes { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def : WriteRes { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} + +def : WriteRes { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 18; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} + +def : WriteRes { + let Latency = 8; + let ResourceCycles = [11]; +} +def : WriteRes { + let Latency = 8; + let ResourceCycles = [10, 1]; +} + +// Carry-less multiplication instructions. +def : WriteRes { + let Latency = 14; + let ResourceCycles = [18]; +} +def : WriteRes { + let Latency = 14; + let ResourceCycles = [17, 1]; +} + +// Load/store MXCSR. +// FIXME: This is probably wrong. Only STMXCSR should require Port4. +def : WriteRes { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } +def : WriteRes { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } + +def : WriteRes { let Latency = 100; } +def : WriteRes { let Latency = 100; } +def : WriteRes; +def : WriteRes; + +// AVX2/FMA is not supported on that architecture, but we should define the basic +// scheduling resources anyway. +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; // Unsupported = 1 + +// Remaining SNB instrs. + +def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r, + COM_FST0r, + UCOM_FPr, + UCOM_Fr)>; + +def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP, + LD_Frr, ST_Frr, ST_FPrr)>; +def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs. +def: InstRW<[SBWriteResGroup2], (instrs RETQ)>; + +def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>; + +def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABS(B|D|W)rr", + "MMX_PADDQirr", + "MMX_PALIGNRrri", + "MMX_PSIGN(B|D|W)rr")>; + +def SBWriteResGroup9 : SchedWriteRes<[SBPort05]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SBWriteResGroup9], (instregex "ROL(8|16|32|64)r1", + "ROL(8|16|32|64)ri", + "ROR(8|16|32|64)r1", + "ROR(8|16|32|64)ri", + "SET(A|BE)r")>; + +def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SBWriteResGroup11], (instrs SCASB, + SCASL, + SCASQ, + SCASW)>; + +def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup12], (instregex "(V?)COMISDrr", + "(V?)COMISSrr", + "(V?)UCOMISDrr", + "(V?)UCOMISSrr")>; + +def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup15], (instrs CWD, + FNSTSW16r)>; + +def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ)>; +def: InstRW<[SBWriteResGroup18], (instregex "MMX_MOVDQ2Qrr")>; + +def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup21], (instregex "PUSHFS64")>; + +def SBWriteResGroup21_16i : SchedWriteRes<[SBPort1, SBPort015]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup21_16i], (instrs IMUL16rri, IMUL16rri8)>; + +def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> { + let Latency = 3; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>; + +def SBWriteResGroup23_2 : SchedWriteRes<[SBPort05]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SBWriteResGroup23_2], (instregex "ROL(8|16|32|64)rCL", + "ROR(8|16|32|64)rCL", + "SAR(8|16|32|64)rCL", + "SHL(8|16|32|64)rCL", + "SHR(8|16|32|64)rCL")>; + +def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SBWriteResGroup25], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr, + XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr, + XCHG16ar, XCHG32ar, XCHG64ar)>; + +def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>; + +def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; + +def SBWriteResGroup27 : SchedWriteRes<[SBPort0,SBPort1]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup27], (instrs IMUL64r, MUL64r)>; + +def SBWriteResGroup27_1 : SchedWriteRes<[SBPort1,SBPort05,SBPort015]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup27_1], (instrs IMUL32r, MUL32r)>; + +def SBWriteResGroup27_2 : SchedWriteRes<[SBPort1,SBPort05,SBPort015]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup27_2], (instrs IMUL16r, MUL16r)>; + +def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup29], (instregex "MOV64sr")>; + +def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>; + +def SBWriteResGroup30 : SchedWriteRes<[SBPort0]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup30], (instregex "(V?)PCMPGTQrr")>; + +def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm(8|16|32)", + "MOVZX(16|32|64)rm(8|16)")>; + +def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>; + +def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup35], (instrs CLI)>; + +def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m", + "PUSHGS64")>; + +def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>; +def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r", + "(V?)EXTRACTPSmr")>; + +def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>; + +def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>; + +def SBWriteResGroup42 : SchedWriteRes<[SBPort05,SBPort015]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG(8|16|32|64)rr")>; + +def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup43], (instregex "SET(A|BE)m")>; + +def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr", + "PUSHF(16|64)")>; + +def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>; + +def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>; + +def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup48], (instregex "MMX_MOVD64from64rm", + "POP(16|32|64)r", + "VBROADCASTSSrm", + "(V?)MOV64toPQIrm", + "(V?)MOVDDUPrm", + "(V?)MOVDI2PDIrm", + "(V?)MOVQI2PQIrm", + "(V?)MOVSDrm", + "(V?)MOVSHDUPrm", + "(V?)MOVSLDUPrm", + "(V?)MOVSSrm")>; + +def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup49], (instregex "MOV16sm")>; + +def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort05]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup50], (instregex "BT(16|32|64)mi8")>; + +def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABS(B|D|W)rm", + "MMX_PALIGNRrmi", + "MMX_PSIGN(B|D|W)rm")>; + +def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup52], (instrs LODSL, LODSQ)>; + +def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> { + let Latency = 6; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m", + "ST_FP(32|64|80)m")>; + +def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> { + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSDYrm", + "VBROADCASTSSYrm", + "VMOVDDUPYrm", + "VMOVSHDUPYrm", + "VMOVSLDUPYrm")>; + +def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup58], (instrs VINSERTF128rm)>; + +def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup59], (instregex "MMX_PADDQirm")>; + +def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SBWriteResGroup62], (instregex "VER(R|W)m")>; + +def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>; + +def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup64], (instrs FARJMP64)>; + +def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup66], (instrs FNSTSWm)>; + +def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r", + "STR(16|32|64)r")>; + +def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup68], (instrs FNSTCW16m)>; +def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>; + +def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SBWriteResGroup69], (instregex "BTC(16|32|64)mi8", + "BTR(16|32|64)mi8", + "BTS(16|32|64)mi8", + "SAR(8|16|32|64)m1", + "SAR(8|16|32|64)mi", + "SHL(8|16|32|64)m1", + "SHL(8|16|32|64)mi", + "SHR(8|16|32|64)m1", + "SHR(8|16|32|64)mi")>; + +def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>; + +def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 8; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16|32|64)rm")>; + +def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [2,3]; +} +def: InstRW<[SBWriteResGroup83], (instrs CMPSB, + CMPSL, + CMPSQ, + CMPSW)>; + +def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,2,2]; +} +def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>; + +def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,2,2]; +} +def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m1", + "ROL(8|16|32|64)mi", + "ROR(8|16|32|64)m1", + "ROR(8|16|32|64)mi")>; + +def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,2,2]; +} +def: InstRW<[SBWriteResGroup86], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; +def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>; + +def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SBWriteResGroup87], (instrs FARCALL64)>; + +def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)SD2SI(64)?rm", + "CVT(T?)SS2SI(64)?rm")>; + +def SBWriteResGroup93_1 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup93_1], (instrs IMUL64m, MUL64m)>; + +def SBWriteResGroup93_2 : SchedWriteRes<[SBPort1,SBPort23,SBPort05,SBPort015]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SBWriteResGroup93_2], (instrs IMUL32m, MUL32m)>; + +def SBWriteResGroup93_3 : SchedWriteRes<[SBPort1,SBPort05,SBPort015,SBPort23]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[SBWriteResGroup93_3], (instrs IMUL16m, MUL16m)>; + +def SBWriteResGroup93_4 : SchedWriteRes<[SBPort1,SBPort015,SBPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup93_4], (instrs IMUL16rmi, IMUL16rmi8)>; + +def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>; + +def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m", + "IST_FP(16|32|64)m")>; + +def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,2,3]; +} +def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL", + "ROR(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; + +def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,2,3]; +} +def: SchedAlias; + +def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,2,2,1]; +} +def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr, + SBB8mr, SBB16mr, SBB32mr, SBB64mr)>; + +def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,1,2,1,1]; +} +def: InstRW<[SBWriteResGroup100], (instregex "BT(16|32|64)mr", + "BTC(16|32|64)mr", + "BTR(16|32|64)mr", + "BTS(16|32|64)mr")>; + +def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", + "ILD_F(16|32|64)m")>; + +def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>; + +def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>; + +def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m")>; + +def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; + +def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 15; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>; + +def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 31; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>; + +def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 34; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>; + +def: InstRW<[WriteZero], (instrs CLC)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedSkylakeClient.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedSkylakeClient.td new file mode 100644 index 0000000..bda088e --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedSkylakeClient.td @@ -0,0 +1,1850 @@ +//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Skylake Client to support +// instruction scheduling and other instruction cost heuristics. +// +//===----------------------------------------------------------------------===// + +def SkylakeClientModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and SKylake can + // decode 6 instructions per cycle. + let IssueWidth = 6; + let MicroOpBufferSize = 224; // Based on the reorder buffer. + let LoadLatency = 5; + let MispredictPenalty = 14; + + // Based on the LSD (loop-stream detector) queue size and benchmarking data. + let LoopMicroOpBufferSize = 50; + + // This flag is set to allow the scheduler to assign a default model to + // unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = SkylakeClientModel in { + +// Skylake Client can issue micro-ops to 8 different ports in one cycle. + +// Ports 0, 1, 5, and 6 handle all computation. +// Port 4 gets the data half of stores. Store data can be available later than +// the store address, but since we don't model the latency of stores, we can +// ignore that. +// Ports 2 and 3 are identical. They handle loads and the address half of +// stores. Port 7 can handle address calculations. +def SKLPort0 : ProcResource<1>; +def SKLPort1 : ProcResource<1>; +def SKLPort2 : ProcResource<1>; +def SKLPort3 : ProcResource<1>; +def SKLPort4 : ProcResource<1>; +def SKLPort5 : ProcResource<1>; +def SKLPort6 : ProcResource<1>; +def SKLPort7 : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>; +def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>; +def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>; +def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>; +def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>; +def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>; +def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>; +def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>; +def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>; +def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>; +def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>; +def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>; + +def SKLDivider : ProcResource<1>; // Integer division issued on port 0. +// FP division and sqrt on port 0. +def SKLFPDivider : ProcResource<1>; + +// 60 Entry Unified Scheduler +def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4, + SKLPort5, SKLPort6, SKLPort7]> { + let BufferSize=60; +} + +// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass SKLWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 5> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to + // the latency (default = 5). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = !add(UOps, 1); + } +} + +// A folded store needs a cycle on port 4 for the store data, and an extra port +// 2/3/7 cycle to recompute the address. +def : WriteRes; + +// Arithmetic. +defm : SKLWriteResPair; // Simple integer ALU op. +defm : SKLWriteResPair; // Integer ALU + flags op. +defm : SKLWriteResPair; // Integer multiplication. +defm : SKLWriteResPair; // Integer 64-bit multiplication. + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; + +defm : SKLWriteResPair; + +def : WriteRes { let Latency = 3; } // Integer multiplication, high part. +def : WriteRes; // LEA instructions can't fold loads. + +defm : SKLWriteResPair; // Conditional move. +defm : SKLWriteResPair; // Conditional (CF + ZF flag) move. +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} +def : WriteRes; +def : WriteRes; // + +// Bit counts. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; + +// Integer shifts and rotates. +defm : SKLWriteResPair; + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// BMI1 BEXTR, BMI2 BZHI +defm : SKLWriteResPair; +defm : SKLWriteResPair; + +// Loads, stores, and moves, not folded with other operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +def : WriteRes; + +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +defm : SKLWriteResPair; + +// Floating point. This covers both scalar and vector operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKLWriteResPair; // Floating point add/sub. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point double add/sub. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Floating point compare. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point double compare. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Floating point compare to flags. + +defm : SKLWriteResPair; // Floating point multiplication. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point double multiplication. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Floating point division. +//defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +//defm : SKLWriteResPair; // Floating point double division. +//defm : SKLWriteResPair; +//defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Floating point square root. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point double square root. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point long double square root. + +defm : SKLWriteResPair; // Floating point reciprocal estimate. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Floating point reciprocal square root estimate. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Fused Multiply Add. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point double dot product. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point fabs/fchs. +defm : SKLWriteResPair; // Floating point rounding. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point and/or/xor logicals. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point TEST instructions. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point vector shuffles. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point vector shuffles. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Floating point vector blends. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Fp vector variable blends. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +// FMA Scheduling helper class. +// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } + +// Vector integer operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKLWriteResPair; // Vector integer ALU op, no logicals. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector integer and/or/xor. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector integer TEST instructions. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector integer multiply. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector PMULLD. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector shuffles. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector shuffles. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector blends. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector variable blends. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector MPSAD. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector PSADBW. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Vector PHMINPOS. + +// Vector integer shifts. +defm : SKLWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; // Vector integer immediate shifts. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; // Variable vector shifts. +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +// Vector insert/extract operations. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 6; + let NumMicroOps = 2; +} +def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; + +def : WriteRes { + let Latency = 3; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + +// Conversion between integer and float. +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; + +// Strings instructions. + +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 19; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} +def : WriteRes { + let Latency = 25; + let NumMicroOps = 10; + let ResourceCycles = [4,3,1,1,1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [4,3,1]; +} +def : WriteRes { + let Latency = 24; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } + +// AES instructions. +def : WriteRes { // Decryption, encryption. + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +def : WriteRes { // InvMixColumn. + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} + +def : WriteRes { // Key Generation. + let Latency = 20; + let NumMicroOps = 11; + let ResourceCycles = [3,6,2]; +} +def : WriteRes { + let Latency = 25; + let NumMicroOps = 11; + let ResourceCycles = [3,6,1,1]; +} + +// Carry-less multiplication instructions. +def : WriteRes { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +// Catch-all for expensive system instructions. +def : WriteRes { let Latency = 100; } // def WriteSystem : SchedWrite; + +// AVX2. +defm : SKLWriteResPair; // Fp 256-bit width vector shuffles. +defm : SKLWriteResPair; // Fp 256-bit width vector variable shuffles. +defm : SKLWriteResPair; // 256-bit width vector shuffles. +defm : SKLWriteResPair; // 256-bit width vector variable shuffles. + +// Old microcoded instructions that nobody use. +def : WriteRes { let Latency = 100; } // def WriteMicrocoded : SchedWrite; + +// Fence instructions. +def : WriteRes; + +// Load/store MXCSR. +def : WriteRes { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } +def : WriteRes { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } + +// Nop, not very useful expect it provides a model for nops! +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; + +// Remaining instrs. + +def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr", + "MMX_PADDUS(B|W)irr", + "MMX_PAVG(B|W)irr", + "MMX_PCMPEQ(B|D|W)irr", + "MMX_PCMPGT(B|D|W)irr", + "MMX_P(MAX|MIN)SWirr", + "MMX_P(MAX|MIN)UBirr", + "MMX_PSUBS(B|W)irr", + "MMX_PSUBUS(B|W)irr")>; + +def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r", + "UCOM_F(P?)r")>; + +def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>; + +def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>; + +def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; + +def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr", + "BLSI(32|64)rr", + "BLSMSK(32|64)rr", + "BLSR(32|64)rr")>; + +def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr", + "VPBLENDD(Y?)rri", + "(V?)PSUB(B|D|Q|W)(Y?)rr")>; + +def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE, + CMC, STC)>; +def: InstRW<[SKLWriteResGroup10], (instregex "SGDT64m", + "SIDT64m", + "SMSW16m", + "STRm", + "SYSCALL")>; + +def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm", + "ST_FP(32|64|80)m", + "VMPTRSTm")>; + +def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>; + +def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP)>; +def: InstRW<[SKLWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>; + +def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKLWriteResGroup15], (instregex "ROL(8|16|32|64)r1", + "ROL(8|16|32|64)ri", + "ROR(8|16|32|64)r1", + "ROR(8|16|32|64)ri", + "SET(A|BE)r")>; + +def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKLWriteResGroup17], (instrs LFENCE, + WAIT, + XGETBV)>; + +def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>; + +def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>; + +def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup23], (instrs CWD)>; +def: InstRW<[SKLWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>; +def: InstRW<[SKLWriteResGroup23], (instregex "ADC8i8", + "ADC8ri", + "SBB8i8", + "SBB8ri")>; + +def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>; + +def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; + +def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, + STOSB, STOSL, STOSQ, STOSW)>; +def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr", + "PUSH64i8")>; + +def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr", + "PEXT(32|64)rr")>; + +def SKLWriteResGroup29_16i : SchedWriteRes<[SKLPort1, SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup29_16i], (instrs IMUL16rri, IMUL16rri8)>; + +def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", + "VPBROADCASTBrr", + "VPBROADCASTWrr", + "(V?)PCMPGTQ(Y?)rr")>; + +def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>; + +def SKLWriteResGroup33 : SchedWriteRes<[SKLPort06]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SKLWriteResGroup33], (instregex "ROL(8|16|32|64)rCL", + "ROR(8|16|32|64)rCL", + "SAR(8|16|32|64)rCL", + "SHL(8|16|32|64)rCL", + "SHR(8|16|32|64)rCL")>; + +def SKLWriteResGroup34 : SchedWriteRes<[SKLPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SKLWriteResGroup34], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr, + XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr, + XCHG16ar, XCHG32ar, XCHG64ar)>; + +def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>; + +def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr", + "(V?)PHSUBSW(Y?)rr")>; + +def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKSSDWirr", + "MMX_PACKSSWBirr", + "MMX_PACKUSWBirr")>; + +def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>; + +def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>; + +def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r1", + "RCL(8|16|32|64)ri", + "RCR(8|16|32|64)r1", + "RCR(8|16|32|64)ri")>; + +def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>; + +def SKLWriteResGroup44 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SKLWriteResGroup44], (instregex "SET(A|BE)m")>; + +def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>; + +def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>; + +def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; + +def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr", + "(V?)CVT(T?)PS2DQ(Y?)rr")>; + +def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup51], (instrs IMUL64r, MUL64r, MULX64rr)>; + +def SKLWriteResGroup51_16 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SKLWriteResGroup51_16], (instrs IMUL16r, MUL16r)>; + +def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m", + "IST_F(16|32)m")>; + +def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [4]; +} +def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>; + +def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>; + +def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>; + +def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>; + +def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm16", + "MOVSX(16|32|64)rm32", + "MOVSX(16|32|64)rm8", + "MOVZX(16|32|64)rm16", + "MOVZX(16|32|64)rm8", + "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67? + +def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup59], (instregex "MMX_CVTPI2PDirr", + "(V?)CVTDQ2PDrr")>; + +def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", + "(V?)CVT(T?)PD2DQrr", + "(V?)CVTPD2PSrr", + "(V?)CVTPS2PDrr", + "(V?)CVTSD2SSrr", + "(V?)CVTSI642SDrr", + "(V?)CVTSI2SDrr", + "(V?)CVTSI2SSrr", + "(V?)CVTSS2SDrr")>; + +def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>; + +def SKLWriteResGroup62 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup62], (instrs IMUL32r, MUL32r, MULX32rr)>; + +def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>; + +def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [2,3]; +} +def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(8|16|32|64)rr")>; + +def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { + let Latency = 5; + let NumMicroOps = 6; + let ResourceCycles = [1,1,4]; +} +def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>; + +def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup67], (instregex "VBROADCASTSSrm", + "(V?)MOVSHDUPrm", + "(V?)MOVSLDUPrm", + "VPBROADCASTDrm", + "VPBROADCASTQrm")>; + +def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKLWriteResGroup68], (instregex "MMX_CVTPI2PSirr")>; + +def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm", + "MMX_PADDSWirm", + "MMX_PADDUSBirm", + "MMX_PADDUSWirm", + "MMX_PAVGBirm", + "MMX_PAVGWirm", + "MMX_PCMPEQBirm", + "MMX_PCMPEQDirm", + "MMX_PCMPEQWirm", + "MMX_PCMPGTBirm", + "MMX_PCMPGTDirm", + "MMX_PCMPGTWirm", + "MMX_PMAXSWirm", + "MMX_PMAXUBirm", + "MMX_PMINSWirm", + "MMX_PMINUBirm", + "MMX_PSUBSBirm", + "MMX_PSUBSWirm", + "MMX_PSUBUSBirm", + "MMX_PSUBUSWirm")>; + +def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr", + "(V?)CVT(T?)SD2SI(64)?rr")>; + +def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup72], (instregex "FARJMP64", + "JMP(16|32|64)m")>; + +def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>; + +def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm", + "BLSI(32|64)rm", + "BLSMSK(32|64)rm", + "BLSR(32|64)rm", + "MOVBE(16|32|64)rm")>; + +def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>; +def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>; + +def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> { + let Latency = 6; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>; + +def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>; + +def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup82], (instregex "BTC(16|32|64)mi8", + "BTR(16|32|64)mi8", + "BTS(16|32|64)mi8", + "SAR(8|16|32|64)m1", + "SAR(8|16|32|64)mi", + "SHL(8|16|32|64)m1", + "SHL(8|16|32|64)mi", + "SHR(8|16|32|64)m1", + "SHR(8|16|32|64)mi")>; + +def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm", + "PUSH(16|32|64)rmm")>; + +def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> { + let Latency = 6; + let NumMicroOps = 6; + let ResourceCycles = [1,5]; +} +def: InstRW<[SKLWriteResGroup84], (instrs STD)>; + +def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> { + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m", + "VBROADCASTF128", + "VBROADCASTI128", + "VBROADCASTSDYrm", + "VBROADCASTSSYrm", + "VMOVDDUPYrm", + "VMOVSHDUPYrm", + "VMOVSLDUPYrm", + "VPBROADCASTDYrm", + "VPBROADCASTQYrm")>; + +def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup86], (instregex "VCVTDQ2PDYrr")>; + +def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm", + "(V?)PMOV(SX|ZX)BQrm", + "(V?)PMOV(SX|ZX)BWrm", + "(V?)PMOV(SX|ZX)DQrm", + "(V?)PMOV(SX|ZX)WDrm", + "(V?)PMOV(SX|ZX)WQrm")>; + +def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2PSYrr", + "VCVTPS2PDYrr", + "VCVT(T?)PD2DQYrr")>; + +def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup91], (instregex "(V?)INSERTF128rm", + "(V?)INSERTI128rm", + "(V?)PADD(B|D|Q|W)rm", + "(V?)PBLENDDrmi", + "(V?)PSUB(B|D|Q|W)rm")>; + +def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSDWirm", + "MMX_PACKSSWBirm", + "MMX_PACKUSWBirm")>; + +def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64, + SCASB, SCASL, SCASQ, SCASW)>; + +def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>; + +def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>; + +def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>; + +def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m1", + "ROL(8|16|32|64)mi", + "ROR(8|16|32|64)m1", + "ROR(8|16|32|64)mi")>; + +def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>; + +def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m", + "FARCALL64")>; + +def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 7; + let NumMicroOps = 7; + let ResourceCycles = [1,3,1,2]; +} +def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>; + +def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm", + "PEXT(32|64)rm")>; + +def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup107_16], (instrs IMUL16rmi, IMUL16rmi8)>; + +def SKLWriteResGroup107_16_2 : SchedWriteRes<[SKLPort1, SKLPort06, SKLPort0156, SKLPort23]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[SKLWriteResGroup107_16_2], (instrs IMUL16m, MUL16m)>; + +def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m", + "VPBROADCASTBYrm", + "VPBROADCASTWYrm", + "VPMOVSXBDYrm", + "VPMOVSXBQYrm", + "VPMOVSXWQYrm")>; + +def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup110], (instregex "VPADD(B|D|Q|W)Yrm", + "VPBLENDDYrmi", + "VPSUB(B|D|Q|W)Yrm")>; + +def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 8; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>; + +def SKLWriteResGroup115 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,3]; +} +def: InstRW<[SKLWriteResGroup115], (instregex "ROR(8|16|32|64)mCL")>; + +def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m1", + "RCL(8|16|32|64)mi", + "RCR(8|16|32|64)m1", + "RCR(8|16|32|64)mi")>; + +def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,3]; +} +def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; + +def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,2,1]; +} +def: SchedAlias; +def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(8|16|32|64)rm")>; + +def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm")>; + +def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup121], (instregex "(V?)PCMPGTQrm", + "VPMOVSXBWYrm", + "VPMOVSXDQYrm", + "VPMOVSXWDYrm", + "VPMOVZXWDYrm")>; + +def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm", + "(V?)CVTPS2PDrm")>; + +def SKLWriteResGroup127 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup127], (instrs IMUL64m, MUL64m, MULX64rm)>; + +def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm", + "(V?)PHSUBSWrm")>; + +def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm", + "LSL(16|32|64)rm")>; + +def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m", + "ILD_F(16|32|64)m", + "VPCMPGTQYrm")>; + +def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm", + "(V?)CVTPS2DQrm", + "(V?)CVTSS2SDrm", + "(V?)CVTTPS2DQrm")>; + +def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm")>; + +def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>; + +def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { + let Latency = 10; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKLWriteResGroup140], (instregex "VPHADDSWYrm", + "VPHSUBSWYrm")>; + +def SKLWriteResGroup142 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort06,SKLPort0156]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup142], (instrs IMUL32m, MUL32m, MULX32rm)>; + +def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 10; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,3]; +} +def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>; + +def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { + let Latency = 11; + let NumMicroOps = 1; + let ResourceCycles = [1,3]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>; + +def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup147], (instregex "VCVTDQ2PSYrm", + "VCVTPS2PDYrm", + "VCVT(T?)PS2DQYrm")>; + +def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>; + +def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>; + +def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm", + "(V?)CVT(T?)SD2SI(64)?rm", + "VCVTTSS2SI64rm", + "(V?)CVT(T?)SS2SIrm")>; + +def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2PSrm", + "CVT(T?)PD2DQrm", + "MMX_CVT(T?)PD2PIirm")>; + +def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { + let Latency = 11; + let NumMicroOps = 7; + let ResourceCycles = [2,3,2]; +} +def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL", + "RCR(16|32|64)rCL")>; + +def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 11; + let NumMicroOps = 9; + let ResourceCycles = [1,5,1,2]; +} +def: InstRW<[SKLWriteResGroup155], (instregex "RCL8rCL")>; + +def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> { + let Latency = 11; + let NumMicroOps = 11; + let ResourceCycles = [2,9]; +} +def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>; + +def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> { + let Latency = 12; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>; + +def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; + +def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup163], (instregex "VCVTDQ2PDYrm")>; + +def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1,3]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1,5]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>; + +def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 14; + let NumMicroOps = 10; + let ResourceCycles = [2,4,1,3]; +} +def: InstRW<[SKLWriteResGroup170], (instregex "RCR8rCL")>; + +def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> { + let Latency = 15; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; + +def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 15; + let NumMicroOps = 10; + let ResourceCycles = [1,1,1,5,1,1]; +} +def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>; + +def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 16; + let NumMicroOps = 14; + let ResourceCycles = [1,1,1,4,2,5]; +} +def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>; + +def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> { + let Latency = 16; + let NumMicroOps = 16; + let ResourceCycles = [16]; +} +def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>; + +def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { + let Latency = 17; + let NumMicroOps = 2; + let ResourceCycles = [1,1,5]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> { + let Latency = 17; + let NumMicroOps = 15; + let ResourceCycles = [2,1,2,4,2,4]; +} +def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>; + +def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,5]; +} +def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>; + +def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 18; + let NumMicroOps = 11; + let ResourceCycles = [2,1,1,4,1,2]; +} +def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>; + +def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { + let Latency = 19; + let NumMicroOps = 2; + let ResourceCycles = [1,1,4]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> { + let Latency = 20; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; + +def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { + let Latency = 20; + let NumMicroOps = 2; + let ResourceCycles = [1,1,4]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 20; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,1,2]; +} +def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>; + +def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> { + let Latency = 20; + let NumMicroOps = 10; + let ResourceCycles = [1,2,7]; +} +def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>; + +def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { + let Latency = 21; + let NumMicroOps = 2; + let ResourceCycles = [1,1,8]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> { + let Latency = 22; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>; + +def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { + let Latency = 22; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm, + VGATHERDPDrm, + VGATHERQPDrm, + VGATHERQPSrm, + VPGATHERDDrm, + VPGATHERDQrm, + VPGATHERQDrm, + VPGATHERQQrm)>; + +def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { + let Latency = 25; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm, + VGATHERQPDYrm, + VGATHERQPSYrm, + VPGATHERDDYrm, + VPGATHERDQYrm, + VPGATHERQDYrm, + VPGATHERQQYrm, + VGATHERDPDYrm)>; + +def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 23; + let NumMicroOps = 19; + let ResourceCycles = [2,1,4,1,1,4,6]; +} +def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>; + +def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 25; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>; + +def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> { + let Latency = 27; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>; + +def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> { + let Latency = 28; + let NumMicroOps = 8; + let ResourceCycles = [2,4,1,1]; +} +def: InstRW<[SKLWriteResGroup207], (instregex "IDIV(8|16|32|64)m")>; + +def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { + let Latency = 30; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>; + +def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,3,4,10]; +} +def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri", + "IN(8|16|32)rr")>; + +def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,2,1,4,10]; +} +def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir", + "OUT(8|16|32)rr")>; + +def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { + let Latency = 37; + let NumMicroOps = 31; + let ResourceCycles = [1,8,1,21]; +} +def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>; + +def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> { + let Latency = 40; + let NumMicroOps = 18; + let ResourceCycles = [1,1,2,3,1,1,1,8]; +} +def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>; + +def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { + let Latency = 41; + let NumMicroOps = 39; + let ResourceCycles = [1,10,1,1,26]; +} +def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>; + +def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> { + let Latency = 42; + let NumMicroOps = 22; + let ResourceCycles = [2,20]; +} +def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>; + +def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { + let Latency = 42; + let NumMicroOps = 40; + let ResourceCycles = [1,11,1,1,26]; +} +def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>; +def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>; + +def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { + let Latency = 46; + let NumMicroOps = 44; + let ResourceCycles = [1,11,1,1,30]; +} +def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>; + +def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> { + let Latency = 62; + let NumMicroOps = 64; + let ResourceCycles = [2,8,5,10,39]; +} +def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>; + +def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 63; + let NumMicroOps = 88; + let ResourceCycles = [4,4,31,1,2,1,45]; +} +def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>; + +def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { + let Latency = 63; + let NumMicroOps = 90; + let ResourceCycles = [4,2,33,1,2,1,47]; +} +def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>; + +def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> { + let Latency = 75; + let NumMicroOps = 15; + let ResourceCycles = [6,3,6]; +} +def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>; + +def SKLWriteResGroup221 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> { + let Latency = 76; + let NumMicroOps = 32; + let ResourceCycles = [7,2,8,3,1,11]; +} +def: InstRW<[SKLWriteResGroup221], (instregex "DIV(16|32|64)r")>; + +def SKLWriteResGroup222 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> { + let Latency = 102; + let NumMicroOps = 66; + let ResourceCycles = [4,2,4,8,14,34]; +} +def: InstRW<[SKLWriteResGroup222], (instregex "IDIV(16|32|64)r")>; + +def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> { + let Latency = 106; + let NumMicroOps = 100; + let ResourceCycles = [9,1,11,16,1,11,21,30]; +} +def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>; + +def: InstRW<[WriteZero], (instrs CLC)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedSkylakeServer.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedSkylakeServer.td new file mode 100644 index 0000000..9d5f855 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86SchedSkylakeServer.td @@ -0,0 +1,2580 @@ +//=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Skylake Server to support +// instruction scheduling and other instruction cost heuristics. +// +//===----------------------------------------------------------------------===// + +def SkylakeServerModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and SKylake can + // decode 6 instructions per cycle. + let IssueWidth = 6; + let MicroOpBufferSize = 224; // Based on the reorder buffer. + let LoadLatency = 5; + let MispredictPenalty = 14; + + // Based on the LSD (loop-stream detector) queue size and benchmarking data. + let LoopMicroOpBufferSize = 50; + + // This flag is set to allow the scheduler to assign a default model to + // unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = SkylakeServerModel in { + +// Skylake Server can issue micro-ops to 8 different ports in one cycle. + +// Ports 0, 1, 5, and 6 handle all computation. +// Port 4 gets the data half of stores. Store data can be available later than +// the store address, but since we don't model the latency of stores, we can +// ignore that. +// Ports 2 and 3 are identical. They handle loads and the address half of +// stores. Port 7 can handle address calculations. +def SKXPort0 : ProcResource<1>; +def SKXPort1 : ProcResource<1>; +def SKXPort2 : ProcResource<1>; +def SKXPort3 : ProcResource<1>; +def SKXPort4 : ProcResource<1>; +def SKXPort5 : ProcResource<1>; +def SKXPort6 : ProcResource<1>; +def SKXPort7 : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def SKXPort01 : ProcResGroup<[SKXPort0, SKXPort1]>; +def SKXPort23 : ProcResGroup<[SKXPort2, SKXPort3]>; +def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>; +def SKXPort04 : ProcResGroup<[SKXPort0, SKXPort4]>; +def SKXPort05 : ProcResGroup<[SKXPort0, SKXPort5]>; +def SKXPort06 : ProcResGroup<[SKXPort0, SKXPort6]>; +def SKXPort15 : ProcResGroup<[SKXPort1, SKXPort5]>; +def SKXPort16 : ProcResGroup<[SKXPort1, SKXPort6]>; +def SKXPort56 : ProcResGroup<[SKXPort5, SKXPort6]>; +def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>; +def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>; +def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>; + +def SKXDivider : ProcResource<1>; // Integer division issued on port 0. +// FP division and sqrt on port 0. +def SKXFPDivider : ProcResource<1>; + +// 60 Entry Unified Scheduler +def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4, + SKXPort5, SKXPort6, SKXPort7]> { + let BufferSize=60; +} + +// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass SKXWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 5> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to + // the latency (default = 5). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = !add(UOps, 1); + } +} + +// A folded store needs a cycle on port 4 for the store data, and an extra port +// 2/3/7 cycle to recompute the address. +def : WriteRes; + +// Arithmetic. +defm : SKXWriteResPair; // Simple integer ALU op. +defm : SKXWriteResPair; // Integer ALU + flags op. +defm : SKXWriteResPair; // Integer multiplication. +defm : SKXWriteResPair; // Integer 64-bit multiplication. + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; + +def : WriteRes { let Latency = 3; } // Integer multiplication, high part. +def : WriteRes; // LEA instructions can't fold loads. + +defm : SKXWriteResPair; // Conditional move. +defm : SKXWriteResPair; // Conditional (CF + ZF flag) move. +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} +def : WriteRes; +def : WriteRes; // + +// Integer shifts and rotates. +defm : SKXWriteResPair; + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Bit counts. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +// BMI1 BEXTR, BMI2 BZHI +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +// Loads, stores, and moves, not folded with other operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +def : WriteRes; + +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +defm : SKXWriteResPair; + +// Floating point. This covers both scalar and vector operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKXWriteResPair; // Floating point add/sub. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point double add/sub. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; // Floating point compare. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point double compare. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; // Floating point compare to flags. + +defm : SKXWriteResPair; // Floating point multiplication. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point double multiplication. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; // 10-14 cycles. // Floating point division. +//defm : SKXWriteResPair; // 10-14 cycles. +defm : SKXWriteResPair; // 10-14 cycles. +defm : SKXWriteResPair; // 10-14 cycles. +//defm : SKXWriteResPair; // 10-14 cycles. // Floating point division. +//defm : SKXWriteResPair; // 10-14 cycles. +//defm : SKXWriteResPair; // 10-14 cycles. +defm : SKXWriteResPair; // 10-14 cycles. + +defm : SKXWriteResPair; // Floating point square root. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point double square root. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point long double square root. + +defm : SKXWriteResPair; // Floating point reciprocal estimate. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; // Floating point reciprocal square root estimate. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; // Fused Multiply Add. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point double dot product. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point fabs/fchs. +defm : SKXWriteResPair; // Floating point rounding. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point and/or/xor logicals. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point TEST instructions. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point vector shuffles. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point vector variable shuffles. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Floating point vector blends. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Fp vector variable blends. +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +// FMA Scheduling helper class. +// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } + +// Vector integer operations. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKXWriteResPair; // Vector integer ALU op, no logicals. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector integer and/or/xor. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector integer TEST instructions. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector integer multiply. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector PMULLD. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector shuffles. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector variable shuffles. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector blends. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector variable blends. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector MPSAD. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector PSADBW. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector PHMINPOS. + +// Vector integer shifts. +defm : SKXWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector integer immediate shifts. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Variable vector shifts. +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +// Vector insert/extract operations. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 6; + let NumMicroOps = 2; +} +def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; + +def : WriteRes { + let Latency = 3; + let NumMicroOps = 2; +} +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + +// Conversion between integer and float. +defm : SKXWriteResPair; // Needs more work: DD vs DQ. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // Needs more work: DD vs DQ. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +// Strings instructions. + +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 19; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} +def : WriteRes { + let Latency = 25; + let NumMicroOps = 10; + let ResourceCycles = [4,3,1,1,1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def : WriteRes { + let Latency = 16; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [4,3,1]; +} +def : WriteRes { + let Latency = 24; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 2; } + +// AES instructions. +def : WriteRes { // Decryption, encryption. + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +def : WriteRes { // InvMixColumn. + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} + +def : WriteRes { // Key Generation. + let Latency = 20; + let NumMicroOps = 11; + let ResourceCycles = [3,6,2]; +} +def : WriteRes { + let Latency = 25; + let NumMicroOps = 11; + let ResourceCycles = [3,6,1,1]; +} + +// Carry-less multiplication instructions. +def : WriteRes { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def : WriteRes { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} + +// Catch-all for expensive system instructions. +def : WriteRes { let Latency = 100; } // def WriteSystem : SchedWrite; + +// AVX2. +defm : SKXWriteResPair; // Fp 256-bit width vector shuffles. +defm : SKXWriteResPair; // Fp 256-bit width vector variable shuffles. +defm : SKXWriteResPair; // 256-bit width vector shuffles. +defm : SKXWriteResPair; // 256-bit width vector variable shuffles. + +// Old microcoded instructions that nobody use. +def : WriteRes { let Latency = 100; } // def WriteMicrocoded : SchedWrite; + +// Fence instructions. +def : WriteRes; + +// Load/store MXCSR. +def : WriteRes { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } +def : WriteRes { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } + +// Nop, not very useful expect it provides a model for nops! +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; + +// Remaining instrs. + +def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr", + "KANDN(B|D|Q|W)rr", + "KMOV(B|D|Q|W)kk", + "KNOT(B|D|Q|W)rr", + "KOR(B|D|Q|W)rr", + "KXNOR(B|D|Q|W)rr", + "KXOR(B|D|Q|W)rr", + "MMX_PADDS(B|W)irr", + "MMX_PADDUS(B|W)irr", + "MMX_PAVG(B|W)irr", + "MMX_PCMPEQ(B|D|W)irr", + "MMX_PCMPGT(B|D|W)irr", + "MMX_P(MAX|MIN)SWirr", + "MMX_P(MAX|MIN)UBirr", + "MMX_PSUBS(B|W)irr", + "MMX_PSUBUS(B|W)irr", + "VPMOVB2M(Z|Z128|Z256)rr", + "VPMOVD2M(Z|Z128|Z256)rr", + "VPMOVQ2M(Z|Z128|Z256)rr", + "VPMOVW2M(Z|Z128|Z256)rr")>; + +def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r", + "KMOV(B|D|Q|W)kr", + "UCOM_F(P?)r")>; + +def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>; + +def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>; + +def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; + +def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr", + "BLSI(32|64)rr", + "BLSMSK(32|64)rr", + "BLSR(32|64)rr")>; + +def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr", + "VBLENDMPS(Z128|Z256)rr", + "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr", + "(V?)PADD(B|D|Q|W)rr", + "VPBLENDD(Y?)rri", + "VPBLENDMB(Z128|Z256)rr", + "VPBLENDMD(Z128|Z256)rr", + "VPBLENDMQ(Z128|Z256)rr", + "VPBLENDMW(Z128|Z256)rr", + "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rr", + "(V?)PSUB(B|D|Q|W)rr", + "VPTERNLOGD(Z|Z128|Z256)rri", + "VPTERNLOGQ(Z|Z128|Z256)rri")>; + +def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE, + CMC, STC)>; +def: InstRW<[SKXWriteResGroup10], (instregex "SGDT64m", + "SIDT64m", + "SMSW16m", + "STRm", + "SYSCALL")>; + +def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup11], (instregex "FBSTPm", + "KMOV(B|D|Q|W)mk", + "ST_FP(32|64|80)m", + "VMPTRSTm")>; + +def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>; + +def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP)>; +def: InstRW<[SKXWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>; + +def SKXWriteResGroup15 : SchedWriteRes<[SKXPort06]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup15], (instregex "ROL(8|16|32|64)r1", + "ROL(8|16|32|64)ri", + "ROR(8|16|32|64)r1", + "ROR(8|16|32|64)ri", + "SET(A|BE)r")>; + +def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup17], (instrs LFENCE, + WAIT, + XGETBV)>; + +def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>; + +def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>; + +def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup23], (instrs CWD)>; +def: InstRW<[SKXWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>; +def: InstRW<[SKXWriteResGroup23], (instregex "ADC8i8", + "ADC8ri", + "SBB8i8", + "SBB8ri")>; + +def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>; + +def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; + +def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, + STOSB, STOSL, STOSQ, STOSW)>; +def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr", + "PUSH64i8")>; + +def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { + let Latency = 2; + let NumMicroOps = 5; + let ResourceCycles = [2,2,1]; +} +def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>; + +def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk", + "KORTEST(B|D|Q|W)rr", + "KTEST(B|D|Q|W)rr")>; + +def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr", + "PEXT(32|64)rr")>; + +def SKXWriteResGroup31_16i : SchedWriteRes<[SKXPort1, SKXPort0156]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup31_16i], (instrs IMUL16rri, IMUL16rri8)>; + + +def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", + "KADD(B|D|Q|W)rr", + "KSHIFTL(B|D|Q|W)ri", + "KSHIFTR(B|D|Q|W)ri", + "KUNPCKBWrr", + "KUNPCKDQrr", + "KUNPCKWDrr", + "VALIGND(Z|Z128|Z256)rri", + "VALIGNQ(Z|Z128|Z256)rri", + "VCMPPD(Z|Z128|Z256)rri", + "VCMPPS(Z|Z128|Z256)rri", + "VCMPSDZrr", + "VCMPSSZrr", + "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined. + "VFPCLASSPD(Z|Z128|Z256)rr", + "VFPCLASSPS(Z|Z128|Z256)rr", + "VFPCLASSSDZrr", + "VFPCLASSSSZrr", + "VPBROADCASTBrr", + "VPBROADCASTWrr", + "VPCMPB(Z|Z128|Z256)rri", + "VPCMPD(Z|Z128|Z256)rri", + "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr", + "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr", + "(V?)PCMPGTQ(Y?)rr", + "VPCMPQ(Z|Z128|Z256)rri", + "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri", + "VPCMPW(Z|Z128|Z256)rri", + "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr", + "VPSADBWZrr", // TODO: 512-bit ops require ports 0/1 to be joined. + "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>; + +def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>; + +def SKXWriteResGroup35 : SchedWriteRes<[SKXPort06]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SKXWriteResGroup35], (instregex "ROL(8|16|32|64)rCL", + "ROR(8|16|32|64)rCL", + "SAR(8|16|32|64)rCL", + "SHL(8|16|32|64)rCL", + "SHR(8|16|32|64)rCL")>; + +def SKXWriteResGroup36 : SchedWriteRes<[SKXPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SKXWriteResGroup36], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr, + XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr, + XCHG16ar, XCHG32ar, XCHG64ar)>; + +def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>; + +def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>; + +def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup41], (instregex "MMX_PACKSSDWirr", + "MMX_PACKSSWBirr", + "MMX_PACKUSWBirr")>; + +def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>; + +def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>; + +def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r1", + "RCL(8|16|32|64)ri", + "RCR(8|16|32|64)r1", + "RCR(8|16|32|64)ri")>; + +def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>; + +def SKXWriteResGroup46 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SKXWriteResGroup46], (instregex "SET(A|BE)m")>; + +def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>; + +def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 3; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>; + +def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; + +def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr", + "(V?)CVTDQ2PSrr", + "VCVTPD2QQ(Z128|Z256)rr", + "VCVTPD2UQQ(Z128|Z256)rr", + "VCVTPS2DQ(Y|Z128|Z256)rr", + "(V?)CVTPS2DQrr", + "VCVTPS2UDQ(Z128|Z256)rr", + "VCVTQQ2PD(Z128|Z256)rr", + "VCVTTPD2QQ(Z128|Z256)rr", + "VCVTTPD2UQQ(Z128|Z256)rr", + "VCVTTPS2DQ(Z128|Z256)rr", + "(V?)CVTTPS2DQrr", + "VCVTTPS2UDQ(Z128|Z256)rr", + "VCVTUDQ2PS(Z128|Z256)rr", + "VCVTUQQ2PD(Z128|Z256)rr")>; + +def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> { + let Latency = 4; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr, + VCVTPD2QQZrr, + VCVTPD2UQQZrr, + VCVTPS2DQZrr, + VCVTPS2UDQZrr, + VCVTQQ2PDZrr, + VCVTTPD2QQZrr, + VCVTTPD2UQQZrr, + VCVTTPS2DQZrr, + VCVTTPS2UDQZrr, + VCVTUDQ2PSZrr, + VCVTUQQ2PDZrr)>; + +def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr", + "VEXPANDPS(Z|Z128|Z256)rr", + "VPEXPANDD(Z|Z128|Z256)rr", + "VPEXPANDQ(Z|Z128|Z256)rr", + "VPMOVDB(Z|Z128|Z256)rr", + "VPMOVDW(Z|Z128|Z256)rr", + "VPMOVQB(Z|Z128|Z256)rr", + "VPMOVQW(Z|Z128|Z256)rr", + "VPMOVSDB(Z|Z128|Z256)rr", + "VPMOVSDW(Z|Z128|Z256)rr", + "VPMOVSQB(Z|Z128|Z256)rr", + "VPMOVSQD(Z|Z128|Z256)rr", + "VPMOVSQW(Z|Z128|Z256)rr", + "VPMOVSWB(Z|Z128|Z256)rr", + "VPMOVUSDB(Z|Z128|Z256)rr", + "VPMOVUSDW(Z|Z128|Z256)rr", + "VPMOVUSQB(Z|Z128|Z256)rr", + "VPMOVUSQD(Z|Z128|Z256)rr", + "VPMOVUSWB(Z|Z128|Z256)rr", + "VPMOVWB(Z|Z128|Z256)rr")>; + +def SKXWriteResGroup52 : SchedWriteRes<[SKXPort1,SKXPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup52], (instrs IMUL64r, MUL64r, MULX64rr)>; + +def SKXWriteResGroup52_16 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SKXWriteResGroup52_16], (instrs IMUL16r, MUL16r)>; + +def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m", + "IST_F(16|32)m", + "VPMOVQD(Z|Z128|Z256)mr(b?)")>; + +def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [4]; +} +def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>; + +def SKXWriteResGroup56 : SchedWriteRes<[SKXPort015,SKXPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>; + +def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>; + +def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm16", + "MOVSX(16|32|64)rm32", + "MOVSX(16|32|64)rm8", + "MOVZX(16|32|64)rm16", + "MOVZX(16|32|64)rm8", + "(V?)MOVDDUPrm")>; // TODO: Should this be SKXWriteResGroup71? + +def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", + "VCVTDQ2PDZ128rr", + "VCVTPD2DQZ128rr", + "(V?)CVT(T?)PD2DQrr", + "VCVTPD2PSZ128rr", + "(V?)CVTPD2PSrr", + "VCVTPD2UDQZ128rr", + "VCVTPS2PDZ128rr", + "(V?)CVTPS2PDrr", + "VCVTPS2QQZ128rr", + "VCVTPS2UQQZ128rr", + "VCVTQQ2PSZ128rr", + "(V?)CVTSD2SS(Z?)rr", + "(V?)CVTSI(64)?2SDrr", + "VCVTSI2SSZrr", + "(V?)CVTSI2SSrr", + "VCVTSI(64)?2SDZrr", + "VCVTSS2SDZrr", + "(V?)CVTSS2SDrr", + "VCVTTPD2DQZ128rr", + "VCVTTPD2UDQZ128rr", + "VCVTTPS2QQZ128rr", + "VCVTTPS2UQQZ128rr", + "VCVTUDQ2PDZ128rr", + "VCVTUQQ2PSZ128rr", + "VCVTUSI2SSZrr", + "VCVTUSI(64)?2SDZrr")>; + +def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>; + +def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>; + +def SKXWriteResGroup64 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { + let Latency = 4; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup64], (instrs IMUL32r, MUL32r, MULX32rr)>; + +def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)", + "VCVTPS2PHZ256mr(b?)", + "VCVTPS2PHZmr(b?)")>; + +def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)", + "VPMOVDW(Z|Z128|Z256)mr(b?)", + "VPMOVQB(Z|Z128|Z256)mr(b?)", + "VPMOVQW(Z|Z128|Z256)mr(b?)", + "VPMOVSDB(Z|Z128|Z256)mr(b?)", + "VPMOVSDW(Z|Z128|Z256)mr(b?)", + "VPMOVSQB(Z|Z128|Z256)mr(b?)", + "VPMOVSQD(Z|Z128|Z256)mr(b?)", + "VPMOVSQW(Z|Z128|Z256)mr(b?)", + "VPMOVSWB(Z|Z128|Z256)mr(b?)", + "VPMOVUSDB(Z|Z128|Z256)mr(b?)", + "VPMOVUSDW(Z|Z128|Z256)mr(b?)", + "VPMOVUSQB(Z|Z128|Z256)mr(b?)", + "VPMOVUSQD(Z|Z128|Z256)mr(b?)", + "VPMOVUSQW(Z|Z128|Z256)mr(b?)", + "VPMOVUSWB(Z|Z128|Z256)mr(b?)", + "VPMOVWB(Z|Z128|Z256)mr(b?)")>; + +def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; +} +def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>; + +def SKXWriteResGroup68 : SchedWriteRes<[SKXPort06,SKXPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [2,3]; +} +def: InstRW<[SKXWriteResGroup68], (instregex "CMPXCHG(8|16|32|64)rr")>; + +def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> { + let Latency = 5; + let NumMicroOps = 6; + let ResourceCycles = [1,1,4]; +} +def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>; + +def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup71], (instregex "VBROADCASTSSrm", + "(V?)MOVSHDUPrm", + "(V?)MOVSLDUPrm", + "VPBROADCASTDrm", + "VPBROADCASTQrm")>; + +def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SKXWriteResGroup72], (instregex "MMX_CVTPI2PSirr", + "VCOMPRESSPD(Z|Z128|Z256)rr", + "VCOMPRESSPS(Z|Z128|Z256)rr", + "VPCOMPRESSD(Z|Z128|Z256)rr", + "VPCOMPRESSQ(Z|Z128|Z256)rr", + "VPERMW(Z|Z128|Z256)rr")>; + +def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup73], (instregex "MMX_PADDSBirm", + "MMX_PADDSWirm", + "MMX_PADDUSBirm", + "MMX_PADDUSWirm", + "MMX_PAVGBirm", + "MMX_PAVGWirm", + "MMX_PCMPEQBirm", + "MMX_PCMPEQDirm", + "MMX_PCMPEQWirm", + "MMX_PCMPGTBirm", + "MMX_PCMPGTDirm", + "MMX_PCMPGTWirm", + "MMX_PMAXSWirm", + "MMX_PMAXUBirm", + "MMX_PMINSWirm", + "MMX_PMINUBirm", + "MMX_PSUBSBirm", + "MMX_PSUBSWirm", + "MMX_PSUBUSBirm", + "MMX_PSUBUSWirm")>; + +def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup76], (instregex "FARJMP64", + "JMP(16|32|64)m")>; + +def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8")>; + +def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm", + "BLSI(32|64)rm", + "BLSMSK(32|64)rm", + "BLSR(32|64)rm", + "MOVBE(16|32|64)rm")>; + +def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)", + "VMOVDI2PDIZrm(b?)")>; + +def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>; +def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>; + +def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> { + let Latency = 6; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr", + "VCVTSI642SSZrr", + "VCVTUSI642SSZrr")>; + +def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>; + +def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup86], (instregex "BTC(16|32|64)mi8", + "BTR(16|32|64)mi8", + "BTS(16|32|64)mi8", + "SAR(8|16|32|64)m1", + "SAR(8|16|32|64)mi", + "SHL(8|16|32|64)m1", + "SHL(8|16|32|64)mi", + "SHR(8|16|32|64)m1", + "SHR(8|16|32|64)mi")>; + +def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm", + "PUSH(16|32|64)rmm")>; + +def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> { + let Latency = 6; + let NumMicroOps = 6; + let ResourceCycles = [1,5]; +} +def: InstRW<[SKXWriteResGroup88], (instrs STD)>; + +def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> { + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m", + "VBROADCASTF128", + "VBROADCASTI128", + "VBROADCASTSDYrm", + "VBROADCASTSSYrm", + "VMOVDDUPYrm", + "VMOVSHDUPYrm", + "VMOVSLDUPYrm", + "VPBROADCASTDYrm", + "VPBROADCASTQYrm")>; + +def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup90], (instregex "VCVTDQ2PDYrr")>; + +def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)", + "VMOVSSZrm(b?)")>; + +def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm", + "(V?)PMOV(SX|ZX)BQrm", + "(V?)PMOV(SX|ZX)BWrm", + "(V?)PMOV(SX|ZX)DQrm", + "(V?)PMOV(SX|ZX)WDrm", + "(V?)PMOV(SX|ZX)WQrm")>; + +def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr", + "VCVTPD2DQ(Y|Z256)rr", + "VCVTPD2PS(Y|Z256)rr", + "VCVTPD2UDQZ256rr", + "VCVTPS2PD(Y|Z256)rr", + "VCVTPS2QQZ256rr", + "VCVTPS2UQQZ256rr", + "VCVTQQ2PSZ256rr", + "VCVTTPD2DQ(Y|Z256)rr", + "VCVTTPD2UDQZ256rr", + "VCVTTPS2QQZ256rr", + "VCVTTPS2UQQZ256rr", + "VCVTUDQ2PDZ256rr", + "VCVTUQQ2PSZ256rr")>; + +def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr, + VCVTPD2DQZrr, + VCVTPD2PSZrr, + VCVTPD2UDQZrr, + VCVTPS2PDZrr, + VCVTPS2QQZrr, + VCVTPS2UQQZrr, + VCVTQQ2PSZrr, + VCVTTPD2DQZrr, + VCVTTPD2UDQZrr, + VCVTTPS2QQZrr, + VCVTTPS2UQQZrr, + VCVTUDQ2PDZrr, + VCVTUQQ2PSZrr)>; + +def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup95], (instregex "VBLENDMPDZ128rm(b?)", + "VBLENDMPSZ128rm(b?)", + "VBROADCASTI32X2Z128m(b?)", + "VBROADCASTSSZ128m(b?)", + "VINSERTF128rm", + "VINSERTI128rm", + "VMOVAPDZ128rm(b?)", + "VMOVAPSZ128rm(b?)", + "VMOVDDUPZ128rm(b?)", + "VMOVDQA32Z128rm(b?)", + "VMOVDQA64Z128rm(b?)", + "VMOVDQU16Z128rm(b?)", + "VMOVDQU32Z128rm(b?)", + "VMOVDQU64Z128rm(b?)", + "VMOVDQU8Z128rm(b?)", + "VMOVNTDQAZ128rm(b?)", + "VMOVSHDUPZ128rm(b?)", + "VMOVSLDUPZ128rm(b?)", + "VMOVUPDZ128rm(b?)", + "VMOVUPSZ128rm(b?)", + "VPADD(B|D|Q|W)Z128rm(b?)", + "(V?)PADD(B|D|Q|W)rm", + "VPBLENDDrmi", + "VPBLENDM(B|D|Q|W)Z128rm(b?)", + "VPBROADCASTDZ128m(b?)", + "VPBROADCASTQZ128m(b?)", + "VPSUB(B|D|Q|W)Z128rm(b?)", + "(V?)PSUB(B|D|Q|W)rm", + "VPTERNLOGDZ128rm(b?)i", + "VPTERNLOGQZ128rm(b?)i")>; + +def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup96], (instregex "MMX_PACKSSDWirm", + "MMX_PACKSSWBirm", + "MMX_PACKUSWBirm")>; + +def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr", + "VPERMI2W256rr", + "VPERMI2Wrr", + "VPERMT2W128rr", + "VPERMT2W256rr", + "VPERMT2Wrr")>; + +def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64, + SCASB, SCASL, SCASQ, SCASW)>; + +def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr", + "(V?)CVTSS2SI64(Z?)rr", + "(V?)CVTTSS2SI64(Z?)rr", + "VCVTTSS2USI64Zrr")>; + +def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>; + +def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; + +def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>; + +def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", + "VCOMPRESSPS(Z|Z128|Z256)mr(b?)", + "VPCOMPRESSD(Z|Z128|Z256)mr(b?)", + "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>; + +def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m1", + "ROL(8|16|32|64)mi", + "ROR(8|16|32|64)m1", + "ROR(8|16|32|64)mi")>; + +def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>; + +def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m", + "FARCALL64")>; + +def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 7; + let ResourceCycles = [1,2,2,2]; +} +def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr, + VPSCATTERQQZ128mr, + VSCATTERDPDZ128mr, + VSCATTERQPDZ128mr)>; + +def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 7; + let ResourceCycles = [1,3,1,2]; +} +def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>; + +def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 11; + let ResourceCycles = [1,4,4,2]; +} +def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr, + VPSCATTERQQZ256mr, + VSCATTERDPDZ256mr, + VSCATTERQPDZ256mr)>; + +def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 19; + let ResourceCycles = [1,8,8,2]; +} +def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr, + VPSCATTERQQZmr, + VSCATTERDPDZmr, + VSCATTERQPDZmr)>; + +def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { + let Latency = 7; + let NumMicroOps = 36; + let ResourceCycles = [1,16,1,16,2]; +} +def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>; + +def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm", + "PEXT(32|64)rm")>; + +def SKXWriteResGroup118_16_1 : SchedWriteRes<[SKXPort1, SKXPort0156, SKXPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup118_16_1], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>; + +def SKXWriteResGroup118_16_2 : SchedWriteRes<[SKXPort1, SKXPort06, SKXPort0156, SKXPort23]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,1,2,1]; +} +def: InstRW<[SKXWriteResGroup118_16_2], (instrs IMUL16m, MUL16m)>; + +def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m", + "VFPCLASSSDZrm(b?)", + "VPBROADCASTBYrm", + "VPBROADCASTB(Z|Z256)m(b?)", + "VPBROADCASTWYrm", + "VPBROADCASTW(Z|Z256)m(b?)", + "VPMOVSXBDYrm", + "VPMOVSXBQYrm", + "VPMOVSXWQYrm")>; + +def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup121], (instregex "VBLENDMPD(Z|Z256)rm(b?)", + "VBLENDMPS(Z|Z256)rm(b?)", + "VBROADCASTF32X2Z256m(b?)", + "VBROADCASTF32X2Zm(b?)", + "VBROADCASTF32X4Z256rm(b?)", + "VBROADCASTF32X4rm(b?)", + "VBROADCASTF32X8rm(b?)", + "VBROADCASTF64X2Z128rm(b?)", + "VBROADCASTF64X2rm(b?)", + "VBROADCASTF64X4rm(b?)", + "VBROADCASTI32X2Z256m(b?)", + "VBROADCASTI32X2Zm(b?)", + "VBROADCASTI32X4Z256rm(b?)", + "VBROADCASTI32X4rm(b?)", + "VBROADCASTI32X8rm(b?)", + "VBROADCASTI64X2Z128rm(b?)", + "VBROADCASTI64X2rm(b?)", + "VBROADCASTI64X4rm(b?)", + "VBROADCASTSD(Z|Z256)m(b?)", + "VBROADCASTSS(Z|Z256)m(b?)", + "VINSERTF32x4(Z|Z256)rm(b?)", + "VINSERTF32x8Zrm(b?)", + "VINSERTF64x2(Z|Z256)rm(b?)", + "VINSERTF64x4Zrm(b?)", + "VINSERTI32x4(Z|Z256)rm(b?)", + "VINSERTI32x8Zrm(b?)", + "VINSERTI64x2(Z|Z256)rm(b?)", + "VINSERTI64x4Zrm(b?)", + "VMOVAPD(Z|Z256)rm(b?)", + "VMOVAPS(Z|Z256)rm(b?)", + "VMOVDDUP(Z|Z256)rm(b?)", + "VMOVDQA32(Z|Z256)rm(b?)", + "VMOVDQA64(Z|Z256)rm(b?)", + "VMOVDQU16(Z|Z256)rm(b?)", + "VMOVDQU32(Z|Z256)rm(b?)", + "VMOVDQU64(Z|Z256)rm(b?)", + "VMOVDQU8(Z|Z256)rm(b?)", + "VMOVNTDQAZ256rm(b?)", + "VMOVSHDUP(Z|Z256)rm(b?)", + "VMOVSLDUP(Z|Z256)rm(b?)", + "VMOVUPD(Z|Z256)rm(b?)", + "VMOVUPS(Z|Z256)rm(b?)", + "VPADD(B|D|Q|W)Yrm", + "VPADD(B|D|Q|W)(Z|Z256)rm(b?)", + "VPBLENDDYrmi", + "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)", + "VPBROADCASTD(Z|Z256)m(b?)", + "VPBROADCASTQ(Z|Z256)m(b?)", + "VPSUB(B|D|Q|W)Yrm", + "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)", + "VPTERNLOGD(Z|Z256)rm(b?)i", + "VPTERNLOGQ(Z|Z256)rm(b?)i")>; + +def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { + let Latency = 8; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>; + +def SKXWriteResGroup126 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,3]; +} +def: InstRW<[SKXWriteResGroup126], (instregex "ROR(8|16|32|64)mCL")>; + +def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m1", + "RCL(8|16|32|64)mi", + "RCR(8|16|32|64)m1", + "RCR(8|16|32|64)mi")>; + +def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,3]; +} +def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; + +def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,2,1]; +} +def: SchedAlias; +def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG(8|16|32|64)rm")>; + +def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { + let Latency = 8; + let NumMicroOps = 8; + let ResourceCycles = [1,2,1,2,2]; +} +def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr, + VPSCATTERQDZ256mr, + VSCATTERQPSZ128mr, + VSCATTERQPSZ256mr)>; + +def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { + let Latency = 8; + let NumMicroOps = 12; + let ResourceCycles = [1,4,1,4,2]; +} +def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr, + VSCATTERDPSZ128mr)>; + +def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { + let Latency = 8; + let NumMicroOps = 20; + let ResourceCycles = [1,8,1,8,2]; +} +def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr, + VSCATTERDPSZ256mr)>; + +def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { + let Latency = 8; + let NumMicroOps = 36; + let ResourceCycles = [1,16,1,16,2]; +} +def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>; + +def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup135], (instregex "MMX_CVTPI2PSirm")>; + +def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup136], (instregex "VALIGNDZ128rm(b?)i", + "VALIGNQZ128rm(b?)i", + "VCMPPDZ128rm(b?)i", + "VCMPPSZ128rm(b?)i", + "VCMPSDZrm", + "VCMPSSZrm", + "VFPCLASSSSZrm(b?)", + "VPCMPBZ128rmi(b?)", + "VPCMPDZ128rmi(b?)", + "VPCMPEQ(B|D|Q|W)Z128rm(b?)", + "VPCMPGT(B|D|Q|W)Z128rm(b?)", + "(V?)PCMPGTQrm", + "VPCMPQZ128rmi(b?)", + "VPCMPU(B|D|Q|W)Z128rmi(b?)", + "VPCMPWZ128rmi(b?)", + "VPERMI2D128rm(b?)", + "VPERMI2PD128rm(b?)", + "VPERMI2PS128rm(b?)", + "VPERMI2Q128rm(b?)", + "VPERMT2D128rm(b?)", + "VPERMT2PD128rm(b?)", + "VPERMT2PS128rm(b?)", + "VPERMT2Q128rm(b?)", + "VPMAXSQZ128rm(b?)", + "VPMAXUQZ128rm(b?)", + "VPMINSQZ128rm(b?)", + "VPMINUQZ128rm(b?)", + "VPMOVSXBDZ128rm(b?)", + "VPMOVSXBQZ128rm(b?)", + "VPMOVSXBWYrm", + "VPMOVSXBWZ128rm(b?)", + "VPMOVSXDQYrm", + "VPMOVSXDQZ128rm(b?)", + "VPMOVSXWDYrm", + "VPMOVSXWDZ128rm(b?)", + "VPMOVSXWQZ128rm(b?)", + "VPMOVZXBDZ128rm(b?)", + "VPMOVZXBQZ128rm(b?)", + "VPMOVZXBWZ128rm(b?)", + "VPMOVZXDQZ128rm(b?)", + "VPMOVZXWDYrm", + "VPMOVZXWDZ128rm(b?)", + "VPMOVZXWQZ128rm(b?)", + "VPTESTMBZ128rm(b?)", + "VPTESTMDZ128rm(b?)", + "VPTESTMQZ128rm(b?)", + "VPTESTMWZ128rm(b?)", + "VPTESTNMBZ128rm(b?)", + "VPTESTNMDZ128rm(b?)", + "VPTESTNMQZ128rm(b?)", + "VPTESTNMWZ128rm(b?)")>; + +def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm", + "(V?)CVTPS2PDrm")>; + +def SKXWriteResGroup142 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup142], (instrs IMUL64m, MUL64m, MULX64rm)>; + +def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm", + "(V?)PHSUBSWrm")>; + +def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> { + let Latency = 9; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm", + "LSL(16|32|64)rm")>; + +def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m", + "ILD_F(16|32|64)m", + "VALIGND(Z|Z256)rm(b?)i", + "VALIGNQ(Z|Z256)rm(b?)i", + "VCMPPD(Z|Z256)rm(b?)i", + "VCMPPS(Z|Z256)rm(b?)i", + "VPCMPB(Z|Z256)rmi(b?)", + "VPCMPD(Z|Z256)rmi(b?)", + "VPCMPEQB(Z|Z256)rm(b?)", + "VPCMPEQD(Z|Z256)rm(b?)", + "VPCMPEQQ(Z|Z256)rm(b?)", + "VPCMPEQW(Z|Z256)rm(b?)", + "VPCMPGTB(Z|Z256)rm(b?)", + "VPCMPGTD(Z|Z256)rm(b?)", + "VPCMPGTQYrm", + "VPCMPGTQ(Z|Z256)rm(b?)", + "VPCMPGTW(Z|Z256)rm(b?)", + "VPCMPQ(Z|Z256)rmi(b?)", + "VPCMPU(B|D|Q|W)Z256rmi(b?)", + "VPCMPU(B|D|Q|W)Zrmi(b?)", + "VPCMPW(Z|Z256)rmi(b?)", + "VPMAXSQ(Z|Z256)rm(b?)", + "VPMAXUQ(Z|Z256)rm(b?)", + "VPMINSQ(Z|Z256)rm(b?)", + "VPMINUQ(Z|Z256)rm(b?)", + "VPTESTM(B|D|Q|W)Z256rm(b?)", + "VPTESTM(B|D|Q|W)Zrm(b?)", + "VPTESTNM(B|D|Q|W)Z256rm(b?)", + "VPTESTNM(B|D|Q|W)Zrm(b?)")>; + +def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)", + "VCVTDQ2PSZ128rm(b?)", + "(V?)CVTDQ2PSrm", + "VCVTPD2QQZ128rm(b?)", + "VCVTPD2UQQZ128rm(b?)", + "VCVTPH2PSZ128rm(b?)", + "VCVTPS2DQZ128rm(b?)", + "(V?)CVTPS2DQrm", + "VCVTPS2PDZ128rm(b?)", + "VCVTPS2QQZ128rm(b?)", + "VCVTPS2UDQZ128rm(b?)", + "VCVTPS2UQQZ128rm(b?)", + "VCVTQQ2PDZ128rm(b?)", + "VCVTQQ2PSZ128rm(b?)", + "VCVTSS2SDZrm", + "(V?)CVTSS2SDrm", + "VCVTTPD2QQZ128rm(b?)", + "VCVTTPD2UQQZ128rm(b?)", + "VCVTTPS2DQZ128rm(b?)", + "(V?)CVTTPS2DQrm", + "VCVTTPS2QQZ128rm(b?)", + "VCVTTPS2UDQZ128rm(b?)", + "VCVTTPS2UQQZ128rm(b?)", + "VCVTUDQ2PDZ128rm(b?)", + "VCVTUDQ2PSZ128rm(b?)", + "VCVTUQQ2PDZ128rm(b?)", + "VCVTUQQ2PSZ128rm(b?)")>; + +def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)", + "VEXPANDPSZ128rm(b?)", + "VPEXPANDDZ128rm(b?)", + "VPEXPANDQZ128rm(b?)")>; + +def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>; + +def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> { + let Latency = 10; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKXWriteResGroup154], (instregex "VPHADDSWYrm", + "VPHSUBSWYrm")>; + +def SKXWriteResGroup156 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort06,SKXPort0156]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup156], (instrs IMUL32m, MUL32m, MULX32rm)>; + +def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 10; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,3]; +} +def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>; + +def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { + let Latency = 11; + let NumMicroOps = 1; + let ResourceCycles = [1,3]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>; + +def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2PD(Z|Z256)rm(b?)", + "VCVTDQ2PSYrm", + "VCVTDQ2PS(Z|Z256)rm(b?)", + "VCVTPH2PS(Z|Z256)rm(b?)", + "VCVTPS2PDYrm", + "VCVTPS2PD(Z|Z256)rm(b?)", + "VCVTQQ2PD(Z|Z256)rm(b?)", + "VCVTQQ2PSZ256rm(b?)", + "VCVT(T?)PD2QQ(Z|Z256)rm(b?)", + "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)", + "VCVT(T?)PS2DQYrm", + "VCVT(T?)PS2DQ(Z|Z256)rm(b?)", + "VCVT(T?)PS2QQZ256rm(b?)", + "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)", + "VCVT(T?)PS2UQQZ256rm(b?)", + "VCVTUDQ2PD(Z|Z256)rm(b?)", + "VCVTUDQ2PS(Z|Z256)rm(b?)", + "VCVTUQQ2PD(Z|Z256)rm(b?)", + "VCVTUQQ2PSZ256rm(b?)")>; + +def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m", + "VEXPANDPD(Z|Z256)rm(b?)", + "VEXPANDPS(Z|Z256)rm(b?)", + "VPEXPANDD(Z|Z256)rm(b?)", + "VPEXPANDQ(Z|Z256)rm(b?)")>; + +def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>; + +def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>; + +def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup166], (instregex "CVTPD2PSrm", + "CVT(T?)PD2DQrm", + "MMX_CVT(T?)PD2PIirm")>; + +def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 11; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>; + +def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { + let Latency = 11; + let NumMicroOps = 7; + let ResourceCycles = [2,3,2]; +} +def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL", + "RCR(16|32|64)rCL")>; + +def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 11; + let NumMicroOps = 9; + let ResourceCycles = [1,5,1,2]; +} +def: InstRW<[SKXWriteResGroup170], (instregex "RCL8rCL")>; + +def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> { + let Latency = 11; + let NumMicroOps = 11; + let ResourceCycles = [2,9]; +} +def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>; + +def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>; + +def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>; + +def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>; + +def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)", + "VCVT(T?)SS2USI64Zrm(b?)")>; + +def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 12; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)", + "VCVT(T?)PS2UQQZrm(b?)")>; + +def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 12; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>; + +def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m", + "VPERMWZ256rm(b?)", + "VPERMWZrm(b?)")>; + +def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup181], (instregex "VCVTDQ2PDYrm")>; + +def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 13; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)", + "VPERMT2W128rm(b?)")>; + +def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1,3]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1,5]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>; + +def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)", + "VCVTPD2PSZrm(b?)", + "VCVTPD2UDQZrm(b?)", + "VCVTQQ2PSZrm(b?)", + "VCVTTPD2DQZrm(b?)", + "VCVTTPD2UDQZrm(b?)", + "VCVTUQQ2PSZrm(b?)")>; + +def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { + let Latency = 14; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)", + "VPERMI2Wrm(b?)", + "VPERMT2W256rm(b?)", + "VPERMT2Wrm(b?)")>; + +def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 14; + let NumMicroOps = 10; + let ResourceCycles = [2,4,1,3]; +} +def: InstRW<[SKXWriteResGroup190], (instregex "RCR8rCL")>; + +def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> { + let Latency = 15; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; + +def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { + let Latency = 15; + let NumMicroOps = 8; + let ResourceCycles = [1,2,2,1,2]; +} +def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>; + +def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 15; + let NumMicroOps = 10; + let ResourceCycles = [1,1,1,5,1,1]; +} +def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>; + +def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 16; + let NumMicroOps = 14; + let ResourceCycles = [1,1,1,4,2,5]; +} +def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>; + +def SKXWriteResGroup200 : SchedWriteRes<[SKXPort0156]> { + let Latency = 16; + let NumMicroOps = 16; + let ResourceCycles = [16]; +} +def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>; + +def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { + let Latency = 17; + let NumMicroOps = 2; + let ResourceCycles = [1,1,5]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> { + let Latency = 17; + let NumMicroOps = 15; + let ResourceCycles = [2,1,2,4,2,4]; +} +def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>; + +def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 18; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>; + +def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,5]; +} +def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>; + +def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 18; + let NumMicroOps = 11; + let ResourceCycles = [2,1,1,4,1,2]; +} +def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>; + +def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { + let Latency = 19; + let NumMicroOps = 2; + let ResourceCycles = [1,1,4]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort015]> { + let Latency = 19; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)", + "VPMULLQZrm(b?)")>; + +def SKXWriteResGroup214 : SchedWriteRes<[]> { + let Latency = 20; + let NumMicroOps = 0; +} +def: InstRW<[SKXWriteResGroup214], (instrs VGATHERDPSZ128rm, + VGATHERQPSZrm, + VPGATHERDDZ128rm)>; + +def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> { + let Latency = 20; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; + +def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { + let Latency = 20; + let NumMicroOps = 2; + let ResourceCycles = [1,1,4]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup218 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { + let Latency = 20; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup218], (instrs VGATHERQPSZ128rm, + VGATHERQPSZ256rm, + VPGATHERQDZ128rm, + VPGATHERQDZ256rm)>; + +def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 20; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,1,2]; +} +def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>; + +def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> { + let Latency = 20; + let NumMicroOps = 10; + let ResourceCycles = [1,2,7]; +} +def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>; + +def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { + let Latency = 21; + let NumMicroOps = 2; + let ResourceCycles = [1,1,8]; +} +def : SchedAlias; // TODO - convert to ZnWriteResFpuPair + +def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> { + let Latency = 22; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>; + +def SKXWriteResGroup224 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { + let Latency = 22; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup224], (instrs VGATHERDPDZ128rm, + VGATHERQPDZ128rm, + VPGATHERDQZ128rm, + VPGATHERQQZ128rm)>; + +def SKXWriteResGroup224_2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> { + let Latency = 22; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup224_2], (instrs VGATHERDPSrm, + VGATHERDPDrm, + VGATHERQPDrm, + VGATHERQPSrm, + VPGATHERDDrm, + VPGATHERDQrm, + VPGATHERQDrm, + VPGATHERQQrm, + VPGATHERDDrm, + VPGATHERQDrm, + VPGATHERDQrm, + VPGATHERQQrm, + VGATHERDPSrm, + VGATHERQPSrm, + VGATHERDPDrm, + VGATHERQPDrm)>; + +def SKXWriteResGroup224_3 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> { + let Latency = 25; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup224_3], (instrs VGATHERDPSYrm, + VGATHERQPDYrm, + VGATHERQPSYrm, + VPGATHERDDYrm, + VPGATHERDQYrm, + VPGATHERQDYrm, + VPGATHERQQYrm, + VPGATHERDDYrm, + VPGATHERQDYrm, + VPGATHERDQYrm, + VPGATHERQQYrm, + VGATHERDPSYrm, + VGATHERQPSYrm, + VGATHERDPDYrm)>; + +def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { + let Latency = 22; + let NumMicroOps = 14; + let ResourceCycles = [5,5,4]; +} +def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr", + "VPCONFLICTQZ256rr")>; + +def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 23; + let NumMicroOps = 19; + let ResourceCycles = [2,1,4,1,1,4,6]; +} +def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>; + +def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { + let Latency = 25; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>; + +def SKXWriteResGroup234 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { + let Latency = 25; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup234], (instrs VGATHERDPDZ256rm, + VGATHERQPDZ256rm, + VPGATHERDQZ256rm, + VPGATHERQDZrm, + VPGATHERQQZ256rm)>; + +def SKXWriteResGroup238 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { + let Latency = 26; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup238], (instrs VGATHERDPDZrm, + VGATHERQPDZrm, + VPGATHERDQZrm, + VPGATHERQQZrm)>; + +def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> { + let Latency = 27; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>; + +def SKXWriteResGroup240 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { + let Latency = 27; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup240], (instrs VGATHERDPSZ256rm, + VPGATHERDDZ256rm)>; + +def SKXWriteResGroup241 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort0156]> { + let Latency = 28; + let NumMicroOps = 8; + let ResourceCycles = [2,4,1,1]; +} +def: InstRW<[SKXWriteResGroup241], (instregex "IDIV(8|16|32|64)m")>; + +def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { + let Latency = 29; + let NumMicroOps = 15; + let ResourceCycles = [5,5,1,4]; +} +def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>; + +def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { + let Latency = 30; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>; + +def SKXWriteResGroup245 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { + let Latency = 30; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SKXWriteResGroup245], (instrs VGATHERDPSZrm, + VPGATHERDDZrm)>; + +def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,3,4,10]; +} +def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri", + "IN(8|16|32)rr")>; + +def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 35; + let NumMicroOps = 23; + let ResourceCycles = [1,5,2,1,4,10]; +} +def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir", + "OUT(8|16|32)rr")>; + +def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { + let Latency = 37; + let NumMicroOps = 21; + let ResourceCycles = [9,7,5]; +} +def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr", + "VPCONFLICTQZrr")>; + +def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> { + let Latency = 37; + let NumMicroOps = 31; + let ResourceCycles = [1,8,1,21]; +} +def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>; + +def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> { + let Latency = 40; + let NumMicroOps = 18; + let ResourceCycles = [1,1,2,3,1,1,1,8]; +} +def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>; + +def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { + let Latency = 41; + let NumMicroOps = 39; + let ResourceCycles = [1,10,1,1,26]; +} +def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>; + +def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> { + let Latency = 42; + let NumMicroOps = 22; + let ResourceCycles = [2,20]; +} +def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>; + +def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { + let Latency = 42; + let NumMicroOps = 40; + let ResourceCycles = [1,11,1,1,26]; +} +def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>; +def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; + +def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { + let Latency = 44; + let NumMicroOps = 22; + let ResourceCycles = [9,7,1,5]; +} +def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)", + "VPCONFLICTQZrm(b?)")>; + +def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> { + let Latency = 62; + let NumMicroOps = 64; + let ResourceCycles = [2,8,5,10,39]; +} +def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>; + +def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 63; + let NumMicroOps = 88; + let ResourceCycles = [4,4,31,1,2,1,45]; +} +def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>; + +def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> { + let Latency = 63; + let NumMicroOps = 90; + let ResourceCycles = [4,2,33,1,2,1,47]; +} +def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>; + +def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { + let Latency = 67; + let NumMicroOps = 35; + let ResourceCycles = [17,11,7]; +} +def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>; + +def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { + let Latency = 74; + let NumMicroOps = 36; + let ResourceCycles = [17,11,1,7]; +} +def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>; + +def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> { + let Latency = 75; + let NumMicroOps = 15; + let ResourceCycles = [6,3,6]; +} +def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>; + +def SKXWriteResGroup264 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> { + let Latency = 76; + let NumMicroOps = 32; + let ResourceCycles = [7,2,8,3,1,11]; +} +def: InstRW<[SKXWriteResGroup264], (instregex "DIV(16|32|64)r")>; + +def SKXWriteResGroup265 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> { + let Latency = 102; + let NumMicroOps = 66; + let ResourceCycles = [4,2,4,8,14,34]; +} +def: InstRW<[SKXWriteResGroup265], (instregex "IDIV(16|32|64)r")>; + +def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> { + let Latency = 106; + let NumMicroOps = 100; + let ResourceCycles = [9,1,11,16,1,11,21,30]; +} +def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>; + +def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> { + let Latency = 140; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>; + +def: InstRW<[WriteZero], (instrs CLC)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86Schedule.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86Schedule.td new file mode 100644 index 0000000..6215d58 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86Schedule.td @@ -0,0 +1,661 @@ +//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// InstrSchedModel annotations for out-of-order CPUs. + +// Instructions with folded loads need to read the memory operand immediately, +// but other register operands don't have to be read until the load is ready. +// These operands are marked with ReadAfterLd. +def ReadAfterLd : SchedRead; + +// Instructions with both a load and a store folded are modeled as a folded +// load + WriteRMW. +def WriteRMW : SchedWrite; + +// Helper to set SchedWrite ExePorts/Latency/ResourceCycles/NumMicroOps. +multiclass X86WriteRes ExePorts, + int Lat, list Res, int UOps> { + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } +} + +// Most instructions can fold loads, so almost every SchedWrite comes in two +// variants: With and without a folded load. +// An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite +// with a folded load. +class X86FoldableSchedWrite : SchedWrite { + // The SchedWrite to use when a load is folded into the instruction. + SchedWrite Folded; +} + +// Multiclass that produces a linked pair of SchedWrites. +multiclass X86SchedWritePair { + // Register-Memory operation. + def Ld : SchedWrite; + // Register-Register operation. + def NAME : X86FoldableSchedWrite { + let Folded = !cast(NAME#"Ld"); + } +} + +// Helpers to mark SchedWrites as unsupported. +multiclass X86WriteResUnsupported { + let Unsupported = 1 in { + def : WriteRes; + } +} +multiclass X86WriteResPairUnsupported { + let Unsupported = 1 in { + def : WriteRes; + def : WriteRes; + } +} + +// Multiclass that wraps X86FoldableSchedWrite for each vector width. +class X86SchedWriteWidths { + X86FoldableSchedWrite Scl = sScl; // Scalar float/double operations. + X86FoldableSchedWrite MMX = sScl; // MMX operations. + X86FoldableSchedWrite XMM = s128; // XMM operations. + X86FoldableSchedWrite YMM = s256; // YMM operations. + X86FoldableSchedWrite ZMM = s512; // ZMM operations. +} + +// Multiclass that wraps X86SchedWriteWidths for each fp vector type. +class X86SchedWriteSizes { + X86SchedWriteWidths PS = sPS; + X86SchedWriteWidths PD = sPD; +} + +// Multiclass that wraps move/load/store triple for a vector width. +class X86SchedWriteMoveLS { + SchedWrite RR = MoveRR; + SchedWrite RM = LoadRM; + SchedWrite MR = StoreMR; +} + +// Multiclass that wraps X86SchedWriteMoveLS for each vector width. +class X86SchedWriteMoveLSWidths { + X86SchedWriteMoveLS Scl = sScl; // Scalar float/double operations. + X86SchedWriteMoveLS MMX = sScl; // MMX operations. + X86SchedWriteMoveLS XMM = s128; // XMM operations. + X86SchedWriteMoveLS YMM = s256; // YMM operations. + X86SchedWriteMoveLS ZMM = s512; // ZMM operations. +} + +// Loads, stores, and moves, not folded with other operations. +def WriteLoad : SchedWrite; +def WriteStore : SchedWrite; +def WriteStoreNT : SchedWrite; +def WriteMove : SchedWrite; + +// Arithmetic. +defm WriteALU : X86SchedWritePair; // Simple integer ALU op. +defm WriteADC : X86SchedWritePair; // Integer ALU + flags op. +def WriteALURMW : WriteSequence<[WriteALULd, WriteStore]>; +def WriteADCRMW : WriteSequence<[WriteADCLd, WriteStore]>; +defm WriteIMul : X86SchedWritePair; // Integer multiplication. +defm WriteIMul64 : X86SchedWritePair; // Integer 64-bit multiplication. +def WriteIMulH : SchedWrite; // Integer multiplication, high part. +def WriteLEA : SchedWrite; // LEA instructions can't fold loads. + +def WriteBSWAP32 : SchedWrite; // Byte Order (Endianness) 32-bit Swap. +def WriteBSWAP64 : SchedWrite; // Byte Order (Endianness) 64-bit Swap. + +// Integer division. +defm WriteDiv8 : X86SchedWritePair; +defm WriteDiv16 : X86SchedWritePair; +defm WriteDiv32 : X86SchedWritePair; +defm WriteDiv64 : X86SchedWritePair; +defm WriteIDiv8 : X86SchedWritePair; +defm WriteIDiv16 : X86SchedWritePair; +defm WriteIDiv32 : X86SchedWritePair; +defm WriteIDiv64 : X86SchedWritePair; + +defm WriteBSF : X86SchedWritePair; // Bit scan forward. +defm WriteBSR : X86SchedWritePair; // Bit scan reverse. +defm WritePOPCNT : X86SchedWritePair; // Bit population count. +defm WriteLZCNT : X86SchedWritePair; // Leading zero count. +defm WriteTZCNT : X86SchedWritePair; // Trailing zero count. +defm WriteCMOV : X86SchedWritePair; // Conditional move. +defm WriteCMOV2 : X86SchedWritePair; // Conditional (CF + ZF flag) move. +def WriteFCMOV : SchedWrite; // X87 conditional move. +def WriteSETCC : SchedWrite; // Set register based on condition code. +def WriteSETCCStore : SchedWrite; +def WriteLAHFSAHF : SchedWrite; // Load/Store flags in AH. +def WriteBitTest : SchedWrite; // Bit Test - TODO add memory folding support + +// Integer shifts and rotates. +defm WriteShift : X86SchedWritePair; +// Double shift instructions. +def WriteSHDrri : SchedWrite; +def WriteSHDrrcl : SchedWrite; +def WriteSHDmri : SchedWrite; +def WriteSHDmrcl : SchedWrite; + +// BMI1 BEXTR, BMI2 BZHI +defm WriteBEXTR : X86SchedWritePair; +defm WriteBZHI : X86SchedWritePair; + +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +def WriteZero : SchedWrite; + +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +defm WriteJump : X86SchedWritePair; + +// Floating point. This covers both scalar and vector operations. +def WriteFLD0 : SchedWrite; +def WriteFLD1 : SchedWrite; +def WriteFLDC : SchedWrite; +def WriteFLoad : SchedWrite; +def WriteFLoadX : SchedWrite; +def WriteFLoadY : SchedWrite; +def WriteFMaskedLoad : SchedWrite; +def WriteFMaskedLoadY : SchedWrite; +def WriteFStore : SchedWrite; +def WriteFStoreX : SchedWrite; +def WriteFStoreY : SchedWrite; +def WriteFStoreNT : SchedWrite; +def WriteFStoreNTX : SchedWrite; +def WriteFStoreNTY : SchedWrite; +def WriteFMaskedStore : SchedWrite; +def WriteFMaskedStoreY : SchedWrite; +def WriteFMove : SchedWrite; +def WriteFMoveX : SchedWrite; +def WriteFMoveY : SchedWrite; + +defm WriteFAdd : X86SchedWritePair; // Floating point add/sub. +defm WriteFAddX : X86SchedWritePair; // Floating point add/sub (XMM). +defm WriteFAddY : X86SchedWritePair; // Floating point add/sub (YMM). +defm WriteFAddZ : X86SchedWritePair; // Floating point add/sub (ZMM). +defm WriteFAdd64 : X86SchedWritePair; // Floating point double add/sub. +defm WriteFAdd64X : X86SchedWritePair; // Floating point double add/sub (XMM). +defm WriteFAdd64Y : X86SchedWritePair; // Floating point double add/sub (YMM). +defm WriteFAdd64Z : X86SchedWritePair; // Floating point double add/sub (ZMM). +defm WriteFCmp : X86SchedWritePair; // Floating point compare. +defm WriteFCmpX : X86SchedWritePair; // Floating point compare (XMM). +defm WriteFCmpY : X86SchedWritePair; // Floating point compare (YMM). +defm WriteFCmpZ : X86SchedWritePair; // Floating point compare (ZMM). +defm WriteFCmp64 : X86SchedWritePair; // Floating point double compare. +defm WriteFCmp64X : X86SchedWritePair; // Floating point double compare (XMM). +defm WriteFCmp64Y : X86SchedWritePair; // Floating point double compare (YMM). +defm WriteFCmp64Z : X86SchedWritePair; // Floating point double compare (ZMM). +defm WriteFCom : X86SchedWritePair; // Floating point compare to flags. +defm WriteFMul : X86SchedWritePair; // Floating point multiplication. +defm WriteFMulX : X86SchedWritePair; // Floating point multiplication (XMM). +defm WriteFMulY : X86SchedWritePair; // Floating point multiplication (YMM). +defm WriteFMulZ : X86SchedWritePair; // Floating point multiplication (YMM). +defm WriteFMul64 : X86SchedWritePair; // Floating point double multiplication. +defm WriteFMul64X : X86SchedWritePair; // Floating point double multiplication (XMM). +defm WriteFMul64Y : X86SchedWritePair; // Floating point double multiplication (YMM). +defm WriteFMul64Z : X86SchedWritePair; // Floating point double multiplication (ZMM). +defm WriteFDiv : X86SchedWritePair; // Floating point division. +defm WriteFDivX : X86SchedWritePair; // Floating point division (XMM). +defm WriteFDivY : X86SchedWritePair; // Floating point division (YMM). +defm WriteFDivZ : X86SchedWritePair; // Floating point division (ZMM). +defm WriteFDiv64 : X86SchedWritePair; // Floating point double division. +defm WriteFDiv64X : X86SchedWritePair; // Floating point double division (XMM). +defm WriteFDiv64Y : X86SchedWritePair; // Floating point double division (YMM). +defm WriteFDiv64Z : X86SchedWritePair; // Floating point double division (ZMM). +defm WriteFSqrt : X86SchedWritePair; // Floating point square root. +defm WriteFSqrtX : X86SchedWritePair; // Floating point square root (XMM). +defm WriteFSqrtY : X86SchedWritePair; // Floating point square root (YMM). +defm WriteFSqrtZ : X86SchedWritePair; // Floating point square root (ZMM). +defm WriteFSqrt64 : X86SchedWritePair; // Floating point double square root. +defm WriteFSqrt64X : X86SchedWritePair; // Floating point double square root (XMM). +defm WriteFSqrt64Y : X86SchedWritePair; // Floating point double square root (YMM). +defm WriteFSqrt64Z : X86SchedWritePair; // Floating point double square root (ZMM). +defm WriteFSqrt80 : X86SchedWritePair; // Floating point long double square root. +defm WriteFRcp : X86SchedWritePair; // Floating point reciprocal estimate. +defm WriteFRcpX : X86SchedWritePair; // Floating point reciprocal estimate (XMM). +defm WriteFRcpY : X86SchedWritePair; // Floating point reciprocal estimate (YMM). +defm WriteFRcpZ : X86SchedWritePair; // Floating point reciprocal estimate (ZMM). +defm WriteFRsqrt : X86SchedWritePair; // Floating point reciprocal square root estimate. +defm WriteFRsqrtX: X86SchedWritePair; // Floating point reciprocal square root estimate (XMM). +defm WriteFRsqrtY: X86SchedWritePair; // Floating point reciprocal square root estimate (YMM). +defm WriteFRsqrtZ: X86SchedWritePair; // Floating point reciprocal square root estimate (ZMM). +defm WriteFMA : X86SchedWritePair; // Fused Multiply Add. +defm WriteFMAX : X86SchedWritePair; // Fused Multiply Add (XMM). +defm WriteFMAY : X86SchedWritePair; // Fused Multiply Add (YMM). +defm WriteFMAZ : X86SchedWritePair; // Fused Multiply Add (ZMM). +defm WriteDPPD : X86SchedWritePair; // Floating point double dot product. +defm WriteDPPS : X86SchedWritePair; // Floating point single dot product. +defm WriteDPPSY : X86SchedWritePair; // Floating point single dot product (YMM). +defm WriteDPPSZ : X86SchedWritePair; // Floating point single dot product (ZMM). +defm WriteFSign : X86SchedWritePair; // Floating point fabs/fchs. +defm WriteFRnd : X86SchedWritePair; // Floating point rounding. +defm WriteFRndY : X86SchedWritePair; // Floating point rounding (YMM). +defm WriteFRndZ : X86SchedWritePair; // Floating point rounding (ZMM). +defm WriteFLogic : X86SchedWritePair; // Floating point and/or/xor logicals. +defm WriteFLogicY : X86SchedWritePair; // Floating point and/or/xor logicals (YMM). +defm WriteFLogicZ : X86SchedWritePair; // Floating point and/or/xor logicals (ZMM). +defm WriteFTest : X86SchedWritePair; // Floating point TEST instructions. +defm WriteFTestY : X86SchedWritePair; // Floating point TEST instructions (YMM). +defm WriteFTestZ : X86SchedWritePair; // Floating point TEST instructions (ZMM). +defm WriteFShuffle : X86SchedWritePair; // Floating point vector shuffles. +defm WriteFShuffleY : X86SchedWritePair; // Floating point vector shuffles (YMM). +defm WriteFShuffleZ : X86SchedWritePair; // Floating point vector shuffles (ZMM). +defm WriteFVarShuffle : X86SchedWritePair; // Floating point vector variable shuffles. +defm WriteFVarShuffleY : X86SchedWritePair; // Floating point vector variable shuffles (YMM). +defm WriteFVarShuffleZ : X86SchedWritePair; // Floating point vector variable shuffles (ZMM). +defm WriteFBlend : X86SchedWritePair; // Floating point vector blends. +defm WriteFBlendY : X86SchedWritePair; // Floating point vector blends (YMM). +defm WriteFBlendZ : X86SchedWritePair; // Floating point vector blends (ZMM). +defm WriteFVarBlend : X86SchedWritePair; // Fp vector variable blends. +defm WriteFVarBlendY : X86SchedWritePair; // Fp vector variable blends (YMM). +defm WriteFVarBlendZ : X86SchedWritePair; // Fp vector variable blends (YMZMM). + +// FMA Scheduling helper class. +class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } + +// Horizontal Add/Sub (float and integer) +defm WriteFHAdd : X86SchedWritePair; +defm WriteFHAddY : X86SchedWritePair; +defm WriteFHAddZ : X86SchedWritePair; +defm WritePHAdd : X86SchedWritePair; +defm WritePHAddX : X86SchedWritePair; +defm WritePHAddY : X86SchedWritePair; +defm WritePHAddZ : X86SchedWritePair; + +// Vector integer operations. +def WriteVecLoad : SchedWrite; +def WriteVecLoadX : SchedWrite; +def WriteVecLoadY : SchedWrite; +def WriteVecLoadNT : SchedWrite; +def WriteVecLoadNTY : SchedWrite; +def WriteVecMaskedLoad : SchedWrite; +def WriteVecMaskedLoadY : SchedWrite; +def WriteVecStore : SchedWrite; +def WriteVecStoreX : SchedWrite; +def WriteVecStoreY : SchedWrite; +def WriteVecStoreNT : SchedWrite; +def WriteVecStoreNTY : SchedWrite; +def WriteVecMaskedStore : SchedWrite; +def WriteVecMaskedStoreY : SchedWrite; +def WriteVecMove : SchedWrite; +def WriteVecMoveX : SchedWrite; +def WriteVecMoveY : SchedWrite; +def WriteVecMoveToGpr : SchedWrite; +def WriteVecMoveFromGpr : SchedWrite; + +defm WriteVecALU : X86SchedWritePair; // Vector integer ALU op, no logicals. +defm WriteVecALUX : X86SchedWritePair; // Vector integer ALU op, no logicals (XMM). +defm WriteVecALUY : X86SchedWritePair; // Vector integer ALU op, no logicals (YMM). +defm WriteVecALUZ : X86SchedWritePair; // Vector integer ALU op, no logicals (ZMM). +defm WriteVecLogic : X86SchedWritePair; // Vector integer and/or/xor logicals. +defm WriteVecLogicX : X86SchedWritePair; // Vector integer and/or/xor logicals (XMM). +defm WriteVecLogicY : X86SchedWritePair; // Vector integer and/or/xor logicals (YMM). +defm WriteVecLogicZ : X86SchedWritePair; // Vector integer and/or/xor logicals (ZMM). +defm WriteVecTest : X86SchedWritePair; // Vector integer TEST instructions. +defm WriteVecTestY : X86SchedWritePair; // Vector integer TEST instructions (YMM). +defm WriteVecTestZ : X86SchedWritePair; // Vector integer TEST instructions (ZMM). +defm WriteVecShift : X86SchedWritePair; // Vector integer shifts (default). +defm WriteVecShiftX : X86SchedWritePair; // Vector integer shifts (XMM). +defm WriteVecShiftY : X86SchedWritePair; // Vector integer shifts (YMM). +defm WriteVecShiftZ : X86SchedWritePair; // Vector integer shifts (ZMM). +defm WriteVecShiftImm : X86SchedWritePair; // Vector integer immediate shifts (default). +defm WriteVecShiftImmX: X86SchedWritePair; // Vector integer immediate shifts (XMM). +defm WriteVecShiftImmY: X86SchedWritePair; // Vector integer immediate shifts (YMM). +defm WriteVecShiftImmZ: X86SchedWritePair; // Vector integer immediate shifts (ZMM). +defm WriteVecIMul : X86SchedWritePair; // Vector integer multiply (default). +defm WriteVecIMulX : X86SchedWritePair; // Vector integer multiply (XMM). +defm WriteVecIMulY : X86SchedWritePair; // Vector integer multiply (YMM). +defm WriteVecIMulZ : X86SchedWritePair; // Vector integer multiply (ZMM). +defm WritePMULLD : X86SchedWritePair; // Vector PMULLD. +defm WritePMULLDY : X86SchedWritePair; // Vector PMULLD (YMM). +defm WritePMULLDZ : X86SchedWritePair; // Vector PMULLD (ZMM). +defm WriteShuffle : X86SchedWritePair; // Vector shuffles. +defm WriteShuffleX : X86SchedWritePair; // Vector shuffles (XMM). +defm WriteShuffleY : X86SchedWritePair; // Vector shuffles (YMM). +defm WriteShuffleZ : X86SchedWritePair; // Vector shuffles (ZMM). +defm WriteVarShuffle : X86SchedWritePair; // Vector variable shuffles. +defm WriteVarShuffleX : X86SchedWritePair; // Vector variable shuffles (XMM). +defm WriteVarShuffleY : X86SchedWritePair; // Vector variable shuffles (YMM). +defm WriteVarShuffleZ : X86SchedWritePair; // Vector variable shuffles (ZMM). +defm WriteBlend : X86SchedWritePair; // Vector blends. +defm WriteBlendY : X86SchedWritePair; // Vector blends (YMM). +defm WriteBlendZ : X86SchedWritePair; // Vector blends (ZMM). +defm WriteVarBlend : X86SchedWritePair; // Vector variable blends. +defm WriteVarBlendY : X86SchedWritePair; // Vector variable blends (YMM). +defm WriteVarBlendZ : X86SchedWritePair; // Vector variable blends (ZMM). +defm WritePSADBW : X86SchedWritePair; // Vector PSADBW. +defm WritePSADBWX : X86SchedWritePair; // Vector PSADBW (XMM). +defm WritePSADBWY : X86SchedWritePair; // Vector PSADBW (YMM). +defm WritePSADBWZ : X86SchedWritePair; // Vector PSADBW (ZMM). +defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD. +defm WriteMPSADY : X86SchedWritePair; // Vector MPSAD (YMM). +defm WriteMPSADZ : X86SchedWritePair; // Vector MPSAD (ZMM). +defm WritePHMINPOS : X86SchedWritePair; // Vector PHMINPOS. + +// Vector insert/extract operations. +defm WriteVecInsert : X86SchedWritePair; // Insert gpr to vector element. +def WriteVecExtract : SchedWrite; // Extract vector element to gpr. +def WriteVecExtractSt : SchedWrite; // Extract vector element and store. + +// MOVMSK operations. +def WriteFMOVMSK : SchedWrite; +def WriteVecMOVMSK : SchedWrite; +def WriteVecMOVMSKY : SchedWrite; +def WriteMMXMOVMSK : SchedWrite; + +// Conversion between integer and float. +defm WriteCvtSD2I : X86SchedWritePair; // Double -> Integer. +defm WriteCvtPD2I : X86SchedWritePair; // Double -> Integer (XMM). +defm WriteCvtPD2IY : X86SchedWritePair; // Double -> Integer (YMM). +defm WriteCvtPD2IZ : X86SchedWritePair; // Double -> Integer (ZMM). + +defm WriteCvtSS2I : X86SchedWritePair; // Float -> Integer. +defm WriteCvtPS2I : X86SchedWritePair; // Float -> Integer (XMM). +defm WriteCvtPS2IY : X86SchedWritePair; // Float -> Integer (YMM). +defm WriteCvtPS2IZ : X86SchedWritePair; // Float -> Integer (ZMM). + +defm WriteCvtI2SD : X86SchedWritePair; // Integer -> Double. +defm WriteCvtI2PD : X86SchedWritePair; // Integer -> Double (XMM). +defm WriteCvtI2PDY : X86SchedWritePair; // Integer -> Double (YMM). +defm WriteCvtI2PDZ : X86SchedWritePair; // Integer -> Double (ZMM). + +defm WriteCvtI2SS : X86SchedWritePair; // Integer -> Float. +defm WriteCvtI2PS : X86SchedWritePair; // Integer -> Float (XMM). +defm WriteCvtI2PSY : X86SchedWritePair; // Integer -> Float (YMM). +defm WriteCvtI2PSZ : X86SchedWritePair; // Integer -> Float (ZMM). + +defm WriteCvtSS2SD : X86SchedWritePair; // Float -> Double size conversion. +defm WriteCvtPS2PD : X86SchedWritePair; // Float -> Double size conversion (XMM). +defm WriteCvtPS2PDY : X86SchedWritePair; // Float -> Double size conversion (YMM). +defm WriteCvtPS2PDZ : X86SchedWritePair; // Float -> Double size conversion (ZMM). + +defm WriteCvtSD2SS : X86SchedWritePair; // Double -> Float size conversion. +defm WriteCvtPD2PS : X86SchedWritePair; // Double -> Float size conversion (XMM). +defm WriteCvtPD2PSY : X86SchedWritePair; // Double -> Float size conversion (YMM). +defm WriteCvtPD2PSZ : X86SchedWritePair; // Double -> Float size conversion (ZMM). + +defm WriteCvtPH2PS : X86SchedWritePair; // Half -> Float size conversion. +defm WriteCvtPH2PSY : X86SchedWritePair; // Half -> Float size conversion (YMM). +defm WriteCvtPH2PSZ : X86SchedWritePair; // Half -> Float size conversion (ZMM). + +def WriteCvtPS2PH : SchedWrite; // // Float -> Half size conversion. +def WriteCvtPS2PHY : SchedWrite; // // Float -> Half size conversion (YMM). +def WriteCvtPS2PHZ : SchedWrite; // // Float -> Half size conversion (ZMM). +def WriteCvtPS2PHSt : SchedWrite; // // Float -> Half + store size conversion. +def WriteCvtPS2PHYSt : SchedWrite; // // Float -> Half + store size conversion (YMM). +def WriteCvtPS2PHZSt : SchedWrite; // // Float -> Half + store size conversion (ZMM). + +// CRC32 instruction. +defm WriteCRC32 : X86SchedWritePair; + +// Strings instructions. +// Packed Compare Implicit Length Strings, Return Mask +defm WritePCmpIStrM : X86SchedWritePair; +// Packed Compare Explicit Length Strings, Return Mask +defm WritePCmpEStrM : X86SchedWritePair; +// Packed Compare Implicit Length Strings, Return Index +defm WritePCmpIStrI : X86SchedWritePair; +// Packed Compare Explicit Length Strings, Return Index +defm WritePCmpEStrI : X86SchedWritePair; + +// AES instructions. +defm WriteAESDecEnc : X86SchedWritePair; // Decryption, encryption. +defm WriteAESIMC : X86SchedWritePair; // InvMixColumn. +defm WriteAESKeyGen : X86SchedWritePair; // Key Generation. + +// Carry-less multiplication instructions. +defm WriteCLMul : X86SchedWritePair; + +// EMMS/FEMMS +def WriteEMMS : SchedWrite; + +// Load/store MXCSR +def WriteLDMXCSR : SchedWrite; +def WriteSTMXCSR : SchedWrite; + +// Catch-all for expensive system instructions. +def WriteSystem : SchedWrite; + +// AVX2. +defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles. +defm WriteFVarShuffle256 : X86SchedWritePair; // Fp 256-bit width variable shuffles. +defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles. +defm WriteVarShuffle256 : X86SchedWritePair; // 256-bit width vector variable shuffles. +defm WriteVarVecShift : X86SchedWritePair; // Variable vector shifts. +defm WriteVarVecShiftY : X86SchedWritePair; // Variable vector shifts (YMM). +defm WriteVarVecShiftZ : X86SchedWritePair; // Variable vector shifts (ZMM). + +// Old microcoded instructions that nobody use. +def WriteMicrocoded : SchedWrite; + +// Fence instructions. +def WriteFence : SchedWrite; + +// Nop, not very useful expect it provides a model for nops! +def WriteNop : SchedWrite; + +// Move/Load/Store wrappers. +def WriteFMoveLS + : X86SchedWriteMoveLS; +def WriteFMoveLSX + : X86SchedWriteMoveLS; +def WriteFMoveLSY + : X86SchedWriteMoveLS; +def SchedWriteFMoveLS + : X86SchedWriteMoveLSWidths; + +def WriteFMoveLSNT + : X86SchedWriteMoveLS; +def WriteFMoveLSNTX + : X86SchedWriteMoveLS; +def WriteFMoveLSNTY + : X86SchedWriteMoveLS; +def SchedWriteFMoveLSNT + : X86SchedWriteMoveLSWidths; + +def WriteVecMoveLS + : X86SchedWriteMoveLS; +def WriteVecMoveLSX + : X86SchedWriteMoveLS; +def WriteVecMoveLSY + : X86SchedWriteMoveLS; +def SchedWriteVecMoveLS + : X86SchedWriteMoveLSWidths; + +def WriteVecMoveLSNT + : X86SchedWriteMoveLS; +def WriteVecMoveLSNTX + : X86SchedWriteMoveLS; +def WriteVecMoveLSNTY + : X86SchedWriteMoveLS; +def SchedWriteVecMoveLSNT + : X86SchedWriteMoveLSWidths; + +// Vector width wrappers. +def SchedWriteFAdd + : X86SchedWriteWidths; +def SchedWriteFAdd64 + : X86SchedWriteWidths; +def SchedWriteFHAdd + : X86SchedWriteWidths; +def SchedWriteFCmp + : X86SchedWriteWidths; +def SchedWriteFCmp64 + : X86SchedWriteWidths; +def SchedWriteFMul + : X86SchedWriteWidths; +def SchedWriteFMul64 + : X86SchedWriteWidths; +def SchedWriteFMA + : X86SchedWriteWidths; +def SchedWriteDPPD + : X86SchedWriteWidths; +def SchedWriteDPPS + : X86SchedWriteWidths; +def SchedWriteFDiv + : X86SchedWriteWidths; +def SchedWriteFDiv64 + : X86SchedWriteWidths; +def SchedWriteFSqrt + : X86SchedWriteWidths; +def SchedWriteFSqrt64 + : X86SchedWriteWidths; +def SchedWriteFRcp + : X86SchedWriteWidths; +def SchedWriteFRsqrt + : X86SchedWriteWidths; +def SchedWriteFRnd + : X86SchedWriteWidths; +def SchedWriteFLogic + : X86SchedWriteWidths; +def SchedWriteFTest + : X86SchedWriteWidths; + +def SchedWriteFShuffle + : X86SchedWriteWidths; +def SchedWriteFVarShuffle + : X86SchedWriteWidths; +def SchedWriteFBlend + : X86SchedWriteWidths; +def SchedWriteFVarBlend + : X86SchedWriteWidths; + +def SchedWriteCvtDQ2PD + : X86SchedWriteWidths; +def SchedWriteCvtDQ2PS + : X86SchedWriteWidths; +def SchedWriteCvtPD2DQ + : X86SchedWriteWidths; +def SchedWriteCvtPS2DQ + : X86SchedWriteWidths; +def SchedWriteCvtPS2PD + : X86SchedWriteWidths; +def SchedWriteCvtPD2PS + : X86SchedWriteWidths; + +def SchedWriteVecALU + : X86SchedWriteWidths; +def SchedWritePHAdd + : X86SchedWriteWidths; +def SchedWriteVecLogic + : X86SchedWriteWidths; +def SchedWriteVecTest + : X86SchedWriteWidths; +def SchedWriteVecShift + : X86SchedWriteWidths; +def SchedWriteVecShiftImm + : X86SchedWriteWidths; +def SchedWriteVarVecShift + : X86SchedWriteWidths; +def SchedWriteVecIMul + : X86SchedWriteWidths; +def SchedWritePMULLD + : X86SchedWriteWidths; +def SchedWriteMPSAD + : X86SchedWriteWidths; +def SchedWritePSADBW + : X86SchedWriteWidths; + +def SchedWriteShuffle + : X86SchedWriteWidths; +def SchedWriteVarShuffle + : X86SchedWriteWidths; +def SchedWriteBlend + : X86SchedWriteWidths; +def SchedWriteVarBlend + : X86SchedWriteWidths; + +// Vector size wrappers. +def SchedWriteFAddSizes + : X86SchedWriteSizes; +def SchedWriteFCmpSizes + : X86SchedWriteSizes; +def SchedWriteFMulSizes + : X86SchedWriteSizes; +def SchedWriteFDivSizes + : X86SchedWriteSizes; +def SchedWriteFSqrtSizes + : X86SchedWriteSizes; +def SchedWriteFLogicSizes + : X86SchedWriteSizes; +def SchedWriteFShuffleSizes + : X86SchedWriteSizes; + +//===----------------------------------------------------------------------===// +// Generic Processor Scheduler Models. + +// IssueWidth is analogous to the number of decode units. Core and its +// descendants, including Nehalem and SandyBridge have 4 decoders. +// Resources beyond the decoder operate on micro-ops and are buffered +// so adjacent micro-ops don't directly compete. +// +// MicroOpBufferSize > 1 indicates that RAW dependencies can be +// decoded in the same cycle. The value 32 is a reasonably arbitrary +// number of in-flight instructions. +// +// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef +// indicates high latency opcodes. Alternatively, InstrItinData +// entries may be included here to define specific operand +// latencies. Since these latencies are not used for pipeline hazards, +// they do not need to be exact. +// +// The GenericX86Model contains no instruction schedules +// and disables PostRAScheduler. +class GenericX86Model : SchedMachineModel { + let IssueWidth = 4; + let MicroOpBufferSize = 32; + let LoadLatency = 4; + let HighLatency = 10; + let PostRAScheduler = 0; + let CompleteModel = 0; +} + +def GenericModel : GenericX86Model; + +// Define a model with the PostRAScheduler enabled. +def GenericPostRAModel : GenericX86Model { + let PostRAScheduler = 1; +} diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86ScheduleAtom.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86ScheduleAtom.td new file mode 100644 index 0000000..daa6fc7 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86ScheduleAtom.td @@ -0,0 +1,917 @@ +//===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the schedule class data for the Intel Atom +// in order (Saltwell-32nm/Bonnell-45nm) processors. +// +//===----------------------------------------------------------------------===// + +// +// Scheduling information derived from the "Intel 64 and IA32 Architectures +// Optimization Reference Manual", Chapter 13, Section 4. + +// Atom machine model. +def AtomModel : SchedMachineModel { + let IssueWidth = 2; // Allows 2 instructions per scheduling group. + let MicroOpBufferSize = 0; // In-order execution, always hide latency. + let LoadLatency = 3; // Expected cycles, may be overridden. + let HighLatency = 30;// Expected, may be overridden. + + // On the Atom, the throughput for taken branches is 2 cycles. For small + // simple loops, expand by a small factor to hide the backedge cost. + let LoopMicroOpBufferSize = 10; + let PostRAScheduler = 1; + let CompleteModel = 0; +} + +let SchedModel = AtomModel in { + +// Functional Units +def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store + // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide +def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA + // SIMD/FP: SIMD ALU, FP Adder + +def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>; + +// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when dispatched by the schedulers. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass AtomWriteResPair RRPorts, + list RMPorts, + int RRLat = 1, int RMLat = 1, + list RRRes = [1], + list RMRes = [1]> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = RRLat; + let ResourceCycles = RRRes; + } + + // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the + // latency. + def : WriteRes { + let Latency = RMLat; + let ResourceCycles = RMRes; + } +} + +// A folded store needs a cycle on Port0 for the store data. +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Arithmetic. +//////////////////////////////////////////////////////////////////////////////// + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; + +defm : X86WriteResPairUnsupported; + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteRes; // x87 conditional move. + +def : WriteRes; +def : WriteRes { + let Latency = 2; + let ResourceCycles = [2]; +} +def : WriteRes { + let Latency = 2; + let ResourceCycles = [2]; +} +def : WriteRes; + +defm : X86WriteResUnsupported; + +// This is for simple LEAs with one or two input operands. +def : WriteRes; + +def AtomWriteIMul16Ld : SchedWriteRes<[AtomPort01]> { + let Latency = 8; + let ResourceCycles = [8]; +} +def : InstRW<[AtomWriteIMul16Ld], (instrs MUL16m, IMUL16m)>; + +def AtomWriteIMul32 : SchedWriteRes<[AtomPort01]> { + let Latency = 6; + let ResourceCycles = [6]; +} +def : InstRW<[AtomWriteIMul32], (instrs MUL32r, IMUL32r)>; + +def AtomWriteIMul64I : SchedWriteRes<[AtomPort01]> { + let Latency = 14; + let ResourceCycles = [14]; +} +def : InstRW<[AtomWriteIMul64I], (instrs IMUL64rri8, IMUL64rri32, + IMUL64rmi8, IMUL64rmi32)>; + +// Bit counts. +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +// BMI1 BEXTR, BMI2 BZHI +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Integer shifts and rotates. +//////////////////////////////////////////////////////////////////////////////// + +defm : AtomWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Loads, stores, and moves, not folded with other operations. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + +//////////////////////////////////////////////////////////////////////////////// +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +//////////////////////////////////////////////////////////////////////////////// + +defm : AtomWriteResPair; + +//////////////////////////////////////////////////////////////////////////////// +// Special case scheduling classes. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes { let Latency = 100; } +def : WriteRes { let Latency = 100; } +def : WriteRes; + +// Nops don't have dependencies, so there's no actual latency, but we set this +// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle. +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Floating point. This covers both scalar and vector operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteRes; +defm : X86WriteRes; +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; + +defm : X86WriteRes; + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Conversions. +//////////////////////////////////////////////////////////////////////////////// + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Vector integer operations. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; +def : WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; +def : WriteRes; +defm : X86WriteResUnsupported; +def : WriteRes; +defm : X86WriteResUnsupported; + +def : WriteRes; +def : WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Vector insert/extract operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : AtomWriteResPair; +def : WriteRes; +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// SSE42 String instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// MOVMSK Instructions. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes { let Latency = 3; let ResourceCycles = [3]; } +def : WriteRes { let Latency = 3; let ResourceCycles = [3]; } +defm : X86WriteResUnsupported; +def : WriteRes { let Latency = 3; let ResourceCycles = [3]; } + +//////////////////////////////////////////////////////////////////////////////// +// AES instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; + +//////////////////////////////////////////////////////////////////////////////// +// Carry-less multiplication instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Load/store MXCSR. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes { let Latency = 5; let ResourceCycles = [5]; } +def : WriteRes { let Latency = 15; let ResourceCycles = [15]; } + +//////////////////////////////////////////////////////////////////////////////// +// Special Cases. +//////////////////////////////////////////////////////////////////////////////// + +// Port0 +def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> { + let Latency = 1; + let ResourceCycles = [1]; +} +def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr, + MOVSX64rr32)>; +def : SchedAlias; +def : SchedAlias; +def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m", + "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>; + +def AtomWrite0_5 : SchedWriteRes<[AtomPort0]> { + let Latency = 5; + let ResourceCycles = [5]; +} +def : InstRW<[AtomWrite0_5], (instregex "IMUL32(rm|rr)")>; + +// Port1 +def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> { + let Latency = 1; + let ResourceCycles = [1]; +} +def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>; +def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r", + "BT(C|R|S)?(16|32|64)(rr|ri8)")>; + +def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> { + let Latency = 5; + let ResourceCycles = [5]; +} +def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm, + MMX_CVTPS2PIirr, MMX_CVTTPS2PIirr)>; + +// Port0 and Port1 +def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> { + let Latency = 1; + let ResourceCycles = [1, 1]; +} +def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r, + POP16rmr, POP32rmr, POP64rmr, + PUSH16r, PUSH32r, PUSH64r, + PUSHi16, PUSHi32, + PUSH16rmr, PUSH32rmr, PUSH64rmr, + PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32, + XCH_F)>; +def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$", + "IRET(16|32|64)?")>; + +def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> { + let Latency = 5; + let ResourceCycles = [5, 5]; +} +def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>; +def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>; + +// Port0 or Port1 +def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> { + let Latency = 1; + let ResourceCycles = [1]; +} +def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT, + LFENCE, + STOSB, STOSL, STOSQ, STOSW, + MOVSSrr, MOVSSrr_REV, + PSLLDQri, PSRLDQri)>; +def : InstRW<[AtomWrite01_1], (instregex "MMX_PACK(SSDW|SSWB|USWB)irr", + "MMX_PUNPCKH(BW|DQ|WD)irr")>; + +def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> { + let Latency = 2; + let ResourceCycles = [2]; +} +def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r, + PUSH16rmm, PUSH32rmm, PUSH64rmm, + LODSB, LODSL, LODSQ, LODSW, + SCASB, SCASL, SCASQ, SCASW)>; +def : InstRW<[AtomWrite01_2], (instregex "BT(C|R|S)(16|32|64)mi8", + "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)", + "XADD(8|16|32|64)rr", + "XCHG(8|16|32|64)(ar|rr)", + "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)", + "MMX_P(ADD|SUB)Qirr", + "MOV(S|Z)X16rr8", + "MOV(UPS|UPD|DQU)mr", + "MASKMOVDQU(64)?", + "P(ADD|SUB)Qrr")>; + +def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> { + let Latency = 3; + let ResourceCycles = [3]; +} +def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm, + CMPSB, CMPSL, CMPSQ, CMPSW, + MOVSB, MOVSL, MOVSQ, MOVSW, + POP16rmm, POP32rmm, POP64rmm)>; +def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm", + "XCHG(8|16|32|64)rm", + "PH(ADD|SUB)Drr", + "MOV(S|Z)X16rm8", + "MMX_P(ADD|SUB)Qirm", + "MOV(UPS|UPD|DQU)rm", + "P(ADD|SUB)Qrm")>; + +def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> { + let Latency = 4; + let ResourceCycles = [4]; +} +def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO, + JCXZ, JECXZ, JRCXZ, + LD_F80m)>; +def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm", + "(MMX_)?PEXTRWrr(_REV)?")>; + +def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> { + let Latency = 5; + let ResourceCycles = [5]; +} +def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>; +def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>; + +def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> { + let Latency = 6; + let ResourceCycles = [6]; +} +def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT, + SHLD16rrCL, SHRD16rrCL, + SHLD16rri8, SHRD16rri8, + SHLD16mrCL, SHRD16mrCL, + SHLD16mri8, SHRD16mri8)>; +def : InstRW<[AtomWrite01_6], (instregex "IMUL16rr", + "IST_F(P)?(16|32|64)?m", + "MMX_PH(ADD|SUB)S?Wrm")>; + +def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> { + let Latency = 7; + let ResourceCycles = [7]; +} +def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>; + +def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> { + let Latency = 8; + let ResourceCycles = [8]; +} +def : InstRW<[AtomWrite01_8], (instrs LOOPE, + PUSHA16, PUSHA32, + SHLD64rrCL, SHRD64rrCL, + FNSTCW16m)>; + +def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> { + let Latency = 9; + let ResourceCycles = [9]; +} +def : InstRW<[AtomWrite01_9], (instrs BT16mr, BT32mr, BT64mr, + POPA16, POPA32, + PUSHF16, PUSHF32, PUSHF64, + SHLD64mrCL, SHRD64mrCL, + SHLD64mri8, SHRD64mri8, + SHLD64rri8, SHRD64rri8, + CMPXCHG8rr)>; +def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F", + "(U)?COMIS(D|S)rr", + "CVT(T)?SS2SI64rr(_Int)?")>; + +def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> { + let Latency = 10; + let ResourceCycles = [10]; +} +def : SchedAlias; +def : InstRW<[AtomWrite01_10], (instregex "(U)?COMIS(D|S)rm", + "CVT(T)?SS2SI64rm(_Int)?")>; + +def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> { + let Latency = 11; + let ResourceCycles = [11]; +} +def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>; +def : InstRW<[AtomWrite01_11], (instregex "BT(C|R|S)(16|32|64)mr")>; + +def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> { + let Latency = 13; + let ResourceCycles = [13]; +} +def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>; + +def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> { + let Latency = 14; + let ResourceCycles = [14]; +} +def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>; + +def AtomWrite01_15 : SchedWriteRes<[AtomPort01]> { + let Latency = 15; + let ResourceCycles = [15]; +} +def : InstRW<[AtomWrite01_15], (instrs CMPXCHG16rr, CMPXCHG32rr, CMPXCHG64rr)>; + +def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> { + let Latency = 17; + let ResourceCycles = [17]; +} +def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>; + +def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> { + let Latency = 18; + let ResourceCycles = [18]; +} +def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>; + +def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> { + let Latency = 20; + let ResourceCycles = [20]; +} +def : InstRW<[AtomWrite01_20], (instrs DAS)>; + +def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> { + let Latency = 21; + let ResourceCycles = [21]; +} +def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>; + +def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> { + let Latency = 22; + let ResourceCycles = [22]; +} +def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>; + +def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> { + let Latency = 23; + let ResourceCycles = [23]; +} +def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>; + +def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> { + let Latency = 25; + let ResourceCycles = [25]; +} +def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>; + +def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> { + let Latency = 26; + let ResourceCycles = [26]; +} +def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>; + +def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> { + let Latency = 29; + let ResourceCycles = [29]; +} +def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>; + +def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> { + let Latency = 30; + let ResourceCycles = [30]; +} +def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>; + +def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> { + let Latency = 32; + let ResourceCycles = [32]; +} +def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>; + +def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> { + let Latency = 45; + let ResourceCycles = [45]; +} +def : InstRW<[AtomWrite01_45], (instrs MONITORrrr)>; + +def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> { + let Latency = 46; + let ResourceCycles = [46]; +} +def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>; + +def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> { + let Latency = 48; + let ResourceCycles = [48]; +} +def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>; + +def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> { + let Latency = 55; + let ResourceCycles = [55]; +} +def : InstRW<[AtomWrite01_55], (instrs FPREM)>; + +def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> { + let Latency = 59; + let ResourceCycles = [59]; +} +def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>; + +def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> { + let Latency = 63; + let ResourceCycles = [63]; +} +def : InstRW<[AtomWrite01_63], (instrs FNINIT)>; + +def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> { + let Latency = 68; + let ResourceCycles = [68]; +} +def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>; + +def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> { + let Latency = 71; + let ResourceCycles = [71]; +} +def : InstRW<[AtomWrite01_71], (instrs FPREM1, + INVLPG, INVLPGA32, INVLPGA64)>; + +def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> { + let Latency = 72; + let ResourceCycles = [72]; +} +def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>; + +def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> { + let Latency = 74; + let ResourceCycles = [74]; +} +def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>; + +def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> { + let Latency = 77; + let ResourceCycles = [77]; +} +def : InstRW<[AtomWrite01_77], (instrs FSCALE)>; + +def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> { + let Latency = 78; + let ResourceCycles = [78]; +} +def : InstRW<[AtomWrite01_78], (instrs RDMSR)>; + +def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> { + let Latency = 79; + let ResourceCycles = [79]; +} +def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$", + "LRETI?(L|Q|W)")>; + +def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> { + let Latency = 92; + let ResourceCycles = [92]; +} +def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>; + +def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> { + let Latency = 94; + let ResourceCycles = [94]; +} +def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>; + +def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> { + let Latency = 99; + let ResourceCycles = [99]; +} +def : InstRW<[AtomWrite01_99], (instrs F2XM1)>; + +def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> { + let Latency = 121; + let ResourceCycles = [121]; +} +def : InstRW<[AtomWrite01_121], (instrs CPUID)>; + +def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> { + let Latency = 127; + let ResourceCycles = [127]; +} +def : InstRW<[AtomWrite01_127], (instrs INT)>; + +def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> { + let Latency = 130; + let ResourceCycles = [130]; +} +def : InstRW<[AtomWrite01_130], (instrs INT3)>; + +def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> { + let Latency = 140; + let ResourceCycles = [140]; +} +def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>; + +def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> { + let Latency = 141; + let ResourceCycles = [141]; +} +def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>; + +def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> { + let Latency = 146; + let ResourceCycles = [146]; +} +def : InstRW<[AtomWrite01_146], (instrs FYL2X)>; + +def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> { + let Latency = 147; + let ResourceCycles = [147]; +} +def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>; + +def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> { + let Latency = 168; + let ResourceCycles = [168]; +} +def : InstRW<[AtomWrite01_168], (instrs FPTAN)>; + +def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> { + let Latency = 174; + let ResourceCycles = [174]; +} +def : InstRW<[AtomWrite01_174], (instrs FSINCOS)>; +def : InstRW<[AtomWrite01_174], (instregex "(COS|SIN)_F")>; + +def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> { + let Latency = 183; + let ResourceCycles = [183]; +} +def : InstRW<[AtomWrite01_183], (instrs FPATAN)>; + +def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> { + let Latency = 202; + let ResourceCycles = [202]; +} +def : InstRW<[AtomWrite01_202], (instrs WRMSR)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86ScheduleBtVer2.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86ScheduleBtVer2.td new file mode 100644 index 0000000..719e71c --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86ScheduleBtVer2.td @@ -0,0 +1,682 @@ +//=- X86ScheduleBtVer2.td - X86 BtVer2 (Jaguar) Scheduling ---*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for AMD btver2 (Jaguar) to support +// instruction scheduling and other instruction cost heuristics. Based off AMD Software +// Optimization Guide for AMD Family 16h Processors & Instruction Latency appendix. +// +//===----------------------------------------------------------------------===// + +def BtVer2Model : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and btver2 can + // decode 2 instructions per cycle. + let IssueWidth = 2; + let MicroOpBufferSize = 64; // Retire Control Unit + let LoadLatency = 5; // FPU latency (worse case cf Integer 3 cycle latency) + let HighLatency = 25; + let MispredictPenalty = 14; // Minimum branch misdirection penalty + let PostRAScheduler = 1; + + // FIXME: SSE4/AVX is unimplemented. This flag is set to allow + // the scheduler to assign a default model to unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = BtVer2Model in { + +// Jaguar can issue up to 6 micro-ops in one cycle +def JALU0 : ProcResource<1>; // Integer Pipe0: integer ALU0 (also handle FP->INT jam) +def JALU1 : ProcResource<1>; // Integer Pipe1: integer ALU1/MUL/DIV +def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU +def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA) +def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA +def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM + +// The Integer PRF for Jaguar is 64 entries, and it holds the architectural and +// speculative version of the 64-bit integer registers. +// Reference: www.realworldtech.com/jaguar/4/ +// +// The processor always keeps the different parts of an integer register +// together. An instruction that writes to a part of a register will therefore +// have a false dependence on any previous write to the same register or any +// part of it. +// Reference: Section 21.10 "AMD Bobcat and Jaguar pipeline: Partial register +// access" - Agner Fog's "microarchitecture.pdf". +def JIntegerPRF : RegisterFile<64, [GR64, CCR]>; + +// The Jaguar FP Retire Queue renames SIMD and FP uOps onto a pool of 72 SSE +// registers. Operations on 256-bit data types are cracked into two COPs. +// Reference: www.realworldtech.com/jaguar/4/ +def JFpuPRF: RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]>; + +// The retire control unit (RCU) can track up to 64 macro-ops in-flight. It can +// retire up to two macro-ops per cycle. +// Reference: "Software Optimization Guide for AMD Family 16h Processors" +def JRCU : RetireControlUnit<64, 2>; + +// Integer Pipe Scheduler +def JALU01 : ProcResGroup<[JALU0, JALU1]> { + let BufferSize=20; +} + +// AGU Pipe Scheduler +def JLSAGU : ProcResGroup<[JLAGU, JSAGU]> { + let BufferSize=12; +} + +// Fpu Pipe Scheduler +def JFPU01 : ProcResGroup<[JFPU0, JFPU1]> { + let BufferSize=18; +} + +// Functional units +def JDiv : ProcResource<1>; // integer division +def JMul : ProcResource<1>; // integer multiplication +def JVALU0 : ProcResource<1>; // vector integer +def JVALU1 : ProcResource<1>; // vector integer +def JVIMUL : ProcResource<1>; // vector integer multiplication +def JSTC : ProcResource<1>; // vector store/convert +def JFPM : ProcResource<1>; // FP multiplication +def JFPA : ProcResource<1>; // FP addition + +// Functional unit groups +def JFPX : ProcResGroup<[JFPA, JFPM]>; +def JVALU : ProcResGroup<[JVALU0, JVALU1]>; + +// Integer loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when dispatched by the schedulers. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass JWriteResIntPair ExePorts, + int Lat, list Res = [], int UOps = 1> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the + // latency. + def : WriteRes { + let Latency = !add(Lat, 3); + let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res)); + let NumMicroOps = UOps; + } +} + +multiclass JWriteResFpuPair ExePorts, + int Lat, list Res = [], int UOps = 1> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on JLAGU and adds 5 cycles to the + // latency. + def : WriteRes { + let Latency = !add(Lat, 5); + let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res)); + let NumMicroOps = UOps; + } +} + +multiclass JWriteResYMMPair ExePorts, + int Lat, list Res = [2], int UOps = 2> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses 2 cycles on JLAGU and adds 5 cycles to the + // latency. + def : WriteRes { + let Latency = !add(Lat, 5); + let ResourceCycles = !listconcat([2], Res); + let NumMicroOps = UOps; + } +} + +// A folded store needs a cycle on the SAGU for the store data. +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Arithmetic. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; // i8/i16/i32 multiplication +defm : JWriteResIntPair; // i64 multiplication +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; + +defm : JWriteResIntPair; + +defm : JWriteResIntPair; // Conditional move. +defm : JWriteResIntPair; // Conditional (CF + ZF flag) move. +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; // Setcc. +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// This is for simple LEAs with one or two input operands. +def : WriteRes; + +// Bit counts. +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; + +// BMI1 BEXTR, BMI2 BZHI +defm : JWriteResIntPair; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Integer shifts and rotates. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResIntPair; + +// SHLD/SHRD. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Loads, stores, and moves, not folded with other operations. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes { let Latency = 5; } +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// Load/store MXCSR. +// FIXME: These are copy and pasted from WriteLoad/Store. +def : WriteRes { let Latency = 5; } +def : WriteRes; + +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + +//////////////////////////////////////////////////////////////////////////////// +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResIntPair; + +//////////////////////////////////////////////////////////////////////////////// +// Special case scheduling classes. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes { let Latency = 100; } +def : WriteRes { let Latency = 100; } +def : WriteRes; + +// Nops don't have dependencies, so there's no actual latency, but we set this +// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle. +def : WriteRes { let Latency = 1; } + +//////////////////////////////////////////////////////////////////////////////// +// Floating point. This covers both scalar and vector operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Conversions. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; + +// FIXME: f+3 ST, LD+STC latency +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; + +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteResUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Vector integer operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Vector insert/extract operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +//////////////////////////////////////////////////////////////////////////////// +// SSE42 String instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; + +//////////////////////////////////////////////////////////////////////////////// +// MOVMSK Instructions. +//////////////////////////////////////////////////////////////////////////////// + +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +defm : X86WriteResUnsupported; +def : WriteRes { let Latency = 3; } + +//////////////////////////////////////////////////////////////////////////////// +// AES Instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResFpuPair; +defm : JWriteResYMMPair; +defm : JWriteResFpuPair; +defm : JWriteResFpuPair; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Carry-less multiplication instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : JWriteResFpuPair; + +//////////////////////////////////////////////////////////////////////////////// +// SSE4A instructions. +//////////////////////////////////////////////////////////////////////////////// + +def JWriteINSERTQ: SchedWriteRes<[JFPU01, JVALU]> { + let Latency = 2; + let ResourceCycles = [1, 4]; +} +def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>; + +//////////////////////////////////////////////////////////////////////////////// +// AVX instructions. +//////////////////////////////////////////////////////////////////////////////// + +def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> { + let Latency = 6; + let ResourceCycles = [1, 2, 4]; + let NumMicroOps = 2; +} +def : InstRW<[JWriteVBROADCASTYLd, ReadAfterLd], (instrs VBROADCASTSDYrm, + VBROADCASTSSYrm)>; + +def JWriteJVZEROALL: SchedWriteRes<[]> { + let Latency = 90; + let NumMicroOps = 73; +} +def : InstRW<[JWriteJVZEROALL], (instrs VZEROALL)>; + +def JWriteJVZEROUPPER: SchedWriteRes<[]> { + let Latency = 46; + let NumMicroOps = 37; +} +def : InstRW<[JWriteJVZEROUPPER], (instrs VZEROUPPER)>; + +/////////////////////////////////////////////////////////////////////////////// +// SchedWriteVariant definitions. +/////////////////////////////////////////////////////////////////////////////// + +def JWriteZeroLatency : SchedWriteRes<[]> { + let Latency = 0; +} + +// Certain instructions that use the same register for both source +// operands do not have a real dependency on the previous contents of the +// register, and thus, do not have to wait before completing. They can be +// optimized out at register renaming stage. +// Reference: Section 10.8 of the "Software Optimization Guide for AMD Family +// 15h Processors". +// Reference: Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", +// Section 21.8 [Dependency-breaking instructions]. + +def JWriteZeroIdiom : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteALU]> +]>; +def : InstRW<[JWriteZeroIdiom], (instrs SUB32rr, SUB64rr, + XOR32rr, XOR64rr)>; + +def JWriteFZeroIdiom : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteFLogic]> +]>; +def : InstRW<[JWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, VXORPDrr, + ANDNPSrr, VANDNPSrr, + ANDNPDrr, VANDNPDrr)>; + +def JWriteVZeroIdiomLogic : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteVecLogic]> +]>; +def : InstRW<[JWriteVZeroIdiomLogic], (instrs MMX_PXORirr, MMX_PANDNirr)>; + +def JWriteVZeroIdiomLogicX : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteVecLogicX]> +]>; +def : InstRW<[JWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr, + PANDNrr, VPANDNrr)>; + +def JWriteVZeroIdiomALU : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteVecALU]> +]>; +def : InstRW<[JWriteVZeroIdiomALU], (instrs MMX_PSUBBirr, MMX_PSUBDirr, + MMX_PSUBQirr, MMX_PSUBWirr, + MMX_PCMPGTBirr, MMX_PCMPGTDirr, + MMX_PCMPGTWirr)>; + +def JWriteVZeroIdiomALUX : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteVecALUX]> +]>; +def : InstRW<[JWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, + PSUBDrr, VPSUBDrr, + PSUBQrr, VPSUBQrr, + PSUBWrr, VPSUBWrr, + PCMPGTBrr, VPCMPGTBrr, + PCMPGTDrr, VPCMPGTDrr, + PCMPGTQrr, VPCMPGTQrr, + PCMPGTWrr, VPCMPGTWrr)>; + +// This write is used for slow LEA instructions. +def JWrite3OpsLEA : SchedWriteRes<[JALU1, JSAGU]> { + let Latency = 2; +} + +// On Jaguar, a slow LEA is either a 3Ops LEA (base, index, offset), or an LEA +// with a `Scale` value different than 1. +def JSlowLEAPredicate : MCSchedPredicate< + CheckAny<[ + // A 3-operand LEA (base, index, offset). + IsThreeOperandsLEAFn, + // An LEA with a "Scale" different than 1. + CheckAll<[ + CheckIsImmOperand<2>, + CheckNot> + ]> + ]> +>; + +def JWriteLEA : SchedWriteVariant<[ + SchedVar, + SchedVar, [WriteLEA]> +]>; + +def : InstRW<[JWriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>; + +def JSlowLEA16r : SchedWriteRes<[JALU01]> { + let Latency = 3; + let ResourceCycles = [4]; +} + +def : InstRW<[JSlowLEA16r], (instrs LEA16r)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86ScheduleSLM.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86ScheduleSLM.td new file mode 100644 index 0000000..b1e8430 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86ScheduleSLM.td @@ -0,0 +1,486 @@ +//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Intel Silvermont to support +// instruction scheduling and other instruction cost heuristics. +// +//===----------------------------------------------------------------------===// + +def SLMModel : SchedMachineModel { + // All x86 instructions are modeled as a single micro-op, and SLM can decode 2 + // instructions per cycle. + let IssueWidth = 2; + let MicroOpBufferSize = 32; // Based on the reorder buffer. + let LoadLatency = 3; + let MispredictPenalty = 10; + let PostRAScheduler = 1; + + // For small loops, expand by a small factor to hide the backedge cost. + let LoopMicroOpBufferSize = 10; + + // FIXME: SSE4 is unimplemented. This flag is set to allow + // the scheduler to assign a default model to unrecognized opcodes. + let CompleteModel = 0; +} + +let SchedModel = SLMModel in { + +// Silvermont has 5 reservation stations for micro-ops +def SLM_IEC_RSV0 : ProcResource<1>; +def SLM_IEC_RSV1 : ProcResource<1>; +def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; } +def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; } +def SLM_MEC_RSV : ProcResource<1>; + +// Many micro-ops are capable of issuing on multiple ports. +def SLM_IEC_RSV01 : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>; +def SLM_FPC_RSV01 : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>; + +def SLMDivider : ProcResource<1>; +def SLMFPMultiplier : ProcResource<1>; +def SLMFPDivider : ProcResource<1>; + +// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 +// cycles after the memory operand. +def : ReadAdvance; + +// Many SchedWrites are defined in pairs with and without a folded load. +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops when queued in the reservation station. +// This multiclass defines the resource usage for variants with and without +// folded loads. +multiclass SLMWriteResPair ExePorts, + int Lat, list Res = [1], int UOps = 1, + int LoadLat = 3> { + // Register variant is using a single cycle on ExePort. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to + // the latency (default = 3). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !listconcat([1], Res); + let NumMicroOps = UOps; + } +} + +// A folded store needs a cycle on MEC_RSV for the store data, but it does not +// need an extra port cycle to recompute the address. +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes { let Latency = 3; } +def : WriteRes; +def : WriteRes; + +// Load/store MXCSR. +// FIXME: These are probably wrong. They are copy pasted from WriteStore/Load. +def : WriteRes; +def : WriteRes { let Latency = 3; } + +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SLMWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteRes; // x87 conditional move. +def : WriteRes; +def : WriteRes { + // FIXME Latency and NumMicrOps? + let ResourceCycles = [2,1]; +} +def : WriteRes; +def : WriteRes; + +// This is for simple LEAs with one or two input operands. +// The complex ones can only execute on port 1, and they require two cycles on +// the port to read all inputs. We don't model that. +def : WriteRes; + +// Bit counts. +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; + +// BMI1 BEXTR, BMI2 BZHI +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; + +// Scalar and vector floating point. +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +defm : X86WriteRes; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; + +// Conversion between integer and float. +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; + +// Vector integer operations. +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +// FIXME: The below is closer to correct, but caused some perf regressions. +//defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; + +// Vector insert/extract operations. +defm : SLMWriteResPair; + +def : WriteRes; +def : WriteRes { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1, 2]; +} + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; + +// String instructions. +// Packed Compare Implicit Length Strings, Return Mask +def : WriteRes { + let Latency = 13; + let ResourceCycles = [13]; +} +def : WriteRes { + let Latency = 13; + let ResourceCycles = [13, 1]; +} + +// Packed Compare Explicit Length Strings, Return Mask +def : WriteRes { + let Latency = 17; + let ResourceCycles = [17]; +} +def : WriteRes { + let Latency = 17; + let ResourceCycles = [17, 1]; +} + +// Packed Compare Implicit Length Strings, Return Index +def : WriteRes { + let Latency = 17; + let ResourceCycles = [17]; +} +def : WriteRes { + let Latency = 17; + let ResourceCycles = [17, 1]; +} + +// Packed Compare Explicit Length Strings, Return Index +def : WriteRes { + let Latency = 21; + let ResourceCycles = [21]; +} +def : WriteRes { + let Latency = 21; + let ResourceCycles = [21, 1]; +} + +// MOVMSK Instructions. +def : WriteRes { let Latency = 4; } +def : WriteRes { let Latency = 4; } +def : WriteRes { let Latency = 4; } +def : WriteRes { let Latency = 4; } + +// AES Instructions. +def : WriteRes { + let Latency = 8; + let ResourceCycles = [5]; +} +def : WriteRes { + let Latency = 8; + let ResourceCycles = [5, 1]; +} + +def : WriteRes { + let Latency = 8; + let ResourceCycles = [5]; +} +def : WriteRes { + let Latency = 8; + let ResourceCycles = [5, 1]; +} + +def : WriteRes { + let Latency = 8; + let ResourceCycles = [5]; +} +def : WriteRes { + let Latency = 8; + let ResourceCycles = [5, 1]; +} + +// Carry-less multiplication instructions. +def : WriteRes { + let Latency = 10; + let ResourceCycles = [10]; +} +def : WriteRes { + let Latency = 10; + let ResourceCycles = [10, 1]; +} + +def : WriteRes { let Latency = 100; } +def : WriteRes { let Latency = 100; } +def : WriteRes; +def : WriteRes; + +// AVX/FMA is not supported on that architecture, but we should define the basic +// scheduling resources anyway. +def : WriteRes; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : SLMWriteResPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86ScheduleZnver1.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86ScheduleZnver1.td new file mode 100644 index 0000000..7184b85 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86ScheduleZnver1.td @@ -0,0 +1,1544 @@ +//=- X86ScheduleZnver1.td - X86 Znver1 Scheduling -------------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Znver1 to support instruction +// scheduling and other instruction cost heuristics. +// +//===----------------------------------------------------------------------===// + +def Znver1Model : SchedMachineModel { + // Zen can decode 4 instructions per cycle. + let IssueWidth = 4; + // Based on the reorder buffer we define MicroOpBufferSize + let MicroOpBufferSize = 192; + let LoadLatency = 4; + let MispredictPenalty = 17; + let HighLatency = 25; + let PostRAScheduler = 1; + + // FIXME: This variable is required for incomplete model. + // We haven't catered all instructions. + // So, we reset the value of this variable so as to + // say that the model is incomplete. + let CompleteModel = 0; +} + +let SchedModel = Znver1Model in { + +// Zen can issue micro-ops to 10 different units in one cycle. +// These are +// * Four integer ALU units (ZALU0, ZALU1, ZALU2, ZALU3) +// * Two AGU units (ZAGU0, ZAGU1) +// * Four FPU units (ZFPU0, ZFPU1, ZFPU2, ZFPU3) +// AGUs feed load store queues @two loads and 1 store per cycle. + +// Four ALU units are defined below +def ZnALU0 : ProcResource<1>; +def ZnALU1 : ProcResource<1>; +def ZnALU2 : ProcResource<1>; +def ZnALU3 : ProcResource<1>; + +// Two AGU units are defined below +def ZnAGU0 : ProcResource<1>; +def ZnAGU1 : ProcResource<1>; + +// Four FPU units are defined below +def ZnFPU0 : ProcResource<1>; +def ZnFPU1 : ProcResource<1>; +def ZnFPU2 : ProcResource<1>; +def ZnFPU3 : ProcResource<1>; + +// FPU grouping +def ZnFPU013 : ProcResGroup<[ZnFPU0, ZnFPU1, ZnFPU3]>; +def ZnFPU01 : ProcResGroup<[ZnFPU0, ZnFPU1]>; +def ZnFPU12 : ProcResGroup<[ZnFPU1, ZnFPU2]>; +def ZnFPU13 : ProcResGroup<[ZnFPU1, ZnFPU3]>; +def ZnFPU23 : ProcResGroup<[ZnFPU2, ZnFPU3]>; +def ZnFPU02 : ProcResGroup<[ZnFPU0, ZnFPU2]>; +def ZnFPU03 : ProcResGroup<[ZnFPU0, ZnFPU3]>; + +// Below are the grouping of the units. +// Micro-ops to be issued to multiple units are tackled this way. + +// ALU grouping +// ZnALU03 - 0,3 grouping +def ZnALU03: ProcResGroup<[ZnALU0, ZnALU3]>; + +// 56 Entry (14x4 entries) Int Scheduler +def ZnALU : ProcResGroup<[ZnALU0, ZnALU1, ZnALU2, ZnALU3]> { + let BufferSize=56; +} + +// 28 Entry (14x2) AGU group. AGUs can't be used for all ALU operations +// but are relevant for some instructions +def ZnAGU : ProcResGroup<[ZnAGU0, ZnAGU1]> { + let BufferSize=28; +} + +// Integer Multiplication issued on ALU1. +def ZnMultiplier : ProcResource<1>; + +// Integer division issued on ALU2. +def ZnDivider : ProcResource<1>; + +// 4 Cycles load-to use Latency is captured +def : ReadAdvance; + +// The Integer PRF for Zen is 168 entries, and it holds the architectural and +// speculative version of the 64-bit integer registers. +// Reference: "Software Optimization Guide for AMD Family 17h Processors" +def ZnIntegerPRF : RegisterFile<168, [GR64, CCR]>; + +// 36 Entry (9x4 entries) floating-point Scheduler +def ZnFPU : ProcResGroup<[ZnFPU0, ZnFPU1, ZnFPU2, ZnFPU3]> { +let BufferSize=36; +} + +// The Zen FP Retire Queue renames SIMD and FP uOps onto a pool of 160 128-bit +// registers. Operations on 256-bit data types are cracked into two COPs. +// Reference: "Software Optimization Guide for AMD Family 17h Processors" +def ZnFpuPRF: RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>; + +// The unit can track up to 192 macro ops in-flight. +// The retire unit handles in-order commit of up to 8 macro ops per cycle. +// Reference: "Software Optimization Guide for AMD Family 17h Processors" +// To be noted, the retire unit is shared between integer and FP ops. +// In SMT mode it is 96 entry per thread. But, we do not use the conservative +// value here because there is currently no way to fully mode the SMT mode, +// so there is no point in trying. +def ZnRCU : RetireControlUnit<192, 8>; + +// FIXME: there are 72 read buffers and 44 write buffers. + +// (a folded load is an instruction that loads and does some operation) +// Ex: ADDPD xmm,[mem]-> This instruction has two micro-ops +// Instructions with folded loads are usually micro-fused, so they only appear +// as two micro-ops. +// a. load and +// b. addpd +// This multiclass is for folded loads for integer units. +multiclass ZnWriteResPair ExePorts, + int Lat, list Res = [], int UOps = 1, + int LoadLat = 4, int LoadUOps = 1> { + // Register variant takes 1-cycle on Execution Port. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on ZnAGU + // adds LoadLat cycles to the latency (default = 4). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res)); + let NumMicroOps = !add(UOps, LoadUOps); + } +} + +// This multiclass is for folded loads for floating point units. +multiclass ZnWriteResFpuPair ExePorts, + int Lat, list Res = [], int UOps = 1, + int LoadLat = 7, int LoadUOps = 0> { + // Register variant takes 1-cycle on Execution Port. + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } + + // Memory variant also uses a cycle on ZnAGU + // adds LoadLat cycles to the latency (default = 7). + def : WriteRes { + let Latency = !add(Lat, LoadLat); + let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res)); + let NumMicroOps = !add(UOps, LoadUOps); + } +} + +// WriteRMW is set for instructions with Memory write +// operation in codegen +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes { let Latency = 8; } + +def : WriteRes; +def : WriteRes; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; + +defm : X86WriteRes; +defm : X86WriteRes; + +defm : ZnWriteResPair; + +defm : X86WriteRes; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +defm : ZnWriteResPair; +defm : ZnWriteResFpuPair; + +defm : ZnWriteResPair; +defm : ZnWriteResPair; +def : WriteRes; +def : WriteRes; +defm : X86WriteRes; +def : WriteRes; + +// Bit counts. +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; + +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + +// BMI1 BEXTR, BMI2 BZHI +defm : ZnWriteResPair; +defm : ZnWriteResPair; + +// IDIV +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; + +// IMULH +def : WriteRes{ + let Latency = 4; +} + +// Floating point operations +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +//defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +//defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; // FIXME: Should folds require 1 extra uops? +defm : ZnWriteResFpuPair; // FIXME: Should folds require 1 extra uops? +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +//defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +//defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; + +// Vector integer operations which uses FPU units +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; + +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; // FIXME +defm : ZnWriteResFpuPair; // FIXME +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; +defm : ZnWriteResFpuPair; + +// Vector Shift Operations +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : X86WriteResPairUnsupported; + +// Vector insert/extract operations. +defm : ZnWriteResFpuPair; + +def : WriteRes { + let Latency = 2; + let ResourceCycles = [1, 2]; +} +def : WriteRes { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1, 2, 3]; +} + +// MOVMSK Instructions. +def : WriteRes; +def : WriteRes; +def : WriteRes; + +def : WriteRes { + let NumMicroOps = 2; + let Latency = 2; + let ResourceCycles = [2]; +} + +// AES Instructions. +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; + +def : WriteRes; +def : WriteRes; + +// Following instructions with latency=100 are microcoded. +// We set long latency so as to block the entire pipeline. +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; + +// Microcoded Instructions +def ZnWriteMicrocoded : SchedWriteRes<[]> { + let Latency = 100; +} + +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; + +//=== Regex based InstRW ===// +// Notation: +// - r: register. +// - m = memory. +// - i = immediate +// - mm: 64 bit mmx register. +// - x = 128 bit xmm register. +// - (x)mm = mmx or xmm register. +// - y = 256 bit ymm register. +// - v = any vector register. + +//=== Integer Instructions ===// +//-- Move instructions --// +// MOV. +// r16,m. +def : InstRW<[WriteALULd, ReadAfterLd], (instregex "MOV16rm")>; + +// MOVSX, MOVZX. +// r,m. +def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>; + +// XCHG. +// r,r. +def ZnWriteXCHG : SchedWriteRes<[ZnALU]> { + let NumMicroOps = 2; + let ResourceCycles = [2]; +} + +def : InstRW<[ZnWriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>; + +// r,m. +def ZnWriteXCHGrm : SchedWriteRes<[ZnAGU, ZnALU]> { + let Latency = 5; + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteXCHGrm, ReadAfterLd], (instregex "XCHG(8|16|32|64)rm")>; + +def : InstRW<[WriteMicrocoded], (instrs XLAT)>; + +// POP16. +// r. +def ZnWritePop16r : SchedWriteRes<[ZnAGU]>{ + let Latency = 5; + let NumMicroOps = 2; +} +def : InstRW<[ZnWritePop16r], (instregex "POP16rmm")>; +def : InstRW<[WriteMicrocoded], (instregex "POPF(16|32)")>; +def : InstRW<[WriteMicrocoded], (instregex "POPA(16|32)")>; + + +// PUSH. +// r. Has default values. +// m. +def ZnWritePUSH : SchedWriteRes<[ZnAGU]>{ + let Latency = 4; +} +def : InstRW<[ZnWritePUSH], (instregex "PUSH(16|32)rmm")>; + +//PUSHF +def : InstRW<[WriteMicrocoded], (instregex "PUSHF(16|32)")>; + +// PUSHA. +def ZnWritePushA : SchedWriteRes<[ZnAGU]> { + let Latency = 8; +} +def : InstRW<[ZnWritePushA], (instregex "PUSHA(16|32)")>; + +//LAHF +def : InstRW<[WriteMicrocoded], (instrs LAHF)>; + +// MOVBE. +// r,m. +def ZnWriteMOVBE : SchedWriteRes<[ZnAGU, ZnALU]> { + let Latency = 5; +} +def : InstRW<[ZnWriteMOVBE, ReadAfterLd], (instregex "MOVBE(16|32|64)rm")>; + +// m16,r16. +def : InstRW<[ZnWriteMOVBE], (instregex "MOVBE(16|32|64)mr")>; + +//-- Arithmetic instructions --// + +// ADD SUB. +// m,r/i. +def : InstRW<[WriteALULd], (instregex "(ADD|SUB)(8|16|32|64)m(r|i)", + "(ADD|SUB)(8|16|32|64)mi8", + "(ADD|SUB)64mi32")>; + +// ADC SBB. +// m,r/i. +def : InstRW<[WriteALULd], + (instregex "(ADC|SBB)(8|16|32|64)m(r|i)", + "(ADC|SBB)(16|32|64)mi8", + "(ADC|SBB)64mi32")>; + +// INC DEC NOT NEG. +// m. +def : InstRW<[WriteALULd], + (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m")>; + +// MUL IMUL. +// r16. +def ZnWriteMul16 : SchedWriteRes<[ZnALU1, ZnMultiplier]> { + let Latency = 3; +} +def : InstRW<[ZnWriteMul16], (instrs IMUL16r, MUL16r)>; +def : InstRW<[ZnWriteMul16], (instrs IMUL16rr, IMUL16rri, IMUL16rri8)>; // TODO: is this right? +def : InstRW<[ZnWriteMul16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>; // TODO: this is definitely wrong but matches what the instregex did. + +// m16. +def ZnWriteMul16Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { + let Latency = 8; +} +def : InstRW<[ZnWriteMul16Ld, ReadAfterLd], (instrs IMUL16m, MUL16m)>; + +// r32. +def ZnWriteMul32 : SchedWriteRes<[ZnALU1, ZnMultiplier]> { + let Latency = 3; +} +def : InstRW<[ZnWriteMul32], (instrs IMUL32r, MUL32r)>; +def : InstRW<[ZnWriteMul32], (instrs IMUL32rr, IMUL32rri, IMUL32rri8)>; // TODO: is this right? +def : InstRW<[ZnWriteMul32], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8)>; // TODO: this is definitely wrong but matches what the instregex did. + +// m32. +def ZnWriteMul32Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { + let Latency = 8; +} +def : InstRW<[ZnWriteMul32Ld, ReadAfterLd], (instrs IMUL32m, MUL32m)>; + +// r64. +def ZnWriteMul64 : SchedWriteRes<[ZnALU1, ZnMultiplier]> { + let Latency = 4; + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteMul64], (instrs IMUL64r, MUL64r)>; +def : InstRW<[ZnWriteMul64], (instrs IMUL64rr, IMUL64rri8, IMUL64rri32)>; // TODO: is this right? +def : InstRW<[ZnWriteMul64], (instrs IMUL64rm, IMUL64rmi32, IMUL64rmi8)>; // TODO: this is definitely wrong but matches what the instregex did. + +// m64. +def ZnWriteMul64Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { + let Latency = 9; + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteMul64Ld, ReadAfterLd], (instrs IMUL64m, MUL64m)>; + +// MULX. +// r32,r32,r32. +def ZnWriteMulX32 : SchedWriteRes<[ZnALU1, ZnMultiplier]> { + let Latency = 3; + let ResourceCycles = [1, 2]; +} +def : InstRW<[ZnWriteMulX32], (instrs MULX32rr)>; + +// r32,r32,m32. +def ZnWriteMulX32Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { + let Latency = 8; + let ResourceCycles = [1, 2, 2]; +} +def : InstRW<[ZnWriteMulX32Ld, ReadAfterLd], (instrs MULX32rm)>; + +// r64,r64,r64. +def ZnWriteMulX64 : SchedWriteRes<[ZnALU1]> { + let Latency = 3; +} +def : InstRW<[ZnWriteMulX64], (instrs MULX64rr)>; + +// r64,r64,m64. +def ZnWriteMulX64Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { + let Latency = 8; +} +def : InstRW<[ZnWriteMulX64Ld, ReadAfterLd], (instrs MULX64rm)>; + +//-- Control transfer instructions --// + +// J(E|R)CXZ. +def ZnWriteJCXZ : SchedWriteRes<[ZnALU03]>; +def : InstRW<[ZnWriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>; + +// INTO +def : InstRW<[WriteMicrocoded], (instrs INTO)>; + +// LOOP. +def ZnWriteLOOP : SchedWriteRes<[ZnALU03]>; +def : InstRW<[ZnWriteLOOP], (instrs LOOP)>; + +// LOOP(N)E, LOOP(N)Z +def ZnWriteLOOPE : SchedWriteRes<[ZnALU03]>; +def : InstRW<[ZnWriteLOOPE], (instrs LOOPE, LOOPNE)>; + +// CALL. +// r. +def ZnWriteCALLr : SchedWriteRes<[ZnAGU, ZnALU03]>; +def : InstRW<[ZnWriteCALLr], (instregex "CALL(16|32)r")>; + +def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>; + +// RET. +def ZnWriteRET : SchedWriteRes<[ZnALU03]> { + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)", + "IRET(16|32|64)")>; + +//-- Logic instructions --// + +// AND OR XOR. +// m,r/i. +def : InstRW<[WriteALULd], + (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)", + "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>; + +// Define ALU latency variants +def ZnWriteALULat2 : SchedWriteRes<[ZnALU]> { + let Latency = 2; +} +def ZnWriteALULat2Ld : SchedWriteRes<[ZnAGU, ZnALU]> { + let Latency = 6; +} + +// BT. +// m,i. +def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>; + +// BTR BTS BTC. +// r,r,i. +def ZnWriteBTRSC : SchedWriteRes<[ZnALU]> { + let Latency = 2; + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteBTRSC], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>; + +// m,r,i. +def ZnWriteBTRSCm : SchedWriteRes<[ZnAGU, ZnALU]> { + let Latency = 6; + let NumMicroOps = 2; +} +// m,r,i. +def : InstRW<[ZnWriteBTRSCm], (instregex "BT(R|S|C)(16|32|64)m(r|i8)")>; + +// BLSI BLSMSK BLSR. +// r,r. +def : InstRW<[ZnWriteALULat2], (instregex "BLS(I|MSK|R)(32|64)rr")>; +// r,m. +def : InstRW<[ZnWriteALULat2Ld], (instregex "BLS(I|MSK|R)(32|64)rm")>; + +// CLD STD. +def : InstRW<[WriteALU], (instrs STD, CLD)>; + +// PDEP PEXT. +// r,r,r. +def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>; +// r,r,m. +def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>; + +// RCR RCL. +// m,i. +def : InstRW<[WriteMicrocoded], (instregex "RC(R|L)(8|16|32|64)m(1|i|CL)")>; + +// SHR SHL SAR. +// m,i. +def : InstRW<[WriteShiftLd], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>; + +// SHRD SHLD. +// m,r +def : InstRW<[WriteShiftLd], (instregex "SH(R|L)D(16|32|64)mri8")>; + +// r,r,cl. +def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)rrCL")>; + +// m,r,cl. +def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>; + +//-- Misc instructions --// +// CMPXCHG. +def ZnWriteCMPXCHG : SchedWriteRes<[ZnAGU, ZnALU]> { + let Latency = 8; + let NumMicroOps = 5; +} +def : InstRW<[ZnWriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>; + +// CMPXCHG8B. +def ZnWriteCMPXCHG8B : SchedWriteRes<[ZnAGU, ZnALU]> { + let NumMicroOps = 18; +} +def : InstRW<[ZnWriteCMPXCHG8B], (instrs CMPXCHG8B)>; + +def : InstRW<[WriteMicrocoded], (instrs CMPXCHG16B)>; + +// LEAVE +def ZnWriteLEAVE : SchedWriteRes<[ZnALU, ZnAGU]> { + let Latency = 8; + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteLEAVE], (instregex "LEAVE")>; + +// PAUSE. +def : InstRW<[WriteMicrocoded], (instrs PAUSE)>; + +// RDTSC. +def : InstRW<[WriteMicrocoded], (instregex "RDTSC")>; + +// RDPMC. +def : InstRW<[WriteMicrocoded], (instrs RDPMC)>; + +// RDRAND. +def : InstRW<[WriteMicrocoded], (instregex "RDRAND(16|32|64)r")>; + +// XGETBV. +def : InstRW<[WriteMicrocoded], (instregex "XGETBV")>; + +//-- String instructions --// +// CMPS. +def : InstRW<[WriteMicrocoded], (instregex "CMPS(B|L|Q|W)")>; + +// LODSB/W. +def : InstRW<[WriteMicrocoded], (instregex "LODS(B|W)")>; + +// LODSD/Q. +def : InstRW<[WriteMicrocoded], (instregex "LODS(L|Q)")>; + +// MOVS. +def : InstRW<[WriteMicrocoded], (instregex "MOVS(B|L|Q|W)")>; + +// SCAS. +def : InstRW<[WriteMicrocoded], (instregex "SCAS(B|W|L|Q)")>; + +// STOS +def : InstRW<[WriteMicrocoded], (instregex "STOS(B|L|Q|W)")>; + +// XADD. +def : InstRW<[WriteMicrocoded], (instregex "XADD(8|16|32|64)rm")>; + +//=== Floating Point x87 Instructions ===// +//-- Move instructions --// + +def ZnWriteFLDr : SchedWriteRes<[ZnFPU13]> ; + +def ZnWriteSTr: SchedWriteRes<[ZnFPU23]> { + let Latency = 5; + let NumMicroOps = 2; +} + +// LD_F. +// r. +def : InstRW<[ZnWriteFLDr], (instregex "LD_Frr")>; + +// m. +def ZnWriteLD_F80m : SchedWriteRes<[ZnAGU, ZnFPU13]> { + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteLD_F80m], (instregex "LD_F80m")>; + +// FBLD. +def : InstRW<[WriteMicrocoded], (instregex "FBLDm")>; + +// FST(P). +// r. +def : InstRW<[ZnWriteSTr], (instregex "ST_(F|FP)rr")>; + +// m80. +def ZnWriteST_FP80m : SchedWriteRes<[ZnAGU, ZnFPU23]> { + let Latency = 5; +} +def : InstRW<[ZnWriteST_FP80m], (instregex "ST_FP80m")>; + +// FBSTP. +// m80. +def : InstRW<[WriteMicrocoded], (instregex "FBSTPm")>; + +def ZnWriteFXCH : SchedWriteRes<[ZnFPU]>; + +// FXCHG. +def : InstRW<[ZnWriteFXCH], (instrs XCH_F)>; + +// FILD. +def ZnWriteFILD : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 11; + let NumMicroOps = 2; +} +def : InstRW<[ZnWriteFILD], (instregex "ILD_F(16|32|64)m")>; + +// FIST(P) FISTTP. +def ZnWriteFIST : SchedWriteRes<[ZnAGU, ZnFPU23]> { + let Latency = 12; +} +def : InstRW<[ZnWriteFIST], (instregex "IS(T|TT)_(F|FP)(16|32|64)m")>; + +def ZnWriteFPU13 : SchedWriteRes<[ZnAGU, ZnFPU13]> { + let Latency = 8; +} + +def ZnWriteFPU3 : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 11; +} + +// FLDZ. +def : SchedAlias; + +// FLD1. +def : SchedAlias; + +// FLDPI FLDL2E etc. +def : SchedAlias; + +// FNSTSW. +// AX. +def : InstRW<[WriteMicrocoded], (instrs FNSTSW16r)>; + +// m16. +def : InstRW<[WriteMicrocoded], (instrs FNSTSWm)>; + +// FLDCW. +def : InstRW<[WriteMicrocoded], (instrs FLDCW16m)>; + +// FNSTCW. +def : InstRW<[WriteMicrocoded], (instrs FNSTCW16m)>; + +// FINCSTP FDECSTP. +def : InstRW<[ZnWriteFPU3], (instrs FINCSTP, FDECSTP)>; + +// FFREE. +def : InstRW<[ZnWriteFPU3], (instregex "FFREE")>; + +// FNSAVE. +def : InstRW<[WriteMicrocoded], (instregex "FSAVEm")>; + +// FRSTOR. +def : InstRW<[WriteMicrocoded], (instregex "FRSTORm")>; + +//-- Arithmetic instructions --// + +def ZnWriteFPU3Lat1 : SchedWriteRes<[ZnFPU3]> ; + +def ZnWriteFPU0Lat1 : SchedWriteRes<[ZnFPU0]> ; + +def ZnWriteFPU0Lat1Ld : SchedWriteRes<[ZnAGU, ZnFPU0]> { + let Latency = 8; +} + +// FCHS. +def : InstRW<[ZnWriteFPU3Lat1], (instregex "CHS_F")>; + +// FCOM(P) FUCOM(P). +// r. +def : InstRW<[ZnWriteFPU0Lat1], (instregex "COM(P?)_FST0r", "UCOM_F(P?)r")>; +// m. +def : InstRW<[ZnWriteFPU0Lat1Ld], (instregex "FCOM(P?)(32|64)m")>; + +// FCOMPP FUCOMPP. +// r. +def : InstRW<[ZnWriteFPU0Lat1], (instrs FCOMPP, UCOM_FPPr)>; + +def ZnWriteFPU02 : SchedWriteRes<[ZnAGU, ZnFPU02]> +{ + let Latency = 9; +} + +// FCOMI(P) FUCOMI(P). +// m. +def : InstRW<[ZnWriteFPU02], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; + +def ZnWriteFPU03 : SchedWriteRes<[ZnAGU, ZnFPU03]> +{ + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,3]; +} + +// FICOM(P). +def : InstRW<[ZnWriteFPU03], (instregex "FICOM(P?)(16|32)m")>; + +// FTST. +def : InstRW<[ZnWriteFPU0Lat1], (instregex "TST_F")>; + +// FXAM. +def : InstRW<[ZnWriteFPU3Lat1], (instrs FXAM)>; + +// FPREM. +def : InstRW<[WriteMicrocoded], (instrs FPREM)>; + +// FPREM1. +def : InstRW<[WriteMicrocoded], (instrs FPREM1)>; + +// FRNDINT. +def : InstRW<[WriteMicrocoded], (instrs FRNDINT)>; + +// FSCALE. +def : InstRW<[WriteMicrocoded], (instrs FSCALE)>; + +// FXTRACT. +def : InstRW<[WriteMicrocoded], (instrs FXTRACT)>; + +// FNOP. +def : InstRW<[ZnWriteFPU0Lat1], (instrs FNOP)>; + +// WAIT. +def : InstRW<[ZnWriteFPU0Lat1], (instrs WAIT)>; + +// FNCLEX. +def : InstRW<[WriteMicrocoded], (instrs FNCLEX)>; + +// FNINIT. +def : InstRW<[WriteMicrocoded], (instrs FNINIT)>; + +//=== Integer MMX and XMM Instructions ===// + +// PACKSSWB/DW. +// mm <- mm. +def ZnWriteFPU12 : SchedWriteRes<[ZnFPU12]> ; +def ZnWriteFPU12Y : SchedWriteRes<[ZnFPU12]> { + let NumMicroOps = 2; +} +def ZnWriteFPU12m : SchedWriteRes<[ZnAGU, ZnFPU12]> ; +def ZnWriteFPU12Ym : SchedWriteRes<[ZnAGU, ZnFPU12]> { + let Latency = 8; + let NumMicroOps = 2; +} + +def : InstRW<[ZnWriteFPU12], (instrs MMX_PACKSSDWirr, + MMX_PACKSSWBirr, + MMX_PACKUSWBirr)>; +def : InstRW<[ZnWriteFPU12m], (instrs MMX_PACKSSDWirm, + MMX_PACKSSWBirm, + MMX_PACKUSWBirm)>; + +// VPMOVSX/ZX BW BD BQ WD WQ DQ. +// y <- x. +def : InstRW<[ZnWriteFPU12Y], (instregex "VPMOV(SX|ZX)(BW|BD|BQ|WD|WQ|DQ)Yrr")>; +def : InstRW<[ZnWriteFPU12Ym], (instregex "VPMOV(SX|ZX)(BW|BD|BQ|WD|WQ|DQ)Yrm")>; + +def ZnWriteFPU013 : SchedWriteRes<[ZnFPU013]> ; +def ZnWriteFPU013Y : SchedWriteRes<[ZnFPU013]> { + let Latency = 2; +} +def ZnWriteFPU013m : SchedWriteRes<[ZnAGU, ZnFPU013]> { + let Latency = 8; + let NumMicroOps = 2; +} +def ZnWriteFPU013Ld : SchedWriteRes<[ZnAGU, ZnFPU013]> { + let Latency = 8; + let NumMicroOps = 2; +} +def ZnWriteFPU013LdY : SchedWriteRes<[ZnAGU, ZnFPU013]> { + let Latency = 9; + let NumMicroOps = 2; +} + +// PBLENDW. +// x,x,i / v,v,v,i +def : InstRW<[ZnWriteFPU013], (instregex "(V?)PBLENDWrri")>; +// ymm +def : InstRW<[ZnWriteFPU013Y], (instrs VPBLENDWYrri)>; + +// x,m,i / v,v,m,i +def : InstRW<[ZnWriteFPU013Ld], (instregex "(V?)PBLENDWrmi")>; +// y,m,i +def : InstRW<[ZnWriteFPU013LdY], (instrs VPBLENDWYrmi)>; + +def ZnWriteFPU01 : SchedWriteRes<[ZnFPU01]> ; +def ZnWriteFPU01Y : SchedWriteRes<[ZnFPU01]> { + let NumMicroOps = 2; +} + +// VPBLENDD. +// v,v,v,i. +def : InstRW<[ZnWriteFPU01], (instrs VPBLENDDrri)>; +// ymm +def : InstRW<[ZnWriteFPU01Y], (instrs VPBLENDDYrri)>; + +// v,v,m,i +def ZnWriteFPU01Op2 : SchedWriteRes<[ZnAGU, ZnFPU01]> { + let NumMicroOps = 2; + let Latency = 8; + let ResourceCycles = [1, 2]; +} +def ZnWriteFPU01Op2Y : SchedWriteRes<[ZnAGU, ZnFPU01]> { + let NumMicroOps = 2; + let Latency = 9; + let ResourceCycles = [1, 3]; +} +def : InstRW<[ZnWriteFPU01Op2], (instrs VPBLENDDrmi)>; +def : InstRW<[ZnWriteFPU01Op2Y], (instrs VPBLENDDYrmi)>; + +// MASKMOVQ. +def : InstRW<[WriteMicrocoded], (instregex "MMX_MASKMOVQ(64)?")>; + +// MASKMOVDQU. +def : InstRW<[WriteMicrocoded], (instregex "(V?)MASKMOVDQU(64)?")>; + +// VPMASKMOVD. +// ymm +def : InstRW<[WriteMicrocoded], + (instregex "VPMASKMOVD(Y?)rm")>; +// m, v,v. +def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>; + +// VPBROADCAST B/W. +// x, m8/16. +def ZnWriteVPBROADCAST128Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1, 2]; +} +def : InstRW<[ZnWriteVPBROADCAST128Ld], + (instregex "VPBROADCAST(B|W)rm")>; + +// y, m8/16 +def ZnWriteVPBROADCAST256Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1, 2]; +} +def : InstRW<[ZnWriteVPBROADCAST256Ld], + (instregex "VPBROADCAST(B|W)Yrm")>; + +// VPGATHER. +def : InstRW<[WriteMicrocoded], (instregex "VPGATHER(Q|D)(Q|D)(Y?)rm")>; + +//-- Arithmetic instructions --// + +// HADD, HSUB PS/PD +// PHADD|PHSUB (S) W/D. +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; + +// PCMPGTQ. +def ZnWritePCMPGTQr : SchedWriteRes<[ZnFPU03]>; +def : InstRW<[ZnWritePCMPGTQr], (instregex "(V?)PCMPGTQ(Y?)rr")>; + +// x <- x,m. +def ZnWritePCMPGTQm : SchedWriteRes<[ZnAGU, ZnFPU03]> { + let Latency = 8; +} +// ymm. +def ZnWritePCMPGTQYm : SchedWriteRes<[ZnAGU, ZnFPU03]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,2]; +} +def : InstRW<[ZnWritePCMPGTQm], (instregex "(V?)PCMPGTQrm")>; +def : InstRW<[ZnWritePCMPGTQYm], (instrs VPCMPGTQYrm)>; + +//-- Logic instructions --// + +// PSLL,PSRL,PSRA W/D/Q. +// x,x / v,v,x. +def ZnWritePShift : SchedWriteRes<[ZnFPU2]> ; +def ZnWritePShiftY : SchedWriteRes<[ZnFPU2]> { + let Latency = 2; +} + +// PSLL,PSRL DQ. +def : InstRW<[ZnWritePShift], (instregex "(V?)PS(R|L)LDQri")>; +def : InstRW<[ZnWritePShiftY], (instregex "(V?)PS(R|L)LDQYri")>; + +//=== Floating Point XMM and YMM Instructions ===// +//-- Move instructions --// + +// VPERM2F128. +def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rr)>; +def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rm)>; + +def ZnWriteBROADCAST : SchedWriteRes<[ZnAGU, ZnFPU13]> { + let NumMicroOps = 2; + let Latency = 8; +} +// VBROADCASTF128. +def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128)>; + +// EXTRACTPS. +// r32,x,i. +def ZnWriteEXTRACTPSr : SchedWriteRes<[ZnFPU12, ZnFPU2]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1, 2]; +} +def : InstRW<[ZnWriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>; + +def ZnWriteEXTRACTPSm : SchedWriteRes<[ZnAGU,ZnFPU12, ZnFPU2]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [5, 1, 2]; +} +// m32,x,i. +def : InstRW<[ZnWriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>; + +// VEXTRACTF128. +// x,y,i. +def : InstRW<[ZnWriteFPU013], (instrs VEXTRACTF128rr)>; + +// m128,y,i. +def : InstRW<[ZnWriteFPU013m], (instrs VEXTRACTF128mr)>; + +def ZnWriteVINSERT128r: SchedWriteRes<[ZnFPU013]> { + let Latency = 2; + let ResourceCycles = [2]; +} +def ZnWriteVINSERT128Ld: SchedWriteRes<[ZnAGU,ZnFPU013]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1, 2]; +} +// VINSERTF128. +// y,y,x,i. +def : InstRW<[ZnWriteVINSERT128r], (instrs VINSERTF128rr)>; +def : InstRW<[ZnWriteVINSERT128Ld], (instrs VINSERTF128rm)>; + +// VGATHER. +def : InstRW<[WriteMicrocoded], (instregex "VGATHER(Q|D)(PD|PS)(Y?)rm")>; + +//-- Conversion instructions --// +def ZnWriteCVTPD2PSr: SchedWriteRes<[ZnFPU3]> { + let Latency = 4; +} +def ZnWriteCVTPD2PSYr: SchedWriteRes<[ZnFPU3]> { + let Latency = 5; +} + +// CVTPD2PS. +// x,x. +def : SchedAlias; +// y,y. +def : SchedAlias; +// z,z. +defm : X86WriteResUnsupported; + +def ZnWriteCVTPD2PSLd: SchedWriteRes<[ZnAGU,ZnFPU03]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,2]; +} +// x,m128. +def : SchedAlias; + +// x,m256. +def ZnWriteCVTPD2PSYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 11; +} +def : SchedAlias; +// z,m512 +defm : X86WriteResUnsupported; + +// CVTSD2SS. +// x,x. +// Same as WriteCVTPD2PSr +def : SchedAlias; + +// x,m64. +def : SchedAlias; + +// CVTPS2PD. +// x,x. +def ZnWriteCVTPS2PDr : SchedWriteRes<[ZnFPU3]> { + let Latency = 3; +} +def : SchedAlias; + +// x,m64. +// y,m128. +def ZnWriteCVTPS2PDLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 10; + let NumMicroOps = 2; +} +def : SchedAlias; +def : SchedAlias; +defm : X86WriteResUnsupported; + +// y,x. +def ZnWriteVCVTPS2PDY : SchedWriteRes<[ZnFPU3]> { + let Latency = 3; +} +def : SchedAlias; +defm : X86WriteResUnsupported; + +// CVTSS2SD. +// x,x. +def ZnWriteCVTSS2SDr : SchedWriteRes<[ZnFPU3]> { + let Latency = 4; +} +def : SchedAlias; + +// x,m32. +def ZnWriteCVTSS2SDLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1, 2]; +} +def : SchedAlias; + +def ZnWriteCVTDQ2PDr: SchedWriteRes<[ZnFPU12,ZnFPU3]> { + let Latency = 5; +} +// CVTDQ2PD. +// x,x. +def : InstRW<[ZnWriteCVTDQ2PDr], (instregex "(V)?CVTDQ2PDrr")>; + +// Same as xmm +// y,x. +def : InstRW<[ZnWriteCVTDQ2PDr], (instrs VCVTDQ2PDYrr)>; + +def ZnWriteCVTPD2DQr: SchedWriteRes<[ZnFPU12, ZnFPU3]> { + let Latency = 5; +} +// CVT(T)PD2DQ. +// x,x. +def : InstRW<[ZnWriteCVTDQ2PDr], (instregex "(V?)CVT(T?)PD2DQrr")>; + +def ZnWriteCVTPD2DQLd: SchedWriteRes<[ZnAGU,ZnFPU12,ZnFPU3]> { + let Latency = 12; + let NumMicroOps = 2; +} +// x,m128. +def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "(V?)CVT(T?)PD2DQrm")>; +// same as xmm handling +// x,y. +def : InstRW<[ZnWriteCVTPD2DQr], (instregex "VCVT(T?)PD2DQYrr")>; +// x,m256. +def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "VCVT(T?)PD2DQYrm")>; + +def ZnWriteCVTPS2PIr: SchedWriteRes<[ZnFPU3]> { + let Latency = 4; +} +// CVT(T)PS2PI. +// mm,x. +def : InstRW<[ZnWriteCVTPS2PIr], (instregex "MMX_CVT(T?)PS2PIirr")>; + +// CVTPI2PD. +// x,mm. +def : InstRW<[ZnWriteCVTPS2PDr], (instrs MMX_CVTPI2PDirr)>; + +// CVT(T)PD2PI. +// mm,x. +def : InstRW<[ZnWriteCVTPS2PIr], (instregex "MMX_CVT(T?)PD2PIirr")>; + +def ZnWriteCVSTSI2SSr: SchedWriteRes<[ZnFPU3]> { + let Latency = 5; +} + +// same as CVTPD2DQr +// CVT(T)SS2SI. +// r32,x. +def : InstRW<[ZnWriteCVTPD2DQr], (instregex "(V?)CVT(T?)SS2SI(64)?rr")>; +// same as CVTPD2DQm +// r32,m32. +def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "(V?)CVT(T?)SS2SI(64)?rm")>; + +def ZnWriteCVSTSI2SDr: SchedWriteRes<[ZnFPU013, ZnFPU3]> { + let Latency = 5; +} +// CVTSI2SD. +// x,r32/64. +def : InstRW<[ZnWriteCVSTSI2SDr], (instregex "(V?)CVTSI(64)?2SDrr")>; + + +def ZnWriteCVSTSI2SIr: SchedWriteRes<[ZnFPU3, ZnFPU2]> { + let Latency = 5; +} +def ZnWriteCVSTSI2SILd: SchedWriteRes<[ZnAGU, ZnFPU3, ZnFPU2]> { + let Latency = 12; +} +// CVTSD2SI. +// r32/64 +def : InstRW<[ZnWriteCVSTSI2SIr], (instregex "(V?)CVT(T?)SD2SI(64)?rr")>; +// r32,m32. +def : InstRW<[ZnWriteCVSTSI2SILd], (instregex "(V?)CVT(T?)SD2SI(64)?rm")>; + +// VCVTPS2PH. +// x,v,i. +def : SchedAlias; +def : SchedAlias; +defm : X86WriteResUnsupported; +// m,v,i. +def : SchedAlias; +def : SchedAlias; +defm : X86WriteResUnsupported; + +// VCVTPH2PS. +// v,x. +def : SchedAlias; +def : SchedAlias; +defm : X86WriteResUnsupported; +// v,m. +def : SchedAlias; +def : SchedAlias; +defm : X86WriteResUnsupported; + +//-- SSE4A instructions --// +// EXTRQ +def ZnWriteEXTRQ: SchedWriteRes<[ZnFPU12, ZnFPU2]> { + let Latency = 2; +} +def : InstRW<[ZnWriteEXTRQ], (instregex "EXTRQ")>; + +// INSERTQ +def ZnWriteINSERTQ: SchedWriteRes<[ZnFPU03,ZnFPU1]> { + let Latency = 4; +} +def : InstRW<[ZnWriteINSERTQ], (instregex "INSERTQ")>; + +//-- SHA instructions --// +// SHA256MSG2 +def : InstRW<[WriteMicrocoded], (instregex "SHA256MSG2(Y?)r(r|m)")>; + +// SHA1MSG1, SHA256MSG1 +// x,x. +def ZnWriteSHA1MSG1r : SchedWriteRes<[ZnFPU12]> { + let Latency = 2; + let ResourceCycles = [2]; +} +def : InstRW<[ZnWriteSHA1MSG1r], (instregex "SHA(1|256)MSG1rr")>; +// x,m. +def ZnWriteSHA1MSG1Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> { + let Latency = 9; + let ResourceCycles = [1,2]; +} +def : InstRW<[ZnWriteSHA1MSG1Ld], (instregex "SHA(1|256)MSG1rm")>; + +// SHA1MSG2 +// x,x. +def ZnWriteSHA1MSG2r : SchedWriteRes<[ZnFPU12]> ; +def : InstRW<[ZnWriteSHA1MSG2r], (instregex "SHA1MSG2rr")>; +// x,m. +def ZnWriteSHA1MSG2Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> { + let Latency = 8; +} +def : InstRW<[ZnWriteSHA1MSG2Ld], (instregex "SHA1MSG2rm")>; + +// SHA1NEXTE +// x,x. +def ZnWriteSHA1NEXTEr : SchedWriteRes<[ZnFPU1]> ; +def : InstRW<[ZnWriteSHA1NEXTEr], (instregex "SHA1NEXTErr")>; +// x,m. +def ZnWriteSHA1NEXTELd : SchedWriteRes<[ZnAGU, ZnFPU1]> { + let Latency = 8; +} +def : InstRW<[ZnWriteSHA1NEXTELd], (instregex "SHA1NEXTErm")>; + +// SHA1RNDS4 +// x,x. +def ZnWriteSHA1RNDS4r : SchedWriteRes<[ZnFPU1]> { + let Latency = 6; +} +def : InstRW<[ZnWriteSHA1RNDS4r], (instregex "SHA1RNDS4rr")>; +// x,m. +def ZnWriteSHA1RNDS4Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> { + let Latency = 13; +} +def : InstRW<[ZnWriteSHA1RNDS4Ld], (instregex "SHA1RNDS4rm")>; + +// SHA256RNDS2 +// x,x. +def ZnWriteSHA256RNDS2r : SchedWriteRes<[ZnFPU1]> { + let Latency = 4; +} +def : InstRW<[ZnWriteSHA256RNDS2r], (instregex "SHA256RNDS2rr")>; +// x,m. +def ZnWriteSHA256RNDS2Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> { + let Latency = 11; +} +def : InstRW<[ZnWriteSHA256RNDS2Ld], (instregex "SHA256RNDS2rm")>; + +//-- Arithmetic instructions --// + +// HADD, HSUB PS/PD +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; + +// VDIVPS. +// TODO - convert to ZnWriteResFpuPair +// y,y,y. +def ZnWriteVDIVPSYr : SchedWriteRes<[ZnFPU3]> { + let Latency = 12; + let ResourceCycles = [12]; +} +def : SchedAlias; + +// y,y,m256. +def ZnWriteVDIVPSYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 19; + let NumMicroOps = 2; + let ResourceCycles = [1, 19]; +} +def : SchedAlias; + +// VDIVPD. +// TODO - convert to ZnWriteResFpuPair +// y,y,y. +def ZnWriteVDIVPDY : SchedWriteRes<[ZnFPU3]> { + let Latency = 15; + let ResourceCycles = [15]; +} +def : SchedAlias; + +// y,y,m256. +def ZnWriteVDIVPDYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { + let Latency = 22; + let NumMicroOps = 2; + let ResourceCycles = [1,22]; +} +def : SchedAlias; + +// DPPS. +// x,x,i / v,v,v,i. +def : SchedAlias; +def : SchedAlias; + +// x,m,i / v,v,m,i. +def : SchedAlias; +def : SchedAlias; + +// DPPD. +// x,x,i. +def : SchedAlias; + +// x,m,i. +def : SchedAlias; + +// RSQRTSS +// TODO - convert to ZnWriteResFpuPair +// x,x. +def ZnWriteRSQRTSSr : SchedWriteRes<[ZnFPU02]> { + let Latency = 5; +} +def : SchedAlias; + +// x,m128. +def ZnWriteRSQRTSSLd: SchedWriteRes<[ZnAGU, ZnFPU02]> { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [1,2]; // FIXME: Is this right? +} +def : SchedAlias; + +// RSQRTPS +// TODO - convert to ZnWriteResFpuPair +// y,y. +def ZnWriteRSQRTPSYr : SchedWriteRes<[ZnFPU01]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def : SchedAlias; + +// y,m256. +def ZnWriteRSQRTPSYLd : SchedWriteRes<[ZnAGU, ZnFPU01]> { + let Latency = 12; + let NumMicroOps = 2; +} +def : SchedAlias; + +//-- Other instructions --// + +// VZEROUPPER. +def : InstRW<[WriteMicrocoded], (instrs VZEROUPPER)>; + +// VZEROALL. +def : InstRW<[WriteMicrocoded], (instrs VZEROALL)>; + +} // SchedModel diff --git a/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86_reduce.td b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86_reduce.td new file mode 100644 index 0000000..cf2ce68 --- /dev/null +++ b/thirdparty/capstone/suite/synctools/tablegen/X86/back/X86_reduce.td @@ -0,0 +1,459 @@ +//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This is a target description file for the Intel i386 architecture, referred +// to here as the "X86" architecture. +// +//===----------------------------------------------------------------------===// + +// Get the target-independent interfaces which we are implementing... +// +include "llvm/Target/Target.td" + +//===----------------------------------------------------------------------===// +// X86 Subtarget state +// + +def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", + "64-bit mode (x86_64)">; +def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true", + "32-bit mode (80386)">; +def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true", + "16-bit mode (i8086)">; + +//===----------------------------------------------------------------------===// +// X86 Subtarget features +//===----------------------------------------------------------------------===// + +def FeatureX87 : SubtargetFeature<"x87","HasX87", "true", + "Enable X87 float instructions">; + +def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true", + "Enable NOPL instruction">; + +def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", + "Enable conditional move instructions">; + +def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", + "Support POPCNT instruction">; + +def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true", + "Support fxsave/fxrestore instructions">; + +def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true", + "Support xsave instructions">; + +def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true", + "Support xsaveopt instructions">; + +def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true", + "Support xsavec instructions">; + +def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true", + "Support xsaves instructions">; + +def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", + "Enable SSE instructions", + // SSE codegen depends on cmovs, and all + // SSE1+ processors support them. + [FeatureCMOV]>; +def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", + "Enable SSE2 instructions", + [FeatureSSE1]>; +def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", + "Enable SSE3 instructions", + [FeatureSSE2]>; +def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", + "Enable SSSE3 instructions", + [FeatureSSE3]>; +def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41", + "Enable SSE 4.1 instructions", + [FeatureSSSE3]>; +def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42", + "Enable SSE 4.2 instructions", + [FeatureSSE41]>; +// The MMX subtarget feature is separate from the rest of the SSE features +// because it's important (for odd compatibility reasons) to be able to +// turn it off explicitly while allowing SSE+ to be on. +def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX", + "Enable MMX instructions">; +def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", + "Enable 3DNow! instructions", + [FeatureMMX]>; +def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", + "Enable 3DNow! Athlon instructions", + [Feature3DNow]>; +// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied +// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) +// without disabling 64-bit mode. +def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", + "Support 64-bit instructions", + [FeatureCMOV]>; +def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true", + "64-bit with cmpxchg16b", + [Feature64Bit]>; +def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true", + "SHLD instruction is slow">; +def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true", + "PMULLD instruction is slow">; +// FIXME: This should not apply to CPUs that do not have SSE. +def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", + "IsUAMem16Slow", "true", + "Slow unaligned 16-byte memory access">; +def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32", + "IsUAMem32Slow", "true", + "Slow unaligned 32-byte memory access">; +def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", + "Support SSE 4a instructions", + [FeatureSSE3]>; + +def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", + "Enable AVX instructions", + [FeatureSSE42]>; +def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", + "Enable AVX2 instructions", + [FeatureAVX]>; +def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", + "Enable three-operand fused multiple-add", + [FeatureAVX]>; +def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", + "Support 16-bit floating point conversion instructions", + [FeatureAVX]>; +def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F", + "Enable AVX-512 instructions", + [FeatureAVX2, FeatureFMA, FeatureF16C]>; +def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true", + "Enable AVX-512 Exponential and Reciprocal Instructions", + [FeatureAVX512]>; +def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true", + "Enable AVX-512 Conflict Detection Instructions", + [FeatureAVX512]>; +def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ", + "true", "Enable AVX-512 Population Count Instructions", + [FeatureAVX512]>; +def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true", + "Enable AVX-512 PreFetch Instructions", + [FeatureAVX512]>; +def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1", + "true", + "Prefetch with Intent to Write and T1 Hint">; +def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true", + "Enable AVX-512 Doubleword and Quadword Instructions", + [FeatureAVX512]>; +def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true", + "Enable AVX-512 Byte and Word Instructions", + [FeatureAVX512]>; +def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true", + "Enable AVX-512 Vector Length eXtensions", + [FeatureAVX512]>; +def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true", + "Enable AVX-512 Vector Byte Manipulation Instructions", + [FeatureBWI]>; +def FeatureVBMI2 : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true", + "Enable AVX-512 further Vector Byte Manipulation Instructions", + [FeatureBWI]>; +def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true", + "Enable AVX-512 Integer Fused Multiple-Add", + [FeatureAVX512]>; +def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true", + "Enable protection keys">; +def FeatureVNNI : SubtargetFeature<"avx512vnni", "HasVNNI", "true", + "Enable AVX-512 Vector Neural Network Instructions", + [FeatureAVX512]>; +def FeatureBITALG : SubtargetFeature<"avx512bitalg", "HasBITALG", "true", + "Enable AVX-512 Bit Algorithms", + [FeatureBWI]>; +def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", + "Enable packed carry-less multiplication instructions", + [FeatureSSE2]>; +def FeatureGFNI : SubtargetFeature<"gfni", "HasGFNI", "true", + "Enable Galois Field Arithmetic Instructions", + [FeatureSSE2]>; +def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true", + "Enable vpclmulqdq instructions", + [FeatureAVX, FeaturePCLMUL]>; +def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", + "Enable four-operand fused multiple-add", + [FeatureAVX, FeatureSSE4A]>; +def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", + "Enable XOP instructions", + [FeatureFMA4]>; +def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem", + "HasSSEUnalignedMem", "true", + "Allow unaligned memory operands with SSE instructions">; +def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", + "Enable AES instructions", + [FeatureSSE2]>; +def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true", + "Promote selected AES instructions to AVX512/AVX registers", + [FeatureAVX, FeatureAES]>; +def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", + "Enable TBM instructions">; +def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true", + "Enable LWP instructions">; +def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", + "Support MOVBE instruction">; +def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", + "Support RDRAND instruction">; +def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true", + "Support FS/GS Base instructions">; +def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true", + "Support LZCNT instruction">; +def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true", + "Support BMI instructions">; +def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true", + "Support BMI2 instructions">; +def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true", + "Support RTM instructions">; +def FeatureADX : SubtargetFeature<"adx", "HasADX", "true", + "Support ADX instructions">; +def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true", + "Enable SHA instructions", + [FeatureSSE2]>; +def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true", + "Support CET Shadow-Stack instructions">; +def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", + "Support PRFCHW instructions">; +def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", + "Support RDSEED instruction">; +def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true", + "Support LAHF and SAHF instructions">; +def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true", + "Enable MONITORX/MWAITX timer functionality">; +def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true", + "Enable Cache Line Zero">; +def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true", + "Enable Cache Demote">; +def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true", + "Support ptwrite instruction">; +def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true", + "Support MPX instructions">; +def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", + "Use LEA for adjusting the stack pointer">; +def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb", + "HasSlowDivide32", "true", + "Use 8-bit divide for positive values less than 256">; +def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl", + "HasSlowDivide64", "true", + "Use 32-bit divide for positive values less than 2^32">; +def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", + "PadShortFunctions", "true", + "Pad short functions">; +def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", + "Invalidate Process-Context Identifier">; +def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", + "Enable Software Guard Extensions">; +def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", + "Flush A Cache Line Optimized">; +def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true", + "Cache Line Write Back">; +def FeatureWBNOINVD : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true", + "Write Back No Invalidate">; +def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true", + "Support RDPID instructions">; +def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true", + "Wait and pause enhancements">; +// On some processors, instructions that implicitly take two memory operands are +// slow. In practice, this means that CALL, PUSH, and POP with memory operands +// should be avoided in favor of a MOV + register CALL/PUSH/POP. +def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops", + "SlowTwoMemOps", "true", + "Two memory operand instructions are slow">; +def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", + "LEA instruction needs inputs at AG stage">; +def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", + "LEA instruction with certain arguments is slow">; +def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true", + "LEA instruction with 3 ops or certain registers is slow">; +def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true", + "INC and DEC instructions are slower than ADD and SUB">; +def FeatureSoftFloat + : SubtargetFeature<"soft-float", "UseSoftFloat", "true", + "Use software floating point features.">; +def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt", + "HasPOPCNTFalseDeps", "true", + "POPCNT has a false dependency on dest register">; +def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt", + "HasLZCNTFalseDeps", "true", + "LZCNT/TZCNT have a false dependency on dest register">; +def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true", + "platform configuration instruction">; +// On recent X86 (port bound) processors, its preferable to combine to a single shuffle +// using a variable mask over multiple fixed shuffles. +def FeatureFastVariableShuffle + : SubtargetFeature<"fast-variable-shuffle", + "HasFastVariableShuffle", + "true", "Shuffles with variable masks are fast">; +// On some X86 processors, there is no performance hazard to writing only the +// lower parts of a YMM or ZMM register without clearing the upper part. +def FeatureFastPartialYMMorZMMWrite + : SubtargetFeature<"fast-partial-ymm-or-zmm-write", + "HasFastPartialYMMorZMMWrite", + "true", "Partial writes to YMM/ZMM registers are fast">; +// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency +// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if +// vector FSQRT has higher throughput than the corresponding NR code. +// The idea is that throughput bound code is likely to be vectorized, so for +// vectorized code we should care about the throughput of SQRT operations. +// But if the code is scalar that probably means that the code has some kind of +// dependency and we should care more about reducing the latency. +def FeatureFastScalarFSQRT + : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT", + "true", "Scalar SQRT is fast (disable Newton-Raphson)">; +def FeatureFastVectorFSQRT + : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT", + "true", "Vector SQRT is fast (disable Newton-Raphson)">; +// If lzcnt has equivalent latency/throughput to most simple integer ops, it can +// be used to replace test/set sequences. +def FeatureFastLZCNT + : SubtargetFeature< + "fast-lzcnt", "HasFastLZCNT", "true", + "LZCNT instructions are as fast as most simple integer ops">; +// If the target can efficiently decode NOPs upto 11-bytes in length. +def FeatureFast11ByteNOP + : SubtargetFeature< + "fast-11bytenop", "HasFast11ByteNOP", "true", + "Target can quickly decode up to 11 byte NOPs">; +// If the target can efficiently decode NOPs upto 15-bytes in length. +def FeatureFast15ByteNOP + : SubtargetFeature< + "fast-15bytenop", "HasFast15ByteNOP", "true", + "Target can quickly decode up to 15 byte NOPs">; +// Sandy Bridge and newer processors can use SHLD with the same source on both +// inputs to implement rotate to avoid the partial flag update of the normal +// rotate instructions. +def FeatureFastSHLDRotate + : SubtargetFeature< + "fast-shld-rotate", "HasFastSHLDRotate", "true", + "SHLD can be used as a faster rotate">; + +// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka +// "string operations"). See "REP String Enhancement" in the Intel Software +// Development Manual. This feature essentially means that REP MOVSB will copy +// using the largest available size instead of copying bytes one by one, making +// it at least as fast as REPMOVS{W,D,Q}. +def FeatureERMSB + : SubtargetFeature< + "ermsb", "HasERMSB", "true", + "REP MOVS/STOS are fast">; + +// Sandy Bridge and newer processors have many instructions that can be +// fused with conditional branches and pass through the CPU as a single +// operation. +def FeatureMacroFusion + : SubtargetFeature<"macrofusion", "HasMacroFusion", "true", + "Various instructions can be fused with conditional branches">; + +// Gather is available since Haswell (AVX2 set). So technically, we can +// generate Gathers on all AVX2 processors. But the overhead on HSW is high. +// Skylake Client processor has faster Gathers than HSW and performance is +// similar to Skylake Server (AVX-512). +def FeatureHasFastGather + : SubtargetFeature<"fast-gather", "HasFastGather", "true", + "Indicates if gather is reasonably fast.">; + +def FeaturePrefer256Bit + : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true", + "Prefer 256-bit AVX instructions">; + +// Enable mitigation of some aspects of speculative execution related +// vulnerabilities by removing speculatable indirect branches. This disables +// jump-table formation, rewrites explicit `indirectbr` instructions into +// `switch` instructions, and uses a special construct called a "retpoline" to +// prevent speculation of the remaining indirect branches (indirect calls and +// tail calls). +def FeatureRetpoline + : SubtargetFeature<"retpoline", "UseRetpoline", "true", + "Remove speculation of indirect branches from the " + "generated code, either by avoiding them entirely or " + "lowering them with a speculation blocking construct.">; + +// Rely on external thunks for the emitted retpoline calls. This allows users +// to provide their own custom thunk definitions in highly specialized +// environments such as a kernel that does boot-time hot patching. +def FeatureRetpolineExternalThunk + : SubtargetFeature< + "retpoline-external-thunk", "UseRetpolineExternalThunk", "true", + "Enable retpoline, but with an externally provided thunk.", + [FeatureRetpoline]>; + +// Direct Move instructions. +def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true", + "Support movdiri instruction">; +def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true", + "Support movdir64b instruction">; + +//===----------------------------------------------------------------------===// +// Register File Description +//===----------------------------------------------------------------------===// + +include "X86RegisterInfo.td" +include "X86RegisterBanks.td" + +//===----------------------------------------------------------------------===// +// Instruction Descriptions +//===----------------------------------------------------------------------===// + +include "X86Schedule.td" +include "X86InstrInfo_reduce.td" + +def X86InstrInfo : InstrInfo; + +//===----------------------------------------------------------------------===// +// Assembly Parser +//===----------------------------------------------------------------------===// + +def ATTAsmParserVariant : AsmParserVariant { + int Variant = 0; + + // Variant name. + string Name = "att"; + + // Discard comments in assembly strings. + string CommentDelimiter = "#"; + + // Recognize hard coded registers. + string RegisterPrefix = "%"; +} + +def IntelAsmParserVariant : AsmParserVariant { + int Variant = 1; + + // Variant name. + string Name = "intel"; + + // Discard comments in assembly strings. + string CommentDelimiter = ";"; + + // Recognize hard coded registers. + string RegisterPrefix = ""; +} + +//===----------------------------------------------------------------------===// +// Assembly Printers +//===----------------------------------------------------------------------===// + +// The X86 target supports two different syntaxes for emitting machine code. +// This is controlled by the -x86-asm-syntax={att|intel} +def ATTAsmWriter : AsmWriter { + string AsmWriterClassName = "ATTInstPrinter"; + int Variant = 0; +} +def IntelAsmWriter : AsmWriter { + string AsmWriterClassName = "IntelInstPrinter"; + int Variant = 1; +} + +def X86 : Target { + // Information about the instructions... + let InstructionSet = X86InstrInfo; + let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant]; + let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; + let AllowRegisterRenaming = 1; +} diff --git a/thirdparty/capstone/suite/x86/README b/thirdparty/capstone/suite/x86/README new file mode 100644 index 0000000..b4de6d1 --- /dev/null +++ b/thirdparty/capstone/suite/x86/README @@ -0,0 +1 @@ +This directory contains some tools to test X86 engine. diff --git a/thirdparty/capstone/suite/x86/verify/README b/thirdparty/capstone/suite/x86/verify/README new file mode 100644 index 0000000..3efc787 --- /dev/null +++ b/thirdparty/capstone/suite/x86/verify/README @@ -0,0 +1,2 @@ +This directory contains some tools to verify Capstone output, +as well as semantics of X86 machine code. diff --git a/thirdparty/capstone/tests/MC/ARM/arm-aliases.s.yaml b/thirdparty/capstone/tests/MC/ARM/arm-aliases.s.yaml new file mode 100644 index 0000000..5338902 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/arm-aliases.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x03, 0x10, 0x82, 0xe0, 0x03, 0x10, 0x42, 0xe0, 0x03, 0x10, 0x22, 0xe0, 0x03, 0x10, 0x82, 0xe1, 0x03, 0x10, 0x02, 0xe0, 0x03, 0x10, 0xc2, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "add r1, r2, r3" + - + asm_text: "sub r1, r2, r3" + - + asm_text: "eor r1, r2, r3" + - + asm_text: "orr r1, r2, r3" + - + asm_text: "and r1, r2, r3" + - + asm_text: "bic r1, r2, r3" diff --git a/thirdparty/capstone/tests/MC/ARM/arm-arithmetic-aliases.s.yaml b/thirdparty/capstone/tests/MC/ARM/arm-arithmetic-aliases.s.yaml new file mode 100644 index 0000000..a178854 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/arm-arithmetic-aliases.s.yaml @@ -0,0 +1,106 @@ +test_cases: + - + input: + bytes: [ 0x06, 0x20, 0x42, 0xe2, 0x06, 0x20, 0x42, 0xe2, 0x03, 0x20, 0x42, 0xe0, 0x03, 0x20, 0x42, 0xe0, 0x06, 0x20, 0x82, 0xe2, 0x06, 0x20, 0x82, 0xe2, 0x03, 0x20, 0x82, 0xe0, 0x03, 0x20, 0x82, 0xe0, 0x06, 0x20, 0x02, 0xe2, 0x06, 0x20, 0x02, 0xe2, 0x03, 0x20, 0x02, 0xe0, 0x03, 0x20, 0x02, 0xe0, 0x06, 0x20, 0x82, 0xe3, 0x06, 0x20, 0x82, 0xe3, 0x03, 0x20, 0x82, 0xe1, 0x03, 0x20, 0x82, 0xe1, 0x06, 0x20, 0x22, 0xe2, 0x06, 0x20, 0x22, 0xe2, 0x03, 0x20, 0x22, 0xe0, 0x03, 0x20, 0x22, 0xe0, 0x06, 0x20, 0xc2, 0xe3, 0x06, 0x20, 0xc2, 0xe3, 0x03, 0x20, 0xc2, 0xe1, 0x03, 0x20, 0xc2, 0xe1, 0x06, 0x20, 0x52, 0x02, 0x06, 0x20, 0x52, 0x02, 0x03, 0x20, 0x52, 0x00, 0x03, 0x20, 0x52, 0x00, 0x06, 0x20, 0x92, 0x02, 0x06, 0x20, 0x92, 0x02, 0x03, 0x20, 0x92, 0x00, 0x03, 0x20, 0x92, 0x00, 0x06, 0x20, 0x12, 0x02, 0x06, 0x20, 0x12, 0x02, 0x03, 0x20, 0x12, 0x00, 0x03, 0x20, 0x12, 0x00, 0x06, 0x20, 0x92, 0x03, 0x06, 0x20, 0x92, 0x03, 0x03, 0x20, 0x92, 0x01, 0x03, 0x20, 0x92, 0x01, 0x06, 0x20, 0x32, 0x02, 0x06, 0x20, 0x32, 0x02, 0x03, 0x20, 0x32, 0x00, 0x03, 0x20, 0x32, 0x00, 0x06, 0x20, 0xd2, 0x03, 0x06, 0x20, 0xd2, 0x03, 0x03, 0x20, 0xd2, 0x01, 0x03, 0x20, 0xd2, 0x01, 0x7b, 0x00, 0x8f, 0xe2 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "sub r2, r2, #6" + - + asm_text: "sub r2, r2, #6" + - + asm_text: "sub r2, r2, r3" + - + asm_text: "sub r2, r2, r3" + - + asm_text: "add r2, r2, #6" + - + asm_text: "add r2, r2, #6" + - + asm_text: "add r2, r2, r3" + - + asm_text: "add r2, r2, r3" + - + asm_text: "and r2, r2, #6" + - + asm_text: "and r2, r2, #6" + - + asm_text: "and r2, r2, r3" + - + asm_text: "and r2, r2, r3" + - + asm_text: "orr r2, r2, #6" + - + asm_text: "orr r2, r2, #6" + - + asm_text: "orr r2, r2, r3" + - + asm_text: "orr r2, r2, r3" + - + asm_text: "eor r2, r2, #6" + - + asm_text: "eor r2, r2, #6" + - + asm_text: "eor r2, r2, r3" + - + asm_text: "eor r2, r2, r3" + - + asm_text: "bic r2, r2, #6" + - + asm_text: "bic r2, r2, #6" + - + asm_text: "bic r2, r2, r3" + - + asm_text: "bic r2, r2, r3" + - + asm_text: "subseq r2, r2, #6" + - + asm_text: "subseq r2, r2, #6" + - + asm_text: "subseq r2, r2, r3" + - + asm_text: "subseq r2, r2, r3" + - + asm_text: "addseq r2, r2, #6" + - + asm_text: "addseq r2, r2, #6" + - + asm_text: "addseq r2, r2, r3" + - + asm_text: "addseq r2, r2, r3" + - + asm_text: "andseq r2, r2, #6" + - + asm_text: "andseq r2, r2, #6" + - + asm_text: "andseq r2, r2, r3" + - + asm_text: "andseq r2, r2, r3" + - + asm_text: "orrseq r2, r2, #6" + - + asm_text: "orrseq r2, r2, #6" + - + asm_text: "orrseq r2, r2, r3" + - + asm_text: "orrseq r2, r2, r3" + - + asm_text: "eorseq r2, r2, #6" + - + asm_text: "eorseq r2, r2, #6" + - + asm_text: "eorseq r2, r2, r3" + - + asm_text: "eorseq r2, r2, r3" + - + asm_text: "bicseq r2, r2, #6" + - + asm_text: "bicseq r2, r2, #6" + - + asm_text: "bicseq r2, r2, r3" + - + asm_text: "bicseq r2, r2, r3" + - + asm_text: "add r0, pc, #0x7b" diff --git a/thirdparty/capstone/tests/MC/ARM/arm-branches.s.yaml b/thirdparty/capstone/tests/MC/ARM/arm-branches.s.yaml new file mode 100644 index 0000000..b443756 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/arm-branches.s.yaml @@ -0,0 +1,18 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x00, 0x00, 0xea, 0x01, 0x00, 0x00, 0xeb, 0x01, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0xfb, 0x01, 0x00, 0x00, 0xea ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "b #4" + - + asm_text: "bl #4" + - + asm_text: "beq #4" + - + asm_text: "blx #2" + - + asm_text: "b #4" diff --git a/thirdparty/capstone/tests/MC/ARM/arm-it-block.s.yaml b/thirdparty/capstone/tests/MC/ARM/arm-it-block.s.yaml new file mode 100644 index 0000000..252fb18 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/arm-it-block.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x03, 0x20, 0xa0, 0x01 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "moveq r2, r3" diff --git a/thirdparty/capstone/tests/MC/ARM/arm-memory-instructions.s.yaml b/thirdparty/capstone/tests/MC/ARM/arm-memory-instructions.s.yaml new file mode 100644 index 0000000..8a3d1a4 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/arm-memory-instructions.s.yaml @@ -0,0 +1,292 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x50, 0x97, 0xe5, 0x3f, 0x60, 0x93, 0xe5, 0xff, 0x2f, 0xb4, 0xe5, 0x1e, 0x10, 0x92, 0xe4, 0x1e, 0x30, 0x11, 0xe4, 0x00, 0x90, 0x12, 0xe4, 0x01, 0x30, 0x98, 0xe7, 0x03, 0x20, 0x15, 0xe7, 0x09, 0x10, 0xb5, 0xe7, 0x08, 0x60, 0x37, 0xe7, 0xa2, 0x11, 0xb0, 0xe7, 0x02, 0x50, 0x99, 0xe6, 0x06, 0x40, 0x13, 0xe6, 0x82, 0x37, 0x18, 0xe7, 0xc3, 0x17, 0x95, 0xe6, 0x00, 0x30, 0xd8, 0xe5, 0x3f, 0x10, 0xdd, 0xe5, 0xff, 0x9f, 0xf3, 0xe5, 0x16, 0x80, 0xd1, 0xe4, 0x13, 0x20, 0x57, 0xe4, 0x05, 0x90, 0xd8, 0xe7, 0x01, 0x10, 0x55, 0xe7, 0x02, 0x30, 0xf5, 0xe7, 0x03, 0x60, 0x79, 0xe7, 0x04, 0x20, 0xd1, 0xe6, 0x05, 0x80, 0x54, 0xe6, 0x81, 0x77, 0x5c, 0xe7, 0xc9, 0x57, 0xd2, 0xe6, 0x04, 0x30, 0xf1, 0xe4, 0x08, 0x20, 0x78, 0xe4, 0x06, 0x80, 0xf7, 0xe6, 0x06, 0x16, 0x72, 0xe6, 0xd0, 0x20, 0xc5, 0xe1, 0xdf, 0x60, 0xc2, 0xe1, 0xd0, 0x02, 0xe9, 0xe1, 0xd8, 0x60, 0xc1, 0xe0, 0xd0, 0x00, 0xc8, 0xe0, 0xd0, 0x00, 0xc8, 0xe0, 0xd0, 0x00, 0x48, 0xe0, 0xd3, 0x40, 0x81, 0xe1, 0xd2, 0x40, 0xa7, 0xe1, 0xdc, 0x00, 0x88, 0xe0, 0xdc, 0x00, 0x08, 0xe0, 0xb0, 0x30, 0xd4, 0xe1, 0xb4, 0x20, 0xd7, 0xe1, 0xb0, 0x14, 0xf8, 0xe1, 0xb4, 0xc0, 0xdd, 0xe0, 0xb4, 0x60, 0x95, 0xe1, 0xbb, 0x30, 0xb8, 0xe1, 0xb1, 0x10, 0x32, 0xe1, 0xb2, 0x90, 0x97, 0xe0, 0xb2, 0x40, 0x13, 0xe0, 0xb0, 0x98, 0xf7, 0xe0, 0xbb, 0x44, 0x73, 0xe0, 0xb0, 0x40, 0xf3, 0xe0, 0xb2, 0x90, 0xb7, 0xe0, 0xb2, 0x40, 0x33, 0xe0, 0xd0, 0x30, 0xd4, 0xe1, 0xd1, 0x21, 0xd7, 0xe1, 0xdf, 0x1f, 0xf8, 0xe1, 0xd9, 0xc0, 0xdd, 0xe0, 0xd4, 0x60, 0x95, 0xe1, 0xdb, 0x30, 0xb8, 0xe1, 0xd1, 0x10, 0x32, 0xe1, 0xd2, 0x90, 0x97, 0xe0, 0xd2, 0x40, 0x13, 0xe0, 0xd1, 0x50, 0xf6, 0xe0, 0xdc, 0x30, 0x78, 0xe0, 0xd0, 0x50, 0xf6, 0xe0, 0xd5, 0x80, 0xb9, 0xe0, 0xd4, 0x20, 0x31, 0xe0, 0xf0, 0x50, 0xd9, 0xe1, 0xf7, 0x40, 0xd5, 0xe1, 0xf7, 0x33, 0xf6, 0xe1, 0xf9, 0x20, 0x57, 0xe0, 0xf5, 0x30, 0x91, 0xe1, 0xf1, 0x40, 0xb6, 0xe1, 0xf6, 0x50, 0x33, 0xe1, 0xf8, 0x60, 0x99, 0xe0, 0xf3, 0x70, 0x18, 0xe0, 0xf1, 0x50, 0xf6, 0xe0, 0xfc, 0x30, 0x78, 0xe0, 0xf0, 0x50, 0xf6, 0xe0, 0xf5, 0x80, 0xb9, 0xe0, 0xf4, 0x20, 0x31, 0xe0, 0x00, 0x80, 0x8c, 0xe5, 0x0c, 0x70, 0x81, 0xe5, 0x28, 0x30, 0xa5, 0xe5, 0xff, 0x9f, 0x8d, 0xe4, 0x80, 0x10, 0x07, 0xe4, 0x00, 0x10, 0x00, 0xe4, 0x03, 0x90, 0x86, 0xe7, 0x02, 0x80, 0x00, 0xe7, 0x06, 0x70, 0xa1, 0xe7, 0x01, 0x60, 0x2d, 0xe7, 0x09, 0x50, 0x83, 0xe6, 0x05, 0x40, 0x02, 0xe6, 0x02, 0x31, 0x04, 0xe7, 0x43, 0x2c, 0x87, 0xe6, 0x00, 0x90, 0xc2, 0xe5, 0x03, 0x70, 0xc1, 0xe5, 0x95, 0x61, 0xe4, 0xe5, 0x48, 0x50, 0xc7, 0xe4, 0x01, 0x10, 0x4d, 0xe4, 0x09, 0x10, 0xc2, 0xe7, 0x08, 0x20, 0x43, 0xe7, 0x07, 0x30, 0xe4, 0xe7, 0x06, 0x40, 0x65, 0xe7, 0x05, 0x50, 0xc6, 0xe6, 0x04, 0x60, 0x42, 0xe6, 0x83, 0x72, 0x4c, 0xe7, 0x42, 0xd6, 0xc7, 0xe6, 0x0c, 0x60, 0xe2, 0xe4, 0x0d, 0x50, 0x66, 0xe4, 0x05, 0x40, 0xe9, 0xe6, 0x82, 0x31, 0x68, 0xe6, 0xf0, 0x20, 0xc4, 0xe1, 0xf1, 0x20, 0xc6, 0xe1, 0xf6, 0x01, 0xe7, 0xe1, 0xf7, 0x40, 0xc8, 0xe0, 0xf0, 0x40, 0xcd, 0xe0, 0xf0, 0x60, 0xce, 0xe0, 0xf0, 0xa0, 0x49, 0xe0, 0xf1, 0x80, 0x84, 0xe1, 0xf9, 0x60, 0xa3, 0xe1, 0xf8, 0x60, 0x85, 0xe0, 0xfa, 0x40, 0x0c, 0xe0, 0xb0, 0x30, 0xc4, 0xe1, 0xb4, 0x20, 0xc7, 0xe1, 0xb0, 0x14, 0xe8, 0xe1, 0xb4, 0xc0, 0xcd, 0xe0, 0xb4, 0x60, 0x85, 0xe1, 0xbb, 0x30, 0xa8, 0xe1, 0xb1, 0x10, 0x22, 0xe1, 0xb2, 0x90, 0x87, 0xe0, 0xb2, 0x40, 0x03, 0xe0, 0xbc, 0x24, 0xe5, 0xe0, 0xb9, 0x81, 0x61, 0xe0, 0xb4, 0x50, 0xa3, 0xe0, 0xb0, 0x60, 0x28, 0xe0, 0xd0, 0x00, 0xcd, 0xe1, 0xf0, 0x00, 0xcd, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldr r5, [r7]" + - + asm_text: "ldr r6, [r3, #0x3f]" + - + asm_text: "ldr r2, [r4, #0xfff]!" + - + asm_text: "ldr r1, [r2], #0x1e" + - + asm_text: "ldr r3, [r1], #-0x1e" + - + asm_text: "ldr r9, [r2], #-0" + - + asm_text: "ldr r3, [r8, r1]" + - + asm_text: "ldr r2, [r5, -r3]" + - + asm_text: "ldr r1, [r5, r9]!" + - + asm_text: "ldr r6, [r7, -r8]!" + - + asm_text: "ldr r1, [r0, r2, lsr #3]!" + - + asm_text: "ldr r5, [r9], r2" + - + asm_text: "ldr r4, [r3], -r6" + - + asm_text: "ldr r3, [r8, -r2, lsl #0xf]" + - + asm_text: "ldr r1, [r5], r3, asr #0xf" + - + asm_text: "ldrb r3, [r8]" + - + asm_text: "ldrb r1, [sp, #0x3f]" + - + asm_text: "ldrb r9, [r3, #0xfff]!" + - + asm_text: "ldrb r8, [r1], #0x16" + - + asm_text: "ldrb r2, [r7], #-0x13" + - + asm_text: "ldrb r9, [r8, r5]" + - + asm_text: "ldrb r1, [r5, -r1]" + - + asm_text: "ldrb r3, [r5, r2]!" + - + asm_text: "ldrb r6, [r9, -r3]!" + - + asm_text: "ldrb r2, [r1], r4" + - + asm_text: "ldrb r8, [r4], -r5" + - + asm_text: "ldrb r7, [r12, -r1, lsl #0xf]" + - + asm_text: "ldrb r5, [r2], r9, asr #0xf" + - + asm_text: "ldrbt r3, [r1], #4" + - + asm_text: "ldrbt r2, [r8], #-8" + - + asm_text: "ldrbt r8, [r7], r6" + - + asm_text: "ldrbt r1, [r2], -r6, lsl #0xc" + - + asm_text: "ldrd r2, r3, [r5]" + - + asm_text: "ldrd r6, r7, [r2, #0xf]" + - + asm_text: "ldrd r0, r1, [r9, #0x20]!" + - + asm_text: "ldrd r6, r7, [r1], #8" + - + asm_text: "ldrd r0, r1, [r8], #0" + - + asm_text: "ldrd r0, r1, [r8], #0" + - + asm_text: "ldrd r0, r1, [r8], #-0" + - + asm_text: "ldrd r4, r5, [r1, r3]" + - + asm_text: "ldrd r4, r5, [r7, r2]!" + - + asm_text: "ldrd r0, r1, [r8], r12" + - + asm_text: "ldrd r0, r1, [r8], -r12" + - + asm_text: "ldrh r3, [r4]" + - + asm_text: "ldrh r2, [r7, #4]" + - + asm_text: "ldrh r1, [r8, #0x40]!" + - + asm_text: "ldrh r12, [sp], #4" + - + asm_text: "ldrh r6, [r5, r4]" + - + asm_text: "ldrh r3, [r8, r11]!" + - + asm_text: "ldrh r1, [r2, -r1]!" + - + asm_text: "ldrh r9, [r7], r2" + - + asm_text: "ldrh r4, [r3], -r2" + - + asm_text: "ldrht r9, [r7], #0x80" + - + asm_text: "ldrht r4, [r3], #-0x4b" + - + asm_text: "ldrht r4, [r3], #0" + - + asm_text: "ldrht r9, [r7], r2" + - + asm_text: "ldrht r4, [r3], -r2" + - + asm_text: "ldrsb r3, [r4]" + - + asm_text: "ldrsb r2, [r7, #0x11]" + - + asm_text: "ldrsb r1, [r8, #0xff]!" + - + asm_text: "ldrsb r12, [sp], #0x9" + - + asm_text: "ldrsb r6, [r5, r4]" + - + asm_text: "ldrsb r3, [r8, r11]!" + - + asm_text: "ldrsb r1, [r2, -r1]!" + - + asm_text: "ldrsb r9, [r7], r2" + - + asm_text: "ldrsb r4, [r3], -r2" + - + asm_text: "ldrsbt r5, [r6], #1" + - + asm_text: "ldrsbt r3, [r8], #-0xc" + - + asm_text: "ldrsbt r5, [r6], #0" + - + asm_text: "ldrsbt r8, [r9], r5" + - + asm_text: "ldrsbt r2, [r1], -r4" + - + asm_text: "ldrsh r5, [r9]" + - + asm_text: "ldrsh r4, [r5, #7]" + - + asm_text: "ldrsh r3, [r6, #0x37]!" + - + asm_text: "ldrsh r2, [r7], #-0x9" + - + asm_text: "ldrsh r3, [r1, r5]" + - + asm_text: "ldrsh r4, [r6, r1]!" + - + asm_text: "ldrsh r5, [r3, -r6]!" + - + asm_text: "ldrsh r6, [r9], r8" + - + asm_text: "ldrsh r7, [r8], -r3" + - + asm_text: "ldrsht r5, [r6], #1" + - + asm_text: "ldrsht r3, [r8], #-0xc" + - + asm_text: "ldrsht r5, [r6], #0" + - + asm_text: "ldrsht r8, [r9], r5" + - + asm_text: "ldrsht r2, [r1], -r4" + - + asm_text: "str r8, [r12]" + - + asm_text: "str r7, [r1, #0xc]" + - + asm_text: "str r3, [r5, #0x28]!" + - + asm_text: "str r9, [sp], #0xfff" + - + asm_text: "str r1, [r7], #-0x80" + - + asm_text: "str r1, [r0], #-0" + - + asm_text: "str r9, [r6, r3]" + - + asm_text: "str r8, [r0, -r2]" + - + asm_text: "str r7, [r1, r6]!" + - + asm_text: "str r6, [sp, -r1]!" + - + asm_text: "str r5, [r3], r9" + - + asm_text: "str r4, [r2], -r5" + - + asm_text: "str r3, [r4, -r2, lsl #2]" + - + asm_text: "str r2, [r7], r3, asr #0x18" + - + asm_text: "strb r9, [r2]" + - + asm_text: "strb r7, [r1, #3]" + - + asm_text: "strb r6, [r4, #0x195]!" + - + asm_text: "strb r5, [r7], #0x48" + - + asm_text: "strb r1, [sp], #-1" + - + asm_text: "strb r1, [r2, r9]" + - + asm_text: "strb r2, [r3, -r8]" + - + asm_text: "strb r3, [r4, r7]!" + - + asm_text: "strb r4, [r5, -r6]!" + - + asm_text: "strb r5, [r6], r5" + - + asm_text: "strb r6, [r2], -r4" + - + asm_text: "strb r7, [r12, -r3, lsl #5]" + - + asm_text: "strb sp, [r7], r2, asr #0xc" + - + asm_text: "strbt r6, [r2], #0xc" + - + asm_text: "strbt r5, [r6], #-0xd" + - + asm_text: "strbt r4, [r9], r5" + - + asm_text: "strbt r3, [r8], -r2, lsl #3" + - + asm_text: "strd r2, r3, [r4]" + - + asm_text: "strd r2, r3, [r6, #1]" + - + asm_text: "strd r0, r1, [r7, #0x16]!" + - + asm_text: "strd r4, r5, [r8], #7" + - + asm_text: "strd r4, r5, [sp], #0" + - + asm_text: "strd r6, r7, [lr], #0" + - + asm_text: "strd r10, r11, [r9], #-0" + - + asm_text: "strd r8, r9, [r4, r1]" + - + asm_text: "strd r6, r7, [r3, r9]!" + - + asm_text: "strd r6, r7, [r5], r8" + - + asm_text: "strd r4, r5, [r12], -r10" + - + asm_text: "strh r3, [r4]" + - + asm_text: "strh r2, [r7, #4]" + - + asm_text: "strh r1, [r8, #0x40]!" + - + asm_text: "strh r12, [sp], #4" + - + asm_text: "strh r6, [r5, r4]" + - + asm_text: "strh r3, [r8, r11]!" + - + asm_text: "strh r1, [r2, -r1]!" + - + asm_text: "strh r9, [r7], r2" + - + asm_text: "strh r4, [r3], -r2" + - + asm_text: "strht r2, [r5], #0x4c" + - + asm_text: "strht r8, [r1], #-0x19" + - + asm_text: "strht r5, [r3], r4" + - + asm_text: "strht r6, [r8], -r0" + - + asm_text: "ldrd r0, r1, [sp]" + - + asm_text: "strd r0, r1, [sp]" diff --git a/thirdparty/capstone/tests/MC/ARM/arm-shift-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/arm-shift-encoding.s.yaml new file mode 100644 index 0000000..4258d2f --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/arm-shift-encoding.s.yaml @@ -0,0 +1,106 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x90, 0xe7, 0x20, 0x00, 0x90, 0xe7, 0x20, 0x08, 0x90, 0xe7, 0x00, 0x00, 0x90, 0xe7, 0x00, 0x08, 0x90, 0xe7, 0x40, 0x00, 0x90, 0xe7, 0x40, 0x08, 0x90, 0xe7, 0x60, 0x00, 0x90, 0xe7, 0x60, 0x08, 0x90, 0xe7, 0x00, 0xf0, 0xd0, 0xf7, 0x20, 0xf0, 0xd0, 0xf7, 0x20, 0xf8, 0xd0, 0xf7, 0x00, 0xf0, 0xd0, 0xf7, 0x00, 0xf8, 0xd0, 0xf7, 0x40, 0xf0, 0xd0, 0xf7, 0x40, 0xf8, 0xd0, 0xf7, 0x60, 0xf0, 0xd0, 0xf7, 0x60, 0xf8, 0xd0, 0xf7, 0x00, 0x00, 0x80, 0xe7, 0x20, 0x00, 0x80, 0xe7, 0x20, 0x08, 0x80, 0xe7, 0x00, 0x00, 0x80, 0xe7, 0x00, 0x08, 0x80, 0xe7, 0x40, 0x00, 0x80, 0xe7, 0x40, 0x08, 0x80, 0xe7, 0x60, 0x00, 0x80, 0xe7, 0x60, 0x08, 0x80, 0xe7, 0x62, 0x00, 0x91, 0xe6, 0x05, 0x30, 0x94, 0xe6, 0x08, 0x60, 0x87, 0xe6, 0x0b, 0x90, 0x8a, 0xe6, 0x0f, 0xd0, 0xae, 0xe0, 0x29, 0x10, 0xa8, 0xe0, 0x2f, 0x28, 0xa7, 0xe0, 0x0a, 0x30, 0xa6, 0xe0, 0x0e, 0x48, 0xa5, 0xe0, 0x4b, 0x50, 0xa4, 0xe0, 0x4d, 0x68, 0xa3, 0xe0, 0x6c, 0x70, 0xa2, 0xe0, 0x60, 0x88, 0xa1, 0xe0, 0x0e, 0x00, 0x5d, 0xe1, 0x28, 0x00, 0x51, 0xe1, 0x27, 0x08, 0x52, 0xe1, 0x06, 0x00, 0x53, 0xe1, 0x05, 0x08, 0x54, 0xe1, 0x44, 0x00, 0x55, 0xe1, 0x43, 0x08, 0x56, 0xe1, 0x62, 0x00, 0x57, 0xe1, 0x61, 0x08, 0x58, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldr r0, [r0, r0]" + - + asm_text: "ldr r0, [r0, r0, lsr #0x20]" + - + asm_text: "ldr r0, [r0, r0, lsr #0x10]" + - + asm_text: "ldr r0, [r0, r0]" + - + asm_text: "ldr r0, [r0, r0, lsl #0x10]" + - + asm_text: "ldr r0, [r0, r0, asr #0x20]" + - + asm_text: "ldr r0, [r0, r0, asr #0x10]" + - + asm_text: "ldr r0, [r0, r0, rrx]" + - + asm_text: "ldr r0, [r0, r0, ror #0x10]" + - + asm_text: "pld [r0, r0]" + - + asm_text: "pld [r0, r0, lsr #0x20]" + - + asm_text: "pld [r0, r0, lsr #0x10]" + - + asm_text: "pld [r0, r0]" + - + asm_text: "pld [r0, r0, lsl #0x10]" + - + asm_text: "pld [r0, r0, asr #0x20]" + - + asm_text: "pld [r0, r0, asr #0x10]" + - + asm_text: "pld [r0, r0, rrx]" + - + asm_text: "pld [r0, r0, ror #0x10]" + - + asm_text: "str r0, [r0, r0]" + - + asm_text: "str r0, [r0, r0, lsr #0x20]" + - + asm_text: "str r0, [r0, r0, lsr #0x10]" + - + asm_text: "str r0, [r0, r0]" + - + asm_text: "str r0, [r0, r0, lsl #0x10]" + - + asm_text: "str r0, [r0, r0, asr #0x20]" + - + asm_text: "str r0, [r0, r0, asr #0x10]" + - + asm_text: "str r0, [r0, r0, rrx]" + - + asm_text: "str r0, [r0, r0, ror #0x10]" + - + asm_text: "ldr r0, [r1], r2, rrx" + - + asm_text: "ldr r3, [r4], r5" + - + asm_text: "str r6, [r7], r8" + - + asm_text: "str r9, [r10], r11" + - + asm_text: "adc sp, lr, pc" + - + asm_text: "adc r1, r8, r9, lsr #0x20" + - + asm_text: "adc r2, r7, pc, lsr #0x10" + - + asm_text: "adc r3, r6, r10" + - + asm_text: "adc r4, r5, lr, lsl #0x10" + - + asm_text: "adc r5, r4, r11, asr #0x20" + - + asm_text: "adc r6, r3, sp, asr #0x10" + - + asm_text: "adc r7, r2, r12, rrx" + - + asm_text: "adc r8, r1, r0, ror #0x10" + - + asm_text: "cmp sp, lr" + - + asm_text: "cmp r1, r8, lsr #0x20" + - + asm_text: "cmp r2, r7, lsr #0x10" + - + asm_text: "cmp r3, r6" + - + asm_text: "cmp r4, r5, lsl #0x10" + - + asm_text: "cmp r5, r4, asr #0x20" + - + asm_text: "cmp r6, r3, asr #0x10" + - + asm_text: "cmp r7, r2, rrx" + - + asm_text: "cmp r8, r1, ror #0x10" diff --git a/thirdparty/capstone/tests/MC/ARM/arm-thumb-trustzone.s.yaml b/thirdparty/capstone/tests/MC/ARM/arm-thumb-trustzone.s.yaml new file mode 100644 index 0000000..5ce7956 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/arm-thumb-trustzone.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xf7, 0x00, 0x80, 0x0c, 0xbf ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "smc #15" + - + asm_text: "ite eq" diff --git a/thirdparty/capstone/tests/MC/ARM/arm-trustzone.s.yaml b/thirdparty/capstone/tests/MC/ARM/arm-trustzone.s.yaml new file mode 100644 index 0000000..09f1141 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/arm-trustzone.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x7f, 0x00, 0x60, 0xe1, 0x70, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "smc #15" + - + asm_text: "smceq #0" diff --git a/thirdparty/capstone/tests/MC/ARM/arm_addrmode2.s.yaml b/thirdparty/capstone/tests/MC/ARM/arm_addrmode2.s.yaml new file mode 100644 index 0000000..0d55f55 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/arm_addrmode2.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0x02, 0x10, 0xb0, 0xe6, 0xa2, 0x11, 0xb0, 0xe6, 0x04, 0x10, 0xb0, 0xe4, 0x00, 0x10, 0xb0, 0xe4, 0x02, 0x10, 0xf0, 0xe6, 0xa2, 0x11, 0xf0, 0xe6, 0x04, 0x10, 0xf0, 0xe4, 0x00, 0x10, 0xf0, 0xe4, 0x02, 0x10, 0xa0, 0xe6, 0xa2, 0x11, 0xa0, 0xe6, 0x04, 0x10, 0xa0, 0xe4, 0x00, 0x10, 0xa0, 0xe4, 0x02, 0x10, 0xe0, 0xe6, 0xa2, 0x11, 0xe0, 0xe6, 0x04, 0x10, 0xe0, 0xe4, 0x00, 0x10, 0xe0, 0xe4, 0xa2, 0x11, 0xb0, 0xe7, 0xa2, 0x11, 0xf0, 0xe7 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldrt r1, [r0], r2" + - + asm_text: "ldrt r1, [r0], r2, lsr #3" + - + asm_text: "ldrt r1, [r0], #4" + - + asm_text: "ldrt r1, [r0], #0" + - + asm_text: "ldrbt r1, [r0], r2" + - + asm_text: "ldrbt r1, [r0], r2, lsr #3" + - + asm_text: "ldrbt r1, [r0], #4" + - + asm_text: "ldrbt r1, [r0], #0" + - + asm_text: "strt r1, [r0], r2" + - + asm_text: "strt r1, [r0], r2, lsr #3" + - + asm_text: "strt r1, [r0], #4" + - + asm_text: "strt r1, [r0], #0" + - + asm_text: "strbt r1, [r0], r2" + - + asm_text: "strbt r1, [r0], r2, lsr #3" + - + asm_text: "strbt r1, [r0], #4" + - + asm_text: "strbt r1, [r0], #0" + - + asm_text: "ldr r1, [r0, r2, lsr #3]!" + - + asm_text: "ldrb r1, [r0, r2, lsr #3]!" diff --git a/thirdparty/capstone/tests/MC/ARM/arm_addrmode3.s.yaml b/thirdparty/capstone/tests/MC/ARM/arm_addrmode3.s.yaml new file mode 100644 index 0000000..2a6a95d --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/arm_addrmode3.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0xd2, 0x10, 0xb0, 0xe0, 0xd4, 0x10, 0xf0, 0xe0, 0xf2, 0x10, 0xb0, 0xe0, 0xf4, 0x10, 0xf0, 0xe0, 0xb2, 0x10, 0xb0, 0xe0, 0xb4, 0x10, 0xf0, 0xe0, 0xb2, 0x10, 0xa0, 0xe0, 0xb4, 0x10, 0xe0, 0xe0 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldrsbt r1, [r0], r2" + - + asm_text: "ldrsbt r1, [r0], #4" + - + asm_text: "ldrsht r1, [r0], r2" + - + asm_text: "ldrsht r1, [r0], #4" + - + asm_text: "ldrht r1, [r0], r2" + - + asm_text: "ldrht r1, [r0], #4" + - + asm_text: "strht r1, [r0], r2" + - + asm_text: "strht r1, [r0], #4" diff --git a/thirdparty/capstone/tests/MC/ARM/arm_instructions.s.yaml b/thirdparty/capstone/tests/MC/ARM/arm_instructions.s.yaml new file mode 100644 index 0000000..72559b8 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/arm_instructions.s.yaml @@ -0,0 +1,52 @@ +test_cases: + - + input: + bytes: [ 0x03, 0x10, 0x02, 0xe0, 0x03, 0x10, 0x12, 0xe0, 0x03, 0x10, 0x22, 0xe0, 0x03, 0x10, 0x32, 0xe0, 0x03, 0x10, 0x42, 0xe0, 0x03, 0x10, 0x52, 0xe0, 0x03, 0x10, 0x82, 0xe0, 0x03, 0x10, 0x92, 0xe0, 0x03, 0x10, 0xa2, 0xe0, 0x03, 0x10, 0xc2, 0xe1, 0x03, 0x10, 0xd2, 0xe1, 0x02, 0x10, 0xa0, 0xe1, 0x02, 0x10, 0xe0, 0xe1, 0x02, 0x10, 0xf0, 0xe1, 0x90, 0x02, 0xcb, 0xe7, 0x7a, 0x00, 0x20, 0xe1, 0x81, 0x17, 0x11, 0xee, 0x81, 0x17, 0x11, 0xfe, 0x13, 0x14, 0x82, 0xe0, 0x30, 0x0f, 0xa6, 0xe6, 0x00, 0x00, 0x0a, 0xf1, 0xb0, 0x30, 0x42, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "and r1, r2, r3" + - + asm_text: "ands r1, r2, r3" + - + asm_text: "eor r1, r2, r3" + - + asm_text: "eors r1, r2, r3" + - + asm_text: "sub r1, r2, r3" + - + asm_text: "subs r1, r2, r3" + - + asm_text: "add r1, r2, r3" + - + asm_text: "adds r1, r2, r3" + - + asm_text: "adc r1, r2, r3" + - + asm_text: "bic r1, r2, r3" + - + asm_text: "bics r1, r2, r3" + - + asm_text: "mov r1, r2" + - + asm_text: "mvn r1, r2" + - + asm_text: "mvns r1, r2" + - + asm_text: "bfi r0, r0, #5, #7" + - + asm_text: "bkpt #0xa" + - + asm_text: "cdp p7, #1, c1, c1, c1, #4" + - + asm_text: "cdp2 p7, #1, c1, c1, c1, #4" + - + asm_text: "add r1, r2, r3, lsl r4" + - + asm_text: "ssat16 r0, #7, r0" + - + asm_text: "cpsie none, #0" + - + asm_text: "strh r3, [r2, #-0]" diff --git a/thirdparty/capstone/tests/MC/ARM/armv8.1m-pacbti.s.yaml b/thirdparty/capstone/tests/MC/ARM/armv8.1m-pacbti.s.yaml new file mode 100644 index 0000000..c0b5282 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/armv8.1m-pacbti.s.yaml @@ -0,0 +1,18 @@ +test_cases: + - + input: + bytes: [ 0xaf, 0xf3, 0x2d, 0x80, 0xaf, 0xf3, 0x0f, 0x80, 0xaf, 0xf3, 0x0f, 0x80, 0xaf, 0xf3, 0x1d, 0x80, 0xaf, 0xf3, 0x0d, 0x80 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "aut r12, lr, sp" + - + asm_text: "bti" + - + asm_text: "bti" + - + asm_text: "pac r12, lr, sp" + - + asm_text: "pacbti r12, lr, sp" diff --git a/thirdparty/capstone/tests/MC/ARM/armv8.2a-dotprod-a32.s.yaml b/thirdparty/capstone/tests/MC/ARM/armv8.2a-dotprod-a32.s.yaml new file mode 100644 index 0000000..5ae5ce2 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/armv8.2a-dotprod-a32.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x12, 0x0d, 0x21, 0xfc, 0x02, 0x0d, 0x21, 0xfc, 0x58, 0x0d, 0x22, 0xfc, 0x48, 0x0d, 0x22, 0xfc, 0x12, 0x0d, 0x21, 0xfe, 0x22, 0x0d, 0x21, 0xfe, 0x54, 0x0d, 0x22, 0xfe, 0x64, 0x0d, 0x22, 0xfe ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vudot.u8 d0, d1, d2" + - + asm_text: "vsdot.s8 d0, d1, d2" + - + asm_text: "vudot.u8 q0, q1, q4" + - + asm_text: "vsdot.s8 q0, q1, q4" + - + asm_text: "vudot.u8 d0, d1, d2[0]" + - + asm_text: "vsdot.s8 d0, d1, d2[1]" + - + asm_text: "vudot.u8 q0, q1, d4[0]" + - + asm_text: "vsdot.s8 q0, q1, d4[1]" diff --git a/thirdparty/capstone/tests/MC/ARM/armv8.2a-dotprod-t32.s.yaml b/thirdparty/capstone/tests/MC/ARM/armv8.2a-dotprod-t32.s.yaml new file mode 100644 index 0000000..218c43f --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/armv8.2a-dotprod-t32.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x21, 0xfc, 0x12, 0x0d, 0x21, 0xfc, 0x02, 0x0d, 0x22, 0xfc, 0x58, 0x0d, 0x22, 0xfc, 0x48, 0x0d, 0x21, 0xfe, 0x12, 0x0d, 0x21, 0xfe, 0x22, 0x0d, 0x22, 0xfe, 0x54, 0x0d, 0x22, 0xfe, 0x64, 0x0d ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vudot.u8 d0, d1, d2" + - + asm_text: "vsdot.s8 d0, d1, d2" + - + asm_text: "vudot.u8 q0, q1, q4" + - + asm_text: "vsdot.s8 q0, q1, q4" + - + asm_text: "vudot.u8 d0, d1, d2[0]" + - + asm_text: "vsdot.s8 d0, d1, d2[1]" + - + asm_text: "vudot.u8 q0, q1, d4[0]" + - + asm_text: "vsdot.s8 q0, q1, d4[1]" diff --git a/thirdparty/capstone/tests/MC/ARM/armv8.5a-sb.s.yaml b/thirdparty/capstone/tests/MC/ARM/armv8.5a-sb.s.yaml new file mode 100644 index 0000000..63e3e71 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/armv8.5a-sb.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x70, 0xf0, 0x7f, 0xf5 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "sb" diff --git a/thirdparty/capstone/tests/MC/ARM/armv8a-fpmul.s.yaml b/thirdparty/capstone/tests/MC/ARM/armv8a-fpmul.s.yaml new file mode 100644 index 0000000..901d69f --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/armv8a-fpmul.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x91, 0x08, 0x20, 0xfc, 0x91, 0x08, 0xa0, 0xfc, 0x52, 0x08, 0x21, 0xfc, 0x52, 0x08, 0xa1, 0xfc, 0x99, 0x08, 0x00, 0xfe, 0x99, 0x08, 0x10, 0xfe, 0x7a, 0x08, 0x01, 0xfe, 0x7a, 0x08, 0x11, 0xfe ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vfmal.f16 d0, s1, s2" + - + asm_text: "vfmsl.f16 d0, s1, s2" + - + asm_text: "vfmal.f16 q0, d1, d2" + - + asm_text: "vfmsl.f16 q0, d1, d2" + - + asm_text: "vfmal.f16 d0, s1, s2[1]" + - + asm_text: "vfmsl.f16 d0, s1, s2[1]" + - + asm_text: "vfmal.f16 q0, d1, d2[3]" + - + asm_text: "vfmsl.f16 q0, d1, d2[3]" diff --git a/thirdparty/capstone/tests/MC/ARM/basic-arm-instructions-v8.s.yaml b/thirdparty/capstone/tests/MC/ARM/basic-arm-instructions-v8.s.yaml new file mode 100644 index 0000000..8a92264 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/basic-arm-instructions-v8.s.yaml @@ -0,0 +1,26 @@ +test_cases: + - + input: + bytes: [ 0x59, 0xf0, 0x7f, 0xf5, 0x51, 0xf0, 0x7f, 0xf5, 0x55, 0xf0, 0x7f, 0xf5, 0x5d, 0xf0, 0x7f, 0xf5, 0x49, 0xf0, 0x7f, 0xf5, 0x41, 0xf0, 0x7f, 0xf5, 0x45, 0xf0, 0x7f, 0xf5, 0x4d, 0xf0, 0x7f, 0xf5, 0x05, 0xf0, 0x20, 0xe3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "dmb ishld" + - + asm_text: "dmb oshld" + - + asm_text: "dmb nshld" + - + asm_text: "dmb ld" + - + asm_text: "dsb ishld" + - + asm_text: "dsb oshld" + - + asm_text: "dsb nshld" + - + asm_text: "dsb ld" + - + asm_text: "sevl" diff --git a/thirdparty/capstone/tests/MC/ARM/basic-arm-instructions.s.yaml b/thirdparty/capstone/tests/MC/ARM/basic-arm-instructions.s.yaml new file mode 100644 index 0000000..ed1fbc0 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/basic-arm-instructions.s.yaml @@ -0,0 +1,2616 @@ +test_cases: + - + input: + bytes: [ 0x0f, 0x10, 0xa2, 0xe2, 0x0f, 0x10, 0xa2, 0xe2, 0x0f, 0x10, 0xa2, 0xe2, 0xff, 0x78, 0xa8, 0xe2, 0x2a, 0x71, 0xa8, 0xe2, 0x2a, 0x71, 0xa8, 0xe2, 0x28, 0x71, 0xa8, 0xe2, 0x28, 0x71, 0xa8, 0xe2, 0x28, 0x71, 0xa8, 0xe2, 0x28, 0x71, 0xa8, 0xe2, 0xf0, 0x10, 0xa2, 0xe2, 0x0f, 0x1c, 0xa2, 0xe2, 0x0f, 0x1a, 0xa2, 0xe2, 0x0f, 0x18, 0xa2, 0xe2, 0x0f, 0x16, 0xa2, 0xe2, 0x0f, 0x14, 0xa2, 0xe2, 0x0f, 0x12, 0xa2, 0xe2, 0xff, 0x12, 0xa2, 0xe2, 0x0f, 0x1c, 0xb2, 0xe2, 0x28, 0x71, 0xb8, 0xe2, 0x0f, 0x1c, 0xb2, 0x02, 0x0f, 0x1c, 0xa2, 0x02, 0x06, 0x40, 0xa5, 0xe0, 0x86, 0x40, 0xa5, 0xe0, 0x86, 0x4f, 0xa5, 0xe0, 0xa6, 0x40, 0xa5, 0xe0, 0xa6, 0x4f, 0xa5, 0xe0, 0x26, 0x40, 0xa5, 0xe0, 0xc6, 0x40, 0xa5, 0xe0, 0xc6, 0x4f, 0xa5, 0xe0, 0x46, 0x40, 0xa5, 0xe0, 0xe6, 0x40, 0xa5, 0xe0, 0xe6, 0x4f, 0xa5, 0xe0, 0x18, 0x69, 0xa7, 0xe0, 0x38, 0x69, 0xa7, 0xe0, 0x58, 0x69, 0xa7, 0xe0, 0x78, 0x69, 0xa7, 0xe0, 0x66, 0x40, 0xa5, 0xe0, 0x06, 0x50, 0xa5, 0xe0, 0x85, 0x40, 0xa4, 0xe0, 0x85, 0x4f, 0xa4, 0xe0, 0xa5, 0x40, 0xa4, 0xe0, 0xa5, 0x4f, 0xa4, 0xe0, 0x25, 0x40, 0xa4, 0xe0, 0xc5, 0x40, 0xa4, 0xe0, 0xc5, 0x4f, 0xa4, 0xe0, 0x45, 0x40, 0xa4, 0xe0, 0xe5, 0x40, 0xa4, 0xe0, 0xe5, 0x4f, 0xa4, 0xe0, 0x65, 0x40, 0xa4, 0xe0, 0x17, 0x69, 0xa6, 0xe0, 0x37, 0x69, 0xa6, 0xe0, 0x57, 0x69, 0xa6, 0xe0, 0x77, 0x69, 0xa6, 0xe0, 0x65, 0x40, 0xa4, 0xe0, 0x03, 0x20, 0x8f, 0xe2, 0x03, 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0xe1, 0xa5, 0x02, 0x34, 0xe1, 0xa5, 0x02, 0x34, 0xe1, 0xc5, 0x02, 0x34, 0xe1, 0xe5, 0x02, 0x34, 0xe1, 0x17, 0x09, 0x36, 0xe1, 0x37, 0x09, 0x36, 0xe1, 0x57, 0x09, 0x36, 0xe1, 0x77, 0x09, 0x36, 0xe1, 0x0f, 0x0a, 0x15, 0xe3, 0x0f, 0x0a, 0x15, 0xe3, 0x0f, 0x0a, 0x15, 0xe3, 0xff, 0x08, 0x17, 0xe3, 0x2a, 0x01, 0x17, 0xe3, 0x2a, 0x01, 0x17, 0xe3, 0x28, 0x01, 0x17, 0xe3, 0x28, 0x01, 0x17, 0xe3, 0x28, 0x01, 0x17, 0xe3, 0x28, 0x01, 0x17, 0xe3, 0x05, 0x00, 0x14, 0xe1, 0x85, 0x02, 0x14, 0xe1, 0xa5, 0x02, 0x14, 0xe1, 0xa5, 0x02, 0x14, 0xe1, 0xc5, 0x02, 0x14, 0xe1, 0xe5, 0x02, 0x14, 0xe1, 0x17, 0x09, 0x16, 0xe1, 0x37, 0x09, 0x16, 0xe1, 0x57, 0x09, 0x16, 0xe1, 0x77, 0x09, 0x16, 0xe1, 0x13, 0x1f, 0x52, 0xe6, 0x13, 0x1f, 0x52, 0xc6, 0x93, 0x1f, 0x52, 0xe6, 0x93, 0x1f, 0x52, 0xd6, 0x30, 0x9f, 0x5c, 0xe6, 0x30, 0x9f, 0x5c, 0x06, 0x55, 0x48, 0xe0, 0xe7, 0x55, 0x48, 0xef, 0xc7, 0x12, 0x4f, 0x78, 0xe6, 0x12, 0x4f, 0x78, 0xc6, 0x92, 0x4f, 0x78, 0xe6, 0x92, 0x4f, 0x78, 0xc6, 0x32, 0x4f, 0x78, 0xe6, 0x32, 0x4f, 0x78, 0xc6, 0x72, 0x4f, 0x78, 0xe6, 0x72, 0x4f, 0x78, 0xc6, 0xf2, 0x4f, 0x78, 0xe6, 0xf2, 0x4f, 0x78, 0xc6, 0x95, 0x36, 0x44, 0xe0, 0x95, 0x36, 0x44, 0xb0, 0x96, 0x28, 0xa4, 0xe0, 0x92, 0x66, 0xa1, 0xc0, 0x92, 0x23, 0xb9, 0xe0, 0x91, 0x32, 0xb5, 0x00, 0x96, 0x28, 0x84, 0xe0, 0x92, 0x66, 0x81, 0xc0, 0x92, 0x23, 0x99, 0xe0, 0x91, 0x32, 0x95, 0x00, 0x13, 0x1f, 0x62, 0xe6, 0x19, 0x4f, 0x67, 0xc6, 0x98, 0x3f, 0x64, 0xe6, 0x92, 0x8f, 0x61, 0xd6, 0x31, 0x2f, 0x64, 0xe6, 0x39, 0x5f, 0x62, 0x86, 0x57, 0x1f, 0x63, 0xe6, 0x52, 0x3f, 0x66, 0xe6, 0x73, 0x1f, 0x65, 0xe6, 0x75, 0x3f, 0x62, 0xc6, 0xf4, 0x2f, 0x61, 0xe6, 0xf9, 0x4f, 0x66, 0xd6, 0x11, 0xf4, 0x82, 0xe7, 0x16, 0xf9, 0x84, 0xd7, 0x15, 0x73, 0x81, 0xe7, 0x12, 0x15, 0x83, 0xc7, 0x1a, 0x80, 0xe1, 0xe6, 0x1a, 0x80, 0xe4, 0xe6, 0x9a, 0x8f, 0xe5, 0xe6, 0x5a, 0x80, 0xff, 0xe6, 0xda, 0x80, 0xf0, 0xe6, 0x37, 0x2f, 0xe2, 0xe6, 0x35, 0x3f, 0xef, 0xe6, 0x54, 0x2f, 0x53, 0xe6, 0x54, 0x2f, 0x53, 0x16, 0x77, 0x4f, 0x52, 0xe6, 0x73, 0x1f, 0x51, 0x86, 0xf5, 0x1f, 0x58, 0xe6, 0xf3, 0x9f, 0x52, 0xd6, 0x74, 0x20, 0xe3, 0xe6, 0x76, 0x40, 0xe5, 0xe6, 0x79, 0x64, 0xe2, 0xb6, 0x74, 0x58, 0xe1, 0xe6, 0x73, 0x7c, 0xe8, 0xe6, 0x74, 0x00, 0xc1, 0xa6, 0x77, 0x60, 0xc2, 0xe6, 0x78, 0x34, 0xc5, 0xe6, 0x71, 0x38, 0xc2, 0xe6, 0x73, 0x1c, 0xc2, 0x06, 0x79, 0x10, 0xf3, 0xe6, 0x76, 0x60, 0xf1, 0x86, 0x73, 0x34, 0xf8, 0xe6, 0x74, 0x28, 0xf2, 0x36, 0x73, 0x9c, 0xf3, 0xe6, 0x74, 0x20, 0xef, 0xa6, 0x76, 0x50, 0xef, 0xe6, 0x79, 0x64, 0xef, 0xe6, 0x71, 0x58, 0xef, 0x36, 0x73, 0x8c, 0xef, 0xe6, 0x74, 0x10, 0xcf, 0xe6, 0x77, 0x60, 0xcf, 0xe6, 0x75, 0x34, 0xcf, 0x26, 0x71, 0x38, 0xcf, 0xe6, 0x73, 0x2c, 0xcf, 0xa6, 0x79, 0x30, 0xff, 0x16, 0x76, 0x10, 0xff, 0xe6, 0x78, 0x34, 0xff, 0xe6, 0x72, 0x28, 0xff, 0xd6, 0x73, 0x9c, 0xff, 0xe6, 0x02, 0xf0, 0x20, 0xe3, 0x02, 0xf0, 0x20, 0x83, 0x03, 0xf0, 0x20, 0xe3, 0x03, 0xf0, 0x20, 0xb3, 0x01, 0xf0, 0x20, 0xe3, 0x01, 0xf0, 0x20, 0x13, 0x04, 0xf0, 0x20, 0xe3, 0x03, 0xf0, 0x20, 0xe3, 0x02, 0xf0, 0x20, 0xe3, 0x01, 0xf0, 0x20, 0xe3, 0x00, 0xf0, 0x20, 0xe3, 0xef, 0xf0, 0x20, 0xc3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "adc r1, r2, #0xf" + - + asm_text: "adc r1, r2, #0xf" + - + asm_text: "adc r1, r2, #0xf" + - + asm_text: "adc r7, r8, #0xff0000" + - + asm_text: "adc r7, r8, #-0x7ffffff6" + - + asm_text: "adc r7, r8, #-0x7ffffff6" + - + asm_text: "adc r7, r8, #0x28, #2" + - + asm_text: "adc r7, r8, #0x28, #2" + - + asm_text: "adc r7, r8, #0x28, #2" + - + asm_text: "adc r7, r8, #0x28, #2" + - + asm_text: "adc r1, r2, #0xf0" + - + asm_text: "adc r1, r2, #0xf00" + - + asm_text: "adc r1, r2, #0xf000" + - + asm_text: "adc r1, r2, #0xf0000" + - + asm_text: "adc r1, r2, #0xf00000" + - + asm_text: "adc r1, r2, #0xf000000" + - + asm_text: "adc r1, r2, #-0x10000000" + - + asm_text: "adc r1, r2, #-0xffffff1" + - + asm_text: "adcs r1, r2, #0xf00" + - + asm_text: "adcs r7, r8, #0x28, #2" + - + asm_text: "adcseq r1, r2, #0xf00" + - + asm_text: "adceq r1, r2, #0xf00" + - + asm_text: "adc r4, r5, r6" + - + asm_text: "adc r4, r5, r6, lsl #1" + - + asm_text: "adc r4, r5, r6, lsl #0x1f" + - + asm_text: "adc r4, r5, r6, lsr #1" + - + asm_text: "adc r4, r5, r6, lsr #0x1f" + - + asm_text: "adc r4, r5, r6, lsr #0x20" + - + asm_text: "adc r4, r5, r6, asr #1" + - + asm_text: "adc r4, r5, r6, asr #0x1f" + - + asm_text: "adc r4, r5, r6, asr #0x20" + - + asm_text: "adc r4, r5, r6, ror #1" + - + asm_text: "adc r4, r5, r6, ror #0x1f" + - + asm_text: "adc r6, r7, r8, lsl r9" + - + asm_text: "adc r6, r7, r8, lsr r9" + - + asm_text: "adc r6, r7, r8, asr r9" + - + asm_text: "adc r6, r7, r8, ror r9" + - + asm_text: "adc r4, r5, r6, rrx" + - + asm_text: "adc r5, r5, r6" + - + asm_text: "adc r4, r4, r5, lsl #1" + - + asm_text: "adc r4, r4, r5, lsl #0x1f" + - + asm_text: "adc r4, r4, r5, lsr #1" + - + asm_text: "adc r4, r4, r5, lsr #0x1f" + - + asm_text: "adc r4, r4, r5, lsr #0x20" + - + asm_text: "adc r4, r4, r5, asr #1" + - + asm_text: "adc r4, r4, r5, asr #0x1f" + - + asm_text: "adc r4, r4, r5, asr #0x20" + - + asm_text: "adc r4, r4, r5, ror #1" + - + asm_text: "adc r4, r4, r5, ror #0x1f" + - + asm_text: "adc r4, r4, r5, rrx" + - + asm_text: "adc r6, r6, r7, lsl r9" + - + asm_text: "adc r6, r6, r7, lsr r9" + - + asm_text: "adc r6, r6, r7, asr r9" + - + asm_text: "adc r6, r6, r7, ror r9" + - + asm_text: "adc r4, r4, r5, rrx" + - + asm_text: "add r2, pc, #3" + - + asm_text: "sub r2, pc, #3" + - + asm_text: "sub r1, pc, #0" + - + asm_text: "sub r1, pc, #301989888" + - + asm_text: "sub r1, pc, #-2147483647" + - + asm_text: "add r1, pc, #301989888" + - + asm_text: "add r1, pc, #-2147483647" + - + asm_text: "add r4, r5, #0xf000" + - + asm_text: "add r4, r5, #0xf000" + - + asm_text: "add r4, r5, #0xf000" + - + asm_text: "sub r4, r5, #0xf000" + - + asm_text: "add r7, r8, #0xff0000" + - + asm_text: "add r7, r8, #-0x7ffffff6" + - + asm_text: "add r7, r8, #-0x7ffffff6" + - + asm_text: "add r7, r8, #0x28, #2" + - + asm_text: "add r7, r8, #0x28, #2" + - + asm_text: "add r7, r8, #0x28, #2" + - + asm_text: "add r7, r8, #0x28, #2" + - + asm_text: "add r4, r5, r6" + - + asm_text: "add r4, r5, r6, lsl #5" + - + asm_text: "add r4, r5, r6, lsr #5" + - + asm_text: "add r4, r5, r6, lsr #5" + - + asm_text: "add r4, r5, r6, asr #5" + - + asm_text: "add r4, r5, r6, ror #5" + - + asm_text: "add r6, r7, r8, lsl r9" + - + asm_text: "add r4, r4, r3, lsl r9" + - + asm_text: "add r6, r7, r8, lsr r9" + - + asm_text: "add r6, r7, r8, asr r9" + - + asm_text: "add r6, r7, r8, ror r9" + - + asm_text: "add r4, r5, r6, rrx" + - + asm_text: "add r5, r5, #0xf000" + - + asm_text: "add r5, r5, #0xf000" + - + asm_text: "add r5, r5, #0xf000" + - + asm_text: "sub r5, r5, #0xf000" + - + asm_text: "add r7, r7, #0xff0000" + - + asm_text: "add r7, r7, #-0x7ffffff6" + - + asm_text: "add r7, r7, #-0x7ffffff6" + - + asm_text: "add r7, r7, #0x28, #2" + - + asm_text: "add r7, r7, #0x28, #2" + - + asm_text: "add r7, r7, #0x28, #2" + - + asm_text: "add r7, r7, #0x28, #2" + - + asm_text: "add r4, r4, r5" + - + asm_text: "add r4, r4, r5, lsl #5" + - + asm_text: "add r4, r4, r5, lsr #5" + - + asm_text: "add r4, r4, r5, lsr #5" + - + asm_text: "add r4, r4, r5, asr #5" + - + asm_text: "add r4, r4, r5, ror #5" + - + asm_text: "add r6, r6, r7, lsl r9" + - + asm_text: "add r6, r6, r7, lsr r9" + - + asm_text: "add r6, r6, r7, asr r9" + - + asm_text: "add r6, r6, r7, ror r9" + - + asm_text: "add r4, r4, r5, rrx" + - + asm_text: "sub r0, r0, #4" + - + asm_text: "sub r4, r5, #0x15" + - + asm_text: "add r0, pc, #-1073741824" + - + asm_text: "addseq r0, pc, #-0x40000000" + - + asm_text: "add r3, r1, r2, lsr #0x20" + - + asm_text: "add r3, r1, r2, asr #0x20" + - + asm_text: "adds r7, r8, #0xff0000" + - + asm_text: "adds r7, r8, #0xff0000" + - + asm_text: "adds r7, r8, #0xff0000" + - + asm_text: "adds r7, r8, #0xff0000" + - + asm_text: "adds r7, r8, #-0x7ffffff6" + - + asm_text: "adds r7, r8, #-0x7ffffff6" + - + asm_text: "adds r7, r8, #0x28, #2" + - + asm_text: "adds r7, r8, #0x28, #2" + - + asm_text: "adds r7, r8, #0x28, #2" + - + asm_text: "adds r7, r8, #0x28, #2" + - + asm_text: "and r10, r1, #0xf" + - + asm_text: "and r10, r1, #0xf" + - + asm_text: "and r10, r1, #0xf" + - + asm_text: "bic r10, r1, #0xe" + - + asm_text: "and r7, r8, #0xff0000" + - + asm_text: "and r7, r8, #-0x7ffffff6" + - + asm_text: "and r7, r8, #-0x7ffffff6" + - + asm_text: "and r7, r8, #0x28, #2" + - + asm_text: "and r7, r8, #0x28, #2" + - + asm_text: "and r7, r8, #0x28, #2" + - + asm_text: "and r7, r8, #0x28, #2" + - + asm_text: "and r10, r1, r6" + - + asm_text: "and r10, r1, r6, lsl #0xa" + - + asm_text: "and r10, r1, r6, lsr #0xa" + - + asm_text: "and r10, r1, r6, lsr #0xa" + - + asm_text: "and r10, r1, r6, asr #0xa" + - + asm_text: "and r10, r1, r6, ror #0xa" + - + asm_text: "and r6, r7, r8, lsl r2" + - + asm_text: "and r6, r7, r8, lsr r2" + - + asm_text: "and r6, r7, r8, asr r2" + - + asm_text: "and r6, r7, r8, ror r2" + - + asm_text: "and r10, r1, r6, rrx" + - + asm_text: "bic r2, r3, #-0x80000000" + - + asm_text: "bic sp, sp, #-0x80000000" + - + asm_text: "bic pc, pc, #-0x80000000" + - + asm_text: "and r1, r1, #0xf" + - + asm_text: "and r1, r1, #0xf" + - + asm_text: "and r1, r1, #0xf" + - + asm_text: "bic r1, r1, #0xe" + - + asm_text: "and r7, r7, #0xff0000" + - + asm_text: "and r7, r7, #-0x7ffffff6" + - + asm_text: "and r7, r7, #-0x7ffffff6" + - + asm_text: "and r7, r7, #0x28, #2" + - + asm_text: "and r7, r7, #0x28, #2" + - + asm_text: "and r7, r7, #0x28, #2" + - + asm_text: "and r7, r7, #0x28, #2" + - + asm_text: "and r10, r10, r1" + - + asm_text: "and r10, r10, r1, lsl #0xa" + - + asm_text: "and r10, r10, r1, lsr #0xa" + - + asm_text: "and r10, r10, r1, lsr #0xa" + - + asm_text: "and r10, r10, r1, asr #0xa" + - + asm_text: "and r10, r10, r1, ror #0xa" + - + asm_text: "and r6, r6, r7, lsl r2" + - + asm_text: "and r6, r6, r7, lsr r2" + - + asm_text: "and r6, r6, r7, asr r2" + - + asm_text: "and r6, r6, r7, ror r2" + - + asm_text: "and r10, r10, r1, rrx" + - + asm_text: "and r3, r1, r2, lsr #0x20" + - + asm_text: "and r3, r1, r2, asr #0x20" + - + asm_text: "asr r2, r4, #0x20" + - + asm_text: "asr r2, r4, #2" + - + asm_text: "mov r2, r4" + - + asm_text: "asr r4, r4, #2" + - + asm_text: "bfc r5, #3, #0x11" + - + asm_text: "bfclo r5, #3, #0x11" + - + asm_text: "bfi r5, r2, #3, #0x11" + - + asm_text: "bfine r5, r2, #3, #0x11" + - + asm_text: "bic r10, r1, #0xf" + - + asm_text: "bic r10, r1, #0xf" + - + asm_text: "bic r10, r1, #0xf" + - + asm_text: "and r10, r1, #0xe" + - + asm_text: "bic r7, r8, #0xff0000" + - + asm_text: "bic r7, r8, #-0x7ffffff6" + - + asm_text: "bic r7, r8, #-0x7ffffff6" + - + asm_text: "bic r7, r8, #0x28, #2" + - + asm_text: "bic r7, r8, #0x28, #2" + - + asm_text: "bic r7, r8, #0x28, #2" + - + asm_text: "bic r10, r1, r6" + - + asm_text: "bic r10, r1, r6, lsl #0xa" + - + asm_text: "bic r10, r1, r6, lsr #0xa" + - + asm_text: "bic r10, r1, r6, lsr #0xa" + - + asm_text: "bic r10, r1, r6, asr #0xa" + - + asm_text: "bic r10, r1, r6, ror #0xa" + - + asm_text: "bic r6, r7, r8, lsl r2" + - + asm_text: "bic r6, r7, r8, lsr r2" + - + asm_text: "bic r6, r7, r8, asr r2" + - + asm_text: "bic r6, r7, r8, ror r2" + - + asm_text: "bic r10, r1, r6, rrx" + - + asm_text: "and r2, r3, #-0x80000000" + - + asm_text: "and sp, sp, #-0x80000000" + - + asm_text: "and pc, pc, #-0x80000000" + - + asm_text: "bic r1, r1, #0xf" + - + asm_text: "bic r1, r1, #0xf" + - + asm_text: "bic r1, r1, #0xf" + - + asm_text: "and r1, r1, #0xe" + - + asm_text: "bic r7, r7, #0xff0000" + - + asm_text: "bic r7, r7, #-0x7ffffff6" + - + asm_text: "bic r7, r7, #-0x7ffffff6" + - + asm_text: "bic r7, r7, #0x28, #2" + - + asm_text: "bic r7, r7, #0x28, #2" + - + asm_text: "bic r7, r7, #0x28, #2" + - + asm_text: "bic r7, r7, #0x28, #2" + - + asm_text: "bic r10, r10, r1" + - + asm_text: "bic r10, r10, r1, lsl #0xa" + - + asm_text: "bic r10, r10, r1, lsr #0xa" + - + asm_text: "bic r10, r10, r1, lsr #0xa" + - + asm_text: "bic r10, r10, r1, asr #0xa" + - + asm_text: "bic r10, r10, r1, ror #0xa" + - + asm_text: "bic r6, r6, r7, lsl r2" + - + asm_text: "bic r6, r6, r7, lsr r2" + - + asm_text: "bic r6, r6, r7, asr r2" + - + asm_text: "bic r6, r6, r7, ror r2" + - + asm_text: "bic r10, r10, r1, rrx" + - + asm_text: "bic r3, r1, r2, lsr #0x20" + - + asm_text: "bic r3, r1, r2, asr #0x20" + - + asm_text: "bkpt #0xa" + - + asm_text: "bkpt #0xffff" + - + asm_text: "blls #0x1b4ec9c" + - + asm_text: "blx #0x1eec280" + - + asm_text: "blx #0xf76140" + - + asm_text: "blx r2" + - + asm_text: "blxne r2" + - + asm_text: "bx r2" + - + asm_text: "bxne r2" + - + asm_text: "bxj r2" + - + asm_text: "bxjne r2" + - + asm_text: "cdp p7, #1, c1, c1, c1, #4" + - + asm_text: "cdp2 p7, #1, c1, c1, c1, #4" + - + asm_text: "cdp2 p12, #0, c6, c12, c0, #7" + - + asm_text: "cdpne p7, #1, c1, c1, c1, #4" + - + asm_text: "clrex" + - + asm_text: "clz r1, r2" + - + asm_text: "clzeq r1, r2" + - + asm_text: "cmn r1, #0xf" + - + asm_text: "cmn r1, #0xf" + - + asm_text: "cmn r1, #0xf" + - + asm_text: "cmp r1, #0xf" + - + asm_text: "cmn r7, #0xff0000" + - + asm_text: "cmn r7, #-0x7ffffff6" + - + asm_text: "cmn r7, #-0x7ffffff6" + - + asm_text: "cmn r7, #0x28, #2" + - + asm_text: "cmn r7, #0x28, #2" + - + asm_text: "cmn r7, #0x28, #2" + - + asm_text: "cmn r7, #0x28, #2" + - + asm_text: "cmn r1, r6" + - + asm_text: "cmn r1, r6, lsl #0xa" + - + asm_text: "cmn r1, r6, lsr #0xa" + - + asm_text: "cmn sp, r6, lsr #0xa" + - + asm_text: "cmn r1, r6, asr #0xa" + - + asm_text: "cmn r1, r6, ror #0xa" + - + asm_text: "cmn r7, r8, lsl r2" + - + asm_text: "cmn sp, r8, lsr r2" + - + asm_text: "cmn r7, r8, asr r2" + - + asm_text: "cmn r7, r8, ror r2" + - + asm_text: "cmn r1, r6, rrx" + - + asm_text: "cmp r1, #0xf" + - + asm_text: "cmp r1, #0xf" + - + asm_text: "cmp r1, #0xf" + - + asm_text: "cmn r1, #0xf" + - + asm_text: "cmp r7, #0xff0000" + - + asm_text: "cmp r7, #-0x7ffffff6" + - + asm_text: "cmp r7, #-0x7ffffff6" + - + asm_text: "cmp r7, #0x28, #2" + - + asm_text: "cmp r7, #0x28, #2" + - + asm_text: "cmp r7, #0x28, #2" + - + asm_text: "cmp r7, #0x28, #2" + - + asm_text: "cmp r1, r6" + - + asm_text: "cmp r1, r6, lsl #0xa" + - + asm_text: "cmp r1, r6, lsr #0xa" + - + asm_text: "cmp sp, r6, lsr #0xa" + - + asm_text: "cmp r1, r6, asr #0xa" + - + asm_text: "cmp r1, r6, ror #0xa" + - + asm_text: "cmp r7, r8, lsl r2" + - + asm_text: "cmp sp, r8, lsr r2" + - + asm_text: "cmp r7, r8, asr r2" + - + asm_text: "cmp r7, r8, ror r2" + - + asm_text: "cmp r1, r6, rrx" + - + asm_text: "cmn r0, #2" + - + asm_text: "cmp lr, #0" + - + asm_text: "cpsie aif" + - + asm_text: "cpsie aif" + - + asm_text: "cps #0xf" + - + asm_text: "cpsid if, #0xa" + - + asm_text: "dbg #0" + - + asm_text: "dbg #5" + - + asm_text: "dbg #0xf" + - + asm_text: "dmb sy" + - + asm_text: "dmb st" + - + asm_text: "dmb #0xd" + - + asm_text: "dmb #0xc" + - + asm_text: "dmb ish" + - + asm_text: "dmb ishst" + - + asm_text: "dmb #0x9" + - + asm_text: "dmb #0x8" + - + asm_text: "dmb nsh" + - + asm_text: "dmb nshst" + - + asm_text: "dmb #0x5" + - + asm_text: "dmb #0x4" + - + asm_text: "dmb osh" + - + asm_text: "dmb oshst" + - + asm_text: "dmb #0x1" + - + asm_text: "dmb #0x0" + - + asm_text: "dmb sy" + - + asm_text: "dmb st" + - + asm_text: "dmb ish" + - + asm_text: "dmb ish" + - + asm_text: "dmb ishst" + - + asm_text: "dmb ishst" + - + asm_text: "dmb nsh" + - + asm_text: "dmb nsh" + - + asm_text: "dmb nshst" + - + asm_text: "dmb nshst" + - + asm_text: "dmb osh" + - + asm_text: "dmb oshst" + - + asm_text: "dmb sy" + - + asm_text: "dsb sy" + - + asm_text: "dsb st" + - + asm_text: "dsb #0xd" + - + asm_text: "dsb #0xc" + - + asm_text: "dsb ish" + - + asm_text: "dsb ishst" + - + asm_text: "dsb #0x9" + - + asm_text: "dsb #0x8" + - + asm_text: "dsb nsh" + - + asm_text: "dsb nshst" + - + asm_text: "dsb #0x5" + - + asm_text: "pssbb" + - + asm_text: "dsb osh" + - + asm_text: "dsb oshst" + - + asm_text: "dsb #0x1" + - + asm_text: "ssbb" + - + asm_text: "dsb #0x8" + - + asm_text: "dsb nsh" + - + asm_text: "dsb sy" + - + asm_text: "dsb st" + - + asm_text: "dsb ish" + - + asm_text: "dsb ish" + - + asm_text: "dsb ishst" + - + asm_text: "dsb ishst" + - + asm_text: "dsb nsh" + - + asm_text: "dsb nsh" + - + asm_text: "dsb nshst" + - + asm_text: "dsb nshst" + - + asm_text: "dsb osh" + - + asm_text: "dsb oshst" + - + asm_text: "dsb sy" + - + asm_text: "dsb sy" + - + asm_text: "dsb oshst" + - + asm_text: "eor r4, r5, #0xf000" + - + asm_text: "eor r4, r5, #0xf000" + - + asm_text: "eor r4, r5, #0xf000" + - + asm_text: "eor r7, r8, #0xff0000" + - + asm_text: "eor r7, r8, #-0x7ffffff6" + - + asm_text: "eor r7, r8, #-0x7ffffff6" + - + asm_text: "eor r7, r8, #0x28, #2" + - + asm_text: "eor r7, r8, #0x28, #2" + - + asm_text: "eor r7, r8, #0x28, #2" + - + asm_text: "eor r7, r8, #0x28, #2" + - + asm_text: "eor r4, r5, r6" + - + asm_text: "eor r4, r5, r6, lsl #5" + - + asm_text: "eor r4, r5, r6, lsr #5" + - + asm_text: "eor r4, r5, r6, lsr #5" + - + asm_text: "eor r4, r5, r6, asr #5" + - + asm_text: "eor r4, r5, r6, ror #5" + - + asm_text: "eor r6, r7, r8, lsl r9" + - + asm_text: "eor r6, r7, r8, lsr r9" + - + asm_text: "eor r6, r7, r8, asr r9" + - + asm_text: "eor r6, r7, r8, ror r9" + - + asm_text: "eor r4, r5, r6, rrx" + - + asm_text: "eor r5, r5, #0xf000" + - + asm_text: "eor r5, r5, #0xf000" + - + asm_text: "eor r5, r5, #0xf000" + - + asm_text: "eor r7, r7, #0xff0000" + - + asm_text: "eor r7, r7, #-0x7ffffff6" + - + asm_text: "eor r7, r7, #-0x7ffffff6" + - + asm_text: "eor r7, r7, #0x28, #2" + - + asm_text: "eor r7, r7, #0x28, #2" + - + asm_text: "eor r7, r7, #0x28, #2" + - + asm_text: "eor r7, r7, #0x28, #2" + - + asm_text: "eor r4, r4, r5" + - + asm_text: "eor r4, r4, r5, lsl #5" + - + asm_text: "eor r4, r4, r5, lsr #5" + - + asm_text: "eor r4, r4, r5, lsr #5" + - + asm_text: "eor r4, r4, r5, asr #5" + - + asm_text: "eor r4, r4, r5, ror #5" + - + asm_text: "eor r6, r6, r7, lsl r9" + - + asm_text: "eor r6, r6, r7, lsr r9" + - + asm_text: "eor r6, r6, r7, asr r9" + - + asm_text: "eor r6, r6, r7, ror r9" + - + asm_text: "eor r4, r4, r5, rrx" + - + asm_text: "eor r3, r1, r2, lsr #0x20" + - + asm_text: "eor r3, r1, r2, asr #0x20" + - + asm_text: "isb sy" + - + asm_text: "isb sy" + - + asm_text: "isb sy" + - + asm_text: "isb #0x1" + - + asm_text: "ldc2 p0, c8, [r1, #4]" + - + asm_text: "ldc2 p1, c7, [r2]" + - + asm_text: "ldc2 p2, c6, [r3, #-0xe0]" + - + asm_text: "ldc2 p3, c5, [r4, #-0x78]!" + - + asm_text: "ldc2 p4, c4, [r5], #0x10" + - + asm_text: "ldc2 p5, c3, [r6], #-0x48" + - + asm_text: "ldc2l p6, c2, [r7, #4]" + - + asm_text: "ldc2l p7, c1, [r8]" + - + asm_text: "ldc2l p8, c0, [r9, #-0xe0]" + - + asm_text: "ldc2l p9, c1, [r10, #-0x78]!" + - + asm_text: "ldc2l p0, c2, [r11], #0x10" + - + asm_text: "ldc2l p1, c3, [r12], #-0x48" + - + asm_text: "ldc p12, c4, [r0, #4]" + - + asm_text: "ldc p13, c5, [r1]" + - + asm_text: "ldc p14, c6, [r2, #-0xe0]" + - + asm_text: "ldc p15, c7, [r3, #-0x78]!" + - + asm_text: "ldc p5, c8, [r4], #0x10" + - + asm_text: "ldc p4, c9, [r5], #-0x48" + - + asm_text: "ldcl p3, c10, [r6, #4]" + - + asm_text: "ldcl p2, c11, [r7]" + - + asm_text: "ldcl p1, c12, [r8, #-0xe0]" + - + asm_text: "ldcl p0, c13, [r9, #-0x78]!" + - + asm_text: "ldcl p6, c14, [r10], #0x10" + - + asm_text: "ldcl p7, c15, [r11], #-0x48" + - + asm_text: "ldclo p12, c4, [r0, #4]" + - + asm_text: "ldchi p13, c5, [r1]" + - + asm_text: "ldchs p14, c6, [r2, #-0xe0]" + - + asm_text: "ldclo p15, c7, [r3, #-0x78]!" + - + asm_text: "ldceq p5, c8, [r4], #0x10" + - + asm_text: "ldcgt p4, c9, [r5], #-0x48" + - + asm_text: "ldcllt p3, c10, [r6, #4]" + - + asm_text: "ldclge p2, c11, [r7]" + - + asm_text: "ldclle p1, c12, [r8, #-0xe0]" + - + asm_text: "ldclne p0, c13, [r9, #-0x78]!" + - + asm_text: "ldcleq p6, c14, [r10], #0x10" + - + asm_text: "ldclhi p7, c15, [r11], #-0x48" + - + asm_text: "ldc2 p2, c8, [r1], {25}" + - + asm_text: "ldm r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldm r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldmib r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldmda r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldmdb r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldm r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldm r2!, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldmib r2!, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldmda r2!, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldmdb r2!, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldm r0, {r0, r2, lr} ^" + - + asm_text: "ldm sp!, {r0, r1, r2, r3, pc} ^" + - + asm_text: "ldrexb r3, [r4]" + - + asm_text: "ldrexh r2, [r5]" + - + asm_text: "ldrex r1, [r7]" + - + asm_text: "ldrexd r6, r7, [r8]" + - + asm_text: "ldrhthi r8, [r11], #-0" + - + asm_text: "ldrhthi r8, [r11], #0" + - + asm_text: "lsl r2, r4, #0x1f" + - + asm_text: "lsl r2, r4, #1" + - + asm_text: "mov r2, r4" + - + asm_text: "lsl r4, r4, #1" + - + asm_text: "lsr r2, r4, #0x20" + - + asm_text: "lsr r2, r4, #2" + - + asm_text: "mov r2, r4" + - + asm_text: "lsr r4, r4, #2" + - + asm_text: "mcr p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr2 p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr2 p7, #1, r5, c1, c1, #4" + - + asm_text: "mcrls p7, #1, r5, c1, c1, #4" + - + asm_text: "mcrls p7, #1, r5, c1, c1, #4" + - + asm_text: "mcrr p7, #0xf, r5, r4, c1" + - + asm_text: "mcrr2 p7, #0xf, r5, r4, c1" + - + asm_text: "mcrr p7, #0xf, r5, r4, c1" + - + asm_text: "mcrr2 p7, #0xf, r5, r4, c1" + - + asm_text: "mcrrgt p7, #0xf, r5, r4, c1" + - + asm_text: "mcrrgt p7, #0xf, r5, r4, c1" + - + asm_text: "mla r1, r2, r3, r4" + - + asm_text: "mlas r1, r2, r3, r4" + - + asm_text: "mlane r1, r2, r3, r4" + - + asm_text: "mlasne r1, r2, r3, r4" + - + asm_text: "mls r2, r5, r6, r3" + - + asm_text: "mlsne r2, r5, r6, r3" + - + asm_text: "mov r3, #7" + - + asm_text: "mov r3, #7" + - + asm_text: "mov r3, #7" + - + asm_text: "mvn r3, #6" + - + asm_text: "mov r4, #0xff0" + - + asm_text: "mov r5, #0xff0000" + - + asm_text: "mov r7, #0x2a" + - + asm_text: "mov r7, #0xa800000" + - + asm_text: "mov r7, #0xff0000" + - + asm_text: "mov r7, #-0x7ffffff6" + - + asm_text: "mov r7, #-0x7ffffff6" + - + asm_text: "mov pc, #0x8000000a" + - + asm_text: "mov r7, #0, #2" + - + asm_text: "mov r7, #0x28, #2" + - + asm_text: "mov r7, #0x28, #2" + - + asm_text: "mov r7, #0x28, #2" + - + asm_text: "mov r7, #0x28, #2" + - + asm_text: "mov r7, #0x2a, #0x1e" + - + asm_text: "movw r6, #0xffff" + - + asm_text: "movw r9, #0xffff" + - + asm_text: "movs r3, #7" + - + asm_text: "moveq r4, #0xff0" + - + asm_text: "movseq r5, #0xff0000" + - + asm_text: "mov r2, r3" + - + asm_text: "movs r2, r3" + - + asm_text: "moveq r2, r3" + - + asm_text: "movseq r2, r3" + - + asm_text: "mov r12, r8" + - + asm_text: "mov r2, r3" + - + asm_text: "mov r12, r8" + - + asm_text: "mov r2, r3" + - + asm_text: "mov r12, r8" + - + asm_text: "mov r2, r3" + - + asm_text: "mov r12, r8" + - + asm_text: "mov r2, r3" + - + asm_text: "movt r3, #7" + - + asm_text: "movt r6, #0xffff" + - + asm_text: "movteq r4, #0xff0" + - + asm_text: "mrc p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc p15, #7, apsr_nzcv, c15, c6, #6" + - + asm_text: "mrc2 p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc2 p9, #7, apsr_nzcv, c15, c0, #1" + - + asm_text: "mrc p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc p15, #7, apsr_nzcv, c15, c6, #6" + - + asm_text: "mrc2 p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc2 p9, #7, apsr_nzcv, c15, c0, #1" + - + asm_text: "mrceq p15, #7, apsr_nzcv, c15, c6, #6" + - + asm_text: "mrceq p15, #7, apsr_nzcv, c15, c6, #6" + - + asm_text: "mrrc p7, #1, r5, r4, c1" + - + asm_text: "mrrc2 p7, #1, r5, r4, c1" + - + asm_text: "mrrc p7, #1, r5, r4, c1" + - + asm_text: "mrrc2 p7, #1, r5, r4, c1" + - + asm_text: "mrrclo p7, #1, r5, r4, c1" + - + asm_text: "mrrclo p7, #1, r5, r4, c1" + - + asm_text: "mrs r8, apsr" + - + asm_text: "mrs r8, apsr" + - + asm_text: "mrs r8, spsr" + - + asm_text: "msr apsr_nzcvq, #5" + - + asm_text: "msr apsr_nzcvq, #5" + - + asm_text: "msr apsr_nzcvq, #5" + - + asm_text: "msr apsr_g, #5" + - + asm_text: "msr apsr_nzcvq, #5" + - + asm_text: "msr apsr_nzcvq, #5" + - + asm_text: "msr apsr_nzcvqg, #5" + - + asm_text: "msr cpsr_fc, #5" + - + asm_text: "msr cpsr_c, #5" + - + asm_text: "msr cpsr_x, #5" + - + asm_text: "msr cpsr_fc, #5" + - + asm_text: "msr cpsr_fc, #5" + - + asm_text: "msr cpsr_fsx, #5" + - + asm_text: "msr spsr_fc, #5" + - + asm_text: "msr spsr_fsxc, #5" + - + asm_text: "msr cpsr_fsxc, #5" + - + asm_text: "msr apsr_nzcvqg, #0xff0000" + - + asm_text: "msr apsr_nzcvq, #0x8000000a" + - + asm_text: "msr apsr_nzcvqg, #0x8000000a" + - + asm_text: "msr spsr_fsxc, #0x28, #2" + - + asm_text: "msr spsr_fsxc, #0x28, #2" + - + asm_text: "msr spsr_fsxc, #0x28, #2" + - + asm_text: "msr spsr_fsxc, #0x28, #2" + - + asm_text: "msr apsr_nzcvq, r0" + - + asm_text: "msr apsr_g, r0" + - + asm_text: "msr apsr_nzcvq, r0" + - + asm_text: "msr apsr_nzcvq, r0" + - + asm_text: "msr apsr_nzcvqg, r0" + - + asm_text: "msr cpsr_fc, r0" + - + asm_text: "msr cpsr_c, r0" + - + asm_text: "msr cpsr_x, r0" + - + asm_text: "msr cpsr_fc, r0" + - + asm_text: "msr cpsr_fc, r0" + - + asm_text: "msr cpsr_fsx, r0" + - + asm_text: "msr spsr_fc, r0" + - + asm_text: "msr spsr_fsxc, r0" + - + asm_text: "msr cpsr_fsxc, r0" + - + asm_text: "mul r5, r6, r7" + - + asm_text: "muls r5, r6, r7" + - + asm_text: "mulgt r5, r6, r7" + - + asm_text: "mulsle r5, r6, r7" + - + asm_text: "mvn r3, #7" + - + asm_text: "mvn r3, #7" + - + asm_text: "mvn r3, #7" + - + asm_text: "mov r3, #6" + - + asm_text: "mvn r7, #0xff" + - + asm_text: "mvn r4, #0xff0" + - + asm_text: "mvn r5, #0xff0000" + - + asm_text: "mvn r7, #0xff0000" + - + asm_text: "mvn r7, #-0x7ffffff6" + - + asm_text: "mvn r7, #-0x7ffffff6" + - + asm_text: "mvn r7, #0x28, #2" + - + asm_text: "mvn r7, #0x28, #2" + - + asm_text: "mvn r7, #0x28, #2" + - + asm_text: "mvn r7, #0x28, #2" + - + asm_text: "mvns r3, #7" + - + asm_text: "mvneq r4, #0xff0" + - + asm_text: "mvnseq r5, #0xff0000" + - + asm_text: "mvn r2, r3" + - + asm_text: "mvns r2, r3" + - + asm_text: "mvn r5, r6, lsl #0x13" + - + asm_text: "mvn r5, r6, lsr #0x9" + - + asm_text: "mvn r5, r6, asr #4" + - + asm_text: "mvn r5, r6, ror #6" + - + asm_text: "mvn r5, r6, rrx" + - + asm_text: "mvneq r2, r3" + - + asm_text: "mvnseq r2, r3, lsl #0xa" + - + asm_text: "mvn r5, r6, lsl r7" + - + asm_text: "mvns r5, r6, lsr r7" + - + asm_text: "mvngt r5, r6, asr r7" + - + asm_text: "mvnslt r5, r6, ror r7" + - + asm_text: "rsb r5, r8, #0" + - + asm_text: "nop" + - + asm_text: "nop" + - + asm_text: "nopgt" + - + asm_text: "orr r4, r5, #0xf000" + - + asm_text: "orr r4, r5, #0xf000" + - + asm_text: "orr r4, r5, #0xf000" + - + asm_text: "orr r7, r8, #0xff0000" + - + asm_text: "orr r7, r8, #-0x7ffffff6" + - + asm_text: "orr r7, r8, #-0x7ffffff6" + - + asm_text: "orr r7, r8, #0x28, #2" + - + asm_text: "orr r7, r8, #0x28, #2" + - + asm_text: "orr r7, r8, #0x28, #2" + - + asm_text: "orr r7, r8, #0x28, #2" + - + asm_text: "orr r4, r5, r6" + - + asm_text: "orr r4, r5, r6, lsl #5" + - + asm_text: "orr r4, r5, r6, lsr #5" + - + asm_text: "orr r4, r5, r6, lsr #5" + - + asm_text: "orr r4, r5, r6, asr #5" + - + asm_text: "orr r4, r5, r6, ror #5" + - + asm_text: "orr r6, r7, r8, lsl r9" + - + asm_text: "orr r6, r7, r8, lsr r9" + - + asm_text: "orr r6, r7, r8, asr r9" + - + asm_text: "orr r6, r7, r8, ror r9" + - + asm_text: "orr r4, r5, r6, rrx" + - + asm_text: "orr r5, r5, #0xf000" + - + asm_text: "orr r5, r5, #0xf000" + - + asm_text: "orr r5, r5, #0xf000" + - + asm_text: "orr r7, r7, #0xff0000" + - + asm_text: "orr r7, r7, #-0x7ffffff6" + - + asm_text: "orr r7, r7, #-0x7ffffff6" + - + asm_text: "orr r7, r7, #0x28, #2" + - + asm_text: "orr r7, r7, #0x28, #2" + - + asm_text: "orr r7, r7, #0x28, #2" + - + asm_text: "orr r7, r7, #0x28, #2" + - + asm_text: "orr r4, r4, r5" + - + asm_text: "orr r4, r4, r5, lsl #5" + - + asm_text: "orr r4, r4, r5, lsr #5" + - + asm_text: "orr r4, r4, r5, lsr #5" + - + asm_text: "orr r4, r4, r5, asr #5" + - + asm_text: "orr r4, r4, r5, ror #5" + - + asm_text: "orr r6, r6, r7, lsl r9" + - + asm_text: "orr r6, r6, r7, lsr r9" + - + asm_text: "orr r6, r6, r7, asr r9" + - + asm_text: "orr r6, r6, r7, ror r9" + - + asm_text: "orr r4, r4, r5, rrx" + - + asm_text: "orrseq r4, r5, #0xf000" + - + asm_text: "orrne r4, r5, r6" + - + asm_text: "orrseq r4, r5, r6, lsl #5" + - + asm_text: "orrlo r6, r7, r8, ror r9" + - + asm_text: "orrshi r4, r5, r6, rrx" + - + asm_text: "orrhs r5, r5, #0xf000" + - + asm_text: "orrseq r4, r4, r5" + - + asm_text: "orrne r6, r6, r7, asr r9" + - + asm_text: "orrslt r6, r6, r7, ror r9" + - + asm_text: "orrsgt r4, r4, r5, rrx" + - + asm_text: "orr r3, r1, r2, lsr #0x20" + - + asm_text: "orr r3, r1, r2, asr #0x20" + - + asm_text: "pkhbt r2, r2, r3" + - + asm_text: "pkhbt r2, r2, r3, lsl #0x1f" + - + asm_text: "pkhbt r2, r2, r3" + - + asm_text: "pkhbt r2, r2, r3, lsl #0xf" + - + asm_text: "pkhbt r2, r3, r2" + - + asm_text: "pkhtb r2, r2, r3, asr #0x1f" + - + asm_text: "pkhtb r2, r2, r3, asr #0xf" + - + asm_text: "pop {r7}" + - + asm_text: "pop {r7, r8, r9, r10}" + - + asm_text: "str r7, [sp, #-0x4]!" + - + asm_text: "push {r7, r8, r9, r10}" + - + asm_text: "qadd r1, r2, r3" + - + asm_text: "qaddne r1, r2, r3" + - + asm_text: "qadd16 r1, r2, r3" + - + asm_text: "qadd16gt r1, r2, r3" + - + asm_text: "qadd8 r1, r2, r3" + - + asm_text: "qadd8le r1, r2, r3" + - + asm_text: "qdadd r6, r7, r8" + - + asm_text: "qdaddhi r6, r7, r8" + - + asm_text: "qdsub r6, r7, r8" + - + asm_text: "qdsubhi r6, r7, r8" + - + asm_text: "qsax r9, r12, r0" + - + asm_text: "qsaxeq r9, r12, r0" + - + asm_text: "qsub r1, r2, r3" + - + asm_text: "qsubne r1, r2, r3" + - + asm_text: "qsub16 r1, r2, r3" + - + asm_text: "qsub16gt r1, r2, r3" + - + asm_text: "qsub8 r1, r2, r3" + - + asm_text: "qsub8le r1, r2, r3" + - + asm_text: "rbit r1, r2" + - + asm_text: "rbitne r1, r2" + - + asm_text: "rev r1, r9" + - + asm_text: "revne r1, r5" + - + asm_text: "rev16 r8, r3" + - + asm_text: "rev16ne r12, r4" + - + asm_text: "revsh r4, r9" + - + asm_text: "revshne r9, r1" + - + asm_text: "rfeda r2" + - + asm_text: "rfedb r3" + - + asm_text: "rfeia r5" + - + asm_text: "rfeib r6" + - + asm_text: "rfeda r4!" + - + asm_text: "rfedb r7!" + - + asm_text: "rfeia r9!" + - + asm_text: "rfeib r8!" + - + asm_text: "rfeda r2" + - + asm_text: "rfedb r3" + - + asm_text: "rfeia r5" + - + asm_text: "rfeib r6" + - + asm_text: "rfeda r4!" + - + asm_text: "rfedb r7!" + - + asm_text: "rfeia r9!" + - + asm_text: "rfeib r8!" + - + asm_text: "rfeia r1" + - + asm_text: "rfeia r1!" + - + asm_text: "ror r2, r4, #0x1f" + - + asm_text: "ror r2, r4, #1" + - + asm_text: "mov r2, r4" + - + asm_text: "ror r4, r4, #1" + - + asm_text: "rsb r4, r5, #0xf000" + - + asm_text: "rsb r4, r5, #0xf000" + - + asm_text: "rsb r4, r5, #0xf000" + - + asm_text: "rsb r7, r8, #0xff0000" + - + asm_text: "rsb r7, r8, #-0x7ffffff6" + - + asm_text: "rsb r7, r8, #-0x7ffffff6" + - + asm_text: "rsb r7, r8, #0x28, #2" + - + asm_text: "rsb r7, r8, #0x28, #2" + - + asm_text: "rsb r7, r8, #0x28, #2" + - + asm_text: "rsb r7, r8, #0x28, #2" + - + asm_text: "rsb r4, r5, r6" + - + asm_text: "rsb r4, r5, r6, lsl #5" + - + asm_text: "rsblo r4, r5, r6, lsr #5" + - + asm_text: "rsb r4, r5, r6, lsr #5" + - + asm_text: "rsb r4, r5, r6, asr #5" + - + asm_text: "rsb r4, r5, r6, ror #5" + - + asm_text: "rsb r6, r7, r8, lsl r9" + - + asm_text: "rsb r6, r7, r8, lsr r9" + - + asm_text: "rsb r6, r7, r8, asr r9" + - + asm_text: "rsble r6, r7, r8, ror r9" + - + asm_text: "rsb r4, r5, r6, rrx" + - + asm_text: "rsb r5, r5, #0xf000" + - + asm_text: "rsb r5, r5, #0xf000" + - + asm_text: "rsb r5, r5, #0xf000" + - + asm_text: "rsb r7, r7, #0xff0000" + - + asm_text: "rsb r7, r7, #-0x7ffffff6" + - + asm_text: "rsb r7, r7, #-0x7ffffff6" + - + asm_text: "rsb r7, r7, #0x28, #2" + - + asm_text: "rsb r7, r7, #0x28, #2" + - + asm_text: "rsb r7, r7, #0x28, #2" + - + asm_text: "rsb r7, r7, #0x28, #2" + - + asm_text: "rsb r4, r4, r5" + - + asm_text: "rsb r4, r4, r5, lsl #5" + - + asm_text: "rsb r4, r4, r5, lsr #5" + - + asm_text: "rsbne r4, r4, r5, lsr #5" + - + asm_text: "rsb r4, r4, r5, asr #5" + - + asm_text: "rsb r4, r4, r5, ror #5" + - + asm_text: "rsbgt r6, r6, r7, lsl r9" + - + asm_text: "rsb r6, r6, r7, lsr r9" + - + asm_text: "rsb r6, r6, r7, asr r9" + - + asm_text: "rsb r6, r6, r7, ror r9" + - + asm_text: "rsb r4, r4, r5, rrx" + - + asm_text: "rsbs r7, r7, #0xff0000" + - + asm_text: "rsbs r7, r7, #0xff0000" + - + asm_text: "rsbs r7, r7, #0xff0000" + - + asm_text: "rsbs r7, r7, #0xff0000" + - + asm_text: "rsbs r7, r8, #-0x7ffffff6" + - + asm_text: "rsbs r7, r8, #-0x7ffffff6" + - + asm_text: "rsbs r7, r8, #0x28, #2" + - + asm_text: "rsbs r7, r8, #0x28, #2" + - + asm_text: "rsbs r7, r8, #0x28, #2" + - + asm_text: "rsbs r7, r8, #0x28, #2" + - + asm_text: "rsc r4, r5, #0xf000" + - + asm_text: "rsc r4, r5, #0xf000" + - + asm_text: "rsc r4, r5, #0xf000" + - + asm_text: "rsc r7, r8, #0xff0000" + - + asm_text: "rsc r7, r8, #-0x7ffffff6" + - + asm_text: "rsc r7, r8, #-0x7ffffff6" + - + asm_text: "rsc r7, r8, #0x28, #2" + - + asm_text: "rsc r7, r8, #0x28, #2" + - + asm_text: "rsc r7, r8, #0x28, #2" + - + asm_text: "rsc r7, r8, #0x28, #2" + - + asm_text: "rsc r4, r5, r6" + - + asm_text: "rsc r4, r5, r6, lsl #5" + - + asm_text: "rsclo r4, r5, r6, lsr #5" + - + asm_text: "rsc r4, r5, r6, lsr #5" + - + asm_text: "rsc r4, r5, r6, asr #5" + - + asm_text: "rsc r4, r5, r6, ror #5" + - + asm_text: "rsc r6, r7, r8, lsl r9" + - + asm_text: "rsc r6, r7, r8, lsr r9" + - + asm_text: "rsc r6, r7, r8, asr r9" + - + asm_text: "rscle r6, r7, r8, ror r9" + - + asm_text: "rscs r1, r8, #0xfe0" + - + asm_text: "rsc r5, r5, #0xf000" + - + asm_text: "rsc r5, r5, #0xf000" + - + asm_text: "rsc r5, r5, #0xf000" + - + asm_text: "rsc r7, r7, #0xff0000" + - + asm_text: "rsc r7, r7, #-0x7ffffff6" + - + asm_text: "rsc r7, r7, #-0x7ffffff6" + - + asm_text: "rsc r7, r7, #0x28, #2" + - + asm_text: "rsc r7, r7, #0x28, #2" + - + asm_text: "rsc r7, r7, #0x28, #2" + - + asm_text: "rsc r7, r7, #0x28, #2" + - + asm_text: "rsc r4, r4, r5" + - + asm_text: "rsc r4, r4, r5, lsl #5" + - + asm_text: "rsc r4, r4, r5, lsr #5" + - + asm_text: "rscne r4, r4, r5, lsr #5" + - + asm_text: "rsc r4, r4, r5, asr #5" + - + asm_text: "rsc r4, r4, r5, ror #5" + - + asm_text: "rscgt r6, r6, r7, lsl r9" + - + asm_text: "rsc r6, r6, r7, lsr r9" + - + asm_text: "rsc r6, r6, r7, asr r9" + - + asm_text: "rsc r6, r6, r7, ror r9" + - + asm_text: "rrx r0, r1" + - + asm_text: "rrx sp, pc" + - + asm_text: "rrx pc, lr" + - + asm_text: "rrx lr, sp" + - + asm_text: "rrxs r0, r1" + - + asm_text: "rrxs sp, pc" + - + asm_text: "rrxs pc, lr" + - + asm_text: "rrxs lr, sp" + - + asm_text: "sadd16 r1, r2, r3" + - + asm_text: "sadd16gt r1, r2, r3" + - + asm_text: "sadd8 r1, r2, r3" + - + asm_text: "sadd8le r1, r2, r3" + - + asm_text: "sasx r9, r12, r0" + - + asm_text: "sasxeq r9, r12, r0" + - + asm_text: "sbc r4, r5, #0xf000" + - + asm_text: "sbc r4, r5, #0xf000" + - + asm_text: "sbc r4, r5, #0xf000" + - + asm_text: "sbc r7, r8, #0xff0000" + - + asm_text: "sbc r7, r8, #-0x7ffffff6" + - + asm_text: "sbc r7, r8, #-0x7ffffff6" + - + asm_text: "sbc r7, r8, #0x28, #2" + - + asm_text: "sbc r7, r8, #0x28, #2" + - + asm_text: "sbc r7, r8, #0x28, #2" + - + asm_text: "sbc r7, r8, #0x28, #2" + - + asm_text: "sbc r4, r5, r6" + - + asm_text: "sbc r4, r5, r6, lsl #5" + - + asm_text: "sbc r4, r5, r6, lsr #5" + - + asm_text: "sbc r4, r5, r6, lsr #5" + - + asm_text: "sbc r4, r5, r6, asr #5" + - + asm_text: "sbc r4, r5, r6, ror #5" + - + asm_text: "sbc r6, r7, r8, lsl r9" + - + asm_text: "sbc r6, r7, r8, lsr r9" + - + asm_text: "sbc r6, r7, r8, asr r9" + - + asm_text: "sbc r6, r7, r8, ror r9" + - + asm_text: "sbc r5, r5, #0xf000" + - + asm_text: "sbc r5, r5, #0xf000" + - + asm_text: "sbc r5, r5, #0xf000" + - + asm_text: "sbc r7, r7, #0xff0000" + - + asm_text: "sbc r7, r7, #-0x7ffffff6" + - + asm_text: "sbc r7, r7, #-0x7ffffff6" + - + asm_text: "sbc r7, r7, #0x28, #2" + - + asm_text: "sbc r7, r7, #0x28, #2" + - + asm_text: "sbc r7, r7, #0x28, #2" + - + asm_text: "sbc r7, r7, #0x28, #2" + - + asm_text: "sbc r4, r4, r5" + - + asm_text: "sbc r4, r4, r5, lsl #5" + - + asm_text: "sbc r4, r4, r5, lsr #5" + - + asm_text: "sbc r4, r4, r5, lsr #5" + - + asm_text: "sbc r4, r4, r5, asr #5" + - + asm_text: "sbc r4, r4, r5, ror #5" + - + asm_text: "sbc r6, r6, r7, lsl r9" + - + asm_text: "sbc r6, r6, r7, lsr r9" + - + asm_text: "sbc r6, r6, r7, asr r9" + - + asm_text: "sbc r6, r6, r7, ror r9" + - + asm_text: "sbfx r4, r5, #0x10, #1" + - + asm_text: "sbfxgt r4, r5, #0x10, #0x10" + - + asm_text: "sel r9, r2, r1" + - + asm_text: "selne r9, r2, r1" + - + asm_text: "setend be" + - + asm_text: "setend be" + - + asm_text: "setend le" + - + asm_text: "setend le" + - + asm_text: "sev" + - + asm_text: "seveq" + - + asm_text: "shadd16 r4, r8, r2" + - + asm_text: "shadd16gt r4, r8, r2" + - + asm_text: "shadd8 r4, r8, r2" + - + asm_text: "shadd8gt r4, r8, r2" + - + asm_text: "shasx r4, r8, r2" + - + asm_text: "shasxgt r4, r8, r2" + - + asm_text: "shsub16 r4, r8, r2" + - + asm_text: "shsub16gt r4, r8, r2" + - + asm_text: "shsub8 r4, r8, r2" + - + asm_text: "shsub8gt r4, r8, r2" + - + asm_text: "smlabb r3, r1, r9, r0" + - + asm_text: "smlabt r5, r6, r4, r1" + - + asm_text: "smlatb r4, r2, r3, r2" + - + asm_text: "smlatt r8, r3, r8, r4" + - + asm_text: "smlabbge r3, r1, r9, r0" + - + asm_text: "smlabtle r5, r6, r4, r1" + - + asm_text: "smlatbne r4, r2, r3, r2" + - + asm_text: "smlatteq r8, r3, r8, r4" + - + asm_text: "smlad r2, r3, r5, r8" + - + asm_text: "smladx r2, r3, r5, r8" + - + asm_text: "smladeq r2, r3, r5, r8" + - + asm_text: "smladxhi r2, r3, r5, r8" + - + asm_text: "smlal r2, r3, r5, r8" + - + asm_text: "smlals r2, r3, r5, r8" + - + asm_text: "smlaleq r2, r3, r5, r8" + - + asm_text: "smlalshi r2, r3, r5, r8" + - + asm_text: "smlalbb r3, r1, r9, r0" + - + asm_text: "smlalbt r5, r6, r4, r1" + - + asm_text: "smlaltb r4, r2, r3, r2" + - + asm_text: "smlaltt r8, r3, r8, r4" + - + asm_text: "smlalbbge r3, r1, r9, r0" + - + asm_text: "smlalbtle r5, r6, r4, r1" + - + asm_text: "smlaltbne r4, r2, r3, r2" + - + asm_text: "smlaltteq r8, r3, r8, r4" + - + asm_text: "smlald r2, r3, r5, r8" + - + asm_text: "smlaldx r2, r3, r5, r8" + - + asm_text: "smlaldeq r2, r3, r5, r8" + - + asm_text: "smlaldxhi r2, r3, r5, r8" + - + asm_text: "smlawb r2, r3, r10, r8" + - + asm_text: "smlawt r8, r3, r5, r9" + - + asm_text: "smlawbeq r2, r7, r5, r8" + - + asm_text: "smlawthi r1, r3, r0, r8" + - + asm_text: "smlsd r2, r3, r5, r8" + - + asm_text: "smlsdx r2, r3, r5, r8" + - + asm_text: "smlsdeq r2, r3, r5, r8" + - + asm_text: "smlsdxhi r2, r3, r5, r8" + - + asm_text: "smlsld r2, r9, r5, r1" + - + asm_text: "smlsldx r4, r11, r2, r8" + - + asm_text: "smlsldeq r8, r2, r5, r6" + - + asm_text: "smlsldxhi r1, r0, r3, r8" + - + asm_text: "smmla r1, r2, r3, r4" + - + asm_text: "smmlar r4, r3, r2, r1" + - + asm_text: "smmlalo r1, r2, r3, r4" + - + asm_text: "smmlarhs r4, r3, r2, r1" + - + asm_text: "smmls r1, r2, r3, r4" + - + asm_text: "smmlsr r4, r3, r2, r1" + - + asm_text: "smmlslo r1, r2, r3, r4" + - + asm_text: "smmlsrhs r4, r3, r2, r1" + - + asm_text: "smmul r2, r3, r4" + - + asm_text: "smmulr r3, r2, r1" + - + asm_text: "smmullo r2, r3, r4" + - + asm_text: "smmulrhs r3, r2, r1" + - + asm_text: "smuad r2, r3, r4" + - + asm_text: "smuadx r3, r2, r1" + - + asm_text: "smuadlt r2, r3, r4" + - + asm_text: "smuadxge r3, r2, r1" + - + asm_text: "smulbb r3, r9, r0" + - + asm_text: "smulbt r5, r4, r1" + - + asm_text: "smultb r4, r2, r2" + - + asm_text: "smultt r8, r3, r4" + - + asm_text: "smulbbge r1, r9, r0" + - + asm_text: "smulbtle r5, r6, r4" + - + asm_text: "smultbne r2, r3, r2" + - + asm_text: "smultteq r8, r3, r4" + - + asm_text: "smull r3, r9, r0, r1" + - + asm_text: "smulls r3, r9, r0, r2" + - + asm_text: "smulleq r8, r3, r4, r5" + - + asm_text: "smullseq r8, r3, r4, r3" + - + asm_text: "smulwb r3, r9, r0" + - + asm_text: "smulwt r3, r9, r2" + - + asm_text: "smusd r3, r0, r1" + - + asm_text: "smusdx r3, r9, r2" + - + asm_text: "smusdeq r8, r3, r2" + - + asm_text: "smusdxne r7, r4, r3" + - + asm_text: "srsda sp, #5" + - + asm_text: "srsdb sp, #1" + - + asm_text: "srsia sp, #0" + - + asm_text: "srsib sp, #0xf" + - + asm_text: "srsda sp!, #0x1f" + - + asm_text: "srsdb sp!, #0x13" + - + asm_text: "srsia sp!, #2" + - + asm_text: "srsib sp!, #0xe" + - + asm_text: "srsib sp, #0xb" + - + asm_text: "srsia sp, #0xa" + - + asm_text: "srsdb sp, #0x9" + - + asm_text: "srsda sp, #5" + - + asm_text: "srsib sp!, #5" + - + asm_text: "srsia sp!, #5" + - + asm_text: "srsdb sp!, #5" + - + asm_text: "srsda sp!, #5" + - + asm_text: "srsia sp, #5" + - + asm_text: "srsia sp!, #5" + - + asm_text: "srsda sp, #5" + - + asm_text: "srsdb sp, #1" + - + asm_text: "srsia sp, #0" + - + asm_text: "srsib sp, #0xf" + - + asm_text: "srsda sp!, #0x1f" + - + asm_text: "srsdb sp!, #0x13" + - + asm_text: "srsia sp!, #2" + - + asm_text: "srsib sp!, #0xe" + - + asm_text: "srsib sp, #0xb" + - + asm_text: "srsia sp, #0xa" + - + asm_text: "srsdb sp, #0x9" + - + asm_text: "srsda sp, #5" + - + asm_text: "srsib sp!, #5" + - + asm_text: "srsia sp!, #5" + - + asm_text: "srsdb sp!, #5" + - + asm_text: "srsda sp!, #5" + - + asm_text: "srsia sp, #5" + - + asm_text: "srsia sp!, #5" + - + asm_text: "ssat r8, #1, r10" + - + asm_text: "ssat r8, #1, r10" + - + asm_text: "ssat r8, #1, r10, lsl #0x1f" + - + asm_text: "ssat r8, #1, r10, asr #0x20" + - + asm_text: "ssat r8, #1, r10, asr #1" + - + asm_text: "ssat16 r2, #1, r7" + - + asm_text: "ssat16 r3, #0x10, r5" + - + asm_text: "ssax r2, r3, r4" + - + asm_text: "ssaxlt r2, r3, r4" + - + asm_text: "ssub16 r1, r0, r6" + - + asm_text: "ssub16ne r5, r3, r2" + - + asm_text: "ssub8 r9, r2, r4" + - + asm_text: "ssub8eq r5, r1, r2" + - + asm_text: "stc2 p0, c8, [r1, #4]" + - + asm_text: "stc2 p1, c7, [r2]" + - + asm_text: "stc2 p2, c6, [r3, #-0xe0]" + - + asm_text: "stc2 p3, c5, [r4, #-0x78]!" + - + asm_text: "stc2 p4, c4, [r5], #0x10" + - + asm_text: "stc2 p5, c3, [r6], #-0x48" + - + asm_text: "stc2l p6, c2, [r7, #4]" + - + asm_text: "stc2l p7, c1, [r8]" + - + asm_text: "stc2l p8, c0, [r9, #-0xe0]" + - + asm_text: "stc2l p9, c1, [r10, #-0x78]!" + - + asm_text: "stc2l p0, c2, [r11], #0x10" + - + asm_text: "stc2l p1, c3, [r12], #-0x48" + - + asm_text: "stc p12, c4, [r0, #4]" + - + asm_text: "stc p13, c5, [r1]" + - + asm_text: "stc p14, c6, [r2, #-0xe0]" + - + asm_text: "stc p15, c7, [r3, #-0x78]!" + - + asm_text: "stc p5, c8, [r4], #0x10" + - + asm_text: "stc p4, c9, [r5], #-0x48" + - + asm_text: "stcl p3, c10, [r6, #4]" + - + asm_text: "stcl p2, c11, [r7]" + - + asm_text: "stcl p1, c12, [r8, #-0xe0]" + - + asm_text: "stcl p0, c13, [r9, #-0x78]!" + - + asm_text: "stcl p6, c14, [r10], #0x10" + - + asm_text: "stcl p7, c15, [r11], #-0x48" + - + asm_text: "stclo p12, c4, [r0, #4]" + - + asm_text: "stchi p13, c5, [r1]" + - + asm_text: "stchs p14, c6, [r2, #-0xe0]" + - + asm_text: "stclo p15, c7, [r3, #-0x78]!" + - + asm_text: "stceq p5, c8, [r4], #0x10" + - + asm_text: "stcgt p4, c9, [r5], #-0x48" + - + asm_text: "stcllt p3, c10, [r6, #4]" + - + asm_text: "stclge p2, c11, [r7]" + - + asm_text: "stclle p1, c12, [r8, #-0xe0]" + - + asm_text: "stclne p0, c13, [r9, #-0x78]!" + - + asm_text: "stcleq p6, c14, [r10], #0x10" + - + asm_text: "stclhi p7, c15, [r11], #-0x48" + - + asm_text: "stc2 p2, c8, [r1], {25}" + - + asm_text: "stm r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "stm r3, {r1, r3, r4, r5, r6, lr}" + - + asm_text: "stmib r4, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "stmda r5, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "stmdb r6, {r1, r3, r4, r5, r6, r8}" + - + asm_text: "stmdb sp, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "stm r8!, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "stmib r9!, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "stmda sp!, {r1, r3, r4, r5, r6}" + - + asm_text: "stmdb r0!, {r1, r5, r7, sp}" + - + asm_text: "strexb r1, r3, [r4]" + - + asm_text: "strexh r4, r2, [r5]" + - + asm_text: "strex r2, r1, [r7]" + - + asm_text: "strexd r6, r2, r3, [r8]" + - + asm_text: "strpl r3, [r10, #-0]!" + - + asm_text: "strpl r3, [r10, #0]!" + - + asm_text: "sub r4, r5, #0xf000" + - + asm_text: "sub r4, r5, #0xf000" + - + asm_text: "sub r4, r5, #0xf000" + - + asm_text: "sub r7, r8, #0xff0000" + - + asm_text: "sub r7, r8, #-0x7ffffff6" + - + asm_text: "sub r7, r8, #-0x7ffffff6" + - + asm_text: "sub r7, r8, #0x28, #2" + - + asm_text: "sub r7, r8, #0x28, #2" + - + asm_text: "sub r7, r8, #0x28, #2" + - + asm_text: "sub r7, r8, #0x28, #2" + - + asm_text: "sub r4, r5, r6" + - + asm_text: "sub r4, r5, r6, lsl #5" + - + asm_text: "sub r4, r5, r6, lsr #5" + - + asm_text: "sub r4, r5, r6, lsr #5" + - + asm_text: "sub r4, r5, r6, asr #5" + - + asm_text: "sub r4, r5, r6, ror #5" + - + asm_text: "sub r6, r7, r8, lsl r9" + - + asm_text: "sub r6, r7, r8, lsr r9" + - + asm_text: "sub r6, r7, r8, asr r9" + - + asm_text: "sub r6, r7, r8, ror r9" + - + asm_text: "sub r5, r5, #0xf000" + - + asm_text: "sub r5, r5, #0xf000" + - + asm_text: "sub r5, r5, #0xf000" + - + asm_text: "sub r7, r7, #0xff0000" + - + asm_text: "sub r7, r7, #-0x7ffffff6" + - + asm_text: "sub r7, r7, #-0x7ffffff6" + - + asm_text: "sub r7, r7, #0x28, #2" + - + asm_text: "sub r7, r7, #0x28, #2" + - + asm_text: "sub r7, r7, #0x28, #2" + - + asm_text: "sub r4, r4, r5" + - + asm_text: "sub r4, r4, r5, lsl #5" + - + asm_text: "sub r4, r4, r5, lsr #5" + - + asm_text: "sub r4, r4, r5, lsr #5" + - + asm_text: "sub r4, r4, r5, asr #5" + - + asm_text: "sub r4, r4, r5, ror #5" + - + asm_text: "sub r6, r6, r7, lsl r9" + - + asm_text: "sub r6, r6, r7, lsr r9" + - + asm_text: "sub r6, r6, r7, asr r9" + - + asm_text: "sub r6, r6, r7, ror r9" + - + asm_text: "sub r3, r1, r2, lsr #0x20" + - + asm_text: "sub r3, r1, r2, asr #0x20" + - + asm_text: "subs r7, r8, #0xff0000" + - + asm_text: "subs r7, r8, #0xff0000" + - + asm_text: "subs r7, r8, #0xff0000" + - + asm_text: "subs r7, r8, #0xff0000" + - + asm_text: "subs r7, r8, #-0x7ffffff6" + - + asm_text: "subs r7, r8, #-0x7ffffff6" + - + asm_text: "subs r7, r8, #0x28, #2" + - + asm_text: "subs r7, r8, #0x28, #2" + - + asm_text: "subs r7, r8, #0x28, #2" + - + asm_text: "subs r7, r8, #0x28, #2" + - + asm_text: "svc #0x10" + - + asm_text: "svc #0" + - + asm_text: "svc #0xffffff" + - + asm_text: "swp r1, r2, [r3]" + - + asm_text: "swp r4, r4, [r6]" + - + asm_text: "swpb r5, r1, [r9]" + - + asm_text: "sxtab r2, r3, r4" + - + asm_text: "sxtab r4, r5, r6" + - + asm_text: "sxtablt r6, r2, r9, ror #8" + - + asm_text: "sxtab r5, r1, r4, ror #0x10" + - + asm_text: "sxtab r7, r8, r3, ror #0x18" + - + asm_text: "sxtab16ge r0, r1, r4" + - + asm_text: "sxtab16 r6, r2, r7" + - + asm_text: "sxtab16 r3, r5, r8, ror #8" + - + asm_text: "sxtab16 r3, r2, r1, ror #0x10" + - + asm_text: "sxtab16eq r1, r2, r3, ror #0x18" + - + asm_text: "sxtah r1, r3, r9" + - + asm_text: "sxtahhi r6, r1, r6" + - + asm_text: "sxtah r3, r8, r3, ror #8" + - + asm_text: "sxtahlo r2, r2, r4, ror #0x10" + - + asm_text: "sxtah r9, r3, r3, ror #0x18" + - + asm_text: "sxtbge r2, r4" + - + asm_text: "sxtb r5, r6" + - + asm_text: "sxtb r6, r9, ror #8" + - + asm_text: "sxtblo r5, r1, ror #0x10" + - + asm_text: "sxtb r8, r3, ror #0x18" + - + asm_text: "sxtb16 r1, r4" + - + asm_text: "sxtb16 r6, r7" + - + asm_text: "sxtb16hs r3, r5, ror #8" + - + asm_text: "sxtb16 r3, r1, ror #0x10" + - + asm_text: "sxtb16ge r2, r3, ror #0x18" + - + asm_text: "sxthne r3, r9" + - + asm_text: "sxth r1, r6" + - + asm_text: "sxth r3, r8, ror #8" + - + asm_text: "sxthle r2, r2, ror #0x10" + - + asm_text: "sxth r9, r3, ror #0x18" + - + asm_text: "teq r5, #0xf000" + - + asm_text: "teq r5, #0xf000" + - + asm_text: "teq r5, #0xf000" + - + asm_text: "teq r7, #0xff0000" + - + asm_text: "teq r7, #-0x7ffffff6" + - + asm_text: "teq r7, #-0x7ffffff6" + - + asm_text: "teq r7, #0x28, #2" + - + asm_text: "teq r7, #0x28, #2" + - + asm_text: "teq r7, #0x28, #2" + - + asm_text: "teq r7, #0x28, #2" + - + asm_text: "teq r4, r5" + - + asm_text: "teq r4, r5, lsl #5" + - + asm_text: "teq r4, r5, lsr #5" + - + asm_text: "teq r4, r5, lsr #5" + - + asm_text: "teq r4, r5, asr #5" + - + asm_text: "teq r4, r5, ror #5" + - + asm_text: "teq r6, r7, lsl r9" + - + asm_text: "teq r6, r7, lsr r9" + - + asm_text: "teq r6, r7, asr r9" + - + asm_text: "teq r6, r7, ror r9" + - + asm_text: "tst r5, #0xf000" + - + asm_text: "tst r5, #0xf000" + - + asm_text: "tst r5, #0xf000" + - + asm_text: "tst r7, #0xff0000" + - + asm_text: "tst r7, #-0x7ffffff6" + - + asm_text: "tst r7, #-0x7ffffff6" + - + asm_text: "tst r7, #0x28, #2" + - + asm_text: "tst r7, #0x28, #2" + - + asm_text: "tst r7, #0x28, #2" + - + asm_text: "tst r7, #0x28, #2" + - + asm_text: "tst r4, r5" + - + asm_text: "tst r4, r5, lsl #5" + - + asm_text: "tst r4, r5, lsr #5" + - + asm_text: "tst r4, r5, lsr #5" + - + asm_text: "tst r4, r5, asr #5" + - + asm_text: "tst r4, r5, ror #5" + - + asm_text: "tst r6, r7, lsl r9" + - + asm_text: "tst r6, r7, lsr r9" + - + asm_text: "tst r6, r7, asr r9" + - + asm_text: "tst r6, r7, ror r9" + - + asm_text: "uadd16 r1, r2, r3" + - + asm_text: "uadd16gt r1, r2, r3" + - + asm_text: "uadd8 r1, r2, r3" + - + asm_text: "uadd8le r1, r2, r3" + - + asm_text: "uasx r9, r12, r0" + - + asm_text: "uasxeq r9, r12, r0" + - + asm_text: "ubfx r4, r5, #0x10, #1" + - + asm_text: "ubfxgt r4, r5, #0x10, #0x10" + - + asm_text: "uhadd16 r4, r8, r2" + - + asm_text: "uhadd16gt r4, r8, r2" + - + asm_text: "uhadd8 r4, r8, r2" + - + asm_text: "uhadd8gt r4, r8, r2" + - + asm_text: "uhasx r4, r8, r2" + - + asm_text: "uhasxgt r4, r8, r2" + - + asm_text: "uhsub16 r4, r8, r2" + - + asm_text: "uhsub16gt r4, r8, r2" + - + asm_text: "uhsub8 r4, r8, r2" + - + asm_text: "uhsub8gt r4, r8, r2" + - + asm_text: "umaal r3, r4, r5, r6" + - + asm_text: "umaallt r3, r4, r5, r6" + - + asm_text: "umlal r2, r4, r6, r8" + - + asm_text: "umlalgt r6, r1, r2, r6" + - + asm_text: "umlals r2, r9, r2, r3" + - + asm_text: "umlalseq r3, r5, r1, r2" + - + asm_text: "umull r2, r4, r6, r8" + - + asm_text: "umullgt r6, r1, r2, r6" + - + asm_text: "umulls r2, r9, r2, r3" + - + asm_text: "umullseq r3, r5, r1, r2" + - + asm_text: "uqadd16 r1, r2, r3" + - + asm_text: "uqadd16gt r4, r7, r9" + - + asm_text: "uqadd8 r3, r4, r8" + - + asm_text: "uqadd8le r8, r1, r2" + - + asm_text: "uqasx r2, r4, r1" + - + asm_text: "uqasxhi r5, r2, r9" + - + asm_text: "uqsax r1, r3, r7" + - + asm_text: "uqsax r3, r6, r2" + - + asm_text: "uqsub16 r1, r5, r3" + - + asm_text: "uqsub16gt r3, r2, r5" + - + asm_text: "uqsub8 r2, r1, r4" + - + asm_text: "uqsub8le r4, r6, r9" + - + asm_text: "usad8 r2, r1, r4" + - + asm_text: "usad8le r4, r6, r9" + - + asm_text: "usada8 r1, r5, r3, r7" + - + asm_text: "usada8gt r3, r2, r5, r1" + - + asm_text: "usat r8, #1, r10" + - + asm_text: "usat r8, #4, r10" + - + asm_text: "usat r8, #5, r10, lsl #0x1f" + - + asm_text: "usat r8, #0x1f, r10, asr #0x20" + - + asm_text: "usat r8, #0x10, r10, asr #1" + - + asm_text: "usat16 r2, #2, r7" + - + asm_text: "usat16 r3, #0xf, r5" + - + asm_text: "usax r2, r3, r4" + - + asm_text: "usaxne r2, r3, r4" + - + asm_text: "usub16 r4, r2, r7" + - + asm_text: "usub16hi r1, r1, r3" + - + asm_text: "usub8 r1, r8, r5" + - + asm_text: "usub8le r9, r2, r3" + - + asm_text: "uxtab r2, r3, r4" + - + asm_text: "uxtab r4, r5, r6" + - + asm_text: "uxtablt r6, r2, r9, ror #8" + - + asm_text: "uxtab r5, r1, r4, ror #0x10" + - + asm_text: "uxtab r7, r8, r3, ror #0x18" + - + asm_text: "uxtab16ge r0, r1, r4" + - + asm_text: "uxtab16 r6, r2, r7" + - + asm_text: "uxtab16 r3, r5, r8, ror #8" + - + asm_text: "uxtab16 r3, r2, r1, ror #0x10" + - + asm_text: "uxtab16eq r1, r2, r3, ror #0x18" + - + asm_text: "uxtah r1, r3, r9" + - + asm_text: "uxtahhi r6, r1, r6" + - + asm_text: "uxtah r3, r8, r3, ror #8" + - + asm_text: "uxtahlo r2, r2, r4, ror #0x10" + - + asm_text: "uxtah r9, r3, r3, ror #0x18" + - + asm_text: "uxtbge r2, r4" + - + asm_text: "uxtb r5, r6" + - + asm_text: "uxtb r6, r9, ror #8" + - + asm_text: "uxtblo r5, r1, ror #0x10" + - + asm_text: "uxtb r8, r3, ror #0x18" + - + asm_text: "uxtb16 r1, r4" + - + asm_text: "uxtb16 r6, r7" + - + asm_text: "uxtb16hs r3, r5, ror #8" + - + asm_text: "uxtb16 r3, r1, ror #0x10" + - + asm_text: "uxtb16ge r2, r3, ror #0x18" + - + asm_text: "uxthne r3, r9" + - + asm_text: "uxth r1, r6" + - + asm_text: "uxth r3, r8, ror #8" + - + asm_text: "uxthle r2, r2, ror #0x10" + - + asm_text: "uxth r9, r3, ror #0x18" + - + asm_text: "wfe" + - + asm_text: "wfehi" + - + asm_text: "wfi" + - + asm_text: "wfilt" + - + asm_text: "yield" + - + asm_text: "yieldne" + - + asm_text: "sev" + - + asm_text: "wfi" + - + asm_text: "wfe" + - + asm_text: "yield" + - + asm_text: "nop" + - + asm_text: "hintgt #0xef" diff --git a/thirdparty/capstone/tests/MC/ARM/basic-thumb-instructions.s.yaml b/thirdparty/capstone/tests/MC/ARM/basic-thumb-instructions.s.yaml new file mode 100644 index 0000000..83e7b0f --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/basic-thumb-instructions.s.yaml @@ -0,0 +1,266 @@ +test_cases: + - + input: + bytes: [ 0x74, 0x41, 0xd1, 0x1c, 0x03, 0x32, 0x08, 0x32, 0xd1, 0x18, 0x42, 0x44, 0x01, 0xb0, 0x7f, 0xb0, 0x01, 0xb0, 0x02, 0xaa, 0xff, 0xaa, 0x82, 0xb0, 0x82, 0xb0, 0x9d, 0x44, 0x6a, 0x44, 0x00, 0xa5, 0x01, 0xa2, 0xff, 0xa3, 0x1a, 0x10, 0x5a, 0x11, 0x5a, 0x10, 0x6d, 0x15, 0x6d, 0x15, 0x6b, 0x15, 0x15, 0x41, 0x97, 0xe3, 0x2e, 0xe7, 0x80, 0xd0, 0x50, 0xd0, 0xd8, 0xf0, 0x20, 0xe8, 0xb0, 0xf1, 0x40, 0xe8, 0xb1, 0x43, 0x00, 0xbe, 0xff, 0xbe, 0xa0, 0x47, 0x10, 0x47, 0xcd, 0x42, 0x20, 0x2e, 0xa3, 0x42, 0x88, 0x45, 0x61, 0xb6, 0x74, 0xb6, 0x6c, 0x40, 0xff, 0xcb, 0xba, 0xca, 0x02, 0xc9, 0x29, 0x68, 0x32, 0x6a, 0xfb, 0x6f, 0x00, 0x99, 0x06, 0x9a, 0xff, 0x9b, 0x97, 0x4b, 0x5c, 0x4b, 0xd1, 0x58, 0x1c, 0x78, 0x35, 0x78, 0xfe, 0x7f, 0x66, 0x5d, 0x1b, 0x88, 0x74, 0x88, 0xfd, 0x8f, 0x96, 0x5b, 0x96, 0x57, 0x7b, 0x5e, 0x2c, 0x00, 0x2c, 0x01, 0x1b, 0x03, 0x1b, 0x03, 0x19, 0x03, 0xb2, 0x40, 0x59, 0x08, 0x19, 0x08, 0x24, 0x0d, 0x24, 0x0d, 0x22, 0x0d, 0xf2, 0x40, 0x00, 0x22, 0xff, 0x22, 0x17, 0x22, 0x23, 0x46, 0x19, 0x00, 0x51, 0x43, 0x5a, 0x43, 0x63, 0x43, 0xde, 0x43, 0x63, 0x42, 0x4c, 0xbc, 0x86, 0xb4, 0x1e, 0xba, 0x57, 0xba, 0xcd, 0xba, 0xfa, 0x41, 0x59, 0x42, 0x9c, 0x41, 0x58, 0xb6, 0x50, 0xb6, 0x44, 0xc1, 0x8e, 0xc1, 0x3a, 0x60, 0x3a, 0x60, 0x4d, 0x60, 0xfb, 0x67, 0x00, 0x92, 0x00, 0x93, 0x05, 0x94, 0xff, 0x95, 0xfa, 0x50, 0x1c, 0x70, 0x35, 0x70, 0xfe, 0x77, 0x66, 0x55, 0x1b, 0x80, 0x74, 0x80, 0xfd, 0x87, 0x96, 0x53, 0xd1, 0x1e, 0x03, 0x3a, 0x08, 0x3a, 0x83, 0xb0, 0xff, 0xb0, 0xd1, 0x1a, 0x00, 0xdf, 0xff, 0xdf, 0x6b, 0xb2, 0x2b, 0xb2, 0x0e, 0x42, 0xd7, 0xb2, 0xa1, 0xb2 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "adcs r4, r6" + - + asm_text: "adds r1, r2, #3" + - + asm_text: "adds r2, #3" + - + asm_text: "adds r2, #8" + - + asm_text: "adds r1, r2, r3" + - + asm_text: "add r2, r8" + - + asm_text: "add sp, #4" + - + asm_text: "add sp, #0x1fc" + - + asm_text: "add sp, #4" + - + asm_text: "add r2, sp, #8" + - + asm_text: "add r2, sp, #0x3fc" + - + asm_text: "sub sp, #8" + - + asm_text: "sub sp, #8" + - + asm_text: "add sp, r3" + - + asm_text: "add r2, sp, r2" + - + asm_text: "adr r5, #0" + - + asm_text: "adr r2, #4" + - + asm_text: "adr r3, #0x3fc" + - + asm_text: "asrs r2, r3, #0x20" + - + asm_text: "asrs r2, r3, #5" + - + asm_text: "asrs r2, r3, #1" + - + asm_text: "asrs r5, r5, #0x15" + - + asm_text: "asrs r5, r5, #0x15" + - + asm_text: "asrs r3, r5, #0x15" + - + asm_text: "asrs r5, r2" + - + asm_text: "b #0x72e" + - + asm_text: "b #-0x1a4" + - + asm_text: "beq #-0x100" + - + asm_text: "beq #0xa0" + - + asm_text: "blx #0xd8040" + - + asm_text: "blx #0x1b0080" + - + asm_text: "bics r1, r6" + - + asm_text: "bkpt #0" + - + asm_text: "bkpt #0xff" + - + asm_text: "blx r4" + - + asm_text: "bx r2" + - + asm_text: "cmn r5, r1" + - + asm_text: "cmp r6, #0x20" + - + asm_text: "cmp r3, r4" + - + asm_text: "cmp r8, r1" + - + asm_text: "cpsie f" + - + asm_text: "cpsid a" + - + asm_text: "eors r4, r5" + - + asm_text: "ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}" + - + asm_text: "ldm r2!, {r1, r3, r4, r5, r7}" + - + asm_text: "ldm r1, {r1}" + - + asm_text: "ldr r1, [r5]" + - + asm_text: "ldr r2, [r6, #0x20]" + - + asm_text: "ldr r3, [r7, #0x7c]" + - + asm_text: "ldr r1, [sp]" + - + asm_text: "ldr r2, [sp, #0x18]" + - + asm_text: "ldr r3, [sp, #0x3fc]" + - + asm_text: "ldr r3, [pc, #0x25c]" + - + asm_text: "ldr r3, [pc, #0x170]" + - + asm_text: "ldr r1, [r2, r3]" + - + asm_text: "ldrb r4, [r3]" + - + asm_text: "ldrb r5, [r6]" + - + asm_text: "ldrb r6, [r7, #0x1f]" + - + asm_text: "ldrb r6, [r4, r5]" + - + asm_text: "ldrh r3, [r3]" + - + asm_text: "ldrh r4, [r6, #2]" + - + asm_text: "ldrh r5, [r7, #0x3e]" + - + asm_text: "ldrh r6, [r2, r6]" + - + asm_text: "ldrsb r6, [r2, r6]" + - + asm_text: "ldrsh r3, [r7, r1]" + - + asm_text: "movs r4, r5" + - + asm_text: "lsls r4, r5, #4" + - + asm_text: "lsls r3, r3, #0xc" + - + asm_text: "lsls r3, r3, #0xc" + - + asm_text: "lsls r1, r3, #0xc" + - + asm_text: "lsls r2, r6" + - + asm_text: "lsrs r1, r3, #1" + - + asm_text: "lsrs r1, r3, #0x20" + - + asm_text: "lsrs r4, r4, #0x14" + - + asm_text: "lsrs r4, r4, #0x14" + - + asm_text: "lsrs r2, r4, #0x14" + - + asm_text: "lsrs r2, r6" + - + asm_text: "movs r2, #0" + - + asm_text: "movs r2, #0xff" + - + asm_text: "movs r2, #0x17" + - + asm_text: "mov r3, r4" + - + asm_text: "movs r1, r3" + - + asm_text: "muls r1, r2, r1" + - + asm_text: "muls r2, r3, r2" + - + asm_text: "muls r3, r4, r3" + - + asm_text: "mvns r6, r3" + - + asm_text: "rsbs r3, r4, #0" + - + asm_text: "pop {r2, r3, r6}" + - + asm_text: "push {r1, r2, r7}" + - + asm_text: "rev r6, r3" + - + asm_text: "rev16 r7, r2" + - + asm_text: "revsh r5, r1" + - + asm_text: "rors r2, r7" + - + asm_text: "rsbs r1, r3, #0" + - + asm_text: "sbcs r4, r3" + - + asm_text: "setend be" + - + asm_text: "setend le" + - + asm_text: "stm r1!, {r2, r6}" + - + asm_text: "stm r1!, {r1, r2, r3, r7}" + - + asm_text: "str r2, [r7]" + - + asm_text: "str r2, [r7]" + - + asm_text: "str r5, [r1, #4]" + - + asm_text: "str r3, [r7, #0x7c]" + - + asm_text: "str r2, [sp]" + - + asm_text: "str r3, [sp]" + - + asm_text: "str r4, [sp, #0x14]" + - + asm_text: "str r5, [sp, #0x3fc]" + - + asm_text: "str r2, [r7, r3]" + - + asm_text: "strb r4, [r3]" + - + asm_text: "strb r5, [r6]" + - + asm_text: "strb r6, [r7, #0x1f]" + - + asm_text: "strb r6, [r4, r5]" + - + asm_text: "strh r3, [r3]" + - + asm_text: "strh r4, [r6, #2]" + - + asm_text: "strh r5, [r7, #0x3e]" + - + asm_text: "strh r6, [r2, r6]" + - + asm_text: "subs r1, r2, #3" + - + asm_text: "subs r2, #3" + - + asm_text: "subs r2, #8" + - + asm_text: "sub sp, #0xc" + - + asm_text: "sub sp, #0x1fc" + - + asm_text: "subs r1, r2, r3" + - + asm_text: "svc #0" + - + asm_text: "svc #0xff" + - + asm_text: "sxtb r3, r5" + - + asm_text: "sxth r3, r5" + - + asm_text: "tst r6, r1" + - + asm_text: "uxtb r7, r2" + - + asm_text: "uxth r1, r4" diff --git a/thirdparty/capstone/tests/MC/ARM/basic-thumb2-instructions.s.yaml b/thirdparty/capstone/tests/MC/ARM/basic-thumb2-instructions.s.yaml new file mode 100644 index 0000000..634286b --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/basic-thumb2-instructions.s.yaml @@ -0,0 +1,2688 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xf1, 0x04, 0x00, 0x51, 0xf1, 0x00, 0x00, 0x42, 0xf1, 0xff, 0x01, 0x47, 0xf1, 0x55, 0x13, 0x4c, 0xf1, 0xaa, 0x28, 0x47, 0xf1, 0xa5, 0x39, 0x43, 0xf1, 0x07, 0x45, 0x42, 0xf1, 0xff, 0x44, 0x42, 0xf5, 0xd0, 0x64, 0x45, 0xeb, 0x06, 0x04, 0x55, 0xeb, 0x06, 0x04, 0x41, 0xeb, 0x03, 0x09, 0x51, 0xeb, 0x03, 0x09, 0x41, 0xeb, 0x33, 0x10, 0x51, 0xeb, 0xc3, 0x10, 0x41, 0xeb, 0xd3, 0x70, 0x51, 0xeb, 0x23, 0x00, 0x0a, 0xbf, 0x11, 0x1d, 0x03, 0xf2, 0xff, 0x35, 0x05, 0xf2, 0x25, 0x14, 0x0d, 0xf5, 0x80, 0x62, 0x08, 0xf5, 0x7f, 0x42, 0x03, 0xf2, 0x01, 0x12, 0x03, 0xf2, 0x01, 0x12, 0x06, 0xf5, 0x80, 0x7c, 0x06, 0xf2, 0x00, 0x1c, 0x12, 0xf5, 0xf8, 0x71, 0x02, 0xf1, 0x01, 0x02, 0x00, 0xf1, 0x20, 0x00, 0x38, 0x32, 0x38, 0x32, 0x07, 0xf1, 0xcb, 0x31, 0xb2, 0xf1, 0x10, 0x02, 0xb2, 0xf1, 0x10, 0x02, 0xa2, 0xf2, 0x10, 0x02, 0xa2, 0xf2, 0x10, 0x02, 0xa2, 0xf2, 0x10, 0x02, 0x02, 0xeb, 0x08, 0x01, 0x09, 0xeb, 0x22, 0x05, 0x13, 0xeb, 0xc1, 0x77, 0x13, 0xeb, 0x56, 0x60, 0x08, 0xeb, 0x31, 0x34, 0xc9, 0x19, 0x08, 0xbf, 0x59, 0x19, 0x08, 0xbf, 0x49, 0x19, 0x08, 0xbf, 0x13, 0xeb, 0x05, 0x01, 0x08, 0xbf, 0x11, 0xeb, 0x05, 0x01, 0xc2, 0x44, 0xc2, 0x44, 0x08, 0xbf, 0x51, 0x44, 0x08, 0xbf, 0x11, 0xeb, 0x0a, 0x01, 0x08, 0xbf, 0xff, 0xaf, 0x08, 0xbf, 0x7f, 0xb0, 0x0d, 0xf1, 0x0f, 0x07, 0x1d, 0xf1, 0x10, 0x07, 0x0d, 0xf1, 0x10, 0x08, 0x0d, 0xf2, 0xfc, 0x36, 0x0d, 0xf2, 0xfb, 0x36, 0x08, 0xbf, 0xe8, 0x44, 0x08, 0xbf, 0xcd, 0x44, 0x0d, 0xeb, 0x0c, 0x02, 0x08, 0xbf, 0x0d, 0xeb, 0x0c, 0x02, 0xaf, 0xf6, 0xc6, 0x4b, 0x0f, 0xf2, 0x03, 0x02, 0xaf, 0xf2, 0x3a, 0x3b, 0xaf, 0xf2, 0x00, 0x01, 0x05, 0xf4, 0x7f, 0x22, 0x1c, 0xf0, 0x0f, 0x03, 0x01, 0xf0, 0xff, 0x01, 0x01, 0xf0, 0xff, 0x01, 0x04, 0xf0, 0xff, 0x35, 0x19, 0xf0, 0xff, 0x31, 0x09, 0xea, 0x08, 0x04, 0x04, 0xea, 0xe8, 0x01, 0x11, 0xea, 0x47, 0x02, 0x15, 0xea, 0x12, 0x54, 0x0c, 0xea, 0x71, 0x49, 0x4f, 0xea, 0x23, 0x32, 0x5f, 0xea, 0x23, 0x08, 0x5f, 0xea, 0x63, 0x02, 0x4f, 0xea, 0x23, 0x12, 0x5f, 0xea, 0xec, 0x32, 0x4f, 0xea, 0xe3, 0x43, 0x5f, 0xea, 0xa8, 0x08, 0x5f, 0xea, 0x67, 0x17, 0x4f, 0xea, 0x6c, 0x5c, 0x51, 0x10, 0x04, 0xbf, 0x5f, 0xea, 0x62, 0x01, 0x51, 0x10, 0x44, 0xfa, 0x02, 0xf3, 0x41, 0xfa, 0x02, 0xf1, 0x54, 0xfa, 0x08, 0xf3, 0x08, 0xbf, 0x13, 0xf5, 0xce, 0xa9, 0x6f, 0xf3, 0xd3, 0x05, 0x38, 0xbf, 0x6f, 0xf3, 0xd3, 0x05, 0x62, 0xf3, 0xd3, 0x05, 0x18, 0xbf, 0x62, 0xf3, 0xd3, 0x05, 0x21, 0xf0, 0x0f, 0x0a, 0x22, 0xf0, 0xff, 0x35, 0x3a, 0xf0, 0xff, 0x3b, 0x23, 0xea, 0x06, 0x0c, 0x22, 0xea, 0x06, 0x3b, 0x24, 0xea, 0xd1, 0x28, 0x25, 0xea, 0xd7, 0x37, 0x27, 0xea, 0x29, 0x06, 0x26, 0xea, 0x78, 0x05, 0x21, 0xf0, 0x0f, 0x01, 0x21, 0xea, 0x01, 0x01, 0x24, 0xea, 0xc2, 0x74, 0x26, 0xea, 0x13, 0x36, 0x27, 0xea, 0xd4, 0x17, 0x28, 0xea, 0xe5, 0x38, 0x2c, 0xea, 0x76, 0x7c, 0x58, 0xbf, 0xea, 0xbe, 0xc5, 0xf3, 0x00, 0x8f, 0x18, 0xbf, 0xc7, 0xf3, 0x00, 0x8f, 0x1f, 0xb9, 0x37, 0xb9, 0x11, 0xee, 0x81, 0x17, 0x11, 0xfe, 0x81, 0x17, 0xbf, 0xf3, 0x2f, 0x8f, 0x18, 0xbf, 0xbf, 0xf3, 0x2f, 0x8f, 0xb2, 0xfa, 0x82, 0xf1, 0x08, 0xbf, 0xb2, 0xfa, 0x82, 0xf1, 0x11, 0xf1, 0x0f, 0x0f, 0x18, 0xeb, 0x06, 0x0f, 0x11, 0xeb, 0x86, 0x2f, 0x11, 0xeb, 0x96, 0x2f, 0x1d, 0xeb, 0x96, 0x2f, 0x11, 0xeb, 0xa6, 0x2f, 0x11, 0xeb, 0xb6, 0x2f, 0xb5, 0xf5, 0x7f, 0x4f, 0xb4, 0xeb, 0x0c, 0x0f, 0xb9, 0xeb, 0x06, 0x3f, 0xb3, 0xeb, 0xd7, 0x7f, 0xbd, 0xeb, 0x56, 0x0f, 0xb2, 0xeb, 0x25, 0x6f, 0xb1, 0xeb, 0xf4, 0x3f, 0x12, 0xf1, 0x02, 0x0f, 0xb9, 0xf1, 0x01, 0x0f, 0x61, 0xb6, 0x74, 0xb6, 0xaf, 0xf3, 0x20, 0x84, 0xaf, 0xf3, 0x80, 0x86, 0xaf, 0xf3, 0x43, 0x85, 0xaf, 0xf3, 0x43, 0x85, 0xaf, 0xf3, 0x29, 0x87, 0xaf, 0xf3, 0x29, 0x87, 0xaf, 0xf3, 0x00, 0x81, 0xaf, 0xf3, 0x00, 0x81, 0xaf, 0xf3, 0xf5, 0x80, 0xaf, 0xf3, 0xf0, 0x80, 0xaf, 0xf3, 0xff, 0x80, 0xaf, 0xf3, 0xf0, 0x80, 0x18, 0xbf, 0xaf, 0xf3, 0xf0, 0x80, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x5e, 0x8f, 0xbf, 0xf3, 0x5d, 0x8f, 0xbf, 0xf3, 0x5c, 0x8f, 0xbf, 0xf3, 0x5b, 0x8f, 0xbf, 0xf3, 0x5a, 0x8f, 0xbf, 0xf3, 0x59, 0x8f, 0xbf, 0xf3, 0x58, 0x8f, 0xbf, 0xf3, 0x57, 0x8f, 0xbf, 0xf3, 0x56, 0x8f, 0xbf, 0xf3, 0x55, 0x8f, 0xbf, 0xf3, 0x54, 0x8f, 0xbf, 0xf3, 0x53, 0x8f, 0xbf, 0xf3, 0x52, 0x8f, 0xbf, 0xf3, 0x51, 0x8f, 0xbf, 0xf3, 0x50, 0x8f, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x5e, 0x8f, 0xbf, 0xf3, 0x5b, 0x8f, 0xbf, 0xf3, 0x5b, 0x8f, 0xbf, 0xf3, 0x5a, 0x8f, 0xbf, 0xf3, 0x5a, 0x8f, 0xbf, 0xf3, 0x57, 0x8f, 0xbf, 0xf3, 0x57, 0x8f, 0xbf, 0xf3, 0x56, 0x8f, 0xbf, 0xf3, 0x56, 0x8f, 0xbf, 0xf3, 0x53, 0x8f, 0xbf, 0xf3, 0x52, 0x8f, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x4e, 0x8f, 0xbf, 0xf3, 0x4d, 0x8f, 0xbf, 0xf3, 0x4c, 0x8f, 0xbf, 0xf3, 0x4b, 0x8f, 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0x1f, 0xf9, 0x16, 0xb0, 0x3f, 0xf9, 0x16, 0xb0, 0x03, 0x49, 0xde, 0xf3, 0x04, 0x8f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "adc r0, r1, #4" + - + asm_text: "adcs r0, r1, #0" + - + asm_text: "adc r1, r2, #0xff" + - + asm_text: "adc r3, r7, #0x550055" + - + asm_text: "adc r8, r12, #0xaa00aa00" + - + asm_text: "adc r9, r7, #0xa5a5a5a5" + - + asm_text: "adc r5, r3, #0x87000000" + - + asm_text: "adc r4, r2, #0x7f800000" + - + asm_text: "adc r4, r2, #0x680" + - + asm_text: "adc.w r4, r5, r6" + - + asm_text: "adcs.w r4, r5, r6" + - + asm_text: "adc.w r9, r1, r3" + - + asm_text: "adcs.w r9, r1, r3" + - + asm_text: "adc.w r0, r1, r3, ror #4" + - + asm_text: "adcs.w r0, r1, r3, lsl #7" + - + asm_text: "adc.w r0, r1, r3, lsr #0x1f" + - + asm_text: "adcs.w r0, r1, r3, asr #0x20" + - + asm_text: "itet eq" + - + asm_text: "addeq r1, r2, #4" + - + asm_text: "addwne r5, r3, #0x3ff" + - + asm_text: "addweq r4, r5, #0x125" + - + asm_text: "add.w r2, sp, #0x400" + - + asm_text: "add.w r2, r8, #0xff00" + - + asm_text: "addw r2, r3, #0x101" + - + asm_text: "addw r2, r3, #0x101" + - + asm_text: "add.w r12, r6, #0x100" + - + asm_text: "addw r12, r6, #0x100" + - + asm_text: "adds.w r1, r2, #0x1f0" + - + asm_text: "add.w r2, r2, #1" + - + asm_text: "add.w r0, r0, #0x20" + - + asm_text: "adds r2, #0x38" + - + asm_text: "adds r2, #0x38" + - + asm_text: "add.w r1, r7, #0xcbcbcbcb" + - + asm_text: "subs.w r2, r2, #0x10" + - + asm_text: "subs.w r2, r2, #0x10" + - + asm_text: "subw r2, r2, #0x10" + - + asm_text: "subw r2, r2, #0x10" + - + asm_text: "subw r2, r2, #0x10" + - + asm_text: "add.w r1, r2, r8" + - + asm_text: "add.w r5, r9, r2, asr #0x20" + - + asm_text: "adds.w r7, r3, r1, lsl #0x1f" + - + asm_text: "adds.w r0, r3, r6, lsr #0x19" + - + asm_text: "add.w r4, r8, r1, ror #0xc" + - + asm_text: "adds r1, r1, r7" + - + asm_text: "it eq" + - + asm_text: "addeq r1, r3, r5" + - + asm_text: "it eq" + - + asm_text: "addeq r1, r1, r5" + - + asm_text: "it eq" + - + asm_text: "addseq.w r1, r3, r5" + - + asm_text: "it eq" + - + asm_text: "addseq.w r1, r1, r5" + - + asm_text: "add r10, r8" + - + asm_text: "add r10, r8" + - + asm_text: "it eq" + - + asm_text: "addeq r1, r10" + - + asm_text: "it eq" + - + asm_text: "addseq.w r1, r1, r10" + - + asm_text: "it eq" + - + asm_text: "addeq r7, sp, #0x3fc" + - + asm_text: "it eq" + - + asm_text: "addeq sp, #0x1fc" + - + asm_text: "add.w r7, sp, #0xf" + - + asm_text: "adds.w r7, sp, #0x10" + - + asm_text: "add.w r8, sp, #0x10" + - + asm_text: "addw r6, sp, #0x3fc" + - + asm_text: "addw r6, sp, #0x3fb" + - + asm_text: "it eq" + - + asm_text: "addeq r8, sp, r8" + - + asm_text: "it eq" + - + asm_text: "addeq sp, r9" + - + asm_text: "add.w r2, sp, r12" + - + asm_text: "it eq" + - + asm_text: "addeq.w r2, sp, r12" + - + asm_text: "adr.w r11, #4294964026" + - + asm_text: "adr.w r2, #3" + - + asm_text: "adr.w r11, #-0x33a" + - + asm_text: "subw r1, pc, #0" + - + asm_text: "and r2, r5, #0xff000" + - + asm_text: "ands r3, r12, #0xf" + - + asm_text: "and r1, r1, #0xff" + - + asm_text: "and r1, r1, #0xff" + - + asm_text: "and r5, r4, #0xffffffff" + - + asm_text: "ands r1, r9, #0xffffffff" + - + asm_text: "and.w r4, r9, r8" + - + asm_text: "and.w r1, r4, r8, asr #3" + - + asm_text: "ands.w r2, r1, r7, lsl #1" + - + asm_text: "ands.w r4, r5, r2, lsr #0x14" + - + asm_text: "and.w r9, r12, r1, ror #0x11" + - + asm_text: "asr.w r2, r3, #0xc" + - + asm_text: "asrs.w r8, r3, #0x20" + - + asm_text: "asrs.w r2, r3, #1" + - + asm_text: "asr.w r2, r3, #4" + - + asm_text: "asrs.w r2, r12, #0xf" + - + asm_text: "asr.w r3, r3, #0x13" + - + asm_text: "asrs.w r8, r8, #2" + - + asm_text: "asrs.w r7, r7, #5" + - + asm_text: "asr.w r12, r12, #0x15" + - + asm_text: "asrs r1, r2, #1" + - + asm_text: "itt eq" + - + asm_text: "asrseq.w r1, r2, #1" + - + asm_text: "asreq r1, r2, #1" + - + asm_text: "asr.w r3, r4, r2" + - + asm_text: "asr.w r1, r1, r2" + - + asm_text: "asrs.w r3, r4, r8" + - + asm_text: "it eq" + - + asm_text: "beq.w #-0x2cc64" + - + asm_text: "bfc r5, #3, #0x11" + - + asm_text: "it lo" + - + asm_text: "bfclo r5, #3, #0x11" + - + asm_text: "bfi r5, r2, #3, #0x11" + - + asm_text: "it ne" + - + asm_text: "bfine r5, r2, #3, #0x11" + - + asm_text: "bic r10, r1, #0xf" + - + asm_text: "bic r5, r2, #0xffffffff" + - + asm_text: "bics r11, r10, #0xffffffff" + - + asm_text: "bic.w r12, r3, r6" + - + asm_text: "bic.w r11, r2, r6, lsl #0xc" + - + asm_text: "bic.w r8, r4, r1, lsr #0xb" + - + asm_text: "bic.w r7, r5, r7, lsr #0xf" + - + asm_text: "bic.w r6, r7, r9, asr #0x20" + - + asm_text: "bic.w r5, r6, r8, ror #1" + - + asm_text: "bic r1, r1, #0xf" + - + asm_text: "bic.w r1, r1, r1" + - + asm_text: "bic.w r4, r4, r2, lsl #0x1f" + - + asm_text: "bic.w r6, r6, r3, lsr #0xc" + - + asm_text: "bic.w r7, r7, r4, lsr #7" + - + asm_text: "bic.w r8, r8, r5, asr #0xf" + - + asm_text: "bic.w r12, r12, r6, ror #0x1d" + - + asm_text: "it pl" + - + asm_text: "bkpt #0xea" + - + asm_text: "bxj r5" + - + asm_text: "it ne" + - + asm_text: "bxjne r7" + - + asm_text: "cbnz r7, #6" + - + asm_text: "cbnz r7, #0xc" + - + asm_text: "cdp p7, #1, c1, c1, c1, #4" + - + asm_text: "cdp2 p7, #1, c1, c1, c1, #4" + - + asm_text: "clrex" + - + asm_text: "it ne" + - + asm_text: "clrexne" + - + asm_text: "clz r1, r2" + - + asm_text: "it eq" + - + asm_text: "clzeq r1, r2" + - + asm_text: "cmn.w r1, #0xf" + - + asm_text: "cmn.w r8, r6" + - + asm_text: "cmn.w r1, r6, lsl #0xa" + - + asm_text: "cmn.w r1, r6, lsr #0xa" + - + asm_text: "cmn.w sp, r6, lsr #0xa" + - + asm_text: "cmn.w r1, r6, asr #0xa" + - + asm_text: "cmn.w r1, r6, ror #0xa" + - + asm_text: "cmp.w r5, #0xff00" + - + asm_text: "cmp.w r4, r12" + - + asm_text: "cmp.w r9, r6, lsl #0xc" + - + asm_text: "cmp.w r3, r7, lsr #0x1f" + - + asm_text: "cmp.w sp, r6, lsr #1" + - + asm_text: "cmp.w r2, r5, asr #0x18" + - + asm_text: "cmp.w r1, r4, ror #0xf" + - + asm_text: "cmn.w r2, #2" + - + asm_text: "cmp.w r9, #1" + - + asm_text: "cpsie f" + - + asm_text: "cpsid a" + - + asm_text: "cpsie.w f" + - + asm_text: "cpsid.w a" + - + asm_text: "cpsie i, #3" + - + asm_text: "cpsie i, #3" + - + asm_text: "cpsid f, #0x9" + - + asm_text: "cpsid f, #0x9" + - + asm_text: "cps #0" + - + asm_text: "cps #0" + - + asm_text: "dbg #5" + - + asm_text: "dbg #0" + - + asm_text: "dbg #0xf" + - + asm_text: "dbg #0" + - + asm_text: "it ne" + - + asm_text: "dbgne #0" + - + asm_text: "dmb sy" + - + asm_text: "dmb st" + - + asm_text: "dmb #0xd" + - + asm_text: "dmb #0xc" + - + asm_text: "dmb ish" + - + asm_text: "dmb ishst" + - + asm_text: "dmb #0x9" + - + asm_text: "dmb #0x8" + - + asm_text: "dmb nsh" + - + asm_text: "dmb nshst" + - + asm_text: "dmb #0x5" + - + asm_text: "dmb #0x4" + - + asm_text: "dmb osh" + - + asm_text: "dmb oshst" + - + asm_text: "dmb #0x1" + - + asm_text: "dmb #0x0" + - + asm_text: "dmb sy" + - + asm_text: "dmb sy" + - + asm_text: "dmb st" + - + asm_text: "dmb ish" + - + asm_text: "dmb ish" + - + asm_text: "dmb ishst" + - + asm_text: "dmb ishst" + - + asm_text: "dmb nsh" + - + asm_text: "dmb nsh" + - + asm_text: "dmb nshst" + - + asm_text: "dmb nshst" + - + asm_text: "dmb osh" + - + asm_text: "dmb oshst" + - + asm_text: "dmb sy" + - + asm_text: "dmb sy" + - + asm_text: "dsb sy" + - + asm_text: "dsb st" + - + asm_text: "dsb #0xd" + - + asm_text: "dsb #0xc" + - + asm_text: "dsb ish" + - + asm_text: "dsb ishst" + - + asm_text: "dsb #0x9" + - + asm_text: "dsb #0x8" + - + asm_text: "dsb nsh" + - + asm_text: "dsb nshst" + - + asm_text: "dsb #0x5" + - + asm_text: "pssbb" + - + asm_text: "dsb osh" + - + asm_text: "dsb oshst" + - + asm_text: "dsb #0x1" + - + asm_text: "ssbb" + - + asm_text: "dsb sy" + - + asm_text: "dsb sy" + - + asm_text: "dsb st" + - + asm_text: "dsb ish" + - + asm_text: "dsb ish" + - + asm_text: "dsb ishst" + - + asm_text: "dsb ishst" + - + asm_text: "dsb nsh" + - + asm_text: "dsb nsh" + - + asm_text: "dsb nshst" + - + asm_text: "dsb nshst" + - + asm_text: "dsb osh" + - + asm_text: "dsb oshst" + - + asm_text: "dsb sy" + - + asm_text: "dsb sy" + - + asm_text: "eor r4, r5, #0xf000" + - + asm_text: "eor.w r4, r5, r6" + - + asm_text: "eor.w r4, r5, r6, lsl #5" + - + asm_text: "eor.w r4, r5, r6, lsr #5" + - + asm_text: "eor.w r4, r5, r6, lsr #5" + - + asm_text: "eor.w r4, r5, r6, asr #5" + - + asm_text: "eor.w r4, r5, r6, ror #5" + - + asm_text: "isb sy" + - + asm_text: "isb sy" + - + asm_text: "isb sy" + - + asm_text: "isb sy" + - + asm_text: "isb sy" + - + asm_text: "isb #0x1" + - + asm_text: "iteet eq" + - + asm_text: "addeq r0, r1, r2" + - + asm_text: "nopne" + - + asm_text: "subne r5, r6, r7" + - + asm_text: "addeq r1, r2, #4" + - + asm_text: "iteet eq" + - + asm_text: "addeq r0, r1, r2" + - + asm_text: "nopne" + - + asm_text: "subne r5, r6, r7" + - + asm_text: "addeq r1, r2, #4" + - + asm_text: "ldc2 p0, c8, [r1, #4]" + - + asm_text: "ldc2 p1, c7, [r2]" + - + asm_text: "ldc2 p2, c6, [r3, #-0xe0]" + - + asm_text: "ldc2 p3, c5, [r4, #-0x78]!" + - + asm_text: "ldc2 p4, c4, [r5], #0x10" + - + asm_text: "ldc2 p5, c3, [r6], #-0x48" + - + asm_text: "ldc2l p6, c2, [r7, #4]" + - + asm_text: "ldc2l p7, c1, [r8]" + - + asm_text: "ldc2l p8, c0, [r9, #-0xe0]" + - + asm_text: "ldc2l p9, c1, [r10, #-0x78]!" + - + asm_text: "ldc2l p0, c2, [r11], #0x10" + - + asm_text: "ldc2l p1, c3, [r12], #-0x48" + - + asm_text: "ldc p12, c4, [r0, #4]" + - + asm_text: "ldc p13, c5, [r1]" + - + asm_text: "ldc p14, c6, [r2, #-0xe0]" + - + asm_text: "ldc p15, c7, [r3, #-0x78]!" + - + asm_text: "ldc p5, c8, [r4], #0x10" + - + asm_text: "ldc p4, c9, [r5], #-0x48" + - + asm_text: "ldcl p3, c10, [r6, #4]" + - + asm_text: "ldcl p2, c11, [r7]" + - + asm_text: "ldcl p1, c12, [r8, #-0xe0]" + - + asm_text: "ldcl p0, c13, [r9, #-0x78]!" + - + asm_text: "ldcl p6, c14, [r10], #0x10" + - + asm_text: "ldcl p7, c15, [r11], #-0x48" + - + asm_text: "ldc2 p2, c8, [r1], {25}" + - + asm_text: "ldm.w r4, {r4, r5, r8, r9}" + - + asm_text: "ldm.w r4, {r5, r6}" + - + asm_text: "ldm.w r5!, {r3, r8}" + - + asm_text: "ldm.w r4, {r4, r5, r8, r9}" + - + asm_text: "ldm.w r4, {r5, r6}" + - + asm_text: "ldm.w r5!, {r3, r8}" + - + asm_text: "ldm.w r5!, {r1, r2}" + - + asm_text: "ldm.w r2, {r1, r2}" + - + asm_text: "ldm.w r4, {r4, r5, r8, r9}" + - + asm_text: "ldm.w r4, {r5, r6}" + - + asm_text: "ldm.w r5!, {r3, r8}" + - + asm_text: "ldm.w r4, {r4, r5, r8, r9}" + - + asm_text: "ldm.w r4, {r5, r6}" + - + asm_text: "ldm.w r5!, {r3, r8}" + - + asm_text: "ldm.w r5!, {r3, r8}" + - + asm_text: "pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}" + - + asm_text: "ldmdb r4, {r4, r5, r8, r9}" + - + asm_text: "ldmdb r4, {r5, r6}" + - + asm_text: "ldmdb r5!, {r3, r8}" + - + asm_text: "ldmdb r5!, {r3, r8}" + - + asm_text: "ldmdb r4, {r5, r6}" + - + asm_text: "ldmdb r5!, {r3, r8}" + - + asm_text: "ldr r5, [r5, #-4]" + - + asm_text: "ldr r5, [r6, #0x20]" + - + asm_text: "ldr.w r5, [r6, #0x21]" + - + asm_text: "ldr.w r5, [r6, #0x101]" + - + asm_text: "ldr.w pc, [r7, #0x101]" + - + asm_text: "ldr r2, [r4, #0xff]!" + - + asm_text: "ldr r8, [sp, #4]!" + - + asm_text: "ldr lr, [sp, #-4]!" + - + asm_text: "ldr r2, [r4], #0xff" + - + asm_text: "pop {r8}" + - + asm_text: "ldr lr, [sp], #-4" + - + asm_text: "ldr r7, [pc, #8]" + - + asm_text: "ldr r7, [pc, #8]" + - + asm_text: "ldr.w r7, [pc, #8]" + - + asm_text: "ldr r4, [pc, #0x3fc]" + - + asm_text: "ldr.w r3, [pc, #-0x3fc]" + - + asm_text: "ldr.w r6, [pc, #0x400]" + - + asm_text: "ldr.w r0, [pc, #-0x400]" + - + asm_text: "ldr.w r2, [pc, #0xfff]" + - + asm_text: "ldr.w r1, [pc, #-0xfff]" + - + asm_text: "ldr.w r8, [pc, #0x84]" + - + asm_text: "ldr.w pc, [pc, #0x100]" + - + asm_text: "ldr.w pc, [pc, #-0x190]" + - + asm_text: "ldr.w sp, [pc, #4]" + - + asm_text: "ldrb.w r9, [pc, #-0]" + - + asm_text: "ldrsb.w r11, [pc, #-0]" + - + asm_text: "ldrh.w r10, [pc, #-0]" + - + asm_text: "ldrsh.w r1, [pc, #-0]" + - + asm_text: "ldr.w r5, [pc, #-0]" + - + asm_text: "ldr.w r1, [r8, r1]" + - + asm_text: "ldr.w r4, [r5, r2]" + - + asm_text: "ldr.w r6, [r0, r2, lsl #3]" + - + asm_text: "ldr.w r8, [r8, r2, lsl #2]" + - + asm_text: "ldr.w r7, [sp, r2, lsl #1]" + - + asm_text: "ldr.w r7, [sp, r2]" + - + asm_text: "ldrb r5, [r5, #-4]" + - + asm_text: "ldrb.w r5, [r6, #0x20]" + - + asm_text: "ldrb.w r5, [r6, #0x21]" + - + asm_text: "ldrb.w r5, [r6, #0x101]" + - + asm_text: "ldrb.w lr, [r7, #0x101]" + - + asm_text: "ldrb r5, [r8, #0xff]!" + - + asm_text: "ldrb r2, [r5, #4]!" + - + asm_text: "ldrb r1, [r4, #-4]!" + - + asm_text: "ldrb lr, [r3], #0xff" + - + asm_text: "ldrb r9, [r2], #4" + - + asm_text: "ldrb r3, [sp], #-4" + - + asm_text: "ldrb.w r1, [r8, r1]" + - + asm_text: "ldrb.w r4, [r5, r2]" + - + asm_text: "ldrb.w r6, [r0, r2, lsl #3]" + - + asm_text: "ldrb.w r8, [r8, r2, lsl #2]" + - + asm_text: "ldrb.w r7, [sp, r2, lsl #1]" + - + asm_text: "ldrb.w r7, [sp, r2]" + - + asm_text: "ldrbt r1, [r2]" + - + asm_text: "ldrbt r1, [r8]" + - + asm_text: "ldrbt r1, [r8, #3]" + - + asm_text: "ldrbt r1, [r8, #0xff]" + - + asm_text: "ldrd r3, r5, [r6, #0x18]" + - + asm_text: "ldrd r3, r5, [r6, #0x18]!" + - + asm_text: "ldrd r3, r5, [r6], #4" + - + asm_text: "ldrd r3, r5, [r6], #-8" + - + asm_text: "ldrd r3, r5, [r6]" + - + asm_text: "ldrd r8, r1, [r3]" + - + asm_text: "ldrd r0, r1, [r2, #-0]" + - + asm_text: "ldrd r0, r1, [r2, #-0]!" + - + asm_text: "ldrd r0, r1, [r2], #-0" + - + asm_text: "ldrex r1, [r4]" + - + asm_text: "ldrex r8, [r4]" + - + asm_text: "ldrex r2, [sp, #0x80]" + - + asm_text: "ldrexb r5, [r7]" + - + asm_text: "ldrexh r9, [r12]" + - + asm_text: "ldrexd r9, r3, [r4]" + - + asm_text: "ldrh r5, [r5, #-4]" + - + asm_text: "ldrh r5, [r6, #0x20]" + - + asm_text: "ldrh.w r5, [r6, #0x21]" + - + asm_text: "ldrh.w r5, [r6, #0x101]" + - + asm_text: "ldrh.w lr, [r7, #0x101]" + - + asm_text: "ldrh r5, [r8, #0xff]!" + - + asm_text: "ldrh r2, [r5, #4]!" + - + asm_text: "ldrh r1, [r4, #-4]!" + - + asm_text: "ldrh lr, [r3], #0xff" + - + asm_text: "ldrh r9, [r2], #4" + - + asm_text: "ldrh r3, [sp], #-4" + - + asm_text: "ldrh.w r1, [r8, r1]" + - + asm_text: "ldrh.w r4, [r5, r2]" + - + asm_text: "ldrh.w r6, [r0, r2, lsl #3]" + - + asm_text: "ldrh.w r8, [r8, r2, lsl #2]" + - + asm_text: "ldrh.w r7, [sp, r2, lsl #1]" + - + asm_text: "ldrh.w r7, [sp, r2]" + - + asm_text: "ldrht r1, [r2]" + - + asm_text: "ldrht r1, [r8]" + - + asm_text: "ldrht r1, [r8, #3]" + - + asm_text: "ldrht r1, [r8, #0xff]" + - + asm_text: "ldrsb r5, [r5, #-4]" + - + asm_text: "ldrsb.w r5, [r6, #0x20]" + - + asm_text: "ldrsb.w r5, [r6, #0x21]" + - + asm_text: "ldrsb.w r5, [r6, #0x101]" + - + asm_text: "ldrsb.w lr, [r7, #0x101]" + - + asm_text: "ldrsb.w r1, [r8, r1]" + - + asm_text: "ldrsb.w r4, [r5, r2]" + - + asm_text: "ldrsb.w r6, [r0, r2, lsl #3]" + - + asm_text: "ldrsb.w r8, [r8, r2, lsl #2]" + - + asm_text: "ldrsb.w r7, [sp, r2, lsl #1]" + - + asm_text: "ldrsb.w r7, [sp, r2]" + - + asm_text: "ldrsb r5, [r8, #0xff]!" + - + asm_text: "ldrsb r2, [r5, #4]!" + - + asm_text: "ldrsb r1, [r4, #-4]!" + - + asm_text: "ldrsb lr, [r3], #0xff" + - + asm_text: "ldrsb r9, [r2], #4" + - + asm_text: "ldrsb r3, [sp], #-4" + - + asm_text: "ldrsbt r1, [r2]" + - + asm_text: "ldrsbt r1, [r8]" + - + asm_text: "ldrsbt r1, [r8, #3]" + - + asm_text: "ldrsbt r1, [r8, #0xff]" + - + asm_text: "ldrsh r5, [r5, #-4]" + - + asm_text: "ldrsh.w r5, [r6, #0x20]" + - + asm_text: "ldrsh.w r5, [r6, #0x21]" + - + asm_text: "ldrsh.w r5, [r6, #0x101]" + - + asm_text: "ldrsh.w lr, [r7, #0x101]" + - + asm_text: "ldrsh.w r1, [r8, r1]" + - + asm_text: "ldrsh.w r4, [r5, r2]" + - + asm_text: "ldrsh.w r6, [r0, r2, lsl #3]" + - + asm_text: "ldrsh.w r8, [r8, r2, lsl #2]" + - + asm_text: "ldrsh.w r7, [sp, r2, lsl #1]" + - + asm_text: "ldrsh.w r7, [sp, r2]" + - + asm_text: "ldrsh r5, [r8, #0xff]!" + - + asm_text: "ldrsh r2, [r5, #4]!" + - + asm_text: "ldrsh r1, [r4, #-4]!" + - + asm_text: "ldrsh lr, [r3], #0xff" + - + asm_text: "ldrsh r9, [r2], #4" + - + asm_text: "ldrsh r3, [sp], #-4" + - + asm_text: "ldrsht r1, [r2]" + - + asm_text: "ldrsht r1, [r8]" + - + asm_text: "ldrsht r1, [r8, #3]" + - + asm_text: "ldrsht r1, [r8, #0xff]" + - + asm_text: "ldrt r1, [r2]" + - + asm_text: "ldrt r2, [r6]" + - + asm_text: "ldrt r3, [r7, #3]" + - + asm_text: "ldrt r4, [r9, #0xff]" + - + asm_text: "lsl.w r2, r3, #0xc" + - + asm_text: "lsls.w r8, r3, #0x1f" + - + asm_text: "lsls.w r2, r3, #1" + - + asm_text: "lsl.w r2, r3, #4" + - + asm_text: "lsls.w r2, r12, #0xf" + - + asm_text: "lsl.w r3, r3, #0x13" + - + asm_text: "lsls.w r8, r8, #2" + - + asm_text: "lsls.w r7, r7, #5" + - + asm_text: "lsl.w r12, r12, #0x15" + - + asm_text: "lsls r1, r2, #1" + - + asm_text: "itt eq" + - + asm_text: "lslseq.w r1, r2, #1" + - + asm_text: "lsleq r1, r2, #1" + - + asm_text: "lsl.w r3, r4, r2" + - + asm_text: "lsl.w r1, r1, r2" + - + asm_text: "lsls.w r3, r4, r8" + - + asm_text: "lsr.w r2, r3, #0xc" + - + asm_text: "lsrs.w r8, r3, #0x20" + - + asm_text: "lsrs.w r2, r3, #1" + - + asm_text: "lsr.w r2, r3, #4" + - + asm_text: "lsrs.w r2, r12, #0xf" + - + asm_text: "lsr.w r3, r3, #0x13" + - + asm_text: "lsrs.w r8, r8, #2" + - + asm_text: "lsrs.w r7, r7, #5" + - + asm_text: "lsr.w r12, r12, #0x15" + - + asm_text: "lsrs r1, r2, #1" + - + asm_text: "itt eq" + - + asm_text: "lsrseq.w r1, r2, #1" + - + asm_text: "lsreq r1, r2, #1" + - + asm_text: "lsr.w r3, r4, r2" + - + asm_text: "lsr.w r1, r1, r2" + - + asm_text: "lsrs.w r3, r4, r8" + - + asm_text: "mcr p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr2 p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr p14, #0, r4, c0, c5, #0" + - + asm_text: "mcr2 p4, #2, r2, c1, c3, #0" + - + asm_text: "mcr p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr2 p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr p14, #0, r4, c0, c5, #0" + - + asm_text: "mcr2 p4, #2, r2, c1, c3, #0" + - + asm_text: "mcrr p7, #0xf, r5, r4, c1" + - + asm_text: "mcrr2 p7, #0xf, r5, r4, c1" + - + asm_text: "mcrr p7, #0xf, r5, r4, c1" + - + asm_text: "mcrr2 p7, #0xf, r5, r4, c1" + - + asm_text: "mla r1, r2, r3, r4" + - + asm_text: "mls r1, r2, r3, r4" + - + asm_text: "movs r1, #0x15" + - + asm_text: "movs.w r1, #0x15" + - + asm_text: "movs.w r8, #0x15" + - + asm_text: "movw r0, #0xffff" + - + asm_text: "movw r1, #0xab01" + - + asm_text: "movw r1, #0xab10" + - + asm_text: "mov.w r0, #0x3fc0000" + - + asm_text: "mov.w r0, #0x3fc0000" + - + asm_text: "movs.w r0, #0x3fc0000" + - + asm_text: "itte eq" + - + asm_text: "movseq.w r1, #0xc" + - + asm_text: "moveq r1, #0xc" + - + asm_text: "movne.w r1, #0xc" + - + asm_text: "mov.w r6, #0x1c2" + - + asm_text: "it lo" + - + asm_text: "movlo.w r1, #-1" + - + asm_text: "mvn r3, #2" + - + asm_text: "movw r11, #0xabcd" + - + asm_text: "movs r0, #1" + - + asm_text: "it ne" + - + asm_text: "movne r3, #0xf" + - + asm_text: "itt eq" + - + asm_text: "moveq r0, #0xff" + - + asm_text: "movweq r1, #0x100" + - + asm_text: "lsl.w r6, r2, #0x10" + - + asm_text: "lsl.w r6, r2, #0x10" + - + asm_text: "lsr.w r6, r2, #0x10" + - + asm_text: "lsr.w r6, r2, #0x10" + - + asm_text: "asrs r6, r2, #0x20" + - + asm_text: "asrs.w r6, r2, #0x20" + - + asm_text: "rors.w r6, r2, #5" + - + asm_text: "rors.w r6, r2, #5" + - + asm_text: "lsls r4, r5" + - + asm_text: "lsls.w r4, r4, r5" + - + asm_text: "lsrs r4, r5" + - + asm_text: "lsrs.w r4, r4, r5" + - + asm_text: "asrs r4, r5" + - + asm_text: "asrs.w r4, r4, r5" + - + asm_text: "rors r4, r5" + - + asm_text: "rors.w r4, r4, r5" + - + asm_text: "lsl.w r4, r4, r5" + - + asm_text: "rors.w r4, r4, r8" + - + asm_text: "lsrs.w r4, r5, r6" + - + asm_text: "itttt eq" + - + asm_text: "lsleq r4, r5" + - + asm_text: "lsreq r4, r5" + - + asm_text: "asreq r4, r5" + - + asm_text: "roreq r4, r5" + - + asm_text: "rrx r4, r4" + - + asm_text: "movt r3, #7" + - + asm_text: "movt r6, #0xffff" + - + asm_text: "it eq" + - + asm_text: "movteq r4, #0xff0" + - + asm_text: "mrc p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc p15, #7, apsr_nzcv, c15, c6, #6" + - + asm_text: "mrc p9, #1, r1, c2, c2, #0" + - + asm_text: "mrc2 p12, #3, r3, c3, c4, #0" + - + asm_text: "mrc2 p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc2 p8, #7, apsr_nzcv, c15, c0, #1" + - + asm_text: "mrc p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc p15, #7, apsr_nzcv, c15, c6, #6" + - + asm_text: "mrc p9, #1, r1, c2, c2, #0" + - + asm_text: "mrc2 p12, #3, r3, c3, c4, #0" + - + asm_text: "mrc2 p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc2 p8, #7, apsr_nzcv, c15, c0, #1" + - + asm_text: "mrrc p7, #1, r5, r4, c1" + - + asm_text: "mrrc2 p7, #1, r5, r4, c1" + - + asm_text: "mrrc p7, #1, r5, r4, c1" + - + asm_text: "mrrc2 p7, #1, r5, r4, c1" + - + asm_text: "mrs r8, apsr" + - + asm_text: "mrs r8, apsr" + - + asm_text: "mrs r8, spsr" + - + asm_text: "msr apsr_nzcvq, r1" + - + asm_text: "msr apsr_g, r2" + - + asm_text: "msr apsr_nzcvq, r3" + - + asm_text: "msr apsr_nzcvq, r4" + - + asm_text: "msr apsr_nzcvqg, r5" + - + asm_text: "msr cpsr_fc, r6" + - + asm_text: "msr cpsr_c, r7" + - + asm_text: "msr cpsr_x, r8" + - + asm_text: "msr cpsr_fc, r9" + - + asm_text: "msr cpsr_fc, r11" + - + asm_text: "msr cpsr_fsx, r12" + - + asm_text: "msr spsr_fc, r0" + - + asm_text: "msr spsr_fsxc, r5" + - + asm_text: "msr cpsr_fsxc, r8" + - + asm_text: "msr cpsr_fc, r3" + - + asm_text: "muls r3, r4, r3" + - + asm_text: "mul r3, r4, r3" + - + asm_text: "mul r3, r4, r6" + - + asm_text: "it eq" + - + asm_text: "muleq r3, r4, r5" + - + asm_text: "it le" + - + asm_text: "mulle r4, r4, r8" + - + asm_text: "mul r5, r6, r5" + - + asm_text: "mvns r8, #0x15" + - + asm_text: "mvn r0, #0x3fc0000" + - + asm_text: "mvns r0, #0x3fc0000" + - + asm_text: "itte eq" + - + asm_text: "mvnseq r1, #0xc" + - + asm_text: "mvneq r1, #0xc" + - + asm_text: "mvnne r1, #0xc" + - + asm_text: "mvn.w r2, r3" + - + asm_text: "mvns r2, r3" + - + asm_text: "mvn.w r5, r6, lsl #0x13" + - + asm_text: "mvn.w r5, r6, lsr #0x9" + - + asm_text: "mvn.w r5, r6, asr #4" + - + asm_text: "mvn.w r5, r6, ror #6" + - + asm_text: "mvn.w r5, r6, rrx" + - + asm_text: "it eq" + - + asm_text: "mvneq r2, r3" + - + asm_text: "rsb.w r5, r2, #0" + - + asm_text: "rsb.w r5, r8, #0" + - + asm_text: "nop.w" + - + asm_text: "orn r4, r5, #0xf000" + - + asm_text: "orn r4, r5, #0xf000" + - + asm_text: "orn r4, r5, r6" + - + asm_text: "orn r4, r5, r6" + - + asm_text: "orns r4, r5, r6" + - + asm_text: "orns r4, r5, r6" + - + asm_text: "orn r4, r5, r6, lsl #5" + - + asm_text: "orn r4, r5, r6, lsl #5" + - + asm_text: "orns r4, r5, r6, lsr #5" + - + asm_text: "orn r4, r5, r6, lsr #5" + - + asm_text: "orns r4, r5, r6, asr #5" + - + asm_text: "orn r4, r5, r6, ror #5" + - + asm_text: "orr r4, r5, #0xf000" + - + asm_text: "orr.w r4, r5, r6" + - + asm_text: "orr.w r4, r5, r6, lsl #5" + - + asm_text: "orrs.w r4, r5, r6, lsr #5" + - + asm_text: "orr.w r4, r5, r6, lsr #5" + - + asm_text: "orrs.w r4, r5, r6, asr #5" + - + asm_text: "orr.w r4, r5, r6, ror #5" + - + asm_text: "pkhbt r2, r2, r3" + - + asm_text: "pkhbt r2, r2, r3, lsl #0x1f" + - + asm_text: "pkhbt r2, r2, r3" + - + asm_text: "pkhbt r2, r2, r3, lsl #0xf" + - + asm_text: "pkhbt r2, r3, r2" + - + asm_text: "pkhtb r2, r2, r3, asr #0x1f" + - + asm_text: "pkhtb r2, r2, r3, asr #0xf" + - + asm_text: "pld [r5, #-4]" + - + asm_text: "pld [r6, #0x20]" + - + asm_text: "pld [r6, #0x21]" + - + asm_text: "pld [r6, #0x101]" + - + asm_text: "pld [r7, #0x101]" + - + asm_text: "pld [r1]" + - + asm_text: "pld [r1, #-0]" + - + asm_text: "pld [r1, #-0]" + - + asm_text: "pld [pc, #-0xfff]" + - + asm_text: "pld [pc, #-0xfff]" + - + asm_text: "pld [r8, r1]" + - + asm_text: "pld [r5, r2]" + - + asm_text: "pld [r5, r2]" + - + asm_text: "pld [r0, r2, lsl #3]" + - + asm_text: "pld [r8, r2, lsl #2]" + - + asm_text: "pld [sp, r2, lsl #1]" + - + asm_text: "pld [sp, r2]" + - + asm_text: "pld [sp, r2, lsl #1]" + - + asm_text: "pli [r5, #-4]" + - + asm_text: "pli [r6, #0x20]" + - + asm_text: "pli [r6, #0x21]" + - + asm_text: "pli [r6, #0x101]" + - + asm_text: "pli [r7, #0x101]" + - + asm_text: "pli [pc, #0xfff]" + - + asm_text: "pli [pc, #-0xfff]" + - + asm_text: "pli [pc, #-0xfff]" + - + asm_text: "pli [r8, r1]" + - + asm_text: "pli [r5, r2]" + - + asm_text: "pli [r5, r2]" + - + asm_text: "pli [r0, r2, lsl #3]" + - + asm_text: "pli [r8, r2, lsl #2]" + - + asm_text: "pli [sp, r2, lsl #1]" + - + asm_text: "pli [sp, r2]" + - + asm_text: "pli [sp, r2, lsl #1]" + - + asm_text: "pop.w {r2, r9}" + - + asm_text: "push.w {r2, r9}" + - + asm_text: "qadd r1, r2, r3" + - + asm_text: "qadd16 r1, r2, r3" + - + asm_text: "qadd8 r1, r2, r3" + - + asm_text: "itte gt" + - + asm_text: "qaddgt r1, r2, r3" + - + asm_text: "qadd16gt r1, r2, r3" + - + asm_text: "qadd8le r1, r2, r3" + - + asm_text: "qdadd r6, r7, r8" + - + asm_text: "qdsub r6, r7, r8" + - + asm_text: "itt hi" + - + asm_text: "qdaddhi r6, r7, r8" + - + asm_text: "qdsubhi r6, r7, r8" + - + asm_text: "qsax r9, r12, r0" + - + asm_text: "it eq" + - + asm_text: "qsaxeq r9, r12, r0" + - + asm_text: "qsub r1, r2, r3" + - + asm_text: "qsub16 r1, r2, r3" + - + asm_text: "qsub8 r1, r2, r3" + - + asm_text: "itet le" + - + asm_text: "qsuble r1, r2, r3" + - + asm_text: "qsub16gt r1, r2, r3" + - + asm_text: "qsub8le r1, r2, r3" + - + asm_text: "rbit r1, r2" + - + asm_text: "it ne" + - + asm_text: "rbitne r1, r2" + - + asm_text: "rev.w r1, r2" + - + asm_text: "rev.w r2, r8" + - + asm_text: "itt ne" + - + asm_text: "revne r1, r2" + - + asm_text: "revne.w r1, r8" + - + asm_text: "rev16.w r1, r2" + - + asm_text: "rev16.w r2, r8" + - + asm_text: "itt ne" + - + asm_text: "rev16ne r1, r2" + - + asm_text: "rev16ne.w r1, r8" + - + asm_text: "revsh.w r1, r2" + - + asm_text: "revsh.w r2, r8" + - + asm_text: "itt ne" + - + asm_text: "revshne r1, r2" + - + asm_text: "revshne.w r1, r8" + - + asm_text: "ror.w r2, r3, #0xc" + - + asm_text: "rors.w r8, r3, #0x1f" + - + asm_text: "rors.w r2, r3, #1" + - + asm_text: "ror.w r2, r3, #4" + - + asm_text: "rors.w r2, r12, #0xf" + - + asm_text: "ror.w r3, r3, #0x13" + - + asm_text: "rors.w r8, r8, #2" + - + asm_text: "rors.w r7, r7, #5" + - + asm_text: "ror.w r12, r12, #0x15" + - + asm_text: "ror.w r3, r4, r2" + - + asm_text: "ror.w r1, r1, r2" + - + asm_text: "rors.w r3, r4, r8" + - + asm_text: "rrx r1, r2" + - + asm_text: "rrxs r1, r2" + - + asm_text: "ite lt" + - + asm_text: "rrxlt r9, r12" + - + asm_text: "rrxsge r8, r3" + - + asm_text: "rsb.w r2, r5, #0xff000" + - + asm_text: "rsbs.w r3, r12, #0xf" + - + asm_text: "rsb.w r1, r1, #0xff" + - + asm_text: "rsb.w r1, r1, #0xff" + - + asm_text: "rsb.w r11, r11, #0" + - + asm_text: "rsb.w r9, r9, #0" + - + asm_text: "rsbs r3, r1, #0" + - + asm_text: "rsb.w r3, r1, #0" + - + asm_text: "rsb r4, r4, r8" + - + asm_text: "rsb r4, r4, r8" + - + asm_text: "rsb r4, r9, r8" + - + asm_text: "rsb r4, r9, r8" + - + asm_text: "rsb r1, r4, r8, asr #3" + - + asm_text: "rsb r1, r4, r8, asr #3" + - + asm_text: "rsbs r2, r1, r7, lsl #1" + - + asm_text: "rsbs r2, r1, r7, lsl #1" + - + asm_text: "rsbs r0, r1, r2" + - + asm_text: "rsbs r0, r1, r2" + - + asm_text: "sadd16 r3, r4, r8" + - + asm_text: "it ne" + - + asm_text: "sadd16ne r3, r4, r8" + - + asm_text: "sadd8 r3, r4, r8" + - + asm_text: "it ne" + - + asm_text: "sadd8ne r3, r4, r8" + - + asm_text: "sasx r9, r2, r7" + - + asm_text: "it ne" + - + asm_text: "sasxne r2, r5, r6" + - + asm_text: "sasx r9, r2, r7" + - + asm_text: "it ne" + - + asm_text: "sasxne r2, r5, r6" + - + asm_text: "sbc r0, r1, #4" + - + asm_text: "sbcs r0, r1, #0" + - + asm_text: "sbc r1, r2, #0xff" + - + asm_text: "sbc r3, r7, #0x550055" + - + asm_text: "sbc r8, r12, #0xaa00aa00" + - + asm_text: "sbc r9, r7, #0xa5a5a5a5" + - + asm_text: "sbc r5, r3, #0x87000000" + - + asm_text: "sbc r4, r2, #0x7f800000" + - + asm_text: "sbc r4, r2, #0x680" + - + asm_text: "sbc.w r4, r5, r6" + - + asm_text: "sbcs.w r4, r5, r6" + - + asm_text: "sbc.w r9, r1, r3" + - + asm_text: "sbcs.w r9, r1, r3" + - + asm_text: "sbc.w r0, r1, r3, ror #4" + - + asm_text: "sbcs.w r0, r1, r3, lsl #7" + - + asm_text: "sbc.w r0, r1, r3, lsr #0x1f" + - + asm_text: "sbcs.w r0, r1, r3, asr #0x20" + - + asm_text: "sbfx r4, r5, #0x10, #1" + - + asm_text: "it gt" + - + asm_text: "sbfxgt r4, r5, #0x10, #0x10" + - + asm_text: "sel r5, r9, r2" + - + asm_text: "it le" + - + asm_text: "selle r5, r9, r2" + - + asm_text: "sev.w" + - + asm_text: "it eq" + - + asm_text: "seveq.w" + - + asm_text: "sadd16 r1, r2, r3" + - + asm_text: "sadd8 r1, r2, r3" + - + asm_text: "ite gt" + - + asm_text: "sadd16gt r1, r2, r3" + - + asm_text: "sadd8le r1, r2, r3" + - + asm_text: "shasx r4, r8, r2" + - + asm_text: "it gt" + - + asm_text: "shasxgt r4, r8, r2" + - + asm_text: "shasx r4, r8, r2" + - + asm_text: "it gt" + - + asm_text: "shasxgt r4, r8, r2" + - + asm_text: "shsax r4, r8, r2" + - + asm_text: "it gt" + - + asm_text: "shsaxgt r4, r8, r2" + - + asm_text: "shsax r4, r8, r2" + - + asm_text: "it gt" + - + asm_text: "shsaxgt r4, r8, r2" + - + asm_text: "shsub16 r4, r8, r2" + - + asm_text: "shsub8 r4, r8, r2" + - + asm_text: "itt gt" + - + asm_text: "shsub16gt r4, r8, r2" + - + asm_text: "shsub8gt r4, r8, r2" + - + asm_text: "smlabb r3, r1, r9, r0" + - + asm_text: "smlabt r5, r6, r4, r1" + - + asm_text: "smlatb r4, r2, r3, r2" + - + asm_text: "smlatt r8, r3, r8, r4" + - + asm_text: "itete gt" + - + asm_text: "smlabbgt r3, r1, r9, r0" + - + asm_text: "smlabtle r5, r6, r4, r1" + - + asm_text: "smlatbgt r4, r2, r3, r2" + - + asm_text: "smlattle r8, r3, r8, r4" + - + asm_text: "smlad r2, r3, r5, r8" + - + asm_text: "smladx r2, r3, r5, r8" + - + asm_text: "itt hi" + - + asm_text: "smladhi r2, r3, r5, r8" + - + asm_text: "smladxhi r2, r3, r5, r8" + - + asm_text: "smlal r2, r3, r5, r8" + - + asm_text: "it eq" + - + asm_text: "smlaleq r2, r3, r5, r8" + - + asm_text: "smlalbb r3, r1, r9, r0" + - + asm_text: "smlalbt r5, r6, r4, r1" + - + asm_text: "smlaltb r4, r2, r3, r2" + - + asm_text: "smlaltt r8, r3, r8, r4" + - + asm_text: "iteet ge" + - + asm_text: "smlalbbge r3, r1, r9, r0" + - + asm_text: "smlalbtlt r5, r6, r4, r1" + - + asm_text: "smlaltblt r4, r2, r3, r2" + - + asm_text: "smlalttge r8, r3, r8, r4" + - + asm_text: "smlald r2, r3, r5, r8" + - + asm_text: "smlaldx r2, r3, r5, r8" + - + asm_text: "ite eq" + - + asm_text: "smlaldeq r2, r3, r5, r8" + - + asm_text: "smlaldxne r2, r3, r5, r8" + - + asm_text: "smlawb r2, r3, r10, r8" + - + asm_text: "smlawt r8, r3, r5, r9" + - + asm_text: "ite eq" + - + asm_text: "smlawbeq r2, r7, r5, r8" + - + asm_text: "smlawtne r1, r3, r0, r8" + - + asm_text: "smlsd r2, r3, r5, r8" + - + asm_text: "smlsdx r2, r3, r5, r8" + - + asm_text: "ite le" + - + asm_text: "smlsdle r2, r3, r5, r8" + - + asm_text: "smlsdxgt r2, r3, r5, r8" + - + asm_text: "smlsld r2, r9, r5, r1" + - + asm_text: "smlsldx r4, r11, r2, r8" + - + asm_text: "ite ge" + - + asm_text: "smlsldge r8, r2, r5, r6" + - + asm_text: "smlsldxlt r1, r0, r3, r8" + - + asm_text: "smmla r1, r2, r3, r4" + - + asm_text: "smmlar r4, r3, r2, r1" + - + asm_text: "ite lo" + - + asm_text: "smmlalo r1, r2, r3, r4" + - + asm_text: "smmlarhs r4, r3, r2, r1" + - + asm_text: "smmls r1, r2, r3, r4" + - + asm_text: "smmlsr r4, r3, r2, r1" + - + asm_text: "ite lo" + - + asm_text: "smmlslo r1, r2, r3, r4" + - + asm_text: "smmlsrhs r4, r3, r2, r1" + - + asm_text: "smmul r2, r3, r4" + - + asm_text: "smmulr r3, r2, r1" + - + asm_text: "ite lo" + - + asm_text: "smmullo r2, r3, r4" + - + asm_text: "smmulrhs r3, r2, r1" + - + asm_text: "smuad r2, r3, r4" + - + asm_text: "smuadx r3, r2, r1" + - + asm_text: "ite lt" + - + asm_text: "smuadlt r2, r3, r4" + - + asm_text: "smuadxge r3, r2, r1" + - + asm_text: "smulbb r3, r9, r0" + - + asm_text: "smulbt r5, r4, r1" + - + asm_text: "smultb r4, r2, r2" + - + asm_text: "smultt r8, r3, r4" + - + asm_text: "itete ge" + - + asm_text: "smulbbge r1, r9, r0" + - + asm_text: "smulbtlt r5, r6, r4" + - + asm_text: "smultbge r2, r3, r2" + - + asm_text: "smulttlt r8, r3, r4" + - + asm_text: "smull r3, r9, r0, r1" + - + asm_text: "it eq" + - + asm_text: "smulleq r8, r3, r4, r5" + - + asm_text: "smulwb r3, r9, r0" + - + asm_text: "smulwt r3, r9, r2" + - + asm_text: "ite gt" + - + asm_text: "smulwbgt r3, r9, r0" + - + asm_text: "smulwtle r3, r9, r2" + - + asm_text: "smusd r3, r0, r1" + - + asm_text: "smusdx r3, r9, r2" + - + asm_text: "ite eq" + - + asm_text: "smusdeq r8, r3, r2" + - + asm_text: "smusdxne r7, r4, r3" + - + asm_text: "srsdb sp, #1" + - + asm_text: "srsia sp, #0" + - + asm_text: "srsdb sp!, #0x13" + - + asm_text: "srsia sp!, #2" + - + asm_text: "srsia sp, #0xa" + - + asm_text: "srsdb sp, #0x9" + - + asm_text: "srsia sp!, #5" + - + asm_text: "srsdb sp!, #5" + - + asm_text: "srsia sp, #5" + - + asm_text: "srsia sp!, #5" + - + asm_text: "srsdb sp, #1" + - + asm_text: "srsia sp, #0" + - + asm_text: "srsdb sp!, #0x13" + - + asm_text: "srsia sp!, #2" + - + asm_text: "srsia sp, #0xa" + - + asm_text: "srsdb sp, #0x9" + - + asm_text: "srsia sp!, #5" + - + asm_text: "srsdb sp!, #5" + - + asm_text: "srsia sp, #5" + - + asm_text: "srsia sp!, #5" + - + asm_text: "ssat r8, #1, r10" + - + asm_text: "ssat r8, #1, r10" + - + asm_text: "ssat r8, #1, r10, lsl #0x1f" + - + asm_text: "ssat r8, #1, r10, asr #1" + - + asm_text: "ssat16 r2, #1, r7" + - + asm_text: "ssat16 r3, #0x10, r5" + - + asm_text: "ssax r2, r3, r4" + - + asm_text: "it lt" + - + asm_text: "ssaxlt r2, r3, r4" + - + asm_text: "ssax r2, r3, r4" + - + asm_text: "it lt" + - + asm_text: "ssaxlt r2, r3, r4" + - + asm_text: "ssub16 r1, r0, r6" + - + asm_text: "ssub8 r9, r2, r4" + - + asm_text: "ite ne" + - + asm_text: "ssub16ne r5, r3, r2" + - + asm_text: "ssub8eq r5, r1, r2" + - + asm_text: "stc2 p0, c8, [r1, #4]" + - + asm_text: "stc2 p1, c7, [r2]" + - + asm_text: "stc2 p2, c6, [r3, #-0xe0]" + - + asm_text: "stc2 p3, c5, [r4, #-0x78]!" + - + asm_text: "stc2 p4, c4, [r5], #0x10" + - + asm_text: "stc2 p5, c3, [r6], #-0x48" + - + asm_text: "stc2l p6, c2, [r7, #4]" + - + asm_text: "stc2l p7, c1, [r8]" + - + asm_text: "stc2l p8, c0, [r9, #-0xe0]" + - + asm_text: "stc2l p9, c1, [r10, #-0x78]!" + - + asm_text: "stc2l p0, c2, [r11], #0x10" + - + asm_text: "stc2l p1, c3, [r12], #-0x48" + - + asm_text: "stc p12, c4, [r0, #4]" + - + asm_text: "stc p13, c5, [r1]" + - + asm_text: "stc p14, c6, [r2, #-0xe0]" + - + asm_text: "stc p15, c7, [r3, #-0x78]!" + - + asm_text: "stc p5, c8, [r4], #0x10" + - + asm_text: "stc p4, c9, [r5], #-0x48" + - + asm_text: "stcl p3, c10, [r6, #4]" + - + asm_text: "stcl p2, c11, [r7]" + - + asm_text: "stcl p1, c12, [r8, #-0xe0]" + - + asm_text: "stcl p0, c13, [r9, #-0x78]!" + - + asm_text: "stcl p6, c14, [r10], #0x10" + - + asm_text: "stcl p7, c15, [r11], #-0x48" + - + asm_text: "stc2 p2, c8, [r1], {25}" + - + asm_text: "stm.w r4, {r4, r5, r8, r9}" + - + asm_text: "stm.w r4, {r5, r6}" + - + asm_text: "stm.w r5!, {r3, r8}" + - + asm_text: "stm.w r4, {r4, r5, r8, r9}" + - + asm_text: "stm.w r4, {r5, r6}" + - + asm_text: "stm.w r5!, {r3, r8}" + - + asm_text: "stm.w r5!, {r1, r2}" + - + asm_text: "stm.w r2, {r1, r2}" + - + asm_text: "stm.w r4, {r4, r5, r8, r9}" + - + asm_text: "stm.w r4, {r5, r6}" + - + asm_text: "stm.w r5!, {r3, r8}" + - + asm_text: "stm.w r4, {r4, r5, r8, r9}" + - + asm_text: "stm.w r4, {r5, r6}" + - + asm_text: "stm.w r5!, {r3, r8}" + - + asm_text: "stm.w r5!, {r3, r8}" + - + asm_text: "stmdb r4, {r4, r5, r8, r9}" + - + asm_text: "stmdb r4, {r5, r6}" + - + asm_text: "stmdb r5!, {r3, r8}" + - + asm_text: "stm.w r5!, {r3, r8}" + - + asm_text: "stmdb r5, {r0, r1}" + - + asm_text: "str r5, [r5, #-4]" + - + asm_text: "str r5, [r6, #0x20]" + - + asm_text: "str.w r5, [r6, #0x21]" + - + asm_text: "str.w r5, [r6, #0x101]" + - + asm_text: "str.w pc, [r7, #0x101]" + - + asm_text: "str r2, [r4, #0xff]!" + - + asm_text: "str r8, [sp, #4]!" + - + asm_text: "str lr, [sp, #-4]!" + - + asm_text: "str r2, [r4], #0xff" + - + asm_text: "str r8, [sp], #4" + - + asm_text: "str lr, [sp], #-4" + - + asm_text: "str.w r1, [r8, r1]" + - + asm_text: "str.w r4, [r5, r2]" + - + asm_text: "str.w r6, [r0, r2, lsl #3]" + - + asm_text: "str.w r8, [r8, r2, lsl #2]" + - + asm_text: "str.w r7, [sp, r2, lsl #1]" + - + asm_text: "str.w r7, [sp, r2]" + - + asm_text: "strb r5, [r5, #-4]" + - + asm_text: "strb.w r5, [r6, #0x20]" + - + asm_text: "strb.w r5, [r6, #0x21]" + - + asm_text: "strb.w r5, [r6, #0x101]" + - + asm_text: "strb.w lr, [r7, #0x101]" + - + asm_text: "strb r5, [r8, #0xff]!" + - + asm_text: "strb r2, [r5, #4]!" + - + asm_text: "strb r1, [r4, #-4]!" + - + asm_text: "strb lr, [r3], #0xff" + - + asm_text: "strb r9, [r2], #4" + - + asm_text: "strb r3, [sp], #-4" + - + asm_text: "strb r4, [r8, #-0]!" + - + asm_text: "strb r1, [r0], #-0" + - + asm_text: "strb.w r1, [r8, r1]" + - + asm_text: "strb.w r4, [r5, r2]" + - + asm_text: "strb.w r6, [r0, r2, lsl #3]" + - + asm_text: "strb.w r8, [r8, r2, lsl #2]" + - + asm_text: "strb.w r7, [sp, r2, lsl #1]" + - + asm_text: "strb.w r7, [sp, r2]" + - + asm_text: "strbt r1, [r2]" + - + asm_text: "strbt r1, [r8]" + - + asm_text: "strbt r1, [r8, #3]" + - + asm_text: "strbt r1, [r8, #0xff]" + - + asm_text: "strd r3, r5, [r6, #0x18]" + - + asm_text: "strd r3, r5, [r6, #0x18]!" + - + asm_text: "strd r3, r5, [r6], #4" + - + asm_text: "strd r3, r5, [r6], #-8" + - + asm_text: "strd r3, r5, [r6]" + - + asm_text: "strd r8, r1, [r3]" + - + asm_text: "strd r0, r1, [r2, #-0]" + - + asm_text: "strd r0, r1, [r2, #-0]!" + - + asm_text: "strd r0, r1, [r2], #-0" + - + asm_text: "strd r0, r1, [r2, #0x100]" + - + asm_text: "strd r0, r1, [r2, #0x100]!" + - + asm_text: "strd r0, r1, [r2], #0x100" + - + asm_text: "strex r1, r8, [r4]" + - + asm_text: "strex r8, r2, [r4]" + - + asm_text: "strex r2, r12, [sp, #0x80]" + - + asm_text: "strexb r5, r1, [r7]" + - + asm_text: "strexh r9, r7, [r12]" + - + asm_text: "strexd r9, r3, r6, [r4]" + - + asm_text: "strh r5, [r5, #-4]" + - + asm_text: "strh r5, [r6, #0x20]" + - + asm_text: "strh.w r5, [r6, #0x21]" + - + asm_text: "strh.w r5, [r6, #0x101]" + - + asm_text: "strh.w lr, [r7, #0x101]" + - + asm_text: "strh r5, [r8, #0xff]!" + - + asm_text: "strh r2, [r5, #4]!" + - + asm_text: "strh r1, [r4, #-4]!" + - + asm_text: "strh lr, [r3], #0xff" + - + asm_text: "strh r9, [r2], #4" + - + asm_text: "strh r3, [sp], #-4" + - + asm_text: "strh.w r1, [r8, r1]" + - + asm_text: "strh.w r4, [r5, r2]" + - + asm_text: "strh.w r6, [r0, r2, lsl #3]" + - + asm_text: "strh.w r8, [r8, r2, lsl #2]" + - + asm_text: "strh.w r7, [sp, r2, lsl #1]" + - + asm_text: "strh.w r7, [sp, r2]" + - + asm_text: "strht r1, [r2]" + - + asm_text: "strht r1, [r8]" + - + asm_text: "strht r1, [r8, #3]" + - + asm_text: "strht r1, [r8, #0xff]" + - + asm_text: "strt r1, [r2]" + - + asm_text: "strt r1, [r8]" + - + asm_text: "strt r1, [r8, #3]" + - + asm_text: "strt r1, [r8, #0xff]" + - + asm_text: "itet eq" + - + asm_text: "subeq r1, r2, #4" + - + asm_text: "subwne r5, r3, #0x3ff" + - + asm_text: "subweq r4, r5, #0x125" + - + asm_text: "sub.w r2, sp, #0x400" + - + asm_text: "sub.w r2, r8, #0xff00" + - + asm_text: "subw r2, r3, #0x101" + - + asm_text: "subw r2, r3, #0x101" + - + asm_text: "sub.w r12, r6, #0x100" + - + asm_text: "subw r12, r6, #0x100" + - + asm_text: "subs.w r1, r2, #0x1f0" + - + asm_text: "sub.w r2, r2, #1" + - + asm_text: "sub.w r0, r0, #0x20" + - + asm_text: "subs r2, #0x38" + - + asm_text: "subs r2, #0x38" + - + asm_text: "sub.w r4, r5, r6" + - + asm_text: "sub.w r4, r5, r6, lsl #5" + - + asm_text: "sub.w r4, r5, r6, lsr #5" + - + asm_text: "sub.w r4, r5, r6, lsr #5" + - + asm_text: "sub.w r4, r5, r6, asr #5" + - + asm_text: "sub.w r4, r5, r6, ror #5" + - + asm_text: "sub.w r5, r2, r12, rrx" + - + asm_text: "sub.w r2, sp, r12" + - + asm_text: "sub.w sp, sp, r12" + - + asm_text: "sub.w sp, sp, r12" + - + asm_text: "sub.w r2, sp, r12" + - + asm_text: "sub.w sp, sp, r12" + - + asm_text: "sub.w sp, sp, r12" + - + asm_text: "svc #0" + - + asm_text: "it eq" + - + asm_text: "svceq #0xff" + - + asm_text: "it ne" + - + asm_text: "svcne #0x21" + - + asm_text: "itt eq" + - + asm_text: "svceq #0" + - + asm_text: "svceq #1" + - + asm_text: "sxtab r2, r3, r4" + - + asm_text: "sxtab r4, r5, r6" + - + asm_text: "it lt" + - + asm_text: "sxtablt r6, r2, r9, ror #8" + - + asm_text: "sxtab r5, r1, r4, ror #0x10" + - + asm_text: "sxtab r7, r8, r3, ror #0x18" + - + asm_text: "sxtab16 r6, r2, r7" + - + asm_text: "sxtab16 r3, r5, r8, ror #8" + - + asm_text: "sxtab16 r3, r2, r1, ror #0x10" + - + asm_text: "ite ne" + - + asm_text: "sxtab16ne r0, r1, r4" + - + asm_text: "sxtab16eq r1, r2, r3, ror #0x18" + - + asm_text: "sxtah r1, r3, r9" + - + asm_text: "sxtah r3, r8, r3, ror #8" + - + asm_text: "sxtah r9, r3, r3, ror #0x18" + - + asm_text: "ite hi" + - + asm_text: "sxtahhi r6, r1, r6" + - + asm_text: "sxtahls r2, r2, r4, ror #0x10" + - + asm_text: "sxtb r5, r6" + - + asm_text: "sxtb.w r6, r9, ror #8" + - + asm_text: "sxtb.w r8, r3, ror #0x18" + - + asm_text: "ite ge" + - + asm_text: "sxtbge r2, r4" + - + asm_text: "sxtblt.w r5, r1, ror #0x10" + - + asm_text: "sxtb.w r7, r8" + - + asm_text: "sxtb16 r1, r4" + - + asm_text: "sxtb16 r6, r7" + - + asm_text: "sxtb16 r3, r1, ror #0x10" + - + asm_text: "ite hs" + - + asm_text: "sxtb16hs r3, r5, ror #8" + - + asm_text: "sxtb16lo r2, r3, ror #0x18" + - + asm_text: "sxth r1, r6" + - + asm_text: "sxth.w r3, r8, ror #8" + - + asm_text: "sxth.w r9, r3, ror #0x18" + - + asm_text: "itt ne" + - + asm_text: "sxthne.w r3, r9" + - + asm_text: "sxthne.w r2, r2, ror #0x10" + - + asm_text: "sxth.w r7, r8" + - + asm_text: "sxtb r5, r6" + - + asm_text: "sxtb.w r6, r9, ror #8" + - + asm_text: "sxtb.w r8, r3, ror #0x18" + - + asm_text: "ite ge" + - + asm_text: "sxtbge r2, r4" + - + asm_text: "sxtblt.w r5, r1, ror #0x10" + - + asm_text: "sxtb16 r1, r4" + - + asm_text: "sxtb16 r6, r7" + - + asm_text: "sxtb16 r3, r1, ror #0x10" + - + asm_text: "ite hs" + - + asm_text: "sxtb16hs r3, r5, ror #8" + - + asm_text: "sxtb16lo r2, r3, ror #0x18" + - + asm_text: "sxth r1, r6" + - + asm_text: "sxth.w r3, r8, ror #8" + - + asm_text: "sxth.w r9, r3, ror #0x18" + - + asm_text: "itt ne" + - + asm_text: "sxthne.w r3, r9" + - + asm_text: "sxthne.w r2, r2, ror #0x10" + - + asm_text: "tbb [r3, r8]" + - + asm_text: "tbh [r3, r8, lsl #1]" + - + asm_text: "it eq" + - + asm_text: "tbbeq [r3, r8]" + - + asm_text: "it hs" + - + asm_text: "tbhhs [r3, r8, lsl #1]" + - + asm_text: "teq.w r5, #0xf000" + - + asm_text: "teq.w r4, r5" + - + asm_text: "teq.w r4, r5, lsl #5" + - + asm_text: "teq.w r4, r5, lsr #5" + - + asm_text: "teq.w r4, r5, lsr #5" + - + asm_text: "teq.w r4, r5, asr #5" + - + asm_text: "teq.w r4, r5, ror #5" + - + asm_text: "tst.w r5, #0xf000" + - + asm_text: "tst r2, r5" + - + asm_text: "tst.w r3, r12, lsl #5" + - + asm_text: "tst.w r4, r11, lsr #4" + - + asm_text: "tst.w r5, r10, lsr #0xc" + - + asm_text: "tst.w r6, r9, asr #0x1e" + - + asm_text: "tst.w r7, r8, ror #2" + - + asm_text: "uadd16 r1, r2, r3" + - + asm_text: "uadd8 r1, r2, r3" + - + asm_text: "ite gt" + - + asm_text: "uadd16gt r1, r2, r3" + - + asm_text: "uadd8le r1, r2, r3" + - + asm_text: "uasx r9, r12, r0" + - + asm_text: "it eq" + - + asm_text: "uasxeq r9, r12, r0" + - + asm_text: "uasx r9, r12, r0" + - + asm_text: "it eq" + - + asm_text: "uasxeq r9, r12, r0" + - + asm_text: "ubfx r4, r5, #0x10, #1" + - + asm_text: "it gt" + - + asm_text: "ubfxgt r4, r5, #0x10, #0x10" + - + asm_text: "uhadd16 r4, r8, r2" + - + asm_text: "uhadd8 r4, r8, r2" + - + asm_text: "itt gt" + - + asm_text: "uhadd16gt r4, r8, r2" + - + asm_text: "uhadd8gt r4, r8, r2" + - + asm_text: "uhasx r4, r1, r5" + - + asm_text: "uhsax r5, r6, r6" + - + asm_text: "itt gt" + - + asm_text: "uhasxgt r6, r9, r8" + - + asm_text: "uhsaxgt r7, r8, r12" + - + asm_text: "uhasx r4, r1, r5" + - + asm_text: "uhsax r5, r6, r6" + - + asm_text: "itt gt" + - + asm_text: "uhasxgt r6, r9, r8" + - + asm_text: "uhsaxgt r7, r8, r12" + - + asm_text: "uhsub16 r5, r8, r3" + - + asm_text: "uhsub8 r1, r7, r6" + - + asm_text: "itt lt" + - + asm_text: "uhsub16lt r4, r9, r12" + - + asm_text: "uhsub8lt r3, r1, r5" + - + asm_text: "umaal r3, r4, r5, r6" + - + asm_text: "it lt" + - + asm_text: "umaallt r3, r4, r5, r6" + - + asm_text: "umlal r2, r4, r6, r8" + - + asm_text: "it gt" + - + asm_text: "umlalgt r6, r1, r2, r6" + - + asm_text: "umull r2, r4, r6, r8" + - + asm_text: "it gt" + - + asm_text: "umullgt r6, r1, r2, r6" + - + asm_text: "uqadd16 r1, r2, r3" + - + asm_text: "uqadd8 r3, r4, r8" + - + asm_text: "ite gt" + - + asm_text: "uqadd16gt r4, r7, r9" + - + asm_text: "uqadd8le r8, r1, r2" + - + asm_text: "uqasx r1, r2, r3" + - + asm_text: "uqsax r3, r4, r8" + - + asm_text: "ite gt" + - + asm_text: "uqasxgt r4, r7, r9" + - + asm_text: "uqsaxle r8, r1, r2" + - + asm_text: "uqasx r1, r2, r3" + - + asm_text: "uqsax r3, r4, r8" + - + asm_text: "ite gt" + - + asm_text: "uqasxgt r4, r7, r9" + - + asm_text: "uqsaxle r8, r1, r2" + - + asm_text: "uqsub8 r8, r2, r9" + - + asm_text: "uqsub16 r1, r9, r7" + - + asm_text: "ite gt" + - + asm_text: "uqsub8gt r3, r1, r6" + - + asm_text: "uqsub16le r4, r6, r4" + - + asm_text: "usad8 r1, r9, r7" + - + asm_text: "usada8 r8, r2, r9, r12" + - + asm_text: "ite gt" + - + asm_text: "usada8gt r3, r1, r6, r9" + - + asm_text: "usad8le r4, r6, r4" + - + asm_text: "usat r8, #1, r10" + - + asm_text: "usat r8, #4, r10" + - + asm_text: "usat r8, #5, r10, lsl #0x1f" + - + asm_text: "usat r8, #0x10, r10, asr #1" + - + asm_text: "usat16 r2, #2, r7" + - + asm_text: "usat16 r3, #0xf, r5" + - + asm_text: "usax r2, r3, r4" + - + asm_text: "it ne" + - + asm_text: "usaxne r6, r1, r9" + - + asm_text: "usax r2, r3, r4" + - + asm_text: "it ne" + - + asm_text: "usaxne r6, r1, r9" + - + asm_text: "usub16 r4, r2, r7" + - + asm_text: "usub8 r1, r8, r5" + - + asm_text: "ite hi" + - + asm_text: "usub16hi r1, r1, r3" + - + asm_text: "usub8ls r9, r2, r3" + - + asm_text: "uxtab r2, r3, r4" + - + asm_text: "uxtab r4, r5, r6" + - + asm_text: "it lt" + - + asm_text: "uxtablt r6, r2, r9, ror #8" + - + asm_text: "uxtab r5, r1, r4, ror #0x10" + - + asm_text: "uxtab r7, r8, r3, ror #0x18" + - + asm_text: "it ge" + - + asm_text: "uxtab16ge r0, r1, r4" + - + asm_text: "uxtab16 r6, r2, r7" + - + asm_text: "uxtab16 r3, r5, r8, ror #8" + - + asm_text: "uxtab16 r3, r2, r1, ror #0x10" + - + asm_text: "it eq" + - + asm_text: "uxtab16eq r1, r2, r3, ror #0x18" + - + asm_text: "uxtah r1, r3, r9" + - + asm_text: "it hi" + - + asm_text: "uxtahhi r6, r1, r6" + - + asm_text: "uxtah r3, r8, r3, ror #8" + - + asm_text: "it lo" + - + asm_text: "uxtahlo r2, r2, r4, ror #0x10" + - + asm_text: "uxtah r9, r3, r3, ror #0x18" + - + asm_text: "it ge" + - + asm_text: "uxtbge r2, r4" + - + asm_text: "uxtb r5, r6" + - + asm_text: "uxtb.w r6, r9, ror #8" + - + asm_text: "it lo" + - + asm_text: "uxtblo.w r5, r1, ror #0x10" + - + asm_text: "uxtb.w r8, r3, ror #0x18" + - + asm_text: "uxtb.w r7, r8" + - + asm_text: "uxtb16 r1, r4" + - + asm_text: "uxtb16 r6, r7" + - + asm_text: "it hs" + - + asm_text: "uxtb16hs r3, r5, ror #8" + - + asm_text: "uxtb16 r3, r1, ror #0x10" + - + asm_text: "it ge" + - + asm_text: "uxtb16ge r2, r3, ror #0x18" + - + asm_text: "it ne" + - + asm_text: "uxthne.w r3, r9" + - + asm_text: "uxth r1, r6" + - + asm_text: "uxth.w r3, r8, ror #8" + - + asm_text: "it le" + - + asm_text: "uxthle.w r2, r2, ror #0x10" + - + asm_text: "uxth.w r9, r3, ror #0x18" + - + asm_text: "uxth.w r7, r8" + - + asm_text: "wfe" + - + asm_text: "wfi" + - + asm_text: "yield" + - + asm_text: "itet lt" + - + asm_text: "wfelt" + - + asm_text: "wfige" + - + asm_text: "yieldlt" + - + asm_text: "sev.w" + - + asm_text: "wfi.w" + - + asm_text: "wfe.w" + - + asm_text: "yield.w" + - + asm_text: "nop.w" + - + asm_text: "sev" + - + asm_text: "wfi" + - + asm_text: "wfe" + - + asm_text: "yield" + - + asm_text: "nop" + - + asm_text: "itet lt" + - + asm_text: "hintlt #0xf" + - + asm_text: "hintge.w #0x10" + - + asm_text: "hintlt.w #0xef" + - + asm_text: "hint #7" + - + asm_text: "hint.w #7" + - + asm_text: "ldrb.w r11, [pc, #0x16]" + - + asm_text: "ldrh.w r11, [pc, #0x16]" + - + asm_text: "ldrsb.w r11, [pc, #0x16]" + - + asm_text: "ldrsh.w r11, [pc, #0x16]" + - + asm_text: "ldr.w r11, [pc, #0x16]" + - + asm_text: "ldrb.w r11, [pc, #0x16]" + - + asm_text: "ldrh.w r11, [pc, #0x16]" + - + asm_text: "ldrsb.w r11, [pc, #0x16]" + - + asm_text: "ldrsh.w r11, [pc, #0x16]" + - + asm_text: "ldr.w r11, [pc, #-0x16]" + - + asm_text: "ldrb.w r11, [pc, #-0x16]" + - + asm_text: "ldrh.w r11, [pc, #-0x16]" + - + asm_text: "ldrsb.w r11, [pc, #-0x16]" + - + asm_text: "ldrsh.w r11, [pc, #-0x16]" + - + asm_text: "ldr.w r11, [pc, #-0x16]" + - + asm_text: "ldrb.w r11, [pc, #-0x16]" + - + asm_text: "ldrh.w r11, [pc, #-0x16]" + - + asm_text: "ldrsb.w r11, [pc, #-0x16]" + - + asm_text: "ldrsh.w r11, [pc, #-0x16]" + - + asm_text: "ldr r1, [pc, #0xc]" + - + asm_text: "subs pc, lr, #4" diff --git a/thirdparty/capstone/tests/MC/ARM/bfloat16-a32.s.yaml b/thirdparty/capstone/tests/MC/ARM/bfloat16-a32.s.yaml new file mode 100644 index 0000000..4acde4f --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/bfloat16-a32.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x3d, 0x04, 0xfc ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vdot.bf16 d3, d4, d5" diff --git a/thirdparty/capstone/tests/MC/ARM/bfloat16-t32.s.yaml b/thirdparty/capstone/tests/MC/ARM/bfloat16-t32.s.yaml new file mode 100644 index 0000000..08354ff --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/bfloat16-t32.s.yaml @@ -0,0 +1,14 @@ +test_cases: + - + input: + bytes: [ 0xb6, 0xff, 0x46, 0x16, 0x18, 0xbf, 0xf3, 0xee, 0xe1, 0x09 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcvt.bf16.f32 d1, q3" + - + asm_text: "it ne" + - + asm_text: "vcvtt.bf16.f32 s1, s3" diff --git a/thirdparty/capstone/tests/MC/ARM/cde-integer.s.yaml b/thirdparty/capstone/tests/MC/ARM/cde-integer.s.yaml new file mode 100644 index 0000000..2a9016b --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/cde-integer.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x06, 0xbf ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "itte eq" diff --git a/thirdparty/capstone/tests/MC/ARM/cde-vec-pred.s.yaml b/thirdparty/capstone/tests/MC/ARM/cde-vec-pred.s.yaml new file mode 100644 index 0000000..79161f7 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/cde-vec-pred.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xfe, 0x00, 0xef ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vptete.i8 eq, q0, q0" diff --git a/thirdparty/capstone/tests/MC/ARM/clrm-asm.s.yaml b/thirdparty/capstone/tests/MC/ARM/clrm-asm.s.yaml new file mode 100644 index 0000000..3f07e55 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/clrm-asm.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x9f, 0xe8, 0x0f, 0x00, 0x9f, 0xe8, 0x1e, 0x00, 0x9f, 0xe8, 0xff, 0xdf, 0x9f, 0xe8, 0x00, 0xc0, 0x9f, 0xe8, 0x03, 0x80, 0x9f, 0xe8, 0x1f, 0xc0 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "clrm {r0, r1, r2, r3}" + - + asm_text: "clrm {r1, r2, r3, r4}" + - + asm_text: "clrm {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr, apsr}" + - + asm_text: "clrm {lr, apsr}" + - + asm_text: "clrm {r0, r1, apsr}" + - + asm_text: "clrm {r0, r1, r2, r3, r4, lr, apsr}" diff --git a/thirdparty/capstone/tests/MC/ARM/cps.s.yaml b/thirdparty/capstone/tests/MC/ARM/cps.s.yaml new file mode 100644 index 0000000..0ea21d9 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/cps.s.yaml @@ -0,0 +1,14 @@ +test_cases: + - + input: + bytes: [ 0x61, 0xb6, 0xaf, 0xf3, 0x43, 0x85, 0xaf, 0xf3, 0x00, 0x81 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "cpsie f" + - + asm_text: "cpsie i, #3" + - + asm_text: "cps #0" diff --git a/thirdparty/capstone/tests/MC/ARM/crc32-thumb.s.yaml b/thirdparty/capstone/tests/MC/ARM/crc32-thumb.s.yaml new file mode 100644 index 0000000..782489e --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/crc32-thumb.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xc1, 0xfa, 0x82, 0xf0, 0xc1, 0xfa, 0x92, 0xf0, 0xc1, 0xfa, 0xa2, 0xf0, 0xd1, 0xfa, 0x82, 0xf0, 0xd1, 0xfa, 0x92, 0xf0, 0xd1, 0xfa, 0xa2, 0xf0 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "crc32b r0, r1, r2" + - + asm_text: "crc32h r0, r1, r2" + - + asm_text: "crc32w r0, r1, r2" + - + asm_text: "crc32cb r0, r1, r2" + - + asm_text: "crc32ch r0, r1, r2" + - + asm_text: "crc32cw r0, r1, r2" diff --git a/thirdparty/capstone/tests/MC/ARM/crc32.s.yaml b/thirdparty/capstone/tests/MC/ARM/crc32.s.yaml new file mode 100644 index 0000000..4b630d1 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/crc32.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x42, 0x00, 0x01, 0xe1, 0x42, 0x00, 0x21, 0xe1, 0x42, 0x00, 0x41, 0xe1, 0x42, 0x02, 0x01, 0xe1, 0x42, 0x02, 0x21, 0xe1, 0x42, 0x02, 0x41, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "crc32b r0, r1, r2" + - + asm_text: "crc32h r0, r1, r2" + - + asm_text: "crc32w r0, r1, r2" + - + asm_text: "crc32cb r0, r1, r2" + - + asm_text: "crc32ch r0, r1, r2" + - + asm_text: "crc32cw r0, r1, r2" diff --git a/thirdparty/capstone/tests/MC/ARM/dot-req.s.yaml b/thirdparty/capstone/tests/MC/ARM/dot-req.s.yaml new file mode 100644 index 0000000..f9be9d9 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/dot-req.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x05, 0xb0, 0xa0, 0xe1, 0x06, 0x10, 0xa0, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "mov r11, r5" + - + asm_text: "mov r1, r6" diff --git a/thirdparty/capstone/tests/MC/ARM/fconst.s.yaml b/thirdparty/capstone/tests/MC/ARM/fconst.s.yaml new file mode 100644 index 0000000..430f726 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/fconst.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x2a, 0xb0, 0xee, 0x00, 0x2a, 0xb7, 0xee, 0x00, 0x3b, 0xb0, 0xee, 0x00, 0x3b, 0xb7, 0xee, 0x01, 0x2a, 0xf0, 0x1e, 0x00, 0x2a, 0xf2, 0xce, 0x03, 0x2b, 0xb0, 0xbe, 0x00, 0x2b, 0xb4, 0xae ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmov.f32 s4, #2.000000e+00" + - + asm_text: "vmov.f32 s4, #1.000000e+00" + - + asm_text: "vmov.f64 d3, #2.000000e+00" + - + asm_text: "vmov.f64 d3, #1.000000e+00" + - + asm_text: "vmovne.f32 s5, #2.125000e+00" + - + asm_text: "vmovgt.f32 s5, #8.000000e+00" + - + asm_text: "vmovlt.f64 d2, #2.375000e+00" + - + asm_text: "vmovge.f64 d2, #1.250000e-01" diff --git a/thirdparty/capstone/tests/MC/ARM/fp-armv8.s.yaml b/thirdparty/capstone/tests/MC/ARM/fp-armv8.s.yaml new file mode 100644 index 0000000..0da54db --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/fp-armv8.s.yaml @@ -0,0 +1,110 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3b, 0xb2, 0xee, 0xcc, 0x2b, 0xf3, 0xee, 0x60, 0x3b, 0xb2, 0xee, 0x41, 0x2b, 0xb3, 0xee, 0xe0, 0x3b, 0xb2, 0xae, 0xcc, 0x2b, 0xf3, 0xce, 0x60, 0x3b, 0xb2, 0x0e, 0x41, 0x2b, 0xb3, 0xbe, 0xe1, 0x1a, 0xbc, 0xfe, 0xc3, 0x1b, 0xbc, 0xfe, 0xeb, 0x3a, 0xbd, 0xfe, 0xe7, 0x3b, 0xbd, 0xfe, 0xc2, 0x0a, 0xbe, 0xfe, 0xc4, 0x0b, 0xbe, 0xfe, 0xc4, 0x8a, 0xff, 0xfe, 0xc8, 0x8b, 0xff, 0xfe, 0x61, 0x1a, 0xbc, 0xfe, 0x43, 0x1b, 0xbc, 0xfe, 0x6b, 0x3a, 0xbd, 0xfe, 0x67, 0x3b, 0xbd, 0xfe, 0x42, 0x0a, 0xbe, 0xfe, 0x44, 0x0b, 0xbe, 0xfe, 0x44, 0x8a, 0xff, 0xfe, 0x48, 0x8b, 0xff, 0xfe, 0xab, 0x2a, 0x20, 0xfe, 0xa7, 0xeb, 0x6f, 0xfe, 0x80, 0x0a, 0x30, 0xfe, 0x24, 0x5b, 0x3a, 0xfe, 0x2b, 0xfa, 0x0e, 0xfe, 0x08, 0x2b, 0x04, 0xfe, 0x07, 0xaa, 0x58, 0xfe, 0x2f, 0x0b, 0x11, 0xfe, 0x00, 0x2a, 0xc6, 0xfe, 0xae, 0x5b, 0x86, 0xfe, 0x46, 0x0a, 0x80, 0xfe, 0x49, 0x4b, 0x86, 0xfe, 0xcc, 0x3b, 0xb6, 0xae, 0xcc, 0x1a, 0xf6, 0xee, 0x40, 0x5b, 0xb6, 0xbe, 0x64, 0x0a, 0xb6, 0xee, 0x6e, 0xcb, 0xf7, 0x0e, 0x47, 0x5a, 0xb7, 0x6e, 0x44, 0x3b, 0xb8, 0xfe, 0x60, 0x6a, 0xb8, 0xfe, 0x44, 0x3b, 0xb9, 0xfe, 0x60, 0x6a, 0xb9, 0xfe, 0x44, 0x3b, 0xba, 0xfe, 0x60, 0x6a, 0xba, 0xfe, 0x44, 0x3b, 0xbb, 0xfe, 0x60, 0x6a, 0xbb, 0xfe, 0x10, 0xda, 0xf5, 0xee ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vcvtt.f64.f16 d3, s1" + - + asm_text: "vcvtt.f16.f64 s5, d12" + - + asm_text: "vcvtb.f64.f16 d3, s1" + - + asm_text: "vcvtb.f16.f64 s4, d1" + - + asm_text: "vcvttge.f64.f16 d3, s1" + - + asm_text: "vcvttgt.f16.f64 s5, d12" + - + asm_text: "vcvtbeq.f64.f16 d3, s1" + - + asm_text: "vcvtblt.f16.f64 s4, d1" + - + asm_text: "vcvta.s32.f32 s2, s3" + - + asm_text: "vcvta.s32.f64 s2, d3" + - + asm_text: "vcvtn.s32.f32 s6, s23" + - + asm_text: "vcvtn.s32.f64 s6, d23" + - + asm_text: "vcvtp.s32.f32 s0, s4" + - + asm_text: "vcvtp.s32.f64 s0, d4" + - + asm_text: "vcvtm.s32.f32 s17, s8" + - + asm_text: "vcvtm.s32.f64 s17, d8" + - + asm_text: "vcvta.u32.f32 s2, s3" + - + asm_text: "vcvta.u32.f64 s2, d3" + - + asm_text: "vcvtn.u32.f32 s6, s23" + - + asm_text: "vcvtn.u32.f64 s6, d23" + - + asm_text: "vcvtp.u32.f32 s0, s4" + - + asm_text: "vcvtp.u32.f64 s0, d4" + - + asm_text: "vcvtm.u32.f32 s17, s8" + - + asm_text: "vcvtm.u32.f64 s17, d8" + - + asm_text: "vselge.f32 s4, s1, s23" + - + asm_text: "vselge.f64 d30, d31, d23" + - + asm_text: "vselgt.f32 s0, s1, s0" + - + asm_text: "vselgt.f64 d5, d10, d20" + - + asm_text: "vseleq.f32 s30, s28, s23" + - + asm_text: "vseleq.f64 d2, d4, d8" + - + asm_text: "vselvs.f32 s21, s16, s14" + - + asm_text: "vselvs.f64 d0, d1, d31" + - + asm_text: "vmaxnm.f32 s5, s12, s0" + - + asm_text: "vmaxnm.f64 d5, d22, d30" + - + asm_text: "vminnm.f32 s0, s0, s12" + - + asm_text: "vminnm.f64 d4, d6, d9" + - + asm_text: "vrintzge.f64 d3, d12" + - + asm_text: "vrintz.f32 s3, s24" + - + asm_text: "vrintrlt.f64 d5, d0" + - + asm_text: "vrintr.f32 s0, s9" + - + asm_text: "vrintxeq.f64 d28, d30" + - + asm_text: "vrintxvs.f32 s10, s14" + - + asm_text: "vrinta.f64 d3, d4" + - + asm_text: "vrinta.f32 s12, s1" + - + asm_text: "vrintn.f64 d3, d4" + - + asm_text: "vrintn.f32 s12, s1" + - + asm_text: "vrintp.f64 d3, d4" + - + asm_text: "vrintp.f32 s12, s1" + - + asm_text: "vrintm.f64 d3, d4" + - + asm_text: "vrintm.f32 s12, s1" + - + asm_text: "vmrs sp, mvfr2" diff --git a/thirdparty/capstone/tests/MC/ARM/fpv8.s.yaml b/thirdparty/capstone/tests/MC/ARM/fpv8.s.yaml new file mode 100644 index 0000000..ad0e685 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/fpv8.s.yaml @@ -0,0 +1,78 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x0b, 0x71, 0xee, 0xe0, 0x0b, 0x71, 0xee, 0xa0, 0x0b, 0xc1, 0xee, 0x07, 0x5b, 0x85, 0xee, 0xa0, 0x0b, 0x61, 0xee, 0xa1, 0x4b, 0x64, 0xee, 0xe0, 0x0b, 0x61, 0xee, 0xe0, 0x1b, 0xf4, 0xee, 0xc0, 0x0b, 0xf5, 0xee, 0xe0, 0x0b, 0xf0, 0xee, 0xe0, 0x0b, 0xb7, 0xee, 0xc0, 0x0a, 0xf7, 0xee, 0x60, 0x0b, 0xf1, 0xee, 0xe0, 0x0b, 0xf1, 0xee, 0xc0, 0x0b, 0xf8, 0xee, 0x40, 0x0b, 0xf8, 0xee, 0xe0, 0x0b, 0xbd, 0xee, 0xe0, 0x0b, 0xbc, 0xee, 0xa1, 0x0b, 0x42, 0xee, 0xe1, 0x0b, 0x42, 0xee, 0xe1, 0x0b, 0x52, 0xee, 0xa1, 0x0b, 0x52, 0xee, 0x60, 0x0b, 0xf1, 0x1e, 0x08, 0x0b, 0xf0, 0xee, 0x08, 0x0b, 0xf8, 0xee, 0x40, 0x0b, 0xbd, 0xee, 0x40, 0x0b, 0xbc, 0xee, 0xc0, 0x0b, 0xba, 0xee, 0x40, 0x0b, 0xba, 0xee, 0xc0, 0x4b, 0xfb, 0xee, 0x40, 0x7b, 0xfb, 0xee, 0xc0, 0x2b, 0xbe, 0xee, 0x40, 0xfb, 0xbe, 0xee, 0xc0, 0x4b, 0xff, 0xee, 0x40, 0x7b, 0xff, 0xee ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vadd.f64 d16, d17, d16" + - + asm_text: "vsub.f64 d16, d17, d16" + - + asm_text: "vdiv.f64 d16, d17, d16" + - + asm_text: "vdiv.f64 d5, d5, d7" + - + asm_text: "vmul.f64 d16, d17, d16" + - + asm_text: "vmul.f64 d20, d20, d17" + - + asm_text: "vnmul.f64 d16, d17, d16" + - + asm_text: "vcmpe.f64 d17, d16" + - + asm_text: "vcmpe.f64 d16, #0" + - + asm_text: "vabs.f64 d16, d16" + - + asm_text: "vcvt.f32.f64 s0, d16" + - + asm_text: "vcvt.f64.f32 d16, s0" + - + asm_text: "vneg.f64 d16, d16" + - + asm_text: "vsqrt.f64 d16, d16" + - + asm_text: "vcvt.f64.s32 d16, s0" + - + asm_text: "vcvt.f64.u32 d16, s0" + - + asm_text: "vcvt.s32.f64 s0, d16" + - + asm_text: "vcvt.u32.f64 s0, d16" + - + asm_text: "vmla.f64 d16, d18, d17" + - + asm_text: "vmls.f64 d16, d18, d17" + - + asm_text: "vnmla.f64 d16, d18, d17" + - + asm_text: "vnmls.f64 d16, d18, d17" + - + asm_text: "vnegne.f64 d16, d16" + - + asm_text: "vmov.f64 d16, #3.000000e+00" + - + asm_text: "vmov.f64 d16, #-3.000000e+00" + - + asm_text: "vcvtr.s32.f64 s0, d0" + - + asm_text: "vcvtr.u32.f64 s0, d0" + - + asm_text: "vcvt.f64.s32 d0, d0, #32" + - + asm_text: "vcvt.f64.s16 d0, d0, #16" + - + asm_text: "vcvt.f64.u32 d20, d20, #32" + - + asm_text: "vcvt.f64.u16 d23, d23, #16" + - + asm_text: "vcvt.s32.f64 d2, d2, #32" + - + asm_text: "vcvt.s16.f64 d15, d15, #16" + - + asm_text: "vcvt.u32.f64 d20, d20, #32" + - + asm_text: "vcvt.u16.f64 d23, d23, #16" diff --git a/thirdparty/capstone/tests/MC/ARM/gas-compl-copr-reg.s.yaml b/thirdparty/capstone/tests/MC/ARM/gas-compl-copr-reg.s.yaml new file mode 100644 index 0000000..7b77861 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/gas-compl-copr-reg.s.yaml @@ -0,0 +1,16 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x4c, 0x90, 0xed, 0x38, 0x6e, 0x02, 0xed, 0x01, 0x4c, 0x90, 0xed, 0x38, 0x6e, 0x02, 0xed ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldc p12, c4, [r0, #4]" + - + asm_text: "stc p14, c6, [r2, #-0xe0]" + - + asm_text: "ldc p12, c4, [r0, #4]" + - + asm_text: "stc p14, c6, [r2, #-0xe0]" diff --git a/thirdparty/capstone/tests/MC/ARM/idiv-thumb.s.yaml b/thirdparty/capstone/tests/MC/ARM/idiv-thumb.s.yaml new file mode 100644 index 0000000..6e2933b --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/idiv-thumb.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x92, 0xfb, 0xf3, 0xf1, 0xb4, 0xfb, 0xf5, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "sdiv r1, r2, r3" + - + asm_text: "udiv r3, r4, r5" diff --git a/thirdparty/capstone/tests/MC/ARM/idiv.s.yaml b/thirdparty/capstone/tests/MC/ARM/idiv.s.yaml new file mode 100644 index 0000000..6cc10c7 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/idiv.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x12, 0xf3, 0x11, 0xe7, 0x14, 0xf5, 0x33, 0xe7 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "sdiv r1, r2, r3" + - + asm_text: "udiv r3, r4, r5" diff --git a/thirdparty/capstone/tests/MC/ARM/implicit-it-generation.s.yaml b/thirdparty/capstone/tests/MC/ARM/implicit-it-generation.s.yaml new file mode 100644 index 0000000..6ddc973 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/implicit-it-generation.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x30, 0x10, 0xf1, 0x01, 0x00, 0x80, 0xe0, 0x00, 0xf0, 0x00, 0xbc, 0x02, 0xd0, 0x00, 0xf0, 0x80, 0x80, 0x02, 0xe0, 0x80, 0xe0, 0x00, 0xf0, 0x00, 0xbc, 0x02, 0xdc, 0x00, 0xf3, 0x80, 0x80 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "adds r0, #1" + - + asm_text: "adds.w r0, r0, #1" + - + asm_text: "b #0x100" + - + asm_text: "b.w #0x800" + - + asm_text: "beq #4" + - + asm_text: "beq.w #0x100" + - + asm_text: "b #4" + - + asm_text: "b #0x100" + - + asm_text: "b.w #0x800" + - + asm_text: "bgt #4" + - + asm_text: "bgt.w #0x100" diff --git a/thirdparty/capstone/tests/MC/ARM/ldrd-strd-gnu-arm.s.yaml b/thirdparty/capstone/tests/MC/ARM/ldrd-strd-gnu-arm.s.yaml new file mode 100644 index 0000000..230eabd --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/ldrd-strd-gnu-arm.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xd0, 0x02, 0xea, 0xe1, 0xd0, 0x02, 0xca, 0xe0, 0xd0, 0x02, 0xca, 0xe1, 0xf0, 0x02, 0xea, 0xe1, 0xf0, 0x02, 0xca, 0xe0, 0xf0, 0x02, 0xca, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldrd r0, r1, [r10, #0x20]!" + - + asm_text: "ldrd r0, r1, [r10], #0x20" + - + asm_text: "ldrd r0, r1, [r10, #0x20]" + - + asm_text: "strd r0, r1, [r10, #0x20]!" + - + asm_text: "strd r0, r1, [r10], #0x20" + - + asm_text: "strd r0, r1, [r10, #0x20]" diff --git a/thirdparty/capstone/tests/MC/ARM/ldrd-strd-gnu-thumb.s.yaml b/thirdparty/capstone/tests/MC/ARM/ldrd-strd-gnu-thumb.s.yaml new file mode 100644 index 0000000..076ae91 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/ldrd-strd-gnu-thumb.s.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0xfa, 0xe9, 0x80, 0x01, 0xfa, 0xe8, 0x80, 0x01, 0xda, 0xe9, 0x80, 0x01, 0xea, 0xe9, 0x80, 0x01, 0xea, 0xe8, 0x80, 0x01, 0xca, 0xe9, 0x80, 0x01, 0xfa, 0xe9, 0x80, 0x12, 0xfa, 0xe8, 0x80, 0x12, 0xda, 0xe9, 0x80, 0x12, 0xea, 0xe9, 0x80, 0x12, 0xea, 0xe8, 0x80, 0x12, 0xca, 0xe9, 0x80, 0x12 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "ldrd r0, r1, [r10, #0x200]!" + - + asm_text: "ldrd r0, r1, [r10], #0x200" + - + asm_text: "ldrd r0, r1, [r10, #0x200]" + - + asm_text: "strd r0, r1, [r10, #0x200]!" + - + asm_text: "strd r0, r1, [r10], #0x200" + - + asm_text: "strd r0, r1, [r10, #0x200]" + - + asm_text: "ldrd r1, r2, [r10, #0x200]!" + - + asm_text: "ldrd r1, r2, [r10], #0x200" + - + asm_text: "ldrd r1, r2, [r10, #0x200]" + - + asm_text: "strd r1, r2, [r10, #0x200]!" + - + asm_text: "strd r1, r2, [r10], #0x200" + - + asm_text: "strd r1, r2, [r10, #0x200]" diff --git a/thirdparty/capstone/tests/MC/ARM/load-store-acquire-release-v8-thumb.s.yaml b/thirdparty/capstone/tests/MC/ARM/load-store-acquire-release-v8-thumb.s.yaml new file mode 100644 index 0000000..6f376cc --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/load-store-acquire-release-v8-thumb.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0xd4, 0xe8, 0xcf, 0x3f, 0xd5, 0xe8, 0xdf, 0x2f, 0xd7, 0xe8, 0xef, 0x1f, 0xd8, 0xe8, 0xff, 0x67, 0xc4, 0xe8, 0xc1, 0x3f, 0xc5, 0xe8, 0xd4, 0x2f, 0xc7, 0xe8, 0xe2, 0x1f, 0xc8, 0xe8, 0xf6, 0x23, 0xd6, 0xe8, 0xaf, 0x5f, 0xd6, 0xe8, 0x8f, 0x5f, 0xd9, 0xe8, 0x9f, 0xcf, 0xc0, 0xe8, 0xaf, 0x3f, 0xc1, 0xe8, 0x8f, 0x2f, 0xc3, 0xe8, 0x9f, 0x2f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "ldaexb r3, [r4]" + - + asm_text: "ldaexh r2, [r5]" + - + asm_text: "ldaex r1, [r7]" + - + asm_text: "ldaexd r6, r7, [r8]" + - + asm_text: "stlexb r1, r3, [r4]" + - + asm_text: "stlexh r4, r2, [r5]" + - + asm_text: "stlex r2, r1, [r7]" + - + asm_text: "stlexd r6, r2, r3, [r8]" + - + asm_text: "lda r5, [r6]" + - + asm_text: "ldab r5, [r6]" + - + asm_text: "ldah r12, [r9]" + - + asm_text: "stl r3, [r0]" + - + asm_text: "stlb r2, [r1]" + - + asm_text: "stlh r2, [r3]" diff --git a/thirdparty/capstone/tests/MC/ARM/load-store-acquire-release-v8.s.yaml b/thirdparty/capstone/tests/MC/ARM/load-store-acquire-release-v8.s.yaml new file mode 100644 index 0000000..de9f4b0 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/load-store-acquire-release-v8.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0x9f, 0x3e, 0xd4, 0xe1, 0x9f, 0x2e, 0xf5, 0xe1, 0x9f, 0x1e, 0x97, 0xe1, 0x9f, 0x6e, 0xb8, 0xe1, 0x93, 0x1e, 0xc4, 0xe1, 0x92, 0x4e, 0xe5, 0xe1, 0x91, 0x2e, 0x87, 0xe1, 0x92, 0x6e, 0xa8, 0xe1, 0x9f, 0x5c, 0x96, 0xe1, 0x9f, 0x5c, 0xd6, 0xe1, 0x9f, 0xcc, 0xf9, 0xe1, 0x93, 0xfc, 0x80, 0xe1, 0x92, 0xfc, 0xc1, 0xe1, 0x92, 0xfc, 0xe3, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldaexb r3, [r4]" + - + asm_text: "ldaexh r2, [r5]" + - + asm_text: "ldaex r1, [r7]" + - + asm_text: "ldaexd r6, r7, [r8]" + - + asm_text: "stlexb r1, r3, [r4]" + - + asm_text: "stlexh r4, r2, [r5]" + - + asm_text: "stlex r2, r1, [r7]" + - + asm_text: "stlexd r6, r2, r3, [r8]" + - + asm_text: "lda r5, [r6]" + - + asm_text: "ldab r5, [r6]" + - + asm_text: "ldah r12, [r9]" + - + asm_text: "stl r3, [r0]" + - + asm_text: "stlb r2, [r1]" + - + asm_text: "stlh r2, [r3]" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-bitops.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-bitops.s.yaml new file mode 100644 index 0000000..e61a502 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-bitops.s.yaml @@ -0,0 +1,198 @@ +test_cases: + - + input: + bytes: [ 0x81, 0xef, 0x52, 0x09, 0x81, 0xef, 0x52, 0x03, 0x86, 0xff, 0x5d, 0x09, 0x86, 0xff, 0x5d, 0x03, 0x86, 0xff, 0x5d, 0x05, 0x86, 0xff, 0x5d, 0x07, 0x82, 0xef, 0x72, 0x09, 0x81, 0xef, 0x71, 0x03, 0x85, 0xff, 0x7d, 0x09, 0x85, 0xff, 0x7d, 0x0b, 0x86, 0xff, 0x7e, 0x01, 0x86, 0xff, 0x7e, 0x03, 0x86, 0xff, 0x7e, 0x05, 0x86, 0xff, 0x7e, 0x07, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0xb0, 0xff, 0x48, 0x00, 0xb4, 0xff, 0x46, 0x20, 0xb8, 0xff, 0x44, 0x00, 0xb0, 0xff, 0xc2, 0x00, 0xb4, 0xff, 0xca, 0x00, 0xb0, 0xff, 0x44, 0x01, 0xb0, 0xff, 0xc4, 0x05, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x40, 0xee, 0x30, 0x8b, 0x20, 0xee, 0x30, 0x5b, 0x2d, 0xee, 0x10, 0xbb, 0x12, 0xee, 0x10, 0x0b, 0x35, 0xee, 0x70, 0x1b, 0x79, 0xee, 0x30, 0x0b, 0x93, 0xee, 0x30, 0x0b, 0xfa, 0xee, 0x70, 0x0b, 0x71, 0xfe, 0x4d, 0x8f, 0xb0, 0xff, 0xc2, 0x05, 0xb0, 0xff, 0xc2, 0x05, 0x71, 0xfe, 0x4d, 0x8f, 0x32, 0xef, 0x54, 0x01, 0x32, 0xef, 0x54, 0x01 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vorr.i16 q0, #0x12" + - + asm_text: "vorr.i32 q0, #0x1200" + - + asm_text: "vorr.i16 q0, #0xed" + - + asm_text: "vorr.i32 q0, #0xed00" + - + asm_text: "vorr.i32 q0, #0xed0000" + - + asm_text: "vorr.i32 q0, #0xed000000" + - + asm_text: "vbic.i16 q0, #0x22" + - + asm_text: "vbic.i32 q0, #0x1100" + - + asm_text: "vbic.i16 q0, #0xdd" + - + asm_text: "vbic.i16 q0, #0xdd00" + - + asm_text: "vbic.i32 q0, #0xee" + - + asm_text: "vbic.i32 q0, #0xee00" + - + asm_text: "vbic.i32 q0, #0xee0000" + - + asm_text: "vbic.i32 q0, #0xee000000" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vrev64.8 q0, q4" + - + asm_text: "vrev64.16 q1, q3" + - + asm_text: "vrev64.32 q0, q2" + - + asm_text: "vrev32.8 q0, q1" + - + asm_text: "vrev32.16 q0, q5" + - + asm_text: "vrev16.8 q0, q2" + - + asm_text: "vmvn q0, q2" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vmov.8 q0[1], r8" + - + asm_text: "vmov.16 q0[2], r5" + - + asm_text: "vmov.32 q6[3], r11" + - + asm_text: "vmov.32 r0, q1[0]" + - + asm_text: "vmov.s16 r1, q2[7]" + - + asm_text: "vmov.s8 r0, q4[13]" + - + asm_text: "vmov.u16 r0, q1[4]" + - + asm_text: "vmov.u8 r0, q5[7]" + - + asm_text: "vpste" + - + asm_text: "vmvnt q0, q1" + - + asm_text: "vmvne q0, q1" + - + asm_text: "vpste" + - + asm_text: "vornt q0, q1, q2" + - + asm_text: "vorne q0, q1, q2" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-float.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-float.s.yaml new file mode 100644 index 0000000..c2b9188 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-float.s.yaml @@ -0,0 +1,212 @@ +test_cases: + - + input: + bytes: [ 0xb6, 0xff, 0x40, 0x24, 0xba, 0xff, 0x48, 0x04, 0xb6, 0xff, 0x42, 0x05, 0xba, 0xff, 0x46, 0x25, 0xb6, 0xff, 0xca, 0x06, 0xba, 0xff, 0xc8, 0x06, 0xb6, 0xff, 0xc0, 0x27, 0xba, 0xff, 0xc2, 0x07, 0xb6, 0xff, 0xc4, 0x24, 0xba, 0xff, 0xc2, 0x24, 0xb6, 0xff, 0xcc, 0x25, 0xba, 0xff, 0xc0, 0x25, 0xb6, 0xee, 0x60, 0x0a, 0xb6, 0xee, 0x41, 0x0b, 0x12, 0xff, 0x56, 0x4d, 0x00, 0xff, 0x5a, 0x0d, 0x24, 0xfc, 0x42, 0x68, 0xa0, 0xfc, 0x4a, 0x08, 0x2e, 0xfd, 0x44, 0x68, 0xae, 0xfd, 0x4c, 0x48, 0x3c, 0xfc, 0x4c, 0x48, 0xb2, 0xfc, 0x46, 0xe8, 0x3a, 0xfd, 0x46, 0x88, 0xb4, 0xfd, 0x4e, 0x68, 0x14, 0xef, 0x56, 0x0c, 0x06, 0xef, 0x5e, 0x0c, 0x34, 0xef, 0x5a, 0x0c, 0x22, 0xef, 0x54, 0x2c, 0x10, 0xef, 0x4a, 0x0d, 0x06, 0xef, 0x40, 0x2d, 0x02, 0xef, 0x44, 0x0d, 0x82, 0xfc, 0x4e, 0x48, 0x8a, 0xfd, 0x4e, 0x48, 0x98, 0xfc, 0x4e, 0x08, 0x94, 0xfd, 0x46, 0x48, 0x30, 0xff, 0x4c, 0x0d, 0x22, 0xff, 0x48, 0x0d, 0xbf, 0xef, 0x5e, 0x2c, 0xb0, 0xef, 0x5e, 0x2c, 0xb5, 0xef, 0x5e, 0x2c, 0xbd, 0xef, 0x52, 0x2d, 0xb6, 0xff, 0x52, 0x4c, 0xbd, 0xff, 0x50, 0x0d, 0xbf, 0xef, 0x5e, 0x2e, 0xa0, 0xef, 0x5e, 0x2e, 0xba, 0xef, 0x5e, 0x2e, 0xab, 0xef, 0x50, 0x2f, 0xbc, 0xff, 0x58, 0x2e, 0xb8, 0xff, 0x5a, 0x2f, 0xb7, 0xff, 0x42, 0x06, 0xb7, 0xff, 0xc8, 0x06, 0xb7, 0xff, 0x40, 0x07, 0xb7, 0xff, 0xc0, 0x07, 0xbb, 0xff, 0x40, 0x06, 0xbb, 0xff, 0xc0, 0x06, 0xbb, 0xff, 0x40, 0x07, 0xbb, 0xff, 0xc4, 0x07, 0xb7, 0xff, 0x4e, 0x00, 0xbc, 0xfe, 0xe1, 0x1a, 0xb7, 0xff, 0x4e, 0x00, 0xbb, 0xff, 0xcc, 0xe1, 0xbb, 0xff, 0x4e, 0x02, 0xbb, 0xff, 0xc8, 0x23, 0xb5, 0xff, 0xce, 0x07, 0xb9, 0xff, 0xc4, 0x07, 0xb5, 0xff, 0x44, 0x07, 0xb9, 0xff, 0x40, 0x07, 0x3f, 0xfe, 0x83, 0x2e, 0x3f, 0xee, 0x8d, 0x4e, 0x3f, 0xfe, 0x85, 0x1e, 0x3f, 0xee, 0x83, 0x1e, 0x08, 0xbf, 0x30, 0xee, 0x20, 0x0a, 0x71, 0xfe, 0x4d, 0x0f, 0x12, 0xef, 0x44, 0x0d, 0x71, 0xfe, 0x4d, 0x8f, 0xbb, 0xff, 0xc2, 0x03, 0xbb, 0xff, 0x42, 0x01, 0x18, 0xbf, 0xbd, 0xee, 0xe0, 0x0a, 0xa8, 0xbf, 0xb2, 0xee, 0xe0, 0x3b, 0x77, 0xee, 0xc1, 0x9f, 0xbb, 0xff, 0xc0, 0x47, 0xbb, 0xff, 0xc0, 0x27, 0x0c, 0xbf, 0xbc, 0xee, 0xe0, 0x0a, 0xb8, 0xee, 0x60, 0x0a, 0x71, 0xfe, 0x4d, 0x8f, 0x12, 0xff, 0x54, 0x0d, 0x12, 0xff, 0x54, 0x0d, 0x0c, 0xbf, 0x20, 0xee, 0x01, 0x0b, 0x20, 0xee, 0x02, 0x1b, 0x08, 0xbf, 0xb1, 0xee, 0x60, 0x0a, 0x04, 0xbf, 0x20, 0xee, 0xc1, 0x0a, 0x20, 0xee, 0x81, 0x0a, 0x71, 0xfe, 0x4d, 0x8f, 0xb6, 0xff, 0x42, 0x04, 0xba, 0xff, 0x42, 0x04 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vrintn.f16 q1, q0" + - + asm_text: "vrintn.f32 q0, q4" + - + asm_text: "vrinta.f16 q0, q1" + - + asm_text: "vrinta.f32 q1, q3" + - + asm_text: "vrintm.f16 q0, q5" + - + asm_text: "vrintm.f32 q0, q4" + - + asm_text: "vrintp.f16 q1, q0" + - + asm_text: "vrintp.f32 q0, q1" + - + asm_text: "vrintx.f16 q1, q2" + - + asm_text: "vrintx.f32 q1, q1" + - + asm_text: "vrintz.f16 q1, q6" + - + asm_text: "vrintz.f32 q1, q0" + - + asm_text: "vrintr.f32 s0, s1" + - + asm_text: "vrintr.f64 d0, d1" + - + asm_text: "vmul.f16 q2, q1, q3" + - + asm_text: "vmul.f32 q0, q0, q5" + - + asm_text: "vcmla.f16 q3, q2, q1, #0" + - + asm_text: "vcmla.f16 q0, q0, q5, #0x5a" + - + asm_text: "vcmla.f16 q3, q7, q2, #0xb4" + - + asm_text: "vcmla.f16 q2, q7, q6, #0x10e" + - + asm_text: "vcmla.f32 q2, q6, q6, #0" + - + asm_text: "vcmla.f32 q7, q1, q3, #0x5a" + - + asm_text: "vcmla.f32 q4, q5, q3, #0xb4" + - + asm_text: "vcmla.f32 q3, q2, q7, #0x10e" + - + asm_text: "vfma.f16 q0, q2, q3" + - + asm_text: "vfma.f32 q0, q3, q7" + - + asm_text: "vfms.f16 q0, q2, q5" + - + asm_text: "vfms.f32 q1, q1, q2" + - + asm_text: "vadd.f16 q0, q0, q5" + - + asm_text: "vadd.f32 q1, q3, q0" + - + asm_text: "vadd.f32 q0, q1, q2" + - + asm_text: "vcadd.f16 q2, q1, q7, #0x5a" + - + asm_text: "vcadd.f16 q2, q5, q7, #0x10e" + - + asm_text: "vcadd.f32 q0, q4, q7, #0x5a" + - + asm_text: "vcadd.f32 q2, q2, q3, #0x10e" + - + asm_text: "vabd.f16 q0, q0, q6" + - + asm_text: "vabd.f32 q0, q1, q4" + - + asm_text: "vcvt.f16.s16 q1, q7, #1" + - + asm_text: "vcvt.f16.s16 q1, q7, #0x10" + - + asm_text: "vcvt.f16.s16 q1, q7, #0xb" + - + asm_text: "vcvt.s16.f16 q1, q1, #3" + - + asm_text: "vcvt.f16.u16 q2, q1, #0xa" + - + asm_text: "vcvt.u16.f16 q0, q0, #3" + - + asm_text: "vcvt.f32.s32 q1, q7, #1" + - + asm_text: "vcvt.f32.s32 q1, q7, #0x20" + - + asm_text: "vcvt.f32.s32 q1, q7, #6" + - + asm_text: "vcvt.s32.f32 q1, q0, #0x15" + - + asm_text: "vcvt.f32.u32 q1, q4, #4" + - + asm_text: "vcvt.u32.f32 q1, q5, #8" + - + asm_text: "vcvt.f16.s16 q0, q1" + - + asm_text: "vcvt.f16.u16 q0, q4" + - + asm_text: "vcvt.s16.f16 q0, q0" + - + asm_text: "vcvt.u16.f16 q0, q0" + - + asm_text: "vcvt.f32.s32 q0, q0" + - + asm_text: "vcvt.f32.u32 q0, q0" + - + asm_text: "vcvt.s32.f32 q0, q0" + - + asm_text: "vcvt.u32.f32 q0, q2" + - + asm_text: "vcvta.s16.f16 q0, q7" + - + asm_text: "vcvta.s32.f32 s2, s3" + - + asm_text: "vcvta.s16.f16 q0, q7" + - + asm_text: "vcvtn.u32.f32 q7, q6" + - + asm_text: "vcvtp.s32.f32 q0, q7" + - + asm_text: "vcvtm.u32.f32 q1, q4" + - + asm_text: "vneg.f16 q0, q7" + - + asm_text: "vneg.f32 q0, q2" + - + asm_text: "vabs.f16 q0, q2" + - + asm_text: "vabs.f32 q0, q0" + - + asm_text: "vmaxnma.f16 q1, q1" + - + asm_text: "vmaxnma.f32 q2, q6" + - + asm_text: "vminnma.f16 q0, q2" + - + asm_text: "vminnma.f32 q0, q1" + - + asm_text: "it eq" + - + asm_text: "vaddeq.f32 s0, s0, s1" + - + asm_text: "vpst" + - + asm_text: "vaddt.f16 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vcvtmt.u32.f32 q0, q1" + - + asm_text: "vcvtne.s32.f32 q0, q1" + - + asm_text: "it ne" + - + asm_text: "vcvtne.s32.f32 s0, s1" + - + asm_text: "it ge" + - + asm_text: "vcvttge.f64.f16 d3, s1" + - + asm_text: "vpte.f32 lt, q3, r1" + - + asm_text: "vcvtt.u32.f32 q2, q0" + - + asm_text: "vcvte.u32.f32 q1, q0" + - + asm_text: "ite eq" + - + asm_text: "vcvteq.u32.f32 s0, s1" + - + asm_text: "vcvtne.f32.u32 s0, s1" + - + asm_text: "vpste" + - + asm_text: "vmult.f16 q0, q1, q2" + - + asm_text: "vmule.f16 q0, q1, q2" + - + asm_text: "ite eq" + - + asm_text: "vmuleq.f64 d0, d0, d1" + - + asm_text: "vmulne.f64 d1, d0, d2" + - + asm_text: "it eq" + - + asm_text: "vnegeq.f32 s0, s1" + - + asm_text: "itt eq" + - + asm_text: "vnmuleq.f32 s0, s1, s2" + - + asm_text: "vmuleq.f32 s0, s1, s2" + - + asm_text: "vpste" + - + asm_text: "vrintnt.f16 q0, q1" + - + asm_text: "vrintne.f32 q0, q1" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-integer.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-integer.s.yaml new file mode 100644 index 0000000..fcc984d --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-integer.s.yaml @@ -0,0 +1,206 @@ +test_cases: + - + input: + bytes: [ 0x81, 0xef, 0x5b, 0x0c, 0x85, 0xef, 0x5c, 0x08, 0x84, 0xef, 0x5c, 0x0e, 0x80, 0xff, 0x5d, 0x0f, 0x84, 0xef, 0x50, 0x0f, 0x84, 0xef, 0x51, 0x0f, 0x83, 0xef, 0x5f, 0x0f, 0xb0, 0xee, 0x60, 0x8a, 0xb0, 0xee, 0x41, 0x0b, 0x81, 0xff, 0x7f, 0x0e, 0x00, 0xef, 0x56, 0x09, 0x10, 0xef, 0x56, 0xc9, 0x26, 0xef, 0x5c, 0xe9, 0x0a, 0xff, 0x4a, 0x0b, 0x18, 0xff, 0x44, 0x2b, 0x2a, 0xff, 0x40, 0x0b, 0x08, 0xef, 0x4a, 0x0b, 0x18, 0xef, 0x40, 0xcb, 0x20, 0xef, 0x4c, 0xab, 0x04, 0xff, 0x4a, 0x68, 0x16, 0xff, 0x4c, 0x08, 0x20, 0xff, 0x4c, 0x08, 0x04, 0xef, 0x44, 0x08, 0x14, 0xef, 0x42, 0x48, 0x20, 0xef, 0x4c, 0x08, 0x0c, 0xef, 0x50, 0x22, 0x1c, 0xef, 0x52, 0x02, 0x20, 0xef, 0x5a, 0x02, 0x04, 0xff, 0x5c, 0x02, 0x1e, 0xff, 0x52, 0x02, 0x28, 0xff, 0x5e, 0x22, 0x02, 0xef, 0x54, 0x00, 0x08, 0xef, 0x5c, 0x00, 0x1a, 0xef, 0x5a, 0x00, 0x20, 0xef, 0x58, 0x00, 0x08, 0xff, 0x54, 0x00, 0x1c, 0xff, 0x5c, 0x80, 0x22, 0xff, 0x54, 0x00, 0x00, 0xef, 0x44, 0x07, 0x1a, 0xef, 0x48, 0x27, 0x26, 0xef, 0x44, 0x47, 0x0c, 0xff, 0x48, 0x27, 0x1c, 0xff, 0x44, 0x07, 0x2e, 0xff, 0x48, 0x07, 0x02, 0xef, 0x42, 0x01, 0x12, 0xef, 0x40, 0x01, 0x28, 0xef, 0x42, 0x01, 0x00, 0xff, 0x4c, 0x21, 0x14, 0xff, 0x4a, 0x41, 0x26, 0xff, 0x40, 0x41, 0x00, 0xef, 0x44, 0x02, 0x16, 0xef, 0x42, 0x22, 0x24, 0xef, 0x4a, 0x02, 0x08, 0xff, 0x44, 0x02, 0x1e, 0xff, 0x4a, 0x02, 0x2c, 0xff, 0x48, 0x42, 0x0e, 0xef, 0x40, 0x00, 0x10, 0xef, 0x44, 0x80, 0x26, 0xef, 0x42, 0x00, 0x00, 0xff, 0x46, 0x60, 0x12, 0xff, 0x46, 0x00, 0x22, 0xff, 0x46, 0x00, 0xec, 0xee, 0x10, 0x8b, 0xae, 0xee, 0x30, 0xeb, 0xa2, 0xee, 0x10, 0x9b, 0xa0, 0xee, 0x30, 0x1b, 0xa0, 0xee, 0x30, 0x1b, 0xb0, 0xff, 0x42, 0x44, 0xb4, 0xff, 0x48, 0x04, 0xb8, 0xff, 0x40, 0x04, 0xb0, 0xff, 0xce, 0x04, 0xb4, 0xff, 0xce, 0x84, 0xb8, 0xff, 0xca, 0xe4, 0xb1, 0xff, 0xc0, 0x23, 0xb5, 0xff, 0xc2, 0x03, 0xb9, 0xff, 0xc4, 0xe3, 0xb1, 0xff, 0x42, 0x23, 0xb5, 0xff, 0x44, 0x03, 0xb9, 0xff, 0x4e, 0x03, 0xb0, 0xff, 0xc0, 0x07, 0xb4, 0xff, 0xc4, 0xc7, 0xb8, 0xff, 0xc4, 0xe7, 0xb0, 0xff, 0x48, 0x47, 0xb4, 0xff, 0x44, 0x07, 0xb8, 0xff, 0x4a, 0x07, 0x71, 0xfe, 0x4d, 0x8f, 0xb1, 0xff, 0xc2, 0x03, 0xb1, 0xff, 0xc2, 0x03, 0x71, 0xfe, 0x4d, 0x0f, 0x12, 0xef, 0x54, 0x00, 0x71, 0xfe, 0x4d, 0x8f, 0xb0, 0xff, 0xc2, 0x07, 0xb4, 0xff, 0xc2, 0x07, 0x33, 0xee, 0x8f, 0x3e, 0x37, 0xee, 0x89, 0x3e, 0x3b, 0xee, 0x8f, 0x1e, 0x33, 0xee, 0x8f, 0x0e, 0x37, 0xee, 0x81, 0x2e, 0x3b, 0xee, 0x81, 0x2e ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmov.i32 q0, #0x1bff" + - + asm_text: "vmov.i16 q0, #0x5c" + - + asm_text: "vmov.i8 q0, #0x4c" + - + asm_text: "vmov.f32 q0, #-3.625000e+00" + - + asm_text: "vmov.f32 q0, #1.250000e-01" + - + asm_text: "vmov.f32 q0, #1.328125e-01" + - + asm_text: "vmov.f32 q0, #3.100000e+01" + - + asm_text: "vmov.f32 s16, s1" + - + asm_text: "vmov.f64 d0, d1" + - + asm_text: "vmov.i64 q0, #0xff0000ffffffffff" + - + asm_text: "vmul.i8 q0, q0, q3" + - + asm_text: "vmul.i16 q6, q0, q3" + - + asm_text: "vmul.i32 q7, q3, q6" + - + asm_text: "vqrdmulh.s8 q0, q5, q5" + - + asm_text: "vqrdmulh.s16 q1, q4, q2" + - + asm_text: "vqrdmulh.s32 q0, q5, q0" + - + asm_text: "vqdmulh.s8 q0, q4, q5" + - + asm_text: "vqdmulh.s16 q6, q4, q0" + - + asm_text: "vqdmulh.s32 q5, q0, q6" + - + asm_text: "vsub.i8 q3, q2, q5" + - + asm_text: "vsub.i16 q0, q3, q6" + - + asm_text: "vsub.i32 q0, q0, q6" + - + asm_text: "vadd.i8 q0, q2, q2" + - + asm_text: "vadd.i16 q2, q2, q1" + - + asm_text: "vadd.i32 q0, q0, q6" + - + asm_text: "vqsub.s8 q1, q6, q0" + - + asm_text: "vqsub.s16 q0, q6, q1" + - + asm_text: "vqsub.s32 q0, q0, q5" + - + asm_text: "vqsub.u8 q0, q2, q6" + - + asm_text: "vqsub.u16 q0, q7, q1" + - + asm_text: "vqsub.u32 q1, q4, q7" + - + asm_text: "vqadd.s8 q0, q1, q2" + - + asm_text: "vqadd.s8 q0, q4, q6" + - + asm_text: "vqadd.s16 q0, q5, q5" + - + asm_text: "vqadd.s32 q0, q0, q4" + - + asm_text: "vqadd.u8 q0, q4, q2" + - + asm_text: "vqadd.u16 q4, q6, q6" + - + asm_text: "vqadd.u32 q0, q1, q2" + - + asm_text: "vabd.s8 q0, q0, q2" + - + asm_text: "vabd.s16 q1, q5, q4" + - + asm_text: "vabd.s32 q2, q3, q2" + - + asm_text: "vabd.u8 q1, q6, q4" + - + asm_text: "vabd.u16 q0, q6, q2" + - + asm_text: "vabd.u32 q0, q7, q4" + - + asm_text: "vrhadd.s8 q0, q1, q1" + - + asm_text: "vrhadd.s16 q0, q1, q0" + - + asm_text: "vrhadd.s32 q0, q4, q1" + - + asm_text: "vrhadd.u8 q1, q0, q6" + - + asm_text: "vrhadd.u16 q2, q2, q5" + - + asm_text: "vrhadd.u32 q2, q3, q0" + - + asm_text: "vhsub.s8 q0, q0, q2" + - + asm_text: "vhsub.s16 q1, q3, q1" + - + asm_text: "vhsub.s32 q0, q2, q5" + - + asm_text: "vhsub.u8 q0, q4, q2" + - + asm_text: "vhsub.u16 q0, q7, q5" + - + asm_text: "vhsub.u32 q2, q6, q4" + - + asm_text: "vhadd.s8 q0, q7, q0" + - + asm_text: "vhadd.s16 q4, q0, q2" + - + asm_text: "vhadd.s32 q0, q3, q1" + - + asm_text: "vhadd.u8 q3, q0, q3" + - + asm_text: "vhadd.u16 q0, q1, q3" + - + asm_text: "vhadd.u32 q0, q1, q3" + - + asm_text: "vdup.8 q6, r8" + - + asm_text: "vdup.16 q7, lr" + - + asm_text: "vdup.32 q1, r9" + - + asm_text: "vdup.16 q0, r1" + - + asm_text: "vdup.16 q0, r1" + - + asm_text: "vcls.s8 q2, q1" + - + asm_text: "vcls.s16 q0, q4" + - + asm_text: "vcls.s32 q0, q0" + - + asm_text: "vclz.i8 q0, q7" + - + asm_text: "vclz.i16 q4, q7" + - + asm_text: "vclz.i32 q7, q5" + - + asm_text: "vneg.s8 q1, q0" + - + asm_text: "vneg.s16 q0, q1" + - + asm_text: "vneg.s32 q7, q2" + - + asm_text: "vabs.s8 q1, q1" + - + asm_text: "vabs.s16 q0, q2" + - + asm_text: "vabs.s32 q0, q7" + - + asm_text: "vqneg.s8 q0, q0" + - + asm_text: "vqneg.s16 q6, q2" + - + asm_text: "vqneg.s32 q7, q2" + - + asm_text: "vqabs.s8 q2, q4" + - + asm_text: "vqabs.s16 q0, q2" + - + asm_text: "vqabs.s32 q0, q5" + - + asm_text: "vpste" + - + asm_text: "vnegt.s8 q0, q1" + - + asm_text: "vnege.s8 q0, q1" + - + asm_text: "vpst" + - + asm_text: "vqaddt.s16 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vqnegt.s8 q0, q1" + - + asm_text: "vqnege.s16 q0, q1" + - + asm_text: "vmina.s8 q1, q7" + - + asm_text: "vmina.s16 q1, q4" + - + asm_text: "vmina.s32 q0, q7" + - + asm_text: "vmaxa.s8 q0, q7" + - + asm_text: "vmaxa.s16 q1, q0" + - + asm_text: "vmaxa.s32 q1, q0" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-interleave.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-interleave.s.yaml new file mode 100644 index 0000000..d73d934 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-interleave.s.yaml @@ -0,0 +1,142 @@ +test_cases: + - + input: + bytes: [ 0x9d, 0xfc, 0x00, 0x1e, 0x90, 0xfc, 0x00, 0x1e, 0xb0, 0xfc, 0x00, 0x1e, 0x9b, 0xfc, 0x00, 0x1e, 0xb0, 0xfc, 0x00, 0xbe, 0x90, 0xfc, 0x20, 0x1e, 0xb0, 0xfc, 0x20, 0x7e, 0x90, 0xfc, 0x80, 0x1e, 0xb0, 0xfc, 0x80, 0x1e, 0x9b, 0xfc, 0x80, 0x1e, 0xb0, 0xfc, 0x80, 0xbe, 0x90, 0xfc, 0xa0, 0x1e, 0xb0, 0xfc, 0xa0, 0x7e, 0x90, 0xfc, 0x00, 0x1f, 0xb0, 0xfc, 0x00, 0x1f, 0x9b, 0xfc, 0x00, 0x1f, 0xb0, 0xfc, 0x00, 0xbf, 0x90, 0xfc, 0x20, 0x1f, 0xb0, 0xfc, 0x20, 0x7f, 0x80, 0xfc, 0x00, 0x1e, 0xa0, 0xfc, 0x00, 0x1e, 0x8b, 0xfc, 0x00, 0x1e, 0xa0, 0xfc, 0x00, 0xbe, 0x80, 0xfc, 0x20, 0x1e, 0xa0, 0xfc, 0x20, 0x7e, 0x80, 0xfc, 0x80, 0x1e, 0xa0, 0xfc, 0x80, 0x1e, 0x8b, 0xfc, 0x80, 0x1e, 0xa0, 0xfc, 0x80, 0xbe, 0x80, 0xfc, 0xa0, 0x1e, 0xa0, 0xfc, 0xa0, 0x7e, 0x80, 0xfc, 0x00, 0x1f, 0xa0, 0xfc, 0x00, 0x1f, 0x8b, 0xfc, 0x00, 0x1f, 0xa0, 0xfc, 0x00, 0xbf, 0x80, 0xfc, 0x20, 0x1f, 0xa0, 0xfc, 0x20, 0x7f, 0x90, 0xfc, 0x01, 0x1e, 0xb0, 0xfc, 0x01, 0x1e, 0x9b, 0xfc, 0x01, 0x1e, 0xb0, 0xfc, 0x01, 0x7e, 0x90, 0xfc, 0x21, 0x1e, 0xb0, 0xfc, 0x21, 0x9e, 0x90, 0xfc, 0x41, 0x1e, 0xb0, 0xfc, 0x41, 0x1e, 0x90, 0xfc, 0x61, 0x1e, 0xb0, 0xfc, 0x61, 0x9e, 0x90, 0xfc, 0x81, 0x1e, 0xb0, 0xfc, 0x81, 0x1e, 0x9b, 0xfc, 0x81, 0x1e, 0xb0, 0xfc, 0x81, 0x7e, 0x90, 0xfc, 0xa1, 0x1e, 0xb0, 0xfc, 0xa1, 0x9e, 0x90, 0xfc, 0xc1, 0x1e, 0xb0, 0xfc, 0xc1, 0x1e, 0x90, 0xfc, 0xe1, 0x1e, 0xb0, 0xfc, 0xe1, 0x9e, 0x90, 0xfc, 0x01, 0x1f, 0xb0, 0xfc, 0x01, 0x1f, 0x9b, 0xfc, 0x01, 0x1f, 0xb0, 0xfc, 0x01, 0x7f, 0x90, 0xfc, 0x21, 0x1f, 0xb0, 0xfc, 0x21, 0x9f, 0x90, 0xfc, 0x41, 0x1f, 0xb0, 0xfc, 0x41, 0x1f, 0x90, 0xfc, 0x61, 0x1f, 0xb0, 0xfc, 0x61, 0x9f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vld20.8 {q0, q1}, [sp]" + - + asm_text: "vld20.8 {q0, q1}, [r0]" + - + asm_text: "vld20.8 {q0, q1}, [r0]!" + - + asm_text: "vld20.8 {q0, q1}, [r11]" + - + asm_text: "vld20.8 {q5, q6}, [r0]!" + - + asm_text: "vld21.8 {q0, q1}, [r0]" + - + asm_text: "vld21.8 {q3, q4}, [r0]!" + - + asm_text: "vld20.16 {q0, q1}, [r0]" + - + asm_text: "vld20.16 {q0, q1}, [r0]!" + - + asm_text: "vld20.16 {q0, q1}, [r11]" + - + asm_text: "vld20.16 {q5, q6}, [r0]!" + - + asm_text: "vld21.16 {q0, q1}, [r0]" + - + asm_text: "vld21.16 {q3, q4}, [r0]!" + - + asm_text: "vld20.32 {q0, q1}, [r0]" + - + asm_text: "vld20.32 {q0, q1}, [r0]!" + - + asm_text: "vld20.32 {q0, q1}, [r11]" + - + asm_text: "vld20.32 {q5, q6}, [r0]!" + - + asm_text: "vld21.32 {q0, q1}, [r0]" + - + asm_text: "vld21.32 {q3, q4}, [r0]!" + - + asm_text: "vst20.8 {q0, q1}, [r0]" + - + asm_text: "vst20.8 {q0, q1}, [r0]!" + - + asm_text: "vst20.8 {q0, q1}, [r11]" + - + asm_text: "vst20.8 {q5, q6}, [r0]!" + - + asm_text: "vst21.8 {q0, q1}, [r0]" + - + asm_text: "vst21.8 {q3, q4}, [r0]!" + - + asm_text: "vst20.16 {q0, q1}, [r0]" + - + asm_text: "vst20.16 {q0, q1}, [r0]!" + - + asm_text: "vst20.16 {q0, q1}, [r11]" + - + asm_text: "vst20.16 {q5, q6}, [r0]!" + - + asm_text: "vst21.16 {q0, q1}, [r0]" + - + asm_text: "vst21.16 {q3, q4}, [r0]!" + - + asm_text: "vst20.32 {q0, q1}, [r0]" + - + asm_text: "vst20.32 {q0, q1}, [r0]!" + - + asm_text: "vst20.32 {q0, q1}, [r11]" + - + asm_text: "vst20.32 {q5, q6}, [r0]!" + - + asm_text: "vst21.32 {q0, q1}, [r0]" + - + asm_text: "vst21.32 {q3, q4}, [r0]!" + - + asm_text: "vld40.8 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld40.8 {q0, q1, q2, q3}, [r0]!" + - + asm_text: "vld40.8 {q0, q1, q2, q3}, [r11]" + - + asm_text: "vld40.8 {q3, q4, q5, q6}, [r0]!" + - + asm_text: "vld41.8 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld41.8 {q4, q5, q6, q7}, [r0]!" + - + asm_text: "vld42.8 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld42.8 {q0, q1, q2, q3}, [r0]!" + - + asm_text: "vld43.8 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld43.8 {q4, q5, q6, q7}, [r0]!" + - + asm_text: "vld40.16 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld40.16 {q0, q1, q2, q3}, [r0]!" + - + asm_text: "vld40.16 {q0, q1, q2, q3}, [r11]" + - + asm_text: "vld40.16 {q3, q4, q5, q6}, [r0]!" + - + asm_text: "vld41.16 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld41.16 {q4, q5, q6, q7}, [r0]!" + - + asm_text: "vld42.16 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld42.16 {q0, q1, q2, q3}, [r0]!" + - + asm_text: "vld43.16 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld43.16 {q4, q5, q6, q7}, [r0]!" + - + asm_text: "vld40.32 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld40.32 {q0, q1, q2, q3}, [r0]!" + - + asm_text: "vld40.32 {q0, q1, q2, q3}, [r11]" + - + asm_text: "vld40.32 {q3, q4, q5, q6}, [r0]!" + - + asm_text: "vld41.32 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld41.32 {q4, q5, q6, q7}, [r0]!" + - + asm_text: "vld42.32 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld42.32 {q0, q1, q2, q3}, [r0]!" + - + asm_text: "vld43.32 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld43.32 {q4, q5, q6, q7}, [r0]!" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-load-store.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-load-store.s.yaml new file mode 100644 index 0000000..363333f --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-load-store.s.yaml @@ -0,0 +1,892 @@ +test_cases: + - + input: + bytes: [ 0x90, 0xed, 0x00, 0x1e, 0x90, 0xed, 0x00, 0x3e, 0x9b, 0xed, 0x00, 0x1e, 0x9b, 0xed, 0x00, 0x7e, 0x94, 0xed, 0x38, 0x1e, 0x94, 0xed, 0x38, 0x9e, 0x98, 0xed, 0x38, 0x1e, 0xb4, 0xed, 0x38, 0xbe, 0xb4, 0xed, 0x38, 0xbe, 0x34, 0xec, 0x19, 0xbe, 0x3a, 0xec, 0x19, 0xbe, 0x1d, 0xed, 0x19, 0xbe, 0x1d, 0xed, 0x7f, 0xbe, 0x80, 0xed, 0x00, 0x1e, 0x80, 0xed, 0x00, 0x3e, 0x8b, 0xed, 0x00, 0x1e, 0x8b, 0xed, 0x00, 0x7e, 0x84, 0xed, 0x38, 0x1e, 0x84, 0xed, 0x38, 0x9e, 0x88, 0xed, 0x38, 0x1e, 0xa4, 0xed, 0x38, 0xbe, 0xa4, 0xed, 0x38, 0xbe, 0x24, 0xec, 0x19, 0xbe, 0x2a, 0xec, 0x19, 0xbe, 0x0d, 0xed, 0x19, 0xbe, 0x8d, 0xed, 0x7f, 0xbe, 0x90, 0xfd, 0x80, 0x0e, 0x90, 0xfd, 0x80, 0x2e, 0x97, 0xfd, 0x80, 0x0e, 0x97, 0xfd, 0x80, 0x6e, 0x94, 0xfd, 0xb8, 0x0e, 0x94, 0xfd, 0xb8, 0x8e, 0x92, 0xfd, 0xb8, 0x0e, 0xb4, 0xfd, 0xb8, 0xae, 0xb4, 0xfd, 0xb8, 0xae, 0x34, 0xfc, 0x81, 0xae, 0x33, 0xfc, 0x99, 0xae, 0x16, 0xfd, 0x99, 0xae, 0x16, 0xfd, 0xc0, 0xae, 0x90, 0xed, 0x80, 0x0e, 0x90, 0xed, 0x80, 0x2e, 0x97, 0xed, 0x80, 0x0e, 0x97, 0xed, 0x80, 0x6e, 0x94, 0xed, 0xb8, 0x0e, 0x94, 0xed, 0xb8, 0x8e, 0x92, 0xed, 0xb8, 0x0e, 0xb4, 0xed, 0xb8, 0xae, 0xb4, 0xed, 0xb8, 0xae, 0x34, 0xec, 0x99, 0xae, 0x33, 0xec, 0x99, 0xae, 0x16, 0xed, 0x99, 0xae, 0x16, 0xed, 0xc0, 0xae, 0x80, 0xed, 0x80, 0x0e, 0x80, 0xed, 0x80, 0x2e, 0x87, 0xed, 0x80, 0x0e, 0x87, 0xed, 0x80, 0x6e, 0x84, 0xed, 0xb8, 0x0e, 0x84, 0xed, 0xb8, 0x8e, 0x85, 0xed, 0xb8, 0x0e, 0xa4, 0xed, 0xb8, 0xae, 0xa4, 0xed, 0xb8, 0xae, 0x24, 0xec, 0x99, 0xae, 0x23, 0xec, 0x99, 0xae, 0x02, 0xed, 0x99, 0xae, 0x02, 0xed, 0xc0, 0xae, 0x90, 0xfd, 0x00, 0x0f, 0x90, 0xfd, 0x00, 0x2f, 0x97, 0xfd, 0x00, 0x0f, 0x97, 0xfd, 0x00, 0x6f, 0x94, 0xfd, 0x38, 0x0f, 0x94, 0xfd, 0x38, 0x8f, 0x92, 0xfd, 0x38, 0x0f, 0xb4, 0xfd, 0x38, 0xaf, 0xb4, 0xfd, 0x38, 0xaf, 0x34, 0xfc, 0x19, 0xaf, 0x33, 0xfc, 0x19, 0xaf, 0x16, 0xfd, 0x19, 0xaf, 0x16, 0xfd, 0x40, 0xaf, 0x90, 0xed, 0x00, 0x0f, 0x90, 0xed, 0x00, 0x2f, 0x97, 0xed, 0x00, 0x0f, 0x97, 0xed, 0x00, 0x6f, 0x94, 0xed, 0x38, 0x0f, 0x94, 0xed, 0x38, 0x8f, 0x92, 0xed, 0x38, 0x0f, 0xb4, 0xed, 0x38, 0xaf, 0xb4, 0xed, 0x38, 0xaf, 0x34, 0xec, 0x19, 0xaf, 0x33, 0xec, 0x19, 0xaf, 0x16, 0xed, 0x19, 0xaf, 0x16, 0xed, 0x40, 0xaf, 0x80, 0xed, 0x00, 0x0f, 0x80, 0xed, 0x00, 0x2f, 0x87, 0xed, 0x00, 0x0f, 0x87, 0xed, 0x00, 0x6f, 0x84, 0xed, 0x38, 0x0f, 0x84, 0xed, 0x38, 0x8f, 0x85, 0xed, 0x38, 0x0f, 0xa4, 0xed, 0x38, 0xaf, 0xa4, 0xed, 0x38, 0xaf, 0x24, 0xec, 0x19, 0xaf, 0x23, 0xec, 0x19, 0xaf, 0x02, 0xed, 0x19, 0xaf, 0x02, 0xed, 0x40, 0xaf, 0x90, 0xed, 0x80, 0x1e, 0x90, 0xed, 0x80, 0x3e, 0x9b, 0xed, 0x80, 0x1e, 0x9b, 0xed, 0x80, 0x7e, 0x94, 0xed, 0x9c, 0x1e, 0x94, 0xed, 0x9c, 0x9e, 0x98, 0xed, 0x9c, 0x1e, 0xb4, 0xed, 0x9c, 0xbe, 0xb4, 0xed, 0x9c, 0xbe, 0x34, 0xec, 0x8d, 0xbe, 0x3a, 0xec, 0x8d, 0xbe, 0x1d, 0xed, 0x8d, 0xbe, 0x1d, 0xed, 0xa0, 0xbe, 0x1d, 0xed, 0xff, 0xbe, 0xba, 0xec, 0xff, 0xbe, 0x80, 0xed, 0x80, 0x1e, 0x80, 0xed, 0x80, 0x3e, 0x8b, 0xed, 0x80, 0x1e, 0x8b, 0xed, 0x80, 0x7e, 0x84, 0xed, 0x9c, 0x1e, 0x84, 0xed, 0x9c, 0x9e, 0x88, 0xed, 0x9c, 0x1e, 0xa4, 0xed, 0x9c, 0xbe, 0xa4, 0xed, 0x9c, 0xbe, 0x24, 0xec, 0x8d, 0xbe, 0x2a, 0xec, 0x8d, 0xbe, 0x0d, 0xed, 0x8d, 0xbe, 0x0d, 0xed, 0xa0, 0xbe, 0x0d, 0xed, 0xff, 0xbe, 0xaa, 0xec, 0xff, 0xbe, 0x98, 0xfd, 0x00, 0x0f, 0x98, 0xfd, 0x00, 0x2f, 0x9f, 0xfd, 0x00, 0x0f, 0x9f, 0xfd, 0x00, 0x6f, 0x9c, 0xfd, 0x1c, 0x0f, 0x9c, 0xfd, 0x1c, 0x8f, 0x9a, 0xfd, 0x1c, 0x0f, 0xbc, 0xfd, 0x1c, 0xaf, 0xbc, 0xfd, 0x1c, 0xaf, 0x3c, 0xfc, 0x0d, 0xaf, 0x3b, 0xfc, 0x0d, 0xaf, 0x1e, 0xfd, 0x0d, 0xaf, 0x1e, 0xfd, 0x20, 0xaf, 0x1e, 0xfd, 0x7f, 0xaf, 0xbc, 0xfd, 0x7f, 0xaf, 0x98, 0xed, 0x00, 0x0f, 0x98, 0xed, 0x00, 0x2f, 0x9f, 0xed, 0x00, 0x0f, 0x9f, 0xed, 0x00, 0x6f, 0x9c, 0xed, 0x1c, 0x0f, 0x9c, 0xed, 0x1c, 0x8f, 0x9a, 0xed, 0x1c, 0x0f, 0xbc, 0xed, 0x1c, 0xaf, 0xbc, 0xed, 0x1c, 0xaf, 0x3c, 0xec, 0x0d, 0xaf, 0x3b, 0xec, 0x0d, 0xaf, 0x1e, 0xed, 0x0d, 0xaf, 0x1e, 0xed, 0x20, 0xaf, 0x1e, 0xed, 0x7f, 0xaf, 0xbc, 0xed, 0x7f, 0xaf, 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0xa2, 0xfd, 0x42, 0xfe, 0xa2, 0xfd, 0x42, 0xfe, 0x92, 0xfd, 0x00, 0x1f, 0x92, 0xfd, 0x00, 0x1f, 0x92, 0xfd, 0x00, 0x1f, 0xb2, 0xfd, 0x00, 0xff, 0xb2, 0xfd, 0x00, 0xff, 0xb2, 0xfd, 0x00, 0xff, 0x92, 0xfd, 0x01, 0xff, 0x92, 0xfd, 0x01, 0xff, 0x92, 0xfd, 0x01, 0xff, 0x32, 0xfd, 0x7f, 0xff, 0x32, 0xfd, 0x7f, 0xff, 0x32, 0xfd, 0x7f, 0xff, 0x82, 0xfd, 0x00, 0x1f, 0x82, 0xfd, 0x00, 0x1f, 0x82, 0xfd, 0x00, 0x1f, 0xa2, 0xfd, 0x00, 0xff, 0xa2, 0xfd, 0x00, 0xff, 0xa2, 0xfd, 0x00, 0xff, 0x82, 0xfd, 0x7f, 0xff, 0x82, 0xfd, 0x7f, 0xff, 0x82, 0xfd, 0x7f, 0xff, 0x22, 0xfd, 0x01, 0xff, 0x22, 0xfd, 0x01, 0xff, 0x22, 0xfd, 0x01, 0xff, 0x71, 0xfe, 0x4d, 0x8f, 0xa2, 0xfd, 0x42, 0xfe, 0x92, 0xfd, 0x01, 0xff ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vldrb.u8 q0, [r0]" + - + asm_text: "vldrb.u8 q1, [r0]" + - + asm_text: "vldrb.u8 q0, [r11]" + - + asm_text: "vldrb.u8 q3, [r11]" + - + asm_text: "vldrb.u8 q0, [r4, #0x38]" + - + asm_text: "vldrb.u8 q4, [r4, #0x38]" + - + asm_text: "vldrb.u8 q0, [r8, #0x38]" + - + asm_text: "vldrb.u8 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u8 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u8 q5, [r4], #-0x19" + - + asm_text: "vldrb.u8 q5, [r10], #-0x19" + - + asm_text: "vldrb.u8 q5, [sp, #-0x19]" + - + asm_text: "vldrb.u8 q5, [sp, #-0x7f]" + - + asm_text: "vstrb.8 q0, [r0]" + - + asm_text: "vstrb.8 q1, [r0]" + - + asm_text: "vstrb.8 q0, [r11]" + - + asm_text: "vstrb.8 q3, [r11]" + - + asm_text: "vstrb.8 q0, [r4, #0x38]" + - + asm_text: "vstrb.8 q4, [r4, #0x38]" + - + asm_text: "vstrb.8 q0, [r8, #0x38]" + - + asm_text: "vstrb.8 q5, [r4, #0x38]!" + - + asm_text: "vstrb.8 q5, [r4, #0x38]!" + - + asm_text: "vstrb.8 q5, [r4], #-0x19" + - + asm_text: "vstrb.8 q5, [r10], #-0x19" + - + asm_text: "vstrb.8 q5, [sp, #-0x19]" + - + asm_text: "vstrb.8 q5, [sp, #0x7f]" + - + asm_text: "vldrb.u16 q0, [r0]" + - + asm_text: "vldrb.u16 q1, [r0]" + - + asm_text: "vldrb.u16 q0, [r7]" + - + asm_text: "vldrb.u16 q3, [r7]" + - + asm_text: "vldrb.u16 q0, [r4, #0x38]" + - + asm_text: "vldrb.u16 q4, [r4, #0x38]" + - + asm_text: "vldrb.u16 q0, [r2, #0x38]" + - + asm_text: "vldrb.u16 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u16 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u16 q5, [r4], #-1" + - + asm_text: "vldrb.u16 q5, [r3], #-0x19" + - + asm_text: "vldrb.u16 q5, [r6, #-0x19]" + - + asm_text: "vldrb.u16 q5, [r6, #-0x40]" + - + asm_text: "vldrb.s16 q0, [r0]" + - + asm_text: "vldrb.s16 q1, [r0]" + - + asm_text: "vldrb.s16 q0, [r7]" + - + asm_text: "vldrb.s16 q3, [r7]" + - + asm_text: "vldrb.s16 q0, [r4, #0x38]" + - + asm_text: "vldrb.s16 q4, [r4, #0x38]" + - + asm_text: "vldrb.s16 q0, [r2, #0x38]" + - + asm_text: "vldrb.s16 q5, [r4, #0x38]!" + - + asm_text: "vldrb.s16 q5, [r4, #0x38]!" + - + asm_text: "vldrb.s16 q5, [r4], #-0x19" + - + asm_text: "vldrb.s16 q5, [r3], #-0x19" + - + asm_text: "vldrb.s16 q5, [r6, #-0x19]" + - + asm_text: "vldrb.s16 q5, [r6, #-0x40]" + - + asm_text: "vstrb.16 q0, [r0]" + - + asm_text: "vstrb.16 q1, [r0]" + - + asm_text: "vstrb.16 q0, [r7]" + - + asm_text: "vstrb.16 q3, [r7]" + - + asm_text: "vstrb.16 q0, [r4, #0x38]" + - + asm_text: "vstrb.16 q4, [r4, #0x38]" + - + asm_text: "vstrb.16 q0, [r5, #0x38]" + - + asm_text: "vstrb.16 q5, [r4, #0x38]!" + - + asm_text: "vstrb.16 q5, [r4, #0x38]!" + - + asm_text: "vstrb.16 q5, [r4], #-0x19" + - + asm_text: "vstrb.16 q5, [r3], #-0x19" + - + asm_text: "vstrb.16 q5, [r2, #-0x19]" + - + asm_text: "vstrb.16 q5, [r2, #-0x40]" + - + asm_text: "vldrb.u32 q0, [r0]" + - + asm_text: "vldrb.u32 q1, [r0]" + - + asm_text: "vldrb.u32 q0, [r7]" + - + asm_text: "vldrb.u32 q3, [r7]" + - + asm_text: "vldrb.u32 q0, [r4, #0x38]" + - + asm_text: "vldrb.u32 q4, [r4, #0x38]" + - + asm_text: "vldrb.u32 q0, [r2, #0x38]" + - + asm_text: "vldrb.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u32 q5, [r4], #-0x19" + - + asm_text: "vldrb.u32 q5, [r3], #-0x19" + - + asm_text: "vldrb.u32 q5, [r6, #-0x19]" + - + asm_text: "vldrb.u32 q5, [r6, #-0x40]" + - + asm_text: "vldrb.s32 q0, [r0]" + - + asm_text: "vldrb.s32 q1, [r0]" + - + asm_text: "vldrb.s32 q0, [r7]" + - + asm_text: "vldrb.s32 q3, [r7]" + - + asm_text: "vldrb.s32 q0, [r4, #0x38]" + - + asm_text: "vldrb.s32 q4, [r4, #0x38]" + - + asm_text: "vldrb.s32 q0, [r2, #0x38]" + - + asm_text: "vldrb.s32 q5, [r4, #0x38]!" + - + asm_text: "vldrb.s32 q5, [r4, #0x38]!" + - + asm_text: "vldrb.s32 q5, [r4], #-0x19" + - + asm_text: "vldrb.s32 q5, [r3], #-0x19" + - + asm_text: "vldrb.s32 q5, [r6, #-0x19]" + - + asm_text: "vldrb.s32 q5, [r6, #-0x40]" + - + asm_text: "vstrb.32 q0, [r0]" + - + asm_text: "vstrb.32 q1, [r0]" + - + asm_text: "vstrb.32 q0, [r7]" + - + asm_text: "vstrb.32 q3, [r7]" + - + asm_text: "vstrb.32 q0, [r4, #0x38]" + - + asm_text: "vstrb.32 q4, [r4, #0x38]" + - + asm_text: "vstrb.32 q0, [r5, #0x38]" + - + asm_text: "vstrb.32 q5, [r4, #0x38]!" + - + asm_text: "vstrb.32 q5, [r4, #0x38]!" + - + asm_text: "vstrb.32 q5, [r4], #-0x19" + - + asm_text: "vstrb.32 q5, [r3], #-0x19" + - + asm_text: "vstrb.32 q5, [r2, #-0x19]" + - + asm_text: "vstrb.32 q5, [r2, #-0x40]" + - + asm_text: "vldrh.u16 q0, [r0]" + - + asm_text: "vldrh.u16 q1, [r0]" + - + asm_text: "vldrh.u16 q0, [r11]" + - + asm_text: "vldrh.u16 q3, [r11]" + - + asm_text: "vldrh.u16 q0, [r4, #0x38]" + - + asm_text: "vldrh.u16 q4, [r4, #0x38]" + - + asm_text: "vldrh.u16 q0, [r8, #0x38]" + - + asm_text: "vldrh.u16 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u16 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u16 q5, [r4], #-0x1a" + - + asm_text: "vldrh.u16 q5, [r10], #-0x1a" + - + asm_text: "vldrh.u16 q5, [sp, #-0x1a]" + - + asm_text: "vldrh.u16 q5, [sp, #-0x40]" + - + asm_text: "vldrh.u16 q5, [sp, #-0xfe]" + - + asm_text: "vldrh.u16 q5, [r10], #0xfe" + - + asm_text: "vstrh.16 q0, [r0]" + - + asm_text: "vstrh.16 q1, [r0]" + - + asm_text: "vstrh.16 q0, [r11]" + - + asm_text: "vstrh.16 q3, [r11]" + - + asm_text: "vstrh.16 q0, [r4, #0x38]" + - + asm_text: "vstrh.16 q4, [r4, #0x38]" + - + asm_text: "vstrh.16 q0, [r8, #0x38]" + - + asm_text: "vstrh.16 q5, [r4, #0x38]!" + - + asm_text: "vstrh.16 q5, [r4, #0x38]!" + - + asm_text: "vstrh.16 q5, [r4], #-0x1a" + - + asm_text: "vstrh.16 q5, [r10], #-0x1a" + - + asm_text: "vstrh.16 q5, [sp, #-0x1a]" + - + asm_text: "vstrh.16 q5, [sp, #-0x40]" + - + asm_text: "vstrh.16 q5, [sp, #-0xfe]" + - + asm_text: "vstrh.16 q5, [r10], #0xfe" + - + asm_text: "vldrh.u32 q0, [r0]" + - + asm_text: "vldrh.u32 q1, [r0]" + - + asm_text: "vldrh.u32 q0, [r7]" + - + asm_text: "vldrh.u32 q3, [r7]" + - + asm_text: "vldrh.u32 q0, [r4, #0x38]" + - + asm_text: "vldrh.u32 q4, [r4, #0x38]" + - + asm_text: "vldrh.u32 q0, [r2, #0x38]" + - + asm_text: "vldrh.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u32 q5, [r4], #-0x1a" + - + asm_text: "vldrh.u32 q5, [r3], #-0x1a" + - + asm_text: "vldrh.u32 q5, [r6, #-0x1a]" + - + asm_text: "vldrh.u32 q5, [r6, #-0x40]" + - + asm_text: "vldrh.u32 q5, [r6, #-0xfe]" + - + asm_text: "vldrh.u32 q5, [r4, #0xfe]!" + - + asm_text: "vldrh.s32 q0, [r0]" + - + asm_text: "vldrh.s32 q1, [r0]" + - + asm_text: "vldrh.s32 q0, [r7]" + - + asm_text: "vldrh.s32 q3, [r7]" + - + asm_text: "vldrh.s32 q0, [r4, #0x38]" + - + asm_text: "vldrh.s32 q4, [r4, #0x38]" + - + asm_text: "vldrh.s32 q0, [r2, #0x38]" + - + asm_text: "vldrh.s32 q5, [r4, #0x38]!" + - + asm_text: "vldrh.s32 q5, [r4, #0x38]!" + - + asm_text: "vldrh.s32 q5, [r4], #-0x1a" + - + asm_text: "vldrh.s32 q5, [r3], #-0x1a" + - + asm_text: "vldrh.s32 q5, [r6, #-0x1a]" + - + asm_text: "vldrh.s32 q5, [r6, #-0x40]" + - + asm_text: "vldrh.s32 q5, [r6, #-0xfe]" + - + asm_text: "vldrh.s32 q5, [r4, #0xfe]!" + - + asm_text: "vstrh.32 q0, [r0]" + - + asm_text: "vstrh.32 q1, [r0]" + - + asm_text: "vstrh.32 q0, [r7]" + - + asm_text: "vstrh.32 q3, [r7]" + - + asm_text: "vstrh.32 q0, [r4, #0x38]" + - + asm_text: "vstrh.32 q4, [r4, #0x38]" + - + asm_text: "vstrh.32 q0, [r5, #0x38]" + - + asm_text: "vstrh.32 q5, [r4, #0x38]!" + - + asm_text: "vstrh.32 q5, [r4, #0x38]!" + - + asm_text: "vstrh.32 q5, [r4], #-0x1a" + - + asm_text: "vstrh.32 q5, [r3], #-0x1a" + - + asm_text: "vstrh.32 q5, [r2, #-0x1a]" + - + asm_text: "vstrh.32 q5, [r2, #-0x40]" + - + asm_text: "vstrh.32 q5, [r2, #-0xfe]" + - + asm_text: "vstrh.32 q5, [r4, #0xfe]!" + - + asm_text: "vldrw.u32 q0, [r0]" + - + asm_text: "vldrw.u32 q1, [r0]" + - + asm_text: "vldrw.u32 q0, [r11]" + - + asm_text: "vldrw.u32 q3, [r11]" + - + asm_text: "vldrw.u32 q0, [r4, #0x38]" + - + asm_text: "vldrw.u32 q4, [r4, #0x38]" + - + asm_text: "vldrw.u32 q0, [r8, #0x38]" + - + asm_text: "vldrw.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrw.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrw.u32 q5, [r4], #-0x1c" + - + asm_text: "vldrw.u32 q5, [r10], #-0x1c" + - + asm_text: "vldrw.u32 q5, [sp, #-0x1c]" + - + asm_text: "vldrw.u32 q5, [sp, #-0x40]" + - + asm_text: "vldrw.u32 q5, [sp, #-0x1fc]" + - + asm_text: "vldrw.u32 q5, [r4, #0x1fc]!" + - + asm_text: "vstrw.32 q0, [r0]" + - + asm_text: "vstrw.32 q1, [r0]" + - + asm_text: "vstrw.32 q0, [r11]" + - + asm_text: "vstrw.32 q3, [r11]" + - + asm_text: "vstrw.32 q0, [r4, #0x38]" + - + asm_text: "vstrw.32 q4, [r4, #0x38]" + - + asm_text: "vstrw.32 q0, [r8, #0x38]" + - + asm_text: "vstrw.32 q5, [r4, #0x38]!" + - + asm_text: "vstrw.32 q5, [r4, #0x38]!" + - + asm_text: "vstrw.32 q5, [r4], #-0x1c" + - + asm_text: "vstrw.32 q5, [r10], #-0x1c" + - + asm_text: "vstrw.32 q5, [sp, #-0x1c]" + - + asm_text: "vstrw.32 q5, [sp, #-0x40]" + - + asm_text: "vstrw.32 q5, [sp, #-0x1fc]" + - + asm_text: "vstrw.32 q5, [r4, #0x1fc]!" + - + asm_text: "vldrb.u8 q0, [r0, q1]" + - + asm_text: "vldrb.u8 q3, [r10, q1]" + - + asm_text: "vldrb.u16 q0, [r0, q1]" + - + asm_text: "vldrb.u16 q3, [r9, q1]" + - + asm_text: "vldrb.s16 q0, [r0, q1]" + - + asm_text: "vldrb.s16 q3, [sp, q1]" + - + asm_text: "vldrb.u32 q0, [r0, q1]" + - + asm_text: "vldrb.u32 q3, [r0, q1]" + - + asm_text: "vldrb.s32 q0, [r0, q1]" + - + asm_text: "vldrb.s32 q3, [r0, q1]" + - + asm_text: "vldrh.u16 q0, [r0, q1]" + - + asm_text: "vldrh.u16 q3, [r0, q1]" + - + asm_text: "vldrh.u32 q0, [r0, q1]" + - + asm_text: "vldrh.u32 q3, [r0, q1]" + - + asm_text: "vldrh.s32 q0, [r0, q1]" + - + asm_text: "vldrh.s32 q3, [r0, q1]" + - + asm_text: "vldrh.u16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vldrw.u32 q0, [r0, q1]" + - + asm_text: "vldrw.u32 q3, [r0, q1]" + - + asm_text: "vldrw.u32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vldrw.u32 q0, [sp, q1, uxtw #2]" + - + asm_text: "vldrd.u64 q0, [r0, q1]" + - + asm_text: "vldrd.u64 q3, [r0, q1]" + - + asm_text: "vldrd.u64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vldrd.u64 q0, [sp, q1, uxtw #3]" + - + asm_text: "vstrb.8 q0, [r0, q1]" + - + asm_text: "vstrb.8 q3, [r10, q1]" + - + asm_text: "vstrb.8 q3, [r0, q3]" + - + asm_text: "vstrb.16 q0, [r0, q1]" + - + asm_text: "vstrb.16 q3, [sp, q1]" + - + asm_text: "vstrb.16 q3, [r0, q3]" + - + asm_text: "vstrb.32 q0, [r0, q1]" + - + asm_text: "vstrb.32 q3, [r0, q1]" + - + asm_text: "vstrb.32 q3, [r0, q3]" + - + asm_text: "vstrh.16 q0, [r0, q1]" + - + asm_text: "vstrh.16 q3, [r0, q1]" + - + asm_text: "vstrh.16 q3, [r0, q3]" + - + asm_text: "vstrh.32 q0, [r0, q1]" + - + asm_text: "vstrh.32 q3, [r0, q1]" + - + asm_text: "vstrh.32 q3, [r0, q3]" + - + asm_text: "vstrh.16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vstrh.32 q3, [r8, q3, uxtw #1]" + - + asm_text: "vstrw.32 q0, [r0, q1]" + - + asm_text: "vstrw.32 q3, [r0, q1]" + - + asm_text: "vstrw.32 q3, [r0, q3]" + - + asm_text: "vstrw.32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vstrw.32 q0, [sp, q1, uxtw #2]" + - + asm_text: "vstrd.64 q0, [r0, q1]" + - + asm_text: "vstrd.64 q3, [r0, q1]" + - + asm_text: "vstrd.64 q3, [r0, q3]" + - + asm_text: "vstrd.64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vstrd.64 q0, [sp, q1, uxtw #3]" + - + asm_text: "vldrw.u32 q0, [q1]" + - + asm_text: "vldrw.u32 q7, [q1]" + - + asm_text: "vldrw.u32 q7, [q1]!" + - + asm_text: "vldrw.u32 q7, [q1, #4]" + - + asm_text: "vldrw.u32 q7, [q1, #-4]" + - + asm_text: "vldrw.u32 q7, [q1, #0x1fc]" + - + asm_text: "vldrw.u32 q7, [q1, #-0x1fc]" + - + asm_text: "vldrw.u32 q7, [q1, #0x108]" + - + asm_text: "vldrw.u32 q7, [q1, #4]!" + - + asm_text: "vstrw.32 q0, [q1]" + - + asm_text: "vstrw.32 q1, [q1]" + - + asm_text: "vstrw.32 q7, [q1]" + - + asm_text: "vstrw.32 q7, [q1]!" + - + asm_text: "vstrw.32 q7, [q7]" + - + asm_text: "vstrw.32 q7, [q1, #4]" + - + asm_text: "vstrw.32 q7, [q1, #-4]" + - + asm_text: "vstrw.32 q7, [q1, #0x1fc]" + - + asm_text: "vstrw.32 q7, [q1, #-0x1fc]" + - + asm_text: "vstrw.32 q7, [q1, #0x108]!" + - + asm_text: "vldrd.u64 q0, [q1]" + - + asm_text: "vldrd.u64 q7, [q1]" + - + asm_text: "vldrd.u64 q7, [q1]!" + - + asm_text: "vldrd.u64 q7, [q1, #8]" + - + asm_text: "vldrd.u64 q7, [q1, #-8]" + - + asm_text: "vldrd.u64 q7, [q1, #0x3f8]" + - + asm_text: "vldrd.u64 q7, [q1, #-0x3f8]" + - + asm_text: "vldrd.u64 q7, [q1, #0x108]" + - + asm_text: "vldrd.u64 q7, [q1, #0x270]" + - + asm_text: "vldrd.u64 q7, [q1, #0x108]" + - + asm_text: "vldrd.u64 q7, [q1, #-0x3f8]!" + - + asm_text: "vstrd.64 q0, [q1]" + - + asm_text: "vstrd.64 q1, [q1]" + - + asm_text: "vstrd.64 q7, [q1]" + - + asm_text: "vstrd.64 q7, [q1]!" + - + asm_text: "vstrd.64 q7, [q7]" + - + asm_text: "vstrd.64 q7, [q1, #8]" + - + asm_text: "vstrd.64 q7, [q1, #-8]!" + - + asm_text: "vstrd.64 q7, [q1, #0x3f8]" + - + asm_text: "vstrd.64 q7, [q1, #-0x3f8]" + - + asm_text: "vstrd.64 q7, [q1, #0x108]" + - + asm_text: "vstrd.64 q7, [q1, #0x270]" + - + asm_text: "vstrd.64 q7, [q1, #0x108]" + - + asm_text: "vldrb.u8 q0, [r0]" + - + asm_text: "vldrb.u8 q0, [r0]" + - + asm_text: "vldrb.u8 q0, [r8, #0x38]" + - + asm_text: "vldrb.u8 q0, [r8, #0x38]" + - + asm_text: "vldrb.u8 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u8 q5, [r4, #0x38]!" + - + asm_text: "vstrb.8 q0, [r0]" + - + asm_text: "vstrb.8 q0, [r0]" + - + asm_text: "vstrb.8 q4, [r4, #0x38]" + - + asm_text: "vstrb.8 q4, [r4, #0x38]" + - + asm_text: "vstrb.8 q5, [r4, #0x38]!" + - + asm_text: "vstrb.8 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u16 q0, [r0]" + - + asm_text: "vldrh.u16 q0, [r0]" + - + asm_text: "vldrh.u16 q0, [r0]" + - + asm_text: "vldrh.u16 q0, [r4, #0x38]" + - + asm_text: "vldrh.u16 q0, [r4, #0x38]" + - + asm_text: "vldrh.u16 q0, [r4, #0x38]" + - + asm_text: "vldrh.u16 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u16 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u16 q5, [r4, #0x38]!" + - + asm_text: "vstrh.16 q0, [r0]" + - + asm_text: "vstrh.16 q0, [r0]" + - + asm_text: "vstrh.16 q0, [r0]" + - + asm_text: "vstrh.16 q0, [r4, #0x38]" + - + asm_text: "vstrh.16 q0, [r4, #0x38]" + - + asm_text: "vstrh.16 q0, [r4, #0x38]" + - + asm_text: "vstrh.16 q5, [r4, #0x38]!" + - + asm_text: "vstrh.16 q5, [r4, #0x38]!" + - + asm_text: "vstrh.16 q5, [r4, #0x38]!" + - + asm_text: "vldrw.u32 q0, [r0]" + - + asm_text: "vldrw.u32 q0, [r0]" + - + asm_text: "vldrw.u32 q0, [r0]" + - + asm_text: "vldrw.u32 q0, [r4, #0x38]" + - + asm_text: "vldrw.u32 q0, [r4, #0x38]" + - + asm_text: "vldrw.u32 q0, [r4, #0x38]" + - + asm_text: "vldrw.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrw.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrw.u32 q5, [r4, #0x38]!" + - + asm_text: "vstrw.32 q0, [r0]" + - + asm_text: "vstrw.32 q0, [r0]" + - + asm_text: "vstrw.32 q0, [r0]" + - + asm_text: "vstrw.32 q0, [r4, #0x38]" + - + asm_text: "vstrw.32 q0, [r4, #0x38]" + - + asm_text: "vstrw.32 q0, [r4, #0x38]" + - + asm_text: "vstrw.32 q5, [r4, #0x38]!" + - + asm_text: "vstrw.32 q5, [r4, #0x38]!" + - + asm_text: "vstrw.32 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u8 q0, [r0, q1]" + - + asm_text: "vldrb.u8 q0, [r0, q1]" + - + asm_text: "vldrh.u16 q3, [r0, q1]" + - + asm_text: "vldrh.u16 q3, [r0, q1]" + - + asm_text: "vldrh.u16 q3, [r0, q1]" + - + asm_text: "vldrh.u16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vldrh.u16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vldrh.u16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vldrw.u32 q0, [r0, q1]" + - + asm_text: "vldrw.u32 q0, [r0, q1]" + - + asm_text: "vldrw.u32 q0, [r0, q1]" + - + asm_text: "vldrw.u32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vldrw.u32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vldrw.u32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vldrd.u64 q0, [r0, q1]" + - + asm_text: "vldrd.u64 q0, [r0, q1]" + - + asm_text: "vldrd.u64 q0, [r0, q1]" + - + asm_text: "vldrd.u64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vldrd.u64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vldrd.u64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vstrb.8 q0, [r0, q1]" + - + asm_text: "vstrb.8 q0, [r0, q1]" + - + asm_text: "vstrh.16 q3, [r0, q1]" + - + asm_text: "vstrh.16 q3, [r0, q1]" + - + asm_text: "vstrh.16 q3, [r0, q1]" + - + asm_text: "vstrh.16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vstrh.16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vstrh.16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vstrw.32 q0, [r0, q1]" + - + asm_text: "vstrw.32 q0, [r0, q1]" + - + asm_text: "vstrw.32 q0, [r0, q1]" + - + asm_text: "vstrw.32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vstrw.32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vstrw.32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vstrd.64 q3, [r0, q1]" + - + asm_text: "vstrd.64 q3, [r0, q1]" + - + asm_text: "vstrd.64 q3, [r0, q1]" + - + asm_text: "vstrd.64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vstrd.64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vstrd.64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vldrw.u32 q0, [q1]" + - + asm_text: "vldrw.u32 q0, [q1]" + - + asm_text: "vldrw.u32 q0, [q1]" + - + asm_text: "vldrw.u32 q7, [q1]!" + - + asm_text: "vldrw.u32 q7, [q1]!" + - + asm_text: "vldrw.u32 q7, [q1]!" + - + asm_text: "vldrw.u32 q7, [q1, #4]" + - + asm_text: "vldrw.u32 q7, [q1, #4]" + - + asm_text: "vldrw.u32 q7, [q1, #4]" + - + asm_text: "vldrw.u32 q7, [q1, #4]!" + - + asm_text: "vldrw.u32 q7, [q1, #4]!" + - + asm_text: "vldrw.u32 q7, [q1, #4]!" + - + asm_text: "vstrw.32 q0, [q1]" + - + asm_text: "vstrw.32 q0, [q1]" + - + asm_text: "vstrw.32 q0, [q1]" + - + asm_text: "vstrw.32 q7, [q1]!" + - + asm_text: "vstrw.32 q7, [q1]!" + - + asm_text: "vstrw.32 q7, [q1]!" + - + asm_text: "vstrw.32 q7, [q1, #0x1fc]" + - + asm_text: "vstrw.32 q7, [q1, #0x1fc]" + - + asm_text: "vstrw.32 q7, [q1, #0x1fc]" + - + asm_text: "vstrw.32 q7, [q1, #0x108]!" + - + asm_text: "vstrw.32 q7, [q1, #0x108]!" + - + asm_text: "vstrw.32 q7, [q1, #0x108]!" + - + asm_text: "vldrd.u64 q0, [q1]" + - + asm_text: "vldrd.u64 q0, [q1]" + - + asm_text: "vldrd.u64 q0, [q1]" + - + asm_text: "vldrd.u64 q7, [q1]!" + - + asm_text: "vldrd.u64 q7, [q1]!" + - + asm_text: "vldrd.u64 q7, [q1]!" + - + asm_text: "vldrd.u64 q7, [q1, #8]" + - + asm_text: "vldrd.u64 q7, [q1, #8]" + - + asm_text: "vldrd.u64 q7, [q1, #8]" + - + asm_text: "vldrd.u64 q7, [q1, #-0x3f8]!" + - + asm_text: "vldrd.u64 q7, [q1, #-0x3f8]!" + - + asm_text: "vldrd.u64 q7, [q1, #-0x3f8]!" + - + asm_text: "vstrd.64 q0, [q1]" + - + asm_text: "vstrd.64 q0, [q1]" + - + asm_text: "vstrd.64 q0, [q1]" + - + asm_text: "vstrd.64 q7, [q1]!" + - + asm_text: "vstrd.64 q7, [q1]!" + - + asm_text: "vstrd.64 q7, [q1]!" + - + asm_text: "vstrd.64 q7, [q1, #0x3f8]" + - + asm_text: "vstrd.64 q7, [q1, #0x3f8]" + - + asm_text: "vstrd.64 q7, [q1, #0x3f8]" + - + asm_text: "vstrd.64 q7, [q1, #-8]!" + - + asm_text: "vstrd.64 q7, [q1, #-8]!" + - + asm_text: "vstrd.64 q7, [q1, #-8]!" + - + asm_text: "vpste" + - + asm_text: "vstrwt.32 q7, [q1, #0x108]!" + - + asm_text: "vldrde.u64 q7, [q1, #8]" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-minmax.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-minmax.s.yaml new file mode 100644 index 0000000..53d8e24 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-minmax.s.yaml @@ -0,0 +1,42 @@ +test_cases: + - + input: + bytes: [ 0x02, 0xff, 0x58, 0x0f, 0x30, 0xff, 0x52, 0x6f, 0x00, 0xef, 0x5e, 0x66, 0x12, 0xef, 0x54, 0x06, 0x22, 0xef, 0x54, 0x06, 0x02, 0xff, 0x54, 0x06, 0x12, 0xff, 0x54, 0x06, 0x22, 0xff, 0x54, 0x06, 0x00, 0xef, 0x4e, 0x66, 0x12, 0xef, 0x44, 0x06, 0x22, 0xef, 0x44, 0x06, 0x02, 0xff, 0x44, 0x06, 0x12, 0xff, 0x44, 0x06, 0x22, 0xff, 0x44, 0x06, 0x71, 0xfe, 0x4d, 0x8f, 0x02, 0xef, 0x54, 0x06, 0x12, 0xef, 0x54, 0x06 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmaxnm.f32 q0, q1, q4" + - + asm_text: "vminnm.f16 q3, q0, q1" + - + asm_text: "vmin.s8 q3, q0, q7" + - + asm_text: "vmin.s16 q0, q1, q2" + - + asm_text: "vmin.s32 q0, q1, q2" + - + asm_text: "vmin.u8 q0, q1, q2" + - + asm_text: "vmin.u16 q0, q1, q2" + - + asm_text: "vmin.u32 q0, q1, q2" + - + asm_text: "vmax.s8 q3, q0, q7" + - + asm_text: "vmax.s16 q0, q1, q2" + - + asm_text: "vmax.s32 q0, q1, q2" + - + asm_text: "vmax.u8 q0, q1, q2" + - + asm_text: "vmax.u16 q0, q1, q2" + - + asm_text: "vmax.u32 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vmint.s8 q0, q1, q2" + - + asm_text: "vmine.s16 q0, q1, q2" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-misc.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-misc.s.yaml new file mode 100644 index 0000000..ed29128 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-misc.s.yaml @@ -0,0 +1,66 @@ +test_cases: + - + input: + bytes: [ 0x3b, 0xfe, 0x05, 0x0f, 0x31, 0xfe, 0x4d, 0x0f, 0x00, 0xf0, 0x43, 0xc3, 0x10, 0xf0, 0x43, 0xc3, 0x24, 0xf0, 0x49, 0xcd, 0x3e, 0xf0, 0xe9, 0xcd, 0x05, 0xf0, 0xb7, 0xc6, 0x11, 0xf0, 0x13, 0xc2, 0x27, 0xf0, 0xe3, 0xc7, 0x01, 0xf0, 0x0d, 0xc9, 0x0a, 0xf0, 0xbf, 0xc2, 0x0a, 0xf0, 0xc1, 0xc2, 0x0a, 0xf0, 0x9b, 0xcc, 0x0a, 0xf0, 0xfb, 0xcf, 0x0b, 0xf0, 0xd1, 0xca, 0x35, 0xf0, 0x01, 0xc0, 0x05, 0xf0, 0x01, 0xe0, 0x15, 0xf0, 0x01, 0xe0, 0x27, 0xf0, 0x01, 0xe0, 0x32, 0xf0, 0x01, 0xe0, 0x1f, 0xf0, 0x01, 0xc8, 0x1f, 0xf0, 0x05, 0xc0, 0x1f, 0xf0, 0xff, 0xcf, 0x0f, 0xf0, 0x01, 0xe0, 0x08, 0xbf, 0x0f, 0xf0, 0x01, 0xe0, 0x71, 0xfe, 0x4d, 0x8f, 0x33, 0xfe, 0x05, 0x0f, 0x33, 0xfe, 0x05, 0x0f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vpsel q0, q5, q2" + - + asm_text: "vpnot" + - + asm_text: "wlstp.8 lr, r0, #0x684" + - + asm_text: "wlstp.16 lr, r0, #0x684" + - + asm_text: "wlstp.32 lr, r4, #0xa92" + - + asm_text: "wlstp.64 lr, lr, #0xbd2" + - + asm_text: "wlstp.8 lr, r5, #0xd6c" + - + asm_text: "wlstp.16 lr, r1, #0x424" + - + asm_text: "wlstp.32 lr, r7, #0xfc4" + - + asm_text: "wlstp.8 lr, r1, #0x21a" + - + asm_text: "wlstp.8 lr, r10, #0x57c" + - + asm_text: "wlstp.8 lr, r10, #0x580" + - + asm_text: "wlstp.8 lr, r10, #0x936" + - + asm_text: "wlstp.8 lr, r10, #0xff6" + - + asm_text: "wlstp.8 lr, r11, #0x5a2" + - + asm_text: "wlstp.64 lr, r5, #0" + - + asm_text: "dlstp.8 lr, r5" + - + asm_text: "dlstp.16 lr, r5" + - + asm_text: "dlstp.32 lr, r7" + - + asm_text: "dlstp.64 lr, r2" + - + asm_text: "letp lr, #-2" + - + asm_text: "letp lr, #-8" + - + asm_text: "letp lr, #-0xffe" + - + asm_text: "lctp" + - + asm_text: "it eq" + - + asm_text: "lctpeq" + - + asm_text: "vpste" + - + asm_text: "vpselt q0, q1, q2" + - + asm_text: "vpsele q0, q1, q2" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-qdest-qsrc.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-qdest-qsrc.s.yaml new file mode 100644 index 0000000..98ecfc2 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-qdest-qsrc.s.yaml @@ -0,0 +1,276 @@ +test_cases: + - + input: + bytes: [ 0x3f, 0xee, 0x09, 0x2e, 0x3f, 0xfe, 0x03, 0x1e, 0xb2, 0xee, 0xc0, 0x0b, 0xf3, 0xee, 0xc2, 0x0b, 0x3f, 0xee, 0x09, 0x3e, 0x0c, 0xee, 0x0c, 0x3e, 0x12, 0xee, 0x08, 0x1e, 0x26, 0xee, 0x0e, 0x1e, 0x02, 0xee, 0x02, 0x0e, 0x14, 0xee, 0x04, 0x0e, 0x2a, 0xee, 0x0e, 0x2e, 0x0e, 0xee, 0x01, 0x1e, 0x10, 0xee, 0x03, 0x1e, 0x20, 0xee, 0x09, 0x3e, 0x22, 0xee, 0x01, 0x3e, 0x20, 0xee, 0x03, 0x3e, 0x0c, 0xee, 0x05, 0x0e, 0x1a, 0xee, 0x09, 0x2e, 0x24, 0xee, 0x05, 0x0e, 0x08, 0xfe, 0x0e, 0x3e, 0x14, 0xfe, 0x0a, 0x1e, 0x28, 0xfe, 0x0c, 0x7e, 0x06, 0xfe, 0x0c, 0x0e, 0x18, 0xfe, 0x02, 0x0e, 0x2a, 0xfe, 0x00, 0x4e, 0x06, 0xfe, 0x03, 0x1e, 0x12, 0xfe, 0x09, 0x1e, 0x2c, 0xfe, 0x07, 0x3e, 0x06, 0xfe, 0x01, 0x6e, 0x1e, 0xfe, 0x09, 0x0e, 0x2c, 0xfe, 0x0f, 0x0e, 0x20, 0xfe, 0x0f, 0x0e, 0x2c, 0xfe, 0x01, 0x0e, 0x32, 0xee, 0x05, 0x0e, 0x34, 0xee, 0x0a, 0xce, 0x30, 0xee, 0x0b, 0x2e, 0x30, 0xee, 0x0a, 0x3e, 0x30, 0xee, 0x0b, 0x3e, 0x30, 0xee, 0x03, 0x3e, 0x3e, 0xfe, 0x0a, 0x2e, 0x38, 0xfe, 0x05, 0x6e, 0x32, 0xfe, 0x06, 0xbe, 0x3e, 0xfe, 0x09, 0x1e, 0x0d, 0xee, 0x00, 0x4e, 0x19, 0xee, 0x06, 0x6e, 0x2b, 0xee, 0x0c, 0x6e, 0x0d, 0xee, 0x04, 0x1e, 0x11, 0xee, 0x04, 0x1e, 0x29, 0xee, 0x08, 0x5e, 0x37, 0xee, 0x0e, 0x4e, 0x33, 0xfe, 0x06, 0x0e, 0x33, 0xee, 0x0e, 0x3e, 0x3f, 0xfe, 0x0e, 0x1e, 0x09, 0xee, 0x0b, 0x0e, 0x1f, 0xee, 0x09, 0x0e, 0x2f, 0xee, 0x09, 0x0e, 0x0b, 0xfe, 0x05, 0x6e, 0x1f, 0xfe, 0x09, 0x4e, 0x27, 0xfe, 0x05, 0x2e, 0x03, 0xee, 0x05, 0x3e, 0x13, 0xee, 0x05, 0x3e, 0x23, 0xee, 0x01, 0x7e, 0x0d, 0xfe, 0x01, 0x3e, 0x17, 0xfe, 0x0d, 0x9e, 0x25, 0xfe, 0x05, 0x3e, 0x33, 0xee, 0x03, 0x0e, 0x33, 0xee, 0x01, 0x5e, 0x37, 0xee, 0x0b, 0x0e, 0x37, 0xee, 0x03, 0x1e, 0x33, 0xfe, 0x09, 0x0e, 0x33, 0xfe, 0x0f, 0x1e, 0x37, 0xfe, 0x09, 0x0e, 0x37, 0xfe, 0x05, 0x1e, 0x3f, 0xee, 0x09, 0x2e, 0x3f, 0xee, 0x09, 0x3e, 0x3f, 0xfe, 0x07, 0x0e, 0x3f, 0xfe, 0x03, 0x1e, 0x31, 0xee, 0x87, 0x0e, 0x31, 0xee, 0x83, 0x9e, 0x35, 0xee, 0x8f, 0x2e, 0x35, 0xee, 0x85, 0x1e, 0x31, 0xfe, 0x8b, 0x2e, 0x31, 0xfe, 0x81, 0x1e, 0x35, 0xfe, 0x81, 0x2e, 0x35, 0xfe, 0x87, 0x7e, 0x0e, 0xee, 0x0a, 0x6f, 0x10, 0xee, 0x0c, 0x0f, 0x10, 0xee, 0x0c, 0x0f, 0x12, 0xee, 0x00, 0x7f, 0x28, 0xee, 0x0a, 0x6f, 0x2e, 0xee, 0x04, 0xdf, 0x30, 0xee, 0x04, 0x2f, 0x32, 0xee, 0x02, 0x1f, 0x00, 0xfe, 0x04, 0x2f, 0x14, 0xfe, 0x06, 0x0f, 0x1a, 0xfe, 0x0a, 0x1f, 0x24, 0xfe, 0x0a, 0x8f, 0x2a, 0xfe, 0x00, 0xbf, 0x32, 0xfe, 0x02, 0x6f, 0x3c, 0xfe, 0x04, 0x5f, 0x38, 0xee, 0x0b, 0x0f, 0x3c, 0xee, 0x0b, 0x1f, 0x36, 0xfe, 0x0f, 0x0f, 0x3e, 0xfe, 0x0b, 0x1f, 0x32, 0xee, 0x01, 0x0f, 0x30, 0xee, 0x0b, 0x1f, 0x32, 0xee, 0x05, 0x1f, 0x30, 0xee, 0x60, 0x0f, 0x20, 0xfe, 0x02, 0x1f, 0x90, 0xfd, 0x42, 0x08, 0x20, 0xee, 0x02, 0x1f, 0x10, 0xee, 0x02, 0x1f, 0xb0, 0xff, 0xc0, 0x00, 0x71, 0xfe, 0x4d, 0x8f, 0x32, 0xfe, 0x05, 0x1f, 0x32, 0xee, 0x05, 0x0f, 0x71, 0xfe, 0x4d, 0x8f, 0x33, 0xee, 0x04, 0x1e, 0x33, 0xfe, 0x04, 0x0e, 0x71, 0xfe, 0x4d, 0x8f, 0x32, 0xee, 0x04, 0x1e, 0x32, 0xee, 0x04, 0x1e, 0x71, 0xfe, 0x4d, 0xcf, 0x3f, 0xee, 0x03, 0x0e, 0xb7, 0xff, 0x42, 0x01, 0x77, 0xee, 0xc1, 0x9f, 0x3f, 0xee, 0x01, 0x5e, 0x3f, 0xfe, 0x01, 0x3e, 0x77, 0xee, 0xc1, 0x9f, 0x3f, 0xee, 0x01, 0x4e, 0x3f, 0xfe, 0x01, 0x2e, 0x0c, 0xbf, 0xb3, 0xee, 0xe0, 0x0a, 0xb3, 0xee, 0xe0, 0x0a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcvtb.f16.f32 q1, q4" + - + asm_text: "vcvtt.f32.f16 q0, q1" + - + asm_text: "vcvtt.f64.f16 d0, s0" + - + asm_text: "vcvtt.f16.f64 s1, d2" + - + asm_text: "vcvtt.f16.f32 q1, q4" + - + asm_text: "vqdmladhx.s8 q1, q6, q6" + - + asm_text: "vqdmladhx.s16 q0, q1, q4" + - + asm_text: "vqdmladhx.s32 q0, q3, q7" + - + asm_text: "vqdmladh.s8 q0, q1, q1" + - + asm_text: "vqdmladh.s16 q0, q2, q2" + - + asm_text: "vqdmladh.s32 q1, q5, q7" + - + asm_text: "vqrdmladhx.s8 q0, q7, q0" + - + asm_text: "vqrdmladhx.s16 q0, q0, q1" + - + asm_text: "vqrdmladhx.s32 q1, q0, q4" + - + asm_text: "vqrdmladhx.s32 q1, q1, q0" + - + asm_text: "vqrdmladhx.s32 q1, q0, q1" + - + asm_text: "vqrdmladh.s8 q0, q6, q2" + - + asm_text: "vqrdmladh.s16 q1, q5, q4" + - + asm_text: "vqrdmladh.s32 q0, q2, q2" + - + asm_text: "vqdmlsdhx.s8 q1, q4, q7" + - + asm_text: "vqdmlsdhx.s16 q0, q2, q5" + - + asm_text: "vqdmlsdhx.s32 q3, q4, q6" + - + asm_text: "vqdmlsdh.s8 q0, q3, q6" + - + asm_text: "vqdmlsdh.s16 q0, q4, q1" + - + asm_text: "vqdmlsdh.s32 q2, q5, q0" + - + asm_text: "vqrdmlsdhx.s8 q0, q3, q1" + - + asm_text: "vqrdmlsdhx.s16 q0, q1, q4" + - + asm_text: "vqrdmlsdhx.s32 q1, q6, q3" + - + asm_text: "vqrdmlsdh.s8 q3, q3, q0" + - + asm_text: "vqrdmlsdh.s16 q0, q7, q4" + - + asm_text: "vqrdmlsdh.s32 q0, q6, q7" + - + asm_text: "vqrdmlsdh.s32 q0, q0, q7" + - + asm_text: "vqrdmlsdh.s32 q0, q6, q0" + - + asm_text: "vcmul.f16 q0, q1, q2, #0x5a" + - + asm_text: "vcmul.f16 q6, q2, q5, #0" + - + asm_text: "vcmul.f16 q1, q0, q5, #0x5a" + - + asm_text: "vcmul.f16 q1, q0, q5, #0xb4" + - + asm_text: "vcmul.f16 q1, q0, q5, #0x10e" + - + asm_text: "vcmul.f16 q1, q0, q1, #0x10e" + - + asm_text: "vcmul.f32 q1, q7, q5, #0" + - + asm_text: "vcmul.f32 q3, q4, q2, #0x5a" + - + asm_text: "vcmul.f32 q5, q1, q3, #0xb4" + - + asm_text: "vcmul.f32 q0, q7, q4, #0x10e" + - + asm_text: "vmullb.s8 q2, q6, q0" + - + asm_text: "vmullb.s16 q3, q4, q3" + - + asm_text: "vmullb.s32 q3, q5, q6" + - + asm_text: "vmullt.s8 q0, q6, q2" + - + asm_text: "vmullt.s16 q0, q0, q2" + - + asm_text: "vmullt.s32 q2, q4, q4" + - + asm_text: "vmullb.p8 q2, q3, q7" + - + asm_text: "vmullb.p16 q0, q1, q3" + - + asm_text: "vmullt.p8 q1, q1, q7" + - + asm_text: "vmullt.p16 q0, q7, q7" + - + asm_text: "vmulh.s8 q0, q4, q5" + - + asm_text: "vmulh.s16 q0, q7, q4" + - + asm_text: "vmulh.s32 q0, q7, q4" + - + asm_text: "vmulh.u8 q3, q5, q2" + - + asm_text: "vmulh.u16 q2, q7, q4" + - + asm_text: "vmulh.u32 q1, q3, q2" + - + asm_text: "vrmulh.s8 q1, q1, q2" + - + asm_text: "vrmulh.s16 q1, q1, q2" + - + asm_text: "vrmulh.s32 q3, q1, q0" + - + asm_text: "vrmulh.u8 q1, q6, q0" + - + asm_text: "vrmulh.u16 q4, q3, q6" + - + asm_text: "vrmulh.u32 q1, q2, q2" + - + asm_text: "vqmovnb.s16 q0, q1" + - + asm_text: "vqmovnt.s16 q2, q0" + - + asm_text: "vqmovnb.s32 q0, q5" + - + asm_text: "vqmovnt.s32 q0, q1" + - + asm_text: "vqmovnb.u16 q0, q4" + - + asm_text: "vqmovnt.u16 q0, q7" + - + asm_text: "vqmovnb.u32 q0, q4" + - + asm_text: "vqmovnt.u32 q0, q2" + - + asm_text: "vcvtb.f16.f32 q1, q4" + - + asm_text: "vcvtt.f16.f32 q1, q4" + - + asm_text: "vcvtb.f32.f16 q0, q3" + - + asm_text: "vcvtt.f32.f16 q0, q1" + - + asm_text: "vqmovunb.s16 q0, q3" + - + asm_text: "vqmovunt.s16 q4, q1" + - + asm_text: "vqmovunb.s32 q1, q7" + - + asm_text: "vqmovunt.s32 q0, q2" + - + asm_text: "vmovnb.i16 q1, q5" + - + asm_text: "vmovnt.i16 q0, q0" + - + asm_text: "vmovnb.i32 q1, q0" + - + asm_text: "vmovnt.i32 q3, q3" + - + asm_text: "vhcadd.s8 q3, q7, q5, #0x5a" + - + asm_text: "vhcadd.s16 q0, q0, q6, #0x5a" + - + asm_text: "vhcadd.s16 q0, q0, q6, #0x5a" + - + asm_text: "vhcadd.s16 q3, q1, q0, #0x10e" + - + asm_text: "vhcadd.s32 q3, q4, q5, #0x5a" + - + asm_text: "vhcadd.s32 q6, q7, q2, #0x10e" + - + asm_text: "vadc.i32 q1, q0, q2" + - + asm_text: "vadci.i32 q0, q1, q1" + - + asm_text: "vcadd.i8 q1, q0, q2, #0x5a" + - + asm_text: "vcadd.i16 q0, q2, q3, #0x5a" + - + asm_text: "vcadd.i16 q0, q5, q5, #0x10e" + - + asm_text: "vcadd.i32 q4, q2, q5, #0x5a" + - + asm_text: "vcadd.i32 q5, q5, q0, #0x10e" + - + asm_text: "vsbc.i32 q3, q1, q1" + - + asm_text: "vsbci.i32 q2, q6, q2" + - + asm_text: "vqdmullb.s16 q0, q4, q5" + - + asm_text: "vqdmullt.s16 q0, q6, q5" + - + asm_text: "vqdmullb.s32 q0, q3, q7" + - + asm_text: "vqdmullt.s32 q0, q7, q5" + - + asm_text: "vqdmullb.s16 q0, q1, q0" + - + asm_text: "vqdmullt.s16 q0, q0, q5" + - + asm_text: "vqdmullt.s16 q0, q1, q2" + - + asm_text: "vqdmullb.s16 q0, q0, r0" + - + asm_text: "vcadd.i32 q0, q0, q1, #0x10e" + - + asm_text: "vcadd.f32 q0, q0, q1, #0x10e" + - + asm_text: "vhcadd.s32 q0, q0, q1, #0x10e" + - + asm_text: "vhcadd.s16 q0, q0, q1, #0x10e" + - + asm_text: "vrev32.8 q0, q0" + - + asm_text: "vpste" + - + asm_text: "vqdmulltt.s32 q0, q1, q2" + - + asm_text: "vqdmullbe.s16 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vmulltt.p8 q0, q1, q2" + - + asm_text: "vmullbe.p16 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vcmult.f16 q0, q1, q2, #0xb4" + - + asm_text: "vcmule.f16 q0, q1, q2, #0xb4" + - + asm_text: "vpstet" + - + asm_text: "vcvtbt.f16.f32 q0, q1" + - + asm_text: "vcvtne.s16.f16 q0, q1" + - + asm_text: "vpte.f32 lt, q3, r1" + - + asm_text: "vcvttt.f16.f32 q2, q0" + - + asm_text: "vcvtte.f32.f16 q1, q0" + - + asm_text: "vpte.f32 lt, q3, r1" + - + asm_text: "vcvtbt.f16.f32 q2, q0" + - + asm_text: "vcvtbe.f32.f16 q1, q0" + - + asm_text: "ite eq" + - + asm_text: "vcvtteq.f16.f32 s0, s1" + - + asm_text: "vcvttne.f16.f32 s0, s1" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-qdest-rsrc.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-qdest-rsrc.s.yaml new file mode 100644 index 0000000..8e23f31 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-qdest-rsrc.s.yaml @@ -0,0 +1,292 @@ +test_cases: + - + input: + bytes: [ 0x07, 0xee, 0x43, 0x1f, 0x1f, 0xee, 0x4e, 0x1f, 0x2b, 0xee, 0x4a, 0x3f, 0x09, 0xee, 0x47, 0x2f, 0x1d, 0xee, 0x4b, 0x0f, 0x23, 0xee, 0x46, 0x0f, 0x04, 0xee, 0x68, 0x5f, 0x18, 0xee, 0x60, 0x3f, 0x24, 0xee, 0x60, 0x1f, 0x02, 0xfe, 0x62, 0x1f, 0x14, 0xfe, 0x66, 0x1f, 0x24, 0xfe, 0x62, 0x1f, 0x0c, 0xee, 0x61, 0x0f, 0x18, 0xee, 0x62, 0x6f, 0x2a, 0xee, 0x6b, 0x0f, 0x02, 0xfe, 0x68, 0x0f, 0x1a, 0xfe, 0x69, 0x0f, 0x20, 0xfe, 0x67, 0x0f, 0x32, 0xee, 0x66, 0x0f, 0x36, 0xfe, 0x0f, 0x0f, 0x32, 0xee, 0x60, 0x1f, 0x38, 0xfe, 0x65, 0x1f, 0x36, 0xfe, 0x47, 0x1f, 0x32, 0xee, 0x4a, 0x3f, 0x32, 0xfe, 0x4e, 0x0f, 0x38, 0xee, 0x44, 0x2f, 0x06, 0xee, 0x4e, 0x1f, 0x10, 0xee, 0x46, 0x1f, 0x24, 0xee, 0x47, 0x3f, 0x0c, 0xfe, 0x45, 0x3f, 0x18, 0xfe, 0x4a, 0x1f, 0x28, 0xfe, 0x4c, 0x1f, 0x04, 0xee, 0x41, 0x0f, 0x14, 0xee, 0x41, 0x0f, 0x20, 0xee, 0x4a, 0x0f, 0x0a, 0xfe, 0x4e, 0x0f, 0x14, 0xfe, 0x42, 0x2f, 0x24, 0xfe, 0x4b, 0x0f, 0x33, 0xee, 0xe0, 0x1e, 0x37, 0xee, 0xe3, 0x1e, 0x3b, 0xee, 0xee, 0x1e, 0x33, 0xfe, 0xe0, 0x1e, 0x37, 0xfe, 0xe2, 0x1e, 0x3b, 0xfe, 0xe3, 0x1e, 0x31, 0xee, 0xe0, 0x1e, 0x35, 0xee, 0xe1, 0x3e, 0x39, 0xee, 0xe3, 0x1e, 0x31, 0xfe, 0xe1, 0x1e, 0x35, 0xfe, 0xeb, 0x1e, 0x39, 0xfe, 0xee, 0x1e, 0x33, 0xee, 0x66, 0x1e, 0x37, 0xee, 0x6e, 0x1e, 0x3b, 0xee, 0x64, 0x1e, 0x33, 0xfe, 0x60, 0x1e, 0x37, 0xfe, 0x6a, 0x1e, 0x3b, 0xfe, 0x61, 0x1e, 0x31, 0xee, 0x6e, 0x1e, 0x35, 0xee, 0x6e, 0x1e, 0x39, 0xee, 0x61, 0x1e, 0x31, 0xfe, 0x6a, 0x1e, 0x35, 0xfe, 0x6a, 0x3e, 0x39, 0xfe, 0x6c, 0x1e, 0x09, 0xfe, 0x68, 0x1e, 0x13, 0xfe, 0x61, 0x1e, 0x2d, 0xfe, 0x60, 0x1e, 0x01, 0xee, 0x6c, 0x1e, 0x19, 0xee, 0x67, 0x1e, 0x23, 0xee, 0x6b, 0x1e, 0x31, 0xfe, 0x6a, 0x0e, 0x33, 0xee, 0x67, 0x0e, 0x03, 0xee, 0x66, 0x0e, 0x15, 0xee, 0x62, 0x0e, 0x27, 0xee, 0x68, 0x2e, 0x05, 0xfe, 0x66, 0x0e, 0x11, 0xfe, 0x62, 0x0e, 0x21, 0xfe, 0x62, 0x0e, 0x31, 0xfe, 0x4c, 0x1e, 0x37, 0xee, 0x4e, 0x1e, 0x01, 0xee, 0x46, 0x1e, 0x15, 0xee, 0x49, 0x1e, 0x2f, 0xee, 0x46, 0x1e, 0x01, 0xee, 0x46, 0x1e, 0x15, 0xee, 0x49, 0x1e, 0x2f, 0xee, 0x46, 0x1e, 0x0b, 0xee, 0x4e, 0x1e, 0x17, 0xee, 0x4c, 0x1e, 0x23, 0xee, 0x4b, 0x3e, 0x33, 0xfe, 0x46, 0x2e, 0x39, 0xee, 0x46, 0xfe, 0x07, 0xee, 0x48, 0x0e, 0x17, 0xee, 0x4a, 0x2e, 0x27, 0xee, 0x41, 0x2e, 0x07, 0xee, 0x48, 0x0e, 0x17, 0xee, 0x4a, 0x2e, 0x27, 0xee, 0x41, 0x2e, 0x0f, 0xee, 0x4a, 0x0e, 0x11, 0xee, 0x47, 0x0e, 0x2d, 0xee, 0x4a, 0x2e, 0x00, 0xee, 0x65, 0x1e, 0x1a, 0xee, 0x6e, 0x1e, 0x24, 0xee, 0x63, 0x1e, 0x06, 0xee, 0x63, 0x0e, 0x16, 0xee, 0x69, 0xae, 0x22, 0xee, 0x6b, 0x0e, 0x0a, 0xee, 0x4a, 0x1e, 0x16, 0xee, 0x42, 0x1e, 0x20, 0xee, 0x44, 0x1e, 0x0a, 0xee, 0x4b, 0x0e, 0x14, 0xee, 0x4a, 0x0e, 0x28, 0xee, 0x4b, 0x0e, 0x0f, 0xee, 0x60, 0x0f, 0x1b, 0xee, 0xe1, 0x2f, 0x2b, 0xee, 0xe4, 0xcf, 0x0d, 0xee, 0xeb, 0x1f, 0x1d, 0xee, 0x61, 0x1f, 0x21, 0xee, 0xe7, 0x1f, 0x0f, 0xee, 0x6f, 0x0f, 0x1f, 0xee, 0xee, 0x0f, 0x2d, 0xee, 0x6e, 0x0f, 0x05, 0xee, 0xee, 0x1f, 0x1b, 0xee, 0xee, 0x1f, 0x21, 0xee, 0xef, 0x5f, 0x0e, 0xf0, 0x01, 0xe8, 0x10, 0xf0, 0x01, 0xe8, 0x2a, 0xf0, 0x01, 0xe8, 0x31, 0xf0, 0x01, 0xe8, 0x71, 0xfe, 0x4d, 0x8f, 0x02, 0xef, 0x54, 0x09, 0x12, 0xef, 0x54, 0x09, 0x71, 0xfe, 0x4d, 0x8f, 0x12, 0xef, 0x54, 0x09, 0x14, 0xef, 0x56, 0x29, 0x3b, 0xfe, 0xe0, 0x1e, 0x71, 0xfe, 0x4d, 0x8f, 0x37, 0xfe, 0xe0, 0x1e, 0x14, 0xef, 0x52, 0x05, 0x71, 0xfe, 0x4d, 0x8f, 0x14, 0xff, 0x42, 0x05, 0x3b, 0xee, 0x60, 0x1e, 0x71, 0xfe, 0x4d, 0x8f, 0x31, 0xee, 0x60, 0x1e, 0x39, 0xfe, 0x60, 0x1e ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vsub.i8 q0, q3, r3" + - + asm_text: "vsub.i16 q0, q7, lr" + - + asm_text: "vsub.i32 q1, q5, r10" + - + asm_text: "vadd.i8 q1, q4, r7" + - + asm_text: "vadd.i16 q0, q6, r11" + - + asm_text: "vadd.i32 q0, q1, r6" + - + asm_text: "vqsub.s8 q2, q2, r8" + - + asm_text: "vqsub.s16 q1, q4, r0" + - + asm_text: "vqsub.s32 q0, q2, r0" + - + asm_text: "vqsub.u8 q0, q1, r2" + - + asm_text: "vqsub.u16 q0, q2, r6" + - + asm_text: "vqsub.u32 q0, q2, r2" + - + asm_text: "vqadd.s8 q0, q6, r1" + - + asm_text: "vqadd.s16 q3, q4, r2" + - + asm_text: "vqadd.s32 q0, q5, r11" + - + asm_text: "vqadd.u8 q0, q1, r8" + - + asm_text: "vqadd.u16 q0, q5, r9" + - + asm_text: "vqadd.u32 q0, q0, r7" + - + asm_text: "vqdmullb.s16 q0, q1, r6" + - + asm_text: "vqdmullb.s32 q0, q3, q7" + - + asm_text: "vqdmullt.s16 q0, q1, r0" + - + asm_text: "vqdmullt.s32 q0, q4, r5" + - + asm_text: "vsub.f16 q0, q3, r7" + - + asm_text: "vsub.f32 q1, q1, r10" + - + asm_text: "vadd.f16 q0, q1, lr" + - + asm_text: "vadd.f32 q1, q4, r4" + - + asm_text: "vhsub.s8 q0, q3, lr" + - + asm_text: "vhsub.s16 q0, q0, r6" + - + asm_text: "vhsub.s32 q1, q2, r7" + - + asm_text: "vhsub.u8 q1, q6, r5" + - + asm_text: "vhsub.u16 q0, q4, r10" + - + asm_text: "vhsub.u32 q0, q4, r12" + - + asm_text: "vhadd.s8 q0, q2, r1" + - + asm_text: "vhadd.s16 q0, q2, r1" + - + asm_text: "vhadd.s32 q0, q0, r10" + - + asm_text: "vhadd.u8 q0, q5, lr" + - + asm_text: "vhadd.u16 q1, q2, r2" + - + asm_text: "vhadd.u32 q0, q2, r11" + - + asm_text: "vqrshl.s8 q0, r0" + - + asm_text: "vqrshl.s16 q0, r3" + - + asm_text: "vqrshl.s32 q0, lr" + - + asm_text: "vqrshl.u8 q0, r0" + - + asm_text: "vqrshl.u16 q0, r2" + - + asm_text: "vqrshl.u32 q0, r3" + - + asm_text: "vqshl.s8 q0, r0" + - + asm_text: "vqshl.s16 q1, r1" + - + asm_text: "vqshl.s32 q0, r3" + - + asm_text: "vqshl.u8 q0, r1" + - + asm_text: "vqshl.u16 q0, r11" + - + asm_text: "vqshl.u32 q0, lr" + - + asm_text: "vrshl.s8 q0, r6" + - + asm_text: "vrshl.s16 q0, lr" + - + asm_text: "vrshl.s32 q0, r4" + - + asm_text: "vrshl.u8 q0, r0" + - + asm_text: "vrshl.u16 q0, r10" + - + asm_text: "vrshl.u32 q0, r1" + - + asm_text: "vshl.s8 q0, lr" + - + asm_text: "vshl.s16 q0, lr" + - + asm_text: "vshl.s32 q0, r1" + - + asm_text: "vshl.u8 q0, r10" + - + asm_text: "vshl.u16 q1, r10" + - + asm_text: "vshl.u32 q0, r12" + - + asm_text: "vbrsr.8 q0, q4, r8" + - + asm_text: "vbrsr.16 q0, q1, r1" + - + asm_text: "vbrsr.32 q0, q6, r0" + - + asm_text: "vmul.i8 q0, q0, r12" + - + asm_text: "vmul.i16 q0, q4, r7" + - + asm_text: "vmul.i32 q0, q1, r11" + - + asm_text: "vmul.f16 q0, q0, r10" + - + asm_text: "vmul.f32 q0, q1, r7" + - + asm_text: "vqdmulh.s8 q0, q1, r6" + - + asm_text: "vqdmulh.s16 q0, q2, r2" + - + asm_text: "vqdmulh.s32 q1, q3, r8" + - + asm_text: "vqrdmulh.s8 q0, q2, r6" + - + asm_text: "vqrdmulh.s16 q0, q0, r2" + - + asm_text: "vqrdmulh.s32 q0, q0, r2" + - + asm_text: "vfmas.f16 q0, q0, r12" + - + asm_text: "vfmas.f32 q0, q3, lr" + - + asm_text: "vmlas.i8 q0, q0, r6" + - + asm_text: "vmlas.i16 q0, q2, r9" + - + asm_text: "vmlas.i32 q0, q7, r6" + - + asm_text: "vmlas.i8 q0, q0, r6" + - + asm_text: "vmlas.i16 q0, q2, r9" + - + asm_text: "vmlas.i32 q0, q7, r6" + - + asm_text: "vmlas.i8 q0, q5, lr" + - + asm_text: "vmlas.i16 q0, q3, r12" + - + asm_text: "vmlas.i32 q1, q1, r11" + - + asm_text: "vfma.f16 q1, q1, r6" + - + asm_text: "vfmas.f32 q7, q4, r6" + - + asm_text: "vmla.i8 q0, q3, r8" + - + asm_text: "vmla.i16 q1, q3, r10" + - + asm_text: "vmla.i32 q1, q3, r1" + - + asm_text: "vmla.i8 q0, q3, r8" + - + asm_text: "vmla.i16 q1, q3, r10" + - + asm_text: "vmla.i32 q1, q3, r1" + - + asm_text: "vmla.i8 q0, q7, r10" + - + asm_text: "vmla.i16 q0, q0, r7" + - + asm_text: "vmla.i32 q1, q6, r10" + - + asm_text: "vqdmlash.s8 q0, q0, r5" + - + asm_text: "vqdmlash.s16 q0, q5, lr" + - + asm_text: "vqdmlash.s32 q0, q2, r3" + - + asm_text: "vqdmlah.s8 q0, q3, r3" + - + asm_text: "vqdmlah.s16 q5, q3, r9" + - + asm_text: "vqdmlah.s32 q0, q1, r11" + - + asm_text: "vqrdmlash.s8 q0, q5, r10" + - + asm_text: "vqrdmlash.s16 q0, q3, r2" + - + asm_text: "vqrdmlash.s32 q0, q0, r4" + - + asm_text: "vqrdmlah.s8 q0, q5, r11" + - + asm_text: "vqrdmlah.s16 q0, q2, r10" + - + asm_text: "vqrdmlah.s32 q0, q4, r11" + - + asm_text: "viwdup.u8 q0, lr, r1, #1" + - + asm_text: "viwdup.u16 q1, r10, r1, #8" + - + asm_text: "viwdup.u32 q6, r10, r5, #4" + - + asm_text: "vdwdup.u8 q0, r12, r11, #8" + - + asm_text: "vdwdup.u16 q0, r12, r1, #2" + - + asm_text: "vdwdup.u32 q0, r0, r7, #8" + - + asm_text: "vidup.u8 q0, lr, #2" + - + asm_text: "vidup.u16 q0, lr, #4" + - + asm_text: "vidup.u32 q0, r12, #1" + - + asm_text: "vddup.u8 q0, r4, #4" + - + asm_text: "vddup.u16 q0, r10, #4" + - + asm_text: "vddup.u32 q2, r0, #8" + - + asm_text: "vctp.8 lr" + - + asm_text: "vctp.16 r0" + - + asm_text: "vctp.32 r10" + - + asm_text: "vctp.64 r1" + - + asm_text: "vpste" + - + asm_text: "vmult.i8 q0, q1, q2" + - + asm_text: "vmule.i16 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vmult.i16 q0, q1, q2" + - + asm_text: "vmule.i16 q1, q2, q3" + - + asm_text: "vqrshl.u32 q0, r0" + - + asm_text: "vpste" + - + asm_text: "vqrshlt.u16 q0, r0" + - + asm_text: "vqrshle.s16 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vrshlt.u16 q0, q1, q2" + - + asm_text: "vrshle.s32 q0, r0" + - + asm_text: "vpste" + - + asm_text: "vshlt.s8 q0, r0" + - + asm_text: "vshle.u32 q0, r0" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-reductions-fp.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-reductions-fp.s.yaml new file mode 100644 index 0000000..192574b --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-reductions-fp.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0xee, 0xfe, 0x86, 0xef, 0xee, 0xee, 0x82, 0xef, 0xec, 0xfe, 0x80, 0xef, 0xec, 0xee, 0x86, 0xef, 0xee, 0xfe, 0x02, 0xef, 0xee, 0xee, 0x02, 0xaf, 0xec, 0xfe, 0x0c, 0x0f, 0xec, 0xee, 0x0e, 0xef ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vminnmv.f16 lr, q3" + - + asm_text: "vminnmv.f32 lr, q1" + - + asm_text: "vminnmav.f16 lr, q0" + - + asm_text: "vminnmav.f32 lr, q3" + - + asm_text: "vmaxnmv.f16 lr, q1" + - + asm_text: "vmaxnmv.f32 r10, q1" + - + asm_text: "vmaxnmav.f16 r0, q6" + - + asm_text: "vmaxnmav.f32 lr, q7" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-reductions.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-reductions.s.yaml new file mode 100644 index 0000000..989b9fd --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-reductions.s.yaml @@ -0,0 +1,118 @@ +test_cases: + - + input: + bytes: [ 0x82, 0xee, 0x07, 0x0f, 0x92, 0xee, 0x07, 0x0f, 0xa2, 0xee, 0x07, 0x0f, 0x82, 0xfe, 0x07, 0x0f, 0x92, 0xfe, 0x07, 0x0f, 0xa2, 0xfe, 0x07, 0x0f, 0xf5, 0xee, 0x00, 0xef, 0xf5, 0xee, 0x0c, 0x0f, 0xf5, 0xee, 0x20, 0xef, 0xc9, 0xee, 0x04, 0x0f, 0x89, 0xfe, 0x02, 0x0f, 0xe2, 0xee, 0x80, 0xef, 0xe6, 0xee, 0x80, 0xef, 0xea, 0xee, 0x84, 0xef, 0xe2, 0xfe, 0x80, 0x0f, 0xea, 0xfe, 0x86, 0xaf, 0xe4, 0xee, 0x80, 0x0f, 0xe0, 0xee, 0x82, 0x0f, 0xe8, 0xee, 0x82, 0xef, 0xe2, 0xee, 0x08, 0xef, 0xe6, 0xee, 0x00, 0xef, 0xea, 0xee, 0x02, 0x1f, 0xe2, 0xfe, 0x08, 0x0f, 0xe6, 0xfe, 0x02, 0x0f, 0xea, 0xfe, 0x00, 0x1f, 0xe0, 0xee, 0x0c, 0xef, 0xe4, 0xee, 0x0c, 0x0f, 0xe8, 0xee, 0x0e, 0xaf, 0xf0, 0xee, 0x0e, 0xee, 0xf1, 0xee, 0x08, 0xee, 0xf0, 0xfe, 0x0e, 0xee, 0xf1, 0xfe, 0x00, 0xee, 0xf0, 0xee, 0x28, 0xee, 0xf0, 0xee, 0x0e, 0x1e, 0xf0, 0xee, 0x2e, 0xfe, 0xf6, 0xee, 0x00, 0xef, 0xf2, 0xfe, 0x0e, 0xef, 0x8c, 0xee, 0x04, 0xef, 0x8a, 0xfe, 0x04, 0xef, 0x8a, 0xfe, 0x04, 0xef, 0x86, 0xee, 0x20, 0xff, 0xdc, 0xfe, 0x0b, 0xee, 0xf0, 0xee, 0x07, 0xee, 0x8c, 0xee, 0x04, 0xef, 0x8a, 0xfe, 0x04, 0xef, 0x86, 0xee, 0x2c, 0xef, 0x8e, 0xfe, 0x22, 0xef, 0xf0, 0xee, 0x07, 0xee, 0xf5, 0xee, 0x0d, 0xee, 0xf2, 0xee, 0x29, 0xfe, 0xf0, 0xee, 0x0e, 0xee, 0x88, 0xee, 0x02, 0xee, 0xd9, 0xee, 0x02, 0xee, 0x8f, 0xee, 0x0c, 0x0e, 0xda, 0xfe, 0x08, 0xee ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vabav.s8 r0, q1, q3" + - + asm_text: "vabav.s16 r0, q1, q3" + - + asm_text: "vabav.s32 r0, q1, q3" + - + asm_text: "vabav.u8 r0, q1, q3" + - + asm_text: "vabav.u16 r0, q1, q3" + - + asm_text: "vabav.u32 r0, q1, q3" + - + asm_text: "vaddv.s16 lr, q0" + - + asm_text: "vaddv.s16 r0, q6" + - + asm_text: "vaddva.s16 lr, q0" + - + asm_text: "vaddlv.s32 r0, r9, q2" + - + asm_text: "vaddlv.u32 r0, r1, q1" + - + asm_text: "vminv.s8 lr, q0" + - + asm_text: "vminv.s16 lr, q0" + - + asm_text: "vminv.s32 lr, q2" + - + asm_text: "vminv.u8 r0, q0" + - + asm_text: "vminv.u32 r10, q3" + - + asm_text: "vminav.s16 r0, q0" + - + asm_text: "vminav.s8 r0, q1" + - + asm_text: "vminav.s32 lr, q1" + - + asm_text: "vmaxv.s8 lr, q4" + - + asm_text: "vmaxv.s16 lr, q0" + - + asm_text: "vmaxv.s32 r1, q1" + - + asm_text: "vmaxv.u8 r0, q4" + - + asm_text: "vmaxv.u16 r0, q1" + - + asm_text: "vmaxv.u32 r1, q0" + - + asm_text: "vmaxav.s8 lr, q6" + - + asm_text: "vmaxav.s16 r0, q6" + - + asm_text: "vmaxav.s32 r10, q7" + - + asm_text: "vmlav.s16 lr, q0, q7" + - + asm_text: "vmlav.s32 lr, q0, q4" + - + asm_text: "vmlav.u16 lr, q0, q7" + - + asm_text: "vmlav.u32 lr, q0, q0" + - + asm_text: "vmlava.s16 lr, q0, q4" + - + asm_text: "vmladavx.s16 r0, q0, q7" + - + asm_text: "vmladavax.s16 lr, q0, q7" + - + asm_text: "vmlav.s8 lr, q3, q0" + - + asm_text: "vmlav.u8 lr, q1, q7" + - + asm_text: "vrmlalvh.s32 lr, r1, q6, q2" + - + asm_text: "vrmlalvh.u32 lr, r1, q5, q2" + - + asm_text: "vrmlalvh.u32 lr, r1, q5, q2" + - + asm_text: "vrmlaldavhax.s32 lr, r1, q3, q0" + - + asm_text: "vrmlsldavh.s32 lr, r11, q6, q5" + - + asm_text: "vmlsdav.s16 lr, q0, q3" + - + asm_text: "vrmlalvh.s32 lr, r1, q6, q2" + - + asm_text: "vrmlalvh.u32 lr, r1, q5, q2" + - + asm_text: "vrmlalvha.s32 lr, r1, q3, q6" + - + asm_text: "vrmlalvha.u32 lr, r1, q7, q1" + - + asm_text: "vmlsdav.s16 lr, q0, q3" + - + asm_text: "vmlsdav.s32 lr, q2, q6" + - + asm_text: "vmlsdavax.s16 lr, q1, q4" + - + asm_text: "vmlav.s16 lr, q0, q7" + - + asm_text: "vmlalv.s16 lr, r1, q4, q1" + - + asm_text: "vmlalv.s32 lr, r11, q4, q1" + - + asm_text: "vmlalv.s32 r0, r1, q7, q6" + - + asm_text: "vmlalv.u16 lr, r11, q5, q4" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-scalar-shift.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-scalar-shift.s.yaml new file mode 100644 index 0000000..44ad6d7 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-scalar-shift.s.yaml @@ -0,0 +1,68 @@ +test_cases: + - + input: + bytes: [ 0x50, 0xea, 0xef, 0x51, 0x5e, 0xea, 0xef, 0x61, 0x50, 0xea, 0x2d, 0x41, 0x52, 0xea, 0x22, 0x9e, 0x57, 0xea, 0x47, 0x9e, 0x5c, 0xea, 0x3c, 0xae, 0x5a, 0xea, 0x3a, 0xbe, 0x59, 0xea, 0x7b, 0x89, 0x5f, 0xea, 0x1f, 0x9e, 0x5f, 0xea, 0x3f, 0xae, 0x5a, 0xea, 0xd7, 0x9e, 0x55, 0xea, 0x2f, 0xae, 0x52, 0xea, 0x42, 0xae, 0x51, 0xea, 0x7b, 0xbe, 0x5e, 0xea, 0xcf, 0x21, 0x5e, 0xea, 0x0d, 0x41, 0x5e, 0xea, 0x1f, 0x31, 0x5e, 0xea, 0x2d, 0xcf, 0x5b, 0xea, 0x2d, 0xcf, 0x5f, 0xea, 0x2d, 0x83, 0x5e, 0xea, 0x7f, 0x4f, 0x5f, 0xea, 0x3f, 0x7b, 0x5e, 0xea, 0xef, 0x2f, 0x5f, 0xea, 0xef, 0x5b, 0x5e, 0xea, 0x0d, 0x1f, 0x5f, 0xea, 0x8d, 0x41, 0x50, 0xea, 0x4f, 0x0f, 0x5f, 0xea, 0xcf, 0x17, 0x50, 0xea, 0x9f, 0x2f, 0x51, 0xea, 0x5f, 0x79 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "asrl r0, r1, #0x17" + - + asm_text: "asrl lr, r1, #0x1b" + - + asm_text: "asrl r0, r1, r4" + - + asm_text: "cinc lr, r2, lo" + - + asm_text: "cinc lr, r7, pl" + - + asm_text: "cinv lr, r12, hs" + - + asm_text: "cneg lr, r10, hs" + - + asm_text: "csel r9, r9, r11, vc" + - + asm_text: "cset lr, eq" + - + asm_text: "csetm lr, hs" + - + asm_text: "csinc lr, r10, r7, le" + - + asm_text: "csinv lr, r5, zr, hs" + - + asm_text: "cinv lr, r2, pl" + - + asm_text: "csneg lr, r1, r11, vc" + - + asm_text: "lsll lr, r1, #0xb" + - + asm_text: "lsll lr, r1, r4" + - + asm_text: "lsrl lr, r1, #0xc" + - + asm_text: "sqrshr lr, r12" + - + asm_text: "sqrshr r11, r12" + - + asm_text: "sqrshrl lr, r3, #0x40, r8" + - + asm_text: "sqshl lr, #0x11" + - + asm_text: "sqshll lr, r11, #0x1c" + - + asm_text: "srshr lr, #0xb" + - + asm_text: "srshrl lr, r11, #0x17" + - + asm_text: "uqrshl lr, r1" + - + asm_text: "uqrshll lr, r1, #0x30, r4" + - + asm_text: "uqshl r0, #1" + - + asm_text: "uqshll lr, r7, #7" + - + asm_text: "urshr r0, #0xa" + - + asm_text: "urshrl r0, r9, #0x1d" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-shifts.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-shifts.s.yaml new file mode 100644 index 0000000..edb26b6 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-shifts.s.yaml @@ -0,0 +1,218 @@ +test_cases: + - + input: + bytes: [ 0xa8, 0xee, 0xce, 0x0f, 0xa8, 0xee, 0x4c, 0x0f, 0xa8, 0xee, 0x48, 0x1f, 0x41, 0xfe, 0x00, 0x0f, 0xa8, 0xee, 0x48, 0x1f, 0xa8, 0xfe, 0x40, 0x0f, 0xa8, 0xfe, 0x44, 0x1f, 0xb0, 0xfe, 0x40, 0x2f, 0xb0, 0xfe, 0x44, 0x1f, 0x31, 0xee, 0x05, 0x0e, 0x31, 0xee, 0x0b, 0x3e, 0xaf, 0xee, 0x40, 0x0f, 0x31, 0xfe, 0x03, 0x2e, 0x31, 0xfe, 0x01, 0x1e, 0xab, 0xfe, 0x40, 0x0f, 0x35, 0xfe, 0x0b, 0x0e, 0x35, 0xfe, 0x07, 0x1e, 0x35, 0xee, 0x01, 0x1e, 0xbe, 0xee, 0x40, 0x1f, 0xbb, 0xee, 0x40, 0x1f, 0xb4, 0xfe, 0x44, 0x0f, 0x8f, 0xfe, 0xc7, 0x0f, 0x8b, 0xfe, 0xc5, 0x1f, 0x98, 0xfe, 0xc9, 0x0f, 0x99, 0xfe, 0xc5, 0x1f, 0x8f, 0xee, 0xc5, 0x2f, 0x8f, 0xee, 0xc3, 0x1f, 0x94, 0xee, 0xc1, 0x0f, 0x9c, 0xee, 0xc5, 0x1f, 0x88, 0xfe, 0xc4, 0x0f, 0x8a, 0xfe, 0xc0, 0x1f, 0x98, 0xfe, 0xc2, 0x1f, 0x93, 0xfe, 0xce, 0x0f, 0x8b, 0xee, 0xce, 0x0f, 0x89, 0xee, 0xc2, 0x1f, 0x9c, 0xee, 0xcc, 0x0f, 0x96, 0xee, 0xc4, 0x1f, 0x88, 0xee, 0x4f, 0x0f, 0x8c, 0xfe, 0x47, 0x3f, 0x99, 0xfe, 0x43, 0x0f, 0x95, 0xee, 0x43, 0x1f, 0x8b, 0xee, 0x4c, 0x0f, 0x8c, 0xee, 0x42, 0x1f, 0x89, 0xfe, 0x46, 0x0f, 0x88, 0xfe, 0x44, 0x1f, 0x9d, 0xee, 0x48, 0x3f, 0x92, 0xfe, 0x44, 0x0f, 0x0c, 0xef, 0x4c, 0xc4, 0x14, 0xef, 0x48, 0x04, 0x2a, 0xef, 0x42, 0x24, 0x04, 0xff, 0x4e, 0x24, 0x10, 0xff, 0x48, 0x04, 0x28, 0xff, 0x44, 0x44, 0x0c, 0xef, 0x52, 0x04, 0x1e, 0xef, 0x56, 0x84, 0x2a, 0xef, 0x5a, 0x04, 0x0c, 0xff, 0x50, 0x04, 0x18, 0xff, 0x5a, 0x04, 0x28, 0xff, 0x50, 0x24, 0x02, 0xef, 0x5c, 0x25, 0x1c, 0xef, 0x58, 0x45, 0x2a, 0xef, 0x50, 0x05, 0x02, 0xff, 0x54, 0x05, 0x10, 0xff, 0x5c, 0x25, 0x20, 0xff, 0x50, 0x05, 0x08, 0xef, 0x4c, 0x05, 0x1e, 0xef, 0x48, 0x25, 0x28, 0xef, 0x48, 0x25, 0x0a, 0xff, 0x46, 0x05, 0x1a, 0xff, 0x4c, 0xa5, 0x26, 0xff, 0x4e, 0x25, 0x8d, 0xff, 0x54, 0x04, 0x9b, 0xff, 0x54, 0x04, 0xb1, 0xff, 0x52, 0x04, 0x8b, 0xff, 0x56, 0x05, 0x9c, 0xff, 0x52, 0x05, 0xa8, 0xff, 0x52, 0x05, 0x8e, 0xef, 0x58, 0x07, 0x8e, 0xff, 0x5c, 0x07, 0x95, 0xef, 0x54, 0x27, 0x93, 0xff, 0x5a, 0x07, 0xbd, 0xef, 0x56, 0x27, 0xb3, 0xff, 0x54, 0x07, 0x88, 0xff, 0x52, 0x06, 0x9c, 0xff, 0x52, 0x46, 0xba, 0xff, 0x58, 0x06, 0x89, 0xef, 0x56, 0x22, 0x8e, 0xff, 0x56, 0x22, 0x96, 0xef, 0x52, 0x02, 0x94, 0xff, 0x5a, 0x02, 0xa9, 0xef, 0x5a, 0x02, 0xa2, 0xff, 0x52, 0x02, 0x8c, 0xef, 0x5e, 0x00, 0x8b, 0xff, 0x54, 0x00, 0x90, 0xef, 0x56, 0x00, 0x98, 0xff, 0x5c, 0xe0, 0xa8, 0xef, 0x5c, 0x00, 0xa2, 0xff, 0x5a, 0x40, 0x8e, 0xef, 0x5c, 0x05, 0x9c, 0xef, 0x50, 0x25, 0xba, 0xef, 0x54, 0x45, 0xa9, 0xee, 0x42, 0x1f, 0x71, 0xfe, 0x4d, 0x8f, 0xb4, 0xee, 0x42, 0x1f, 0xb8, 0xfe, 0x42, 0x0f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vshlc q0, lr, #8" + - + asm_text: "vmovlb.s8 q0, q6" + - + asm_text: "vmovlt.s8 q0, q4" + - + asm_text: "vpt.i8 eq, q0, q0" + - + asm_text: "vmovltt.s8 q0, q4" + - + asm_text: "vmovlb.u8 q0, q0" + - + asm_text: "vmovlt.u8 q0, q2" + - + asm_text: "vmovlb.u16 q1, q0" + - + asm_text: "vmovlt.u16 q0, q2" + - + asm_text: "vshllb.s8 q0, q2, #8" + - + asm_text: "vshllt.s8 q1, q5, #8" + - + asm_text: "vshllb.s8 q0, q0, #7" + - + asm_text: "vshllb.u8 q1, q1, #8" + - + asm_text: "vshllt.u8 q0, q0, #8" + - + asm_text: "vshllb.u8 q0, q0, #3" + - + asm_text: "vshllb.u16 q0, q5, #0x10" + - + asm_text: "vshllt.u16 q0, q3, #0x10" + - + asm_text: "vshllt.s16 q0, q0, #0x10" + - + asm_text: "vshllt.s16 q0, q0, #0xe" + - + asm_text: "vshllt.s16 q0, q0, #0xb" + - + asm_text: "vshllb.u16 q0, q2, #4" + - + asm_text: "vrshrnb.i16 q0, q3, #1" + - + asm_text: "vrshrnt.i16 q0, q2, #5" + - + asm_text: "vrshrnb.i32 q0, q4, #8" + - + asm_text: "vrshrnt.i32 q0, q2, #7" + - + asm_text: "vshrnb.i16 q1, q2, #1" + - + asm_text: "vshrnt.i16 q0, q1, #1" + - + asm_text: "vshrnb.i32 q0, q0, #0xc" + - + asm_text: "vshrnt.i32 q0, q2, #4" + - + asm_text: "vqrshrunb.s16 q0, q2, #8" + - + asm_text: "vqrshrunt.s16 q0, q0, #6" + - + asm_text: "vqrshrunt.s32 q0, q1, #8" + - + asm_text: "vqrshrunb.s32 q0, q7, #0xd" + - + asm_text: "vqshrunb.s16 q0, q7, #5" + - + asm_text: "vqshrunt.s16 q0, q1, #7" + - + asm_text: "vqshrunb.s32 q0, q6, #4" + - + asm_text: "vqshrunt.s32 q0, q2, #0xa" + - + asm_text: "vqrshrnb.s16 q0, q7, #8" + - + asm_text: "vqrshrnt.u16 q1, q3, #4" + - + asm_text: "vqrshrnb.u32 q0, q1, #7" + - + asm_text: "vqrshrnt.s32 q0, q1, #0xb" + - + asm_text: "vqshrnb.s16 q0, q6, #5" + - + asm_text: "vqshrnt.s16 q0, q1, #4" + - + asm_text: "vqshrnb.u16 q0, q3, #7" + - + asm_text: "vqshrnt.u16 q0, q2, #8" + - + asm_text: "vqshrnt.s32 q1, q4, #3" + - + asm_text: "vqshrnb.u32 q0, q2, #0xe" + - + asm_text: "vshl.s8 q6, q6, q6" + - + asm_text: "vshl.s16 q0, q4, q2" + - + asm_text: "vshl.s32 q1, q1, q5" + - + asm_text: "vshl.u8 q1, q7, q2" + - + asm_text: "vshl.u16 q0, q4, q0" + - + asm_text: "vshl.u32 q2, q2, q4" + - + asm_text: "vqshl.s8 q0, q1, q6" + - + asm_text: "vqshl.s16 q4, q3, q7" + - + asm_text: "vqshl.s32 q0, q5, q5" + - + asm_text: "vqshl.u8 q0, q0, q6" + - + asm_text: "vqshl.u16 q0, q5, q4" + - + asm_text: "vqshl.u32 q1, q0, q4" + - + asm_text: "vqrshl.s8 q1, q6, q1" + - + asm_text: "vqrshl.s16 q2, q4, q6" + - + asm_text: "vqrshl.s32 q0, q0, q5" + - + asm_text: "vqrshl.u8 q0, q2, q1" + - + asm_text: "vqrshl.u16 q1, q6, q0" + - + asm_text: "vqrshl.u32 q0, q0, q0" + - + asm_text: "vrshl.s8 q0, q6, q4" + - + asm_text: "vrshl.s16 q1, q4, q7" + - + asm_text: "vrshl.s32 q1, q4, q4" + - + asm_text: "vrshl.u8 q0, q3, q5" + - + asm_text: "vrshl.u16 q5, q6, q5" + - + asm_text: "vrshl.u32 q1, q7, q3" + - + asm_text: "vsri.8 q0, q2, #3" + - + asm_text: "vsri.16 q0, q2, #5" + - + asm_text: "vsri.32 q0, q1, #0xf" + - + asm_text: "vsli.8 q0, q3, #3" + - + asm_text: "vsli.16 q0, q1, #0xc" + - + asm_text: "vsli.32 q0, q1, #8" + - + asm_text: "vqshl.s8 q0, q4, #6" + - + asm_text: "vqshl.u8 q0, q6, #6" + - + asm_text: "vqshl.s16 q1, q2, #5" + - + asm_text: "vqshl.u16 q0, q5, #3" + - + asm_text: "vqshl.s32 q1, q3, #0x1d" + - + asm_text: "vqshl.u32 q0, q2, #0x13" + - + asm_text: "vqshlu.s8 q0, q1, #0" + - + asm_text: "vqshlu.s16 q2, q1, #0xc" + - + asm_text: "vqshlu.s32 q0, q4, #0x1a" + - + asm_text: "vrshr.s8 q1, q3, #7" + - + asm_text: "vrshr.u8 q1, q3, #2" + - + asm_text: "vrshr.s16 q0, q1, #0xa" + - + asm_text: "vrshr.u16 q0, q5, #0xc" + - + asm_text: "vrshr.s32 q0, q5, #0x17" + - + asm_text: "vrshr.u32 q0, q1, #0x1e" + - + asm_text: "vshr.s8 q0, q7, #4" + - + asm_text: "vshr.u8 q0, q2, #5" + - + asm_text: "vshr.s16 q0, q3, #0x10" + - + asm_text: "vshr.u16 q7, q6, #8" + - + asm_text: "vshr.s32 q0, q6, #0x18" + - + asm_text: "vshr.u32 q2, q5, #0x1e" + - + asm_text: "vshl.i8 q0, q6, #6" + - + asm_text: "vshl.i16 q1, q0, #0xc" + - + asm_text: "vshl.i32 q2, q2, #0x1a" + - + asm_text: "vshllt.s8 q0, q1, #1" + - + asm_text: "vpste" + - + asm_text: "vshlltt.s16 q0, q1, #4" + - + asm_text: "vshllbe.u16 q0, q1, #8" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-vcmp.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-vcmp.s.yaml new file mode 100644 index 0000000..5b3fdd8 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-vcmp.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x31, 0xfe, 0x08, 0x0f, 0x35, 0xfe, 0x8e, 0x0f, 0x31, 0xfe, 0x00, 0x1f, 0x31, 0xfe, 0x82, 0x1f, 0x33, 0xfe, 0x09, 0x1f, 0x35, 0xfe, 0x8d, 0x1f, 0x35, 0xee, 0x0a, 0x0f, 0x37, 0xee, 0x88, 0x0f, 0x31, 0xee, 0x0e, 0x1f, 0x3b, 0xee, 0x84, 0x1f, 0x35, 0xee, 0x0f, 0x1f, 0x35, 0xee, 0x89, 0x1f, 0x09, 0xfe, 0x0c, 0x0f, 0x05, 0xfe, 0x84, 0x0f, 0x09, 0xfe, 0x0c, 0x0f, 0x05, 0xfe, 0x84, 0x0f, 0x09, 0xfe, 0x0c, 0x0f, 0x05, 0xfe, 0x84, 0x0f, 0x01, 0xfe, 0x00, 0x1f, 0x05, 0xfe, 0x8e, 0x1f, 0x09, 0xfe, 0x07, 0x1f, 0x0f, 0xfe, 0x87, 0x1f, 0x03, 0xfe, 0x89, 0x0f, 0x03, 0xfe, 0x09, 0x0f, 0x19, 0xfe, 0x0e, 0x0f, 0x15, 0xfe, 0x82, 0x0f, 0x13, 0xfe, 0x0e, 0x1f, 0x11, 0xfe, 0x82, 0x1f, 0x13, 0xfe, 0x0f, 0x1f, 0x15, 0xfe, 0x83, 0x1f, 0x13, 0xfe, 0x89, 0x0f, 0x13, 0xfe, 0x09, 0x0f, 0x25, 0xfe, 0x0e, 0x0f, 0x25, 0xfe, 0x88, 0x0f, 0x2b, 0xfe, 0x0a, 0x1f, 0x25, 0xfe, 0x84, 0x1f, 0x21, 0xfe, 0x03, 0x1f, 0x2b, 0xfe, 0x89, 0x1f, 0x23, 0xfe, 0x89, 0x0f, 0x23, 0xfe, 0x09, 0x0f, 0x39, 0xfe, 0x6f, 0x1f, 0x39, 0xfe, 0x4c, 0x0f, 0x37, 0xee, 0xc0, 0x0f, 0x03, 0xfe, 0x40, 0x0f, 0x03, 0xfe, 0xe0, 0x1f, 0x03, 0xfe, 0x60, 0x0f, 0x1b, 0xfe, 0x4a, 0x0f, 0x23, 0xfe, 0x44, 0x0f, 0x71, 0xfe, 0x4d, 0x8f, 0x01, 0xfe, 0x40, 0x0f, 0x11, 0xfe, 0xc0, 0x0f, 0xb4, 0xee, 0x60, 0x09, 0xb4, 0xee, 0xe0, 0x09, 0x04, 0xbf, 0xb4, 0xee, 0x60, 0x0a, 0xb4, 0xee, 0xe0, 0x0a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcmp.f16 eq, q0, q4" + - + asm_text: "vcmp.f16 ne, q2, q7" + - + asm_text: "vcmp.f16 ge, q0, q0" + - + asm_text: "vcmp.f16 lt, q0, q1" + - + asm_text: "vcmp.f16 gt, q1, q4" + - + asm_text: "vcmp.f16 le, q2, q6" + - + asm_text: "vcmp.f32 eq, q2, q5" + - + asm_text: "vcmp.f32 ne, q3, q4" + - + asm_text: "vcmp.f32 ge, q0, q7" + - + asm_text: "vcmp.f32 lt, q5, q2" + - + asm_text: "vcmp.f32 gt, q2, q7" + - + asm_text: "vcmp.f32 le, q2, q4" + - + asm_text: "vcmp.i8 eq, q4, q6" + - + asm_text: "vcmp.i8 ne, q2, q2" + - + asm_text: "vcmp.i8 eq, q4, q6" + - + asm_text: "vcmp.i8 ne, q2, q2" + - + asm_text: "vcmp.i8 eq, q4, q6" + - + asm_text: "vcmp.i8 ne, q2, q2" + - + asm_text: "vcmp.s8 ge, q0, q0" + - + asm_text: "vcmp.s8 lt, q2, q7" + - + asm_text: "vcmp.s8 gt, q4, q3" + - + asm_text: "vcmp.s8 le, q7, q3" + - + asm_text: "vcmp.u8 hi, q1, q4" + - + asm_text: "vcmp.u8 cs, q1, q4" + - + asm_text: "vcmp.i16 eq, q4, q7" + - + asm_text: "vcmp.i16 ne, q2, q1" + - + asm_text: "vcmp.s16 ge, q1, q7" + - + asm_text: "vcmp.s16 lt, q0, q1" + - + asm_text: "vcmp.s16 gt, q1, q7" + - + asm_text: "vcmp.s16 le, q2, q1" + - + asm_text: "vcmp.u16 hi, q1, q4" + - + asm_text: "vcmp.u16 cs, q1, q4" + - + asm_text: "vcmp.i32 eq, q2, q7" + - + asm_text: "vcmp.i32 ne, q2, q4" + - + asm_text: "vcmp.s32 ge, q5, q5" + - + asm_text: "vcmp.s32 lt, q2, q2" + - + asm_text: "vcmp.s32 gt, q0, q1" + - + asm_text: "vcmp.s32 le, q5, q4" + - + asm_text: "vcmp.u32 hi, q1, q4" + - + asm_text: "vcmp.u32 cs, q1, q4" + - + asm_text: "vcmp.f16 gt, q4, zr" + - + asm_text: "vcmp.f16 eq, q4, r12" + - + asm_text: "vcmp.f32 ne, q3, r0" + - + asm_text: "vcmp.i8 eq, q1, r0" + - + asm_text: "vcmp.s8 le, q1, r0" + - + asm_text: "vcmp.u8 cs, q1, r0" + - + asm_text: "vcmp.i16 eq, q5, r10" + - + asm_text: "vcmp.i32 eq, q1, r4" + - + asm_text: "vpste" + - + asm_text: "vcmpt.i8 eq, q0, r0" + - + asm_text: "vcmpe.i16 ne, q0, r0" + - + asm_text: "vcmp.f16 s0, s1" + - + asm_text: "vcmpe.f16 s0, s1" + - + asm_text: "itt eq" + - + asm_text: "vcmpeq.f32 s0, s1" + - + asm_text: "vcmpeeq.f32 s0, s1" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-vmov-pair.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-vmov-pair.s.yaml new file mode 100644 index 0000000..957e55d --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-vmov-pair.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x07, 0xec, 0x0e, 0x8f, 0x11, 0xec, 0x14, 0x6f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmov lr, r7, q4[2], q4[0]" + - + asm_text: "vmov q3[3], q3[1], r4, r1" diff --git a/thirdparty/capstone/tests/MC/ARM/mve-vpt.s.yaml b/thirdparty/capstone/tests/MC/ARM/mve-vpt.s.yaml new file mode 100644 index 0000000..c49bc19 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/mve-vpt.s.yaml @@ -0,0 +1,16 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xfe, 0x02, 0x2f, 0x21, 0xfe, 0x03, 0x3f, 0x71, 0xfe, 0x82, 0xef, 0x1c, 0xff, 0x54, 0x2f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vpteee.i8 eq, q0, q1" + - + asm_text: "vptttt.s32 gt, q0, q1" + - + asm_text: "vptete.f16 ne, q0, q1" + - + asm_text: "vmaxnmt.f16 q1, q6, q2" diff --git a/thirdparty/capstone/tests/MC/ARM/negative-immediates.s.yaml b/thirdparty/capstone/tests/MC/ARM/negative-immediates.s.yaml new file mode 100644 index 0000000..c530b98 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/negative-immediates.s.yaml @@ -0,0 +1,26 @@ +test_cases: + - + input: + bytes: [ 0x61, 0xf1, 0x01, 0x10, 0x61, 0xf1, 0x01, 0x20, 0xa0, 0xf1, 0xfe, 0x10, 0xa1, 0xf2, 0xff, 0x00, 0xa1, 0xf1, 0xff, 0x00, 0x21, 0xf0, 0x01, 0x20, 0x01, 0xf0, 0x01, 0x20, 0x61, 0xf0, 0x01, 0x20, 0x41, 0xf0, 0x01, 0x20 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "sbc r0, r1, #0x10001" + - + asm_text: "sbc r0, r1, #0x1000100" + - + asm_text: "sub.w r0, r0, #0xfe00fe" + - + asm_text: "subw r0, r1, #0xff" + - + asm_text: "sub.w r0, r1, #0xff" + - + asm_text: "bic r0, r1, #0x1000100" + - + asm_text: "and r0, r1, #0x1000100" + - + asm_text: "orn r0, r1, #0x1000100" + - + asm_text: "orr r0, r1, #0x1000100" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-abs-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-abs-encoding.s.yaml new file mode 100644 index 0000000..0dabf26 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-abs-encoding.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x03, 0xf1, 0xf3, 0x20, 0x03, 0xf5, 0xf3, 0x20, 0x03, 0xf9, 0xf3, 0x20, 0x07, 0xf9, 0xf3, 0x60, 0x03, 0xf1, 0xf3, 0x60, 0x03, 0xf5, 0xf3, 0x60, 0x03, 0xf9, 0xf3, 0x60, 0x07, 0xf9, 0xf3, 0x20, 0x07, 0xf0, 0xf3, 0x20, 0x07, 0xf4, 0xf3, 0x20, 0x07, 0xf8, 0xf3, 0x60, 0x07, 0xf0, 0xf3, 0x60, 0x07, 0xf4, 0xf3, 0x60, 0x07, 0xf8, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vabs.s8 d16, d16" + - + asm_text: "vabs.s16 d16, d16" + - + asm_text: "vabs.s32 d16, d16" + - + asm_text: "vabs.f32 d16, d16" + - + asm_text: "vabs.s8 q8, q8" + - + asm_text: "vabs.s16 q8, q8" + - + asm_text: "vabs.s32 q8, q8" + - + asm_text: "vabs.f32 q8, q8" + - + asm_text: "vqabs.s8 d16, d16" + - + asm_text: "vqabs.s16 d16, d16" + - + asm_text: "vqabs.s32 d16, d16" + - + asm_text: "vqabs.s8 q8, q8" + - + asm_text: "vqabs.s16 q8, q8" + - + asm_text: "vqabs.s32 q8, q8" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-absdiff-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-absdiff-encoding.s.yaml new file mode 100644 index 0000000..11b03d4 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-absdiff-encoding.s.yaml @@ -0,0 +1,84 @@ +test_cases: + - + input: + bytes: [ 0xa1, 0x07, 0x40, 0xf2, 0xa1, 0x07, 0x50, 0xf2, 0xa1, 0x07, 0x60, 0xf2, 0xa1, 0x07, 0x40, 0xf3, 0xa1, 0x07, 0x50, 0xf3, 0xa1, 0x07, 0x60, 0xf3, 0xa1, 0x0d, 0x60, 0xf3, 0xe2, 0x07, 0x40, 0xf2, 0xe2, 0x07, 0x50, 0xf2, 0xe2, 0x07, 0x60, 0xf2, 0xe2, 0x07, 0x40, 0xf3, 0xe2, 0x07, 0x50, 0xf3, 0xe2, 0x07, 0x60, 0xf3, 0xe2, 0x0d, 0x60, 0xf3, 0xa1, 0x07, 0xc0, 0xf2, 0xa1, 0x07, 0xd0, 0xf2, 0xa1, 0x07, 0xe0, 0xf2, 0xa1, 0x07, 0xc0, 0xf3, 0xa1, 0x07, 0xd0, 0xf3, 0xa1, 0x07, 0xe0, 0xf3, 0xb1, 0x07, 0x42, 0xf2, 0xb1, 0x07, 0x52, 0xf2, 0xb1, 0x07, 0x62, 0xf2, 0xb1, 0x07, 0x42, 0xf3, 0xb1, 0x07, 0x52, 0xf3, 0xb1, 0x07, 0x62, 0xf3, 0xf4, 0x27, 0x40, 0xf2, 0xf4, 0x27, 0x50, 0xf2, 0xf4, 0x27, 0x60, 0xf2, 0xf4, 0x27, 0x40, 0xf3, 0xf4, 0x27, 0x50, 0xf3, 0xf4, 0x27, 0x60, 0xf3, 0xa2, 0x05, 0xc3, 0xf2, 0xa2, 0x05, 0xd3, 0xf2, 0xa2, 0x05, 0xe3, 0xf2, 0xa2, 0x05, 0xc3, 0xf3, 0xa2, 0x05, 0xd3, 0xf3, 0xa2, 0x05, 0xe3, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vabd.s8 d16, d16, d17" + - + asm_text: "vabd.s16 d16, d16, d17" + - + asm_text: "vabd.s32 d16, d16, d17" + - + asm_text: "vabd.u8 d16, d16, d17" + - + asm_text: "vabd.u16 d16, d16, d17" + - + asm_text: "vabd.u32 d16, d16, d17" + - + asm_text: "vabd.f32 d16, d16, d17" + - + asm_text: "vabd.s8 q8, q8, q9" + - + asm_text: "vabd.s16 q8, q8, q9" + - + asm_text: "vabd.s32 q8, q8, q9" + - + asm_text: "vabd.u8 q8, q8, q9" + - + asm_text: "vabd.u16 q8, q8, q9" + - + asm_text: "vabd.u32 q8, q8, q9" + - + asm_text: "vabd.f32 q8, q8, q9" + - + asm_text: "vabdl.s8 q8, d16, d17" + - + asm_text: "vabdl.s16 q8, d16, d17" + - + asm_text: "vabdl.s32 q8, d16, d17" + - + asm_text: "vabdl.u8 q8, d16, d17" + - + asm_text: "vabdl.u16 q8, d16, d17" + - + asm_text: "vabdl.u32 q8, d16, d17" + - + asm_text: "vaba.s8 d16, d18, d17" + - + asm_text: "vaba.s16 d16, d18, d17" + - + asm_text: "vaba.s32 d16, d18, d17" + - + asm_text: "vaba.u8 d16, d18, d17" + - + asm_text: "vaba.u16 d16, d18, d17" + - + asm_text: "vaba.u32 d16, d18, d17" + - + asm_text: "vaba.s8 q9, q8, q10" + - + asm_text: "vaba.s16 q9, q8, q10" + - + asm_text: "vaba.s32 q9, q8, q10" + - + asm_text: "vaba.u8 q9, q8, q10" + - + asm_text: "vaba.u16 q9, q8, q10" + - + asm_text: "vaba.u32 q9, q8, q10" + - + asm_text: "vabal.s8 q8, d19, d18" + - + asm_text: "vabal.s16 q8, d19, d18" + - + asm_text: "vabal.s32 q8, d19, d18" + - + asm_text: "vabal.u8 q8, d19, d18" + - + asm_text: "vabal.u16 q8, d19, d18" + - + asm_text: "vabal.u32 q8, d19, d18" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-add-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-add-encoding.s.yaml new file mode 100644 index 0000000..682dd47 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-add-encoding.s.yaml @@ -0,0 +1,244 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x08, 0x41, 0xf2, 0xa0, 0x08, 0x51, 0xf2, 0xa0, 0x08, 0x71, 0xf2, 0xa0, 0x08, 0x61, 0xf2, 0xa1, 0x0d, 0x40, 0xf2, 0xe2, 0x0d, 0x40, 0xf2, 0xa0, 0x00, 0xc1, 0xf2, 0xa0, 0x00, 0xd1, 0xf2, 0xa0, 0x00, 0xe1, 0xf2, 0xa0, 0x00, 0xc1, 0xf3, 0xa0, 0x00, 0xd1, 0xf3, 0xa0, 0x00, 0xe1, 0xf3, 0xa2, 0x01, 0xc0, 0xf2, 0xa2, 0x01, 0xd0, 0xf2, 0xa2, 0x01, 0xe0, 0xf2, 0xa2, 0x01, 0xc0, 0xf3, 0xa2, 0x01, 0xd0, 0xf3, 0xa2, 0x01, 0xe0, 0xf3, 0xa1, 0x00, 0x40, 0xf2, 0xa1, 0x00, 0x50, 0xf2, 0xa1, 0x00, 0x60, 0xf2, 0xa1, 0x00, 0x40, 0xf3, 0xa1, 0x00, 0x50, 0xf3, 0xa1, 0x00, 0x60, 0xf3, 0xe2, 0x00, 0x40, 0xf2, 0xe2, 0x00, 0x50, 0xf2, 0xe2, 0x00, 0x60, 0xf2, 0xe2, 0x00, 0x40, 0xf3, 0xe2, 0x00, 0x50, 0xf3, 0xe2, 0x00, 0x60, 0xf3, 0x28, 0xb0, 0x0b, 0xf2, 0x27, 0xc0, 0x1c, 0xf2, 0x26, 0xd0, 0x2d, 0xf2, 0x25, 0xe0, 0x0e, 0xf3, 0x24, 0xf0, 0x1f, 0xf3, 0xa3, 0x00, 0x60, 0xf3, 0x68, 0x20, 0x02, 0xf2, 0x66, 0x40, 0x14, 0xf2, 0x64, 0x60, 0x26, 0xf2, 0x62, 0x80, 0x08, 0xf3, 0x60, 0xa0, 0x1a, 0xf3, 0x4e, 0xc0, 0x2c, 0xf3, 0xa1, 0x01, 0x40, 0xf2, 0xa1, 0x01, 0x50, 0xf2, 0xa1, 0x01, 0x60, 0xf2, 0xa1, 0x01, 0x40, 0xf3, 0xa1, 0x01, 0x50, 0xf3, 0xa1, 0x01, 0x60, 0xf3, 0xe2, 0x01, 0x40, 0xf2, 0xe2, 0x01, 0x50, 0xf2, 0xe2, 0x01, 0x60, 0xf2, 0xe2, 0x01, 0x40, 0xf3, 0xe2, 0x01, 0x50, 0xf3, 0xe2, 0x01, 0x60, 0xf3, 0xa1, 0x01, 0x40, 0xf2, 0xa1, 0x01, 0x50, 0xf2, 0xa1, 0x01, 0x60, 0xf2, 0xa1, 0x01, 0x40, 0xf3, 0xa1, 0x01, 0x50, 0xf3, 0xa1, 0x01, 0x60, 0xf3, 0xe2, 0x01, 0x40, 0xf2, 0xe2, 0x01, 0x50, 0xf2, 0xe2, 0x01, 0x60, 0xf2, 0xe2, 0x01, 0x40, 0xf3, 0xe2, 0x01, 0x50, 0xf3, 0xe2, 0x01, 0x60, 0xf3, 0xb1, 0x00, 0x40, 0xf2, 0xb1, 0x00, 0x50, 0xf2, 0xb1, 0x00, 0x60, 0xf2, 0xb1, 0x00, 0x70, 0xf2, 0xb1, 0x00, 0x40, 0xf3, 0xb1, 0x00, 0x50, 0xf3, 0xb1, 0x00, 0x60, 0xf3, 0xb1, 0x00, 0x70, 0xf3, 0xf2, 0x00, 0x40, 0xf2, 0xf2, 0x00, 0x50, 0xf2, 0xf2, 0x00, 0x60, 0xf2, 0xf2, 0x00, 0x70, 0xf2, 0xf2, 0x00, 0x40, 0xf3, 0xf2, 0x00, 0x50, 0xf3, 0xf2, 0x00, 0x60, 0xf3, 0xf2, 0x00, 0x70, 0xf3, 0xb1, 0x00, 0x40, 0xf2, 0xb1, 0x00, 0x50, 0xf2, 0xb1, 0x00, 0x60, 0xf2, 0xb1, 0x00, 0x70, 0xf2, 0xb1, 0x00, 0x40, 0xf3, 0xb1, 0x00, 0x50, 0xf3, 0xb1, 0x00, 0x60, 0xf3, 0xb1, 0x00, 0x70, 0xf3, 0xf2, 0x00, 0x40, 0xf2, 0xf2, 0x00, 0x50, 0xf2, 0xf2, 0x00, 0x60, 0xf2, 0xf2, 0x00, 0x70, 0xf2, 0xf2, 0x00, 0x40, 0xf3, 0xf2, 0x00, 0x50, 0xf3, 0xf2, 0x00, 0x60, 0xf3, 0xf2, 0x00, 0x70, 0xf3, 0xa2, 0x04, 0xc0, 0xf2, 0xa2, 0x04, 0xd0, 0xf2, 0xa2, 0x04, 0xe0, 0xf2, 0xa2, 0x04, 0xc0, 0xf3, 0xa2, 0x04, 0xd0, 0xf3, 0xa2, 0x04, 0xe0, 0xf3, 0x05, 0x68, 0x06, 0xf2, 0x01, 0x78, 0x17, 0xf2, 0x02, 0x88, 0x28, 0xf2, 0x03, 0x98, 0x39, 0xf2, 0x4a, 0xc8, 0x0c, 0xf2, 0x42, 0xe8, 0x1e, 0xf2, 0xc4, 0x08, 0x60, 0xf2, 0xc6, 0x28, 0x72, 0xf2, 0x05, 0xc1, 0x8c, 0xf2, 0x01, 0xe1, 0x9e, 0xf2, 0x82, 0x01, 0xe0, 0xf2, 0x05, 0xc1, 0x8c, 0xf3, 0x01, 0xe1, 0x9e, 0xf3, 0x82, 0x01, 0xe0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vadd.i8 d16, d17, d16" + - + asm_text: "vadd.i16 d16, d17, d16" + - + asm_text: "vadd.i64 d16, d17, d16" + - + asm_text: "vadd.i32 d16, d17, d16" + - + asm_text: "vadd.f32 d16, d16, d17" + - + asm_text: "vadd.f32 q8, q8, q9" + - + asm_text: "vaddl.s8 q8, d17, d16" + - + asm_text: "vaddl.s16 q8, d17, d16" + - + asm_text: "vaddl.s32 q8, d17, d16" + - + asm_text: "vaddl.u8 q8, d17, d16" + - + asm_text: "vaddl.u16 q8, d17, d16" + - + asm_text: "vaddl.u32 q8, d17, d16" + - + asm_text: "vaddw.s8 q8, q8, d18" + - + asm_text: "vaddw.s16 q8, q8, d18" + - + asm_text: "vaddw.s32 q8, q8, d18" + - + asm_text: "vaddw.u8 q8, q8, d18" + - + asm_text: "vaddw.u16 q8, q8, d18" + - + asm_text: "vaddw.u32 q8, q8, d18" + - + asm_text: "vhadd.s8 d16, d16, d17" + - + asm_text: "vhadd.s16 d16, d16, d17" + - + asm_text: "vhadd.s32 d16, d16, d17" + - + asm_text: "vhadd.u8 d16, d16, d17" + - + asm_text: "vhadd.u16 d16, d16, d17" + - + asm_text: "vhadd.u32 d16, d16, d17" + - + asm_text: "vhadd.s8 q8, q8, q9" + - + asm_text: "vhadd.s16 q8, q8, q9" + - + asm_text: "vhadd.s32 q8, q8, q9" + - + asm_text: "vhadd.u8 q8, q8, q9" + - + asm_text: "vhadd.u16 q8, q8, q9" + - + asm_text: "vhadd.u32 q8, q8, q9" + - + asm_text: "vhadd.s8 d11, d11, d24" + - + asm_text: "vhadd.s16 d12, d12, d23" + - + asm_text: "vhadd.s32 d13, d13, d22" + - + asm_text: "vhadd.u8 d14, d14, d21" + - + asm_text: "vhadd.u16 d15, d15, d20" + - + asm_text: "vhadd.u32 d16, d16, d19" + - + asm_text: "vhadd.s8 q1, q1, q12" + - + asm_text: "vhadd.s16 q2, q2, q11" + - + asm_text: "vhadd.s32 q3, q3, q10" + - + asm_text: "vhadd.u8 q4, q4, q9" + - + asm_text: "vhadd.u16 q5, q5, q8" + - + asm_text: "vhadd.u32 q6, q6, q7" + - + asm_text: "vrhadd.s8 d16, d16, d17" + - + asm_text: "vrhadd.s16 d16, d16, d17" + - + asm_text: "vrhadd.s32 d16, d16, d17" + - + asm_text: "vrhadd.u8 d16, d16, d17" + - + asm_text: "vrhadd.u16 d16, d16, d17" + - + asm_text: "vrhadd.u32 d16, d16, d17" + - + asm_text: "vrhadd.s8 q8, q8, q9" + - + asm_text: "vrhadd.s16 q8, q8, q9" + - + asm_text: "vrhadd.s32 q8, q8, q9" + - + asm_text: "vrhadd.u8 q8, q8, q9" + - + asm_text: "vrhadd.u16 q8, q8, q9" + - + asm_text: "vrhadd.u32 q8, q8, q9" + - + asm_text: "vrhadd.s8 d16, d16, d17" + - + asm_text: "vrhadd.s16 d16, d16, d17" + - + asm_text: "vrhadd.s32 d16, d16, d17" + - + asm_text: "vrhadd.u8 d16, d16, d17" + - + asm_text: "vrhadd.u16 d16, d16, d17" + - + asm_text: "vrhadd.u32 d16, d16, d17" + - + asm_text: "vrhadd.s8 q8, q8, q9" + - + asm_text: "vrhadd.s16 q8, q8, q9" + - + asm_text: "vrhadd.s32 q8, q8, q9" + - + asm_text: "vrhadd.u8 q8, q8, q9" + - + asm_text: "vrhadd.u16 q8, q8, q9" + - + asm_text: "vrhadd.u32 q8, q8, q9" + - + asm_text: "vqadd.s8 d16, d16, d17" + - + asm_text: "vqadd.s16 d16, d16, d17" + - + asm_text: "vqadd.s32 d16, d16, d17" + - + asm_text: "vqadd.s64 d16, d16, d17" + - + asm_text: "vqadd.u8 d16, d16, d17" + - + asm_text: "vqadd.u16 d16, d16, d17" + - + asm_text: "vqadd.u32 d16, d16, d17" + - + asm_text: "vqadd.u64 d16, d16, d17" + - + asm_text: "vqadd.s8 q8, q8, q9" + - + asm_text: "vqadd.s16 q8, q8, q9" + - + asm_text: "vqadd.s32 q8, q8, q9" + - + asm_text: "vqadd.s64 q8, q8, q9" + - + asm_text: "vqadd.u8 q8, q8, q9" + - + asm_text: "vqadd.u16 q8, q8, q9" + - + asm_text: "vqadd.u32 q8, q8, q9" + - + asm_text: "vqadd.u64 q8, q8, q9" + - + asm_text: "vqadd.s8 d16, d16, d17" + - + asm_text: "vqadd.s16 d16, d16, d17" + - + asm_text: "vqadd.s32 d16, d16, d17" + - + asm_text: "vqadd.s64 d16, d16, d17" + - + asm_text: "vqadd.u8 d16, d16, d17" + - + asm_text: "vqadd.u16 d16, d16, d17" + - + asm_text: "vqadd.u32 d16, d16, d17" + - + asm_text: "vqadd.u64 d16, d16, d17" + - + asm_text: "vqadd.s8 q8, q8, q9" + - + asm_text: "vqadd.s16 q8, q8, q9" + - + asm_text: "vqadd.s32 q8, q8, q9" + - + asm_text: "vqadd.s64 q8, q8, q9" + - + asm_text: "vqadd.u8 q8, q8, q9" + - + asm_text: "vqadd.u16 q8, q8, q9" + - + asm_text: "vqadd.u32 q8, q8, q9" + - + asm_text: "vqadd.u64 q8, q8, q9" + - + asm_text: "vaddhn.i16 d16, q8, q9" + - + asm_text: "vaddhn.i32 d16, q8, q9" + - + asm_text: "vaddhn.i64 d16, q8, q9" + - + asm_text: "vraddhn.i16 d16, q8, q9" + - + asm_text: "vraddhn.i32 d16, q8, q9" + - + asm_text: "vraddhn.i64 d16, q8, q9" + - + asm_text: "vadd.i8 d6, d6, d5" + - + asm_text: "vadd.i16 d7, d7, d1" + - + asm_text: "vadd.i32 d8, d8, d2" + - + asm_text: "vadd.i64 d9, d9, d3" + - + asm_text: "vadd.i8 q6, q6, q5" + - + asm_text: "vadd.i16 q7, q7, q1" + - + asm_text: "vadd.i32 q8, q8, q2" + - + asm_text: "vadd.i64 q9, q9, q3" + - + asm_text: "vaddw.s8 q6, q6, d5" + - + asm_text: "vaddw.s16 q7, q7, d1" + - + asm_text: "vaddw.s32 q8, q8, d2" + - + asm_text: "vaddw.u8 q6, q6, d5" + - + asm_text: "vaddw.u16 q7, q7, d1" + - + asm_text: "vaddw.u32 q8, q8, d2" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-bitcount-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-bitcount-encoding.s.yaml new file mode 100644 index 0000000..44fcb1b --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-bitcount-encoding.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x05, 0xf0, 0xf3, 0x60, 0x05, 0xf0, 0xf3, 0xa0, 0x04, 0xf0, 0xf3, 0xa0, 0x04, 0xf4, 0xf3, 0xa0, 0x04, 0xf8, 0xf3, 0xe0, 0x04, 0xf0, 0xf3, 0xe0, 0x04, 0xf4, 0xf3, 0xe0, 0x04, 0xf8, 0xf3, 0x20, 0x04, 0xf0, 0xf3, 0x20, 0x04, 0xf4, 0xf3, 0x20, 0x04, 0xf8, 0xf3, 0x60, 0x04, 0xf0, 0xf3, 0x60, 0x04, 0xf4, 0xf3, 0x60, 0x04, 0xf8, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vcnt.8 d16, d16" + - + asm_text: "vcnt.8 q8, q8" + - + asm_text: "vclz.i8 d16, d16" + - + asm_text: "vclz.i16 d16, d16" + - + asm_text: "vclz.i32 d16, d16" + - + asm_text: "vclz.i8 q8, q8" + - + asm_text: "vclz.i16 q8, q8" + - + asm_text: "vclz.i32 q8, q8" + - + asm_text: "vcls.s8 d16, d16" + - + asm_text: "vcls.s16 d16, d16" + - + asm_text: "vcls.s32 d16, d16" + - + asm_text: "vcls.s8 q8, q8" + - + asm_text: "vcls.s16 q8, q8" + - + asm_text: "vcls.s32 q8, q8" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-bitwise-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-bitwise-encoding.s.yaml new file mode 100644 index 0000000..df1ee14 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-bitwise-encoding.s.yaml @@ -0,0 +1,310 @@ +test_cases: + - + input: + bytes: [ 0xb0, 0x01, 0x41, 0xf2, 0xf2, 0x01, 0x40, 0xf2, 0xb0, 0x01, 0x41, 0xf3, 0xf2, 0x01, 0x40, 0xf3, 0xb0, 0x01, 0x61, 0xf2, 0xf2, 0x01, 0x60, 0xf2, 0x11, 0x07, 0xc0, 0xf2, 0x51, 0x07, 0xc0, 0xf2, 0x50, 0x01, 0xc0, 0xf2, 0xb0, 0x01, 0x51, 0xf2, 0xf2, 0x01, 0x50, 0xf2, 0xf6, 0x41, 0x54, 0xf2, 0x11, 0x91, 0x19, 0xf2, 0x3f, 0x0b, 0xc7, 0xf3, 0x7f, 0x0b, 0xc7, 0xf3, 0x3f, 0x09, 0xc7, 0xf3, 0x7f, 0x09, 0xc7, 0xf3, 0x3f, 0x07, 0xc7, 0xf3, 0x7f, 0x07, 0xc7, 0xf3, 0x3f, 0x05, 0xc7, 0xf3, 0x7f, 0x05, 0xc7, 0xf3, 0x3f, 0x03, 0xc7, 0xf3, 0x7f, 0x03, 0xc7, 0xf3, 0x3f, 0x01, 0xc7, 0xf3, 0x7f, 0x01, 0xc7, 0xf3, 0x3c, 0xa9, 0x87, 0xf3, 0x7c, 0x49, 0xc7, 0xf3, 0x3c, 0xab, 0x87, 0xf3, 0x7c, 0x4b, 0xc7, 0xf3, 0x3c, 0xa7, 0x87, 0xf3, 0x7c, 0x47, 0xc7, 0xf3, 0x3c, 0xa5, 0x87, 0xf3, 0x7c, 0x45, 0xc7, 0xf3, 0x3c, 0xa3, 0x87, 0xf3, 0x7c, 0x43, 0xc7, 0xf3, 0x3c, 0xa1, 0x87, 0xf3, 0x7c, 0x41, 0xc7, 0xf3, 0xb0, 0x01, 0x71, 0xf2, 0xf2, 0x01, 0x70, 0xf2, 0xa0, 0x05, 0xf0, 0xf3, 0xe0, 0x05, 0xf0, 0xf3, 0xb0, 0x21, 0x51, 0xf3, 0xf2, 0x01, 0x54, 0xf3, 0xb0, 0x21, 0x61, 0xf3, 0xf2, 0x01, 0x64, 0xf3, 0xb0, 0x21, 0x71, 0xf3, 0xf2, 0x01, 0x74, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x5a, 0xc1, 0x0c, 0xf2, 0x5a, 0xc1, 0x0c, 0xf2, 0x52, 0xe1, 0x0e, 0xf2, 0xd4, 0x01, 0x40, 0xf2, 0xd4, 0x01, 0x40, 0xf2, 0x5a, 0xc1, 0x0c, 0xf3, 0x5a, 0xc1, 0x0c, 0xf3, 0x52, 0xe1, 0x0e, 0xf3, 0xd4, 0x01, 0x40, 0xf3, 0xd4, 0x01, 0x40, 0xf3, 0x5a, 0xc1, 0x0c, 0xf3, 0x5a, 0xc1, 0x0c, 0xf3, 0x52, 0xe1, 0x0e, 0xf3, 0xd4, 0x01, 0x40, 0xf3, 0xd4, 0x01, 0x40, 0xf3, 0x4a, 0xa2, 0xb5, 0xf3, 0x05, 0x52, 0xb5, 0xf3, 0x56, 0xa8, 0x1a, 0xf3, 0x13, 0x58, 0x15, 0xf3, 0x46, 0xa3, 0x1a, 0xf2, 0x03, 0x53, 0x15, 0xf2, 0x56, 0xa3, 0x1a, 0xf2, 0x13, 0x53, 0x15, 0xf2, 0x4a, 0xa0, 0xb5, 0xf3, 0x05, 0x50, 0xb5, 0xf3, 0xca, 0xa0, 0xb5, 0xf3, 0x85, 0x50, 0xb5, 0xf3, 0x4a, 0xa1, 0xb5, 0xf3, 0x05, 0x51, 0xb5, 0xf3, 0xca, 0xa1, 0xb5, 0xf3, 0x85, 0x51, 0xb5, 0xf3, 0x3e, 0x5e, 0x05, 0xf3, 0x56, 0xae, 0x0a, 0xf3, 0x3e, 0x5e, 0x25, 0xf3, 0x56, 0xae, 0x2a, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vand d16, d17, d16" + - + asm_text: "vand q8, q8, q9" + - + asm_text: "veor d16, d17, d16" + - + asm_text: "veor q8, q8, q9" + - + asm_text: "vorr d16, d17, d16" + - + asm_text: "vorr q8, q8, q9" + - + asm_text: "vorr.i32 d16, #0x1000000" + - + asm_text: "vorr.i32 q8, #0x1000000" + - + asm_text: "vorr.i32 q8, #0x0" + - + asm_text: "vbic d16, d17, d16" + - + asm_text: "vbic q8, q8, q9" + - + asm_text: "vbic q10, q10, q11" + - + asm_text: "vbic d9, d9, d1" + - + asm_text: "vbic.i16 d16, #0xff00" + - + asm_text: "vbic.i16 q8, #0xff00" + - + asm_text: "vbic.i16 d16, #0xff" + - + asm_text: "vbic.i16 q8, #0xff" + - + asm_text: "vbic.i32 d16, #0xff000000" + - + asm_text: "vbic.i32 q8, #0xff000000" + - + asm_text: "vbic.i32 d16, #0xff0000" + - + asm_text: "vbic.i32 q8, #0xff0000" + - + asm_text: "vbic.i32 d16, #0xff00" + - + asm_text: "vbic.i32 q8, #0xff00" + - + asm_text: "vbic.i32 d16, #0xff" + - + asm_text: "vbic.i32 q8, #0xff" + - + asm_text: "vbic.i16 d10, #0xfc" + - + asm_text: "vbic.i16 q10, #0xfc" + - + asm_text: "vbic.i16 d10, #0xfc00" + - + asm_text: "vbic.i16 q10, #0xfc00" + - + asm_text: "vbic.i32 d10, #0xfc000000" + - + asm_text: "vbic.i32 q10, #0xfc000000" + - + asm_text: "vbic.i32 d10, #0xfc0000" + - + asm_text: "vbic.i32 q10, #0xfc0000" + - + asm_text: "vbic.i32 d10, #0xfc00" + - + asm_text: "vbic.i32 q10, #0xfc00" + - + asm_text: "vbic.i32 d10, #0xfc" + - + asm_text: "vbic.i32 q10, #0xfc" + - + asm_text: "vorn d16, d17, d16" + - + asm_text: "vorn q8, q8, q9" + - + asm_text: "vmvn d16, d16" + - + asm_text: "vmvn q8, q8" + - + asm_text: "vbsl d18, d17, d16" + - + asm_text: "vbsl q8, q10, q9" + - + asm_text: "vbit d18, d17, d16" + - + asm_text: "vbit q8, q10, q9" + - + asm_text: "vbif d18, d17, d16" + - + asm_text: "vbif q8, q10, q9" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vand q6, q6, q5" + - + asm_text: "vand q6, q6, q5" + - + asm_text: "vand q7, q7, q1" + - + asm_text: "vand q8, q8, q2" + - + asm_text: "vand q8, q8, q2" + - + asm_text: "veor q6, q6, q5" + - + asm_text: "veor q6, q6, q5" + - + asm_text: "veor q7, q7, q1" + - + asm_text: "veor q8, q8, q2" + - + asm_text: "veor q8, q8, q2" + - + asm_text: "veor q6, q6, q5" + - + asm_text: "veor q6, q6, q5" + - + asm_text: "veor q7, q7, q1" + - + asm_text: "veor q8, q8, q2" + - + asm_text: "veor q8, q8, q2" + - + asm_text: "vclt.s16 q5, q5, #0" + - + asm_text: "vclt.s16 d5, d5, #0" + - + asm_text: "vceq.i16 q5, q5, q3" + - + asm_text: "vceq.i16 d5, d5, d3" + - + asm_text: "vcgt.s16 q5, q5, q3" + - + asm_text: "vcgt.s16 d5, d5, d3" + - + asm_text: "vcge.s16 q5, q5, q3" + - + asm_text: "vcge.s16 d5, d5, d3" + - + asm_text: "vcgt.s16 q5, q5, #0" + - + asm_text: "vcgt.s16 d5, d5, #0" + - + asm_text: "vcge.s16 q5, q5, #0" + - + asm_text: "vcge.s16 d5, d5, #0" + - + asm_text: "vceq.i16 q5, q5, #0" + - + asm_text: "vceq.i16 d5, d5, #0" + - + asm_text: "vcle.s16 q5, q5, #0" + - + asm_text: "vcle.s16 d5, d5, #0" + - + asm_text: "vacge.f32 d5, d5, d30" + - + asm_text: "vacge.f32 q5, q5, q3" + - + asm_text: "vacgt.f32 d5, d5, d30" + - + asm_text: "vacgt.f32 q5, q5, q3" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-cmp-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-cmp-encoding.s.yaml new file mode 100644 index 0000000..8a72f2f --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-cmp-encoding.s.yaml @@ -0,0 +1,182 @@ +test_cases: + - + input: + bytes: [ 0xb1, 0x08, 0x40, 0xf3, 0xb1, 0x08, 0x50, 0xf3, 0xb1, 0x08, 0x60, 0xf3, 0xa1, 0x0e, 0x40, 0xf2, 0xf2, 0x08, 0x40, 0xf3, 0xf2, 0x08, 0x50, 0xf3, 0xf2, 0x08, 0x60, 0xf3, 0xe2, 0x0e, 0x40, 0xf2, 0xb1, 0x03, 0x40, 0xf2, 0xb1, 0x03, 0x50, 0xf2, 0xb1, 0x03, 0x60, 0xf2, 0xb1, 0x03, 0x40, 0xf3, 0xb1, 0x03, 0x50, 0xf3, 0xb1, 0x03, 0x60, 0xf3, 0xa1, 0x0e, 0x40, 0xf3, 0xf2, 0x03, 0x40, 0xf2, 0xf2, 0x03, 0x50, 0xf2, 0xf2, 0x03, 0x60, 0xf2, 0xf2, 0x03, 0x40, 0xf3, 0xf2, 0x03, 0x50, 0xf3, 0xf2, 0x03, 0x60, 0xf3, 0xe2, 0x0e, 0x40, 0xf3, 0xb1, 0x0e, 0x40, 0xf3, 0xf2, 0x0e, 0x40, 0xf3, 0xa1, 0x03, 0x40, 0xf2, 0xa1, 0x03, 0x50, 0xf2, 0xa1, 0x03, 0x60, 0xf2, 0xa1, 0x03, 0x40, 0xf3, 0xa1, 0x03, 0x50, 0xf3, 0xa1, 0x03, 0x60, 0xf3, 0xa1, 0x0e, 0x60, 0xf3, 0xe2, 0x03, 0x40, 0xf2, 0xe2, 0x03, 0x50, 0xf2, 0xe2, 0x03, 0x60, 0xf2, 0xe2, 0x03, 0x40, 0xf3, 0xe2, 0x03, 0x50, 0xf3, 0xe2, 0x03, 0x60, 0xf3, 0xe2, 0x0e, 0x60, 0xf3, 0xb1, 0x0e, 0x60, 0xf3, 0xf2, 0x0e, 0x60, 0xf3, 0xb1, 0x08, 0x40, 0xf2, 0xb1, 0x08, 0x50, 0xf2, 0xb1, 0x08, 0x60, 0xf2, 0xf2, 0x08, 0x40, 0xf2, 0xf2, 0x08, 0x50, 0xf2, 0xf2, 0x08, 0x60, 0xf2, 0x20, 0x01, 0xf1, 0xf3, 0xa0, 0x00, 0xf1, 0xf3, 0xa0, 0x01, 0xf1, 0xf3, 0x20, 0x00, 0xf1, 0xf3, 0x20, 0x02, 0xf1, 0xf3, 0x6a, 0x83, 0x46, 0xf2, 0x6a, 0x83, 0x56, 0xf2, 0x6a, 0x83, 0x66, 0xf2, 0x6a, 0x83, 0x46, 0xf3, 0x6a, 0x83, 0x56, 0xf3, 0x6a, 0x83, 0x66, 0xf3, 0x6a, 0x8e, 0x66, 0xf3, 0x0d, 0xc3, 0x03, 0xf2, 0x0d, 0xc3, 0x13, 0xf2, 0x0d, 0xc3, 0x23, 0xf2, 0x0d, 0xc3, 0x03, 0xf3, 0x0d, 0xc3, 0x13, 0xf3, 0x0d, 0xc3, 0x23, 0xf3, 0x0d, 0xce, 0x23, 0xf3, 0xb0, 0x03, 0x41, 0xf2, 0xb0, 0x03, 0x51, 0xf2, 0xb0, 0x03, 0x61, 0xf2, 0xb0, 0x03, 0x41, 0xf3, 0xb0, 0x03, 0x51, 0xf3, 0xb0, 0x03, 0x61, 0xf3, 0xa0, 0x0e, 0x41, 0xf3, 0xf0, 0x03, 0x42, 0xf2, 0xf0, 0x03, 0x52, 0xf2, 0xf0, 0x03, 0x62, 0xf2, 0xf0, 0x03, 0x42, 0xf3, 0xf0, 0x03, 0x52, 0xf3, 0xf0, 0x03, 0x62, 0xf3, 0xe0, 0x0e, 0x42, 0xf3, 0xf6, 0x2e, 0x68, 0xf3, 0x1b, 0x9e, 0x2c, 0xf3, 0xf6, 0x6e, 0x68, 0xf3, 0x1b, 0xbe, 0x2c, 0xf3, 0xf6, 0x2e, 0x48, 0xf3, 0x1b, 0x9e, 0x0c, 0xf3, 0xf6, 0x6e, 0x48, 0xf3, 0x1b, 0xbe, 0x0c, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vceq.i8 d16, d16, d17" + - + asm_text: "vceq.i16 d16, d16, d17" + - + asm_text: "vceq.i32 d16, d16, d17" + - + asm_text: "vceq.f32 d16, d16, d17" + - + asm_text: "vceq.i8 q8, q8, q9" + - + asm_text: "vceq.i16 q8, q8, q9" + - + asm_text: "vceq.i32 q8, q8, q9" + - + asm_text: "vceq.f32 q8, q8, q9" + - + asm_text: "vcge.s8 d16, d16, d17" + - + asm_text: "vcge.s16 d16, d16, d17" + - + asm_text: "vcge.s32 d16, d16, d17" + - + asm_text: "vcge.u8 d16, d16, d17" + - + asm_text: "vcge.u16 d16, d16, d17" + - + asm_text: "vcge.u32 d16, d16, d17" + - + asm_text: "vcge.f32 d16, d16, d17" + - + asm_text: "vcge.s8 q8, q8, q9" + - + asm_text: "vcge.s16 q8, q8, q9" + - + asm_text: "vcge.s32 q8, q8, q9" + - + asm_text: "vcge.u8 q8, q8, q9" + - + asm_text: "vcge.u16 q8, q8, q9" + - + asm_text: "vcge.u32 q8, q8, q9" + - + asm_text: "vcge.f32 q8, q8, q9" + - + asm_text: "vacge.f32 d16, d16, d17" + - + asm_text: "vacge.f32 q8, q8, q9" + - + asm_text: "vcgt.s8 d16, d16, d17" + - + asm_text: "vcgt.s16 d16, d16, d17" + - + asm_text: "vcgt.s32 d16, d16, d17" + - + asm_text: "vcgt.u8 d16, d16, d17" + - + asm_text: "vcgt.u16 d16, d16, d17" + - + asm_text: "vcgt.u32 d16, d16, d17" + - + asm_text: "vcgt.f32 d16, d16, d17" + - + asm_text: "vcgt.s8 q8, q8, q9" + - + asm_text: "vcgt.s16 q8, q8, q9" + - + asm_text: "vcgt.s32 q8, q8, q9" + - + asm_text: "vcgt.u8 q8, q8, q9" + - + asm_text: "vcgt.u16 q8, q8, q9" + - + asm_text: "vcgt.u32 q8, q8, q9" + - + asm_text: "vcgt.f32 q8, q8, q9" + - + asm_text: "vacgt.f32 d16, d16, d17" + - + asm_text: "vacgt.f32 q8, q8, q9" + - + asm_text: "vtst.8 d16, d16, d17" + - + asm_text: "vtst.16 d16, d16, d17" + - + asm_text: "vtst.32 d16, d16, d17" + - + asm_text: "vtst.8 q8, q8, q9" + - + asm_text: "vtst.16 q8, q8, q9" + - + asm_text: "vtst.32 q8, q8, q9" + - + asm_text: "vceq.i8 d16, d16, #0" + - + asm_text: "vcge.s8 d16, d16, #0" + - + asm_text: "vcle.s8 d16, d16, #0" + - + asm_text: "vcgt.s8 d16, d16, #0" + - + asm_text: "vclt.s8 d16, d16, #0" + - + asm_text: "vcgt.s8 q12, q3, q13" + - + asm_text: "vcgt.s16 q12, q3, q13" + - + asm_text: "vcgt.s32 q12, q3, q13" + - + asm_text: "vcgt.u8 q12, q3, q13" + - + asm_text: "vcgt.u16 q12, q3, q13" + - + asm_text: "vcgt.u32 q12, q3, q13" + - + asm_text: "vcgt.f32 q12, q3, q13" + - + asm_text: "vcgt.s8 d12, d3, d13" + - + asm_text: "vcgt.s16 d12, d3, d13" + - + asm_text: "vcgt.s32 d12, d3, d13" + - + asm_text: "vcgt.u8 d12, d3, d13" + - + asm_text: "vcgt.u16 d12, d3, d13" + - + asm_text: "vcgt.u32 d12, d3, d13" + - + asm_text: "vcgt.f32 d12, d3, d13" + - + asm_text: "vcge.s8 d16, d17, d16" + - + asm_text: "vcge.s16 d16, d17, d16" + - + asm_text: "vcge.s32 d16, d17, d16" + - + asm_text: "vcge.u8 d16, d17, d16" + - + asm_text: "vcge.u16 d16, d17, d16" + - + asm_text: "vcge.u32 d16, d17, d16" + - + asm_text: "vcge.f32 d16, d17, d16" + - + asm_text: "vcge.s8 q8, q9, q8" + - + asm_text: "vcge.s16 q8, q9, q8" + - + asm_text: "vcge.s32 q8, q9, q8" + - + asm_text: "vcge.u8 q8, q9, q8" + - + asm_text: "vcge.u16 q8, q9, q8" + - + asm_text: "vcge.u32 q8, q9, q8" + - + asm_text: "vcge.f32 q8, q9, q8" + - + asm_text: "vacgt.f32 q9, q12, q11" + - + asm_text: "vacgt.f32 d9, d12, d11" + - + asm_text: "vacgt.f32 q11, q12, q11" + - + asm_text: "vacgt.f32 d11, d12, d11" + - + asm_text: "vacge.f32 q9, q12, q11" + - + asm_text: "vacge.f32 d9, d12, d11" + - + asm_text: "vacge.f32 q11, q12, q11" + - + asm_text: "vacge.f32 d11, d12, d11" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-convert-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-convert-encoding.s.yaml new file mode 100644 index 0000000..dd1a7b4 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-convert-encoding.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x07, 0xfb, 0xf3, 0xa0, 0x07, 0xfb, 0xf3, 0x20, 0x06, 0xfb, 0xf3, 0xa0, 0x06, 0xfb, 0xf3, 0x60, 0x07, 0xfb, 0xf3, 0xe0, 0x07, 0xfb, 0xf3, 0x60, 0x06, 0xfb, 0xf3, 0xe0, 0x06, 0xfb, 0xf3, 0x30, 0x0f, 0xff, 0xf2, 0x20, 0x07, 0xfb, 0xf3, 0x30, 0x0f, 0xff, 0xf3, 0xa0, 0x07, 0xfb, 0xf3, 0x30, 0x0e, 0xff, 0xf2, 0x20, 0x06, 0xfb, 0xf3, 0x30, 0x0e, 0xff, 0xf3, 0xa0, 0x06, 0xfb, 0xf3, 0x70, 0x0f, 0xff, 0xf2, 0x60, 0x07, 0xfb, 0xf3, 0x70, 0x0f, 0xff, 0xf3, 0xe0, 0x07, 0xfb, 0xf3, 0x70, 0x0e, 0xff, 0xf2, 0x60, 0x06, 0xfb, 0xf3, 0x70, 0x0e, 0xff, 0xf3, 0xe0, 0x06, 0xfb, 0xf3, 0x20, 0x07, 0xf6, 0xf3, 0x20, 0x06, 0xf6, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vcvt.s32.f32 d16, d16" + - + asm_text: "vcvt.u32.f32 d16, d16" + - + asm_text: "vcvt.f32.s32 d16, d16" + - + asm_text: "vcvt.f32.u32 d16, d16" + - + asm_text: "vcvt.s32.f32 q8, q8" + - + asm_text: "vcvt.u32.f32 q8, q8" + - + asm_text: "vcvt.f32.s32 q8, q8" + - + asm_text: "vcvt.f32.u32 q8, q8" + - + asm_text: "vcvt.s32.f32 d16, d16, #1" + - + asm_text: "vcvt.s32.f32 d16, d16" + - + asm_text: "vcvt.u32.f32 d16, d16, #1" + - + asm_text: "vcvt.u32.f32 d16, d16" + - + asm_text: "vcvt.f32.s32 d16, d16, #1" + - + asm_text: "vcvt.f32.s32 d16, d16" + - + asm_text: "vcvt.f32.u32 d16, d16, #1" + - + asm_text: "vcvt.f32.u32 d16, d16" + - + asm_text: "vcvt.s32.f32 q8, q8, #1" + - + asm_text: "vcvt.s32.f32 q8, q8" + - + asm_text: "vcvt.u32.f32 q8, q8, #1" + - + asm_text: "vcvt.u32.f32 q8, q8" + - + asm_text: "vcvt.f32.s32 q8, q8, #1" + - + asm_text: "vcvt.f32.s32 q8, q8" + - + asm_text: "vcvt.f32.u32 q8, q8, #1" + - + asm_text: "vcvt.f32.u32 q8, q8" + - + asm_text: "vcvt.f32.f16 q8, d16" + - + asm_text: "vcvt.f16.f32 d16, q8" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-crypto.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-crypto.s.yaml new file mode 100644 index 0000000..bcabb88 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-crypto.s.yaml @@ -0,0 +1,38 @@ +test_cases: + - + input: + bytes: [ 0x42, 0x03, 0xb0, 0xf3, 0x02, 0x03, 0xb0, 0xf3, 0xc2, 0x03, 0xb0, 0xf3, 0x82, 0x03, 0xb0, 0xf3, 0xc2, 0x02, 0xb9, 0xf3, 0x82, 0x03, 0xba, 0xf3, 0xc2, 0x03, 0xba, 0xf3, 0x44, 0x0c, 0x02, 0xf2, 0x44, 0x0c, 0x22, 0xf2, 0x44, 0x0c, 0x12, 0xf2, 0x44, 0x0c, 0x32, 0xf2, 0x44, 0x0c, 0x02, 0xf3, 0x44, 0x0c, 0x12, 0xf3, 0x44, 0x0c, 0x22, 0xf3, 0xa1, 0x0e, 0xe0, 0xf2 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "aesd.8 q0, q1" + - + asm_text: "aese.8 q0, q1" + - + asm_text: "aesimc.8 q0, q1" + - + asm_text: "aesmc.8 q0, q1" + - + asm_text: "sha1h.32 q0, q1" + - + asm_text: "sha1su1.32 q0, q1" + - + asm_text: "sha256su0.32 q0, q1" + - + asm_text: "sha1c.32 q0, q1, q2" + - + asm_text: "sha1m.32 q0, q1, q2" + - + asm_text: "sha1p.32 q0, q1, q2" + - + asm_text: "sha1su0.32 q0, q1, q2" + - + asm_text: "sha256h.32 q0, q1, q2" + - + asm_text: "sha256h2.32 q0, q1, q2" + - + asm_text: "sha256su1.32 q0, q1, q2" + - + asm_text: "vmull.p64 q8, d16, d17" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-dup-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-dup-encoding.s.yaml new file mode 100644 index 0000000..00c93e4 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-dup-encoding.s.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0x90, 0x0b, 0xc0, 0xee, 0xb0, 0x0b, 0x80, 0xee, 0x90, 0x0b, 0x80, 0xee, 0x90, 0x0b, 0xe0, 0xee, 0xb0, 0x0b, 0xa0, 0xee, 0x90, 0x0b, 0xa0, 0xee, 0x20, 0x0c, 0xf3, 0xf3, 0x20, 0x0c, 0xf6, 0xf3, 0x20, 0x0c, 0xfc, 0xf3, 0x60, 0x0c, 0xf3, 0xf3, 0x60, 0x0c, 0xf6, 0xf3, 0x60, 0x0c, 0xfc, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vdup.8 d16, r0" + - + asm_text: "vdup.16 d16, r0" + - + asm_text: "vdup.32 d16, r0" + - + asm_text: "vdup.8 q8, r0" + - + asm_text: "vdup.16 q8, r0" + - + asm_text: "vdup.32 q8, r0" + - + asm_text: "vdup.8 d16, d16[1]" + - + asm_text: "vdup.16 d16, d16[1]" + - + asm_text: "vdup.32 d16, d16[1]" + - + asm_text: "vdup.8 q8, d16[1]" + - + asm_text: "vdup.16 q8, d16[1]" + - + asm_text: "vdup.32 q8, d16[1]" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-minmax-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-minmax-encoding.s.yaml new file mode 100644 index 0000000..83bb5e2 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-minmax-encoding.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x03, 0x16, 0x02, 0xf2, 0x06, 0x46, 0x15, 0xf2, 0x09, 0x76, 0x28, 0xf2, 0x0c, 0xa6, 0x0b, 0xf3, 0x0f, 0xd6, 0x1e, 0xf3, 0xa2, 0x06, 0x61, 0xf3, 0xa5, 0x3f, 0x44, 0xf2, 0x03, 0x26, 0x02, 0xf2, 0x06, 0x56, 0x15, 0xf2, 0x09, 0x86, 0x28, 0xf2, 0x0c, 0xb6, 0x0b, 0xf3, 0x0f, 0xe6, 0x1e, 0xf3, 0xa2, 0x16, 0x61, 0xf3, 0xa5, 0x4f, 0x44, 0xf2, 0x46, 0x26, 0x04, 0xf2, 0x4c, 0x86, 0x1a, 0xf2, 0xe2, 0xe6, 0x20, 0xf2, 0xe8, 0x46, 0x46, 0xf3, 0xee, 0xa6, 0x5c, 0xf3, 0x60, 0xc6, 0x2e, 0xf3, 0x42, 0x2f, 0x4a, 0xf2, 0x46, 0x46, 0x04, 0xf2, 0x4c, 0xa6, 0x1a, 0xf2, 0xe2, 0x06, 0x60, 0xf2, 0xc4, 0x66, 0x46, 0xf3, 0x4a, 0x86, 0x18, 0xf3, 0x60, 0xe6, 0x2e, 0xf3, 0x42, 0x4f, 0x04, 0xf2, 0x13, 0x16, 0x02, 0xf2, 0x16, 0x46, 0x15, 0xf2, 0x19, 0x76, 0x28, 0xf2, 0x1c, 0xa6, 0x0b, 0xf3, 0x1f, 0xd6, 0x1e, 0xf3, 0xb2, 0x06, 0x61, 0xf3, 0xa5, 0x3f, 0x64, 0xf2, 0x13, 0x26, 0x02, 0xf2, 0x16, 0x56, 0x15, 0xf2, 0x19, 0x86, 0x28, 0xf2, 0x1c, 0xb6, 0x0b, 0xf3, 0x1f, 0xe6, 0x1e, 0xf3, 0xb2, 0x16, 0x61, 0xf3, 0xa5, 0x4f, 0x64, 0xf2, 0x56, 0x26, 0x04, 0xf2, 0x5c, 0x86, 0x1a, 0xf2, 0xf2, 0xe6, 0x20, 0xf2, 0xf8, 0x46, 0x46, 0xf3, 0xfe, 0xa6, 0x5c, 0xf3, 0x70, 0xc6, 0x2e, 0xf3, 0x42, 0x2f, 0x6a, 0xf2, 0x56, 0x46, 0x04, 0xf2, 0x5c, 0xa6, 0x1a, 0xf2, 0xf2, 0x06, 0x60, 0xf2, 0xd4, 0x66, 0x46, 0xf3, 0x5a, 0x86, 0x18, 0xf3, 0x70, 0xe6, 0x2e, 0xf3, 0x42, 0x4f, 0x24, 0xf2 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmax.s8 d1, d2, d3" + - + asm_text: "vmax.s16 d4, d5, d6" + - + asm_text: "vmax.s32 d7, d8, d9" + - + asm_text: "vmax.u8 d10, d11, d12" + - + asm_text: "vmax.u16 d13, d14, d15" + - + asm_text: "vmax.u32 d16, d17, d18" + - + asm_text: "vmax.f32 d19, d20, d21" + - + asm_text: "vmax.s8 d2, d2, d3" + - + asm_text: "vmax.s16 d5, d5, d6" + - + asm_text: "vmax.s32 d8, d8, d9" + - + asm_text: "vmax.u8 d11, d11, d12" + - + asm_text: "vmax.u16 d14, d14, d15" + - + asm_text: "vmax.u32 d17, d17, d18" + - + asm_text: "vmax.f32 d20, d20, d21" + - + asm_text: "vmax.s8 q1, q2, q3" + - + asm_text: "vmax.s16 q4, q5, q6" + - + asm_text: "vmax.s32 q7, q8, q9" + - + asm_text: "vmax.u8 q10, q11, q12" + - + asm_text: "vmax.u16 q13, q14, q15" + - + asm_text: "vmax.u32 q6, q7, q8" + - + asm_text: "vmax.f32 q9, q5, q1" + - + asm_text: "vmax.s8 q2, q2, q3" + - + asm_text: "vmax.s16 q5, q5, q6" + - + asm_text: "vmax.s32 q8, q8, q9" + - + asm_text: "vmax.u8 q11, q11, q2" + - + asm_text: "vmax.u16 q4, q4, q5" + - + asm_text: "vmax.u32 q7, q7, q8" + - + asm_text: "vmax.f32 q2, q2, q1" + - + asm_text: "vmin.s8 d1, d2, d3" + - + asm_text: "vmin.s16 d4, d5, d6" + - + asm_text: "vmin.s32 d7, d8, d9" + - + asm_text: "vmin.u8 d10, d11, d12" + - + asm_text: "vmin.u16 d13, d14, d15" + - + asm_text: "vmin.u32 d16, d17, d18" + - + asm_text: "vmin.f32 d19, d20, d21" + - + asm_text: "vmin.s8 d2, d2, d3" + - + asm_text: "vmin.s16 d5, d5, d6" + - + asm_text: "vmin.s32 d8, d8, d9" + - + asm_text: "vmin.u8 d11, d11, d12" + - + asm_text: "vmin.u16 d14, d14, d15" + - + asm_text: "vmin.u32 d17, d17, d18" + - + asm_text: "vmin.f32 d20, d20, d21" + - + asm_text: "vmin.s8 q1, q2, q3" + - + asm_text: "vmin.s16 q4, q5, q6" + - + asm_text: "vmin.s32 q7, q8, q9" + - + asm_text: "vmin.u8 q10, q11, q12" + - + asm_text: "vmin.u16 q13, q14, q15" + - + asm_text: "vmin.u32 q6, q7, q8" + - + asm_text: "vmin.f32 q9, q5, q1" + - + asm_text: "vmin.s8 q2, q2, q3" + - + asm_text: "vmin.s16 q5, q5, q6" + - + asm_text: "vmin.s32 q8, q8, q9" + - + asm_text: "vmin.u8 q11, q11, q2" + - + asm_text: "vmin.u16 q4, q4, q5" + - + asm_text: "vmin.u32 q7, q7, q8" + - + asm_text: "vmin.f32 q2, q2, q1" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-mov-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-mov-encoding.s.yaml new file mode 100644 index 0000000..52866b2 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-mov-encoding.s.yaml @@ -0,0 +1,158 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x0e, 0xc0, 0xf2, 0x10, 0x08, 0xc1, 0xf2, 0x10, 0x0a, 0xc1, 0xf2, 0x10, 0x00, 0xc2, 0xf2, 0x10, 0x02, 0xc2, 0xf2, 0x10, 0x04, 0xc2, 0xf2, 0x10, 0x06, 0xc2, 0xf2, 0x10, 0x0c, 0xc2, 0xf2, 0x10, 0x0d, 0xc2, 0xf2, 0x33, 0x0e, 0xc1, 0xf3, 0x58, 0x0e, 0xc0, 0xf2, 0x50, 0x08, 0xc1, 0xf2, 0x50, 0x0a, 0xc1, 0xf2, 0x50, 0x00, 0xc2, 0xf2, 0x50, 0x02, 0xc2, 0xf2, 0x50, 0x04, 0xc2, 0xf2, 0x50, 0x06, 0xc2, 0xf2, 0x50, 0x0c, 0xc2, 0xf2, 0x50, 0x0d, 0xc2, 0xf2, 0x73, 0x0e, 0xc1, 0xf3, 0x30, 0x08, 0xc1, 0xf2, 0x30, 0x0a, 0xc1, 0xf2, 0x30, 0x00, 0xc2, 0xf2, 0x30, 0x02, 0xc2, 0xf2, 0x30, 0x04, 0xc2, 0xf2, 0x30, 0x06, 0xc2, 0xf2, 0x30, 0x0c, 0xc2, 0xf2, 0x30, 0x0d, 0xc2, 0xf2, 0x30, 0x0a, 0xc8, 0xf2, 0x30, 0x0a, 0xd0, 0xf2, 0x30, 0x0a, 0xe0, 0xf2, 0x30, 0x0a, 0xc8, 0xf3, 0x30, 0x0a, 0xd0, 0xf3, 0x30, 0x0a, 0xe0, 0xf3, 0x20, 0x02, 0xf2, 0xf3, 0x20, 0x02, 0xf6, 0xf3, 0x20, 0x02, 0xfa, 0xf3, 0xa0, 0x02, 0xf2, 0xf3, 0xa0, 0x02, 0xf6, 0xf3, 0xa0, 0x02, 0xfa, 0xf3, 0xe0, 0x02, 0xf2, 0xf3, 0xe0, 0x02, 0xf6, 0xf3, 0xe0, 0x02, 0xfa, 0xf3, 0x60, 0x02, 0xf2, 0xf3, 0x60, 0x02, 0xf6, 0xf3, 0x60, 0x02, 0xfa, 0xf3, 0xb0, 0x0b, 0x50, 0xee, 0xf0, 0x0b, 0x10, 0xee, 0xb0, 0x0b, 0xd0, 0xee, 0xf0, 0x0b, 0x90, 0xee, 0x90, 0x0b, 0x30, 0xee, 0xb0, 0x1b, 0x40, 0xee, 0xf0, 0x1b, 0x00, 0xee, 0x90, 0x1b, 0x20, 0xee, 0xb0, 0x1b, 0x42, 0xee, 0xf0, 0x1b, 0x02, 0xee, 0x90, 0x1b, 0x22, 0xee, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmov.i8 d16, #0x8" + - + asm_text: "vmov.i16 d16, #0x10" + - + asm_text: "vmov.i16 d16, #0x1000" + - + asm_text: "vmov.i32 d16, #0x20" + - + asm_text: "vmov.i32 d16, #0x2000" + - + asm_text: "vmov.i32 d16, #0x200000" + - + asm_text: "vmov.i32 d16, #0x20000000" + - + asm_text: "vmov.i32 d16, #0x20ff" + - + asm_text: "vmov.i32 d16, #0x20ffff" + - + asm_text: "vmov.i64 d16, #0xff0000ff0000ffff" + - + asm_text: "vmov.i8 q8, #0x8" + - + asm_text: "vmov.i16 q8, #0x10" + - + asm_text: "vmov.i16 q8, #0x1000" + - + asm_text: "vmov.i32 q8, #0x20" + - + asm_text: "vmov.i32 q8, #0x2000" + - + asm_text: "vmov.i32 q8, #0x200000" + - + asm_text: "vmov.i32 q8, #0x20000000" + - + asm_text: "vmov.i32 q8, #0x20ff" + - + asm_text: "vmov.i32 q8, #0x20ffff" + - + asm_text: "vmov.i64 q8, #0xff0000ff0000ffff" + - + asm_text: "vmvn.i16 d16, #0x10" + - + asm_text: "vmvn.i16 d16, #0x1000" + - + asm_text: "vmvn.i32 d16, #0x20" + - + asm_text: "vmvn.i32 d16, #0x2000" + - + asm_text: "vmvn.i32 d16, #0x200000" + - + asm_text: "vmvn.i32 d16, #0x20000000" + - + asm_text: "vmvn.i32 d16, #0x20ff" + - + asm_text: "vmvn.i32 d16, #0x20ffff" + - + asm_text: "vmovl.s8 q8, d16" + - + asm_text: "vmovl.s16 q8, d16" + - + asm_text: "vmovl.s32 q8, d16" + - + asm_text: "vmovl.u8 q8, d16" + - + asm_text: "vmovl.u16 q8, d16" + - + asm_text: "vmovl.u32 q8, d16" + - + asm_text: "vmovn.i16 d16, q8" + - + asm_text: "vmovn.i32 d16, q8" + - + asm_text: "vmovn.i64 d16, q8" + - + asm_text: "vqmovn.s16 d16, q8" + - + asm_text: "vqmovn.s32 d16, q8" + - + asm_text: "vqmovn.s64 d16, q8" + - + asm_text: "vqmovn.u16 d16, q8" + - + asm_text: "vqmovn.u32 d16, q8" + - + asm_text: "vqmovn.u64 d16, q8" + - + asm_text: "vqmovun.s16 d16, q8" + - + asm_text: "vqmovun.s32 d16, q8" + - + asm_text: "vqmovun.s64 d16, q8" + - + asm_text: "vmov.s8 r0, d16[1]" + - + asm_text: "vmov.s16 r0, d16[1]" + - + asm_text: "vmov.u8 r0, d16[1]" + - + asm_text: "vmov.u16 r0, d16[1]" + - + asm_text: "vmov.32 r0, d16[1]" + - + asm_text: "vmov.8 d16[1], r1" + - + asm_text: "vmov.16 d16[1], r1" + - + asm_text: "vmov.32 d16[1], r1" + - + asm_text: "vmov.8 d18[1], r1" + - + asm_text: "vmov.16 d18[1], r1" + - + asm_text: "vmov.32 d18[1], r1" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-mul-accum-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-mul-accum-encoding.s.yaml new file mode 100644 index 0000000..023b3df --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-mul-accum-encoding.s.yaml @@ -0,0 +1,84 @@ +test_cases: + - + input: + bytes: [ 0xa1, 0x09, 0x42, 0xf2, 0xa1, 0x09, 0x52, 0xf2, 0xa1, 0x09, 0x62, 0xf2, 0xb1, 0x0d, 0x42, 0xf2, 0xe4, 0x29, 0x40, 0xf2, 0xe4, 0x29, 0x50, 0xf2, 0xe4, 0x29, 0x60, 0xf2, 0xf4, 0x2d, 0x40, 0xf2, 0xc3, 0x80, 0xe0, 0xf3, 0xa2, 0x08, 0xc3, 0xf2, 0xa2, 0x08, 0xd3, 0xf2, 0xa2, 0x08, 0xe3, 0xf2, 0xa2, 0x08, 0xc3, 0xf3, 0xa2, 0x08, 0xd3, 0xf3, 0xa2, 0x08, 0xe3, 0xf3, 0xa2, 0x09, 0xd3, 0xf2, 0xa2, 0x09, 0xe3, 0xf2, 0x47, 0x63, 0xdb, 0xf2, 0x4f, 0x63, 0xdb, 0xf2, 0x67, 0x63, 0xdb, 0xf2, 0x6f, 0x63, 0xdb, 0xf2, 0xa1, 0x09, 0x42, 0xf3, 0xa1, 0x09, 0x52, 0xf3, 0xa1, 0x09, 0x62, 0xf3, 0xb1, 0x0d, 0x62, 0xf2, 0xe4, 0x29, 0x40, 0xf3, 0xe4, 0x29, 0x50, 0xf3, 0xe4, 0x29, 0x60, 0xf3, 0xf4, 0x2d, 0x60, 0xf2, 0xe6, 0x84, 0x98, 0xf3, 0xa2, 0x0a, 0xc3, 0xf2, 0xa2, 0x0a, 0xd3, 0xf2, 0xa2, 0x0a, 0xe3, 0xf2, 0xa2, 0x0a, 0xc3, 0xf3, 0xa2, 0x0a, 0xd3, 0xf3, 0xa2, 0x0a, 0xe3, 0xf3, 0xa2, 0x0b, 0xd3, 0xf2, 0xa2, 0x0b, 0xe3, 0xf2 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmla.i8 d16, d18, d17" + - + asm_text: "vmla.i16 d16, d18, d17" + - + asm_text: "vmla.i32 d16, d18, d17" + - + asm_text: "vmla.f32 d16, d18, d17" + - + asm_text: "vmla.i8 q9, q8, q10" + - + asm_text: "vmla.i16 q9, q8, q10" + - + asm_text: "vmla.i32 q9, q8, q10" + - + asm_text: "vmla.f32 q9, q8, q10" + - + asm_text: "vmla.i32 q12, q8, d3[0]" + - + asm_text: "vmlal.s8 q8, d19, d18" + - + asm_text: "vmlal.s16 q8, d19, d18" + - + asm_text: "vmlal.s32 q8, d19, d18" + - + asm_text: "vmlal.u8 q8, d19, d18" + - + asm_text: "vmlal.u16 q8, d19, d18" + - + asm_text: "vmlal.u32 q8, d19, d18" + - + asm_text: "vqdmlal.s16 q8, d19, d18" + - + asm_text: "vqdmlal.s32 q8, d19, d18" + - + asm_text: "vqdmlal.s16 q11, d11, d7[0]" + - + asm_text: "vqdmlal.s16 q11, d11, d7[1]" + - + asm_text: "vqdmlal.s16 q11, d11, d7[2]" + - + asm_text: "vqdmlal.s16 q11, d11, d7[3]" + - + asm_text: "vmls.i8 d16, d18, d17" + - + asm_text: "vmls.i16 d16, d18, d17" + - + asm_text: "vmls.i32 d16, d18, d17" + - + asm_text: "vmls.f32 d16, d18, d17" + - + asm_text: "vmls.i8 q9, q8, q10" + - + asm_text: "vmls.i16 q9, q8, q10" + - + asm_text: "vmls.i32 q9, q8, q10" + - + asm_text: "vmls.f32 q9, q8, q10" + - + asm_text: "vmls.i16 q4, q12, d6[2]" + - + asm_text: "vmlsl.s8 q8, d19, d18" + - + asm_text: "vmlsl.s16 q8, d19, d18" + - + asm_text: "vmlsl.s32 q8, d19, d18" + - + asm_text: "vmlsl.u8 q8, d19, d18" + - + asm_text: "vmlsl.u16 q8, d19, d18" + - + asm_text: "vmlsl.u32 q8, d19, d18" + - + asm_text: "vqdmlsl.s16 q8, d19, d18" + - + asm_text: "vqdmlsl.s32 q8, d19, d18" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-mul-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-mul-encoding.s.yaml new file mode 100644 index 0000000..9d31fcd --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-mul-encoding.s.yaml @@ -0,0 +1,150 @@ +test_cases: + - + input: + bytes: [ 0xb1, 0x09, 0x40, 0xf2, 0xb1, 0x09, 0x50, 0xf2, 0xb1, 0x09, 0x60, 0xf2, 0xb1, 0x0d, 0x40, 0xf3, 0xf2, 0x09, 0x40, 0xf2, 0xf2, 0x09, 0x50, 0xf2, 0xf2, 0x09, 0x60, 0xf2, 0xf2, 0x0d, 0x40, 0xf3, 0xb1, 0x09, 0x40, 0xf3, 0xf2, 0x09, 0x40, 0xf3, 0x68, 0x28, 0xd8, 0xf2, 0xb1, 0x09, 0x40, 0xf2, 0xb1, 0x09, 0x50, 0xf2, 0xb1, 0x09, 0x60, 0xf2, 0xb1, 0x0d, 0x40, 0xf3, 0xf2, 0x09, 0x40, 0xf2, 0xf2, 0x09, 0x50, 0xf2, 0xf2, 0x09, 0x60, 0xf2, 0xf2, 0x0d, 0x40, 0xf3, 0xb1, 0x09, 0x40, 0xf3, 0xf2, 0x09, 0x40, 0xf3, 0xa1, 0x0b, 0x50, 0xf2, 0xa1, 0x0b, 0x60, 0xf2, 0xe2, 0x0b, 0x50, 0xf2, 0xe2, 0x0b, 0x60, 0xf2, 0xa1, 0x0b, 0x50, 0xf2, 0xa1, 0x0b, 0x60, 0xf2, 0xe2, 0x0b, 0x50, 0xf2, 0xe2, 0x0b, 0x60, 0xf2, 0x43, 0xbc, 0x92, 0xf2, 0xa1, 0x0b, 0x50, 0xf3, 0xa1, 0x0b, 0x60, 0xf3, 0xe2, 0x0b, 0x50, 0xf3, 0xe2, 0x0b, 0x60, 0xf3, 0xa1, 0x0c, 0xc0, 0xf2, 0xa1, 0x0c, 0xd0, 0xf2, 0xa1, 0x0c, 0xe0, 0xf2, 0xa1, 0x0c, 0xc0, 0xf3, 0xa1, 0x0c, 0xd0, 0xf3, 0xa1, 0x0c, 0xe0, 0xf3, 0xa1, 0x0e, 0xc0, 0xf2, 0xa1, 0x0d, 0xd0, 0xf2, 0xa1, 0x0d, 0xe0, 0xf2, 0x64, 0x08, 0x90, 0xf2, 0x6f, 0x18, 0x91, 0xf2, 0x49, 0x28, 0x92, 0xf2, 0x42, 0x38, 0xa3, 0xf2, 0x63, 0x48, 0xa4, 0xf2, 0x44, 0x58, 0xa5, 0xf2, 0x65, 0x69, 0xa6, 0xf2, 0x64, 0x08, 0x90, 0xf3, 0x6f, 0x28, 0x92, 0xf3, 0x49, 0x48, 0x94, 0xf3, 0x42, 0x68, 0xa6, 0xf3, 0x63, 0x88, 0xa8, 0xf3, 0x44, 0xa8, 0xaa, 0xf3, 0x65, 0xc9, 0xac, 0xf3, 0x64, 0x98, 0x90, 0xf2, 0x6f, 0x88, 0x91, 0xf2, 0x49, 0x78, 0x92, 0xf2, 0x42, 0x68, 0xa3, 0xf2, 0x63, 0x58, 0xa4, 0xf2, 0x44, 0x48, 0xa5, 0xf2, 0x65, 0x39, 0xa6, 0xf2, 0x64, 0x28, 0xd0, 0xf3, 0x6f, 0x08, 0xd2, 0xf3, 0x49, 0xe8, 0x94, 0xf3, 0x42, 0xc8, 0xa6, 0xf3, 0x63, 0xa8, 0xa8, 0xf3, 0x44, 0x88, 0xaa, 0xf3, 0x65, 0x69, 0xac, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmul.i8 d16, d16, d17" + - + asm_text: "vmul.i16 d16, d16, d17" + - + asm_text: "vmul.i32 d16, d16, d17" + - + asm_text: "vmul.f32 d16, d16, d17" + - + asm_text: "vmul.i8 q8, q8, q9" + - + asm_text: "vmul.i16 q8, q8, q9" + - + asm_text: "vmul.i32 q8, q8, q9" + - + asm_text: "vmul.f32 q8, q8, q9" + - + asm_text: "vmul.p8 d16, d16, d17" + - + asm_text: "vmul.p8 q8, q8, q9" + - + asm_text: "vmul.i16 d18, d8, d0[3]" + - + asm_text: "vmul.i8 d16, d16, d17" + - + asm_text: "vmul.i16 d16, d16, d17" + - + asm_text: "vmul.i32 d16, d16, d17" + - + asm_text: "vmul.f32 d16, d16, d17" + - + asm_text: "vmul.i8 q8, q8, q9" + - + asm_text: "vmul.i16 q8, q8, q9" + - + asm_text: "vmul.i32 q8, q8, q9" + - + asm_text: "vmul.f32 q8, q8, q9" + - + asm_text: "vmul.p8 d16, d16, d17" + - + asm_text: "vmul.p8 q8, q8, q9" + - + asm_text: "vqdmulh.s16 d16, d16, d17" + - + asm_text: "vqdmulh.s32 d16, d16, d17" + - + asm_text: "vqdmulh.s16 q8, q8, q9" + - + asm_text: "vqdmulh.s32 q8, q8, q9" + - + asm_text: "vqdmulh.s16 d16, d16, d17" + - + asm_text: "vqdmulh.s32 d16, d16, d17" + - + asm_text: "vqdmulh.s16 q8, q8, q9" + - + asm_text: "vqdmulh.s32 q8, q8, q9" + - + asm_text: "vqdmulh.s16 d11, d2, d3[0]" + - + asm_text: "vqrdmulh.s16 d16, d16, d17" + - + asm_text: "vqrdmulh.s32 d16, d16, d17" + - + asm_text: "vqrdmulh.s16 q8, q8, q9" + - + asm_text: "vqrdmulh.s32 q8, q8, q9" + - + asm_text: "vmull.s8 q8, d16, d17" + - + asm_text: "vmull.s16 q8, d16, d17" + - + asm_text: "vmull.s32 q8, d16, d17" + - + asm_text: "vmull.u8 q8, d16, d17" + - + asm_text: "vmull.u16 q8, d16, d17" + - + asm_text: "vmull.u32 q8, d16, d17" + - + asm_text: "vmull.p8 q8, d16, d17" + - + asm_text: "vqdmull.s16 q8, d16, d17" + - + asm_text: "vqdmull.s32 q8, d16, d17" + - + asm_text: "vmul.i16 d0, d0, d4[2]" + - + asm_text: "vmul.i16 d1, d1, d7[3]" + - + asm_text: "vmul.i16 d2, d2, d1[1]" + - + asm_text: "vmul.i32 d3, d3, d2[0]" + - + asm_text: "vmul.i32 d4, d4, d3[1]" + - + asm_text: "vmul.i32 d5, d5, d4[0]" + - + asm_text: "vmul.f32 d6, d6, d5[1]" + - + asm_text: "vmul.i16 q0, q0, d4[2]" + - + asm_text: "vmul.i16 q1, q1, d7[3]" + - + asm_text: "vmul.i16 q2, q2, d1[1]" + - + asm_text: "vmul.i32 q3, q3, d2[0]" + - + asm_text: "vmul.i32 q4, q4, d3[1]" + - + asm_text: "vmul.i32 q5, q5, d4[0]" + - + asm_text: "vmul.f32 q6, q6, d5[1]" + - + asm_text: "vmul.i16 d9, d0, d4[2]" + - + asm_text: "vmul.i16 d8, d1, d7[3]" + - + asm_text: "vmul.i16 d7, d2, d1[1]" + - + asm_text: "vmul.i32 d6, d3, d2[0]" + - + asm_text: "vmul.i32 d5, d4, d3[1]" + - + asm_text: "vmul.i32 d4, d5, d4[0]" + - + asm_text: "vmul.f32 d3, d6, d5[1]" + - + asm_text: "vmul.i16 q9, q0, d4[2]" + - + asm_text: "vmul.i16 q8, q1, d7[3]" + - + asm_text: "vmul.i16 q7, q2, d1[1]" + - + asm_text: "vmul.i32 q6, q3, d2[0]" + - + asm_text: "vmul.i32 q5, q4, d3[1]" + - + asm_text: "vmul.i32 q4, q5, d4[0]" + - + asm_text: "vmul.f32 q3, q6, d5[1]" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-neg-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-neg-encoding.s.yaml new file mode 100644 index 0000000..c80c070 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-neg-encoding.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x03, 0xf1, 0xf3, 0xa0, 0x03, 0xf5, 0xf3, 0xa0, 0x03, 0xf9, 0xf3, 0xa0, 0x07, 0xf9, 0xf3, 0xe0, 0x03, 0xf1, 0xf3, 0xe0, 0x03, 0xf5, 0xf3, 0xe0, 0x03, 0xf9, 0xf3, 0xe0, 0x07, 0xf9, 0xf3, 0xa0, 0x07, 0xf0, 0xf3, 0xa0, 0x07, 0xf4, 0xf3, 0xa0, 0x07, 0xf8, 0xf3, 0xe0, 0x07, 0xf0, 0xf3, 0xe0, 0x07, 0xf4, 0xf3, 0xe0, 0x07, 0xf8, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vneg.s8 d16, d16" + - + asm_text: "vneg.s16 d16, d16" + - + asm_text: "vneg.s32 d16, d16" + - + asm_text: "vneg.f32 d16, d16" + - + asm_text: "vneg.s8 q8, q8" + - + asm_text: "vneg.s16 q8, q8" + - + asm_text: "vneg.s32 q8, q8" + - + asm_text: "vneg.f32 q8, q8" + - + asm_text: "vqneg.s8 d16, d16" + - + asm_text: "vqneg.s16 d16, d16" + - + asm_text: "vqneg.s32 d16, d16" + - + asm_text: "vqneg.s8 q8, q8" + - + asm_text: "vqneg.s16 q8, q8" + - + asm_text: "vqneg.s32 q8, q8" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-pairwise-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-pairwise-encoding.s.yaml new file mode 100644 index 0000000..771b395 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-pairwise-encoding.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0xb0, 0x0b, 0x41, 0xf2, 0xb0, 0x0b, 0x51, 0xf2, 0xb0, 0x0b, 0x61, 0xf2, 0xa1, 0x0d, 0x40, 0xf3, 0xb0, 0x1b, 0x41, 0xf2, 0xb0, 0x1b, 0x51, 0xf2, 0xb0, 0x1b, 0x61, 0xf2, 0xa1, 0x0d, 0x40, 0xf3, 0x20, 0x02, 0xf0, 0xf3, 0x20, 0x02, 0xf4, 0xf3, 0x20, 0x02, 0xf8, 0xf3, 0xa0, 0x02, 0xf0, 0xf3, 0xa0, 0x02, 0xf4, 0xf3, 0xa0, 0x02, 0xf8, 0xf3, 0x60, 0x02, 0xf0, 0xf3, 0x60, 0x02, 0xf4, 0xf3, 0x60, 0x02, 0xf8, 0xf3, 0xe0, 0x02, 0xf0, 0xf3, 0xe0, 0x02, 0xf4, 0xf3, 0xe0, 0x02, 0xf8, 0xf3, 0x21, 0x06, 0xf0, 0xf3, 0x21, 0x06, 0xf4, 0xf3, 0x21, 0x06, 0xf8, 0xf3, 0xa1, 0x06, 0xf0, 0xf3, 0xa1, 0x06, 0xf4, 0xf3, 0xa1, 0x06, 0xf8, 0xf3, 0x60, 0x26, 0xf0, 0xf3, 0x60, 0x26, 0xf4, 0xf3, 0x60, 0x26, 0xf8, 0xf3, 0xe0, 0x26, 0xf0, 0xf3, 0xe0, 0x26, 0xf4, 0xf3, 0xe0, 0x26, 0xf8, 0xf3, 0xb1, 0x0a, 0x40, 0xf2, 0xb1, 0x0a, 0x50, 0xf2, 0xb1, 0x0a, 0x60, 0xf2, 0xb1, 0x0a, 0x40, 0xf3, 0xb1, 0x0a, 0x50, 0xf3, 0xb1, 0x0a, 0x60, 0xf3, 0xa1, 0x0f, 0x60, 0xf3, 0xa1, 0x0a, 0x40, 0xf2, 0xa1, 0x0a, 0x50, 0xf2, 0xa1, 0x0a, 0x60, 0xf2, 0xa1, 0x0a, 0x40, 0xf3, 0xa1, 0x0a, 0x50, 0xf3, 0xa1, 0x0a, 0x60, 0xf3, 0xa1, 0x0f, 0x40, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vpadd.i8 d16, d17, d16" + - + asm_text: "vpadd.i16 d16, d17, d16" + - + asm_text: "vpadd.i32 d16, d17, d16" + - + asm_text: "vpadd.f32 d16, d16, d17" + - + asm_text: "vpadd.i8 d17, d17, d16" + - + asm_text: "vpadd.i16 d17, d17, d16" + - + asm_text: "vpadd.i32 d17, d17, d16" + - + asm_text: "vpadd.f32 d16, d16, d17" + - + asm_text: "vpaddl.s8 d16, d16" + - + asm_text: "vpaddl.s16 d16, d16" + - + asm_text: "vpaddl.s32 d16, d16" + - + asm_text: "vpaddl.u8 d16, d16" + - + asm_text: "vpaddl.u16 d16, d16" + - + asm_text: "vpaddl.u32 d16, d16" + - + asm_text: "vpaddl.s8 q8, q8" + - + asm_text: "vpaddl.s16 q8, q8" + - + asm_text: "vpaddl.s32 q8, q8" + - + asm_text: "vpaddl.u8 q8, q8" + - + asm_text: "vpaddl.u16 q8, q8" + - + asm_text: "vpaddl.u32 q8, q8" + - + asm_text: "vpadal.s8 d16, d17" + - + asm_text: "vpadal.s16 d16, d17" + - + asm_text: "vpadal.s32 d16, d17" + - + asm_text: "vpadal.u8 d16, d17" + - + asm_text: "vpadal.u16 d16, d17" + - + asm_text: "vpadal.u32 d16, d17" + - + asm_text: "vpadal.s8 q9, q8" + - + asm_text: "vpadal.s16 q9, q8" + - + asm_text: "vpadal.s32 q9, q8" + - + asm_text: "vpadal.u8 q9, q8" + - + asm_text: "vpadal.u16 q9, q8" + - + asm_text: "vpadal.u32 q9, q8" + - + asm_text: "vpmin.s8 d16, d16, d17" + - + asm_text: "vpmin.s16 d16, d16, d17" + - + asm_text: "vpmin.s32 d16, d16, d17" + - + asm_text: "vpmin.u8 d16, d16, d17" + - + asm_text: "vpmin.u16 d16, d16, d17" + - + asm_text: "vpmin.u32 d16, d16, d17" + - + asm_text: "vpmin.f32 d16, d16, d17" + - + asm_text: "vpmax.s8 d16, d16, d17" + - + asm_text: "vpmax.s16 d16, d16, d17" + - + asm_text: "vpmax.s32 d16, d16, d17" + - + asm_text: "vpmax.u8 d16, d16, d17" + - + asm_text: "vpmax.u16 d16, d16, d17" + - + asm_text: "vpmax.u32 d16, d16, d17" + - + asm_text: "vpmax.f32 d16, d16, d17" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-reciprocal-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-reciprocal-encoding.s.yaml new file mode 100644 index 0000000..d83492b --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-reciprocal-encoding.s.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x04, 0xfb, 0xf3, 0x60, 0x04, 0xfb, 0xf3, 0x20, 0x05, 0xfb, 0xf3, 0x60, 0x05, 0xfb, 0xf3, 0xb1, 0x0f, 0x40, 0xf2, 0xf2, 0x0f, 0x40, 0xf2, 0xa0, 0x04, 0xfb, 0xf3, 0xe0, 0x04, 0xfb, 0xf3, 0xa0, 0x05, 0xfb, 0xf3, 0xe0, 0x05, 0xfb, 0xf3, 0xb1, 0x0f, 0x60, 0xf2, 0xf2, 0x0f, 0x60, 0xf2 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vrecpe.u32 d16, d16" + - + asm_text: "vrecpe.u32 q8, q8" + - + asm_text: "vrecpe.f32 d16, d16" + - + asm_text: "vrecpe.f32 q8, q8" + - + asm_text: "vrecps.f32 d16, d16, d17" + - + asm_text: "vrecps.f32 q8, q8, q9" + - + asm_text: "vrsqrte.u32 d16, d16" + - + asm_text: "vrsqrte.u32 q8, q8" + - + asm_text: "vrsqrte.f32 d16, d16" + - + asm_text: "vrsqrte.f32 q8, q8" + - + asm_text: "vrsqrts.f32 d16, d16, d17" + - + asm_text: "vrsqrts.f32 q8, q8, q9" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-reverse-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-reverse-encoding.s.yaml new file mode 100644 index 0000000..4493caa --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-reverse-encoding.s.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x00, 0xf0, 0xf3, 0x20, 0x00, 0xf4, 0xf3, 0x20, 0x00, 0xf8, 0xf3, 0x60, 0x00, 0xf0, 0xf3, 0x60, 0x00, 0xf4, 0xf3, 0x60, 0x00, 0xf8, 0xf3, 0xa0, 0x00, 0xf0, 0xf3, 0xa0, 0x00, 0xf4, 0xf3, 0xe0, 0x00, 0xf0, 0xf3, 0xe0, 0x00, 0xf4, 0xf3, 0x20, 0x01, 0xf0, 0xf3, 0x60, 0x01, 0xf0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vrev64.8 d16, d16" + - + asm_text: "vrev64.16 d16, d16" + - + asm_text: "vrev64.32 d16, d16" + - + asm_text: "vrev64.8 q8, q8" + - + asm_text: "vrev64.16 q8, q8" + - + asm_text: "vrev64.32 q8, q8" + - + asm_text: "vrev32.8 d16, d16" + - + asm_text: "vrev32.16 d16, d16" + - + asm_text: "vrev32.8 q8, q8" + - + asm_text: "vrev32.16 q8, q8" + - + asm_text: "vrev16.8 d16, d16" + - + asm_text: "vrev16.8 q8, q8" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-satshift-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-satshift-encoding.s.yaml new file mode 100644 index 0000000..36148b7 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-satshift-encoding.s.yaml @@ -0,0 +1,156 @@ +test_cases: + - + input: + bytes: [ 0xb0, 0x04, 0x41, 0xf2, 0xb0, 0x04, 0x51, 0xf2, 0xb0, 0x04, 0x61, 0xf2, 0xb0, 0x04, 0x71, 0xf2, 0xb0, 0x04, 0x41, 0xf3, 0xb0, 0x04, 0x51, 0xf3, 0xb0, 0x04, 0x61, 0xf3, 0xb0, 0x04, 0x71, 0xf3, 0xf0, 0x04, 0x42, 0xf2, 0xf0, 0x04, 0x52, 0xf2, 0xf0, 0x04, 0x62, 0xf2, 0xf0, 0x04, 0x72, 0xf2, 0xf0, 0x04, 0x42, 0xf3, 0xf0, 0x04, 0x52, 0xf3, 0xf0, 0x04, 0x62, 0xf3, 0xf0, 0x04, 0x72, 0xf3, 0x30, 0x07, 0xcf, 0xf2, 0x30, 0x07, 0xdf, 0xf2, 0x30, 0x07, 0xff, 0xf2, 0xb0, 0x07, 0xff, 0xf2, 0x30, 0x07, 0xcf, 0xf3, 0x30, 0x07, 0xdf, 0xf3, 0x30, 0x07, 0xff, 0xf3, 0xb0, 0x07, 0xff, 0xf3, 0x30, 0x06, 0xcf, 0xf3, 0x30, 0x06, 0xdf, 0xf3, 0x30, 0x06, 0xff, 0xf3, 0xb0, 0x06, 0xff, 0xf3, 0x70, 0x07, 0xcf, 0xf2, 0x70, 0x07, 0xdf, 0xf2, 0x70, 0x07, 0xff, 0xf2, 0xf0, 0x07, 0xff, 0xf2, 0x70, 0x07, 0xcf, 0xf3, 0x70, 0x07, 0xdf, 0xf3, 0x70, 0x07, 0xff, 0xf3, 0xf0, 0x07, 0xff, 0xf3, 0x70, 0x06, 0xcf, 0xf3, 0x70, 0x06, 0xdf, 0xf3, 0x70, 0x06, 0xff, 0xf3, 0xf0, 0x06, 0xff, 0xf3, 0xb0, 0x05, 0x41, 0xf2, 0xb0, 0x05, 0x51, 0xf2, 0xb0, 0x05, 0x61, 0xf2, 0xb0, 0x05, 0x71, 0xf2, 0xb0, 0x05, 0x41, 0xf3, 0xb0, 0x05, 0x51, 0xf3, 0xb0, 0x05, 0x61, 0xf3, 0xb0, 0x05, 0x71, 0xf3, 0xf0, 0x05, 0x42, 0xf2, 0xf0, 0x05, 0x52, 0xf2, 0xf0, 0x05, 0x62, 0xf2, 0xf0, 0x05, 0x72, 0xf2, 0xf0, 0x05, 0x42, 0xf3, 0xf0, 0x05, 0x52, 0xf3, 0xf0, 0x05, 0x62, 0xf3, 0xf0, 0x05, 0x72, 0xf3, 0x30, 0x09, 0xc8, 0xf2, 0x30, 0x09, 0xd0, 0xf2, 0x30, 0x09, 0xe0, 0xf2, 0x30, 0x09, 0xc8, 0xf3, 0x30, 0x09, 0xd0, 0xf3, 0x30, 0x09, 0xe0, 0xf3, 0x30, 0x08, 0xc8, 0xf3, 0x30, 0x08, 0xd0, 0xf3, 0x30, 0x08, 0xe0, 0xf3, 0x70, 0x09, 0xc8, 0xf2, 0x70, 0x09, 0xd0, 0xf2, 0x70, 0x09, 0xe0, 0xf2, 0x70, 0x09, 0xc8, 0xf3, 0x70, 0x09, 0xd0, 0xf3, 0x70, 0x09, 0xe0, 0xf3, 0x70, 0x08, 0xc8, 0xf3, 0x70, 0x08, 0xd0, 0xf3, 0x70, 0x08, 0xe0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vqshl.s8 d16, d16, d17" + - + asm_text: "vqshl.s16 d16, d16, d17" + - + asm_text: "vqshl.s32 d16, d16, d17" + - + asm_text: "vqshl.s64 d16, d16, d17" + - + asm_text: "vqshl.u8 d16, d16, d17" + - + asm_text: "vqshl.u16 d16, d16, d17" + - + asm_text: "vqshl.u32 d16, d16, d17" + - + asm_text: "vqshl.u64 d16, d16, d17" + - + asm_text: "vqshl.s8 q8, q8, q9" + - + asm_text: "vqshl.s16 q8, q8, q9" + - + asm_text: "vqshl.s32 q8, q8, q9" + - + asm_text: "vqshl.s64 q8, q8, q9" + - + asm_text: "vqshl.u8 q8, q8, q9" + - + asm_text: "vqshl.u16 q8, q8, q9" + - + asm_text: "vqshl.u32 q8, q8, q9" + - + asm_text: "vqshl.u64 q8, q8, q9" + - + asm_text: "vqshl.s8 d16, d16, #7" + - + asm_text: "vqshl.s16 d16, d16, #0xf" + - + asm_text: "vqshl.s32 d16, d16, #0x1f" + - + asm_text: "vqshl.s64 d16, d16, #0x3f" + - + asm_text: "vqshl.u8 d16, d16, #7" + - + asm_text: "vqshl.u16 d16, d16, #0xf" + - + asm_text: "vqshl.u32 d16, d16, #0x1f" + - + asm_text: "vqshl.u64 d16, d16, #0x3f" + - + asm_text: "vqshlu.s8 d16, d16, #7" + - + asm_text: "vqshlu.s16 d16, d16, #0xf" + - + asm_text: "vqshlu.s32 d16, d16, #0x1f" + - + asm_text: "vqshlu.s64 d16, d16, #0x3f" + - + asm_text: "vqshl.s8 q8, q8, #7" + - + asm_text: "vqshl.s16 q8, q8, #0xf" + - + asm_text: "vqshl.s32 q8, q8, #0x1f" + - + asm_text: "vqshl.s64 q8, q8, #0x3f" + - + asm_text: "vqshl.u8 q8, q8, #7" + - + asm_text: "vqshl.u16 q8, q8, #0xf" + - + asm_text: "vqshl.u32 q8, q8, #0x1f" + - + asm_text: "vqshl.u64 q8, q8, #0x3f" + - + asm_text: "vqshlu.s8 q8, q8, #7" + - + asm_text: "vqshlu.s16 q8, q8, #0xf" + - + asm_text: "vqshlu.s32 q8, q8, #0x1f" + - + asm_text: "vqshlu.s64 q8, q8, #0x3f" + - + asm_text: "vqrshl.s8 d16, d16, d17" + - + asm_text: "vqrshl.s16 d16, d16, d17" + - + asm_text: "vqrshl.s32 d16, d16, d17" + - + asm_text: "vqrshl.s64 d16, d16, d17" + - + asm_text: "vqrshl.u8 d16, d16, d17" + - + asm_text: "vqrshl.u16 d16, d16, d17" + - + asm_text: "vqrshl.u32 d16, d16, d17" + - + asm_text: "vqrshl.u64 d16, d16, d17" + - + asm_text: "vqrshl.s8 q8, q8, q9" + - + asm_text: "vqrshl.s16 q8, q8, q9" + - + asm_text: "vqrshl.s32 q8, q8, q9" + - + asm_text: "vqrshl.s64 q8, q8, q9" + - + asm_text: "vqrshl.u8 q8, q8, q9" + - + asm_text: "vqrshl.u16 q8, q8, q9" + - + asm_text: "vqrshl.u32 q8, q8, q9" + - + asm_text: "vqrshl.u64 q8, q8, q9" + - + asm_text: "vqshrn.s16 d16, q8, #8" + - + asm_text: "vqshrn.s32 d16, q8, #0x10" + - + asm_text: "vqshrn.s64 d16, q8, #0x20" + - + asm_text: "vqshrn.u16 d16, q8, #8" + - + asm_text: "vqshrn.u32 d16, q8, #0x10" + - + asm_text: "vqshrn.u64 d16, q8, #0x20" + - + asm_text: "vqshrun.s16 d16, q8, #8" + - + asm_text: "vqshrun.s32 d16, q8, #0x10" + - + asm_text: "vqshrun.s64 d16, q8, #0x20" + - + asm_text: "vqrshrn.s16 d16, q8, #8" + - + asm_text: "vqrshrn.s32 d16, q8, #0x10" + - + asm_text: "vqrshrn.s64 d16, q8, #0x20" + - + asm_text: "vqrshrn.u16 d16, q8, #8" + - + asm_text: "vqrshrn.u32 d16, q8, #0x10" + - + asm_text: "vqrshrn.u64 d16, q8, #0x20" + - + asm_text: "vqrshrun.s16 d16, q8, #8" + - + asm_text: "vqrshrun.s32 d16, q8, #0x10" + - + asm_text: "vqrshrun.s64 d16, q8, #0x20" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-shift-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-shift-encoding.s.yaml new file mode 100644 index 0000000..4296dbd --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-shift-encoding.s.yaml @@ -0,0 +1,482 @@ +test_cases: + - + input: + bytes: [ 0xa1, 0x04, 0x40, 0xf3, 0xa1, 0x04, 0x50, 0xf3, 0xa1, 0x04, 0x60, 0xf3, 0xa1, 0x04, 0x70, 0xf3, 0x30, 0x05, 0xcf, 0xf2, 0x30, 0x05, 0xdf, 0xf2, 0x30, 0x05, 0xff, 0xf2, 0xb0, 0x05, 0xff, 0xf2, 0xe2, 0x04, 0x40, 0xf3, 0xe2, 0x04, 0x50, 0xf3, 0xe2, 0x04, 0x60, 0xf3, 0xe2, 0x04, 0x70, 0xf3, 0x70, 0x05, 0xcf, 0xf2, 0x70, 0x05, 0xdf, 0xf2, 0x70, 0x05, 0xff, 0xf2, 0xf0, 0x05, 0xff, 0xf2, 0x30, 0x00, 0xc9, 0xf3, 0x30, 0x00, 0xd1, 0xf3, 0x30, 0x00, 0xe1, 0xf3, 0xb0, 0x00, 0xc1, 0xf3, 0x70, 0x00, 0xc9, 0xf3, 0x70, 0x00, 0xd1, 0xf3, 0x70, 0x00, 0xe1, 0xf3, 0xf0, 0x00, 0xc1, 0xf3, 0x30, 0x00, 0xc9, 0xf2, 0x30, 0x00, 0xd1, 0xf2, 0x30, 0x00, 0xe1, 0xf2, 0xb0, 0x00, 0xc1, 0xf2, 0x70, 0x00, 0xc9, 0xf2, 0x70, 0x00, 0xd1, 0xf2, 0x70, 0x00, 0xe1, 0xf2, 0xf0, 0x00, 0xc1, 0xf2, 0x30, 0x00, 0xc9, 0xf3, 0x30, 0x00, 0xd1, 0xf3, 0x30, 0x00, 0xe1, 0xf3, 0xb0, 0x00, 0xc1, 0xf3, 0x70, 0x00, 0xc9, 0xf3, 0x70, 0x00, 0xd1, 0xf3, 0x70, 0x00, 0xe1, 0xf3, 0xf0, 0x00, 0xc1, 0xf3, 0x30, 0x00, 0xc9, 0xf2, 0x30, 0x00, 0xd1, 0xf2, 0x30, 0x00, 0xe1, 0xf2, 0xb0, 0x00, 0xc1, 0xf2, 0x70, 0x00, 0xc9, 0xf2, 0x70, 0x00, 0xd1, 0xf2, 0x70, 0x00, 0xe1, 0xf2, 0xf0, 0x00, 0xc1, 0xf2, 0x16, 0x01, 0xc9, 0xf2, 0x32, 0xa1, 0xd1, 0xf2, 0x1a, 0xb1, 0xa1, 0xf2, 0xb3, 0xc1, 0x81, 0xf2, 0x70, 0x21, 0x89, 0xf2, 0x5e, 0x41, 0x91, 0xf2, 0x5c, 0x61, 0xa1, 0xf2, 0xda, 0x81, 0x81, 0xf2, 0x30, 0x01, 0xc9, 0xf2, 0x1f, 0xf1, 0x91, 0xf2, 0x1e, 0xe1, 0xa1, 0xf2, 0x9d, 0xd1, 0x81, 0xf2, 0x58, 0x81, 0x89, 0xf2, 0x5a, 0xa1, 0x91, 0xf2, 0x5c, 0xc1, 0xa1, 0xf2, 0xde, 0xe1, 0x81, 0xf2, 0x16, 0x01, 0xc9, 0xf3, 0x32, 0xa1, 0xd1, 0xf3, 0x1a, 0xb1, 0xa1, 0xf3, 0xb3, 0xc1, 0x81, 0xf3, 0x70, 0x21, 0x89, 0xf3, 0x5e, 0x41, 0x91, 0xf3, 0x5c, 0x61, 0xa1, 0xf3, 0xda, 0x81, 0x81, 0xf3, 0x30, 0x01, 0xc9, 0xf3, 0x1f, 0xf1, 0x91, 0xf3, 0x1e, 0xe1, 0xa1, 0xf3, 0x9d, 0xd1, 0x81, 0xf3, 0x58, 0x81, 0x89, 0xf3, 0x5a, 0xa1, 0x91, 0xf3, 0x5c, 0xc1, 0xa1, 0xf3, 0xde, 0xe1, 0x81, 0xf3, 0x16, 0x04, 0xc9, 0xf3, 0x32, 0xa4, 0xd1, 0xf3, 0x1a, 0xb4, 0xa1, 0xf3, 0xb3, 0xc4, 0x81, 0xf3, 0x70, 0x24, 0x89, 0xf3, 0x5e, 0x44, 0x91, 0xf3, 0x5c, 0x64, 0xa1, 0xf3, 0xda, 0x84, 0x81, 0xf3, 0x30, 0x04, 0xc9, 0xf3, 0x1f, 0xf4, 0x91, 0xf3, 0x1e, 0xe4, 0xa1, 0xf3, 0x9d, 0xd4, 0x81, 0xf3, 0x58, 0x84, 0x89, 0xf3, 0x5a, 0xa4, 0x91, 0xf3, 0x5c, 0xc4, 0xa1, 0xf3, 0xde, 0xe4, 0x81, 0xf3, 0x16, 0x05, 0xcf, 0xf3, 0x32, 0xa5, 0xdf, 0xf3, 0x1a, 0xb5, 0xbf, 0xf3, 0xb3, 0xc5, 0xbf, 0xf3, 0x70, 0x25, 0x8f, 0xf3, 0x5e, 0x45, 0x9f, 0xf3, 0x5c, 0x65, 0xbf, 0xf3, 0xda, 0x85, 0xbf, 0xf3, 0x30, 0x05, 0xcf, 0xf3, 0x1f, 0xf5, 0x9f, 0xf3, 0x1e, 0xe5, 0xbf, 0xf3, 0x9d, 0xd5, 0xbf, 0xf3, 0x58, 0x85, 0x8f, 0xf3, 0x5a, 0xa5, 0x9f, 0xf3, 0x5c, 0xc5, 0xbf, 0xf3, 0xde, 0xe5, 0xbf, 0xf3, 0x30, 0x0a, 0xcf, 0xf2, 0x30, 0x0a, 0xdf, 0xf2, 0x30, 0x0a, 0xff, 0xf2, 0x30, 0x0a, 0xcf, 0xf3, 0x30, 0x0a, 0xdf, 0xf3, 0x30, 0x0a, 0xff, 0xf3, 0x20, 0x03, 0xf2, 0xf3, 0x20, 0x03, 0xf6, 0xf3, 0x20, 0x03, 0xfa, 0xf3, 0x30, 0x08, 0xc8, 0xf2, 0x30, 0x08, 0xd0, 0xf2, 0x30, 0x08, 0xe0, 0xf2, 0xa1, 0x05, 0x40, 0xf2, 0xa1, 0x05, 0x50, 0xf2, 0xa1, 0x05, 0x60, 0xf2, 0xa1, 0x05, 0x70, 0xf2, 0xa1, 0x05, 0x40, 0xf3, 0xa1, 0x05, 0x50, 0xf3, 0xa1, 0x05, 0x60, 0xf3, 0xa1, 0x05, 0x70, 0xf3, 0xe2, 0x05, 0x40, 0xf2, 0xe2, 0x05, 0x50, 0xf2, 0xe2, 0x05, 0x60, 0xf2, 0xe2, 0x05, 0x70, 0xf2, 0xe2, 0x05, 0x40, 0xf3, 0xe2, 0x05, 0x50, 0xf3, 0xe2, 0x05, 0x60, 0xf3, 0xe2, 0x05, 0x70, 0xf3, 0x30, 0x02, 0xc8, 0xf2, 0x30, 0x02, 0xd0, 0xf2, 0x30, 0x02, 0xe0, 0xf2, 0xb0, 0x02, 0xc0, 0xf2, 0x30, 0x02, 0xc8, 0xf3, 0x30, 0x02, 0xd0, 0xf3, 0x30, 0x02, 0xe0, 0xf3, 0xb0, 0x02, 0xc0, 0xf3, 0x70, 0x02, 0xc8, 0xf2, 0x70, 0x02, 0xd0, 0xf2, 0x70, 0x02, 0xe0, 0xf2, 0xf0, 0x02, 0xc0, 0xf2, 0x70, 0x02, 0xc8, 0xf3, 0x70, 0x02, 0xd0, 0xf3, 0x70, 0x02, 0xe0, 0xf3, 0xf0, 0x02, 0xc0, 0xf3, 0x70, 0x08, 0xc8, 0xf2, 0x70, 0x08, 0xd0, 0xf2, 0x70, 0x08, 0xe0, 0xf2, 0x70, 0x09, 0xcc, 0xf2, 0x70, 0x09, 0xd3, 0xf2, 0x70, 0x09, 0xf3, 0xf2, 0x70, 0x09, 0xcc, 0xf3, 0x70, 0x09, 0xd3, 0xf3, 0x70, 0x09, 0xf3, 0xf3, 0x48, 0x84, 0x0a, 0xf2, 0x48, 0x84, 0x1a, 0xf2, 0x48, 0x84, 0x2a, 0xf2, 0x48, 0x84, 0x3a, 0xf2, 0x48, 0x84, 0x0a, 0xf3, 0x48, 0x84, 0x1a, 0xf3, 0x48, 0x84, 0x2a, 0xf3, 0x48, 0x84, 0x3a, 0xf3, 0x04, 0x44, 0x05, 0xf2, 0x04, 0x44, 0x15, 0xf2, 0x04, 0x44, 0x25, 0xf2, 0x04, 0x44, 0x35, 0xf2, 0x04, 0x44, 0x05, 0xf3, 0x04, 0x44, 0x15, 0xf3, 0x04, 0x44, 0x25, 0xf3, 0x04, 0x44, 0x35, 0xf3, 0x58, 0x85, 0x8a, 0xf2, 0x58, 0x85, 0x9e, 0xf2, 0x58, 0x85, 0xbb, 0xf2, 0xd8, 0x85, 0xa3, 0xf2, 0x14, 0x45, 0x8e, 0xf2, 0x14, 0x45, 0x9a, 0xf2, 0x14, 0x45, 0xb1, 0xf2, 0x94, 0x45, 0xab, 0xf2, 0x0b, 0xb5, 0x04, 0xf2, 0x0c, 0xc5, 0x15, 0xf2, 0x0d, 0xd5, 0x26, 0xf2, 0x0e, 0xe5, 0x37, 0xf2, 0x0f, 0xf5, 0x08, 0xf3, 0x20, 0x05, 0x59, 0xf3, 0x21, 0x15, 0x6a, 0xf3, 0x22, 0x25, 0x7b, 0xf3, 0xc2, 0x25, 0x00, 0xf2, 0xc4, 0x45, 0x1e, 0xf2, 0xc6, 0x65, 0x2c, 0xf2, 0xc8, 0x85, 0x3a, 0xf2, 0xca, 0xa5, 0x08, 0xf3, 0xcc, 0xc5, 0x16, 0xf3, 0xce, 0xe5, 0x24, 0xf3, 0xe0, 0x05, 0x72, 0xf3, 0x1f, 0xf0, 0x88, 0xf2, 0x1c, 0xc0, 0x90, 0xf2, 0x1d, 0xd0, 0xa0, 0xf2, 0x9e, 0xe0, 0x80, 0xf2, 0x30, 0x00, 0xc8, 0xf3, 0x31, 0x10, 0xd0, 0xf3, 0x16, 0x60, 0xa0, 0xf3, 0x9a, 0xa0, 0x80, 0xf3, 0x52, 0x20, 0x88, 0xf2, 0x54, 0x40, 0x90, 0xf2, 0x56, 0x60, 0xa0, 0xf2, 0xd8, 0x80, 0x80, 0xf2, 0x5a, 0xa0, 0x88, 0xf3, 0x5c, 0xc0, 0x90, 0xf3, 0x5e, 0xe0, 0xa0, 0xf3, 0xf0, 0x00, 0xc0, 0xf3, 0x1f, 0xf2, 0x88, 0xf2, 0x1c, 0xc2, 0x90, 0xf2, 0x1d, 0xd2, 0xa0, 0xf2, 0x9e, 0xe2, 0x80, 0xf2, 0x30, 0x02, 0xc8, 0xf3, 0x31, 0x12, 0xd0, 0xf3, 0x16, 0x62, 0xa0, 0xf3, 0x9a, 0xa2, 0x80, 0xf3, 0x52, 0x22, 0x88, 0xf2, 0x54, 0x42, 0x90, 0xf2, 0x56, 0x62, 0xa0, 0xf2, 0xd8, 0x82, 0x80, 0xf2, 0x5a, 0xa2, 0x88, 0xf3, 0x5c, 0xc2, 0x90, 0xf3, 0x5e, 0xe2, 0xa0, 0xf3, 0xf0, 0x02, 0xc0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vshl.u8 d16, d17, d16" + - + asm_text: "vshl.u16 d16, d17, d16" + - + asm_text: "vshl.u32 d16, d17, d16" + - + asm_text: "vshl.u64 d16, d17, d16" + - + asm_text: "vshl.i8 d16, d16, #7" + - + asm_text: "vshl.i16 d16, d16, #0xf" + - + asm_text: "vshl.i32 d16, d16, #0x1f" + - + asm_text: "vshl.i64 d16, d16, #0x3f" + - + asm_text: "vshl.u8 q8, q9, q8" + - + asm_text: "vshl.u16 q8, q9, q8" + - + asm_text: "vshl.u32 q8, q9, q8" + - + asm_text: "vshl.u64 q8, q9, q8" + - + asm_text: "vshl.i8 q8, q8, #7" + - + asm_text: "vshl.i16 q8, q8, #0xf" + - + asm_text: "vshl.i32 q8, q8, #0x1f" + - + asm_text: "vshl.i64 q8, q8, #0x3f" + - + asm_text: "vshr.u8 d16, d16, #7" + - + asm_text: "vshr.u16 d16, d16, #0xf" + - + asm_text: "vshr.u32 d16, d16, #0x1f" + - + asm_text: "vshr.u64 d16, d16, #0x3f" + - + asm_text: "vshr.u8 q8, q8, #7" + - + asm_text: "vshr.u16 q8, q8, #0xf" + - + asm_text: "vshr.u32 q8, q8, #0x1f" + - + asm_text: "vshr.u64 q8, q8, #0x3f" + - + asm_text: "vshr.s8 d16, d16, #7" + - + asm_text: "vshr.s16 d16, d16, #0xf" + - + asm_text: "vshr.s32 d16, d16, #0x1f" + - + asm_text: "vshr.s64 d16, d16, #0x3f" + - + asm_text: "vshr.s8 q8, q8, #7" + - + asm_text: "vshr.s16 q8, q8, #0xf" + - + asm_text: "vshr.s32 q8, q8, #0x1f" + - + asm_text: "vshr.s64 q8, q8, #0x3f" + - + asm_text: "vshr.u8 d16, d16, #7" + - + asm_text: "vshr.u16 d16, d16, #0xf" + - + asm_text: "vshr.u32 d16, d16, #0x1f" + - + asm_text: "vshr.u64 d16, d16, #0x3f" + - + asm_text: "vshr.u8 q8, q8, #7" + - + asm_text: "vshr.u16 q8, q8, #0xf" + - + asm_text: "vshr.u32 q8, q8, #0x1f" + - + asm_text: "vshr.u64 q8, q8, #0x3f" + - + asm_text: "vshr.s8 d16, d16, #7" + - + asm_text: "vshr.s16 d16, d16, #0xf" + - + asm_text: "vshr.s32 d16, d16, #0x1f" + - + asm_text: "vshr.s64 d16, d16, #0x3f" + - + asm_text: "vshr.s8 q8, q8, #7" + - + asm_text: "vshr.s16 q8, q8, #0xf" + - + asm_text: "vshr.s32 q8, q8, #0x1f" + - + asm_text: "vshr.s64 q8, q8, #0x3f" + - + asm_text: "vsra.s8 d16, d6, #7" + - + asm_text: "vsra.s16 d26, d18, #0xf" + - + asm_text: "vsra.s32 d11, d10, #0x1f" + - + asm_text: "vsra.s64 d12, d19, #0x3f" + - + asm_text: "vsra.s8 q1, q8, #7" + - + asm_text: "vsra.s16 q2, q7, #0xf" + - + asm_text: "vsra.s32 q3, q6, #0x1f" + - + asm_text: "vsra.s64 q4, q5, #0x3f" + - + asm_text: "vsra.s8 d16, d16, #7" + - + asm_text: "vsra.s16 d15, d15, #0xf" + - + asm_text: "vsra.s32 d14, d14, #0x1f" + - + asm_text: "vsra.s64 d13, d13, #0x3f" + - + asm_text: "vsra.s8 q4, q4, #7" + - + asm_text: "vsra.s16 q5, q5, #0xf" + - + asm_text: "vsra.s32 q6, q6, #0x1f" + - + asm_text: "vsra.s64 q7, q7, #0x3f" + - + asm_text: "vsra.u8 d16, d6, #7" + - + asm_text: "vsra.u16 d26, d18, #0xf" + - + asm_text: "vsra.u32 d11, d10, #0x1f" + - + asm_text: "vsra.u64 d12, d19, #0x3f" + - + asm_text: "vsra.u8 q1, q8, #7" + - + asm_text: "vsra.u16 q2, q7, #0xf" + - + asm_text: "vsra.u32 q3, q6, #0x1f" + - + asm_text: "vsra.u64 q4, q5, #0x3f" + - + asm_text: "vsra.u8 d16, d16, #7" + - + asm_text: "vsra.u16 d15, d15, #0xf" + - + asm_text: "vsra.u32 d14, d14, #0x1f" + - + asm_text: "vsra.u64 d13, d13, #0x3f" + - + asm_text: "vsra.u8 q4, q4, #7" + - + asm_text: "vsra.u16 q5, q5, #0xf" + - + asm_text: "vsra.u32 q6, q6, #0x1f" + - + asm_text: "vsra.u64 q7, q7, #0x3f" + - + asm_text: "vsri.8 d16, d6, #7" + - + asm_text: "vsri.16 d26, d18, #0xf" + - + asm_text: "vsri.32 d11, d10, #0x1f" + - + asm_text: "vsri.64 d12, d19, #0x3f" + - + asm_text: "vsri.8 q1, q8, #7" + - + asm_text: "vsri.16 q2, q7, #0xf" + - + asm_text: "vsri.32 q3, q6, #0x1f" + - + asm_text: "vsri.64 q4, q5, #0x3f" + - + asm_text: "vsri.8 d16, d16, #7" + - + asm_text: "vsri.16 d15, d15, #0xf" + - + asm_text: "vsri.32 d14, d14, #0x1f" + - + asm_text: "vsri.64 d13, d13, #0x3f" + - + asm_text: "vsri.8 q4, q4, #7" + - + asm_text: "vsri.16 q5, q5, #0xf" + - + asm_text: "vsri.32 q6, q6, #0x1f" + - + asm_text: "vsri.64 q7, q7, #0x3f" + - + asm_text: "vsli.8 d16, d6, #7" + - + asm_text: "vsli.16 d26, d18, #0xf" + - + asm_text: "vsli.32 d11, d10, #0x1f" + - + asm_text: "vsli.64 d12, d19, #0x3f" + - + asm_text: "vsli.8 q1, q8, #7" + - + asm_text: "vsli.16 q2, q7, #0xf" + - + asm_text: "vsli.32 q3, q6, #0x1f" + - + asm_text: "vsli.64 q4, q5, #0x3f" + - + asm_text: "vsli.8 d16, d16, #7" + - + asm_text: "vsli.16 d15, d15, #0xf" + - + asm_text: "vsli.32 d14, d14, #0x1f" + - + asm_text: "vsli.64 d13, d13, #0x3f" + - + asm_text: "vsli.8 q4, q4, #7" + - + asm_text: "vsli.16 q5, q5, #0xf" + - + asm_text: "vsli.32 q6, q6, #0x1f" + - + asm_text: "vsli.64 q7, q7, #0x3f" + - + asm_text: "vshll.s8 q8, d16, #7" + - + asm_text: "vshll.s16 q8, d16, #0xf" + - + asm_text: "vshll.s32 q8, d16, #0x1f" + - + asm_text: "vshll.u8 q8, d16, #7" + - + asm_text: "vshll.u16 q8, d16, #0xf" + - + asm_text: "vshll.u32 q8, d16, #0x1f" + - + asm_text: "vshll.i8 q8, d16, #8" + - + asm_text: "vshll.i16 q8, d16, #0x10" + - + asm_text: "vshll.i32 q8, d16, #0x20" + - + asm_text: "vshrn.i16 d16, q8, #8" + - + asm_text: "vshrn.i32 d16, q8, #0x10" + - + asm_text: "vshrn.i64 d16, q8, #0x20" + - + asm_text: "vrshl.s8 d16, d17, d16" + - + asm_text: "vrshl.s16 d16, d17, d16" + - + asm_text: "vrshl.s32 d16, d17, d16" + - + asm_text: "vrshl.s64 d16, d17, d16" + - + asm_text: "vrshl.u8 d16, d17, d16" + - + asm_text: "vrshl.u16 d16, d17, d16" + - + asm_text: "vrshl.u32 d16, d17, d16" + - + asm_text: "vrshl.u64 d16, d17, d16" + - + asm_text: "vrshl.s8 q8, q9, q8" + - + asm_text: "vrshl.s16 q8, q9, q8" + - + asm_text: "vrshl.s32 q8, q9, q8" + - + asm_text: "vrshl.s64 q8, q9, q8" + - + asm_text: "vrshl.u8 q8, q9, q8" + - + asm_text: "vrshl.u16 q8, q9, q8" + - + asm_text: "vrshl.u32 q8, q9, q8" + - + asm_text: "vrshl.u64 q8, q9, q8" + - + asm_text: "vrshr.s8 d16, d16, #8" + - + asm_text: "vrshr.s16 d16, d16, #0x10" + - + asm_text: "vrshr.s32 d16, d16, #0x20" + - + asm_text: "vrshr.s64 d16, d16, #0x40" + - + asm_text: "vrshr.u8 d16, d16, #8" + - + asm_text: "vrshr.u16 d16, d16, #0x10" + - + asm_text: "vrshr.u32 d16, d16, #0x20" + - + asm_text: "vrshr.u64 d16, d16, #0x40" + - + asm_text: "vrshr.s8 q8, q8, #8" + - + asm_text: "vrshr.s16 q8, q8, #0x10" + - + asm_text: "vrshr.s32 q8, q8, #0x20" + - + asm_text: "vrshr.s64 q8, q8, #0x40" + - + asm_text: "vrshr.u8 q8, q8, #8" + - + asm_text: "vrshr.u16 q8, q8, #0x10" + - + asm_text: "vrshr.u32 q8, q8, #0x20" + - + asm_text: "vrshr.u64 q8, q8, #0x40" + - + asm_text: "vrshrn.i16 d16, q8, #8" + - + asm_text: "vrshrn.i32 d16, q8, #0x10" + - + asm_text: "vrshrn.i64 d16, q8, #0x20" + - + asm_text: "vqrshrn.s16 d16, q8, #4" + - + asm_text: "vqrshrn.s32 d16, q8, #0xd" + - + asm_text: "vqrshrn.s64 d16, q8, #0xd" + - + asm_text: "vqrshrn.u16 d16, q8, #4" + - + asm_text: "vqrshrn.u32 d16, q8, #0xd" + - + asm_text: "vqrshrn.u64 d16, q8, #0xd" + - + asm_text: "vshl.s8 q4, q4, q5" + - + asm_text: "vshl.s16 q4, q4, q5" + - + asm_text: "vshl.s32 q4, q4, q5" + - + asm_text: "vshl.s64 q4, q4, q5" + - + asm_text: "vshl.u8 q4, q4, q5" + - + asm_text: "vshl.u16 q4, q4, q5" + - + asm_text: "vshl.u32 q4, q4, q5" + - + asm_text: "vshl.u64 q4, q4, q5" + - + asm_text: "vshl.s8 d4, d4, d5" + - + asm_text: "vshl.s16 d4, d4, d5" + - + asm_text: "vshl.s32 d4, d4, d5" + - + asm_text: "vshl.s64 d4, d4, d5" + - + asm_text: "vshl.u8 d4, d4, d5" + - + asm_text: "vshl.u16 d4, d4, d5" + - + asm_text: "vshl.u32 d4, d4, d5" + - + asm_text: "vshl.u64 d4, d4, d5" + - + asm_text: "vshl.i8 q4, q4, #2" + - + asm_text: "vshl.i16 q4, q4, #0xe" + - + asm_text: "vshl.i32 q4, q4, #0x1b" + - + asm_text: "vshl.i64 q4, q4, #0x23" + - + asm_text: "vshl.i8 d4, d4, #6" + - + asm_text: "vshl.i16 d4, d4, #0xa" + - + asm_text: "vshl.i32 d4, d4, #0x11" + - + asm_text: "vshl.i64 d4, d4, #0x2b" + - + asm_text: "vrshl.s8 d11, d11, d4" + - + asm_text: "vrshl.s16 d12, d12, d5" + - + asm_text: "vrshl.s32 d13, d13, d6" + - + asm_text: "vrshl.s64 d14, d14, d7" + - + asm_text: "vrshl.u8 d15, d15, d8" + - + asm_text: "vrshl.u16 d16, d16, d9" + - + asm_text: "vrshl.u32 d17, d17, d10" + - + asm_text: "vrshl.u64 d18, d18, d11" + - + asm_text: "vrshl.s8 q1, q1, q8" + - + asm_text: "vrshl.s16 q2, q2, q15" + - + asm_text: "vrshl.s32 q3, q3, q14" + - + asm_text: "vrshl.s64 q4, q4, q13" + - + asm_text: "vrshl.u8 q5, q5, q12" + - + asm_text: "vrshl.u16 q6, q6, q11" + - + asm_text: "vrshl.u32 q7, q7, q10" + - + asm_text: "vrshl.u64 q8, q8, q9" + - + asm_text: "vshr.s8 d15, d15, #8" + - + asm_text: "vshr.s16 d12, d12, #0x10" + - + asm_text: "vshr.s32 d13, d13, #0x20" + - + asm_text: "vshr.s64 d14, d14, #0x40" + - + asm_text: "vshr.u8 d16, d16, #8" + - + asm_text: "vshr.u16 d17, d17, #0x10" + - + asm_text: "vshr.u32 d6, d6, #0x20" + - + asm_text: "vshr.u64 d10, d10, #0x40" + - + asm_text: "vshr.s8 q1, q1, #8" + - + asm_text: "vshr.s16 q2, q2, #0x10" + - + asm_text: "vshr.s32 q3, q3, #0x20" + - + asm_text: "vshr.s64 q4, q4, #0x40" + - + asm_text: "vshr.u8 q5, q5, #8" + - + asm_text: "vshr.u16 q6, q6, #0x10" + - + asm_text: "vshr.u32 q7, q7, #0x20" + - + asm_text: "vshr.u64 q8, q8, #0x40" + - + asm_text: "vrshr.s8 d15, d15, #8" + - + asm_text: "vrshr.s16 d12, d12, #0x10" + - + asm_text: "vrshr.s32 d13, d13, #0x20" + - + asm_text: "vrshr.s64 d14, d14, #0x40" + - + asm_text: "vrshr.u8 d16, d16, #8" + - + asm_text: "vrshr.u16 d17, d17, #0x10" + - + asm_text: "vrshr.u32 d6, d6, #0x20" + - + asm_text: "vrshr.u64 d10, d10, #0x40" + - + asm_text: "vrshr.s8 q1, q1, #8" + - + asm_text: "vrshr.s16 q2, q2, #0x10" + - + asm_text: "vrshr.s32 q3, q3, #0x20" + - + asm_text: "vrshr.s64 q4, q4, #0x40" + - + asm_text: "vrshr.u8 q5, q5, #8" + - + asm_text: "vrshr.u16 q6, q6, #0x10" + - + asm_text: "vrshr.u32 q7, q7, #0x20" + - + asm_text: "vrshr.u64 q8, q8, #0x40" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-shiftaccum-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-shiftaccum-encoding.s.yaml new file mode 100644 index 0000000..9f81e38 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-shiftaccum-encoding.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x30, 0x11, 0xc8, 0xf2, 0x1e, 0xf1, 0x90, 0xf2, 0x1c, 0xd1, 0xa0, 0xf2, 0x9a, 0xb1, 0x80, 0xf2, 0x54, 0xe1, 0x88, 0xf2, 0x5c, 0x61, 0x90, 0xf2, 0x5a, 0x21, 0xe0, 0xf2, 0xd8, 0x01, 0xc0, 0xf2, 0x30, 0x11, 0xc8, 0xf3, 0x1e, 0xb1, 0x95, 0xf3, 0x1f, 0xc1, 0xaa, 0xf3, 0xb0, 0xd1, 0x8a, 0xf3, 0x5e, 0x21, 0x88, 0xf3, 0x5e, 0x41, 0x9a, 0xf3, 0x5c, 0x61, 0xab, 0xf3, 0xda, 0x81, 0xa7, 0xf3, 0x30, 0x01, 0xc8, 0xf2, 0x1e, 0xe1, 0x90, 0xf2, 0x1c, 0xc1, 0xa0, 0xf2, 0x9a, 0xa1, 0x80, 0xf2, 0x54, 0x41, 0x88, 0xf2, 0x5c, 0xc1, 0x90, 0xf2, 0x5a, 0xa1, 0xa0, 0xf2, 0xd8, 0x81, 0x80, 0xf2, 0x30, 0x01, 0xc8, 0xf3, 0x1e, 0xe1, 0x95, 0xf3, 0x1f, 0xf1, 0xaa, 0xf3, 0xb0, 0x01, 0xca, 0xf3, 0x5e, 0xe1, 0x88, 0xf3, 0x5e, 0xe1, 0x9a, 0xf3, 0x5c, 0xc1, 0xab, 0xf3, 0xda, 0xa1, 0xa7, 0xf3, 0x3a, 0x53, 0x88, 0xf2, 0x39, 0x63, 0x90, 0xf2, 0x38, 0x73, 0xa0, 0xf2, 0xb7, 0xe3, 0x80, 0xf2, 0x36, 0xf3, 0x88, 0xf3, 0x35, 0x03, 0xd0, 0xf3, 0x34, 0x13, 0xe0, 0xf3, 0xb3, 0x23, 0xc0, 0xf3, 0x54, 0x23, 0x88, 0xf2, 0x56, 0x43, 0x90, 0xf2, 0x58, 0x63, 0xa0, 0xf2, 0xda, 0x83, 0x80, 0xf2, 0x5c, 0xa3, 0x88, 0xf3, 0x5e, 0xc3, 0x90, 0xf3, 0x70, 0xe3, 0xa0, 0xf3, 0xf2, 0x03, 0xc0, 0xf3, 0x3a, 0xa3, 0xc8, 0xf2, 0x39, 0x93, 0xd0, 0xf2, 0x38, 0x83, 0xe0, 0xf2, 0xb7, 0x73, 0xc0, 0xf2, 0x36, 0x63, 0xc8, 0xf3, 0x35, 0x53, 0xd0, 0xf3, 0x34, 0x43, 0xe0, 0xf3, 0xb3, 0x33, 0xc0, 0xf3, 0x54, 0x43, 0x88, 0xf2, 0x56, 0x63, 0x90, 0xf2, 0x58, 0x83, 0xa0, 0xf2, 0xda, 0xa3, 0x80, 0xf2, 0x5c, 0xc3, 0x88, 0xf3, 0x5e, 0xe3, 0x90, 0xf3, 0x70, 0x03, 0xe0, 0xf3, 0xf2, 0x23, 0xc0, 0xf3, 0x1c, 0xb5, 0x8f, 0xf3, 0x1d, 0xc5, 0x9f, 0xf3, 0x1e, 0xd5, 0xbf, 0xf3, 0x9f, 0xe5, 0xbf, 0xf3, 0x70, 0x25, 0x8f, 0xf3, 0x5e, 0x45, 0x9f, 0xf3, 0x58, 0x65, 0xbf, 0xf3, 0xda, 0x85, 0xbf, 0xf3, 0x1b, 0xc4, 0xc8, 0xf3, 0x1c, 0xa4, 0xd0, 0xf3, 0x1d, 0x84, 0xe0, 0xf3, 0x9e, 0x54, 0xc0, 0xf3, 0x70, 0x24, 0x88, 0xf3, 0x54, 0xa4, 0x90, 0xf3, 0x58, 0xe4, 0xa0, 0xf3, 0xdc, 0x24, 0xc0, 0xf3, 0x1c, 0xc5, 0x8f, 0xf3, 0x1d, 0xd5, 0x9f, 0xf3, 0x1e, 0xe5, 0xbf, 0xf3, 0x9f, 0xf5, 0xbf, 0xf3, 0x70, 0x05, 0xcf, 0xf3, 0x5e, 0xe5, 0x9f, 0xf3, 0x58, 0x85, 0xbf, 0xf3, 0xda, 0xa5, 0xbf, 0xf3, 0x1b, 0xb4, 0x88, 0xf3, 0x1c, 0xc4, 0x90, 0xf3, 0x1d, 0xd4, 0xa0, 0xf3, 0x9e, 0xe4, 0x80, 0xf3, 0x70, 0x04, 0xc8, 0xf3, 0x54, 0x44, 0x90, 0xf3, 0x58, 0x84, 0xa0, 0xf3, 0xdc, 0xc4, 0x80, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vsra.s8 d17, d16, #8" + - + asm_text: "vsra.s16 d15, d14, #0x10" + - + asm_text: "vsra.s32 d13, d12, #0x20" + - + asm_text: "vsra.s64 d11, d10, #0x40" + - + asm_text: "vsra.s8 q7, q2, #8" + - + asm_text: "vsra.s16 q3, q6, #0x10" + - + asm_text: "vsra.s32 q9, q5, #0x20" + - + asm_text: "vsra.s64 q8, q4, #0x40" + - + asm_text: "vsra.u8 d17, d16, #8" + - + asm_text: "vsra.u16 d11, d14, #0xb" + - + asm_text: "vsra.u32 d12, d15, #0x16" + - + asm_text: "vsra.u64 d13, d16, #0x36" + - + asm_text: "vsra.u8 q1, q7, #8" + - + asm_text: "vsra.u16 q2, q7, #6" + - + asm_text: "vsra.u32 q3, q6, #0x15" + - + asm_text: "vsra.u64 q4, q5, #0x19" + - + asm_text: "vsra.s8 d16, d16, #8" + - + asm_text: "vsra.s16 d14, d14, #0x10" + - + asm_text: "vsra.s32 d12, d12, #0x20" + - + asm_text: "vsra.s64 d10, d10, #0x40" + - + asm_text: "vsra.s8 q2, q2, #8" + - + asm_text: "vsra.s16 q6, q6, #0x10" + - + asm_text: "vsra.s32 q5, q5, #0x20" + - + asm_text: "vsra.s64 q4, q4, #0x40" + - + asm_text: "vsra.u8 d16, d16, #8" + - + asm_text: "vsra.u16 d14, d14, #0xb" + - + asm_text: "vsra.u32 d15, d15, #0x16" + - + asm_text: "vsra.u64 d16, d16, #0x36" + - + asm_text: "vsra.u8 q7, q7, #8" + - + asm_text: "vsra.u16 q7, q7, #6" + - + asm_text: "vsra.u32 q6, q6, #0x15" + - + asm_text: "vsra.u64 q5, q5, #0x19" + - + asm_text: "vrsra.s8 d5, d26, #8" + - + asm_text: "vrsra.s16 d6, d25, #0x10" + - + asm_text: "vrsra.s32 d7, d24, #0x20" + - + asm_text: "vrsra.s64 d14, d23, #0x40" + - + asm_text: "vrsra.u8 d15, d22, #8" + - + asm_text: "vrsra.u16 d16, d21, #0x10" + - + asm_text: "vrsra.u32 d17, d20, #0x20" + - + asm_text: "vrsra.u64 d18, d19, #0x40" + - + asm_text: "vrsra.s8 q1, q2, #8" + - + asm_text: "vrsra.s16 q2, q3, #0x10" + - + asm_text: "vrsra.s32 q3, q4, #0x20" + - + asm_text: "vrsra.s64 q4, q5, #0x40" + - + asm_text: "vrsra.u8 q5, q6, #8" + - + asm_text: "vrsra.u16 q6, q7, #0x10" + - + asm_text: "vrsra.u32 q7, q8, #0x20" + - + asm_text: "vrsra.u64 q8, q9, #0x40" + - + asm_text: "vrsra.s8 d26, d26, #8" + - + asm_text: "vrsra.s16 d25, d25, #0x10" + - + asm_text: "vrsra.s32 d24, d24, #0x20" + - + asm_text: "vrsra.s64 d23, d23, #0x40" + - + asm_text: "vrsra.u8 d22, d22, #8" + - + asm_text: "vrsra.u16 d21, d21, #0x10" + - + asm_text: "vrsra.u32 d20, d20, #0x20" + - + asm_text: "vrsra.u64 d19, d19, #0x40" + - + asm_text: "vrsra.s8 q2, q2, #8" + - + asm_text: "vrsra.s16 q3, q3, #0x10" + - + asm_text: "vrsra.s32 q4, q4, #0x20" + - + asm_text: "vrsra.s64 q5, q5, #0x40" + - + asm_text: "vrsra.u8 q6, q6, #8" + - + asm_text: "vrsra.u16 q7, q7, #0x10" + - + asm_text: "vrsra.u32 q8, q8, #0x20" + - + asm_text: "vrsra.u64 q9, q9, #0x40" + - + asm_text: "vsli.8 d11, d12, #7" + - + asm_text: "vsli.16 d12, d13, #0xf" + - + asm_text: "vsli.32 d13, d14, #0x1f" + - + asm_text: "vsli.64 d14, d15, #0x3f" + - + asm_text: "vsli.8 q1, q8, #7" + - + asm_text: "vsli.16 q2, q7, #0xf" + - + asm_text: "vsli.32 q3, q4, #0x1f" + - + asm_text: "vsli.64 q4, q5, #0x3f" + - + asm_text: "vsri.8 d28, d11, #8" + - + asm_text: "vsri.16 d26, d12, #0x10" + - + asm_text: "vsri.32 d24, d13, #0x20" + - + asm_text: "vsri.64 d21, d14, #0x40" + - + asm_text: "vsri.8 q1, q8, #8" + - + asm_text: "vsri.16 q5, q2, #0x10" + - + asm_text: "vsri.32 q7, q4, #0x20" + - + asm_text: "vsri.64 q9, q6, #0x40" + - + asm_text: "vsli.8 d12, d12, #7" + - + asm_text: "vsli.16 d13, d13, #0xf" + - + asm_text: "vsli.32 d14, d14, #0x1f" + - + asm_text: "vsli.64 d15, d15, #0x3f" + - + asm_text: "vsli.8 q8, q8, #7" + - + asm_text: "vsli.16 q7, q7, #0xf" + - + asm_text: "vsli.32 q4, q4, #0x1f" + - + asm_text: "vsli.64 q5, q5, #0x3f" + - + asm_text: "vsri.8 d11, d11, #8" + - + asm_text: "vsri.16 d12, d12, #0x10" + - + asm_text: "vsri.32 d13, d13, #0x20" + - + asm_text: "vsri.64 d14, d14, #0x40" + - + asm_text: "vsri.8 q8, q8, #8" + - + asm_text: "vsri.16 q2, q2, #0x10" + - + asm_text: "vsri.32 q4, q4, #0x20" + - + asm_text: "vsri.64 q6, q6, #0x40" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-shuffle-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-shuffle-encoding.s.yaml new file mode 100644 index 0000000..d88d80c --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-shuffle-encoding.s.yaml @@ -0,0 +1,124 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x03, 0xf1, 0xf2, 0xa0, 0x05, 0xf1, 0xf2, 0xe0, 0x03, 0xf2, 0xf2, 0xe0, 0x07, 0xf2, 0xf2, 0xa0, 0x06, 0xf1, 0xf2, 0xe0, 0x0c, 0xf2, 0xf2, 0xe0, 0x08, 0xf2, 0xf2, 0xa0, 0x13, 0xf1, 0xf2, 0x0b, 0x75, 0xb7, 0xf2, 0x60, 0x63, 0xb6, 0xf2, 0xc8, 0x27, 0xf2, 0xf2, 0x2a, 0x16, 0xb1, 0xf2, 0x60, 0xac, 0xba, 0xf2, 0x60, 0xa8, 0xba, 0xf2, 0xa0, 0x10, 0xf2, 0xf3, 0xa0, 0x10, 0xf6, 0xf3, 0xa0, 0x10, 0xfa, 0xf3, 0xe0, 0x20, 0xf2, 0xf3, 0xe0, 0x20, 0xf6, 0xf3, 0xe0, 0x20, 0xfa, 0xf3, 0x20, 0x11, 0xf2, 0xf3, 0x20, 0x11, 0xf6, 0xf3, 0x60, 0x21, 0xf2, 0xf3, 0x60, 0x21, 0xf6, 0xf3, 0x60, 0x21, 0xfa, 0xf3, 0xa0, 0x11, 0xf2, 0xf3, 0xa0, 0x11, 0xf6, 0xf3, 0xe0, 0x21, 0xf2, 0xf3, 0xe0, 0x21, 0xf6, 0xf3, 0xe0, 0x21, 0xfa, 0xf3, 0x83, 0x20, 0xba, 0xf3, 0x83, 0x20, 0xba, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vext.8 d16, d17, d16, #3" + - + asm_text: "vext.8 d16, d17, d16, #5" + - + asm_text: "vext.8 q8, q9, q8, #3" + - + asm_text: "vext.8 q8, q9, q8, #7" + - + asm_text: "vext.16 d16, d17, d16, #3" + - + asm_text: "vext.32 q8, q9, q8, #3" + - + asm_text: "vext.64 q8, q9, q8, #1" + - + asm_text: "vext.8 d17, d17, d16, #3" + - + asm_text: "vext.8 d7, d7, d11, #5" + - + asm_text: "vext.8 q3, q3, q8, #3" + - + asm_text: "vext.8 q9, q9, q4, #7" + - + asm_text: "vext.16 d1, d1, d26, #3" + - + asm_text: "vext.32 q5, q5, q8, #3" + - + asm_text: "vext.64 q5, q5, q8, #1" + - + asm_text: "vtrn.8 d17, d16" + - + asm_text: "vtrn.16 d17, d16" + - + asm_text: "vtrn.32 d17, d16" + - + asm_text: "vtrn.8 q9, q8" + - + asm_text: "vtrn.16 q9, q8" + - + asm_text: "vtrn.32 q9, q8" + - + asm_text: "vuzp.8 d17, d16" + - + asm_text: "vuzp.16 d17, d16" + - + asm_text: "vuzp.8 q9, q8" + - + asm_text: "vuzp.16 q9, q8" + - + asm_text: "vuzp.32 q9, q8" + - + asm_text: "vzip.8 d17, d16" + - + asm_text: "vzip.16 d17, d16" + - + asm_text: "vzip.8 q9, q8" + - + asm_text: "vzip.16 q9, q8" + - + asm_text: "vzip.32 q9, q8" + - + asm_text: "vtrn.32 d2, d3" + - + asm_text: "vtrn.32 d2, d3" + - + asm_text: "vtrn.8 d3, d9" + - + asm_text: "vtrn.8 d3, d9" + - + asm_text: "vtrn.8 d3, d9" + - + asm_text: "vtrn.8 d3, d9" + - + asm_text: "vtrn.16 d3, d9" + - + asm_text: "vtrn.16 d3, d9" + - + asm_text: "vtrn.16 d3, d9" + - + asm_text: "vtrn.16 d3, d9" + - + asm_text: "vtrn.32 d3, d9" + - + asm_text: "vtrn.32 d3, d9" + - + asm_text: "vtrn.32 d3, d9" + - + asm_text: "vtrn.32 d3, d9" + - + asm_text: "vtrn.32 d3, d9" + - + asm_text: "vtrn.8 q14, q6" + - + asm_text: "vtrn.8 q14, q6" + - + asm_text: "vtrn.8 q14, q6" + - + asm_text: "vtrn.8 q14, q6" + - + asm_text: "vtrn.16 q14, q6" + - + asm_text: "vtrn.16 q14, q6" + - + asm_text: "vtrn.16 q14, q6" + - + asm_text: "vtrn.16 q14, q6" + - + asm_text: "vtrn.32 q14, q6" + - + asm_text: "vtrn.32 q14, q6" + - + asm_text: "vtrn.32 q14, q6" + - + asm_text: "vtrn.32 q14, q6" + - + asm_text: "vtrn.32 q14, q6" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-sub-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-sub-encoding.s.yaml new file mode 100644 index 0000000..91e179f --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-sub-encoding.s.yaml @@ -0,0 +1,170 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x08, 0x41, 0xf3, 0xa0, 0x08, 0x51, 0xf3, 0xa0, 0x08, 0x61, 0xf3, 0xa0, 0x08, 0x71, 0xf3, 0xa1, 0x0d, 0x60, 0xf2, 0xe2, 0x08, 0x40, 0xf3, 0xe2, 0x08, 0x50, 0xf3, 0xe2, 0x08, 0x60, 0xf3, 0xe2, 0x08, 0x70, 0xf3, 0xe2, 0x0d, 0x60, 0xf2, 0x25, 0xd8, 0x0d, 0xf3, 0x26, 0xe8, 0x1e, 0xf3, 0x27, 0xf8, 0x2f, 0xf3, 0xa8, 0x08, 0x70, 0xf3, 0xa9, 0x1d, 0x61, 0xf2, 0x64, 0x28, 0x02, 0xf3, 0x62, 0x48, 0x14, 0xf3, 0x60, 0x68, 0x26, 0xf3, 0x4e, 0x88, 0x38, 0xf3, 0x4c, 0xad, 0x2a, 0xf2, 0xa0, 0x02, 0xc1, 0xf2, 0xa0, 0x02, 0xd1, 0xf2, 0xa0, 0x02, 0xe1, 0xf2, 0xa0, 0x02, 0xc1, 0xf3, 0xa0, 0x02, 0xd1, 0xf3, 0xa0, 0x02, 0xe1, 0xf3, 0xa2, 0x03, 0xc0, 0xf2, 0xa2, 0x03, 0xd0, 0xf2, 0xa2, 0x03, 0xe0, 0xf2, 0xa2, 0x03, 0xc0, 0xf3, 0xa2, 0x03, 0xd0, 0xf3, 0xa2, 0x03, 0xe0, 0xf3, 0xa1, 0x02, 0x40, 0xf2, 0xa1, 0x02, 0x50, 0xf2, 0xa1, 0x02, 0x60, 0xf2, 0xa1, 0x02, 0x40, 0xf3, 0xa1, 0x02, 0x50, 0xf3, 0xa1, 0x02, 0x60, 0xf3, 0xe2, 0x02, 0x40, 0xf2, 0xe2, 0x02, 0x50, 0xf2, 0xe2, 0x02, 0x60, 0xf2, 0xb1, 0x02, 0x40, 0xf2, 0xb1, 0x02, 0x50, 0xf2, 0xb1, 0x02, 0x60, 0xf2, 0xb1, 0x02, 0x70, 0xf2, 0xb1, 0x02, 0x40, 0xf3, 0xb1, 0x02, 0x50, 0xf3, 0xb1, 0x02, 0x60, 0xf3, 0xb1, 0x02, 0x70, 0xf3, 0xf2, 0x02, 0x40, 0xf2, 0xf2, 0x02, 0x50, 0xf2, 0xf2, 0x02, 0x60, 0xf2, 0xf2, 0x02, 0x70, 0xf2, 0xf2, 0x02, 0x40, 0xf3, 0xf2, 0x02, 0x50, 0xf3, 0xf2, 0x02, 0x60, 0xf3, 0xf2, 0x02, 0x70, 0xf3, 0xa2, 0x06, 0xc0, 0xf2, 0xa2, 0x06, 0xd0, 0xf2, 0xa2, 0x06, 0xe0, 0xf2, 0xa2, 0x06, 0xc0, 0xf3, 0xa2, 0x06, 0xd0, 0xf3, 0xa2, 0x06, 0xe0, 0xf3, 0x28, 0xb2, 0x0b, 0xf2, 0x27, 0xc2, 0x1c, 0xf2, 0x26, 0xd2, 0x2d, 0xf2, 0x25, 0xe2, 0x0e, 0xf3, 0x24, 0xf2, 0x1f, 0xf3, 0xa3, 0x02, 0x60, 0xf3, 0x68, 0x22, 0x02, 0xf2, 0x66, 0x42, 0x14, 0xf2, 0x64, 0x62, 0x26, 0xf2, 0x62, 0x82, 0x08, 0xf3, 0x60, 0xa2, 0x1a, 0xf3, 0x4e, 0xc2, 0x2c, 0xf3, 0x05, 0xc3, 0x8c, 0xf2, 0x01, 0xe3, 0x9e, 0xf2, 0x82, 0x03, 0xe0, 0xf2, 0x05, 0xc3, 0x8c, 0xf3, 0x01, 0xe3, 0x9e, 0xf3, 0x82, 0x03, 0xe0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vsub.i8 d16, d17, d16" + - + asm_text: "vsub.i16 d16, d17, d16" + - + asm_text: "vsub.i32 d16, d17, d16" + - + asm_text: "vsub.i64 d16, d17, d16" + - + asm_text: "vsub.f32 d16, d16, d17" + - + asm_text: "vsub.i8 q8, q8, q9" + - + asm_text: "vsub.i16 q8, q8, q9" + - + asm_text: "vsub.i32 q8, q8, q9" + - + asm_text: "vsub.i64 q8, q8, q9" + - + asm_text: "vsub.f32 q8, q8, q9" + - + asm_text: "vsub.i8 d13, d13, d21" + - + asm_text: "vsub.i16 d14, d14, d22" + - + asm_text: "vsub.i32 d15, d15, d23" + - + asm_text: "vsub.i64 d16, d16, d24" + - + asm_text: "vsub.f32 d17, d17, d25" + - + asm_text: "vsub.i8 q1, q1, q10" + - + asm_text: "vsub.i16 q2, q2, q9" + - + asm_text: "vsub.i32 q3, q3, q8" + - + asm_text: "vsub.i64 q4, q4, q7" + - + asm_text: "vsub.f32 q5, q5, q6" + - + asm_text: "vsubl.s8 q8, d17, d16" + - + asm_text: "vsubl.s16 q8, d17, d16" + - + asm_text: "vsubl.s32 q8, d17, d16" + - + asm_text: "vsubl.u8 q8, d17, d16" + - + asm_text: "vsubl.u16 q8, d17, d16" + - + asm_text: "vsubl.u32 q8, d17, d16" + - + asm_text: "vsubw.s8 q8, q8, d18" + - + asm_text: "vsubw.s16 q8, q8, d18" + - + asm_text: "vsubw.s32 q8, q8, d18" + - + asm_text: "vsubw.u8 q8, q8, d18" + - + asm_text: "vsubw.u16 q8, q8, d18" + - + asm_text: "vsubw.u32 q8, q8, d18" + - + asm_text: "vhsub.s8 d16, d16, d17" + - + asm_text: "vhsub.s16 d16, d16, d17" + - + asm_text: "vhsub.s32 d16, d16, d17" + - + asm_text: "vhsub.u8 d16, d16, d17" + - + asm_text: "vhsub.u16 d16, d16, d17" + - + asm_text: "vhsub.u32 d16, d16, d17" + - + asm_text: "vhsub.s8 q8, q8, q9" + - + asm_text: "vhsub.s16 q8, q8, q9" + - + asm_text: "vhsub.s32 q8, q8, q9" + - + asm_text: "vqsub.s8 d16, d16, d17" + - + asm_text: "vqsub.s16 d16, d16, d17" + - + asm_text: "vqsub.s32 d16, d16, d17" + - + asm_text: "vqsub.s64 d16, d16, d17" + - + asm_text: "vqsub.u8 d16, d16, d17" + - + asm_text: "vqsub.u16 d16, d16, d17" + - + asm_text: "vqsub.u32 d16, d16, d17" + - + asm_text: "vqsub.u64 d16, d16, d17" + - + asm_text: "vqsub.s8 q8, q8, q9" + - + asm_text: "vqsub.s16 q8, q8, q9" + - + asm_text: "vqsub.s32 q8, q8, q9" + - + asm_text: "vqsub.s64 q8, q8, q9" + - + asm_text: "vqsub.u8 q8, q8, q9" + - + asm_text: "vqsub.u16 q8, q8, q9" + - + asm_text: "vqsub.u32 q8, q8, q9" + - + asm_text: "vqsub.u64 q8, q8, q9" + - + asm_text: "vsubhn.i16 d16, q8, q9" + - + asm_text: "vsubhn.i32 d16, q8, q9" + - + asm_text: "vsubhn.i64 d16, q8, q9" + - + asm_text: "vrsubhn.i16 d16, q8, q9" + - + asm_text: "vrsubhn.i32 d16, q8, q9" + - + asm_text: "vrsubhn.i64 d16, q8, q9" + - + asm_text: "vhsub.s8 d11, d11, d24" + - + asm_text: "vhsub.s16 d12, d12, d23" + - + asm_text: "vhsub.s32 d13, d13, d22" + - + asm_text: "vhsub.u8 d14, d14, d21" + - + asm_text: "vhsub.u16 d15, d15, d20" + - + asm_text: "vhsub.u32 d16, d16, d19" + - + asm_text: "vhsub.s8 q1, q1, q12" + - + asm_text: "vhsub.s16 q2, q2, q11" + - + asm_text: "vhsub.s32 q3, q3, q10" + - + asm_text: "vhsub.u8 q4, q4, q9" + - + asm_text: "vhsub.u16 q5, q5, q8" + - + asm_text: "vhsub.u32 q6, q6, q7" + - + asm_text: "vsubw.s8 q6, q6, d5" + - + asm_text: "vsubw.s16 q7, q7, d1" + - + asm_text: "vsubw.s32 q8, q8, d2" + - + asm_text: "vsubw.u8 q6, q6, d5" + - + asm_text: "vsubw.u16 q7, q7, d1" + - + asm_text: "vsubw.u32 q8, q8, d2" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-table-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-table-encoding.s.yaml new file mode 100644 index 0000000..7f2e073 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-table-encoding.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x08, 0xf1, 0xf3, 0xa2, 0x09, 0xf0, 0xf3, 0xa4, 0x0a, 0xf0, 0xf3, 0xa4, 0x0b, 0xf0, 0xf3, 0xe1, 0x28, 0xf0, 0xf3, 0xe2, 0x39, 0xf0, 0xf3, 0xe5, 0x4a, 0xf0, 0xf3, 0xe5, 0x4b, 0xf0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vtbl.8 d16, {d17}, d16" + - + asm_text: "vtbl.8 d16, {d16, d17}, d18" + - + asm_text: "vtbl.8 d16, {d16, d17, d18}, d20" + - + asm_text: "vtbl.8 d16, {d16, d17, d18, d19}, d20" + - + asm_text: "vtbx.8 d18, {d16}, d17" + - + asm_text: "vtbx.8 d19, {d16, d17}, d18" + - + asm_text: "vtbx.8 d20, {d16, d17, d18}, d21" + - + asm_text: "vtbx.8 d20, {d16, d17, d18, d19}, d21" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-v8.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-v8.s.yaml new file mode 100644 index 0000000..217c03f --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-v8.s.yaml @@ -0,0 +1,82 @@ +test_cases: + - + input: + bytes: [ 0x11, 0x4f, 0x05, 0xf3, 0x5c, 0x4f, 0x08, 0xf3, 0x3e, 0x5f, 0x24, 0xf3, 0xd4, 0x0f, 0x2a, 0xf3, 0x06, 0x40, 0xbb, 0xf3, 0x8a, 0xc0, 0xbb, 0xf3, 0x4c, 0x80, 0xbb, 0xf3, 0xe4, 0x80, 0xbb, 0xf3, 0x2e, 0x13, 0xbb, 0xf3, 0x8a, 0xc3, 0xbb, 0xf3, 0x64, 0x23, 0xbb, 0xf3, 0xc2, 0xa3, 0xfb, 0xf3, 0x21, 0xf1, 0xbb, 0xf3, 0x83, 0x51, 0xbb, 0xf3, 0x60, 0x61, 0xbb, 0xf3, 0xc6, 0xa1, 0xbb, 0xf3, 0x25, 0xb2, 0xbb, 0xf3, 0xa7, 0xe2, 0xbb, 0xf3, 0x6e, 0x82, 0xbb, 0xf3, 0xe0, 0x22, 0xfb, 0xf3, 0x00, 0x34, 0xba, 0xf3, 0x48, 0x24, 0xba, 0xf3, 0x8c, 0x54, 0xba, 0xf3, 0xc6, 0x04, 0xba, 0xf3, 0x00, 0x35, 0xba, 0xf3, 0x44, 0x05, 0xfa, 0xf3, 0xa2, 0xc5, 0xba, 0xf3, 0xc8, 0x25, 0xfa, 0xf3, 0x80, 0x36, 0xba, 0xf3, 0xc8, 0x26, 0xba, 0xf3, 0x80, 0x37, 0xba, 0xf3, 0xc8, 0x27, 0xba, 0xf3, 0x00, 0x34, 0xba, 0xf3, 0xc6, 0x04, 0xba, 0xf3, 0x00, 0x35, 0xba, 0xf3, 0xc8, 0x25, 0xfa, 0xf3, 0xc8, 0x27, 0xba, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmaxnm.f32 d4, d5, d1" + - + asm_text: "vmaxnm.f32 q2, q4, q6" + - + asm_text: "vminnm.f32 d5, d4, d30" + - + asm_text: "vminnm.f32 q0, q13, q2" + - + asm_text: "vcvta.s32.f32 d4, d6" + - + asm_text: "vcvta.u32.f32 d12, d10" + - + asm_text: "vcvta.s32.f32 q4, q6" + - + asm_text: "vcvta.u32.f32 q4, q10" + - + asm_text: "vcvtm.s32.f32 d1, d30" + - + asm_text: "vcvtm.u32.f32 d12, d10" + - + asm_text: "vcvtm.s32.f32 q1, q10" + - + asm_text: "vcvtm.u32.f32 q13, q1" + - + asm_text: "vcvtn.s32.f32 d15, d17" + - + asm_text: "vcvtn.u32.f32 d5, d3" + - + asm_text: "vcvtn.s32.f32 q3, q8" + - + asm_text: "vcvtn.u32.f32 q5, q3" + - + asm_text: "vcvtp.s32.f32 d11, d21" + - + asm_text: "vcvtp.u32.f32 d14, d23" + - + asm_text: "vcvtp.s32.f32 q4, q15" + - + asm_text: "vcvtp.u32.f32 q9, q8" + - + asm_text: "vrintn.f32 d3, d0" + - + asm_text: "vrintn.f32 q1, q4" + - + asm_text: "vrintx.f32 d5, d12" + - + asm_text: "vrintx.f32 q0, q3" + - + asm_text: "vrinta.f32 d3, d0" + - + asm_text: "vrinta.f32 q8, q2" + - + asm_text: "vrintz.f32 d12, d18" + - + asm_text: "vrintz.f32 q9, q4" + - + asm_text: "vrintm.f32 d3, d0" + - + asm_text: "vrintm.f32 q1, q4" + - + asm_text: "vrintp.f32 d3, d0" + - + asm_text: "vrintp.f32 q1, q4" + - + asm_text: "vrintn.f32 d3, d0" + - + asm_text: "vrintx.f32 q0, q3" + - + asm_text: "vrinta.f32 d3, d0" + - + asm_text: "vrintz.f32 q9, q4" + - + asm_text: "vrintp.f32 q1, q4" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-vld-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-vld-encoding.s.yaml new file mode 100644 index 0000000..a6af6c6 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-vld-encoding.s.yaml @@ -0,0 +1,432 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0x07, 0x60, 0xf4, 0x4f, 0x07, 0x60, 0xf4, 0x8f, 0x07, 0x60, 0xf4, 0xcf, 0x07, 0x60, 0xf4, 0x1f, 0x0a, 0x60, 0xf4, 0x6f, 0x0a, 0x60, 0xf4, 0x8f, 0x0a, 0x60, 0xf4, 0xcf, 0x0a, 0x60, 0xf4, 0x0f, 0x16, 0x23, 0xf4, 0x5f, 0x46, 0x23, 0xf4, 0x8f, 0x56, 0x23, 0xf4, 0xdf, 0x66, 0x23, 0xf4, 0x0f, 0x12, 0x23, 0xf4, 0x5f, 0x42, 0x23, 0xf4, 0x8f, 0x52, 0x23, 0xf4, 0xdf, 0x62, 0x23, 0xf4, 0x1d, 0x07, 0x60, 0xf4, 0x4d, 0x07, 0x60, 0xf4, 0x8d, 0x07, 0x60, 0xf4, 0xcd, 0x07, 0x60, 0xf4, 0x1d, 0x0a, 0x60, 0xf4, 0x6d, 0x0a, 0x60, 0xf4, 0x8d, 0x0a, 0x60, 0xf4, 0xcd, 0x0a, 0x60, 0xf4, 0x15, 0x07, 0x60, 0xf4, 0x45, 0x07, 0x60, 0xf4, 0x85, 0x07, 0x60, 0xf4, 0xc5, 0x07, 0x60, 0xf4, 0x15, 0x0a, 0x60, 0xf4, 0x65, 0x0a, 0x60, 0xf4, 0x85, 0x0a, 0x60, 0xf4, 0xc5, 0x0a, 0x60, 0xf4, 0x0d, 0x16, 0x23, 0xf4, 0x5d, 0x46, 0x23, 0xf4, 0x8d, 0x56, 0x23, 0xf4, 0xdd, 0x66, 0x23, 0xf4, 0x06, 0x16, 0x23, 0xf4, 0x56, 0x46, 0x23, 0xf4, 0x86, 0x56, 0x23, 0xf4, 0xd6, 0x66, 0x23, 0xf4, 0x0d, 0x12, 0x23, 0xf4, 0x5d, 0x42, 0x23, 0xf4, 0x8d, 0x52, 0x23, 0xf4, 0xdd, 0x62, 0x23, 0xf4, 0x08, 0x12, 0x23, 0xf4, 0x58, 0x42, 0x23, 0xf4, 0x88, 0x52, 0x23, 0xf4, 0xd8, 0x62, 0x23, 0xf4, 0x1f, 0x08, 0x60, 0xf4, 0x6f, 0x08, 0x60, 0xf4, 0x8f, 0x08, 0x60, 0xf4, 0x1f, 0x03, 0x60, 0xf4, 0x6f, 0x03, 0x60, 0xf4, 0xbf, 0x03, 0x60, 0xf4, 0x1d, 0x38, 0x60, 0xf4, 0x6d, 0x08, 0x60, 0xf4, 0x8d, 0x48, 0x60, 0xf4, 0x1d, 0x43, 0x20, 0xf4, 0x6d, 0x13, 0x20, 0xf4, 0xbd, 0xe3, 0x20, 0xf4, 0x16, 0x38, 0x60, 0xf4, 0x66, 0x08, 0x60, 0xf4, 0x86, 0x48, 0x60, 0xf4, 0x16, 0x43, 0x20, 0xf4, 0x66, 0x13, 0x20, 0xf4, 0xb6, 0xe3, 0x20, 0xf4, 0x0f, 0x04, 0x61, 0xf4, 0x4f, 0x64, 0x22, 0xf4, 0x8f, 0x14, 0x23, 0xf4, 0x1f, 0x05, 0x60, 0xf4, 0x4f, 0xb5, 0x64, 0xf4, 0x8f, 0x65, 0x25, 0xf4, 0x01, 0xc4, 0x26, 0xf4, 0x42, 0xb4, 0x27, 0xf4, 0x83, 0x24, 0x28, 0xf4, 0x04, 0x45, 0x29, 0xf4, 0x44, 0xe5, 0x29, 0xf4, 0x85, 0x05, 0x6a, 0xf4, 0x0d, 0x64, 0x28, 0xf4, 0x4d, 0x94, 0x27, 0xf4, 0x8d, 0x14, 0x26, 0xf4, 0x1d, 0x05, 0x60, 0xf4, 0x4d, 0x45, 0x65, 0xf4, 0x8d, 0x55, 0x24, 0xf4, 0x1f, 0x00, 0x61, 0xf4, 0x6f, 0x00, 0x62, 0xf4, 0xbf, 0x00, 0x63, 0xf4, 0x3f, 0x11, 0x65, 0xf4, 0x4f, 0x11, 0x67, 0xf4, 0x8f, 0x01, 0x68, 0xf4, 0x1d, 0x00, 0x61, 0xf4, 0x6d, 0x00, 0x62, 0xf4, 0xbd, 0x00, 0x63, 0xf4, 0x3d, 0x11, 0x65, 0xf4, 0x4d, 0x11, 0x67, 0xf4, 0x8d, 0x01, 0x68, 0xf4, 0x18, 0x00, 0x61, 0xf4, 0x47, 0x00, 0x62, 0xf4, 0x95, 0x00, 0x63, 0xf4, 0x32, 0x01, 0x64, 0xf4, 0x43, 0x01, 0x66, 0xf4, 0x84, 0x11, 0x69, 0xf4, 0x0f, 0x4c, 0xa1, 0xf4, 0x0d, 0x4c, 0xa1, 0xf4, 0x03, 0x4c, 0xa1, 0xf4, 0x2f, 0x4c, 0xa1, 0xf4, 0x2d, 0x4c, 0xa1, 0xf4, 0x23, 0x4c, 0xa1, 0xf4, 0x6f, 0x00, 0xe0, 0xf4, 0x9f, 0x04, 0xe0, 0xf4, 0xbf, 0x08, 0xe0, 0xf4, 0xcd, 0xc0, 0xa2, 0xf4, 0xc2, 0xc0, 0xa2, 0xf4, 0xcd, 0xc4, 0xa2, 0xf4, 0x82, 0xc4, 0xa2, 0xf4, 0x3f, 0x01, 0xe0, 0xf4, 0x5f, 0x05, 0xe0, 0xf4, 0x8f, 0x09, 0xe0, 0xf4, 0x6f, 0x15, 0xe0, 0xf4, 0x5f, 0x19, 0xe0, 0xf4, 0x5d, 0x19, 0xe0, 0xf4, 0x83, 0x21, 0xa2, 0xf4, 0x8d, 0x21, 0xa2, 0xf4, 0x8f, 0x21, 0xa2, 0xf4, 0x8f, 0x6d, 0xe1, 0xf4, 0xaf, 0x6d, 0xe1, 0xf4, 0x8d, 0xad, 0xa3, 0xf4, 0xad, 0xed, 0xa4, 0xf4, 0x84, 0x6d, 0xe5, 0xf4, 0xa4, 0x6d, 0xe6, 0xf4, 0x2f, 0x02, 0xe1, 0xf4, 0x4f, 0x66, 0xa2, 0xf4, 0x8f, 0x1a, 0xa3, 0xf4, 0xaf, 0xb6, 0xe4, 0xf4, 0x4f, 0x6a, 0xa5, 0xf4, 0x61, 0xc2, 0xa6, 0xf4, 0x82, 0xb6, 0xa7, 0xf4, 0x83, 0x2a, 0xa8, 0xf4, 0xa4, 0xe6, 0xa9, 0xf4, 0x45, 0x0a, 0xea, 0xf4, 0xcd, 0x62, 0xa8, 0xf4, 0x8d, 0x96, 0xa7, 0xf4, 0x8d, 0x1a, 0xa6, 0xf4, 0xad, 0x46, 0xe5, 0xf4, 0x4d, 0x5a, 0xa4, 0xf4, 0x0f, 0x0e, 0xe1, 0xf4, 0x4f, 0x0e, 0xe2, 0xf4, 0x8f, 0x0e, 0xe3, 0xf4, 0x2f, 0x1e, 0xe7, 0xf4, 0x6f, 0x1e, 0xe7, 0xf4, 0xaf, 0x0e, 0xe8, 0xf4, 0x0d, 0x0e, 0xe1, 0xf4, 0x4d, 0x0e, 0xe2, 0xf4, 0x8d, 0x0e, 0xe3, 0xf4, 0x2d, 0x1e, 0xe7, 0xf4, 0x6d, 0x1e, 0xe7, 0xf4, 0xad, 0x0e, 0xe8, 0xf4, 0x08, 0x0e, 0xe1, 0xf4, 0x47, 0x0e, 0xe2, 0xf4, 0x85, 0x0e, 0xe3, 0xf4, 0x23, 0x0e, 0xe6, 0xf4, 0x63, 0x0e, 0xe6, 0xf4, 0xa4, 0x1e, 0xe9, 0xf4, 0x2f, 0x03, 0xe1, 0xf4, 0x4f, 0x07, 0xe2, 0xf4, 0x8f, 0x0b, 0xe3, 0xf4, 0x6f, 0x17, 0xe7, 0xf4, 0xcf, 0x0b, 0xe8, 0xf4, 0x3d, 0x03, 0xe1, 0xf4, 0x5d, 0x07, 0xe2, 0xf4, 0xad, 0x0b, 0xe3, 0xf4, 0x6d, 0x17, 0xe7, 0xf4, 0xcd, 0x0b, 0xe8, 0xf4, 0x38, 0x03, 0xe1, 0xf4, 0x47, 0x07, 0xe2, 0xf4, 0x95, 0x0b, 0xe3, 0xf4, 0x63, 0x07, 0xe6, 0xf4, 0xc4, 0x1b, 0xe9, 0xf4, 0x0f, 0x0f, 0xe1, 0xf4, 0x4f, 0x0f, 0xe2, 0xf4, 0x8f, 0x0f, 0xe3, 0xf4, 0x2f, 0x1f, 0xe7, 0xf4, 0x6f, 0x1f, 0xe7, 0xf4, 0xaf, 0x0f, 0xe8, 0xf4, 0x0d, 0x0f, 0xe1, 0xf4, 0x4d, 0x0f, 0xe2, 0xf4, 0x8d, 0x0f, 0xe3, 0xf4, 0x2d, 0x1f, 0xe7, 0xf4, 0x6d, 0x1f, 0xe7, 0xf4, 0xad, 0x0f, 0xe8, 0xf4, 0x08, 0x0f, 0xe1, 0xf4, 0x47, 0x0f, 0xe2, 0xf4, 0x85, 0x0f, 0xe3, 0xf4, 0x23, 0x0f, 0xe6, 0xf4, 0x63, 0x0f, 0xe6, 0xf4, 0xa4, 0x1f, 0xe9, 0xf4, 0x0f, 0x6a, 0x29, 0xf4, 0x0f, 0x62, 0x29, 0xf4, 0x0f, 0x27, 0x22, 0xf4, 0x0f, 0x27, 0x22, 0xf4, 0x0f, 0x27, 0x22, 0xf4, 0x0f, 0x4a, 0x22, 0xf4, 0x0f, 0x4a, 0x22, 0xf4, 0x0f, 0x4a, 0x22, 0xf4, 0x8f, 0x4a, 0x22, 0xf4, 0x0f, 0x26, 0x22, 0xf4, 0x8f, 0x26, 0x22, 0xf4, 0xcf, 0x26, 0x22, 0xf4, 0xed, 0x22, 0x22, 0xf4, 0xed, 0x22, 0x22, 0xf4, 0x1f, 0x08, 0x60, 0xf4, 0x6f, 0x08, 0x60, 0xf4 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vld1.8 {d16}, [r0:64]" + - + asm_text: "vld1.16 {d16}, [r0]" + - + asm_text: "vld1.32 {d16}, [r0]" + - + asm_text: "vld1.64 {d16}, [r0]" + - + asm_text: "vld1.8 {d16, d17}, [r0:64]" + - + asm_text: "vld1.16 {d16, d17}, [r0:128]" + - + asm_text: "vld1.32 {d16, d17}, [r0]" + - + asm_text: "vld1.64 {d16, d17}, [r0]" + - + asm_text: "vld1.8 {d1, d2, d3}, [r3]" + - + asm_text: "vld1.16 {d4, d5, d6}, [r3:64]" + - + asm_text: "vld1.32 {d5, d6, d7}, [r3]" + - + asm_text: "vld1.64 {d6, d7, d8}, [r3:64]" + - + asm_text: "vld1.8 {d1, d2, d3, d4}, [r3]" + - + asm_text: "vld1.16 {d4, d5, d6, d7}, [r3:64]" + - + asm_text: "vld1.32 {d5, d6, d7, d8}, [r3]" + - + asm_text: "vld1.64 {d6, d7, d8, d9}, [r3:64]" + - + asm_text: "vld1.8 {d16}, [r0:64]!" + - + asm_text: "vld1.16 {d16}, [r0]!" + - + asm_text: "vld1.32 {d16}, [r0]!" + - + asm_text: "vld1.64 {d16}, [r0]!" + - + asm_text: "vld1.8 {d16, d17}, [r0:64]!" + - + asm_text: "vld1.16 {d16, d17}, [r0:128]!" + - + asm_text: "vld1.32 {d16, d17}, [r0]!" + - + asm_text: "vld1.64 {d16, d17}, [r0]!" + - + asm_text: "vld1.8 {d16}, [r0:64], r5" + - + asm_text: "vld1.16 {d16}, [r0], r5" + - + asm_text: "vld1.32 {d16}, [r0], r5" + - + asm_text: "vld1.64 {d16}, [r0], r5" + - + asm_text: "vld1.8 {d16, d17}, [r0:64], r5" + - + asm_text: "vld1.16 {d16, d17}, [r0:128], r5" + - + asm_text: "vld1.32 {d16, d17}, [r0], r5" + - + asm_text: "vld1.64 {d16, d17}, [r0], r5" + - + asm_text: "vld1.8 {d1, d2, d3}, [r3]!" + - + asm_text: "vld1.16 {d4, d5, d6}, [r3:64]!" + - + asm_text: "vld1.32 {d5, d6, d7}, [r3]!" + - + asm_text: "vld1.64 {d6, d7, d8}, [r3:64]!" + - + asm_text: "vld1.8 {d1, d2, d3}, [r3], r6" + - + asm_text: "vld1.16 {d4, d5, d6}, [r3:64], r6" + - + asm_text: "vld1.32 {d5, d6, d7}, [r3], r6" + - + asm_text: "vld1.64 {d6, d7, d8}, [r3:64], r6" + - + asm_text: "vld1.8 {d1, d2, d3, d4}, [r3]!" + - + asm_text: "vld1.16 {d4, d5, d6, d7}, [r3:64]!" + - + asm_text: "vld1.32 {d5, d6, d7, d8}, [r3]!" + - + asm_text: "vld1.64 {d6, d7, d8, d9}, [r3:64]!" + - + asm_text: "vld1.8 {d1, d2, d3, d4}, [r3], r8" + - + asm_text: "vld1.16 {d4, d5, d6, d7}, [r3:64], r8" + - + asm_text: "vld1.32 {d5, d6, d7, d8}, [r3], r8" + - + asm_text: "vld1.64 {d6, d7, d8, d9}, [r3:64], r8" + - + asm_text: "vld2.8 {d16, d17}, [r0:64]" + - + asm_text: "vld2.16 {d16, d17}, [r0:128]" + - + asm_text: "vld2.32 {d16, d17}, [r0]" + - + asm_text: "vld2.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vld2.16 {d16, d17, d18, d19}, [r0:128]" + - + asm_text: "vld2.32 {d16, d17, d18, d19}, [r0:256]" + - + asm_text: "vld2.8 {d19, d20}, [r0:64]!" + - + asm_text: "vld2.16 {d16, d17}, [r0:128]!" + - + asm_text: "vld2.32 {d20, d21}, [r0]!" + - + asm_text: "vld2.8 {d4, d5, d6, d7}, [r0:64]!" + - + asm_text: "vld2.16 {d1, d2, d3, d4}, [r0:128]!" + - + asm_text: "vld2.32 {d14, d15, d16, d17}, [r0:256]!" + - + asm_text: "vld2.8 {d19, d20}, [r0:64], r6" + - + asm_text: "vld2.16 {d16, d17}, [r0:128], r6" + - + asm_text: "vld2.32 {d20, d21}, [r0], r6" + - + asm_text: "vld2.8 {d4, d5, d6, d7}, [r0:64], r6" + - + asm_text: "vld2.16 {d1, d2, d3, d4}, [r0:128], r6" + - + asm_text: "vld2.32 {d14, d15, d16, d17}, [r0:256], r6" + - + asm_text: "vld3.8 {d16, d17, d18}, [r1]" + - + asm_text: "vld3.16 {d6, d7, d8}, [r2]" + - + asm_text: "vld3.32 {d1, d2, d3}, [r3]" + - + asm_text: "vld3.8 {d16, d18, d20}, [r0:64]" + - + asm_text: "vld3.16 {d27, d29, d31}, [r4]" + - + asm_text: "vld3.32 {d6, d8, d10}, [r5]" + - + asm_text: "vld3.8 {d12, d13, d14}, [r6], r1" + - + asm_text: "vld3.16 {d11, d12, d13}, [r7], r2" + - + asm_text: "vld3.32 {d2, d3, d4}, [r8], r3" + - + asm_text: "vld3.8 {d4, d6, d8}, [r9], r4" + - + asm_text: "vld3.16 {d14, d16, d18}, [r9], r4" + - + asm_text: "vld3.32 {d16, d18, d20}, [r10], r5" + - + asm_text: "vld3.8 {d6, d7, d8}, [r8]!" + - + asm_text: "vld3.16 {d9, d10, d11}, [r7]!" + - + asm_text: "vld3.32 {d1, d2, d3}, [r6]!" + - + asm_text: "vld3.8 {d16, d18, d20}, [r0:64]!" + - + asm_text: "vld3.16 {d20, d22, d24}, [r5]!" + - + asm_text: "vld3.32 {d5, d7, d9}, [r4]!" + - + asm_text: "vld4.8 {d16, d17, d18, d19}, [r1:64]" + - + asm_text: "vld4.16 {d16, d17, d18, d19}, [r2:128]" + - + asm_text: "vld4.32 {d16, d17, d18, d19}, [r3:256]" + - + asm_text: "vld4.8 {d17, d19, d21, d23}, [r5:256]" + - + asm_text: "vld4.16 {d17, d19, d21, d23}, [r7]" + - + asm_text: "vld4.32 {d16, d18, d20, d22}, [r8]" + - + asm_text: "vld4.8 {d16, d17, d18, d19}, [r1:64]!" + - + asm_text: "vld4.16 {d16, d17, d18, d19}, [r2:128]!" + - + asm_text: "vld4.32 {d16, d17, d18, d19}, [r3:256]!" + - + asm_text: "vld4.8 {d17, d19, d21, d23}, [r5:256]!" + - + asm_text: "vld4.16 {d17, d19, d21, d23}, [r7]!" + - + asm_text: "vld4.32 {d16, d18, d20, d22}, [r8]!" + - + asm_text: "vld4.8 {d16, d17, d18, d19}, [r1:64], r8" + - + asm_text: "vld4.16 {d16, d17, d18, d19}, [r2], r7" + - + asm_text: "vld4.32 {d16, d17, d18, d19}, [r3:64], r5" + - + asm_text: "vld4.8 {d16, d18, d20, d22}, [r4:256], r2" + - + asm_text: "vld4.16 {d16, d18, d20, d22}, [r6], r3" + - + asm_text: "vld4.32 {d17, d19, d21, d23}, [r9], r4" + - + asm_text: "vld1.8 {d4[]}, [r1]" + - + asm_text: "vld1.8 {d4[]}, [r1]!" + - + asm_text: "vld1.8 {d4[]}, [r1], r3" + - + asm_text: "vld1.8 {d4[], d5[]}, [r1]" + - + asm_text: "vld1.8 {d4[], d5[]}, [r1]!" + - + asm_text: "vld1.8 {d4[], d5[]}, [r1], r3" + - + asm_text: "vld1.8 {d16[3]}, [r0]" + - + asm_text: "vld1.16 {d16[2]}, [r0:16]" + - + asm_text: "vld1.32 {d16[1]}, [r0:32]" + - + asm_text: "vld1.8 {d12[6]}, [r2]!" + - + asm_text: "vld1.8 {d12[6]}, [r2], r2" + - + asm_text: "vld1.16 {d12[3]}, [r2]!" + - + asm_text: "vld1.16 {d12[2]}, [r2], r2" + - + asm_text: "vld2.8 {d16[1], d17[1]}, [r0:16]" + - + asm_text: "vld2.16 {d16[1], d17[1]}, [r0:32]" + - + asm_text: "vld2.32 {d16[1], d17[1]}, [r0]" + - + asm_text: "vld2.16 {d17[1], d19[1]}, [r0]" + - + asm_text: "vld2.32 {d17[0], d19[0]}, [r0:64]" + - + asm_text: "vld2.32 {d17[0], d19[0]}, [r0:64]!" + - + asm_text: "vld2.8 {d2[4], d3[4]}, [r2], r3" + - + asm_text: "vld2.8 {d2[4], d3[4]}, [r2]!" + - + asm_text: "vld2.8 {d2[4], d3[4]}, [r2]" + - + asm_text: "vld2.32 {d22[], d23[]}, [r1]" + - + asm_text: "vld2.32 {d22[], d24[]}, [r1]" + - + asm_text: "vld2.32 {d10[], d11[]}, [r3]!" + - + asm_text: "vld2.32 {d14[], d16[]}, [r4]!" + - + asm_text: "vld2.32 {d22[], d23[]}, [r5], r4" + - + asm_text: "vld2.32 {d22[], d24[]}, [r6], r4" + - + asm_text: "vld3.8 {d16[1], d17[1], d18[1]}, [r1]" + - + asm_text: "vld3.16 {d6[1], d7[1], d8[1]}, [r2]" + - + asm_text: "vld3.32 {d1[1], d2[1], d3[1]}, [r3]" + - + asm_text: "vld3.16 {d27[2], d29[2], d31[2]}, [r4]" + - + asm_text: "vld3.32 {d6[0], d8[0], d10[0]}, [r5]" + - + asm_text: "vld3.8 {d12[3], d13[3], d14[3]}, [r6], r1" + - + asm_text: "vld3.16 {d11[2], d12[2], d13[2]}, [r7], r2" + - + asm_text: "vld3.32 {d2[1], d3[1], d4[1]}, [r8], r3" + - + asm_text: "vld3.16 {d14[2], d16[2], d18[2]}, [r9], r4" + - + asm_text: "vld3.32 {d16[0], d18[0], d20[0]}, [r10], r5" + - + asm_text: "vld3.8 {d6[6], d7[6], d8[6]}, [r8]!" + - + asm_text: "vld3.16 {d9[2], d10[2], d11[2]}, [r7]!" + - + asm_text: "vld3.32 {d1[1], d2[1], d3[1]}, [r6]!" + - + asm_text: "vld3.16 {d20[2], d22[2], d24[2]}, [r5]!" + - + asm_text: "vld3.32 {d5[0], d7[0], d9[0]}, [r4]!" + - + asm_text: "vld3.8 {d16[], d17[], d18[]}, [r1]" + - + asm_text: "vld3.16 {d16[], d17[], d18[]}, [r2]" + - + asm_text: "vld3.32 {d16[], d17[], d18[]}, [r3]" + - + asm_text: "vld3.8 {d17[], d19[], d21[]}, [r7]" + - + asm_text: "vld3.16 {d17[], d19[], d21[]}, [r7]" + - + asm_text: "vld3.32 {d16[], d18[], d20[]}, [r8]" + - + asm_text: "vld3.8 {d16[], d17[], d18[]}, [r1]!" + - + asm_text: "vld3.16 {d16[], d17[], d18[]}, [r2]!" + - + asm_text: "vld3.32 {d16[], d17[], d18[]}, [r3]!" + - + asm_text: "vld3.8 {d17[], d19[], d21[]}, [r7]!" + - + asm_text: "vld3.16 {d17[], d19[], d21[]}, [r7]!" + - + asm_text: "vld3.32 {d16[], d18[], d20[]}, [r8]!" + - + asm_text: "vld3.8 {d16[], d17[], d18[]}, [r1], r8" + - + asm_text: "vld3.16 {d16[], d17[], d18[]}, [r2], r7" + - + asm_text: "vld3.32 {d16[], d17[], d18[]}, [r3], r5" + - + asm_text: "vld3.8 {d16[], d18[], d20[]}, [r6], r3" + - + asm_text: "vld3.16 {d16[], d18[], d20[]}, [r6], r3" + - + asm_text: "vld3.32 {d17[], d19[], d21[]}, [r9], r4" + - + asm_text: "vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1]" + - + asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2]" + - + asm_text: "vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3]" + - + asm_text: "vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]" + - + asm_text: "vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]" + - + asm_text: "vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!" + - + asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]!" + - + asm_text: "vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]!" + - + asm_text: "vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!" + - + asm_text: "vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]!" + - + asm_text: "vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8" + - + asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7" + - + asm_text: "vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5" + - + asm_text: "vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3" + - + asm_text: "vld4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4" + - + asm_text: "vld4.8 {d16[], d17[], d18[], d19[]}, [r1]" + - + asm_text: "vld4.16 {d16[], d17[], d18[], d19[]}, [r2]" + - + asm_text: "vld4.32 {d16[], d17[], d18[], d19[]}, [r3]" + - + asm_text: "vld4.8 {d17[], d19[], d21[], d23[]}, [r7]" + - + asm_text: "vld4.16 {d17[], d19[], d21[], d23[]}, [r7]" + - + asm_text: "vld4.32 {d16[], d18[], d20[], d22[]}, [r8]" + - + asm_text: "vld4.8 {d16[], d17[], d18[], d19[]}, [r1]!" + - + asm_text: "vld4.16 {d16[], d17[], d18[], d19[]}, [r2]!" + - + asm_text: "vld4.32 {d16[], d17[], d18[], d19[]}, [r3]!" + - + asm_text: "vld4.8 {d17[], d19[], d21[], d23[]}, [r7]!" + - + asm_text: "vld4.16 {d17[], d19[], d21[], d23[]}, [r7]!" + - + asm_text: "vld4.32 {d16[], d18[], d20[], d22[]}, [r8]!" + - + asm_text: "vld4.8 {d16[], d17[], d18[], d19[]}, [r1], r8" + - + asm_text: "vld4.16 {d16[], d17[], d18[], d19[]}, [r2], r7" + - + asm_text: "vld4.32 {d16[], d17[], d18[], d19[]}, [r3], r5" + - + asm_text: "vld4.8 {d16[], d18[], d20[], d22[]}, [r6], r3" + - + asm_text: "vld4.16 {d16[], d18[], d20[], d22[]}, [r6], r3" + - + asm_text: "vld4.32 {d17[], d19[], d21[], d23[]}, [r9], r4" + - + asm_text: "vld1.8 {d6, d7}, [r9]" + - + asm_text: "vld1.8 {d6, d7, d8, d9}, [r9]" + - + asm_text: "vld1.8 {d2}, [r2]" + - + asm_text: "vld1.8 {d2}, [r2]" + - + asm_text: "vld1.8 {d2}, [r2]" + - + asm_text: "vld1.8 {d4, d5}, [r2]" + - + asm_text: "vld1.8 {d4, d5}, [r2]" + - + asm_text: "vld1.8 {d4, d5}, [r2]" + - + asm_text: "vld1.32 {d4, d5}, [r2]" + - + asm_text: "vld1.8 {d2, d3, d4}, [r2]" + - + asm_text: "vld1.32 {d2, d3, d4}, [r2]" + - + asm_text: "vld1.64 {d2, d3, d4}, [r2]" + - + asm_text: "vld1.64 {d2, d3, d4, d5}, [r2:128]!" + - + asm_text: "vld1.64 {d2, d3, d4, d5}, [r2:128]!" + - + asm_text: "vld2.8 {d16, d17}, [r0:64]" + - + asm_text: "vld2.16 {d16, d17}, [r0:128]" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-vld-vst-align.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-vld-vst-align.s.yaml new file mode 100644 index 0000000..d5a1486 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-vld-vst-align.s.yaml @@ -0,0 +1,1922 @@ +test_cases: + - + input: + bytes: [ 0x24, 0xf9, 0x0f, 0x07, 0x24, 0xf9, 0x1f, 0x07, 0x24, 0xf9, 0x0d, 0x07, 0x24, 0xf9, 0x1d, 0x07, 0x24, 0xf9, 0x06, 0x07, 0x24, 0xf9, 0x16, 0x07, 0x24, 0xf9, 0x0f, 0x0a, 0x24, 0xf9, 0x1f, 0x0a, 0x24, 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0xf9, 0x0d, 0x00, 0x04, 0xf9, 0x1d, 0x00, 0x04, 0xf9, 0x2d, 0x00, 0x04, 0xf9, 0x3d, 0x00, 0x04, 0xf9, 0x06, 0x00, 0x04, 0xf9, 0x16, 0x00, 0x04, 0xf9, 0x26, 0x00, 0x04, 0xf9, 0x36, 0x00, 0x04, 0xf9, 0x0f, 0x01, 0x04, 0xf9, 0x1f, 0x01, 0x04, 0xf9, 0x2f, 0x01, 0x04, 0xf9, 0x3f, 0x01, 0x04, 0xf9, 0x0d, 0x01, 0x04, 0xf9, 0x1d, 0x01, 0x04, 0xf9, 0x2d, 0x01, 0x04, 0xf9, 0x3d, 0x01, 0x04, 0xf9, 0x06, 0x01, 0x04, 0xf9, 0x16, 0x01, 0x04, 0xf9, 0x26, 0x01, 0x04, 0xf9, 0x36, 0x01, 0x84, 0xf9, 0x2f, 0x03, 0x84, 0xf9, 0x3f, 0x03, 0x84, 0xf9, 0x2d, 0x03, 0x84, 0xf9, 0x3d, 0x03, 0x84, 0xf9, 0x26, 0x03, 0x84, 0xf9, 0x36, 0x03, 0x04, 0xf9, 0x4f, 0x00, 0x04, 0xf9, 0x5f, 0x00, 0x04, 0xf9, 0x6f, 0x00, 0x04, 0xf9, 0x7f, 0x00, 0x04, 0xf9, 0x4d, 0x00, 0x04, 0xf9, 0x5d, 0x00, 0x04, 0xf9, 0x6d, 0x00, 0x04, 0xf9, 0x7d, 0x00, 0x04, 0xf9, 0x46, 0x00, 0x04, 0xf9, 0x56, 0x00, 0x04, 0xf9, 0x66, 0x00, 0x04, 0xf9, 0x76, 0x00, 0x04, 0xf9, 0x4f, 0x01, 0x04, 0xf9, 0x5f, 0x01, 0x04, 0xf9, 0x6f, 0x01, 0x04, 0xf9, 0x7f, 0x01, 0x04, 0xf9, 0x4d, 0x01, 0x04, 0xf9, 0x5d, 0x01, 0x04, 0xf9, 0x6d, 0x01, 0x04, 0xf9, 0x7d, 0x01, 0x04, 0xf9, 0x46, 0x01, 0x04, 0xf9, 0x56, 0x01, 0x04, 0xf9, 0x66, 0x01, 0x04, 0xf9, 0x76, 0x01, 0x84, 0xf9, 0x4f, 0x07, 0x84, 0xf9, 0x5f, 0x07, 0x84, 0xf9, 0x4d, 0x07, 0x84, 0xf9, 0x5d, 0x07, 0x84, 0xf9, 0x46, 0x07, 0x84, 0xf9, 0x56, 0x07, 0x84, 0xf9, 0x6f, 0x07, 0x84, 0xf9, 0x7f, 0x07, 0x84, 0xf9, 0x6d, 0x07, 0x84, 0xf9, 0x7d, 0x07, 0x84, 0xf9, 0x66, 0x07, 0x84, 0xf9, 0x76, 0x07, 0x04, 0xf9, 0x8f, 0x00, 0x04, 0xf9, 0x9f, 0x00, 0x04, 0xf9, 0xaf, 0x00, 0x04, 0xf9, 0xbf, 0x00, 0x04, 0xf9, 0x8d, 0x00, 0x04, 0xf9, 0x9d, 0x00, 0x04, 0xf9, 0xad, 0x00, 0x04, 0xf9, 0xbd, 0x00, 0x04, 0xf9, 0x86, 0x00, 0x04, 0xf9, 0x96, 0x00, 0x04, 0xf9, 0xa6, 0x00, 0x04, 0xf9, 0xb6, 0x00, 0x04, 0xf9, 0x8f, 0x01, 0x04, 0xf9, 0x9f, 0x01, 0x04, 0xf9, 0xaf, 0x01, 0x04, 0xf9, 0xbf, 0x01, 0x04, 0xf9, 0x8d, 0x01, 0x04, 0xf9, 0x9d, 0x01, 0x04, 0xf9, 0xad, 0x01, 0x04, 0xf9, 0xbd, 0x01, 0x04, 0xf9, 0x86, 0x01, 0x04, 0xf9, 0x96, 0x01, 0x04, 0xf9, 0xa6, 0x01, 0x04, 0xf9, 0xb6, 0x01, 0x84, 0xf9, 0x8f, 0x0b, 0x84, 0xf9, 0x9f, 0x0b, 0x84, 0xf9, 0xaf, 0x0b, 0x84, 0xf9, 0x8d, 0x0b, 0x84, 0xf9, 0x9d, 0x0b, 0x84, 0xf9, 0xad, 0x0b, 0x84, 0xf9, 0x86, 0x0b, 0x84, 0xf9, 0x96, 0x0b, 0x84, 0xf9, 0xa6, 0x0b, 0x84, 0xf9, 0xcf, 0x0b, 0x84, 0xf9, 0xdf, 0x0b, 0x84, 0xf9, 0xef, 0x0b, 0x84, 0xf9, 0xcd, 0x0b, 0x84, 0xf9, 0xdd, 0x0b, 0x84, 0xf9, 0xed, 0x0b, 0x84, 0xf9, 0xc6, 0x0b, 0x84, 0xf9, 0xd6, 0x0b, 0x84, 0xf9, 0xe6, 0x0b, 0x84, 0xf9, 0x8d, 0x0b, 0x84, 0xf9, 0x9d, 0x0b, 0x84, 0xf9, 0xad, 0x0b, 0x84, 0xf9, 0x86, 0x0b, 0x84, 0xf9, 0x96, 0x0b, 0x84, 0xf9, 0xa6, 0x0b, 0x84, 0xf9, 0xcf, 0x0b, 0x84, 0xf9, 0xdf, 0x0b, 0x84, 0xf9, 0xef, 0x0b, 0x84, 0xf9, 0xcd, 0x0b, 0x84, 0xf9, 0xdd, 0x0b, 0x84, 0xf9, 0xed, 0x0b, 0x84, 0xf9, 0xc6, 0x0b, 0x84, 0xf9, 0xd6, 0x0b, 0x84, 0xf9, 0xe6, 0x0b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vld1.8 {d0}, [r4]" + - + asm_text: "vld1.8 {d0}, [r4:64]" + - + asm_text: "vld1.8 {d0}, [r4]!" + - + asm_text: "vld1.8 {d0}, [r4:64]!" + - + asm_text: "vld1.8 {d0}, [r4], r6" + - + asm_text: "vld1.8 {d0}, [r4:64], r6" + - + asm_text: "vld1.8 {d0, d1}, [r4]" + - + asm_text: "vld1.8 {d0, d1}, [r4:64]" + - + asm_text: "vld1.8 {d0, d1}, [r4:128]" + - + asm_text: "vld1.8 {d0, d1}, [r4]!" + - + asm_text: "vld1.8 {d0, d1}, [r4:64]!" + - + asm_text: "vld1.8 {d0, d1}, [r4:128]!" + - + asm_text: "vld1.8 {d0, d1}, [r4], r6" + - + asm_text: "vld1.8 {d0, d1}, [r4:64], r6" + - + asm_text: "vld1.8 {d0, d1}, [r4:128], r6" + - + asm_text: "vld1.8 {d0, d1, d2}, [r4]" + - + asm_text: "vld1.8 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld1.8 {d0, d1, d2}, [r4]!" + - + asm_text: "vld1.8 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld1.8 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld1.8 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld1.8 {d0[2]}, [r4]" + - + asm_text: "vld1.8 {d0[2]}, [r4]!" + - + asm_text: "vld1.8 {d0[2]}, [r4], r6" + - + asm_text: "vld1.8 {d0[]}, [r4]" + - + asm_text: "vld1.8 {d0[]}, [r4]!" + - + asm_text: "vld1.8 {d0[]}, [r4], r6" + - + asm_text: "vld1.8 {d0[], d1[]}, [r4]" + - + asm_text: "vld1.8 {d0[], d1[]}, [r4]!" + - + asm_text: "vld1.8 {d0[], d1[]}, [r4], r6" + - + asm_text: "vld1.16 {d0}, [r4]" + - + asm_text: "vld1.16 {d0}, [r4:64]" + - + asm_text: "vld1.16 {d0}, [r4]!" + - + asm_text: "vld1.16 {d0}, [r4:64]!" + - + asm_text: "vld1.16 {d0}, [r4], r6" + - + asm_text: "vld1.16 {d0}, [r4:64], r6" + - + asm_text: "vld1.16 {d0, d1}, [r4]" + - + asm_text: "vld1.16 {d0, d1}, [r4:64]" + - + asm_text: "vld1.16 {d0, d1}, [r4:128]" + - + asm_text: "vld1.16 {d0, d1}, [r4]!" + - + asm_text: "vld1.16 {d0, d1}, [r4:64]!" + - + asm_text: "vld1.16 {d0, d1}, [r4:128]!" + - + asm_text: "vld1.16 {d0, d1}, [r4], r6" + - + asm_text: "vld1.16 {d0, d1}, [r4:64], r6" + - + asm_text: "vld1.16 {d0, d1}, [r4:128], r6" + - + asm_text: "vld1.16 {d0, d1, d2}, [r4]" + - + asm_text: "vld1.16 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld1.16 {d0, d1, d2}, [r4]!" + - + asm_text: "vld1.16 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld1.16 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld1.16 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld1.16 {d0[2]}, [r4]" + - + asm_text: "vld1.16 {d0[2]}, [r4:16]" + - + asm_text: "vld1.16 {d0[2]}, [r4]!" + - + asm_text: "vld1.16 {d0[2]}, [r4:16]!" + - + asm_text: "vld1.16 {d0[2]}, [r4], r6" + - + asm_text: "vld1.16 {d0[2]}, [r4:16], r6" + - + asm_text: "vld1.16 {d0[]}, [r4]" + - + asm_text: "vld1.16 {d0[]}, [r4:16]" + - + asm_text: "vld1.16 {d0[]}, [r4]!" + - + asm_text: "vld1.16 {d0[]}, [r4:16]!" + - + asm_text: "vld1.16 {d0[]}, [r4], r6" + - + asm_text: "vld1.16 {d0[]}, [r4:16], r6" + - + asm_text: "vld1.16 {d0[], d1[]}, [r4]" + - + asm_text: "vld1.16 {d0[], d1[]}, [r4:16]" + - + asm_text: "vld1.16 {d0[], d1[]}, [r4]!" + - + asm_text: "vld1.16 {d0[], d1[]}, [r4:16]!" + - + asm_text: "vld1.16 {d0[], d1[]}, [r4], r6" + - + asm_text: "vld1.16 {d0[], d1[]}, [r4:16], r6" + - + asm_text: "vld1.32 {d0}, [r4]" + - + asm_text: "vld1.32 {d0}, [r4:64]" + - + asm_text: "vld1.32 {d0}, [r4]!" + - + asm_text: "vld1.32 {d0}, [r4:64]!" + - + asm_text: "vld1.32 {d0}, [r4], r6" + - + asm_text: "vld1.32 {d0}, [r4:64], r6" + - + asm_text: "vld1.32 {d0, d1}, [r4]" + - + asm_text: "vld1.32 {d0, d1}, [r4:64]" + - + asm_text: "vld1.32 {d0, d1}, [r4:128]" + - + asm_text: "vld1.32 {d0, d1}, [r4]!" + - + asm_text: "vld1.32 {d0, d1}, [r4:64]!" + - + asm_text: "vld1.32 {d0, d1}, [r4:128]!" + - + asm_text: "vld1.32 {d0, d1}, [r4], r6" + - + asm_text: "vld1.32 {d0, d1}, [r4:64], r6" + - + asm_text: "vld1.32 {d0, d1}, [r4:128], r6" + - + asm_text: "vld1.32 {d0, d1, d2}, [r4]" + - + asm_text: "vld1.32 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld1.32 {d0, d1, d2}, [r4]!" + - + asm_text: "vld1.32 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld1.32 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld1.32 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld1.32 {d0[1]}, [r4]" + - + asm_text: "vld1.32 {d0[1]}, [r4:32]" + - + asm_text: "vld1.32 {d0[1]}, [r4]!" + - + asm_text: "vld1.32 {d0[1]}, [r4:32]!" + - + asm_text: "vld1.32 {d0[1]}, [r4], r6" + - + asm_text: "vld1.32 {d0[1]}, [r4:32], r6" + - + asm_text: "vld1.32 {d0[]}, [r4]" + - + asm_text: "vld1.32 {d0[]}, [r4:32]" + - + asm_text: "vld1.32 {d0[]}, [r4]!" + - + asm_text: "vld1.32 {d0[]}, [r4:32]!" + - + asm_text: "vld1.32 {d0[]}, [r4], r6" + - + asm_text: "vld1.32 {d0[]}, [r4:32], r6" + - + asm_text: "vld1.32 {d0[], d1[]}, [r4]" + - + asm_text: "vld1.32 {d0[], d1[]}, [r4:32]" + - + asm_text: "vld1.32 {d0[], d1[]}, [r4]!" + - + asm_text: "vld1.32 {d0[], d1[]}, [r4:32]!" + - + asm_text: "vld1.32 {d0[], d1[]}, [r4], r6" + - + asm_text: "vld1.32 {d0[], d1[]}, [r4:32], r6" + - + asm_text: "vld1.32 {d0[1]}, [r4]" + - + asm_text: "vld1.32 {d0[1]}, [r4:32]" + - + asm_text: "vld1.32 {d0[1]}, [r4]!" + - + asm_text: "vld1.32 {d0[1]}, [r4:32]!" + - + asm_text: "vld1.32 {d0[1]}, [r4], r6" + - + asm_text: "vld1.32 {d0[1]}, [r4:32], r6" + - + asm_text: "vld1.64 {d0}, [r4]" + - + asm_text: "vld1.64 {d0}, [r4:64]" + - + asm_text: "vld1.64 {d0}, [r4]!" + - + asm_text: "vld1.64 {d0}, [r4:64]!" + - + asm_text: "vld1.64 {d0}, [r4], r6" + - + asm_text: "vld1.64 {d0}, [r4:64], r6" + - + asm_text: "vld1.64 {d0, d1}, [r4]" + - + asm_text: "vld1.64 {d0, d1}, [r4:64]" + - + asm_text: "vld1.64 {d0, d1}, [r4:128]" + - + asm_text: "vld1.64 {d0, d1}, [r4]!" + - + asm_text: "vld1.64 {d0, d1}, [r4:64]!" + - + asm_text: "vld1.64 {d0, d1}, [r4:128]!" + - + asm_text: "vld1.64 {d0, d1}, [r4], r6" + - + asm_text: "vld1.64 {d0, d1}, [r4:64], r6" + - + asm_text: "vld1.64 {d0, d1}, [r4:128], r6" + - + asm_text: "vld1.64 {d0, d1, d2}, [r4]" + - + asm_text: "vld1.64 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld1.64 {d0, d1, d2}, [r4]!" + - + asm_text: "vld1.64 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld1.64 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld1.64 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld2.8 {d0, d1}, [r4]" + - + asm_text: "vld2.8 {d0, d1}, [r4:64]" + - + asm_text: "vld2.8 {d0, d1}, [r4:128]" + - + asm_text: "vld2.8 {d0, d1}, [r4]!" + - + asm_text: "vld2.8 {d0, d1}, [r4:64]!" + - + asm_text: "vld2.8 {d0, d1}, [r4:128]!" + - + asm_text: "vld2.8 {d0, d1}, [r4], r6" + - + asm_text: "vld2.8 {d0, d1}, [r4:64], r6" + - + asm_text: "vld2.8 {d0, d1}, [r4:128], r6" + - + asm_text: "vld2.8 {d0, d2}, [r4]" + - + asm_text: "vld2.8 {d0, d2}, [r4:64]" + - + asm_text: "vld2.8 {d0, d2}, [r4:128]" + - + asm_text: "vld2.8 {d0, d2}, [r4]!" + - + asm_text: "vld2.8 {d0, d2}, [r4:64]!" + - + asm_text: "vld2.8 {d0, d2}, [r4:128]!" + - + asm_text: "vld2.8 {d0, d2}, [r4], r6" + - + asm_text: "vld2.8 {d0, d2}, [r4:64], r6" + - + asm_text: "vld2.8 {d0, d2}, [r4:128], r6" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld2.8 {d0[2], d1[2]}, [r4]" + - + asm_text: "vld2.8 {d0[2], d1[2]}, [r4:16]" + - + asm_text: "vld2.8 {d0[2], d1[2]}, [r4]!" + - + asm_text: "vld2.8 {d0[2], d1[2]}, [r4:16]!" + - + asm_text: "vld2.8 {d0[2], d1[2]}, [r4], r6" + - + asm_text: "vld2.8 {d0[2], d1[2]}, [r4:16], r6" + - + asm_text: "vld2.8 {d0[], d1[]}, [r4]" + - + asm_text: "vld2.8 {d0[], d1[]}, [r4:16]" + - + asm_text: "vld2.8 {d0[], d1[]}, [r4]!" + - + asm_text: "vld2.8 {d0[], d1[]}, [r4:16]!" + - + asm_text: "vld2.8 {d0[], d1[]}, [r4], r6" + - + asm_text: "vld2.8 {d0[], d1[]}, [r4:16], r6" + - + asm_text: "vld2.8 {d0[], d2[]}, [r4]" + - + asm_text: "vld2.8 {d0[], d2[]}, [r4:16]" + - + asm_text: "vld2.8 {d0[], d2[]}, [r4]!" + - + asm_text: "vld2.8 {d0[], d2[]}, [r4:16]!" + - + asm_text: "vld2.8 {d0[], d2[]}, [r4], r6" + - + asm_text: "vld2.8 {d0[], d2[]}, [r4:16], r6" + - + asm_text: "vld2.16 {d0, d1}, [r4]" + - + asm_text: "vld2.16 {d0, d1}, [r4:64]" + - + asm_text: "vld2.16 {d0, d1}, [r4:128]" + - + asm_text: "vld2.16 {d0, d1}, [r4]!" + - + asm_text: "vld2.16 {d0, d1}, [r4:64]!" + - + asm_text: "vld2.16 {d0, d1}, [r4:128]!" + - + asm_text: "vld2.16 {d0, d1}, [r4], r6" + - + asm_text: "vld2.16 {d0, d1}, [r4:64], r6" + - + asm_text: "vld2.16 {d0, d1}, [r4:128], r6" + - + asm_text: "vld2.16 {d0, d2}, [r4]" + - + asm_text: "vld2.16 {d0, d2}, [r4:64]" + - + asm_text: "vld2.16 {d0, d2}, [r4:128]" + - + asm_text: "vld2.16 {d0, d2}, [r4]!" + - + asm_text: "vld2.16 {d0, d2}, [r4:64]!" + - + asm_text: "vld2.16 {d0, d2}, [r4:128]!" + - + asm_text: "vld2.16 {d0, d2}, [r4], r6" + - + asm_text: "vld2.16 {d0, d2}, [r4:64], r6" + - + asm_text: "vld2.16 {d0, d2}, [r4:128], r6" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld2.16 {d0[2], d1[2]}, [r4]" + - + asm_text: "vld2.16 {d0[2], d1[2]}, [r4:32]" + - + asm_text: "vld2.16 {d0[2], d1[2]}, [r4]!" + - + asm_text: "vld2.16 {d0[2], d1[2]}, [r4:32]!" + - + asm_text: "vld2.16 {d0[2], d1[2]}, [r4], r6" + - + asm_text: "vld2.16 {d0[2], d1[2]}, [r4:32], r6" + - + asm_text: "vld2.16 {d0[2], d2[2]}, [r4]" + - + asm_text: "vld2.16 {d0[2], d2[2]}, [r4:32]" + - + asm_text: "vld2.16 {d0[2], d2[2]}, [r4]!" + - + asm_text: "vld2.16 {d0[2], d2[2]}, [r4:32]!" + - + asm_text: "vld2.16 {d0[2], d2[2]}, [r4], r6" + - + asm_text: "vld2.16 {d0[2], d2[2]}, [r4:32], r6" + - + asm_text: "vld2.16 {d0[], d1[]}, [r4]" + - + asm_text: "vld2.16 {d0[], d1[]}, [r4:32]" + - + asm_text: "vld2.16 {d0[], d1[]}, [r4]!" + - + asm_text: "vld2.16 {d0[], d1[]}, [r4:32]!" + - + asm_text: "vld2.16 {d0[], d1[]}, [r4], r6" + - + asm_text: "vld2.16 {d0[], d1[]}, [r4:32], r6" + - + asm_text: "vld2.16 {d0[], d2[]}, [r4]" + - + asm_text: "vld2.16 {d0[], d2[]}, [r4:32]" + - + asm_text: "vld2.16 {d0[], d2[]}, [r4]!" + - + asm_text: "vld2.16 {d0[], d2[]}, [r4:32]!" + - + asm_text: "vld2.16 {d0[], d2[]}, [r4], r6" + - + asm_text: "vld2.16 {d0[], d2[]}, [r4:32], r6" + - + asm_text: "vld2.32 {d0, d1}, [r4]" + - + asm_text: "vld2.32 {d0, d1}, [r4:64]" + - + asm_text: "vld2.32 {d0, d1}, [r4:128]" + - + asm_text: "vld2.32 {d0, d1}, [r4]!" + - + asm_text: "vld2.32 {d0, d1}, [r4:64]!" + - + asm_text: "vld2.32 {d0, d1}, [r4:128]!" + - + asm_text: "vld2.32 {d0, d1}, [r4], r6" + - + asm_text: "vld2.32 {d0, d1}, [r4:64], r6" + - + asm_text: "vld2.32 {d0, d1}, [r4:128], r6" + - + asm_text: "vld2.32 {d0, d2}, [r4]" + - + asm_text: "vld2.32 {d0, d2}, [r4:64]" + - + asm_text: "vld2.32 {d0, d2}, [r4:128]" + - + asm_text: "vld2.32 {d0, d2}, [r4]!" + - + asm_text: "vld2.32 {d0, d2}, [r4:64]!" + - + asm_text: "vld2.32 {d0, d2}, [r4:128]!" + - + asm_text: "vld2.32 {d0, d2}, [r4], r6" + - + asm_text: "vld2.32 {d0, d2}, [r4:64], r6" + - + asm_text: "vld2.32 {d0, d2}, [r4:128], r6" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld2.32 {d0[1], d1[1]}, [r4]" + - + asm_text: "vld2.32 {d0[1], d1[1]}, [r4:64]" + - + asm_text: "vld2.32 {d0[1], d1[1]}, [r4]!" + - + asm_text: "vld2.32 {d0[1], d1[1]}, [r4:64]!" + - + asm_text: "vld2.32 {d0[1], d1[1]}, [r4], r6" + - + asm_text: "vld2.32 {d0[1], d1[1]}, [r4:64], r6" + - + asm_text: "vld2.32 {d0[1], d2[1]}, [r4]" + - + asm_text: "vld2.32 {d0[1], d2[1]}, [r4:64]" + - + asm_text: "vld2.32 {d0[1], d2[1]}, [r4]!" + - + asm_text: "vld2.32 {d0[1], d2[1]}, [r4:64]!" + - + asm_text: "vld2.32 {d0[1], d2[1]}, [r4], r6" + - + asm_text: "vld2.32 {d0[1], d2[1]}, [r4:64], r6" + - + asm_text: "vld2.32 {d0[], d1[]}, [r4]" + - + asm_text: "vld2.32 {d0[], d1[]}, [r4:64]" + - + asm_text: "vld2.32 {d0[], d1[]}, [r4]!" + - + asm_text: "vld2.32 {d0[], d1[]}, [r4:64]!" + - + asm_text: "vld2.32 {d0[], d1[]}, [r4], r6" + - + asm_text: "vld2.32 {d0[], d1[]}, [r4:64], r6" + - + asm_text: "vld2.32 {d0[], d2[]}, [r4]" + - + asm_text: "vld2.32 {d0[], d2[]}, [r4:64]" + - + asm_text: "vld2.32 {d0[], d2[]}, [r4]!" + - + asm_text: "vld2.32 {d0[], d2[]}, [r4:64]!" + - + asm_text: "vld2.32 {d0[], d2[]}, [r4], r6" + - + asm_text: "vld2.32 {d0[], d2[]}, [r4:64], r6" + - + asm_text: "vld3.8 {d0, d1, d2}, [r4]" + - + asm_text: "vld3.8 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld3.8 {d0, d1, d2}, [r4]!" + - + asm_text: "vld3.8 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld3.8 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld3.8 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld3.8 {d0, d2, d4}, [r4]" + - + asm_text: "vld3.8 {d0, d2, d4}, [r4:64]" + - + asm_text: "vld3.8 {d0, d2, d4}, [r4]!" + - + asm_text: "vld3.8 {d0, d2, d4}, [r4:64]!" + - + asm_text: "vld3.8 {d0, d2, d4}, [r4], r6" + - + asm_text: "vld3.8 {d0, d2, d4}, [r4:64], r6" + - + asm_text: "vld3.8 {d0[1], d1[1], d2[1]}, [r4]" + - + asm_text: "vld3.8 {d0[1], d1[1], d2[1]}, [r4]!" + - + asm_text: "vld3.8 {d0[1], d1[1], d2[1]}, [r4], r6" + - + asm_text: "vld3.8 {d0[], d1[], d2[]}, [r4]" + - + asm_text: "vld3.8 {d0[], d1[], d2[]}, [r4]!" + - + asm_text: "vld3.8 {d0[], d1[], d2[]}, [r4], r6" + - + asm_text: "vld3.8 {d0[], d2[], d4[]}, [r4]" + - + asm_text: "vld3.8 {d0[], d2[], d4[]}, [r4]!" + - + asm_text: "vld3.8 {d0[], d2[], d4[]}, [r4], r6" + - + asm_text: "vld3.16 {d0, d1, d2}, [r4]" + - + asm_text: "vld3.16 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld3.16 {d0, d1, d2}, [r4]!" + - + asm_text: "vld3.16 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld3.16 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld3.16 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld3.16 {d0, d2, d4}, [r4]" + - + asm_text: "vld3.16 {d0, d2, d4}, [r4:64]" + - + asm_text: "vld3.16 {d0, d2, d4}, [r4]!" + - + asm_text: "vld3.16 {d0, d2, d4}, [r4:64]!" + - + asm_text: "vld3.16 {d0, d2, d4}, [r4], r6" + - + asm_text: "vld3.16 {d0, d2, d4}, [r4:64], r6" + - + asm_text: "vld3.16 {d0[1], d1[1], d2[1]}, [r4]" + - + asm_text: "vld3.16 {d0[1], d1[1], d2[1]}, [r4]!" + - + asm_text: "vld3.16 {d0[1], d1[1], d2[1]}, [r4], r6" + - + asm_text: "vld3.16 {d0[1], d2[1], d4[1]}, [r4]" + - + asm_text: "vld3.16 {d0[1], d2[1], d4[1]}, [r4]!" + - + asm_text: "vld3.16 {d0[1], d2[1], d4[1]}, [r4], r6" + - + asm_text: "vld3.16 {d0[], d1[], d2[]}, [r4]" + - + asm_text: "vld3.16 {d0[], d1[], d2[]}, [r4]!" + - + asm_text: "vld3.16 {d0[], d1[], d2[]}, [r4], r6" + - + asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4]" + - + asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4]!" + - + asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4], r6" + - + asm_text: "vld3.32 {d0, d1, d2}, [r4]" + - + asm_text: "vld3.32 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld3.32 {d0, d1, d2}, [r4]!" + - + asm_text: "vld3.32 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld3.32 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld3.32 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld3.32 {d0, d2, d4}, [r4]" + - + asm_text: "vld3.32 {d0, d2, d4}, [r4:64]" + - + asm_text: "vld3.32 {d0, d2, d4}, [r4]!" + - + asm_text: "vld3.32 {d0, d2, d4}, [r4:64]!" + - + asm_text: "vld3.32 {d0, d2, d4}, [r4], r6" + - + asm_text: "vld3.32 {d0, d2, d4}, [r4:64], r6" + - + asm_text: "vld3.32 {d0[1], d1[1], d2[1]}, [r4]" + - + asm_text: "vld3.32 {d0[1], d1[1], d2[1]}, [r4]!" + - + asm_text: "vld3.32 {d0[1], d1[1], d2[1]}, [r4], r6" + - + asm_text: "vld3.32 {d0[1], d2[1], d4[1]}, [r4]" + - + asm_text: "vld3.32 {d0[1], d2[1], d4[1]}, [r4]!" + - + asm_text: "vld3.32 {d0[1], d2[1], d4[1]}, [r4], r6" + - + asm_text: "vld3.32 {d0[], d1[], d2[]}, [r4]" + - + asm_text: "vld3.32 {d0[], d1[], d2[]}, [r4]!" + - + asm_text: "vld3.32 {d0[], d1[], d2[]}, [r4], r6" + - + asm_text: "vld3.32 {d0[], d2[], d4[]}, [r4]" + - + asm_text: "vld3.32 {d0[], d2[], d4[]}, [r4]!" + - + asm_text: "vld3.32 {d0[], d2[], d4[]}, [r4], r6" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4]" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:64]" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:128]" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:256]" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4]!" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:64]!" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:128]!" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:256]!" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4], r6" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:64], r6" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:128], r6" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:256], r6" + - + asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]" + - + asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]" + - + asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!" + - + asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6" + - + asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4]" + - + asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]" + - + asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4]!" + - + asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]!" + - + asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4], r6" + - + asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32], r6" + - + asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4]" + - + asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]" + - + asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4]!" + - + asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]!" + - + asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4], r6" + - + asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r6" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4]" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:64]" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:128]" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:256]" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4]!" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:64]!" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:128]!" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:256]!" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4], r6" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:64], r6" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:128], r6" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:256], r6" + - + asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]" + - + asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]" + - + asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!" + - + asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6" + - + asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]" + - + asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]" + - + asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]!" + - + asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!" + - + asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6" + - + asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6" + - + asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4]" + - + asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]" + - + asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4]!" + - + asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]!" + - + asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4], r6" + - + asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64], r6" + - + asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4]" + - + asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]" + - + asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4]!" + - + asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]!" + - + asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4], r6" + - + asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r6" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4]" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:64]" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:128]" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:256]" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4]!" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:64]!" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:128]!" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:256]!" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4], r6" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:64], r6" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:128], r6" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:256], r6" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4]" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4]!" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]!" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]!" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4], r6" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64], r6" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128], r6" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4]" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4]!" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]!" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]!" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4], r6" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64], r6" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r6" + - + asm_text: "vst1.8 {d0}, [r4]" + - + asm_text: "vst1.8 {d0}, [r4:64]" + - + asm_text: "vst1.8 {d0}, [r4]!" + - + asm_text: "vst1.8 {d0}, [r4:64]!" + - + asm_text: "vst1.8 {d0}, [r4], r6" + - + asm_text: "vst1.8 {d0}, [r4:64], r6" + - + asm_text: "vst1.8 {d0, d1}, [r4]" + - + asm_text: "vst1.8 {d0, d1}, [r4:64]" + - + asm_text: "vst1.8 {d0, d1}, [r4:128]" + - + asm_text: "vst1.8 {d0, d1}, [r4]!" + - + asm_text: "vst1.8 {d0, d1}, [r4:64]!" + - + asm_text: "vst1.8 {d0, d1}, [r4:128]!" + - + asm_text: "vst1.8 {d0, d1}, [r4], r6" + - + asm_text: "vst1.8 {d0, d1}, [r4:64], r6" + - + asm_text: "vst1.8 {d0, d1}, [r4:128], r6" + - + asm_text: "vst1.8 {d0, d1, d2}, [r4]" + - + asm_text: "vst1.8 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst1.8 {d0, d1, d2}, [r4]!" + - + asm_text: "vst1.8 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst1.8 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst1.8 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst1.8 {d0[2]}, [r4]" + - + asm_text: "vst1.8 {d0[2]}, [r4]!" + - + asm_text: "vst1.8 {d0[2]}, [r4], r6" + - + asm_text: "vst1.16 {d0}, [r4]" + - + asm_text: "vst1.16 {d0}, [r4:64]" + - + asm_text: "vst1.16 {d0}, [r4]!" + - + asm_text: "vst1.16 {d0}, [r4:64]!" + - + asm_text: "vst1.16 {d0}, [r4], r6" + - + asm_text: "vst1.16 {d0}, [r4:64], r6" + - + asm_text: "vst1.16 {d0, d1}, [r4]" + - + asm_text: "vst1.16 {d0, d1}, [r4:64]" + - + asm_text: "vst1.16 {d0, d1}, [r4:128]" + - + asm_text: "vst1.16 {d0, d1}, [r4]!" + - + asm_text: "vst1.16 {d0, d1}, [r4:64]!" + - + asm_text: "vst1.16 {d0, d1}, [r4:128]!" + - + asm_text: "vst1.16 {d0, d1}, [r4], r6" + - + asm_text: "vst1.16 {d0, d1}, [r4:64], r6" + - + asm_text: "vst1.16 {d0, d1}, [r4:128], r6" + - + asm_text: "vst1.16 {d0, d1, d2}, [r4]" + - + asm_text: "vst1.16 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst1.16 {d0, d1, d2}, [r4]!" + - + asm_text: "vst1.16 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst1.16 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst1.16 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst1.16 {d0[2]}, [r4]" + - + asm_text: "vst1.16 {d0[2]}, [r4:16]" + - + asm_text: "vst1.16 {d0[2]}, [r4]!" + - + asm_text: "vst1.16 {d0[2]}, [r4:16]!" + - + asm_text: "vst1.16 {d0[2]}, [r4], r6" + - + asm_text: "vst1.16 {d0[2]}, [r4:16], r6" + - + asm_text: "vst1.32 {d0}, [r4]" + - + asm_text: "vst1.32 {d0}, [r4:64]" + - + asm_text: "vst1.32 {d0}, [r4]!" + - + asm_text: "vst1.32 {d0}, [r4:64]!" + - + asm_text: "vst1.32 {d0}, [r4], r6" + - + asm_text: "vst1.32 {d0}, [r4:64], r6" + - + asm_text: "vst1.32 {d0, d1}, [r4]" + - + asm_text: "vst1.32 {d0, d1}, [r4:64]" + - + asm_text: "vst1.32 {d0, d1}, [r4:128]" + - + asm_text: "vst1.32 {d0, d1}, [r4]!" + - + asm_text: "vst1.32 {d0, d1}, [r4:64]!" + - + asm_text: "vst1.32 {d0, d1}, [r4:128]!" + - + asm_text: "vst1.32 {d0, d1}, [r4], r6" + - + asm_text: "vst1.32 {d0, d1}, [r4:64], r6" + - + asm_text: "vst1.32 {d0, d1}, [r4:128], r6" + - + asm_text: "vst1.32 {d0, d1, d2}, [r4]" + - + asm_text: "vst1.32 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst1.32 {d0, d1, d2}, [r4]!" + - + asm_text: "vst1.32 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst1.32 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst1.32 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst1.32 {d0[1]}, [r4]" + - + asm_text: "vst1.32 {d0[1]}, [r4:32]" + - + asm_text: "vst1.32 {d0[1]}, [r4]!" + - + asm_text: "vst1.32 {d0[1]}, [r4:32]!" + - + asm_text: "vst1.32 {d0[1]}, [r4], r6" + - + asm_text: "vst1.32 {d0[1]}, [r4:32], r6" + - + asm_text: "vst1.64 {d0}, [r4]" + - + asm_text: "vst1.64 {d0}, [r4:64]" + - + asm_text: "vst1.64 {d0}, [r4]!" + - + asm_text: "vst1.64 {d0}, [r4:64]!" + - + asm_text: "vst1.64 {d0}, [r4], r6" + - + asm_text: "vst1.64 {d0}, [r4:64], r6" + - + asm_text: "vst1.64 {d0, d1}, [r4]" + - + asm_text: "vst1.64 {d0, d1}, [r4:64]" + - + asm_text: "vst1.64 {d0, d1}, [r4:128]" + - + asm_text: "vst1.64 {d0, d1}, [r4]!" + - + asm_text: "vst1.64 {d0, d1}, [r4:64]!" + - + asm_text: "vst1.64 {d0, d1}, [r4:128]!" + - + asm_text: "vst1.64 {d0, d1}, [r4], r6" + - + asm_text: "vst1.64 {d0, d1}, [r4:64], r6" + - + asm_text: "vst1.64 {d0, d1}, [r4:128], r6" + - + asm_text: "vst1.64 {d0, d1, d2}, [r4]" + - + asm_text: "vst1.64 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst1.64 {d0, d1, d2}, [r4]!" + - + asm_text: "vst1.64 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst1.64 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst1.64 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst1.64 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst1.64 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst1.64 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst2.8 {d0, d1}, [r4]" + - + asm_text: "vst2.8 {d0, d1}, [r4:64]" + - + asm_text: "vst2.8 {d0, d1}, [r4:128]" + - + asm_text: "vst2.8 {d0, d1}, [r4]!" + - + asm_text: "vst2.8 {d0, d1}, [r4:64]!" + - + asm_text: "vst2.8 {d0, d1}, [r4:128]!" + - + asm_text: "vst2.8 {d0, d1}, [r4], r6" + - + asm_text: "vst2.8 {d0, d1}, [r4:64], r6" + - + asm_text: "vst2.8 {d0, d1}, [r4:128], r6" + - + asm_text: "vst2.8 {d0, d2}, [r4]" + - + asm_text: "vst2.8 {d0, d2}, [r4:64]" + - + asm_text: "vst2.8 {d0, d2}, [r4:128]" + - + asm_text: "vst2.8 {d0, d2}, [r4]!" + - + asm_text: "vst2.8 {d0, d2}, [r4:64]!" + - + asm_text: "vst2.8 {d0, d2}, [r4:128]!" + - + asm_text: "vst2.8 {d0, d2}, [r4], r6" + - + asm_text: "vst2.8 {d0, d2}, [r4:64], r6" + - + asm_text: "vst2.8 {d0, d2}, [r4:128], r6" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst2.8 {d0[2], d1[2]}, [r4]" + - + asm_text: "vst2.8 {d0[2], d1[2]}, [r4:16]" + - + asm_text: "vst2.8 {d0[2], d1[2]}, [r4]!" + - + asm_text: "vst2.8 {d0[2], d1[2]}, [r4:16]!" + - + asm_text: "vst2.8 {d0[2], d1[2]}, [r4], r6" + - + asm_text: "vst2.8 {d0[2], d1[2]}, [r4:16], r6" + - + asm_text: "vst2.32 {d0, d1}, [r4]" + - + asm_text: "vst2.32 {d0, d1}, [r4:64]" + - + asm_text: "vst2.32 {d0, d1}, [r4:128]" + - + asm_text: "vst2.32 {d0, d1}, [r4]!" + - + asm_text: "vst2.32 {d0, d1}, [r4:64]!" + - + asm_text: "vst2.32 {d0, d1}, [r4:128]!" + - + asm_text: "vst2.32 {d0, d1}, [r4], r6" + - + asm_text: "vst2.32 {d0, d1}, [r4:64], r6" + - + asm_text: "vst2.32 {d0, d1}, [r4:128], r6" + - + asm_text: "vst2.32 {d0, d2}, [r4]" + - + asm_text: "vst2.32 {d0, d2}, [r4:64]" + - + asm_text: "vst2.32 {d0, d2}, [r4:128]" + - + asm_text: "vst2.32 {d0, d2}, [r4]!" + - + asm_text: "vst2.32 {d0, d2}, [r4:64]!" + - + asm_text: "vst2.32 {d0, d2}, [r4:128]!" + - + asm_text: "vst2.32 {d0, d2}, [r4], r6" + - + asm_text: "vst2.32 {d0, d2}, [r4:64], r6" + - + asm_text: "vst2.32 {d0, d2}, [r4:128], r6" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst2.32 {d0[1], d1[1]}, [r4]" + - + asm_text: "vst2.32 {d0[1], d1[1]}, [r4:64]" + - + asm_text: "vst2.32 {d0[1], d1[1]}, [r4]!" + - + asm_text: "vst2.32 {d0[1], d1[1]}, [r4:64]!" + - + asm_text: "vst2.32 {d0[1], d1[1]}, [r4], r6" + - + asm_text: "vst2.32 {d0[1], d1[1]}, [r4:64], r6" + - + asm_text: "vst2.32 {d0[1], d2[1]}, [r4]" + - + asm_text: "vst2.32 {d0[1], d2[1]}, [r4:64]" + - + asm_text: "vst2.32 {d0[1], d2[1]}, [r4]!" + - + asm_text: "vst2.32 {d0[1], d2[1]}, [r4:64]!" + - + asm_text: "vst2.32 {d0[1], d2[1]}, [r4], r6" + - + asm_text: "vst2.32 {d0[1], d2[1]}, [r4:64], r6" + - + asm_text: "vst3.8 {d0, d1, d2}, [r4]" + - + asm_text: "vst3.8 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst3.8 {d0, d1, d2}, [r4]!" + - + asm_text: "vst3.8 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst3.8 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst3.8 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst3.8 {d0, d2, d4}, [r4]" + - + asm_text: "vst3.8 {d0, d2, d4}, [r4:64]" + - + asm_text: "vst3.8 {d0, d2, d4}, [r4]!" + - + asm_text: "vst3.8 {d0, d2, d4}, [r4:64]!" + - + asm_text: "vst3.8 {d0, d2, d4}, [r4], r6" + - + asm_text: "vst3.8 {d0, d2, d4}, [r4:64], r6" + - + asm_text: "vst3.8 {d0[1], d1[1], d2[1]}, [r4]" + - + asm_text: "vst3.8 {d0[1], d1[1], d2[1]}, [r4]!" + - + asm_text: "vst3.8 {d0[1], d1[1], d2[1]}, [r4], r6" + - + asm_text: "vst3.16 {d0, d1, d2}, [r4]" + - + asm_text: "vst3.16 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst3.16 {d0, d1, d2}, [r4]!" + - + asm_text: "vst3.16 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst3.16 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst3.16 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst3.16 {d0, d2, d4}, [r4]" + - + asm_text: "vst3.16 {d0, d2, d4}, [r4:64]" + - + asm_text: "vst3.16 {d0, d2, d4}, [r4]!" + - + asm_text: "vst3.16 {d0, d2, d4}, [r4:64]!" + - + asm_text: "vst3.16 {d0, d2, d4}, [r4], r6" + - + asm_text: "vst3.16 {d0, d2, d4}, [r4:64], r6" + - + asm_text: "vst3.16 {d0[1], d1[1], d2[1]}, [r4]" + - + asm_text: "vst3.16 {d0[1], d1[1], d2[1]}, [r4]!" + - + asm_text: "vst3.16 {d0[1], d1[1], d2[1]}, [r4], r6" + - + asm_text: "vst3.16 {d0[1], d2[1], d4[1]}, [r4]" + - + asm_text: "vst3.16 {d0[1], d2[1], d4[1]}, [r4]!" + - + asm_text: "vst3.16 {d0[1], d2[1], d4[1]}, [r4], r6" + - + asm_text: "vst3.32 {d0, d1, d2}, [r4]" + - + asm_text: "vst3.32 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst3.32 {d0, d1, d2}, [r4]!" + - + asm_text: "vst3.32 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst3.32 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst3.32 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst3.32 {d0, d2, d4}, [r4]" + - + asm_text: "vst3.32 {d0, d2, d4}, [r4:64]" + - + asm_text: "vst3.32 {d0, d2, d4}, [r4]!" + - + asm_text: "vst3.32 {d0, d2, d4}, [r4:64]!" + - + asm_text: "vst3.32 {d0, d2, d4}, [r4], r6" + - + asm_text: "vst3.32 {d0, d2, d4}, [r4:64], r6" + - + asm_text: "vst3.32 {d0[1], d1[1], d2[1]}, [r4]" + - + asm_text: "vst3.32 {d0[1], d1[1], d2[1]}, [r4]!" + - + asm_text: "vst3.32 {d0[1], d1[1], d2[1]}, [r4], r6" + - + asm_text: "vst3.32 {d0[1], d2[1], d4[1]}, [r4]" + - + asm_text: "vst3.32 {d0[1], d2[1], d4[1]}, [r4]!" + - + asm_text: "vst3.32 {d0[1], d2[1], d4[1]}, [r4], r6" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4]" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:64]" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:128]" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:256]" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4]!" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:64]!" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:128]!" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:256]!" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4], r6" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:64], r6" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:128], r6" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:256], r6" + - + asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]" + - + asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]" + - + asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!" + - + asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4]" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:64]" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:128]" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:256]" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4]!" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:64]!" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:128]!" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:256]!" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4], r6" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:64], r6" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:128], r6" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:256], r6" + - + asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]" + - + asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]" + - + asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!" + - + asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6" + - + asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]" + - + asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]" + - + asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]!" + - + asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!" + - + asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6" + - + asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4]" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:64]" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:128]" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:256]" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4]!" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:64]!" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:128]!" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:256]!" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4], r6" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:64], r6" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:128], r6" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:256], r6" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-vst-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-vst-encoding.s.yaml new file mode 100644 index 0000000..7988717 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-vst-encoding.s.yaml @@ -0,0 +1,246 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0x07, 0x40, 0xf4, 0x4f, 0x07, 0x40, 0xf4, 0x8f, 0x07, 0x40, 0xf4, 0xcf, 0x07, 0x40, 0xf4, 0x1f, 0x0a, 0x40, 0xf4, 0x6f, 0x0a, 0x40, 0xf4, 0x8f, 0x0a, 0x40, 0xf4, 0xcf, 0x0a, 0x40, 0xf4, 0x1f, 0x06, 0x40, 0xf4, 0x1d, 0x06, 0x40, 0xf4, 0x03, 0x06, 0x40, 0xf4, 0x1f, 0x02, 0x40, 0xf4, 0x5d, 0x02, 0x41, 0xf4, 0xc2, 0x02, 0x43, 0xf4, 0x1f, 0x08, 0x40, 0xf4, 0x6f, 0x08, 0x40, 0xf4, 0x8f, 0x08, 0x40, 0xf4, 0x1f, 0x03, 0x40, 0xf4, 0x6f, 0x03, 0x40, 0xf4, 0xbf, 0x03, 0x40, 0xf4, 0x1d, 0x08, 0x40, 0xf4, 0x6d, 0xe8, 0x40, 0xf4, 0x8d, 0xe8, 0x00, 0xf4, 0x1d, 0x03, 0x40, 0xf4, 0x6d, 0x23, 0x40, 0xf4, 0xbd, 0x83, 0x00, 0xf4, 0x0f, 0x04, 0x41, 0xf4, 0x4f, 0x64, 0x02, 0xf4, 0x8f, 0x14, 0x03, 0xf4, 0x1f, 0x05, 0x40, 0xf4, 0x4f, 0xb5, 0x44, 0xf4, 0x8f, 0x65, 0x05, 0xf4, 0x01, 0xc4, 0x06, 0xf4, 0x42, 0xb4, 0x07, 0xf4, 0x83, 0x24, 0x08, 0xf4, 0x04, 0x45, 0x09, 0xf4, 0x44, 0xe5, 0x09, 0xf4, 0x85, 0x05, 0x4a, 0xf4, 0x0d, 0x64, 0x08, 0xf4, 0x4d, 0x94, 0x07, 0xf4, 0x8d, 0x14, 0x06, 0xf4, 0x1d, 0x05, 0x40, 0xf4, 0x4d, 0x45, 0x45, 0xf4, 0x8d, 0x55, 0x04, 0xf4, 0x1f, 0x00, 0x41, 0xf4, 0x6f, 0x00, 0x42, 0xf4, 0xbf, 0x00, 0x43, 0xf4, 0x3f, 0x11, 0x45, 0xf4, 0x4f, 0x11, 0x47, 0xf4, 0x8f, 0x01, 0x48, 0xf4, 0x1d, 0x00, 0x41, 0xf4, 0x6d, 0x00, 0x42, 0xf4, 0xbd, 0x00, 0x43, 0xf4, 0x3d, 0x11, 0x45, 0xf4, 0x4d, 0x11, 0x47, 0xf4, 0x8d, 0x01, 0x48, 0xf4, 0x18, 0x00, 0x41, 0xf4, 0x47, 0x00, 0x42, 0xf4, 0x95, 0x00, 0x43, 0xf4, 0x32, 0x01, 0x44, 0xf4, 0x43, 0x01, 0x46, 0xf4, 0x84, 0x11, 0x49, 0xf4, 0x3f, 0x01, 0xc0, 0xf4, 0x5f, 0x05, 0xc0, 0xf4, 0x8f, 0x09, 0xc0, 0xf4, 0x6f, 0x15, 0xc0, 0xf4, 0x5f, 0x19, 0xc0, 0xf4, 0x83, 0x21, 0x82, 0xf4, 0x8d, 0x21, 0x82, 0xf4, 0x8f, 0x21, 0x82, 0xf4, 0x6f, 0x15, 0xc0, 0xf4, 0x5f, 0x19, 0xc0, 0xf4, 0x6d, 0x75, 0x81, 0xf4, 0x5d, 0x69, 0x82, 0xf4, 0x65, 0x25, 0x83, 0xf4, 0x57, 0x59, 0x84, 0xf4, 0x2f, 0x02, 0xc1, 0xf4, 0x4f, 0x66, 0x82, 0xf4, 0x8f, 0x1a, 0x83, 0xf4, 0x6f, 0xb6, 0xc4, 0xf4, 0xcf, 0x6a, 0x85, 0xf4, 0x21, 0xc2, 0x86, 0xf4, 0x42, 0xb6, 0x87, 0xf4, 0x83, 0x2a, 0x88, 0xf4, 0x64, 0xe6, 0x89, 0xf4, 0xc5, 0x0a, 0xca, 0xf4, 0x2d, 0x62, 0x88, 0xf4, 0x4d, 0x96, 0x87, 0xf4, 0x8d, 0x1a, 0x86, 0xf4, 0x6d, 0x46, 0xc5, 0xf4, 0xcd, 0x5a, 0x84, 0xf4, 0x2f, 0x03, 0xc1, 0xf4, 0x4f, 0x07, 0xc2, 0xf4, 0x8f, 0x0b, 0xc3, 0xf4, 0x6f, 0x17, 0xc7, 0xf4, 0xcf, 0x0b, 0xc8, 0xf4, 0x3d, 0x03, 0xc1, 0xf4, 0x5d, 0x07, 0xc2, 0xf4, 0xad, 0x0b, 0xc3, 0xf4, 0x6d, 0x17, 0xc7, 0xf4, 0xcd, 0x0b, 0xc8, 0xf4, 0x38, 0x03, 0xc1, 0xf4, 0x47, 0x07, 0xc2, 0xf4, 0x95, 0x0b, 0xc3, 0xf4, 0x63, 0x07, 0xc6, 0xf4, 0xc4, 0x1b, 0xc9, 0xf4, 0x0f, 0x27, 0x02, 0xf4, 0x0f, 0x27, 0x02, 0xf4, 0x0f, 0x27, 0x02, 0xf4, 0x0f, 0x4a, 0x02, 0xf4, 0x0f, 0x4a, 0x02, 0xf4, 0x0f, 0x4a, 0x02, 0xf4, 0x8f, 0x4a, 0x02, 0xf4, 0x0f, 0x89, 0x04, 0xf4, 0xbf, 0x98, 0x83, 0xf4, 0xbd, 0xb8, 0xc9, 0xf4, 0xb5, 0xb8, 0xc3, 0xf4, 0x1f, 0x08, 0x40, 0xf4, 0x6f, 0x08, 0x40, 0xf4 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vst1.8 {d16}, [r0:64]" + - + asm_text: "vst1.16 {d16}, [r0]" + - + asm_text: "vst1.32 {d16}, [r0]" + - + asm_text: "vst1.64 {d16}, [r0]" + - + asm_text: "vst1.8 {d16, d17}, [r0:64]" + - + asm_text: "vst1.16 {d16, d17}, [r0:128]" + - + asm_text: "vst1.32 {d16, d17}, [r0]" + - + asm_text: "vst1.64 {d16, d17}, [r0]" + - + asm_text: "vst1.8 {d16, d17, d18}, [r0:64]" + - + asm_text: "vst1.8 {d16, d17, d18}, [r0:64]!" + - + asm_text: "vst1.8 {d16, d17, d18}, [r0], r3" + - + asm_text: "vst1.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vst1.16 {d16, d17, d18, d19}, [r1:64]!" + - + asm_text: "vst1.64 {d16, d17, d18, d19}, [r3], r2" + - + asm_text: "vst2.8 {d16, d17}, [r0:64]" + - + asm_text: "vst2.16 {d16, d17}, [r0:128]" + - + asm_text: "vst2.32 {d16, d17}, [r0]" + - + asm_text: "vst2.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vst2.16 {d16, d17, d18, d19}, [r0:128]" + - + asm_text: "vst2.32 {d16, d17, d18, d19}, [r0:256]" + - + asm_text: "vst2.8 {d16, d17}, [r0:64]!" + - + asm_text: "vst2.16 {d30, d31}, [r0:128]!" + - + asm_text: "vst2.32 {d14, d15}, [r0]!" + - + asm_text: "vst2.8 {d16, d17, d18, d19}, [r0:64]!" + - + asm_text: "vst2.16 {d18, d19, d20, d21}, [r0:128]!" + - + asm_text: "vst2.32 {d8, d9, d10, d11}, [r0:256]!" + - + asm_text: "vst3.8 {d16, d17, d18}, [r1]" + - + asm_text: "vst3.16 {d6, d7, d8}, [r2]" + - + asm_text: "vst3.32 {d1, d2, d3}, [r3]" + - + asm_text: "vst3.8 {d16, d18, d20}, [r0:64]" + - + asm_text: "vst3.16 {d27, d29, d31}, [r4]" + - + asm_text: "vst3.32 {d6, d8, d10}, [r5]" + - + asm_text: "vst3.8 {d12, d13, d14}, [r6], r1" + - + asm_text: "vst3.16 {d11, d12, d13}, [r7], r2" + - + asm_text: "vst3.32 {d2, d3, d4}, [r8], r3" + - + asm_text: "vst3.8 {d4, d6, d8}, [r9], r4" + - + asm_text: "vst3.16 {d14, d16, d18}, [r9], r4" + - + asm_text: "vst3.32 {d16, d18, d20}, [r10], r5" + - + asm_text: "vst3.8 {d6, d7, d8}, [r8]!" + - + asm_text: "vst3.16 {d9, d10, d11}, [r7]!" + - + asm_text: "vst3.32 {d1, d2, d3}, [r6]!" + - + asm_text: "vst3.8 {d16, d18, d20}, [r0:64]!" + - + asm_text: "vst3.16 {d20, d22, d24}, [r5]!" + - + asm_text: "vst3.32 {d5, d7, d9}, [r4]!" + - + asm_text: "vst4.8 {d16, d17, d18, d19}, [r1:64]" + - + asm_text: "vst4.16 {d16, d17, d18, d19}, [r2:128]" + - + asm_text: "vst4.32 {d16, d17, d18, d19}, [r3:256]" + - + asm_text: "vst4.8 {d17, d19, d21, d23}, [r5:256]" + - + asm_text: "vst4.16 {d17, d19, d21, d23}, [r7]" + - + asm_text: "vst4.32 {d16, d18, d20, d22}, [r8]" + - + asm_text: "vst4.8 {d16, d17, d18, d19}, [r1:64]!" + - + asm_text: "vst4.16 {d16, d17, d18, d19}, [r2:128]!" + - + asm_text: "vst4.32 {d16, d17, d18, d19}, [r3:256]!" + - + asm_text: "vst4.8 {d17, d19, d21, d23}, [r5:256]!" + - + asm_text: "vst4.16 {d17, d19, d21, d23}, [r7]!" + - + asm_text: "vst4.32 {d16, d18, d20, d22}, [r8]!" + - + asm_text: "vst4.8 {d16, d17, d18, d19}, [r1:64], r8" + - + asm_text: "vst4.16 {d16, d17, d18, d19}, [r2], r7" + - + asm_text: "vst4.32 {d16, d17, d18, d19}, [r3:64], r5" + - + asm_text: "vst4.8 {d16, d18, d20, d22}, [r4:256], r2" + - + asm_text: "vst4.16 {d16, d18, d20, d22}, [r6], r3" + - + asm_text: "vst4.32 {d17, d19, d21, d23}, [r9], r4" + - + asm_text: "vst2.8 {d16[1], d17[1]}, [r0:16]" + - + asm_text: "vst2.16 {d16[1], d17[1]}, [r0:32]" + - + asm_text: "vst2.32 {d16[1], d17[1]}, [r0]" + - + asm_text: "vst2.16 {d17[1], d19[1]}, [r0]" + - + asm_text: "vst2.32 {d17[0], d19[0]}, [r0:64]" + - + asm_text: "vst2.8 {d2[4], d3[4]}, [r2], r3" + - + asm_text: "vst2.8 {d2[4], d3[4]}, [r2]!" + - + asm_text: "vst2.8 {d2[4], d3[4]}, [r2]" + - + asm_text: "vst2.16 {d17[1], d19[1]}, [r0]" + - + asm_text: "vst2.32 {d17[0], d19[0]}, [r0:64]" + - + asm_text: "vst2.16 {d7[1], d9[1]}, [r1]!" + - + asm_text: "vst2.32 {d6[0], d8[0]}, [r2:64]!" + - + asm_text: "vst2.16 {d2[1], d4[1]}, [r3], r5" + - + asm_text: "vst2.32 {d5[0], d7[0]}, [r4:64], r7" + - + asm_text: "vst3.8 {d16[1], d17[1], d18[1]}, [r1]" + - + asm_text: "vst3.16 {d6[1], d7[1], d8[1]}, [r2]" + - + asm_text: "vst3.32 {d1[1], d2[1], d3[1]}, [r3]" + - + asm_text: "vst3.16 {d27[1], d29[1], d31[1]}, [r4]" + - + asm_text: "vst3.32 {d6[1], d8[1], d10[1]}, [r5]" + - + asm_text: "vst3.8 {d12[1], d13[1], d14[1]}, [r6], r1" + - + asm_text: "vst3.16 {d11[1], d12[1], d13[1]}, [r7], r2" + - + asm_text: "vst3.32 {d2[1], d3[1], d4[1]}, [r8], r3" + - + asm_text: "vst3.16 {d14[1], d16[1], d18[1]}, [r9], r4" + - + asm_text: "vst3.32 {d16[1], d18[1], d20[1]}, [r10], r5" + - + asm_text: "vst3.8 {d6[1], d7[1], d8[1]}, [r8]!" + - + asm_text: "vst3.16 {d9[1], d10[1], d11[1]}, [r7]!" + - + asm_text: "vst3.32 {d1[1], d2[1], d3[1]}, [r6]!" + - + asm_text: "vst3.16 {d20[1], d22[1], d24[1]}, [r5]!" + - + asm_text: "vst3.32 {d5[1], d7[1], d9[1]}, [r4]!" + - + asm_text: "vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1]" + - + asm_text: "vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2]" + - + asm_text: "vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3]" + - + asm_text: "vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]" + - + asm_text: "vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]" + - + asm_text: "vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!" + - + asm_text: "vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]!" + - + asm_text: "vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]!" + - + asm_text: "vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!" + - + asm_text: "vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]!" + - + asm_text: "vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8" + - + asm_text: "vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7" + - + asm_text: "vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5" + - + asm_text: "vst4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3" + - + asm_text: "vst4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4" + - + asm_text: "vst1.8 {d2}, [r2]" + - + asm_text: "vst1.8 {d2}, [r2]" + - + asm_text: "vst1.8 {d2}, [r2]" + - + asm_text: "vst1.8 {d4, d5}, [r2]" + - + asm_text: "vst1.8 {d4, d5}, [r2]" + - + asm_text: "vst1.8 {d4, d5}, [r2]" + - + asm_text: "vst1.32 {d4, d5}, [r2]" + - + asm_text: "vst2.8 {d8, d10}, [r4]" + - + asm_text: "vst1.32 {d9[1]}, [r3:32]" + - + asm_text: "vst1.32 {d27[1]}, [r9:32]!" + - + asm_text: "vst1.32 {d27[1]}, [r3:32], r5" + - + asm_text: "vst2.8 {d16, d17}, [r0:64]" + - + asm_text: "vst2.16 {d16, d17}, [r0:128]" diff --git a/thirdparty/capstone/tests/MC/ARM/neon-vswp.s.yaml b/thirdparty/capstone/tests/MC/ARM/neon-vswp.s.yaml new file mode 100644 index 0000000..56acf94 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neon-vswp.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x02, 0x10, 0xb2, 0xf3, 0x44, 0x20, 0xb2, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vswp d1, d2" + - + asm_text: "vswp q1, q2" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-abs-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-abs-encoding.s.yaml new file mode 100644 index 0000000..7fa31d7 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-abs-encoding.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0xf1, 0xff, 0x20, 0x03, 0xf5, 0xff, 0x20, 0x03, 0xf9, 0xff, 0x20, 0x03, 0xf9, 0xff, 0x20, 0x07, 0xf1, 0xff, 0x60, 0x03, 0xf5, 0xff, 0x60, 0x03, 0xf9, 0xff, 0x60, 0x03, 0xf9, 0xff, 0x60, 0x07, 0xf0, 0xff, 0x20, 0x07, 0xf4, 0xff, 0x20, 0x07, 0xf8, 0xff, 0x20, 0x07, 0xf0, 0xff, 0x60, 0x07, 0xf4, 0xff, 0x60, 0x07, 0xf8, 0xff, 0x60, 0x07 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vabs.s8 d16, d16" + - + asm_text: "vabs.s16 d16, d16" + - + asm_text: "vabs.s32 d16, d16" + - + asm_text: "vabs.f32 d16, d16" + - + asm_text: "vabs.s8 q8, q8" + - + asm_text: "vabs.s16 q8, q8" + - + asm_text: "vabs.s32 q8, q8" + - + asm_text: "vabs.f32 q8, q8" + - + asm_text: "vqabs.s8 d16, d16" + - + asm_text: "vqabs.s16 d16, d16" + - + asm_text: "vqabs.s32 d16, d16" + - + asm_text: "vqabs.s8 q8, q8" + - + asm_text: "vqabs.s16 q8, q8" + - + asm_text: "vqabs.s32 q8, q8" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-absdiff-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-absdiff-encoding.s.yaml new file mode 100644 index 0000000..7f70dda --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-absdiff-encoding.s.yaml @@ -0,0 +1,84 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xef, 0xa1, 0x07, 0x50, 0xef, 0xa1, 0x07, 0x60, 0xef, 0xa1, 0x07, 0x40, 0xff, 0xa1, 0x07, 0x50, 0xff, 0xa1, 0x07, 0x60, 0xff, 0xa1, 0x07, 0x60, 0xff, 0xa1, 0x0d, 0x40, 0xef, 0xe2, 0x07, 0x50, 0xef, 0xe2, 0x07, 0x60, 0xef, 0xe2, 0x07, 0x40, 0xff, 0xe2, 0x07, 0x50, 0xff, 0xe2, 0x07, 0x60, 0xff, 0xe2, 0x07, 0x60, 0xff, 0xe2, 0x0d, 0xc0, 0xef, 0xa1, 0x07, 0xd0, 0xef, 0xa1, 0x07, 0xe0, 0xef, 0xa1, 0x07, 0xc0, 0xff, 0xa1, 0x07, 0xd0, 0xff, 0xa1, 0x07, 0xe0, 0xff, 0xa1, 0x07, 0x42, 0xef, 0xb1, 0x07, 0x52, 0xef, 0xb1, 0x07, 0x62, 0xef, 0xb1, 0x07, 0x42, 0xff, 0xb1, 0x07, 0x52, 0xff, 0xb1, 0x07, 0x62, 0xff, 0xb1, 0x07, 0x40, 0xef, 0xf4, 0x27, 0x50, 0xef, 0xf4, 0x27, 0x60, 0xef, 0xf4, 0x27, 0x40, 0xff, 0xf4, 0x27, 0x50, 0xff, 0xf4, 0x27, 0x60, 0xff, 0xf4, 0x27, 0xc3, 0xef, 0xa2, 0x05, 0xd3, 0xef, 0xa2, 0x05, 0xe3, 0xef, 0xa2, 0x05, 0xc3, 0xff, 0xa2, 0x05, 0xd3, 0xff, 0xa2, 0x05, 0xe3, 0xff, 0xa2, 0x05 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vabd.s8 d16, d16, d17" + - + asm_text: "vabd.s16 d16, d16, d17" + - + asm_text: "vabd.s32 d16, d16, d17" + - + asm_text: "vabd.u8 d16, d16, d17" + - + asm_text: "vabd.u16 d16, d16, d17" + - + asm_text: "vabd.u32 d16, d16, d17" + - + asm_text: "vabd.f32 d16, d16, d17" + - + asm_text: "vabd.s8 q8, q8, q9" + - + asm_text: "vabd.s16 q8, q8, q9" + - + asm_text: "vabd.s32 q8, q8, q9" + - + asm_text: "vabd.u8 q8, q8, q9" + - + asm_text: "vabd.u16 q8, q8, q9" + - + asm_text: "vabd.u32 q8, q8, q9" + - + asm_text: "vabd.f32 q8, q8, q9" + - + asm_text: "vabdl.s8 q8, d16, d17" + - + asm_text: "vabdl.s16 q8, d16, d17" + - + asm_text: "vabdl.s32 q8, d16, d17" + - + asm_text: "vabdl.u8 q8, d16, d17" + - + asm_text: "vabdl.u16 q8, d16, d17" + - + asm_text: "vabdl.u32 q8, d16, d17" + - + asm_text: "vaba.s8 d16, d18, d17" + - + asm_text: "vaba.s16 d16, d18, d17" + - + asm_text: "vaba.s32 d16, d18, d17" + - + asm_text: "vaba.u8 d16, d18, d17" + - + asm_text: "vaba.u16 d16, d18, d17" + - + asm_text: "vaba.u32 d16, d18, d17" + - + asm_text: "vaba.s8 q9, q8, q10" + - + asm_text: "vaba.s16 q9, q8, q10" + - + asm_text: "vaba.s32 q9, q8, q10" + - + asm_text: "vaba.u8 q9, q8, q10" + - + asm_text: "vaba.u16 q9, q8, q10" + - + asm_text: "vaba.u32 q9, q8, q10" + - + asm_text: "vabal.s8 q8, d19, d18" + - + asm_text: "vabal.s16 q8, d19, d18" + - + asm_text: "vabal.s32 q8, d19, d18" + - + asm_text: "vabal.u8 q8, d19, d18" + - + asm_text: "vabal.u16 q8, d19, d18" + - + asm_text: "vabal.u32 q8, d19, d18" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-add-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-add-encoding.s.yaml new file mode 100644 index 0000000..b61dc0c --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-add-encoding.s.yaml @@ -0,0 +1,136 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xef, 0xa0, 0x08, 0x51, 0xef, 0xa0, 0x08, 0x71, 0xef, 0xa0, 0x08, 0x61, 0xef, 0xa0, 0x08, 0x40, 0xef, 0xa1, 0x0d, 0x40, 0xef, 0xe2, 0x0d, 0xc1, 0xef, 0xa0, 0x00, 0xd1, 0xef, 0xa0, 0x00, 0xe1, 0xef, 0xa0, 0x00, 0xc1, 0xff, 0xa0, 0x00, 0xd1, 0xff, 0xa0, 0x00, 0xe1, 0xff, 0xa0, 0x00, 0xc0, 0xef, 0xa2, 0x01, 0xd0, 0xef, 0xa2, 0x01, 0xe0, 0xef, 0xa2, 0x01, 0xc0, 0xff, 0xa2, 0x01, 0xd0, 0xff, 0xa2, 0x01, 0xe0, 0xff, 0xa2, 0x01, 0x40, 0xef, 0xa1, 0x00, 0x50, 0xef, 0xa1, 0x00, 0x60, 0xef, 0xa1, 0x00, 0x40, 0xff, 0xa1, 0x00, 0x50, 0xff, 0xa1, 0x00, 0x60, 0xff, 0xa1, 0x00, 0x40, 0xef, 0xe2, 0x00, 0x50, 0xef, 0xe2, 0x00, 0x60, 0xef, 0xe2, 0x00, 0x40, 0xff, 0xe2, 0x00, 0x50, 0xff, 0xe2, 0x00, 0x60, 0xff, 0xe2, 0x00, 0x40, 0xef, 0xa1, 0x01, 0x50, 0xef, 0xa1, 0x01, 0x60, 0xef, 0xa1, 0x01, 0x40, 0xff, 0xa1, 0x01, 0x50, 0xff, 0xa1, 0x01, 0x60, 0xff, 0xa1, 0x01, 0x40, 0xef, 0xe2, 0x01, 0x50, 0xef, 0xe2, 0x01, 0x60, 0xef, 0xe2, 0x01, 0x40, 0xff, 0xe2, 0x01, 0x50, 0xff, 0xe2, 0x01, 0x60, 0xff, 0xe2, 0x01, 0x40, 0xef, 0xb1, 0x00, 0x50, 0xef, 0xb1, 0x00, 0x60, 0xef, 0xb1, 0x00, 0x70, 0xef, 0xb1, 0x00, 0x40, 0xff, 0xb1, 0x00, 0x50, 0xff, 0xb1, 0x00, 0x60, 0xff, 0xb1, 0x00, 0x70, 0xff, 0xb1, 0x00, 0x40, 0xef, 0xf2, 0x00, 0x50, 0xef, 0xf2, 0x00, 0x60, 0xef, 0xf2, 0x00, 0x70, 0xef, 0xf2, 0x00, 0x40, 0xff, 0xf2, 0x00, 0x50, 0xff, 0xf2, 0x00, 0x60, 0xff, 0xf2, 0x00, 0x70, 0xff, 0xf2, 0x00, 0xc0, 0xef, 0xa2, 0x04, 0xd0, 0xef, 0xa2, 0x04, 0xe0, 0xef, 0xa2, 0x04, 0xc0, 0xff, 0xa2, 0x04, 0xd0, 0xff, 0xa2, 0x04, 0xe0, 0xff, 0xa2, 0x04 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vadd.i8 d16, d17, d16" + - + asm_text: "vadd.i16 d16, d17, d16" + - + asm_text: "vadd.i64 d16, d17, d16" + - + asm_text: "vadd.i32 d16, d17, d16" + - + asm_text: "vadd.f32 d16, d16, d17" + - + asm_text: "vadd.f32 q8, q8, q9" + - + asm_text: "vaddl.s8 q8, d17, d16" + - + asm_text: "vaddl.s16 q8, d17, d16" + - + asm_text: "vaddl.s32 q8, d17, d16" + - + asm_text: "vaddl.u8 q8, d17, d16" + - + asm_text: "vaddl.u16 q8, d17, d16" + - + asm_text: "vaddl.u32 q8, d17, d16" + - + asm_text: "vaddw.s8 q8, q8, d18" + - + asm_text: "vaddw.s16 q8, q8, d18" + - + asm_text: "vaddw.s32 q8, q8, d18" + - + asm_text: "vaddw.u8 q8, q8, d18" + - + asm_text: "vaddw.u16 q8, q8, d18" + - + asm_text: "vaddw.u32 q8, q8, d18" + - + asm_text: "vhadd.s8 d16, d16, d17" + - + asm_text: "vhadd.s16 d16, d16, d17" + - + asm_text: "vhadd.s32 d16, d16, d17" + - + asm_text: "vhadd.u8 d16, d16, d17" + - + asm_text: "vhadd.u16 d16, d16, d17" + - + asm_text: "vhadd.u32 d16, d16, d17" + - + asm_text: "vhadd.s8 q8, q8, q9" + - + asm_text: "vhadd.s16 q8, q8, q9" + - + asm_text: "vhadd.s32 q8, q8, q9" + - + asm_text: "vhadd.u8 q8, q8, q9" + - + asm_text: "vhadd.u16 q8, q8, q9" + - + asm_text: "vhadd.u32 q8, q8, q9" + - + asm_text: "vrhadd.s8 d16, d16, d17" + - + asm_text: "vrhadd.s16 d16, d16, d17" + - + asm_text: "vrhadd.s32 d16, d16, d17" + - + asm_text: "vrhadd.u8 d16, d16, d17" + - + asm_text: "vrhadd.u16 d16, d16, d17" + - + asm_text: "vrhadd.u32 d16, d16, d17" + - + asm_text: "vrhadd.s8 q8, q8, q9" + - + asm_text: "vrhadd.s16 q8, q8, q9" + - + asm_text: "vrhadd.s32 q8, q8, q9" + - + asm_text: "vrhadd.u8 q8, q8, q9" + - + asm_text: "vrhadd.u16 q8, q8, q9" + - + asm_text: "vrhadd.u32 q8, q8, q9" + - + asm_text: "vqadd.s8 d16, d16, d17" + - + asm_text: "vqadd.s16 d16, d16, d17" + - + asm_text: "vqadd.s32 d16, d16, d17" + - + asm_text: "vqadd.s64 d16, d16, d17" + - + asm_text: "vqadd.u8 d16, d16, d17" + - + asm_text: "vqadd.u16 d16, d16, d17" + - + asm_text: "vqadd.u32 d16, d16, d17" + - + asm_text: "vqadd.u64 d16, d16, d17" + - + asm_text: "vqadd.s8 q8, q8, q9" + - + asm_text: "vqadd.s16 q8, q8, q9" + - + asm_text: "vqadd.s32 q8, q8, q9" + - + asm_text: "vqadd.s64 q8, q8, q9" + - + asm_text: "vqadd.u8 q8, q8, q9" + - + asm_text: "vqadd.u16 q8, q8, q9" + - + asm_text: "vqadd.u32 q8, q8, q9" + - + asm_text: "vqadd.u64 q8, q8, q9" + - + asm_text: "vaddhn.i16 d16, q8, q9" + - + asm_text: "vaddhn.i32 d16, q8, q9" + - + asm_text: "vaddhn.i64 d16, q8, q9" + - + asm_text: "vraddhn.i16 d16, q8, q9" + - + asm_text: "vraddhn.i32 d16, q8, q9" + - + asm_text: "vraddhn.i64 d16, q8, q9" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-bitcount-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-bitcount-encoding.s.yaml new file mode 100644 index 0000000..446c5fe --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-bitcount-encoding.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0xf0, 0xff, 0x20, 0x05, 0xf0, 0xff, 0x60, 0x05, 0xf0, 0xff, 0xa0, 0x04, 0xf4, 0xff, 0xa0, 0x04, 0xf8, 0xff, 0xa0, 0x04, 0xf0, 0xff, 0xe0, 0x04, 0xf4, 0xff, 0xe0, 0x04, 0xf8, 0xff, 0xe0, 0x04, 0xf0, 0xff, 0x20, 0x04, 0xf4, 0xff, 0x20, 0x04, 0xf8, 0xff, 0x20, 0x04, 0xf0, 0xff, 0x60, 0x04, 0xf4, 0xff, 0x60, 0x04, 0xf8, 0xff, 0x60, 0x04 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcnt.8 d16, d16" + - + asm_text: "vcnt.8 q8, q8" + - + asm_text: "vclz.i8 d16, d16" + - + asm_text: "vclz.i16 d16, d16" + - + asm_text: "vclz.i32 d16, d16" + - + asm_text: "vclz.i8 q8, q8" + - + asm_text: "vclz.i16 q8, q8" + - + asm_text: "vclz.i32 q8, q8" + - + asm_text: "vcls.s8 d16, d16" + - + asm_text: "vcls.s16 d16, d16" + - + asm_text: "vcls.s32 d16, d16" + - + asm_text: "vcls.s8 q8, q8" + - + asm_text: "vcls.s16 q8, q8" + - + asm_text: "vcls.s32 q8, q8" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-bitwise-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-bitwise-encoding.s.yaml new file mode 100644 index 0000000..ade8ef8 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-bitwise-encoding.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xef, 0xb0, 0x01, 0x40, 0xef, 0xf2, 0x01, 0x41, 0xff, 0xb0, 0x01, 0x40, 0xff, 0xf2, 0x01, 0x61, 0xef, 0xb0, 0x01, 0x60, 0xef, 0xf2, 0x01, 0x51, 0xef, 0xb0, 0x01, 0x50, 0xef, 0xf2, 0x01, 0x71, 0xef, 0xb0, 0x01, 0x70, 0xef, 0xf2, 0x01, 0xf0, 0xff, 0xa0, 0x05, 0xf0, 0xff, 0xe0, 0x05, 0x51, 0xff, 0xb0, 0x21, 0x54, 0xff, 0xf2, 0x01, 0x61, 0xff, 0xb0, 0x21, 0x64, 0xff, 0xf2, 0x01, 0x71, 0xff, 0xb0, 0x21, 0x74, 0xff, 0xf2, 0x01 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vand d16, d17, d16" + - + asm_text: "vand q8, q8, q9" + - + asm_text: "veor d16, d17, d16" + - + asm_text: "veor q8, q8, q9" + - + asm_text: "vorr d16, d17, d16" + - + asm_text: "vorr q8, q8, q9" + - + asm_text: "vbic d16, d17, d16" + - + asm_text: "vbic q8, q8, q9" + - + asm_text: "vorn d16, d17, d16" + - + asm_text: "vorn q8, q8, q9" + - + asm_text: "vmvn d16, d16" + - + asm_text: "vmvn q8, q8" + - + asm_text: "vbsl d18, d17, d16" + - + asm_text: "vbsl q8, q10, q9" + - + asm_text: "vbit d18, d17, d16" + - + asm_text: "vbit q8, q10, q9" + - + asm_text: "vbif d18, d17, d16" + - + asm_text: "vbif q8, q10, q9" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-cmp-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-cmp-encoding.s.yaml new file mode 100644 index 0000000..b83a7f6 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-cmp-encoding.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0xfb, 0xff, 0x20, 0x07, 0xfb, 0xff, 0xa0, 0x07, 0xfb, 0xff, 0x20, 0x06, 0xfb, 0xff, 0xa0, 0x06, 0xfb, 0xff, 0x60, 0x07, 0xfb, 0xff, 0xe0, 0x07, 0xfb, 0xff, 0x60, 0x06, 0xfb, 0xff, 0xe0, 0x06, 0xff, 0xef, 0x30, 0x0f, 0xff, 0xff, 0x30, 0x0f, 0xff, 0xef, 0x30, 0x0e, 0xff, 0xff, 0x30, 0x0e, 0xff, 0xef, 0x70, 0x0f, 0xff, 0xff, 0x70, 0x0f, 0xff, 0xef, 0x70, 0x0e, 0xff, 0xff, 0x70, 0x0e ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcvt.s32.f32 d16, d16" + - + asm_text: "vcvt.u32.f32 d16, d16" + - + asm_text: "vcvt.f32.s32 d16, d16" + - + asm_text: "vcvt.f32.u32 d16, d16" + - + asm_text: "vcvt.s32.f32 q8, q8" + - + asm_text: "vcvt.u32.f32 q8, q8" + - + asm_text: "vcvt.f32.s32 q8, q8" + - + asm_text: "vcvt.f32.u32 q8, q8" + - + asm_text: "vcvt.s32.f32 d16, d16, #1" + - + asm_text: "vcvt.u32.f32 d16, d16, #1" + - + asm_text: "vcvt.f32.s32 d16, d16, #1" + - + asm_text: "vcvt.f32.u32 d16, d16, #1" + - + asm_text: "vcvt.s32.f32 q8, q8, #1" + - + asm_text: "vcvt.u32.f32 q8, q8, #1" + - + asm_text: "vcvt.f32.s32 q8, q8, #1" + - + asm_text: "vcvt.f32.u32 q8, q8, #1" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-convert-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-convert-encoding.s.yaml new file mode 100644 index 0000000..e2450a0 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-convert-encoding.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0xfb, 0xff, 0x20, 0x07, 0xfb, 0xff, 0xa0, 0x07, 0xfb, 0xff, 0x20, 0x06, 0xfb, 0xff, 0xa0, 0x06, 0xfb, 0xff, 0x60, 0x07, 0xfb, 0xff, 0xe0, 0x07, 0xfb, 0xff, 0x60, 0x06, 0xfb, 0xff, 0xe0, 0x06, 0xff, 0xef, 0x30, 0x0f, 0xff, 0xff, 0x30, 0x0f, 0xff, 0xef, 0x30, 0x0e, 0xff, 0xff, 0x30, 0x0e, 0xff, 0xef, 0x70, 0x0f, 0xff, 0xff, 0x70, 0x0f, 0xff, 0xef, 0x70, 0x0e, 0xff, 0xff, 0x70, 0x0e, 0xf6, 0xff, 0x20, 0x07, 0xf6, 0xff, 0x20, 0x06 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcvt.s32.f32 d16, d16" + - + asm_text: "vcvt.u32.f32 d16, d16" + - + asm_text: "vcvt.f32.s32 d16, d16" + - + asm_text: "vcvt.f32.u32 d16, d16" + - + asm_text: "vcvt.s32.f32 q8, q8" + - + asm_text: "vcvt.u32.f32 q8, q8" + - + asm_text: "vcvt.f32.s32 q8, q8" + - + asm_text: "vcvt.f32.u32 q8, q8" + - + asm_text: "vcvt.s32.f32 d16, d16, #1" + - + asm_text: "vcvt.u32.f32 d16, d16, #1" + - + asm_text: "vcvt.f32.s32 d16, d16, #1" + - + asm_text: "vcvt.f32.u32 d16, d16, #1" + - + asm_text: "vcvt.s32.f32 q8, q8, #1" + - + asm_text: "vcvt.u32.f32 q8, q8, #1" + - + asm_text: "vcvt.f32.s32 q8, q8, #1" + - + asm_text: "vcvt.f32.u32 q8, q8, #1" + - + asm_text: "vcvt.f32.f16 q8, d16" + - + asm_text: "vcvt.f16.f32 d16, q8" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-dup-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-dup-encoding.s.yaml new file mode 100644 index 0000000..10ecb49 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-dup-encoding.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0xc0, 0xee, 0x90, 0x1b, 0x8f, 0xee, 0x30, 0x2b, 0x8e, 0xee, 0x10, 0x3b, 0xe2, 0xee, 0x90, 0x4b, 0xa0, 0xee, 0xb0, 0x5b, 0xae, 0xee, 0x10, 0x6b, 0xf1, 0xff, 0x0b, 0x0c, 0xf2, 0xff, 0x0c, 0x1c, 0xf4, 0xff, 0x0d, 0x2c, 0xb1, 0xff, 0x4a, 0x6c, 0xf2, 0xff, 0x49, 0x2c, 0xf4, 0xff, 0x48, 0x0c, 0xf3, 0xff, 0x0b, 0x0c, 0xf6, 0xff, 0x0c, 0x1c, 0xfc, 0xff, 0x0d, 0x2c, 0xb3, 0xff, 0x4a, 0x6c, 0xf6, 0xff, 0x49, 0x2c, 0xfc, 0xff, 0x48, 0x0c ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vdup.8 d16, r1" + - + asm_text: "vdup.16 d15, r2" + - + asm_text: "vdup.32 d14, r3" + - + asm_text: "vdup.8 q9, r4" + - + asm_text: "vdup.16 q8, r5" + - + asm_text: "vdup.32 q7, r6" + - + asm_text: "vdup.8 d16, d11[0]" + - + asm_text: "vdup.16 d17, d12[0]" + - + asm_text: "vdup.32 d18, d13[0]" + - + asm_text: "vdup.8 q3, d10[0]" + - + asm_text: "vdup.16 q9, d9[0]" + - + asm_text: "vdup.32 q8, d8[0]" + - + asm_text: "vdup.8 d16, d11[1]" + - + asm_text: "vdup.16 d17, d12[1]" + - + asm_text: "vdup.32 d18, d13[1]" + - + asm_text: "vdup.8 q3, d10[1]" + - + asm_text: "vdup.16 q9, d9[1]" + - + asm_text: "vdup.32 q8, d8[1]" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-minmax-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-minmax-encoding.s.yaml new file mode 100644 index 0000000..b78bb41 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-minmax-encoding.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x02, 0xef, 0x03, 0x16, 0x15, 0xef, 0x06, 0x46, 0x28, 0xef, 0x09, 0x76, 0x0b, 0xff, 0x0c, 0xa6, 0x1e, 0xff, 0x0f, 0xd6, 0x61, 0xff, 0xa2, 0x06, 0x44, 0xef, 0xa5, 0x3f, 0x02, 0xef, 0x03, 0x26, 0x15, 0xef, 0x06, 0x56, 0x28, 0xef, 0x09, 0x86, 0x0b, 0xff, 0x0c, 0xb6, 0x1e, 0xff, 0x0f, 0xe6, 0x61, 0xff, 0xa2, 0x16, 0x44, 0xef, 0xa5, 0x4f, 0x04, 0xef, 0x46, 0x26, 0x1a, 0xef, 0x4c, 0x86, 0x20, 0xef, 0xe2, 0xe6, 0x46, 0xff, 0xe8, 0x46, 0x5c, 0xff, 0xee, 0xa6, 0x2e, 0xff, 0x60, 0xc6, 0x4a, 0xef, 0x42, 0x2f, 0x04, 0xef, 0x46, 0x46, 0x1a, 0xef, 0x4c, 0xa6, 0x60, 0xef, 0xe2, 0x06, 0x46, 0xff, 0xc4, 0x66, 0x18, 0xff, 0x4a, 0x86, 0x2e, 0xff, 0x60, 0xe6, 0x04, 0xef, 0x42, 0x4f, 0x02, 0xef, 0x13, 0x16, 0x15, 0xef, 0x16, 0x46, 0x28, 0xef, 0x19, 0x76, 0x0b, 0xff, 0x1c, 0xa6, 0x1e, 0xff, 0x1f, 0xd6, 0x61, 0xff, 0xb2, 0x06, 0x64, 0xef, 0xa5, 0x3f, 0x02, 0xef, 0x13, 0x26, 0x15, 0xef, 0x16, 0x56, 0x28, 0xef, 0x19, 0x86, 0x0b, 0xff, 0x1c, 0xb6, 0x1e, 0xff, 0x1f, 0xe6, 0x61, 0xff, 0xb2, 0x16, 0x64, 0xef, 0xa5, 0x4f, 0x04, 0xef, 0x56, 0x26, 0x1a, 0xef, 0x5c, 0x86, 0x20, 0xef, 0xf2, 0xe6, 0x46, 0xff, 0xf8, 0x46, 0x5c, 0xff, 0xfe, 0xa6, 0x2e, 0xff, 0x70, 0xc6, 0x6a, 0xef, 0x42, 0x2f, 0x04, 0xef, 0x56, 0x46, 0x1a, 0xef, 0x5c, 0xa6, 0x60, 0xef, 0xf2, 0x06, 0x46, 0xff, 0xd4, 0x66, 0x18, 0xff, 0x5a, 0x86, 0x2e, 0xff, 0x70, 0xe6, 0x24, 0xef, 0x42, 0x4f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmax.s8 d1, d2, d3" + - + asm_text: "vmax.s16 d4, d5, d6" + - + asm_text: "vmax.s32 d7, d8, d9" + - + asm_text: "vmax.u8 d10, d11, d12" + - + asm_text: "vmax.u16 d13, d14, d15" + - + asm_text: "vmax.u32 d16, d17, d18" + - + asm_text: "vmax.f32 d19, d20, d21" + - + asm_text: "vmax.s8 d2, d2, d3" + - + asm_text: "vmax.s16 d5, d5, d6" + - + asm_text: "vmax.s32 d8, d8, d9" + - + asm_text: "vmax.u8 d11, d11, d12" + - + asm_text: "vmax.u16 d14, d14, d15" + - + asm_text: "vmax.u32 d17, d17, d18" + - + asm_text: "vmax.f32 d20, d20, d21" + - + asm_text: "vmax.s8 q1, q2, q3" + - + asm_text: "vmax.s16 q4, q5, q6" + - + asm_text: "vmax.s32 q7, q8, q9" + - + asm_text: "vmax.u8 q10, q11, q12" + - + asm_text: "vmax.u16 q13, q14, q15" + - + asm_text: "vmax.u32 q6, q7, q8" + - + asm_text: "vmax.f32 q9, q5, q1" + - + asm_text: "vmax.s8 q2, q2, q3" + - + asm_text: "vmax.s16 q5, q5, q6" + - + asm_text: "vmax.s32 q8, q8, q9" + - + asm_text: "vmax.u8 q11, q11, q2" + - + asm_text: "vmax.u16 q4, q4, q5" + - + asm_text: "vmax.u32 q7, q7, q8" + - + asm_text: "vmax.f32 q2, q2, q1" + - + asm_text: "vmin.s8 d1, d2, d3" + - + asm_text: "vmin.s16 d4, d5, d6" + - + asm_text: "vmin.s32 d7, d8, d9" + - + asm_text: "vmin.u8 d10, d11, d12" + - + asm_text: "vmin.u16 d13, d14, d15" + - + asm_text: "vmin.u32 d16, d17, d18" + - + asm_text: "vmin.f32 d19, d20, d21" + - + asm_text: "vmin.s8 d2, d2, d3" + - + asm_text: "vmin.s16 d5, d5, d6" + - + asm_text: "vmin.s32 d8, d8, d9" + - + asm_text: "vmin.u8 d11, d11, d12" + - + asm_text: "vmin.u16 d14, d14, d15" + - + asm_text: "vmin.u32 d17, d17, d18" + - + asm_text: "vmin.f32 d20, d20, d21" + - + asm_text: "vmin.s8 q1, q2, q3" + - + asm_text: "vmin.s16 q4, q5, q6" + - + asm_text: "vmin.s32 q7, q8, q9" + - + asm_text: "vmin.u8 q10, q11, q12" + - + asm_text: "vmin.u16 q13, q14, q15" + - + asm_text: "vmin.u32 q6, q7, q8" + - + asm_text: "vmin.f32 q9, q5, q1" + - + asm_text: "vmin.s8 q2, q2, q3" + - + asm_text: "vmin.s16 q5, q5, q6" + - + asm_text: "vmin.s32 q8, q8, q9" + - + asm_text: "vmin.u8 q11, q11, q2" + - + asm_text: "vmin.u16 q4, q4, q5" + - + asm_text: "vmin.u32 q7, q7, q8" + - + asm_text: "vmin.f32 q2, q2, q1" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-mov-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-mov-encoding.s.yaml new file mode 100644 index 0000000..c0b06ab --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-mov-encoding.s.yaml @@ -0,0 +1,122 @@ +test_cases: + - + input: + bytes: [ 0xc0, 0xef, 0x18, 0x0e, 0xc1, 0xef, 0x10, 0x08, 0xc1, 0xef, 0x10, 0x0a, 0xc2, 0xef, 0x10, 0x00, 0xc2, 0xef, 0x10, 0x02, 0xc2, 0xef, 0x10, 0x04, 0xc2, 0xef, 0x10, 0x06, 0xc2, 0xef, 0x10, 0x0c, 0xc2, 0xef, 0x10, 0x0d, 0xc1, 0xff, 0x33, 0x0e, 0xc0, 0xef, 0x58, 0x0e, 0xc1, 0xef, 0x50, 0x08, 0xc1, 0xef, 0x50, 0x0a, 0xc2, 0xef, 0x50, 0x00, 0xc2, 0xef, 0x50, 0x02, 0xc2, 0xef, 0x50, 0x04, 0xc2, 0xef, 0x50, 0x06, 0xc2, 0xef, 0x50, 0x0c, 0xc2, 0xef, 0x50, 0x0d, 0xc1, 0xff, 0x73, 0x0e, 0xc1, 0xef, 0x30, 0x08, 0xc1, 0xef, 0x30, 0x0a, 0xc2, 0xef, 0x30, 0x00, 0xc2, 0xef, 0x30, 0x02, 0xc2, 0xef, 0x30, 0x04, 0xc2, 0xef, 0x30, 0x06, 0xc2, 0xef, 0x30, 0x0c, 0xc2, 0xef, 0x30, 0x0d, 0xc8, 0xef, 0x30, 0x0a, 0xd0, 0xef, 0x30, 0x0a, 0xe0, 0xef, 0x30, 0x0a, 0xc8, 0xff, 0x30, 0x0a, 0xd0, 0xff, 0x30, 0x0a, 0xe0, 0xff, 0x30, 0x0a, 0xf2, 0xff, 0x20, 0x02, 0xf6, 0xff, 0x20, 0x02, 0xfa, 0xff, 0x20, 0x02, 0xf2, 0xff, 0xa0, 0x02, 0xf6, 0xff, 0xa0, 0x02, 0xfa, 0xff, 0xa0, 0x02, 0xf2, 0xff, 0xe0, 0x02, 0xf6, 0xff, 0xe0, 0x02, 0xfa, 0xff, 0xe0, 0x02, 0xf2, 0xff, 0x60, 0x02, 0xf6, 0xff, 0x60, 0x02, 0xfa, 0xff, 0x60, 0x02, 0x50, 0xee, 0xb0, 0x0b, 0x10, 0xee, 0xf0, 0x0b, 0xd0, 0xee, 0xb0, 0x0b, 0x90, 0xee, 0xf0, 0x0b, 0x30, 0xee, 0x90, 0x0b, 0x40, 0xee, 0xb0, 0x1b, 0x00, 0xee, 0xf0, 0x1b, 0x20, 0xee, 0x90, 0x1b, 0x42, 0xee, 0xb0, 0x1b, 0x02, 0xee, 0xf0, 0x1b, 0x22, 0xee, 0x90, 0x1b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmov.i8 d16, #0x8" + - + asm_text: "vmov.i16 d16, #0x10" + - + asm_text: "vmov.i16 d16, #0x1000" + - + asm_text: "vmov.i32 d16, #0x20" + - + asm_text: "vmov.i32 d16, #0x2000" + - + asm_text: "vmov.i32 d16, #0x200000" + - + asm_text: "vmov.i32 d16, #0x20000000" + - + asm_text: "vmov.i32 d16, #0x20ff" + - + asm_text: "vmov.i32 d16, #0x20ffff" + - + asm_text: "vmov.i64 d16, #0xff0000ff0000ffff" + - + asm_text: "vmov.i8 q8, #0x8" + - + asm_text: "vmov.i16 q8, #0x10" + - + asm_text: "vmov.i16 q8, #0x1000" + - + asm_text: "vmov.i32 q8, #0x20" + - + asm_text: "vmov.i32 q8, #0x2000" + - + asm_text: "vmov.i32 q8, #0x200000" + - + asm_text: "vmov.i32 q8, #0x20000000" + - + asm_text: "vmov.i32 q8, #0x20ff" + - + asm_text: "vmov.i32 q8, #0x20ffff" + - + asm_text: "vmov.i64 q8, #0xff0000ff0000ffff" + - + asm_text: "vmvn.i16 d16, #0x10" + - + asm_text: "vmvn.i16 d16, #0x1000" + - + asm_text: "vmvn.i32 d16, #0x20" + - + asm_text: "vmvn.i32 d16, #0x2000" + - + asm_text: "vmvn.i32 d16, #0x200000" + - + asm_text: "vmvn.i32 d16, #0x20000000" + - + asm_text: "vmvn.i32 d16, #0x20ff" + - + asm_text: "vmvn.i32 d16, #0x20ffff" + - + asm_text: "vmovl.s8 q8, d16" + - + asm_text: "vmovl.s16 q8, d16" + - + asm_text: "vmovl.s32 q8, d16" + - + asm_text: "vmovl.u8 q8, d16" + - + asm_text: "vmovl.u16 q8, d16" + - + asm_text: "vmovl.u32 q8, d16" + - + asm_text: "vmovn.i16 d16, q8" + - + asm_text: "vmovn.i32 d16, q8" + - + asm_text: "vmovn.i64 d16, q8" + - + asm_text: "vqmovn.s16 d16, q8" + - + asm_text: "vqmovn.s32 d16, q8" + - + asm_text: "vqmovn.s64 d16, q8" + - + asm_text: "vqmovn.u16 d16, q8" + - + asm_text: "vqmovn.u32 d16, q8" + - + asm_text: "vqmovn.u64 d16, q8" + - + asm_text: "vqmovun.s16 d16, q8" + - + asm_text: "vqmovun.s32 d16, q8" + - + asm_text: "vqmovun.s64 d16, q8" + - + asm_text: "vmov.s8 r0, d16[1]" + - + asm_text: "vmov.s16 r0, d16[1]" + - + asm_text: "vmov.u8 r0, d16[1]" + - + asm_text: "vmov.u16 r0, d16[1]" + - + asm_text: "vmov.32 r0, d16[1]" + - + asm_text: "vmov.8 d16[1], r1" + - + asm_text: "vmov.16 d16[1], r1" + - + asm_text: "vmov.32 d16[1], r1" + - + asm_text: "vmov.8 d18[1], r1" + - + asm_text: "vmov.16 d18[1], r1" + - + asm_text: "vmov.32 d18[1], r1" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-mul-accum-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-mul-accum-encoding.s.yaml new file mode 100644 index 0000000..d861d51 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-mul-accum-encoding.s.yaml @@ -0,0 +1,88 @@ +test_cases: + - + input: + bytes: [ 0x42, 0xef, 0xa1, 0x09, 0x52, 0xef, 0xa1, 0x09, 0x62, 0xef, 0xa1, 0x09, 0x42, 0xef, 0xb1, 0x0d, 0x40, 0xef, 0xe4, 0x29, 0x50, 0xef, 0xe4, 0x29, 0x60, 0xef, 0xe4, 0x29, 0x40, 0xef, 0xf4, 0x2d, 0xe0, 0xff, 0xc3, 0x80, 0xc3, 0xef, 0xa2, 0x08, 0xd3, 0xef, 0xa2, 0x08, 0xe3, 0xef, 0xa2, 0x08, 0xc3, 0xff, 0xa2, 0x08, 0xd3, 0xff, 0xa2, 0x08, 0xe3, 0xff, 0xa2, 0x08, 0xa5, 0xef, 0x4a, 0x02, 0xd3, 0xef, 0xa2, 0x09, 0xe3, 0xef, 0xa2, 0x09, 0xdb, 0xef, 0x47, 0x63, 0xdb, 0xef, 0x4f, 0x63, 0xdb, 0xef, 0x67, 0x63, 0xdb, 0xef, 0x6f, 0x63, 0x42, 0xff, 0xa1, 0x09, 0x52, 0xff, 0xa1, 0x09, 0x62, 0xff, 0xa1, 0x09, 0x62, 0xef, 0xb1, 0x0d, 0x40, 0xff, 0xe4, 0x29, 0x50, 0xff, 0xe4, 0x29, 0x60, 0xff, 0xe4, 0x29, 0x60, 0xef, 0xf4, 0x2d, 0x98, 0xff, 0xe6, 0x84, 0xc3, 0xef, 0xa2, 0x0a, 0xd3, 0xef, 0xa2, 0x0a, 0xe3, 0xef, 0xa2, 0x0a, 0xc3, 0xff, 0xa2, 0x0a, 0xd3, 0xff, 0xa2, 0x0a, 0xe3, 0xff, 0xa2, 0x0a, 0xd9, 0xff, 0xe9, 0x66, 0xd3, 0xef, 0xa2, 0x0b, 0xe3, 0xef, 0xa2, 0x0b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmla.i8 d16, d18, d17" + - + asm_text: "vmla.i16 d16, d18, d17" + - + asm_text: "vmla.i32 d16, d18, d17" + - + asm_text: "vmla.f32 d16, d18, d17" + - + asm_text: "vmla.i8 q9, q8, q10" + - + asm_text: "vmla.i16 q9, q8, q10" + - + asm_text: "vmla.i32 q9, q8, q10" + - + asm_text: "vmla.f32 q9, q8, q10" + - + asm_text: "vmla.i32 q12, q8, d3[0]" + - + asm_text: "vmlal.s8 q8, d19, d18" + - + asm_text: "vmlal.s16 q8, d19, d18" + - + asm_text: "vmlal.s32 q8, d19, d18" + - + asm_text: "vmlal.u8 q8, d19, d18" + - + asm_text: "vmlal.u16 q8, d19, d18" + - + asm_text: "vmlal.u32 q8, d19, d18" + - + asm_text: "vmlal.s32 q0, d5, d10[0]" + - + asm_text: "vqdmlal.s16 q8, d19, d18" + - + asm_text: "vqdmlal.s32 q8, d19, d18" + - + asm_text: "vqdmlal.s16 q11, d11, d7[0]" + - + asm_text: "vqdmlal.s16 q11, d11, d7[1]" + - + asm_text: "vqdmlal.s16 q11, d11, d7[2]" + - + asm_text: "vqdmlal.s16 q11, d11, d7[3]" + - + asm_text: "vmls.i8 d16, d18, d17" + - + asm_text: "vmls.i16 d16, d18, d17" + - + asm_text: "vmls.i32 d16, d18, d17" + - + asm_text: "vmls.f32 d16, d18, d17" + - + asm_text: "vmls.i8 q9, q8, q10" + - + asm_text: "vmls.i16 q9, q8, q10" + - + asm_text: "vmls.i32 q9, q8, q10" + - + asm_text: "vmls.f32 q9, q8, q10" + - + asm_text: "vmls.i16 q4, q12, d6[2]" + - + asm_text: "vmlsl.s8 q8, d19, d18" + - + asm_text: "vmlsl.s16 q8, d19, d18" + - + asm_text: "vmlsl.s32 q8, d19, d18" + - + asm_text: "vmlsl.u8 q8, d19, d18" + - + asm_text: "vmlsl.u16 q8, d19, d18" + - + asm_text: "vmlsl.u32 q8, d19, d18" + - + asm_text: "vmlsl.u16 q11, d25, d1[3]" + - + asm_text: "vqdmlsl.s16 q8, d19, d18" + - + asm_text: "vqdmlsl.s32 q8, d19, d18" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-mul-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-mul-encoding.s.yaml new file mode 100644 index 0000000..eb2b66b --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-mul-encoding.s.yaml @@ -0,0 +1,68 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xef, 0xb1, 0x09, 0x50, 0xef, 0xb1, 0x09, 0x60, 0xef, 0xb1, 0x09, 0x40, 0xff, 0xb1, 0x0d, 0x40, 0xef, 0xf2, 0x09, 0x50, 0xef, 0xf2, 0x09, 0x60, 0xef, 0xf2, 0x09, 0x40, 0xff, 0xf2, 0x0d, 0x40, 0xff, 0xb1, 0x09, 0x40, 0xff, 0xf2, 0x09, 0xd8, 0xef, 0x68, 0x28, 0x50, 0xef, 0xa1, 0x0b, 0x60, 0xef, 0xa1, 0x0b, 0x50, 0xef, 0xe2, 0x0b, 0x60, 0xef, 0xe2, 0x0b, 0x92, 0xef, 0x43, 0xbc, 0x50, 0xff, 0xa1, 0x0b, 0x60, 0xff, 0xa1, 0x0b, 0x50, 0xff, 0xe2, 0x0b, 0x60, 0xff, 0xe2, 0x0b, 0xc0, 0xef, 0xa1, 0x0c, 0xd0, 0xef, 0xa1, 0x0c, 0xe0, 0xef, 0xa1, 0x0c, 0xc0, 0xff, 0xa1, 0x0c, 0xd0, 0xff, 0xa1, 0x0c, 0xe0, 0xff, 0xa1, 0x0c, 0xc0, 0xef, 0xa1, 0x0e, 0xd0, 0xef, 0xa1, 0x0d, 0xe0, 0xef, 0xa1, 0x0d, 0x97, 0xef, 0x49, 0x2b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmul.i8 d16, d16, d17" + - + asm_text: "vmul.i16 d16, d16, d17" + - + asm_text: "vmul.i32 d16, d16, d17" + - + asm_text: "vmul.f32 d16, d16, d17" + - + asm_text: "vmul.i8 q8, q8, q9" + - + asm_text: "vmul.i16 q8, q8, q9" + - + asm_text: "vmul.i32 q8, q8, q9" + - + asm_text: "vmul.f32 q8, q8, q9" + - + asm_text: "vmul.p8 d16, d16, d17" + - + asm_text: "vmul.p8 q8, q8, q9" + - + asm_text: "vmul.i16 d18, d8, d0[3]" + - + asm_text: "vqdmulh.s16 d16, d16, d17" + - + asm_text: "vqdmulh.s32 d16, d16, d17" + - + asm_text: "vqdmulh.s16 q8, q8, q9" + - + asm_text: "vqdmulh.s32 q8, q8, q9" + - + asm_text: "vqdmulh.s16 d11, d2, d3[0]" + - + asm_text: "vqrdmulh.s16 d16, d16, d17" + - + asm_text: "vqrdmulh.s32 d16, d16, d17" + - + asm_text: "vqrdmulh.s16 q8, q8, q9" + - + asm_text: "vqrdmulh.s32 q8, q8, q9" + - + asm_text: "vmull.s8 q8, d16, d17" + - + asm_text: "vmull.s16 q8, d16, d17" + - + asm_text: "vmull.s32 q8, d16, d17" + - + asm_text: "vmull.u8 q8, d16, d17" + - + asm_text: "vmull.u16 q8, d16, d17" + - + asm_text: "vmull.u32 q8, d16, d17" + - + asm_text: "vmull.p8 q8, d16, d17" + - + asm_text: "vqdmull.s16 q8, d16, d17" + - + asm_text: "vqdmull.s32 q8, d16, d17" + - + asm_text: "vqdmull.s16 q1, d7, d1[1]" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-neg-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-neg-encoding.s.yaml new file mode 100644 index 0000000..0e303dd --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-neg-encoding.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0xf1, 0xff, 0xa0, 0x03, 0xf5, 0xff, 0xa0, 0x03, 0xf9, 0xff, 0xa0, 0x03, 0xf9, 0xff, 0xa0, 0x07, 0xf1, 0xff, 0xe0, 0x03, 0xf5, 0xff, 0xe0, 0x03, 0xf9, 0xff, 0xe0, 0x03, 0xf9, 0xff, 0xe0, 0x07, 0xf0, 0xff, 0xa0, 0x07, 0xf4, 0xff, 0xa0, 0x07, 0xf8, 0xff, 0xa0, 0x07, 0xf0, 0xff, 0xe0, 0x07, 0xf4, 0xff, 0xe0, 0x07, 0xf8, 0xff, 0xe0, 0x07 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vneg.s8 d16, d16" + - + asm_text: "vneg.s16 d16, d16" + - + asm_text: "vneg.s32 d16, d16" + - + asm_text: "vneg.f32 d16, d16" + - + asm_text: "vneg.s8 q8, q8" + - + asm_text: "vneg.s16 q8, q8" + - + asm_text: "vneg.s32 q8, q8" + - + asm_text: "vneg.f32 q8, q8" + - + asm_text: "vqneg.s8 d16, d16" + - + asm_text: "vqneg.s16 d16, d16" + - + asm_text: "vqneg.s32 d16, d16" + - + asm_text: "vqneg.s8 q8, q8" + - + asm_text: "vqneg.s16 q8, q8" + - + asm_text: "vqneg.s32 q8, q8" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-pairwise-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-pairwise-encoding.s.yaml new file mode 100644 index 0000000..b7fb1c8 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-pairwise-encoding.s.yaml @@ -0,0 +1,92 @@ +test_cases: + - + input: + bytes: [ 0x05, 0xef, 0x1b, 0x1b, 0x12, 0xef, 0x1c, 0xdb, 0x21, 0xef, 0x1d, 0xeb, 0x40, 0xff, 0x8e, 0x3d, 0xb0, 0xff, 0x0a, 0x72, 0xb4, 0xff, 0x0b, 0x82, 0xb8, 0xff, 0x0c, 0x92, 0xb0, 0xff, 0x8d, 0x02, 0xb4, 0xff, 0x8e, 0x52, 0xb8, 0xff, 0x8f, 0x62, 0xb0, 0xff, 0x4e, 0x82, 0xb4, 0xff, 0x4c, 0xa2, 0xb8, 0xff, 0x4a, 0xc2, 0xb0, 0xff, 0xc8, 0xe2, 0xf4, 0xff, 0xc6, 0x02, 0xf8, 0xff, 0xc4, 0x22, 0xf0, 0xff, 0x04, 0x06, 0xf4, 0xff, 0x09, 0x46, 0xf8, 0xff, 0x01, 0x26, 0xb0, 0xff, 0xa9, 0xe6, 0xb4, 0xff, 0x86, 0xc6, 0xb8, 0xff, 0x87, 0xb6, 0xb0, 0xff, 0x64, 0x86, 0xb4, 0xff, 0x66, 0xa6, 0xb8, 0xff, 0x68, 0xc6, 0xb0, 0xff, 0xea, 0xe6, 0xf4, 0xff, 0xec, 0x06, 0xf8, 0xff, 0xee, 0x26, 0x4d, 0xef, 0x9a, 0x0a, 0x5c, 0xef, 0x9b, 0x1a, 0x6b, 0xef, 0x9c, 0x2a, 0x4a, 0xff, 0x9d, 0x3a, 0x59, 0xff, 0x9e, 0x4a, 0x68, 0xff, 0x9f, 0x5a, 0x67, 0xff, 0xa0, 0x6f, 0x04, 0xef, 0xa1, 0x3a, 0x15, 0xef, 0xa0, 0x4a, 0x26, 0xef, 0x8f, 0x5a, 0x07, 0xff, 0x8e, 0x6a, 0x18, 0xff, 0x8d, 0x7a, 0x29, 0xff, 0x8c, 0x8a, 0x0a, 0xff, 0x8b, 0x9f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vpadd.i8 d1, d5, d11" + - + asm_text: "vpadd.i16 d13, d2, d12" + - + asm_text: "vpadd.i32 d14, d1, d13" + - + asm_text: "vpadd.f32 d19, d16, d14" + - + asm_text: "vpaddl.s8 d7, d10" + - + asm_text: "vpaddl.s16 d8, d11" + - + asm_text: "vpaddl.s32 d9, d12" + - + asm_text: "vpaddl.u8 d0, d13" + - + asm_text: "vpaddl.u16 d5, d14" + - + asm_text: "vpaddl.u32 d6, d15" + - + asm_text: "vpaddl.s8 q4, q7" + - + asm_text: "vpaddl.s16 q5, q6" + - + asm_text: "vpaddl.s32 q6, q5" + - + asm_text: "vpaddl.u8 q7, q4" + - + asm_text: "vpaddl.u16 q8, q3" + - + asm_text: "vpaddl.u32 q9, q2" + - + asm_text: "vpadal.s8 d16, d4" + - + asm_text: "vpadal.s16 d20, d9" + - + asm_text: "vpadal.s32 d18, d1" + - + asm_text: "vpadal.u8 d14, d25" + - + asm_text: "vpadal.u16 d12, d6" + - + asm_text: "vpadal.u32 d11, d7" + - + asm_text: "vpadal.s8 q4, q10" + - + asm_text: "vpadal.s16 q5, q11" + - + asm_text: "vpadal.s32 q6, q12" + - + asm_text: "vpadal.u8 q7, q13" + - + asm_text: "vpadal.u16 q8, q14" + - + asm_text: "vpadal.u32 q9, q15" + - + asm_text: "vpmin.s8 d16, d29, d10" + - + asm_text: "vpmin.s16 d17, d28, d11" + - + asm_text: "vpmin.s32 d18, d27, d12" + - + asm_text: "vpmin.u8 d19, d26, d13" + - + asm_text: "vpmin.u16 d20, d25, d14" + - + asm_text: "vpmin.u32 d21, d24, d15" + - + asm_text: "vpmin.f32 d22, d23, d16" + - + asm_text: "vpmax.s8 d3, d20, d17" + - + asm_text: "vpmax.s16 d4, d21, d16" + - + asm_text: "vpmax.s32 d5, d22, d15" + - + asm_text: "vpmax.u8 d6, d23, d14" + - + asm_text: "vpmax.u16 d7, d24, d13" + - + asm_text: "vpmax.u32 d8, d25, d12" + - + asm_text: "vpmax.f32 d9, d26, d11" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-reciprocal-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-reciprocal-encoding.s.yaml new file mode 100644 index 0000000..b44836b --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-reciprocal-encoding.s.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0xfb, 0xff, 0x20, 0x04, 0xfb, 0xff, 0x60, 0x04, 0xfb, 0xff, 0x20, 0x05, 0xfb, 0xff, 0x60, 0x05, 0x40, 0xef, 0xb1, 0x0f, 0x40, 0xef, 0xf2, 0x0f, 0xfb, 0xff, 0xa0, 0x04, 0xfb, 0xff, 0xe0, 0x04, 0xfb, 0xff, 0xa0, 0x05, 0xfb, 0xff, 0xe0, 0x05, 0x60, 0xef, 0xb1, 0x0f, 0x60, 0xef, 0xf2, 0x0f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vrecpe.u32 d16, d16" + - + asm_text: "vrecpe.u32 q8, q8" + - + asm_text: "vrecpe.f32 d16, d16" + - + asm_text: "vrecpe.f32 q8, q8" + - + asm_text: "vrecps.f32 d16, d16, d17" + - + asm_text: "vrecps.f32 q8, q8, q9" + - + asm_text: "vrsqrte.u32 d16, d16" + - + asm_text: "vrsqrte.u32 q8, q8" + - + asm_text: "vrsqrte.f32 d16, d16" + - + asm_text: "vrsqrte.f32 q8, q8" + - + asm_text: "vrsqrts.f32 d16, d16, d17" + - + asm_text: "vrsqrts.f32 q8, q8, q9" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-reverse-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-reverse-encoding.s.yaml new file mode 100644 index 0000000..d02f9b1 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-reverse-encoding.s.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0xf0, 0xff, 0x20, 0x00, 0xf4, 0xff, 0x20, 0x00, 0xf8, 0xff, 0x20, 0x00, 0xf0, 0xff, 0x60, 0x00, 0xf4, 0xff, 0x60, 0x00, 0xf8, 0xff, 0x60, 0x00, 0xf0, 0xff, 0xa0, 0x00, 0xf4, 0xff, 0xa0, 0x00, 0xf0, 0xff, 0xe0, 0x00, 0xf4, 0xff, 0xe0, 0x00, 0xf0, 0xff, 0x20, 0x01, 0xf0, 0xff, 0x60, 0x01 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vrev64.8 d16, d16" + - + asm_text: "vrev64.16 d16, d16" + - + asm_text: "vrev64.32 d16, d16" + - + asm_text: "vrev64.8 q8, q8" + - + asm_text: "vrev64.16 q8, q8" + - + asm_text: "vrev64.32 q8, q8" + - + asm_text: "vrev32.8 d16, d16" + - + asm_text: "vrev32.16 d16, d16" + - + asm_text: "vrev32.8 q8, q8" + - + asm_text: "vrev32.16 q8, q8" + - + asm_text: "vrev16.8 d16, d16" + - + asm_text: "vrev16.8 q8, q8" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-satshift-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-satshift-encoding.s.yaml new file mode 100644 index 0000000..8fb2e12 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-satshift-encoding.s.yaml @@ -0,0 +1,156 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xef, 0xb0, 0x04, 0x51, 0xef, 0xb0, 0x04, 0x61, 0xef, 0xb0, 0x04, 0x71, 0xef, 0xb0, 0x04, 0x41, 0xff, 0xb0, 0x04, 0x51, 0xff, 0xb0, 0x04, 0x61, 0xff, 0xb0, 0x04, 0x71, 0xff, 0xb0, 0x04, 0x42, 0xef, 0xf0, 0x04, 0x52, 0xef, 0xf0, 0x04, 0x62, 0xef, 0xf0, 0x04, 0x72, 0xef, 0xf0, 0x04, 0x42, 0xff, 0xf0, 0x04, 0x52, 0xff, 0xf0, 0x04, 0x62, 0xff, 0xf0, 0x04, 0x72, 0xff, 0xf0, 0x04, 0xcf, 0xef, 0x30, 0x07, 0xdf, 0xef, 0x30, 0x07, 0xff, 0xef, 0x30, 0x07, 0xff, 0xef, 0xb0, 0x07, 0xcf, 0xff, 0x30, 0x07, 0xdf, 0xff, 0x30, 0x07, 0xff, 0xff, 0x30, 0x07, 0xff, 0xff, 0xb0, 0x07, 0xcf, 0xff, 0x30, 0x06, 0xdf, 0xff, 0x30, 0x06, 0xff, 0xff, 0x30, 0x06, 0xff, 0xff, 0xb0, 0x06, 0xcf, 0xef, 0x70, 0x07, 0xdf, 0xef, 0x70, 0x07, 0xff, 0xef, 0x70, 0x07, 0xff, 0xef, 0xf0, 0x07, 0xcf, 0xff, 0x70, 0x07, 0xdf, 0xff, 0x70, 0x07, 0xff, 0xff, 0x70, 0x07, 0xff, 0xff, 0xf0, 0x07, 0xcf, 0xff, 0x70, 0x06, 0xdf, 0xff, 0x70, 0x06, 0xff, 0xff, 0x70, 0x06, 0xff, 0xff, 0xf0, 0x06, 0x41, 0xef, 0xb0, 0x05, 0x51, 0xef, 0xb0, 0x05, 0x61, 0xef, 0xb0, 0x05, 0x71, 0xef, 0xb0, 0x05, 0x41, 0xff, 0xb0, 0x05, 0x51, 0xff, 0xb0, 0x05, 0x61, 0xff, 0xb0, 0x05, 0x71, 0xff, 0xb0, 0x05, 0x42, 0xef, 0xf0, 0x05, 0x52, 0xef, 0xf0, 0x05, 0x62, 0xef, 0xf0, 0x05, 0x72, 0xef, 0xf0, 0x05, 0x42, 0xff, 0xf0, 0x05, 0x52, 0xff, 0xf0, 0x05, 0x62, 0xff, 0xf0, 0x05, 0x72, 0xff, 0xf0, 0x05, 0xc8, 0xef, 0x30, 0x09, 0xd0, 0xef, 0x30, 0x09, 0xe0, 0xef, 0x30, 0x09, 0xc8, 0xff, 0x30, 0x09, 0xd0, 0xff, 0x30, 0x09, 0xe0, 0xff, 0x30, 0x09, 0xc8, 0xff, 0x30, 0x08, 0xd0, 0xff, 0x30, 0x08, 0xe0, 0xff, 0x30, 0x08, 0xc8, 0xef, 0x70, 0x09, 0xd0, 0xef, 0x70, 0x09, 0xe0, 0xef, 0x70, 0x09, 0xc8, 0xff, 0x70, 0x09, 0xd0, 0xff, 0x70, 0x09, 0xe0, 0xff, 0x70, 0x09, 0xc8, 0xff, 0x70, 0x08, 0xd0, 0xff, 0x70, 0x08, 0xe0, 0xff, 0x70, 0x08 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vqshl.s8 d16, d16, d17" + - + asm_text: "vqshl.s16 d16, d16, d17" + - + asm_text: "vqshl.s32 d16, d16, d17" + - + asm_text: "vqshl.s64 d16, d16, d17" + - + asm_text: "vqshl.u8 d16, d16, d17" + - + asm_text: "vqshl.u16 d16, d16, d17" + - + asm_text: "vqshl.u32 d16, d16, d17" + - + asm_text: "vqshl.u64 d16, d16, d17" + - + asm_text: "vqshl.s8 q8, q8, q9" + - + asm_text: "vqshl.s16 q8, q8, q9" + - + asm_text: "vqshl.s32 q8, q8, q9" + - + asm_text: "vqshl.s64 q8, q8, q9" + - + asm_text: "vqshl.u8 q8, q8, q9" + - + asm_text: "vqshl.u16 q8, q8, q9" + - + asm_text: "vqshl.u32 q8, q8, q9" + - + asm_text: "vqshl.u64 q8, q8, q9" + - + asm_text: "vqshl.s8 d16, d16, #7" + - + asm_text: "vqshl.s16 d16, d16, #0xf" + - + asm_text: "vqshl.s32 d16, d16, #0x1f" + - + asm_text: "vqshl.s64 d16, d16, #0x3f" + - + asm_text: "vqshl.u8 d16, d16, #7" + - + asm_text: "vqshl.u16 d16, d16, #0xf" + - + asm_text: "vqshl.u32 d16, d16, #0x1f" + - + asm_text: "vqshl.u64 d16, d16, #0x3f" + - + asm_text: "vqshlu.s8 d16, d16, #7" + - + asm_text: "vqshlu.s16 d16, d16, #0xf" + - + asm_text: "vqshlu.s32 d16, d16, #0x1f" + - + asm_text: "vqshlu.s64 d16, d16, #0x3f" + - + asm_text: "vqshl.s8 q8, q8, #7" + - + asm_text: "vqshl.s16 q8, q8, #0xf" + - + asm_text: "vqshl.s32 q8, q8, #0x1f" + - + asm_text: "vqshl.s64 q8, q8, #0x3f" + - + asm_text: "vqshl.u8 q8, q8, #7" + - + asm_text: "vqshl.u16 q8, q8, #0xf" + - + asm_text: "vqshl.u32 q8, q8, #0x1f" + - + asm_text: "vqshl.u64 q8, q8, #0x3f" + - + asm_text: "vqshlu.s8 q8, q8, #7" + - + asm_text: "vqshlu.s16 q8, q8, #0xf" + - + asm_text: "vqshlu.s32 q8, q8, #0x1f" + - + asm_text: "vqshlu.s64 q8, q8, #0x3f" + - + asm_text: "vqrshl.s8 d16, d16, d17" + - + asm_text: "vqrshl.s16 d16, d16, d17" + - + asm_text: "vqrshl.s32 d16, d16, d17" + - + asm_text: "vqrshl.s64 d16, d16, d17" + - + asm_text: "vqrshl.u8 d16, d16, d17" + - + asm_text: "vqrshl.u16 d16, d16, d17" + - + asm_text: "vqrshl.u32 d16, d16, d17" + - + asm_text: "vqrshl.u64 d16, d16, d17" + - + asm_text: "vqrshl.s8 q8, q8, q9" + - + asm_text: "vqrshl.s16 q8, q8, q9" + - + asm_text: "vqrshl.s32 q8, q8, q9" + - + asm_text: "vqrshl.s64 q8, q8, q9" + - + asm_text: "vqrshl.u8 q8, q8, q9" + - + asm_text: "vqrshl.u16 q8, q8, q9" + - + asm_text: "vqrshl.u32 q8, q8, q9" + - + asm_text: "vqrshl.u64 q8, q8, q9" + - + asm_text: "vqshrn.s16 d16, q8, #8" + - + asm_text: "vqshrn.s32 d16, q8, #0x10" + - + asm_text: "vqshrn.s64 d16, q8, #0x20" + - + asm_text: "vqshrn.u16 d16, q8, #8" + - + asm_text: "vqshrn.u32 d16, q8, #0x10" + - + asm_text: "vqshrn.u64 d16, q8, #0x20" + - + asm_text: "vqshrun.s16 d16, q8, #8" + - + asm_text: "vqshrun.s32 d16, q8, #0x10" + - + asm_text: "vqshrun.s64 d16, q8, #0x20" + - + asm_text: "vqrshrn.s16 d16, q8, #8" + - + asm_text: "vqrshrn.s32 d16, q8, #0x10" + - + asm_text: "vqrshrn.s64 d16, q8, #0x20" + - + asm_text: "vqrshrn.u16 d16, q8, #8" + - + asm_text: "vqrshrn.u32 d16, q8, #0x10" + - + asm_text: "vqrshrn.u64 d16, q8, #0x20" + - + asm_text: "vqrshrun.s16 d16, q8, #8" + - + asm_text: "vqrshrun.s32 d16, q8, #0x10" + - + asm_text: "vqrshrun.s64 d16, q8, #0x20" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-shift-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-shift-encoding.s.yaml new file mode 100644 index 0000000..e3643a4 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-shift-encoding.s.yaml @@ -0,0 +1,166 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xff, 0xa1, 0x04, 0x50, 0xff, 0xa1, 0x04, 0x60, 0xff, 0xa1, 0x04, 0x70, 0xff, 0xa1, 0x04, 0xcf, 0xef, 0x30, 0x05, 0xdf, 0xef, 0x30, 0x05, 0xff, 0xef, 0x30, 0x05, 0xff, 0xef, 0xb0, 0x05, 0x40, 0xff, 0xe2, 0x04, 0x50, 0xff, 0xe2, 0x04, 0x60, 0xff, 0xe2, 0x04, 0x70, 0xff, 0xe2, 0x04, 0xcf, 0xef, 0x70, 0x05, 0xdf, 0xef, 0x70, 0x05, 0xff, 0xef, 0x70, 0x05, 0xff, 0xef, 0xf0, 0x05, 0xc8, 0xff, 0x30, 0x00, 0xd0, 0xff, 0x30, 0x00, 0xe0, 0xff, 0x30, 0x00, 0xc0, 0xff, 0xb0, 0x00, 0xc8, 0xff, 0x70, 0x00, 0xd0, 0xff, 0x70, 0x00, 0xe0, 0xff, 0x70, 0x00, 0xc0, 0xff, 0xf0, 0x00, 0xc8, 0xef, 0x30, 0x00, 0xd0, 0xef, 0x30, 0x00, 0xe0, 0xef, 0x30, 0x00, 0xc0, 0xef, 0xb0, 0x00, 0xc8, 0xef, 0x70, 0x00, 0xd0, 0xef, 0x70, 0x00, 0xe0, 0xef, 0x70, 0x00, 0xc0, 0xef, 0xf0, 0x00, 0xcf, 0xef, 0x30, 0x0a, 0xdf, 0xef, 0x30, 0x0a, 0xff, 0xef, 0x30, 0x0a, 0xcf, 0xff, 0x30, 0x0a, 0xdf, 0xff, 0x30, 0x0a, 0xff, 0xff, 0x30, 0x0a, 0xf2, 0xff, 0x20, 0x03, 0xf6, 0xff, 0x20, 0x03, 0xfa, 0xff, 0x20, 0x03, 0xc8, 0xef, 0x30, 0x08, 0xd0, 0xef, 0x30, 0x08, 0xe0, 0xef, 0x30, 0x08, 0x40, 0xef, 0xa1, 0x05, 0x50, 0xef, 0xa1, 0x05, 0x60, 0xef, 0xa1, 0x05, 0x70, 0xef, 0xa1, 0x05, 0x40, 0xff, 0xa1, 0x05, 0x50, 0xff, 0xa1, 0x05, 0x60, 0xff, 0xa1, 0x05, 0x70, 0xff, 0xa1, 0x05, 0x40, 0xef, 0xe2, 0x05, 0x50, 0xef, 0xe2, 0x05, 0x60, 0xef, 0xe2, 0x05, 0x70, 0xef, 0xe2, 0x05, 0x40, 0xff, 0xe2, 0x05, 0x50, 0xff, 0xe2, 0x05, 0x60, 0xff, 0xe2, 0x05, 0x70, 0xff, 0xe2, 0x05, 0xc8, 0xef, 0x30, 0x02, 0xd0, 0xef, 0x30, 0x02, 0xe0, 0xef, 0x30, 0x02, 0xc0, 0xef, 0xb0, 0x02, 0xc8, 0xff, 0x30, 0x02, 0xd0, 0xff, 0x30, 0x02, 0xe0, 0xff, 0x30, 0x02, 0xc0, 0xff, 0xb0, 0x02, 0xc8, 0xef, 0x70, 0x02, 0xd0, 0xef, 0x70, 0x02, 0xe0, 0xef, 0x70, 0x02, 0xc0, 0xef, 0xf0, 0x02, 0xc8, 0xff, 0x70, 0x02, 0xd0, 0xff, 0x70, 0x02, 0xe0, 0xff, 0x70, 0x02, 0xc0, 0xff, 0xf0, 0x02, 0xc8, 0xef, 0x70, 0x08, 0xd0, 0xef, 0x70, 0x08, 0xe0, 0xef, 0x70, 0x08 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vshl.u8 d16, d17, d16" + - + asm_text: "vshl.u16 d16, d17, d16" + - + asm_text: "vshl.u32 d16, d17, d16" + - + asm_text: "vshl.u64 d16, d17, d16" + - + asm_text: "vshl.i8 d16, d16, #7" + - + asm_text: "vshl.i16 d16, d16, #0xf" + - + asm_text: "vshl.i32 d16, d16, #0x1f" + - + asm_text: "vshl.i64 d16, d16, #0x3f" + - + asm_text: "vshl.u8 q8, q9, q8" + - + asm_text: "vshl.u16 q8, q9, q8" + - + asm_text: "vshl.u32 q8, q9, q8" + - + asm_text: "vshl.u64 q8, q9, q8" + - + asm_text: "vshl.i8 q8, q8, #7" + - + asm_text: "vshl.i16 q8, q8, #0xf" + - + asm_text: "vshl.i32 q8, q8, #0x1f" + - + asm_text: "vshl.i64 q8, q8, #0x3f" + - + asm_text: "vshr.u8 d16, d16, #8" + - + asm_text: "vshr.u16 d16, d16, #0x10" + - + asm_text: "vshr.u32 d16, d16, #0x20" + - + asm_text: "vshr.u64 d16, d16, #0x40" + - + asm_text: "vshr.u8 q8, q8, #8" + - + asm_text: "vshr.u16 q8, q8, #0x10" + - + asm_text: "vshr.u32 q8, q8, #0x20" + - + asm_text: "vshr.u64 q8, q8, #0x40" + - + asm_text: "vshr.s8 d16, d16, #8" + - + asm_text: "vshr.s16 d16, d16, #0x10" + - + asm_text: "vshr.s32 d16, d16, #0x20" + - + asm_text: "vshr.s64 d16, d16, #0x40" + - + asm_text: "vshr.s8 q8, q8, #8" + - + asm_text: "vshr.s16 q8, q8, #0x10" + - + asm_text: "vshr.s32 q8, q8, #0x20" + - + asm_text: "vshr.s64 q8, q8, #0x40" + - + asm_text: "vshll.s8 q8, d16, #7" + - + asm_text: "vshll.s16 q8, d16, #0xf" + - + asm_text: "vshll.s32 q8, d16, #0x1f" + - + asm_text: "vshll.u8 q8, d16, #7" + - + asm_text: "vshll.u16 q8, d16, #0xf" + - + asm_text: "vshll.u32 q8, d16, #0x1f" + - + asm_text: "vshll.i8 q8, d16, #8" + - + asm_text: "vshll.i16 q8, d16, #0x10" + - + asm_text: "vshll.i32 q8, d16, #0x20" + - + asm_text: "vshrn.i16 d16, q8, #8" + - + asm_text: "vshrn.i32 d16, q8, #0x10" + - + asm_text: "vshrn.i64 d16, q8, #0x20" + - + asm_text: "vrshl.s8 d16, d17, d16" + - + asm_text: "vrshl.s16 d16, d17, d16" + - + asm_text: "vrshl.s32 d16, d17, d16" + - + asm_text: "vrshl.s64 d16, d17, d16" + - + asm_text: "vrshl.u8 d16, d17, d16" + - + asm_text: "vrshl.u16 d16, d17, d16" + - + asm_text: "vrshl.u32 d16, d17, d16" + - + asm_text: "vrshl.u64 d16, d17, d16" + - + asm_text: "vrshl.s8 q8, q9, q8" + - + asm_text: "vrshl.s16 q8, q9, q8" + - + asm_text: "vrshl.s32 q8, q9, q8" + - + asm_text: "vrshl.s64 q8, q9, q8" + - + asm_text: "vrshl.u8 q8, q9, q8" + - + asm_text: "vrshl.u16 q8, q9, q8" + - + asm_text: "vrshl.u32 q8, q9, q8" + - + asm_text: "vrshl.u64 q8, q9, q8" + - + asm_text: "vrshr.s8 d16, d16, #8" + - + asm_text: "vrshr.s16 d16, d16, #0x10" + - + asm_text: "vrshr.s32 d16, d16, #0x20" + - + asm_text: "vrshr.s64 d16, d16, #0x40" + - + asm_text: "vrshr.u8 d16, d16, #8" + - + asm_text: "vrshr.u16 d16, d16, #0x10" + - + asm_text: "vrshr.u32 d16, d16, #0x20" + - + asm_text: "vrshr.u64 d16, d16, #0x40" + - + asm_text: "vrshr.s8 q8, q8, #8" + - + asm_text: "vrshr.s16 q8, q8, #0x10" + - + asm_text: "vrshr.s32 q8, q8, #0x20" + - + asm_text: "vrshr.s64 q8, q8, #0x40" + - + asm_text: "vrshr.u8 q8, q8, #8" + - + asm_text: "vrshr.u16 q8, q8, #0x10" + - + asm_text: "vrshr.u32 q8, q8, #0x20" + - + asm_text: "vrshr.u64 q8, q8, #0x40" + - + asm_text: "vrshrn.i16 d16, q8, #8" + - + asm_text: "vrshrn.i32 d16, q8, #0x10" + - + asm_text: "vrshrn.i64 d16, q8, #0x20" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-shiftaccum-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-shiftaccum-encoding.s.yaml new file mode 100644 index 0000000..79c71a7 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-shiftaccum-encoding.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xc8, 0xef, 0x30, 0x11, 0x90, 0xef, 0x1e, 0xf1, 0xa0, 0xef, 0x1c, 0xd1, 0x80, 0xef, 0x9a, 0xb1, 0x88, 0xef, 0x54, 0xe1, 0x90, 0xef, 0x5c, 0x61, 0xe0, 0xef, 0x5a, 0x21, 0xc0, 0xef, 0xd8, 0x01, 0xc8, 0xff, 0x30, 0x11, 0x95, 0xff, 0x1e, 0xb1, 0xaa, 0xff, 0x1f, 0xc1, 0x8a, 0xff, 0xb0, 0xd1, 0x88, 0xff, 0x5e, 0x21, 0x9a, 0xff, 0x5e, 0x41, 0xab, 0xff, 0x5c, 0x61, 0xa7, 0xff, 0xda, 0x81, 0xc8, 0xef, 0x30, 0x01, 0x90, 0xef, 0x1e, 0xe1, 0xa0, 0xef, 0x1c, 0xc1, 0x80, 0xef, 0x9a, 0xa1, 0x88, 0xef, 0x54, 0x41, 0x90, 0xef, 0x5c, 0xc1, 0xa0, 0xef, 0x5a, 0xa1, 0x80, 0xef, 0xd8, 0x81, 0xc8, 0xff, 0x30, 0x01, 0x95, 0xff, 0x1e, 0xe1, 0xaa, 0xff, 0x1f, 0xf1, 0xca, 0xff, 0xb0, 0x01, 0x88, 0xff, 0x5e, 0xe1, 0x9a, 0xff, 0x5e, 0xe1, 0xab, 0xff, 0x5c, 0xc1, 0xa7, 0xff, 0xda, 0xa1, 0x88, 0xef, 0x3a, 0x53, 0x90, 0xef, 0x39, 0x63, 0xa0, 0xef, 0x38, 0x73, 0x80, 0xef, 0xb7, 0xe3, 0x88, 0xff, 0x36, 0xf3, 0xd0, 0xff, 0x35, 0x03, 0xe0, 0xff, 0x34, 0x13, 0xc0, 0xff, 0xb3, 0x23, 0x88, 0xef, 0x54, 0x23, 0x90, 0xef, 0x56, 0x43, 0xa0, 0xef, 0x58, 0x63, 0x80, 0xef, 0xda, 0x83, 0x88, 0xff, 0x5c, 0xa3, 0x90, 0xff, 0x5e, 0xc3, 0xa0, 0xff, 0x70, 0xe3, 0xc0, 0xff, 0xf2, 0x03, 0xc8, 0xef, 0x3a, 0xa3, 0xd0, 0xef, 0x39, 0x93, 0xe0, 0xef, 0x38, 0x83, 0xc0, 0xef, 0xb7, 0x73, 0xc8, 0xff, 0x36, 0x63, 0xd0, 0xff, 0x35, 0x53, 0xe0, 0xff, 0x34, 0x43, 0xc0, 0xff, 0xb3, 0x33, 0x88, 0xef, 0x54, 0x43, 0x90, 0xef, 0x56, 0x63, 0xa0, 0xef, 0x58, 0x83, 0x80, 0xef, 0xda, 0xa3, 0x88, 0xff, 0x5c, 0xc3, 0x90, 0xff, 0x5e, 0xe3, 0xe0, 0xff, 0x70, 0x03, 0xc0, 0xff, 0xf2, 0x23, 0x8f, 0xff, 0x1c, 0xb5, 0x9f, 0xff, 0x1d, 0xc5, 0xbf, 0xff, 0x1e, 0xd5, 0xbf, 0xff, 0x9f, 0xe5, 0x8f, 0xff, 0x70, 0x25, 0x9f, 0xff, 0x5e, 0x45, 0xbf, 0xff, 0x58, 0x65, 0xbf, 0xff, 0xda, 0x85, 0xc8, 0xff, 0x1b, 0xc4, 0xd0, 0xff, 0x1c, 0xa4, 0xe0, 0xff, 0x1d, 0x84, 0xc0, 0xff, 0x9e, 0x54, 0x88, 0xff, 0x70, 0x24, 0x90, 0xff, 0x54, 0xa4, 0xa0, 0xff, 0x58, 0xe4, 0xc0, 0xff, 0xdc, 0x24, 0x8f, 0xff, 0x1c, 0xc5, 0x9f, 0xff, 0x1d, 0xd5, 0xbf, 0xff, 0x1e, 0xe5, 0xbf, 0xff, 0x9f, 0xf5, 0xcf, 0xff, 0x70, 0x05, 0x9f, 0xff, 0x5e, 0xe5, 0xbf, 0xff, 0x58, 0x85, 0xbf, 0xff, 0xda, 0xa5, 0x88, 0xff, 0x1b, 0xb4, 0x90, 0xff, 0x1c, 0xc4, 0xa0, 0xff, 0x1d, 0xd4, 0x80, 0xff, 0x9e, 0xe4, 0xc8, 0xff, 0x70, 0x04, 0x90, 0xff, 0x54, 0x44, 0xa0, 0xff, 0x58, 0x84, 0x80, 0xff, 0xdc, 0xc4 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vsra.s8 d17, d16, #8" + - + asm_text: "vsra.s16 d15, d14, #0x10" + - + asm_text: "vsra.s32 d13, d12, #0x20" + - + asm_text: "vsra.s64 d11, d10, #0x40" + - + asm_text: "vsra.s8 q7, q2, #8" + - + asm_text: "vsra.s16 q3, q6, #0x10" + - + asm_text: "vsra.s32 q9, q5, #0x20" + - + asm_text: "vsra.s64 q8, q4, #0x40" + - + asm_text: "vsra.u8 d17, d16, #8" + - + asm_text: "vsra.u16 d11, d14, #0xb" + - + asm_text: "vsra.u32 d12, d15, #0x16" + - + asm_text: "vsra.u64 d13, d16, #0x36" + - + asm_text: "vsra.u8 q1, q7, #8" + - + asm_text: "vsra.u16 q2, q7, #6" + - + asm_text: "vsra.u32 q3, q6, #0x15" + - + asm_text: "vsra.u64 q4, q5, #0x19" + - + asm_text: "vsra.s8 d16, d16, #8" + - + asm_text: "vsra.s16 d14, d14, #0x10" + - + asm_text: "vsra.s32 d12, d12, #0x20" + - + asm_text: "vsra.s64 d10, d10, #0x40" + - + asm_text: "vsra.s8 q2, q2, #8" + - + asm_text: "vsra.s16 q6, q6, #0x10" + - + asm_text: "vsra.s32 q5, q5, #0x20" + - + asm_text: "vsra.s64 q4, q4, #0x40" + - + asm_text: "vsra.u8 d16, d16, #8" + - + asm_text: "vsra.u16 d14, d14, #0xb" + - + asm_text: "vsra.u32 d15, d15, #0x16" + - + asm_text: "vsra.u64 d16, d16, #0x36" + - + asm_text: "vsra.u8 q7, q7, #8" + - + asm_text: "vsra.u16 q7, q7, #6" + - + asm_text: "vsra.u32 q6, q6, #0x15" + - + asm_text: "vsra.u64 q5, q5, #0x19" + - + asm_text: "vrsra.s8 d5, d26, #8" + - + asm_text: "vrsra.s16 d6, d25, #0x10" + - + asm_text: "vrsra.s32 d7, d24, #0x20" + - + asm_text: "vrsra.s64 d14, d23, #0x40" + - + asm_text: "vrsra.u8 d15, d22, #8" + - + asm_text: "vrsra.u16 d16, d21, #0x10" + - + asm_text: "vrsra.u32 d17, d20, #0x20" + - + asm_text: "vrsra.u64 d18, d19, #0x40" + - + asm_text: "vrsra.s8 q1, q2, #8" + - + asm_text: "vrsra.s16 q2, q3, #0x10" + - + asm_text: "vrsra.s32 q3, q4, #0x20" + - + asm_text: "vrsra.s64 q4, q5, #0x40" + - + asm_text: "vrsra.u8 q5, q6, #8" + - + asm_text: "vrsra.u16 q6, q7, #0x10" + - + asm_text: "vrsra.u32 q7, q8, #0x20" + - + asm_text: "vrsra.u64 q8, q9, #0x40" + - + asm_text: "vrsra.s8 d26, d26, #8" + - + asm_text: "vrsra.s16 d25, d25, #0x10" + - + asm_text: "vrsra.s32 d24, d24, #0x20" + - + asm_text: "vrsra.s64 d23, d23, #0x40" + - + asm_text: "vrsra.u8 d22, d22, #8" + - + asm_text: "vrsra.u16 d21, d21, #0x10" + - + asm_text: "vrsra.u32 d20, d20, #0x20" + - + asm_text: "vrsra.u64 d19, d19, #0x40" + - + asm_text: "vrsra.s8 q2, q2, #8" + - + asm_text: "vrsra.s16 q3, q3, #0x10" + - + asm_text: "vrsra.s32 q4, q4, #0x20" + - + asm_text: "vrsra.s64 q5, q5, #0x40" + - + asm_text: "vrsra.u8 q6, q6, #8" + - + asm_text: "vrsra.u16 q7, q7, #0x10" + - + asm_text: "vrsra.u32 q8, q8, #0x20" + - + asm_text: "vrsra.u64 q9, q9, #0x40" + - + asm_text: "vsli.8 d11, d12, #7" + - + asm_text: "vsli.16 d12, d13, #0xf" + - + asm_text: "vsli.32 d13, d14, #0x1f" + - + asm_text: "vsli.64 d14, d15, #0x3f" + - + asm_text: "vsli.8 q1, q8, #7" + - + asm_text: "vsli.16 q2, q7, #0xf" + - + asm_text: "vsli.32 q3, q4, #0x1f" + - + asm_text: "vsli.64 q4, q5, #0x3f" + - + asm_text: "vsri.8 d28, d11, #8" + - + asm_text: "vsri.16 d26, d12, #0x10" + - + asm_text: "vsri.32 d24, d13, #0x20" + - + asm_text: "vsri.64 d21, d14, #0x40" + - + asm_text: "vsri.8 q1, q8, #8" + - + asm_text: "vsri.16 q5, q2, #0x10" + - + asm_text: "vsri.32 q7, q4, #0x20" + - + asm_text: "vsri.64 q9, q6, #0x40" + - + asm_text: "vsli.8 d12, d12, #7" + - + asm_text: "vsli.16 d13, d13, #0xf" + - + asm_text: "vsli.32 d14, d14, #0x1f" + - + asm_text: "vsli.64 d15, d15, #0x3f" + - + asm_text: "vsli.8 q8, q8, #7" + - + asm_text: "vsli.16 q7, q7, #0xf" + - + asm_text: "vsli.32 q4, q4, #0x1f" + - + asm_text: "vsli.64 q5, q5, #0x3f" + - + asm_text: "vsri.8 d11, d11, #8" + - + asm_text: "vsri.16 d12, d12, #0x10" + - + asm_text: "vsri.32 d13, d13, #0x20" + - + asm_text: "vsri.64 d14, d14, #0x40" + - + asm_text: "vsri.8 q8, q8, #8" + - + asm_text: "vsri.16 q2, q2, #0x10" + - + asm_text: "vsri.32 q4, q4, #0x20" + - + asm_text: "vsri.64 q6, q6, #0x40" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-shuffle-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-shuffle-encoding.s.yaml new file mode 100644 index 0000000..f4c00eb --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-shuffle-encoding.s.yaml @@ -0,0 +1,52 @@ +test_cases: + - + input: + bytes: [ 0xf1, 0xef, 0xa0, 0x03, 0xf1, 0xef, 0xa0, 0x05, 0xf2, 0xef, 0xe0, 0x03, 0xf2, 0xef, 0xe0, 0x07, 0xf1, 0xef, 0xa0, 0x06, 0xf2, 0xef, 0xe0, 0x0c, 0xf2, 0xff, 0xa0, 0x10, 0xf6, 0xff, 0xa0, 0x10, 0xfa, 0xff, 0xa0, 0x10, 0xf2, 0xff, 0xe0, 0x20, 0xf6, 0xff, 0xe0, 0x20, 0xfa, 0xff, 0xe0, 0x20, 0xf2, 0xff, 0x20, 0x11, 0xf6, 0xff, 0x20, 0x11, 0xf2, 0xff, 0x60, 0x21, 0xf6, 0xff, 0x60, 0x21, 0xfa, 0xff, 0x60, 0x21, 0xf2, 0xff, 0xa0, 0x11, 0xf6, 0xff, 0xa0, 0x11, 0xf2, 0xff, 0xe0, 0x21, 0xf6, 0xff, 0xe0, 0x21, 0xfa, 0xff, 0xe0, 0x21 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vext.8 d16, d17, d16, #3" + - + asm_text: "vext.8 d16, d17, d16, #5" + - + asm_text: "vext.8 q8, q9, q8, #3" + - + asm_text: "vext.8 q8, q9, q8, #7" + - + asm_text: "vext.16 d16, d17, d16, #3" + - + asm_text: "vext.32 q8, q9, q8, #3" + - + asm_text: "vtrn.8 d17, d16" + - + asm_text: "vtrn.16 d17, d16" + - + asm_text: "vtrn.32 d17, d16" + - + asm_text: "vtrn.8 q9, q8" + - + asm_text: "vtrn.16 q9, q8" + - + asm_text: "vtrn.32 q9, q8" + - + asm_text: "vuzp.8 d17, d16" + - + asm_text: "vuzp.16 d17, d16" + - + asm_text: "vuzp.8 q9, q8" + - + asm_text: "vuzp.16 q9, q8" + - + asm_text: "vuzp.32 q9, q8" + - + asm_text: "vzip.8 d17, d16" + - + asm_text: "vzip.16 d17, d16" + - + asm_text: "vzip.8 q9, q8" + - + asm_text: "vzip.16 q9, q8" + - + asm_text: "vzip.32 q9, q8" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-sub-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-sub-encoding.s.yaml new file mode 100644 index 0000000..f4c00eb --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-sub-encoding.s.yaml @@ -0,0 +1,52 @@ +test_cases: + - + input: + bytes: [ 0xf1, 0xef, 0xa0, 0x03, 0xf1, 0xef, 0xa0, 0x05, 0xf2, 0xef, 0xe0, 0x03, 0xf2, 0xef, 0xe0, 0x07, 0xf1, 0xef, 0xa0, 0x06, 0xf2, 0xef, 0xe0, 0x0c, 0xf2, 0xff, 0xa0, 0x10, 0xf6, 0xff, 0xa0, 0x10, 0xfa, 0xff, 0xa0, 0x10, 0xf2, 0xff, 0xe0, 0x20, 0xf6, 0xff, 0xe0, 0x20, 0xfa, 0xff, 0xe0, 0x20, 0xf2, 0xff, 0x20, 0x11, 0xf6, 0xff, 0x20, 0x11, 0xf2, 0xff, 0x60, 0x21, 0xf6, 0xff, 0x60, 0x21, 0xfa, 0xff, 0x60, 0x21, 0xf2, 0xff, 0xa0, 0x11, 0xf6, 0xff, 0xa0, 0x11, 0xf2, 0xff, 0xe0, 0x21, 0xf6, 0xff, 0xe0, 0x21, 0xfa, 0xff, 0xe0, 0x21 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vext.8 d16, d17, d16, #3" + - + asm_text: "vext.8 d16, d17, d16, #5" + - + asm_text: "vext.8 q8, q9, q8, #3" + - + asm_text: "vext.8 q8, q9, q8, #7" + - + asm_text: "vext.16 d16, d17, d16, #3" + - + asm_text: "vext.32 q8, q9, q8, #3" + - + asm_text: "vtrn.8 d17, d16" + - + asm_text: "vtrn.16 d17, d16" + - + asm_text: "vtrn.32 d17, d16" + - + asm_text: "vtrn.8 q9, q8" + - + asm_text: "vtrn.16 q9, q8" + - + asm_text: "vtrn.32 q9, q8" + - + asm_text: "vuzp.8 d17, d16" + - + asm_text: "vuzp.16 d17, d16" + - + asm_text: "vuzp.8 q9, q8" + - + asm_text: "vuzp.16 q9, q8" + - + asm_text: "vuzp.32 q9, q8" + - + asm_text: "vzip.8 d17, d16" + - + asm_text: "vzip.16 d17, d16" + - + asm_text: "vzip.8 q9, q8" + - + asm_text: "vzip.16 q9, q8" + - + asm_text: "vzip.32 q9, q8" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-table-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-table-encoding.s.yaml new file mode 100644 index 0000000..11fbd48 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-table-encoding.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0xf1, 0xff, 0xa0, 0x08, 0xf0, 0xff, 0xa2, 0x09, 0xf0, 0xff, 0xa4, 0x0a, 0xf0, 0xff, 0xa4, 0x0b, 0xf0, 0xff, 0xe1, 0x28, 0xf0, 0xff, 0xe2, 0x39, 0xf0, 0xff, 0xe5, 0x4a, 0xf0, 0xff, 0xe5, 0x4b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vtbl.8 d16, {d17}, d16" + - + asm_text: "vtbl.8 d16, {d16, d17}, d18" + - + asm_text: "vtbl.8 d16, {d16, d17, d18}, d20" + - + asm_text: "vtbl.8 d16, {d16, d17, d18, d19}, d20" + - + asm_text: "vtbx.8 d18, {d16}, d17" + - + asm_text: "vtbx.8 d19, {d16, d17}, d18" + - + asm_text: "vtbx.8 d20, {d16, d17, d18}, d21" + - + asm_text: "vtbx.8 d20, {d16, d17, d18, d19}, d21" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-vld-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-vld-encoding.s.yaml new file mode 100644 index 0000000..78ded52 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-vld-encoding.s.yaml @@ -0,0 +1,108 @@ +test_cases: + - + input: + bytes: [ 0x60, 0xf9, 0x1f, 0x07, 0x60, 0xf9, 0x4f, 0x07, 0x60, 0xf9, 0x8f, 0x07, 0x60, 0xf9, 0xcf, 0x07, 0x60, 0xf9, 0x1f, 0x0a, 0x60, 0xf9, 0x6f, 0x0a, 0x60, 0xf9, 0x8f, 0x0a, 0x60, 0xf9, 0xcf, 0x0a, 0x60, 0xf9, 0x1f, 0x08, 0x60, 0xf9, 0x6f, 0x08, 0x60, 0xf9, 0x8f, 0x08, 0x60, 0xf9, 0x1f, 0x03, 0x60, 0xf9, 0x6f, 0x03, 0x60, 0xf9, 0xbf, 0x03, 0x60, 0xf9, 0x1f, 0x04, 0x60, 0xf9, 0x4f, 0x04, 0x60, 0xf9, 0x8f, 0x04, 0x60, 0xf9, 0x1d, 0x05, 0x60, 0xf9, 0x1d, 0x15, 0x60, 0xf9, 0x4d, 0x05, 0x60, 0xf9, 0x4d, 0x15, 0x60, 0xf9, 0x8d, 0x05, 0x60, 0xf9, 0x8d, 0x15, 0x60, 0xf9, 0x1f, 0x00, 0x60, 0xf9, 0x6f, 0x00, 0x60, 0xf9, 0xbf, 0x00, 0x60, 0xf9, 0x3d, 0x01, 0x60, 0xf9, 0x3d, 0x11, 0x60, 0xf9, 0x4d, 0x01, 0x60, 0xf9, 0x4d, 0x11, 0x60, 0xf9, 0x8d, 0x01, 0x60, 0xf9, 0x8d, 0x11, 0xe0, 0xf9, 0x6f, 0x00, 0xe0, 0xf9, 0x9f, 0x04, 0xe0, 0xf9, 0xbf, 0x08, 0xe0, 0xf9, 0x3f, 0x01, 0xe0, 0xf9, 0x5f, 0x05, 0xe0, 0xf9, 0x8f, 0x09, 0xe0, 0xf9, 0x6f, 0x15, 0xe0, 0xf9, 0x5f, 0x19, 0xe0, 0xf9, 0x2f, 0x02, 0xe0, 0xf9, 0x4f, 0x06, 0xe0, 0xf9, 0x8f, 0x0a, 0xe0, 0xf9, 0x6f, 0x06, 0xe0, 0xf9, 0xcf, 0x1a, 0xe0, 0xf9, 0x3f, 0x03, 0xe0, 0xf9, 0x4f, 0x07, 0xe0, 0xf9, 0xaf, 0x0b, 0xe0, 0xf9, 0x7f, 0x07, 0xe0, 0xf9, 0x4f, 0x1b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vld1.8 {d16}, [r0:64]" + - + asm_text: "vld1.16 {d16}, [r0]" + - + asm_text: "vld1.32 {d16}, [r0]" + - + asm_text: "vld1.64 {d16}, [r0]" + - + asm_text: "vld1.8 {d16, d17}, [r0:64]" + - + asm_text: "vld1.16 {d16, d17}, [r0:128]" + - + asm_text: "vld1.32 {d16, d17}, [r0]" + - + asm_text: "vld1.64 {d16, d17}, [r0]" + - + asm_text: "vld2.8 {d16, d17}, [r0:64]" + - + asm_text: "vld2.16 {d16, d17}, [r0:128]" + - + asm_text: "vld2.32 {d16, d17}, [r0]" + - + asm_text: "vld2.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vld2.16 {d16, d17, d18, d19}, [r0:128]" + - + asm_text: "vld2.32 {d16, d17, d18, d19}, [r0:256]" + - + asm_text: "vld3.8 {d16, d17, d18}, [r0:64]" + - + asm_text: "vld3.16 {d16, d17, d18}, [r0]" + - + asm_text: "vld3.32 {d16, d17, d18}, [r0]" + - + asm_text: "vld3.8 {d16, d18, d20}, [r0:64]!" + - + asm_text: "vld3.8 {d17, d19, d21}, [r0:64]!" + - + asm_text: "vld3.16 {d16, d18, d20}, [r0]!" + - + asm_text: "vld3.16 {d17, d19, d21}, [r0]!" + - + asm_text: "vld3.32 {d16, d18, d20}, [r0]!" + - + asm_text: "vld3.32 {d17, d19, d21}, [r0]!" + - + asm_text: "vld4.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vld4.16 {d16, d17, d18, d19}, [r0:128]" + - + asm_text: "vld4.32 {d16, d17, d18, d19}, [r0:256]" + - + asm_text: "vld4.8 {d16, d18, d20, d22}, [r0:256]!" + - + asm_text: "vld4.8 {d17, d19, d21, d23}, [r0:256]!" + - + asm_text: "vld4.16 {d16, d18, d20, d22}, [r0]!" + - + asm_text: "vld4.16 {d17, d19, d21, d23}, [r0]!" + - + asm_text: "vld4.32 {d16, d18, d20, d22}, [r0]!" + - + asm_text: "vld4.32 {d17, d19, d21, d23}, [r0]!" + - + asm_text: "vld1.8 {d16[3]}, [r0]" + - + asm_text: "vld1.16 {d16[2]}, [r0:16]" + - + asm_text: "vld1.32 {d16[1]}, [r0:32]" + - + asm_text: "vld2.8 {d16[1], d17[1]}, [r0:16]" + - + asm_text: "vld2.16 {d16[1], d17[1]}, [r0:32]" + - + asm_text: "vld2.32 {d16[1], d17[1]}, [r0]" + - + asm_text: "vld2.16 {d17[1], d19[1]}, [r0]" + - + asm_text: "vld2.32 {d17[0], d19[0]}, [r0:64]" + - + asm_text: "vld3.8 {d16[1], d17[1], d18[1]}, [r0]" + - + asm_text: "vld3.16 {d16[1], d17[1], d18[1]}, [r0]" + - + asm_text: "vld3.32 {d16[1], d17[1], d18[1]}, [r0]" + - + asm_text: "vld3.16 {d16[1], d18[1], d20[1]}, [r0]" + - + asm_text: "vld3.32 {d17[1], d19[1], d21[1]}, [r0]" + - + asm_text: "vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]" + - + asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]" + - + asm_text: "vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]" + - + asm_text: "vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64]" + - + asm_text: "vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]" diff --git a/thirdparty/capstone/tests/MC/ARM/neont2-vst-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/neont2-vst-encoding.s.yaml new file mode 100644 index 0000000..91ffb02 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/neont2-vst-encoding.s.yaml @@ -0,0 +1,102 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xf9, 0x1f, 0x07, 0x40, 0xf9, 0x4f, 0x07, 0x40, 0xf9, 0x8f, 0x07, 0x40, 0xf9, 0xcf, 0x07, 0x40, 0xf9, 0x1f, 0x0a, 0x40, 0xf9, 0x6f, 0x0a, 0x40, 0xf9, 0x8f, 0x0a, 0x40, 0xf9, 0xcf, 0x0a, 0x40, 0xf9, 0x1f, 0x08, 0x40, 0xf9, 0x6f, 0x08, 0x40, 0xf9, 0x8f, 0x08, 0x40, 0xf9, 0x1f, 0x03, 0x40, 0xf9, 0x6f, 0x03, 0x40, 0xf9, 0xbf, 0x03, 0x40, 0xf9, 0x1f, 0x04, 0x40, 0xf9, 0x4f, 0x04, 0x40, 0xf9, 0x8f, 0x04, 0x40, 0xf9, 0x1d, 0x05, 0x40, 0xf9, 0x1d, 0x15, 0x40, 0xf9, 0x4d, 0x05, 0x40, 0xf9, 0x4d, 0x15, 0x40, 0xf9, 0x8d, 0x05, 0x40, 0xf9, 0x8d, 0x15, 0x40, 0xf9, 0x1f, 0x00, 0x40, 0xf9, 0x6f, 0x00, 0x40, 0xf9, 0x3d, 0x01, 0x40, 0xf9, 0x3d, 0x11, 0x40, 0xf9, 0x4d, 0x01, 0x40, 0xf9, 0x4d, 0x11, 0x40, 0xf9, 0x8d, 0x01, 0x40, 0xf9, 0x8d, 0x11, 0xc0, 0xf9, 0x3f, 0x01, 0xc0, 0xf9, 0x5f, 0x05, 0xc0, 0xf9, 0x8f, 0x09, 0xc0, 0xf9, 0x6f, 0x15, 0xc0, 0xf9, 0x5f, 0x19, 0xc0, 0xf9, 0x2f, 0x02, 0xc0, 0xf9, 0x4f, 0x06, 0xc0, 0xf9, 0x8f, 0x0a, 0xc0, 0xf9, 0xaf, 0x16, 0xc0, 0xf9, 0x4f, 0x0a, 0xc0, 0xf9, 0x3f, 0x03, 0xc0, 0xf9, 0x4f, 0x07, 0xc0, 0xf9, 0xaf, 0x0b, 0xc0, 0xf9, 0xff, 0x17, 0xc0, 0xf9, 0x4f, 0x1b, 0x04, 0xf9, 0x0f, 0x89 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vst1.8 {d16}, [r0:64]" + - + asm_text: "vst1.16 {d16}, [r0]" + - + asm_text: "vst1.32 {d16}, [r0]" + - + asm_text: "vst1.64 {d16}, [r0]" + - + asm_text: "vst1.8 {d16, d17}, [r0:64]" + - + asm_text: "vst1.16 {d16, d17}, [r0:128]" + - + asm_text: "vst1.32 {d16, d17}, [r0]" + - + asm_text: "vst1.64 {d16, d17}, [r0]" + - + asm_text: "vst2.8 {d16, d17}, [r0:64]" + - + asm_text: "vst2.16 {d16, d17}, [r0:128]" + - + asm_text: "vst2.32 {d16, d17}, [r0]" + - + asm_text: "vst2.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vst2.16 {d16, d17, d18, d19}, [r0:128]" + - + asm_text: "vst2.32 {d16, d17, d18, d19}, [r0:256]" + - + asm_text: "vst3.8 {d16, d17, d18}, [r0:64]" + - + asm_text: "vst3.16 {d16, d17, d18}, [r0]" + - + asm_text: "vst3.32 {d16, d17, d18}, [r0]" + - + asm_text: "vst3.8 {d16, d18, d20}, [r0:64]!" + - + asm_text: "vst3.8 {d17, d19, d21}, [r0:64]!" + - + asm_text: "vst3.16 {d16, d18, d20}, [r0]!" + - + asm_text: "vst3.16 {d17, d19, d21}, [r0]!" + - + asm_text: "vst3.32 {d16, d18, d20}, [r0]!" + - + asm_text: "vst3.32 {d17, d19, d21}, [r0]!" + - + asm_text: "vst4.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vst4.16 {d16, d17, d18, d19}, [r0:128]" + - + asm_text: "vst4.8 {d16, d18, d20, d22}, [r0:256]!" + - + asm_text: "vst4.8 {d17, d19, d21, d23}, [r0:256]!" + - + asm_text: "vst4.16 {d16, d18, d20, d22}, [r0]!" + - + asm_text: "vst4.16 {d17, d19, d21, d23}, [r0]!" + - + asm_text: "vst4.32 {d16, d18, d20, d22}, [r0]!" + - + asm_text: "vst4.32 {d17, d19, d21, d23}, [r0]!" + - + asm_text: "vst2.8 {d16[1], d17[1]}, [r0:16]" + - + asm_text: "vst2.16 {d16[1], d17[1]}, [r0:32]" + - + asm_text: "vst2.32 {d16[1], d17[1]}, [r0]" + - + asm_text: "vst2.16 {d17[1], d19[1]}, [r0]" + - + asm_text: "vst2.32 {d17[0], d19[0]}, [r0:64]" + - + asm_text: "vst3.8 {d16[1], d17[1], d18[1]}, [r0]" + - + asm_text: "vst3.16 {d16[1], d17[1], d18[1]}, [r0]" + - + asm_text: "vst3.32 {d16[1], d17[1], d18[1]}, [r0]" + - + asm_text: "vst3.16 {d17[2], d19[2], d21[2]}, [r0]" + - + asm_text: "vst3.32 {d16[0], d18[0], d20[0]}, [r0]" + - + asm_text: "vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]" + - + asm_text: "vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]" + - + asm_text: "vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]" + - + asm_text: "vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]" + - + asm_text: "vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]" + - + asm_text: "vst2.8 {d8, d10}, [r4]" diff --git a/thirdparty/capstone/tests/MC/ARM/simple-fp-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/simple-fp-encoding.s.yaml new file mode 100644 index 0000000..0775016 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/simple-fp-encoding.s.yaml @@ -0,0 +1,360 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x0b, 0x71, 0xee, 0x80, 0x0a, 0x30, 0xee, 0xe0, 0x0b, 0x71, 0xee, 0xc0, 0x0a, 0x30, 0xee, 0xa0, 0x0b, 0xc1, 0xee, 0x80, 0x0a, 0x80, 0xee, 0xa3, 0x2a, 0xc2, 0xee, 0x07, 0x5b, 0x85, 0xee, 0xa0, 0x0b, 0x61, 0xee, 0xa1, 0x4b, 0x64, 0xee, 0x80, 0x0a, 0x20, 0xee, 0xaa, 0x5a, 0x65, 0xee, 0xe0, 0x0b, 0x61, 0xee, 0xc0, 0x0a, 0x20, 0xee, 0x60, 0x1b, 0xf4, 0xee, 0x40, 0x0a, 0xf4, 0xee, 0x40, 0x1b, 0xf5, 0xee, 0x40, 0x0a, 0xf5, 0xee, 0xe0, 0x1b, 0xf4, 0xee, 0xc0, 0x0a, 0xf4, 0xee, 0xc0, 0x0b, 0xf5, 0xee, 0xc0, 0x0a, 0xb5, 0xee, 0xe0, 0x0b, 0xf0, 0xee, 0xc0, 0x0a, 0xb0, 0xee, 0xe0, 0x0b, 0xb7, 0xee, 0xc0, 0x0a, 0xf7, 0xee, 0x60, 0x0b, 0xf1, 0xee, 0x40, 0x0a, 0xb1, 0xee, 0xe0, 0x0b, 0xf1, 0xee, 0xc0, 0x0a, 0xb1, 0xee, 0xc0, 0x0b, 0xf8, 0xee, 0xc0, 0x0a, 0xb8, 0xee, 0x40, 0x0b, 0xf8, 0xee, 0x40, 0x0a, 0xb8, 0xee, 0xe0, 0x0b, 0xbd, 0xee, 0xc0, 0x0a, 0xbd, 0xee, 0xe0, 0x0b, 0xbc, 0xee, 0xc0, 0x0a, 0xbc, 0xee, 0xa1, 0x0b, 0x42, 0xee, 0x00, 0x0a, 0x41, 0xee, 0xe1, 0x0b, 0x42, 0xee, 0x40, 0x0a, 0x41, 0xee, 0xe1, 0x0b, 0x52, 0xee, 0x40, 0x0a, 0x51, 0xee, 0xa1, 0x0b, 0x52, 0xee, 0x00, 0x0a, 0x51, 0xee, 0x10, 0xfa, 0xf1, 0xee, 0x10, 0xfa, 0xf1, 0xee, 0x10, 0xfa, 0xf1, 0xee, 0x10, 0x2a, 0xf0, 0xee, 0x10, 0x3a, 0xf0, 0xee, 0x10, 0x4a, 0xf7, 0xee, 0x10, 0x5a, 0xf6, 0xee, 0x60, 0x0b, 0xf1, 0x1e, 0x10, 0x0a, 0x00, 0x1e, 0x10, 0x1a, 0x00, 0x0e, 0x10, 0x1a, 0x11, 0xee, 0x10, 0x3a, 0x02, 0xee, 0x12, 0x1b, 0x55, 0xec, 0x14, 0x3b, 0x49, 0xec, 0x10, 0x0a, 0xf1, 0xee, 0x10, 0x0a, 0xf8, 0xee, 0x10, 0x0a, 0xf0, 0xee, 0x10, 0x1a, 0xf9, 0xee, 0x10, 0x8a, 0xfa, 0xee, 0x10, 0x0a, 0xe1, 0xee, 0x10, 0x0a, 0xe8, 0xee, 0x10, 0x0a, 0xe0, 0xee, 0x10, 0x3a, 0xe9, 0xee, 0x10, 0x4a, 0xea, 0xee, 0x08, 0x0b, 0xf0, 0xee, 0x08, 0x0a, 0xb0, 0xee, 0x08, 0x0b, 0xf8, 0xee, 0x08, 0x0a, 0xb8, 0xee, 0x10, 0x0a, 0x00, 0xee, 0x90, 0x1a, 0x00, 0xee, 0x10, 0x2a, 0x01, 0xee, 0x90, 0x3a, 0x01, 0xee, 0x10, 0x0a, 0x10, 0xee, 0x90, 0x1a, 0x10, 0xee, 0x10, 0x2a, 0x11, 0xee, 0x90, 0x3a, 0x11, 0xee, 0x30, 0x0b, 0x51, 0xec, 0x31, 0x1a, 0x42, 0xec, 0x11, 0x1a, 0x42, 0xec, 0x31, 0x1a, 0x52, 0xec, 0x11, 0x1a, 0x52, 0xec, 0x1f, 0x1b, 0x42, 0xec, 0x30, 0x1b, 0x42, 0xec, 0x1f, 0x1b, 0x52, 0xec, 0x30, 0x1b, 0x52, 0xec, 0x00, 0x1b, 0xd0, 0xed, 0x00, 0x0a, 0x9e, 0xed, 0x00, 0x0b, 0x9e, 0xed, 0x08, 0x1b, 0x92, 0xed, 0x08, 0x1b, 0x12, 0xed, 0x00, 0x2b, 0x93, 0xed, 0x00, 0x3b, 0x9f, 0xed, 0x00, 0x3b, 0x9f, 0xed, 0x00, 0x3b, 0x1f, 0xed, 0x00, 0x6a, 0xd0, 0xed, 0x08, 0x0a, 0xd2, 0xed, 0x08, 0x0a, 0x52, 0xed, 0x00, 0x1a, 0x93, 0xed, 0x00, 0x2a, 0xdf, 0xed, 0x00, 0x2a, 0xdf, 0xed, 0x00, 0x2a, 0x5f, 0xed, 0x00, 0x4b, 0x81, 0xed, 0x06, 0x4b, 0x81, 0xed, 0x06, 0x4b, 0x01, 0xed, 0x00, 0x0a, 0x8e, 0xed, 0x00, 0x0b, 0x8e, 0xed, 0x00, 0x2a, 0x81, 0xed, 0x06, 0x2a, 0x81, 0xed, 0x06, 0x2a, 0x01, 0xed, 0x0c, 0x2b, 0x91, 0xec, 0x06, 0x1a, 0x91, 0xec, 0x0c, 0x2b, 0x81, 0xec, 0x06, 0x1a, 0x81, 0xec, 0x10, 0x8b, 0x2d, 0xed, 0x07, 0x0b, 0xb5, 0xec, 0x05, 0x4b, 0x90, 0x0c, 0x07, 0x4b, 0x35, 0x1d, 0x11, 0x0b, 0xa5, 0xec, 0x05, 0x8b, 0x84, 0x0c, 0x07, 0x2b, 0x27, 0x1d, 0x40, 0x0b, 0xbd, 0xee, 0x60, 0x0a, 0xbd, 0xee, 0x40, 0x0b, 0xbc, 0xee, 0x60, 0x0a, 0xbc, 0xee, 0x90, 0x8a, 0x00, 0xee, 0x10, 0x4a, 0x01, 0xee, 0x90, 0x6a, 0x01, 0xee, 0x10, 0x1a, 0x02, 0xee, 0x90, 0x2a, 0x02, 0xee, 0x10, 0x3a, 0x03, 0xee, 0x10, 0x1a, 0x14, 0xee, 0x10, 0x2a, 0x12, 0xee, 0x10, 0x3a, 0x13, 0xee, 0x90, 0x4a, 0x10, 0xee, 0x10, 0x5a, 0x11, 0xee, 0x90, 0x6a, 0x11, 0xee, 0xc6, 0x0a, 0xbb, 0xee, 0xc0, 0x0b, 0xba, 0xee, 0x67, 0x0a, 0xbb, 0xee, 0x40, 0x0b, 0xba, 0xee, 0xc6, 0x0a, 0xfa, 0xee, 0xc0, 0x4b, 0xfb, 0xee, 0x67, 0x8a, 0xfa, 0xee, 0x40, 0x7b, 0xfb, 0xee, 0xc6, 0x6a, 0xbf, 0xee, 0xc0, 0x2b, 0xbe, 0xee, 0x67, 0xea, 0xbf, 0xee, 0x40, 0xfb, 0xbe, 0xee, 0xc6, 0x0a, 0xfe, 0xee, 0xc0, 0x4b, 0xff, 0xee, 0x67, 0x8a, 0xfe, 0xee, 0x40, 0x7b, 0xff, 0xee, 0x10, 0x40, 0x80, 0xf2, 0x12, 0x46, 0x84, 0xf2, 0x00, 0x2a, 0xf7, 0xee, 0x00, 0x2a, 0xf4, 0xee, 0x0e, 0x2a, 0xff, 0xee, 0x03, 0x2a, 0xfe, 0xee, 0x00, 0x6b, 0xb7, 0xee, 0x00, 0x6b, 0xb4, 0xee, 0x0e, 0x6b, 0xbf, 0xee, 0x03, 0x6b, 0xbe, 0xee, 0x10, 0x7f, 0x87, 0xf2, 0x10, 0x7f, 0x84, 0xf2, 0x1e, 0x7f, 0x87, 0xf3, 0x13, 0x7f, 0x86, 0xf3, 0x50, 0x0f, 0xc7, 0xf2, 0x50, 0x0f, 0xc4, 0xf2, 0x5e, 0x0f, 0xc7, 0xf3, 0x53, 0x0f, 0xc6, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vadd.f64 d16, d17, d16" + - + asm_text: "vadd.f32 s0, s1, s0" + - + asm_text: "vsub.f64 d16, d17, d16" + - + asm_text: "vsub.f32 s0, s1, s0" + - + asm_text: "vdiv.f64 d16, d17, d16" + - + asm_text: "vdiv.f32 s0, s1, s0" + - + asm_text: "vdiv.f32 s5, s5, s7" + - + asm_text: "vdiv.f64 d5, d5, d7" + - + asm_text: "vmul.f64 d16, d17, d16" + - + asm_text: "vmul.f64 d20, d20, d17" + - + asm_text: "vmul.f32 s0, s1, s0" + - + asm_text: "vmul.f32 s11, s11, s21" + - + asm_text: "vnmul.f64 d16, d17, d16" + - + asm_text: "vnmul.f32 s0, s1, s0" + - + asm_text: "vcmp.f64 d17, d16" + - + asm_text: "vcmp.f32 s1, s0" + - + asm_text: "vcmp.f64 d17, #0" + - + asm_text: "vcmp.f32 s1, #0" + - + asm_text: "vcmpe.f64 d17, d16" + - + asm_text: "vcmpe.f32 s1, s0" + - + asm_text: "vcmpe.f64 d16, #0" + - + asm_text: "vcmpe.f32 s0, #0" + - + asm_text: "vabs.f64 d16, d16" + - + asm_text: "vabs.f32 s0, s0" + - + asm_text: "vcvt.f32.f64 s0, d16" + - + asm_text: "vcvt.f64.f32 d16, s0" + - + asm_text: "vneg.f64 d16, d16" + - + asm_text: "vneg.f32 s0, s0" + - + asm_text: "vsqrt.f64 d16, d16" + - + asm_text: "vsqrt.f32 s0, s0" + - + asm_text: "vcvt.f64.s32 d16, s0" + - + asm_text: "vcvt.f32.s32 s0, s0" + - + asm_text: "vcvt.f64.u32 d16, s0" + - + asm_text: "vcvt.f32.u32 s0, s0" + - + asm_text: "vcvt.s32.f64 s0, d16" + - + asm_text: "vcvt.s32.f32 s0, s0" + - + asm_text: "vcvt.u32.f64 s0, d16" + - + asm_text: "vcvt.u32.f32 s0, s0" + - + asm_text: "vmla.f64 d16, d18, d17" + - + asm_text: "vmla.f32 s1, s2, s0" + - + asm_text: "vmls.f64 d16, d18, d17" + - + asm_text: "vmls.f32 s1, s2, s0" + - + asm_text: "vnmla.f64 d16, d18, d17" + - + asm_text: "vnmla.f32 s1, s2, s0" + - + asm_text: "vnmls.f64 d16, d18, d17" + - + asm_text: "vnmls.f32 s1, s2, s0" + - + asm_text: "vmrs APSR_nzcv, fpscr" + - + asm_text: "vmrs APSR_nzcv, fpscr" + - + asm_text: "vmrs APSR_nzcv, fpscr" + - + asm_text: "vmrs r2, fpsid" + - + asm_text: "vmrs r3, fpsid" + - + asm_text: "vmrs r4, mvfr0" + - + asm_text: "vmrs r5, mvfr1" + - + asm_text: "vnegne.f64 d16, d16" + - + asm_text: "vmovne s0, r0" + - + asm_text: "vmoveq s0, r1" + - + asm_text: "vmov r1, s2" + - + asm_text: "vmov s4, r3" + - + asm_text: "vmov r1, r5, d2" + - + asm_text: "vmov d4, r3, r9" + - + asm_text: "vmrs r0, fpscr" + - + asm_text: "vmrs r0, fpexc" + - + asm_text: "vmrs r0, fpsid" + - + asm_text: "vmrs r1, fpinst" + - + asm_text: "vmrs r8, fpinst2" + - + asm_text: "vmsr fpscr, r0" + - + asm_text: "vmsr fpexc, r0" + - + asm_text: "vmsr fpsid, r0" + - + asm_text: "vmsr fpinst, r3" + - + asm_text: "vmsr fpinst2, r4" + - + asm_text: "vmov.f64 d16, #3.000000e+00" + - + asm_text: "vmov.f32 s0, #3.000000e+00" + - + asm_text: "vmov.f64 d16, #-3.000000e+00" + - + asm_text: "vmov.f32 s0, #-3.000000e+00" + - + asm_text: "vmov s0, r0" + - + asm_text: "vmov s1, r1" + - + asm_text: "vmov s2, r2" + - + asm_text: "vmov s3, r3" + - + asm_text: "vmov r0, s0" + - + asm_text: "vmov r1, s1" + - + asm_text: "vmov r2, s2" + - + asm_text: "vmov r3, s3" + - + asm_text: "vmov r0, r1, d16" + - + asm_text: "vmov s3, s4, r1, r2" + - + asm_text: "vmov s2, s3, r1, r2" + - + asm_text: "vmov r1, r2, s3, s4" + - + asm_text: "vmov r1, r2, s2, s3" + - + asm_text: "vmov d15, r1, r2" + - + asm_text: "vmov d16, r1, r2" + - + asm_text: "vmov r1, r2, d15" + - + asm_text: "vmov r1, r2, d16" + - + asm_text: "vldr d17, [r0]" + - + asm_text: "vldr s0, [lr]" + - + asm_text: "vldr d0, [lr]" + - + asm_text: "vldr d1, [r2, #0x20]" + - + asm_text: "vldr d1, [r2, #-0x20]" + - + asm_text: "vldr d2, [r3]" + - + asm_text: "vldr d3, [pc]" + - + asm_text: "vldr d3, [pc]" + - + asm_text: "vldr d3, [pc, #-0]" + - + asm_text: "vldr s13, [r0]" + - + asm_text: "vldr s1, [r2, #0x20]" + - + asm_text: "vldr s1, [r2, #-0x20]" + - + asm_text: "vldr s2, [r3]" + - + asm_text: "vldr s5, [pc]" + - + asm_text: "vldr s5, [pc]" + - + asm_text: "vldr s5, [pc, #-0]" + - + asm_text: "vstr d4, [r1]" + - + asm_text: "vstr d4, [r1, #0x18]" + - + asm_text: "vstr d4, [r1, #-0x18]" + - + asm_text: "vstr s0, [lr]" + - + asm_text: "vstr d0, [lr]" + - + asm_text: "vstr s4, [r1]" + - + asm_text: "vstr s4, [r1, #0x18]" + - + asm_text: "vstr s4, [r1, #-0x18]" + - + asm_text: "vldmia r1, {d2, d3, d4, d5, d6, d7}" + - + asm_text: "vldmia r1, {s2, s3, s4, s5, s6, s7}" + - + asm_text: "vstmia r1, {d2, d3, d4, d5, d6, d7}" + - + asm_text: "vstmia r1, {s2, s3, s4, s5, s6, s7}" + - + asm_text: "vpush {d8, d9, d10, d11, d12, d13, d14, d15}" + - + asm_text: "fldmiax r5!, {d0, d1, d2}" + - + asm_text: "fldmiaxeq r0, {d4, d5}" + - + asm_text: "fldmdbxne r5!, {d4, d5, d6}" + - + asm_text: "fstmiax r5!, {d0, d1, d2, d3, d4, d5, d6, d7}" + - + asm_text: "fstmiaxeq r4, {d8, d9}" + - + asm_text: "fstmdbxne r7!, {d2, d3, d4}" + - + asm_text: "vcvtr.s32.f64 s0, d0" + - + asm_text: "vcvtr.s32.f32 s0, s1" + - + asm_text: "vcvtr.u32.f64 s0, d0" + - + asm_text: "vcvtr.u32.f32 s0, s1" + - + asm_text: "vmov s1, r8" + - + asm_text: "vmov s2, r4" + - + asm_text: "vmov s3, r6" + - + asm_text: "vmov s4, r1" + - + asm_text: "vmov s5, r2" + - + asm_text: "vmov s6, r3" + - + asm_text: "vmov r1, s8" + - + asm_text: "vmov r2, s4" + - + asm_text: "vmov r3, s6" + - + asm_text: "vmov r4, s1" + - + asm_text: "vmov r5, s2" + - + asm_text: "vmov r6, s3" + - + asm_text: "vcvt.f32.u32 s0, s0, #0x14" + - + asm_text: "vcvt.f64.s32 d0, d0, #0x20" + - + asm_text: "vcvt.f32.u16 s0, s0, #1" + - + asm_text: "vcvt.f64.s16 d0, d0, #0x10" + - + asm_text: "vcvt.f32.s32 s1, s1, #0x14" + - + asm_text: "vcvt.f64.u32 d20, d20, #0x20" + - + asm_text: "vcvt.f32.s16 s17, s17, #1" + - + asm_text: "vcvt.f64.u16 d23, d23, #0x10" + - + asm_text: "vcvt.u32.f32 s12, s12, #0x14" + - + asm_text: "vcvt.s32.f64 d2, d2, #0x20" + - + asm_text: "vcvt.u16.f32 s28, s28, #1" + - + asm_text: "vcvt.s16.f64 d15, d15, #0x10" + - + asm_text: "vcvt.s32.f32 s1, s1, #0x14" + - + asm_text: "vcvt.u32.f64 d20, d20, #0x20" + - + asm_text: "vcvt.s16.f32 s17, s17, #1" + - + asm_text: "vcvt.u16.f64 d23, d23, #0x10" + - + asm_text: "vmov.i32 d4, #0x0" + - + asm_text: "vmov.i32 d4, #0x42000000" + - + asm_text: "vmov.f32 s5, #1.000000e+00" + - + asm_text: "vmov.f32 s5, #1.250000e-01" + - + asm_text: "vmov.f32 s5, #-1.875000e+00" + - + asm_text: "vmov.f32 s5, #-5.937500e-01" + - + asm_text: "vmov.f64 d6, #1.000000e+00" + - + asm_text: "vmov.f64 d6, #1.250000e-01" + - + asm_text: "vmov.f64 d6, #-1.875000e+00" + - + asm_text: "vmov.f64 d6, #-5.937500e-01" + - + asm_text: "vmov.f32 d7, #1.000000e+00" + - + asm_text: "vmov.f32 d7, #1.250000e-01" + - + asm_text: "vmov.f32 d7, #-1.875000e+00" + - + asm_text: "vmov.f32 d7, #-5.937500e-01" + - + asm_text: "vmov.f32 q8, #1.000000e+00" + - + asm_text: "vmov.f32 q8, #1.250000e-01" + - + asm_text: "vmov.f32 q8, #-1.875000e+00" + - + asm_text: "vmov.f32 q8, #-5.937500e-01" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb-add-sub-width.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb-add-sub-width.s.yaml new file mode 100644 index 0000000..5c235b7 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb-add-sub-width.s.yaml @@ -0,0 +1,56 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x44, 0x08, 0x44, 0x40, 0x18, 0x40, 0x18, 0x08, 0x44, 0x08, 0x44, 0x40, 0x18, 0x40, 0x18, 0x01, 0xbf, 0x40, 0x18, 0x08, 0x44, 0x10, 0xeb, 0x01, 0x00, 0x10, 0xeb, 0x01, 0x00, 0x40, 0x1a, 0x40, 0x1a, 0xa0, 0xeb, 0x01, 0x00, 0xa0, 0xeb, 0x01, 0x00, 0x40, 0x1a, 0x40, 0x1a, 0x01, 0xbf, 0x40, 0x1a, 0x40, 0x1a, 0xb0, 0xeb, 0x01, 0x00, 0xb0, 0xeb, 0x01, 0x00 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "add r0, r1" + - + asm_text: "add r0, r1" + - + asm_text: "adds r0, r0, r1" + - + asm_text: "adds r0, r0, r1" + - + asm_text: "add r0, r1" + - + asm_text: "add r0, r1" + - + asm_text: "adds r0, r0, r1" + - + asm_text: "adds r0, r0, r1" + - + asm_text: "itttt eq" + - + asm_text: "addeq r0, r0, r1" + - + asm_text: "addeq r0, r1" + - + asm_text: "addseq.w r0, r0, r1" + - + asm_text: "addseq.w r0, r0, r1" + - + asm_text: "subs r0, r0, r1" + - + asm_text: "subs r0, r0, r1" + - + asm_text: "sub.w r0, r0, r1" + - + asm_text: "sub.w r0, r0, r1" + - + asm_text: "subs r0, r0, r1" + - + asm_text: "subs r0, r0, r1" + - + asm_text: "itttt eq" + - + asm_text: "subeq r0, r0, r1" + - + asm_text: "subeq r0, r0, r1" + - + asm_text: "subseq.w r0, r0, r1" + - + asm_text: "subseq.w r0, r0, r1" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb-fp-armv8.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb-fp-armv8.s.yaml new file mode 100644 index 0000000..304c64c --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb-fp-armv8.s.yaml @@ -0,0 +1,92 @@ +test_cases: + - + input: + bytes: [ 0xb2, 0xee, 0xe0, 0x3b, 0xf3, 0xee, 0xcc, 0x2b, 0xb2, 0xee, 0x60, 0x3b, 0xb3, 0xee, 0x41, 0x2b, 0xbc, 0xfe, 0xe1, 0x1a, 0xbc, 0xfe, 0xc3, 0x1b, 0xbd, 0xfe, 0xeb, 0x3a, 0xbd, 0xfe, 0xe7, 0x3b, 0xbe, 0xfe, 0xc2, 0x0a, 0xbe, 0xfe, 0xc4, 0x0b, 0xff, 0xfe, 0xc4, 0x8a, 0xff, 0xfe, 0xc8, 0x8b, 0xbc, 0xfe, 0x61, 0x1a, 0xbc, 0xfe, 0x43, 0x1b, 0xbd, 0xfe, 0x6b, 0x3a, 0xbd, 0xfe, 0x67, 0x3b, 0xbe, 0xfe, 0x42, 0x0a, 0xbe, 0xfe, 0x44, 0x0b, 0xff, 0xfe, 0x44, 0x8a, 0xff, 0xfe, 0x48, 0x8b, 0x20, 0xfe, 0xab, 0x2a, 0x6f, 0xfe, 0xa7, 0xeb, 0x30, 0xfe, 0x80, 0x0a, 0x3a, 0xfe, 0x24, 0x5b, 0x0e, 0xfe, 0x2b, 0xfa, 0x04, 0xfe, 0x08, 0x2b, 0x58, 0xfe, 0x07, 0xaa, 0x11, 0xfe, 0x2f, 0x0b, 0xc6, 0xfe, 0x00, 0x2a, 0x86, 0xfe, 0xae, 0x5b, 0x80, 0xfe, 0x46, 0x0a, 0x86, 0xfe, 0x49, 0x4b, 0xf6, 0xee, 0xcc, 0x1a, 0xb6, 0xee, 0x64, 0x0a, 0xb8, 0xfe, 0x44, 0x3b, 0xb8, 0xfe, 0x60, 0x6a, 0xb9, 0xfe, 0x44, 0x3b, 0xb9, 0xfe, 0x60, 0x6a, 0xba, 0xfe, 0x44, 0x3b, 0xba, 0xfe, 0x60, 0x6a, 0xbb, 0xfe, 0x44, 0x3b, 0xbb, 0xfe, 0x60, 0x6a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcvtt.f64.f16 d3, s1" + - + asm_text: "vcvtt.f16.f64 s5, d12" + - + asm_text: "vcvtb.f64.f16 d3, s1" + - + asm_text: "vcvtb.f16.f64 s4, d1" + - + asm_text: "vcvta.s32.f32 s2, s3" + - + asm_text: "vcvta.s32.f64 s2, d3" + - + asm_text: "vcvtn.s32.f32 s6, s23" + - + asm_text: "vcvtn.s32.f64 s6, d23" + - + asm_text: "vcvtp.s32.f32 s0, s4" + - + asm_text: "vcvtp.s32.f64 s0, d4" + - + asm_text: "vcvtm.s32.f32 s17, s8" + - + asm_text: "vcvtm.s32.f64 s17, d8" + - + asm_text: "vcvta.u32.f32 s2, s3" + - + asm_text: "vcvta.u32.f64 s2, d3" + - + asm_text: "vcvtn.u32.f32 s6, s23" + - + asm_text: "vcvtn.u32.f64 s6, d23" + - + asm_text: "vcvtp.u32.f32 s0, s4" + - + asm_text: "vcvtp.u32.f64 s0, d4" + - + asm_text: "vcvtm.u32.f32 s17, s8" + - + asm_text: "vcvtm.u32.f64 s17, d8" + - + asm_text: "vselge.f32 s4, s1, s23" + - + asm_text: "vselge.f64 d30, d31, d23" + - + asm_text: "vselgt.f32 s0, s1, s0" + - + asm_text: "vselgt.f64 d5, d10, d20" + - + asm_text: "vseleq.f32 s30, s28, s23" + - + asm_text: "vseleq.f64 d2, d4, d8" + - + asm_text: "vselvs.f32 s21, s16, s14" + - + asm_text: "vselvs.f64 d0, d1, d31" + - + asm_text: "vmaxnm.f32 s5, s12, s0" + - + asm_text: "vmaxnm.f64 d5, d22, d30" + - + asm_text: "vminnm.f32 s0, s0, s12" + - + asm_text: "vminnm.f64 d4, d6, d9" + - + asm_text: "vrintz.f32 s3, s24" + - + asm_text: "vrintr.f32 s0, s9" + - + asm_text: "vrinta.f64 d3, d4" + - + asm_text: "vrinta.f32 s12, s1" + - + asm_text: "vrintn.f64 d3, d4" + - + asm_text: "vrintn.f32 s12, s1" + - + asm_text: "vrintp.f64 d3, d4" + - + asm_text: "vrintp.f32 s12, s1" + - + asm_text: "vrintm.f64 d3, d4" + - + asm_text: "vrintm.f32 s12, s1" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb-hints.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb-hints.s.yaml new file mode 100644 index 0000000..a9df282 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb-hints.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xbf, 0x10, 0xbf, 0x20, 0xbf, 0x30, 0xbf, 0x40, 0xbf, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "nop" + - + asm_text: "yield" + - + asm_text: "wfe" + - + asm_text: "wfi" + - + asm_text: "sev" + - + asm_text: "dmb sy" + - + asm_text: "dmb sy" + - + asm_text: "dsb sy" + - + asm_text: "dsb sy" + - + asm_text: "isb sy" + - + asm_text: "isb sy" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb-mov.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb-mov.s.yaml new file mode 100644 index 0000000..5ea3a9a --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb-mov.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x85, 0x46, 0x68, 0x46, 0xed, 0x46, 0x87, 0x46, 0x78, 0x46, 0xff, 0x46, 0x4f, 0xea, 0x00, 0x0d, 0x4f, 0xea, 0x0d, 0x00 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "mov sp, r0" + - + asm_text: "mov r0, sp" + - + asm_text: "mov sp, sp" + - + asm_text: "mov pc, r0" + - + asm_text: "mov r0, pc" + - + asm_text: "mov pc, pc" + - + asm_text: "mov.w sp, r0" + - + asm_text: "mov.w r0, sp" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb-neon-crypto.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb-neon-crypto.s.yaml new file mode 100644 index 0000000..d009104 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb-neon-crypto.s.yaml @@ -0,0 +1,38 @@ +test_cases: + - + input: + bytes: [ 0xb0, 0xff, 0x42, 0x03, 0xb0, 0xff, 0x02, 0x03, 0xb0, 0xff, 0xc2, 0x03, 0xb0, 0xff, 0x82, 0x03, 0xb9, 0xff, 0xc2, 0x02, 0xba, 0xff, 0x82, 0x03, 0xba, 0xff, 0xc2, 0x03, 0x02, 0xef, 0x44, 0x0c, 0x22, 0xef, 0x44, 0x0c, 0x12, 0xef, 0x44, 0x0c, 0x32, 0xef, 0x44, 0x0c, 0x02, 0xff, 0x44, 0x0c, 0x12, 0xff, 0x44, 0x0c, 0x22, 0xff, 0x44, 0x0c, 0xe0, 0xef, 0xa1, 0x0e ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "aesd.8 q0, q1" + - + asm_text: "aese.8 q0, q1" + - + asm_text: "aesimc.8 q0, q1" + - + asm_text: "aesmc.8 q0, q1" + - + asm_text: "sha1h.32 q0, q1" + - + asm_text: "sha1su1.32 q0, q1" + - + asm_text: "sha256su0.32 q0, q1" + - + asm_text: "sha1c.32 q0, q1, q2" + - + asm_text: "sha1m.32 q0, q1, q2" + - + asm_text: "sha1p.32 q0, q1, q2" + - + asm_text: "sha1su0.32 q0, q1, q2" + - + asm_text: "sha256h.32 q0, q1, q2" + - + asm_text: "sha256h2.32 q0, q1, q2" + - + asm_text: "sha256su1.32 q0, q1, q2" + - + asm_text: "vmull.p64 q8, d16, d17" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb-neon-v8.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb-neon-v8.s.yaml new file mode 100644 index 0000000..6d8fe53 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb-neon-v8.s.yaml @@ -0,0 +1,82 @@ +test_cases: + - + input: + bytes: [ 0x05, 0xff, 0x11, 0x4f, 0x08, 0xff, 0x5c, 0x4f, 0x24, 0xff, 0x3e, 0x5f, 0x2a, 0xff, 0xd4, 0x0f, 0xbb, 0xff, 0x06, 0x40, 0xbb, 0xff, 0x8a, 0xc0, 0xbb, 0xff, 0x4c, 0x80, 0xbb, 0xff, 0xe4, 0x80, 0xbb, 0xff, 0x2e, 0x13, 0xbb, 0xff, 0x8a, 0xc3, 0xbb, 0xff, 0x64, 0x23, 0xfb, 0xff, 0xc2, 0xa3, 0xbb, 0xff, 0x21, 0xf1, 0xbb, 0xff, 0x83, 0x51, 0xbb, 0xff, 0x60, 0x61, 0xbb, 0xff, 0xc6, 0xa1, 0xbb, 0xff, 0x25, 0xb2, 0xbb, 0xff, 0xa7, 0xe2, 0xbb, 0xff, 0x6e, 0x82, 0xfb, 0xff, 0xe0, 0x22, 0xba, 0xff, 0x00, 0x34, 0xba, 0xff, 0x48, 0x24, 0xba, 0xff, 0x8c, 0x54, 0xba, 0xff, 0xc6, 0x04, 0xba, 0xff, 0x00, 0x35, 0xfa, 0xff, 0x44, 0x05, 0xba, 0xff, 0xa2, 0xc5, 0xfa, 0xff, 0xc8, 0x25, 0xba, 0xff, 0x80, 0x36, 0xba, 0xff, 0xc8, 0x26, 0xba, 0xff, 0x80, 0x37, 0xba, 0xff, 0xc8, 0x27, 0xba, 0xff, 0x00, 0x34, 0xba, 0xff, 0xc6, 0x04, 0xba, 0xff, 0x00, 0x35, 0xfa, 0xff, 0xc8, 0x25, 0xba, 0xff, 0xc8, 0x27 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmaxnm.f32 d4, d5, d1" + - + asm_text: "vmaxnm.f32 q2, q4, q6" + - + asm_text: "vminnm.f32 d5, d4, d30" + - + asm_text: "vminnm.f32 q0, q13, q2" + - + asm_text: "vcvta.s32.f32 d4, d6" + - + asm_text: "vcvta.u32.f32 d12, d10" + - + asm_text: "vcvta.s32.f32 q4, q6" + - + asm_text: "vcvta.u32.f32 q4, q10" + - + asm_text: "vcvtm.s32.f32 d1, d30" + - + asm_text: "vcvtm.u32.f32 d12, d10" + - + asm_text: "vcvtm.s32.f32 q1, q10" + - + asm_text: "vcvtm.u32.f32 q13, q1" + - + asm_text: "vcvtn.s32.f32 d15, d17" + - + asm_text: "vcvtn.u32.f32 d5, d3" + - + asm_text: "vcvtn.s32.f32 q3, q8" + - + asm_text: "vcvtn.u32.f32 q5, q3" + - + asm_text: "vcvtp.s32.f32 d11, d21" + - + asm_text: "vcvtp.u32.f32 d14, d23" + - + asm_text: "vcvtp.s32.f32 q4, q15" + - + asm_text: "vcvtp.u32.f32 q9, q8" + - + asm_text: "vrintn.f32 d3, d0" + - + asm_text: "vrintn.f32 q1, q4" + - + asm_text: "vrintx.f32 d5, d12" + - + asm_text: "vrintx.f32 q0, q3" + - + asm_text: "vrinta.f32 d3, d0" + - + asm_text: "vrinta.f32 q8, q2" + - + asm_text: "vrintz.f32 d12, d18" + - + asm_text: "vrintz.f32 q9, q4" + - + asm_text: "vrintm.f32 d3, d0" + - + asm_text: "vrintm.f32 q1, q4" + - + asm_text: "vrintp.f32 d3, d0" + - + asm_text: "vrintp.f32 q1, q4" + - + asm_text: "vrintn.f32 d3, d0" + - + asm_text: "vrintx.f32 q0, q3" + - + asm_text: "vrinta.f32 d3, d0" + - + asm_text: "vrintz.f32 q9, q4" + - + asm_text: "vrintp.f32 q1, q4" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb-shift-encoding.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb-shift-encoding.s.yaml new file mode 100644 index 0000000..4909702 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb-shift-encoding.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0x6e, 0xeb, 0x00, 0x0c, 0x68, 0xeb, 0x19, 0x01, 0x67, 0xeb, 0x1a, 0x42, 0x66, 0xeb, 0x0a, 0x03, 0x65, 0xeb, 0x0e, 0x44, 0x64, 0xeb, 0x2b, 0x05, 0x63, 0xeb, 0x2c, 0x46, 0x62, 0xeb, 0x3c, 0x07, 0x61, 0xeb, 0x30, 0x48, 0x0e, 0xea, 0x00, 0x0c, 0x08, 0xea, 0x19, 0x01, 0x07, 0xea, 0x1a, 0x42, 0x06, 0xea, 0x0a, 0x03, 0x05, 0xea, 0x0e, 0x44, 0x04, 0xea, 0x2b, 0x05, 0x03, 0xea, 0x2c, 0x46, 0x02, 0xea, 0x3c, 0x07, 0x01, 0xea, 0x30, 0x48 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "sbc.w r12, lr, r0" + - + asm_text: "sbc.w r1, r8, r9, lsr #0x20" + - + asm_text: "sbc.w r2, r7, r10, lsr #0x10" + - + asm_text: "sbc.w r3, r6, r10" + - + asm_text: "sbc.w r4, r5, lr, lsl #0x10" + - + asm_text: "sbc.w r5, r4, r11, asr #0x20" + - + asm_text: "sbc.w r6, r3, r12, asr #0x10" + - + asm_text: "sbc.w r7, r2, r12, rrx" + - + asm_text: "sbc.w r8, r1, r0, ror #0x10" + - + asm_text: "and.w r12, lr, r0" + - + asm_text: "and.w r1, r8, r9, lsr #0x20" + - + asm_text: "and.w r2, r7, r10, lsr #0x10" + - + asm_text: "and.w r3, r6, r10" + - + asm_text: "and.w r4, r5, lr, lsl #0x10" + - + asm_text: "and.w r5, r4, r11, asr #0x20" + - + asm_text: "and.w r6, r3, r12, asr #0x10" + - + asm_text: "and.w r7, r2, r12, rrx" + - + asm_text: "and.w r8, r1, r0, ror #0x10" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb.s.yaml new file mode 100644 index 0000000..8bff9f5 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0x91, 0x42, 0x16, 0xbc, 0xfe, 0xde, 0xc8, 0x47, 0xd0, 0x47, 0x1a, 0xba, 0x63, 0xba, 0xf5, 0xba, 0x5a, 0xb2, 0x1a, 0xb2, 0x2c, 0x42, 0xf3, 0xb2, 0xb3, 0xb2, 0x8b, 0x58, 0x02, 0xbe, 0xc0, 0x46, 0x67, 0xb6, 0x78, 0x46 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "cmp r1, r2" + - + asm_text: "pop {r1, r2, r4}" + - + asm_text: "trap" + - + asm_text: "blx r9" + - + asm_text: "blx r10" + - + asm_text: "rev r2, r3" + - + asm_text: "rev16 r3, r4" + - + asm_text: "revsh r5, r6" + - + asm_text: "sxtb r2, r3" + - + asm_text: "sxth r2, r3" + - + asm_text: "tst r4, r5" + - + asm_text: "uxtb r3, r6" + - + asm_text: "uxth r3, r6" + - + asm_text: "ldr r3, [r1, r2]" + - + asm_text: "bkpt #2" + - + asm_text: "mov r8, r8" + - + asm_text: "cpsie aif" + - + asm_text: "mov r0, pc" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb2-b.w-encodingT4.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb2-b.w-encodingT4.s.yaml new file mode 100644 index 0000000..6f5e220 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb2-b.w-encodingT4.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x36, 0xf0, 0x06, 0xbc ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "b.w #0x3680c" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb2-branches.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb2-branches.s.yaml new file mode 100644 index 0000000..b700f2a --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb2-branches.s.yaml @@ -0,0 +1,192 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe4, 0xff, 0xe3, 0xff, 0xf7, 0x00, 0xbc, 0x00, 0xf0, 0xff, 0xbb, 0x66, 0xf6, 0x30, 0xbc, 0x99, 0xf1, 0xcf, 0xbb, 0x00, 0xe4, 0xff, 0xe3, 0xff, 0xf7, 0xff, 0xbb, 0x00, 0xf0, 0x00, 0xbc, 0x66, 0xf6, 0x30, 0xbc, 0x99, 0xf1, 0xcf, 0xbb, 0x08, 0xbf, 0x00, 0xe4, 0x18, 0xbf, 0x01, 0xe4, 0xc8, 0xbf, 0xff, 0xf7, 0x00, 0xbc, 0xd8, 0xbf, 0x00, 0xf0, 0xff, 0xbb, 0xa8, 0xbf, 0x66, 0xf6, 0x30, 0xbc, 0xb8, 0xbf, 0x99, 0xf1, 0xcf, 0xbb, 0x80, 0xd0, 0x7f, 0xd1, 0x00, 0xf0, 0x80, 0xf8, 0x18, 0xbf, 0x00, 0xf0, 0x80, 0xf8, 0x3f, 0xf5, 0x80, 0xaf, 0x40, 0xf0, 0x7f, 0x80, 0xc0, 0xf6, 0x00, 0x80, 0xbf, 0xf2, 0xff, 0xaf, 0x80, 0xd1, 0x7f, 0xdc, 0x7f, 0xf4, 0x7f, 0xaf, 0x00, 0xf3, 0x80, 0x80, 0x40, 0xf4, 0x00, 0x80, 0x3f, 0xf3, 0xff, 0xaf, 0x08, 0xbf, 0x08, 0x44, 0x40, 0xd1, 0x0c, 0xbf, 0x08, 0x44, 0x40, 0xe0, 0x00, 0xe4, 0xff, 0xe3, 0xff, 0xf7, 0x00, 0xbc, 0x00, 0xf0, 0xff, 0xbb, 0x66, 0xf6, 0x30, 0xbc, 0x99, 0xf1, 0xcf, 0xbb, 0x00, 0xe4, 0xff, 0xe3, 0xff, 0xf7, 0xff, 0xbb, 0x00, 0xf0, 0x00, 0xbc, 0x66, 0xf6, 0x30, 0xbc, 0x99, 0xf1, 0xcf, 0xbb, 0x08, 0xbf, 0x00, 0xe4, 0x18, 0xbf, 0x01, 0xe4, 0xc8, 0xbf, 0xff, 0xf7, 0x00, 0xbc, 0xd8, 0xbf, 0x00, 0xf0, 0xff, 0xbb, 0xa8, 0xbf, 0x66, 0xf6, 0x30, 0xbc, 0xb8, 0xbf, 0x99, 0xf1, 0xcf, 0xbb, 0x80, 0xd0, 0x7f, 0xd1, 0x3f, 0xf5, 0x80, 0xaf, 0x40, 0xf0, 0x7f, 0x80, 0xc0, 0xf6, 0x00, 0x80, 0xbf, 0xf2, 0xff, 0xaf, 0x80, 0xd1, 0x7f, 0xdc, 0x7f, 0xf4, 0x7f, 0xaf, 0x00, 0xf3, 0x80, 0x80, 0x40, 0xf4, 0x00, 0x80, 0x3f, 0xf3, 0xff, 0xaf, 0x08, 0xbf, 0x08, 0x44, 0x40, 0xd1, 0x0c, 0xbf, 0x08, 0x44, 0x40, 0xe0, 0x01, 0xe0, 0x00, 0xf0, 0x01, 0xf8, 0x01, 0xd0, 0x08, 0xb1, 0x00, 0xf0, 0x02, 0xe8 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "b #-0x800" + - + asm_text: "b #0x7fe" + - + asm_text: "b.w #-0x800" + - + asm_text: "b.w #0x7fe" + - + asm_text: "b.w #-0x1997a0" + - + asm_text: "b.w #0x19979e" + - + asm_text: "b #-0x800" + - + asm_text: "b #0x7fe" + - + asm_text: "b.w #-0x802" + - + asm_text: "b.w #0x800" + - + asm_text: "b.w #-0x1997a0" + - + asm_text: "b.w #0x19979e" + - + asm_text: "it eq" + - + asm_text: "beq #-0x800" + - + asm_text: "it ne" + - + asm_text: "bne #-0x7fe" + - + asm_text: "it gt" + - + asm_text: "bgt.w #-0x800" + - + asm_text: "it le" + - + asm_text: "ble.w #0x7fe" + - + asm_text: "it ge" + - + asm_text: "bge.w #-0x1997a0" + - + asm_text: "it lt" + - + asm_text: "blt.w #0x19979e" + - + asm_text: "beq #-0x100" + - + asm_text: "bne #0xfe" + - + asm_text: "bl #0x100" + - + asm_text: "it ne" + - + asm_text: "blne #0x100" + - + asm_text: "bmi.w #-0x100" + - + asm_text: "bne.w #0xfe" + - + asm_text: "blt.w #-0x100000" + - + asm_text: "bge.w #0xffffe" + - + asm_text: "bne #-0x100" + - + asm_text: "bgt #0xfe" + - + asm_text: "bne.w #-0x102" + - + asm_text: "bgt.w #0x100" + - + asm_text: "bne.w #-0x100000" + - + asm_text: "bgt.w #0xffffe" + - + asm_text: "it eq" + - + asm_text: "addeq r0, r1" + - + asm_text: "bne #0x80" + - + asm_text: "ite eq" + - + asm_text: "addeq r0, r1" + - + asm_text: "bne #0x80" + - + asm_text: "b #-0x800" + - + asm_text: "b #0x7fe" + - + asm_text: "b.w #-0x800" + - + asm_text: "b.w #0x7fe" + - + asm_text: "b.w #-0x1997a0" + - + asm_text: "b.w #0x19979e" + - + asm_text: "b #-0x800" + - + asm_text: "b #0x7fe" + - + asm_text: "b.w #-0x802" + - + asm_text: "b.w #0x800" + - + asm_text: "b.w #-0x1997a0" + - + asm_text: "b.w #0x19979e" + - + asm_text: "it eq" + - + asm_text: "beq #-0x800" + - + asm_text: "it ne" + - + asm_text: "bne #-0x7fe" + - + asm_text: "it gt" + - + asm_text: "bgt.w #-0x800" + - + asm_text: "it le" + - + asm_text: "ble.w #0x7fe" + - + asm_text: "it ge" + - + asm_text: "bge.w #-0x1997a0" + - + asm_text: "it lt" + - + asm_text: "blt.w #0x19979e" + - + asm_text: "beq #-0x100" + - + asm_text: "bne #0xfe" + - + asm_text: "bmi.w #-0x100" + - + asm_text: "bne.w #0xfe" + - + asm_text: "blt.w #-0x100000" + - + asm_text: "bge.w #0xffffe" + - + asm_text: "bne #-0x100" + - + asm_text: "bgt #0xfe" + - + asm_text: "bne.w #-0x102" + - + asm_text: "bgt.w #0x100" + - + asm_text: "bne.w #-0x100000" + - + asm_text: "bgt.w #0xffffe" + - + asm_text: "it eq" + - + asm_text: "addeq r0, r1" + - + asm_text: "bne #0x80" + - + asm_text: "ite eq" + - + asm_text: "addeq r0, r1" + - + asm_text: "bne #0x80" + - + asm_text: "b #2" + - + asm_text: "bl #2" + - + asm_text: "beq #2" + - + asm_text: "cbz r0, #2" + - + asm_text: "blx #4" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb2-bxj-v8.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb2-bxj-v8.s.yaml new file mode 100644 index 0000000..280932a --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb2-bxj-v8.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xcd, 0xf3, 0x00, 0x8f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "bxj sp" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb2-bxj.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb2-bxj.s.yaml new file mode 100644 index 0000000..51e7838 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb2-bxj.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xc2, 0xf3, 0x00, 0x8f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "bxj r2" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb2-ldr.w-str.w.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb2-ldr.w-str.w.s.yaml new file mode 100644 index 0000000..baf6f74 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb2-ldr.w-str.w.s.yaml @@ -0,0 +1,118 @@ +test_cases: + - + input: + bytes: [ 0x51, 0xf8, 0x04, 0x3b, 0x51, 0xf8, 0x04, 0x3b, 0x40, 0xf8, 0x04, 0x3b, 0x40, 0xf8, 0x04, 0x3b, 0x51, 0xf8, 0x04, 0x3d, 0x51, 0xf8, 0x04, 0x3d, 0x40, 0xf8, 0x04, 0x3d, 0x40, 0xf8, 0x04, 0x3d, 0x51, 0xf8, 0x04, 0x0d, 0x51, 0xf8, 0x04, 0xdd, 0x51, 0xf8, 0x04, 0xfd, 0x50, 0xf8, 0x04, 0x1d, 0x5d, 0xf8, 0x04, 0x1d, 0x50, 0xf8, 0xff, 0x1f, 0x50, 0xf8, 0xff, 0x1d, 0x50, 0xf8, 0x00, 0x1f, 0x08, 0xbf, 0x50, 0xf8, 0xff, 0x1f, 0xd8, 0xbf, 0x50, 0xf8, 0xff, 0x1f, 0x51, 0xf8, 0x04, 0x0b, 0x51, 0xf8, 0x04, 0xdb, 0x51, 0xf8, 0x04, 0xfb, 0x51, 0xf8, 0x04, 0x0b, 0x5d, 0xf8, 0x04, 0x0b, 0x5f, 0xf8, 0x04, 0x0b, 0x51, 0xf8, 0xff, 0x0b, 0x51, 0xf8, 0x00, 0x0b, 0x51, 0xf8, 0xff, 0x09, 0x08, 0xbf, 0x51, 0xf8, 0xff, 0x0b, 0xd8, 0xbf, 0x51, 0xf8, 0xff, 0x0b, 0x40, 0xf8, 0x04, 0x1d, 0x40, 0xf8, 0x04, 0xdd, 0x42, 0xf8, 0x04, 0x1d, 0x4d, 0xf8, 0x04, 0x1d, 0x42, 0xf8, 0xff, 0x1f, 0x42, 0xf8, 0x00, 0x1f, 0x42, 0xf8, 0xff, 0x1d, 0x08, 0xbf, 0x42, 0xf8, 0xff, 0x1f, 0xd8, 0xbf, 0x42, 0xf8, 0xff, 0x1f, 0x40, 0xf8, 0x04, 0x1b, 0x40, 0xf8, 0x04, 0xdb, 0x41, 0xf8, 0x04, 0x0b, 0x4d, 0xf8, 0x04, 0x0b, 0x40, 0xf8, 0xff, 0x1b, 0x40, 0xf8, 0x00, 0x1b, 0x40, 0xf8, 0xff, 0x19, 0x08, 0xbf, 0x40, 0xf8, 0xff, 0x1b, 0xd8, 0xbf, 0x40, 0xf8, 0xff, 0x1b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "ldr r3, [r1], #4" + - + asm_text: "ldr r3, [r1], #4" + - + asm_text: "str r3, [r0], #4" + - + asm_text: "str r3, [r0], #4" + - + asm_text: "ldr r3, [r1, #-4]!" + - + asm_text: "ldr r3, [r1, #-4]!" + - + asm_text: "str r3, [r0, #-4]!" + - + asm_text: "str r3, [r0, #-4]!" + - + asm_text: "ldr r0, [r1, #-4]!" + - + asm_text: "ldr sp, [r1, #-4]!" + - + asm_text: "ldr pc, [r1, #-4]!" + - + asm_text: "ldr r1, [r0, #-4]!" + - + asm_text: "ldr r1, [sp, #-4]!" + - + asm_text: "ldr r1, [r0, #0xff]!" + - + asm_text: "ldr r1, [r0, #-0xff]!" + - + asm_text: "ldr r1, [r0, #0]!" + - + asm_text: "it eq" + - + asm_text: "ldreq r1, [r0, #0xff]!" + - + asm_text: "it le" + - + asm_text: "ldrle r1, [r0, #0xff]!" + - + asm_text: "ldr r0, [r1], #4" + - + asm_text: "ldr sp, [r1], #4" + - + asm_text: "ldr pc, [r1], #4" + - + asm_text: "ldr r0, [r1], #4" + - + asm_text: "pop {r0}" + - + asm_text: "ldr.w r0, [pc, #-0xb04]" + - + asm_text: "ldr r0, [r1], #0xff" + - + asm_text: "ldr r0, [r1], #0" + - + asm_text: "ldr r0, [r1], #-0xff" + - + asm_text: "it eq" + - + asm_text: "ldreq r0, [r1], #0xff" + - + asm_text: "it le" + - + asm_text: "ldrle r0, [r1], #0xff" + - + asm_text: "str r1, [r0, #-4]!" + - + asm_text: "str sp, [r0, #-4]!" + - + asm_text: "str r1, [r2, #-4]!" + - + asm_text: "str r1, [sp, #-4]!" + - + asm_text: "str r1, [r2, #0xff]!" + - + asm_text: "str r1, [r2, #0]!" + - + asm_text: "str r1, [r2, #-0xff]!" + - + asm_text: "it eq" + - + asm_text: "streq r1, [r2, #0xff]!" + - + asm_text: "it le" + - + asm_text: "strle r1, [r2, #0xff]!" + - + asm_text: "str r1, [r0], #4" + - + asm_text: "str sp, [r0], #4" + - + asm_text: "str r0, [r1], #4" + - + asm_text: "str r0, [sp], #4" + - + asm_text: "str r1, [r0], #0xff" + - + asm_text: "str r1, [r0], #0" + - + asm_text: "str r1, [r0], #-0xff" + - + asm_text: "it eq" + - + asm_text: "streq r1, [r0], #0xff" + - + asm_text: "it le" + - + asm_text: "strle r1, [r0], #0xff" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb2-ldrexd-strexd.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb2-ldrexd-strexd.s.yaml new file mode 100644 index 0000000..044932e --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb2-ldrexd-strexd.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0xd2, 0xe8, 0x7f, 0x01, 0xc6, 0xe8, 0x73, 0x45 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "ldrexd r0, r1, [r2]" + - + asm_text: "strexd r3, r4, r5, [r6]" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb2-mclass.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb2-mclass.s.yaml new file mode 100644 index 0000000..fa7c524 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb2-mclass.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0xef, 0xf3, 0x00, 0x80, 0xef, 0xf3, 0x01, 0x80, 0xef, 0xf3, 0x02, 0x80, 0xef, 0xf3, 0x03, 0x80, 0xef, 0xf3, 0x05, 0x80, 0xef, 0xf3, 0x06, 0x80, 0xef, 0xf3, 0x07, 0x80, 0xef, 0xf3, 0x08, 0x80, 0xef, 0xf3, 0x09, 0x80, 0xef, 0xf3, 0x10, 0x80, 0xef, 0xf3, 0x14, 0x80, 0x80, 0xf3, 0x05, 0x88, 0x80, 0xf3, 0x06, 0x88, 0x80, 0xf3, 0x07, 0x88, 0x80, 0xf3, 0x08, 0x88, 0x80, 0xf3, 0x09, 0x88, 0x80, 0xf3, 0x10, 0x88, 0x80, 0xf3, 0x14, 0x88 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "mrs r0, apsr" + - + asm_text: "mrs r0, iapsr" + - + asm_text: "mrs r0, eapsr" + - + asm_text: "mrs r0, xpsr" + - + asm_text: "mrs r0, ipsr" + - + asm_text: "mrs r0, epsr" + - + asm_text: "mrs r0, iepsr" + - + asm_text: "mrs r0, msp" + - + asm_text: "mrs r0, psp" + - + asm_text: "mrs r0, primask" + - + asm_text: "mrs r0, control" + - + asm_text: "msr ipsr, r0" + - + asm_text: "msr epsr, r0" + - + asm_text: "msr iepsr, r0" + - + asm_text: "msr msp, r0" + - + asm_text: "msr psp, r0" + - + asm_text: "msr primask, r0" + - + asm_text: "msr control, r0" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb2-narrow-dp.ll.yaml b/thirdparty/capstone/tests/MC/ARM/thumb2-narrow-dp.ll.yaml new file mode 100644 index 0000000..5cdb15d --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb2-narrow-dp.ll.yaml @@ -0,0 +1,836 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x1d, 0x08, 0x31, 0x11, 0xf1, 0x08, 0x01, 0x18, 0xf1, 0x08, 0x08, 0x08, 0xbf, 0x40, 0x1d, 0x08, 0xbf, 0x08, 0x31, 0x08, 0xbf, 0x10, 0xf1, 0x05, 0x00, 0x08, 0xbf, 0x11, 0xf1, 0x08, 0x01, 0x50, 0x18, 0x52, 0x18, 0x0b, 0x44, 0x08, 0xbf, 0x50, 0x18, 0x08, 0xbf, 0x52, 0x18, 0x08, 0xbf, 0x12, 0xeb, 0x01, 0x00, 0x08, 0xbf, 0x12, 0xeb, 0x01, 0x02, 0x0b, 0x44, 0x7c, 0x44, 0x7c, 0x44, 0x97, 0x44, 0x97, 0x44, 0xef, 0x44, 0x05, 0xb0, 0x7f, 0xb0, 0x0d, 0xf5, 0x00, 0x7d, 0xe9, 0x44, 0xd5, 0x44, 0xd5, 0x44, 0xfd, 0x44, 0x12, 0xea, 0x01, 0x00, 0x0a, 0x40, 0x0a, 0x40, 0x10, 0xea, 0x01, 0x00, 0x11, 0xea, 0x03, 0x03, 0x01, 0xea, 0x00, 0x00, 0x0f, 0x40, 0x0f, 0x40, 0x11, 0xea, 0x08, 0x08, 0x18, 0xea, 0x01, 0x08, 0x18, 0xea, 0x00, 0x00, 0x11, 0xea, 0x08, 0x01, 0x12, 0xea, 0x41, 0x02, 0x11, 0xea, 0x50, 0x00, 0x08, 0xbf, 0x02, 0xea, 0x01, 0x00, 0x08, 0xbf, 0x0b, 0x40, 0x08, 0xbf, 0x0b, 0x40, 0x08, 0xbf, 0x00, 0xea, 0x01, 0x00, 0x08, 0xbf, 0x01, 0xea, 0x02, 0x02, 0x08, 0xbf, 0x11, 0xea, 0x00, 0x00, 0x08, 0xbf, 0x0f, 0x40, 0x08, 0xbf, 0x0f, 0x40, 0x08, 0xbf, 0x01, 0xea, 0x08, 0x08, 0x08, 0xbf, 0x08, 0xea, 0x01, 0x08, 0x08, 0xbf, 0x08, 0xea, 0x04, 0x04, 0x08, 0xbf, 0x04, 0xea, 0x08, 0x04, 0x08, 0xbf, 0x00, 0xea, 0x41, 0x00, 0x08, 0xbf, 0x01, 0xea, 0x55, 0x05, 0x92, 0xea, 0x01, 0x00, 0x4d, 0x40, 0x4d, 0x40, 0x90, 0xea, 0x01, 0x00, 0x91, 0xea, 0x02, 0x02, 0x81, 0xea, 0x01, 0x01, 0x4f, 0x40, 0x4f, 0x40, 0x91, 0xea, 0x08, 0x08, 0x98, 0xea, 0x01, 0x08, 0x98, 0xea, 0x06, 0x06, 0x90, 0xea, 0x08, 0x00, 0x92, 0xea, 0x41, 0x02, 0x91, 0xea, 0x50, 0x00, 0x08, 0xbf, 0x82, 0xea, 0x01, 0x03, 0x08, 0xbf, 0x48, 0x40, 0x08, 0xbf, 0x4a, 0x40, 0x08, 0xbf, 0x83, 0xea, 0x01, 0x03, 0x08, 0xbf, 0x81, 0xea, 0x00, 0x00, 0x08, 0xbf, 0x91, 0xea, 0x01, 0x01, 0x08, 0xbf, 0x4f, 0x40, 0x08, 0xbf, 0x4f, 0x40, 0x08, 0xbf, 0x81, 0xea, 0x08, 0x08, 0x08, 0xbf, 0x88, 0xea, 0x01, 0x08, 0x08, 0xbf, 0x88, 0xea, 0x00, 0x00, 0x08, 0xbf, 0x83, 0xea, 0x08, 0x03, 0x08, 0xbf, 0x84, 0xea, 0x41, 0x04, 0x08, 0xbf, 0x81, 0xea, 0x50, 0x00, 0x12, 0xfa, 0x01, 0xf0, 0x8a, 0x40, 0x11, 0xfa, 0x02, 0xf2, 0x10, 0xfa, 0x01, 0xf0, 0x11, 0xfa, 0x04, 0xf4, 0x01, 0xfa, 0x04, 0xf4, 0x8f, 0x40, 0x11, 0xfa, 0x08, 0xf8, 0x18, 0xfa, 0x01, 0xf8, 0x18, 0xfa, 0x03, 0xf3, 0x15, 0xfa, 0x08, 0xf5, 0x08, 0xbf, 0x02, 0xfa, 0x01, 0xf0, 0x08, 0xbf, 0x8a, 0x40, 0x08, 0xbf, 0x01, 0xfa, 0x02, 0xf2, 0x08, 0xbf, 0x00, 0xfa, 0x01, 0xf0, 0x08, 0xbf, 0x01, 0xfa, 0x03, 0xf3, 0x08, 0xbf, 0x11, 0xfa, 0x04, 0xf4, 0x08, 0xbf, 0x8f, 0x40, 0x08, 0xbf, 0x01, 0xfa, 0x08, 0xf8, 0x08, 0xbf, 0x08, 0xfa, 0x01, 0xf8, 0x08, 0xbf, 0x08, 0xfa, 0x00, 0xf0, 0x08, 0xbf, 0x03, 0xfa, 0x08, 0xf3, 0x32, 0xfa, 0x01, 0xf6, 0xca, 0x40, 0x31, 0xfa, 0x02, 0xf2, 0x32, 0xfa, 0x01, 0xf2, 0x31, 0xfa, 0x03, 0xf3, 0x21, 0xfa, 0x04, 0xf4, 0xcf, 0x40, 0x31, 0xfa, 0x08, 0xf8, 0x38, 0xfa, 0x01, 0xf8, 0x38, 0xfa, 0x02, 0xf2, 0x35, 0xfa, 0x08, 0xf5, 0x08, 0xbf, 0x22, 0xfa, 0x01, 0xf6, 0x08, 0xbf, 0xcf, 0x40, 0x08, 0xbf, 0x21, 0xfa, 0x07, 0xf7, 0x08, 0xbf, 0x27, 0xfa, 0x01, 0xf7, 0x08, 0xbf, 0x21, 0xfa, 0x02, 0xf2, 0x08, 0xbf, 0x31, 0xfa, 0x00, 0xf0, 0x08, 0xbf, 0xcf, 0x40, 0x08, 0xbf, 0x21, 0xfa, 0x08, 0xf8, 0x08, 0xbf, 0x28, 0xfa, 0x01, 0xf8, 0x08, 0xbf, 0x28, 0xfa, 0x01, 0xf1, 0x08, 0xbf, 0x24, 0xfa, 0x08, 0xf4, 0x56, 0xfa, 0x05, 0xf7, 0x08, 0x41, 0x51, 0xfa, 0x00, 0xf0, 0x53, 0xfa, 0x01, 0xf3, 0x51, 0xfa, 0x01, 0xf1, 0x41, 0xfa, 0x00, 0xf0, 0x0f, 0x41, 0x51, 0xfa, 0x08, 0xf8, 0x58, 0xfa, 0x01, 0xf8, 0x58, 0xfa, 0x05, 0xf5, 0x55, 0xfa, 0x08, 0xf5, 0x08, 0xbf, 0x42, 0xfa, 0x01, 0xf0, 0x08, 0xbf, 0x0a, 0x41, 0x08, 0xbf, 0x42, 0xfa, 0x01, 0xf1, 0x08, 0xbf, 0x44, 0xfa, 0x01, 0xf4, 0x08, 0xbf, 0x41, 0xfa, 0x06, 0xf6, 0x08, 0xbf, 0x51, 0xfa, 0x03, 0xf3, 0x08, 0xbf, 0x0f, 0x41, 0x08, 0xbf, 0x41, 0xfa, 0x08, 0xf8, 0x08, 0xbf, 0x48, 0xfa, 0x01, 0xf8, 0x08, 0xbf, 0x48, 0xfa, 0x01, 0xf1, 0x08, 0xbf, 0x43, 0xfa, 0x08, 0xf3, 0x52, 0xeb, 0x01, 0x05, 0x4d, 0x41, 0x4b, 0x41, 0x52, 0xeb, 0x01, 0x02, 0x51, 0xeb, 0x03, 0x03, 0x41, 0xeb, 0x00, 0x00, 0x4f, 0x41, 0x4f, 0x41, 0x51, 0xeb, 0x08, 0x08, 0x58, 0xeb, 0x01, 0x08, 0x58, 0xeb, 0x05, 0x05, 0x52, 0xeb, 0x08, 0x02, 0x53, 0xeb, 0x41, 0x03, 0x51, 0xeb, 0x54, 0x04, 0x08, 0xbf, 0x42, 0xeb, 0x03, 0x01, 0x08, 0xbf, 0x49, 0x41, 0x08, 0xbf, 0x4b, 0x41, 0x08, 0xbf, 0x43, 0xeb, 0x01, 0x03, 0x08, 0xbf, 0x41, 0xeb, 0x00, 0x00, 0x08, 0xbf, 0x51, 0xeb, 0x03, 0x03, 0x08, 0xbf, 0x4f, 0x41, 0x08, 0xbf, 0x4f, 0x41, 0x08, 0xbf, 0x41, 0xeb, 0x08, 0x08, 0x08, 0xbf, 0x48, 0xeb, 0x01, 0x08, 0x08, 0xbf, 0x48, 0xeb, 0x03, 0x03, 0x08, 0xbf, 0x41, 0xeb, 0x08, 0x01, 0x08, 0xbf, 0x42, 0xeb, 0x41, 0x02, 0x08, 0xbf, 0x41, 0xeb, 0x51, 0x01, 0x72, 0xeb, 0x01, 0x03, 0x8c, 0x41, 0x74, 0xeb, 0x01, 0x01, 0x74, 0xeb, 0x01, 0x04, 0x71, 0xeb, 0x02, 0x02, 0x61, 0xeb, 0x00, 0x00, 0x8f, 0x41, 0x71, 0xeb, 0x08, 0x08, 0x78, 0xeb, 0x01, 0x08, 0x78, 0xeb, 0x04, 0x04, 0x73, 0xeb, 0x08, 0x03, 0x72, 0xeb, 0x41, 0x02, 0x71, 0xeb, 0x55, 0x05, 0x08, 0xbf, 0x62, 0xeb, 0x01, 0x05, 0x08, 0xbf, 0x8d, 0x41, 0x08, 0xbf, 0x65, 0xeb, 0x01, 0x01, 0x08, 0xbf, 0x65, 0xeb, 0x01, 0x05, 0x08, 0xbf, 0x61, 0xeb, 0x00, 0x00, 0x08, 0xbf, 0x71, 0xeb, 0x02, 0x02, 0x08, 0xbf, 0x8f, 0x41, 0x08, 0xbf, 0x61, 0xeb, 0x08, 0x08, 0x08, 0xbf, 0x68, 0xeb, 0x01, 0x08, 0x08, 0xbf, 0x68, 0xeb, 0x07, 0x07, 0x08, 0xbf, 0x67, 0xeb, 0x08, 0x07, 0x08, 0xbf, 0x62, 0xeb, 0x41, 0x02, 0x08, 0xbf, 0x61, 0xeb, 0x55, 0x05, 0x72, 0xfa, 0x01, 0xf3, 0xc8, 0x41, 0x70, 0xfa, 0x01, 0xf1, 0x72, 0xfa, 0x01, 0xf2, 0x71, 0xfa, 0x02, 0xf2, 0x61, 0xfa, 0x05, 0xf5, 0xcf, 0x41, 0x71, 0xfa, 0x08, 0xf8, 0x78, 0xfa, 0x01, 0xf8, 0x78, 0xfa, 0x06, 0xf6, 0x76, 0xfa, 0x08, 0xf6, 0x08, 0xbf, 0x62, 0xfa, 0x01, 0xf4, 0x08, 0xbf, 0xcc, 0x41, 0x08, 0xbf, 0x64, 0xfa, 0x01, 0xf1, 0x08, 0xbf, 0x64, 0xfa, 0x01, 0xf4, 0x08, 0xbf, 0x61, 0xfa, 0x00, 0xf0, 0x08, 0xbf, 0x71, 0xfa, 0x00, 0xf0, 0x08, 0xbf, 0xcf, 0x41, 0x08, 0xbf, 0x61, 0xfa, 0x08, 0xf8, 0x08, 0xbf, 0x68, 0xfa, 0x01, 0xf8, 0x08, 0xbf, 0x68, 0xfa, 0x03, 0xf3, 0x08, 0xbf, 0x61, 0xfa, 0x08, 0xf1, 0x52, 0xea, 0x01, 0x07, 0x0a, 0x43, 0x0b, 0x43, 0x54, 0xea, 0x01, 0x04, 0x51, 0xea, 0x05, 0x05, 0x41, 0xea, 0x02, 0x02, 0x0f, 0x43, 0x0f, 0x43, 0x51, 0xea, 0x08, 0x08, 0x58, 0xea, 0x01, 0x08, 0x58, 0xea, 0x01, 0x01, 0x50, 0xea, 0x08, 0x00, 0x51, 0xea, 0x41, 0x01, 0x51, 0xea, 0x50, 0x00, 0x08, 0xbf, 0x42, 0xea, 0x01, 0x00, 0x08, 0xbf, 0x0d, 0x43, 0x08, 0xbf, 0x0d, 0x43, 0x08, 0xbf, 0x42, 0xea, 0x01, 0x02, 0x08, 0xbf, 0x41, 0xea, 0x03, 0x03, 0x08, 0xbf, 0x51, 0xea, 0x04, 0x04, 0x08, 0xbf, 0x0f, 0x43, 0x08, 0xbf, 0x0f, 0x43, 0x08, 0xbf, 0x41, 0xea, 0x08, 0x08, 0x08, 0xbf, 0x48, 0xea, 0x01, 0x08, 0x08, 0xbf, 0x48, 0xea, 0x00, 0x00, 0x08, 0xbf, 0x40, 0xea, 0x08, 0x00, 0x08, 0xbf, 0x42, 0xea, 0x41, 0x02, 0x08, 0xbf, 0x41, 0xea, 0x52, 0x02, 0x32, 0xea, 0x01, 0x03, 0x8a, 0x43, 0x32, 0xea, 0x01, 0x01, 0x32, 0xea, 0x01, 0x02, 0x31, 0xea, 0x00, 0x00, 0x21, 0xea, 0x00, 0x00, 0x8f, 0x43, 0x31, 0xea, 0x08, 0x08, 0x38, 0xea, 0x01, 0x08, 0x38, 0xea, 0x07, 0x07, 0x35, 0xea, 0x08, 0x05, 0x33, 0xea, 0x41, 0x03, 0x31, 0xea, 0x54, 0x04, 0x08, 0xbf, 0x22, 0xea, 0x01, 0x00, 0x08, 0xbf, 0x8d, 0x43, 0x08, 0xbf, 0x25, 0xea, 0x01, 0x01, 0x08, 0xbf, 0x24, 0xea, 0x01, 0x04, 0x08, 0xbf, 0x21, 0xea, 0x02, 0x02, 0x08, 0xbf, 0x31, 0xea, 0x05, 0x05, 0x08, 0xbf, 0x8f, 0x43, 0x08, 0xbf, 0x21, 0xea, 0x08, 0x08, 0x08, 0xbf, 0x28, 0xea, 0x01, 0x08, 0x08, 0xbf, 0x28, 0xea, 0x00, 0x00, 0x08, 0xbf, 0x22, 0xea, 0x08, 0x02, 0x08, 0xbf, 0x24, 0xea, 0x41, 0x04, 0x08, 0xbf, 0x21, 0xea, 0x55, 0x05 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "adds r0, r0, #5" + - + asm_text: "adds r1, #8" + - + asm_text: "adds.w r1, r1, #8" + - + asm_text: "adds.w r8, r8, #8" + - + asm_text: "it eq" + - + asm_text: "addeq r0, r0, #5" + - + asm_text: "it eq" + - + asm_text: "addeq r1, #8" + - + asm_text: "it eq" + - + asm_text: "addseq.w r0, r0, #5" + - + asm_text: "it eq" + - + asm_text: "addseq.w r1, r1, #8" + - + asm_text: "adds r0, r2, r1" + - + asm_text: "adds r2, r2, r1" + - + asm_text: "add r3, r1" + - + asm_text: "it eq" + - + asm_text: "addeq r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "addeq r2, r2, r1" + - + asm_text: "it eq" + - + asm_text: "addseq.w r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "addseq.w r2, r2, r1" + - + asm_text: "add r3, r1" + - + asm_text: "add r4, pc" + - + asm_text: "add r4, pc" + - + asm_text: "add pc, r2" + - + asm_text: "add pc, r2" + - + asm_text: "add pc, sp, pc" + - + asm_text: "add sp, #0x14" + - + asm_text: "add sp, #0x1fc" + - + asm_text: "add.w sp, sp, #0x200" + - + asm_text: "add r9, sp, r9" + - + asm_text: "add sp, r10" + - + asm_text: "add sp, r10" + - + asm_text: "add sp, pc" + - + asm_text: "ands.w r0, r2, r1" + - + asm_text: "ands r2, r1" + - + asm_text: "ands r2, r1" + - + asm_text: "ands.w r0, r0, r1" + - + asm_text: "ands.w r3, r1, r3" + - + asm_text: "and.w r0, r1, r0" + - + asm_text: "ands r7, r1" + - + asm_text: "ands r7, r1" + - + asm_text: "ands.w r8, r1, r8" + - + asm_text: "ands.w r8, r8, r1" + - + asm_text: "ands.w r0, r8, r0" + - + asm_text: "ands.w r1, r1, r8" + - + asm_text: "ands.w r2, r2, r1, lsl #1" + - + asm_text: "ands.w r0, r1, r0, lsr #1" + - + asm_text: "it eq" + - + asm_text: "andeq.w r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "andeq r3, r1" + - + asm_text: "it eq" + - + asm_text: "andeq r3, r1" + - + asm_text: "it eq" + - + asm_text: "andeq.w r0, r0, r1" + - + asm_text: "it eq" + - + asm_text: "andeq.w r2, r1, r2" + - + asm_text: "it eq" + - + asm_text: "andseq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "andeq r7, r1" + - + asm_text: "it eq" + - + asm_text: "andeq r7, r1" + - + asm_text: "it eq" + - + asm_text: "andeq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "andeq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "andeq.w r4, r8, r4" + - + asm_text: "it eq" + - + asm_text: "andeq.w r4, r4, r8" + - + asm_text: "it eq" + - + asm_text: "andeq.w r0, r0, r1, lsl #1" + - + asm_text: "it eq" + - + asm_text: "andeq.w r5, r1, r5, lsr #1" + - + asm_text: "eors.w r0, r2, r1" + - + asm_text: "eors r5, r1" + - + asm_text: "eors r5, r1" + - + asm_text: "eors.w r0, r0, r1" + - + asm_text: "eors.w r2, r1, r2" + - + asm_text: "eor.w r1, r1, r1" + - + asm_text: "eors r7, r1" + - + asm_text: "eors r7, r1" + - + asm_text: "eors.w r8, r1, r8" + - + asm_text: "eors.w r8, r8, r1" + - + asm_text: "eors.w r6, r8, r6" + - + asm_text: "eors.w r0, r0, r8" + - + asm_text: "eors.w r2, r2, r1, lsl #1" + - + asm_text: "eors.w r0, r1, r0, lsr #1" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r3, r2, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq r0, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq r2, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r3, r3, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "eorseq.w r1, r1, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r0, r8, r0" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r3, r3, r8" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r4, r4, r1, lsl #1" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r0, r1, r0, lsr #1" + - + asm_text: "lsls.w r0, r2, r1" + - + asm_text: "lsls r2, r1" + - + asm_text: "lsls.w r2, r1, r2" + - + asm_text: "lsls.w r0, r0, r1" + - + asm_text: "lsls.w r4, r1, r4" + - + asm_text: "lsl.w r4, r1, r4" + - + asm_text: "lsls r7, r1" + - + asm_text: "lsls.w r8, r1, r8" + - + asm_text: "lsls.w r8, r8, r1" + - + asm_text: "lsls.w r3, r8, r3" + - + asm_text: "lsls.w r5, r5, r8" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "lsleq r2, r1" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r2, r1, r2" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r0, r0, r1" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r3, r1, r3" + - + asm_text: "it eq" + - + asm_text: "lslseq.w r4, r1, r4" + - + asm_text: "it eq" + - + asm_text: "lsleq r7, r1" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r0, r8, r0" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r3, r3, r8" + - + asm_text: "lsrs.w r6, r2, r1" + - + asm_text: "lsrs r2, r1" + - + asm_text: "lsrs.w r2, r1, r2" + - + asm_text: "lsrs.w r2, r2, r1" + - + asm_text: "lsrs.w r3, r1, r3" + - + asm_text: "lsr.w r4, r1, r4" + - + asm_text: "lsrs r7, r1" + - + asm_text: "lsrs.w r8, r1, r8" + - + asm_text: "lsrs.w r8, r8, r1" + - + asm_text: "lsrs.w r2, r8, r2" + - + asm_text: "lsrs.w r5, r5, r8" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r6, r2, r1" + - + asm_text: "it eq" + - + asm_text: "lsreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r7, r1, r7" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r7, r7, r1" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r2, r1, r2" + - + asm_text: "it eq" + - + asm_text: "lsrseq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "lsreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r1, r8, r1" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r4, r4, r8" + - + asm_text: "asrs.w r7, r6, r5" + - + asm_text: "asrs r0, r1" + - + asm_text: "asrs.w r0, r1, r0" + - + asm_text: "asrs.w r3, r3, r1" + - + asm_text: "asrs.w r1, r1, r1" + - + asm_text: "asr.w r0, r1, r0" + - + asm_text: "asrs r7, r1" + - + asm_text: "asrs.w r8, r1, r8" + - + asm_text: "asrs.w r8, r8, r1" + - + asm_text: "asrs.w r5, r8, r5" + - + asm_text: "asrs.w r5, r5, r8" + - + asm_text: "it eq" + - + asm_text: "asreq.w r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "asreq r2, r1" + - + asm_text: "it eq" + - + asm_text: "asreq.w r1, r2, r1" + - + asm_text: "it eq" + - + asm_text: "asreq.w r4, r4, r1" + - + asm_text: "it eq" + - + asm_text: "asreq.w r6, r1, r6" + - + asm_text: "it eq" + - + asm_text: "asrseq.w r3, r1, r3" + - + asm_text: "it eq" + - + asm_text: "asreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "asreq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "asreq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "asreq.w r1, r8, r1" + - + asm_text: "it eq" + - + asm_text: "asreq.w r3, r3, r8" + - + asm_text: "adcs.w r5, r2, r1" + - + asm_text: "adcs r5, r1" + - + asm_text: "adcs r3, r1" + - + asm_text: "adcs.w r2, r2, r1" + - + asm_text: "adcs.w r3, r1, r3" + - + asm_text: "adc.w r0, r1, r0" + - + asm_text: "adcs r7, r1" + - + asm_text: "adcs r7, r1" + - + asm_text: "adcs.w r8, r1, r8" + - + asm_text: "adcs.w r8, r8, r1" + - + asm_text: "adcs.w r5, r8, r5" + - + asm_text: "adcs.w r2, r2, r8" + - + asm_text: "adcs.w r3, r3, r1, lsl #1" + - + asm_text: "adcs.w r4, r1, r4, lsr #1" + - + asm_text: "it eq" + - + asm_text: "adceq.w r1, r2, r3" + - + asm_text: "it eq" + - + asm_text: "adceq r1, r1" + - + asm_text: "it eq" + - + asm_text: "adceq r3, r1" + - + asm_text: "it eq" + - + asm_text: "adceq.w r3, r3, r1" + - + asm_text: "it eq" + - + asm_text: "adceq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "adcseq.w r3, r1, r3" + - + asm_text: "it eq" + - + asm_text: "adceq r7, r1" + - + asm_text: "it eq" + - + asm_text: "adceq r7, r1" + - + asm_text: "it eq" + - + asm_text: "adceq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "adceq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "adceq.w r3, r8, r3" + - + asm_text: "it eq" + - + asm_text: "adceq.w r1, r1, r8" + - + asm_text: "it eq" + - + asm_text: "adceq.w r2, r2, r1, lsl #1" + - + asm_text: "it eq" + - + asm_text: "adceq.w r1, r1, r1, lsr #1" + - + asm_text: "sbcs.w r3, r2, r1" + - + asm_text: "sbcs r4, r1" + - + asm_text: "sbcs.w r1, r4, r1" + - + asm_text: "sbcs.w r4, r4, r1" + - + asm_text: "sbcs.w r2, r1, r2" + - + asm_text: "sbc.w r0, r1, r0" + - + asm_text: "sbcs r7, r1" + - + asm_text: "sbcs.w r8, r1, r8" + - + asm_text: "sbcs.w r8, r8, r1" + - + asm_text: "sbcs.w r4, r8, r4" + - + asm_text: "sbcs.w r3, r3, r8" + - + asm_text: "sbcs.w r2, r2, r1, lsl #1" + - + asm_text: "sbcs.w r5, r1, r5, lsr #1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r5, r2, r1" + - + asm_text: "it eq" + - + asm_text: "sbceq r5, r1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r1, r5, r1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r5, r5, r1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "sbcseq.w r2, r1, r2" + - + asm_text: "it eq" + - + asm_text: "sbceq r7, r1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r7, r8, r7" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r7, r7, r8" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r2, r2, r1, lsl #1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r5, r1, r5, lsr #1" + - + asm_text: "rors.w r3, r2, r1" + - + asm_text: "rors r0, r1" + - + asm_text: "rors.w r1, r0, r1" + - + asm_text: "rors.w r2, r2, r1" + - + asm_text: "rors.w r2, r1, r2" + - + asm_text: "ror.w r5, r1, r5" + - + asm_text: "rors r7, r1" + - + asm_text: "rors.w r8, r1, r8" + - + asm_text: "rors.w r8, r8, r1" + - + asm_text: "rors.w r6, r8, r6" + - + asm_text: "rors.w r6, r6, r8" + - + asm_text: "it eq" + - + asm_text: "roreq.w r4, r2, r1" + - + asm_text: "it eq" + - + asm_text: "roreq r4, r1" + - + asm_text: "it eq" + - + asm_text: "roreq.w r1, r4, r1" + - + asm_text: "it eq" + - + asm_text: "roreq.w r4, r4, r1" + - + asm_text: "it eq" + - + asm_text: "roreq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "rorseq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "roreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "roreq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "roreq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "roreq.w r3, r8, r3" + - + asm_text: "it eq" + - + asm_text: "roreq.w r1, r1, r8" + - + asm_text: "orrs.w r7, r2, r1" + - + asm_text: "orrs r2, r1" + - + asm_text: "orrs r3, r1" + - + asm_text: "orrs.w r4, r4, r1" + - + asm_text: "orrs.w r5, r1, r5" + - + asm_text: "orr.w r2, r1, r2" + - + asm_text: "orrs r7, r1" + - + asm_text: "orrs r7, r1" + - + asm_text: "orrs.w r8, r1, r8" + - + asm_text: "orrs.w r8, r8, r1" + - + asm_text: "orrs.w r1, r8, r1" + - + asm_text: "orrs.w r0, r0, r8" + - + asm_text: "orrs.w r1, r1, r1, lsl #1" + - + asm_text: "orrs.w r0, r1, r0, lsr #1" + - + asm_text: "it eq" + - + asm_text: "orreq.w r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "orreq r5, r1" + - + asm_text: "it eq" + - + asm_text: "orreq r5, r1" + - + asm_text: "it eq" + - + asm_text: "orreq.w r2, r2, r1" + - + asm_text: "it eq" + - + asm_text: "orreq.w r3, r1, r3" + - + asm_text: "it eq" + - + asm_text: "orrseq.w r4, r1, r4" + - + asm_text: "it eq" + - + asm_text: "orreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "orreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "orreq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "orreq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "orreq.w r0, r8, r0" + - + asm_text: "it eq" + - + asm_text: "orreq.w r0, r0, r8" + - + asm_text: "it eq" + - + asm_text: "orreq.w r2, r2, r1, lsl #1" + - + asm_text: "it eq" + - + asm_text: "orreq.w r2, r1, r2, lsr #1" + - + asm_text: "bics.w r3, r2, r1" + - + asm_text: "bics r2, r1" + - + asm_text: "bics.w r1, r2, r1" + - + asm_text: "bics.w r2, r2, r1" + - + asm_text: "bics.w r0, r1, r0" + - + asm_text: "bic.w r0, r1, r0" + - + asm_text: "bics r7, r1" + - + asm_text: "bics.w r8, r1, r8" + - + asm_text: "bics.w r8, r8, r1" + - + asm_text: "bics.w r7, r8, r7" + - + asm_text: "bics.w r5, r5, r8" + - + asm_text: "bics.w r3, r3, r1, lsl #1" + - + asm_text: "bics.w r4, r1, r4, lsr #1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "biceq r5, r1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r1, r5, r1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r4, r4, r1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r2, r1, r2" + - + asm_text: "it eq" + - + asm_text: "bicseq.w r5, r1, r5" + - + asm_text: "it eq" + - + asm_text: "biceq r7, r1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "biceq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r0, r8, r0" + - + asm_text: "it eq" + - + asm_text: "biceq.w r2, r2, r8" + - + asm_text: "it eq" + - + asm_text: "biceq.w r4, r4, r1, lsl #1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r5, r1, r5, lsr #1" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb2-pldw.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb2-pldw.s.yaml new file mode 100644 index 0000000..5604eb4 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb2-pldw.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xb0, 0xf8, 0x01, 0xf1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "pldw [r0, #0x101]" diff --git a/thirdparty/capstone/tests/MC/ARM/thumb_rewrites.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumb_rewrites.s.yaml new file mode 100644 index 0000000..7b27020 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumb_rewrites.s.yaml @@ -0,0 +1,70 @@ +test_cases: + - + input: + bytes: [ 0xc9, 0x1c, 0x03, 0x31, 0x08, 0x30, 0x00, 0x18, 0x40, 0x44, 0x41, 0x44, 0x85, 0x44, 0x6c, 0x44, 0x08, 0xb0, 0xfe, 0xad, 0x08, 0x44, 0x1a, 0x44, 0x00, 0x1a, 0x5b, 0x1f, 0x05, 0x3b, 0x08, 0x3a, 0x84, 0xb0, 0x08, 0x40, 0x08, 0x40, 0x48, 0x40, 0x48, 0x40, 0x88, 0x40, 0xc8, 0x40, 0x08, 0x41, 0x48, 0x41, 0x48, 0x41, 0x88, 0x41, 0xc8, 0x41, 0x08, 0x43, 0x08, 0x43, 0x88, 0x43 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "adds r1, r1, #3" + - + asm_text: "adds r1, #3" + - + asm_text: "adds r0, #8" + - + asm_text: "adds r0, r0, r0" + - + asm_text: "add r0, r8" + - + asm_text: "add r1, r8" + - + asm_text: "add sp, r0" + - + asm_text: "add r4, sp, r4" + - + asm_text: "add sp, #0x20" + - + asm_text: "add r5, sp, #0x3f8" + - + asm_text: "add r0, r1" + - + asm_text: "add r2, r3" + - + asm_text: "subs r0, r0, r0" + - + asm_text: "subs r3, r3, #5" + - + asm_text: "subs r3, #5" + - + asm_text: "subs r2, #8" + - + asm_text: "sub sp, #0x10" + - + asm_text: "ands r0, r1" + - + asm_text: "ands r0, r1" + - + asm_text: "eors r0, r1" + - + asm_text: "eors r0, r1" + - + asm_text: "lsls r0, r1" + - + asm_text: "lsrs r0, r1" + - + asm_text: "asrs r0, r1" + - + asm_text: "adcs r0, r1" + - + asm_text: "adcs r0, r1" + - + asm_text: "sbcs r0, r1" + - + asm_text: "rors r0, r1" + - + asm_text: "orrs r0, r1" + - + asm_text: "orrs r0, r1" + - + asm_text: "bics r0, r1" diff --git a/thirdparty/capstone/tests/MC/ARM/thumbv7em.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumbv7em.s.yaml new file mode 100644 index 0000000..e35517f --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumbv7em.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x80, 0xf3, 0x00, 0x84, 0x80, 0xf3, 0x00, 0x8c, 0x80, 0xf3, 0x01, 0x84, 0x80, 0xf3, 0x01, 0x8c, 0x80, 0xf3, 0x02, 0x84, 0x80, 0xf3, 0x02, 0x8c, 0x80, 0xf3, 0x03, 0x84, 0x80, 0xf3, 0x03, 0x8c ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "msr apsr_g, r0" + - + asm_text: "msr apsr_nzcvqg, r0" + - + asm_text: "msr iapsr_g, r0" + - + asm_text: "msr iapsr_nzcvqg, r0" + - + asm_text: "msr eapsr_g, r0" + - + asm_text: "msr eapsr_nzcvqg, r0" + - + asm_text: "msr xpsr_g, r0" + - + asm_text: "msr xpsr_nzcvqg, r0" diff --git a/thirdparty/capstone/tests/MC/ARM/thumbv7m.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumbv7m.s.yaml new file mode 100644 index 0000000..c31e3d2 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumbv7m.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xef, 0xf3, 0x11, 0x80, 0xef, 0xf3, 0x12, 0x80, 0xef, 0xf3, 0x13, 0x80, 0x80, 0xf3, 0x11, 0x88, 0x80, 0xf3, 0x12, 0x88, 0x80, 0xf3, 0x13, 0x88 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "mrs r0, basepri" + - + asm_text: "mrs r0, basepri_max" + - + asm_text: "mrs r0, faultmask" + - + asm_text: "msr basepri, r0" + - + asm_text: "msr basepri_max, r0" + - + asm_text: "msr faultmask, r0" diff --git a/thirdparty/capstone/tests/MC/ARM/thumbv8.1m-vmrs-vmsr.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumbv8.1m-vmrs-vmsr.s.yaml new file mode 100644 index 0000000..bc3bb69 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumbv8.1m-vmrs-vmsr.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0xe2, 0xee, 0x10, 0x0a, 0xf2, 0xee, 0x10, 0xaa, 0xfe, 0xee, 0x10, 0x0a, 0xee, 0xee, 0x10, 0xaa, 0xef, 0xee, 0x10, 0x5a, 0xfe, 0xee, 0x10, 0x3a, 0xff, 0xee, 0x10, 0x0a, 0xfc, 0xee, 0x10, 0x0a, 0xfd, 0xee, 0x10, 0x4a, 0xec, 0xee, 0x10, 0x0a, 0xed, 0xee, 0x10, 0x4a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmsr fpscr_nzcvqc, r0" + - + asm_text: "vmrs r10, fpscr_nzcvqc" + - + asm_text: "vmrs r0, fpcxtns" + - + asm_text: "vmsr fpcxtns, r10" + - + asm_text: "vmsr fpcxts, r5" + - + asm_text: "vmrs r3, fpcxtns" + - + asm_text: "vmrs r0, fpcxts" + - + asm_text: "vmrs r0, vpr" + - + asm_text: "vmrs r4, p0" + - + asm_text: "vmsr vpr, r0" + - + asm_text: "vmsr p0, r4" diff --git a/thirdparty/capstone/tests/MC/ARM/thumbv8.1m.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumbv8.1m.s.yaml new file mode 100644 index 0000000..d3f18fe --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumbv8.1m.s.yaml @@ -0,0 +1,338 @@ +test_cases: + - + input: + bytes: [ 0x42, 0xf0, 0x01, 0xe0, 0x4e, 0xf0, 0x01, 0xe0, 0x40, 0xf0, 0x01, 0xe0, 0x41, 0xf0, 0x01, 0xe0, 0x4a, 0xf0, 0x01, 0xe0, 0x4b, 0xf0, 0x01, 0xe0, 0x4c, 0xf0, 0x01, 0xe0, 0x42, 0xf0, 0x01, 0xe0, 0x43, 0xf0, 0x01, 0xe0, 0x45, 0xf0, 0x01, 0xe0, 0x46, 0xf0, 0x01, 0xe0, 0x47, 0xf0, 0x01, 0xe0, 0x48, 0xf0, 0x01, 0xe0, 0x49, 0xf0, 0x01, 0xe0, 0x2f, 0xf0, 0x35, 0xc8, 0x2f, 0xf0, 0x4b, 0xc2, 0x2f, 0xf0, 0x5d, 0xca, 0x2f, 0xf0, 0x77, 0xc2, 0x2f, 0xf0, 0x77, 0xca, 0x2f, 0xf0, 0x83, 0xc2, 0x2f, 0xf0, 0x83, 0xca, 0x2f, 0xf0, 0x0b, 0xc3, 0x2f, 0xf0, 0x59, 0xc8, 0x2f, 0xf0, 0xad, 0xcb, 0x2f, 0xf0, 0xb7, 0xc3, 0x2f, 0xf0, 0xbb, 0xcb, 0x2f, 0xf0, 0x0f, 0xc4, 0x2f, 0xf0, 0x6d, 0xcc, 0x2f, 0xf0, 0x8b, 0xc4, 0x2f, 0xf0, 0x8d, 0xc4, 0x2f, 0xf0, 0xcd, 0xc4, 0x2f, 0xf0, 0x7b, 0xc8, 0x2f, 0xf0, 0xd7, 0xc4, 0x2f, 0xf0, 0x09, 0xcd, 0x2f, 0xf0, 0x83, 0xc8, 0x2f, 0xf0, 0x33, 0xc5, 0x2f, 0xf0, 0x51, 0xcd, 0x2f, 0xf0, 0x9b, 0xc5, 0x2f, 0xf0, 0xa1, 0xcd, 0x2f, 0xf0, 0x29, 0xce, 0x2f, 0xf0, 0x65, 0xce, 0x2f, 0xf0, 0x8d, 0xc6, 0x2f, 0xf0, 0xa9, 0xc8, 0x2f, 0xf0, 0xc1, 0xce, 0x2f, 0xf0, 0xcd, 0xc6, 0x2f, 0xf0, 0xeb, 0xce, 0x2f, 0xf0, 0x1f, 0xc7, 0x2f, 0xf0, 0x2f, 0xc7, 0x2f, 0xf0, 0x37, 0xc7, 0x2f, 0xf0, 0x8b, 0xc7, 0x2f, 0xf0, 0xc9, 0xcf, 0x2f, 0xf0, 0xd3, 0xcf, 0x2f, 0xf0, 0xe1, 0xcf, 0x2f, 0xf0, 0xef, 0xc7, 0x2f, 0xf0, 0xf3, 0xc7, 0x2f, 0xf0, 0xef, 0xc8, 0x2f, 0xf0, 0x11, 0xc1, 0x2f, 0xf0, 0x25, 0xc9, 0x2f, 0xf0, 0x2f, 0xc9, 0x2f, 0xf0, 0x49, 0xc1, 0x2f, 0xf0, 0x73, 0xc1, 0x2f, 0xf0, 0x7d, 0xc9, 0x2f, 0xf0, 0xaf, 0xc9, 0x2f, 0xf0, 0xb3, 0xc9, 0x0f, 0xf0, 0x1d, 0xc2, 0x0f, 0xf0, 0x29, 0xc2, 0x0f, 0xf0, 0x41, 0xc2, 0x0f, 0xf0, 0xdb, 0xca, 0x0f, 0xf0, 0xdf, 0xca, 0x0f, 0xf0, 0x27, 0xc3, 0x0f, 0xf0, 0x31, 0xc3, 0x0f, 0xf0, 0x4f, 0xcb, 0x0f, 0xf0, 0x59, 0xcb, 0x0f, 0xf0, 0x9d, 0xcb, 0x0f, 0xf0, 0xab, 0xcb, 0x0f, 0xf0, 0xb5, 0xc3, 0x0f, 0xf0, 0xc1, 0xcb, 0x0f, 0xf0, 0xc3, 0xcb, 0x0f, 0xf0, 0x01, 0xc8, 0x0f, 0xf0, 0x1d, 0xc4, 0x0f, 0xf0, 0x23, 0xc4, 0x0f, 0xf0, 0x31, 0xc4, 0x0f, 0xf0, 0x47, 0xc4, 0x0f, 0xf0, 0x95, 0xc4, 0x0f, 0xf0, 0xcd, 0xc4, 0x0f, 0xf0, 0x19, 0xc5, 0x0f, 0xf0, 0x1d, 0xc5, 0x0f, 0xf0, 0x1f, 0xcd, 0x0f, 0xf0, 0x3d, 0xc5, 0x0f, 0xf0, 0x43, 0xcd, 0x0f, 0xf0, 0x91, 0xcd, 0x0f, 0xf0, 0x97, 0xc5, 0x0f, 0xf0, 0xdf, 0xc5, 0x0f, 0xf0, 0xe5, 0xcd, 0x0f, 0xf0, 0x99, 0xc0, 0x0f, 0xf0, 0x0d, 0xce, 0x0f, 0xf0, 0x4f, 0xc6, 0x0f, 0xf0, 0x7b, 0xc6, 0x0f, 0xf0, 0x83, 0xc6, 0x0f, 0xf0, 0x8d, 0xce, 0x0f, 0xf0, 0xbd, 0xcf, 0x0f, 0xf0, 0xe5, 0xcf, 0x0f, 0xf0, 0xeb, 0xc7, 0x0f, 0xf0, 0xe5, 0xc8, 0x0f, 0xf0, 0x1d, 0xc0, 0x0f, 0xf0, 0x23, 0xc9, 0x0f, 0xf0, 0x53, 0xc1, 0x0f, 0xf0, 0x79, 0xc1, 0x0f, 0xf0, 0x27, 0xc0, 0x0f, 0xf0, 0x91, 0xc9, 0x0f, 0xf0, 0xaf, 0xc9, 0x0f, 0xf0, 0xc3, 0xc9, 0x0f, 0xf0, 0xe5, 0xc1, 0x4e, 0xf0, 0x55, 0xc2, 0x4e, 0xf0, 0x2b, 0xcc, 0x4e, 0xf0, 0xe1, 0xc9, 0x40, 0xf0, 0x43, 0xc3, 0x40, 0xf0, 0x49, 0xcd, 0x40, 0xf0, 0xe9, 0xcd, 0x40, 0xf0, 0xb7, 0xc6, 0x41, 0xf0, 0x13, 0xc2, 0x41, 0xf0, 0xe3, 0xc7, 0x41, 0xf0, 0x0d, 0xc9, 0x4a, 0xf0, 0xbf, 0xc2, 0x4a, 0xf0, 0xc1, 0xc2, 0x4a, 0xf0, 0x9b, 0xcc, 0x4a, 0xf0, 0xfb, 0xcf, 0x4b, 0xf0, 0xd1, 0xca, 0x4b, 0xf0, 0x3b, 0xcd, 0x4b, 0xf0, 0x0d, 0xcf, 0x4c, 0xf0, 0x67, 0xc8, 0x4c, 0xf0, 0xa9, 0xc5, 0x4c, 0xf0, 0x5d, 0xce, 0x42, 0xf0, 0x55, 0xce, 0x42, 0xf0, 0x7d, 0xc7, 0x42, 0xf0, 0xb5, 0xc1, 0x43, 0xf0, 0xdd, 0xce, 0x43, 0xf0, 0x1b, 0xc7, 0x43, 0xf0, 0xb3, 0xcf, 0x43, 0xf0, 0x65, 0xc1, 0x44, 0xf0, 0x31, 0xcc, 0x44, 0xf0, 0xdb, 0xcc, 0x45, 0xf0, 0xb9, 0xcb, 0x45, 0xf0, 0xa3, 0xc6, 0x46, 0xf0, 0x7f, 0xce, 0x46, 0xf0, 0xd1, 0xc0, 0x46, 0xf0, 0xd3, 0xc8, 0x47, 0xf0, 0xc9, 0xce, 0x47, 0xf0, 0x1d, 0xc7, 0x48, 0xf0, 0x47, 0xc5, 0x49, 0xf0, 0x2d, 0xca, 0x49, 0xf0, 0xe1, 0xc3, 0x49, 0xf0, 0x57, 0xcf, 0x49, 0xf0, 0x6b, 0xc7, 0x52, 0xea, 0x22, 0x9e, 0x57, 0xea, 0x47, 0x9e, 0x5c, 0xea, 0x3c, 0xae, 0x5a, 0xea, 0x3a, 0xbe, 0x59, 0xea, 0x7b, 0x89, 0x5f, 0xea, 0x1f, 0x9e, 0x5f, 0xea, 0x3f, 0xae, 0x5a, 0xea, 0xd7, 0x9e, 0x55, 0xea, 0x2f, 0xae, 0x52, 0xea, 0x42, 0xae, 0x50, 0xea, 0x01, 0x80 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "dls lr, r2" + - + asm_text: "dls lr, lr" + - + asm_text: "dls lr, r0" + - + asm_text: "dls lr, r1" + - + asm_text: "dls lr, r10" + - + asm_text: "dls lr, r11" + - + asm_text: "dls lr, r12" + - + asm_text: "dls lr, r2" + - + asm_text: "dls lr, r3" + - + asm_text: "dls lr, r5" + - + asm_text: "dls lr, r6" + - + asm_text: "dls lr, r7" + - + asm_text: "dls lr, r8" + - + asm_text: "dls lr, r9" + - + asm_text: "le #-0x6a" + - + asm_text: "le #-0x494" + - + asm_text: "le #-0x4ba" + - + asm_text: "le #-0x4ec" + - + asm_text: "le #-0x4ee" + - + asm_text: "le #-0x504" + - + asm_text: "le #-0x506" + - + asm_text: "le #-0x614" + - + asm_text: "le #-0xb2" + - + asm_text: "le #-0x75a" + - + asm_text: "le #-0x76c" + - + asm_text: "le #-0x776" + - + asm_text: "le #-0x81c" + - + asm_text: "le #-0x8da" + - + asm_text: "le #-0x914" + - + asm_text: "le #-0x918" + - + asm_text: "le #-0x998" + - + asm_text: "le #-0xf6" + - + asm_text: "le #-0x9ac" + - + asm_text: "le #-0xa12" + - + asm_text: "le #-0x106" + - + asm_text: "le #-0xa64" + - + asm_text: "le #-0xaa2" + - + asm_text: "le #-0xb34" + - + asm_text: "le #-0xb42" + - + asm_text: "le #-0xc52" + - + asm_text: "le #-0xcca" + - + asm_text: "le #-0xd18" + - + asm_text: "le #-0x152" + - + asm_text: "le #-0xd82" + - + asm_text: "le #-0xd98" + - + asm_text: "le #-0xdd6" + - + asm_text: "le #-0xe3c" + - + asm_text: "le #-0xe5c" + - + asm_text: "le #-0xe6c" + - + asm_text: "le #-0xf14" + - + asm_text: "le #-0xf92" + - + asm_text: "le #-0xfa6" + - + asm_text: "le #-0xfc2" + - + asm_text: "le #-0xfdc" + - + asm_text: "le #-0xfe4" + - + asm_text: "le #-0x1de" + - + asm_text: "le #-0x220" + - + asm_text: "le #-0x24a" + - + asm_text: "le #-0x25e" + - + asm_text: "le #-0x290" + - + asm_text: "le #-0x2e4" + - + asm_text: "le #-0x2fa" + - + asm_text: "le #-0x35e" + - + asm_text: "le #-0x366" + - + asm_text: "le lr, #-0x438" + - + asm_text: "le lr, #-0x450" + - + asm_text: "le lr, #-0x480" + - + asm_text: "le lr, #-0x5b6" + - + asm_text: "le lr, #-0x5be" + - + asm_text: "le lr, #-0x64c" + - + asm_text: "le lr, #-0x660" + - + asm_text: "le lr, #-0x69e" + - + asm_text: "le lr, #-0x6b2" + - + asm_text: "le lr, #-0x73a" + - + asm_text: "le lr, #-0x756" + - + asm_text: "le lr, #-0x768" + - + asm_text: "le lr, #-0x782" + - + asm_text: "le lr, #-0x786" + - + asm_text: "le lr, #-2" + - + asm_text: "le lr, #-0x838" + - + asm_text: "le lr, #-0x844" + - + asm_text: "le lr, #-0x860" + - + asm_text: "le lr, #-0x88c" + - + asm_text: "le lr, #-0x928" + - + asm_text: "le lr, #-0x998" + - + asm_text: "le lr, #-0xa30" + - + asm_text: "le lr, #-0xa38" + - + asm_text: "le lr, #-0xa3e" + - + asm_text: "le lr, #-0xa78" + - + asm_text: "le lr, #-0xa86" + - + asm_text: "le lr, #-0xb22" + - + asm_text: "le lr, #-0xb2c" + - + asm_text: "le lr, #-0xbbc" + - + asm_text: "le lr, #-0xbca" + - + asm_text: "le lr, #-0x130" + - + asm_text: "le lr, #-0xc1a" + - + asm_text: "le lr, #-0xc9c" + - + asm_text: "le lr, #-0xcf4" + - + asm_text: "le lr, #-0xd04" + - + asm_text: "le lr, #-0xd1a" + - + asm_text: "le lr, #-0xf7a" + - + asm_text: "le lr, #-0xfca" + - + asm_text: "le lr, #-0xfd4" + - + asm_text: "le lr, #-0x1ca" + - + asm_text: "le lr, #-0x38" + - + asm_text: "le lr, #-0x246" + - + asm_text: "le lr, #-0x2a4" + - + asm_text: "le lr, #-0x2f0" + - + asm_text: "le lr, #-0x4c" + - + asm_text: "le lr, #-0x322" + - + asm_text: "le lr, #-0x35e" + - + asm_text: "le lr, #-0x386" + - + asm_text: "le lr, #-0x3c8" + - + asm_text: "wls lr, lr, #0x4a8" + - + asm_text: "wls lr, lr, #0x856" + - + asm_text: "wls lr, lr, #0x3c2" + - + asm_text: "wls lr, r0, #0x684" + - + asm_text: "wls lr, r0, #0xa92" + - + asm_text: "wls lr, r0, #0xbd2" + - + asm_text: "wls lr, r0, #0xd6c" + - + asm_text: "wls lr, r1, #0x424" + - + asm_text: "wls lr, r1, #0xfc4" + - + asm_text: "wls lr, r1, #0x21a" + - + asm_text: "wls lr, r10, #0x57c" + - + asm_text: "wls lr, r10, #0x580" + - + asm_text: "wls lr, r10, #0x936" + - + asm_text: "wls lr, r10, #0xff6" + - + asm_text: "wls lr, r11, #0x5a2" + - + asm_text: "wls lr, r11, #0xa76" + - + asm_text: "wls lr, r11, #0xe1a" + - + asm_text: "wls lr, r12, #0xce" + - + asm_text: "wls lr, r12, #0xb50" + - + asm_text: "wls lr, r12, #0xcba" + - + asm_text: "wls lr, r2, #0xcaa" + - + asm_text: "wls lr, r2, #0xef8" + - + asm_text: "wls lr, r2, #0x368" + - + asm_text: "wls lr, r3, #0xdba" + - + asm_text: "wls lr, r3, #0xe34" + - + asm_text: "wls lr, r3, #0xf66" + - + asm_text: "wls lr, r3, #0x2c8" + - + asm_text: "wls lr, r4, #0x862" + - + asm_text: "wls lr, r4, #0x9b6" + - + asm_text: "wls lr, r5, #0x772" + - + asm_text: "wls lr, r5, #0xd44" + - + asm_text: "wls lr, r6, #0xcfe" + - + asm_text: "wls lr, r6, #0x1a0" + - + asm_text: "wls lr, r6, #0x1a6" + - + asm_text: "wls lr, r7, #0xd92" + - + asm_text: "wls lr, r7, #0xe38" + - + asm_text: "wls lr, r8, #0xa8c" + - + asm_text: "wls lr, r9, #0x45a" + - + asm_text: "wls lr, r9, #0x7c0" + - + asm_text: "wls lr, r9, #0xeae" + - + asm_text: "wls lr, r9, #0xed4" + - + asm_text: "cinc lr, r2, lo" + - + asm_text: "cinc lr, r7, pl" + - + asm_text: "cinv lr, r12, hs" + - + asm_text: "cneg lr, r10, hs" + - + asm_text: "csel r9, r9, r11, vc" + - + asm_text: "cset lr, eq" + - + asm_text: "csetm lr, hs" + - + asm_text: "csinc lr, r10, r7, le" + - + asm_text: "csinv lr, r5, zr, hs" + - + asm_text: "cinv lr, r2, pl" + - + asm_text: "csel r0, r0, r1, eq" diff --git a/thirdparty/capstone/tests/MC/ARM/thumbv8m.s.yaml b/thirdparty/capstone/tests/MC/ARM/thumbv8m.s.yaml new file mode 100644 index 0000000..bbec48e --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/thumbv8m.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0xbf, 0xf3, 0x6f, 0x8f, 0x92, 0xfb, 0xf3, 0xf1, 0xb2, 0xfb, 0xf3, 0xf1, 0xbf, 0xf3, 0x2f, 0x8f, 0x52, 0xe8, 0x01, 0x1f, 0xd2, 0xe8, 0x4f, 0x1f, 0xd2, 0xe8, 0x5f, 0x1f, 0x43, 0xe8, 0x01, 0x21, 0xc3, 0xe8, 0x41, 0x2f, 0xc3, 0xe8, 0x51, 0x2f, 0x4f, 0xf6, 0xff, 0x71, 0xcf, 0xf6, 0xff, 0x71, 0xd2, 0xe8, 0xaf, 0x1f, 0xd2, 0xe8, 0x8f, 0x1f, 0xd2, 0xe8, 0x9f, 0x1f, 0xc3, 0xe8, 0xaf, 0x1f, 0xc3, 0xe8, 0x8f, 0x1f, 0xc3, 0xe8, 0x9f, 0x1f, 0xd2, 0xe8, 0xef, 0x1f, 0xd2, 0xe8, 0xcf, 0x1f, 0xd2, 0xe8, 0xdf, 0x1f, 0xc3, 0xe8, 0xe1, 0x2f, 0xc3, 0xe8, 0xc1, 0x2f, 0xc3, 0xe8, 0xd1, 0x2f, 0x7f, 0xe9, 0x7f, 0xe9, 0x04, 0x47, 0x74, 0x47, 0x84, 0x47, 0x41, 0xe8, 0x00, 0xf0, 0x4d, 0xe8, 0x00, 0xf0, 0x41, 0xe8, 0x80, 0xf0, 0x41, 0xe8, 0x40, 0xf0, 0x41, 0xe8, 0xc0, 0xf0, 0xef, 0xf3, 0x88, 0x81, 0x82, 0xf3, 0x89, 0x88, 0xef, 0xf3, 0x90, 0x83, 0x84, 0xf3, 0x94, 0x88, 0xef, 0xf3, 0x98, 0x85, 0xef, 0xf3, 0x0a, 0x86, 0xef, 0xf3, 0x0b, 0x87, 0x88, 0xf3, 0x0a, 0x88, 0x89, 0xf3, 0x0b, 0x88, 0xef, 0xf3, 0x8a, 0x8a, 0x8b, 0xf3, 0x8b, 0x88, 0xef, 0xf3, 0x92, 0x88, 0x88, 0xf3, 0x92, 0x80 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "isb sy" + - + asm_text: "sdiv r1, r2, r3" + - + asm_text: "udiv r1, r2, r3" + - + asm_text: "clrex" + - + asm_text: "ldrex r1, [r2, #4]" + - + asm_text: "ldrexb r1, [r2]" + - + asm_text: "ldrexh r1, [r2]" + - + asm_text: "strex r1, r2, [r3, #4]" + - + asm_text: "strexb r1, r2, [r3]" + - + asm_text: "strexh r1, r2, [r3]" + - + asm_text: "movw r1, #0xffff" + - + asm_text: "movt r1, #0xffff" + - + asm_text: "lda r1, [r2]" + - + asm_text: "ldab r1, [r2]" + - + asm_text: "ldah r1, [r2]" + - + asm_text: "stl r1, [r3]" + - + asm_text: "stlb r1, [r3]" + - + asm_text: "stlh r1, [r3]" + - + asm_text: "ldaex r1, [r2]" + - + asm_text: "ldaexb r1, [r2]" + - + asm_text: "ldaexh r1, [r2]" + - + asm_text: "stlex r1, r2, [r3]" + - + asm_text: "stlexb r1, r2, [r3]" + - + asm_text: "stlexh r1, r2, [r3]" + - + asm_text: "sg" + - + asm_text: "bxns r0" + - + asm_text: "bxns lr" + - + asm_text: "blxns r0" + - + asm_text: "tt r0, r1" + - + asm_text: "tt r0, sp" + - + asm_text: "tta r0, r1" + - + asm_text: "ttt r0, r1" + - + asm_text: "ttat r0, r1" + - + asm_text: "mrs r1, msp_ns" + - + asm_text: "msr psp_ns, r2" + - + asm_text: "mrs r3, primask_ns" + - + asm_text: "msr control_ns, r4" + - + asm_text: "mrs r5, sp_ns" + - + asm_text: "mrs r6, msplim" + - + asm_text: "mrs r7, psplim" + - + asm_text: "msr msplim, r8" + - + asm_text: "msr psplim, r9" + - + asm_text: "mrs r10, msplim_ns" + - + asm_text: "msr psplim_ns, r11" + - + asm_text: "mrs r8, 0x92" + - + asm_text: "msr 0x92, r8" diff --git a/thirdparty/capstone/tests/MC/ARM/udf-arm.s.yaml b/thirdparty/capstone/tests/MC/ARM/udf-arm.s.yaml new file mode 100644 index 0000000..2a4769d --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/udf-arm.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xf0, 0x00, 0xf0, 0xe7 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "udf #0" diff --git a/thirdparty/capstone/tests/MC/ARM/udf-thumb-2.s.yaml b/thirdparty/capstone/tests/MC/ARM/udf-thumb-2.s.yaml new file mode 100644 index 0000000..1ca8f42 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/udf-thumb-2.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xde, 0xf0, 0xf7, 0x00, 0xa0 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "udf #0" + - + asm_text: "udf.w #0" diff --git a/thirdparty/capstone/tests/MC/ARM/udf-thumb.s.yaml b/thirdparty/capstone/tests/MC/ARM/udf-thumb.s.yaml new file mode 100644 index 0000000..49b9943 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/udf-thumb.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xde ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "udf #0" diff --git a/thirdparty/capstone/tests/MC/ARM/vfp4-thumb.s.yaml b/thirdparty/capstone/tests/MC/ARM/vfp4-thumb.s.yaml new file mode 100644 index 0000000..498c32b --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/vfp4-thumb.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0xa2, 0xee, 0x00, 0x1a, 0x42, 0xef, 0xb1, 0x0c, 0x08, 0xef, 0x50, 0x4c, 0x92, 0xee, 0x40, 0x1a, 0xa2, 0xee, 0x40, 0x1a, 0x62, 0xef, 0xb1, 0x0c, 0x28, 0xef, 0x50, 0x4c, 0x92, 0xee, 0x00, 0x1a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vfma.f32 s2, s4, s0" + - + asm_text: "vfma.f32 d16, d18, d17" + - + asm_text: "vfma.f32 q2, q4, q0" + - + asm_text: "vfnma.f32 s2, s4, s0" + - + asm_text: "vfms.f32 s2, s4, s0" + - + asm_text: "vfms.f32 d16, d18, d17" + - + asm_text: "vfms.f32 q2, q4, q0" + - + asm_text: "vfnms.f32 s2, s4, s0" diff --git a/thirdparty/capstone/tests/MC/ARM/vfp4.s.yaml b/thirdparty/capstone/tests/MC/ARM/vfp4.s.yaml new file mode 100644 index 0000000..82700c7 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/vfp4.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x1a, 0xa2, 0xee, 0xb1, 0x0c, 0x42, 0xf2, 0x50, 0x4c, 0x08, 0xf2, 0x40, 0x1a, 0x92, 0xee, 0x40, 0x1a, 0xa2, 0xee, 0xb1, 0x0c, 0x62, 0xf2, 0x50, 0x4c, 0x28, 0xf2, 0x00, 0x1a, 0x92, 0xee ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vfma.f32 s2, s4, s0" + - + asm_text: "vfma.f32 d16, d18, d17" + - + asm_text: "vfma.f32 q2, q4, q0" + - + asm_text: "vfnma.f32 s2, s4, s0" + - + asm_text: "vfms.f32 s2, s4, s0" + - + asm_text: "vfms.f32 d16, d18, d17" + - + asm_text: "vfms.f32 q2, q4, q0" + - + asm_text: "vfnms.f32 s2, s4, s0" diff --git a/thirdparty/capstone/tests/MC/ARM/vmov-vmvn-replicate.s.yaml b/thirdparty/capstone/tests/MC/ARM/vmov-vmvn-replicate.s.yaml new file mode 100644 index 0000000..3a5b627 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/vmov-vmvn-replicate.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x3f, 0x2e, 0x87, 0xf3, 0x7f, 0x4e, 0x87, 0xf3, 0x1f, 0x2e, 0x87, 0xf3, 0x5f, 0x4e, 0x87, 0xf3, 0x1b, 0x2e, 0x82, 0xf3, 0x5b, 0x4e, 0x82, 0xf3, 0x1b, 0x2e, 0x82, 0xf3, 0x5b, 0x4e, 0x82, 0xf3, 0x5b, 0x4e, 0x82, 0xf3, 0x5b, 0x4e, 0x82, 0xf3, 0x3a, 0x2e, 0x82, 0xf3, 0x7a, 0x4e, 0x82, 0xf3, 0x15, 0x28, 0x82, 0xf3, 0x55, 0x48, 0x82, 0xf3, 0x15, 0x28, 0x82, 0xf3, 0x55, 0x48, 0x82, 0xf3, 0x15, 0x2a, 0x82, 0xf3, 0x55, 0x4a, 0x82, 0xf3, 0x15, 0x2a, 0x82, 0xf3, 0x55, 0x4a, 0x82, 0xf3, 0x15, 0x20, 0x82, 0xf3, 0x55, 0x40, 0x82, 0xf3, 0x15, 0x2d, 0x82, 0xf3, 0x55, 0x4d, 0x82, 0xf3, 0x10, 0x2e, 0x80, 0xf2, 0x50, 0x4e, 0x80, 0xf2, 0x10, 0x2e, 0x80, 0xf2, 0x50, 0x4e, 0x80, 0xf2, 0x14, 0x2e, 0x85, 0xf2, 0x54, 0x4e, 0x85, 0xf2, 0x14, 0x2e, 0x85, 0xf2, 0x54, 0x4e, 0x85, 0xf2, 0x14, 0x2e, 0x85, 0xf2, 0x54, 0x4e, 0x85, 0xf2, 0x35, 0x28, 0x82, 0xf3, 0x75, 0x48, 0x82, 0xf3, 0x35, 0x28, 0x82, 0xf3, 0x75, 0x48, 0x82, 0xf3, 0x35, 0x2a, 0x82, 0xf3, 0x75, 0x4a, 0x82, 0xf3, 0x35, 0x2a, 0x82, 0xf3, 0x75, 0x4a, 0x82, 0xf3, 0x35, 0x20, 0x82, 0xf3, 0x75, 0x40, 0x82, 0xf3, 0x35, 0x2d, 0x82, 0xf3, 0x75, 0x4d, 0x82, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmov.i64 d2, #0xffffffffffffffff" + - + asm_text: "vmov.i64 q2, #0xffffffffffffffff" + - + asm_text: "vmov.i8 d2, #0xff" + - + asm_text: "vmov.i8 q2, #0xff" + - + asm_text: "vmov.i8 d2, #0xab" + - + asm_text: "vmov.i8 q2, #0xab" + - + asm_text: "vmov.i8 d2, #0xab" + - + asm_text: "vmov.i8 q2, #0xab" + - + asm_text: "vmov.i8 q2, #0xab" + - + asm_text: "vmov.i8 q2, #0xab" + - + asm_text: "vmov.i64 d2, #0xff00ff00ff00ff00" + - + asm_text: "vmov.i64 q2, #0xff00ff00ff00ff00" + - + asm_text: "vmov.i16 d2, #0xa5" + - + asm_text: "vmov.i16 q2, #0xa5" + - + asm_text: "vmov.i16 d2, #0xa5" + - + asm_text: "vmov.i16 q2, #0xa5" + - + asm_text: "vmov.i16 d2, #0xa500" + - + asm_text: "vmov.i16 q2, #0xa500" + - + asm_text: "vmov.i16 d2, #0xa500" + - + asm_text: "vmov.i16 q2, #0xa500" + - + asm_text: "vmov.i32 d2, #0xa5" + - + asm_text: "vmov.i32 q2, #0xa5" + - + asm_text: "vmov.i32 d2, #0xa5ffff" + - + asm_text: "vmov.i32 q2, #0xa5ffff" + - + asm_text: "vmov.i8 d2, #0x0" + - + asm_text: "vmov.i8 q2, #0x0" + - + asm_text: "vmov.i8 d2, #0x0" + - + asm_text: "vmov.i8 q2, #0x0" + - + asm_text: "vmov.i8 d2, #0x54" + - + asm_text: "vmov.i8 q2, #0x54" + - + asm_text: "vmov.i8 d2, #0x54" + - + asm_text: "vmov.i8 q2, #0x54" + - + asm_text: "vmov.i8 d2, #0x54" + - + asm_text: "vmov.i8 q2, #0x54" + - + asm_text: "vmvn.i16 d2, #0xa5" + - + asm_text: "vmvn.i16 q2, #0xa5" + - + asm_text: "vmvn.i16 d2, #0xa5" + - + asm_text: "vmvn.i16 q2, #0xa5" + - + asm_text: "vmvn.i16 d2, #0xa500" + - + asm_text: "vmvn.i16 q2, #0xa500" + - + asm_text: "vmvn.i16 d2, #0xa500" + - + asm_text: "vmvn.i16 q2, #0xa500" + - + asm_text: "vmvn.i32 d2, #0xa5" + - + asm_text: "vmvn.i32 q2, #0xa5" + - + asm_text: "vmvn.i32 d2, #0xa5ffff" + - + asm_text: "vmvn.i32 q2, #0xa5ffff" diff --git a/thirdparty/capstone/tests/MC/ARM/vmovhr.s.yaml b/thirdparty/capstone/tests/MC/ARM/vmovhr.s.yaml new file mode 100644 index 0000000..d9997f6 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/vmovhr.s.yaml @@ -0,0 +1,16 @@ +test_cases: + - + input: + bytes: [ 0x16, 0xee, 0x90, 0x09, 0x0a, 0xee, 0x90, 0x19, 0x01, 0xee, 0x10, 0xd9, 0x12, 0xee, 0x90, 0xd9 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmov.f16 r0, s13" + - + asm_text: "vmov.f16 s21, r1" + - + asm_text: "vmov.f16 s2, sp" + - + asm_text: "vmov.f16 sp, s5" diff --git a/thirdparty/capstone/tests/MC/ARM/vpush-vpop-thumb.s.yaml b/thirdparty/capstone/tests/MC/ARM/vpush-vpop-thumb.s.yaml new file mode 100644 index 0000000..3aede96 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/vpush-vpop-thumb.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x2d, 0xed, 0x0a, 0x8b, 0x2d, 0xed, 0x05, 0x4a, 0xbd, 0xec, 0x0a, 0x8b, 0xbd, 0xec, 0x05, 0x4a, 0x2d, 0xed, 0x0a, 0x8b, 0x2d, 0xed, 0x05, 0x4a, 0xbd, 0xec, 0x0a, 0x8b, 0xbd, 0xec, 0x05, 0x4a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vpush {d8, d9, d10, d11, d12}" + - + asm_text: "vpush {s8, s9, s10, s11, s12}" + - + asm_text: "vpop {d8, d9, d10, d11, d12}" + - + asm_text: "vpop {s8, s9, s10, s11, s12}" + - + asm_text: "vpush {d8, d9, d10, d11, d12}" + - + asm_text: "vpush {s8, s9, s10, s11, s12}" + - + asm_text: "vpop {d8, d9, d10, d11, d12}" + - + asm_text: "vpop {s8, s9, s10, s11, s12}" diff --git a/thirdparty/capstone/tests/MC/ARM/vpush-vpop.s.yaml b/thirdparty/capstone/tests/MC/ARM/vpush-vpop.s.yaml new file mode 100644 index 0000000..4a6edad --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/vpush-vpop.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x0a, 0x8b, 0x2d, 0xed, 0x05, 0x4a, 0x2d, 0xed, 0x0a, 0x8b, 0xbd, 0xec, 0x05, 0x4a, 0xbd, 0xec, 0x0a, 0x8b, 0x2d, 0xed, 0x05, 0x4a, 0x2d, 0xed, 0x0a, 0x8b, 0xbd, 0xec, 0x05, 0x4a, 0xbd, 0xec ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vpush {d8, d9, d10, d11, d12}" + - + asm_text: "vpush {s8, s9, s10, s11, s12}" + - + asm_text: "vpop {d8, d9, d10, d11, d12}" + - + asm_text: "vpop {s8, s9, s10, s11, s12}" + - + asm_text: "vpush {d8, d9, d10, d11, d12}" + - + asm_text: "vpush {s8, s9, s10, s11, s12}" + - + asm_text: "vpop {d8, d9, d10, d11, d12}" + - + asm_text: "vpop {s8, s9, s10, s11, s12}" diff --git a/thirdparty/capstone/tests/MC/ARM/vscclrm-asm.s.yaml b/thirdparty/capstone/tests/MC/ARM/vscclrm-asm.s.yaml new file mode 100644 index 0000000..b416335 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/vscclrm-asm.s.yaml @@ -0,0 +1,26 @@ +test_cases: + - + input: + bytes: [ 0x9f, 0xec, 0x04, 0x0a, 0xdf, 0xec, 0x06, 0x1a, 0x9f, 0xec, 0x0c, 0x9a, 0xdf, 0xec, 0x01, 0xfa, 0x9f, 0xec, 0x04, 0x0b, 0x9f, 0xec, 0x08, 0x0b, 0x9f, 0xec, 0x06, 0x5b, 0x88, 0xbf, 0xdf, 0xec, 0x1d, 0x1a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vscclrm {s0, s1, s2, s3, vpr}" + - + asm_text: "vscclrm {s3, s4, s5, s6, s7, s8, vpr}" + - + asm_text: "vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}" + - + asm_text: "vscclrm {s31, vpr}" + - + asm_text: "vscclrm {d0, d1, vpr}" + - + asm_text: "vscclrm {d0, d1, d2, d3, vpr}" + - + asm_text: "vscclrm {d5, d6, d7, vpr}" + - + asm_text: "it hi" + - + asm_text: "vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}" diff --git a/thirdparty/capstone/tests/MC/ARM/vstrldr_sys.s.yaml b/thirdparty/capstone/tests/MC/ARM/vstrldr_sys.s.yaml new file mode 100644 index 0000000..9d0aff5 --- /dev/null +++ b/thirdparty/capstone/tests/MC/ARM/vstrldr_sys.s.yaml @@ -0,0 +1,102 @@ +test_cases: + - + input: + bytes: [ 0x80, 0xed, 0x80, 0x2f, 0x09, 0xed, 0x86, 0x4f, 0x29, 0xed, 0x86, 0x4f, 0x29, 0xec, 0x86, 0x4f, 0x88, 0xbf, 0x80, 0xed, 0x80, 0x2f, 0x90, 0xed, 0x80, 0x2f, 0x19, 0xed, 0x86, 0x4f, 0x39, 0xed, 0x86, 0x4f, 0x39, 0xec, 0x86, 0x4f, 0x3d, 0xec, 0x8d, 0x4f, 0x88, 0xbf, 0x90, 0xed, 0x80, 0x2f, 0xcc, 0xed, 0xff, 0xef, 0xec, 0xed, 0xff, 0xef, 0xec, 0xec, 0xff, 0xef, 0x6d, 0xec, 0x86, 0xef, 0xdc, 0xed, 0xff, 0xef, 0xfc, 0xed, 0xff, 0xef, 0xfc, 0xec, 0xff, 0xef, 0x7d, 0xec, 0x86, 0xef, 0xc0, 0xed, 0x80, 0xcf, 0x49, 0xed, 0x86, 0xcf, 0xc6, 0xed, 0xfd, 0xcf, 0x4e, 0xed, 0xff, 0xcf, 0xcc, 0xed, 0xff, 0xcf, 0x6d, 0xec, 0x86, 0xcf, 0xd0, 0xed, 0x80, 0xcf, 0x59, 0xed, 0x86, 0xcf, 0xd6, 0xed, 0xfd, 0xcf, 0x5e, 0xed, 0xff, 0xcf, 0xdc, 0xed, 0xff, 0xcf, 0x7d, 0xec, 0x86, 0xcf, 0xc6, 0xed, 0xfd, 0x8f, 0x4e, 0xed, 0xff, 0xaf, 0xe6, 0xed, 0xfd, 0x8f, 0x6e, 0xed, 0xff, 0xaf, 0xe6, 0xec, 0xfd, 0x8f, 0x6e, 0xec, 0xff, 0xaf, 0x6d, 0xec, 0x86, 0xaf, 0xd6, 0xed, 0xfd, 0x8f, 0x5e, 0xed, 0xff, 0xaf, 0xf6, 0xed, 0xfd, 0x8f, 0x7e, 0xed, 0xff, 0xaf, 0xf6, 0xec, 0xfd, 0x8f, 0x7e, 0xec, 0xff, 0xaf, 0x7d, 0xec, 0x86, 0xaf ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vstr fpscr, [r0]" + - + asm_text: "vstr fpscr_nzcvqc, [r9, #-0x18]" + - + asm_text: "vstr fpscr_nzcvqc, [r9, #-0x18]!" + - + asm_text: "vstr fpscr_nzcvqc, [r9], #-0x18" + - + asm_text: "it hi" + - + asm_text: "vstrhi fpscr, [r0]" + - + asm_text: "vldr fpscr, [r0]" + - + asm_text: "vldr fpscr_nzcvqc, [r9, #-0x18]" + - + asm_text: "vldr fpscr_nzcvqc, [r9, #-0x18]!" + - + asm_text: "vldr fpscr_nzcvqc, [r9], #-0x18" + - + asm_text: "vldr fpscr_nzcvqc, [sp], #-0x34" + - + asm_text: "it hi" + - + asm_text: "vldrhi fpscr, [r0]" + - + asm_text: "vstr fpcxts, [r12, #0x1fc]" + - + asm_text: "vstr fpcxts, [r12, #0x1fc]!" + - + asm_text: "vstr fpcxts, [r12], #0x1fc" + - + asm_text: "vstr fpcxts, [sp], #-0x18" + - + asm_text: "vldr fpcxts, [r12, #0x1fc]" + - + asm_text: "vldr fpcxts, [r12, #0x1fc]!" + - + asm_text: "vldr fpcxts, [r12], #0x1fc" + - + asm_text: "vldr fpcxts, [sp], #-0x18" + - + asm_text: "vstr fpcxtns, [r0]" + - + asm_text: "vstr fpcxtns, [r9, #-0x18]" + - + asm_text: "vstr fpcxtns, [r6, #0x1f4]" + - + asm_text: "vstr fpcxtns, [lr, #-0x1fc]" + - + asm_text: "vstr fpcxtns, [r12, #0x1fc]" + - + asm_text: "vstr fpcxtns, [sp], #-0x18" + - + asm_text: "vldr fpcxtns, [r0]" + - + asm_text: "vldr fpcxtns, [r9, #-0x18]" + - + asm_text: "vldr fpcxtns, [r6, #0x1f4]" + - + asm_text: "vldr fpcxtns, [lr, #-0x1fc]" + - + asm_text: "vldr fpcxtns, [r12, #0x1fc]" + - + asm_text: "vldr fpcxtns, [sp], #-0x18" + - + asm_text: "vstr vpr, [r6, #0x1f4]" + - + asm_text: "vstr p0, [lr, #-0x1fc]" + - + asm_text: "vstr vpr, [r6, #0x1f4]!" + - + asm_text: "vstr p0, [lr, #-0x1fc]!" + - + asm_text: "vstr vpr, [r6], #0x1f4" + - + asm_text: "vstr p0, [lr], #-0x1fc" + - + asm_text: "vstr p0, [sp], #-0x18" + - + asm_text: "vldr vpr, [r6, #0x1f4]" + - + asm_text: "vldr p0, [lr, #-0x1fc]" + - + asm_text: "vldr vpr, [r6, #0x1f4]!" + - + asm_text: "vldr p0, [lr, #-0x1fc]!" + - + asm_text: "vldr vpr, [r6], #0x1f4" + - + asm_text: "vldr p0, [lr], #-0x1fc" + - + asm_text: "vldr p0, [sp], #-0x18" diff --git a/thirdparty/capstone/tests/MC/X86/3DNow.s.yaml b/thirdparty/capstone/tests/MC/X86/3DNow.s.yaml new file mode 100644 index 0000000..1ca4563 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/3DNow.s.yaml @@ -0,0 +1,253 @@ +test_cases: + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xbf ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pavgusb %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0x5c, 0x16, 0x09, 0xbf ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pavgusb 9(%esi, %edx), %mm3" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pf2id %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0x5c, 0x16, 0x09, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pf2id 9(%esi, %edx), %mm3" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xae ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfacc %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x9e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfadd %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xb0 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfcmpeq %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x90 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfcmpge %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xa0 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfcmpgt %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xa4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfmax %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x94 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfmin %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xb4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfmul %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x96 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfrcp %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xa6 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfrcpit1 %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xb6 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfrcpit2 %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xa7 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfrsqit1 %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x97 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfrsqrt %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x9a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfsub %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xaa ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfsubr %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pi2fd %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xb7 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pmulhrw %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "femms" + - + input: + bytes: [ 0x0f, 0x0d, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "prefetch (%eax)" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pf2iw %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pi2fw %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x8a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfnacc %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x8e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfpnacc %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xbb ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pswapd %mm2, %mm1" diff --git a/thirdparty/capstone/tests/MC/X86/address-size.s.yaml b/thirdparty/capstone/tests/MC/X86/address-size.s.yaml new file mode 100644 index 0000000..cae1ba1 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/address-size.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x67, 0xc6, 0x06, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movb $0x0, (%esi)" + - + input: + bytes: [ 0xc6, 0x06, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movb $0x0, (%rsi)" + - + input: + bytes: [ 0x67, 0xc6, 0x06, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movb $0x0, (%esi)" + - + input: + bytes: [ 0xc6, 0x06, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movb $0x0, (%rsi)" diff --git a/thirdparty/capstone/tests/MC/X86/avx512-encodings.s.yaml b/thirdparty/capstone/tests/MC/X86/avx512-encodings.s.yaml new file mode 100644 index 0000000..e13d723 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/avx512-encodings.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x62, 0xa3, 0x55, 0x48, 0x38, 0xcd, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vinserti32x4 $1, %xmm21, %zmm5, %zmm17" + - + input: + bytes: [ 0x62, 0xe3, 0x1d, 0x40, 0x38, 0x4f, 0x10, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vinserti32x4 $1, 256(%rdi), %zmm28, %zmm17" + - + input: + bytes: [ 0x62, 0x33, 0x7d, 0x48, 0x39, 0xc9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextracti32x4 $1, %zmm9, %xmm17" + - + input: + bytes: [ 0x62, 0x33, 0xfd, 0x48, 0x3b, 0xc9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextracti64x4 $1, %zmm9, %ymm17" + - + input: + bytes: [ 0x62, 0x73, 0xfd, 0x48, 0x3b, 0x4f, 0x10, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextracti64x4 $1, %zmm9, 512(%rdi)" + - + input: + bytes: [ 0x62, 0xb1, 0x35, 0x40, 0x72, 0xe1, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad $2, %zmm17, %zmm25" + - + input: + bytes: [ 0x62, 0xf1, 0x35, 0x40, 0x72, 0x64, 0xb7, 0x08, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad $2, 512(%rdi, %rsi, 4), %zmm25" + - + input: + bytes: [ 0x62, 0x21, 0x1d, 0x48, 0xe2, 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad %xmm17, %zmm12, %zmm25" + - + input: + bytes: [ 0x62, 0x61, 0x1d, 0x48, 0xe2, 0x4c, 0xb7, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad 512(%rdi, %rsi, 4), %zmm12, %zmm25" + - + input: + bytes: [ 0x62, 0xf2, 0x7d, 0xc9, 0x58, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpbroadcastd %xmm0, %zmm1 {%k1} {z}" + - + input: + bytes: [ 0x62, 0xf1, 0xfe, 0x4b, 0x6f, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqu64 %zmm0, %zmm1 {%k3}" diff --git a/thirdparty/capstone/tests/MC/X86/intel-syntax-encoding.s.yaml b/thirdparty/capstone/tests/MC/X86/intel-syntax-encoding.s.yaml new file mode 100644 index 0000000..cd827fb --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/intel-syntax-encoding.s.yaml @@ -0,0 +1,262 @@ +test_cases: + - + input: + bytes: [ 0x66, 0x83, 0xf0, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "xor ax, 12" + - + input: + bytes: [ 0x83, 0xf0, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "xor eax, 12" + - + input: + bytes: [ 0x48, 0x83, 0xf0, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "xor rax, 12" + - + input: + bytes: [ 0x66, 0x83, 0xc8, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "or ax, 12" + - + input: + bytes: [ 0x83, 0xc8, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "or eax, 12" + - + input: + bytes: [ 0x48, 0x83, 0xc8, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "or rax, 12" + - + input: + bytes: [ 0x66, 0x83, 0xf8, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmp ax, 12" + - + input: + bytes: [ 0x83, 0xf8, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmp eax, 12" + - + input: + bytes: [ 0x48, 0x83, 0xf8, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmp rax, 12" + - + input: + bytes: [ 0x48, 0x89, 0x44, 0x24, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "mov qword ptr [rsp - 16], rax" + - + input: + bytes: [ 0x66, 0x83, 0xc0, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "add ax, -12" + - + input: + bytes: [ 0x83, 0xc0, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "add eax, -12" + - + input: + bytes: [ 0x48, 0x83, 0xc0, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "add rax, -12" + - + input: + bytes: [ 0x66, 0x83, 0xd0, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "adc ax, -12" + - + input: + bytes: [ 0x83, 0xd0, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "adc eax, -12" + - + input: + bytes: [ 0x48, 0x83, 0xd0, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "adc rax, -12" + - + input: + bytes: [ 0x66, 0x83, 0xd8, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sbb ax, -12" + - + input: + bytes: [ 0x83, 0xd8, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sbb eax, -12" + - + input: + bytes: [ 0x48, 0x83, 0xd8, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sbb rax, -12" + - + input: + bytes: [ 0x66, 0x83, 0xf8, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmp ax, -12" + - + input: + bytes: [ 0x83, 0xf8, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmp eax, -12" + - + input: + bytes: [ 0x48, 0x83, 0xf8, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmp rax, -12" + - + input: + bytes: [ 0xf2, 0x0f, 0x10, 0x2c, 0x25, 0xf8, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movsd xmm5, qword ptr [0xfffffffffffffff8]" + - + input: + bytes: [ 0xd1, 0xe7 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shl edi, 1" + - + input: + bytes: [ 0x0f, 0xc2, 0xd1, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmpltps xmm2, xmm1" + - + input: + bytes: [ 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0xcb ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "retf" + - + input: + bytes: [ 0xc2, 0x08, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "ret 8" + - + input: + bytes: [ 0xca, 0x08, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "retf 8" diff --git a/thirdparty/capstone/tests/MC/X86/x86-32-avx.s.yaml b/thirdparty/capstone/tests/MC/X86/x86-32-avx.s.yaml new file mode 100644 index 0000000..bcf43a1 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86-32-avx.s.yaml @@ -0,0 +1,7354 @@ +test_cases: + - + input: + bytes: [ 0xc5, 0xca, 0x58, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddss %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xca, 0x59, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulss %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xca, 0x5c, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubss %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xca, 0x5e, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivss %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xcb, 0x58, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xcb, 0x59, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulsd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xcb, 0x5c, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubsd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xcb, 0x5e, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivsd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xea, 0x58, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xea, 0x5c, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xea, 0x59, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xea, 0x5e, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x58, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x5c, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x59, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x5e, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xc8, 0x58, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddps %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc8, 0x5c, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubps %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc8, 0x59, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulps %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc8, 0x5e, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivps %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc9, 0x58, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddpd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc9, 0x5c, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubpd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc9, 0x59, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulpd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc9, 0x5e, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivpd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xe8, 0x58, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0x5c, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0x59, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0x5e, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x58, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x5c, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x59, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x5e, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xda, 0x5f, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxss %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xdb, 0x5f, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxsd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xda, 0x5d, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminss %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xdb, 0x5d, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminsd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xea, 0x5f, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxss -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x5f, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxsd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xea, 0x5d, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminss -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x5d, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminsd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xd8, 0x5f, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxps %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd9, 0x5f, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxpd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd8, 0x5d, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminps %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd9, 0x5d, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminpd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xe8, 0x5f, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x5f, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0x5d, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x5d, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xd8, 0x54, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandps %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd9, 0x54, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandpd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xe8, 0x54, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x54, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xd8, 0x56, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorps %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd9, 0x56, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorpd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xe8, 0x56, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x56, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xd8, 0x57, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorps %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd9, 0x57, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorpd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xe8, 0x57, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x57, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xd8, 0x55, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnps %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd9, 0x55, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnpd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xe8, 0x55, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x55, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xfa, 0x10, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovss -4(%ebx, %ecx, 8), %xmm5" + - + input: + bytes: [ 0xc5, 0xea, 0x10, 0xec ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovss %xmm4, %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xfb, 0x10, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovsd -4(%ebx, %ecx, 8), %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x10, 0xec ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovsd %xmm4, %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0x15, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhps %xmm1, %xmm2, %xmm4" + - + input: + bytes: [ 0xc5, 0xe9, 0x15, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhpd %xmm1, %xmm2, %xmm4" + - + input: + bytes: [ 0xc5, 0xe8, 0x14, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklps %xmm1, %xmm2, %xmm4" + - + input: + bytes: [ 0xc5, 0xe9, 0x14, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklpd %xmm1, %xmm2, %xmm4" + - + input: + bytes: [ 0xc5, 0xe8, 0x15, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x15, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0x14, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x14, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0xc8, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqps %xmm0, %xmm6, %xmm1" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0x08, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqps (%eax), %xmm6, %xmm1" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0xc8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordps %xmm0, %xmm6, %xmm1" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0xc8, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqpd %xmm0, %xmm6, %xmm1" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0x08, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqpd (%eax), %xmm6, %xmm1" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0xc8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordpd %xmm0, %xmm6, %xmm1" + - + input: + bytes: [ 0xc5, 0xe8, 0xc6, 0xd9, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufps $8, %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc6, 0x5c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufps $8, -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc6, 0xd9, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufpd $8, %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc6, 0x5c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufpd $8, -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpleps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnleps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpleps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnleps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordps -4(%ebx, %ecx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplepd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlepd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqpd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplepd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltpd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqpd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlepd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltpd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordpd -4(%ebx, %ecx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordpd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x50, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovmskps %xmm2, %eax" + - + input: + bytes: [ 0xc5, 0xf9, 0x50, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovmskpd %xmm2, %eax" + - + input: + bytes: [ 0xc5, 0xfc, 0x50, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovmskps %ymm2, %eax" + - + input: + bytes: [ 0xc5, 0xfd, 0x50, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovmskpd %ymm2, %eax" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpless %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnless %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqss -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpless -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltss -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqss -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnless -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltss -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordss -4(%ebx, %ecx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordss -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplesd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlesd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqsd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplesd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltsd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqsd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlesd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltsd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordsd -4(%ebx, %ecx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordsd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x2e, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vucomiss %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x2e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vucomiss (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x2f, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcomiss %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x2f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcomiss (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x2e, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vucomisd %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x2e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vucomisd (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x2f, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcomisd %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x2f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcomisd (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0x2c, 0xc1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttss2si %xmm1, %eax" + - + input: + bytes: [ 0xc5, 0xf2, 0x2a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsi2ssl (%eax), %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfb, 0x2c, 0xc1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttsd2si %xmm1, %eax" + - + input: + bytes: [ 0xc5, 0xfb, 0x2c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttsd2si (%ecx), %eax" + - + input: + bytes: [ 0xc5, 0xf3, 0x2a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%eax), %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x28, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovaps (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x28, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovaps %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x29, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovaps %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf9, 0x28, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovapd (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x28, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovapd %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x29, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovapd %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0x10, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovups (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x10, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovups %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x11, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovups %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf9, 0x10, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovupd (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x10, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovupd %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x11, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovupd %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0x13, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovlps %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xe8, 0x12, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovlps (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x13, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovlpd %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xe9, 0x12, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovlpd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x17, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovhps %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xe8, 0x16, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovhps (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x17, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovhpd %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xe9, 0x16, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovhpd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0x16, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovlhps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0x12, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovhlps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xfa, 0x2d, 0xc1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtss2si %xmm1, %eax" + - + input: + bytes: [ 0xc5, 0xfa, 0x2d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtss2si (%eax), %ebx" + - + input: + bytes: [ 0xc5, 0xfa, 0x2d, 0xc1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtss2si %xmm1, %eax" + - + input: + bytes: [ 0xc5, 0xfa, 0x2d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtss2si (%eax), %ebx" + - + input: + bytes: [ 0xc5, 0xf8, 0x5b, 0xf5 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2ps %xmm5, %xmm6" + - + input: + bytes: [ 0xc5, 0xf8, 0x5b, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2ps (%eax), %xmm6" + - + input: + bytes: [ 0xc5, 0xdb, 0x5a, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsd2ss %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xdb, 0x5a, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsd2ss (%eax), %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xf9, 0x5b, 0xda ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2dq %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x5b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2dq (%eax), %xmm3" + - + input: + bytes: [ 0xc5, 0xda, 0x5a, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtss2sd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xda, 0x5a, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtss2sd (%eax), %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xf8, 0x5b, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2ps %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xf8, 0x5b, 0x21 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2ps (%ecx), %xmm4" + - + input: + bytes: [ 0xc5, 0xfa, 0x5b, 0xda ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttps2dq %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xfa, 0x5b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttps2dq (%eax), %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x5a, 0xda ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2pd %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x5a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2pd (%eax), %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x5a, 0xda ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x51, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtpd %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x51, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtpd (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x51, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtps %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x51, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtps (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xeb, 0x51, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0x51, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtsd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0x51, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0x51, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtss (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x52, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrsqrtps %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x52, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrsqrtps (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xea, 0x52, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrsqrtss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0x52, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrsqrtss (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x53, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrcpps %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x53, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrcpps (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xea, 0x53, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrcpss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0x53, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrcpss (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0xe7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntdq %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf9, 0x2b, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntpd %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0x2b, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntps %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0xae, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vldmxcsr (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0xae, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vstmxcsr (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0xae, 0x15, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vldmxcsr 0xdeadbeef" + - + input: + bytes: [ 0xc5, 0xf8, 0xae, 0x1d, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vstmxcsr 0xdeadbeef" + - + input: + bytes: [ 0xc5, 0xe9, 0xf8, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf9, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf9, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfa, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfa, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfb, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe8, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubsb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubsb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe9, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe9, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd8, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubusb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubusb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd9, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubusw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd9, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubusw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfc, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfd, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfd, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfe, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfe, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd4, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd4, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xec, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddsb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xec, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddsb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xed, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xed, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdc, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddusb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddusb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdd, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddusw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdd, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddusw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe4, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulhuw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe4, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulhuw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe5, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulhw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe5, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulhw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd5, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmullw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd5, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmullw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf4, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmuludq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf4, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmuludq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe0, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpavgb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe0, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpavgb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe3, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpavgw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe3, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpavgw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xea, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xea, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xda, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminub %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xda, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminub (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xee, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xee, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xde, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxub %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xde, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxub (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf6, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsadbw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsadbw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf1, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsllw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf1, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsllw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf2, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpslld %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf2, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpslld (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf3, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsllq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf3, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsllq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe1, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsraw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe1, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsraw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe2, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrad %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe2, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrad (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd1, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrlw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd1, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrlw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd2, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrld %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd2, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrld (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd3, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrlq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd3, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrlq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x72, 0xf2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpslld $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x73, 0xfa, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpslldq $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x73, 0xf2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsllq $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x71, 0xf2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsllw $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x72, 0xe2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrad $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x71, 0xe2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsraw $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x72, 0xd2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrld $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x73, 0xda, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrldq $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x73, 0xd2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrlq $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x71, 0xd2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrlw $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x72, 0xf2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpslld $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdb, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpand %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpand (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xeb, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpor %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpor (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xef, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpxor %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xef, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpxor (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdf, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpandn %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdf, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpandn (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x74, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x74, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x75, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x75, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x76, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x76, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x64, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x64, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x65, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x65, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x66, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x66, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x63, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpacksswb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x63, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpacksswb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6b, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpackssdw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpackssdw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x67, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpackuswb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x67, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpackuswb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x70, 0xda, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshufd $4, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x70, 0x18, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshufd $4, (%eax), %xmm3" + - + input: + bytes: [ 0xc5, 0xfa, 0x70, 0xda, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshufhw $4, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xfa, 0x70, 0x18, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshufhw $4, (%eax), %xmm3" + - + input: + bytes: [ 0xc5, 0xfb, 0x70, 0xda, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshuflw $4, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xfb, 0x70, 0x18, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshuflw $4, (%eax), %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x60, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpcklbw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x60, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpcklbw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x61, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpcklwd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x61, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpcklwd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x62, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckldq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x62, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckldq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6c, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpcklqdq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpcklqdq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x68, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhbw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x68, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhbw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x69, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhwd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x69, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhwd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6a, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhdq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhdq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6d, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhqdq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhqdq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc4, 0xd8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrw $7, %eax, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc4, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrw $7, (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0xc5, 0xc2, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrw $7, %xmm2, %eax" + - + input: + bytes: [ 0xc5, 0xf9, 0xd7, 0xc1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovmskb %xmm1, %eax" + - + input: + bytes: [ 0xc5, 0xf9, 0xf7, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovdqu %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x7e, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovd %xmm1, %eax" + - + input: + bytes: [ 0xc5, 0xf9, 0x7e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovd %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf9, 0x6e, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovd %eax, %xmm1" + - + input: + bytes: [ 0xc5, 0xf9, 0x6e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovd (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xf9, 0xd6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovq %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xfa, 0x7e, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovq %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0x7e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovq (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xfb, 0xe6, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0xe6, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2pd %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0xe6, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2pd (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0x16, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovshdup %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0x16, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovshdup (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0x12, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovsldup %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0x12, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovsldup (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xfb, 0x12, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovddup %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfb, 0x12, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovddup (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xeb, 0xd0, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf3, 0xd0, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubps (%eax), %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xe9, 0xd0, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf1, 0xd0, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubpd (%eax), %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xeb, 0x7c, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0x7c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddps (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x7c, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x7c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddpd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0x7d, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0x7d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubps (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x7d, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x7d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubpd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x1c, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpabsb %xmm1, %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x1c, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpabsb (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x1d, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpabsw %xmm1, %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x1d, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpabsw (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x1e, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpabsd %xmm1, %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x1e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpabsd (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x01, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphaddw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x01, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphaddw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x02, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphaddd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x02, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphaddd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x03, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphaddsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x03, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphaddsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x05, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphsubw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x05, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphsubw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x06, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphsubd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x06, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphsubd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x07, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphsubsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x07, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphsubsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x04, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaddubsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x04, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaddubsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x00, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshufb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x00, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshufb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x08, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsignb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x08, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsignb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x09, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsignw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x09, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsignw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x0a, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsignd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x0a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsignd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x0b, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulhrsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x0b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulhrsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x0f, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpalignr $7, %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x0f, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpalignr $7, (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x0b, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundsd $7, %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x0b, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundsd $7, (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x0a, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundss $7, %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x0a, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundss $7, (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x09, 0xda, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundpd $7, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x09, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundpd $7, (%eax), %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x08, 0xda, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundps $7, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x08, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundps $7, (%eax), %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x41, 0xda ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphminposuw %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x41, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphminposuw (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x2b, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpackusdw %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x2b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpackusdw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x29, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqq %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x29, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x38, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminsb %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x38, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminsb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x39, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminsd %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x39, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminsd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x3b, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminud %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x3b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminud (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x3a, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminuw %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x3a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminuw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x3c, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxsb %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x3c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxsb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x3d, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxsd %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x3d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxsd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x3f, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxud %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x3f, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxud (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x3e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxuw %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x3e, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxuw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x28, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmuldq %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x28, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmuldq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x40, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulld %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x40, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulld (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x0c, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendps $3, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x0c, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendps $3, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x0d, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendpd $3, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x0d, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendpd $3, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x0e, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpblendw $3, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x0e, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpblendw $3, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x42, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmpsadbw $3, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x42, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmpsadbw $3, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x40, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdpps $3, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x40, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdpps $3, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x41, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdppd $3, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x41, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdppd $3, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x4b, 0xdd, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendvpd %xmm2, %xmm5, %xmm1, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x4b, 0x18, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendvpd %xmm2, (%eax), %xmm1, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x4a, 0xdd, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendvps %xmm2, %xmm5, %xmm1, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x4a, 0x18, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendvps %xmm2, (%eax), %xmm1, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x4c, 0xdd, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpblendvb %xmm2, %xmm5, %xmm1, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x4c, 0x18, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpblendvb %xmm2, (%eax), %xmm1, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x20, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxbw %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x20, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxbw (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x23, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxwd %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x23, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxwd (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x25, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxdq %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x25, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxdq (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x30, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxbw %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x30, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxbw (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x33, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxwd %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x33, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxwd (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x35, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxdq %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x35, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxdq (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x22, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxbq %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x22, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxbq (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x32, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxbq %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x32, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxbq (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x21, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxbd %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x21, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxbd (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x24, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxwq %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x24, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxwq (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x31, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxbd %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x31, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxbd (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x34, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxwq %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x34, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxwq (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0xc5, 0xc2, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrw $7, %xmm2, %eax" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x15, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrw $7, %xmm2, (%eax)" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x16, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrd $7, %xmm2, %eax" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x16, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrd $7, %xmm2, (%eax)" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x14, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrb $7, %xmm2, %eax" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x14, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrb $7, %xmm2, (%eax)" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x17, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vextractps $7, %xmm2, (%eax)" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x17, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vextractps $7, %xmm2, %eax" + - + input: + bytes: [ 0xc5, 0xe9, 0xc4, 0xe8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrw $7, %eax, %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0xc4, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrw $7, (%eax), %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x20, 0xe8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrb $7, %eax, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x20, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrb $7, (%eax), %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x22, 0xe8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrd $7, %eax, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x22, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrd $7, (%eax), %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x21, 0xca, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vinsertps $7, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x21, 0x08, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vinsertps $7, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x17, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vptest %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x17, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vptest (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x2a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntdqa (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x37, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtq %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x37, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtq (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x62, 0xea, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpistrm $7, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x62, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpistrm $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x60, 0xea, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpestrm $7, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x60, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpestrm $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x63, 0xea, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpistri $7, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x63, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpistri $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x61, 0xea, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpestri $7, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x61, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpestri $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0xdb, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesimc %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0xdb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesimc (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xdc, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesenc %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xdc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesenc (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xdd, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesenclast %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xdd, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesenclast (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xde, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesdec %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xde, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesdec (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xdf, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesdeclast %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xdf, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesdeclast (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0xdf, 0xea, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaeskeygenassist $7, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0xdf, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaeskeygenassist $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeq_uqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpngeps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpngtps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpfalseps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneq_oqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpgeps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpgtps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmptrueps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeq_osps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplt_oqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmple_oqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunord_sps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneq_usps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnle_uqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpord_sps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeq_usps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnge_uqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpngt_uqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpfalse_osps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneq_osps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpge_oqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpgt_oqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmptrue_usps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xfc, 0x28, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovaps (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x28, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovaps %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x29, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovaps %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xfd, 0x28, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovapd (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x28, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovapd %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x29, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovapd %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xfc, 0x10, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovups (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x10, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovups %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x11, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovups %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xfd, 0x10, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovupd (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x10, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovupd %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x11, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovupd %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xec, 0x15, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhps %ymm1, %ymm2, %ymm4" + - + input: + bytes: [ 0xc5, 0xed, 0x15, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhpd %ymm1, %ymm2, %ymm4" + - + input: + bytes: [ 0xc5, 0xec, 0x14, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklps %ymm1, %ymm2, %ymm4" + - + input: + bytes: [ 0xc5, 0xed, 0x14, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklpd %ymm1, %ymm2, %ymm4" + - + input: + bytes: [ 0xc5, 0xec, 0x15, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhps -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xed, 0x15, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhpd -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xec, 0x14, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklps -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xed, 0x14, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklpd -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfd, 0xe7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntdq %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xfd, 0x2b, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntpd %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xfc, 0x2b, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntps %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0x50, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovmskps %xmm2, %eax" + - + input: + bytes: [ 0xc5, 0xf9, 0x50, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovmskpd %xmm2, %eax" + - + input: + bytes: [ 0xc5, 0xdc, 0x5f, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5f, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5d, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5d, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5c, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5c, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5e, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5e, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x58, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x58, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x59, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x59, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5f, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxps (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5f, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxpd (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5d, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminps (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5d, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminpd (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5c, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubps (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5c, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubpd (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivps (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivpd (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x58, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddps (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x58, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddpd (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x59, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulps (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x59, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulpd (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xfd, 0x51, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtpd %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x51, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtpd (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x51, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtps %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x51, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtps (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x52, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrsqrtps %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x52, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrsqrtps (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x53, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrcpps %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x53, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrcpps (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xdc, 0x54, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x54, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xec, 0x54, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandps -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xed, 0x54, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandpd -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xdc, 0x56, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x56, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xec, 0x56, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorps -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xed, 0x56, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorpd -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xdc, 0x57, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x57, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xec, 0x57, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorps -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xed, 0x57, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorpd -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xdc, 0x55, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x55, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xec, 0x55, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnps -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xed, 0x55, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnpd -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfc, 0x5a, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2pd %xmm3, %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x5a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2pd (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfe, 0xe6, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2pd %xmm3, %ymm2" + - + input: + bytes: [ 0xc5, 0xfe, 0xe6, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2pd (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x5b, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2ps %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfc, 0x5b, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2ps (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x5b, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2dq %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfd, 0x5b, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2dq (%eax), %ymm5" + - + input: + bytes: [ 0xc5, 0xfe, 0x5b, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttps2dq %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfe, 0x5b, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttps2dq (%eax), %ymm5" + - + input: + bytes: [ 0xc5, 0xf9, 0xe6, 0xe9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %xmm1, %xmm5" + - + input: + bytes: [ 0xc5, 0xfd, 0xe6, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %ymm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xf9, 0xe6, 0xe9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %xmm1, %xmm5" + - + input: + bytes: [ 0xc5, 0xf9, 0xe6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttpd2dqx (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xfd, 0xe6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %ymm2, %xmm1" + - + input: + bytes: [ 0xc5, 0xfd, 0xe6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttpd2dqy (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xfd, 0x5a, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %ymm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xf9, 0x5a, 0xe9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %xmm1, %xmm5" + - + input: + bytes: [ 0xc5, 0xf9, 0x5a, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2psx (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xfd, 0x5a, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %ymm2, %xmm1" + - + input: + bytes: [ 0xc5, 0xfd, 0x5a, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2psy (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xff, 0xe6, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %ymm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xff, 0xe6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %ymm2, %xmm1" + - + input: + bytes: [ 0xc5, 0xff, 0xe6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2dqy (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xfb, 0xe6, 0xe9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %xmm1, %xmm5" + - + input: + bytes: [ 0xc5, 0xfb, 0xe6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2dqx (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpleps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnleps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpleps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnleps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xcc, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordps -4(%ebx, %ecx, 8), %ymm6, %ymm2" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplepd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlepd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqpd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplepd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltpd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqpd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlepd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltpd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xcd, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordpd -4(%ebx, %ecx, 8), %ymm6, %ymm2" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordpd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeq_uqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpngeps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpngtps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpfalseps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneq_oqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpgeps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpgtps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmptrueps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeq_osps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplt_oqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmple_oqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunord_sps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneq_usps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnle_uqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpord_sps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeq_usps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnge_uqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpngt_uqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpfalse_osps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneq_osps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpge_oqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpgt_oqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmptrue_usps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xef, 0xd0, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xf7, 0xd0, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubps (%eax), %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xed, 0xd0, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xf5, 0xd0, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubpd (%eax), %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xef, 0x7c, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xef, 0x7c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddps (%eax), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0x7c, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0x7c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddpd (%eax), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xef, 0x7d, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xef, 0x7d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubps (%eax), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0x7d, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0x7d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubpd (%eax), %ymm2, %ymm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x0c, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendps $3, %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x0c, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendps $3, (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x0d, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendpd $3, %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x0d, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendpd $3, (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x40, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdpps $3, %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x40, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdpps $3, (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x1a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vbroadcastf128 (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x19, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vbroadcastsd (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x18, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vbroadcastss (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x18, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vbroadcastss (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe3, 0x6d, 0x18, 0xea, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vinsertf128 $7, %xmm2, %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x6d, 0x18, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vinsertf128 $7, (%eax), %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x19, 0xd2, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vextractf128 $7, %ymm2, %xmm2" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x19, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vextractf128 $7, %ymm2, (%eax)" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x2f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovpd %xmm2, %xmm5, (%eax)" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x2f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovpd %ymm2, %ymm5, (%eax)" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x2d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovpd (%eax), %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x6d, 0x2d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovpd (%eax), %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x2e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovps %xmm2, %xmm5, (%eax)" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x2e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovps %ymm2, %ymm5, (%eax)" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x2c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovps (%eax), %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x6d, 0x2c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovps (%eax), %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x04, 0xe9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps $7, %xmm1, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x04, 0xcd, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps $7, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x04, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x04, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps $7, (%eax), %ymm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x0c, 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps %xmm1, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x0c, 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps %ymm1, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x0c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x0c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x05, 0xe9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd $7, %xmm1, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x05, 0xcd, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd $7, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x05, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x05, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd $7, (%eax), %ymm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x0d, 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd %xmm1, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x0d, 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd %ymm1, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x0d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x0d, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x06, 0xca, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vperm2f128 $7, %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x06, 0x08, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vperm2f128 $7, (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc5, 0xfc, 0x77 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vzeroall" + - + input: + bytes: [ 0xc5, 0xf8, 0x77 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vzeroupper" + - + input: + bytes: [ 0xc5, 0xfb, 0x2d, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsd2si %xmm4, %ecx" + - + input: + bytes: [ 0xc5, 0xfb, 0x2d, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsd2si (%ecx), %ecx" + - + input: + bytes: [ 0xc5, 0xfb, 0x2d, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsd2si %xmm4, %ecx" + - + input: + bytes: [ 0xc5, 0xfb, 0x2d, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsd2si (%ecx), %ecx" + - + input: + bytes: [ 0xc5, 0xfb, 0x2a, 0x7d, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%ebp), %xmm0, %xmm7" + - + input: + bytes: [ 0xc5, 0xfb, 0x2a, 0x3c, 0x24 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%esp), %xmm0, %xmm7" + - + input: + bytes: [ 0xc5, 0xfb, 0x2a, 0x7d, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%ebp), %xmm0, %xmm7" + - + input: + bytes: [ 0xc5, 0xfb, 0x2a, 0x3c, 0x24 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%esp), %xmm0, %xmm7" + - + input: + bytes: [ 0xc5, 0xff, 0xf0, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vlddqu (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xff, 0x12, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovddup %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xff, 0x12, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovddup (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x6f, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovdqa %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfd, 0x7f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovdqa %ymm2, (%eax)" + - + input: + bytes: [ 0xc5, 0xfd, 0x6f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovdqa (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfe, 0x6f, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovdqu %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfe, 0x7f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovdqu %ymm2, (%eax)" + - + input: + bytes: [ 0xc5, 0xfe, 0x6f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovdqu (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfe, 0x16, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovshdup %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfe, 0x16, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovshdup (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfe, 0x12, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovsldup %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfe, 0x12, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovsldup (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x17, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vptest %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x17, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vptest (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x09, 0xcd, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundpd $7, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x09, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundpd $7, (%eax), %ymm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x08, 0xcd, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundps $7, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x08, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundps $7, (%eax), %ymm5" + - + input: + bytes: [ 0xc5, 0xd5, 0xc6, 0xca, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufpd $7, %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc5, 0xd5, 0xc6, 0x08, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufpd $7, (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc5, 0xd4, 0xc6, 0xca, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufps $7, %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc5, 0xd4, 0xc6, 0x08, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufps $7, (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x0f, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestpd %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x0f, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestpd %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x0f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestpd (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x0f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestpd (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x0e, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestps %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x0e, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestps %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x0e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestps (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x0e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestps (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe3, 0x75, 0x4b, 0x94, 0x20, 0xad, 0xde, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendvpd %ymm0, 0xdead(%eax), %ymm1, %ymm2" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x44, 0xca, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpclmulqdq $17, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x44, 0x18, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpclmulqdq $17, (%eax), %xmm5, %xmm3" diff --git a/thirdparty/capstone/tests/MC/X86/x86-32-fma3.s.yaml b/thirdparty/capstone/tests/MC/X86/x86-32-fma3.s.yaml new file mode 100644 index 0000000..52f78ef --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86-32-fma3.s.yaml @@ -0,0 +1,1504 @@ +test_cases: + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x96, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x96, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x96, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x96, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x97, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x97, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x97, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x97, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x9a, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x9a, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x9a, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x9a, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xaa, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xaa, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xaa, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xaa, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xba, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xba, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xba, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xba, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x9c, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x9c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x9c, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x9c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xac, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xac, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xac, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xac, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xbc, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xbc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xbc, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xbc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x9e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x9e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x9e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x9e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xae, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xae, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xae, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xae, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xbe, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xbe, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xbe, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xbe, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x96, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x96, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x96, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x96, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x97, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x97, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x97, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x97, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x9a, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x9a, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x9a, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x9a, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xaa, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xaa, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xaa, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xaa, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xba, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xba, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xba, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xba, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x9c, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x9c, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x9c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xac, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xac, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xac, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xac, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xbc, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xbc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xbc, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xbc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x9e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x9e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x9e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x9e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xae, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xae, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xae, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xae, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xbe, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xbe, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xbe, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xbe, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231ps (%eax), %ymm5, %ymm1" diff --git a/thirdparty/capstone/tests/MC/X86/x86-32-ms-inline-asm.s.yaml b/thirdparty/capstone/tests/MC/X86/x86-32-ms-inline-asm.s.yaml new file mode 100644 index 0000000..c4a35a5 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86-32-ms-inline-asm.s.yaml @@ -0,0 +1,235 @@ +test_cases: + - + input: + bytes: [ 0x8b, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl (%ebx), %eax" + - + input: + bytes: [ 0x89, 0x4b, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl %ecx, 4(%ebx)" + - + input: + bytes: [ 0x8b, 0x04, 0x85, 0x04, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(, %eax, 4), %eax" + - + input: + bytes: [ 0x8b, 0x04, 0x85, 0x04, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(, %eax, 4), %eax" + - + input: + bytes: [ 0x8b, 0x04, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl (%esi, %eax), %eax" + - + input: + bytes: [ 0x8b, 0x04, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl (%esi, %eax), %eax" + - + input: + bytes: [ 0x8b, 0x04, 0x86 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl (%esi, %eax, 4), %eax" + - + input: + bytes: [ 0x8b, 0x04, 0x86 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl (%esi, %eax, 4), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x06, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x06, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x06, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x06, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 8(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 8(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 8(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 8(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 16(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x0f, 0x18, 0x40, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "prefetchnta 64(%eax)" + - + input: + bytes: [ 0x60 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pushal" + - + input: + bytes: [ 0x61 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "popal" + - + input: + bytes: [ 0x60 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pushal" + - + input: + bytes: [ 0x61 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "popal" diff --git a/thirdparty/capstone/tests/MC/X86/x86_64-avx-clmul-encoding.s.yaml b/thirdparty/capstone/tests/MC/X86/x86_64-avx-clmul-encoding.s.yaml new file mode 100644 index 0000000..c8ca1c4 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86_64-avx-clmul-encoding.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xc4, 0x43, 0x29, 0x44, 0xdc, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpclmulqdq $17, %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x29, 0x44, 0x28, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpclmulqdq $17, (%rax), %xmm10, %xmm13" diff --git a/thirdparty/capstone/tests/MC/X86/x86_64-avx-encoding.s.yaml b/thirdparty/capstone/tests/MC/X86/x86_64-avx-encoding.s.yaml new file mode 100644 index 0000000..50c2e4f --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86_64-avx-encoding.s.yaml @@ -0,0 +1,9514 @@ +test_cases: + - + input: + bytes: [ 0xc4, 0x41, 0x32, 0x58, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddss %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x32, 0x59, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulss %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x32, 0x5c, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubss %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x32, 0x5e, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivss %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x33, 0x58, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsd %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x33, 0x59, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulsd %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x33, 0x5c, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubsd %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x33, 0x5e, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivsd %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc5, 0x2a, 0x58, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddss -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2a, 0x5c, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubss -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2a, 0x59, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulss -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2a, 0x5e, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivss -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2b, 0x58, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2b, 0x5c, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubsd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2b, 0x59, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulsd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2b, 0x5e, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivsd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x20, 0x58, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddps %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x20, 0x5c, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubps %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x20, 0x59, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulps %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x20, 0x5e, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivps %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x21, 0x58, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddpd %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x21, 0x5c, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubpd %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x21, 0x59, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulpd %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x21, 0x5e, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivpd %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc5, 0x28, 0x58, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddps -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x28, 0x5c, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubps -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x28, 0x59, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulps -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x28, 0x5e, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivps -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x29, 0x58, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddpd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x29, 0x5c, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubpd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x29, 0x59, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulpd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x29, 0x5e, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivpd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x0a, 0x5f, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxss %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x0b, 0x5f, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxsd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x0a, 0x5d, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminss %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x0b, 0x5d, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminsd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x1a, 0x5f, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxss -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1b, 0x5f, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxsd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1a, 0x5d, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminss -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1b, 0x5d, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminsd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x08, 0x5f, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxps %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x09, 0x5f, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxpd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x08, 0x5d, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminps %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x09, 0x5d, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminpd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x18, 0x5f, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxps -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0x5f, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxpd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x18, 0x5d, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminps -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0x5d, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminpd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x08, 0x54, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandps %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x09, 0x54, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandpd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x18, 0x54, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandps -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0x54, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandpd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x08, 0x56, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorps %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x09, 0x56, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorpd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x18, 0x56, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorps -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0x56, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorpd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x08, 0x57, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorps %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x09, 0x57, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorpd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x18, 0x57, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorps -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0x57, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorpd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x08, 0x55, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnps %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x09, 0x55, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnpd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x18, 0x55, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnps -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0x55, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnpd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x7a, 0x10, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovss -4(%rbx, %rcx, 8), %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x2a, 0x10, 0xfe ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovss %xmm14, %xmm10, %xmm15" + - + input: + bytes: [ 0xc5, 0x7b, 0x10, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsd -4(%rbx, %rcx, 8), %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x2b, 0x10, 0xfe ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsd %xmm14, %xmm10, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0x15, 0xef ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhps %xmm15, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x15, 0xef ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhpd %xmm15, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0x14, 0xef ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklps %xmm15, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x14, 0xef ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklpd %xmm15, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0x15, 0x7c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhps -4(%rbx, %rcx, 8), %xmm12, %xmm15" + - + input: + bytes: [ 0xc5, 0x19, 0x15, 0x7c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhpd -4(%rbx, %rcx, 8), %xmm12, %xmm15" + - + input: + bytes: [ 0xc5, 0x18, 0x14, 0x7c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklps -4(%rbx, %rcx, 8), %xmm12, %xmm15" + - + input: + bytes: [ 0xc5, 0x19, 0x14, 0x7c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklpd -4(%rbx, %rcx, 8), %xmm12, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xfa, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqps %xmm10, %xmm12, %xmm15" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x38, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqps (%rax), %xmm12, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xfa, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordps %xmm10, %xmm12, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xfa, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqpd %xmm10, %xmm12, %xmm15" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x38, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqpd (%rax), %xmm12, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xfa, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordpd %xmm10, %xmm12, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc6, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufps $8, %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc6, 0x6c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufps $8, -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc6, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufpd $8, %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc6, 0x6c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufpd $8, -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpleps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnleps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpleps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnleps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordps -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplepd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlepd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplepd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlepd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordpd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpless %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnless %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpless -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnless -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordss -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplesd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlesd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplesd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlesd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordsd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngeps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalseps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgeps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrueps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_osps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_sps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_usps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_sps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_usps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_osps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_osps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_usps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngeps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalseps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgeps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtps -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrueps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_sps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqps -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_sps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqps -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngepd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalsepd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgepd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptruepd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_ospd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_spd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_uspd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_spd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uspd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_ospd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_ospd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_uspd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngepd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalsepd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgepd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtpd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptruepd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_spd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqpd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_spd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqpd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngess %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalsess %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgess %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptruess %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_osss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_sss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_usss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_sss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_usss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_osss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_osss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_usss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngess -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalsess -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgess -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtss -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptruess -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_sss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqss -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_sss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqss -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngesd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalsesd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgesd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptruesd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_ossd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_ssd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_ussd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_ssd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_ussd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_ossd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_ossd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_ussd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngesd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalsesd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgesd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtsd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptruesd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_ssd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqsd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_ssd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqsd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x2e, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vucomiss %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x2e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vucomiss (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x2f, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcomiss %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x2f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcomiss (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x2e, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vucomisd %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x79, 0x2e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vucomisd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x2f, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcomisd %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x79, 0x2f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcomisd (%rax), %xmm12" + - + input: + bytes: [ 0xc5, 0xfa, 0x2c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttss2si (%rcx), %eax" + - + input: + bytes: [ 0xc5, 0x22, 0x2a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2ssl (%rax), %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x22, 0x2a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2ssl (%rax), %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0xfb, 0x2c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttsd2si (%rcx), %eax" + - + input: + bytes: [ 0xc5, 0x23, 0x2a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%rax), %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x23, 0x2a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%rax), %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x28, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x28, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x29, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x79, 0x28, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovapd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x28, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovapd %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x79, 0x29, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovapd %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x78, 0x10, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x10, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x11, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x79, 0x10, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovupd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x10, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovupd %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x79, 0x11, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovupd %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x78, 0x13, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovlps %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x18, 0x12, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovlps (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x79, 0x13, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovlpd %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x19, 0x12, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovlpd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x78, 0x17, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovhps %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x18, 0x16, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovhps (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x79, 0x17, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovhpd %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x19, 0x16, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovhpd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0x16, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovlhps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0x12, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovhlps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x7a, 0x2d, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtss2si %xmm11, %eax" + - + input: + bytes: [ 0xc5, 0xfa, 0x2d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtss2si (%rax), %ebx" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x5b, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2ps %xmm10, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x5b, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2ps (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x13, 0x5a, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsd2ss %xmm12, %xmm13, %xmm10" + - + input: + bytes: [ 0xc5, 0x13, 0x5a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsd2ss (%rax), %xmm13, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x5b, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2dq %xmm12, %xmm11" + - + input: + bytes: [ 0xc5, 0x79, 0x5b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2dq (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x12, 0x5a, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtss2sd %xmm12, %xmm13, %xmm10" + - + input: + bytes: [ 0xc5, 0x12, 0x5a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtss2sd (%rax), %xmm13, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x5b, 0xd5 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2ps %xmm13, %xmm10" + - + input: + bytes: [ 0xc5, 0x78, 0x5b, 0x29 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2ps (%rcx), %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x7a, 0x5b, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttps2dq %xmm12, %xmm11" + - + input: + bytes: [ 0xc5, 0x7a, 0x5b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttps2dq (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x5a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2pd %xmm12, %xmm11" + - + input: + bytes: [ 0xc5, 0x78, 0x5a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2pd (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x5a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %xmm12, %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x51, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtpd %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x79, 0x51, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtpd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x51, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtps %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x51, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtps (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0x51, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtsd %xmm11, %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1b, 0x51, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtsd (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0x51, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtss %xmm11, %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1a, 0x51, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtss (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x52, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrsqrtps %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x52, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrsqrtps (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0x52, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrsqrtss %xmm11, %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1a, 0x52, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrsqrtss (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x53, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrcpps %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x53, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrcpps (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0x53, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrcpss %xmm11, %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1a, 0x53, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrcpss (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x79, 0xe7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntdq %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x79, 0x2b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntpd %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x78, 0x2b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntps %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0xf8, 0xae, 0x15, 0xfc, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vldmxcsr -4(%rip)" + - + input: + bytes: [ 0xc5, 0xf8, 0xae, 0x5c, 0x24, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vstmxcsr -4(%rsp)" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf8, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf8, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf9, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf9, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xfa, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xfa, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xfb, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xfb, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe8, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubsb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe8, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubsb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe9, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe9, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd8, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubusb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd8, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubusb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd9, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubusw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd9, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubusw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xfc, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xfc, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xfd, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xfd, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xfe, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xfe, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd4, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd4, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xec, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddsb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xec, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddsb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xed, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xed, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xdc, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddusb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xdc, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddusb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xdd, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddusw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xdd, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddusw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe4, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulhuw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe4, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulhuw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe5, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulhw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe5, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulhw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd5, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmullw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd5, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmullw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf4, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmuludq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf4, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmuludq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe0, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpavgb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe0, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpavgb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe3, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpavgw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe3, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpavgw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xea, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xea, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xda, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminub %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xda, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminub (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xee, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xee, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xde, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxub %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xde, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxub (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf6, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsadbw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf6, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsadbw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf1, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsllw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf1, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsllw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf2, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpslld %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf2, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpslld (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf3, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsllq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf3, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsllq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe1, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsraw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe1, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsraw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe2, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe2, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd1, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrlw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd1, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrlw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd2, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrld %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd2, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrld (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd3, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrlq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd3, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrlq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x72, 0xf4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpslld $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x73, 0xfc, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpslldq $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x73, 0xf4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsllq $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x71, 0xf4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsllw $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x72, 0xe4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x71, 0xe4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsraw $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x72, 0xd4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrld $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x73, 0xdc, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrldq $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x73, 0xd4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrlq $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x71, 0xd4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrlw $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x72, 0xf4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpslld $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xdb, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpand %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xdb, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpand (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xeb, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpor %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xeb, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpor (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xef, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpxor %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xef, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpxor (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xdf, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpandn %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xdf, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpandn (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x74, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x74, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x75, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x75, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x76, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x76, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x64, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x64, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x65, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x65, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x66, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x66, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x63, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpacksswb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x63, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpacksswb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x6b, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpackssdw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x6b, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpackssdw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x67, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpackuswb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x67, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpackuswb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x70, 0xec, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshufd $4, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x79, 0x70, 0x28, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshufd $4, (%rax), %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x7a, 0x70, 0xec, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshufhw $4, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x7a, 0x70, 0x28, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshufhw $4, (%rax), %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x7b, 0x70, 0xec, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshuflw $4, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x7b, 0x70, 0x28, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshuflw $4, (%rax), %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x60, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpcklbw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x60, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpcklbw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x61, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpcklwd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x61, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpcklwd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x62, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckldq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x62, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckldq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x6c, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpcklqdq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x6c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpcklqdq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x68, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhbw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x68, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhbw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x69, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhwd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x69, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhwd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x6a, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhdq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x6a, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhdq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x6d, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhqdq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x6d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhqdq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc4, 0xe8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrw $7, %eax, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc4, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrw $7, (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x79, 0xc5, 0xc4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrw $7, %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0xc1, 0x79, 0xd7, 0xc4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovmskb %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0xf7, 0xfe ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovdqu %xmm14, %xmm15" + - + input: + bytes: [ 0xc5, 0x79, 0x6e, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovd %eax, %xmm14" + - + input: + bytes: [ 0xc5, 0x79, 0x6e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovd (%rax), %xmm14" + - + input: + bytes: [ 0xc5, 0x79, 0x7e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovd %xmm14, (%rax)" + - + input: + bytes: [ 0xc4, 0x61, 0xf9, 0x6e, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %rax, %xmm14" + - + input: + bytes: [ 0xc4, 0xe1, 0xf9, 0x7e, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %xmm0, %rax" + - + input: + bytes: [ 0xc5, 0x79, 0xd6, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %xmm14, (%rax)" + - + input: + bytes: [ 0xc4, 0x41, 0x7a, 0x7e, 0xe6 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x7a, 0x7e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq (%rax), %xmm14" + - + input: + bytes: [ 0xc4, 0x61, 0xf9, 0x6e, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %rax, %xmm14" + - + input: + bytes: [ 0xc4, 0x61, 0xf9, 0x7e, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %xmm14, %rax" + - + input: + bytes: [ 0xc4, 0x41, 0x7b, 0xe6, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %xmm11, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7a, 0xe6, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2pd %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x7a, 0xe6, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2pd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7a, 0x16, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovshdup %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x7a, 0x16, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovshdup (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7a, 0x12, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsldup %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x7a, 0x12, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsldup (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7b, 0x12, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovddup %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x7b, 0x12, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovddup (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xd0, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x23, 0xd0, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubps (%rax), %xmm11, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd0, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x21, 0xd0, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubpd (%rax), %xmm11, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0x7c, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0x7c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddps (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x7c, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x7c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddpd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0x7d, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0x7d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubps (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x7d, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x7d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubpd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x1c, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpabsb %xmm11, %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x1c, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpabsb (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x1d, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpabsw %xmm11, %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x1d, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpabsw (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x1e, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpabsd %xmm11, %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x1e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpabsd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x01, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x01, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x02, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x02, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x03, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x03, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x05, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x05, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x06, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x06, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x07, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x07, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x04, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaddubsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x04, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaddubsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x00, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshufb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x00, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshufb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x08, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsignb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x08, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsignb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x09, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsignw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x09, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsignw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x0a, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsignd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x0a, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsignd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x0b, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulhrsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x0b, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulhrsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x19, 0x0f, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpalignr $7, %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x0f, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpalignr $7, (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x19, 0x0b, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundsd $7, %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x0b, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundsd $7, (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x19, 0x0a, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundss $7, %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x0a, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundss $7, (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x09, 0xec, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundpd $7, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x09, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundpd $7, (%rax), %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x08, 0xec, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundps $7, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x08, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundps $7, (%rax), %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x41, 0xec ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphminposuw %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x41, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphminposuw (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x2b, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpackusdw %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x2b, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpackusdw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x29, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqq %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x29, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x38, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminsb %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x38, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminsb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x39, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminsd %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x39, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminsd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x3b, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminud %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x3b, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminud (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x3a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminuw %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x3a, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminuw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x3c, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxsb %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x3c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxsb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x3d, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxsd %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x3d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxsd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x3f, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxud %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x3f, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxud (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x3e, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxuw %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x3e, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxuw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x28, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmuldq %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x28, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmuldq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x51, 0x40, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulld %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x51, 0x40, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulld (%rax), %xmm5, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x51, 0x0c, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendps $3, %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x51, 0x0c, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendps $3, (%rax), %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x43, 0x51, 0x0d, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendpd $3, %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x51, 0x0d, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendpd $3, (%rax), %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x43, 0x51, 0x0e, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpblendw $3, %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x51, 0x0e, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpblendw $3, (%rax), %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x43, 0x51, 0x42, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmpsadbw $3, %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x51, 0x42, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmpsadbw $3, (%rax), %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x43, 0x51, 0x40, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdpps $3, %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x51, 0x40, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdpps $3, (%rax), %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x43, 0x51, 0x41, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdppd $3, %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x51, 0x41, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdppd $3, (%rax), %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x21, 0x4b, 0xed, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendvpd %xmm12, %xmm5, %xmm11, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x21, 0x4b, 0x28, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendvpd %xmm12, (%rax), %xmm11, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x21, 0x4a, 0xed, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendvps %xmm12, %xmm5, %xmm11, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x21, 0x4a, 0x28, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendvps %xmm12, (%rax), %xmm11, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x21, 0x4c, 0xed, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpblendvb %xmm12, %xmm5, %xmm11, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x21, 0x4c, 0x28, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpblendvb %xmm12, (%rax), %xmm11, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x20, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxbw %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x20, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxbw (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x23, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxwd %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x23, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxwd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x25, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxdq %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x25, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxdq (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x30, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxbw %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x30, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxbw (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x33, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxwd %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x33, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxwd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x35, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxdq %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x35, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxdq (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x22, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxbq %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x22, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxbq (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x32, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxbq %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x32, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxbq (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x21, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxbd %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x21, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxbd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x24, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxwq %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x24, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxwq (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x31, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxbd %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x31, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxbd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x34, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxwq %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x34, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxwq (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0xc1, 0x79, 0xc5, 0xc4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrw $7, %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x15, 0x20, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrw $7, %xmm12, (%rax)" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x16, 0xe0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrd $7, %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x16, 0x20, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrd $7, %xmm12, (%rax)" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x14, 0xe0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrb $7, %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x14, 0x20, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrb $7, %xmm12, (%rax)" + - + input: + bytes: [ 0xc4, 0x63, 0xf9, 0x16, 0xe1, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrq $7, %xmm12, %rcx" + - + input: + bytes: [ 0xc4, 0x63, 0xf9, 0x16, 0x21, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrq $7, %xmm12, (%rcx)" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x17, 0x20, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextractps $7, %xmm12, (%rax)" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x17, 0xe0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextractps $7, %xmm12, %eax" + - + input: + bytes: [ 0xc5, 0x19, 0xc4, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrw $7, %eax, %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0xc4, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrw $7, (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x20, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrb $7, %eax, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x20, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrb $7, (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x22, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrd $7, %eax, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x22, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrd $7, (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x99, 0x22, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrq $7, %rax, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x99, 0x22, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrq $7, (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x43, 0x29, 0x21, 0xdc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vinsertps $7, %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x29, 0x21, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vinsertps $7, (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x17, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vptest %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x17, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vptest (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x2a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntdqa (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x37, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtq %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x37, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtq (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x62, 0xd4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpistrm $7, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x62, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpistrm $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x60, 0xd4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpestrm $7, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x60, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpestrm $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x63, 0xd4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpistri $7, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x63, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpistri $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x61, 0xd4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpestri $7, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x61, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpestri $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0xdb, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesimc %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0xdb, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesimc (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xdc, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesenc %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xdc, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesenc (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xdd, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesenclast %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xdd, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesenclast (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xde, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesdec %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xde, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesdec (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xdf, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesdeclast %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xdf, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesdeclast (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0xdf, 0xd4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaeskeygenassist $7, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0xdf, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaeskeygenassist $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngeps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalseps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgeps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrueps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_osps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_sps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_usps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_sps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_usps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_osps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_osps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_usps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x7c, 0x28, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x28, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7c, 0x29, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %ymm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x7d, 0x28, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovapd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x28, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovapd %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7d, 0x29, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovapd %ymm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x7c, 0x10, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x10, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7c, 0x11, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %ymm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x7d, 0x10, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovupd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x10, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovupd %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7d, 0x11, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovupd %ymm11, (%rax)" + - + input: + bytes: [ 0xc4, 0xc1, 0x1c, 0x15, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhps %ymm11, %ymm12, %ymm4" + - + input: + bytes: [ 0xc4, 0xc1, 0x1d, 0x15, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhpd %ymm11, %ymm12, %ymm4" + - + input: + bytes: [ 0xc4, 0xc1, 0x1c, 0x14, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklps %ymm11, %ymm12, %ymm4" + - + input: + bytes: [ 0xc4, 0xc1, 0x1d, 0x14, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklpd %ymm11, %ymm12, %ymm4" + - + input: + bytes: [ 0xc5, 0x1c, 0x15, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhps -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1d, 0x15, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhpd -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1c, 0x14, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklps -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1d, 0x14, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklpd -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7d, 0xe7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntdq %ymm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x7d, 0x2b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntpd %ymm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x7c, 0x2b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntps %ymm11, (%rax)" + - + input: + bytes: [ 0xc4, 0xc1, 0x78, 0x50, 0xc4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovmskps %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0xc1, 0x79, 0x50, 0xc4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovmskpd %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0xc1, 0x5c, 0x5f, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxps %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5d, 0x5f, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxpd %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5c, 0x5d, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminps %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5d, 0x5d, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminpd %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5c, 0x5c, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubps %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5d, 0x5c, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubpd %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5c, 0x5e, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivps %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5d, 0x5e, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivpd %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5c, 0x58, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddps %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5d, 0x58, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddpd %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5c, 0x59, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulps %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5d, 0x59, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulpd %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5f, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxps (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5f, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxpd (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5d, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminps (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5d, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminpd (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5c, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubps (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5c, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubpd (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivps (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivpd (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x58, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddps (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x58, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddpd (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x59, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulps (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x59, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulpd (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x51, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtpd %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7d, 0x51, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtpd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x51, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtps %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7c, 0x51, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtps (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x52, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrsqrtps %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7c, 0x52, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrsqrtps (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x53, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrcpps %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7c, 0x53, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrcpps (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x0c, 0x54, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandps %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc4, 0x41, 0x0d, 0x54, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandpd %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc5, 0x1c, 0x54, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandps -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1d, 0x54, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandpd -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x0c, 0x56, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorps %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc4, 0x41, 0x0d, 0x56, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorpd %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc5, 0x1c, 0x56, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorps -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1d, 0x56, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorpd -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x0c, 0x57, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorps %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc4, 0x41, 0x0d, 0x57, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorpd %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc5, 0x1c, 0x57, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorps -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1d, 0x57, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorpd -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x0c, 0x55, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnps %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc4, 0x41, 0x0d, 0x55, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnpd %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc5, 0x1c, 0x55, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnps -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1d, 0x55, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnpd -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x5a, 0xe5 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2pd %xmm13, %ymm12" + - + input: + bytes: [ 0xc5, 0x7c, 0x5a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2pd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7e, 0xe6, 0xe5 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2pd %xmm13, %ymm12" + - + input: + bytes: [ 0xc5, 0x7e, 0xe6, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2pd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x5b, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2ps %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7c, 0x5b, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2ps (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x5b, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2dq %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7d, 0x5b, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2dq (%rax), %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x7e, 0x5b, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttps2dq %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7e, 0x5b, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttps2dq (%rax), %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0xe6, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %xmm11, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0xe6, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %ymm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0xe6, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %xmm11, %xmm10" + - + input: + bytes: [ 0xc5, 0x79, 0xe6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttpd2dqx (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0xe6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %ymm12, %xmm11" + - + input: + bytes: [ 0xc5, 0x7d, 0xe6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttpd2dqy (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x5a, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %ymm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x5a, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %xmm11, %xmm10" + - + input: + bytes: [ 0xc5, 0x79, 0x5a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2psx (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x5a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %ymm12, %xmm11" + - + input: + bytes: [ 0xc5, 0x7d, 0x5a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2psy (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x7f, 0xe6, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %ymm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x7f, 0xe6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %ymm12, %xmm11" + - + input: + bytes: [ 0xc5, 0x7f, 0xe6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2dqy (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x7b, 0xe6, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %xmm11, %xmm10" + - + input: + bytes: [ 0xc5, 0x7b, 0xe6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2dqx (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpleps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnleps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpleps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnleps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x4c, 0xc2, 0x64, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordps -4(%rbx, %rcx, 8), %ymm6, %ymm12" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplepd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlepd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqpd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplepd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltpd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqpd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlepd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltpd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x4d, 0xc2, 0x64, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordpd -4(%rbx, %rcx, 8), %ymm6, %ymm12" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordpd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngeps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalseps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgeps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrueps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_osps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_sps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_usps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_sps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_usps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_osps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_osps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_usps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1f, 0xd0, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x27, 0xd0, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubps (%rax), %ymm11, %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xd0, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x25, 0xd0, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubpd (%rax), %ymm11, %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1f, 0x7c, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1f, 0x7c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddps (%rax), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0x7c, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0x7c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddpd (%rax), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1f, 0x7d, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1f, 0x7d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubps (%rax), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0x7d, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0x7d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubpd (%rax), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x43, 0x2d, 0x0c, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendps $3, %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x2d, 0x0c, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendps $3, (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x43, 0x2d, 0x0d, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendpd $3, %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x2d, 0x0d, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendpd $3, (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x43, 0x2d, 0x40, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdpps $3, %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x2d, 0x40, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdpps $3, (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x7d, 0x1a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vbroadcastf128 (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x62, 0x7d, 0x19, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vbroadcastsd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x18, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vbroadcastss (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x7d, 0x18, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vbroadcastss (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x43, 0x1d, 0x18, 0xd4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vinsertf128 $7, %xmm12, %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x63, 0x1d, 0x18, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vinsertf128 $7, (%rax), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x43, 0x7d, 0x19, 0xe4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextractf128 $7, %ymm12, %xmm12" + - + input: + bytes: [ 0xc4, 0x63, 0x7d, 0x19, 0x20, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextractf128 $7, %ymm12, (%rax)" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x2f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovpd %xmm12, %xmm10, (%rax)" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x2f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovpd %ymm12, %ymm10, (%rax)" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x2d, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovpd (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x1d, 0x2d, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovpd (%rax), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x2e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovps %xmm12, %xmm10, (%rax)" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x2e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovps %ymm12, %ymm10, (%rax)" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x2c, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovps (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x1d, 0x2c, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovps (%rax), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x04, 0xd3, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps $7, %xmm11, %xmm10" + - + input: + bytes: [ 0xc4, 0x43, 0x7d, 0x04, 0xda, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps $7, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x04, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x7d, 0x04, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps $7, (%rax), %ymm10" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x0c, 0xdb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps %xmm11, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x0c, 0xdb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps %ymm11, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x0c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x0c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x05, 0xd3, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd $7, %xmm11, %xmm10" + - + input: + bytes: [ 0xc4, 0x43, 0x7d, 0x05, 0xda, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd $7, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x05, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x7d, 0x05, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd $7, (%rax), %ymm10" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x0d, 0xdb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd %xmm11, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x0d, 0xdb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd %ymm11, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x0d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x0d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x43, 0x2d, 0x06, 0xdc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vperm2f128 $7, %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x2d, 0x06, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vperm2f128 $7, (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x41, 0x7b, 0x2d, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsd2si %xmm8, %r8d" + - + input: + bytes: [ 0xc5, 0xfb, 0x2d, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsd2si (%rcx), %ecx" + - + input: + bytes: [ 0xc4, 0xe1, 0xfa, 0x2d, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtss2si %xmm4, %rcx" + - + input: + bytes: [ 0xc4, 0x61, 0xfa, 0x2d, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtss2si (%rcx), %r8" + - + input: + bytes: [ 0xc4, 0x41, 0x3b, 0x2a, 0xf8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl %r8d, %xmm8, %xmm15" + - + input: + bytes: [ 0xc5, 0x3b, 0x2a, 0x7d, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%rbp), %xmm8, %xmm15" + - + input: + bytes: [ 0xc4, 0xe1, 0xdb, 0x2a, 0xf1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2sdq %rcx, %xmm4, %xmm6" + - + input: + bytes: [ 0xc4, 0xe1, 0xdb, 0x2a, 0x31 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2sdq (%rcx), %xmm4, %xmm6" + - + input: + bytes: [ 0xc4, 0xe1, 0xda, 0x2a, 0xf1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2ssq %rcx, %xmm4, %xmm6" + - + input: + bytes: [ 0xc4, 0xe1, 0xda, 0x2a, 0x31 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2ssq (%rcx), %xmm4, %xmm6" + - + input: + bytes: [ 0xc4, 0xe1, 0xfb, 0x2c, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttsd2si %xmm4, %rcx" + - + input: + bytes: [ 0xc4, 0xe1, 0xfb, 0x2c, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttsd2si (%rcx), %rcx" + - + input: + bytes: [ 0xc4, 0xe1, 0xfa, 0x2c, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttss2si %xmm4, %rcx" + - + input: + bytes: [ 0xc4, 0xe1, 0xfa, 0x2c, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttss2si (%rcx), %rcx" + - + input: + bytes: [ 0xc5, 0x7f, 0xf0, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vlddqu (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7f, 0x12, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovddup %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7f, 0x12, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovddup (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x6f, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqa %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7d, 0x7f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqa %ymm12, (%rax)" + - + input: + bytes: [ 0xc5, 0x7d, 0x6f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqa (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7e, 0x6f, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqu %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7e, 0x7f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqu %ymm12, (%rax)" + - + input: + bytes: [ 0xc5, 0x7e, 0x6f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqu (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7e, 0x16, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovshdup %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7e, 0x16, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovshdup (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7e, 0x12, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsldup %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7e, 0x12, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsldup (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x42, 0x7d, 0x17, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vptest %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x62, 0x7d, 0x17, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vptest (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x43, 0x7d, 0x09, 0xda, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundpd $7, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x7d, 0x09, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundpd $7, (%rax), %ymm10" + - + input: + bytes: [ 0xc4, 0x43, 0x7d, 0x08, 0xda, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundps $7, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x7d, 0x08, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundps $7, (%rax), %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x2d, 0xc6, 0xdc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufpd $7, %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc5, 0x2d, 0xc6, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufpd $7, (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x41, 0x2c, 0xc6, 0xdc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufps $7, %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc5, 0x2c, 0xc6, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufps $7, (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x0f, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestpd %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x42, 0x7d, 0x0f, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestpd %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x0f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestpd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x7d, 0x0f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestpd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x0e, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestps %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x42, 0x7d, 0x0e, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestps %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x0e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestps (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x7d, 0x0e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestps (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x17, 0xc0, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextractps $10, %xmm8, %r8d" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x17, 0xe1, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextractps $7, %xmm4, %ecx" + - + input: + bytes: [ 0xc4, 0xe1, 0xf9, 0x7e, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %xmm4, %rcx" + - + input: + bytes: [ 0xc5, 0xf9, 0x50, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovmskpd %xmm4, %ecx" + - + input: + bytes: [ 0xc5, 0xfd, 0x50, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovmskpd %ymm4, %ecx" + - + input: + bytes: [ 0xc5, 0xf8, 0x50, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovmskps %xmm4, %ecx" + - + input: + bytes: [ 0xc5, 0xfc, 0x50, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovmskps %ymm4, %ecx" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x14, 0xe1, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrb $7, %xmm4, %ecx" + - + input: + bytes: [ 0xc4, 0x41, 0x01, 0xc4, 0xc0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrw $7, %r8d, %xmm15, %xmm8" + - + input: + bytes: [ 0xc5, 0xd9, 0xc4, 0xf1, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrw $7, %ecx, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xf9, 0xd7, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovmskb %xmm4, %ecx" + - + input: + bytes: [ 0xc4, 0x63, 0x1d, 0x4b, 0xac, 0x20, 0xad, 0xde, 0x00, 0x00, 0xb0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendvpd %ymm11, 0xdead(%rax, %riz), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x81, 0x78, 0x29, 0x1c, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm3, (%r14, %r11)" + - + input: + bytes: [ 0xc4, 0x81, 0x78, 0x28, 0x1c, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps (%r14, %r11), %xmm3" + - + input: + bytes: [ 0xc4, 0xc1, 0x78, 0x29, 0x1c, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm3, (%r14, %rbx)" + - + input: + bytes: [ 0xc4, 0xc1, 0x78, 0x28, 0x1c, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps (%r14, %rbx), %xmm3" + - + input: + bytes: [ 0xc4, 0xa1, 0x78, 0x29, 0x1c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm3, (%rax, %r11)" + - + input: + bytes: [ 0xc4, 0xe2, 0xf9, 0x92, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherdpd %xmm0, (%rdi, %xmm1, 2), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0xf9, 0x93, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherqpd %xmm0, (%rdi, %xmm1, 2), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0xfd, 0x92, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherdpd %ymm0, (%rdi, %xmm1, 2), %ymm2" + - + input: + bytes: [ 0xc4, 0xe2, 0xfd, 0x93, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherqpd %ymm0, (%rdi, %ymm1, 2), %ymm2" + - + input: + bytes: [ 0xc4, 0x02, 0x39, 0x92, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherdps %xmm8, (%r15, %xmm9, 2), %xmm10" + - + input: + bytes: [ 0xc4, 0x02, 0x39, 0x93, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherqps %xmm8, (%r15, %xmm9, 2), %xmm10" + - + input: + bytes: [ 0xc4, 0x02, 0x3d, 0x92, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherdps %ymm8, (%r15, %ymm9, 2), %ymm10" + - + input: + bytes: [ 0xc4, 0x02, 0x3d, 0x93, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherqps %xmm8, (%r15, %ymm9, 2), %xmm10" + - + input: + bytes: [ 0xc4, 0xe2, 0xf9, 0x90, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherdq %xmm0, (%rdi, %xmm1, 2), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0xf9, 0x91, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherqq %xmm0, (%rdi, %xmm1, 2), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0xfd, 0x90, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherdq %ymm0, (%rdi, %xmm1, 2), %ymm2" + - + input: + bytes: [ 0xc4, 0xe2, 0xfd, 0x91, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherqq %ymm0, (%rdi, %ymm1, 2), %ymm2" + - + input: + bytes: [ 0xc4, 0x02, 0x39, 0x90, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherdd %xmm8, (%r15, %xmm9, 2), %xmm10" + - + input: + bytes: [ 0xc4, 0x02, 0x39, 0x91, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherqd %xmm8, (%r15, %xmm9, 2), %xmm10" + - + input: + bytes: [ 0xc4, 0x02, 0x3d, 0x90, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherdd %ymm8, (%r15, %ymm9, 2), %ymm10" + - + input: + bytes: [ 0xc4, 0x02, 0x3d, 0x91, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherqd %xmm8, (%r15, %ymm9, 2), %xmm10" + - + input: + bytes: [ 0xc5, 0x78, 0x28, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm0, %xmm8" + - + input: + bytes: [ 0xc5, 0x78, 0x29, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm8, %xmm0" + - + input: + bytes: [ 0xc5, 0x7c, 0x28, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %ymm0, %ymm8" + - + input: + bytes: [ 0xc5, 0x7c, 0x29, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %ymm8, %ymm0" + - + input: + bytes: [ 0xc5, 0x78, 0x10, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %xmm0, %xmm8" + - + input: + bytes: [ 0xc5, 0x78, 0x11, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %xmm8, %xmm0" + - + input: + bytes: [ 0xc5, 0x7c, 0x10, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %ymm0, %ymm8" + - + input: + bytes: [ 0xc5, 0x7c, 0x11, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %ymm8, %ymm0" + - + input: + bytes: [ 0xc5, 0x7a, 0x10, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovss %xmm0, %xmm0, %xmm8" + - + input: + bytes: [ 0xc5, 0xba, 0x10, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovss %xmm0, %xmm8, %xmm0" + - + input: + bytes: [ 0xc5, 0x7a, 0x11, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovss %xmm8, %xmm0, %xmm0" + - + input: + bytes: [ 0xc5, 0x7b, 0x10, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsd %xmm0, %xmm0, %xmm8" + - + input: + bytes: [ 0xc5, 0xbb, 0x10, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsd %xmm0, %xmm8, %xmm0" + - + input: + bytes: [ 0xc5, 0x7b, 0x11, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsd %xmm8, %xmm0, %xmm0" diff --git a/thirdparty/capstone/tests/MC/X86/x86_64-bmi-encoding.s.yaml b/thirdparty/capstone/tests/MC/X86/x86_64-bmi-encoding.s.yaml new file mode 100644 index 0000000..af5be80 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86_64-bmi-encoding.s.yaml @@ -0,0 +1,451 @@ +test_cases: + - + input: + bytes: [ 0xc4, 0xc2, 0x28, 0xf3, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsmskl %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0xc2, 0xa8, 0xf3, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsmskq %r11, %r10" + - + input: + bytes: [ 0xc4, 0xe2, 0x28, 0xf3, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsmskl (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0xe2, 0xa8, 0xf3, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsmskq (%rax), %r10" + - + input: + bytes: [ 0xc4, 0xc2, 0x28, 0xf3, 0xdb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsil %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0xc2, 0xa8, 0xf3, 0xdb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsiq %r11, %r10" + - + input: + bytes: [ 0xc4, 0xe2, 0x28, 0xf3, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsil (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0xe2, 0xa8, 0xf3, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsiq (%rax), %r10" + - + input: + bytes: [ 0xc4, 0xc2, 0x28, 0xf3, 0xcb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsrl %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0xc2, 0xa8, 0xf3, 0xcb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsrq %r11, %r10" + - + input: + bytes: [ 0xc4, 0xe2, 0x28, 0xf3, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsrl (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0xe2, 0xa8, 0xf3, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsrq (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x62, 0x20, 0xf2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "andnl (%rax), %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0xa0, 0xf2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "andnq (%rax), %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0x18, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrl %r12d, (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0x18, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x98, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrq %r12, (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x98, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0x18, 0xf5, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bzhil %r12d, (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0x18, 0xf5, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bzhil %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x98, 0xf5, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bzhiq %r12, (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x98, 0xf5, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bzhiq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x22, 0xf5, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pextl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x22, 0xf5, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pextl (%rax), %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0xa2, 0xf5, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pextq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0xa2, 0xf5, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pextq (%rax), %r11, %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x23, 0xf5, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pdepl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x23, 0xf5, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pdepl (%rax), %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0xa3, 0xf5, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pdepq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0xa3, 0xf5, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pdepq (%rax), %r11, %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x23, 0xf6, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "mulxl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x23, 0xf6, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "mulxl (%rax), %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0xa3, 0xf6, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "mulxq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0xa3, 0xf6, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "mulxq (%rax), %r11, %r10" + - + input: + bytes: [ 0xc4, 0x43, 0x7b, 0xf0, 0xd4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rorxl $10, %r12d, %r10d" + - + input: + bytes: [ 0xc4, 0x63, 0x7b, 0xf0, 0x10, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rorxl $31, (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0x43, 0xfb, 0xf0, 0xd4, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rorxq $1, %r12, %r10" + - + input: + bytes: [ 0xc4, 0x63, 0xfb, 0xf0, 0x10, 0x3f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rorxq $63, (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shlxl %r12d, (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shlxl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x99, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shlxq %r12, (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x99, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shlxq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0x1a, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sarxl %r12d, (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0x1a, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sarxl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x9a, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sarxq %r12, (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x9a, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sarxq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0x1b, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shrxl %r12d, (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0x1b, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shrxl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x9b, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shrxq %r12, (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x9b, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shrxq %r12, %r11, %r10" diff --git a/thirdparty/capstone/tests/MC/X86/x86_64-encoding.s.yaml b/thirdparty/capstone/tests/MC/X86/x86_64-encoding.s.yaml new file mode 100644 index 0000000..9c83b28 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86_64-encoding.s.yaml @@ -0,0 +1,523 @@ +test_cases: + - + input: + bytes: [ 0x65, 0x48, 0x8b, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq %gs:(%rdi), %rax" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf0, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b %bl, %eax" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf0, 0x43, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b 4(%rbx), %eax" + - + input: + bytes: [ 0x66, 0xf2, 0x0f, 0x38, 0xf1, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32w %bx, %eax" + - + input: + bytes: [ 0x66, 0xf2, 0x0f, 0x38, 0xf1, 0x43, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32w 4(%rbx), %eax" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l %ebx, %eax" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x43, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l 4(%rbx), %eax" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x8c, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l -0x21524111(%rbx, %rcx, 8), %ecx" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x0c, 0x25, 0x45, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l 0x45, %ecx" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x0c, 0x25, 0xed, 0x7e, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l 0x7eed, %ecx" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x0c, 0x25, 0xfe, 0xca, 0xbe, 0xba ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l 0xffffffffbabecafe, %ecx" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l %ecx, %ecx" + - + input: + bytes: [ 0xf2, 0x41, 0x0f, 0x38, 0xf0, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b %r11b, %eax" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf0, 0x43, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b 4(%rbx), %eax" + - + input: + bytes: [ 0xf2, 0x48, 0x0f, 0x38, 0xf0, 0xc7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b %dil, %rax" + - + input: + bytes: [ 0xf2, 0x49, 0x0f, 0x38, 0xf0, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b %r11b, %rax" + - + input: + bytes: [ 0xf2, 0x48, 0x0f, 0x38, 0xf0, 0x43, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b 4(%rbx), %rax" + - + input: + bytes: [ 0xf2, 0x48, 0x0f, 0x38, 0xf1, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32q %rbx, %rax" + - + input: + bytes: [ 0xf2, 0x48, 0x0f, 0x38, 0xf1, 0x43, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32q 4(%rbx), %rax" + - + input: + bytes: [ 0x49, 0x0f, 0x6e, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq %r8, %mm1" + - + input: + bytes: [ 0x41, 0x0f, 0x6e, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movd %r8d, %mm1" + - + input: + bytes: [ 0x48, 0x0f, 0x6e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq %rdx, %mm1" + - + input: + bytes: [ 0x0f, 0x6e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movd %edx, %mm1" + - + input: + bytes: [ 0x49, 0x0f, 0x7e, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq %mm1, %r8" + - + input: + bytes: [ 0x41, 0x0f, 0x7e, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movd %mm1, %r8d" + - + input: + bytes: [ 0x48, 0x0f, 0x7e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq %mm1, %rdx" + - + input: + bytes: [ 0x0f, 0x7e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movd %mm1, %edx" + - + input: + bytes: [ 0x0f, 0x3a, 0xcc, 0xd1, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1rnds4 $1, %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x3a, 0xcc, 0x10, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1rnds4 $1, (%rax), %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xc8, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1nexte %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xc9, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1msg1 %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xc9, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1msg1 (%rax), %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xca, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1msg2 %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xca, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1msg2 (%rax), %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256rnds2 %xmm0, (%rax), %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcb, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256rnds2 %xmm0, %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256rnds2 %xmm0, (%rax), %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcb, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256rnds2 %xmm0, %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcc, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256msg1 %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcc, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256msg1 (%rax), %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcd, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256msg2 %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcd, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256msg2 (%rax), %xmm2" + - + input: + bytes: [ 0x48, 0x8b, 0x1c, 0x25, 0xad, 0xde, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq 0xdead, %rbx" + - + input: + bytes: [ 0x48, 0x8b, 0x04, 0x25, 0xef, 0xbe, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq 0xbeef, %rax" + - + input: + bytes: [ 0x48, 0x8b, 0x04, 0xe5, 0xfc, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq -4(, %riz, 8), %rax" + - + input: + bytes: [ 0x48, 0x8b, 0x04, 0x21 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq (%rcx, %riz), %rax" + - + input: + bytes: [ 0x48, 0x8b, 0x04, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq (%rcx, %riz, 8), %rax" + - + input: + bytes: [ 0x48, 0x0f, 0xae, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "fxsave64 (%rax)" + - + input: + bytes: [ 0x48, 0x0f, 0xae, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "fxrstor64 (%rax)" + - + input: + bytes: [ 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "leave" + - + input: + bytes: [ 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "leave" + - + input: + bytes: [ 0x67, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "flds (%edi)" + - + input: + bytes: [ 0x67, 0xdf, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "filds (%edi)" + - + input: + bytes: [ 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "flds (%rdi)" + - + input: + bytes: [ 0xdf, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "filds (%rdi)" + - + input: + bytes: [ 0x66, 0x0f, 0xd7, 0xcd ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pmovmskb %xmm5, %ecx" + - + input: + bytes: [ 0x66, 0x0f, 0xc4, 0xe9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pinsrw $3, %ecx, %xmm5" + - + input: + bytes: [ 0x66, 0x0f, 0xc4, 0xe9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pinsrw $3, %ecx, %xmm5" diff --git a/thirdparty/capstone/tests/MC/X86/x86_64-fma3-encoding.s.yaml b/thirdparty/capstone/tests/MC/X86/x86_64-fma3-encoding.s.yaml new file mode 100644 index 0000000..4724442 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86_64-fma3-encoding.s.yaml @@ -0,0 +1,1513 @@ +test_cases: + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x96, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x96, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x96, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x96, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xa6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xa6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xa6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xa6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xb6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xb6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xb6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xb6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x97, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x97, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x97, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x97, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xa7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xa7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xa7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xa7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xb7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xb7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xb7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xb7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x9a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x9a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x9a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x9a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xaa, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xaa, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xaa, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xaa, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xba, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xba, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xba, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xba, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x9c, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x9c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x9c, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x9c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xac, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xac, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xac, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xac, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xbc, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xbc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xbc, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xbc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x9e, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x9e, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x9e, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x9e, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xae, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xae, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xae, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xae, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xbe, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xbe, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xbe, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xbe, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x96, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x96, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x96, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x96, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xa6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xa6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xa6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xa6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xb6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xb6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xb6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xb6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x97, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x97, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x97, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x97, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xa7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xa7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xa7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xa7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xb7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xb7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xb7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xb7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x9a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x9a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x9a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x9a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xaa, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xaa, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xaa, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xaa, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xba, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xba, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xba, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xba, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x9c, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x9c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x9c, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x9c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xac, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xac, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xac, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xac, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xbc, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xbc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xbc, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xbc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x9e, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x9e, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x9e, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x9e, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xae, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xae, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xae, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xae, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xbe, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xbe, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xbe, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xbe, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231ps (%rax), %ymm10, %ymm11" diff --git a/thirdparty/capstone/tests/MC/X86/x86_64-fma4-encoding.s.yaml b/thirdparty/capstone/tests/MC/X86/x86_64-fma4-encoding.s.yaml new file mode 100644 index 0000000..84384b1 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86_64-fma4-encoding.s.yaml @@ -0,0 +1,874 @@ +test_cases: + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6a, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddss (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x6a, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddss %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6a, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddss %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6b, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x6b, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6b, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xc3, 0xf9, 0x6b, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsd %xmm10, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x68, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddps (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x68, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddps %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x68, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddps %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x69, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddpd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x69, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddpd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x69, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddpd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x68, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddps (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x68, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddps %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x68, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddps %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x69, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddpd (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x69, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddpd %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x69, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddpd %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubss (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x6e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubss %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6e, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubss %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubsd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x6f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubsd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6f, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubsd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubps (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x6c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubps %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6c, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubps %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubpd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x6d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubpd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6d, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubpd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x6c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubps (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x6c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubps %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x6c, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubps %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x6d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubpd (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x6d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubpd %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x6d, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubpd %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7a, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddss (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x7a, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddss %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7a, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddss %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7b, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddsd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x7b, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddsd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7b, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddsd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x78, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddps (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x78, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddps %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x78, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddps %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x79, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddpd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x79, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddpd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x79, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddpd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x78, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddps (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x78, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddps %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x78, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddps %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x79, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddpd (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x79, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddpd %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x79, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddpd %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubss (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x7e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubss %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7e, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubss %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubsd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x7f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubsd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7f, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubsd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubps (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x7c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubps %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7c, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubps %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubpd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x7d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubpd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7d, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubpd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x7c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubps (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x7c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubps %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x7c, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubps %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x7d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubpd (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x7d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubpd %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x7d, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubpd %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubps (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x5c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubps %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5c, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubps %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubpd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x5d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubpd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5d, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubpd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubps (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x5c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubps %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5c, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubps %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubpd (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x5d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubpd %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5d, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubpd %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddps (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x5e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddps %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5e, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddps %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddpd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x5f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddpd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5f, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddpd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddps (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x5e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddps %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5e, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddps %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddpd (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x5f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddpd %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5f, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddpd %ymm2, %ymm1, %ymm0, %ymm0" diff --git a/thirdparty/capstone/tests/MC/X86/x86_64-imm-widths.s.yaml b/thirdparty/capstone/tests/MC/X86/x86_64-imm-widths.s.yaml new file mode 100644 index 0000000..d88cee5 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86_64-imm-widths.s.yaml @@ -0,0 +1,235 @@ +test_cases: + - + input: + bytes: [ 0x04, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addb $0x00, %al" + - + input: + bytes: [ 0x04, 0x7f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addb $0x7F, %al" + - + input: + bytes: [ 0x04, 0x80 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addb $0x80, %al" + - + input: + bytes: [ 0x04, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addb $0xFF, %al" + - + input: + bytes: [ 0x66, 0x83, 0xc0, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addw $0x0000, %ax" + - + input: + bytes: [ 0x66, 0x83, 0xc0, 0x7f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addw $0x007F, %ax" + - + input: + bytes: [ 0x66, 0x83, 0xc0, 0x80 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addw $-0x80, %ax" + - + input: + bytes: [ 0x66, 0x83, 0xc0, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addw $-1, %ax" + - + input: + bytes: [ 0x83, 0xc0, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addl $0x00000000, %eax" + - + input: + bytes: [ 0x83, 0xc0, 0x7f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addl $0x0000007F, %eax" + - + input: + bytes: [ 0x05, 0x80, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addl $0xFF80, %eax" + - + input: + bytes: [ 0x05, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addl $0xFFFF, %eax" + - + input: + bytes: [ 0x83, 0xc0, 0x80 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addl $-0x80, %eax" + - + input: + bytes: [ 0x83, 0xc0, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addl $-1, %eax" + - + input: + bytes: [ 0x48, 0x83, 0xc0, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0x0000000000000000, %rax" + - + input: + bytes: [ 0x48, 0x83, 0xc0, 0x7f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0x000000000000007F, %rax" + - + input: + bytes: [ 0x48, 0x83, 0xc0, 0x80 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0xFFFFFFFFFFFFFF80, %rax" + - + input: + bytes: [ 0x48, 0x83, 0xc0, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0xFFFFFFFFFFFFFFFF, %rax" + - + input: + bytes: [ 0x48, 0x83, 0xc0, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0x0000000000000000, %rax" + - + input: + bytes: [ 0x48, 0x05, 0x80, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0xFF80, %rax" + - + input: + bytes: [ 0x48, 0x05, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0xFFFF, %rax" + - + input: + bytes: [ 0x48, 0xb8, 0x80, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movabsq $0xFFFFFF80, %rax" + - + input: + bytes: [ 0x48, 0xb8, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movabsq $0xFFFFFFFF, %rax" + - + input: + bytes: [ 0x48, 0x05, 0xff, 0xff, 0xff, 0x7f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0x000000007FFFFFFF, %rax" + - + input: + bytes: [ 0x48, 0x05, 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0xFFFFFFFF80000000, %rax" + - + input: + bytes: [ 0x48, 0x05, 0x00, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0xFFFFFFFFFFFFFF00, %rax" diff --git a/thirdparty/capstone/tests/MC/X86/x86_64-rand-encoding.s.yaml b/thirdparty/capstone/tests/MC/X86/x86_64-rand-encoding.s.yaml new file mode 100644 index 0000000..30339e4 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86_64-rand-encoding.s.yaml @@ -0,0 +1,109 @@ +test_cases: + - + input: + bytes: [ 0x66, 0x0f, 0xc7, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdrandw %ax" + - + input: + bytes: [ 0x0f, 0xc7, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdrandl %eax" + - + input: + bytes: [ 0x48, 0x0f, 0xc7, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdrandq %rax" + - + input: + bytes: [ 0x66, 0x41, 0x0f, 0xc7, 0xf3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdrandw %r11w" + - + input: + bytes: [ 0x41, 0x0f, 0xc7, 0xf3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdrandl %r11d" + - + input: + bytes: [ 0x49, 0x0f, 0xc7, 0xf3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdrandq %r11" + - + input: + bytes: [ 0x66, 0x0f, 0xc7, 0xf8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdseedw %ax" + - + input: + bytes: [ 0x0f, 0xc7, 0xf8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdseedl %eax" + - + input: + bytes: [ 0x48, 0x0f, 0xc7, 0xf8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdseedq %rax" + - + input: + bytes: [ 0x66, 0x41, 0x0f, 0xc7, 0xfb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdseedw %r11w" + - + input: + bytes: [ 0x41, 0x0f, 0xc7, 0xfb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdseedl %r11d" + - + input: + bytes: [ 0x49, 0x0f, 0xc7, 0xfb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdseedq %r11" diff --git a/thirdparty/capstone/tests/MC/X86/x86_64-rtm-encoding.s.yaml b/thirdparty/capstone/tests/MC/X86/x86_64-rtm-encoding.s.yaml new file mode 100644 index 0000000..0efe2ad --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86_64-rtm-encoding.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0x0f, 0x01, 0xd5 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "xend" + - + input: + bytes: [ 0x0f, 0x01, 0xd6 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "xtest" + - + input: + bytes: [ 0xc6, 0xf8, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "xabort $13" diff --git a/thirdparty/capstone/tests/MC/X86/x86_64-tbm-encoding.s.yaml b/thirdparty/capstone/tests/MC/X86/x86_64-tbm-encoding.s.yaml new file mode 100644 index 0000000..6110a9a --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86_64-tbm-encoding.s.yaml @@ -0,0 +1,352 @@ +test_cases: + - + input: + bytes: [ 0x8f, 0xea, 0x78, 0x10, 0xc7, 0xfe, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrl $2814, %edi, %eax" + - + input: + bytes: [ 0x8f, 0xea, 0x78, 0x10, 0x07, 0xfe, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrl $2814, (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xea, 0xf8, 0x10, 0xc7, 0xfe, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrq $2814, %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xea, 0xf8, 0x10, 0x07, 0xfe, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrq $2814, (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xcf ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcfilll %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcfilll (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xcf ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcfillq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcfillq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x02, 0xf7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcil %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x02, 0x37 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcil (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x02, 0xf7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blciq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x02, 0x37 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blciq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xef ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcicl %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x2f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcicl (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xef ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcicq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x2f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcicq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x02, 0xcf ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcmskl %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x02, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcmskl (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x02, 0xcf ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcmskq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x02, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcmskq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xdf ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcsl %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcsl (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xdf ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcsq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcsq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xd7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsfilll %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsfilll (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xd7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsfillq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsfillq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xf7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsicl %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x37 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsicl (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xf7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsicq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "t1mskcl %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x3f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "t1mskcl (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "t1mskcq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x3f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "t1mskcq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xe7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "tzmskl %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x27 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "tzmskl (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xe7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "tzmskq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x27 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "tzmskq (%rdi), %rax" diff --git a/thirdparty/capstone/tests/MC/X86/x86_64-xop-encoding.s.yaml b/thirdparty/capstone/tests/MC/X86/x86_64-xop-encoding.s.yaml new file mode 100644 index 0000000..d1400f9 --- /dev/null +++ b/thirdparty/capstone/tests/MC/X86/x86_64-xop-encoding.s.yaml @@ -0,0 +1,1360 @@ +test_cases: + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xe2, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubwd (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xe2, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubwd %xmm0, %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xe3, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubdq (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xe3, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubdq %xmm0, %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xe1, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubbw (%rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xe1, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubbw %xmm2, %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc7, 0x21 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddwq (%rcx), %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc7, 0xd6 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddwq %xmm6, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc6, 0x3c, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddwd (%rdx, %rax), %xmm7" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc6, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddwd %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd7, 0x34, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphadduwq (%rcx, %rax), %xmm6" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd7, 0xc7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphadduwq %xmm7, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd6, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphadduwd (%rax), %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphadduwd %xmm2, %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xdb, 0x64, 0x01, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddudq 8(%rcx, %rax), %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xdb, 0xd6 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddudq %xmm6, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd1, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddubw (%rcx), %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd1, 0xc5 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddubw %xmm5, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd3, 0x21 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddubq (%rcx), %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd3, 0xd2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddubq %xmm2, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd2, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddubd (%rax), %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd2, 0xfd ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddubd %xmm5, %xmm7" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xcb, 0x22 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphadddq (%rdx), %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xcb, 0xec ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphadddq %xmm4, %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc1, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddbw (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc1, 0xf5 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddbw %xmm5, %xmm6" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc3, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddbq (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc3, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddbq %xmm2, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc2, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddbd (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc2, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddbd %xmm1, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x82, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczss (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x82, 0xfd ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczss %xmm5, %xmm7" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x83, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczsd (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x83, 0xc7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczsd %xmm7, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x80, 0x58, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczps 4(%rax), %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x80, 0xee ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczps %xmm6, %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x80, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczps (%rcx), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x7c, 0x80, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczps %ymm2, %ymm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x81, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczpd (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x81, 0xc7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczpd %xmm7, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x7c, 0x81, 0x14, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczpd (%rcx, %rax), %ymm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x7c, 0x81, 0xdd ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczpd %ymm5, %ymm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x95, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlw %xmm0, %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0xf0, 0x95, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlw (%rax), %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x95, 0x14, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlw %xmm0, (%rax, %rcx), %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x68, 0x97, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlq %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0x8f, 0xe9, 0xe8, 0x97, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlq (%rcx), %xmm2, %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x50, 0x97, 0x34, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlq %xmm5, (%rdx, %rcx), %xmm6" + - + input: + bytes: [ 0x8f, 0xe9, 0x40, 0x96, 0xdd ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshld %xmm7, %xmm5, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0xe0, 0x96, 0x58, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshld 4(%rax), %xmm3, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x70, 0x96, 0x2c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshld %xmm1, (%rax, %rcx), %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x70, 0x94, 0xda ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x94, 0x39 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlb (%rcx), %xmm0, %xmm7" + - + input: + bytes: [ 0x8f, 0xe9, 0x68, 0x94, 0x1c, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlb %xmm2, (%rax, %rdx), %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x40, 0x99, 0xdd ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshaw %xmm7, %xmm5, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0xe8, 0x99, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshaw (%rax), %xmm2, %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x99, 0x5c, 0x08, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshaw %xmm0, 8(%rax, %rcx), %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x58, 0x9b, 0xe4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshaq %xmm4, %xmm4, %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0xe8, 0x9b, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshaq (%rcx), %xmm2, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x48, 0x9b, 0x2c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshaq %xmm6, (%rax, %rcx), %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x50, 0x9a, 0xc4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshad %xmm5, %xmm4, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0xe8, 0x9a, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshad (%rax), %xmm2, %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x68, 0x9a, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshad %xmm2, (%rax), %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x70, 0x98, 0xc1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshab %xmm1, %xmm1, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0xd8, 0x98, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshab (%rcx), %xmm4, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x50, 0x98, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshab %xmm5, (%rcx), %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0xe0, 0x91, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotw (%rax), %xmm3, %xmm6" + - + input: + bytes: [ 0x8f, 0xe9, 0x50, 0x91, 0x0c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotw %xmm5, (%rax, %rcx), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x91, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotw %xmm0, %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc1, 0x09, 0x2a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotw $42, (%rcx), %xmm1" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc1, 0x20, 0x29 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotw $41, (%rax), %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc1, 0xd9, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotw $40, %xmm1, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0xf0, 0x93, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotq (%rax), %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0xf0, 0x93, 0x14, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotq (%rax, %rcx), %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x93, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotq %xmm0, %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc3, 0x10, 0x2a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotq $42, (%rax), %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc3, 0x14, 0x08, 0x2a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotq $42, (%rax, %rcx), %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc3, 0xd1, 0x2a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotq $42, %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x92, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotd (%rax), %xmm0, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x68, 0x92, 0x24, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotd %xmm2, (%rax, %rcx), %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x50, 0x92, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotd %xmm5, %xmm3, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc2, 0x31, 0x2b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotd $43, (%rcx), %xmm6" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc2, 0x3c, 0x08, 0x2c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotd $44, (%rax, %rcx), %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc2, 0xe4, 0x2d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotd $45, %xmm4, %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0xe8, 0x90, 0x29 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotb (%rcx), %xmm2, %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x50, 0x90, 0x24, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotb %xmm5, (%rax, %rcx), %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x58, 0x90, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotb %xmm4, %xmm3, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc0, 0x18, 0x2e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotb $46, (%rax), %xmm3" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc0, 0x3c, 0x08, 0x2f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotb $47, (%rax, %rcx), %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc0, 0xed, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotb $48, %xmm5, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xb6, 0xe2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmadcswd %xmm1, %xmm2, %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xb6, 0x20, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmadcswd %xmm1, (%rax), %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0xa6, 0xe4, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmadcsswd %xmm1, %xmm4, %xmm6, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xa6, 0x24, 0x08, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmadcsswd %xmm1, (%rax, %rcx), %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x50, 0x95, 0xe2, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsww %xmm0, %xmm2, %xmm5, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0x95, 0x20, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsww %xmm1, (%rax), %xmm6, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0x96, 0xfd, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacswd %xmm4, %xmm5, %xmm6, %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x70, 0x96, 0x10, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacswd %xmm0, (%rax), %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x68, 0x85, 0xcb, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssww %xmm4, %xmm3, %xmm2, %xmm1" + - + input: + bytes: [ 0x8f, 0xe8, 0x40, 0x85, 0x39, 0x60 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssww %xmm6, (%rcx), %xmm7, %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x58, 0x86, 0xd2, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsswd %xmm4, %xmm2, %xmm4, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x70, 0x86, 0x44, 0x08, 0x08, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsswd %xmm0, 8(%rax, %rcx), %xmm1, %xmm0" + - + input: + bytes: [ 0x8f, 0xe8, 0x68, 0x87, 0xe1, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssdql %xmm1, %xmm1, %xmm2, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0x87, 0x29, 0x70 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssdql %xmm7, (%rcx), %xmm6, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0x8f, 0xca, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssdqh %xmm3, %xmm2, %xmm0, %xmm1" + - + input: + bytes: [ 0x8f, 0xe8, 0x68, 0x8f, 0x1c, 0x08, 0x70 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssdqh %xmm7, (%rax, %rcx), %xmm2, %xmm3" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0x8e, 0xea, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssdd %xmm2, %xmm2, %xmm3, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x70, 0x8e, 0x10, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssdd %xmm4, (%rax), %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0x97, 0xf8, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsdql %xmm3, %xmm0, %xmm6, %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0x97, 0x69, 0x08, 0x50 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsdql %xmm5, 8(%rcx), %xmm3, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0x9f, 0xd5, 0x70 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsdqh %xmm7, %xmm5, %xmm3, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x68, 0x9f, 0x40, 0x04, 0x50 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsdqh %xmm5, 4(%rax), %xmm2, %xmm0" + - + input: + bytes: [ 0x8f, 0xe8, 0x58, 0x9e, 0xd6, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsdd %xmm4, %xmm6, %xmm4, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x58, 0x9e, 0x1c, 0x08, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsdd %xmm4, (%rax, %rcx), %xmm4, %xmm3" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xcd, 0xe2, 0x2a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomw $42, %xmm2, %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xcd, 0x20, 0x2a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomw $42, (%rax), %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xed, 0xe9, 0x2b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomuw $43, %xmm1, %xmm3, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xed, 0x34, 0x08, 0x2c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomuw $44, (%rax, %rcx), %xmm0, %xmm6" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xef, 0xfb, 0x2d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomuq $45, %xmm3, %xmm3, %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xef, 0x08, 0x2e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomuq $46, (%rax), %xmm3, %xmm1" + - + input: + bytes: [ 0x8f, 0xe8, 0x70, 0xee, 0xd0, 0x2f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomud $47, %xmm0, %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0xee, 0x58, 0x04, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomud $48, 4(%rax), %xmm6, %xmm3" + - + input: + bytes: [ 0x8f, 0xe8, 0x58, 0xec, 0xeb, 0x31 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomub $49, %xmm3, %xmm4, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0xec, 0x11, 0x32 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomub $50, (%rcx), %xmm6, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xcf, 0xeb, 0x33 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomq $51, %xmm3, %xmm0, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x70, 0xcf, 0x38, 0x34 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomq $52, (%rax), %xmm1, %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xce, 0xc3, 0x35 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomd $53, %xmm3, %xmm3, %xmm0" + - + input: + bytes: [ 0x8f, 0xe8, 0x68, 0xce, 0x11, 0x36 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomd $54, (%rcx), %xmm2, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x58, 0xcc, 0xd6, 0x37 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomb $55, %xmm6, %xmm4, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xcc, 0x50, 0x08, 0x38 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomb $56, 8(%rax), %xmm3, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xa3, 0xe2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpperm %xmm1, %xmm2, %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0xe0, 0xa3, 0x20, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpperm (%rax), %xmm2, %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xa3, 0x20, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpperm %xmm1, (%rax), %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xa2, 0xe2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmov %xmm1, %xmm2, %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0xe0, 0xa2, 0x20, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmov (%rax), %xmm2, %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xa2, 0x20, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmov %xmm1, (%rax), %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x64, 0xa2, 0xe2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmov %ymm1, %ymm2, %ymm3, %ymm4" + - + input: + bytes: [ 0x8f, 0xe8, 0xe4, 0xa2, 0x20, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmov (%rax), %ymm2, %ymm3, %ymm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x64, 0xa2, 0x20, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmov %ymm1, (%rax), %ymm3, %ymm4" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x49, 0xfa, 0x51 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $1, %xmm5, %xmm2, %xmm1, %xmm7" + - + input: + bytes: [ 0xc4, 0xe3, 0xe1, 0x49, 0x20, 0x32 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $2, (%rax), %xmm3, %xmm3, %xmm4" + - + input: + bytes: [ 0xc4, 0xe3, 0xdd, 0x49, 0x70, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $3, 8(%rax), %ymm0, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x49, 0x04, 0x08, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $0, %xmm3, (%rax, %rcx), %xmm1, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x65, 0x49, 0xe2, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $1, %ymm1, %ymm2, %ymm3, %ymm4" + - + input: + bytes: [ 0xc4, 0xe3, 0x65, 0x49, 0x20, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $2, %ymm1, (%rax), %ymm3, %ymm4" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x48, 0xcb, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2ps $0, %xmm4, %xmm3, %xmm2, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0xe1, 0x48, 0x40, 0x04, 0x21 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xd5, 0x48, 0x30, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2ps $2, (%rax), %ymm1, %ymm5, %ymm6" + - + input: + bytes: [ 0xc4, 0xe3, 0x61, 0x48, 0x20, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2ps $3, %xmm1, (%rax), %xmm3, %xmm4" + - + input: + bytes: [ 0xc4, 0xe3, 0x6d, 0x48, 0xd4, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2ps $0, %ymm4, %ymm4, %ymm2, %ymm2" + - + input: + bytes: [ 0xc4, 0xe3, 0x75, 0x49, 0x40, 0x04, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $1, %ymm1, 4(%rax), %ymm1, %ymm0"